Patent ID: 12200860

DETAILED DESCRIPTION

The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines include a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. The first set of data lines may also include a third subset of point-to-point data lines coupled between the memory controller and a third socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The second set of data lines may also include a fourth subset of data lines coupled between the first socket and the second socket and a fifth subset of data lines coupled between the first socket and the third socket. The first and second sets of data lines can make up a memory channel and the memory channel can be a one socket per channel (SPC) memory channel, a 2-SPC memory channel, or a 3-SPC channel when there are three module sockets. Module sockets are also described herein as slots of a motherboard substrate. Thus, sockets and slots are used interchangeably in the description. Also, nibbles as used herein may include four wires of data signals (with one bit on each wire during each bit interval) and two wires of timing signals (with a differential timing event per bit interval). Various embodiments are directed to DIMMS that are greater than 64-bits, such as 72-bit wide DIMMs that support ECC, such as used in server memory systems.

Description of various embodiments herein are described with respect to memory systems with up to three R+DDR4 LRDIMMs that can be operated at 3 DIMMs per channel (DPC) at 3.2 Gb/s using Dynamic Point-Point (DPP) as described herein. Some embodiments do not require change to DRAM devices themselves and a central processing unit (CPU), but may include changes in a module interface and buffer components of the module and changes to a motherboard. The R+DDR4 LRDIMMs described herein are compatible with the DDR4 LRDIMM standard. The R+DDR4 LRDIMMs support various error correction coding (ECC) techniques, including single error correcting and, simultaneously, double error detecting (SEC-DED), as well as the ChipKill™ ECC computer memory technology or other advanced ECC computer memory technologies. The embodiments of R+DDR4 LRDIMMs described herein do not need dynamic on-die termination (ODT) and may have the same or lower power than standard LRDIMMs. The embodiments of R+LRDIMM architecture, as described herein, may be scale to beyond-DDR4 data rates, e.g., up to 6.4 Gb/s in one embodiment. The embodiments described herein can be used in a memory system where a primary bus can be run at a higher rate and may only be limited by the speed of transfers.

Embodiments of a motherboard are also described herein. In some embodiments, the motherboard can enable 3 DPC at maximum data rates. The R+DDR4 LRDIMMs can also be used in standard motherboards and behave like standard LRDIMMs in those implementation. In other embodiment where interoperability with standard motherboards is not needed, then R+LRDIMMs can be developed with lower cost than standard LRDIMM as described in more detail below.

Embodiments of memory modules can also be inserted in sockets of a memory system in different configurations. The R+LRDIMMs may be built from standard memory components. Standard memory controller components (with minimal modifications) and new memory modules may be used in standard memory systems or in new LRDIMM memory systems. The minimal modifications may be that the memory controllers are configured to send appropriate control information given the different configurations. The embodiments of R+DDR4 LRDIMMs are described as being deployed using DPP. DPP ensures that all data (DQ) nets in a memory channel are always point-to-point, irrespective of the memory configuration (e.g., 1-SPC, 2-SPC, or 3-SPC). Eliminating the multi-drop topology of DQ nets may reduce reflections and other inter-symbol-interference (ISI) effects, thus allowing higher data rates. In some memory configurations, DPP uses one or more continuity DIMMs (CDIMMs). A CDIMM is a printed circuit board (PCB) (e.g., a FR-4 board) with no active or passive components and includes traces that short one set of DQ pins to another set of DQ pins.

FIGS.1A-1Bare diagrams illustrating 2-SPC memory channel wirings for a 1 DPC memory configuration100and a 2 DPC memory configuration150, respectively.

FIG.1Ais a diagram illustrating 2-SPC memory channel wiring with 1 R+LRDIMM in a 1 DPC memory configuration100according to one embodiment. In the 1 DPC memory configuration100, a first slot102is populated with a continuity module (C-DIMM)106and a second slot104is populated with a R+LRDIMM108.FIG.1Aillustrates an 8-bit slice of a 72-bit wide DIMM architecture, including a first nibble received by the R+LRDIMM108at the second slot104on data lines110and a second nibble received by the C-DIMM106at the first slot102on data lines120and routed to the R+LRDIMM108at the second slot104on data lines130.

FIG.1Bis a diagram illustrating 2-SPC memory channel wiring with 2 R+LRDIMMs in a 2 DPC memory configuration150according to one embodiment. The 2-SPC memory channel wiring is similar in the 1 DPC memory configuration100is similar to the 2-SPC memory channel wiring in the 2 DPC memory configuration150as noted by similar reference labels. In the 2 DPC memory configuration150, the first slot102is populated with a first R+LRDIMM108and the second slot104is populated with a second R+LRDIMM108. Since both the first slot102and the second slot104are populated with R+LDIMMs108, the data lines130are not used and the first nibble is received by the second R+LRDIMM108at the second slot104on data lines110and the second nibble is received by the first R+LRDIMM108at the first slot102on data lines120. Although one 8-bit slice of the 72-bit wide DIMM is illustrated inFIGS.1A-1B, the other slices of the 72-bit wide DIMM architecture may be identical. It should also be noted that the embodiments above describe receiving nibbles at the C-DIMM106and R+LRDIMM108, but it would be understood that the nibbles can also be sent by the LRDIMM108to a memory controller on the data lines, some of which would pass through the C-DIMM106.

FIGS.2A-2Care diagrams illustrating 3-SPC memory channel wirings for a 1 DPC memory configuration200, a 2 DPC memory configuration250, and a 3 DPC memory configuration260, respectively.

FIG.2Ais a diagram illustrating 3-SPC memory channel wiring with 1 R+LRDIMM in a 1 DPC memory configuration200according to one embodiment. In the 1 DPC memory configuration200, a first slot202is populated with a first C-DIMM206, a second slot203is populated with a second C-DIMM206, and a third slot204is populated with a R+LRDIMM208.FIG.2Aillustrates an 24-bit slice of a 72-bit wide DIMM architecture, including: 1) a first nibble received by the R+LRDIMM108at the third slot204on data lines210; 2) a second nibble received by the second C-DIMM206at the second slot203on data lines212and routed to the R+LRDIMM208at the third slot204on data lines222, 3) a third nibble received by the first C-DIMM206at the first slot202on data lines214, routed to the second C-DIMM206at the second slot203on data lines224, and routed to the R+LRDIMM208at the third slot204on data lines226; 4) a fourth nibble received by the first C-DIMM206at the first slot202on data lines216and routed to the R+LRDIMM208at the third slot204on data lines228; 5) a fifth nibble received by the second C-DIMM206at the second slot203on data lines218and routed to the R+LRDIMM208at the third slot204on data lines230; and 6) a sixth nibble received by the R+LRDIMM208at the third slot204on data lines220.

FIG.2Bis a diagram illustrating 3-SPC memory channel wiring with 2 R+LRDIMMs in a 2 DPC memory configuration250according to one embodiment. The 3-SPC memory channel wiring in the 1 DPC memory configuration200is similar to the 3-SPC memory channel wiring in the 2 DPC memory configuration250as noted by similar reference labels. In the 2 DPC memory configuration250, the first slot202is populated with a C-DIMM206, the second slot203is populated with a first R+LRDIMM208and the third slot1204is populated with a second R+LRDIMM208. Since both the second slot203and the third slot204are populated with R+LDIMMs208, the data lines222,226and230are not used, but the data lines224and228are still used since the first slot202is populated with the C-DIMM206.

FIG.2Cis a diagram illustrating 3-SPC memory channel wiring with 3 R+LRDIMMs in a 3 DPC memory configuration260according to one embodiment. The 3-SPC memory channel wiring in the 1 DPC memory configuration250is similar to the 3-SPC memory channel wiring in the 2 DPC memory configuration260as noted by similar reference labels. In the 2 DPC memory configuration260, the first slot202is populated with a first R+LRDIMM208, the second slot203is populated with a second R+LRDIMM208and the third slot1204is populated with a third R+LRDIMM208. Since the first slot202, second slot203, and third slot204are populated with R+LDIMMs208, the data lines222,224,226,228and230are not used. Although one 24-bit slice of the 72-bit wide DIMM is illustrated inFIGS.2A-2C, the other slices of the 72-bit wide DIMM architecture may be identical. It should also be noted that the embodiments above describe receiving nibbles at the C-DIMM206and R+LRDIMM208, but it would be understood that the nibbles can also be sent by the LRDIMM208to a memory controller on the data lines, some of which would pass through the C-DIMM206.

FIG.3is a diagram illustrating 2-SPC memory channel wiring300with a CPU slot301and two DIMM slots302,304for R+LRDIMMs coupled to the CPU slot301with data lines according to even and odd nibbles according to one embodiment. A first set of data lines306, corresponding to even nibbles, are connected to the DIMM slots302,304and the CPU slot301. A second set of data lines308, corresponding to odd nibbles, are connected between the two DIMM slots302,304. That is odd nibbles of one DIMM slot is coupled to odd nibbles of the other DIMM slot. The first and second sets of data lines306,308can accommodate 9 even nibbles and 9 odd nibbles for a 72-bit wide DIMM in 1 DPC or 2 DPC memory configurations, as described below with respect toFIGS.4A-4B.

FIG.4Ais a diagram illustrating 2-SPC DDR4 channel400with one DIMM slot populated with one R+LRDIMM408and another DIMM slot populated with a continuity DIMM (C-DIMM)406according to one embodiment. The R+LRDIMM408includes eighteen device sites, where each site may be a single memory component or multiple memory components. For case of description, the data lines of two devices sites412,414in the 2-SPC DDR4 channel400are described. A first device site412is coupled to the CPU401via data lines416(even nibble). A second device site414is coupled to the C-DIMM406via data lines418(odd nibble of R+LRDIMM to odd nibble of C-DIMM). The C-DIMM406use internal traces420to couple the data lines418to data lines422, which are coupled to the CPU401(odd nibble).

InFIG.4A, a DQ buffer component430is coupled between the first device site412and second device site414and the data lines416and418, respectively. The DQ buffer component430acts as a repeater with one R+LRDIMM408in the 2-SPC DDR4 channel400. It should be noted that C1[2:0] is qualified by CS1# (not illustrated inFIG.4A) and C0[2:0] is qualified by CS0# (not illustrated inFIG.4B).

FIG.4Bis a diagram illustrating 2-SPC DDR4 channel450with one DIMM slot populated with one R+LRDIMM408and another DIMM slot populated with another one R+LRDIMM408according to one embodiment. The 2-SPC DDR4 channel450is similar to the 2-SPC DDR channel400as noted by similar reference labels. However, the other slot is populated with a second R+LRDIMM458. The R+LRDIMM458includes eighteen device sites, where each site may be a single memory component or multiple memory components. For case of description, the data lines of two devices sites412,452in the 2-SPC DDR4 channel450are described. A first device site412is coupled to the CPU401via data lines416(even nibble) as described above with respect to 2-SPC DDR4 channel400. A second device site452is coupled to the CPU401via data lines422(even nibble). In effect, location of the second device site414of the 2-SPC DDR4 channel400is swapped with the first device site452of 2-SPC DDR4 channel450when both slots are populated with R+LRDIMMs408,458. It should be noted that the electrical connections for data lines418and internal data lines to the DQ buffer components are present on the motherboard and R+LDIMMs, but are not used.

InFIG.4B, the DQ buffer component430acts as a multiplexer (MUX) with two R+LRDIMMs408,458in the 2-SPC DDR4 channel450. It should be noted that C1[2:0] is qualified by CS1# (not illustrated inFIG.4A) and C0[2:0] is qualified by CS0# (not illustrated inFIG.4B).

FIG.5is a diagram illustrating 3-SPC memory channel wiring500with a CPU slot501and three DIMM slots502-504for R+LRDIMMs coupled to the CPU slot501with data lines according to sets of nibbles according to one embodiment. A first set of data lines506of the three DIMM slot502-504are connected to CPU slot501. A second set of data lines508are connected between the second and third DIMM slots503-504. A third set of data lines510are connected between the first and third DIMM slots502,504. A fourth set of data lines512are connected between the first and second DIMM slots502,503. The data lines for only one 24-bit wide slice are labeled, but the first, second, third, and fourth sets of data lines can accommodate eighteen nibbles for 1 DPC, 2 DPC, and 3 DPC memory configurations, as described below with respect toFIGS.6A-6C.

FIG.6Ais a diagram illustrating 3-SPC DDR4 channel600with one DIMM slot populated with one R+LRDIMM608and two DIMM slots populated with C-DIMMs606according to one embodiment. A 24-bit slice of a 72-bit wide DIMM is illustrated, but other slices are wired identically. The slice of R+LRDIMM408includes six device sites, where each site may be a single memory component or multiple memory components. For case of description, the data lines of three devices sites612,614,616in the 3-SPC DDR4 channel600are described. A first device site612is coupled to the CPU601via data lines617(first nibble). A second device site614is coupled to the second C-DIMM606in the second slot via data lines618, and the inner traces620of second C-DIMM606connect data lines618to data lines622, which are coupled to the CPU601(second nibble). A third device site616is coupled to the first C-DIMM606in the first slot via data lines624, and the inner traces626of first C-DIMM606connect data lines624to data lines624, which are coupled to the CPU601(third nibble). Similar data lines can be used to connect the other device sites of the R+LRDIMM608to the CPU601for the other three nibbles in the slice. The DQ buffer component632, with or without DQ buffer component631, can be used for the other device sites of the R+LRDIMM608.

InFIG.6A, a DQ buffer component630is coupled between the first device site612and second device site614and the data lines617and618, respectively. A second DQ buffer component631is coupled between the third device site616and data lines624. In another embodiment, the DQ buffer component630is coupled to the three device sites612-616and the third device site616is coupled to the DQ buffer component630via data lines641. Electrical connections may be presented for data lines640between the first and second C-DIMMS606, but may be unused. Similarly, electrical connections may be presented for the data lines641, but may be unused in some embodiments. The DQ buffer component630acts as a repeater with one R+LRDIMM608in the 3-SPC DDR4 channel600. The DQ buffer component630could also act as multiplexer in some cases. It should be noted that C2[2:0], C1[2:0] and C0[2:0] are qualified by CS2#, CS1#, and CS0#, respectively (not illustrated inFIG.6A).

FIG.6Bis a diagram illustrating 3-SPC DDR4 channel650with two DIMM slots populated with R+LRDIMMs608,658and another DIMM slot populated with a C-DIMM606according to one embodiment. The 3-SPC DDR4 channel650is similar to the 3-SPC DDR channel600as noted by similar reference labels. However, the second slot is populated with a second R+LRDIMM658. The corresponding slice of the R+LRDIMM658includes six device sites, where each site may be a single memory component or multiple memory components. For case of description, the data lines of three devices sites612-616in the 3-SPC DDR4 channel650are described. A first device site612is coupled to the CPU401via data lines617(first nibble) as described above with respect to 3-SPC DDR4 channel600. A second device site652is coupled to the CPU401via data lines622(second nibble). A third device site616is coupled to the CPU via data lines624, which are coupled to the first slot with the C-DIMM606. The internal traces of the C-DIMM606connect the data lines624to the data lines628(third nibble). In effect, location of the second device site614of the 3-SPC DDR4 channel600is swapped with the first device site452of 3-SPC DDR4 channel650when both slots are populated with R+LRDIMMs608,658. It should be noted that the electrical connections for data lines618and internal data lines to the DQ buffer components are present on the motherboard and R+LDIMMs, but are not used. Similar data lines can be used to connect the other device sites of the two R+LRDIMMs608,658to the CPU601for the other three nibbles in the slice. The DQ buffer components630-632and DQ buffer components670-672may be used for the device sites of the two R+LRDIMMs608,658. In some cases, the DQ buffer components may act as repeaters or multiplexers as described herein. It should be noted that C2[2:0], C1[2:0] and C0[2:0] are qualified by CS2#, CS1#, and CS0#, respectively (not illustrated inFIG.6B).

FIG.6Cis a diagram illustrating 3-SPC DDR4 channel670with three DIMM slots populated with R+LRDIMMs608,658,678according to one embodiment. The 3-SPC DDR4 channel670is similar to the 3-SPC DDR channel650as noted by similar reference labels. However, the first slot is populated with a third R+LRDIMM678. The corresponding slice of the R+LRDIMM678includes six device sites, where each site may be a single memory component or multiple memory components. For case of description, the data lines of three devices sites612,652,672in the 3-SPC DDR4 channel670are described. A first device site612is coupled to the CPU401via data lines617(first nibble) as described above with respect to 3-SPC DDR4 channel600. A second device site652is coupled to the CPU401via data lines622(second nibble). A third device site672is coupled to the CPU401via data lines628(third nibble). It should be noted that the electrical connections for data lines618,624and internal data lines to the DQ buffer components are present on the motherboard and R+LDIMMs, but are not used. Similar data lines can be used to connect the other device sites of the three R+LRDIMMs608,658,678to the CPU601for the other three nibbles in the slice. The DQ buffer components630-632, DQ buffer components670-672, and DQ buffer components680-682may be used for the device sites of the three R+LRDIMMs608,658,678. In some cases, the DQ buffer components may act as repeaters or multiplexers as described herein. It should be noted that C2[2:0], C1[2:0] and C0[2:0] are qualified by CS2#, CS1#, and CS0#, respectively (not illustrated inFIG.6C).

In some implementations, DDR4 R+LRDIMM requires that all CS # and CKE signals in a memory channel be broadcast to all the DIMM slots (or DIMM sockets or module sockets) in the channel. With DPP, each data signal is connected to only one R+LRDIMM. In a channel with multiple R+LRDIMMs, each and every R+LRDIMM respond s to a Read or Write operation. The DDR4 specification allows up to 8 ranks per DIMM slot. In one implementation, for single rank (SR) DIMM, rank 0 is controlled by CS0#, CKE0, and ODT0, for double-rank (DR) DIMM, rank 1 is controlled by CS1#, CKE1, and ODT1, and for quad-rank (QR) DIMM or octa-rank (OR) DIMM, rank is controlled by C[2:0], CS #, CKE, and ODT. The CS # signal may be a 1-cycle signal and is connected to only one DIMM slot, and broadcasting CS # to all DIMM slots may violate register setup and hold times. The embodiments described below create a private shared bus between the DIMM slots in a memory channel using pins defined as not connected (NC) or non-functional (NF) in the DDR4 RDIMM specification. ODT pins in each DIMM slot may optionally be used for the private bus since all DQ nets are always point-to-point. CA buffer components (also referred to as CA register) may be modified for operation with a local CS signal (local CS #) and clock enabled (CKE) signals and a distant CS signal (distant CS #) and CKE signals. Local CS signals are signals received directly from the memory controller (MC) and distant signals are signals from another DIMM connector on the private bus. The CA buffer component treats local CS signals different than distant CS signals. For example, in one embodiment, local signals go through two flip-flops before being driven to the DRAM devices, whereas distant signals go through 1 flip-flop before being driven to the DRAM devices.

FIG.7is a diagram illustrating a private bus750between three DIMM slots702-704of a 3-SPC memory system700according to one embodiment. In the memory system700, a memory controller (MC)701is coupled to three slots702-704. A first set of control lines712is coupled between the MC701and a first slot702(slot 0) (e.g., CS0#[2:0], CKE0, and ODT0). A second set of control lines713is coupled between the MC701and a second slot703(slot1) (e.g., CS1#[2:0], CKE1, and ODT1). A third set of control lines714is coupled between the MC701and a third slot704(slot2) (e.g., CS2#[2:0], CKE2, and ODT2). For a SR DIMM configuration, rank 0 is controlled by CS0#, CKE0, and ODT0. For a DR DIMM configuration, rank 0 is controlled by CS0#, CKE0, and ODT0and rank 1 is controlled by CS1#, CKE1, and ODT1. For a QR DIMM configuration or OR DIMM configuration, ranks are controlled by C[2:0], CS #, CKE, and ODT. C[2:0] may be 3 encoded CS signals with each one of CS0# or CS1#. C[2:0] may be used to control up to 8 ranks (e.g., stacked devices). For stacked technology devices, also referred to as 3DS technology, there may be 18 device sites and three C bits can be used to select devices at the selected device site. The CS # signal may be a 1-cycle signal and is connected to only one DIMM slot.

In one embodiment, the R+LRDIMMs at the three slots702-704receive three signals each and the R+LRDIMMs retransmit the signals to the other two slots on the private bus750. The private bus750includes a first data line722for CKE_COPY, a second data line723for CS #_COPY, and a third set of data lines724for SLOT_ID[1:0] and C[2:0]_COPY. The SLOT_ID[1:0] can be used to identify which of the three slots702-704is retransmitting the CS information. C[2:0]_COPY is a copy of the CS[2:0] received by the respective slot. Similarly, CKE_COPY is a copy of the CKE received by the respective slot and CS #_COPY is a copy of the CS # received by the respective slot. The private bus750may use wired-OR pins with a pull-up on a motherboard upon which the three slots702-704are disposed.

In one embodiment, the following NC pins are available to use for the private bus750:92,202,224,227,232and234. In another embodiment, the following NF pins may be used:88,90,200,215, and216. These NC and NF pins may be in the vicinity of the CA pins.

FIG.8is a diagram illustrating local control signals801and distant control signals803of a private bus823between two DIMM slots802,804of a memory system800according to one embodiment. A first DIMM slot802(slot 0) is populated with a first memory module with a CA buffer component840and a second DIMM slot804(slot 1) is populated with second memory module with a CA buffer component850. The first memory module in the first DIMM slot802includes multiple device sites860and the second memory module in the second DIMM slot804includes multiple device sites870. The device sites860,870may each include a single memory component or each multiple memory components. These memory components may be DDR4 DRAM devices and the memory modules may be R+LRDIMMs. It should be noted thatFIG.8illustrates two single-rank LRDIMMs for sake of clarity, but similar data lines can be connected to other devices sites860and870.

The CA buffer component840includes a primary interface with a first pin805, which is coupled to data line812to receive a local chip select (CS) signal (CS0#)801, and a second pin807, which is coupled to a data line of the private bus823to receive a distant CS signal (CS_COPY #)803. The primary interface is coupled to the CPU801. The CA buffer component840includes a secondary interface to select one or more of the device sites860(e.g.,862,864,866,868). The CA buffer component840selects the device sites862,864when the local CS signal801is received on the first pin805(for slot 0) and selects the device sites866,868when the distant CS signal803is received on the second pin807(for slot 0). In other embodiments where there are additional slots, the CA buffer component840receives a second distant CS signal on a third pin (not illustrated) to select other device sites.

In a further embodiment, the CA buffer component840includes: 1) a first flip-flop842coupled to the first pin805; 2) a second flip-flop844coupled to an output of the first flip-flop842. An output of the second flip-flop844is coupled to the device sites862,864. The CA buffer component840also includes an input buffer843coupled to the second pin807and an output of the input buffer843is coupled to a third flip-flop846. An output of the third flip-flop846is coupled to the device sites866,868. The first flip-flop842, second flip-flop844, and third flip-flop846are clocked by a timing signal847. The timing signal847can be generated by a phase locked loop (PLL)845, which is coupled to a fourth pin809that receive a clock signal (CLK0) on data line814from the CPU801. The CA buffer component840also includes an output buffer841coupled to the output of the first flip-flop842. An output of the output buffer841is coupled to the second pin807. The output buffer841generates a second distant CS signal (e.g., CS_COPY #) on second pin807. The output buffer841retransmits the local CS signal801received on the first pin805as the distant CS signal803on the second pin807to one or more other modules in other slots (e.g., second slot804).

The CA buffer component850may also include similar primary and secondary interfaces as the CA buffer component840. The primary interface couples to the CPU801and the secondary interface is to select one or more of the device sites870(e.g.,872,874,876,878). The CA buffer component850selects the device sites872,874when the local CS signal (CS1#) is received on a first pin811(for slot 1) from data line813coupled to the CPU801. The CA buffer component850selects the device sites876,878when the distant CS signal (CS_COPY #) is received on the second pin807(for slot 1) from the data line of the private bus823coupled to the first slot802. The CA buffer component850includes: 1) a first flip-flop852coupled to the first pin811; 2) a second flip-flop854coupled to an output of the first flip-flop852. An output of the second flip-flop854is coupled to the device sites872,874. The CA buffer component850also includes an input buffer853coupled to the second pin807and an output of the input buffer853is coupled to a third flip-flop856. An output of the third flip-flop856is coupled to the device sites876,878. The first flip-flop852, second flip-flop854, and third flip-flop856are clocked by a timing signal857. The timing signal857can be generated by a PLL855, which is coupled to a fourth pin809that receives a clock signal (CLK1) on data line815from the CPU801. The CA buffer component850also includes an output buffer851coupled to the output of the first flip-flop852. An output of the output buffer851is coupled to the second pin807. The output buffer851generates a second distant CS signal (e.g., CS_COPY #) on second pin807. The output buffer841retransmits the local CS signal received on the first pin811as the distant CS signal on the second pin807to one or more other modules in other slots (e.g., first slot802).

AlthoughFIG.8illustrates two DIMM slots802,804and only four device sites per DIMM slot, in other embodiments, more than two DIMM slots can be used and more than four device sites per DIMM slot may be used.FIG.8also illustrates single-device memory sites, but in other embodiments, multi-device memory sites may be used, such as illustrated inFIG.9.

FIG.9is a diagram illustrating a CA buffer component900according to one embodiment. The CA buffer component900includes a first flip-flop902that receives a local CS signal (CS0#) on a first pin905. An output of the first flip-flop902is coupled to an output driver932to generate a distant CS signal (CS #_COPY) on a second pin907. A distant CS signal can also be received on second pin907and an input buffer934directs the distant CS signal to a multiplexer903, which also receives the output of the first flip-flop902. An output of the multiplexer903is coupled to a second flip-flop904. An output of the second flip-flop904is input into CS generation logic930. The CS generation logic930also receives input from a DPC counter928and signals received on the pins915through an input buffer924(e.g., CHIP_ID[1:0], C[2:0]_COPY). The CS generation logic930generates CS signals on pins919(e.g., Q_CS[n:0]#). A PLL945receives a clock signal (CK, CK #) on pin909and generates a timing signal used to clock the first flip-flop902and the second flip-flop904. The timing signal is also output on pin921(e.g., Q_CK, Q_CK #). CS logic926receives an output of the first flip-flop902and a SLOT ID from SLOT ID register920. An output of the CS logic926enables fourth flip-flops908that output signals on pins917(e.g., Q_C[2:0]), sixth flip-flops912that output signals on pins925(e.g., Q_ODT0, Q_CKE0), and eighth flip-flop916that output signals on pins929(e.g., QA[n:0], QBA[1:0], QBG[1:0], Q_RAS #, Q_CAS #, Q_WE #). The fourth flip-flop908, sixth flip-flop912and eighth flip-flop916receives outputs from third flip-flop906, fifth flip-flop910, and seventh flip-flop914. These flip-flops are also clocked by the timing signal generated by the PLL945. The third flip-flop906receive signals C[2:0] on pins913. The fifth flip-flops910receive signals a clock signal enable signal (CKE0) and ODT signal (ODT0) on pins923. The seventh flip-flops914receive signals (e.g., A[n:0], BA[1:0], BG[1:0], RAS #, CAS #, WE #) on pins927. An output of the third flip-flop906is coupled to a multiplexer999, which also receives signals received on the pins915through the input buffer924(e.g., CHIP_ID[1:0], C[2:0]_COPY). An output of the multiplexer999is coupled to an input of the fourth flip-flop908. An output of the fifth flip-flop910is coupled to an output buffer918to drive copies of the clock enable signal and ODT signal on pins911(e.g., CKE_COPY). An output of the third flip-flop906is coupled to an output buffer922to drive copes of the signals on pins915(e.g., CHIP_ID[1:0], C[2:0]_COPY).

In some implementations, some logic blocks can be bypassed when the CA buffer component900is operating as a standard DDR4 CA buffer component. The bypass path is not illustrated inFIG.9. It should be noted that clock enable logic (CKE0logic) is similar to the CS logic for CS0# logic, but is not shown for sake of clarity. In a further embodiment, the CA buffer component900sends configuration information and multiplexer control signals to DQ buffers on existing sideband signals as described herein.

FIG.10is a diagram illustrating a data (DQ) buffer component1000according to one embodiment. The DQ buffer component1000includes a multiplexer1002, control logic1004and a synchronizer1006. The multiplexer1002is coupled to multiple input ports: IN_PORTA, IN_PORTB, and IN_PORTC. The multiplexer1002receives a first nibble, including data signals S_DQ[3:0] and timing signals S_DQS0and S_DQS0#. It should be noted that nibble, as used herein, refers to the data signals and the corresponding timing signals, and thus, is 6-bits. The multiplexer1002receives a second nibble, including data signals S_DQ[7:4] and timing signals S_DQS1and S_DQS1#. In a further embodiment, the multiplexer1002receives a third nibble, including S_DQ[11:9] and timing signals S_DQS2and S_DQS2#. The third port can be used for 3 SPC configurations, but these pins may not be needed for 2 SPC configurations. It should be noted that the multiplexer1002is a bi-directional multiplexer, such as a 3:1 mux and 1:3 demux.

As described above, sideband signals1001can be generated by the CA buffer component900ofFIG.9. Control logic1004receives the sideband signals1001to control the multiplexer1002and the synchronizer1006. The synchronizer1006synchronizes the data to be output on first and second ports (OUT_PORTA, OUT_PORTB). For example, the synchronizer1006can output data signals (e.g., P_DQ[3:0]) and timing signals1011(e.g., P_DQS0and P_DQS0#) on first port and can output data signals (e.g., P_DQ[7:4]) and timing signals1013(e.g., P_DQS1and P_CDQ1#) on the second port.

FIG.11is a diagram illustrating data flow in a 2-SPC system1100when populated with one R+LRDIMM in a 1 DPC configuration1110and when populated with two R+LRDIMMs in a 2 DPC configuration1120according to one embodiment. The 2-SPC system1100includes a first slot1102(slot 0) and a second slot1104(slot 1). An 8-bit slice of a 72-bit wide DIMM is illustrated inFIG.11, but the other slices are identical. A first set of data lines1003is disposed on a motherboard substrate and coupled to the first slot1102and second slot1104and a memory controller (not illustrated). The first set1103of data lines includes point-to-point data lines, each point-to-point data line of the first set1103is coupled to the memory controller and either one of the slots, but not both slots (also referred to herein as module sockets). The first set1103of data lines is greater than 64 data lines. The first set1103of data lines may be 72 bits to support ECC as described herein. A second set1105of data lines is disposed on the motherboard substrate and coupled between the first slot1102and second slot1104. The CS signals1117are received at the first slot1102and second slot1104.

In the 1 DPC configuration1110, the first slot1102is populated with a C-DIMM1106and the second slot1104is populated with a R+LRDIMM1108. Data flows to and from a first memory site1112of the R+LRDIMM1108along a first data path1107(first nibble) and data flows to and from a second memory site1114of the R+LRDIMM1108along a second path1109through the C-DIMM1106(second nibble). As described herein, the first and second nibbles may include 4-bits of data signals and two timing/clock signals.

In the 2 DPC configuration1120, the first slot1102is populated with a first R+LRDIMM1108and the second slot1104is populated with a second R+LRDIMM1108. Data flows to and from a first memory site1112of the second R+LRDIMM1108along a first data path1111(first nibble) and data flows to and from a first memory site1122of the first R+LRDIMM1108along a second path1113. In this 2 DPC configuration, the second set of data lines1105are not used and are considered inactive. As described herein, the first and second nibbles may include 4-bits of data signals and two timing/clock signals.

FIG.12is a diagram illustrating chip select (CS) generation in a 2-SPC system1200when populated with one R+LRDIMM in a 1 DPC configuration1210and when populated with two R+LRDIMMs in a 2 DPC configuration1220according to one embodiment. In the 1 DPC configuration1210, a first slot is populated with a C-DIMM1206and a second slot is populated with a R+LRDIMM1208. The R+LRDIMM1208includes a DQ buffer component1230and CA buffer component1240. The CA buffer component1240receives CS information on a primary interface and sends CS information on a secondary interface to select one of the device sites1212,1214. In this configuration, two DRAMS are mapped to a single rank. Alternatively, other configurations may be used.

In the 2 DPC configuration1220, the first slot is populated with a second R+LRDIMM1228and the second slot is populated with a first R+LRDIMM1208. The first R+LRDIMM1208includes the DQ buffer component1230and CA buffer component1240. The second R+LRDIMM1228includes a DQ buffer component1250and CA buffer component1260. The CA buffer components1240,1260receive CS information on respective primary interfaces and send CS information on respective secondary interfaces to select the device sites1212,1214and1218,1222, respectively. In this configuration, two DRAMS are mapped to two different ranks (CS #1, CS0#). Alternatively, other configurations may be used. It should also be noted thatFIG.12illustrates one 8-bit slice of a 72-bit wide DIMM, but other slices are identical.

FIG.13is a diagram illustrating CS generation in a 3-SPC system when populated with one R+LRDIMM in a 1 DPC configuration1310, when populated with two R+LRDIMMs in a 2 DPC configuration1320, and when populated with three R+LRDIMMs in a 3 DPC configuration1330according to one embodiment.FIG.13illustrates only one R+LRDIMM1308in the 1 DPC, 2 DPC, and 3 DPC configurations1310,1320,1330. The R+LRDIMM1308includes a CA buffer component1340and three DQ buffer components1350in the 1 DPC and 2 DPC configurations1310,1320. The R+LRDIMM1308includes a CA buffer component1340and two DQ buffer components1350in the 3 DPC configuration1330. In 1 DPC configuration1310six DRAM devices are mapped to a single rank. In 2 DPC configuration1320six DRAM devices1312are mapped to two ranks (CS2# & CS1#). In 3 DPC configuration1330six DRAM devices are mapped to three ranks (CS2#, CS1#, and CS0#) rank. Alternatively, the device sites of the six DRAM devices1312can be device sites with multiple DRAM devices such as in stacked technologies.

The CA buffer component1240receives CS information on a primary interface and sends CS information on a secondary interface to select the appropriate DRAM device1312. In this embodiment, all DRAM devices share common C[2:0] bus. In embodiments with multiple devices at a device site, additional CS information may be received on the primary interface to select the appropriate device at the selected device site. It should also be noted thatFIG.13illustrates one 24-bit slice of a 72-bit wide DIMM, but other slices are identical.

FIG.14is a diagram illustrating a R+DDR4 DRAM1400according to one embodiment. The R+DDR4 DRAM1400includes an array1402, a data path1404coupled to the array1402, and a command decoder1406coupled to the array1042and the data path1404. A primary port1408is coupled to a secondary port1410, which is coupled to the data path1404. The R+DDR4 DRAM1400also includes a delay locked loop (DLL)1412. The array1402may also refer to a local stack at a device site, such as in a 3DS structure. The data path1404may include a read first-in-first-out (FIFO) buffer, a write deserializer, and a latency counter. The command decoder1406receives CA signals1407from a CA buffer component (not illustrated) to control the array1402and data path1404. In some cases, data (DQ_P) is directed by the data path1404to or from the array1402through the primary port1408and secondary port1410. In other cases, data (DQ_S) is directed by the data path1404to or from the array1402through the secondary port1410. The primary port1408and secondary port1410are coupled to a DQ buffer component (not illustrated). In other scenarios, the primary port1408may be coupled to one DQ buffer component (not illustrated) and the secondary port1410may be coupled to another DQ buffer component (not illustrated).

In one embodiment, the R+DDR4 DRAM is x4 DDR4 DRAM or DDR4 3DS DRAM with dual x4 ports. The primary port1408maps to the DQ[3:0] nibble in a x4 DRAM and the secondary port1410maps to the unused DQ[7:4] nibble in a x4 DRAM. The R+DDR4 DRAM can be configured through a 2-bit configuration register, according to the following: 'b00: DRAM transmits and receives on the primary (DQ[3:0]) port; 'b01: DRAM transmits and receives on the secondary (DQ[7:4]) port; 'b10: DRAM MUX's primary port to either the internal core (or local 3DS stack) or the secondary port based on an external sideband signal; and 'b11: RFU (reserved for future use). As described herein, the DRAM configuration depends on a number of DIMM slots populated in a memory channel.

FIG.15Ais a diagram illustrating a 2-SPC DDR4 channel1500with one DIMM slot populated with one low-cost R+LRDIMM1508and another DIMM slot populated with a C-DIMM1506according to one embodiment. The low-cost R+LRDIMM1508is considered low-cost in that it does not include the DQ buffer components present in the R+LRDIMMs described above. All DRAM devices (e.g.,1512,1514) of low-cost R+LRDIMM1508are configured to transmit and receive on DQ[3:0] port ('b00). The low-cost R+LRDIMM1508includes 72 bits and eighteen device sites, each including a single DRAM device, such as illustrated with DRAM devices1512,1514. The DRAM device1512is coupled to a CPU1501via a first set of data lines1522(first nibble). The second DRAM device1514is coupled to the CPU1501via a second set of data lines1524, and inner traces1526of C-DIMM1506connect data lines1524to data lines1528, which are coupled to the CPU1501(second nibble). Although only two DRAM devices1512,1514are described, similar sets of data lines can be used to connect the other sixteen DRAM devices to the CPU1501when the 2-SPC DDR4 channel1500is populated with one low-cost R+LRDIMM1508. In this configuration, data lines1516between the first DRAM device1512and second DRAM device1514are unused (inactive). In one implementation, JEDEC standard DDR4 LRDIMM has ten buffer components (10 chips) to address SI limitations of multi-drop topology, including one CA buffer components (also referred to as C/A register (RCD)) and nine DQ buffered components (also referred to as DBs). This 10-chip solution has significant cost premium over RDIMM. The low-cost DDR4 R+LRDIMM1508uses DPP technology to ensure that all DQ signals are always point-to-point and there are no multi-drop DQ nets. Since all DQ signals are point-to-point, RCD and DBs can be combined into a single integrated circuit (IC) (or “single chip”). The single chip solution provides cost savings and power savings over a 10-chip solution, reducing cost premium of LRDIMM over RDIMM. The low-cost DDR4 R+LRDIMM1508can be buffer-less in that the low-cost DDR4 R+LRDIMM1508can implement the buffer function in an R+DDR DRAM device. This cost reduction may fit well with 3DS structures that are supported in the DDR4 specification. 3DS master-slave architecture presents a single electrical load on the channel irrespective of a number of ranks in the DIMM. The changes to the CA buffer component, as described herein, to support R+LRDIMM may also enable low-cost R+LRDIMM. That is, the same CA buffer component can be used for R+LRDIMM and low-cost R+LRDIMM. For example, the steering logic on a master device can be presented and not enabled.

FIG.15Bis a diagram illustrating 2-SPC DDR4 channel1550with two DIMM slots populated with low-cost R+LRDIMMs1508,1558according to one embodiment. The low-cost R+LRDIMMs1508,1558are considered low-cost in that they do not include the DQ buffer components present in the R+LRDIMMs described above. Some of DRAM devices (e.g.,1514,1564) of low-cost R+LRDIMMs1508,1558are configured to transmit and receive on DQ[7:4] port ('b01) and others DRAM devices (e.g.,1512,1562) are configured as multiplexers (port 'b10) and transmit and receive on DQ[3:0] port. The low-cost R+LRDIMM1508includes 72 bits and eighteen device sites, each including a single DRAM device, such as illustrated with DRAM devices1512,1514. The low-cost R+LRDIMM1558also includes 72 bits and eighteen device sites, each including a single DRAM device, such as illustrated with DRAM devices1562,1564. The DRAM device1512is coupled to a CPU1501via the first set of data lines1522(first nibble). The DRAM device1562is coupled to the CPU1501via data lines1528. The second DRAM device1514is coupled to the first DRAM device1512via data lines1530. The second DRAM device1564is coupled to the first DRAM device1562via data lines1532.

Although only two DRAM devices (1512,1514or1562,1564) are described, similar sets of data lines can be used to connect the other sixteen DRAM devices to the CPU1501when the 2-SPC DDR4 channel1550is populated with two low-cost R+LRDIMMs1508,1558. In this configuration, data lines1524between the first and second slots are unused (inactive).

In the 2-SPC DDR4 channel1550, the data lines1522and1528are considered a primary channel and the data lines1530and1532are considered a secondary channel. Simulations have shown that the primary channel and the secondary channel can both operate at 3.2 Gb/s. In some embodiments, the private bus, as described above, can operate at 1.6 Gb/s, the CA bus can operate at 1.6 Gb/s, and the DQ bus can operate at 3.2 Gb/s for a DDR4 3 SPC memory system. In further embodiments, the R+LRDIMM architecture can scale to rates beyond DDR4 data rates. For example, In one embodiment, the private bus can operate at 1.6 Gb/s, the CA bus can operate at 1.6 Gb/s, and the DQ bus can operate at 6.4 Gb/s for a beyond-DDR4 3 SPC memory system. These data rates can be achieved in 72-bit wide DIMMs as described herein. Alternatively, other width DIMMs can utilize the technologies descried herein.

The beyond-DDR4 DRAM devices can be used in various memory systems, as illustrated inFIGS.16A-16E. The beyond-DDR4 DRAM devices can be used for tablets, PCs, and servers. The data rates for the DQ buses may be in a range between 3.2 Gb/s to 6.4 Gb/s data rates with low voltage swing terminated logic (LVSTL), single-ended signaling. Multi-rank and multi-DIMM cycle redundancy check (CRC) may ensure integrity of data transmission. The beyond-DDR4 DRAM devices can have higher power efficiency than DDR4 DRAM devices, such as greater than 25%. For example, there may be zero DRAM input-output (I/O) power dissipation at all times except during CAS operation. In addition, an asymmetric design of the beyond-DDR4 DRAM device may ensure lower DRAM cost and higher DRAM yield. DLL and other complex timing circuits may be moved to the memory controller. As illustrated and described below with respect toFIGS.16A=16E. For example, unregister DIMM (UDIMM), registered DIMM (RDIMM), LRDIMM, and motherboard configurations can be used to achieve full capacity expansion, 2 DPC or 3 DPC) at a maximum data rate (e.g., 3.2 Gb/s or 6.4 Gb/s). The beyond-DDR4 DRAM device also reuses existing infrastructure of the DDR4 DRAM device. This may allow the use of standard connectors, memory modules, IC packages, PCBs, or the like.

As described herein, the DPP may permit the memory bus to operate at data rates beyond DDR4 data rates. to operate memory bus at beyond DDR4 data rates. Even with LRDIMM, multi-drop topology limits bus speed to less than 3 Gb/s for 2 DPC. The proposed DPP implementations fit well within the “beyond-DDR4” DRAM devices being developed. The CA bus may operate at 1.6 Gb/s and the private bus can be implemented with 1-clock added latency if no CPU support. The beyond-DDR4 data rates depend on memory channel configuration. For example, 4.8 Gb/s data rates can be demonstrated under WC conditions with 1 CDIMM (i.e. partially loaded channel) and 6.4 Gb/s data rates can be demonstrated under WC conditions with no CDIMMs (i.e. fully loaded channel)

FIG.16Ais a diagram illustrating a tablet memory configuration1600with a system on chip (SoC)1602and four beyond-DDR4 DRAM devices1604according to one embodiment. A CA bus1603can operate at 1.6 Gb/s to control the four beyond-DDR4 DRAM devices1604and a DQ bus1605between the SoC1602and the four beyond-DDR4 DRAM devices1604can operate at 6.4 Gb/s. This is 2× data rate of DDR4 devices and lower power than DDR4 devices. The tablet memory configuration1600may be used in a tablet device. Alternatively, the tablet memory configuration1600can be used in other portable electronic devices.

FIG.16Bis a diagram illustrating a personal computer (PC) memory configuration1620with a CPU1622and two memory channels1623,1625to two DIMM slots1624,1626, populated with beyond-DDR4 DRAM devices according to one embodiment. A first memory channel1623is coupled between the first DIMM slot1624(e.g., UDIMM/SODIMM) and includes a CA bus1627that operates at 1.6 Gb/s and DQ bus1629that operates at 6.4 Gb/x. A second memory channel1625is coupled between the second DIMM slot1626(e.g., UDIMM/SODIMM) and includes a CA bus1631that operates at 1.6 Gb/s and DQ bus1633that operates at 6.4 Gb/x. This is 2× data rate of DDR4 devices and lower power than DDR4 devices. The PC memory configuration1620may be used in a PC. Alternatively, the PC memory configuration1620can be used in other electronic devices with a CPU and one or more DIMMs.

FIG.16Cis a diagram illustrating a first server memory configuration1640with a CPU1642and a 1-SPC memory channel1643with one DIMM slot1644(e.g., ECC UDIMM) populated with one or more beyond-DDR4 R+LRDIMMs according to one embodiment. The memory channel1643is coupled between the DIMM slot1644(e.g., ECC UDIMM) and includes a CA bus1645that operates at 1.6 Gb/s and DQ bus1647that operates at 6.4 Gb/s. This is 2× data rate of DDR4 devices and lower power than DDR4 devices.

FIG.16Dis a diagram illustrating a second server memory configuration1660with a CPU1662and a 2-SPC memory channel1663with two DIMM slots1664,1666, populated with one or two R+LRDIMMs with beyond-DDR4 DRAM devices according to one embodiment. The memory channel1663is coupled between a first DIMM slot1664(e.g., LRDIMM) and a second DIMM slot1666(e.g., RDIMM/LRDIMM). The memory channel1663includes a CA bus1665that operates at 1.6 Gb/s. The CA bus1665may be a multi-drop bus. The memory channel1663also includes a first portion1667of a DQ bus between the CPU1662and the first slot1664that operates at 6.4 Gb/s and a second portion1669of the DQ bus between the CPU1662and the second slot1666that operates at 4.8 Gb/s. Ranks 2-8 may operate at 1.5× data rate of DDR4 and 16 ranks may operate at 2× data rate of DDR4.

FIG.16Eis a diagram illustrating a third server memory configuration1680with a CPU and a 3-SPC memory channel1683with three DIMM slots populated with one, two or three R+LRDIMMs with beyond-DDR4 DRAM devices according to one embodiment. The memory channel1683is coupled between a first DIMM slot1684(e.g., LRDIMM), a second DIMM slot1686(e.g., LRDIMM), and a third DIMM slot1688(e.g., RDIMM/LRDIMM). The memory channel1683includes a CA bus1685that operates at 1.6 Gb/s. The CA bus1685may be a multi-drop bus. The memory channel1683also includes a DQ bus that operates at 6.4 Gb/s. The DQ bus may include a first portion1687between the CPU1682and the first DIMM slot1684, a second portion1689between the CPU1682and the second DIMM slot1686, and a third portion1691between the CPU1682and the third DIMM slot1688. Ranks 2-16 may operate at 1.5× data rate of DDR4 and 24 ranks may operate at 2× data rate of DDR4. Alternatively, other server memory configurations are possible using the R+LRDIMMs and low-cost R+LRDIMMs described herein.

The embodiments described herein may also be compatible with standard error detection and correction (EDC) codes. This includes standard (Hamming) ECC bit codes and standard “Chip-kill” symbol codes. In fact, in some configurations, the embodiments can correct for the complete failure of a module. In some embodiments, the device sites include at least one of a single memory die, a package stack of at least two memory dies, or a die stack of at least two memory dies. In other embodiments, a memory system includes a memory controller, a motherboard substrate with at least three module sockets (or slots). At least one of the at least three memory modules socket is populated with a memory module including multiple memory components and a command and address (CA) buffer component. The memory system further includes a first set of data lines coupled between the memory controller and the at least three module sockets; and a second set of data lines coupled between the two module sockets. The module sockets may be dual in-line memory modules (DIMM) sockets.

In another embodiment, a memory module includes multiple module connector pins; multiple device sites; and a CA buffer component. The CA buffer component is configured to: receive chip select information on a primary set of CS lines coupled between the module connector pins and the CA buffer component; and send the CS information on a private bus to other modules in other module sockets as described herein. The CS information selects one of multiple ranks.

In other embodiments, the memory module further includes a second set of multiple module connector pins; a DQ buffer component; a third set of data lines coupled between the second multiple module connector pins and the DQ buffer component; and a fourth set of data lines coupled between the DQ buffer component and the multiple device sites. The memory module may include a second DQ buffer component and a third DQ buffer component. Each of the multiple ranks includes at least three device sites. These device sites may contain at least one of a single memory device, a package stack of at least two memory devices, or a die stack of at least two memory devices.

In other embodiments, a memory module includes multiple module connector pins; multiple device sites; and a CA buffer component. The CA buffer component includes a primary CA interface connected to a memory channel and a secondary CA interface connected to the multiple device sites. The CA buffer component is further configured to receive a first set of one-hot chip select control signals on the primary CA interface, and pass the one-hot chip select signals to the private bus to the other module sockets. The CA buffer components selects one memory device at each of the multiple device sites to perform a first command specified on other lines of the CA interface.

In another embodiment, the memory module further includes multiple data-link buffer devices. The memory module is configured to operate in a first mode of operation or a second mode of operation. In the first mode of operation, the memory module is inserted onto a first type of memory channel with multi-drop data links shared with at least one other memory module. In the second mode of operation, the memory module is inserted onto a second type of memory channel with point-to-point data links that do not share with the at least one other memory module as described herein.

In another embodiment, a motherboard substrate includes at least three module sockets (or slots). At least one of the at least three memory modules socket is populated with a memory module. The memory module includes multiple device sites coupled to a DQ buffer component via data lines and coupled to a CA buffer component via CS lines. There are two classes of links: the CA (control-address) links and the DQ (data) links. These signals are transmitted (and received, in the case of DQ links) by a memory controller component (also referred to herein as a memory controller but can be other components that control access to the memory modules). These signals are typically received (and transmitted, in the case of DQ links) by buffer components on a module, such as a CA buffer component and one or more DQ buffer components. Various embodiments discussed in present application are directed to memory modules with seventy-two data links (72 DQ links) to accommodate standard ECC codes. The technologies described in the present embodiments can be applied to memory modules with other number of data links as well, such as sixty-four DQ links.

The embodiments disclosed in this disclosure can be employed to gain a number of important benefits. For example, the signaling integrity of the DQ links may be improved significantly from the multi-drop topology of standard systems: each DQ link uses a point-to-point topology. High capacity systems described herein may allow standard error detection and correction codes (i.e. ECC, Chip-kill); in addition, in some configurations it is possible to correct for the complete failure of a module. These improvements may be achieved while maintaining a high degree of compatibility to standard memory systems and their components. For example, there may be no changes to the memory components, modest changes or no changes to the memory controller component. There may be changes to the module and the motherboard wiring as described herein. However, the modules described herein may be compatible with standard systems, as well as high-capacity systems. By offering a standard mode and an improved mode of operation, the manufacturer of the controller component and the buffer component can deliver the same product into both standard motherboards and improved, high capacity motherboards, for example.

FIG.17is a diagram of one embodiment of a computer system1700, including main memory1704with three memory modules1780according to one embodiment. The computer system1700may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet. The computer system1700can be a host in a cloud, a cloud provider system, a cloud controller, a server, a client, or any other machine. The computer system1700can operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a console device or set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The computer system1700includes a processing device1702(e.g., host processor or processing device), a main memory1704(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), a storage memory1706(e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory1718(e.g., a data storage device in the form of a drive unit, which may include fixed or removable computer-readable storage medium), which communicate with each other via a bus1730. The main memory1704includes one, two or three memory modules1780(e.g., R+LRDIMMS) that are described in various embodiments herein.

Processing device1702represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device1702may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device1702may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processing device1702includes a memory controller1720as described above. The memory controller1754is a digital circuit that manages the flow of data going to and from the main memory1704. The memory controller1720can be a separate integrated circuit, but can also be implemented on the die of a microprocessor. The memory controller1720may the memory controller described in various embodiments described herein.

In one embodiment, the processing device1702may reside on a first integrated circuit and the main memory1704may reside on a second integrated circuit. For example, the integrated circuit may include a host computer (e.g., CPU having one more processing cores, L1 caches, L2 caches, or the like), a host controller or other types of processing devices1702. The second integrated circuit may include a memory device coupled to the host device, and whose primary functionality is dependent upon the host device, and can therefore be considered as expanding the host device's capabilities, while not forming part of the host device's core architecture. The memory device may be capable of communicating with the host device via a DQ bus and a CA bus. For example, the memory device may be a single chip or a multi-chip module including any combination of single chip devices on a common integrated circuit substrate. The components ofFIG.17can reside on “a common carrier substrate,” such as, for example, an integrated circuit (“IC”) die substrate, a multi-chip module substrate or the like. Alternatively, the memory device may reside on one or more printed circuit boards, such as, for example, a mother board, a daughter board or other type of circuit card. In other implementations, the main memory and processing device1702can reside on the same or different carrier substrates.

The computer system1700may include a chipset1708, which refers to a group of integrated circuits, or chips, that are designed to work with the processing device1702and controls communications between the processing device1702and external devices. For example, the chipset1708may be a set of chips on a motherboard that links the processing device1702to very high-speed devices, such as main memory1704and graphic controllers, as well as linking the processing device to lower-speed peripheral buses of peripherals1710, such as USB, PCI or ISA buses.

The computer system1700may further include a network interface device1722. The computer system1700also may include a video display unit (e.g., a liquid crystal display (LCD)) connected to the computer system through a graphics port and graphics chipset, an alphanumeric input device (e.g., a keyboard), a cursor control device (e.g., a mouse), and a signal generation device (e.g., a speaker).

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention.

For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments.

Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links.

Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments.

Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented.

With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition.

Conversely, a signal is said to be “de-asserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition).

A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits.

A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is de-asserted.

Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state).

A line over a signal name (e.g., ‘ ’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures.

Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement.

While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

In the above description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that embodiments of the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the description.

Some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as “encrypting,” “decrypting,” “storing,” “providing,” “deriving,” “obtaining,” “receiving,” “authenticating,” “deleting,” “executing,” “requesting,” “communicating,” or the like, refer to the actions and processes of a computing system, or similar electronic computing device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and memories into other data similarly represented as physical quantities within the computing system memories or registers or other such information storage, transmission or display devices.

The words “example” or “exemplary” are used herein to mean serving as an example, instance or illustration. Any aspect or design described herein as “example’ or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this disclosure, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this disclosure and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an embodiment” or “one embodiment” or “an implementation” or “one implementation” throughout is not intended to mean the same embodiment or implementation unless described as such.

Embodiments descried herein may also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMS, EEPROMs, magnetic or optical cards, flash memory, or any type of media suitable for storing electronic instructions. The term “computer-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and/or associated caches and servers) that store the one or more sets of instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments. The term “computer-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, magnetic media, any medium that is capable of storing a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the embodiments as described herein.

The above description sets forth numerous specific details such as examples of specific systems, components, methods and so forth, in order to provide a good understanding of several embodiments of the present invention. It will be apparent to one skilled in the art, however, that at least some embodiments of the present invention may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present invention. Thus, the specific details set forth above are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present invention.

It is to be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.