Patent ID: 12198746

DETAILED DESCRIPTION

In order to clarify objectives, technical solutions, and advantages of embodiments of the present disclosure, hereinafter technical solutions in embodiments of the present disclosure are described clearly and completely in conjunction with the drawings in embodiments of the present closure. Apparently, the described embodiments are only some rather than all of the embodiments of the present disclosure. Any other embodiments obtained based on the embodiments of the present disclosure by those skilled in the art without any creative effort shall fall within the protection scope of the present disclosure.

In the specification, claims, and accompanying drawings of the present disclosure, the terms “first”, “second”, and the like are intended for distinguishing similar objects rather than necessitating a specific order. The data termed in such a way are interchangeable in proper circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than the order illustrated or described herein. Moreover, the terms “include”, “contain” and any other variants are meant to be non-exclusive. For example, a process, a method, a system, a product, or a device that includes a series of steps or units is not necessarily limited to those expressly listed steps or units, but may include another step or another unit which is not expressly listed or which is inherent to such process, such method, such system, such product, or such device.

Herein the terms “upper”, “lower”, “left”, “right”, “front”, “rear”, “top”, “bottom”, “inner”, “outer”, “middle”, “vertical”, “horizontal”, “transverse”, “longitudinal”, and the like, indicates orientations or position relationships based on illustrations as shown in the drawings. The terms are merely for convenience of describing embodiments of the present disclosure, and are not intended for limiting the indicated devices, elements or components to be arranged, constructed, or operated based on particular orientations.

Moreover, some of the above terms may be further used under other meanings. For example, the term “on top of” may indicate attachment or connection in some cases. Those of ordinary skill in the art can understand specific meanings of such terms in the present disclosure based on specific situations.

Furthermore, the terms “install”, “dispose”, “provide”, “connect”, “couple”, “socket” should be broadly interpreted. For example, there may be a fixed connection, a detachable connection, or an integral structure, there may be a mechanical connection or an electrical connection, there may be a direct connection or an indirect connection via an intermediate, or there may be connection between inner spaces of two devices, elements, or components. Those of ordinary skill in the art can understand specific meanings of such terms in the present disclosure based on specific situations.

Hereinafter some embodiments of the present disclosure are described in detail in conjunction with the drawings. Embodiments described hereinafter and features therein are may be combined where there is no conflict.

A double-input single-output (DISO) in-memory computing unit is provided according to an embodiment of the present disclosure. The DISO in-memory computing unit is implemented based on STT-MTJs (spin transfer torque magnetic tunnel junctions).FIG.1shows a schematic structural diagram of the in-memory computing unit. As shown inFIG.1, the DISO in-memory computing unit includes two input STT-MTJs and one output STT-MTJ. Free layer sides (i.e., a terminal at a side where a free layer is located) of the two input STT-MTJs serve as a voltage input terminal and are connected to a positive terminal of an operating voltage Vdd. Reference layer sides (i.e., a terminal at a side where a reference layer is located) of the two input STT-MTJs are connected to a reference layer side of the output STT-MTJ. A free layer side of the output STT-MTJ serves as a ground and is connected to a negative terminal GND of the operating voltage.

Here the DISO in-memory computing unit is formed through serial and parallel connection among STT-MTJs, and states of resistance of the STT-MTJs are used as inputs and an output of logical operations. Reference is made toFIG.1. Under a certain operating voltage Vdd, different resistance states of the two input STT-MTJs would lead to different combined currents flowing through the output STT-MTJ. Therefore, the resistance state of the output STT-MTJ is correlated with the resistance states of the input STT-MTJs, which can implement the Boolean logic. In addition, different logic may be achieved through initializing the output STT-MTJ to certain resistance state and providing a suitable operating voltage Vdd. Thereby, data storage and logical operations can be realized under the same circuit architecture, and the logic is reconfigurable.

FIG.2shows a schematic structural diagram of an in-memory computing unit according to another embodiment of the present disclosure. As shown inFIG.2, the DISO in-memory computing unit includes two input STT-MTJs and one output STT-MTJ. Reference layer sides of the two input STT-MTJs serve as a voltage input terminal and are connected to a positive terminal of an operating voltage Vdd. Free layer sides of the two input STT-MTJs are connected to a free layer side of the output STT-MTJ. The reference layer side of the output STT-MTJ serves as a ground and is connected to a negative terminal GND of the operating voltage. The structure of the in-memory computing unit as shown inFIG.2and the structure of the in-memory computing unit as shown inFIG.1differ in a manner of connection, and operate based on a same principle that the logic is implemented based on a current flowing through the STT-MTJs.

Practical experiment has evidence that the foregoing DISO in-memory computing units are capable to implement each of following four logical operations: NAND, NOR, AND, and OR.

The DISO in-memory computing unit is configured to implement the NAND logical operation in case of a following condition. The output STT-MTJ is initialized to logic 0, the operating voltage at the voltage input terminal with respect to the ground ranges from 0.0731V to 0.0908V, and a ratio among critical dimensions of the two input STT-MTJs and the output STT-MTJ is 1:1:1.

The DISO in-memory computing unit is configured to implement the NOR logical operation in case of a following condition. The output STT-MTJ is initialized to logic 0, the operating voltage at the voltage input terminal with respect to the ground ranges from 0.0650V to 0.0730V, and a ratio among critical dimensions of the two input STT-MTJs and the output STT-MTJ is 1:1:1.

The DISO in-memory computing unit is configured to implement the AND logical operation in case of a following condition. The output STT-MTJ is initialized to logic 1, the operating voltage at the voltage input terminal with respect to the ground ranges from −0.202V to 0.195V, and a ratio among critical dimensions of the two input STT-MTJs and the output STT-MTJ is 1:1:0.5.

The DISO in-memory computing unit is configured to implement the OR logical operation in case of a following condition. The output STT-MTJ is initialized to logic 1, the operating voltage at the voltage input terminal with respect to the ground ranges from −0.211V to 0.205V, and a ratio among critical dimensions of the two input STT-MTJs and the output STT-MTJ is 1:1:0.7.

It can be seen that the four logical operations can be implemented by the DISO in-memory computing unit through adjusting the operating voltage applied between the voltage input terminal and the ground and adjusting the initialization value of the output STT-MTJ.

On a basis of the DISO in-memory computing unit, an in-memory computing circuit having reconfigurable logic is further provided according to another embodiment of the present disclosure. The in-memory computing unit includes an input stage, N output stages, and multiple switches.

The input stage includes STT-MTJs, of which a quantity of 2Nand each of which stores one bit.

Among the N output stages, the first output stage includes 2N-1STT-MTJs, and each stage other than the first output stage in the N output stages includes STT-MTJs of which a quantity is equal to a half of a quantity of STT-MTJs in the output stage just previous to said stage. The last output stage includes only one STT-MTJ.

The switches are disposed between the input stage and the first output stage, and between successive output stages. The switches are configured to connect and disconnect the STT-MTJs between the input stage and the first output stage, and connect and disconnect the STT-MTJs among the successive N output stages.

The STT-MTJs in the first output stage are in one-to-one correspondence to STT-MTJ groups, each of which includes two STT-MTJs of the STT-MTJs in the input stage, and the STT-MTJs in the first output stage and the STT-MTJs in the input stage form DISO in-memory computing units, of which a quantity is 2N-1, via a configuration of the switches between the input stage and the first output stage. In each DISO in-memory computing unit, the two STT-MTJs in the input stage serve as two input STT-MTJs, and the corresponding STT-MTJ in the first output stage serves as an output STT-MTJ. Free layer sides of the two input STT-MTJs serve as a voltage input terminal and are connected to a positive terminal of an operating voltage, reference layer sides of the two input STT-MTJs are connected to a reference layer side of the output STT-MTJ, and a free layer side of the output STT-MTJ serves as a ground and is connected to a negative terminal of the operating voltage. Or, reference layer sides of the two input STT-MTJs serve as a voltage input terminal and are connected to a positive terminal of an operating voltage, free layer sides of the two input STT-MTJs are connected to a free layer side of the output STT-MTJ, and a reference layer side of the output STT-MTJ serves as a ground and is connected to a negative terminal of the operating voltage.

For each output stage, the STT-MTJs in said output stage are in one-to-one correspondence to STT-MTJ groups, each of which includes two STT-MTJs in the output stage just previous to said stage, and the STT-MTJs in said stage and the STT-MTJs in the previous output stage form DISO in-memory computing units via a configuration of the switches between said stage and the previous output stage. In each DISO in-memory computing unit, the two STT-MTJs in the output stage serve as two input STT-MTJs, and the corresponding STT-MTJ in said output stage serves as an output STT-MTJ. Free layer sides of the two input STT-MTJs serve as a voltage input terminal and are connected to a positive terminal of an operating voltage, reference layer sides of the two input STT-MTJs are connected to a reference layer side of the output STT-MTJ, and a free layer side of the output STT-MTJ serves as a ground and is connected to a negative terminal of the operating voltage. Or, reference layer sides of the two input STT-MTJs serve as a voltage input terminal and are connected to a positive terminal of an operating voltage, free layer sides of the two input STT-MTJs are connected to a free layer side of the output STT-MTJ, and a reference layer side of the output STT-MTJ serves as a ground and is connected to a negative terminal of the operating voltage.

Similarly, each DISO in-memory computing unit in the foregoing in-memory computing circuit having reconfigurable logic is capable to implement following four logical operations: NAND, NOR, AND, and OR.

The DISO in-memory computing unit is configured to implement the NAND logical operation in case of a following condition. The output STT-MTJ is initialized to logic 0, the operating voltage at the voltage input terminal with respect to the ground ranges from 0.0731V to 0.0908V, and a ratio among critical dimensions of the two input STT-MTJs and the output STT-MTJ is 1:1:1.

The DISO in-memory computing unit is configured to implement the NOR logical operation in case of a following condition. The output STT-MTJ is initialized to logic 0, the operating voltage at the voltage input terminal with respect to the ground ranges from 0.0650V to 0.0730V, and a ratio among critical dimensions of the two input STT-MTJs and the output STT-MTJ is 1:1:1.

The DISO in-memory computing unit is configured to implement the AND logical operation in case of a following condition. The output STT-MTJ is initialized to logic 1, the operating voltage at the voltage input terminal with respect to the ground ranges from −0.202V to 0.195V, and a ratio among critical dimensions of the two input STT-MTJs and the output STT-MTJ is 1:1:0.5.

The DISO in-memory computing unit is configured to implement the OR logical operation in case of a following condition. The output STT-MTJ is initialized to logic 1, the operating voltage at the voltage input terminal with respect to the ground ranges from −0.211V to 0.205V, and a ratio among critical dimensions of the two input STT-MTJs and the output STT-MTJ is 1:1:0.7.

In essence, herein the in-memory computing circuit having reconfigurable logic includes multiple cascaded stages of the in-memory computing units, and switches are provided between successive two stages to configure connection between the stages. An output of the previous stage serves as an input of the subsequent stage. All logic values are represented by resistance states of the MTJs, and therefore there is no need to exchange data with outside. In addition, each in-memory computing unit can be reconfigured among four Boolean logic operations through different switch settings. Therefore the whole circuit is reconfigurable among with 4nconfigurations, where n represents a quantity of the DISO in-memory computing units in the circuit.

When constructing the in-memory computing circuit, the switches for the in-memory computing units may be of various forms. For example, each switch may be a single-pole single-throw electronic switch or a single-pole double-throw electronic switch.

Hereinafter an example is illustrated to facilitate understanding the foregoing in-memory computing circuit having reconfigurable logic.

FIG.3is a schematic diagram of an in-memory computing circuit having reconfigurable logic according to an embodiment of the present disclosure. As shown inFIG.3, the in-memory computing circuit includes an input stage, a first output stage, a second output stage, a third output stage, and switches.

The input stage includes eight STT-MTJs, which are a first STT-MTJ, a second STT-MTJ, a third STT-MTJ, a fourth STT-MTJ, a fifth STT-MTJ, a sixth STT-MTJ, a seventh STT-MTJ, and an eighth STT-MTJ, and which are denoted by MTJ1, MTJ2, . . . and MTJ8, respectively. Each of the eight STT-MTJs stores one bit.

The first output stage includes four STT-MTJs, which are a ninth STT-MTJ, a tenth STT-MTJ, an eleventh STT-MTJ, and a twelfth STT-MTJ, and which are denoted by MTJ9, MTJ10, MTJ11and MTJ8, respectively.

The second output stage includes two STT-MTJs, which are a thirteenth STT-MTJ and a fourteenth STT-MTJ, and which are denoted by MTJ13and MTJ14, respectively.

The third output stage includes a fifteenth STT-MTJ denoted by MTJ15.

There are sixteen switches, which area first switch to a sixteenth switch, and which are denoted by S1to S16, respectively.

Hereinafter illustrated are connections in the in-memory computing circuit.

The STT-MTJs in the first output stage are in one-to-one correspondence to STT-MTJ groups, each of which includes two STT-MTJs of the STT-MTJs in the input stage, and the STT-MTJs in the input stage and the STT-MTJs in the first output stage form four DISO in-memory computing units.

The MTJ1, the MTJ4, and the MTJ9form a first in-memory computing unit. A free layer side of the MTJ1and a free layer side of the MTJ4serve as the voltage input terminal and are connected to a first operating voltage Vdd1, a reference layer side of the MTJ1and a reference layer side of the MTJ4are connected to a reference layer side of the MTJ9via the first switch S1, a free layer side of the MTJ9is connected to a ground via the ninth switch S9.

The MTJ2, the MTJ3, and the MTJ10form a second in-memory computing unit. A free layer side of the MTJ2and a free layer side of the MTJ3serve as the voltage input terminal and are connected to the first operating voltage Vdd1, a reference layer side of the MTJ2and a reference layer side of the MTJ3are connected to a reference layer side of the MTJ10via the fourth switch S4, a free layer side of the MTJ10is connected to the ground via the twelfth switch S12.

The MTJ5, the MTJ8, and the MTJ11form a third in-memory computing unit. A free layer side of the MTJ5and a free layer side of the MTJ8serve as the voltage input terminal and are connected to the first operating voltage Vdd1, a reference layer side of the MTJ5and a reference layer side of the MTJ8are connected to a reference layer side of the MTJ11via the fifth switch S5, a free layer side of the MTJ11is connected to the ground via the thirteenth switch S13.

The MTJ6, the MTJ7, and the MTJ12form a fourth in-memory computing unit. A free layer side of the MTJ6and a free layer side of the MTJ7serve as the voltage input terminal and are connected to the first operating voltage Vdd1, a reference layer side of the MTJ6and a reference layer side of the MTJ7are connected to a reference layer side of the MTJ12via the eighth switch S8, a free layer side of the MTJ12is connected to the ground via the sixteenth switch S16.

The STT-MTJs in the second output stage are in one-to-one correspondence to STT-MTJ groups, each of which includes two STT-MTJs of the STT-MTJs in the first output stage, and the STT-MTJs in the first output stage and the STT-MTJs in the second output stage form two DISO in-memory computing units.

The MTJ9, the MTJ10, and the MTJ13form a fifth in-memory computing unit. A reference layer side of the MTJ9and a reference layer side of the MTJ10serve as the voltage input terminal, the reference layer side of the MTJ9is connected to a second operating voltage Vdd2via the second switch S2, and the reference layer side of the MTJ10is connected to the second operating voltage Vdd2via the third switch S3, a free layer side of the MTJ9is connected to a free layer side of the MTJ13via the tenth switch S10, and a free layer side of the MTJ10is connected to the free layer side of the MTJ13via the eleventh switch S11.

The MTJ11, the MTJ12, and the MTJ14form a sixth in-memory computing unit. A reference layer side of the MTJ11and a reference layer side of the MTJ12serve as the voltage input terminal, the reference layer side of the MTJ11is connected to a second operating voltage Vdd2via the sixth switch S6, and the reference layer side of the MTJ12is connected to the second operating voltage Vdd2via the seventh switch S7, a free layer side of the MTJ11is connected to a free layer side of the MTJ14via the fourteenth switch S14, and a free layer side of the MTJ12is connected to the free layer side of the MTJ14via the fifteenth switch S15.

The two STT-MTJs in the second output stage and the single STT-MTJ in the third output stage form a seventh DISO in-memory computing unit.

A free layer side of the MTJ13and a free layer side of the MTJ14serve as the voltage input terminal, a reference layer side of the MTJ13and a reference layer side of the MTJ14are connected to a reference layer side of the MTJ15, and a free layer side of the MTJ15is connected to the ground.

The circuit as shown inFIG.3may be configured to implement the first-order Robert operator. Hereinafter is a truth table of the first-order Robert operator.

FirstSecondThirdFourthInputInputInputInputOutput00000000110010100111010010101101100011111000110011101001011111001110111110111110

There may be a case that the first STT-MTJ stores data A, the second STT-MTJ stores a negation A′ of the data A, the third STT-MTJ stores data D, the fourth STT-MTJ stores a negation D′ of the data D, the fifth STT-MTJ stores data C, and the sixth STT-MTJ stores a negation C′ of the data C, the seventh STT-MTJ stores data B, and the eighth STT-MTJ stores a negation B′ of the data B. Further, the first in-memory computing unit, the second in-memory computing unit, the third in-memory computing unit, and the fourth in-memory computing unit are configured to implement the AND logical operation, and the fifth in-memory computing unit, the sixth in-memory computing unit, and the seventh in-memory computing unit are configured to implement the OR logical operation. In such case, the switches S1, S4, S5, S8, S9, S12, S13, and S16is first switched on, so that the AND operations are performed between A and D′, A′ and D, B and C′, and C′ and D, respectively under the operating voltage of Vdd1. Then, switches S2, S3, S6, S7, S10, S11, S14, and S15are switched on, so that an output from each previous stage serves as an input into the corresponding subsequent stage, and the OR operations are performed under the operating voltage of Vdd2. Consequently, the overall logical operation is completed as y=A′*D+A*D′+B*C′+B′ *C, that is, image edge extraction based on the Robert operator is implemented. Therefore, the computing manner herein does not rely on a CMOS logic circuit, and in-memory computing is achieved.

Each of the first in-memory computing unit to the seventh in-memory computing unit is capable to implement the four logical operations under different configurations. Hence, the circuit can be reconfigured to implement other operators based on the structure as shown inFIG.3.

Reference is made toFIG.4for an example. The first STT-MTJ stores a negation ˜C of data C, the second STT-MTJ storing data A, the third STT-MTJ storing a negation ˜B of data B, the fourth STT-MTJ storing the data A, the fifth STT-MTJ storing the data B, the sixth STT-MTJ storing a negation ˜A of the data A, the seventh STT-MTJ storing the data C, and the eighth STT-MTJ storing the negation ˜A of the data A. The first in-memory computing unit, the second in-memory computing unit, the third in-memory computing unit, the fourth in-memory computing unit, the fifth in-memory computing unit, and the sixth in-memory computing unit are configured to implement the NOR logical operation, and the seventh in-memory computing unit is configured to implement the NAND logical operation. In such case, the in-memory computing circuit is configured to implement a gradient operator.

Reference is made toFIG.5for another example. The first STT-MTJ stores a negation of data D, the second STT-MTJ stores data C, the third STT-MTJ stores a negation ˜C of the data C, the fourth STT-MTJ stores data B, the fifth STT-MTJ storing a negation ˜B of the data B, the sixth STT-MTJ stores data A, the seventh STT-MTJ stores the data D, and the eighth STT-MTJ stores a negation ˜A of the data A. The first in-memory computing unit, the second in-memory computing unit, the third in-memory computing unit, the fourth in-memory computing unit, the fifth in-memory computing unit, and the sixth in-memory computing unit are configured to implement the NOR logical operation, and the seventh in-memory computing unit is configured to implement the NAND logical operation. In such case, the in-memory computing circuit is configured to implement a basic operator.

The structure of the in-memory computing circuit is provided according to embodiments of the present disclosure. Each logical operation unit includes the DISO in-memory computing unit. Input data, logical operations, and results of the operations are all stored in the same circuit architecture, and hence additional accesses to a memory are not necessary. Moreover, the circuit architecture stores the original input data, the computing operation of image edge extraction, and the output result data, which achieves in-memory computing.

Furthermore, the correlation between different logic is implemented through multiple switches which are configured between on-off combinations using time multiplexing. Thereby, an operational amplifier required by conventional spin logic cascading is saved, which reduces power consumption. Moreover, the logic of the last operation has been reconfigured when the current operation is performed, so that confidentiality of the circuit is enhanced.

In addition, the three operators can be achieved under the same circuit architecture through different configurations. A time of reconfiguration is equal to a writing time of the output MTJ for each operation unit, and thus the reconfiguration can be reduced to a nanosecond level. The switches may be controlled by an asynchronous clock to implement the computation process, and hence a CMOS logic circuit is not necessary. Moreover, the circuit supports large-scale parallel computation due to the in-memory computing characteristic.

The in-memory computing circuit provided herein is applicable to a circuit for image edge extraction, and is capable to implement various operators for image edge extraction flexibly.

Hereinabove described are only specific embodiments of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field disclosed in the present disclosure can easily make modification or substitutions, and such modification or substitutions shall all fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be defined the scope of the claims.