Patent ID: 12253584

DETAILED DESCRIPTION OF EMBODIMENTS

FIG.1schematically depicts a block diagram of a radio frequency (RF) receiver system in accordance with an embodiment of the invention. The RF receiver system1comprises at least one RF coil with at least one connection port2for receiving an analog MR information signal. The RF receiver system1further comprises a low noise amplifier LNA for amplifying the analog MR information signal. The amplified MR information signal is propagated to an analog to digital converter ADC. The ADC in this embodiment is a RF single-bit sigma-delta analog to digital converter with a variable output strength feedback DAC. The loop filter LF, the quantizer unit QUANT and digital to analog convertor DAC form the sigma delta ADC control loop. The output strength of the DAC must be sufficient (i.e. larger than the maximum input) to compensate for all signal levels at the LNA output during each period of the ADC clock FADC. A high output strength (or gain) of the DAC allows a high signal magnitude to be tracked. A low DAC gain results in low quantization noise and respectively high resolution for small signals. DAC gain therefore provides the possibility to shift the operational range of the ADC with respect to input signal strength, ideally keeping all other parameters (e.g. quantization and thermal noise) the same. It should be noted, however, that for high input signals, when the DAC gain is also made high numerous non-linear effects start to appear, due to the increased signal levels internal to the SDM that lead to degradation of the SNDR. Further, for any DAC gain settings, for high input signal non-linearities appear in the ADC operation that are also observed as a decrease of the SNDR. In this line a well-timed switching between low and high DAC gain is essential for proper operation. By increasing DAC gain only during periods of high signal magnitude the DR is extended only when needed and the corresponding decrease in SNDR is minimized. This is particularly advantageous for MRI echo signals that are only high for a limited duration, limiting a decrease in SNDR. In practice, this decrease in SNDR is marginal.

The automatic gain control AGC circuit inFIG.1tracks the magnitude of the detected signal and adjusts the DAC gain GDACaccordingly. Simultaneously, a digital representation of the DAC gain GADJis used to adjust the digital signal to compensate for the current DAC gain. The compensation is performed by multiplying the digital signal with GADJ.

The remainder of the circuit comprises the ranging receiver. The quantized signal is frequency shifted to baseband with a digital mixer MIX. The required RF carrier frequency is generated by a numerically controlled oscillator NCO. Subsequently, the baseband signal is low-pas filtered and decimated to baseband by a digital down convertor DDC. This mechanism provides for sufficiently fast and accurate determination of the switching point and for automatic calibration (equalization) of the digital data such that a uniform bitstream representing the complete dynamic range can be reconstructed.

It is advantageous to operate the AGC at an intermediate frequency FAGC. To this end, the DDC is split in two parts DDC1, DDC2. DDC1 converts the signal at FADCto the intermediate sampling frequency FAGCat which the AGC operates. DDC2 then further converts the signal to the baseband sampling frequency FBASEBAND.

FIG.2schematically depicts a block diagram of a radio frequency (RF) receiver system with a two-level (high-low) DAC in accordance with another embodiment of the invention. In this embodiment, the DAC is a two-level DAC with a high gain H and a low gain L. A calibration circuit CAL adjusts the sampled signal according to the relative gain between the H and L states of the DAC. CAL consists of a signed digital value that replaces the single-bit value output by QUANT when in the H state. For example, a DAC that has a nominal gain of 1.0 in the L state and a nominal gain of 5.0 in the H state may in practice have a relative gain of 4.9963. CAL consequently generates the following values as function of the gain state and QUANT output:

StateQUANTCALL−1−1.0000L+1+1.0000H−1−4.9863H+1+4.9863
A calibration procedure may be required to accurately determine relative DAC gain. Alternatively, the DAC may be calibrated during production, for example, through laser trimming of a resistor. Since the calibrated relative gain value must have sufficient accuracy to span the entire dynamic range of the input signal, it necessarily requires a large number of bits. For example, an MRI signal typically has a dynamic range of ˜90 dB and as a result, at least (˜90/6.02)=˜15 bits are required to accurately represent relative DAC gain. This results in a significant increase in DDC power consumption.

FIG.3schematically depicts a diagram of the threshold value TH and TL. To avoid excessive transitions between H an L states, the AGC may be implemented with hysteresis. This requires a high threshold value TH and a low threshold value TL. When the signal magnitude is larger than the high threshold (X>TH) the DAC transitions to the H state. When the signal magnitude is less than the low threshold (X<TL) the DAC transitions to the L state.

FIG.4schematically depicts a block diagram of a radio frequency (RF) receiver system with a two-level (high-low) DAC with a high-low calibration performed at the intermediate signal bandwidth, in accordance with another embodiment of the invention. DDC power consumption is proportional to both the number of bits required to represent the signal and the sampling frequency at which it operates. GADJnecessarily requires numerous bits to compensate the analogue GDACto sufficient accuracy. This increases the DDC consumption power required to down convert to baseband. By first converting the (unadjusted) signal to a lower intermediate sampling frequency, bit count at high sampling frequencies is reduced. FAGC thus provides a trade off between the maximum signal bandwidth that can be tracked by the AGC and the power consumption of the DDC.

Since the unadjusted signal is down converted to FAGC, it is necessary to down convert the H and L states signals concurrently, combining the two only after relative gain adjustment. This is performed by the high DDC HDDC and low DDC LDDC signal paths. The signal paths are summed by a summator SUM after calibration. Calibration now requires a multiplication MIX in the digital domain as the down converted signal has become a multi-bit signal due to the digital processing before multiplication/mixing.

FIG.5shows a flowchart of a method for extending the dynamic range of an ADC of a radio frequency (RF) receiver system in accordance with an embodiment of the invention. The method starts with step500, in which a providing a radio frequency (RF) receiver system according to claim1is provided.

Then in step510an analog MR information signal is received at the at least one connection port of the at least one RF coil within the RF receiver system.

Afterwards in step520an analog to digital conversion of the analog MR information signal into a digital MR information signal is performed in the RF receiver system.

The digital MR information signal at an ADC sampling frequency FADCis converted to an intermediate sampling frequency FAGCby a first digital down convertor DDC1 in step530.

The magnitude of the digital MR information signal is tracked with the automatic gain control AGC circuit in step540.

Afterwards the DAC gain GDACis adjusted regarding the magnitude of the digital MR information signal in step550.

In an embodiment of the invention the digital MR information signal is frequency shifted to a baseband sampling frequency FBasebandby a numerical controlled oscillator NCO for providing a RF carrier frequency and a digital mixer MIX. Furthermore, it may be provided in an execution example of the invention that the signal at an intermediate sampling frequency FAGCis converted to a baseband sampling frequency FBasebandby the second DDC DDC2.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope. Further, for the sake of clearness, not all elements in the drawings may have been supplied with reference signs.

REFERENCE SYMBOL LIST

Radio frequency (RF) receiver system1Connection port2Low-noise amplifier LNALoop filter LFQuantizer unit QUANTDigital to analog converter DACSigma delta modulator SDMAnalog to digital converter ADCADC Clock FADCIntermediate sampling frequency FAGCBaseband sampling frequency FBasebandAutomatic gain control AGCDigital down converter DDCNumerically controlled oscillator NCOFirst digital down converter DDC1Second digital down converter DDC2Low state LHigh state HDAC Gain GDACDigital representation of DAC gain GADJCalibration circuit CALLow digital down converter LDDCHigh digital down converter HDDCLow threshold TLHigh threshold THSummator SUMMixer MIX