Patent ID: 12215016

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Many MEMS devices (e.g., accelerometers, gyroscopes, etc.) comprise a movable mass and a fixed electrode plate. The movable mass has a planar surface aligned in parallel and spaced apart from an opposed planar surface of the fixed electrode plate. In response to external stimuli (e.g., pressure, acceleration, gravity, etc.), the movable mass is displaced inside a cavity. This displacement changes a distance between the movable mass and the fixed electrode plate. The change in distance may be detected by a change in capacitive coupling between the movable mass and the fixed electrode and analyzed by appropriate electrical circuits to derive a measurement of a physical quantity associated with the change in distance, such as acceleration.

One of the design challenges with MEMS devices is to prevent the movable mass from sticking to adjacent parts of the MEMS device, an effect known as stiction. As the scale of these devices continues to shrink, and spacing between adjacent surfaces becomes smaller, prevention of unintended stiction becomes an increasingly important design consideration. Stiction can occur under a number of conditions. During manufacturing, stiction can occur when, for example, the movable mass is not fully released from its neighboring surface. Stiction can also occur during normal operation when the movable mass deflects to a point in which the movable mass comes into contact with neighboring parts (e.g., surface of a cavity, surface of a stopper/bump, etc.).

Various embodiments of the present application are directed toward a MEMS device having a piezoelectric anti-stiction structure. The MEMS device includes an interlayer dielectric (ILD) structure that is disposed over a first semiconductor substrate. An upper surface of the ILD structure at least partially defines a bottom of a cavity. A second semiconductor substrate is disposed over the ILD structure and comprises a movable mass. In response to external stimuli, the movable mass is configured to be displaced within the cavity. The piezoelectric anti-stiction structure comprises a piezoelectric structure and an electrode. Further, the piezoelectric anti-stiction structure is disposed between the moveable mass and the upper surface of the ILD structure. Because the piezoelectric anti-stiction structure is disposed between the moveable mass and the upper surface of the ILD structure, the piezoelectric anti-stiction structure may prevent/correct stiction.

For example, if the movable mass deflects beyond a given point towards the bottom of the cavity, the piezoelectric anti-stiction structure will prevent the movable mass from contacting the bottom of the cavity and potentially sticking to the upper surface of the ILD structure. Thus, if the movable mass were to stick to a neighboring part, the movable mass would stick to the piezoelectric anti-stiction structure. If the movable mass becomes stuck to the piezoelectric anti-stiction structure, a voltage can be applied to the electrode that is sufficient to cause the piezoelectric structure to deform (or vibrate), thereby generating a mechanical force that may release the movable mass from its stuck state on the piezoelectric anti-stiction structure.

Another example of the piezoelectric anti-stiction structure preventing/correcting stiction may comprise the movable mass having a first doping type. In such embodiments, a first voltage is applied to the electrode, and a second voltage is applied to the movable mass. Thus, a voltage across the piezoelectric structure will differ based on a distance the movable mass is from the electrode. Accordingly, if the movable mass deflects beyond a given point towards the bottom of the cavity (e.g., contacting the piezoelectric anti-stiction structure), the distance between the movable mass and the electrode will cause the voltage across the piezoelectric anti-stiction structure to be sufficient to cause the piezoelectric structure to deform, thereby generating a mechanical force that may release the movable mass from its stuck state on the piezoelectric anti-stiction structure.

FIG.1illustrates a cross-sectional view of some embodiments of a microelectromechanical system (MEMS) device100comprising a piezoelectric anti-stiction structure. The MEMS device100may be, for example, an accelerometer, a gyroscope, or some other MEMS device.

As shown inFIG.1, the MEMS device100comprises a first semiconductor substrate102. The first semiconductor substrate102may comprise any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.). In some embodiments, one or more semiconductor devices104may be disposed on/in the first semiconductor substrate102. In further embodiments, the semiconductor devices104may be or comprise, for example, metal-oxide-semiconductor (MOS) field-effect transistors (FETs), some other MOS devices, or some other semiconductor devices. In yet further embodiments, the first semiconductor substrate102may be referred to as a complementary metal-oxide-semiconductor (CMOS) substrate.

An interlayer dielectric (ILD) structure106is disposed over the first semiconductor substrate102and the semiconductor devices104. An interconnect structure108(e.g., copper interconnect) is embedded in the ILD structure106. The interconnect structure108comprises a plurality of conductive features (e.g., metal lines, metal vias, metal contacts, etc.). In some embodiments, the ILD structure106comprises one or more stacked ILD layers, which may respectively comprise a low-k dielectric (e.g., a dielectric material with a dielectric constant less than about 3.9), an oxide (e.g., SiO2), or the like. In further embodiments, the ILD structure106comprises a lower ILD structure110and an upper ILD structure112disposed over the lower ILD structure110. In yet further embodiments, the plurality of conductive features may comprise, for example, copper (Cu), aluminum (Al), tungsten (W), titanium nitride (TiN), aluminum-copper (AlCu), some other conductive material, or a combination of the foregoing.

A second semiconductor substrate114is disposed over both the ILD structure106and the first semiconductor substrate102. The second semiconductor substrate114may comprise any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, SiGe, SOI, etc.). In some embodiments, the second semiconductor substrate114may have a first doping type (e.g., p-type/n-type). In further embodiments, the second semiconductor substrate114may be referred to as a MEMS substrate. In further embodiments, a third semiconductor substrate116is disposed over both the second semiconductor substrate114and the first semiconductor substrate102. The third semiconductor substrate116may comprise any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, SiGe, SOI, etc.). In yet further embodiments, the third semiconductor substrate116may be referred to as a cap substrate.

The ILD structure106at least partially defines a cavity118. In some embodiments, the upper ILD structure112, the interconnect structure108, the second semiconductor substrate114, and the third semiconductor substrate116define the cavity118. In further embodiments, an upper conductive line120of the interconnect structure108may at least partially define the cavity118. For example, the upper conductive line120and an upper surface of the upper ILD structure112may define a bottom surface of the cavity118, and a bottom surface of the third semiconductor substrate116may define an upper surface of the cavity118. In further embodiments, the upper conductive line120of the interconnect structure108may be the uppermost conductive line (e.g., uppermost metal line) of the interconnect structure108. In yet further embodiments, the third semiconductor substrate116at least partially defines an upper portion of the cavity118, and the upper ILD structure112at least partially defines a lower portion of the cavity118.

The second semiconductor substrate114comprises a movable mass122(e.g., proof mass). The movable mass122is a portion of the second semiconductor substrate114that is suspended in the cavity118by one or more tethers (not shown). In some embodiments, the movable mass122has the first doping type (e.g., p-type) or a second doping type (e.g., n-type) opposite the first doping type. In further embodiments, the movable mass122may have a first doping concentration of first doping type dopants (e.g., p-type dopants) that is greater than or equal to about 1×1020cm−3, or a second doping concentration of second doping type dopants (e.g., n-type dopants) that is greater than or equal to about 1×1020cm−3. In yet further embodiments, opposite sidewalls of the movable mass122are disposed between opposite sidewall of the upper ILD structure112.

A plurality of piezoelectric anti-stiction structures124are disposed in the cavity118. For example, a first piezoelectric anti-stiction structure124aand a second piezoelectric anti-stiction structure124bare disposed in the cavity118and spaced apart. In some embodiments, the piezoelectric anti-stiction structures124are disposed between an upper surface of the upper ILD structure112and the movable mass122. It will be appreciated that, in some embodiments, only a single piezoelectric anti-stiction structure may be disposed in the cavity118.

For clarity, features of the piezoelectric anti-stiction structures124may be described in reference to only one of the piezoelectric anti-stiction structures124(e.g., the first piezoelectric anti-stiction structure124a), and it will be appreciated that each of the plurality of piezoelectric anti-stiction structures124may also comprise such features. For example, the first piezoelectric anti-stiction structure124acomprises a first electrode126a. Therefore, it will be appreciated that the second piezoelectric anti-stiction structure124bmay comprise a second electrode126b(and any other piezoelectric anti-stiction structure may also comprise an electrode).

The first piezoelectric anti-stiction structure124acomprises a first piezoelectric structure128adisposed on the first electrode126a. In some embodiments, a first conductive structure130ais disposed on the first piezoelectric structure128a. In further embodiments, the first electrode126ais electrically coupled to one or more of the semiconductor devices104via the interconnect structure108. In further embodiments, the first electrode126ais electrically coupled to the upper conductive line120.

The first electrode126amay comprise, for example, platinum (Pt), titanium (Ti), copper (Cu), gold (Au), aluminum (Al), zinc (Zn), tin (Sn), some other conductive material, or a combination of the foregoing. In some embodiments, the first piezoelectric structure128amay comprise, for example, lead zirconate titanate (PZT), zinc oxide (ZnO), barium titanate (BaTiO3), potassium niobate (KNbO3), sodium-tungsten-oxide (Na2WO3), barium-sodium-niobium-oxide (Ba2NaNb5O5), lead-potassium-niobium-oxide (Pb2KNb5O15), langasite (La3Ga5SiO14), gallium phosphate (GaPO4), lithium-niobium-oxide (LiNbO3), lithium tantalate (LiTaO3), some other piezoelectric material, or a combination of the foregoing. The first conductive structure130amay comprise, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, some other conductive material, or a combination of the foregoing. In some embodiments, the first electrode126aand the first conductive structure130acomprise a same material (e.g., Pt). In other embodiments, the first electrode126amay comprise a different material than the first conductive structure130a. In further embodiments, the upper conductive line120may be a multi-layered structure comprising a first layer (e.g., TiN), a second layer (e.g., AlCu) disposed over and on the first layer, and a third layer (e.g., TiN) disposed over and on the second layer.

The first electrode126ais configured to receive a first voltage. In some embodiments, the first voltage is less than or equal to about 25 volts (V). More specifically, the first voltage may be between about 15 V and about 25 V. In some embodiments, the first conductive structure130ais configured to be electrically floating (e.g., having a floating voltage). In other embodiments, the first conductive structure130ais configured to receive a second voltage. In some embodiments, the second voltage may be less than or equal to about 5 V. In yet further embodiments, the movable mass122is configured to receive a third voltage. The third voltage may be less than or equal to about 5 V.

Because the piezoelectric anti-stiction structures124are disposed between the upper ILD structure112and the movable mass122, the piezoelectric anti-stiction structures124may prevent/correct stiction. For example, if the movable mass122becomes stuck to the first piezoelectric anti-stiction structure124a, the first voltage can be provided to the first electrode126a. By providing the first voltage to the first electrode126a, the first piezoelectric structure128amay deform (or vibrate) from a first shape to a second shape different than the first shape due to a voltage across the first piezoelectric structure128a, thereby generating a mechanical force that may be sufficient to correct (or prevent) a seized state (e.g., the movable mass122being stuck to the first piezoelectric anti-stiction structure124a).

FIG.2illustrates a cross-sectional view of some other embodiments of the MEMS device100ofFIG.1.

As shown inFIG.2, the piezoelectric anti-stiction structures124may comprise dielectric structures202disposed on the piezoelectric structures128, respectively. For example, the first piezoelectric anti-stiction structure124amay comprise a first dielectric structure202adisposed on the first piezoelectric structure128a, and the second piezoelectric anti-stiction structure124bmay comprise a second dielectric structure202bdisposed on a second piezoelectric structure128b. The first dielectric structure202ais separated from the upper ILD structure112by both the first piezoelectric structure128aand the first electrode126a. In some embodiments, the first dielectric structure202amay comprise, for example, an oxide (e.g., SiO2), a nitride (e.g., silicon nitride (SiN)), an oxy-nitride (e.g., silicon oxy-nitride (SiOXNY)), some other dielectric material, or a combination of the foregoing.

In embodiments in which the piezoelectric anti-stiction structures124comprise the dielectric structures202, respectively, the movable mass122may have the first doping type and have the first doping concentration or have the second doping type and have the second doping concentration. In such embodiments, the piezoelectric anti-stiction structures124may prevent/correct stiction by providing the third voltage to the movable mass122and applying the first voltage to the first electrode126a. In some embodiments, the third voltage and the first voltage may be applied whether the movable mass122is in a seized state (e.g., unable to freely move) or in movable state (e.g., normal operating state). By providing the first voltage to the first electrode126aand the third voltage to the movable mass122, a voltage across the first piezoelectric structure128awill differ based on a distance in which the movable mass122is from the first electrode126a. Accordingly, if the movable mass122deflects beyond a given point towards the first piezoelectric anti-stiction structure124a(e.g., contacts/sticks to the first dielectric structure202a), the voltage across the first piezoelectric structure128amay be sufficient to cause the first piezoelectric structure128ato deform, thereby generating a mechanical force that may be sufficient to correct (or prevent) a seized state. In further embodiments, the first doping concentration and/or the second doping concentration may be such that the voltage across the first piezoelectric structure128ais not sufficient to deform the first piezoelectric structure128aunless the movable mass122contacts/sticks to the first dielectric structure202a.

FIG.3illustrates a cross-sectional view of some other embodiments of the MEMS device100ofFIG.1.

As shown inFIG.3, the piezoelectric anti-stiction structures124may be disposed between the movable mass122and the third semiconductor substrate116. For example, a third piezoelectric anti-stiction structure124cand a fourth piezoelectric anti-stiction structure124dare disposed in the cavity118and between the movable mass122and a bottom surface of the third semiconductor substrate116. Because the third piezoelectric anti-stiction structure124cis disposed between the movable mass122and the third semiconductor substrate116, the third piezoelectric anti-stiction structure124cmay prevent/correct stiction in which the movable mass122is stuck to a surface disposed above the movable mass122(e.g., the bottom surface of the third semiconductor substrate116). In some embodiments, the piezoelectric anti-stiction structures124disposed between the movable mass122and the third semiconductor substrate116may be referred to as piezoelectric anti-stiction stoppers. In further embodiments, the piezoelectric anti-stiction structures124disposed between the movable mass122and the upper ILD structure112may be referred to as piezoelectric anti-stiction bumps.

In some embodiments, the third piezoelectric anti-stiction structure124ccomprises a third dielectric structure202cdisposed on a third piezoelectric structure128c. The third dielectric structure202cseparates both the third piezoelectric structure128cand a third electrode126cfrom the movable mass122. In further embodiments, the third electrode126cmay contact both the third semiconductor substrate116and the third piezoelectric structure128c.

In some embodiments, the piezoelectric anti-stiction structures124disposed above the movable mass122may be aligned in a vertical direction with the piezoelectric anti-stiction structures124disposed below the movable mass122, respectively. For example, the third piezoelectric anti-stiction structure124cmay be vertically aligned with the first piezoelectric anti-stiction structure124a. In other embodiments, the piezoelectric anti-stiction structures124disposed above the movable mass122may not be aligned with the piezoelectric anti-stiction structures124disposed below the movable mass122, respectively. For example, the third piezoelectric anti-stiction structure124cmay be spaced a first lateral distance from a sidewall of the upper ILD structure112, and the first piezoelectric anti-stiction structure124amay be spaced a second lateral distance from the sidewall of the upper ILD structure112different than the first lateral distance.

FIG.4illustrates a cross-sectional view of some other embodiments of the MEMS device100ofFIG.1.

As shown inFIG.4, some of the piezoelectric anti-stiction structures124may comprise the dielectric structures202and some other of the piezoelectric anti-stiction structures124may comprise the conductive structures130. For example, the first piezoelectric anti-stiction structure124amay comprise the first conductive structure130a, and the third piezoelectric anti-stiction structure124cmay comprise the third dielectric structure202c.

In some embodiments, a layout of the first piezoelectric anti-stiction structure124amay be generally square shaped, rectangular shaped, or the like. In some embodiments, sidewalls of the first piezoelectric anti-stiction structure124amay be substantially vertical. In other embodiments, the sidewalls of the first piezoelectric anti-stiction structure124amay be angled (e.g., angled inward as they extend from the upper surface of the upper ILD structure112). In further embodiments, sidewalls of the first electrode126amay be substantially aligned with sidewalls of the first piezoelectric structure128a. The sidewalls of the first piezoelectric structure128amay be substantially aligned with sidewalls of the first conductive structure130a. In yet further embodiments, sidewalls of the third piezoelectric structure128cmay be substantially aligned with sidewalls of the third dielectric structure202c.

The upper surface of the upper ILD structure112(e.g., bottom of the cavity118) is vertically spaced from an uppermost surface of the upper ILD structure112by a first distance D1. The first piezoelectric anti-stiction structure124ahas a first height H1. In some embodiments, the first height H1is between about 30 percent and about 50 percent of the first distance D1. In further embodiments, the first distance D1is less than or equal to about 3 micrometers (um). More specifically, the first distance D1may be between about 2 um and 3 um. In yet further embodiments, the first height H1is less than or equal to about 1.5 um. More specifically, the first height H1is about 1 um.

The bottom surface of the third semiconductor substrate116(e.g., top of the cavity118) is vertically spaced from a bottommost surface of the third semiconductor substrate116by a second distance D2. The third piezoelectric anti-stiction structure124chas a second height H2. In some embodiments, the second height H2is between about 30 percent and about 50 percent of the second distance D2. The second distance D2may be less than or equal to about 3 um. More specifically, the second distance D2may be between about 2 um and 3 um. The second height H2may be less than or equal to about 1.5 um. More specifically, the second height H2may be about 1 um.

In some embodiments, the first height H1may be substantially the same as the second height H2. In other embodiments, the first height H1may be different than the second height H2. In further embodiments, the first distance D1may be substantially the same as the second distance D2. In other embodiments, the first distance D1may be different than the second distance D2.

In some embodiments, a length (and/or width) of each the piezoelectric anti-stiction structures124may be substantially the same. In other embodiments, the length (and/or width) of some of the piezoelectric anti-stiction structures124may be different than the length (and/or width) of some other of the piezoelectric anti-stiction structures124. In further embodiments, a length of the first piezoelectric anti-stiction structure124amay be between about 15 percent and about 50 percent of the first distance D1. More specifically, the length of the first piezoelectric anti-stiction structure124amay be between about 0.5 um and about 1 um. In yet further embodiments, a width of the first piezoelectric anti-stiction structure124amay be between about 15 percent and about 50 percent of the first distance D1. More specifically, the width of the first piezoelectric anti-stiction structure124amay be between about 0.5 um and about 1 um.

In some embodiments, a length of the third piezoelectric anti-stiction structure124cmay be between about 15 percent and about 50 percent of the second distance D2. More specifically, the length of the third piezoelectric anti-stiction structure124cmay be between about 0.5 um and about 1 um. In further embodiments, a width of the third piezoelectric anti-stiction structure124cmay be between about 15 percent and about 50 percent of the second distance D2. More specifically, the width of the third piezoelectric anti-stiction structure124cmay be between about 0.5 um and about 1 um.

FIG.5illustrates a cross-sectional view of some more detailed embodiments of the MEMS device100ofFIG.1.

As shown inFIG.5, an upper conductive via502(e.g., a metal via) is disposed in the upper ILD structure112. In some embodiments, the upper conductive via502is disposed in the both the upper ILD structure112and the lower ILD structure110. The upper conductive via502is electrically coupled to the interconnect structure108and the second semiconductor substrate114. In further embodiments, the upper conductive via502may comprise, for example, Cu, Al, W, or the like.

A first conductive channel504is disposed in the second semiconductor substrate114and provides an electrical connection between the upper conductive via502and the movable mass122. The first conductive channel504is a portion of the second semiconductor substrate114having the first doping type or the second doping type. In some embodiments, the third voltage may be applied to the movable mass122via the interconnect structure108, the upper conductive via502, and the first conductive channel504. In further embodiments, the third voltage may be applied to the movable mass122because the movable mass122has a same doping type as the first conductive channel504. In further embodiments, the first conductive channel504may extend from a fixed portion of the second semiconductor substrate114, along one or more of the tethers (not shown), and to a region of the movable mass122having the first doping type or the second doping type. In yet further embodiments, the first conductive channel504may be referred to as a first doped region.

In some embodiments, the third semiconductor substrate116is bonded to the second semiconductor substrate114via a bond structure506(e.g., a eutectic bond structure). The bond structure506may comprise an upper bond ring508disposed on a lower bond ring510. In some embodiments, the bond structure506is electrically conductive. In further embodiments, the lower bond ring510may comprise, for example, Cu, Al, Au, Sn, Ti, some other bonding material, or a combination of the foregoing. In further embodiments, the upper bond ring508may comprise, for example, Cu, Al, Au, Sn, Ge, some other bonding material, or a combination of the foregoing. The upper bond ring508may have a ring-shaped top layout that continuously extends around the movable mass122. In yet further embodiments, the lower bond ring510may have a ring-shaped top layout that continuously extends around the movable mass122.

A through-substrate via (TSV)512is disposed in the second semiconductor substrate114, the upper ILD structure112, and the lower ILD structure110. In some embodiments, the TSV512is disposed over the lower ILD structure110. The TSV512extends completely through the second semiconductor substrate114to electrically couple the interconnect structure108to the bond structure506. In further embodiments, the TSV512extends through an isolation structure514(e.g., shallow trench isolation (STI) structure) disposed in the second semiconductor substrate114. In yet further embodiments, the TSV512may comprise, for example, Cu, Al, W, or the like.

A second conductive channel516is disposed in the third semiconductor substrate116and provides an electrical connection between the bond structure506and a fourth electrode126d. The second conductive channel516is a portion of the third semiconductor substrate116having the first doping type or the second doping type. In some embodiments, the first voltage may be applied to the fourth electrode126dvia the interconnect structure108, the TSV512, the bond structure506, and the second conductive channel516. In further embodiments, the second conductive channel516may be referred to as a second doped region.

A third conductive channel518is disposed in the third semiconductor substrate116and provides an electrical connection between the bond structure506and the third electrode126c. The third conductive channel518is a portion of the third semiconductor substrate116having the first doping type or the second doping type. In some embodiments, the first voltage may be applied to the third electrode126cvia the interconnect structure108, the TSV512(or another TSV), the bond structure506, and the third conductive channel518. In further embodiments, the third conductive channel518may be referred to as a third doped region.

FIG.6illustrates a view of some embodiments of a system600comprising some embodiments of the MEMS device100ofFIG.1.

As shown inFIG.6, the system600comprises the MEMS device100and bias circuitry602. The bias circuitry602is electrically coupled to the MEMS device100. The bias circuitry602is configured to provide one or more bias signals606to the MEMS device100to prevent/correct stiction of the movable mass122of the MEMS device100(see, e.g.,FIG.5). For example, the bias circuitry602may provide a first bias signal606ahaving the first voltage to the electrodes126of the piezoelectric anti-stiction structures124, and the bias circuitry602may provide a second bias signal606bhaving the third voltage to the movable mass122.

In some embodiments, during operation of the MEMS device100, the bias circuitry602may continuously provide the one or more bias signals606to the MEMS device100. In other embodiments, the bias circuitry602may selectively provide the one or more bias signals606to the MEMS device100. In further embodiments, the bias circuitry602may selectively provide the one or more bias signals606to the electrodes126of the piezoelectric anti-stiction structures124. For example, in some embodiments, the bias circuitry602may provide only the first bias signal606ato the first electrode126a.

In some embodiments, the system600comprises measurement circuitry604that is electrically coupled to the MEMS device100. In further embodiments, the measurement circuitry604is electrically coupled to the bias circuitry602. The measurement circuitry604is configured to determine whether the MEMS device100is in a movable state (e.g., the movable mass122is free to move about the cavity118) or in a seized state (e.g., the movable mass122is unable to move freely about the cavity118). For example, the measurement circuitry604may provide one or more analysis signals608to the MEMS device100. The measurement circuitry604receives one or more response signals610that correspond to the one or more analysis signals608. For example, the measurement circuitry604may provide a first analysis signal608aand a second analysis signal608band receive a first response signal610aand a second response signal610b, respectively. The measurement circuitry analyzes the one or more response signals610to determine whether the movable mass122is in the movable state or the seized state (e.g., analyzing voltages to determine the location of the movable mass122in the cavity118in relation to one or more fixed electrodes).

The measurement circuitry604may determine the MEMS device100is in a first seized state or a second seized state. The first seized state may be referred to as a touch-down state and result when the movable mass122contacts/sticks to the first piezoelectric anti-stiction structure124aand the second piezoelectric anti-stiction structure124b. The second seized state may be referred to a tilt state and result when the movable mass122contacts/sticks to the first piezoelectric anti-stiction structure124abut not the second piezoelectric anti-stiction structure124b, or vice versa. In some embodiments, the measurement circuitry604may determine the movable mass122is in the first seized state when both the first response signal610aand the second response signal610bindicate the movable mass122is stuck to both the first piezoelectric anti-stiction structure124aand the second piezoelectric anti-stiction structure124b. In further embodiments, the measurement circuitry604may determine the movable mass122is in the second seized state when the first response signal610aindicates the movable mass122is stuck to the first piezoelectric anti-stiction structure124a, but the second response signal610bindicates the movable mass122is not stuck to the second piezoelectric anti-stiction structure124b.

In some embodiments, the measurement circuitry604may provide one or more state indicating signals612that are based on the state of the MEMS device100to the bias circuitry602. Based on the one or more state indicating signals612, the bias circuitry602may (or may not) provide the one or more bias signals606to the MEMS device100. For example, the measurement circuitry604may provide one or more state indicating signals612that indicate the MEMS device is in the movable state, and the bias circuitry602may not provide any of the one or more bias signals606to the MEMS device100. In other embodiments, during operation of the MEMS device100, the bias circuitry602continuously provides the one or more bias signals606to the MEMS device100.

In some embodiments, the measurement circuitry604may provide a first state indicating signal612aand a second state indicating signal612bto the bias circuitry602indicating the MEMS device100is in the first seized state, and the bias circuitry602may provide the one or more bias signals606to the MEMS device100. In such embodiments, the one or more bias signals606may be provided to one or more of the electrodes126of the piezoelectric anti-stiction structures124. In other embodiments, the measurement circuitry604may provide the first state indicating signal612aand the second state indicating signal612bto the bias circuitry602to indicate the MEMS device100is in the second seized state. For example, the first state indicating signal612amay indicate the movable mass122is stuck to the first piezoelectric anti-stiction structure124a, and the second state indicating signal612bmay indicate the movable mass122is not stuck to the second piezoelectric anti-stiction structure124b. In such embodiments, the bias circuitry602may provide a corresponding one or more bias signals606to the MEMS device100. For example, the bias circuitry602may provide the first bias signal606ato the first electrode126ato deform the first piezoelectric structure128a. In other such embodiments, the bias circuitry602may provide the one or more bias signals606to the MEMS device100. For example, the bias circuitry602may provide the first bias signal606ato the first electrode126ato deform the first piezoelectric structure128aand the second bias signal606bto the second electrode126bto deform the second piezoelectric structure128b.

In some embodiments, an integrated chip (IC) comprises the system600. In other embodiments, a first IC may comprise the MEMS device100, and a second IC different than the first IC may comprise the bias circuitry602and/or the measurement circuitry604. In yet other embodiments, the first IC may comprise the MEMS device100, the second IC may comprise the bias circuitry602, and a third IC different than the first IC and the second IC may comprise the measurement circuitry604. In some embodiments, the bias circuitry602comprises one or more of the one or more semiconductor devices104(see, e.g.,FIG.5). In further embodiments, the measurement circuitry604comprises one or more of the one or more semiconductor devices104. In yet further embodiments, the bias circuitry602and the measurement circuitry604may be disposed on/over a same semiconductor substrate (e.g., the first semiconductor substrate102).

FIGS.7-22illustrate a series of cross-sectional views of some embodiments for forming the MEMS device100ofFIG.5.

As shown inFIG.7, a portion of an interconnect structure108is disposed in a lower ILD structure110and over a first semiconductor substrate102. Further, one or more semiconductor devices104are disposed on/in the first semiconductor substrate102. In some embodiments, a method for forming the structure illustrated inFIG.7comprises forming the one or more semiconductor devices104by forming pairs of source/drain regions in the first semiconductor substrate102(e.g., via ion implantation). Thereafter, gate dielectrics and gate electrodes are formed over the first semiconductor substrate and between the pairs of source/drain regions (e.g., via deposition/growth processes and etching processes). A first ILD layer is then formed over the one or more semiconductor devices104, and contact openings are formed in the first ILD. A conductive material (e.g., W) is formed on the first ILD layer and in the contact openings. Thereafter, a planarization process (e.g., chemical-mechanical polishing (CMP)) is performed into the conductive material to form conductive contacts (e.g., metal contacts) in the first ILD layer.

A second ILD layer is then formed over the first ILD layer and the conductive contacts, and first conductive line trenches are formed in the second ILD layer. A conductive material (e.g., Cu) is formed on the second ILD layer and in the first conductive line trenches. Thereafter, a planarization process (e.g., CMP) is performed into the conductive material to form a conductive line (e.g., metal 1) in the second ILD. A third ILD layer is then formed over the second ILD layer and the conductive line, and conductive via openings are formed in the third ILD layer. A conductive material (e.g., Cu) is formed on the third ILD layer and in the conductive via openings. Thereafter, a planarization process (e.g., (CMP) is performed into the conductive material to form conductive vias (e.g., metal vias) in the third ILD. The above processes for forming the conductive line and the conductive vias may be repeated any number of times. In some embodiments, the above layers and/or structures may be formed using a deposition or growth process such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, sputtering, electrochemical plating, electroless plating, some other deposition or growth process, or a combination of the foregoing.

As shown inFIG.8, a first conductive layer802is formed over the lower ILD structure110and the portion of the interconnect structure108. In some embodiments, a process for forming the first conductive layer802comprises depositing the first conductive layer802on the lower ILD structure110and the portion of the interconnect structure108. The first conductive layer802may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In further embodiments, the first conductive layer802may comprise, for example, Cu, Al, TiN, AlCu, some other conductive material, or a combination of the foregoing.

In some embodiments, the first conductive layer802comprises multiple layers. For example, the first conductive layer may comprise a first layer (e.g., TiN), a second layer (e.g., AlCu) disposed over and on the first layer, and a third layer (e.g., TiN) disposed over and on the second layer. In such embodiments, a process for forming the first conductive layer802may comprise depositing the first layer on the lower ILD structure110and the portion of the interconnect structure108, the second layer on the first layer, and the third layer on the second layer.

As shown inFIG.9, a second conductive layer902is formed over the first conductive layer802. In some embodiments, a process for forming the second conductive layer902comprises depositing the second conductive layer902on the first conductive layer802. The second conductive layer902may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In further embodiments, the second conductive layer902may comprise, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, Ru, some other conductive material, or a combination of the foregoing.

Also shown inFIG.9, a first piezoelectric layer904is formed over the second conductive layer902. In some embodiments, a process for forming the first piezoelectric layer904comprises depositing the first piezoelectric layer904on the second conductive layer902. The first piezoelectric layer904may be deposited or grown by, for example, sputtering, a spin-on process, CVD, PVD, ALD, molecular-beam epitaxy, some other deposition or growth process, or a combination of the foregoing. In further embodiments, the first piezoelectric layer904may comprise, for example, PZT, ZnO, BaTiO3, KNbO3, Na2WO3, Ba2NaNb5O5, Pb2KNb5O15, La3Ga5SiO14, GaPO4, LiNbO3, LiTaO3, some other piezoelectric material, or a combination of the foregoing.

Also shown inFIG.9, a third conductive layer906is formed over the first piezoelectric layer904. In some embodiments, a process for forming the third conductive layer906comprises depositing the third conductive layer906on the first piezoelectric layer904. The third conductive layer906may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In further embodiments, the third conductive layer906may comprise, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, Ru, some other conductive material, or a combination of the foregoing. In embodiments in which the dielectric structures202are disposed on the piezoelectric structures128, respectively, the third conductive layer906may not be formed over the first piezoelectric layer904.

As shown inFIG.10, a first plurality of piezoelectric anti-stiction structures124are formed over the first conductive layer802. In some embodiments, a process for forming the piezoelectric anti-stiction structures124comprises forming a masking layer (not shown) (e.g., a positive/negative photoresist) on the third conductive layer906(see, e.g.,FIG.9). Thereafter, the third conductive layer906, the first piezoelectric layer904, and the second conductive layer902(see, e.g.,FIG.9) are exposed to an etchant (e.g., a wet/dry etchant). The etchant removes unmasked portions of the third conductive layer906, thereby forming a plurality of conductive structures130on the first piezoelectric layer904; unmasked portions of the first piezoelectric layer904, thereby forming a plurality of piezoelectric structures128on the second conductive layer902; and unmasked portions of the second conductive layer902, thereby forming a plurality of electrodes126on the first conductive layer802. Subsequently, the masking layer may be stripped away. It will be appreciated that one or more etchants and/or masking layers may be utilized to form the piezoelectric anti-stiction structures124.

As shown inFIG.11, an upper conductive line120of the interconnect structure108is formed. In some embodiments, a process for forming the upper conductive line120comprises forming a masking layer (not shown) on the first conductive layer802and covering the piezoelectric anti-stiction structures124(see, e.g.,FIG.10). Thereafter, the first conductive layer802is exposed to an etchant. The etchant removes unmasked portions of the first conductive layer802, thereby forming the upper conductive line120. Subsequently, the masking layer may be stripped away.

As shown inFIG.12, an upper ILD layer1202is formed over the upper conductive line120and over the piezoelectric anti-stiction structures124. The upper ILD layer1202may be formed with a substantially planar upper surface. In some embodiments, a process for forming the upper ILD layer1202comprises depositing the upper ILD layer1202on the upper conductive line120and the piezoelectric anti-stiction structures124. The upper ILD layer1202may be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing. In further embodiments, a planarization process (e.g., CMP) may be performed into the upper ILD layer1202to planarize the upper surface of the upper ILD layer1202. The upper ILD layer1202may comprise a low-k dielectric, (e.g., a dielectric material with a dielectric constant less than about 3.9), an oxide (e.g., SiO2), or the like. It will be appreciated that, in some embodiments, the upper ILD layer1202may comprise one or more stacked ILD layers, which may respectively comprise a low-k dielectric, an oxide, or the like.

Also shown inFIG.12, an upper conductive via502is formed in the upper ILD layer1202. The upper conductive via502is formed extending through the upper ILD layer1202to the upper conductive line120. In some embodiments, a process for forming the upper conductive via502comprises forming a masking layer (not shown) on the upper ILD layer1202. Thereafter, the upper ILD layer1202is exposed to an etchant to remove unmasked portions of the upper ILD layer1202, thereby forming an opening (not shown) in the upper ILD layer1202. A conductive layer (not shown) is then deposited on the upper ILD layer1202and in the opening. In some embodiments, the conductive layer comprises, for example, Cu, Al, W, or the like. In further embodiments, the conductive layer may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. Thereafter, a planarization process (e.g., CMP) is performed into the conductive layer, thereby forming the upper conductive via502.

As shown inFIG.13, an upper ILD structure112is formed over the lower ILD structure110. In some embodiments, a process for forming the upper ILD structure112comprises forming a first opening1302in the upper ILD layer1202that exposes the piezoelectric anti-stiction structures124. In some embodiments, a process for forming the first opening1302comprises forming a masking layer (not shown) on the upper ILD layer1202and the upper conductive via502. Thereafter, the upper ILD layer1202is exposed to an etchant to remove unmasked portions of the upper ILD layer1202, thereby forming the first opening1302. In further embodiments, formation of the upper ILD structure112completes formation of an ILD structure106.

In embodiments in which the dielectric structures202are disposed on the piezoelectric structures128, respectively, the dielectric structures202may be formed during or after formation of the upper ILD structure112. For example, the dielectric structures202may be formed during formation of the upper ILD structure112by selectively forming the first opening1302(e.g., via multiple masking layers and etch processes), so that portions of the upper ILD layer1202remain on the piezoelectric structures128, respectively, as the dielectric structures202. In another example, the dielectric structures202may be formed after formation of the upper ILD structure112by depositing a dielectric layer onto the exposed piezoelectric structures128, and selectively etching the dielectric layer to form the dielectric structures202on the piezoelectric structures128, respectively.

As shown inFIG.14, a second semiconductor substrate114is bonded to the upper ILD structure112. In some embodiments, bonding the second semiconductor substrate114to the upper ILD structure112forms a first lower portion of a cavity118. In further embodiments, the second semiconductor substrate114may be bonded to the upper ILD structure112by, for example, direct bonding, hybrid bonding, eutectic bonding, or some other boning process. In yet further embodiments, after the second semiconductor substrate114is bonded to the upper ILD structure112, the second semiconductor substrate114may be thinned down by removing (e.g., via grinding or CMP) an upper portion of the second semiconductor substrate114.

As shown inFIG.15, a through-substrate via (TSV)512is formed extending through the second semiconductor substrate114to the interconnect structure108. In some embodiments, the TSV512is formed extending through the second semiconductor substrate114, the upper ILD structure112, and at least a portion of the lower ILD structure110. The TSV512may be formed extending through an isolation structure514disposed in the second semiconductor substrate114. In some embodiments, the isolation structure514is formed prior to the TSV512. In further embodiments, the isolation structure514may be formed by forming a trench in the second semiconductor substrate114and then filling the trench with a dielectric material. In yet further embodiments, a planarization process (e.g., CMP) may be performed into the dielectric material.

In some embodiments, a process for forming the TSV512comprises forming a masking layer (not shown) on the second semiconductor substrate114. Thereafter, the second semiconductor substrate114is exposed to an etchant that removes unmasked portions of the second semiconductor substrate114and underlying portions of the upper ILD structure112and lower ILD structure110, thereby forming a TSV opening that extends through the second semiconductor substrate114to the interconnect structure108. After the TSV opening is formed, a conductive layer (not shown) is deposited on the second semiconductor substrate114and in the TSV opening. In some embodiments, the conductive layer comprises, for example, Cu, Al, W, or the like. In further embodiments, the conductive layer may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. Thereafter, a planarization process (e.g., CMP) is performed into the conductive layer, thereby forming the TSV512. It will be appreciated that, in some embodiments, the TSV512may be one of multiple TSVs formed by the above process.

As shown inFIG.16, a lower bond ring510is formed on the second semiconductor substrate114and the TSV512. In some embodiments, a process for forming the lower bond ring510comprises forming a masking layer (not shown) over the second semiconductor substrate114and the TSV512. The masking layer comprises a plurality of openings that expose portions of the second semiconductor substrate114and the TSV512. A conductive layer (not shown) is then deposited on the masking layer and in the plurality of openings. In some embodiments, the conductive layer comprises, for example, Cu, Al, Au, Sn, some other bonding material, or a combination of the foregoing. In further embodiments, the conductive layer may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. Thereafter, a planarization process (e.g., CMP) is performed into the conductive layer, thereby forming the lower bond ring510. Subsequently, in some embodiments, the masking layer is stripped away.

As shown inFIG.17, a movable mass122is formed in the second semiconductor substrate114. In some embodiments, a process for forming the movable mass122comprises forming a masking layer (not shown) on the second semiconductor substrate114and the lower bond ring510. Thereafter, the second semiconductor substrate114is exposed to an etchant. The etchant removes unmasked portion(s) of the second semiconductor substrate114, thereby forming the movable mass122. Subsequently, in some embodiments, the masking layer is stripped away.

As shown inFIG.18, an upper bond ring508is formed on a third semiconductor substrate116. In some embodiments, the upper bond ring508is formed with a layout that corresponds to a layout of the lower bond ring510. In some embodiments, a process for forming the upper bond ring508comprises forming a masking layer (not shown) over the third semiconductor substrate116. The masking layer comprises a plurality of openings that expose portions of the third semiconductor substrate116. A conductive layer (not shown) is then deposited on the masking layer and in the plurality of openings. In some embodiments, the conductive layer comprises, for example, Cu, Al, Au, Sn, some other bonding material, or a combination of the foregoing. In further embodiments, the conductive layer may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. Thereafter, a planarization process (e.g., CMP) is performed into the conductive layer, thereby forming the upper bond ring508. Subsequently, in some embodiments, the masking layer is stripped away. In yet further embodiments, before the upper bond ring508is formed, one or more doped regions may be formed in the third semiconductor substrate116(e.g., via ion implantation).

As shown inFIG.19, a second opening1902is formed in the third semiconductor substrate116. In some embodiments, a process for forming the second opening1902comprises depositing a first masking layer1904(e.g., negative/positive photoresist) on the third semiconductor substrate116and covering the upper bond ring508. The third semiconductor substrate116is then exposed to an etchant. The etchant removes unmasked portions of the third semiconductor substrate116, thereby forming the second opening1902. In some embodiments, the first masking layer1904may be stripped away.

As shown inFIG.20, a fourth conductive layer2002is formed over the third semiconductor substrate116, the upper bond ring508, and the first masking layer1904. In some embodiments, the fourth conductive layer2002lines the second opening1902(see, e.g.,FIG.19). In further embodiments, a process for forming the fourth conductive layer2002comprises depositing the fourth conductive layer2002on the third semiconductor substrate116and the first masking layer1904. The fourth conductive layer2002may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In yet further embodiments, the fourth conductive layer2002may comprise, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, some other conductive material, or a combination of the foregoing.

Also shown inFIG.20, a second piezoelectric layer2004is formed over the fourth conductive layer2002. In some embodiments, a process for forming the second piezoelectric layer2004comprises depositing the second piezoelectric layer2004on the fourth conductive layer2002. The second piezoelectric layer2004may be deposited or grown by, for example, sputtering, a spin-on process, CVD, PVD, ALD, molecular-beam epitaxy, some other deposition or growth process, or a combination of the foregoing. In further embodiments, the second piezoelectric layer2004may comprise, for example, PZT, ZnO, BaTiO3, KNbO3, Na2WO3, Ba2NaNb5O5, Pb2KNb5O15, La3Ga5SiO14, GaPO4, LiNbO3, LiTaO3, some other piezoelectric material, or a combination of the foregoing.

Also shown inFIG.20, a fifth conductive layer2006is formed over the second piezoelectric layer2004. In some embodiments, a process for forming the fifth conductive layer2006comprises depositing the fifth conductive layer2006on the second piezoelectric layer2004. The fifth conductive layer2006may be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing. In further embodiments, the fifth conductive layer2006may comprise, for example, Pt, Ti, Cu, Au, Al, Zn, Sn, some other conductive material, or a combination of the foregoing. In embodiments in which the dielectric structures202are disposed on the piezoelectric structures128, respectively, the fifth conductive layer2006may not be formed over the second piezoelectric layer2004.

As shown inFIG.21, a second plurality of piezoelectric anti-stiction structures124are formed over the third semiconductor substrate116. In some embodiments, the piezoelectric anti-stiction structures124are formed within the second opening1902(see, e.g.,FIG.19). In some embodiments, a process for forming the piezoelectric anti-stiction structures124comprises forming a second masking layer (not shown) on the fifth conductive layer2006(see, e.g.,FIG.20). Thereafter, the fifth conductive layer2006, the second piezoelectric layer2004, and the fourth conductive layer2002(see, e.g.,FIG.20) are exposed to an etchant. The etchant removes unmasked portions of the fifth conductive layer2006, thereby forming a plurality of conductive structures130on the second piezoelectric layer2004; unmasked portions of the second piezoelectric layer2004, thereby forming a plurality of piezoelectric structures128on the fourth conductive layer2002; and unmasked portions of the fourth conductive layer2002, thereby forming a plurality of electrodes126on the third semiconductor substrate116.

As shown inFIG.22, the third semiconductor substrate116is bonded to the second semiconductor substrate114, thereby forming an upper portion of the cavity118. In some embodiments, the cavity118is formed as a sealed cavity. In further embodiments, a process for bonding the third semiconductor substrate116to the second semiconductor substrate114comprises bonding the upper bond ring508to the lower bond ring510. The upper bond ring508may be bonded to the lower bond ring510by, for example, eutectic bonding. It will be appreciated that the third semiconductor substrate116may be bonded to the second semiconductor substrate114via other bonding processes (e.g., direct bonding, hybrid bonding, etc.). In yet further embodiments, after the third semiconductor substrate116is bonded to the second semiconductor substrate114, formation of the MEMS device100is complete.

FIG.23illustrates a flowchart2300of some embodiments of a method for forming a MEMS device comprising a piezoelectric anti-stiction structure. While the flowchart2300ofFIG.23is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At act2302, a first semiconductor substrate is provided having a lower interlayer dielectric (ILD) structure disposed on the first semiconductor substrate.FIG.7illustrates a cross-sectional view of some embodiments corresponding to act2302.

At act2304, a plurality of piezoelectric anti-stiction structures are formed over the lower ILD structure and the first semiconductor substrate.FIGS.8-10illustrate a series of cross-sectional views of some embodiments corresponding to act2304.

At act2306, an upper ILD structure is formed over the lower ILD structure and the first semiconductor substrate, wherein the piezoelectric anti-stiction structures are disposed in an opening of the upper ILD structure.FIGS.11-13illustrate a series of cross-sectional views of some embodiments corresponding to act2306.

At act2308, a second semiconductor substrate is bonded to the upper ILD structure, wherein the second semiconductor substrate extends across the opening to form a cavity, and wherein the piezoelectric anti-stiction structures are disposed in the cavity.FIG.14illustrates a cross-sectional view of some embodiments corresponding to act2308.

At act2310, a movable mass is formed in the second semiconductor substrate and over the piezoelectric anti-stiction structures.FIGS.15-17illustrate a series of cross-sectional views of some embodiments corresponding to act2310.

At act2312, a third semiconductor substrate is bonded to the second semiconductor substrate.FIGS.18-22illustrate a series of cross-sectional views of some embodiments corresponding to act2312.

In some embodiments, the present application provides a microelectromechanical system (MEMS) device. The MEMS device comprises a first dielectric structure disposed over a first semiconductor substrate, wherein the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and comprises a movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure comprises a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.

In some embodiments, the present application provides an integrated chip (IC). The IC comprises a microelectromechanical system (MEMS). The MEMS comprises: a semiconductor substrate; a movable mass spaced from the semiconductor; a cavity at least partially disposed between the semiconductor substrate and the movable mass, wherein opposite sidewalls of the movable mass are disposed between opposite sidewalls of the cavity; and a piezoelectric anti-stiction structure disposed on a surface of the cavity, wherein the piezoelectric anti-stiction structure comprises a piezoelectric structure and an electrode. Bias circuitry is electrically coupled to the electrode, wherein the bias circuitry is configured to provide a first voltage to the electrode.

In some embodiments, the present application provides a method for forming a microelectromechanical system (MEMS) device. The method comprises forming a first conductive layer on a lower interlayer dielectric (ILD) structure, wherein the lower ILD structure is disposed over a semiconductor substrate. A first conductive layer is formed on the lower ILD. A second conductive layer is formed on the first conductive layer. A piezoelectric layer is formed on the second conductive layer. The first piezoelectric layer and the second conductive layer are etched to form a piezoelectric structure and an electrode, respectively, wherein the piezoelectric structure is disposed on the electrode. The first conductive layer is etched to form the conductive line. An upper ILD structure is formed over the lower ILD structure, the conductive line, the electrode, and the piezoelectric structure. An opening is formed in the upper ILD structure that exposes the piezoelectric structure. A movable mass is formed over the upper ILD structure, wherein the movable mass is formed having opposite sidewalls disposed between opposite sidewalls of the opening.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.