Patent ID: 12254928

DESCRIPTION OF THE EMBODIMENTS

FIG.1is a circuit diagram illustrating a portion of a memory device10according to some embodiments of the present disclosure. Referring toFIG.1, the memory device10is a NAND flash memory device, and includes multiple memory banks. Each of the memory banks may include a plurality of memory blocks, which respectively include memory cells100arranged as an array. Some of the memory cells100in one of the memory blocks are shown inFIG.1.

Each memory cell100may be a flash transistor, and includes a channel structure and a gate structure coupled to the channel structure. The gate structure may include a floating gate, a tunneling dielectric layer, a control gate and an inter-gate dielectric layer. During a write operation, the control gate receives a write voltage, to induce a carrier channel along the channel structure. In addition, this write voltage results in a sufficient electric field, such that carriers in the channel structure tunnel through the tunneling dielectric layer to enter the floating gate, and are captured in the floating gate. Accordingly, the memory cell100being written has a greater threshold voltage, and may store a logic data “0”. In contrast, a memory cell100has not been written may be identified as storing a logic data “1”.

During a read operation, the control gate receives a read voltage. The read voltage is preliminarily set, such that the written memory cell100can not be turned on by the read voltage, whereas the memory cell100has not been written can be turned on by the read voltage. By sensing a channel current of a selected memory cell100, whether if the selected memory cell100is turned on can be identified. Accordingly, either the selected memory cell100stores the logic data “0” or the logic data “1” can be identified.

The memory cells10in each memory block of the memory device10are arranged along strings. The memory cells100in each cell string ST are serially connected. Specifically, the memory cells100in each cell string ST are connected with one another by the channel structures, and opposite ends of the connected channel structure are coupled to a bit line BL and a source line CSL via a drain select transistor DST and a source select transistor SST, respectively. The cell strings ST may be connected to respective bit lines BL. For instance, the bit lines BL may include bit lines BL0to BL3. In addition, multiple ones of the cell strings ST may share the same source line CSL.

Further, the memory cells100in each cell string ST may be connected to respective word lines WL via the control gates. For instance, the word lines WL may include word lines WL0to WLn. Moreover, the memory cells100from multiple ones of the cell strings ST and arranged along the same row may share the same word line WL. Similarly, the drain select transistors DST arranged along an additional row are connected to a drain select line DSL by gate terminals, and the source select transistors CST arranged along another additional row are connected to a source select line SSL by gate terminals.

FIG.2is a flow diagram illustrating a method for operating the memory array10, according to some embodiments of the present disclosure. Referring toFIG.2, the operation method of the memory device10includes cycles each including a write operation S200, a read operation S210and an erase operation S220. The write operation S200may include multiple write steps S202. Multiple ones of the memory cells100connected along one of the word lines WL may be selected for writing during each of the write steps S202. Specifically, during each write step S202, a write voltage may be provided to a selected one of the word lines WL. In addition, multiple ones of the bit lines BL may be coupled to a bias voltage, to form a voltage difference between the selected bit lines BL and the source line CSL coupled to a reference voltage. By asserting the drain select line DSL and the source select line SSL to turn on the drain select transistor DST and the source select transistor SST, the channel structures of the cell strings ST intersecting the selected bit lines BL can be connected to the selected bit lines BL and the source line CSL by opposite ends, and a voltage difference is established at opposite ends of each of these channel structures. Accordingly, the memory cells100connected to the selected word lines WL, the selected bit lines BL and the source line CSL are turned on, and capture carriers to result in a relatively high threshold voltage.

Following each of the write steps S202, a write verification step S204is performed, to verify if threshold voltages of the memory cells100being written during the latest write step S202reach a pre-determined value. If the threshold voltages are higher than the pre-determined value, the latest write step S202is identified as an effective write step, and the next write step S202can be performed. On the other hand, if the threshold voltages do not reach the per-determined value, then the cycle including the latest write step S202and the following write verification step S204is repeated by increasing the write voltage, till the threshold voltages of the written memory cells100exceed the pre-determined value.

During each write verification step S204, a bias voltage is provided to the bit lines BL corresponding to the memory cells100being written in the latest write step S202, and the drain select transistors DST and the source select transistors SST are turned on by asserting the drain select line DSL and the source line CSL. Accordingly, the connected channel structures of the cell strings ST including the targeted memory cells100(i.e., the memory cells100being written in the latest write step S202) are coupled to the corresponding bit lines BL and the source line CSL, and a voltage difference is provided at opposite ends of each of these channel structures. In addition, a write verification voltage is provided to the word line WL connected to the targeted memory cells100, and a pass voltage is provided to other word lines WL, to ensure that other memory cells100in these memory strings ST can be turned on. If the threshold voltages of the targeted memory cells100are greater than the write verification voltage, the targeted memory cells100would not be turned on, and very limited current can be sensed on the channel structures of these memory strings ST. In this case, the latest write step S202is identified as effective, and the write operation S200can proceed to the next write step S202. On the other hand, if the threshold voltages of the targeted memory cells100are lower than the write verification voltage, the targeted memory cells100would be turned on, and greater current can be sensed on the channel structures of these memory strings ST. In this case, the latest write step S202is identified as ineffective, and the cycle consists of the latest write step S202and the following write verification step S204is repeated by increasing the write voltage, till the threshold voltages of the written memory cells100exceed the write verification voltage.

As the write operation S200is completed, the read operation S210may be performed. During each read operation S210, a plurality of the memory cells100connected to one of the word lines WL can be selected for reading. A method for reading the targeted memory cells100is similar to the method for performing write verification on selected memory cells100. Specifically, in order to read the targeted memory cells100, a bias voltage is provided to the bit lines BL corresponding to the targeted memory cells100, and the drain select transistors DST and the source select transistors SST are turned on by asserting the drain select line DSL and the source line CSL. Accordingly, the connected channel structures of the cell strings ST including the targeted memory cells100are coupled to the corresponding bit lines BL and the source line CSL, and a voltage difference is provided at opposite ends of each of these channel structures. In addition, a read voltage is provided to the word line WL connected to the targeted memory cells100, and a pass voltage is provided to other word lines WL, to ensure that other memory cells100in these memory strings ST can be turned on. If the threshold voltage of one of the targeted memory cells100is greater than the read voltage, this targeted memory cell100would not be turned on, and very limited current can be sensed on the channel structure of the corresponding memory string ST. In this case, it can be identified that this targeted memory cell100has been written and stores logic data “0”. On the other hand, if the threshold voltage of one of the targeted memory cells100is lower than the write verification voltage, this targeted memory cell100would be turned on, and greater current can be sensed on the channel structure of the corresponding memory string ST. In this case, it can be identified that this targeted memory cell100is not written, and stores logic data “1”.

Prior to the next write operation S200, the erase operation S220is performed. Specifically, one of the memory blocks may be selected for each erase operation S200. As an example, the memory block including the memory cells100shown inFIG.1is targeted in an erase operation S220. In this example, all of the bit lines and the source line CSL are coupled to a ground voltage, and the drain select transistors DST as well as the source select transistors SST are turned on by asserting the drain select line DSL and the source select line SSL. Further, all of the word lines WL are coupled to an erase voltage opposite to the write voltage in terms of polarity. As a result, charges are removed from the floating gates of all of the memory cells100. Accordingly, all of the memory cells100have a relative low threshold voltage, and represent logic data “1”. After performing the erase operation S220, the erased memory block can be subjected to a next cycle of the write operation S200, the read operation S210and the erase operation S220.

Further, each write step S202in a write operation S200is performed on a single page. That is, multiple ones of the memory cells100connected to a single word line WL are selected for writing in each write step S202. After all of the memory cells100in a page that are assigned to be written have been subjected to writing, the writing can proceed to next page. More particularly, multiple write steps S202in a write operation S200are performed on pages of the memory cells100by following arrangement sequence of the word lines WL. As an example, writing of the memory cells100connected to the word line WLnis followed by writing of the memory cells100connected to the word line WLn-1. Thereafter, the memory cells100connected to the word line WLn-2, the memory cells100connected to the word line WLn-3, . . . , and the memory cells100connected to the word line WL0are sequentially subjected to writing.

Moreover, batch writing is performed to the memory cells100connected to the same word line WL. Specifically, for the memory cells100connected to the same word line WL, the memory cells100connected to the even-numbered bit lines BL may be written at first, then the memory cells100connected to the odd-numbered bit lines BL may be written afterwards. Alternatively, for the memory cells100connected to the same word line WL, the memory cells100connected to the odd-numbered bit lines BL may be written at first, then the memory cells100connected to the even-numbered bit lines BL may be written afterwards.

According to the write sequence, one of adjacent pages of the memory cells100is subjected to writing before or after the other, and the memory cells100in the same page are written in groups. When spacing between adjacent memory cells100is very short, writing one of the memory cells100may affects other memory cells100arranged nearby.

The memory cells100a,100bare used for describing interference between the memory cells100in the same page. The memory cells100a,100bare connected to the same word line WLn-2, but the memory cell100ais connected to the bit line BL2, while the memory cell100bis connected to the bit line BL3. Assumed that the even-numbered memory cells100in this page are subjected to an earlier write step, and the odd-numbered memory cells100in this page are subjected to a later write step. That is, the memory cell100amay be written and verified before the write and the write verification of the memory cell100b. Since the memory cells100a,100bare connected to the same word line WLn-2, a threshold voltage of the memory cell100amay be unintentionally raised when the memory cell100bis subjected to writing, and vice versa. Nevertheless, since the steps of write and write verification of the memory cell100bare later than the steps of write and write verification of the memory cell100a, the threshold voltage sensed during write verification of the memory cell100bwould be a result of the writing of the memory cell100band the unintentional coupling during writing of the memory cell100a, whereas the threshold voltage sensed during write verification of the memory cell100amay not be resulted from the unintentional coupling during writing of the memory cell100b. As a consequence, the threshold voltage sensed from the memory cell100aduring a later read operation may be higher than the threshold voltage sensed during write verification of the memory cell100a, and the threshold voltage sensed from the memory cell100bduring a later read operation may be rather close to the threshold voltage sensed during write verification of the memory cell100b. In other words, as compared to the memory cell100b, the memory cell100awould be resulted in a greater difference between the threshold voltage sensed during write verification and the threshold voltage sensed during reading.

In addition, the memory cells100a,100care used for describing interference between the memory cells100in the same cell string ST. The memory cells100a,100care both connected to the bit line BL2, but the memory cell100ais connected to the word line WLn-2, whereas the memory cell100cis connected to the word line WLn-3. The memory cell100amay be written and verified before the write and the write verification of the memory cell100c. The threshold voltage of the memory cell100cwould be raised as a result of writing the memory cell100c, and a transconductance on the channel structure of the cell string ST corresponding to the memory cells100c,100cwould be further lowered. As a consequence, channel current sensed during reading of the memory cell100awould be lower than channel current sensed during write verification of the memory cell100a. Equivalently, the threshold voltage sensed from the memory cell100aduring reading would be higher than the threshold voltage sensed from the memory cell100aduring write verification. On the other hand, the threshold voltage sensed from the memory cell100cduring reading may be rather close to the threshold voltage sensed from the memory cell100cduring write verification.

Therefore, for the memory cells100in the same cell string ST, the memory cells100written in a later write step (e.g., the memory cell100c) may affect the memory cells100written in an earlier write step (e.g., the memory cell100a). Further, as described, for the memory cells100in the same page, the memory cells100written in an earlier write step may have a greater threshold voltage variation, as compared to the memory cells100written in a later write step. For these reasons, in each page, the memory cells100being written in an earlier write step may also be referred to as high cross-coupling memory cells. As compared to a cell string ST having less high cross-coupling memory cells, a cell string ST with more high cross-coupling memory cells would be worse in terms of read disturb. Further, if an amount of the high cross-coupling memory cells greatly varies among the cell strings ST, the read disturb may be unevenly distributed, which may cause difficulties in reading. Moreover, the high cross-coupling memory cells may interfere with each other (further raising threshold voltage). Therefore, when each high cross-coupling memory cell is surrounded by more of other high cross-coupling memory cells, read disturb among the high cross-coupling memory cells becomes worse.

FIG.3is a schematic diagram illustrating a write sequence according to some embodiments of the present disclosure. It should be appreciated that, only a portion of the memory cells100in a memory block of the memory device10are used for illustrating the write sequence, and drain select transistors DST, source select transistors SST and the source line CSL connected to these memory cells100are omitted from illustration.

Referring toFIG.3, each memory cell100in each page can be grouped as a memory cell100written in an earlier write step (also referred to as a high cross-coupling memory cell100s) or a memory cell100written in a later write step, depending on either the connected bit line BL is odd-numbered or even-numbered. In terms of write sequence, each page of the memory cells100is identical with one of two adjacent pages of the memory cells100, but opposite to the other. In this way, a pattern of the write sequences of sequentially arranged pages of the memory cells may include repetitive sub-patterns, each formed by the write sequences of four serially arranged pages of the memory cells100.

For instance, for the memory cells100connected to the word line WLn, the memory cells100connected to the even-numbered bit lines BL (e.g., including the bit lines BL0, BL2) are written in an earlier write step, and the memory cells100connected to the odd-numbered bit lines BL (e.g., including the bit lines BL1, BL3) are written in a later write step. As a result, the memory cells100connected to the word line WL, and the bit lines BL0, BL2become two of the high cross-coupling memory cells100s.

After the memory cells100connected to the word line WLnhave been written, the memory cells100connected to the next word line WLn-1are subjected to batch writing. As a difference, for the memory cells100connected to the word line WLn-1, the memory cells100connected to the odd-numbered bit lines BL are written in an earlier write step, and the memory cells100connected to the even-numbered bit lines BL are written in a later write step. As a result, the memory cells100connected to the word line WLn-1and the bit lines BL1, BL3become two of the high cross-coupling memory cells100s.

Thereafter, the memory cells100connected to the word line WLn-2are subjected to batch writing, by using the write sequence identical with the write sequence applied to the memory cells100connected to the word line WLn-1. That is, for the memory cells100connected to the word line WLn-2, the memory cells100connected to the odd-numbered bit lines BL are written in an earlier write step, and the memory cells100connected to the even-numbered bit lines BL are written in a later write step. As a result, the memory cells100connected to the word line WLn-2and the bit lines BL1, BL3become two of the high cross-coupling memory cells100s.

Subsequently, the memory cells100connected to the word line WLn-3are subjected to batch writing, by using the write sequence opposite to the write sequence applied to the memory cells100connected to the word line WLn-2. That is, for the memory cells connected to the word line WLn-3, the memory cells100connected to the even-numbered bit lines BL are written in an earlier write step, and the memory cells100connected to the odd-numbered bit lines BL are written in a later write step. As a result, the memory cells100connected to the word line WLn-3and the bit lines BL0, BL2become two of the high cross-coupling memory cells100s.

Up to here, four serially arranged pages connected to the word lines WLn, WLn-1, WLn-2. WLn-3have been written. The write sequence applied to these four pages can be used for the next four pages of the memory cells100(including the page of the memory cells100connected to the word line WLn-5). As repeating multiple times, all of the memory cells100(that are assigned to be written) in a memory block of the memory device10can be written. That is, a pattern of the write sequences for the four serially arranged pages of the memory cells100(according to numbering of the connected word lines WL) can be one of repetitive sub-patterns for writing the entire memory block.

The write sequence for a page of the memory cells100can be indicated by the distribution of the high cross-coupling memory cells100sin this page. If the high cross-coupling memory cells100sin a page of the memory cells100are the memory cells connected to the even-numbered bit lines BL, then the memory cells100connected to the even-numbered bit lines BL in this page are written in an earlier write step, and the memory cells100connected to the odd-numbered bit lines BL in this page are written in a later write step. On the other hand, if the high cross-coupling memory cells100sin a page of the memory cells100are the memory cells connected to the odd-numbered bit lines BL, then the memory cells100connected to the odd-numbered bit lines BL in this page are written in an earlier write step, and the memory cells100connected to the even-numbered bit lines BL in this page are written in a later write step.

As shown inFIG.3, in terms of distribution of the high cross-coupling memory cells100s, each page of the memory cells100is identical with one of adjacent pages of the memory cells100, but different from the other adjacent page of the memory cells100. This indicates that each page of the memory cells100is identical in terms of write sequence with an adjacent page of the memory cells100, but opposite in terms of write sequence with the other adjacent page of the memory cells100. For instance, for the page of the memory cells100connected to the word line WLn-2, the high cross-coupling memory cells100sare the memory cells100connected to the odd-numbered bit lines BL (e.g., the bit lines BL1, BL3). The word line WLn-2is adjacent to and arranged between the word line WLn-1and the word line WLn-3. For the memory cells100connected to the word line WLn-1, the high cross-coupling memory cells100sare the memory cells100connected to the odd-numbered bit lines BL (e.g., the bit lines BL1, BL3). On the other hand, for the memory cells100connected to the word line WLn-3, the high cross-coupling memory cells100sare the memory cells100connected to the even-numbered bit lines BL (e.g., the bit lines BL2, BL4). This shows that the page of the memory cells100connected to the word line WLn-2is identical in term of write sequence with the page of the memory cells100connected to the word line WLn-1, but opposite in terms of write sequence with the page of the memory cells100connected to the word line WLn-3. Such distribution of the high cross-coupling memory cells100and pattern of write sequences are also shown in pages of the memory cells100connected to other word lines WL.

By applying the pattern of write sequences, an amount of the high cross-coupling memory cells100sin each cell string ST is close to an amount of the high cross-coupling memory cells100sin each of other cell strings ST. Specifically, a difference between an amount of the high cross-coupling memory cells100sin each cell string ST and an amount of the high cross-coupling memory cells100sin each of other cell strings ST is no greater than 1. As an example shown inFIG.3, each of the four cell strings ST connected to the bit lines BL0, BL1, BL2, BL3includes 3 high cross-coupling memory cells100s. In other examples that an amount of the cell pages is an odd number, a difference between an amount of the high cross-coupling memory cells100sin each cell string ST and an amount of the high cross-coupling memory cells100sin each of other cell strings ST could be 1. As a result of such distribution of the high cross-coupling memory cells100s, read disturb may be prevented from being concentrated in certain cell strings ST. Therefore, the memory cells100in each of the cell strings ST can be read out with higher accuracy.

Moreover, as compared to setting each cell page opposite in terms of write sequence to both of adjacent cell pages, using the write sequences according to embodiments of the present disclosure for performing writing on the memory device10may result that each high cross-coupling memory cell100sis surrounded by fewer of other high cross-coupling memory cells100s. Accordingly, interference between the high cross-coupling memory cells100scan be effectively reduced. Specifically, setting each cell page opposite in terms of write sequence to both of adjacent cell pages would result in each high cross-coupling memory cell surrounded by 4 nearest high cross-coupling memory cells. In contrast, using the write sequences according to embodiments of the present disclosure for performing writing on the memory device10may result that each high cross-coupling memory cell100sis surrounded by only 3 nearest high cross-coupling memory cells100s. For instance, as indicated by the region enclosed by a dashed line inFIG.3, the high cross-coupling memory cell100sconnected to the word line WLn-3and the bit line BL2is surrounded by 3 high cross-coupling memory cells100s, including 2 high cross-coupling memory cells100sconnected to the word line WLn-2and the bit lines BL1, BL3and 1 high cross-coupling memory cell100sconnected to the word line WLn-4and the bit line BL2. Each of other high cross-coupling memory cells100sis also surrounded by 3 nearest high cross-coupling memory cells100s.

As above, an operation method for a memory device is provided. The operation method includes performing write sequences to each memory block of the memory device. Each memory block of the memory device includes memory cells arranged in an array. Bit lines serially arranged and numbered are respectively connected to a cell string, and word lines serially arranged and numbered are respectively connected to a page of the memory cells. Each memory cells in each page can be grouped as a memory cell written in an earlier write step or a memory cell written in a later write step, depending on either the connected bit line is even-numbered or odd-numbered. As the write steps for writing a page of the memory cells (e.g., the page of the memory cells100connected to the word line WLn) are completed, cell writing proceeds to the next page of the memory cells (e.g., the page of the memory cells100connected to the word line WLn-1). In addition, each cell page is identical in terms of write sequence (indicating either the memory cells connected to the even-numbered bit lines or the memory cells connected to the odd-numbered bit lines are written in an earlier write step) with one of nearest two cell pages, but opposite in terms of write sequence with the other of the nearest two cell pages. In this way, the memory cells being written before the others in the same page are evenly distributed among the cell strings, thus read disturb can be avoided from being concentrated in certain cell strings. Further, as compared to setting each cell page opposite in terms of write sequence to both of adjacent cell pages, using the write sequences according to embodiments of the present disclosure may result that each of the memory cells being written before the others in each cell page is surrounded by fewer of other memory cells being written before the others in the same page. Accordingly, interference between the memory cells being written before the others in the same page can be effectively reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.