Patent ID: 12254939

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Implementations of the present disclosure are illustrated below through specific embodiments. Those skilled in the art can easily understand other advantages and efficacy of the present disclosure according to the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific implementations. Various modifications or variations can also be made on details in this specification based on different opinions and applications without departing from the spirit of the present disclosure.

It should be noted that, the figures provided in this embodiment merely illustrate the basic conception of the present disclosure schematically. Therefore, the figures only show components related to the present disclosure, and are not drawn according to the quantity, shapes and sizes of components during actual implementation. The pattern, quantity and ratio of components during actual implementation can be changed arbitrarily, and the component layout may also be more complex.

The present disclosure effectively overcomes various disadvantages in the prior arts and hence has high industrial usage value. The foregoing embodiments only illustrate the principle and efficacy of the present disclosure exemplarily, and are not meant to limit variations of the technique. Any person skilled in the art can make modifications on the foregoing embodiments without departing from the spirit and scope of the present disclosure. Accordingly, all equivalent modifications or variations completed by those with ordinary skill in the art without departing from the spirit and technical thinking disclosed by the present disclosure should fall within the scope of claims of the present disclosure.

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms, and should not be construed as being limited to the examples set forth herein; on the contrary, the provision of these embodiments makes the present disclosure more comprehensive and complete, and fully conveys the concept of the example embodiments to those skilled in the art. The drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures denote the same or similar parts, and thus their repeated description will be omitted.

Furthermore, the described features, structures or characteristics can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to give a sufficient understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known structures, methods, devices, implementations, or operations are not shown or described in detail to avoid overwhelming attention and obscure all aspects of the present disclosure.

In addition, the terms “first” and “second” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other instances, well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

In addition, the drawings are merely schematic illustrations of the present disclosure, and the same reference numerals in the drawings denote the same or similar parts, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the figures are functional entities, which do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

FIG.1is a schematic structural diagram of a memory structure according to an exemplary embodiment of the present disclosure.

Referring toFIG.1, the memory structure100may include:a plurality of memory arrays11arranged in parallel along the first direction and extending along the second direction, a sensitivity amplifier array extending along the second direction is arranged between every two memory arrays11, and the sensitivity amplifier array includes an odd-numbered sensitivity amplifier array12and the even-numbered sensitivity amplifier array13, the odd-numbered sensitivity amplifier array12and the even-numbered sensitivity amplifier array13are staggered along the first direction, the odd-numbered sensitivity amplifier array12is connected to the odd-numbered global signal line, and the even-numbered sensitivity amplifier array13is connected to the even-numbered global signal line. It can be known that the aforementioned first direction is the direction in which the bit lines extend, and the aforementioned second direction is the direction in which the word lines extend. The memory array11shown inFIG.1may be one rank (row), for example.

The spare memory array14is arranged on one side of the memory array11located at the edge in the first direction. A first sensitivity amplifier array15is arranged between the spare memory array14and the memory array11located at the edge. Both odd-numbered global signal lines and even-numbered global signal line are connected. Since the odd-numbered global signal lines and the even-numbered global signal line are simultaneously connected, the first sensitivity amplifier array15can simultaneously control the spare memory array14and the memory array11located at the edge. When it is detected that any memory array11is faulty, the first sensitivity amplifier array15can be controlled to read and write to the spare memory array14, so as to realize the replacement of the faulty memory array. When any odd-numbered sensitivity amplifier array12or even-numbered sensitivity amplifier array13is detected to be faulty, the first sensitivity amplifier array15can be used to replace the faulty sensitivity amplifier array.

Since the sensitivity amplifier array reads and writes half of the memory array, in one embodiment, two spare memory arrays14and two first sensitivity amplifier arrays14can be used to implement replacement of a failed memory array or a failed sensitivity amplifier array.

FIG.2is a schematic structural diagram of a memory structure in an embodiment of the present disclosure.

Referring toFIG.2, in one embodiment, the number of spare memory arrays14is two, which are respectively disposed beside the two memory arrays11located at the edge. Correspondingly, the number of the first sensitivity amplifier arrays15is also two. Referring to the embodiment shown inFIG.2, the number of the spare memory arrays14is the same as the number of the first sensitivity amplifier arrays15. When those skilled in the art set up more spare memory arrays14, the first sensitivity amplifier arrays15can be connected according to the above rules. It can be understood that when more than two spare memory arrays14are provided, other spare memory arrays14may be provided beside the spare memory arrays14shown inFIG.2. Same asFIG.1, the first sensitivity amplifier array15can be arranged either on the right side of the spare memory array14or on the left side of the spare memory array14, that is, the relative position of the first sensitivity amplifier array15and the spare memory array14. It can be interchanged, and the present disclosure does not make any special limitation to this.

In practical applications, the structure shown inFIG.1orFIG.2can realize the replacement of the faulty memory array when the memory array fails.

It can be determined that the memory array is faulty according to the detection result of the memory array detection circuit. For example, when a memory product is detected, the faulty memory array can be determined according to the memory array failure message generated by the detection; or, during the use of the memory product, it can be triggered in various ways (for example, timing or each power-on startup, etc.) to detect memory arrays to determine memory array failures.

Since a memory array usually has multiple memory sub-arrays (blocks), and each memory sub-array usually has multiple memory cells (cells), it can be determined how many memory cells or how many memory sub-arrays according to the general settings of the product, when there is a failure (e.g. 30% failure), the memory array is determined to be faulty. The embodiment of the present disclosure does not limit the specific trigger logic for judging the memory failure.

There can be one or more failed memory arrays. When the number of the failed memory arrays is less than half the number of the spare memory arrays, the spare memory arrays can be used to replace the failed memory arrays. When the number of failed memory arrays is more than or equal to one-half the number of spare memory arrays, the location of the failed memory array can be critical (e.g., middle or edge) or damaged (e.g., what percentage of memory cells or memory sub-array failure), determine which failed memory arrays to replace with spare memory arrays.

In order to further illustrate the replacement functions of the spare memory array14and the first sensitivity amplifier array15in the present disclosure, the connection relationship of the data lines in the exemplary embodiment of the present disclosure is described below with reference toFIG.3andFIG.4.

FIG.3is a schematic structural diagram of a memory structure in an embodiment of the present disclosure.

Referring toFIG.3, in one embodiment, each memory array11includes a plurality of memory sub-arrays111arranged along the second direction, the odd-numbered sensitivity amplifier array12includes a plurality of odd-numbered sensitivity amplifier sub-arrays121, and the even-numbered sensitive amplifier sub-arrays131. The even-numbered sensitivity amplifier array13includes a plurality of even-numbered sensitivity amplifier sub-arrays131, and the odd-numbered sensitivity amplifier sub-arrays121or the even-numbered sensitivity amplifier sub-arrays131correspond to the memory sub-array111.

Each odd-numbered sensitivity amplifier sub-arrays121is electrically connected to a plurality of odd-numbered global signal lines through an odd-numbered read-write conversion circuit, and all odd-numbered read-write conversion circuits corresponding to an odd-numbered sensitivity amplifier array12constitute an odd-numbered read-write conversion circuit array16; each even-numbered sensitivity amplifier sub-arrays131are electrically connected to a plurality of even-numbered global signal line through an even-numbered read-write conversion circuit, and all even-numbered read-write conversion circuits corresponding to one even-numbered sensitivity amplifier array13constitute an even-numbered read-write conversion array17.

The spare memory array14includes a plurality of first spare memory sub-arrays141, the first sensitivity amplifier array15includes a plurality of first sensitivity amplifier sub-arrays151, and each first spare memory sub-array141corresponds to a first sensitivity amplifier sub-array151. Each first sensitivity amplifier sub-array151is electrically connected to both the odd-numbered global signal line and the even-numbered global signal line through a spare read-write conversion circuit, and the spare read-write conversion circuit corresponding to the first sensitivity amplifier array15forms a spare read-write conversion array18. It can be understood that the odd-numbered read-write conversion array16is connected to the odd-numbered read control signal line and the odd-numbered write control signal line, and the even-numbered read-write conversion array17is connected to the even-numbered read control signal line and the even-numbered write control signal line. The spare read-write conversion array18is simultaneously connected to odd-numbered read control signal lines, odd-numbered write control signal lines, even-numbered read control signal lines, and even-numbered write control signal lines, each of which is not shown in the figure.

FIG.4is a schematic diagram of a memory array control circuit.

InFIG.4, the memory array control circuit mainly includes a row decoding and control circuit41(XDEC, X Decoder), a column decoding circuit42(YDEC, Y Decoder), a read amplifier circuit and a write drive circuit43. The column decoding circuit42is used for providing a column selection signal (CSL, Column Select). The read amplifier circuit and the write drive circuit43include a second sensitivity amplifier (SSA) and a write driver (write driver). Both the read amplifier circuit and the write driver circuit are connected to the global signal line YIO and the complementary global signal line YIO #. The global signal line YIO and the complementary global signal line YIO # appear in pairs, and a pair of global signal lines YIO and the complementary global signal line YIO # constitute a group of signals corresponding to the odd-numbered global signal lines shown inFIG.1,FIG.2orFIG.3line or a group of signal lines corresponding to the even-numbered global signal lines. For the relationship between the global signal lines and the memory array11, the odd-numbered sensitivity amplifier array12, the even-numbered sensitivity amplifier array13, the odd-numbered read-write conversion circuit array16and the even-numbered read-write conversion circuit array17, please refer to the partial enlargement on the right side ofFIG.4.

When a WL (Word Line) is selected by the XDEC line decoder and control circuit41, the data of the corresponding memory array11is transmitted to the odd-numbered sensitivity amplifier array12and the even-numbered sensitive amplifier array12located on both sides of the memory array. The amplifier array13is amplified by the odd-numbered sensitivity amplifier array12and the even-numbered sensitivity amplifier array13, and then written back to the memory cells connected to the selected WL. When the data needs to be changed or rewritten, the column decoding circuit42selects the corresponding sensitivity amplifier, and the data is transmitted from a set of YIO&YIO # global signal lines to a set of Ldat&Ldat # local signal lines through a read-write conversion circuit (lrwap), Write to the sensitivity amplifier and the connected memory unit corresponding to the read-write conversion circuit. When data is read out, the direction of data transmission is reversed. The YDEC column decoding circuit42selects the corresponding sensitivity amplifier, and the data is transmitted to a group of Ldat&Ldat # local signal lines, and then transmitted by the read-write conversion circuit (lrwap) connected to the sensitivity amplifier to a group of YIO&YIO # global signal lines, and finally amplified and output by the SSA in the read amplifying circuit and the write drive circuit43. When working, YIO&YIO # is a dual-phase paired mode, and the read or write modes are in opposite complementary polarities.

It can be seen that each odd-numbered read-write conversion circuit161inFIG.4is connected to odd-numbered global signal lines (eg YIOn+1, YIOn+3), complementary odd-numbered global signal lines (YIOn+1 #, YIOn+3 #) And a group of Ldat&Ldat # signal lines, a plurality of odd-numbered read-write conversion circuits161constitute an odd-numbered read-write conversion circuit array16; each even-numbered read-write conversion circuit171connects to a complementary even-numbered global signal line (YIOn #, YIOn+2 #), a group of Ldat&Ldat # signal lines, and a plurality of even-numbered read-write conversion circuits171constitute an even-numbered read-write conversion circuit array17. The above n is an even number greater than or equal to zero. In some embodiments, the odd-numbered read-write conversion circuit161may not be connected to the complementary odd-numbered global signal line, that is, if the complementary odd-numbered global signal line is not provided. Similarly, the even-numbered read-write conversion circuit171may also not be connected to the complementary even-numbered signal line. The odd numbered global signal line, that is, the complementary even numbered global signal line is not provided, which is not specifically limited in the present disclosure.

From the perspective of the memory unit, the odd-numbered sensitivity amplifier array12or the even-numbered sensitivity amplifier array13includes multiple sensitivity amplifier sub-arrays, and each sensitivity amplifier sub-array controls half of the memory arrays11on the left and right sides. The lines of the array are bit lines (BL, Bit Line). It can be known fromFIG.4in combination withFIG.3that half of the memory cells in the spare memory array14are controlled by the first sensitivity amplifier array15connected to the spare memory array14. Replacing a complete memory array11can be achieved by using the two first sensitivity amplifier arrays15to control the two spare memory arrays14respectively.

Specifically, when a memory array11fails, control a first sensitivity amplifier array15to perform data exchange with the odd-numbered global signal lines connected to the odd-numbered sensitivity amplifier array corresponding to the faulty memory array, so as to use a spare memory array14Realize the replacement of the memory cells of half of the faulty memory arrays; control another first sensitivity amplifier array15to perform data exchange with the even-numbered global signal lines connected to the even-numbered sensitivity amplifier arrays corresponding to the faulty memory array, so as to use another spare memory array14enables replacement of the memory cells of the other half of the failed memory array.

In addition, the embodiment of the present disclosure can also use the first sensitivity amplifier array15and the spare memory array14to replace the two memory arrays11affected by the faulty sensitivity amplifier array when the sensitivity amplifier array is damaged.

When a sensitivity amplifier array (whether it is an odd-numbered sensitivity amplifier array12or an even-numbered sensitivity amplifier array13) is damaged, half of the memory cells in the two memory arrays11it controls are affected. Therefore, when it is determined that the sensitivity amplifier array is faulty, one spare memory array14can be used to replace half of the memory cells in the memory array11that cannot function properly due to the faulty sensitivity amplifier, and another spare memory array14can be used to replace half of the memory cells that are affected by the faulty sensitivity amplifier. The other half of the memory cells in the memory array11in normal operation.

During specific implementation, if a certain whole sensitivity amplifier array is faulty, for example, the odd-numbered sensitivity amplifier array12fails, the sensitivity amplifier s in the array exchange data with the odd-numbered global signal lines, so when replacing them, Half of the two first sensitivity amplifier arrays15corresponding to the two spare memory arrays14connected to the spare memory array14are used as odd-numbered sensitivity amplifier arrays, and carry out data with the odd-numbered global signal lines corresponding to the faulty odd-numbered sensitivity amplifier arrays12exchange. Only when it is judged that data exchange with an affected memory array11is required through the faulty sensitivity amplifier array, the word line WL is set to select the memory array11and a corresponding spare memory array14, and control the connection of the spare memory array14. The first sensitivity amplifier array15and the odd-numbered global signal line connected to the faulty sensitivity amplifier realize data exchange (the memory array11connected to the first sensitivity amplifier15is not selected at this time); when exchanging data with another affected memory array11, set the word line WL to select the memory array11and its corresponding other spare memory array14, and control the first sensitivity amplifier array15connected to the spare memory array14to be connected with the fault. The odd-numbered global signal lines connected to the sensitivity amplifier s realize data exchange. The connection between the spare memory array14and the word line WL is the same as the connection between the memory array11and the word line WL.

In the same way, if the even-numbered sensitivity amplifier array13fails and is used for replacement, the half of the connection between the two first sensitivity amplifier arrays15corresponding to the two spare memory array14, and the spare memory array14also needs to be used as an even-numbered sensitivity amplifier array, and perform data exchange with the even-numbered global signal line corresponding to the faulty even-numbered sensitivity amplifier array13.

As can be seen from the above description, the first sensitivity amplifier array15must support both the functions of being an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array. Therefore, the control mode of each sensitivity amplifier in the first sensitivity amplifier array15needs to be modified, that is, the spare read-write conversion circuit needs to be modified.

FIG.5is a schematic diagram of the working principle of the spare read-write conversion circuit in the embodiment of the present disclosure.

Referring toFIG.5, a pair of local signal lines Ldat and complementary local signal lines Ldat # connected to the odd-numbered read-write conversion circuit161or the even-numbered read-write conversion circuit171are connected to an odd-numbered sensitivity amplifier sub-arrays121or an even-numbered sensitive amplifier sub-array131. In the even-numbered sensitivity amplifier sub-arrays131, each read-write conversion circuit is connected to a pair of local signal lines Ldat and complementary local signal lines Ldat # and a pair of YIO and YIO # signal lines. The odd-numbered read-write conversion circuit161is connected to the odd-numbered global signal line YIOn+1 and the complementary odd-numbered global signal line YIOn+1 #, and the even-numbered read-write conversion circuit171is connected to the even-numbered global signal line YIOn and the complementary even-numbered global signal line YIOn #. In some embodiments, each read-write conversion circuit may only be connected to the YIO signal line, that is, in some embodiments, the odd-numbered read-write conversion circuit161may also not be connected to the complementary odd-numbered global signal line YIOn+1 #. In principle, the even-numbered read-write conversion circuit171may also not be connected to the complementary even-numbered global signal line YIOn #, which is not specifically limited in the present disclosure.

A pair of signal lines of the spare read-write conversion circuit181are connected to a spare sensitivity amplifier sub-array151. A plurality of spare read-write conversion circuits181corresponding to one first sensitivity amplifier array15constitute a spare read-write conversion array18. The spare read-write conversion circuit181connects the odd-numbered global signal lines and the even-numbered global signal line at the same time, so that the spare memory array14can be controlled to flexibly replace the faulty memory array, or replace the memory array affected by the faulty sensitivity amplifier array.

FIG.6is a schematic circuit diagram of the spare read-write conversion circuit181in the spare read-write conversion circuitry in the embodiment of the present disclosure.

Referring toFIG.6, the spare read-write conversion circuit181may include:a even-numbered read control circuit61connected to the even-numbered global signal line YIOn, the even-numbered read control signal line Rdn and the complementary local signal line Ldat #;

The even-numbered write control circuit62is connected to the even-numbered global signal line YIOn, the even-numbered write control signal line Wrn, the complementary local signal line Ldat #, and the local sign line Ldat,an odd-numbered read control circuit63connected to the odd-numbered global signal line YIOn+1, the odd-numbered read control signal line Rdn+1 and the local signal line Ldat; andan odd-numbered write control circuit64connected to the odd-numbered global signal line YIOn+1, the odd-numbered write control signal line Wrn+1, the complementary local signal line Ldat #, and the local signal line Ldat.

In the embodiment shown inFIG.6, the even-numbered read control circuit61includes a first N-type transistor M1 and a second N-type transistor M2, the drain of the first N-type transistor M1 is connected to the odd-numbered global signal line YIOn+1, and the gate is connected to the complementary local signal line Ldat #, the drain of the second N-type transistor M2 is connected to the source of the first N-type transistor M1, the gate of the second N-type transistor M2 is connected to the even-numbered read control signal line Rdn, and the source of the second N-type transistor M2 is grounded.

The even-numbered write control circuit62includes a third N-type transistor M3, a fourth N-type transistor M4, and a fifth N-type transistor M5. The first end of the third N-type transistor M3 is connected to the odd-numbered global signal line YIOn+1, and the second end is connected to the local signal line Ldat, the gate is connected to the even-numbered write control signal line Wrn, the drain of the fourth N-type transistor M4 is connected to the local signal line Ldat, the gate of the fourth N-type transistor M4 is connected to the odd-numbered global signal line YIOn+1, and the drain of the fifth N-type transistor M5 is connected to the source of the fourth N-type transistor M4, the gate of the fifth N-type transistor M5 is connected to the even-numbered write control signal line Wrn, and the source of the fifth N-type transistor M5 is grounded.

The odd-numbered read control circuit63includes: a sixth N-type transistor M6 and a seventh N-type transistor M7, the drain of the sixth N-type transistor M6 is connected to the even-numbered global signal line YIOn, the gate of the sixth N-type transistor M6 is connected to the local signal line Ldat, and the drain of the seventh N-type transistor M7 is connected to the source of the sixth N-type transistor M6, the gate is connected to the odd-numbered read control signal line Rdn+1, and the source is grounded.

The odd-numbered write control circuit64includes an eighth N-type transistor M8, a ninth N-type transistor M9, and a tenth N-type transistor M10. The first end of the eighth N-type transistor M8 is connected to the even-numbered global signal line YIOn, and the second end is connected to The complementary local signal line Ldat #, the gate is connected to the odd-numbered write control signal line Wrn+1, the drain of the ninth N-type transistor M9 is connected to the complementary local signal line Ldat #, the gate is connected to the even-numbered global signal line YIOn, the tenth N The drain of the type transistor M10 is connected to the source of the ninth N-type transistor M9, the gate is connected to the odd-numbered write control signal line Wrn+1, and the source is grounded.

When the circuit is in an even-numbered read state, after pre-charging the even-numbered global signal line YIOn (the pre-charging circuit of the signal line YIO is not shown), the even-numbered read control signal line Rdn enables the second N-type transistor M2 on, when the complementary local signal line Ldat # is at a high potential and the local signal line Ldat is at a low potential, the first N-type transistor M1 is turned on, and the local signal line Ldat is transmitted to the even-numbered voltage through the ground voltage connected by the second N-type transistor M2. In the bit global signal line YIOn, the voltage of the even-numbered global signal line YIOn becomes a low level, and at this time, the even-numbered global signal line YIOn reads out the data on the local signal line Ldat. When the complementary local signal line Ldat # is at a low level and the local signal line Ldat is at a high level, the first N-type transistor M1 is turned off, and the ground voltage connected to the second N-type transistor M2 cannot be transmitted to the even-numbered global signal line YIOn, the even-numbered global signal line YIOn maintains the high potential after pre-charging, and at this time, the even-numbered global signal line YIOn reads out the data on the local signal line Ldat. When the circuit is in the write state of the even bits, the even-numbered write control signal Wrn enables the third N-type transistor M3 and the fifth N-type transistor M5. At this time, if the even-numbered global signal line YIOn is at a high level, the fourth N-type transistor M3 and the fifth N-type transistor M5 are enabled by the even-numbered write control signal Wrn. The N-type transistor M4 is turned on, the complementary local signal line Ldat # becomes a low potential, and the local signal line Ldat maintains the pre-charged high potential. If the even-numbered global signal line YIOn is at a low potential, the fourth N-type transistor M4 is turned off, and the complementary local signal line is turned off. The signal line Ldat # becomes a high potential after precharging, and the local signal line Ldat becomes a low potential. The reading and writing principles of odd-numbered bits are the same, and are not repeated here. It can be seen from the above that after receiving different read-write control signals, the spare read-write conversion circuit can read and write even-numbered or odd-numbered bits, so as to write signals of odd-numbered or even-numbered bits according to different read-write control signals. The spare memory array or read from the spare memory array.

FIG.7is a schematic diagram of the spare read-write conversion circuit181in another embodiment of the present disclosure.

Referring toFIG.7, in an exemplary embodiment of the present disclosure, the spare read-write conversion circuit181may further include a precharge circuit71. The precharge circuit71is connected to the complementary local signal line Ldat #, the local signal line Ldat, the power supply voltage Vcc and the precharge signal Pre, and the precharge circuit71is used to pull up the complementary local signal line Ldat # and the local signal line Ldat, and to the complementary local signal line Ldat # and the local signal line Ldat are precharged.

In the embodiment shown inFIG.7, the precharge circuit71may include:a first P-type transistor M11, the source of M11 is connected to the power supply voltage Vcc, the gate is connected to the precharge control signal Pre, and the drain is connected to the local signal line Ldat;a second P-type transistor M12, the source of M11 is connected to the power supply voltage Vcc, the gate is connected to the precharge control signal Pre, and the drain is connected to the complementary local signal line Ldat #; anda third P-type transistor M13 which has a first end connected to the complementary local signal line Ldat #, a second end connected to the local signal line Ldat, and a control end connected to the precharge control signal Pre.

In the embodiment of the present disclosure, the precharge circuit71is provided, and before writing, the first P-type transistor M11 and the second P-type transistor M12 are enabled by outputting the precharge control signal Pre, so as to provide a signal to the complementary local signal line Ldat # Precharge with local signal line Ldat.

By pulling up the complementary local signal line Ldat # and the local signal line Ldat, the threshold loss of signal transmission can also be avoided, so that the effect of signal transmission is better.

FIG.8is a schematic diagram of the spare read-write conversion circuit181in still another embodiment of the present disclosure.

Referring toFIG.8, in an exemplary embodiment of the present disclosure, the spare read-write conversion circuit181further includes a read-write auxiliary circuit81, which is connected to the complementary local signal line Ldat #, the local signal line Ldat and the enable signal, the read/write auxiliary circuit81is used to amplify the complementary local signal line Ldat # and the local signal line Ldat.

In the embodiment shown inFIG.8, the read/write auxiliary circuit81includes:a fourth P-type transistor M14, the source is connected to the power supply voltage;a fifth P-type transistor M15, the source is connected to the power supply voltage, the gate is connected to the source M14 of the fourth P-type transistor, and the source is connected to the gate of the fourth P-type transistor M14;an eleventh N-type transistor M16, the drain is connected to the source of the fourth P-type transistor M14, and the gate is connected to the source of the fifth P-type transistor M15;a twelfth N-type transistor M17, the drain is connected to the source of the fifth P-type transistor M15, the gate is connected to the source of the fourth P-type transistor M14, and the source is connected to the source of the eleventh N-type transistor M16; anda thirteenth N-type transistor M18, the drain is connected to the source of the eleventh N-type transistor M16, the gate is connected to the enable signal En, and the source is grounded.

The read/write auxiliary circuit81can amplify the complementary local signal line Ldat # and the local signal line Ldat when the enable signal En is in the enable state, so that the signal transmission effect is better.

When the memory array fails, the spare memory array14and the first sensitivity amplifier array15are automatically used to replace the failed memory array, and when the sensitivity amplifier array fails, the spare memory array14and the first sensitivity amplifier array15are automatically used to replace the failed sensitive amplifier. The two memory arrays affected by the amplifier can not only effectively improve the reliability of memory products, but also improve the test success rate and yield rate of memory products, thereby reducing production costs.

FIG.9is a schematic diagram of a memory structure in another embodiment of the present disclosure.

Referring toFIG.9, in an embodiment of the present disclosure, a second spare memory sub-array91is further arranged in the memory array11, and a spare sensitivity amplifier sub-array is arranged between the second spare memory sub-arrays91of the adjacent memory arrays11. The spare sensitivity amplifier sub-arrays92located in different odd-numbered sensitivity amplifier arrays12are all electrically connected to the same spare odd-numbered global signal line, and the spare sensitivity amplifier sub-arrays92located in different even-numbered sensitivity amplifier arrays13are all electrically connected to the same spare even-numbered global signal line.

Meanwhile, the spare memory array14also includes a second spare memory sub-array91, the second spare memory sub-array91is provided with a corresponding spare first sensitivity amplifier sub-array93located in the first sensitivity amplifier array15, and the spare first sensitivity amplifier sub-array93is simultaneously connected to the spare odd-numbered global signal lines and the spare even-numbered global signal line through the spare read-write conversion array18.

In the embodiment shown inFIG.9, the number of second spare memory sub-arrays91in both the memory array11and the spare memory array14is one. In other embodiments, more second spare sub-arrays may be set in each memory array. The sub-array91is stored. In addition, the second spare memory sub-arrays91may be located at various positions in the memory arrays, and each second spare memory sub-array91has the same position in the respective memory arrays. In an exemplary embodiment of the present disclosure, the second spare memory sub-array91is located in the middle of the memory array11or the spare memory array14. Those skilled in the art can set the quantity and location of the second spare memory sub-arrays91according to actual conditions, which is not particularly limited in the present disclosure.

Referring toFIG.9, when a large failure occurs in a key position related to a column, a column of memory sub-array B (also called a column block area) where the faulty memory sub-array is located can be disabled first, and each memory array can be used for a second spare memory sub-array A in a row to repair the replacement. At this time, if the spare memory array14is enabled, the second spare memory sub-array A in this row includes the second spare memory sub-array91in each memory array11and the second spare memory sub-array91in the spare memory array14; If the spare memory array14is not enabled, the second spare memory sub-array aof the column includes only the second spare memory sub-array91in each memory array11.

In the peripheral circuit, when data needs to be written to a row of memory sub-arrays B including the faulty memory sub-arrays, a row of second spare memory sub-arrays A in all memory arrays11can be read and written to replace the faulty memory sub-arrays. The column where it is located stores sub-array B. When reading, it is necessary to control to output the YIO data read out from a column of the second spare memory sub-array A to a position corresponding to the replaced column of memory sub-arrays.

The replacement function of column A to column B can perform the entire replacement of column A to column B, or a partial replacement. For example, when accessing one memory array, use the second spare memory sub-array in column A to replace the failed memory sub-array in column B; when accessing another memory array, use the second spare memory sub-array in column A to replace failed memory sub-array in column C.

FIG.10is a schematic diagram of a memory circuit having a redundancy replacement function in an embodiment of the present disclosure.

Referring toFIG.10, in the memory circuit1000, an odd-numbered sensitivity amplifier array12and an even-numbered sensitivity amplifier array13are arranged between the memory arrays11. A spare memory array14and a first sensitivity amplifier array15are arranged beside the memory array11located at the edge. In addition, the memory circuit1000further includes a column decoding circuit (YDEC)101, a sensitivity amplifier data write driver circuit (YIO SA & write driver)102, a plurality of data selectors (MUX, multiplexer)103, a sensitivity amplifier data write driver102includes a plurality of sensitivity amplifier data writing circuits1021.

Each sensitivity amplifier data writing circuit1021is connected to an odd-numbered global signal line104or an even-numbered signal line105and is connected to a data selector103. The other end of the data selector103is connected to the data bus110, and is controlled by the control logic and the column block repair logic. The data writing circuit1021of the sensitivity amplifier writes to the odd-numbered global signal line104or even-numbered global signal line105.

The memory circuit1000is divided into a plurality of column blocks in the second direction, each block includes a memory sub-array and a sensitivity amplifier sub-array located in the same column, for example, the column blocks10B,10C,10D, all column blocks connected to four odd-numbered global signal lines104and four even-numbered global signal line105, that is, 8-bit data can be transmitted. Specifically, an odd-numbered sensitivity amplifier sub-array is connected to four odd-numbered global signal lines through four read-write conversion circuits, and an even-numbered sensitivity amplifier sub-array is connected to four even-numbered global signal line through four read-write conversion circuits. The number of odd-numbered global signal lines104and even-numbered global signal line105connected in each column block area may vary according to the memory capacity or memory processing capability of the memory array, and the present disclosure is not limited thereto.

The odd-numbered global signal line104is electrically connected to the odd-numbered sensitivity amplifier array12through the odd-numbered connection point106(specifically, the odd-numbered global signal line104is connected to the odd numbered sensitivity amplifier sub-arrays121shown inFIG.3through the odd numbered read-write conversion circuit), the even-numbered global signal line105is electrically connected to the even-numbered sensitivity amplifier array13through the even-numbered connection point107(specifically, the even-numbered global signal line105is connected to the even-numbered sensitivity amplifier sub-array shown inFIG.3through the even-numbered read-write conversion circuit17connection). In addition, the odd-numbered global signal lines104and the even-numbered global signal lines105are electrically connected to the first sensitivity amplifier array15through the odd-numbered connection points106and the even-numbered connection points107. For connection methods, refer to the circuits shown inFIGS.6to8. The present disclosure will not be repeated here.

The spare column block area A includes a plurality of second spare memory sub-arrays and spare sensitivity amplifier sub-arrays located in the same column. In some embodiments, when the spare memory array and the first sensitivity amplifier array are enabled, the spare column block area10A included are a first spare memory sub-array in the spare memory array and a spare first sensitivity amplifier sub-array in the first sensitivity amplifier array. The spare sensitivity amplifier sub-arrays located in the odd-numbered sensitivity amplifier array12are all electrically connected to the same four spare odd-numbered global signal lines108, and the spare sensitivity amplifier sub-arrays located in the even-numbered sensitivity amplifier array13are electrically connected to the same four. The spare even-numbered global signal line109and the spare first sensitivity amplifier sub-array are electrically connected to the four spare odd-numbered global signal lines108and the four spare even-numbered global signal line109at the same time. The spare column block area10A is connected to four spare odd-numbered global signal lines108and four even-numbered global signal line109in total, that is, 8 bits of data can be transmitted. The number of odd-numbered global signal lines108and even-numbered global signal line109connected in the spare column block area10A may vary according to the memory capacity or memory processing capability of the memory array, which is the same as the column block areas10B,10C, and10D. It can be known that, in some embodiments, the number of rank blocks may be 16 (excluding the spare rank block A). The connection mode of the spare odd-numbered global signal line108or spare even-numbered global signal line109and the spare sensitivity amplifier sub-array (the position where the dotted line box intersects the odd-numbered sensitivity amplifier array12or the even-numbered sensitivity amplifier array13inFIG.10is the same as the other odd-numbered global signal lines or even-numbered global signal line corresponding to the sensitivity amplifier array where the spare sensitivity amplifier sub-array is located are the same, and details are not described herein again.

The relative positions and numbers of the spare column block areas10A are only examples. In other embodiments of the present disclosure, the spare column block areas10A may also be located at other positions, and the number may also be equal to or more than two.

When any one of the column block regions10B,10C,10D is damaged (e.g., the number of inoperable memory sub-arrays and/or sensitivity amplifier sub-arrays exceeds a preset threshold), the spare column block region10A can be used for the damaged column in the block area10B,10C, or10D is replaced by the entire column. During specific execution, the data selector103is set by the column block area replacement logic, so that the data corresponding to the damaged column block area10B,10C or10D is transmitted to the spare column block area10A, and then the data selector103is changed by the control logic to perform data output control. The column block area or the spare column block area can be enabled through a column select signal (CSL, column select) corresponding to each column.

Similarly, when any one of the memory array11, the odd-numbered sensitivity amplifier12, and the even-numbered sensitivity amplifier13is damaged, the spare memory array14and the first sensitivity amplifier array15can be used for replacement, thereby realizing the replacement in the row direction. In one embodiment, row block repair logic can be used to control the enabling of the memory array11, the odd-numbered sensitivity amplifier12, the even-numbered sensitivity amplifier13, the spare memory array14, and the first sensitivity amplifier array15, or disabled so that the data is transferred correctly to the memory array or to a spare memory array.

Through the memory structure provided by the embodiments of the present disclosure, whether it is a large-area manufacturing error related to a column or a row, it can be repaired by replacing the entire block together, thereby improving the repair capability and chip reliability. Yield rate, success rate, especially for the early research and development of new processes is more effective.

According to a second aspect of the present disclosure, there is provided a memory including the memory structure of any preceding item.

It should be noted that although several modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.

Other embodiments of the present disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or techniques in the technical field not disclosed by the present disclosure. The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the disclosure being indicated by the claims.

INDUSTRIAL APPLICABILITY

In the embodiment of the present disclosure, by arranging a spare memory array and a first sensitivity amplifier array beside the memory array, and simultaneously connecting the first sensitivity amplifier array to the odd-numbered global signal lines and the even-numbered global signal line, when damage of the memory array or the sensitivity amplifier array occurs, the first sensitivity amplifier array and the spare memory array are automatically used for replacement, thereby improving the reliability of the memory product and the success rate of the factory test, improving the yield of the product, and reducing the production cost and use cost of the memory product.