Patent ID: 12210458

DETAILED DESCRIPTION

In general, according to one embodiment, an information processing system includes a memory system including a non-volatile memory; and a host device including a host memory and a processor executing software for accessing data stored in the non-volatile memory. The processor is configured to: allocate a cache area in the host memory to cache data stored in the non-volatile memory; when the software is executed, perform a tag lookup of the cache area, and in a case where a cache hit has occurred upon the lookup, access the cache area without accessing the non-volatile memory; and refill the data stored in the non-volatile memory into the cache area at a second frequency lower than a first frequency at which a cache miss occurs.

Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are denoted by the same reference numerals. In addition, in a case where a plurality of components having a common reference sign is distinguished, the common reference sign is added with a suffix to be distinguished. Note that, in a case where a plurality of components does not need to be particularly distinguished, only common reference numerals are attached to the plurality of components, and no suffixes are attached thereto.

1. First Embodiment

1.1 Configuration

A configuration of an information processing system according to a first embodiment will be described.

1.1.1 Hardware Configuration of Information Processing System

FIG.1is a block diagram illustrating an example of a hardware configuration of the information processing system according to the first embodiment, An information processing system1includes a host device10and a memory system20.

The information processing system1is, for example, a personal computer or a server in a data center. The host device10includes a processor11and a host memory12.

The processor11includes, for example, a central processing unit (CPU) and a graphics processing unit (GPU). The processor11requests input and output (access) of data to the memory system20. For example, the processor11requests the memory system20to perform data write processing and read processing. Hereinafter, the request processing related to the read processing in the host device10is also referred to as read access processing.

The host memory12is, for example, a dynamic random access memory (DRAM). The host memory12is used as a work area when the processor11executes an operating system (OS), an application program, and the like. The host memory12is also used as a memory area for temporarily storing data read from the memory system20.

The memory system20is a storage device configured to be coupled to the host device10. The memory system20is, for example, a memory card such as an SD™ card, a universal flash storage (UFS), or a solid state drive (SSD). The memory system20includes a memory controller30and a non-volatile memory40.

The memory controller30includes, for example, an integrated circuit such as a system-on-a-chip (SoC). The memory controller30includes a control circuit31, a host interface circuit (host I/F)32, and a memory interface circuit (memory I/F)33.

The control circuit31includes, for example, a processor such as a CPU, a ROM, and a RAM. The control circuit31controls input and output of data between the host device10and the non-volatile memory40. For example, the control circuit31executes read processing to read data from the non-volatile memory40in response to a read request from the host device10.

The host interface circuit32manages communication between the host device10and the memory controller30. The host interface circuit32is coupled to the host device10via a host bus HB. The host bus HB conforms to, for example, an SD™ interface, a serial attached SCSI (small computer system interface) (SAS), a serial ATA (advanced technology attachment) (SATA), or a PCI (peripheral component interconnect) Express™ (PCIe).

The memory interface circuit33manages communication between the non-volatile memory40and the memory controller30. The memory interface circuit33is coupled to the non-volatile memory40via a memory bus MB. The memory bus MB conforms to, for example, a single data rate (SDR) interface, a toggle double data rate (DDR) interface, or an open NAND flash interface (ONFI).

The non-volatile memory40is, for example, a NAND flash memory. The non-volatile memory40includes a plurality of memory chips CP_1, . . . , CP_n (n is an integer of 2 or more). Each of the plurality of memory chips CP_1to CP_nincludes a plurality of memory cells. Each of the plurality of memory cells stores data in a non-volatile manner.

Note that, in the above example, a configuration in which the host device10and the memory system20are assumed to be components in a personal computer or a server has been described, but the present invention is not limited thereto. For example, the host device10and the memory system20may be coupled to each other via a network. In this case, the information processing system1is a cluster including a plurality of servers. The memory system20is, for example, a storage server. In this case, the host bus HB coupling the host device10and the memory system20may be, for example, Ethernet™, InfiniBand, or the like.

1.1.2 Functional Configuration of Information Processing System

FIG.2is a block diagram illustrating a functional configuration of the information processing system according to the first embodiment.

The host device10functions as a buffer area110, a cache area120, a queue130, an application140, a miss frequency collection module150, and a cache replacement module160. The memory controller30functions as a read module310. The non-volatile memory40functions as an access area410.

The buffer area110is, for example, a memory area that functions as a direct memory access (DMA) buffer in the host memory12. In the buffer area110, for example, data output from the memory system20in response to a read request is temporarily stored.

The cache area120is, for example, a memory area that functions as a software cache in the host memory12. The cache area120stores, for example, information regarding data to be cached over the medium to long term (that is, the access frequency is high in the medium to long term) among data stored in the access area410. The cache area120includes data fields121aand121band tag fields122aand122b.

In the data fields121aand121b, entities of the data to be cached are stored. Data fields121aand121bare associated with tag fields122aand122b, respectively. The tag fields122aand122bstore information for searching the data stored in the data fields121aand121b, respectively. The data structure of the data field121aand the tag field122ais equivalent to the data structure of the data field121band the tag field122b. Details of the data structure in the cache area120will be described later.

The queue130includes an SQ131and a CQ132. The SQ131is a submission queue. The SQ131stores, for example, various requests (for example, a read request) to the memory system20. The CQ132is a completion queue. The CQ132stores results of various requests ended by the memory system20. For example, the CQ132stores a pointer indicating an address of a storage destination of data output from the memory system20in response to the read request.

The application140is a software program executed by the processor11. For example, a multithreaded execution is implemented in the application140. The application140determines whether or not data in the access destination (access target data) is stored in the cache area120according to the occurrence of the read access processing. The processing of determining whether or not the access target data is stored in the cache area120is also referred to as a lookup processing. That is, the application140performs the lookup of the cache area120when the read access processing is occurred. When the access target data is stored in the cache area120as the result of the lookup, the application140accesses the access target data in the data field121of the cache area120. When the access target data is not stored in the cache area120, the application140causes the read request to be stored in the SQ131. The application140accesses the data output from the memory system20as a result of the read request based on the pointer stored in the CQ132. The data output from the memory system20is stored in the buffer area110, for example.

In addition, the application140stores reference count values141aand141b. The reference count value141aand141bmay be stored in and managed by the cache area120. The reference count value141ais a value of a counter indicating how many threads of the application140are accessing the data field121aand the tag field122aof the cache area120. The reference count value141bis a value of a counter indicating how many threads of the application140are accessing the data field121band the tag field122bof the cache area120.

In the following description, a state in which the access target data is stored in the cache area is also referred to as a “cache hit”. A state in which the access target data is not stored in the cache area is also referred to as a “cache miss”.

Note that the read access processing is performed on any one of a set of the data field121aand the tag field122aand a set of the data field121band the tag field122b. In the following description, a set of the data field121aand the tag field122aor a set of the data field121band the tag field122b, on which the read access processing is about to be executed, is referred to as a “cache area120in an active state”. A set of the data field121aand the tag field122aor a set of the data field121band the tag field122b, on which the read access processing is not executed in the application140, is referred to as a “cache area120in an inactive state”. In addition, the reference count value141aor141bcorresponding to the cache area120in an active state is referred to as “reference count value141in an active state”. The reference count value141aor141bcorresponding to the cache area120in an inactive state is referred to as “reference count value141in an inactive state”.

The miss frequency collection module150is a module that executes miss frequency collection processing. The miss frequency collection processing is processing of collecting a frequency (miss frequency) at which a cache miss occurs in the read access processing in association with the access area410. For example, every time the first period elapses, the miss frequency collection module150may count the number of read requests stored in the SQ131for each address of access target (access destination). The first period is, for example, 10 milliseconds or less. In this case, the miss frequency collection processing is executed asynchronously with the read access processing (lookup processing). For example, every time the number of cache misses reaches the first number, the miss frequency collection module150may count the number of read requests stored in the SQ131for each address of access target. The first number is, for example, 128 or less. In this case, the miss frequency collection processing is executed synchronously with the read access processing (lookup processing). The miss frequency may be reset before the miss frequency collection processing is executed, but the miss frequency is not necessarily reset. In a case where the miss frequency is not reset before the miss frequency collection processing is executed, the miss frequency collection module150may set, for example, a value obtained by uniformly halving the already collected miss frequency as a new miss frequency, and accumulate the collected miss frequency. The miss frequency collection module150stores the collected miss frequency as miss frequency information151.

The miss frequency collection module150may include a bloom filter, a count-min sketch (CM sketch), and a map structure. The bloom filter is a data structure that can probabilistically determine whether or not a miss frequency occurs in a Boolean format for the given access target. The CM sketch is a data structure that can probabilistically determine the number of occurrences of misses in integer form for the given access target. The map structure is a data structure that determines the number of occurrences of misses in an integer format for the given access target. With the above configuration, the miss frequency collection module150selectively calculates the access target having a high miss frequency with high accuracy while probabilistically calculating the access target having a low miss frequency. As a result, the miss frequency collection module150can operate with fewer memory resources than when precisely collecting all miss frequencies.

The cache replacement module160is a module that performs a cache replacement processing. The cache replacement processing is processing of replacing data stored in the cache area120in an inactive state with data having a high miss frequency. For example, the cache replacement module160may execute the cache replacement processing every time a second period longer than the first period elapses. The second period is, for example, several hundred milliseconds. In this case, the cache replacement processing is executed asynchronously with the read access processing. For example, the cache replacement module160may execute the cache replacement processing every time the number of cache misses reaches a second number larger than the first number. The second number is, for example, 1024. In this case, the cache replacement processing may be executed synchronously with the read access processing. A timer that counts up to the second period and a counter that counts up to the second number are reset each time the cache replacement processing is executed.

In the cache replacement processing, the cache replacement module160determines which data has a high miss frequency among the data stored in the memory system based on the miss frequency information151. For example, the cache replacement module160determines data having a cache miss count equal to or greater than a threshold among the data stored in the memory system20as data having a high miss frequency. Furthermore, the cache replacement module160may determine the top N pieces of data having a large number of cache misses among the data stored in the memory system20as data having a high miss frequency (N is a natural number). In the following description, data having a high miss frequency determined by the cache replacement module160is called as “replacement target data”.

The cache replacement module160randomly determines whether or not to replace the data stored in the cache area120with the data determined to have a high miss frequency. Then, in a case where it is determined to replace the data, the cache replacement module160replaces the data stored in the cache area120in an inactive state with the data having a high miss frequency. If it is determined not to replace the data, the cache replacement module160does not replace the data. Note that the cache replacement module160may unconditionally replace the data stored in the cache area120with the data determined to have a high miss frequency.

The read module310is a module that executes read processing in response to a read request. Upon receiving the read request, the read module310reads the access target data from the non-volatile memory40via the memory bus MB. Then, the read module310outputs the access target data read from the non-volatile memory40to the host device10via the host bus HB. The output access target data is temporarily stored in the buffer area110, for example.

The access area410is a memory area for storing data in a non-volatile manner in the non-volatile memory40. In the access area410, data to be access target in the read access processing is stored in a non-volatile manner.

1.1.3 Configuration of Access Area

FIG.3is a diagram illustrating an example of a configuration of an access area of the information processing system according to the first embodiment. As illustrated inFIG.3, the access area410is divided into a plurality of sub-areas. Data DAT to be access target is stored in each of the plurality of sub-areas.

Specifically, for example, each of the plurality of sub-areas in the access area410is associated with one tag number of x tag numbers and one group of y groups (each of x and y is an integer of 2 or more). In the example ofFIG.3, in an arbitrary combination of i of 1 or more and x or less and j of 1 or more and y or less, a case where data DAT ((i−1)y+j) is stored is indicated in a sub-area associated with a set of a tag number “i” and a group “j”.

With the above configuration, different tag numbers are allocated to x sub areas associated with the same group among a plurality of sub areas in the access area410.

1.1.4 Configuration of Cache Area

FIG.4is a diagram illustrating an example of a configuration of a cache area of the information processing system according to the first embodiment.FIG.4illustrates an example of a configuration of a set of the data field121aand the tag field122a. Note that the configuration of the set of the data field121band the tag field122bis equivalent to the configuration of the set of the data field121aand the tag field122a, and thus the description will be omitted. However, the set of the data field121aand the tag field122acan be different from the set of the data field121band the tag field122b.

A set of the data field121aand the tag field122ais divided into y sub-areas. The y sub-areas are each associated with a group “1” to a group “y”. That is, a sub-area of a set of the data field121aand the tag field122aassociated with the group “j” is allocated as a cache area for x sub-areas associated with the group “j” in the access area410.

The cache data CDAT is stored in a sub-area of the data field121a. In a sub-area of the tag field122a, a set of a tag number and a valid flag is stored.

The valid flag of the tag field122aindicates whether or not valid cache data CDAT is stored in the corresponding data field121a. Specifically, for example, when the valid flag V2of the tag field122aassociated with the group “2” is “true”, the cache data CDAT2of the data field121aassociated with the group “2” is valid. When the valid flag V3of the tag field122aassociated with the group “3” is “false”, the cache data CDAT3of the data field121aassociated with the group “3” is invalid.

The tag number of the tag field122aindicates to which tag number the cache data CDAT stored in the data field121ais allocated in the access area410. Specifically, for example, when the tag number T1of the tag field122aassociated with the group “1” is “3”, the cache data CDAT1stored in the data field121aassociated with the group “1” is data DAT (2y+1). When the tag number Ty of the tag field122aassociated with the group “y” is “x”, the cache data CDATy stored in the data field121aassociated with the group “y” is data DAT (xy).

With the above configuration, it is possible to specify which sub-area of the access area410the cache data CDAT stored in the cache area120corresponds to. Such a data structure in the cache area120is also referred to as a direct-mapped cache structure. In the examples ofFIGS.3and4, the case where the sub-area is identified by a set of a tag number and a group has been described, but the present invention is not limited thereto. For example, the tag number and the group may be calculated as an output when the address of the access area410is input to the hash function. Moreover, each data is not limited to a fixed length, and may store variable-length data.

1.2 Operation

Next, an operation in the information processing system according to the first embodiment will be described.

1.2.1 Read Access Processing

FIG.5is a flowchart illustrating an example of read access processing in an application of the information processing system according to the first embodiment.

When a read access occurs (start), the application140increments the reference count value141in an active state (S1). More specifically, the application140acquires the cache number (current number) of the cache area120in an active state. Then, the application140increments the reference count value141of the current number.

The application140determines whether or not the access target data is stored in the cache area120of the current number. In other words, the application140determines whether or not a cache hit has occurred (S2).

When a cache hit occurs (S2; yes), the application140accesses the access target data stored in the data field121of the cache area120of the current number (S3). As a result, the application140uses the access target data. Note that switching from the active state to the inactive state of the cache area120is executed asynchronously with the application140. Therefore, the cache area120in an active state may be switched to the inactive state, for example, at the time of the processing of S1and at the time of the processing of S3. Therefore, the application140acquires the current number at the time of the processing of S1, and stores the current number until the read access processing ends.

After the processing of S3, the application140decrements the reference count value141of the current number (S4).

When a cache miss occurs (S2; no), the application140decrements the reference count value141of the current number (S5).

The application140causes the memory system20to execute a read processing of the access target data (S6). The access target data output from the memory system by the read processing in S6is stored in the buffer area110.

The application140accesses the access target data stored in the buffer area110(S7). As a result, the application140uses the access target data.

When the processing of S4or the processing of S7ends, the read access processing ends (end).

As described above, the read access processing is divided into processing of accessing the data field121of the cache area120when a cache hit occurs and processing of accessing the access area410when a cache miss occurs. Therefore, the frequency at which the read access processing occurs is the sum of the frequency at which the cache hit occurs (that is, the frequency of access to the data field121of the cache area120) and the frequency at which the cache miss occurs (that is, the frequency of access to the access area410).

1.2.2 Read Processing

FIG.6is a flowchart illustrating an example of a read module of the information processing system according to the first embodiment. The processing of S11and S12illustrated inFIG.6corresponds to the processing of S6inFIG.5.

When the read request is stored in the SQ131(start), the read module310executes read processing of the access target data from the access area410in the non-volatile memory40(S11).

The read module310outputs the access target data read from the access area410by the processing of S11to the host device10(S12). The data output to the host device10is stored in the buffer area110.

When the processing of S12ends, the read processing ends (end).

1.2.3 Miss Frequency Collection Processing

FIG.7is a flowchart illustrating an example of miss frequency collection processing in the miss frequency collection module of the information processing system according to the first embodiment.

When the first period elapses or the number of cache misses reaches the first number (start), the miss frequency collection module150obtains an address of access target included in the read request in the SQ131(S21).

The miss frequency collection module150determines whether or not the address obtained in the processing of S21has been registered in the bloom filter (S22).

When the obtained address is not registered in the bloom filter (S22; no), the miss frequency collection module150registers the address obtained in the processing of S21in the bloom filter (S23). As a result, information for probabilistically determining whether or not a cache miss has already occurred in a boolean format for each address in the access area410is stored in the miss frequency information151. Note that a case where it is determined that the obtained address has been registered in the bloom filter includes a case of a false positive. Therefore, even when the obtained address has not been registered in the bloom filter, the miss frequency collection module150may erroneously determine that the address has been registered in the bloom filter.

When the obtained address is already registered in the bloom filter (S22; yes), the miss frequency collection module150determines whether or not the number of counts of the address obtained in the processing of S21by the CM sketch has reached the upper limit (S24).

When the number of counts of the obtained address by the CM sketch does not reach the upper limit (S24; no), the miss frequency collection module150increments the number of counts by the CM sketch of the address obtained in the processing of S21(S25). As a result, information for probabilistically determining how many cache misses has occurred in an integer format for each address in the access area410is stored in the miss frequency information151.

When the number of counts of the obtained address by the CM sketch reaches the upper limit (S24; yes), the miss frequency collection module150increments the exact number of counts of the address obtained in the processing of S21(S26).

Note that a case where it is determined that the number of counts by the CM sketch of the obtained address has reached the upper limit includes some errors with probability. Therefore, even when the number of counts does not reach the upper limit in a case where the miss frequencies are collected precisely, the miss frequency collection module150may erroneously determine that the number of counts by the CM sketch has reached the upper limit.

After the processing of S23, the processing of S25, or the processing of S26, the miss frequency collection module150determines whether or not addresses included in all read requests in the SQ131have been selected (S27).

When the addresses included in all the read requests in the SQ131are not obtained (S27; no), the miss frequency collection module150obtains an address of access target included in the read request in the SQ131(S21). Subsequently, the subsequent processing of S22to27is executed. As a result, the processing of S21to S27is repeated until addresses included in all read requests in the SQ131are obtained.

When the addresses included in all the read requests in the SQ131are obtained (S27; yes), the miss frequency collection processing ends (end).

1.2.4 Cache Replacement Processing

FIG.8is a flowchart illustrating an example of cache replacement processing in the cache replacement module of the information processing system according to the first embodiment.

When the second period elapses or the number of cache misses reaches the second number (start), the cache replacement module160specifies the addresses of the replacement target data from the access area410based on the miss frequency information151(S31).

The cache replacement module160switches the cache area120to be activated (S32). Specifically, when the set of the data field121aand the tag field122ais in an active state, the data field121aand the tag field122aare turned into the inactive state, and the data field121band the tag field122bare turned into the active state. When the set of the data field121band the tag field122bis in an active state, the data field121band the tag field122bare turned into the inactive state, and the data field121aand the tag field122aare turned into the active state.

The cache replacement module160determines whether or not the reference count value141in an inactive state is “0” (S33).

When the reference count value141in an inactive state is not “0” (S33; no), the cache replacement module160stands by until the reference count value141in an inactive state becomes “0” (S34).

When the reference count value141in an inactive state is “0” (S33; yes), or after the processing of S34, the cache replacement module160determines whether or not to replace the data in the cache area120with the addresses specified in the processing of S31(S35). For example, the cache replacement module160randomly determines whether or not to replace the data in the cache area120. When unconditionally replacing the data in the cache area120, in the processing of S35, the cache replacement module160determines to replace the data in the cache area120(S35; yes).

When it is determined that the data in the cache area120is to be replaced (S35; yes), the cache replacement module160causes the memory system20to execute read processing of the replacement target data (S36).

The cache replacement module160causes the replacement target data to be stored in the cache area120in an inactive state corresponding to the address specified in the processing of S31(S37). Accordingly, the data stored currently in the cache area120in an inactive state corresponding to the address specified in the processing of S31is evicted.

When it is determined that the data in the cache area120is not to be replaced (S35; no) or the processing of S37ends, the cache replacement processing ends (end). Note that, in the cache replacement processing described above, the processing of S31may be executed with any order if it ends before the processing of S35. Note that, in a case where a plurality of addresses is specified in the processing of S31, the cache replacement module160performs the processing of S35to S37for each specified address.

1.2.5 Relationship Between Frequencies of Various Processing

FIG.9is a diagram illustrating a relationship between a frequency of a read access processing and a frequency of the cache replacement processing in the information processing system according to the first embodiment.

As described above, the cache replacement processing can be executed asynchronously or synchronously with the read access processing. Regardless of whether the cache replacement processing is executed asynchronously or synchronously with the read access processing, the overhead of the cache replacement processing is set sufficiently low with respect to the CPU processing load of the processor11in the read access processing. In a case where the cache replacement processing is executed synchronously with the read access processing, the frequency of cache replacement processing can be lower than the frequency of the read access processing as shown inFIG.9. In a case where the cache replacement processing is executed asynchronously with the read access processing, the frequency of cache replacement processing may be lower than the frequency of the read access processing as shown inFIG.9by setting the second period of the cache replacement processing to be sufficiently long.

1.3 Effects According to First Embodiment

According to the first embodiment, the cache replacement module160executes the cache replacement processing at a frequency lower than the frequency of the read access processing (that is, the frequency at which it is determined whether or not the data to be read is cached in the cache area120.) in many cases. Specifically, the cache replacement module160performs the cache replacement processing when the number of times of cache misses in the read access processing reaches the second number. Alternatively, the cache replacement module160executes the cache replacement processing when the second period has elapsed from the cache replacement processing executed immediately before. As a result, it is not necessarily to execute the cache data CDAT replacement processing every time the read access processing occurs. Therefore, it is possible to suppress an increase in the CPU processing load of the processor11in the read access processing.

Incidentally, the CPU processing load of the processor11in the read access processing includes a load associated with the software cache and a load associated with input and output of data from the memory system20when a cache miss occurs. When there are many accesses to the data stored in the memory system20(specifically, for example, in a case where the frequency of read accesses including both cases of a cache hit and a cache miss in one thread exceeds 5 million times per second (5M Read Per Second)), the load is large. In a case where software optimization is performed to reduce a load associated with input and output of data due to a high input and output per second (IOPS) of the memory system20, there is a possibility that the load associated with the software cache can be significant.

According to the first embodiment, the cache replacement processing is executed at a frequency lower than the miss frequency in many cases. As a result, the CPU processing load of the processor11associated with the software cache can be reduced as compared with a case where the cache replacement processing is executed each time a cache miss occurs. Therefore, even when the IOPS of the memory system20is sufficiently high, the load associated with the software cache can be sufficiently reduced.

In addition, the frequency of the cache replacement processing is lower than the miss frequency in many cases. As a result, the cache replacement processing is suitable for caching data that is often used in a medium to long term period (for example, several hundred milliseconds). Therefore, the frequency of data replacement for the cache area120can be reduced in a medium to long term period.

The miss frequency collection module150executes the miss frequency collection processing. Specifically, the miss frequency collection module150executes the miss frequency collection processing when the number of cache misses in the read access processing reaches the first number, which is smaller than the second number. Alternatively, the miss frequency collection module150executes the miss frequency collection processing when the first period, which is shorter than the second period, elapses from the miss frequency collection processing executed immediately before. As a result, it is not necessarily to execute the cache data CDAT replacement processing every time the read access processing occurs. Therefore, it is possible to suppress an increase in the CPU processing load of the processor11in the read access processing.

In addition, the cache replacement module160randomly determines whether or not to replace the data in the cache area120with the replacement target data in the cache replacement processing. As a result, it is possible to determine whether or not to replace the data in the cache area120by processing with a small load. In addition, since the data in the cache area120is randomly replaced, it is possible to prevent specific data from continuing to remain in the cache area120.

2. Second Embodiment

Next, an information processing system according to a second embodiment will be described. The second embodiment is different from the first embodiment in that whether or not to replace the data in a cache area120with replacement target data in cache replacement processing is determined based on the access frequency of the data in the cache area120. In the following description, description of configurations and operations equivalent to those of the first embodiment will be omitted, and configurations and operations different from those of the first embodiment will be mainly described.

2.1 Functional Configuration of Information Processing System

FIG.10is a block diagram illustrating a functional configuration of the information processing system according to the second embodiment.FIG.10corresponds toFIG.2in the first embodiment.

An information processing system1A includes a host device10A and a memory system20. Since the functional configuration of the memory system20is equivalent to that of the first embodiment, the description will be omitted.

The host device10A functions as a buffer area110, a cache area120A, a queue130, an application140A, a miss frequency collection module150, and a cache replacement module160A. The functional configurations of the buffer area110, the queue130, and the miss frequency collection module150are equivalent to those of the first embodiment, and thus, the description will be omitted.

The cache area120A includes data fields121aand121band tag fields122A a and122Ab. The configurations of the data fields121aand121bare equivalent to those of the first embodiment. Data fields121aand121bare associated with tag fields122Aa and122Ab, respectively. The tag fields122Aa and122Ab store information for searching the data stored in the data fields121aand121b, respectively. The data structure of the data field121aand the tag field122Aa is equivalent to the data structure of the data field121band the tag field122Ab. Details of the data structure in the cache area120A will be described later.

In the cache area120A, the frequency at which data is read from the cache area120A in the read access processing is stored for each address as access frequency information142. Specifically, in the cache area120A, an approximate frequency at which a cache hit occurs is stored for each address as the access frequency information142. The access frequency is, for example, the number of accesses per unit time. The access frequency information142may be initialized by, for example, miss frequency information151. The access frequency information142may be reset each time the cache replacement processing is executed, or the access frequency information142is not necessarily reset. In a case where the access frequency information142is not reset, the access frequency information142is not necessarily updated or may be updated after being initialized, for example. In a case where the access frequency information142is updated, the access frequency information142may be halved at every certain time interval, or may be updated by the access count value143. The access count value143is a value of a counter indicating the number of times a cache hit has occurred for data that can be an access count target in the cache area120A.

The cache replacement module160A determines, based on the access frequency information142, whether or not to replace the data stored in the cache area120A with the data determined to have a high miss frequency. Specifically, the cache replacement module160A compares the miss frequency of the data determined to have a high miss frequency with the access frequency associated with the address of the cache area120A that replaces the data. As a result of the comparison, in a case where the miss frequency is higher than the access frequency, the cache replacement module160A replaces the data stored in the cache area120A in an inactive state with the data having a high miss frequency. If the miss frequency is lower than the access frequency, the cache replacement module160A does not replace the data.

2.2 Configuration of Cache Area

FIG.11is a diagram illustrating an example of a configuration of a cache area and an access frequency of the information processing system according to the second embodiment.FIG.11corresponds toFIG.4in the first embodiment.FIG.11illustrates an example of a configuration of a set of the data field121aand the tag field122Aa. Note that the configuration of the set of the data field121band the tag field122Ab is equivalent to the configuration of the set of the data field121aand the tag field122Aa, and thus the description will be omitted.

A set of the data field121aand the tag field122Aa is divided into y sub-areas. The y sub-areas are each associated with a group “1” to a group “y”.

In a sub area of the tag field122Aa, a set of a tag number, a valid flag, and an access count flag is stored. The access count flag of the tag field122Aa indicates whether or not the access count value143is incremented when data is read from the corresponding data field121a. When the access count flag E1of the tag field122Aa associated with the group “1” is “true”, the access frequency information A1corresponding to the cache data CDAT1may be updated by the access count value. In a case where the access count flag E1is “false”, the access frequency information A1corresponding to the cache data CDAT1is not updated by the access count value.

For example, the access count flag is periodically switched between “true” and “false”. As a result, it is possible to control the number of groups for which the access count value is calculated in a certain period. Therefore, the management load of the access frequency information142by the application140A can be reduced.

2.3 Read Access Processing

FIG.12is a flowchart illustrating an example of read access processing in an application of the information processing system according to the second embodiment.FIG.12corresponds toFIG.5in the first embodiment.

When a read access occurs (start), the application140A increments the reference count value141in an active state (S41). More specifically, the application140A acquires the cache number (current number) of the cache area120A in an active state. Then, the application140A increments the reference count value141of the current number.

The application140A determines whether or not a cache hit has occurred (S42).

When a cache hit occurs (S42; yes), the application140A accesses the access target data stored in the data field121of the cache area120A of the current number (S43).

After the processing of S43, the application140A determines whether or not the access count flag corresponding to the cache area120A in which the access target data is stored is “true” (S44).

In a case where the access count flag corresponding to the cache area120A in which the access target data is stored is “true” (S44; yes), the application140A increments the corresponding access count value143(S45).

In a case where the access count flag corresponding to the cache area120A in which the access target data is stored is “false” (S44; no), or after the processing of S45, the application140A decrements the reference count value141of the current number (S46).

When a cache miss occurs (S42; no), the application140A decrements the reference count value141of the current number (S47).

The application140A causes the memory system20to execute a read processing of the access target data (S48). The access target data output from the memory system by the read processing in S48is stored in the buffer area110.

The application140A accesses the access target data stored in the buffer area110(S49).

When the processing of S46or the processing of S49ends, the read access processing ends (end).

Note that the cache replacement module160A updates the access count value143to the corresponding access frequency information142at every certain time interval, for example. As a result, the access frequency information142is appropriately updated to the latest access frequency.

2.4 Cache Replacement Processing

FIG.13is a flowchart illustrating an example of cache replacement processing in a cache replacement module of the information processing system according to the second embodiment.FIG.13corresponds toFIG.8in the first embodiment.

When the second period elapses or the number of cache misses reaches the second number (start), the cache replacement module160A specifies the address of the replacement target data from the access area410based on the miss frequency information151(S51). Specifically, for example, the cache replacement module160A specifies the address of the access area410in which the data having the maximum miss frequency is stored.

The cache replacement module160A switches the cache area120A to be activated (552).

The cache replacement module160A determines whether or not the reference count value141in an inactive state in the read access processing is “0” (S53).

When the reference count value141in an inactive state is not “0” (S53; no), the cache replacement module160A stands by until the reference count value141in an inactive state becomes “0” (S54).

When the reference count value141in an inactive state is “0” (S53; yes), or after the processing of S54, the cache replacement module160A determines whether the miss frequency of the replacement target data is higher than the access frequency of the cache area120A in an inactive state corresponding to the address specified in the processing of S51(S55).

In a case where the miss frequency of the replacement target data is higher than the access frequency of the cache area120A in an inactive state corresponding to the address specified in the processing of S51(S55; yes), the cache replacement module160A causes the memory system20to execute read processing of the replacement target data (S56).

The cache replacement module160A causes the replacement target data to be stored in the cache area120A in an inactive state corresponding to the address specified in the processing of S51(S57). Accordingly, the data stored up to the present in the cache area120A in an inactive state corresponding to the address specified in the processing of S51is evicted.

In a case where the miss frequency of the replacement target data is lower than the access frequency of the cache area120A in an inactive state corresponding to the address specified in the processing of S51(S55; no), or when the processing of S57ends, the cache replacement processing ends (end).

2.5 Effects According to Second Embodiment

According to the second embodiment, in a case where the access frequency is lower than the miss frequency, the cache replacement module160A causes the replacement target data to be stored in the cache area120A in an inactive state. As a result, in a case where the access frequency of the data already stored in the cache area120A is high, it is possible to suppress the data from being evicted from the cache area120A. Therefore, it is possible to more accurately maintain a state in which data having a high access frequency in the medium to long term is cached.

3. Third Embodiment

Next, an information processing system according to a third embodiment will be described. The third embodiment is different from the first embodiment in that a cache is implemented in a memory system. In the following description, description of configurations and operations equivalent to those of the first embodiment will be omitted, and configurations and operations different from those of the first embodiment will be mainly described.

3.1 Hardware Configuration of Information Processing System

FIG.14is a block diagram illustrating an example of a hardware configuration of the information processing system according to the third embodiment.FIG.14corresponds toFIG.1in the first embodiment.

An information processing system1B includes a host device10and a memory system20B. The memory system20B includes a memory controller30B and a non-volatile memory40. Since the functional configuration of the host device10and the non-volatile memory40is equivalent to that of the first embodiment, the description will be omitted.

The memory controller30B includes a control circuit31, a host interface circuit32, a memory interface circuit33, and a cache memory34. Since the configurations of the control circuit31, the host interface circuit32, and the memory interface circuit33are equivalent to those of the first embodiment, the description will be omitted.

The cache memory34is, for example, a static random access memory (SRAM) or a DRAM. The cache memory34is used as a memory area for temporarily storing data read from the non-volatile memory40.

3.2 Functional Configuration of Information Processing System

FIG.15is a block diagram illustrating a functional configuration of the information processing system according to the third embodiment.FIG.15corresponds toFIG.2in the first embodiment.

The memory controller30B functions as a read module310B and a cache area320.

The cache area320is a memory area that functions as a cache. The cache constituting the cache area320may be implemented in hardware or by using software on a processor in the memory controller30B. In the cache area320, for example, data that is frequently accessed in a short term with respect to data stored in the cache area120is stored. For example, every time a cache miss occurs, data in which the cache miss occurs is refilled into the cache area320.

When receiving the read request, the read module310B determines whether or not the access target data is stored in the cache area320. In a case where the access target data is stored in the cache area320, the read module310B outputs the access target data in the cache area320to the host device10. In a case where the access target data is not stored in the cache area320, the read module310B reads the access target data from the non-volatile memory40via the memory bus MB. Then, the read module310B outputs the access target data read from the non-volatile memory40to the host device10via the host bus HB. In addition, the read module310B refills the access target data read from the non-volatile memory40into the cache area320.

3.3 Read Processing

FIG.16is a flowchart illustrating an example of a read processing in a read module of the information processing system according to the third embodiment.FIG.16corresponds toFIG.6in the first embodiment.

When the read request is stored in the SQ131(start), the read module310B determines whether or not the access target data is stored in the cache area320. In other words, the read module310B determines whether or not a cache hit has occurred (S61).

When a cache hit has occurred (S61; yes), the read module310B outputs the access target data read from the cache area320to the host device10(S62).

When a cache miss occurs (S61; no), the read module310B executes a read processing from the access target of the access area410(S63).

The read module310B stores the access target data read from the access area410by the processing of S63in the cache area320(S64).

The read module310B outputs the access target data read from the access area410by the processing of S63to the host device10(S65).

When the processing of S62or the processing of S65ends, the read processing ends (end). Additionally, the data output to the host device10is stored in the buffer area110.

3.4 Effects According to Third Embodiment

According to the third embodiment, the memory controller30B includes the cache memory34. In the read processing, the read module310B determines whether or not the access target data is stored in the cache area320. As a result, even if the access target data is not stored in the cache area120, the read module310B can output the access target data to the host device10without accessing the access area410as long as the access target data is stored in the cache area320. Therefore, when a cache miss occurs in the cache area120, the processing load on the non-volatile memory40can be reduced, and the latency until data is output from the memory system20B can be reduced.

As described above, the frequency of the cache replacement processing for the cache area120is set lower than the frequency of the read access processing. As a result, data having a high access frequency in a medium to long term period is likely to be stored in the cache area120. Therefore, data having a high access frequency in a short term period may not be stored in the cache area120.

According to the third embodiment, every time a cache miss occurs in the cache area320, access target data is read from the access area410and stored in the cache area320. As a result, it is possible to store, in the cache area320, data having a high access frequency in a short term period that is difficult to be stored in the cache area120. Therefore, it is possible to prevent access to the access area410even for data having a high access frequency in a short term period.

4. Fourth Embodiment

Next, an information processing system according to a fourth embodiment will be described. The fourth embodiment is different from the first embodiment in that a tag field is implemented in a memory system. In the following description, description of configurations and operations equivalent to those of the first embodiment will be omitted, and configurations and operations different from those of the first embodiment will be mainly described.

4.1 Functional Configuration of Information Processing System

FIG.17is a block diagram illustrating a functional configuration of the information processing system according to the fourth embodiment.FIG.17corresponds toFIG.2in the first embodiment. An information processing system1C includes a host device10C and a memory system20C. The memory system20C includes a memory controller30C and a non-volatile memory40. Since the configuration of the non-volatile memory40is equivalent to that of the first embodiment, the description will be omitted.

The host device10C functions as a buffer area110, a cache area120C, a queue130, an application140C, a miss frequency collection module150, and a cache replacement module160. The memory controller30C functions as a read module310C and tag fields330aand330b. The functional configurations of the buffer area110, the queue130, the miss frequency collection module150, and the cache replacement module160are equivalent to those of the first embodiment, and thus, the description will be omitted.

The cache area120C includes data fields121aand121b, but does not include a tag field. The data fields121aand121bare associated with tag fields330aand330bin the memory controller30C, respectively. The tag fields330aand330bhave the equivalent configuration as the tag fields122aand122bhave in the first embodiment.

The application140C causes the read request to be stored in the SQ131in response to the occurrence of the read access processing. The application140C acquires the data output from the memory system20C as a result of the read request based on the pointer stored in the CQ132.

Note that, as described above, the application140C acquires the current number in response to the occurrence of the read access processing. The application140C notifies the read module310C of the current number (that is, the cache number used for the read access processing) by including the current number in the SQ131.

Upon receiving the read request, the read module310C determines to which of the tag fields330aand330bis referred based on the current number in the SQ131. The read module310C determines whether or not the access target data is stored in the cache area120C by referring to the tag field330aor330bspecified by the read request. In a case where the access target data is stored in the cache area120C, the read module310C outputs a pointer indicating the address of the cache area120C in which the access target data is stored to the host device10C. As a result, the pointer indicating the address of the cache area120C in which the access target data is stored is stored in the CQ132.

In a case where the access target data is not stored in the cache area120C, the read module310C reads the access target data from the non-volatile memory40via the memory bus MB. Then, the read module310C outputs the access target data read from the non-volatile memory40to the host device10C via the host bus HB. The output access target data is stored in the buffer area110. As a result, the pointer indicating the address of the buffer area110in which the access target data is stored is stored in the CQ132.

4.2 Read Access Processing

FIG.18is a flowchart illustrating an example of read access processing in an application of the information processing system according to the fourth embodiment.FIG.18corresponds toFIG.5in the first embodiment.

When a read access occurs (start), the application140C increments the reference count value141in an active state (S71). More specifically, the application140C acquires the cache number (current number) of the cache area120C in an active state. Then, the application140C increments the reference count value141of the current number.

The application140C causes the read request of the access target data to be stored in the SQ131(S72). The SQ131includes the current number acquired in the processing of S71.

The application140C stands by until the result of the read request stored in the SQ131in the processing of S72is stored in the CQ132(S73).

After the processing of S73, the application140C accesses the data indicated by the pointer stored in the CQ132as the access target data (S74).

After the processing of S74, the application140C decrements the reference count value141of the current number (S75).

When the processing of S75ends, the read access processing ends (end).

4.3 Read Processing

FIG.19is a flowchart illustrating an example of a read processing in a read module of the information processing system according to the fourth embodiment.FIG.19corresponds toFIG.6in the first embodiment.

When the read request is stored in the SQ131(start), the read module310C refers to the tag field330aor330bof the current number in the SQ131to determine whether or not the access target data is stored in the cache area120C. In other words, the read module310C determines whether or not a cache hit has occurred (S81).

When a cache hit has occurred (S81; yes), the read module310C outputs a pointer indicating the address of the data field121aor121bof the current number in which the access target data is stored to the host device10C (S82). As a result, a pointer indicating the address of the data field121aor121bof the current number in which the access target data is stored is stored in the CQ132.

When a cache miss occurs (S81; no), the read module310C executes read processing of the access target data from the access area410in the non-volatile memory40(S83).

The read module310C outputs the access target data read from the access area410by the processing of S83to the host device10C (S84). The data output to the host device10C is stored in the buffer area110. As a result, the pointer indicating the address of the buffer area110in which the access target data is stored is stored in the CQ132.

When the processing of S82or the processing of S84ends, the read processing ends (end).

4.4 Effects According to Fourth Embodiment

According to the fourth embodiment, the tag fields330aand330bare managed by the memory controller30C. As a result, the management load on the cache area120C in the host memory12can be reduced.

Incidentally, in a case where the tag field is managed by the host device10C, the tag field having a high access frequency is cached in a hardware cache (not illustrated) in the host device10C. This reduces the margin of the memory area of the hardware cache in the host device10C, which is not preferable.

According to the fourth embodiment, the tag fields330aand330bare offloaded by the memory controller30C. Therefore, it is possible to prevent the tag field from being cached in the memory area of the hardware cache in the host device10C.

5. Fifth Embodiment

Next, an information processing system according to a fifth embodiment will be described. The fifth embodiment is different from the first embodiment in that a miss frequency collection module is implemented in a memory system. In the following description, description of configurations and operations equivalent to those of the first embodiment will be omitted, and configurations and operations different from those of the first embodiment will be mainly described.

5.1 Functional Configuration of Information Processing System

FIG.20is a block diagram illustrating a functional configuration of the information processing system according to the fifth embodiment.FIG.20corresponds toFIG.2in the first embodiment.

An information processing system1D includes a host device10D and a memory system20D. The memory system20D includes a memory controller30D and a non-volatile memory40. Since the functional configuration of the non-volatile memory40is equivalent to that of the first embodiment, the description will be omitted.

The host device10D functions as a buffer area110, a cache area120, a queue130, an application140, and a cache replacement module160D. The memory controller30D functions as a read module310and a miss frequency collection module340. Since the functional configurations except the cache replacement module160D and the miss frequency collection module340are equivalent to those of the first embodiment, the description will be omitted.

The miss frequency collection module340is a module that executes miss frequency collection processing. For example, the miss frequency collection module340counts the number of read requests for each address of access target each time the read request stored in the SQ131is acquired. The miss frequency collection module340stores the collected miss frequency as miss frequency information341. The configuration of the miss frequency information341is equivalent to that of the miss frequency information151in the first embodiment.

The cache replacement module160D determines which data has a high miss frequency among the data stored in the memory system20D based on the miss frequency information341. The cache replacement module160D determines whether or not to replace the data stored in the cache area120with the data determined to have a high miss frequency. Then, in a case where it is determined to replace the data, the cache replacement module160D replaces the data stored in the cache area120in an inactive state with the data having a high miss frequency. If it is determined not to replace the data, the cache replacement module160D does not replace the data.

5.2 Effects According to Fifth Embodiment

According to the fifth embodiment, the miss frequency collection module340is implemented in the memory controller30D. As a result, the load of the miss frequency collection processing can be offloaded from the processor11to the memory controller30D. Therefore, the CPU load for managing the cache area120in the host device10D can be further reduced.

6. Sixth Embodiment

Next, an information processing system according to a sixth embodiment will be described. The sixth embodiment is different from the fifth embodiment in that a cache replacement module is further implemented in a memory system in addition to a miss frequency collection module. In the following description, description of configurations and operations equivalent to those of the fifth embodiment will be omitted, and configurations and operations different from those of the fifth embodiment will be mainly described.

6.1 Functional Configuration of Information Processing System

FIG.21is a block diagram illustrating a functional configuration of the information processing system according to the sixth embodiment.FIG.21corresponds toFIG.20in the fifth embodiment.

An information processing system1E includes a host device10E and a memory system20E. The memory system20E includes a memory controller30E and a non-volatile memory40. Since the functional configuration of the non-volatile memory40is equivalent to that of the fifth embodiment, the description will be omitted.

The host device10E functions as a buffer area110, a cache area120, a queue130, and an application140. The memory controller30E functions as a read module310, a miss frequency collection module340, and a cache replacement module350. Since the functional configurations except the cache replacement module350are equivalent to those of the fifth embodiment, the description will be omitted.

The cache replacement module350determines which data has a high miss frequency among the data stored in the memory system20E based on miss frequency information341. The cache replacement module350determines whether or not to replace the data stored in the cache area120with the data determined to have a high miss frequency. Then, in a case where it is determined to replace the data, the cache replacement module350replaces the data stored in the cache area120in an inactive state with the data having a high miss frequency. If it is determined not to replace the data, the cache replacement module350does not replace the data.

6.2 Effects According to Sixth Embodiment

According to the sixth embodiment, the cache replacement module350is implemented in the memory controller30E. As a result, the load of the cache replacement processing can be offloaded from the processor11to the memory controller30E. Therefore, the CPU load for managing the cache area120in the host device10E can be further reduced.

7. Seventh Embodiment

Next, an information processing system according to a seventh embodiment will be described. The seventh embodiment is different from the first embodiment in that a memory chip in which replacement target data is stored (replacement target memory chip) is specified before specifying the replacement target data in a cache replacement processing. In the following description, description of configurations and operations equivalent to those of the first embodiment will be omitted, and configurations and operations different from those of the first embodiment will be mainly described.

7.1 Cache Replacement Processing

FIG.22is a flowchart illustrating an example of cache replacement processing in a cache replacement module of an information processing system according to a seventh embodiment.FIG.22corresponds toFIG.8in the first embodiment.

When the second period elapses or the number of cache misses reaches the second number (start), a cache replacement module160specifies the replacement target memory chip from the plurality of memory chips CP_1to CP_n based on miss frequency information151(S91).

Specifically, for example, the cache replacement module160specifies a memory chip having the maximum total number of cache misses among the plurality of memory chips CP_1to CP_n.

The cache replacement module160specifies the address of the replacement target data from an access area410in the replacement target memory chip specified in the processing of S91based on the miss frequency information151(S92). Specifically, for example, the cache replacement module160specifies the address of the access area410in which the data having the maximum miss frequency is stored.

The cache replacement module160switches the cache area120to be activated (S93).

The cache replacement module160determines whether or not a reference count value141in an inactive state in the read access processing is “0” (S94).

When the reference count value141in an inactive state is not “0” (S94; no), the cache replacement module160stands by until the reference count value141in an inactive state becomes “0” (S95).

When the reference count value141in an inactive state is “0” (S94; yes), or after the processing of S95, the cache replacement module160determines whether or not to replace the data in the cache area120(S96).

When it is determined that the data in the cache area120is to be replaced (S96; yes), the cache replacement module160causes the memory system20to execute read processing of the replacement target data (S97).

The cache replacement module160causes the replacement target data to be stored in the cache area120in an inactive state corresponding to the address specified in the processing of S92(S98). Accordingly, the data stored up to the present in the cache area120in an inactive state corresponding to the address specified in the processing of S92is evicted.

When it is determined that the data in the cache area120is not to be replaced (S96; no) or the processing of S98ends, the cache replacement processing ends (end).

7.2 Effects According to Seventh Embodiment

According to the seventh embodiment, the cache replacement module160specifies the replacement target memory chip from the plurality of memory chips CP_1to CP_n based on the miss frequency information151. Specifically, the cache replacement module160specifies the memory chip having the highest access frequency as the replacement target memory chip. This makes it possible to avoid concentration of accesses to a specific memory chip. Therefore, a period during which the memory controller30does not operate the plurality of memory chips CP_1to CP_n in parallel can be shortened. Therefore, the performance of the memory system20can be maximized.

8. Modifications and the Like

The above-described first to seventh embodiments are not limited to the above-described examples, and various modifications can be applied.

For example, descriptions have been given on the case where the third to seventh embodiments described above are applied to the first embodiment, but the present invention is not limited thereto. The third to seventh embodiments described above may be applied to the second embodiment. That is, in the cache replacement processing of the third to seventh embodiments described above, whether or not to cache the replacement target data may be determined based on whether the miss frequency of access target data or the access frequency of replacement target data is greater. Furthermore, the third to seventh embodiments described above may be combined with each other.

In addition, for example, in the first to seventh embodiments described above, a case where one memory system is coupled to the host device10via the host bus HB has been described, but the present invention is not limited thereto. A plurality of memory systems20may be coupled to the host device10via the host bus HB.

FIG.23is a block diagram illustrating an example of a hardware configuration of an information processing system according to a modification.FIG.23corresponds toFIG.1in the first embodiment. The information processing system1F includes a host device10and a plurality of memory systems20_1, . . . , and20_m (m is an integer of 2 or more).

The configuration of each of the plurality of memory systems20_1to20_m is equivalent to the configuration of the memory system20in the first embodiment. Each of the plurality of memory systems20_1to20_m is commonly coupled to the host device10via the host bus HB.

In a case where the above-described modification is applied to the fourth embodiment, each of the plurality of memory systems20_1to20_m stores tag fields330aand330bassociated with data fields121aand121bcorresponding to its own access area410. In this case, the data fields121aand121bmay be divided by the number of memory systems20_1to20_m. As a result, the application140C can inquire of the memory system from which the access target data is read when the cache miss occurs among the plurality of memory systems20_1to20_m whether the cache hit has occurred.

In a case where the above-described modification is applied to the fifth embodiment, the miss frequency collection module340of each of the plurality of memory systems20_1to20_m stores the miss frequency information341based on the read request for its own access area410stored in the SQ131. A cache replacement module160D aggregates the miss frequency information341stored in each of plurality of memory systems20_1to20_m and specifies the address of the replacement target data.

In a case where the above-described modification is applied to the sixth embodiment, the cache replacement module350can be provided in each of the plurality of memory systems20_1to20_m. In this case, the cache area120is managed independently for each memory system. That is, the data fields121aand121band the tag fields122aand122bare divided into independent areas for each memory system. Switching between the active state and the inactive state of the cache area120is also independently controlled for each memory system. Then, the cache replacement module350of each of the plurality of memory systems20_1to20_m specifies the address of the replacement target data based on the miss frequency information341collected by its own miss frequency collection module340.

Alternatively, in a case where the above-described modification is applied to the sixth embodiment, the cache replacement module350can be provided in one memory system of the plurality of memory systems20_1to20_m. The cache replacement module350aggregates the miss frequency information341collected by each miss frequency collection module340of the memory systems20_1to20_m and specifies the address of the replacement target data. In this case, the cache area120does not need to be managed independently for each memory system.

Although some embodiments of the present invention have been described, these embodiments have been presented as examples, and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention and are included in the invention described in the claims and the equivalent scope thereof.