Patent ID: 12254954

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Electrically conductive lines are used to connect various pins (or pads) of memory devices to other circuits in an electronic product. These electrically conductive lines tend to behave as transmission lines during high frequency data transfer operations in digital systems. In such digital systems, in which an input pin or pad of an integrated circuit represents an impedance load that does not match the impedance of the transmission line connected to it, a portion of the energy of an incoming signal is reflected back resulting in “noise” that adversely affects signal quality. In other words, the impedance mismatch between the input impedance and transmission line impedance produces an impedance “discontinuity” that causes signal reflections which in turn degrade the incoming signal.

Terminating these lines may reduce the impedance mismatch between the input and the transmission line. Since signal reflections degrade signal integrity, and thereby limit the performance of various electronic products, it is desirable to reduce the signal reflections. Terminating these lines, thus reducing signal reflections, may be referred to herein as line termination. Line termination may be implemented by, for example, introducing a resistive load at, or near, the destination end of a signal line. In some implementations, according to the present disclosure, the aforementioned resistive loads may be on a die rather than external to the die, and may be referred to as on-die termination.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art and having the benefit of the present disclosure will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications that benefit from the acceleration of digital data transfers.

It is noted that references in the specification to “one implementation,” “an implementation,” “an example implementation,” “an illustrative implementation,” “some implementations,” “certain implementations,” etc., indicate that the implementation described may include a particular feature, structure, or characteristic, but every implementation may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same implementation. Further, when a particular feature, structure, or characteristic is described in connection with an implementation, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other implementations whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for the existence of additional factors not necessarily expressly described, again, depending at least in part on context.

Aspects of the present disclosure will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application, and the design and cost constraints imposed on the overall system.

Various terms, expressions, and acronyms are used throughout the present disclosure. For convenience, those various terms, expressions, and acronyms commonly used herein are listed below, and in some instances further include explanations.

Chip, die, and integrated circuit are closely related terms, and their usage is context sensitive. As used herein, integrated circuit refers to active and/or passive circuit elements fabricated together on a die. Dice, as used herein, is the plural form of die. As used herein, die refers to a single integrated circuit. When used alone, the term “die” may refer to a single integrated circuit regardless of whether the die is part of a wafer or has been separated from the wafer. A die that is separated from a wafer may be referred to herein as a singulated die, and a die that is not separated from a wafer may be referred to herein and an unsingulated die.

An input/out pad is referred to herein as an I/O pad. And, as used herein, I/O pad refers to a connection point, or terminal within an integrated circuit through which bidirectional signaling with external components may be performed. Thus, an I/O pad is internally coupled to, at least, an output buffer for driving signals off the die of the I/O pad, and an input circuit for receiving incoming signals from an external transmission line.

As used herein, signal integrity is a general expression relating to performance-degrading problems such as, but not limited to, delays, noise, reflections, ringing, crosstalk, electromagnetic interference (EMI), and the like.

Impedance discontinuity refers to a point in a signal path where there is a change in characteristic impedance.

Transmission lines, which are often used in radio frequency (RF) applications, may be specially constructed to have a nominally uniform characteristic impedance. And, it is known that typical wires, interconnects, or traces on a printed circuit board (PCB), for example, can act like transmission lines when the switching speeds of digital signals on those wires, interconnects, or PCB traces, become very high. But when a transmission line, or a wire, interconnect, or PCB trace behaving as a transmission line, meets an impedance discontinuity, the signals thereon may suffer from signal reflections at the point of impedance discontinuity.

In some electronic product designs, signal reflections may result in errors or failures. These errors or failures may be reduced or eliminated by addressing the impedance discontinuity through the use of termination circuitry. In many instances, termination includes providing a termination resistor at the source, or destination, or source and destination of the signal on the conductor that is behaving as a transmission line.

Although the use of termination resistors may be very helpful in reducing the problems caused by signal reflections, the placement of such resistors consumes area on the printed circuit board, or similar substrate, of electronic systems or subsystems. One approach to saving area on the PCB or other substrate is to move the burden of providing termination resistors onto the integrated circuits, i.e., the die, that are used to build the electronic products. This architectural approach is referred to as on-die termination (ODT).

As used herein, On-Die Termination (ODT) refers to a process of providing a termination resistance to an electrical path to improve signal integrity, typically by reducing signal reflections through a reduction in an impedance mismatch between the electrical path acting as a transmission line, and the input impedance of the load to which the transmission line is connected.

As used herein, motherboard termination refers to an electrical component or circuit disposed on a motherboard. More generally, this can be thought of as applying to any PCB or similar substrate upon or within which termination resistors are placed.

As used herein, On-Die Termination circuit (ODT circuit) refers to the circuitry used to implement the impedance mismatch reduction function of the ODT process. Many ODT circuit configurations are possible, and a number of different ODT circuit configurations have been used commercially. ODT circuits are typically configured to terminate a transmission line by modifying the input impedance “seen” by the transmission line to which the pad is coupled. ODT circuits are integrated on the same die as the pad, and are therefore referred to as on-die termination circuits.

SSD refers to a solid-state drive. An SSD is a data storage having no moving parts. This distinguishes an SSD from storage devices such as, for example, hard disk drives, compact disc drives, and digital video disc drives. SSDs commonly use non-volatile memory devices such as, but not limited to, flash memory devices.

FIG.1is a high-level block diagram of one approach to providing an ODT configuration value to an ODT configuration circuit. Generally, an ODT Rtt circuit block may provide one of several possible termination resistances (Rtt). The termination resistance provided by the ODT Rtt circuit block may be determined by enabling and disabling various pathways within the ODT Rtt circuit block, so as to “program” or “configure” the ODT Rtt circuit block to effectively provide the desired termination resistance.

Referring toFIG.1, a functional architecture100for determining the desired magnitude of, and providing, a termination resistance includes an ODT configuration value provider circuit102, which can provide ODT configuration values104-1,104-2, . . .104-n, where n is a positive integer. In functional architecture100, a logic block103is configured to provide a select signal to an n-to-1 multiplexer106. ODT configuration values104-1,104-2, . . .104-nare coupled to corresponding input terminals of n-to-1 multiplexer106, which outputs one of the n ODT configuration values104-1,104-2, . . .104-n. The output of n-to-1 multiplexer106is coupled to ODT configuration control logic108A. ODT configuration control logic108A is coupled to ODT Rtt circuit block108B. ODT configuration control logic108A generates and provides control signals to ODT Rtt circuit block108B, based on the selected ODT configuration value received from n-to-1 multiplexer106. ODT Rtt circuit block108B, responsive to the control signals it receives from ODT configuration control logic108A, is configured to provide the desired termination resistance.

As noted above,FIG.1illustrates a functional architecture for configuring an ODT Rtt circuit block108B. That is, there are many circuit options for implementing the various logical operations of functional architecture100. For example, ODT configuration value provider circuit102may store ODT configuration values104-1,104-2, . . .104-n, in a non-volatile memory such as, but not limited to, a flash memory, which may be factory programmed, or programmed by a flash memory controller during an initialization operation. Alternatively, ODT configuration values104-1,104-2, . . .104-n, may be hardwired. In a further alternative, ODT configuration values104-1,104-2, . . .104-n, may be stored in a volatile memory such as, but not limited to, a static random-access memory (SRAM), a dynamic random-access memory (DRAM), or the bits of a register (either static or dynamic). Such volatile memories may be written to during an initialization procedure, or similar update operation. In a further example, the functional architecture of selecting1of n possible ODT configuration values104-1,104-2, . . .104-n, is illustrated with n-to-1 multiplexer106. However, in implementations that use addressable memories (regardless of whether these addressable memories are volatile or non-volatile) to store ODT configuration values104-1,104-2, . . .104-n, a multiplexer is not needed and the output of logic block103can be used as at least a portion of the memory address to access the stored ODT configuration values.

FIG.2is a high-level block diagram illustrating a logical architecture200of an ODT arrangement compatible with an NV-DDR3 architecture of the Open NAND FLASH Interface (ONFI) specification.FIG.2highlights a feature of the NV-DDR3 architecture of the Open NAND FLASH Interface (ONFI) specification that takes note of the fact that in a memory system or a memory subsystem, some non-volatile memory dice are non-targets and some non-volatile memory dice are targets for a given memory transaction; and sets the ODT termination resistance to be the same nominal value for both targets and non-targets.

Still referring toFIG.2, logical architecture200provides a single ODT configuration value in block202. Block202of logical architecture200may provide a digital signal of one or more bits to the ODT configuration control logic for setting the desired termination resistance. As indicated inFIG.2, regardless of whether the ODT circuitry on a non-volatile memory die is intended to operate as a target (block204) or as a non-target (block206) in a particular memory transaction, the same ODT configuration value is used. Because the actual input load characteristics between a target and non-target may be different, data transfer rates between the non-volatile memory dice and their controller in a non-volatile memory system or subsystem, may be sub-optimal. This is unlike various implementations in accordance with the present disclosure that provide ODT configuration values to targets and non-targets that may be individually set to accommodate different input load conditions at different dice within the non-volatile memory system, or subsystem.

FIG.3Ais a high-level schematic diagram showing an arrangement300of NAND flash memory dice having an ODT capability, arrangement300having a common data channel. Arrangement300includes a first package302of flash memory dice304,306, a second package308of flash memory dice310,312, and a third package314of flash memory dice316,318. Flash memory dice304,306have their data pads coupled together, and have their chip-enable pads coupled together. Flash memory dice310,312have their data pads coupled together, and have their chip-enable pads coupled together. Flash memory dice316,318have their data pads coupled together, and have their chip-enable pads coupled together. First package302is coupled to a first chip-enable signal320; second package308is coupled to a second chip-enable signal322; and third package314is coupled to a third chip-enable signal324. Flash memory dice304,306,310,312,316, and318are all coupled to data channel326.

Still referring toFIG.3A, in the case where flash memory die304in first package302is a target for a memory operation, and all the other flash memory dice306,310,312,316,318, are not a target, and the load on the target and non-target pads are not all the same, then better signal integrity, and thus better performance, may be obtained by having the ability to individually configure the termination resistance on the different dice. That is, rather than having a single ODT configuration value, better signal integrity may be obtained by individually configuring the ODT termination resistance of each flash memory die. In some implementations of the present disclosure, a target pad is configured to have a first termination resistance, and non-target pads are configured to have a second termination resistance. In other implementations of the present disclosure, a target pad is configured to have a first termination resistance, and non-target pads may be configured to have one of a plurality of termination resistances.

FIG.3Bis a high-level schematic diagram showing an arrangement of NAND flash memory dice having an ODT capability, and a NAND flash memory controller coupled to the NAND flash memory dice.FIG.3Bis very similar toFIG.3A, but further includes a memory controller328coupled to the memory die304,306,310,312,316, and318. Those skilled in the art will recognize that although this illustrative implementation uses NAND flash memory and a NAND flash memory controller, alternative implementations that provide on-die termination in accordance with the present disclosure may be constructed with different types of memory technologies.

FIG.4is a block diagram illustrating the logical architecture400of an ODT arrangement similar to that shown inFIG.2, except that different ODT configuration values are provided for targets as compared to non-targets.FIG.4shows that instead of using the same ODT configuration value for both target and non-target pins (as indicated inFIG.2), providing the ability to use a different ODT configuration value for target and non-target pins allows a greater flexibility, and a greater degree of control for setting the termination resistance. By enabling independent control of the termination resistance at each of the target and non-target pins, higher signal quality may be obtained, which in turn contributes to higher I/O performance.

Still referring toFIG.4, logical architecture400includes a first logical block402that provides an ODT configuration value for a target pin. This ODT configuration value for a target pin is communicated by way of a first communication pathway403to first ODT Rtt circuit block404. Logical architecture400further includes a second logical block406that provides an ODT configuration value for a non-target pin. This ODT configuration value for a non-target pin is communicated by way of a second communication pathway405to second ODT Rtt circuit block408. In accordance with logical architecture400, different ODT configuration values are provided, respectively, to target and non-target pins.

FIG.5is a high-level block diagram illustrating a logical architecture500for selecting different ODT values based on whether a non-volatile memory die is a target or non-target for a memory operation. Logical architecture500provides for determining whether the non-volatile memory die is a target or non-target, and based at least in part on that determination, provides a corresponding ODT configuration value to a configuration control logic circuit. In turn, the configuration control logic circuit, which is coupled to an ODT Rtt circuit, configures the ODT Rtt circuit to provide an on-die termination resistance, the magnitude of which is based, at least in part on the ODT configuration value received by the configuration control logic circuit.

Still referring toFIG.5, logical architecture500includes an ODT configuration value provider block501. ODT configuration value provider block501may be configured to provide ODT configuration values502-1,502-2. In this example, ODT configuration values502-1and502-2represent, respectively, a first configuration value for use when the non-volatile memory die is a target in a memory operation, and a second configuration value for use when the non-volatile memory die is a non-target in a memory operation. In some implementations, a control logic block508, which is part of ODT configuration value provider block501, is coupled to provide control signals503-1and503-2for loading or setting, ODT configuration values502-1and502-2respectively.

Logical architecture500includes a mechanism for providing a selected one of ODT configuration values502-1and502-2, to an ODT configuration control circuit506A. In this example, the mechanism for providing the selected one of ODT configuration values502-1and502-2, to ODT configuration control circuit506A is 2-to-1 multiplexer504. A control logic block508generates and provides a select control signal to 2-to-1 multiplexer504. In this example, the select control signal is a digital signal that is communicated to 2-to-1 multiplexer504via pathway509. As shown inFIG.5, ODT configuration control circuit506A is coupled to ODT Rtt circuit block506B. ODT configuration control circuit506A generates and provides control signals to ODT Rtt circuit block506B, based on the selected ODT configuration value received from 2-to-1 multiplexer504. ODT Rtt circuit block506B, responsive to the control signals it receives from ODT configuration control circuit506A, is configured to provide the desired termination resistance.

As noted above,FIG.5illustrates a logical architecture for configuring an ODT Rtt circuit block506B. That is, there are many circuit options for implementing the various logical operations of logical architecture500. For example, ODT configuration value provider block501may store ODT configuration values502-1,502-2, in a non-volatile memory such as, but not limited to, a flash memory, which may be factory programmed, or programmed by a flash memory controller during an initialization operation. Alternatively, ODT configuration values502-1,502-2, may be hardwired. In a further alternative, ODT configuration values502-1,502-2, may be stored in a volatile memory such as, but not limited to, an SRAM, a DRAM, or the bits of a register (either static or dynamic). Such volatile memories may be written during an initialization procedure, or similar update operation, to set the ODT configuration values. In a further example, the logical architecture of selecting1of2possible ODT configuration values502-1,502-2, is illustrated with 2-to-1 multiplexer504. However, in implementations that use addressable memories (regardless of whether these addressable memories are volatile or non-volatile) to store ODT configuration values502-1,502-2, a multiplexer is not needed, and the output of control logic block508can be used as at least a portion of the memory address to access the stored ODT configuration values502-1,502-2.

FIGS.6and7are similar in that they each illustrate non-volatile memory subsystems wherein the non-volatile memory dice are each coupled in common to a data channel, and each coupled in common to an ID channel. However,FIGS.6and7, are different in that the arrangement of the chip-enable (CE) channel(s) is different from the implementations shown inFIGS.6and7. As described in more detail below, the CE channel shownFIG.6is coupled to all of the non-volatile memory dice, whereas there are two separate CE channels (CE channel 0 and CE channel 1) shown inFIG.7, with a first portion of the non-volatile memory dice coupled in common to CE channel 0, and a second portion of the non-volatile memory dice coupled in common to CE channel 1.

FIG.6is a high-level block diagram illustrating a non-volatile memory subsystem600including a plurality of non-volatile memory dice coupled to share a data channel, an ID channel, and a CE channel. Non-volatile memory subsystem600can benefit from implementations of the present disclosure in terms of improved signal integrity. In this illustrative implementation, non-volatile memory subsystem600includes a non-volatile memory device-0602, a non-volatile memory device-1604, a non-volatile memory device-2606, a non-volatile memory device-3608, a non-volatile memory device-4610, a non-volatile memory device-5612, a non-volatile memory device-6614, and a non-volatile memory device-7616. It will be appreciated that non-volatile memory devices602through616may be, but are not limited to, flash memory devices, NAND flash memory devices, three-dimensional (3D) NAND devices, or 3D phase-change material (PCM) memory devices.

Still referring toFIG.6, each of non-volatile memory devices602,604,606,608,610,612, and614, are coupled in common to an ID channel620, a CE channel622, and a data channel624. Non-volatile memory devices602,604,606,608,610,612, and614, may be, but are not limited to, planar flash memories, 3D flash memories, or 3D phase-change material (PCM) memories. In this illustrative implementation, all of non-volatile memory devices602,604,606,608,610,612, and614, include ODT circuitry, and may therefore participate in providing termination for data channel624to which they are all connected in common. For example, if device-0602, is a target for a memory operation and device-1 through device-7 are non-targets, then not only can targeted device-0 participate in providing termination resistance, but device-1 through device-7 may also participate in providing termination resistance. And, because the ODT configuration value for the non-target termination resistance may be set individually for each non-volatile memory die, the ODT performance of the non-target dice may be based, at least in part, on the relative position of the non-target die, the wire length to the data channel, and any other factor that would result in selecting a “better” ODT configuration value. The ODT behavior of non-volatile memory dice may be, but is not required to be, determined based, at least in part, on the ID channel and memory operation to be performed.

FIG.7is a block diagram illustrating another non-volatile memory subsystem700including a plurality of non-volatile memory dice coupled to share a data channel and an ID channel; and a first portion of the plurality of non-volatile memory dice share a first chip-enable channel, and a second portion of the plurality of non-volatile memory dice share a second chip-enable channel. Non-volatile memory subsystem700can benefit from implementations of the present disclosure. In this illustrative implementation, non-volatile memory subsystem700includes a non-volatile memory device-0702, a non-volatile memory device-1704, a non-volatile memory device-2706, a non-volatile memory device-3708, each of which is coupled in common to CE channel 0722. Non-volatile memory subsystem700further includes a non-volatile memory device-0710, a non-volatile memory device-1712, a non-volatile memory device-2714, and a non-volatile memory device-3716, each of which is coupled in common to CE channel 1.

It will be appreciated that non-volatile memory devices702through716may be, but are not limited to, flash memory devices, NAND flash memory devices, three-dimensional (3D) NAND flash memory devices, or 3D phase-change material (PCM) memory devices.

Still referring toFIG.7, each of non-volatile memory devices702,704,706,708,710,712,714, and716, are coupled in common to an ID channel720, and a data channel724. Further, each of non-volatile memory devices702,704,706,708are coupled in common to a CE channel-0722; and each of non-volatile memory devices710,712,714,716are coupled in common to a CE channel-1718. In some implementations, the ODT configuration values for non-volatile memory devices702,704,706,708, which are coupled to CE channel 0 may be different from the ODT configuration values of non-volatile memory devices710,712,714,716, which are coupled to CE channel 1.

FIG.8is a flow diagram of an illustrative method800in accordance with the present disclosure. Illustrative method800configures an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice in a non-volatile memory system, or subsystem, that has a plurality of non-volatile memory dice having one or more pads coupled in common with each other. In some implementations, the one or more pads coupled in common with each other are further coupled to a data channel. Method800includes determining802, by each non-volatile memory die of the plurality of non-volatile memory dice, whether that non-volatile memory die is a target or a non-target for an operation, for example, a memory operation in which data may be transferred over the data channel. Method800also includes setting804, by each non-volatile memory die of the plurality of non-volatile memory dice that determines it is a target, a first on-die termination configuration value, and setting806, by each non-volatile memory die of the plurality of non-volatile memory dice that determines it is a non-target, a second on-die termination configuration value. In some implementations, rather than simply setting the second on-die termination configuration value for all the non-target non-volatile memory dice, each of the non-target non-volatile memory dice may set their on-die termination configuration value independently on the other non-target non-volatile memory dice. Method800further includes configuring808, by each target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value, and concurrently with the configuring by each target non-volatile memory die, configuring810, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least in part, on the second on-die termination configuration value. In some implementations, configuring the on-die termination circuit may be further based, at least in part, on junction temperature of the circuit, ambient temperature, power supply voltage, or other factors that may affect signal integrity on the data channel. In some implementations, one or more non-target on-die termination circuits may be disabled rather than configured to provide a particular input impedance.

FIG.9is a flow diagram of an illustrative method900in accordance with the present disclosure. Illustrative method900is similar to method800but further includes receiving signals from a flash memory controller. Method900configures an on-die termination circuit in each flash memory die of a plurality of flash memory dice in a flash memory system, or subsystem, that has a plurality of flash memory dice having one or more pads coupled in common with each other. In some implementations, the one or more pads coupled in common with each other are further coupled to a data channel. Method900includes determining902, by each flash memory die of the plurality of flash memory dice, whether that flash memory die is a target or a non-target for an operation, for example, a memory operation in which data may be transferred over the data channel. Method900also includes setting904, by each flash memory die of the plurality of flash memory dice that determines it is a target, a first on-die termination configuration value, and setting906, by each flash memory die of the plurality of flash memory dice that determines it is a non-target, a second on-die termination configuration value. In some implementations, rather than simply setting the second on-die termination configuration value for all the non-target flash memory dice, each of the non-target flash memory dice may set their on-die termination configuration value independently on the other non-target flash memory dice. Method900further includes configuring908, by each target flash memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value, and concurrently with the configuring by each target flash memory die, configuring910, by each non-target flash memory die, its corresponding on-die termination circuit to provide a second impedance based, at least in part, on the second on-die termination configuration value. In some implementations, configuring the on-die termination circuit may be further based, at least in part, on junction temperature of the circuit, ambient temperature, power supply voltage, or other factors that may affect signal integrity on the data channel. In some implementations, one or more non-target on-die termination circuits may be disabled rather than configured to provide a particular input impedance.

In various implementations, the non-volatile memory dice may be, but are not limited to, NAND flash memories, 3D NAND flash memories, or 3D phase-change-memories, for example. Further, the mechanism by which these non-volatile memories store data may be, but is not limited to, floating gate, charge-trap, and phase-change. In these illustrative implementations, whether a non-volatile memory die is a target or non-target is determined by logical operations performed within that die. Various implementations may perform such logical operations by, for example, logic circuitry, or logic circuitry together with an embedded controller executing program code to perform at least a portion of the logical operations resulting in the determination of whether the aforementioned non-volatile memory die is a target or a non-target for a particular memory access operation.

In some implementations, determining by each non-volatile memory die of the plurality of non-volatile memory dice, whether that non-volatile memory die is a target or a non-target for an operation. Include receiving one or more signals from a non-volatile memory controller, such as but not limited to a flash memory controller.

In some implementations, the on-die termination configuration value may be a digital value, and the digital value directs on-die termination configuration circuitry to configure the on-die termination circuit to provide the termination resistance specified by the on-die termination configuration value.

In some implementations, the first memory area is a first register, and the second memory area is a second register.

In some implementations, the on-die termination circuit is configured provide a first termination impedance configuration responsive, at least in part, to the non-volatile memory device being a target, and the on-die termination circuit is configured provide a second termination impedance configuration responsive, at least in part, to the non-volatile memory device being a non-target, and the first termination impedance configuration and the second termination impedance configuration are different from each other.

The foregoing description of the specific implementations will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific implementations, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Implementations of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may set forth one or more but not all exemplary implementations of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the subjoined claims in any way.

Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain implementations include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

The breadth and scope of the present disclosure should not be limited by any of the above-described illustrative implementations, but should be defined only in accordance with the subjoined claims and their equivalents.