Patent ID: 12232325

DETAILED DESCRIPTION

Embodiments provide a semiconductor storage device of which an operation reliability may be improved.

In general, according to one embodiment, a semiconductor storage device includes: a first conductive layer that is stacked on a substrate in a first direction perpendicular to a surface of the substrate and extends in a second direction orthogonal to the first direction; a second conductive layer that is stacked on the substrate in the first direction, extends in the second direction, and is separated from the first conductive layer in a third direction orthogonal to the second direction; a third conductive layer that is stacked on the substrate in the first direction, extends in the second direction, and is separated from the first conductive layer in the third direction; a contact plug that is provided on the substrate and extends in the first direction; a first insulating layer that extends in the first direction between the second conductive layer and the third conductive layer, is continuously provided around the contact plug, and surrounds a first area in which the contact plug is disposed; and a second area that is separated from the first area in the second direction and includes a pillar penetrating the first conductive layer in the first direction. The second conductive layer extends in the second direction between the first area and the second area, further extends in the third direction, and is connected to the first conductive layer. The third conductive layer extends in the second direction on the opposite side of the first area to the second area, further extends in the third direction, and is connected to the first conductive layer.

Hereinafter, embodiments will be described with reference to the drawings. In the following descriptions, components having a similar function or configuration will be denoted by the same reference numerals. Further, each embodiment to be described hereinafter is an example of a device or a method for embodying the technical idea of the present disclosure, and does not limit materials, shapes, structures, arrangements and others of components to those described in the embodiment.

Each functional block may be implemented as hardware, computer software, or a combination thereof. The respective functional blocks may not be necessarily discriminated as in the examples described hereinafter. For example, some functions may be executed by other functional blocks than the illustrated function blocks. Furthermore, the illustrated functional blocks may be further divided into smaller functional sub-blocks. Herein, a three-dimensional stacking-type NAND flash memory in which memory cell transistors are stacked above a semiconductor substrate will be described as an example of the semiconductor storage device. In the descriptions herein, the memory cell transistors may be referred to as memory cells.

1. First Embodiment

A semiconductor storage device according to a first embodiment will be described below.

1.1 Circuit Block Configuration of Semiconductor Storage Device

First, the circuit block configuration of the semiconductor storage device according to the first embodiment will be described. The semiconductor storage device of the first embodiment is a NAND type flash memory capable of storing data in a nonvolatile manner.

FIG.1is a block diagram illustrating the circuit configuration of the semiconductor storage device of the first embodiment. The semiconductor storage device1includes a memory cell array10, a row decoder11, a driver12, a sense amplifier13, an address register14, a command register15, an input/output circuit16, and a sequencer17. For example, an external device (e.g., a host device or a controller) (not illustrated) is connected to the semiconductor storage device1via an external NAND bus.

1.1.1 Configuration of Each Block

The memory cell array10includes a plurality of blocks BLK0, BLK1, BLK2, . . . , and BLKn (n is an integer of 0 or more). Each of the plurality of blocks BLK0to BLKn includes a plurality of memory cell transistors associated with rows and columns. Each of the memory cell transistors are able to store data in a nonvolatile manner and electrically rewrite data. In the memory cell array10, a plurality of word lines, a plurality of bit lines, a source line and the like are arranged to control voltages applied to the memory cell transistors. Hereinafter, a block BLK refers to each of the blocks BLK0to BLKn. Details of the memory cell array10and the block BLK will be described later.

The row decoder11receives a row address from the address register14and decodes the row address. The row decoder11selects one of the blocks BLK based on the decoding result of the row address, and further selects a word line in the selected block BLK. Furthermore, the row decoder11transfers a plurality of voltages necessary for a write operation, a read operation, and an erase operation to the memory cell array10.

The driver12supplies a plurality of voltages to the selected block BLK via the row decoder11.

The sense amplifier13detects and amplifies data read from a memory cell transistor into a bit line when data is read. Further, the sense amplifier13transfers write data DAT to a bit line when data is written.

The address register14stores an address ADD received from, for example, an external device. The address ADD includes a block address that specifies a block BLK of an operation target, and a page address that specifies a word line of an operation target in the specified block. The command register15stores a command CMD received from an external device. The command CMD includes, for example, a write command that instructs the sequencer17to perform a write operation, and a read command that instructs the sequencer17to perform a read operation.

The input/output circuit16is connected to an external device via a plurality of input/output lines (DQ lines). The input/output circuit16receives the command CMD and the address ADD from the external device. The input/output circuit16transmits the received command CMD to the command register15, and transmits the received address ADD to the address register14. Further, the input/output circuit16transmits and receives data DAT to and from the external device.

The sequencer17receives a control signal CNT from an external device. The control signal CNT includes a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn and the like. The “n” appended to a signal name indicates that the signal is a low active signal.

The sequencer17controls the operation of the semiconductor storage device1based on the command CMD stored in the command register15and the control signal CNT. Specifically, the sequencer17controls the row decoder11, the driver12, and the sense amplifier13based on a write command received from the command register15to perform a write into a plurality of memory cell transistors specified by the address ADD. The sequencer17also controls the row decoder11, the driver12, and the sense amplifier13based on a read command received from the command register15to perform a read from a plurality of memory cell transistors specified by the address ADD.

1.1.2 Circuit Configuration of Memory Cell Array10

Next, the circuit configuration of the memory cell array10will be described. As described above, the memory cell array10includes the plurality of blocks BLK0to BLKn. Here, a circuit configuration of one of the blocks, BLK, is described, and a circuit configuration of each of the other blocks is substantially similar.

FIG.2is a circuit diagram of one block BLK in the memory cell array10. The block BLK includes a plurality of string units. Here, a case where the block BLK includes string units SU0, SU1, SU2, . . . , and SU7will be described as an example. Each of the string units SU0to SU7corresponds to one page which is, for example, a write unit.FIG.2illustrates the string units SU0to SU3. Any number of string units can be included in the block BLK. Hereinafter, a string unit SU refers to each of the string units SU0to SU7.

The string units SU0to SU7include the even-numbered string units SU0, SU2, SU4, and SU6and the odd-numbered string units SU1, SU3, SU5, and SU7. Hereinafter, each of the even-numbered string units SU0, SU2, SU4, and SU6will be denoted by SUe, and each of the odd-numbered string units SU1, SU3, SU5and SU7is denoted by SUo.

The even-numbered string unit SUe includes a plurality of NAND strings NSe. The odd-numbered string unit SUo includes a plurality of NAND strings NSo. When the NAND strings NSe and NSo are not distinguished from each other, each NAND string will be referred to as a NAND string NS.

The NAND string NS includes, for example, eight memory cell transistors MT0, MT1, MT2, . . . , and MT7, and select transistors ST1and ST2. Here, a case where the NAND string NS includes eight memory cell transistors is described as an example, but any number of memory cell transistors can be included in the NAND string NS.

Each of the memory cell transistors MT0to MT7includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The memory cell transistors MT0to MT7are connected in series between the source of the select transistor ST1and the drain of the select transistor ST2. The memory cell transistor MT may be of a metal-oxide-nitride-oxide-silicon (MONOS) type using an insulating film as the charge storage layer, or a floating gate (FG) type using a conductive layer as the charge storage layer. Hereinafter, a memory cell transistor MT refers to each of the memory cell transistors MT0to MT7.

The gates of the select transistors ST1in the respective string units SU0to SU7are connected to select gate lines SGD0, SGD1, SGD2, . . . , SDG7, respectively. Each of the select gate lines SGD0to SGD7is independently controlled by the row decoder11.

The gate of the select transistor ST2in each of the even-numbered string units SU0, SU2, . . . , and SU6is connected to, for example, a select gate line SGSe. The gate of the select transistor ST2in each of the odd-numbered string units SU1, SU3, . . . , and SU7is connected to, for example, a select gate line SGSo. For example, the select gate lines SGSe and SGSo may be connected to each other to be the same wire, or may be separate wires.

In addition, the control gates of the memory cell transistors MT0to MT7in the string units SUe in the same block BLK are connected to word lines WLe0, WLe1, WLe2, . . . , and WLe7, respectively. Meanwhile, the control gates of the memory cell transistors MT0to MT7in the string units SUo are connected to word lines WLo0, WLo1, WLo2, . . . , and WLo7, respectively. Each of the word lines WLe0to WLe7and WLo0to WLo7is independently controlled by the row decoder11.

The block BLK is, for example, an erase unit of data. That is, data stored in the memory cell transistors MT in the same block BLK are collectively erased. In addition, data may be erased in the unit of the string unit SU or in the unit smaller than string unit SU.

Further, the drains of the select transistors ST1of the NAND strings NS in the same column in the memory cell array10are connected to each corresponding bit line of the bit lines BL0to BL(m−1). Here, m is a natural number of 1 or more. That is, each of the bit lines BL0to BL(m−1) commonly connects the NAND strings NS to each other among the plurality of string units SU. Furthermore, the sources of the plurality of select transistors ST2are connected to a source line SL.

That is, the string unit SU includes a plurality of NAND strings NS which are connected to the different bit lines BL and connected to the same select gate line SGD. In addition, the block BLK also includes the plurality of string units SUe which share the word lines WLe and the plurality of string units SUo which share the word lines WLo. Further, the memory cell array10includes the plurality of blocks BLK which share the bit lines BL.

In the memory cell array10, the select gate lines SGS, the word lines WL, and the select gate lines SGD are stacked in an order above the semiconductor substrate, so as to form the memory cell array10in which the select transistors ST2, the memory cell transistors MT, and the select transistors ST1are three-dimensionally stacked.

In addition, the memory cell array110may have other configurations. That is, the configuration of the memory cell array110is described in, for example, U.S. patent application Ser. No. 12/407,403 filed on Mar. 19, 2009 and entitled “THREE DIMENSIONAL STACKED NONVOLATILEN SEMICONDUCTOR MEMORY,” Further, the configuration of the memory cell array is described in U.S. patent application Ser. No. 12/406,524 filed on Mar. 18, 2009 and entitled “THREE DIMENSIONAL STACKED NONVOLATILEN SEMICONDUCTOR MEMORY,” U.S. patent application Ser. No. 12/679,991 filed on Mar. 25, 2010 and entitled “NON-VOLATILEE SEMICONDUCTOR STORAGE DEVICE METHOD AND METHOD OF MANUFACTURING THE SAME,” and U.S. patent application Ser. No. 12/532,030 filed on Mar. 23, 2009 and entitled “SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME.” These patent applications are hereby incorporated by reference in their entirety.

1.2 Layout and Structure of Semiconductor Storage Device

Next, the layout and structure of the semiconductor storage device1of the first embodiment will be described.

1.2.1 Outline of Layout and Structure of Semiconductor Storage Device

FIG.3is a schematic view of the layout of the semiconductor storage device of the first embodiment. InFIG.3and the subsequent figures, the two directions which are orthogonal to each other while being in parallel with the surface of the semiconductor substrate are defined as the X direction and the Y direction, respectively, and the direction orthogonal to a plane including the X direction and the Y direction (XY plane) is defined as a Z direction (stacking direction).

The semiconductor storage device1includes a memory array area100and hookup areas200eand200o. The hookup areas200eand200oare disposed at both ends of the memory array area100in the X direction such that the memory array area100is interposed between the hookup areas200eand200oin the X direction. That is, the hookup area200eis disposed at one end of the memory array area100in the X direction, and the hookup area200ois disposed at the other end of the memory array area100in the X direction.

The memory array area100includes the plurality of blocks BLK0to BLKn, andFIG.3represents the blocks BLK0to BLK3. The blocks BLK0to BLK3are arranged in an order in the Y direction.

1.2.1.1 Layout of Memory Array Area and Layout of Hookup Areas

Next, the layout of the memory array area100and the hookup areas200eand200oin the semiconductor storage device1will be described.

FIG.4is a view illustrating the outline of the block BLK inFIG.3, and is a planar layout illustrating a portion of the memory array area100and the hookup areas200eand200o. To explain the outline of the layout of the block BLK,FIG.4omits a slit area and a contact area formed in the memory array area100, and illustrates the layout of memory trenches MST, memory pillars MP, and select gate lines SGD (or word lines WL). The detailed layout of the memory array area100will be described later with reference toFIG.10and the subsequent figures.

As illustrated inFIG.4, the memory array area100is provided, and the hookup areas200eand200oare provided at one end and the other end of the memory array area100, respectively. InFIG.4, the word line WLe7of the word lines WLe0to WLe7is illustrated as an example, and the word line WLo7of the word lines WLo0to WLo7is illustrated as an example.

The block BLK includes the string units SU0to SU7as described above. The extensions of the select gate lines SGD0, SGD2, SGD4, and SGD6of the string units SU0, SU2, SU4and SU6, that is, the string units SUe, and the word line WLe7are provided in the hookup area200e. Contact plugs CP1econnect the select gate lines SGD0, SGD2, SGD4, and SGD6, respectively, to an upper layer wire (not illustrated). The word line WLe7is provided below the select gate lines SGD0, SGD2, SGD4, and SGD6.

The extensions of the select gate lines SGD1, SGD3, SGD5, and SGD7of the string units SU1, SU3, SU5, and SU7, that is, the string units SUo, and the word line WLo7are provided in the hookup area200o. Contact plugs CP1oconnect the select gate lines SGD1, SGD3, SGD5, and SGD7, respectively, to an upper layer wire (not illustrated). The word line WLo7is provided below the select gate lines SGD1, SGD3, SGD5, and SGD7.

The block BLK includes a plurality of memory trenches MST, a plurality of memory pillars MP, a plurality of select gate lines SGD, and a plurality of word lines WL (not illustrated). The plurality of memory trenches MST extend in the X direction and are arranged at predetermined intervals in the Y direction. Each memory trench MST is an insulating area (or an insulating layer) and includes, for example, a silicon oxide layer.

The plurality of memory pillars MP are arranged in a staggered manner in the X direction and the Y direction on the plurality of memory trenches MST. That is, the plurality of memory pillars MP are arranged at predetermined intervals in the X direction on each memory trench MST. Assuming that two adjacent memory trenches MST are a first memory trench and a second memory trench, the memory pillars MP arranged on the second memory trench are arranged at positions shifted by half pitch from the memory pillars MP arranged on the first memory trench.

A conductive layer20is provided between adjacent memory trenches MST. The conductive layers20include conductive layers20-0to20-15to be described later. The conductive layers20are connected to each other in the hookup area200eor200o, and correspond to the select gate lines SGD. The word lines WLe7and WLo7are provided below the select gate lines SGD.

In the hookup areas200eand200o, slit areas STH1are provided on the memory trenches MST. The slit areas STH1are alternately arranged on the memory trenches MST arranged in the Y direction. Each slit area STH1is an area in which an insulating material is embedded in a hole used in a replacement process for forming the conductive layers20. The slit area STH1is an insulating area (or insulating layer) and includes, for example, a silicon oxide layer.

In the hookup areas200eand200o, slit areas STH2are provided on the memory trenches MST and the conductive layers20. The slit areas STH2are arranged in a staggered manner in the Y direction. Each slit area STH2is an area in which an insulating material is embedded in a hole used in a replacement process for forming the conductive layers20, and an area that isolates the conductive layers20into the select gate lines SGDe and SGDo in alternate and insulating manners. The replacement process is, for example, a process of removing sacrificial layers (e.g., insulating layers) present in areas where the word lines WL and the select gate lines SGD are to be disposed, and replacing the areas with conductive layers (e.g., tungsten (W)). The slit area STH2is an insulating area (or insulating layer) and includes, for example, a silicon oxide layer.

In addition, in the hookup areas200eand200o, contact plugs are connected to the plurality of stacked word lines, respectively, but are omitted here.

1.2.1.2 Cross-Sectional Structures of Memory Array Area and Hookup Areas

Next, the sectional structures of the memory array area100and the hookup areas200eand200owill be described.FIG.5is a cross-sectional view of the block BLK which is taken along the Y direction. In addition, the insulating layers between the conductive layers and on the conductive layers, and a peripheral circuit between the semiconductor substrate and the memory cell array are omitted.

As illustrated inFIG.5, conductive layers22are provided above the semiconductor substrate (e.g., a p-type well area)23. The conductive layers22function as the select gate lines SGSe and SGSo. Eight conductive layers21are stacked above the conductive layers22along the Z direction. Each conductive layer21includes conductive layers21-0to21-15, and the eight conductive layers21function as the word lines WLe0to WLe7or WLo0to WLo7.

The conductive layers20are provided above the conductive layers21. The conductive layers20include the conductive layers20-0to20-15, and function as the select gate lines SGD0to SGD7.

The memory trenches MST and the memory pillars MP are alternately provided in the Y direction. The memory trenches MST and the memory pillars MP are extended in the Z direction so as to reach from the conductive layers20to a source line SL (not illustrated) below the conductive layers22.

The conductive layers22are arranged such that a memory trench MST or a memory pillar MP is interposed between the conductive layers22, and alternately function as the select gate line SGSe and SGSo. Similarly, the conductive layers21are arranged such that a memory trench MST or a memory pillar MP is interposed between the conductive layers21, and alternately function as the word lines WLe and WLo.

Contact plugs24are provided on the memory pillars MP. Furthermore, a conductive layer25is provided on the contact plugs24along the Y direction. The conductive layer25functions as the bit line BL.

The cross section of the block BLK which is taken along the X direction will be described below.

FIG.6is a cross-sectional view of the block BLK which is taken along the X direction, and illustrates a cross-sectional structure of an area that passes the memory pillars MP along the select gate line SGD0inFIG.4, as an example. In addition, the insulating layers between the conductive layers and on the conductive layers, and a peripheral circuit between the semiconductor substrate and the memory cell array are omitted.

As described above with reference toFIG.5, the conductive layers22,21, and20are provided in an order above the semiconductor substrate23. In addition, the memory array area100is the same as described above with reference toFIG.5.

As illustrated inFIG.6, in the hookup area200e, the conductive layers20to22extend, for example, in a step-like manner. That is, in the hookup area200e, each of the conductive layers20to22has a terrace (or step-like) portion which does not overlap with the next higher conductive layer, when viewed in the XY plane or XZ plane. A contact plug26is provided on the terrace portion. In addition, the contact plug26is connected to a conductive layer27. The contact plug26and the conductive layer27contain, for example, a metal such as tungsten (W).

By the plurality of conductive layers27, the conductive layers20that function as the even-numbered select gate lines SGD0, SGD2, SGD4, and SGD6, the conductive layers21that function as the even-numbered word lines WLe, and the conductive layers22that function as the even-numbered select gate lines SGSe are electrically connected to the row decoder11.

Similarly, in the hookup area200o, the conductive layers20to22extend, for example, in a step-like manner. That is, in the hookup area200o, each of the conductive layers20to22has a terrace portion which does not overlap with that of a conductive layer higher than the corresponding conductive layer, when viewed in the XY plane or XZ plane. A contact plug28is provided on the terrace portion. The contact plug28is connected to a conductive layer29. The contact plug28and the conductive layer29contain, for example, a metal such as tungsten (W).

By the plurality of conductive layers29, the conductive layers20that function as the odd-numbered select gate lines SGD1, SGD3, SGD5, and SGD7, the conductive layers21that function as the odd-numbered word lines WLo, and the conductive layers22that function as the odd-numbered select gate lines SGSo are electrically connected to the row decoder11.

1.2.1.3 Cross-Sectional Structure of Memory Pillar MP

Next, descriptions will be made on a structure and equivalent circuits of a memory pillar MP and memory cell transistors MT.FIG.7is a cross-sectional view of a memory pillar MP which is taken along the XY plane.FIG.8is a cross-sectional view of a memory pillar MP which is taken along the YZ plane. In particular, each ofFIGS.7and8represents an area in which two memory cell transistors MT are provided.

As illustrated inFIGS.7and8, the memory pillar MP includes an insulating layer30, a semiconductor layer31, and insulating layers32to34. The word lines WLe and WLo include the conductive layer21.

Each of the insulating layer30, the semiconductor layer31, and the insulating layers32to34extends along the Z direction. The insulating layer30is, for example, a silicon oxide layer. The semiconductor layer31surrounds the side surface of the insulating layer30. The semiconductor layer31functions as an area in which a channel of a memory cell transistor MT is formed. The semiconductor layer31is, for example, a polycrystalline silicon layer.

The insulating layer32surrounds the side surface of the semiconductor layer31. The insulating layer32functions as a gate insulating film of a memory cell transistor MT. The insulating layer32has a structure in which, for example, a silicon oxide layer and a silicon nitride layer are stacked. The insulating layer33surrounds the side surface of the insulating layer32. The insulating layer33functions as a charge storage layer of a memory cell transistor MT. The insulating layer33is, for example, a silicon nitride layer. The insulating layer34surrounds the side surface of the insulating layer33. The insulating layer34functions as a block insulating film of a memory cell transistor MT. The insulating layer34is, for example, a silicon oxide layer. An insulating layer such as, for example, a silicon oxide layer is embedded in the memory trench MST excluding the portion of the memory pillar MP.

According to the above-described configuration, two memory cell transistors MT are provided in one memory pillar MP along the Y direction, to be provided in the conductive layers21, respectively. Each of the select transistors ST1and ST2has the same configuration.

In addition, equivalent circuits of the memory pillar MP will be described below.FIG.9is an equivalent circuit diagram of the memory pillar MP. As illustrated, two NAND strings NSe and NSo are provided in one memory pillar MP. That is, two select transistors ST1provided in one memory pillar MP are connected to different select gate lines, for example, SGD0and SGD1. Memory cell transistors MTe0to MTe7and MTo0to MTo7are connected to different word lines WLe and WLo, respectively. Further, the select transistors ST2are also connected to different select gate lines SGSe and SGSo, respectively.

One ends of the two NAND strings NSe and NSo in the memory pillar MP are connected to the same bit line BL, and the other ends thereof are connected to the same source line SL. Furthermore, the two NAND strings NSe and NSo share a back gate (the semiconductor layer31).

1.2.2 Details of Layout and Structure of Semiconductor Storage Device

Next, details of the layout and structure of the semiconductor storage device1of the first embodiment will be described.

First, the outline of the layout of the semiconductor storage device1will be described in detail.FIG.10is a schematic view illustrating the layout of the semiconductor storage device1.

As illustrated inFIG.10, the hookup area200eis disposed at one end of the memory array area100in the X direction, and the hookup area200ois disposed at the other end of the memory array area100in the X direction. The blocks BLK0to BLK3are arranged in an order in the Y direction.

The memory array area100includes memory areas100aand a contact area100b. The memory array area100is divided into, for example, the respective memory areas100aand the contact area100b. The slit areas STH1are arranged on the dashed lines that divide the areas100aand100b.

The memory pillars MP are arranged in a staggered manner in the memory areas100a. One or more contact plugs are provided in the contact area100b.

One or more contact plugs are also provided at the boundaries of the blocks BLK, for example, between the blocks BLK0and BLK1indicated by an area101. An example in which the contact plugs are provided between the blocks BLK0and BLK1will be described later as a first example. Here, although an example in which the contact plugs are provided between the blocks BLK0and BLK1is illustrated, the contact plugs may be provided between any other blocks BLK.

Further, as described above, the contact plugs are provided in the contact area100bdisposed between the memory areas100a. An example in which the contact plugs are provided in the contact area100bwill be described later as a second example.

In the present embodiment, an example in which the contact plugs are provided between the blocks BLK and in the contact area100bis illustrated, but the contact plugs may be provided between the blocks BLK or in the contact area100b. In addition, a plurality of contact areas100bmay be provided in the memory array area100.

1.2.2.1 Details of Layout and Structure of Memory Array Area

Next, descriptions will be made on a planar layout of the memory array area100of the semiconductor storage device1according to the first embodiment.

a. First Example

FIG.11is a planar layout in which the area101illustrated inFIG.10is enlarged, and represents a boundary between the blocks BLK0and BLK1in the memory array area100(100a).FIG.11illustrates memory trenches MST, memory pillars MP, conductive layers21, slit areas STH1, insulating areas BST, and a contact plug CP2.

As illustrated inFIG.11, the blocks BLK0and BLK1are arranged in the Y direction. Each of the blocks BLK0and BLK1has a plurality of memory trenches MST, a plurality of memory pillars MP, a plurality of conductive layers21and a plurality of slit areas STH1. The insulating areas BST are provided between the blocks BLK0and BLK1. The insulating areas BST will be described in detail later.

The layout of the memory trenches MST and the memory pillars MP is the same as that described above with reference toFIG.4.

A conductive layer21is provided between adjacent memory trenches MST. The conductive layers21are connected to each other in the hookup area200eor200o, and correspond to the word lines WL.

The slit areas STH1are provided on the memory trenches MST. The slit areas STH1are alternately arranged on the memory trenches MST in the Y direction.

Each slit area STH1is an area in which an insulating material is embedded in a hole used in a replacement process for forming the conductive layer21. The slit area STH1is an insulating layer and includes, for example, a silicon oxide layer. The arrangement of the slit areas STH1will be described in detail later.

The insulating areas BST between the blocks BLK0and BLK1will be described below.

A plurality of insulating areas BST are provided between the blocks BLK0and BLK1. The insulating areas BST have a predetermined length extending in the X direction and are arranged at predetermined intervals in the X direction. The width of each insulating area BST extending in the Y direction is longer than the width of each memory trench MST extending in the Y direction. A slit area STH1is disposed between the insulating areas BST.

One or more contact plugs CP2are provided in the insulating areas BST. InFIG.11, the contact plug CP2is disposed on a line in which the slit areas STH1are arranged in the Y direction. That is, the contact plug CP2is disposed on a line that passes through the slit areas STH1along the Y direction. However, the position of the contact plug CP2may be any position in the insulating areas BST as long as the position is not blocked by the bit lines BL.

The contact plug CP2is connected between an upper layer wire above the memory array area100and a peripheral circuit provided below the memory array area100. The peripheral circuit is provided between the semiconductor substrate23and the memory array area100.

Furthermore, the bit lines BL are provided above the memory pillars MP, and the respective memory pillars MP are electrically connected to the bit lines BL.

Next, the cross-sectional structure of the area101in the memory array area100will be described.FIG.12is a cross-sectional view taken along line A1-A2inFIG.11, and illustrates the cross sections of the insulating areas BST, the contact plug CP2, and the stacked body including the conductive layers20and21, the memory pillars MP and others.

As illustrated inFIG.12, the semiconductor storage device1has a peripheral circuit area300provided on the semiconductor substrate23, and a memory array area100provided on the peripheral circuit area300. For example, a silicon semiconductor substrate is used as the semiconductor substrate23.

The structure of the peripheral circuit area300will be described in detail below.

The peripheral circuit area300includes a peripheral circuit for controlling write, read, and erase of data on a memory cell transistor MT. For example, the peripheral circuit area300is an area for the row decoder11, the driver12, the sense amplifier13, the address register14, the command register15, and the sequencer17(FIG.1) to be disposed. Specifically, the peripheral circuit area300includes an n-channel MOS transistor (hereinafter, nMOS transistor)40, a p-channel MOS transistor (hereinafter, pMOS transistor)41, conductive layers42and43, and contact plugs44and45.

The nMOS transistor40and the pMOS transistor41are provided on the semiconductor substrate23. An element isolation area (e.g., STI (shallow trench isolation))46is provided between the nMOS transistor40and the pMOS transistor41to isolate the transistors from each other. The element isolation area46includes, for example, a silicon oxide layer.

The contact plug44is provided on a source area47or a drain area48of the nMOS transistor40or the pMOS transistor41. The conductive layer42is provided on the contact plug44. The contact plug45is provided on the conductive layer42, and the conductive layer43is provided on the contact plug45. Furthermore, a contact plug CP2that extends in the Z direction is provided on the conductive layer43.

The conductive layers42and43contain, for example, tungsten (W) and function as a wire or an electrode pad. The contact plugs44and45contain, for example, tungsten (W).

An insulating layer49is provided around the nMOS transistor40, the pMOS transistor41, the conductive layers42and43, and the contact plugs44and45. The insulating layer49includes, for example, a silicon oxide layer.

The structure of the memory array area100will be described in detail below.

The memory array area100has the memory cell array10. Specifically, as illustrated inFIG.12, the memory array area100includes conductive layers20to22and50, insulating layers51, memory pillars MP, a contact plug CP2, insulating areas BST, and a slit area STH1.

The conductive layer50is provided on the insulating layer49. The conductive layer50functions as the source line SL. The conductive layer50contains, for example, polycrystalline silicon or tungsten (W).

The plurality of insulating layers51and the plurality of conductive layers22,21, and20are alternately stacked on the conductive layer50. The stacked insulating layers51and conductive layers22,21, and20will be referred to as a stacked body. The conductive layers22,21, and20extend in the X direction. The conductive layer22functions as a select gate line SGS. Each conductive layer21functions as a word line WL. The conductive layer20functions as a select gate line SGD. The conductive layers22,21, and20contain, for example, tungsten (W). Each insulating layer51includes, for example, a silicon oxide layer.

The columnar memory pillars MP that extend in the Z direction are provided on the insulating layers51and the conductive layers22,21, and20(i.e., the stacked body). The lower end of each memory pillar MP is connected to the conductive layer50(the source line SL). A contact plug52that extends in the Z direction is provided on the upper end of the memory pillar MP, and a conductive layer53is provided on the contact plug52. That is, the memory pillar MP reaches the source line SL from the lower end of the contact plug52through the select gate line SGD, the word lines WL0to WL7, the select gate line SGS, and the plurality of insulating layers51.

The memory pillar MP has a semiconductor layer31and a cell insulating layer35. The cell insulating layer35includes insulating layers32to34. Details of the memory pillar MP shall be referred to the descriptions with reference toFIGS.7and8.

The conductive layer53functions as, for example, a bit line BL. The contact plug52and the conductive layer53contain, for example, tungsten (W).

Further, as illustrated inFIG.12, in the cross section of the insulating areas BST, the contact plug CP2is provided between the insulating areas BST. The lower end of the contact plug CP2is connected to the conductive layer43of the peripheral circuit. A conductive layer54is provided on the upper end of the contact plug CP2, and a contact plug55is provided on the conductive layer54. Further, a conductive layer56is provided on the contact plug55, and a contact plug57is provided on the conductive layer56. Furthermore, a conductive layer58is provided on the contact plug57. As a result, the contact plug CP2electrically connects the conductive layer (upper layer wire)58and the conductive layer43of the peripheral circuit to each other.

The contact plug CP2has a conductive layer CP2aand an insulating layer CP2bprovided around the conductive layer CP2a. The conductive layer CP2acontains, for example, tungsten (W). The insulating layer CP2bincludes, for example, a silicon oxide layer. The conductive layer58functions as an upper layer wire or an electrode pad. The conductive layers54,56, and58and the contact plugs55and57contain, for example, tungsten (W).

Further, in the cross section of the insulating areas BST, the slit area STH1is provided between the insulating areas BST. The insulating area BST extends in a planar form along the XZ plane that passes through the X direction and the Z direction. Each insulating area BST extends from the upper layer of the conductive layer20to the conductive layer50. The length of the insulating area BST in the Y direction is longer than the length of each memory trench MST in the Y direction. The insulating area BST includes, for example, a silicon oxide layer.

The slit area STH1extends in the Z direction. The slit area STH1extends from the upper layer of the conductive layer20to the conductive layer50. The slit area STH1includes, for example, a silicon oxide layer.

An insulating layer59is provided on the conductive layer20, the insulating areas BST, and the slit area STH1. The insulating layer59covers the periphery of the conductive layers53,54,56, and58and the contact plugs52,55, and57. The insulating layer59includes, for example, a silicon oxide layer.

Next, a modification of the first example will be described with reference toFIG.13.

FIG.13illustrates a modification of the first example, and is a planar layout in which the area101is enlarged.FIG.13illustrates the boundary between the blocks BLK0and BLK1in the memory array area100(100a).

As illustrated inFIG.13, a plurality of memory pillars MP are arranged in a staggered manner on the memory trenches MST in the memory area100a. The upper ends of the memory pillars MP are connected to the bit lines BL, respectively. Insulating areas BST are provided between the blocks BLK0and BLK1in which the memory pillars MP are arranged.

Further, a plurality of dummy memory pillars MPa are arranged in a staggered manner on the memory trenches MST in another memory area100c. The upper ends of the respective dummy memory pillar MPa are not connected to bit lines BL. That is, the dummy memory pillars MPa arranged in the memory area100chave dummy memory cell transistors (hereinafter, dummy memory cells). The dummy memory cells are memory cells which are not used for a write, read or erase operation, and no bit lines BL are connected to the memory pillars MPa having the dummy memory cells.

The insulating areas BST are provided between the blocks BLK0and BLK1in which the dummy memory pillars MPa are arranged. One or more contact plugs CP2are provided in the insulating areas BST between the blocks BLK in which the dummy memory pillars MPa are arranged. The contact plugs CP2are arranged in the X direction. The contact plugs CP2electrically connect the conductive layer (upper layer wire)58and the conductive layer43of the peripheral circuit to each other. The other configurations are the same as those of the first example.

b. Second Example

FIG.14is a planar layout in which the area102illustrated inFIG.10is enlarged, and illustrates a memory area100aand a contact area100b.

As illustrated inFIG.14, in the memory area100a, a plurality of memory trenches MST extend in the X direction and are arranged at predetermined intervals in the Y direction. A plurality of memory pillars MP are arranged in a staggered manner in the X direction and the Y direction on the plurality of memory trenches MST.

A conductive layer21is provided between adjacent memory trenches MST. Slit areas STH1are provided on the memory trenches MST at the boundary between the memory area100aand the contact area100band at the boundary between the memory area100aand another memory area100a. The slit areas STH1are alternately arranged on the memory trenches MST arranged in the Y direction.

In the contact area100b, a plurality of memory trenches MST that extend in the X direction and in directions oblique to the X direction are arranged at predetermined intervals in the Y direction. Specifically, two memory trenches MST are arranged in a polygonal shape (e.g., a hexagonal shape, a quadrangular shape, or an elliptical shape) to surround a contact arrangement area36. A plurality of memory trenches MST are arranged at predetermined intervals in the Y direction around the two memory trenches MST.

FIG.14illustrates an example in which the two memory trenches MST surround the contact arrangement area36in a hexagonal shape. In this case, each memory trench MST first extends in the X direction from the slit area STH1disposed at one end of the contact area100b, extends obliquely to the X direction, extends in the X direction, extends obliquely to the X direction to be axisymmetric with the first inclination, and further extends in the X direction to reach the slit area STH1at the other end of the contact area100b.

A plurality of contact plugs CP2are arranged in the X direction in the contact arrangement area36. Here, four contact plugs CP2are represented as an example. The other configurations are the same as those of the first example.

In addition, no memory pillars MP are arranged in the contact area100b.

Next, the cross-sectional structure of the area102in the memory array area100will be described.FIG.15is a cross-sectional view taken along line A3-A4inFIG.14, and illustrates the cross sections of the memory pillars MP, the stacked body including the conductive layers20and21, the contact plugs CP2and others.

As illustrated inFIG.15, the semiconductor storage device1has a peripheral circuit area300provided on a semiconductor substrate23, and a memory array area100provided on the peripheral circuit area300. The structure of the peripheral circuit area300is the same as that of the first example.

The structure of the memory array area100will be described in detail below.

The structure of the memory area100ain the memory array area100is the same as that of the first example.

For example, four contact plugs CP2are provided in the contact arrangement area36within the contact area100b. As illustrated inFIG.15, the two central contact plugs CP2electrically connect the conductive layer (upper layer wire)58and the conductive layer43of the peripheral circuit to each other. The lower and upper ends of the contact plugs CP2are connected in the same manner as described in the first example.

The contact plugs CP2disposed outside the two central contact plugs CP2, respectively, electrically connect the conductive layer58and the conductive layer50(the source line SL) to each other. The lower ends of the respective external contact plugs CP2are connected to the conductive layer50. A conductive layer54, a contact plug55, a conductive layer56, a contact plug57, and a conductive layer58are provided in an order on the upper end of each of the external contact plugs CP2.

In the cross section of the contact arrangement area36surrounded by the memory trenches MST, a plurality of insulating layers51and a plurality of sacrificial layers (e.g., insulating layers such as silicon nitride layers)60are alternately stacked on the insulating layer49or the conductive layer50. The other structures are the same as those of the first example.

Next, the arrangement of the slit areas STH1in the memory array area100will be described with reference to FIG.16.FIG.16illustrates the arrangement of the slit areas STH1in the memory area100aand the contact area100b.

As illustrated inFIG.16, an arrangement interval (or arrangement pitch) P1of the slit areas STH1in the X direction in the memory array area100is set to a predetermined interval. In other words, an interval P1at which the plurality of slit areas STH1arranged in the Y direction at the boundary between the memory area100aand the contact area100band at the boundary between the memory area100aand another memory area100aare arranged in the X direction is a predetermined length. That is, the plurality of slit areas STH1arranged in the Y direction are arranged at the predetermined intervals P1in the X direction.

In this way, in the memory array area100where the plurality of slit areas STH1in the Y direction are arranged in the X direction at the equal intervals, when a removal of the sacrificial layers by etching is performed from the slit areas STH1in the replacement process performed using the slit areas STH1, the distance to be etched is the equal distance from the slit areas STH1.

Thus, the time for which a block insulating film and others of a memory pillar are exposed to an etching solution after the removal of the sacrificial layers by etching may be shortened, so that a damage to the block insulating layer may be reduced.

Next, descriptions will be made on a control of the replacement process for leaving the insulating layers51and the sacrificial layers60in the contact arrangement area36within the memory array area100, with reference toFIG.17.FIG.17is a view illustrating the control of the replacement process using the slit areas STH1in the memory array area100.

The planar layout illustrated inFIG.17is similar to the layout described inFIG.14. As described above, the contact arrangement area36in which the contact plugs CP2are arranged is surrounded by the memory trenches MST. That is, the memory trenches MST are arranged without a gap around the contact arrangement area36.

In this layout, when the sacrificial layers60are removed through the slit areas SHT1in the replacement process, the etching solution is prevented from intruding into the contact arrangement area36as indicated by arrows61inFIG.17. Therefore, the sacrificial layers60within the contact arrangement area36are not removed, and are not replaced with the conductive layers21. As a result, the insulating layers (e.g., silicon oxide layers)51and the sacrificial layers (e.g., silicon nitride layers)60are maintained in the stacked state within the contact arrangement area36.

1.3 Effects of First Embodiment

According to the first embodiment, it is possible to provide a semiconductor storage device of which the operation reliability may be improved.

For example, in a semiconductor storage device having a configuration in which a peripheral circuit is provided below a memory cell array where memory cells are arranged in an array form, that is, a configuration in which a peripheral circuit is provided between a memory cell array and a semiconductor substrate, contact plugs for the connection to transistors and others of the peripheral circuit are arranged in the memory cell array. However, it may be difficult to provide an area for arranging the contact plugs for the connection to the peripheral circuit in the memory cell array area.

In the first example and its modification, the contact plug CP2is provided in the insulating area between the blocks BLK. As a result, the upper layer wire on the memory array area100and the peripheral circuit below the memory array area100are electrically interconnected by the contact plug CP2. As a result, it is possible to improve the operation reliability of the semiconductor storage device in which the peripheral circuit is provided below the memory cell array.

In the second example, in the X direction, the contact arrangement area36in which the contact plugs CP2are arranged is provided in the memory array area100in which memory cells are arranged. As a result, the upper layer wire above the memory array100and the peripheral circuit below the memory array100are electrically interconnected by the contact plugs CP2. As a result, it is possible to improve the operation reliability of the semiconductor storage device in which the peripheral circuit is provided below the memory cell array.

In the second example, the length of the contact area100bin the X direction is the same as the length of the memory area100ain the X direction. As a result, the arrangement interval P1of the slit areas STH1in the X direction is set to be constant in the memory array area100.

In the replacement process performed using the slit areas STH1, the removal of the sacrificial layers (e.g., silicon nitride layers)60by etching is performed at an equal distance from the slit areas STH1. Therefore, in the memory array area100in which the slit areas STH1are arranged at the equal intervals P1, the sacrificial layers60are removed by etching in substantially the same time. As a result, the time for which a block insulating layer and others of a memory pillar MP are exposed to the etching solution after the removal of the sacrificial layers60by etching may be shortened, so that a damage to the block insulating layer and others may be reduced.

In the second example, the memory trenches MST are arranged without a gap around the contact arrangement area36. In this layout, in the replacement process, the etching solution for removing the sacrificial layers60does not intrude into the contact arrangement area36through the slit areas SHT1. Therefore, the sacrificial layers60within the contact arrangement area36are not removed, and are not replaced with the conductive layers21. As a result, the insulating layers (e.g., silicon oxide layers)51and the sacrificial layers60are maintained in the stacked state within the contact arrangement area36. As a result, the contact arrangement area36and other areas where contact plugs are to be provided have a cross-sectional structure in which the contact plugs CP2may be provided using the same process.

2. Second Embodiment

Next, a semiconductor storage device according to a second embodiment will be described. The second embodiment is an example in which two conductive layers (word lines) are integrated into one conductive layer in a contact area100bin a memory area100ain order to form a contact arrangement area. The second embodiment will be described focusing on differences from the first embodiment. The other configurations which are not described are the same as those of the first embodiment.

As described above with reference toFIG.4, the block BLK in the semiconductor storage device1includes select gate lines SGD0to SGD7. Each of the select gate lines SGD0to SGD7corresponds to two conductive layers21corresponding to the word lines WL.

In the second embodiment, a planar layout of the conductive layers21, as word lines, that correspond to the select gate lines SGD0to SGD7, memory trenches MST, and memory pillars MP will be described. Hereinafter, the conductive layers21(word lines WL) that correspond to the select gate lines SGD0to SGD7will be denoted by21(SGD0),21(SGD1),21(SGD2),21(SGD3),21(SGD4),21(SGD5),21(SGD6), and21(SGD7), respectively.

2.1 Details of Layout of Memory Array Area

a. First Example

FIG.18is a planar layout of conductive layers21, memory trenches MST, and memory pillars MP of a first example.

As illustrated inFIG.18, for example, the conductive layers21(SGD2),21(SGD3),21(SGD4), and21(SGD5), as word lines, that correspond to the select gate lines SGD2to SGD5are arranged.

The conductive layer21(SGD2) has a first portion21a, a plurality of second portions21b, and a plurality of third portions21c.

The first portion21aextends in the X direction from one end of the memory array area100to the other end thereof. The second portions21beach have a predetermined length extending in the X direction, and are arranged in the X direction at a predetermined interval. The third portions21cextend in the Y direction and are arranged in the X direction at a predetermined interval. The third portions21ceach connects the respective first portion21aand the second portions21bto each other. In other words, the second portions21bare connected to one end of the first portion21a, and are connected to the first portion21aby the third portions21cat a predetermined interval from the one end of the first portion21a.

The conductive layer21(SGD3) has the same configuration as that of the conductive layer21(SGD2), except for the contact arrangement area, and has a point-symmetrical layout with respect to the central points of the conductive layers21(SGD2) and21(SGD3).

The conductive layers21(SGD2) and21(SGD3) are arranged so as to combine with each other in the second portion21b. Memory pillars MP are arranged at positions where the first portion21aand the second portion21bof the conductive layer21(SGD2) face with each other in the Y direction and the first portion21aand the second portion21bof the conductive layer21(SGD3) face with each other in the Y direction.

Furthermore, a third portion21cof the conductive layer21(SGD3) is expanded in the X direction by a predetermined distance, so as to provide an area where the conductive layer21does not exist. The contact arrangement area36is provided in the area where the conductive layer21does not exist. One or more contact plugs CP2are arranged in the contact arrangement area36. Here, the third portion21cof the conductive layer21(SGD3) is expanded to provide the contact arrangement area36in which the conductive layer does not exist. However, a third portion21cof the conductive layer21(SGD2) may be expanded to provide the contact arrangement area36in which the conductive layer21does not exist.

The layout of the conductive layers21(SGD4) and21(SGD5) is the same as the layout of the conductive layers21(SGD2) and21(SGD3). Furthermore, the layout of the conductive layers21(SGD0) and21(SGD1) and the layout of the conductive layers21(SGD6) and21(SGD7) are also the same as the layout of the conductive layers21(SGD2) and21(SGD3).

FIG.19is a planar layout of conductive layers21, memory trenches MST, and memory pillars MP of a second example. In this case as well, the planar layout will be described using the conductive layers21(SGD2) to21(SGD5).

The conductive layer21(SGD2) has a plurality of first portions21d, a plurality of second portions21e, and a plurality of third portions21f.

The first portions21deach have a predetermined length extending in the X direction and are arranged at a predetermined interval in the X direction. The second portions21eeach have a predetermined length extending in the X direction and are arranged at a predetermined interval in the X direction. The third portions21feach have a predetermined length extending in the Y direction and are arranged at a predetermined interval in the X direction. When the planar layout illustrated inFIG.19is viewed from above, the left end of each first portion21dis described as one end, and the right end thereof is described as the other end. The upper end of each third portion21fis described as one end, and the lower end thereof is described as the other end.

Two third portions21fform a pair, and one end of each of the pair of third portions21fis connected to the other end of the first portion21dand one end of another adjacent first portion21d. The other end of each of the pair of third portions21fis connected to the central portion of the second portion21e. Then, a plurality of pairs of third portions21fare arranged at predetermined intervals in the X direction, and each pair of third portions21fconnects two first portions21dand one second portion21eto each other.

The conductive layer21(SGD3) has the same configuration as that of the conductive layer21(SGD2) and has a point-symmetrical layout with respect to the central points of the conductive layers21(SGD2) and21(SGD3).

The conductive layers21(SGD2) and21(SGD3) are arranged so as to combine with each other in the first portion21dand the second portion21e. Memory pillars MP are arranged at positions where the first portion21dand the second portion21eof the conductive layer21(SGD2) face with each other in the Y direction and the first portion21dand the second portion21eof the conductive layer21(SGD3) face with each other in the Y direction.

The layout of the conductive layers21(SGD4) and21(SGD5) is the same as the layout of the conductive layers21(SGD2) and21(SGD3). The conductive layers21(SGD4) and21(SGD5) have a layout in which the conductive layers21(SGD2) and21(SGD3) are arranged to be axisymmetric with each other with respect to a straight line parallel to the X direction.

Furthermore, an area where the conductive layer21does not exist is provided between the pair of third portions21fof the conductive layer21(SGD3) and between the pair of third portions21fof the conductive layer21(SGD4). The contact arrangement area36is disposed in the area where the conductive layer21does not exist. One or more contact plugs CP2are arranged in the contact arrangement area36. Details of the contact arrangement area36will be described later.

FIG.20is a planar layout of the conductive layers21(SGD0) to21(SGD7) including the contact arrangement area36illustrated inFIG.19.

At the one end side of the contact area100b, the second portion21eand the first portion21dof the conductive layer21(SGD3) extend in the X direction, and the first portion21dbends in the Y direction to form the third portion21f. The third portion21fextends in the Y direction and is connected to the second portion21e. The second portion21econnected to the third portion21ffurther extends in the X direction. At the other end side of the contact area100b, the second portion21eextends in the X direction and branches in the Y direction to form the third portion21f. Furthermore, the third portion21fextends in the Y direction and is connected to the first portion21d. That is, the second portion21eand the first portion21dof the conductive layer21(SGD3) are integrated into one second portion21enear the one end of the contact area100b, and branches into the second portion21eand the first portion21dnear the other end of the contact area100b.

At the other end side of the contact area100b, the second portion21eand the first portion21dof the conductive layer21(SGD4) extend in the X direction, and the first portion21dbends in the Y direction to form the third portion21f. The third portion21fextends in the Y direction and is connected to the second portion21e. The second portion21econnected to the third portion21ffurther extends in the X direction. At the one end side of the contact area100b, the second portion21eextends in the X direction and branches in the Y direction to form the third portion21f. Furthermore, the third portion21fextends in the Y direction and is connected to the first portion21d. That is, the second portions21eand the first portion21dof the conductive layer21(SGD4) are integrated into one second portion21enear the other end of the contact area100b, and branch into the second portion21eand the first portion21dnear the one end of the contact area100b.

The plurality of other conductive layers21extend in the X direction and are arranged at predetermined intervals in the Y direction. Memory trenches MST are arranged between the conductive layers21.

A contact arrangement area (also referred to as a first area)36surrounded by the memory trenches MST is arranged between the conductive layers21(SGD3) and21(SGD4) and between the first portions21dof the one end and the other end of the contact area100b. One or more contact plugs CP2are arranged in the contact arrangement area36.

In addition, one or more dummy memory trenches MSTa may be arranged in the contact arrangement area36. The dummy memory trench MSTa extends along the X direction and the Z direction (or the XZ plane) and reaches the conductive layer50from the upper layer of the conductive layer20. The dummy memory trench MSTa is an insulating area (or insulating layer), and includes, for example, a silicon oxide layer. Memory pillars MP are not arranged in the dummy memory trench MSTa.

The slit areas STH1are arranged in the Y direction at the one end and the other end in the contact area100b. Furthermore, the slit areas STH1are arranged in the Y direction at a substantially central portion between the one end and the other end in the contact area100b. The width of each slit area STH1extending in the Y direction is longer than the width of the memory trench MST extending in the Y direction.

In addition, a memory area100a(also referred to as a second area) is provided apart from the contact arrangement area36in the X direction. Memory pillars MP that penetrate the memory trenches MST in the Z direction are provided in the memory area100a.

As illustrated inFIG.20, the contact area100bmay be provided in an area which is twice the arrangement interval P1of the slit areas STH1in the X direction, or may be provided in an area of the arrangement interval P1of the slit areas STH1.

c. Third Example

FIG.21is a planar layout of conductive layers21, memory trenches MST, and memory pillars MP of a third example. In this case as well, the planar layout is described using the conductive layers21(SGD2) to21(SGD5).

The conductive layer21(SGD2) has a first portion21h, a plurality of second portions21i, and a plurality of third portions21j.

The first portion21hextends in the X direction from one end of the memory array area100to the other end thereof. The second portions21ieach have a predetermined length extending in the X direction, and are arranged at a predetermined interval in the X direction. The third portions21jeach have a predetermined length extending in the Y direction, and are arranged at a predetermined interval in the X direction. When the planar layout illustrated inFIG.21is viewed from above, the left end of each second portion21iis described as one end, and the right end thereof is described as the other end. The upper end of each third portion21jis described as one end, and the lower end thereof is described as the other end.

One end of each of the third portions21jis connected to the first portion21h, and the other end of each of the third portions21jis connected to one end of the second portion21i. In other words, the one end of the second portion21iis connected to the other end of the third portion21j, and the one end of the third portion21jis connected at a predetermined interval to the first portion21hthat extends in the X direction.

The conductive layer21(SGD3) has a plurality of first portions21k, a plurality of second portions21m, and a plurality of third portions21n. The first portions21keach have a predetermined length extending in the X direction, and are arranged at a predetermined interval in the X direction. The second portions21meach have a predetermined length extending in the X direction, and are arranged at a predetermined interval in the X direction. The third portions21neach have a predetermined length extending in the Y direction, and are arranged at a predetermined interval in the X direction. When the planar layout illustrated inFIG.21is viewed from above, the left end of each first portion21kis described as one end, and the right end thereof is described as the other end. The left end of each second portion21mis described as one end, and the right end thereof is described as the other end. The upper end of each third portion21nis described as one end, and the lower end thereof is described as the other end.

Two third portions21nform a pair, and one end of each of the pair of third portions21nis connected to the other end of the second portion21m. The other end of each of the pair of third portions21nis connected to the other end of the first portion21kand one end of another adjacent first portion21k. Then, a plurality of pairs of third portions21nare arranged at predetermined intervals in the X direction, and each pair of third portions21nconnects two first portions21kand one second portion21mto each other.

The conductive layers21(SGD2) and21(SGD3) are arranged so as to combine with each other in the first portion21hand the second portion21i, and the first portion21kand the second portion21m. Memory pillars MP are arranged at positions where the first portion21hand the second portion21iof the conductive layer21(SGD2) face with each other in the Y direction and the first portion21kand the second portion21mof the conductive layer21(SGD3) face with each other in the Y direction.

The layout of the conductive layer21(SGD4) is the same as the layout of the conductive layer21(SGD3). The layout of the conductive layer21(SGD5) is the same as the layout of the conductive layer21(SGD2). The conductive layers21(SGD4) and21(SGD5) have a layout in which the conductive layers21(SGD2) and21(SGD3) are arranged to be axisymmetric with each other with respect to a straight line parallel to the X direction.

Furthermore, an area where the conductive layer21does not exist is provided between the pair of third portions21nof the conductive layer21(SGD3) and between the pair of third portions21nof the conductive layer21(SGD4). The contact arrangement area36is disposed in the area where the conductive layer21does not exist. One or more contact plugs CP2are arranged in the contact arrangement area36. Details of the contact arrangement area36will be described later.

FIG.22is a planar layout of the conductive layers21(SGD0) to21(SGD7) including the contact arrangement area36illustrated inFIG.21.

At the one end side of the contact area100b, the second portion21mof the conductive layer21(SGD3) extends in the X direction to become an end near the one end of the contact area100b. The first portion21kextends in the X direction, and bends in the Y direction to form the third portion21n. The third portion21nextends in the Y direction and is connected to the second portion21m. The second portion21mconnected to the third portion21nfurther extends in the X direction. At the other end side of the contact area100b, the second portion21mextends in the X direction and branches in the Y direction to form the third portion21n. Furthermore, the third portion21nextends in the Y direction and is connected to the first portion21k. Furthermore, the first portion21kextends in the X direction. That is, the second portion21mand the first portion21kof the conductive layer21(SGD3) become one second portion21mnear the one end of the contact area100b, and branch into the second portion21mand the first portion21knear the other end of the contact area100b.

At the other end side of the contact area100b, the second portion21mand the first portion21kof the conductive layer21(SGD4) extend in the X direction, and the first portion21kbends in the Y direction to form the third portion21n. The third portion21nextends in the Y direction and is connected to the second portion21m. The second portion21mconnected to the third portion21nfurther extends in the X direction. At the one end side of the contact area100b, the second portion21mbends in the Y direction to form the third portion21n. The third portion21nextends in the Y direction and further bends in the X direction to form the first portion21k. Furthermore, the first portion21kextends in the X direction. That is, the second portions21mand the first portion21kof the conductive layer21(SGD4) are integrated into one second portion21mnear the other end of the contact area100band is maintained as one second portion21mto the portion near to the one end of the contact area100b.

The plurality of other conductive layers21extend in the X direction and are arranged at predetermined intervals in the Y direction. Memory trenches MST are arranged among the conductive layers21.

A contact arrangement area36surrounded by the memory trenches MST is disposed between the conductive layers21(SGD3) and21(SGD4) and between the first portions21kof the one end and the other end of the contact area100b. One or more contact plugs CP2are arranged in the contact arrangement area36.

One or more dummy memory trenches MSTa may be arranged in the contact arrangement area36.

In addition, the memory area100ais provided apart from the contact arrangement area36in the X direction. Memory pillars MP that penetrate the memory trenches MST in the Z direction are provided in the memory area100a.

d. Fourth Example

FIG.23is a planar layout of conductive layers21, memory trenches MST, and memory pillars MP of a fourth example. In this case as well, the planar layout is described using the conductive layers21(SGD2) to21(SGD5).

The layout of the conductive layer21(SGD2) is the same as the layout of the conductive layer21(SGD2) of the third example, and the layout of the conductive layer21(SGD3) is the same as the layout of the conductive layer21(SGD3) of the third example.

The layout of the conductive layer21(SGD4) is the same as the layout of the conductive layer21(SGD2) of the third example except that, in the layout of the conductive layer21(SGD2) of the third example, the third portion21jis divided into two (one pair of) third portions21jand the space between the two third portions21jis expanded. The layout of the conductive layer21(SGD5) is the same as the conductive layer21(SGD3) of the third example except that, in the layout of the conductive layer21(SGD3) of the third example, there is no area between the two (one pair of) third portions21nand the two third portions21nbecome one third portion21n.

The conductive layers21(SGD4) and21(SGD5) are arranged such that the third portions21jof the conductive layers21(SGD4) and21(SGD5) coincide with one pair of third portions21nof the conductive layers21(SGD2) and21(SGD3) in the Y direction.

Further, an area where the conductive layer21does not exist is provided between the pair of third portions21nof the conductive layer21(SGD3) and between the pair of third portions21jof the conductive layer21(SGD4). The contact arrangement area36is disposed in the area where the conductive layer21does not exist. One or more contact plugs CP2are arranged in the contact arrangement area36. Details of the contact arrangement area36will be described later.

FIG.24is a planar layout of the conductive layers21(SGD0) to21(SGD7) including the contact arrangement area36illustrated inFIG.23.

At the one end side of the contact area100b, the second portion21mof the conductive layer21(SGD3) extends in the X direction to become an end near the one end of the contact area100b. The first portion21kextends in the X direction, and bends in the Y direction to form the third portion21n. The third portion21nextends in the Y direction and is connected to the second portion21m. The second portion21mconnected to the third portion21nfurther extends in the X direction. At the other end side of the contact area100b, the second portion21mextends in the X direction and branches in the Y direction to form the third portion21n. Furthermore, the third portion21nextends in the Y direction and is connected to the first portion21k. That is, the second portion21mof the conductive layer21(SGD3) becomes an end near the one end of the contact area100b, and the first portion21kof the conductive layer21(SGD3) becomes the second portion21mnear the one end of the contact area100band branches into the second portion21mand the first portion21knear the other end of the contact area100b.

At the other end side of the contact area100b, the second portion21iof the conductive layer21(SGD4) extends in the X direction to become an end near the other end of the contact area100b. The first portion21hextends in the X direction, and bends in the Y direction to form the third portion21j. The third portion21jextends in the Y direction and is connected to the second portion21i. The second portion21iconnected to the third portion21jfurther extends in the X direction. At the one end side of the contact area100b, the second portion21iextends in the X direction and branches in the Y direction to form the third portion21j. Furthermore, the third portion21jextends in the Y direction and is connected to the first portion21h. That is, the second portion21jof the conductive layer21(SGD4) becomes an end near the other end of the contact area100b, and the first portion21hof the conductive layer21(SGD4) becomes the second portion21inear the other end of the contact area100band branches into the second portion21iand the first portion21hnear the one end of the contact area100b.

The plurality of other conductive layers21extend in the X direction and are arranged at predetermined intervals in the Y direction. Memory trenches MST are arranged between the conductive layers21.

A contact arrangement area36surrounded by the memory trenches MST is disposed between the conductive layers21(SGD3) and21(SGD4) and between the first portions21k(or first portions21h) of the one end and the other end of the contact area100b. One or more contact plugs CP2are arranged in the contact arrangement area36.

One or more dummy memory trenches MSTa may be arranged in the contact arrangement area36.

In addition, the memory area100ais provided apart from the contact arrangement area36in the X direction. Memory pillars MP that penetrate the memory trenches MST in the Z direction are provided in the memory area100a.

e. Fifth Example

For example, in the third example illustrated inFIG.21, the conductive layer21(SGD2) has a first portion21h, a second portion21i, and a third portion21j. The first portion21his a conductive layer that extends in the X direction in the memory array100, and the second portion21iand the third portion21jare conductive layers that are connected to the first portion21hat a predetermined interval and branch from the first portion21h. Therefore, the first portion21hmay be regarded as a trunk wire, and the second portion21iand the third portion21jmay be regarded as branch wires. In the fifth example, the wire width of the first portion21has the trunk wire is widened.

FIG.25is a planar layout of conductive layers21and memory trenches MST of the fifth example. As illustrated, the wire width of the first portion21has the trunk wire is made wider (or longer) than the wire width of the second portion21i. That is, the length of the first portion21hin the Y direction is made longer than the length of the second portion21iin the Y direction.

In order to widen the wire width of the first portion21h, the wire width of the second portion21imay be narrowed. Since the second portion21icorresponds to a branch wire, no problem occurs even when the wire width is narrowed somewhat.

2.2 Effects of Second Embodiment

According to the second embodiment, it is possible to provide a semiconductor storage device of which the operation reliability may be improved.

In the first example, the third portion21cof the conductive layer21(SGD3) is expanded in the X direction, such that the contact arrangement area36in which the conductive layer21does not exist is provided between the first portion21aof the conductive layer21(SGD3) and the first portion21aof the conductive layer21(SGD2).

In the layout of the first example, since there is no narrow portion between the memory trenches MST (or between the conductive layers21), it is possible to prevent the deterioration of the operation reliability or the defect occurrence in the manufacture of a semiconductor storage device which may be caused from narrow conductive layers21. Further, in the X direction of the memory array area100, the contact arrangement area36may be provided in any of the plurality of third portions21c. As a result, the third portion21cin which the contact arrangement area36is to be provided may be freely selected, thereby improving the degree of freedom in design.

In the second example, the space between the pair of third portions21fof the conductive layer21(SGD3) and the conductive layer21(SGD4) is expanded in the X direction, and the contact arrangement area36in which the conductive layer21does not exist is provided between the second portion21eof the conductive layer21(SGD3) and the second portion21eof the conductive layer21(SGD4). Furthermore, in the contact area100b, the contact arrangement area36is disposed in an area provided by integrating two conductive layers into one conductive layer. As a result, the number of conductive layers may be reduced, so that a narrow portion of the distance between memory trenches MST (or between conductive layers21) may be eliminated. Thus, it is possible to prevent the deterioration of the operation reliability or the defect occurrence in the manufacture of a semiconductor storage device which may be caused from narrow conductive layers21.

In the third example, the space between the pair of third portions21nof the conductive layer21(SGD3) and the conductive layer21(SGD4) is expanded in the X direction, and the contact arrangement area36in which the conductive layer21does not exist is provided between the second portion21mof the conductive layer21(SGD3) and the second portion21mof the conductive layer21(SGD4). Furthermore, in the contact area100b, the contact arrangement area36is disposed in an area provided by integrating two conductive layers into one conductive layer. As a result, the number of conductive layers may be reduced, so that a narrow portion of the distance between memory trenches MST (or between conductive layers21) may be eliminated. Further, the second portion21i(or21m) and the third portion21j(or21n) branch from the first portion21h(or21k) in the direction in which a current flows in the conductive layer21. Therefore, a delay due to the wire resistance and the wire capacitance of the conductive layer21as the word line WL may be reduced. Thus, it is possible to prevent the deterioration of the operation reliability or the defect occurrence in the manufacture of a semiconductor storage device which may be caused from narrow conductive layers21.

In the fourth example, the space between the pair of third portions21nof the conductive layer21(SGD3) and the space between the pair of third portions21jof the conductive layer21(SGD4) are expanded in the X direction, and the contact arrangement area36in which the conductive layer21does not exist is provided between the second portion21mof the conductive layer21(SGD3) and the second portion21iof the conductive layer21(SGD4). Furthermore, in the contact area100b, the contact arrangement area36is disposed in an area provided by integrating two conductive layers into one conductive layer. As a result, the number of conductive layers may be reduced, so that a narrow portion of the distance between memory trenches MST (or between conductive layers21) may be eliminated. Further, the second portion21i(or21m) and the third portion21j(or21n) branch from the first portion21h(or21k) in the direction in which a current flows in the conductive layer21. Therefore, a delay due to the wire resistance and the wire capacitance of the conductive layer21as the word line WL may be reduced. Thus, it is possible to prevent the deterioration of the operation reliability or the defect occurrence in the manufacture of a semiconductor storage device which may be caused from narrow conductive layers21.

In the fifth example, among the first portion21h, the second portion21i, and the third portion21jof the conductive layer21, the wire width of the first portion21hcorresponding to a trunk wire (or main wire) is set to be wider than the wire width of the second portion21icorresponding to a branch wire. As a result, the wire resistance and signal delay of the conductive layer21as the word line WL may be reduced.

The other effects are the same as those of the first embodiment described above.

3. Other Modifications

In the above-described embodiments, a NAND type flash memory has been described as an example of the semiconductor storage device. However, the present disclosure is not limited to the NAND flash memory, but may be applied to other general semiconductor memories and may be further applied to various memory devices other than the semiconductor storage device.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.