Patent ID: 12262134

MODE FOR CARRYING OUT THE INVENTION

Modes for carrying out the present technology (hereinafter referred to as embodiments) are hereinafter described. The description will be given in the following order.1. First Embodiment (Example in Which Levels Are Held in Three capacitors)2. Second Embodiment (Example in Which Levels Are held in Three Capacitors and Reading of Reference Voltage Is Omitted)3. Third Embodiment (Example in Which Sample-and-Hold Circuit That Holds Levels in Three Capacitors Is Shared by Four Pixels)4. Example of Application to Mobile Body

1. First Embodiment

[Configuration Example of Imaging Device]

FIG.1is a block diagram illustrating a configuration example of an imaging device100in a first embodiment of the present technology. The imaging device100is a device for capturing image data (frame), and includes an optical unit110, a solid-state imaging element200, and a digital signal processing (DSP) circuit120. The imaging device100further includes a display unit130, an operation unit140, a bus150, a frame memory160, a storage unit170, and a power supply unit180. As the imaging device100, for example, in addition to a digital camera such as a digital still camera, a smartphone and a personal computer having an imaging function, an in-vehicle camera, and the like are assumed.

The optical unit110condenses light from a subject and guides the light to the solid-state imaging element200. The solid-state imaging element200generates a frame by photoelectric conversion in synchronization with a vertical synchronization signal. Here, the vertical synchronization signal is a periodic signal of a predetermined frequency indicating imaging timing. The solid-state imaging element200supplies the generated image data to the DSP circuit120via a signal line209.

The DSP circuit120executes predetermined signal processing on the frame from the solid-state imaging element200. The DSP circuit120outputs the processed frame to the frame memory160and the like via the bus150.

The display unit130displays frames. As the display unit130, for example, a liquid crystal panel or an organic electro luminescence (EL) panel is assumed. The operation unit140generates an operation signal according to a user's operation.

The bus150is a common path through which the optical unit110, the solid-state imaging element200, the DSP circuit120, the display unit130, the operation unit140, the frame memory160, the storage unit170, and the power supply unit180exchange data with each other.

The frame memory160holds image data. The storage unit170stores various data such as frames. The power supply unit180supplies power to the solid-state imaging element200, the DSP circuit120, the display unit130and the like.

[Configuration Example of Solid-State Imaging Element]

FIG.2is a view illustrating an example of a stacked structure of the solid-state imaging element200in the first embodiment of the present technology. The solid-state imaging element200includes a circuit chip202and a light reception chip201stacked on the circuit chip202. These chips are connected by Cu—Cu bonding, vias, or bumps.

FIG.3is a block diagram illustrating a configuration example of the solid-state imaging element200in the first embodiment of the present technology. The solid-state imaging element200includes a vertical scanning circuit211, a timing control circuit212, a digital to analog converter (DAC)213, a pixel array unit214, a column signal processing circuit220, and a horizontal transfer scanning circuit215.

In the pixel array unit214, a plurality of pixels is arranged in a two-dimensional grid pattern. Furthermore, two adjacent pixels (for example, two pixels arranged in the vertical direction) in the pixel array unit214share one sample-and-hold circuit. The sample-and-hold circuit is omitted in the drawing. A circuit including the sample-and-hold circuit and two pixels (such as the pixel310and the pixel320) sharing the circuit is referred to as an SH shared block300.

The pixel (such as the pixel310) photoelectrically converts incident light to generate an analog pixel signal.

The vertical scanning circuit211drives a pixel and outputs a pixel signal to the column signal processing circuit220. The timing control circuit212controls operation timings of the vertical scanning circuit211, the DAC213, the column signal processing circuit220, and the horizontal transfer scanning circuit215in synchronization with the vertical synchronization signal.

The DAC213generates a predetermined reference signal and supplies the generated reference signal to the column signal processing circuit220. For example, a sawtooth-shaped ramp signal is used as the reference signal.

The column signal processing circuit220includes an ADC for each column of the SH shared block300, and performs analog to digital (AD) conversion on an analog signal of each column. The column signal processing circuit220sequentially outputs the AD-converted digital signals to the DSP circuit120under the control of the horizontal transfer scanning circuit215. For each row of the SH shared block300, AD conversion is executed for each column in the row. One piece of image data is generated by executing the AD conversion on all the rows.

The horizontal transfer scanning circuit215controls the column signal processing circuit220to sequentially output the digital signals to the DSP circuit120.

[Configuration Example of SH Shared Block]

FIG.4is a circuit diagram illustrating a configuration example of the SH shared block300in the first embodiment of the present technology. The SH shared block300includes pixels310and320, a connection transistor351, a load metal-oxide-semiconductor (MOS) transistor352, and a sample-and-hold circuit400. Furthermore, in the pixel array unit214, a vertical signal line309is wired for each column of the SH shared block300. As the connection transistor351and the load MOS transistor352, for example, n-channel MOS (nMOS) transistors are used.

The pixels310and320are disposed, for example, on the light reception chip201, and a circuit (such as the sample-and-hold circuit400) at a subsequent stage thereof is disposed on the circuit chip202. Note that the pixel310is an example of a first pixel described in the claims, and the pixel320is an example of a second pixel described in the claims.

The pixel310includes a charge discharge transistor311, a photoelectric conversion element312, a transfer transistor313, a reset transistor314, an amplification transistor315, and a selection transistor316. The pixel320includes a charge discharge transistor321, a photoelectric conversion element322, a transfer transistor323, a reset transistor324, an amplification transistor325, and a selection transistor326. As transistors in these pixels, for example, nMOS transistors are used.

The charge discharge transistor311discharges the charge having overflowed from the photoelectric conversion element312to the power supply voltage according to a discharge control signal OFG from the vertical scanning circuit211. The charge discharge transistor321discharges the charge having overflowed from the photoelectric conversion element322to the power supply voltage according to the discharge control signal OFG.

The photoelectric conversion element312converts incident light to the pixel310into a charge. The photoelectric conversion element322converts incident light to the pixel320into a charge.

The transfer transistor313transfers charge from the photoelectric conversion element312to a floating diffusion layer (not illustrated) according to a transfer signal TRG from the vertical scanning circuit211. The transfer transistor323transfers charges from the photoelectric conversion element322to a floating diffusion layer (not illustrated) according to the control signal TRG.

The reset transistor314initializes the floating diffusion layer according to a reset signal RST1from the vertical scanning circuit211. The reset transistor324initializes the floating diffusion layer according to a reset signal RST2from the vertical scanning circuit211.

The amplification transistor315amplifies the voltage of the floating diffusion layer. The amplification transistor325amplifies a voltage of the floating diffusion layer.

The selection transistor316outputs a signal of the amplified voltage to an input node350as a pixel signal SIG according to a selection signal SEL1from the vertical scanning circuit211. The selection transistor326outputs a signal of the amplified voltage to the input node350as the pixel signal SIG according to a selection signal SEL2from the vertical scanning circuit211.

A predetermined bias voltage VB is applied to the gate of the load MOS transistor352. The load MOS transistor352supplies a load current corresponding to the bias voltage.

The connection transistor351opens and closes a path between the load MOS transistor352and the input node350according to a control signal PC from the vertical scanning circuit211.

The sample-and-hold circuit400includes short-circuit transistors411,421, and461, connection transistors412,422, and462, a common capacitor450, individual capacitors451and452, an amplification transistor463, and a selection transistor464. As transistors in the sample-and-hold circuit400, for example, nMOS transistors are used.

For example, MIM elements are used as the common capacitor450, the individual capacitor451, and the individual capacitor452. The capacitance values of these capacitors are assumed to be the same. Also, one end (right side in the drawing) of each of these three capacitors is connected to an output-side node405. The voltage of the output-side node405is defined as VG. Also, the other end of the common capacitor450is connected to the input node350.

The short-circuit transistor411opens and closes a path between the other end (left side in the drawing) of the individual capacitor451and the input node350according to a control signal Sla from the vertical scanning circuit211. The short-circuit transistor421opens and closes a path between the other end (left side in the drawing) of the individual capacitor452and the input node350according to a control signal S2afrom the vertical scanning circuit211.

The connection transistor412opens and closes a path between a node of a reference voltage VREF and the other end of the individual capacitor451according to a control signal S1bfrom the vertical scanning circuit211. The connection transistor422opens and closes a path between a node of a reference voltage VREF and the other end of the individual capacitor452according to a control signal S2bfrom the vertical scanning circuit211.

The short-circuit transistor461opens and closes a path between one end and the other end of the common capacitor450according to a control signal S0from the vertical scanning circuit211. The connection transistor462opens and closes a path between a node of a reference voltage VREF and the output-side node405according to a control signal RB from the vertical scanning circuit211.

The amplification transistor463amplifies a voltage VG of the output-side node405. The selection transistor464outputs a signal of the voltage amplified by the amplification transistor463to the vertical signal line309according to a control signal SEL0from the vertical scanning circuit211. The signal of the vertical signal line309is supplied to the column signal processing circuit220as an analog output signal Aout.

Details of the control timing of each of the above-described transistors will be described later. Note that the power supply voltage of the pixels310and320and the power supply voltage of the sample-and-hold circuit400may be the same or different. Furthermore, a control signal to the sample-and-hold circuit400can be supplied from the timing control circuit212instead of the vertical scanning circuit211.

FIG.5is a diagram illustrating an arrangement example of MIM elements in the first embodiment of the present technology. As described above, in the SH shared block300, for example, three MIM elements are disposed as the common capacitor450, the individual capacitor451, and the individual capacitor452. With the circuit chip202as a lower chip, the individual capacitor451is disposed immediately below the corresponding pixel310, and the individual capacitor452is disposed immediately below the corresponding pixel320. Further, the common capacitor450is disposed between the individual capacitors451and452.

[Configuration Example of Column Signal Processing Circuit]

FIG.6is a block diagram illustrating a configuration example of the column signal processing circuit220in the first embodiment of the present technology. In the column signal processing circuit220, an ADC221and a latch circuit224are disposed for each column of the SH shared block300.

The ADC221converts the analog output signal Aout from the corresponding column into a digital signal Dout. This AD conversion is also called “reading” of the analog signal. The ADC221is, for example, a single-slope ADC, and includes a comparator222and a counter223. Note that the ADC221is not limited to a single-slope type. For example, a successive approximation register analog to digital converter (SARADC) can be used as the ADC221.

The comparator222compares a reference signal RMP from the DAC213with the output signal Aout. The comparator222supplies a comparison result CMP to the counter223.

The counter223counts a count value over a period until the comparison result CMP is inverted. The counter223outputs a digital signal Dout indicating the count value to the latch circuit224. In addition, the counter223can perform either up counting or down counting, and can switch from one of up counting and down counting to the other under the control of the timing control circuit212.

The latch circuit224holds the digital signal Dout and outputs it under the control of the horizontal transfer scanning circuit215.

[Operation Example of Solid-State Imaging Element]

FIG.7is a timing chart illustrating an example of an operation of the solid-state imaging element from exposure to analog CDS in the first embodiment of the present technology. The vertical scanning circuit211sets the discharge control signal OFG and the reset signals RST1and RST2to the high level over a predetermined period. Timing TO when the period has elapsed corresponds to the start timing of the exposure period.

At timing T1before the lapse of the exposure period, the vertical scanning circuit211sets the control signal PC to the high level.

Then, the vertical scanning circuit211sets the reset signal RST1to the high level over the pulse period from timing T2immediately before the end of the exposure period. Thereby, a floating diffusion layer of the pixel310is initialized. The level of the pixel signal SIG at the time of this initialization is hereinafter referred to as a “P-phase level”. The P-phase level can also be referred to as a reset level.

Furthermore, the vertical scanning circuit211sets the selection signal SEL1and the control signals S0and S1bto the high level over the period from timing T2to timing T3. During this period, the P-phase level of the pixel310is sampled and held.

Then, the vertical scanning circuit211sets the reset signal RST2to the high level over the pulse period from timing T3. Furthermore, the vertical scanning circuit211sets the selection signal SEL2and the control signals S0and S2bto the high level over the period from timing T3to timing T4. During this period, the P-phase level of the pixel320is sampled and held.

Then, the vertical scanning circuit211sets the transfer signal TRG to the high level over the pulse period from timing T5. Accordingly, an amount of charge corresponding to the exposure amount is transferred to the floating diffusion layer. The level of the pixel signal SIG at the time of this transfer is hereinafter referred to as a “D-phase level”. The D-phase level can also be referred to as a signal level. Further, timing T5corresponds to the end timing of the exposure period.

Furthermore, the vertical scanning circuit211sets the selection signal SEL1and the control signal RB to the high level over the period of timing T5to timing T6. During this period, the D-phase level of the pixel310is sampled and held.

Then, the vertical scanning circuit211sets the control signal Sla to the high level over the pulse period from timing T6. During this period, analog CDS for obtaining a difference between the P-phase level and the D-phase level of the pixel310is performed.

Furthermore, the vertical scanning circuit211sets the selection signal SEL2and the control signal RB to the high level over the period of timing T7to timing T8. During this period, the D-phase level of the pixel320is sampled and held.

Then, the vertical scanning circuit211sets the control signal S2ato the high level over the pulse period from timing T8. During this period, analog CDS for obtaining a difference between the P-phase level and the D-phase level of the pixel320is performed.

Then, at timing T9, the vertical scanning circuit211sets the discharge control signal OFG, the reset signals RST1and RST2to the high level, and sets the control signal PC to the low level.

The control illustrated in the drawing is simultaneously performed on all the pixels. That is, exposure is performed by the global shutter method. In this global shutter method, timings of start and end of exposure of all pixels are completely matched.

FIG.8is a diagram illustrating an example of variations of the pixel signal SIG in the first embodiment of the present technology. In the drawing, the vertical axis represents the level of the pixel signal SIG, and the horizontal axis represents time. Immediately before timing T5at which the exposure period ends, the pixel signal SIG becomes “P0”. The reference voltage VREF in the sample-and-hold circuit400is set to a value lower than P0. A difference between the reference voltage VREF and P0 is defined as “P1”. This P1 represents a P-phase level when the reference voltage VREF is used as a reference. In addition, P0 represents a P-phase level when a ground voltage or the like in the pixel is used as a reference.

After timing T5, the pixel signal SIG decreases according to the exposure amount and becomes “D0”. A difference between P0 and D0 is defined as “D1”. This D1 is the net D-phase level obtained by analog CDS. The difference between P1 and D1 represents the D-phase level before analog CDS when the reference voltage VREF is used as a reference. In addition, D0 represents a D-phase level before analog CDS when the ground voltage or the like is used as a reference.

In summary, in a case where the reference voltage VREF is used as a reference, “P1” corresponds to the P-phase level of the pixel310, and “P1-D1” corresponds to the D-phase level before analog CDS. Also, “D1” corresponds to the net D-phase level after analog CDS. Furthermore, the P-phase level of the pixel320and the D-phase levels before and after CDS are “P2”, “P2-D2”, and “D2”.

FIG.9is a diagram for describing an operation of the sample-and-hold circuit400immediately before exposure ends in the first embodiment of the present technology. In the drawing, the transistor is represented by a symbol of a switch, and the amplification transistor463and the selection transistor464are omitted. An arrow in the drawing indicates the direction of the potential when the reference voltage VREF is used as a reference.

As illustrated in a of the drawing, when the P-phase level of the pixel310is input to the input node350, the connection transistor412shifts to a closed state, and the reference voltage VREF is connected to a terminal on the input side of the individual capacitor451. In addition, the short-circuit transistor461shifts to the closed state, and both ends of the common capacitor450are short-circuited. As a result, the P-phase level “P1” of the pixel310based on the reference voltage VREF is held in the individual capacitor451.

Then, as illustrated in b of the drawing, when the P-phase level of the pixel320is input to the input node350, the connection transistor422shifts to the closed state, and the reference voltage VREF is connected to a terminal on the input side of the individual capacitor452. In addition, the short-circuit transistor461shifts to the closed state, and both ends of the common capacitor450are short-circuited. As a result, the P-phase level “P2” of the pixel320based on the reference voltage VREF is held in the individual capacitor452.

As illustrated in the drawing, the sample-and-hold circuit400holds the P-phase level “P1” in the individual capacitor451and holds the P-phase level “P2” in the individual capacitor452.

Note that the P-phase level “P1” is an example of a first reset level described in the claims, and the P-phase level “P2” is an example of a second reset level described in the claims. Further, the circuit including the connection transistors412and422and the short-circuit transistor461is an example of a reset level sampling circuit described in the claims. The connection transistor412is an example of a first connection transistor described in the claims, and the connection transistor422is an example of a second connection transistor described in the claims. The short-circuit transistor461is an example of a common short-circuit transistor described in the claims.

Furthermore, the operation illustrated in the drawing is performed during the period from timing T2to timing T4inFIG.7.

FIG.10is a diagram for describing an operation of analog CDS in the first embodiment of the present technology. In the drawing, the transistor is represented by a symbol of a switch, and the amplification transistor463and the selection transistor464are omitted. An arrow in the drawing indicates the direction of the potential when the reference voltage VREF is used as a reference.

As illustrated in a of the drawing, when the D-phase level of the pixel310is input to the input node350, the connection transistor462shifts to the closed state, and the node of the reference voltage VREF is connected to a terminal on the output side of the common capacitor450. As a result, the D-phase level “P1-D1” before analog CDS is held in the common capacitor450.

Then, as illustrated in b of the drawing, after the connection transistor462shifts to an open state, the short-circuit transistor411shifts to the closed state, and the terminal on the input side of the individual capacitor451and a terminal on the input side of the common capacitor450are short-circuited. The potentials held in the individual capacitor451and the common capacitor450immediately before are opposite in direction. For this reason, “P1” is canceled, and “−(D1)/2” is held in each of the capacitors. The absolute value of “−(D1)/2” is a level corresponding to the difference “D1” between the P-phase level and the D-phase level. The processing of obtaining the difference between the P-phase level and the D-phase level in this manner is called analog CDS.

Next, as illustrated in c of the drawing, when the D-phase level of the pixel320is input to the input node350, the connection transistor462shifts to the closed state, and the node of the reference voltage VREF is connected to the terminal on the output side of the common capacitor450. As a result, the D-phase level “P2-D2” before analog CDS is held in the common capacitor450.

Then, as illustrated in d of the drawing, after the connection transistor462shifts to the open state, the short-circuit transistor421shifts to the closed state, and the terminal on the input side of the individual capacitor452and the terminal on the input side of the common capacitor450are short-circuited. The potentials held in the individual capacitor452and the common capacitor450immediately before are opposite in direction. For this reason, “P2” is canceled, and “−(D2)/2” is held in each of the capacitors. The absolute value of “−(D2)/2” is a level corresponding to the difference “D2” between the P-phase level and the D-phase level.

As illustrated in the drawing, the sample-and-hold circuit400performs analog CDS processing of holding “−(D1)/2” according to the difference between the P-phase level and the D-phase level of the pixel310in the common capacitor450and the individual capacitor451. Furthermore, the sample-and-hold circuit400performs analog CDS processing of holding “−(D2)/2” according to the difference between the P-phase level and the D-phase level of the pixel320in the common capacitor450and the individual capacitor451.

Note that the D-phase level “P1-D1” is an example of a first signal level described in the claims, and the D-phase level “P2-D2” is an example of a second signal level described in the claims. In addition, the circuit including the connection transistor462and the short-circuit transistors411and421is an example of a correlated double sampling circuit described in the claims. Also, the connection transistor462is an example of a common connection transistor described in the claims. The short-circuit transistor411is an example of a first short-circuit transistor described in the claims, and the short-circuit transistor421is an example of a second short-circuit transistor described in the claims.

In addition, the operation illustrated in the drawing is performed in a period between timing T5inFIG.7and the time point when the pulse period has elapsed from timing T8.

FIG.11is a timing chart illustrating an example of a read operation of the solid-state imaging element200in the first embodiment of the present technology. The read operation in the drawing is performed immediately after the analog CDS illustrated inFIGS.7and10.

At timing T10of the start of the read period, the vertical scanning circuit211sets the control signal SEL0to the high level. Then, the vertical scanning circuit211sets the control signals RB and S0to the high level over the period of timing T11to timing T12. During this period, the voltage VG in the sample-and-hold circuit400becomes the reference voltage VREF, and the ADC221performs AD conversion (reading) of the reference voltage VREF by down counting. The reference voltage VREF is removed as an offset voltage by a subsequent circuit.

Subsequently, the vertical scanning circuit211sets the control signal S1bto the high level over the period of timing T12to timing T13. During this period, the voltage VG becomes a level obtained by adding (D1)/2 to the reference voltage VREF, and the ADC221performs AD conversion (reading) of the level by up counting. Since the reference voltage VREF has been AD-converted by down counting, the reference voltage VREF is removed as an offset voltage by subsequent up counting. As a result, (D1)/2 is read by the ADC221. In this manner, processing of removing the offset voltage of the digital signal can be referred to as digital CDS.

Note that the ADC221removes the reference voltage VREF (offset voltage) by down counting and up counting, but the present disclosure is not limited to this configuration. The ADC221may perform only the up counting or the down counting, and a subsequent circuit (the DSP circuit120or the like) may remove the offset voltage.

Then, the vertical scanning circuit211sets the control signals RB and S0to the high level over the period of timing T13to timing T14. During this period, the voltage VG in the sample-and-hold circuit400becomes the reference voltage VREF (offset voltage) again, and the ADC221reads the offset voltage by down counting.

Subsequently, the vertical scanning circuit211sets the control signal S2bto the high level over the period of timing T14to timing T15. During this period, the voltage VG becomes a level obtained by adding (D2)/2 to the reference voltage VREF, and the ADC221reads the level by up counting. As a result, (D2)/2 is read. Then, at timing T16of the end of the read period, the vertical scanning circuit211sets the control signal SEL0to the low level.

The reading illustrated in the drawing is sequentially executed for each row of the SH shared block300. One piece of image data is generated by reading all the rows.

Furthermore, processing of multiplying “(D1)/2” or “(D2)/2” by “2” to obtain D1 or D2 is executed by, for example, the DSP circuit120or the column signal processing circuit220in the subsequent stage. In a case where the column signal processing circuit220performs multiplication, a multiplication circuit is added in the column signal processing circuit220.

FIG.12is a diagram for describing an operation of the sample-and-hold circuit400at the time of reading in the first embodiment of the present technology. In the drawing, the transistor is represented by a symbol of a switch, and the amplification transistor463and the selection transistor464are omitted. An arrow in the drawing indicates the direction of the potential when the reference voltage VREF is used as a reference.

As illustrated in a of the drawing, the short-circuit transistor461and the connection transistor462shift to the closed state immediately after the analog CDS. Accordingly, the voltage of the node on the output side of the common capacitor450becomes the reference voltage VREF. Note that the input node350is in a high impedance state at the time of reading.

Next, as illustrated in b of the drawing, after the short-circuit transistor461and the connection transistor462shift to the open state, the connection transistor412shifts to the closed state. Accordingly, the voltage of the node on the output side becomes a level obtained by adding (D1)/2 to the reference voltage VREF.

Then, as illustrated in c of the drawing, the short-circuit transistor461and the connection transistor462shift to the closed state. Accordingly, the voltage of the node on the output side of the common capacitor450becomes the reference voltage VREF again.

Next, as illustrated in d of the drawing, after the short-circuit transistor461and the connection transistor462shift to the open state, the connection transistor422shifts to the closed state. Accordingly, the voltage of the node on the output side becomes a level obtained by adding (D2)/2 to the reference voltage VREF.

Here, the circuit described in FIG. 3 of Patent Document 1 is assumed as a comparative example.

FIG.13is a circuit diagram illustrating a configuration example of an SH shared block in a comparative example. In the SH shared block of the comparative example, pixels A and B share one sample-and-hold circuit. A reset signal RST1and a transfer signal TX1are input to the pixel A, and a reset signal RST2and a transfer signal TX2are input to the pixel B. That is, unlike the circuit illustrated inFIG.4, an individual reset signal and transfer signal are input for each pixel.

Further, the sample-and-hold circuit of the comparative example includes capacitors113,110A, and110B, and transistors108A,109A,111A,107A,108B,109B,111B, and107B.

A terminal on the input side of the capacitor113is commonly connected to the pixels A and B. The transistor108A opens and closes a path between a terminal on the output side of the capacitor113and one end of the capacitor110A. The transistor109A opens and closes a path between the node of the reference voltage VREF and one end of the capacitor110A. The transistor111A amplifies the voltage at one end of the capacitor110A, and the transistor107A outputs the amplified voltage to the vertical signal line.

The transistor108B opens and closes a path between the terminal on the output side of the capacitor113and one end of the capacitor110B. The transistor109B opens and closes a path between the node of the reference voltage VREF and one end of the capacitor110B. The transistor111B amplifies the voltage at one end of the capacitor110B, and the transistor107B outputs the amplified voltage to the vertical signal line.

FIG.14is a timing chart illustrating an example of an operation of a solid-state imaging element in a comparative example. This drawing is a simplified timing chart of FIG. 4 of Patent Document 1.

In the comparative example, after the P-phase level of the pixel A is sampled and held, the D-phase level of the pixel A is sampled and held. Next, the P-phase level of the pixel B is sampled and held, and then the D-phase level of the pixel B is sampled and held. Thus, in the comparative example, the sampling cannot be performed in the order of the P-phase level of the pixel A, the P-phase level of the pixel B, the D-phase level of the pixel A, and the D-phase level of the pixel B. This is because, in the circuit configuration illustrated inFIG.13, the common capacitor113is used for the samples at the P-phase level of both the pixels A and B.

Then, in the comparative example, since it is necessary to perform the sampling in the order of the P-phase level of the pixel A, the D-phase level of the pixel A, the P-phase level of the pixel B, and the D-phase level of the pixel B, it is necessary to shift the timings of the start and end of the exposure of the pixels A and B. For example, an exposure period A of the pixel A starts at timing T0, and ends at timing T2. Furthermore, an exposure period B of the pixel B starts at timing T1, and ends at timing T3.

As illustrated inFIG.14, in the comparative example, the timings of the start and end of the exposure of the pixels A and B do not match, resulting in an incomplete global shutter method at the time of exposure.

On the other hand, in the sample-and-hold circuit400illustrated inFIG.4, the P-phase level of each of the pixels310and320is held in the individual capacitors451and452, and the common capacitor450is not used. For this reason, the sample-and-hold circuit400can perform sampling in the order of the P-phase level of the pixel310, the P-phase level of the pixel320, the D-phase level of the pixel310, and the D-phase level of the pixel320. For this reason, the timings of the start and end of exposure of the pixels310and320can be completely matched.

Furthermore, in the comparative example, the level based on the reference voltage VREF is sampled at the end of exposure, and the level based on the reference voltage VREF is also read at the time of reading. For this reason, in a case where the reference voltage VREF has different values at the end of exposure and at the time of reading due to voltage fluctuation in a long period, an error occurs in the read digital signal. This error may deteriorate the PRNU.

On the other hand, in the sample-and-hold circuit400illustrated inFIG.4, −(D2)/2 and −(D1)/2 that do not depend on the reference voltage VREF are held at the end of exposure. For this reason, even in a case where the reference voltage VREF is different between the end of exposure and the time of reading due to the voltage fluctuation in the long period, an error is less likely to occur in the digital signal. Accordingly, deterioration of the PRNU is suppressed.

The matching of the exposure timings and the suppression of the deterioration of the PRNUs described above can improve the image quality of the image data in the sample-and-hold circuit400illustrated inFIG.4.

Thus, according to the first embodiment of the present technology, the sample-and-hold circuit400causes the individual capacitors451and452to hold the P-phase level, and causes the individual capacitors451and452and the common capacitor450to hold the level corresponding to the difference between the P-phase level and the D-phase level. Accordingly, the timings of the start and end of exposure of the pixels310and320can be completely matched, and deterioration of the PRNU can be suppressed. As a result, the image quality of the image data is improved.

2. Second Embodiment

In the first embodiment described above, the solid-state imaging element200sequentially reads the reference voltage (offset voltage), a sum value of (D1)/2 and the reference voltage, the reference voltage, and a sum value of (D2)/2 and the reference voltage for each row. However, in this reading method, the reading speed may be insufficient. A solid-state imaging element200of a second embodiment is different from that of the first embodiment in that the second reading of the reference voltage is omitted and the reading speed is increased.

FIG.15is a timing chart illustrating an example of a read operation of the solid-state imaging element200in the second embodiment of the present technology. The solid-state imaging element200of the second embodiment is different from that of the first embodiment in that the second reading of the reference voltage (offset voltage) is omitted.

As illustrated in the drawing, the ADC221performs AD conversion (reading) of the reference voltage VREF (offset voltage) during a period from timing T11to timing T12. The column signal processing circuit220holds the read reference voltage VREF. During the period from timing T12to timing T13, the ADC221reads a sum value of the reference voltage VREF and (D1)/2 (D-phase level) of the pixel310.

The vertical scanning circuit211sets the control signals RB and S0to the high level over the period of timing T13to timing T14. The ADC221does not perform reading during this period. Since the second reading of the reference voltage is omitted, the period between timing T13to timing T14of the second embodiment is set to a period shorter than the period required for AD conversion.

Then, during the period from timing T15to timing T16, the ADC221reads a sum value of the reference voltage VREF and (D2)/2 of the pixel320. The column signal processing circuit220uses the held reference voltage VREF at the time of digital CDS of the pixel320.

As illustrated in the drawing, by omitting the second reading of the reference voltage for each row, the reading speed can be increased.

Hereinafter, the reading of the first embodiment is referred to as “PDPD reading”, and the reading of the second embodiment is referred to as “PDD reading”.

FIG.16is a block diagram illustrating a configuration example of the column signal processing circuit220in the second embodiment of the present technology. The column signal processing circuit220of the second embodiment is different from that of the first embodiment in that it further includes a selector225, a memory226, and a subtractor227for each column.

The selector225outputs the digital signal from the ADC221to either the subtractor227or the memory226under the control of the timing control circuit212. The memory226holds a digital signal. The subtractor227obtains a difference between the digital signal from the selector225and the digital signal held in the memory226, and outputs the difference to the latch circuit224.

The timing control circuit212controls the selector225to output the reference voltage VREF of the pixel310to the memory226. The memory226holds the reference voltage VREF. Then, the timing control circuit212controls the selector225to output a sum value of the reference voltage VREF and (D1)/2 to the subtractor227. Furthermore, the timing control circuit212controls the selector225to output a sum value of the reference voltage VREF and (D2)/2 to the subtractor227.

Note that the digital CDS processing of the circuit including the selector225, the memory226, and the subtractor227can be executed by a subsequent circuit (such as the DPS circuit120) instead of the column signal processing circuit220.

In this way, according to the second embodiment of the present technology, since the ADC221omits the second reading of the reference voltage (offset voltage), the reading speed can be increased.

3. Third Embodiment

In the first embodiment described above, two pixels share one sample-and-hold circuit400, but the number of pixels sharing the sample-and-hold circuit400is not limited to two pixels. A solid-state imaging element200of a third embodiment is different from that of the first embodiment in that four pixels share one sample-and-hold circuit400.

FIG.17is a circuit diagram illustrating a configuration example of the SH shared block300in the third embodiment of the present technology. The SH shared block300of the third embodiment is different from that of the first embodiment in that it further includes pixels330and340, short-circuit transistors431and441, connection transistors432and442, and individual capacitors453and454.

The circuit configuration of each of the pixels330and340is similar to that of the pixels310and320. These four pixels are arranged in, for example, 2 rows×2 columns.

One end (right side in the drawing) of each of the individual capacitors453and454is connected to the output-side node405.

The short-circuit transistor431opens and closes a path between the other end (left side in the drawing) of the individual capacitor453and the input node350according to a control signal S3afrom the vertical scanning circuit211. The short-circuit transistor441opens and closes a path between the other end (left side in the drawing) of the individual capacitor454and the input node350according to a control signal S4afrom the vertical scanning circuit211.

The connection transistor432opens and closes a path between a node of a reference voltage VREF and the other end of the individual capacitor453according to a control signal S3bfrom the vertical scanning circuit211. The connection transistor442opens and closes a path between a node of a reference voltage VREF and the other end of the individual capacitor454according to a control signal S4bfrom the vertical scanning circuit211.

As illustrated in the drawing, by sharing one sample-and-hold circuit by four pixels, the number of elements per pixel can be reduced as compared with the first embodiment in which two pixels share one sample-and-hold circuit.

Note that more than four pixels (eight pixels) can also share one sample-and-hold circuit. In this case, transistors corresponding to the short-circuit transistor411and the connection transistor412and an individual capacitor are added for each pixel. If the number of pixels to be shared is N (N is an integer), the number M1of capacitors in the sample-and-hold circuit400is expressed by the following equation.
M1=N+1  Equation 1

Furthermore, the number M2of transistors in the sample-and-hold circuit400is expressed by the following equation.
M2=2N+4  Equation 2

Furthermore, the number M3of control signals (Sla and the like) to the sample-and-hold circuit400is expressed by the following equation.
M3=2N+3  Equation 3

FIG.18is a diagram illustrating an arrangement example of MIM elements in the third embodiment of the present technology. In the SH shared block300, five MIM elements are disposed as a common capacitor450and individual capacitors451to454. With the circuit chip202as a lower chip, the individual capacitors451to454are disposed immediately below the corresponding pixels. Furthermore, the common capacitor450is disposed between the individual capacitors451to454(for example, the central portion of 2 rows×2 columns).

Note that the second embodiment can also be applied to the third embodiment. In this case, the second, third, and fourth reading of the reference voltage is omitted. Similarly, in a case where the number of pixels to be shared is larger than four, reading of the reference voltage from the second time onwards is omitted.

Thus, according to the third embodiment of the present technology, since four pixels share one sample-and-hold circuit400, the number of elements per pixel can be reduced as compared with a case where two pixels share one sample-and-hold circuit400.

Next, respective features of the comparative example and the above-described first to third embodiments will be described.

FIG.19is a diagram for describing features of the comparative example and the sample-and-hold circuit400in the embodiment of the present technology. The number of capacitors in the sample-and-hold circuit of the comparative example is expressed by Equation 1. In addition, the number of transistors in the sample-and-hold circuit of the comparative example is 4N. On the other hand, in the sample-and-hold circuit400, the number of capacitors is the same as that in the comparative example. The number of transistors is expressed by Equation 2.

Comparing the number of transistors, in a case where N is 3 or more, the number of transistors in the sample-and-hold circuit400is smaller than that in the comparative example.

Also, the number of control signals of the comparative example is 3N. On the other hand, in the sample-and-hold circuit400, the number of control signals is expressed by Equation 3. Comparing the number of control signals, in a case where N is 3 or more, the number of control signals in the sample-and-hold circuit400is smaller than that in the comparative example. For this reason, the number of signal lines for transmitting control signals can be reduced as compared with the comparative example.

In addition, the transmission gain of the sample-and-hold circuit400is equivalent to that of the comparative example. Furthermore, as described above, in the comparative example, the start and end timings of the exposure of each of the plurality of pixels sharing the sample-and-hold circuit do not match. On the other hand, the start and end timings of the exposure of the plurality of pixels sharing the sample-and-hold circuit400match.

In addition, as described above, in the comparative example, voltage fluctuation tolerance in a long period is weak. On the other hand, in the sample-and-hold circuit400, voltage fluctuation tolerance in a long period is strong. Furthermore, in the comparative example, PDPD reading is possible, but PDD reading is not possible. On the other hand, in a case where the sample-and-hold circuit400is used, both the PDPD reading and the PDD reading are possible.

4. Example of Application to Mobile Body

The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may also be realized as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot.

FIG.20is a block diagram illustrating a schematic configuration example of a vehicle control system which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

The vehicle control system12000includes a plurality of electronic control units connected to each other via a communication network12001. In the example illustrated inFIG.20, the vehicle control system12000includes a driving system control unit12010, a body system control unit12020, an outside-vehicle information detecting unit12030, an in-vehicle information detecting unit12040, and an integrated control unit12050. Furthermore, as a functional configuration of the integrated control unit12050, a microcomputer12051, a sound/image output section12052, and an in-vehicle network interface (I/F)12053are illustrated.

The driving system control unit12010controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit12010functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

The body system control unit12020controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit12020functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit12020. The body system control unit12020receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The outside-vehicle information detecting unit12030detects information about the outside of the vehicle including the vehicle control system12000. For example, the outside-vehicle information detecting unit12030is connected with an imaging section12031. The outside-vehicle information detecting unit12030makes the imaging section12031image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit12030may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section12031is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section12031can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section12031may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit12040detects information about the inside of the vehicle. The in-vehicle information detecting unit12040is, for example, connected with a driver state detecting section12041that detects the state of a driver. The driver state detecting section12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section12041, the in-vehicle information detecting unit12040may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

The microcomputer12051can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040, and output a control command to the driving system control unit12010. For example, the microcomputer12051can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

In addition, the microcomputer12051can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040.

Furthermore, the microcomputer12051can output a control command to the body system control unit12020on the basis of information regarding the outside of the vehicle, the information being acquired by the outside-vehicle information detecting unit12030. For example, the microcomputer12051can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit12030.

The sound/image output section12052transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example ofFIG.20, an audio speaker12061, a display section12062, and an instrument panel12063are illustrated as the output device. The display section12062may, for example, include at least one of an on-board display and a head-up display.

FIG.21is a diagram illustrating an example of the installation position of the imaging section12031.

InFIG.21, the imaging section12031includes imaging sections12101,12102,12103,12104, and12105.

The imaging sections12101,12102,12103,12104, and12105are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle12100as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section12101provided to the front nose and the imaging section12105provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle12100. The imaging sections12102and12103provided to the sideview mirrors obtain mainly an image of the sides of the vehicle12100. The imaging section12104provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle12100. The imaging section12105provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Note thatFIG.21illustrates an example of imaging ranges of the imaging sections12101to12104. An imaging range12111represents the imaging range of the imaging section12101provided to the front nose. Imaging ranges12112and12113respectively represent the imaging ranges of the imaging sections12102and12103provided to the sideview mirrors. An imaging range12114represents the imaging range of the imaging section12104provided to the rear bumper or the back door. A bird's-eye image of the vehicle12100as viewed from above is obtained by superimposing image data imaged by the imaging sections12101to12104, for example.

At least one of the imaging sections12101to12104may have a function of obtaining distance information. For example, at least one of the imaging sections12101to12104may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer12051can determine a distance to each three-dimensional object within the imaging ranges12111to12114and a temporal change in the distance (relative speed with respect to the vehicle12100) on the basis of the distance information obtained from the imaging sections12101to12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle12100and which travels in substantially the same direction as the vehicle12100at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer12051can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

For example, the microcomputer12051can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections12101to12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer12051identifies obstacles around the vehicle12100as obstacles that the driver of the vehicle12100can recognize visually and obstacles that are difficult for the driver of the vehicle12100to recognize visually. Then, the microcomputer12051determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer12051outputs a warning to the driver via the audio speaker12061or the display section12062, and performs forced deceleration or avoidance steering via the driving system control unit12010. The microcomputer12051can thereby assist in driving to avoid collision.

At least one of the imaging sections12101to12104may be an infrared camera that detects infrared rays. The microcomputer12051can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections12101to12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections12101to12104as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer12051determines that there is a pedestrian in the imaged images of the imaging sections12101to12104, and thus recognizes the pedestrian, the sound/image output section12052controls the display section12062so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section12052may also control the display section12062so that an icon or the like representing the pedestrian is displayed at a desired position.

An example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure may be applied to the imaging section12031, for example, out of the configurations described above. Specifically, the imaging device inFIG.1can be applied to the imaging section12031. By applying the technology according to the present disclosure to the imaging section12031, a more easily viewable captured image can be obtained, by which fatigue of the driver can be reduced.

Note that the embodiments described above are examples for embodying the present technology, and the matters in the embodiments and the matters used to specify the invention in the claims have a corresponding relationship. Similarly, there is a correspondence relationship between the matters specifying the invention in claims and the matters in the embodiments of the present technology having the same names. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the gist thereof.

Note that, the effect described in the present specification is illustrative only and is not limitative; there may also be another effect.

Note that the present technology may also have a following configuration.(1) A solid-state imaging element including:a first pixel that generates a predetermined first reset level and a first signal level according to an exposure amount;a second pixel that generates a predetermined second reset level and a second signal level according to an exposure amount; anda sample-and-hold circuit that performs reset level sampling processing and correlated double sampling processing, the reset level sampling processing causing a first individual capacitor to hold the first reset level and causing a second individual capacitor to hold the second reset level, the correlated double sampling processing causing a common capacitor and the first individual capacitor to hold a first output level according to a difference between the first reset level and the first signal level and causing the common capacitor and the second individual capacitor to hold a second output level according to a difference between the second reset level and the second signal level.(2) The solid-state imaging element according to (1),in which the sample-and-hold circuit includes:the first individual capacitor;the second individual capacitor;the common capacitor;a reset level sampling circuit that performs the reset level sampling processing; anda correlated double sampling circuit that performs the correlated double sampling processing.(3) The solid-state imaging element according to (2) above,in which one ends of the first individual capacitor, the second individual capacitor, and the common capacitor are commonly connected to a predetermined output-side node,another end of the common capacitor is commonly connected to the first and second pixels, andthe reset level sampling circuit includes:a first connection transistor that connects a node of a predetermined reference voltage to another end of the first individual capacitor;a second connection transistor that connects a node of the reference voltage to another end of the second individual capacitor; anda common short-circuit transistor that short-circuits both ends of the common capacitor.(4) The solid-state imaging element according to (3) above,in which the correlated double sampling circuit includes:a common connection transistor that connects a node of the reference voltage to the output-side node;a first short-circuit transistor that short-circuits between the another end of the first individual capacitor and the another end of the common capacitor; anda second short-circuit transistor that short-circuits between the another end of the second individual capacitor and the another end of the common capacitor.(5) The solid-state imaging element according to any one of (1) to (4) above, further including an analog-to-digital converter,in which the sample-and-hold circuit further performs, after the correlated double sampling processing, processing of sequentially outputting the reference voltage, a sum value of the reference voltage and the first output level, the reference voltage, and a sum value of the reference voltage and the second output level to the analog-to-digital converter.(6) The solid-state imaging element according to (5) above, in which the analog-to-digital converter sequentially converts the reference voltage, a sum value of the reference voltage and the first output level, the reference voltage, and a sum value of the reference voltage and the second output level into a digital signal.(7) The solid-state imaging element according to (5) above, in which the analog-to-digital converter sequentially converts the reference voltage, a sum value of the reference voltage and the first output level, and a sum value of the reference voltage and the second output level into a digital signal.(8) The solid-state imaging element according to any one of (1) to (7) above, further including:a third pixel that generates a predetermined third reset level and a third signal level according to an exposure amount; anda fourth pixel that generates a predetermined fourth reset level and a fourth signal level according to an exposure amount,in which the sample-and-hold circuit causes a third individual capacitor to hold the third reset level and causes a fourth individual capacitor to hold the fourth reset level in the reset level sampling processing, and causes the common capacitor and the third individual capacitor to hold a third output level according to a difference between the third reset level and the fourth signal level and causes the common capacitor and the fourth individual capacitor to hold a fourth output level according to a difference between the fourth reset level and the fourth signal level in the correlated double sampling processing.(9) An imaging device including:a first pixel that generates a predetermined first reset level and a first signal level according to an exposure amount;a second pixel that generates a predetermined second reset level and a second signal level according to an exposure amount;a sample-and-hold circuit that performs reset level sampling processing and correlated double sampling processing, the reset level sampling processing causing a first individual capacitor to hold the first reset level and causing a second individual capacitor to hold the second reset level, the correlated double sampling processing causing a common capacitor and the first individual capacitor to hold a first output level according to a difference between the first reset level and the first signal level and causing the common capacitor and the second individual capacitor to hold a second output level according to a difference between the second reset level and the second signal level; anda column signal processing circuit that converts a level output from the sample-and-hold circuit into a digital signal.(10) A method for controlling a solid-state imaging element, the method including:a reset level sampling step of causing a first individual capacitor to hold a predetermined first reset level and causing a second individual capacitor to hold a predetermined second reset level; anda sample-and-hold step of performing correlated double sampling processing of causing a common capacitor and the first individual capacitor to hold a first output level according to a difference between the first reset level and a first signal level according to an exposure amount and causing the common capacitor and the second individual capacitor to hold a second output level according to a difference between the second reset level and a second signal level according to an exposure amount.

REFERENCE SIGNS LIST

100Imaging device107A,108A,109A,111A,107B,108B,109B,111B Transistor110Optical unit110A,110B,113Capacitor120DSP circuit130Display unit140Operation unit150Bus160Frame memory170Storage unit180Power supply unit200Solid-state imaging element201Light reception chip202Circuit chip211Vertical scanning circuit212Timing control circuit213DAC214Pixel array unit215Horizontal transfer scanning circuit220Column signal processing circuit221ADC222Comparator223Counter224Latch circuit225Selector226Memory227Subtractor300SH shared block310,320,330,340Pixel311,321Charge discharge transistor312,322Photoelectric conversion element313,323Transfer transistor314,324Reset transistor315,325,463Amplification transistor316,326,464Selection transistor351,412,422,432,442,462Connection transistor352Load MOS transistor400Sample-and-hold circuit411,421,431,441,461Short-circuit transistor450Common capacitor451,452,453,454Individual capacitor12031Imaging section