Patent ID: 12206340

DETAILED DESCRIPTION OF THE INVENTION

InFIG.1, a generalized circuit topology100for an i-th sub-module is shown in a configuration of the circuit topology according to aspects of the invention. A first intermediate circuit capacitor Ci1111and, in parallel thereto, a first half bridge having a fifth semiconductor switch Si5105and a sixth semiconductor switch Si6106are arranged between a lower input connection131and an upper input connection132. Furthermore in parallel thereto, a second half bridge is connected to a first semiconductor switch Si1101and a second semiconductor switch Si2102, and a third half bridge is connected to a third semiconductor switch Si3103, and a fourth semiconductor switch Si4104is connected to the lower input connection131and, via a respectively repeatable voltage level unit120and a seventh semiconductor switch Si7107to the upper input connection132. Moreover, a second intermediate circuit capacitor Ci2is arranged between a center tap of the first half bridge and the seventh semiconductor switch Si7107. By a respective center tap at the second and third half bridges, an output voltage is provided at an output connection139to a load. The repeatable voltage level unit120comprises a third intermediate circuit capacitor Ci3, a further half bridge comprising an eighth semiconductor switch Si8108and a ninth semiconductor switch Si9109, and a tenth semiconductor switch. By respectively repeating the voltage level unit120, the generalized circuit topology100is expanded by respectively two voltage levels, whereby the output voltage can advantageously be varied according to a predetermined number of voltage levels.

FIG.2shows circuit diagrams230,250,270,290with different numbers of voltage level units in further configurations of the circuit topology according to aspects of the invention. While a three-level circuit topology230known from the prior art can be derived from the generalized circuit topology100inFIG.1by omitting the first half bridge with semiconductor switches105and106, as well as further components107and112, a five-level circuit topology250, a seven-level circuit topology270, and a nine-level circuit topology290are correspondingly obtained by omitting the voltage level unit120, by arranging once the voltage level unit120, and by arranging twice the voltage level unit120ofFIG.1. In the nine-level circuit topology290, the repeated arrangement adds a repeated eighth semiconductor switch Si11208, a repeated ninth semiconductor switch Si12209, a repeated tenth semiconductor switch Si13210, and a repeated third intermediate circuit capacitor Ci4213.

FIG.3shows current paths321,331,341,351,361,371in a circuit diagram310,320,330,340,350,360,370with five voltage levels in yet a further configuration of the circuit topology according to aspects of the invention. Using the five-level circuit topology310, a first zero-voltage-level path321in the circuit diagram320, a positive-voltage-level path331in the circuit diagram330, a negative-voltage-level path341in the circuit diagram340, a second zero-voltage-level path351in the circuit diagram350, a dual-positive-voltage-level path361in the circuit diagram360, and a dual-negative-voltage-level path371in the circuit diagram370are shown. Six different current paths321,331,341,351,361,371are thus shown, resulting in five voltage levels −2VCi1, −VCi1, 0, +VCi1, +2VCi1. This is achieved via seven (power) semiconductor switches Si1101, Si2102, Si3103, Si4104, Si5105, Si6106, Si7107and two intermediate circuit capacitors Ci1111and Ci2112, wherein in the second and third half bridges, the respectively upper semiconductor switches Si1101and Si3103are switched complementarily to the respectively lower semiconductor switches Si2102and Si4104. It should be noted that either the lower semiconductor switches (Si2102and Si4104) or the upper semiconductor switches (Si1101and Si3103) of the second and third half bridges respectively comprise an internal antiparallel diode, while the latter are optional in the respectively other semiconductor switches of the second and third half bridges, i.e., the respectively upper semiconductor switches (Si1101and Si3103) or lower semiconductor switches (Si2102and Si4104). Just as optional are internal antiparallel diodes in the fifth semiconductor switch Si5105and the sixth semiconductor switch Si6106of the first half bridge, while the seventh semiconductor switch Si7107must not comprise an internal antiparallel diode. As can be seen from the circuit topology according to aspects of the invention, a negative connection of the first intermediate circuit capacitor111is intrinsically connected to a zero point of a load phase. Depending on a respective switching state of the sub-module, one of five voltage levels of the output voltage can be represented, which is described further below.

First, with circuit diagrams320and350, there are two zero-voltage-level paths321and351, which do not provide a voltage contribution to a load current flowing through the output connection139, wherein either the semiconductor switches Si1101and Si3103in the first zero-voltage-level path321and the semiconductor switches Si2102and Si4104in the second zero-voltage-level path351are closed. Meanwhile, the respective zero-voltage-level paths321and351do not affect the two intermediate circuit capacitors Ci1111and Ci2112, wherein, however, it is possible that said capacitors, possibly connected in parallel to balance their capacitor voltages, may be charged by a DC voltage source connected to the input connections. A DC voltage source or a DC current source may be realized as a battery, capacitor, solar cell or solar module, DC voltage or DC current output of an electrical converter (e.g., power electronics), rectifier output, or the like,

The positive-voltage-level path331in the circuit diagram330is formed by closed semiconductor switches Si2102, Si3103, Si6106, and Si7107and adds a voltage level +VCi1to the load current. The respective closed semiconductor switches charge the second intermediate circuit capacitor Ci2112up to the capacitor voltage VCi1so that VCi1=VCi2.

Two voltage levels Vi=VCi1+VCi11are achieved in the circuit diagram360by the dual-positive-voltage-level path361with the two intermediate circuit capacitors Ci1111and Ci2112. Since, in a switching cycle for generating an alternating voltage, a switching state with two positive voltage levels follows a switching state with one positive voltage level, the intermediate circuit capacitor Ci2112was charged to the capacitor voltage VCi2=VCi1in the previously actuated switching state with one voltage level. The two capacitor voltages are thus equal and Vi=+2VCi1applies. The dual-positive-voltage-level path361is formed by means of closed semiconductor switches Si2102, Si3103, and Si5105, while the remaining semiconductor switches of the sub-module are open.

In the negative-voltage-level path341, the semiconductor switches Si1101, Si4104, Si6106, and Si7107are closed, resulting in an output voltage Vi=−VCi1. In particular, the two closed semiconductor switches Si6106and Si7107form a current path through which the second intermediate circuit capacitor Ci2112is charged to the capacitor voltage of the first intermediate circuit capacitor Ci1111, ultimately resulting in VCi2=VCi1when charging is completed.

The dual-negative-voltage-level path371is formed by closed semiconductor switches Si1101, Si4104, and Si5105, and the lowest output voltage is formed with Vi=−(VCi1+VCi2). Since, in the switching cycle for generating the alternating voltage, a switching state with two negative voltage levels follows a switching state with one negative voltage level, the intermediate circuit capacitor Ci2112was charged to the capacitor voltage VCi2=VCi1in the previously actuated switching state with one voltage level. The two capacitor voltages are thus equal and Vi=−2VCi1applies.

The sub-module states leading to a respective output voltage are shown in Table 1 as a function of a respective semiconductor switch position.

TABLE 1DiagramSi1Si2Si3Si4Si5Si6Si7Vi320ONOFFONOFFOFFOFFOFF0330OFFONONOFFOFFONON+VCi1340ONOFFOFFONOFFONON−VCi1350OFFONOFFONOFFOFFOFF0360OFFONONOFFONOFFOFF+2 VCi1370ONOFFOFFONONOFFOFF−2 VCi1

FIG.4shows a selection of semiconductor switches for the circuit topology according to aspects of the invention. As explained above, the antiparallel diode is necessary for some semiconductor switches in the sub-module, while it is not absolutely necessary or even prohibited for other semiconductor switches. A selection of semiconductor switches with an antiparallel diode is shown in diagram410. Although a symbol used in the circuit diagrams of the FIGs. for the semiconductor switches of the half bridges stands for a metal-oxide-semiconductor field-effect transistor MOSFET411, it may also be replaced in terms of circuitry by a bipolar junction transistor (BJT)412or a field-effect transistor (FET)413or a bipolar junction transistor with an isolated gate electrode and npn structure (IGBT/NPN)414or an n-channel bipolar junction transistor with an isolated gate electrode (IGBT/N-channel)415, each provided with the antiparallel diode. However, the selection shown is not intended to exclude further semiconductor switch types with an antiparallel diode. A selection of semiconductor switches without an antiparallel diode is shown in diagram420. Although a symbol used in the circuit diagrams of the FIGs. for such semiconductor switches stands for a bipolar junction transistor with an isolated gate electrode and npn structure (IGBT/NPN)421, it may also be replaced in terms of circuitry by a bipolar junction transistor (BJT)422or a field-effect transistor (FET)423or an n-channel bipolar junction transistor with an isolated gate electrode (IGBT/N-channel)424or a field-effect transistor (FET) with an upstream diode425. However, the selection shown here is also not intended to exclude further semiconductor switch types without an antiparallel diode.

FIG.5shows a control scheme500for second and third half bridges of the circuit topology according to aspects of the invention by means of pulse duration modulation. In order to generate a sinusoidal waveform in the output voltage of each sub-module, the pulse duration modulation is used, while voltage references for multiphase voltages are provided by changing a respective reference voltage510for a respective sub-module. This is implemented by means of the control scheme500, wherein the reference voltage510of the i-th phase Vi* and a carrier signal520are used to generate a gate signal501for semiconductor switches Si1, a gate signal502for semiconductor switches Si2, a gate signal503for semiconductor switches Si3, and a gate signal504for semiconductor switches Si4. A whole range of control methods for load regulation are conceivable in order to generate the reference voltage510. A simple example is a sinusoidal waveform:

Vi*=sin⁡(2⁢π⁢ft+2⁢π⁢iN).(12)

FIG.6schematically shows a circuit600with a single load630in a first configuration of the circuit topology according to aspects of the invention. Without being connected to further sub-modules, the circuit600generates a single-phase AC current for the single load630from a DC current source611.

FIG.7schematically shows a parallel connection700of sub-modules in a second configuration of the multilevel converter according to aspects of the invention. The respective sub-modules701,702,703,704connected in parallel to a DC current source711at their input connections each generate a phase of a multiphase current for a multiphase load730.

FIG.8schematically shows a serial connection800of sub-modules in a further configuration of the multilevel converter according to aspects of the invention. The respective sub-modules701,702,703,809each generate a phase of a multiphase current for a multiphase load730. The sub-modules701,702,703,809are connected in series to one another at their input connections, wherein a first sub-module701and an N-th sub-module809are connected to the DC current source711. As a result, an input voltage of each sub-module701,702,703,809is reduced by a divisor 1/ N compared to a terminal voltage VDCof the DC current source711(see Eq. (9)).

FIG.9shows two replacement circuit diagrams910,920for the DC voltage output in another configuration of the circuit topology according to aspects of the invention. By suitable controlling of a respective sub-module, and in particular of the semiconductor switches Si3103and Si4104in the third half bridge (seeFIG.1), the respective sub-module can be used to output DC voltage, depending on the number of voltage level units120with a different switchable voltage value. While the further semiconductor switches105,106,107,108,109,110of the respective sub-module are suitably switched to generate a selected voltage level, the third semiconductor switch Si3103ofFIG.1is open in the replacement circuit diagram910so that DC voltage connections911result for connection to 9 a DC voltage load, whereas the fourth semiconductor switch Si4104ofFIG.1is open in the replacement circuit diagram920so that DC voltage connections921result for connection to the DC voltage load,

FIG.10shows two circuit diagrams1010,1020with parallel functionality in yet other configurations of the circuit topology according to aspects of the invention. In circuit diagram1010, in accordance with known implementations of parallel functionality in modular multilevel converters, a connection1018to a preceding adjacent sub-module in a strand and a connection1019to a following adjacent sub-module in the strand are formed, but for outputting a DC current. In the circuit diagram1020, a fourth half bridge with an eleventh semiconductor switch Si111021and a twelfth semiconductor switch Si121022, and a fifth half bridge with a thirteenth semiconductor switch Si131023and a fourteenth semiconductor switch Si141024are additionally arranged in the circuit topology according to aspects of the invention (reference sign100inFIG.1). With the center taps at the second and third half bridges (denoted inFIG.1by reference sign139), a connection1029to a following adjacent sub-module in the strand is formed in accordance with known implementations of parallel functionality in modular multilevel converters, e.g., in the aforementioned MMSPC. By the center tap at the two newly added fourth and fifth half bridges, a connection1028is formed to a preceding adjacent sub-module in the strand. The circuit diagram1020is provided for an alternating current. Due to the arrangement according to aspects of the invention of the first half bridge with the semiconductor switches Si5105and Si6106and the repeatable voltage level unit120, a voltage contribution of the respective sub-module to the alternating current can be formed.

LIST OF REFERENCE NUMBERS

100Generalized circuit topology for i-th sub-module101First semiconductor switch Si1102Second semiconductor switch Si2103Third semiconductor switch Si3104Fourth semiconductor switch Si4105Fifth semiconductor switch Si5106Sixth semiconductor switch Si6107Seventh semiconductor switch Si7108Eighth semiconductor switch Si8109Ninth semiconductor switch Si9110Tenth semiconductor switch Si10111First intermediate circuit capacitor Ci1112Second intermediate circuit capacitor Ci2113Third intermediate circuit capacitor Ci3120Repeatable voltage level unit131Lower input connection132Upper input connection139Connection to Load208Repeated eighth semiconductor switch Si11209Repeated ninth semiconductor switch Si12210Repeated tenth semiconductor switch Si13213Repeated third intermediate circuit capacitor Ci4230Circuit with three-level circuit topology250Circuit with five-level circuit topology270Circuit with seven-level circuit topology290Circuit with nine-level circuit topology310Five-level circuit topology320Circuit diagram with output voltage zero321First zero-voltage-level path330Circuit diagram with output voltage Vi331Positive-voltage-level path340Circuit diagram with output voltage −Vi341Negative-voltage-level path350Circuit diagram with output voltage zero351Second zero-voltage-level path360Circuit diagram with output voltage 2Vi361Dual-positive-voltage-level path370Circuit diagram with output voltage −2Vi371Dual-negative-voltage-level path410Semiconductor switch with an antiparallel diode411MOSFET412Bipolar junction transistor BJT413FET414IGBT (NPN)415IGBT (N-channel)420Semiconductor switch without an antiparallel diode421IGBT (NPN)422BJT423FET424IGBT (N-channel)425FET and diode500Control scheme for pulse duration modulation501To Gate Si1502To Gate Si2503To Gate Si3504To Gate Si4510Reference voltage of the i-th phase Vi*520Carrier signal600Circuit diagram for single load611DC current source630Single-phase load700Circuit diagram with parallel connection711DC current source701First sub-module702Second sub-module703Third sub-module704Fourth sub-module730Multiphase load800Circuit diagram with serial connection809N-th sub-module910Replacement circuit diagram with first variant for DC output911Connection to Load920Replacement circuit diagram with second variant for DC output921Connection to Load1010Circuit diagram with DC output as first variant1018Connection to the preceding sub-module1019Connection to the following sub-module1020Circuit diagram with AC output as second variant1021Eleventh semiconductor switch1022Twelfth semiconductor switch1023Thirteenth semiconductor switch1024Fourteenth semiconductor switch1028Connection to the preceding sub-module1029Connection to the following sub-module