Patent ID: 12244498

DETAILED DESCRIPTION

To help those skilled in the art understand technical solutions of the present disclosure better, the present disclosure is further described in detail below in combination with accompanying drawings and specific embodiments. It should be understood that the accompanying drawings and embodiments of the present disclosure are for exemplary purposes only and are not intended to limit the scope of protection of the present disclosure.

It should be understood that the individual steps documented in the method embodiments of the present disclosure may be performed in a different order, and/or in parallel. In addition, the method embodiments may include additional steps and/or omit the steps illustrated. The scope of the present disclosure is not limited in this regard.

The term “include” and its variations are used herein as an open inclusion, that is, “including, but not limited to”. The term “based on” means “based, at least in part, on”. The term “an embodiment” means “at least one embodiment”. The term “another embodiment” means “at least one additional embodiment”. The term “some embodiments” means “at least some embodiments”. Relevant definitions of other terms will be given in the descriptions below.

It should be noted that the concepts such as “first” and “second” mentioned in the present disclosure are used only to distinguish between different apparatuses, modules or units, and are not intended to define the order or mutual interdependence of the functions performed by these apparatuses, modules or units. The terms “module,” “sub-module,” “circuit,” “sub-circuit,” “circuitry,” “sub-circuitry,” “unit,” or “sub-unit” may include memory (shared, dedicated, or group) that stores code or instructions that can be executed by one or more processors. A module may include one or more circuits with or without stored code or instructions. The module or circuit may include one or more components that are directly or indirectly connected. These components may or may not be physically attached to, or located adjacent to, one another. A unit or module may be implemented purely by software, purely by hardware, or by a combination of hardware and software. In a pure software implementation, for example, the unit or module may include functionally related code blocks or software components, that are directly or indirectly linked together, so as to perform a particular function. For example, a “receiving unit” may also be referred to as a “receiving circuit” or a “receiver”.

It should be noted that the modifications of “one”, “a” and “plurality of” referred to in the present disclosure are illustrative rather than limiting, and it should be understood by those skilled in the art to mean “one or more” unless the context clearly indicates otherwise.

The names of messages or information exchanged between the plurality of apparatuses in the embodiments of the present disclosure are used for illustrative purposes only and are not intended to limit the scope of the messages or information.

In multi-core or many-core chips, different cores on the chip are connected with each other via Fabric to transmit data, and each core includes a storage unit and a data transmission circuit. An embodiment of the present disclosure provides a data transmission circuit applied to the above multi-core or many-core chip.

As shown inFIG.3, a first optional embodiment of the present disclosure relates to a data transmission circuit TR. The data transmission circuit TR includes a receiving unit Rx (i.e., receiver), a controlling unit Ctrl (i.e., controller), a lookup table unit LUT (i.e., lookup table circuit) and a selecting unit Sx (i.e. selector). An input terminal of the receiving unit Rx is for connecting to an output terminal of a data exchange apparatus Fabric, and an output terminal of the receiving unit Rx is connected to an input terminal of the controlling unit Ctrl, an input terminal of the lookup table unit LUT and a first input terminal In1 of the selecting unit Sx respectively; and the output terminal of the receiving unit Rx is also connected to an input terminal of a storage unit Memory (i.e., storage) in a core Core. A control terminal of the controlling unit Ctrl is connected to a control terminal of the lookup table unit LUT and a control terminal of the selecting unit Sx respectively, and an output terminal of the lookup table unit LUT is connected to the first input terminal In1 of the selecting unit Sx.

Specifically, the receiving unit Rx is configured to receive an original data packet from the Fabric and send original data in the original data packet to the selecting unit Sx, send an original control bit C0 of a header of the original data packet to the controlling unit Ctrl, and send an original index Index of the header of the original data packet to the lookup table unit LUT. The controlling unit Ctrl is configured to determine whether the original data packet needs to be relayed based on the original control bit C0; if yes, the controlling unit sends a relay control signal; if not, the controlling unit sends a non-relay control signal. In response to that the original data packet needs to be relayed, that is, in response to receiving the relay control signal, the controlling unit Ctrl is configured to control the first input terminal In1 of the selecting unit Sx to be enabled; in this way, the selecting unit Sx is configured to send a new data packet to the Fabric via the first input terminal In1. The new data packet includes the original data and a new header acquired by the lookup table unit LUT based on the original index, and the new header includes a new control bit, a new index and a target address.

Referring toFIG.3andFIG.4, for example, the core Cineeds to send the original data packet to a plurality of cores, such as the core Cmand the core Cn, wherein the core Cmand the core Cnare both provided with the data transmission circuit as shown inFIG.3.

Specifically, the data transmission process between the core Ciand the core Cmis as follows.

The core Cifirstly sends the original data packet to the Fabric, and the receiving unit Rx in the core Cmreceives the original data packet from the Fabric and sends a control bit in the original data packet to the controlling unit Ctrl and sends an index in the original data packet to the lookup table unit LUT. The controlling unit Ctrl checks the control bit C0 of the header of the original data packet, and outputs a value C1 when determining that the original data packet needs to be relayed; the lookup table unit LUT looks up a corresponding new header from the lookup table based on the original index Index of the header of the original data packet, that is, a new header corresponding to a next destination core Cn, wherein the new header includes a new control bit (that is, whether data transmitted to the core Cnneeds to be further relayed), a new index (that is, an index of a next destination to which the data transmitted to the core Cnis further relayed) and a target address (the target address is the address of the core Cn). Then, the selecting unit Sx sends a new data packet composed of the new header and the original data to the Fabric via the first input terminal In1 of the selecting unit, and the Fabric sends the new data packet to the core Cn.

Further, the receiving unit Rx in the core Cnreceives the new data packet from the Fabric, the controlling unit Ctrl in the core Cnchecks the control bit in the header of the new data packet. When determining that the new data packet needs not to be relayed according to the control bit, the data in the new data packet is stored in a storage unit Memory of the core Cn, and the transmission of the new data packet is ended.

In the data transmission circuit of the embodiment, it is not required to firstly store the data packet in the storage unit in the core and then read the data packet out, thereby reducing the power consumption of the transmission circuit. In addition, the storage of each data packet in the storage unit Memory in the core and the relay transmission of each data packet are performed in parallel rather than firstly writing the data packet in and then reading the data packet out, thereby greatly reducing the time that the subsequent data receiver waits for the data. In addition, parameters required in the entire data transmission process are contained in the header of the sent data packet and analyzed by the local circuit, so that the micro-controlling unit is not occupied.

It should be noted that each unit structure of the data transmission circuit in the embodiment may be implemented in the form of a hardware circuit. For example, the receiving unit Rx may be of a receiver structure, the controlling unit Ctrl may be of a comparator structure that determines whether the data packet needs to be relayed according to the control bit, and the selecting unit Sx may be a selector that determines whether to output the corresponding data packet to the Fabric according to the control bit. Certainly, in addition to the above form of hardware, each unit structure of the transmission circuit in the embodiment may also be implemented in the form of software, as long as functions corresponding to each unit can be implemented.

The data transmission circuit TR according to a second optional embodiment of the present disclosure may further include a splicing unit Merge (i.e. splicer), as shown inFIG.5.

An input terminal of the splicing unit Merge is connected to the output terminal of the lookup table unit LUT and the output terminal of the receiving unit Rx respectively, an output terminal of the splicing unit Merge is connected to the first input terminal In1 of the selecting unit Sx, and a control terminal of the splicing unit Merge is connected to the control terminal of the controlling unit Ctrl. The splicing unit Merge is configured to form a new data packet by packing the original data and the new header acquired by the lookup table unit LUT from the lookup table based on the original index, and send the new data packet to the selecting unit Sx.

It may be understood that, since the splicing unit Merge is added, the output terminal of the receiving unit Rx is connected to the first input terminal In1 of the selecting unit Sx via the splicing unit Merge; the output terminal of the lookup table unit LUT is connected to the first input terminal In1 of the selecting unit Sx via the splicing unit Merge.

It should be noted that a specific structure of the splicing unit Merge is not limited herein. For example, the splicing unit Merge may be a simple splicing circuit that splices pure data and the new header acquired from the lookup table unit LUT together.

It may be understood that the following relevant descriptions of the second optional embodiment are also applicable to the foregoing first optional embodiment without the splicing unit Merge, except that a position where the original data and the new header are packed is changed. In the first optional embodiment, packing and splicing are performed in the selecting unit Sx; and in the second optional embodiment, packing and splicing are performed in the splicing unit Merge. Those skilled in the art may understand that other descriptions are applicable to both optional embodiments.

As shown inFIG.5, the selecting unit Sx further includes a second input terminal In0. The second input terminal In0 is connected to the output terminal of the storage unit Memory, reads from the storage unit Memory data in the core, i.e., a second data packet stored in the core, and sends the second data packet to the Fabric. The data in the core may be a packed data packet. At this time, in response to that the original data packet needs not to be relayed, the controlling unit Ctrl is further configured to control the second input terminal In0 of the selecting unit Sx to be enabled; in this way, the selecting unit Sx may directly send the second data packet to the Fabric.

Optionally, the controlling unit Ctrl may only connect the second input terminal and the storage unit when the second input terminal In0 of the selecting unit Sx is enabled. However, the selecting unit may choose not to output, and of course, it may also send signals such as an ending relay transmission signal.

Further, when the core in which the data transmission circuit is located is used as the source core (i.e., the data sending core), the controlling unit sends a control signal to the control terminal of the selecting unit, and controls the second input terminal of the selecting unit to be enabled; and further, the data stored in the storage unit is sent to the Fabric via the second input terminal of the selecting unit, and is sent to the target core by the Fabric.

It should be noted that a specific implementation structure in which the first input terminal In1 and the second input terminal In0 of the selecting unit Sx are connected to the output terminal of the splicing unit Merge and the output terminal of the storage unit Memory is not limited herein. Those skilled in the art may design a circuit structure satisfying such connection manner according to actual requirements.

As shown inFIG.3andFIG.5, the selecting unit Sx includes a selecting sub-unit S (i.e., selecting sub-circuit) and a sending sub-unit Tx (i.e., sending sub-circuit); an input terminal of the sending sub-unit Tx is connected to an output terminal of the selecting sub-unit S; and an output terminal of the sending sub-unit Tx is connected to the Fabric. In this way, the sending sub-unit Tx may send the data packet output by the selecting sub-unit S to the Fabric.

Specifically, as shown inFIG.6, the selecting sub-unit S includes a first selection transistor T1 and a second selection transistor T2. A control electrode of the first selection transistor T1 is connected to the control terminal of the controlling unit Ctrl, a first electrode of the first selection transistor T1 is connected to the output terminal of the splicing unit Merge, and a second electrode of the first selection transistor T1 is connected to the input terminal of the sending sub-unit Tx. A control electrode of the second selection transistor T2 is connected to the control terminal of the controlling unit Ctrl, a first electrode of the second selection transistor T2 is connected to the output terminal of the storage unit Memory, and a second electrode of the second selection transistor T2 is connected to the input terminal of the sending sub-unit Tx. Further, one of the first selection transistor T1 and the second selection transistor T2 is an N-type transistor, and the other is a P-type transistor.

It should be noted that, for the first selection transistor T1 and the second selection transistor T2, the control electrodes are gate electrodes, the first electrodes may be source electrodes, and the second electrodes may be drain electrodes; or the first electrodes may be drain electrodes, and the second electrodes may be source electrodes. In addition, when the first selection transistor T1 is the N-type transistor (which is turned on when the control electrode thereof receives a high-level signal), the second selection transistor is the P-type transistor (which is turned on when the control electrode thereof receives a low-level signal), and vice versa.

As shown inFIG.7, the sending sub-unit Tx includes a controlling sub-unit Tx_1 (i.e., sub-controller) and a level setting sub-unit Tx_2 (i.e., level setting sub-circuit) connected to the controlling sub-unit Tx_1. The level setting sub-unit Tx_2 is configured to set sending levels of the new data packet and the data packet in the core (i.e., the second data packet). The controlling sub-unit Tx_1 is configured to send the new data packet and the data packet in the core according to the sending levels.

It should be noted that a specific rule for the sending level is not limited. For example, the new data packet may be processed with priority; or sending priority may be equally distributed, that is, the new data packet and the second data packet are sent alternately. The specific rule for the sending level may be determined according to actual requirements.

In the data transmission circuit of the embodiment, level setting is performed on the data sent by the sending sub-unit Tx to effectively ensure that important data is transmitted with priority, thereby effectively ensuring the data transmission efficiency.

As shown inFIG.8, the lookup table unit LUT includes a lookup sub-unit LUT_1 (i.e., lookup sub-circuit) and a storage sub-unit LUT_2 (i.e., sub-storage) connected to the lookup sub-unit LUT_1. The storage sub-unit LUT_2 is configured to pre-store a lookup table. The lookup table includes a plurality of items, and each item corresponds to a unique original index and includes a new header. The lookup sub-unit LUT_1 is configured to lookup an item that corresponds to the original index from the lookup table as a new header based on the original index.

Specifically, for example, the storage sub-unit LUT_2 stores a plurality of items, and each item is a complete header, as shown in the following table.

Index is an index that uniquely corresponds to an item in the LUT. The item to which the Index points is a new header NewHeader of the new data packet that will be spliced with the original data in the splicing unit Merge and sent out.

The content of the item in the LUT is also the content of the new header NewHeader as follows:

C0IndexAddr_dest

In the above table, C0 is a new control bit that determines whether the new data packet needs to be further relayed, Index is an index of the LUT, and Addr_dest is a destination address of the new data packet, which may be a target core address, or a target core address and a target storage address.

Preferably, to effectively save the power consumption of the transmission circuit, when receiving a non-relay signal, that is, in response to that the original data packet needs not to be relayed, the lookup table unit LUT and the splicing unit Merge are shut off. That is, a table lookup function and a merging and packing function are stopped. The shut-off of the lookup table unit LUT and the splicing unit Merge effectively saves the power consumption.

As shown inFIG.5andFIG.9, the controlling unit Ctrl includes a determining sub-unit Ctrl_1 (i.e., determining sub-circuit) and a transmitting sub-unit Ctrl_2 (i.e., transmitting sub-circuit). The determining sub-unit Ctrl_1 is configured to determine whether the original data packet needs to be relayed according to a value of the original control bit; if yes, an output value C1 of the determining sub-unit Ctrl_1 is set to a first value, for example, 1; if not, the output value C1 of the determining sub-unit Ctrl_1 is set to a second value different from the first value, for example, 0. The transmitting sub-unit Ctrl_2 is configured to transmit the output value C1 of the determining sub-unit Ctrl_1 to the lookup table unit LUT and the splicing unit Merge respectively.

As shown inFIG.10, the data transmission circuit TR further includes a changing unit Gx (i.e., changing circuit) connected to the receiving unit Rx. The receiving unit Rx is further configured to receive a change request carrying a new control bit and a new index. The changing unit Gx is configured to change the header of the original data packet received by the receiving unit based on the change request. For example, a local MCU or host may perform change according to different tasks, so as to transmit data in different task states.

As shown inFIG.3andFIG.5, a third optional embodiment of the present disclosure provides a processing core Core including a storage unit Memory and a data transmission circuit. The data transmission circuit is the foregoing data transmission circuit TR with a specific structure for which reference may be made to the above relevant descriptions, which will not be repeated herein. The output terminal of the receiving unit Rx is connected to the input terminal of the storage unit Memory, and the second input terminal In0 of the selecting unit Sx is connected to the output terminal of the storage unit Memory.

The processing core of the embodiment has the foregoing data transmission circuit, and it is not required to firstly store the data packet in the storage unit in the core and then read the data packet out, thereby reducing the power consumption of the transmission circuit. In addition, the storage of each data packet in the storage unit Memory in the core and the relay transmission of each data packet are performed in parallel rather than firstly writing the data packet in and then reading the data packet out, thereby greatly reducing the time that the subsequent data receiver waits for the data. In addition, parameters required in the entire data transmission process are contained in the header of the sent data packet and analyzed by the local circuit, so that the micro-controlling unit is not occupied.

A fourth optional embodiment of the present disclosure provides a chip with a multi-core structure. The chip with the multi-core structure includes a plurality of cores and Fabric connecting the processing cores with each other. At least one processing core includes the foregoing data transmission circuit with the specific structure for which reference may be made to the above relevant descriptions, which will not be repeated herein; or, at least one processing core is the foregoing processing core.

The chip with the multi-core structure of the embodiment has the foregoing data transmission circuit or processing core, and it is not required to firstly store the data packet in the storage unit in the core and then read the data packet out, thereby reducing the power consumption of the transmission circuit. In addition, the storage of each data packet in the storage unit Memory in the core and the relay transmission of each data packet are performed in parallel rather than firstly writing the data packet in and then reading the data packet out, thereby greatly reducing the time that the subsequent data receiver waits for the data. In addition, parameters required in the entire data transmission process are contained in the header of the sent data packet and analyzed by the local circuit, so that the micro-controlling unit is not occupied.

As shown inFIG.11, a fifth optional embodiment of the present disclosure provides a data transmission method S100. The data transmission method S100may adopt the structure of the foregoing data transmission circuit, for which reference may be specifically made to the above relevant descriptions that will not be repeated herein. Specifically, the data transmission method S100may include the following steps.

In S110, an original data packet in Fabric is received, wherein a header of the original data packet carries an original control bit and an original index.

In S120, whether the original data packet needs to be relayed is determined based on the original control bit.

In S130, in response to that the original data packet needs to be relayed, a new data packet is sent to the Fabric, wherein the new data packet includes original data and a new header acquired based on the original index.

In the data transmission method of the embodiment, it is not required to firstly store the data packet in the storage unit in the core and then read the data packet out, thereby reducing the power consumption of the transmission circuit. In addition, the storage of each data packet in the storage unit Memory in the core and the relay transmission of each data packet are performed in parallel rather than firstly writing the data packet in and then reading the data packet out, thereby greatly reducing the time that the subsequent data receiver waits for the data. In addition, parameters required in the entire data transmission process are contained in the header of the sent data packet and analyzed by the local circuit, so that the micro-controlling unit is not occupied.

Specifically, the step of sending the new data packet to the Fabric includes:acquiring a new header from a preset lookup table based on the original index, forming a new data packet by packing the new header and the original data, and then sending the new data packet to the Fabric.

Specifically, as shown inFIG.11, the data transmission method S100further includes the following step.

In S140, in response to that the original data packet needs not to be relayed, local data as a second data packet is sent to the Fabric.

To transmit the data efficiently, the data transmission method further includes the following step.

After sending levels of the new packet and the second data packet are set, the new packet and the second data packet are sent according to the sending levels. For example, the sending levels are set so that the sending level of the new data packet is higher than the sending level of the second data packet, or the new packet and the second data packet are sent alternately.

To reduce the power consumption, the data transmission method S100further includes:in response to that the original data packet needs not to be relayed, stopping table lookup and/or splicing.

Optionally, step S120specifically includes:determining whether the original data packet needs to be relayed according to a value of the original control bit; if yes, setting an output value to 1; if not, setting the output value to 0.

Optionally, the data transmission method further includes:receiving a change request carrying a new control bit and a new index; andchanging the received header of the original data packet based on the change request.

A sixth optional embodiment of the present disclosure provides an electronic device, including:one or more processors; anda storage unit configured to store one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the foregoing data transmission method.

The electronic device of the embodiment stores the program in the storage unit thereof, and the program, when executed by the processor, causes the processor to implement the foregoing data transmission method. It is not required to firstly store the data packet in the storage unit in the core and then read the data packet out, thereby reducing the power consumption of the transmission circuit. In addition, the storage of each data packet in the storage unit Memory in the core and the relay transmission of each data packet are performed in parallel rather than firstly writing the data packet in and then reading the data packet out, thereby greatly reducing the time that the subsequent data receiver waits for the data. In addition, parameters required in the entire data transmission process are contained in the header of the sent data packet and analyzed by the local circuit, so that the micro-controlling unit is not occupied.

A seventh optional embodiment of the present disclosure provides a computer-readable storage medium storing a computer program. The computer program, when executed by a processor, causes the processor to implement the foregoing data transmission method, for which reference may be specifically made to the above relevant descriptions.

The computer-readable storage medium may be included in an apparatus, device and system of the present disclosure, or may be provided independently.

The computer-readable storage medium may be any tangible medium that contains or stores a program, and may be an electronic, magnetic, optical, electromagnetic, infrared or semi-conductor system, apparatus or device. More specific examples of the computer-readable storage medium include but not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, an optical fiber, a random-access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The computer-readable storage medium may further include a data signal with a computer-readable program code embodied therein propagated in a baseband or as part of a carrier wave. Specific examples of the propagated data signal include but not limited to, electromagnetic signals, optical signals or any suitable combination of the foregoing.

It may be understood that the above embodiments are merely illustrative embodiments used for describing principles of the present disclosure but not intended to limit the present disclosure. Those of ordinary skill in the art may make various modifications and improvements without departing from the spirit and essence of the present disclosure, and these modifications and improvements shall also be encompassed in the scope of protection of the present disclosure.