Patent ID: 12261099

The figures herein depict various embodiments of the invention for purposes of illustration only. It will be appreciated that additional or alternative structures, assemblies, systems, and methods may be implemented within the principles set out by the present disclosure.

DETAILED DESCRIPTION

Embodiments herein provide for integrated cooling assemblies embedded within a device package. The embedded cooling assemblies shorten the thermal resistance path between a device and a heat sink and reduce thermal communication between devices disposed in the same package.

As used herein, the term “substrate” means and includes any workpiece, wafer, or article that provides a base material or supporting surface from which or upon which components, elements, devices, assemblies, modules, systems, or features of the heat-generating devices, packaging components, and cooling assembly components described herein may be formed. The term substrate also includes “semiconductor substrates” that provide a supporting material upon which elements of a semiconductor device are fabricated or attached, and any material layers, features, and/or electronic devices formed thereon, therein, or therethrough.

As described below, the semiconductor substrates herein generally have a “device side,” e.g., the side on which semiconductor device elements are fabricated, such as transistors, resistors, and capacitors, and a “backside” that is opposite the device side. The term “active side” should be understood to include a surface of the device side of the substrate and may include the device side surface of the semiconductor substrate and/or a surface of any material layer, device element, or feature formed thereon or extending outwardly therefrom, and/or any openings formed therein. Thus, it should be understood that the material(s) that form the active side may change depending on the stage of device fabrication and assembly. Similarly, the term “non-active side” (opposite the active side) includes the non-active side of the substrate at any stage of device fabrication, including the surfaces of any material layer, any feature formed thereon, or extending outwardly therefrom, and/or any openings formed therein. Thus, the terms “active side” or “non-active side” may include the respective surfaces of the semiconductor substrate at the beginning of device fabrication and any surfaces formed during material removal, e.g., after substrate thinning operations. Depending on the stage of device fabrication or assembly, the terms “active” and “non-active sides” are also used to describe surfaces of material layers or features formed on, in, or through the semiconductor substrate, whether or not the material layers or features are ultimately present in the fabricated or assembled device.

Spatially relative terms are used herein to describe the relationships between elements, such as the relationships between substrates, heat-generating devices, cooling assembly components, device packaging components, and other features described below. Unless the relationship is otherwise defined, terms such as “above,” “over,” “upper,” “upwardly,” “outwardly,” “on,” “below,” “under,” “beneath,” “lower,” and the like are generally made with reference to the X, Y, and Z directions set forth in the drawings. Thus, it should be understood that the spatially relative terms used herein are intended to encompass different orientations of the substrate and, unless otherwise noted, are not limited by the direction of gravity. Unless the relationship is otherwise defined, terms describing the relationships between elements such as “disposed on,” “embedded in,” “coupled to,” “connected by,” “attached to,” “bonded to,” either alone or in combination with a spatially relevant term include both relationships with intervening elements and direct relationships where there are no intervening elements.

Unless otherwise noted, the term “cold plate” generally refers to a base plate, or a stack of base plates directly bonded to one another, which may be bonded to the semiconductor device. The cold plate may include material layers and/or metal features formed on or in a surface of the base plate or stack of base plates that facilitate direct dielectric or hybrid bonding with the semiconductor device. The direct bonding methods enable heat from the semiconductor device to be transferred through the cold plate to a fluid flowed thereover without the use of a thermal interface material. Unless otherwise noted, the device packages and cold plates described herein may be used with any desired fluid coolant, e.g., liquid, gas, and/or vapor-phase coolants. Thus, the terms should not be construed as limiting the coolant to any one fluid phase.

FIG.1is a schematic plan view of an example of a system panel100, in accordance with embodiments of the disclosure. Generally, the system panel100includes a printed circuit board, here PCB102, a plurality of device packages301mounted to the PCB102, and a plurality of coolant lines108fluidly coupling each of the device packages301and to a coolant source110. It is contemplated that coolant may be delivered to each of the device packages301in any desired fluid phase, e.g., liquid, vapor, gas, or combinations thereof and may flow out from the device package301in the same phase or a different phase. In some embodiments the coolant is delivered to the device package301and returned therefrom as a liquid and the coolant source110may comprise a heat exchanger or chiller to maintain the coolant at a desired temperature. In other embodiments, the coolant may be delivered to the device packages301as a liquid, vaporized to a liquid within the device package, and returned to the coolant source110as a vapor. In those embodiments, the device packages301may be fluidly coupled to the coolant source110in parallel and the coolant source110may include or further include a compressor (not shown) for condensing the received vapor to a liquid form.

FIG.2is a schematic partial sectional side view of a portion of the system panel100ofFIG.1. As shown, each device package301is disposed in a socket114of the PCB102and connected thereto using a plurality of pins116, or by other suitable connection methods, such as solder bumps (not shown). The device package301may be seated in the socket114and secured to the PCB102using a mounting frame106and a plurality of fasteners112, e.g., compression screws, collectively configured to exert a relatively uniform downward force on the upward facing edges of the device package301. The uniform downward force ensures proper pin contact between the device package301and the socket114.

As shown, each device package301is disposed in a socket114of the PCB102and connected thereto using a plurality of pins116, or by other suitable connection methods, such as solder bumps (not shown). The device package301may be seated in the socket114and secured to the PCB102using a mounting frame106and a plurality of fasteners112, e.g., compression screws, collectively configured to exert a relatively uniform downward force on the upward facing edges of the device package301. The uniform downward force ensures proper pin contact between the device package301and the socket114.

FIG.3Ais a schematic exploded isometric view of the device package301.FIG.3Bis a schematic sectional view of the device package301taken along line A-A′. Generally, the device package301includes a package substrate302, an integrated cooling assembly303, and a package cover308. The device package301further includes an adhesive layer322that attaches the integrated cooling assembly303to the package cover308to define a coolant channel310therebetween.

Typically, the package substrate302is formed of a rigid material, such as an epoxy or resin-based laminate, that supports the integrated cooling assembly and the package cover308. The package substrate302typically includes conductive features that electrically couple the integrated cooling assembly303to the PCB102. The integrated cooling assembly303may include a semiconductor device, here device304, disposed on the package substrate302and a cold plate306bonded to the device304. Here, the device304has an active side318that includes device components, e.g., transistors, resistors, and capacitors, formed thereon or therein, and a non-active backside320opposite the active side318. As shown, the active side318is positioned adjacent to and facing towards the package substrate302. The active side318may be electrically connected to the package substrate302by use of conductive bumps319, which are encapsulated by an first underfill layer321disposed between the device304and the package substrate302. The first underfill layer321may comprise a cured polymer resin or epoxy, which provides mechanical support to the conductive bumps319and protects against thermal fatigue.

Here, the cold plate306is attached to the device backside320without the use of an intervening adhesive material, e.g., directly bonded to the device backside320, such that the cold plate306and the device backside320are in direct thermal contact. In some embodiments, the cold plate306is attached to the device backside320using a direct dielectric bonding process. In other embodiments, the cold plate306is attached to the device backside320using a hybrid of direct dielectric bonds, and direct metal bonds formed therebetween. For example, in some embodiments, one or both of the device backside320and the device-facing side of the cold plate306comprise a dielectric material layer, e.g., a first dielectric material layer334A and a second dielectric material layer334B respectively, and the cold plate306is directly bonded to the device backside320through bonds formed between the dielectric material layers334A-B. In some embodiments, the cold plate306is directly bonded to the device backside320using a hybrid bonding technique, where bonds are formed between the dielectric material layers334A-B and between metal features, such as between first metal pads336A and second metal pads336B, disposed in the dielectric material layers334A-B.

Suitable dielectrics that may be used as the dielectric material layers334A-B include silicon oxides, silicon nitrides, silicon oxynitrides, silicon carbon nitrides, metal-oxides, metal-nitrides, silicon carbide, silicon oxycarbides, silicon oxycarbonitride, silicon carbonitride, diamond-like carbon (DLC), or combinations thereof. In some embodiments, one or both of the dielectric material layers334A-B formed of an inorganic dielectric material, i.e., a dielectric material substantially free of organic polymers. Typically, one or both of the layers334A-B are deposited to a thickness greater than the thickness of a native oxide, such as about 1 nm or more, 5 nm or more, 10 nm or more, 50 nm or more, 100 nm or more, or 200 nm or more. In some embodiments, the one or both of the layers334A-B are deposited to a thickness of 301 nm or less, such as 200 nm or less, 100 nm or less, or 50 nm or less.

Beneficially, direct bonding of the dielectric and (optionally) metal surfaces eliminates the need for an intervening adhesive layer or thermal interface material (TIM) layer between the device304and the cold plate306. Thus, the device package301provides for a reduced thermal resistance the heat transfer path326when compared to the heat transfer path of a conventional device package, e.g., by50X or more. Methods for forming direct dielectric and hybrid bonds are described below.

As shown, the upwardly facing surfaces of the cold plate306form a cavity comprising a base surface309that forms a bottom of the coolant channel310and sidewalls311that surround the base surface309and protrude upwardly therefrom. The upward-facing surfaces of the sidewalls311form a peripheral surface313that supports the adhesive layer322. Generally, when the device package301is assembled, the coolant channel310comprises the space between the base surface309and the package cover308. The adhesive layer322attaches the peripheral surface313to the package cover308and forms an impermeable barrier that prevents coolant delivered to the coolant channel310from reaching the active side318of the device304and causing damage thereto. Here, the adhesive layer322that absorbs the differences in linear expansion between different materials, thus the adhesive layer322may be considered a decoupling adhesive material that allows for differences in CTE's between the package cover308and the cold plate306. In some embodiments, the adhesive layer322comprises a decoupling membrane disposed between and adhered to each the cold plate306and the package cover308.

In some embodiments, the cold plate306includes a plurality of protruding features324, such as fins, columns, or pillars that extend upwardly from the base surface309. The protruding features324provide increased surface area and disrupt laminar fluid flow at the interface of the coolant and the cold plate306resulting in increased heat transfer therebetween. To further increase heat dissipation from the device, the protruding features324may comprise and/or be formed of a thermally conductive metal, such as copper. Typically, the protruding features324are arranged in a repeating pattern. In some embodiments, the protruding features324may be arranged in a randomized pattern.

In some embodiments, the cold plate306is formed of a material having a coefficient of thermal expansion (CTE) substantially similar to the CTE of the bulk semiconductor substrate of device304. For example, in some embodiments, the device304may be formed on a monocrystalline silicon substrate, and the cold plate306may be formed from a monocrystalline silicon or polycrystalline silicon substrate. Forming the cold plate306from CTE matched materials (with respect to the bulk substrate material of the device304) prevents undesired separation of the device304and cold plate306across repeated thermal cycles.

In some embodiments, the cold plate306may be formed from non-crystalline silicon materials, such as a bulk substrate material comprising metal, metal alloys, ceramics, composite materials or other low CTE materials suitable for the bonding using the methods described below. For example, the cold plate306may be formed from a bulk material selected from the group comprising copper, aluminum, copper alloys (e.g., copper molybdenum alloys and copper tungsten alloys), iron-cobalt nickel alloys (e.g., Kovar® from Magellan Industrial Trading Co., Inc. of South Norwalk Connecticut USA), iron-cobalt nickel silver alloys, iron-nickel alloys (e.g., Invar® superalloys from Magellan), iron-nickel silicon alloys, aluminum silicon carbides, aluminum-silicon alloys, beryllium, beryllium oxides, beryllium, and beryllium oxide composites, aluminum-graphite fibers, copper-graphite fibers, metal diamond composite materials (e.g., aluminum diamond composites and silver-diamond composites), metal oxides, metal nitrides, and combinations thereof. The non-silicon substrate materials may be prepared for bonding as described below and may or may not include a dielectric material layer deposited on the device facing side to form a bonding surface.

The package cover308generally comprises one or more vertical or sloped sidewall portions308A and a lateral portion308B that spans and connects the sidewall portions308A. The sidewall portions308A extend upwardly from a peripheral surface of the package substrate302to surround the device304and the cold plate306disposed thereon. The lateral portion308B is disposed over the cold plate306and is typically spaced apart from the cold plate306by a gap corresponding to the thickness of the adhesive layer322. Coolant is circulated through the coolant channel310through the inlet/outlet openings312formed through the lateral portion308B. Cooling lines may be attached to the device package301by use of threads formed in the sidewalls of the inlet/outlet openings312and/or connector features that surround the openings312and extend upwardly from a surface of the lateral portion308B.

Typically, the package cover308is formed of semi-rigid or rigid material so that at least a portion of the downward force exerted on the package cover308by the mounting frame106(FIG.2) is transferred to the supporting surface of the package substrate302and not transferred to the cold plate306and the device304therebelow. In some embodiments, the package cover308is formed of a thermally conductive metal, such as aluminum or copper. In some embodiments, the package cover308functions as a heat spreader that redistributes heat from one or more electronic components within a multi-component device package, such as described below.

As noted above, the adhesive layer322thermally couples the cold plate306to the package cover308and defines a coolant channel310in combination therewith. As shown, the adhesive layer322is disposed between the peripheral surface313of the cold plate306the lateral portion308B of the package cover308. Here, the cold plate306forms the lower or base surfaces of the coolant channel310and at least a portion of the coolant channel sidewalls, the package cover308forms the upper surfaces of the coolant channel310, and the adhesive layer322forms a seal between the package cover308and the peripheral surface313of the cold plate306. In other embodiments, the adhesive layer322may be disposed between the sidewalls311of the cold plate306and the sidewall portions308A of the package cover308. Generally, when the device package301is assembled, the adhesive layer322forms an impermeable barrier that prevents coolant delivered to the coolant channel310from reaching the active side318of the device304and causing damage thereto.

In some embodiments, the device package301further includes a second underfill layer338(shown inFIG.3B) disposed in gaps regions outside of the coolant channel310, such as between the package cover308, the adhesive layer322, and the package substrate302. For example, the second underfill layer338may include a polymer or epoxy material that extends upwardly from the package substrate302to encapsulate and/or surround the device304and, in some embodiments, at least portion of the cold plate306. When used, the second underfill layer338may provide mechanical support that improves system reliability and extends the useful lifetime of the device package301. For example, the second underfill layer338may reduce mechanical stresses that can weaken interfacial bonds and/or electrical connections between the components of the device package301, such as stresses caused by vibrations, mechanical and thermal shocks, and/or fatigue caused by repeated thermal cycles. In some embodiments, the second underfill layer338may be a thermally conductive material, such as a polymer or epoxy having one or more thermally conductive additives, such as silver and/or graphite.

FIG.4Ais a schematic isometric view of an integrated cooling assembly403that provides increased thermal dissipation from a high heat flux region, i.e., a hotspot region408relative to the thermal dissipation from adjacent regions of the device304.FIG.4Bis a schematic side sectional view of the integrated cooling assembly403(taken along line B-B′ ofFIG.4A) that shows an embedded thermoelectric cooler, here a TEC404, disposed over the device hotspot408.FIG.4Cis a close up view of the TEC404. Typically, the integrated cooling assembly403includes one or more TECs404, each disposed in a corresponding cavity formed in the cold plate406. Generally, each TEC404includes alternating n-type semiconductor pillars410and p-type semiconductor pillars412that are electrically connected in a series by a plurality of conductive plates414. Each TEC404is coupled to a DC power supply416and as current flows therethrough heat is moved from a first side of the TEC404disposed adjacent to the hotspot region408to a second side of the TEC404adjacent to the cold plate406. Each TEC404may be secured to one or both of the device304and the cold plate406using a direct bonding method described below.

Here, power is delivered to the TEC404using metal interconnects and/or vias formed in, on, or through the device304, such as the through-substrate vias (TSVs)418shown. In some embodiments, power may be delivered to the TECs404using conductive features formed in or between the interfacing surfaces of the device304and the cold plate406. In some embodiments, power may be delivered to the TECs404through conductive features, e.g., metal interconnects and vias formed in and/or through the cold plate406.

In some embodiments, the number of protruding features (count), density, size, and/or shape of the protruding features324extending upwardly from the base surface309in regions disposed above a TECs404is different from the surrounding regions of the base surface309. For example, as shown inFIGS.4A-4B, the surface region409disposed above the TEC404has fewer or no protrusions when compared to adjacent regions of the base surface309, which provides for increase volumetric flowrates of coolant over the region409, resulting in turn, in increased relative heat transfer therefrom.

FIG.5is a schematic side sectional view of an example of a multi-component device package501that includes a cold plate506directly bonded to the backside surfaces of two or more devices. As shown, the device package501includes a package substrate502, e.g., an interposer that facilitates communication between the device304and the device stack604, an integrated cooling assembly503, a package cover308, and an adhesive layer322. The integrated cooling assembly503may include a plurality of devices which may be singulated, e.g., device304and/or disposed in a vertical device stack504, and a cold plate306bonded to each of the devices304and device stacks504. In some embodiments the device304may comprise a processor and the device stack504may comprise a plurality of memory devices. As shown, the device304and the device stack504are disposed in a side-by-side arrangement on the package substrate302and are electrically connected thereto using a suitable method. The cold plate506is disposed over and is directly bonded to the backside of the device304and a backside of the uppermost device of the stack504. Here, the cold plate506is sized to provide a bonding surface for attachment to both the device304and the device stack504but may otherwise be the same or substantially similar to other cold plates described herein. For example, the cold plate506may include any one or combination of the features of the cold plates described in relation to the other figures herein. In some embodiments, the integrated cooling assembly503may include one or more TECs404(FIG.4B) embedded between the cold plate506and the first device904A and/or between the cold plate506and the device stack504.

FIG.6is a schematic side sectional view of an example of a multi-component device package601that includes the integrated cooling assembly303and a device stack604, where heat is transferred from the device stack604to the integrated cooling assembly303via the package cover608. Here, the device package601includes a package substrate502, the integrated cooling assembly303, one or more second devices (shown here as the device stack604), and the package cover608. Typically, the integrated cooling assembly303is coupled to the package cover608by use of an adhesive layer322to define a coolant channel310disposed therebetween. The device stack604may be disposed on the package substrate502in a side-by-side arrangement with the device304. As described above, heat generated by the device304is dissipated to a coolant that is circulated through a coolant channel, here coolant channel310via inlet/outlet openings312formed through the package cover608. The package cover608may be formed of a thermally conductive material and function as a thermal spreader. Heat generated by the device stack604is dissipated to the coolant via the package cover608which is thermally coupled to the device stack604by use of a TIM layer616. Beneficially, the cold plate306blocks a thermal pathway between the device304and the device stack604to prevent heat from transferring therebetween. Thus, the device package601may be advantageously used to facilitate closely spaced devices on an interposer, such as high-power devices and memory stacks, to provide for reduced latency while simultaneously eliminating undesirable heat transfer therebetween.

In some embodiments, the device package601further includes a heat sink608A disposed on a portion of the package cover601above the device stack604. The heat sink608A may be thermally coupled to the package cover608by use of a TIM layer (not shown) or by direct bonding using the methods described herein. In some embodiments, the device package601includes one or more TECs404and/or a second underfill layer338, as shown above.

FIG.7Ais a schematic side section view of a device package701with additional adhesive between the package cover308and inner surfaces715of the cold plate706.FIG.7Bis a schematic isometric exploded view of the integrated cooling assembly703and the adhesive layer322. Generally, the device package701includes a package substrate302, an integrated cooling assembly703, and a package cover308. The integrated cooling assembly703includes a device304and a cold plate706directly bonded to the device304by use of the adhesive layer722which includes a first portion722A disposed on the peripheral surface313and a second portion722B disposed on inner surfaces715(surfaces of the cold plate706disposed inwardly from the peripheral surface313). Here, the first portion722A forms a hermetic seal between the cold plate706and the package cover308to define a perimeter of a coolant channel710disposed between the cold plate706and the package cover308. The second portion722B attaches the inner surfaces715to the corresponding portions of the package cover308disposed thereover. The inner surfaces715may be disposed on protrusions extending upwardly from the base surface309(as shown) or may comprise regions of the base surface309. The additional attachment locations provided by the second portion722B substantially reduce or prevent distortion of the package cover308due to the high pressure coolant circulated through the coolant channel710. Thus, the additional attachment locations allow for increased coolant flowrates that in turn provide for increased cooling efficiency. It is contemplated that the additional attachment locations provided by the second portion722B of can be used with any of the device packages described herein.

FIG.8Ais a schematic side section view of a device package801where portions of an integrated cooling assembly803protrude into a lower surface of a package cover808to provide added structural support.FIG.8Bis a schematic isometric exploded view of the integrated cooling assembly803. As shown, the integrated cooling assembly803includes a device304and a cold plate806directly bonded to the device304. The cold plate806includes a plurality of plates patterned and directly bonded to one another, shown here as a first plate812and a second plate814directly bonded to the first plate812. The first plate812may be substantially similar to, or comprise any combination of features of, the cold plates306,406,506described above. Here, the first plate812includes the base surface309, the protruding features329, the sidewalls311, and the peripheral surface313described above in relation to the cold plate306. The second plate814includes a plurality of sidewalls811aligned with and bonded to the sidewalls311of the first plate812. A blind opening formed in an inner surface of the package cover808and/or protrusions extending downwardly form the inner surface form a well-region that is sized and shaped to receive the upper portions of the sidewalls811. In some embodiments, the sidewalls811form a rectangular annulus (when viewed form the z-direction) and the well-region820has a corresponding rectangular annulus shape.

Here, the integrated cooling assembly803may be attached to the package cover808by an adhesive layer822disposed in the well-region820. The adhesive layer822surrounds an upper portion of the sidewalls811to form a hermetic seal between the cold plate806and the package cover808and define the perimeter of the coolant channel810. In some embodiments, the adhesive layer822is formed of a compliant material that, when compressed between the package cover808and the cold plate806forms an impermeable seal around a perimeter of the coolant channel810.

In some embodiments, the second plate814includes one or more inner supports815(one shown) that connect opposing sidewalls811A, and are spaced apart from each of the sidewalls811B. In those embodiments, a portion of the well-region820may be sized and shaped to receive upper portions of the inner supports815. When used, the inner supports815provide structural support to the second plate814and further secure the package cover808to the integrated cooling assembly803. The additional attachment points provided by the inner supports815substantially reduces or prevents distortion of the package cover808due to high pressure coolant circulated through the coolant channel810. Thus, the additional attachment points allow for increased coolant flowrates which provide for corresponding increased cooling efficiency. It is contemplated that the features of device package, such as the cold plate806and the package cover808described above, can be advantageously used in combination with the features of any other of the device packages described herein.

FIG.9is a schematic side section view of a device package901with one or more cold plates906positioned to cool portions of a 3DIC device904. Generally, the device package901includes an integrated cooling assembly903disposed on and electrically connected to the package substrate302, and a package cover908disposed over the integrated cooling assembly903. The integrated cooling assembly903includes the 3DIC device904, which includes a first device904A and one or more second devices904B (one shown), and the one or more cold plates906. Here, the first device904A is disposed facing towards the package substrate302, i.e., active-side down, and the second device904B is disposed on and bonded to a portion of a backside of the first device904A. The first device904A comprises a plurality of interconnects formed between the active side and the backside, e.g., through-substrate vias (TSVs918). In those embodiments, the first device904A and the second device904B may be interconnected using the TSVs918and hybrid bonds formed between the active side of the second device904B and the backside of the first device904A. In some embodiments, the one or more second devices or device stacks604are directly bonded to, and interconnected with, the first device904A using direct hybrid bonds.

Here, the first device904A is cooled using the one or more cold plates906(two shown) which are disposed on and bonded to the backside of the first device904A in a side-by-side arrangement with the second device904B. Each of the one or more cold plates906are attached to the package cover908using an adhesive layer822, where the adhesive material forms a hermetic seal between a peripheral surface of the cold plate906and the package cover908, respectively, to at least partially define a coolant channel therebetween. Heat generated by the first device904A is dissipated from the device package via coolant flowing through the coolant channels910disposed thereover. In some embodiments, the second device904B is thermally coupled to the package cover908by use of a TIM layer616. In those embodiments, the package cover908may function as a heat spreader so that heat generated by the second device904B is transferred to the coolant in the coolant channels910via a heat transfer path that includes the TIM layer616and the package cover908.

FIG.10Ais a schematic side sectional view of device package1001with a coolant channel1010disposed between a first HI device1004A and a second HI device1004B of an integrated cooling assembly1003.FIG.10Bis a schematic sectional view of the integrated cooling assembly1003taken along line C-C′ ofFIG.10A. Here, the device package1001A includes a package substrate302, the integrated cooling assembly1003disposed on the package substrate302, and (optionally) a package cover1008disposed over the integrated cooling assembly1003. The integrated cooling assembly1003forms a fluid chamber that includes a first heterogenous integration (HI) device1004A, a second HI device1004B, and a frame shaped cold plate, here a cold frame1006disposed between the first HI device1004A and the second HI device1004B.

Generally, the first HI device1004A and/or the second HI device1004B comprises a plurality of dissimilar integrated circuits that have been connected to one another via hybrid bonding to form the heterogeneous integration. For example, the first HI device1004A may include an interposer1005A and a plurality of semiconductor devices1007A (and/or device stacks) disposed in a side-by-side arrangement on the interposer1005A. Here, the semiconductor devices1007A are interconnected through the interposer1005A using hybrid bonds formed therebetween. The second device1004B is a 3DIC integration that includes a base die1005B and one or more second devices1007B, e.g., chiplets, bonded to the base die1005B, e.g., by hybrid bonds. In other embodiments, both devices are a 2.5DIC or a 3DIC integration or the relative positions of the first HI device1004A and the second HI device1004B may be exchanged. In some embodiments, the interposer1005A and/or base die1005B comprise a plurality of conductive features (not shown), e.g., bond pads, formed in the peripheral surfaces thereof.

The cold frame1006generally comprises a plurality of sidewalls that form a polygonal annulus shape, e.g., a rectangular annulus shape, when viewed from the Z-direction. In some embodiments, the cold frame1006may further include a plurality of vias1018(FIG.10B) disposed in the sidewalls and extending between opposite surfaces of the plate (in the Z-direction). The cold frame1006is aligned with and bonded to the peripheral surfaces of the interposer and/or die1005A-B, by use of hybrid bonding. As shown, the devices1004A-B and cold frame1006bonded therebetween collectively define a coolant channel1010, where the backside surfaces of the devices1007A-B are disposed in the coolant channel1010. Coolant fluid is circulated through the coolant channel1010via inlet/outlet openings1022formed through opposing sidewalls of the cold frame1006. In some embodiments, the device package1001A may include a package cover1008disposed over the integrated cooling assembly1003and an adhesive or molding material1038disposed between the package cover1008and the integrated cooling assembly. In those embodiments, the coolant fluid may be delivered to the channel1010via a flow pathway that includes inlet/outlet openings1012, openings in the molding material1038, and the openings1022formed through the plate sidewalls, each of which is in registration or fluid communication with one another.

In the device package1001A, the integrated cooling assembly1003is disposed on and electrically connected to the package substrate302, e.g., by conductive bumps319disposed between the package substrate and the interposer1005A. The second device1004B is in electrical communication with the package substrate through the vias1018and the hybrid bonds formed between the interposer1005A, the cold frame1006, and the base die1005B.

FIG.10Cis a schematic side sectional view of a device package1011with a coolant channel1010is disposed between a first HI device1004A and a second HI device1004B of an integrated cooling assembly1003, where the first HI device1004A is electrically connected to a first package substrate302A and the second device1004B is electrically connected to a second package substrate302B. In those embodiments, the device package1011may be disposed between and connected opposing PCB102A-B.

FIG.11shows a method1100that can be used to manufacture the device packages described herein.FIG.12uses the device package301at different stages of the manufacturing process to illustrate aspects of the method1100. At least some of the features of the device package301described below can be found with referenced toFIG.3. It is contemplated, however, that the method1100can be used to manufacture any of the device packages described herein. At block1102, the method1100includes aligning a first substrate1202with a second substrate1204, where the first substrate1202includes a plurality of to-be-singulated die, e.g., devices304, and the second substrate1204includes a plurality of to-be-singulated cold plates306. The cold plates306may be formed from one or more base plates924a-b(two shown), according to any one of the embodiments described above inFIGS.4-7. As shown, the first substrate1202includes a plurality of the devices304arranged in a rectangular array and spaced apart from one another by a plurality of scribe lines1206that extend in the X and Y directions to form a grid pattern.

The first substrate1202may include a bulk material and a plurality of material layers disposed on the bulk material. The bulk material may include any semiconductor material suitable for manufacturing semiconductor devices, such as silicon, silicon germanium, germanium, group III-V semiconductor materials, group II-VI semiconductor materials, or combinations thereof. For example, in some embodiments, the first substrate1202may include a monocrystalline wafer, such as a silicon wafer, a plurality of device components formed in or on the silicon wafer, and a plurality of interconnect layers formed over the plurality of device components. In other embodiments, the substrate may comprise a reconstituted substrate, e.g., a substrate formed from a plurality of singulated devices embedded in a support material.

The bulk material of the first substrate1202may be thinned after the devices304are formed using one or more backgrind, etching, and polishing operations that remove material from the backside. Thinning the first substrate1202may include using a combination of grinding and etching processes to reduce the thickness (in the Z-direction) to about 450 μm or less, such as about 301 μm or less, or about 150 μm or less. After thinning, the backside may be polished to a desired smoothness using a chemical mechanical polishing (CMP) process, and the dielectric material layer may be deposited thereon. In some embodiments, the dielectric material layer may be polished to a desired smoothness to prepare the substrate1202for the bonding process. In some embodiments, the method1100includes forming the plurality of metal features in the dielectric material layer in preparation for a hybrid bonding process, such as by use of a damascene process.

In some embodiments, the active side is temporarily bonded to a carrier substrate (not shown) before or after the thinning process. When used, the carrier substrate provides support for the thinning operation and/or for the thinned material to facilitate substrate handling during one or more of the subsequent manufacturing operations described herein. In some embodiments, the second substrate1204is formed of a plurality of substrates (not shown), each comprising a unitary bulk material patterned to define a plurality of plates, such as the first and second plates806A-B of the integrated cooling assembly803ofFIG.8B. Each of the plurality of substrates may have substantially the same size and shape as the first substrate1202when viewed from top-down (in the Z-direction) so that the interfacing surfaces are substantially coextensive with one another. In some embodiments, each of the substrates has a thickness (in the Z-direction) of between about 0.5 mm and about 10 mm, or between about 1 mm and about 8 mm, or between about 1 mm and 6 mm, such as about 0.5 mm or more, such as about 1 mm or more, or about 2 mm or more, or about 10 mm or less, such as about 8 mm or less, or about 6 mm or less.

In some embodiments, the second substrate1204is formed of a bulk material having a substantially similar coefficient of linear thermal expansion (CTE) to the bulk material of the first substrate1202, where the CTE is a fractional change in length of the material (in the X-Y plane) per degree of temperature change. In some embodiments, the CTEs of the first and second substrates are matched so that the CTE of the second substrate1204is within about +/−20% or less of the CTE of the first substrate1202, such as within +/−15% or less, within +/−10% or less, or within about +/−5% or less when measured across a desired temperature range. In some embodiments, the CTEs are matched across a temperature range from about −60° C. to about 200° ° C., or from about 60° ° C. to about 175° C. In one example embodiment, the matched CTE materials each include silicon. For example, the bulk material of the first substrate1202may include monocrystalline silicon, and the bulk material of the second substrate1204may include monocrystalline silicon or polycrystalline silicon. In some embodiments, the method1100includes forming a dielectric material layer and, optionally, a plurality of metal features on the lower surface of the second substrate1204.

At block1104, the method1100includes directly bonding the plurality of cold plates306formed in the second substrate1204to the plurality of devices304in the first substrate1202. As described above, the bonding surfaces may each comprise a dielectric material layer, and directly bonding the first and second substrates1202,1204includes forming dielectric bonds between the first dielectric material layer334A and the second dielectric material layer334B. Optionally, the first and second substrates1202,1204may be directly bonded using a hybrid of the dielectric bonds and metal bonds formed between the metal features.

Generally, directly bonding the surfaces (of the dielectric material layers) includes preparing, aligning, and contacting the surfaces. Preparing the surfaces may include smoothing the respective surfaces to a desired surface roughness, such as between 0.1 to 3.0 nm RMS, activating the surfaces to weaken or open chemical bonds in the dielectric material, and terminating the surfaces with a desired species. Smoothing the surfaces may include polishing the substrates1202,1204using a chemical mechanical polishing (CMP) process. Activating and terminating the surfaces with a desired species may include exposing the surfaces to radical species formed in a plasma.

In some embodiments, the plasma is formed using a nitrogen-containing gas, e.g., N2, and the terminating species includes nitrogen and hydrogen. In some embodiments, the surfaces may be activated using a wet cleaning process, e.g., by exposing the surfaces to an aqueous ammonia solution. In some embodiments, the dielectric bonds may be formed using a dielectric material layer deposited on only one of the substrates1202,1204but not on both. In those embodiments, the direct dielectric bonds may be formed by contacting the deposited dielectric material layer of one substrate directly with a bulk material surface of the other substrate, e.g., a bulk semiconductor or poly-silicon material surface. In such embodiments, the bulk material surface may comprise a thin layer of native oxide or may be cleaned prior to contact so that it is substantially free of native oxide.

Directly forming direct dielectric bonds between the substrates at block1104includes bringing the prepared and aligned surfaces into direct contact at a temperature less than 150° C., such as less than 100° C., for example, less than 30° C., or about room temperature, e.g., between 20° C. and 30° C. Without intending to be bound by theory, it is believed that the hydrogen terminating species diffuse from the interfacial bonding surfaces, and chemical bonds are formed between the remaining nitrogen species during the direct bonding process. In some embodiments, the direct bond is strengthened using an anneal process, where the substrates are heated to and maintained at a temperature of greater than about 30° C. and less than about 450° C., for example, greater than about 50° C. and less than about 250° C., or about 150° C. for a duration of about 5 minutes or more, such as about 15 minutes. Typically, the bonds will strengthen over time even without the application of heat. Thus in some embodiments, the method does not include heating the substrates.

In embodiments where the substrates are bonded using hybrid dielectric and metal bonds, the method may further include planarizing or recessing the metal features below the field surface before contacting and bonding the dielectric material layers. After the dielectric bonds are formed, the substrates1202,1204may be heated to a temperature of 150° C. or more and maintained at the elevated temperature for a duration of about 1 hour or more, such as between 8 and 24 hours, to form direct metallurgical bonds between the metal features. Suitable direct dielectric and hybrid bonding technologies that may be used to perform aspects of the methods described herein include ZiBond® and DBI®, each of which are commercially available from Adeia Holding Corp., San Jose, CA, USA.

At block1106, the method1100includes singulating the plurality of integrated cooling assemblies303from the bonded substrates. Singulation after bonding imparts distinctive structural characteristics on the integrated cooling assemblies303as the bonding surface of each cold plate306has the same perimeter as the backside of the device304bonded thereto. Thus, the sidewalls of the cold plate306are typically flush with the edges of the device304about their common perimeters. In some embodiments, the cold plates306are singulated from the second substrate1204using a process that cuts or divides the second substrate1204in a vertical plane, i.e., parallel to the Z-direction. In those embodiments, the sides of the cold plates306are substantially perpendicular to the backside of the device, i.e., a horizontal (X-Y) plane of an attachment interface between the device304and the cold plate306. In some embodiments, the cold plates306are singulated using a saw or laser dicing process.

At block1108, the method includes connecting the integrated cooling assembly to the package substrate302and attaching the package cover308to the integrated cooling assembly303with the adhesive layer322. In some embodiments, the method further includes at least partially encapsulating the integrated cooling assembly303with a second underfill layer338.

The methods described above advantageously provide for embedded cold plates that eliminate and/or substantially reduce the thermal resistance pathway typically associated with cooling systems attached to the exterior of a device package. The cold plates may be attached to a semiconductor device using a direct dielectric or hybrid dielectric and metal bonding method. Such bonding methods allow for relatively low thermal budgets while providing substantially increased bonding strengths when compared to conventional silicon-to-silicon bonding methods, such as thermocompression bonding methods.

The cold plate and the semiconductor device may be formed of CTE matched materials which eliminates the need for an intervening TIM layer. The cold plate and the package cover may be formed of CTE mismatched materials and attached to one another using a flexible adhesive material. The flexible adhesive material absorbs the difference in linear expansion between the package cover and the cold plate during repeated thermal cycles to extend the useful lifetime of the device package.

This specification discloses embodiments which include, but are not limited to, the following:

The embodiments discussed above are intended to be illustrative and not limiting. One skilled in the art would appreciate that individual aspects of the cooling assemblies, device packages, and methods discussed herein may be omitted, modified, combined, and/or rearranged without departing from the scope of the invention. Only the claims that follow are meant to set bounds as to what the present invention includes.