Patent ID: 12191255

DESCRIPTION OF EMBODIMENTS

In the following, embodiments of the present invention will be described with reference to the accompanying drawings.

In the following, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same components are referred to by the same reference characters, and a duplicate description thereof may be omitted.

First Embodiment

Structure of Interconnect Substrate

FIGS.1A and1Bare drawings illustrating an interconnect substrate according to a first embodiment.FIG.1Ais a partial plan view, andFIG.1Bis a partial cross-sectional view taken along the line A-A inFIG.1A.

Referring toFIGS.1A and1B, the interconnect substrate1includes a pad10, an insulating layer20, an interconnect layer30, an insulating layer40, and an interconnect layer50. The interconnect substrate1may be configured such that one or more additional insulating layers and interconnect layers are laminated.

In the present embodiment, for the sake of convenience, the insulating layer20side of the interconnect substrate1inFIG.1Bis referred to as an upper side or a first side, and the insulating layer40side is referred to as a lower side or a second side. In addition, the surface of a member on the upper side is referred to as an upper surface or a first surface, and the surface of the member on the lower side is referred to as a lower surface or a second surface. Nonetheless, the interconnect substrate1can be used upside-down or can be arranged at any angle. In addition, a plan view refers to a view of an object taken in a direction normal to an upper surface20aof the insulating layer20, and a plane shape refers to the shape of an object viewed in the direction normal to the upper surface20aof the insulating layer20.

The pad10is used for external connection. The pad10can be used for electrical connection to a mounting substrate (not shown) such as a motherboard, for example. The pad10has a laminated structure. For example, a metal layer13, which is the lowermost layer in contact with the insulating layer20, is a copper layer (Cu layer), and a metal layer12, which is the uppermost layer, is a gold layer (Au layer). The thickness of the metal layer13is, for example, approximately 10 to 30 μm.

The metal layer12may have a laminated structure in which the uppermost layer is an Au layer. The metal layer12may be, for example, a Ni/Au layer (i.e., a metal layer in which a Ni layer and an Au layer are stacked in this order on the metal layer13), a Ni/Pd/Au layer (i.e., a metal layer in which a Ni layer, a Pd layer, and an Au layer are stacked in this order on the metal layer13), or the like. When the metal layer12is a Ni/Pd/Au layer, for example, the thickness of the Ni layer is about 5 to 10 μm, and the thickness of the Pd layer is about 0.015 to 0.065 μm, with the thickness of the Au layer being about 0.030 to 0.090 μm.

The plane shape of the pad10is, for example, a circle having a diameter of about 600 μm to 800 μm. Alternatively, the planar shape of the pad10may be an elliptical shape, a rectangular shape, or any other shape.

The pad10is exposed on the upper surface20aside of the insulating layer20. As a material of the insulating layer20, for example, an insulating resin containing an epoxy-based resin as a main component can be used. The insulating layer20may contain a filler such as silica (SiO2). The thickness of the insulating layer20may be, for example, about 10 to 70 μm.

A portion of the lower surface of the pad10(i.e., a portion excluding a portion connected to the via interconnect) is covered with the insulating layer20. The upper surface10aof the pad10is situated at a position lower than the upper surface20aof the insulating layer20. The distance between the upper surface10aof the pad10and the upper surface20aof the insulating layer20is, for example, about 5 to 20 μm. The insulating layer20is provided with a groove20gthat is located around the pad10in a plan view and whose opening is on the upper surface20aside of the insulating layer20. When the plane shape of the pad10is circular, the groove20gmay be, for example, a ring shape such that the inner edge and outer edge thereof each have a circular shape with different diameters in a plan view. The width of the groove20gmay be, for example, about 80 μm to 100 μm.

The bottom surface of the groove20gis, for example, at a position deeper than the lower surface of the pad10(i.e., the lower surface of the metal layer13). Alternatively, the bottom surface of the groove20gmay be at the same position as the lower surface of the pad10(i.e., the lower surface of the metal layer13), or may be at a position shallower than the lower surface of the pad10(i.e., the lower surface of the metal layer13). The bottom surface of the groove20gis located, for example, within ±30 μm from the lower surface of the pad10(i.e., the lower surface of the metal layer13). That is, although the side surface of the pad10is generally exposed from the insulating layer20, in one case the entire side surface of the pad10is exposed from the insulating layer20, and in the other case a portion of the side surface of the pad10close to the upper surface10ais exposed, with a portion thereof close to the lower surface being covered with the insulating layer20.

The interconnect layer30is formed on the second side of the insulating layer20. The interconnect layer30includes, for example, a via interconnect in a via hole20xthat penetrates the insulating layer20and that exposes the lower surface of the pad10, and also includes both a via receiving pad formed on the lower surface of the insulating layer20and an interconnect pattern. The via interconnect extends through the insulating layer20, and is in contact with the lower surface of the pad10. The via hole20xmay be a truncated cone-shaped recess in which the size of the opening on the insulating layer40side is larger than the size of the back end of the hole at the lower surface of the pad10. Copper or the like, for example, may be used as the material of the interconnect layer30. The thickness of the via receiving pad and the interconnect pattern constituting the interconnect layer30may be, for example, about 10 to 30 μm.

The insulating layer40is formed on the lower surface of the insulating layer20so as to cover the interconnect layer30. The material and thickness of the insulating layer40may be, for example, the same as those of the insulating layer20. The insulating layer40may contain a filler such as silica (SiO2).

The interconnect layer50is formed on the other side of the insulating layer40. The interconnect layer50includes, for example, a via interconnect in a via hole40xthat penetrates the insulating layer40and that exposes the lower surface of the via receiving pad of the interconnect layer30, and also includes both a pad formed on the lower surface of the insulating layer40and an interconnect pattern. The via hole40xmay be a truncated cone-shaped recess in which the size of the opening on the lower surface side of the insulating layer40is larger than the size of the back end of the hole at the lower surface of the via receiving pad of the interconnect layer30. The material of the interconnect layer50and the thicknesses of the via receiving pad and the interconnect pattern constituting the interconnect layer50may be the same as those of the interconnect layer30, for example.

As described above, the interconnect substrate1is configured such that the insulating layer20is provided with the groove20gthat is located around the pad10in a plan view and whose opening is on the upper surface20aside of the insulating layer20. With this arrangement, the outer edge of the pad10can be situated further in than the perimeter of the opening of the insulating layer20(i.e., the outer edge of the groove20g) in a plan view, so that the area of the upper surface10aof the pad10can be made small. Reduction in the area of the upper surface10aof the pad10enables the reduction of the electrostatic capacitance of the pad10, thereby reducing the deterioration of an electric signal passing through the pad10.

If the groove20gwere not provided, the position of the opening of the insulating layer20that exposes the upper surface10aof the pad10would be arranged as illustrated inFIG.4A, which will be described later. That is, in a plan view, the perimeter of the opening and the outer edge of the pad10would be located at the same position. In this case, if the area of the upper surface10aof the pad10were made smaller than that of the conventional one, the size of the opening would also be made smaller, failing to ensure compatibility with conventional circuit substrates.

When a socket is used for connection to a mounting substrate such as a motherboard, the opening of the insulating layer20that exposes the upper surface10aof the pad10has a size such that the socket does not come into contact with the insulating layer20. Therefore, in order to reduce the electrostatic capacity of the pad10while ensuring the compatibility with conventional circuit substrates, it is necessary to reduce the area of the upper surface10aof the pad10without changing the size of the opening of the insulating layer20. By providing the groove20gthat is located around the pad10in a plan view and whose opening is on the upper surface20aside of the insulating layer20, it is possible to reduce the area of the upper surface10aof the pad10while ensuring compatibility with conventional circuit substrates.

Further, when the pad10and a mounting substrate such as a motherboard are connected via solder, excess solder flows from the upper surface10aof the pad10into the groove20g.which reduces the likelihood of short-circuiting between adjacent pads. Further, the provision of solder entering the groove20genables three-dimensional bonding between the solder and the upper surface10aand side surface of the pad10, thereby improving the bonding strength between the pad10and the solder. In addition, in the interconnect substrate1, since the bottom surface of the groove20gis lower than the upper surface10aof the pad10, the center of gravity of the entire solder is located on the center side of the interconnect substrate1. In particular, it is possible to significantly improve the durability of the solder against a force applied horizontally (in a direction parallel to the upper surface10a). These effects relating to the bonding with the solder are especially prominent when the bottom surface of the groove20gis at the same position as the lower surface of the pad10or situated lower than the lower surface of the pad10.

Method of Making Interconnect Substrate

In the following, a method of making the interconnect substrate according to the first embodiment will be described.FIGS.2A through4Bare drawings illustrating the method of making the interconnect substrate according to the first embodiment. This embodiment is directed to the process steps of making a single interconnect substrate. Alternatively, however, a plurality of structures to serve as respective interconnect substrates may be made as a single piece, followed by being separated into respective interconnect substrates.

In the step illustrated inFIG.2A, a support300having a flat upper surface is prepared. Although a metal plate, a metal foil, or the like can be used as the support300, the support300made of a copper foil will be used as an example in the present embodiment. The thickness of the support300may be, for example, about 18 to 100 μm.

A resist layer400(for example, a dry film resist or the like) having an opening400xin a portion where the pad10is to be formed is formed at a predetermined position on the upper surface of the support300. A sacrificial layer11and a pad10for external connection are sequentially stacked on the upper surface of the support300exposed in the opening400xof the resist layer400by an electrolytic plating method or the like using the support300as a plating power feed layer. Thereafter, the resist layer400is removed.

The pad10may be, for example, a laminated structure in which a metal layer12and a metal layer13are sequentially laminated on the sacrificial layer11. The metal layer12may also be a laminated structure. In this example, the sacrificial layer11and the metal layer13are copper layers. The metal layer12is a laminated structure made by stacking a gold layer, a nickel layer, and a palladium layer in this order from bottom to top on the sacrificial layer11. The thickness of each metal layer is as described above. The sacrificial layer11is a metal layer that is to be removed by etching in the end.

In the step illustrated inFIG.2B, a semi-cured epoxy-based resin film or the like is laminated on the upper surface of the support300such that the lower surface of the film is in contact with the upper surface of the support300and such that the film covers the side surface of the sacrificial layer11as well as the upper surface and side surface of the pad10. The film is cured to form the insulating layer20. Alternatively, instead of laminating the epoxy-based resin film or the like, an epoxy-based resin liquid, paste, or the like may be applied and then cured to form the insulating layer20. The thickness and the like of the insulating layer20are as described above.

In the step illustrated inFIG.3A, a via hole20xis formed in the insulating layer20such as to extend through the insulating layer20and expose the upper surface of the pad10. The via hole20xcan be formed by, for example, a laser processing method using a CO2laser or the like. Subsequently, a desmear process may be performed to remove residual resins adhering to the upper surface of the pad10exposed at the bottom of the via hole20x.

In the step illustrated inFIG.3B, an interconnect layer30is formed on the insulating layer20. The interconnect layer30includes, for example, a via interconnect filling the via hole20x, a via receiving pad formed on the insulating layer20, and an interconnect pattern. The interconnect layer30is electrically connected to the pad10exposed at the bottom of the via hole20x.Copper (Cu) or the like, for example, may be used as the material of the interconnect layer30. The interconnect layer30can be formed using various interconnect layer forming methods such as a semi-additive method and a subtractive method.

In the step illustrated inFIG.3C, the same processes as those illustrated inFIGS.2B through3Bare repeated to form an insulating layer40on the interconnect layer30, to form a via hole40xexposing the upper surface of the via receiving pad of the interconnect layer30in the insulating layer40, and also to form an interconnect layer50. The material and thickness of the insulating layer40may be, for example, substantially the same as the material and thickness of the insulating layer20. The material and thickness of the interconnect layer50may be, for example, substantially the same as the material and thickness of the interconnect layer30.

In the step illustrated inFIG.4A, the support300is removed. The support300made of a copper foil can be removed by wet etching using, for example, a hydrogen peroxide and sulfuric acid-based aqueous solution, a sodium persulfate aqueous solution, an ammonium persulfate aqueous solution, or the like. Since the sacrificial layer11is also a copper layer, the sacrificial layer11is also removed simultaneously with the removal of the support300.

The uppermost surface of the metal layer12, which is a gold layer, is not removed by the etching solution for removing the copper layer, and serves as an etching stopper layer. The upper surface10aof the pad10(i.e., the upper surface of the metal layer12) is exposed at a position recessed from the upper surface20aof the insulating layer20. It may be noted that what is illustrated inFIG.4Ais upside down relative toFIG.3Cand the like. The same applies toFIG.4B, which will be described below.

In the step illustrated inFIG.4B, a groove20gis formed in the insulating layer20around the pad10in a plan view such that the opening thereof is on the same side as the upper surface20aof the insulating layer20. The groove20gcan be formed by, for example, a laser processing method. The groove20gis formed in a ring shape, for example, such that the inner edge and the outer edge have circular shapes with different diameters in a plan view. The bottom surface of the groove20gis formed, for example, at a position deeper than the lower surface of the pad10(i.e., the lower surface of the metal layer13). However, the bottom surface of the groove20gmay be formed at the same position as the lower surface of the pad10(i.e., the lower surface of the metal layer13) , or may be formed at a position shallower than the lower surface of the pad10(i.e., the lower surface of the metal layer13). The position of the bottom surface of the groove20gcan be adjusted by the power of laser, and is formed within ±30 μm in the vertical direction from the lower surface of the pad10(i.e., the lower surface of the metal layer13), for example. With this, the interconnect substrate1is completed in final form.

First Variation of First Embodiment

The first variation of the first embodiment is directed to an example in which an insulating layer covers the side surface of a pad. In the first variation of the first embodiment, a description of the same components as those of the previously described embodiment may be omitted.

FIGS.5A and5Bare drawings illustrating an interconnect substrate according to the first variation of the first embodiment.FIG.5Ais a partial plan view, andFIG.5Bis a partial cross-sectional view taken along the line B-B inFIG.5A.

Referring toFIGS.5A and5B, an interconnect substrate1A is different from the interconnect substrate1(seeFIGS.1A and1Band the like) in that the entire side surface of the pad10is covered with the insulating layer20. That is, the insulating layer20has a ring-shaped covering portion20rcovering the entire side surface of the pad10between the side surface of the pad10and the bottom surface of the groove20gin a plan view. The width of the covering portion20ris, for example, about 0.1 to 2 μm. The covering portion20rmay be formed by adjusting the position where the insulating layer20is irradiated with laser light for forming the groove20g.

As described above, the side surface of the pad10may not necessarily be exposed from the insulating layer20. Such an arrangement also reduces the area of the upper surface10aof the pad10while ensuring compatibility with conventional circuit substrates, thereby enabling the reduction of electrostatic capacity of the pad10.

Second Embodiment

The second embodiment is directed to an example of an interconnect substrate in which the pad has an alternative layer structure. In the second embodiment, a description of the same components as those of the previously described embodiment may be omitted.

FIGS.6A and6Bare drawings illustrating an interconnect substrate according to the second embodiment.FIG.6Ais a partial plan view, andFIG.6Bis a partial cross-sectional view taken along the line C-C inFIG.6A.

Referring toFIGS.6A and6B, an interconnect substrate2is different from the interconnect substrate1(seeFIGS.1A and1Band the like) in that the pad10has a single-layer structure. The pad10is, for example, a copper layer. The surface of the insulating layer20covering the lower surface of the pad10has, for example, an extending portion20sextending in a ring shape between the side surface of the pad10and the bottom surface of the groove20gin a plan view. The width of the extending portion20sis, for example, about 0.5 to 3 μm. An organic film (not shown), for example, is formed on the upper surface10aof the pad10. The organic film may also cover the side surface of the pad10. The organic film includes, for example, an azole compound, an imidazole compound, or the like.

The structure of the pad10and the insulating layer20illustrated inFIGS.6A and6Bmay be formed as follows, for example. First, in the step illustratedFIG.2A, the sacrificial layer11is a copper layer, and the metal layer12is formed as a nickel layer. In this case, the metal layer12also serves as a sacrificial layer. After the steps ofFIGS.2B through3Care performed, the support300and the sacrificial layer11are removed in the step illustrated inFIG.4A, and then the metal layer12serving as the sacrificial layer is removed with an etching solution that etches nickel but does not etch copper.

Subsequently, a groove20gis formed similarly to the manner described in connection withFIG.4B. At this point in time, the inner edge of the groove20gand the outer edge of the pad10are at the same position in a plan view. Then, in order to remove the oxide film formed on the upper surface10aand the side surface of the pad10, the upper surface10aand the side surface of the pad10are etched about 2 to 3 μm. This results in the structure in which the surface of the insulating layer20covering the lower surface of the pad10has the extending portion20sextending in a ring shape between the side surface of the pad10and the bottom surface of the groove20gin a plan view. An organic solderability preservative (OSP) process is then performed on the pad10to form an organic coating.

In the case in which an organic film is not formed on the pad10having a single-layer structure, the etching process for removing the oxide film is not necessary. In this case, the inner edge of the groove20gand the outer edge of the pad10are at the same position in a plan view, without the extending portion20sbeing formed.

The second embodiment may be combined with the first variation of the first embodiment. In such an arrangement, the side surface of the single-layer pad10is covered with the insulating layer20. An organic film, if any, is formed only on the upper surface10aof the pad10.

Third Embodiment

The third embodiment is directed to an example of an interconnect substrate having a plurality of pads. In the third embodiment, a description of the same components as those of the previously described embodiments may be omitted.

FIGS.7A and7Bare drawings illustrating an interconnect substrate according to the third embodiment.FIG.7Ais a partial plan view, andFIG.7Bis a partial cross-sectional view taken along the line D-D inFIG.7A.

Referring toFIGS.7A and7B, an interconnect substrate3has a plurality of pads10.FIGS.7A and7Billustrate two adjacent pads10among the plurality of pads. Grooves20gare present around the respective pads10, and the grooves20garound the adjacent pads10communicate with each other.

As described above, adjacent grooves20gmay communicate with each other. Such an arrangement is effective when the interval between adjacent pads10is narrow. The adjacent pads10may be pads at the same potential. For example, the adjacent pads10may be GND. In this case, there is no problem even if solder flows into the adjacent grooves20gand electrically connects the adjacent pads10. In the case in which the adjacent pads10are at different potentials, solder may be formed only on the upper surface10aof each pad10.

The third embodiment may be combined with the first variation of the first embodiment and/or the second embodiment.

According to at least one embodiment, an interconnect substrate is provided in which the outer edge of a pad for external connection is located further in than the perimeter of an opening of an insulating layer in a plan view.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment(s) of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.

One aspect of the subject-matter described herein is set out non-exclusively in the following clause.

[Clause] A method of making an interconnect substrate, comprising:

laminating a sacrificial layer and a pad for external connection at a predetermined position on an upper surface of a support, such that the sacrificial layer is situated between the pad and the support;

forming an insulating layer on the upper surface of the support, the insulating layer having a first surface in contact with the upper surface of the support and covering the sacrificial layer and the pad;

removing the support and the sacrificial layer; and

forming a groove in the insulating layer, the groove being located around the pad in a plan view and having an opening on a same side as the first surface of the insulating layer.