Patent ID: 12206332

5. DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for generating currents with variable slopes for DC-to-DC voltage converters. Merely by way of example, some embodiments of the invention have been applied to buck-boost converters. But it would be recognized that the invention has a much broader range of applicability.

FIG.1is a simplified diagram showing a compensation current generator for a DC-to-DC voltage converter according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG.1, the compensation current generator100includes a voltage generator110and a current generator120. For example, the compensation current generator100is a system for generating one or more compensation currents for a DC-to-DC voltage converter. As an example, the DC-to-DC voltage converter is a buck-boost converter. Although the above has been shown using a selected group of components for the compensation current generator100, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to some embodiments, the compensation current generator100receives the reference voltage130(e.g., VREF), the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), and the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter), and generates the compensation current150(e.g., ISLP_BST) and the compensation current152(e.g., ISLP_BUK) based at least in part on the reference voltage130(e.g., VREF), the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), and the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter). For example, if the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter) is larger than the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), the compensation current generator100generates the compensation current150(e.g., ISLP_BST) based at least in part on the reference voltage130(e.g., VREF), wherein the compensation current150(e.g., ISLP_BST) flows out of the compensation current generator100. As an example, if the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter) is smaller than the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), the compensation current generator100generates the compensation current152(e.g., ISLP_BUK) based at least in part on the reference voltage130(e.g., VREF), wherein the compensation current152(e.g., ISLP_BUK) flows into the compensation current generator100.

In certain embodiments, the voltage generator110receives the reference voltage130(e.g., VREF). For example, the reference voltage130(e.g., VREF) is a predetermined voltage. As an example, the voltage generator110generates a ramp voltage132(e.g., VRMP_BST) based at least in part on the reference voltage130(e.g., VREF). For example, the voltage generator110also generates a ramp voltage134(e.g., VRMP_BUK) based at least in part on the reference voltage130(e.g., VREF).

In some embodiments, the current generator120receives the reference voltage130(e.g., VREF), the ramp voltage132(e.g., VRMP_BST), the ramp voltage134(e.g., VRMP_BUK), the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), and the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter). For example, the DC-to-DC voltage converter is a buck-boost converter. As an example, the buck-boost converter operates in the buck mode when the output voltage142is smaller than the input voltage140, and the buck-boost converter operates in the boost mode when the output voltage142is larger than the input voltage140.

In certain examples, the current generator120generates the compensation current150(e.g., ISLP_BST) based at least in part on the reference voltage130(e.g., VREF), the ramp voltage132(e.g., VRMP_BST), the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), and the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter). For example, if the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter) is larger than the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), the current generator120generates the compensation current150(e.g., ISLP_BST) based at least in part on the reference voltage130(e.g., VREF) and the ramp voltage132(e.g., VRMP_BST). As an example, the compensation current150(e.g., ISLP_BST) changes (e.g., increases) with a variable slope. For example, the slope of the compensation current150(e.g., ISLP_BST) changes with the ramp voltage132(e.g., VRMP_BST).

In some examples, the current generator120also generates the compensation current152(e.g., ISLP_BUK) based at least in part on the reference voltage130(e.g., VREF), the ramp voltage134(e.g., VRMP_BUK), the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), and the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter). For example, if the output voltage142(e.g., an output voltage of the DC-to-DC voltage converter) is smaller than the input voltage140(e.g., an input voltage of the DC-to-DC voltage converter), the current generator120generates the compensation current152(e.g., ISLP_BUK) based at least in part on the reference voltage130(e.g., VREF) and the ramp voltage134(e.g., VRMP_BUK). As an example, the compensation current152(e.g., ISLP_BUK) changes (e.g., decreases) with a variable slope. For example, the slope of the compensation current152(e.g., ISLP_BUK) changes with the ramp voltage134(e.g., VRMP_BUK).

According to certain embodiments, the compensation current150(e.g., ISLP_BST) changes with time at a slope. For example, the slope changes in response to the change of magnitude of the ramp voltage132(e.g., VRMP_BST). As an example, the magnitude of the ramp voltage132(e.g., VRMP_BST) changes with time, and the slope of the compensation current150(e.g., ISLP_BST) also changes with time. In certain embodiments, the compensation current152(e.g., ISLP_BUK) changes with time at a slope. For example, the slope changes in response to the change of magnitude of the ramp voltage134(e.g., VRMP_BUK). As an example, the magnitude of the ramp voltage134(e.g., VRMP_BUK) changes with time, and the slope of the compensation current152(e.g., ISLP_BUK) also changes with time.

FIG.2is a simplified diagram showing the voltage generator110as part of the compensation current generator100as shown inFIG.1for a DC-to-DC voltage converter according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG.2, the voltage generator110includes a current source210(e.g., I1), a current source212(e.g., I2), a current source214(e.g., I3), a capacitor220(e.g., C1), a capacitor222(e.g., C2), a capacitor224(e.g., C3), a transistor230(e.g., M1), a transistor232(e.g., M2), a transistor234(e.g., M3), a comparator240, a frequency divider242, a buffer250, a NOT gate252, and one-shot pulse generators260and262. Although the above has been shown using a selected group of components for the voltage generator110, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to certain embodiments, a clock signal241(e.g., CLK_OSC) is received by a gate terminal of the transistor230(e.g., M1) to turn on and/or turn off the transistor230(e.g., M1) in order to generate a ramp voltage211(e.g., VRMP_OSC). In some examples, if the clock signal241is at a logic high level, the transistor230(e.g., M1) is turned on, and if the clock signal241is at a logic low level, the transistor230(e.g., M1) is turned off. For example, if the transistor230(e.g., M1) is turned off by the clock signal241, the current source210(e.g., I1) charges the capacitor220(e.g., C1) and the ramp voltage211(e.g., VRMP_OSC) increases with time. As an example, if the transistor230(e.g., M1) is turned on by the clock signal241, the capacitor220(e.g., C1) is discharged and the ramp voltage211(e.g., VRMP_OSC) decreases with time. In certain examples, the ramp voltage211(e.g., VRMP_OSC) is received by a non-inverting input terminal (e.g., the “+” terminal) of the comparator240, which also includes an inverting input terminal (e.g., the “−” terminal) and an output terminal. For example, the inverting input terminal (e.g., the “−” terminal) of the comparator240receives the reference voltage130(e.g., VREF). As an example, the comparator240generates the clock signal241based at least in part on the reference voltage130(e.g., VREF) and the ramp voltage211(e.g., VRMP_OSC) and outputs the clock signal241at the output terminal. In some examples, the frequency of the clock signal241equals the frequency of the ramp voltage211(e.g., VRMP_OSC).

According to some embodiments, the clock signal241is received by the buffer250, which in response generates a signal251. For example, the signal251is a periodic signal (e.g., a clock signal). As an example, the frequency of the clock signal251equals the frequency of the clock signal241. In certain examples, the signal divider242receives the signal251and generates a signal243(e.g., CLK_BST) based at least in part on the signal251. For example, the signal243(e.g., CLK_BST) is a periodic signal (e.g., a clock signal). As an example, the frequency of the signal243(e.g., CLK_BST) equals half of the frequency of the clock signal251. In some examples, the signal243(e.g., CLK_BST) is received by the NOT gate252, which in response generates a signal253(e.g., CLK_BUK). For example, the frequency of the signal253(e.g., CLK_BUK) equals the frequency of the signal243(e.g., CLK_BST). As an example, if the signal243(e.g., CLK_BST) is at the logic high level, the signal253(e.g., CLK_BUK) is at the logic low level, and if the signal243(e.g., CLK_BST) is at the logic low level, the signal253(e.g., CLK_BUK) is at the logic high level.

In certain embodiments, the signal253(e.g., CLK_BUK) is received by the one-shot pulse generator260, which in response generates a signal261. For example, if the signal253(e.g., CLK_BUK) changes from the logic low level to the logic high level, the one-shot pulse generator260changes the signal261from the logic low level to the logic high level, keeps the signal261at the logic high level for a predetermined time duration, and then changes the signal261back to the logic low level. In some examples, if the signal261is at the logic high level, the transistor232(e.g., M2) is turned on, and if the signal261is at the logic low level, the transistor232(e.g., M2) is turned off. For example, if the transistor232(e.g., M2) is turned off by the signal261, the current source212(e.g., I2) charges the capacitor222(e.g., C2) and the ramp voltage134(e.g., VRMP_BUK) increases with time. As an example, if the transistor232(e.g., M2) is turned on by the signal261, the capacitor222(e.g., C2) is discharged and the ramp voltage134(e.g., VRMP_BUK) decreases with time.

In some embodiments, the signal243(e.g., CLK_BST) is received by the one-shot pulse generator262, which in response generates a signal263. For example, if the signal263(e.g., CLK_BST) changes from the logic low level to the logic high level, the one-shot pulse generator262changes the signal263from the logic low level to the logic high level, keeps the signal263at the logic high level for a predetermined time duration, and then changes the signal263back to the logic low level. In some examples, if the263is at the logic high level, the transistor234(e.g., M3) is turned on, and if the signal263is at the logic low level, the transistor234(e.g., M3) is turned off. For example, if the transistor234(e.g., M3) is turned off by the signal263, the current source214(e.g., I3) charges the capacitor224(e.g., C3) and the ramp voltage132(e.g., VRMP_BST) increases with time. As an example, if the transistor234(e.g., M3) is turned on by the signal263, the capacitor224(e.g., C3) is discharged and the ramp voltage132(e.g., VRMP_BST) decreases with time.

According to certain embodiments, the frequency of the clock signal241equals twice the frequency of the signal243(e.g., CLK_BST), and the frequency of the clock signal241equals twice the frequency of the signal253(e.g., CLK_BUK), with the following relationship:

I1C1=2×I2C2=2×I3C3(Equation⁢1)
where I1represents the current generated by the current source210, I2represents the current generated by the current source212, and I3represents the current generated by the current source214. Additionally, C1represents the capacitance of the capacitor220, C2represents the capacitance of the capacitor222, and C3represents the capacitance of the capacitor224.

FIG.3is a simplified diagram showing the current generator120as part of the compensation current generator100as shown inFIG.1for a DC-to-DC voltage converter according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG.3, the current generator120includes voltage dividers310and312, a transconductance amplifier320, an operational amplifier330, current generators380and382, and a voltage divider390. Although the above has been shown using a selected group of components for the current generator120, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to some embodiments, the operational amplifier330receives the reference voltage130(e.g., VREF) and in response generates a voltage331. For example, the voltage331equals the reference voltage130(e.g., VREF). As an example, the voltage331is received by the voltage divider390. In certain examples, the voltage divider390includes a resistor392(e.g., R1), a resistor394(e.g., R2), a resistor396(e.g., R3), and a resistor398(e.g., R4). For example, the voltage divider390generates a threshold voltage371(e.g., VT1), a threshold voltage373(e.g., VT2), and a threshold voltage375(e.g., VT3) based at least in part on the voltage331. As an example, the threshold voltage371(e.g., VT1) is smaller than the threshold voltage373(e.g., VT2), and the threshold voltage373(e.g., VT2) is smaller than the threshold voltage375(e.g., VT3).

According to certain embodiments, the output voltage142(e.g., VOUT) is received by the voltage divider310, and the input voltage140(e.g., VIN) is received by the voltage divider312. For example, the voltage divider310generates a voltage311based at least in part on the output voltage142(e.g., VOUT), and the voltage divider312generates a voltage313based at least in part on the input voltage140(e.g., VIN). As an example, the voltage311equals the output voltage142(e.g., VOUT) multiplied by a predetermined constant (e.g., k), and the voltage313equals the input voltage140(e.g., VIN) multiplied by the predetermined constant (e.g., k), wherein the predetermined constant (e.g., k) is larger than zero and smaller than one.

According to some embodiments, the voltage311is received by a non-inverting input terminal (e.g., the “+” terminal) of the transconductance amplifier320, and the voltage313is received by an inverting input terminal (e.g., the “−” terminal) of the transconductance amplifier320. In certain examples, if the voltage311is smaller than the voltage313, the transconductance amplifier320generates a current341based at least in part on the voltages311and313, wherein the current341flows into the transconductance amplifier320.

As an example, if the voltage311is larger than the voltage313, the transconductance amplifier320generates a current343based at least in part on the voltages311and313, wherein the current343flows out of the transconductance amplifier320.

In certain embodiments, the current341flows into the transconductance amplifier320from the current generator380. For example, the current341is used to generate a current351(e.g., ID2), a current353(e.g., ID3), and a current355(e.g., ID4). As an example, based at least in part on the current351(e.g., ID2), the current353(e.g., ID3), and/or the current355(e.g., ID4), the current generator380generates the compensation current152(e.g., ISLP_BUK), wherein the compensation current152(e.g., ISLP_BUK) flows into the current generator380. In some examples, if the ramp voltage134(e.g., VRMP_BUK) is smaller than the threshold voltage371(e.g., VT1), the compensation current152(e.g., ISLP_BUK) equals zero. In certain examples, if the ramp voltage134(e.g., VRMP_BUK) is larger than the threshold voltage371(e.g., VT1) and smaller than the threshold voltage373(e.g., VT2), the compensation current152(e.g., ISLP_BUK) equals the current351(e.g., ID2) in magnitude. In some examples, if the ramp voltage134(e.g., VRMP_BUK) is larger than the threshold voltage373(e.g., VT2) and smaller than the threshold voltage375(e.g., VT3), the compensation current152(e.g., ISLP_BUK) equals the sum of the current351(e.g., ID2) and the current353(e.g., ID3) in magnitude. In certain examples, if the ramp voltage134(e.g., VRMP_BUK) is larger than the threshold voltage375(e.g., VT3), the compensation current152(e.g., ISLP_BUK) equals the sum of the current351(e.g., ID2), the current353(e.g., ID3), and the current355(e.g., ID4) in magnitude.

In some embodiments, the current343flows out of the transconductance amplifier320into the current generator382. For example, the current343is used to generate a current361(e.g., ID15), a current363(e.g., ID16), and a current365(e.g., ID17). As an example, based at least in part on the current361(e.g., ID15), the current363(e.g., ID16), and/or the current365(e.g., ID17), the current generator382generates the compensation current150(e.g., ISLP_BST), wherein the compensation current150(e.g., ISLP_BST) flows out of the current generator382. In certain examples, if the ramp voltage132(e.g., VRMP_BST) is smaller than the threshold voltage371(e.g., VT1), the compensation current150(e.g., ISLP_BST) equals zero. In some examples, if the ramp voltage132(e.g., VRMP_BST) is larger than the threshold voltage371(e.g., VT1) and smaller than the threshold voltage373(e.g., VT2), the compensation current150(e.g., ISLP_BST) equals the current361(e.g., ID15). In certain examples, if the ramp voltage132(e.g., VRMP_BST) is larger than the threshold voltage373(e.g., VT2) and smaller than the threshold voltage375(e.g., VT3), the compensation current150(e.g., ISLP_BST) equals the sum of the current361(e.g., ID15) and the current363(e.g., ID16) in magnitude. In some examples, if the ramp voltage132(e.g., VRMP_BST) is larger than the threshold voltage375(e.g., VT3), the compensation current150(e.g., ISLP_BST) equals the sum of the current361(e.g., ID15), the current363(e.g., ID16), and the current365(e.g., ID17) in magnitude.

FIG.4shows simplified timing diagrams for the compensation current generator100as shown inFIG.1that includes the voltage generator110as shown inFIG.2and the current generator120as shown inFIG.3according to some embodiments of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the waveform430represents the reference voltage130(e.g., VREF) as a function of time, the waveform411represents the ramp voltage211(e.g., VRMP_OSC) as a function of time, the waveform441represents the clock signal241(e.g., CLK_OSC) as a function of time, the waveform443represents the signal243(e.g., CLK_BST) as a function of time, and the waveform453represents the signal253(e.g., CLK_BUK) as a function of time. As an example, the waveform434represents the ramp voltage134(e.g., VRMP_BUK) as a function of time, the waveform452represents the compensation current152(e.g., ISLP_BUK) as a function of time, the waveform432represents the ramp voltage132(e.g., VRMP_BST) as a function of time, and the waveform450represents the compensation current150(e.g., ISLP_BST) as a function of time.

As shown by the waveform411, during one period of the ramp voltage211, the ramp voltage211(e.g., VRMP_OSC) increases from a minimum voltage460towards the reference voltage130represented by the waveform430, and after the ramp voltage211(e.g., VRMP_OSC) reaches the reference voltage130, the ramp voltage211(e.g., VRMP_OSC) decreases towards the minimum voltage460according to certain embodiments. For example, as shown by the waveform441, during one period of the clock signal241(e.g., CLK_OSC), when the ramp voltage211(e.g., VRMP_OSC) increases from the minimum voltage460towards the reference voltage130, the clock signal241(e.g., CLK_OSC) remains at a logic high level, and when the ramp voltage211(e.g., VRMP_OSC) decreases towards the minimum voltage460, the clock signal241(e.g., CLK_OSC) remains at a logic low level. As an example, if the ramp voltage211(e.g., VRMP_OSC) drops to the minimum voltage460, the clock signal241(e.g., CLK_OSC) changes from the logic low level to the logic high level, and if the ramp voltage211(e.g., VRMP_OSC) reaches the reference voltage130, the clock signal241(e.g., CLK_OSC) changes from the logic high level to the logic low level.

As shown by the waveforms443and453, during one period of the clock signal241(e.g., CLK_OSC), the signal243(e.g., CLK_BST) is at the logic low level and the signal253(e.g., CLK_BUK) is at the logic high level, and immediately after this period of the clock signal241(e.g., CLK_OSC), during another period of the clock signal241(e.g., CLK_OSC), the signal243(e.g., CLK_BST) is at the logic high level and the signal253(e.g., CLK_BUK) is at the logic low level, according to some embodiments. For example, the frequency of the signal243(e.g., CLK_BST) equals half of the frequency of the ramp voltage211(e.g., VRMP_OSC), and the frequency of the signal253(e.g., CLK_BUK) also equals half of the frequency of the ramp voltage211(e.g., VRMP_OSC). As an example, the duty cycle of the signal243(e.g., CLK_BST) is equal to 0.5, and the duty cycle of the signal253(e.g., CLK_BUK) is also equal to 0.5.

In certain embodiments, during one period of the signal253(e.g., CLK_BUK) that starts when the signal253(e.g., CLK_BUK) changes from the logic high level to the logic low level and ends when the signal253(e.g., CLK_BUK) again changes from the logic high level to the logic low level, the ramp voltage134(e.g., VRMP_BUK) increases from a minimum voltage462to a maximum voltage142e464, passing through the threshold voltage371(e.g., VT1), the threshold voltage373(e.g., VT2), and the threshold voltage375(e.g., VT3), as shown by the waveform434, and the magnitude of the compensation current152(e.g., ISLP_BUK) changes from a maximum current466to a minimum current468as shown by the waveform452. For example, when the ramp voltage134(e.g., VRMP_BUK) is larger than the minimum voltage462and smaller than the threshold voltage371(e.g., VT1), the magnitude of the compensation current152(e.g., ISLP_BUK) remains constant at a slope S0that is equal to zero. As an example, when the ramp voltage134(e.g., VRMP_BUK) is larger than the threshold voltage371(e.g., VT1) and smaller than the threshold voltage373(e.g., VT2), the magnitude of the compensation current152(e.g., ISLP_BUK) decreases with time at a slope S1, wherein the slope S1is smaller than zero and the absolute value of the slope S1is equal to the slope S1multiplied by −1. For example, when the ramp voltage134(e.g., VRMP_BUK) is larger than the threshold voltage373(e.g., VT2) and smaller than the threshold voltage375(e.g., VT3), the magnitude of the compensation current152(e.g., ISLP_BUK) decreases with time at a slope S2, wherein the slope S2is smaller than zero and the absolute value of the slope S2is equal to the slope S2multiplied by −1. As an example, when the ramp voltage134(e.g., VRMP_BUK) is larger than the threshold voltage375(e.g., VT3) and is smaller than the maximum voltage464, the magnitude of the compensation current152(e.g., ISLP_BUK) decreases with time at a slope S3, wherein the slope S3is smaller than zero and the absolute value of the slope S3is equal to the slope S3multiplied by −1. In some examples, the slope S0is larger than the slope S1, the slope S1is larger than the slope S2, the slope S2is larger than the slope S3. In certain examples, the absolute value of the slope S0is smaller than the absolute value of the slope S1, the absolute value of the slope S1is smaller than the absolute value of the slope S2, and the absolute value of the slope S2is smaller than the absolute value of the slope S3.

In some embodiments, during one period of the signal243(e.g., CLK_BST) that starts when the signal243(e.g., CLK_BST) changes from the logic high level to the logic low level and ends when the signal243(e.g., CLK_BST) again changes from the logic high level to the logic low level, the ramp voltage132(e.g., VRMP_BST) increases from a minimum voltage482to a maximum voltage484, passing through the threshold voltage371(e.g., VT1), the threshold voltage373(e.g., VT2), and the threshold voltage375(e.g., VT3), as shown by the waveform432, and the magnitude of the compensation current150(e.g., ISLP_BST) changes from a minimum current488to a maximum current486to as shown by the waveform450. For example, when the ramp voltage132(e.g., VRMP_BST) is larger than the minimum voltage482and smaller than the threshold voltage371(e.g., VT1), the magnitude of the compensation current150(e.g., ISLP_BST) remains constant at a slope S10that is equal to zero. As an example, when the ramp voltage132(e.g., VRMP_BST) is larger than the threshold voltage371(e.g., VT1) and smaller than the threshold voltage373(e.g., VT2), the magnitude of the compensation current150(e.g., ISLP_BST) increases with time at a slope S11, wherein the slope S11is larger than zero and the absolute value of the slope S11is equal to the slope S11. For example, when the ramp voltage132(e.g., VRMP_BST) is larger than the threshold voltage373(e.g., VT2) and smaller than the threshold voltage375(e.g., VT3), the magnitude of the compensation current150(e.g., ISLP_BST) increases with time at a slope S12, wherein the slope S12is larger than zero and the absolute value of the slope S12is equal to the slope S12. As an example, when the ramp voltage132(e.g., VRMP_BST) is larger than the threshold voltage375(e.g., VT3) and is smaller than the maximum voltage484, the magnitude of the compensation current150(e.g., ISLP_BST) increases with time at a slope S13, wherein the slope S13is larger than zero and the absolute value of the slope S13is equal to the slope S13. In some examples, the slope S10is smaller than the slope S11, the slope S11is smaller than the slope S12, the slope S12is smaller than the slope S13. In certain examples, the absolute value of the slope S10is smaller than the absolute value of the slope S11, the absolute value of the slope S11is smaller than the absolute value of the slope S12, and the absolute value of the slope S12is smaller than the absolute value of the slope S13.

FIG.5is a simplified diagram showing a buck-boost converter that includes the compensation current generator100as shown inFIG.1according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The buck-boost converter500includes a buck-booster controller510, a switch520(e.g., S1), a switch522(e.g., S2), a switch524(e.g., S3), a switch526(e.g., S4), a coil530, a resistor540(e.g., RSNS), a resistor542(e.g., RFB1), a resistor544(e.g., RFB2). For example, the buck-booster controller510includes the compensation current generator100, transconductance amplifiers620and622, comparators630and632, a logic signal generator640, resistors650and652, a resistor654(e.g., RCOMP), and a capacitor660(e.g., CCOMP). As an example, the buck-boost converter500operates with a fixed frequency. Although the above has been shown using a selected group of components for the buck-boost converter500, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

As shown inFIG.5, the buck-boost converter500receives the input voltage140and generates the output voltage142based at least in part on the input voltage140according to certain embodiments. For example, the resistor542(e.g., RFB1) and the resistor544(e.g., RFB2) are parts of a voltage divider, which receives the output voltage142and generates a feedback voltage543. In some examples, the feedback voltage543is received by a non-inverting input terminal (e.g., the “+” terminal) of the transconductance amplifier622, which also includes an inverting input terminal (e.g., the “−” terminal) and an output terminal. For example, the inverting input terminal (e.g., the “−” terminal) of the feedback voltage543receives the reference voltage130(e.g., VREF). As an example, the output terminal of the transconductance amplifier622is coupled to one terminal of the resistor654(e.g., RCOMP). In certain examples, another terminal of the resistor654(e.g., RCOMP) is connected to one terminal of the capacitor660(e.g., CCOMP). For example, another terminal of the capacitor660(e.g., CCOMP) is biased to the ground voltage.

According to some embodiments, the output terminal of the transconductance amplifier622is biased to a voltage131(e.g., VCOMP), which is received by an inverting input terminal (e.g., the “−” terminal) of the comparator630(e.g., PWM_BST) and a non-inverting input terminal (e.g., the “+” terminal) of the comparator632(e.g., PWM_BUK). In certain examples, the resistor540(e.g., RSNS) is connected in series with the coil530. For example, one terminal of the resistor540(e.g., RSNS) provides a voltage541to a non-inverting input terminal of the transconductance amplifier620, and another terminal of the resistor540(e.g., RSNS) provides a voltage543to an inverting input terminal of the transconductance amplifier620. As an example, the transconductance amplifier620determines the voltage541minus the voltage543, wherein the voltage541minus the voltage543represents a coil current531that flows through the coil530. In some examples, based at least in part on the information associated with the coil current531that flows through the coil530, the transconductance amplifier620generates a current621(e.g., ISENSE).

In certain embodiments, the current621(e.g., ISENSE) is the same as a current631in magnitude and direction, and the current621(e.g., ISENSE) is also the same as a current633in magnitude and direction. For example, the current631flows through the resistor650to the ground, and the current633flows through the resistor652to the ground. As an example, the compensation current150(e.g., ISLP_BST) also flows through the resistor650to the ground, and the compensation current152(e.g., ISLP_BUK) also flows through the resistor652to the ground.

In some embodiments, the currents631and150that flows through the resistor650generates a voltage651(e.g., VSUM_BST), and the currents633and152that flows through the resistor652generates a voltage653(e.g., VSUM_BUK). For example, the voltage651(e.g., VSUM_BST) is received by the non-inverting input terminal (e.g., the “+” terminal) of the comparator630. As an example, the voltage653(e.g., VSUM_BUK) is received by the inverting input terminal (e.g., the “−” terminal) of the comparator632. In some examples, the comparator630generates a comparison signal631based at least in part on the voltage651(e.g., VSUM_BST) and the voltage131(e.g., VCOMP). In certain examples, the comparator632generates a comparison signal633based at least in part on the voltage131(e.g., VCOMP) and the voltage653(e.g., VSUM_BUK).

According to certain embodiments, the comparison signals631and633are received by the logic signal generator640, which in response generate logic signals641,643,645, and647. For example, the logic signal641is used to open and/or close the switch520(e.g., S1), and the logic signal643is used to open and/or close the switch522(e.g., S2). As an example, the logic signal645is used to open and/or close the switch540(e.g., S3), and the logic signal647is used to open and/or close the switch526(e.g., S4). In certain embodiments, based at least in part on the logic signals641,643,645, and647, the buck-boost converter500converts the input voltage140to the output voltage142. For example, the input voltage140to the output voltage142are received by the compensation current generator100, which generates the compensation current150(e.g., ISLP_BST) and the compensation current152(e.g., ISLP_BUK). As an example, the compensation current150(e.g., ISLP_BST) and the compensation current152(e.g., ISLP_BUK) are used to generate the logic signals641,643,645, and647.

According to some embodiments, based at least in part on the information associated with the coil current531that flows through the coil530, the transconductance amplifier620generates the current621(e.g., ISENSE), which represents the coil current531. For example, when the buck-boost converter500operates under the boost mode (e.g., when the output voltage142is larger than the input voltage140), the compensation current150(e.g., ISLP_BST) is used to compensate the current631, which is the same as the current621(e.g., ISENSE) in magnitude and direction. As an example, when the buck-boost converter500operates under the buck mode (e.g., when the output voltage142is smaller than the input voltage140), the compensation current152(e.g., ISLP_BUK) is used to compensate the current633, which is the same as the current621(e.g., ISENSE) in magnitude and direction. In certain examples, the compensation provided by the compensation current150(e.g., ISLP_BST) and/or the compensation current152(e.g., ISLP_BUK) reduces (e.g., eliminates) sub-harmonic oscillation of the buck-boost converter500.

Certain embodiments of the present invention provide a DC-to-DC voltage converter (e.g., the buck-boost converter500) that can convert a wide range of input voltage to a wide range of output voltage and also can provide a high power to the load of the DC-to-DC voltage converter. For example, the slope of the compensation current152(e.g., ISLP_BUK) changes with the ramp voltage134(e.g., VRMP_BUK). As an example, the slope of the compensation current150(e.g., ISLP_BST) changes with the ramp voltage132(e.g., VRMP_BST).

According to some embodiments, a system for generating one or more compensation currents for a DC-to-DC voltage converter includes: a voltage generator configured to receive a reference voltage and generate a first ramp voltage and a second ramp voltage based at least in part on the reference voltage; and a current generator configured to receive the first ramp voltage, the second ramp voltage, an input voltage, and an output voltage; wherein the current generator is further configured to: if the output voltage is smaller than the input voltage, generate a first compensation current based at least in part on the first ramp voltage; and if the output voltage is larger than the input voltage, generate a second compensation current based at least in part on the second ramp voltage; wherein: the first compensation current changes with time at a first variable slope; and the first variable slope changes with the first ramp voltage; wherein: the second compensation current changes with time at a second variable slope; and the second variable slope changes with the second ramp voltage. For example, the system for generating one or more compensation currents is implemented according to at leastFIG.1.

As an example, the input voltage is an input voltage of the DC-to-DC voltage converter; and the output voltage is an output voltage of the DC-to-DC voltage converter. For example, the first compensation current flows into the current generator; and the second compensation current flows out of the current generator. As an example, the first compensation current decreases with time at the first variable slope, the first variable slope being equal to or smaller than zero; and the absolute value of the first variable slope increases with the first ramp voltage. For example, the current generator is further configured to receive the reference voltage and generate one or more threshold voltages based at least in part on the reference voltage. As an example, the current generator is further configured to, if the first ramp voltage becomes larger than one threshold voltage of the one or more threshold voltages, change the absolute value of the first variable slope from a first value to a second value; wherein: the first value is equal to or larger than zero; and the second value is larger than the first value. For example, the second compensation current increases with time at the second variable slope, the second variable slope being equal to or larger than zero; and the absolute value of the second variable slope increases with the second ramp voltage. As an example, the current generator is further configured to receive the reference voltage and generate one or more threshold voltages based at least in part on the reference voltage. For example, the current generator is further configured to, if the second ramp voltage becomes larger than one threshold voltage of the one or more threshold voltages, change the absolute value of the second variable slope from a first value to a second value; wherein: the first value is equal to or larger than zero; and the second value is larger than the first value.

According to certain embodiments, a controller for a DC-to-DC voltage converter includes: a compensation current generator configured to receive a reference voltage, an input voltage and an output voltage and generate the first compensation current and the second compensation current based at least in part on the reference voltage, the input voltage and the output voltage; and a logic signal generator configured to generate one or more logic signals based on at least information associated with the first compensation current and the second compensation current; wherein the compensation current generator is further configured to: generate a first ramp voltage and a second ramp voltage based at least in part on the reference voltage; if the output voltage is smaller than the input voltage, generate the first compensation current based at least in part on the first ramp voltage; and if the output voltage is larger than the input voltage, generate the second compensation current based at least in part on the second ramp voltage; wherein: the first compensation current changes with time at a first variable slope; and the first variable slope changes with the first ramp voltage; wherein: the second compensation current changes with time at a second variable slope; and the second variable slope changes with the second ramp voltage. For example, the controller is implemented according to at leastFIG.5and/orFIG.1.

As an example, the input voltage is an input voltage of the DC-to-DC voltage converter; and the output voltage is an output voltage of the DC-to-DC voltage converter. For example, the first compensation current flows into the compensation current generator; and the second compensation current flows out of the compensation current generator.

According to some embodiments, a method for generating one or more compensation currents for a DC-to-DC voltage converter includes: receiving a reference voltage; generating a first ramp voltage and a second ramp voltage based at least in part on the reference voltage; receiving the first ramp voltage, the second ramp voltage, an input voltage, and an output voltage; if the output voltage is smaller than the input voltage, generating a first compensation current based at least in part on the first ramp voltage; and if the output voltage is larger than the input voltage, generating a second compensation current based at least in part on the second ramp voltage; wherein: the first compensation current changes with time at a first variable slope; and the first variable slope changes with the first ramp voltage; wherein: the second compensation current changes with time at a second variable slope; and the second variable slope changes with the second ramp voltage. For example, the method for generating one or more compensation currents is implemented according to at leastFIG.1.

As an example, the input voltage is an input voltage of the DC-to-DC voltage converter; and the output voltage is an output voltage of the DC-to-DC voltage converter. For example, the first compensation current decreases with time al the first variable slope, the first variable slope being equal to or smaller than zero; and the absolute value of the first variable slope increases with the first ramp voltage. As an example, the method further includes: receiving the reference voltage; and generating one or more threshold voltages based at least in part on the reference voltage. For example, the method further includes: if the first ramp voltage becomes larger than one threshold voltage of the one or more threshold voltages, changing the absolute value of the first variable slope from a first value to a second value; wherein: the first value is equal to or larger than zero; and the second value is larger than the first value. As an example, the second compensation current increases with time at the second variable slope, the second variable slope being equal to or larger than zero; and the absolute value of the second variable slope increases with the second ramp voltage. For example, the method further includes: receiving the reference voltage; and generating one or more threshold voltages based at least in part on the reference voltage. As an example, the method further includes: if the second ramp voltage becomes larger than one threshold voltage of the one or more threshold voltages, changing the absolute value of the second variable slope from a first value to a second value; wherein: the first value is equal to or larger than zero; and the second value is larger than the first value.

According to certain embodiments, a method for a DC-to-DC voltage converter includes: receiving a reference voltage, an input voltage and an output voltage; generating the first compensation current and the second compensation current based at least in part on the reference voltage, the input voltage and the output voltage; processing information associated with the first compensation current and the second compensation current; and generating one or more logic signals based on at least information associated with the first compensation current and the second compensation current; wherein the generating the first compensation current and the second compensation current based at least in part on the reference voltage, the input voltage and the output voltage includes: generating a first ramp voltage and a second ramp voltage based at least in part on the reference voltage; if the output voltage is smaller than the input voltage, generating the first compensation current based at least in part on the first ramp voltage; and if the output voltage is larger than the input voltage, generating the second compensation current based at least in part on the second ramp voltage; wherein: the first compensation current changes with time at a first variable slope; and the first variable slope changes with the first ramp voltage; wherein: the second compensation current changes with time at a second variable slope; and the second variable slope changes with the second ramp voltage. For example, the method is implemented according to at leastFIG.5and/orFIG.1. As an example, the input voltage is an input voltage of the DC-to-DC voltage converter; and the output voltage is an output voltage of the DC-to-DC voltage converter.

For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. As an example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. For example, various embodiments and/or examples of the present invention can be combined.

Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments.