Patent ID: 12243739

DESCRIPTION OF EMBODIMENTS

Semiconductor wafers and methods for manufacturing the same according to embodiments of the present invention are described with reference to drawings. Identical or corresponding constitutional elements are given the same reference numerals, and the repeated description of such constitutional elements may be omitted.

First Embodiment

FIG.1is a cross-sectional view of a semiconductor wafer100according to a first embodiment. The semiconductor wafer100includes a silicon substrate10. A gallium nitride growth layer12is provided on an upper surface of the silicon substrate10. The gallium nitride growth layer12is divided into a plurality of small sections13. The plurality of small sections13are separate from one another. The gallium nitride growth layer is, for example, a multi-layer including In1-x-yGaxAlyN layer. Here, 0≤x≤1 and 0≤y≤1.

An insulating film14is provided on the upper surface of the silicon substrate10. With the insulating film14, portions between the plurality of small sections13are filled. A thickness of the insulating film14is, for example, equal to or greater than 1 μm and equal to or less than a thickness of the gallium nitride growth layer12. The insulating film14is, for example, a silicon nitride film. The insulating film14continues from one and to the other end of the silicon substrate10.

A method for manufacturing the semiconductor wafer100will be described next. First, a thermal oxide film16is formed on the upper surface of the silicon substrate10.FIG.2is a plan view illustrating a state where the thermal oxide film16is formed on the silicon substrate10. A grid pattern is formed on the thermal oxide film16through photolithography. By this means, a grid-like oxide film is formed. The upper surface of the silicon substrate10is separated into a plurality of regions11by the thermal oxide film16.

Then, the gallium nitride growth layer12is formed on the silicon substrate10. The gallium nitride growth layer12is formed through, for example, metal-organic chemical vapor deposition or molecular beam epitaxy. By this means, the gallium nitride growth layer12is formed at portions which are not covered by the thermal oxide film16among the silicon substrate10. In other words, the plurality of small sections13are grown in the plurality of regions11. Note that it is assumed that the gallium nitride growth layer12includes a buffer layer for epitaxially growing gallium nitride.

Thereafter, the thermal oxide film16is removed. The thermal oxide film16is removed using, for example, hydrofluoric acid.FIG.3is a plan view illustrating a state where the thermal oxide film16is removed.FIG.4is a cross-sectional view illustrating a state where the thermal oxide film16is removed. The above-described process of forming the gallium nitride growth layer12, which is divided into the plurality of small sections13, on the upper surface of the silicon substrate10is a first process.

Then, a second process of filling portions between the plurality of small sections13with the insulating film14is performed.FIG.5is a cross-sectional view illustrating a state where the insulating film14is formed. The insulating film14is deposited on the silicon substrate10through, for example, chemical vapor deposition (CVD). The insulating film14is formed so as to tightly adhere to the silicon substrate10.

The insulating film14exerts stress on the silicon substrate10in a direction opposite to a direction in which the gallium nitride growth layer12exerts stress on the silicon substrate10. The insulating film14is formed with a material which applies stress opposite to stress of the gallium nitride growth layer12, to the silicon substrate10. The insulating film14is, for example, a silicon nitride film or a silicon oxide film. The insulating film14is preferably formed with a material which applies great stress to the silicon substrate10.

Typically, the silicon nitride film can generate tensile stress or compressive stress of approximately several GPa in accordance with deposition conditions. While film stress depends on a manufacturing device, the silicon nitride film formed through plasma CVD can provide film stress of approximately 300 MPa, and the silicon nitride film formed through thermal CVD can provide film stress of approximately 1 GPa. Further, the insulating film14may be formed through electron cyclotron resonance (ECR) sputtering. The silicon nitride film formed through ECR sputtering can provide film stress of approximately 3 GPa.

The insulating film14may be formed through plasma CVD using, for example, SiH4and NH3as a process gas. In this case, by changing a ratio of SiH4with respect to NH3between 0.5 and 2, film stress can be changed between tensile stress of approximately 100 MPa and compressive stress of approximately 300 MPa. Thus, for example, by setting the ratio of SiH4with respect to NH3at equal to or less than 0.5, tensile stress can be applied from the insulating film14to the silicon substrate10. Further, by setting the ratio of SiH4with respect to NH3at equal to or greater than 2, tensile stress can be applied from the insulating film14to the silicon substrate10.

Then, as illustrated inFIG.1, the insulating film14is removed until the gallium nitride growth layer12is exposed. The insulating film14is removed through etching such as dry etching. In this event, a thickness of the insulating film14is adjusted by adjusting an etching period. Typically, as the insulating film14is thicker, stress to be exerted on the silicon substrate10becomes greater. Thus, by adjusting the etching period, a level of stress to be applied by the insulating film14to the silicon substrate10can be adjusted.

Further, warpage which can be corrected becomes greater in proportion to the thickness of the insulating film14. The thickness of the insulating film14may be determined from an amount of warpage of the silicon substrate10in a state where the gallium nitride growth layer12is formed and before the insulating film14is formed. The thickness of the insulating film14may be set so that the silicon substrate10becomes flat in a state where the insulating film14is formed.

Typically, the film thickness of the insulating film, which is required to reduce warpage of the substrate, depends on a size of a region between the gallium nitride growth layers or film stress of the insulating film. For example, if the insulating film14having film stress of 1 GPa is deposited to have a thickness of 1 μm, warpage of the silicon substrate10of approximately several micrometers to 10 μm can be corrected compared to a case where the insulating film14is not provided. Here, a width of the insulating film14put between adjacent small sections13is set at 1/10 with respect to the width of the small section13. Further, the thickness of the silicon substrate10is set at 625 μm. From the above-described settings, it is possible to sufficiently reduce warpage of the silicon substrate10by setting the thickness of the insulating film14at, for example, equal to or greater than 1 μm.

Through the above-described process, the insulating film14is formed. As illustrated inFIG.3, the insulating film14is formed at portions where the gallium nitride growth layer12is removed and the silicon substrate10is exposed in a grid shape. In other words, the insulating film14is formed in a grid shape.

An electrode, or the like, is formed on a surface of the gallium nitride growth layer12exposed from the insulating film14. A device is thereby formed.

Typically, a heterostructure can be manufactured by using a nitride-based semiconductor material such as gallium nitride (GaN), aluminum gallium nitride (AlGaN) and aluminum nitride (AlN). Thus, these materials are sometimes utilized to create a high-frequency device, an optical device or a power device.

A nitride-based semiconductor structure is typically manufactured through epitaxial growth on silicon carbide, sapphire or a silicon substrate. In particular, a silicon substrate is inexpensive compared to silicon carbide, or the like. It is therefore possible to reduce material cost.

Here, typically, there is a case where a substrate is warped if the gallium nitride is grown on the silicon substrate. This may lead to occurrence of a problem in a process of conveyance, exposure, or the like.

A lattice constant of silicon is 0.5431 nm. Thus, an interatomic spacing on a (111) plane of silicon is 0.5431/√{square root over (2)}=0.3840 nm. In contrast, a lattice constant of gallium nitride is 0.3819 nm. A lattice spacing of gallium nitride is narrower than a lattice spacing of silicon. Thus, the silicon substrate receives compressive stress from gallium nitride which is epitaxially grown on the (111) plane.

Further, a linear expansion coefficient of silicon is 2.6×10−6K−1. In contrast, a linear expansion coefficient of gallium nitride is 5.6×10−6K−1. Normally, gallium nitride is grown at a high temperature of equal to or higher than 800° C. Thus, when the temperature falls from a growth temperature to a room temperature, gallium nitride contracts more than silicon. Thus, the silicon substrate receives compressive stress from the gallium nitride growth layer.

Accordingly, if the gallium nitride growth layer is formed on the silicon substrate, the silicon substrate is warped so that the gallium nitride growth layer is on an inside. Actually, a direction of warpage differs depending on conditions of epitaxial growth or a configuration of the buffer layer.

Further, it is also possible to reduce warpage of the substrate by dividing the gallium nitride growth layer into small sections to disperse stress. However, typically, it is difficult to completely eliminate warpage of the substrate with such a method. For example, there is a possibility that wafer warpage of approximately several micrometers to 10 μm may be left on a substrate of 4 inches. Such warpage particularly becomes a problem in a gate exposure process, or the like, in which it is necessary to form a fine pattern.

In contrast, the insulating film14in the present embodiment exerts stress on the silicon substrate10in a direction opposite to a direction in which the gallium nitride growth layer12exerts stress on the silicon substrate10. In other words, in a case where the gallium nitride growth layer12exerts compressive stress on the silicon substrate10, a material which exerts tensile stress on the silicon substrate is used as the insulating film14. Further, in a case where the gallium nitride growth layer12exerts tensile stress on the silicon substrate10, a material which exerts compressive stress on the silicon substrate is used as the insulating film14.

By this means, stress received by the silicon substrate10from the gallium nitride growth layer12can be cancelled out by the insulating film14. It is therefore possible to reduce warpage of the silicon substrate10. In the present embodiment, both an effect of dispersing stress by dividing the gallium nitride growth layer12into small sections13and an effect of cancelling out stress by the insulating film14can be obtained. It is therefore possible to easily implement an exposure process while reducing warpage of wafer.

Further, stress to be exerted on the silicon substrate10can be adjusted by the thickness of the insulating film14. The thickness of the insulating film14can be adjusted by an etching period. It is therefore possible to easily make the silicon substrate10flat.

Note that it is difficult to reduce warpage by forming a thick thermal oxide film16illustrated inFIG.2. In this case, a thick thermal oxide film16is formed on the silicon substrate10before epitaxial growth. In this event, the thermal oxide film16has great film stress, and thus, there is a possibility that wafer is greatly warped when epitaxial growth starts. This may make an epitaxial growth process difficult.

It is therefore necessary to form a thin thermal oxide film16to prevent the silicon substrate10from being greatly warped. In contrast, the insulating film14is formed to have a thickness greater than a thickness of the thermal oxide film16so as to apply greater stress to the silicon substrate10.

As a modified example of the present embodiment, a shape of a region where the gallium nitride growth layer12is removed illustrated inFIG.3is not limited to a grid shape. The region where the gallium nitride growth layer12is removed may have other shapes if the gallium nitride growth layer12can be divided into a plurality of small sections13. The region where the gallium nitride growth layer12is removed preferably vertically and horizontally continues from one end to the other end of the silicon substrate10considering that the insulating film14is formed to apply stress to the silicon substrate10.

Further, the first process may be performed as follows. First, the gallium nitride growth layer12is formed on the whole upper surface of the silicon substrate10through metal-organic chemical vapor deposition or molecular beam epitaxy. Then, a mask layer such as photoresist is formed on the gallium nitride growth layer12. Then, the gallium nitride growth layer12is etched using the mask layer until the silicon substrate10is exposed. As a result of this, the silicon substrate10is exposed in a grid shape, and the gallium nitride growth layer12is divided into a plurality of small sections13. Then, the mask layer is removed.

These modifications can be applied, as appropriate, to semiconductor wafers and methods for manufacturing the same according to the following embodiments. Note that the semiconductor wafers and the methods for manufacturing the same according to the following embodiments are similar to those of the first embodiment in many respects, and thus differences between the semiconductor wafers and the methods for manufacturing the same according to the following embodiments and those of the first embodiment will be mainly described below.

Second Embodiment

FIG.6is a cross-sectional view of a semiconductor wafer200according to a second embodiment. A structure of an insulating film214in the semiconductor wafer200is different from the structure of the insulating film in the semiconductor wafer100. Concave portions215are formed between pairs of small sections13adjacent to each other among the plurality of small sections13in the insulating film214.

A method for manufacturing the semiconductor wafer200will be described next. The first process is the same as the first process in the first embodiment. The second process will be described next.FIG.7is a cross-sectional view describing the method for manufacturing the semiconductor wafer according to the second embodiment. First, an upper surface of the silicon substrate10and a side surface and an upper surface of each of the plurality of small sections13are covered with the insulating film214.

The insulating film214is formed along the silicon substrate10and the plurality of small sections13. Concavities and convexities reflecting the shape of the plurality of small sections13are formed on a surface of the insulating film214. In this event, concave portions215are formed at portions between pairs of small sections13adjacent to each other in the insulating film214. A thickness of portions which cover side surfaces of the small sections13in the insulating film214is equal to or less than ½ of a width of a region put between the adjacent small sections13.

Then, resist218is applied. The resist218is provided on the insulating film214so that the concave portions215are filled with the resist218. An upper surface of the resist218is flat. The resist218has such a thickness that concavities and convexities on the surface of the insulating film214are not reflected on the upper surface of the resist218.

Then, an etching process is performed. By this means, upper surfaces of the plurality of small sections13are exposed from the insulating film214.FIG.8is a cross-sectional view illustrating a state where the upper surfaces of the plurality of small sections13are exposed. In the etching process, the resist218is also removed along with the insulating film214through dry etching until the gallium nitride growth layer12is exposed. As a result of this, portions of the resist218provided above the upper surfaces of the plurality of small sections13and portions of the insulating film214provided above the upper surfaces of the plurality of small sections13are removed.

In this event, it is preferable to use etching conditions which make an etching rate of the resist218equal to an etching rate of the insulating film214. Typically, it is possible to find etching conditions which make the etching rate of the resist equal to the etching rate of the insulating film in a silicon oxide film and a silicon nitride film. Such etching conditions can expose the upper surfaces of the plurality of small sections13with high accuracy.

After the etching process, potions of the resist218, with which the concave portions215are filled are removed. Through the above-described process, the insulating film214is formed.

If the insulating film214is provided so as to cover the plurality of small sections13, as illustrated inFIG.7, there is a case where grid-like concavities and convexities may be formed on the surface of the insulating film214. If only the insulating film214is etched until the gallium nitride growth layer12is exposed, similar to the first embodiment, without the resist218being applied, the insulating film214on the silicon substrate10is also etched. Thus, there is a possibility that the insulating film214is scarcely left on the silicon substrate10.

In an extreme case where a film having coverage of 0 is used as the insulating film214, the insulating film214has the same thickness on the gallium nitride growth layer12and on the silicon substrate10. Thus, if the insulating film214is etched until the gallium nitride growth layer12is exposed, the insulating film214on the silicon substrate10is also completely removed.

In contrast, in the present embodiment, a thick insulating film214can be left on the silicon substrate10also in a case where concavities and convexities are formed on the surface of the insulating film214. It is therefore possible to sufficiently reduce warpage of the silicon substrate10by the insulating film214.

Third Embodiment

FIG.9is a cross-sectional view of a semiconductor wafer300according to a third embodiment. The semiconductor wafer300is different from the semiconductor wafer100in a structure of a silicon substrate310. A plurality of convex portions310aare formed on a side of an upper surface of the silicon substrate310. The plurality of small sections13are provided on the plurality of convex portions310a.

A method for manufacturing the semiconductor wafer300will be described next. First, the gallium nitride growth layer12is formed on the upper surface of the silicon substrate310. In this state, the upper surface of the silicon substrate310is flat. Further, the gallium nitride growth layer12is formed on the whole upper surface of the silicon substrate310.

Then, an etching process is performed. In the etching process, first, a mask layer such as photoresist is formed on the gallium nitride growth layer12. Then, part of the gallium nitride growth layer12is removed using the mask layer through etching. The etching is, for example, dry etching. By this means, the gallium nitride growth layer12is removed in a grid shape, and the silicon substrate310is exposed. The gallium nitride growth layer12is divided into a plurality of small sections13through the etching process.

Further, etching is continued also after the silicon substrate310is exposed. As a result of this, the silicon substrate310is etched, and grooves are formed on the silicon substrate310. In other words, a plurality of convex portions310aare formed on the side of the upper surface of the silicon substrate310.

Then, the insulating film14is formed. With the insulating film14, portions between adjacent convex portions310aare filled. The subsequent process is similar to the process in the first embodiment.

In the present embodiment, it is possible to make the insulating film14thicker by an amount corresponding to a depth of the grooves formed on the silicon substrate310. It is therefore possible to apply stress greater than stress in the first embodiment to the silicon substrate310by the insulating film14. Further, also in a case where the thickness of the gallium nitride growth layer12is thinner than the thickness of the insulating film14which is required to reduce warpage, the insulating film14can be made thick.

Fourth Embodiment

FIG.10is a cross-sectional view of a semiconductor wafer400according to a fourth embodiment. In the present embodiment, the thermal oxide film16is provided on the upper surface of the silicon substrate10. The insulating film14is provided on the thermal oxide film16. The thermal oxide film16and the insulating film14form an insulating layer.

A method for manufacturing the semiconductor wafer400will be described next. Processes until the process of growing the gallium nitride growth layer12is similar to those in the first embodiment. In the present embodiment, the thermal oxide film16is not removed. Then, the insulating film14is formed on the thermal oxide film16. The subsequent processes are similar to those in the first embodiment.

In the present embodiment, the thermal oxide film16is not removed, so that it is possible to simplify the manufacturing process. Further, in a case where the thermal oxide film16exerts stress which corrects warpage of the silicon substrate10, the thermal oxide film16can be effectively utilized to reduce warpage.

Note that the technical features described in the above embodiments may be combined as appropriate.

REFERENCE SIGNS LIST

10silicon substrate,11region,12gallium nitride growth layer,13small section,14insulating film,16thermal oxide film,100,200semiconductor wafer,214insulating film,215concave portion,218resist,300semiconductor wafer,310silicon substrate,310aconvex portion,400semiconductor wafer