Patent ID: 12191380

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Various embodiments provide methods of forming channel regions in semiconductor devices having improved profiles and semiconductor devices formed by said methods. The methods may include forming channel regions having gradient concentrations of semiconductor materials and thinning the channel regions. In some embodiments, the channel regions may be formed of silicon germanium having higher germanium concentrations at the bottom of the channel regions and lower germanium concentrations at the top of the channel regions. The channel regions may be thinned by exposing the channel regions to alkaline or acid solutions, which may be combined with or cycled with oxidant solutions. Portions of the channel regions having higher germanium concentrations may be thinned at higher rates than portions of the channel regions having lower germanium concentrations, which may be used to provide channel regions having rectangular profiles. Providing channel regions having more rectangular profiles reduces drain-induced barrier lowering (DIBL), increasing performance and reducing device defects of the resulting semiconductor devices.

FIG.1illustrates an example of FinFETs, in accordance with some embodiments. The FinFETs comprise fins55on a substrate50(e.g., a semiconductor substrate). Shallow trench isolation (STI) regions58are disposed in the substrate50, and the fins55protrude above and from between neighboring STI regions58. Although the STI regions58are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of STI regions. Additionally, although the fins55are illustrated as single, continuous materials with the substrate50, the fins55and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fins55refer to the portions extending between the neighboring STI regions58.

Gate dielectric layers100are along sidewalls and over a top surface of the fins55, and gate electrodes102are over the gate dielectric layers100. Epitaxial source/drain regions92are disposed on opposite sides of the fins55, the gate dielectric layers100, and the gate electrodes102.FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode102and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions92of the FinFETs. Cross-section B-B′ is perpendicular to cross-section A-A′ and is along a longitudinal axis of a fin55and in a direction of, for example, the current flow between the epitaxial source/drain regions92of the FinFETs. Cross-section C-C′ is parallel to cross-section A-A′ and extends through the epitaxial source/drain regions92of the FinFETs. Subsequent figures refer to these reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context of fin field effect transistors (FinFETs) and nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs) formed using gate-last processes. In some embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices or the like.

FIGS.2through16Bare cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.2,3A,3B,3C,4A,4B,5,13C,16C,16D, and16Eillustrate reference cross-section A-A′ illustrated inFIG.1, including a region50N and a region50P.FIGS.6A,11A,12A,13A,14A,15A, and16Aare illustrated along reference cross-section A-A′ illustrated inFIG.1in the region50N or the region50P.FIGS.6B,7B,8B,9B,10B,11B,12B,13B,13D,13E,14B,14C,15B, and16Bare illustrated along a similar cross-section B-B′ illustrated inFIG.1.FIGS.7A,8A,9A,10A, and10Care illustrated along reference cross-section C-C′ illustrated inFIG.1.

InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.

The substrate50has a region50N and a region50P. The region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The region50N may be physically separated from the region50P (as illustrated by divider51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the region50N and the region50P.

Further inFIG.2, a portion of the substrate50in the region50P may be replaced with a first epitaxial semiconductor material52. A patterned mask (not separately illustrated), such as a patterned photoresist, may be formed over the region50N. The patterned photoresist may be formed by depositing a photoresist layer over the substrate50using spin-on coating or the like. The photoresist layer may then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove an exposed or unexposed portion of the photoresist layer, thereby forming the patterned photoresist. The substrate50in the region50P is then etched to form a first opening using a suitable etch process, such as an anisotropic etch process (e.g., a dry etch process) or the like. The patterned photoresist may then be removed.

The first epitaxial semiconductor material52is then formed filling the first opening. The first epitaxial semiconductor material52may be deposited by an epitaxial growth process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first epitaxial semiconductor material52may comprise a semiconductor material such silicon germanium or the like.

The first epitaxial semiconductor material52may be formed with a gradient germanium concentration. For example, in some embodiments, a germanium concentration of the first epitaxial semiconductor material52may be gradually and continuously increased from a top surface of the first epitaxial semiconductor material52to a bottom surface of the first epitaxial semiconductor material52. In some embodiments, an atomic percentage of germanium in the first epitaxial semiconductor material52may range from about 0 percent at a top surface of the first epitaxial semiconductor material52to about 90 percent at a bottom surface of the first epitaxial semiconductor material52. In some embodiments, the atomic percentage of germanium in the first epitaxial semiconductor material52may range from about 8 percent at the top surface of the first epitaxial semiconductor material52to about 32 percent at the bottom surface of the first epitaxial semiconductor material52. In some embodiments, a ratio of the atomic percentage of germanium at the top surface of the first epitaxial semiconductor material52to the atomic percentage of germanium at the bottom surface of the first epitaxial semiconductor material52may range from about 1:2 to about 1:8 or from about 1:3 to about 1:5. As will be discussed in greater detail below, including the first epitaxial semiconductor material52with the prescribed ratios of atomic percentages of germanium results in fins (such as the fins55, discussed below with respect toFIGS.3A through4B) having improved rectangular profiles, which results in better gate control, reduced fin-width variation, and decreased drain induced barrier loading.

In embodiments in which the first epitaxial semiconductor materials52are deposited by CVD, the gradient germanium concentration in the first epitaxial semiconductor material52may be achieved by gradually decreasing a flowrate of a germanium-containing precursor (e.g., germane (GeH4) or the like) relative to a flowrate of a silicon-containing precursor (e.g., dichlorosilane (H2Cl2Si), silane (SiH4), or the like) during the deposition of the first epitaxial semiconductor material52. For example, a ratio of a flowrate of a germanium precursor to a flowrate of a silicon precursor may be from about 1 to about 9 or from about 1 to about 3 at the beginning of the deposition process used to deposit the first epitaxial semiconductor materials52and a ratio of the flowrate of the germanium precursor to the flowrate of the silicon precursor may be from about 0 to about 1 or from about 0 to about 0.5 at the end of the deposition process used to deposit the first epitaxial semiconductor material52. After the first epitaxial semiconductor material52is deposited, top surfaces of the substrate50in the region50N and the first epitaxial semiconductor material52in the region50P may be planarized by a process such as a chemical mechanical polish (CMP). A thickness T1of the first epitaxial semiconductor material52may be from about 10 nm to about 200 nm or from about 40 nm to about 60 nm.

InFIG.3A, fins55are formed in the substrate50and the first epitaxial semiconductor material52. The fins55are semiconductor strips. In some embodiments, the fins55may be formed in the substrate50and the first epitaxial semiconductor material52by etching trenches in the substrate50and the first epitaxial semiconductor material52. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), a neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic.

The fins55may be patterned by any suitable method. For example, the fins55may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. In some embodiments, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins55. In some embodiments, the mask (or other layer) may remain on the fins55. As illustrated inFIG.3A, the fins55in both the region50N and the region50P may have tapered profiles in which widths at the bottoms of the fins55are greater than widths at the top of the fins55.

In the region50N, the fins55(including fin-shaped portions of the substrate50extending from a flat top surface of the substrate50) may have a bottom width W1from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; a top width W2from about 2 nm to about 50 nm, from about 20 to 30 nm, or from about 23 nm to about 27 nm; a ratio of the top width W2to the bottom width W1from about 0.5 to about 2 or from about 0.7 to about 0.9; and a height H1from about 10 nm to about 200 nm or from about 70 nm to about 90 nm. The fins55in the region50N may be spaced with a pitch P1from about 2 nm to about 100 nm or from about 25 nm to about 35 nm. An angle θ1between sidewalls of the fins55in the region50N and a top surface of the substrate50may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. In the region50P, the fins55(including fin-shaped portions of the first epitaxial semiconductor material52and the substrate50extending from a flat top surface of the substrate50) may have a bottom width W3from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; a middle width W4at an interface between the substrate50and the first epitaxial semiconductor material52from about 2.2 nm to about 80 nm, from about 23 nm to about 33 nm, or from about 26 nm to about 30 nm; a top width W5from about 2 nm to about 50 nm, from about 20 nm to about 30 nm, or about 23 nm to about 27 nm; and a height H2from about 10 nm to about 200 nm or from about 70 nm to about 90 nm. A ratio of the top width W5to the middle width W4may be from about 2 to about 0.5 or from about 0.8 to about 1.0 and a ratio of the middle width W4to the bottom width W3may be from about 2 to about 0.5 or from about 0.8 to about 1.0. The fins55in the region50pmay be spaced with a pitch P2from about 2 nm to about 100 nm or from about 25 nm to about 35 nm. An angle θ2between sidewalls of the fins55in the region50P and a top surface of the substrate50may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°.

FIG.3Billustrates an embodiment in which a thinning process is performed to thin the fins55after forming the fins55and before STI regions (such as the STI regions58, discussed below with respect toFIG.4A). In the embodiment illustrated inFIG.3B, the fins55in the region50N may be exposed to etchants used to thin the fins55in the region50P and the fins55in the region50P may be exposed to etchants used to thin the fins in the region50N.

InFIG.3B, exposed portions of the fins55in the region50N and exposed portions of the fins55in the region50P formed in the substrate50may be etched using first etching chemicals in a first etching process. During the first etching process, the fins55in both the region50N and the region50P may be exposed to the first etching chemicals. A first etching selectivity, which is the ratio of the etching rate (sometimes referred to as the trimming rate) of the fins55in the region50N and portions of the fins55in the region50P formed in the substrate50(e.g., portions of the fins55formed of silicon) to the etching rate of portions of the fins55in the region50P formed of the first epitaxial semiconductor material52(e.g., portions of the fins55formed of silicon germanium), may be desired to be high in order to minimize the etching of the portions of the fins55in the region50P formed of the first epitaxial semiconductor material52. For example, the first etching selectivity may be higher than about 5, and may range from about 5 to about 20, or higher. The first etching process may be performed at a temperature ranging from about 5° C. to about 100° C., such as about room temperature (e.g. about 23° C.). The fins55may be exposed to the first etching chemicals for a period ranging from about 10 seconds to about 5 minutes or from about 45 seconds to about 75 seconds.

In some embodiments, the first etching chemicals may include a first etchant dissolved in a first solvent. The first etching chemicals may be free from oxidants. The first etchant may include an alkaline or an acid. In embodiments in which the first etchant includes an alkaline, the first etchant may include a metal hydroxide (Mn+(OH−)n), amine derivatives, ammonium derivatives, combinations thereof, or the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivatives may include ammonia (NH3), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH, (CH3)4N(OH)), tetraethyl ammonium hydroxide (TEAH, (C2H5)4N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH3)3(C14H29)N(OH)), tetrabutylammonium hydroxide (TBAH, (C4H9)4N(OH)), combinations thereof, or the like. In embodiments in which the first etchant is an alkaline, a pH of the first etching chemicals may be from about 7 to about 13 or from about 8 to about 10. The first etchant may be present in the first etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

In embodiments in which the first etchant includes an acid, the first etchant may include hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H2SO4), phosphoric acid (H3PO4), nitric acid (HNO3), carboxylic acid derivatives (CnH2n+1COOH), combinations thereof, or the like. In embodiments in which the first etchant is an acid, a pH of the first etching chemicals may be from about 0 to about 7 or from about 1 to about 3. The first etchant may be present in the first etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

The first solvent may be utilized to help mix and deliver the first etchant. The first solvent may not participate in the etching reaction itself. In a particular embodiment the first etching solvent may be a solvent such as deionized water or the like. However, any suitable solvent may be utilized.

The first etching chemicals may further include ionic or nonionic surfactants such as quaternary ammonium (NR4+), sulfate (SO42−), sulfonate (R—SO3−), phosphate (—PO43−), carboxylates (R—COO−), alcohol ethoxylates, alkyl phenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, or the like, which may be added to reduce the surface tension of the first etching chemicals. The surfactants may be present in the first etching chemicals in a concentration ranging from about 0.0001 M to about 1 M or from about 0.005 m to about 0.02 M.

Prior to etching the fins55with the first etching process, the fins55have tapered profiles in which widths at the bottom of the fins55are greater than widths at the top of the fins55(as discussed previously in the discussed related toFIG.3A). The first etching process may have the same etching rates at the top of the fins55and the bottom of the fins55, such that the fins55in the region50N and portions of the fins55in the region50P formed in the substrate50still have a tapered profile after etching the fins55with the first etching process.

After the fins55in the region50N and the region50P are etched with the first etching process, the fins55in the region50N may have a height H5from about 10 nm to about 200 nm or from about 60 nm to about 80 nm; a bottom width W10from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm; a top width W11from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and a ratio of the top width W11to the bottom width W10from about 0.5 to about 2 or from about 0.65 to about 0.85. An angle θ5between sidewalls of the fins55in the region50N and a top surface of the substrate50may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. Portions of the fins55in the region50P formed in the substrate50may have a bottom width W12from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm; a top width W13from about 2 nm to about 80 nm, from about 13 nm to about 23 nm, or from about 16 nm to about 20 nm; and a ratio of the top width W13to the bottom width W12from about 0.5 to about 2 or from about 0.8 to about 1.0. An angle θ6between sidewalls of the portions of the fins55formed in the substrate50in the region50P and a top surface of the substrate50may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°.

Further inFIG.3B, exposed portions of the fins55in the region50P formed of the first epitaxial semiconductor material52may be etched using second etching chemicals in a second etching process separate from the first etching process. During the second etching process, the fins55in both the region50P and the region50N may be exposed to the second etching chemicals. A second etching selectivity, which is the ratio of the etching rate of the portions of the fins55in the region50P formed of the first epitaxial semiconductor material52to the etching rate of the fins55in the region50N and the portions of the fins55in the region50P formed in the substrate50, is desired to be high in order to minimize the etching of the fins55in the region50N and the portions of the fins in the region50P formed in the substrate50. For example, the second etching selectivity may be higher than about 5, and may range from about 5 to about 20, or higher. The second etching process may be performed at a temperature ranging from about 5° C. to about 100° C., such as about room temperature (e.g. about 23° C.).

In some embodiments, the second etching chemicals may include an oxidant and a second etchant dissolved in a second solvent. The fins55may be exposed to the oxidant and the second etchant simultaneously. In the embodiments in which the fins55are exposed to the oxidant and the second etchant simultaneously, the fins55may be exposed to the second etching chemicals for a period from about 30 seconds to about 2 minutes or from about 45 seconds to about 75 seconds. In some embodiments, the second etchant may be the same as the first etchant. For example, in some embodiments, the second etchant may be an alkaline or an acid.

In embodiments in which the second etchant includes an alkaline, the second etchant may include a metal hydroxide (Mn+(OH−)n), amine derivatives, ammonium derivatives, combinations thereof, or the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivatives may include ammonia (NH3), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH, (CH3)4N(OH)), tetraethyl ammonium hydroxide (TEAH, (C2H5)4N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH3)3(C14H29)N(OH)), tetrabutylammonium hydroxide (TBAH, (C4H9)4N(OH)), combinations thereof, or the like. In embodiments in which the second etchant is an alkaline, a pH of the second etching chemicals may be from about 7 to about 13 or from about 8 to about 10. The second etchant may be present in the second etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

In embodiments in which the second etchant includes an acid, the second etchant may include hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H2SO4), phosphoric acid (H3PO4), nitric acid (HNO3), carboxylic acid derivatives (CnH2n+1COOH), combinations thereof, or the like. In embodiments in which the second etchant is an acid, a pH of the second etching chemicals may be from about 0 to about 7 or from about 1 to about 3. The second etchant may be present in the second etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

The oxidant may include ozonated de-ionized water (DIO3), hydrogen peroxide (H2O2), other non-metal oxidants, combinations thereof, or the like. An oxidizing agent may be present in the second etching chemicals in a concentration ranging from about 0.0001 M to about 1 M or from about 0.0005 m to about 0.002 M. Including the oxidant in addition to the second etchant allows the first epitaxial semiconductor material52to be etched selectively with respect to the fins55in the region50N and portions of the fins55in the region50P formed in the substrate50. The oxidant may be used to oxidize the fins55in the region50P, forming silicon germanium oxide in the fins55, and the second etchant may then be used to etch the silicon germanium oxide material, thinning the fins55in the region50P. On the other hand, in the region50N, the oxidant may be used to oxidize the fins55, forming silicon oxide in the fins55, which is etched at a slower rate by the second etchant. Silicon may also be oxidized at a slower rate than silicon germanium, such that any silicon oxide layer formed in the fins55in the region50N and portions of the fins55in the region50P formed in the substrate50is thinner than an oxide layer formed in the fins55in the region50P. Accordingly, the fins55in the region50N and portions of the fins55in the region50P formed in the substrate50are substantially un-thinned, while the fins55in the region50P are thinned.

The second solvent may be utilized to help mix and deliver the oxidant and the second etchant. The second solvent may not participate in the etching reaction itself. In a particular embodiment the second etching solvent may be a solvent such as deionized water, acetic acid (CH3COOH), or the like. In embodiments in which the oxidant includes ozonated deionized water, the deionized water may also act as a solvent. Any suitable solvents may be utilized.

The second etching chemicals may further include ionic or nonionic surfactants such as quaternary ammonium (NR4+), sulfate (SO42−), sulfonate (R—SO3−), phosphate (—PO43−), carboxylates (R—COO−), alcohol ethoxylates, alkyl phenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, or the like, which may be added to reduce the surface tension of the second etching chemicals. The surfactants may be present in the second etching chemicals in a concentration ranging from about 0.0001 M to about 1 M or from about 0.005 m to about 0.02 M.

In a specific embodiment, the second etching chemicals may include hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH). The acetic acid may be a solvent in which the hydrofluoric acid and the hydrogen peroxide dissolved. The hydrogen peroxide may be an oxidant, which is used to oxidize the fins55in the region50P. The hydrofluoric acid may be a second etchant which is used to thin the fins55in the region50P. A volume ratio of hydrofluoric acid:hydrogen peroxide:acetic acid may be about 1:2:3.

In further embodiments, the fins55may be exposed to an oxidant, then the oxidant may be removed and the fins55may be exposed to second etchant in a cyclical process to thin the fins55. Exposing the fins55to the oxidant may oxidize the fins55in the region50N and the region50P. Exposing the fins55to the etchants may selectively etch the oxide formed in the first epitaxial semiconductor material52relative to the oxide formed in the fins55in the region50N and portions of the fins55in the region50P formed in the substrate50.

The oxidant used in the cyclical process may be the same as those described above as being used in the process in which the fins55are exposed to the oxidant and the second etchant simultaneously. For example, the oxidant may include ozonated de-ionized water (DIO3), hydrogen peroxide (H2O2), other non-metal oxidants, combinations thereof, or the like. An oxidizing agent may be present in the oxidant at a concentration ranging from about 0.0001 M to about 1 M or from about 0.0005 m to about 0.002 M. As discussed previously, exposing the fins55may oxidize the fins55in the region50P. The fins55in the region50N may also be oxidize, but may be oxidized at a slower rate than the fins55in the region50P.

The second etchant used in the cyclical process may be the same as or similar to the first etchant. The second etchant may be present in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M. Exposing the fins55to the second etchant thins the fins55. As discussed previously, the fins55in the region50N may be thinned at a slower rate than the fins55in the region50P.

For each cycle, the fins55may be exposed to the oxidant for a period ranging from about 10 seconds to about 2 minutes or from about 45 seconds to about 75 seconds and the fins55may be exposed to the second etchant for a period ranging from about 10 seconds to about 5 minutes or from about 45 seconds to about 75 seconds. The cyclical etching process may be repeated for up to 20 cycles, up to 10 cycles, 4 to 6 cycles, or the like. Exposing the fins55to the oxidant, then the second etchant in a cyclical process may provide better control of the etching of the first epitaxial semiconductor material52. This results in improved gate control of resulting FinFETs, reduces the fin-width variation, and leads to decreased DIBL.

The second etching process may have etching rates which depend on the concentration of germanium in the first epitaxial semiconductor material52. For example, the second etching process may have higher etching rates with increasing germanium concentration in the first epitaxial semiconductor material52. As discussed previously in the discussion related toFIG.2, the first epitaxial semiconductor material52may have a gradient germanium concentration in which the germanium concentration is higher at the bottom surface of the first epitaxial semiconductor material52and gradually and continually decreases towards the top surface of the first epitaxial semiconductor material52. Thus, bottom portions of the first epitaxial semiconductor material52may be etched by the second etching process with higher etching rates than top portions of the first epitaxial semiconductor material52. A ratio of the etching rate at the bottom surface of the first epitaxial semiconductor material52(e.g., a maximum etching rate) to the etching rate at the top surface of the first epitaxial semiconductor material52(e.g., a minimum etching rate) may be from about 1 to about 3 or from about 1.25 to about 1.75.

Prior to etching the fins55in the region50P with the second etching process, the fins55have a tapered profile in which widths at the bottom of the fins55are greater than widths at the top of the fins55(as discussed previously in the discussed related toFIG.3A). Etching the first epitaxial semiconductor material52with the second etching process which has a higher etching rate at the bottom of the first epitaxial semiconductor material52than the top of the first epitaxial semiconductor material52results in the first epitaxial semiconductor material52having a more rectangular profile after etching the first epitaxial semiconductor material52with the second etching process.

After the first epitaxial semiconductor material52is etched with the second etching process, portions of the fins55in the region50P formed of the first epitaxial semiconductor material52may have a height H6from about 5 nm to about 100 nm or from about 60 nm to about 80 nm; a bottom width W14from about 2.2 nm to about 100 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; a top width W15from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and a ratio of the top width W15to the bottom width W14from about 0.8 to about 1.2 or from about 0.9 to about 1.1. An angle θ7between sidewalls of the portions of the fins55formed of the first epitaxial semiconductor material52in the region50P and a top surface of the substrate50may be from about 80° to about 100°, from about 85° to about 95°, or from about 88° to about 92°. The fins55in the region50P may have a height H7from about 10 nm to about 200 nm or from about 70 nm to about 90 nm.

Forming the fins55in the region50P having a gradient germanium concentration and thinning the fins55in the region50P using an etching process which has a higher etching rate with increasing germanium concentration results in the fins55in the region50P having more rectangular profiles and improves control of the process used to etch the fins55in the region50P. Including the fins55in FinFETs results in better gate control, reduced fin-width variation, and decreased DIBL.

FIG.3Cillustrates another embodiment in which a thinning process is performed to thin the fins55after forming the fins55and before STI regions (such as the STI regions58, discussed below with respect toFIG.4A). In the embodiment illustrated inFIG.3C, the fins55in the region50N may be masked while the fins55in the region50P are thinned and the fins55in the region50P may be masked while the fins55in the region50N are thinned.

InFIG.3C, the fins55in the region50N are exposed to the first etching chemicals while the fins55in the region50P are protected. The fins55in the region50P may be protected by forming a patterned mask (not separately illustrated), such as a patterned photoresist, over the region50P. The patterned photoresist may be formed by depositing a photoresist layer over the substrate50using spin-on coating or the like. The photoresist layer may then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove an exposed or unexposed portion of the photoresist layer, thereby forming the patterned photoresist. The fins55in the region50N are then thinned by exposing the fins55to the first etching chemicals. The patterned photoresist may then be removed. In some embodiments, the fins55in the region50N may also be protected while the fins55in the region50P are exposed to the second etching chemicals using a process the same as or similar to the process used to protect the fins55in the region50P. The first etching chemicals and processes used to etch the fins55in the region50N and the second etching chemicals and processes used to etch the fins55in the region50P may be the same as or similar to those described above in reference toFIG.3B.

After the fins55in the region50N and the region50P are etched, the fins55in the region50N may have the same dimensions as the fins55in the region50N discussed above with respect toFIG.3B. Portions of the fins55in the region50P formed in the substrate50may have the same or similar dimensions as the portions of the fins55in the region50P formed in the substrate50as discussed above with respect toFIG.3A. For example, widths of the fins55in the region50P formed in the substrate50P may be within about 10 nm of the widths discussed above with respect toFIG.3A. Portions of the fins55in the region50P formed of the first epitaxial semiconductor material52may have a height fig from about 5 nm to about 100 nm or from about 60 nm to about 80 nm; a bottom width W16from about 2.2 nm to about 100 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; a top width W17from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and a ratio of the top width W17to the bottom width W16from about 0.8 to about 1.2, or from about 0.9 to about 1.1. An angle θ8between sidewalls of the portions of the fins55formed of the first epitaxial semiconductor material52in the region50P and a top surface of the substrate50may be from about 80° to about 100°, from about 85° to about 95°, or from about 88° to about 92°. The fins55in the region50P may have a height H9from about 10 nm to about 200 nm or from about 70 nm to about 90 nm.

Forming the fins55in the region50P having a gradient germanium concentration and thinning the fins55in the region50P using an etching process which has a higher etching rate with increasing germanium concentration results in the fins55in the region50P having more rectangular profiles and improves control of the process used to etch the fins55in the region50P. Including the fins55in FinFETs results in better gate control, reduced fin-width variation, and decreased DIBL. Using various masks to protect the fins55in the region50N while etching the fins55in the region50P and to protect the fins in the region50P while etching the fins55in the region50N allows for additional control over fin profiles in the region50N and the region50P.

FIG.4Aillustrates an embodiment in which the fins55are not thinned until after shallow trench isolation (STI) regions58are formed. For example, the thinning process may be performed after the formation of the STI regions58, as will be discussed below with respect toFIG.4B, or after the removal of dummy gate stacks (such as dummy gate stacks including the dummy gates72and the dummy dielectric layers60, discussed below with respect toFIGS.6A and6B), as will be discussed below with respect toFIGS.13C through13E. However, it should be understood that the steps performed inFIG.4Aand subsequent figures may be performed on fins55which have been thinned as described above in reference toFIGS.3B and3C.

InFIG.4A, shallow trench isolation (STI) regions58are formed adjacent the fins55. The STI regions58may be formed by forming an insulation material (not separately illustrated) over the substrate50and between neighboring fins55. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system with post curing to convert the deposited material to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In some embodiments, the insulation material is formed such that excess insulation material covers the fins55. The insulation material may comprise a single layer or may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along surfaces of the substrate50and the fins55. Thereafter, a fill material, such as those discussed above may be formed over the liner.

A removal process is then applied to the insulation material to remove excess insulation material over the fins55. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process may planarize the insulation material and the fins55. The planarization process exposes the fins55such that top surfaces of the fins55and the insulation material are level after the planarization process is complete.

The insulation material is then recessed to form the STI regions58as illustrated inFIG.4A. The insulation material is recessed such that upper portions of the fins55and the substrate50protrude from between neighboring STI regions58. Further, the top surfaces of the STI regions58may have flat surfaces as illustrated, convex surfaces, concave surfaces (such as dishing), or a combination thereof. The top surfaces of the STI regions58may be formed flat, convex, and/or concave by an appropriate etch. The STI regions58may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins55and the substrate50). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. A height H11of the STI regions58may be from about 30 nm to about 100 nm or from about 55 nm to about 75 nm.

Further inFIG.4A, appropriate wells (not separately illustrated) may be formed in the fins55and/or the substrate50. In some embodiments, a P well may be formed in the region50N, and an N well may be formed in the region50P. In some embodiments, a P well or an N well are formed in both the region50N and the region50P.

In the embodiments with different well types, the different implant steps for the region50N and the region50P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins55and the STI regions58in the region50N. The photoresist is patterned to expose the region50P of the substrate50, such as a PMOS region. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the region50N, such as an NMOS region. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 1×1018atoms/cm3, such as between about 1×1016atoms/cm3and about 1×1018atoms/cm3. After the implant, the photoresist is removed, such as by an acceptable ashing process.

Following the implanting of the region50P, a photoresist is formed over the fins55and the STI regions58in the region50P. The photoresist is patterned to expose the region50N of the substrate50, such as the NMOS region. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the region50P, such as the PMOS region. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 1×1018atoms/cm3, such as between about 1×1016atoms/cm3and about 1×1018atoms/cm3. After the implant, the photoresist may be removed, such as by an acceptable ashing process.

After the implants of the region50N and the region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

FIG.4Billustrates an embodiment in which the thinning process is performed to thin the fins55after forming the STI regions58, rather than being performed after forming the fins55and before forming the STI regions58, as discussed above in reference toFIGS.3B and3C. In the embodiment illustrated inFIG.4B, the fins55in the region50N may be exposed to etchants used to thin the fins55in the region50P and the fins55in the region50P may be exposed to etchants used to thin the fins55in the region50N.

In the embodiment illustrated inFIG.4B, the fins55in both the region50N and the region50P are exposed to the first etching chemicals and the second etching chemicals in processes the same as or similar to those described above with respect toFIG.3B. Following the first etching process, the fins55(including fin-shaped portions of the substrate50extending from a flat top surface of the substrate50) in the region50N may have a height H3from about 5 nm to about 100 nm or from about 60 nm to about 80 nm; a bottom width W6from about 2.2 nm to about 80 nm, from about 17 nm to about 27 nm, or from about 20 nm to about 24 nm; a top width W7from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and a ratio of the top width W7to the bottom width W6from about 0.5 to about 2 or from about 0.6 to about 0.8. An angle θ3between sidewalls of the fins55in the region50N and a top surface of the substrate50may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. Following the second etching process, the fins55(including fin-shaped portions of the first epitaxial semiconductor material52and the substrate50extending from a flat top surface of the substrate50) in the region50P may have a height H4from about 5 nm to about 100 nm or from about 60 nm to about 80 nm; a bottom width W8from about 2.2 nm to about 80 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; a top width W9from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and a ratio of the top width W9to the bottom width W8from about 0.8 to about 1.2 or from about 0.9 to about 1.1. In some embodiments, the bottom width W8of the fins55in the region50P may be within 10 nm, within 5 nm, or within 1 nm of the top width W9of the fins55in the region50P. An angle θ4between sidewalls of the fins55in the region50P and a top surface of the substrate50may be from about 80° to about 100°, from about 85° to about 95°, or from about 88° to about 92°.

Portions of the fins55in the region50N and the region50P surrounded by the STI regions58may remain unchanged after the thinning process is performed. For example, portions of the fins55disposed below top surfaces of the STI regions58may have widths similar to or the same as those discussed above with respect toFIG.3A. As illustrated inFIG.4B, there may be a step change in the widths of the fins55level with the top surfaces of the STI regions58due to the thinning process.

Forming the fins55in the region50P having a gradient germanium concentration and thinning the fins55in the region50P using an etching process which has a higher etching rate with increasing germanium concentration results in the fins55in the region50P having more rectangular profiles and improves control of the process used to etch the fins55in the region50P. Including the fins55in FinFETs results in better gate control, reduced fin-width variation, and decreased DIBL.

FIG.5illustrates an embodiment in which the fins55are not thinned until after dummy gates stacks (such as dummy gate stacks including the dummy gates72and the dummy dielectric layers60, discussed below with respect toFIGS.6A and6B) are formed. For example, the thinning process may be performed after the removal of the dummy gate stacks, as will be discussed below with respect toFIGS.13C through13E. However, it should be understood that the steps performed inFIG.5and subsequent figures may be performed on fins55which have been thinned as described above in reference toFIGS.3B,3C, and4B.

InFIG.5, dummy dielectric layers60are formed on the fins55and the substrate50. The dummy dielectric layers60may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer62is formed over the dummy dielectric layers60, and a mask layer64is formed over the dummy gate layer62. The dummy gate layer62may be deposited over the dummy dielectric layers60and then planarized by a process such as CMP. The mask layer64may be deposited over the dummy gate layer62. The dummy gate layer62may be conductive or non-conductive materials and may be selected from a group including amorphous silicon, polycrystalline-silicon (poly silicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer62may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing the selected material. The dummy gate layer62may be made of other materials that have a high etching selectivity from the material of the STI regions58. The mask layer64may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer62and a single mask layer64are formed across the region50N and the region50P. It is noted that the dummy dielectric layers60are shown covering only the fins55and the substrate50for illustrative purposes only. In some embodiments, the dummy dielectric layers60may be deposited such that the dummy dielectric layers60cover the STI regions58, extending between the dummy gate layer62and the STI regions58.

FIGS.6A through16Eillustrate various additional steps in the manufacturing of embodiment devices.FIGS.6A through13BandFIGS.14A through16Billustrate features in either of the region50N or the region50P. For example, the structures illustrated inFIGS.6A through13BandFIGS.14A through16Bmay be applicable to both the region50N and the region50P. Differences (if any) in the structures of the region50N and the region50P are described in the text accompanying each figure. For example, the structures illustrated inFIGS.13C through13EandFIGS.16C through16Edescribe differences between the region50N and the region50P.

InFIGS.6A and6B, the mask layer64(seeFIG.5) may be patterned using acceptable photolithography and etching techniques to form masks74. An acceptable etching technique may be used to transfer the pattern of the masks74to the dummy gate layer62to form dummy gates72. In some embodiments, the pattern of the masks74may also be transferred to the dummy dielectric layers60. The dummy gates72cover respective channel regions68of the fins55. The pattern of the masks74may be used to physically separate each of the dummy gates72from adjacent dummy gates. The dummy gates72may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins55. The dummy dielectric layers60, the dummy gates72, and the masks74may be collectively referred to as “dummy gate stacks.”

InFIGS.7A and7B, a first spacer layer80and a second spacer layer82are formed over the structures illustrated inFIGS.6A and6B. InFIGS.7A and7B, the first spacer layer80is formed on top surfaces of the STI regions58, top surfaces and sidewalls of the fins55and the masks74, and sidewalls of the dummy gates72and the dummy dielectric layers60. The second spacer layer82is deposited over the first spacer layer80. The first spacer layer80may be formed by thermal oxidation or deposited by CVD, ALD, or the like. The first spacer layer80may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. The second spacer layer82may be deposited by CVD, ALD, or the like. The second spacer layer82may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

InFIGS.8A and8B, the first spacer layer80and the second spacer layer82are etched to form first spacers81and second spacers83. The first spacer layer80and the second spacer layer82may be etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like. The first spacers81and the second spacers83may be disposed on sidewalls of the fins55, the dummy dielectric layers60, the dummy gates72, and the masks74. The first spacers81and the second spacers83may have different heights adjacent the fins55and the dummy gate stacks due to the etching processes used to etch the first spacer layer80and the second spacer layer82, as well as differing heights between the fins55and the dummy gate stacks. Specifically, as illustrated inFIGS.8A and8B, in some embodiments, the first spacers81and the second spacers83may extend partially up sidewalls of the fins55and the dummy gate stacks. In some embodiments, the first spacers81and the second spacers83may extend to top surfaces of the dummy gate stacks.

After the first spacers81and the second spacers83are formed, implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above inFIG.4, a mask, such as a photoresist, may be formed over the region50N, while exposing the region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins55and the substrate50in the region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the region50P while exposing the region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins55and the substrate50in the region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities of from about 1×1015atoms/cm3to about 1×1019atoms/cm3. An anneal may be used to repair implant damage and to activate the implanted impurities.

It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers81may be formed prior to forming the second spacers83, additional spacers may be formed and removed, and/or the like). Furthermore, the n-type and p-type devices may be formed using a different structures and steps.

InFIGS.9A and9B, first recesses86are formed in the fins55and the substrate50. As illustrated inFIG.9A, top surfaces of the STI regions58may be level with top surfaces of the substrate50. The substrate50may be etched such that bottom surfaces of the first recesses86are disposed above or below the top surfaces of the STI regions58. The first recesses86may be formed by etching the fins55and the substrate50using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers81, the second spacers83, and the masks74mask portions of the fins55and the substrate50during the etching processes used to form the first recesses86. A single etch process or multiple etch processes may be used to form the first recesses86. Timed etch processes may be used to stop the etching of the first recesses86after the first recesses86reach a desired depth.

InFIGS.10A-10C, epitaxial source/drain regions92are formed in the first recesses86to exert stress on the channel regions68of the fins55, thereby improving performance. As illustrated inFIG.10B, the epitaxial source/drain regions92are formed in the first recesses86such that each dummy gate72is disposed between respective neighboring pairs of the epitaxial source/drain regions92. In some embodiments, the first spacers81are used to separate the epitaxial source/drain regions92from the dummy gates72by an appropriate lateral distance so that the epitaxial source/drain regions92do not short out subsequently formed gates of the resulting FinFETs.

The epitaxial source/drain regions92in the region50N, e.g., the NMOS region, may be formed by masking the region50P, e.g., the PMOS region. Then, the epitaxial source/drain regions92are epitaxially grown in the first recesses86. The epitaxial source/drain regions92may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fins55are silicon, the epitaxial source/drain regions92may include materials exerting a tensile strain on the fins55, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions92may have surfaces raised from respective surfaces of the fins55and may have facets.

The epitaxial source/drain regions92in the region50P, e.g., the PMOS region, may be formed by masking the region50N, e.g., the NMOS region. Then, the epitaxial source/drain regions92are epitaxially grown in the first recesses86. The epitaxial source/drain regions92may include any acceptable material, such as appropriate for p-type NSFETs. For example, if the fins55are silicon, the epitaxial source/drain regions92may comprise materials exerting a compressive strain on the fins55, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions92may also have surfaces raised from respective surfaces of the fins55and may have facets.

The epitaxial source/drain regions92, the fins55, and/or the substrate50may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×1019atoms/cm3and about 1×1021atoms/cm3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions92may be in situ doped during growth.

As a result of the epitaxy processes used to form the epitaxial source/drain regions92in the region50N and the region50P, upper surfaces of the epitaxial source/drain regions92have facets which expand laterally outward beyond sidewalls of the fins55. In some embodiments, these facets cause adjacent epitaxial source/drain regions92of a same FinFET to merge as illustrated byFIG.10A. In some embodiments, adjacent epitaxial source/drain regions92remain separated after the epitaxy process is completed as illustrated byFIG.10C. In the embodiments illustrated inFIGS.10A and10C, the first spacers81may be formed covering portions of the sidewalls of the fins55that extend above the STI regions58thereby blocking the epitaxial growth. In some embodiments, the spacer etch used to form the first spacers81may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region58.

InFIGS.11A and11B, a first interlayer dielectric (ILD)96is deposited over the structure illustrated inFIGS.6A and10B(the processes ofFIGS.7A-10Cdo not alter the cross-section illustrated inFIGS.6A, which illustrates the dummy gates72and the multi-layer stack56protected by the dummy gates72), respectively. The first ILD96may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)94is disposed between the first ILD96and the epitaxial source/drain regions92, the masks74, and the first spacers81. The CESL94may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD96.

InFIGS.12A and12B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD96with the top surfaces of the dummy gates72or the masks74. The planarization process may also remove the masks74on the dummy gates72, and portions of the first spacers81along sidewalls of the masks74. After the planarization process, top surfaces of the dummy gates72, the first spacers81, and the first ILD96are level. Accordingly, the top surfaces of the dummy gates72are exposed through the first ILD96. In some embodiments, the masks74may remain, in which case the planarization process levels the top surface of the first ILD96with top surface of the masks74and the first spacers81.

InFIGS.13A and13B, the dummy gates72, and the masks74if present, are removed in an etching step(s), so that second recesses98are formed. Portions of the dummy dielectric layers60in the second recesses98may also be removed. In some embodiments, only the dummy gates72are removed and the dummy dielectric layers60remain and are exposed by the second recesses98. In some embodiments, the dummy dielectric layers60are removed from second recesses98in a first region of a die (e.g., a core logic region) and remain in second recesses98in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates72are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates72at a faster rate than the first ILD96or the first spacers81. Each second recess98exposes and/or overlies a channel region68of a respective fin55. Each channel region68is disposed between neighboring pairs of the epitaxial source/drain regions92. During the removal, the dummy dielectric layer60may be used as an etch stop layer when the dummy gates72are etched. The dummy dielectric layer60may then be optionally removed after the removal of the dummy gates72.

FIGS.13C through13Eillustrate an embodiment in which the thinning process is performed to thin the fins55after removing the dummy gate stacks, rather than being performed after forming the fins55and before forming the STI regions58, as discussed above in reference toFIGS.3B and3C, or after forming the STI regions58, as discussed above in reference toFIG.4B. In the embodiment illustrated inFIGS.13C through13E, the fins55in the region50N may be exposed to etchants used to thin the fins55in the region50P and the fins55in the region50P may be exposed to etchants used to thin the fins55in the region50N.

In the embodiment illustrated inFIGS.13C through13E, the fins55in both the region50N and the region50P are exposed to the first etching chemicals and the second etching chemicals in processes the same as or similar to those described above with respect toFIG.3B. Following the first etching process, the fins55in the region50N may have the same dimensions as the fins55in the region50N discussed above with respect toFIG.4B. Following the second etching process, portions of the fins55in the region50P formed of the first epitaxial semiconductor material52may have the same dimensions as the portions of the fins55in the region50P formed of the first epitaxial semiconductor material52as discussed above with respect toFIG.4B.

As illustrated inFIGS.13D and13E, the thinning of the fins55may recess exposed portions of top surfaces of the fins55between the second spacers83. InFIG.13D, a recess is formed in a top portion of the fin55formed of the substrate50in the region50N. InFIG.13E, a recess is formed in a top portion of the fin55formed of the first epitaxial semiconductor material in the region50P. Depths of the recesses may be greatest at points between the second spacers83. The depths of the recesses may become shallower closer to the second spacer83. The fins55in the region50N may be recessed to a depth D2from about 2 nm to about 50 nm, from about 5 nm to about 15 nm, or from about 8 nm to about 12 nm below topmost surfaces of the fins55in the region50N. The fins55in the region50P may be recessed to a depth D3from about 2 nm to about 50 nm, from about 5 nm to about 15 nm, or from about 8 nm to about 12 nm below topmost surfaces of the fins55in the region50P.

Forming the fins55in the region50P having a gradient germanium concentration and thinning the fins55in the region50P using an etching process which has a higher etching rate with increasing germanium concentration results in the fins55in the region50P having more rectangular profiles and improves control of the process used to etch the fins55in the region50P. Including the fins55in FinFETs results in better gate control, reduced fin-width variation, and decreased DIBL.

FIGS.14A through14Cillustrate an embodiment in which the fins55are not thinned after removing the dummy gate stacks. InFIGS.14A and14B, gate dielectric layers100and gate electrodes102are formed for replacement gates.FIG.14Cillustrates a detailed view of region101ofFIG.14B. The gate dielectric layers100are deposited conformally in the second recesses98, such as on top surfaces and sidewalls of the fins55and the first spacers81and on top surfaces of the STI regions58, the first ILD96, the second spacers83, and the CESL94. In accordance with some embodiments, the gate dielectric layers100comprise silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric layers100include a high-k dielectric material, and in these embodiments, the gate dielectric layers100may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation methods of the gate dielectric layers100may include molecular-beam deposition (MBD), ALD, PECVD, or the like. In embodiments where portions of the dummy dielectric layers60remain in the second recesses98, the gate dielectric layers100include a material of the dummy dielectric layers60(e.g., SiO2).

The gate electrodes102are deposited over the gate dielectric layers100, respectively, and fill the remaining portions of the second recesses98. The gate electrodes102may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode102is illustrated inFIG.14B, the gate electrode102may comprise any number of liner layers102A, any number of work function tuning layers102B, and a fill material102C as illustrated byFIG.14C. After the filling of the second recesses98, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers100and the material of the gate electrodes102, which excess portions are over the top surface of the first ILD96. The remaining portions of material of the gate electrodes102and the gate dielectric layers100thus form replacement gates of the resulting FinFETs. The gate electrodes102and the gate dielectric layers100may be collectively referred to as “gate stacks.” The gate and the gate stacks may extend along sidewalls of the channel regions68of the fins55.

The formation of the gate dielectric layers100in the region50N and the region50P may occur simultaneously such that the gate dielectric layers100in each region are formed from the same materials, and the formation of the gate electrodes102may occur simultaneously such that the gate electrodes102in each region are formed from the same materials. In some embodiments, the gate dielectric layers100in each region may be formed by distinct processes, such that the gate dielectric layers100may be different materials, and/or the gate electrodes102in each region may be formed by distinct processes, such that the gate electrodes102may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

InFIGS.15A and15B, a second ILD106is deposited over the first ILD96. In some embodiments, the second ILD106is a flowable film formed by FCVD. In some embodiments, the second ILD106is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. In some embodiments, before the formation of the second ILD106, the gate stack (including the gate dielectric layers100and the corresponding overlying gate electrodes102) is recessed, so that a recess is formed directly over the gate stack and between opposing portions of first spacers81. A gate mask104comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD96. Subsequently formed gate contacts (such as the gate contacts112, discussed below with respect toFIGS.16A and16B) penetrate through the gate mask104to contact the top surface of the recessed gate electrodes102.

InFIGS.16A and16B, gate contacts112and source/drain contacts114are formed through the second ILD106and the first ILD96. Openings for the source/drain contacts114are formed through the first ILD96and the second ILD106and openings for the gate contacts112are formed through the second ILD106and the gate mask104. The openings may be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD106. The remaining liner and conductive material form the source/drain contacts114and the gate contacts112in the openings. An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions92and the source/drain contacts114. The source/drain contacts114are physically and electrically coupled to the epitaxial source/drain regions92, and the gate contacts112are physically and electrically coupled to the gate electrodes102. The source/drain contacts114and the gate contacts112may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts114and the gate contacts112may be formed in different cross-sections, which may avoid shorting of the contacts.

FIGS.16C through16Eillustrate the structures ofFIGS.16A and16Bin embodiments in which the fins55are thinned at various stages.FIG.16Cillustrates the embodiment ofFIG.3B, wherein the fins55are thinned simultaneously before forming the STI regions58. Portions of the fins55in the region50N formed above and below top surfaces of the STI regions58may have continuous sidewalls which are angled at the same angles with respect to a major surface of the substrate50. Portions of the fins55in the region50P formed above and below top surfaces of the STI regions58may have sidewalls which are angled at different angles with respect to a major surface of the substrate50. For example, as illustrated inFIG.16C, sidewalls of the portion of the fins55in the region50P above the top surfaces of the STI regions58and formed of the first epitaxial semiconductor material52may be more vertical than sidewalls of the portion of the fins55in the region50P below the top surfaces of the STI regions58and formed in the substrate50.

FIG.16Dillustrates the embodiment ofFIG.3C, wherein the fins55in the region50P are masked while thinning the fins55in the region50N and the fins55in the region50N are masked while thinning the fins55in the region50P. Portions of the fins55in the region50N formed above and below top surfaces of the STI regions58may have continuous sidewalls which are angled at a same angle with respect to a major surface of the substrate50. Portions of the fins55in the region50P formed in the first epitaxial semiconductor material52and formed in the substrate50may have sidewalls which are angled at different angles with respect to a major surface of the substrate50and which have a step difference in widths. For example, as illustrated inFIG.16D, sidewalls of the portions of the fins55in the region50P formed in the first epitaxial semiconductor material52may be more vertical than sidewalls of the portions of the fins55in the region50P formed in the substrate50. Moreover, there may be a step difference between widths of the portions of the fins55formed in the first epitaxial semiconductor material52and the portions of the fins55formed in the substrate50, with the portions of the fins55formed in the first epitaxial semiconductor material52having widths less than widths of the portions of the fins55formed in the substrate50.

FIG.16Eillustrates the embodiment ofFIGS.4B or13C through13E, wherein the fins55are thinned after forming the STI regions58or after removing the dummy gate stacks. Portions of the fins55in the region50N formed above and below top surfaces of the STI regions58may have sidewalls which are angled at different angles with respect to a major surface of the substrate50, and which have a step difference in widths. For example, as illustrated inFIG.16E, sidewalls of the portions of the fins55in the region50N formed below the top surfaces of the STI regions58may be more vertical than sidewalls of the portions of the fins55in the region50N formed above the top surfaces of the STI regions58. Moreover, there may be a step difference between widths of the portions of the fins55formed below the top surfaces of the STI regions58and the portions of the fins55formed above the top surfaces of the STI regions58, with the portions of the fins55formed below the top surfaces of the STI regions58having widths greater than widths of the portions of the fins55formed above the top surfaces of the STI regions58.

Portions of the fins55in the region50P formed above and below the top surfaces of the STI regions58may have sidewalls which are angled at different angles with respect to a major surface of the substrate50, and which have a step difference in widths. For example, as illustrated inFIG.16E, sidewalls of the portions of the fins55in the region50P formed above the top surfaces of the STI regions58(e.g., portions of the fins55formed in the first epitaxial semiconductor material52) may be more vertical than sidewalls of the portions of the fins55in the region50P formed below the top surfaces of the STI regions58(e.g., portions of the fins55formed in the substrate50). Moreover, there may be a step difference between widths of the portions of the fins55formed below the top surfaces of the STI regions58and the portions of the fins55formed above the top surfaces of the STI regions58, with the portions of the fins55formed below the top surfaces of the STI regions58having widths greater than widths of the portions of the fins55formed above the top surfaces of the STI regions58.

As discussed above, forming the fins55in the region50P having a gradient germanium concentration and thinning the fins55in the region50P using an etching process which has a higher etching rate with increasing germanium concentration results in the fins55in the region50P having more rectangular profiles and improves control of the process used to etch the fins55in the region50P. Including the fins55in FinFETs results in better gate control, reduced fin-width variation, and decreased DIBL.

FIG.17illustrates an example of nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), in accordance with some embodiments. The NSFETs comprise nanostructures255over a substrate250(e.g., a semiconductor substrate). The nanostructures255include second semiconductor layers254A-254C, which act as channel regions of the nanostructures255. Shallow trench isolation (STI) regions258are disposed in the substrate250, and the nanostructures255are disposed above and between neighboring STI regions258. Although the STI regions258are described/illustrated as being separate from the substrate250, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the STI regions.

Gate dielectric layers300are along top surfaces, sidewalls, and bottom surfaces of the nanostructures255, such as on top surfaces, sidewalls, and bottom surfaces of each of the second semiconductor layers254A-254C, and along top surfaces and sidewalls of portions of the substrate250. Gate electrodes302are over the gate dielectric layers300. Epitaxial source/drain regions292are disposed on opposite sides of the nanostructures255, the gate dielectric layers300, and the gate electrodes302.FIG.17further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode302and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions292of the NSFETs. Cross-section B-B′ is perpendicular to cross-section A-A′ and is along a longitudinal axis of a nanostructure255and in a direction of, for example, the current flow between the epitaxial source/drain regions292of the NSFETs. Cross-section C-C′ is parallel to cross-section A-A′ and extends through the epitaxial source/drain regions292of the NSFETs. Subsequent figures refer to these reference cross-sections for clarity.

FIGS.18through35Dare cross-sectional views of intermediate stages in the manufacturing of NSFETs, in accordance with some embodiments.FIGS.18,19A,19B,20A,20B,21,31D,35C, and35Dillustrate reference cross-section A-A′ illustrated inFIG.17, including a region250N and a region250P.FIGS.22A,29A,30A,31A,32A,32C,33A,33C,33E,34A, and35Aare illustrated along reference cross-section A-A′ illustrated inFIG.17in the region250N or the region250P.FIGS.22B,23B,24B,25B,26B,26C,27B,27C,28B,28C,29B,29C,30B,30C,31B,31C,31E,32B,32D,33B,33D,33F,34B, and35B are illustrated along a similar cross-section B-B′ illustrated inFIG.17.FIGS.23A,24A,25A,26A,27A,28A, and28D are illustrated along reference cross-section C-C′ illustrated inFIG.17.

InFIG.18, a substrate250is provided for forming NSFETs. The substrate250may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate250may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate250may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.

The substrate250has a region250N and a region250P. The region250N can be for forming n-type devices, such as NMOS transistors, e.g., n-type NSFETs. The region250P can be for forming p-type devices, such as PMOS transistors, e.g., p-type NSFETs. The region250N may be physically separated from the region250P (as illustrated by divider251), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the region250N and the region250P.

The substrate250may be lightly doped with a p-type or an n-type impurity. An anti-punch-through (APT) implantation may be performed on an upper portion of the substrate250to form an APT region253. During the APT implantation, dopants may be implanted in the region250N and the region250P. The dopants may have a conductivity type opposite a conductivity type of source/drain regions (such as the epitaxial source/drain regions292, discussed below with respect toFIGS.28A-28D) to be formed in each of the region250N and the region250P. The APT region253may extend under the subsequently formed source/drain regions in the resulting NSFETs, which will be formed in subsequent processes. The APT region253may be used to reduce the leakage from the source/drain regions to the substrate250. In some embodiments, the doping concentration in APT region253may be from about 1×1018atoms/cm3to about 1×1019atoms/cm3. For simplicity and legibility, the APT region253is not illustrated in subsequent drawings.

Further inFIG.18, a multi-layer stack256is formed over the substrate250. The multi-layer stack256includes alternating first semiconductor layers252and second semiconductor layers254of different semiconductor materials. The first semiconductor layers252may be formed of first semiconductor materials, which may include, for example, silicon germanium (SiGe) or the like. The second semiconductor layers254may be formed of second semiconductor materials, which may include, for example, silicon (Si), silicon carbon (SiC), or the like. In some embodiments, the first semiconductor layers252may be formed of the second semiconductor materials and the second semiconductor layers254may be formed of the first semiconductor materials. For purposes of illustration, the multi-layer stack256includes three of the first semiconductor layers252(e.g., first semiconductor layers252A-252C) and three of the second semiconductor layers254(e.g., second semiconductor layers254A-254C). In some embodiments, the multi-layer stack256may include any number of the first semiconductor layers252and the second semiconductor layers254. Each of the layers of the multi-layer stack256may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. Each of the first semiconductor layers252A-252C may have a thickness from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm. Each of the second semiconductor layers254A-254C may have a thickness from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm.

The first semiconductor layers252A-252C may be formed with gradient germanium concentrations. For example, in some embodiments, a germanium concentration of each of the first semiconductor layers252A-252C may be gradually and continuously decreased from a bottom surface of the layer to a top surface of the layer. An atomic percentage of germanium in the first semiconductor layer252A may range from about 90 percent at a bottom surface of the first semiconductor layer252A to about 40 percent at a top surface of the first semiconductor layer252A, from about 32 percent at the bottom surface of the first semiconductor layer252A to about 15 percent at the top surface of the first semiconductor layer252A, or the like. An atomic percentage of germanium in the first semiconductor layer252B may range from about 60 percent at a bottom surface of the first semiconductor layer252B to about 20 percent at a top surface of the first semiconductor layer252B, from about 25 percent at the bottom surface of the first semiconductor layer252B to about 8 percent at the top surface of the first semiconductor layer252B, or the like. An atomic percentage of germanium in the first semiconductor layer252C may range from about 50 percent at a bottom surface of the first semiconductor layer252C to about 0 percent at a top surface of the first semiconductor layer252C, from about 20 percent at the bottom surface of the first semiconductor layer252C to about 8 percent at the top surface of the first semiconductor layer252C, or the like.

In some embodiments, a ratio of the atomic percentage of germanium at the top surface of the each of the first semiconductor layers252A-252C to the atomic percentage of germanium at the bottom surface of each of the first semiconductor layers252A-252C may range from about 1:1 to about 1:4 or from about 1:2 to about 1:3. A ratio of the atomic percentage of germanium at the top surface of the first semiconductor layer252C to the atomic percentage of germanium at the bottom surface of the first semiconductor layer252A may range from about 1:2 to about 1:8 or from about 1:3 to about 1:5. As will be discussed in greater detail below, including the first semiconductor layers252A-252C with the prescribed ratios of atomic percentages of germanium results in nanostructures (such as the nanostructures255, discussed below with respect toFIGS.19A through20B) having improved rectangular profiles, which results in better gate control, reduced nanostructure-width variation, and decreased drain induced barrier loading.

In embodiments in which the first semiconductor layers252A-252C are deposited by CVD, the gradient germanium concentrations in the first semiconductor layers252A-252C may be achieved by gradually decreasing a flowrate of a germanium-containing precursor (e.g., germane (GeH4) or the like) relative to a flowrate of a silicon-containing precursor (e.g., dichlorosilane (H2Cl2Si), silane (SiH4), or the like) during the deposition of each of the first semiconductor layers252A-252C. For example, a ratio of a flowrate of a germanium precursor to a flowrate of a silicon precursor may be from about 1 to about 9 or from about 1 to about 3 at the beginning of the deposition process used to deposit the first semiconductor layer252A and a ratio of the flowrate of the germanium precursor to the flowrate of the silicon precursor may be from about 0 to about 1 or from about 0 to about 0.5 at the end of the deposition process used to deposit the first semiconductor layer252C.

For purposes of illustration, the second semiconductor layers254will be described as forming channel regions in the region250N and the first semiconductor layers252will be described as forming channel regions in the region250P in completed NSFET devices. The first semiconductor layers252may be sacrificial layers in the region250N and the second semiconductor layers254may be sacrificial layers in the region250P, which may be subsequently removed. In some embodiments, the first semiconductor layers252may form channel regions in the region250N and the region250P and the second semiconductor layers254may be sacrificial layers. In some embodiments, the second semiconductor layers254may form channel regions in the region250N and the region250P and the first semiconductor layers252may be sacrificial layers.

InFIG.19A, nanostructures255are formed in the multi-layer stack256and the substrate250is etched. In some embodiments, the nanostructures255may be formed by etching trenches in the multi-layer stack256and the substrate250. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic.

The nanostructures255and the substrate250may be patterned by any suitable method. For example, the nanostructures255and the substrate250may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructures255and the substrate250. In some embodiments, a mask (or other layer) may remain on the nanostructures255after patterning the nanostructures255and the substrate250. As illustrated inFIG.19A, the nanostructures255in both the region250N and the region250P may have tapered profiles in which widths at the bottoms of the nanostructures255are greater than widths at the top of the nanostructures255.

In the region250N, the nanostructures255may have a bottom width W18from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; a top width W19from about 2 nm to about 50 nm, from about 20 nm to about 30 nm, or from about 23 nm to about 27 nm; and a ratio of the top width W19to the bottom width W18from about 0.5 to about 2 or from about 0.7 to about 0.9. The nanostructures255in the region250N may be spaced with a pitch P3from about 2 nm to about 50 nm or from about 15 nm to about 25 nm. An angle θ9between sidewalls of the nanostructures255in the region250N and a top surface of the substrate250may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. In the region250P, the nanostructures255may have a bottom width W20from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; a top width W21from about 2 nm to about 50 nm, from about 20 nm to about 30 nm, or from about 23 nm to about 27 nm; and a ratio of the top width W21to the bottom width W20from about 0.5 to about 2 or from about 0.7 to about 0.9. The nanostructures255in the region250P may be spaced with a pitch P4from about 2 nm to about 50 nm or from about 15 nm to about 25 nm. An angle θ10between sidewalls of the nanostructures255in the region250P and a top surface of the substrate250may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. The nanostructures255in the region250N and the region250P may have heights H10from about 10 nm to about 200 nm or from about 70 nm to about 90 nm. The substrate250may be etched to a depth D1from about 30 nm to about 100 nm or from about 60 nm to about 70 nm below a top surface of the substrate250.

FIG.19Billustrates an embodiment in which a thinning process is performed to thin the nanostructures255after forming the nanostructures255and before STI regions (such as the STI regions258, discussed below with respect toFIG.20A). In the embodiment illustrated inFIG.19B, the nanostructures255in the region250N may be exposed to etchants used to thin the nanostructures255in the region250P and the nanostructures255in the region250P may be exposed to etchants used to thin the nanostructures in the region250N.

InFIG.19B, exposed portions of the second semiconductor layers254A-254C in the region250N and the region250P may be etched using first etching chemicals in a first etching process. During the first etching process, the first semiconductor layers252A-252C and the second semiconductor layers254A-254C in both the region250N and the region250P may be exposed to the first etching chemicals. A first etching selectivity, which is the ratio of the etching rate (sometimes referred to as the trimming rate) of the second semiconductor layers254A-254C (formed of, e.g., silicon) to the etching rate of the first semiconductor layers252A-252C (formed of, e.g., silicon germanium), is desired to be high in order to minimize the etching of the first semiconductor layers252A-252C. For example, the first etching selectivity may be higher than about 5, and may range from about 5 to about 20, or higher. The first etching process may be performed at a temperature ranging from about 5° C. to about 100° C., such as about room temperature (e.g. about 23° C.). The nanostructures255may be exposed to the first etching chemicals for a period ranging from about 10 seconds to about 5 minutes or from about 45 seconds to about 75 seconds.

In some embodiments, the first etching chemicals may include a first etchant dissolved in a first solvent. The first etching chemicals may be free from oxidants. The first etchant may include an alkaline or an acid. In embodiments in which the first etchant includes an alkaline, the first etchant may include a metal hydroxide (Mn+(OH−)n), amine derivatives, ammonium derivatives, combinations thereof, or the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivatives may include ammonia (NH3), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH, (CH3)4N(OH)), tetraethyl ammonium hydroxide (TEAH, (C2H5)4N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH3)3(C14H29)N(OH)), tetrabutylammonium hydroxide (TBAH, (C4H9)4N(OH)), combinations thereof, or the like. In embodiments in which the first etchant is an alkaline, a pH of the first etching chemicals may be from about 7 to about 13 or from about 8 to about 10. The first etchant may be present in the first etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

In embodiments in which the first etchant includes an acid, the first etchant may include hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H2SO4), phosphoric acid (H3PO4), nitric acid (HNO3), carboxylic acid derivatives (CnH2n+1COOH), combinations thereof, or the like. In embodiments in which the first etchant is an acid, a pH of the first etching chemicals may be from about 0 to about 7 or from about 1 to about 3. The first etchant may be present in the first etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

The first solvent may be utilized to help mix and deliver the first etchant. The first solvent may not participate in the etching reaction itself. In a particular embodiment the first etching solvent may be a solvent such as deionized water or the like. However, any suitable solvent may be utilized.

The first etching chemicals may further include ionic or nonionic surfactants such as quaternary ammonium (NR4+), sulfate (SO42−), sulfonate (R—SO3−), phosphate (—PO43−), carboxylates (R—COO−), alcohol ethoxylates, alkyl phenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, or the like, which may be added to reduce the surface tension of the first etching chemicals. The surfactants may be present in the first etching chemicals in a concentration ranging from about 0.0001 M to about 1 M or from about 0.0005 m to about 0.002 M.

Prior to etching the second semiconductor layers254A-254C with the first etching process, each of the second semiconductor layers254A-254C have tapered profiles in which widths at the bottom of the second semiconductor layers254A-254C are greater than widths at the top of the second semiconductor layers254A-254C (as discussed previously in the discussed related toFIG.19A). The first etching process may have the same etching rates at the top of the second semiconductor layers254A-254C and the bottom of the second semiconductor layers254A-254C, such that the second semiconductor layers254A-254C still have tapered profiles after etching the nanostructures255with the first etching process. The first etching process may etch top surfaces as well as sidewalls of the second semiconductor layers254C such that the second semiconductor layers254C have heights less than the second semiconductor layers254A-254B.

After the nanostructures255in the region250N and the region250P are etched with the first etching process, the second semiconductor layers254A-254B may have a height H13from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm and the second semiconductor layers254C may have a height H14from about 2 nm to about 30 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. In some embodiments, the widths of the nanostructures255may be different in the region250N and the region250P. For example, in the region250N, an average width W22of the second semiconductor layers254A may be from about 2.2 nm to about 80 nm, from about 12 nm to about 22 nm, or from about 15 nm to about 19 nm; an average width W23of the second semiconductor layers254B may be from about 2.2 nm to about 80 nm, from about 11 nm to about 21 nm, or from about 14 nm to about 18 nm; and an average width W24of the second semiconductor layers254C may be from about 2.2 nm to about 80 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. A ratio of the width W24to the width W23may be from about 0.5 to about 2 or from about 0.8 to about 1.0, a ratio of the width W23to the width W22may be from about 0.5 to about 2 or from about 0.8 to about 1.0, and a ratio of the width W24to the width W22may be from about 0.25 to about 4 or from about 0.64 to about 1.0. In the region250P, an average width W25of the second semiconductor layers254A may be from about 2.2 nm to about 80 nm, from about 12 nm to about 22 nm, or from about 15 nm to about 19 nm; an average width W26of the second semiconductor layers254B may be from about 2.2 nm to about 80 nm, from about 11 nm to about 21 nm, or from about 14 nm to about 18 nm; and an average width W27of the second semiconductor layers254C may be from about 2.2 nm to about 80 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. A ratio of the width W27to the width W26may be from about 0.5 to about 2 or from about 0.8 to about 1.0 and a ratio of the width W26to the width W25may be from about 0.5 to about 2 or from about 0.8 to about 1.0.

Portions of the nanostructures255formed in the substrate250in the region250N may have a bottom width W30from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm and a top width W31from about 2.2 nm to about 80 nm, from about 13 nm to about 23 nm, or from about 16 nm to about 20 nm. A ratio of the top width W31to the bottom width W30may be from about 0.5 to about 2 or from about 0.8 to about 1.0. An angle θ11between sidewalls of the portions of the nanostructures255formed in the substrate250in the region250N and a top surface of the substrate250may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. Portions of the nanostructures255formed in the substrate250in the region250P may have a bottom width W32from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm and a top width W33from about 2.2 nm to about 80 nm, from about 13 nm to about 23 nm, or from about 15 nm to about 20 nm. An angle θ12between sidewalls of the portions of the nanostructures255formed in the substrate250in the region250P and a top surface of the substrate250may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. A ratio of the top width W33to the bottom width W32may be from about 0.5 to about 2 or from about 0.8 to about 1.0.

Further inFIG.19B, exposed portions of the first semiconductor layers252A-252C in the region250N and the region250P may be etched using second etching chemicals in a second etching process separate from the first etching process. During the second etching process, the first semiconductor layers252A-252C and the second semiconductor layers254A-254C in both the region250N and the region250P may be exposed to the second etching chemicals. A second etching selectivity, which is the ratio of the etching rate (sometimes referred to as the trimming rate) of the first semiconductor layers252A-252C (formed of, e.g., silicon germanium) to the etching rate of the second semiconductor layers254A-254C (formed of, e.g., silicon), is desired to be high in order to minimize the etching of the second semiconductor layers254A-254C. For example, the second etching selectivity may be higher than about 5, and may range from about 5 to about 20, or higher. The second etching process may be performed at a temperature ranging from about 5° C. to about 100° C., such as about room temperature (e.g. about 23° C.).

In some embodiments, the second etching chemicals may include an oxidant and a second etchant dissolved in a second solvent. The nanostructures55may be exposed to the oxidant and the second etchant simultaneously. In the embodiments in which the nanostructures255are exposed to the oxidants and the second etchants simultaneously, the nanostructures255may be exposed to the second etching chemicals for a period from about 30 seconds to about 2 minutes or from about 45 seconds to about 75 seconds. In some embodiments, the second etchant may be the same as the first etchant. The second etchant may be an alkaline or an acid.

In embodiments in which the second etchant includes an alkaline, the second etchant may include a metal hydroxide (Mn+(OH−)n), amine derivatives, ammonium derivatives, combinations thereof, or the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivatives may include ammonia (NH3), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH, (CH3)4N(OH)), tetraethyl ammonium hydroxide (TEAH, (C2H5)4N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH3)3(C14H29)N(OH)), tetrabutylammonium hydroxide (TBAH, (C4H9)4N(OH)), combinations thereof, or the like. In embodiments in which the second etchant is an alkaline, a pH of the second etching chemicals may be from about 7 to about 13 or from about 8 to about 10. The second etchant may be present in the second etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

In embodiments in which the second etchant includes an acid, the second etchant may include hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H2SO4), phosphoric acid (H3PO4), nitric acid (HNO3), carboxylic acid derivatives (CnH2n+1COOH), combinations thereof, or the like. In embodiments in which the second etchant is an acid, a pH of the second etching chemicals may be from about 0 to about 7 or from about 1 to about 3. The second etchant may be present in the second etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

The oxidant may include ozonated de-ionized water (DIO3), hydrogen peroxide (H2O2), other non-metal oxidants, combinations thereof, or the like. An oxidizing agent may be present in the second etching chemicals in a concentration ranging from about 0.0001 M to about 1 M or from about 0.0005 m to about 0.002 M. Including the oxidant in addition to the second etchant allows the first semiconductor layers252A-252C to be etched selectively with respect to the second semiconductor layers254A-254C. The oxidant may be used to oxidize the first semiconductor layers252A-252C, forming silicon germanium oxide in the first semiconductor layers252A-252C, and the second etchant may then be used to etch the silicon germanium oxide material, thinning the first semiconductor layers252A-252C. On the other hand, in the region250N, the oxidant may be used to oxidize the second semiconductor layers254A-254C, forming silicon oxide in the second semiconductor layers254A-254C, which is etched at a slower rate by the second etchant. Silicon may also be oxidized at a slower rate than silicon germanium, such that any silicon oxide layer formed in the second semiconductor layers254A-254C is thinner than an oxide formed in the first semiconductor layers252A-252C. Accordingly, the second semiconductor layers254A-254C are substantially un-thinned, while the first semiconductor layers252A-252C are thinned.

The second solvent may be utilized to help mix and deliver the oxidant and the second etchant. The second solvent may not participate in the etching reaction itself. In a particular embodiment the second etching solvent may be a solvent such as deionized water, acetic acid (CH3COOH), or the like. In embodiments in which the oxidant includes ozonated deionized water, the deionized water may also act as a solvent. Any suitable solvents may be utilized.

The second etching chemicals may further include ionic or nonionic surfactants such as quaternary ammonium (NR4+), sulfate (SO42−), sulfonate (R—SO3−), phosphate (—PO43−), carboxylates (R—COO−), alcohol ethoxylates, alkyl phenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, or the like, which may be added to reduce the surface tension of the second etching chemicals. The surfactants may be present in the second etching chemicals in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.

In a specific embodiment, the second etching chemicals may include hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH). The acetic acid may be a solvent in which the hydrofluoric acid and the hydrogen peroxide dissolved. The hydrogen peroxide may be an oxidant, which is used to oxidize the first semiconductor layers252A-252C. The hydrofluoric acid may be a second etchant which is used to thin the first semiconductor layers252A-252C. A volume ratio of hydrofluoric acid:hydrogen peroxide:acetic acid may be about 1:2:3.

In further embodiments, the nanostructures255may be exposed to the oxidant, then the oxidant may be removed and the nanostructures255may be exposed to the second etchant in a cyclical process to thin the second semiconductor layers254A-254C of the nanostructures255. Exposing the nanostructures255to the oxidant may oxidize the nanostructures255in the region250N and the region250P. Exposing the nanostructures255to the second etchant may selectively etch the oxide formed in the first semiconductor layers252A-252C relative to the oxide formed in the second semiconductor layers254A-254C.

The oxidant used in the cyclical process may be the same as those described above as being used in the process in which the nanostructures255are exposed to the oxidant and the second etchant simultaneously. For example, the oxidant may include ozonated de-ionized water (DIO3), hydrogen peroxide (H2O2), other non-metal oxidants, combinations thereof, or the like. An oxidizing agent may be present in the oxidant in a concentration ranging from about 0.0001 M to about 1 M or from about 0.0005 m to about 0.002 M. As discussed previously, exposing the nanostructures255may oxidize the first semiconductor layers252A-252C. The second semiconductor layers254A-254C may also be oxidize, but may be oxidized at a slower rate than the first semiconductor layers252A-252C.

The second etchant used in the cyclical process may be the same as or similar to the first etchant. The second etchant may be present in a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M. Exposing the nanostructures255to the second etchant thins the second semiconductor layers254A-254C. As discussed previously, the first semiconductor layers252A-252C may be thinned at a slower rate than the second semiconductor layers254A-254C.

For each cycle, the nanostructures255may be exposed to the oxidant for a period ranging from about 10 seconds to about 5 minutes or from about 45 seconds to about 75 seconds and the nanostructures255may be exposed to the second etchant for a period ranging from about 10 seconds to about 5 minutes or from about 45 seconds to about 75 seconds. The cyclical etching process may be repeated for up to 20 cycles, up to 10 cycles, 4 to 6 cycles, or the like. Exposing the nanostructures255to the oxidant, then the second etchant in a cyclical process may provide better control of the etching of the first semiconductor layers252A-252C. This results in improved gate control of resulting NSFETs, reduces the nanostructure-width variation, and leads to decreased DIBL.

The second etching process may have etching rates which depend on the concentration of germanium in the first semiconductor layers252A-252C. For example, the second etching process may have higher etching rates with increasing germanium concentration in the first semiconductor layers252A-252C. As discussed previously in the discussion related toFIG.18, each of the first semiconductor layers252A-252C may have a gradient germanium concentration in which the germanium concentration is higher at the bottom surface of the respective first semiconductor layer252A-252C and gradually and continually decreases towards the top surface of the respective first semiconductor layer252A-252C. Thus, bottom portions of the first semiconductor layers252A-252C may be etched by the second etching process with higher etching rates than top portions of the first semiconductor layers252A-252C. A ratio of the etching rate at the bottom surface of the first semiconductor layer252A (e.g., a maximum etching rate) to the etching rate at the top surface of the first semiconductor layer252C (e.g., a minimum etching rate) may be from about 0.5 to about 2 or from about 0.75 to about 1.25.

Prior to etching the first semiconductor layers252A-252C with the second etching process, the first semiconductor layers252A-252C have tapered profiles in which widths at the bottom of each of the first semiconductor layers252A-252C are greater than widths at the top of each of the first semiconductor layers252A-252C (as discussed previously in the discussed related toFIG.19A). Etching the first semiconductor layers252A-252C with the second etching process which has a higher etching rate at the bottom of each of the first semiconductor layers252A-252C than the top of each of the first semiconductor layers252A-252C results in the first semiconductor layers252A-252C having a more rectangular profile after etching the first semiconductor layers252A-252C with the second etching process.

After the first semiconductor layers252A-252C are etched with the second etching process, each of the first semiconductor layers252A-252C in the region250N may an average width W28from about 2.2 nm to about 80 nm, from about 23 nm to about 33 nm, or from about 26 nm to about 30 nm. A ratio of the width W28of the top first semiconductor layers252C to the bottom first semiconductor layers252A may be from about 0.8 to about 1.2 or from about 0.9 to about 1.1. Each of the first semiconductor layers252A-252C in the region250P may an average width W29from about 2.2 nm to about 80 nm, from about 23 nm to about 33 nm, or from about 26 nm to about 30 nm. A ratio of the width W29of the top first semiconductor layers252C to the bottom first semiconductor layers252A may be from about 0.8 to about 1.2 or from about 0.9 to about 1.1. Each of the first semiconductor layers252A-252C in the region250N and the region250P may have a height His from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm.

Forming the first semiconductor layers252A-252C having a gradient germanium concentration and thinning the first semiconductor layers252A-252C using an etching process which has a higher etching rate with increasing germanium concentration results in the first semiconductor layers252A-252C having more rectangular profiles and improves control of the process used to etch the first semiconductor layers252A-252C. Including the first semiconductor layers252A-252C in NSFETs results in better gate control, reduced nanostructure-width variation, and decreased DIBL.

FIG.20Aillustrates an embodiment in which the nanostructures255are not thinned until after shallow trench isolation (STI) regions258are formed. For example, the thinning process may be performed after the formation of the STI regions258, as will be discussed below with respect toFIG.20B, or after the removal of dummy gate stacks (such as dummy gate stacks including the dummy gates272and the dummy dielectric layers260, discussed below with respect toFIGS.22A and22B), as will be discussed below with respect toFIGS.31D and31E. However, it should be understood that the steps performed inFIG.20Aand subsequent figures may be performed on nanostructures255which have been thinned as described above in reference toFIG.19B.

InFIG.20A, shallow trench isolation (STI) regions258are formed adjacent the nanostructures255and the patterned portions of the substrate250. The STI regions258may be formed by forming an insulation material (not separately illustrated) over the substrate250and between neighboring nanostructures255/patterned portions of the substrate250. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system with post curing to convert the deposited material to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In some embodiments, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In some embodiments, the insulation material is formed such that excess insulation material covers the nanostructures255. The insulation material may comprise a single layer or may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along surfaces of the substrate250and the nanostructures255. Thereafter, a fill material, such as those discussed above may be formed over the liner.

A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures255. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process may planarize the insulation material and the nanostructures255. The planarization process exposes the nanostructures255such that top surfaces of the nanostructures255and the insulation material are level after the planarization process is complete.

The insulation material is then recessed to form the STI regions258as illustrated inFIG.20A. The insulation material is recessed such that upper portions of the nanostructures255and the substrate250protrude from between neighboring STI regions258. Further, the top surfaces of the STI regions258may have flat surfaces as illustrated, convex surfaces, concave surfaces (such as dishing), or a combination thereof. The top surfaces of the STI regions258may be formed flat, convex, and/or concave by an appropriate etch. The STI regions258may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the nanostructures255and the substrate250). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. A height H12of the STI regions258may be from about 30 nm to about 100 nm or from about 55 nm to about 75 nm.

FIG.20Billustrates an embodiment in which the thinning process is performed to thin the nanostructures255after forming the STI regions258, rather than being performed after forming the nanostructures255and before forming the STI regions258, as discussed above in reference toFIG.19B. In the embodiment illustrated inFIG.20B, the nanostructures255in the region250N may be exposed to etchants used to thin the nanostructures255in the region250P and the nanostructures255in the region250P may be exposed to etchants used to thin the nanostructures255in the region250N.

In the embodiment illustrated inFIG.20B, the nanostructures255in both the region250N and the region250P are exposed to the first etching chemicals and the second etching chemicals in processes the same as or similar to those described above with respect toFIG.19B. Following the first etching process, the second semiconductor layers254A-254C in the region250N and the region250P may have the same or similar dimensions as the second semiconductor layers254A-254C discussed above with respect toFIG.19B. Following the second etching process, the first semiconductor layers252A-252C in the region250N and the region250P may have the same or similar dimensions as the first semiconductor layers252A-252C as discussed above with respect toFIG.19B. For example, the dimensions of the first semiconductor layers252A-252C and the dimensions of the second semiconductor layers254A-254C may be within about 10 nm of the dimensions discussed above with respect toFIG.19B.

Forming the first semiconductor layers252A-252C having a gradient germanium concentration and thinning the first semiconductor layers252A-252C using an etching process which has a higher etching rate with increasing germanium concentration results in the first semiconductor layers252A-252C having more rectangular profiles and improves control of the process used to etch the first semiconductor layers252A-252C. Including the first semiconductor layers252A-252C in NSFETs results in better gate control, reduced nanostructure-width variation, and decreased DIBL.

Portions of the nanostructures255in the region250N and the region250P surrounded by the STI regions258may remain unchanged after the thinning process is performed. For example, portions of the nanostructures255disposed below top surfaces of the STI regions258may have widths similar to or the same as those discussed above with respect toFIG.19A. As illustrated inFIG.20B, there may be a step change in the widths of the nanostructures255level with the top surfaces of the STI regions258due to the thinning process.

FIG.21illustrates an embodiment in which the nanostructures255are not thinned until after dummy gates stacks (such as dummy gate stacks including the dummy gates272and the dummy dielectric layers260, discussed below with respect toFIGS.22A and22B) are formed. For example, the thinning process may be performed after the removal of the dummy gate stacks, as will be discussed below with respect toFIGS.31D and31E. However, it should be understood that the steps performed inFIG.21and subsequent figures may be performed on nanostructures255which have been thinned as described above in reference toFIG.19B or20B.

InFIG.21, dummy dielectric layers260are formed on the nanostructures255and the substrate250. The dummy dielectric layers260may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer262is formed over the dummy dielectric layers260, and a mask layer264is formed over the dummy gate layer262. The dummy gate layer262may be deposited over the dummy dielectric layers260and then planarized by a process such as CMP. The mask layer264may be deposited over the dummy gate layer262. The dummy gate layer262may be conductive or non-conductive materials and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer262may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing the selected material. The dummy gate layer262may be made of other materials that have a high etching selectivity from the material of the STI regions258. The mask layer264may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer262and a single mask layer264are formed across the region250N and the region250P. It is noted that the dummy dielectric layers260are shown covering only the nanostructures255and the substrate250for illustrative purposes only. In some embodiments, the dummy dielectric layers260may be deposited such that the dummy dielectric layers260cover the STI regions258, extending between the dummy gate layer262and the STI regions258.

FIGS.22A through35Dillustrate various additional steps in the manufacturing of embodiment devices.FIGS.22A through25B,26A,27A,28A,28D,29A,30A,31A,31E,34A, and35Aillustrate features in either of the region250N or the region250P. For example, the structures illustrated inFIGS.22A through25B,26A,27A,28A,28D,29A,30A,31A,31E,34A, and35Amay be applicable to both the region250N and the region250P. Differences (if any) in the structures of the region250N and the region250P are described in the text accompanying each figure. For example, theFIGS.26B,27B,28B,29B,30B,31B,32A,32B,33A,33B,33E,33F,34B, and35Billustrate structures in the region250N,FIGS.26C,27C,28C,29C,30C,31C,32C,32D,33C, and33Dillustrate structures in the region250P, andFIGS.31D,35C, and35Dillustrate structures in the region250N and the region250P.

InFIGS.22A and22B, the mask layer264(seeFIG.21) may be patterned using acceptable photolithography and etching techniques to form masks274. An acceptable etching technique may be used to transfer the pattern of the masks274to the dummy gate layer262to form dummy gates272. In some embodiments, the pattern of the masks274may also be transferred to the dummy dielectric layers260. The dummy gates272cover respective channel regions of the nanostructures255. In some embodiments, the channel regions may be formed in the second semiconductor layers254A-254C including the second semiconductor materials in the region250N and the channel regions may be formed in the first semiconductor layers252A-252C including the first semiconductor materials in the region250P. The pattern of the masks274may be used to physically separate each of the dummy gates272from adjacent dummy gates272. The dummy gates272may have a lengthwise direction substantially perpendicular to lengthwise directions of respective nanostructures255. The dummy dielectric layers260, the dummy gates272, and the masks274may be collectively referred to as “dummy gate stacks.”

InFIGS.23A and23B, a first spacer layer280and a second spacer layer282are formed over the structures illustrated inFIGS.22A and22B. InFIGS.23A and23B, the first spacer layer280is formed on top surfaces of the STI regions258, top surfaces and sidewalls of the nanostructures255and the masks274, and sidewalls of the substrate250, the dummy gates272and the dummy dielectric layers260. The second spacer layer282is deposited over the first spacer layer280. The first spacer layer280may be formed by thermal oxidation or deposited by CVD, ALD, or the like. The first spacer layer280may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. The second spacer layer282may be deposited by CVD, ALD, or the like. The second spacer layer282may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

InFIGS.24A and24B, the first spacer layer280and the second spacer layer282are etched to form first spacers281and second spacers283. The first spacer layer280and the second spacer layer282may be etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like. The first spacers281and the second spacers283may be disposed on sidewalls of the nano structures255, the dummy dielectric layers260, the dummy gates272, and the masks274. The first spacers281and the second spacers283may have different heights adjacent the nanostructures255and the dummy gate stacks due to the etching processes used to etch the first spacer layer280and the second spacer layer282, as well as differing heights between the nanostructures255and the dummy gate stacks. Specifically, as illustrated inFIGS.24A and24B, in some embodiments, the first spacers281and the second spacers283may extend partially up sidewalls of the nanostructures255and may extend to top surfaces of the dummy gate stacks. In some embodiments, the first spacers281and the second spacers283may extend partially up sidewalls of the dummy gate stacks. For example, top surfaces of the first spacers281and the second spacers283may be disposed above top surfaces of the dummy gates272and below top surfaces of the masks274.

InFIGS.25A and25B, first recesses286are formed in the nanostructures255and the substrate250. The first recesses286may extend through the first semiconductor layers252A-252C and the second semiconductor layers254A-254C. In some embodiments, the first recesses286may also extend into the substrate250. As illustrated inFIG.25A, top surfaces of the STI regions258may be level with top surfaces of the substrate250. In some embodiments, the substrate250may be etched such that bottom surfaces of the first recesses286are disposed below the top surfaces of the STI regions258or the like. The first recesses286may be formed by etching the nanostructures255and/or the substrate250using one or more anisotropic etching processes, such as RIE, NBE, or the like. The first spacers281, the second spacers283, and the masks274mask portions of the nanostructures255and the substrate250during the etching processes used to form the first recesses286. A single etch process may be used to etch each layer of the multi-layer stack256. In some embodiments, multiple etch processes may be used to etch the layers of the multi-layer stack256. Timed etch processes may be used to stop the etching of the first recesses286after the first recesses286reach a desired depth.

InFIGS.26A through26C, portions of sidewalls of the first semiconductor layers252A-252C and the second semiconductor layers254A-254C of the multi-layer stack256are etched to form sidewall recesses288. For example, as illustrated inFIGS.26B and26C, respectively, sidewalls of the first semiconductor layers252A-252C in the region250N formed of the first semiconductor materials and sidewalls of the second semiconductor layers254A-254C in the region250P formed of the second semiconductor materials are etched to form the sidewall recesses288. A mask, such as a photoresist, may be formed over the region250P, while sidewall recesses288are formed in the first semiconductor layers252A-252C in the region250N. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the region250N while sidewall recesses288are formed in the second semiconductor layers254A-254C in the region250P. The mask may then be removed.

Although sidewalls of the first semiconductor layers252A-252C and the second semiconductor layers254A-254C adjacent the sidewall recesses288are illustrated as being straight inFIGS.26B and26C, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching, dry etching, or the like. The etchants used to etch the first semiconductor layers252A-252C may be selective to the first semiconductor materials such that the second semiconductor layers254A-254C and the substrate250remain relatively unetched as compared to the first semiconductor layers252A-252C. Similarly, the etchants used to etch the second semiconductor layers254A-254C may be selective to the second semiconductor materials such that the first semiconductor layers252A-252C and the substrate250remain relatively unetched as compared to the second semiconductor layers254A-254C.

InFIGS.27A through27C, first inner spacers290are formed in the sidewall recess288. The first inner spacers290may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated inFIGS.26A through26C. The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be etched to form the first inner spacers290. Although outer sidewalls of the first inner spacers290are illustrated as being flush with sidewalls of the second semiconductor layers254A-254C inFIG.27Band the first semiconductor layers252A-252C inFIG.27C, the outer sidewalls of the first inner spacers290may extend beyond or be recessed from sidewalls of the second semiconductor layers254A-254C and the first semiconductor layers252A-252C. Moreover, although the outer sidewalls of the first inner spacers290are illustrated as being straight inFIGS.27B and27C, the outer sidewalls of the first inner spacers290may be concave or convex. The inner spacer layer may be etched by an anisotropic etching process, such as RIE, NBE, or the like.

The first inner spacers290may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions292, discussed below with respect toFIGS.28A through28D) by subsequent etching processes. The first inner spacers290may also insulate subsequently formed gate electrodes (such as the gate electrodes302, discussed below with respect toFIGS.33A through33F) from the subsequently formed epitaxial source/drain regions292, which may prevent shorts in the resulting NSFETs.

InFIGS.28A through28D, epitaxial source/drain regions292are formed in the first recesses286to exert stress on the second semiconductor layers254A-254C and the first semiconductor layers252A-252C of the nanostructures255, thereby improving performance. As illustrated inFIGS.28B and28C, the epitaxial source/drain regions292are formed in the first recesses286such that each dummy gate272is disposed between respective neighboring pairs of the epitaxial source/drain regions292. In some embodiments, the first spacers281are used to separate the epitaxial source/drain regions292from the dummy gates272by an appropriate lateral distance so that the epitaxial source/drain regions292do not short out subsequently formed gates of the resulting NSFETs.

The epitaxial source/drain regions292in the region250N, e.g., the NMOS region, may be formed by masking the region250P, e.g., the PMOS region. Then, the epitaxial source/drain regions292are epitaxially grown in the first recesses286. The epitaxial source/drain regions292may include any acceptable material, such as appropriate for n-type NSFETs. For example, if the second semiconductor layers254A-254C are silicon, the epitaxial source/drain regions292may include materials exerting a tensile strain on the second semiconductor layers254A-254C, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions292may have surfaces raised from respective surfaces of the multi-layer stack256and may have facets.

The epitaxial source/drain regions292in the region250P, e.g., the PMOS region, may be formed by masking the region250N, e.g., the NMOS region. Then, the epitaxial source/drain regions292are epitaxially grown in the first recesses286. The epitaxial source/drain regions292may include any acceptable material, such as appropriate for p-type NSFETs. For example, if the second semiconductor layers254A-254C are silicon germanium, the epitaxial source/drain regions292may comprise materials exerting a compressive strain on the second semiconductor layers254A-254C, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions292may also have surfaces raised from respective surfaces of the multi-layer stack256and may have facets.

The epitaxial source/drain regions292may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1×1019atoms/cm3and about 1×1021atoms/cm3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions292may be in situ doped during growth.

As a result of the epitaxy processes used to form the epitaxial source/drain regions292in the region250N and the region250P, upper surfaces of the epitaxial source/drain regions292have facets which expand laterally outward beyond sidewalls of the nanostructures255. In some embodiments, these facets cause adjacent epitaxial source/drain regions292of a same NSFET to merge as illustrated byFIG.28A. In some embodiments, adjacent epitaxial source/drain regions292remain separated after the epitaxy process is completed as illustrated byFIG.28D. In the embodiments illustrated inFIGS.28A and28D, the first spacers281may be formed covering portions of the sidewalls of the nanostructures255and the substrate250that extend above the STI regions258thereby blocking the epitaxial growth. In some embodiments, the spacer etch used to form the first spacers281may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region258.

InFIGS.29A through29C, a first interlayer dielectric (ILD)296is deposited over the structure illustrated inFIGS.22A,28B, and28C(the processes ofFIGS.23A through28Ddo not alter the cross-section illustrated inFIG.22A, which illustrates the dummy gates272and the multi-layer stack256protected by the dummy gates272), respectively. The first ILD296may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)294is disposed between the first ILD296and the epitaxial source/drain regions292, the masks274, and the first spacers281. The CESL294may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD296.

InFIGS.30A through30C, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD296with the top surfaces of the dummy gates272or the masks274. The planarization process may also remove the masks274on the dummy gates272, and portions of the first spacers281along sidewalls of the masks274. After the planarization process, top surfaces of the dummy gates272, the first spacers281, and the first ILD296are level. Accordingly, the top surfaces of the dummy gates272are exposed through the first ILD296. In some embodiments, the masks274may remain, in which case the planarization process levels the top surface of the first ILD296with top surface of the masks274and the first spacers281.

InFIGS.31A through31C, the dummy gates272, and the masks274if present, are removed in an etching step(s), so that second recesses298are formed. Portions of the dummy dielectric layers260in the second recesses298may also be removed. In some embodiments, the dummy gates272are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates272at a faster rate than the first ILD296or the first spacers281. Each second recess298exposes and/or overlies portions of the multi-layer stack256, which act as channel regions in subsequently completed NSFETs. Portions of the multi-layer stack256which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions292. During the removal, the dummy dielectric layers260may be used as etch stop layers when the dummy gates272are etched. The dummy dielectric layers260may then be removed after the removal of the dummy gates272.

FIGS.31D and31Eillustrate an embodiment in which the thinning process is performed to thin the nanostructures255after removing the dummy gate stacks, rather than being performed after forming the nanostructures255and before forming the STI regions258, as discussed above in reference toFIG.19B, or after forming the STI regions258, as discussed above in reference toFIG.20B. In the embodiment illustrated inFIGS.31D and31E, the nanostructures255in the region250N may be exposed to etchants used to thin the nanostructures255in the region250P and the nanostructures255in the region250P may be exposed to etchants used to thin the nanostructures255in the region250N.

In the embodiment illustrated inFIGS.31D and31E, the nanostructures255in both the region250N and the region250P are exposed to the first etching chemicals and the second etching chemicals in processes the same as or similar to those described above with respect toFIG.19B. Following the first etching process, the second semiconductor layers254A-254C in the region250N and the region250P may have the same dimensions as the second semiconductor layers254A-254C discussed above with respect toFIG.19B. Following the second etching process, the first semiconductor layers252A-252C in the region250N and the region250P may have the same dimensions as the first semiconductor layers252A-252C as discussed above with respect toFIG.19B.

As illustrated inFIG.31E, the thinning of the nanostructures255may recess exposed portions of top surfaces of the second semiconductor layers254C between the second spacers283. InFIG.31E, recesses are formed in top portions of the second semiconductor layer254C. Depths of the recesses may be greatest at points between the second spacers283. The depths of the recesses may become shallower closer to the second spacer283. The second semiconductor layers254C may be recessed to a depth D4from about 5 nm to about 40 nm, from about 5 nm to about 15 nm, or from about 8 nm to about 12 nm below topmost surfaces of the second semiconductor layers254C in both the region250N and the region250P.

Forming the first semiconductor layers252A-252C having a gradient germanium concentration and thinning the first semiconductor layers252A-252C using an etching process which has a higher etching rate with increasing germanium concentration results in the first semiconductor layers252A-252C having more rectangular profiles and improves control of the process used to etch the first semiconductor layers252A-252C. Including the first semiconductor layers252A-252C in NSFETs results in better gate control, reduced nanostructure-width variation, and decreased DIBL.

FIGS.32A through32Dillustrate an embodiment in which the nanostructures255are not thinned after removing the dummy gate stacks. InFIGS.32A through32D, the first semiconductor layers252A-252C are removed from the region250N and the second semiconductor layers254A-254C are removed from the region250P, extending the second recesses298. A mask, such as a photoresist, may be formed over the region250P, while removing the first semiconductor layers252A-252C from the region250N. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the region250N while removing the second semiconductor layers254A-254C from the regions250P. The mask may then be removed.

The layers of the multi-layer stack256may be removed by isotropic etching processes such as wet etching or the like. The etchants used to remove the first semiconductor layers252A-252C may be selective to the materials of the second semiconductor layers254A-254C, while the etchants used to etch the second semiconductor layers254A-254C may be selective to the materials of the first semiconductor layers252A-252C. In an embodiment in which the first semiconductor layers252A-252C comprise the first semiconductor material (e.g., SiGe or the like) and the second semiconductor layers254A-254C comprise the second semiconductor material (e.g., Si, SiC, or the like), tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used remove layers of the multi-layer stack256in the regions250N and diluted ammonium hydroxide-hydrogen peroxide mixture (APM), sulfuric acid-hydrogen peroxide mixture (SPM), or the like may be used to remove layers of the multi-layer stack256in the region250P. A plasma, such as a plasma formed from hydrogen gas (H2) or the like, may be used to remove the first semiconductor layers252A-252C. A solution including hydrofluoric acid (HF) and hydrogen peroxide (H2O2), a solution including hydrofluoric acid, nitric acid (HNO3), and water (H2O), or the like may be used to remove the second semiconductor layers254A-254C.

InFIGS.33A through33D, gate dielectric layers300and gate electrodes302are formed for replacement gates.FIG.33Eillustrates a detailed view of region301ofFIG.33AandFIG.33Fillustrates a detailed view of region303ofFIG.33B. In the region250N illustrated inFIGS.33A and33B, the gate dielectric layers300are deposited conformally in the second recesses298, such as on top surfaces of the STI regions258, on top surfaces of the substrate250, and on top surfaces, sidewalls, and bottom surfaces of the second semiconductor layers254A-254C. In the region250P, illustrated inFIGS.33C and33D, the gate dielectric layers300are deposited conformally in the second recesses298, such as on top surfaces of the STI regions258and on top surfaces, sidewalls, and bottom surfaces of the first semiconductor layers252A-252C.

In accordance with some embodiments, the gate dielectric layers300comprise silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric layers300include a high-k dielectric material, and in these embodiments, the gate dielectric layers300may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation methods of the gate dielectric layers300may include molecular-beam deposition (MBD), ALD, PECVD, or the like. In embodiments where portions of the dummy dielectric layers260remain in the second recesses298, the gate dielectric layers300include a material of the dummy dielectric layers260(e.g., SiO2).

The gate electrodes302are deposited over the gate dielectric layers300, respectively, and fill the remaining portions of the second recesses298. The gate electrodes302may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode302is illustrated inFIGS.33A through33D, the gate electrode302may comprise any number of liner layers302A, any number of work function tuning layers302B, and a fill material302C as illustrated byFIGS.33E and33F. After the filling of the second recesses298, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers300and the material of the gate electrodes302, which excess portions are over the top surface of the first ILD296. The remaining portions of material of the gate electrodes302and the gate dielectric layers300thus form replacement gates of the resulting NSFETs. The gate electrodes302and the gate dielectric layers300may be collectively referred to as “gate stacks.” The gate and the gate stacks may extend along sidewalls of the channel regions268of the nanostructures255.

The formation of the gate dielectric layers300in the region250N and the region250P may occur simultaneously such that the gate dielectric layers300in each region are formed from the same materials, and the formation of the gate electrodes302may occur simultaneously such that the gate electrodes302in each region are formed from the same materials. In some embodiments, the gate dielectric layers300in each region may be formed by distinct processes, such that the gate dielectric layers300may be different materials, and/or the gate electrodes302in each region may be formed by distinct processes, such that the gate electrodes302may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

InFIGS.34A and34B, a second ILD306is deposited over the first ILD296. In some embodiments, the second ILD306is a flowable film formed by FCVD. In some embodiments, the second ILD306is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. In some embodiments, before the formation of the second ILD306, the gate stack (including the gate dielectric layers300and the corresponding overlying gate electrodes302) is recessed, so that a recess is formed directly over the gate stack and between opposing portions of first spacers281. A gate mask304comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD296. Subsequently formed gate contacts (such as the gate contacts312, discussed below with respect toFIGS.35A and35B) penetrate through the gate mask304to contact the top surface of the recessed gate electrodes302.

InFIGS.35A and35B, gate contacts312and source/drain contacts314are formed through the second ILD306and the first ILD296. Openings for the source/drain contacts314are formed through the first ILD296and the second ILD306and openings for the gate contacts312are formed through the second ILD306and the gate mask304. The openings may be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD306. The remaining liner and conductive material form the source/drain contacts314and the gate contacts312in the openings. An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions292and the source/drain contacts314. The source/drain contacts314are physically and electrically coupled to the epitaxial source/drain regions292, and the gate contacts312are physically and electrically coupled to the gate electrodes302. The source/drain contacts314and the gate contacts312may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts314and the gate contacts312may be formed in different cross-sections, which may avoid shorting of the contacts.

FIGS.35C and35Dillustrate the structures ofFIGS.35A and35Bin embodiments in which the nanostructures255are thinned at various stages.FIG.35Cillustrates the embodiment ofFIG.19B, wherein the nanostructures255are thinned before forming the STI regions258. Portions of the nanostructures255in the region250N formed above top surfaces of the STI regions258(e.g., portions of the nanostructures255formed of the second semiconductor layers254A-254C) and portions of the nanostructures255formed below the top surfaces of the STI regions258(e.g., portions of the nanostructures255formed in the substrate250) may have sidewalls which are angled at the same angles with respect to a major surface of the substrate250. Portions of the nanostructures255in the region250P formed above and below top surfaces of the STI regions258may have sidewalls which are angled at different angles with respect to a major surface of the substrate250. For example, as illustrated inFIG.35C, sidewalls of the portion of the nanostructures255in the region250P above the top surfaces of the STI regions258and formed of the first semiconductor layers252A-252C may be more vertical than sidewalls of the portion of the nanostructures255in the region250P below the top surfaces of the STI regions258and formed in the substrate250.

FIG.35Dillustrates the embodiment ofFIGS.20B or31D and31E, wherein the nanostructures255are thinned after forming the STI regions258or after removing the dummy gate stacks. Portions of the nanostructures255in the region250N formed above and below top surfaces of the STI regions258may have sidewalls which are angled at different angles with respect to a major surface of the substrate250. For example, sidewalls of the portions of the nanostructures255in the region250N formed below the top surfaces of the STI regions258and formed in the substrate250may be more vertical than sidewalls of the portions of the nanostructures255in the region250N formed above the top surfaces of the STI regions258and formed in the second semiconductor layers254A-254C.

Portions of the nanostructures255in the region250P formed above and below the top surfaces of the STI regions258may have sidewalls which are angled at different angles with respect to a major surface of the substrate250, and which have a step difference in widths. For example, as illustrated inFIG.35D, sidewalls of the portions of the nanostructures255in the region250P formed above the top surfaces of the STI regions258(e.g., portions of the nanostructures255formed in the first semiconductor layers252A-252C) may be more vertical than sidewalls of the portions of the nanostructures255in the region250P formed below the top surfaces of the STI regions258(e.g., portions of the nanostructures255formed in the substrate250). Moreover, there may be a step difference between widths of the portions of the nanostructures255formed below the top surfaces of the STI regions258and the portions of the nanostructures255formed above the top surfaces of the STI regions258, with the portions of the nanostructures255formed below the top surfaces of the STI regions258having widths greater than widths of the portions of the nanostructures255formed above the top surfaces of the STI regions258.

As discussed above, forming the first semiconductor layers252A-252C having a gradient germanium concentration and thinning the first semiconductor layers252A-252C using an etching process which has a higher etching rate with increasing germanium concentration results in the first semiconductor layers252A-252C having more rectangular profiles and improves control of the process used to etch the nanostructures255in the region250N and the region250P. The first semiconductor layers252A-252C are then used as channel regions in the region250P. Including channel regions formed from the first semiconductor layers252A-252C in NSFETs results in better gate control, reduced nanostructure-width variation, and decreased DIBL.

In accordance with an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin. In an embodiment, a first angle between a sidewall of the semiconductor fin and the major surface of the semiconductor substrate before trimming the semiconductor fin is different from a second angle between the sidewall of the semiconductor fin and the major surface of the semiconductor substrate after trimming the semiconductor fin. In an embodiment, a ratio of a trimming rate of the first portion of the semiconductor fin to a trimming rate of the second portion of the semiconductor fin is from 1 to 3. In an embodiment, trimming the semiconductor fin includes exposing the semiconductor fin to an oxidant. In an embodiment, trimming the semiconductor fin includes exposing the semiconductor fin to an oxidant, then exposing the semiconductor fin to an alkaline or an acid in a cyclical process. In an embodiment, the method further includes forming a shallow trench isolation region surrounding at least a portion of the semiconductor fin, the semiconductor fin being trimmed after forming the shallow trench isolation region. In an embodiment, the method further includes forming a shallow trench isolation region surrounding at least a portion of the semiconductor fin, the semiconductor fin being trimmed before forming the shallow trench isolation region. In an embodiment, the method further includes forming a dummy gate over the semiconductor fin; and removing the dummy gate to expose the semiconductor fin, the semiconductor fin being trimmed after removing the dummy gate.

In accordance with another embodiment, a semiconductor device includes a semiconductor substrate; a first semiconductor fin over the semiconductor substrate, the first semiconductor fin including silicon germanium, a germanium concentration of the first semiconductor fin decreasing with increasing distance from the semiconductor substrate; a second semiconductor fin over the semiconductor substrate, the second semiconductor fin including silicon, wherein a first angle between a sidewall of the first semiconductor fin and a major surface of the semiconductor substrate is closer to perpendicular than a second angle between a sidewall of the second semiconductor fin and the major surface of the semiconductor substrate; a gate stack over the first semiconductor fin; and a source/drain region at least partially in the first semiconductor fin adjacent the gate stack. In an embodiment, the first angle is from 85° to 95°. In an embodiment, the second angle is from 70° to 85° or from 95° to 120°. In an embodiment, a ratio of an atomic percentage of germanium in a first portion of the first semiconductor fin to an atomic percentage of germanium in a second portion of the first semiconductor fin is from 1:2 to 1:8. In an embodiment, the first portion has a first width, the second portion has a second width, and the second width is greater than the first width by less than 1 nm. In an embodiment, the semiconductor device further includes a shallow trench isolation region surrounding a portion of the first semiconductor fin, a ratio of a topmost width of a portion of the first semiconductor fin extending above the shallow trench isolation region to a bottommost width of the portion of the first semiconductor fin extending above the shallow trench isolation region being from 0.8 to 1.2. In an embodiment, the semiconductor device further includes a shallow trench isolation region surrounding a portion of the first semiconductor fin, the first semiconductor fin having a step change in width at a top surface of the shallow trench isolation region. In an embodiment, the first semiconductor fin includes first straight sidewalls above the top surface of the shallow trench isolation region and second straight sidewalls below the top surface of the shallow trench isolation region, a third angle between the first straight sidewalls and the major surface of the semiconductor substrate being closer to perpendicular than a fourth angle between the second straight sidewalls and the major surface of the semiconductor substrate.

In accordance with yet another embodiment, a semiconductor device includes a first channel region over a semiconductor substrate, the first channel region including silicon germanium, the first channel region having a first width; a second channel region over the first channel region, the second channel region including silicon germanium, the second channel region having a lower germanium concentration than the first channel region, the second channel region having a second width; a third channel region over the semiconductor substrate, the third channel region including silicon, the third channel region having a third width; a fourth channel region over the third channel region, the fourth channel region including silicon, the fourth channel region having a fourth width, a difference between the first width and the second width being less than a difference between the third width and the fourth width; and a gate stack surrounding the first channel region and the second channel region. In an embodiment, the first channel region has a gradient germanium concentration which decreases with increasing distance from the semiconductor substrate, and the second channel region has a gradient germanium concentration which decreases with increasing distance from the semiconductor substrate. In an embodiment, a ratio of the second width to the first width is from 0.9 to 1.1. In an embodiment, a ratio of the fourth width to the third width is from 0.64 to 1.0.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.