Patent ID: 12224216

REFERENCE NUMERALS

substrate:100; isolation structure:101; substrate-side pad:102; first test device:110; second test device:120; first well region:111; second well region:112; third well region:121; fourth well region:122; first heavily doped region:1121; second heavily doped region:1122; third heavily doped region:1111; fourth heavily doped region:1221; fifth heavily doped region:1222; sixth heavily doped region:1211; lightly doped region:1123; passivation layer:200.

DETAILED DESCRIPTION

In order to facilitate the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the present disclosure belongs. Here, terms used in the description of the present disclosure are merely intended to describe specific embodiments, rather than limiting the present disclosure. As used herein, the term “and/or” includes any or all of one or more associated listed items or combinations thereof.

In the description of the present disclosure, it should be understood that orientations or location relationships indicated by terms such as “upper”, “lower”, “vertical”, “horizontal”, “inner”, “outer” are the directions and the location relationships illustrated on the basis of the drawings, and used just for convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the devices or elements must have a specific orientation and be constructed and operated in the specific orientation, and therefore shall not be considered as any limitations to the present disclosure.

FIG.1is a schematic diagram of a model parameter test structure for a transistor in an embodiment. As shown inFIG.1, the model parameter test structure comprises a substrate100, a first test device110and a second test device120.

The substrate100has a first conductivity type, a plurality of isolation structures101are provided in the substrate100, and the isolation structures101are used to isolate different doped regions.

The different doped regions refer to doped regions where the parameters of the doping process are different. The parameters of the doping process comprise, but are not limited to, doping elements, doping concentration, doping depth, etc. Doping predetermined elements in intrinsic semiconductors may form N-type semiconductors or P-type semiconductors, and the first conductivity type is N-type or P-type.

Specifically, in this embodiment, isolating the different doped regions via the isolation structures101can, on one hand, prevent ion diffusion between adjacent doped regions, thereby avoiding the change in the conductivity of the doped regions; and on the other hand, avoid leakage current between adjacent doped regions. Therefore, the test structure in this embodiment has high stability and reliability. Optionally, the isolation structures101are shallow trench isolation structures.

The first test device110is formed in the substrate100and configured to obtain characteristic parameters of a source side of a transistor; and the second test device120is formed in the substrate100and configured to obtain characteristic parameters of a drain side of the transistor, wherein, the structure of the first test device110is different from that of the second test device120.

The transistor is an asymmetric transistor to be tested in this embodiment. The asymmetric transistor may be a field effect transistor with an asymmetric structure, that is, a field effect transistor with different device structures at its source and drain. The asymmetric transistor may be a transistor in a dynamic random-access memory.

Specifically, the test device and the transistor in this embodiment are prepared synchronously, that is, the same process parameters and conditions are used for the corresponding layers of the test device and the transistor. Therefore, the characteristic parameters extracted from the test device may be used to accurately establish a simulation model of the transistor. Further, this embodiment is directed to transistors with an asymmetric structure, that is, transistors with different functional layers on the source side and the drain side and with different processes in the manufacturing process. The use of the same test device on the source and drain sides will lead to deviations in the extraction of characteristic parameters. Therefore, in this embodiment, corresponding test devices with different structures are provided for the source side and the drain side, so that the test devices can accurately reflect the characteristics of the device structure on the corresponding side, thereby improving the accuracy of the simulation model established by the extracted characteristic parameters.

The model parameter test structure for a transistor comprises: a substrate100having a first conductivity type, a plurality of isolation structures101being provided in the substrate100and the isolation structures101being used to isolate different doped regions; a first test device110formed in the substrate100and configured to obtain characteristic parameters of a source side of a transistor; and a second test device120formed in the substrate100and configured to obtain characteristic parameters of a drain side of the transistor; wherein, the structure of the first test device110is different from that of the second test device120. For transistors with asymmetric structures, in this embodiment, by the first test device110and the second test device120correspondingly prepared based on different device structures on the source side and the drain side, the model parameter extraction error caused by the test structure is reduced, the accuracy of extracting characteristic parameters on the source and drain sides of the transistor is improved.

In an embodiment, the structural difference between the first test device110and the second test device120matches the structural difference between the source side and the drain side of the transistor to be tested. Specifically, the structural difference matching means that, for example, assuming that the doping concentration of a set region on the source side of the transistor to be tested is A and the doping concentration of a region corresponding to the set region on the drain side of the transistor to be tested is B, then a set of corresponding regions is provided in the first test device110and the second test device120and the doping concentration is A and B, respectively. Or, for example, if one more doped region is provided on the source side than the drain side of the transistor to be tested, then one more doped region having the same doping characteristics as this doped region is provided in the first test device110than in the second test device120. Further, in a field effect transistor with an asymmetric structure, usually, one more lightly doped region is provided on the source side than the drain side. By the structural difference matching in this embodiment, the design difficulty of the test structure is reduced, and meanwhile, the characteristic parameters of the source and drain of the transistor are accurately obtained.

In an embodiment, the first test device110and the second test device120are both junction diodes. The junction diode has a variety of characteristic parameters, for example volt-ampere characteristics, forward characteristics, reverse characteristics, breakdown characteristics, etc. Therefore, the connection of external test devices to the first test device110and the second test device120in a set test manner can accurately obtain multiple performance parameters of the test devices, so as to obtain the characteristic parameters of the source and drain, which are then used for electrical simulations.

Further, the diode is a semiconductor device with a simple structure. On the basis of being able to realize the test function, the use of a relatively simple diode device structure can reduce the difficulty in preparing the first test device110and the second test device120, and reduce the failure of the test devices. Therefore, the test efficiency of the test structure in this embodiment is improved.

FIG.2is a schematic structure diagram of a first test device110in an embodiment. As shown inFIG.2, the first test device110comprises: a first well region111, having a first conductivity type and being formed in the substrate100; a second well region112, having a second conductivity type and being formed in the substrate100, a side surface of the second well region112being isolated from the first well region111via the isolation structure101; a first heavily doped region1121, having the second conductivity type and being formed in the second well region112; a second heavily doped region1122, having the first conductivity type and being formed in the second well region112, two side surfaces of the second heavily doped region1122being respectively isolated from the first heavily doped region1121and the second well region112via the isolation structure101; a third heavily doped region1111, having the first conductivity type and being formed in the first well region111; and a lightly doped region1123formed in the second well region112, the lightly doped region1123being located on a lower side of the second heavily doped region1122, and two side surfaces of the lightly doped region1123being respectively isolated from the first heavily doped region1121and the second well region112via the isolation structure101.

FIG.3is a schematic structure diagram of a second test device in an embodiment. As shown inFIG.3, the second test device120comprises: a third well region121, having the first conductivity type and being formed in the substrate100; a fourth well region122, having a second conductivity type and being formed in the substrate100, a side surface of the fourth well region122being isolated from the third well region121via the isolation structure101; a fourth heavily doped region1221, having the second conductivity type and being formed in the fourth well region122; a fifth heavily doped region1222, having the first conductivity type and being formed in the fourth well region122, two side surfaces of the fifth heavily doped region1222being respectively isolated from the fourth heavily doped region1221and the fourth well region122via the isolation structure101; and a sixth heavily doped region1211, having the first conductivity type and being formed in the third well region121.

Specifically, in the above-mentioned embodiment of the first test device110, the first well region111, the second well region112, the first heavily doped region1121, the second heavily doped region1122, and the third heavily doped region1111constitute a basic junction diode structure. In the above-mentioned embodiment of the second test device120, the third well region121, the fourth well region122, the fourth heavily doped region1221, the fifth heavily doped region1222, and the sixth heavily doped region1211constitute a basic junction diode structure; and the lightly doped region1123in the first test device110matches, as the structural difference of the device, the structural difference between the source side and the drain side of the transistor. Thus, the extraction of characteristic parameters on the source side and the drain side is realized. The junction diode device in this embodiment has a simple structure, is easy to manufacture, and has high device stability and reliability. Moreover, by the lightly doped region1123provided only in the first test device110, it is possible to accurately obtain the characteristic parameters on the source and drain sides, respectively.

In an embodiment, as shown inFIGS.1to3, the model parameter test structure further comprises: a passivation layer200formed on the surface of the substrate100to protect the substrate; and a substrate-side pad102, one end of which is connected to a set region in the first test device110or the second test device120and the other end extends to the surface of the passivation layer200, used for lapping parameter test probes. The set region in the first test device110or the second test device120is the set doped region in the test device. The parameter test probes are probes of the external test device. The parameter test probes can obtain the electrical performance of the test device by contacting the substrate-side pad102.

In an embodiment, as shown inFIG.2, the first test device110is connected to three substrate-side pads102which are respectively connected to the first heavily doped region1121, the second heavily doped region1122and the third heavily doped region1111. It should be noted that the number of substrate-side pads102in the first test device110may be determined according to the design model for electrical simulations. Therefore, for different electrical simulation models, a corresponding number of substrate-side pads102need to be provided. The number of substrate-side pads is not limited to 3 in this embodiment.

In an embodiment, as shown inFIG.3, the second test device120is connected to three substrate-side pads102which are respectively connected to the fourth heavily doped region1221, the fifth heavily doped region1222and the sixth heavily doped region1211. It should be noted that the number of substrate-side pads102in the second test device120may be determined according to the design model for electrical simulations. Therefore, for different electrical simulation models, a corresponding number of substrate-side pads102need to be provided. The number of substrate-side pads is not limited to 3 in this embodiment.

In an embodiment, the first conductivity type is P-type. Specifically, the first conductivity type is P-type, and the second conductivity type is N-type. In another embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

FIG.4is a flowchart of a method for preparing a model parameter test structure for a transistor in an embodiment. As shown inFIG.4, the preparation method comprises steps S100to S300.FIG.5is a schematic structure diagram of the device after the step S100in this embodiment. FIG.6is a schematic structure diagram of the device after the step S200in this embodiment, andFIG.1is a schematic structure diagram of the device after the step S300in this embodiment. It should be noted thatFIG.6shows only the overall outline of the first test device110and the second test device120, not the arrangement of the doped regions and the isolation structures therein.

S100: A substrate100having a first conductivity type is provided, a plurality of isolation structures101being provided in the substrate100.

Specifically, as shown inFIG.5, the isolation structures101may be shallow trench isolation structures. Forming the shallow trench isolation structures comprises: etching a trench in the substrate; filling dielectric in the trench; and flattening the surface of the wafer by chemical mechanical polishing. The dielectric, for example silicon oxide, is filled in the trench by chemical vapor deposition. The shallow trench isolation structure is a great isolation process due to its small surface area, compatibility with chemical mechanical polishing, and adaption to requirements on smaller line width and higher integration. It should be noted that the isolation structures101in this embodiment are not limited to shallow trench isolation structures, and other isolation structures101that can realize isolation are also possible.

In an embodiment, as shown inFIG.5, before the step S200, the method further comprises: forming a passivation layer200on the surface of the substrate100, the passivation layer200being used to protect the substrate100. The passivation layer200may be made of silicon nitride or silicon oxide.

S200: A first test device110and a second test device120are formed in the substrate100, the first test device110is configured to obtain characteristic parameters of a source side of the transistor, and the second test device120is configured to obtain characteristic parameters of a drain side of the transistor; wherein, the structure of the first test device110is different from that of the second test device120.

Specifically, a plurality of doped regions are provided at a set position in the substrate100by ion implantation. The plurality of doped regions form the first test device110and the second test device120shown inFIG.6according to the set device structure. Each test device comprises a plurality of doped regions, and the adjacent doped regions are isolated via the isolation structures101so as to prevent ion diffusion or leakage current between the adjacent doped regions. Moreover, the preparation method in this embodiment forms the first test device110and the second test device120with different structures, which avoids the inaccurate electrical parameter test caused by the use of the same test device.

S300: A substrate-side pad102is formed in the substrate100, one end of which is connected to a set region in the first test device110or the second test device120and the other end extends to the surface of the substrate100, and which is used for lapping parameter test probes.

Specifically, the substrate-side pad102is used for lapping parameter test probes. The parameter test probes are probes of the external test device. The parameter test probes can obtain the electrical performance of the test device by contacting the substrate-side pad102. Optionally, the substrate-side pad102is made of any one of copper, aluminum and tungsten. Further, if a passivation layer200is formed on the surface of the substrate100, the end of the substrate-side pad102used for lapping the parameter test probes extends to the surface of the passivation layer200.

FIG.7is a flowchart of forming the first test device110and the second test device120in the substrate100in an embodiment. As shown inFIG.7, the method comprises steps S210to S240.FIGS.8to11are schematic structure diagrams of the device after the steps S210to S240in this embodiment.

S210: A first well region111, a second well region112, a third well region121, and a fourth well region122are formed in the substrate100, a side surface of the second well region112being isolated from the first well region111via the isolation structure101and a side surface of the fourth well region122being isolated from the third well region121via the isolation structure101.

S220: A first heavily doped region1121is formed in the second well region112, and a fourth heavily doped region1221is formed in the fourth well region122.

S230: A lightly doped region1123is formed in the second well region112, two side surfaces of the lightly doped region1123being respectively isolated from the first heavily doped region1121and the second well region112via the isolation structure101.

S240: A third heavily doped region1111is formed in the first well region111, a second heavily doped region1122is formed in the second well region112, a sixth heavily doped region1211is formed in the third well region121, and a fifth heavily doped region1222is formed in the fourth well region122.

The first well region111, the third well region121, the second heavily doped region1122, the third heavily doped region1111, the fifth heavily doped region1222and the sixth heavily doped region1211all have the first conductivity type, and the second well region112, the fourth well region122, the first heavily doped region1121and the fourth heavily doped region1221all have the second conductivity type.

This embodiment provides a specific implementation of the first test device110and the second test device120. By forming the first test device110and the second test device120of the junction diode structure, in this embodiment, on the basis of being able to realize the test function, the use of a relatively simple diode device structure can reduce the difficulty in preparing the first test device110and the second test device120, and reduce the failure of the test devices. Therefore, the test efficiency of the test structure in this embodiment is improved.

Various technical features of the above embodiments can be arbitrarily combined. For simplicity, all possible combinations of various technical features of the above embodiments are not described. However, all those technical features shall be included in the protection scope of the present disclosure if not conflict.

The embodiments described above are merely some implementations of the present disclosure. Although those embodiments have been described in specific details, they are not construed as any limitation to the scope of the present disclosure. It should be noted that, for a person of ordinary skill in the art, a number of variations and improvements may be made without departing from the concept of the present disclosure, and those variations and improvements should be regarded as falling into the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the appended claims.