Patent ID: 12245529

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A programmable metallization cell generally includes a data storage layer arranged between a top electrode and a bottom electrode. An active metal layer may be disposed between the data storage layer and the top electrode. During a set operation a set voltage is applied across the top and bottom electrodes, such that a conductive bridge is formed within the data storage layer (e.g., resulting in a low resistance state). While applying the set voltage, ions may travel from the active metal layer to the data storage layer, thereby forming the conductive bridge within the data storage layer. During a reset operation a reset voltage is applied across the top and bottom electrodes, such that the conductive bridge may at least be partially removed from the data storage layer (e.g., resulting in a high resistance state). While applying the reset voltage, ions may travel from the data storage layer to the active metal layer, thereby at least partially dissolving the conductive bridge within the data storage layer.

The top electrode may be or comprise a diffusive species, such as, for example, titanium, tantalum, a nitride of the foregoing, or the like. Before operation of the programmable metallization cell (i.e., before applying the set and/or reset voltages), a baking process may be performed on the programmable metallization cell to verify data retention of the programmable metallization cell at high temperatures (e.g., about 400 degrees Celsius). The high temperatures of the baking process may result in problems, such as causing diffusion of the diffusive species from the top electrode to the active metal layer and/or the data storage layer. After performing the baking process, set and/or reset operations may be performed on the programmable metallization cell. During a set operation, the diffusive species may align with the ions from the active metal layer to form the conductive bridge within the data storage layer. However, in some embodiments, the reset voltage may be unable to remove the diffusive species from the data storage layer, such that at least a portion of the conductive bridge may remain within the data storage layer after applying the reset voltage. Thus, the programmable metallization cell may be unable to switch between the high resistance state and the low resistance state. Further, the buildup of the diffusive species within the data storage layer may effectively reduce an effective thickness of the data storage layer, thereby decreasing a breakdown voltage of the programmable metallization cell and/or causing undesired switching into the high resistance state. Furthermore, high heat may accumulate between the data storage layer and the top electrode due to the formation and/or removal of the conductive bridge. The high heat may further increase the diffusion of the diffusive species into the data storage layer, thereby further decreasing a performance and/or endurance of the programmable metallization cell.

Some embodiments of the present disclosure relate to a programmable metallization cell that includes a diffusion barrier layer disposed between a data storage layer and a top electrode. The data storage layer is disposed between the top electrode and a bottom electrode. An active metal layer is disposed between the top electrode and the data storage layer. The top and bottom electrodes each has a lower reactivity to oxygen than the active metal layer. The top electrode may comprise a diffusive species (e.g., titanium, tantalum, a nitride of the foregoing, etc.). The diffusion barrier layer is configured to prevent and/or block diffusion of the diffusive species from the top electrode and/or the active metal layer into the data storage layer. Thus, the diffusion barrier layer mitigates and/or eliminates buildup of the diffusive species in the data storage layer, such that the reset voltage may dissolve the conductive bridge within the data storage layer. This in turn increases a performance, endurance, and/or reliability of the programmable metallization cell.

FIG.1illustrates a cross-sectional view of some embodiments of a memory device100having a programmable metallization cell140that includes a diffusion barrier layer132overlying a data storage layer130. The programmable metallization cell140may, for example, be a cation-type resistive random-access memory (RRAM) cell or some other suitable type of RRAM cell. Note that the cation-type RRAM cell may, for example, be referred to as a programmable metallization cell (PMC) or a conductive-bridging random-access memory (CBRAM) cell.

The memory device100includes a substrate102and the programmable metallization cell140overlying the substrate102. An interconnect dielectric structure118overlies the substrate102. A lower conductive via114is disposed within the interconnect dielectric structure118and overlies the substrate102. In some embodiments, a semiconductor device104may be disposed within and/or over the substrate102. In some embodiments, the semiconductor device104may, for example, be configured as a transistor. In such embodiments, the semiconductor device104includes source/drain regions106, a gate dielectric layer108, a gate electrode110, and a sidewall spacer structure112. In some embodiments, the lower conductive via114overlies a source/drain region106of the semiconductor device104.

A lower conductive wire116is disposed within the interconnect dielectric structure118and overlies the lower conductive via114, such that the lower conductive wire116is electrically coupled to the semiconductor device104. A dielectric structure120is disposed along an upper surface of the lower conductive wire116. The dielectric structure120includes a lower dielectric layer120aand an upper dielectric layer120b. The programmable metallization cell140is disposed within the interconnect dielectric structure118and overlies a bottom electrode via122. The bottom electrode via122may include a conductive liner124and a conductive structure126, in which the conductive liner124laterally surrounds the conductive structure126. In some embodiments, the programmable metallization cell140includes a bottom electrode128, the data storage layer130, the diffusion barrier layer132, an active metal layer134, and a top electrode136. An upper conductive via142overlies the top electrode136and an upper conductive wire144overlies the upper conductive via142. In some embodiments, the active metal layer134may be configured as an ion reservoir layer.

During operation of the programmable metallization cell140, a conductive bridge may be repeatedly formed and dissolved within a region131of the data storage layer130to change the programmable metallization cell140between a low resistance state and a high resistance state. While forming the conductive bridge, a set voltage is applied between the top and bottom electrodes136,128. The set voltage may induce oxidation of the active metal layer134and forms metal cations. Further, an electric field from the set voltage causes the metal cations to migrate to the data storage layer130and to reduce into the conductive bridge within the region131. While dissolving or removing the conductive bridge, a reset voltage is applied between the top and bottom electrodes136,128. The reset voltage may induce oxidation of the conductive bridge and form metal cations. Further, an electric field from the reset voltage causes the metal cations to migrate to the active metal layer134and to reduce into the active metal layer134.

The top and bottom electrodes136,128and the active metal layer134are conductive. However, the active metal layer134is electrochemically active compared to the top and bottom electrodes136,128. Hence, the top and bottom electrodes136,128have lower reactivates with oxygen than the active metal layer134and depend upon more energy to oxidize than the active metal layer134. For example, the top and bottom electrodes136,128may depend upon 5 or more electron volts (eV) to oxidize, whereas the active metal layer134may depend upon 3 or less eV to oxidize. Other eV values are, however, amenable. The top and/or the bottom electrodes136,128may, for example, be or comprise titanium, tantalum, titanium nitride, tantalum nitride, some other suitable material(s), or any combination of the foregoing.

The data storage layer130may be a solid electrolyte for metal cations that result from oxidation of the active metal layer134. For example, where the active metal layer134is or comprises aluminum, the data storage layer130may be a solid electrolyte for aluminum cations. In some embodiments, the data storage layer130is or comprises silicon oxide (e.g., SiO2), hafnium oxide (e.g., HfO2), silicon nitride (e.g., SiN x), aluminum oxide (e.g., Al2O3), zirconium oxide (e.g., ZrO2), tantalum oxide (e.g., TaOx), titanium oxide (e.g., TiOx), aluminum nitride, some other suitable dielectric(s), or any combination of the foregoing. Further, in some embodiments, the data storage layer130is or comprises germanium sulfur (e.g., GeS), germanium selenium (e.g., GeSe), germanium tellurium (e.g., GeTe), a metal oxide, amorphous silicon, some other suitable electrolyte(s), or any combination of the foregoing.

In some embodiments, the top electrode136may be or comprise a diffusive species (e.g., titanium, tantalum, a metal nitride(s) of the foregoing, etc.). In yet further embodiments, the diffusion barrier layer132may, for example, be or comprise ruthenium, iridium, tungsten, some other suitable diffusion barrier material, or the like. In some embodiments, the diffusion barrier layer132may be or comprise a single material (e.g., ruthenium, iridium, or tungsten), such that the diffusion barrier layer132is a continuous layer of the single material. In some embodiments, the diffusion barrier layer132is conductive and/or is configured to block or otherwise slow diffusion of the diffusive species to the data storage layer130and/or the active metal layer134. In some embodiments, the diffusion barrier layer132comprises a low diffusivity material (e.g., ruthenium, iridium, or tungsten) that blocks or otherwise slows diffusion of the diffusive species. For example, by virtue of the diffusion barrier layer132comprising a single continuous layer of the low diffusivity material it may have grain sizes that are smaller than grain sizes of the top electrode136, such that the diffusive species may not travel across grain boundaries of the diffusion barrier layer132to the data storage layer130. In yet further embodiments, the diffusion barrier layer132may not comprise grain boundaries (e.g., the diffusion barrier layer132may have an amorphous structure), thereby increasing a diffusion-path complexity for the diffusive species of the top electrode136. Alternatively, in some embodiments, the diffusion barrier layer132has a monocrystalline structure and metal grains of the top electrode136are equiaxed grains, thereby increasing the diffusion-path complexity for the diffusive species. Thus, the diffusion barrier layer132increases diffusion-path complexity for the diffusive species, thereby blocking or slowing diffusion of the diffusive species from the top electrode136to the data storage layer130.

In some embodiments, the top electrode136may have a low diffusion activation temperature (e.g., less than about 400 degrees Celsius). A diffusion activation temperature may be a temperature in which atoms from a structure and/or layer may diffuse from the structure and/or layer to another structure. In yet further embodiments, the diffusion barrier layer132may have a high diffusion activation temperature (e.g., greater than about 400 degrees Celsius). In some embodiments, after fabricating the programmable metallization cell140, a baking process may be performed on the programmable metallization cell140to verify data retention of the programmable metallization cell140at high temperatures (e.g., about 400 degrees Celsius). In some embodiments, the high temperatures are greater than the low diffusion activation temperature. However, by virtue of the high diffusion activation temperature, atoms from the diffusion barrier layer132may not diffuse out of the diffusion barrier layer during the baking process. Further, the diffusion barrier layer132may prevent or mitigate diffusion of the diffusive species from the top electrode136to the data storage layer130during the baking process. By preventing the diffusion of the diffusive species, the diffusion barrier layer132increases discrete data states of the programmable metallization cell140and increases a number of set and/or reset operations that may be performed on the programmable metallization cell140. Thus, the diffusion barrier layer132increases a performance, endurance, and reliability of the programmable metallization cell140.

In yet further embodiments, the bottom electrode128may comprise a material different from the top electrode136. For example, the bottom electrode128may be or comprise a same material of the diffusion barrier layer132, such that the bottom electrode128is configured to prevent diffusion of the diffusive species to the data storage layer130. In some embodiments, the diffusion barrier layer132and/or the active metal layer134may each be substantially free of the diffusive species. In further embodiments, an atomic percentage of the diffusive species (e.g., titanium, tantalum, and/or nitrogen) within the diffusion barrier layer132and/or the active metal layer134may be about 0 percent, less than 1 percent, less than 3 percent, or less than about 5 percent, such that the diffusion barrier layer132and/or the active metal layer134may each be substantially free of the diffusive species.

FIG.2illustrates a cross-sectional view of some embodiments of a memory device200according to some alternative embodiments of the memory device100ofFIG.1.

In some embodiments, the diffusion barrier layer132is disposed between the active metal layer134and the top electrode136. The diffusion barrier layer132is configured to prevent and/or mitigate diffusion of the diffusive species from the top electrode136to the active metal layer134and/or the data storage layer130. In further embodiments, a bottom surface of the diffusion barrier layer132directly contacts a top surface of the active metal layer134and a top surface of the diffusion barrier layer132directly contacts a bottom surface of the top electrode136.

The dielectric structure120surrounds the bottom electrode via122, between the programmable metallization cell140and the lower conductive wire116. In some embodiments, the dielectric structure120is a multilayer film including a lower dielectric layer120aand an upper dielectric layer120boverlying the lower dielectric layer120a. The lower and upper dielectric layers120a,120bare different materials. In some embodiments, the lower dielectric layer120amay, for example, be or comprise silicon carbide, silicon oxy-carbide, or another suitable dielectric material. In further embodiments, the upper dielectric layer120bmay, for example, be or comprise silicon oxide (e.g., SiO2), silicon nitride, or another suitable dielectric material. In alternative embodiments, the dielectric structure120is a single layer.

FIG.3illustrates a cross-sectional view of some embodiments of a memory device300according to some alternative embodiments of the memory device100ofFIG.1.

The memory device300includes a diffusion barrier layer132disposed between the data storage layer130and the active metal layer134, and an upper diffusion barrier layer302disposed between the active metal layer134and the top electrode136. In some embodiments, the upper diffusion barrier layer302may, for example, be or comprise ruthenium, tungsten, iridium, or the like and/or the upper diffusion barrier layer302is configured as the diffusion barrier layer132. In some embodiments, the upper diffusion barrier layer302is configured to prevent diffusion of the diffusive species (e.g., titanium, tantalum, nitrogen) from the top electrode136to the active metal layer134. In yet further embodiments, the upper diffusion barrier layer302comprises a same material as the diffusion barrier layer132. Thus, the upper diffusion barrier layer302may further mitigate and/or prevent diffusion of the diffusive species to the data storage layer130, thereby further increasing the performance, endurance, and reliability of the programmable metallization cell140.

In further embodiments, the bottom electrode128comprises a first bottom electrode layer128aand a second bottom electrode layer128boverlying the first bottom electrode layer128a. In some embodiments, the second bottom electrode layer128bmay be configured as the diffusion barrier layer132, such that the second bottom electrode layer128bis configured to prevent and/or block diffusion of the diffusive species from the first bottom electrode layer128aand/or other underlying layers/structures to the data storage layer130. In some embodiments, the first bottom electrode layer128amay, for example, be or comprise titanium, tantalum, titanium nitride, tantalum nitride, or another suitable conductive material. In further embodiments, the second bottom electrode layer128bmay, for example, be or comprise ruthenium, tungsten, iridium, or the like and/or may have a thickness within a range of about 10 to 30 Angstroms. Thus, in some embodiments, the second bottom electrode layer128bmay be configured as a bottom electrode diffusion barrier layer and may further increase the performance, endurance, and reliability of the programmable metallization cell140. Although the second bottom electrode layer128bis illustrated inFIG.3, it may be appreciated that the bottom electrode128ofFIG.1,2,4,5, or10-12may each be configured as the bottom electrode128ofFIG.3. Thus, the bottom electrode128ofFIG.1,2,4,5, or10-12may each comprise the second bottom electrode layer128boverlying the first bottom electrode layer128a, such that the second bottom electrode layer128bis configured as the diffusion barrier layer132and blocks diffusion of the diffusive species.

FIG.4illustrates a cross-sectional view400of some embodiments of the programmable metallization cell140ofFIG.2.

In some embodiments, a thickness of the data storage layer130is less than a thickness of the diffusion barrier layer132. In further embodiments, the thickness of the diffusion barrier layer132is less than a thickness of the bottom electrode128and/or a thickness of the top electrode136. In yet further embodiments, the thickness of the diffusion barrier layer132is less than a thickness of the active metal layer134.

In some embodiments, the thickness of the data storage layer130is within a range of about 10 to 50 Angstroms. In further embodiments, if the thickness of the data storage layer130is less than about 10 Angstroms, then a breakdown voltage of the programmable metallization cell140may be increased. In yet further embodiments, if the thickness of the data storage layer130is greater than 50 Angstroms, then the set and/or reset voltages may be increased in order to form or dissolve the conductive bridge within the data storage layer130, thereby increasing a power consumption of the programmable metallization cell140. In various embodiments, the thickness of the diffusion barrier layer132is within a range of about 10 to 30 Angstroms. In some embodiments, if the thickness of the diffusion barrier layer132is less than about 10 Angstroms, then an ability of the diffusion barrier layer132to prevent and/or block the diffusive species may be degraded. In further embodiments, if the thickness of the diffusion barrier layer132is greater than about 30 Angstroms, then the set and/or reset voltages may be increased to form and/or dissolve the conductive bridge, thereby increasing a power consumption of the programmable metallization cell140.

FIG.5illustrates a cross-sectional view of some embodiments of an integrated chip500with an interconnect structure502and a programmable metallization cell140that includes a diffusion barrier layer132. The programmable metallization cell140is disposed within the interconnect structure502. In some embodiments, the programmable metallization cell140is configured as the programmable metallization cell140ofFIG.1,2, or3.

The integrated chip500includes the interconnect structure502overlying a substrate102. In some embodiments, the substrate102may, for example, be a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate and/or may comprise a first doping type (e.g., p-type). In some embodiments, a semiconductor device104is disposed within/on the substrate102. In further embodiments, the semiconductor device104may be configured as an access transistor. In such embodiments, the semiconductor device104includes source/drain regions106, a gate dielectric layer108, a gate electrode110, and a sidewall spacer structure112. The source/drain regions106are disposed within the substrate102and may comprise a second doping type (e.g., n-type) opposite the first doping type (e.g., p-type). In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. The source/drain regions106may be disposed on opposite sides of the gate electrode110. The gate dielectric layer108is disposed between the gate electrode110and the substrate102. Further, the sidewall spacer structure112laterally surrounds sidewalls of the gate dielectric layer108and sidewalls of the gate electrode110. In some embodiments, the gate dielectric layer108may, for example, be or comprise silicon dioxide, a high-k dielectric material, or another suitable dielectric material. In further embodiments, the gate electrode110may, for example, be or comprise polysilicon, a metal, such as aluminum, titanium, another suitable metal, or the like. In yet further embodiments, the sidewall spacer structure112may, for example, be or comprise silicon nitride, silicon carbide, another suitable dielectric material, or a combination of the foregoing.

The interconnect structure502includes an interconnect dielectric structure118, a plurality of conductive vias504, and a plurality of conductive wires506. The plurality of conductive vias504and the plurality of conductive wires506are disposed within the interconnect dielectric structure118and are configured to electrically couple devices (e.g., the semiconductor device104and the programmable metallization cell140) disposed within the integrated chip500together. The interconnect dielectric structure118may be or comprise a plurality of inter-level dielectric (ILD) layers. In some embodiments, the plurality of ILD layers may, for example, respectively be or comprise silicon dioxide, a low-k dielectric material, an extreme low-k dielectric layer, or the like. In further embodiments, the plurality of conductive vias and/or wires504,506may respectively, for example, be or comprise aluminum, copper, tungsten, another suitable conductive material, or a combination of the foregoing. The programmable metallization cell140is disposed within the interconnect structure502between a lower layer of the conductive wires506and an upper layer of the conductive wires506.

In some embodiments, the gate electrode110of the semiconductor device104is electrically coupled to a word line (WL). A source/drain region106of the semiconductor device104is electrically coupled to a source line (SL) by way of the interconnect structure502. Further, the programmable metallization cell140is electrically coupled to a bit line (BL) by overlying conductive vias504and overlying conductive wires506. In further embodiments, an output of the BL and/or the programmable metallization cell140may be accessed at the SL upon application of an appropriate WL voltage to the WL. In yet further embodiments, a set operation and/or a reset operation may be performed on the programmable metallization cell140by applying appropriate bias conditions to the BL, the SL, and/or the WL, such that a conductive bridge may be formed or dissolved within the data storage layer130of the programmable metallization cell140. The diffusion barrier layer132is configured to prevent or mitigate diffusion of a diffusive species (e.g., titanium) from the top electrode136and/or the active metal layer134to the data storage layer130. This may increase a number of set and/or reset operations that may be performed on the programmable metallization cell140.

FIG.6illustrates a top view600of some alternative embodiments of the integrated chip500ofFIG.5taken along the line inFIG.5.

In some embodiments, as illustrated inFIG.6, the programmable metallization cell140and/or the top electrode136may each have a rectangular shape or a square shape when viewed from above. In further embodiments, when viewed from above, the programmable metallization cell140may have a circular shape or an elliptical shaped when viewed from above (not shown).

FIGS.7-12illustrate cross-sectional views700-1200of some embodiments of a method for forming a memory device having a programmable metallization cell that includes a diffusion barrier layer. Although the cross-sectional views700-1200shown inFIGS.7-12are described with reference to a method, it will be appreciated that the structures shown inFIGS.7-12are not limited to the method but rather may stand alone separate of the method. Further, althoughFIGS.7-12are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

As shown in cross-sectional view700ofFIG.7, a lower inter-level dielectric (ILD) structure702is formed over a substrate102and a lower conductive wire116is formed within the lower ILD structure702. Further, a dielectric structure120is formed over the lower ILD structure702. In some embodiments, the lower ILD structure702and/or the dielectric structure120may, for example, each be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or another suitable deposition or growth process. In further embodiments, the lower conductive wire116may be formed by a single damascene process or a dual damascene process. In some embodiments, the dielectric structure120may include a lower dielectric layer120aand an upper dielectric layer120boverlying the lower dielectric layer120a. In some embodiments, the lower ILD structure702may, for example, be or comprise silicon dioxide, a low-k dielectric material, an extreme low-k dielectric material, a combination of the foregoing, or the like. In further embodiments, the lower dielectric layer120amay, for example, be or comprise silicon carbide, silicon oxy-carbide, or the like. In yet further embodiments, the upper dielectric layer120bmay, for example, be or comprise silicon oxide, silicon nitride, or the like.

As shown in cross-sectional view800ofFIG.8, a conductive liner124and a conductive structure126are formed over the lower conductive wire116. In some embodiments, before forming the conductive liner124and the conductive structure126, the dielectric structure120is patterned to form a bottom electrode via opening, thereby exposing an upper surface of the lower conductive wire116. After forming the bottom electrode via opening, the conductive liner124is deposited over the lower conductive wire116and the dielectric structure120, such that the conductive liner124at least partially lines the bottom electrode via opening. In further embodiments, after forming the conductive liner124, the conductive structure126is deposited over the conductive liner124. In some embodiments, the conductive structure126fills a remaining portion of the bottom electrode via opening. In further embodiments, the conductive liner124and/or the conductive structure126may, for example, each be deposited by CVD, PVD, electroless plating, electroplating, sputtering, or another suitable growth or deposition process. In some embodiments, the conductive liner124may, for example, be or comprise tantalum nitride and/or some other suitable conductive liner material(s). In further embodiments, the conductive structure126may, for example, be or comprise titanium nitride and/or some other suitable conductive material(s).

As shown in cross-sectional view900ofFIG.9, a planarization process is performed on the conductive liner124and the conductive structure126until an upper surface of the dielectric structure120is reached, thereby defining a bottom electrode via122. In some embodiments, the planarization process may include performing a chemical mechanical planarization (CMP) process.

As shown in cross-sectional view1000ofFIG.10, a memory cell layer stack1002is formed over the dielectric structure120and the bottom electrode via122. In some embodiments, the memory cell layer stack1002includes a bottom electrode128, a data storage layer130, a diffusion barrier layer132, an active metal layer134, and a top electrode136. In further embodiments, the diffusion barrier layer132may be disposed between the data storage layer130and the top electrode136. In some embodiments, the top electrode136is formed in such a manner that it comprises a diffusive species (e.g., titanium, tantalum, nitrogen, a combination of the foregoing, or the like). The diffusion barrier layer132is configured to prevent diffusion of the diffusive species from the top electrode136and/or the active metal layer134to the data storage layer130. In some embodiments, each layer within the memory cell layer stack1002may, for example, be deposited by CVD, PVD, ALD, sputtering, co-sputtering, or another suitable growth or deposition process. Further, after depositing layers of the memory cell layer stack1002, a masking layer1004may be formed over the memory cell layer stack1002. In some embodiments, the masking layer1004may be or comprise a photoresist, a hard masking layer, or the like.

As shown in cross-sectional view1100ofFIG.11, the memory cell layer stack1002is patterned according to the masking layer (1004ofFIG.10), thereby defining a programmable metallization cell140. In some embodiments, the patterning process includes exposing unmasked regions of layers within the memory cell layer stack1002to one or more etchants and subsequently performing a removal process to remove the masking layer (1004ofFIG.10).

As shown in cross-sectional view1200ofFIG.12, an upper ILD structure1202is formed over the dielectric structure120and the programmable metallization cell140. In some embodiments, the upper ILD structure1202may be formed by, for example, CVD, PVD, ALD, or another suitable deposition or growth process. In further embodiments, the upper ILD structure1202may, for example, be or comprise silicon dioxide, a low-k dielectric material, an extreme low-k dielectric material, or another suitable dielectric material. Further, an upper conductive via142and an upper conductive wire144are formed over the programmable metallization cell140. In some embodiments, the upper conductive via and/or wire142,144may, for example, respectively be or comprise aluminum, copper, tungsten, another suitable dielectric material, or a combination of the foregoing. In further embodiments, the upper conductive via142and/or the upper conductive wire144may each be formed by a single damascene process or a dual damascene process.

In some embodiments, after forming the programmable metallization cell140, a baking process is performed on the programmable metallization cell140to verify data retention of the programmable metallization cell140at high temperatures. Further, set and/or reset operations may be performed on the programmable metallization cell140after performing the baking process. In some embodiments, the baking process may reach a high temperature of about 400 degrees Celsius and/or may maintain the high temperature for a duration of about 30 minutes. In some embodiments, if, for example, the diffusion barrier layer132is omitted (not shown), then the baking process may cause diffusion of the diffusive species from the top electrode136to the active metal layer134and/or the data storage layer130. This in turn may result in a reduced number of set and/or reset operations that may be performed on the programmable metallization cell140and/or may reduce an effective thickness of the data storage layer130. However, according to embodiments of the present disclosure, the diffusion barrier layer132is disposed between the data storage layer130and the top electrode136and is configured to prevent diffusion of the diffusive species from the top electrode136to the data storage layer130during the baking process. This in part may be because the diffusion barrier layer132increases a diffusion-path complexity for the diffusive species, such that the diffusive species may not traverse the diffusion barrier layer132to the data storage layer130. In addition, a diffusion activation temperature of the diffusion barrier layer132is greater than the high temperature (e.g., about 400 degrees Celsius) of the baking process, such that atoms within the diffusion barrier layer132do not diffuse out of the diffusion barrier layer132during the baking process.

In some embodiments, after performing the baking process, the data storage layer130and/or the active metal layer134may each be substantially free of the diffusive species. For example, an atomic percentage of the diffusive species (e.g., titanium, tantalum, and/or nitrogen) within the data storage layer130and/or the active metal layer134may be about 0 percent, less than 1 percent, less than 3 percent, or less than 5 percent, such that the data storage layer130and/or the active metal layer134are each substantially free of the diffusive species. In further embodiments, an atomic percentage of the diffusive species (e.g., titanium, tantalum, and/or nitrogen) within the diffusion barrier layer132may be about 0 percent, less than 1 percent, less than 3 percent, or less than 5 percent, such that the diffusion barrier layer132is substantially free of the diffusive species after the baking process. Thus, the diffusive species may not diffusive from the top electrode136during the baking process. In yet further embodiments, the bottom electrode128may comprise a bottom electrode diffusion barrier layer (not shown) that is configured as the diffusion barrier layer132(e.g., seeFIG.3), such that the diffusive species is blocked from diffusing from the bottom electrode128to the data storage layer130during the baking process.

In further embodiments, a formation temperature of an alloy comprising the diffusive species (e.g., titanium) and a material (e.g., tungsten, ruthenium, or iridium) of the diffusion barrier layer132is greater than the high temperature (e.g., 400 degrees Celsius) of the baking process. This, in part, further prevents and/or mitigates diffusion of the diffusive species into the diffusion barrier layer132and/or layer(s)/structure(s) underlying the diffusion barrier layer132. In some embodiments, a formation temperature of a titanium-ruthenium (Ti—Ru) alloy, a formation temperature of a titanium-iridium (Ti—Ir) alloy, and/or a formation temperature of a titanium-tungsten (Ti—W) alloy are each greater than 400 degrees Celsius.

FIG.13illustrates a method1300of forming a memory device having a programmable metallization cell that includes a diffusion barrier layer according to the present disclosure. Although the method1300is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At act1302, a lower conductive wire is formed over a substrate.FIG.7illustrates a cross-sectional view700corresponding to some embodiments of act1302.

At act1304, a dielectric structure is formed over the lower conductive wire.FIG.7illustrates a cross-sectional view700corresponding to some embodiments of act1304.

At act1306, a bottom electrode via is formed over the lower conductive wire, such that the bottom electrode via extends through the dielectric structure and contacts the lower conductive wire.FIGS.8and9illustrate cross-sectional views800and900corresponding to some embodiments of act1306.

At act1308, a memory cell layer stack is formed over the bottom electrode via. The memory cell layer stack includes a top electrode, a data storage layer, and a diffusion barrier layer disposed between the top electrode and the data storage layer.FIG.10illustrates a cross-sectional view1000corresponding to some embodiments of act1308.

At act1310, the memory cell layer stack is patterned, thereby defining a programmable metallization cell.FIG.11illustrates a cross-sectional view1100corresponding to some embodiments of act1310.

At act1312, an upper conductive via and an upper conductive wire are formed over the programmable metallization cell.FIG.12illustrates a cross-sectional view1200corresponding to some embodiments of act1312.

Accordingly, in some embodiments, the present application relates to a programmable metallization cell including a bottom electrode, a data storage layer, a top electrode, and a diffusion barrier layer, in which the diffusion barrier layer is configured to prevent diffusion of a diffusive species to the data storage layer.

In various embodiments, the present application provides a memory device including a substrate; a bottom electrode overlying the substrate; a data storage layer overlying the bottom electrode; a top electrode overlying the data storage layer, wherein a conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode; and a diffusion barrier layer disposed between the data storage layer and the top electrode.

In various embodiments, the present application provides an integrated chip including a substrate; a bottom electrode via overlying the substrate; and a programmable metallization cell overlying the bottom electrode via, wherein the programmable metallization cell includes a top electrode, a data storage layer, an active metal layer, and a diffusion barrier layer, wherein the top electrode comprises a diffusive species, wherein the top electrode has a lower reactivity to oxygen than the active metal layer, wherein the active metal layer is disposed between the top electrode and the data storage layer, and wherein the diffusion barrier layer underlies the top electrode and is configured to prevent diffusion of the diffusive species to the data storage layer.

In various embodiments, the present application provides a method for forming a memory device, the method including forming a lower conductive wire over a substrate; forming a bottom electrode via over the lower conductive wire; forming a memory cell layer stack over the bottom electrode via, wherein the memory cell layer stack includes a bottom electrode, a data storage layer, a diffusion barrier layer, and a top electrode, wherein the diffusion barrier layer is disposed between the data storage layer and the top electrode, wherein the top electrode comprises a diffusive species, and wherein the diffusion barrier layer is configured to block diffusion of the diffusive species; and patterning the memory cell layer stack, thereby defining a programmable metallization cell.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.