Patent ID: 12224174

DETAILED DESCRIPTION OF THE EMBODIMENTS

The disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the specification and the claims, the term “and/or” is intended to include any combination of the terms “and” and “or” for the purpose of its meaning and interpretation. For example, “A and/or B” may be understood to mean “A, B, or A and B.” The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.”

In the specification and the claims, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.”

The terms “comprises,” “comprising,” “includes,” and/or “including,”, “has,” “have,” and/or “having,” and variations thereof when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

When a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numbers indicate the same components throughout the specification.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For instance, a first element discussed below could be termed a second element without departing from the teachings of the disclosure. Similarly, the second element could also be termed the first element.

The terms “overlap” or “overlapped” mean that a first object may be above or below or to a side of a second object, and vice versa. Additionally, the term “overlap” may include layer, stack, face or facing, extending over, covering, or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art.

“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG.1is a schematic cross-sectional view of a stacked structure including a semiconductor structure according to an embodiment.

Referring toFIG.1, a stacked structure10according to an embodiment may include a base substrate110, a metal buffer layer200, and a semiconductor structure300. The metal buffer layer200may include a first metal buffer layer210and a second metal buffer layer220. The semiconductor structure300may include a first semiconductor layer310, an active layer330, and a second semiconductor layer320.

The base substrate110may include an amorphous substrate. For example, the base substrate110may include glass, plastic, or the like as an amorphous substrate. In an embodiment, the base substrate110may include a glass substrate.

The metal buffer layer200may be disposed on the base substrate110. Specifically, the metal buffer layer200may be disposed on a surface (for example, upper surface in the drawing) of the base substrate110. The metal buffer layer200may include a first metal buffer layer210and a second metal buffer layer220.

The first metal buffer layer210may be disposed on a surface (for example, upper surface in the drawing) of the base substrate110. The first metal buffer layer210may be formed to reduce a difference in lattice constant between the base substrate110and the first semiconductor layer310of the semiconductor structure300. For example, even in case that the base substrate110is an amorphous substrate, the first metal buffer layer210having crystal grains may be formed on the base substrate110, so that a difference in lattice constant between the base substrate110and the first semiconductor layer310(to be described later) may be reduced. The first metal buffer layer210may include a material capable of having a structure that has crystal grains and may be self-aligned and oriented in a single direction on the base substrate110, which may be an amorphous substrate having no crystal structure. The first metal buffer layer210may include a material having a hexagonal close packed (HCP) crystal structure in consideration of the crystal structure of the first semiconductor layer310of the semiconductor structure300to be described later.

In an embodiment, the first metal buffer layer210may include a metal material capable of self-alignment in a single orientation. For example, the first metal buffer layer210may include beryllium (Be), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), strontium (Sr), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), antimony (Sb), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), lawrencium (Lr), platinum (Pt), gold (Au), mercury (Hg), lead (Pb), thallium (Tl), a combination thereof, or a nitride thereof, but the material thereof is not limited thereto.

The second metal buffer layer220may be disposed on the first metal buffer layer210. The second metal buffer layer220may serve to improve the crystallinity of the first semiconductor layer310by reducing a difference in lattice constant between the base substrate110and the first semiconductor layer310of the semiconductor structure300. The second metal buffer layer220may be a seed layer for forming the first semiconductor layer310of the semiconductor structure300to be described later.

In an embodiment in which the second metal buffer layer220may be formed on the first metal buffer layer210having a hexagonal close packed (HCP) crystal structure, similarly to the first metal buffer layer210, the second metal buffer layer220may have a hexagonal close packed (HCP) crystal structure. Since the first and second metal buffer layers210and220have a hexagonal close packed (HCP) crystal structure, the crystallinity of the first semiconductor layer310of the semiconductor structure300may be improved. However, the disclosure is not limited thereto, and at least one of the first and second metal buffer layers210and220may have a face centered cubic (FCC) crystal structure.

In an embodiment, the second metal buffer layer220may include Be, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Hf, Ta, W, Re, Os, Lr, Pt, Au, Hg, Pb, Tl, a combination thereof, or a nitride thereof, but the material thereof is not limited thereto.

The semiconductor structure300may be disposed on the metal buffer layer200. The semiconductor structure300may be disposed on a surface of the second metal buffer layer220. The semiconductor structure300may include a first semiconductor layer310, an active layer330, and a second semiconductor layer320.

The first semiconductor layer310may be disposed on the second metal buffer layer220. The first semiconductor layer310may be formed by growing on the second metal buffer layer220by an epitaxial method.

The first semiconductor layer310may include a semiconductor material having a formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer310may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer310may include Gallium Nitride (GaN), and GaN may be at least one of GaN doped with a n-type dopant, GaN doped with a p-type dopant, and undoped GaN.

In an embodiment, the first semiconductor layer310may include an n-type semiconductor having a first conductivity type. For example, the first semiconductor layer310may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN, which may be doped with an n-type dopant. The first semiconductor layer310may be doped with a first conductive dopant. For example, the first conductive dopant may be Silicon (Si), Germanium (Ge), or Tin (Sn). In an embodiment, the first semiconductor layer310may be n-GaN doped with n-type Si, but is not limited thereto.

In some embodiments, the first semiconductor layer310may include an undoped semiconductor, and the undoped semiconductor may be a material not doped with an n-type or p-type dopant. For example, the first semiconductor layer310may include GaN not doped with an n-type or p-type dopant.

The active layer330may be disposed on the first semiconductor layer310. The active layer330may include a material having a single or multiple quantum well structure. In case that the active layer330includes a material having a multiple quantum well structure, the active layer330may have structure in which quantum layers and well layers may be alternately stacked with each other.

The active layer330may emit light by combination of an electron-hole pair according to an electric signal applied through the first semiconductor layer310and the second semiconductor layer320. For example, in case that the active layer330emits light of a blue wavelength band, the active layer330may include a material such as AlGaN or AlGaInN. In particular, in case that the active layer330has a multiple quantum well structure in which quantum layers and well layers may be alternately stacked, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN. In an embodiment, the active layer330may include quantum layers including AlGaInN and well layers including AlInN, and may emit blue light having a center wavelength band ranging from about 450 nm to about 495 nm.

However, the disclosure is not limited thereto, and the active layer330may have a structure in which semiconductor materials having high band gap energy and semiconductor materials having low band gap energy may be alternately stacked with each other, and may include other Group 3 to Group 5 semiconductor materials depending on the wavelength band of emitted light. The light emitted by the active layer330may not be limited to light of a blue wavelength band, and in some cases, light of a red wavelength band or light of a green wavelength band may be emitted.

The second semiconductor layer320may be disposed on the active layer330. The second semiconductor layer320may include a semiconductor material having a formula of AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer320may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer320may include GaN, and GaN may be at least one of GaN doped with a n-type dopant, GaN doped with a p-type dopant, and undoped GaN.

In an embodiment, the second semiconductor layer320may include a p-type semiconductor having a second conductivity type. For example, the second semiconductor layer320may include at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN, which may be doped with a p-type dopant. The second semiconductor layer320may be doped with a second conductive dopant. For example, the second conductive dopant may be Mg, Zn, Ca, Se, or Ba. In an embodiment, the second semiconductor layer320may be n-GaN doped with p-type Mg, but is not limited thereto.

Although it is shown in the drawings that each of the first semiconductor layer310and the second semiconductor layer320is configured as one layer, the disclosure is not limited thereto. In some embodiments, each of the first semiconductor layer310and the second semiconductor layer320may include a larger number of layers, for example, clad layers or tensile strain barrier reducing (TSBR) layers.

Hereinafter, a process of manufacturing a stacked structure including a semiconductor structure according to an embodiment will be described with reference toFIGS.1to7.

FIG.2is a flowchart illustrating a method of manufacturing a stacked structure including a semiconductor structure according to an embodiment.FIGS.3to7are schematic cross-sectional views illustrating a process of manufacturing a stacked structure according to an embodiment.

Referring toFIG.2, a method of manufacturing a stacked structure10including a semiconductor structure300according to an embodiment may include forming a first metal buffer layer210on a base substrate110(S100), forming a second metal buffer material layer220′ on the first metal buffer layer210(S200), crystallizing the second metal buffer material layer220′ to form a second metal buffer layer220(S300), and forming a semiconductor structure300on the second metal buffer layer220(S400).

First, a first metal buffer layer210may be formed on abase substrate110(S100inFIG.2).

Specifically, referring toFIG.3, the base substrate110may include an amorphous substrate. As described above, the base substrate110may include a glass substrate as the amorphous substrate.

The first metal buffer layer210having crystal grains may be formed on the base substrate110. The grain density of crystal grains included in the first metal buffer layer210may have a first density. In the specification, the density of crystal grains may be understood as the number of grains included per unit volume. The first metal buffer layer210may include a material capable of having a structure that has crystal grains and may be self-aligned and oriented in a single direction on the base substrate110, which may be an amorphous substrate having no crystal structure. The first metal buffer layer210may include a material having a hexagonal close packed (HCP) crystal structure in consideration of the crystal structure of the first semiconductor layer310of the semiconductor structure300to be described later. The first metal buffer layer210may be formed to have a HCP crystal structure suitable for the epitaxial method of the first semiconductor layer310formed on the second metal buffer layer220and the second metal buffer layer220, thereby improving the quality of the semiconductor structure. For example, the first metal buffer layer210may include Be, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Hf, Ta, W, Re, Os, Lr, Pt, Au, Hg, Pb, Tl, a combination thereof, or a nitride thereof, but the material thereof is not limited thereto. The first metal buffer layer210may include Ti or TiN, but the material thereof is not limited thereto.

The first metal buffer layer210may be formed on a surface of the base substrate110by a method such as sputtering, vacuum deposition, or plasma laser deposition (PLD). In an embodiment, the first metal buffer layer210may be formed by sputtering, but the disclosure is not limited thereto. In order to have a structure in which the first metal buffer layer210may be oriented in a single direction with predetermined crystal grains on the base substrate110, which may be an amorphous substrate, process conditions of a sputtering process may be adjusted. For example, sputtering of the first metal buffer layer210may be performed by first DC power. For example, the first metal buffer layer210may include Ti, and the first DC power may be about 200 W.

Although not shown in the drawing, the first metal buffer layer210may be formed on a surface of the base substrate110, and a heat treatment process may be further performed to improve the crystallinity of the first metal buffer layer210. The heat treatment process may be performed at a temperature lower than the phase transition temperature of the metal material included in the first metal buffer layer210. Since the heat treatment process may be performed at a temperature lower than the phase transition temperature of the metal material included in the first metal buffer layer210, the crystallinity of the first metal buffer layer210may be improved.

Further, after the first metal buffer layer210may be formed on a surface of the base substrate110, a heat treatment process performed at a high temperature may be required so as to improve the crystallinity of the first metal buffer layer210to obtain a desired crystal structure. After the process of forming the first metal buffer layer210may be performed to obtain a desired crystal structure by increasing the phase transition temperature of the metal material included in the first metal buffer layer210, the first metal buffer layer210may be doped with an element such as Carbon (C), Oxygen (O), or Nitrogen (N). In case that a heat treatment process is performed after doping the first metal buffer layer210with an element such as C, O, or N, the phase transition temperature of the material included in the first metal buffer layer210may be increased, so that the heat treatment process may be performed at a high temperature, thereby obtaining a desired crystal structure.

Subsequently, a second metal buffer material layer220′ may be formed on the first metal buffer layer210(S200inFIG.2).

The second metal buffer material layer220′ may be formed on the first metal buffer layer210. The second metal buffer material layer220′ may not include crystal grains or may include crystal grains whose distribution thereof may be smaller than a distribution of crystal grains included in the first metal buffer layer210. The density of crystal grains included in the second metal buffer material layer220′ may have a second density. The second density may be smaller than the first density. The second metal buffer material layer220′ may include a material having a hexagonal close packed (HCP) crystal structure in consideration of the crystal structure of the first semiconductor layer310of the semiconductor structure300to be described later, but the disclosure is not limited thereto. For example, the second metal buffer material layer220′ may not have a crystal structure.

The second metal buffer material layer220′ may be formed on a surface of the first metal buffer layer210by a method such as sputtering, vacuum deposition, or plasma laser deposition (PLD). In an embodiment, the second metal buffer material layer220′ may be formed by sputtering, but the disclosure is not limited thereto. The second metal buffer material layer220′ may have a smaller distribution ratio of crystal grains than the first metal buffer layer210. In order for the second metal buffer material layer220′ to have a smaller distribution ratio of crystal grains than the first metal buffer layer210, process conditions for a sputtering process for forming the second metal buffer material layer220′ may be adjusted. For example, sputtering of the second metal buffer material layer220′ may be performed by second DC power lower than the first DC power. For example, the second metal buffer material layer220′ may include Ti, and the second DC power may be about 100 W.

Subsequently, the second metal buffer material layer220′ may be crystallized to form a second metal buffer layer220(S300inFIG.2).

Specifically, referring toFIGS.4and5, a second metal buffer layer220containing crystal grains as shown inFIG.5may be formed by crystallizing the second metal buffer material layer220′ containing little or no crystal grains. Although not limited thereto, a process of crystallizing the second metal buffer material layer220′ into the second metal buffer layer220may be performed through a heat treatment process. The heat treatment process may be performed at a temperature lower than the phase transition temperature of the metal material included in the second metal buffer material layer220′. Since the heat treatment process may be performed at a temperature lower than the phase transition temperature of the metal material included in the second metal buffer material layer220′, the crystallinity of the second metal buffer material layer220′ may be improved, so that the second metal buffer layer220may be formed.

Although not shown in the drawings, the step of forming the second metal buffer layer220by crystallizing the second metal buffer material layer220′ may include a step of doping the second metal buffer material layer220′ with an element such as C, O, or N, and a step of heat-treating the doped second metal buffer material layer220′. Specifically, in order to obtain a desired crystal structure by improving the crystallinity of the second metal buffer material layer220′, a heat treatment process performed at a high temperature may be required. After the process of forming the second metal buffer material layer220′ may be performed to obtain a desired crystal structure by increasing the phase transition temperature of the metal material included in the second metal buffer material layer220′, the second metal buffer material layer220′ may be doped with an element such as C, O, or N. In case that a heat treatment process is performed after doping the second metal buffer material layer220′ with at least one of C, O, and N, the phase transition temperature of the material included in the second metal buffer material layer220′ may be increased, so that the heat treatment process may be performed at a high temperature, thereby forming the second metal buffer layer220having a desired crystal structure.

Subsequently, a semiconductor structure300may be formed on the second metal buffer layer220(S400inFIG.2).

The step of forming the semiconductor structure300on the second metal buffer layer220may include a step of forming a first semiconductor layer310on the second metal buffer layer220, a step of forming an active layer330on the first semiconductor layer310, and a step of forming a second semiconductor layer320on the active layer330.

Specifically, referring toFIG.6, the first semiconductor layer310may be formed on the second metal buffer layer220. In the method of forming the first semiconductor layer310, the first semiconductor layer310may be formed by growing a surface of the second metal buffer layer220by an epitaxial method. For example, the first semiconductor layer310may be formed using the second metal buffer layer220as a seed layer.

In the method of forming the first semiconductor layer310, the first semiconductor layer310may be formed using electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), or the like. In an embodiment, the first semiconductor layer310may be formed by physical vapor deposition (PVD), but the disclosure is not limited thereto.

The first semiconductor layer310may be grown using the second metal buffer layer220as a buffer layer. The first semiconductor layer310may be formed by growing GaN on the second metal buffer layer220. The growth temperature for forming the first semiconductor layer310may be adjusted to be lower than the phase transition temperature of the metal material included in the first and second metal buffer layers210and220. Further, the growth temperature for forming the first semiconductor layer310may be adjusted to a temperature at which a glass substrate may not be damaged in case that the base substrate110includes the glass substrate. For example, the growth temperature for forming the first semiconductor layer310may have a temperature range of about 800° C. or lower.

As described above, the process for growing the first semiconductor layer310at a temperature lower than the phase transition temperature of the metal materials included in the first and second metal buffer layers210and220without damaging the glass substrate may be performed by physical vapor deposition (PVD). In other embodiments, the process for growing the first semiconductor layer310may be performed by RF sputtering or pulsed DC sputtering.

Subsequently, referring toFIG.7, an active layer330may be formed on the first semiconductor layer310. The active layer330may include a material having a single or multiple quantum well structure. In case that the active layer330includes a material having a multiple quantum well structure, the active layer330may have a structure in which quantum layers and well layers may be alternately stacked with each other. As described above, the active layer330may be formed by a process listed as the process for forming the first semiconductor layer310.

Subsequently, referring toFIG.1, a second semiconductor layer320may be formed on the active layer330. The second semiconductor layer320may include GaN doped with a p-type dopant. Similarly, the second semiconductor layer320may also be formed by a process listed as the process for forming the first semiconductor layer310.

According to the process of manufacturing the stacked structure10according to an embodiment, in case that the base substrate110includes an amorphous substrate, semiconductor layers may be grown on the base substrate110by controlling their directions and positions. Specifically, the first and second metal buffer layers210and220having a crystal structure may be formed on the base substrate110, so that the first semiconductor layer310may be grown by reflecting the crystal structure of the first and second metal buffer layers210and220. Accordingly, in the process of manufacturing the stacked structure10according to an embodiment, a semiconductor layer having high crystallinity may be grown even on the base substrate110that may be inexpensive and capable of large area, so that it may be possible to reduce the manufacturing cost for manufacturing a semiconductor device.

FIG.8is a schematic graph illustrating a pattern of analyzing a metal buffer layer formed on a base substrate with an X-ray diffraction analyzer (XRD).

FIG.8is a schematic graph illustrating a pattern analyzed with an X-ray diffraction analyzer (XRD) for the result of forming a metal buffer layer containing Ti as a single layer by sputtering at a temperature of about 700° C. or less, which may be the maximum heat treatment temperature of a glass substrate, on an amorphous glass substrate. InFIG.8. the metal buffer layer #1 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as a single layer with a sputter power of about DC100 W at a process temperature of about 700° C. The metal buffer layer #2 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as a single layer with a sputter power of about DC100 W at a process temperature of about 600° C. The metal buffer layer #3 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as a single layer with a sputter power of about DC100 W at a process temperature of about 500° C. The metal buffer layer #4 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as a single layer with a sputter power of about DC100 W. Referring toFIG.8, it may be found that the crystal structure of the metal buffer layer #1 formed at about 700° C., which may be the maximum heat treatment temperature of the glass substrate, may be biased toward a FCC structure. In case that the crystal structure of the metal buffer layer has an FCC structure, it may be disadvantageous in the growth of the first semiconductor layer grown on the metal buffer layer by an epitaxial method.

FIG.9is a schematic graph illustrating a pattern analyzed by an X-ray diffraction analyzer (XRD) in case that first and second metal buffer layers are formed as layers on a base substrate.

FIG.9is a schematic graph illustrating a pattern analyzed with an X-ray diffraction analyzer (XRD) for the result of forming a metal buffer layer containing Ti as a single layer or double layers by sputtering at a temperature of about 700° C. or less, which may be the maximum heat treatment temperature of a glass substrate, on an amorphous glass substrate. InFIG.9. the metal buffer layer #1 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as a single layer at a process temperature of about 700° C. The metal buffer layer #2 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as double layers with about hp-Ti(700s)/Ti at a process temperature of about 700° C. The metal buffer layer #3 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as double layers with about hp-Ti(2100s)/Ti at a process temperature of about 700° C. The metal buffer layer #4 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as double layers with about hp-Ti(4200s)/Ti at a process temperature of about 700° C. The metal buffer layer #5 may be obtained by forming a metal buffer layer containing Ti on a glass substrate as double layers with about hp-Ti(6300s)/Ti at a process temperature of about 700° C. In the specification, about hp-Ti (700s) may mean that a metal buffer layer including Ti may be deposited for about 700 seconds at high power. For example, hp may refer to high power, and the number in parentheses may refer to process time for depositing the metal buffer layer containing Ti. As shown inFIG.9, it may be found that the metal buffer layer #1 formed as a single layer has a crystal structure of FCC, and each of the metal buffer layer #2, the metal buffer layer #3, the metal buffer layer #4, and the metal buffer layer #5 formed as double layers has a crystal structure of Hex (or HCP) without being biased toward FCC. Accordingly, the metal buffer layer may be formed as double layers in two steps, thereby improving the crystallinity of the first semiconductor layer even in case that the base substrate is a glass substrate.

Hereinafter, a light emitting element formed by using the aforementioned stacked structure10including the base substrate110, the metal buffer layer200, and the semiconductor structure300, and/or a display device including the light emitting element will be described. A case where the stacked structure10may be applied to a light emitting element and/or a display device including the light emitting element will be described as an example, but the disclosure is not limited thereto, and the aforementioned stacked structure10may be applied to various semiconductor devices.

FIG.10is a schematic view of a light emitting element according to an embodiment.

Referring toFIG.10, a first light emitting element ED1according to an embodiment may be a particulate element, and may have a rod shape or a cylindrical shape having a predetermined aspect ratio. The length of the first light emitting element ED1may be larger than the diameter of the first light emitting element ED1, and the aspect ratio thereof may be 6:5 to 100:1, but is not limited thereto.

The first light emitting element ED1may have a size of a nano-meter scale (about 1 nm or more and less than about 1 μm) to a micrometer scale (about 1 μm or more and less than about 1 mm). In an embodiment, both diameter and length of the first light emitting element ED1may have a size of a nanometer scale, or may have a size of a micrometer scale. In some embodiments, the diameter of the first light emitting element ED1may have a size of a nanometer scale, while the length of the first light emitting element ED1may have a size of a micrometer scale. In some embodiments, some of the first light emitting element ED1may have a size of a nanometer scale in diameter and/or length, while others of the first light emitting element ED1may have a size of a micrometer scale in diameter and/or length.

In an embodiment, the first light emitting element ED1may be an inorganic light emitting diode. The inorganic light emitting diode may include semiconductor layers. For example, the inorganic light emitting diode may include a first conductive (for example, n-type) semiconductor layer, a second conductive (for example, p-type) semiconductor layer, and an active semiconductor layer interposed therebetween. The active semiconductor layer may receive holes and electrons from the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, respectively, and the holes and electrons having reached the active semiconductor layer may be combined with each other to emit light.

In an embodiment, the above-described semiconductor layers may be sequentially stacked along the length direction of the first light emitting element ED1. As shown inFIG.10, the first light emitting element ED1may include a light emitting element core30and an insulating layer38surrounding the outer circumferential surface of the light emitting element core30.

The light emitting element core30may include a first semiconductor31, an element active layer33, a second semiconductor32, and an element electrode layer37, which may be sequentially stacked in the length direction of the first light emitting element ED1. The first semiconductor31, the element active layer33, and the second semiconductor32may be the above-described first conductive semiconductor layer, active semiconductor layer, and second conductive semiconductor layer, respectively. Further, the first semiconductor31, element active layer33, and second semiconductor32of the first light emitting element ED1may correspond to the first semiconductor layer310, the active layer330, and the second semiconductor layer320, which have been described with reference toFIG.1, respectively.

The first semiconductor31may be doped with a first conductive dopant. The first conductive dopant may be at least one of Si, Ge, Sn, or the like. In an embodiment, the first semiconductor31may be n-GaN doped with n-type Si.

The second semiconductor32may be disposed to be spaced apart from the first semiconductor31with the element active layer33interposed therebetween. The second semiconductor32may be doped with a second conductive dopant such as at least one of Mg, Zn, Ca, Se, or Ba. In an embodiment, the second semiconductor32may be p-GaN doped with p-type Mg.

The element active layer33may include a material having a single or multiple quantum well structure. As described above, the element active layer33may emit light by combination of an electron-hole pair according to an electric signal applied through the first semiconductor31and the second semiconductor32. In some embodiments, the active layer33may have a structure in which semiconductor materials having high band gap energy and semiconductor materials having low band gap energy may be alternately stacked with each other, and may include other Group 3 to Group 5 semiconductor materials depending on the wavelength band of emitted light.

Light emitted from the element active layer33may be emitted not only to the outer surface of the first light emitting element ED1in the length direction, but also to both side surfaces thereof. For example, the direction of light emitted from the element active layer33may not be limited to one direction.

The element electrode layer37may be disposed on the second semiconductor32. The element electrode layer37may be in contact with the second semiconductor32. The element electrode layer37may be an ohmic contact electrode, but is not limited thereto, and may be a Schottky contact electrode.

In case that ends of the first light emitting element ED1are electrically connected to electrodes so as to apply electric signals to the first semiconductor31and the second semiconductor32, the electrode layer37may be disposed between the second semiconductor32and the electrodes to reduce resistance. The element electrode layer37may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin-zinc oxide (ITZO). The element electrode layer37may include a semiconductor material doped with an n-type or p-type dopant.

The insulating layer38may be disposed to surround an outer peripheral surface of the light emitting element core30. The insulating layer38may be disposed to surround at least an outer surface of the element active layer33and may extend in one direction in which the first light emitting element ED1extends. The insulating layer38may perform a function of protecting the members. The insulating layer38may be made of a material having insulating properties, and may prevent an electric short that may occur in case that the element active layer33is in direct contact with an electrode through which an electric signal may be transmitted to the first light emitting element ED1. Further, since the insulating film38protects the outer peripheral surfaces of the first and second semiconductors31and32and the element active layer33, it may be possible to prevent a decrease in light emission efficiency.

Hereinafter, a process of manufacturing the first light emitting element according to an embodiment will be described with reference toFIGS.1and11to15.

FIGS.11to15are schematic cross-sectional views illustrating a process of manufacturing the first light emitting element ofFIG.10.

FIGS.11to15illustrate processes after the process of manufacturing the stacked structure10described above with reference toFIGS.1to7. Hereinafter, the method or process conditions for forming the stacked structure10including the base substrate110, the metal buffer layer200, and the semiconductor structure300described above with reference toFIGS.1to7will be omitted, and the order of the method of manufacturing the first light emitting element ED1and the stacked structure will be described in detail, as a process after forming the stacked structure10.

First, referring toFIG.11, a stacked structure10including a base substrate110, a metal buffer layer200formed on the base substrate110, and a semiconductor structure300formed on the metal buffer layer200may be prepared.

Specifically, referring toFIG.11, an electrode material layer370may be formed on a second semiconductor layer320of the stacked structure10using electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), or the like, but the disclosure is not limited thereto.

The first semiconductor layer310, active layer330, and second semiconductor layer320included in the semiconductor structure300may correspond to the first semiconductor31, element active layer33, and second semiconductor32of the first light emitting element ED1, respectively. Specifically, the first semiconductor layer310, the active layer330, the second semiconductor layer320, and the electrode material layer370may be layers including the same materials as the first semiconductor31, element active layer33, the second semiconductor32, and element electrode layer37of the first light emitting element ED1.

Subsequently, the semiconductor structure300and the electrode material layer370may be vertically etched to form light emitting element cores30spaced apart from each other.

Specifically, referring toFIG.12, a vertical direction in which the semiconductor structure300and the electrode material layer370may be etched may be parallel to the stacking direction of the layers. The semiconductor structure300and the electrode material layer370may be etched by an etching method. For example, an etching mask layer may be formed on the electrode material layer370, and the semiconductor structure300and the electrode material layer370may be etched along the etching mask layer in a direction perpendicular to the base substrate110. A space may be formed between the light emitting element cores30by the etching process. Further, the first and second metal buffer layers210and220may remain without being etched by the etching process.

For example, the etching process for forming the light emitting element core30spaced apart from each other may be formed by dry etching, wet etching, reactive ion etching (RIE), or inductively coupled plasma reactive ion etching (ICP-RIE). In the case of dry etching, anisotropic etching may be possible, so it may be suitable for vertical etching. In case of using the above-described etching method, an etchant may be Cl2or O2. However, the disclosure is not limited thereto.

In some embodiments, the etching process for forming the light emitting element cores30may be performed by combination of dry etching and wet etching. For example, first, etching in the depth direction may be performed by dry etching, and wet etching, which may be isotropic etching, may be performed, to allow the etched sidewalls to be placed on a plane perpendicular to the surface.

Subsequently, an insulating material layer380may be formed on the light emitting element core30.

Specifically, referring toFIG.13, the insulating material layer380may be formed entirely on the light emitting element core30. The insulating material layer380may be formed on the side and upper surfaces of the light emitting element core30and the upper surface of the second metal buffer layer220exposed to the area between the light emitting element cores30.

The insulating material layer380may be formed using a method of applying or immersing an inorganic material on the outer surface of the light emitting element core30. However, the disclosure is not limited thereto. For example, the insulating material layer380may be formed by atomic layer deposition (ALD). Although it is shown in the drawing that the insulating material layer380may be formed as a single layer, the disclosure is not limited thereto. In case that the insulating material layer380has a multi-layer structure including insulating material layers, the insulating material layer380may be formed by sequentially stacking insulating layers.

Subsequently, a part of the insulating material layer380may be partially removed to form first light emitting elements ED1on the metal buffer layer200.

Specifically, referring toFIGS.13and14, the insulating material layer380covering the upper and side surfaces of the light emitting element core30may be partially removed to form an insulating layer38exposing the upper surface of the light emitting element core30and surrounding the side surface of the light emitting element core30. The process of partially removing the insulating material layer380may be performed by dry etching or back etching, which may be anisotropic etching. Through this etching process, the insulating material layer380disposed on the second metal buffer layer220exposed in the area where the light emitting cores30may be spaced apart from each other may be partially removed.

Subsequently, the first light emitting element ED1may be separated from the base substrate110.

Specifically, referring toFIG.15, a first light emitting element ED1according to an embodiment may be manufactured by separating the first light emitting element ED1from the base substrate110, specifically, the second metal buffer layer220. The method of separating the first light emitting device ED1from the second metal buffer layer220is not particularly limited. The process of separating the first light emitting device ED1from the second metal buffer layer220may be performed by a physical separation method or a chemical separation method.

In an embodiment, the first light emitting element ED1including semiconductor layers may be formed by growth on the base substrate110, which may be an amorphous substrate, by an epitaxial method. Specifically, the first light emitting element ED1may be manufactured through a subsequent process after forming a semiconductor structure300including a base substrate110, a metal buffer layer200, first and second semiconductor layers310and320, and an active layer330. The first semiconductor layer310of the stacked structure10corresponding to the semiconductor layers included in the first light emitting device ED1, for example, the first semiconductor31including GaN, may be difficult to grow directly on the base substrate110, which may be an amorphous substrate, by epitaxial method, and may be grown in any direction without orientation. Accordingly, in case that the base substrate110is an amorphous substrate, the first and second metal buffer layers210and220having a structure in which crystal grains may be aligned in a single direction regardless of the crystal structure of the base substrate110may be formed on the base substrate110, so that seed crystals may be formed by the first and second metal buffer layers210and220. Further, since the first and second metal buffer layers210and220having a crystalline structure may be formed on the base substrate110, a difference in lattice constant between the base substrate110and the first semiconductor layer310may be reduced although the base substrate110may be an amorphous substrate, thereby improving manufacturing quality of the first light emitting element ED1. Since the first light emitting element ED1may be manufactured using the base substrate110including a glass substrate less costly than a sapphire substrate, a silicon substrate, or a quartz substrate through the above-described process, manufacturing cost of the light emitting element may be reduced.

FIG.16is an exploded schematic perspective view of a display device according to an embodiment.FIG.17is a schematic cross-sectional view of the display device taken along line I-I′ ofFIG.16.

Referring toFIGS.16and17, a display device1, which may be a device for display an image, may be applied to various electronic appliances such as televisions, external billboards, monitors, personal computers, notebook computers, tablet PCs, smart phones, car navigation units, cameras, center information displays (CIDs) for automobiles, wristwatch type electronic appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), and game machines. These electronic appliances are only presented as examples, and the display device may be employed in other electronic appliances without departing from the concept of the disclosure.

Hereinafter, in the drawings for explaining the display device1, a third direction X, a fourth direction Y, and a fifth direction Z are defined. The third direction X and the fourth direction Y may be directions perpendicular to each other in one plane. The fifth direction Z may be a direction perpendicular to a plane in which the third direction X and the fourth direction Y may be located. The fifth direction Z may be perpendicular to each of the third direction X and the fourth direction Y. In embodiments, the fifth direction Z represents a thickness direction of the display device1.

Unless otherwise specified, the “upper” or “upper side” represents a thickness direction (upper side in the drawing) of the display device1in one side of the fifth direction Z, and likewise, the “upper surface” represents a surface facing one side in the fifth direction Z. Further, the “lower” or “lower side” represents a direction (lower side in the drawing) opposite to the thickness direction of the display device1in the other side of the fifth direction Z, and likewise, the “lower surface” represents a surface facing the other side in the fifth direction Z. These terms are spatially relative and should encompass other orientations such as may occur when a device is turned over, etc.

The display device1may have a rectangular shape including long sides in the third direction X and short sides in the fourth direction Y in a plan view. In a plan view, the corner where the long side of the display device1meets the short side of the display device1may have a right-angled shape, but the disclosure is not limited thereto, and may have a rounded curved shape. The planar shape of the display device1is not limited to the disclosed embodiment, and the display device1may have a square shape, a circular shape, an elliptical shape, or other polygonal shapes. The display surface of the display device1may be disposed at one side of the fifth direction Z, which may be a thickness direction.

The display device1may include a display panel50, a light-emitting unit (e.g., a backlight unit)20disposed under the display panel50to provide light to the display panel50, and a housing70accommodating the display panel50and the light-emitting unit20. However, the disclosure is not limited thereto, and the display device1may omit any one of the members or include a larger number of members.

The display panel50may, in an embodiment, receive light emitted from the light-emitting unit20to display an image. In an embodiment, the display panel50may be a light-receiving display panel. For example, the display panel50may be a liquid crystal display panel, an electrowetting display panel, an electrophoretic display panel, or the like. However, the description of the display panel50is not limited to the above mentioned types but may be applied to any type of display panel.

The display panel50may include pixels. The pixels of the display panel50may be arranged in a matrix direction. The display panel50may include a switching element provided for each pixel, a pixel electrode, and a common electrode facing the pixel electrode.

As shown inFIG.17, the display panel50may include an upper substrate510, a lower substrate520facing the upper substrate510, and a switching layer530disposed therebetween. The pixels of the display panel50may be arranged in a matrix direction. The display panel50may include a switching element provided for each pixel, a pixel electrode, and a common electrode facing the pixel electrode. The switching element and the pixel electrode may be disposed on the lower substrate520, and the common electrode may be disposed on the upper substrate510. However, the disclosure is not limited thereto, and the common electrode may also be disposed on the lower substrate520. A sealing member92may be disposed at the edges of the upper substrate510and the lower substrate520to confine molecules of the switching layer530(e.g., in an embodiment, crystal molecules of a liquid crystal layer).

The light-emitting unit20may be disposed under the display panel50. The light-emitting unit20may include a light source member100, a wavelength conversion layer410, a diffusion plate420, and an optical film430.

The light source member100may include a base substrate110and second light emitting elements ED2disposed on the base substrate110. The second light emitting element ED2may emit light provided to the display panel50. Light emitted from the second light emitting element ED2may be incident on the overlying wavelength conversion layer410.

The base substrate110may include an amorphous substrate. As described above, the base substrate110may include a glass substrate. The second light emitting elements ED2may be disposed on the base substrate110. Specifically, the second light emitting elements ED2may be manufactured by performing a subsequent process on the stacked structure10including the semiconductor structure300formed on the above-described base substrate110. Details thereof will be described later.

The wavelength conversion layer410may be disposed on the light source member100to overlap the light source member100. The conversion layer410may be entirely disposed on the light source member100or may be partially disposed on the second light emitting elements ED2to surround the second light emitting elements ED2. The wavelength conversion layer410may convert the wavelength of at least a part of incident light. In an embodiment, the wavelength conversion layer410may be disposed on the light source member100to be spaced apart from the light source member100in the fifth direction Z in a film form.

The wavelength conversion layer410may include a binder layer and wavelength conversion particles dispersed in the binder layer. The wavelength conversion layer410may further include scattering particles dispersed in the binder layer in addition to the wavelength conversion particles.

The binder layer may be a medium in which wavelength conversion particles may be dispersed, and may be made of various resin compositions. However, the disclosure is not limited thereto, and any medium capable of dispersing and distributing wavelength converting particles and/or scattering particles may be referred to as a binder layer regardless of its name, additional other functions, and constituent materials.

The wavelength conversion particle may be a particle that converts the wavelength of incident light, and may be, for example, a quantum dot (QD), a fluorescent material, or a phosphorescent material.

The wavelength conversion particles may include multiple wavelength conversion particles that convert incident light into light of different wavelengths. For example, the wavelength conversion particles may include first wavelength conversion particles that convert incident light of a specific wavelength into light of a first wavelength and emit the light of a first wavelength, and second wavelength conversion particles that convert incident light of a specific wavelength into light of a second wavelength and emit the light of a second wavelength.

The diffusion plate420may be disposed over the wavelength conversion layer410. The diffusion plate420may be disposed to be spaced apart from the wavelength conversion layer410in the fifth direction Z. The diffusion plate420performs a function of diffusing light emitted from the wavelength conversion layer410to the display panel50to serve to provide the light emitted from the second light emitting element ED2to the display panel50with more uniform luminance.

The diffusion plate420may include a light-transmitting material. For example, the diffusion plate420may include a material such as polymethyl methacrylate (PMMA), polystyrene (PS), polypropylene (PP), polyethylene terephthalate (PET), polycarbonate (PC), or a combination thereof. However, the material of the diffusion plate420is not limited thereto.

The optical film430may be disposed on the diffusion plate420. The display device1may include at least one optical film430, and the number thereof is not particularly limited. Although it is shown in the drawing that the optical film430is disposed to be spaced apart from the diffusion plate420and the display panel50in the fifth direction Z, the disclosure is not limited thereto. In some cases, the optical film430may be disposed to be in contact with the diffusion plate420and the display panel50. The optical film430may perform optical functions such as condensing, refraction, diffusion, reflection, polarization and phase retardation for incident light. Examples of the optical film430may include a prism film, a microlens film, a lenticular film, a polarizing film, a reflective polarizing film, a retardation film, and a protective film.

The housing70may accommodate the light-emitting unit20and the display panel50. The housing70may include a bottom chassis or bracket. Although not shown in the drawings, the housing70may further include a top chassis.

The housing70may include a bottom surface71and a side wall72. The side wall72of the housing70may be connected to the bottom surface71thereof, and may be bent from the bottom surface71thereof in a vertical direction. The light source member100of the light-emitting unit20may be disposed on the bottom surface71of the housing70. The diffusion plate420and optical film430of the backlight unit20and the display panel50may be fixed to the side wall72of the housing70through an adhesive tape91. However, the disclosure is not limited thereto, and the above-described members may be mounted on another mounting structure of the housing70or may be mounted on or attached to a mold frame provided inside the housing70.

Hereinafter, the light source member100will be described in detail.

FIG.18is an enlarged schematic cross-sectional view illustrating an example of a light source member included in a display device according to an embodiment.

Referring toFIG.18, a light source member100according to an embodiment may include a base substrate110, a metal buffer layer200disposed on the base substrate110, and a second light emitting element ED2formed on the metal buffer layer200.

The base substrate110may include an amorphous substrate. For example, the base substrate110may include a glass or plastic substrate as an amorphous substrate. In an embodiment, the base substrate110may include a glass substrate.

The metal buffer layer200may be provided on the base substrate110. The metal buffer layer200may include a first metal buffer layer210and a second metal buffer layer220.

The first metal buffer layer210may be formed on the base substrate110. The first metal buffer layer210may be formed to reduce a difference in lattice constant between the first semiconductor layer31_1of the second light emitting element ED2and the base substrate110in order to form the second light emitting element ED2on the base substrate110, which may be an amorphous substrate having no crystal structure. The first metal buffer layer210may include a metal material having a hexagonal close-packed (HCP) structure or a face-centered cubic (FCC) structure as a crystal structure. The crystal structure of the first metal buffer layer210may include a hexagonal close-packed (HCP) structure. The first metal buffer layer210may include a metal having a small difference in lattice constant from the first semiconductor layer31_1of the second light emitting element ED2. The first metal buffer layer210may include at least one of the materials listed as materials that may be included in the first metal buffer layer210of the stacked structure10described above with reference toFIG.1.

The second metal buffer layer220may be formed on the first metal buffer layer210. The second metal buffer layer220may be used as a seed layer to form the stacked structure10including the semiconductor structure300ofFIG.1for forming the second light emitting element ED2.

The second light emitting element ED2may be disposed on the second metal buffer layer220. The second light emitting element ED2may include a first semiconductor layer31_1, an element active layer33_1, and a second semiconductor layer321. The light emitting element ED1may further include a first electrode41and a second electrode42.

The first semiconductor layer31_1, element active layer33_1, and second semiconductor layer32_1of the second light emitting element ED2may correspond to the first semiconductor layer310, active layer330, and second semiconductor layer320described above with reference toFIG.1, respectively. The first semiconductor layer31_1, element active layer33_1, and second semiconductor layer32_1of the second light emitting element ED2may include the same materials as the first semiconductor31, element active layer33, and second semiconductor32of the above-described first light emitting element ED1, respectively.

The second light emitting element ED2may receive electric signals from an external device through the first electrode41formed on the first semiconductor layer31_1and the second electrode42formed on the second semiconductor layer32_1. The first electrode41and the second electrode42may include a conductive material, and may thus transmit electric signals transmitted from an external device or a transistor to the first semiconductor layer31_1and the second semiconductor layer32_1. However, the structure of the second light emitting element ED2is not limited thereto, and in some embodiments, may have other structures.

In the optical member100according to an embodiment, after the first and second metal buffer layers210and220may be formed on the base substrate110, the second light emitting element ED2may be formed on the second metal buffer layer220, thereby reducing a difference in lattice constant between the first semiconductor layer31_1of the second light emitting element ED2and the base substrate110. Further, second light emitting elements ED2may be formed on the base substrate110including a glass substrate, and the second light emitting elements ED may be used as the light source member100, thereby omitting a process of separating and reassembling the second light emitting elements ED2from the base substrate110having the second light emitting elements ED2formed thereon. For example, the base substrate110including the glass substrate may be used as the base substrate110in the process of forming the second light emitting element ED2and simultaneously used as the light source member100of the display device1, thereby improving the manufacturing efficiency of the display device1. Further, a glass substrate less costly than a sapphire substrate, a silicon substrate or a quartz substrate may be used as the base substrate110for forming the second light emitting element ED2, so that the manufacturing cost of the display device1may be reduced.

FIG.19is an enlarged schematic cross-sectional view illustrating another example of a light source member included in a display device according to an embodiment.

Referring toFIG.19, a light source member100_1according to an embodiment may be different from the light source member100ofFIG.18in that the first electrode41may be disposed on the second metal buffer layer220.

Specifically, the first electrode41may be formed on the second metal buffer layer220. As described above, since the second metal buffer layer220includes a metal material, it may function as an electrode for applying an electric signal to the first semiconductor layer31_1formed on the second metal buffer layer220. Accordingly, the first electrode41may be formed on the second metal buffer layer220, thereby applying electric signals to the second light emitting element ED2_1through the first electrode41and the second metal buffer layer220. The first electrode41may be omitted.

In an embodiment, the first electrode41may be formed on the second metal buffer layer220, so that the second metal buffer layer220may be used as an electrode for applying an electric signal to the second light emitting element ED2_1. The second metal buffer layer220aligned in a single orientation and formed by an epitaxial method may have excellent electrical conductivity as compared with a metal layer aligned in multiple orientations. Accordingly, the light emission performance of the second light emitting element ED2_1using the second metal buffer layer220as an electrode may be improved.

Although embodiments have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure.