Patent ID: 12230598

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring toFIGS.1to3,FIG.1illustrates a diagram view of a semiconductor package100according to an embodiment of the invention, andFIGS.2and3illustrate top views of configuration relationships between the package module120and the second electronic element150ofFIG.1.

As illustrated inFIG.1, the semiconductor package100includes a carrier110, a package module120, a first adhesive layer125, a second package body130, at least one second conductive wire140, at least one second electronic element150, a second adhesive layer155and at least one third electronic element160. In the present embodiment, the conductive wire could be made of a material including, for example, Au, Ag, Cu, Ni, etc.

The package module120is disposed on the carrier110and includes a first substrate121, at least one first electronic element122, at least one first conductive wire123and a first package body124. The first substrate121has a first electrical surface121bfacing the carrier110and a second electrical surface121uopposite to the first electrical surface121b. The first electronic elements122are disposed on the first electrical surface121b. The first conductive wires123connect the first electronic elements122with the first electrical surface121bof the first substrate121. The first package body124encapsulates the first electrical surface121b, the first electronic element122and the first conductive wires123. The second package body130encapsulates the package module120and a portion of the carrier110.

Compared to the conductive wire being bonded to the carrier110, the conductive wire could more reliably (or steadily) be boned to the package module120. In other words, due to the package module120provides a steady platform, it could increase the stability of the wire bonding and reduce the complexity of the wire bonding. In addition, due to the electronic elements122being embedded in the first package body124in advance, the required number of the second conductive wires140could be reduced and/or it could reduce the complexity of the wire bonding.

The carrier110is, for example, lead frame. The carrier110includes a plurality of inner leads111, a plurality of outer leads112, a grounding ring113and a die pad114, wherein each the outer lead112is connected to the corresponding inner lead111, and the grounding ring113could be connected to one or some of the inner leads111. The inner leads111and the grounding ring113are encapsulated by the second package body130, and the outer leads112protrude relative to the second package body130for electrically connected with an external electronic device. For example, Printed Circuit Board (PCB). The die pad114could carry the package module120.

The package module120further has a package surface120baway from the second electrical surface121u. The package surface120bfaces the carrier110, and the second electrical surface121ufaces away from the carrier110.

The first substrate121has, for example, single-layered structure or multi-layered structure. In the present embodiment, the first substrate121has multi-layered structure including at least one dielectric layer1211, at least one conductive layer1212and at least one conductive via1213. In addition, the dielectric layer1211could be made of a material of non-conductive material, for example, epoxy or resin. Two of the conductive layers1212are separated from each other by one of the dielectric layers1211, and electrically connected with each other by one of the conductive vias1213. Each conductive layer1212includes at least one trace, and at least one conductive via1213connects with the traces of the conductive layers1212. In addition, the bottommost conductive layer1212includes at least one trace and/or pad which form the first electrical surface121b, and the bottommost conductive layer1212could be covered by solder mask (not illustrated) exposing the pad. The topmost dielectric layer1212includes at least one trace and/or pad which form the second electrical surface121u, and the topmost conductive layer1212could be covered by solder mask (not illustrated) exposing the pad.

In another embodiment, the first substrate121is, for example, a PCB, interposer, etc.; however, such exemplification is not meant to be for limiting.

Some of the first electronic elements122could be stacked each other and/or a group of the stacked first electronic elements122and another group of the stacked first electronic elements122are disposed side by side. The number of a group of the stacked first electronic elements122is, for example, two, three or more. The number of the stacked group including the stacked first electronic elements122is, for example, one, two, three or more. In another embodiment, two first electronic elements122on which no first electronic element122is stacked are disposed with side by side, or one first electronic element122on which no first electronic element122is stacked and one stacked group of are disposed with side by side.

The first electronic element122is, for example, memory chip, Sop (System on a Chip), etc.; however, such exemplification is not meant to be for limiting. In addition, the first electronic element122has an active surface122afacing the carrier110, that is, the first electronic element122is disposed in a reverse orientation and at least one of the first conductive wire123electrically connects the active surface122aof at least one of the first electronic elements122with the first electrical surface121b. The first electronic element122has a back surface122bopposite to the active surface122a, and the back surface122bfaces the first substrate121. In addition, the package module120further includes at least one adhesive layer126disposed between the active surface122aof the electronic element122with the back surface122bof the electronic element122.

At least one of the first conductive wires123electrically connect the first electronic elements122with the first electrical surface121bof the first substrate121. For example, at least one of the first conductive wires123connects the first electronic elements122with the bottommost conductive layers1212forming the first electrical surface121b. In another, at least one of the first conductive wires123electrically connect two of the first electronic elements122.

The first package body124has the package surface120b. The package body124could be made of a material including, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers also can be included, such as powdered SiO2. The package body124could be applied using any of a number of molding techniques, such as compression molding, injection molding, or transfer molding.

The first adhesive layer125is disposed between the package module120and the carrier110. Furthermore, the first adhesive layer125is disposed between the package surface120bof the package module120and the die pad114of the carrier110for fixing the relative position between the carrier110and the package module120.

The second package body130encapsulates the package module120, a portion of the carrier110, the second conductive wires140, the second electronic element150and the third electronic element160. The second package body130could be made of a material the same as or similar to the first package body124.

At least one of the second conductive wires140connect the package module120with the second electrical surface121uof the first substrate121of the package module120. For example, at least one of the second conductive wires140connect the package module120with the topmost dielectric layer1212forming the second electrical surface121u. In addition, one of some of the second conductive wires140electrically connect the grounding ring113with the second electronic element150.

The second electronic element150is, for example, active chip, such as a SoC, etc. The second electronic element150is disposed on the second electrical surface121u.

The second adhesive layer155is disposed between the package module120and the second electronic element150. Furthermore, the second adhesive layer155is disposed between the second electrical surface121uof the package module120and the second electronic element150for fixing the relative position between the second electronic element150and the package module120.

The third electronic element160is, for example, passive element, such as resistor, inductor and/or capacitor; however, such exemplification is not meant to be for limiting. The third electronic element160is disposed on the second electrical surface121u.

As illustrated inFIGS.2and3, at least one portion of the second electronic element150could overlap the package module120. For example, inFIG.2, a portion of the second electronic element150is disposed over the package module120. InFIG.3, the entire of the second electronic element150is disposed over the package module120. The position of the second electronic element150could be determined according to design of the wire bonding.

Referring toFIG.4,FIG.4illustrates a diagram view of a semiconductor package200according to another embodiment of the invention.

The semiconductor package200includes the carrier110, the package module120, the first adhesive layer125, the second package body130, at least one second conductive wire140, at least one second electronic element150, the second adhesive layer155and at least one third electronic element160.

The semiconductor package200includes the features the same as or similar to that of the semiconductor package100expect that the second electronic element150and the package module120are disposed on the die pad114of the carrier110side by side.

Referring toFIG.5,FIG.5illustrates a diagram view of a semiconductor package300according to another embodiment of the invention.

The semiconductor package300includes a carrier210, the package module120, the first adhesive layer125, the second package body130, at least one second conductive wire140, at least one second electronic element150, the second adhesive layer155and at least one third electronic element160.

The semiconductor package300includes the features the same as or similar to that of the semiconductor package200expect that the carrier210has the structure different from that of the carrier110. In the present embodiment, the carrier210is a second substrate including the structure the same as or similar to that of the first substrate121of the package module120.

The carrier210has, for example, single-layered structure or multi-layered structure. In the present embodiment, the carrier210has multi-layered structure including at least one dielectric layer211, at least one conductive layer212and at least one conductive via213. In addition, the dielectric layer211could be made of a material of non-conductive material, for example, epoxy or resin. Two of the conductive layers212are separated from each other by one of the dielectric layers211, and electrically connected with each other by one of the conductive vias213.

In addition, the first adhesive layer125is disposed between the carrier210and package surface120bof the package module120for fixing the relative position between the carrier210and the second electronic element150. The second adhesive layer155is disposed between the carrier210and the second electronic element150for fixing the relative position between the carrier210and the second electronic element150.

The carrier210has a third electrical surface210u. The second package body130encapsulates the third electrical surface210uof the carrier210. The third electrical surface210uis entirely covered by, for example, the package module120and the second electronic element150and the second package body130.

Referring toFIG.6,FIG.6illustrates a diagram view of a semiconductor package400according to another embodiment of the invention.

The semiconductor package400includes the carrier210, the package module120, the first adhesive layer125, the second package body130, at least one second conductive wire140, at least one second electronic element150, the second adhesive layer155and at least one third electronic element160.

The semiconductor package400includes the features the same as or similar to that of the semiconductor package300expect that the second electronic element150and the package module120are stacked to each other.

Referring toFIGS.7A to7B,FIGS.7A to7Billustrate diagram views of some package modules120A to120B according to some embodiments of the invention.

The package module120of each of the semiconductor packages100to400could be replaced by one of the package modules120A and120B.

As illustrated inFIGS.7A and7B, the first substrate121of the package modules120A has a through hole120A1and further includes a plug120A2filling up the through hole120A1. The plug120A2protrudes respect to the second electrical surface121uof the first substrate121and covers a portion of the second electrical surface121u. In addition, in the present embodiment, the back surface122bof the first electronic elements122is, for example, active surface. At least one of the first electronic elements122electrically connects with the second electrical surface121uby one or some of the first conductive wires123encapsulated by the plug120A2.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.