Patent ID: 12243890

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1toFIG.6are schematic cross sectional views of various stages in a manufacturing process of a semiconductor device structure according to some exemplary embodiments of the present disclosure. Referring toFIG.1, in some embodiments, a substrate110is provided. The substrate110includes a surface110a. The substrate110is, for example, a semiconductor substrate. The substrate110may include, for example, silicon, strained silicon, silicon alloy, silicon carbide, silicon-germanium, silicon-germanium carbide, germanium, a germanium alloy, germanium-arsenic, indium-arsenic, group III-V semiconductors, organic plastic substrates, glass or a combination thereof. In some embodiments, the substrate110may be a wafer and may include doped regions, such as p-type regions, n-type regions or a combination thereof.

Referring toFIG.2, one or more devices112may be formed at the surface110aof the substrate110. The devices112may be, for example, light sensing devices. In some embodiments, the devices112are formed in the substrate110(not shown). InFIG.2, the devices112are shown to be formed on the surface110aof the substrate110. In other embodiments, the devices112are not on the surface110a, but are formed in the substrate110, and do not protrude out of the substrate. The devices112may include, for example, a pixel, a single-photon avalanche diode (SPAD), a photo diode (PD), a photo transistor, a time of flight (ToF) camera, a photo gate, a pinned photo diode, or a combination thereof. In some embodiments, additional semiconductor devices with different functions or integrated circuits may also be included on the substrate110or in the substrate110. The scope of the disclosure is not limited to the embodiments or drawings described therein. Furthermore, the structure may only require one light sensing device112or an array of multiple light sensing devices112. The number of light sensing devices112or configuration of multiple light sensing devices112may be adjusted according to user requirements.

Referring toFIG.3, in some embodiments, a wiring structure120is formed on the surface110aof the substrate110. In certain embodiments, the wiring structure120includes one or more contacts122connected to the devices112and metal interconnection patterns124,126,128. In some embodiments, the contact(s)122is formed within the dielectric layer121, and the metal interconnection patterns124,126,128are fabricated with one or more interlayer dielectric layers123. In some embodiments, the dielectric layer121may include a pre-metal dielectric layer, and the dielectric layer123may include one or more inter dielectric layers. The materials of the metal interconnection patterns124,126,128include, for example, aluminum, copper, copper alloys or any other suitable metal materials. The wiring structure120including the dielectric layers121,123, the contact(s)122and the metal interconnection patterns124,126,128may be formed in the back end of line processes.

Referring toFIG.4, a passivation layer130is formed on the wiring structure120. The passivation layer130having a top surface130ais deposited over the wiring structure120. In some embodiments, the material of the passivation layer130includes, for example, silicon carbide (SiC), SiCN, silicon nitride, silicon oxynitride, silicon oxide, a low-k dielectric material or combinations thereof, but is not limited by the above-mentioned materials. In some embodiments, the material of the passivation layer130is light transmissive, with an index of refraction greater than or equal to 2.0. The material of the passivation layer130may be selected according to the requirements or design of the products. In other embodiments, the passivation layer130is formed on a backside surface of the substrate110opposite to the surface110a, see a semiconductor device300ofFIG.14and a semiconductor device400ofFIG.15.

Referring toFIG.5andFIG.6, in certain embodiments, a photolithography process and an etching process are performed towards the passivation layer130to form a plurality of microstructures130b. In some embodiments, a photoresist pattern200formed on the surface130aof the passivation layer130. In some embodiments, the photoresist pattern200is formed by forming a photoresist layer through spin coating and then patterning by projecting light through a photo mask (not shown).

Referring toFIG.6, in some embodiments, using the photoresist pattern200as the mask, the etching process is performed to remove a portion of the passivation layer130from the passivation layer130so as to form the microstructures130b. In some examples, performing the etching process includes performing at least one dry etching process and/or a wet etching process. Herein, a semiconductor device structure100is formed. In some embodiments, the semiconductor device structure100includes one or more CMOS image sensor devices, which are able to sense incident light or signals. Of course, the semiconductor device structure100may include other suitable light sensor devices for sensing incident light at different wavelengths. Although in certain embodiments the etching process is performed to form the microstructures130bas described above, the microstructures130bmay be formed using a laser ablation technique or even mechanical ablation technology in some other embodiments. In other embodiments, the passivation layer130formed on a backside surface of the substrate110opposite to the surface110a(not shown) also performs the same steps inFIG.5andFIG.6to form the microstructures130b. When formed on the backside surface, the structure may be suitable for backside illumination. When formed on the surface110aof the substrate110, the structure may be suitable for front side illumination.

Furthermore, in some embodiments, the microstructures130bare formed to cover substantially the whole area of the passivation layer130. In some embodiments, the semiconductor device structure100may further include an array of micro lens (not shown) disposed over the microstructures130b. In other embodiments, the microstructures130bare formed only at certain regions or sections of the passivation layer130. In the case that the microstructures130bformed are only at one or more regions of the passivation layer130, the region(s) formed with the microstructures130bis a light sensing region with light sensing devices below the light sensing region. That is to say, the microstructures130bare located in the light sensing region above the devices112(including light sensing devices) and are adapted to enhance the light absorption. In some embodiments, when the microstructures130bare located in the light sensing regions, the micro lens (not shown) may be disposed above and adjacent to the microstructures130bor on the microstructures130b. In some embodiments, the layout of the wiring structure120or the patterns of the metal interconnection patterns124,126,128are arranged aside of the light sensing region(s) or away from the light sensing region(s) (from the top view), and are not directly above the devices112, so as not to obstruct light from reaching the light sensing regions.

FIG.7is an enlarged schematic cross sectional view of a passivation layer of a semiconductor device structure ofFIG.6.FIG.8is a tilted top view of the passivation layer ofFIG.7. Referring toFIG.7toFIG.8, in some embodiments, each microstructure130bis formed with a cross-section shape of, for example, a triangle. However, in other embodiments, a cross-section shape of each microstructure130bis, for example, a trapezoid or arc, such as semi-circle or semi-ellipse (not shown). It is not limited that each of the microstructures has to have exactly the same shape and there may be certain variations of shapes among the microstructures. Furthermore, in certain embodiments, the shape of the microstructure130bis a cone shape as shown inFIG.8. The shape of the microstructure130bmay be a right pyramid shape, a triangular pyramid shape or any other suitable shape.FIG.8is a partial schematic view of the passivation layer130. FromFIG.8, the microstructures130bare formed regularly with the same shape, dimension and pitch and are arranged in an array. In some other embodiments, the microstructures130bmay be formed with different shapes, dimensions, pitches or patterns. The arrangement of the microstructures130bdepends on user requirements or product designs. In addition, as seen inFIG.7toFIG.8, the formed microstructures130bdo not extend through the entire thickness of the passivation layer130. The ratio of the height of the microstructures130bto the thickness of the remained passivation layer130that is not formed into parts of the microstructures130bis adjustable. In other embodiments, the microstructures130bcan be formed extending through the entire thickness of the passivation layer130such that the height of the microstructures130bis substantially equivalent to the entire thickness or height of the passivation layer130. The shape, configuration or dimension of the microstructures130bmay be changed depending on, for example, the material of the passivation layer130or the wavelength(s) of incident light that is to be detected or sensed.

Further referring toFIG.7toFIG.8, in some embodiments, the microstructures130bare formed with the arrangement that any two most adjacent ones of the microstructures130bare abutting with each other and the peripheries of the bases130cof adjacent microstructures130bare in direct contact with each other. The microstructure130bhas a height h1, and a pitch w1between any two most adjacent ones of the microstructures130b. In some embodiments, the height h1is between 100λ and λ/100, and the pitch w1is between 100λ and λ/100, λ representing a wavelength of an incident light140. In some embodiments, the height h1is greater than λ/2.5, and the pitch w1is greater than λ/2. With the microstructures130b, a larger top surface area for receiving the incident light140is provided for multiple reflection, and an incident angle of the incident light140projected to the surface131of the microstructures130bis smaller than that of the incident light140projected to a flat surface of the passivation layer130, so that most of the incident light140can pass through the microstructures130to be sensed by the devices112. The reflection loss of the incident light140is reduced because the incident light140is multiply reflected and refracted by the microstructures130band the reflection loss ratio keeps decreasing after multiple reflections and refractions within the microstructures130b. Hence, the absorption ratio of the incident light140is significantly raised. Furthermore, the light beam of the incident light140is narrowed by the designed multiple reflections from the microstructures130b.

FIG.9is an enlarged partial schematic cross sectional view of the passivation layer ofFIG.7. Specifically, as seen inFIG.9, in some embodiments, the incident light140is incident on the microstructure130bso that part of the incident light140is refracted into and passes through the microstructure130band part of the incident light140is reflected off the microstructure130bto become a first reflected light142. The first reflected light142is then incident on an adjacent microstructure130bsuch that a portion of the first reflected light142is refracted into and passes through the adjacent microstructure130band a portion of the first reflected light142is reflected off the adjacent microstructure130bto become a second reflected light144. The second reflected light144is then incident on the same microstructure130bthe incident light140was incident to, such that a portion of the second reflected light144is refracted into and passes through the microstructure130band a portion of the second reflected light144is reflected off the microstructure130bto become a third reflected light146. The third reflected light146is reflected in a direction away from the microstructures130bsuch that the light is lost. In certain embodiments, the incident light140refracted multiple times into the microstructures130bis absorbed by the underlying light sensing device. In some embodiments, the incident light140is also reflected multiple times to become the first, second and third reflected light142,144,146with decreasing reflection ratios. In exemplary embodiments, when the microstructures130bare made of silicon nitride (refraction index of 2.4), the incident light140from air (refraction index of 1.0) is also reflected multiple times to become the first, second and third reflected light142,144,146with reflection ratios of 0.169 (16.9%), 0.029 (2.9%) and 0.005 (5%). As the incident light140is reflected multiple times, the amount of light lost is reduced to only 5% of the third reflected light146, which is significantly lower than that of the first reflected light142(if the incident light140was only refracted and reflected once and lost). That is to say, only 5% of the incident light140was lost, and 95% of the incident light140passes through the microstructures130bof the passivation layer130to be sensed or absorbed by the devices112. The reflection paths of the incident light140, the first reflected light142, the second reflected light144, and the third reflected light146described in the drawings are exemplary, as the reflection/refraction paths and the transmission/reflection rates of the light may vary depending on the incident angle and the indexes of refraction of the materials at the interface (reflection law and Snell's law). The material of the microstructures130band the incident angle of the incident light140affect the light reflection/refraction paths. The aforementioned light path is merely exemplary to show that the microstructures130ballow the absorption ratio of the incident light140to be significantly raised. In addition, through the microstructures130bthe beam width of the incident light140is also narrowed.

FIG.10is an enlarged schematic cross sectional view of a passivation layer of a semiconductor device structure according to some exemplary embodiments of the present disclosure. Referring toFIG.10, the passivation layer230with the microstructures230bis adapted to be formed on the semiconductor device structure100inFIG.6. The difference between the passivation layer230and the passivation layer130inFIG.6is that in the passivation layer230, in the operation of forming the microstructures230b, the bases230cof any two most adjacent ones of the microstructures230bare separated from each other. That is to say, the bases230cof the microstructures230bare not adjoined. As shown inFIG.10, each microstructure230bhas a height h2, and a pitch w2is formed between any two adjacent ones of the microstructures230b. In some embodiments, the height h2is between 100λ and λ/100, and the pitch w2is between 100λ and λ/100. In some embodiments, the height h2is greater than λ/2.5, and the pitch w2is greater than212. The microstructures230bare not adjoined based on user requirements. Similar to the microstructures130binFIG.7, the microstructures230binFIG.10also allow an incident light (not shown) to be multiply refracted, and then pass through to be absorbed by the devices112. Hence, the absorption ratio of the incident light is significantly raised. In addition, through the microstructures230bthe beam width of the incident light is also narrowed. An incident light is not shown inFIG.10as a similar light path can be referred to inFIG.7.

FIG.11is an enlarged partial schematic cross sectional view of a plurality of passivation layers of a semiconductor device structure according to some exemplary embodiments of the present disclosure. Referring toFIG.11,FIG.11shows a plurality of passivation layers130stacked on top of each other. The passivation layers130are the same as the passivation layer130shown inFIG.6andFIG.7. That is to say, in the embodiment ofFIG.11, additional passivation layers130are formed on the single passivation layer130shown inFIG.6, and the embodiment is applicable to the semiconductor device structure shown inFIG.6.FIG.11only shows two of the microstructures130bon each of the passivation layers130as a partial schematic view. As seen inFIG.11, in some embodiments, a total of three passivation layers130with the microstructures130bare shown. However, the disclosure is not limited thereto, and the number of passivation layers130may be adjusted according to user requirements. The additional passivation layers130are formed layer by layer similar to the description of the formation of the passivation layer130inFIG.6. That is to say, the photolithography process and the etching process are performed during each formation of the microstructures130bof the passivation layers130. The microstructures130bof one passivation layer130are formed first, and then another passivation layer130is deposited and patterned to form the microstructures130bon the additional passivation layer130. As seen inFIG.11, in some embodiments, the microstructures130bof each passivation layer130are aligned with each other in a stacking direction of the passivation layer130. To be specific, as seen inFIG.11, the microstructures130bof each passivation layer130are aligned in a vertical direction. With this configuration, the microstructures130bof the stacked passivation layers130allow an incident light150to be multiply refracted, and then pass through to be absorbed by the devices112. Hence, the absorption ratio of the incident light150is significantly raised. Specifically, similar to the light path of the incident light140inFIG.7, the incident light150also reflected and refracted multiple times as shown in the light path150aof the incident light150. Furthermore, as the incident light150passes through the microstructures130bof the stacked passivation layers130, the light beam of the incident light150is further narrowed such that the stacked passivation layers130are a stacked optical collimator.

FIG.12is an enlarged partial schematic cross sectional view of a plurality of passivation layers of a semiconductor device structure according to some exemplary embodiments of the present disclosure. Referring toFIG.12, the embodiment ofFIG.12is similar to the embodiment ofFIG.11, and the same description is not repeated herein. The difference between the embodiment ofFIG.12and the embodiment ofFIG.11is that in the embodiment ofFIG.12, the microstructures330bof each passivation layer330are alternately aligned with each other in a stacking direction of the passivation layer330. To be specific, as seen inFIG.12, the microstructures330bof each passivation layer330are alternately aligned in a vertical direction such that a microstructure330bof a passivation layer330is between two adjacent microstructures330bin the above passivation layer330. Similar to the embodiment ofFIG.11, the stacked passivation layers330ofFIG.12narrow an incident light beam (not shown) to be a stacked optical collimator. In the embodiments ofFIG.11andFIG.12, the microstructures230bofFIG.10may also be applied. Furthermore, the microstructures inFIG.11andFIG.12may be any suitable shape or arrangement on each passivation layer. The disclosure is not limited thereto.

FIG.13is a schematic cross section view of a semiconductor device structure according to some exemplary embodiments of the present disclosure. Referring toFIG.13, a semiconductor device structure200is similar to the semiconductor device structure100in FIG.6. Similar elements are referenced with the same reference numerals. The same description is not repeated herein. The difference is that the semiconductor device structure200further includes an antireflective layer160. The antireflective layer160is coated on the microstructures130bafter the microstructures130bare formed. The antireflective layer160further reduces that amount of light that is reflected. That is to say, the antireflective layer160improves the absorption ratio of the incident light, and reduces the amount of incident light lost to reflection. In the embodiments, ofFIG.11andFIG.12, the antireflective layer160may also be coated on the topmost passivation layer130,230of the stacked passivation layers130,230. Of course, the antireflective layer160may also be omitted is desired by the user. A material of the antireflective layer160is, for example, magnesium fluoride fluoropolymers, or any other suitable material. In addition, in the embodiments ofFIGS.10,11,12, and13, the microstructures formed can extend through the entire thickness of the passivation layer130such that the height of the microstructures130bis the entire thickness or height of the passivation layer130. The parameters of the microstructures formed may depend on the material of the passivation layer or the configuration of the semiconductor device structure.

According to some embodiments, a semiconductor device structure for sensing an incident light includes a substrate, a wiring structure, and at least one passivation layer. The substrate has a light sensing device. The at least one passivation layer is disposed above the wiring structure. The at least one passivation layer includes a plurality of microstructures disposed above the light sensing device, and each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed below the at least one passivation layer.

According to some embodiments, a method for manufacturing a semiconductor device structure includes the following steps. A substrate having a device is provided. A wiring structure is formed on the substrate. A passivation layer is formed on the wiring structure. A plurality of microstructures are formed from the passivation layer, and each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc.

According to some embodiments, a method for manufacturing a semiconductor device structure includes the following steps. A substrate having a device is provided. A wiring structure is formed on the substrate. A plurality of passivation layers are formed on the wiring structure. A plurality of microstrucutres are formed from at least two passivation layers of the passivation layers. The microstructures formed from the at least two passivation layers are stacked on top of each other. Each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc.

According to some embodiments, a semiconductor device structure for sensing an incident light includes a substrate, a passivation layer and a wiring structure. The substrate has a device embedded therein. The passivation layer is disposed on the substrate, wherein the passivation layer has a first side and a second side opposite to the first side, the first side of the passivation layer includes a plurality of microstructures disposed on the substrate, and the second side of the passivation layer is a continuous flat plane, wherein each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed on the substrate, wherein the writing structure includes at least one contact and metal interconnection patterns respectively formed in different dielectric layers, and the at least one contact and the metal interconnection patterns are electrically connected, wherein the substrate is located between the passivation layer and the wiring structure.

According to some embodiments, a semiconductor device structure for sensing an incident light includes a substrate, a passivation layer and a wiring structure. The substrate has at least one light sensing region with a light sensing device formed therein. The passivation layer is disposed on the substrate, wherein a first side of the passivation layer includes a plurality of microstructures covering the substrate and overlapped with the at least one light sensing region, and a second side of the passivation layer is a continuous flat plane, wherein the first side is opposite to the second side, and each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed on the substrate, wherein the writing structure includes at least one contact and metal interconnection patterns respectively formed in different dielectric layers, and the at least one contact and the metal interconnection patterns are electrically connected, wherein the substrate is located between the passivation layer and the wiring structure.

According to some embodiments, a method for manufacturing a semiconductor device structure includes the following steps, providing a substrate having a device embedded therein; forming a wiring structure comprising at least one contact and metal interconnection patterns respectively formed in different dielectric layers on the substrate, wherein the at least one contact and the metal interconnection patterns are electrically connected; and forming a passivation layer having microstructures on the substrate, a first side of the passivation layer comprising the microstructures, a second side of the passivation layer being a continuous flat plane and opposite to the first side, wherein each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc, and the substrate is located between the passivation layer and the wiring structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.