Patent ID: 12218040

EMBODIMENTS OF THE DISCLOSURE

Described herein are nested interposers having a through-silicon via bridge die and methods of forming such electronic packages, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As noted above, current packaging solutions are beginning to use multi-die architectures. However, the inclusion of multiple dies in a single package is not without issue. In addition to the larger footprint of existing multi-die architectures, such systems also suffer from poor yield and reliability. Particularly, the interconnections between dies are difficult to control due to warpage and other alignment issues when using traditional packaging substrates. Accordingly, embodiments disclosed herein include electronic packages that utilize nested interposers with through-silicon via (TSV) Si bridge dies for fine bump pitch die-to-die tiling.

To provide context, nested interposers can include an interposer with one or more cavities. Nested components may be positioned in the cavities. One or more dies may be connected to the interposer and the nested components with interconnects. In an embodiment, the interconnects include intermediate pads that are positioned between the pads of the nested component and the die and between the pads of the interposer and the die. In some embodiments, the intermediate pads are connected to the interposer pads and the nested component pads by a via. In other embodiments, the intermediate pads are directly connected to the interposer pads and the nested component pads. The intermediate pads (and in some embodiments the vias) provide misalignment correction for misalignment between the interposer and the nested component. Accordingly, embodiments allow for high yields and reliability, even when fine pitched interconnects are used (e.g., when the nested component is a bridge between two dies).

Referring now toFIG.1A, a cross-sectional illustration of an electronic package100is shown, in accordance with an embodiment. In an embodiment, the electronic package100may include an interposer130and a nested component140. The nested component140is positioned within a cavity135that passes through the interposer130. The nested component140is referred to as being “nested” because the component140is placed into the cavity135. That is, the nested component140is surrounded by portions of the interposer130. In the illustrated embodiment, a single cavity135is shown in the interposer130. However, it is to be appreciated that any number of cavities135may be used, depending on the device. Examples of multiple cavities135are provided below in greater detail. In the illustrated embodiment, a single nested component140in the cavity135is shown. However, it is to be appreciated that any number of nested components140may be positioned in a single cavity135. Examples of multiple nested components140in a single cavity135are provided below in greater detail.

In an embodiment, the interposer130may be any suitable substrate material. For example, the interposer130may be or include a substrate including glass, ceramic, semiconductor materials (e.g., high or low resistivity silicon, group III-V semiconductors, or the like), or organic substrates (high density interconnect (HDI) substrates, embedded trace substrates (ETS), high density package (HDP) substrates, molded substrates, or the like). In some embodiments, the interposer130is a passive device. That is, the interposer130may include only passive components (e.g., traces, vias, etc.). For example, the interposer130may include vias134that provide connections between pads133below the interposer130and pads136above the interposer130. In other embodiments, the interposer130may be an active interposer. That is, the interposer130may include active devices (e.g., transistors etc.).

In an embodiment, the nested component140may be an active or passive component. For example, an active nested component140may include logic devices, analog/RF devices, I/O circuits, memory devices, voltage regulators, sensors, or the like. Passive nested components140may include high density multi-die interconnect bridge dies, capacitors, inductors, resistors, thermo-electric coolers, high speed connectors, or the like. In the illustrated embodiment, the nested component140includes an active surface141. While referred to as an “active” surface141, it is to be appreciated that the active surface141may include entirely passive features. In an embodiment, the nested component140may include through component vias (TCVs)144. The TCVs144may electrically couple the active surface141to pads143on the backside of the nested component140.

In an embodiment, the interposer130and the nested component140may be embedded by a mold layer132. The mold layer132may fill the remaining portions of the cavity135. That is, portions of the mold layer132may be positioned between sidewalls of the nested component140and sidewalls of the interposer130. In an embodiment, the mold layer132may cover top surfaces of the nested component140and top surfaces of the interposer130.

In an embodiment, pads133of the interposer130and pads143of the nested component140may be contacted by bumps137positioned in openings through a solder resist195around the pads133and the pads143. In an embodiment, the bumps137may be referred to as “package side bumps” (PSBs). The PSBs may interface with a package substrate (not shown).

In an embodiment, the electronic package100may further include one or more dies120embedded in a mold layer122. In an embodiment, the active surfaces121of the dies120may be electrically coupled to the interposer130and the nested component140. For example, interconnects181provide electrical connections between the die120and the interposer130, and interconnects182provide electrical connections between the die120and the nested component140. In an embodiment, the interconnects181may have a different pitch than the interconnects182. For example, the interconnects182may have a smaller pitch than the interconnects181. In the illustrated embodiment, the nested component140is a bridge that provides an electrical connection between the two dies120.

Referring now toFIG.1B, a zoomed in portion180of the electronic package100is shown, in accordance with an embodiment. Portion180illustrates more clearly the architecture of the interconnects181and182. As shown, the interconnects181and182are substantially similar to each other, with the exception that the widths of the interconnects182are smaller than the widths of the interconnects181. In an embodiment, the interconnects include an intermediate pad184. The intermediate pads184may be positioned over a top surface of the mold layer132. A bump183(e.g., a solder bump) may be positioned over the intermediate pads184. The bumps183may be electrically coupled to die pads123of the die120.

In an embodiment, the intermediate pads184may be electrically coupled to interposer pads136or component pads146by vias191. The vias191may extend through a portion of the mold layer132. In the illustrated embodiment, the vias191are illustrated as having substantially vertical sidewall profiles. Such an embodiment may be provided when the via openings are lithographically defined. However, it is to be appreciated that embodiments may also include vias191with tapered sidewall profiles. Such embodiments are typically formed when the via openings are formed with a laser drilling process.

The use of intermediate pads184and vias191provides interconnects181and182that have an improved alignment to the die120. Particularly, since the nested component140is placed into the cavity135of the interposer130, there may be some degree of misalignment between the interposer pads136and the component pads146. However, since the vias191may all be formed with a single lithography operation, they will be aligned with each other. Similarly, the intermediate pads184may be fabricated with a single lithography process that aligns the intermediate pads184to each other. InFIG.1B, the interposer130, the nested component140, and the die120are shown as being perfectly aligned, and the benefit of alignment correction capabilities of the interconnects181and182are not clearly evident.

Referring now toFIG.1C, a cross-sectional illustration of the portion180that more clearly exhibits the benefits of the alignment correction features is shown, in accordance with an embodiment. As shown inFIG.1C, the nested component140is offset from the center of the cavity135. Accordingly, the component pads146are misaligned with respect to the interposer pads136. However, the vias191are all aligned with respect to each other, and the intermediate pads184are all aligned with respect to each other. For example, the centerlines of the vias191over the component pads146are not aligned with the centerlines of the component pads146. So long as the vias191land on some surface of the component pads146(without also landing on a neighboring component pad146) the misalignment can be corrected. InFIG.1C, the centerline of the via191over the interposer pad136is shown as being substantially aligned with the centerline of the interposer pad136. However, it is to be appreciated that the via191may be shifted with respect to the interposer pad136in some embodiments.

InFIG.1C, misalignment in the X direction is shown. That is, the vias191may provide misalignment correction in the X-Y plane. However, it is to be appreciated that the vias191may also provide Z-height corrections as well. For example, if the thickness of the interposer130and the nested component140are not uniform, then vias of different heights can be used to provide a uniform Z-height for subsequent connections.

Referring now toFIG.2A, a cross-sectional illustration of an electronic package200is shown, in accordance with an additional embodiment. In an embodiment, the electronic package200may be substantially similar to the electronic package100described above, with the exception that the interconnects281and282are modified. For example, the electronic package200may include an interposer230with a cavity235and a nested component240in the cavity235. The interposer230and the nested component240may be embedded in a mold layer232. Active surfaces221of the dies220may be connected to the interposer230and the nested component240by interconnects281and282. The dies220may be embedded in a mold layer222. In an embodiment, the interposer230may include vias234that provide connection to pads233and bumps237, and the nested component240may include vias244that connect an active surface241to pads243and bumps237. Solder resist295may be positioned around the pads233and243.

Referring now toFIG.2B, a zoomed in cross-sectional illustration of region280inFIG.2Athat more clearly illustrates the interconnects281and282is shown, in accordance with an embodiment. As shown, the interconnects281and282are substantially similar to each other, with the exception that the widths of the interconnects282are smaller than the widths of the interconnects281. In an embodiment, the interconnects include an intermediate pad284. The intermediate pads284may be positioned over a top surface of the mold layer232. A bump283(e.g., a solder bump) may be positioned over the intermediate pads284. The bumps283may be electrically coupled to die pads223of the die220.

In an embodiment, the intermediate pads284may be directly connected to interposer pads236or component pads246. Instead of using vias (as shown inFIGS.1A-1C), the interposer pads236and the component pads246have a thickness T that extends through the mold layer232. Accordingly, the interposer pads236and the component pads246provide the same functionality provided by the vias191inFIGS.1A-1C.

The use of intermediate pads284provides interconnects281and282that have an improved alignment to the die220. Particularly, since the nested component240is placed into the cavity235of the interposer230, there may be some degree of misalignment between the interposer pads236and the component pads246. However, since the intermediate pads284may all be formed with a single lithography operation, they will be aligned with each other. InFIG.2B, the interposer230, the nested component240, and the die220are shown as being perfectly aligned, and the benefit of alignment correction capabilities of the interconnects281and282are not clearly evident.

Referring now toFIG.2C, a cross-sectional illustration of the region280that more clearly exhibits the benefits of the alignment correction features is shown, in accordance with an embodiment. As shown inFIG.2C, the nested component240is offset from the center of the cavity235. Accordingly, the component pads246are misaligned with respect to the interposer pads236. However, the intermediate pads284are all aligned with respect to each other. For example, the centerlines of the intermediate pads284over the component pads246are not aligned with the centerlines of the component pads246. So long as the intermediate pads284land on some surface of the component pads246(without also landing on a neighboring component pad246) the misalignment can be corrected. InFIG.2C, the centerline of the intermediate pad284over the interposer pad236is shown as being substantially aligned with the centerline of the interposer pad236. However, it is to be appreciated that the intermediate pad284may be shifted with respect to the interposer pad236in some embodiments.

InFIG.2C, misalignment in the X direction is shown. That is, the intermediate pads284may provide misalignment correction in the X-Y plane. However, it is to be appreciated that thick interposer pads236and component pads246may also provide Z-height corrections as well. The use of interposer pads236and component pads246to provide Z-height corrections will be described in greater detail below.

In another aspect, the demand for miniaturization of form factor and increased levels of integration for high performance are driving sophisticated packaging approaches in the semiconductor industry. Die partitioning enables miniaturization of small form factor and high performance without yield issues seen with other methods but needs fine die to die interconnections. Embedded Multi-die Interconnect Bridge (EMIB) is a breakthrough that enables a lower cost and simpler 2.5D packaging approach for very high-density interconnects between heterogeneous dies on a single package. Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high-density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate.

For future generations of die partitioning, several bridges that can connect the dies at much finer bump pitches (e.g., 25 microns or lower) than that are currently delivered by EMIB are needed. However, the EMIB approach can suffer from a high cumulative Bump Thickness Variation (BTV) and as the number of bridges to be embedded increase, cost of embedding and yields can suffer. Alternate architectures such as patch approaches have been proposed. One patch approach can involve an EMIB-T (EMIB with TSV connections) or an active functional die instead of a standard bridge die with no TSV connections. Fine die-to-die interconnections for die tiling can be accomplished through this embedded die. A patch can be simplified to have no multiple redistribution layer (RDL) routing or fanout layers due to assembly concerns of attaching the patch to the bottom substrate (mid-level interconnect, MLI). While mass reflow is not feasible, significant flattening issues that arise due to the stack warpage can result in a very narrow Thermal Compression Bonding (TCB) attach window. Fabrication of a nested interposer package with glass can result in significant decrease in the warpage but the architecture may not be suitable for EMIB-T or an active die which are usually thinner, and the warpage advantage from nesting diminishes with reduced interposer thickness. To realize the full potential of the nested interposer architecture, in accordance with one or more embodiments of the present disclosure, an EMIB-T or an active die is nested while retaining the warpage benefits from having a thick interposer for MLI attach to the bottom substrate.

Embodiments described herein can be implemented to enable fabrication of a nested interposer architecture that can accommodate a thin EMIB-T or active die for fine bump pitch D2D interconnections. The nesting in this case is performed using a cavity of desired thickness in which the EMIB-T or active die are placed. The TSV connections of the die embedded in the cavity to the bottom substrate can be accomplished through metallized vias created under the cavity. Other top die connections to bottom substrate can be handled through vias in the non-cavity regions of the interposer.

To provide further context, several approaches are being investigated to enable die tiling but none of them offer or provide a robust warpage mitigation solution for reliable MLI attach which is a need for fabricating the final package. A nested interposer package described above can provide significant warpage reduction and render mass reflow feasible at desired no fan-out pitch. Mechanical data collected with a configuration simulating nested glass interposer reveals that the glass thickness needed may be about 350 μm for low warpage. However, a through cavity configuration may not be amenable for embedding EMIB-T or active die. Additionally, equipment and process improvements may only result in limited improvements in patch attach window while changes in material formulations for reducing patch warpage may have undesirable effects or even not possible in some occasions. While warpage improves significantly for a nested interposer, making mass reflow attach process feasible, thickness of the glass and a through cavity configuration may not be suitable for embedding EMIB-T or active die.

In accordance with one or more embodiments of the present disclosure, a nested interposer architecture has a cavity with desired thickness in which the EMIB-T or active die are placed. The TSV connections of the die embedded in the cavity to the bottom substrate are accomplished through metallized vias created under the cavity. Other top die connections to bottom substrate are handled through vias in the non-cavity regions of the interposer. A patch with this configuration may be implemented to not only provide desired low warpage for robust MLI attach but also accommodate an active or EMIB-T die.

To provide further context, a modular die approach or die partitioning is becoming an increasing need in the packaging industry as it enables heterogeneous die integration, miniaturization of form factor and high performance with improved yield. Multiple approaches have been proposed to interconnect the modular die; however, each of the approaches come with their own drawbacks. Embodiments described herein may be implemented to offer a low cost, mature and high yield approach to overcome the issues described above and can be adopted by a variety of applications needing high density die-die interconnections.

A process flow can be implemented for creating packages in a high volume manufacturing (HVM) glass panels processing line, such as for creating a nested interposer with EMIB-T or active die for fine die to die (D2D) tiling. As an exemplary process flow,FIGS.3A-3Killustrate cross-sectional views representing various operations in a method of fabricating a nested interposer having a through-silicon via bridge die, in accordance with an embodiment of the present disclosure.

Referring toFIG.3A, a glass substrate or panel300is selected or fabricated to have a desired final interposer thickness. It is to be appreciated that the glass substrate or panel300may be panel level, sub-panel level, wafer-level, etc. The glass substrate or panel300is drilled to provide patterned glass substrate300A having openings302therein, as is depicted inFIG.3B.

Referring toFIG.3C, the openings302ofFIG.3Bare plated to form vias334, which may be referred to as through interposer vias or through glass vias. A cavity304and openings306are then drilled into the patterned glass substrate300A to form twice patterned glass substrate300B. A component340is then placed into the cavity304, as is depicted inFIG.3D. In one embodiment, the component340is an EMIB-T (through silicon via bridge die) or an active die. In one embodiment, the component340through component vias344coupled to backside die pads343A and bumps343B covered in a backside dielectric341, e.g., a die bonding film (DBF). The front side of the component can include front side die pads308and front side pillars309.

Referring toFIG.3E, a dielectric layer310is disposed over the exposed surfaces. In an embodiment, the dielectric layer310embeds the glass substrate300B and the nested component340. For example, the dielectric layer310may fill the cavity304so that portions of the dielectric layer310fill space between sidewalls of the nested component340and sidewalls of the glass substrate300B. While referred to as a “dielectric layer,” it is to be appreciated that dielectric layer310may be any suitable material or formed with any suitable material deposition process for packaging applications. For example, the dielectric layer310may be formed with a molding process, a lamination process, a deposition process, or the like. The backside dielectric341of the component340is then etched through openings306to form openings311exposing a portion of the bumps343B, as is depicted inFIG.3F. In one embodiment, the dielectric layer310protects the front side bumps309during the etching to form openings311.

Referring toFIG.3G, the dielectric layer310is then thinned to form thinned dielectric layer310A revealing the tops of the front side bumps309of the component340. Openings312are then formed in the thinned dielectric layer310A to expose vias334, as depicted inFIG.3H.

Referring toFIG.3I, plating and/or semi-additive processing is then performed to form, on the front side, interposer pads336, component pads346, and traces347. Semi-additive processing can also be performed to form, on the backside, core vias314beneath the component340, backside interposer pads333A and333B. The backside interposer pads333B are coupled to the core vias314. Two-sided solder resist lamination is then performed to form front side solder resist layer316A and backside solder resist layer316B, as is depicted inFIG.3J.

Referring again toFIG.3J, an interposer389includes the front side solder resist layer316A covering the interposer pads336and the component pads346. Vias391A and391B are formed in the front side solder resist layer316A and are coupled to the interposer pads336and component pads346, respectively. Intermediate pads384are then formed on the front side solder resist layer316A and are coupled to the vias391A and391B. Bumps383are formed on the intermediate pads384. Die pads323are formed on the intermediate pads384. Interposer389also includes the backside solder resist layer316B covering the backside pads333A and333B. Vias318A and318B are formed in the backside solder resist layer316B and are coupled to the backside pads333A and333B, respectively. Intermediate pads319A are then formed on the backside solder resist layer316B and are coupled to the vias318A and318B. Bumps319B are formed on the intermediate pads319A. Package substrate pads319C are formed on the intermediate pads319A.

Referring toFIG.3K, a multi-chip structure399is formed by coupling dies393A and393B to the interposer389ofFIG.3J. The dies393A and393B can include bumps395A and395B for coupling to die pads323of the interposer389. The bumps395A are over and may be coupled to the vias interposer substrate, while the bumps395B are over and may be coupled to the component340. The multi-chip structure399can also include an underfill394and/or an over die mold397, as is depicted.

In accordance with an embodiment of the present disclosure, with reference again toFIGS.3A-3K, for the sake of simplicity, a single interposer formation is shown. However, multiple interposers may be formed on a panel. A process flow can begin with a panel level glass of desired thickness and CTE (e.g., low CTE of about 3.4 or less). First, core vias (e.g., vias that connect a top die to a bottom substrate directly) are fabricated using a crack-free laser-based drilling process. Drilled hole pitch and diameter can be chosen as per the desired application. A seed layer is formed on the surface and side walls of the drilled holes using sputtering or electroless plating. Through Glass Vias (TGVs) are subsequently filled with copper using an electroplating approach. Extra copper on the glass surface is then removed by polishing to leave the vias flush with the glass surface. A cavity of desired thickness that will ultimately house an EMIB-T or an active die is then drilled, followed by vias that will connect the embedded die to the bottom substrate. The EMIB-T or active die is then placed in the cavity and is encapsulated on the top with a dielectric. The dielectric can be a traditional build-up dielectric material such as ABF. A plasma etch process can then be used to remove the portions of a die-bonding film and expose TSV pads on the back side of the die. Front side processing then continues with polishing/grinding to reveal the embedded die pillars. The core vias are then drilled and a semi-additive process (SAP) is used to fill and form pads and traces on the front side. The resulting layer can serve as a reset or routing layer for HBM/FIVR integration. Subsequently, backside vias that connect the embedded die TSV pads are metallized followed by pad formation. A solder resist layer is then laminated on the front and backside. First level interconnect (FLI) bumps are then formed by standard process, and core vias are opened with litho and vias for fine die to die connection using a UV laser followed by a lithography-based plating process, such as a tin (Sn) plating process. Alternately, an Litho Via process can be used to create the FLI bumps. MLI formation is also performed. A solder resist opening is fabricated by exposure and develop to create via openings. Copper fill plating followed by Litho-based Sn bump formation can then be performed. A micro-ball bumping process can also be performed to create MLI bumps. In the case of multiple interposers, the interposers can then be singulated into units and sent to assembly for top die attach which is usually performed at unit level. In one embodiment, the glass in the interposer provides excellent co-planarity and tight alignment accuracy to ensure fine die-to-die (D2D) connections. Top die assembly can be performed using Thermal Compression Bonding (TCB) to attach the top die to the nested interposer. Underfill formation, over-mold formation and subsequent grind can then performed to expose a die back side and subsequent die backside metallization.

It is to be appreciated that glass-based nesting is described here, however, any material (e.g., Silicon, Ceramic, etc., that can provide stiffness) can be implemented. The presence of a cavity that houses an active die or EMIB with TSV connections and metallized vias in the interposer that connect these TSV connections to the bottom substrate will be uniquely visible in a final product. Such connections can be used to power an embedded die or for any other desired functionalities. Embodiments can be implemented to enable finer D2D tiling and a robust MLI attach of tiled die in various interconnect architectures. This can be enabled using a nested interposer architecture that can accommodate a thin EMIB-T or an active die for fine bump pitch D2D interconnections. Embodiments can be implemented by nesting the EMIB-T or active die in a cavity of desired thickness. The TSV connections of the die embedded in the cavity to the bottom substrate can be enabled through metallized vias fabricated beneath/under the cavity. Such connections can be used to power the embedded die or for any other desired functionalities. Other top die connections to bottom substrate can be handled through vias in the non-cavity regions of the interposer. In one embodiment, the nested interposer provides a low warpage and the MLI attach to the bottom substrate can be accomplished using a relatively inexpensive mass reflow process. It is to be appreciated that such heterogeneous die integration or die tiling/stitching can be implemented to extend Moore's Law.

In another aspect, referring now toFIG.4A, a plan view illustration of an electronic package400is shown, in accordance with an exemplary embodiment. In an embodiment, the electronic package400includes an interposer430with a plurality of cavities435A-E. In an embodiment, a plurality of nested components440are positioned in the cavities435. It is to be appreciated that for ease of illustration, the cavities435are depicted as extending entirely through the interposer430; however, in at least some embodiments, the cavities435extend only partially through and not entirely through the interposer430. In some embodiments, at least one of the cavities435includes a plurality of nested components440. For example, two nested components440are positioned in cavity435B. In an embodiment, the cavities435may be entirely within a footprint of a die420(indicated by dashed lines), within the footprint of more than one die420, and/or partially within the footprint of a single die420. For example, cavities435Aand435Bare entirely within a footprint of die420A, cavity435Cis within the footprint of die420Aand420B, cavity435Eis within the footprint of die420Aand420C, and cavity435Dis partially within the footprint of die420B.

Referring now toFIG.4B, a cross-sectional schematic illustration of the electronic package400inFIG.4Aalong line B-B′ is shown, in accordance with an embodiment. In the illustrated embodiment, the interposer430is shown with nested components440within cavities435A,435C, and435D. The interposer430and the nested components440may be electrically coupled to the dies420Aand420Bby interconnects that include a layer of intermediate pads484. The intermediate pads484are shown schematically between the dies420A,420Band the interposer430and the nested components440for simplicity. However, it is to be appreciated that the intermediate pads484may be part of an interconnect substantially to the interconnects181and182described above with respect toFIGS.1A-1Cor interconnects281and282described above with respect toFIGS.2A-2C. In an embodiment, the bottom surfaces of the interposer430and the nested components440may be electrically coupled to package side bumps437.

Referring now toFIG.4C, a cross-sectional schematic illustration of the electronic package400inFIG.4Aalong line C-C′ is shown, in accordance with an embodiment. In the illustrated embodiment, the interposer430is shown with nested components440within cavities435Band435E. The interposer430and the nested components440may be electrically coupled to the dies420Aand420Bby interconnects that include a layer of intermediate pads484. The intermediate pads484are shown schematically between the dies420A,420Band the interposer430and the nested components440for simplicity. However, it is to be appreciated that the intermediate pads484may be part of an interconnect substantially to the interconnects181and182described above with respect toFIGS.1A-1Cor interconnects281and282described above with respect toFIGS.2A-2C. In an embodiment, the bottom surfaces of the interposer430and the nested components440may be electrically coupled to package side bumps437.

In another aspect, referring now toFIG.5, a plan view illustration of an electronic package500is shown, in accordance with an exemplary embodiment. In an embodiment, the electronic package500may include a plurality of interposers530A-D. Each interposer530may be any shape. For example, the interposers530are illustrated as being rectilinear. The interposers530may be arranged so that sidewalls of the interposers530define a cavity535. In an embodiment, one or more nested components540may be positioned in the cavity535. In an embodiment, one or more dies520(indicated with dashed lines) may be provided above the interposers530and the nested components540. Each of the dies520may extend over one or more of interposers530.

In an embodiment, each of the interposers530may be substantially similar to each other. For example, each of the interposers530may be passive interposers530or active interposers530. In other embodiments, the interposers530may not all be the same. For example, one or more of the interposers530may be an active interposer530and one or more of the interposers530may be a passive interposer.

In an embodiment, a nested interposer is attached to a bottom substrate (MLI Attach). The nested interposer with EMIB-T/active die with the assembled top die complex is then attached to the bottom substrate. The nested interposer can provide a low warpage and the attachment can be accomplished using a cheap mass reflow process. The resulting assembly can be attached to a board. As an example,FIG.6illustrates a cross-sectional view representing formation of an electronic system including a nested interposer having a through-silicon via bridge die, in accordance with an embodiment of the present disclosure.

Referring toFIG.6, an electronic assembly600is fabricated by coupling an assembly399(such as described above in association withFIG.3K) to a package substrate602, e.g., with solder balls604at bumps or pads615of the package substrate602. The package substrate602is coupled to a board606(such as a printed circuit board (PCB)), e.g., with solder balls608at bumps or pads617of package substrate602. In one embodiment, package substrate602includes a die side614, a board side616, and a core or direct routing layer612. In some embodiments, the assembly399is coupled directly to the board606. That is, the package substrate602may be optionally omitted.

FIG.7illustrates a computing device700in accordance with one implementation of the disclosure. The computing device700houses a board702. The board702may include a number of components, including but not limited to a processor704and at least one communication chip706. The processor704is physically and electrically coupled to the board702. In some implementations the at least one communication chip706is also physically and electrically coupled to the board702. In further implementations, the communication chip706is part of the processor704.

These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip706enables wireless communications for the transfer of data to and from the computing device700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip706may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device700may include a plurality of communication chips706. For instance, a first communication chip706may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip706may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor704of the computing device700includes an integrated circuit die packaged within the processor704. In some implementations of the disclosure, the integrated circuit die of the processor may be packaged in an electronic system that includes a multi-chip package with an interposer and a nested component that are coupled to one or more dies by interconnects, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip706also includes an integrated circuit die packaged within the communication chip706. In accordance with another implementation of the disclosure, the integrated circuit die of the communication chip706may be packaged in an electronic system700that includes a multi-chip package with an interposer and a nested component that are coupled to one or more dies by interconnects, in accordance with embodiments described herein.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example embodiment 1: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

Example embodiment 2: The electronic package of example embodiment 1, wherein the first interconnect and the second interconnect each include an intermediate pad, and a bump over the intermediate pad.

Example embodiment 3: The electronic package of example embodiment 1 or 2, further including a dielectric layer over and around the interposer and the nested component.

Example embodiment 4: The electronic package of example embodiment 3, wherein the intermediate pads are over a surface of the dielectric layer.

Example embodiment 5: The electronic package of example embodiment 4, wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the dielectric layer, and wherein the intermediate pad of the second interconnect is coupled to the component pad by a second via that passes through a portion of the dielectric layer.

Example embodiment 6: The electronic package of example embodiment 4, wherein the intermediate pad of the first interconnect is directly connected to the interposer pad, and wherein the intermediate pad of the second interconnect is directly connected to the component pad.

Example embodiment 7: The electronic package of example embodiment 1, 2, 3, 4, 5 or 6, wherein a centerline of the first interconnect is offset from a centerline of the interposer pad, and wherein a centerline of the second interconnect is offset from a centerline of the component pad.

Example embodiment 8: The electronic package of example embodiment 1, 2, 3, 4, 5, 6 or 7, wherein a first portion of the cavity is within a footprint of the die, and wherein a second portion of the cavity is outside of the footprint of the die.

Example embodiment 9: The electronic package of example embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the nested component is an active component.

Example embodiment 10: The electronic package of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, further including a second die, wherein the second die is coupled to the nested component by a third interconnect, the third interconnect including an intermediate pad, and a bump over the intermediate pad.

Example embodiment 11: The electronic package of example embodiment 10, wherein the nested component electrically couples the first die to the second die.

Example embodiment 12: The electronic package of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein an active surface of the nested component faces towards the die.

Example embodiment 13: The electronic package of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the interposer substrate includes glass, ceramic, silicon, silicon carbide, alumina, or organic materials.

Example embodiment 14: An electronic system includes a board and an interposer electrically coupled to the board. The interposer includes a cavity that passes into but not through an interposer substrate, a nested component in the cavity, a through interposer via (TIV) within the interposer substrate, and a core via beneath the nested component, the core via extending from the nested component through the interposer substrate. A first die is electrically coupled to the interposer and the nested component by a first plurality of interconnects. A second die is electrically coupled to the interposer and the nested component by a second plurality of interconnects.

Example embodiment 15: The electronic system of example embodiment 14, wherein the nested component electrically couples the first die to the second die.

Example embodiment 16: The electronic system of example embodiment 14 or 15, further including a package substrate, wherein the package substrate is electrically coupled to the board, and wherein the interposer is electrically coupled to the package substrate.

Example embodiment 17: An electronic package includes an interposer having a glass substrate, a cavity that passes into but not through the glass substrate, a through glass via (TGV) within the glass substrate, and an interposer pad electrically coupled to the TGV. The electronic package includes a silicon bridge die in the cavity, wherein the silicon bridge die includes a silicon bridge die pad coupled to a through-silicon via. A core via is beneath the silicon bridge die, the core via extending from the silicon bridge die through the glass substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the silicon bridge die pad by a second interconnect.

Example embodiment 18: The electronic package of example embodiment 17, wherein the first interconnect and the second interconnect each include an intermediate pad, and a bump over the intermediate pad.

Example embodiment 19: The electronic package of example embodiment 18 or 19, further including a dielectric layer over and around the interposer and the silicon bridge die.

Example embodiment 20: The electronic package of example embodiment 19, wherein the intermediate pads are over a surface of the dielectric layer.

Example embodiment 21: The electronic package of example embodiment 20, wherein the intermediate pad of the first interconnect is coupled to the interposer pad by a first via that passes through a portion of the dielectric layer, and wherein the intermediate pad of the second interconnect is coupled to the silicon bridge die pad by a second via that passes through a portion of the dielectric layer.

Example embodiment 22: The electronic package of example embodiment 20, wherein the intermediate pad of the first interconnect is directly connected to the interposer pad, and wherein the intermediate pad of the second interconnect is directly connected to the silicon bridge die pad.

Example embodiment 23: The electronic package of example embodiment 17, 18, 19, 20, 21 or 22, wherein a centerline of the first interconnect is offset from a centerline of the interposer pad, and wherein a centerline of the second interconnect is offset from a centerline of the silicon bridge die pad.

Example embodiment 24: The electronic package of example embodiment 17, 18, 19, 20, 21, 22 or 23, wherein a first portion of the cavity is within a footprint of the die, and wherein a second portion of the cavity is outside of the footprint of the die.

Example embodiment 25: The electronic package of example embodiment 17, 18, 19, 20, 21, 22, 23 or 24, further including a second die, wherein the second die is coupled to the silicon bridge die by a third interconnect, the third interconnect including an intermediate pad, and a bump over the intermediate pad.