Patent ID: 12191155

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The advanced lithography process, method, and materials described in the current disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs can be processed according to the above disclosure.

The present disclosure is directed to a patterning process for semiconductor structure. Specifically, the SADP technology is introduced in which mandrels are patterned, followed by the formation of spacers along sidewalls of the mandrels. The mandrels are removed while the spacers remain and are used to define a pattern at about half a pitch of the mandrels. The abovementioned patterning process may be performed to pattern lines in a semiconductor structure. The lines patterned in this way may attain a pitch that is difficult to achieve using existing lithographic equipment alone.

FIG.1is a flow diagram showing a method200of fabricating a semiconductor structure300shown inFIGS.14A and14B.FIGS.2A,7D,7E,8D,8E,9E and9Fare schematic perspective of the semiconductor structure views illustrating different stages of the method200.FIGS.2B,3B,4B,5B,5C,6B,6C,7B,8B,9C,9D,9G,10B,11B,12B,13B and14Bare schematic cross-sectional views illustrating different stages of sequential operations of the method200.FIGS.3A,4A,5A,6A,7A,7C,8A,8C,9A,10A,11A,12A,13A and14Aare schematic top views illustrating different stages of sequential operations of the method200.

In operation201, a stacked structure101is formed on a substrate100, as shown inFIGS.2A and2B. The stacked structure101includes a mask layer110over the substrate100and a resist layer over the mask layer110. In some embodiments, the substrate100is a semiconductor substrate including doped or undoped silicon (Si), a bulk semiconductor substrate, a crystalline semiconductor substrate or an active region of a semiconductor-on-insulator (SOI) substrate. The substrate100may include other semiconductor materials such as germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb) or alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP or combinations thereof.

In other embodiments, the substrate100can be replaced with a dielectric layer which includes, but not limited to, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), boro-phospho-silicate glass (BPSG), other low dielectric constant (<3.9) materials, or combinations thereof. In some embodiments, the dielectric layer is an interlayer dielectric layer or an inter-metal dielectric (IMD) layer. In some embodiments, the substrate100includes conductive lines or vias (i.e., metal lines) that provide electrical connections to subsequently formed components.

The mask layer110is formed on a top surface S1of the substrate100. In some embodiments, the mask layer110is formed of a metal or a metallic compound such as titanium (Ti), tantalum (Ta), titanium nitride (TiN) or tantalum nitride (TaN). The mask layer110may be formed of metal-doped carbide (e.g., tungsten carbide) or a metalloid (e.g., silicon nitride, boron nitride or silicon carbide). In other embodiments, the mask layer110includes silicon oxynitride (SiON), nitride, oxide, low-k or high-k dielectrics. These materials are usually considered to be a “hard mask.” The mask layer110may include a single-layer structure or a multilayer structure. The mask layer110may be formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like.

The resist layer120is formed on a top surface S2of the mask layer110. In some embodiments, the resist layer120is formed of a photoresist. The photoresist may be a single layer or include multiple layers. The resist layer120may be formed using spin coating or other suitable methods. In some embodiments, the resist layer120and the mask layer110are stacked over the substrate100along a thickness direction D1substantially orthogonal to the top surface S1of the substrate100. Each of the resist layer120and the mask layer110has a uniform thickness along a length direction D2and a width direction D3over the substrate100. The length direction D2and the width direction D3are respectively orthogonal to the thickness direction D1.

In operation203, the resist layer120of the stacked structure101is patterned, as shown inFIGS.3A and3B. In some embodiments, the patterning process at least includes a lithography operation, such as exposure and developing steps. After the patterning process, portions of the resist layer120are removed and the remaining portions of the resist layer120form a mandrel pattern122on the mask layer110. In some embodiments, multiple parallel trenches T1are formed in the mandrel pattern122and portions of a top surface S2of the mask layer110are exposed through the trenches T1. As illustrated inFIG.3B, in some embodiments, the trench T1extends along the length direction D2.

In operation205, a spacer layer130is formed on the stacked structure101, as shown inFIGS.4A and4B. The spacer layer130may be deposited over the mandrel pattern122and the mask layer110. In some embodiments, the material of the spacer layer130is selected to have a high etching selectivity between the mask layer110and mandrel pattern122. For example, the etching selectivity between the mandrel pattern122and the mask layer110is between about 2.0 and about 8.0. In some embodiments, the spacer layer130is formed of aluminum oxide (AlO3), titanium oxide (TiO2), tantalum oxide (Ta2O5), silicon oxide (SiO2), hafnium oxide (HfO2) or the like. The spacer layer130may be formed using a deposition process such as ALD, CVD, or the like.

As illustrated inFIG.4B, the spacer layer130covers sidewalls of the mandrel pattern122and portions of the top surface S2of the mask layer110. In some embodiments, the spacer layer130is conformally formed such that the spacer layer130has substantially equal thicknesses across sidewalk and top surfaces of the mandrel pattern122.

In operation207, an etching operation is performed on the spacer layer130, as shown inFIGS.5A,5B and5C.FIGS.5B and5Care schematic cross-sectional views respectively taken along line A-A′ and line B-B′ shown inFIG.5A. In some embodiments, the etching process for removing portions of the spacer layer130is achieved by reactive ion etching (RIE). During the etching operation, the spacer layer130over the mandrel pattern122is completely removed and the spacer layer130over the mask layer110is partially removed. In such embodiments, the remaining portion of the spacer layer130forms multiple spacer patterns132left on sidewalk of the mandrel pattern122. The spacer pattern132may have a closed contour, e.g., the spacer pattern132includes an opening O1from a top-view perspective.

As illustrated inFIGS.5B and5C, in some embodiments, the opening O1extends along the length direction D2. Multiple openings O1may be formed over the mask layer110and parallel to each other. Portions of the mask layer110are exposed through the openings O1.

In operation209, the mandrel pattern122is removed, as shown inFIGS.6A,6B and6C.FIGS.6B and6Care schematic cross-sectional views respectively taken along line A-A′ and line B-B′ shown inFIG.6A. An etching operation may be used to remove the mandrel pattern122and leave the spacer patterns132on the mask layer110. In some embodiments, the mandrel pattern122is differentiated from the spacer patterns132and the mask layer110in terms of an etching selectivity of the same etchant. The etching process may be selective to the mandrel pattern122and do not remove (or remove insignificantly) the spacer patterns132and the mask layer110. Therefore, the mandrel pattern122can be completely removed while the spacer patterns132and the mask layer110are kept substantially intact after the etching process. In some embodiments, the underlying mask layer110acts as an etch stop layer during the removal of the mandrel pattern122. After the mandrel pattern122is removed, each of the spacer patterns132is formed on the mask layer110along with the respective opening O1. The opening O1may be defined by the spacer pattern132as a closed contour. In some embodiments, at least one of the spacer patterns132has a ring shape when viewed from above. The ring-shaped spacer pattern132may have rounded corners around their top portions. In some embodiments, each of the spacer patterns132has a pair of length portions L1extending along the length direction D2, a pair of width portions R1extending along the width direction D3, and corner portions C1connecting the length portions L1and the width portions R1.

In operation211, at least one directional etching operation is performed on the spacer patterns132, as shown inFIGS.7A to7E and8A to8E. In some embodiments, the directional etching operation includes a slanted plasma etching. The tilt angle of the plasma may be controlled based on a desired etching profile so as to adjust the etching direction.

Referring toFIG.7A, in some embodiments, a directional etching operation E11is applied to the spacer patterns132along the length direction D2from a top-view perspective. The directional etching operation E11may be selective to the spacer patterns132and do not remove (or substantially do not remove) the mask layer110. As shown inFIG.7A, the width portions R1and the corner portion C1of the spacer patterns132are orthogonal to an incident direction of the directional etching operation E11, as shown inFIG.7A, and therefore the width portions R1and the corner portions C1of the spacer patterns132may encounter more plasma than the length portions L1. In such embodiments, the width portions R1and the corner portions C1receive more ion treatments or plasma bombardment during the directional etching operation E11. In some embodiments, the directional etching operation E11is used to trim the width portions R1while substantially preserving the length portions L1from trimming.

FIG.7Bis a schematic cross-sectional view taken along line B-B′ shown inFIG.7A. In the directional etching operation E11, a plasma with a first tilt angle θ1is used to bombard the width portions R1along one side of the length direction D2(i.e., the left side of the length direction D2in the cross-sectional view). The first tilt angle θ1refers to an angle between the incident direction of the directional etching operation E11and a normal axis Z1that extends along the thickness direction D1.

FIG.7Cillustrates one of the spacer patterns132shown inFIG.7Abeing etched during the directional etching operation E11from a top-view perspective. The width portion R1may include a first width portion R11and a second width portion R12opposite to each other. In some embodiments, the width portion R11is bombarded from an exterior side of the spacer pattern132, and the width portion R12is bombarded from an interior side of the spacer pattern132. In such embodiments, the two opposing width portions R11and R12are simultaneously bombarded by the plasma in the directional etching operation E11. As the plasma continuously bombards the first and second width portions R11, R12, the opening O1is gradually elongated along the length direction D2. After the two opposing width portions R11and R12are etched through, the closed contour of the spacer pattern132is broken or cut open. Corner portions C1of the spacer pattern132may be partially trimmed during the removal of the width portion R1.

FIGS.7D and7Eare respectively schematic perspective views of the first and second width portions R11and R12inFIG.7C. In some embodiments, the first width portion R11is directionally etched from the exterior side of the spacer pattern132, as shown inFIG.7D. In some embodiments, the second width portion R12is directionally etched from the interior side of the spacer pattern132, as shown inFIG.7E. In such embodiments, the exterior and interior sides of the spacer pattern132are simultaneously etched.

Referring toFIG.8A, in some embodiments, a directional etching operation E12is applied to the spacer patterns132along the length direction D2from a top-view perspective. In some embodiments, the directional etching operation E12is applied along an opposite direction to the directional etching operation E11from a top-view perspective. The directional etching operation E12may be similar to the directional etching operation E11in many aspects except for the incident direction.

FIG.8Bis a schematic cross-sectional view taken along line B-B′ shown inFIG.8A. In the directional etching operation E12, a plasma with a second tilt angle θ2is used to bombard the width portions R1along the other side of the length direction D2(i.e., the right side of the length direction D2in the cross-sectional view). The definition of the second tilt angle θ2may be the same as the first tilt angle θ1but symmetrical to the first tilt angle θ1with respect to the normal axis Z1. In some embodiments, the second tilt angle θ2is substantially equal to the first tilt angle θ1in value. In other embodiments, the first tilt angle θ1and the second tilt angle θ2are different.

FIG.8Cillustrates one of the spacer patterns132shown inFIG.8Abeing etched during the directional etching operation E12from a top-view perspective. In some embodiments, the width portion R11is bombarded from the interior side of the spacer pattern132, and the width portion R12is bombarded from the exterior side of the spacer pattern132. In such embodiments, the two opposing width portions R11and R12are simultaneously bombarded by the plasma in the directional etching operation E12.

FIGS.8D and8Eare respectively schematic perspective views of the first and second width portions R11and R12inFIG.8C. In some embodiments, the first width portion R11is directionally etched from the interior side of the spacer pattern132, as shown inFIG.8D. In some embodiments, the second width portion R12is directionally etched from the exterior side of the spacer pattern132, as shown inFIG.8E. In such embodiments, the exterior and interior sides of the spacer pattern132are simultaneously etched.

In some embodiments, the directional etching operation E11and the directional etching operation E12together etch through the first and second width portions R11, R12and break the closed contour of the spacer pattern132. In such embodiments, the two directional etching operations E11and E12are alternatively performed with more than one cycle, such as 2 to 4 cycles, until the width portions R1of the spacer patterns132are completely removed. In other embodiments, the directional etching operation E11alone etches through the first and second width portions R11, R12and breaks the closed contour of the spacer pattern132.

FIG.9Ais a schematic top view illustrating multiple spacer features134generated from the spacer patterns132after operation211. After applying the directional etching operation E11and/or the directional etching operation E12, the spacer features134are formed on the mask layer110. In some embodiments, the spacer features134extend along the length direction D2. In some embodiments, the spacer features134are arranged in parallel along the width direction D3.

FIG.9Bis a schematic top view continued fromFIG.7C or8Cand shows a pair of spacer features134. Since the directional etching operations E11and E12are symmetrical to each other, two adjacent spacer features134may be formed in a pair when a single spacer pattern132is etched to remove its opposite width portions R11and R12. In some embodiments, each of the spacer patterns132is cut into two spacer features134A and134B. The two spacer features134A and134B may be symmetrical with respect to a central line M1extending in the length direction D2between the two spacer features134A and134B from a top-view perspective. That is, the two spacer features134A and134B may mirror images to each other. The spacer features134may have rounded or sharp corners from a top-view perspective. In some embodiments, each of the spacer features134A and134B has two trimmed ends136, The trimmed end136may have a sharp corner137connected to the inner sides of the length portion L1and a round corner138connected to the outer sides of the length portion L1.

FIG.9Cis a schematic cross-sectional view taken along line A-A′ shown inFIG.9A. In some embodiments, any two adjacent spacer features134have a fixed pitch P1, which is a feature of an SADP process. The pitch P1is substantially equals to a total width of one opening O1(as shown inFIG.6B) and one spacer feature134.

FIG.9Dis a schematic cross-sectional view taken along line B-B′ shown inFIG.9A. Since the spacer features134are formed along the length direction D2, there may be no spacer feature134shown in the cross-sectional view along line B-B′.

FIGS.9E and9Fillustrate schematic perspective views of spacer features134. Each of the spacer features134may have an inner sidewall W1and an outer sidewall W2. The inner sidewall W1may be connected to the outer sidewall W2via a boundary line B1. In some embodiments, the inner sidewall W1is substantially a flat surface. The inner sidewall W1may face the width direction D3, and the pair of inner sidewalls W1may face each other. In some embodiments, the outer sidewall W2is substantially a curved surface. The outer sidewall W2at least includes a round portion near the boundary line B1and may include a flat portion connected to the length portion L1.

Referring toFIG.9E, in some embodiments, the boundary line B1is upright and parallel to the normal axis Z1. That is, the angle between the boundary line B1and the normal axis Z1is substantially 0 degrees. In such embodiments, the inner sidewall W1has a rectangular shape, and the outer sidewall W2is substantially upright.

Referring toFIG.9F, in some embodiments, the boundary line B1is slanted and apart from the normal axis Z1, That is, an inclination angle α greater than 0 degrees may exist between the boundary line B1and the normal axis Z1. In such embodiments, the inner sidewall W1has a trapezoid shape and the outer sidewall W2is at least partially inclined. In some embodiments, the outer sidewall W2includes a bevel portion around the boundary line B1.

FIG.9Gis a schematic cross-sectional view taken along line C-C′ shown inFIG.9A. The spacer feature134may have a pair of boundary lines B1at two ends of the inner sidewall W1. In some embodiments, the inclination angle α between the boundary line B1and the normal axis Z1is between about −60 to about +60 degrees. The minus sign of the “−60 degrees” may refer to the inclination angle α measured in a counterclockwise direction from the normal axis Z1, and the plus sign of the “+60 degrees” refers to the inclination angle α measured in a clockwise direction from the normal axis Z1. In some other embodiments, the minus sign of the “−60 degrees” may refer to the inclination angle α measured in a clockwise direction from the normal axis Z1, and the plus sign of the “+60 degrees” refers to the inclination angle α measure in a counterclockwise direction from the normal axis Z1. In some embodiments, when one end of the inner sidewall W1corresponds to an inclination angle of +α, the other end of the inner sidewall W1corresponds to an inclination angle of −α, and vice versa.

The present disclosure uses an SADP technology in accompany with a directional etching operation to cut spacer patterns into a pair of spacer features, which can save a lithographic process. With the use of the directional etching operation, a photomask and lithography operations used to form a photoresist pattern that protect the length portions L1and expose the width portions R1of the spacer patterns132are saved. As a result, the manufacturing process can be simplified and the process cost can be reduced.

In operation213, the mask layer110of the stacked structure101is patterned, as shown inFIGS.10A and10B. In some embodiments, the mask layer110is etched using the spacer features134as an etch mask. In some embodiments, the underlying substrate100acts as an etch stop layer during the patterning of the mask layer110. After the patterning process, portions of the mask layer110are removed and portions of the top surface S1are exposed. The remaining portion of the mask layer110forms multiple mask patterns112over the substrate100.

In operation215, the spacer features134are removed, as shown inFIGS.11A and11B. An etching process may be used to remove the spacer features134and leave the mask patterns112on the substrate100. In some embodiments, the spacer features134are differentiated from the mask patterns112and the substrate100in terms of an etching selectivity of the same etchant. The etching process may be selective to the spacer features134and do not remove (or substantially do not remove) the mask patterns112and the substrate100. Therefore, the spacer features134can be completely removed while the mask patterns112and the substrate100are kept substantially intact after the etching process.

As illustrated inFIG.11B, after the spacer features134are removed, each of the mask patterns112is formed on the substrate100and extend along the length direction D2. In some embodiments, the mask patterns112are parallel arranged along the width direction D3. Referring toFIGS.9C and11B, the pitch P1of the spacer features134may be provided as the pitch of the mask patterns112.

In operation217, the substrate100is patterned, as shown inFIGS.12A and12B, In some embodiments, the substrate100is etched using the mask patterns112as an etch mask. After the patterning process, portions of the substrate100are removed and the remaining substrate100forms a substrate102. As illustrated inFIG.12B, in some embodiments, the substrate102includes multiple protruding fin patterns104. The fin patterns104are respectively covered by the mask patterns112.

In operation219, the mask patterns112are removed, as shown inFIGS.13A and13B. An etching process may be used to remove the mask patterns112and leave the substrate102. In some embodiments, the mask patterns112are differentiated from the substrate102in terms of an etching selectivity of the same etchant. The etching process may be selective to the mask patterns112and do not remove (or substantially do not remove) the substrate102. Therefore, the mask patterns112can be completely removed while the substrate102are kept substantially intact after the etching process. As illustrated inFIG.13B, in some embodiments, the fin patterns104extend along the length direction D2and are arranged in parallel along the width direction D3. In some embodiments, a trench H1is formed between two adjacent fin patterns104from a cross-sectional view. Multiple trenches H1may be arranged between the fin patterns104.

In operation221, a dielectric layer140is deposited onto the substrate102, as shown inFIGS.14A and14B. In some embodiments, the material of the dielectric layer140includes oxide, nitride, oxynitride, carbide, a combination thereof, or the like. The dielectric layer140may be formed using a deposition process such as CVD.

In some embodiments, the trench H1is not completely filled with the dielectric layer140. The fin patterns104may protrude from the dielectric layer140. In other embodiments, the trench H1is completely filled with the dielectric layer140. As a result, the semiconductor structure300formed using the method200has been fabricated.

In some embodiments, multiple directional etching operations are used in the method200. One or more of these directional etching operations may be used to trim a target pattern or remove a sacrificial pattern that is otherwise removed by another operation.FIGS.15A and15Bare schematic top views illustrating various applications of the directional etching operation. Referring toFIG.15A, multiple target patterns150may be arranged in parallel along the width direction D3and over a substrate (not shown). Each of the target patterns150extends along the length direction D2. In some embodiments, the target patterns150are spacer patterns, mask patterns, fins of FinFETs or the like. The target patterns150may have a first length L10. Multiple sacrificial patterns160may be disposed near end portions of the target patterns150. Each of the sacrificial patterns160extends along the width direction D3.

In some embodiments, a directional etching operation E10is applied to the target patterns150along the length direction D2. The directional etching operation E10may at least include two single etching operations with respective etching directions. Either etching operation can be applied downwards or upwards to the target patterns150from a top-view perspective. As illustrated inFIG.15A, all of the sacrificial patterns160may receive most of the ion bombardments of the directional etching operation E10since each sacrificial patterns160is substantially orthogonal to an incident direction the directional etching E10. After receiving a significant amount of ion treatments or plasma bombardment of the directional etching operation E10, all of the sacrificial patterns160may be removed, as shown inFIG.15B. The removal of the sacrificial patterns160does not require any additional lithographic process. Since there is no need to use any photomask or photoresist, the processing cost can be greatly reduced.

Further, two ends152of each target patterns150may receive part of the directional etching operation E10. The two ends152may be partially or completely removed at the same time as the sacrificial patterns160are removed. Therefore, the target patterns150can be trimmed. Referring toFIG.14B, after the directional etching operation E10, the remaining portion of the target pattern150may have a second length L20substantially less the first length L10. In some embodiments, the trimmed ends of the target patterns150have a sharp corner or a round corner from a top-view perspective.

FIGS.16A,16B,17A,17B,18A and18Bare schematic top views illustrating multiple directional etching operations applied in the method200.

Continued fromFIG.9Aand referring toFIG.16A, in some embodiments, the method200further includes a second directional etching operation E2performed on the spacer features134between operation211and operation213. The second directional etching operation E2may at least include two single etching operations with respective etching directions. Either etching operation can be applied downwards or upwards to the spacer features134from a top-view perspective. In some embodiments, the second directional etching operation E2includes a slanted plasma etching. The tilt angle of the plasma may be controlled based on a desired etching profile so as to adjust the etching direction. In some embodiments, the second directional etching operation E2is applied to the spacer features134along the length direction D2. Two ends (marked as dashed boxes) of each spacer features134may be at least partially removed. Therefore, the spacer features134can be trimmed to have a desired length, as shown inFIG.16B, prior to subsequent operations. In some embodiments, the trimmed ends of the spacer feature134have a sharp corner or a round corner from a top-view perspective.

Continued fromFIG.11Aand referring toFIG.17A, in some embodiments, the method200further includes a third directional etching operation E3performed on the mask patterns112between operation215and operation217. The third directional etching operation E3may at least include two single etching operations with respective etching directions. Either operation can be applied downwards or upwards to the mask patterns112from a top-view perspective. In some embodiments, the third directional etching operation E3includes a slanted plasma etching. The tilt angle of the plasma may be controlled based on a desired etching profile so as to adjust the etching direction. In some embodiments, the third directional etching operation E3is applied to the mask patterns112along the length direction D2. Two ends (marked as dashed boxed) of each mask patterns112may be at least partially removed. Therefore, the mask patterns112can be trimmed to have a desired length, as shown inFIG.17B, prior to subsequent operations. In some embodiments, trimmed ends of the mask patterns112have a sharp corner or a round corner from a top-view perspective.

Continued fromFIG.13Aand referring toFIG.18A, in some embodiments, the method200further includes a fourth directional etching operation E4performed on the fin patterns104between operation219and operation221. The fourth directional etching operation E4may at least include two etching operations with respective etching directions. Either operation can be applied downwards or upwards to the fin patterns104from a top-view perspective. In some embodiments, the fourth directional etching operation E4includes a slanted plasma etching. The tilt angle of the plasma may be controlled based on a desired etching profile so as to adjust the etching direction. In some embodiments, the fourth directional etching operation E4is applied to the fin patterns104along the length direction D2. Two ends (marked as dashed boxes) of each fin patterns104may be at least partially removed. Therefore, the fin patterns104can be trimmed to have a desired length, as shown inFIG.18B, prior to subsequent operations. In some embodiments, the trimmed ends of the fin patterns104have a sharp corner or a round corner from a top-view perspective.

The directional etching operations E2, E3and E4do not require any lithographic process. As a result, the trimming of spacer features134, mask patterns112or fin patterns104does not need any photomask or photoresist, and thus the processing cost can be greatly reduced. It is noted that one or more of the directional etching operations E2, E3and E4may be optional. Therefore, each of the directional etching operations E2, E3and E4may be used in accompany with the use of the directional etching operation E1.

One aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

One aspect of the present disclosure provides another method of manufacturing a semiconductor structure. The method includes providing a substrate; forming a mask layer over the substrate; forming a mandrel pattern over the mask layer, wherein the mandrel pattern extends along a first direction; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern to form an opening defined by the spacer pattern, wherein the spacer pattern has a closed contour; and applying a directional etching operation along the first direction to etch two opposing sidewalls of the spacer pattern.

One aspect of the present disclosure provides another method of manufacturing a semiconductor structure. The method includes providing a substrate; forming at least one target pattern on the substrate, wherein the at least one target pattern extends along a first direction; forming at least one sacrificial pattern adjacent to the at least one target pattern, wherein the at least one sacrificial pattern extends along a second direction perpendicular to the first direction; and applying a directional etching operation along the first direction to trim two ends of the at least one target pattern.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.