Patent ID: 12191391

DETAILED DESCRIPTION

Referring toFIGS.1-2, in whichFIG.1is a top view illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention, the left portion ofFIG.2illustrates a cross-sectional view ofFIG.1for fabricating the semiconductor device along the sectional line AA′, and the right portion ofFIG.2illustrates a cross-sectional view ofFIG.1for fabricating the semiconductor device along the sectional line BB′. As shown inFIGS.1-2, a substrate12, such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, a first region such as a NMOS region14and a second region such as a PMOS region16are defined on the substrate12, and at least a fin-shaped structure18is formed on each of the NMOS region14and PMOS region16. It should be noted that even though four fin-shaped structures18are disposed on each of the transistor regions in this embodiment, it would also be desirable to adjust the number of fin-shaped structures18depending on the demand of the product, which is also within the scope of the present invention.

Preferably, the fin-shaped structures18of this embodiment could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained.

Alternatively, the fin-shaped structures18could also be obtained by first forming a patterned mask (not shown) on the substrate,12, and through an etching process, the pattern of the patterned mask is transferred to the substrate12to form the fin-shaped structures18. Moreover, the formation of the fin-shaped structures18could also be accomplished by first forming a patterned hard mask (not shown) on the substrate12, and a semiconductor layer composed of silicon germanium is grown from the substrate12through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structures18. These approaches for forming fin-shaped structure are all within the scope of the present invention. It should be noted that after the fin-shaped structures18are formed, a liner22made of silicon oxide could be formed on the surface of the fin-shaped structures18on the NMOS region14and PMOS region16.

Next, a shallow trench isolation (STI)20is formed around the fin-shaped structures18. In this embodiment, the formation of the STI20could be accomplished by conducting a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer on the substrate12and covering the fin-shaped structures18entirely. Next, a chemical mechanical polishing (CMP) process along with an etching process are conducted to remove part of the silicon oxide layer so that the top surface of the remaining silicon oxide is slightly lower than the top surface of the fin-shaped structures18for forming the STI20.

Next, as shown inFIG.2, an etching process is conducted by using a patterned mask (not shown) as mask to remove part of the liner22and part of the fin-shaped structures18to form trenches24, in which each of the trenches24preferably divides each of the fin-shaped structures18disposed on the NMOS region14and PMOS region16into two portions, including a portion26on the left side of the trench24and a portion28on the right side of the trench24. In this embodiment, the width of the trench24on the NMOS region14is preferably greater than the width of the trench24on the PMOS region16. Nevertheless, according to other embodiment of the present invention, it would also be desirable to adjust the width of the trenches24on both NMOS region14and PMOS region16so that the trenches24on both region14,16could have same widths or different widths, which are all within the scope of the present invention.

Next, as shown inFIG.3, an oxidation process is conducted to form another liner30made of silicon oxide in the trenches24on the NMOS region14and PMOS region16, in which the liner30is disposed on the bottom surface and two sidewalls of the trenches24and contacting the liner22directly. Next, a dielectric layer32is formed in the trenches24and filling the trenches24completely, and a planarizing process such as chemical mechanical polishing (CMP) process and/or etching process is conducted to remove part of the dielectric layer32so that the top surface of the remaining dielectric layer32is even with or slightly higher than the top surface of the fin-shaped structures18. This forms a double diffusion break (DDB) structure34on the NMOS region14and a SDB structure34on the PMOS region16at the same time.

Preferably, two gate structures will be formed on the DDB structure34in the later process whereas only a single gate structure will be formed on the SDB structure36. As shown inFIG.1, each of the fin-shaped structures18on the NMOS region14and PMOS region16are disposed extending along a first direction (such as X-direction) while the DDB structure34and the SDB structure36are disposed extending along a second direction (such as Y-direction), in which the first direction is orthogonal to the second direction.

It should be noted that the dielectric layer32and the liner30in this embodiment are preferably made of different materials, in which the liner30is preferably made of silicon oxide and the dielectric layer32is made of silicon oxycarbonitride (SiOCN). Specifically, the DDB structure34and the SDB structure36made of SiOCN in this embodiment are preferably structures having low stress, in which the concentration proportion of oxygen within SiOCN is preferably between 30% to 60% and the stress of each of the DDB structure34and the SDB structure36is between 100 MPa to −500 MPa or most preferably at around 0 MPa. In contrast to the conventional DDB or SDB structures made of dielectric material such as silicon oxide or silicon nitride, the SDB structures of this embodiment made of low stress material such as SiOCN could increase the performance of on/off current in each of the transistors thereby boost the performance of the device.

Next, as shown inFIG.4, an ion implantation process could be conducted to form deep wells or well regions in the fin-shaped structures18on the NMOS region14and PMOS region16, and a clean process could be conducted by using diluted hydrofluoric acid (dHF) to remove the liner22on the surface of the fin-shaped structures18completely, part of the liner30on sidewalls of the trenches24, and even part of the DDB structure34and the SDB structure36. This exposes the surface of the fin-shaped structures18and the top surfaces of the remaining liner30, the DDB structure34, and the SDB structure36are slightly lower than the top surface of the fin-shaped structures18while the top surface of the DDB structure34and the SDB structure36is also slightly higher than the top surface of the remaining liner30.

Next, as shown inFIG.5, at least a gate structure such as gate structures38,40,74or dummy gates are formed on the fin-shaped structures18on the NMOS region14and PMOS region16. In this embodiment, the formation of the first gate structure38,40,74could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a high-k last approach, a gate dielectric layer42or interfacial layer, a gate material layer44made of polysilicon, and a selective hard mask could be formed sequentially on the substrate12or fin-shaped structures18, and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of the gate material layer44and part of the gate dielectric layer42through single or multiple etching processes. After stripping the patterned resist, gate structures38,40,74each composed of a patterned gate dielectric layer42and a patterned material layer44are formed on the fin-shaped structures18.

It should be noted that the formation of the gate structures38,40,74by patterning the gate material layer44could be accomplished by a sidewall image transfer (SIT) process. For instance, a plurality of patterned sacrificial layers or mandrels having same widths and same distance therebetween could be formed on the gate material layer44and then deposition and etching process could be conducted to form spacers on sidewalls of the patterned sacrificial layers. After removing the patterned sacrificial layers, the pattern of the spacers is then transferred to the gate material layer44for forming gate structures38,40,74. In this embodiment, two gate structures38,40are formed on the DDB structure34on NMOS region16while only a single gate structure74is formed on the SDB structure36on PMOS region14, in which the width of each of the gate structures38,40on the NMOS region16is substantially equal to the width of the gate structure74on the PMOS region14. Nevertheless, according to other embodiment of the present invention, it would also be desirable to adjust the size including widths of the gate structures38,40,74during the formation of the gate structures38,40,74so that the width of each of the gate structures38,40on the NMOS region14could be less than or greater than the width of the gate structure74on the PMOS region16, which are all within the scope of the present invention.

Next, at least a spacer46is formed on sidewalls of the each of the gate structures38,40,74, a source/drain region48and/or epitaxial layer50is formed in the fin-shaped structure18adjacent to two sides of the spacer46, and selective silicide layers (not shown) could be formed on the surface of the source/drain regions48. In this embodiment, each of the spacers46could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer and a main spacer. Preferably, the offset spacer and the main spacer could include same material or different material while both the offset spacer and the main spacer could be made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof. The source/drain regions48and epitaxial layers50could include different dopants and/or different materials depending on the conductive type of the device being fabricated. For instance, the source/drain region48on the NMOS region14could include n-type dopants and the epitaxial layer50on the same region could include silicon phosphide (SiP) while the source/drain region48on the PMOS region16could include p-type dopants and the epitaxial layer50on the same region could include silicon germanium (SiGe). It should be noted that since the spacers46and the DDB structure34on the NMOS region14could be made of same material including but not limited to for example silicon oxide or silicon nitride, part of the DDB structure34could be removed to form at least a protrusion76between the two gate structures38,40when deposition and etching back processes were conducted to form the spacers46.

Next, as shown inFIG.6, a contact etch stop layer (CESL)52is formed on the surface of the fin-shaped structures18and covering the gate structures38,40,74, and an interlayer dielectric (ILD) layer54is formed on the CESL52. Next, a planarizing process such as CMP is conducted to remove part of the ILD layer54and part of the CESL52for exposing the gate material layer44made of polysilicon, in which the top surface of the gate material layer44is even with the top surface of the ILD layer54.

Next, a replacement metal gate (RMG) process is conducted to transform the gate structures38,40,74into metal gates60. For instance, the RMG process could be accomplished by first performing a selective dry etching or wet etching process using etchants including but not limited to for example ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer44and even gate dielectric layer42from the gate structures38,40,74for forming recesses56in the ILD layer54.

Next, as shown inFIG.7, a selective interfacial layer or gate dielectric layer62, a high-k dielectric layer64, a work function metal layer66, and a low resistance metal layer68are formed in the recesses56, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer68, part of work function metal layer66, and part of high-k dielectric layer64to form metal gates60. Next, part of the low resistance metal layer68, part of the work function metal layer66, and part of the high-k dielectric layer64are removed to form a recess (not shown) on each of the transistor region, and a hard mask70made of dielectric material including but not limited to for example silicon nitride is deposited into the recesses so that the top surfaces of the hard mask70and ILD layer54are coplanar. In this embodiment, each of the gate structures or metal gates60fabricated through high-k last process of a gate last process preferably includes an interfacial layer or gate dielectric layer62, a U-shaped high-k dielectric layer64, a U-shaped work function metal layer66, and a low resistance metal layer68.

In this embodiment, the high-k dielectric layer64is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer64may be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof.

In this embodiment, the work function metal layer66is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the work function metal layer66having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer66having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer66and the low resistance metal layer68, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer68may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.

Next, a pattern transfer process is conducted by using a patterned mask (not shown) as mask to remove part of the ILD layer54and part of the CESL52for forming contact holes (not shown) exposing the source/drain regions48underneath. Next, metals including a barrier layer selected from the group consisting of Ti, TiN, Ta, and TaN and a low resistance metal layer selected from the group consisting of W, Cu, Al, TiAl, and CoWP are deposited into the contact holes, and a planarizing process such as CMP is conducted to remove part of aforementioned barrier layer and low resistance metal layer for forming contact plugs72electrically connecting the source/drain regions48. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention.

It should be noted that even though a SIT scheme is employed to form the gate structures38,40,74on NMOS region14and PMOS region16respectively, according to other embodiment of the present invention, it would also be desirable to first form gate structures and spacers having equal widths on NMOS region14and PMOS region16at the same time, remove the gate structure made of polysilicon on the NMOS region14so that the remaining spacer could be used as a sacrificial gate structure, and then form new spacer on sidewalls of the sacrificial gate structure on the NMOS region14. Next, RMG process conducted fromFIGS.6-7could be carried out to transform the sacrificial or dummy gate structure originally made from spacer on NMOS region14and the gate structure made from polysilicon on PMOS region16to metal gates. In this approach, since the metal gate on the NMOS region14is transformed from spacer, the width of the final metal gate formed on NMOS region14would be equal to the width of the spacer on each sidewall of the gate structure74on PMOS region16.

Referring toFIG.7,FIG.7further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG.7, the semiconductor device includes a DDB structure34disposed on the NMOS region14for dividing the fin-shaped structure18on the NMOS region14into two portions including portions26and28adjacent to two sides of the DDB structure34, gate structures38and40disposed on the DDB structure34, a SDB structure36disposed on the PMOS region16for dividing the fin-shaped structure18on the PMOS region16into two portions including portions26and28adjacent to two sides of the SDB structure36, and a single gate structure74disposed on the SDB structure36.

In this embodiment, the two gate structures38,40disposed on the DDB structure34preferably overlap the fin-shaped structure18and the DDB structure34at the same time. For instance, the left gate structure38is disposed to overlap or stand on the fin-shaped structure18on the left and part of the DDB structure34at the same time while the right gate structure40is disposed to overlap the fin-shaped structure18on the right and part of the DDB structure34at the same time. Preferably, the bottom surfaces of the gate structures38,40disposed directly on the DDB structure34are slightly lower than the top surface of the fin-shaped structure18on two adjacent sides. Specifically, the DDB structure34also includes a protrusion76protruding from the top surface of the DDB structure34and between the two gate structures38,40, in which the top surface of the protrusion76could be slightly lower than, even with, or higher than the top surface of the fin-shaped structure18.

Only a single gate structure74however is disposed on top of the SDB structure36on the PMOS region16, in which the bottom surface of the gate structure74is preferably lower than the top surface of the fin-shaped structure18on two adjacent sides as the gate structure74is standing on the fin-shaped structure18and the SDB structure36at the same time. Preferably, the width of each of the gate structures38,40on the DDB structure34could be less than, equal to, or greater than the width of the gate structure74disposed on the SDB structure36, the width of either bottom surface or top surface of the DDB structure34could be less than, equal to, or greater than the width of bottom surface or top surface of the SDB structure36, and the top surface of the DDB structure34excluding the protrusion76could be lower than, even with, or higher than the top surface of the SDB structure36, which are all within the scope of the present invention.

Overall, the present invention provides an approach for integrating DDB structure and SDB structure for accommodating tensile stress applied on NMOS devices and compressive stress applied on PMOS devices, in which a DDB structure is formed on the NMOS region while a SDB structure is formed on the PMOS region. Structurally, the top surface of both the DDB structure and SDB structure is slightly lower than the top surface of fin-shaped structures on two adjacent sides, two gate structures are disposed on the DDB structure and fin-shaped structures on two adjacent sides at the same time, a protrusion is formed on the top surface of the DDB structure and between the two gate structures, and only a single gate structure is disposed on the SDB structure and fin-shaped structures on two adjacent sides.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.