Patent ID: 12222748

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, hardware manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are utilized in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Please refer toFIG.1, which is a schematic diagram of a clock generating circuit1according to an embodiment of the present invention. The clock generating circuit1includes a gray counter10, a shielding circuit20, an input terminal30and an output terminal40. The input terminal30is configured to receive a clock signal CK provided by a phase-locked loop (PLL) or a delay-locked loop (DLL), and the output terminal40is configured to output an output signal OUT. The gray counter circuit10is coupled to the input terminal, and configured to divide the clock signal CK by 2 to produce a first output signal OUT1. It should be noted that the gray counter circuit10(also known as a binary counter) includes a ripple counter circuit12and an encoder circuit14. The encoder circuit14converts a binary code output by the ripple counter circuit12into a gray code output. The process of converting the binary code to the gray code is well known in the art and will not be discussed in detail here.

When the clock signal CK has a very high frequency (e.g., greater than a threshold of 800 MHZ, but not limited thereto), the first output signal OUT1generated by the gray counter10may have a glitch. If the glitch is fed directly to the ADC, it can cause the ADC to malfunction. To eliminate the glitch from the first output signal OUT1, the shielding circuit20is coupled to the input terminal30(which receives the clock signal CK), the gray counter circuit10and the output terminal40. Specifically, the shielding circuit20is configured to shield the glitch from the first output signal OUT1and generate the output signal OUT based on the clock signal CK. It is important to note that the glitch in the first output signal OUT1is related to the clock signal CK. Therefore, the shielding circuit20may determine when the glitch occurs by analyzing the clock signal CK, and eliminate the glitch accordingly. This ensures that the output signal OUT has a better duty cycle of 50%-50% and contains no glitch (i.e., deglitch), which prevents ADC malfunction or missing code.

To implement the clock generating circuit1, please refer toFIG.2, which is a schematic diagram of an embodiment of the clock generating circuit1. InFIG.2, the ripple counter circuit12includes a first D-flip flop circuit DFF1and a second D-flip flop circuit DFF2. The first D-flip flop circuit DFF1includes a first clock input terminal CK1, a first data input terminal D1, a first data output terminal Q1and a first inverted data output terminal QB1. The second D-flip flop circuit DFF2includes a second clock input terminal CK2, a second data input terminal D2, a second data output terminal Q2and a second inverted data output terminal QB2. In detail, the first clock input terminal CK1is configured to receive the clock signal CK. The first data output terminal Q1is coupled to the second clock input terminal CK2and configured to output the first data output signal. The second data output terminal Q2is configured to output the second data output signal. The first data input terminal D1is coupled to the first inverted data output terminal QB1. The second data input terminal D2is coupled to the second inverted data output terminal QB2. On the other hand, the encoder circuit14is an exclusive or (XOR) circuit XOR1, including a third input data terminal and a fourth input data terminal to receive the first data output signal and the second data output signal, respectively, and a third data output terminal to output the first output signal OUT1according to the first data output signal and the second data output signal. In other words, the XOR circuit XOR1converts the binary codes (i.e., the first data output signal and the second data output signal) into the gray code (i.e., the first output signal OUT1).

Furthermore, please refer toFIG.2, the shielding circuit20is a D-latch circuit202, which includes a fifth input data terminal D3to receive the first output signal OUT1, a third clock input terminal CK3to receive the clock signal CK, and a fourth data output terminal Q3to output the output signal OUT based on the first output signal OUT1and the clock signal CK. Please refer toFIG.3Afor more details.FIG.3Ais a waveform diagram of the clock signal CK, the first output signal OUT1and the output signal OUT, as well as a detail circuit diagram and a truth table of the D-latch circuit202according to an embodiment of the present invention. As shown in the circuit diagram of the D-latch circuit202, the D-latch circuit202consists of multiplexer MUX, transmission gate TG or switch SW. The D-latch circuit202is well known in the art, and will not be repeated here. As shown in the truth table of the D-latch circuit202, when the clock signal CK is high, the first output signal OUT1is shield, thus the output signal OUT is latched at the previous status, which means that the output signal OUT does not change. It should be noted that the glitch in the first output signal OUT1is related to the clock signal CK. Therefore, as shown in the waveform diagram inFIG.3A, the time when the clock signal CK is high covers the occurrence time of the glitch, so the output signal OUT is latched. In this way, the output signal OUT has no glitch and has a better duty cycle of 50%-50%, which will not cause ADC malfunction or missing code. In another embodiment, the D-latch circuit202may be designed to operate inversely as shown inFIG.3B. For example, when the clock signal CK is low, the first output signal OUT1is shield, thus the output signal OUT is latched at the previous status. That is, the time when the clock signal CK is low covers the occurrence time of the glitch, so the output signal OUT is latched to eliminate the glitch effect.

It should be noted thatFIG.2is an embodiment of the present invention, and those skilled in the art may make appropriate adjustments according to the system requirements. For example, the clock generating circuit may provide a plurality of clock signals with various frequencies. Please refer toFIG.4, which is a schematic diagram of a clock generating circuit2according to an embodiment of the present invention. The clock generating circuit2is derived from the clock generating circuit1, so the elements are represented by the same symbols. The difference between the clock generating circuit2and the clock generating circuit1is that the gray counter10of the clock generating circuit2has more bits, which provides more output signals with varies frequencies.

In detail, the ripple counter circuit12of the clock generating circuit2further includes a third D-flip flop circuit DFF3, and the encoder circuit20of the clock generating circuit2further includes a second XOR circuit XOR2. The third D-flip flop circuit DFF3of the clock generating circuit2includes a fourth clock input terminal CK4, a fourth data input terminal D4, a fourth data output terminal Q4and a fourth inverted data output terminal QB4. The fourth clock input terminal CK4is coupled to the second data output terminal Q2, and configured to receive the second data output signal. The fourth data input terminal D4is coupled to the fourth inverted data output terminal QB4, and the fourth inverted data output terminal Q4is configured to output a third data output signal. On the other hand, the second XOR circuit XOR2receives and encoders the second data output signal and the third data output signal into a second output signal OUT2.

Furthermore, the shielding circuit20of the clock generating circuit2includes a D-latch circuit204to shield the glitch in the second output signal OUT2according to the clock signal CK. The detailed operation of the D-latch circuit204is as described above and will not be repeated here.

In an embodiment, a clock generating circuit3may include a 9-bit gray counter circuit. Please refer toFIGS.5A and5B. FIG.5A andFIG.5Bdepict waveforms of the output signals of the gray counter circuit10and the shielding circuit20of the clock generating circuit3, respectively, according to embodiments of the present invention. As shown inFIG.5A, the output signals OUT1-OUT9of the gray counter circuit10may have glitches, which are particularly noticeable in the output signals OUT1-OUT3with higher frequencies. However, as shown inFIG.5B, the glitches are eliminated after the output signals OUT1-OUT9are latched by the shielding circuit20according to the clock signal CK.

In summary, the clock generating circuit of the present invention utilizes the latch circuit to eliminate the glitches in the output signal of the gray counter, with the clock signal acting as the source for both the gray counter and the latch circuit. By doing so, the output signals of the clock generating circuit have no glitch and exhibit a better duty cycle of 50%-50%, which helps avoid issues such as ADC malfunction or missing code.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.