Patent ID: 12230557

DETAILED DESCRIPTION

Hereinafter, various embodiments of the present inventive concept will be described with reference to the accompanying drawings.

FIG.1is a side cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept, andFIG.2is a bottom view illustrating the semiconductor package illustrated inFIG.1.

Referring toFIGS.1and2, a semiconductor package200according to the present embodiment includes a base substrate210and a semiconductor chip220mounted on the base substrate210.

The base substrate210may include a substrate body211in which a plurality of insulating layers are stacked and an interconnection circuit215having conductive vias and conductive patterns formed on the respective insulating layers. The base substrate210may include a plurality of upper pads212disposed on an upper surface210A of the substrate body211and a plurality of first and second lower pads214A and214B disposed on a lower surface210B of the substrate body211. The interconnection circuit215may electrically connect the plurality of upper pads212to the plurality of first and second lower pads214A and214B.

As used herein, components described as being “electrically connected” are configured such that an electrical signal can be transferred from one component to the other (although such electrical signal may be attenuated in strength as it transferred and may be selectively transferred).

In some embodiments, the substrate body211may include or be formed of a resin-based insulating layer, such as an epoxy resin, a Bakelite resin, a paper epoxy, a glass epoxy, and the like. The interconnection circuit215may be formed of gold (Au), silver (Ag), platinum (Pt), aluminum (Al), copper (Cu), or the like. For example, the base substrate210may include or may be a printed circuit board (PCB). In another embodiment, the base substrate210may be a redistribution substrate having a circuit pattern. The substrate body211may include or be formed of an inorganic insulating layer such as silicon oxide or silicon nitride and/or a photosensitive organic insulating material such as a photoimageable dielectric (PID).

First and second solder resist layers216and217are respectively disposed on the upper surface210A and the lower surface210B of the base substrate210. The first solder resist layer216may have a plurality of openings exposing a region of each of the plurality of upper pads212. Similarly, the second solder resist layer217has a plurality of first and second openings OP1 and OP2 exposing a region of each of the plurality of first and second lower pads214A and214B.

In the present embodiment, the plurality of first and second openings OP1 and OP2 have substantially the same size. Here, the term “substantially” is used to include a difference in size made due to a manufacturing process, etc. For example, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. The regions of the plurality of first and second lower pads214A and214B exposed by the first and second openings OP1 and OP2 having substantially the same size may have substantially the same size as indicated by “do” having the same diameter (seeFIG.2).

The plurality of first and second external connection conductors219A and219B may be disposed in the exposed regions of the plurality of first and second lower pads214A and214B, respectively. The semiconductor package200may be electrically connected to an external system by the plurality of first and second external connection conductors219A and219B. The plurality of first and second external connection conductors219A and219B may have a shape obtainable through a reflow process, for example, a spherical shape or a substantially spherical shape (e.g., an elliptical sphere). The plurality of first and second external connection conductors219A and219B are formed in pad regions having the same diameter “do”, but a size Sb of the second external connection conductors219B may be greater than a size Sa of the first external connection conductor219A (seeFIG.2).

For example, the plurality of first external connection conductors219A may have a first height h1, and the plurality of second external connection conductors219B may have a second height h2 greater than the first height h1. Each of the plurality of second external connection conductors219B has a second volume greater than a first volume of each of the plurality of first external connection conductors219A, but since the plurality of second external connection conductors219B are respectively disposed in exposed regions having the same area as that of each of the first external connection conductors219A, the second height h2 of the plurality of second external connection conductors219B may be greater than the first height h1 of the plurality of first external connection conductors219A.

In the present embodiment, each of the plurality of second external connection conductors219B may be formed to have a relatively large volume and a relatively large height by applying a plurality of solder balls having the same size to the same pad region and then merging the plurality of solder balls through a reflow process (seeFIGS.3to8). Accordingly, the second volume of each of the plurality of second external connection conductors219B may be substantially an integer multiple of the first volume. Since the plurality of second external connection conductors219B are also formed in the same size of exposed pad regions as the first external connection conductors219A, it may be difficult to apply an excessively larger number of the solder balls than those for one first external connection conductor219A. Accordingly, the second volume of each of the plurality of second external connection conductors219B may be double or triple the first volume.

As such, even if warpage occurs in the semiconductor package200, the semiconductor package may be stably mounted on an external device having a flat top surface (e.g., a motherboard) using a height deviation of the plurality of first and second external connection conductors219A and219B.

As illustrated inFIG.2, in the present embodiment, a plurality of second external connection conductors219B (or the second lower pad214B) are disposed in a region adjacent to an edge of the base substrate210, and the plurality of first external connection conductors219A (or the first lower pad214A) may be disposed in an inner region of the lower surface of the base substrate210.

In the present embodiment, the plurality of second external connection conductors219B are arranged to surround an outer periphery of the first external connection conductor219A, but the present inventive concept is not limited thereto and the plurality of second external connection connectors219B may be arranged in various manners depending on the warpage shape of the semiconductor package, according to shapes of warpage of the semiconductor package (seeFIGS.9to12).

In order to adjust a gap deviation caused by warpage, the height h2 of the plurality of second external connection conductors219B may be 10% to 40% greater than the first height h1. In another aspect, the second height h2 of the plurality of second external connection conductors219B may be at least 10 μm greater than the first height h1.

The plurality of first and second external connection conductors219A and219B may each include or be formed of a eutectic metal such as a solder ball. For example, the solder ball may include or be formed of at least one of tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and combinations thereof, and may be formed by a soldering device.

The semiconductor chip220may include, for example, silicon (Si), but is not limited thereto, and the semiconductor chip220may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the semiconductor chip220may have a silicon on insulator (SOI) structure. For example, the semiconductor chip220may include a buried oxide layer (BOX). The semiconductor chip220may include a conductive region, for example, a well doped with an impurity or a structure doped with an impurity. For example, the semiconductor chip220may have various device isolation structures such as a shallow trench isolation (STI) structure.

The semiconductor chip220may include or may be a system LSI, flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, or RRAM. For example, the semiconductor chip220may include a plurality of various types of individual devices. The plurality of various types of individual devices may include or may be various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor transistor (CMOS), a system large scale integration (LSI), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active device, a passive device, and the like. The plurality of various types of individual devices may be electrically connected to the conductive region. The semiconductor package200may include at least two of the plurality of individual devices and/or a conductive wiring and/or a conductive plug electrically connecting the plurality of individual devices to the conductive region. Also, each of the plurality of individual devices may be electrically isolated/insulated from other adjacent individual devices by insulating layers.

The semiconductor chip220may include a plurality of interconnection structures for connecting the plurality of individual devices to other interconnections. The plurality of interconnection structures may include a metal interconnection layer and a via plug. The metal interconnection layer and the via plug may include a barrier layer for interconnection and a metal layer for interconnection. The barrier layer for interconnection may include or be formed of at least one material selected from Ti, TiN, Ta, and TaN. The metal layer for interconnection may include or be formed of at least one metal selected from W, Al, and Cu.

The semiconductor chip220may be electrically connected to the upper pad212of the base substrate210by a bonding wire240. The semiconductor chip220may be mounted on the first solder resist layer216using a die attach film230.

A mold portion290may be formed on the upper surface201A of the base substrate210, e.g., on the first solder resist layer216. The mold portion290may be formed on the upper surface210A of the base substrate210, e.g., on the first solder resist layer216, to surround the semiconductor chip220and the bonding wire240. The mold portion290may be formed of resin. The mold portion290may include or be formed of, for example, epoxy mold compound (EMC).

FIGS.3to8are cross-sectional views illustrating respective steps of process of forming external connection conductors219A and219B of the semiconductor package illustrated inFIG.1. The cross-sectional views may be understood as a region corresponding to a portion A ofFIG.1.

Referring toFIG.3, a partial region of the base substrate210, e.g., a lower surface in which the first and second lower pads214A and214B are arranged is illustrated.

An interconnection circuit (not shown, see215ofFIG.1) including a conductive pattern and a conductive via may be included in the base substrate210. The interconnection circuit215may include an upper surface pad212and first and second lower surface pads214A and214B.

Next, referring toFIG.4, a second solder resist layer217in which first and second openings OP1 and OP2 are formed may be formed.

The second solder resist layer217may be formed by applying, for example, a photoimageable solder resist material on the entire lower surface of the base substrate210by a screen-printing method or a spray coating method, or by bonding a film type solder resist material by a laminating method.

The first and second openings OP1 and OP2 may be formed to have the same size “do”. The second solder resist layer217formed on the lower surface of the base substrate210may be formed by removing portions corresponding to the first and second openings OP1 and OP2 by exposure and development and curing the portions with heat, UV or IR. The opening forming process is not limited thereto, and other processes such as laser processing may be used.

Next, referring toFIG.5, a flux layer FXe may be applied to a solder resist region adjacent to the second opening OP2 together with the pad region exposed by the first and second openings OP1 and OP2 using a flux supply device600.

The flux layer is applied to a region in which a solder ball is to be disposed using the flux supply device600. In the present embodiment, first and second flux layers FX1 and FX2 are formed in the pad regions exposed by the first and second openings OP1 and OP2, and an extension flux layer FXe is additionally applied to a solder resist region adjacent to the second opening OP2. The extension flux layer FXe may be a region extending from the second flux layer FX2, but is not limited thereto, and the second flux layer FX2 and the extension flux layer FXe may be disposed to be spaced apart from each other within a range in which solder balls to be disposed in a subsequent process may be merged. Such flux improves spreadability and wettability of the solder, and the flux may be pre-applied to the region to be soldered or included in a non-conductive film (e.g., in the second solder resist layer217). By forming the expansion flux layer FXe, solder balls may be stably disposed in the solder resist region adjacent to the second opening OP2. For example, the flux may be classified as a resin-based, organic-based, and inorganic-based flux, and the flux used in an electronic device may be a resin-based flux.

According to the present embodiment, in order to form an external connection conductor having a different size or height, flux may be applied to desired regions as shown inFIG.5through a simple modification of installing a new inlet610bin addition to an existing inlet610ain the flux supply device600, without having to change the design of the first and second pads214A and214B and/or the first and second openings OP1 and OP2. However, the present inventive concept is not limited thereto, and, in some embodiments, after the first and second flux layers FX1 and FX2 are applied to the pad regions of the first and second openings OP1 and OP2, the extension flux layer FXe may be additionally formed in the solder resist region adjacent to the second opening OP2 by moving the inlet of some fluxes.

Next, referring toFIG.6, first to third solder balls SB1, SB2, and SB3 may be applied to the first and second flux layers FX1 and FX2 and the extension flux layer FXe, respectively.

The first to third solder balls SB1, SB2, and SB3 having the same size d may be disposed on the flux layers FX1, FX2, and FXe described above with reference toFIG.5. The first and second solder balls SB1 and SB2 may be disposed on the first and second flux layers FX1 and FX2 positioned in the first and second openings OP1 and OP2, respectively, and the third solder ball SB3 may also be disposed on the solder resist region adjacent to the second solder ball SB2 with the flux layer FXe. As described above, the first and second solder balls SB1 and SB2 may be respectively disposed in the regions exposed by the first and second openings OP1 and OP2, and the third solder ball SB3 may be disposed in a region adjacent to the second opening OP2.

While the third solder ball SB3 is disposed adjacent to the second solder ball SB2, a sufficient distance to the first solder ball SB1 may be secured so as not to be merged with the first solder ball SB1 in the reflow process. Accordingly, the first and second lower pads214A and214B may be arranged at a pitch of three or more times the diameter d of each solder ball. In view of a final structure, the diameter d of each solder ball is similar to or the same as a width of the first external connection conductor219A formed of one solder ball, so a pitch of the first and second lower pads214A and214B may be defined as more than three times the width of the first external connection conductor219A.

Next, the first to third solder balls SB1, SB2, and SB3 may be melted using a reflow device to form the first and second external connection conductors219A and219B having desired shapes. For example, the reflow device may melt the first to third solder balls SB1, SB2, and SB3 by heating the solder balls SB1, SB2 and SB3 in a heating chamber, while conveying the base substrate210by a conveyor or the like.

First, referring toFIG.7, the first to third solder balls are melted through the reflow device, and the molten solder balls SB1, SB2, and SB3 may be in close contact with the pad regions and the spherical connection conductors219A′ and219B′ may be deformed by surface tension. In this process, adjacent second and third solder balls SB2 and SB3 may be merged. The merged second and third solder balls SB2 and SB3 may form the second external connection conductor219B in a region exposed to the second opening OP2 as illustrated inFIG.8.

As such, since the second external connection conductor219B is formed by the two solder balls SB2 and SB3, the second external connection conductor219B may have twice the volume of the first external connection conductor219A. In addition, since the second external connection conductor219B has twice the volume and is formed in the pad region having the same area as the first external connection conductor219A, the second external connection conductor219B may be formed to have a height greater than the height of the first external connection conductor219A. Although there are some differences depending on the shapes of the first and second external connection conductors219A and219B, a height h2 of the second external connection conductor219B may be about 10% to 40% greater than a first height h1. In another aspect, a deviation of a substrate level due to a curvature of the warpage may be compensated for using a deviation D of the first and second heights. As for the deviation D, the second height h2 of the second external connection conductor219B may be at least 10 μm greater than the first height h1. For example, a difference between a highest level and a lowest level of the lower surface210B of the base substrate210may be 20 μm or more.

As used herein, a “level” may be a vertical distance from a horizontal reference plane. Spatially relative terms, such as “level,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe positional relationships. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures.

The external connection conductor for gap adjustment (i.e., the second external connection conductor) having a height greater than that of other external connection conductors may be easily applied to semiconductor packages having various structures. In addition, since the external connection conductor for gap adjustment may be easily arranged in a desired region of the substrate, a deviation of the substrate level (e.g., a gap between the semiconductor package and the substrate) due to various types of warpage may be effectively compensated. These various embodiments will be described with reference toFIGS.9to13.

FIGS.9and10are side cross-sectional views of semiconductor packages according to various embodiments of the present inventive concept, respectively.

Referring toFIG.9, a semiconductor package300A according to the present embodiment includes a base substrate310, an interposer110mounted on the base substrate310, and first and second semiconductor chips120A and120B mounted on the interposer110.

Similar to the base substrate210illustrated inFIG.1, the base substrate310may include a plurality of upper pads312, a plurality of first and second lower pads314A and314B, and an interconnection circuit (not shown), and an interconnection circuit may electrically connect the plurality of upper pads312and the plurality of first and second lower pads314A and314B. For example, the base substrate310may include or may be a printed circuit board (PCB).

The interposer110may be disposed on an upper surface of the base substrate310and may include a plurality of lower connection pads114respectively and electrically connected to the plurality of upper pads312and a plurality of upper connection pads112electrically connected the plurality of lower connection pads114. The interposer110may include a substrate having a redistribution layer, and the substrate may be formed of, for example, a semiconductor substrate (e.g., a silicon substrate), an inorganic insulating layer, or a photosensitive organic insulating layer such as PID.

The first and second semiconductor chips120A and120B may be disposed on an upper surface of the interposer and may be electrically connected to a plurality of upper connection pads112, respectively. In some embodiments, the first semiconductor chip120A may include or may be a logic chip. For example, the first semiconductor chip120A may include or may be a controller or a microprocessor including a logic device. In some embodiments, the second semiconductor chip120B may include or may be a memory chip such as a DRAM, an SRAM, a flash, a PRAM, a ReRAM, a FeRAM, or an MRAM (FeRAM). For example, the second semiconductor chip120B may be a high-band memory (HBD) chip including a memory stack electrically connected through a TSV structure.

The first and second semiconductor chips120A and120B may each have an active surface facing the first surface of the interposer110and an inactive surface (i.e., upper surface) positioned opposite to the active surface. The first and second semiconductor chips120A and120B may include a plurality of connection electrodes125A and125B respectively disposed on the active surfaces. The connection electrodes125A and125B of the first and second semiconductor chips120A and120B may be electrically connected to the first upper connection pads112of the interposer110by connection bumps116.

An underfill180may be disposed between an upper surface of the interposer substrate110and the first and second semiconductor chips120A and120B. The underfill180may fill a space between the plurality of bumps116. The underfill180may protect the plurality of upper pads112, the plurality of connection bumps116, and active surfaces of the first and second semiconductor chips120A and120B from the outside. For example, the underfill180may include or be formed of an insulating polymer material such as an epoxy resin.

The molding portion190may be disposed on the upper surface of the interposer110and have a structure surrounding the first and second semiconductor chips120A and120B. The molding portion190may include or be formed of an insulating polymer material similar to the underfill180. For example, the molding portion190may be formed of an epoxy resin or EMC. The upper surfaces of the first and second semiconductor chips120A and120B may be exposed from an upper surface of the molding portion190and may form a flat coplanar surface with each other.

The base substrate310employed in the present embodiment may improve warpage of the semiconductor package300A using a height deviation of the plurality of first and second external connection conductors319A and319B.

The base substrate310illustrated inFIG.9may be deformed such that a center thereof has a lower level than an edge region of the base substrate310and a region adjacent to an edge has a higher level than the center of the base substrate310. Due to the warpage, the base substrate310has a level deviation D1, and in order to compensate for this deviation, an external connection conductor (i.e., a second external connection conductor319B) having a relatively large height is disposed in a region adjacent to the edge.

For example, a solder resist layer317is disposed on a lower surface of the base substrate310, and a plurality of first and second openings OP1 and OP2 respectively opening the plurality of first and second lower pads314A and314B are formed in the solder resist layer317. The plurality of first and second openings OP1 and OP2 have substantially the same size. Exposed regions of the plurality of first and second lower pads314A and314B by the first and second openings OP1 and OP2 having substantially the same size may also have substantially the same size. In the present embodiment, the second lower pads314B may be arranged in two rows in a region adjacent to the edge of the lower surface of the base substrate310. For example, the second lower pads314B may be disposed in two rows along the edge of the lower surface of the base substrate310.

The plurality of first and second external connection conductors319A and319B may be disposed on exposed regions of the plurality of first and second lower pads314A and314B, respectively. Even if the plurality of second external connection conductors319B have a second volume larger than the first volume of the plurality of first external connection conductors319A, since the plurality of second external connection conductors319B are respectively disposed in the exposed regions having the same area as those of the first external connection conductors319A, a second height h2 of the plurality of second external connection conductors319B may be greater than a first height h1 of the plurality of first external connection conductors319A. In the present embodiment, the second external connection conductors319B may be arranged in two rows319B1and319B2in a region adjacent to the edge of the lower surface of the base substrate310. For example, the height h2 of the second external connection conductors319B may be 10% to 40% greater than the first height h1 of the first external connection conductors319A.

In this manner, the deviation D1 of the substrate level due to warpage of the semiconductor package300A may be reduced by the deviation D2 of the actual level during mounting using a height deviation (h2−h1) of the plurality of first and second external connection conductors319A and319B. As in the present embodiment, the second external connection conductors319B may be arranged in two or more rows according to the degree of bending.

Referring toFIG.10, the semiconductor package300B according to the present embodiment may be understood as being similar to or the same as the semiconductor package300A illustrated inFIG.9, except that a bent direction of the base substrate310thereof is the opposite to that of the base substrate310of the semiconductor package300A and an arrangement of the first and second external connection conductors319A and319B is different. The description of the components of the present embodiment may refer to the description of the same or similar components of the semiconductor package300A illustrated inFIG.9unless otherwise specified.

The base substrate310illustrated inFIG.10is deformed such that a region adjacent to the edge has a lower level than a central region and a central region has a higher level than an edge of the base substrate310. Due to the warpage, a deviation D1′ occurs in the level of the base substrate310, and in order to compensate for the deviation D1′ of the substrate level, an external connection conductor (i.e., a second external connection conductor319B) having a relatively large height is disposed in the central region.

For example, by arranging the second external connection conductor319B having a relatively large height in the center and on both sides of the center and forming the first external connection conductor319A having a relatively low height in the remaining region, deviation D1′ of the substrate level may be reduced. For example, the deviation D1′ of the substrate level may be reduced to a deviation D2′, e.g., in view of bottom levels of the external connection conductors319, during mounting of the semiconductor package300B using a height deviation h2−h1 of the plurality of first and second external connection conductors319A and319B.

FIGS.11and12are side cross-sectional views of semiconductor packages according to various embodiments of the present inventive concept, respectively.

Referring toFIG.11, a semiconductor package200A according to the present embodiment may be understood to be similar to or the same as the semiconductor package200illustrated inFIGS.1and2, except that a plurality of semiconductor chips220are stacked on the base substrate210and that three types of external connection conductors219A,219B, and219C having different heights are employed to compensate bending of the base substrate. The description of the components of the present embodiment may refer to the descriptions of the same or similar components of the semiconductor package200illustrated inFIGS.1and2, unless otherwise specified.

The semiconductor package200A according to the present embodiment may include a plurality of stacked semiconductor chips220disposed on the base substrate210. As described above, the semiconductor package200A according to the present embodiment may employ various types of semiconductor chips.

The base substrate210illustrated inFIG.11is deformed such that a center thereof has a lower level than an edge region of the base substrate210and a region adjacent to the edge has a higher level than the center of the base substrate210.

In the present embodiment, three types of external connection conductors219A,219B, and219C having different heights may be employed depending on the bending positons of the base substrate210, and level differences of the substrate may be compensated more precisely than the ones in the previous embodiment. In order to compensate for a level deviation of the base substrate210due to the warpage, a first external connection conductor219A having a first height h1 is disposed in a central region, and a third external connection conductor219C having a third height h3 is disposed in a region closest to the edge. Also, a second external connection conductor219B having a second height h2, an intermediate height, may be disposed between the first external connection conductor219A and the third external connection conductor219B. For example, the third height h3 may be greater than the second height h2, and the second height h2 may be greater than the first height h1. If necessary, some external connection conductors may be arranged in multiple rows. In the present embodiment, first and second external connection conductors219A and219B may be arranged in a plurality of columns (e.g., two columns).

For example, a solder resist layer217is disposed on a lower surface of the base substrate210, and a plurality of first to third openings OP1, OP2, and OP3 opening respective regions of a plurality of first to third lower pads214A to214C is formed in the solder resist layer217. The plurality of first to third openings OP1, OP2, and OP3 have substantially the same size. The plurality of first to third external connection conductors219A,219B, and219C may be respectively disposed on exposed regions of the plurality of first to third lower pads214A,214B, and214C. As described in the previous process (seeFIGS.5to9), the plurality of first to third external connection conductors219A,219B, and219C may be formed by adjusting the number of solder balls having the same size. For example, the first external connection conductor219A may be formed of one solder ball, the second external connection conductor219B may be formed of two solder balls, and the third external connection conductor219C may be formed of three solder balls to secure respective desired heights.

In this manner, a deviation of the substrate level due to warpage of the semiconductor package200A may be gradually reduced using the height deviations of the plurality of first to third external connection conductors219A,219B, and219C. For example, in the present embodiment, by employing the first to third external connection conductors219A,219B, and219C having different heights, level differences of the substrate may be more precisely compensated than the ones in the previous embodiments.

Referring toFIG.12, a semiconductor package200B according to the present embodiment may be understood as being similar to or the same as the semiconductor package200A illustrated inFIG.11, except that a bending direction of the base substrate210is opposite to bending direction of the base substrate210of the semiconductor package200A and that an arrangement of the first to third external connection conductors219A,219B, and219C is different. The description of the components of the present embodiment may refer to the description of the same or similar components of the semiconductor package200A illustrated inFIG.11unless otherwise specified.

The base substrate210illustrated inFIG.12is deformed such that a region adjacent to the edge has a lower level than a center of the base substrate210and a central region has a higher level than an edge of the base substrate210. In order to compensate for the level deviation of the base substrate210due to the warpage, a third external connection conductor219C having a relatively large third height is disposed in the central region and a first external connection conductor219A having the smallest height h1 is disposed in the region closest to the edge. Also, a second external connection conductor219B having a second height h2, an intermediate height, may be disposed between the first external connection conductor219A and the third external connection conductor219B. For example, the third height h3 may be greater than the second height h2, and the second height h2 may be greater than the first height h1. In the present embodiment, first and second external connection conductors219A and219B may be arranged in a plurality of columns (e.g., two columns). For example, two or more columns of first external connection conductors219A may be arranged along an edge of the base substrate210, and two or more columns of second external connection conductors219B may be arranged between the first external connection conductors219A and the third external connection conductor219C.

As described above, the deviation of the substrate level may be more precisely compensated through the arrangement of the first to third external connection conductors219A,219B, and219C having different heights.

FIG.13is a side cross-sectional view of a POP-type semiconductor package according to an embodiment of the present inventive concept.

Referring toFIG.13, a semiconductor package600according to the present embodiment may include a first semiconductor package400, a second semiconductor package500disposed on the first semiconductor package400, and an interposer450disposed between the first semiconductor package400and the second semiconductor package500and electrically connect the first and second semiconductor packages400and500to each other.

The first semiconductor package400may include a first substrate410, a first semiconductor chip420on the first substrate410, and a first molding portion490disposed on the first substrate to cover a first semiconductor chip420.

The first substrate410may be a substrate for a package. For example, the first substrate410may be a printed circuit board or a ceramic substrate. The first substrate410may be formed of a single layer or multiple layers. The first substrate410may include an upper surface and a lower surface opposing each other. The first substrate410may include a first lower pad414, a first upper pad416, and an interconnection circuit (not shown). A first solder resist layer417including an opening exposing a partial region of the first lower pad414may be disposed on a lower surface of the first substrate410. A first external connection conductor419may be disposed on an exposed region of the first lower pad414. For example, a plurality of first external connection conductors419may be disposed on exposed regions of a plurality of first lower pads414respectively. The first external connection conductor419may electrically connect the first semiconductor package400to an external device.

The first semiconductor chip420may be mounted on the first substrate410. In some embodiments, the first semiconductor chip420may be a non-memory semiconductor chip such as a logic semiconductor chip. For example, the first semiconductor chip420may be an application processor (AP). For convenience of description, it is illustrated that only a single semiconductor chip is formed on the first substrate410, but the technical spirit of the present inventive concept is not limited thereto. For example, a plurality of semiconductor chips may be formed/mounted side by side on the first substrate410, or a plurality of semiconductor chips may be sequentially stacked on the first substrate410(seeFIGS.11and12).

In the present embodiment, the first semiconductor chip420may be mounted on the first substrate410by a flip chip bonding method. For example, a first bump416may be interposed between the first substrate410and the first semiconductor chip420to electrically connect the first substrate410and the first semiconductor chip420to each other.

The interposer450may include an upper surface and a lower surface facing/opposite each other. The interposer450may reduce warpage of the semiconductor package600together with easy electrical connection between the first semiconductor package400and the second semiconductor package500.

The interposer450may include a lower connection pad454and an upper connection pad452. For example, the lower connection pad454may be disposed on a lower surface of the interposer450, and the upper connection pad452may be disposed on an upper surface of the interposer450. The lower connection pad454and the upper connection pad452may be electrically connected by an electrical interconnection circuit formed in the interposer450, for example, an interconnection pattern and vias. A portion of the upper connection pad452may be exposed by an opening of the solder resist layer456.

In some embodiments, the interposer450may be electrically connected to the first substrate410by a vertical connection member430. The vertical connection member430may be disposed between the first substrate410and the interposer450to electrically connect the first substrate410and the interposer450to each other. In some embodiments, a plurality of vertical connection members430may be formed to surround the first semiconductor chip420. For example, the vertical connection member430may include or be formed of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but is not limited thereto.

Although the interposer450is illustrated to be spaced apart from the first semiconductor chip420, the technical spirit of the present inventive concept is not limited thereto. For example, depending on a size of the vertical connection member430, the interposer450may contact the first semiconductor chip420.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

The second semiconductor package500may include a second substrate510disposed on the interposer450, a second semiconductor chip520on the second substrate510, and a second molding portion590disposed on the second substrate510and surrounding the second semiconductor chip520.

The second substrate510may be a substrate for a package. For example, the second substrate510may be a printed circuit board (PCB) or a ceramic substrate. The second substrate510may be formed of a single layer or multiple layers. The second substrate510may include an upper surface and a lower surface facing/opposite each other.

A plurality of second lower pads514and a plurality of second upper pads512may be disposed on a lower surface and an upper surface of the second substrate510, respectively. The plurality of second lower pads514and the plurality of second upper pads512may be electrically connected by an electrical interconnection circuit in the second substrate510, for example, an interconnection pattern and a conductive via. The second semiconductor chip520may be mounted on the second substrate510. In some embodiments, the second semiconductor chip520may be a memory semiconductor chip.

For convenience of description, it is illustrated that only a single semiconductor chip is formed on the second substrate520, but the technical spirit of the present inventive concept is not limited thereto. For example, a plurality of semiconductor chips may be formed/mounted side by side on the second substrate510, or a plurality of semiconductor chips may be sequentially stacked on the second substrate510(seeFIGS.11and12).

The second semiconductor chip520may be mounted on the second substrate510by a plurality of second bumps526. The plurality of second bumps526may be disposed between the second substrate510and the second semiconductor chip520to electrically connect the second substrate510and the second semiconductor chip520to each other.

The second semiconductor package500may include a second solder resist layer517disposed on a lower surface of the second substrate510and having a plurality of openings OP exposing partial regions of the plurality of second lower pads514. The plurality of openings OP may have the same size, and exposed regions of the plurality of second lower pads514may also have substantially the same size. A plurality of second external connection conductors519may be respectively disposed on the exposed regions of the plurality of second lower pads514. The plurality of second external connection conductors519includes external connection conductors519S for gap adjustment having a volume and a height greater than those of the other external connection conductors519. The external connection conductors519S for gap adjustment are components/elements corresponding to the second or third external connection conductors219B,219C, and319B described above in the previous embodiment and may be external connection conductors each of which is formed by merging a plurality of solder balls having the same size as the solder balls each of which forms one of the other external connection conductors519in pad regions having the same area. In the present embodiment, the external connection conductors519S for gap adjustment may be disposed adjacent to edge regions of the second substrate510and may be used to compensate for a large gap between the interposer450and the second substrate510in the edge regions of the second substrate510.

According to the embodiments described above, by applying a different number of solder balls having the same size to each pad, some external connection conductors may be formed to have different volumes and different heights. Therefore, it is beneficial to compensate for deviations due to warpage (e.g., a gap between a semiconductor package and a substrate) and significantly improve mounting quality of the package (bonding quality between PKGs in the case of a POP structure).

While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.