Patent ID: 12210368

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The nature and use of the embodiments are discussed in detail as follows. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to embody and use the disclosure, without limiting the scope thereof.

FIG.1Ais a schematic diagram of a bias voltage generating device100in accordance with some embodiments of the present disclosure.FIG.1Adiscloses an exemplary circuit of the bias voltage generating device100. The bias voltage generating device100may include three terminals101,102, and103. The terminal103may be an output voltage terminal to output a bias voltage. The terminal103may be a voltage terminal to provide a bias voltage to drive an electronic device. A supply voltage (e.g., VDD) may be provided at the terminal101. A common voltage (e.g., VSS or GND) may be provided at the terminal102.

The bias voltage generating device100may include transistor pairs110and120. The transistor pairs110and120may be or include diode connected transistor pairs. The transistor pair110may include a p-type transistor111and a n-type transistor112. In some embodiments, each of the p-type transistor111and the n-type transistor112may be a diode-connected transistor. For example, the p-type transistor111may be a p-type MOSFET, and the drain and the gate of the p-type transistor111may be connected to each other. For example, the n-type transistor112may be a n-type MOSFET, and the drain and the gate of the n-type transistor112may be connected to each other. In the transistor pair110, the drain and the gate of the p-type transistor111is connected to the drain and the gate of the n-type transistor112.

The transistor pair120may include a p-type transistor121and a n-type transistor122. Each of the p-type transistor121and the n-type transistor122may be a diode-connected transistor. For example, the p-type transistor121may be a p-type MOSFET, and the drain and the gate of the p-type transistor121may be connected to each other. For example, the n-type transistor122may be a n-type MOSFET, and the drain and the gate of the n-type transistor122may be connected to each other. In the transistor pair120, the drain and the gate of the p-type transistor121is connected to the drain and the gate of the n-type transistor122.

The transistor pairs110and120are connected to each other. For example, the source of the n-type transistor112may be connected to the source of the p-type transistor121.

The bias voltage generating device100may include impedance elements191and192. In some embodiments, the impedance elements191and192may include resistors, transistors, diodes, or any other elements that can provide impedance for the bias voltage generating device100. The impedance element191may be connected between the terminal101and the transistor pair110. The impedance element191may be connected between the terminal101and the p-type transistor111. The impedance element192may be connected to the transistor pair120and the terminal102. The impedance element192may be connected between the n-type transistor122and the terminal102.

The bias voltage generating device100may include a transistor pair130. The transistor pair130may be connected to the terminals101,102, and103. The transistor pair130may include a n-type transistor131and a p-type transistor132. For example, the n-type transistor131may be a n-type MOSFET, and the p-type transistor132may be a p-type MOSFET. The drain of the n-type transistor131may be connected to the terminal101. The drain of the p-type transistor132may be connected to the terminal102. The source of the n-type transistor131may be connected to the source of the p-type transistor132. The source of the n-type transistor131and the source of the p-type transistor132are connected to the terminal103. The gate of the n-type transistor131may be connected to the transistor pair110. The gate of the n-type transistor131may be connected to the gate of the n-type transistor112. The gate of the p-type transistor132may be connected to the transistor pair120. The gate of the p-type transistor132may be connected to the gate of the p-type transistor121.

In some embodiments, the transistor pairs110and120and impedance elements191and192may function as a reference bias section140for the bias voltage generating device100. In some embodiments, the transistor pair130may function as a driving section150(or an output stage) of the bias voltage generating device100.

In some embodiments, VDD is provided at the terminal101, and GND is provided at the terminal102. The output voltage at the terminal103may be expressed as

VO=12⁢VDD+12[(VTP⁢1+VTN⁢1)-(VTP⁢2+VTN⁢2)],
where VTP1represents the threshold voltage of the p-type transistor111, VTN1represents the threshold voltage of the n-type transistor112, VTP2represents the threshold voltage of the p-type transistor121, and VTN2represents the threshold voltage of the n-type transistor122. A threshold voltage of a transistor (e.g., VTP1, VTN1, VTP2, and VTN2) may be temperature dependent, which would adversely affect the accuracy of the output voltage at the terminal103. When the p-type transistors111,121and the n-type transistors112,122are selected so that VTP1+VTN1is equal to VTP2+VTN2, the output voltage at the terminal103may be expressed as

VO=12⁢V⁢DD
Since the variation of the threshold voltage of the transistors (e.g., the p-type transistors111,121and the n-type transistors112,122) is eliminated or mitigated, the output voltage of the bias voltage generating device100would be more accurate and stable.

In some embodiments, a ratio of the current flowing through the reference bias section140to that flowing through the driving section150may be 1:1. In some embodiments, the ratio of the current flowing through the reference bias section140to that flowing through the driving section150may be 1:X depending on an aspect ratio of the n-type transistor112to the n-type transistor131(and the p-type transistor121to the p-type transistor132).

FIG.1Bis a schematic diagram of a bias voltage generating device100A in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, resistors191A and192A are used in the bias voltage generating device100A. The bias voltage generating device100A may include the resistors191A and192A. The resistor191A may be connected between the terminal101and the transistor pair110. The resistor191A may be connected between the terminal101and the transistor pair110. The resistor192A may be connected between the transistor pair120and the terminal102. The resistor192A may be connected between the transistor pair120and the terminal102.

FIG.1Cis a schematic diagram of a bias voltage generating device100B in accordance with some embodiments of the present disclosure. Compared with the device100inFIG.1A, long channel MOS diodes191B and192B are used in the bias voltage generating device100B. The bias voltage generating device100B may include the long channel MOS diodes191B and192B. The long channel MOS diodes191B and192B may include two or more p-type MOSFETs, for example two or more diode-connected p-type MOSFETs. The long channel MOS diode191B may be connected between the terminal101and the transistor pair110. The long channel MOS diode191B may be connected between the terminal101and the diode-connected transistor pair110. The long channel MOS diode192B may be connected between the transistor pair120and the terminal102. The long channel MOS diode192B may be connected between the transistor pair120and the terminal102.

FIG.1Dis a schematic diagram of a bias voltage generating device100C in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, long channel MOS diodes191C and192C are used in the bias voltage generating device100C. The bias voltage generating device100C may include the long channel MOS diodes191C and192C. The long channel MOS diodes191C and192C may include two or more n-type MOSFETs, for example two or more diode-connected n-type MOSFETs. The long channel MOS diode191C may be connected between the terminal101and the transistor pair110. The long channel MOS diode191C may be connected between the terminal101and the transistor pair110. The long channel MOS diode192C may be connected between the transistor pair120and the terminal102. The long channel MOS diode192C may be connected between the transistor pair120and the terminal102. Compared with the long channel MOS diode made of p-type MOSFETs, because n-type MOSFETs have good mobility, the long channel MOS diode made of n-type MOSFETs may use more n-type MOSFETs to achieve the same effect.

FIG.1Eis a schematic diagram of a bias voltage generating device100D in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, the impedance elements191D and192D may comprise a resistor and a long channel MOS diode. InFIG.1E, the long channel MOS diode of the impedance elements191D and192D may made of p-type MOSFETs. The long channel MOS diode of the impedance elements191D and192D may comprise n-type MOSFETs. The sequence of the resistor and the long channel MOS diode in the impedance elements191D or192D may be reversed.

InFIG.1E, the bias voltage generating device100D may include the impedance elements191D and192D. The impedance elements191D and192D may include two or more n-type MOSFETs, for example two or more diode-connected n-type MOSFETs. The impedance element191D may be connected between the terminal101and the transistor pair110. The impedance element191D may be connected between the terminal101and the transistor pair110. The impedance element192D may be connected between the transistor pair120and the terminal102. The impedance element192D may be connected between the transistor pair120and the terminal102. The impedance elements191D and192D including a resistor and a long channel MOS diode may prevent low threshold voltage of the transistors of the long channel MOS diode due to low temperature.

When VDD provided at the terminal101of the bias voltage generating device100is 1.8V and the GND is provided at the terminal102of the bias voltage generating device100, the output voltage at the terminal103may be 0.9V. In simulation, the output voltage at the terminal103may be from 0.896V to 0.9V. In some simulations, the output voltage at the terminal103may be 0.896V, 0.897V, 0.898V, or 0.899V. The error rate (e.g., variation) of the output voltage at the terminal103of the bias voltage generating device100may be from 0 to 0.4%. In some simulations, the error rate (e.g., variation) of the output voltage at the terminal103of the bias voltage generating device100may be 0.1%, 0.2%, 0.3%, or 0.4%.

For conventional devices for generating bias voltage of ½VDD, when VDD is 1.8V, the output voltage may be from 0.878V to 0.902V. In some simulations, the output voltage of the conventional devices may be 0.879V, 0.88V, 0.886V, 0.888V, 0.89V, 0.893V, 0.9V, or 0.902V. The error rate (e.g., variation) of the output voltage of the conventional devices may be from 0 to 2.3%. In some simulations, the error rate (e.g., variation) of the output voltage at the terminal103of the device100may be 0.1%, 0.2%, 0.8%, 1%, 1.3%, 1.5%, or 2.3%.

FIG.2is a schematic diagram of a bias voltage generating device200in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, the bias voltage generating device200may further include a sense section210and a gain section230. Compared with the device100inFIG.1A, the device200may further include a push-pull stage and a feedback mechanism.

InFIG.2, the bias voltage generating device200may include p-type transistors211,212,216, and232(e.g., p-type MOSFETs) and n-type transistors213,214,215, and231(e.g., n-type MOSFETs). The sense section210may include the p-type transistors211,212, and216(e.g., p-type MOSFETs) and the n-type transistors213,214, and215(e.g., n-type MOSFETs). The gain section230may include the p-type transistor232(e.g., a p-type MOSFET) and the n-type transistor231(e.g., a n-type MOSFET).

InFIG.2, the p-type transistor211may be a diode-connected transistor. The gate and the drain of the p-type transistor211may be connected to each other. The p-type transistor211may be connected between the terminal101, the p-type transistor212, and the n-type transistor215. The source of the p-type transistor211may be connected to the terminal101. The drain of the p-type transistor211may be connected to the drain of the n-type transistor215. The gate of the p-type transistor211may be connected to the gate of the p-type transistor212.

InFIG.2, the p-type transistor212may be connected between the terminal101, the p-type transistor212, and the n-type transistor231. The source of the p-type transistor212may be connected to the terminal101. The drain of the p-type transistor212may be connected to the drain of the n-type transistor231. The gate of the p-type transistor212may be connected to the gate of the p-type transistor211. The p-type transistors211and212may form a current mirror.

InFIG.2, the n-type transistor215may be connected between the p-type transistor211, the transistor pair110, the terminal103, and the p-type transistor216. The drain of the n-type transistor215may be connected to the drain of the p-type transistor211. The source of the n-type transistor215may be connected to the terminal103and the source of the p-type transistor216. The gate of the n-type transistor215may be connected to the transistor pair110(e.g., the gate of the n-type transistor112).

InFIG.2, the p-type transistor216may be connected between the n-type transistor215, the transistor pair120, the terminal103, and the n-type transistor213. The source of the p-type transistor216may be connected to the terminal103and the source of the n-type transistor215. The drain of the p-type transistor216may be connected to the drain of the n-type transistor213. The gate of the p-type transistor216may be connected to the transistor pair120(e.g., the gate of the p-type transistor121).

InFIG.2, the n-type transistor213may be a diode-connected transistor. The gate and the drain of the n-type transistor213may be connected to each other. The n-type transistor213may be connected between the p-type transistor216, the n-type transistor214, and the terminal102. The drain of the n-type transistor213may be connected to the drain of the p-type transistor216. The source of the n-type transistor213may be connected to the terminal102. The gate of the n-type transistor213may be connected to the gate of the n-type transistor214.

InFIG.2, the n-type transistor214may be connected between the p-type transistor232, the n-type transistor213, and the terminal102. The drain of the n-type transistor214may be connected to the drain of the p-type transistor232. The source of the n-type transistor214may be connected to the terminal102. The gate of the n-type transistor214may be connected to the gate of the n-type transistor213. The n-type transistors213and214may form a current mirror.

InFIG.2, the n-type transistor231may be a diode-connected transistor. The gate and the drain of the n-type transistor231may be connected to each other. The n-type transistor231may be connected between the p-type transistor212, the p-type transistor232, and the transistor pair130. The drain of the n-type transistor231may be connected to the drain of the p-type transistor212. The source of the n-type transistor231may be connected to the source of the p-type transistor232. The gate of the n-type transistor231may be connected to the transistor pair130(e.g., the gate of the n-type transistor131). The n-type transistors131and231may form a current mirror.

InFIG.2, the p-type transistor232may be a diode-connected transistor. The gate and the drain of the p-type transistor232may be connected to each other. The p-type transistor232may be connected between the n-type transistor231, the n-type transistor214, and the transistor pair130. The source of the p-type transistor232may be connected to the source of the n-type transistor231. The drain of the p-type transistor232may be connected to the drain of the n-type transistor214. The gate of the p-type transistor232may be connected to the transistor pair130(e.g., the gate of the p-type transistor132). The p-type transistors132and232may form a current mirror. The n-type transistor213and the p-type transistor214may be a transistor pair or a gain transistor pair.

In the bias voltage generating device200, when the output voltage at the terminal103increases, a sense current may be generated between the transistors213and216. The sense current may flow from the transistor216to the transistor213. Because of the current mirror formed by the transistors213and214, a current between the transistors214and232may be generated in response to the sense current (i.e., between the transistors213and216). The current between the transistors214and232may flow from the transistor232to transistor214. Because of the transistor232of the gain section230and the transistor132of transistor pair130(which may form a current mirror), current from the transistor132to the terminal102may be generated, which may cause the output voltage at the terminal103to be pulled down.

In the bias voltage generating device200, when the output voltage at the terminal103decreases, a sense current may be generated between the transistors211and215. The sense current may flow from the transistor211to the transistor215. Because of the current mirror formed by transistors211and212, a current between the transistors212and231may be generated in accordance with the sense current (i.e., between the transistors211and215). The current between the transistors212and231may flow from the transistor212to transistor231. Because of the transistor231of the gain section230and the transistor131of transistor pair130(which may form a current mirror), current from the terminal101to the transistor131may be generated, which may cause the output voltage at the terminal103to be pushed up.

Due to the sense section210and the gain section230in the bias voltage generating device200, the output voltage at the terminal103may be more stable, and the error rate (e.g., variation) of the output voltage at the terminal103may be decreased.

FIG.3Ais a schematic diagram of bias voltage generating device300in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, the bias voltage generating device300may further include an impedance element391, a transistor pair310, and a n-type transistor361(e.g., a n-type MOSFET). When VDD is provided at the terminal101and GND is provided at the terminal102, the output voltage of ½VDD is provided at the terminal103of the bias voltage generating device300.

InFIG.3A, the impedance element391may be connected between the terminal101, the impedance element191, and the n-type transistor361.

InFIG.3A, the transistor pair310may be or include a diode connected transistor pair. The transistor pair310may be connected between the impedance element191and the transistor pair110. The transistor pair310may include a p-type transistor311and a n-type transistor312. In some embodiments, each of the p-type transistor311and the n-type transistor312may be a diode-connected transistor. For example, the p-type transistor311may be a p-type MOSFET, and the drain and the gate of the p-type transistor311may be connected to each other. For example, the n-type transistor312may be a n-type MOSFET, and the drain and the gate of the n-type transistor312may be connected to each other. In the transistor pair310, the drain and the gate of the p-type transistor311is connected to the drain and the gate of the n-type transistor312. The source of the p-type transistor311may be connected to the impedance element191. The source of the n-type transistor312may be connected to the transistor pair110(e.g., the source of the p-type transistor111).

InFIG.3A, a reference bias section of the bias voltage generating device300may include the impedance elements191,192, and391, and the transistor pairs110,120, and310.

InFIG.3A, the n-type transistor361may be connected to the terminal101, the impedance elements391and191, and the transistor pair130. The drain of the n-type transistor361may be connected to the terminal101. The source of the n-type transistor361may be connected to the drain of the n-type transistor131. The gate of the n-type transistor361may be connected to the impedance elements391and191. When VDD is provided at the terminal101and GND is provided at the terminal102, the voltage applied to the gate of the n-type transistor361may be ⅔VDD+2Vt, where Vt may represent the threshold voltage of the transistors311and312.

InFIG.3A, a driving section of the bias voltage generating device300may include the n-type transistor361and the transistor pair130.

In bias voltage generating device300, the n-type transistor361may cause a voltage drop between the terminal101and the transistor pair130(e.g., the n-type transistor131). Without the n-type transistor361, the voltage between the gate and the drain of the n-type transistor131may be 1.2V when 1.8V is provided at the terminal101and GND is provided at the terminal102. The n-type transistor361may protect the n-type transistor131from high voltage stress. In some embodiments, the bias voltage generating device300may not have the n-type transistor361.

FIG.3Bis a schematic diagram of a bias voltage generating device300A in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, the bias voltage generating device300A may further include an impedance element391, a transistor pair310, and a n-type transistor361(e.g., a n-type MOSFET). When VDD is provided at the terminal101and GND is provided at the terminal102, the output voltage of ⅓VDD is provided at terminal103of the bias voltage generating device300A.

InFIG.3B, the impedance element391may be connected between the terminal101and transistor pair310.

InFIG.3B, the transistor pair310may be or include a diode connected transistor pair. The transistor pair310may be connected between the impedance elements191and391and connected to the n-type transistor361. The transistor pair310may include a p-type transistor311and a n-type transistor312. In some embodiments, each of the p-type transistor311and the n-type transistor312may be a diode-connected transistor. For example, the p-type transistor311may be a p-type MOSFET, and the drain and the gate of the p-type transistor311may be connected. For example, the n-type transistor312may be a n-type MOSFET, and the drain and the gate of the n-type transistor312may be connected to each other. In the transistor pair310, the drain and the gate of the p-type transistor311is connected to the drain and the gate of the n-type transistor312. The source of the p-type transistor311may be connected to the impedance element391. The source of the n-type transistor312may be connected to the impedance element191and the n-type transistor361.

InFIG.3B, a reference bias section of the bias voltage generating device300may include the impedance elements191,192, and391, and the transistor pairs110,120, and310.

InFIG.3B, the n-type transistor361may be connected between the terminal101, the impedance element191, the transistor pair310, and the transistor pair130. The drain of the n-type transistor361may be connected to the terminal101. The source of the n-type transistor361may be connected to the drain of the n-type transistor131. The gate of the n-type transistor361may be connected to the impedance element191and the transistor pair310(e.g., the source of the n-type transistor312). When VDD is provided at the terminal101and GND is provided at the terminal102, the voltage applied to the gate of the n-type transistor361may be ⅔VDD.

InFIG.3B, a driving section of the bias voltage generating device300may include the n-type transistor361and the transistor pair130.

In bias voltage generating device300A, the n-type transistor361may cause a voltage drop between the terminal101and the transistor pair130(e.g., the n-type transistor131). The n-type transistor361may protect the n-type transistor131from high voltage stress. In some embodiments, the bias voltage generating device300A may not have the n-type transistor361.

FIG.4is a schematic diagram of a bias voltage generating device400in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device300A inFIG.3B, the bias voltage generating device400may further include a sense section410and a gain section230. Compared with the bias voltage generating device300A inFIG.3B, the bias voltage generating device400may include a further push-pull stage. Compared with the bias voltage generating device300A inFIG.3B, the bias voltage generating device400may include a negative feedback function.

InFIG.4, the bias voltage generating device400may include p-type transistors211,212,216,232, and462(e.g., p-type MOSFETs) and n-type transistors213,214,215,231,361, and461(e.g., n-type MOSFETs). The sense section410may include the p-type transistors211,212,216, and462(e.g., p-type MOSFETs) and the n-type transistors213,214,215, and461(e.g., n-type MOSFETs). The gain section230may include the p-type transistor232(e.g., a p-type MOSFET) and the n-type transistor231(e.g., a n-type MOSFET).

InFIG.4, the p-type transistor211may be a diode-connected transistor. The gate and the drain of the p-type transistor211may be connected to each other. The p-type transistor211may be connected between the terminal101, the p-type transistor212, and the n-type transistor461. The source of the p-type transistor211may be connected to the terminal101. The drain of the p-type transistor211may be connected to the drain of the n-type transistor461. The gate of the p-type transistor211may be connected to the gate of the p-type transistor212.

InFIG.4, the p-type transistor212may be connected between the terminal101, the p-type transistor212, and the p-type transistor462. The source of the p-type transistor212may be connected to the terminal101. The drain of the p-type transistor212may be connected to the source of the p-type transistor462. The gate of the p-type transistor212may be connected to the gate of the p-type transistor211. The p-type transistors211and212may form a current mirror.

InFIG.4, the drain of the n-type transistor461may be connected to the drain of the p-type transistor211. The source of the n-type transistor461may be connected to the drain of the n-type transistor215. The gate of the n-type transistor461may be connected to the transistor pair310(e.g., the source of the n-type transistor312), the impedance element191, the gate of the p-type transistor462, and the gate of the n-type transistor361.

InFIG.4, the source of the p-type transistor462may be connected to the drain of the p-type transistor212. The drain of the p-type transistor462may be connected to the drain of the n-type transistor231. The gate of the p-type transistor462may be connected to the transistor pair310(e.g., the source of the n-type transistor312), the impedance element191, the gate of the n-type transistor461, and the gate of the n-type transistor361.

InFIG.4, the n-type transistor215may be connected between the n-type transistor461, the transistor pair110, the terminal103, and the p-type transistor216. The drain of the n-type transistor215may be connected to the source of the n-type transistor461. The source of the n-type transistor215may be connected to the terminal103and the source of the p-type transistor216. The gate of the n-type transistor215may be connected to the transistor pair110(e.g., the gate of the n-type transistor112).

InFIG.4, the p-type transistor216may be connected between the n-type transistor215, the transistor pair120, the terminal103, and the n-type transistor213. The source of the p-type transistor216may be connected to the terminal103and the source of the n-type transistor215. The drain of the p-type transistor216may be connected to the drain of the n-type transistor213. The gate of the p-type transistor216may be connected to the transistor pair120(e.g., the gate of the p-type transistor121).

InFIG.4, the n-type transistor213may be a diode-connected transistor. The gate and the drain of the n-type transistor213may be connected. The n-type transistor213may be connected between the p-type transistor216, the n-type transistor214, and the terminal102. The drain of the n-type transistor213may be connected to the drain of the p-type transistor216. The source of the n-type transistor213may be connected to the terminal102. The gate of the n-type transistor213may be connected to the gate of the n-type transistor214.

InFIG.4, the n-type transistor214may be connected between the p-type transistor232, the n-type transistor213, and the terminal102. The drain of the n-type transistor214may be connected to the drain of the p-type transistor232. The source of the n-type transistor214may be connected to the terminal102. The gate of the n-type transistor214may be connected to the gate of the n-type transistor213. The n-type transistors213and214may form a current mirror.

InFIG.4, the n-type transistor231may be a diode-connected transistor. The gate and the drain of the n-type transistor231may be connected. The n-type transistor231may be connected between the p-type transistor462, the p-type transistor232, and the transistor pair130. The drain of the n-type transistor231may be connected to the drain of the p-type transistor462. The source of the n-type transistor231may be connected to the source of the p-type transistor232. The gate of the n-type transistor232may be connected to the transistor pair130(e.g., the gate of the n-type transistor131). The n-type transistors131and231may form a current mirror.

InFIG.4, the p-type transistor232may be a diode-connected transistor. The gate and the drain of the p-type transistor232may be connected. The p-type transistor232may be connected between the n-type transistor231, the n-type transistor214, and the transistor pair130. The source of the p-type transistor232may be connected to the source of the n-type transistor231. The drain of the p-type transistor232may be connected to the drain of the n-type transistor214. The gate of the p-type transistor232may be connected to the transistor pair130(e.g., the gate of the p-type transistor132). The p-type transistors132and232may form a current mirror. The n-type transistor213and the p-type transistor214may be a transistor pair or a gain transistor pair.

In bias voltage generating device400, the n-type transistor361may cause a voltage drop between the terminal101and the transistor pair130(e.g., the n-type transistor131). The n-type transistor361may protect the n-type transistor131from high voltage stress. In some embodiments, the bias voltage generating device400may not have the n-type transistor361.

The n-type transistor461may cause a voltage drop between the transistors211and215. The n-type transistor461may protect the n-type transistor215from high voltage stress. In some embodiments, the bias voltage generating device400may not have the n-type transistor461.

The p-type transistor462may cause a voltage drop between the transistors212and231. The p-type transistor462may protect the p-type transistor212from high voltage stress. In some embodiments, the bias voltage generating device400may not have the p-type transistor462.

When VDD is provided at the terminal101and GND is provided at the terminal102, the voltage applied to the gate of the transistor361, the gate of the transistor461, and the gate of the transistor462may be

23⁢V⁢DD

Because of the sense section410and the gain section230in the bias voltage generating device400, the output voltage at the terminal103may be more stable, and the error rate (e.g., variation) of the output voltage at the terminal103may be decreased.

FIG.5Ais a schematic diagram of a bias voltage generating bias voltage generating device500in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, the bias voltage generating device500may further include an impedance element591, a transistor pair510, and a p-type transistor561(e.g., a p-type MOSFET). When VDD is provided at the terminal101and GND is provided at the terminal102, the output voltage of

23⁢V⁢DD
is provided at terminal103of the bias voltage generating device300.

InFIG.5A, the impedance element591may be connected between the terminal102, the impedance element192, and the p-type transistor561.

InFIG.5A, the transistor pair510may be or include a diode connected transistor pair. The transistor pair510may be connected between the impedance element192and the transistor pair120. The transistor pair510may include a p-type transistor511and a n-type transistor512. In some embodiments, each of the p-type transistor511and the n-type transistor512may be a diode-connected transistor. For example, the p-type transistor511may be a p-type MOSFET, and the drain and the gate of the p-type transistor511may be connected to each other. For example, the n-type transistor512may be a n-type MOSFET, and the drain and the gate of the n-type transistor512may be connected to each other. In the transistor pair510, the drain and the gate of the p-type transistor511is connected to the drain and the gate of the n-type transistor512. The source of the p-type transistor511may be connected to the transistor pair120(e.g., the source of the n-type transistor122). The source of the n-type transistor512may be connected to the impedance element192.

InFIG.5A, a reference bias section of the bias voltage generating device500may include the impedance elements191,192, and591, and the transistor pairs110,120, and510.

InFIG.5A, the p-type transistor561may be connected between the terminal102, the impedance elements591and191, and the transistor pair130. The drain of the p-type transistor561may be connected to the terminal102. The source of the p-type transistor561may be connected to the drain of the p-type transistor132. The gate of the p-type transistor561may be connected to the impedance elements591and191. When VDD is provided at the terminal101and GND is provided at the terminal102, the voltage applied to the gate of the p-type transistor561may be

13⁢V⁢DD-2⁢V⁢t
where Vt represents the threshold voltage of the transistors511and512.

InFIG.5A, a driving section of the bias voltage generating device500may include the p-type transistor561and the transistor pair130.

In bias voltage generating device500, the p-type transistor561may cause a voltage drop between terminal102and the transistor pair130(e.g., the p-type transistor132). The p-type transistor561may protect the p-type transistor132from high voltage stress. In some embodiments, the bias voltage generating device500may not have the p-type transistor561.

FIG.5Bis a schematic diagram of a bias voltage generating device500A in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, the bias voltage generating device500A may further include an impedance element591, a transistor pair510, and a p-type transistor561(e.g., a p-type MOSFET). When VDD is provided at the terminal101and GND is provided at the terminal102, the output voltage of

23⁢V⁢DD
is provided at terminal103of the bias voltage generating device500A.

InFIG.5B, the impedance element591may be connected between the terminal102and the transistor pair510.

InFIG.5B, the transistor pair510may be or include a diode connected transistor pair. The transistor pair510may be connected between the impedance elements191and591and the p-type transistor561. The transistor pair510may include a p-type transistor511and a n-type transistor512. In some embodiments, each of the p-type transistor511and the n-type transistor512may be a diode-connected transistor. For example, the p-type transistor511may be a p-type MOSFET, and the drain and the gate of the p-type transistor511may be connected to each other. For example, the n-type transistor512may be a n-type MOSFET, and the drain and the gate of the n-type transistor512may be connected to each other. In the transistor pair510, the drain and the gate of the p-type transistor511is connected to the drain and the gate of the n-type transistor512. The source of the p-type transistor511may be connected to the impedance element192and the p-type transistor561. The source of the n-type transistor512may be connected to the impedance element591.

InFIG.5B, a reference bias section of the bias voltage generating device500A may include the impedance elements191,192, and591, and the transistor pairs110,120, and510.

InFIG.5B, the p-type transistor561may be connected between the terminal102, the impedance element192, the transistor pair510, and the transistor pair130. The drain of the p-type transistor561may be connected to the terminal102. The source of the p-type transistor561may be connected to the drain of the p-type transistor132. The gate of the p-type transistor561may be connected to the impedance element192and the transistor pair510(e.g., the source of the p-type transistor512). When VDD is provided at the terminal101and GND is provided at the terminal102, the voltage applied to the gate of the p-type transistor561may be

13⁢V⁢DD

InFIG.5B, a driving section of the bias voltage generating device500A may include the p-type transistor561and the transistor pair130.

In bias voltage generating device500A, the p-type transistor561may cause a voltage drop between the terminal102and the transistor pair130(e.g., the p-type transistor132). The p-type transistor561may protect the p-type transistor132from high voltage stress. In some embodiments, the bias voltage generating device500A may not have the p-type transistor561.

FIG.6is a schematic diagram of a bias voltage generating device600in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device500A inFIG.5B, the bias voltage generating device600may further include a sense section610and a gain section230. Compared with the bias voltage generating device500A inFIG.5B, the bias voltage generating device600may include a further push-pull stage. Compared with the bias voltage generating device500A inFIG.5B, the bias voltage generating device600may include a negative feedback function.

InFIG.6, the bias voltage generating device600may include p-type transistors211,212,216,232,561, and661(e.g., p-type MOSFETs) and n-type transistors213,214,215,231, and662(e.g., n-type MOSFETs). The sense section610may include the p-type transistors211,212,216, and661(e.g., p-type MOSFETs) and the n-type transistors213,214,215, and662(e.g., n-type MOSFETs). The gain section230may include the p-type transistor232(e.g., a p-type MOSFET) and the n-type transistor231(e.g., a n-type MOSFET).

InFIG.6, the p-type transistor211may be a diode-connected transistor. The gate and the drain of the p-type transistor211may be connected. The p-type transistor211may be connected between the terminal101, the p-type transistor212, and the n-type transistor215. The source of the p-type transistor211may be connected to the terminal101. The drain of the p-type transistor211may be connected to the drain of the n-type transistor215. The gate of the p-type transistor211may be connected to the gate of the p-type transistor212.

InFIG.6, the p-type transistor212may be connected between the terminal101, the p-type transistor212, and the n-type transistor231. The source of the p-type transistor212may be connected to the terminal101. The drain of the p-type transistor212may be connected to the drain of the n-type transistor231. The gate of the p-type transistor212may be connected to the gate of the p-type transistor211. The p-type transistors211and212may form a current mirror.

InFIG.6, the n-type transistor215may be connected between the p-type transistor211, the transistor pair110, the terminal103, and the p-type transistor216. The drain of the n-type transistor215may be connected to the drain of the p-type transistor211. The source of the n-type transistor215may be connected to the terminal103and the source of the p-type transistor216. The gate of the n-type transistor215may be connected to the transistor pair110(e.g., the gate of the n-type transistor112).

InFIG.6, the p-type transistor216may be connected between the n-type transistor215, the transistor pair120, the terminal103, and the p-type transistor661. The source of the p-type transistor216may be connected to the terminal103and the source of the n-type transistor215. The drain of the p-type transistor216may be connected to the source of the p-type transistor661. The gate of the p-type transistor216may be connected to the transistor pair120(e.g., the gate of the p-type transistor121).

InFIG.6, the drain of the p-type transistor661may be connected to the drain of the n-type transistor213. The source of the p-type transistor661may be connected to the drain of the p-type transistor216. The gate of the p-type transistor661may be connected to the transistor pair510(e.g., the source of the p-type transistor511), the impedance element192, the gate of the n-type transistor662, and the gate of the p-type transistor561.

InFIG.6, the source of the n-type transistor662may be connected to the drain of the n-type transistor214. The drain of the n-type transistor662may be connected to the drain of the p-type transistor232. The gate of the n-type transistor662may be connected to the transistor pair510(e.g., the source of the p-type transistor511), the impedance element192, the gate of the p-type transistor661, and the gate of the p-type transistor561.

InFIG.6, the n-type transistor213may be a diode-connected transistor. The gate and the drain of the n-type transistor213may be connected. The n-type transistor213may be connected between the p-type transistor661, the n-type transistor214, and the terminal102. The drain of the n-type transistor213may be connected to the drain of the p-type transistor661. The source of the n-type transistor213may be connected to the terminal102. The gate of the n-type transistor213may be connected to the gate of the n-type transistor214.

InFIG.6, the n-type transistor214may be connected between the n-type transistor662, the n-type transistor213, and the terminal102. The drain of the n-type transistor214may be connected to the source of the n-type transistor662. The source of the n-type transistor214may be connected to the terminal102. The gate of the n-type transistor214may be connected to the gate of the n-type transistor213. The n-type transistors213and214may form a current mirror.

InFIG.6, the n-type transistor231may be a diode-connected transistor. The gate and the drain of the n-type transistor231may be connected. The n-type transistor231may be connected between the p-type transistor212, the p-type transistor232, and the transistor pair130. The drain of the n-type transistor231may be connected to the drain of the p-type transistor212. The source of the n-type transistor231may be connected to the source of the p-type transistor232. The gate of the n-type transistor232may be connected to the transistor pair130(e.g., the gate of the n-type transistor131). The n-type transistors131and231may form a current mirror.

InFIG.6, the p-type transistor232may be a diode-connected transistor. The gate and the drain of the p-type transistor232may be connected. The p-type transistor232may be connected between the n-type transistor231, the n-type transistor662, and the transistor pair130. The source of the p-type transistor232may be connected to the source of the n-type transistor231. The drain of the p-type transistor232may be connected to the drain of the n-type transistor662. The gate of the p-type transistor232may be connected to the transistor pair130(e.g., the gate of the p-type transistor132). The p-type transistors132and232may form a current mirror. The n-type transistor213and the p-type transistor214may be a transistor pair or a gain transistor pair.

In bias voltage generating device600, the n-type transistor561may cause a voltage drop between the terminal102and the transistor pair130(e.g., the p-type transistor132). The n-type transistor561may protect the p-type transistor132from high voltage stress. In some embodiments, the bias voltage generating device600may not have the p-type transistor561.

The p-type transistor661may cause a voltage drop between the transistors213and216. The p-type transistor661may protect the p-type transistor216from high voltage stress. In some embodiments, the bias voltage generating device600may not have the p-type transistor661.

The n-type transistor662may cause a voltage drop between the transistors214and232. The n-type transistor662may protect the p-type transistor214from high voltage stress. In some embodiments, the bias voltage generating device600may not have the n-type transistor662.

When VDD is provided at the terminal101and GND is provided at the terminal102, the voltage applied to the gate of the transistor561, the gate of the transistor661, and the gate of the transistor662may be

13⁢V⁢DD

Due to the sense section610and the gain section230in the bias voltage generating device600, the output voltage at the terminal103may be more stable, and the error rate (e.g., variation) of the output voltage at the terminal103may be decreased.

FIG.7is a schematic diagram of a bias voltage generating bias voltage generating device700in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, the bias voltage generating device700may further include an impedance element791, transistor pairs710,720,740, and750, a transistor pair730, and a terminal703.

The terminal703may be an output terminal to output a bias voltage. The voltage terminal703may be a voltage terminal to drive an electronic device. When VDD is provided at the terminal101and GND is provided at the terminal102, the output voltage of

23⁢V⁢DD
is provided at the terminal103of the bias voltage generating device700, and the output voltage of

13⁢V⁢DD
is provided at the terminal703of the bias voltage generating device700.

InFIG.7, the transistor pair710may be or include a diode connected transistor pair. The transistor pair710may be connected between the impedance element192and the transistor pair720. The transistor pair710may include a p-type transistor711and a n-type transistor712. In some embodiments, each of the p-type transistor711and the n-type transistor712may be a diode-connected transistor. For example, the p-type transistor711may be a p-type MOSFET, and the drain and the gate of the p-type transistor711may be connected to each other. For example, the n-type transistor712may be a n-type MOSFET, and the drain and the gate of the n-type transistor712may be connected to each other. In the transistor pair710, the drain and the gate of the p-type transistor711is connected to the drain and the gate of the n-type transistor712.

InFIG.7, the transistor pair720may be or include a diode connected transistor pair. The transistor pair720may be connected between the impedance element791and the transistor pair710. The transistor pair720may include a p-type transistor721and a n-type transistor722. In some embodiments, each of the p-type transistor721and the n-type transistor722may be a diode-connected transistor. For example, the p-type transistor721may be a p-type MOSFET, and the drain and the gate of the p-type transistor721may be connected to each other. For example, the n-type transistor722may be a n-type MOSFET, and the drain and the gate of the n-type transistor722may be connected to each other. In the transistor pair720, the drain and the gate of the p-type transistor721is connected to the drain and the gate of the n-type transistor722.

The transistor pairs710and720are connected. For example, the source of the n-type transistor712may be connected to the source of the p-type transistor721.

InFIG.7, the transistor pair740may be or include a diode connected transistor pair. The transistor pair740may be connected between the impedance element191and the terminal101. The transistor pair740may include a p-type transistor741and a n-type transistor742. In some embodiments, each of the p-type transistor741and the n-type transistor742may be a diode-connected transistor. For example, the p-type transistor741may be a p-type MOSFET, and the drain and the gate of the p-type transistor741may be connected to each other. For example, the n-type transistor742may be a n-type MOSFET, and the drain and the gate of the n-type transistor742may be connected to each other. In the transistor pair740, the drain and the gate of the p-type transistor741is connected to the drain and the gate of the n-type transistor742. The source of the p-type transistor741may be connected to the terminal101. The source of the n-type transistor742may be connected to the impedance element191.

InFIG.7, the impedance element791may be connected between the transistor pairs720and750. The impedance element791may be connected to source of the n-type transistor pair722. The impedance element791may be connected to source of the p-type transistor pair751.

InFIG.7, the transistor pair750may be or include a diode connected transistor pair. The transistor pair750may be connected between the impedance element791and the terminal102. The transistor pair750may include a p-type transistor751and a n-type transistor752. In some embodiments, each of the p-type transistor751and the n-type transistor752may be a diode-connected transistor. For example, the p-type transistor751may be a p-type MOSFET, and the drain and the gate of the p-type transistor751may be connected to each other. For example, the n-type transistor752may be a n-type MOSFET, and the drain and the gate of the n-type transistor752may be connected to each other. In the transistor pair750, the drain and the gate of the p-type transistor751is connected to the drain and the gate of the n-type transistor752. The source of the p-type transistor751may be connected to the impedance element791. The source of the n-type transistor752may be connected to the terminal102.

InFIG.7, a reference bias section of the bias voltage generating device700may include the impedance elements191,192, and791, and the transistor pairs110,120,710,720,740, and750.

The transistor pair730may be connected between the transistor pair130and the terminals102and703. The transistor pair730may be connected to the drain of the p-type transistor132. The transistor pair730may include a n-type transistor731and a p-type transistor732. For example, the n-type transistor731may be a n-type MOSFET, and the p-type transistor732may be a p-type MOSFET. The source of the n-type transistor731may be connected to the source of the p-type transistor732. The gate of the n-type transistor731may be connected to the transistor pair710. The gate of the n-type transistor731may be connected to the gate of the n-type transistor712. The gate of the p-type transistor732may be connected to the transistor pair720. The gate of the p-type transistor732may be connected to the gate of the p-type transistor721. The terminal703may be connected to the source of the n-type transistor731and the source of the p-type transistor732.

InFIG.7, a driving section of the bias voltage generating device700may include the transistor pairs130and730.

FIG.8Ais a schematic diagram of a bias voltage generating device800in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device100inFIG.1A, the bias voltage generating device800may further include impedance elements891-iand892-j, transistor pairs810-iand820-j, a n-type transistor861-i(e.g., a n-type MOSFET), and a p-type transistor862-j(e.g., a p-type MOSFET).

In the bias voltage generating device800, 0≤i≤M and 0≤j≤N, where i, j, M, and N may be non-negative integers. For example, when M is 5, i may be 0, 1, 2, 3, 4, and 5; when N is 4, j may be 0, 1, 2, 3, and 4. In embodiments in which both M and N are 0, the bias voltage generating device800may be substantially identical to the bias voltage generating device100.

When VDD is provided at the terminal101and GND is provided at the terminal102, the output voltage of

(1+N)(2+M+N)⁢V⁢DD
is provided at the terminal103of the bias voltage generating device800, where the variants M and N may represent non-negative integers. For example, if both M and N are 0, the output voltage of

12⁢V⁢DD
is provided at the terminal103of the bias voltage generating device800. If M is 1 and N is 2, the output voltage of

35⁢V⁢DD
is provided at the terminal103of the bias voltage generating device800.

InFIG.8A, the transistor pair810-imay be or include a diode connected transistor pair. The transistor pair810-imay be connected between the impedance element891-iand the terminal101. The transistor pair810-imay include a p-type transistor811-iand a n-type transistor812-i. In some embodiments, each of the p-type transistor811-iand the n-type transistor812-imay be a diode-connected transistor. For example, the p-type transistor811-imay be a p-type MOSFET, and the drain and the gate of the p-type transistor811-imay be connected to each other. For example, the n-type transistor812-imay be a n-type MOSFET, and the drain and the gate of the n-type transistor812-imay be connected to each other. In the transistor pair810-i, the drain and the gate of the p-type transistor811-iis connected to the drain and the gate of the n-type transistor812-i. The source of the n-type transistor812-imay be connected to the impedance element891-i.

InFIG.8A, the impedance element891-imay be connected to the transistor pair810-i(e.g., source of the n-type transistor812-i) and the gate of n-type transistor861-i.

In some embodiments, the sequence of the impedance element891-iand the diode connected pair810-imay be reversed. For example, the impedance element891-imay be connected to the source of the p-type transistor811-i, and the source of the n-type transistor812-imay be connected to the gate of the n-type transistor861-iand the impedance element192.

InFIG.8A, the n-type transistor861-imay be connected between the terminal101, the impedance element891-i, and the transistor pair130. The drain of the n-type transistor861-imay be connected to the terminal101. The source of the n-type transistor861-imay be connected to the drain of the n-type transistor131. The gate of the n-type transistor861-imay be connected to the impedance element891-i.

InFIG.8A, the n-type transistor861-imay cause a voltage drop between the terminal101and the transistor pair130(e.g., the n-type transistor131). The n-type transistor861-imay protect the n-type transistor131from high voltage stress. In some embodiments, the bias voltage generating device800may not have the n-type transistor861-i.

InFIG.8A, the transistor pair820-jmay be or include a diode connected transistor pair. The transistor pair820-jmay be connected to the impedance element892-j. The transistor pair820-jmay include a p-type transistor821-jand a n-type transistor822-j. In some embodiments, each of the p-type transistor821-jand the n-type transistor822-jmay be a diode-connected transistor. For example, the p-type transistor821-jmay be a p-type MOSFET, and the drain and the gate of the p-type transistor821-jmay be connected to each other. For example, the n-type transistor822-jmay be a n-type MOSFET, and the drain and the gate of the n-type transistor822-jmay be connected to each other. In the transistor pair820-j, the drain and the gate of the p-type transistor821-jmay be connected to the drain and the gate of the n-type transistor822-j. The source of the n-type transistor822-jmay be connected to the impedance element892-j.

InFIG.8A, the impedance element892-jmay be connected between the transistor pair820-j(e.g., source of the n-type transistor822-j) and the terminal102.

In some embodiments, the sequence of the impedance element892-jand the diode connected pair820-jmay be reversed. For example, the impedance element892-jmay be connected between the source of the p-type transistor821-j, the gate of the p-type transistor862-j, and the impedance element192, and the source of the n-type transistor822-jmay be connected to the terminal102.

InFIG.8A, the p-type transistor862-jmay be connected between the terminal102, the impedance element192, and the transistor pair130. The drain of the p-type transistor862-jmay be connected to the terminal102. The source of the p-type transistor862-jmay be connected to the drain of the p-type transistor132. The gate of the p-type transistor862-jmay be connected to diode connected pair820-j(e.g., the source of the p-type transistor821-i).

InFIG.8A, the p-type transistor862-jmay cause a voltage drop between the terminal101and the transistor pair130(e.g., the p-type transistor132). The p-type transistor862-jmay protect the p-type transistor132from high voltage stress. In some embodiments, the bias voltage generating device800may not have the p-type transistor862-j.

The bias voltage generating device800may include a reference bias section and a driving section. The reference bias section may include the transistor pairs110,120,810-i, and820-j, and impedance elements191,192,891-i, and892-j. The driving section may include the transistor pair130and transistors861-iand862-j.

In embodiments in which M is 0, the bias voltage generating device800may not include the impedance element891-i, the transistor pair810-i, and the n-type transistor861-i.

FIG.8Bis a schematic diagram of a portion of bias voltage generating device800in accordance with some embodiments of the present disclosure. In particular,FIG.8Bis a schematic diagram of a portion of bias voltage generating device800in accordance with embodiments in which M is 1.

InFIG.8B, the impedance element891-1may be connected between the impedance element191and the transistor pair810-1(e.g., the source of the n-type transistor812-1) and connected to the gate of the n-type transistor861-1. The transistor pair810-1may be connected between the impedance element891-1and the terminal101(through the source of the p-type transistor811-1). The drain of the n-type transistor861-1may be connected to the terminal101. The source of the n-type transistor861-1may be connected to the transistor pair130(e.g., the drain of the n-type transistor131).

FIG.8Cis a schematic diagram of a portion of bias voltage generating device800in accordance with some embodiments of the present disclosure. In particular,FIG.8Cis a schematic diagram of a portion bias voltage generating device800in accordance with embodiments in which M is 3.

InFIG.8C, the impedance element891-1may be connected between the impedance element191and the transistor pair810-1(e.g., the source of the n-type transistor812-1), and the gate of the n-type transistor861-1. The transistor pair810-1may be connected between the impedance element891-1(through the source of the n-type transistor812-1) and the impedance element891-2(through the source of the p-type transistor811-1) and connected to the gate of the n-type transistor861-2(through the source of the p-type transistor811-1). The drain of the n-type transistor861-1may be connected to the source of the n-type transistor861-2. The source of the n-type transistor861-1may be connected to the transistor pair130(e.g., the drain of the n-type transistor131).

InFIG.8C, the impedance element891-2may be connected between the transistor pair810-1(e.g., the source of the p-type transistor811-1), the transistor pair810-2(e.g., the source of the n-type transistor812-2), and the gate of the n-type transistor861-2. The transistor pair810-2may be connected between the impedance element891-2(through the source of the n-type transistor812-2), the impedance element891-3(through the source of the p-type transistor811-2), and the gate of the n-type transistor861-3(through the source of the p-type transistor811-2). The drain of the n-type transistor861-2may be connected to the source of the n-type transistor861-3. The source of the n-type transistor861-2may be connected to the drain of the n-type transistor861-1.

InFIG.8C, the impedance element891-3may be connected between the transistor pair810-2(e.g., the source of the p-type transistor811-2) and the transistor pair810-3(e.g., the source of the n-type transistor812-2) and connected to the gate of the n-type transistor861-3. The transistor pair810-3may be connected between the impedance element891-3(through the source of the n-type transistor812-3) and the terminal101(through the source of the p-type transistor811-3). The drain of the n-type transistor861-3may be connected to terminal101. The source of the n-type transistor861-3may be connected to the drain of the n-type transistor861-2.

In embodiments in which N is 0, the bias voltage generating device800may not include the impedance element892-j, the transistor pair820-j, and the p-type transistor862-j.

FIG.8Dis a schematic diagram of a portion of bias voltage generating device800in accordance with some embodiments of the present disclosure. In particular,FIG.8Dis a schematic diagram of a portion of bias voltage generating device800in accordance with embodiments in which N is 1.

InFIG.8D, the impedance element892-1may be connected between the terminal102and the transistor pair820-1(e.g., the source of the n-type transistor822-1). The transistor pair820-1may be connected between the impedance element892-1and the impedance element192(through the source of the p-type transistor821-1) and connected to the gate of the p-type transistor862-1(through the source of the p-type transistor821-1). The drain of the p-type transistor862-1may be connected to the terminal102. The source of the p-type transistor862-1may be connected to the transistor pair130(e.g., the drain of the p-type transistor132).

FIG.8Eis a schematic diagram of a portion of bias voltage generating device800in accordance with some embodiments of the present disclosure. In particular,FIG.8Eis a schematic diagram of a portion bias voltage generating device800in accordance with embodiments in which Nis3.

InFIG.8E, the impedance element892-1may be connected between the transistor pair820-1(e.g., the source of the n-type transistor822-1) and the transistor pair820-2(e.g., the source of the p-type transistor821-2) and connected to the gate of the p-type transistor862-1. The transistor pair820-1may be connected between the impedance element192(through the source of the p-type transistor821-1), the impedance element892-1(through the source of the n-type transistor822-1), and the gate of the p-type transistor862-1(through the source of the p-type transistor821-1). The drain of the p-type transistor862-1may be connected to the source of the p-type transistor862-2. The source of the p-type transistor862-1may be connected to the transistor pair130(e.g., the drain of the p-type transistor132).

InFIG.8E, the impedance element892-2may be connected between the transistor pair820-2(e.g., the source of the n-type transistor822-2), the transistor pair820-3(e.g., the source of the p-type transistor821-3), and the gate of the p-type transistor862-3. The transistor pair820-2may be connected between the impedance element892-2(through the source of the n-type transistor822-2) and the impedance element892-1(through the source of the p-type transistor821-2) and connected to the gate of the p-type transistor862-2(through the source of the p-type transistor821-2). The drain of the p-type transistor862-2may be connected to the source of the p-type transistor862-3. The source of the p-type transistor862-2may be connected to the drain of the p-type transistor862-1.

InFIG.8E, the impedance element892-3may be connected between the transistor pair820-3(e.g., the source of the n-type transistor822-3) and the terminal102. The transistor pair820-3may be connected between the impedance element892-3(through the source of the n-type transistor822-3), the impedance element892-2(through the source of the p-type transistor821-3), and the gate of the p-type transistor862-3(through the source of the p-type transistor821-3). The drain of the p-type transistor862-3may be connected to terminal102. The source of the p-type transistor862-3may be connected to the drain of the n-type transistor862-2.

FIG.9Ais a schematic diagram of a bias voltage generating device900in accordance with some embodiments of the present disclosure. Compared with the bias voltage generating device900inFIG.8A, the bias voltage generating device900may further include a sense section910and a gain section230. Compared with the bias voltage generating device800inFIG.8A, the bias voltage generating device900may include a further push-pull stage. Compared with the bias voltage generating device800inFIG.8A, the bias voltage generating device900may include a negative feedback function.

InFIG.9A, the bias voltage generating device900may include p-type transistors211,212,216,232,862-j,962-i, and963-j(e.g., p-type MOSFETs) and n-type transistors213,214,215,231,861-i,961-i, and964-j(e.g., n-type MOSFETs). The sense section910may include the p-type transistors211,212,216,962-i, and963-j(e.g., p-type MOSFETs) and the n-type transistors213,214,215,961-i, and964-j(e.g., n-type MOSFETs). The gain section230may include the p-type transistor232(e.g., a p-type MOSFET) and the n-type transistor231(e.g., a n-type MOSFET). The reference bias section may include the transistor pairs110,120,810-i, and820-j, and impedance elements191,192,891-i, and892-j. The driving section may include the transistor pair130and transistors861-iand862-j.

InFIG.9A, the p-type transistor211may be a diode-connected transistor. The gate and the drain of the p-type transistor211may be connected. The p-type transistor211may be connected to the terminal101, the p-type transistor212, and the n-type transistor961-i. The source of the p-type transistor211may be connected to the terminal101. The drain of the p-type transistor211may be connected to the drain of the n-type transistor961-i. The gate of the p-type transistor211may be connected to the gate of the p-type transistor212.

InFIG.9A, the p-type transistor212may be connected between the terminal101, the p-type transistor212, and the p-type transistor962-i. The source of the p-type transistor212may be connected to the terminal101. The drain of the p-type transistor212may be connected to the source of the p-type transistor962-i. The gate of the p-type transistor212may be connected to the gate of the p-type transistor211. The p-type transistors211and212may form a current mirror.

InFIG.9A, the drain of the n-type transistor961-imay be connected to the drain of the p-type transistor211. The source of the n-type transistor961-imay be connected to the drain of the n-type transistor215. The gate of the n-type transistor961-imay be connected to the impedance element191, the impedance element891-i, the gate of the p-type transistor962-i, and the gate of the n-type transistor861-i.

InFIG.9A, the source of the p-type transistor962-imay be connected to the drain of the p-type transistor212. The drain of the p-type transistor962-imay be connected to the drain of the n-type transistor231. The gate of the p-type transistor962-imay be connected to the impedance element191, the impedance element891-i, the gate of the n-type transistor961-i, and the gate of the n-type transistor861-i.

InFIG.9A, the n-type transistor215may be connected between the n-type transistor961-i, the transistor pair110, the terminal103, and the p-type transistor216. The drain of the n-type transistor215may be connected to the source of the n-type transistor961-i. The source of the n-type transistor215may be connected to the terminal103and the source of the p-type transistor216. The gate of the n-type transistor215may be connected to the transistor pair110(e.g., the gate of the n-type transistor112).

InFIG.9A, the p-type transistor216may be connected between the n-type transistor215, the transistor pair120, the terminal103, and the p-type transistor963-j. The source of the p-type transistor216may be connected to the terminal103and the source of the n-type transistor215. The drain of the p-type transistor216may be connected to the source of the p-type transistor963-j. The gate of the p-type transistor216may be connected to the transistor pair120(e.g., the gate of the p-type transistor121).

InFIG.9A, the drain of the p-type transistor963-jmay be connected to the drain of the n-type transistor213. The source of the p-type transistor963-jmay be connected to the drain of the p-type transistor216. The gate of the p-type transistor963-jmay be connected to the transistor pair820-j(e.g., the source of the p-type transistor820-j), the impedance element192, the gate of the n-type transistor964-j, and the gate of the p-type transistor862-j.

InFIG.9A, the source of the n-type transistor964-jmay be connected to the drain of the n-type transistor214. The drain of the n-type transistor964-jmay be connected to the drain of the p-type transistor232. The gate of the n-type transistor964-jmay be connected to the transistor pair820-j(e.g., the source of the p-type transistor821-j), the impedance element192, the gate of the p-type transistor963-j, and the gate of the p-type transistor862-j.

InFIG.9A, the n-type transistor213may be a diode-connected transistor. The gate and the drain of the n-type transistor213may be connected. The n-type transistor213may be connected between the p-type transistor963-j, the n-type transistor214, and the terminal102. The drain of the n-type transistor213may be connected to the drain of the p-type transistor963-j. The source of the n-type transistor213may be connected to the terminal102. The gate of the n-type transistor213may be connected to the gate of the n-type transistor214.

InFIG.9A, the n-type transistor214may be connected between the n-type transistor964-j, the n-type transistor213, and the terminal102. The drain of the n-type transistor214may be connected to the source of the n-type transistor964-j. The source of the n-type transistor214may be connected to the terminal102. The gate of the n-type transistor214may be connected to the gate of the n-type transistor213. The n-type transistors213and214may form a current mirror.

InFIG.9A, the n-type transistor231may be a diode-connected transistor. The gate and the drain of the n-type transistor231may be connected. The n-type transistor231may be connected between the p-type transistor962-i, the p-type transistor232, and the transistor pair130. The drain of the n-type transistor231may be connected to the drain of the p-type transistor962-i. The source of the n-type transistor231may be connected to the source of the p-type transistor232. The gate of the n-type transistor232may be connected to the transistor pair130(e.g., the gate of the n-type transistor131). The n-type transistors131and231may form a current mirror.

InFIG.9A, the p-type transistor232may be a diode-connected transistor. The gate and the drain of the p-type transistor232may be connected. The p-type transistor232may be connected between the n-type transistor231, the n-type transistor964-j, and the transistor pair130. The source of the p-type transistor232may be connected to the source of the n-type transistor231. The drain of the p-type transistor232may be connected to the drain of the n-type transistor964-j. The gate of the p-type transistor232may be connected to the transistor pair130(e.g., the gate of the p-type transistor132). The p-type transistors132and232may form a current mirror. The n-type transistor213and the p-type transistor214may be a transistor pair or a gain transistor pair.

In bias voltage generating device900, the n-type transistor961-imay cause a voltage drop between the transistors211and215. The n-type transistor961-imay protect the n-type transistor215from high voltage stress. In some embodiments, the bias voltage generating device900may not have the n-type transistor961-i. The p-type transistor962-imay cause a voltage drop between the transistors212and231. The p-type transistor962-imay protect the p-type transistor212from high voltage stress. In some embodiments, the bias voltage generating device900may not have the p-type transistor962-i.

In the bias voltage generating device900, the p-type transistor963-jmay cause a voltage drop between the transistors213and216. The p-type transistor963-jmay protect the p-type transistor216from high voltage stress. In some embodiments, the bias voltage generating device900may not have the p-type transistor963-j. The n-type transistor964-jmay cause a voltage drop between the transistors214and232. The n-type transistor964-jmay protect the p-type transistor214from high voltage stress. In some embodiments, the bias voltage generating device900may not have the n-type transistor964-j.

In the bias voltage generating device900, 0≤i≤M and 0≤j≤N, where i, j, M, and N may be non-negative integers. For example, when M is 5, i may be 0, 1, 2, 3, 4, and 5; when N is 4, j may be 0, 1, 2, 3, and 4. In embodiments in which both M and N are 0, the bias voltage generating device900may be substantially identical the bias voltage generating device200.

When VDD is provided at the terminal101and GND is provided at the terminal102, the output voltage of

(1+N)(2+M+N)⁢V⁢DD
is provided at the terminal103of the bias voltage generating device900, where the variants M and N may represent non-negative integers. For example, if both M and N are 0, the output voltage of

12⁢V⁢DD
is provided at the terminal103of the bias voltage generating device900. If M is 1 and N is 2, the output voltage of

35⁢V⁢DD
is provided at the terminal103of the bias voltage generating device900.

Because of the sense section910and the gain section230in the bias voltage generating device900, the output voltage at the terminal103may be more stable, and the error rate (e.g., variation) of the output voltage at the terminal103may be decreased.

In embodiments in which M is 0, the bias voltage generating device900may not include the impedance element891-i, the transistor pair810-i, the n-type transistor961-i, the p-type transistor962-i, and the n-type transistor861-i.

FIG.9Bis a schematic diagram of a portion of bias voltage generating device800in accordance with some embodiments of the present disclosure. In particular,FIG.9Bis a schematic diagram of a portion bias voltage generating device800in accordance with embodiments in which M is 1.FIG.9Bclearly discloses the coupling between components in embodiments in which M is 1.

FIG.9Cis a schematic diagram of a portion of bias voltage generating device800in accordance with some embodiments of the present disclosure. In particular,FIG.9Cis a schematic diagram of a portion of bias voltage generating device800in accordance with embodiments in which M is 3.FIG.9cclearly discloses coupling between components in embodiments in which M is 3.

In embodiments in which N is 0, the bias voltage generating device900may not include the impedance element892-j, the transistor pair820-j, the p-type transistor963-j, the n-type transistor964-j, and the p-type transistor862-j.

FIG.9Dis a schematic diagram of a portion of bias voltage generating device800in accordance with some embodiments of the present disclosure. In particular,FIG.9Dis a schematic diagram of a portion bias voltage generating device800in accordance with embodiments in which N is 1.FIG.9Dclearly discloses coupling between components in embodiments in which N is 1.

FIG.9Eis a schematic diagram of a portion of bias voltage generating device800in accordance with some embodiments of the present disclosure. In particular,FIG.9Eis a schematic diagram of a portion bias voltage generating device800in accordance with embodiments in which N is 3.FIG.9Eclearly discloses coupling between components in embodiments in which N is 3.

FIG.10is a flowchart of a method1000for generating bias voltage in accordance with some embodiments of the present disclosure. In operation1001, a bias voltage generating circuit may be formed. The bias voltage generating circuit may comprise: a first voltage terminal; a second voltage terminal; a first output terminal; a reference bias section connected to the first voltage terminal and the second voltage terminal; and a driving section connected to the reference bias section, the first voltage terminal and the second voltage terminal. The reference bias section may comprise a first impedance element, a second impedance element, a first diode-connected transistor pair, and a second diode-connected transistor pair. The driving section may comprise a first transistor pair.

In operation1003, a first voltage may be supplied at the first voltage terminal. In operation1005, a second voltage may be supplied at the second voltage terminal. In operation1007, an output voltage may be output or generated at the first output terminal. The output voltage may be half of a voltage difference between the first voltage and the second voltage.

In some embodiments, the bias voltage generating circuit may further comprise a sense section and a gain section. The sense section may be connected to the first voltage terminal and the second voltage terminal. The sense section may comprise a second transistor pair, a first current mirror, and a second current mirror. The gain section may be connected to the first transistor pair, the first current mirror, and the second current mirror. The gain section may include a diode-connected n-type transistor and a diode-connected p-type transistor.

In some embodiments, the present disclosure provides a bias voltage generating device. The bias voltage generating device includes a first voltage terminal; a second voltage terminal; a first output terminal; a first diode-connected transistor pair; a second diode-connected transistor pair; a first impedance element; a second impedance element; and a first transistor pair. The first impedance element is connected to the first voltage terminal and the first diode-connected transistor pair. The first diode-connected transistor pair is connected to the first impedance element and the second diode-connected transistor pair. The second diode-connected transistor pair is connected to the first diode-connected transistor pair and the second impedance element. The second impedance element is connected to the second diode-connected transistor pair and the second voltage terminal. The first transistor pair connected to the first voltage terminal, the second voltage terminal, the first output terminal, the first diode-connected transistor pair, and the second diode-connected transistor pair.

In some embodiments, the present disclosure provides a bias voltage generating device. The bias voltage generating device includes a first voltage terminal; a second voltage terminal; a first output terminal; a reference bias section connected to the first voltage terminal and the second voltage terminal; and a driving section connected to the reference bias section, the first voltage terminal and the second voltage terminal. The reference bias section comprises a first impedance element, a second impedance element, a first diode-connected transistor pair, and a second diode-connected transistor pair. The driving section comprising a first transistor pair. The bias voltage generating device is configured to generate an output voltage at the first output terminal, the output voltage is half of a voltage difference between the first voltage terminal and the second voltage terminal.

In some embodiments, the present disclosure provides a method for generating bias voltage. The method includes forming a bias voltage generating circuit; supplying a first voltage at the first voltage terminal; supplying a second voltage at the second voltage terminal; outputting an output voltage at the first output terminal, wherein the output voltage is half of a voltage difference between the first voltage and the second voltage. The bias voltage generating circuit comprises: a first voltage terminal; a second voltage terminal; a first output terminal; a reference bias section connected to the first voltage terminal and the second voltage terminal; and a driving section connected to the reference bias section, the first voltage terminal and the second voltage terminal. The reference bias section comprises a first impedance element, a second impedance element, a first diode-connected transistor pair, and a second diode-connected transistor pair. The driving section comprises a first transistor pair.

The scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As those skilled in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, composition of matter, means, methods or steps presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such as processes, machines, manufacture, compositions of matter, means, methods or steps/operations. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.