Patent ID: 12243846

DETAILED DESCRIPTION

It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

FIG.1Ais a cross-sectional view of a semiconductor package including a bonding wire, according to an example embodiment.FIG.1Bis a cross-sectional view of a Region BB inFIG.1A.FIG.1Cis a plan view of a first pad portion.FIG.1Dis a plan view of a second pad portion.

Referring toFIGS.1A,1B,1C and1D, a semiconductor package100may include a first semiconductor chip110, a second semiconductor chip120, an assembly board210, a molding member310, and a bonding wire10.

The semiconductor package100may include the first and second semiconductor chips110and120, which are vertically stacked on the assembly board210.

The first and second semiconductor chips110and120may each be electrically connected to the assembly board210through the bonding wire10. In addition, the first and second semiconductor chips110and120may be attached to each other by an adhesive film AF.

Each of the first and second semiconductor chips110and120may include a memory chip or a logic chip. For example, both of the first and second semiconductor chips110and120may include the same type of memory chip, or one of the first and second semiconductor chips110and120may include a memory chip and the other may include a logic chip.

The memory chip may include a volatile or nonvolatile memory chip. The volatile memory chip may include, for example, an existing volatile memory chip, such as dynamic random access memory (DRAM), static RAM (SRAM), or thyristor RAM (TRAM), or a volatile memory chip that is being developed. The nonvolatile memory chip may include, for example, an existing nonvolatile memory chip, such as flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM (STT-MRAM), ferroelectric RAM (FRAM), phase change RAM (PRAM), or resistive RAM (RRAM), or a nonvolatile memory chip that is being developed.

The logic chip may be implemented as, for example, a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, or a system on chip, but is not limited thereto.

Although the semiconductor package100in which the first and second semiconductor chips110and120are stacked is illustrated, the number of semiconductor chips stacked in the semiconductor package100is not limited to two. For example, one, three, four or more semiconductor chips may be stacked in the semiconductor package100.

The first semiconductor chip110may include a first semiconductor substrate113and a chip pad115. The chip pad115may be referred to as a first pad herein. The first semiconductor substrate113may have a top surface and a bottom surface which face each other. The first semiconductor substrate113may include a semiconductor device layer. The chip pad115may be formed on the semiconductor device layer. The chip pad115may include at least one material among aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

The first semiconductor substrate113may include, for example, silicon. Alternatively, the first semiconductor substrate113may include a semiconductor element such as germanium or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first semiconductor substrate113may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate113may include a buried oxide (BOX) layer. The first semiconductor substrate113may include a conductive region, e.g., an impurity-doped well or an impurity-doped structure. The first semiconductor substrate113may have diverse isolation structures including a shallow trench isolation (STI) structure.

A passivation layer may be formed on the first semiconductor substrate113to protect the semiconductor device layer and other structures in the first semiconductor substrate113from external shock or moisture. The passivation layer may expose at least a portion of a top surface of the chip pad115.

An adhesive film may be provided between a top surface of the assembly board210and a bottom surface of the first semiconductor chip110to attach the first semiconductor chip110to the assembly board210.

The second semiconductor chip120may be mounted on a top surface of the first semiconductor chip110. The adhesive film AF may be provided between the top surface of the first semiconductor chip110and a bottom surface of the second semiconductor chip120to attach the second semiconductor chip120to the first semiconductor chip110.

The second semiconductor chip120may include a second semiconductor substrate123and a chip pad125. The second semiconductor substrate123may have a top surface and a bottom surface which face each other. The second semiconductor substrate123may include a semiconductor device layer. The chip pad125may be formed on the semiconductor device layer.

The adhesive film AF may include, for example, a die attach film (DAF). The DAF may be classified into an inorganic adhesive or a polymer adhesive. The polymer adhesive may be classified into thermosetting resin and thermoplastic resin. The thermosetting resin has a three-dimensional cross-link structure after monomers are heated and is not softened when reheated. In contrast, the thermoplastic resin shows plasticity when heated and has a linear polymer structure. There is also a hybrid type produced by mixing these two types of resins.

The assembly board210is a supporting board and may include a body portion211, a lower protective layer, and an upper protective layer. The assembly board210may be formed based on a printed circuit board (PCB), a wafer substrate, a ceramic substrate, a glass substrate, an interposer, or the like. In some example embodiments, the assembly board210may include a PCB. However, the assembly board210is not limited to a PCB.

An internal wiring214may be formed in the assembly board210. The internal wiring214may be electrically connected to the first and second semiconductor chips110and120through the bonding wire10connected to an upper pad215in the top surface of the assembly board210. The upper pad215may be referred to as a second pad herein.

In addition, an external connection terminal230may be located on a lower pad213in a bottom surface of the assembly board210. The assembly board210may be electrically connected to and mounted on a module board or a system board of an electronic product through the external connection terminal230. The external connection terminal230may include, for example, a pillar structure, a ball structure, or a solder layer.

The internal wiring214may be formed in multiple layers or a single layer in the body portion211. The external connection terminal230may be electrically connected to the first and second semiconductor chips110and120through the internal wiring214. The lower protective layer and the upper protective layer protect the body portion211and may include, for example, solder resist.

When the assembly board210is a PCB, the body portion211may be embodied by compressing a polymer material such as thermosetting resin, epoxy resin such as flame retardant 4 (FR-4), bismaleimide triazine (BT), or an Ajinomoto build-up film (ABF), or phenol resin to a certain thickness to form a thin profile, coating both surfaces of the thin profile with a copper foil, and forming the internal wiring214, i.e., the transmission path of electrical signals, using patterning. The lower protective layer and the upper protective layer may be formed by applying solder resist to the entire bottom and top surfaces of the body portion211except for the lower pad213and the upper pad215.

Meanwhile, PCBs may be classified into a single layer PCB having the internal wiring214only at one side or a double layer PCB having the internal wiring214at each of both sides. In addition, at least three layers of copper foil may be formed using an insulator called prepreg, and at least three internal wirings214may be formed according to the number of layers of copper foil, so that a multilayer PCB may be implemented. The assembly board210is not limited to the structures or materials of a PCB, which have been described above.

The molding member310may be formed to surround the first and second semiconductor chips110and120and the bonding wire10.

The molding member310may include, for example, an epoxy molding compound. In some example embodiments, the molding member310is not limited to an epoxy molding compound and may include various materials, e.g., epoxy materials, thermosetting materials, thermoplastic materials, ultraviolet (UV) materials, etc. The thermosetting materials may include a phenol curing agent, an acid anhydride curing agent, an amine curing agent, and an acrylic polymer additive.

The molding member310is formed by injecting an appropriate amount of a molding material onto the assembly board210through an injection process, thereby forming the outer shape of the semiconductor package100. When necessary, the outer shape of the semiconductor package100is formed by applying pressure to the molding material in a pressure process such as pressing. At this time, process conditions, such as delay time between the injection and the pressing of the molding material, the amount of the injected molding material, and pressing temperature/pressure, may be set taking into account a physical property, such as viscosity, of the molding material.

Side and top surfaces of the molding member310may be at right angles. A marking pattern, e.g., a barcode, a number, a character, or a symbol, which includes information of the first and second semiconductor chips110and120, may be formed in a portion of the side surface of the molding member310.

The molding member310may function to protect the first and second semiconductor chips110and120from external influences such as contamination and shock. For this function, the molding member310may have a thickness at least enough to completely surround the first and second semiconductor chips110and120. The molding member310fully blankets the assembly board210, and a width of the molding member310may be substantially the same as a width of the semiconductor package100.

The bonding wire10may electrically connect each of the chip pads115and125to the upper pad215.

At least one of a control signal for an operation of each of the first and second semiconductor chips110and120, a power signal, and a ground signal may be received through the bonding wire10. A data signal to be stored in each of the first and second semiconductor chips110and120may be received through the bonding wire10. Data stored in the first and second semiconductor chips110and120may be output through the bonding wire10.

Although the bonding wire10is arranged on only one surface of each of the first and second semiconductor chips110and120in the drawings, the arrangement of the bonding wire10is not limited thereto. For example, the bonding wire10may be arranged on each of at least two surfaces of each of the first and second semiconductor chips110and120.

The bonding wire10may include at least one material among Au, silver (Ag), Cu, and Al. In some example embodiments, the bonding wire10may be connected using thermo-compression bonding, ultrasonic bonding, or thermosonic bonding, which is a combination of thermo-compression bonding and ultrasonic bonding.

For convenience's sake in the description, the bonding wire10connecting the chip pad115of the first semiconductor chip110to the upper pad215will be exemplarily described.

The bonding wire10may include a ball part11, a neck part13, a wire part15, and a stitch part17. In detail, the ball part11may be in direct contact with the top surface of the chip pad115. The neck part13may be on a top surface of the ball part11. The stitch part17may be in direct contact with a top surface of the upper pad215. The wire part15may connect the neck part13and the stitch part17to each other. In other words, the bonding wire10may be bonded to the chip pad115using a ball bonding method and to the upper pad215using a stitch bonding method.

At least a portion of a top surface13T of the neck part13of the bonding wire10may not to be covered with the wire part15. The top surface13T of the neck part13that is not covered with the wire part15may be substantially flat.

In some example embodiments, the wire part15of the bonding wire10may be in contact with the neck part13, the ball part11, and the chip pad115. In detail, the wire part15may be in contact with top and side surfaces of the neck part13, top and side surfaces of the ball part11, and the top surface of the chip pad115.

In some example embodiments, a pressed region15P having a V-shape may be formed in the wire part15of the bonding wire10that is connected to the neck part13. A sunken point in the pressed region15P, i.e., a point at which a top surface of the wire part15is at the lowest level, may be in a region in which the wire part15is in contact with the top surface of the chip pad115. The level of the sunken point in the pressed region15P may be lower than the level of the top surface13T of the neck part13. In addition, a lowest bottom surface of the pressed region15P may be in contact with the top surface of the chip pad115alongside a bottom surface of the ball part11.

In some example embodiments, a portion of the bonding wire10may pass through the inside of the adhesive film AF. The adhesive film AF may have a protrusion region AFP having a V-shape in a portion corresponding to the pressed region15P.

In the side cross-sectional view, a sum TH of a height of the ball part11and a height of the neck part13may be about 35 μm to about 40 μm. When the sum TH of the respective heights of the ball part11and the neck part13is less than 35 μm, the reliability of a strong connection structure may decrease. Contrarily, when the sum TH of the respective heights of the ball part11and the neck part13is greater than 40 μm, a thickness AFH of the adhesive film AF increases, and therefore, it may be hard to realize a small short lightweight semiconductor package.

As illustrated inFIG.1C, a diameter11D of the ball part11may be greater than a diameter13D of the neck part13. The diameter13D of the neck part13may be less than a maximum width15PW of the pressed region15P. A diameter15D of a normal region of the wire part15may be less than the maximum width15PW of the pressed region15P.

The bonding wire10may curve to form a loop shape. In this case, a loop height LH from the top surface of the chip pad115to the highest top surface of the bonding wire10may be greater than a sunken point15V of the bonding wire at the pressed region15P. In other words, the sunken point15V of the bonding wire10may be relatively lower than the loop height LH. The adhesive film AF may be formed such that the thickness AFH of the adhesive film AF is greater than the loop height LH of the bonding wire10, thereby preventing the bonding wire10from directly contacting the second semiconductor chip120.

Because the pressed region15P is formed by applying a mechanical force to the wire part15, a cutting defect may occur in the pressed region15P of the wire part15.

According to example embodiments, the pressed region15P having the V-shape is formed to be in contact with the neck part13, the ball part11, and the chip pad115in the bonding wire10, so that the loop height LH of the bonding wire10may be decreased and the occurrence of a cutting defect in the pressed region15P may also be decreased.

Therefore, in the semiconductor package100including the bonding wire10having the pressed region15P, the thickness AFH of the adhesive film AF covering a portion of the bonding wire10may be decreased.

Consequently, the semiconductor package100including the bonding wire10may decrease the loop height LH of the bonding wire10and secure the reliability of a connection structure, so that the total thickness of the semiconductor package100may be decreased. As a result, the semiconductor package100may have a high degree of integration and a high capacity, and may be short, small and lightweight.

FIG.2Ais a cross-sectional view of a semiconductor package including a bonding wire20, according to some example embodiments.FIG.2Bis a cross-sectional view of a Region BB inFIG.2A.

Because elements of a bonding wire20and a semiconductor package200and a material included in each of the elements are the same as or similar to those described above with reference toFIGS.1A,1B,1C and1D, descriptions below will focus on differences.

Referring toFIGS.2A and2B, the semiconductor package200may include the first semiconductor chip110, the second semiconductor chip120, the assembly board210, the molding member310, and the bonding wire20.

The bonding wire20may include a ball part21, a neck part23, a wire part25, and a stitch part27. In detail, the ball part21may be in direct contact with the top surface of the chip pad115. The neck part23may be on a top surface of the ball part21. The stitch part27may be in direct contact with a top surface of the upper pad215. The wire part25may connect the neck part23and the stitch part27to each other. In other words, the bonding wire20may be bonded to the chip pad115using a ball bonding method and to the upper pad215using a stitch bonding method.

A top surface23T of the neck part23of the bonding wire20may not be covered with the wire part25. In other words, the entire top surface23T of the neck part23may be completely covered with the adhesive film AF. The top surface23T of the neck part23that is not completely covered with the wire part25may be substantially flat.

In some example embodiments, the wire part25of the bonding wire20may be in contact with the neck part23, the ball part21, and the chip pad115. In detail, the wire part25of the bonding wire20may be in contact with a side surface of the neck part23, top and side surfaces of the ball part21, and the top surface of the chip pad115.

FIG.3is a flowchart of a wire bonding method according to an example embodiment.

The wire bonding method may include processes described below. The order of processes may be different from the order in which the processes are described. For instance, two processes sequentially described may be substantially performed simultaneously or in reverse order.

Referring toFIG.3, a wire bonding method S10may include forming a ball part by bonding a free air ball created at an end of a wire to a first pad using a capillary in operation S110, forming a neck part on the ball part by vertically moving up the capillary in operation S120, substantially leveling at least a portion of a top surface of the neck part by horizontally moving the capillary toward a second pad in operation S130, forming a wire part connected to the neck part by vertically moving down the capillary in operation S140, and extending and bonding the wire part to the second pad by moving the capillary to the second pad in operation S150.

In the wire bonding method S10, a V-shaped pressed region is formed to enable the wire part to be in contact with the neck part, the ball part, and the first pad, so that a loop height of a bonding wire formed on the first pad may be decreased and a cutting defect may also be decreased in the neck part and the wire part. At this time, the capillary may move from the first pad toward the second pad but not in a reverse direction.

FIGS.4A,4B,4C,4D,4E,4F,4G and4Hare cross-sectional views of stages in a wire bonding method, according to an example embodiment.

Referring toFIG.4A, the first semiconductor chip110may include the chip pad115. The assembly board210may include the upper pad215. Hereinafter, the chip pad115and the upper pad215are called a first pad and a second pad, respectively.

The first semiconductor chip110may be arranged on the assembly board210such that the second pad215is not covered. An adhesive film may be provided between the top surface of the assembly board210and the bottom surface of the first semiconductor chip110to attach the first semiconductor chip110to the assembly board210.

A capillary CA may be arranged at a first bonding position, e.g., above the first pad115. In some example embodiments, the capillary CA may be located at a level corresponding to a certain height, e.g., an electronic flame-off height, above the first pad115.

A portion of a reserve wire10P may protrude from a central hole of the capillary CA. The reserve wire10P may include at least one material among Au, Ag, Cu, and Al. An electric spark may be provided to the reserve wire10P protruding from the central hole of the capillary CA such that a lower end of the reserve wire10P may be melted. Accordingly, a free air ball10F may be formed at the lower end of the reserve wire10P in the central hole of the capillary CA. In some example embodiments, instead of an electric spark, ultrasonic energy or thermal energy may be provided to the lower end of the reserve wire10P.

Movement of the reserve wire10P may be limited in the capillary CA by closing a clamp.

Referring toFIG.4B, the capillary CA may be moved toward the first pad115such that the free air ball10F (seeFIG.4A) may contact the first pad115.

The free air ball10F may be pressed between the capillary CA and the first pad115such that the ball part11and the neck part13may be formed at the lower end of the reserve wire10P. Thermal energy and/or ultrasonic energy may be provided to the first semiconductor chip110such that the ball part11may be bonded to the first pad115. Consequently, a ball bonding method, by which the ball part11is bonded to the first pad115, may be implemented.

The neck part13may be shaped according to a chamfer angle inside the capillary CA. A diameter of the neck part13may be less than a diameter of the ball part11. Accordingly, the neck part13may be fully seated on the top surface of the ball part11.

Referring toFIG.4C, the capillary CA may be moved up perpendicular to the top surface of the first pad115such that the neck part13may be exposed outside the capillary CA.

The capillary CA may be vertically moved up to a height corresponding to a first distance D1from the first pad115. The first distance D1may be about 35 μm to about 40 μm.

In some example embodiments, the capillary CA may be vertically moved until the top surface of the neck part13is at the same level as a bottom surface of the capillary CA.

Referring toFIG.4D, the capillary CA may be moved in parallel with the top surface of the first pad115toward the second pad215such that a portion of the top surface13T of the neck part13may be exposed.

The capillary CA may be horizontally moved toward the second pad215by a second distance D2from the center of the neck part13. The second distance D2may be about 35 μm to about 45 μm but is not limited thereto.

In some example embodiments, the capillary CA may be horizontally moved in a state where the top surface13T of the neck part13is at the same level as the bottom surface of the capillary CA. In this case, the top surface13T of the neck part13may be in partial contact with the reserve wire10P. In other words, the bottom surface of the capillary CA may push a portion of the reserve wire10P, which contacts the top surface13T of the neck part13, toward the second pad215, so that the portion of the top surface13T of the neck part13may be exposed.

Referring toFIG.4E, the capillary CA may be moved down perpendicular to the top surface of the first pad115such that the bottom surface of the capillary CA may press down the wire part15, thereby forming the pressed region15P having a V-shape in the wire part15that is connected to the neck part13.

The pressed region15P may be formed by applying a mechanical force to the wire part15using the capillary CA. The capillary CA may be moved down perpendicular to the top surface of the first pad115by a third distance D3from the top surface13T of the neck part13. The third distance D3may be about 20 μm to about 30 μm but is not limited thereto.

The capillary CA may be horizontally moved such that the central hole of the capillary CA may be positioned above the first pad115that is not occupied by the ball part11and then moved down perpendicular to the top surface of the first pad115. The wire part15may be pressed down by the bottom surface of the capillary CA such that the pressed region15P, which has a V-shape and a maximum width greater than a diameter of the neck part13, may be formed in the wire part15having a cylindrical shape.

In some example embodiments, the pressed region15P may be formed using the capillary CA such that the wire part15may be in contact with the neck part13, the ball part11, and the first pad115. In detail, the wire part15may be in contact with the top and side surfaces of the neck part13, the top and side surfaces of the ball part11, and the top surface of the first pad115.

In some example embodiments, a sunken point15V in the pressed region15P may be in a region in which the wire part15is in contact with the top surface of the first pad115. In addition, the level of the sunken point15V in the pressed region15P may be lower than the level of the top surface13T of the neck part13.

Referring toFIG.4F, the capillary CA may be moved up perpendicular to the top surface of the first pad115.

In the side cross-sectional view, the sum TH of the respective heights of the ball part11and the neck part13may be about 35 μm to about 40 μm. This is because the reliability of a strong connection structure may decrease when the sum TH of the respective heights of the ball part11and the neck part13is less than 35 μm, and a thickness of the adhesive film may increase in subsequent processes, and therefore, it may be hard to realize a small short lightweight semiconductor package, when the sum TH of the respective heights of the ball part11and the neck part13is greater than 40 μm.

The clamp may be opened to allow reserve wire10P to form the wire part15that extends vertically from the top surface of the first pad115.

Referring toFIG.4G, the capillary CA that has been vertically moved up from the first pad115may be horizontally moved toward a second bonding position, e.g., the second pad215.

When the capillary CA moves with the clamp open, the wire part15discharged from the lower end of the capillary CA may be extended along the sliding of the capillary CA.

Through this operation, a wire loop may be formed between the first pad115and the second pad215. The wire part15may form the wire loop and move along the curvature path of the capillary CA without a break.

Referring toFIG.4H, when the capillary CA is vertically moved up from the top surface of the second pad215in a state where the clamp is closed, the reserve wire10P may be cut off from the stitch part17. As a result, the bonding wire10that electrically connects the first pad115and the second pad215to each other may be formed.

Due to the upward movement of the capillary CA, the stitch part17may be formed in a portion in which the reserve wire10P is bonded to the second pad215. In other words, a stitch bonding method, by which the stitch part17that is a part of the bonding wire10is bonded to the second pad215, may be implemented.

In some example embodiments, thermal energy or ultrasonic energy may be applied to the reserve wire10P when the reserve wire10P is cut off from the stitch part17.

The capillary CA may be moved up to the level corresponding to the electronic frame-off height. Thereafter, the capillary CA may perform a new wire bonding process or be on standby. For example, the capillary CA may repeat the stages shown inFIGS.4A,4B,4C,4D,4E,4F,4G and4H, thereby forming a plurality of bonding wires10.

Consequently, the wire bonding method may decrease the loop height of the bonding wire10and improve the reliability of a strong connection structure. Accordingly, the total thickness of the semiconductor package100(seeFIG.1A) including the bonding wire10may be decreased, to form the semiconductor package100that is short, small, and lightweight and has a high degree of integration and a high capacity.

FIG.5is a schematic diagram showing a moving direction of a capillary in a wire bonding method, according to an example embodiment.

Referring toFIG.5, a bonding wire may be formed by a continuous movement of a capillary from a point “a” to a point “b” to a point “c” to a point “d” to a point “e” to a point “e” to a point “f” to a point “g”.

After a free air ball is formed at an end of a reserve wire, the capillary may press down the free air ball to a center of the first pad115using a ball bonding method. A position of the capillary when the ball part11and the neck part13are completely formed using the ball bonding method is marked with the point “a”, and a moving path of the capillary is represented with the points “a,” “b,” “c,” “d,” “e,” “f” and “g.”

In a first movement from the point “a” to the point “b”, the ball part11and the neck part13may be formed on the top surface of the first pad115. The first movement may refer to a movement of the capillary traveling up perpendicular to the top surface of the first pad115and may correspond to the description made above with reference toFIG.4C.

In a second movement from the point “b” to the point “c”, a portion of the top surface of the neck part13may be formed substantially flat and exposed. The second movement may refer to a movement of the capillary traveling toward the second pad215in parallel with the top surface of the first pad115and may correspond to the description made above with reference toFIG.4D.

In a third movement from the point “c” to the point “d”, a wire part may be pressed down with the capillary such that a V-shaped pressed region may be formed in the wire part connected to the neck part13. The third movement may refer to a movement of the capillary traveling down perpendicular to the top surface of the first pad115and may correspond to the description made above with reference toFIG.4E.

In a fourth movement from the point “d” to the point “e”, the wire part may be elongated. The fourth movement may refer to a movement of the capillary traveling up perpendicular to the top surface of the first pad115and may correspond to the description made above with reference toFIG.4F.

In a fifth movement from the point “e” to the point “f”, the wire part may slide toward the second pad215along the curvature path of the capillary and land on the second pad215. The fifth movement may refer to a movement of the capillary traveling along the curvature path from the top surface of the first pad115to a center of the second pad215and may correspond to the description made above with reference toFIG.4G.

In a sixth movement from the point “f” to the point “g”, the reserve wire is cut off forming a stitch part, so that a bonding wire electrically connecting the first pad115and the second pad215to each other may be formed. The sixth movement may refer to a movement of the capillary traveling up perpendicular to the top surface of the second pad215and may correspond to the description made above with reference toFIG.4H.

In a wire bonding method according to example embodiments, the continuous first through sixth movements of the capillary from the point “a” to the point “b” to the point “c” to the point “d” to the point “e” to the point “e” to the point “f” to the point “g” may progress in a direction from the first pad115toward the second pad215but not in a reverse direction.

Consequently, because the capillary moves only forward horizontally from the center of the first pad115to the center of the second pad215but not in the reverse direction, the product and process efficiencies of a bonding wire may be increased.

FIGS.6A and6Bare cross-sectional views of some stages in a wire bonding method, according to some example embodiments.

In detail, an example of a method of manufacturing the bonding wire20according to the example embodiment described above with reference toFIGS.2A and2Bwill be described.

FIG.6Acorresponds to the stage described above with reference toFIG.4D.FIG.6Bcorresponds to the stage described above with reference toFIG.4E. The method of manufacturing the bonding wire20is the same as or similar to the wire bonding method described above with reference toFIGS.4A,4B,4C,4D,4E,4F,4G and4H, the description below will focus on the differences between the methods.

Referring toFIG.6A, the capillary CA may be moved in parallel with the top surface of the first pad115toward the second pad215such that the top surface23T of the neck part23may be entirely exposed, not covered by a reserve wire20P.

The capillary CA may be horizontally moved toward the second pad215by a second distance D2′ from the center of the neck part23. The second distance D2′ may be greater than the second distance D2described above with reference toFIG.4D. The second distance D2′ may be about 35 μm to about 45 μm but is not limited thereto.

In some example embodiments, the capillary CA may be horizontally moved in a state where the top surface23T of the neck part23is at the same level as the bottom surface of the capillary CA.

In this case, the top surface23T of the neck part23may not be in contact with the reserve wire20P, but the side surface of the neck part23may be in contact with the reserve wire20P. In other words, the bottom surface of the capillary CA may push all of the reserve wire20P, which contacts the top surface23T of the neck part23, toward the second pad215so that all of the top surface23T of the neck part23may be exposed.

Referring toFIG.6B, the capillary CA may be moved down perpendicular to the top surface of the first pad115such that the capillary CA may press down the wire part25, thereby forming the pressed region25P having a V-shape in the wire part25that is connected to the neck part23.

The pressed region25P may be formed by applying a mechanical force to the wire part25using the capillary CA. The capillary CA may be moved down perpendicular to the top surface of the first pad115by the third distance D3from the top surface23T of the neck part23. The third distance D3may be about 20 μm to about 30 μm but is not limited thereto.

In some example embodiments, the pressed region25P may be formed using the capillary CA such that the wire part25may be in contact with the neck part23, the ball part21, and the first pad115. In detail, the wire part25may be in contact with the side surface of the neck part23, the top and side surfaces of the ball part21, and the top surface of the first pad115.

In some example embodiments, a sunken point25V of the pressed region25P may be in a region in which the wire part25is in contact with the top surface of the first pad115. In addition, the level of the sunken point25V of the pressed region25P may be lower than the level of the top surface23T of the neck part23.

Consequently, according to the current example embodiments, the wire bonding method may decrease the loop height of the bonding wire20and secure the reliability of a strong connection structure. Accordingly, the total thickness of the semiconductor package200(seeFIG.2A) including the bonding wire20may be decreased, so that the semiconductor package200that is short, small and lightweight, and has a high degree of integration and a high capacity may be realized.

FIG.7is a plan view of a semiconductor module including a semiconductor package, according to an example embodiment.

Referring toFIG.7, a semiconductor module1000may include a module board1010, a control chip1020mounted on the module board1010, and a plurality of semiconductor packages1030mounted on the module board1010.

A plurality of input/output terminals1050, which may be inserted into a socket of a main board, may be arranged at a side of the module board1010. At least one of the semiconductor packages1030may include any of the semiconductor packages100and200described with reference toFIGS.1A,1B,1C,1D,2A and2B.

FIG.8is a block diagram of a system of a semiconductor package, according to an example embodiment.

Referring toFIG.8, a system1100may include a controller1110, an input/output device1120, a memory1130, an interface1140, and a bus1150.

The system1100may transmit or receive information. The system1100may be a mobile system. In some example embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

The controller1110may control an executable program in the system1100. The controller1110may include a microprocessor, a digital signal processor, a microcontroller, or a device similar thereto.

The input/output device1120may be used to input or output data of the system1100. The system1100may be connected to an external device, e.g., a personal computer or a network, via the input/output device1120and may exchange data with the external device. The input/output device1120may include, for example, a touch pad, a keyboard, or a display.

The memory1130may store data for operation of the controller1110or data processed by the controller1110. The memory1130may include any of the semiconductor packages100and200described with reference toFIGS.1A,1B,1C,1D,2A and2B.

The interface1140may be a data transmission path between the system1100and an external device. The controller1110, the input/output device1120, the memory1130, and the interface1140may communicate with one another via the bus1150.

While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.