Patent ID: 12230682

DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the drawings, and repeated descriptions thereof are omitted.

FIG.1is a plan layout diagram of an integrated circuit (IC) device100according to example embodiments.FIG.2Ais a cross-sectional view of some components corresponding to cross-sections taken along lines X1-X1′ and X2-X2′ ofFIG.1.FIG.2Bis a cross-sectional view of some components corresponding to a cross-section taken along line Y1-Y1′ ofFIG.1.FIG.2Cis an enlarged cross-sectional view of region EX1ofFIG.2A.

Referring toFIGS.1and2A to2C, the IC device100may include a logic cell including a fin field-effect transistor (FinFET) device. The IC device100may include a logic cell LC formed in a region defined by a cell boundary BN on a substrate110.

The substrate110may have a main surface110M, which extends in a lateral direction (a direction of an X-Y plane). The substrate110may include a semiconductor (e.g., silicon (Si) or germanium (Ge)) or a compound semiconductor (e.g., silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). The substrate110may include a conductive region, for example, a doped well or a doped structure.

The logic cell LC may include a first device region RX1and a second device region RX2. A plurality of fin-type active regions FA may be in each of the first device region RX1and the second device region RX2and protrude from the substrate110. The plurality of fin-type active regions FA may extend parallel to each other in a widthwise direction of the logic cell LC (i.e., a first lateral direction (X direction)).

As shown inFIG.2B, a device isolation film112may be on the substrate110in the first device region RX1and the second device region RX2. The device isolation film112may be between the plurality of fin-type active regions FA and cover a lower sidewall of each of the fin-type active regions FA. In the first device region RX1and the second device region RX2, each of the plurality of fin-type active regions FA may protrude as a fin type over the device isolation film112. An inter-device isolation region DTA may be between the first device region RX1and the second device region RX2. A deep trench DT may be formed in the inter-device isolation region DTA to define the first device region RX1and the second device region RX2. The deep trench DT may be filled with an inter-device isolation insulating film114. Each of the device isolation film112and the inter-device isolation insulating film114may include an oxide film

On the substrate110, a plurality of gate insulating films132and a plurality of gate lines GL may extend in a height direction (i.e., a second lateral direction (Y direction)) of the logic cell LC, which is a direction intersecting with the plurality of fin-type active regions FA. The plurality of gate insulating films132and the plurality of gate lines GL may cover a top surface and both sidewalls of each of the plurality of fin-type active regions FA, a top surface of the device isolation film112, and a top surface of the inter-device isolation insulating film114.

A plurality of metal-oxide-semiconductor (MOS) transistors may be formed along the plurality of gate lines GL in the first device region RX1and the second device region RX2. Each of the plurality of MOS transistors may be a MOS transistor having a three-dimensional (3D) structure in which a channel is formed in the top surface and the both sidewalls of one of the plurality of fin-type active regions FA. In example embodiments, the first device region RX1may be an NMOS transistor region, and a plurality of NMOS transistors may be formed at intersections between the fin-type active regions FA and the gate lines GL in the first device region RX1. The second device region RX2may be a PMOS transistor region, and a plurality of PMOS transistors may be formed at intersections between the fin-type active regions FA and the gate lines GL in the second device region RX2.

A dummy gate line DGL may extend along a portion of the cell boundary BN, which extends in the second lateral direction (Y direction). The dummy gate line DGL may include the same material as the plurality of gate lines GL. The dummy gate line DGL may be maintained in an electrical floating state during an operation of the IC device100and function as an electrical isolation region between the logic cell LC and other logic cell adjacent thereto. The plurality of gate lines GL and a plurality of dummy gate lines DGL may each have the same width in the first lateral direction (X direction) and be arranged at a constant pitch in the first lateral direction (X direction).

The plurality of gate insulating films132may include a silicon oxide film, a high-k dielectric film, or a combination thereof. The high-k dielectric film may include a material having a higher dielectric constant than a silicon oxide film. The high-k dielectric film may include a metal oxide or a metal oxynitride. An interface film (not shown) may be between the fin-type active region FA and the gate insulating film132. The interface film may include an oxide film, a nitride film, or an oxynitride film.

Each of the plurality of gate lines GL and the plurality of dummy gate lines DGL may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal film are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal selected from titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), and hafnium (Hf). The gap-fill metal film may include a tungsten (W) film or an aluminum (Al) film. Each of the plurality of gate lines GL and a plurality of dummy gate lines DGL may include a work-function metal-containing film. The work-function metal-containing film may include at least one metal selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). In example embodiments, each of the plurality of gate lines GL and the plurality of dummy gate lines DGL may include a stack structure of TiAlC/TiN/W, a stack structure of TiN/TaN/TiAlC/TiN/W, or a stack structure of TiN/TaN/TiN/TiAlC/TiN/W, without being limited thereto.

A plurality of insulating spacers120may cover sidewalls of the plurality of gate lines GL and the plurality of dummy gate lines DGL, respectively. The plurality of gate lines GL, the plurality of dummy gate lines DGL, the plurality of gate insulating films132, and the plurality of insulating spacers120may be covered by insulating capping lines140. Each of the insulating capping lines140and the plurality of insulating spacers120may extend in a line shape in the second lateral direction (Y direction).

Each of the plurality of insulating spacers120may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), or a combination thereof, without being limited thereto. A combination may include any number of the listed materials and may not include some of the listed materials. The plurality of insulating capping lines140may include silicon nitride (SiN). As used herein, each of the terms “SiN,” “SiCN,” “SiBN,” “SiON,” “SiOCN,” and “SiBCN” refers to a material including elements included therein, without referring to a chemical formula representing a stoichiometric relationship.

The plurality of recess regions RR may be formed in the top surfaces of the plurality of fin-type active regions FA, respectively. The plurality of gate lines GL may include a pair of gate lines GL, which are adjacent to one recess region RR and apart from each other with the one recess region RR therebetween. The plurality of source/drain regions130may be inside the plurality of recess regions RR. At least some of the plurality of source/drain regions130may be between a pair of gate lines GL. The gate line GL may be apart from the source/drain region130with the gate insulating film132and the insulating spacer120therebetween.

The plurality of source/drain regions130may include an epitaxial semiconductor layer epitaxially grown from the plurality of recess regions RR. For example, the plurality of source/drain regions130may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or a plurality of epitaxially grown SiGe layers. When the first device region RX1may be an NMOS transistor region and the second device region RX2may be a PMOS transistor region, the plurality of source/drain regions130in the first device region RX1may include a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant, and the plurality of source/drain regions130in the second device region RX2may include a SiGe layer doped with a p-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). The p-type dopant may be selected from boron (B) and gallium (Ga).

In example embodiments, the plurality of source/drain regions130in the first device region RX1may have a different shape and a different size from the plurality of source/drain regions130in the second device region RX2. A shape of each of the plurality of source/drain regions130is not limited to that shown inFIGS.2A and2C. A plurality of source/drain regions130having various shapes and sizes may be formed in the first device region RX1and the second device region RX2.

As shown inFIG.2C, a recess surface130R may be formed in the top surface of each of the plurality of source/drain regions130. The plurality of metal silicide films152may be along the recess surfaces130R of the plurality of source/drain regions130on the plurality of source/drain regions130, respectively. Each of the plurality of metal silicide films152may cover the top surface of the source/drain region130. Each of the plurality of source/drain regions130and the plurality of metal silicide films152may constitute a conductive region.

Each of the plurality of metal silicide films152may include a first metal. In example embodiments, the first metal may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film152may include titanium silicide, without being limited thereto.

An insulating liner146and an inter-gate dielectric film148may be sequentially on the plurality of source/drain regions130and the plurality of metal silicide films152. The insulating liner146and the inter-gate dielectric film148may constitute a lower insulating structure. In example embodiments, the insulating liner146may include SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, without being limited thereto. The inter-gate dielectric film148may include a silicon oxide film, without being limited thereto.

Each of a plurality of source/drain contacts CA may pass through the inter-gate dielectric film148and the insulating liner146in a vertical direction (Z direction) and be connected to the source/drain region130through the metal silicide film152. Each of the plurality of source/drain contacts CA may be apart from the gate line GL with the insulating spacer120therebetween in the first lateral direction (X direction). Each of the plurality of source/drain regions130may be connected to an upper conductive line through the metal silicide film152and the source/drain contact CA.

Each of the plurality of source/drain contacts CA may include a conductive barrier pattern154and a conductive plug156(first conductive plug), which are sequentially stacked on the metal silicide film152.

The conductive plug156may pass through the inter-gate dielectric film148and the insulating liner146and extend long in the vertical direction (Z direction). The conductive barrier pattern154may be between the metal silicide film152and the conductive plug156. The conductive barrier pattern154may include a surface in contact with the metal silicide film152and a surface in contact with the conductive plug156. A bottom surface and a lower sidewall of the conductive plug156may be in contact with the conductive barrier pattern154, and an upper sidewall of the conductive plug156may be in contact with the lower insulating structure including the insulating liner146and the inter-gate dielectric film148.

The conductive plug156may include a second metal. The conductive barrier pattern154may include a third metal. In example embodiments, the first metal included in the metal silicide film152, the second metal included in the conductive plug156, and the third metal included in the conductive barrier pattern154may respectively include different elements. In other example embodiments, some of the first metal, the second metal, and the third metal may include different elements. In still other example embodiments, at least some of the first metal, the second metal, and the third metal may include the same element.

As an example, the second metal may include a different element from the first metal included in the metal silicide film152. As another example, the first metal and the second metal may include the same element. As still another example, the first metal and the third metal may include different elements. As yet another example, the first metal and the third metal may include the same element. In example embodiments, when the first metal included in the metal silicide film152includes a different element from the second metal included in the conductive plug156, because the conductive pattern154is between the metal silicide film152and the conductive plug156, the intermixing of metal atoms between the metal silicide film152and the conductive plug156may be blocked by the conductive barrier pattern154.

In example embodiments, the second metal may include a metal solely including one element selected from molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), and aluminum (Al) or include a metal including a combination thereof, without being limited thereto. The conductive barrier pattern154may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), or a combination thereof, without being limited thereto.

As shown inFIGS.2A and2C, the conductive barrier pattern154may have a variable thickness according to a position thereof. The conductive barrier pattern154may include a vertical barrier portion154V. The vertical barrier portion154V may include a portion between the metal silicide film152and the conductive plug156and a portion between the conductive plug156and the lower insulating structure including the insulating liner146and the inter-gate dielectric film148. The vertical barrier portion154V may have a shape of which a width may be gradually reduced in the lateral direction (e.g., X direction) in a direction away from the substrate110or the metal silicide film152. Restated, the vertical barrier portion154V may have the width in a lateral direction that tapers along a direction away from the substrate110or the metal silicide film152. In example embodiments, the vertical barrier portion154V of the conductive barrier pattern154may have a ring shape surrounding the conductive plug156in a view from above (e.g., on an X-Y plane).

A surface of the conductive barrier pattern154, which may be in contact with the metal silicide film152, may have a convex shape toward the substrate110, and a surface of the conductive barrier pattern154, which may be in contact with the conductive plug156, may have a concave shape toward the conductive plug156. A width of a lower portion of the conductive plug156in a lateral direction (e.g., X direction) may be defined by the vertical barrier portion154V of the conductive barrier pattern154, and a width of an upper portion of the conductive plug156in the lateral direction (e.g., X direction) may be defined by the lower insulating structure including the insulating liner146and the inter-gate dielectric film148.

As shown inFIG.2C, the vertical barrier portion154V of the conductive barrier pattern154may have a tapered surface154T facing the conductive plug156. The distance between the tapered surface154T and the lower insulating structure including the insulating liner146and the inter-gate dielectric film148may decrease along a direction away from the substrate110or the metal silicide film152in the vertical direction (Z direction) or a direction away from the substrate110or the metal silicide film152. For example, a distance between the tapered surface154T and the inter-gate dielectric film148in the lateral direction may be gradually reduced in a direction away from the metal silicide film152in the vertical direction (Z direction).

In example embodiments, the conductive barrier pattern154may have a thickness greater than 0 nm and equal to or less than 1 nm between the metal silicide film152and the conductive plug156. A thickness of the vertical barrier portion154V of the conductive barrier pattern154may be gradually reduced within a range of about 1 nm or less in a direction away from the metal silicide film152in the vertical direction (Z direction).

The IC device100may include an insulating film149, which covers the top surface of each of the plurality of source/drain contacts CA and a top surface of each of the plurality of insulating capping lines140. Each of the plurality of source/drain contacts CA may be inside a source/drain contact hole CAH, which passes through the insulating film149in the vertical direction (Z direction). The upper sidewall of the conductive plug156included in each of the plurality of source/drain contacts CA may be in contact with the insulating film149. The insulating film149may constitute a middle insulating structure. In example embodiments, the insulating film149may include silicon oxide film, without being limited thereto.

As shown inFIGS.2A and2B, a top surface of the insulating film149and the top surface of each of the plurality of source/drain contacts CA may be covered by an upper insulating structure180. The upper insulating structure180may include an etch stop film182and an interlayer insulating film184, which are sequentially stacked on the plurality of source/drain contacts CA and the insulating film149. The etch stop film182may include silicon carbide (SiC), silicon nitride (SiN), nitrogen (N)-doped silicon carbide (SiC:N), silicon oxycarbide (SiOC), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), aluminum oxycarbide (AlOC), or a combination thereof. The interlayer insulating film184may include an oxide film, a nitride film, an ultralow-k (ULK) film having a ultralow dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating film184may include a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) oxide film, a boro-phospho-silicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, without being limited thereto.

As shown inFIGS.1and2A, a plurality of via contacts CAV may be on the plurality of source/drain contacts CA. Each of the plurality of via contacts CAV may pass through the upper insulating structure180and be in contact with the conductive plug156of the source/drain contact CA. The plurality of via contacts CAV may constitute an upper wiring structure.

In example embodiments, the plurality of via contacts CAV may include a fourth metal. The fourth metal may include the same element as the second metal included in the conductive plug156. For example, each of a plurality of conductive plugs156and the plurality of via contacts CAV may include molybdenum. In other example embodiments, the fourth metal may include a different element from the second metal included in the conductive plug156.

In example embodiments, bottom surfaces of the plurality of via contacts CAV may be in contact with top surfaces of the conductive plugs156, respectively. Each of the plurality of via contacts CAV may include an upper conductive plug, which may be in direct contact with the conductive plug156without passing through a separate conductive barrier film. In a case where the via contact CAV and the conductive plug156include the same metal, even when the intermixing of metal atoms occurs between the via contact CAV and the conductive plug156, the intermixing phenomenon may not affect the electrical characteristics of the IC device100. Accordingly, a separate conductive barrier film configured to block the intermixing phenomenon may not be between the conductive plug156and the via contact CAV.

In example embodiments, the upper conductive plug156may include a metal solely including one element selected from molybdenum, copper, tungsten, cobalt, ruthenium, manganese, titanium, tantalum, and aluminum or include a metal including a combination thereof, without being limited thereto. For example, the upper conductive plug156included in each of the plurality of via contacts CAV may include molybdenum.

As shown inFIGS.1and2B, a plurality of gate contacts CB may be on the plurality of gate lines GL. Each of the plurality of gate contacts CB may pass through the upper insulating structure180, the insulating film149, and the insulating capping line140and be in contact with a top surface of the gate line GL. Each of the plurality of gate lines GL may be connected to the upper conductive line through the gate contact CB.

As shown inFIG.2B, the gate contact CB may include a conductive barrier pattern194and a conductive plug196, which are sequentially stacked on the gate line GL. The conductive barrier pattern194may include a vertical barrier portion194V between an insulating structure including the insulating capping line140and the insulating film149and the conductive plug196. The vertical barrier portion194V may have a shape of which a width may be gradually reduced in a lateral direction (e.g., X direction) in a direction away from the substrate110or the gate line GL. Restated, the width may taper along a direction away from the substrate110or the gate line GL. In example embodiments, the vertical barrier portion194V of the conductive barrier pattern194may have a ring shape surrounding the conductive plug196in a view from above (e.g., on an X-Y plane).

The vertical barrier portion194V of the conductive barrier pattern194may have a tapered surface194T facing the conductive plug196. The distance between the tapered surface194T and the insulating structure including the insulating capping line140and the insulating film149may decrease along a direction away from the substrate110or the gate line GL in the vertical direction (Z direction) or a direction away from the substrate110or the gate line GL. For example, a distance between the tapered surface194T and the insulating capping line140in the lateral direction may be gradually reduced in a direction away from the gate line GL in the vertical direction (Z direction). Detailed configurations and effects of the conductive barrier pattern194and the conductive plug196may be substantially the same as those of the conductive barrier pattern154and the conductive plug156of the source/drain contact CA, which have been described with reference toFIGS.1and2A to2C.

As shown inFIG.1, in the logic cell LC, a ground line VSS may be connected to the fin-type active region FA in the first device region RX1through one of the plurality of source/drain contacts CA, which is in the first device region RX1. A power line VDD may be connected to the fin-type active region FA in the second device region RX2through one of the plurality of source/drain contacts CA, which is in the second device region RX2. The ground line VSS and the power line VDD may be formed at a higher level than the top surface of each of the plurality of source/drain contacts CA and the plurality of gate contacts CB.

In example embodiments, the ground line VSS and the power line VDD may include a conductive barrier pattern and a wiring conductive layer, respectively. The conductive barrier pattern and the wiring conductive layer, which are respectively included in the ground line VSS and the power line VDD, may have substantially the same configurations as the conductive barrier pattern154and the conductive plug156of the source/drain contact CA, which have been described above.

In the IC device100shown inFIGS.1and2A to2C, the plurality of source/drain contacts CA may include the conductive barrier pattern154and the conductive plug156, and the gate contact CB may include the conductive barrier pattern194and the conductive plug196. The conductive barrier patterns154and194may be in contact with the bottom surfaces and the lower surfaces of the conductive plugs156and196without being in contact with the upper sidewalls of the conductive plugs156and196. Accordingly, portions of the plurality of source/drain contacts CA and the gate contact CB, which are taken up by the conductive barrier patterns154and194, may be minimized Thus, increases in resistances due to the conductive barrier patterns154and194may be minimized in the plurality of source/drain contacts CA4and the gate contact CB4. In addition, because an upper space of the source/drain contact hole CAH in which the source/drain contact CA is contained and an upper space of a gate contact hole CBH in which the gate contact CB is contained are not taken up by the conductive barrier patterns154and194, an upper inner space of each of the source/drain contact hole CAH and the gate contact hole CBH may widen, and thus, gap-fill characteristics may be improved during the formation of the source/drain contact CA and the gate contact CB. Thus, undesired defects (e.g., voids) may be prevented from being generated in the source/drain contact hole CAH and the gate contact hole CBH, and the conductive plugs156and196including a high-quality metal-containing film may be obtained. Accordingly, even when the IC device100has a device region having a reduced area due to the downscaling of IC devices, the electrical characteristics and reliability of the IC device100may be improved while reducing a contact resistance of each of the source/drain contact CA and the gate contact CB.

FIG.3is a cross-sectional view of an IC device200according to example embodiments.FIG.3illustrates a cross-sectional configuration of regions of the IC device200, which correspond to a cross-section taken along lines X1-X1′ and X2-X2′ ofFIG.1. InFIG.3, the same reference numerals are used to denote the same elements as inFIGS.2A to2C, and detailed descriptions thereof are omitted.

Referring toFIG.3, the IC device200may have substantially the same configuration as the IC device100described with reference toFIGS.1and2A to2C. However, the IC device200may include a plurality of via contacts CAV2instead of the plurality of via contacts CAV.

Each of the plurality of via contacts CAV2may pass through an upper insulating structure180and be in contact with a conductive plug156of a source/drain contact CA. The plurality of via contacts CAV2may constitute an upper wiring structure.

Each of the plurality of via contacts CAV2may include an upper conductive barrier pattern274and an upper conductive plug276, which are sequentially stacked on the conducive plug156of the source/drain contact CA. In each of the plurality of via contacts CAV2, a bottom surface and a lower sidewall of the upper conductive plug276may be in contact with the upper conductive barrier pattern274, and an upper sidewall of the upper conductive plug276may be in contact with the upper insulating structure180.

The upper conductive barrier pattern274may include an upper conductive line274V between the upper insulating structure180and the upper conductive plug276. The upper conductive line274V may have a shape of which a width is gradually reduced in a lateral direction (e.g., X direction) in a direction away from the conductive plug156of the source/drain contact CA. In example embodiments, the upper conductive line274V of the upper conductive barrier pattern274may have a ring shape surrounding the upper conductive plug276in a view from above (e.g., on an X-Y plane). Detailed configurations and effects of the upper conductive barrier pattern274and the upper conductive plug276may be substantially the same as those of the conductive barrier pattern154and the conductive plug156of the source/drain contact CA, which have been described with reference toFIGS.1and2A to2C.

FIG.4is a cross-sectional view of main components of an IC device300A according to example embodiments.

Referring toFIG.4, the IC device300A may include a lower structure310. The lower structure310may include a semiconductor substrate including a semiconductor (e.g., Si or Ge) or a compound semiconductor (e.g., SiGe, SiC, GaAs, InAs, or InP). The lower structure310may include a conductive region (not shown). The conductive region may include a doped well, a doped structure, or conductive layer. In example embodiments, the lower structure310may include circuit elements (not shown), such as a gate structure, an impurity region, and a contact plug. For example, the lower structure310may include structures of the IC device100, which are described with reference toFIGS.1and2A to2C, or structures of the IC device200, which are described with reference toFIG.3.

A first etch stop film312and a lower insulating film314may be sequentially stacked on the lower structure310, and a lower wiring structure320may pass through the lower insulating film314and the first etch stop film312and be on the lower structure310.

The first etch stop film312may include a material having an etch selectivity with respect to the lower insulating film314. In example embodiments, the first etch stop film312may include a silicon nitride film, a carbon-doped silicon nitride film, or a carbon-doped silicon oxynitride film. In other example embodiments, the first etch stop film312may include a metal nitride film, for example, an aluminum nitride (AlN) film. In example embodiments, the lower insulating film314may include a silicon oxide film. For example, the lower insulating film314may include a silicon oxide-based material, such as plasma-enhanced oxide (PEOX), TEOS, boro TEOS (BTEOS), phosphorous TEOS (PTEOS), boro phospho TESO (BPTEOS), boro silicate glass (BSG), phospho silicate glass (PSG), and BPSG. In other example embodiments, the lower insulating film314may have a low-k dielectric film (e.g., a SiOC film or a SiCOH film) having a low dielectric constant K of about 2.2 to about 3.0. The lower wiring structure320may include a metal film and a conductive barrier film surrounding the metal film. The metal film may include molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), or cobalt (Co). The conductive barrier film may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof. In example embodiments, the lower wiring structure320may be electrically connected to the conductive region formed in the lower structure310. In some other example embodiments, the lower wiring structure320may be connected to a source/drain region (not shown) or a gate electrode (not shown) of a transistor formed in the lower structure310.

A second etch stop film322and a first insulating film324may be sequentially arranged on the lower insulating film314. A first metal wiring structure ML1may pass through an insulating structure including the first insulating film324and the second etch stop film322and extend to the lower wiring structure320.

The first metal wiring structure ML1may include a lower conductive barrier pattern334and a lower conductive line336, which are sequentially stacked on the lower wiring structure320. The lower conductive line336may include a plug-shaped portion adjacent to the lower wiring structure320and a line-shaped portion integrally connected to the plug-shaped portion. The line-shaped portion of the lower conductive line336may be apart from the lower conductive barrier pattern334with the plug-shaped portion therebetween.

In the first metal wiring structure ML1, a bottom surface and a lower sidewall of the plug-shaped portion of the lower conductive line336may be in contact with the lower conductive barrier pattern334, and an upper sidewall of the plug-shaped portion of the lower conductive line336may be in contact with the first insulating film324. An outer surface of the line-shaped portion of the lower conductive line336may be in contact with the first insulating film324.

The lower conductive barrier pattern334may include a vertical barrier portion334V between the lower conductive line336and the insulating structure including the second etch stop film322and the first insulating film324. The vertical barrier portion334V may have a shape of which a width is gradually reduced in a lateral direction (e.g., X direction) in a direction away from the lower wiring structure320. In example embodiments, the vertical barrier portion334V of the lower conductive barrier pattern334may have a ring shape surrounding the lower conductive line336in a view from above (e.g., on an X-Y plane). Detailed configurations and effects of the lower conductive barrier pattern334and the lower conductive line336may be substantially the same as those of the conductive barrier pattern154and the conductive plug156of the source/drain contact CA, which have been described with reference toFIGS.1and2A to2C.

The IC device300A may include an insulating capping layer350, which covers a top surface of each of the first metal wiring structure ML1and the first insulating film324. In example embodiments, the insulating capping layer350may include a multilayered structure including a first insulating capping layer352including a metal and a second insulating capping layer354that is free of a metal. In example embodiments, the first insulating capping layer352may include AlN, AlON, AlO, or AlOC, and the second insulating capping layer354may include SiC, SiN, SiC:N, or SiOC, without being limited thereto. In example embodiments, any one of the first insulating capping layer352and the second insulating capping layer354may be omitted from the insulating capping layer350.

The insulating capping layer350may be covered by a second insulating film356. A second metal wiring structure ML2may pass through an insulating structure including the insulating capping layer350and the second insulating film356and be connected to the first metal wiring structure ML1. A constituent material of the second insulating film356may be the same as that of the lower insulating film314described above.

The second metal wiring structure ML2may be in contact with a top surface of the lower conductive line336. The second metal wiring structure ML2may include an upper wiring366, which is in direct contact with the lower conductive line336of the first metal wiring structure ML1without passing through a separate conductive barrier film. In example embodiments, the upper wiring366may include a metal solely including one element selected from molybdenum, copper, tungsten, cobalt, ruthenium, manganese, titanium, tantalum, and aluminum or include a metal including a combination thereof, without being limited thereto. In example embodiments, the lower conductive line336of the first metal wiring structure ML1may include the same metal as the upper wiring366included in the second metal wiring structure ML2. For example, each of the lower conductive line336of the first metal wiring structure ML1and the upper wiring366included in the second metal wiring structure ML2may include molybdenum (Mo), without being limited thereto.

FIG.5is a cross-sectional view of an IC device300B according to example embodiments. InFIG.5, the same reference numerals are used to denote the same elements as inFIG.4, and detailed descriptions thereof are omitted.

Referring toFIG.5, the IC device300B may have substantially the same configuration as the IC device300A described with reference toFIG.4. However, the IC device300B may include a second metal wiring structure ML2A instead of the second metal wiring structure ML2.

The second metal wiring structure ML2A may pass through an insulating structure including an insulating capping layer350and a second insulating film356and be connected to a first metal wiring structure ML1. The second metal wiring structure ML2A may constitute an upper wiring structure.

The second metal wiring structure ML2A may include an upper conductive barrier pattern374and an upper conductive line376, which are sequentially stacked on a lower conductive line336of the first metal wiring structure ML1. The upper conductive line376may include a plug-shaped portion adjacent to the first metal wiring structure ML1and a line-shaped portion integrally connected to the plug-shaped portion. The line-shaped portion may be apart from the upper conductive barrier pattern374with the plug-shaped portion therebetween.

In example embodiments, a line-shaped portion included in the lower conductive line336may extend long in a first lateral direction (X direction), and the line-shaped portion included in the upper conductive line376may extend long in a second lateral direction (Y direction), which intersects with the first lateral direction (X direction).

In the second metal wiring structure ML2A, a bottom surface and a lower sidewall of the plug-shaped portion of the upper conductive line376may be in contact with the upper conductive barrier pattern374, and an upper sidewall of the plug-shaped portion of the upper conductive line376may be in contact with the second insulating film356. An outer surface of the line-shaped portion of the upper conductive line376may be in contact with the second insulating film356.

The upper conductive barrier pattern374may include an upper vertical barrier portion374V between the upper conductive line376and the insulating structure including the insulating capping layer350and the second insulating film356. The upper vertical barrier portion374V may have a shape of which a width is gradually reduced in a lateral direction (e.g., X direction) in a direction away from the first metal wiring structure ML1. In example embodiments, the upper vertical barrier portion374V may have a ring shape surrounding the upper conductive line376in a view from above (e.g., on an X-Y plane). Detailed configurations and effects of the upper conductive barrier pattern374and the upper conductive line376may be substantially the same as those of the conductive barrier pattern154and the conductive plug156of the source/drain contact CA, which have been described with reference toFIGS.1and2A to2C.

FIG.6is a plan layout diagram of some components of an IC device400according to example embodiments.FIG.7Ais a cross-sectional view taken along line X4-X4′ ofFIG.6.FIG.7Bis a cross-sectional view taken along line Y4-Y4′ ofFIG.6.

Referring toFIGS.6,7A, and7B, the IC device400may include a plurality of fin-type active regions F4and a plurality of nanosheet stacks NSS. The plurality of fin-type active regions F4may protrude from a substrate402and extend long in a first lateral direction (X direction). The plurality of nanosheet stacks NSS may be apart upward from the plurality of fin-type active regions F4in a vertical direction (Z direction) and face top surfaces FT4of the plurality of fin-type active regions F4. As used herein, the term “nanosheet” refers to a conductive structure having a cross-section that is substantially perpendicular to a direction in which current flows. The nanosheet should be interpreted as including a nanowire.

Trenches T4may be formed in the substrate402to define the plurality of fin-type active regions F4, and then filled with a device isolation film412. The substrate402, the plurality of fin-type active regions F4, and the device isolation film412may respectively have substantially the same configurations as the substrate110, the fin-type active region FA, and the device isolation film112described with reference toFIGS.2A to2C.

A plurality of gate lines460may extend on the plurality of fin-type active regions F4in the second lateral direction (Y direction). The plurality of nanosheet stacks NSS may be respectively on the top surfaces FT4of the plurality of fin-type active regions F4in regions where the plurality of fin-type active regions F4intersect with the plurality of gate lines460. Also, the plurality of nanosheet stacks NSS may be apart from the fin-type active regions F4and face the top surfaces FT4of the fin-type active regions F4. On the substrate402, a plurality of nanosheet transistors may be formed at intersections between the plurality of fin-type active regions F4and the plurality of gate lines460.

Each of the plurality of nanosheet stacks NSS may include a plurality of nanosheets (e.g., N1, N2, and N3), which overlap each other in the vertical direction (Z direction) on the top surface FT4of the fin-type active region F4. The plurality of nanosheets (e.g., N1, N2, and N3) may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3, which are at different vertical distances from the top surface FT4of the fin-type active region F4.

FIG.6illustrates a case in which the nanosheet stack NSS approximately has a rectangular planar shape, without being limited thereto. The nanosheet stack NSS may have various planar shapes according to a planar shape of each of the fin-type active region F4and the gate line460. The present example embodiment pertains to an example configuration in which the plurality of nanosheet stacks NSS and the plurality of gate lines460are formed on one fin-type active region F4, and the plurality of nanosheet stacks NSS are arranged in a line in the first lateral direction (X direction) on one fin-type active region F4. However, according to the inventive concept, the number of nanosheet stacks NSS on one fin-type active region is not specifically limited. For example, one nanosheet stack NSS may be formed on one fin-type active region F4. The present example embodiment pertains to a case in which each of the plurality of nanosheet stacks NSS includes three nanosheets, but the inventive concept is not limited thereto. For example, the nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets included in the nanosheet stack NSS is not specifically limited.

Each of the first to third nanosheets N1, N2, and N3may have a channel region. In example embodiments, each of the first to third nanosheets N1, N2, and N3may include a Si layer, a SiGe layer, or a combination thereof.

A plurality of recess regions R4may be formed in an upper portion of the fin-type active region F4, and a plurality of source/drain regions430may be on the plurality of recess regions R4. The plurality of source/drain regions430may include an epitaxial semiconductor layer. A detailed configuration of the plurality of source/drain regions430may be the same as that of the source/drain regions130described with reference toFIGS.2A and2C.

The gate line460may surround each of the first to third nanosheets N1, N2, and N3and cover the nanosheet stack NSS on the fin-type active region F4. Each of the plurality of gate lines460may include a main gate portion460M and a plurality of sub-gate portions460S. The main gate portion460M may cover a top surface of the nanosheet stack NSS and extend long in the second lateral direction (Y direction). The plurality of sub-gate portions460S may be integrally connected to the main gate portion460M and arranged one by one between the first to third nanosheets N1, N2, and N3and between the fin-type active region F4and the first nanosheet N1. The first to third nanosheets N1, N2, and N3may have a gate-all-around (GAA) structure surrounded by the gate line460. The gate line460may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may include TiAlC. A gate insulating film432may be between the nanosheet stack NSS and the gate line460. The gate insulating film432may have substantially the same configuration as the gate insulating film132described with reference toFIGS.2A to2C.

A metal silicide film452may be formed in a top surface of each of the plurality of source/drain regions430. The metal silicide film452may have substantially the same configuration as the metal silicide film152described with reference toFIGS.2A and2C.

Both sidewalls of the plurality of gate lines460may be respectively covered by a plurality of outer insulating spacers418. The plurality of outer insulating spacers418may cover both sidewalls of the main gate portions460M on the plurality of nanosheet stacks NSS. The plurality of outer insulating spacers418and the plurality of source/drain regions430may be covered by an insulating liner442. Each of the outer insulating spacer418and the insulating liner442may include silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOC), silicon dioxide (SiO2), or a combination thereof. The insulating liner442may be omitted.

A plurality of inner insulating spacers428may be between the first to third nanosheets N1, N2, and N3and between the fin-type active region F4and the first nanosheet N1. Both sidewalls of each of the plurality of sub-gate portions460S may be covered by the inner insulating spacers428with the gate insulating film432therebetween. The plurality of inner insulating spacers428may be between the plurality of sub-gate portions460S and the source/drain region430. In example embodiments, the outer insulating spacer418may include the same insulating material as the inner insulating spacer428. In other example embodiments, the outer insulating spacer418may include a different insulating material from the inner insulating spacer428. The inner insulating spacer428may include SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or a combination thereof. The inner insulating spacer428may further include an air gap. In example embodiments, the plurality of inner insulating spacers428may be omitted. In this case, each of the plurality of source/drain regions430may be in contact with the gate insulating film432, which is between the source/drain region430and the sub-gate portion460S.

The insulating liner442may be covered by an inter-gate dielectric film444. The inter-gate dielectric film444may include a silicon oxide film. A plurality of source/drain contacts CA4may be inside a plurality of source/drain contact holes CAH4, which pass through the inter-gate dielectric film444and the insulating liner442. Each of the plurality of source/drain contacts CA4may be connected to the source/drain region430through the metal silicide film452. Each of the plurality of source/drain contacts CA4may include a conductive barrier pattern454and a conductive plug456, which are sequentially stacked on the metal silicide film452.

The conductive plug456may pass through the inter-gate dielectric film444and the insulating liner442and extend long in the vertical direction (Z direction). The conductive barrier pattern454may be between the metal silicide film452and the conductive plug456. The conductive barrier pattern454may have a surface in contact with the metal silicide film452and a surface in contact with the conductive plug456. A bottom surface and a lower sidewall of the conductive plug456may be in contact with the conductive barrier pattern454, and an upper sidewall of the conductive plug456may be in contact with a lower insulating structure including the insulating liner442and the inter-gate dielectric film444.

As shown inFIG.7A, the conductive barrier pattern454may include a vertical barrier portion454V between the conductive plug456and the lower insulating structure including the insulating liner442and the inter-gate dielectric film444. The vertical barrier portion454V may have a shape of which a width is gradually reduced in a lateral direction (e.g., X direction) in a direction away from the substrate402or the metal silicide film452. In example embodiments, the vertical barrier portion454V of the conductive barrier pattern454may have a ring shape surrounding the conductive plug456in a view from above (e.g., on an X-Y plane).

A surface of the conductive barrier pattern454, which is in contact with the metal silicide film452, may have a convex shape toward the substrate402, and a surface of the conductive barrier pattern454, which is in contact with the conductive plug456, may have a concave shape toward the conductive plug456. A width of a lower portion of the conductive plug456in a lateral direction (e.g., X direction) may be defined by the vertical barrier portion454V of the conductive barrier pattern454, and a width of an upper portion of the conductive plug456in the lateral direction (e.g., X direction) may be defined by the lower insulating structure including the insulating liner442and the inter-gate dielectric film444.

Detailed configurations and effects of the conductive barrier pattern454and the conductive plug456may be substantially the same as those of the conductive barrier pattern154and the conductive plug156of the source/drain contact CA, which have been described with reference toFIGS.1and2A to2C.

Each of the plurality of gate lines460may be covered by an insulating capping line440. The insulating capping line440may have substantially the same configuration as the insulating capping line140described with reference toFIGS.2A to2C.

The IC device400may include an upper insulating structure480, which covers a top surface of each of the plurality of source/drain contacts CA4, a plurality of insulating capping lines440, and the inter-gate dielectric film444. The upper insulating structure480may include an etch stop film482and an interlayer insulating film484, which are sequentially stacked on the source/drain contact CA4and the insulating capping line440. The etch stop film482and the interlayer insulating film484may respectively have substantially the same configuration as the etch stop film182and the interlayer insulating film184, which have been described with reference toFIGS.2A and2B.

As shown inFIG.6, the plurality of via contacts CAV4may be on the plurality of source/drain contacts CA4. Each of the plurality of via contacts CAV4may pass through the upper insulating structure480and be in contact with the top surface of the source/drain contact CA4. In example embodiments, each of the plurality of via contacts CAV4may have substantially the same configuration as each of the plurality of via contacts CAV described with reference toFIG.2A. In other example embodiments, each of the plurality of via contacts CAV4may have substantially the same configuration as each of the plurality of via contacts CAV2described with reference toFIG.3.

As shown inFIGS.6,7A, and7B, a gate contact CB4may be on the gate line460. The gate contact CB4may be within a gate contact hole CBH4, which passes through the upper insulating structure480and the insulating capping line440in the vertical direction (Z direction), and be connected to a top surface of the gate line460.

The gate contact CB4may include a conductive barrier pattern494and a conductive plug496, which are sequentially stacked on the gate line460. The conductive barrier pattern494may include a vertical barrier portion494V between an insulating structure including the insulating capping line440and the conductive plug496. The vertical barrier portion494V may have a shape of which a width is gradually reduced in a lateral direction (e.g., X direction) in a direction away from the substrate402or the gate line460. In example embodiments, the vertical barrier portion494V of the conductive barrier pattern494may have a ring shape surrounding the conductive plug496in a view from above (e.g., on an X-Y plane). Detailed configurations and effects of the conductive barrier pattern494and the conductive plug496may be substantially the same as those of the conductive barrier pattern154and the conductive plug156of the source/drain contact CA, which have been described with reference toFIGS.1and2A to2C.

In the IC device400described with reference toFIGS.6,7A, and7B, the source/drain contact CA4may include the conductive barrier pattern454and the conductive plug456, and the gate contact CB4may include the conductive barrier pattern494and the conductive plug496. The conductive barrier patterns454and494may be in contact with the bottom surfaces and the lower sidewalls of the conductive plugs456and496without being in contact with the upper sidewalls of the conductive plugs456and496. Accordingly, portions of the source/drain contacts CA4and the gate contact CB4, which are taken up by the conductive barrier patterns454and494, may be minimized. Thus, increases in resistances due to the conductive barrier patterns454and494may be minimized in the plurality of source/drain contacts CA4and the gate contact CB4. In addition, because an upper space of the source/drain contact hole CAH4in which the source/drain contact CA4is contained and an upper space of the gate contact hole CBH4in which the gate contact CB4is contained are not taken up by the conductive barrier patterns454and494, an upper inner space of each of the source/drain contact hole CAH4and the gate contact hole CBH4may widen, and thus, gap-fill characteristics may be improved during the formation of the source/drain contact CA4and the gate contact CB4. Thus, undesired defects (e.g., voids) may be prevented from being generated in the source/drain contact hole CAH4and the gate contact hole CBH4, and the conductive plugs456and496including a high-quality metal-containing film may be obtained. Accordingly, even when the IC device400has a device region having a reduced area due to the downscaling of IC devices, the electrical characteristics and reliability of the IC device400may be improved while reducing a contact resistance of each of the source/drain contact CA4and the gate contact CB4.

Hereinafter, a method of manufacturing an IC device according to example embodiments will be described in detail.

FIGS.8A to8Jare cross-sectional views of a process sequence of a method of manufacturing an IC device, according to example embodiments. Specifically,FIGS.8A to8Jare cross-sectional views of partial regions of portions corresponding to a cross-section taken along line X2-X2′ ofFIG.1, according to the process sequence. A method of manufacturing the IC device100shown inFIGS.1and2A to2C, according to an example embodiment, will be described with reference toFIGS.8A to8J. Although a process sequence in a partial region of a second device region RX2is illustrated inFIGS.8A to8J, processes that are the same as or similar to processes described below may be performed also on a first device region RX1. InFIGS.8A to8J, the same reference numerals are used to denote the same elements as inFIGS.1and2A to2C, and detailed descriptions thereof are omitted.

Referring toFIG.8A, partial regions of a substrate110may be etched in the first device region RX1and the second device region RX2(refer toFIGS.1and2A) to form a plurality of fin-type active regions FA, which protrude over a main surface110M of the substrate110upward in a vertical direction (Z direction) and extend parallel to each other in a first lateral direction (X direction). Also, a device isolation film112(refer toFIG.2B) may be formed to cover both lower sidewalls of each of the plurality of fin-type active regions FA. Thereafter, a portion of the device isolation film112and a portion of the substrate110may be etched to form a deep trench DT (refer toFIG.2B) defining the first device region RX1and the second device region RX2, and the deep trench DT may be then filled with an inter-device isolation insulating film114. As shown inFIG.2B, after the deep trench DT is filled with the inter-device isolation insulating film114in the inter-device isolation region DTA, the plurality of fin-type active regions FA may protrude over a top surface of the device isolation film112in the first device region RX1and the second device region RX2.

Referring toFIG.8B, a plurality of dummy gate structures DGS may be formed on the device isolation film112and the inter-device isolation insulating film114(refer toFIG.2B) and extend to intersect with the plurality of fin-type active regions FA. Each of the plurality of dummy gate structures DGS may include a dummy gate insulating film D12, a dummy gate line D14, and a dummy insulating capping layer D16, which are sequentially stacked on a fin top surface FT of each of the plurality of fin-type active regions FA and each of the device isolation film112and the inter-device isolation insulating film114(refer toFIG.2B). The dummy gate insulating film D12may include a silicon oxide film. The dummy gate line D14may include a polysilicon film. The dummy insulating capping layer D16may include a silicon nitride film.

Insulating spacers120may be formed on both sidewalls of the dummy gate structure DGS, and portions of the plurality of fin-type active regions FA, which are respectively exposed between the dummy gate structures DGS, may be etched, and thus, a plurality of recess regions RR may be respectively formed in the plurality of fin-type active regions FA.

Thereafter, a plurality of source/drain regions130may be respectively formed to fill the plurality of recess regions RR in the first device region RX1and the second device region RX2. In example embodiments, to form the source/drain region130, a low-pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process may be performed using source materials including an element semiconductor precursor. In example embodiments, to form the source/drain region130including a silicon layer doped with an n-type dopant, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), and/or dichlorosilane (SiH2Cl2) may be used as a silicon source. The n-type dopant may be selected from phosphorus, arsenic, and antimony. In other example embodiments, to form the source/drain region130including a SiGe layer doped with a p-type dopant, a silicon source and a germanium source may be used. Silane (SiH4), disilane (Si2H6), trisilane (Si3H8), and/or dichlorosilane (SiH2Cl2) may be used as the silicon source. Germane (GeH4), digermane (Ge2H6), trigermane (Ge3H8), tetragermane (Ge4H10), and/or dichlorogermane (Ge2H2Cl2) may be used as the Ge source. The p-type dopant may be selected from boron and gallium.

The process of forming the source/drain region130in the first device region RX1and the process of forming the source/drain region130in the second device region RX2may be sequentially performed. For example, forming the source/drain region130in the first device region RX1may be followed by forming the source/drain region130in the second device region RX2. Alternatively, forming the source/drain region130in the second device region RX2may be followed by forming the source/drain region130in the first device region RX1.

An insulating liner146and an inter-gate dielectric film148may be formed to sequentially cover the resultant structure in which the source/drain region130is formed in each of the first device region RX1and the second device region RX2. The inter-gate dielectric film148may be formed to have a planarized top surface. After the inter-gate dielectric film148is formed, a top surface of the dummy insulating capping layer D16may be exposed.

Referring toFIG.8C, the dummy insulating capping layer D16and insulating films adjacent thereto may be removed from the resultant structure ofFIG.8Bby using a chemical mechanical polishing (CMP) process top expose a top surface of the dummy gate line D14. As a result, heights of the insulating liner146, the inter-gate dielectric film148, and the plurality of insulating spacers120may be reduced.

Referring toFIG.8D, a plurality of dummy gate lines D14and a plurality of dummy gate insulating films D12may be removed from the resultant structure ofFIG.8Cto provide a plurality of gate spaces GA. The insulating spacers120, the plurality of fin-type active regions FA, the device isolation film112, and the inter-device isolation insulating film114(refer toFIG.2B) may be exposed through the plurality of gate spaces GA.

Referring toFIG.8E, a gate insulating film132, a gate line GL, and an insulating capping line140may be formed in each of the plurality of gate spaces GA in the resultant structure ofFIG.8D.

To form the gate insulating film132, the gate line GL, and the insulating capping line140, a plurality of gate insulating films132and a plurality of gate lines GL may be formed to fill the plurality of gate spaces GA, and then etched back such that the plurality of gate insulating films132and the plurality of gate lines GL fill only lower portions of the gate spaces GA, respectively. During the etchback process, an upper portion of the insulating spacer120may be removed together, and thus, a height of the insulating spacer120may be reduced.

Afterwards, in the plurality of gate spaces GA, a plurality of insulating capping lines140may be formed to cover a top surface of each of the gate lines GL, the gate insulating film132, and the insulating spacers120and fill upper portions of the gate spaces GA. The insulating capping line140may be formed to have a planarized top surface. During the planarization of the top surface of the insulating capping line140, respective upper portions of the insulating liner146and the inter-gate dielectric film148may be removed together, and thus, heights of the insulating liner146and the inter-gate dielectric film148may be reduced. Afterwards, an insulating film149may be formed to cover the top surface of each of the insulating capping line140, the insulating liner146, and the inter-gate dielectric film148.

In example embodiments, before the gate insulating film132is formed, an interface film (not shown) may be formed to cover a surface of each of the plurality of fin-type active regions FA exposed through the plurality of gate spaces GA. To form the interface film, portions of the plurality of fin-type active regions FA exposed inside the plurality of gate spaces GA may be oxidized.

Referring toFIG.8F, in the resultant structure ofFIG.8E, a source/drain contact hole CAH may be formed to pass through the insulating film149and the inter-gate dielectric film148and expose the source/drain region130. After the source/drain region130is exposed through the source/drain contact hole CAH, a partial region of the source/drain region130may be removed using an anisotropic etching process through the source/drain contact hole CAH, and thus, the source/drain contact hole CAH may extend long toward the substrate110. In example embodiments, the anisotropic etching process for forming the source/drain contact hole CAH may be performed using plasma.

After the source/drain contact hole CAH is formed, a metal silicide film152may be formed on the source/drain region130, which is exposed at the bottom of the source/drain contact hole CAH. In example embodiments, the formation of the metal silicide film152may include forming a metal liner (not shown) to conformally cover an inner wall of the source/drain contact hole CAH and causing a reaction of the source/drain region130with a metal included in the metal liner by annealing the metal liner. After the metal silicide film152is formed, the remaining portion of the metal liner may be removed. A portion of the source/drain region130may be consumed during the formation of the metal silicide film152. In example embodiments, when the metal silicide film152includes a titanium silicide film, the metal liner may include a titanium film.

Referring toFIG.8G, in the resultant structure ofFIG.8F, a conductive barrier film154L may be formed to conformally cover surfaces exposed in an inner space of the source/drain contact hole CAH.

In example embodiments, the conductive barrier film154L may be formed using an atomic layer deposition (ALD) process. The conductive barrier film154L may be a preliminary barrier film required to form the conductive barrier pattern154shown inFIGS.2A and2C. The conductive barrier film154L may be formed to have a thickness of about 1.5 times to about 3 times a target thickness of the conductive barrier pattern154. By forming the conductive barrier film154L using an ALD process to a thickness greater than a target thickness of the conductive barrier pattern154, the conductive barrier film154L having a dense structure without defects (e.g., pits) may be obtained as compared to the case of forming a conductive barrier film having a relatively small thickness corresponding to the target thickness of the conductive barrier pattern154using an ALD process.

Referring toFIG.8H, the conductive barrier film154L may be etched back in the resultant structure ofFIG.8G, and thus, the conductive barrier pattern154may be formed from the conductive barrier film154L.

In example embodiments, to etch back the conductive barrier film154L, an etch gas capable of selectively etching the conductive barrier film154L may be used. The process of etching back the conductive barrier film154L using the etch gas may be performed in an atmosphere in which a bias voltage is not applied. The process of etching back the conductive barrier film154L may be performed using the etch gas that is not excited to a plasma state.

In example embodiments, the process of etching back the conductive barrier film154L may be performed at a temperature of about 100° C. to about 500° C., for example, a temperature of about 300° C. to about 450° C., without being limited thereto. In example embodiments, the process of etching back the conductive barrier film154L may be performed under a pressure of about 10 Torr to about 600 Torr.

In example embodiments, when the conductive barrier film154L includes a TiN film, the etch gas may include a halogen element-containing compound and H2gas. An etch rate of the conductive barrier film154L may be controlled by controlling a relative content of each of the halogen element-containing compound and the H2gas included in the etch gas. In example embodiments, the halogen element-containing compound may be selected from MoCl3, MoCl5, MoOCl4, MoCl6, MoO2Cl2, MoOCl4, WCl6, WCl5, WCl4, CHF3, BCl3, Cl2, and a combination thereof, without being limited thereto.

In example embodiments, the etch gas used during the process of etching back the conductive barrier film154L may include the same compound as a metal precursor required for a subsequent process of forming a conductive plug156. For example, when the conductive plug156includes Mo, the etch gas used during the process of etching back the conductive barrier film154L may include a Mo-containing compound, for example, MoCl3, MoCl5, MoOCl4, MoCl6, MoO2Cl2, MoOCl4, or a combination thereof.

As described above with reference toFIGS.8G and8H, the conductive barrier film154L having a relatively dense structure and a relatively great thickness may be formed and then etched back to form the conductive barrier pattern154. Thus, even when the conductive barrier pattern154having a relatively small thickness of about 1 nm or less is formed, the conductive barrier pattern154having a dense and uniform structure without defects (e.g., pits) may be obtained.

Referring toFIG.8I, in the resultant structure ofFIG.8H, a metal-containing film156L may be formed to fill a space of the source/drain contact hole CAH on the conductive barrier pattern154. The metal-containing film156L may be formed to fill the source/drain contact hole CAH and cover a top surface of the insulating film149.

The metal-containing film156L may include a metal selected from molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), and a combination thereof.

In example embodiments, the metal-containing film156L may include a molybdenum (Mo) film. In this case, the metal-containing film156L may be formed by means of an ALD process or a chemical vapor deposition (CVD) process using a molybdenum precursor. When the metal-containing film156L includes a molybdenum film, the molybdenum precursor may be selected from MoCl3, MoCl5, MoOCl4, MoCl6, Mo(CO)6, MoO2Cl2, MoOCl4, MoF6, an organic molybdenum compound, and a combination thereof. In example embodiments, the organic molybdenum compound may be selected from molybdenum acetylacetonate, biscyclopentadienyl molybdenum dihydride, bismethylcyclopentadienyl molybdenum dihydride, bisethylcyclopentadienyl molybdenum dihydride, bisisopropyl cyclopentadienyl molybdenum dihydride, biscyclopentadienyl imide molybdenum, and a combination thereof. However, types of molybdenum precursor that may be used to form the metal-containing film156L are not limited to the examples described above.

Referring toFIG.8J, in the resultant structure ofFIG.8I, a portion of the metal-containing film156L, which is outside the source/drain contact hole CAH, may be removed using a CMP process to expose the top surface of the insulating film149. As a result, the conductive plug156may be obtained from the metal-containing film156L, and a source/drain contact CA including the conductive barrier pattern154and the conductive plug156may be formed inside the source/drain contact hole CAH.

Thereafter, as shown inFIGS.2A and2B, an etch stop film182and an interlayer insulating film184may be sequentially formed on the resultant structure ofFIG.8Jto form an upper insulating structure180. A plurality of via contacts CAV may be respectively formed to be connected to the source/drain contacts CA, and a plurality of gate contacts CB may be respectively formed to be connected to the plurality of gate lines GL. Thus, the IC device100described with reference toFIGS.1and2A to2Cmay be manufactured.

In example embodiments, to form the plurality of gate contacts CB, processes similar to the processes of forming the source/drain contact CA, which has been described with reference toFIGS.8G to8J, may be performed.

FIGS.9A to16are cross-sectional views of a process sequence of a method of manufacturing an IC device, according to example embodiments, whereinFIGS.9A,10A,11A,12A,13A,14A,15, and16are cross-sectional views of a portion corresponding to a cross-section taken along line X4-X4′ ofFIG.6, according to the process sequence, andFIGS.9B,10B,11B,12B,13B, and14Bare cross-sectional views of a portion corresponding to a cross-section taken along line Y4-Y4′ ofFIG.6. A method of manufacturing the IC device400shown inFIGS.6.7A, and7B, according to an example embodiment, will be described with reference toFIGS.9A to16. InFIGS.9A to16, the same reference numerals are used to denote the same elements as inFIGS.6,7A, and7B, and detailed descriptions thereof are omitted.

Referring toFIGS.9A and9B, a plurality of sacrificial semiconductor layers404and a plurality of nanosheet semiconductor layers NS may be alternately stacked one by one on a substrate402. The plurality of sacrificial semiconductor layers404may include a different semiconductor material from the plurality of nanosheet semiconductor layers NS. In example embodiments, the plurality of sacrificial semiconductor layers404may include silicon germanium (SiGe), and the plurality of nanosheet semiconductor layers NS may include silicon.

Referring toFIGS.10A and10B, the plurality of sacrificial semiconductor layers404, the plurality of nanosheet semiconductor layers NS, and the substrate402may be partially etched to form trenches T4, and a device isolation film412may be formed inside the trenches T4. As a result, fin-type active regions F4may be defined by the trenches T4, respectively. Stack structures of the plurality of sacrificial semiconductor layers404and the plurality of nanosheet semiconductor layers NS may remain on top surfaces FT4of the fin-type active regions F4, respectively.

Referring toFIGS.11A and11B, in the resultant structure ofFIGS.10A and10B, a plurality of dummy gate structures DGS4may be formed on the stack structures of the plurality of sacrificial semiconductor layers404and the plurality of nanosheet semiconductor layers NS, and a plurality of outer insulating spacers418may be formed to cover both sidewalls of the plurality of dummy gate structures DGS4, respectively. Afterwards, the plurality of sacrificial semiconductor layers404and the plurality of nanosheet semiconductor layers NS may be partially etched using the plurality of dummy gate structures DGS4and the plurality of outer insulating spacers418as etch masks, respectively, and thus, the plurality of nanosheet semiconductor layers NS may be divided into a plurality of nanosheet stacks NSS including first to third nanosheets N1, N2, and N3. Thereafter, the fin-type active regions F4exposed between the plurality of nanosheet stacks NSS may be etched, and thus, a plurality of recess regions R4may be formed in upper portions of the fin-type active region F4.

Each of the plurality of dummy gate structures DGS4may extend long in the second lateral direction (Y direction). Each of the plurality of dummy gate structures DGS4may have a structure in which an insulating layer D462, a dummy gate layer D464, and a capping layer D466are sequentially stacked. In example embodiments, the insulating layer D462may include silicon oxide, the dummy gate layer D464may include polysilicon, and the capping layer D466may include silicon nitride.

Referring toFIGS.12A and12B, respective portions of the plurality of sacrificial semiconductor layers404exposed around the plurality of recess regions R4may be removed from the resultant structure ofFIGS.11A and11B, and thus, a plurality of indent regions may be formed between the first to third nanosheets N1, N2, and N3and between the first nanosheet N1and the top surface FT4of the fin-type active region F4. Thereafter, a plurality of inner insulating spacers428may be formed to fill the plurality of indent regions.

Referring toFIGS.13A and13B, in the resultant structure ofFIGS.12A and12B, a semiconductor material may be epitaxially grown from respective exposed surfaces of the plurality of recess regions R4and respective exposed surfaces of the first to third nanosheets N1, N2, and N3to form a plurality of source/drain regions430. Thereafter, an insulating liner442may be formed to cover the resultant structure including the plurality of source/drain regions430, and an inter-gate dielectric film444may be formed on the insulating liner442. Next, a top surface of each of the insulating liner442and the inter-gate dielectric film444may be planarized to expose a top surface of the capping layer D466(refer toFIGS.12A and12B).

Thereafter, a plurality of gate spaces GS may be prepared by removing the plurality of dummy gate structures DGS4shown inFIGS.12A and12B. The plurality of sacrificial semiconductor layers404may be removed through the gate spaces GS, and thus, the gate spaces GS may extend to respective spaces between the first to third nanosheets N1, N2, and N3and a space between the first nanosheet N1and the top surface FT4of the fin-type active region F4.

Referring toFIGS.14A and14B, a gate insulating film432may be formed to cover the exposed surfaces of the first to third nanosheets N1, N2, and N3and the fin-type active region F4. A plurality of gate lines460may be formed on the gate insulating film432to fill the gate spaces GS. Thereafter, respective upper portions of the plurality of gate lines460and respective upper portions of the gate insulating film432and the plurality of outer insulating spacers418, which are adjacent to the upper portions of the plurality of gate lines460, may be removed to empty respective upper spaces of the plurality of gate spaces GS. Afterwards, the upper space of each of the plurality of gate spaces GS may be filled with the insulating capping line440. By performing the planarization process during the formation of the plurality of gate lines460and the insulating capping line440, a height of each of the insulating liner442and the inter-gate dielectric film444may be reduced.

Referring toFIG.15, the inter-gate dielectric film444and the insulating liner442may be partially etched to form a plurality of source/drain contact holes CAH4exposing the plurality of source/drain regions430. Thereafter, a partial region of each of the source/drain regions430may be removed using an anisotropic etching process through the source/drain contact hole CAH4, and thus, the source/drain contact hole CAH4may extend long toward the substrate402.

Thereafter, a metal silicide film552may be formed on the source/drain region430, which is exposed at the bottom of the source/drain hole CAH4, by using a method similar to the process of forming the metal silicide film152, which has been described with reference toFIG.8F. A conductive barrier pattern454and a conductive plug456may be sequentially formed inside the source/drain contact hole CAH4by using a method similar to the process of forming the source/drain contact CA, which has been described with reference toFIGS.8A to8J, and thus, a source/drain contact CA4may be formed.

Referring toFIG.16, an etch stop film482and an interlayer insulating film484may be formed to sequentially cover the resultant structure ofFIG.15to form an upper insulating structure480, and a gate contact CB4may be formed to be connected to the gate line460. To form the gate contact CB4, processes similar to the process of forming the source/drain contact CA, which has been described with reference toFIGS.8G to8J, may be performed.

In addition, as shown inFIG.6, a plurality of source/drain via contacts CAV4may be formed to be connected to the plurality of source/drain contacts CA4, respectively. In example embodiments, the plurality of source/drain via contacts CAV4may be formed simultaneously with the plurality of gate contacts CB4. In other example embodiments, the plurality of source/drain via contacts CAV4and the plurality of gate contacts CB4may be sequentially formed using separate processes. In this case, forming the plurality of source/drain via contacts CAV4may be followed by forming the plurality of gate contacts CB4. Alternatively, forming the plurality of gate contacts CB4may be followed by following the plurality of source/drain via contacts CAV4.

Although the method of manufacturing the IC device100shown inFIGS.1and2A to2Cand the method of manufacturing the IC device400shown inFIGS.6,7A, and7Bhave been described with reference toFIGS.8A to16, it will be understood that the IC device200shown inFIG.3, the IC device300A shown inFIG.4, and the IC device300B shown inFIG.5, and IC devices having various other structures may be manufactured by making various modifications and changes within the scope of the inventive concept with reference to the above description.

While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.