Patent ID: 12200942

DETAILED DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

Exemplary embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The disclosure may, however, be exemplified in many different forms and should not be construed as being limited to the specific exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As appreciated by the present inventors, an FeFET device can function as a non-volatile memory device by changing the threshold voltage of the device to represent different states, which can be retained by the device when power is removed. For example, the FeFET device can be placed in a “programmed” state or an “erased” state by establishing a respective threshold voltage by applying a program or erase voltage to switch the polarization of a ferroelectric layer in the device. During polarization switching charges may be trapped in an interfacial layer partially or fully offsetting the polarization. As time passes the charges trapped in the interfacial layer can be neutralized through emission of the carriers or other neutralization events. The polarization is increasingly reflected over time as the trapped carriers screening the polarization charge are neutralized. Accordingly, after writing an FeFET device, a delay time is allotted to allow for the trapped carriers to be sufficiently neutralized before the state of the FeFET device may be correctly read.

As described herein in some embodiments according to the invention, a non-zero bias voltage (i.e., a negative or positive bias relative to 0 volts) can be added (during the delay time) to a voltage pulse train used to program or erase an FeFET to significantly alter the neutralization time constant for traps arising during operation of FeFET devices. In some embodiments, the non-zero bias voltage can have the opposite polarity of the voltage level that is used to program or erase the FeFET device. For example, a negative bias voltage can be applied during the delay time after the FeFET is placed in the programmed state with a positive voltage pulse. In contrast, a positive bias voltage can be applied during the delay time after the FeFET is placed in the erased state using a negative voltage pulse.

The non-zero bias voltage (Vdelay,PRGand Vdelay,ERS) can be applied across the FeFET gate/source electrodes during the delay time, which occurs directly after completion of the program voltage pulse or the erase voltage pulse and before a read operation is performed to the FeFET. The non-zero bias voltage can reduce the amount of delay needed before the correct state of the FeFET device can be read. This approach may be especially effective for traps as capture and emission times can have an exponential dependence upon surface potential.

FIG.1is a schematic illustration of an FeFET device105coupled to a controller circuit100that is configured to provide voltage pulses (sometimes referred to herein as a “pulse train”) including a non-zero bias voltage level to the FeFET device105to the establish the programmed state or the erased state for the FeFET device105in some embodiments accord to the invention. According toFIG.1, the controller circuit100can include a write voltage circuit115that can provide the voltage levels used for write operations to establish the state of the FeFET device105. The controller circuit100also includes a read voltage circuit120that can provide the voltage level used for read operations to determine the state the FeFET device105.

As shown inFIG.1, in some embodiments according to the invention, the FeFET device105can be an n-type FeFET device having n+ doped source and drain regions formed in a p-type substrate to allow for the formation of an inversion layer IL in the channel region between the source S and drain D regions in response to a voltage applied across the gate-source junction. The gate can include a gate stack including a gate metal G, a tungsten layer W, and a TiN layer on a Ferroelectric layer over the channel region between the source S and drain D regions. Other FeFET device types and structures may also be within the scope of the present invention.

It will be understood that, as used herein, the term “write operation” includes a program operation and an erase operation. In some embodiments according to the invention, the write voltage level for a program operation is a positive voltage level and the write voltage level for an erase operation is a negative voltage level. Furthermore, it will be understood that the voltage levels described herein are provided at the gate electrode of the FeFET device105relative to the source electrode of the FeFET device105. Accordingly, a program operation can be performed by applying a program voltage level that is positive at the gate electrode relative to the source electrode. Furthermore, an erase operation can be performed by applying an erase voltage level that is negative at the gate electrode relative to the source electrode. It will be understood, therefore, that in some embodiments according to the invention the program and erase voltage levels can be provided at the gate electrode by shifting the reference level at the source electrode.

As further shown inFIG.1, the controller circuit100can include a non-zero bias voltage circuit125that is configured to provide a particular non-zero bias voltage level for inclusion in the pulse train for the program operation and for the erase operation. As described herein in some embodiments according to the present invention, the non-zero bias voltage level is used to shift the voltage level provided to the gate electrode of the FeFET device105to a value other than 0 volts for a delay time that occurs directly after the write operation is complete. In some embodiments according to the invention, the write operation is complete when the voltage pulse to the FeFET device105changes from the write voltage level to a value that is more than or less than a value that is specified to initiate the program or erase operation for the FeFET device105.

As further shown inFIG.1, the controller circuit100can include a timing control circuit110that is configured to control a switch circuit130to apply the write voltages, the read voltage, and the non-zero bias voltages to the FeFET device105for the times in order to perform program operations, erase operations, and read operations in accordance with embodiments of the present invention.

In operation, the timing control circuit110operates the switch circuit130to provide voltage pulses to the FeFET device105as shown inFIGS.2A and2Bto perform program and erase operations respectively, followed by read operations. As shown inFIG.2A, a program operation can be performed to the FeFET device105by applying a positive voltage pulse from the write voltage circuit115at a program voltage level VPRGneeded to initiate a program operation for the FeFET device105. The program voltage level VPRGis maintained by the timing control circuit110for a program operation time interval (when VPRGis high) that is specified to perform the program operation.

Directly after the program operation time interval, the timing control circuit110switches to a negative bias voltage VDELAY,PRGso that Vout transitions from VPRGto VDELAY,PRG. Furthermore, timing control circuit110maintains VDELAY,PRGat Vout for a delay time interval before the timing control circuit110switches the read voltage circuit120to provide VREADas Vout to the FeFET device105.

As shown inFIG.2B, an erase operation can be performed to the FeFET device105by applying a negative voltage pulse from the write voltage circuit115at an erase voltage level VERSneeded to initiate an erase operation as Vout for the FeFET device105. The erase voltage level VERSis maintained by the timing control circuit110for an erase operation time interval that is specified to perform the erase operation.

Directly after the erase operation time interval, the timing control circuit110switches to a positive bias voltage VDELAY,ERSso that Vout transitions from VERSto VDELAY,ERS. Furthermore, timing control circuit110maintains VDELAY,ERSat Vout for a delay time interval before the timing control circuit110switches the read voltage circuit120to provide VREADto Vout.

In some embodiments according to the invention, the delay time occurs when the write voltage level is changed from the write voltage level to begin a delay time that specifies an amount of time that should elapse before the state of the FeFET device105can be determined. In some embodiments according to the invention, Vout transitions from VPRGto VDELAY,PRGand/or from VERSto VDELAY,ERSon a continuous edge. In some embodiments according to the invention, Vout transitions from VPRGto VDELAY,PRGand/or from VERSto VDELAY,ERSincluding an intervening time interval at a voltage level that is between VPRGand VDELAY,PRGor between VERSand VDELAY,ERSbefore settling at the non-zero bias voltage.

FIG.3is a graph illustrating the tdelayto achieve IPRG/IERSof about 100 for different Vdelay,PRG/Vdelay,ERSin some embodiments according to the invention. According toFIG.3, by applying an increasing non-zero bias voltage having a polarity that is the opposite of the polarity of the signal used for the write operation, the threshold of the IPGM/IERS=100 can be achieved in a shorter delay time interval indicating a significant improvement in the neutralization time.

FIG.4is a graph illustrating tdelayfor a range of bias voltage levels for Vdelay,PRG/Vdelay,ERSin some embodiments according to the invention. In particular, as shown inFIG.4, the delay time interval for a IPGM/IERSof about 100 decreases more than 5 orders of magnitude for increasing voltage of the opposite polarity as the program and erase voltages.

FIG.5is a flowchart illustrating operations of the controller circuit100ofFIG.1using a non-zero bias voltage level to the establish the programmed state or the erased state for the FeFET device105in some embodiments according to the invention. According toFIG.5, operations of the controller circuit100can begin when a program operation voltage is applied to the FeFET device105as Vout for a program time to establish a programmed state for the FeFET device (block505). Directly after the end of the program time, the level of the voltage signal is changed to a negative bias voltage level for a delay time to reduce neutralization of a trap state associated with the program operation of the FeFET device (block510).

After the delay time, the level of the voltage signal is changed to a read voltage level as a read operation to the FeFET device to determine the programmed state of the FeFET device established during the program operation (block515). A voltage signal having an erase voltage level as an erase program operation is applied as Vout to the FeFET device105for an erase time to establish a programmed state for the FeFET device1015(Block520).

Directly after the end of the erase time, the level of the voltage signal is changed to a positive bias voltage level for a delay time to reduce neutralization of a trap state associated with the erase operation of the FeFET device (block525). After the delay time, the level of the voltage signal is changed to a read voltage level as a read operation to the FeFET device105to determine the erased state of the FeFET device105established during the erase operation.

FIG.6is a block diagram of the switch circuit130included in the controller circuit100operating under control of the timing control circuit110ofFIG.1in some embodiments according to the invention. According toFIG.6, the switch circuit130includes two multiplexers (MUXs)605and610so that the output voltage (Vout) can be provided by selecting output from then write voltage circuit115, the non-zero bias voltage circuit125, and the read voltage circuit120through operation of the control signals CTRL_SIGN and CTRL_WR generated by the timing control circuit110.

FIG.7Ais a diagram illustrating example timing and voltage levels for control signals generated by the timing control circuit ofFIG.1in some embodiments accord to the invention.FIG.7Bis a diagram illustrating example timing and voltage levels of Voutgenerated by the switch circuit to the FeFET device ofFIG.1in some embodiments according to the invention.

FIG.8is a schematic illustration of the non-zero bias voltage circuit125ofFIG.1as a negative charge pump circuit to provide the non-zero bias voltage level in some embodiments according to the invention.FIG.9are diagrams illustrating example timing and voltage levels for operation of the negative charge pump circuit ofFIG.8in some embodiments according to the invention.FIG.10are diagrams illustrating example timing and voltage levels for V1and V2associated with operation of the negative charge pump circuit ofFIG.8in some embodiments according to the invention.

Referring toFIG.6-10, to perform a write operation, the control signal (CTRL_SIGN) is set to ‘1’ to select write voltage (Vwrite) from the first MUX605, which is a DC voltage, and write control signal (CTRL_WR) is set to ‘0’ to pass Vwrite through the second MUX610to Vout. To apply the bias voltage during the delay time interval, a DC voltage generator, such as the negative charge pump circuit of 8, can be used. According toFIG.8, a pulse having polarity opposite to that of the write pulse can be generated. In some embodiments according to the present invention, the negative charge pump circuit can include two n-type I/O transistors with deep N-well, M1and M2and two coupling capacitors, C1and C2.

The internal nodes n1and n2, and the output node (V1) are pre-charged to 0V. The negative hold voltage can be generated by forcing control signal1(Ctrl_1) from the pre-charged level VDD to 0V, which subsequently brings n1, n2and the output voltage of the pump (V1) from 0V to about −VDD. The purpose of C2is similar to that of C1but C2can be used to fine tune the negative hold voltage by the control signal2(Ctrl_2). Both control signals (Ctrl_1and Ctrl_2) are of non-negative voltages and can be provided by the timing control circuit110. The CTRL_SIGN is set to ‘0’ to select V1and CTRL_WR is set to ‘0’ to pass V1through the second MUX610to Vout. To perform a read operation, CTRL_WR is set to ‘1’ to pass DC read voltage (Vread) from the read voltage circuit120, through the second MUX610to Vout.

As described herein, by applying negative Vdelay,PRGdirectly after a program voltage pulse as shown inFIG.2A, for example, IPRGcan rise faster for a larger negative voltage as a result of faster neutralization of acceptor type states. However, IPGMcan begin to reduce due to donor becoming charged as the negative bias point is held for longer periods of time. As shown inFIG.11, IERScan be reduced by applying positive Vdelay,ERSby increasing the neutralization rate for donor states; no increase in IERSis observed on the linear scale due to the FeFET being in the off-state. With Vdelay,PRG=1.5 V and Vdelay,ERS=1.5 V, IPRG/IERS ratio of 100 can be accomplished with a tdelayof −400 ns as shown inFIG.3.FIG.4compares tdelayfor different Vdelay,PRG/Vdelay,ERScombinations, demonstrating that the read after write wait times can be reduced monotonically by applying a negative or positive voltage bias and can be reduced by 105times using ±1.5 V standby voltages relative to the zero standby voltage scenario, which can make the read after write time sufficient for many applications.

As described herein in some embodiments according to the invention, a non-zero bias voltage (i.e., a negative or positive bias relative to 0 volts) can be added (during the delay time) to a voltage pulse train used to program or erase an FeFET to significantly alter the neutralization time constant for traps arising during operation of FeFET devices. In some embodiments, the non-zero bias voltage can have the opposite polarity of the voltage level that is used to program or erase the FeFET device. For example, a negative bias voltage can be applied during the delay time after the FeFET is placed in the programmed state with a positive voltage pulse. In contrast, a positive bias voltage can be applied during the delay time after the FeFET is placed in the erased state using a negative voltage pulse.

As used herein any reference to “one embodiment” or “an embodiment” means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

Some embodiments may be described using the expression “coupled” and “connected” along with their derivatives. For example, some embodiments may be described using the term “coupled” to indicate that two or more elements are in direct physical or electrical contact. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other. The embodiments are not limited in this context.

As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).

In addition, use of the “a” or “an” are employed to describe elements and components of the embodiments herein. This is done merely for convenience and to give a general sense of various embodiments. This description should be read to include one or at least one and the singular also includes the plural unless it is obvious that it is meant otherwise.

It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and/or relative positioning of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present inventive concept. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments. The same reference numbers may be used to describe like or similar parts. Further, while several examples have been disclosed herein, any features from any examples may be combined with or replaced by other features from other examples. Moreover, while several examples have been dis-closed herein, changes may be made to the disclosed examples within departing from the scope of the claims.

Those skilled in the art will recognize that a wide variety of modifications, alterations, and combinations can be made with respect to the above described embodiments without departing from the scope of the inventive concept, and that such modifications, alterations, and combinations are to be viewed as being within the ambit of the inventive concept.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting to other embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including”, “have” and/or “having” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Elements described as being “to” perform functions, acts and/or operations may be configured to or other structured to do so.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments described herein belong. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Terms such as “substantially,” “about,” “approximately” or the like as used in referring to a relationship between two objects is intended to reflect not only an exact relationship but also variances in that relationship that may be due to various factors such as the effects of environmental conditions, common error tolerances, manufacturing variances, or the like. It should further be understood that although some values or other relationships may be expressed herein without a modifier, these values or other relationships may also be exact or may include a degree of variation due to various factors such as the effects of environmental conditions, common error tolerances, manufacturing variances, or the like.

In some embodiments, the term “about” generally refers to a range of numeric values that one of skill in the art would consider equivalent to the recited numeric value or having the same function or result. For example, “about” may refer to a range that is within ±1%, ±2%, ±5%, ±7%, ±10%, ±15%, or even ±20% of the indicated value, depending upon the numeric values that one of skill in the art would consider equivalent to the recited numeric value or having the same function or result. Furthermore, in some embodiments, a numeric value modified by the term “about” may also include a numeric value that is “exactly” the recited numeric value. In addition, any numeric value presented without modification will be appreciated to include numeric values “about” the recited numeric value, as well as include “exactly” the recited numeric value. Similarly, the term “substantially” means largely, but not wholly, the same form, manner or degree and the particular element will have a range of configurations as a person of ordinary skill in the art would consider as having the same function or result. When a particular element is expressed as an ap-proximation by use of the term “substantially,” it will be understood that the particular element forms another embodiment.

Conditional language, such as, among others, “can,” “could,” “might,” or “may,” unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or steps. Thus, such conditional language is not generally intended to im-ply that features, elements and/or steps are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without user input or prompting, whether these features, elements and/or steps are included or are to be performed in any particular embodiment.

Unless the context clearly requires otherwise, throughout the description and the claims, the words “include,” “can include,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the con-text permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, covers all of the following interpretations of the word: any one of the items in the list, all of the items in the list, and any combination of the items in the list. Likewise the term “and/or” in reference to a list of two or more items, covers all of the following interpretations of the word: any one of the items in the list, all of the items in the list, and any combination of the items in the list.

Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is otherwise understood with the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (non-limiting examples: X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present.

Unless otherwise explicitly stated, articles such as “a” or “an” should generally be interpreted to include one or more described items. Accordingly, phrases such as “a device configured to” are intended to include one or more recited devices. Such one or more recited devices can also be collectively configured to carry out the stated recitations. For example, “a processor configured to carry out recitations A, B and C” can include a first processor configured to carry out recitation A working in conjunction with a second processor configured to carry out recitations B and C.

While the detailed description f has shown, described, and pointed out novel features as applied to various embodiments, it can be understood that various omissions, substitutions, and changes in the form and details of the devices or algorithms illustrated can be made without departing from the spirit of the disclosure. As can be recognized, certain embodiments described elsewhere herein can be embodied within a form that does not provide all of the features and benefits set forth herein, as some features can be used or practiced separately from others. The scope of certain embodiments disclosed herein is indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

These and other changes can be made to the invention in light of the detailed description. While the above description describes certain examples of the invention, and describes the best mode contemplated, no matter how detailed the above appears in text, the invention can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the invention disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the invention with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification, unless the above detailed description section explicitly de-fines such terms. Accordingly, the actual scope of the invention encompasses not only the dis-closed examples, but also all equivalent ways of practicing or implementing the invention under the claims.