Patent ID: 12262603

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments. Further, various embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concepts.

Unless otherwise specified, the illustrated embodiments are to be understood as providing features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements.

When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the DR1-axis, the DR2-axis, and the DR3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z — axes, and may be interpreted in a broader sense. For example, the DR1-axis, the DR2-axis, and the DR3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Various embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

Further, throughout the specification, the phrase “on a plane” means viewing a target portion from the top, and the phrase “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side.

First, a display device according to an embodiment of the inventive concepts will be described with reference toFIG.1andFIG.2.

FIG.1is a top plan view of a display device according to an embodiment, andFIG.2is a cross-sectional view ofFIG.1, taken along the line II-II.

As shown inFIG.1andFIG.2, a display device1000according to an embodiment includes a substrate110and emitting diodes ED1and ED2that are disposed on the substrate110.

The substrate110includes a display area DA and a peripheral area PA that is adjacent to the display area DA.

The display area DA may be disposed in a center of the display device1000, may have a substantially rectangular shape, and each corner may have a rounded shape. However, the shape of the display area DA and the shape of the corner are not limited thereto, and may be variously changed. The display area DA may include a first display area DA1and second display areas DA2that are adjacent to the first display area DA1. The first display area DA1may be disposed in a center of the display area DA, and the second display area DA2may be disposed on both sides of the first display area DA1, for example, left and right. However, this is only an example, and the positions of the first display area DA1and the second display area DA2may be variously changed. For example, the first display area DA1may be formed in an approximately quadrangle shape, and the second display area DA2may be disposed so as to surround the four corners of the first display area DA1.

The peripheral area PA may be formed to surround the display area DA. The peripheral area PA is an area in which an image is not displayed, and may be disposed on an outer side of the display device1000.

At least a part of the display device according to the embodiment may include a bent portion that can be bent. For example, a center portion of the display device1000may be flat, and edge portions of the display device1000may be bent. In this case, at least a part of the second display area DA2may be disposed in the bent portion. That is, at least a part of the second display area DA2of the substrate110may be bent.

The emitting diodes ED1and ED2may emit a predetermined light. For example, the emitting diodes ED1and ED2may emit light of red, green, and blue, or white. The display device1000may display a predetermined image through light emitted from the emitting diodes ED1and ED2. The emitting diodes ED1and ED2may include a first emitting diode ED1and a second emitting diode ED2. The emitting diodes ED1and ED2may be disposed in the display area DA. The first emitting diode ED1may be disposed in the first display area DA1, and the second emitting diode ED2may be disposed in the second display area DA2. Although it is not illustrated, the display device1000according to the embodiment may include plurality of first emitting diodes ED1and a plurality of second emitting diodes ED2. The plurality of first emitting diodes ED1may be arranged in the first display area DA1along a first direction DR1and a second direction DR2, and the plurality of second emitting diodes ED2may be arranged in the second display area DA2along the first direction DR1and the second direction DR2. The size of the first emitting diode ED1and the size of the second emitting diode ED2may be the same or different. For example, the size of the second emitting diode ED2may be larger than the size of the first emitting diode ED1. The number of first emitting diodes ED1per unit area and the number of second emitting diodes ED2per unit area may be the same or different. For example, the number of second emitting diodes ED2per unit area may be less than the number of first emitting diodes ED1per unit area. The resolution of the first display area DA1and the resolution of the second display area DA2may be the same or different. For example, the resolution of the first display area DA1may be higher than that of the second display area DA2. The alignment form, size, and resolution of the first display area DA1and the second display area DA2of the first emitting diode ED1and the second emitting diode ED2are not limited thereto, and may be variously changed.

The display device1000according to the embodiment may further include pixel circuit portions PC1and PC2disposed on the substrate110. The pixel circuit portions PC1and PC2may include a first pixel circuit portion PC1and a second pixel circuit portion PC2. The display device1000according to the embodiment may include a plurality of first pixel circuit portions PC1and a plurality of second pixel circuit portions PC2. The first pixel circuit portion PC1substantially indicates an area where the plurality of first pixel circuit portions PC1are arranged along the first direction DR1and the second direction DR2, and the second pixel circuit portion PC2substantially indicates an area where the plurality of second pixel circuit portions PC2are arranged in the first direction DR1and the second direction DR2. The arrangement form of the plurality of pixel circuit portions PC1and PC2is not particularly limited, and they may be arranged in various forms. The first pixel circuit portion PC1may be disposed in the first display area DA1, and the second pixel circuit portion PC2may be disposed in the second display area DA2. Each of the pixel circuit portions PC1and PC2may be connected to one of the emitting diodes ED1and ED2. The first pixel circuit portion PC1may be connected with the first emitting diode ED1, and the second pixel circuit portion PC2may be connected with the second emitting diode ED2. The size of one first pixel circuit portion PC1and the size of one second pixel circuit portion PC2may be the same or different. For example, the size of one second pixel circuit portion PC2may be larger than the size of one first pixel circuit portion PC1. In addition, the structure of the first pixel circuit portion PC1and the structure of the second pixel circuit portion PC2may be different.

The display device1000according to the embodiment may further include a driving circuit portion DR disposed on the substrate110. The driving circuit portion DR may be connected to the first pixel circuit portion PC1and the second pixel circuit portion PC2. The driving circuit portion DR may include a plurality of driver and signal wires. For example, the driving circuit portion DR may include a scan driver, data driver, a driving voltage supply line, a common voltage supply line, and signal transmission wires connected to the scan driver, the data driver, the driving voltage supply line, and the common voltage supply line. The scan driver generates a scan signal and transmits the scan signal to the pixel circuit portions PC1and PC2through a scan line. The data driver generates a data signal and transmits the data signal to the pixel circuit portions PC1and PC2through a data line. The driving voltage supply line transmits a driving voltage to the pixel circuit portions PC1and PC2. The common voltage supply line transmits a common voltage to one electrode of the emitting diodes ED1and ED2. At least a part of the driving circuit portion DR may be disposed in the second display area DA2, and the remaining portion may be disposed in the peripheral area PA.

In the first display area DA1, the first pixel circuit portion PC1may be electrically connected with the first emitting diode ED1disposed on the first pixel circuit portion PC1. In this case, a light emission area of the first emitting diode ED1may overlap the first pixel circuit portion PC1that is connected thereto. The first display area DA1is an area from which light is emitted by the first emitting diode ED1.

In the second display area DA2, the second pixel circuit portion PC2may be connected with the second emitting diode ED2that is disposed at a predetermined distance therefrom. In this case, a light emitting area of the second emitting diode ED2may not overlap the second pixel circuit portion PC2that is connected thereto. The light emitting area of the second emitting diode ED2may overlap with the second pixel circuit portion PC2that is not connected thereto. The light emitting area of the second emitting diode ED2may overlap the driving circuit portion DR. The light emitting areas of some second emitting diodes ED2may overlap with the second pixel circuit portion PC2connected thereto. The second display area DA2is an area from which light is emitted by the second emitting diode ED2.

In a general display device, the pixel circuit portion and emitting diode are disposed in the display area, the driving circuit portion is disposed in the peripheral area surrounding the display area, and the pixel circuit portion and emitting diode are not disposed. Accordingly, light is not emitted from the peripheral area where the driving circuit portion is disposed, and a dead space is formed. In the display device according to the embodiment, the second emitting diode ED2is disposed at a portion where the driving circuit portion DR is disposed to emit light, thereby expanding a region in which a screen is displayed. That is, the dead space can be reduced and the bezel can be reduced by positioning the second emitting diode ED2on the driving circuit portion DR.

Hereinafter, a connection relationship between each pixel circuit portion and an emitting diode of the display device according to the embodiment will be described with reference toFIG.3toFIG.5.

FIG.3is a top plan view of a connection relationship between the pixel circuit portion and the light emitting element of the display device according to the embodiment,FIG.4is a cross-sectional view of a part of the display device according to the embodiment, andFIG.5is a cross-sectional view of enlarged some layers of some area ofFIG.4.

First, as shown inFIG.3andFIG.4, the light emitting area of the first emitting diode ED1of the display device according to the embodiment overlaps the first pixel circuit portion PC1that is connected with the first emitting diode ED1.

The first pixel circuit portion PC1includes a semiconductor1130disposed on the first display area DA1of the substrate110, a gate electrode1151, a source electrode1173, and a drain electrode1175.

The substrate110may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. The substrate110may contain a flexible material that can be bent or folded, and may be single-layered or multi-layered.

A buffer layer111may be disposed on the substrate110. The buffer layer111may have a single-layered or multi-layered structure. The buffer layer111may include an inorganic insulating material such as a silicon nitride (SiNY), a silicon oxide (SiOX), and a silicon oxynitride (SiOXNY), or an organic insulating material. The buffer layer111may be omitted as necessary. In addition, a barrier layer may further be disposed between the substrate110and the buffer layer111. The barrier layer may have a single-layer or multi-layer structure. The barrier layer may include an inorganic insulating material such as a silicon nitride (SiNY), a silicon oxide (SiOX), a silicon oxynitride (SiOXNY), and the like.

A semiconductor layer including the semiconductor1130of the first pixel circuit portion PC1may be disposed on the buffer layer111. The semiconductor1130may include a first region1131, a channel1132, and a second region1133. The first region1131and the second region1133may be respectively disposed at opposite sides of the channel1132of the semiconductor1130of the first pixel circuit portion PC1. The semiconductor1130of the first pixel circuit portion PC1may include a semiconductor material such as amorphous silicon, a polysilicon, an oxide semiconductor, and the like.

A first gate insulating layer141may be disposed on the semiconductor1130of the first pixel circuit portion PC1. The first gate insulating layer141may have a single-layer or multi-layer structure. The first gate insulating layer141may include an inorganic insulating material such as a silicon nitride (SiNY), a silicon oxide (SiOX), a silicon oxynitride (SiOXNY), and the like.

A first gate conductive layer that includes the gate electrode1151of the first pixel circuit portion PC1may be disposed on the first gate insulating layer141. The gate electrode1151of the first pixel circuit portion PC1may overlap the channel1132of the semiconductor1130. The first gate conductive layer may have a single-layer or multi-layer structure. The first gate conductive layer may include may include a metallic material such as molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti). After forming the first gate conductive layer, a doping process or plasma treatment may be performed. A portion of the semiconductor layer, covered by the first gate conductive layer, is not doped or plasma treated, and a portion of the semiconductor layer, not covered by the first gate conductive layer, is doped or plasma treated and thus it may have the same characteristic as a conductor.

A second gate insulating layer142may be disposed on the first gate conductive layer including the gate electrode1151of the first pixel circuit portion PC1. The second gate insulating layer142may have a single-layer or multi-layer structure. The second gate insulating layer142may include an inorganic insulating material such as a silicon nitride (SiNY), a silicon oxide (SiOX), a silicon oxynitride (SiOXNY), and the like.

A second gate conductive layer that includes a first sustain electrode1153may be disposed on the second gate insulating layer142. The second gate conductive layer may have a single-layer or multi-layer structure. The second gate conductive layer may include a metallic material such as molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti). The first sustain electrode1153forms a sustain capacitor by overlapping the gate electrode1151.

A first interlayer insulating layer160may be disposed on the second gate conductive layer that includes the first sustain electrode1153. The first interlayer insulating layer160may have a single-layer or multi-layer structure. The first interlayer insulating layer160may include an inorganic insulating material or an organic insulating material.

A first data conductive layer that includes the source electrode1173and the drain electrode1175of the first pixel circuit portion PC1may be disposed on the first interlayer insulating layer160. The first data conductive layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu).

The first interlayer insulating layer160may include an opening that overlaps the source electrode1173of the first pixel circuit portion PC1and the first region1131of the semiconductor1130. The source electrode1173of the first pixel circuit portion PC1may be connected with the first region1131of the semiconductor1130through the opening. The first interlayer insulating layer160may include an opening that overlaps the drain electrode1175of the first pixel circuit portion PC1and the second region1133of the semiconductor1130. The drain electrode1175of the first pixel circuit portion PC1may be connected with the second region1133of the semiconductor1130through the opening.

A first protective layer180may be disposed on the first data conductor layer that includes the source electrode1173and the drain electrode1175of the first pixel circuit portion is PC1. The first protective layer180may include an inorganic insulating material such as a silicon nitride (SiNY), a silicon oxide (SiOX), a silicon oxynitride (SiOXNY), and the like and/or an organic insulating material such as a polyimide, an acryl-based polymer, a siloxane-based polymer, and the like.

A second data conductive layer that includes the connection electrode510of the first pixel circuit portion PC1may be disposed on the first protective layer180. The second data conductive layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), potassium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu).

The first protective layer180may include an opening that overlaps the drain electrode1175of the first pixel circuit portion PC1. The connection electrode510of the first pixel circuit portion PC1may be connected with the drain electrode1175through the opening.

A second protective layer182may be disposed on the second data conductive layer that includes the connection electrode510of the first pixel circuit portion PC1. The second protective layer182may contain an organic insulating material such as general-purpose polymers such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acryl-based polymers, imide-based polymers, polyimide, acryl-based polymers, siloxane-based polymers, and the like.

A first emitting diode ED1connected with the first pixel circuit portion PC1may be disposed on the second protective layer182. The first emitting diode ED1may include a pixel electrode1191, an emission layer1370, and a common electrode270.

The pixel electrode1191of the first emitting diode ED1may be disposed on the second protective layer182. The second protective layer182may include an opening that overlaps the pixel electrode1191of the first emitting diode ED1and the connection electrode510of the first pixel circuit portion PC1. The pixel electrode1191of the first emitting diode ED1may be connected with the connection electrode510of the first pixel circuit portion PC1through the opening1181. Thus, the pixel electrode1191of the first emitting diode ED1may be connected with the drain electrode1175of the first pixel circuit portion PC1through the connection electrode510.

A partitioning wall350may be disposed on the pixel electrode1191of the first emitting diode ED1. A pixel opening1351is formed in the partitioning wall350, and the pixel opening1351of the partitioning wall350may overlap the pixel electrode1191.

An emission layer1370of the first emitting diode ED1may be disposed in the pixel opening1351of the partitioning wall350. The emission layer1370may overlap the pixel electrode1191.

A common electrode270may be disposed on the emission layer1370and the partitioning wall350.

The first emitting diode ED1emits light around a region where the pixel electrode1191, the emission layer1370, and the common electrode270overlap, and a light emitting region of the first emitting diode ED1overlaps with the first pixel circuit portion PC1connected thereto.

In the first display area DA1, the first pixel circuit portion PC1and the first emitting diode ED1are respectively arranged in a matrix format along a first direction DR1and a second direction DR2. In this case, a pixel circuit portion PC1disposed at a first row and a first column is connected to the first emitting diode ED1, while overlapping the first emitting diode ED1. A pixel circuit portion PC1disposed at the first row and a second column is connected with the first emitting diode ED1, while overlapping the first emitting diode ED1. A pixel circuit portion PC1disposed at a second row and the first column is connected with the first emitting diode ED1, while overlapping the first emitting diode ED1. A pixel circuit portion PC1disposed at the second row and the second column is connected with the first emitting diode ED1, while overlapping the first emitting diode ED1.

In this case, the first emitting diode ED1may display at least one of a first color, a second color, and a third color. For example, the first emitting diode ED1may display red R, green G, and blue B colors. In this case, a first emitting diode ED1displaying red R, a first emitting diode ED1displaying green G, a first emitting diode ED1displaying blue B, and a first emitting diode ED1displaying green G may be repeatedly disposed in the first row and the third row. A first emitting diode ED1displaying blue B, a first emitting diode ED1displaying green G, a first emitting diode ED1displaying red R, and a first emitting diode ED1displaying green G may be repeatedly disposed in a second row and a fourth row.

A light emitting region of the second emitting diode ED2of the display device according to the embodiment may or may not overlap the second pixel circuit portion PC2connected to the second emitting diode ED2. A part of the plurality of second emitting diodes ED2may overlap the second pixel circuit portion PC2connected with the second emitting diode ED2. Another part of the plurality of second emitting diodes ED2may overlap the driving circuit portion DR.

The second pixel circuit portion PC2may include a semiconductor2130, a gate electrode2151, a source electrode2173, and a drain electrode2175disposed on the second display area DA2of the substrate110. The driving circuit portion DR may include a semiconductor3130, a gate electrode3151, a source electrode3173, and a drain electrode3175disposed on the second display area DA2of the substrate110.

A buffer layer111may be disposed on the substrate110, the semiconductor2130of the second pixel circuit portion PC2, and the semiconductor3130of the driving circuit portion DR may be disposed on the buffer layer111. The semiconductor2130of the second pixel circuit portion PC2and the semiconductor3130of the driving circuit portion DR may be disposed in the semiconductor layer.

A first gate insulating layer141may be disposed on the semiconductor2130of the second pixel circuit portion PC2and the semiconductor3130of the driving circuit portion DR, and the gate electrode2151of the second pixel circuit portion PC2and the gate electrode3151of the driving circuit portion DR may be disposed on the first gate insulating layer141. The semiconductor2130of the second pixel circuit portion PC2and the semiconductor3130of the driving circuit portion DR may be disposed in the first gate conductive layer. The gate electrode2151of the second pixel circuit portion PC2may overlap the channel2132of the semiconductor2130.

The second gate insulating layer142may be disposed on the gate electrode2151of the second pixel circuit portion PC2and the gate electrode3151of the driving circuit portion DR, and a first sustain electrode2153of the second pixel circuit portion PC2and a first sustain electrode3153of the driving circuit portion DR may be disposed on the second gate insulating layer142. The first sustain electrode2153of the second pixel circuit portion PC2may overlap the gate electrode2151of the second pixel circuit portion PC2. The first sustain electrode3153of the driving circuit portion DR may overlap the gate electrode3151of the driving circuit portion DR.

A first interlayer insulating layer160may be disposed on the first sustain electrode2153of the second pixel circuit portion PC2and the first sustain electrode3153of the driving circuit portion DR. The source electrode2173and the drain electrode2175of the second pixel circuit portion PC2and the source electrode3173and the drain electrode3175of the driving circuit portion DR may be disposed on the first interlayer insulating layer160. The source electrode2173and the drain electrode2175of the second pixel circuit portion PC2and the source electrode3173and the drain electrode3175of the driving circuit portion DR may be disposed in the first data conductive layer.

The first interlayer insulating layer160may include an opening2161that overlaps the source electrode2173of the second pixel circuit portion PC2and the first region2131of the semiconductor2130. The source electrode2173of the second pixel circuit portion PC2may be connected with the first region2131of the semiconductor2130through the opening2161. The first interlayer insulating layer160may include an opening2162that overlaps the drain electrode2175of the second pixel circuit portion PC2and the second region2133of the semiconductor2130

The drain electrode2175of the second pixel circuit portion PC2may be connected with the second region2133of the semiconductor2130through the opening2162. Similarly, the source electrode3173of the driving circuit portion DR may be connected to a first region of the semiconductor3130, and the drain electrode3175may be connected to a second region of the semiconductor3130.

The first data conductive layer may further include an initialization voltage line127. The initialization voltage line127may transmit an initialization voltage Vint. The initialization voltage Vint is formed as a constant voltage. That is, a constant voltage is applied to the initialization voltage line127.

The first protective layer180may be disposed on the source electrode2173and the drain electrode2175of the second pixel circuit portion PC2and the source electrode3173and the drain electrode3175of the driving circuit portion DR.

The connection electrode520of the second pixel circuit portion PC2may be disposed on the first protective layer180. The connection electrode520of the second pixel circuit portion PC2may be disposed in the second data conductive layer. The first protective layer180may include an opening that overlaps the drain electrode2175of the second pixel circuit portion PC2. The connection electrode520of the second pixel circuit portion PC2may be connected with the drain electrode2175through the opening.

The second data conductive layer may further include a shield electrode530. The first protective layer180may include an opening that overlaps the initialization voltage line127. The shield electrode530may be connected with the initialization voltage line127through the opening. The shield electrode530may overlap the driving circuit portion DR, and may cover the driving circuit portion DR. The shield electrode530may receive the initialization voltage Vint through the initialization voltage line127.

The shield electrode530may be disposed between the driving circuit portion DR and the second emitting diode ED2. The second emitting diode ED2may overlap the driving circuit portion DR, and may be affected by the voltage applied to the driving circuit portion DR. In the display device according to the embodiment, the effect of the driving circuit portion DR on the second emitting diode ED2may be shielded by the shield electrode530to which a constant voltage such as the initialization voltage Vint is applied. It has been described above that the shield electrode530is connected to the initialization voltage line127, but is not limited thereto. The shield electrode530may be connected to another wire, and a constant voltage may be applied to the shield electrode530. For example, the shield electrode530may be connected to a wire to which a common voltage ELVSS is applied.

A second interlayer insulating layer162may be disposed on the connection electrode520of the second pixel circuit portion PC2. A part of the connection electrode520of the second pixel circuit portion PC2may be covered by the second interlayer insulating layer162, and another part of the connection electrode520of the second pixel circuit portion PC2may be covered by the second protective layer182.

An extension wire600may be disposed on the second interlayer insulating layer162. The extension wire600may be connected to the connection electrode520of the second pixel circuit portion PC2, and a connection relationship therebetween will be described in more detail with reference toFIG.5. The extension wire600and the second interlayer insulating layer162may be simultaneously patterned by using the same mask. Thus, the extension wire600may have a planar shape substantially equivalent to the second interlayer insulating layer162. The extension wire600may be disposed only in the second display area DA2and may not be disposed in the first display area DA1. The second interlayer insulating layer162may also be disposed only in the second display area DA2and may not be disposed in the first display area DA1. Thus, the second interlayer insulating layer162may at least partially overlap the second pixel circuit portion PC2and the second emitting diode ED2, and may not overlap the first pixel circuit portion PC1and the first emitting diode ED1at all. By simultaneously patterning the extension wire600and the second interlayer insulating layer162, the number of masks used in the process of manufacturing the display device according to the embodiment can be reduced. Accordingly, it is possible to reduce process cost, time, and the like. The extension wire600may overlap a portion of an edge of the connection electrode520of the second pixel circuit portion PC2. The second interlayer insulating layer162is disposed between the extension wire600and the connection electrode520of the second pixel circuit portion PC2, and the extension wire600and the connection electrode520of the second pixel circuit portion PC2are not directly connected to each other. The extension wire600may also overlap the shield electrode530. The second interlayer insulating layer162is disposed between the extension wire600and the shield electrode530. The extension wire600and the shield electrode530may be insulated by the second interlayer insulating layer162.

The second protective layer182is disposed on the connection electrode520of the second pixel circuit portion PC2and the extension wire600. The second protective layer182includes an overlapping portion of the connection electrode520and the extension wire600of the second pixel circuit portion PC2, and an opening2183overlapping the periphery thereof. A bridge electrode195may be disposed on the second protective layer182. The bridge electrode195may be disposed on the same layer as the pixel electrode1191of the first emitting diode ED1. The bridge electrode195is disposed in the opening2183, and may be connected to the connection electrode520of the second pixel circuit portion PC2and the extension wire600in the opening2183. Accordingly, the extension wire600and the connection electrode520of the second pixel circuit portion PC2may be connected by the bridge electrode195.

The second emitting diode ED2connected to the second pixel circuit portion PC2may be disposed on the second protective layer182. The second emitting diode ED2may include a pixel electrode2191, an emission layer2370, and a common electrode270.

The pixel electrode2191of the second emitting diode ED2may be disposed on the second protective layer182. The pixel electrode2191of the second emitting diode ED2may be disposed on the same layer as the pixel electrode1191of the first emitting diode ED1and the bridge electrode195. The second protective layer182may include an opening2181overlapping the pixel electrode2191of the second emitting diode ED2and the extension wire600. The pixel electrode2191of the second emitting diode ED2may be connected to the extension wire600through the opening2181. The extension wire600may be connected to the second pixel circuit portion PC2through the bridge electrode195. Accordingly, the extension wire600may connect between the second pixel circuit portion PC2and the second emitting diode ED2. The second emitting diode ED2may be far apart from the second pixel circuit portion PC2connected to the second emitting diode ED2without overlapping it. The extension wire600may connect the second emitting diode ED2and the second pixel circuit portion PC2that are spaced apart from each other.

For comparison with the display device according to the embodiment, a display device according to a reference example, which does not include an extension wire, may be considered. In the display device according to the reference example, a pixel electrode2191of a second emitting diode ED2may be extended to be connected to a second pixel circuit portion PC2that is disposed far away. In this case, the pixel electrode2191may extend long, and it may cause complication in a process of designing the pixel electrode2191to bypass to thereby prevent collision with adjacent pixels, and short circuit defects may occur. In the display device according to the embodiment, the second pixel circuit portion PC2and the second emitting diode ED2are connected through the extension wire600disposed on a different layer from the pixel electrode2191of the second emitting diode ED2, and thus wiring can be simplified and short circuit failure can be prevented.

The partitioning wall350may be disposed on the pixel electrode2191of the second emitting diode ED2. A pixel opening2351is formed in the partitioning wall350, and the pixel opening2351of the partitioning wall350may overlap the pixel electrode2191.

The emission layer2370of the second emitting diode ED2may be disposed within the pixel opening2351of the partitioning wall350. The emission layer2370may overlap the pixel electrode2191.

The common electrode270may be disposed on the emission layer2370and the partitioning wall350. The common electrode270of the second emitting diode ED2and the common electrode270of the first emitting diode ED1may be formed integrally, and may be entirely disposed in most regions on the substrate110.

The second emitting diode ED2emits light around a region where the pixel electrode2191, the emission layer2370, and the common electrode270overlap, and the light emitting region of the second emitting diode ED2may or may not overlap with the second pixel circuit portion PC2connected thereto.

In the second display area DA2, the second pixel circuit portion PC2and the second emitting diode ED2are disposed in a matrix format along the first direction DR1and the second direction DR2, respectively. In this case, the second pixel circuit portion PC2disposed in the first row and first column may be connected with the second emitting diode ED2disposed in the first row and first column, but they do not overlap each other. That is, a light emitting region of the second emitting diode ED2may not overlap a second pixel circuit portion PC2connected thereto. The second emitting diode ED2and the second pixel circuit portion PC2spaced apart from each other without overlapping may be connected by an extension wire600.

In addition, the second pixel circuit portion PC2disposed in the first row and second column is connected with the second emitting diode ED2disposed in the first row and second column, but a light emitting region of the second emitting diode ED2does not overlap a second pixel circuit portion PC2connected thereto. In addition, the second pixel circuit portion disposed in the second row and first column is connected with the second emitting diode ED2disposed in the second row and first column, but does not overlap a second pixel circuit portion PC2connected thereto. In addition, the second pixel circuit portion PC2disposed in the second row and second column is connected with the second emitting diode ED2disposed in the second row and second column, but does not overlap a second pixel circuit portion PC2connected thereto.

However, some light emitting regions of the second emitting diode ED2may overlap with the second pixel circuit portion PC2that is not connected thereto. For example, a light emitting region of the second emitting diode ED2disposed in the first row and fourth column may overlap the second pixel circuit portion PC2disposed in the first row and first column. In addition, a light emitting region of the second emitting diode ED2disposed in the first row and fifth column may overlap the second pixel circuit portion PC2disposed in the first row and third column. In addition, a light emitting region of the second emitting diode ED2disposed in the first row and sixth column may overlap the second pixel circuit portion PC2disposed in the first row and fifth column.

In addition, light emitting regions of some second emitting diode ED2may overlap with the second pixel circuit portion PC2connected thereto. For example, a light emitting region of the second emitting diode ED2disposed in the second row and sixth column may overlap the second pixel circuit portion PC2disposed in the second row and sixth column.

In this case, each of the second emitting diodes ED2may display at least one of a first color, a second color, and a third color. For example, the second emitting diode ED2may include red R, green G, and blue B colors. In this case, the second emitting diode ED2displaying red R and the second emitting diode ED2displaying blue B may be iteratively disposed in the first and third rows. The second emitting diode ED2displaying green G may be disposed in the second and fourth rows.

In the display device according to the embodiment, the second emitting diode ED2is disposed not only in the region where the second pixel circuit portion PC2is disposed but also in a region where the driving circuit portion DR is disposed, thereby expanding a region where the screen is displayed. Accordingly, the pixel density in the second display area DA2may be relatively lower than the pixel density in the first display area DA1. In this case, the size of the second emitting diode ED2may be increased to increase the luminance of the second emitting diode ED2to compensate for the decreased pixel density. Accordingly, in order to supply more current to the second emitting diode ED2, the size of each element such as a storage capacitor included in the second pixel circuit portion PC2may be increased. That is, the area occupied by the second pixel circuit portion PC2may be widened. For example, the area of the second pixel circuit portion PC2may be about twice the area of the first pixel circuit portion PC1. In this case, the area of the second emitting diode ED2may be about twice the area of the first emitting diode ED1. However, this is only an example, and the area of the second pixel circuit portion PC2and the second emitting diode ED2may be set in various ways.

Although one transistor of each pixel has been described above, each pixel may include a plurality of transistors. Hereinafter, an example of a pixel of a display device according to an embodiment will be described.

FIG.6is a circuit diagram of a pixel of a display device according to an embodiment.

As shown inFIG.6, a display device according to an embodiment includes a plurality of pixels PX that can display an image, and a plurality of signal lines127,151,152,153,154,171, and172connected to the plurality of pixels PX. Each pixel may include a plurality of transistors T1, T2, T3, T4, T5, T6, and T7connected to the plurality of signal lines127,151,152,153,154,171, and172, a capacitor Cst, and at least one light emitting diode LED. In the present embodiment, it will be exemplarily described that one pixel PX includes one light emitting diode LED.

The signal lines127,151,152,154,155,171, and172may include an initialization voltage line127, a plurality of scan lines151,152, and154, a light emission control line155, a data line171, and a driving voltage line172.

The initialization voltage line127may transmit an initialization voltage Vint. Each of the plurality of scan lines151,152, and154may transmit scan signals GWn, GIn, and GI(n+1). The scan signals GWn, GIn, and GI(n+1) may transmit a gate-on voltage and a gate-off voltage that can turn-on/turn-off the transistors T2, T3, T4, and T4included in the pixel PX.

The scan lines151,152, and154connected to one pixel PX may include a first scan line151that may transmit a scan signal GWn, a second scan line152that can transmit a scan signal GIn having a gate-on voltage at different timing to that of the first scan line151, and the third scan line154that may transmit a scan signal GI(n+1). In the present embodiment, an example in which the second scan line152transmits the gate-on voltage at a timing earlier than the first scan line151will be mainly described. For example, when the scan signal GWn is an n-th scan signal Sn (n is a natural number greater than1) among scan signals applied during one frame, the scan signal Gin may be a previous scan signal such as a scan signal S(n-1) and the scan signal GI(n+1) may be the n-th scan signal Sn. However, the present embodiment is not limited thereto, and the scan signal GI(n+1) may be a scan signal that is different from the n-th scan signal Sn.

The light emission control line155may transmit a control signal, particularly, a light emission control signal EM that is capable of controlling light emission of the light emitting diode LED included in the pixel PX. The control signal transmitted by the light emission control line155may transmit a gate-on voltage and a gate-off voltage, and may have a waveform that is different from the scan signal transmitted by the scan lines151,152, and154.

The data line171may transmit a data signal Dm, and the driving voltage line172may transmit a driving voltage ELVDD

The data signal Dm may have a different voltage level according to an image signal input to the display device, and the driving voltage ELVDD may substantially have a constant level.

The display device may further include a driver that transmits signals to the plurality of signal lines127,151,152,153,154,171, and172.

The plurality of transistors T1, T2, T3, T4, T5, T6, and T7included in one pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

The first scan line151may transmit the scan signal GWn to the second transistor T2and the third transistor T3, the second scan line152may transmit the scan signal Gin to the fourth transistor T4, the third scan line154may transmit the scan signal GI(n+1) to the seventh transistor T7, and the light emission control line155may transmit the light emission control signal EM to the fifth transistor T5and the sixth transistor T6.

A gate electrode G1of the first transistor T1is connected with one end of the capacitor Cst through a driving gate node GN, a first electrode Ea1of the first transistor T1is connected with the driving voltage line172via the fifth transistor T5, and a second electrode Eb1of the first transistor T1is connected with an anode of the light emitting diode LED via the sixth transistor T6. The first transistor T1may receive the data signal Dm transmitted from the data line171according to the switching operation of the second transistor T2and supply a driving current Id to the light emitting diode LED.

A gate electrode G2of the second transistor T2is connected with the first scan line151, a first electrode Ea2of the second transistor T2is connected with the data line171, and a second electrode Eb2of the second transistor T2is connected with the first electrode Ea1of the first transistor T1and is connected with the driving voltage line172via the fifth transistor T5. The second transistor T2is turned on according to the scan signal GWn transmitted through the first scan line151and transmits the data signal Dm transmitted from the data line171to the first electrode Ea1of the first transistor T1.

A gate electrode G3of the third transistor T3is connected with the first scan line151, and a first electrode Ea3of the third transistor T3is connected with the second electrode Eb1of the first transistor T1and connected with an anode of the light emitting diode LED via the sixth transistor T6. A second electrode Eb3of the third transistor T3is connected to a second electrode Eb4of the fourth transistor T4, a first end of the capacitor Cst, and the gate electrode G1of the first transistor T1. The third transistor T3is turned on according to the scan signal GWn transmitted through the first scan line151, and may diode-connect the first transistor T1by connecting the gate electrode G1and the second electrode Eb1of the first transistor T1.

A gate electrode G4of the fourth transistor T4is connected with the second scan line152, a first electrode Ea4of the fourth transistor T4is connected with the initialization voltage Vint terminal of the initialization voltage Vint terminal, and a second electrode Eb4of the fourth transistor T4is connected with the first end of the capacitor Cst and the gate electrode G1of the first transistor T1through the second electrode Eb3of the third transistor T3. The fourth transistor T4is turned on according to the scan signal Gin transmitted through the second scan line152and transmits the initialization voltage Vint to the gate electrode G1of the first transistor T1such that a voltage of the gate electrode G1of the first transistor T1can be initialized.

A gate electrode G5of the fifth transistor T5is connected with the light emission control line155, a first electrode Ea5of the fifth transistor T5is connected with the driving voltage line172, and a second electrode Eb5of the fifth transistor T5is connected with the first electrode Ea1of the first transistor T1and the second electrode Eb2of the second transistor T2.

A gate electrode G6of the sixth transistor T6is connected with the light emission control line155, a first electrode Ea6of the sixth transistor T6is connected with the second electrode Eb1of the first transistor T1and the first electrode Ea3of the third transistor T3, and a second electrode Eb6of the sixth transistor T6is electrically connected with the anode of the light emitting diode LED. The fifth transistor T5and the sixth transistor T6are simultaneously turned on according to the light emission control signal transmitted through the light emission control line155and thus the driving voltage ELVDD is compensated through the diode-connected first transistor T1and then transmitted to the light emitting diode LED.

A gate electrode G7of the seventh transistor T7is connected with the third scan line154, a first electrode Ea7of the seventh transistor T7is connected with the second electrode Eb6of the sixth transistor T6and the anode of the light emitting diode LED, and a second electrode Eb7of the seventh transistor T7is connected with the terminal of the initialization voltage Vint and the first electrode Ea4of the fourth transistor T4.

The transistors T1, T2, T3, T4, T5, T6, and T7may be P-type channel transistors such as PMOS, but are not limited thereto, and among the transistors T1, T2, T3, T4, T5, T6, and T7, at least one may be an N-type channel transistor.

The first end of the capacitor Cst is connected to the gate electrode G1of the first transistor T1and a second end is connected to the driving voltage line172as described above. A cathode of the light emitting diode LED may be connected to a terminal of a common voltage ELVSS, which transmits the common voltage ELVSS, and thus may receive the common voltage ELVSS.

Pixels PX disposed in the first display area DA1and pixels PX disposed in the second display area DA2both may have the circuit structure of the pixel shown inFIG.6. However, the present invention is not limited thereto, and the circuit structure of the pixel PX disposed in the first display area DA1may be different from the circuit structure of the pixel PX disposed in the second display area DA2. The circuit diagram of the pixel shown inFIG.6is only an example, and the number of transistors, the number of capacitors, and their connection relationship included in one pixel PX of the display device according to the embodiment can be variously changed.

Next, a display device according to an embodiment will be described with reference toFIG.7.

A display device according to an embodiment shown inFIG.7is almost the same as the display device according to the embodiment shown inFIG.1toFIG.6, and therefore the same parts will not be described. The present embodiment is different from the previous embodiment in that a bridge electrode is not formed, and will be described further below.

FIG.7is a cross-sectional view of a display device according to an embodiment.FIG.7illustrates a second pixel circuit portion PC2and a second emitting diode ED2disposed in a second display area DA2. Although it is not illustrated, the second emitting diode ED2may overlap a driving circuit portion, and a shield electrode may be disposed between the second emitting diode ED2and the driving circuit portion.

As shown inFIG.7, a display device according to an embodiment includes a substrate110, the second pixel circuit portion PC2disposed on the substrate110, and the second emitting diode ED2connected to the second pixel circuit portion PC2.

The second pixel circuit portion PC2includes a semiconductor2130, a gate electrode2151, a source electrode2173, and a drain electrode2175which are disposed on the substrate110. The second pixel circuit portion PC2may further include a connection electrode520, and the connection electrode520may be connected with the drain electrode2175.

A second interlayer insulating layer162may be disposed on the connection electrode520, and an extension wire600may be disposed on the second interlayer insulating layer162. In the previous embodiment, the second interlayer insulating layer162may be disposed only below the extension wire600, and in the present embodiment, the second interlayer insulating layer162may be disposed not only under the extension wire600but also entirely. That is, the second interlayer insulating layer162may be entirely disposed on the first display area DA1and the second display area DA2of the substrate110. In the previous embodiment, the second interlayer insulating layer162and the extension wire600may be patterned simultaneously with the same mask, and in the present embodiment, the second interlayer insulating layer162and the extension wire600may be patterned separately by using different masks, respectively.

The second interlayer insulating layer162may include an opening that overlaps the connection electrode520, and the extension wire600may be connected with the connection electrode520through the opening. In the previous embodiment, the extension wire600and the connection electrode520are not directly connected, but may be connected through a bridge electrode. In the present embodiment, the bridge electrode is not formed, and the extension wire600and the connection electrode520can be directly connected.

A second protective layer182may be disposed on the second interlayer insulating layer162and the extension wire600, and the second emitting diode ED2connected with the second pixel circuit portion PC2may be disposed on the second protective layer182. The second emitting diode ED2may include a pixel electrode2191, an emission layer2370, and a common electrode270. The pixel electrode2191of the second emitting diode ED2may be connected with the second pixel circuit portion PC2through the pixel electrode2191.

In the display device according to the present embodiment, the second pixel circuit portion PC2and the second emitting diode ED2are connected through the extension wire600disposed on a different layer from the pixel electrode2191of the second emitting diode ED2, thereby simplifying the wire and preventing a short circuit failure.

Next, referring toFIG.8, a display device according to an embodiment will be described.

A display device according to an embodiment shown inFIG.8is almost the same as the display device according to the embodiment shown inFIG.7, and therefore, the same parts will not be described. The present embodiment is different from the previous embodiment in that a plurality of second emitting diodes ED2are connected to one second pixel circuit portion PC2, and this will be described in detail.

FIG.8is a cross-sectional view of a display device according to an embodiment.FIG.8illustrate a second pixel circuit portion PC2and a second emitting diode ED2that are disposed in a second display area DA2. Although it is not illustrated, the second emitting diode ED2may overlap a driving circuit portion, and a shield electrode may be disposed between the second emitting diode ED2and the driving circuit portion.

As shown inFIG.8, a display device according to an embodiment includes a substrate110, the second pixel circuit portion PC2disposed on the substrate110, and the second emitting diode ED2connected to the second pixel circuit portion PC2.

In the previous embodiment, one second pixel circuit portion PC2may be connected to one second emitting diode ED2. In the present embodiment, one second pixel circuit portion PC2may be connected to a plurality of second emitting diodes ED2.

For example, each second pixel circuit portion PC2of the display device according to the present embodiment may be connected with two second emitting diodes ED2. A drain electrode2175of the second pixel circuit portion PC2is connected with a connection electrode520, and the connection electrode520may be connected with an extension wire600. The extension wire600may be two pixel electrodes2191that are separated from each other. A second protective layer182may be disposed on the extension wire600, and the second protective layer182may include a plurality of openings2181that partially overlap the extension wire600. A plurality of pixel electrodes2191may be separately disposed on the second protective layer182. Two separated pixel electrodes2191may be connected with the same extension wire600through the opening2181. An emission layer2370and a common electrode270are respectively disposed on the two pixel electrodes2191such that two second light emitting diodes ED2are formed. Thus, one second pixel circuit portion PC2may be connected to two light emitting diodes ED2through the extension wire600.

However, the number of second light emitting diodes ED2connected to one second pixel circuit portion PC2is not limited thereto, and each second pixel circuit portion PC2may be connected to three or more second light emitting diodes ED2.

In addition, the extension wire600is connected to two separated pixel electrodes2191in the present embodiment, but the present embodiment is not limited thereto. The extension wire600may be connected to a single pixel electrode2191, and the pixel electrode2191connected to the extension wire600is extended to two or more points to form two or more second emitting diodes ED2.

The plurality of pixel electrodes2191connected to the second pixel circuit portion PC2may be applied with the same signal. Thus, the plurality of second light emitting diodes ED2connected to the second pixel circuit portion PC2may emit with the same luminance. In the display device according to the present embodiment, a single second pixel circuit portion PC2is connected to a plurality of second light emitting diodes ED2such that the number of second light emitting diodes ED2can be increased. Accordingly, it is possible to prevent a boundary between a first display area DA1and a second display area DA2from being visually recognized according to a difference in resolution between the first display area DA1and the second display area DA2.

Next, a display device according to an embodiment will be described with reference toFIG.9.

A display device according to an embodiment shown inFIG.9is almost the same as the display device according to the embodiment shown inFIG.1toFIG.6, and therefore the same parts will not be described. The present embodiment is different from the previous embodiment in that a plurality of second emitting diodes ED2are connected to one second pixel circuit portion PC2, and this will be described in detail.

FIG.9is a cross-sectional view of a display device according to an embodiment.FIG.9illustrates a second pixel circuit portion PC2and a second emitting diode ED2disposed in a second display area DA2. Although it is not illustrated, the second emitting diode ED2may overlap a driving circuit portion, and a shield electrode may be disposed between the second emitting diode ED2and the driving circuit portion.

As shown inFIG.9, a display device according to an embodiment includes a substrate110, the second pixel circuit portion PC2disposed on the substrate110, and the second emitting diode ED2connected to the second pixel circuit portion PC2.

In the previous embodiment, one second pixel circuit portion PC2may be connected to one second emitting diode ED2. In the present embodiment, one second pixel circuit portion PC2may be connected with a plurality of second emitting diodes ED2.

For example, each second pixel circuit portion PC2of the display device according to the present embodiment may be connected with two second emitting diodes ED2. A drain electrode2175of the second pixel circuit portion PC2is connected with a connection electrode520, and the connection electrode520may be connected with an extension wire600through a bridge electrode195. The extension wire600may be two pixel electrodes2191that are separated from each other. An emission layer2370and a common electrode270are respectively disposed on the two pixel electrodes2191such that two second light emitting diodes ED2are formed. Thus, one second pixel circuit portion PC2may be connected to two light emitting diodes ED2through the extension wire600. However, this is not restrictive, and one second pixel circuit portion PC2may be connected to three or more second emitting diodes ED2. In addition, the extension wire600may be connected to a single pixel electrode2191, and the pixel electrodes2191connected to the extension wire600may extend to two or more points such that two or more second emitting diodes ED2can be formed.

In the display device according to the present embodiment, one second pixel circuit portion PC2is connected to a plurality of second emitting diodes ED2such that the number of second emitting diodes ED2can be increased. Thus, it is possible to prevent a boundary between a first display area DA1and a second display area DA2from being viewed according to a difference in resolution between the first display area DA1and the second display area DA2.

In the display device according to the embodiment shown inFIG.8andFIG.9, one second pixel circuit portion PC2is connected to a plurality of second emitting diodes ED2. In this case, the plurality of second emitting diodes ED2can be variously arranged, and various alignments of the second emitting diodes ED2will be described hereinafter with reference toFIG.10toFIG.21.

First, referring toFIG.10andFIG.11, a connection relationship and alignment form of a plurality of second emitting diode ED2of a display device according to an embodiment will be described.

FIG.10is a top plan view of a connection relationship of a plurality of second light emitting diodes of a display device according to an embodiment, andFIG.11shows an alignment form of second pixel circuit portions and an alignment form of second emitting diodes of the display device according to the embodiment. InFIG.11, the second pixel circuit portion PC2and the second emitting diode ED2are separately illustrated for description, but actually, the second pixel circuit portion PC2may overlap a part of the second emitting diode ED2.

As shown inFIG.10andFIG.11, a plurality of second emitting diodes ED2may be arranged in a row direction and a column direction on a second display area of a substrate of a display device according to an embodiment. For example, a second emitting diode ED2displaying red R, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying blue B, and a second emitting diode ED2displaying green G may be sequentially arranged in a first row and a third row. A second emitting diode ED2displaying blue B, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying R, and a second emitting diode ED2displaying green G may be sequentially arranged in a second row and a fourth row.

The second emitting diode ED2displaying red R, disposed in the first row and the first column and the second emitting diode ED2displaying red R, disposed in the second row and the third column may be connected with each other. The second emitting diode ED2displaying green G, disposed in the first row and the second column and the second emitting diode ED2displaying green G, disposed in the second row and the second column may be connected with each other. The second emitting diode ED2displaying blue B disposed in the first row and third column and the second emitting diode ED2displaying blue B disposed in the second row and first column may be connected to each other. The second emitting diode ED2displaying green G disposed in the first row and fourth column and the second emitting diode ED2displaying green G disposed in the second row and fourth column may be connected to each other. Similarly, a plurality of second emitting diodes ED2displaying the same color among the second emitting diodes ED2disposed in the third and fourth rows may be connected to each other.

The plurality of second emitting diodes ED2may be connected to each other by an extension wire or may be connected to each other by a pixel electrode.

A plurality of second pixel circuit portions PC2may be arranged in a row direction and a column direction on the second display area of the substrate of the display device according to the embodiment. Each of the second pixel circuit portions PC2may be connected with a plurality of second emitting diodes ED2. One second pixel circuit portion PC2may be connected with two second emitting diodes ED2. For example, a second pixel circuit portion PC2disposed in the first row and the first column is connected with the second emitting diode ED2disposed in the first row and the first column and the second emitting diode ED2disposed in the second row and the third column and thus may transmit the same signal R11. Thus, the second emitting diode ED2disposed in the first row and the first column and the second emitting diode ED2disposed in the second row and the second column may have the same luminance. In addition, the second pixel circuit portion PC2disposed in the first row and the second column is connected with the second emitting diode ED2disposed in the first row and the second column and the second emitting diode ED2disposed in the second row and the second column and thus may transmit the same signal G12. In addition, the second pixel circuit portion PC2disposed in the second row and the first column is connected with the second emitting diode ED2disposed in the first row and the third column and the second emitting diode ED2disposed in the second row and the first column and thus may transmit the same signal B21. In addition, the second pixel circuit portion PC2disposed in the second row and the second column is connected with the second emitting diode ED2disposed in the first row and the fourth column and the second emitting diode ED2disposed in the second row and the fourth column and thus may transmit the same signal G22. Similarly, each second pixel circuit portion PC2disposed in the third and fourth rows may be connected to a plurality of second emitting diodes ED2to transmit the same signal.

For the signal transmitted to the second emitting diode ED2, a value calculated through rendering may be used. The size or disposition interval of the second emitting diodes ED2may be similar to those of the first emitting diode. Accordingly, it is possible to prevent the boundary between the first display area DA1and the second display area DA2from being viewed.

Next, referring toFIG.12andFIG.13, a connection relationship and alignment form of a plurality of second emitting diode ED2of a display device according to an embodiment will be described.

FIG.12is a top plan view of a connection relationship of a plurality of second light emitting diodes of a display device according to an embodiment, andFIG.13shows an alignment form of second pixel circuit portions and an alignment form of second emitting diodes of the display device according to the embodiment. InFIG.13, the second pixel circuit portion PC2and the second emitting diode ED2are separately illustrated for description, but actually, the second pixel circuit portion PC2may overlap a part of the second emitting diode ED2.

As shown inFIG.12andFIG.13, a plurality of second emitting diodes ED2may be arranged in a row direction and a column direction on a second display area of a substrate of a display device according to an embodiment. For example, a second emitting diode ED2displaying red R, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying blue B, and a second emitting diode ED2displaying green G may be sequentially arranged in a first row and a third row. A second emitting diode ED2displaying blue B, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying R, and a second emitting diode ED2displaying green G may be sequentially arranged in a second row and a fourth row.

The four second emitting diodes ED2displaying R, disposed in the first row and the first column, the first row and a fifth column, the second row and the third column, and the second row and a seventh column may be connected with each other. The fourth second emitting diodes ED2disposed in the first row and second column, the first row and fourth column, and second row and second column, and the second row and fourth column and displaying green G may be connected with each other. The fourth second emitting diodes ED2displaying blue B and disposed in the first row and third column, the first row and seventh column, the second row and first column, and the second row and fifth column may be connected with each other. The four second emitting diodes ED2displaying green G and disposed in the first row and sixth column, the first row and eighth column, the second row and sixth column, and the second row and eighth column may be connected with each other. Similarly, a plurality of second emitting diodes ED2displaying the same color among the second emitting diodes ED2disposed in the third and fourth rows may be connected to each other.

The plurality of second emitting diodes ED2may be connected to each other by an extension wire or may be connected to each other by a pixel electrode.

A plurality of second pixel circuit portions PC2may be arranged in a row direction and a column direction on the second display area of the substrate of the display device according to the embodiment. Each of the second pixel circuit portions PC2may be connected with a plurality of second emitting diodes ED2. One second pixel circuit portion PC2may be connected with four second emitting diodes ED2. For example, the second pixel circuit portion PC2disposed in the first row and first column may be connected with the second emitting diodes ED2disposed in the first row and first column, the first row and fifth column, the second row and third column, and the second row and seventh column and thus may transmit the same signal R11. In addition, the second pixel circuit portion PC2disposed in the first row and second column may be connected with the second emitting diodes ED2disposed in the first row and second column, the first row and fourth column, the second row and second column, and the second row and fourth column and thus may transmit the same signal G12. In addition, the second pixel circuit portion PC2disposed in the second row and firth column may be connected with the second emitting diodes ED2disposed in the first row and third column, the first row and seventh column, the second row and first column, and the second row and fifth column and thus may transmit the same signal B21. In addition, the second pixel circuit portion PC2disposed in the second row and second column may be connected with the second emitting diodes ED2disposed in the first row and sixth column, the first row and eighth column, the second row and sixth column, and the second row and eighth column and thus may transmit the same signal G22. Similarly, each second pixel circuit portion PC2disposed in the third and fourth rows may be connected to a plurality of second emitting diodes ED2to transmit the same signal.

For the signal transmitted to the second emitting diode ED2, a value calculated through rendering may be used. The size or disposition interval of the second emitting diodes ED2may be similar to those of the first emitting diode. Accordingly, it is possible to prevent the boundary between the first display area DA1and the second display area DA2from being viewed.

Next, referring toFIG.14andFIG.15, a connection relationship and alignment form of a plurality of second emitting diodes ED2of a display device according to an embodiment will be described.

FIG.14is a top plan view of a connection relationship of a plurality of second light emitting diodes of a display device according to an embodiment, andFIG.15shows an alignment form of second pixel circuit portions and an alignment form of second emitting diodes of the display device according to the embodiment. InFIG.15, the second pixel circuit portion PC2and the second emitting diode ED2are separately illustrated for description, but actually, the second pixel circuit portion PC2may overlap a part of the second emitting diode ED2.

As shown inFIG.14andFIG.15, a plurality of second emitting diodes ED2may be arranged in a row direction and a column direction on a second display area of a substrate of a display device according to an embodiment. For example, a second emitting diode ED2displaying red R, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying blue B, and a second emitting diode ED2displaying green G may be sequentially arranged in a first row and a third row. A second emitting diode ED2displaying blue B, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying R, and a second emitting diode ED2displaying green G may be sequentially arranged in a second row and a fourth row.

Two second emitting diodes ED2disposed in a first row and first column and a first row and third column and displaying red R may be connected with each other. Two second emitting diodes ED2disposed in the first row and second column and the second row and second column and displaying red R may be connected with each other. Two second emitting diodes ED2disposed in the first row and third column and the second row and first column may be connected with each other. Two second emitting diodes ED2disposed in the first row and fourth column and the second row and fourth column and displaying green G may be connected with each other. Similarly, a plurality of second emitting diodes ED2displaying the same color among the second emitting diodes ED2disposed in the third and fourth rows may be connected to each other.

The plurality of second emitting diodes ED2may be connected to each other by an extension wire or may be connected to each other by a pixel electrode.

A plurality of second pixel circuit portions PC2may be arranged in a row direction and a column direction on the second display area of the substrate of the display device according to the embodiment. Each of the second pixel circuit portions PC2may be connected with a plurality of second emitting diodes ED2. One second pixel circuit portion PC2may be connected with two second emitting diodes ED2. The second pixel circuit portion PC2disposed in the first row and first column is connected with the second emitting diodes ED2disposed in the first row and first column and the second row and third column and thus may transmit the same signal R11. In addition, the second pixel circuit portion PC2disposed in the first row and second column may be connected with the second emitting diodes ED2disposed in the first row and second column and the second row and second column and thus may transmit the same signal G12. In addition, the second pixel circuit portion PC2disposed in the first row and third column may be connected with the second emitting diodes ED2disposed in the first row and third column and the second row and first column and thus may transmit the same signal B13. In addition, the second pixel circuit portion PC2disposed in the first row and fourth column may be connected with the second emitting diodes ED2disposed in the first row and fourth column and the second row and fourth column and thus may transmit the same signal G14. Similarly, each second pixel circuit portion PC2disposed in the third row may be connected to a plurality of second emitting diodes ED2to transmit the same signal. In the present embodiment, the second pixel circuit portions PC2are not disposed in the second row and the fourth row and accordingly, the number of scan lines can be reduced to half.

For the signal transmitted to the second emitting diode ED2, a value calculated through rendering may be used. The size or disposition interval of the second emitting diodes ED2may be similar to those of the first emitting diode. Accordingly, it is possible to prevent the boundary between the first display area DA1and the second display area DA2from being viewed.

Next, referring toFIG.16andFIG.17, a connection relationship and alignment form of a plurality of second emitting diodes ED2of a display device according to an embodiment will be described.

FIG.16is a top plan view of a connection relationship of a plurality of second light emitting diodes of a display device according to an embodiment, andFIG.17shows an alignment form of second pixel circuit portions and an alignment form of second emitting diodes of the display device according to the embodiment. InFIG.17, the second pixel circuit portion PC2and the second emitting diode ED2are separately illustrated for description, but actually, the second pixel circuit portion PC2may overlap a part of the second emitting diode ED2.

As shown inFIG.16andFIG.17, a plurality of second emitting diodes ED2may be arranged in a row direction and a column direction on a second display area of a substrate of a display device according to an embodiment. For example, a second emitting diode ED2displaying red R, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying blue B, and a second emitting diode ED2displaying green G may be sequentially arranged in a first row and a third row. A second emitting diode ED2displaying blue B, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying R, and a second emitting diode ED2displaying green G may be sequentially arranged in a second row and a fourth row.

The four second emitting diodes ED2disposed in the first row and first column, the second row and third column, the third row and first column, and the fourth row and third column and displaying red R may be connected with each other. The fourth second emitting diodes ED2disposed in the first row and second column, the first row and fourth column, the second row and second column, and the second row and fourth column and displaying green G may be connected with each other. The four second emitting diodes ED2disposed in the first row and third column, the second row and first column, the third row and third column, and the fourth row and first column and displaying blue B may be connected with each other. The four second emitting diodes ED2disposed in the third row and second column, the third row and fourth column, the fourth row and second column, and the fourth row and fourth column and displaying green G may be connected with each other. Similarly, a plurality of second emitting diodes ED2displaying the same color among the second emitting diodes ED2disposed in fifth to eighth columns may be connected with each other. In the present embodiment, the second pixel circuit portion PC2is not disposed in the second to fourth rows, and thus the number of scan lines can be reduced to one quarter.

The plurality of second emitting diodes ED2may be connected to each other by an extension wire or may be connected to each other by a pixel electrode.

A plurality of second pixel circuit portions PC2may be arranged in a row direction and a column direction on the second display area of the substrate of the display device according to the embodiment. Each of the second pixel circuit portions PC2may be connected with a plurality of second emitting diodes ED2. One second pixel circuit portion PC2may be connected with two second emitting diodes ED2. For example, the second pixel circuit portions PC2disposed in the first row and first column, the second row and third column, the third row and first column, and the fourth row and third column may be connected with the second emitting diodes ED2and thus may transmit the same signal R11. In addition, the second pixel circuit portion PC2disposed in the first row and second column may be connected with the second emitting diodes ED2disposed in the first row and second column, the first row and fourth column, the second row and second column, and the second row and fourth column and thus may transmit the same signal G12. In addition, the second pixel circuit portion PC2disposed in the first row and third column may be connected with the second emitting diodes ED2disposed in the third row and second column, the third row and fourth column, the fourth row and second column, and the fourth row and fourth column and thus may transmit the same signal B13. In addition, the second pixel circuit portion PC2disposed in the first row and fourth column may be connected with the second emitting diodes ED2disposed in the third row and second column, the third row and fourth column, the fourth row and second column, and the fourth row and fourth column and thus may transmit the same signal G14. Similarly, each second pixel circuit portion PC2disposed in fifth to eighth columns may be connected to a plurality of second emitting diodes ED2to transmit the same signal.

For the signal transmitted to the second emitting diode ED2, a value calculated through rendering may be used. The size or disposition interval of the second emitting diodes ED2may be similar to those of the first emitting diode. Accordingly, it is possible to prevent the boundary between the first display area DA1and the second display area DA2from being viewed.

Next, referring toFIG.18andFIG.19, a connection relationship and alignment form of a plurality of second emitting diode ED2of a display device according to an embodiment will be described.

FIG.18is a top plan view of a connection relationship of a plurality of second light emitting diodes of a display device according to an embodiment, andFIG.19shows an alignment form of second pixel circuit portions and an alignment form of second emitting diodes of the display device according to the embodiment. InFIG.19, the second pixel circuit portion PC2and the second emitting diode ED2are separately illustrated for description, but actually, the second pixel circuit portion PC2may overlap a part of the second emitting diode ED2.

As shown inFIG.18andFIG.19, a plurality of second emitting diodes ED2may be arranged in a row direction and a column direction on a second display area of a substrate of a display device according to an embodiment. For example, a second emitting diode ED2displaying red R, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying blue B, and a second emitting diode ED2displaying green G may be sequentially arranged in a first row and a third row. A second emitting diode ED2displaying blue B, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying R, and a second emitting diode ED2displaying green G may be sequentially arranged in a second row.

The three second emitting diodes ED2disposed in the first row and first column, the second row and third column, and the first row and fifth column and displaying red R may be connected with each other. The three second emitting diodes ED2disposed in the first row and second column, the first row and fourth column, and the first row and sixth column and displaying green G may be connected with each other. The three second emitting diodes ED2disposed in the second row and first column, the first row and third column, and the second row and fifth column and displaying blue B may be connected with each other. The three second emitting diodes ED2disposed in the second row and second column, the second row and fourth column, and the second row and sixth column and displaying green G may be connected with each other. Similarly, a plurality of second emitting diodes ED2displaying the same color among the second emitting diodes ED2disposed in seventh to twelfth columns may be connected with each other.

The plurality of second emitting diodes ED2may be connected to each other by an extension wire or may be connected to each other by a pixel electrode.

A plurality of second pixel circuit portions PC2may be arranged in a row direction and a column direction on the second display area of the substrate of the display device according to the embodiment. Each of the second pixel circuit portions PC2may be connected with a plurality of second emitting diodes ED2. One second pixel circuit portion PC2may be connected with two second emitting diodes ED2. For example, the second pixel circuit portions PC2disposed in the first row and first column, the second row and third column, the third row and first column, and the first row and fifth column may be connected with the second emitting diodes ED2and thus may transmit the same signal R11. In addition, the second pixel circuit portion PC2disposed in the first row and second column may be connected with the second emitting diodes ED2disposed in the first row and second column, the first row and fourth column, and the first row and sixth column and thus may transmit the same signal G12. In addition, the second pixel circuit portion PC2disposed in the first row and third column may be connected with the second emitting diodes ED2disposed in the second row and first column, the first row and third column, and the second row and fifth column and thus may transmit the same signal B13. In addition, the second pixel circuit portion PC2disposed in the second row and fourth column may be connected with the second emitting diodes ED2disposed in the second row and second column, the second row and fourth column, and the second row and sixth column and thus may transmit the same signal G24. Similarly, each second pixel circuit portion PC2disposed in fifth to eighth columns may be connected to a plurality of second emitting diodes ED2to transmit the same signal.

For the signal transmitted to the second emitting diode ED2, a value calculated through rendering may be used. The size or disposition interval of the second emitting diodes ED2may be similar to those of the first emitting diode. Accordingly, it is possible to prevent the boundary between the first display area DA1and the second display area DA2from being viewed.

Next, referring toFIG.20andFIG.21, a connection relationship and alignment form of a plurality of second emitting diode ED2of a display device according to an embodiment will be described.

FIG.20is a top plan view of a connection relationship of a plurality of second light emitting diodes of a display device according to an embodiment, andFIG.21shows an alignment form of second pixel circuit portions and an alignment form of second emitting diodes of the display device according to the embodiment. InFIG.21, the second pixel circuit portion PC2and the second emitting diode ED2are separately illustrated for description, but actually, the second pixel circuit portion PC2may overlap a part of the second emitting diode ED2.

As shown inFIG.20andFIG.21, a plurality of second emitting diodes ED2may be arranged in a row direction and a column direction on a second display area of a substrate of a display device according to an embodiment. For example, a second emitting diode ED2displaying red R, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying blue B, and a second emitting diode ED2displaying green G may be sequentially arranged in a first row and a third row. A second emitting diode ED2displaying blue B, a second emitting diode ED2displaying green G, a second emitting diode ED2displaying R, and a second emitting diode ED2displaying green G may be sequentially arranged in a second row.

Four second emitting diodes ED2disposed in the first row and first column, the second row and third column, the first row and fifth column, and the second row and seventh column and displaying red R may be connected with each other. Fourth second emitting diodes ED2disposed in the first row and second column, the first row and fourth column, the first row and sixth column, and the first row and eighth column and displaying green G may be connected with each other. Four second emitting diodes ED2disposed in the second row and first column, the first row and third column, the second row and fifth column, and the first row and seventh column and displaying blue B may be connected with each other. Four second emitting diodes ED2disposed in the second row and second column, the second row and fourth column, the second row and sixth column, and the second row and eighth column and displaying green G may be connected with each other. Similarly, a plurality of second emitting diodes ED2displaying the same color among the second emitting diodes ED2disposed in ninth to sixteenth columns may be connected with each other.

The plurality of second emitting diodes ED2may be connected to each other by an extension wire or may be connected to each other by a pixel electrode.

A plurality of second pixel circuit portions PC2may be arranged in a row direction and a column direction on the second display area of the substrate of the display device according to the embodiment. Each of the second pixel circuit portions PC2may be connected with a plurality of second emitting diodes ED2. One second pixel circuit portion PC2may be connected with two second emitting diodes ED2. For example, the second pixel circuit portions PC2disposed in the first row and first column, the second row and third column, the first row and fifth column, and the second row and seventh column are connected with the second emitting diodes ED2and thus may transmit the same signal R11. In addition, the second pixel circuit portion PC2disposed in the second row and second column may be connected with the second emitting diodes ED2disposed in the first row and second column, the first row and fourth column, the first row and sixth column, and the first row and eighth column and thus may transmit the same signal G22. In addition, the second pixel circuit portions PC2disposed in the first row and third column may be connected with the second emitting diodes ED2disposed in the second row and firth column, the first row and third column, and the second row and fifth column and thus may transmit the same signal B13. In addition, the second pixel circuit portion PC2disposed in the second row and fourth column may be connected with the second emitting diodes ED2disposed in the second row and second column, the second row and fourth column, the second row and sixth column, and the second row and eighth column and thus may transmit the same signal G24. Similarly, each second pixel circuit portion PC2disposed in ninth to sixteenth columns may be connected to a plurality of second emitting diodes ED2to transmit the same signal.

For the signal transmitted to the second emitting diode ED2, a value calculated through rendering may be used. The size or disposition interval of the second emitting diodes ED2may be similar to those of the first emitting diode. Accordingly, it is possible to prevent the boundary between the first display area DA1and the second display area DA2from being viewed.

Hereinafter, an image displayed on a display device according to an embodiment will be described with reference toFIG.22andFIG.23.

FIG.22shows an image displayed on a display device according to an embodiment, andFIG.23is an enlarged view of some region ofFIG.22.FIG.22andFIG.23show a case (REF) that one pixel circuit portion is connected to one emitting diode, a case (2PXL) that one pixel circuit portion is connected to two emitting diodes, a case (4PXL(vertical)) that one pixel circuit portion is connected to four adjacent emitting diodes in the vertical direction, and a case (4PXL(horizontal)) that one pixel circuit portion is connected to four adjacent emitting diode in the horizontal direction, separately. In this case, each emitting diode may have substantially the same size.

When one pixel circuit portion is connected to a plurality of emitting diodes, the resolution may be lower than when one pixel circuit portion is connected to one emitting diode. As shown inFIG.23, when the image is enlarged, it can be seen that when one pixel circuit portion is connected to a plurality of emitting diodes, the resolution is relatively low. As shown inFIG.22, in a non-enlarged state, it can be seen that such a resolution difference is hardly recognized.

Hereinafter, referring toFIG.24, an image displayed around the boundary between the first display area and the second display area of the display device according to the embodiment will be described.

FIG.24shows an image displayed on the display device according to the embodiment.FIG.24shows a case (REF) that a second display area is not included, a case (1PX) that a second pixel circuit portion is connected to one second emitting diode in the second display area and the size of the second emitting diode is relatively large, a case (4PXL) that a second pixel circuit portion is connected to four second emitting diodes in the second display area, and a case (2PXL) that a second pixel circuit portion is connected to two second emitting diodes in the second display area, separately. InFIG.24, the red dotted line indicates the boundary between the first display area and the second display area.

As shown inFIG.24, when one second pixel circuit portion is connected to one second emitting diode and the size of the second emitting diode is relatively large compared to a first emitting diode, the density of the second emitting diode in the second pixel area is lower than the density (number per unit area) of the first emitting diode in the first pixel area. Accordingly, a difference in resolution between the first pixel area and the second pixel area is recognized, and a boundary between the first pixel area and the second pixel area may be clearly displayed. When one second pixel circuit portion is connected to a plurality of second emitting diodes and the size of the second emitting diode is formed to correspond to that of the first emitting diode, the density of the first emitting diode in the first pixel area and the density of the first emitting diode in the second pixel area may be substantially equivalent. That is, although the number of signals applied per unit area in the second pixel area is reduced compared to the first pixel area, the density of the emitting diode is made substantially equivalent and the signal is applied through the rendering method such that a difference in the resolution of the area may not be recognized. Accordingly, the boundary between the first display area and the second display area may not be recognized.

Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art.