Patent ID: 12230744

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The embodiment of the application is illustrated in detail, and is plotted in the drawings. The same or the similar part is illustrated in the drawings and the specification with the same number.

FIG.1illustrates a top view of a light-emitting device1in accordance with an embodiment of the present application.FIG.2illustrates a top view pattern of each layer of the light-emitting device1in accordance with an embodiment of the present application.FIG.3illustrates a cross-sectional view taken along line a-a′ ofFIG.1.FIG.3Aillustrates a cross-sectional view taken along line A-A′ ofFIG.1.FIG.4illustrates a cross-sectional view taken along line B-B′ ofFIG.1.FIG.5illustrates a cross-sectional view taken along line C-C′ ofFIG.1. The light extraction efficiency of the light-emitting device1in the present application is improved.

As shown inFIG.1,FIG.3andFIG.3A, a light-emitting device1includes a substrate10including a top surface100, a first side surface101, a second side surface102, a third side surface103and a fourth side surface104. The first side surface101and the second side surface102of the substrate10are located at two opposite sides of the top surface100of the substrate10and not parallel to the top surface100, and the third side surface103and the fourth side surface104of the substrate10are located at another two opposite sides of the top surface100of the substrate10and not parallel to the top surface100. The first side surface101, the second side surface102, the third side surface103and the fourth side surface104form a periphery of the substrate10.

The light-emitting device1includes a semiconductor stack20formed on the top surface100of the substrate10. The semiconductor stack20includes a first semiconductor layer201, a second semiconductor layer202, and an active layer203formed between the first semiconductor layer201and the second semiconductor layer202.

In an embodiment of the present application, the substrate10can be a growth substrate, including gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or sapphire (Al2O3) wafer, gallium nitride (GaN) wafer, silicon carbide (SiC) wafer or aluminum nitride (AlN) wafer for growing gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN).

In an embodiment of the present application, a semiconductor stack20including optical characteristics and semiconductor materials is formed on the substrate10by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating, wherein physical vapor deposition (PVD) includes sputtering or evaporation.

The wavelength of the light emitted from the light-emitting device1is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack20. The material of the semiconductor stack20includes a group III-V semiconductor material, such as AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, wherein 0≤x, y≤1; (x+y)≤1. According to the material of the active layer203, when the material of the semiconductor stack20is AlInGaP series material, red light having a wavelength between 610 nm and 650 nm or yellow light having a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack20is InGaN series material, blue or deep blue light having a wavelength between 400 nm and 490 nm or green light having a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack20is AlGaN series material, UV light having a wavelength between 400 nm and 250 nm can be emitted.

The first semiconductor layer201and the second semiconductor layer202can be cladding layers, and have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer201is an n-type semiconductor and the second semiconductor layer202is a p-type semiconductor. The active layer203is formed between the first semiconductor layer201and the second semiconductor layer202. The electrons and holes combine in the active layer203under a current driving to convert electric energy into light which is then emitted from the active layer203. The active layer203can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure (MQW). The material of the active layer203can be i-type, p-type, or n-type semiconductor. The first semiconductor layer201, the second semiconductor layer202or the active layer203can be a single layer or a structure including a plurality of layers.

As shown inFIG.2andFIG.3, the semiconductor stack20is selectively etched to form a via200, a recess204and a semiconductor mesa205on the semiconductor stack20. For example, a photoresist pattern of the via200, the recess204and the semiconductor mesa205is formed by coating a photoresist and then removing a portion of the photoresist through a lithography process. The photoresist pattern is provided to form the via200, the recess204and the semiconductor mesa205. Specifically, the semiconductor mesa205is formed by removing portions of the second semiconductor layer202and the active layer203to form a structure including the first semiconductor layer201, the second semiconductor layer202, and the active layer203. The via200and the recess204are formed by removing portions of the second semiconductor layer202and the active layer203to respectively expose the first semiconductor layer201. The remaining photoresist pattern is removed after the etching process.

As shown inFIG.3, the semiconductor mesa205includes an upper surface t1 and a lower surface b1. The active layer203includes a first upper surface203tand a second lower surface203b, wherein the first upper surface203tof the active layer202is closer to the upper surface t1 of the semiconductor mesa205than the second lower surface203bof the active layer202to the upper surface t1 of the semiconductor mesa205. A first thickness is between the upper surface t1 of the semiconductor mesa205and the first upper surface203tof the active layer203, a second thickness is between the lower surface b1 of the semiconductor mesa205and the second lower surface203bof the active layer203, and the second thickness is greater than the first thickness.

As shown inFIG.1, in a top view of the light-emitting device1, the substrate10of the light-emitting device1includes a plurality of corners and a plurality of edges, wherein any one of the corners is constituted by two adjacent edges. The plurality of corners includes a first corner C1, a second corner C2, a third corner C3, and a fourth corner C4. The plurality of edges includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4.

As shown inFIG.1andFIG.2, an outer periphery205eof the semiconductor mesa205includes a first outer periphery2051eadjacent to the first edge E1 and a second outer periphery2052eadjacent to the second edge E2. In order to increase the light emitting area and the light extraction efficiency of the light-emitting device1, the first outer periphery2051eadjacent to the first edge E1 includes a first plurality of concave parts2050and a first plurality of convex parts2051as compared with the second outer periphery2052eadjacent to the second edge E2. A first plurality of concave parts2050and a first plurality of convex parts2051are alternately arranged.

As shown inFIG.1, a first space D1 between one side of the convex part2051of the first outer periphery2051eand the first edge E1 is smaller than a second space D2 between the second outer periphery2052eand the second edge E2.

A contour formed by the first plurality of concave parts2050and the first plurality of convex parts2051constitute a first outer periphery2051e. In the top view of the light-emitting device1, the first outer periphery2051eincludes a shape including wavy, zigzag or square. The position of the opening of the insulating layer, the contact layer, or the electrode layer subsequently formed may be determined according to the position arrangement of the first plurality of concave parts2050and the first plurality of convex parts2051. The light extraction efficiency of the light-emitting device can be improved by the pattern design on the side surface of the semiconductor stack20.

As shown inFIG.1andFIG.2, the corner205cof the semiconductor mesa205can be rounded to avoid the electrical current locally crowding in the corner of the light-emitting device1.

As shown inFIG.2, the recess204is located at an outermost side of the semiconductor stack20, wherein the recess204continuously or discontinuously exposes the first semiconductor layer201of the outermost side of the semiconductor stack20to continuously or discontinuously surround a portion of the first semiconductor layer201, the second semiconductor layer203, and the active layer202of the semiconductor mesa205.

In another embodiment (not shown), the recess204discontinuously exposes the first semiconductor layer201of the outermost side of the semiconductor stack20to discontinuously surround a portion of the first semiconductor layer201, the second semiconductor layer203, and the active layer202of the semiconductor mesa205.

As shown inFIG.1andFIG.2, the via200is located inside the semiconductor stack20and is surrounded by the recess204. In other words, the via200is surrounded by a portion of the first semiconductor layer201, the second semiconductor layer202, and the active layer203. In the top view of the light-emitting device1, the shape of the via200can be an ellipse, a circle, a rectangle, or any other shapes.

The light-emitting device1includes a plurality of vias200, and the amount and the arrangement of the plurality of vias200are not limited. The plurality of vias200may be regularly arranged with a regular interval so that an electrical current can be uniformly spread along the horizontal direction. The plurality of via200may be arranged in a plurality of columns to form an array. The vias200between any two adjacent columns or between every two adjacent columns may be aligned with or staggered from each other. The position of the contact layer and the electrode layer subsequently formed can be determined according to the arrangement of the plurality of vias200.

As shown inFIG.3, the via200includes a first surface S1 having an angle within a range with respect to the inner surface200sof the first semiconductor layer201, wherein the angle is between 10 and 80 degrees. The recess204includes a second surface S2 having an angle within a range with respect to the outer surface204sof the first semiconductor layer201, wherein the angle is between 10 and 80 degrees. If the angle is less than 10 degrees, an excessively low slope reduces the area of the active layer202, and a decreased area of the active layer202decreases the luminance of the light-emitting device1. If the angle is greater than 80 degrees, the insulating layer and the metal layer subsequently formed may not completely cover the sidewalls of the first semiconductor layer201, the second semiconductor layer202, and/or the active layer203, thereby causing cracking of the films.

In an embodiment of the present application, the second surface S2 includes an angle between 20 degrees and 75 degrees, preferably between 30 degrees and 65 degrees, and more preferably between 40 degrees and 55 degrees with respect to the outer surface204sof the first semiconductor layer201.

FIG.3illustrates a cross-sectional view taken along line a-a′ ofFIG.1. As shown inFIG.3, the first semiconductor layer201adjacent to the fourth edge E4 includes a first sidewall2011connected to the top surface100of the substrate10or directly connected to the fourth side surface104of the substrate10. The first semiconductor layer201adjacent to the second edge E2 includes a second sidewall2012inclined to the top surface100of the substrate10and spaced apart from the second side surface102of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10.

FIG.3Aillustrates a cross-sectional view taken along line A-A′ ofFIG.1. As shown inFIG.3A, the first semiconductor layer201adjacent to the first edge E1 includes a first sidewall2011connected to the top surface100of the substrate10, and spaced apart from the first side surface101of the substrate10by a second distance D′ to expose a portion of the top surface100of the substrate10. The first semiconductor layer201adjacent to the second edge E2 includes a second sidewall2012inclined to the top surface100of the substrate10and spaced apart from the second side surface102of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10. The second distance D′ is smaller than the first distance D.

In an embodiment of the present application, as shown inFIG.1, the first semiconductor layer201includes a plurality of first sidewalls2011and a plurality of second sidewalls2012to form a periphery of the first semiconductor layer201. The plurality of first sidewalls2011is respectively located adjacent to the first edge E1, the third edge E3, and the fourth edge E4, and the plurality of second side walls2012is respectively located adjacent to the second edge E2, the third edge E3, and the fourth edge E4. In atop view of the light-emitting device1, one of the plurality of first sidewalls2011adjacent to the third edge E3 and the fourth edge E4 is connected to one of the plurality of second sidewalls2012by a sidewall201s. The sidewall201scan be a flat surface or a curve surface. Two ends of the sidewall201sare respectively connected to the first sidewall2011and the second sidewall2012with an angle to increase the light extraction efficiency of the light-emitting device1.

In an embodiment of the present application, the first sidewall2011adjacent to the first edge E1 is spaced apart from the first side surface101of the substrate10by a second distance D′ to expose a portion of the top surface100of the substrate10. The second sidewall2012adjacent to the second edge E2 is spaced apart from the second side surface102of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10. The second distance D′ is smaller than the first distance D. The first sidewalls2011adjacent to the third edge E3 and the fourth edge E4 are directly connected to the third side surface103and the fourth side surface104of the substrate10, respectively. The second sidewalls2012adjacent to the third edge E3 and the fourth edge E4 are respectively inclined to the top surface100of the substrate10and spaced apart from the second side surface102of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10.

In an embodiment of the present application (not shown), the first sidewalls2011adjacent to the first edge E1, the third edge E3, and the fourth edge E4 are directly connected to the first side surface101, the third side surface103, and the fourth side surface104of the substrate10, respectively. The second sidewalls2012adjacent to the second edge E2, the third edge E3, and the fourth edge E4 are respectively inclined to the top surface100of the substrate10, and are spaced apart from the second side surface102, the third side surface103, and the fourth side surface104of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10.

In an embodiment of the present application (not shown), the plurality of first sidewalls2011is respectively adjacent to the first edge E1 and the third edge E3, and the plurality of second side walls2012is respectively adjacent to the second edge E2 and the fourth edge E4. The sidewalls201sare respectively located at the third corner C3 and the fourth corner C4 with an oblique angle, and are respectively connected to the first sidewall2011and the second sidewall2012.

In an embodiment of the present application, as shown inFIG.1, the plurality of first sidewalls2011and the plurality of second sidewalls2012may be adjusted in accordance with the shape of the light-emitting device1, such as a circle, a triangle, a hexagon, a rectangle, or a square. In an embodiment of the present application, the positions of the plurality of first sidewalls2011and the plurality of second sidewalls2012can be adjusted according to the user design, and is not limited by the above described. Based on the subsequent processes, for example, an area surrounded by the plurality of first sidewalls2011and the plurality of second sidewalls2012can accommodate the electrode pad subsequently formed.

In an embodiment of the present application, as shown inFIG.3, the first distance D is preferably larger than 5 μm and less than 50 μm, more preferably less than 30 μm. The top surface100of the substrate10exposed by the first distance D is a rough surface. The rough surface may be a surface having an irregular shape or a surface having a regular shape. The irregular shape includes a plurality of pattern units having different shapes or intervals, and the regular shape includes a plurality of pattern units having substantially the same shape or interval. The rough surface includes a plurality of hemispherical shapes protruding or recessed from the top surface100, a surface having a plurality of cones protruding or recessed from the top surface100, or a surface having a plurality of pyramids protruding or recessed from the top surface100.

As shown inFIG.3, a first angle θ1 is between the first sidewall2011of the first semiconductor layer201and the top surface100of the substrate10, and a second angle θ2 is between the second sidewall2012of the first semiconductor layer201and the top surface100of the substrate10, and the second angle θ2 is different from the first angle θ1.

In an embodiment of the present application, the first angle θ1 is larger than the second angle θ2.

In an embodiment of the present application, the first angle θ1 is between 70 and 90 degrees. The second angle θ2 is between 20 and 70 degrees.

In an embodiment of the present application, the angle difference between the first angle θ1 and the second angle θ2 is larger than 20 degrees.

FIG.16illustrates a top view of a light-emitting device5in accordance with an embodiment of the present application.FIG.17illustrates a cross-sectional view taken along line I-I′ ofFIG.16.FIG.18illustrates a cross-sectional view taken along line J-J′ ofFIG.16. The light-emitting device5and the light-emitting device1substantially include the same structure, the same designations and numbers of the light-emitting device5illustrated inFIGS.16˜18and the light-emitting device1illustrated inFIGS.1-6Dinclude the same material, or the same function, and the related descriptions will be properly omitted.

A light-emitting device5includes a substrate10including a top surface100, a first side surface101, a second side surface102, a third side surface103and a fourth side surface104. The first side surface101and the second side surface102of the substrate10are located at two opposite sides of the top surface100of the substrate10and not parallel to the top surface100, and the third side surface103and the fourth side surface104of the substrate10are located at another two opposite sides of the top surface100of the substrate10and not parallel to the top surface100. The first side surface101, the second side surface102, the third side surface103, and the fourth side surface104form a periphery of the substrate10.

As shown inFIG.16, in a top view of the light-emitting device5, the substrate10of the light-emitting device5includes a plurality of corners and a plurality of edges, wherein any one of the corners is constituted by two adjacent edges. The plurality of corners includes a first corner C1, a second corner C2, a third corner C3, and a fourth corner C4. The plurality of edges includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4.

An outer periphery205eof the semiconductor mesa205includes a first outer periphery2051eadjacent to the first edge E1; a second outer periphery2052e′ adjacent to the second edge E2; a third outer periphery2053eadjacent to the third edge E3; and a fourth outer periphery2054eadjacent to the fourth edge E4.

In order to increase the light emitting area and the light extraction efficiency of the light-emitting device5, the first outer periphery2051eadjacent to the first edge E1 includes a first plurality of concave parts2050and a first plurality of convex parts2051.

A first plurality of concave parts2050and a first plurality of convex parts2051are alternately arranged. The second outer periphery2052e′ adjacent to the second edge E2 includes a second plurality of concave parts20520and a second plurality of convex parts20521. The second plurality of concave parts20520and the second plurality of convex parts20521are alternately arranged. The first plurality of concave parts2050and the second plurality of concave parts20520include different curvature radii in the top view of the light-emitting device5. The first plurality of convex parts2051and the second plurality of convex parts20521include different curvature radii in the top view of the light-emitting device5. In the top view of the light-emitting device5, the first outer periphery2051eand the second outer periphery2052e′ include wavy shape, zigzag shape, or square shape.

In the top view of the light-emitting device5, an amount of the plurality of concave parts2050is larger than that of the second plurality of concave parts20520. An amount of the plurality of convex parts2051is larger than that of the second plurality of convex parts20521.

One portion of the third outer periphery2053eof the third edge E3 near the first edge E1 includes a plurality of concave parts2050and a plurality of convex parts2051, wherein the plurality of concave parts2050and the plurality of convex parts2051are continuously and alternately arranged. In an embodiment, the contour of the third outer periphery2053eformed by the plurality of concave parts2050and the plurality of convex parts2051is the same as or different from the contour of the first outer periphery2051eformed by the plurality of concave parts2050and the plurality of convex parts2051.

Another portion of the third outer periphery2053eof the third edge E3 near the second edge E2 includes the second plurality of concave parts20520and the second plurality of convex parts20521, wherein the second plurality of concave parts20520and the second plurality of convex parts20521are continuously and alternately arranged. In an embodiment, the contour of the third outer periphery2053eformed by the second plurality of concave parts20520and the second plurality of convex parts20521is the same as or different from the contour of the second outer periphery2052e′ formed by the second plurality of concave parts20520and the second plurality of convex parts20521. The plurality of concave parts2050, the plurality of convex parts2051, the second plurality of concave parts20520and the second plurality of convex part20521are continuously and alternately arranged to form the contour of the third outer periphery2053e. The first plurality of concave parts2050and the second plurality of concave parts20520include different curvature radii in the top view of the light-emitting device5. The first plurality of convex parts2051and the second plurality of convex parts20521include different curvature radii in the top view of the light-emitting device5. In the top view of the light-emitting device5, the contour of the third outer periphery2053emay be a wave shape, a zigzag shape or a square wave shape.

One portion of the fourth outer periphery2054eof the fourth edge E4 near the first edge E1 includes the plurality of concave parts2050and the plurality of convex parts2051, wherein the plurality of concave parts2050and the plurality of convex parts2051are continuously and alternately arranged. In an embodiment, the contour of the fourth outer periphery2054eformed by the plurality of concave parts2050and the plurality of convex parts2051is the same as or different from the contour of the first outer periphery2051eformed by the plurality of concave parts2050and the plurality of convex parts2051.

Another portion of the fourth outer periphery2054eof the fourth edge E4 near the second edge E2 includes the second plurality of concave parts20520and the second plurality of convex parts20521, wherein the second plurality of concave parts20520and the second plurality of convex parts20521are continuously and alternately arranged. In an embodiment, the contour of the fourth outer periphery2054eformed by the second plurality of concave parts20520and the second plurality of convex parts20521is the same as or different from the contour of the second outer periphery2052e′ formed by the second plurality of concave parts20520and the second plurality of convex parts20521. The plurality of concave parts2050, the plurality of convex parts2051, the second plurality of concave parts20520and the second plurality of convex parts20521are continuously and alternately arranged to form the contour of the fourth outer periphery2054e. The first plurality of concave parts2050and the second plurality of concave parts20520include different curvature radii in the top view of the light-emitting device5. The first plurality of convex parts2051and the second plurality of convex parts20521include different curvature radii in the top view of the light-emitting device5. In the top view of the light-emitting device5, the contour of the fourth outer periphery2054emay be a wave shape, a zigzag shape or a square wave shape.

As shown inFIG.16, a first space D1 between one side of the convex mesa2051of the first outer periphery2051eand the first edge E1 is smaller than a second space D2′ between one side of the convex mesa20521of the second outer periphery2052eand the second edge E2.

In the top view of the light-emitting device5, a third space D0 is between a side of the convex mesa2051of the first outer periphery2051eand a side of the concave part2050of the first outer periphery2051e. A fourth space D0′ is between the second plurality of concave parts20520and the second plurality of the convex parts20521of the second outer periphery2052e′. In an embodiment of the present application, the third space D0 and the fourth space D0′ include same distance. In another embodiment of the present application, the third space D0 and the fourth space D0′ include different distances.

In accordance with the positions of the plurality of concave parts2050, the plurality of convex parts2051, the second plurality of concave parts20520and the plurality of convex parts20521, the positions of the opening of the insulating layer, the contact layer, or the electrode layer subsequently formed can be determined. The light extraction efficiency of the light-emitting device5can be improved by the pattern design on the side surface of the semiconductor stack20.

The recess204is located at an outermost side of the semiconductor stack20, wherein the recess204continuously or discontinuously exposes the first semiconductor layer201of the outermost side of the semiconductor stack20to continuously or discontinuously surround the second semiconductor layer203and the active layer202of the semiconductor mesa205.

The via200is located inside the semiconductor stack20and is surrounded by the recess204. In other words, the via200is surrounded by the second semiconductor layer202and the active layer203. In the top view of the light-emitting device5, the via200includes an elliptical shape, a circular shape, a rectangular shape, or any other shape.

As shown inFIG.17, the first semiconductor layer201adjacent to the first edge E1 includes a first sidewall2011connected to the top surface100of the substrate10, and spaced apart from the first side surface101of the substrate10by a second distance D′ to expose a portion of the top surface100of the substrate10. The first semiconductor layer201adjacent to the second edge E2 includes a second sidewall2012inclined to the top surface100of the substrate10and spaced apart from the second side surface102of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10. The second distance D′ is smaller than the first distance D.

As shown inFIG.18, the first semiconductor layer201adjacent to the fourth edge E4 includes a first sidewall2011connected to the top surface100of the substrate10, and directly connected to the fourth side surface104of the substrate10. The first semiconductor layer201adjacent to the second edge E2 includes a second sidewall2012inclined to the top surface100of the substrate10and spaced apart from the second side surface102of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10.

The first distance D is preferably larger than 5 μm and less than 50 μm, more preferably less than 30 μm. The top surface100exposed by the first distance D is a rough surface. The rough surface may be a surface having an irregular shape or a surface having a regular shape. The irregular shape includes a plurality of pattern unit having different shapes or intervals, and the regular shape includes a plurality of pattern unit having substantially same shape or interval. The rough surface includes a plurality of hemispherical shapes protruding or recessed from the top surface100, a surface having a plurality of cones protruding or recessed from the top surface100, or a surface having a plurality of pyramids protruding or recessed from the top surface100.

The structure of the third edge E3 and the structure of the fourth edge E4 of the light-emitting device5is substantially the same as the third edge E3 and the structure of the fourth edge E4 of the light-emitting device1. The side surface structure of the first semiconductor layer201adjacent to the third edge E3 of the light-emitting device5includes the first sidewall2011and the second sidewall2012, wherein the first sidewall2011is directly connected to the third side surface103of the substrate10, and the second sidewall2012is inclined to the top surface100of the substrate10and spaced apart from the third side surface103of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10. And, the second sidewall2012is closer to the second edge E2 than the first sidewall2011to the second edge E2. The side surface structure of the first semiconductor layer201adjacent to the fourth edge E4 of light-emitting device5includes the first sidewall2011and the second sidewall2012, wherein the first sidewall2011is directly connected to the fourth side surface104of the substrate10, and the second sidewall2012is inclined to the top surface100of the substrate10and spaced apart from the fourth side surface104of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10. And, the second sidewall2012is closer to the second edge E2 than the first sidewall2011to the second edge E2.

As shown inFIG.1,FIG.2,FIG.3,FIG.17andFIG.18, a first insulating layer30is formed on the semiconductor stack20. An opening300of the first insulating layer30is formed in the via200by selectively etching the first insulating layer30to expose the first semiconductor layer201on the via200. One or a plurality of first openings301of the first insulating layer30are formed on the recess204adjacent to the first edge E1 to expose the first semiconductor layer201on the recess204. One or a plurality of second openings302of the first insulating layer30are formed on the recess204adjacent to the second edge E2 to expose the first semiconductor layer201on the recess204. A third opening303of the first insulating layer30is formed on the second semiconductor layer202. The first insulating layer30adjacent to the opening300of the first insulating layer30covers portions of the second semiconductor layer202beyond the via200and covers the first surface S1 of the via200. The first insulating layer30adjacent to the recess204covers portions of the second semiconductor layer202beyond the recess204and covers the second surface S2 of the recess204.

As shown inFIG.1andFIG.2, in order to provide same areas of the first semiconductor layer201exposed by the first opening301of the first insulating layer30and the second opening302of the first insulating layer30, the second opening302of the first insulating layer30adjacent to the second edge E2 includes a maximum length302wgreater than a maximum length301wof the first opening301of the first insulating layer30adjacent to the first edge E1.

In an embodiment, the first insulating layer30includes an insulating material having light transparency. For example, the material of the first insulating layer30includes SiOx.

In an embodiment of the present application, the first insulating layer30includes a thickness between 1000 angstrom (A) and 20,000 angstrom (A).

In an embodiment of the present application, the material of the first insulating layer30includes SiO2, TiO2, or SiNx. If the thickness of the first insulating layer30is less than 1000 angstrom (A), the thinner thickness may make the insulating ability of the first insulating layer30weak. As shown inFIG.2,FIG.3,FIG.4,FIG.17, andFIG.18, the first insulating layer30is formed on the first surface S1 and the second surface S2 after etching. The first insulating layer30formed by conformally covering the surface has a specific slope. If the first insulating layer30including a thickness less than 1000 angstrom (Å), it may cause cracking of the film.

In an embodiment of the present application, the material of the first insulating layer30includes SiO2, TiO2, or SiNx. If the thickness of the first insulating layer30is thicker than 20000 angstrom (A), it is getting difficult to perform selectively etching on the first insulating layer30. Nevertheless, the above embodiments do not exclude other materials having a good extensibility material or a high etch selectivity to avoid the problem caused by the thin thickness or the thick thickness of the first insulating layer30.

As shown inFIG.3,FIG.3A,FIG.4,FIG.5,FIG.17, andFIG.18, the first insulating layer30includes a side surface which is an inclined surface with respect to a horizontally extending surface of the inner surface200sor the outer surface204sof the first semiconductor layer201exposed through the selective etching. The inclined surface includes an angle ranged between 10 and 70 degrees with respect to the horizontally extending surface of the inner surface200sor the outer surface204sof the first semiconductor layer201exposed through the selective etching.

If the angle of the side surface of the first insulating layer30is less than 10 degrees, the thickness of the first insulating layer30will substantially be reduced. Therefore, it may be difficult to ensure the insulation properties thereof.

If the angle of the side surface of the first insulating layer30is greater than 70 degrees, the insulating layer and the metal layer subsequently formed may not completely cover the side surface, thereby causing the film cracking thereof.

In an embodiment of the present application, the side surface of the first insulating layer30has an angle between 20 and 75 degrees, preferably between 30 and 65 degrees, more preferably between 40 and 55 degrees.

As shown inFIG.3,FIG.3A,FIG.4,FIG.5,FIG.17, andFIG.18, a contact electrode40is formed on the second semiconductor layer202. Specifically, the contact electrode40is formed in the third opening303of the first insulating layer30. The contact electrode40includes a transparent electrode. The material of the transparent electrode includes a transparent conductive oxide or a transparent thin metal. The transparent conductive oxide includes indium tin oxide (ITO), zinc oxide (ZnO), zinc indium tin oxide (ZITO), zinc indium oxide (ZIO), zinc tin oxide (ZTO), gallium indium tin oxide (GITO), gallium indium oxide (GIO) or gallium zinc oxide (GZO). The transparent conductive oxide includes various dopants such as aluminum doped zinc oxide (AZO) or fluorine doped tin oxide (FTO). The transparent thin metal includes nickel (Ni) or gold (Au).

The thickness of the contact electrode40is not limited, but may have a thickness between 0.1 nm and 1000 nm. In an embodiment, the material of the contact electrode40includes a light-transmitting conductive oxide. If the thickness of the contact electrode40is less than 0.1 nm, the thickness of the contact electrode40is too thin and not able to form an ohmic contact with the second semiconductor layer202. If the thickness of the contact electrode40is larger than 1000 nm, the contact electrode40having the thick thickness may partially absorb the light emitted from the active layer203, and the luminance of the light-emitting device1is reduced. Since the contact electrode40has a thickness range described above, the current can be uniformly spread in the horizontal direction to improve the electrical performance of the light-emitting device1. However, the above embodiments do not exclude other materials being capable of providing lateral current spreading.

As shown inFIG.2,FIG.3,FIG.3A,FIG.17, andFIG.18, the contact electrode40is substantially formed on the entire surface of the second semiconductor layer202, and forms a low-resistance contact with the second semiconductor layer202, such as an ohmic contact. The electrical current is uniformly spread through the second semiconductor layer202by the contact electrode40. In an embodiment, in the cross-sectional view of the light-emitting device1, the contact electrode40includes an outermost side which is separated from the second surface S2 of the recess204by a horizontal distance less than 20 μm, preferably less than 10 μm and more preferably less than 5 μm.

As shown inFIG.2,FIG.3,FIG.3A,FIG.17, andFIG.18, a reflective layer50is formed on the contact electrode40. The material of the reflective layer50includes a metal such as aluminum (Al), silver (Ag), rhodium (Rh), platinum (Pt) or an alloy of the above materials. The reflective layer50reflects the light, and the reflected light is emitted outward and toward the substrate10, wherein the light is formed in the active layer203.

In another embodiment, the step of forming the contact electrode40may be omitted. The reflective layer50is formed in the third opening303of the first insulating layer30, and the reflective layer50forms an ohmic contact with the second semiconductor layer202.

In an embodiment, in the cross-sectional view of the light-emitting device, as shown inFIG.3,FIG.3A,FIG.4,FIG.5,FIG.17, andFIG.18, the reflective layer50includes an outermost side that is separated from the second surface S2 of the recess204by a horizontal distance less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm.

In an embodiment, the reflective layer50can be a structure including one or more sub-layers, such as a Distributed Bragg reflector.

In one embodiment, a side surface of the reflective layer50is an inclined surface with respect to the top surface of the second semiconductor layer202, and the inclined surface includes an angle between 10 and 60 degrees with respect to the top surface of the second semiconductor layer202. The material of the reflective layer50can be silver (Ag). If the angle of the reflective layer50is less than 10 degrees, a gentle slope can lower the reflection efficiency of the light. In addition, an angle less than 10 degrees is also difficult to achieve a uniform thickness. If the angle of the reflective layer50is greater than 60 degrees, it may cause cracking of the film subsequently formed. However, the above embodiments do not exclude other materials having high reflectance.

The adjustment of the angle of the reflective layer50can be achieved by changing the configuration of the substrate and the deposition direction of the metal atoms in the thermal deposition process. For example, the position of the substrate is adjusted such that the surface of the substrate is an inclined surface with respect to the deposition direction in the evaporation or the sputtering.

In an embodiment, a barrier layer (not shown) is formed on the reflective layer50to cover the top surface and the side surface of the reflective layer40to avoid the surface oxidation of the reflective layer50which deteriorated the reflectance of the reflective layer50. The material of the barrier layer includes a metal such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), chromium (Cr), platinum (Pt) or an alloy of the above materials. The barrier layer includes one or more layers, such as titanium (Ti)/aluminum (Al), and/or nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW). In an embodiment of the present application, the barrier layer includes a laminated structure including titanium (Ti)/aluminum (Al) and a laminated structure including nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW), wherein laminated structure including titanium (Ti)/aluminum (Al) is formed on one side away from the reflective layer50, and the laminated structure including nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW) is adjacent to one side adjacent to the reflective layer50. In an embodiment of the application, the material of the reflective layer50and the barrier layer preferably includes a metal material other than gold (Au) or copper (Cu).

The laminated structure of the barrier layer includes nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW)/platinum (Pt)/titanium (Ti)/aluminum (Al)/titanium (Ti)/aluminum (Al)/Chromium (Cr)/platinum (Pt), the barrier layer includes an angle between 10 and 60 degrees with respect to the surface of the second semiconductor layer203. In an embodiment, if the angle of the barrier layer is less than 10 degrees, the barrier layer cannot completely cover the reflective layer50and is also difficult to achieve a uniform thickness. If the angle of the barrier layer is greater than 60 degrees, it may cause cracking of the film subsequently formed.

In an embodiment, the thickness of the reflective layer50or the barrier layer is preferably between 100 nm and 1 μm. If the thickness of the reflective layer50or the barrier layer is less than 100 nm, the light emitted from the active layer202cannot be effectively reflected. If the thickness of the reflective layer50or the barrier layer is larger than 1 μm, the manufacturing loss is caused by excessive production time.

In order to cover the top surface and the side surface of the reflective layer50, the barrier layer includes a bottom surface contacting with the second semiconductor layer202and/or the contact electrode40.

As shown inFIG.2,FIG.3,FIG.3A,FIG.4,FIG.17, andFIG.18, a second insulating layer60is formed on the semiconductor stack20, and an opening600of the second insulating layer60is formed in the via200by a selectively etching to expose the first semiconductor layer201on the via200. A plurality of first openings601of the second insulating layer60is formed on the recess204adjacent to the first edge E1 to expose the first semiconductor layer201on the recess204. A plurality of second openings602of the second insulating layer60is formed on the recess204adjacent to the second edge E2 to expose the substrate10and the first semiconductor layer201on the recess204. A third opening603of the second insulating layer60is formed on the second semiconductor layer202to expose portions of the second semiconductor layer202, the reflective layer50, and/or the barrier layer. The remaining area is shielded by the second insulating layer60.

As shown inFIG.1andFIG.2, in order to provide same areas of the first semiconductor layer201exposed by the first opening601of the second insulating layer60and the second opening602of the second insulating layer60, the second opening602of the second insulating layer60adjacent to the second edge E2 includes a maximum length602wgreater than a maximum length601wof the first opening601of the second insulating layer60adjacent to the first edge E1.

In an embodiment, the second insulating layer60includes an insulating material having light transparency. For example, the second insulating layer60includes SiOx.

In an embodiment of the present application, the second insulating layer60includes a thickness between 1000 angstrom (A) and 60,000 angstrom (A).

In an embodiment of the present application, the material of the second insulating layer60includes SiO2, TiO2, or SiNx. If the thickness of the second insulating layer60is less than 1000 angstrom (A), the thinner thickness may make the insulating property of the second insulating layer60weak. Specifically, the second insulating layer60is conformally formed on the etched first surface S1 and the etched second surface S2, and the second insulating layer60includes an inclined surface, if the second insulating layer60includes a thickness less than 1000 angstrom (A), it may cause cracking of the film.

In an embodiment of the present application, the material of the second insulating layer60includes SiO2, TiO2, or SiNx. If the thickness of the second insulating layer60is thicker than 60000 angstrom (A), it is difficult to perform the selective etching on the second insulating layer60. Nevertheless, the above embodiments do not exclude other materials having a good extensibility material or a high etch selectivity to avoid the problem caused by the thin thickness or the thick thickness of the second insulating layer60.

As shown inFIG.3,FIG.3A,FIG.4,FIG.5,FIG.17, andFIG.18, the second insulating layer60includes a side surface which is an inclined surface with respect to a horizontally extending surface of the inner surface200sor the outer surface204sof the first semiconductor layer201exposed through the selectively etching. The inclined surface includes an angle between 10 and 70 degrees with respect to the horizontally extending surface of the inner surface200sor the outer surface204sof the first semiconductor layer201exposed through the selectively etching.

If the angle of the side surface of the first insulating layer60is less than 10 degrees, the thickness of the second insulating layer60will be substantially reduced. Therefore, it may be difficult to ensure the insulation properties thereof.

If the angle of the side surface of the second insulating layer60is greater than 70 degrees, the insulating layer and the metal layer subsequently formed may not completely cover the second insulating layer60, thereby causing the film cracking of the insulating layer and the metal layer.

In an embodiment of the present application, the side surface of the second insulating layer60has an angle between 20 and 75 degrees, preferably between 30 and 65 degrees, more preferably between 40 and 55 degrees.

The opening600of the second insulating layer60, the first opening601of the second insulating layer60, the second opening602of the second insulating layer60, and the third opening603of the second insulating layer60are formed at positions respectively corresponding to those of the opening300of the first insulating layer30, the first opening301of the first insulating layer30, the second opening302of the first insulating layer30, and the third opening303of the first insulating layer30.

As shown inFIG.2,FIG.3,FIG.3A,FIG.4,FIG.17, andFIG.18, the bottom electrode71is formed on the second insulating layer60, extends into the one or the plurality of openings600of the second insulating layer60, directly contacts the first semiconductor layer201in the via200, and is electrically connected to the first semiconductor layer201of the light-emitting device1. The bottom electrode71extends from the semiconductor mesa205along the first surface S1 to cover the first semiconductor layer201on the via200. As shown inFIGS.4,5, the bottom electrode71extends from the semiconductor mesa205, covers the first opening601of the second insulating layer60formed adjacent to the first edge E1 and the second opening602of the second insulating layer60formed adjacent to the second edge E2, and directly contacts the first semiconductor layer201located on the recess204so that the electrical current is uniformly diffused on the outer periphery of the light-emitting device1.

As shown inFIG.1,FIG.2,FIG.4andFIG.16, a plurality of concave parts2050and a plurality of convex parts2051are alternately arranged with each other. The concave part2050between two discontinuous convex parts2051exposes the first semiconductor layer201. The bottom electrode71covers the plurality of convex parts2051, extends along the second surface S2 to cover the outer surface204sof the first semiconductor layer201exposed on the recess204.

In order to uniformly spread the electrical current at the outer periphery of the light-emitting device1, as shown inFIG.1,FIG.2, andFIG.4, the plurality of first openings601of the second insulating layer60is provided at a regular interval. A fifth distance d1 between the adjacent two of the first openings601of the second insulating layer60may be greater than n times the width w1 of the first opening601of the second insulating layer60, d1=(1+n)w1, wherein n may be an integer or not an integer. For example, it is more than 0.5 times, preferably more than one times, more preferably more than twice.

As shown inFIG.5, the plurality of second openings602of the second insulating layer60discontinuously exposes the outer surface204sof the first semiconductor layer201. The bottom electrode71covers the first insulating layer30and the second insulating layer60, and is electrically connected to the first semiconductor layer201through the plurality of second openings602of the first insulating layer30and the plurality of second openings602of the second insulating layer60.

In order to uniformly spread the electrical current at the outer periphery of the light-emitting device1, as shown inFIG.4, the plurality of second openings602of the second insulating layer60is disposed at a regular interval. The sixth distance d2 between the adjacent two of the second openings602of the second insulating layer60may be greater than n times the width w2 of the second opening602of the second insulating layer60, d2=(1+n)w2, wherein n may be an integer or not an integer. For example, it is more than 0.5 times, preferably more than one times, more preferably more than twice.

As shown inFIG.1, in order to uniformly spread the electrical current at the outer periphery of the light-emitting device1, in an embodiment of the present application, the fifth distance d1 between the adjacent two first openings601of the second insulating layer60formed adjacent to the first edge E1 is substantially the same as the sixth distance d2 between the adjacent two second openings602of the second insulating layer60formed adjacent to the second edge E2.

As shown inFIG.1, in order to uniformly spread the electrical current at the outer periphery of the light-emitting device1, in an embodiment of the present application, the width w1 of the first opening601of the second insulating layer60adjacent to the first edge E1 is substantially the same as the width w2 of the second opening602of the second insulating layer60adjacent to the second edge E2.

As shown inFIG.3andFIG.3A, the top electrode72is formed in the third opening603of the second insulating layer60. The top electrode72contacts the second semiconductor layer202and electrically connected to the second semiconductor layer202and the reflective layer50. The second insulating layer60is located between the bottom electrode71and the top electrode72to prevent the bottom electrode71and the top electrode72from contacting each other to form a short circuit.

As shown inFIGS.1and2, in the top view of the light-emitting device1, the top electrode72includes an area smaller than that of the bottom electrode71, and the top electrode72is surrounded by the bottom electrode71.

The bottom electrode71and the top electrode72include a metal material including chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The bottom electrode71and the top electrode72include single layer or multilayers. For example, the bottom electrode71or the top electrode72includes Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack.

The bottom electrode71or the top electrode72includes a thickness preferably between 0.5 m and 3.5 μm.

In an embodiment, as shown inFIG.3,FIG.3A,FIG.17, andFIG.18, the top electrode72includes a top surface72sthat is lower than a top surface71sof the bottom electrode71. In other words, a step height is formed between the top surface72sof the top electrode72and the top surface71sof the bottom electrode71, wherein the step height is between 2000 angstrom (Å) and 60,000 angstrom (Å).

In an embodiment, a step height between the top surface72sof the top electrode72and the top surface71sof bottom electrode71is substantially same as the thickness of the second insulating layer60.

In an embodiment, a step height between the top surface72sof the top electrode72and the top surface71sof bottom electrode71has a deviation of ±30% from the thickness of the second insulating layer60.

In an embodiment, as shown inFIG.3,FIG.3A,FIG.17, andFIG.18, a step height between the top surface71sof the bottom electrode71and the top surface72sof the top electrode72is smaller than 2000 angstrom (Å), preferably smaller than 1000 angstrom (Å), and more preferably smaller than 500 angstrom (Å).

In an embodiment (not shown), a metal pad is formed below the bottom electrode, and the thickness of the metal pad has a deviation of ±30% from the thickness of the second insulating layer60, so that the top surface71sof the bottom electrode71and the top surface72sof the top electrode72are substantially flush.

As shown inFIG.2,FIG.3,FIG.3A,FIG.17, andFIG.18, a third insulating layer80is formed on the semiconductor stack20. A first opening801of the third insulating layer80is formed on the bottom electrode71by the selective etching to expose a portion of the top surface71sof the bottom electrode71. A second opening802of the third insulating layer80is formed on the top electrode72to expose the top surface72sof the top electrode72.

The third insulating layer80includes an insulating material having light transparency. For example, the third insulating layer80includes SiOx.

The first insulating layer30, the second insulating layer60, or the third insulating layer80includes two or more materials having different refractive indices alternately stacked to form a Distributed Bragg Reflector (DBR). In an embodiment, the first insulating layer30, the second insulating layer60, or the third insulating layer80is laminated with sub-layers of SiO2/TiO2or SiO2/Nb2O5to selectively reflect the light of a specific wavelength, thereby increasing the light extraction efficiency of the light-emitting device1. When the peak emission wavelength of the light-emitting device1is λ, the optical thickness of the first insulating layer30, the second insulating layer60, or the third insulating layer80can be an integral multiple of λ/4. The peak emission wavelength refers to the wavelength having a strongest intensity in the emission spectrum of the light-emitting device1. The thickness of the first insulating layer30, the second insulating layer60, or the third insulating layer80may have a deviation of ±30% on the basis of an integral multiple of the optical thickness λ/4.

The first insulating layer30, the second insulating layer60, or the third insulating layer80includes a non-conductive material including organic material, inorganic material or dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx).

In an embodiment, the material of the third insulating layer80includes SiO2, TiO2, or SiNx. The thickness of the third insulating layer80is between 10000 angstrom (Å) and 60000 angstrom (Å). If the thickness of the third insulating layer80is less than 10000 angstrom (Å), the thinner thickness may weaken the insulating ability and moisture resistance of the third insulating layer80. In another embodiment, the material of the third insulating layer80includes SiO2, TiO2, or SiNx. When the thickness of the third insulating layer80is thicker than 60000 angstrom (Å), it is difficult to perform the selective etching on the third insulating layer80. Nevertheless, the above embodiments do not exclude other materials having a good extensibility material or having a high etch selectivity to avoid the problem caused by the excessively thin or excessively thick film of the third insulating layer80.

As shown inFIG.1,FIG.3,FIG.3A,FIG.17, andFIG.18, the light-emitting device1includes a first electrode pad91covering the first opening801of the third insulating layer80and contacting the bottom electrode71. The first electrode pad91is electrically connected to the first semiconductor layer201through the bottom electrode71. The light-emitting device1includes a second electrode pad92covering the second opening802of the third insulating layer80and contacting the top electrode72to form an electrical connection with the reflective layer50, the contact electrode40, and the second semiconductor layer202.

In an embodiment, as shown inFIG.3, the first sidewall2011of the first semiconductor layer201near the fourth edge E4 is not covered by the third insulating layer80and is exposed. The second side wall2012of the first semiconductor layer201near the second edge E2 is covered by the third insulating layer80.

In an embodiment, as shown inFIG.3A, the first sidewall2011of the first semiconductor layer201near the first edge E1 is covered by the third insulating layer80, and the second side wall2012of the first semiconductor layer201near the second edge E2 is covered by the third insulating layer80.

In an embodiment, as shown inFIG.3A, the third insulating layer80includes a first side surface of a third insulating layer and a second side surface of a third insulating layer. The first side surface of the third insulating layer is directly connected to the first side surface101of the substrate10.

In an embodiment (not shown), the first side surface of the third insulating layer80is directly connected to the first side surface101of the substrate10. In the cross-sectional view of the light-emitting device, the second side surface of the third insulating layer is located between the second side surface102of the substrate10and the second sidewall2012of the first semiconductor layer201, and spaced apart from the second side surface102of the substrate10to expose the substrate10.

In the top view of the light-emitting device1, as shown inFIG.1, the first electrode pad91includes a top surface area smaller than a top surface area of the bottom electrode71. The second electrode pad92includes a top surface area that is smaller than a top surface area of the top electrode72.

The first electrode pad91and the second electrode pad92include a metal material including chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first electrode pad91and the second electrode pad92include single layer or multilayers. For example, the first electrode pad91or the second electrode pad92includes Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack, or Cr/Al/Cr/Ni/Au stack.

In an embodiment of the present application, the first electrode pad91includes a size that is the same as or different from a size of the second electrode pad92. The size includes a width or an area. For example, a top area of the first electrode pad91or the second electrode pad92may be 0.8 times or more of the top areas of the first electrode pad91and the second electrode pad92, and be less than one time a sum of the top areas of the first electrode pad91and the second electrode pad92.

The first electrode pad91or the second electrode pad92respectively includes an inclined side surface, and the cross-sectional area of the first electrode pad91or the second electrode pad92varies along the thickness direction. For example, the cross-sectional area of the first electrode pad91or the second electrode pad92gradually diminishes away from the upper surface of the semiconductor stack20.

The first electrode pad91or the second electrode pad92includes a thickness between 1 and 100 μm, preferably between 1.5 and 6 μm.

A space is between the first electrode pad91and the second electrode pad92, and the space is ranged from 10 μm to 250 μm. In the distance range described above, the top areas of the first electrode pad91and the second electrode pad92can be increased by reducing the distance of the space between the first electrode pad91and the second electrode pad92. The heat dissipation efficiency of the light-emitting device1can be improved, and a short circuit between the first electrode pad91and the second electrode pad92can also be avoided.

FIG.6Ais a partially enlarged top view of a portion X1 ofFIG.1.FIG.6Billustrates a cross-sectional view taken along line X1′-X1″ ofFIG.6A.FIG.6Cis a partially enlarged top view of a portion X2 ofFIG.1.FIG.6Dillustrates a cross-sectional view taken along line X2′-X2″ ofFIG.6C.

In an embodiment of the present application, as shown inFIG.1, in the top view of the light-emitting device1, the light-emitting device1includes a plurality of corners, wherein the plurality of corners includes a first corner C1, a second corner. C2, a third corner C3, and a fourth corner C4. The light-emitting device1includes a plurality of semiconductor structures206, wherein the plurality of semiconductor structures206includes a first semiconductor structure2061, a second semiconductor structure2062, a third semiconductor structure2063, and a fourth semiconductor structure2064. The first semiconductor structure2061, the second semiconductor structure2062, the third semiconductor structure2063, and the fourth semiconductor structure2064are respectively located at the first corner C1, the second corner C2, the third corner C3, and the fourth corner C4.

In another embodiment of the present application (not shown), the light-emitting device1includes a plurality of edges, wherein the plurality of edges include a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. The plurality of semiconductor structures206can be respectively located on the plurality of edges.

As shown inFIG.1andFIGS.6A-6D, the plurality of semiconductor structures206is respectively separated from the semiconductor mesa205, and the plurality of semiconductor structures206is separated from each other.

As shown inFIG.1andFIGS.6A-6B, the first semiconductor structure2061adjacent to the first edge E1 is separated from the semiconductor mesa205by a first shortest distance L1. The fourth semiconductor structure2064adjacent to the first edge E1 is separated from the semiconductor mesa205by a fourth shortest distance L4 (not shown). As shown inFIG.1,FIG.6C, andFIG.6D, the second semiconductor structure2062adjacent to the second edge E2 is separated from the semiconductor mesa205by a second shortest distance L2. The third semiconductor structure2063adjacent to the second edge E2 is separated from the semiconductor mesa205by a third shortest distance L3 (not shown) In an embodiment of the present application, the second shortest distance L2 and the third shortest distance L3 are respectively larger than the first shortest distance L1.

In an embodiment of the present application, the second shortest distance L2 and the third shortest distance L3 are substantially the same.

In an embodiment of the present application, the second shortest distance L2 and the third shortest distance L3 have a deviation of ±30%.

In an embodiment of the present application, the first shortest distance L1 and the fourth shortest distance L4 are different to be an identification point of the light-emitting device1. The fourth shortest distance L4 is larger than the first shortest distance L1, the second shortest distance L2, and/or the third shortest distance L3, respectively.

As shown inFIG.6B, the first semiconductor layer201adjacent to the first corner C1 is located between the first semiconductor structure2061and the semiconductor mesa205, and the first semiconductor layer201connects the first semiconductor structure2061and the semiconductor mesa205. The first semiconductor layer201adjacent to the fourth corner C4 is located between the fourth semiconductor structure2064and the semiconductor mesa205, and the first semiconductor layer201connects the first semiconductor structure2061and the semiconductor mesa205(not shown). As shown inFIG.6D, the first semiconductor layer201adjacent to the second corner C2 and formed between the second semiconductor structure2062and the semiconductor mesa205is removed, the substrate10is exposed, and the second semiconductor structure2062and the semiconductor mesa205are separated from each other. The first semiconductor layer201adjacent to the third corner C3 and formed between the third semiconductor structure2063and the semiconductor mesa205is removed, the substrate10is exposed, and the third semiconductor structure2063and the semiconductor mesa205are separated from each other (not shown).

In an embodiment of the present application, in the top view of the light-emitting device1, the first semiconductor structure2061, the second semiconductor structure2062, the third semiconductor structure2063, and the fourth semiconductor structure2064include a shape such as rectangular, triangular or fan shape.

FIG.7illustrates a top view of a light-emitting device2in accordance with an embodiment of the present application.FIG.8illustrates a top view pattern of each layer of the light-emitting device2in accordance with an embodiment of the present application.FIG.9illustrates a cross-sectional view taken along line D-D′ ofFIG.7.FIG.9Aillustrates a cross-sectional view taken along line H-H′ ofFIG.7.FIG.10illustrates a cross-sectional view taken along line E-E′ ofFIG.7.FIG.11illustrates a cross-sectional view taken along line F-F′ ofFIG.7.FIG.12illustrates a cross-sectional view taken along line G-G′ ofFIG.7. The light-emitting device2illustrated inFIGS.7˜12and the light-emitting device1illustrated inFIGS.1-6Dsubstantially includes the same structure with the same designations and numbers, the same material, or the same function, and the related descriptions will be properly omitted in the following paragraphs.

As shown inFIG.7,FIG.8,FIG.9,FIG.9A, andFIG.10, the light-emitting device2includes a substrate10; and a first light-emitting element2aand a second light-emitting element2bformed on the substrate10, wherein the first light-emitting element2aand the second light-emitting element2bare separated by a trench11, and the trench11exposes the top surface100of the substrate10.

As shown inFIG.7,FIG.8,FIG.9,FIG.9A, andFIG.10, the substrate10includes a first side surface101and a second side surface102, wherein the first side surface101and the second side surface102are respectively connected to two opposite sides of the top surface100of the substrate10and not parallel to the top surface100. As shown inFIG.7, substrate10further includes a third side surface103and a fourth side surface104, wherein the third side surface103and the fourth side surface104are respectively connected to another two opposite sides of the top surface100of the substrate10and not parallel to the top surface100. The first side surface101, the second side surface102, the third side surface103and the fourth side surface104form a periphery of the substrate10.

As shown inFIG.7, the third side surface103of the substrate10includes a first section1031of the third side surface and a second section1032of the third side surface. The fourth side surface104of the substrate10includes a first section1041of the fourth side surface and a second section1042of the fourth side surface. The first section1031of the third side surface and the first section1041of the fourth side surface are located on two opposite sides of the first light-emitting element2a. The second section1032of the third side surface and the second section1042of the fourth side surface are located on two opposite sides of the first light-emitting element2b.

The first light-emitting element2aand the second light-emitting element2bare formed on the top surface100of the substrate10, wherein the first light-emitting element2aand the second light-emitting element2beach includes a first semiconductor layer201, a second semiconductor layer202, and an active layer203formed between the first semiconductor layer201and the second semiconductor layer202.

As shown inFIG.8,FIG.9,FIG.9A, andFIG.10, the semiconductor stack20of the first light-emitting element2ais selectively etched to form a first recess204aand a first semiconductor mesa205a. The semiconductor stack20of the second light-emitting element2bis selectively etched to form a second recess204band a second semiconductor mesa205b. For example, a photoresist pattern of the recess and the semiconductor mesa is formed by coating a photoresist and then removing a portion of the photoresist through a lithography process. The photoresist pattern is used to form the recess and the semiconductor mesa. Specifically, the semiconductor mesa is formed by removing portions of the second semiconductor layer202and the active layer203to form a structure including the first semiconductor layer201, the second semiconductor layer202, and the active layer203. The first recess204aand the second recess204bare formed by removing portions of the second semiconductor layer202and the active layer203to expose the outer surface204asand the outer surface204bsof the first semiconductor layer201. The remaining photoresist pattern is removed after the etching process.

As shown inFIG.9andFIG.9A, the first recess204aand the second recess204brespectively includes a second surface S2 having an angle within a range with respect to the outer surfaces200as,204bsof the first semiconductor layer201, for example, an angle between 10 and 80 degrees. If the angle is less than 10 degrees, an excessively low slope may reduce the area of the active layer202, and a decreased area of the active layer202decreases the luminance of the light-emitting device2. If the angle is greater than 80 degrees, the insulating layer and the metal layer subsequently formed may not completely cover the sidewalls of the first semiconductor layer201, the second semiconductor layer202, and/or the active layer203, thereby causing cracking of the films formed thereon.

As shown inFIG.7, in the top view of the light-emitting device2, the light-emitting device2includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. The first semiconductor mesa205aadjacent to the first edge E1 includes a first outer periphery2051eand the second semiconductor mesa205badjacent to the second edge E2 includes a second outer periphery2052e. In order to increase the light-emitting area of the light-emitting device2, the first outer edge2051eof the first semiconductor mesa205aadjacent to the first edge E1 includes a plurality of concave parts2050and a plurality of convex parts2051alternately arranged as compared with the second outer periphery2052eof the second semiconductor mesa205badjacent to the second edge E2. A first space D1 between one side of the convex part2051and the first edge E1 is smaller than a second space D2 between the second outer periphery2052eand the second edge E2. A contour formed by the plurality of concave parts2050and the plurality of convex parts2051constitute a first outer periphery2051e. In the top view of the light-emitting device2, the first outer periphery2051eincludes a shape including wavy, zigzag or square. The position of the opening of the insulating layer, the contact layer, or the electrode layer subsequently formed can be determined according to the arrangement positions of the plurality of concave parts2050and the plurality of convex parts2051.

In an embodiment, the first outer periphery2051eof the first semiconductor mesa205aadjacent to the first section1031of the third side surface and the outer periphery2051eof the first semiconductor mesa205aadjacent to the first section1041of the fourth side surface respectively include a plurality of concave parts2050and a plurality of convex parts2051, wherein the plurality of concave parts2050and the plurality of convex parts2051are alternately arranged with each other. In an embodiment, the contour of the plurality of concave parts2050of the outer periphery2051eof the first semiconductor mesa205aadjacent to each side surface is the same or different from the contour of the plurality of convex parts2051.

In another embodiment of the present application, the second outer periphery2052eof the second semiconductor mesa205bincludes a shape including wavy, zigzag or square.

As shown inFIG.7, the first corner2051cof the first semiconductor mesa205aand the second corner2052cof the second semiconductor mesa205bcan be rounded to avoid the electrical current crowding locally at the corner of the light-emitting device2.

As shown inFIG.8, the first recess204ais located at an outermost side of the semiconductor stack20of the first light-emitting element2a, and the second recess204bis located at an outermost side of the semiconductor stack20of the second light-emitting element2b. The first recess204aand the second recess204bcontinuously or discontinuously expose the first semiconductor layer201of the outermost side of the semiconductor stack20, the second semiconductor layer203and the active layer202of the first semiconductor mesa205ais continuously or discontinuously surrounded by the first recess204a, and the second semiconductor layer203and the active layer202of the second semiconductor mesa205bis continuously or discontinuously surrounded by the second recess204b, wherein a portion of the top surface100of the substrate10of the light-emitting element2bis exposed to surround the first semiconductor layer201of the outermost side of the light-emitting element2b.

In an embodiment, the first light-emitting element2aincludes one first recess204ato continuously surround the first semiconductor mesa205a, and the second light-emitting element2bincludes one second recess204bto continuously surround the second semiconductor mesa205b. The first recess204aand the second recess204binclude a shape including a rectangular shape and are respectively located at the outermost side of the first light-emitting element2aand the second light-emitting element2b, wherein the corners of the rectangular shape can be rounded to prevent the electrical current locally crowding on the corners of each light-emitting element.

As shown inFIG.7andFIG.9, the first semiconductor layer201of the first light-emitting element2aadjacent to the first section1031of the third side surface103of the substrate10includes a first sidewall2011connected to the top surface100of the substrate10or directly connected to the third side surface103of the substrate10. The first semiconductor layer201of the second light-emitting element2badjacent to the second section1032of the third side surface103of the substrate10includes a second sidewall2012inclined to the top surface100of the substrate10and spaced apart from the third side surface103of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10.

FIG.9Aillustrates a cross-sectional view taken along line H-H′ ofFIG.7. As shown inFIG.9A, the first semiconductor layer201of the first light-emitting element2aadjacent to the first edge E1 includes a first sidewall2011connected to the top surface100of the substrate10, and spaced apart from the first side surface101of the substrate10by a second distance D′ to expose a portion of the top surface100of the substrate10. The first semiconductor layer201of the second light-emitting element2badjacent to the second section1042of the fourth side E4 includes a second sidewall20inclined to the top surface100of the substrate10, and spaced apart from the fourth side surface104of the substrate10by a first distance D to expose a portion of the top surface100of the substrate10. The second distance D′ is less than the first distance D.

In an embodiment of the present application, the first semiconductor layer201of the first light-emitting element2aincludes a plurality of first sidewalls2011and a third sidewall2013to form a first periphery of the first light-emitting element2a, wherein the distances between the plurality of first sidewalls2011and the side surface of the substrate10are different. Specifically, the first side wall2011adjacent to the first edge E1 is connected to the top surface100of the substrate10, and spaced apart from the first side surface101of the substrate10by a second distance D′ to expose a portion of the top surface100of the substrate10. The first sidewalls2011respectively adjacent to the third edge E3 and the fourth edge E4 are directly connected to the third side surface103and the fourth side surface104of the substrate10, respectively. The third sidewall2013of the first semiconductor layer201of the first light-emitting element2aforms one side of the trench11and the third sidewall2013is inclined to the top surface100of the substrate10.

In another embodiment of the present application (not shown), the first semiconductor layer201of the first light-emitting element2aincludes a plurality of first sidewalls2011and a third sidewall2012to form a first periphery of the first light-emitting element2a. The plurality of first sidewalls2011is respectively connected to the first side surface101, the first section1031of the third side surface, and the first section1041of the fourth side surface. The third sidewall2013of the first semiconductor layer201of the first light-emitting element2aform a side of the trench11, and the third sidewall2013is inclined to the top surface100of the substrate10.

In an embodiment of the present application, as shown inFIG.7,FIG.8,FIG.9,FIG.9A, andFIG.10, the first semiconductor layer201of the second light-emitting element2bincludes a plurality of second sidewalls2011and a fourth sidewall2014to form a second periphery of the second light-emitting element2b. The plurality of second sidewalls2012is respectively inclined to the top surface100of the substrate10and respectively separated from the second side surface102, a second section1032of the third side surface, and a second section1042of the fourth side surface by a first distance D to expose a portion of the top surface100of the substrate10. The fourth sidewall2014of the first semiconductor layer201of the first light-emitting element2aform another side of the trench11, and the fourth sidewall2014is inclined to the top surface100of the substrate10.

In an embodiment of the present application, the first distances D between the plurality of second sidewalls2012and the second side surface102, the second section1032of the third side surface, and the second section1042of the fourth side surface of the substrate10can be the same or different.

In an embodiment of the present application, as shown inFIG.9,FIG.9AandFIG.10, the first distance D is preferably larger than 5 μm and less than 50 μm, more preferably less than 30 μm. The exposed top surface100is a rough surface. The rough surface may be a surface having an irregular shape or a surface having a regular shape. The irregular shape includes a plurality of pattern unit having different shapes or intervals, and the regular shape includes a plurality of pattern unit having substantially same shape or interval. The rough surface includes a plurality of hemispherical shapes protruding or recessed from the top surface100, a surface having a plurality of cones protruding or recessed from the top surface100, or a surface having a plurality of pyramids protruding or recessed from the top surface100.

As shown inFIG.9andFIG.9A, a first angle θ1 is between the first sidewall2011of the first semiconductor layer201of the first light-emitting element2aand the top surface100of the substrate10, and a second angle θ2 is between the second sidewall2012of the first semiconductor layer201of the second light-emitting element2band the top surface100of the substrate10, and the second angle θ2 is different from the first angle θ1.

In an embodiment of the present application, the first angle θ1 is larger than the second angle θ2.

In an embodiment of the present application, the first angle θ1 is between 70 and 90 degrees. The second angle θ2 is between 20 and 70 degrees.

In an embodiment of the present application, the angle difference between the first angle θ1 and the second angle θ2 is larger than 20 degrees.

In an embodiment of the present application, the third sidewall2013of the first light-emitting element2ais inclined to the top surface100of the substrate10by a third angle θ3, and the fourth sidewall2014of the second light-emitting element2bis inclined to the top surface100of the substrate10by a fourth angle θ4.

In an embodiment of the present application, the third angle θ3 is different from the fourth angle θ4. The third angle θ3 and the fourth angle θ4 are respectively between 20 and 70 degrees.

In an embodiment of the present application, the difference between the third angle θ3 and the fourth angle θ4 is smaller than 20 degrees.

In an embodiment of the present application, the third angle θ3 is larger than the fourth angle θ4. The third angle θ3 and the fourth angle θ4 are respectively between 20 and 70 degrees.

In an embodiment of the present application, the third angle θ3 is smaller than the fourth angle θ4. The third angle θ3 and the fourth angle θ4 are respectively between 20 and 70 degrees.

In an embodiment of the present application, the second angle θ2 is different from the third angle θ3. The second angle θ2 and the third angle θ3 are respectively between 20 and 70 degrees.

In an embodiment of the present application, the second angle θ2 is larger than the third angle θ3. The second angle θ2 and the third angle θ3 are respectively between 20 and 70 degrees.

In an embodiment of the present application, the second angle θ2 is smaller than the third angle θ3. The second angle θ2 and the third angle θ3 are respectively between 20 and 70 degrees.

As shown inFIG.7andFIG.8, a first insulating layer30is formed on the semiconductor stack20of the first light-emitting element2aand the second light-emitting element2b. One or a plurality of first openings301of the first insulating layer30are formed on the first recess204aadjacent to the first edge E1 to expose the first semiconductor layer201of the first recess204aof the first light-emitting element2a. One or a plurality of second openings302of the first insulating layer30are formed on the second recess204badjacent to the second edge E2 to expose the first semiconductor layer201of the second recess204bof the second light-emitting element2b. The third openings303a,303bof the first insulating layer30are respectively formed on the first light-emitting element2aand the second light-emitting element2bto expose the second semiconductor layer202.

In an embodiment of the present application, as shown inFIG.7andFIG.8, the position of the openings of the first insulating layer30is provided to determine the positions of the contact layer and the electrode subsequently formed. In order to uniformly spread the electrical current at the outer edge of the light-emitting device2, the plurality of second openings302of the first insulating layer30adjacent to the second edge E2 include an amount equal to the amount of the plurality of first openings301of the first insulating layer30adjacent to the first edge E1.

As shown inFIG.7andFIG.8, in order to provide same areas of the first semiconductor layer201exposed by the first opening301of the first insulating layer30and the second opening302of the first insulating layer30, the second opening302of the first insulating layer30adjacent to the second edge E2 includes a maximum length302wgreater than a maximum length301wof the first opening301of the first insulating layer30adjacent to the first edge E1.

As shown inFIG.8,FIG.9, andFIG.9A, a first contact electrode40ais formed in the third opening303aof the first insulating layer30of the first light-emitting element2ato ohmic contact the second semiconductor layer202of the first light-emitting element2a. A second contact electrode40bis formed in the third opening303bof the first insulating layer30of the second light-emitting element2bto ohmic contact the second semiconductor layer202of the second light-emitting element2b. The first contact electrode40aand the second contact electrode40binclude transparent electrode. The material of the transparent electrode includes a transparent conductive oxide or a transparent thin metal.

The thickness of the first contact electrode40aand the second contact electrode40bis not limited, but may respectively include a thickness between 0.1 nm and 200 nm. In an embodiment, the material of the first contact electrode40aand the second contact electrode40bincludes a transparent conductive oxide. If the thickness of the first contact electrode40aor the second contact electrode40bis less than 0.1 nm, the thickness of the first contact electrode40aor the second contact electrode40bis too thin and not able to form an ohmic contact with the second semiconductor layer202. If the thickness of the first contact electrode40aor the second contact electrode40bis larger than 200 nm, the first contact electrode40aand the second contact electrode40bhaving the thick thickness may partially absorb the light emitted from the active layer203, and the luminance of the light-emitting device2is reduced. Since the first contact electrode40aand the second contact electrode40bhave a thickness range described above, the current can be uniformly spread in the horizontal direction to improve the electrical performance of the light-emitting device2. However, the above embodiments do not exclude other materials being capable of lateral current spreading

The first contact electrode40aand the second contact electrode40bare formed on the surface of the second semiconductor layer202, and form a low-resistance contact with the second semiconductor layer202, such as an ohmic contact. The electrical current is uniformly spread through the second semiconductor layer202by the first contact electrode40aand the second contact electrode40b. In an embodiment, in the cross-sectional view of the light-emitting device2, the first contact electrode40aand the second contact electrode40brespectively includes an outermost side which is separated from the first recess204aand the second recess204bby a horizontal distance less than 20 μm, preferably less than 10 μm, and more preferably less than 5 μm.

As shown inFIG.8,FIG.9, andFIG.9A, a first reflective layer50ais formed on the first contact electrode40aand a second reflective layer50bis formed on the second contact electrode40b. The material of the first reflective layer50aand the second reflective layer50bincludes metal material such as aluminum (Al), silver (Ag), rhodium (Rh), platinum (Pt) or an alloy of the above materials. The first reflective layer50aand the second reflective layer50breflect a light and the reflected light emits outward toward the substrate10, wherein the light is formed in the active layer203.

In another embodiment, the step of forming the first contact electrode40aand the second contact electrode40bmay be omitted. The first reflective layer50aand the second reflective layer50bare respectively formed in the third openings303aand303bof the first insulating layer30. The first reflective layer50aand the second reflective layer50bohmic contact with the second semiconductor layer202.

In an embodiment, in the cross-sectional view of the light-emitting device5, as shown inFIG.9andFIG.10, the first reflective layer50aand the second reflective layer50brespectively includes an outermost side that is separated from the first recess204aand the second recess204bby a horizontal distance less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm.

In another embodiment, a barrier layer (not shown) is formed on the first reflective layer50aand the second reflective layer50bto respectively cover the top surface and the side surface of the first reflective layer50aand the second reflective layer50bto avoid surface oxidation of the first reflective layer50aand the second reflective layer50bwhich deteriorated the reflectance of the first reflective layer50aand the second reflective layer50b. The material of the barrier layer includes a metal.

As shown inFIG.9,FIG.9A, andFIG.10, the light-emitting device2includes a second insulating layer60formed on the semiconductor stack20of the first light-emitting element2aand the second light-emitting element2b. One or a plurality of first openings600of second insulating layer60is formed on the first recess204aby selectively etching method to expose the first semiconductor layer201of the first recess204aof the first light-emitting element2a. One or a plurality of second openings602of the second insulating layer60is formed on the second recess204bto expose the first semiconductor layer201on the second recess204bof the second light-emitting element2b. One or a plurality of third openings603aof the second insulating layer60is formed on the first light-emitting element2ato expose the second semiconductor layer202, the reflective layer50a, and/or the barrier layer of the first light-emitting element2a. A fourth openings603bof the second insulating layer60is formed on the second light-emitting element2bto expose the second semiconductor layer202, the reflective layer50b, and/or the barrier layer of the second light-emitting element2b.

The forming positions of the first opening601of the second insulating layer60, the second opening602of the second insulating layer60and the fourth opening603bof the second insulating layer60are respectively corresponding to that of the first opening301of the first insulating layer30, the second opening302of the first insulating layer30and the third opening303bof the first insulating layer30. A forming position of the third opening603aof the second insulating layer60overlaps with that of the third opening303bof the first insulating layer30.

As shown inFIG.7andFIG.8, the area of the first semiconductor layer201exposed by the first opening601of the second insulating layer60and the area of the first semiconductor layer201exposed by the second opening602of the second insulating layer60are substantially the same, the plurality of second openings602of the second insulating layer60on the second light-emitting element2brespectively includes a maximum length602w, which is greater than a maximum length601wof one of plurality of first openings601of the second insulating layer60on the first light-emitting element2a.

The position of the opening of the second insulating layer60may be used to determine the position of the electrode subsequently formed. As shown inFIG.7,FIG.8andFIG.10, in order to uniformly spread the electrical current at the outer edge of the light-emitting device2, the second insulating layer60further includes one or more openings600of the second insulating layer60formed between the first light-emitting element2aand the second light-emitting element2b. The openings600of the second insulating layer60includes one or a plurality of first cell openings600aof the second insulating layer60exposing the first semiconductor layer201located on the first recess204aof the first light-emitting element2a; and one or a plurality of second cell openings600bof the second insulating layer60exposing the first semiconductor layer201located on the second recess204bof the second light-emitting element2b.

In another embodiment, the plurality of first cell openings600aof the second insulating layer60and the plurality of third openings603aof the second insulating layer60are located on the same side of the first light-emitting element2a, and the plural of first cell openings600aof the second insulating layer and the plurality of third openings603aof the second insulating layer60are alternately arranged with each other. In order to increase the injection current and reduce the loss of the light-emitting area, the number of the third openings603aof the second insulating layer60is more than that of the plurality of first cell openings600aof the second insulating layer60. The amount of the first cell openings600aof the second insulating layer60is the same as the amount of the second cell openings600bof the second insulating layer60. The first cell opening600aof the second insulating layer60and the second cell opening600bof the second insulating layer60are connected in the top view of the light-emitting device2.

The second insulating layer60includes an insulating material having light transparency. For example, the second insulating layer60includes SiOx.

In an embodiment of the present application, the second insulating layer60includes a thickness ranged between 1000 Å and 60,000 Å.

As shown inFIG.9,FIG.9A, andFIG.10, the second insulating layer60includes a side surface having an angle between 10 and 70 degrees with respect to a horizontally extending surface of the outer surface204asof the first semiconductor layer201exposed through the selective etching

If the angle of the side surface of the first insulating layer60is less than 10 degrees, the thickness of the second insulating layer60will be substantially reduced. Therefore, it will be difficult to ensure the insulation properties.

If the angle of the side surface of the second insulating layer60is greater than 70 degrees, the insulating layer and the metal layer subsequently formed may not completely cover the second insulating layer60, thereby causing the film cracking.

In an embodiment of the present application, the side surface of the second insulating layer60has an angle between 20 and 75 degrees, preferably between 30 and 65 degrees, more preferably between 40 and 55 degrees.

As shown inFIG.7,FIG.9andFIG.9A, the light-emitting device2includes one or a plurality of connecting electrodes70formed between the first light-emitting element2aand the second light-emitting element2b. The one or the plurality of connecting electrodes70respectively includes a first connecting section701formed on the first recess204aof the first light-emitting element2a, extending to cover and electrically connected the second semiconductor layer202of the first light-emitting element2a; a second connecting section702formed on the second recess204bof the second light-emitting element2band electrically connected to the first semiconductor layer201of the first light-emitting element2b; and a third connecting section703formed in the trench11, disposed between the first recess204aand the second recess204b, and between the first connecting section701and the second connecting section702.

As shown inFIG.9andFIG.9A, the first insulating layer30and/or the second insulating layer60are formed between the first connecting section701and the first semiconductor layer201. The first insulating layer30and/or the second insulating layer60are formed between the second connecting section702and the first semiconductor layer201.

In an embodiment of the present application, in the top view of the light-emitting device2, the connecting electrode70includes a width of at least 15 μm or more, preferably more than 30 μm, and more preferably more than 50 μm.

As shown inFIG.7,FIG.9, andFIG.9A, the light-emitting device2includes a first bottom electrode71aon the first light-emitting element2a, a second bottom electrode71bon the second light-emitting element2b, and a second top electrode72bon the second light-emitting element2b. The external current is injected into the light-emitting device2through the first bottom electrode71aand the second top electrode72b, and electrically connects the first light-emitting element2aand the second light-emitting element2bin series through the second connecting section702of the connecting electrode70extended from the second bottom electrode71b, the third connecting section703in the trench11and the first connecting section701.

As shown inFIG.7,FIG.9, andFIG.9A, the second insulating layer60is located between the second connecting section702and the first semiconductor layer201of the second light-emitting element2bto prevent the second connecting section702from directly contacting the first semiconductor layer201of the second light-emitting element2b. As shown inFIG.7andFIG.10, the second element opening600bof the second insulating layer60exposes the first semiconductor layer201on the second recess204bof the second light-emitting element2b. The second bottom electrode71bdirectly contacts the first semiconductor layer201of the second light-emitting element2bthrough the second element opening600bof the second insulating layer60. The current flowing through the second connecting section702is conducted to the first semiconductor layer201of the second light emitting element2bby the second bottom electrode71bof the second light-emitting element2b.

The connecting electrode70, the first bottom electrode71a, the second bottom electrode71band/or the second top electrode72binclude a metal material including chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The connecting electrode70, the first bottom electrode71a, the second bottom electrode71band/or the second top electrode72binclude single layer or multilayers. For example, the connecting electrode70, the first bottom electrode71a, the second bottom electrode71band/or the second top electrode72binclude Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack.

The connecting electrode70, the first bottom electrode71a, the second bottom electrode71band/or the second top electrode72binclude a thickness preferably between 0.5 μm and 3.5 μm.

As shown inFIG.9,FIG.9A, andFIG.10, the light-emitting device2includes a third insulating layer80formed on the first light-emitting element2aand the second light-emitting element2b. A first opening801of the third insulating layer80is formed on the first bottom electrode71aby selective etching to expose a top surface of the first bottom electrode71a. A second opening802of the third insulating layer80is formed on the second top electrode72bto expose a top surface of the second top electrode72b.

The second insulating layer60or the third insulating layer80includes an insulating material having light transparency. For example, the third insulating layer80includes SiOx.

As shown inFIG.7,FIG.9,FIG.9A, andFIG.10, the light-emitting device2includes a first electrode pad91to cover the first opening801of the third insulating layer80and contact the first bottom electrode71a. The first electrode pad91is electrically connected to the first semiconductor layer201of the first light-emitting element2aby the first bottom electrode71a. The light-emitting device2includes a second electrode pad92covering the second opening802of the third insulating layer80and contacting the second top electrode72b.

In an embodiment, as shown inFIG.9, the first sidewall2011of the first semiconductor layer201near the first section1031of the third side surface is not covered by the third insulating layer80. The second sidewall2012of the first semiconductor layer201near the second section1032of the third side surface is covered by the third insulating layer80.

In an embodiment, as shown inFIG.9A, the first sidewall2011of the first semiconductor layer201near the first side surface101of the substrate10is covered by the third insulating layer80. The second sidewall2012of the first semiconductor layer201near the second section1042of the fourth side surface is covered by a third insulating layer.

In an embodiment, as shown inFIG.10, the first sidewall2011of the first semiconductor layer201adjacent to the first section1041of the fourth side surface104is not covered by the third insulating layer80. The second sidewall2012of the first semiconductor layer201near the second section1042of the fourth side surface104is covered by the third insulating layer80.

The first electrode pad91and the second electrode pad92include a metal material including chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first electrode pad91and the second electrode pad92include single layer or multilayers. For example, the first electrode pad91or the second electrode pad92includes Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack.

In an embodiment of the present application, the first electrode pad91includes a size that is the same as or different from a size of the second electrode pad92. The size includes a width or an area. For example, a top area of the first electrode pad91or the second electrode pad92may be 0.8 times or more and less than one time a sum obtained by adding the top areas of the first electrode pad91and the second electrode pad92.

The first electrode pad91or the second electrode pad92respectively includes an inclined side surface, and the cross-sectional area of the first electrode pad91or the second electrode pad92varies along the thickness direction of the light-emitting device2. For example, the cross-sectional area of the first electrode pad91or the second electrode pad92gradually diminishes away from the upper surface of the semiconductor stack20.

The first electrode pad91or the second electrode pad92includes a thickness between 1 and 100 μm, preferably between 1.5 and 6 μm.

A space is between the first electrode pad91and the second electrode pad92, and the space includes a distance between 10 μm and 250 μm. In the distance range described above, the top view area of the first electrode pad91and the second electrode pad92can be increased by reducing the distance of the space between the first electrode pad91and the second electrode pad92. The heat dissipation efficiency of the light-emitting device1can be improved, and a short circuit between the first electrode pad91and the second electrode pad92also can be avoided.

FIG.11illustrates a cross-sectional view taken along line F-F′ ofFIG.7.FIG.12illustrates a cross-sectional view taken along line G-G′ ofFIG.7In an embodiment of the present application, as shown inFIG.7, in the top view of the light-emitting device2, the light-emitting device2includes a plurality of corners, wherein the plurality of corners includes a first corner C1, a second corner C2, a third corner C3 and a fourth corner C4. The light-emitting device2includes a plurality of semiconductor structures206, wherein the plurality of semiconductor structures206includes a first semiconductor structure2061, a second semiconductor structure2062, a third semiconductor structure2063, and a fourth semiconductor structure2064. The positions of the first semiconductor structure2061, the second semiconductor structure2062, the third semiconductor structure2063, and the fourth semiconductor structure2064are respectively located at the first corner C1, the second corner C2, the third corner C3, and the fourth corner C4.

In another embodiment of the present application (not shown), the light-emitting device2includes a plurality of edges, wherein the plurality of edges includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. A plurality of semiconductor structures206is respectively located on the plurality of edges.

As shown inFIG.7,FIG.11, andFIG.12, the first semiconductor structure2061and the fourth semiconductor structure2064are respectively separated from the first semiconductor mesa205aby a distance, and the first semiconductor structure2061and the fourth semiconductor Structures2064are separated from each other. The second semiconductor structure2062and the third semiconductor structure2063are respectively separated from the second semiconductor mesa205bby a distance, and the second semiconductor structure2062and the third semiconductor structure2063are separated from each other.

As shown inFIG.11, the first semiconductor structure2061adjacent to the first edge E1 is separated from the first semiconductor mesa205aby a first shortest distance L1, and the fourth semiconductor structure2064adjacent to the first edge E1 is separated from the semiconductor mesa205aby a fourth shortest distance L4 (not shown). As shown inFIG.12, the second semiconductor structure2062adjacent to the second edge E2 is separated from the second semiconductor mesa205bby a second shortest distance L2, and the third semiconductor structure2063adjacent to the second edge E2 is separated from the second semiconductor mesa205bby a third shortest distance L3 (not shown).

In an embodiment of the present application, the second shortest distance L2 and the third shortest distance L3 are respectively larger than the first shortest distance L1.

As shown inFIG.7andFIG.11, in an embodiment of the present application, the first semiconductor layer201adjacent to the first corner C1 is located between the first semiconductor structure2061and the first semiconductor mesa205a, and connects the first semiconductor structure2061and the first semiconductor mesa205a. The first semiconductor layer201adjacent to the fourth corner C4 is located between the fourth semiconductor structure2064and the first semiconductor mesa205a, and connects the fourth semiconductor structure2064with the first semiconductor mesa205a(not shown). As shown inFIG.7andFIG.12, in an embodiment of the present application, the first semiconductor layer201adjacent to the second corner C2, and between the second semiconductor structure2062and the second semiconductor mesa205bis removed to expose the substrate10, and the second semiconductor structure2062and the second semiconductor mesa205bare separated from each other. Adjacent to the third corner C3, the first semiconductor layer201between the third semiconductor structure2063and the second semiconductor mesa205bis removed to expose the substrate10, and the third semiconductor structure2063and the second semiconductor mesa205bare separated from each other (not shown).

In an embodiment of the present application, in the top view of the light-emitting device2, the first semiconductor structure2061, the second semiconductor structure2062, the third semiconductor structure2063, and the fourth semiconductor structure2064include a shape including rectangular, triangular or fan shape.

FIG.13Aillustrates a manufacturing method of a light-emitting device1A in accordance with an embodiment of the present application.FIG.13Billustrates the manufacturing method of the light-emitting device1A in accordance with an embodiment of the present application.FIG.13Cillustrates a top view of the light-emitting device1A in accordance with an embodiment of the present application.

FIG.13Ais a partial top view of the wafer in the manufacturing process of the light-emitting device1A on the wafer.

As described above, the wafer including gallium arsenide (GaAs) wafer, sapphire (Al2O3) wafer, gallium nitride (GaN) wafer, or silicon carbide (SiC) wafer is used as a growth substrate. Growing the semiconductor stack on the growing substrate by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion plating, for example, a light-emitting structure composed of a first semiconductor layer, a second semiconductor layer, and an active layer. The electrodes and the insulating layers are subsequently formed by the lithography process and the etching process.

After forming a wafer including a semiconductor light-emitting device thereof, the wafer is separated into individual semiconductor light-emitting devices by dicing. Since the size of the light-emitting device has a tendency to gradually decrease according to different applications, for example, the area of a single light-emitting device is less than 100,000 μm2, if the accuracy of the dicing is not precise enough, the production yield of the light-emitting device is affected. Therefore, in the dicing process, it is necessary to provide a reference point preserved to the dicing device (not shown) so that the dicing device can be accurately positioned on the dicing path. The disclosure provides an identification method and identification structure assisting the accuracy of the dicing to improve the production yield of the light-emitting device.

Refer toFIG.13AandFIG.13B.FIG.13Bis a partially enlarged view of positions1001,2001and3001shown inFIG.13A. The scribe lines Z1, Z2 are formed on the wafer including the light-emitting device1A to define a plurality of light-emitting devices1A. A second identification structure222is disposed on a side of the light-emitting device1A adjacent to the scribe line Z1, and/or a first identification structure221and a third identification structure223are respectively disposed on two corners adjacent to the aforementioned side. The identification structures221,222and223are used as markings for the dicing device to identify the position of the scribe line Z1.

In an embodiment of the present application, a plurality of light-emitting devices TA is arranged in an array on the wafer. In order to accurately dice the plurality of light-emitting devices TA, a second identification structure222is disposed on each side of the light-emitting device1A, or a first identification structure221or a third identification structure223is disposed on each corner of the light-emitting device1A. The first identification structure221, the second identification structure222, and/or the third identification structure223include a semiconductor structure.

In an embodiment, the semiconductor structure of the second identification structure222, the first identification structure221, and/or the third identification structure223includes a semiconductor stack.

In an embodiment of the present application, as shown inFIG.13C, the light-emitting device1A includes a semiconductor stack, the first identification structure221at the corner position1000, the second identification structure222at the edge2000, and the third identification structure22at the corner3000, wherein the first identification structure221, the second identification structure222and the third identification structure22respectively includes the semiconductor structure. The light-emitting device TA includes the plurality of edges and the plurality of corners, wherein the corner is formed by two adjacent edges. The plurality of edges includes a first edge IOTA, a second edge102A, a third edge103A, and a fourth edge104A. The plurality of semiconductor structures is respectively located on the plurality of corners or the plurality of sides. The plurality of semiconductor structures is located at the plurality of corners. For example, the first identification structure221or the third identification223are separated from the semiconductor stack by a distance. In an embodiment, the first identification structure221is separated from the semiconductor stack by the distance mentioned above, the first identification structure221does not connect to the semiconductor stack and there is no semiconductor layer between the first identification structure221and the semiconductor stack; the third identification structure223is connected to the semiconductor stack with the semiconductor layers. The distance mentioned above exposes the semiconductor stack or the surface of the substrate. The plurality of semiconductor structures, such as the first identification structure221or the third identification structure223, are separated from each other. The plurality of semiconductor structures on the plurality of edges, such as the second identification structure222, is directly connected to the semiconductor stack.

FIG.14is a schematic view of a light-emitting apparatus3in accordance with an embodiment of the present application. The light-emitting device1, TA,2or5in the foregoing embodiment is mounted on the first spacer511and the second spacer512of the package substrate51in the form of flip chip. The first spacer511and the second spacer512are electrically insulated from each other by an insulating portion53including an insulating material. The main light-extraction surface of the flip chip is one side of the growth substrate opposite to the electrode-forming surface where the electrodes are formed on. A reflective structure54can be provided around the light-emitting device1, TA,2or5to increase the light extraction efficiency of the light-emitting apparatus3.

Another object of the present application is to provide a light-emitting device and a manufacturing method thereof which improve the reliability of a package device. The light-emitting device1is illustrated as an example, when the light-emitting device1is flipped to be mounted onto the first spacer511and the second spacer512of the package substrate51, the first electrode pad91is bonded to the first spacer511through the solder, and the second electrode pad92is bonded to the second spacer512through the solder. Since the first electrode pad91is electrically connected to the first semiconductor layer201, even the solder overflows from the first electrode pad91to contact the first semiconductor layer201, the light-emitting device1does not have leakage failure. However, the second electrode pad92is electrically connected to the second semiconductor layer202, and if the solder overflows from the second electrode pad92to contact the first semiconductor layer201, the light-emitting device1fails because of electrical discharge. The present application is to improve the reliability of the light-emitting device by forming the third insulating layer80to cover the outer surface204sand the second side wall2012of the first semiconductor layer201on the side close to the second electrode pad92, thereby improving the reliability of the light-emitting device. Further, since the first semiconductor layer201adjacent to the first electrode pad91does not need to be covered by insulating layers, it is also possible to reduce the area where the semiconductor layers are removed, thereby improving the brightness of the light-emitting device.

FIG.15illustrates a structure diagram of a light-emitting apparatus4in accordance with an embodiment of the present application. A light bulb includes an envelope602, a lens604, a light-emitting module610, a base612, a heat sink614, a connector616and an electrical connecting device618. The light-emitting module610includes a submount606and a plurality of light-emitting devices608on the submount606, wherein the plurality of light-emitting devices608can be the light-emitting device1,1A,2,5or the light-emitting apparatus3described in above embodiments.

The principle and the efficiency of the present application illustrated by the embodiments above are not the limitation of the application. Any person having ordinary skill in the art can modify or change the aforementioned embodiments. Therefore, the protection range of the rights in the application will be listed as the following claims.