Patent ID: 12207569

DETAILED DESCRIPTION

Technologies are described for constructing and packaging microwave integrated quantum circuits to be used in quantum computing systems. Prior to describing example implementations of techniques for constructing and packaging microwave integrated quantum circuits, structural aspects and functional aspects of a quantum computing system are described.

FIG.1shows an example of a quantum computing system100. The quantum computing system100includes a control system110, a signal delivery system106, and a quantum processor cell102. More generally, quantum computing systems may include additional or different features, and the components of a quantum computing system may operate as described with respect toFIG.1or in another manner.

The quantum computing system100shown inFIG.1can perform quantum computational tasks by executing quantum algorithms (e.g., step-by-step procedures for solving a problem on a quantum computer). In some implementations, the quantum computing system100can perform quantum computation by storing and manipulating information within individual quantum states of a composite quantum system. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system. Coupler devices can be used to perform quantum logic operations on single qubits or conditional quantum logic operations on multiple qubits. In some instances, the conditional quantum logic can be performed in a manner that allows large-scale entanglement within the quantum computing device. Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the individual qubits.

In some implementations, the quantum computing system100can operate using gate-based models for quantum computing. In some models, fault-tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, topological quantum error correction schemes can operate on a lattice of nearest-neighbor-coupled qubits. In some instances, these and other types of quantum error correcting schemes can be adapted for a two- or three-dimensional lattice of nearest-neighbor-coupled qubits, for example, to achieve fault-tolerant quantum computation. The lattice can allow each qubit to be independently controlled and measured without introducing errors on other qubits in the lattice. Adjacent pairs of qubits in the lattice can be addressed, for example, with two-qubit gate operations that are capable of generating entanglement, independent of other pairs in the lattice.

In some implementations, the quantum computing system100is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large number of qubits to achieve large-scale general purpose coherent quantum computing. In some instances, the architecture is adaptable and can incorporate a variety of modes for each technical component. For example, the architecture can be adapted to incorporate different types of qubit devices, coupler devices, readout devices, signaling devices, etc.

The quantum processor cell102includes qubit devices that are used to store and process quantum information. In some instances, all or part of the quantum processor cell102functions as a quantum processor, a quantum memory, or another type of subsystem. The quantum processor cell102can be implemented, for example, based on the examples described below or in another manner.

In the quantum processor cell102, the qubit devices each store a single qubit (a bit of quantum information), and the qubits can collectively define the computational state of a quantum processor or quantum memory. The quantum processor cell102may also include readout devices that selectively interact with the qubit devices to detect their quantum states. For example, the readout devices may generate readout signals that indicate the computational state of the quantum processor or quantum memory. The quantum processor cell102may also include coupler devices that selectively operate on individual qubits or pairs of qubits. For example, the coupler devices may produce entanglement or other multi-qubit states over two or more qubits in the quantum processor cell102.

In some implementations, the quantum processor cell102processes the quantum information stored in the qubit devices by applying control signals to the qubit devices or to the coupler devices housed in the quantum processor cell. The control signals can be configured to encode information in the qubit devices, to process the information by performing logical gates or other types of operations, or to extract information from the qubit devices. In some examples, the operations can be expressed as single-qubit gates, two-qubit gates, or other types of logical gates that operate on one or more qubit devices. A sequence of operations can be applied to the qubit devices to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.

The signal delivery system106provides communication between the control system110and the quantum processor cell102. For example, the signal delivery system106can receive control signals (e.g., qubit control signals, readout control signals, coupler control signals, etc.) from the control system110and deliver the control signals to the quantum processor cell102. In some instances, the signal delivery system106performs preprocessing, signal conditioning, or other operations to the control signals before delivering them to the quantum processor cell102. In many instances, the signal delivery system106includes an interposer which provides electrical connections between the quantum processor cell102and cables (or other signal lines) to the control system110.

The control system110controls operation of the quantum processor cell102. The control system110may include data processors, signal generators, interface components and other types of systems or subsystems. In some cases, the control system110includes one or more classical computers or classical computing components.

Various implementations of the quantum processor cell102are described below, including various embodiments of its components along with various methods for fabricating the quantum processor cell and its components.

While generally the quantum processor cell102can be implemented using a variety of different qubit devices, readout devices, and coupler devices,FIG.2Ashows an equivalent circuit of an example of a microwave integrated quantum circuit148that can be used to perform quantum operations. Here, the microwave integrated quantum circuit148includes a subset of qubit devices144, their corresponding readout devices146and a subset of the coupler devices142from the quantum processor cell102. In this example, the microwave integrated quantum circuit148includes qubit devices144-jand144-(j+1), corresponding readout devices146-jand146-(j+1), and a tunable coupler device142-(j,j+1) disposed between the qubit devices144-jand144-(j+1). In the example shown inFIG.2A, each of the qubit devices144-jand144-(j+1) is capacitively coupled to the coupler device142-(j,j+1) by respective differential capacitances150-jand150-(j+1). Also, each of the qubit devices144-jand144-(j+1) is capacitively coupled to its respective readout device146-jand146-(j,j+1) by respective differential capacitances152-jand152-(j+1).

Write signals (e.g., coupler control signals, qubit control signals, readout control signals, etc.) can be transmitted from the control system110, through the signal delivery system106, to various input ports of the microwave integrated quantum circuit148. An example of such input port is shown inFIG.2Aas a coupler control input port154-(j,j+1). In this manner, the tunable coupler device142-(j,j+1) is inductively coupled with a source of coupler control signals at the coupler control input port154-(j,j+1). Other examples of input ports are shown inFIG.2Aas qubit+readout control port156-jand qubit+readout control port156-(j+1). In this manner, each of the readout devices146-jand146-j+1 is capacitively coupled to a source of qubit control signals and a source of readout control signals at the respective qubit+readout control ports156-jand156-(j+1). Additionally, readout signals (e.g., qubit readout signals) are received by the control signal110through the system delivery system106and from various output ports in the microwave integrated quantum circuit148. In the example microwave integrated quantum circuit148shown inFIG.2A, the qubit+readout control ports156-jand156-(j+1) also are used as output ports. Note that the control signals and the readout signals used to operate the quantum circuit devices of the microwave integrated quantum circuit148and of other microwave integrated quantum circuits disclosed in this specification have frequencies in the microwave frequency range. As such, the term operating frequency (i.e., f0) of a quantum circuit device, as used in this specification, represents a microwave frequency of a control signal or a readout signal used to operate quantum circuit devices of a microwave integrated quantum circuits disclosed in this specification.

Each of the qubit devices144-j,144-(j+1) includes a Josephson junction (represented by the symbol “X” inFIG.2A) and a shunt capacitance. Qubit devices144-j,144-(j+1) can be implemented as transmon qubits, as flux qubits or as fluxonium qubits, as described in connection withFIG.3Bof PCT application publication WO 2015/178990, the content of which is incorporated herein by reference. In the example shown inFIG.2A, the tunable coupler device142-(j,j+1) includes a Josephson junction (represented by the symbol “X” inFIG.2A), a shunt inductance and a shunt capacitance. A tunable coupler device142can be implemented as a fluxonium coupler170, as described in connection withFIG.3Bof PCT application publication WO 2015/178990.

The portion of the microwave integrated quantum circuit148illustrated inFIG.2Acan be copied multiple times, e.g., as a unit cell, to extend the microwave integrated quantum circuit148along a path (e.g., along x-axis of a Cartesian coordinate system), on a surface (e.g., x-y plane of a Cartesian coordinate system) or in space (e.g., as layers parallel to x-y plane that are distributed along a z-axis of a Cartesian coordinate system). For example, fault-tolerance quantum computing can be achieved by implementing gate-based models in a two-dimensional (2D) microwave integrated quantum circuit148that includes a large number of nearest-neighbor coupled qubit devices144. A 2D microwave integrated quantum circuit148can allow each qubit device144to be independently controlled and measured without introducing crosstalk or errors on other qubit devices144in the 2D microwave integrated quantum circuit. Nearest-neighbor pairs of qubit devices144in the 2D microwave integrated quantum circuit148should be addressable with two-qubit gate operations capable of generating entanglement, independent of all other such pairs in the 2D microwave integrated quantum circuit148. Exemplary implementations of 2D microwave integrated quantum circuits200,300,400,500,600A,600B are described below in relation to respectiveFIGS.2B,3A,4A,5A,6A,6B. As another example, fault-tolerant quantum computing can likewise be performed in a three-dimensional (3D) microwave integrated quantum circuit148M that includes a large number of nearest-neighbor coupled qubit devices144. Exemplary implementations of 3D microwave integrated quantum circuits400M,600AM,600BM are described below in relation to respectiveFIGS.4E,6E,6F.

A variety of technical features may be used (alone or in combination) in microwave integrated quantum circuits to carry out large-scale, fault tolerant quantum computing. One such feature is the delivery of control signals to qubit devices144and tunable coupling devices142of a 2D microwave integrated quantum circuit148or a 3D microwave integrated quantum circuit148, and another such feature is the extraction of measurement signals from the qubit devices144being performed with low-crosstalk of the applied signals from target qubit devices to non-target qubit devices. Another such feature is the ability to sustain coherence of individual and entangled quantum states of the qubit devices144of the 2D microwave integrated quantum circuit148or the 3D microwave integrated quantum circuit148. Yet another such feature is the shielding and isolation of the qubit device144-jfrom external noise, from the external environment, and from each other qubit device144-(j+k) in the 2D microwave integrated quantum circuit148or the 3D microwave integrated quantum circuit148to which the qubit device144-jis not specifically coupled (k≠0 or ±1) for performing a two-qubit gate.

For instance,FIG.2Bshows a 2D microwave integrated quantum circuit200, similar to the microwave integrated quantum circuit148, including quantum circuit devices240fabricated on a first substrate210. As the first substrate supports the quantum circuit devices240, it will also be referred to as the circuit wafer210. Microwave signals may be used to operate each of the quantum circuit devices240of 2D microwave integrated quantum circuit200. In this example, such microwave signals can propagate to nearest-neighbor quantum circuit devices (and beyond) by the appearance of an in-air electric field spatial distribution (i.e., Eair) and an in-substrate electric field spatial distribution (i.e., Esub) of the operating signals, as shown inFIG.2B. Additionally, the quantum circuit devices240of the 2D microwave integrated quantum circuit200may be exposed to the external electromagnetic environment.

In some implementations, the quantum circuit devices240can be isolated (e.g., exponentially) from each other using one encapsulation substrate or a pair of encapsulation substrates lined with an electrically conducting layer that is grounded during operation of the microwave integrated quantum circuits (e.g., see 2D microwave integrated quantum circuits300,400and 3D microwave integrated quantum circuit400M, described below). In some implementations, the electrically conducting layer includes a multi-layer material stack. The multi-layer material stack may include one or more layers of superconducting material and one or more layers of non-superconducting material (e.g., palladium), while maintaining one or more superconducting properties. Here, recesses of the encapsulation substrates are sized to cause available modes of the recesses to evanesce with respect to relevant operating frequencies of the encapsulated quantum circuit devices240. In certain implementations, the quantum circuit devices240can be isolated from each other using electrically conducting thru vias formed in the circuit wafer210of the 2D microwave integrated quantum circuit, where the electrically conducting thru vias are grounded during operation of the microwave integrated quantum circuit (e.g., see 2D microwave integrated quantum circuit500, described below). Here, the electrically-conducting thru vias are distributed around a respective footprint of each quantum circuit device240to cause available modes of the electrically conducting thru via distribution to evanesce with respect to relevant operating frequencies of the surrounded quantum circuit device. In some implementations, a combination of an encapsulation substrate and electrically-conducting thru vias so-distributed is used to isolate the quantum circuit devices240from each other (e.g., see 2D microwave integrated quantum circuits600A,600B, and 3D microwave integrated quantum circuits600AM,600BM, described below). In this manner, the quantum circuit devices240can be shielded and isolated from their nearest neighbors and from the external electromagnetic environment.

FIG.3Ais a side view of a 2D microwave integrated quantum circuit300, andFIG.3Bis a top view of the same circuit in the vicinity of one of a plurality of quantum circuit devices240included in the 2D microwave integrated quantum circuit. Here, the 2D microwave integrated quantum circuit300includes a first substrate210, also referred to as a circuit wafer, such that the quantum circuit devices240are disposed on a first surface of the circuit wafer210. Each quantum circuit device QC-j240, where j=1, 2, 3, . . . , has an associated operating frequency f0-j. In some implementations, the operating frequencies of the quantum circuit devices240are different from each other. In other implementations, at least some of the quantum circuit devices240have common operating frequencies.

The 2D microwave integrated quantum circuit300further includes a second substrate310having a first surface that defines recesses320of the second substrate that correspond to the quantum circuit devices240disposed on the circuit wafer210. In this manner, the circuit wafer210and second substrate310are arranged such that each recess320of the second substrate forms an enclosure that houses a respective quantum circuit device240. A dimension Ch, e.g., along the z-axis, of each recess320can range from 5 μm-500 μm (e.g., 20 μm-200 μm) for a thickness of the second substrate210in a range from 1 μm to 1 mm. As the second substrate310“caps” the quantum circuit devices240disposed on the circuit wafer210, the second substrate will be referred to as the cap wafer310. Note that the cap wafer310is bonded to the circuit wafer210, as described below in relation toFIGS.14A-14B,15and16. In addition, spacers (or standoff bumps) may be used between the bonded cap wafer310and the circuit wafer210, as described below in relation toFIGS.12,13A-13B,14A-14B,15and16.

Additionally, the 2D microwave integrated quantum circuit300includes an electrically conducting layer350that covers at least a portion of each of the recesses320of the cap wafer310. In some implementations, the electrically conducting layer350includes a material (e.g., Al, In, Ti, Pn, Sn, etc.) that is superconducting at an operating temperature of the 2D microwave integrated quantum circuit300. In other implementations, the electrically conducting layer350includes a material that has normal conductance (i.e., it is an electrical conductor but not superconducting) at the operating temperature of the 2D microwave integrated quantum circuit300. In this manner, the 2D microwave integrated quantum circuit300can be operated at cryogenic temperatures (e.g., using liquid helium) and the electrically conducting layer350(or at least a portion thereof) can operate as a superconducting layer at that temperature. In addition, during operation of the 2D microwave integrated quantum circuit300, the electrically conducting layer350is grounded. Although illustrated as one layer inFIG.3A, in some implementations, the electrically conducting layer350includes a multi-layer material stack. For example, the electrically conducting layer350may include a stack similar to the stacks2811,2821described below with respect toFIG.28. In some instances, one or more layers of the multi-layer material stack include a superconducting material. In some instances, one or more layers of the multi-layer material stack include a non-superconducting material (e.g., palladium, platinum, or gold), but the multi-layer material stack may maintain one or more superconducting properties. For example, despite containing a non-superconducting material, the multi-layer material stack may exhibit a zero or near-zero resistance (e.g., less than one milli-ohm).

Moreover, each recess320is configured (e.g., sized) to suppress propagation inside the recess of electromagnetic waves that have frequencies “f” below a cutoff frequency fC, (i.e., f<fC), where the cutoff frequency fCis larger than the operating frequency f0, (i.e., f0<fC) of the respective encapsulated quantum circuit device240. The noted suppression of the propagation of the recess modes is illustrated inFIG.3Aby the relative appearance of the in-air electric field spatial distribution (i.e., Eair) and the in-substrate electric field spatial distribution (i.e., Esub) of operating signals. Note that because the cutoff frequency fCis larger than the operating frequency f0, the enclosure formed by the recess320is a non-resonant cavity relative to operation of the encapsulated quantum circuit device240.

In this manner, a lateral dimension WW of a recess320is smaller than a maximum distance LMAX corresponding to the cutoff frequency fC. For example, the lateral dimension WW of a recess320can be range from 20 μm to 2 mm. Additionally, a distance DW between the outer perimeter of the encapsulated quantum circuit device240and a nearest wall of the recess320corresponds to a value of a capacitance between the encapsulated quantum circuit device and the portion of the electrically conducting layer350that covers the wall of the recess.

Moreover, adjacent quantum circuit devices240disposed on the circuit wafer210can be coupled electromagnetically through a coupling line that includes an electrical conductor241extending along the first surface of the circuit wafer over at least a portion of the distance between the adjacent quantum circuit devices. The coupling between the adjacent quantum circuit devices240can be capacitive or direct. Note that at least a portion of the coupling line is encapsulated by a trench321of the cap wafer310, as illustrated inFIG.3B.

The use of the cap wafer310can improve coherence times of the quantum circuit devices240disposed on the circuit wafer210. Quantum circuit devices240with long coherence times are useful for the realization of a robust quantum processor cell106. The cap wafer310can improve coherence times of the quantum circuit devices240of the 2D microwave integrated quantum circuit300relative to the 2D microwave integrated quantum circuit200. Such improvement can include decreasing the participation ratio of the circuit wafer210(which is lossy at microwave frequencies) and increasing that of the air (which is lossless) so that more of the field resides in air. To estimate the improvement in coherence time due to cap wafer310we consider a dimension Chof the recess320of the cap wafer310on top of a silicon circuit wafer210of a given thickness. The participation ratios of the substrate P and air P are defined as

Pa⁢i⁢r=EairEair+Es⁢u⁢b(1)Pa⁢i⁢r=Es⁢u⁢bEair+Es⁢u⁢b(2)
where Eair=∫dVϵair|Eair|2and Esub=∫dVϵsub|Esub|2are energies stored, respectively in the electric field in air (i.e., Eair) and in the circuit wafer210(i.e., Esub).

The loss in the circuit wafer210can be described by the quality factor, QΣ. In general, the dissipation factor (the loss-rate of energy) is related to the tangent δ via

1QΣ=∑j⁢Pj⁢tan⁢δj(3)

The coherence time T1can be expressed in terms of the quality factor as

T1=QΣω=1ω⁢Ps⁢u⁢b⁢tan⁢δs⁢u⁢b(4)
where ω is the operating frequency of a quantum circuit device240.

The participation ratio of air can be increased by tuning the dimension Chof the recess320of the cap wafer310as compared to the thickness of the circuit wafer210. Simulations show that a more concentrated field in air is observed when the dimension Chof the recess320is smaller than the thickness of the circuit wafer210.

FIG.3Cis a plot301that shows that, for a thickness of 100 μm for the circuit wafer210, the participation ratio of the circuit wafer decreases as the dimension Chof the recess320of the cap wafer310decreases. This effect is substantial when the dimension Chof the recess320is below 50 μm. Note that the dimension Chof the recess320cannot be decreased indefinitely due to the possibility of other undesired effects, such as surface loss.

FIG.3Dis a plot303that shows a dependence of the coherence time T1on a dimension Chof the recess320of the cap wafer310. The dependence is illustrated for multiple operating frequencies (i.e., f0) of the quantum circuit devices240, which is enclosed by the recess320. A comparison of plots301and303suggests that the coherence time T1increases as the participation ratio of the circuit wafer210decreases. The participation ratio of air can be further improved by sandwiching the circuit wafer210between a pair of cap wafers, as described below.

FIG.4Ais a side view of a 2D microwave integrated quantum circuit400that includes a third substrate410(also referred to as a second cap wafer) in addition to the circuit wafer210that supports on its first surface the quantum circuit devices240and the cap wafer310described above in connection withFIGS.3A-3B. The second cap wafer410has a first surface that defines recesses420of the third substrate that also correspond to the quantum circuit devices240disposed on the circuit wafer210. Here, the circuit wafer210is sandwiched between the cap wafer310and the second cap wafer410. Moreover, the cap wafer310and the second cap wafer410are arranged such that each recess420of the second cap wafer410and a back surface of the circuit wafer210form an enclosure that registers with a respective recess320. The recess320houses an associated quantum circuit device240. Note that the second cap wafer410is bonded to the circuit wafer210, as described below in connection withFIGS.15&16. In addition, spacers (or standoff bumps) may be used between the bonded cap wafer310and circuit wafer210, as described below in relation toFIGS.12,13A-13B,15and16.

Additionally, the 2D microwave integrated quantum circuit400includes an electrically-conducting layer450that covers at least a portion of each of the recesses420of the second cap wafer410. In some implementations, the electrically conducting layer450includes a material (e.g., Al, In, Ti, Pn, Sn, etc.) that is superconducting at an operating temperature of the 2D microwave integrated quantum circuit400. In other implementations, the electrically conducting layer450includes a material that has a normal conductance (i.e., it is electrically conducting but not superconducting) at the operating temperature of the 2D microwave integrated quantum circuit400. In this manner, the 2D microwave integrated quantum circuit400can be operated at cryogenic temperatures (e.g., using liquid helium) and the electrically-conducting layer450(or at least a portion thereof) can operate as a superconducting layer at that temperature. In addition, during operation of the 2D microwave integrated quantum circuit400, both electrically-conducting layers350and450are grounded. Although illustrated as one layer inFIG.4A, in some implementations, the electrically-conducting layer450includes a multi-layer material stack. For example, the electrically conducting layer450may include a stack similar to the stacks2811,2821described below in relation toFIG.28. In some instances, one or more layers of the multi-layer material stack include a superconducting material. In some instances, one or more layers of the multi-layer material stack include a non-superconducting material (e.g., palladium, platinum, or gold), but the multi-layer material stack may maintain one or more superconducting properties. For example, despite containing a non-superconducting material, the multi-layer material stack may exhibit a zero or near-zero resistance (e.g., less than one milli-ohm).

Moreover, each recess420is configured (e.g., sized) to suppress propagation of electromagnetic waves that have frequencies “f” below the cutoff frequency fC(i.e., f<fC). Such suppression may occur inside the recess and across a volume of the circuit wafer210that is sandwiched between the recesses320and420. The noted propagation suppression of the recess modes and of the substrate modes is illustrated inFIG.4Aby the relative appearance of an in-air electric field spatial distribution (i.e., Eair) and an in-substrate electric field spatial distribution (i.e., Esub) of operating signals. Note that because the cutoff frequency fCis larger than the operating frequency f0, the enclosure formed by the recess420also is a non-resonant cavity relative to operation of the quantum circuit device240encapsulated in the non-resonant cavity formed by the recess320.

Performance of the quantum circuit devices240of the 2D microwave integrated quantum circuit400can improve relative to the 2D microwave integrated quantum circuit300in the following manner. A participation ratio of the 2D microwave integrated quantum circuit400is given by

Pk=EkEair,1+Eair,2+Esub(5)
where Eair,1=∫dVϵair,1|Eair,1|2, Eair,1=∫dVϵair,1|Eair,1|2, and Esub=∫dVϵsub|Esub|2are energies stored in the electric field in air (i.e., Eair,1) confined by the top recess320, electric field in air (i.e., Eair,2) confined by the bottom recess420, and electric field confined in the circuit wafer210, respectively.

The participation ratio of the circuit wafer210, in general, increases as its thickness increases. For example, for a fixed Chdimension of the top recess320and the bottom recess320of 100 μm, the participation ratio of the circuit wafer210can be as low as 70% for a circuit wafer of thickness 100 μm.FIG.4Bis a plot401that shows that the participation ratio goes up to 90% when the thickness of the circuit wafer210is increased to 500 μm. This increase is because, when the circuit wafer210is thick, most of the electric field emitted by the enclosed quantum circuit device240will be stored in the substrate.

Note that the participation ratio strongly depends on the dimension Chof the top and bottom recesses320and420. The smaller the dimension Chof the top recess320, the larger the participation ratio of air, and the smaller the participation ratio of the circuit wafer210.FIG.4Cis a plot403that shows that, fixing the thickness of the circuit wafer210at 100 μm (a minimum thickness such that the circuit wafer is mechanically robust and reasonable to handle in microfabrication processes), the participation ratio of the circuit wafer can go below 50% for a dimension Chof the top recess320of less than 50 μm and a dimension Chof the bottom recess420of 500 μm. In fact, the participation ratio of the circuit wafer210can be significantly reduced by using dimensions Chof the top and bottom recesses320,420less than 50 μm along with a thin (less than 200 μm) thick circuit wafer210. It is therefore beneficial to use two cap wafers310,410to decrease the participation ratio of circuit wafer210, albeit fabrication and bonding subtleties. Alternatively, the thickness of the circuit wafer210can be extremely thin (e.g., less than 10 μm) to reduce or minimize the participation ratio of the circuit wafer. Such a 2D microwave integrated quantum circuit can be fabricated on a thin membrane made of a low-loss material such as high-quality silicon oxide or silicon nitride substrates.

FIG.4Dis a top view of either the 2D microwave integrated quantum circuit300or the 2D microwave integrated quantum circuit400. Here, it is shown that the 2D microwave integrated quantum circuit300,400can be scaled to a large number of quantum circuit devices240that include multiple qubits144, resonators146,148, tunable couplers142, and so forth. Here, distances between adjacent qubits144can range from 0.5 mm to 5 mm, for instance. Note that recesses320of the (top) cap wafer310enclose each quantum circuit device240formed on the circuit wafer210and trenches321(which are recesses with large aspect ratio) of the (top) cap wafer enclose the coupling lines241. Further note that in the case of 2D microwave integrated quantum circuit400, the contours representing the recess walls can be the common footprint of the recesses320of the top cap wafer310and the recesses420of the bottom cap wafer410.

FIG.4Eis a side view of a 3D microwave integrated quantum circuit400M that includes multiple 2D microwave integrated quantum circuits similar to the microwave integrated quantum circuit400. The outermost layers of the 3D microwave integrated quantum circuit400M are the cap wafer310and the second cap wafer410that have been described above in relation toFIGS.3A &4A, respectively. Further, the 3D microwave integrated quantum circuit400M includes multiple circuit wafers210stacked along the z-axis, each of the circuit wafers supporting a plurality of quantum circuit devices240. For instance, quantum circuit devices QC1, QC2, QC3are disposed on a first circuit wafer210, quantum circuit devices QC4, QC5, QC6are disposed on a second circuit wafer210, and so forth. In this manner, a given quantum circuit device240, e.g., QC2, has a particular number of near-neighbor quantum circuit devices disposed on the same circuit wafer210, e.g., some of which are QC1and QC3, and one or two near-neighbor quantum circuit devices disposed on respective one or two adjacent circuit wafers, e.g., QC5. Moreover, each quantum circuit device QC-j240, where j=1, 2, 3, 4, 5, 6, . . . , has an associated operating frequency f0-j. In some implementations, the operating frequencies of adjacent quantum circuit devices240are different from each other. In other implementations, at least some of the adjacent quantum circuit devices240, whether in-plane or out-of-plane, have common operating frequencies.

Note that adjacent instances of the multiple stacked circuit wafers210are separated by another type of cap wafer referred to as a bottom or top cap wafer430. The bottom or top cap wafer430has a first surface that defines recesses420corresponding to the recesses420of the bottom cap wafer410, and a second, opposing surface that defines recesses320corresponding to the recesses320of the top cap wafer310. Here, the recesses420of the bottom or top cap wafer430correspond to the quantum circuit devices240disposed on the circuit wafer210adjacent to the first surface of the bottom or top cap wafer. Similarly, the recesses320of the bottom or top cap wafer430correspond to the quantum circuit devices240disposed on the circuit wafer210adjacent to the second surface of the bottom or top cap wafer. Note that the bottom or top cap wafer430is bonded to each of adjacent circuit wafers210, as described below in relation toFIGS.14A-14B,15and16. In addition, spacers (or standoff bumps) may be used between the bonded bottom or top cap wafer430and each of adjacent circuit wafers210, as described below in relation toFIGS.12,13A-13B,14A-14B,15and16.

Additionally, the 3D microwave integrated quantum circuit400M includes, for each bottom/top cap wafer430, a first electrically conducting layer450that covers at least a portion of each of the recesses420of the bottom/top cap wafer, and a second electrically conducting layer350that covers at least a portion of each of the recesses320of the bottom/top cap wafer. During operation of the 3D microwave integrated quantum circuit400M, all electrically conducting layers350and450are grounded. In some implementations, either or both of the electrically conducting layers350,450may include a multi-layer material stack, such as, for example, the multi-layer material stacks2811,2821described below with respect toFIG.28.

Moreover, each recess420and each recess320of the bottom or top cap wafer430is configured to suppress propagation inside the recess of electromagnetic waves that have frequencies “f” below an associated cutoff frequency fC-j (i.e., f<fC-j), where the associated cutoff frequency fC-j is larger than an operating frequency f0-j (i.e., f0-j<fC-j) of a corresponding quantum circuit device240-j. For example, a recess420of bottom or top cap wafer430corresponding to quantum circuit device QC2is configured to suppress propagation inside the recess of electromagnetic waves that have frequencies “f” below cutoff frequency fC2(i.e., f<fC2), where the cutoff frequency fez is larger than an operating frequency f02(i.e., f02<fC2) of quantum circuit device QC2, while a recess320of the bottom or top cap wafer430corresponding to quantum circuit device QC5is configured to suppress propagation inside the recess of electromagnetic waves that have frequencies “f” below cutoff frequency fC5(i.e., f<fC5) where the cutoff frequency fC5is larger than an operating frequency f05(i.e., f05<fC5) of quantum circuit device QC5. In the latter example, the recess420can have a different size in the x-y plane from the recess320.

As noted above in connection withFIG.2B, another approach to isolate quantum circuit devices240of a microwave integrated quantum circuit uses electrically conducting thru vias. Microwave integrated quantum circuits designed based on this approach are described next.

FIG.5Ais a side view of a 2D microwave integrated quantum circuit500, andFIG.5Bis a top view of the same circuit in the vicinity of one of a plurality of quantum circuit devices240included in the 2D microwave integrated quantum circuit. Here, the 2D microwave integrated quantum circuit300includes a first substrate210, also referred to as a circuit wafer, such that the quantum circuit devices240are disposed on a first surface of the circuit wafer210. Each quantum circuit device QC-j240, where j=1, 2, 3, . . . , has an associated operating frequency f0-j. In some implementations, the operating frequencies of the quantum circuit devices240are different from each other. In other implementations, at least some of the quantum circuit devices240have common operating frequencies.

The 2D microwave integrated quantum circuit500further includes electrically conducting vias560each extending through the circuit wafer210outside of a footprint of each quantum circuit device240. A length of the electrically conducting vias560along the z-axis corresponds to a thickness of the circuit layer210, which can range from 1 μm to 2 mm. Note that the electrically conducting vias560include a material (e.g., Al, In, Ti, Pn, Sn, etc.) that is superconducting at an operating temperature of the 2D microwave integrated quantum circuit500. In this manner, the 2D microwave integrated quantum circuit500can be operated at cryogenic temperatures (e.g., using liquid helium) and the electrically conducting vias560(or at least portions thereof) can operate as superconducting vias at that temperature. In addition, during operation of the 2D microwave integrated quantum circuit500, the electrically conducting vias560are grounded.

Moreover, the electrically conducting vias560are distributed around the footprint of each quantum circuit device240to suppress propagation of electromagnetic waves (also referred to as substrate modes) that have frequencies “f” below a cutoff frequency fC(i.e., f<fC). Such suppression occurs across a volume of the circuit wafer210that is adjacent to the footprint of the quantum circuit device. Here, the cutoff frequency fCis larger than the operating frequency f0(i.e., f0<fC) of the surrounded quantum circuit device. The noted suppression of the propagation of the substrate modes is illustrated inFIG.5Aby the relative appearance of an in-air electric field spatial distribution Eairand an in-substrate electric field spatial distribution Esubof operating signals.

In this manner, a separation S between adjacent electrically conducting vias560is smaller than a maximum separation SMAXcorresponding to the cutoff frequency fC. In general, structures with parallel metal plates support the propagation of parallel-plate or substrate modes. A resonant frequency of these modes depends on the metal plate area: it drops as the area increases.FIG.5Cis a plot501that shows a dependence of the resonant frequency of the first fundamental mode of a square cavity of silicon versus size. Silicon represents one material from which the circuit wafer210can be made. Without being limited by theory or mode of operation, the dependence of the resonant frequency may follow the relationship below:

fq=c2⁢π⁢ϵr⁢(πq)2+(πq)2+(πr)2(6)
where c is the speed of light in free space, ϵris the relative dielectric constant of silicon, and p, q and r are the dimensions of the cavity. Such substrate modes can cause undesired coupling among the quantum circuit devices240of the 2D microwave integrated quantum circuit500, giving rise to a degraded performance of the quantum circuit devices240. Therefore, if substrate modes have frequencies in a bandwidth that includes the operating frequency of the quantum circuit devices240, the electrically conducting vias560may be used to suppress them.

Referring again toFIG.5B, a distance DV between the outer perimeter of the surrounded quantum circuit device240and a nearest electrically conducting via560corresponds to a value of a capacitance between the surrounded quantum circuit device and the nearest electrically conducting via. Moreover, adjacent quantum circuit devices240disposed on the circuit wafer210can be coupled electromagnetically through a coupling line that includes an electrical conductor241extending along the first surface of the circuit wafer over at least a portion of the distance between the adjacent quantum circuit devices. The coupling between the adjacent quantum circuit devices240can be capacitive, inductive, or galvanic. In some implementations, one or more electrically conducting vias560can be distributed along at least a portion of the coupling line to isolate it from interaction to unwanted modes (e.g., environmental modes), as shown inFIG.7A.

It was noted above in connection withFIG.2Bthat yet another approach to isolate quantum circuit devices240of a microwave integrated quantum circuit combines the isolation approach that uses cap wafers, as described relation toFIGS.3-4, with the isolation approach that uses electrically conducting thru vias, as described in relation toFIG.5. The design of microwave integrated quantum circuits based on this combined approach are described next.

FIG.6Ais a side view of a 2D microwave integrated quantum circuit600A that includes electrically conducting vias560, each extending through the circuit wafer210as described in relation toFIGS.5A-5B. The electrically-conducting vias560are in addition to the components of the 2D microwave integrated quantum circuit300described in relation toFIGS.3A-3B. Here, the electrically conducting vias560are disposed outside of a footprint of each recess320encapsulating an associated quantum circuit device240.FIG.6Bis a side view of a 2D microwave integrated quantum circuit600B that includes electrically conducting vias560, each extending through the circuit wafer210as described in relation toFIGS.5A-5B. The electrically conducting vias560are in addition to the components of the 2D microwave integrated quantum circuit400described in relationFIG.4A. Here, the electrically conducting vias560are disposed outside of a common footprint of each recess320encapsulating an associated quantum circuit device, and respective recess420on the other side of the circuit wafer from the encapsulated quantum circuit device.FIG.6Cis a top view of either the 2D microwave integrated quantum circuit600A or the 2D microwave integrated quantum circuit600B in the vicinity of one of a plurality of quantum circuit devices240included therein.

During operation of the 2D microwave integrated quantum circuit600A, the electrically conducting layer350and the electrically conducting vias560are grounded. During operation of the 2D microwave integrated quantum circuit600B, the electrically conducting layers350and450, and the electrically conducting vias560are grounded.

Note that each recess320of the cap wafer310is configured to suppress propagation inside the recess of electromagnetic waves that have frequencies “f” below a cutoff frequency fC, where the cutoff frequency fChas been established based on the separation S of the electrically conducting vias560, as described in relation toFIGS.5A-5B. The noted suppression of the propagation of the recess modes and of the substrate modes is illustrated inFIG.6by the relative appearance of the in-air electric field spatial distribution (i.e., Eair) and in-substrate electric field spatial distribution (i.e., Esub) of operating signals. Moreover, (i) the separation S of the electrically conducting vias560distributed around the footprint of each recess320encapsulating an associated quantum circuit device240, and (ii) the size WW of the recess are both determined by the cutoff frequency fC. As noted above, in the case of the 2D microwave integrated quantum circuit600A, a separation DV between the perimeter of the quantum circuit device240and nearest electrically conducting vias560is larger than or at most equal to a separation DW between the perimeter of the quantum circuit device240and adjacent walls of the recess320of the cap wafer310.

Moreover, adjacent quantum circuit devices240disposed on the circuit wafer210can be coupled electromagnetically through a coupling line that includes an electrical conductor241extending along the first surface of the circuit wafer over at least a portion of the distance between the adjacent quantum circuit devices. The coupling between the adjacent quantum circuit devices240can be capacitive or direct. Note that, as illustrated inFIG.6C, at least a portion of the coupling line is electromagnetically isolated from environmental noise because it is encapsulated by a trench321of the cap wafer310and flanked by electrically conducting vias560disposed outside the trench.

Referring again toFIG.6B, the 2D microwave integrated quantum circuit600B further includes a routing wafer610. Some electrically conducting lines650of the routing wafer610are coupled with signal vias660extending through the cap wafer310to supply control signals to, or retrieve readout signals from, the quantum circuit devices240encapsulated in respective recesses320. The foregoing input-output (I/O) signals can be provided/retrieved through the routing wafer610directly from the signal delivery system106of the quantum computing system100or from quantum circuit devices in adjacent 2D microwave integrated quantum circuit600B that is stacked vertically, e.g., along the z-axis, as shown below inFIG.6F. Other electrically conducting lines650of the routing wafer610are coupled with ground vias560extending through the cap wafer310to provide ground to the electrically conducting layer350(or to the electrically conducting layer450, or the electrically conducting vias560that extend through the circuit wafer210.

In the example illustrated inFIG.6B, the cap wafer310has hollow thru vias or apertures330into the recess320. A capacitive coupling can be formed, through such an aperture330, between a quantum circuit device240encapsulated in a recess320and an I/O signal carrying electrically conducting line650.

FIG.6Dis a top view of either the 2D microwave integrated quantum circuit600A or the 2D microwave integrated quantum circuit600B. Here, it is shown that the 2D microwave integrated quantum circuit600A/600B can be scaled to a large number of quantum circuit devices240that include multiple qubits144, resonators146,148, tunable couplers142, and so forth. Here, distances between adjacent qubits144can range from 0.5 mm to 5 mm, for instance. Note that recesses320of the (top) cap wafer310enclose each quantum circuit device240formed on the circuit wafer and trenches321(which are recesses with a large aspect ratio) of the (top) cap wafer enclose the coupling lines241. Further note that in the case of the 2D microwave integrated quantum circuit600B, the contours representing the recess walls can be the common footprint of the recesses320of the top cap wafer310and the recesses420of the bottom cap wafer410.

Furthermore, a plurality of electrically conducting vias that includes ground vias560and I/O signal delivery vias660(or other types of via electrically conducting vias that will be described below in connection withFIGS.7A-7D) are distributed outside of the footprint of the recesses320for the 2D microwave integrated quantum circuit600A, or the common footprint of the recesses320/420for the 2D microwave integrated quantum circuit600B, and between the qubits144, resonators146,148, tunable couplers142of the circuit wafer210. For example, the electrically conducting vias560adjacent to the footprint of the recesses320/420are grounded, while the electrically conducting vias660further apart from the footprint of the recesses320/420can be vias660that carry signals.

Note that at least some of the electrically-conducting vias560, e.g., the ones that are far from the footprint of the recesses320/420, are used mainly to provide thermalization, e.g., because these electrically-conducting vias serve as a heat sink that reduces heat dissipation to the circuit wafer210. In this manner, the quantum circuit devices240disposed on the thermalized circuit wafer210can experience reduced loss.

FIG.6Eis a side view of a 3D microwave integrated quantum circuit600AM that includes multiple 2D microwave integrated quantum circuits similar to the microwave integrated quantum circuit600A. The outermost layers of the 3D microwave integrated quantum circuit600AM are the cap wafer310and the circuit wafer210that have been described in relation toFIG.3A. Further, the 3D microwave integrated quantum circuit600AM includes one or more substrates260stacked along the z-axis between the cap wafer310and the circuit wafer210, each of the substrates supporting quantum circuit devices240included in the 3D microwave integrated quantum circuit600AM. Note that the substrates260are of a different type than the circuit wafer210and are referred to as circuit/cap wafers260. Each circuit/cap wafer260has a first surface onto which associated quantum circuit devices240are disposed, and a second, opposing surface that defines recesses320the correspond to quantum circuit devices240disposed on another circuit/cap wafer or circuit wafer210adjacent to the second surface of the circuit/cap wafer. Note that the circuit/cap wafer260is bonded to each of two adjacent wafers from among a circuit wafer210, a cap wafer310, or another circuit/cap wafer, as described in relation toFIGS.14A-14B,15and16. In addition, spacers (or standoff bumps) may be used between the bonded circuit/cap wafer260and each of adjacent wafers, as described below in connection withFIGS.12,13A-13B,14A-14B,15and16.

Additionally, the 3D microwave integrated quantum circuit600AM includes, for each circuit/cap wafer260, an electrically-conducting layer350that covers at least a portion of each of the recesses320of the circuit/cap wafer. Further, for each circuit/cap wafer260and for the circuit wafer210, the 3D microwave integrated quantum circuit600AM includes electrically conducting vias560each extending through the circuit/cap wafer and through the circuit wafer. Here, the electrically conducting vias560are disposed outside of a footprint of each recess320encapsulating an associated quantum circuit device240. During operation of the 3D microwave integrated quantum circuit600AM, all electrically conducting layers350and all the electrically conducting vias560are grounded.

Note that each recess320of the cap wafer310and of each of the circuit/cap wafers260is configured to suppress propagation inside the recess of electromagnetic waves that have frequencies “f” below an associated cutoff frequency fC-j (i.e., f<fC-j), where the associated cutoff frequency fC-j is larger than an operating frequency f0-j of a corresponding encapsulated quantum circuit device240-j(i.e., f0-j<fC-j). Moreover, the cutoff frequency fC-j has been established based on a separation S-j of the electrically conducting vias560distributed around the footprint of recess320-jencapsulating the associated quantum circuit device240-j, as described above in connection withFIGS.5A-5B.

For example, a recess320-2of cap wafer310corresponding to quantum circuit device QC2has a width W2and electrically conducting vias560-2extending through the circuit/cap wafer260and surrounding the footprint of recess320-2are separated by a separation S2to suppress propagation inside the recess320-2of electromagnetic waves that have frequencies “f” below cutoff frequency fC2(i.e., f<fC2), where the cutoff frequency fC2is larger than an operating frequency f02of quantum circuit device QC2(i.e., f02<fC2); further, a recess320-5of the circuit/cap wafer260corresponding to quantum circuit device QC5has a width W5and electrically conducting vias560-6extending through the circuit wafer210and surrounding the footprint of recess320-5are separated by a separation S5to suppress propagation inside the recess320-5of electromagnetic waves that have frequencies “f” below cutoff frequency fC5(i.e., f<fC5), where the cutoff frequency fC5is larger than an operating frequency f05of quantum circuit device QC5(i.e., f05<fC5). In this example, the width W2of the recess320-2of cap wafer310can be different from the width W2of the recess320-5of circuit/cap wafer260, and the separation S2of the electrically conducting vias560-2extending through the circuit/cap wafer260and surrounding the footprint of recess320-2can be different from the separation S5of the electrically conducting vias560-5extending through the circuit wafer210and surrounding the footprint of recess320-5.

FIG.6Fis a side view of a 3D microwave integrated quantum circuit600BM that includes multiple 2D microwave integrated quantum circuits like the microwave integrated quantum circuit600B stacked along the z-axis. Note that, as each microwave integrated quantum circuit600B (j), where j=2, . . . ,N, includes a routing wafer610, adjacent microwave integrated quantum circuit600B (j),600B (j+1) interface through such a routing wafer. As such, the quantum circuit devices240from adjacent microwave integrated quantum circuits600B (j),600B (j+1) can be coupled through the routing wafer610disposed between them, e.g., in the example shown inFIG.6Fthrough the routing wafer610of the microwave integrated quantum circuit600B (j+1). For example, the quantum circuit devices240from adjacent microwave integrated quantum circuits600B (j),600B (j+1) can be capacitively coupled through an aperture330in the cap wafer310of the microwave integrated quantum circuit600B (j+1). As another example, the quantum circuit devices240from adjacent microwave integrated quantum circuits600B (j),600B (j+1) can be directly coupled through a I/O signal carrying via660extending through the cap wafer310of the microwave integrated quantum circuit600B (j+1).

Various types of electrically conductive vias will be described next in more detail. Prior to that, note that in addition to the quantum circuit devices240disposed on one of the surfaces (e.g., the top surface) of the circuit wafer210of at least some of the microwave integrated quantum circuits described above, additional electrically-conducting circuits can be disposed on the opposing surface (e.g., the bottom surface) of the circuit wafer, in some implementations.

FIG.7Ais a top view of a portion of the 3D microwave integrated quantum circuit600A, for instance. Note that adjacent qubit circuit devices144are coupled with each other through a coupler circuit device142, where the qubit circuit devices and the coupler circuit device are disposed on a circuit/cap wafer260. Signal vias660extending through the circuit/cap wafer260provide control signals to and retrieve readout signals from a control/readout resonator disposed on another circuit/cap wafer or circuit wafer210(not shown). Coupling lines241, which can be capacitive, inductive, or direct, are used to in-plane couple the qubit circuit devices144with the coupler circuit device142and with the signal vias660.

Note that recesses320of the cap wafer310or of another circuit/cap wafer260encapsulate each of the qubit circuit devices144and coupler circuit device142, while trenches321(which are recesses with a large aspect ratio) of the cap wafer310or of the other circuit/cap wafer enclose the coupling lines241. Also note that electrically conducting vias560extending through the circuit/cap wafer260flank the walls of the recesses320and trenches321. Electrically conducting vias560are spaced apart from each other by a separation S related to a cutoff frequency fCassociated with operating frequencies f0of the qubit circuit devices144and coupler circuit device142, as described in relation toFIGS.5A-5B. In this manner, the electrically conducting vias560are grounded during operation of the 3D microwave integrated quantum circuit600A to isolate, from spurious substrate modes, the qubit circuit devices144and coupler circuit device142encapsulated by the recesses320and the coupling lines241encapsulated by the trenches321.

FIG.7Bis a close-up perspective view of two quantum circuit devices240of the 3D microwave integrated quantum circuit600A, for instance. A first quantum circuit device240, a first coupling line241and a first contact pad762are disposed on the circuit/cap wafer260and are encapsulated by a recess320of the cap wafer310. A second quantum circuit device240, a second coupling line241and a second contact pad762are displaced along the z-axis from the first quantum circuit device240, the first coupling line241and the first contact pad762, are disposed on the circuit wafer210, and are encapsulated by a recess320of the circuit/cap wafer260. Note that in this example, capacitive coupling is established between the first coupling line241and the first contact pad762, and between the second coupling line241and the second contact pad762. However, a direct contact via662extending through the recess320and remaining thickness of the circuit/cap wafer260provides direct contact between the first contact pad762and the second contact pad762.

In the example illustrated inFIG.7B, the vertical distance between the layers of the 3D microwave integrated quantum circuit600A is usually set by fabrication technology and flexibility in designing a desired coupling capacitance between quantum circuit devices240might be limited if the capacitance is to be made between layers, e.g., along the z-axis. Here, the direct contact via662helps with transferring a control signal or a readout signal between layers of the 3D microwave integrated quantum circuit600A, because a planar coupling capacitance could be designed in a more straightforward manner with much more flexibility.

FIG.7Cis a (x-y) cross-section of a circuit wafer210or a circuit/cap wafer260in the vicinity of a signal via660extending through the circuit wafer or the circuit/cap wafer to transfer control signals or readout signals between the sides of the circuit wafer or the circuit/cap wafer. Note that the signal via660is surrounded by electrically conductive vias560that are separated from each other by a spacing S. The spacing S is related to a cutoff frequency fCthat is larger than operating frequencies f0of the signals transferred through the signal via660. The electrically conductive vias560are grounded when signals are being transferred through the signal via660to isolate the transferred signals from spurious substrate modes. A radius R of the path of electrically conductive vias560surrounding the signal via660is related to a capacitance of the arrangement illustrated inFIG.7C.

FIG.7Dis a (x-y) cross-section of a circuit wafer210or a circuit/cap wafer260in the vicinity of a DC pad764. A plurality of direct contact vias662extend through the circuit wafer or the circuit/cap wafer to deliver, to the DC pad764, DC signals from a DC signal source disposed on the opposite side of the circuit wafer or the circuit/cap wafer relative to the DC pad. A DC resistance of the DC connection illustrated inFIG.7Ddecreases when the number of direct contact vias662increases.

Note that the electrically-conductive vias described in relation toFIGS.5,6and7—regardless of their function—are formed from a material (e.g., Al, In, Ti, Pn, Sn, etc.) that is superconducting at an operating temperature of the disclosed microwave integrated quantum circuits. Such a material is referred to as a superconducting material. In this manner, the disclosed microwave integrated quantum circuits can be operated at cryogenic temperatures (e.g., using liquid helium) and the electrically-conducting vias (or at least portions thereof) can operate as superconducting vias at that temperature. In some implementations, each of the disclosed electrically-conductive vias comprises a pair of end caps of the superconducting material, where the end caps are disposed adjacent to the first surface and an opposing surface of the circuit wafer210or circuit/cap wafer260. In some implementations, the disclosed electrically-conductive vias have a hollow structure, e.g., are formed as tubes of superconducting material. In some implementations, the disclosed electrically-conductive vias can be filled with conductive material and coated with a layer of superconducting material. For example, the conductive material (which here means a conductive material that is not superconducting at the operating temperature of the disclosed microwave integrated quantum circuits) can be Au, Cu, Pd, and so forth.

The microwave integrated quantum circuits described in relation toFIGS.3-6can be fabricated by forming their respective components, e.g., from among circuit wafers210, circuit/cap wafers260, cap wafers310,410, bottom/top cap wafers430, or routing wafers610, and then by bonding together their respective components. Various techniques are described for fabricating and assembling the components of the disclosed microwave integrated quantum circuits. At least some of the disclosed fabrication techniques satisfy one or more of the following capabilities: (i) deep etching processes of thick wafers are used that are capable to form the recesses320,420of the circuit/cap wafers260, cap wafers310,410, bottom/top cap wafers430that have a dimension Chof the order of hundreds of microns; (ii) deposition processes are used that are capable of coating superconducting materials (e.g., Al, In, Ti, Pn, Sn, etc.); and (iii) plating processes are used that are capable of filling with a conductor material via holes that are coated with a superconducting material.

A circuit wafer210can include signal delivery circuitry of quantum circuit devices240, e.g., qubits, couplers, and I/O signals, while a routing wafer610can includes couplers and I/O signal paths. Thus, processes for their fabrication can be very similar. An example of such fabrication process can include metal patterning on a substrate, machining via holes and metalizing the via holes. The pattering on the substrate could be through metal etching or lift-off depending on the feature sizes.

FIG.8shows an example of a method800for fabricating either of circuit wafers210or routing wafers610based on etching. At810, a metal layer852is deposited on a substrate816. In some implementations, the substrate can be a high-resistivity silicon wafer. In some implementations, the metal layer includes Al or other material (e.g., In, Ti, Pn, Sn, etc.) that is superconducting at an operating temperature of the disclosed microwave integrated quantum circuits. Here, the Al deposition is performed by either sputtering or e-beam evaporation methods. Note that deposition of a Ti adhesion layer might be needed.

At820, a photoresist layer822is spun on the metal layer852. Additionally, the photoresist layer822can be soft-baked.

At830, the photoresist layer822is patterned for metal features. In some implementations, when higher resolution pattering is required for the circuit wafer210, this operation is performed using E-beam lithography. In other implementations, the photoresist layer822is exposed and developed.

At840, the metal layer852is wet-etched to obtain metal features650. An etch mask used for the wet etch is the patterned photoresist layer822.

At850, the patterned photoresist layer822is stripped to expose the metal features650. Operations810-850can be repeated for depositing additional metal layers or a metal oxide (e.g., Al2O3). At this point, fabrication of a circuit wafer210may be completed. If via holes also are needed in the circuit wafer210or a routing wafer610, the method800continues in the following manner:

At860, another photoresist layer824is spun on the metal layer852on the circuit wafer210.

At870, the photoresist layer824is patterned for vias. In this example, the photoresist layer824is exposed and developed.

At880, the substrate816is thru etched to obtain a via hole330. In some implementations, the via hole330is obtained through wet-etching. In other implementations, the via hole330is obtained through dry etching.

At890, the patterned photoresist layer824is stripped to expose the metal features650.

In some implementations, operations860-890can be replaced with a laser drilling process in the following manner. As a first operation, a protective layer is deposited on sensitive areas of the circuit wafer210or routing wafer610. As a second operation, the via hole330is drilled using a laser. At a third operation, the protective layer is removed from the sensitive areas of the circuit wafer210or routing wafer610.

As noted above, the metal features650on the substrate816could be obtained through a lift-off process as an alternative to operations810-850. Such lift of process can be performed in the following manner: (i) Photoresist is spun, then soft baked; (ii) Either one of an e-beam lithography with a reverse mask, or alternatively, a photoresist development bake can be used to pattern the photoresist; (iii) Al is deposited over the patterned photoresist by either sputtering or e-beam evaporation methods. Note that deposition of a Ti adhesion layer might be needed; and (iv) The patterned photoresist is stripped for lift-off. In this case, Al is lifted-off from areas of the patterned photoresist.

An alternative method to reduce or avoid the possibility of damaging sensitive superconducting circuit components during laser drilling or etching vias is to perform via drilling/etching process in the first step. Depending on the sizes/dimensions of the vias, spinning a uniform layer of photoresist might not be practical in some instances. One solution is to fill the vias with Al or In (or with any superconducting paste) and polish the surface.

Cap wafers310,410, bottom/top cap wafers430, or circuit/cap wafers260can be fabricated from substrates (e.g., wafers) that include one or more of Si, Al2O3, SiO2, Si3N4(or another silicon nitride stoichiometry), SiOx, lithographically defined thick photoresists (such as SU8, etc.) or superconducting metals. Processes that used to fabricate either of cap wafers310,410, bottom/top cap wafers430, or circuit/cap wafers260include (i) micromachining of recesses320,420and trenches321, and (ii) deposition of a superconducting material to at least partially cover the walls and bottom of the micromachined recesses and trenches.

Processes for fabricating either of wafers310,410, bottom/top cap wafers430, or circuit/cap wafers260from thick Si wafers or silicon-on-insulator (SOI) wafers will be described. TABLE 1 lists processes for fabricating either of cap wafers310,410, bottom/top cap wafers430, or circuit/cap wafers260that are described in detail below.

TABLE 1ProcessProcessProcessProcess900110010001150StructuralSiSOISU-8materialProcessWet etchDRIEDRIE orSU-8 exposewet etch& developDescribed in911A1011B-11Cconnection withFIG.PhotoresistHard (SiO2,Soft and thickSoft andN/ASi2N4,thickmetals)Etch depthRequiredRequiredNotN/Acontrol(timing)(timing)requiredWallsAngled/Vertical/EitherVertical/smoothscallopedsmoothCostMediumMediumHighLow

FIG.9shows an implementation of a process900for fabricating either one of cap wafers310/410, bottom/top cap wafers430, or circuit/cap wafers260using wet-etching of Si wafers916. Here, a Si wafer916can be up to 2 mm thick.

At910, a hard mask912is deposited on a Si wafer916. As photoresists do not hold up to wet etchants, the hard mask912can be SiO2, Si3N4(or another silicon nitride stoichiometry) and metals. For example, low pressure chemical vapor deposition (LPCVD) of 1 μm of SiO2is performed in a furnace tube, e.g., Tempress TS 6604 S1 (that can be used to deposit low temperature oxide).

At920, photoresist922is spun on the hard mask912. Then, the photoresist922is soft baked. For example, photoresist S1813can be used to obtain a film of about 1.3 μm thickness. First, photoresist S1813is dispensed at 900 rpm for 5 seconds, then spun at 4000 rpm for 60 seconds. Then, the spun photoresist is soft baked on a hot plate at 115° C. for 60 seconds.

At930, the photoresist922is exposed, developed and hard baked. In this manner, the lateral dimensions (e.g., a width) WW and locations in the (x-y) plane of recesses320are defined at this operation. For example, the soft baked photoresist is exposed with GCA 8500 G-Line (0.35 NA), then developed with MIF-319 developer for 60 seconds. Finally, the developed resist is rinsed with DI water and dried.

Alternative to operations920and930, features of the photoresist922can be laser printed.

At940, the hard mask912is etched. Wet or dry etching can be used depending on the material of the hard mask912. As the hard mask912is about 1 μm thick, the wet etch undercut is not a concern given the tolerances. For example, buffered hydrofluoric acid is used (etch rate for LPCVD SiO2: 120 nm) for 8 minutes and 20 seconds to etch 1 mm of SiO2. The etched SiO2is then rinsed with DI water and dried.

At950, the Si wafer916is wet-etched to form recesses320with a depth Ch. Possible etchants are an aqueous solution of HNO3+HF, a solution of KOH in isopropyl alcohol, an aqueous solution of ethylene diamine and pyrocatechol (EDP), and an aqueous solution of tetramethylammonium hydroxide (TMAH). The recommended etchant for different materials of the masks912are listed in TABLE 2.

TABLE 2OperatingR100Mask materialEtchantTemp (° C.)(μm/min)S = R100/R111SiO2, Si3N4, Au, Cr, Ag,Ethylenediamine1000.4717Cupyrocatechol (EDP)SiO2, Si3N4(etches atKOH/isopropyl501.04002.8 nm/min)alcohol (IPA)SiO2, Si3N4Tetrametylammonium800.637hydroxide(TMAH)

Note that common Si wet etchants are usually anisotropic with an etch rate depending upon orientation to crystalline planes. For instance, for <100>-oriented wafers, KOH selectively etches the <111> crystallographic plane, which results in angled sidewalls) (54.7°). Etch depth must be time-controlled after characterizing the etch rate for the specific etchants conditions (temperature, etc.). Etching is stopped when a depth equal to a dimension Chof a recess320is obtained. For example, a wet process is used based on an available recipe and a desired etch depth. Etch time for a target depth of a recess320is calculated based on etch rate. The etched recess320is then rinsed with de-ionized (DI) water and dried.

At960, the patterned photoresist922and the hard mask912are removed. In this manner, a cap wafer310that has recesses320with a width WW and a depth Chis obtained. For example, the SiO2is removed using HF or BHF. Note that the photoresist922may be removed before operation950, otherwise it lifts off during the wet etching. Finally, the cap wafer310is rinsed with DI water and dried.

FIG.10shows an implementation of another process1000for fabricating either of cap wafers310/410, bottom/top cap wafers430, or circuit/cap wafers260using wet-etching of Si on insulator (SOI) wafers1012. In other implementations, a Si-insulator-Si (SIS) wafer can be used, where an insulator layer is sandwiched between two Si layers. An SOI wafer1012includes an insulator layer1114and a Si layer1116. The insulator layer1114can include one or more of SiO2, Si3N4(or another silicon nitride stoichiometry), Al2O3, etc.

A depth Chof a recess320is given by the thickness (e.g., 0.5 mm-1.5 mm) of the Si layer1016of the SOI wafer1012. The thickness of the Si layer1016is measured between the outer surface1024of the SOI wafer1012and the interface1018between the Si layer and the insulator layer1014. In the example illustrated inFIG.10, the insulator layer1014of the SOI wafer1012is used as an etch stop to avoid difficulties associated with characterization of etch rates. As the insulator layer1014has high selectivity to Si etchants, time-controlled etching is not required for process1000.

At1010, a hard mask912is deposited on the Si layer1016. For example, LPCVD of 1 μm of SiO2is performed in a furnace tube, e.g., Tempress TS 6604 S1 (that can be used to deposit low temperature oxide).

At1020, the hard mask912is patterned to define the lateral dimensions (e.g., a width) WW and locations in the (x,y) plane of the recess320. For example, photoresist S1813can be used to obtain a film of about 1.3 μm thickness. First, photoresist S1813is dispensed at 900 rpm for 5 seconds, then spun at 4000 rpm for 60 seconds. The spun photoresist is soft baked on a hot plate at 115° C. for 60 seconds. The soft baked photoresist is exposed with GCA 8500 G-Line (0.35 NA), and developed with MIF-319 developer for 60 seconds. Finally, the developed resist is rinsed with de-ionized water and dried. Then, the SiO2hard mask912is etched using buffered hydrofluoric acid. The etching of the SiO2hard mask912may take around 8 minutes and 20 seconds, depending on the etch rate and thickness of the SiO2hard mask. Finally, the etched SiO2hard mask912is rinsed with DI water and dried. Note that the photoresist may be removed before operation1030, otherwise it lifts off during the wet etching.

At1030, the Si layer1016is wet etched to obtain the recess320with a depth Chequal to the thickness of the Si layer. One of the wet etch recipes listed in TABLE 2 can be used, although no timing is necessary in this case, as the wet etching of the Si layer1016will stop at the interface1018between the Si layer and the insulator layer1014. The etched recess320is then rinsed with DI water and dried.

At1040, the patterned photoresist and the hard mask912are removed. In this manner, a cap wafer310that has recesses320with a width WW and a depth Chis obtained. For example, the SiO2hard mask912is removed using HF or BHF. Finally, the cap wafer310is rinsed with DI water and dried.

FIG.11Ashows an implementation of another process1100for fabricating either of cap wafers310/410, bottom/top cap wafers430, or circuit/cap wafers260using deep reactive-ion etching (DRIE) of Si wafers916. DRIE is a highly anisotropic etch process used to create deep, steep-sided recesses320and trenches321in Si wafers916, with aspect ratios of 20:1 or more. Here, a Si wafer916can be up to 2 mm thick.

At1110, a mask layer1122is deposited on the Si wafer916. In some implementations, the mask layer1122is a layer of thick photoresist that is spun onto the Si wafer916, and then soft baked. In other implementations, the mask layer1122jcan be a layer of SiO2or Si3N4(or another silicon nitride stoichiometry) which have high selectivity to Si etchants. Note that metal masks are not desirable as they sputter inside the DRIE chamber and result in high surface roughness. For example, a 24 μm thick film of AZ 9260 photoresist can be deposited on the Si wafer916in the following manner: (i) first coat target: 10 μm film thickness: dispense: static or dynamic @ 300 rpm spin: 2400 rpm, 60 seconds; (ii) edge bead removal rinse: 500 rpm, 10 second dry: 1000 rpm, 10 sec; (iii) first soft bake 110° C., 80 second hotplate; (iv) second coat target: 24 μm total film thickness: dispense: static or dynamic @ 300 rpm spin: 2100 rpm, 60 seconds; (v) edge bead removal rinse: 500 rpm, 10 second dry: 1000 rpm, 10 second; and (vi) second soft bake 110° C., 160 second hotplate.

At1120, the mask layer1122is patterned to define the lateral dimensions (e.g., a width) WW and the locations in the (x,y) plane of the recess320. For example, the mask layer1122that is a thick photoresist layer is exposed, developed and hard baked. Here, the 24 μm thick film of soft baked AZ 9260 photoresist is patterned in the following manner: (i) exposure dose (10% bias) 2100 mJ/cm2, broadband stepper; (ii) development AZ® 400K Developer 1:4, 260 second spray dispense temp. 27° C. rinse: 300 rpm, 20 second dry: 4000 rpm, 15 seconds; and (iii) rinse with de-ionized water and dry.

As another example, if the mask layer1122is a layer of SiO2or Si3N4(or another silicon nitride stoichiometry), then photolithography operations described above in connection withFIGS.9and10are used to pattern the layer of SiO2or Si3N4. Moreover, laser printing can be used as an alternative method to operations1110and1120.

At1130, the Si layer1016is etched using DRIE to obtain the recess320with a depth Ch. For example, a Bosch DRIE process can be used. This process contains successive cycles of etching and passivation with the flow of SF6and C4F8gases. C4F8source gas yields a substance similar to Teflon. Scalloped etched walls are common features of DRIE which could be made smooth by lowering the etch rate. Etch depth (e.g., for obtaining the target depth Ch) must be time-controlled after characterizing the etch rate for specific chamber conditions (temperature, pressure, gas content, etc.).

At1140, the patterned photoresist mask layer912is removed. In this manner, a cap wafer310that has recesses320with a width WW and a depth Chis obtained. For example, the 24 μm thick film of hard baked AZ 9260 photoresist is stripped in the following manner: wet photoresist stripper (NMP: 1-Methyl-2-pyrrolidon or DMSO: dimethyl sulfoxide) or dry oxygen plasma. For 20+ μm photoresist film thickness about 15 minutes is sufficient to remove it all. Then, the cap wafer310is rinsed with DI water and dried.

FIG.11Bshows an implementation of another process1150that uses SU-8 as structural material for fabricating either of cap wafers310/410, bottom/top cap wafers430, or circuit/cap wafers260. SU-8 is an epoxy-based, highly viscous, negative photoresist. It can be spun up to a thickness above 1 mm (normally with multiple spinning steps) and still be processed with optical contact lithography methods. SU-8 has been used to fabricate high aspect ratio waveguide structures. By using SU-8, the bulk micromachining process can be performed through exposure and developing the photoresist rather than etching silicon. As a result, the sidewalls of the recesses320are vertical and smooth. In general, cap wafers310do not need to have any specific conditions (thickness, crystal planes, etc.) as it remains intact and serves only as the holder during the process.

At1160, an SU-8 layer1152is spun on a substrate1116. The substrate1116can be a Si wafer, an insulator wafer, a ceramic wafer or a metallic plate. Here, a thickness of the SU-8 layer1152can be equal to or larger than the depth Chof the recess320. The spun SU-8 layer1152is then baked.FIG.11Cis a plot1101that shows dependence of film thickness on the spin speed, for two SU-8 materials.

Referring again toFIG.11B, at1170, the baked SU-8 layer1152is patterned to obtain a recess with lateral dimensions (e.g., a width) WW at a desired location in the (x,y) plane. Here, the baked SU-8 layer1152is first exposed and then developed. A total processing time of operations1160and1170can take about 10 min.

After the cap wafers310/410, bottom/top cap wafers430, or circuit/cap wafers260have been fabricated using either of the fabrication processes900,1000,1100or1150, at least portions of the cap wafers, bottom/top cap wafers, or circuit/cap wafers that include the recesses320/420and trenches321are coated with an electrically conducting layer that is superconducting at operating temperatures of quantum computing systems100. In some implementations, spacers (also referred to as standoff bumps) are formed, on a surface of the cap wafers, bottom/top cap wafers, or circuit/cap wafers, between recesses320/420and trenches321, prior to depositing the electrically conducting layer. The standoff bumps are used to control (i) a spacing between a cap wafer on which they are formed with another wafer to which the cap wafer is bonded, and (ii) forces applied, during the bonding process, to a bonding line between the bonded wafers. In some implementations, indium bumps are deposited on a surface of the cap wafers, bottom/top cap wafers, or circuit/cap wafers, between recesses320/420and trenches321, after depositing the electrically conducting layer. The indium bumps are used to bond a cap wafer on which they are formed with another wafer to which the cap wafer is bonded. In some implementations, the electrically conducting layer includes a multi-layer material stack. For example, the electrically conducting layer may be similar to stack2811or the stack2821described below with respect toFIG.28. In some instances, the electrically conducting layer includes one or more layers of non-superconducting material, but maintains one or more properties of superconductivity (e.g., a zero (0) or near-zero resistance, such as less than one (1) milliohm (mΩ)).

FIG.12shows an implementation of another process1200for fabricating cap wafers, for instance, where a fabricated cap wafer310A has standoff bumps1215, is coated with an electrically conducting layer350, and further has In bumps1284. The process1200has four stages: (i) forming the standoff bumps1215; (ii) forming the recesses320; (iii) coating the electrically conducting layer350; and (iv) forming the In bumps1284.

Stage (i), or forming the standoff bumps1215, includes the following operations: at1202, a SiO2layer1214is thermally grown on a Si wafer916. A thickness of the SiO2layer1214defines the height of the standoff bumps1215.

At1204, a photoresist layer1222is patterned to define the location in the (x-y) plane of the standoff bumps1215. The patterned photoresist layer1222will be used as a mask for etching the SiO2layer1214.

At1206, the SiO2layer1214is etched to form the standoff bumps1215at their desired location in the (x-y) plane. The photoresist layer1222is now stripped and the Si wafer916that supports the standoff bumps1215is cleaned in preparation for the next stage of process1200.

Stage (ii), or forming the recesses320, includes the following operations: at1220, a photoresist layer1222is patterned on the Si wafer916to define the lateral dimensions (e.g., a width) WW and the locations in the (x,y) plane of the recesses320. This operation can be performed in a manner similar to the way operation1120of process1100is performed.

At1240, the Si wafer916is etched using DRIE, and then the photoresist layer1222is removed. In this manner, recesses320with a depth Chare obtained. This operation can be performed in a manner similar to the way operation1130of process1100is performed. The photoresist layer1222is now stripped (in a manner similar to the photoresist stripping1140of process1100), and, hence, the Si wafer916—that supports the standoff bumps1215and has the recesses320—is ready for the next stage of process1200.

Stage (iii), or coating the electrically conducting layer350, includes the following operations: at1250, the electrically conducting layer350is coated on the Si wafer916, over the standoff bumps1215and, at least in part, over the recesses320. For example, a layer of Al having a thickness in the range of 0.1-2 μm is coated using sputter deposition. Sputtering is a non-directional physical vapor deposition (PVD) process which provides the best step/sidewall coverage among all the PVD and chemical vapor deposition (CVD) methods. In this manner, the base and the sidewalls of the recesses320, and the top and the sidewalls of the standoff bumps1215can be effectively covered. To ensure the required thickness on the sidewalls, a layer350that is at least twice as much thicker than required is deposited especially for the cases where sidewalls are vertical. After the deposition, EDX could be used to measure the thickness of the deposited layer350. In some implementations, sub-steps performed at1250can be: (a) oxygen plasma treatment to enhance aluminum adhesion; and (b) sputtering aluminum twice as thick as the minimum required thickness to ensure sidewall coverage. Note that a Ti adhesion layer might be needed. In some implementations, a cold/hot deposition can be used for smoother step coverage. The cold/hot deposition consists of cumulatively depositing two layers of Al at different temperatures to achieve a desired total thickness of the electrically conducting layer350. At this point, the Si wafer916—that supports standoff bumps1215, has recesses320, and is coated with an electrically conducting layer350—is ready for the next stage of process1200.

Stage (iv), or forming the indium bumps1284, includes the following operations: at1260, a negative photoresist layer1224is spun on the electrically conducting layer350. Here, the negative photoresist layer1224is coated in a conformal manner to cover the sidewalls of the recesses320. For this purpose, the negative photoresist layer1224has a thickness of up to 10 μm.

At1270, the negative photoresist layer1224is patterned to define openings1272in the negative photoresist layer that correspond to locations in the (x-y) plane of the indium bumps1284. Note that the indium bumps1284are disposed between the recesses320. Although not shown inFIG.12, but shown inFIGS.14A-14B, the indium bumps1284can be formed based on a pattern that includes channels used to pump out the trapped gas between bumps. This is advantageous because the disclosed microwave integrated quantum circuits will experience low pressure inside dilution refrigerators, and, therefore, trapped gases should be pumped out.

At1280, the indium bumps1284are formed. Before the forming of the indium bumps1284, a Ti adhesion layer1282is formed on the electrically conducting layer350inside the openings1272. Then, the indium bumps1284are evaporated on the Ti adhesion layer1282, such that a height of the In bumps is larger than a total height of the standoff bumps1215coated with the electrically conducting layer350. Once the patterned negative photoresist layer1224has been removed, the cap wafer310A is ready to be bonded to a circuit wafer210as part of any of the microwave integrated quantum circuits described above. Note that the cap wafer310A formed by using process1200has standoff bumps1215, has recesses320of width WW and depth Ch, is coated with an electrically conducting layer350, and further includes indium bumps1284.

As described in relation toFIGS.5&6, electrically conducting vias560,660,662have an important role in isolating quantum circuit devices240from each other and from spurious substrate modes, in reducing thermal noise in microwave integrated quantum circuits, in transferring control signals and readout signals between different quantum circuit devices and/or between the quantum circuit devices and the signal delivery system106.FIGS.13A-13Bshow an example of a process1200for fabricating any of the electrically conducting vias560,660,662extending through any of the cap wafers or circuit wafers described herein.

At1305, a Si wafer916is etched using DRIE to form via holes330(or openings having a high aspect ratio of 20:1 or more, i.e., openings that are deep and narrow, with steep sidewalls. Operation1305includes sub-operations that can be performed in a manner similar to the way the operations860-890of process800are performed, or to the way the operations of process1100are performed.

At1310, a metal layer1312—that is superconducting at an operating temperature of the quantum processor cell102—is deposited. Here, a barrier layer1311, made from Si3N4(or another silicon nitride stoichiometry), is formed using low pressure chemical vapor deposition (LPCVD). In this manner, the barrier layer1311is formed on the Si wafer916to coat the via holes330. Ti is a superconductor with a critical temperature of 300 mK, and, hence, Ti is a metal that is superconducting at the operating temperature (Top<300 mK) of the quantum processor cell102. In this manner, the metal layer1312, made from Ti using LPCVD, is formed on the barrier layer1311to coat the via holes330. As the via holes330that are lined with the Si3N4layer1311and the Ti layer1312will be filled with Cu as part of an upcoming operation of process1300, a Cu seed layer1313is formed next on the Ti layer. Here, the Cu seed layer1313is formed using metal-organic chemical vapor phase deposition (MOCVD).

At1315, a Cu layer1314is plated over the Cu seed layer1313and fills the inside of the via holes330to form blind vias1316. Here, the plating recipe is adjusted to prevent void creation inside the via holes330. Further here, the Si3N4layer1311and Ti layer1312are used to prevent the diffusion of Cu from inside the blind via1316to the Si wafer916.

At1320, layers are removed from the top of the Si wafer916. First, the overburden Cu layer1314is removed using chemical mechanical polishing (CMP). The first CMP is stopped on the Ti layer1312. A post CMP cleaning is performed next, followed by annealing at 400° C. for 1 h or 300° C. for 2 h (to release wafer tension). Second, the Ti layer1312and then the Si2N4layer1311are removed using CMP. Here, an additional layer of thickness 0.5 μm from the Si wafer916is CMP-ed to remove the contamination diffused on the surface of the Si wafer. A surface1306of the Si wafer916is formed in this manner.

At1325, the blind vias1316are capped with Ti caps762to form single-capped vias1326. First, a layer of Ti is formed on the surface1306of the Si wafer916over the blind vias1316; photoresist is spun on the layer of Ti is patterned to define the size of the caps762; then the layer of Ti is wet etched to form the Ti caps762; also, Ti oxide is cleaned from the Ti caps762using reverse sputtering (here, reverse sputtering is a process where an Ar plasma is run with no target, therefore, instead of deposition of material from the target, etching from the substrate happens and the oxide layers on the Ti caps are etched away). Second, an Al layer1328is formed on the surface1306of the Si wafer916over the single-capped vias1326; photoresist spun on the Al layer1328is patterned to define desired Al features (e.g., coupling line, signal lines, etc.); then the Al layer1328is wet etched to form the desired Al features.

At1330, a passivation layer1332is formed on the surface1306of the Si wafer916. The passivation layer1332is chosen to be resistant to the developing and etching chemistries which happen at later stages and to be robust at cryogenic temperatures. For instance, the passivation layer1332can be a polyimide, e.g., PBO (Polybenzoxazoles) or BCB (Benzocyclobutene). The passivation layer1332is patterned to define openings1334over at least some of the single-capped vias1326and the features of the Al layer1328.

At1335, an under-bump metal layer1336inside the openings1334of the passivation layer1332is formed. In this manner, the under-bump metal layer1336is formed on the Ti caps762of the single-capped vias1326and on the features of the Al layer1328. The under-bump metal layer1336can be formed from Ti/Pd or Ti/Pt using sputter deposition. The goal of operation1335is to deposit a metal which is solderable on surfaces of metals that are not solderable. For example, Al is not solderable, so bonding to the features of the Al layer1328would be challenging if the under-bump metal layer1336were not deposited.

At1340, a temporary carrier1342is bonded to the passivation layer1332. As the Si wafer916will be thinned down during an upcoming operation of process1300, the carrier wafer1342will ease future handling of the Si wafer.

At1345, the Si wafer916is thinned down until ends of the single-capped vias1326are revealed and a surface1346is formed. As the thinning down is performed using CMP, the resulting surface1346of the Si wafer916can be smooth.

At1350, the single-capped vias1326are capped at their respective revealed ends with Ti caps762to form double-capped vias1352, referred to simply as capped vias1352. First, CuO is removed from the revealed ends of the single-capped vias1326using reverse sputtering. Second, another layer of Ti is formed on the surface1346of the Si wafer916over the capped vias1352; photoresist spun on the other layer of Ti is patterned to define the size of the caps762; then the other layer of Ti is wet-etched to form the Ti caps762on the surface1346of the Si wafer916. Here, the surface1346is cleaned with Acetone (ultrasonic bath), isopropyl alcohol (ultrasonic bath), dehydration (i.e., vacuum or an N2gas environment for 1 hour), and exposure to an O2plasma. In this manner, the capped vias1352include bulk Cu (which is an electrical conductor but is non-superconducting at operating temperatures) capped with and surrounded by Ti (which is superconducting at operating temperatures). In this manner, the non-superconducting material inside the capped vias1352will not be exposed to electromagnetic fields in the Si wafer916.

At1355, a negative photoresist layer1224is formed on the surface1346of the Si wafer916. The negative photoresist layer1224is then patterned to define openings1356to the surface1346.

At1360, a layer of Ti/Pd is deposited over the patterned negative photoresist layer1224. The patterned negative photoresist layer1224is then lifted-off to form alignment marks1362for e-beam writing on the surface1346of the Si wafer916. Here, the surface1346of the Si wafer916is cleaned.

At1365, a negative photoresist layer1224is formed on the surface1346of the Si wafer916. The negative photoresist layer1224is then patterned to define size and location of Al features to be formed on the surface1346. Ti oxide is removed from the alignment marks1362using reverse sputtering.

At1370, another Al layer1328is formed over the patterned negative photoresist layer1224to cover the alignment marks1362. The patterned negative photoresist layer1224is then lifted-off to form features of the Al layer1328that cover the alignment marks1362.

At1375, the carrier wafer1342is de-bonded from the passivation layer1332. In addition, the Si wafer916is diced into smaller pieces.

At1380, the features of the Al layer1328that cover the alignment marks1362are modified. First, the surface1346of the Si wafer916is cleaned, then aluminum oxide is removed, then negative photoresist is spun and patterned. Second, a double-angle Al evaporation is performed, followed by lift-off to obtained modified features of the Al layer1328that cover the alignment marks1362.

In this manner, the process1300can be used to form pieces of Si wafer916and capped vias1352extending through the Si wafer from a surface1306to the opposing surface1346. Features of an Al layer1328cover alignment marks1362formed on the1346surface. Another Al layer1328has different features on the surface1306. A passivation layer1332is attached to the surface1306of the Si wafer916. An under-bump metal layer1336is disposed inside openings of the passivation layer1332on Ti caps of at least some of the capped vias1352and on at least some of the features of the Al layer1328on the surface1306of the Si wafer916.

As described above, the various types of cap wafers (e.g.,310,410,430,260) are bonded together with various types of circuit wafers (e.g.,210,260) to form 2D microwave integrated quantum circuits (e.g.,300,400,500,600A,600B) or 3D microwave integrated quantum circuits (e.g.,400M,600AM,600BM). The bonding methods described below, that are used to fabricate such microwave integrated quantum circuits, satisfy one or more of the following features. Bonding elements (e.g., bumps, balls, etc.) used by the disclosed bonding processes are superconducting at cryogenic temperatures (˜10 mK) so that the bonding elements do not induce additional loss mechanism to the quantum circuit devices240, which operate at the cryogenic temperature. Temperature is maintained low (e.g., <100° C., preferably <80° C.) during some of the disclosed bonding processes due to the heat sensitivity of Josephson junctions of some of the quantum circuit devices240. For example, force-only bonding (at room temperature) is used in some cases. As another example, Al—Al bonding can be performed at low temperatures if the native grown oxide on the surface of Al pads is removed (by plasma surface treatment, for instance). As yet another example, ductile material, e.g., indium, is preferable because its oxide can be broken by applying pressure and deforming it. Bonding interfaces are not hermetic because the disclosed microwave integrated quantum circuits will experience low pressure inside dilution refrigerators, and, therefore, trapped gases should be pumped out.

FIG.14Ashows an example of a process1400for fabricating a 2D microwave integrated quantum circuit, e.g., like the 2D microwave integrated quantum circuit600A described above in connection withFIG.6A.

At1410, a circuit wafer210and a cap wafer310A are received. Here, the circuit wafer210supports quantum circuit devices240(only one of which is shown inFIG.14A). Note that process1300has been used to fabricate electrically conducting thru vias560and Al features1284of the circuit wafer210. Moreover, process1200has been used to fabricate the cap wafer310A that has recesses320and standoff bumps1215.FIG.14Adepicts only one such cap wafer. However, this depiction is not intended as limiting. Other numbers of cap wafers are possible. The cap wafer310A is coated with an electrically conducting layer350and has indium bumps1284connected to the electrically conducting layer through a Ti adhesion layer1282.

At1420, the circuit wafer210is cold bonded to the cap wafer310A. Here, the bonding is performed using a press1422, in which circuit wafer210can be held fixed while applying pressure to the cap wafer310A against the circuit wafer. The press1422can be part of a dedicated mechanical fixture, or part of an integrated bonding system, e.g., a flip-chip bonder. As described in relation toFIG.12, the height of the indium bumps1284before bonding is larger than the total height of the stand-off bumps1215coated with the electrically conducting layer350. Therefore, a value of the pressure experienced by the indium bumps1284, as they deform when the press1422applies pressure to the cap wafer310A, is controlled by the height of the coated standoff bumps1215. In fact, the deforming pressure is maximum when an air gap is formed between the cap wafer310A and the circuit wafer210that has a gap thickness equal to the height of the coated standoff bumps1215. Additionally, the deformed In bumps1284* are thicker and shorter (e.g., >35% shorter) than the In bumps1284before bonding.

In general, bonding two naturally oxidized metallic layers includes removing or breaking the oxides from both sides to create metal-metal bonds. As such, the pressure applied on the cap wafer310has to exceed a threshold pressure that allows: (i) breakage of the naturally grown indium oxide (e.g., In2O3) to expose barren indium on the deformed In bumps1284*, and (ii) breakage of the naturally grown Al2O3to expose Al on the Al features1328, in order to create metal-metal bonds necessary for bonding. To lower the threshold pressure, in some implementations, the receiving operation1410includes dispersing sharp, edged diamond nanoparticles1412over the indium bumps1284so that the indium oxide layer on the deformed indium oxide bumps1284* and the Al2O3layer on the Al features1328can easily be broken when pressure is applied. Note that the bonding operation1420is performed at temperatures that do not exceed 100° C., e.g., at temperatures less than 80° C.

A process1400M for fabricating a 3D microwave integrated quantum circuit, e.g., like the 3D microwave integrated quantum circuit600A described above in connection withFIG.6Eis described next. The process1400M includes performing the operation1410of the process1400, and performing an appropriate number of iterations of the operation1420of process1400.

At1410M, a circuit wafer210and a cap wafer310A are received as described in connection with the operation1410of the process1400. In addition, at1410M, N circuit/cap wafers260A are received, as illustrated inFIG.14B. Here, the circuit wafer210and the circuit/cap wafers260A each supports quantum circuit devices240(only one of which is shown inFIG.14B). Note that the process1300has been used to fabricate electrically conducting thru vias560and Al features1284of the circuit wafer210and of the circuit/cap wafers260A. Moreover, process1200has been used to fabricate the cap wafer310A and at least portions of the circuit/cap wafers260A, where each of the cap wafer and the circuit/cap wafers that has recesses320(only one of which is shown inFIG.14B) and standoff bumps1215, is coated with an electrically conducting layer350, and further has indium bumps1284connected to the electrically conducting layer through a Ti adhesion layer1282. Note that the N circuit/cap wafers260A are configured such that an area in the (x,y) plane, A(j), of the jth circuit/cap wafer260A(j), where j=1 . . . . N, increases from top to bottom: A(1)<A(2)< . . . <A(N). Moreover, area A(1) of the circuit/cap wafer260A(1) adjacent to the cap wafer310A is smaller than the area in the (x,y) plane of the cap wafer, and area A(N) of the circuit/cap wafer260A(N) adjacent to the circuit wafer210equal to or larger than the area in the (x,y) plane of the circuit wafer.

The iteration of operations1420are performed bottom-to-top, in the following manner. As a first iteration of operation1420, the circuit wafer210is cold bonded to the circuit/cap wafer260A(N) by applying pressure P(N) to the circuit/cap wafer260A(N) against the circuit wafer. Here, a value of the applied pressure is P(N)=F(N)/A(N), where F(N) is the force used to press on the circuit/cap wafer260A(N) over its area A(N).

As a second iteration of operation1420, the circuit/cap wafer260A(N) is cold bonded to the circuit/cap wafer260A(N−1) by applying pressure P(N−1) to the circuit/cap wafer260A(N−1) against the circuit/cap wafer260A(N). Here, a value of the applied pressure is P(N−1)=F(N−1)/A(N−1), where F(N−1) is the force used to press on the circuit/cap wafer260A(N−1) over its area A(N−1). Because A(N−1)<A(N), a smaller force F(N−1)<F(N) is used to press on the circuit/cap wafer260A(N−1) to obtain the same or slightly smaller bonding pressure P(N−1)≤P(N). And so on, in each additional step, the utilized bonding force is smaller than the previous one F(j−1)<F(j), where j=N . . . 1, and thus the bonding of the previous pair is not compromised. In some implementations, the relative magnitude of the force applied for consecutive iterations can be controlled by the relative height of the coated standoff bumps1215, in the following manner. To insure that the condition F(j−1)<F(j) holds, the height H (j−1) of the coated standoff bumps1215for an iteration (j−1) has to be larger than the height H (j) of the coated standoff bumps1215for the previous iteration (j), where j=N . . . 1. In other words, the height of the coated standoff bumps1215decreases top-to-bottom, with the tallest coated standoff bumps1215between the cap wafer310A and the circuit/cap wafer260A(1), and the shortest coated standoff bumps1215between the circuit/cap wafer260A(N) and the circuit wafer210.

As the before last iteration of operation1420, the circuit/cap wafer260A(1) is cold bonded to the circuit/cap wafer260A(2) by applying pressure P(1) to the circuit/cap wafer260A(1) against the circuit/cap wafer260A(2). Here, a value of the applied pressure is P(1)=F(1)/A(1), where F(1) is the force used to press on the circuit/cap wafer260A(1) over its area A(1). Because A(1)<A(2), a smaller force F(1)<F(2) is used to press on the circuit/cap wafer260A(1) to obtain the same or slightly smaller bonding pressure P(1)≤P(2).

As the last iteration of operation1420, the cap wafer310A is cold bonded to the circuit/cap wafer260A(1) by applying pressure P(310A) to the cap wafer310A against the circuit/cap wafer260A(1). Here, a value of the applied pressure is P(310A)=F(310A)/A(310A), where F(310A) is the force used to press on the cap wafer3100A over its area A(310A). Because A(310A)<A(1), a smaller force F(310A)<F(1) is used to press on the cap wafer310A to obtain the same or slightly smaller bonding pressure P(310A)≤P(1).

Here, the number of N circuit/cap wafers260A included in a 3D microwave integrated quantum circuit obtained using process1410M can be N=1, as in the 3D microwave integrated quantum circuit600AM, N=2, 3, 7, 15, 31 or other numbers.

FIG.15shows another example of a process1500for fabricating a 2D microwave integrated quantum circuit, e.g., like the 2D microwave integrated quantum circuit600B described above in connection withFIG.6B.

At1510, a circuit wafer210, a top cap wafer310A and a bottom cap wafer410A are received. Here, the circuit wafer210supports quantum circuit devices240(only one of which is shown inFIG.15). Note that either of the processes800or1300can be used to fabricate via holes330in the circuit wafer210. Moreover, a process similar to process1200has been used to fabricate the cap wafers310A,410A, each of which has recesses320,420(only one of each is shown inFIG.15), is coated with an electrically conducting layer350,450, and further has In balls1286connected to the electrically conducting layer.

As part of the receiving operation1510, surfaces of the top cap wafer310A and the bottom cap wafer410A that are to be bonded can be cleaned using a plasma treatment. These surfaces include surfaces of the In balls1286and areas of the electrically conducting layers350,450adjacent to the In balls.

After the plasma treatment, the following alignments are performed: (i) the top cap wafer310A is aligned relative to the circuit wafer210, such that the In balls1286connected to the top cap wafer register to the top end of the via holes330of the circuit wafer; and (ii) the bottom cap wafer410A is aligned relative to the circuit wafer210, such that the In balls1286connected to the bottom cap wafer register to the bottom end of the via holes330of the circuit wafer.

At1520, the circuit wafer210, the top cap wafer310A and the bottom cap wafer410A are cold bonded together. Here, the bonding is performed using a press1522, in which the top cap wafer310A is pressed against the top surface of the circuit wafer210, and the bottom cap wafer410A is pressed against the bottom surface of the circuit wafer. Ductility of In (Mohs scale: 1.2) enables the In balls1286to deform (and not break) and fill the via holes330when the pressure is applied by the press1522. In this manner, the top cap wafer310, the circuit wafer210and the bottom cap wafer410are bonded together by the In that filled the via holes330to form In vias1560. Note that the bonding operation1520is performed at temperatures that do not exceed 100° C., e.g., at temperatures less than 80° C.

The In vias1560also provide an electrical connection between the electrically conducting layers350,450of the cap wafers310,410. In this manner, it is sufficient to provide a single ground connection to one of the electrically conducting layers350,450, and the other one of the electrically conducting layers450,350will also be grounded through the In vias1560.

FIG.16shows another example of a process1600for fabricating a 2D microwave integrated quantum circuit, e.g., like the 2D microwave integrated quantum circuit600B described above in connection withFIG.6B. Process1600includes the operations of process1400and an alignment step from process1500.

At1610, a circuit wafer210, a top cap wafer310A and a bottom cap wafer410A are received. Here, the circuit wafer210supports quantum circuit devices240(only one of which is shown inFIG.16). Note that process1300can be used to fabricate electrically conducting vias560in the circuit wafer210. Moreover, a process similar to process1200has been used to fabricate the cap wafers310A,410A, each of which has recesses320,420(only one of each is shown inFIG.16), is coated with an electrically conducting layer350,450, and further has solder bumps1288connected to the electrically conducting layer. The solder bumps1288can include a solder alloy, e.g., an In-based solder alloy, such as In/Ga solder, that can be reflowed at low temperature. For example, In/Ga solder has meting temperature ˜16° C.

As part of the receiving operation1610, surfaces of the top cap wafer310A and the bottom cap wafer410A that are to be bonded can be cleaned using a plasma treatment. These surfaces include surfaces of the solder bumps1288and areas of the electrically conducting layers350,450adjacent to the solder bumps.

After the plasma treatment, the following alignments are performed: (i) the top cap wafer310A is aligned relative to the circuit wafer210, such that the solder bumps1288connected to the top cap wafer register to the top end of the electrically conducting vias560of the circuit wafer; and (ii) the bottom cap wafer410A is aligned relative to the circuit wafer210, such that the solder bumps1288connected to the bottom cap wafer register to the bottom end of the electrically conducting vias of the circuit wafer.

At1620, the circuit wafer210, the top cap wafer310A and the bottom cap wafer410A are bonded together by reflowing the solder bumps1288. Here, the bonding is performed using a reflow apparatus1622, to apply pressure and temperature for solder reflow. In this manner, the top cap wafer310, the circuit wafer210and the bottom cap wafer410are bonded together by metal-metal bonds formed between caps of the electrically conducting vias560and the reflowed bumps1288*. Note that the solder reflow operation1520is performed at temperatures that do not exceed 100° C., e.g., at temperatures less than 80° C.

The solder-capped vias (1288*-560-1288*) provide an electrical connection between the electrically conducting layers350,450of the cap wafers310,410. In this manner, it is sufficient to provide a single ground connection to one of the electrically conducting layers350,450, and the other one of the electrically conducting layers450,350will also be grounded through the solder-capped vias (1288*-560-1288*).

In some implementations, a 2D microwave integrated quantum circuit can be fabricated using cap wafers with mating features, such that In or solder bumps, electrically conductive vias are not required for assembling the 2D microwave integrated quantum circuit. An example of such a 2D microwave integrated quantum circuit is shown inFIG.17A.FIG.17is a side view of an example of a 2D microwave integrated quantum circuit1700including a circuit wafer210B, a top cap wafer310B and a bottom cap wafer410B that are arranged and configured like the corresponding components of the 2D microwave integrated quantum circuit400described above in connection withFIGS.4A-4B.

However, the top cap wafer310B has, in addition to structural and functional characteristics of the top cap wafer310, a plurality of mating recesses1744(although only one is shown inFIG.17A) that form a top cap pattern. Further, the bottom cap wafer410B has, in addition to structural and functional characteristics of the bottom cap wafer410, a plurality of mating protrusions1742that form a bottom cap pattern that is a “negative image” of the top cap pattern. Furthermore, the circuit wafer210B has, in addition to structural and functional characteristics of the top circuit wafer210, a plurality of openings1746(although only one is shown inFIG.17A) arranged based on the bottom cap pattern. As such, the circuit wafer210B is disposed over the bottom cap wafer410such that the mating protrusions1742protrude through the openings1746. In this manner, the circuit wafer210B and the bottom cap wafer410B are secured together in the (x,y) plane. Moreover, the top cap wafer310B is disposed over the circuit wafer210B such that the mating recesses1744rest on top of the mating protrusions1742of the bottom cap wafer410B. In this manner, the top cap wafer310B and the circuit wafer210B are secured together in the (x,y) plane.

Note that the mating protrusions1742and mating recesses1744form large contact surface areas which ensure, when compression along the z-axis is maintained on the 2D microwave integrated quantum circuit1700, reliable DC (e.g., ground) and RF(e.g., signal) connections between at least portions of the electrically conducting layer350that coats the top cap wafer310B and of the electrically conducting layer450that coats the bottom cap wafer410B, without the use of solder bumps, In bumps, In vias, etc. In some implementations, cold welding may occur upon compressing the 2D microwave integrated quantum circuit1700, for example, between when surfaces of the electrically conducting layers350,450are covered with In.

FIG.17Bshows a process1702for fabricating the bottom cap wafers410B using wet etching. In some implementations, wafers1012used for this process include an etch stopping layer1018for enhanced control of recess depth.

At1710, a hard mask912(e.g., SiOx, SiN, etc.) is patterned on the wafer1012to define locations in the (x,y) plane of mating protrusions1742and their respective lateral sizes. Then, a soft mask922(e.g., a photoresist layer) is spin-coated on the patterned hard mask912.

At1720, the soft mask922is patterned to define locations in the (x,y) plane of the enclosure-forming recesses420and their width WW.

At1730, the wafer1012is subjected to a first wet etch to form the enclosure-forming recesses420. In other implementations, the first etch used to form the recesses enclosure-forming420can be DRIE. The depth of the first wet etch corresponds to the depth Ch of the recesses enclosure-forming420. Then, the patterned soft mask922is removed.

At1740, the wafer1012is subjected to a second wet etch to form the mating protrusions1742. In other implementations, the second etch used to form the mating protrusions1742can be DRIE. The depth of the second wet etch, which may be controlled using the etch stopping layer1018, corresponds to a height HPof the mating protrusions1742. The height HP of the mating protrusions1742is the sum of the depth Ch of the mating recesses1744and the thickness T of the circuit wafer210, HP=Ch+T. Then, the patterned hard mask912is removed.

At1750, an electrically conducting layer450is coated on the wafer1012over the enclosure-forming recesses420and the mating protrusions1742. Note that the bottom cap wafer410B formed by using process1702has enclosure-forming recesses420of width WW and depth Ch, has mating protrusions1742of height HP, and is coated with an electrically conducting layer450. Moreover, the enclosure-forming recesses420are arranged in accordance with a pattern of the quantum circuit devices240supported on the circuit wafer210B, and the mating protrusions1742are arranged in accordance with a predefined bottom cap pattern.

FIG.17Cshows a process1705for fabricating the top cap wafers310A using wet etching. Process1705can be based on process900described above in connection withFIG.9. Accordingly, Si wafers916can be used for process1705.

At1715, a single hard mask912(e.g., SiOx, SiN, etc.) is patterned on the Si wafer916to define locations in the (x,y) plane of the enclosure-forming recesses320and their width WW, and locations in the (x,y) plane of mating recesses1744and their respective lateral dimensions. Note that the locations in the (x,y) plane of mating recesses1744and their respective lateral dimensions matches the locations in the (x,y) plane of mating protrusions1742and their respective lateral dimensions defined at1710of process1702.

At1725, the Si wafer916is subjected to a wet etch to form the enclosure-forming recesses320and the mating recesses1744. In other implementations, the etch used to form the enclosure-forming recesses320and the mating recesses1744can be DRIE. The depth of the wet etch corresponds to the depth Chof the enclosure-forming recesses320and of the mating recesses1744. Then, the patterned hard mask912is removed.

At1735, an electrically conducting layer350is coated on the Si wafer916over the enclosure-forming recesses320and the mating recesses1744. Note that the top cap wafer310B formed by using process1705has enclosure-forming recesses320of width WW and depth Ch, has mating protrusions1742of depth Ch, and is coated with an electrically conducting layer350. Moreover, the enclosure-forming recesses320are arranged in accordance with the pattern of the quantum circuit devices240supported on the circuit wafer210B, and the mating recesses1744are arranged in accordance with a predefined top cap pattern that matches the bottom cap pattern.

FIG.18is a side view of another example of a 2D microwave integrated quantum circuit1800including a circuit wafer210C, a top cap wafer310C and a bottom cap wafer410C that are arranged and similar to the corresponding components of the 2D microwave integrated quantum circuit400described above in connection withFIGS.4A-4B.

However, although the height Cht of recesses1844of the top cap wafer310C is the same as the height of the recesses of the top cap wafer310, a width of the recesses1844is (WW+2WP). Further, bottom cap wafer410C has a plurality of pairs of mating protrusions1842, each pair corresponding to a quantum circuit device240and defining a recess1845. Each mating protrusion1842has a width WP. Additionally, the recess1845has a depth equal to the sum (Cht+T+Chb), where Tis the thickness of the circuit wafer210C and Chb equals the height of the recesses of the bottom cap wafer410. Here, the recesses1844of the top cap wafer310C and the recesses1845of the bottom cap wafer410C correspond to the quantum circuit device240supported on the circuit wafer210C. Furthermore, the circuit wafer210C has, in addition to structural and functional characteristics of the circuit wafer210, a plurality of openings of width WP through which the mating protrusions1842penetrate as the circuit wafer rests on the bottom cap wafer410C. In this manner, the circuit wafer210C and the bottom cap wafer410C are secured together in the (x,y) plane. Moreover, the top cap wafer310C is disposed over the circuit wafer210C such that the recesses1844rest on top of the mating protrusions1842of the bottom cap wafer410C. In this manner, the top cap wafer310C and the circuit wafer210C are secured together in the (x,y) plane.

Note that the mating protrusions1842and mating recesses1844form large contact surface areas to ensure, when compression along the z-axis is maintained on the 2D microwave integrated quantum circuit1800, reliable DC (e.g., ground) and RF(e.g., signal) connections between at least portions of the electrically conducting layer350that coats the top cap wafer310C and of the electrically conducting layer450that coats the bottom cap wafer410C, without the use of solder bumps, In bumps, In vias, etc. In some implementations, cold welding may occur upon compressing the 2D microwave integrated quantum circuit1800, for example, between when surfaces of the electrically conducting layers350,450are covered with In.

A main distinction between the cap wafers310B,410B of the 2D microwave integrated quantum circuit1700the cap wafers310C,410C of the 2D microwave integrated quantum circuit1800is that the former have mating recesses1744and protrusions1742that are spaced apart from the enclosure-forming recesses320,420, while the latter have mating recesses1844and protrusions1842that help define the enclosure-forming recesses320,420.

The cap wafers310C,410C can be fabricated using any of the processes900,1000,1100and1150described above in connection withFIGS.9,10,11A and11B, respectively.

As discussed previously, in general, quantum computing systems100can include a signal delivery system106to deliver signals between a control system110and a quantum processor cell102. In many implementations, the signal delivery system106includes an interposer for electrically routing signal pads on an exterior surface of a circuit wafer210to cable connectors. For example, referring toFIG.19, a quantum computing apparatus1900includes a quantum circuit device1910attached to an interposer1920. Interposer1920connects quantum circuit device1910to a series of cables1950, which connect the quantum computing apparatus1900to a control system (not shown).

Generally, an interposer is a multi-layer device that includes electrical contacts on one surface that are connected to signal lines that fan out, through the layers, to the electrical connectors, e.g., on the opposing side of the interposer. The electrical contacts on the interposer have the same layout as the contact electrodes on the circuit wafer to that, when attached to the circuit wafer, the interposer provides electrical conduction paths from the cable connectors to the quantum circuit device. By fanning the signal lines out, the interposer facilitates connection of conventional cabling (e.g., RF coaxial cables) to the micro circuitry of the quantum computing device. Generally, the interposer includes at least one electrically insulating substrate layer with through holes (e.g., laser drilled or etched, such as DRIE etched) for the signal lines. Common materials for the substrate layer include silicon, BeO, Al2O3, AlN, quartz, sapphire, and PCB. The signal lines can be formed by coating the via holes with a conductive film (e.g., a normal conductor or superconductor).

Typically, the interposer also includes a conductive film (e.g., a normal conductor or superconductor), often metal (e.g., indium, aluminum, tin), deposited on a surface of the substrate layer. These films can be formed on the substrate layer in a variety of ways, such as by sputtering, evaporation, or electroplating. Typically, the conductive layer is patterned using a conventional patterning technique (e.g., wet etching, dry etching, lift off, laser writing, milling, screen printing, etc.).

In many cases, the interposer includes more than one substrate layers bonded together. For example, the interposer1920depicted inFIG.19includes intermediate layers1930(e.g., one or more layers) and a connectorization layer1940. Intermediate layers1930includes signal lines connecting electrical contacts on the surface of quantum circuit device1910facing interposer1920with connectorization layer1940in addition to circuitry (e.g., integrated circuitry) for performing one or more of a variety of functions, such as amplifying signals, multiplexing or de-multiplexing signals, routing signals, etc.

Connectorization layer1940provides mechanical support for the intermediate layers of interposer1920and includes connectors for cables1950, along with signal lines connecting the cable connectors to the signal lines of intermediate layers1930.

Before turning to exemplary embodiments of interposers, it is noted that a variety of circuit wafer structures may be used to reliably attach the circuit wafer to the interposer. For example, in some embodiments a pattern layer of aluminum can be provided on the lower surface of a circuit wafer for attachment to an interposer. Specifically, referring toFIG.20A, a quantum computing apparatus2000includes a quantum circuit device2010and an interposer2020. The quantum circuit device2010includes a circuit wafer2014, which supports a quantum circuit2012on one surface, and a patterned aluminum layer—depicted as portions2016and2018—on the opposing surface. The patterned aluminum layer provides electrical contacts to signal lines (e.g., through vias) in circuit wafer2014. The patterned aluminum layer can be formed by natively growing a layer of aluminum on the surface of circuit wafer2014and then patterning the layer using conventional lithographic techniques. The interposer2020may then be bonded to the patterned aluminum layer using conventional bonding techniques, such as wire bonding, ball bonding, etc.

Of course, whileFIG.20Adepicts only a single quantum circuit and a pair of aluminum portions, in general the circuit wafer can support numerous quantum circuits and aluminum portions. Moreover, while quantum circuit device2010is depicted with minimal structure, it will be understood that any of the microwave integrated quantum circuits described above can be used.

Other circuit wafer structures for interposer attachment may also be used. For example, referring toFIG.20B, a quantum computing apparatus2000′ includes a quantum circuit device2010′ and interposer2020. Quantum circuit device2010′ includes quantum circuit2012, circuit wafer2014, and portions2016and2018of a patterned aluminum layer. This surface also includes a passivation layer2030and a patterned layer of a solderable metal (e.g., Pt, Au, or Pd) including portions2032and2034. Portion2032is registered and in contact with Al portion2016, providing an electrical contact to signal lines in circuit wafer2014. Similarly, Portion2034is registered and in contact with Al portion2018, providing another electrical contact.

In general, at least one of the layers of the interposer provides a substrate for supporting other layers and/or connectors. The interposer substrate material can be silicon, sapphire, ceramic, printed circuit board (PCB) or other material that is sufficiently mechanically robust and compatible with the other layers, manufacturing techniques, and operational conditions of the quantum computing apparatus.

In general, interposers suitable for a quantum circuit device should include some (e.g., all) of the following attributes. First, the interposer should be compatible with the operational temperature of the quantum computing device, i.e., cryogenic temperatures, such as liquid helium temperature. The interposer should also be sufficiently robust to endure the same thermal cycling as the quantum computing device (e.g., cycling between room temperature and cryogenic temperatures). Thermal robustness may be achieved by forming the interposer from a material that has a similar (e.g., the same) coefficient of thermal expansion as the circuit wafer (e.g., silicon) so that any expansion or contraction of the circuit wafer is matched by the interposer during thermal cycling.

The interposer materials should also have relatively low microwave loss, specifically at the operational frequencies of the quantum circuit device.

The layers forming the interposer should have relatively flat surfaces in order to facilitate accurate registration of features (e.g., electrical contacts) between different layers and/or to the quantum circuit device. Specifically, surfaces should have sufficiently smooth, planar surfaces so that reliable and robust connections can be made between contact electrodes on opposing surfaces. In some embodiments, surfaces can have a Ra value of 5 μm or less (e.g., 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less).

Furthermore, the materials forming the interposer should be compatible with the processes used to form and package the quantum circuit device. For instance, materials should be compatible with conventional integrated circuit forming and packaging techniques, including photolithography, deposition of metal and passivation layers, polishing (e.g., chemical mechanical polishing), and etching (e.g., reactive ion etching) techniques.

Example materials for use in the interposer include silicon, sapphire, ceramics (e.g., alumina, aluminum nitride), printed circuit boards (PCB), Kapton, polyimide, and deposited layers such as SiO2and Si2N4.

Moreover, in addition to forming the interposer from materials that are compatible with the quantum circuit device, compatible layer bonding techniques should also be used. In general, bonding should provide sufficiently robust attachment between layers to maintain good contact between contact electrodes on adjacent surfaces. Typically, bonding will depend on the materials (e.g., metals) being bonded. In many cases, wafer bonding techniques are applied. For example, in some embodiments, bonding can be achieved using indium bumps or indium balls. The indium can be patterned using lift off or screen printing techniques. Indium bonding can be achieved using force-only, low temperature or high temperature bonding.

In certain embodiments, bonding is achieved using solder bumps or solder balls, e.g., patterned using a screen printing process. Such bonding can also be achieved used high temperature or low temperature bonding. Aluminum bonding at high or low temperature can also be used. Alternatively, or additionally, connection of contact electrodes between adjacent surfaces can be enabled by mechanical connections, such as using pins (e.g., pogo pins), fuzz buttons, and/or with tips covered with diamond nanoparticles.

Wire-bonding can also be used. For example, the interposer substrate layer(s) can include one or more physical holes acting as pass-thrus for wire bonds from the interposer to the back surface of the quantum circuit device. In some embodiments, the chip stack of the quantum circuit device is assembled onto a carrier, e.g., a substrate formed from aluminum, molybdenum, copper, etc. The chip stack can be glued onto the carrier using an adhesive material, such as an epoxy, eccosorb, etc. The carrier can provide pressure relief by use of compressible or spring-like material, such as fuzz buttons, copper wool, brass wool, gold wool, etc. The carrier can be mounted on a PCB using, e.g., alignment pins and registration marks. In some embodiments, a back plate forms an electromagnetic closure on the opposite side of the PCB from the chip stack and carrier. For example, lossy microwave material can be integrated into the assembly formed by the chip stack, carrier, and PCB. In some implementations, oxygen-free high thermal conductivity (OFHC) copper can be used.

In general, the signal lines provide electrical connections for DC signals, RF signals, and/or ground connections. In various embodiments, the interposer is composed of PCB that includes multiple layers of metal (e.g., 3-30 metal layers). The PCB can include thru and blind vias between the metal layers. RF signals may be routed on a particular metal layer of the PCB, and wire bonds for RF signals make connections from that metal layer to the back plane of the chip stack. DC or low frequency signals may be routed on a different metal layer from the RF signals. Wire bonds from the DC/LF metal layer may also form connections from that layer to the back plane of the chip stack.

Turning now to specific examples of interposers and referring toFIG.21, a quantum computing apparatus2100includes a quantum circuit device2110and a multilayer interposer2180for connecting the quantum circuit device to cables2170. Quantum circuit device2110is a 3D device composed of multiple, stacked circuit wafers including a first circuit wafer2118and an N-th circuit wafer2120. Each circuit wafer supports a quantum circuit, including quantum circuit2116which is supported by circuit wafer2118and quantum circuit2122supported by circuit wafer2120. A cap wafer2112encloses quantum circuit2116in a cavity2114(which may also be referred to as a pocket or enclosure). While quantum circuit device2110is depicted with minimal structure, it will be understood that any of the microwave quantum integrated circuits described above can be used.

Interposer2180is a multi-layer scalable interposer that includes a routing layer2130, a directional coupling layer2140, a layer2150that includes quantum amplifiers and multiplexers, and a connectorization layer2160having connectors for cables2170. Routing layer2130, directional coupling layer2140, and a layer2150each include integrated circuits for performing the functions associated with that layer. Additional layers with integrated circuitry may be included between layer2150and connectorization layer2160. Each layer may include its own substrate or may be mechanically supported on a substrate of another layer. Suitable substrate materials include silicon, ceramic, sapphire, and PCB.

The layers of interposer2180are bonded together using bonding materials and techniques suitable for the two layers being attached. For example, ball bonding, solder bonding, or spring loaded connections may be used.

In some embodiments, the interposer can include one or more ceramic layers (e.g., alumina or AlN). For example, referring toFIG.22, a quantum computing apparatus2200includes a quantum circuit device2210and an interposer2280including a ceramic layer2240for connecting the quantum circuit device to cables2270.

Quantum circuit device2210is a 3D device composed of multiple, stacked circuit wafers including a first circuit wafer2218and an N-th circuit wafer2220. Each circuit wafer supports a quantum circuit, including quantum circuit2216which is supported by circuit wafer2218and quantum circuit2222supported by circuit wafer2220. A cap wafer2212encloses quantum circuit2216in a cavity2214. While quantum circuit device2210is depicted with minimal structure, it will be understood that any of the microwave integrated quantum circuits described above can be used.

Certain ceramics have coefficients of thermal expansion (CTE's) which are close to the CTE of silicon over temperature ranges spanning from cryogenic temperatures (e.g., liquid Helium temperatures) to room temperature, and are therefore promising candidates for bonding to silicon circuit wafers. For instance, alumina has a CTE of 6-7 ppm/° C. and AlN has a CTE of 4 ppm/° C. while silicon has a CTE of 2.6 ppm/° C. Ceramics such as alumina and AlN have relatively low microwave attenuation. Moreover, ceramic layers can be formed with relatively flat surfaces, e.g., having a Ra of about 1 μm or less.

Ceramic layer2240may be in the form of a thick film having a thickness in a range of about 25-30 mils, for instance.

A variety of methods can be used to form ceramic layer2240. For example, in some implementations, ceramic layer2240is formed using a low temperature co-firing process to form a low temperature co-fired ceramic (LTCC) layer. Typically, LTCC technology involves the production of multilayer circuits from ceramic substrate tapes or sheets. Conductive, dielectric, and/or resistive pastes can be applied on each sheet or tape, and then the sheets/tapes are laminated together and fired in one step. The resulting layer is a hermetic, monolithic structure. A typical LTCC structure has multiple dielectric layers, screen-printed or photo-imaged low-loss conductors, and via holes for interconnecting the multiple layers. Alternatively, thick film processes that involve applying conductive or dielectric pastes on top of a thick ceramic substrate and firing them together can be used. Similar to LTCC, conductors may be screen-printed or photo-imaged to achieve desired feature sizes.

Ceramic layer2240is ball-bonded to circuit wafer2220using solder balls of, e.g., low temperature indium or other low temperature solder alloys. For example, the layers can be bonded together by placing the balls on the top surface of ceramic layer2240and bonding the surface of circuit wafer2220to the balls using a low temperature indium or solder bonding process, forming a permanent bond between the circuit wafer and the ceramic layer.

In addition to ceramic layer2240, interposer2280includes a thinnerposer2250and connectorization layer2260, providing connection to cables2270. Thinnerposer2250includes electrically conducting fuzz button interconnects2252embedded in a dielectric substrate. Thinnerposers offer low signal distortion, robustness, and consistency and are commercially available from Custom Interconnects (Centennial, CO).

In some implementations, interposers can use wire bonding to connect to a circuit wafer. For example, referring toFIG.23, a quantum computing apparatus2300includes a quantum circuit device2310and an interposer2380for connecting, using wire bonds, the quantum circuit device to cables2370. Quantum circuit device2310is a 3D device composed of multiple, stacked circuit wafers including a first circuit wafer2318and an N-th circuit wafer2320. Each circuit wafer supports a quantum circuit, including quantum circuit2316which is supported by circuit wafer2318and quantum circuit2322supported by circuit wafer2320. A cap wafer2312encloses quantum circuit2316in a cavity2314. While quantum circuit device2310is depicted with minimal structure, it will be understood that any of the microwave integrated quantum circuits described above can be used.

Interposer2380is a multi-layer interposer formed from four PCB layers2340, a thinnerposer2350, and a connectorization layer2360for connecting the quantum circuit device to cables2370.

Each PCB layer includes metalized surfaces (e.g.,2341) for bonding and forming signal lines. Vertical metallic interconnects (e.g., via2342) run through the PCB layers in the z-direction, connecting the signal lines through to the lower surface of PCB layers2340. Wires2332bonded at one end to a conducting metal layer on a PCB layer and to an electrode2330on circuit wafer2320connect the signal lines to the quantum computing device2310. Each PCB layer includes an aperture registered with apertures on the other layers and thus providing a through hole for threading the wires and providing access to circuit wafer2320.

Thinnerposer2350includes fuzz buttons registered with electrical contacts on the underside of the PCB layers2340on one side, and registered with electrical contacts connected to cables2370on the other side.

In some implementations, the interposer can include multiple substrate layers of silicon. For example, referring toFIG.24, a quantum computing apparatus2400includes a quantum circuit device2410and an all-silicon interposer2480for connecting, using wire bonds, the quantum circuit device to cables2470. Quantum circuit device2410is a 3D device composed of multiple, stacked circuit wafers including a first circuit wafer2418and an N-th circuit wafer2420. Each circuit wafer supports a quantum circuit, including quantum circuit2416which is supported by circuit wafer2418and quantum circuit2422supported by circuit wafer2420. A cap wafer2412encloses quantum circuit2416in a cavity2414. While quantum circuit device2410is depicted with minimal structure, it will be understood that any of the microwave integrated quantum circuits described above can be used.

Interposer2480includes three stacked silicon layers2440,2445, and2450and a silicon connectorization layer2460. Layer2440includes routing circuitry, layer2445includes directional coupling circuitry, and layer2450includes quantum amplification circuitry and multiplexing circuitry. Additional silicon layers can also be included, e.g., between layer2450and connectorization layer2460. The silicon substrates can be fabricated with standard silicon microfabrication techniques, such as silicon DRIE for vias, metal sputtering, photolithography, etc. Generally, metallization can be any non-magnetic metal, preferably superconducting at the operational temperature of quantum computing apparatus2400.

The silicon layers are bonded together using low temperature wafer bonding using indium bumps or indium balls, discussed above. In order to bond more than two silicon layers using low temperature indium bonding, the bonding may be performed bottom to top, the bottom being connectorization layer2460, and the top being cap wafer2412of quantum circuit device2510. In order to fan out the signal lines, the area of the layers of interposer2480increase as they proceed to connectorization layer2460. By bonding the largest layers first (i.e., those at the bottom of the structure), the bonding utilizing the largest bonding force occurs earlier in the process. Sequentially bonding subsequent smaller layers uses less bonding force, meaning there is less chance that the structure will be comprised during formation as the number of layers increase. This can improve yields. Other advantages of indium bonding multiple silicon layers for form an interposer include CTE match to the quantum circuit device, low microwave loss of the structure, and planarity of the surfaces.

Alternatively, or additionally, indium bonding can also be used to bond silicon layers in the interposer. For example, referring toFIG.25, a quantum computing apparatus2500includes a quantum circuit device2510and an interposer2580having silicon layers bonded using indium for connecting the quantum circuit device to cables2570. Quantum circuit device2510is a 3D device composed of multiple, stacked circuit wafers including a first circuit wafer2518and an N-th circuit wafer2520. Each circuit wafer supports a quantum circuit, including quantum circuit2516which is supported by circuit wafer2518and quantum circuit2522supported by circuit wafer2520. A cap wafer2512encloses quantum circuit2516in a cavity2514. While quantum circuit device2510is depicted with minimal structure, it will be understood that any of the microwave integrated quantum circuits described above can be used.

Interposer2580includes three stacked silicon layers2540,2550, and2560. Additional silicon layers can also be included, e.g., between layers2550and2560. Vias2545are also shown for each of silicon layers2540,2550, and2560. These layers are bonded using aluminum bonding. This involves metallization of each surface of silicon layers2540,2550, and2560with aluminum, patterning the aluminum layer to provide contacts2532, and bonding the contacts of adjacent layers with bonding balls2530.

Interposer2580also includes a thinnerposer2565and a connectorization layer2570, connected to cables2575. Thinnerposer2565includes fuzz buttons registered with corresponding aluminum contacts on silicon layer2560and with cable connectors on connectorization layer2570.

Aluminum metallization can also be used for bonding silicon layers together. For example, referring toFIG.26, a quantum computing apparatus2600includes a quantum circuit device2610and an interposer2680for connecting the quantum circuit device to cables2670. Quantum circuit device2610is a 3D device composed of multiple, stacked circuit wafers including a first circuit wafer2618and an N-th circuit wafer2620. Each circuit wafer supports a quantum circuit, including quantum circuit2616which is supported by circuit wafer2618and quantum circuit2622supported by circuit wafer2620. A cap wafer2612encloses quantum circuit2616in a cavity2614. While quantum circuit device2610is depicted with minimal structure, it will be understood that any of the microwave integrated quantum circuits described above can be used.

Interposer2680includes three stacked silicon layers2640,2640, and2650and a silicon connectorization layer2460. Additional silicon layers can also be included, e.g., between layer2450and connectorization layer2460. Layer2640includes routing circuitry, layer2640includes directional coupling circuitry, and layer2650includes quantum amplification circuitry and multiplexing circuitry. Additional silicon layers may be included, e.g., between layer2650and connectorization layer2660, which connects to cables2670.

Each of the silicon layers includes aluminum metallization on its opposing surfaces, patterned to form electrodes. Aluminum electrodes2632on the top surface of layer2630are registered and bonded with aluminum electrodes2624on the bottom surface of circuit wafer2620. Aluminum electrodes2642on the top surface of layer2640are registered and bonded with aluminum electrodes2634on the bottom surface of layer2630. Similarly, aluminum electrodes2652on the top surface of layer2650are registered and bonded with aluminum electrodes2644on the bottom surface of layer2430. Electrodes2662on the top surface of connectorization layer2660are also shown. These are registered and bonded with corresponding electrodes on the bottom surface of the adjacent silicon layer. In each case, low temperature covalent bonding with ion milling can be used to ensure robust bonding between the aluminum electrodes.

In some embodiments, integrated circuit layers of the interposer can be integrated directly onto a circuit wafer of the quantum computing device. For example, referring toFIG.27, a quantum computing apparatus2700includes a quantum circuit device2710and an interposer2780for connecting the quantum circuit device to cables2770. Quantum circuit device2710is a 3D device composed of multiple, stacked circuit wafers including a first circuit wafer2718and an N-th circuit wafer2720. Each circuit wafer supports a quantum circuit, including quantum circuit2716which is supported by circuit wafer2718and quantum circuit2722supported by circuit wafer2720. A cap wafer2712encloses quantum circuit2716in a cavity2714. While quantum circuit device2710is depicted with minimal structure, it will be understood that any of the microwave integrated quantum circuits described above can be used.

Interposer2780includes a routing circuit layer2730formed on the surface of the lowest (Nth) circuit wafer2720. A direction coupling layer2740is formed on the routing circuit layer2730, and a multiplexing circuit layer2750is formed on the direction coupling layer2740. Passivation layers may be provided between circuit wafer2720and routing circuit layer2730, between routing circuit layer2730and direction coupling layer2740, and/or between direction coupling layer2740and multiplexing circuit layer2750. Suitable materials for passivation layers include silicon oxide, which may be deposited, or organic materials like polyimides, which may be spin coated. Such structures may be formed by sequentially depositing, patterning, and planarizing each layer using conventional semiconductor manufacturing methods. In the above description, numerous specific details have been set forth in order to provide a thorough understanding of the disclosed technologies. In other instances, well known structures, interfaces, and processes have not been shown in detail in order to avoid unnecessarily obscuring the disclosed technologies. However, it will be apparent to one of ordinary skill in the art that those specific details disclosed herein need not be used to practice the disclosed technologies and do not represent a limitation on the scope of the disclosed technologies, except as recited in the claims. It is intended that no part of this specification be construed to effect a disavowal of any part of the full scope of the disclosed technologies. Although certain embodiments of the present disclosure have been described, these embodiments likewise are not intended to limit the full scope of the disclosed technologies.

FIG.28is a schematic diagram of example multi-layer material stacks2811,2821on an example cap wafer2810and circuit wafer2820. In some cases, the stacks2811,2821shown inFIG.28may be formed using one or more of the processes described above. In the example shown, the cap wafer2810has a multi-layer material stack2811disposed on its lower side and the circuit wafer2820has a multi-layer material stack2821disposed on its upper side, such that the stacks2811,2821face each other. In some implementations, the stacks2811,2821include a combination of superconducting material layers and non-superconducting material layers, yet maintain one or more superconducting properties. In some implementations, the stacks2811,2821are bonded together to form a bonded multi-layer material stack that maintains superconducting properties despite including non-superconducting material layers (e.g., through the proximity effect). Once bonded together, current may flow perpendicular to the layers of the bonded stack (in the direction shown inFIG.6) to provide a lossless connection between circuit elements on the cap wafer and circuit elements on the circuit wafer. The stacks2811,2821may be implemented as an electrically conducting layer between wafers in a microwave integrated quantum circuit. For example, one or more of the electrically conducting layers described above (e.g., electrically conducting layers350,450) may be implemented similar to either or both of stacks2811,2821.

In the example shown, the stack2811includes a layer2812of aluminum, a layer2814of molybdenum, a layer2816of titanium, and a layer2818of indium, and the stack2821includes a layer2822of aluminum, a layer2824of titanium, and a layer2826of palladium. In some implementations, the combined thickness of the layers2812,2814is between approximately 0.5-2 μm, and the thickness of the respective layers can be divided in various ways between the two materials. In some instances, such as when the layer2814includes molybdenum, the layer2814may be approximately 200 nm thick. Where the layer2814includes molybdenum, the layer may produce a conductive oxide, which may facilitate superconductivity through proximity effect with non-superconducting layers in the stack. However, in instances where the layer2814includes a non-superconducting material, the layer2814may be less than 60 nm thick (to allow for the stack to still exhibit superconducting properties through the proximity effect, as described below). In some implementations, the thickness of layer616is between 0 nm and 35 nm, such as, for example, 30 nm. In some implementations, the thickness of layer618is between 3 μm and 10 μm, such as, for example approximately 6 μm. In some implementations, the layer2822may have a thickness between approximately 50-300 nm, the layer2824may have a thickness between approximately 2-5 nm, and the layer2824may have a thickness between approximately 30-60 nm. In some implementations, the layer2826may have a thickness between approximately 40-70 nm (thicknesses greater than 40 nm may allow for visibility as an alignment mark, while thicknesses greater than 70 nm may limit the proximity effect).

AlthoughFIG.28depicts the multilayer stack2811of the example cap wafer2810has having four layers and the multilayer stack2821of the circuit wafer as having three layers. This depiction is not intended as limiting. The multilayer stacks2811,2821may have any number of layers provided the number maintains the one or more superconducting properties.

For example, the multilayer stack2811of the cap wafer2810may have four layers formed of, respectively, niobium, an alloy of titanium and tungsten (e.g., TiW), niobium, and an alloy of molybdenum and rhenium. The first layer of niobium may be in contact with the cap wafer2810and the layer of molybdenum and rhenium may be an outer layer of the multilayer stack2811. The layer of titanium and tungsten may be sandwiched between the first and second layers of niobium. The first layer of niobium may act as an adhesion layer for adhesion of the layer of titanium and tungsten to the cap wafer2810. However, the first layer of niobium may suffer from copper inter-diffusion, such as from an underlying through-silicon via (TSV). As such, the first layer of niobium may lose its capability to become superconducting (or become degraded in its ability to superconduct). The layer of titanium and tungsten is present as a diffusion barrier to prevent copper from diffusing further into the second layer of niobium. The second layer of niobium may thus serve as a primary carrier of superconducting electrical current, through which, signals propagate through the cap wafer2810. The layer of molybdenum and rhenium is present as a diffusion barrier to oxygen, preventing the oxidization of the underlying second layer of niobium.

It will be appreciated that the first layer of niobium improves the adhesion of the layer of titanium and tungsten and prevents delamination of that layer. The layer of titanium and tungsten prevents copper diffusion into the superconducting signal carrier layer, i.e., the second layer of niobium, which is critical to signal integrity. The layer of titanium and tungsten is not superconducting, but its thickness is tuned such that superconducting signals can be exchanged between the first and second layers of niobium through the Holm-Meissner proximity effect (and subsequently from the first layer of niobium to copper-containing through-silicon vias). The layer of molybdenum and rhenium, which serves as a passivation layer, adds to the robustness of the multilayer stack2811by preventing the formation of metal oxides and allowing the first and second layers of niobium to survive through high heat processes.

It will be understood that the quantum circuits on the circuit wafer2820are electromagnetically shielded from elements formed from non-superconducting copper (e.g., TSVs). Normal metals such as copper can disrupt a quantum coherence of a superconducting metal used to form and connect the quantum circuits. The second layer of niobium is used for this shielding. As mentioned above, the second layer of niobium is kept substantially copper-free by the layer of titanium and tungsten, which serves as a diffusion barrier. All metal layers (other than copper) are deposited in-situ without breaking vacuum. All metal layers are also patterned in the same lithography step, and subsequently etched in a single dry etch step. This greatly reduces processing times and complexity, and prevents the formation of interfacial metal oxides.

In this example, the multilayer stack2821of the circuit wafer2820may be two layers formed of, respectively, an alloy molybdenum and rhenium and niobium. The layer of niobium may be in contact with the circuit wafer2820and the layer of molybdenum and rhenium may be an outer layer of the multilayer stack2821. In some instances, the alloy of molybdenum and rhenium may have same composition between the multilayer stacks2811,2821. In other instances, the alloy of molybdenum and rhenium have a different composition between the multilayer stacks2811,2821.

In another example, the multilayer stacks2811,2821may each have two layers, one formed of niobium and another formed of an alloy of molybdenum and rhenium. The layers of niobium may be, respectively, in contact with the cap wafer2810and the circuit wafer2820while that layers of molybdenum and rhenium may be outer layers of the multilayer stacks2811,2821. In some instances, the alloy of molybdenum and rhenium may have same composition between the multilayer stacks2811,2821. In other instances, the alloy of molybdenum and rhenium have a different composition between the multilayer stacks2811,2821.

In the example shown, the cap wafer2810and circuit wafer2820are bonded together to form a microwave integrated quantum circuit. In some instances, to bond the wafers2810,2820together, the cap wafer2810and the circuit wafer2820may be bonded together by applying a force to the cap wafer2810as shown inFIG.28until the multi-layer material stack2811meets and bonds with the multi-layer material stack2821on the circuit wafer2820. In some implementations, the force applied may be approximately equivalent to 45 kg. In some instances, the surface area of the layer2818is between approximately 2-11 mm2and the force applied to the cap wafer2810exerts a pressure on the material layer stacks that is between 40-220 MPa. In some implementations, the bonding process takes place at a temperature between approximately 65-70° C., since, in some cases, higher temperatures may cause damages to Josephson junctions formed on the cap wafer2810or circuit wafer2820. In some instances, the bonding process may occur at or near room temperature to reduce or avoid oxidation on the layers of the stacks2811,2821. In such instances, the force applied to the cap wafer2810may be greater than 45 kg to ensure proper bonding between the stacks2811,2821(since lower temperatures may require higher amounts of force to be applied to the cap wafer to deform the materials of stacks2811,2821and bond the wafers).

When bonded together, the stacks2811,2821may form a multi-layer material stack that provides a zero resistance or near-zero resistance conductive path at low temperatures (e.g., cryogenic temperatures). In some cases, although the layer2826is composed of a non-superconducting material (e.g., palladium in the example shown), the bonded stacks2811,2821may still exhibit superconducting properties. For example, the bonded stacks2811,2821may have a resistance that is zero or approximately zero, such as less than 1 mΩ, when subjected to temperatures below the constituent materials' critical temperatures (e.g., at or below 100, 10, or 1 K), depending on the critical temperature of the materials in the bonded stacks). Thus, although the bonded stacks include one or more non-superconducting materials, the bonded stacks may act similar to a stack that contains only superconducting materials. The bonded stack may exhibit such superconducting properties because of the proximity effect, which is the phenomenon where the superconductivity of a superconducting material “extends” into a non-superconducting material (e.g., based on Andreev reflection). With the proximity effect, the superconducting order may decay exponentially as a function of the distance into the non-superconducting material, with a decay constant on the order of tens of nanometers (which may depend on the conductivity of the non-superconducting material). A material such as palladium (or another material that is, like palladium, non-oxidizing and dense enough to be visible as an alignment mark in an electron-beam lithography tool; e.g., gold or platinum) may be chosen for use in the layer2826because it can be deposited using evaporation techniques and is conductive enough to obtain superconductivity through the proximity effect discussed above. In addition, palladium, gold, platinum, or another similar material may be chosen for layer2826because of its oxidation-resistive properties.

Although shown inFIG.28as including particular materials, the multi-layer material stacks2811,2821may include other materials or compounds. For example, a number of different superconducting materials may be used in place of the aluminum of layers2812,2822, such as, for example, niobium, titanium nitride, molybdenum, or vanadium. As another example, palladium, gold, platinum, or alloys such as an alloy of molybdenum and rhenium (which may be more resistant to oxidation than molybdenum) can be used in place of the molybdenum in layer2814. In addition, another type of non-oxidizing material that can be deposited via conformal deposition methods (e.g., sputtering, atomic layer deposition, or chemical vapor deposition) and can be thin enough to maintain a proximity effect may be used in place of the molybdenum in layer2814. As yet another example, platinum or gold may be used in place of the palladium in layer2826. As yet another example, gallium may be used in place of the indium in layer2818. In such instances, because gallium's melting point is approximately 30 degrees Celsius, the bonding process may occur below 30 degrees Celsius (e.g., at or near room temperature). Furthermore, although a number of layers are shown in the stacks2811,2821, fewer or additional material layers than those illustrated may be used.

While this specification contains many details, these should not be understood as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples. Certain features that are described in this specification or shown in the drawings in the context of separate implementations can also be combined. Conversely, various features that are described or shown in the context of a single implementation can also be implemented in multiple embodiments separately or in any suitable subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims.