Patent ID: 12224292

Elements in the drawings are designated by reference numerals listed below.

referencereferencenumeralelementnumeralelement10display panel1216second gateelectrode100array substrate1217interlayerinsulating layer110substrate122second thin filmtransistor120thin film transistor1221second activelayerlayer121first thin film1222second gatetransistorinsulating layer1211first active layer1223third gateelectrode1212first gate insulating1224third gatelayerinsulating layer1212afirst via1225fourth gateelectrode1212bsecond via1226second sourceand drainelectrode layer1212cthird via1226asecond sourceelectrode1212dfourth via1226bsecond drainelectrode1213first source and123planarization layerdrain electrodelayer1213afirst source124light shieldingelectrodemetal layer1213bfirst drain electrode125buffer layer1214first gate electrode200light-emittingdevice1215gap300encapsulatingcomponent

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts are within the scope of the present disclosure. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the disclosure, and are not used to limit the disclosure. In the present disclosure, in the case of no explanation to the contrary, the orientation words used such as “on” and “under” usually refer to upper and lower directions of the device in actual use or working state, and specifically the directions in the drawings; and “inside” and “outside” refers to the outline of the device.

The embodiments of the present disclosure provide an array substrate, a display panel, and a manufacturing method of the array substrate. They will be described in detail in the following. It should be noted that an order of description in the following embodiments is not meant to limit a preferred order of the embodiments.

First, an embodiment of the present disclosure provides an array substrate. As shown inFIGS.1,5, and6, the array substrate100includes a substrate110, and the substrate110is used as a supporting structure in the array substrate100to support other film structures on the array substrate100, thereby maintaining relative stability of the array substrate100. Wherein, the substrate110may be a glass substrate, a hard substrate of other materials, or a flexible substrate, and is not limited herein.

The array substrate100includes a thin film transistor layer120disposed on the substrate110, and the thin film transistor layer120is used as a switch control structure of the array substrate100and is configured to control other functional layer structures disposed on the array substrate100to satisfy different application requirements.

Wherein, the thin film transistor layer120includes a first thin film transistor121, and the first thin film transistor121includes a first active layer1211, a first gate insulating layer1212, and a first source and drain electrode layer1213disposed in a stack on the substrate110. The first gate insulating layer1212is disposed between the first active layer1211and the first source and drain electrode layer1213to separate the first active layer1211from the first source and drain electrode layer1213, thereby being convenient for a design of connecting the first source and drain electrode layer1213to the first active layer1211.

It should be noted that the first active layer1211, the first gate insulating layer1212, and the first source and drain electrode layer1213are disposed in sequence in a direction away from the substrate110, or the first source and drain electrode layer1213, the first gate insulating layer1212, and the first active layer1211are disposed in sequence in the direction away from the substrate110. That is, positions of the first active layer1211and the first source and drain electrode layer1213relative to the substrate110may be exchanged, and a specific setting method can be adjusted according to actual design requirements.

Wherein, the first source and drain electrode layer1213includes a first source electrode1213aand a first drain electrode1213bthat are electrically connected to the first active layer1211. Turning on and off of the first active layer1211that is connected between the first source electrode1213aand the first drain electrode1213bcan be realized by electrically connecting the first source electrode1213aand the first drain electrode1213bto the first active layer1211and adjusting driving voltages of the first source electrode1213aand the first drain electrode1213b, thereby realizing controlling other functional layer structures disposed on the array substrate100.

Optionally, the first thin film transistor121further includes a first gate electrode1214disposed on the first gate insulating layer1212. The first gate electrode1214is used as a switch structure, and the first thin film transistor121can be turned on or off by adjusting a driving voltage of an input terminal of the first gate electrode1214, so the first thin film transistor121can regulate other functional structures.

Wherein, the first gate electrode1214and the first source and drain electrode layer1213are disposed on a same layer. That is, the first gate electrode1214and the first source and drain electrode layer1213belong to a same metal layer, that is, the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bare disposed on the same layer. This structural setting method allows the first gate electrode1214and the first source electrode1213aand the first drain electrode1213bof the first source and drain electrode layer1213can be manufactured at a same time by a same mask during the manufacturing process. Therefore, one mask can be omitted, the manufacturing process of the array substrate100can be simplified, production efficiency of the array substrate100can be improved, and production costs can be reduced.

In the embodiment of the present disclosure, the array substrate100includes the substrate110and the thin film transistor layer120. The thin film transistor layer120includes the first thin film transistor121, and the first thin film transistor121includes the first active layer1211, the first gate insulating layer1212, the first source and drain electrode layer1213, and the first gate electrode1214. Wherein, the first source and drain electrode layer1213includes the first source electrode1213aand the first drain electrode1213belectrically connected to the first active layer1211, and the first gate electrode1214and the first source and drain electrode layer1213are disposed on the same layer. By disposing the first gate electrode1214and the first source and drain electrode layer1213on the same layer, the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bcan be manufactured at the same time by the same mask during the manufacturing process. Therefore, the manufacturing process of the array substrate100can be simplified, the production efficiency of the array substrate100can be improved, and the production costs can be reduced.

Optionally, gaps1215are defined between the first gate electrode1214and the first source electrode1213aand between the first gate electrode1214and the first drain electrode1213b. That is, the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bare disposed at intervals. Therefore, the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bcan prevent mutual interference, thereby affecting normal turning on and off of the first thin film transistor121.

Wherein, the first gate insulating layer1212corresponding to the gaps1215is provided with first vias1212a, thereby ensuring that the first gate electrode1214can be completely separated from the first source electrode1213aand the first drain electrode1213b. Incomplete etching caused by etching accuracy or etching depths during the manufacturing process of the array substrate100, which makes interference occur between the first gate electrode1214and the first source electrode1213aand the first drain electrode1213b, can be prevented, thereby ensuring structural stability of the first thin film transistor121.

Optionally, the array substrate100includes a planarization layer123disposed on the first source and drain electrode layer1213and the first gate electrode1214, and the planarization layer123is filled in the gaps1215among the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213b, and the first vias1212aon the first gate insulating layer1212. By disposing the planarization layer123, a surface of the array substrate100can be flattened to facilitate connection between the array substrate100and subsequent functional layer structures, and electrical insulation between the first gate electrode1214, and the first source electrode1213aand the first drain electrode1213bcan be improved, thereby preventing mutual interference, and improving the structural stability of the first thin film transistor121.

Optionally, the first thin film transistor121further includes a second gate electrode1216and an interlayer insulating layer1217, the second gate electrode1216is disposed on one side of the first active layer1211adjacent to the substrate110, and the interlayer insulating layer1217is disposed between the first active layer1211and the second gate electrode1216. Therefore, the second gate electrode1216and the first active layer1211can be isolated from each other, thereby preventing the second gate electrode1216from directly in contact with the first active layer1211and affecting control of turning on and off of the first thin film transistor121.

Wherein, the second gate electrode1216is disposed on the side of the first active layer1211adjacent to the substrate110, which allows the second gate electrode1216and the first gate electrode1214to form a double-gate structure, and the second gate electrode1216can have an effective static-shielding effect between the first gate electrode1214and the first drain electrode1213b. Therefore, a feedback capacitance between the first gate electrode1214and the first drain electrode1213bis greatly reduced, and carrier mobility of the first thin film transistor121is improved.

In addition, the second gate electrode1216is disposed opposite to the first active layer1211, so the second gate electrode1216can also play a role of a light shielding metal layer124at a same time, which shields ambient light to prevent the ambient light from irradiating on the first active layer1211and affecting a structure of the first active layer1211, so overall structural stability of the first thin film transistor121can be further improved.

It should be noted that the second gate electrode1216may also be disposed on one side of the first active layer1211away from the substrate110. That is, the second gate electrode1216and the first gate electrode1214are disposed on a same side of the first active layer1211, and the second gate electrode1216and the first gate electrode1214can still form the double-gate structure to improve the carrier mobility of the first thin film transistor121. In addition, in order to prevent the ambient light from affecting the structure of the first active layer1211, one light shielding metal layer124may be formed on the substrate110corresponding to the first active layer1211, thereby ensuring the overall structural stability of the first thin film transistor121.

Optionally, the array substrate100includes a second thin film transistor122disposed in parallel with the first thin film transistor121on the substrate110. Diversity of driving control of the array substrate100can be improved by designs of coordination among various thin film transistors, thereby satisfying different control requirements of other functional layer structures disposed on the array substrate100.

Wherein, the second thin film transistor122includes a second active layer1221, the first gate insulating layer1212, and a second source and drain electrode layer1226disposed in a stack on the substrate110. The first gate insulating layer1212is disposed between the second active layer1221and the second source and drain electrode layer1226to separate the second active layer1221from the second source and drain electrode layer1226, thereby being convenient for a design of connecting the second source and drain electrode layer1226to the second active layer1221.

It should be noted that the second active layer1221, the first gate insulating layer1212, and the second source and drain electrode layer1226are disposed in sequence in the direction away from the substrate110, or the second source and drain electrode layer1226, the first gate insulating layer1212, and the second active layer1221are disposed in sequence in the direction away from the substrate110. That is, positions of the second active layer1221and the second source and drain electrode layer1226relative to the substrate110may be exchanged, and a specific setting method can be adjusted according to actual design requirements.

Wherein, the second source and drain electrode layer1226includes a second source electrode1226aand a second drain electrode1226belectrically connected to the second active layer1221. Turning on and off of the second active layer1221that is connected between the second source electrode1226aand the second drain electrode1226bcan be realized by electrically connecting the second source electrode1226aand the second drain electrode1226bto the second active layer1221and adjusting driving voltages of the second source electrode1226aand the second drain electrode1226b, thereby realizing controlling other functional layer structures disposed on the array substrate100.

Optionally, the second source and drain electrode layer1226is disposed on the same layer as the first source and drain electrode layer1213and the first gate electrode1214. That is, the second source and drain electrode layer1226, the first source and drain electrode layer1213, and the first gate electrode1214are disposed on the same layer, that is, the second source electrode1226a, the second drain electrode1226b, the first source electrode1213a, the first drain electrode1213b, and the first gate electrode1214are disposed on the same layer. This structural setting method allows the second source electrode1226a, the second drain electrode1226b, the first source electrode1213a, the first drain electrode1213b, and the first gate electrode1214can be manufactured at the same time by the same mask during the manufacturing process. Therefore, the manufacturing process of the array substrate100can be simplified, the production efficiency can be improved, and the production costs can be reduced.

Optionally, the first gate insulating layer1212corresponding to the first source electrode1213ais defined with a second via1212b, the second via1212bexposes the second active layer1221, and the first source electrode1213ais electrically connected to the second active layer1221by the second via1212b. At a same time, positions of the first gate insulating layer1212corresponding to the first source electrode1213aand the first drain electrode1213bare defined with third vias1212c, and the first source electrode1213aand the first drain electrode1213bare electrically connected to the first active layer1211by the third vias1212c. Positions of the first gate insulating layer1212corresponding to the second source electrode1226aand the second drain electrode1226bare defined with fourth vias1212d, and the second source electrode1226aand the second drain electrode1226bare electrically connected to the second active layer1221by the fourth vias1212d. Therefore, an electrical connection between the first thin film transistor121and the second thin film transistor122can be realized, thereby facilitating coordinated control of other functional layer structures disposed on the array substrate100.

Optionally, the second thin film transistor122includes a third gate electrode1223and a second gate insulating layer1222. Wherein, the third gate electrode1223is disposed corresponding to the second active layer1221, and the second gate insulating layer1222is disposed between the third gate electrode1223and the second active layer1221to separate the third gate electrode1223from the second active layer1221, thereby preventing the third gate electrode1223from directly in contact with the second active layer1221and affecting control of turning on and off of the second thin film transistor122.

In some embodiments, the third gate electrode1223is disposed on one side of the second active layer1221away from the substrate110. By adjusting a driving voltage of an input terminal of the third gate electrode1223, control of conduction or disconnection between the second source electrode1226aand the second drain electrode1226bcan be realized, thereby realizing control of conduction or disconnection of the second thin film transistor122.

Since the third gate electrode1223is disposed on the side of the second active layer1221away from the substrate110, the ambient light may irradiate on the second active layer1221through the substrate110and then affects the structure of the second active layer1221. Therefore, it is necessary to dispose the light shielding metal layer124on the side of the second active layer1221adjacent to the substrate110to prevent the second active layer1221from being irradiated by the ambient light and having structural changes, so structural stability of the second thin film transistor122can be ensured.

In another embodiments, the third gate electrode1223is disposed on the side of the second active layer1221adjacent to the substrate110. At this time, the third gate electrode1223can not only control the conduction or disconnection between the second source electrode1226aand the second drain electrode1226b, but also can play the role of the light shielding metal layer124, thereby protecting the second active layer1221and ensuring the structural stability of the second thin film transistor122.

Optionally, the third gate electrode1223and the second gate electrode1216may be disposed on the same layer, that is, the third gate electrode1223and the second gate electrode1216belong to a same metal layer. This structural setting method allows the third gate electrode1223and the second gate electrode1216can be manufactured at the same time by the same mask during the manufacturing process. Therefore, the manufacturing process of the array substrate100can be simplified, the production efficiency can be improved, and the production costs can be reduced.

In some embodiments, the third gate electrode1223and the first source and drain electrode layer1213may also be disposed on the same layer, that is, the third gate electrode1223, the second source electrode1226a, the second drain electrode1226b, the first source electrode1213a, the first drain electrode1213b, and the first gate electrode1214all belong to the same metal layer. Therefore, the manufacturing process of the array substrate100can be further simplified, the production efficiency can be improved, and the production costs can be reduced.

Optionally, the second thin film transistor122further includes a fourth gate electrode1225and a third gate insulating layer1224, the third gate insulating layer1224is disposed between the third gate electrode1223and the fourth gate electrode1225, and the fourth gate electrode1225is disposed corresponding to the second active layer1221. The second thin film transistor122can form a double-gate structure by disposing the fourth gate electrode1225, thereby improving the carrier mobility of the second thin film transistor122.

Wherein, when the third gate electrode1223and the fourth gate electrode1225are both disposed on the side of the second active layer1221away from the substrate110, it is necessary to dispose the light shielding metal layer124on the side of the second active layer1221adjacent to the substrate110to ensure the structural stability of the second thin film transistor122. When at least one of the third gate electrode1223or the fourth gate electrode1225is disposed on the side of the second active layer1221adjacent to the substrate110, the at least one can play the role of the light shielding metal layer124at the same time, so the disposition of the light shielding metal layer124can be omitted, thereby simplifying overall structure of the array substrate100.

Optionally, in the embodiments, a material of the first active layer1211includes one or more of indium gallium zinc oxide, indium tin oxide, or indium zinc oxide, and a material of the second active layer1221includes low temperature polysilicon. That is, the first thin film transistor121is a metal oxide thin film transistor, and the second thin film transistor122is a low temperature polysilicon (LTPS) thin film transistor.

Wherein, low temperature polysilicon thin film transistors have advantages of high mobility, small sizes, fast charging, and fast switching speeds, so they have good effects when used to drive gate electrodes. Metal oxide thin film transistors have advantages of good uniformity and low leakage currents and may be used to drive display pixels. Therefore, by using the low temperature polysilicon thin film transistors and the metal oxide thin film transistors to form mixed thin film transistor structures, driving currents in gate driving circuits of display devices can be increased, and leakage currents generated when driving the display pixels of the display devices can also be reduced, thereby improving applicability of the array substrate100.

Second, an embodiment of the present disclosure further provides a display panel. The display panel includes the array substrate. A specific structure of the array substrate can refer to the above embodiments. Since the display panel adopts all technical solutions of all the foregoing embodiments, it has at least all the beneficial effects brought about by the technical solutions of the foregoing embodiments, and will not be repeated herein.

FIG.2is a schematic structural diagram of the display panel according to an embodiment of the present disclosure. As shown inFIG.2, the display panel10includes the array substrate100, a light-emitting device200, and an encapsulating component300. Wherein, the light-emitting device200is disposed on the array substrate100, and the encapsulating component300is disposed on the light-emitting device200.

Wherein, the light-emitting device200includes a plurality of light-emitting pixels, the array substrate100includes a plurality of first thin film transistors121and a plurality of second thin film transistors122, and the light-emitting pixels are electrically connected to corresponding first thin film transistors121and second thin film transistors122. By connection designs of the first thin film transistor121and the second thin film transistor122and adjustment of conduction or disconnection of the first thin film transistor121and the second thin film transistor122, controlling of light-emitting methods of the light-emitting pixels can be realized, so different display requirements of the display panel10can be realized, thereby improving the display effect of the display panel10.

It should be noted that the display panel10in the embodiments of the present disclosure has a wide range of applications, including televisions, computers, mobile phones, various display and illuminating display devices such as foldable and rollable display screens, as well as wearable devices such as smart bracelets and smart watches, are all within the scope of the application fields of the display panel10in the embodiment of the present disclosure.

Further, an embodiment of the present disclosure provides a manufacturing method of the array substrate. As shown inFIG.3, the manufacturing method of the array substrate includes following steps.

S100: providing the substrate110. The substrate110is used as a supporting structure in the array substrate100to support other film structures on the array substrate100, thereby maintaining relative stability of the array substrate100. Wherein, the substrate110may be a glass substrate, a hard substrate of other materials, or a flexible substrate, and is not limited herein.

S200: disposing the first active layer1211and the first gate insulating layer1212in sequence on the substrate110.

As shown inFIG.5, after cleaning the substrate110, the first active layer1211is deposited on the substrate110first, and then is etched according to design requirements to form target patterns. The material of the first active layer1211includes one or more of indium gallium zinc oxide, indium tin oxide, or indium zinc oxide, that is, the first active layer1211is a metal oxide semiconductor.

Wherein, a thickness of the first active layer1211is greater than or equal to 400 angstroms, and is less than or equal to 1000 angstroms. If the thickness of the first active layer1211is too small, the carrier mobility of the first active layer1211may be affected, thereby affecting overall performance of the array substrate100. If the thickness of the first active layer1211is overly large, an overall thickness of the array substrate100will be too large, which is not beneficial to a structural design of the array substrate100.

In actual manufacturing processes, the thickness of the first active layer1211may be 400 angstroms, 600 angstroms, 800 angstroms, 1000 angstroms, etc., and a specific thickness thereof can be adjusted according to actual design requirements, which is not specifically limited herein.

After the first active layer1211is formed, the first gate insulating layer1212is needed to form on a surface of the first active layer1211, and the first gate insulating layer1212covers the first active layer1211and the substrate110. On one hand, the first gate insulating layer1212can isolate the first active layer1211to facilitate designs of the connection between subsequent film layers and the first active layer1211. On another hand, the first gate insulating layer1212can planarize the surface of the first active layer1211to facilitate effective production of the subsequent film layers.

A material of the first gate insulating layer1212includes one or more of silicon oxide, silicon nitride, or silicon oxynitride. A thickness of the first gate insulating layer1212is greater than or equal to 1000 angstroms, and is less than or equal to 5000 angstroms, which can ensure the first gate insulating layer1212to have sufficient ability of physical insulation and electrical insulation, and at a same time, can prevent the thickness of the first gate insulating layer1212from being overly large and causing the overall thickness of the array substrate100to be overly large, thereby facilitating overall structural design of the array substrate100.

S300: forming the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bon the first gate insulating layer1212and allowing the first source electrode1213aand the first drain electrode1213bto be electrically connected to the first active layer1211.

As shown inFIG.6, after separating the first active layer1211by the first gate insulating layer1212, it needs to form the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bon the first gate insulating layer1212. Since the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bare all conductive structures, when materials used are the same, the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bmay be made at the same time using the same mask. At this time, the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bare in the same layer, which is beneficial to simplify the manufacturing process of the array substrate100, thereby improving the production efficiency of the array substrate100.

The first active layer1211, the first gate insulating layer1212, the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213btogether form the first thin film transistor121. Since the material of the first active layer1211includes one or more of indium gallium zinc oxide, indium tin oxide, or indium zinc oxide, so the first thin film transistor121is a metal oxide thin film transistor.

It should be noted that during the process of forming the first gate insulating layer1212, by defining the third vias1212con the first gate insulating layer1212corresponding to the first active layer1211, the third vias1212cexpose a part of the first active layer1211, and when the first source electrode1213aand the first drain electrode1213bare formed, the first source electrode1213aand the first drain electrode1213bwill be filled in corresponding third vias1212c, respectively, thereby realizing electrical connections between the first source electrode1213aand the first active layer1211and between the first drain electrode1213band the first active layer1211.

In the embodiments, the manufacturing method of the array substrate100includes the steps of disposing the first active layer1211and the first gate insulating layer1212in sequence on the substrate110, then forming the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bon the first gate insulating layer1212, and then allowing the first source electrode1213aand the first drain electrode1213bto be electrically connected to the first active layer1211. By forming the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bon the first gate insulating layer1212at the same time, the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bare allowed to be in the same layer. Therefore, a mask that is independently used to manufacture the first gate electrode1214can be omitted, thereby simplifying the manufacturing process of the array substrate100, improving the production efficiency, and reducing the production costs.

Optionally, as shown inFIG.4, the step of S200: disposing the first active layer1211and the first gate insulating layer1212in sequence on the substrate110mainly includes following steps.

S210: disposing the second active layer1221and the second gate insulating layer1222in sequence on the substrate110.

After cleaning the substrate110, the second active layer1221is deposited on the substrate110first, and then is etched according to design requirements to form target patterns. The material used for the second active layer1221includes low temperature polysilicon, that is, the second active layer1221is a low temperature polysilicon semiconductor.

After the second active layer1221is formed, the second gate insulating layer1222is needed to form on a surface of the second active layer1221, and the second gate insulating layer1222covers the second active layer1221and the substrate110. On one hand, the second gate insulating layer1222can isolate the second active layer1221to facilitate designs of the connection between subsequent film layers and the second active layer1221. On another hand, the second gate insulating layer1222can planarize the surface of the second active layer1221to facilitate effective production of the subsequent film layers.

A material of the second gate insulating layer1222includes one or more of silicon oxide, silicon nitride, or silicon oxynitride. A thickness of the second gate insulating layer1222is greater than or equal to 1000 angstroms, and is less than or equal to 5000 angstroms, which can ensure the second gate insulating layer1222to have sufficient ability of physical insulation and electrical insulation, and at a same time, can prevent the thickness of the second gate insulating layer1222from being overly large and causing the overall thickness of the array substrate100to be overly large, thereby facilitating overall structural design of the array substrate100.

S220: forming the second gate electrode1216and the third gate electrode1223on the second gate insulating layer1222and allowing the third gate electrode1223to correspond to the second active layer1221.

After forming the second gate insulating layer1222, a metal layer is deposited on the second gate insulating layer1222, and then the metal layer is etched according to design requirements to form the third gate electrode1223on a position corresponding to the second active layer1221, thereby facilitating a structural design of thin film transistor corresponding to the second active layer1221.

While etching the metal layer, the second gate electrode1216is formed on the second gate insulating layer1222. The second gate electrode1216corresponds to another thin film transistor, and a specific disposed position thereof may be adjusted according to disposition requirements of the thin film transistor. Just make sure that the second gate electrode1216and the third gate electrode1223are in the same metal layer, and the second gate electrode1216and the third gate electrode1223can be formed at the same time by the same mask. Therefore, the manufacturing process of the array substrate100can be simplified, the production efficiency can be improved, and the production costs can be reduced.

S230: disposing the interlayer insulating layer1217on the second gate electrode1216and the third gate electrode1223.

After patterning and etching to form the second gate electrode1216and the third gate electrode1223, the interlayer insulating layer1217is needed to be deposited on the second gate electrode1216and the third gate electrode1223, and the interlayer insulating layer1217covers the second gate electrode1216, the third gate electrode1223, and the second gate insulating layer1222. On one hand, the interlayer insulating layer1217can separate the second gate electrode1216from the third gate electrode1223to facilitate designs of the connection among subsequent film layers, the second gate electrode1216, and the third gate electrode1223. On another hand, the interlayer insulating layer1217can planarize the surface of the second gate electrode1216and the third gate electrode1223to facilitate effective production of the subsequent film layers.

A material of the interlayer insulating layer1217includes one or more of silicon oxide, silicon nitride, or silicon oxynitride. A thickness of the interlayer insulating layer1217is greater than or equal to 1000 angstroms, and is less than or equal to 5000 angstroms, which can ensure the interlayer insulating layer1217to have sufficient ability of physical insulation and electrical insulation, and at a same time, can prevent the thickness of the interlayer insulating layer1217from being overly large and causing the overall thickness of the array substrate100to be overly large, thereby facilitating overall structural design of the array substrate100.

S240: forming the first active layer1211on the interlayer insulating layer1217corresponding to the second gate electrode1216.

After forming the interlayer insulating layer1217, the first active layer1211is deposited on the interlayer insulating layer1217and then is etched to form target patterns, and the first active layer1211is allowed to correspond to the second gate electrode1216. Wherein, the first active layer1211and the second gate electrode1216correspond to a same thin film transistor, and the first active layer1211and the second gate electrode1216are disposed corresponding to each other, which is beneficial to the structural design of the thin film transistor.

S250: disposing the first gate insulating layer1212on the first active layer1211.

After patterning to form the first active layer1211, the first gate insulating layer1212is needed to form on the surface of the first active layer1211to allow the first gate insulating layer1212to cover the first active layer1211and the interlayer insulating layer1217. On one hand, the first gate insulating layer1212can isolate the first active layer1211to facilitate designs of the connection between subsequent film layers and the first active layer1211. On another hand, the first gate insulating layer1212can planarize the surface of the first active layer1211to facilitate effective production of the subsequent film layers.

Optionally, the step S300of forming the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bon the first gate insulating layer1212includes a following step:

forming the first gate electrode1214, the first source electrode1213a, the first drain electrode1213b, a second source electrode1226a, and a second drain electrode1226bon the first gate insulating layer1212, allowing the first source electrode1213aand the first drain electrode1213bto be electrically connected to the first active layer1211, and allowing the first source electrode1213a, the second source electrode1226a, and the second drain electrode1226bto be electrically connected to the second active layer1221.

Wherein, the second active layer1221, the second gate insulating layer1222, the third gate electrode1223, the first gate insulating layer1212, the second source electrode1226a, and the second drain electrode1226bform the second thin film transistor122. Since the material of the second active layer1221includes low temperature polysilicon, so the second thin film transistor122is a low temperature polysilicon thin film transistor.

It should be noted that during the process of forming the first gate insulating layer1212, by defining the third vias1212con the first gate insulating layer1212corresponding to the first active layer1211, the third vias1212cexpose a part of the first active layer1211, thereby facilitating electrical connections between the first source electrode1213aand the first active layer1211and between the first drain electrode1213band the first active layer1211. The first gate insulating layer1212corresponding to the second active layer1221is etched to form the fourth vias1212d, the fourth vias1212dexpose a part of the second active layer1221, thereby facilitating electrical connections between the second source electrode1226aand the second active layer1221and between the second drain electrode1226band the second active layer1221.

In addition, the first gate insulating layer1212corresponding to the second active layer1221is further etched to form the second via1212b, and the first source electrode1213ais electrically connected to the second active layer1221by the second via1212b. That is, the first source electrode1213ais electrically connected to the first active layer1211and the second active layer1221at the same time, thereby realizing the electrical connection between the first thin film transistor121and the second thin film transistor122and facilitating coordinated control of other functional layer structures disposed on the array substrate100.

Specifically, when forming the first gate electrode1214, the first source electrode1213a, the first drain electrode1213b, the second source electrode1226a, and the second drain electrode1226bon the first gate insulating layer1212, a metal layer is deposited on the first gate insulating layer1212first, and then the metal layer is etched according to requirements of target pattern designs to form the first gate electrode1214, the first source electrode1213a, the first drain electrode1213b, the second source electrode1226a, and the second drain electrode1226bon the first gate insulating layer1212at the same time. Therefore, unnecessary photomask processes can be omitted, the manufacturing process of the array substrate100can be simplified, and the production efficiency can be improved.

Since the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213bbelong to the first thin film transistor121and they are located relatively close to each other, in order to ensure that the first gate electrode1214is completely separated from the first source electrode1213aand the first drain electrode1213b, when the metal layer is etched at the same time that the gaps1215are formed among the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213b, the first gate insulating layer1212corresponding to the gaps1215will be further etched to form the first vias1212a, thereby ensuring that the first gate electrode1214is completely separated from the first source electrode1213aand the first drain electrode1213b. Incomplete etching caused by etching accuracy or etching depths during the manufacturing process of the array substrate100, which makes interference occur between the first gate electrode1214and the first source electrode1213aand the first drain electrode1213b, can be prevented, thereby ensuring structural stability of the first thin film transistor121.

Optionally, the manufacturing method of the array substrate100in the embodiment further includes a following step: disposing the planarization layer123on the first gate electrode1214, the first source electrode1213a, the first drain electrode1213b, the second source electrode1226a, and the second drain electrode1226b. The planarization layer123covers the first gate insulating layer1212and fills the gaps1215among the first gate electrode1214, the first source electrode1213a, and the first drain electrode1213b, and the first vias1212aon the first gate insulating layer1212. By disposing the planarization layer123, a surface of the array substrate100can be flattened to facilitate connection between the array substrate100and subsequent functional layer structures, and electrical insulation between the first gate electrode1214, and the first source electrode1213aand the first drain electrode1213bcan be improved, thereby preventing mutual interference, and improving the structural stability of the first thin film transistor121.

Optionally, during the manufacturing process of the array substrate100, in order to improve the structural stability of the array substrate100, after cleaning the substrate110, the light shielding metal layer124is directly disposed on the surface of the substrate110, and then the buffer layer125is disposed on the light shielding metal layer124.

A disposed position of the light shielding metal layer124may be adjusted according to a target disposed position of corresponding thin film transistor, and it is only necessary to make the light shielding metal layer124correspond to corresponding first active layer1211and second active layer1221. Disposing the light shielding metal layer124on the substrate110can prevent the ambient light from irradiating on the first active layer1211and the second active layer1221through the substrate110, thereby ensuring structural stability of the first active layer1211and the second active layer1221.

The disposition of the buffer layer125can separate the light shielding metal layer124from the subsequent film layers, thereby preventing mutual interference. At the same time, the buffer layer125can also planarize the surface of the light shielding metal layer124to facilitate effective formation of the subsequent film layers.

It should be noted that in the manufacturing process of the array substrate100, each metal film layer in the embodiment of the present disclosure, which includes the first gate electrode1214, the second gate electrode1216, the first source electrode1213a, and the first drain electrode1213bof the first thin film transistor121and the third gate electrode1223, the fourth gate electrode1225, the second source electrode1226a, and the second drain electrode1226bof the second thin film transistor122, can cooperate with each other to be manufactured by a same layer production method under the premise that the manufacturing process is feasible. Therefore, a maximum number of masks can be omitted, the manufacturing process of the array substrate100can be simplified, and the production efficiency can be improved.

Both the first thin film transistor121and the second thin film transistor122may be a bottom gate structure or a top gate structure. According to design requirements of actual structures, positions of corresponding gate electrodes may be adjusted. When relative positions of the first gate electrode1214, second gate electrode1216, third gate electrode1223, and fourth gate electrode1225are changed, corresponding manufacturing processes can also be changed accordingly, and gate electrode structures disposed in the same layer by a same mask can also be changed accordingly. It only needs to ensure that under the premise that structure design requirements of the array substrate100are satisfied, the number of masks can be omitted, the manufacturing process of the array substrate100can be simplified, the production efficiency of the array substrate100can be improved, and the production costs can be reduced.

The array substrate, the display panel, and the manufacturing method of the array substrate provided by the embodiments of the present disclosure are described in detail above. Specific examples are used herein to explain the principles and implementation of the present disclosure. The descriptions of the above embodiments are only used to help understand the method of the present disclosure and its core ideas; meanwhile, for those skilled in the art, the range of specific implementation and application may be changed according to the ideas of the present disclosure. In summary, the content of the specification should not be construed as causing limitations to the present disclosure.