Patent ID: 12261095

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Various embodiments provide packaged semiconductor devices having improved heat dissipation and methods of forming the same. The method includes forming an interconnect structure, forming a via over the interconnect structure, and attaching a semiconductor die to the interconnect structure. An insulation layer is formed over the interconnect structure, the via, and the semiconductor die and a molding compound is formed over the insulation layer. The insulation layer may be electrically insulating and may isolate the via and any exposed conductive features of the interconnect structure and the semiconductor die from one another. This allows electrically conductive materials to be used for the molding compound. The insulation layer may also reduce stress between the molding compound and underlying structures, which allows for materials having higher thermal expansion coefficients to be used for the molding compound. The greater flexibility in the choices of materials for the molding compound allows for materials with higher thermal conductivities to be used for the molding compound. This, in turn, provides better heat dissipation, improves device quality, improves device performance, and reduces device defects.

FIG.1illustrates a cross-sectional view of an integrated circuit die50. The integrated circuit die50will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die50may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SoC), an application processor (AP), a microcontroller, an application-specific integrated circuit (ASIC) die, or the like), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM) die, or the like), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die or the like), a front-end die (e.g., an analog front-end (AFE) die), the like, or a combination thereof.

The integrated circuit die50may be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit die50may be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit die50includes a semiconductor substrate52, such as silicon, doped or un-doped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate52may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate52has an active surface (e.g., the surface facing upwards inFIG.1), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards inFIG.1), sometimes called a backside.

Devices54(represented by a transistor) may be formed at the active surface of the semiconductor substrate52. The devices54may be active devices (e.g., transistors, diodes, or the like), capacitors, resistors, or the like. An inter-layer dielectric (ILD)56is over the active surface of the semiconductor substrate52. The ILD56surrounds and may cover the devices54. The ILD56may include one or more dielectric layers formed of materials such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), un-doped silicate glass (USG), or the like.

Conductive plugs58extend through the ILD56to electrically and physically couple the devices54. For example, when the devices54are transistors, the conductive plugs58may couple the gates and source/drain regions of the transistors. The conductive plugs58may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structure60is over the ILD56and conductive plugs58. The interconnect structure60interconnects the devices54to form an integrated circuit. The interconnect structure60may be formed by, for example, metallization patterns in dielectric layers on the ILD56. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of the interconnect structure60are electrically coupled to the devices54by the conductive plugs58.

The integrated circuit die50further includes pads62, such as aluminum pads, to which external connections are made. The pads62are on the active side of the integrated circuit die50, such as in and/or on the interconnect structure60. One or more passivation films64are on the integrated circuit die50, such as on portions of the interconnect structure60and the pads62. Openings extend through the passivation films64to the pads62. Die connectors66, such as conductive pillars (for example, formed of a metal such as copper), extend through the openings in the passivation films64and are physically and electrically coupled to respective ones of the pads62. The die connectors66may be formed by, for example, plating, or the like. The die connectors66electrically couple the respective integrated circuits of the integrated circuit die50.

Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on the pads62. The solder balls may be used to perform chip probe (CP) testing on the integrated circuit die50. CP testing may be performed on the integrated circuit die50to ascertain whether the integrated circuit die50is a known good die (KGD). Thus, only integrated circuit dies50, which are KGDs, undergo subsequent processing and are packaged, and dies, which fail the CP testing, are not packaged. After testing, the solder regions may be removed in subsequent processing steps.

A dielectric layer68may (or may not) be on the active side of the integrated circuit die50, such as on the passivation films64and the die connectors66. The dielectric layer68laterally encapsulates the die connectors66, and the dielectric layer68is laterally coterminous with the integrated circuit die50. Initially, the dielectric layer68may bury the die connectors66, such that the topmost surface of the dielectric layer68is above the topmost surfaces of the die connectors66. In some embodiments where solder regions are disposed on the die connectors66, the dielectric layer68may bury the solder regions as well. Alternatively, the solder regions may be removed prior to forming the dielectric layer68.

The dielectric layer68may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, phosphosilicate glass (PSG), boro-silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; the like, or a combination thereof. The dielectric layer68may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors66are exposed through the dielectric layer68during formation of the integrated circuit die50. In some embodiments, the die connectors66remain buried and are exposed during a subsequent process for packaging the integrated circuit die50. Exposing the die connectors66may remove any solder regions that may be present on the die connectors66.

In some embodiments, the integrated circuit die50is a stacked device that includes multiple semiconductor substrates52. For example, the integrated circuit die50may be a memory device such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like that includes multiple memory dies. In such embodiments, the integrated circuit die50includes multiple semiconductor substrates52interconnected by through-substrate vias (TSVs) (also referred to as through-silicon vias). Each of the semiconductor substrates52may (or may not) have an interconnect structure60.

FIGS.2through25illustrate cross-sectional views of manufacturing an integrated circuit package with improved heat dissipation, in accordance with some embodiments. InFIG.2, a carrier substrate102is provided, and a release layer104is formed on the carrier substrate102. The carrier substrate102may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate102may be a wafer, such that multiple packages can be formed on the carrier substrate102simultaneously. In some embodiments, one or more of the integrated circuit dies50may be packaged to form an integrated circuit package in each of a plurality of package regions over the wafer. The completed integrated circuit packages may also be referred to as integrated fan-out (InFO) packages.

The release layer104may be formed of a polymer-based material, which may be removed along with the carrier substrate102from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer104is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In some embodiments, the release layer104may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer104may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate102, or the like. The top surface of the release layer104may be leveled and may have a high degree of planarity.

InFIG.3, a front-side redistribution structure124is formed on the release layer104. The front-side redistribution structure124includes dielectric layers106,110,114, and118; and metallization patterns108,112,116, and120(including conductive pads120A and120B). The metallization patterns108,112,116, and120may also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure124illustrated inFIG.3includes four dielectric layers and four layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure124. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed below may be repeated.

The front-side redistribution structure124may be formed by depositing the dielectric layer106on the release layer104. In some embodiments, the dielectric layer106may be formed of a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer106may be formed by spin coating, lamination, CVD, the like, or a combination thereof.

The metallization pattern108is formed on the dielectric layer106. The metallization pattern108may be formed by forming a seed layer (not separately illustrated) over the dielectric layer106. The seed layer may be a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be deposited by physical vapor deposition (PVD) or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern108. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating (e.g., electroplating or electroless plating) or the like. The conductive material may comprise a metal, such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the metallization pattern108. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed by an acceptable etching process, such as wet or dry etching.

The dielectric layer110is deposited on the metallization pattern108and the dielectric layer106. The dielectric layer110may be formed of materials and in a manner the same as or similar to the dielectric layer106. Openings may be patterned through the dielectric layer110to expose the underlying metallization pattern108. The openings may be patterned through the dielectric layer110by an acceptable process. In embodiments in which the dielectric layer110comprises a photosensitive material, the dielectric layer110may be exposed to a patterned energy source (e.g., a patterned light source) and developed to form the openings extending through the dielectric layer110. In some embodiments, a patterned mask may be formed over the dielectric layer110and the dielectric layer110may be patterned through the patterned mask using an etching process, such as an anisotropic etch, to form the openings extending through the dielectric layer110.

The metallization pattern112is formed on the dielectric layer110and the metallization pattern108. The metallization pattern112includes portions on and extending along a top surface of the dielectric layer110(e.g., conductive lines) and portions extending through the dielectric layer110(e.g., conductive vias). The portions of the metallization pattern112extending through the dielectric layer110may be electrically coupled to and physically contact the metallization pattern108. The metallization pattern112may be formed of materials and in a manner the same as or similar to the metallization pattern108. In some embodiments, the metallization pattern112has a different size from the metallization pattern108. For example, the conductive lines and/or the conductive vias of the metallization pattern112may be wider or thicker than the conductive lines of the metallization pattern108. Further, the metallization pattern112may be formed to a greater pitch than the metallization pattern108.

The dielectric layer114is deposited on the metallization pattern112and the dielectric layer110. The dielectric layer114may be patterned to expose the metallization pattern112. The dielectric layer114may be formed of materials, and formed and patterned in a manner the same as or similar to the dielectric layer110.

The metallization pattern116is formed on the dielectric layer114and the metallization pattern112. The metallization pattern116includes portions on and extending along a top surface of the dielectric layer114(e.g., conductive lines) and portions extending through the dielectric layer114(e.g., conductive vias). The portions of the metallization pattern116extending through the dielectric layer114may be electrically coupled to and physically contact the metallization pattern112. The metallization pattern116may be formed of materials and in a manner the same as or similar to the metallization pattern108. In some embodiments, the metallization pattern116has a different size from the metallization pattern108and the metallization pattern112. For example, the conductive lines and/or the conductive vias of the metallization pattern116may be wider or thicker than the conductive lines and/or the conductive vias of the metallization pattern108and the metallization pattern112. Further, the metallization pattern116may be formed to a greater pitch than the metallization pattern108and the metallization pattern112.

The dielectric layer118is deposited on the metallization pattern116and the dielectric layer114. The dielectric layer118may be patterned to form openings exposing the metallization pattern116. The dielectric layer118may be formed of materials, and formed and patterned in a manner the same as or similar to the dielectric layer110.

The metallization pattern120is formed in the openings extending through the dielectric layer118. In some embodiments, the metallization pattern120may be formed on the dielectric layer118and the metallization pattern116. The metallization pattern120may be formed of materials and in a manner the same as or similar to the metallization pattern108. After the metallization pattern120is formed, a planarization process may be performed on the metallization pattern120to level top surfaces of the metallization pattern120with top surfaces of the dielectric layer118. The planarization process may be a chemical-mechanical polish (CMP), a grinding process, or the like. The metallization pattern120may include conductive pads120A, on which vias (such as the vias126, discussed below with respect toFIG.4) may be subsequently formed, and conductive pads120B, to which conductive connectors (such as the conductive connectors128, discussed below with respect toFIG.5) may be subsequently bonded.

InFIG.4, vias126(also referred to as through-mold interconnects (TMIs)) are formed on the conductive pads120A of the metallization pattern120. The vias126may extend away from the topmost dielectric layer of the front-side redistribution structure124(e.g., the dielectric layer118). As an example to form the vias126, a seed layer (not separately illustrated) is formed over the front-side redistribution structure124, e.g., on the dielectric layer118and the metallization pattern120. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. In some embodiments, such as embodiments where the vias126are the same width as or narrower than the underlying conductive pads120A, a separate seed layer may be omitted, and the conductive pads120A may act as the seed layer.

A photoresist is formed and patterned on the seed layer (if present) and the front-side redistribution structure124. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to vias126. The patterning forms openings through the photoresist to expose the seed layer or the conductive pads120A. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer (if present) are removed using an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the vias126.

In some embodiments, wire bond structures may be used in place of the vias126. For example, a wire bond structure (not separately illustrated) may be formed on each of the conductive pads120A. Each of the wire bond structures may include a bond ball formed on the respective conductive pad120A and a metal wire attached to the respective bond ball.

InFIG.5, two integrated circuit dies50are bonded in the illustrated package region. AlthoughFIG.5illustrates two integrated circuit dies50bonded in the illustrated package region, any number of the integrated circuit dies50may be bonded in each of a plurality of package regions on a wafer. InFIG.5, the integrated circuit dies50are disposed face down such that the front sides of the integrated circuit dies50face the conductive pads120B, and the back sides of the integrated circuit dies50face away from the conductive pads120B. The integrated circuit dies50are bonded to the conductive pads120B through conductive connectors128. The conductive connectors128are formed over the conductive pads120B. The conductive connectors128may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors128may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors128are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the layer of solder has been formed, a reflow may be performed in order to shape the material into the desired bump shapes. In some embodiments, the conductive connectors128comprise metal pillars (such as copper pillars), which may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof. The metal cap layer may be formed by a plating process.

InFIG.6, an underfill130is formed between the integrated circuit dies50and the front-side redistribution structure124. The underfill130may surround the conductive connectors128. The underfill130may be formed by a capillary flow process after the integrated circuit dies50are attached, or may be formed by a suitable deposition method before the integrated circuit dies50are attached. In some embodiments, the underfill130may be formed of a polymer material, and may increase the bonding strength of the integrated circuit dies50to the front-side redistribution structure124.

InFIG.7, an insulation layer132is formed over the vias126, the integrated circuit dies50, the underfill130, and the front-side redistribution structure124, and an encapsulant134is formed over the insulation layer132. The insulation layer132may be a conformal layer. In some embodiments, the insulation layer132may be deposited by CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), PVD, sputtering, spin coating, thermal spraying, or the like. The insulation layer132may be formed of an electrically insulating material. In some embodiments, the insulation layer132may be formed of a material having a high thermal conductivity, such as a thermal conductivity greater than about 10 W/m·K. In the embodiments in which the insulation layer132is formed of a high-thermal conductivity material, the insulation layer132may comprise aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond, aluminum oxide (Al2O3), magnesium oxide (MgO), combinations or multiple layers thereof, or the like. In some embodiments, the insulation layer132may be formed of a material having a relatively low thermal conductivity, such as a thermal conductivity of less than about 10 W/m·K, a thermal conductivity ranging from about 1 W/m·K to about 10 W/m·K, or the like. In the embodiments in which the insulation layer132is formed of a relatively low-thermal conductivity material, the insulation layer132may comprise silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiONx), combinations or multiple layers thereof, or the like. In some embodiments, the insulation layer132may comprise a polymer material. The insulation layer132may have a thermal conductivity ranging from about 1 W/m·K to about 100 W/m·K, an electrical conductivity ranging from about ranging from about 107Ω·cm to about 1014Ω·cm, and a coefficient of thermal expansion (CTE) ranging from about 0.1 ppm/° C. to about 10 ppm/° C.

The encapsulant134is then formed over the insulation layer132. The encapsulant134may be a molding compound, an epoxy, or the like. In some embodiments, the encapsulant134may include a mixture of epichlorohydrin with any of bisphenol-A (BPA), bisphenol A diglycidyl ether (DGEBA), bisphenol-F (BPF), phenols, thiols, anhydrides, amines, aliphatic alcohols, fillers, combinations thereof, or the like. The encapsulant134may be applied by compression molding, transfer molding, or the like, and may be formed such that the through vias126and/or the integrated circuit dies50are buried or covered. The encapsulant134may be applied in a liquid or semi-liquid form and subsequently cured.

The encapsulant134may be formed of high-thermal conductivity materials, which improves heat dissipation through the encapsulant134. For example, in some embodiments, the encapsulant134may be formed of a mix of epoxy and conductive fillers, which may comprise graphite, graphene, carbon nanotubes, conductive particles (e.g., copper (Cu), silicon (Si), silver (Ag), gold (Au), iron (Fe), tungsten (W), combinations thereof, or the like), combinations thereof, or the like. In some embodiments, the graphite fillers may include flakes having a size less than 1 μm. The graphene fillers may be single-layer or multi-layer and may include flakes having a size less than 10 μm. The carbon nanotube fillers may be single-wall or multi-wall and may include sizes less than 50 μm. The conductive fillers may have a thermal conductivity ranging from about 10 W/m·K to about 1,000 W/m·K, an electrical conductivity ranging from about ranging from about 10−3Ω·cm to about 1014Ω·cm, and a coefficient of thermal expansion (CTE) ranging from about 1 ppm/° C. to about 10 ppm/° C. The encapsulant134may include the conductive fillers at a concentration ranging from about 5% to about 95% by volume. In some embodiments, the encapsulant134may include the conductive fillers at a concentration ranging from about 70% to about 95% by volume, a concentration ranging from about 5% to about 40% by volume, or a concentration ranging from about 30% to about 70% by volume. Including the conductive fillers in the prescribed ranges of concentrations may improve heat dissipation through the encapsulant134. In some embodiments, the encapsulant134may further include non-conductive fillers, such as AlN, diamond, BN, BeO, magnesium oxide (MgO), Al2O3, SiO2, silicon (Si), silicon nitride (SiNx), combinations thereof, or the like.

The encapsulant134may have a thermal conductivity greater than the thermal conductivity of the insulation layer132. In some embodiments, the encapsulant134may have a thermal conductivity of greater than about 40 W/m·K; a thermal conductivity ranging from about 40 W/m·K to about 100 W/m·K, from about 5 W/m·K to about 200 W/m·K, or from about 100 W/m·K to about 200 W/m·K; or the like. The encapsulant134may have an electrical conductivity ranging from about ranging from about 10−3Ω·cm to about 1014Ω·cm and a coefficient of thermal expansion (CTE) ranging from about 0.1 ppm/° C. to about 20 ppm/° C.

Forming the insulation layer132over the vias126, the integrated circuit dies50, and the front-side redistribution structure124allows for greater flexibility in the choice of materials for the encapsulant134. For example, providing the insulation layer132formed of an electrically insulating material prevents shorts between the vias126, the integrated circuit dies50, and the front-side redistribution structure124, even when the encapsulant134is formed of an electrically conductive material. The insulation layer132provides a buffer layer between the encapsulant134and each of the vias126, the integrated circuit dies50, and the front-side redistribution structure124, which reduces stress. This allows for the encapsulant134to be formed of materials having higher thermal expansion coefficients. The greater flexibility in the choice of materials for the encapsulant134allows for materials having high thermal conductivities to be used for the encapsulant134, which improves heat dissipation from the integrated circuit dies50. This improves device performance and reduces device defects.

The insulation layer132may have a thickness t, ranging from about 10 nm to about 100 nm. Forming the insulation layer132to a thickness less than the prescribed range may cause difficulties in the formation of the insulation layer132and may be insufficient for providing the benefits of the insulation layer132(e.g., providing electrical isolation between the vias126, the integrated circuit dies50, and the front-side redistribution structure124and providing a buffer layer between the encapsulant134and the underlying structures). Further, the insulation layer132may be formed of a material having a lower thermal conductivity than the material of the encapsulant134. Forming the insulation layer132to a thickness greater than the prescribed range lowers the combined thermal conductivity of the insulation layer132and the encapsulant134.

InFIG.8, a planarization process is performed on the encapsulant134and the insulation layer132. As illustrated inFIG.9, the planarization process may expose the vias126. The vias126pass through the insulation layer132and the encapsulant134, and may be subsequently referred to as through vias126. In some embodiments, at least a portion of the insulation layer132may remain on back sides of the integrated circuit dies50. In some embodiments, portions of the encapsulant134may also remain over the back sides of the integrated circuit dies50, or the encapsulant134and the insulation layer132may be planarized such that the back sides of the integrated circuit dies50are exposed. The planarization process may also remove material of the through vias126. Top surfaces of the through vias126, the insulation layer132, and the encapsulant134may be level with one another following the planarization process (e.g., within process variations). In some embodiments, the planarization process may be a CMP, a grinding process, or the like.

InFIG.9, a backside redistribution structure144is formed on the encapsulant134, the through vias126, and the insulation layer132. The backside redistribution structure144includes a dielectric layer138and metallization patterns136and140. The metallization patterns136and140may also be referred to as redistribution layers or redistribution lines. The backside redistribution structure144illustrated inFIG.9includes one dielectric layer and two layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the backside redistribution structure144. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed below may be repeated.

The backside redistribution structure144may be formed by forming the metallization pattern136on the encapsulant134, the insulation layer132, and the through vias126. The metallization pattern136may be formed of materials and in a manner the same as or similar to the metallization pattern108. After the metallization pattern136is formed and patterned, the metallization pattern136may include portions extending along top surfaces of the encapsulant134, the insulation layer132, and the through vias126. The metallization pattern136may be electrically coupled the through vias126.

The dielectric layer138is deposited on the metallization pattern136, the encapsulant134, the insulation layer132, and the through vias126. The dielectric layer138may be formed of materials and in a manner the same as or similar to the dielectric layer106. Openings may be patterned through the dielectric layer138to expose the underlying metallization pattern136. The openings may be patterned through the dielectric layer138by an acceptable process. In embodiments in which the dielectric layer138comprises a photosensitive material, the dielectric layer138may be exposed to a patterned energy source (e.g., a patterned light source) and developed to form the openings extending through the dielectric layer138. In some embodiments, a patterned mask may be formed over the dielectric layer138and the dielectric layer138may be patterned through the patterned mask using an etching process, such as an anisotropic etch, to form the openings extending through the dielectric layer138.

The metallization pattern140is formed in the openings extending through the dielectric layer138. In some embodiments, the metallization pattern140may be formed on the dielectric layer138and the metallization pattern136. The metallization pattern120may be formed of materials and in a manner the same as or similar to the metallization pattern108. After the metallization pattern140is formed, a planarization process may be performed on the metallization pattern140to level top surfaces of the metallization pattern140with top surfaces of the dielectric layer138. The planarization process may be a CMP, a grinding process, or the like.

Thus, a first package component100is formed in the illustrated package region. The first package component100includes the integrated circuit dies50, the encapsulant134, the insulation layer132, the through vias126, the front-side redistribution structure124, and the backside redistribution structure144.

InFIG.10, conductive connectors146are formed over the metallization pattern140. The conductive connectors146may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors146may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors146are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the layer of solder has been formed, a reflow may be performed in order to shape the material into the desired bump shapes. In some embodiments, the conductive connectors146comprise metal pillars (such as copper pillars), which may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder free and have vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof. The metal cap layer may be formed by a plating process.

InFIG.11, a second package component200is coupled to the conductive connectors146. The second package component200is coupled to the first package component wo to form an integrated circuit device stack in the illustrated package region. The second package component200includes a substrate202and one or more stacked dies210(e.g., a first stacked die210A and a second stacked die210B) coupled to the substrate202. Although one set of stacked dies210(e.g., the first stacked die210A and the second stacked die210B) is illustrated, in some embodiments, multiple sets of stacked dies210(each including one or more stacked dies) may be disposed side-by-side and coupled to a surface of the substrate202. The substrate202may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may be used. The substrate202may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In some embodiments, the substrate202may be based on an insulating core, such as a fiberglass-reinforced resin core. The core material may be a fiberglass resin, such as FR4. In some embodiments, the core material may include bismaleimide-triazine (BT) resin, other printed circuit board (PCB) materials or films, or the like. Build-up films, such as Ajinomoto build-up film (ABF) or other laminates, may be used for the substrate202.

The substrate202may include active and passive devices (not separately illustrated). A wide variety of devices, such as transistors, capacitors, resistors, combinations of these, and the like, may be used to generate the structural and functional requirements of the design for the second package component200. The devices may be formed using any suitable methods.

The substrate202may also include metallization layers (not separately illustrated) and conductive vias208. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper) with vias interconnecting the layers of conductive materials. The metallization layers may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate202is substantially free of active and passive devices.

The substrate202may include bond pads204on a first side of the substrate202and bond pads206on a second side of the substrate202opposite the first side. The bond pads204may be used to couple to the stacked dies210and the bond pads206may be used to couple to the conductive connectors146. In some embodiments, such as the embodiment illustrated by the bond pads206, the bond pads204and the bond pads206are formed by forming recesses (not separately illustrated) into dielectric layers (not separately illustrated) on the first and second sides of the substrate202. The recesses may be formed to allow the bond pads204and the bond pads206to be embedded into the dielectric layers. In other embodiments, such as the embodiment illustrated by the bond pads204, the recesses are omitted as the bond pads204and the bond pads206may be formed on the dielectric layers. In some embodiments, the bond pads204and the bond pads206include a thin seed layer (not separately illustrated) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads204and the bond pads206may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. In some embodiments, the conductive material of the bond pads204and the bond pads206is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In some embodiments, the bond pads204and the bond pads206are UBMs, which include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, may be used for the bond pads204and the bond pads206. Any suitable materials or layers of material that may be used for the bond pads204and the bond pads206are fully intended to be included within the scope of the current application. In some embodiments, the conductive vias208extend through the substrate202and couple at least one of the bond pads204to at least one of the bond pads206.

In the illustrated embodiment, the stacked dies210are coupled to the substrate202by wire bonds212, although other connections may be used, such as conductive bumps. In some embodiments, the stacked dies210are stacked memory dies. For example, the stacked dies210may be memory dies, such as low-power (LP) double data rate (DDR) memory modules (e.g., LPDDR1, LPDDR2, LPDDR3, LPDDR4), DRAM dies, combinations thereof, or the like.

The stacked dies210and the wire bonds212may be encapsulated by a molding material214. In some embodiment, the molding material214may be molded on the stacked dies210and the wire bonds212using compression molding. In some embodiments, the molding material214is a molding compound, a polymer, an epoxy, a silicon oxide material, the like, or a combination thereof. A curing process may be performed to cure the molding material214. The curing process may be a thermal curing, a UV curing, the like, or a combination thereof. In some embodiments, the stacked dies210and the wire bonds212are buried in the molding material214. After the curing of the molding material214, a planarization step, such as a grinding, is performed to remove excess portions of the molding material214and provide a planar surface for the second package component200.

After the second package component200is formed, the second package component200may be bonded to the first package component100by way of the conductive connectors146, the bond pads206, and the metallization pattern140. In some embodiments, the stacked dies210may be coupled to the integrated circuit dies50through the wire bonds212, the bond pads204, the conductive vias208, the bond pads206, the conductive connectors146, the backside redistribution structure144, the through vias126, and the front-side redistribution structure124.

In some embodiments, a solder resist (not separately illustrated) is formed on the second side of the substrate202. The conductive connectors146may be disposed in openings in the solder resist to be electrically and mechanically coupled to conductive features (e.g., the bond pads206) in the substrate202. The solder resist may be used to protect areas of the substrate202from external damage. In some embodiments, the conductive connectors146have an epoxy flux (not separately illustrated) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the second package component200is attached to the first package component100.

InFIG.12, an encapsulant148is formed between the first package component100and the second package components200, surrounding the conductive connectors146. In some embodiments (not separately illustrated), the encapsulant148may further be formed around the second package component200, and the encapsulant148may be formed around the first package component100. The encapsulant148may be a molding compound, epoxy, a molding underfill, or the like. The encapsulant148may be applied by compression molding, transfer molding, or the like. The encapsulant148is further formed in gap regions between the second package component200and the underlying first package component100. The encapsulant148may be applied in liquid or semi-liquid form and subsequently cured.

InFIG.13, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate102from the first package component100(e.g., the dielectric layer106). In some embodiments, the de-bonding includes projecting a light, such as a laser light or a UV light, on the release layer104so that the release layer104decomposes under the heat of the light and the carrier substrate102can be removed. A major surface of the dielectric layer106may be exposed after removing the carrier substrate102and the release layer104.

After the carrier substrate102and the release layer104are removed, UBMs160and conductive connectors162are formed for external connection to the front-side redistribution structure124. The UBMs160include bump portions on and extending along the major surface of the dielectric layer106, and via portions extending through the dielectric layer106. The via portions of the UBMs160may be electrically coupled to and physically contact the metallization patterns108. As a result, the UBMs160are electrically coupled to the through vias126and the integrated circuit dies50through the front-side redistribution structure124. The UBMs160may be formed of materials and in a manner the same as or similar to the metallization pattern108.

Conductive connectors162are formed on the UBMs160. The conductive connectors162may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors162may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors162are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In some embodiments, the conductive connectors162comprise metal pillars (such as copper pillars), which may be formed by sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof. The metal cap layer may be formed by a plating process.

Further inFIG.13, the first package component100is mounted to a substrate300. The substrate300may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate300may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In some embodiments, the substrate300may be based on an insulating core such as a fiberglass reinforced resin core. In some embodiments, the core material may be a fiberglass resin such as FR4. In some embodiments, the core material may include bismaleimide-triazine (BT) resin, other printed circuit board (PCB) materials, or other films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used for the substrate300.

The substrate300may include active and passive devices (not separately illustrated). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be included. The devices may be formed using any suitable methods. The substrate300may also include metallization layers (not separately illustrated). The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper) with vias interconnecting the layers of conductive materials. The metallization layers may be formed through any suitable processes (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate300is substantially free of active and passive devices.

The substrate300may include bond pads302formed on a first side of the substrate300facing the first package component100. In some embodiments, the bond pads302may be formed by forming recesses (not separately illustrated) into dielectric layers (not separately illustrated) on the first side of the substrate300. The recesses may be formed to allow the bond pads302to be embedded into the dielectric layers. In some embodiments, the recesses are omitted and the bond pads302may be formed on the dielectric layers. In some embodiments, the bond pads302include a thin seed layer (not separately illustrated) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive materials of the bond pads302may be deposited over the thin seed layer. The conductive materials may be formed by an electro-chemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. In an embodiment, the conductive materials of the bond pads302include copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In some embodiments, the bond pads302are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, may be utilized for the formation of the bond pads302. Any suitable materials or layers of materials that may be used for the bond pads302are fully intended to be included within the scope of the current application.

The substrate300is electrically coupled and physically attached to the first package component wo by way of the bond pads302, the conductive connectors162, and the UBMs160. The substrate300may be placed over the first package component100and a reflow process may be performed to reflow the conductive connectors162and bond the bond pads302to the UBMs160through the conductive connectors162.

An underfill164may then be formed between the first package component100and the substrate300, surrounding the bond pads302, the UBMs160, and the conductive connectors162. The underfill164may reduce stress and protect the joints resulting from the reflowing of the conductive connectors162. The underfill164may be formed by a capillary flow process after the first package component100is attached to the substrate300, or may be formed by a suitable deposition method before the first package component100is attached.

Including the insulation layer132disposed between the encapsulant134and each of the through vias126, the integrated circuit dies50, and the metallization pattern120allows for a greater variety of materials to be used for the encapsulant134. For example, the insulation layer132provides electrical isolation, such that electrically conductive materials may be used for the encapsulant134. Further, the insulation layer132may provide a physical buffer layer, such that materials having high thermal expansion coefficients may be used for the encapsulant134. This allows for materials having high thermal conductivity to be used for the encapsulant134, which increases heat dissipation through the encapsulant134. This improves device performance and reduces device defects.

FIGS.14and15illustrate an embodiment in which integrated circuit dies50A are directly bonded to the front-side redistribution structure124(without the conductive connectors128and the underfill130disposed there between). InFIG.14the integrated circuit dies50A are bonded to the front-side redistribution structure124illustrated inFIG.4and an insulation layer132and an encapsulant134are formed over the resulting structure. The integrated circuit dies50A may be the same as or similar to the integrated circuit dies50, discussed above. The integrated circuit dies50A are disposed face down such that front sides of the integrated circuit dies50A face the conductive pads120B, and backsides of the integrated circuit dies50A face away from the conductive pads120B.

In some embodiments, the integrated circuit dies50A are bonded to the conductive pads120B of the metallization pattern120in a hybrid bonding configuration. For example, a dielectric layer68of the integrated circuit dies50A may be directly bonded to the dielectric layer118of the front-side redistribution structure124, and die connectors66of the integrated circuit dies50A may be directly bonded to the conductive pads120B. In an embodiment, the bond between the dielectric layer68and the dielectric layer118may be an oxide-to-oxide bond, or the like. The hybrid bonding process further directly bonds the die connectors66of the integrated circuit dies50A to the conductive pads120B through direct metal-to-metal bonding. Thus, electrical connection between the integrated circuit dies50A and the front-side redistribution structure124is provided by the physical connection of the die connectors66to the conductive pads120B.

As an example, the hybrid bonding process may start by applying a surface treatment to the dielectric layer118of the front-side redistribution structure124and/or the dielectric layer68of the integrated circuit dies50A. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water or the like) that may be applied to the dielectric layer118and/or the dielectric layer68of the integrated circuit dies50A. The hybrid bonding process may then proceed to aligning the die connectors66to the conductive pads120B. Next, the hybrid bonding includes a pre-bonding step, during which the die connectors66are brought into physical contact with the conductive pads120B. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). The hybrid bonding process continues with performing an anneal at a temperature ranging from about 150° C. to about 400° C. for a duration ranging from about 0.5 hours to about 3 hours. The anneal causes the metal of the die connectors66(e.g., copper) and the metal of the conductive pads120B (e.g., copper) to inter-diffuse with each other, forming the direct metal-to-metal bonding. The anneal may further form covalent bonds between the dielectric layer68and the dielectric layer118. In some embodiments, other bonding parameters and/or methods (e.g., solder bonding) may be used.

After the integrated circuit dies50A are bonded to the front-side redistribution structure124, the insulation layer132and the encapsulant134may be formed over the through vias126, the integrated circuit dies50A, and the front-side redistribution structure. The insulation layer132may be formed of materials and in a manner the same as or similar to those discussed above with respect toFIG.7. Similarly, the encapsulant134may be formed of materials and in a manner the same as or similar to those discussed above with respect toFIG.7.

FIG.15illustrates the structure ofFIG.14after the processes discussed above with respect toFIG.8through13are performed. Directly bonding the integrated circuit dies50A to the front-side redistribution structure124simplifies the process for bonding the integrated circuit dies50A to the front-side redistribution structure124, eliminates the steps required to form the underfill130, and reduces the height of the final structure. Moreover, including the insulation layer132disposed between the encapsulant134and each of the through vias126, the integrated circuit dies50A, and the metallization pattern120allows for a greater variety of materials to be used for the encapsulant134. For example, the insulation layer132provides electrical isolation, such that electrically conductive materials may be used for the encapsulant134. Further, the insulation layer132may provide a physical buffer layer, such that materials having high thermal expansion coefficients may be used for the encapsulant134. This allows for materials having high thermal conductivity to be used for the encapsulant134, which increases heat dissipation through the encapsulant134. This improves device performance and reduces device defects.

FIGS.16through18illustrate an embodiment in which multiple integrated circuit dies50B and50C along with interconnection dies70are bonded to the front-side redistribution structure124. InFIGS.16and17the integrated circuit dies50B and50C and the interconnection dies70are bonded to the front-side redistribution structure124illustrated inFIG.4and an insulation layer132and an encapsulant134are formed over the resulting structure. The integrated circuit dies50B and50C may be the same as or similar to the integrated circuit dies50, discussed above. The integrated circuit dies50B and50C are disposed face down such that front sides of the integrated circuit dies50B and50C face the conductive pads120B, and backsides of the integrated circuit dies50B and50C face away from the conductive pads120B. Further, the integrated circuit dies50B may include through-substrate vias (TSVs)67(also referred to as through-silicon vias) that extend through the semiconductor substrate52of the integrated circuit dies50B.

The interconnection dies70may be local silicon interconnects (LSIs), large-scale integration packages, interposer dies, or the like. The interconnection dies70include substrates72, with conductive features formed in and/or on the substrates72. The substrates72may be semiconductor substrates, dielectric layers, or the like. The interconnection dies70may include through-substrate vias (TSVs)74(also referred to as through-silicon vias), which extend into or through the substrate72. In the embodiment illustrated inFIGS.16through18, the TSVs74extend through the substrate72and are exposed at both front-sides and backsides of the interconnection dies70.

The integrated circuit dies50B may be bonded to the front-side redistribution structure124through conductive connectors128and an underfill130, through processes similar to or the same as those discussed above with respect toFIGS.5and6. The interconnection dies70may be bonded to the integrated circuit dies50B and the integrated circuit dies50C may be bonded to the interconnection dies70by hybrid bonding processes the same as or similar to those discussed above with respect toFIG.14. Specifically, the TSVs74of the interconnection dies70may be bonded to the TSVs67of the integrated circuit dies50B through metal-to-metal bonding; the substrates72of the interconnection dies70may be bonded to the semiconductor substrates52of the integrated circuit dies50B through oxide-to-oxide bonding; the die connectors66of the integrated circuit dies50C may be bonded to the TSVs74of the interconnection dies70through metal-to-metal; and the dielectric layers68of the integrated circuit dies50C may be bonded to the substrates72of the interconnection dies70through oxide-to-oxide bonding.FIG.16illustrates an embodiment in which each of the integrated circuit dies50B and50C and the interconnection dies70have the same widths.FIG.17illustrates an embodiment in which the interconnection dies70may have widths less than the integrated circuit dies50B and the integrated circuit dies50C may have widths equal to or less than the interconnection dies70. More generally, the width of the each of the dies stacked over the front-side redistribution structure124may be equal to or less than the width of an underlying die on which the die is stacked. Although three dies are illustrated in each stack inFIGS.16and17, any number of the interconnection dies70and the integrated circuit dies50B and50C may be included.

After the integrated circuit dies50B and50C and the interconnection dies70are bonded to the front-side redistribution structure124, the insulation layer132and the encapsulant134may be formed over the through vias126, the integrated circuit dies50B and50C, the interconnection dies70, and the front-side redistribution structure124. The insulation layer132may be formed of materials and in a manner the same as or similar to those discussed above with respect toFIG.7. Similarly, the encapsulant134may be formed of materials and in a manner the same as or similar to those discussed above with respect toFIG.7.

FIG.18illustrates the structure ofFIG.16after the processes discussed above with respect toFIG.8through13are performed. Including the insulation layer132disposed between the encapsulant134and each of the through vias126, the integrated circuit dies50B and50C, the interconnection dies70, and the metallization pattern120allows for a greater variety of materials to be used for the encapsulant134. For example, the insulation layer132provides electrical isolation, such that electrically conductive materials may be used for the encapsulant134. Further, the insulation layer132may provide a physical buffer layer, such that materials having high thermal expansion coefficients may be used for the encapsulant134. This allows for materials having high thermal conductivity to be used for the encapsulant134, which increases heat dissipation through the encapsulant134. This improves device performance and reduces device defects. Moreover, providing stacked dies surrounded by the encapsulant134improves heat dissipation from all of the encapsulated dies, and provides for improved functionality of the packaged structure.

FIGS.19through21illustrate an embodiment in which interconnection dies70A are directly bonded to the front-side redistribution structure124and integrated circuit dies50D are directly bonded to the interconnection dies70A or are directly bonded to interconnection dies70B, which are directly bonded to the interconnection dies70A. InFIG.19the integrated circuit dies50D are bonded to the interconnection dies70A, and the stacks including the integrated circuit dies50D and the interconnection dies70A are bonded to the front-side redistribution structure124illustrated inFIG.4. An insulation layer132and an encapsulant134are formed over the resulting structure. InFIG.20the integrated circuit dies50D are bonded to the interconnection dies70B, the interconnection dies70B are bonded to the interconnection dies70A, and the stacks including the integrated circuit dies50D, the interconnection dies70B, and the interconnection dies70A are bonded to the front-side redistribution structure124illustrated inFIG.4. An insulation layer132and an encapsulant134are formed over the resulting structure. The integrated circuit dies50D may be the same as or similar to the integrated circuit dies50, discussed above. The integrated circuit dies50B and50C are disposed face down such that front sides of the integrated circuit dies50B and50C face the conductive pads120B, and backsides of the integrated circuit dies50B and50C face away from the conductive pads120B. The interconnection dies70A and70B may be the same as or similar to the interconnection dies70, discussed above.

The interconnection dies70A may be bonded to the front-side redistribution structure124by hybrid bonding processes the same as or similar to those discussed above with respect toFIG.14. Specifically, the TSVs74of the interconnection dies70A may be bonded to the conductive pads120B of the front-side redistribution structure124through metal-to-metal bonding and the substrates72of the interconnection dies70A may be bonded to the dielectric layer118of the front-side redistribution structure124through oxide-to-oxide bonding. The interconnection dies70B may be bonded to the interconnection dies70A by hybrid bonding processes the same as or similar to those discussed above with respect toFIG.14. Specifically, the TSVs74of the interconnection dies70B may be bonded to the TSVs74of the interconnection dies70A through metal-to-metal bonding and the substrates72of the interconnection dies70B may be bonded to the substrates72of the interconnection dies70A through oxide-to-oxide bonding. The integrated circuit dies50D may be bonded to the interconnection dies70A or70B by hybrid bonding processes the same as or similar to those discussed above with respect toFIG.14. Specifically, the die connectors66of the integrated circuit dies50D may be bonded to the TSVs74of the interconnection dies70A or70B through metal-to-metal bonding and the dielectric layers68of the integrated circuit dies50D may be bonded to the substrates72of the interconnection dies70A or70B through oxide-to-oxide bonding.

FIG.19illustrates an embodiment in which each of the integrated circuit dies50D and the interconnection dies70A have the same widths, and each of the integrated circuit dies50D is bonded to the front-side redistribution structure124through a single interconnection die70A.FIG.20illustrates an embodiment in which the interconnection dies70B may have widths less than the interconnection dies70A and the integrated circuit dies50D may have widths equal to or less than the interconnection dies70B. More generally, the width of the each of the dies stacked over the front-side redistribution structure124may be equal to or less than the width of an underlying die on which the die is stacked. Further inFIG.20, each of the integrated circuit dies50D is bonded to the front-side redistribution structure124through an interconnection die70B and an interconnection die70A. Although two dies are illustrated in each stack inFIG.19and three dies are illustrated in each stack inFIG.20, any number of the interconnection dies70A, the interconnection dies70B, and the integrated circuit dies50D may be included.

After the integrated circuit dies50D and the interconnection dies70A and70B are bonded to the front-side redistribution structure124, the insulation layer132and the encapsulant134may be formed over the through vias126, the integrated circuit dies50D, the interconnection dies70A and70B, and the front-side redistribution structure124. The insulation layer132may be formed of materials and in a manner the same as or similar to those discussed above with respect toFIG.7. Similarly, the encapsulant134may be formed of materials and in a manner the same as or similar to those discussed above with respect toFIG.7.

FIG.21illustrates the structure ofFIG.19after the processes discussed above with respect toFIG.8through13are performed. Including the insulation layer132disposed between the encapsulant134and each of the through vias126, the integrated circuit dies50D, the interconnection dies70A and70B, and the metallization pattern120allows for a greater variety of materials to be used for the encapsulant134. For example, the insulation layer132provides electrical isolation, such that electrically conductive materials may be used for the encapsulant134. Further, the insulation layer132may provide a physical buffer layer, such that materials having high thermal expansion coefficients may be used for the encapsulant134. This allows for materials having high thermal conductivity to be used for the encapsulant134, which increases heat dissipation through the encapsulant134. This improves device performance and reduces device defects. Moreover, providing stacked dies surrounded by the encapsulant134improves heat dissipation from all of the encapsulated dies, and provides for improved functionality of the packaged structure.

FIGS.22through25illustrate an embodiment in which an insulation layer408(illustrated inFIGS.23through25) is formed along sidewalls of the through vias126, without being formed over the remainder of the front-side redistribution structure125or the integrated circuit dies50. InFIG.22, a mask layer402and a photoresist404are formed over the front-side redistribution structure124illustrated inFIG.3. The mask layer402may include, for example, silicon nitride, silicon oxynitride, or the like. In some embodiments, the mask layer402may be a polymer layer. The mask layer402may be formed, for example, by spin coating, lamination, CVD, ALD, or the like. The photoresist404is formed over the mask layer402. The photoresist404may be formed by depositing a photosensitive layer over the mask layer402using spin-on coating or the like.

The photoresist404and the mask layer402may then be patterned. The photoresist404may be patterned by exposing the photoresist404to a patterned energy source (e.g., a patterned light source) and developing the photoresist404to remove an exposed or unexposed portion of the photoresist404. Openings406exposing the mask layer402are formed extending through the photoresist404. The mask layer402may be etched using the photoresist404as a mask using any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The mask layer402may be etched by an anisotropic etch process.

InFIG.23, the photoresist404is removed and an insulation layer408is formed along sidewalls of the mask layer402in the openings406. The photoresist404may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. The insulation layer408may be formed of materials and deposited in a manner the same as or similar to the insulation layer132. After the insulation layer408is deposited, the insulation layer408may be etched to expose the conductive pads120A of the front-side redistribution structure124. The insulation layer408may have a thickness t2ranging from about 10 nm to about wo nm. Forming the insulation layer408to a thickness less than the prescribed range may cause difficulties in the formation of the insulation layer408and may be insufficient for providing the benefits of the insulation layer408(e.g., providing electrical isolation for subsequently formed vias, such as vias126, discussed below with respect toFIG.24). Further, the insulation layer408may be formed of a material having a lower thermal conductivity than the material of a subsequently formed encapsulant (such as the encapsulant134, discussed below with respect toFIG.25). Forming the insulation layer408to a thickness greater than the prescribed range lowers the combined thermal conductivity of the insulation layer408and the encapsulant134.

InFIG.24, vias126are formed on the conductive pads120A of the metallization pattern120and filling the openings406. The vias126may extend away from the topmost dielectric layer of the front-side redistribution structure124(e.g., the dielectric layer118) and may extend between portions of the insulation layer408formed on opposite sidewalls of each of the openings406. As an example to form the vias126, a seed layer (not separately illustrated) is formed in the openings406over the conductive pads120A and the insulation layer408and over the mask layer402. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. In some embodiments, such as embodiments where the vias126are the same width as or narrower than the underlying conductive pads120A, a separate seed layer may be omitted, and the conductive pads120A may act as the seed layer. A conductive material is then formed over the seed layer and filling the openings406. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. After the conductive material is formed, a planarization process may be performed on the conductive material and the seed layer. The planarization process may be a CMP, a grinding process, or the like. The remaining portions of the seed layer and the conductive material form the vias126. Top surfaces of the vias126, the insulation layer408, and the mask layer402may be level with one another following the planarization process (e.g., within process variations).

InFIG.25, the mask layer402is removed and the processes discussed above with respect toFIG.5through13are performed (with the processes used to form the insulation layer132being omitted). The mask layer402may be removed by an etching process, such as an isotropic or an anisotropic etching process, or the like. Including the insulation layer408disposed between the encapsulant134and the through vias126allows for a greater variety of materials to be used for the encapsulant134. For example, the insulation layer408provides electrical isolation, such that electrically conductive materials may be used for the encapsulant134. Further, the insulation layer408may provide a physical buffer layer, such that materials having high thermal expansion coefficients may be used for the encapsulant134. This allows for materials having high thermal conductivity to be used for the encapsulant134, which increases heat dissipation through the encapsulant134. This improves device performance and reduces device defects. Moreover, forming the insulation layer408only along sidewalls of the through vias126improves precision of the deposition of the insulation layer408, and reduces the material used for the insulation layer408. However, forming the insulation layer408only along sidewalls of the through vias126may also increase costs compared to embodiments in which the insulation layer132is formed.

Embodiments may achieve various advantages. For example, forming the insulation layer over underlying vias, redistribution structures, and integrated circuit dies enables a wider range of materials to be used for the encapsulant formed over the insulation layer. The insulation layer may provide electrical insulation and a physical buffer between the encapsulant and the underlying structures, which enables the encapsulant to be formed of electrically conductive materials and materials having higher thermal expansion coefficients, respectively. This allows materials having higher thermal conductivities to be used for the encapsulant, which improves heat dissipation through the encapsulant, and improves device performance and reduces device defects.

In accordance with an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume. In an embodiment, the encapsulant has a thermal conductivity of greater than 40 W/m·K. In an embodiment, a top surface of the encapsulant is level with a top surface of the first through via and top surfaces of the insulation layer, and the top surface of the encapsulant is above a top surface of the first die. In an embodiment, the insulation layer extends along sidewalls of the first through via, a top surface of the first redistribution structure, and a top surface and sidewalls of the first die. In an embodiment, the first die is bonded to the first redistribution structure by oxide-to-oxide bonds and metal-to-metal bonds. In an embodiment, the first die is bonded to the first redistribution structure through conductive connectors, the semiconductor device further includes a first underfill surrounding the conductive connectors, and the insulation layer extends along sidewalls of the first underfill. In an embodiment, the insulation layer has a thickness ranging from 10 nm to 100 nm, and the encapsulant has a thermal conductivity ranging from 40 W/m·K to 100 W/m·K.

In accordance with another embodiment, a semiconductor device includes a first integrated circuit die; a front-side redistribution structure on a front-side of the first integrated circuit die; a backside redistribution structure on a backside of the first integrated circuit die; a molding compound encapsulating the first integrated circuit die between the front-side redistribution structure and the backside redistribution structure, the molding compound having a thermal conductivity of greater than 40 W/m·K; a through via extending through the molding compound, the through via being electrically coupled to the front-side redistribution structure and the backside redistribution structure; and an insulation layer covering sidewalls of the through via, the insulation layer separating the through via from the molding compound. In an embodiment, the molding compound includes conductive particles selected from copper (Cu), silicon (Si), silver (Ag), gold (Au), iron (Fe), and tungsten (W), and the molding compound includes the conductive particles at a concentration ranging from 70% to 95% by volume. In an embodiment, the molding compound has a thermal conductivity ranging from 40 W/m·K to wo W/m·K, and the insulation layer has a thermal conductivity less than the thermal conductivity of the molding compound. In an embodiment, the insulation layer includes at least one of aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond, or aluminum oxide (Al2O3). In an embodiment, the semiconductor device further includes an interconnection die bonded to the first integrated circuit die by metal-to-metal bonds and oxide-to-oxide bonds. In an embodiment, the molding compound physically contacts the front-side redistribution structure, the backside redistribution structure, and the first integrated circuit die. In an embodiment, the insulation layer covers a top surface of the front-side redistribution structure and a backside and sidewalls of the first integrated circuit die, and the insulation layer separates the front-side redistribution structure and the first integrated circuit die from the molding compound.

In accordance with yet another embodiment, a method includes forming a via over a redistribution structure; bonding a semiconductor die to the redistribution structure adjacent the via; depositing an insulation layer over the via, the redistribution structure, and the semiconductor die, the insulation layer electrically isolating the through via, the redistribution structure, and the semiconductor die from one another; and preparing a molding compound by mixing an epoxy and conductive fillers, the conductive fillers making up 70% to 95% of the molding compound by volume; depositing the molding compound over the insulation layer, the molding compound being configured to conduct heat from the semiconductor die. In an embodiment, the insulation layer is deposited by a conformal deposition process. In an embodiment, the method further includes planarizing the molding compound and the insulation layer to expose the via. In an embodiment, bonding the semiconductor die to the redistribution structure includes reflowing conductive connectors between semiconductor die and the redistribution structure; and forming an underfill material surrounding the conductive connectors, the insulation layer being deposited on sidewalls of the underfill material. In an embodiment, bonding the semiconductor die to the redistribution structure includes forming oxide-to-oxide bonds and metal-to-metal bonds between the semiconductor die and the redistribution structure. In an embodiment, bonding the semiconductor die to the redistribution structure includes bonding a die stack to the redistribution structure, the die stack including the semiconductor die and an interconnection die, the insulation layer being further deposited on the interconnection die.

Certain embodiments disclosed herein provide for a semiconductor device including a first redistribution structure. The semiconductor device also includes a first die electrically coupled to the first redistribution structure. The device also includes a continuous insulation layer extending over the first redistribution structure and the first die. The device also includes an encapsulant may include conductive fillers and extending over the continuous insulation layer, the encapsulant surrounding portions of the first die. The device also includes a conductive via extending through the encapsulant, sidewalls of the conductive via being surrounded by the continuous insulating layer, where a top surface of the encapsulant is level with a top surface of the conductive via and a top surface of the continuous insulation layer.

Certain other embodiments disclosed herein provide for semiconductor device having a first redistribution structure. The semiconductor device also includes a first integrated circuit die on and electrically connected to the first redistribution structure. The device also includes a molding compound at least partially encapsulating the first integrated circuit die, the molding compound may include conductive fillers. The device also includes a through via extending through the molding compound and electrically contacting the redistribution structure. The device also includes an insulation layer covering sidewalls of the through via, where the insulation layer electrically insulates the through via from the molding compound, and further where the insulation layer electrically insulates the first redistribution structure and the first integrated circuit die from the molding compound.

Certain additional embodiments disclosed herein provide for a method including forming a conductive via on a redistribution structure. The method also includes bonding a semiconductor die to the redistribution structure. The method also includes at least partially surrounding the conductive via and the semiconductor die with an insulation layer. The method also includes depositing over the insulating layer, a molding compound may include conductive fillers the molding compound being configured to conduct heat from the semiconductor die, and the insulating layer being configured to electrically insulate the conductive via and the semiconductor die from the molding compound.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.