Patent ID: 12249908

FIG.1shows a power inverter circuit1. The power inverter circuit1comprises an electrical component2, an inverter semiconductor bridge3and a magnetic element4. The electrical component2comprises an input port2aand an output port2b. The input port2aof the electrical component2is also the input port of the power inverter circuit1. The input port2aof the electrical component2is configured to be connected to a DC input, for example a battery.

The inverter semiconductor bridge3comprises an input port3aand an output port3b. The output port2bof the electrical component2is configured to be connected to the input port3aof the inverter semiconductor bridge3. The output port3bof the inverter semiconductor bridge3is configured to be connected to a cable wherein the inverter semiconductor bridge3is configured to provide an alternating current to the cable. The cable is configured to be connected to a motor. The magnetic element4is arranged around the output port3bof the inverter semiconductor bridge3. The magnetic element4is configured to provide a filtering of the alternating current provided at the output port3bof the inverter semiconductor bridge3.

The inverter semiconductor bridge3is configured to transform a direct current provided at the input port of the power inverter circuit1into an alternating current provided at the output port of the power inverter circuit1. The inverter semiconductor bridge3comprises one or more transistors.

The electrical component comprises a DC link capacitor CDCLand an EMC filter (EMC=electromagnetic compatibility). The DC link capacitor CDCLis configured to store energy. The EMC filter is configured to limit unwanted emissions and to increase the inverter immunity.

The DC link capacitor CDCLand the EMC filter of the electrical component are integrated into a single circuit. Thus, for connecting the DC link capacitor CDCLand the EMC filter to the power inverter circuit1, only a single interface connection between the electrical component2and the inverter semiconductor bridge3has to be closed.

The EMC filter comprises a first filter stage6and a second filter stage7which are schematically indicated inFIG.1. The first filter stage6is arranged between the input port2aof the electrical component2and the DC link capacitor CDCL. The second filter stage7is arranged between the output port2bof the electrical component2and the DC link capacitor CDCL.

During operation of the power inverter circuit1, parasitic currents and disturbances can be generated in the inverter semiconductor bridge3. By arranging the second filter stage7at the output port2bof the electrical component2, the second filter stage7is arranged close to the inverter semiconductor bridge3. Accordingly, the second filter stage7can filter and reduce any parasitic current or disturbances generated in the inverter semiconductor bridge3before the parasitic currents or disturbances can reach the DC link capacitor CDCL. Thus, the second filter stage7can avoid noise migration from the inverter semiconductor bridge3to the DC link capacitor CDCL. The second filter stage7is configured to filter noise right at the source before it can spread in an uncontrolled manner within the power inverter circuit. Accordingly, the second filter stage7is an early filter stage.

The first filter stage6is arranged between the DC link capacitor CDCLand the input port2asuch that the first filter stage6is configured to filter and reduce any noise or parasitic currents provided at the input port2abefore the noise can mitigate into the DC link capacitor CDCL.

The electrical component2is discussed in detail with respect toFIG.2which shows a circuit diagram of the electrical component2. In particular,FIG.2shows the first filter stage6and the second filter stage7in more detail.

The input port2aand the output port2bof the electrical component2each comprise two terminals. A first terminal of the input port2ais connected by the first signal line8to a first terminal of the output port2b. A second terminal of the input port2ais connected by a second signal line9to a second terminal of the output port2b.

The first filter stage6comprises a first y-capacitor Cy11, a second y-capacitor Cy12, an x-capacitor Cx, a first magnetic element Lb1and a second magnetic element Lb2wherein each of the magnetic elements Lb1, Lb2operates as an inductor.

The y-capacitors Cy11, Cy12are designed to filter out common-mode noise. The first y-capacitor Cy11of the first filter stage6is connected to the first signal line8and a reference potential. The reference potential can be a housing or a chassis of the electrical component2. The first Y-capacitor Cy11is connected in series with a first resistor R1. In particular, the first signal line8is connected via the first resistor R1and the first y-capacitor Cy11of the first filter stage6to the reference potential. The first resistor R1provides resistive damping.

The second y-capacitor Cy12of the first filter stage6is connected to the second signal line9and to the reference potential. In particular, the second signal line9is connected via a second resistor R2, the second Y-capacitor Cy12to the reference potential.

The x-capacitor Cxis connected between the two signal lines8,9. The x-capacitor Cxis configured to protect the power inverter circuit1against differential mode interference.

Each of the magnetic elements Lb1, Lb2comprises a core. According to one embodiment, the cores comprise manganese-zinc ferrite. According to another embodiment, the cores comprise nanocrystalline tape cores.

The first magnetic element Lb1is arranged around the first signal line8. The second magnetic element Lb2is arranged around the second signal line9.

Additionally, the first filter stage6comprises a third resistor R3which is connected between the two signal lines8,9. The third resistor R3is connected parallel to the DC link capacitor CDCL.

The second filter stage7comprises a first y-capacitor Cy21, a second y-capacitor Cy22, a snubber capacitor CS, a first magnetic element La1and a second magnetic element La2, each of the magnetic elements La1, La2operating as inductors.

The y-capacitors Cy21, Cy22of the second filter stage7are designed to filter out common-mode noise. The first y-capacitor Cy21of the second filter stage7is connected to the first signal line8and a reference potential. The reference potential can be a housing or a chassis of the electrical component2. The first Y-capacitor Cy21is connected in series with a fourth resistor R4. In particular, the first signal line8is connected via the fourth resistor R4and the first y-capacitor Cy21of the second filter stage7to the reference potential. The fourth resistor R4provides resistive damping.

The second y-capacitor Cy22of the second filter stage7is connected to the second signal line9and to the reference potential. In particular, the second signal line9is connected via a fifth resistor R5and the second Y-capacitor Cy22to the reference potential.

The snubber capacitor CSis connected between the two signal lines8,9.

Each of the magnetic elements La1, La2of the second filter stage7comprises a core. According to one embodiment, the cores comprise manganese-zinc ferrite. According to another embodiment, the cores comprise nanocrystalline tape cores.

The first magnetic element La1is arranged around the first signal line8. The second magnetic element La2is arranged around the second signal line9.

Additionally, the second filter stage7comprises a sixth resistor R6which is connected between the two signal lines8,9. The sixth resistor R6is connected parallel to the DC link capacitor CDCL.

The magnetic elements La1, La2are configured to decouple a parasitic current provided at the output port2bof the electrical component2. In particular, current peaks of a parasitic current can be damped by the magnetic elements La1, La2. At the same time, the magnetic elements La1, La2operating as an inductor create a leakage inductance which is compensated by the snubber capacitor CS. Accordingly, the magnetic elements La1, La2and the snubber capacitor CSprovide an LC-filter.

Each of the first filter stage6and the second filter stage7forms an LC-filter which is additionally combined with y-capacitors. As the DC link capacitor CDCLis arranged between the two filter stages6,7which each comprise a magnetic element Lb1, Lb2, La1, La2operating as an inductor, the DC link capacitor CDCLis configured and arranged to provide capacitive noise suppression. Accordingly, the DC link capacitor CDCLprovides an additional pole in the filter circuit and helps to reduce the overall amount of additional symmetrical capacitors in the circuit.

Parasitic inductances of the DC link capacitor CDCLcan result in ringing. The two filter stages6,7of the EMC filter comprising y-capacitors Cy11, Cy12, Cy21, Cy22, the snubber capacitor CSand, respectively, the x-capacitor Cxcan reduce the unwanted ringing.

FIGS.3and4show the permeability for two cores which can be used as magnetic elements Lb1, Lb2, La1, La2for different frequencies.FIG.3shows the real permeability andFIG.4shows the complex permeability of the two cores. According to a first embodiment, the cores of the magnetic elements Lb1, Lb2, La1, La2are MnZn cores. According to a second embodiment, the cores are nanocrystalline tape cores. The curves K1show the real and complex permeability of the cores of the first embodiment and the curves K2show the real and complex permeability of the cores of the second embodiment.

Both cores have, in general, losses in the range above 100 KHz which help to damp ringing. The complex part of the permeability shown inFIG.4reflects the losses. It can be seen inFIG.4that the MnZn core provides high losses and therefore good filtering for frequencies of roughly 106Hz. Further, the nanocrystalline tape cores provide particularly good filtering for frequencies of roughly 100 KHz. The nanocrystalline tape cores can provide good losses in the kilohertz up to FM frequency range.

FIG.5shows the electrical component2in a perspective view. The DC link capacitor CDCLrequires most of the volume of the electrical component2. The first filter stage6is arranged between the input port2aand the DC link capacitor CDCLand the second filter stage7is arranged between the output port2band the DC link capacitor CDCL. By combining the EMC filter and the DC link capacitor CDCLinto a single component comprising one chassis10with input and output terminals, the overall volume requirement is reduced compared to a device wherein the DC link capacitor and the EMC filter are separate components.

FIG.6shows the noise level NLnewof the power inverter circuit1shown inFIG.1compared to the noise level NLcompof a comparative power inverter circuit wherein the EMC filter and the DC link capacitor are provided as separate elements, as shown inFIG.7. It is shown that the noise level NLnewfor the power inverter circuit1comprising the electrical component2of the present invention is reduced compared to the comparative power inverter circuit. Thus, the performance of the power inverter circuit1is improved over the comparative embodiment. In particular, for frequencies above 10 MHz the noise of the power inverter circuit1of the present invention is reduced compared to the comparative embodiment.

REFERENCE NUMERALS

1power inverter circuit2electrical component2ainput port2boutput port3inverter semiconductor bridge3ainput port3boutput port4magnetic element6first filter stage7second filter stage8first signal line9second signal line10chassisCDCLDC link capacitorCy11first y-capacitor of the first filter stageCy12second y-capacitor of the first filter stageCxx-capacitorLb1first magnetic element of the first filter stageLb2second magnetic element of the first filter stageCy21first y-capacitor of the second filter stageCy22second y-capacitor of the second filter stageCxsnubber capacitorLa1first magnetic element of the second filter stageLa2second magnetic element of the second filter stageR1first resistorR2second resistorR3third resistorR4fourth resistorR5fifth resistorR6sixth resistor