Patent ID: 12211769

DETAILED DESCRIPTION

FIG.1shows an exemplary embodiment of an open TSV1according to the improved concept. In this embodiment, the insulation layer20comprises a first and a second sublayer21,22.

In detail, the embodiment shown comprises a substrate body10that has a semiconducting portion11and an interlayer dielectric portion12. For example, the semiconducting portion11is a silicon substrate. The semiconducting portion11comprises a surface13that is arranged on the side of the semiconducting portion11that faces away from the interlayer dielectric portion12. For example, the surface13is a process surface such as a polished surface. Typically, this surface13is referred to as the backside of the semiconducting portion11.

The interlayer dielectric portion12is arranged adjacent to a further surface, typically a processed surface referred to as the top surface of the semiconducting portion11, of the semiconducting portion11that faces away from the surface13. For example, the interlayer dielectric portion12is arranged immediately adjacent to the semiconducting portion11, i.e. the interlayer dielectric portion12is in direct contact with the semiconducting portion11. The interlayer dielectric portion12comprises metal contact layers60that are insulated from each other by means of an interlayer dielectric such as an oxide and form active circuitry of an integrated circuit, for instance. For illustration purposes,FIG.1only shows a single contact layer60.

The TSV1further comprises a trench14that X tends from the surface13at least through the semiconducting portion11and optionally, as illustrated here, partially through the interlayer dielectric portion12. The trench14is characterized by side walls15that extend vertically, i.e. in a direction perpendicular to the surface13, and a bottom wall16that extends horizontally, i.e. in a direction parallel to the surface13. The trench14may be configured to expose a contact surface of a contact layer60arranged within the interlayer dielectric portion12.

The surface13and the side walls15are covered by the insulation layer20. To this end, in this embodiment the insulation layer20comprises sublayers21,22, which may be referred to as the first insulation sublayer and the second insulation sublayer. The first of the sublayers21in this embodiment is a conformal layer extending into the trench14, i.e. it covers both at least portions of the surface13and at least portions of the side walls15with a substantially identical thickness. The thickness is measured in a perpendicular direction with respect to the surface13and the side walls15. The second of the sublayers22in this embodiment is a non-conformal layer, i.e. it covers at least portions of the surface13without extending into the trench14.

The first and the second of the sublayers21,22differ from each other in terms of material properties such as intrinsic stress. For example, the first of the sublayers21is based on a tetraethoxysilane, TEOS, precursor while the second of the sublayers22is based on a different silane precursor. In this way, the first of the sublayers21may be characterized by a certain intrinsic stress while the second of the sublayers22has an intrinsic stress larger than that of the first of the sublayers21. Hence, the overall intrinsic stress inside the trench14is capped at a level at which the cracking probability is insignificant. Outside the trench14, the second of the sublayers22in this embodiment serves the purpose of compensating intrinsic stress formed within or across the substrate body10and the remaining layers30,40,50. The sublayers21,22can be distinguished and/or identified by means of a short hydrofluoric etch as they possess significantly distinct etch rates.

The insulation layer20in this embodiment is disposed immediately adjacent to the substrate body10. In alternative embodiments, additional layers may be arranged in between the insulation layer20and the substrate body10. Examples of such additional layers include adhesive promoting layers. Moreover, in alternative embodiments, the first of the sublayers21may be a non-conformal layer while the second of the sublayers22may be a conformal layer extending into the trench14.

The insulation layer20is covered by a metallization layer30and a redistribution layer40. The metallization layer30is configured to cover at least portions of the insulation layer20that is disposed adjacent to the side walls15as well as the bottom wall16. Optionally, the metallization layer30is arranged immediately adjacent to, i.e. in contact with, a contact layer60. The redistribution layer40is configured to cover at least portions of the metallization layer30and at least portions of the insulation layer20that is disposed adjacent to the surface13. In this embodiment, the metallization layer30is disposed immediately adjacent to the bottom wall16and to the insulation layer20, i.e. the first of the sublayers21. In alternative embodiments not shown, additional layers may be arranged in between the insulation layer20and the metallization layer30.

The redistribution layer40is arranged immediately adjacent to the metallization layer30, i.e. said layers are in direct contact with each other. To this end, the redistribution layer extends at least partially into the trench14. The metallization layer30and the redistribution layer40are of an electrically conductive materials such as metals. For example, the metallization layer30and the redistribution layer40of the same material such as tungsten. Likewise, the contact layer60is of an electrically conductive material, such that the metallization layer30provides an electrically conductive connection between the contact layer60and the redistribution layer40, wherein the latter may be in electrical contact with contact pads. Alternatively, the redistribution layer40may be at least partially exposed in order to form contact pads.

A capping layer50is disposed adjacent to at least a portion of the metallization layer30and to at least a portion of the redistribution layer40. The capping layer50may serve as a protective layer and/or for stress compensation and may be of a semiconductor material such as an oxide. For example, the material of the capping layer50corresponds to a material of the insulation layer20. In this embodiment, the capping layer50is disposed immediately adjacent to the metallization layer30and the redistribution layer40. In alternative embodiments not shown, additional layers may be arranged in between the capping layer50and the metallization and redistribution layers30,40.

The intrinsic stress of the first and the second of the sublayers21,22is chosen in such a manner that an overall strain of the TSV1is prevented. For example, the intrinsic stress of the first of the sublayers21is chosen in the way that the overall stress resulting from the substrate body10and all layers20,30,40,50within the trench14is substantially zero. The metallization layer30for example has a tensile type stress, which is typical for tungsten, such that a material of the first of the sublayers21is chosen to have an intrinsic stress of substantially the same magnitude but of a compressive type. In order to compensate for a global compressive or tensile stress, the second of the sublayers22is consequently chosen to have a stress necessary for the desired compensation. For example, an intrinsic stress of the second of the sublayers22is compressive or tensile with a magnitude larger than the intrinsic stress of the first of the sublayers21. The intrinsic stress is controlled during deposition of the respective sublayer, for instance.

FIG.2shows an alternative exemplary embodiment of an open TSV1. In this embodiment, the insulation layer20is a single layer extending into the trench14in order to cover both the surface13and the side walls15. For example, the insulation layer20in this embodiment is a conformal layer. However, a thickness of the portion of the insulation layer20that is disposed adjacent to the surface13may be different than a thickness of the portion of the insulation layer20that is disposed adjacent to the side walls15. For example, the latter thickness is smaller than the former thickness in order to keep the overall stress within the trench14at a low level.

In contrast to the embodiment shown inFIG.1, in this embodiment the capping layer50comprises sublayers51,52. Similar to the embodiment ofFIG.1, the first of the sublayers51, which may be referred to as the first capping sublayer, in this embodiment is a conformal layer covering the surface13and extending into the trench14for covering the sidewalls15and the bottom wall16. The first of the sublayers51in this embodiment is disposed immediately adjacent to the redistribution layer40and the metallization layer30. In alternative embodiments not shown, additional layers may be arranged in between said layers.

The second of the sublayers52, which may be referred to as the second capping sublayer, in this embodiment is a non-conformal layer covering the surface13without extending into the trench14. The second of the sublayers52in this embodiment is disposed immediately adjacent to the first of the sublayers51. In alternative embodiments not shown, the second of the sublayers52may be arranged in between the redistribution layer40and the first of the sublayers51. In other words, the one of the sublayers that is arranged closest to the surface13may be a non-conformal layer while the respective other of the sublayers is a conformal layer in said alternative embodiments.

In this embodiment, the sublayers51,52of the capping layer50serve the purpose of stress compensation similar to the sublayers21,22of the embodiment shown inFIG.1. For example, the first of the sublayers51is based on a TEOS precursor while the second of the sublayers52is based on the different silane precursor analogous to the embodiment shown inFIG.1. In this embodiment, a material of the capping layer50corresponds to the material of the insulation layer20, for instance.

FIG.3shows an alternative exemplary embodiment of an open TSV1. This embodiment combines the sublayer options of the embodiments shown inFIGS.1and2. In detail, both the insulation layer20and the capping layer50comprises sublayers21,22,51,52according to the embodiments described above. Forming both the insulation layer20and the capping layer50from sublayers21,22,51,52may serve the purpose of compensating for a substantial overall stress formed by the substrate body10and the remaining layers30,40.

For example, the material of the first capping sublayer51corresponds to the material of the first insulation sublayer21while the material of the second capping sublayer52corresponds to the material of the second insulation sublayer22. Alternatively, all sublayers21,22,51,52are different materials based on different precursors, for instance.

The embodiments shown in theFIGS.1to3as stated represent exemplary embodiments of the TSV1, therefore they do not constitute a complete list of all embodiments according to the improved concept. Actual TSV configurations may vary from the embodiments shown in terms of shape, size and materials, for example.

A TSV1according to one of the embodiments shown may be conveniently employed in a semiconductor device that require a low level of global stress in order to prevent cracking from strain formed from said stress. Possible applications include semiconductor devices in which a TSV according to the improved concept is employed for providing electrical connection of an integrated circuit through a substrate. Examples for such devices include ASICs that are commonly employed in sensors such as environmental sensors and image sensors.