Patent ID: 12191271

DETAILED DESCRIPTION

As described in the background art, during the flip-chip bonding, the semiconductor chip is prone to inclination or misalignment to cause the poor bonding.

According to the research, the existing semiconductor chip is usually flipped onto the substrate with thermo compression bonding, and during the thermo compression bonding, the semiconductor chip is inclined or misaligned for the deviated thermal pressure or non-uniform pressure distribution to cause the poor bonding.

In view of this, the present application provides a semiconductor structure and a forming method thereof. The present application can prevent misalignment or inclination of the semiconductor chip when the semiconductor chip is flipped onto the substrate, and thus prevent poor bonding.

To make the above objectives, features and advantages of the present application clearer, specific implementations of the present application will be described below in detail with reference to accompanying drawings. In detailed descriptions on embodiments of the present application, schematic views are not partially enlarged according to a general proportion for ease of descriptions. The schematic views merely serve as examples, rather than limitations to the scope of protection of the present application. In addition, dimensions in a three-dimensional (3D) space including a length, width and depth shall be provided in actual manufacture.

Referring toFIG.1, a wafer100is provided. A plurality of semiconductor chips101are formed on the wafer100. A plurality of metal pillars102and solder bumps103on top surfaces of the metal pillars102are formed on each of the semiconductor chips101.

The wafer100includes a plurality of chip regions arranged in rows and columns, and scribe lane regions located between the chip regions. A plurality of semiconductor chips101are formed in the chip regions. The wafer100may be made of monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon-germanium (GeSi) or silicon carbide (SiC); or may also be made of silicon on insulator (SOI) or germanium on insulator (GOI); or may further be made of another material such as gallium arsenide or other III-V compounds.

The semiconductor chips101each are provided therein with an IC (not shown in the figure). A plurality of pads (not shown in the figure) are provided on a surface of each of the semiconductor chips101. The pads on the surface of each of the semiconductor chips101are electrically connected to the IC in each of the semiconductor chips. The metal pillars102are correspondingly formed on the pads. The solder bumps103are formed on the top surfaces of the metal pillars102.

The metal pillars102are made of aluminum, nickel, tungsten, platinum, copper, titanium, chromium, tantalum, tin alloy, gold or silver. The solder bumps103are made of tin or tin alloy. The tin alloy may be one or more of tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony.

In some embodiments, a process for forming the metal pillars102and the solder bumps103includes: A passivation layer covering a surface of the wafer100is formed, openings exposing parts of surfaces of pads on the semiconductor chip101being formed in the passivation layer. Under bump metal (UBM) layers are formed on a surface of the passivation layer as well as on sidewalls and bottom surfaces of the openings, the UBM layers serving as conductive layers and seed layers in subsequent electroplating for formation of the metal pillars. Mask layers (such as photoresist layers) are formed on the UBM layers, openings exposing parts of surfaces of the UBM layers on the pads being formed in the mask layers. Metal is filled in the openings with electroplating to form the metal pillars102. The solder bumps103are formed on surfaces of the metal pillars102with screen printing. The mask layers are removed.

The solder bumps103formed are not reflowed to keep original shapes of the solder bumps103. The solder bumps103are square bumps.

Referring toFIG.2, a second covering film104covering the plurality of protruded metal pillars102and the solder bumps103on the top surfaces of the metal pillars are formed on the wafer100.

The second covering film104isolates and protects the metal pillars102.

In some embodiments, the second covering film104is made of an NCF. The NCF includes Si and an epoxy resin material.

In other embodiments, the second covering film104may be made of other resin materials.

Referring toFIG.3, the wafer100(referring toFIG.2) is diced to form a plurality of discrete semiconductor chips101.

On a surface of each of the semiconductor chips101, there are a plurality of protruded metal pillars102and solder bumps103on top surfaces of the metal pillars102, as well as a second covering film104covering the plurality of metal pillars102and the solder bumps103.

Referring toFIG.5, a substrate200is provided, a plurality of metal pads203being formed on a surface of the substrate200.

In some embodiments, the package substrate200is a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate, a metal substrate, a metal frame or an alloy frame. The substrate200may be a single-layer plate or a multi-layer plate.

In some embodiments, the substrate200includes a front side and a back side opposite to the front side. The plurality of metal pads203are formed on the front side of the substrate200. The metal pads203are subsequently connected to the solder bumps103on the semiconductor chip101(referring toFIG.3). A plurality of external pads204are formed on the back side of the substrate200. The plurality of external pads204may be configured to connect other semiconductor chips. The metal pads203on the front side of the substrate200may be connected to the external pads204on the back side of the substrate200through a metal connecting structure in the substrate200and/or on the surface of the substrate.

In some embodiments, a process for forming the metal pads203and the external pads204includes: Referring toFIG.4, metal layers201are formed on the front side and the back side of the substrate200. The metal layers201may be made of one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni. The metal layers201may be formed by sputtering, sputtering coating, electroplating, evaporation, etc. The metal layers201are formed on surfaces of the front side and the back side of the substrate200. Dry films are formed on surfaces of the metal layers on the front side and the back side of the substrate200. The dry films are photosensitive films and may be formed by lamination. The dry films are exposed and developed, such that first openings exposing a part of the surface of the metal layer on the front side of the substrate200are formed in the dry film on the front side, and second openings exposing a part of the surface of the metal layer on the back side of the substrate200are formed in the dry film on the back side. The exposed metal layers are removed by etching along the first openings and the second openings, thus forming the plurality of metal pads203on the front side of the substrate200and the plurality of external pads204(referring toFIG.5) on the back side of the substrate200. The dry films are removed.

Referring toFIG.8, a first covering film205covering the metal pads203and the surface of the substrate200is formed on the substrate200, a plurality of up-narrow and down-wide openings209being formed in the first covering film205, and bottoms of the up-narrow and down-wide openings209correspondingly exposing surfaces of the metal pads203.

In some embodiments, the first covering film205may be formed on the front side and the back side of the substrate200. A plurality of up-narrow and down-wide openings209are formed in the first covering film205on the front side of the substrate200. Bottoms of the up-narrow and down-wide openings209correspondingly expose surfaces of the metal pads203. Second openings210exposing parts of surfaces of the external pads204may be formed in the first covering film205on the back side of the substrate200.

The plurality of up-narrow and down-wide openings209in the first covering film205have the following functions: When the semiconductor chip101(referring toFIG.3) is subsequently flipped onto the substrate200, the solder bumps103on the metal pillars102of the semiconductor chip101are correspondingly stretched into the up-narrow and down-wide openings209. As the up-narrow and down-wide openings209limit the positions of the solder bumps103, the solder bumps103are bonded with the metal pads203more firmly, thus preventing misalignment or inclination of the semiconductor chip and preventing the poor bonding. In addition, owing to the up-narrow and down-wide openings209, the solder bumps103molten are limited within the up-narrow and down-wide openings209, for fear of a short circuit between adjacent metal pillars102due to solder overflow.

In some embodiments, the up-narrow and down-wide openings209each may include a first opening and a second opening that communicate with each other, the second opening is located on the first opening, and the second opening is narrower than the first opening.

In the embodiment, the first covering film205is a negative photoresist film. Referring toFIGS.6-8, a process for forming the up-narrow and down-wide openings209includes: Referring toFIG.6, the negative photoresist film205covering the metal pads203and the surface of the substrate200is formed on the substrate200. In some embodiments, the negative photoresist film205may be formed by lamination.

Referring toFIG.7, exposure21is performed on the negative photoresist film205. During the exposure, the negative photoresist film205directly over the metal pads203is not exposed (the negative photoresist film205is shielded by an opaque photomask pattern206), the negative photoresist film205over peripheral edge regions of the metal pads203is half exposed (the negative photoresist film205is shielded by a semi-transparent photomask pattern207. During the half exposure, only a part of the negative photoresist film205close to the surface is exposed), and the remaining negative photoresist film205is fully exposed (there no region shielded by the photomask pattern).

Referring toFIG.8, the negative photoresist film205is developed upon the exposure, the unexposed negative photoresist film is removed, and the up-narrow and down-wide openings209are formed in the remaining negative photoresist film205.

The up-narrow and down-wide openings209are formed simply with the above method.

In other embodiments, referring toFIGS.9-11, a method for forming the up-narrow and down-wide openings209in the first covering film205is further provided. The embodiment differs from the above embodiment in that: The first covering film205includes a first film layer205acovering the metal pads203and the surface of the substrate200and a second film layer205bon the first film layer205a, a material of the first film layer205ais different from a material of the second film layer205b, and there is a different process for forming the up-narrow and down-wide openings209.

Specifically, referring toFIG.9, the first film layer205acovering the metal pads203and the surface of the substrate200is formed. The second film layer205bis formed on the first film layer205a. The first film layer205aand the second film layer205bare formed into the first covering film205.

The material of the second film layer205bis different from the material of the first film layer205a, such that the second film layer205band the first film layer205ahave different etch selectivities in subsequent etching to form the up-narrow and down-wide openings. The first film layer205amay be made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, carbon, boron-doped silicon oxide, phosphorus-doped silicon oxide, boron nitride, silicon germanide, polycrystalline silicon, amorphous silicon or amorphous carbon. The second film layer205bmay be made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, carbon, boron-doped silicon oxide, phosphorus-doped silicon oxide, boron nitride, silicon germanide, polycrystalline silicon, amorphous silicon or amorphous carbon. The second film layer205band the first film layer205aare formed by deposition. In a specific embodiment, the first film layer205ais made of silicon oxide, and the second film layer205bis made of silicon nitride.

Referring toFIG.10, the second film layer205bis etched with anisotropic dry etching to form second openings209ain the second film layer205b. Bottoms of the second openings209aexpose a part of the surface of the first film layer205a.

The anisotropic dry etching includes anisotropic plasma etching.

Referring toFIG.11, the first film layer205aon the bottoms of the second openings209ais etched with isotropic wet etching along the second openings209ato form first openings209bin the first film layer205a. Widths of the first openings209bare greater than widths of the second openings209a. The first openings209band the second openings209aare formed into the up-narrow and down-wide openings209.

Referring toFIG.12andFIG.13, the semiconductor chip101is flipped onto the substrate200, such that the solder bumps103on the metal pillars102are correspondingly located in the up-narrow and down-wide openings209through the first covering film205, and the solder bumps103fill the up-narrow and down-wide openings209.

In some embodiments, after the semiconductor chip101is flipped onto the substrate200, thermo compression bonding is employed to ensure that the solder bumps103on the metal pillars102are correspondingly located in the up-narrow and down-wide openings209through the first covering film205, and the solder bumps103fill the up-narrow and down-wide openings209.

In some embodiments, the thermo compression bonding includes: The semiconductor chip101is clamped with a clamping head11and first heating is performed on the semiconductor chip101, such that the second covering film104is molten, and the solder bumps103on the metal pillars102are correspondingly located in the up-narrow and down-wide openings209through the first covering film205. The first heating is performed at a temperature less than a melting temperature of the solder bumps103. Second heating is performed on the semiconductor chip101through the clamping head11, such that the solder bumps103are molten to fill the up-narrow and down-wide openings209. A temperature of the second heating is higher than that of the first heating.

In some embodiments, the thermo compression bonding is performed at a pressure of 5-12 N for 3-5 s. The first heating is performed at the temperature of 60-70° C. The second heating is performed at the temperature of 220-250° C.

In other embodiments, there may further be a baking process and a reflow process, such that the solder bumps103are better molten to fill the up-narrow and down-wide openings209and achieve the higher bonding strength between the solder bumps103and the metal pads203.

An embodiment of the present application further provides a semiconductor structure. Referring toFIG.13, the semiconductor structure includes:a semiconductor chip101, a plurality of protruded metal pillars102and solder bumps103on top surfaces of the metal pillars102being formed on the semiconductor chip101;a substrate200, a plurality of metal pads203being formed on a surface of the substrate200; anda first covering film205located on the substrate200and covering the metal pads203and the surface of the substrate200, a plurality of up-narrow and down-wide openings209being formed in the first covering film205, and bottoms of the up-narrow and down-wide openings209correspondingly exposing surfaces of the metal pads203.

The semiconductor chip101is flipped onto the substrate200, such that the solder bumps103on the metal pillars102are correspondingly located in the up-narrow and down-wide openings209, and fill the up-narrow and down-wide openings209.

In some embodiments, the up-narrow and down-wide openings209each include a first opening and a second opening that communicate with each other, the second opening is located on the first opening, and a width of the second opening is smaller than a width of the first opening.

In some embodiments, the width of the second opening is ⅕-½ of the width of the first opening.

In some embodiments, the first covering film205is a negative photoresist film.

In some embodiments, referring toFIG.11, the first covering film205includes a first film layer205acovering the metal pads203and the surface of the substrate200and a second film layer205bon the first film layer205a. A material of the first film layer205ais different from a material of the second film layer205b. The up-narrow and down-wide openings209each include a second opening209ain the second film layer205band a first opening209bin the first film layer205a. The first opening209bcommunicates with the second opening209a. The first opening209bis wider than the second opening209a.

In some embodiments, referring also toFIG.13, a second covering film104covering the plurality of protruded metal pillars102is further provided between the semiconductor chip101and the substrate200.

In some embodiments, the second covering film104is made of an NCF.

In some embodiments, the substrate200includes a front side and a back side opposite to the front side. The plurality of metal pads203are formed on the front side of the substrate200. A plurality of external pads204are formed on the back side of the substrate200.

Preferable embodiments of the present application have been described above and are not intended to limit the present application. Those skilled in the art can make possible alterations and modifications on the technical solutions of the present application with the above methods and technical contents without departing from the spirit and scope of the present application. Accordingly, any simple changes, equivalent alterations and modifications made on the embodiments according to the technical essence of the present application without departing from the contents in the technical solution of the present application shall fall within the scope of protection in the technical solutions of the present application.