Patent ID: 12249585

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

The following disclosure provides for many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In the present disclosure, reference to the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Besides, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

FIG.1Aillustrates a cross-sectional view of a semiconductor device package1in accordance with some embodiments of the present disclosure. The semiconductor device package1includes a substrate10, an antenna layer11, circuit layers12,13, an electronic component14and a package body15.

The substrate10has a surface101and a surface102opposite to the surface101. The substrate10may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. In some embodiments, the substrate10may be a multi-layer substrate which includes a core layer and a conductive material and/or structure. For example, the substrate10includes a core portion, and may be in a wafer type, a panel type or a strip type. The substrate10may include one or more conductive layers10p1,10p2in proximity to, adjacent to, or embedded in and exposed at both surfaces (e.g., the surfaces101and102) of the substrate10. In some embodiments, the substrate10includes a through via10vpenetrating the substrate10to electrically connect the conductive layer10p1with the conductive layer10p2. In some embodiments, a protection layer10d(e.g., levelling layer) may be disposed on the surface101of the substrate10to cover the conductive layer10p1. For example, a lateral surface and a top surface of the conductive layer10p1may be covered by and in contact with the protection layer10d.

In some embodiments, the substrate10or a portion of the substrate10and the antenna layer11may serve as an antenna region. In some embodiments, the through via10vof the substrate10may serve as a feeding via (or feeding port) of the antenna region. The thickness of the substrate10may serve as the height of the resonator (or resonant cavity) for RF signal emitted by or received from the antenna region.

The antenna layer11is disposed on the surface102of the substrate10. In some embodiments, the antenna layer11is in contact with the substrate10. For example, the antenna layer11is in contact with the surface102of the substrate10. The antenna layer11includes one or more conductive layers11c1,11c2and one or more dielectric layers11d. A portion of the conductive layers11cis covered or encapsulated by the dielectric layer11dwhile another portion of the conductive layer11cis exposed from the dielectric layer11d. In some embodiments, the dielectric layer11dmay cover the conductive layer10p2of the substrate10. For example, the conductive layer10p2is in contact with the dielectric layer11d. In some embodiments, the conductive layers11c1,11c2define or include an antenna pattern. The conductive layers11c1,11c2may be electromagnetically coupled to the substrate10(e.g., to the conductive layer10p2) for signal transmission. In some embodiments, a protection layer11s(e.g., solder resist) is disposed on a surface of the dielectric layer11dfacing away from the substrate10to cover a portion of the conductive layer11c2.

In some embodiments, the dielectric layers11dmay include pre-impregnated composite fibers (e.g., pre-preg), Borophosphosilicate Glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, Undoped Silicate Glass (USG), any combination of two or more thereof, or the like. Examples of a pre-preg may include, but are not limited to, a multi-layer structure formed by stacking or laminating a number of pre-impregnated materials/sheets. In some embodiments, the conductive layers11c1,11c2are, or include, a conductive material such as a metal or metal alloy. Examples of the conductive material include gold (Au), silver (Ag), copper (Cu), platinum (Pt), Palladium (Pd), other metal(s) or alloy(s), or a combination of two or more thereof. There may be any number of the dielectric layers11dand conductive layers11c1,11c2depending on different design specifications.

The circuit layer12is disposed on the surface101of the substrate10. In some embodiments, the circuit layer12is connected to the protection layer10dthrough an adhesive layer10h(e.g., a tape or a die attach film (DAF)). The circuit layer12includes one or more conductive layers12cand one or more dielectric layers12d. A portion of the conductive layer12cis covered or encapsulated by the dielectric layer12dwhile another portion of the conductive layer12cis exposed from the dielectric layer12d. In some embodiments, the circuit layer12may include conductive vias12v(e.g., through vias) penetrating the dielectric layer12d, the adhesive layer10hand the protection layer10dto be electrically connected to the conductive layer10p1. For example, the conductive vias12vare in contact with the conductive layer10p1. In some embodiments, the conductive layer12cdefines or includes an antenna pattern. The conductive layer12cmay be electrically connected to the substrate10(e.g., to the conductive layer10p1) through the conductive via12vfor signal transmission.

In some embodiments, the dielectric layers12dmay include pre-impregnated composite fibers (e.g., pre-preg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination of two or more thereof, or the like. Examples of a pre-preg may include, but are not limited to, a multi-layer structure formed by stacking or laminating a number of pre-impregnated materials/sheets. In some embodiments, the dielectric layer12dand the dielectric layer11dmay include the same material. Alternatively, the dielectric layer12dand the dielectric layer11dmay include different materials. In some embodiments, the conductive layer12cand the conductive vias12vare, or include, a conductive material such as a metal or metal alloy. Examples of the conductive material include Au, Ag, Cu, Pt, Pd, other metal(s) or alloy(s), or a combination of two or more thereof. There may be any number of the dielectric layers12dand conductive layers12cdepending on different design specifications.

In some embodiments, as shown inFIG.1A, a portion of the antenna layer11and a portion of the conductive layer10p2of the substrate10encircled by a dotted-line square may define an antenna A1, and the other portion of the antenna layer11and the circuit layer12encircled by another dotted-line square may define another antenna A2. In some embodiments, the antenna A1and the antenna A2may include different types of antenna. Alternatively, the antenna A1and the antenna A2may include the same type of antenna. In some embodiments, the antenna A1and the antenna A2may include different operation frequencies or bandwidths. Alternatively, the antenna A1and the antenna A2may include the same operation frequency or bandwidth.

The circuit layer13(or a routing layer) is disposed on the surface101of the substrate10. The circuit layer13is disposed adjacent to the circuit layer12. For example, as shown inFIG.1B(which illustrates a top view of the semiconductor device package1as shown inFIG.1A, in accordance with some embodiments of the present disclosure), the circuit layer13and the circuit layer12are disposed side-by-side on the surface101of the substrate10. For example, as shown inFIG.1C(which illustrates a top view of the semiconductor device package1as shown inFIG.1A, in accordance with some embodiments of the present disclosure), the circuit layer12surrounds the circuit layer13. For example, as shown inFIG.1D(which illustrates a top view of the semiconductor device package1as shown inFIG.1A, in accordance with some embodiments of the present disclosure), the circuit layer13is disposed between the circuit layers12. In other words, the circuit layer13is sandwiched by the circuit layers12. In some embodiments, the circuit layer12and the circuit layer13are disposed at the same altitude with respect to the substrate10(or the antenna layer11).

Referring toFIG.1A, the circuit layer13is connected to the protection layer10dthrough the adhesive layer10h. The circuit layer13includes one or more conductive layers13cand one or more dielectric layers13d. A portion of the conductive layer13cis covered or encapsulated by the dielectric layer13dwhile another portion of the conductive layer13cis exposed from the dielectric layer13d. In some embodiments, the circuit layer13may include conductive vias13vpenetrating the dielectric layer13d, the adhesive layer10hand the protection layer10dto be electrically connected to the conductive layer10p1. The conductive layer13cmay be electrically connected to the substrate10(e.g., to the conductive layer10p1) through the conductive via13vfor signal transmission. In some embodiments, the circuit layer13is electrically connected to the circuit layer12through the substrate10(e.g., through the conductive layer10p1).

In some embodiments, the dielectric layer13dmay include polymers or any other suitable materials. In some embodiments, a Dk and a Df of the dielectric layer13dis higher than a Dk and a Df of the dielectric layers11d,12d. For example, the dielectric layers11d,12dhave a Dk less than approximately 5. The dielectric layers11d,12dhave a Dk less than approximately approximately 3. The dielectric layers11d,12dhave a Df less than approximately 0.005. The dielectric layers11d,12dhave a Df less than approximately 0.003.

In some embodiments, a rigidity of the dielectric layer13dis higher than a rigidity of the dielectric layers11d,12d. In some embodiments, a coefficient of thermal expansion (CTE) of the dielectric layers11d,12dis greater than a CTE of the dielectric layer13d. For example, the CTE of the dielectric layers11d,12dis from about 120 K−1to about 150 K−1, and the CTE of the dielectric layer13dis from about 20 K−1to about 50 K−1. In some embodiments, the dielectric layer13dmay include fibers, and the dielectric layers11dand12ddo not include fibers.

In some embodiments, the conductive layer13cis, or includes, a conductive material such as a metal or metal alloy. Examples of the conductive material include Au, Ag, Cu, Pt, Pd, other metal(s) or alloy(s), or a combination of two or more thereof. There may be any number of the dielectric layers13dand conductive layers13cdepending on different design specifications. In some embodiments, a line/space (L/S or pitch or density) of the conductive layer12cof the circuit layer12is higher than a L/S of the conductive layer13cof the circuit layer13.

In some embodiments, a thickness of the circuit layer13is substantially the same as a thickness of the circuit layer12. Alternatively, the thickness of the circuit layer13is different from the thickness of the circuit layer12. In some embodiments, the number of the dielectric layers13dand conductive layers13cof the circuit layer13is the same as the number of the dielectric layers12dand conductive layers12cof the circuit layer12. Alternatively, the number of the dielectric layers13dand conductive layers13cof the circuit layer13is different from the number of the dielectric layers12dand conductive layers12cof the circuit layer12.

The electronic component14is disposed on the circuit layer13and electrically connected to the circuit layer13, and electrical connection may be attained by way of flip-chip or wire-bond techniques. The electronic component14may be a chip or a die including a semiconductor substrate, one or more integrated circuit devices and one or more overlying interconnection structures therein. The integrated circuit devices may include active devices such as transistors and/or passive devices such resistors, capacitors, inductors, or a combination thereof.

The package body15is disposed on the circuit layer12and the circuit layer13and encapsulates the electronic component14. In some embodiments, the package body15includes an epoxy resin having fillers dispersed therein.

In some comparative embodiments, an antenna layer having a dielectric layer with a relatively low Dk and Df is directly disposed on a circuit layer having a dielectric layer with a relatively high Dk and Df. However, such unbalanced structure would cause a warpage issue (e.g., the warpage is larger than 5 millimeters) during the manufacturing process, which may result in the failure of the semiconductor device package. In accordance with the embodiments, as shown inFIGS.1A to1D, there are two kinds of circuit layers (or routing layers) disposed over the antenna layer11, one (i.e., the circuit layer12) having the dielectric layer12dwith the Dk and Df similar or identical to the Dk and Df of the dielectric layer11dof the antenna layer11, and the other (i.e., circuit layer13) having a relatively high Dk and Df to provide a higher rigidity for the semiconductor device package1. The warpage issue may be eliminated or mitigated.

In addition, in some embodiments of the present disclosure, since the dielectric layer12dof the circuit layer12does not have fibers, a pitch of the conductive via12vof the circuit layer12is less than a pitch of the conductive via13vof the circuit layer13. Hence, the density (or L/S) of the conductive layer12cof the circuit layer12is higher than the density of the conductive layer13cof the circuit layer13. This would reduce the number of the conductive layers13cof the circuit layer13required for signal transmission, and the thickness of the semiconductor device package1can be reduced as well. In some embodiments, in the case that a ratio of the area of the circuit layer12to the area of the circuit layer13is about 2:3, the number of the conductive layer13cof the circuit layer13can be reduced by 1 layer. In the case that the ratio of the area of the circuit layer12to the area of the circuit layer13is about 1:1, the number of the conductive layer13cof the circuit layer13can be reduced by 2 layers. In some embodiments, the ratio of the area of the circuit layer12to the area of the circuit layer13is in a ranger from about 2:3 to about 7:3. In some embodiments, a thickness of the semiconductor device package1is equal to or less than 950 micrometers.

FIG.2Aillustrates a cross-sectional view of a semiconductor device package2A in accordance with some embodiments of the present disclosure. The semiconductor device package2A is similar to the semiconductor device package1as shown inFIG.1A, except that inFIG.2A, the electronic component14is disposed on the circuit layer12and electrically connected to the circuit layer12.

As shown inFIG.2B(which illustrates a top view of the semiconductor device package2A as shown inFIG.2A, in accordance with some embodiments of the present disclosure), the circuit layer13and the circuit layer12are disposed side-by-side on the surface101of the substrate10. As shown inFIG.2C(which illustrates a top view of the semiconductor device package2A as shown inFIG.2A, in accordance with some embodiments of the present disclosure), the circuit layer13surrounds the circuit layer12. As shown inFIG.2D(which illustrates a top view of the semiconductor device package2A as shown inFIG.2A, in accordance with some embodiments of the present disclosure), the circuit layer12is disposed between the circuit layers13. In other words, the circuit layer12is sandwiched by the circuit layers13.

FIG.2Eillustrates a cross-sectional view of a semiconductor device package2E in accordance with some embodiments of the present disclosure. The semiconductor device package2E is similar to the semiconductor device package2A as shown inFIG.2A, except that inFIG.2A, the circuit layer12is electrically connected to the circuit layer13through a conductive layer10p3disposed on the surface101of the substrate10.

FIG.3illustrates a cross-sectional view of a semiconductor device package3in accordance with some embodiments of the present disclosure. The semiconductor device package3is similar to the semiconductor device package1as shown inFIG.1A, and the differences therebetween are described below.

As shown inFIG.3, a portion15aof the package body15is disposed between the circuit layer12and the circuit layer13. For example, the circuit layer12and the circuit layer13are spaced apart from each other through the package body15. For example, a lateral surface of the circuit layer12facing the circuit layer13is in contact with the portion15aof the package body15. For example, a lateral surface of the circuit layer13facing the circuit layer12is in contact with the portion15aof the package body15. Using the package body15covering the circuit layer12and the circuit layer13and extending between the circuit layer12and the circuit layer13may prevent the circuit layer12from being peeled off from the circuit layer13(e.g., delamination issue). In some embodiments, a thickness of the portion15aof the package body15is equal to or greater than 150 micrometers. For example, a distance between the circuit layer12and the circuit layer13is equal to or greater than 150 micrometers.

FIG.4Aillustrates a cross-sectional view of a semiconductor device package4A in accordance with some embodiments of the present disclosure. The semiconductor device package4A is similar to the semiconductor device package3as shown inFIG.3, and the differences therebetween are described below.

A protection layer30d(e.g., levelling layer) is disposed on the surface102of the substrate10to cover the conductive layer10p2. For example, a lateral surface and a top surface of the conductive layer10p2may be covered by and in contact with the protection layer30d.

The antenna layer11is connected to the protection layer30dthrough an adhesive layer30h(e.g., a tape or a DAF). The antenna layer11may include conductive vias liv (e.g., through vias) penetrating the dielectric layer11d, the adhesive layer30hand the protection layer30dto be electrically connected to the conductive layer10p2. For example, the conductive vias liv are in contact with the conductive layer10p2. The conductive layer11c1may be electrically connected to the substrate10(e.g., to the conductive layer10p2) through the conductive via11vfor signal transmission. In other embodiments, the conductive via liv may be omitted, and the signal transmission may be achieved by magnetically coupling.

FIG.4Billustrates a cross-sectional view of a semiconductor device package4B in accordance with some embodiments of the present disclosure. The semiconductor device package4B is similar to the semiconductor device package4A as shown inFIG.4B, and the differences therebetween are described below.

The package body15further covers lateral surfaces of the circuit layers12,13, the substrate10and the antenna layer11. In some embodiments, a distance between the lateral surface of the circuit layer12or13and the lateral surface of the package body15is in a range from about 2 millimeters to about 3 millimeters.

FIG.5A,FIG.5B,FIGS.5C and5Dare cross-sectional views of a semiconductor device package at various stages of fabrication, in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure. In some embodiments, the method illustrated inFIG.5A,FIG.5B,FIGS.5C and5Dmay be used to manufacture the semiconductor device package1as shown inFIG.1A.

Referring toFIG.5A, a substrate10(or core) is provided. Conductive layers10p1and10p2are disposed on the surfaces101and102respectively. One or more through vias10vpenetrate the substrate10to electrically connect the conductive layer10p1with the conductive layer10p2.

Referring toFIG.5B, an antenna layer11including conductive layers11c1,11c2, a dielectric layer11dand a protection layer11s(e.g., solder resist) is formed on the surface102of the substrate10. In some embodiments, the antenna layer11may be formed on the surface102of the substrate10by, for example, lamination or any other suitable processes. A protection layer10d(e.g., levelling layer) is formed on the surface101of the substrate10to cover the conductive layer10p1.

Referring toFIG.5C, a circuit layer12including one or more conductive layers12c, conductive vias12viand dielectric layers12dis connected to the protection layer10dthrough an adhesive layer10h(e.g., a tape or a DAF). The conductive vias12viare electrically connected to the conductive layers12cat different layers. A circuit layer13including a conductive layer13c, a conductive via13viand a dielectric layer13dis connected to the protection layer10dthrough an adhesive layer10h. The conductive vias13viare electrically connected to the conductive layers13cat different layers.

Referring toFIG.5D, one or more conductive vias (e.g., through vias)12vare formed to penetrate the dielectric layer12d, the adhesive layer10hand the protection layer10dto be electrically connected to the conductive layer10p1. One or more conductive vias (e.g., through vias)13vare formed to penetrate the dielectric layer13d, the adhesive layer10hand the protection layer10dto be electrically connected to the conductive layer10p1.

An electronic component14is disposed on the circuit layer13and electrically connected to the circuit layer13. A package body15is then formed on the circuit layers12and13to cover the electronic component14by, for example, molding or any other suitable techniques.

FIG.6A,FIGS.6B and6Care cross-sectional views of a semiconductor device package at various stages of fabrication, in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure. In some embodiments, the method illustrated inFIG.6A,FIGS.6B and6Cmay be used to manufacture the semiconductor device package4A as shown inFIG.4A. In some embodiments, the operation inFIG.6Amay be carried out after the operation as shown inFIG.5A.

Referring toFIG.6A, a protection layer30d(e.g., levelling layer) is formed on the surface102of the substrate10to cover the conductive layer10p2. An antenna layer11including conductive layers11c1,11c2, a dielectric layer11dand a protection layer11s(e.g., solder resist) is connected to the protection layer30dthrough an adhesive layer30h(e.g., a tape or a DAF). A protection layer10d(e.g., levelling layer) is formed on the surface101of the substrate10to cover the conductive layer10p1.

Referring toFIG.6B, a circuit layer12including one or more conductive layers12c, conductive vias12viand dielectric layers12dis connected to the protection layer10dthrough an adhesive layer10h(e.g., a tape or a DAF). The conductive vias12viare electrically connected to the conductive layers12cat different layers. A circuit layer13including a conductive layer13c, a conductive via13viand a dielectric layer13dis connected to the protection layer10dthrough an adhesive layer10h. The conductive vias13viare electrically connected to the conductive layers13cat different layers. The circuit layer12and the circuit layer13are spaced apart from each other. For example, there is a gap15hbetween the circuit layer12and the circuit layer13.

Referring toFIG.6C, one or more conductive vias (e.g., through vias)12vare formed to penetrate the dielectric layer12d, the adhesive layer10hand the protection layer10dto be electrically connected to the conductive layer10p1. One or more conductive vias (e.g., through vias)13vare formed to penetrate the dielectric layer13d, the adhesive layer10hand the protection layer10dto be electrically connected to the conductive layer10p1.

An electronic component14is disposed on the circuit layer13and electrically connected to the circuit layer13. A package body15is then formed on the circuit layers12and13to cover the electronic component14by, for example, molding or any other suitable techniques. The package body15is further formed within the gap15hbetween the circuit layer12and the circuit layer13. For example, a portion15aof the package body15is disposed between the circuit layer12and the circuit layer13. For example, a lateral surface of the circuit layer12facing the circuit layer13is in contact with the portion15aof the package body15, and a lateral surface of the circuit layer13facing the circuit layer12is in contact with the portion15aof the package body15.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “left,” “right” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

As used herein, the terms “approximately”, “substantially”, “substantial” and “about” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (m) of lying along the same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values.

The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.