Patent ID: 12213310

DETAILED DESCRIPTION

FIG.1is a layout view illustrating a semiconductor device according to an example embodiment.

Referring toFIG.1, a semiconductor device10may include first and second semiconductor structures S1and S2stacked in a vertical direction. The first semiconductor structure S1may be configured as a peripheral circuit structure and may include a row decoder DEC, a page buffer PB, and other peripheral circuits PC. The second semiconductor structure S2may be configured as a memory cell structure and may include memory cell arrays MCA and first and second through interconnection regions TR1and TR2.

In the first semiconductor structure S1, the row decoder DEC may generate and transmit driving signals of a word line by decoding an input address. The page buffer PB may be connected to the memory cell arrays MCA through bit lines and may read data stored in the memory cells. The other peripheral circuit PC may be configured as a region including a control logic and a voltage generator, and may include, e.g., a latch circuit, a cache circuit, and/or a sense amplifier. The first region R1may further include a pad region. In this case, the pad region may include an electrostatic discharge (ESD) device or a data input/output circuit.

At least a portion of the various circuit regions DEC, PB, and PC in the first semiconductor structure S1may be disposed below the memory cell arrays MCA of the second semiconductor structure S2. For example, the page buffer PB and/or other peripheral circuits PC may be disposed below the memory cell arrays MCA to overlap the memory cell arrays MCA. However, circuits included in the first semiconductor structure S1and the arrangement form thereof may be varied, and accordingly, circuits overlapping the memory cell arrays MCA may also be varied.

The second semiconductor structure S2may have first to third regions R1, R2, and R3. The first and second regions R1and R2may be configured as a region in which a substrate may be disposed such that the memory cell arrays MCA may be disposed. The third region R3may be configured as a region on an external side of the substrate. The first region R1may be configured as a region in which the memory cells are disposed. The second region R2may be configured to electrically connect word lines to the circuit regions DEC, PB, and PC of the first semiconductor structure S1.

In the second semiconductor structure S2, the memory cell arrays MCA may be disposed to be spaced apart from each other. The four memory cell arrays MCA are disposed inFIG.1, but in example embodiments, the number and the arrangement form of the memory cell arrays MCA disposed on the second semiconductor structure S2may be varied.

The first and second through interconnection regions TR1and TR2may include an interconnection structure penetrating the second semiconductor structure S2and connected to the first semiconductor structure S1. The first through interconnection regions TR1may be disposed in the memory cell arrays MCA in the first region R1by predetermined intervals. For example, an interconnection structure electrically connected to the page buffer PB of the first semiconductor structure S1may be included. The second through interconnection regions TR2may be disposed in at least one edge region of the memory cell arrays MCA in the second region R2, and may include an interconnection structure such as a contact plug electrically connected to the row decoder DEC of the first semiconductor structure S1. The number of the second through interconnection regions TR2may be larger than the number of the first through interconnection regions TR1, but the shape, the number, and the position of the first and second through interconnection regions TR1and TR2may be varied in example embodiments.

In the second semiconductor structure S2, the nitride layer NL may remain in a cell region insulating layer190(seeFIG.3A) and/or below the cell region insulating layer190in the third region R3. The nitride layer NL may remain in an external side edge region of the second region R2in contact with the third region R3. This configuration will be described in greater detail below with reference toFIGS.2to3B.

FIG.2is a plan view illustrating a semiconductor device according to an example embodiment.FIGS.3A and3Bare cross-sectional views illustrating a semiconductor device according to an example embodiment.FIG.3Ais a cross-sectional view taken along line I-I′ inFIG.2, andFIG.3Bis a cross-sectional view taken along line II-IF inFIG.2.FIGS.4A to4Care enlarged views illustrating a partial region of a semiconductor device according to an example embodiment.FIG.4Ais an enlarged view illustrating region “A” inFIG.3A,FIG.4Bis an enlarged view illustrating region “B” inFIG.3A, andFIG.4Cis an enlarged view illustrating region “C” inFIG.3A.

Referring toFIGS.2to3B, the semiconductor device100may include a peripheral circuit region PERI, which may be a first semiconductor structure including a first substrate201, and a memory cell region CELL, which may be a second semiconductor structure including a second substrate101. The memory cell region CELL may be disposed above the peripheral circuit region PERI. In another implementation, in example embodiments, the memory cell region CELL may be disposed below the peripheral circuit region PERI.

The peripheral circuit region PERI may include the first substrate201, source/drain regions205and device separation layers210in the first substrate201, circuit devices220disposed on the first substrate201, circuit contact plugs270, circuit interconnection lines280, and a peripheral region insulating layer290.

The first substrate201may have an upper surface extending in the x direction and the y direction. An active region may be defined by the device separation layers210on the first substrate201. The source/drain regions205including impurities may be disposed in a portion of the active region. The first substrate201may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate201may be provided as a bulk wafer or an epitaxial layer.

The circuit devices220may include a planar transistor. Each of the circuit devices220may include a circuit gate dielectric layer222, a spacer layer224, and a circuit gate electrode225. The source/drain regions205may be disposed in the first substrate201on both sides of the circuit gate electrode225.

The peripheral region insulating layer290may be disposed on the circuit device220on the first substrate201. The circuit contact plugs270may penetrate the peripheral region insulating layer290and may be connected to the source/drain regions205. An electrical signal may be applied to the circuit device220by the circuit contact plugs270. In a region not illustrated, the circuit contact plugs270may also be connected to the circuit gate electrode225. The circuit interconnection lines280may be connected to the circuit contact plugs270and may be disposed in a plurality of layers.

The memory cell region CELL may include a second substrate101having a first region R1and a second region R2, gate electrodes130stacked on the second substrate101, interlayer insulating layers120alternately stacked with the gate electrodes130, channel structures CH disposed to penetrate the stack structure of the gate electrodes130, first and second separation regions MS1and MS2extending by penetrating the stack structure of the gate electrodes130, contact plugs170extending by penetrating the gate electrodes130in the second region R2, and through plugs175disposed in a third region R3disposed on an external side of the second substrate101.

The memory cell region CELL may further include first and second contact plug insulating layers160and165surrounding the contact plugs170, first and second through plug insulating layers180and185surrounding the through plugs175, first and second nitride layers150L and150U in contact with the first and second through plug insulating layers180and185, respectively, and first and second dummy gate electrodes131D and132D.

The memory cell region CELL may include a first horizontal conductive layer102on the first region R1, a horizontal insulating layer110disposed in parallel to the first horizontal conductive layer102on the second region R2, a second horizontal conductive layer104on the first horizontal conductive layer102and the horizontal insulating layer110, a substrate insulating layer121penetrating the second substrate101, upper separation regions SS penetrating a portion of the stack structure of the gate electrodes130, dummy channel structures DCH disposed to penetrate the stack structure of the gate electrodes130in the second region R2, a cell region insulating layer190, and cell interconnection lines195.

The first region R1of the second substrate101may be configured as a region in which the gate electrodes130may be vertically stacked and the channel structures CH may be disposed, and memory cells may be disposed in the first region R1. The second region R2may be configured as a region in which the gate electrodes130may extend by different lengths, and may be configured to electrically connect the memory cells to the peripheral circuit region PERI. The second region R2may be disposed on at least one end of the first region R1in at least one direction, in the x direction, for example.

The second substrate101may have an upper surface extending in the x direction and the y direction. The second substrate101may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate101may further include impurities. The second substrate101may be provided as a polycrystalline semiconductor layer or an epitaxial layer such as a polycrystalline silicon layer.

The first and second horizontal conductive layers102and104may be stacked in order on an upper surface of the first region R1of the second substrate101. The first horizontal conductive layer102may not extend to the second region R2of the second substrate101. The second horizontal conductive layer104may extend to the second region R2.

The first horizontal conductive layer102may function as a portion of a common source line of the semiconductor device100, and may function as a common source line together with the second substrate101, for example. Referring to the enlarged view inFIG.3B, the first horizontal conductive layer102may be directly connected to the channel layer140around the channel layer140.

The second horizontal conductive layer104may be in contact with the second substrate101in regions in which the first horizontal conductive layer102and the horizontal insulating layer110are not disposed. The second horizontal conductive layer104may be bent to cover ends of the first horizontal conductive layer102or the horizontal insulating layer110in the regions and may extend onto the second substrate101.

The first and second horizontal conductive layers102and104may include a semiconductor material. For example, both the first and second horizontal conductive layers102and104may include polycrystalline silicon. In this case, at least the first horizontal conductive layer102may be a doped layer, and the second horizontal conductive layer104may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer102. However, the second horizontal conductive layer104may be replaced with an insulating layer.

The horizontal insulating layer110may be disposed on the second substrate101side by side with the first horizontal conductive layer102in at least a portion of the second region R2. The horizontal insulating layer110may include first and second horizontal insulating layers111and112alternately stacked on the second region R2of the second substrate101. The horizontal insulating layer110may be a layer remaining after a portion thereof are replaced with the first horizontal conductive layer102in a process of manufacturing the semiconductor device100.

The horizontal insulating layer110may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layers111and the second horizontal insulating layers112may include different insulating materials. For example, the first horizontal insulating layers111may be formed of the same material as a material of the interlayer insulating layers120, and the second horizontal insulating layer112may be formed of a material different from a material of the interlayer insulating layers120.

The substrate insulating layer121may extend in the z direction and may penetrate the second substrate101, the horizontal insulating layer110, and the second horizontal conductive layer104in the second region R2. The substrate insulating layer121may be disposed to surround each of the contact plugs170. Accordingly, the contact plugs170connected to the different gate electrodes130may be electrically separated from each other. The substrate insulating layer121may also be disposed on the third region R3, an external side of the second substrate101. The substrate insulating layer121may include, e.g., silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

The gate electrodes130may be vertically stacked and spaced apart from each other on the second substrate101and may form a stack structure. The gate electrodes130may include lower gate electrodes130L forming a gate of a ground select transistor, memory gate electrodes130M forming a plurality of memory cells, and upper gate electrodes130U forming gates of string select transistors. The number of the memory gate electrodes130M forming the memory cells may be determined according to capacity of the semiconductor device100. In some example embodiments, each number of the upper and lower gate electrodes130U and130L may be 1 to 4 or more, and may have the same structure as or a different structure from that of the memory gate electrodes130M. In some example embodiments, the gate electrodes130may further include a gate electrode130disposed above the upper gate electrodes130U and/or below the lower gate electrodes130L and forming an erase transistor used in an erase operation using a gate induced drain leakage (GIDL) phenomenon. Also, a portion of the gate electrodes130, the memory gate electrodes130M adjacent to the upper or lower gate electrodes130U and130L, e.g., may be dummy gate electrodes.

The gate electrodes130may be vertically stacked and spaced apart from each other on the first region R1and may extend from the first region R1to the second region R2by different lengths and may form a stepped structure in a staircase shape. Referring toFIG.3A, the gate electrodes130may form a stepped structure between the gate electrodes130in the x direction, and may also have a stepped structure in the y direction.

Due to the stepped structure, the lower gate electrode130L may extend longer than the upper gate electrode130U such that the gate electrodes130may have regions exposed upwardly from the interlayer insulating layers120, and the regions may be referred to as pad regions130P. In each of the gate electrodes130, the pad region130P may include an end in the x direction. The pad region130P may correspond to a portion of an uppermost gate electrode130among the gate electrodes130forming the stack structure in the second region R2of the second substrate101. The gate electrodes130may be connected to the contact plugs170in the pad regions130P.

The gate electrodes130may have an increased thickness in the pad regions130P. The thickness of each of the gate electrodes130may increase in such a manner that a level of the lower surface thereof may be constant and a level of an upper surface thereof may be increased. Referring toFIG.4A, the gate electrodes130may extend from the first region R1toward the second region R2by a first thickness T1, and may have a second thickness T2greater than the first thickness T1in the pad regions130P marked by a dotted line inFIG.4A. The second thickness T2may range from about 150% to about 210% of the first thickness T1.

The gate electrodes130may be separated from each other in the y direction by a first separation region MS1extending in the x direction. The gate electrodes130between a pair of first separation regions MS1may form one memory block, but the range of the memory block is not limited thereto. The gate electrodes130may include a metal material, such as tungsten (W), for example. In some example embodiments, the gate electrodes130may include polycrystalline silicon or a metal silicide material.

The interlayer insulating layers120may be disposed between the gate electrodes130. Similarly to the gate electrodes130, the interlayer insulating layers120may be spaced apart from each other in a direction perpendicular to the upper surface of the second substrate101and may extend in the x direction. The interlayer insulating layers120may include an insulating material such as silicon oxide or silicon nitride.

The first and second separation regions MS1and MS2may be disposed to penetrate the gate electrodes130and may extend in the x direction. The first and second separation regions MS1and MS2may be disposed parallel to each other. The first and second separation regions MS1and MS2may penetrate the entire gate electrodes130stacked on the second substrate101and may be connected to the second substrate101. The first separation regions MS1may extend as a single region in the x direction, and the second separation regions MS2may intermittently extend between a pair of first separation regions MS1or may be disposed only in a partial region. However, the arrangement order and the number of the first and second separation regions MS1and MS2are not limited to the examples illustrated inFIG.2. Referring toFIG.3B, a separation insulating layer105may be disposed in the first and second separation regions MS1and MS2. The separation insulating layer105may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, for example.

Referring toFIG.2, the upper separation regions SS may extend in the x direction between the first separation regions MS1and the second separation regions MS2in the first region R1. Referring toFIG.3B, the upper separation regions SS may separate three gate electrodes130including the upper gate electrodes130U from each other in the y direction. However, the number of gate electrodes130separated by the upper separation regions SS may be varied in example embodiments. The upper gate electrodes130U separated by the upper separation regions SS may form different string select lines. The upper separation insulating layer103may be disposed in the upper separation regions SS. The upper separation insulating layer103may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, for example.

Referring toFIG.2, each of the channel structures CH may form a single memory cell string, and may be spaced apart from each other and may form rows and columns on the first region R1. The channel structures CH may be disposed to form a grid pattern or may be disposed in a zigzag pattern in one direction. The channel structures CH may have a columnar shape, and may have an inclined side surface having a width decreasing towards the second substrate101depending on an aspect ratio.

The channel structures CH may include first and second channel structures CH1and CH2vertically stacked, as for the example embodiment illustrated inFIG.3A. In the channel structures CH, first channel structures CH1penetrating the lower stack structures of the gate electrodes130may be connected to second channel structures CH2penetrating the upper stack structures of the gate electrodes130, and may have a bent portion due to a difference in width in a connection region. However, the number of channel structures stacked in the z direction may be varied.

Referring to the enlarged view inFIG.3B, a channel layer140may be disposed in the channel structures CH. In the channel structures CH, the channel layer140may be formed in an annular shape surrounding a channel filling insulating layer147therein. The channel layer140may be connected to the first horizontal conductive layer102in a lower portion. The channel layer140may include a semiconductor material such as polycrystalline silicon or single crystal silicon.

The gate dielectric layer145may be disposed between the gate electrodes130and the channel layer140. Although not specifically illustrated, the gate dielectric layer145may include a tunneling layer, a charge storage layer, and a blocking layer stacked in order from the channel layer140. The tunneling layer may tunnel charges to the charge storage layer, and may include, e.g., silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In some example embodiments, at least a portion of the gate dielectric layer145may extend in a horizontal direction along the gate electrodes130. The channel pad149may be disposed only on an upper end of the upper second channel structure CH2. The channel pads149may include, e.g., doped polycrystalline silicon.

The channel layer140, the gate dielectric layer145, and the channel filling insulating layer147may be connected to each other between the first channel structure CH1and the second channel structure CH2. An upper interlayer insulating layer125having a relatively great thickness may be disposed between the first channel structure CH1and the second channel structure CH2, that is, between the lower stack structure and the upper stack structure. However, the shapes of the interlayer insulating layers120and the upper interlayer insulating layer125may be varied.

The dummy channel structures DCH may be spaced apart from each other and may form rows and columns in the second region R2. The dummy channel structures DCH may have a size larger than that of the channel structures CH on a plan view, but example embodiments are not limited thereto. The dummy channel structures DCH may be further disposed in a portion of the first region R1adjacent to the second region R2. The dummy channel structures DCH may not be electrically connected to upper interconnection structures, and may not form a memory cell string in the semiconductor device100, differently from the channel structures CH.

The dummy channel structures DCH may have the same structure as or a different structure from the channel structures CH. When the dummy channel structures DCH are formed together with the channel structures CH, the dummy channel structures DCH may have the same structure as the channel structures CH. When the dummy channel structures DCH are formed using a portion of a process of forming the contact plugs170, the dummy channel structures DCH may have a structure different from of the channel structures CH. In this case, e.g., the dummy channel structures DCH may have a structure filled with an insulating material such as oxide.

The contact plugs170may penetrate the uppermost gate electrodes130and the first contact plug insulating layers160disposed below the uppermost gate electrodes130in the second region R2, and may be connected to the pad regions130P of the gate electrodes130. The contact plugs170may penetrate at least a portion of the cell region insulating layer190and may be connected to each of the pad regions130P of the gate electrodes130exposed upwardly. The contact plugs170may penetrate the second substrate101, the second horizontal conductive layer104, and the horizontal insulating layer110in a lower portion of the gate electrodes130and may be connected to the circuit interconnection lines280in the peripheral circuit region PERI. The contact plugs170may be spaced apart from the second substrate101, the second horizontal conductive layer104, and the horizontal insulating layer110by the substrate insulating layer121.

Referring toFIG.4A, each of the contact plugs170may include a vertical extension portion170V extending in the z direction and a horizontal extension portion170H extending horizontally from the vertical extension portion170V and in contact with the pad regions130P. The vertical extension portion170V may have a cylindrical shape of which a width may decrease toward the second substrate101due to an aspect ratio. The horizontal extension portion170H may be disposed along a circumference of the vertical extension portion170V, and may extend from a side surface of the vertical extension portion170V to the other end by a first length L1. The first length L1may be shorter than a second length L2of the lower first contact plug insulating layers160.

Referring toFIG.4C, the contact plugs170may be surrounded by the substrate insulating layer121so as to be electrically separated from the second substrate101. A region including a lower end of the contact plugs170may be surrounded by pad layers285on the circuit interconnection lines280. The pad layers285may be configured to protect the circuit interconnection lines280during the process of manufacturing the semiconductor device100, and may include a conductive material, such as polycrystalline silicon, for example.

The contact plugs170may include, e.g., at least one of tungsten (W), copper (Cu), aluminum (Al), and an alloy thereof. In some example embodiments, the contact plugs170may further include a barrier layer on sidewalls and bottom surfaces of the contact holes in which the contact plugs170are disposed. The barrier layer may include, e.g., at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

The first contact plug insulating layers160may be disposed below the pad regions130P to surround side surfaces of the contact plugs170. Internal side surfaces of the first contact plug insulating layers160may surround the contact plugs170, and external side surfaces of the first contact plug insulating layers160may be surrounded by the gate electrodes130. Each of the contact plugs170may be physically and electrically connected to a single gate electrode130by the first contact plug insulating layers160, and may be electrically separated from the gate electrodes130disposed therebelow.

The second contact plug insulating layers165may be disposed above the pad regions130P to surround side surfaces of a portion of the contact plugs170. For example, the second contact plug insulating layers165may be disposed to surround the contact plugs170connected to the gate electrodes130of the lower stack structure. A gate electrode disposed most adjacent to a lower end of the second channel structures CH2among the gate electrodes130of the upper stack structure may be referred to as a second gate electrode132. The second contact plug insulating layers165may be disposed on a level corresponding to a level of the second gate electrode132or a level similar to a level of the second gate electrode132. In the present example embodiment, “corresponding level” may refer to a level within a range in which a certain component is disposed. Accordingly, the second contact plug insulating layers165may be disposed on a level overlapping a level on which the second gate electrode132is disposed or on a level similar to a level on which the second gate electrode132is disposed. In the present example embodiment, the second contact plug insulating layers165may be disposed on a level overlapping a level on which the second gate electrode132is disposed, and may be disposed a level lower than a level of the upper surface of the second gate electrode132.

The first and second contact plug insulating layers160and165may include an insulating material, and may include, e.g., at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The through plugs175may be disposed in the third region R3of the memory cell region CELL, which may be an external side region of the second substrate101, and may penetrate the cell region insulating layer190and may extend to the peripheral circuit region PERI. The through plugs175may be disposed to connect the cell interconnection lines195of the memory cell region CELL to the circuit interconnection lines280of the peripheral circuit region PERI. The through plugs175may include a conductive material, and may include a metal material such as tungsten (W), copper (Cu), and aluminum (Al). The through plugs175may be formed in the same process of forming the contact plugs170, may include the same material, and may have the same internal structure.

The first and second through plug insulating layers180and185may be disposed to surround side surfaces of the through plugs175in lower and upper portions, respectively. The first through plug insulating layers180may be disposed in a region corresponding to a lower portion of the gate electrodes130. For example, the first through plug insulating layers180may be disposed on a level corresponding to a level of the lowermost first gate electrode131or a level similar to the first gate electrode131. In the present example embodiment, the first through plug insulating layers180may be disposed on a level lower than a level of the upper surface of the first gate electrode131.

The second through plug insulating layers185may be disposed on substantially the same level as a level of the second contact plug insulating layers165. In the present example embodiment, “substantially the same” refers to an example in which a difference in a range of deviations which may be the same as or occurring in the manufacturing process, and may be interpreted the same even when the expression “substantially” is omitted. For example, the second through plug insulating layers185may be disposed on a level corresponding to a level of the second gate electrode132or a level similar to a level of the second gate electrode132.

The first and second through plug insulating layers180and185may have substantially the same thickness and/or width, but example embodiments are not limited thereto. The second through plug insulating layers185may have substantially the same thickness as that of the second contact plug insulating layers165. The first and second through plug insulating layers180and185may include an insulating material, and may include, e.g., at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The first and second nitride layers150L and150U may correspond to the nitride layer NL described above with reference toFIG.1. The first and second nitride layers150L and150U may extend parallel to the upper surface of the second substrate101in a portion of the second region R2and in the third region R3. The first nitride layer150L may be in contact with an external side surface of the first through plug insulating layers180and may extend horizontally along an x-y plane on a level corresponding to a level of the first gate electrode131. The second nitride layer150U may be in contact with external side surfaces of the second through plug insulating layers185and may extend horizontally along the x-y plane on a level corresponding to a level of the second gate electrode132. The first and second nitride layers150L and150U may be deposited to thicken the pad regions130P of the gate electrodes130during the manufacturing process and may remain.

Referring toFIG.4B, the first nitride layer150L may surround the first through plug insulating layers180, and may be in contact with the side surface of the first dummy gate electrode131D on an end adjacent to the second region R2. The first nitride layer150L may be disposed on a level higher than a level of the upper surface of the second substrate101. A thickness T4of the first nitride layer150L may be substantially the same as a thickness T3of the first dummy gate electrode131D and a thickness T5of the first through plug insulating layers180. The thickness T4of the first nitride layer150L may have a thickness smaller than the increased thickness T2in the pad region130P of the first gate electrode131. For example, the thickness T4of the first nitride layer150L may be the same as or similar to a difference between the second thickness T2and the first thickness T1described with reference toFIG.4A.

Similarly, the second nitride layer150U may also surround the second through plug insulating layers185and may be in contact with the second dummy gate electrode132D on an end adjacent to the second region R2. The second nitride layer150U may have substantially the same thickness as that of the first nitride layer150L, and the above description of the thickness T4of the first nitride layer150L may be applied thereto.

The first and second nitride layers150L and150U may include silicon nitride and may have a composition of SixNyor SixNy:H. Referring toFIG.4B, the first and second nitride layers150L and150U may include two layers152and154having different compositions and stacked vertically, but example embodiments are not limited thereto. For example, the lower layer152may have a thickness greater than a thickness of the upper layer154and may have a high content of hydrogen (H).

The first and second dummy gate electrodes131D and132D may be disposed on levels corresponding to levels of the first and second gate electrodes131and132, respectively. The first and second dummy gate electrodes131D and132D may be disposed to be spaced apart from ends of the first and second gate electrodes131and132by a predetermined distance in the x direction, respectively. The distance may be, e.g., about 50 nm or less. Accordingly, the first and second dummy gate electrodes131D and132D may be electrically separated from the first and second gate electrodes131and132, respectively.

The first and second dummy gate electrodes131D and132D may have first ends spaced apart from the ends of the first and second gate electrodes131and132, respectively, and may have second ends in contact with the first and second nitrides layers150L and150U, respectively. In the first and second dummy gate electrodes131D and132D, positions of the second ends may be the same or similar in the z direction. The second dummy gate electrode132D may be in contact with external side surfaces of the second contact plug insulating layers165and may surround the second contact plug insulating layers165.

Referring toFIG.2, an external side end of the first dummy gate electrode131D may have a wavy shape along the ends of the first and second separation regions MS1and MS2on a plan view, and may surround the ends. The external side end of the second dummy gate electrode132D may also be disposed above the external side end of the first dummy gate electrode131D and may have a shape the same as or similar to that of the first dummy gate electrode131D.

The first and second dummy gate electrodes131D and132D may have a region extending outwardly in the x direction, extending farther than the first and second separation regions MS1and MS2. In the wavy shape, since the first and second dummy gate electrodes131D and132D are formed in a region from which a portion of the first and second nitride layers150L and150U may be removed, the first and second dummy gate electrodes131D and132D may have a shape according to a profile of an etchant injected from the first and second separation regions MS1and MS2.

As described above with reference toFIG.4B, the first dummy gate electrode131D may have substantially the same thickness as that of the first nitride layer150L and the first through plug insulating layers180. The second dummy gate electrode132D may have substantially the same thickness as those of the second contact plug insulating layer165, the second nitride layer150U, and the second through plug insulating layers185. The first and second dummy gate electrodes131D and132D may have a thickness smaller than the above-described first thickness T1and the second thickness T2of the gate electrodes130including the first and second gate electrodes131and132. Also, the first and second dummy gate electrodes131D and132D may be formed of the same material as that of the gate electrodes130.

The cell region insulating layer190may be disposed to cover the second substrate101, the gate electrodes130on the second substrate101, and the peripheral region insulating layer290. The cell region insulating layer190may be formed of an insulating material, or may be formed of a plurality of insulating layers.

The cell interconnection lines195may form an upper interconnection structure electrically connected to the memory cells in the memory cell region CELL. The cell interconnection lines195may be connected to the contact plugs170and the through plugs175, and may be electrically connected to the gate electrodes130and the channel structures CH. In some example embodiments, the number of the contact plugs and the interconnection lines forming the upper interconnection structure may be varied. The cell interconnection lines195may include metal, and may include, e.g., tungsten (W), copper (Cu), aluminum (Al), or the like.

FIGS.5A and5Bare enlarged perspective views illustrating a partial region of a semiconductor device according to an example embodiment.

FIG.5Aillustrates the arrangement of the contact plug170and the second dummy gate electrode132D. For example,FIG.5Aillustrates the contact plug170connected to the gate electrode130of the lower stack structure surrounding the lower first channel structures CH1, above the pad region130P. The contact plug170may be surrounded by the second contact plug insulating layer165, and the second contact plug insulating layer165may be surrounded by the second dummy gate electrode132D.

FIG.5Billustrates the arrangement of the through plug175and the first and second nitride layers150L and150U. The through plug175may be surrounded by the first through plug insulating layer180in a lower portion, and the first through plug insulating layer180may be surrounded by the first nitride layer150L. The through plug175may be surrounded by the second through plug insulating layer185in an upper portion, and the second through plug insulating layer185may be surrounded by the second nitride layer150U.

When comparing the contact plug170with the through plug175, both the elements may be surrounded by an insulating layer, but a layer disposed on an external side the insulating layer may be different. For example, in the contact plug170, the second dummy gate electrode132D, which may be a conductive material, may be disposed on an external side of the second contact plug insulating layer165. In the through plug175, first and second nitride layers150L and150U, which may be insulating materials, may be disposed on an external side of the first and second through plug insulating layers180and185.

FIG.6is an enlarged perspective view illustrating a partial region of a semiconductor device according to an example embodiment.

FIG.6illustrates partial components disposed on a level corresponding to a level of the first gate electrode131inFIG.3A. The first gate electrodes131may be separated from each other in they direction by the first and second separation regions MS1and MS2in a region including an end portion. The first dummy gate electrode131D may be spaced apart from the first gate electrode131and may be disposed as a single layer. The first dummy gate electrode131D may have a region surrounding ends of the first and second separation regions MS1and MS2, and may have a semicircle or a wavy shape along the ends. The first nitride layer150L may be in contact with the wavy side surface of the first dummy gate electrode131D and may extend horizontally. The first nitride layer150L and the first dummy gate electrode131D may have a thickness less than that of the first gate electrode131.

The through plugs175may penetrate the first nitride layer150L and may be spaced apart from the first nitride layer150L by the first through plug insulating layers180.

FIGS.7A and7Bare a cross-sectional view illustrating a semiconductor device and an enlarged view illustrating a portion of a semiconductor device, respectively, according to an example embodiment.FIG.7Bis an enlarged view illustrating region “B” inFIG.7A.

Referring toFIGS.7A and7B, in the semiconductor device100a, a level on which the first and second nitride layers150L and150U are disposed may be different from the example embodiment inFIG.3A. Accordingly, the levels of the first and second dummy gate electrodes131D and132D, the second contact plug insulating layers165, and the first and second through plug insulating layers180and185may also be different from the example embodiment inFIG.3A.

Referring toFIGS.7A and7B, the first nitride layer150L may be disposed on a level lower than a level of a lower surface of the first gate electrode131. The first nitride layer150L may be disposed to not overlap the first gate electrode131in the x direction. For example, the first nitride layer150L may be disposed to be in contact with an upper surface of the second horizontal conductive layer104and an upper surface of the substrate insulating layer121. The above-described structure may be formed when a lowermost interlayer insulating layer120is removed from an external side of the sacrificial insulating layers118during a process of etching the sacrificial insulating layers118described below with reference toFIG.13B.

However, the interlayer insulating layer120may not be completely removed and may remain in a relatively small thickness. In this case, the lower surface of the first nitride layer150L may not be coplanar with the lower surface of the first gate electrode131, differently from the example embodiment inFIG.3A, and may be disposed at a level lower than a level of the lower surface of the first gate electrode131. According to example embodiments, the upper surface of the first nitride layer150L may be disposed on a level higher than a level of the lower surface of the first gate electrode131, differently from the illustrated present example embodiment.

Similarly, the second nitride layer150U may be disposed on a level lower than levels of the upper and lower surfaces of the second gate electrode132. The second nitride layer150U may be disposed so as not to overlap the second gate electrode132in the x direction. For example, the second nitride layer150U may be disposed within the cell region insulating layer190. However, a portion of the interlayer insulating layer120may also be described as belonging to the cell region insulating layer190depending on a description method, a boundary between the interlayer insulating layer120and the cell region insulating layer190may be varied. Also, in example embodiments, differently from the example embodiment inFIG.3A, the lower surface of the second nitride layer150U may not coplanar with the lower surface of the second gate electrode132, and may be disposed on a level lower than a level of the lower surface of the second gate electrode132, and differently from the example embodiment, the upper surface of the second nitride layer150U may be disposed on a level higher than a level of the lower surface of the second gate electrode132.

As described above, in example embodiments, the first and second nitride layers150L and150U may be disposed on a level corresponding to or lower than a level of each of the first and second gate electrodes131and132, and the specific arrangement level may be varied. Also, in example embodiments, a relative level relationship between the first nitride layer150L and the first gate electrodes131may be different from a relative height relationship between the second nitride layer150U and the second gate electrodes132. When a level of the first nitride layer150L is changed, levels of the first dummy gate electrode131D and the first through plug insulating layers180may also be changed. When a level of the second nitride layer150U is changed, the levels of the second dummy gate electrode132D, the second contact plug insulating layers165, and the second through plug insulating layers185may also be changed.

FIG.8is an enlarged view illustrating a portion of a semiconductor device according to an example embodiment, illustrating a region corresponding to region “D” inFIG.3B.

Referring toFIG.8, in a semiconductor device100b, a memory cell region CELL may not include the first and second horizontal conductive layers102and104on the second substrate101, differently from the example embodiments inFIGS.3A and3B. Also, a channel structure CHb may further include an epitaxial layer107.

The epitaxial layer107may be disposed on the second substrate101on a lower end of the channel structure CHb, and may be disposed on a side surface of at least one gate electrode130. The epitaxial layer107may be disposed in a recessed region of the second substrate101. A level of a lower surface of the epitaxial layer107may be higher than a level of an upper surface of a lowermost lower gate electrode130L and may be lower than a level of a lower surface of the lower gate electrode130L disposed above the lowermost lower gate electrode130L, but example embodiments are not limited thereto. The epitaxial layer107may be connected to the channel layer140through an upper surface. A gate insulating layer141may be further disposed between the lower gate electrode130L in contact with the epitaxial layer107.

FIG.9is a cross-sectional view illustrating a semiconductor device according to an example embodiment.

Referring toFIG.9, in a semiconductor device100c, differently from the example embodiment inFIG.3A, the second nitride layer150U, the second dummy gate electrode132D, the second contact plug insulating layers165, and the second through plug insulating layers185may not be disposed. Also, channel structures CHc may have a form in which a width thereof may gradually change, rather than a form in which upper and lower portions are connected.

The channel structures CHc in the present example embodiment may be formed by etching the entire lower stack structure and the upper stack structure of the sacrificial insulating layers118inFIGS.13B and13Ein a single process. Accordingly, the nitride layers forming the sacrificial pad regions118P may not be formed through a plurality of divided processes, and may be formed by a single process. Accordingly, since the second nitride layer150U is not separately formed, the second dummy gate electrode132D, the second contact plug insulating layers165, and the second through plug insulating layers185may be not formed. However, even in this case, the first nitride layer150L, the first dummy gate electrode131D, and the first through plug insulating layers180may be disposed on a level corresponding to or similar to a level of the first gate electrode131.

FIG.10is a cross-sectional view illustrating a semiconductor device according to an example embodiment.

Referring toFIG.10, in a semiconductor device100d, differently from the example embodiment inFIG.3A, the first and second through plug insulating layers180and185surrounding the through plugs175may not be disposed. The through plugs175may penetrate the first and second nitride layers150L and150U in addition to the cell region insulating layer190and may include a region surrounded by the first and second nitride layers150L and150U. This structure may be manufactured by forming the through plugs175in a process separate from a process of forming the contact plugs170. Accordingly, even in this case, a portion of the contact plugs170may have a region surrounded by the second contact plug insulating layers165.

FIG.11is a cross-sectional view illustrating a semiconductor device according to an example embodiment.

Referring toFIG.11, in a semiconductor device100e, a memory cell region CELL may further include a through interconnection region TR. The through interconnection region TR may correspond to the second through interconnection region TR2inFIG.1, and the first through interconnection region TR1may have the same or similar structure. In addition to the first through plugs175A, the memory cell region CELL may further include second through plugs175B disposed in the through interconnection region TR. Also, the second contact plugs170B connected to the upper gate electrodes130U may have a shape different from a shape of the other first contact plugs170A.

The through interconnection region TR may include second through plugs175B penetrating the second substrate101from an upper portion of the memory cell region CELL and extending in the z direction. The second through plugs175B may have the same shape as that of the first through plugs175A, and may not be connected to the gate electrodes130. The entire gate electrodes130may be disposed up to the uppermost upper gate electrode130U in the through interconnection region TR, and the uppermost upper gate electrode130U may not have a pad region130P in the through interconnection region TR. Thus, the uppermost upper gate electrode130U may not have an increased thickness. The second through plugs175B may be separated from the gate electrodes130by the first contact plug insulating layer160. The through interconnection region TR may be formed by performing a process to prevent the second nitride layer150U from remaining during the manufacturing process. However, the second nitride layer150U may not be removed by a separate process, and may be removed using a layer used for stop etching when a stepped portion is formed.

Differently from the first contact plugs170A, the second contact plugs170B may be disposed to be connected to the upper gate electrodes130U in the pad region130P and to not penetrate the upper gate electrodes130U. The second contact plugs170B may be disposed to be partially recessed into the upper gate electrodes130U or may be disposed to be in contact with the upper surfaces of the upper gate electrodes130U.

FIG.12is a cross-sectional view illustrating a semiconductor device according to an example embodiment.

Referring toFIG.12, a semiconductor device100fmay have a structure in which a peripheral circuit region PERI may be vertically bonded to a memory cell region CELL. In the present example embodiment, the peripheral circuit region PERI may further include first bonding metal layers295, and the memory cell region CELL may further include upper plugs187, second bonding metal layers197, and a passivation layer198on the second substrate101. Also, upper ends of the contact plugs170and the through plugs175may be disposed in the second substrate101and the substrate insulating layer121, respectively.

The first bonding metal layers295may be disposed on the circuit contact plugs270and the circuit interconnection lines280and an upper surface thereof may be exposed to an upper surface of the peripheral circuit region PERI through the peripheral region insulating layer290. The second bonding metal layers197may be disposed below the upper plugs187, and a lower surface thereof may be exposed to a lower surface of the memory cell region CELL through the cell region insulating layer190. The first bonding metal layers295and the second bonding metal layers197may include a conductive material, such as copper (Cu), for example. In some example embodiments, each of the peripheral region insulating layer290and the cell region insulating layer190may include a bonding dielectric layer surrounding the first bonding metal layers295and the second bonding metal layers197, respectively and disposed at a predetermined depth from an upper surface. The bonding dielectric layer may include, e.g., at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. The passivation layer198may be disposed on the second substrate101to protect the second substrate101and may include an insulating material.

The peripheral circuit region PERI and the memory cell region CELL may be bonded by bonding the first bonding metal layers295to the second bonding metal layers197and bonding the bonding dielectric layers to each other. The bonded first bonding metal layers295and second bonding metal layers197may be, e.g., copper (Cu)-copper (Cu) bonding. The bonded bonding dielectric layers may be bonded to each other by dielectric-dielectric bonding, and may be, e.g., SiCN—SiCN bonded layers. The peripheral circuit region PERI and the memory cell region CELL may be bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

Upper ends of the contact plugs170may be disposed to be electrically separated from each other in the second substrate101. In the present example embodiment, the second substrate101may include an insulating region106, and upper ends of the contact plugs170may be disposed in the insulating region106. However, the second substrate101may have a divided form to electrically separate the contact plugs170from each other, instead of including the insulating region106.

FIGS.13A to13Kare cross-sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment.

Referring toFIG.13A, a peripheral circuit region PERI including circuit devices220and lower interconnection structures may be formed on a first substrate201, a second substrate101on which the memory cell region CELL is provided, a horizontal insulating layer110, a second horizontal conductive layer104, and a substrate insulating layer121may be formed above the peripheral circuit region PERI.

Device separation layers210may be formed in the first substrate201, and the circuit gate dielectric layer222and the circuit gate electrode225may be formed in order on the first substrate201. The device separation layers210may be formed by, e.g., a shallow trench separation (STI) process. The circuit gate dielectric layer222and the circuit gate electrode225may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer222may be formed of silicon oxide, and the circuit gate electrode225may be formed of at least one of polysilicon or metal silicide layers, but example embodiments are not limited thereto. Thereafter, a spacer layer224and source/drain regions205may be formed on both sidewalls of the circuit gate dielectric layer222and the circuit gate electrode225. In some example embodiments, the spacer layer224may be formed of a plurality of layers. Thereafter, the source/drain regions205may be formed by performing an ion implantation process.

Among the lower interconnection structures, the circuit contact plugs270may be formed by partially forming the peripheral region insulating layer290, removing a portion thereof by etching, and filling a conductive material. The circuit interconnection lines280may be formed by depositing a conductive material and patterning the conductive material.

The peripheral region insulating layer290may include a plurality of insulating layers. The peripheral region insulating layer290may be partially formed in each process of forming the lower interconnection structures and may be partially formed on the uppermost circuit interconnection line280, such that the peripheral region insulating layer290may be formed to cover the circuit devices220and the lower interconnection structures.

Thereafter, the second substrate101may be formed on the peripheral region insulating layer290. The second substrate101may be formed of, e.g., polycrystalline silicon, and may be formed by a CVD process. Polycrystalline silicon forming the second substrate101may include impurities.

The first and second horizontal insulating layers111and112forming the horizontal insulating layer110may be alternately stacked on the second substrate101. The horizontal insulating layer110may be partially replaced with the first horizontal conductive layer102inFIG.3Athrough a subsequent process. The first horizontal insulating layers111may include a material different from a material of the second horizontal insulating layer112. For example, the first horizontal insulating layers111may be formed of the same material as a material of the interlayer insulating layers120, and the second horizontal insulating layer112may be formed of the same material as a material of the subsequent sacrificial insulating layers118. Partial regions of the horizontal insulating layer110may be removed by a patterning process, e.g., in the second region R2of the second substrate101.

The second horizontal conductive layer104may be formed on the horizontal insulating layer110and may be in contact with the second substrate101in a region from which the horizontal insulating layer110is removed. Accordingly, the second horizontal conductive layer104may be bent along ends of the horizontal insulating layer110, may cover the ends and may extend onto the second substrate101.

The substrate insulating layer121may penetrate the second substrate101in regions in which the contact plugs170(seeFIG.3A) of the second region R2are disposed and in the third region R3. The substrate insulating layer121may be formed by removing a portion of the second substrate101, the horizontal insulating layer110, and the second horizontal conductive layer104and filling an insulating material. After filling the insulating material, a planarization process may be further performed using a chemical mechanical polishing (CMP) process. Accordingly, an upper surface of the substrate insulating layer121may be substantially coplanar with an upper surface of the second horizontal conductive layer104.

Referring toFIG.13B, sacrificial insulating layers118and interlayer insulating layers120forming a lower stack structure may be alternately stacked on the second horizontal conductive layer104, a stepped structure may be formed, and a first preliminary nitride layer150LP may be formed.

In this process, the sacrificial insulating layers118and the interlayer insulating layers120may be formed in a region on a level on which the first channel structures CH1(seeFIG.3A) are disposed. An upper interlayer insulating layer125having a relatively great thickness may be formed on an uppermost portion, and an etch stop layer126may be formed above the upper interlayer insulating layer125. The sacrificial insulating layers118may be replaced with the gate electrodes130(seeFIG.3A) through a subsequent process. The sacrificial insulating layers118may be formed of a material different from that of the interlayer insulating layers120, and may be formed of a material etched with etch selectivity for the interlayer insulating layers120under predetermined etching conditions. For example, the interlayer insulating layer120and the upper interlayer insulating layer125may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layers118may be formed of a material different from that of the interlayer insulating layer120, selected from among silicon, silicon oxide, silicon carbide, and silicon nitride. In some example embodiments, the interlayer insulating layers120may not have the same thickness. Also, the thicknesses of the interlayer insulating layers120and the sacrificial insulating layers118and the number of layers thereof may be varied from the illustrated example. The etch stop layer126may be a layer for protecting a structure disposed below when a stepped structure is formed, and may be referred to as a hard mask layer.

Thereafter, in the second region R2, a photolithography process and an etching process may be repeatedly performed on the sacrificial insulating layers118using a mask layer such that the upper sacrificial insulating layers118may extend less than the lower sacrificial insulating layers118. Accordingly, the sacrificial insulating layers118may form a stepped structure by a predetermined unit, and sacrificial pad regions118P disposed on an uppermost portion of the sacrificial insulating layers118may be exposed upwardly. The first nitride layer150L in the example embodiment ofFIGS.7A and7Bmay be formed by forming the lowermost interlayer insulating layer120to extend by the same length as that of the sacrificial insulating layer118disposed above the lowermost interlayer insulating layer120.

Thereafter, a first preliminary nitride layer150LP may be formed on the lower stack structure. The first preliminary nitride layer150LP may, along the staircase shape of the lower stack structure, cover the exposed sacrificial pad regions118P, may cover side surfaces of the staircase of the lower stack structure, and may extend into the lowermost interlayer insulating layer120. A thickness of the first preliminary nitride layer150LP may range from about 50% to about 110% of a thickness of the sacrificial insulating layers118, but example embodiments are not limited thereto.

Referring toFIG.13C, the first nitride layer150L may be formed by partially removing the first preliminary nitride layer150LP to remain only on the sacrificial pad regions118P.

The first preliminary nitride layer150LP may be selectively removed from side surfaces of the staircase of the lower stack structure. The removing process may be performed after changing physical properties of horizontally deposited regions of the first preliminary nitride layer150LP using plasma, for example. Accordingly, the first preliminary nitride layer150LP may remain on the sacrificial pad regions118P and the lowermost interlayer insulating layer120and may form the first nitride layer150L. On the lowermost interlayer insulating layer120, the first nitride layer150L may be spaced apart from adjacent sacrificial pad region118P.

In the present example embodiment, a process for removing the first nitride layer150L from an external side of the lower stack structure may not be performed, thereby simplifying the process and improving productivity. Accordingly, the first nitride layer150L on the lowermost interlayer insulating layer120may remain in a portion of the second region R2and the third region R3and may be included in the semiconductor device100.

Referring toFIG.13D, first channel sacrificial layers116apenetrating the lower stack structure may be formed.

First, a portion of the cell region insulating layer190covering the lower stack structure of the sacrificial insulating layers118and the interlayer insulating layers120may be formed, and the etch stop layer126may be removed by a planarization process.

Thereafter, the first channel sacrificial layers116amay be formed in a region corresponding to the first channel structures CH1(seeFIG.3A) in the first region R1. The first channel sacrificial layers116amay be formed by forming lower channel holes to penetrate the lower stack structure, and depositing a material forming the first channel sacrificial layers116ain the lower channel holes. The first channel sacrificial layers116amay include, e.g., polycrystalline silicon.

Referring toFIG.13E, the sacrificial insulating layers118and the interlayer insulating layers120forming an upper stack structure may be alternately stacked on the lower stack structure, a stepped structure may be formed, and a second nitride layer150U may be formed.

In this process, in the upper region on a level on which the second channel structures CH2(seeFIG.3A) is disposed, the process for the lower stack structure described above with reference toFIGS.13B and13Cmay be performed in the same manner. Accordingly, the second nitride layer150U may remain only on the sacrificial pad regions118P and on the lowermost interlayer insulating layer120of the upper stack structure. Also, on the lowermost interlayer insulating layer120of the upper stack structure, the second nitride layer150U may be spaced apart from an adjacent sacrificial pad region118P. The second nitride layer150U in the example embodiment ofFIGS.7A and7Bmay be formed by forming the lowermost interlayer insulating layer120of the upper stack structure to extend by the same length as that of the sacrificial insulating layer118disposed above the lowermost interlayer insulating layer120.

In the present example embodiment, a process for removing the second nitride layer150U from an external side of the upper stack structure may not be performed, thereby simplifying the process and improving productivity. Accordingly, the second nitride layer150U on the lowermost interlayer insulating layer120of the upper stack structure may remain in a portion of the second region R2and the third region R3and may be included in the semiconductor device100.

Referring toFIG.13F, second channel sacrificial layers116bpenetrating the upper stack structure may be formed.

A portion of the cell region insulating layer190covering the upper stack structure of the sacrificial insulating layers118and the interlayer insulating layers120may be formed.

Thereafter, the second channel sacrificial layers116bmay be formed by forming upper channel holes to penetrate the upper stack structure and to expose upper ends of the first channel sacrificial layers116aand depositing a material forming the second channel sacrificial layers116bin the upper channel holes. The second channel sacrificial layers116bmay include, e.g., polycrystalline silicon.

Referring toFIG.13G, the first and second sacrificial channel layers116aand116bmay be removed, the channel structures CH may be formed, and openings OH may be formed.

In the upper stack structure, an upper separation region SS (seeFIG.3B) may be formed by removing a portion of the sacrificial insulating layers118and the interlayer insulating layers120. To form the upper separation region SS, a region in which the upper separation region SS is to be formed may be exposed using a mask layer, a predetermined number of the sacrificial insulating layers118and the interlayer insulating layers120may be removed, an insulating material may be deposited, thereby forming the upper separation insulating layer103(seeFIG.3B).

The channel structures CH may be formed by forming channel holes by removing the first and second sacrificial channel layers116aand116band filling the channel holes. For example, the channel structures CH may be formed by forming a gate dielectric layer145, a channel layer140, a channel filling insulating layer147, and a channel pad149in order in the channel holes. In this process, at least a portion of the gate dielectric layer145extending vertically along the channel layer140may be formed. The channel layer140may be formed on the gate dielectric layer145in the channel structures CH. The channel filling insulating layer147may be formed to fill the channel structures CH, and may be an insulating material. The channel pads149may be formed of a conductive material, such as polycrystalline silicon, for example.

The openings OH may be formed in a region in which the contact plugs170and the through plugs175inFIG.3Aare to be formed. Before the openings OH are formed, a portion of the cell region insulating layer190covering the channel structures CH may be further formed. The openings OH may have a cylindrical hole shape, may penetrate the substrate insulating layer121, and may extend to the peripheral circuit region PERI. Although not specifically illustrated, the openings OH may be formed to expose the pad layers285(seeFIG.4C) on the circuit interconnection lines280. A portion of the openings OH may extend by penetrating the first and second nitride layers150L and150U.

Referring toFIG.13H, the sacrificial insulating layers118and the first and second nitride layers150L and150U exposed through the openings OH may be partially removed.

By providing an etchant through the openings OH, the sacrificial insulating layers118and the first and second nitride layers150L and150U may be removed from a circumference of the openings OH by a predetermined length, thereby forming first tunnel portions TL1. The first tunnel portions TL1may be formed to have a relatively short length in the sacrificial pad regions118P, and may be formed to have a relatively long length in the sacrificial insulating layers118disposed below the sacrificial pad regions118P.

For example, at first, the first tunnel portions TL1may be formed relatively long in the sacrificial pad regions118P, which may be because an etching rate of the first and second preliminary nitride layers150LP and150UP may be relatively higher than an etching rate of etching the sacrificial insulating layers118. Thereafter, a sacrificial layer may be formed in the openings OH and the first tunnel portions TL1. The sacrificial layer may be formed of a material having an etching rate slower than those of the first and second preliminary nitride layers150LP and150UP and the sacrificial insulating layers118. Thereafter, a portion of the sacrificial layer and the sacrificial insulating layers118may be removed. In this case, the sacrificial layer may remain in an uppermost portion, and in a lower portion, the sacrificial layer may be removed and portions of the sacrificial insulating layers118may be removed. Accordingly, the first tunnel portions TL1may be formed to have a relatively short length in the sacrificial pad regions118P.

Referring toFIG.13I, the first tunnel portions TL1and the openings OH may be filled with preliminary contact plug insulating layers160P and vertical sacrificial layers191, the sacrificial insulating layers118may be removed, thereby forming second tunnel portions TL2.

The preliminary contact plug insulating layers160P may remain in a subsequent process, and may form the first and second contact plug insulating layers160and165and the first and second through plug insulating layers180and185. The preliminary contact plug insulating layers160P may be deposited by, e.g., an ALD process. The preliminary contact plug insulating layers160P may not completely fill the first tunnel portions TL1in an uppermost region of each of the stepped regions having a relatively great thickness, a region from which the sacrificial pad regions118P are partially removed, and may completely fill the first tunnel portions TL1in a lower region and the region form which the first and second nitride layers150L and150U are removed.

The vertical sacrificial layers191may be formed to fill the remaining space in the openings OH. The vertical sacrificial layers191may include a material different from that of the preliminary contact plug insulating layers160P, and may include, e.g., polycrystalline silicon.

Thereafter, openings penetrating the sacrificial insulating layers118and the interlayer insulating layers120and extending toward the second substrate101may be formed in the positions of the first and second separation regions MS1and MS2(seeFIG.2).

By forming sacrificial spacer layers in the openings and performing an etch-back process, the horizontal insulating layer110may be selectively removed from the first region R1and a portion of the exposed gate dielectric layer145may also be removed. The first horizontal conductive layer102may be formed by depositing a conductive material in the region from which the horizontal insulating layer110is removed, and the sacrificial spacer layers may be removed from the openings. By this process, the first horizontal conductive layer102may be formed in the first region R1.

The sacrificial insulating layers118may be selectively removed with reference to the interlayer insulating layers120, the second horizontal conductive layer104, and the substrate insulating layer121using wet etching, for example. Accordingly, the second tunnel portions TL2may be formed between the interlayer insulating layers120. In this process, a portion of the first and second nitride layers150L and150U may also be removed. For example, the first and second nitride layers150L and150U may be removed from regions corresponding to the first and second dummy gate electrodes131D and132D illustrated inFIG.3A.

Referring toFIG.13J, the gate electrodes130may be formed by filling the second tunnel portions TL2with a conductive material, the vertical sacrificial layers191may be removed, and the preliminary contact plug insulating layers160P may be partially removed.

Before the gate electrodes130are formed, a portion of the gate dielectric layer145extending vertically along the gate electrode130may be formed, and the gate electrodes130and the first and second dummy gate electrodes131D and132D may be formed. The conductive material forming the gate electrodes130may fill the second tunnel portions TL2. The conductive material may include a metal, polycrystalline silicon, or metal silicide material. After the gate electrodes130is formed, the separation insulating layer105may be formed in the openings formed in the regions of the first and second separation regions MS1and MS2.

The vertical sacrificial layers191in the openings OH may be selectively removed. After the vertical sacrificial layers191are removed, the exposed preliminary contact plug insulating layers160P may be partially removed. In this case, in the pad regions130P, the preliminary contact plug insulating layers160P may be entirely removed such that third tunnel portions TL3may be formed, and the preliminary contact plug insulating layers160P may remain in a lower portion and may form the first contact plug insulating layers160. In the third tunnel portions TL3, after the preliminary contact plug insulating layers160P are removed, the exposed gate dielectric layer145may also be partially removed to expose side surfaces of the gate electrodes130. On a level corresponding to the first and second nitride layers150L and150U, the preliminary contact plug insulating layers160P may remain and may form the second contact plug insulating layer165and the first and second through plug insulating layers180and185.

Referring toFIG.13K, contact plugs170and through contact plugs175may be formed by depositing a conductive material in the openings OH.

The circuit interconnection lines280may be exposed by removing the pad layers285(seeFIG.4C) from a lower end of the openings OH, and the conductive material may be deposited. The contact plugs170and the through contact plugs175may be formed together in the same process, and thus the contact plugs170and the through contact plugs175may have the same structure. The contact plugs170may be formed to have horizontal extension portions170H (seeFIG.4A) in the pad regions130P, thereby being physically and electrically connected to the gate electrodes130.

Referring back toFIG.3A, the semiconductor device100may be manufactured by forming cell interconnection lines195connected to the upper ends of the through contact plugs175and the contact plugs170.

FIG.14is a view illustrating a data storage system including a semiconductor device according to an example embodiment.

Referring toFIG.14, a data storage system1000may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The data storage system1000may be implemented as a storage device including one or a plurality of semiconductor devices1100or an electronic device including a storage device. For example, the data storage system1000may be implemented as a solid state drive device (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, including one or a plurality of semiconductor devices1100.

The semiconductor device1100may be implemented as a nonvolatile memory device, and may be implemented as the NAND flash memory device described with reference toFIGS.1to12, for example. The semiconductor device1100may include a first semiconductor structure1100F and a second semiconductor structure1100S on the first semiconductor structure1100F. In some example embodiments, the first semiconductor structure1100F may be disposed on the side of the second semiconductor structure1100S. The first semiconductor structure1100F may be configured as a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second semiconductor structure1100S may be configured as a memory cell structure including a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second semiconductor structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be varied in example embodiments.

In some example embodiments, the upper transistors UT1and UT2may include a string select transistor, and the lower transistors LT1and LT2may include a ground select transistor. The gate lower lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

In some example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground select transistor LT2connected to each other in series. The upper transistors UT1and UT2may include a string select transistor UT1and an upper erase control transistor UT2connected to each other in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT1may be used for an erase operation of erasing data stored in the memory cell transistors MCT using a GIDL phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection interconnections1115extending from the semiconductor structure1100F to the second semiconductor structure1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection interconnections1125extending from the first semiconductor structure1100F to the second semiconductor structure1100S.

In the first semiconductor structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through an input and output pad1101electrically connected to the logic circuit1130. The input and output pad1101may be electrically connected to the logic circuit1130through an input and output connection interconnection1135extending from the first semiconductor structure1100F to the second semiconductor structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In some example embodiments, the data storage system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control overall operation of the data storage system1000including the controller1200. The processor1210may operate according to a predetermined firmware, and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221for processing communication with the semiconductor device1100. Control commands for controlling the semiconductor device1100, data to be written in the memory cell transistors MCT of the semiconductor device1100, and data to be read from the memory cell transistors MCT of the semiconductor device1100may be transmitted through the NAND interface1221. The host interface1230may provide a communication function between the data storage system1000and an external host. When a control command is received from an external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.15is a perspective view illustrating a data storage system including a semiconductor device according to an example embodiment.

Referring toFIG.15, a data storage system2000according to an example embodiment may include a main substrate2001, a controller2002mounted on the main substrate2001, one or more semiconductor packages2003, and a DRAM2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by interconnection patterns2005formed on the main substrate2001.

The main substrate2001may include a connector2006including a plurality of pins coupled to an external host. The number and the arrangement of the plurality of pins in the connector2006may be varied depending on a communication interface between the data storage system2000and the external host. In some example embodiments, the data storage system2000may communication with the external host through one of a universal serial bus (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), and an M-phy for universal flash storage (UFS). In some example embodiments, the data storage system2000may operate by power supplied from the external host through the connector2006. The data storage system2000may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller2002and the semiconductor package2003.

The controller2002may write data in the semiconductor package2003or may read data from the semiconductor package2003, and may improve an operation speed of the data storage system2000.

The DRAM2004may be configured as a buffer memory for mitigating a difference in speeds between the semiconductor package2003, a data storage space, and an external host. The DRAM2004included in the data storage system2000may also operate as a cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package2003. When the DRAM2004is included in the data storage system2000, the controller2002further may include a DRAM controller for controlling the DRAM2004in addition to the NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be configured as a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300disposed on a lower surface of each of the semiconductor chips2200, a connection structure2400electrically connecting the semiconductor chips2200to the package substrate2100, and a molding layer2500covering the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be configured as a printed circuit board including the package upper pads2130. Each of the semiconductor chips2200may include an input and output pad2210. The input and output pad2210may correspond to the input and output pad1101inFIG.14. Each of the semiconductor chips2200may include gate stack structures3210and channel structures3220. Each of the semiconductor chips2200may include the semiconductor device described with reference toFIGS.1to12.

In some example embodiments, the connection structure2400may be a bonding wire electrically connecting the input and output pad2210to the package upper pads2130. Accordingly, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other through a bonding wire method, and may be electrically connected to the package upper pads2130of the package substrate2100. In some example embodiments, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by a connection structure a through silicon via (TSV), instead of the connection structure2400of a bonding wire method.

In some example embodiments, the controller2002and the semiconductor chips2200may be included in a single package. For example, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate different from the main substrate2001, and the controller2002may be connected to the semiconductor chips2200by interconnections formed on the interposer substrate.

FIG.16is a cross-sectional view illustrating a semiconductor device according to an example embodiment.FIG.16illustrates an example embodiment of the semiconductor package2003inFIG.15, and illustrates the semiconductor package2003inFIG.15taken along line III-III′.

Referring toFIG.16, in the semiconductor package2003, the package substrate2100may be configured as a printed circuit board. The package substrate2100may include a package substrate body portion2120, package upper pads2130(seeFIG.15) disposed on an upper surface of the package substrate body portion2120, lower pads2125disposed on a lower surface of the package substrate body portion2120or exposed through the lower surface, and internal interconnections2135electrically connecting the upper pads2130to the lower pads2125in the package substrate body portion2120. The upper pads2130may be electrically connected to the connection structures2400. The lower pads2125may be connected to the interconnection patterns2005of the main substrate2001of the data storage system2000through conductive connection portions2800as inFIG.14.

Each of the semiconductor chips2200may include a semiconductor substrate3010and a first structure3100and a second structure3200stacked in order on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region including peripheral interconnections3110. The second structure3200may include a common source line3205, a gate stack structure3210on the common source line3205, channel structures3220and separation structures3230penetrating the gate stack structure3210, bit lines3240electrically connected to the channel structures3220, and contact plugs3235electrically connected to the word lines WL (seeFIG.14) of the gate stack structure3210. As described with reference toFIGS.1to12, in each of the semiconductor chips2200, the first and second nitride layers150L and150U may remain in a portion of the second region R2and in the third region R3.

Each of the semiconductor chips2200may include a through interconnection3245electrically connected to the peripheral interconnections3110of the first structure3100and extending into the second semiconductor structure3200. The through interconnection3245may be disposed on an external side of the gate stack structure3210, and may be further disposed to penetrate the gate stack structure3210. Each of the semiconductor chips2200may further include an input and output pad2210(seeFIG.15) electrically connected to the peripheral interconnections3110of the first structure3100.

Example embodiments may include a contact plug structure surrounded by first contact plug insulating layers and a remaining nitride layer for forming pad regions of gate electrodes.

As described above, an example embodiment may provide a semiconductor device having improved productivity. An example embodiment may provide a data storage system including a semiconductor device having improved productivity.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.