Patent ID: 12210962

DETAILED DESCRIPTION

The present disclosure includes apparatuses and methods related to artificial neural networks (ANNs) on a deep learning accelerator (DLA). ANN application workloads deployed on edge devices, such as fog computing nodes, can change dramatically due to usage requirements. Under some situations, the compute units available on an edge device might become oversubscribed. Such situations may be addressed with manual or automated load management switching the deployed ANN model based on workload requirements. However, switching between ANN models at runtime may incur overheads such as recompiling ANN models and creating runtime schedules. Such overhead can be detrimental to the overall robustness and the real-time aspects of the ANN applications.

Some DLAs include a vast systolic array of compute units. A vast systolic array is an homogenous network of tightly coupled data accessing units such as multiply and accumulate units (MAC). However, such approaches can be inefficient if the ANNs do not efficiently utilize the large MAC units. Other DLAs include smaller compute units that work in tandem such that an ANN workload is executed through a fixed schedule. The scalable aspect of smaller compute units allows for the execution of multiple ANNs on the same DLA, such as an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). However, each ANN utilizes a fixed set of computing units and a fixed execution schedule. Such a workload strategy is ignorant of changing workloads and user performance requirements.

Aspects of the present disclosure address the above and other deficiencies. For instance, a respective throughput of each ANN deployed on a DLA can be changed at runtime. For example, the change can be made based on data in the input pipeline and/or user-specified values. The change can be made without going through a full recompilation and redeployment of the ANNs on the DLA. In at least one embodiment, multiple ANNs can be co-compiled as a single workload and deployed on the DLA. The compiler can produce several execution schedules for the ANNs on the DLA. Each execution schedule corresponds to a unique distribution of the ANNs across various compute units of the DLA. The execution schedules can employ techniques such as weight sharing and layer fusion between different ANNs. The execution schedules can be stored in a low-level format that can be accessed at runtime. As the throughput requirements of each ANN change (e.g., as specified by a user or workload-dependent), the execution schedule in use can be changed during runtime. In at least one embodiment, data representing the ANNs can be stored in a partially compiled state individually and then combined execution schedules can be created just-in-time as the throughput demand for the ANNs change. “Data representing the ANN” refers to any instructions associated with execution of the ANN and/or data such as weights, biases, etc. associated with the ANN.

An ANN can provide learning by forming probability weight associations between an input and an output. The probability weight associations can be provided by a plurality of nodes that comprise the ANN. The nodes together with weights, biases, and activation functions can be used to generate an output of the ANN based on the input to the ANN. As used herein, artificial intelligence refers to the ability to improve a machine through “learning” such as by storing patterns and/or examples which can be utilized to take actions at a later time. Deep learning refers to a device's ability to learn from data provided as examples. Deep learning can be a subset of artificial intelligence. Artificial neural networks, among other types of networks, can be classified as deep learning.

Fog computing is an architecture that uses edge devices, which are also referred to as nodes, to carry out some or all of the computation and/or storage locally and to communicate at least partially processed data over a network, such as the Internet. Fog computing can be used for surveillance applications. For example, a metropolitan area network can include sensors deployed on infrastructure such as that used for lighting, power transmission, communication, traffic control, etc. The sensors can be used to track automobiles, people, mobile phones, etc. In the fog surveillance application, some of the workload of the overall application can be handled by nodes proximal to the sensors so that that computational workload is distributed throughout the network rather than being bottlenecked at a centralized server.

As used herein, the singular forms “a”, “an”, and “the” include singular and plural referents unless the content clearly dictates otherwise. Furthermore, the word “may” is used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, mean “including, but not limited to.” The term “coupled” means directly or indirectly connected.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example,126may reference element “26” inFIG.1, and a similar element may be referenced as226inFIG.2. Analogous elements within a Figure may be referenced with a hyphen and extra numeral or letter. See, for example, elements228-1,228-2inFIG.2. Such analogous elements may be generally referenced without the hyphen and extra numeral or letter. For example, elements228-1and228-2may be collectively referenced as228. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention and should not be taken in a limiting sense.

FIG.1is a block diagram of an apparatus in the form of a computing system100including a memory device104in accordance with a number of embodiments of the present disclosure. The memory device104is coupled to a host102via an interface124. As used herein, a host102, a memory device104, or a memory array110, for example, might also be separately considered to be an “apparatus.” The interface124can pass control, address, data, and other signals between the memory device104and the host102. The interface124can include a command bus (e.g., coupled to the command/address circuitry106), an address bus (e.g., coupled to the command/address circuitry106), and a data bus (e.g., coupled to the input/output (I/O) circuitry122). Although the command/address circuitry106is illustrated as a single component, embodiments are not so limited, as the command circuitry and address circuitry can be discrete components. In some embodiments, the command bus and the address bus can be comprised of a common command/address bus. In some embodiments, the command bus, the address bus, and the data bus can be part of a common bus. The command bus can pass signals between the host102and the command/address circuitry106such as clock signals for timing, reset signals, chip selects, parity information, alerts, etc. The address bus can pass signals between the host102and the command/address circuitry106such as logical addresses of memory banks in the memory array110for memory operations. The interface124can be a physical interface employing a suitable protocol. Such a protocol may be custom or proprietary, or the interface124may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z interconnect, cache coherent interconnect for accelerators (CCIX), etc. In some cases, the command/address circuitry106is a register clock driver (RCD), such as RCD employed on an RDIMM or LRDIMM.

The memory device104and host102can be a fog computing node, a satellite, a communications tower, a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, a memory card reader, an Internet-of-Things (IoT) enabled device, an automobile, among various other types of systems. For clarity, the system100has been simplified to focus on features with particular relevance to the present disclosure. The host102can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing the memory device104.

The memory device104can provide main memory for the host102or can be used as additional memory or storage for the host102. By way of example, the memory device104can be a dual in-line memory module (DIMM) including memory arrays110operated as double data rate (DDR) DRAM, such as DDR5, a graphics DDR DRAM, such as GDDR6, or another type of memory system. Embodiments are not limited to a particular type of memory device104. Other examples of memory arrays110include RAM, ROM, SDRAM, LPDRAM, PCRAM, RRAM, flash memory, and three-dimensional cross-point, among others. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased.

The command/address circuitry106can decode signals provided by the host102. The command/address circuitry106can also be referred to as a command input and control circuit (or more generally, “control circuitry”) and can represent the functionality of different discrete ASICs or portions of different ASICs depending on the implementation. The signals can be commands provided by the host102. These signals can include chip enable signals, write enable signals, and address latch signals, among others, that are used to control operations performed on the memory array110. Such operations can include data read operations, data write operations, data erase operations, data move operations, etc. The command/address circuitry106can comprise a state machine, a sequencer, and/or some other type of control circuitry, which may be implemented in the form of hardware, firmware, or software, or any combination of the three. The commands can be decoded by command decode circuitry108and forwarded to the memory array110via column decode circuitry116and/or row decode circuitry118.

Data can be provided to and/or from the memory array110via data lines coupling the memory array110to input/output (I/O) circuitry122via read/write circuitry114. The I/O circuitry122can be used for bi-directional data communication with the host102over an interface. The read/write circuitry114is used to write data to the memory array110or read data from the memory array110. As an example, the read/write circuitry114can comprise various drivers, latch circuitry, etc. In some embodiments, the data path can bypass the command/address circuitry106.

The memory device104includes address decode circuitry120to latch address signals provided over an interface. Address signals are received and decoded by address decode circuitry120and provided therefrom to row decode circuitry118and/or column decode circuitry116to access the memory array110. Data can be read from memory array110by sensing voltage and/or current changes on the sense lines using sensing circuitry112. The sensing circuitry112can be coupled to the memory array110. The sensing circuitry112can comprise, for example, sense amplifiers that can read and latch a page (e.g., row) of data from the memory array110. Sensing (e.g., reading) a bit stored in a memory cell can involve sensing a relatively small voltage difference on a pair of sense lines, which may be referred to as digit lines or data lines.

The memory array110can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although the memory array110is shown as a single memory array, the memory array110can represent a plurality of memory arrays arraigned in banks of the memory device104. The memory array110can include a number of memory cells, such as volatile memory cells (e.g., DRAM memory cells, among other types of volatile memory cells) and/or non-volatile memory cells (e.g., RRAM memory cells, among other types of non-volatile memory cells).

The memory device can also include a DLA hardware device126. The DLA hardware device126can be coupled to the command/address circuitry106to receive commands therefrom or to provide instructions thereto. The DLA hardware device126can be coupled to the I/O circuitry122to receive data therefrom or provide data thereto. Such data can be data to be exchanged with the memory array110and/or the host102. Although not specifically illustrated, in some embodiments, the DLA hardware device126can be coupled to the memory array110for direct exchange of data therewith. The DLA hardware device126can be an ASIC, and FPGA, or other hardware component of the memory device104. As illustrated, the DLA hardware device126can have multiple ANNs128co-compiled and deployed thereon.

The ANNs128can be compiled by a compiler103on the host102. The compiler103can be hardware and/or software (executed instructions) that translates instructions (computer code) written in one programming language (a source language) into another language (the target language). In this case, the target language is that of the DLA hardware device126. For example, the compiler103can compile instructions from the host102to cause the DLA hardware device126to execute one or more ANNs128in accordance with the instructions.

The DLA hardware device126can be configured to share compute resources between the ANNs128deployed thereon according to a first execution schedule accessed from the memory array110. The DLA hardware device126can be configured to share compute resources between the ANNs128differently according to a second execution schedule accessed from the memory array110. Execution schedules are described in more detail below. The DLA hardware device126can be configured to share compute resources between the ANNs128differently according to any of a plurality of execution schedules accessed from the memory array110. The DLA hardware device126can be configured to share compute resources between the ANNs128differently without having the ANNs128redeployed on the DLA hardware device126.

The DLA hardware device126can be configured to prefetch weights associated with a second ANN128from the memory array110while executing a first ANN128. The DLA hardware device126can be configured to prefect the weights according to an upcoming context switch from the first ANN128to the second ANN128as indicated by the first execution schedule. For example, the first execution schedule may indicate that a portion of time dedicated to execution of the first ANN is about to elapse. The DLA hardware device126can prefetch the weights based on a time remaining in the first execution schedule and a time required to prefect the weights such that the weights are received prior to the context switch. Context switching is described in more detail with respect toFIG.2.

FIG.2is a block diagram of a computing system illustrating switching between different artificial neural networks deployed on a deep learning accelerator in accordance with a number of embodiments of the present disclosure. The system includes a host (Host CPU)202coupled to memory (Shared Memory)210, which is coupled to a DLA226. The memory210is illustrated as storing two engines (Engine_0 and Engine_1), which represent a first ANN228-1and a second ANN228-2. Each ANN228is associated with respective inputs230-1,230-2, outputs232-1,232-2, weights234-1,234-2, instructions236-1,236-2, and priority information238-1,238-2.

An individual ANN228can receive input data230and can generate an output232, which can be referred to as a predicted output because it is a prediction of the result of the classification, identification, or analysis performed on the input data230by the ANN228. An example of the output232is an identification of an object in an image, where the image is the input data230. The ANN228can include layers of nodes including an initial or input layer and a final or output layer with intermediate layers therebetween. The input data230can be input to the nodes of the input layer. The nodes of the output layer can provide signals that represent the output232of the ANN228.

Each node of the ANN228can be coupled to adjacent nodes. Signals can be provided from the nodes of a previous layer to connected nodes of a subsequent layer. The connection between adjacent nodes can be assigned a weight234. In some embodiments, each connection in the ANN228can have an individual weight234assigned thereto. A topology of the ANN228describes the coupling of the nodes. The topology of the ANN228also describes the quantity of nodes. The topology of the ANN228further describes the layers of the ANN228.

A node can provide (or not provide) an input signal to each of the nodes to which it is coupled. For a given pair of coupled nodes, that signal can be combined with a weight assigned to the connection therebetween. For example, the weight can be multiplied with the signal provided from a first node to the second node. A given node can have a quantity of inputs thereto from a corresponding quantity of nodes coupled thereto. The node can sum the product of the signals input thereto and the corresponding weights assigned to the connections. A bias can be added to the sum. The addition (e.g., sum of the bias and the sum of the product of the signals and the corresponding weights) can be performed by the nodes. The result of the addition can be used in an activation function to determine whether the corresponding node will provide a signal to each of the nodes to which the corresponding node is coupled.

The ANNs228can be represented by instructions236, which, according to the present disclosure, are compiled together to deploy the ANNs228on the DLA226as a single workload. Although the ANNs228are deployed on the DLA226, the backing data for the ANNs228can be stored in the memory210. The priority information238can represent a respective throughput for each of the ANNs228, a relative portion of the available resources of the DLA226that are assigned to or used by each ANN228, and/or a relative portion of execution time of the DLA226that is assigned to each ANN228. The priority information238is a target that can be adjusted. In at least one embodiment, the priority information238can be adjusted by user input. In at least one embodiment, the priority information238can be adjusted automatically based on the respective input data230for each ANN228. For example, the priority information238can be adjusted based on a relative volume of input data230for each ANN228(e.g., where a relatively greater quantity of input data230-1for a first ANN228-1yields a relatively higher priority information238-1for the first ANN228-1).

The right side ofFIG.2illustrates the DLA226using memory associated with the first ANN228-1during a first time240-1. As the priority information238indicates that a time for a context switch is approaching, the DLA226can prefetch the weights234-2associated with the second ANN238-2at the second time240-2. After prefetching the weights234-2, the context switch from the first ANN238-1to the second ANN238-2can occur at a third time240-3, after which, the DLA226uses memory associated with the second ANN238-2during a fourth time240-4. Context switching is also referred to herein as changing from one execution schedule to another execution schedule, as described in more detail with respect toFIG.3.

FIG.3is a diagram of a machine-readable medium350including instructions352to change the throughput of artificial neural networks at runtime in accordance with a number of embodiments of the present disclosure. The instructions354can be executed to compile a plurality (more than one) ANN as a single workload. As opposed to some previous approaches that compile each ANN as a separate workload (either for a general purpose processor or for a DLA hardware device), at least one embodiment of the present disclosure compiles multiple ANNs as a single workload so that the throughput for each ANN can be changed dynamically without recompiling and/or redeploying the ANNs. In some embodiments, because the multiple ANNs are compiled as a single workload, the DLA can execute both ANNs simultaneously. In some embodiments, although the multiple ANNs are compiled as a single workload, they may not be executed simultaneously by the DLA, or at least not executed simultaneously by the DLA all the time.

The instructions356can be executed to deploy the ANNs on a DLA hardware device. Deploying an ANN on the DLA can include providing instructions for execution of the ANN on the DLA to the DLA, providing weights for operation of the ANN on the DLA, providing inputs to the ANN to the DLA, and/or providing priority information for execution of the ANN (e.g., vis-à-vis other ANNs) to the DLA.

The instructions358can be executed to change a throughput for each of the ANNs at runtime. The throughput for each ANN can refer to a relative portion of the available resources of the DLA that are assigned to or used by each ANN and/or a relative portion of execution time of the DLA that is assigned to each ANN. The throughput can be adjusted, for example, by assigning a different portion of the compute resources of the DLA or a different relative portion of the execution time of the DLA to the ANNs. In at least one embodiment, the throughput can be changed based on data in an input pipeline. In at least one embodiment, the throughput can be changed based on a user specification or input. The throughputs for the ANNs can be changed without recompiling the ANNs.

Although not specifically illustrated, the instructions352can be executed to create execution schedules for the ANNs on the DLA hardware device. Each execution schedule can correspond to a respective distribution of the ANNs to the compute units of the DLA hardware device. An execution schedule can share at least one weight between at least two different ANNs. An execution schedule can share at least one layer between at least two different ANNs. The execution schedules can be stored in a low-level format, meaning that the execution schedules can be stored directly in a storage medium (e.g., the memory210illustrated inFIG.2), bypassing a file system. In at least one embodiment, in order to effectuate changes in respective throughputs for different ANNs, an active execution schedule can be changed. For example, the DLA hardware device can execute the ANNs according to a first execution schedule and then subsequently execute the ANNs according to a second execution schedule, where the first and second execution schedules correspond to different distributions of the ANNs across the compute units of the DLA hardware device. In some instances, a particular execution schedule can be represented as a directed acyclic graph.

FIG.4is a flow diagram of a method for operating the plurality of artificial neural networks on a deep learning accelerator in accordance with a number of embodiments of the present disclosure. The method can be performed by processing logic that can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method is performed by a host (e.g., host102illustrated inFIG.1), by a memory device (e.g., the memory device104illustrated inFIG.1) and/or by a DLA hardware device (e.g., the DLA hardware device126illustrated inFIG.1). Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At block460, the method can include storing data representative of ANNs (e.g., partially compiled ANNs). The ANNs can be stored in a tangible machine-readable medium such as memory. In some embodiments, each of the ANNs can be partially compiled individually. Each ANN can be stored individually. Partially compiled means that the source code of the ANN has been translated into an intermediate form for later just-in-time compiling or later interpretation and execution. Just-in-time compiling is described in more detail below.

At block462, the method can include creating a first execution schedule, in response to a first throughput demand, for operation of the ANNs on a DLA hardware device. At block464, the method can include operating the ANNs by processing the data on the DLA hardware device according to the first execution schedule. The first execution schedule corresponds to a first distribution of the ANNs to compute units of the DLA hardware device. At block466, the method can include creating a second execution schedule, in response to a second throughput demand, for operation of the ANNs on the DLA hardware device. The second execution schedule corresponds to a second distribution (different than the first distribution) of the ANNs to compute units of the DLA hardware device. At block468, the method can include operating the ANNs by processing the data on the DLA hardware device according to the second execution schedule.

Creating the first execution schedule and/or creating the second execution schedule can include just-in-time compiling the ANNs. Just-in-time compiling the ANNs mean that they are compiled at runtime rather than before runtime during compile time. Compiling the ANNs just-in-time can advantageously allow for the ANNs to be tailored more narrowly to the dynamically changing throughput demands for each ANN. Although not specifically illustrated, the method can include determining the first throughput demand and the second throughput demand based on data in an input pipeline. For example, the first ANN can be configured to operate on data input from a first source and the second ANN can be configured to operate on data input from a second source. The first and second sources can provide different and/or variable amounts of data at different times. Alternatively or additionally, the method can include determining the first throughput demand and the second throughput demand based on user input. The user input can be a predefined value or a real-time input from the user. The user input can define a relative proportion of the compute resources and/or compute time of the DLA hardware device that is dedicated to execution of each ANN. Embodiments are not limited to the use of two ANNs as embodiments can include more than two ANNs simultaneously being deployed on a DLA hardware device.

FIG.5illustrates an example computer system within which a set of instructions, for causing a machine to perform various methodologies discussed herein, can be executed. In various embodiments, the computer system590can correspond to a system (e.g., the computing system100ofFIG.1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory device104ofFIG.1) or can be used to perform the operations of control circuitry. In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system590includes a processing device591, a main memory593(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory597(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system599, which communicate with each other via a bus597.

The processing device591represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device591can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device591is configured to execute instructions552for performing the operations and steps discussed herein. The computer system590can further include a network interface device595to communicate over the network596.

The data storage system599can include a machine-readable storage medium550(also known as a computer-readable medium) on which is stored one or more sets of instructions552or software embodying any one or more of the methodologies or functions described herein. The instructions552can also reside, completely or at least partially, within the main memory593and/or within the processing device591during execution thereof by the computer system590, the main memory593and the processing device591also constituting machine-readable storage media.

The instructions552can be analogous to the instructions352illustrated inFIG.3. However, the instructions552can be different instructions to carry out any of the embodiments described herein. In at least one embodiment, the instructions552include instructions to implement functionality corresponding to the host102, the memory device104, the DLA hardware device126, and/or the ANNs128ofFIG.1.

While the machine-readable storage medium550is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

FIG.6is a block diagram of a fog computing network in accordance with a number of embodiments of the present disclosure. The fog computing network includes a plurality of sensors, such as the sensors670-1,670-2, . . . ,670-N coupled to the fog computing node672-1. Additional sensors (although not specifically enumerated) are coupled to different fog computing nodes672-2, . . . ,672-M. Non-limiting examples of sensors670include cameras, thermometers, antennas, etc. The sensors670generate data and transmit the data to the fog computing node672coupled thereto. The sensors670can be coupled to the fog computing nodes672in a wired or wireless manner.

The first fog computing node672-1includes a memory device604-1and a DLA hardware device626-1. The second fog computing node672-2includes a memory device604-2and a DLA hardware device626-2. The fog computing node672-M includes a memory device604-M and a DLA hardware device626-M. The DLA hardware devices626can be integrated with the memory devices604in respective single packages as a component thereof. The DLA hardware devices626can be external to the memory devices604(on a separate chip). Although not specifically illustrated, in some embodiments, the fog computing nodes672can include additional processing resources. The DLA hardware devices626can have more than one artificial neural network compiled as a single workload and deployed thereon, as described herein.

A DLA hardware device626-1can be configured to operate a first artificial neural network based on data from a first sensor670-1and to operate a second artificial neural network based on data from a second sensor670-2. The DLA hardware device626-1can be configured to operate the first and the second artificial neural networks according to a first schedule in response to the first sensor670-1providing a greater quantity of data than the second sensor670-2over a period of time. The DLA hardware device626-1can be configured to operate the first and the second artificial neural networks according to a second schedule in response to the second sensor670-2providing a greater quantity of data than the first sensor670-1over the period of time.

The fog computing nodes672are coupled to a fog computing server674, which includes processing resources691and memory resources693. The fog computing server674can be configured to execute a surveillance application using data received from the fog computing nodes672. For example, the surveillance application can function to track the location of mobile devices, automobiles, people, etc., among other surveillance applications.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combinations of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.