Patent ID: 12260051

DETAILED DESCRIPTION

In the specification, the expression that a first component (or region, layer, part, portion, etc.) is “on”, “connected with”, or “coupled to” a second component means that the first component is directly on, connected with, or coupled to the second component or means that a third component is disposed therebetween.

In the drawings, the same reference numeral may refer to the same component.

Hereinafter, embodiments of the present disclosure will be described with reference to accompanying drawings.

FIG.1is a perspective view of an electronic device1000, according to an embodiment of the present disclosure.

Referring toFIG.1, in an embodiment, the electronic device1000is activated in response to an electrical signal. For example, the electronic device1000may be one of a cellular phone, a laptop computer, a television, a tablet, a vehicle navigation system, a game console, or a wearable device, but is not necessarily limited thereto.FIG.1illustrates that the electronic device1000is a tablet PC.

The electronic device1000includes an active region1000A and a peripheral region1000NA. The electronic device1000displays an image through the active region1000A. The active region1000A includes a surface that is parallel to a plane defined by a first direction DR1and a second direction DR2. The peripheral region1000NA surrounds the active region1000A.

The thickness direction of the electronic device1000is parallel to a third direction DR3that crosses the first direction DR1and the second direction DR2. Accordingly, front surfaces (or top surfaces) and rear surfaces (or bottom surfaces) of members of the electronic device1000are defined based on the third direction DR3.

AlthoughFIG.1illustrates the bar-type electronic device1000, embodiments of the disclosure are not necessarily limited thereto. For example, the following description is applicable to electronic devices according to other embodiment, such as a rollable electronic device1000or a slidable electronic device1000.

FIG.2illustrates an operation of the electronic device1000according to an embodiment of the present disclosure.

Referring toFIG.2, in an embodiment, the electronic device1000includes a display layer100, a sensor layer200, a display driving unit100C, a sensor driving unit200C, and a main driving unit1000C.

The display layer100generates an image. The display layer100is a light emitting display layer. For example, the display layer100is one of an organic light emitting display layer, an inorganic light emitting display layer, an organic-inorganic display layer, a quantum dot display layer, a micro-LED display layer, or a nano-LED display layer.

The sensor layer200is disposed on the display layer100. The sensor layer200can sense an externally applied input2000. The external input2000includes all inputs that can change a capacitance. For example, the sensor layer200can sense an input made by an active-type input unit that provides a driving signal, as well as a passive-type input unit, such as a user's body.

The sensor layer200includes a first sensing group and a second sensing group. Coordinates from the external input2000are sensed by the first sensing group, and a gesture is sensed by the second sensing group. The details thereof will be described below.

The main driving unit1000C controls an overall operation of the electronic device1000. For example, the main driving unit1000C controls the operations of the display driving unit100C and the sensor driving unit200C. The main driving unit1000C includes at least one microprocessor, and may be referred to as a “host”. The main driving unit1000C may further include a graphics controller.

The display driving unit100C controls the display layer100. The display driving unit100C receives image data RGB and a control signal D-CS from the main driving unit1000C. The control signal D-CS includes various signals. For example, the control signal D-CS includes an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, and a data enable signal. The display driving unit100C generates a vertical synchronization signal and a horizontal synchronization signal that control a timing to provide a signal to the display layer100, based on the control signal D-CS.

The sensor driving unit200C controls the sensor layer200. The sensor driving unit200C receives a sensing control signal I-CS from the main driving unit1000C. The control signal I-CS includes a mode determining signal that determines a driving mode of the sensor driving unit200C, and a clock signal.

The sensor driving unit200C calculates information on coordinates of a user input, based on a signal received from the sensor layer200, and provides a signal I-SS that includes the coordinate information to the main driving unit1000C. Alternatively, the sensor driving unit200C senses a gesture, based on a signal received from the sensor layer200, and provides the signal I-SS that includes information on the gesture to the main driving unit1000C. The main driving unit1000C executes an operation that corresponds to the user input, based on the signal I-SS. For example, the main driving unit1000C operates the display driving unit100C such that a new application image is displayed on the display layer100, based on the signal I-SS.

According to an embodiment of the present disclosure, the sensor layer200senses coordinates (2D touch) from the external input2000and a gesture input (for example, a 3D touch). Accordingly, the 2D touch and the 3D touch can be sensed by one sensor driving unit200cto control the sensor layer200. However, embodiments are not necessarily limited thereto. For example, in other embodiments, a driving unit that senses the 2D touch and a driving unit that senses the 3D touch are separately provided.

FIG.3Ais a cross-sectional view of the electronic device1000, according to an embodiment of the present disclosure.

Referring toFIG.3A, in an embodiment, the electronic device1000includes the display layer100, the sensor layer200, an anti-reflection layer300, and a window400.

The display layer100includes a base layer110, a circuit layer120, a light emitting device layer130, and an encapsulation layer140.

The base layer110provides a base surface for disposing the circuit layer120. The base layer110is at least one of a glass substrate, a metal substrate, or a polymer substrate. However, embodiments are not necessarily limited thereto, and in other embodiments, the base layer110is one of an inorganic layer, an organic layer, or a composite material layer.

The circuit layer120is disposed on the base layer110. The circuit layer120includes an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The insulating layer, the semiconductor layer, and the conductive layer are formed on the base layer110through a coating or deposition process. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer are selectively patterned through multiple photolithography processes. Afterwards, the semiconductor pattern, the conductive pattern, and the signal line in the circuit layer120are formed.

The light emitting device layer130is disposed on the circuit layer120. The light emitting device layer130includes a light emitting device. For example, the light emitting device layer130includes at least one of an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED.

The encapsulation layer140is disposed on the light emitting device layer130. The encapsulation layer140protects the light emitting device layer130from foreign substances such as moisture, oxygen, and dust particles.

The sensor layer200is disposed on the display layer100. The sensor layer200is formed on the display layer100through a successive process. For example, the sensor layer200is directly disposed on the display layer100. The wording “˜directly disposed˜” indicates that no third component is interposed between the sensor layer200and the display layer100. For example, no additional adhesive member is interposed between the sensor layer200and the display layer100. However, embodiments are not necessarily limited thereto, and in other embodiments, the sensor layer200is bonded to the display layer100through an adhesive member. The adhesive member includes at least one of a typical adhesive or a sticking agent.

The anti-reflection layer300is disposed on the sensor layer200. The anti-reflection layer300reduces the reflectance of external light that is incident on the electronic device1000. The anti-reflection layer300is directly disposed on the sensor layer200. However, embodiments of the present disclosure are not necessarily limited thereto, and in other embodiments, an adhesive member is further interposed between the anti-reflection layer300and the sensor layer200.

The window400is disposed on the anti-reflection layer300. The window400includes an optically transparent material. For example, the window400includes one of glass or plastic. The window400may have a multi-layer structure or a single-layer structure. For example, the window400includes a plurality of plastic films coupled by an adhesive, or has a glass substrate and a plastic film coupled by an adhesive.

FIG.3Bis a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

Referring toFIG.3B, an electronic device1000-1includes a display layer100_1, a sensor layer200_1, the anti-reflection layer300, and the window400.

The display layer100_1includes a base substrate110_1, a circuit layer120_1, a light emitting device layer130_1, an encapsulation substrate140_1, and a coupling member150_1.

Each of the base substrate110_1and the encapsulation substrate140_1includes at least one of a glass substrate, a metal substrate, or a polymer substrate, but is not necessarily limited thereto.

The coupling member150_1is interposed between the base substrate110_1and the encapsulation substrate140_1. The coupling member150_1couples the encapsulation substrate140_1to the base substrate110_1or the circuit layer120_1. The coupling member150_1may include an inorganic material or an organic material. For example, the inorganic material includes a frit seal, and the organic material includes a photo-curable resin or a photo-plastic resin. However, a material constituting the coupling member150_1is not necessarily limited to the above example.

The sensor layer200_1is directly disposed on the encapsulation substrate140_1. For example, “directly disposed” means that no third component is interposed between the sensor layer200_1and the encapsulation substrate140_1. For example, an separate adhesive member is interposed between the sensor layer200_1and the display layer100_1. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, an adhesive layer is further interposed between the sensor layer200_1and the encapsulation substrate140_1.

FIG.4is a cross-sectional view of the electronic device1000, according to an embodiment of the present disclosure.

Referring toFIG.4, in an embodiment, at least one inorganic layer is formed on a top surface of the base layer110. The inorganic layer includes at least one of an aluminum oxide, a titanium oxide, a silicon oxide, a silicon nitride, a silicon oxynitride, a zirconium oxide, or a hafnium oxide. The inorganic layer has a multiple-layer structure. Multiple inorganic layers form a barrier layer and/or a buffer layer. According to an embodiment, the display layer100is illustrated as including a buffer layer BFL.

The buffer layer BFL improves a bonding force between the base layer110and a semiconductor pattern. The buffer layer BFL includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. For example, the buffer layer BFL has a structure in which a silicon oxide layer and a silicon nitride layer are alternately stacked.

The semiconductor pattern is disposed on the buffer layer BFL. For example, the semiconductor pattern includes polysilicon. However, embodiments of the present disclosure are not necessarily limited thereto, and in other embodiments, the semiconductor pattern includes one of amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductor.

FIG.4illustrates a portion of the semiconductor pattern, and the semiconductor pattern may be further disposed in another region. Semiconductor patterns are arranged across pixels according to a specific rule. The semiconductor patterns has a different electrical properties, depending on whether the patterns are doped. The semiconductor patterns include a first region that has higher conductivity and a second region that has lower conductivity. The first region may be doped with N-type dopants or P-type dopants. A P-type transistor includes a doping region doped with a P-type dopant, and an N-type transistor includes a doping region doped with an N-type dopant. The second region may be a non-doping region or a region doped at a concentration lower than the concentration of the first region.

The conductivity of the first region is greater than the conductivity of the second region, and the first region substantially serves as an electrode or a signal line. The second region corresponds to an active region (or channel) of a transistor. For example, a portion of the semiconductor pattern is an active region of a transistor, another portion of the semiconductor pattern is a source or a drain of the transistor, and still another portion of the semiconductor pattern is a connection electrode or a connection signal line.

Each of pixels can be expressed by an equivalent circuit that includes seven transistors, one capacitor, and a light emitting device, and the equivalent circuit of the pixel can be modified into various forms. One transistor100PC and one light emitting device100PE of the pixel are illustrated inFIG.4by way of example.

A source region SC, an active region AL, and a drain region DR of the transistor100PC are formed from the semiconductor pattern. The source region SC and the drain region DR extend in opposite directions from the active region AL, when viewed in a cross-sectional view. A portion of a connection signal line SCL formed from the semiconductor pattern is illustrated inFIG.4. In addition, the connection signal line SCL is connected to the drain region DR of the transistor100PC, when viewed in a plan view.

A first insulating layer10is disposed on the buffer layer BFL. The first insulating layer10commonly overlaps the pixels and the first insulating layer10covers the semiconductor pattern. The first insulating layer10may be an inorganic layer and/or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer10includes at least one of an aluminum oxide, a titanium oxide, a silicon oxide, a silicon nitride, a silicon oxynitride, a zirconium oxide, or a hafnium oxide. According to an embodiment, the first insulating layer10is a single-layer silicon oxide layer. The insulating layer of the circuit layer120, which is to be described below, in addition to the first insulating layer10, is an inorganic layer and/or an organic layer, and has a single-layer structure or a multi-layer structure. The inorganic layer includes, but is not necessarily limited to, at least one of the above-described materials.

A gate GT of the transistor100PC is disposed on the first insulating layer10. The gate GT is a portion of a metal pattern. The gate GT overlaps the active region AL. The gate GT functions as a mask in a process of doping the semiconductor pattern.

A second insulating layer20is disposed on the first insulating layer10and covers the gate GT. The second insulating layer20commonly overlaps the pixels. The second insulating layer20may be an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. The second insulating layer20includes at least one of silicon oxide, silicon nitride, or silicon oxynitride. According to an embodiment, the second insulating layer20has a multi-layer structure that includes a silicon oxide layer and a silicon nitride layer.

A third insulating layer30is disposed on the second insulating layer20. The third insulating layer30may have a single-layer or multi-layer structure. For example, the third insulating layer30has a multi-layer structure that includes a silicon oxide layer and a silicon nitride layer.

A first connection electrode CNE1is disposed on the third insulating layer30. The first connection electrode CNE1is connected to the connection signal line SCL through a contact hole CNT-1formed through the first insulating layer10, the second insulating layer20, and the third insulating layer30.

A fourth insulating layer40is disposed on the third insulating layer30and covers the first connection electrode CNE1. The fourth insulating layer40is a single silicon oxide layer. A fifth insulating layer50is disposed on the fourth insulating layer40. The fifth insulating layer50is an organic layer.

A second connection electrode CNE2is disposed on the fifth insulating layer50. The second connection electrode CNE2is connected to the first connection electrode CNE1through a contact hole CNT-2formed through the fourth insulating layer40, and the fifth insulating layer50.

A sixth insulating layer60is disposed on the fifth insulating layer50and covers the second connection electrode CNE2. The sixth insulating layer60is an organic layer.

The light emitting device layer130is disposed on the circuit layer120. The light emitting device layer130includes the light emitting device100PE. For example, the light emitting device layer130includes at least one of an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED. The following description will be described assuming that the light emitting device100PE is an organic light emitting device, by way of example, but embodiments of the present disclosure are not necessarily limited thereto.

The light emitting device100PE includes a first electrode AE, a light emitting layer EL, and a second electrode CE.

The first electrode AE is disposed on the sixth insulating layer60. The first electrode AE is connected with the second connection electrode CNE2through a contact hole CNT-3formed through the sixth insulating layer60.

A pixel defining layer70is disposed on the sixth insulating layer60and covers a portion of the first electrode AE. An opening70-OP is formed in the pixel defining layer70. The opening70-OP of the pixel defining layer70exposes at least a portion of the first electrode AE.

The active region1000A (seeFIG.1) includes a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA surrounds the light emitting region PXA. According to an embodiment, the light emitting region PXA corresponds to the portion of the first electrode AE that is exposed by the opening70-OP.

The light emitting layer EL is disposed on the first electrode AE. The light emitting layer EL is disposed in a region that corresponds to the opening70-OP. For example, the light emitting layer EL is separately formed in each pixel. When the light emitting layer EL is separately formed in each pixel, each of the light emitting layers EL emits light of at least one of a blue color, a red color, or a green color. However, embodiments of the present disclosure are not necessarily limited thereto, and in other embodiments, the light emitting layer EL is connected with and commonly provided in the pixels. For example, the light emitting layer EL provides blue light or white light.

The second electrode CE is disposed on the light emitting layer EL. The second electrode CE is integrally formed and commonly disposed in the plurality of pixels.

In addition, a hole control layer is interposed between the first electrode AE and the light emitting layer EL. The hole control layer is commonly disposed in the light emitting region PXA and the non-light emitting region NPXA. The hole control layer includes a hole transport layer and may further include a hole injection layer. An electron control layer is interposed between the light emitting layer EL and the second electrode CE. The electron control layer includes an electron transport layer, and may further include an electron injection layer. The hole control layer and the electron control layer are commonly formed in the pixels by using an open mask or through an ink-jet process.

The encapsulation layer140is disposed on the light emitting device layer130. The encapsulation layer140includes an inorganic layer, an organic layer, and an inorganic layer that are sequentially stacked, although layers of the encapsulation layer140are not necessarily limited thereto. The inorganic layers protect the light emitting device layer130from moisture and oxygen, and the organic layer protect the light emitting device layer130from foreign materials such as dust particles. The inorganic layers include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer includes an acrylic-based organic layer, but embodiments of the present disclosure are not necessarily limited thereto.

The sensor layer200includes a base layer201, a first conductive layer202, a sensing insulating layer203, a second conductive layer204, and a cover insulating layer205.

The base layer201is disposed on the encapsulation layer140, and the first conductive layer202are disposed on the base layer. The sensing insulating layer203is disposed on the base layer201and covers the first conductive layer202. The second conductive layer204is disposed on the sensing insulating layer203and is connected to the first conductive layer202through a hole formed through the sensing insulating layer203. The cover insulating layer205is disposed on the sensing insulating layer203and covers the second conductive layer204.

In an embodiment, the base layer201is an inorganic layer that includes at least one of silicon nitride, silicon oxynitride, or silicon oxide. In an embodiment, the base layer201is an organic layer that includes at least one of an epoxy resin, an acrylate resin, or an imide-based resin. The base layer201may have a single-layer structure or a multi-layer structure stacked in the third direction DR3.

Each of the first conductive layer202and the second conductive layer204may have a single-layer structure or a multi-layer structure stacked in the third direction DR3.

A conductive layer in a single-layer structure includes at least one of a metal layer or a transparent conductive layer. The metal layer includes at least one of molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer includes a transparent conductive oxide, such as one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer includes a conductive polymer, such as one of PEDOT, a metal nano-wire, or graphene.

A conductive layer in a multi-layer structure includes metal layers. The metal layers have, for example, a three-layer structure of titanium/aluminum/titanium. The conductive layer of a multi-layer structure includes at least one metal layer and at least one transparent conductive layer.

At least one of the sensing insulating layer203or the cover insulating layer205includes an inorganic film. The inorganic film includes at least one of an aluminum oxide, a titanium oxide, a silicon oxide, a silicon nitride, a silicon oxynitride, a zirconium oxide, or a hafnium oxide.

At least one of the sensing insulating layer203or the cover insulating layer205includes an organic film. The organic film includes at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, or a perylene-based resin.

The anti-reflection layer300is disposed on the sensor layer200. The anti-reflection layer300includes a partition layer310, a plurality of color filters320, and a planarization layer330.

The partition layer310is disposed on and overlaps the second conductive layer204. The cover insulating layer205is interposed between the partition layer310and the second conductive layer204. According to an embodiment of the present disclosure, the cover insulating layer205is omitted.

The partition layer310prevents reflection of external light from the second conductive layer204. A material of the partition layer310is not necessarily limited, as long as the material absorbs light. The partition layer310includes a layer that has a black color. According to an embodiment, the partition layer310includes a black coloring agent. The black coloring agent is one or more of a black dye or a black pigment. The black coloring agent includes a metal, such as carbon black or chromium, or an oxide thereof.

The partition layer310has a partition opening310-opformed therein. The partition opening310-opoverlaps the light emitting layer EL and the opening70-OP of the pixel defining layer70. A color filter320is disposed that corresponds to the partition opening310-op. The color filter320transmits light emitted from the light emitting layer EL that overlaps the color filter320.

The planarization layer330covers the partition layer310and the color filter320. The planarization layer330includes an organic material, and provides a flat top surface of the planarization layer330. According to an embodiment, the planarization layer330is omitted.

According to an embodiment of the present disclosure, the anti-reflection layer300includes a reflection adjusting layer instead of the color filters320. For example, as illustrated inFIG.4, the color filters320are omitted and replaced with the reflection adjusting layer. The reflection adjusting layer selectively absorbs some wavelength bands of light reflected from the display panel and/or inside the electronic device, or external light incident on the display panel and/or the electronic device.

For example, in an embodiment, the reflection adjusting layer absorbs a first wavelength region of 490 nm to 505 nm and a second wavelength region of 585 nm to 600 nm, so that the light transmittance in the first wavelength region and the second wavelength region is 40% or less. The reflection adjusting layer may absorb light of wavelengths outside the wavelength range of red, green, and blue light emitted from the light emitting layer EL. As described above, the reflection adjusting layer absorbs light of wavelengths not in the red, green, or blue wavelength range emitted from the light emitting layer EL, thereby minimizing the reduction in brightness of the display panel and/or electronic device. In addition, simultaneously, the reduction of light emitting efficiency of the display panel and/or the electronic device is minimized, thereby increasing visibility.

The reflection adjusting layer is an organic material layer that includes at least one of a dye, a pigment, or a combination thereof. For example, the reflection adjusting layer include at least one of a tetraazaporphyrin (TAP)-based compound, a porphyrin-based compound, a metal porphyrin-based compound, an oxazine-based compound, a squarylium-based compound, a triarylmethane-based compound, a polymethine-based compound, an thraquinone-based compound, a phthalocyanine-based compound, an azo-based compound, a perylene-based compound, a xanthene-based compound, a dimmonium-based compound, a dipyrromethene-based compound, or a cyanine-based compound.

According to an embodiment, the reflection adjusting layer has a transmittance of about 64% to 72%. The transmittance of the reflection adjusting layer is adjusted depending on the content of the pigment and/or dye in the reflection adjusting layer.

The window400is disposed on the anti-reflection layer300. An adhesive member ADH is interposed between the window400and the anti-reflection layer300. However, embodiments of the present disclosure are not necessarily limited thereto, and in other embodiments, the window400is directly disposed on the anti-reflection layer300. Alternatively, the window400may not be attached to the anti-reflective layer300, and a gap may be defined between the window400and the anti-reflective layer300.

FIG.5is a block diagram of the display layer100and the display driving unit100C, according to an embodiment of the present disclosure.

Referring toFIG.5, in an embodiment, the display layer100includes a plurality of scan lines SL1to SLn, a plurality of data lines DL1to DLm, where n and m are positive integers greater than one, and a plurality of pixels PX. Each of the plurality of pixels PX are connected with relevant data lines of the plurality of data lines DL1to DLm and relevant scan lines of the plurality of scan lines SL1to SLn. According to an embodiment of the present disclosure, the display layer100further includes light emitting control lines, and the display driving unit100C further includes a light emitting driving circuit that provides control signals to the light emitting control lines. A configuration of the display layer100is not necessarily limited to that shown inFIG.5.

Each of the plurality of scan lines SL1to SLn extends in the first direction DR1, and the plurality of scan lines SL1to SLn are spaced from each other in the second direction DR2. Each of the plurality of data lines DL1to DLm extends in the second direction DR2, and the plurality of data lines DL1to DLm are spaced from each other in the first direction DR1.

The display driving unit100C includes a signal control circuit100C1, a scan driving circuit100C2, and a data driving circuit100C3.

The signal control circuit100C1receives the image data RGB and the control signal D-CS from the main driving unit1000C (seeFIG.2). The control signal D-CS includes various signals. For example, the control signal D-CS includes an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, a data enable signal, etc.

The signal control circuit100C1generates a first control signal CONT1and a vertical synchronization signal Vsync based on the control signal D-CS and outputs the first control signal CONT1and the vertical synchronization signal Vsync to the scan driving circuit100C2.

The signal control circuit100C1generates a second control signal CONT2and a horizontal synchronization signal Hsync based on the control signal D-CS, and outputs the second control signal CONT2and the horizontal synchronization signal Hsync to the data driving circuit100C3.

In addition, the signal control circuit100C1outputs a driving signal DS to the data driving circuit100C3. The driving signal DS is obtained by processing the image data RGB to be appropriate for an operating condition of the display layer100. The first control signal CONT1and the second control signal CONT2are signals for operating the scan driving circuit100C2and the data driving circuit100C3and are not specifically limited.

The scan driving circuit100C2drives the plurality of scan lines SL1to SLn in response to the first control signal CONT1and the vertical synchronization signal Vsync. According to an embodiment of the present disclosure, the scan driving circuit100C2is formed in the same process as the circuit layer120(seeFIG.4) in the display layer100, but embodiments of the present disclosure are not necessarily limited thereto. For example, in other embodiments, the scan driving circuit100C2is implemented in the form of an integrated circuit (IC) that is directly mounted in a specific region of the display layer100, or mounted as a chip on film (COF) on a separate printed circuit board that is electrically connected to the display layer100.

The data driving circuit100C3outputs a gray scale voltage to data lines DL1to DLm in response to the second control signal CONT2, the horizontal synchronization signal Hsync, and the driving signal DS. The data driving circuit100C3is an integrated circuit that is directly mounted in a specific region of the display layer100or mounted on a separate printed circuit board as a chip on film, but embodiments of the present disclosure are not necessarily limited thereto. For example, in other embodiments, the data driving circuit100C3is formed in the same process as the circuit layer120(seeFIG.4) in the display layer100.

FIG.6Ais a block diagram of the sensor layer200and the sensor driving unit200C, according to an embodiment of the present disclosure.

Referring toFIG.6A, in an embodiment, the sensor layer200includes a first sensing group200G1and a second sensing group200G2. The coordinates from an external input are sensed by the first sensing group200G1, and a gesture is sensed by the second sensing group200G2. The first sensing group200G1and the second sensing group200G2overlap the active region1000A (seeFIG.1). Accordingly, the electronic device1000(seeFIG.1) can sense a gesture without increasing an area of the peripheral region1000NA (seeFIG.1).

The first sensing group200G1includes a plurality of first electrodes210and a plurality of second electrodes220. The first electrodes210are arranged in the first direction DR1, and extend in the second direction DR2. The second electrodes220are arranged in the second direction DR2, and extend in the first direction DR1. The first electrodes210cross the second electrodes220.

Each of the first electrodes210includes a first part211and a second part212. The first part211and the second part212have an integrated form, and are disposed in the same layer.

Each of the second electrodes220includes sensing patterns221and bridge patterns222. In an embodiment, one bridge pattern222electrically connects two adjacent sensing patterns221to each other, but embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, two adjacent sensing patterns221are electrically connected to each other through the plurality of bridge patterns222.

The first electrodes210includes a first-first electrode210-1, a first-second electrode210-2, a first-third electrode210-3, a first-fourth electrode210-4, and a first-fifth electrode210-5. The first-first electrode210-1, the first-second electrode210-2, the first-third electrode210-3, the first-fourth electrode210-4, and the first-fifth electrode210-5are classified according to the shapes thereof, and a plurality of at least some of the components may be provided.

A plurality of openings210opare formed in the first electrodes210. The openings210opinclude first openings210op1, second openings210op2, third openings210op3, fourth openings210op4, and fifth openings210op5. For example, one first opening210op1is formed in the first-first electrode210-1, one second opening210op2is formed in the first-second electrode210-2, one third opening210op3is formed in the first-third electrode210-3, one fourth opening210op4, and one fifth opening210op5are formed. One third opening210op3, one fourth opening210op4, and one fifth opening210op5are spaced apart from each other in the second direction DR2.

The first-first electrode210-1, the first-third electrode210-3, and the first-second electrode210-2are arranged in the first direction DR1. The first-fourth electrode210-4is interposed between the first-first electrode210-1and the first-third electrode210-3, and the first-fifth electrode210-5is interposed between the first-third electrode210-3and the first-second electrode210-2.

The sensing group200G2includes a central electrode230and a plurality of peripheral electrodes240,250,260, and270. The central electrode230and the peripheral electrodes240,250,260, and270are disposed in the openings210op. Accordingly, the second sensing group200G2overlaps the active region1000A (seeFIG.1). Accordingly, the electronic device1000(seeFIG.1) can sense a gesture without increasing an area of the peripheral region1000NA (seeFIG.1).

The peripheral electrodes240,250,260, and270include the first peripheral electrode240, the second peripheral electrode250, the third peripheral electrode260, and the fourth peripheral electrode270spaced apart from each other.

The first peripheral electrode240and the second peripheral electrode250are spaced apart from each other in the first direction DR1with the central electrode230interposed therebetween, and the third peripheral electrode260and the fourth peripheral electrode270are spaced apart from each other in the second direction DR2with the central electrode230interposed therebetween. In addition, the central electrode230is disposed at the center, and the fourth peripheral electrode270, the second peripheral electrode250, the third peripheral electrode260, and the first peripheral electrode240are arranged clockwise. Accordingly, a downward gesture, an upward gesture, a rightward gesture, a leftward gesture, a clockwise gesture, and a counterclockwise gesture can be sensed by the central electrode230and the first to fourth peripheral electrodes240,250,260, and270.

As the distance between the central electrode230and each of the first to fourth peripheral electrodes240,250,260, and270increases, the height of a gesture to be sensed increases. Accordingly, the distance between a transmission electrode, such as the central electrode230, and a reception electrode, such as one of the first to fourth peripheral electrodes240,250,260, and270, in the second sensing group200G2is greater than the distance between a transmission electrode, such as the first electrode210, and a reception electrode, such as the second electrode220, in the first sensing group200G1.

At least one of the first electrodes210or at least one second electrodes220is interposed between the central electrode230and the first to fourth peripheral electrodes240,250,260, and270.FIG.6Ashows that two first electrodes or two second electrodes are arranged between the central electrode230and each of the first to fourth peripheral electrodes240,250,260, and270, but embodiments of the present disclosure are not necessarily limited thereto. The openings210opare not formed in the first electrodes, such as the first-fourth electrode210-4and the first-fifth electrode210-5disposed between the central electrode230and the first to fourth peripheral electrodes240,250,260, and270.

The sensor driving unit200C receives a control signal I-CS from the main driving unit1000C (seeFIG.2) and provides a signal I-SS to the main driving unit1000C (seeFIG.2).

The sensor driving unit200C may be an integrated circuit (IC) that is directly mounted in a specific region of the sensor layer200, or mounted in the form of a chip on film (COF) on a separate printed circuit board that is electrically connected to the display layer100.

The sensor driving unit200C includes a sensor control circuit200C1, a signal generating circuit200C2, and an input detecting circuit200C3. The sensor control circuit200C1controls operations of the signal generating circuit200C2and the input detecting circuit200C3, in response to the control signal I-CS.

The sensor driving unit200C is selectively driven in one of a first driving mode or a second driving mode. For example, the sensor driving unit200C is driven in time division in the first driving mode and the second driving mode. The first driving mode controls the operation of the first sensing group200G1, and the second driving mode controls the operation of the second sensing group200G2. The first driving mode is a 2D touch sensing mode that senses coordinates of an external input, and the second driving mode is a 3D touch sensing mode that senses a gesture.

In the first driving mode, the signal generating circuit200C2sequentially outputs a driving signal DS1to the sensor layer200, such as the first electrodes210. The input detecting circuit200C3receives sensing signals SS1from the sensor layer200. For example, the input detecting circuit200C3receives the sensing signals SS1from the second electrodes220. According to an embodiment of the present disclosure, the signal generating circuit200C2sequentially outputs the driving signal DS1to the second electrodes220, and the input detecting circuit200C3receives the sensing signals SS1from the first electrodes210. The driving signal DS1may be referred to as a first driving signal, a first transmission signal, or a first TX signal, and the sensing signals SS1may be referred to as first sensing signals, first receiving signals, or first RX signals.

In the second driving mode, the signal generating circuit200C2sequentially outputs a driving signal DS2to the sensor layer200, such as the central electrode230. The input detecting circuit200C3receives sensing signals SS2from the sensor layer200, such as the first to fourth peripheral electrodes240,250,260, and270. The driving signal DS2may be referred to as a second driving signal, a second transmission signal, or a second TX signal, and the sensing signals SS2may be referred to as second sensing signals, second receiving signals, or second RX signals.

FIG.6Bis a plan view of the sensor layer200according to an embodiment of the present disclosure.

Referring toFIGS.6A and6B, in an embodiment, a plurality of trace lines210t,220t,230t,240t,250t,260t, and270tinclude a plurality of first trace lines210telectrically connected to the first electrodes210, a plurality of second trace lines220telectrically connected to the second electrodes220, a central trace line230telectrically connected to the central electrode230, a first peripheral trace line240telectrically connected to the first peripheral electrode240, a second peripheral trace line250telectrically connected to the second peripheral electrode250, a third peripheral trace line260telectrically connected to the third peripheral electrode260, and a fourth peripheral trace line270telectrically connected to the fourth peripheral electrode270.

According to an embodiment of the present disclosure, the central trace line230tand the first to fourth peripheral trace lines240t,250t,260t, and270tare not adjacent to each other. For example, signal interference between the central trace line230tand the first to fourth peripheral trace lines240t,250t,260t, and270tconnected to the second sensing group200G2is reduced or eliminated. Accordingly, a gesture can be more exactly sensed.

According to an embodiment as illustrated inFIG.6B, some first of the first trace lines210tare disposed between the third peripheral trace line260tand the central trace line230t. Other first trace lines210tand some second trace lines220tare disposed between the central trace line230tand the second peripheral trace line250t. Other second trace lines220tare disposed between the second peripheral trace line250tand the fourth peripheral trace line270t. Other first trace lines210tare disposed between the first peripheral trace line240tand the third peripheral trace line260t.

However, embodiments are not necessarily limited thereto. For example, other embodiments include various modifications as long as at least some of the first trace lines210tand the second trace lines220tare disposed between the central trace line230tand the first to fourth peripheral trace lines240t,250t,260t, and270t.

The trace lines210t,220t,230t,240t,250t,260t, and270tare connected to a plurality of pads PD. Accordingly, the pads PD are electrically connected to the first sensing group200G1and the second sensing group200G2.

FIG.7Ais a cross-sectional view of the sensor layer200taken along line I-I′ inFIG.6B, according to an embodiment of the present disclosure.

Referring toFIGS.6B and7A, in an embodiment, the sensor layer200has a bottom bridge structure. For example, the bridge pattern222is formed from the first conductive layer202(seeFIG.4), and the first part211, the second part212, and the sensing pattern221are formed from the second conductive layer204(seeFIG.4). The sensing pattern221is connected to the bridge pattern222through a contact hole CNT-I that penetrates through the sensing insulating layer203.

FIG.7Bis a cross-sectional view of the sensor layer200taken along line I-I′ inFIG.6B, according to an embodiment of the present disclosure.

Referring toFIGS.6B and7B, in an embodiment, the sensor layer200has a top bridge structure. For example, the bridge pattern222is formed from the second conductive layer204(seeFIG.4), and the first part211, the second part212, and the sensing pattern221are formed from the first conductive layer202(seeFIG.4). The bridge pattern222is connected to the sensing pattern221through the contact hole CNT-I that penetrates through the sensing insulating layer203.

FIG.8Ais a cross-sectional view of the sensor layer200taken along line II-II′ inFIG.6B, according to an embodiment of the present disclosure.

According to an embodiment,FIG.8Ais a cross-sectional view of the second trace line220tand the fourth peripheral trace line270t, of the trace lines210t,220t,230t,240t,250t,260t, and270t.

Each of the second trace line220tand the fourth peripheral trace line270tincludes a plurality of layers. For example, each of the second trace line220tand the fourth peripheral trace line270tincludes a first layer line formed from the first conductive layer202(seeFIG.4), a second layer line formed from the second conductive layer204(seeFIG.4), and the first layer line and the second layer line are electrically connected to each other. When each of the second trace line220tand the fourth peripheral trace line270tincludes a plurality of layers, the resistance is lower.

FIG.8Bis a cross-sectional view of the sensor layer200taken along line II-II′ inFIG.6B, according to an embodiment of the present disclosure.

According to an embodiment,FIG.8Bis a cross-sectional view of the second trace line220taand the fourth peripheral trace line270taof the trace lines210t,220t,230t,240t,250t,260t, and270t(seeFIG.6B). Each of the second trace line220taand the fourth peripheral trace line270tais formed from the second conductive layer204(seeFIG.4). However, embodiments of the present disclosure are not necessarily limited thereto. In other embodiments, the second trace line220taand the fourth peripheral trace line270taare formed from the first conductive layer202(seeFIG.4) and is disposed between the base layer201and the sensing insulating layer203.

According to an embodiment of the present disclosure, some of the trace lines210t,220t,230t,240t,250t,260t, and270thave a multi-layer structure as illustrated inFIG.8A, and other trace lines have a single-layer structure as illustrated inFIG.8B. According to an embodiment of the present disclosure, some of the trace lines210t,220t,230t,240t,250t,260t, and270tare formed from the first conductive layer202(seeFIG.4) and are interposed between the base layer201and the sensing insulating layer203, and other trace lines are formed from the second conductive layer204(SeeFIG.4).

FIG.9is an enlarged plan view of region XX′ inFIG.6B.

Referring toFIGS.6B and9, in an embodiment, the first part211has a mesh structure. An opening OP-M is formed in the first part211. The opening OP-M overlaps the opening70-OP formed in the pixel defining layer70(seeFIG.4). However, embodiments are not necessarily limited thereto, and in other embodiments, the opening OP-M overlaps a plurality of openings70-OP.

The second part212, the sensing pattern221, the bridge pattern222, the central electrode230, and the peripheral electrodes240,250,260, and270have substantially the same mesh structure as the first part211.

FIG.10is a plan view of a sensing unit SU, according to an embodiment of the present disclosure.FIG.11is an enlarged plan view of a crossing region SU-CA of the sensing unit SU according to an embodiment of the present disclosure.

Referring toFIGS.6B,10, and11, in an embodiment, the sensor layer200is divided into a plurality of sensing units SU. Each of the sensing units SU includes a crossing region between the first electrodes210and the second electrodes220. The crossing region is where the bridge patterns222are disposed.

The sensing unit SU includes a half of the first portion211, the second portion212, another half of first portion211with the second portion212between the half of the first portion211and the another half of the first portion211, a half of sensing pattern221, two bridge patterns222, and another half of sensing pattern221.

Two bridge patterns222connect two sensing patterns221to each other. First to fourth connection regions CNT-A1to CNT-A4are provided between the two bridge patterns222and the two sensing patterns221. Four contact holes CNT-1are formed in the first to fourth connection regions CNT-A1to CNT-A4, respectively. However, embodiments are not necessarily limited thereto. In other embodiments, two sensing patterns221are electrically connected to each other through one bridge pattern as described with reference toFIGS.6A and6B. In addition, according to an embodiment of the present disclosure, the two sensing patterns221are electrically connected to each other through at least three bridge patterns.

FIG.12is an enlarged plan view of region AA′ inFIG.6B.

Referring toFIGS.6A,6B, and12, in an embodiment, the central electrode230includes a plurality of central patterns231and a plurality of central bridge patterns232. The central patterns231are arranged in the first direction DR1. Each of the central patterns231extends in the second direction DR2. The central bridge patterns232are electrically connected to the central patterns231.

One central pattern231is disposed in each fourth opening210op4. Two adjacent central patterns231are electrically connected to each other by one central bridge pattern232.

According to an embodiment of the present disclosure, the central patterns231are included in the second conductive layer204(seeFIG.4), and the central bridge patterns232are included in the first conductive layer202(seeFIG.4). According to an embodiment of the present disclosure, the central patterns231are included in the first conductive layer202(seeFIG.4), and the central bridge patterns232are included in the second conductive layer204(seeFIG.4).

The central trace line230tis electrically connected to the central electrode230. For example, the central trace line230tand one central pattern231closest to the central trace line230tare electrically connected to each other through the central bridge pattern232. A line opening210opL is formed in one first electrode, such as the first-fifth electrode210-5of the first electrodes210. The central trace line230toverlaps the line opening210opL. At least a portion of the central trace line230thas a mesh structure that is similar to the first electrode210. For example, a portion that overlaps the active region1000A (seeFIG.1), of the central trace line230thas a mesh structure.

FIG.13is an enlarged plan view of region BB′ inFIG.6B.FIG.14Ais an enlarged plan view of region CC′ inFIG.6B.

Referring toFIGS.6A,6B,13and14A, in an embodiment, the first peripheral electrode240includes a plurality of first peripheral patterns241and a first peripheral bridge pattern242. The first peripheral patterns241are arranged in the first direction DR1. Each of the first peripheral patterns241extends in the second direction DR2.

The second peripheral electrode250includes a plurality of second peripheral patterns251and a second peripheral bridge pattern252. The second peripheral patterns251are arranged in the second direction DR2. Each of the second peripheral patterns251extends in the second direction DR2.

One first peripheral pattern241is disposed in each first opening210op1. Two adjacent first peripheral patterns241are electrically connected to each other by the first peripheral bridge pattern242. One second peripheral pattern251is disposed in the second opening210op2. Two adjacent second peripheral patterns251are electrically connected to each other by the second peripheral bridge pattern252.

In an embodiment, the first peripheral patterns241and the second peripheral patterns251are included in the second conductive layer204(seeFIG.4), and the first peripheral bridge pattern242and the second peripheral bridge pattern252are included in the first conductive layer202(seeFIG.4), but embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the first peripheral patterns241and the second peripheral patterns251are included in the first conductive layer202(seeFIG.4), and the first peripheral bridge pattern242and the second peripheral bridge pattern252are included in the second conductive layer204(seeFIG.4).

The first peripheral trace line240tis electrically connected to the first peripheral electrode240, and the second peripheral trace line250tis electrically connected to the second peripheral electrode250. The first peripheral trace line240tis disposed on the same layer as the first peripheral patterns241. In addition, the second peripheral trace line250tis disposed on the same layer as the second peripheral patterns251. For example, the first peripheral trace line240tis integrally formed together with one first peripheral pattern241and has a protruding and extending shape. The second peripheral trace line250tis integrally formed together with one second peripheral pattern251and has a protruding and extending shape.

Referring toFIG.6A, a first length LT1of the central patterns231(seeFIG.12) in the second direction DR2is substantially equal to a second length LT2of the first peripheral patterns241in the second direction DR2and a third length LT3of the second peripheral patterns251in the second direction DR2.

The number of the first peripheral patterns241is equal to the number of the second peripheral patterns251. AlthoughFIGS.13and14Ashow two first peripheral patterns241and two second peripheral patterns251, embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, one first peripheral pattern241and one second peripheral patterns251are provided. For example, the first peripheral bridge pattern242and the second peripheral bridge pattern252are omitted. The number of the first peripheral patterns241and the number of the second peripheral patterns251may be three or more. For example, as the number of the first peripheral patterns241and the number of the second peripheral patterns251increases, the number of first peripheral bridge patterns242and the number of second peripheral bridge patterns252may be two or more.

FIG.14Bis an enlarged plan view of a region corresponding to region CC′ inFIG.6B, according to an embodiment of the present disclosure.

Referring toFIG.14B, in an embodiment, the second peripheral trace line250tais electrically connected to the second peripheral electrode250. At least a portion of the second peripheral trace line250tais disposed in the same layer as the second peripheral bridge pattern252. For example, in an embodiment, referring toFIG.6B, the entire portion of the second peripheral trace line250tais disposed in the same layer as the second peripheral bridge pattern252. For example, in an embodiment, a portion that overlaps the first-second electrode210-2of the second peripheral trace line250tais included in the first conductive layer202(seeFIG.4), and the remaining portion of the second peripheral trace line250tais included in the second conductive layer204(seeFIG.4). For example, in an embodiment, the remaining portion of the second peripheral trace line250tahas a multi-layer structure as described inFIG.8A.

Although only the second peripheral trace line250tahas been described with reference toFIG.14B, the description presented with reference toFIG.14Balso applies to the first peripheral trace line240t(seeFIG.13).

FIG.15is an enlarged plan view of region DD′ inFIG.6B.

Referring toFIGS.6A,6B, and15, in an embodiment, the third peripheral electrode260includes a plurality of third peripheral patterns261and a plurality of third peripheral bridge patterns262. The third peripheral patterns261are arranged in the first direction DR1. Each of the third peripheral patterns261extends in the second direction DR2.

One third peripheral pattern261is disposed in each third opening210op3. Two adjacent third peripheral patterns261are electrically connected to each other by the third peripheral bridge pattern262. In an embodiment, the third peripheral patterns261are included in the second conductive layer204(seeFIG.4), and the third peripheral bridge pattern262are included in the first conductive layer202(seeFIG.4), but the present disclosure is not limited thereto. For example, in an embodiment, the third peripheral patterns261are included in the first conductive layer202(seeFIG.4), and the third peripheral bridge patterns262are included in the second conductive layer204(seeFIG.4).

The peripheral trace line260tis electrically connected to the third peripheral electrode260.

FIG.16Ais an enlarged plan view of region EE′ inFIG.6B.

Referring toFIGS.6A,6B, and16A, in an embodiment, the fourth peripheral electrode270includes a plurality of fourth peripheral patterns271. The fourth peripheral patterns271are arranged in the first direction DR1. Each of the fourth peripheral patterns271extends in the second direction DR2. One fourth peripheral pattern271is disposed in each fifth opening210op5. In an embodiment, the fourth peripheral patterns271are included in the second conductive layer204(seeFIG.4), but embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the fourth peripheral patterns271are included in the first conductive layer202(seeFIG.4).

The fourth peripheral electrode270is spaced apart from the pads PD with the third peripheral electrode260interposed therebetween. No other trace lines are disposed around the fourth peripheral trace line270t. Accordingly, the fourth peripheral patterns271are electrically connected to each other by a connection trace portion270cp. The connection trace portion270cpoverlaps the peripheral region1000NA (seeFIG.1). The fourth peripheral trace line270tis electrically connected to the fourth peripheral electrode270through the connection trace portion270cp.

Referring toFIGS.12,15, and16Atogether, in an embodiment, the number of third peripheral patterns261is equal to the number of fourth peripheral patterns271. The number of the third peripheral patterns261and the number of the fourth peripheral patterns271are equal to the number of the central patterns231

AlthoughFIGS.12,15, and16Ashow that the number of third peripheral patterns261, the number of fourth peripheral patterns271, and the number of central patterns231are four, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the number of peripheral patterns may be one or two or more.

FIG.16Bis an enlarged plan view of a region that corresponds to region EE′ inFIG.6Baccording to an embodiment of the present disclosure.

Referring toFIG.16B, in an embodiment, the fourth peripheral electrode270aincludes fourth peripheral patterns271and fourth peripheral bridge patterns272. The fourth peripheral patterns271are arranged in the first direction DR1. Each of the fourth peripheral patterns271extends in the second direction DR2.

Two adjacent fourth peripheral patterns271are electrically connected to each other by the fourth peripheral bridge pattern272. The fourth peripheral trace line270tais directly connected to the fourth peripheral electrode270a. In an embodiment, the fourth peripheral patterns271are included in the second conductive layer204(seeFIG.4), and the fourth peripheral bridge patterns272are included in the first conductive layer202(seeFIG.4), but embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the fourth peripheral patterns271are included in the first conductive layer202(seeFIG.4), and the fourth peripheral bridge patterns272are included in the second conductive layer204(seeFIG.4).

FIG.17is an enlarged plan view of a region that corresponds to region AA′ inFIG.6B, according to an embodiment of the present disclosure.

Referring toFIG.17, in an embodiment, a central electrode230aincludes the central patterns231and central bridge patterns232a. The embodiment illustrated inFIG.17has a greater number of central bridge patterns232athan an embodiment illustrated inFIG.12. For example, two adjacent central patterns231are electrically connected to each other by one central bridge pattern232. An embodiment illustrated inFIG.17can be applied to the bridge patterns described with reference toFIGS.13,14A,15, and16B.

FIG.18is a plan view of a sensor layer according to an embodiment of the present disclosure.

Referring toFIG.18, in an embodiment, a second sensing group200G2aincludes the central electrode230sand the plurality of peripheral electrodes240,250,260, and270. An embodiment illustrated inFIG.18has a larger size central electrode230swhen compared to an embodiment illustrated inFIG.6B.

The width of the central electrode230sin the first direction DR1is greater than the width in the first direction DR1of each of the third peripheral electrode260and the fourth peripheral electrode270. In addition, the width of the central electrode230sin the second direction DR2is greater than the width in the second direction DR2of each of the first peripheral electrode240and the second peripheral electrode250.

A first length LT Is of the central pattern231of the central electrode230sin the second direction DR2is greater than the second length LT2of the first peripheral pattern241in the second direction DR2and the third length LT3of the second peripheral pattern251in the second direction DR2. In addition, the number of third peripheral patterns261and the number of fourth peripheral patterns271are each less than the number of the central patterns231.

FIG.19is a plan view of a sensor layer according to an embodiment of the present disclosure.

Referring toFIG.19, in an embodiment, a second sensing group200G2bincludes the central electrode230and the plurality of peripheral electrodes240s,250s,260s, and270s. An embodiment illustrated inFIG.19has larger size peripheral electrodes240s,250s,260s, and270s, when compared to an embodiment illustrated inFIG.6B.

The width of the central electrode230in the first direction DR1is less than the width in the first direction DR1of each of the third peripheral electrode260sand the fourth peripheral electrode270s. In addition, the width of the central electrode230sin the second direction DR2is less than the width in the second direction DR2of each of the first peripheral electrode240sand the second peripheral electrode250s.

The first length LT1of the central pattern231of the central electrode230in the second direction DR2is less than the second length LT2sof the first peripheral pattern241sin the second direction DR2and the third length LT3sof the second peripheral pattern251sin the second direction DR2. In addition, the number of the third peripheral patterns261sand the number of the fourth peripheral patterns271sare each greater than the number of the central patterns231

FIG.20is a plan view of a sensor layer according to an embodiment of the present disclosure.

Referring toFIG.20, in an embodiment, the second sensing group200G2cincludes the central electrode230and first to fourth peripheral electrodes240sa,250sa,260, and270. An embodiment illustrated inFIG.20has larger size first peripheral electrode240saand second peripheral electrode250sawhen compared to an embodiment illustrated inFIG.6B.

One first electrode210is interposed between the central electrode230and the first peripheral electrode240sa, and one first electrode210is interposed between the central electrode230and the second peripheral electrode250sa. Two second electrodes220are interposed between the central electrode230and the third peripheral electrode260, and two second electrodes220are interposed between the central electrode230and the fourth peripheral electrode270.

A distance DT1between the central electrode230and the first peripheral electrode240sais less than a distance DT2between the central electrode230and the third peripheral electrode260. In addition, a length L1of a portion of the central electrode230that faces the first peripheral electrode240sais longer than a length L2of a portion of the central electrode230that faces the fourth peripheral electrode270.

According to an embodiment of the present disclosure, a distance between the central electrode230and the first to fourth peripheral electrodes240sa,250sa,260, and270can be changed based on the capacitance between the central electrode230and each of the first to fourth peripheral electrodes240sa,250sa,260, and270

As described above, coordinates of an external input can be sensed by the first sensing group, and a gesture can be sensed by the second sensing group. The first sensing group and the second sensing group overlap the active region. Accordingly, electronic device is provided that can sense a gesture without increasing the size of the peripheral region.

In addition, the central trace line connected to the second sensing group and the first to fourth trace lines are not adjacent to each other. Accordingly, signal interference between the central trace line and the first to fourth peripheral trace lines can be reduced or eliminated. Accordingly, the gesture can be more exactly sensed.

Although embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, and substitutions are possible, without departing from the scope and spirit of embodiments of the disclosure as recited in the accompanying claims. Accordingly, the technical scope of embodiments of the inventive concept is not limited to the detailed description of this specification, but should be defined by the claims.