Patent ID: 12249646

DETAIL DESCRIPTION

Described herein are techniques to fabricate a double-diffused metal-oxide-semiconductor (DMOS) transistor that includes a recessed dielectric and a non-recessed dielectric that is not recessed. In one example, the recessed dielectric enables a shorter electron path, which decreases an on-resistance of the DMOS transistor. In one example, the non-recessed dielectric provides an increased breakdown voltage by withstanding high voltage that may be applied to a drain of the DMOS transistor. In one example, the techniques described herein enable fabrication of a DMOS transistor that requires low Rsp (specific resistance) by reducing a width of a dielectric. The techniques described herein also enable the fabrication of a DMOS transistor that includes three reduced surface fields (RESURFs) to also increase a breakdown voltage of the DMOS and lower a Rsp of the DMOS.

Referring toFIG.1, an example of a DMOS transistor with a recessed dielectric is a DMOS transistor100. The DMOS transistor100includes a p-type region102, a polysilicon gate104, a dielectric106directly below the gate104, a source110, a drain116, a deep n-type well118directly below the drain116, a n-type epitaxial layer124, a n-type well132, and a p-type well136directly below the source. The n-type epitaxial layer124is directly below the p-type well136, the dielectric106the n-type well132and the deep n-type well118.

The dielectric106includes a dielectric106aand a dielectric106b. In one example, the dielectric106aand the dielectric106bare the same material. In one example the dielectric106aand the dielectric106bare silicon dioxide. In other examples, the dielectric106aand the dielectric106bare different materials.

The dielectric106aextends a distance d1in the Y-direction, and the dielectric106bextends a distance d2in the Y-direction. d1corresponds to a thickness of the dielectric106aand d2corresponds to a thickness of the dielectric106b. With d1>d2, the dielectric106bis recessed or thinner with respect to the dielectric106a.

The dielectric106ais thick enough to protect the gate104from high voltage that may come from the drain116resulting from, for example, electrostatic discharge (ESD). By having the dielectric106bthinner than the dielectric106a, electrons that are activated during a high voltage event have a shorter path to traverse from the drain116to the source110than if the dielectric106bwas as thick as the dielectric106a. A width of the dielectric106ain the X-direction is shorter than traditional DMOS transistors and therefore the DMOS transistor100has a lower on-resistance than traditional DMOS transistors.

The deep n-type well118extends into the n-type epitaxial layer124at least 10,000 Angstroms±2,000 Angstroms. In one example, the deep n-type well118is linearly doped.

The DMOS transistor100includes a reduced surface field (RESURF). The RESURF is formed by the polysilicon gate104, the dielectric106, and the n-type well132.

Referring toFIG.2, an example of a process used to fabricate a DMOS transistor with a recessed dielectric is a process200. In one example, all or some of the process200may be used in a process to fabricate the DMOS transistor100(FIG.1).

Process200deposits a first oxide layer (202). In one example, the first oxide layer is silicon dioxide. In one example, the first oxide layer is 200 Angstrom thick±20 Angstroms. In one example, the first oxide layer is deposited on the deep n-type well118and the n-type well132(FIG.1).

Process200deposits a first silicon nitride (204). For example, a first silicon nitride layer is deposited on the first oxide layer, the deep n-type well118and the n-type well132(FIG.1). In one example, the first silicon nitride layer is 1,500 Angstroms thick±15 Angstroms.

Process200deposits a first photoresist (206) and uses a first a photolithographic process to remove at least a portion of the first photoresist (208). For example, a first photoresist is deposited on the first silicon nitride, and the photolithographic process is used to remove at least a portion of the first photoresist to expose at least a portion of the first silicon nitride and/or the first oxide layer that will be etched.

Process200performs a first etching (210). For example, the at least exposed portion of the first silicon nitride and/or first oxide layer is etched, and the deep n-type well118and the n-type well132(FIG.1) underneath the etched first silicon nitride and/or etched first oxide is also etched. In one example, the deep n-type well118and the n-type well132(FIG.1) are etched 4,000 Angstroms±400 Angstroms.

Process200deposits a first dielectric (212). For example, a high-density-plasma (HDP) chemical vapor deposition (CVD) process is used to deposit the dielectric106a(FIG.1). In one example, the first dielectric is silicon dioxide. In one example, the first dielectric is 6,000 Angstroms±600 Angstroms thick.

Process200performs a first planarization (214). In one example, the first dielectric is planarized using a chemical-mechanical planarization (CMP) process. In one example, the first oxide layer applied in processing block202is also removed.

Process200removes the first silicon nitride (216). For example, the first silicon nitride is removed by phosphoric acid. In one example, the first photoresist is also removed.

Process200deposits a second oxide layer (218). In one example, the second oxide layer is silicon dioxide. In one example, the second oxide layer is 200 Angstrom thick±20 Angstroms.

Process200deposits a second silicon nitride (220). For example, a second silicon nitride layer is deposited on the second oxide layer, the n-type epitaxial layer124and the n-well132(FIG.1). In one example, the second silicon nitride layer is 1,500 Angstroms thick±150 Angstroms.

Process200deposits a second photoresist (222) and uses a second a photolithographic process to remove at least a portion of the second photoresist (224). For example, a second photoresist is deposited on the second silicon nitride, and the photolithographic process is used to remove at least a portion of the second photoresist to expose at least a portion of the second silicon nitride and/or the second oxide layer that will be etched.

Process200performs a second etching (226). For example, the at least exposed portion of the second silicon nitride and/or the second oxide is etched, and the n-type epitaxial layer124and the n-type well132(FIG.1) underneath the etched second silicon nitride and/or etched second oxide is also etched. In one example, the n-type epitaxial layer124and the n-type well132are etched 2,000 Angstroms±200 Angstroms.

Process200deposits a second dielectric (228). For example, a HDP CVD process is used to deposit the dielectric106bnext to and in contact with the dielectric106a(FIG.1). In one example, the second dielectric is silicon dioxide. In one example, the second dielectric is 4,000 Angstroms±400 Angstroms thick.

Process200performs a second planarization (230). In one example, the second dielectric is planarized using a CMP process. In one example, the second oxide layer applied in processing block218is also removed.

Referring toFIG.3, another example of a DMOS transistor with a recessed dielectric is a DMOS transistor300. All or some of the process200(FIG.2) may be used to fabricate the DMOS transistor300.

The DMOS transistor300includes a p-type region302; a polysilicon gate304a; dielectric306; a source310; a drain316; a deep n-type well318; n-epitaxial layer324, which includes a first portion324a, a second portion324band a third portion324c; a n-type buried layer328; a p-type substrate330; a n-type well332; a p-type well336; a gate oxide348between the polysilicon gate304and the dielectric106; and spacers352a,352on each side of the polysilicon gate304.

The DMOS transistor300also includes a via362connected to the source310; a metal layer364connected to the via362; a P+ region342disposed between the p-type well336and the source310; and a N+ region344next to the P+ region342and disposed between the p-type well336and the source310.

The DMOS transistor300has three RESURFs or a triple RESURF. The three RESURFs include the n-type epitaxial layer324c, n-type well332, the deep n-type well318, the p-type well336, the p-type region302and the n-type buried layer328. The n-type epitaxial layer324c, the n-type well332and the deep n-type well318are linearly doped in the drift region resulting in a double RESURF. The p-type well336, the p-type region302and the n-type buried layer328form the triple RESURF by completely depleting the p-type region302because of the high doping (e.g., on the order of 1×1019/cm3) of the n-type buried layer328. The n-type buried layer328also isolates the p-type well336and the p-type region302from the p-type substrate330by preventing minority carrier flowing into p-type substrate330.

In addition, the DMOS transistor300is configured to provide a decrease in on-resistance compared to traditional devices. For example, the p-type well336provides a very shallow channel length of about 0.1 microns that decreases on-resistance by 10 to 20% from a nominal Rsp with a longer channel such as 0.3 um.

The processes described herein are not limited to the specific examples described. For example, the process200is not limited to the specific processing order ofFIG.2. Rather, any of the processing blocks ofFIG.2may be re-ordered, combined, or removed, performed in parallel or in serial, as necessary, to achieve the results set forth above.

Having described embodiments, which serve to illustrate various concepts, structures, and techniques, which are the subject of this patent, it will now become apparent to those of ordinary skill in the art that other embodiments incorporating these concepts, structures and techniques may be used.

Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.