Patent ID: 12207456

DETAILED DESCRIPTION OF EMBODIMENTS

FIG.1is a layout diagram showing an integrated circuit device100according to example embodiments.FIG.2is a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.1, andFIG.3is a partially enlarged view of highlighted region CX1ofFIG.2.

Referring toFIGS.1to3, a device isolation trench112T is formed in a substrate110, and a device isolation layer112may be formed in, and may at least partially fill, the device isolation trench112T. A plurality of active regions AC may be defined in the substrate110, between corresponding portions of the device isolation layer112.

The active regions AC may be arranged to have long axes diagonal to a first direction X and a second direction Y, as shown byFIG.1. A plurality of word lines WL may extend in parallel to one another in the first direction, X, across the active regions AC. An insulation liner156may extend in the first direction X on both sidewalls of each of the word lines WL. In addition, a plurality of bit lines BL may extend in parallel to one another in the second direction, Y, on the word lines WL. The bit lines BL may be connected to the active regions AC via direct contacts DC.

A buried contact BC may be formed between each two adjacent bit lines BL from among the bit lines BL. The buried contacts BC may be linearly arranged in the first direction X and the second direction Y. A plurality of landing pads LP may be respectively formed on the buried contacts BC. The buried contacts BC and the landing pads LP may connect bottom electrodes (not shown) of capacitors formed over the bit lines BL to the active regions AC. The landing pads LP may be arranged to partially overlap the buried contacts BC, respectively.

The substrate110may include silicon, such as monocrystalline silicon, polycrystalline silicon, silicon-on-insulator, and/or amorphous silicon. In some other embodiments, the substrate110may include at least one selected from among Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate110may include a conductive region (e.g., a well doped with an impurity or a structure doped with an impurity). The device isolation layer112may include an oxide film, a nitride film, or a combination thereof.

A plurality of word line trenches WH extending in the first direction X are formed in the substrate110. The word line trenches WH may each include a lower portion WHL, an upper portion WHU, and an inflection portion WHI, as shown in cross-section byFIG.3. The lower portion WHL may have a first width W1 in the second direction Y. For example, the first width W1 thereof may be, but is not limited to, from about 3 nm (i.e., 30 Å) to about 100 nm (i.e., 1000 Å). The upper portion WHU is at a vertical level higher than that of the lower portion WHL and may have a second width W2 that is greater than the first width W1 in the second direction Y. For example, the second width W2 may be from about 110% to about 200% of the first width W1. For example, the second width W2 may be from about 5 nm (i.e., 50 Å) to about 200 nm (i.e., 2000 Å).

The inflection portion WHI may refer to a portion of a word line trench WH in which the width thereof changes discontinuously. For example, the inflection portion WHI may refer to a sidewall portion of the word line trench WH in which a sidewall inclination, in a transition from the lower portion WHL to the upper portion WHU, changes rapidly. The inflection portion WHI may be defined between the lower portion WHL and the upper portion WHU and sidewalls of the upper portion WHU may extend outward with respect to sidewalls of the lower portion WHL.

A plurality of gate insulation layers152, the word lines WL, a plurality of gate capping layers154, and a plurality of insulation liners156may be arranged in the word line trenches WH. The gate insulation layer152may be conformally arranged on inner walls of the word line trench WH, without interruption, along the upper portion WHU, the inflection portion WHI, and the lower portion WHL of the word line trench WH. The word lines WL may be arranged in the lower portion WHL of the word line trench WH, and sidewalls and the bottom surface of the word line WL may be surrounded by the gate insulation layer152.

A gate capping layer154may be arranged on the word line WL, as shown byFIG.3. The gate capping layer154may include a first “upper” portion154P1at a vertical level higher than that of the inflection portion WHI and a second “lower” portion154P2at a vertical level lower than that of the inflection portion WHI. The first portion154P1may be inside the upper portion WHU of the word line trench WH, whereas the second portion154P2may be inside the lower portion WHL of the word line trench WH. For example, the first portion154P1may have a third width W3 in the second direction Y, whereas the second portion154P2may have a fourth width W4 that is less than the third width W3 in the second direction Y.

The insulation liners156may be arranged on inner walls of the upper portion WHU of the word line trench WH. For example, the insulation liners156may extend from the top surface of the substrate110to the inflection portion WHI along the upper portion WHU of the word line trench WH and may be between the gate insulation layer152and the substrate110. The insulation liner156may have a first thickness T1 in the second direction Y. The first thickness T1 thereof may be, but is not limited to, from about 0.5 nm (i.e., 5 Å) to about 10 nm (i.e., 100 Å).

Advantageously, the insulation liners156may perform a dual-function as an etching mask in a 2-stage etching operation for forming the word line trenches WH, including the upper portion WHU and the lower portion WHL having different widths, and partially remain, as an electrical insulator, after the etching mask is partially removed. In a manufacturing method according to example embodiments, the upper portion WHU of the word line trench WH may be formed first, and then the insulation liners156may be formed on the inner walls of the upper portion WHU. Next, the lower portion WHL of the word line trench WH may be formed by partially etching the substrate110using the insulation liner156as an etching mask, however, as the insulation liner156is partially removed thickness-wise during etching of the substrate110, the insulation liner156may become thinner.

As shown inFIG.3, the top surface of the substrate110may be at a reference level LV0 (i.e., on a primary surface of the substrate110) and the inflection portion WHI may be at a first vertical level LV1 that is lower than (i.e., below) the reference level LV0. The top surface of the “buried” word line WL may be at a second vertical level LV2 that is lower than the first vertical level LV1. For example, a distance from the top surface of the word line WL to the top surface of the substrate110may be greater than a distance from the inflection portion WHI to the top surface of the substrate110. Also, because the insulation liner156is placed on the inner wall of the upper portion WHU of the word line trench WH, the bottom surface of the insulation liner156may be at a level higher than that of the top surface of the word line WL.

As shown inFIG.2, a distance between lower portions WHL of two adjacent word line trenches WH may be greater than a distance between upper portions WHU of the two adjacent word line trenches WH. Therefore, a relatively large distance may be secured between two word lines WL arranged in the lower portions WHL of the two adjacent word line trenches WH. Accordingly, any electrical coupling (or a disturbance caused by switching one word line WL relative to another, adjacent, word line WL) may be reduced or prevented.

In example embodiments, the word lines WL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. The “sidewall” gate insulation layer152may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide/nitride/oxide (ONO) film, or a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film. The gate capping layer154may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The insulation liner156may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

A first lower insulation layer122and a second lower insulation layer124covering the top surface of the gate capping layer154may be arranged on the substrate110. In some embodiments, the first lower insulation layer122may include a silicon oxide, whereas the second lower insulation layer124may include a silicon oxynitride or a silicon nitride.

A plurality of direct contacts DC may be respectively formed in a plurality of direct contact holes DCH in the substrate110. The direct contacts DC may be respectively connected to the active regions AC. The direct contacts DC may include doped polysilicon. For example, the direct contacts DC may include polysilicon containing an n-type impurity like phosphor (P), arsenic (As), bismuth (Bi), and antimony (Sb) at a relatively high concentration.

The bit lines BL may extend in the second direction Y over the substrate110and the direct contacts DC. The bit lines BL may be connected to the active regions AC via the direct contacts DC, respectively. The bit lines BL may each include a lower conductive layer132, an intermediate conductive layer134, and an upper conductive layer136that are sequentially stacked on the substrate110. The lower conductive layer132may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. For example, the lower conductive layer132may include polysilicon. The intermediate conductive layer134and the upper conductive layer136may each include TiN, TiSiN, W, tungsten silicide, or a combination thereof. In example embodiments, the intermediate conductive layer134may include TiN, TiSiN, or a combination thereof, whereas the upper conductive layer136may include W. The bit lines BL may be covered by a plurality of bit line capping layers138, respectively. The bit line capping layers138may include silicon nitride, and may extend in the second direction Y on the bit lines BL.

Bit line spacers140may be arranged on both sidewalls of each of the bit lines BL, and the bit line spacers140may extend in the second direction Y on both sidewalls of the bit lines BL. In some embodiments, as shown inFIG.2, a bit line spacer140may have a single layer structure; however, in other embodiments, the bit line spacer140may have a structure including a plurality of material layers. For example, the bit line spacer140may have an air spacer structure including an air space surround by insulation layers. A direct contact spacer142that fills the interior of the direct contact hole DCH and covers both sidewalls of the direct contact DC may be disposed below the bit line spacer140.

A plurality of buried contacts BC and a plurality of insulation fences (not shown) may be arranged in a row in the second direction Y, between the bit lines BL. The buried contacts BC may extend from buried contact holes BCH formed in the substrate110in a vertical direction (Z direction). The insulation fences are arranged on the gate capping layers154arranged on the word line trenches WH and may each be arranged between two adjacent buried contacts BC. In the second direction Y, both sidewalls of each of the buried contacts BC may be insulated from each other by the insulation fences. The insulation fence may include silicon nitride films.

A plurality of metal silicide films144and the landing pads LP may be formed over the buried contacts BC. The metal silicide films144and the landing pads LP may be arranged to vertically overlap the buried contacts BC. A metal silicide film144may include cobalt silicide, nickel silicide, or manganese silicide. The landing pads LP may be connected to the buried contacts BC via the metal silicide films144, respectively.

The landing pads LP may cover at least portions of the top surfaces of the bit line capping layers138to vertically overlap portions of the bit lines BL. The landing pads LP may each include a conductive barrier film172and a landing pad conductive layer174. The conductive barrier film172may include Ti, TiN, or a combination thereof. The landing pad conductive layer174may include a metal, a metal nitride, a conductive polysilicon, or a combination thereof. For example, the landing pad conductive layer174may include W. The landing pads LP may have a pattern shape of a plurality of islands in a view from above.

The landing pads LP may be electrically insulated from one another by an insulation pattern176filling an insulation space (not shown) around the landing pads LP. In some embodiments, the insulation pattern176may include a silicon nitride, a silicon oxynitride, a silicon oxide, or a combination thereof. In some embodiments, the insulation pattern176may include a first material layer (not shown) and a double-layer structure of a second material layer (not shown), wherein the first material layer may include a low-k material, such as SiO2, SiOCH, and SiOC, and the second material layer may include a silicon nitride or a silicon oxynitride.

Generally, as a distance between adjacent word lines is reduced, a problem, such as an electrical/capacitive coupling disturbance, may occur between the closely-spaced word lines. And, when the width of a word line is reduced to reduce this coupling disturbance, a difficulty in forming a metal layer constituting a word line within a relatively narrow word line trench, and an etchback process on the upper portion of the metal layer may significantly increase. Therefore, when precise control of an etchback process fails, deviation of heights of word lines becomes relatively large (or a window of heights of word lines becomes larger). Accordingly, it may be difficult for a plurality of buried channel transistors formed using the buried word lines to have uniform electrical properties.

According to example embodiments, the upper portion WHU of the word line trench WH may be formed with a relatively large width first, and then the lower portion WHL of the word line trench WH may be formed with a width less than that of the upper portion WHU by using the insulation liner156as a dual-function sidewall insulator and etching mask. Therefore, due to the relatively large width of the upper portion WHU of the word line trench WH, the difficulty of an etchback process of forming the word line WL may decrease, and the etchback process may be more precisely controlled. Furthermore, a sufficiently large distance may be secured between the word lines WL in the lower portion WHL of the word line trench WH, and thus, an electrical/capacitive coupling or a disturbance may be reduced or prevented. Thus, the integrated circuit device100, as described above, may have excellent and reliable electrical performance characteristics and high manufacturing yield.

FIG.4is a cross-sectional view of an integrated circuit device100A according to example embodiments. In particular,FIG.4is an enlarged view of a portion corresponding to a region CX1inFIG.2. InFIG.4, reference numerals that are the same as those inFIGS.1to3denote the same elements.

Referring toFIG.4, the insulation liner156(see, e.g.,FIG.3) may not be disposed on the inner walls of the upper portion WHU of the word line trench WH. The gate insulation layer152may be arranged on the inner walls of the upper portion WHU of the word line trench WH, and a first portion154P1of the gate capping layer154may entirely fill the upper portion WHU of the word line trench WH on the gate insulation layer152.

The insulation liners156may function as an etching mask in a 2-stage etching operation for forming the word line trenches WH including the upper portion WHU and the lower portion WHL having different widths. In a manufacturing method according to example embodiments, the upper portion WHU of the word line trench WH may be formed first, and then the insulation liners156may be formed on the inner walls of the upper portion WHU. Next, the lower portion WHL of the word line trench WH may be formed by partially etching the substrate110by using the insulation liner156as an etching mask, wherein the insulation liner156may be completely removed. As the insulation liner156is removed, the gate capping layer154may have a relatively large width in the upper portion WHU of the word line trench WH.

According to the example embodiments described above, due to the relatively large width of the upper portion WHU of the word line trench WH, the difficulty of an etchback process of forming the word line WL may decrease, and the etchback process may be precisely controlled. Furthermore, a sufficiently large distance may be secured between the word lines WL in the lower portion WHL of the word line trench WH, and thus, an electrical coupling or a disturbance may be reduced or prevented. The integrated circuit device100A as described above may have excellent electrical performance.

FIG.5is a cross-sectional view of an integrated circuit device100B according to example embodiments.FIG.5is an enlarged view of a portion corresponding to the region CX1inFIG.2. InFIG.5, reference numerals that are the same as those inFIGS.1to4denote the same elements.

Referring toFIG.5, the top surface of the substrate110may be at the reference level LV0, the inflection portion WHI may be at the first vertical level LV1 that is lower than the reference level LV0, and the top surface of a word line WLB may be at a third vertical level LV3 that is higher than the first vertical level LV1. For example, a distance from the top surface of the word line WLB to the top surface of the substrate110may be less than a distance from the inflection portion WHI to the top surface of the substrate110. Also, because the insulation liner156is on the inner wall of the upper portion WHU of the word line trench WH, the bottom surface of the insulation liner156may be at a level lower than that of the top surface of the word line WLB.

As shown inFIG.5, the word line WLB may include an extended portion WLEX at the upper portion thereof. The extended portion WLEX is at a vertical level higher than the inflection portion WHI of the word line trench WH and may be inside the upper portion WHU of the word line trench WH.

According to the example embodiments described above, due to the relatively large width of the upper portion WHU of the word line trench WH, the difficulty of an etchback process of forming the word line WLB may decrease, and the etchback process may be precisely controlled. Furthermore, a sufficiently large distance may be secured between word lines WLB in the lower portion WHL of the word line trench WH, and thus, an electrical coupling or a disturbance may be reduced or prevented. The integrated circuit device100B as described above may have excellent electrical performance.

FIG.6is a cross-sectional view of an integrated circuit device100C according to example embodiments.FIG.6is an enlarged view of a portion corresponding to the region CX1inFIG.2. InFIG.6, reference numerals that are the same as those inFIGS.1to5denote the same elements.

Referring toFIG.6, the insulation liner156(see, e.g.,FIG.5) may not be disposed on the inner walls of the upper portion WHU of the word line trench WH, and the top surface of a word line WLC may be at the third vertical level LV3 that is higher than the first vertical level LV1. The word line WLC may include an extended portion WLEX at an upper portion thereof. The extended portion WLEX is at a vertical level higher than the inflection portion WHI of the word line trench WH and may be inside the upper portion WHU of the word line trench WH.

An insulation capping layer154C may be inside the upper portion WHU of the word line trench WH, and the bottom surface of the insulation capping layer154C may be at a vertical level higher than that of the inflection portion WHI. The insulation capping layer154C may have substantially flat sidewalls.

The insulation liners156may function as an etching mask in a 2-stage etching operation for forming the word line trenches WH including the upper portion WHU and the lower portion WHL having different widths. In a manufacturing method according to example embodiments, the upper portion WHU of the word line trench WH may be formed first, and then the insulation liners156may be formed on the inner walls of the upper portion WHU. Next, the lower portion WHL of the word line trench WH may be formed by partially etching the substrate110by using the insulation liner156as an etching mask, wherein the insulation liner156may be completely removed. As the insulation liner156is removed, the insulation capping layer154C may have a relatively large width in the upper portion WHU of the word line trench WH.

FIG.7is a cross-sectional view of an integrated circuit device100D according to example embodiments.FIG.7is an enlarged view of a portion corresponding to the region CX1inFIG.2. InFIG.7, reference numerals that are the same as those inFIGS.1to6denote the same elements.

Referring toFIG.7, an insulation liner156D disposed on the inner walls of the upper portion WHU of the word line trench WH may have a thickness decreasing upward. For example, the insulation liner156D may have a shape tapered toward the upper portion WHU of the word line trench WH.

The insulation liner156D may function as an etching mask in a 2-stage etching operation for forming the word line trenches WH including the upper portion WHU and the lower portion WHL having different widths. In a manufacturing method according to example embodiments, the upper portion WHU of the word line trench WH may be formed first, and then the insulation liner156D may be formed on the inner walls of the upper portion WHU. Next, the lower portion WHL of the word line trench WH may be formed by partially etching the substrate110by using the insulation liner156D as an etching mask, and an etching operation for partially removing the insulation liner156D, thickness-wise, may be performed. Through the etching operation, a relatively large amount of the insulation liner156D may be removed near the entrance of the word line trench WH, and thus, the insulation liner156D may become thinner near the entrance of the word line trench WH.

FIGS.8to27are cross-sectional views sequentially showing operations of a method of manufacturing an integrated circuit device according to example embodiments. Referring toFIGS.8to27, a method of manufacturing the integrated circuit device100shown inFIGS.1to3will be described.

Referring toFIG.8, a plurality of device isolation trenches112T may be formed in a substrate110, and a device isolation layer112may be formed in the device isolation trenches112T, thereby defining a plurality of active regions AC in the substrate110. As shown inFIG.1, the active regions AC may be arranged to have long axes diagonal to a first direction X and a second direction Y.

Referring toFIG.9, a first hard mask layer210A and a second hard mask layer210B may be formed on the substrate110. The first hard mask layer210A and the second hard mask layer210B may include openings210H extending in the first direction X. Next, upper portions WHU of word line trenches WH may be formed in the substrate110by using the first hard mask layer210A and the second hard mask layer210B as an etching mask. An upper portion WHU of a word line trench WH may have a second width W2 (refer toFIG.3) in the second direction Y, wherein the second width W2 may be from about 5 nm to about 200 nm.

Referring toFIG.10, an insulation liner156may be conformally formed on inner walls of the upper portion WHU of the word line trench WH and the top surface of the second hard mask layer210B. In example embodiments, the insulation liner156may have an initial thickness TO from about 1 nm to about 30 nm in the second direction Y, but the inventive concept is not limited thereto. In example embodiments, the insulation liner156may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The insulation liner156may be formed through a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc.

Referring toFIG.11, an anisotropic etching operation is performed on the insulation liner156, thereby removing a portion of the insulation liner156on the second hard mask layer210B and a portion of the insulation liner156on the bottom of the upper portion WHU of the word line trench WH and leaving only a portion of the insulation liner156on the inner walls of the upper portion WHU of the word line trench WH.

Thereafter, a lower portion WHL of the word line trench WH is formed by expanding the word line trench WH in a vertical direction by using the portion of the insulation liner156on the inner walls of the upper portion WHU of the word line trench WH as an etching mask. For example, the lower portion WHL of the word line trench WH may have the first width W1 (refer toFIG.3) in the second direction Y, wherein the first width W1 may be less than the second width W2. In example embodiments, the first width W1 may be from about 3 nm to about 100 nm.

As the insulation liner156functions as an etching mask, the inner walls of the insulation liner156and the sidewalls of the lower portion WHL may be aligned with respect to each other, and the width of the lower portion WHL may be limited in correspondence to a distance between two insulation liners156arranged on the inner walls of one word line trench WH. For example, the first width W1 may correspond to a difference between the second width W2 of the upper portion WHU of the word line trench WH and twice the initial thickness TO of the insulation liner156(i.e., W1=W2−2T0).

The lower portion WHL is formed to have a smaller width than the upper portion WHU, and the inflection portion WHI may be defined between the lower portion WHL and the upper portion WHU. For example, the inflection portion WHI may refer to a portion of the word line trench WH in which the width of the word line trench WH changes discontinuously or may refer to a sidewall portion of the word line trench WH in which sidewall inclination varies rapidly. For example, the inflection portion WHI may be at the first vertical level LV1 (refer toFIG.3), and the inflection portion WHI may be at the same level as the bottom surface of the insulation liner156.

In example embodiments, at least a portion of the second hard mask layer210B may be removed in an operation for forming the lower portion WHL and, as shown inFIG.11, the top surface of the first hard mask layer210A may be exposed as the second hard mask layer210B is removed.

Referring toFIG.12, an etching operation for removing a portion of the insulation liner156on the sidewalls of the upper portion WHU of the word line trench WH, thickness-wise, may be performed. For example, after the etching operation is performed, the insulation liner156may have the first thickness T1 (refer toFIG.3) that is less than the initial thickness TO (refer toFIG.10). The first thickness T1 may be from about 0.5 nm to about 10 nm.

As the thickness of the insulation liner156is reduced from the initial thickness T0 to the first thickness T1, the top surface of the inflection portion WHI may be exposed inside the word line trench WH without being covered by the insulation liner156. Also, the upper portion WHU may expand in lateral directions with respect to the lower portion WHL.

In some other embodiments, a portion of the insulation liner156around the entrance of the word line trench WH is exposed more to an etching atmosphere and removed more in an etching operation for forming the lower portion WHL and/or an etching operation for removing a portion of the insulation liner156thickness-wise, and thus, the thickness of the insulation liner156may decrease upward. In this case, the insulation liner156D as described above with reference toFIG.7may be formed. Thereafter, a result structure in which the word line trench WH and the insulation liner156are formed may be cleaned.

Referring toFIG.13, gate insulation layers152may be formed on the inner walls of the word line trenches WH and on the first hard mask layer210A. In example embodiments, the gate insulation layers152may be conformally arranged on the inner walls of the word line trenches WH along the upper portions WHU (e.g., on the insulation liner156), the inflection portions WHI, and the lower portions WHL of the word line trenches WH. In example embodiments, the gate insulation layer152may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide/nitride/oxide (ONO) film, or a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film.

Referring toFIG.14, a word line metal layer WLP may be formed in the word line trenches WH. The word line metal layer WLP may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

Referring toFIG.15, a word line WL may be formed by performing an etchback operation on the word line metal layer WLP (refer toFIG.14). In example embodiments, the etchback operation may be performed, such that the word line WL has the top surface at a lower level than the inflection portion WHI. In this case, the word line WL may be formed by sequentially performing a first etchback step for removing the upper portion of the word line metal layer WLP to the same level as the inflection portion WHI and a second etchback step for removing the upper portion of the word line metal layer WLP to a level lower than that of the inflection portion WHI. However, the etchback operation is not limited thereto.

For example, as a portion of the word line metal layer WLP inside the upper portion WHU of the word line trench WH having a relatively large width is removed in the first etchback step, the difficulty of the overall etchback operation may be lowered. Therefore, the etchback operation may be precisely controlled. For example, the height of the word line WL may be adjusted precisely.

Referring toFIG.16, a gate capping layer154may be formed by forming an insulation layer (not shown) inside the word line trench WH, and by performing a planarization operation on the insulation layer so that the top surface of the substrate110is exposed. In the planarization operation, the first hard mask layer210A may be removed together. Thereafter, a plurality of source/drain regions (not shown) may be formed over the active regions AC by implanting impurity ions to both side portions of the word lines WL in the active regions AC.

Referring toFIG.17, a first lower insulation layer122and a second lower insulation layer124may be formed on the substrate110, and then a lower conductive layer132may be formed on the second lower insulation layer124. In example embodiments, the lower conductive layer132may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. For example, the lower conductive layer132may include polysilicon.

Referring toFIG.18, direct contact holes DCH exposing the active regions AC of the substrate110may be formed by forming a first mask pattern (not shown) on the lower conductive layer132, etching a portion of the lower conductive layer132exposed in an opening (not shown) of the first mask pattern, and etching a portion of the substrate110and a portion of the device isolation layer112exposed as a result of etching the portion of the lower conductive layer132.

Referring toFIG.19, the first mask pattern is removed, and direct contacts DC are formed in the direct contact holes DCH. In an example operation for forming the direct contacts DC, a conductive layer having a sufficient thickness to fill the direct contact holes DCH may be formed inside the direct contact holes DCH and on the lower conductive layer132, and the conductive layer may be etched back, such that the conductive layer only remains inside the direct contact holes DCH. The conductive layer may include polysilicon.

Referring toFIG.20, an intermediate conductive layer134and an upper conductive layer136may be sequentially formed on the lower conductive layer132and the direct contacts DC. The intermediate conductive layer134and the upper conductive layer136may each include TiN, TiSiN, W, tungsten silicide, or a combination thereof. In example embodiments, the intermediate conductive layer134may include TiN, TiSiN, or a combination thereof, whereas the upper conductive layer136may include W.

Referring toFIG.21, a plurality of bit line capping layers138extending in the second direction Y may be formed by forming an insulation layer (not shown) on the upper conductive layer136and patterning the insulation layer. The bit line capping layers138may include silicon nitride films.

Referring toFIG.22, the upper conductive layer136, the intermediate conductive layer134, and the lower conductive layer132may be patterned by using the bit line capping layers138as an etching mask. Therefore, the bit lines BL each including the lower conductive layer132, the intermediate conductive layer134, and the upper conductive layer136are formed. During a process of forming the bit lines BL, portions of the sidewalls of the direct contacts DC may be removed, and the direct contact holes DCH may be partially exposed.

Referring toFIG.23, direct contact spacers142may be formed on the sidewalls of the direct contacts DC, and bit line spacers140may be formed on sidewalls of the bit lines BL. In example embodiments, after an insulation layer (not shown) is conformally formed on the sidewalls and the top surfaces of the bit lines BL, an anisotropic etching operation may be performed on the insulation layer, thereby leaving the bit line spacers140on the sidewalls of the bit lines BL and leaving the direct contact spacers142on the sidewalls of the direct contacts DC. In example embodiments, the bit line spacers140and the direct contact spacers142may include a silicon nitride.

Referring toFIG.24, a plurality of insulation fences (not shown) may be formed between the bit lines BL. A plurality of buried contact holes BCH exposing the active regions AC of the substrate110between the bit lines BL are formed by removing portions of the second lower insulation layer124, the first lower insulation layer122, and the substrate110exposed in spaces between two adjacent insulation fences from among the insulation fences and between two bit lines BL.

Referring toFIG.25, a plurality of buried contacts BC filling the buried contact holes BCH between the bit lines BL and filling spaces between the bit lines BL are formed. Thereafter, metal silicide films144may be respectively formed on the buried contacts BC.

Referring toFIG.26, a conductive barrier film172and a landing pad conductive layer174covering exposed surfaces of the result structure are formed on the substrate110.

Referring toFIG.27, a plurality of landing pads LP may be formed by patterning the landing pad conductive layer174and the conductive barrier film172. As shown inFIG.1, the landing pads LP may have a pattern shape of a plurality of islands in a view from above. The landing pads LP may be formed to vertically overlap portions of the bit lines BL on the metal silicide films144.

As the landing pads LP are formed to have a pattern shape of a plurality of islands, an insulation space176S surrounding the landing pads LP may be formed. An insulation pattern176may be formed on inner walls of the insulation space176S by using an insulation material. The insulation pattern176may be formed through a spin coating process, a CVD process, a flowable CVD (FCVD) process, etc. Thereafter, capacitor lower electrodes (not shown) may be formed on the landing pads LP.

Generally, as a distance between adjacent word lines is reduced, a problem like a disturbance due to electrical coupling between the adjacent word lines adjacent occurs. When the width of a word line is reduced to prevent a disturbance, the difficulty of a process of forming a metal layer constituting a word line within a relatively narrow word line trench and an etchback process on the upper portion of the metal layer may significantly increase. Therefore, when precise control of an etchback process fails, deviation of heights of word lines becomes relatively large (or a window of heights of word lines becomes larger), and thus, it may be difficult for a plurality of buried channel transistors formed by word lines to have uniform electrical properties.

However, according to the embodiments above, the upper portion WHU of the word line trench WH may be formed with a relatively large width first, and then the lower portion WHL of the word line trench WH may be formed with a width less than that of the upper portion WHU by using the insulation liner156as an etching mask. Therefore, due to the relatively large width of the upper portion WHU of the word line trench WH, the difficulty of an etchback process of forming the word line WL may decrease, and the etchback process may be precisely controlled. Furthermore, a sufficiently large distance may be secured between the word lines WL in the lower portion WHL of the word line trench WH, and thus, an electrical coupling or a disturbance may be reduced or prevented. The integrated circuit device100as described above may have excellent electrical performance.

FIGS.28to31are cross-sectional views sequentially showing operations of a method of manufacturing an integrated circuit device according to example embodiments. Referring toFIGS.28to31, a method of manufacturing the integrated circuit device100C shown inFIG.6will be described.

First, the word line trench WH including the upper portion WHU, the lower portion WHL, and the inflection portion WHI may be formed by performing the operations described above with reference toFIGS.8to11. Here, the insulation liner156is disposed on the sidewalls of the upper portion WHU and may function as an etching mask for forming the lower portion WHL.

Referring toFIG.28, a portion of the insulation liner156on the sidewalls of the upper portion WHU of the word line trench WH may be removed. Therefore, a portion of the surface of the substrate110at the upper portion WHU of the word line trench WH may be exposed again.

Referring toFIG.29, gate insulation layers152may be formed on the inner walls of the word line trenches WH and on the first hard mask layer210A. In example embodiments, a gate insulation layer152may be conformally arranged on inner walls of the word line trench WH along the upper portion WHU, the inflection portion WHI, and the lower portion WHL of the word line trench WH.

Referring toFIG.30, a word line metal layer WLP may be formed in the word line trenches WH.

Referring toFIG.31, a word line WLC may be formed by performing an etchback operation on the word line metal layer WLP (refer toFIG.30).

In example embodiments, the etchback operation may be performed, such that the word line WLC has the top surface placed at a higher level than the inflection portion WHI. For example, as a portion of the word line metal layer WLP inside the upper portion WHU of the word line trench WH having a relatively large width is removed in etchback operation, the difficulty of the overall etchback operation may be lowered. Therefore, the etchback operation may be precisely controlled. For example, the height of the word line WLC may be adjusted precisely. Thereafter, the integrated circuit device1000may be completed by performing the operations described above with reference toFIGS.16to27.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.