Patent ID: 12243814

DESCRIPTION OF THE PREFERRED EMBODIMENT

Hereinafter, preferable embodiments of the present invention will be described in detail with reference to the accompanying drawings. Advantages and features of the present invention, and a method of achieving them, will become apparent with reference to preferable embodiments which are described in detail in conjunction with the accompanying drawings. Terms used in the description are provided not to limit the present invention but to describe the embodiments. In the embodiments, the singular form also includes the plural form unless otherwise specifically mentioned. Further, the terms ‘comprise’ and/or ‘comprising’ used in the specification are used in the sense of not precluding the presence or addition of at least one other component, step, operation, and/or element other than the stated components, steps, operations and/or elements.

FIG.8is a view illustrating the inside of a power module proposed in the present invention.

Cross-sectional areas of a gate line26and a source line28of a chip12through which current flows are increased compared toFIG.3illustrating a conventional power semiconductor power module. However, as shown inFIG.2, increasing thicknesses of upper and lower sides of a direct bond copper (DBC)14is limited. Accordingly, Cu bonding is used to increase a current cross-sectional area by overcoming the limited DBC thickness and increasing widths of the gate line and the source line. Further, a gate resistor13for an upper chip M1and a gate resistor13′ for a lower chip M10are rotated by 90° unlike other resistors to form parasitic inductances similar to those of chips M2and M9respectively adjacent to the chips M1and M10.

In a specific description, inFIG.8, a DBC area at a left side becomes wider than a DBC area at a right side with respect to a portion “B” vertically indicated on an upper chip arrangement part. To this end, conductors30and32such as several strands of Cu or the like are bonded to the lines26and28. As shown inFIG.8, the gate line26is bonded to be wider than the source line28, and to this end, five strands of conductor30are bonded to the gate line26, and three strands of conductor32are bonded to the source line28.

As another embodiment, in addition to Cu bonding, Al bonding and bonding using other various metals may be used. Further, a method of applying the same number of bonding strands to the gate line26and the source line28and performing soldering on the bonding to expand an area through which the current flows is also possible. Various types of solders may be used for a solder in this case.

As still another embodiment, the number of copper bonding strands may be increased to increase the area as the distance increases from a gate pin and a source pin. That is, inFIG.8, more strands of bonding are applied to the gate line and the source line of M1compared to the gate line and the source line of M4. Likewise, more strands of bonding are applied to the gate line and the source line of M10compared to the gate line and the source line of M6.

Like the above, in order to check a current balance of the power module composed of the chips which are connected in parallel according to the present invention, simulation is performed using a circuit the same as the circuit inFIG.5. A parasitic inductance of the power module having the configuration inFIG.8is extracted through “Q3D” program by Ansys and added to each gate.

According to a result of the experiment, in a description with respect to the upper arrangement, M5closest to the gate pin and the source pin was 15 nH and M1most distant from the gate pin and the source pin was 24.1 nH. Compared to a conventional design inFIG.3, the maximum and minimum difference between parasitic inductance values was reduced from 15.1 nH to 9.1 nH. Even in the lower arrangement having the same configuration, M6closest to the gate pin and the source pin was 15 nH and M10most distant from the gate pin and the source pin was 24.1 nH. The parasitic inductance values of the remaining chips are as follows: M2is 21.9 nH, M3is 19.2 nH, M4is 16.5 nH, M7is 16.5 nH, M8is 19.2 nH, and M9is 21.9 nH.

FIG.9is a waveform diagram of “OrCAD” simulation of the circuit diagram inFIG.5, to which the present invention is applied. An upper waveform indicates a current flowing through each chip and a lower waveform indicates a gate voltage of each chip, which are obtained from the measurement points in the circuit diagram ofFIG.5.

FIG.10illustrates an enlarged waveform of a portion “C” indicated in FIG.9. The indicated portion is a waveform when a switch of the chip is turned off. As shown inFIG.7, square (□) marked lines indicate the most distant chip, and circle (◯) marked lines indicate the closest chip. It can be seen that the most distant chip is more quickly turned off compared to other chips in the gate voltage waveform at a lower side inFIG.10, and the current waveform at an upper side is also formed lower than those of other chips. A maximum current difference between M6(17.75 A) and M10(18.15 A) is 0.4 A, and a current deviation of 2% is present. Compared toFIG.7which is the simulation waveform of the previously designed power module, it can be seen that the current deviation of 2% is improved.

Although the present invention has been described in detail through preferable embodiments of the present invention, those skilled in the art may understand that the present invention may be embodied in specific forms other than contents disclosed in the specification without changing the technical spirit or essential features of the present invention.