Patent ID: 12243610

DETAILED DESCRIPTION

In some implementations, a memory device may include an interconnected stack of multiple semiconductor dies (e.g., semiconductor chips, memory dies), which each may support a functionality of the memory device. For example, each memory die may include an array of memory cells and various circuitry (e.g., access circuitry, control circuitry, signaling circuitry) that supports various access operations (e.g., write operations, read operations) on the array of memory cells. Such a memory device may provide an aggregate storage capacity or throughput of multiple memory dies in a stacked arrangement, which may leverage performance characteristics of multiple semiconductor substrates, such as transistor performance characteristics associated with a crystalline semiconductor of a respective semiconductor substrate.

Memory dies configured for integration in a multiple-die stack may include contacts (e.g., electrical contacts, contact pads) that support signaling between or via one or more other memory dies in a stack. In some examples, performance characteristics of such memory dies may be evaluated (e.g., tested, validated, confirmed) before or as part of assembly in a multiple-die stack using such contacts. However, probing of contacts of a memory die (e.g., by an evaluation probe) may cause damage to the contacts (e.g., deformation, composition changes), which may render the contacts less effective or inoperable or less effective for some types of interconnections between memory dies.

In accordance with examples as disclosed herein, a memory die may be configured with parallel interfaces (e.g., parallel sets of contacts) that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a first memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack (e.g., in a mission mode). The first memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations (e.g., in a test mode, for contact with an evaluation probe), which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which will improve capabilities for supporting a multiple-die stack in a memory device. For example, the first set of contacts may be configured with a smaller cross-sectional area (e.g., contact area), with a reduced spacing, with a greater quantity of contacts, or any combination thereof, which may be supported by relatively precise techniques for bonding between contacts of opposed memory dies that might otherwise be unavailable in the presence of damage (e.g., due to evaluation probing). In some examples, such improvements to the first set of contacts will support a higher throughput (e.g., a higher bit rate, a higher burst rate) of the memory device, a reduced power consumption of the memory device, or a reduced heating of the memory device, among other benefits.

Features of the disclosure are initially described in the context of systems and dies as described with reference toFIGS.1and2. Features of the disclosure are described in the context of a data path, a device, and a layout with reference toFIGS.3through5. These and other features of the disclosure are further illustrated by and described with reference to a flowchart that relates to memory with parallel main and test interfaces as described with reference toFIG.6.

FIG.1illustrates an example of a system100that supports memory with parallel main and test interfaces in accordance with examples as disclosed herein. The system100may include a host device105, a memory device110, and a plurality of channels115coupling the host device105with the memory device110. The system100may include one or more memory devices110, but aspects of the one or more memory devices110may be described in the context of a single memory device (e.g., memory device110).

The system100may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other systems. For example, the system100may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, or the like. The memory device110may be a component of the system100that is operable to store data for one or more other components of the system100.

Portions of the system100may be examples of the host device105. The host device105may be an example of a processor (e.g., circuitry, processing circuitry, a processing component) within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other stationary or portable electronic device, among other examples. In some examples, the host device105may refer to the hardware, firmware, software, or any combination thereof that implements the functions of an external memory controller120. In some examples, the external memory controller120may be referred to as a host (e.g., host device105).

A memory device110may be an independent device or a component that is operable to provide physical memory addresses/space that may be used or referenced by the system100. In some examples, a memory device110may be configurable to work with one or more different types of host devices. Signaling between the host device105and the memory device110may be operable to support one or more of: modulation schemes to modulate the signals, various pin configurations for communicating the signals, various form factors for physical packaging of the host device105and the memory device110, clock signaling and synchronization between the host device105and the memory device110, timing conventions, or other functions.

The memory device110may be operable to store data for the components of the host device105. In some examples, the memory device110(e.g., operating as a secondary-type device to the host device105, operating as a dependent-type device to the host device105) may respond to and execute commands provided by the host device105through the external memory controller120. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

The host device105may include one or more of an external memory controller120, a processor125, a basic input/output system (BIOS) component130, or other components such as one or more peripheral components or one or more input/output controllers. The components of the host device105may be coupled with one another using a bus135.

The processor125may be operable to provide functionality (e.g., control functionality) for the system100or the host device105. The processor125may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, the processor125may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or an SoC, among other examples. In some examples, the external memory controller120may be implemented by or be a part of the processor125.

The BIOS component130may be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the system100or the host device105. The BIOS component130may also manage data flow between the processor125and the various components of the system100or the host device105. The BIOS component130may include instructions (e.g., a program, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

The memory device110may include a device memory controller155and one or more memory dies160(e.g., memory chips) to support a capacity (e.g., a desired capacity, a specified capacity) for data storage. Each memory die160may include a local memory controller165and a memory array170. A memory array170may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells, with each memory cell being operable to store one or more bits of data. A memory device110including two or more memory dies160may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

The device memory controller155may include components (e.g., circuitry, logic) operable to control operation of the memory device110. The device memory controller155may include hardware, firmware, or instructions that enable the memory device110to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device110. The device memory controller155may be operable to communicate with one or more of the external memory controller120, the one or more memory dies160, or the processor125. In some examples, the device memory controller155may control operation of the memory device110described herein in conjunction with the local memory controller165of the memory die160.

A local memory controller165(e.g., local to a memory die160) may include components (e.g., circuitry, logic) operable to control operation of the memory die160. In some examples, a local memory controller165may be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller155. In some examples, a memory device110may not include a device memory controller155, and a local memory controller165or the external memory controller120may perform various functions described herein. As such, a local memory controller165may be operable to communicate with the device memory controller155, with other local memory controllers165, or directly with the external memory controller120, or the processor125, or any combination thereof. Examples of components that may be included in the device memory controller155or the local memory controllers165or both may include receivers for receiving signals (e.g., from the external memory controller120), transmitters for transmitting signals (e.g., to the external memory controller120), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other components operable for supporting described operations of the device memory controller155or local memory controller165or both.

The external memory controller120may be operable to enable communication of information (e.g., data, commands, or both) between components of the system100(e.g., between components of the host device105, such as the processor125, and the memory device110). The external memory controller120may process (e.g., convert, translate) communications exchanged between the components of the host device105and the memory device110. In some examples, the external memory controller120, or other component of the system100or the host device105, or its functions described herein, may be implemented by the processor125. For example, the external memory controller120may be hardware, firmware, or software, or some combination thereof implemented by the processor125or other component of the system100or the host device105. Although the external memory controller120is depicted as being external to the memory device110, in some examples, the external memory controller120, or its functions described herein, may be implemented by one or more components of a memory device110(e.g., a device memory controller155, a local memory controller165) or vice versa.

The components of the host device105may exchange information with the memory device110using one or more channels115. The channels115may be operable to support communications between the external memory controller120and the memory device110. Each channel115may be an example of a transmission medium that carries information between the host device105and the memory device110. Each channel115may include one or more signal paths (e.g., a transmission medium, a conductor) between terminals associated with the components of the system100. A signal path may be an example of a conductive path operable to carry a signal. For example, a channel115may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host device105and a second terminal at the memory device110. A terminal may be an example of a conductive input or output point of a device of the system100, and a terminal may be operable to act as part of a channel.

Channels115(and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, the channels115may include one or more command and address (CA) channels186, one or more clock signal (CK) channels188, one or more data (DQ) channels190, one or more other channels192, or any combination thereof. In some examples, signaling may be communicated over the channels115using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

In some implementations, a memory device110may include multiple memory dies160that are configured in a stacked configuration (e.g., with one memory die160stacked over another memory die160). Memory dies160that are configured in such aa manner may include contacts (e.g., electrical contacts, contact pads) that support signaling between or via one or more other memory dies160in the stack. In some examples, performance characteristics of such memory dies160may be evaluated (e.g., tested, validated, confirmed) before or as part of assembly in a multiple-die stack using such contacts. However, probing of contacts of a memory die160(e.g., by an evaluation probe) may cause damage to the contacts (e.g., deformation, composition changes), which may render the contacts less effective or inoperable for some types of interconnections between memory dies160in the memory device110.

In accordance with examples as disclosed herein, memory dies160may be configured with parallel interfaces (e.g., parallel sets of contacts) that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack, in response to commands from a host device105). For example, a memory die160may include a first set of one or more contacts that support communicating signaling with or via another memory die160, or a die associated with a device memory controller155, in a multiple-die stack (e.g., in a mission mode). The memory die160may also include a second set of one or more contacts that support probing for pre-assembly evaluations (e.g., in a test mode, for contact with an evaluation probe), which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed on the memory die160using the second set of contacts without damaging the first set of contacts, which will improve capabilities of the memory die160for supporting a multiple-die stack in a memory device110. For example, the first set of contacts may be configured with a smaller cross-sectional area (e.g., contact area), with a reduced spacing, with a greater quantity of contacts, or any combination thereof, which may be supported by relatively precise techniques for bonding between contacts of opposed memory dies160that might otherwise be unavailable in the presence of damage (e.g., due to evaluation probing). In some examples, such improvements to the first set of contacts will support a higher throughput (e.g., a higher bit rate, a higher burst rate) of the memory device110, a reduced power consumption of the memory device110, or a reduced heating of the memory device110, among other benefits.

FIG.2illustrates an example of a memory die200that supports memory with parallel main and test interfaces in accordance with examples as disclosed herein. The memory die200may be an example of the memory dies160described with reference toFIG.1. In some examples, the memory die200may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die200may include one or more memory cells205that may be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell205may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell205(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells205may be arranged in an array, such as a memory array170described with reference toFIG.1.

In some examples, a memory cell205may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed. The memory cell205may include a logic storage component, such as capacitor230, and a switching component235(e.g., a cell selection component). The capacitor230may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor230may be coupled with a voltage source240, which may be the cell plate reference voltage, such as Vpl, or may be ground, such as Vss.

The memory die200may include access lines (e.g., word lines210, digit lines215) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell205and may be used to perform access operations on the memory cell205. In some examples, word lines210may be referred to as row lines. In some examples, digit lines215may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or their analogues, are interchangeable without loss of understanding. Memory cells205may be positioned at intersections of the word lines210and the digit lines215.

Operations such as reading and writing may be performed on the memory cells205by activating access lines such as a word line210or a digit line215. By biasing a word line210and a digit line215(e.g., applying a voltage to the word line210or the digit line215), a single memory cell205may be accessed at their intersection. The intersection of a word line210and a digit line215in a two-dimensional or in a three-dimensional configuration may be referred to as an address of a memory cell205. Activating a word line210or a digit line215may include applying a voltage to the respective line.

Accessing the memory cells205may be controlled through a row decoder220, or a column decoder225, or any combination thereof. For example, a row decoder220may receive a row address from the local memory controller260and activate a word line210based on the received row address. A column decoder225may receive a column address from the local memory controller260and may activate a digit line215based on the received column address.

Selecting or deselecting the memory cell205may be accomplished by activating or deactivating the switching component235using a word line210. The capacitor230may be coupled with the digit line215using the switching component235. For example, the capacitor230may be isolated from digit line215when the switching component235is deactivated, and the capacitor230may be coupled with digit line215when the switching component235is activated.

The sense component245may be operable to detect a state (e.g., a charge) stored on the capacitor230of the memory cell205and determine a logic state of the memory cell205based on the stored state. The sense component245may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell205. The sense component245may compare a signal detected from the memory cell205to a reference250(e.g., a reference voltage). The detected logic state of the memory cell205may be provided as an output of the sense component245(e.g., to an input/output255), and may indicate the detected logic state to another component of a memory device (e.g., a memory device110) that includes the memory die200.

The local memory controller260may control the accessing of memory cells205through the various components (e.g., row decoder220, column decoder225, sense component245). The local memory controller260may be an example of the local memory controller165described with reference toFIG.1. In some examples, one or more of the row decoder220, column decoder225, and sense component245may be co-located with the local memory controller260. The local memory controller260may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller120associated with a host device105, another controller associated with the memory die200), translate the commands or the data (or both) into information that can be used by the memory die200, perform one or more operations on the memory die200, and communicate data from the memory die200to a host (e.g., a host device105) based on performing the one or more operations. The local memory controller260may generate row signals and column address signals to activate the target word line210and the target digit line215. The local memory controller260also may generate and control various signals (e.g., voltages, currents) used during the operation of the memory die200. In general, the amplitude, the shape, or the duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory die200.

The local memory controller260may be operable to perform one or more access operations on one or more memory cells205of the memory die200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller260in response to various access commands (e.g., from a host device105). The local memory controller260may be operable to perform other access operations not listed here or other operations related to the operating of the memory die200that are not directly related to accessing the memory cells205.

In accordance with examples as disclosed herein, the memory die200may be configured with parallel interfaces (e.g., parallel sets of contacts) that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack, in response to commands from a host device105). For example, the memory die200may include a first set of one or more contacts that support communicating signaling with or via another memory die200, or a die associated with a device memory controller155, in a multiple-die stack (e.g., in a mission mode). The memory die200may also include a second set of one or more contacts that support probing for pre-assembly evaluations (e.g., in a test mode, for contact with an evaluation probe), which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed on the memory die200using the second set of contacts without damaging the first set of contacts, which will improve capabilities of the memory die200for supporting a multiple-die stack in a memory device110. For example, the first set of contacts may be configured with a smaller cross-sectional area (e.g., contact area), with a reduced spacing, with a greater quantity of contacts, or any combination thereof, which may be supported by relatively precise techniques for bonding between contacts of opposed memory dies200that might otherwise be unavailable in the presence of damage (e.g., due to evaluation probing). In some examples, such improvements to the first set of contacts will support a higher throughput (e.g., a higher bit rate, a higher burst rate) of the memory device110, a reduced power consumption of the memory device110, or a reduced heating of the memory device110, among other benefits.

FIG.3illustrates an example of a data path300that supports memory with parallel main and test interfaces in accordance with examples as disclosed herein. The data path300illustrates an example of circuitry of a memory die (e.g., a memory die160, a memory die200) that supports a communication of data between array circuitry305and a set of contacts360. The array circuitry305may include a set of one or more memory arrays (e.g., a memory array170, memory cells205), as well as circuitry configured to access the array of memory cells (e.g., a row decoder220, a column decoder225, a sense component245). The contacts360may be configured for communicating signals from or to the memory die, and may include various configurations of conductive interfaces (e.g., connection pads, solder pads, signaling contacts, bonding contacts, metal landing pads) that support a communicative coupling with another component.

Signals to and from the array circuitry305may be routed via signal paths315of a bus310(e.g., a first data bus), which may be a relatively dense metal interconnect region of a memory die, and which may be referred to as a global input/output (GIO) bus or a GIO interconnect. Signals of the bus310may be driven from the array circuitry305and detected by conversion circuitry320, which may be supported by one or more analog data sense amp (DSA) circuits of the conversion circuitry320. In some examples, such DSA circuits may translate a low-swing signal (e.g., signaling associated with a relatively smaller voltage range or relatively smaller drive strength, associated with signaling of the array circuitry305, analog signaling) to a full swing signal (e.g., signaling associated with a relatively larger voltage range or relatively larger drive strength, digital signaling) associated with a bus330(e.g., a second data bus), which may be referred to as a data read-write (DRW) bus. In some examples, such a translation of low-swing signaling may be implemented in the conversion circuitry320because an amplification ability of the array circuitry305(e.g., an amplification ability of a sense component245), or a parasitic loading of the bus310(e.g., of the signal paths315), or a combination thereof may not support signal transitions occurring in accordance with a specified performance criteria (e.g., a speed criteria, a latency criteria, a criteria for signaling communicated to or from a memory device110that includes the data path300). In some examples, each signal path315of the bus310may involve a separate DSA circuit of the conversion circuitry320. The conversion circuitry320may also include write driver circuitry, which may support writing information to memory cells205of the array circuitry305.

The conversion circuitry320may also include latches, drivers, and multiplexers that are compatible with full-swing signaling. For example, control logic may be implemented to provide clock signals to latches of the conversion circuitry such that a quantity of signals (e.g., a quantity of signal paths315) on the bus310may be divided by the quantity of latches connected to the bus330. In the example of data path300, each signal path335of the bus330may be associated with two signal paths315of the bus310, such that signaling of the bus330(e.g., DRW signaling) may be supported by latches, drivers, and multiplexers operating on the bus330at twice the frequency of transitions of the signaling on the bus310(e.g., GIO signaling) when memory cells of the array circuitry305are being read. Accordingly, a transfer of signals on the bus310to one-half the quantity of signals on the bus330may be supported by an interconnect density (e.g., pitch) of the bus330being half of the interconnect density of the bus310. Such a ratio may also be implemented in the opposite direction, in which case signals driven on the bus330may be translated by the conversion circuitry320from higher bandwidth on the bus330to lower bandwidth on the bus310(e.g., when memory cells of the array circuitry305are being written). Although some examples of the data path300may be configured with a 2:1 ratio between the bus310and the bus330, other examples of a data path in accordance with examples as disclosed herein may implement different ratios between a bus310and a bus330.

In some examples, packaging of a memory die that includes the data path300may utilize I/O circuitry340, including at least drivers345, which may be implemented to drive electrical signals through the contacts360via a bus355(e.g., a third data bus) and, in some examples, through solder ball connections to an external interconnect. However, I/O circuitry340may occupy a relatively large area of the memory die, which may limit a density of contacts360, and accordingly may limit a bandwidth of signals communicated to or from the memory die that includes the data path300(e.g., signals via contacts360). For example, a bandwidth of signaling with a may be a function of the interconnect density (e.g., metal pitch and unit area) and a frequency of signal transitions, but an interconnect density of the bus330may be greater than a density of the contacts360(e.g., relatively granular I/O landing pads). Thus, to maintain bandwidth of data transfer between the on-die interconnect (e.g., of the bus330) and external interconnects (e.g., of the contacts360), the I/O circuitry340may also include or be associated with respective serializer/deserializer components350(e.g., a SERDES) associated with each contact360. By including serializer/deserializer components350, the density of contacts360may be reduced for a given bandwidth by supporting a proportional increase in the frequency of signals conveyed via contacts360. Although some examples of the data path300may be configured with a 4:1 ratio between signal paths of the bus330and contacts360, other examples of a data path in accordance with examples as disclosed herein may implement different ratios between signal paths of a bus330and contacts360.

In some examples, performance characteristics of a memory die that includes the data path300may be evaluated via contacts360, which may include an evaluation before the contacts360are coupled with corresponding contacts of another component (e.g., of another semiconductor die). For example, an evaluation probe may establish an electrical coupling with contacts360(e.g., based on physical contact between the evaluation probe and the contacts360), and may issue commands to evaluate various operations or configurations of the array circuitry305(e.g., including write commands and read commands to evaluate performance of a memory array of the array circuitry305). However, probing of the contacts360may cause damage such as deformation of the contacts360, or a change in material composition of the contacts360, which may render the contacts360less effective or inoperable for some types of interconnections between stacked memory dies160of a memory device110.

In accordance with examples as disclosed herein, a memory die that includes the data path300may be configured with parallel interfaces (e.g., parallel sets of contacts) that may separately support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack, in response to commands from a host device105). For example, at least some of the contacts of a memory die may be configured to support evaluation operations, but may not be configured for interconnection with another semiconductor die. Rather, to support such interconnection, the memory die may include a set of one or more other contacts, which may be electrically isolated from a set of one or more contacts used for evaluation operations. By including another set of contacts for such interconnection, evaluation operations such as probing may be performed without associated damage impairing an interconnection between semiconductor dies, which may improve design flexibility for configuring interconnection among the semiconductor dies.

In some examples of the described techniques, a memory die may include multiple sets of contacts360(e.g., redundant sets, duplicate sets), such that a first set of contacts360may be used for evaluation operations (e.g., via a first set of I/O circuitry340) and a second set of contacts360may be used for interconnection with another semiconductor die (e.g., via the first set of I/O circuitry340, via a second set of I/O circuitry340). In some other examples, a memory die may include a set of contacts360for evaluation operations (e.g., using signaling via I/O circuitry340), and a set of other contacts (not shown) for interconnection that supports a different signaling configuration (e.g., a different driver configuration, a different multiplexing configuration). In some other examples, a memory die may include a set of contacts360for interconnection (e.g., using signaling via I/O circuitry340), and a set of other contacts (not shown) for evaluation operations that supports a different signaling configuration (e.g., a different driver configuration, a different multiplexing configuration).

In some examples, to support different sets of interfaces for evaluation and interconnection, a first set of contacts may be associated with signaling over a bus330via serializer/deserializer components350, whereas a second set of contacts may not be associated with (e.g., may omit) serializer/deserializer components350. Additionally, or alternatively, a first set of contacts may be associated with signaling via drivers345, whereas a second set of contacts may not be associated with (e.g., may omit) drivers345. For example, a set of contacts for interconnection with another semiconductor die may be implemented with a direct connection to a bus330(e.g., a direct DRW interconnection, which may implement drivers of conversion circuitry320to support signaling via interconnection contacts), or may be implemented with a direct connection to a bus310(e.g., a direct GIO interconnection, which may implement drivers of array circuitry305, or signal amplification of a sense component245, among other circuitry to support signaling via interconnection contacts), or some combination thereof. In some examples, such techniques may involve configurations of I/O circuitry that is different than the I/O circuitry340(e.g., which may be used to support an evaluation of the memory die via contacts360). In some examples, a relatively higher density direct interconnection with the bus330or the bus310may be facilitated by not involving the same contacts for die interconnection and evaluation, which may also overcome limitations related to probe contact density (e.g., with or without associated evaluation probe damage), among other issues.

In some examples, I/O circuitry340associated with contacts360used for evaluation operations may be deactivated after performing the evaluation operations, which may include disabling such I/O circuitry340(e.g., by removing power from the I/O circuitry or otherwise deselecting the I/O circuitry340), or electrically disconnecting such I/O circuitry340from the bus330(e.g., by opening one or more fused connections between the I/O circuitry340and the bus330). In some examples, such techniques will reduce a power consumption of a memory die, or will reduce an associated heating of a memory die, compared with techniques that involve I/O circuitry340for communicating signaling via contacts360(e.g., compared to techniques that use I/O circuitry340for both evaluation operations and for signaling among semiconductor dies of a multiple-die stack).

FIG.4illustrates an example of a device400that supports memory with parallel main and test interfaces in accordance with examples as disclosed herein. The device400includes memory dies405-aand405-b(e.g., a stack of memory dies, vertically interconnected memory dies, semiconductor dies), which may be examples of memory dies as described herein. In some examples, the device400may be an example of a memory device110described with reference toFIG.1, although the device may be configured differently than a memory device110(e.g., as an integrated assembly including one or more memory dies integrated with one or more processor dies). Although described with reference to two memory dies405, the device400may include any quantity or one or more memory dies405.

Each of the memory dies405may include array circuitry430, which may include a set of one or more memory arrays and various circuitry configured to operate the set of memory arrays. In some examples, array circuitry430may be an example of or may include array circuitry305. Array circuitry430also may include various circuitry that supports communication of signaling outside the memory dies405, such as a bus310, conversion circuitry320, a bus330, I/O circuitry340, or a bus355, or any combination thereof.

Each of the memory dies405includes one or more contacts420that support routing signals external to the respective memory die405(e.g., contacts configured for communicative coupling with contacts of another semiconductor die, when assembled in a multiple-die stack). For example, the memory die405-amay include a contact420-a-1(e.g., on a bottom surface of the memory die405-a) and a contact420-a-2(e.g., on a top surface of the memory die405-a), each of which may support an electrical connection with array circuitry430-athrough a dielectric portion410-aof the memory die405-a. Further, the memory die405-bmay include a contact420-b-1(e.g., on a bottom surface of the memory die405-b) and a contact420-b-2(e.g., on a top surface of the memory die405-a), each of which may support an electrical connection with array circuitry430-bthrough a dielectric portion410-bof the memory die405-b. Although each of the memory dies405are illustrated with one contact420on a top surface and one contact420on a bottom surface, a memory die405of the device400may include any quantity of one or more contacts420on a top surface, or any quantity of one or more contacts420on a bottom surface, or may omit contacts420on one of a bottom surface or a top surface (e.g., omitting contact420-b-2), among other configurations. Moreover, although each of the contacts420are illustrated as being electrically connected with array circuitry430of a given memory die405, in some examples, contacts420may be configured to support a bypass connection through a memory die405(e.g., to communicate signaling through the memory die405without involvement or modification by the array circuitry430, or otherwise bypassing the array circuitry430or functional components thereof).

In some examples, the device400may include a substrate450, which may be a semiconductor die, or may be an organic substrate such as a printed circuit board (PCB), among other examples. A substrate450may include substrate circuitry455, which may support various operations with the memory dies405. For example, the substrate circuitry455may include a device memory controller155, or a processor (e.g., of a processor die), among other circuitry, which may be coupled with one or more contacts460that are operable for communicating signaling with the memory die405-a, or the memory die405-b, or both. Although the substrate450is illustrated with a single contact460, a substrate of the device400may include any quantity of one or more contacts460, which may include respective sets of one or more contacts460that are dedicated to signaling with a given one of the memory dies405. In some examples, the substrate450may also include contacts (not shown) configured for conveying signaling to or from the device400, such as with a host device105(e.g., via channels115) or other interfacing device.

The contacts420may be configured for various interconnection techniques between memory dies405, or between a memory die405and a substrate450, where applicable. For example, operations to manufacture the device400may include establishing a communicative coupling (e.g., an electrical coupling, a mechanical coupling, a bonding) between the contact420-b-1and the contact420-a-2, and establishing a communicative coupling between the contact420-a-1and the contact460. In some examples, contacts420, or contacts460, or both may be metal landing pads (e.g., at a relatively granular spacing) that accommodate soldered connections between memory dies405. In some other examples, contacts420, or contacts460, or both may be configured to support direct connections (e.g., metal-to-metal connections) without a separate bonding material (e.g., a direct connection between material of the contact420-a-2and material of the contact420-b-1, without a solder material, which may be referred to as a hybrid bond), which may be formed using pressure, heat, vibration, or any combination thereof. In some examples, a direct metal-to-metal connection may support higher density interconnection (e.g., supporting a relatively higher quantity of contacts420or contacts460, supporting contacts420or460with a relatively smaller area, supporting location of contacts420or460in a relatively smaller area, or various combinations thereof) than would be supported by other techniques, such as soldered connections. For example, metal-to-metal connections may support contacts420being coupled with a bus330of array circuitry430, or a bus310of array circuitry430, among other examples. Such techniques may be combined with through-silicon vias (TSVs), for which an interconnect may be routed vertically through holes formed in passivation layers of the memory dies405. In some examples, TSV implementations may avoid horizontal metal interconnection between memory dies that might otherwise be connected in a planar manner, which will conserve area and power associated with parasitic losses, or electrical impedance, or other phenomena. In some examples, relatively fine-pitch bonding via contacts420or contacts460may enable high-density interconnect for stacking the memory dies405, including direct bonding to a processor (e.g., of a substrate450, coupled with a substrate450) for heterogeneous systems contained in the same package.

In some examples, stacking of memory dies405using fine-pitch bonding via contacts420, or such stacking with a substrate450via contacts460, where applicable, may overcome some electrical and physical limitations related to some techniques for interconnection (e.g., limitations related to solder ball techniques), which may support interconnections via contacts420or contacts460performing similarly to die-level metal connections. However, fine-pitch bonding may be associated with challenges for probing and testing stacked systems such as the device400. For example, some probing techniques may involve a temporary connection to the testing equipment through contacts of a semiconductor die. In some examples, probing contacts420may be impractical, because the pitch and size of the contacts420may be incompatible with probe equipment. Moreover, physically contacting the contacts420with test signal probes may damage the contacts420, which may cause the contacts420to be less effective or inoperable for interconnection (e.g., for metal-to-metal interconnection).

To support evaluation of the memory dies405without probing the contacts420, each memory die405may also include one or more contacts440that are coupled with the array circuitry of the memory die405. The contacts440may be configured for testing operations of memory dies405(e.g., before or as part of assembly in the device400). In some examples, the contacts440may not be used for signaling when the memory dies405are assembled in the device400and, alternatively, may be configured for contact by an evaluation probe prior to such assembly.

The contacts440may be configured for electrical isolation from adjacent memory dies405(e.g., another memory die405of the stack, which may be directly or indirectly adjacent to or in contact with the contacts440), or from a substrate450, where applicable, or both. For example, as illustrated, the contact440-aof the memory die405-amay be configured to be in contact with the dielectric portion410-bof the memory die405-b, and the contact440-bof the memory die405-bmay be configured to be in contact with a dielectric portion470of the device400, which may be a dielectric coating (e.g., a conformal coating) over at least the stack of memory dies405. In some examples, the contacts440may be configured to be physically inaccessible after assembly in the device400(e.g., physically covered by another component, physically covered by a dielectric covering).

In some examples, the contacts420and the contacts440may be associated with different geometric characteristics (e.g., different cross-sectional areas, different contact areas, different pitch dimensions). For example, the contacts420may be relatively small, or may be separated by a relatively small pitch dimension (e.g., on the order of a pitch of a bus310, on the order of a pitch of a bus330, a pitch of 12 microns or less, a pitch of 6 microns or less, a pitch of 3 microns or less), or both, which may support a relatively greater quantity of contacts420in a given area (e.g., to support a higher quantity of signal paths that may support a relatively higher throughput of the device400, to support a relatively high interconnection density). The contacts420may be relatively large, or may be separated by a relatively large pitch dimension (e.g., on the order of a pitch of a bus355, a pitch of 12 microns or more, a pitch of 6 microns or more, a pitch of 3 microns or more), or both, which may facilitate a communicative coupling with an evaluation probe. In some examples, contacts420and contacts440may be located in different regions of a memory die405. For example, contacts420may be located relatively close to memory arrays or supporting circuitry of the array circuitry430(e.g., to preferentially reduce signal degradation in the as-assembled condition), whereas contacts460may be located relatively farther from the array circuitry430in an area reserved for probing (e.g., relatively close to an evaluation interface of the array circuitry430, such as an IEEE1500 interface).

In some examples, a memory die405may include subsets of contacts for different purposes. For example, to support operations in an assembled state of the device400(e.g., to support signaling from or via a substrate450, to support signaling with a device memory controller155of the substrate circuitry455), a memory die405may include a subset of contacts420that are configured for control signaling associated with operating the memory die405(e.g., configuration signaling, commands to access a memory array of the array circuitry430), a subset of contacts420that are configured for data signaling associated with operating the memory die405(e.g., via a data bus), or a subset of contacts that are associated with receiving power, or various combinations thereof. To support evaluation operations (e.g., prior to assembly of the device400, to support signaling from or via an evaluation probe), a memory die405may include a subset of contacts440that are configured for control signaling associated with evaluating the memory die405(e.g., configuration signaling, commands to access a memory array of the array circuitry430), a subset of contacts440that are configured for data signaling associated with evaluating the memory die405(e.g., via a data bus), or a subset of contacts that are associated with receiving power, or various combinations thereof. In some examples, the contacts420and the contacts440may be coupled with different data buses of a memory die405. For example, contacts440may be coupled with a bus355(e.g., a relatively granular bus of a memory die405, in which case the contacts440may be an example of contacts360), whereas contacts420may be coupled with a bus330, or a bus310, among other examples.

FIG.5illustrates an example of a layout500that supports memory with parallel main and test interfaces in accordance with examples as disclosed herein. The layout500illustrates an example of circuitry that may be implemented in a semiconductor die, such as a memory die (e.g., a memory die160, a memory die200, a memory die405), which may include a first set of contacts configured for communicative coupling with another semiconductor die (e.g., as assembled in stack of semiconductor dies) and a second set of contacts configured for evaluation operations of the semiconductor die (e.g., before or as part of assembly in a stack of semiconductor dies).

The layout500includes a set of memory arrays505, which each may include an array of memory cells (e.g., memory cells205) in accordance with various memory architectures. For example, memory cells of the memory arrays505may include capacitive storage elements (e.g., DRAM memory cells), ferroelectric storage elements (e.g., FeRAM memory cells), chalcogenide storage elements (e.g., phase change memory cells, thresholding memory cells), transistor-based storage elements (e.g., NAND memory cells, SRAM memory cells), among other types of storage elements.

Each memory array505may be associated with row circuitry510, each instance of which may include components such as a row decoder, a row driver, a row access strobe, or bank logic, among other circuitry that may be associated with accessing rows of memory cells (e.g., accessing word lines210). Each memory array505also may be associated with column circuitry515, each instance of which may include components such as a column decoder, a column driver, a column access strobe, or a sense component, among other circuitry that may be associated with accessing columns of memory cells (e.g., accessing digit lines215). Operations of the row circuitry510and the column circuitry515may be controlled via a control interface520, which may be supported via signaling over a control bus525that is coupled with the row circuitry510and the column circuitry.

In some examples, the layout500may include one or more buses530that may be operable for coupling with a set of one or more instances of column circuitry515. Each bus530may include a set of signal paths535, and may be an example of a bus310(e.g., a GIO bus) described with reference toFIG.3. In some examples (e.g., to support signaling of read operations on a memory array505), signaling of a bus530may be driven by a component of a corresponding instance of column circuitry515, such as a set of sense amplifiers coupled with the signal paths535and respective memory cells being read.

The layout500also may include a bus540that may be operable for coupling with one or more of the buses530. The bus540may include a set of signal paths545, and may be an example of a bus330(e.g., a DRW bus) or a bus355described with reference toFIG.3. In some examples (e.g., to support signaling of read operations on a memory array505), signaling of a bus540may be driven at least in part by a data sense amplifier550, which may be associated with translations between relatively low-swing signaling of the bus530(e.g., analog signaling) and full-swing signaling of the bus540(e.g., digital signaling). In some examples, a quantity of signal paths545of the bus540may be less than a quantity of signal paths535of the bus530, which may be supported by a serializer/deserializer component555(e.g., between the bus540and a bus530. In various examples, operations of the data sense amplifiers550, the serializer/deserializer components555, or both may be controlled vial the control interface520.

The layout500may include contacts570, which may be configured for communicative coupling with contacts of another semiconductor die (e.g., in a multiple-die stack). In some examples, contacts570-amay support data signaling with or via another semiconductor die, and may support a direct connection with the bus530. In some examples, contacts570-bmay support control signaling with or via another semiconductor die (e.g., including a device memory controller155or another type of processor), which may include control signaling communicated with the control interface520. In some examples, contacts570-cmay support power delivery to the layout500(e.g., from or via a substrate450, in accordance with one or more voltage levels), which may be routed via the control interface520, among other portions of the layout500. In some examples, contacts570may have a relatively small contact area, or may be associated with a relatively small pitch dimension between contacts, or both, which may support a relatively large quantity of contacts between semiconductor dies (e.g., to support relatively high throughput of signaling while avoiding power consumption and heat generation associated with data sense amplifiers550and serializer/deserializer components555, among other circuitry). In some examples, contacts570may include bypass contacts that are configured to convey signaling through a semiconductor die that includes the layout500, which may not be coupled with circuitry of the layout500

The layout500also may include contacts580, which may be configured for evaluation operations associated with the layout500(e.g., before a semiconductor die including the layout500is coupled with another semiconductor die). In some examples, the contacts580may be electrically isolated from the contacts570. In some examples, one or more of the contacts580may be included in a region585(e.g., a common logic and test access block, a test probe region, a reserved area of the semiconductor die). In some examples, contacts580-amay support data signaling with an evaluation probe, and may support a connection with the bus540(e.g., utilizing a more granular DRW bus to facilitate observation points in the layout500). In some examples, contacts580-bmay support control signaling with an evaluation probe. In some examples, contacts580-cmay support power delivery to the layout500(e.g., from or via an evaluation probe, in accordance with one or more voltage levels), which also may be routed via the control interface520, among other portions of the layout500. In some examples, contacts580may have a relatively large contact area, or may be associated with a relatively large pitch dimension between contacts, or both, which may facilitate coupling with an evaluation probe.

In some examples, control signaling via contacts580-bmay include signaling with an evaluation interface590, which may translate or otherwise respond to signaling via the contacts580-b(e.g., from an evaluation probe) by generating control signaling for operations with the control interface520. For example, an evaluation probe coupled with the contacts580-bmay transmit control signaling (e.g., commands to access the memory arrays505) to the evaluation interface590to invoke evaluation protocols (e.g., configuration settings, data patterns, access patterns, registers), which may be associated with instructions stored at the evaluation interface590. Such protocols may be called to initiate various access sequences by the control interface520for accessing the memory arrays505, which may include various techniques for encoding or compressing signaling via the contacts580. In some examples, the evaluation interface590may provide customer-facing access to the layout500, such as an IEEE1500 interface or other proprietary access logic.

In some examples, the bus540may be associated with buffers560(e.g., buffer circuits, which may amplify signals through inverters), which may support extending the bus540across a semiconductor die to support access by different sections of the memory logic. The buffers560may be bidirectional, which may support amplifying signals both left and right of a channel for reading from the memory arrays505or writing to the memory arrays505. Buffers560may be included in various configurations along the bus540(e.g., between portions of the bus540and interconnections with one or more buses530) to support various functionality of the layout500. For example, the buffers560may be activated or deactivated, for various signaling or evaluations, which may include activations or deactivations by the control interface520(e.g., in response to data access commands), or by the evaluation interface590(e.g., in response to evaluation commands), or both, which may include commands to activate one or more of the buffers560.

In some examples, the buffers560may support isolating one or more sections of the bus540for use in a mission mode (e.g., when a semiconductor die including the layout500is assembled in a multiple-die stack, for signaling operational data rather than an evaluation mode), which may reduce a loading of driver circuits involved with accessing data. In some examples, the buffers560may support amplifying data signals so they can be observed at contacts580-a, or through registers accessed through the evaluation interface590. Although the contacts580may not be accessible after assembling a multiple-die stack, in some examples, signals of the bus540may be otherwise made available after assembly through other bonds (e.g., other contacts of the layout500, not shown), which may support other connections with an evaluation interface590(e.g., IEEE1500 interface logic) that may be evaluated by an end user.

In some examples, accessing sections of the bus540may be supported by programming (e.g., configuring, enabling) buffers560to turn on signal paths corresponding to memory arrays505and physical interface of the memory channel to be observed, which may be performed via a bus interconnect associated with the evaluation interface590. For example, test circuit operation may be verified during a manufacturing test for reliability both before or as part of assembly in a multiple-die stack and after such assembly, which may include verifying continuity of the bond connections to the test circuit. In some examples, such evaluations may be relatively minor compared with creating test circuits for verifying bond connections for the many connections involved with memory access. Once the test logic is verified, post packaging, the test circuit may then be used for verifying the bond connections of a multiple-die stack using the more simplified test logic interface. In some examples, after assembling a multiple-die stack, one or more of the bus540, the buffers560, the serializer/deserializer components555, or the data sense amplifiers550may be disabled which may reduce a power consumption or heat loading of the assembled stack.

Thus, in accordance with these and other examples, a semiconductor die may include one or more memory arrays, a set of first contacts (e.g., contacts580) that are configured for signaling associated with operating the one or more memory arrays in accordance with a first mode (e.g., for evaluation operations, before coupling the first semiconductor die with a second semiconductor die), and a set of second contacts (e.g., contacts570) that are configured for signaling associated with operating the one or more memory arrays in accordance with a second mode (e.g., a mission mode, after coupling the first semiconductor die with a second semiconductor die). By implementing such sets of contacts, the layout500may support evaluation operations using the set of first contacts without damaging the set of second contacts, which may improve capabilities of the layout500for supporting a multiple-die stack. In some examples, such configurations may support a higher throughput (e.g., a higher bit rate, a higher burst rate) via the set of first contacts, a reduced power consumption of the semiconductor die, or a reduced heating of the semiconductor die, among other benefits.

FIG.6shows a flowchart illustrating a method600that supports memory with parallel main and test interfaces in accordance with examples as disclosed herein. The operations of method600may be implemented by a manufacturing system or its components as described herein. In some examples, a manufacturing system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the manufacturing system may perform aspects of the described functions using special-purpose hardware.

At605, the method may include providing a first semiconductor die including a set of one or more memory arrays, a set of one or more first contacts, and a set of one or more second contacts. The operations of605may be performed in accordance with examples as disclosed with reference toFIGS.3through5.

At610, the method may include evaluating operations of the first semiconductor die based at least in part on contacting the set of one or more second contacts with an evaluation probe. The operations of610may be performed in accordance with examples as disclosed with reference toFIGS.3through5.

At615, the method may include coupling the first semiconductor die with a second semiconductor die based at least in part on evaluating the operations of the first semiconductor die, where the coupling includes establishing a communicative coupling between each first contact of the set of one or more first contacts with a respective contact of the second semiconductor die. The operations of615may be performed in accordance with examples as disclosed with reference toFIGS.3through5.

In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform a method or methods, such as the method600. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof for performing the following aspects of the present disclosure:

Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing a first semiconductor die including a set of one or more memory arrays, a set of one or more first contacts, and a set of one or more second contacts; evaluating operations of the first semiconductor die based at least in part on contacting the set of one or more second contacts with an evaluation probe; and coupling the first semiconductor die with a second semiconductor die based at least in part on evaluating the operations of the first semiconductor die, where the coupling includes establishing a communicative coupling between each first contact of the set of one or more first contacts with a respective contact of the second semiconductor die.

Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing power to the first semiconductor die via a first subset of the set of one or more second contacts, where the evaluating is based at least in part on the provided power.

Aspect 3: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 2, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing commands to access at least one of the one or more memory arrays of the first semiconductor die via a second subset of the set of one or more second contacts, where the evaluating is based at least in part on the commands to access the at least one of the one or more memory arrays.

Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 3, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing the commands to access the at least one of the one or more memory arrays to evaluation interface circuitry of the first semiconductor die.

Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 4 where at least a subset of the one or more first contacts are coupled with a first data bus of the first semiconductor die and at least a subset of the one or more second contacts are coupled with one or more second data buses of the first semiconductor die.

Aspect 6: The method, apparatus, or non-transitory computer-readable medium of aspect 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing commands to activate one or more buffers between the first data bus and the one or more second data buses, where the evaluating is based at least in part on the commands to activate the one or more buffers.

Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing the first semiconductor die including a second set of one or more one or more first contacts and coupling the first semiconductor die with a third semiconductor die, where the coupling includes establishing a communicative coupling between each first contact of the second set of one or more first contacts with a respective contact of the third semiconductor die.

Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 7, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing the second semiconductor die including a second set of one or more one or more memory arrays.

It should be noted that the methods described herein describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

Aspect 9: An apparatus, including: a set of one or more memory arrays of a first memory die; a set of one or more first contacts of the first memory die that are configured for communicative coupling with a set of one or more contacts of a second memory die; and a set of one or more second contacts of the first memory die that are configured for testing operations of the first memory die, where the set of one or more second contacts of the first memory die is configured for electrical isolation from circuitry of the second memory die.

Aspect 10: The apparatus of aspect 9, where: at least a subset of the one or more first contacts are coupled with a first data bus of the first memory die; and at least a subset of the one or more second contacts are coupled with one or more second data buses of the first memory die.

Aspect 11: The apparatus of aspect 10, further including one or more buffers between the first data bus and the one or more second data buses.

Aspect 12: The apparatus of any of aspects 10 through 11, further including one or more serializer/deserializer components between the first data bus and the one or more second data buses.

Aspect 13: The apparatus of any of aspects 9 through 12, where the set of one or more second contacts of the first memory die are configured to be physically inaccessible after the communicative coupling.

Aspect 14: The apparatus of any of aspects 9 through 13, where the set of one or more second contacts of the first memory die is configured for contact with a dielectric portion of the second memory die.

Aspect 15: The apparatus of any of aspects 9 through 14, where the set of one or more second contacts of the first memory die are configured for contact by an evaluation probe prior to the communicative coupling.

Aspect 16: The apparatus of any of aspects 9 through 15, where a first subset of the one or more second contacts is configured for control signaling associated with operating the first memory die and a second subset of the one or more second contacts is configured for data signaling associated with operating the first memory die.

Aspect 17: The apparatus of any of aspects 9 through 16, where a third subset of the set of one or more second contacts is configured for receiving power for operating the first memory die.

Aspect 18: The apparatus of any of aspects 9 through 17, where the set of one or more first contacts of the first memory die is configured for a soldered connection with the one or more contacts of the second memory die.

Aspect 19: The apparatus of any of aspects 9 through 18, where the set of one or more first contacts of the first memory die is configured for a direct connection with the one or more contacts of the second memory die.

Aspect 20: The apparatus of any of aspects 9 through 19, where the set of one or more first contacts of the first memory die is configured for conveying data signaling, command signaling, or a combination thereof.

Aspect 21: The apparatus of any of aspects 9 through 20, where the set of one or more first contacts of the first memory die is configured for communicating signaling with a controller communicatively coupled with the first memory die and with the second memory die.

Aspect 22: The apparatus of any of aspects 9 through 21, where the set of one or more first contacts of the memory is associated with a first pitch between the first contacts and the set of one or more second contacts are configured with a second pitch between the second contacts that is different than the first pitch.

Aspect 23: The apparatus of any of aspects 9 through 22, where the one or more first contacts of the memory are associated with a first cross-sectional area and the one or more second contacts are associated with a second cross-sectional area that is different than the first cross-sectional area.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

Aspect 24: An apparatus, including: a first semiconductor die of a memory device including a first set of one or more memory arrays, a first set of one or more first contacts, and a first set of one or more second contacts that are configured for evaluating operations of the first semiconductor die; and a second semiconductor die of the memory device including a second set of one or more memory arrays, a second set of one or more first contacts communicatively coupled with the first set of one or more first contacts, and a second set of one or more second contacts that are configured for evaluating operations of the second semiconductor die.

Aspect 25: The apparatus of aspect 24, where: at least a subset of the one or more first contacts of the first semiconductor die are coupled with a first data bus of the first semiconductor die; at least a subset of the one or more first contacts of the second semiconductor die are coupled with a first data bus of the second semiconductor die; at least a subset of the one or more second contacts of the first semiconductor die are coupled with one or more second data buses of the first semiconductor die; and at least a subset of the one or more second contacts of the second semiconductor die are coupled with one or more second data buses of the second semiconductor die.

Aspect 26: The apparatus of any of aspects 24 through 25, where the first set of one or more second contacts, the second set of one or more second contacts, or both are physically inaccessible while the second set of one or more first contacts is communicatively coupled with the first set of one or more first contacts.

Aspect 27: The apparatus of any of aspects 24 through 26, where: the first set of one or more second contacts is in contact with a dielectric portion of the second semiconductor die.

Aspect 28: The apparatus of any of aspects 24 through 27, further including: a substrate including a third set of one or more first contacts, where the first semiconductor die includes a fourth set of one or more first contacts communicatively coupled with the third set of one or more first contacts.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

Aspect 29: An apparatus, including: a set of one or more memory arrays of a first semiconductor die; a set of one or more first contacts of the first semiconductor die that are configured for signaling associated with operating the one or more memory arrays before coupling the first semiconductor die with a second semiconductor die; and a set of one or more second contacts of the first semiconductor die that are configured for signaling associated with operating the one or more memory arrays after coupling the first semiconductor die with the second semiconductor die.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

Aspect 30: An apparatus, including: a set of one or more memory arrays of a first semiconductor die; a set of one or more first contacts of the first semiconductor die that are configured for signaling associated with operating the one or more memory arrays in accordance with a first mode; and a set of one or more second contacts of the first semiconductor die, separate from the set of one or more first contacts, that are configured for signaling associated with operating the one or more memory arrays in accordance with a second mode.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (e.g., in conductive contact with, connected with, coupled with) one another if there is any electrical path (e.g., conductive path) between the components that can, at any time, support the flow of signals (e.g., charge, current voltage) between the components. At any given time, a conductive path between components that are in electronic communication with each other (e.g., in conductive contact with, connected with, coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. A conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

The term “coupling” refers to condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components (e.g., over a conductive path) to a closed-circuit relationship between components in which signals are capable of being communicated between components (e.g., over the conductive path). When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A switching component (e.g., a transistor) discussed herein may represent a field-effect transistor (FET), and may comprise a three-terminal component including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components through conductive materials (e.g., metals, alloys). The source and drain may be conductive, and may comprise a doped (e.g., heavily-doped, degenerate) semiconductor region. The source and drain may be separated by a doped (e.g., lightly-doped) semiconductor region or channel. If the channel is n-type (e.g., majority carriers are electrons), then the FET may be referred to as a n-type FET. If the channel is p-type (e.g., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions (e.g., code) on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a processor, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic device, or any combination thereof designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer, or a processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.