Patent ID: 12213252

The use of the same reference symbols in different drawings indicates similar or identical items.

DETAILED DESCRIPTION OF DRAWINGS

The following description in combination with the Figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings, and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other teachings can certainly be used in this application. The teachings can also be used in other applications, and with several different types of architectures, such as distributed computing architectures, client/server architectures, or middleware server architectures and associated resources.

FIG.1illustrates an exploded view of a processor mounting stack-up100andFIG.2is a side view of the stack-up. Stack-up100is provided on an information handling system for mounting a central processing unit (CPU) to the information handling system. Stack-up100includes a heat sink110, an insulating collar120, a power delivery hat130, a conductive stack gasket140, a CPU150, a printed circuit board (PCB)160, and four (4) heat sink mounting bolts170and nuts172. Heat sink110includes a ground contact surface112, heatsink fins114, and a thermal interface surface116. Conductive stack gasket140(as illustrated inFIG.6) includes a ground compression contact ring142and a power compression contact ring144. CPU150includes a ground pad ring152, a power pad ring154, and a heat spreader156. PCB160includes heat sink mounting bolt/ground pads162(hereinafter “ground pads162,” on an under side of the PCB, as illustrated inFIG.2), and power pads164.

Processor stack-up100will be understood to represent an assembly of the information handling system configured to securely affix CPU150to PCB160. As such, stack-up100may represent any form of CPU attachment mechanism as may be known in the art. For example, stack-up100is illustrated such that CPU150is a ball-grid array (BGA) device that may be soldered to PCB160, e.g., in a surface mount process. In another example, stack-up100may utilize a socketed attachment mechanism, such as where CPU150represents a pin-grid array (PGA) device. Here, PCB160will be understood to include a PGA socket connector to electrically connect, and mechanically retain CPU150to the information handling system. As such, stack-up100may include other elements, such as a PGA socket, a retainment mechanism, or other elements, as needed or desired. The mounting of processors on an information handling system, and in particular, processor mounting stack-ups, are known in the art, and will not be further described herein, except as may be needed to illustrate the current embodiments.

As the speed and functionality of CPUs increase, CPUs are requiring higher supply currents at lower operating voltages. As such, the pin count on CPUs is increasing, not only for signals, but also for power delivery. Moreover, as the speed of the interfaces on CPUs increases, the need for more localized power and ground delivery in order to assure good signal quality is also increasing. Thus a typical CPU may include over 300 power pins to deliver input power (VCCIN) to the CPU, and over 300 ground pins (over 600 pins just for power and ground). This high pin count results in larger CPU packages and much greater complexity in routing power, ground, and signals to the CPU in the PCB. Furthermore, the large number of power and ground connections between the CPU and the PCB results in greater heat generation in the CPU package.

In a particular embodiment, stack-up100operates provide current to CPU150through the elements of the stack-up. In particular, as illustrated inFIGS.3and4and described further below, CPU150is configured to such that a portion of the ground contacts on a die of the CPU are route through a substrate of the CPU to ground pad ring152, and a portion of the input power (VCCIN) contacts on the die are routed through the substrate to power pad ring154. Here, as illustrated by an input power flow200inFIG.2, input power (VCCIN) from one or more power plane of PCB160is routed to power pads164, through power delivery hat130and power compression contact ring144of conductive stack gasket140to power pad ring154to provide input power input power (VCCIN) to CPU150at power pad ring154. Then, as illustrated by a return power flow202inFIG.2, the return current from CPU150flows from ground pad ring152through ground compression contact ring142of conductive stack gasket140, heat sink110, and heat sink mounting bolts170and nuts172to ground pads162. Here, one or more ground plane of PCB160is routed to ground pads162.

In assembly, after CPU150is affixed to PCB160, conductive stack gasket140is placed atop the CPU. Conductive stack gasket140is configured such that heat spreader156fits snugly into a cut-out center portion of the conductive stack gasket, such that a bottom side of ground compression contact ring142makes electrical contact with ground pad ring152, and such that a bottom side of power compression contact ring144makes electrical contact with power pad ring154. Power deliver hat130is placed atop conductive stack gasket140. Power delivery hat130is formed of an electrically conductive material, such as copper, or other suitable materials, as needed or desired. Power delivery hat130is configured such that a bottom side of the power delivery hat makes electrical contact with a top side of power compression contact ring144, but not with a top side of ground compression contact ring142. Power delivery hat130is further configured to extend beyond the bounds of CPU150, and is formed with downward extensions to make electrical contact with power pads164on PCB160. Insulating collar120is placed atop power delivery hat130, heat sink110is placed atop the insulating collar, and heat sink mounting bolts170are installed into the heat sink, through holes in PCB160, and into nut172, and tightened. In tightening heat sink mounting bolts170into nuts172, thermal interface surface116is brought into good thermal contact with heat spreader156, ground contact surface112makes electrical contact with a top side of ground compression contact ring142(as shown inFIG.6) but not with a top side of power compression contact ring144(as shown inFIG.6), and the heat sink mounting bolts make electrical contact with ground pads162. Insulating collar120is formed of an insulating material, and operates to electrically isolate heat sink110from power delivery hat130.

FIGS.3and4illustrate top-, bottom-, and side-views of CPU150. In the top-view, CPU150is illustrated with ground pad ring152, power pad ring154, and heat spreader156. Here, ground pad ring152and power pad ring154represent conductive surfaces on the top side of a substrate of CPU150, and may be formed of any suitable conductive material such as copper or another conductive material, as needed or desired. In the bottom-view, the electrical connections of CPU150are illustrated as separate contacts. Here, where CPU150represents a surface mount device such as a BGA device, the contacts may be understood to represent solder bumps. Where CPU150represents a socketed device such as a PGA device, the contacts may be understood to represent connector pins. In other examples, the contacts may be any other suitable contact and attachment mechanism, as needed or desired. Here, a limited number of contacts are shown for simplicity of illustration, but it will be understood that a typical CPU will include more contacts or less contacts than are illustrated herein, as needed or desired. Moreover, CPU150should not be understood to necessarily be illustrated to scale, and a typical CPU may be understood to be smaller or larger than the illustrated CPU, as needed or desired.

Ground pad ring152and power pad ring154may be understood to carry all of the current associated with CPU150, or may be understood to carry a portion of the current associated with the CPU. For example, a typical CPU may be understood to have a first current demand associated with the processing functions of the CPU, and a second current demand associated with input/output operations of the CPU. The first current demand may have less need to be closely collocated with the processing functions of the CPU, while the second current demand may need to be more closely collocated with the input/output signal contacts of the CPU. Here, the first current demand may be satisfied through ground pad ring152and power pad ring154, while the second current demand may be satisfied through ground and power connectors on the bottom surface of CPU150. In another embodiment, only a portion of the first current demand may be satisfied through ground pad ring152and power pad ring154, while a remainder of the first current demand may be satisfied through ground and power connectors on the bottom surface of CPU150. In a particular embodiment, the current flowing into power pad ring154and the current from ground pad ring152are configured to be substantially equal to each other. That is, the current capacity of ground pad ring152and power pad ring154may be configured to a common current rating. In another embodiment, one or the other of ground pad ring152and power pad ring154may be configured to carry a higher current than the other, as needed or desired. Here, for example, it will be understood that where the current capacity in ground pad ring152is higher than in power pad ring154, then the number of the power connectors on the bottom side of CPU150may be greater than the number ground connectors.

The side-view of CPU150, as illustrated inFIG.4shows a possible fabrication of the CPU. Here, a substrate of CPU150may be fabricated as a multilayer substrate, with signal, ground, and power layers interconnected by signal vias. In this case, through ground pad ring152and power pad ring154will each be understood to be connected to a CPU die by power paths which connect the respective through ground pad ring and power pad ring to ground contacts and power contacts of the CPU die. The circuit paths will be understood to include circuit vias and ground and power traces in the respective ground and power layers, as needed or desired. Similarly, signal ground, signal power, and signal connections will likewise be understood to route the respective circuits through the CPU substrate between the CPU die and the associated connectors on the bottom surface of the substrate. Here, the signal ground, signal power, and signal connections are illustrated as directly passing through the CPU substrate, but this is not necessarily so, and the contacts of the CPU die may be routed through the CPU substrate to various locations on the bottom surface of the CPU substrate as needed or desired. The details of multi-layer substrate fabrication and the forming of circuit traces therein are known in the art and will not be further described herein, except as needed to illustrate the current embodiments. In other embodiments, the interconnections between ground pad ring152and power pad ring154and the respective contacts of the CPU die are formed by other processes as needed or desired. For example, the interconnections between ground pad ring152and power pad ring154and the respective contacts of the CPU die may be formed by a redistribution layer (RDL) process, as needed or desired. The details of RDL fabrication are known in the art and will not be further described herein, except as needed to illustrate the current embodiments.

As illustrated, ground pad ring152and power pad ring154are continuous and concentric conductive surfaces on the top-side of the CPU substrate, but this is not necessarily so. In this regard, ground pad ring152and power pad ring154may each be formed as two or more separate contact surfaces as needed or desired. Further, ground pad ring152and power pad ring154may be formed of discrete contact points on the top-side of the substrate. Here, the discrete contact points may include features configured to elevate the contact point, such as where each discrete contact point includes a solder bump or another elevated feature, as needed or desired. Here, conductive stack gasket140will be understood to have respective ground compression contact ring142and power compression contact ring144that are configured to match the configuration of the associated ground pad ring152and power pad ring154, as needed or desired. Further, other configurations of ground pad ring152and power pad ring154may be utilized as needed or desired. For example, ground pad ring152and power pad ring154may be configured as ground and power bars, with the ground bars located closer to heat spreader156and the power bars located closer to an edge of CPU150. In another example, one or more power bar may be located on a first side of the CPU substrate and one or more ground bar may be located on an opposite side of the CPU substrate, as needed or desired.

FIG.5illustrates top- and bottom-views of PCB160. In the top-view, PCB160is illustrated with power pads154. Here, power pads164represent conductive surfaces on the top side of PCB160, and may be formed of any suitable conductive material such as copper or another conductive material, as needed or desired. In addition, the electrical connections of CPU150are illustrated as contacts on the top surface of PCB160. Here, where CPU150represents a surface mount device such as a BGA device, the CPU contacts may be understood to represent solder pads. Where CPU150represents a socketed device such as a PGA device, the contacts may be understood to represent connector pins in a socket. In other examples, the contacts may be any other suitable contact and attachment mechanism, as needed or desired. As described above, a limited number of contacts are shown for simplicity of illustration. In the bottom-view, PCB160is illustrated with ground pads162. Here, ground pads162represent conductive surfaces on the bottom side of PCB160, and may be formed of any suitable conductive material such as copper or another conductive material, as needed or desired.

Ground pads162and power pads654may be understood to carry all of the current associated with CPU150, or may be understood to carry a portion of the current associated with the CPU. For example, a first current demand of CPU150as described above may be satisfied through ground pads162and power pads164, while the second current demand as described above may be satisfied through ground and power connectors on the top surface of PCB160. In another embodiment, only a portion of the first current demand may be satisfied through ground pads162and power pads164, while a remainder of the first current demand may be satisfied through ground and power connectors on the top surface of PCB160. In a particular embodiment, the current flowing into power pads164and the current from ground pads162are configured to be substantially equal to each other, and the current capacity of the ground pads and the power pads may be configured to a common current rating. In another embodiment, one or the other of ground pads162and power pads164may be configured to carry a higher current than the other, as needed or desired. PCB160is typically fabricated as a multilayer substrate, with signal, ground, and power layers interconnected by signal vias. In this case, ground pads162and power pads164will each be understood to be connected to respective ground and power planes of PCB160with power and ground vias.

Power pads164are continuous conductive surfaces on the top side of PCB160, and form a landing for the downward extensions of power delivery hat130. Here, the tightening of heat sink mounting bolts170into nuts172operates to compress heat sink110, insulating collar120, and power delivery hat130such that the extensions of the power delivery hat form a reliable power connection to power pads164. Here, a bottom edge of the extensions of power delivery hat130may have a straight profile. However, surface imperfections in power pads164may result in imperfect power connections between power delivery hat130and power pads164. As such, in a particular embodiment, the bottom edge of the extensions of power delivery hat130may have a jagged profile such that, under compression, the tips of the jagged profile are firmly connected to the power pads to form a more reliable power connection.

Ground pads162are continuous conductive surfaces on the bottom side of PCB160, and form a landing for heat sink mounting bolts170and nuts172. In a first case, the force of tightening heat sink mounting bolt170into nut172serves to form a reliable ground connection between heat sink110and ground pads162. In another case, nut172is soldered to ground pad162to ensure a reliable ground connection at the ground pad. In another embodiment, heat sink mounting bolt170is inserted up from the bottom of PCB160and heat sink110includes threaded holes into which the heat sink mounting bolt is tightened. While heat sink mounting bolts170are shown and described as a threaded bolt mechanism, this is not necessarily so and other conductive attachment mechanisms may be utilized as needed or desired. For example, a conductive rivet attachment mechanism or another conductive attachment mechanism may be utilized to firmly adhere heat sink110to CPU150for thermal, mechanical, and electrical mounting as described above, as needed or desired. Further, while four (4) heat sink mounting bolts are shown and described, a greater or a lesser number of heat sink mounting bolts may be utilized as needed or desired.

FIG.6illustrates a top- and side-view of conductive stack gasket140. In the top-view, conductive stack gasket140is illustrated with ground compression contact ring142and power compression contact ring144. Here, it will be understood that a bottom-view of conductive stack gasket140may be functionally visually similar to the top-view. Ground compression contact ring142and power compression contact ring144represent compressible conductive contact elements146that form electrical connections through conductive stack gasket. In particular, when contact elements146form ground compression contact ring142, the conductive contacts of ground compression contact ring142connect ground pad ring152of CPU150to ground contact surface112of heatsink110, and when contact elements146form power compression contact ring144, the conductive contacts of power compression contact ring144connect power pad ring154of CPU150to power delivery hat140. As illustrated, contact elements146represent compressible contact elements which, when stack-up100is tightened, form reliable electrical connections. Contact elements146may be formed of other conductive materials, such as solder bumps or other raised contact surfaces, as needed or desired. In another embodiment, only a portion of the first current demand may be satisfied through ground compression contact ring142and power compression contact ring144, as needed or desired. In another embodiment, one or the other of ground compression contact ring142and power compression contact ring144may be configured to carry a higher current than the other, as needed or desired.

As illustrated, ground compression contact ring142and power compression contact ring144are continuous and concentric conductive surfaces on the top- and bottom-sides of the conductive stack gasket140. However, this is not necessarily so, and ground compression contact ring142and power compression contact ring144may each be formed to conform with the configuration of respective ground pad ring152and power pad ring154, as needed or desired. While the teachings of the current disclosure are provided in the context of CPU power delivery, this is not necessarily so, and the teachings of the current disclosure may be utilized in conjunction with other types of components that utilize a heat sink to dissipate heat from the component, and where the processor stack-up may reasonably be utilized for carrying power and ground current paths, as needed or desired.

FIG.7illustrates a generalized embodiment of an information handling system300. For purpose of this disclosure an information handling system can include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, information handling system300can be a personal computer, a laptop computer, a smart phone, a tablet device or other consumer electronic device, a network server, a network storage device, a switch router or other network communication device, or any other suitable device and may vary in size, shape, performance, functionality, and price. Further, information handling system300can include processing resources for executing machine-executable code, such as a central processing unit (CPU), a programmable logic array (PLA), an embedded device such as a System-on-a-Chip (SoC), or other control logic hardware. Information handling system300can also include one or more computer-readable medium for storing machine-executable code, such as software or data. Additional components of information handling system300can include one or more storage devices that can store machine-executable code, one or more communications ports for communicating with external devices, and various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. Information handling system300can also include one or more buses operable to transmit information between the various hardware components.

Information handling system300can include devices or modules that embody one or more of the devices or modules described below, and operates to perform one or more of the methods described below. Information handling system300includes a processors302and304, an input/output (I/O) interface310, memories320and325, a graphics interface330, a basic input and output system/universal extensible firmware interface (BIOS/UEFI) module340, a disk controller350, a hard disk drive (HDD)354, an optical disk drive (ODD)356, a disk emulator360connected to an external solid state drive (SSD)364, an I/O bridge370, one or more add-on resources374, a trusted platform module (TPM)376, a network interface380, a management device390, and a power supply395. Processors302and304, I/O interface310, memories320and325, graphics interface330, BIOS/UEFI module340, disk controller350, HDD354, ODD356, disk emulator360, SSD364, I/O bridge370, add-on resources374, TPM376, and network interface380operate together to provide a host environment of information handling system300that operates to provide the data processing functionality of the information handling system. The host environment operates to execute machine-executable code, including platform BIOS/UEFI code, device firmware, operating system code, applications, programs, and the like, to perform the data processing tasks associated with information handling system300.

In the host environment, processor302is connected to I/O interface310via processor interface306, and processor304is connected to the I/O interface via processor interface308. Memory320is connected to processor302via a memory interface322. Memory325is connected to processor304via a memory interface327. Graphics interface330is connected to I/O interface310via a graphics interface332, and provides a video display output335to a video display334. In a particular embodiment, information handling system300includes separate memories that are dedicated to each of processors302and304via separate memory interfaces. An example of memories320and325include random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.

BIOS/UEFI module340, disk controller350, and I/O bridge370are connected to I/O interface310via an I/O channel312. An example of I/O channel312includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. I/O interface310can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/UEFI module340includes BIOS/UEFI code operable to detect resources within information handling system300, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/UEFI module340includes code that operates to detect resources within information handling system300, to provide drivers for the resources, to initialize the resources, and to access the resources.

Disk controller350includes a disk interface352that connects the disk controller to HDD354, to ODD356, and to disk emulator360. An example of disk interface352includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator360permits SSD364to be connected to information handling system300via an external interface362. An example of external interface362includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive364can be disposed within information handling system300.

I/O bridge370includes a peripheral interface372that connects the I/O bridge to add-on resource374, to TPM376, and to network interface380. Peripheral interface372can be the same type of interface as I/O channel312, or can be a different type of interface. As such, I/O bridge370extends the capacity of I/O channel312when peripheral interface372and the I/O channel are of the same type, and the I/O bridge translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel372when they are of a different type. Add-on resource374can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource374can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system300, a device that is external to the information handling system, or a combination thereof.

Network interface380represents a NIC disposed within information handling system300, on a main circuit board of the information handling system, integrated onto another component such as I/O interface310, in another suitable location, or a combination thereof. Network interface device380includes network channels382and384that provide interfaces to devices that are external to information handling system300. In a particular embodiment, network channels382and384are of a different type than peripheral channel372and network interface380translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels382and384includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels382and384can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.

Management device390represents one or more processing devices, such as a dedicated baseboard management controller (BMC) System-on-a-Chip (SoC) device, one or more associated memory devices, one or more network interface devices, a complex programmable logic device (CPLD), and the like, that operate together to provide the management environment for information handling system300. In particular, management device390is connected to various components of the host environment via various internal communication interfaces, such as a Low Pin Count (LPC) interface, an Inter-Integrated-Circuit (I2C) interface, a PCIe interface, or the like, to provide an out-of-band (OOB) mechanism to retrieve information related to the operation of the host environment, to provide BIOS/UEFI or system firmware updates, to manage non-processing components of information handling system300, such as system cooling fans and power supplies. Management device390can include a network connection to an external management system, and the management device can communicate with the management system to report status information for information handling system300, to receive BIOS/UEFI or system firmware updates, or to perform other task for managing and controlling the operation of information handling system300. Management device390can operate off of a separate power plane from the components of the host environment so that the management device receives power to manage information handling system300when the information handling system is otherwise shut down. An example of management device390include a commercially available BMC product or other device that operates in accordance with an Intelligent Platform Management Initiative (IPMI) specification, a Web Services Management (WSMan) interface, a Redfish Application Programming Interface (API), another Distributed Management Task Force (DMTF), or other management standard, and can include an Integrated Dell Remote Access Controller (iDRAC), an Embedded Controller (EC), or the like.

Management device390may further include associated memory devices, logic devices, security devices, or the like, as needed or desired.

Although only a few exemplary embodiments have been described in detail herein, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the embodiments of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the embodiments of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover any and all such modifications, enhancements, and other embodiments that fall within the scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.