Patent ID: 12211793

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In emerging technology nodes, the small size of transistor components may cause restrictive topology choices for routing back-end-of-the-line (BEOL) metal interconnect layers. To alleviate metal interconnect routing problems, middle-end-of-the-line (MEOL) local interconnect layers may be used. MEOL local interconnect layers are conductive (e.g., metal) layers that are vertically positioned between the front-end-of-line (FEOL) and the BEOL. MEOL local interconnect layers can provide very high-density local routing that avoids consumption of scarce routing resources on the lower BEOL metal interconnect layers.

Typically, MEOL local interconnect layers comprise MEOL structures that are formed directly onto an active area (e.g., a source/drain region). Conductive contacts are subsequently formed onto some of the MEOL structures to form an electrical connection with an overlying BEOL metal interconnect layers. It has been appreciated that in emerging technology nodes (e.g., 14 nm, 10 nm, 7 nm, etc.) the small size of MEOL structures and/or the conductive contacts is becoming small enough to be a significant source of parasitic resistance. The parasitic resistance can cause a drop in voltage and/or current (e.g., between a source voltage VDDor ground voltage VSSand a transistor source/drain region) that degrades transistor device performance.

In some embodiments, the present disclosure relates to an integrated circuit having parallel conductive paths between a BEOL interconnect layer and a MEOL structure, which are configured to reduce a parasitic resistance and/or capacitance of the integrated circuit. The integrated circuit comprises source/drain regions arranged within a semiconductor substrate and separated by a channel region. A first gate structure is arranged over the channel region, and a middle-end-of-the-line (MEOL) structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, so as to form parallel conductive paths extending between the BEOL interconnect layer and the MEOL structure. The parallel conductive paths have an increased cross-sectional area (compared to a single conductive path) for current to pass from the BEOL interconnect layer to the MEOL structure (i.e., a semiconductor device), thereby reducing a parasitic resistance of the device.

FIG.1illustrates a top-view of some embodiments of an integrated circuit100having a power horn structure configured to reduce parasitic resistance.

The integrated circuit100comprises a plurality of gate structures106a-106barranged over an active area104within a semiconductor substrate102. In some embodiments, the plurality of gate structures comprise an electrically active gate structure106aand a dummy gate structure106b(i.e., an electrically inactive gate structure). The electrically active gate structure106ais coupled to an overlying first BEOL metal interconnect wire114acomprising a control node CTRL (e.g., a control voltage) by way of a first conductive contact112a. The electrically active gate structure106ais configured to control a flow of charge carriers within a transistor device116comprising the active area104. In some embodiments, the plurality of gate structures106a-106bextend along the first direction120, and the active area104extends along a second direction122that is perpendicular to the first direction120. In some embodiments, the active area104includes at least one fin, together with the plurality of gate structures106a-106b, to form FinFET transistors.

A plurality of middle-end-of-the-line (MEOL) structures108a-108care interleaved between the plurality of gate structures106a-106b. The plurality of MEOL structures comprise a first MEOL structure108aand a second MEOL structure108bconfigured to provide electrical connections to the active area104. In some embodiments, the first MEOL structure108ais coupled to an overlying second BEOL metal interconnect wire114bcomprising a first input/output node I/O1by way of a second conductive contact112b. The second MEOL structure108bis coupled to an overlying third BEOL metal interconnect wire114ccomprising a second input/output node I/O2by way of a third conductive contact112c. The third conductive contact112cforms a first conductive path118a(i.e., electrical connection) between the third BEOL metal interconnect wire114cand the second MEOL structure108b.

A conductive structure110is arranged over the second MEOL structure108b. A fourth conductive contact112dforms a second conductive path118bbetween the third BEOL metal interconnect wire114cand the second MEOL structure108bby way of the conductive structure110. In some embodiments, the plurality of MEOL structures comprise a third MEOL structure108cseparated from the second MEOL structure108bby the dummy gate structure106b. In some such embodiments, the third and fourth conductive contacts,112cand112d, are connected directly from the third BEOL metal interconnect wire114cto the second MEOL structure108band the third MEOL structure108c, respectively. In other such embodiments, the third and fourth conductive contacts,112cand112d, are connected directly to the conductive structure110. In some embodiments, the conductive structure110extends over the dummy gate structure106b.

Therefore, the conductive structure110provides for first and second conductive paths,118aand118b, which extend in parallel between the third BEOL metal interconnect wire114cand the second MEOL structure108b. The parallel conductive paths,118aand118b, provide for an increased cross-sectional area (compared to a single conductive path) for current to pass from the third BEOL metal interconnect wire114cto the transistor device116, thereby reducing a parasitic resistance of the transistor device116.

FIG.2Aillustrates a cross-sectional view (shown along cross-sectional line A-A′ ofFIG.1)) of some embodiments of an integrated circuit200having a power horn structure configured to reduce parasitic resistance.

The integrated circuit200comprises an active area104having a plurality of source/drain regions204a-204carranged within a semiconductor substrate102. In some embodiments, the active area104may be included within a well region202having a doping type opposite the semiconductor substrate102and the source/drain regions204a-204c(e.g., a PMOS active area formed within a p-type substrate may comprise p-type source/drain regions arranged within an n-well). The plurality of source/drain regions204a-204ccomprise highly doped regions (e.g., having a doping concentration greater than that of the surrounding semiconductor substrate102). In some embodiments, the plurality of source/drain regions204a-204care epitaxial source/drain regions. In some embodiments, the active area104includes at least one fin, protruding outward from the semiconductor substrate102, to form FinFET transistors.

A plurality of gate structures106a-106bare arranged over the semiconductor substrate102at locations laterally between the plurality of source/drain regions204a-204c. The plurality of gate structures106a-106bcomprise an active gate structure106aand a dummy gate structure106b. The active gate structure106ais configured to control the flow of charge carriers within a channel region206arranged between the first source/drain region204aand a second source/drain region204bduring operation of a transistor device116, while the dummy gate structure106bis not. In some embodiments, the plurality of gate structures106a-106bmay comprise a gate dielectric layer208and an overlying gate electrode layer210. In various embodiments, the gate dielectric layer208may comprise an oxide or a high-k dielectric layer. In various embodiments, the gate electrode layer210may comprise polysilicon or a metal (e.g., aluminum).

A plurality of MEOL structures108a-108care laterally interleaved between the plurality of gate structures106a-106b. The plurality of MEOL structures108a-108care arranged over the source/drain regions204a-204cand, in some embodiments, have heights that are substantially equal to heights of the plurality of gate structures106a-106b(i.e., upper surfaces of the plurality of MEOL structures108a-108care substantially co-planar with upper surfaces of the gate electrode layer210). In some embodiments, the heights of the MEOL structures108a-108care larger than heights of the plurality of gate structures106a-106b. The plurality of MEOL structures108a-108cmay comprise a conductive material such as aluminum, copper, and/or tungsten, for example. In some embodiments, the plurality of MEOL structures108a-108cand the plurality of gate structures106a-106bare arranged at a substantially regular pitch (i.e., a spacing is substantially the same between left edges of the gate structures or between right edges of the gate structure). For example, the regular pitch may have values that vary due to misalignment errors by approximately 5% (e.g., a first pitch may be between 0.95 and 1.05 times a second pitch).

A conductive structure110is arranged over a second MEOL structure108bof the plurality of MEOL structures108a-108b. The conductive structure110has a lower surface that contacts an upper surface of the second MEOL structure108b. In some embodiments, the lower surface of the conductive structure110also contacts an upper surface of a dummy gate structure106band/or a third MEOL structure108c. The conductive structure110is arranged within an inter-level dielectric (ILD) layer212. In some embodiments, the ILD layer212may comprise more than one dielectric layer.

A third conductive contact112cand a fourth conductive contact112dare arranged within a first inter-metal dielectric (IMD) layer214overlying the ILD layer212. The third conductive contact112cand a fourth conductive contact112dare configured to couple the second MEOL structure108bto a third BEOL metal interconnect wire114carranged within a second IMD layer216overlying the first IMD layer214. In some embodiments, the third BEOL metal interconnect wire114cmay comprise copper or a copper alloy. In some embodiments, the third and fourth conductive contacts,112cand112d, are arranged along an upper surface of the second and third MEOL structures,108band108c, respectively. In other embodiments, the third and fourth conductive contacts,112cand112d, are arranged along an upper surface of the conductive structure110. The third conductive contact112cis configured to provide current from the third BEOL metal interconnect wire114cto the second MEOL structure108balong a first conductive path118aand the second conductive contact112bis configured to provide current from the third BEOL metal interconnect wire114cto the second MEOL structure108balong a second conductive path118bthat is parallel to the first conductive path118a.

AlthoughFIG.2Aillustrates a cross-sectional view of an integrated circuit200comprising MEOL structures108a-108bhaving different materials (shading) than the conductive structure110, it will be appreciated that this is a non-limiting embodiment. For example,FIG.2Billustrates some alternative embodiments of an integrated circuit218having two different MEOL layers. A first MEOL layer220extends vertically between the semiconductor substrate102and conductive contacts220b-220d, and includes the MEOL structures108a-108cand the conductive structure110. A second MEOL layer222extends vertically between a top of the active gate structure106aand conductive contact220a. In such embodiments, the conductive contacts220a-220dhave a height h that is less than a height of conductive contacts112a-112d, illustrated inFIG.2A.

FIG.3illustrates some additional embodiments of an integrated circuit300having a power horn structure configured to reduce parasitic resistance.

The integrated circuit300comprises a plurality of MEOL structures108a-108cextending over an active area104in a first direction120and interleaved between a plurality of gate structures106a-106balong a second direction122. In some embodiments, the active area104may include at least one fin, protruding outward from a semiconductor substrate102, to form FinFET transistors. The plurality of MEOL structures comprise a first MEOL structure108a, a second MEOL structure108b, and a third MEOL structure108c. In some embodiments, the plurality of MEOL structures108a-108cmay straddle opposing edges of the active area104along the first direction120. A conductive structure302is arranged over the second and third MEOL structures,108band108c, at a location that is offset from the active area104in the first direction120. The conductive structure302is coupled to a third BEOL metal interconnect wire114cby way of a third conductive contact112c, thereby providing a first conductive path304abetween the third BEOL metal interconnect wire114cand the second MEOL structure108b. The conductive structure302is also coupled to the third BEOL metal interconnect wire114cby way of a fourth conductive contact112d, thereby providing for a second conductive path304bbetween the third BEOL metal interconnect wire114cand the second MEOL structure108b.

FIG.4illustrates some additional embodiments of an integrated circuit400having a power horn structure configured to reduce parasitic resistance.

The integrated circuit400comprises a plurality of MEOL structures108a-108cinterleaved between a plurality of gate structures106a-106balong a second direction122. The plurality of MEOL structures comprise a first MEOL structure108aand a second MEOL structure108barranged over an active area402, and a third MEOL structure108carranged at a location offset from the active area402along the second direction122. In some embodiments, the active area402may include at least one fin, protruding outward from a semiconductor substrate102, to form FinFET transistors. A conductive structure404straddles an end of the active area402and extends between the second MEOL structure108band the third MEOL structure108c. In some embodiments, the conductive structure404extends over a dummy gate structure106b. The second MEOL structure108bis coupled to a third BEOL metal interconnect wire114cby way of a third conductive contact112c, thereby providing a first conductive path406abetween the third BEOL metal interconnect wire114cand the second MEOL structure108b. The third MEOL structure108cis coupled to the third BEOL metal interconnect wire114cby way of a fourth conductive contact112d, thereby providing a second conductive path406bbetween the third BEOL metal interconnect wire114cand the second MEOL structure108bthat extends through the conductive structure404.

FIG.5illustrates some additional embodiments of an integrated circuit500having a power horn structure configured to reduce parasitic resistance.

The integrated circuit500comprises a plurality of MEOL structures108a-108bextending over an active area502in a first direction120and interleaved between a plurality of gate structures106a-106balong a second direction122. In some embodiments, the active area502may include at least one fin, protruding outward from a semiconductor substrate102, to form FinFET transistors. The plurality of MEOL structures108a-108bcomprise a first MEOL structure108aand a second MEOL structure108b. A conductive structure504is arranged over the second MEOL structure108bat a location that is offset from the active area502in the first direction120. The active area502extends past the conductive structure504in the second direction122. The conductive structure504is coupled to a third BEOL metal interconnect wire114cby way of a third conductive contact112c, thereby providing a first conductive path506abetween the third BEOL metal interconnect wire114cand the second MEOL structure108b. The conductive structure504is also coupled to the third BEOL metal interconnect wire114cby way of a fourth conductive contact112d, thereby providing for a second conductive path506bbetween the third BEOL metal interconnect wire114cand the second MEOL structure108b.

FIG.6illustrates some additional embodiments of an integrated circuit600having a power horn structure configured to reduce parasitic resistance.

The integrated circuit600comprises a plurality of MEOL structures108a-108binterleaved between a plurality of gate structures106a-106balong a second direction122. The plurality of MEOL structures comprise a first MEOL structure108aand a second MEOL structure108barranged over an active area602. In some embodiments, the active area602may include at least one fin, protruding outward from a semiconductor substrate102, to form FinFET transistors. A conductive structure604is arranged over the second MEOL structure108bat a location that is offset from the active area602in a first direction120. The conductive structure604extends past the active area602in the second direction122. The conductive structure604is coupled to a third BEOL metal interconnect wire114cby way of a third conductive contact112c, thereby providing a first conductive path606abetween the third BEOL metal interconnect wire114cand the second MEOL structure108b. The conductive structure604is also coupled to the third BEOL metal interconnect wire114cby way of a fourth conductive contact112d, thereby providing for a second conductive path606bbetween the third BEOL metal interconnect wire114cand the second MEOL structure108b.

FIG.7Aillustrates a top-view of some additional embodiments of an integrated circuit700having a power horn structure configured to reduce parasitic resistance.FIG.7Billustrates a cross-sectional view708shown along cross-sectional line A-A′ of the integrated circuit700ofFIG.7A.

As shown inFIG.7A, the integrated circuit700comprises a plurality of MEOL structures108a-108dinterleaved between a plurality of gate structures106a-106calong a second direction122. The plurality of MEOL structures comprise a first MEOL structure108aand a second MEOL structure108barranged over a first active area702a, a third MEOL structure108carranged at a location offset from the first active area702aalong the second direction122, and a fourth MEOL structure108darranged over a second active area702b. In some embodiments, the first active area702ais included within a first well region710aand the second active area702bis included in a second well region710b. In some embodiments, the first active area702aand/or the second active area702bmay include at least one fin, protruding outward from a semiconductor substrate102, to form FinFET transistors. A conductive structure704extends from over the first active area702ato over the second active area702b. The conductive structure704is arranged over the second MEOL structure108b, the third MEOL structure108c, and the fourth MEOL structure108d.

In some embodiments, the conductive structure704extends over multiple dummy gate structures,106band106c. In some embodiments, the second MEOL structure108bis coupled to a third BEOL metal interconnect wire114cby way of a third conductive contact112cto provide a first conductive path706abetween the third BEOL metal interconnect wire114cand the second MEOL structure108b, the third MEOL structure108cis coupled to the third BEOL metal interconnect wire114cby way of a fourth conductive contact112dto provide a second conductive path706bbetween the third BEOL metal interconnect wire114cand the second MEOL structure108bthat extends through the conductive structure704, and the fourth MEOL structure108dis coupled to the third BEOL metal interconnect wire114cby way of a fifth conductive contact112eto provide a third conductive path706cbetween the third BEOL metal interconnect wire114cand the second MEOL structure108bthat extends through the conductive structure704. In other embodiments, the third conductive contact112c, the fourth conductive contact112d, and the fifth conductive contact112emay be connected directly to the conductive structure704.

FIGS.8A-8Cillustrates some embodiments of a NOR gate having a power horn structure configured to reduce parasitic resistance.

As shown in top-view800, the NOR gate comprises a first active area802aand a second active area802b. As shown in cross-sectional view814ofFIG.8C(along line A-A′ ofFIG.8A), the first active area802acomprises a plurality of source/drain regions816a-816dhaving n-type doping. In some embodiments, the plurality of source/drain regions816a-816dmay be arranged within a well region818having p-type doping. The second active area802bcomprises a plurality of source/drain regions having p-type doping. In some embodiments, the first active area802aand/or the second active area802bmay include at least one fin, protruding outward from a semiconductor substrate102, to form FinFET transistors.

A first gate structure804aand a second gate structure804bextend over the first active area802ato form a first PMOS transistor T1and a second PMOS transistor T2arranged in series between a first power rail808a(illustrated as transparent to show the underlying layers) held at a source voltage VDDand an output pin ZN (as shown in schematic diagram812ofFIG.8B). The first gate structure804aand the second gate structure804bare coupled to input pins A1and A2configured to provide control signals to the first gate structure804aand the second gate structure804b, respectively. In some embodiments, the first power rail808a, the output pin ZN, and the input pins A1and A2are arranged on a same BEOL metal wire layer (e.g., an ‘M1’ layer).

A first plurality of MEOL structures806a-806bare arranged over the first active area802a. The first plurality of MEOL structures comprise a first MEOL structure806acoupled to the output pin ZN by a conductive contact810(to simplify the illustration, a single conductive contact810is labeled with a reference numeral inFIG.8A). The first plurality of MEOL structures further comprise a second MEOL structure806band a third MEOL structure806c, which extend from over the first active area802ato under the first power rail808a. The second MEOL structure806band the third MEOL structure806care coupled by a first conductive structure812athat provides for parallel current paths between the first power rail808aand the second MEOL structure806b.

The first gate structure804aand the second gate structure804balso extend over the second active area802bto form a first NMOS transistor T3and a second NMOS transistor T4arranged in parallel between the output pin ZN and a second power rail808bheld at ground voltage VSS. A second plurality of MEOL structures806d-806gare arranged over the second active area802b. The second plurality of MEOL structures comprise a fourth MEOL structure806dcoupled to the output pin ZN by a conductive contact810. The second plurality of MEOL structures further comprise a fifth MEOL structure806e, a sixth MEOL structure806f, and a seventh MEOL structure806g, which extend from over the second active area802bto under the second power rail808b. The sixth MEOL structure806fand the seventh MEOL structure806gare coupled by a second conductive structure812bthat provides for parallel current paths between the second power rail808band the sixth MEOL structure806f.

FIG.9illustrates a top-view of some embodiments of an integrated circuit900having a power horn structure and output pins configured to reduce parasitic capacitance.

The integrated circuit900comprises a plurality of input pins A1-A4. The plurality of input pins A1-A4comprise wires on a metal interconnect layer902. The input pins A1-A4are configured to provide an input signal (e.g., an input voltage) to a gate structure904device that extends over an active area906of a transistor. The input signal controls operation of the gate structure904(i.e., controls a flow of charge carriers in the transistor devices). In some embodiments, the plurality of input pins A1-A4may be arranged on a first metal interconnect layer (i.e., a lowest metal interconnect layer above MEOL structures908). The integrated circuit900also comprises one or more output pins ZN comprising wires on the metal interconnect layer902. The one or more output pins ZN are configured to provide an output signal (e.g., an output voltage) from a transistor device. In some embodiments, the one or more output pins ZN may be arranged on the first metal interconnect layer.

The one or more output pins ZN have relatively short length LOPwhich reduces an overlap910between the input pins A1-A4and the one or more output pins ZN. Decreasing the overlap910between the one or more output pins ZN and the input pins A1-A4decreases a parasitic capacitance of the integrated circuit900. This is because the parasitic capacitance between adjacent metal interconnect wires is proportional to an overlap of the wires and a distance between the wires (i.e., C=A·D; where C is capacitance, A is an area of overlap between wires, and D is a distance between the wires).

In some embodiments the one or more output pins ZN may have a length LOPthat is less than approximately 1.5 times the contact gate pitch Cop (i.e., a distance between same edges of adjacent gate structures904). In some embodiments, a length LOPof the one or more output pins ZN is less than or equal to a length LIPof the input pins A1-A4, thereby ensuring an overlap between the input pins A1-A4and the one or more output pins ZN is on a single end of the output pins ZN. In some additional embodiments, the one or more output pins ZN may have a length LOPthat is set by a minimum metal cut distance (i.e., a distance between cuts on a cut mask) in a self-align double patterning process.

In some embodiments, the one or more output pins ZN may be located along a wiring track that is between an input pin A1-A4and a power rail912(e.g., held at a source voltage VDDor a ground voltage VSS). In such embodiments, the one or more output pins ZN may overlap an input pin A1-A4along one side but not both, thereby reducing a parasitic capacitance between the one or more output pins ZN and the output pins A1-A4.

FIGS.10-17illustrate some embodiments of a method of forming an integrated circuit having a power horn structure.

As shown in cross-section view1000, a semiconductor substrate102is provided. The semiconductor substrate102may be any type of semiconductor body (e.g., silicon, SiGe, SOI) such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of metal layer, device, semiconductor and/or epitaxial layers, etc., associated therewith. The semiconductor substrate102may comprise an intrinsically doped semiconductor substrate having a first doping type (e.g., an n-type doping or a p-type doping).

In some embodiments, a well region202may be formed within the semiconductor substrate102. The well region202may be formed by implanting the semiconductor substrate102with a dopant species1002having a second doping type that is opposite the first doping type of the semiconductor substrate102(e.g., a p-type substrate may be implanted with an n-type dopant, or vice versa). In some embodiments, the well region202may be formed be implanting the dopant species1002into the semiconductor substrate102according to a first masking layer1004(e.g., a photoresist layer).

As shown in cross-sectional view1100, a plurality of gate structures106a-106bare formed over the semiconductor substrate102. The plurality of gate structures my comprise an electrically active gate structure106aarranged between a first source/drain region204aand a second source/drain region204b, and a dummy gate structure106barranged between the second source/drain region204band a third source/drain region204c. The plurality of gate structures106a-106bmay be formed by forming a gate dielectric layer208onto the semiconductor substrate102and forming a gate electrode layer210over the gate dielectric layer208. The gate dielectric layer208and the gate electrode layer210are subsequently patterned according to a photolithography process to form the plurality of gate structures,106a-106b.

Source/drain regions,204a-204c, may be formed within the semiconductor substrate102on opposing sides of the plurality of gate structures106a-106b. In some embodiments, the source/drain regions,204a-204cmay be formed by an implantation process that selectively implants the semiconductor substrate102with a dopant species1102having the first doping type. The implantation process may use the plurality of gate structures106a-106band a second masking layer1104to define the source/drain regions,204a-204c. In some embodiments, the second masking layer1104may be the same as the first masking layer1004. The dopant species1102may be subsequently driven into the semiconductor substrate102by a high temperature thermal anneal. In other embodiments, the source/drain regions,204a-204c, may be formed by etching the semiconductor substrate102and then performing an epitaxial process.

As shown in cross-sectional view1200, a first ILD layer1202is formed over the semiconductor substrate102. In various embodiments, the first ILD layer1202may comprise an oxide, an ultra-low k dielectric material, or a low-k dielectric material (e.g., SiCO). The first ILD layer1202may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, PVD, etc.).

The first ILD layer1202is subsequently patterned to form one or more openings1204. In some embodiment, the first ILD layer1202may be patterned by forming a third masking layer1206over the first ILD layer1202, and subsequently exposing the first ILD layer1202to an etchant1208in areas not covered by the third masking layer1206. In some embodiments, the third masking layer1206may comprise a photoresist layer having a pattern defined by a photolithography process. In various embodiments, the etchant1208may comprise a dry etchant (e.g., a plasma etch with tetrafluoromethane (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), etc.) or a wet etchant (e.g., hydrofluoric (HF) acid).

As shown in cross-sectional view1300, a plurality of MEOL structures108a-108care formed within the openings1204in the first ILD layer1202. The plurality of MEOL structures may comprise a first MEOL structure108aarranged over a first source/drain region204a, a second MEOL structure108barranged over a second source/drain region204b, and a third MEOL structure108carranged over a third source/drain region204c. The plurality of MEOL structures108a-108cmay comprise a conductive material such as aluminum, copper, and/or tungsten, for example. The plurality of MEOL structures108a-108cmay be formed by a deposition process and/or a plating process. In some embodiments, a deposition process may be used to form a seed layer within the one or more openings1204, followed by a subsequent plating process (e.g., an electroplating process, an electro-less plating process) that forms a metal material to a thickness that fills the one or more openings1204. In some embodiments, a chemical mechanical polishing (CMP) process may be used to remove excess of the metal material from a top surface of the first ILD layer1202.

As shown in cross-sectional view1400, a conductive structure110is formed within a second ILD layer1402arranged over the first ILD layer1202. The conductive structure110is arranged over the second MEOL structure108band the third MEOL structure108c. The conductive structure110has a lower surface that contacts an upper surface of the second MEOL structure108b. In some embodiments, the lower surface of the conductive structure110also contacts an upper surface of a dummy gate structure106band/or the third MEOL structure108c. In some embodiments, the conductive structure110is formed by etching the second ILD layer1402to form an opening and subsequently forming a conductive material within the opening.

As shown in cross-sectional view1500, a plurality of conductive contacts112a-112dare formed in a first IMD layer214. The plurality of conductive contacts112a-112dmay be formed by etching the first IMD layer214to form a plurality of openings. A conductive material (e.g., tungsten) is then formed within the plurality of openings.

As shown in cross-sectional view1600and top-view1604, a BEOL metal interconnect layer is formed over the plurality of conductive contacts112a-112d. The BEOL metal interconnect layer comprises an input pin1602acoupled to the active gate structure106aby a second conductive contact112b, an output pin1602bcoupled to the first MEOL structure108aby a first conductive contact112a, and a power rails1602celectrically coupled to the second MEOL structure108bby a third conductive contact112cand a fourth conductive contact112d. In some embodiments, the third and fourth conductive contacts,112cand112d, are arranged along an upper surface of the second and third MEOL structures,108band108c, respectively. In other embodiments, the third and fourth conductive contacts,112cand112d, are arranged along an upper surface of the conductive structure110.

As shown in top-view1700, the input pin1602aand/or the output pins,1602band1602d, are selectively cut to reduce a length of the input pin1602aand/or the output pins,1602band1602d. For example, as shown in top-view1700, a length of output pin1602dis reduced from LOP′ to LOP. In some embodiments, a cut mask may be used to reduce a length of the input pin1602aand the output pins,1602band1602d. The cut mask has a plurality of cut regions1704, which ‘cut’ the input pin1602aand the output pins,1602band1602d, by removing metal material from selective areas of a metal layer comprising the input pin1602aand the output pins,1602band1602d.

In some additional embodiments, the cut regions1704are separated by a minimum metal cut distance, so that the output pin1702dhas a length LOPthat is set by the minimum metal cut distance. For example, in some embodiments the output pin1702dmay have a length LOPthat is less than approximately 1.5 times the contact gate pitch CGP(i.e., a distance between same edges of adjacent gate structures904). In some additional embodiments, a length LOPof the output pin1702dis less than or equal to a length LIPof the input pin1702a, thereby ensuring an overlap between the input pin1702aand the output pin1702dis on a single end of the output pin1702d.

FIG.18illustrates a flow diagram of some embodiments of a method1800of forming an integrated circuit having a power horn structure configured to reduce parasitic resistance.

While the disclosed method1800is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At1802, a first gate structure is formed over a semiconductor substrate. In some embodiments, the first gate structure may comprise one of a plurality of gate structures are formed over a semiconductor substrate at a substantially regular pitch.FIG.11illustrates some embodiments corresponding to act1802.

At1804, an active area is formed. The active area comprises a first source/drain region and a second source/drain region formed on opposing sides of a first one of the plurality of gate structures. In some embodiments, the active area may include at least one fin, protruding outward from the semiconductor substrate, to form FinFET transistors.FIGS.10-11illustrate some embodiments corresponding to act1804.

At1806, first and second MEOL structures are formed over the first and second source/drain regions, respectively.FIGS.12-13illustrate some embodiments corresponding to act1806.

At1808, a conductive structure is formed over the second MEOL structure.FIG.14illustrates some embodiments corresponding to act1808.

At1810, a plurality of conductive contacts are formed over the MEOL structures and the plurality of gate structures.FIG.15illustrates some embodiments corresponding to act1810.

At1812, a metal interconnect layer is formed. The metal interconnect wire layer comprises a first metal wire coupled to the first gate structure by a conductive contact, a second metal wire coupled to the first source/drain region by a conductive contact, and a third metal wire electrically coupled to the second MEOL structure by two or more conductive contacts.FIG.16A-16Billustrates some embodiments corresponding to act1812.

At1814, one or more of the first or second metal wires are cut to reduce lengths of the one or more of the first or second metal wires.FIG.17illustrates some embodiments corresponding to act1814.

FIG.19illustrates a cross-sectional view of some embodiments of an integrated circuit1900having a power horn structure.

The integrated circuit1900comprises source/drain regions204al-204barranged within a semiconductor substrate102and separated by a channel region. An electrically active gate structure106a is arranged over the channel region. A metal layer comprises a MEOL structure108barranged over source/drain region204band a MEOL structure108cseparated from the MEOL structure108bby a dummy gate structure106b. Conductive contacts112are arranged between the MEOL structures,108band108c, and a power rail114. A conductive structure110is configured to electrically couple MEOL structure108bto MEOL structure108c. In some embodiments, the conductive structure110vertically contacts the dummy gate structure106band laterally contacts MEOL structure108band MEOL structure108c. In some embodiments, the conductive structure110has an upper surface that is substantially aligned with an upper surface of the metal layer. In some embodiments, the conductive structure110is arranged below the conductive contacts112.

FIG.20illustrates some additional embodiments of an integrated circuit2000having a power horn structure.

The integrated circuit2000comprises a plurality of source/drain regions204arranged within a semiconductor substrate102. Gate structures106a-106bare arranged between the plurality of source/drain regions204and MEOL structures108are over the plurality of source/drain regions204. The gate structures106a-106binclude electrically active gate structures106aand dummy gate structures106b. Conductive structures110are over the dummy gate structures106b. The conductive structures110vertically contact the dummy gate structures106band laterally contact MEOL structures108.

FIG.21illustrates yet additional embodiments of an integrated circuit2100having a power horn structure. The integrated circuit2100comprises a conductive structure110vertically contacting a dummy gate structure106b and laterally contacting MEOL structures108.

Therefore, the present disclosure relates to an integrated circuit having parallel conductive paths between a BEOL interconnect layer and a MEOL structure, which are configured to reduce a parasitic resistance and/or capacitance of an integrated circuit.

In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit comprises a first source/drain region and a second source/drain region arranged within a semiconductor substrate and separated by a channel region. A gate structure is arranged over the channel region, and a middle-end-of-the-line (MEOL) structure arranged over the second source/drain region. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is vertically arranged between the MEOL structure and a back-end-the-line (BEOL) interconnect wire, and a second conductive contact configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure.

In other embodiments, the present disclosure relates to an integrated circuit. The integrated circuit comprises a first gate structure extending over an active area in a first direction. The active area comprises a first source/drain region and a second source/drain region disposed within a semiconductor substrate. A first MEOL structure and a second MEOL structure are arranged on opposite sides of the first gate structure. The first MEOL structure extends over the first source/drain region and the second MEOL structure extends over the second source/drain region in the first direction. A conductive structure is arranged over and in electrical contact with the second MEOL structure. A first conductive contact is arranged over the second MEOL structure and below a metal power rail extending in a second direction perpendicular to the first direction. A second conductive contact configured to electrically couple the metal power rail and the second MEOL structure along a conductive path extending through the conductive structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

In yet other embodiments, the present disclosure relates to a method of forming an integrated circuit. The method comprises forming a first gate structure over a semiconductor substrate. The method further comprises forming a first source/drain region and a second source/drain region on opposing sides of the first gate structure. The method further comprises forming a first MEOL structure onto the first source/drain region and a second MEOL structure onto the second source/drain region. The method further comprises forming a conductive structure on and in direct contact with the second MEOL structure. The method further comprises forming a BEOL metal interconnect wire coupled to the second MEOL structure by a first conductive path extending through a first conductive contact arranged over the second MEOL structure and by a second conductive path extending through the conductive structure.