Patent ID: 12261221

DETAILED DESCRIPTION

Embodiments provide improvements in transistor characteristics.

In general, according to at least one embodiment, a transistor includes: an upper electrode; a lower electrode; a gate electrode disposed between the upper electrode and the lower electrode; and a columnar portion penetrating the gate electrode and disposed between the upper electrode and the lower electrode. The columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode, the semiconductor layer embedded in the gate insulating film and between the gate insulating film and the upper electrode and in contact with the upper electrode.

Hereinafter, embodiments for carrying out the disclosure will be described with reference to the drawings. The drawings are schematic. For example, thickness-planar dimension relationships, the ratio of the thickness of each layer, and so on may differ from the actual ones. In addition, in the embodiments, substantially identical components are denoted by the same reference numerals with redundant description omitted.

1. First Embodiment

A first embodiment will be described with reference toFIGS.1to8andFIGS.15.

1.1. Configuration

1.1.1. Configuration of Semiconductor Memory device

FIG.1is a perspective view schematically illustrating an example of the structure of the semiconductor memory device of the first embodiment. In at least one embodiment, a semiconductor memory device100is a nonvolatile semiconductor memory device such as a NAND flash memory. As illustrated inFIG.1, the semiconductor memory device100has a substrate1, a memory cell array2, a word line WL, a bit line BL, a drive circuit3, a sense amplifier4, a source-side select gate line SGS, and a drain-side select gate line SGD.

The memory cell array2includes a plurality of memory cell units MU above the substrate1. The memory cell unit MU has a memory string MS, a drain-side select transistor S1, and a source-side select transistor S2. In the memory string MS, a plurality of memory cells MC (MC1to MC4) (memory transistors) are connected in series. The drain-side select transistor S1and the source-side select transistor S2are respectively connected to both ends of the memory string MS. Although four memory cells MC are provided in one memory string MS inFIG.1, the number of memory cells MC provided in one memory string MS is not limited thereto. Of the memory cells MC in the memory string MS, one or more memory cells MC close to the source-side select gate line SGS and the drain-side select gate line SGD may be dummy cells not used for valid data storage. The number of dummy cells is freely selected.

The word line WL is connected in common to the memory cells MC adjacent to each other in the X direction inFIG.1. In addition, the source-side select gate line SGS is connected in common to the source-side select transistors S2adjacent to each other in the X direction. The drain-side select gate line SGD is connected in common to the drain-side select transistors S1adjacent to each other in the X direction.

The word line WL, the source-side select gate line SGS, and the drain-side select gate line SGD are processed so as to be stepped in the end portion in the X direction. As a result, each of the word line WL, the source-side select gate line SGS, and the drain-side select gate line SGD can be independently connected to a contact plug5. The contact plug5extends from the upper surface of the end portion of each of the word line WL, the source-side select gate line SGS, and the drain-side select gate line SGD processed so as to be stepped. Further, an upper layer wiring6is formed at the upper end of the contact plug5. A word line drive circuit31, a source-side select gate line drive circuit32, and a drain-side select gate line drive circuit33are connected to the word line WL, the source-side select gate line SGS, and the drain-side select gate line SGD via the contact plug5respectively. Although the word line WL, the source-side select gate line SGS, and the drain-side select gate line SGD are processed so as to be stepped in the X-direction end portion of the memory cell array2inFIG.1, the word line WL, the source-side select gate line SGS, and the drain-side select gate line SGD may be processed so as to be stepped so as to surround the entire periphery of the memory cell array2including the Y-direction end portion of the memory cell array2.

The bit lines BL are located at predetermined intervals in the X direction with the Y direction, which intersects with the X direction, serving as a long side. The bit line BL is connected to the plurality of memory strings MS via the drain-side select transistor S1.

A source line SL (not illustrated inFIG.1) is disposed with, for example, its long side extending in the Y direction. The source line SL is connected to the plurality of memory strings MS via the source-side select transistor S2.

The drive circuit3has the word line drive circuit31, the source-side select gate line drive circuit32, and the drain-side select gate line drive circuit33. The word line drive circuit31controls the voltage that is applied to the word line WL. The source-side select gate line drive circuit32controls the voltage that is applied to the source-side select gate line SGS. The drain-side select gate line drive circuit33controls the voltage that is applied to the drain-side select gate line SGD.

The sense amplifier4is a circuit amplifying a signal read from the selected memory cell MC to the bit line BL.

1.1.2. Configuration of Memory Cell Array

FIG.2is a perspective view illustrating the structure of a part of the memory cell array of the first embodiment.FIG.3is a plan view illustrating a part of the memory cell array of the first embodiment. An example of the configuration of the memory cell array will be described with reference toFIGS.2and3. Illustrated inFIG.1is a case where four layers of word line WL, one layer of source-side select gate line SGS, and one layer of drain-side select gate line SGD, that is, a total of six layers of conductive film11are provided. Illustrated inFIG.2is a case where 27 layers of word line WL, four layers of source-side select gate line SGS, and four layers of drain-side select gate line SGD, that is, a total of 35 layers of conductive film11are provided.

The memory cell array2has a structure in which the conductive films11and interlayer insulating films12are alternately stacked above the substrate1along the Z direction, which intersects with each of the X and Y directions. The conductive film11functions as a memory cell control gate (word line WL), the source-side select gate line SGS, and the drain-side select gate line SGD. The conductive film11is, for example, tungsten (W), titanium nitride (TiN), or the like. The interlayer insulating films12are disposed above and below the conductive film11and electrically insulate the conductive films12from each other. The interlayer insulating film12is, for example, silicon oxide (SiO2) or the like.

In addition, the stacked body of the interlayer insulating film12and the conductive film11in the memory cell array2is divided into blocks. The block is the minimum unit of data erasure. A trench7is formed at the boundary of the divided blocks. An interlayer insulating layer9(not illustrated inFIG.2) is embedded in the trench7. Further, a source contact8is formed through the interlayer insulating layer9. The source contacts8are formed at predetermined intervals in the Y direction with the X direction serving as a long side. The lower end of the source contact8is connected to the substrate1, and the upper end of the source contact8is connected to the source line SL.

A semiconductor layer14functions as a channel for the memory cell, the drain-side select transistor S1, and the source-side select transistor S2. The semiconductor layers14are, for example, aligned in a diagonal direction with respect to the X direction and the Y direction in a line. One bit line BL extending in the Y direction is connected to any one of the semiconductor layers14arranged in the diagonal direction. As a result, only one memory string MS in one region sandwiched between two source contacts8can be connected to one bit line BL. However, the arrangement illustrated inFIG.3is merely an example and the semiconductor layers14may be aligned in the X direction and the Y direction.

In addition, the semiconductor layers14are located at predetermined intervals in the XY plane so as to penetrate the stacked body of the interlayer insulating film12and the conductive film11in the Z direction. The upper end of the semiconductor layer14is connected to the bit line BL via a contact. In addition, the lower end of the semiconductor layer14is electrically connected to the substrate1. The lower end of the semiconductor layer14is connected to the source line SL via the substrate1and the source contact8.

In at least one embodiment, the semiconductor layer14is, for example, an oxide semiconductor. The oxide semiconductor contains, for example, indium oxide, gallium oxide, and zinc oxide. The oxide semiconductor containing indium oxide, gallium oxide, and zinc oxide as described above is referred to as In—Ga—Zn oxide (IGZO). In addition, an oxide containing at least one of indium, zinc, and tin (e.g. InO, InZnO, InSnO, Sno, Zno, and ZnSnO) may be used as the oxide semiconductor.

A gate insulating film13is provided around the semiconductor as to surround the layer14so semiconductor layer14. The gate insulating film13is, for example, silicon oxide (SiO2).

1.1.3. Configuration of Transistor

FIG.4is a perspective view illustrating an example of the configuration of the transistor of the first embodiment.

A transistor10is used as a memory cell (memory transistor) in at least one embodiment. As illustrated inFIG.4, the transistor10includes a conductive film111as a lower electrode BE, a conductive film112as a gate electrode GE, a conductive film113as an upper electrode TE, and a columnar portion PI. Although the source-side select gate line SGS is disposed between the conductive film111and the substrate1, the source-side select gate line SGS is not illustrated inFIG.4. The transistor10ofFIG.4is the transistor at the top ofFIG.1. That is, the transistor10ofFIG.4is the drain side selection transistor S1ofFIG.1. However, the transistor10ofFIG.4may be the memory cell MC.

Each of the conductive film111and the conductive film113functions as a source electrode or a drain electrode of the transistor10. The conductive film111is, for example, provided above the substrate1. The conductive film113is provided above the conductive film111. For example, indium tin oxide (ITO), tungsten (W), or the like is used for the conductive film111and the conductive film113.

The conductive film112functions as a gate electrode of the transistor10. The conductive film112is provided between the conductive film113as the upper electrode TE and the conductive film111as the lower electrode BE. For example, tungsten (W), titanium nitride (TiN), or the like is used for the conductive film112.

The columnar portion PI has the semiconductor layer14and the gate insulating film13. The columnar portion PI is provided in, for example, a columnar shape extending in the Z direction. In addition, the columnar portion PI penetrates the conductive film112and is provided between the conductive film111and the conductive film113. The lower end of the columnar portion PI is electrically connected to the conductive film111, and the upper end of the columnar portion PI is electrically connected to the conductive film113.

In this manner, the transistor10is referred to as, for example, a vertical transistor because a current flows via the columnar portion PI extending in the Z direction between the conductive film111as the lower electrode BE and the conductive film113as the upper electrode TE.

FIG.5is a cross-sectional view illustrating an example of the configuration of the transistor of the first embodiment. A more detailed configuration of the transistor10will be described with reference toFIG.5.

As illustrated inFIG.5, the transistor10includes the conductive film111as the lower electrode BE, an interlayer insulating film121as a first insulating film, the conductive film112as the gate electrode GE, an interlayer insulating film122as a second insulating film, the conductive film113as the upper electrode TE, and the columnar portion PI.

The interlayer insulating film121is provided on the conductive film111. The conductive film112is provided on the interlayer insulating film121. The interlayer insulating film122is provided on the conductive film112. The conductive film113is provided on the interlayer insulating film122. The columnar portion PI extending in the Z direction is provided between the conductive film111and the conductive film113.

In the columnar portion PI, the gate insulating film13is provided in a cylindrical shape and is in contact with the conductive film112as the gate electrode GE. The upper end of the gate insulating film13is separated by a first distance T1from the lower end of the conductive film113as the upper electrode TE. The lower end of the gate insulating film13is in contact with the conductive film111. For example, silicon oxide (SiO2) or the like is used for the gate insulating film13.

The semiconductor layer14is basically embedded in the gate insulating film13provided in a cylindrical shape. The upper end of the semiconductor layer14is in contact with the conductive film113. Although the upper end of the semiconductor layer14is in contact with the conductive film113in at least one embodiment, the upper end of the semiconductor layer14may be in contact with the conductive film113via a contact. The lower end of the semiconductor layer14is in contact with the conductive film111. In other words, the upper end of the semiconductor layer14is higher than the upper end of the gate insulating film13. Accordingly, the semiconductor layer14has a part14aembedded in the gate insulating film13and a part14bembedded between the gate insulating film13and the conductive film113as the upper electrode TE. The part14aof the semiconductor layer14embedded in the gate insulating film13is insulated from the conductive film112by the gate insulating film13. In addition, a recess portion is formed in the middle of the semiconductor layer14. An embedded insulating film15is formed in the recess portion.FIG.15is a perspective view schematically illustrating an example of the structure of a semiconductor memory device of an alternative example of the first embodiment. As shown inFIG.15, the embedded insulating film15may not be formed in the recess portion.

In at least one embodiment, the thickness of a film in the XY plane is referred to as the film diameter. A film diameter T2aof the part14aof the semiconductor layer14embedded in the gate insulating film13is represented by T2a=a radius T3of the columnar portion PI—a film diameter T4of the gate insulating film13. In addition, a film diameter T2bof the part14bof the semiconductor layer14embedded between the gate insulating film13and the conductive film113is preferably larger than the film diameter T2aof the part14aof the semiconductor layer14embedded in the gate insulating film13and smaller than the radius T3of the columnar portion PI. In other words, the film diameter T2aof the part14aof the semiconductor layer14embedded in the gate insulating film13, the film diameter T2bof the part14bof the semiconductor layer14embedded between the gate insulating film13and the conductive film113, and the radius T3of the columnar portion PI have the relationship of T2a<T2b<T3. Further, the distance T1from the upper end of the gate insulating film13to the lower end of the conductive film113is preferably equal to or less than the film diameter T2aof the part14aof the semiconductor layer14embedded in the gate insulating film13.

1.2. Manufacturing Method

A manufacturing method for the transistor of the first embodiment will be described with reference toFIGS.6and7.

FIG.6is a flowchart illustrating an example of the manufacturing method for the transistor of the first embodiment.FIG.7is a process diagram illustrating an example of the manufacturing method for the transistor of the first embodiment. Hereinafter, an example of the manufacturing method for the transistor10according to the first embodiment will be described from the formation of the conductive film111as the lower electrode BE to the formation of the conductive film113as the upper electrode TE with reference toFIGS.6and7.

First, in Step S1, the conductive film111as the lower electrode BE is formed above the substrate1(not illustrated inFIG.7) as illustrated inFIG.7A. For example, sputtering is used for the formation of the conductive film111.

Next, in Step S2, the interlayer insulating film121as the first insulating film is formed on the conductive film111as illustrated inFIG.7B. For example, sputtering is used for the formation of the interlayer insulating film121.

Next, in Step S3, the conductive film112as the gate electrode GE is formed on the interlayer insulating film121as illustrated inFIG.7C.

Next, in Step S4, the interlayer insulating film122as the second insulating film is formed on the conductive film112as illustrated inFIG.7D.

Next, in Step S5, a hole HL corresponding to the columnar portion PI is formed as illustrated inFIG.7E. In other words, the radius T3of the columnar portion PI is equal to the radius of the hole HL. The hole HL is formed by, for example, photolithography and anisotropic etching so as to penetrate the interlayer insulating film121, the conductive film112, and the interlayer insulating film122and reach the upper surface of the conductive film111. For example, reactive ion etching (RIE) is used as the anisotropic etching.

Next, in Step S6, the gate insulating film13is formed on the side wall of the hole HL as illustrated inFIG.7F. Specifically, first, the gate insulating film13is formed on each of the upper surface of the interlayer insulating film122, the side wall of the hole HL, and the upper surface of a part of the conductive film111as the bottom surface of the hole HL by, for example, chemical vapor deposition (CVD) or the like.

Next, in Step S7, the gate insulating film13formed on, for example, each of the interlayer insulating film122and the upper surface of the part of the conductive film111as the bottom surface of the hole HL is removed by etching back the entire surface by anisotropic etching such as RIE. Then, as illustrated inFIG.7G, the gate insulating film13at a part of the side wall of the hole HL is further removed by etch back. In the present embodiment, the gate insulating film13on the side wall of the hole HL is removed up to the position where the distance from the upper end of the interlayer insulating film122to the upper end of the gate insulating film13is T1. As a result, the height of the semiconductor layer14becomes higher than the height of the gate insulating film13by a process to be described later. After the etch back, the upper surface of the interlayer insulating film122may be flattened by chemical mechanical polishing (CMP).

Next, in Step S8, the semiconductor layer14is formed as illustrated inFIG.7H. Specifically, the semiconductor layer14is embedded in the hole HL and on the gate insulating film13by, for example, atomic layer deposition (ALD) or the like and comes into contact with the conductive film111as the lower electrode BE on the bottom surface of the hole HL. In the present embodiment, the semiconductor layer14is also formed on the interlayer insulating film122as the semiconductor layer14is formed in the hole HL. In addition, the recess portion where the embedded insulating film15can be embedded in, for example, a step to be described later is formed in the middle portion of the semiconductor layer14on the side of the conductive film113as the upper electrode TE.

Next, in Step S9, the embedded insulating film15is formed as illustrated inFIG.7I. Specifically, the embedded insulating film15is formed in the middle recess portion of the semiconductor layer14and on the semiconductor layer14formed in Step S8. By forming the embedded insulating film15, flattening the step10described later becomes easy. In addition, when the embedded insulating film15is not formed, step S9 may be omitted.

Subsequently, in Step S10, the semiconductor layer14and the embedded insulating film15are flattened as illustrated inFIG.7J. Specifically, the upper surfaces of the semiconductor layer14and the embedded insulating film15are flattened by, for example, CMP and the height becomes equal to the height of the interlayer insulating film122.

Then, in Step S11, the conductive film113as the upper electrode TE is formed by, for example, sputtering as illustrated inFIG.7K. As a result, the structure of the transistor10according to the first embodiment described with reference toFIG.5is formed.

1.3. Effect

A current Id flowing through the channel of the transistor is represented by a drain voltage Vd/(contact resistance Rate of the upper electrode TE+contact resistance Rcbe of the lower electrode BE+channel resistance Rch). Contact resistance Rc is the resistance attributable to the contact between the upper electrode TE and the channel, and the channel and the lower electrode BE.

When annealing is performed in the process of manufacturing the transistor, oxygen preferentially enters from the upper electrode TE side. Accordingly, the oxygen vacancy concentration on the upper electrode TE side of the semiconductor layer is lower than the oxygen vacancy concentration on the lower electrode BE side of the semiconductor layer. Accordingly, the contact resistance on the upper electrode TE side is larger than the contact resistance on the lower electrode BE side (Rcte>Rcbe). Accordingly, the transistor characteristics are different between a case where the upper electrode TE is a drain electrode and the lower electrode BE is a source electrode and a case where the upper electrode TE is a source electrode and the lower electrode BE is a drain electrode.

In addition, when the contact diameter of the source electrode/drain electrode falls below, for example, approximately 40 nm as a result of miniaturization, the value of the contact resistance becomes dominant in the current Id. In the miniaturization, the current Id can be increased by reducing the contact resistance.

Hereinafter, the effect of the present embodiment will be described using a comparative example.

FIG.8is a cross-sectional view illustrating the comparative example of the transistor of the first embodiment. As illustrated inFIG.8, a transistor10′ includes a conductive film111′ as the lower electrode BE, an interlayer insulating film121′, a conductive film112′ as the gate electrode GE, a conductive film113′ as the upper electrode TE, an interlayer insulating film122′, and the columnar portion PI. The columnar portion PI includes a gate insulating film13′ and a semiconductor layer14′. The heights of the gate insulating film13′ and the semiconductor layer14′ are equal to each other, and the upper ends of the gate insulating film13′ and the semiconductor layer14′ are in contact with the conductive film113′ as the upper electrode TE. The other configurations are similar to those of the transistor10described with reference toFIG.5and the description thereof will be omitted.

In at least one embodiment, the upper end of the gate insulating film13is lower than the upper end of the semiconductor layer14and the semiconductor layer14is provided between the gate insulating film13and the conductive film113as the upper electrode TE. Accordingly, the area of contact of the semiconductor layer14with the upper electrode TE can be increased as compared with the transistor10′ of the comparative example and the resistance on the upper electrode TE side can be reduced. Specifically, the film diameter of the semiconductor layer14coming into contact with the upper electrode TE is T2bin at least one embodiment whereas the film diameter of the semiconductor layer14′ coming into contact with the upper electrode TE is T2ain the comparative example. Accordingly, the area of contact with the upper electrode TE can be increased by approximately (T2b∧2-T2a∧2)π.

From the above, according to at least one embodiment, the height of the gate insulating film13is made lower than the height of the semiconductor layer14, the semiconductor layer14is provided between the gate insulating film13and the conductive film113as the upper electrode TE, and thus the resistance Rcte on the upper electrode TE side of the semiconductor layer14can be reduced and the current Id flowing through the channel of the transistor can be increased. In addition, the difference between the contact resistance Rcte on the upper electrode TE side and the contact resistance Rcbe on the lower electrode BE side can be reduced. In other words, the transistor characteristics can be improved. Further, a more remarkable effect can be obtained at a contact diameter at which the contact resistance Rc is dominant with respect to the current Id flowing through the channel of the transistor.

In addition, in at least one embodiment, the film diameter T2bof the part14bof the semiconductor layer14embedded between the gate insulating film13and the conductive film113is larger than the film diameter T2aof the part14aof the semiconductor layer14embedded in the gate insulating film13and smaller than the radius T3of the columnar portion PI. Accordingly, the columnar portion PI can be disposed as illustrated inFIG.3without the semiconductor layer14protruding from the columnar portion PI.

In addition, the distance T1from the upper end of the gate insulating film13to the lower end of the conductive film113is equal to or less than the film diameter T2aof the part14aof the semiconductor layer14embedded in the gate insulating film13. Accordingly, it is possible to prevent a decrease in the area of contact between the semiconductor layer14and the upper electrode TE attributable to the embedded insulating film15formed in the recess portion of the semiconductor layer14and an increase in the length of the semiconductor layer14as a channel.

In addition, in the semiconductor memory device100including the transistor10according to at least one embodiment, the current Id flowing through the channel of the transistor can be increased. Further, an improvement in operating speed can be anticipated from the improvement of the transistor characteristics.

In addition, in the manufacturing method for the transistor10according to at least one embodiment, the height of the gate insulating film13is lower than the height of the interlayer insulating film122and the semiconductor layer14is easily embedded by the frontage widening. Accordingly, the occurrence of poor embedding of the semiconductor layer14can be prevented.

2. Second Embodiment

Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that the upper electrode TE comes into contact with not only the upper portion of the semiconductor layer but also the side surface and the middle recess portion. The configuration is similar to that of the first embodiment except that the upper electrode TE comes into contact with not only the upper surface of the semiconductor layer but also the side surface and the middle recess portion, and thus the same parts will be denoted by the same reference numerals with redundant description omitted.

2.1. Configuration

The configuration of the transistor of the second embodiment will be described with reference toFIG.9.FIG.9is a cross-sectional view illustrating an example of the configuration of the transistor of the second embodiment.

A transistor20is used as a memory cell (memory transistor) in the present embodiment. As illustrated inFIG.9, the transistor20includes the conductive film111as the lower electrode BE, the interlayer insulating film121, the conductive film112as the gate electrode GE, an interlayer insulating film222as the second insulating film, the conductive film113as the upper electrode TE, and the columnar portion PI.

The interlayer insulating film121is provided on the conductive film111. The conductive film112is provided on the interlayer insulating film121. The interlayer insulating film222is provided on the conductive film112. The conductive film113is provided on the interlayer insulating film222. The columnar portion PI extending in the Z direction is provided between the conductive film111and the conductive film113.

Each of the conductive film111and the conductive film113functions as a source electrode or a drain electrode of the transistor20. The conductive film111is, for example, provided above the substrate1. The conductive film113is provided above the conductive film111. For example, indium tin oxide (ITO), tungsten (W), or the like is used for the conductive film111and the conductive film113.

The columnar portion PI has a semiconductor layer24and the gate insulating film13. The columnar portion PI is provided in, for example, a columnar shape extending in the Z direction and penetrates the conductive film112. The lower end of the columnar portion PI is electrically connected to the conductive film111, and the upper end of the columnar portion PI is electrically connected to the conductive film113.

In the columnar portion PI, the semiconductor layer24has a recess portion in the middle on the side of the conductive film113as the upper electrode TE. The conductive film113as the upper electrode TE is formed in the recess portion. The lower end of the recess portion is higher than the upper end of the gate insulating film13. In at least one embodiment, the conductive film113as the upper electrode TE is formed in the recess portion, but the embedded insulating film15may be formed in the recess portion.

The upper end of the semiconductor layer24is in contact with the conductive film113. In addition, the upper end of the semiconductor layer24is higher by a second distance T5than the upper end of the gate insulating film13. At least a part of the side surface of the part14bof the semiconductor layer24embedded between the gate insulating film13and the conductive film113is in contact with the conductive film113. In at least one embodiment, the side surface of a part24cof the semiconductor layer24higher than the upper end of the interlayer insulating film222and not embedded in the gate insulating film13is in contact with the conductive film113. Further, the recess portion of the semiconductor layer24is also in contact with the conductive film113. The lower end of the semiconductor layer24is in contact with the conductive film111. In other words, the upper end of the semiconductor layer24is higher than the upper end of the gate insulating film13. Specifically, the upper end of the semiconductor layer24is higher by the second distance T5than the upper end of the gate insulating film13. In addition, the first distance T1as the distance from the upper end of the gate insulating film13to the lower end of the conductive film113is smaller than the second distance T5as the distance from the upper end of the gate insulating film13to the upper end of the semiconductor layer24.

2.2. Manufacturing Method

A manufacturing method for the transistor of the second embodiment will be described with reference toFIGS.10and11.

FIG.10is a flowchart illustrating an example of the manufacturing method for the transistor of the second embodiment.FIG.11is a process diagram illustrating an example of the manufacturing method for the transistor of the second embodiment. Hereinafter, an example of the manufacturing method for the transistor20according to the second embodiment will be described from the formation of the conductive film111as the lower electrode BE to the formation of the conductive film113as the upper electrode TE with reference toFIGS.10and11.

Up to Step S3 (FIG.7C) is the same as in the first embodiment.

First, in Step S21, the interlayer insulating film222is formed as illustrated inFIG.11A. The interlayer insulating film222is partially removed in Step S22to be described later, and thus the interlayer insulating film222is formed thicker than the interlayer insulating film122of the first embodiment.

Subsequently, Steps S5 to S6 are performed similarly to the first embodiment as illustrated inFIGS.11B to11C.

Next, in Step S7, the gate insulating film13formed on, for example, each of the interlayer insulating film222and the upper surface of a part of the conductive film111as the bottom surface of the hole HL is removed by anisotropic etching such as RIE. Then, as illustrated inFIG.11D, the gate insulating film13at a part of the side wall of the hole HL is removed by etch back. In at least one embodiment, the gate insulating film13on the side wall of the hole HL is removed up to the position where the distance from the upper end of the interlayer insulating film222to the upper end of the gate insulating film13is the second distance T5. As a result, the height of the semiconductor layer24becomes higher than the height of the gate insulating film13by a process to be described later. After the etch back, the upper surface of the interlayer insulating film222may be flattened by chemical mechanical polishing (CMP).

Subsequently, Steps S8 to S10are performed similarly to the first embodiment as illustrated inFIGS.11E to11G.

Next, in Step S22, a part of the interlayer insulating film222and the embedded insulating film15are removed by etch back as illustrated inFIG.11H. For example, the interlayer insulating film222and the embedded insulating film15are removed at the position higher by the first distance T1than the upper end of the gate insulating film13. Specifically, in at least one embodiment, the interlayer insulating film222is removed so as to be higher than the lower end of the recess portion of the semiconductor layer24and lower than the upper end of the semiconductor layer24. All embedded insulating film15is removed. Accordingly, the height of the semiconductor layer24becomes higher than that of the interlayer insulating film222and the side surface of the semiconductor layer24is exposed in part. In addition, by removing a part of the interlayer insulating film222up to a position higher than the lower end of the recess portion of the semiconductor layer24, it is possible to avoid problems such as leakage current generation while increasing the area of contact between the recess portion of the semiconductor layer24and the conductive film113as the upper electrode TE. In at least one embodiment, all embedded insulating films15is removed, but a part of the embedded insulating film15may be removed, and a part of the embedded insulating film15may be formed in the recess portion.

Then, as illustrated inFIG.11I, the conductive film113is formed in Step22as in the first embodiment. As a result, the structure of the transistor20of the second embodiment described with reference toFIG.9is formed.

2.3. Effect

As described above, effects similar to those of the first embodiment can be obtained according to the present embodiment. In addition, since the upper electrode TE comes into contact with a part of the side surface of the semiconductor layer24and the recess portion of the semiconductor layer24in addition to the upper surface of the semiconductor layer24, the area of contact between the semiconductor layer24and the upper electrode TE can be further increased and the current Id flowing through the channel of the transistor can be further increased as compared with the first embodiment. Further, the contact resistance Rcte on the upper electrode TE side can be further reduced as compared with the first embodiment, and thus the transistor characteristics can be expected to be further improved.

In addition, in a semiconductor memory device including the transistor20according to at least one embodiment, more power reduction than in the first embodiment can be achieved. Further, since the transistor characteristics can be expected to be further improved as compared with the first embodiment, the operating speed can be expected to be further improved as compared with the first embodiment. In addition, effects similar to those of the first embodiment can be obtained also in the manufacturing method for the transistor20according to the present embodiment.

3. Third Embodiment

Next, a third embodiment will be described. The third embodiment differs from the first embodiment in that the radius of the columnar portion PI decreases toward the lower electrode BE. The configuration is similar to that of the first embodiment except that the radius of the columnar portion PI decreases toward the lower electrode BE, and thus the same parts will be denoted by the same reference numerals with redundant description omitted.

3.1. Configuration

The transistor of the third embodiment will be described with reference toFIG.12and Fid.16.FIG.12is a cross-sectional view illustrating an example of the structure of the transistor of the third embodiment.FIG.16is a perspective view schematically illustrating an example of the structure of a semiconductor memory device of an alternative example of the third embodiment.

As illustrated inFIG.12, a transistor30of the third embodiment includes the conductive film111as the lower electrode BE, the interlayer insulating film121, the conductive film112as the gate electrode GE, the interlayer insulating film122, the conductive film113as the upper electrode TE, and the columnar portion PI.

The diameter of the columnar portion PI decreases toward the conductive film111from the conductive film113. Specifically, the radius of the columnar portion PI is T3on the side of the conductive film113as the upper electrode TE and T6on the side of the conductive film111as the lower electrode BE (T3>T6). In addition, as the radius of the columnar portion PI decreases, a film diameter T7of the semiconductor layer14on the side of the conductive film111as the lower electrode BE is smaller than the film diameter T2aof the semiconductor layer14on the side of the conductive film111as the lower electrode BE of the transistor10of the first embodiment (T2a>T7). The fact that the diameter of the columnar portion PI decreases toward the conductive film111from the conductive film113can be rephrased as the cross-sectional area of the columnar portion PI in the XY direction decreasing toward the conductive film111from the conductive film113. As shown inFIG.16, the embedded insulating film15may not be formed in the recess portion.

3.2. Effect

As described above, effects similar to those of the first embodiment can be obtained according to the present embodiment. In addition, the radius of the semiconductor layer14on the upper electrode TE side of the columnar portion PI with respect to the diameter of the semiconductor layer14on the lower electrode BE side is larger than in the first embodiment. Accordingly, the area of contact of the semiconductor layer14on the upper electrode TE side with the upper electrode TE can be increased as compared with the first embodiment and the current Id flowing through the channel of the transistor can be further increased. Further, the contact resistance Rcte on the upper electrode TE side can be reduced as compared with the first embodiment and the transistor characteristics can be expected to be further improved.

In addition, in a semiconductor memory device including the transistor30according to the present embodiment, more power reduction than in the first embodiment can be achieved. Further, since the transistor characteristics can be expected to be further improved as compared with the first embodiment, the operating speed can be expected to be further improved as compared with the first embodiment. In addition, effects similar to those of the first embodiment can be obtained also in the manufacturing method for the transistor30according to the present embodiment.

4. Fourth Embodiment

Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment in that the transistor is used in a peripheral circuit. The configuration is similar to that of the first embodiment except that the transistor is used in a peripheral circuit, and thus the same parts will be denoted by the same reference numerals with redundant description omitted.

In addition, in the present embodiment, reference numerals without alphabetic suffixes will be used when the components indicated by reference numerals with different alphabetic suffixes do not have to be distinguished from each other.

4.1. Configuration

FIG.13is a circuit diagram illustrating an example of the configuration of the memory cell array of the semiconductor memory device of the fourth embodiment. In the present embodiment, the semiconductor memory device is, for example, a volatile semiconductor memory device such as a dynamic random access memory (DRAM).

The semiconductor memory device includes a memory cell array400. As illustrated inFIG.13, the memory cell array400includes a memory cell40(40a,40b), the word line WL (WLa, WLb), the bit line BL (BLa, BLb), the source line SL, and a dummy cell42(42a,42b).

The word line WL is connected in common to the memory cells40adjacent to each other in the X direction. The bit lines BL are located at predetermined intervals in the X direction with the Y direction, which intersects with the X direction, serving as a long side. In addition, the memory cell40sadjacent to each other in the Y direction are connected to the common bit line BL. The source line SL is disposed with, for example, the Y direction serving as a long side.

In the present embodiment, the memory cell40includes the transistor10and a capacitor41.

One terminal of the transistor10is connected to the bit line BL. The other terminal of the transistor10is connected to one terminal of the capacitor41. The other terminal of the capacitor41is connected to the source line SL. In addition, the gate of the transistor10is connected to the word line WL.

The dummy cell42(42a,42b) is provided in, for example, the end portion of the memory cell array400in the Y direction. One terminal of the dummy cell42is connected to the bit line BL. The other terminal of the dummy cell42is connected to the source line SL. The gate of the dummy cell42ais connected to a word line WLza. The gate of the dummy cell42bis connected to a word line WLzb. In addition, in the dummy cell42, the capacitor41is not provided between the transistor10and the source line SL.

During operation with respect to the memory cell40, the dummy cell42is set to the ON state in addition to the transistor10. The dummy cell42contributes to the operation of the memory cell40. The dummy cell42functions as a selection element of the memory cell40. Specifically, for example, the dummy cell42bis activated when the memory cell40abetween the bit line BLa and the source line SL is selected in response to the operation to be executed by the DRAM. On the other hand, the dummy cell42ais activated when the memory cell40bbetween the bit line BLb and the source line SL is selected. In this manner, during operation with respect to the memory cell40, the capacitor41is connected to the two bit lines BLa and BLb via the transistor10and the dummy cell42.

FIG.14is a cross-sectional view illustrating an example of the configuration of the memory cell array of the semiconductor memory device of the fourth embodiment. A cross-sectional structure of the memory cell array400is schematically illustrated inFIG.14. The insulating layer that covers the components of the DRAM is not illustrated inFIG.14. The insulating film that covers the components of the DRAM is, for example, an interlayer insulating film.

As illustrated inFIG.14, in the DRAM of the present embodiment, the memory cell array400is provided above a substrate (not illustrated). A transistor10bis provided above the bit line BLb. A capacitor41bis provided above the transistor10b. The source line SL is provided above the capacitor41b. A capacitor41ais provided above the source line SL. A transistor10ais provided above the capacitor41a. The bit line BLa is provided above the transistor10a.

As described above, in the memory cell40of the DRAM of the present embodiment, the transistor10(10a,10b) and the capacitor (41a,41b) are stacked41perpendicularly to the surface of the substrate.

In the memory cell40, the capacitor41(41a,41b) includes a conductive film114and a conductive film115as capacitor electrodes and an insulating film16as a capacitor insulating film. The insulating film16is provided between the conductive film114and the conductive film115. The insulating film16is a dielectric between the conductive film114and the conductive film115. The capacitor41is capable of holding an electric charge. The capacitance of the capacitor41is appropriately set in accordance with the area of facing of the conductive films114and115as two capacitor electrodes, the dielectric constant of the material of the insulating film16as a capacitor insulating film, the film diameter of the insulating film16as a capacitor insulating film, and so on.

The transistor10(10a,10b) includes the gate insulating film13, the semiconductor layer14, the conductive film111as the lower electrode BE, the conductive film112as the gate electrode GE, and the conductive film113as the upper electrode TE.

The configuration of the transistor10of the present embodiment is similar to that of the transistor of the first embodiment illustrated inFIG.5, and thus detailed description thereof will be omitted.

In addition, as illustrated inFIG.14, the dummy cell42bis provided above the bit line BLb in the DRAM of the present embodiment. A contact plug43bis provided above a dummy cell24b. The source line SL is provided above the contact plug43b. A contact plug43ais provided above the source line SL. The dummy cell42ais provided above the contact plug43a. The bit line BLa is provided above the dummy cell42a.

4.2. Effect

As described above, effects similar to those of the first embodiment can be obtained according to the present embodiment. In addition, use is possible not only in a nonvolatile semiconductor memory device such as the NAND flash memory illustrated in the first to third embodiments but also in a volatile semiconductor memory device such as the DRAM illustrated in the present embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure.

The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.