Patent ID: 12218188

Like reference symbols in the various drawings indicate like elements. Details of one or more implementations of the present disclosure are set forth in the accompanying drawings and the descriptions below. The figures are not drawn to scale and they are provided merely to illustrate the disclosure. Specific details, relationships and methods are set forth to provide an understanding of the disclosure. Other features and advantages may be apparent from the description and drawings and from the claims.

DETAILED DESCRIPTION

The present disclosure is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.

Deep trench structures are found in many semiconductor devices such as high voltage analog semiconductor devices. In high voltage applications, a deep trench structure may include a conductive filler which can serve as a field plate for reducing electrical field density or as a gate electrode of a vertical transistor (e.g., a vertical diffused MOS (VDMOS transistor)). Deep trench structures can be formed with dielectric fill materials to provide isolation between electrical components.

In this disclosure and the claims that follow, unless stated otherwise and/or specified to the contrary, any one or more of the layers set forth herein can be formed in any number of suitable ways, such as with spin-on techniques, sputtering techniques (e.g., Magnetron and/or ion beam sputtering), (thermal) growth techniques or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD), for example. As another example, silicon nitride may be a silicon-rich silicon nitride or an oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the materials dielectric constant is substantially different from that of high purity stoichiometric silicon nitride.

It is noted that terms such as top, bottom, and under may be used in this disclosure. These terms should not be construed as limiting the position or orientation of a structure or element, but should be used to provide spatial relationship between structures or elements.

Shown inFIG.1AthroughFIG.1E, a semiconductor device100can be formed under a sequence that forms a deep trench structure. Referring toFIG.1A, the semiconductor device100can be a discrete component device (e.g., A single transistor) or a semiconductor device having multiple devices. At an early state of the fabrication sequence, a pad oxide layer104, a nitride cap layer106and a hard mask layer108may be sequentially formed on a top surface of a semiconductor substrate102. The pad oxide layer104services the function of stress relief between the semiconductor substrate102and subsequent layers, and it may include silicon dioxide that is formed by a thermal oxidation process or a chemical vapor deposition process. The nitride cap layer106serves the function of exclusionary film allowing selective oxidation, and it may include silicon nitride (e.g., Si3N4that is deposited under a low-pressure chemical vapor deposition (LPCVD) furnace process). The hard mask layer108serves the function of a hard mask during a subsequent deep trench etch process, and it may include a silicon dioxide that is deposited under a plasma enhanced chemical vapor deposition (PECVD) process.

Next, a photoresist mask110is deposited and patterned with an opening exposing a deep trench region112of the semiconductor substrate102. The photoresist mask110serves the function of masking the hard mask layer108and it may include a light sensitive organic material that is coated, exposed and developed.

InFIG.1B, a deep trench etch process114is performed to form a deep trench116. The deep trench etch process114may include multiple sequences. In one implementation for example, a hard mask etch may be first performed to remove the hard mask layer108exposed by the patterned photoresist mask110, and a silicon etch may then be performed to remove the nitride cap layer106, the pad oxide layer104, and the semiconductor substrate102that are exposed by the etched hard mask layer. During the silicon etch, the photoresist mask110is also removed, leaving the hard mask layer108to prevent the area outside of the deep trench region112from being etched.

As shown inFIG.1C, for example, a dielectric liner118may be deposited onto the surfaces of the semiconductor substrate102by a dielectric liner deposition process120. In one implementation, the dielectric liner deposition process120may include a sub atmospheric chemical vapor deposition of an oxide target. The dielectric liner deposition process120may be followed by a trench dielectric etch process to achieve a uniform thickness of the dielectric liner118along the sidewall of the deep trench116. In one version of this example, the dielectric liner118may include silicon dioxide formed by a thermal oxidation process.

Referring toFIG.1D, a trench fill deposition process122is performed to fill the deep trench116with a conductive or dielectric material. The trench fill deposition process122may be implemented as a dielectric deposition process122or a polycrystalline silicon, referred to herein as polysilicon, deposition process122, by way of example.

As a result, a trench filler material124is formed in the deep trench116, and extending over the top surface of a semiconductor substrate102. The trench filler material124may contact the dielectric liner118. Alternatively, the trench filler structure may directly contact the sidewall of the deep trench116in versions of this example in which the dielectric liner118is absent. During the trench fill deposition process122, a trench filler seam126may form along the vertical middle section of the trench filler material124. The dimensions of the trench filler seam126may depend on the aspect ratio of the deep trench116.

Referring toFIG.1E, after the trench filler material124is formed, material of the trench filler material124outside of the deep trench116is removed by a planarization process128, leaving the trench filler material124outside of the deep trench116to form a deep trench structure130. The planarization process128may be implemented as a chemical mechanical polish (CMP) process128or an etch back process, by way of example.

FIG.2AandFIG.2Bare a top view and a cross section, respectively, of an example semiconductor device200with four intersecting linear trench segments. Referring toFIG.2A, the semiconductor device200includes a semiconductor substrate202. The semiconductor device200of this example includes a deep trench structure230having a first linear trench segment232in the semiconductor substrate202, a second linear trench segment234in the semiconductor substrate202, a third linear trench segment236in the semiconductor substrate202, and a fourth linear trench segment238in the semiconductor substrate202. The first linear trench segment232, the second linear trench segment234, the third linear trench segment236, and the fourth linear trench segment238may be formed as disclosed in reference toFIG.1AthroughFIG.1E. The first linear trench segment232, the second linear trench segment234, the third linear trench segment236, and the fourth linear trench segment238may include a dielectric liner218in contact with the semiconductor substrate202, and a trench filler material224on the dielectric liner218. The first linear trench segment232is perpendicular to the second linear trench segment234and the fourth linear trench segment238, and is parallel to, and aligned with, the third linear trench segment236. The second linear trench segment234is perpendicular to the third linear trench segment236, and is parallel to, and aligned with, the fourth linear trench segment238. The third linear trench segment236is perpendicular to the fourth linear trench segment238. The terms “perpendicular” and “parallel” refer to orientations in the plane ofFIG.2A, and similarly for other examples disclosed herein.

The semiconductor device200includes a trench intersection240of the deep trench structure230. The first linear trench segment232, the second linear trench segment234, the third linear trench segment236, and the fourth linear trench segment238each extend to the trench intersection240. The trench intersection240includes a first connector trench segment242of the deep trench structure230in the semiconductor substrate202, connecting the first linear trench segment232to the second linear trench segment234. The trench intersection240also includes a second connector trench segment244of the deep trench structure230in the semiconductor substrate202, connecting the second linear trench segment234to the third linear trench segment236. The trench intersection240of this example includes a third connector trench segment246of the deep trench structure230in the semiconductor substrate202, connecting the third linear trench segment236to the fourth linear trench segment238. The trench intersection240of this example further includes a fourth connector trench segment248of the deep trench structure230in the semiconductor substrate202, connecting the fourth linear trench segment238to the first linear trench segment232. It is noted that a portion of the trench intersection240may form part of both the first and second connector trench segments242and244, both the second and third connector trench segments244and246, both the third and fourth connector trench segments246and248, or both the fourth and first connector trench segments248and242. The first connector trench segment242, the second connector trench segment244, the third connector trench segment246, and the fourth connector trench segment248are formed concurrently with the first linear trench segment232, the second linear trench segment234, the third linear trench segment236, and the fourth linear trench segment238, and include the dielectric liner218and the trench filler material224.

A substrate pillar250is located in the trench intersection240, and is laterally surrounded by the first connector trench segment242, the second connector trench segment244, the third connector trench segment246, and the fourth connector trench segment248. The terms “lateral” and “laterally” refer to directions in the plane ofFIG.2A.

The first linear trench segment232has a first linear segment width252, the second linear trench segment234has a second linear segment width254, the third linear trench segment236has a third linear segment width256, and the fourth linear trench segment238has a fourth linear segment width258. In this example, the first linear segment width252, the second linear segment width254, the third linear segment width256, and the fourth linear segment width258may all be equal, and may be 0.5 microns to 3 microns, by way of example.

The first connector trench segment242has a first connector segment width260, measured across the first connector trench segment242to the substrate pillar250. The first connector segment width260is at least as great as a minimum of the first linear segment width252and the second linear segment width254, and is no greater than a maximum of the first linear segment width252and the second linear segment width254. In this example, in which the first linear segment width252and the second linear segment width254are equal, the first connector segment width260is thus equal to the first linear segment width252and equal to the second linear segment width254.

The second connector trench segment244has a second connector segment width262, measured across the second connector trench segment244to the substrate pillar250. The second connector segment width262is at least as great as a minimum of the second linear segment width254and the third linear segment width256, and is no greater than a maximum of the second linear segment width254and the third linear segment width256. In this example, in which the second linear segment width254and the third linear segment width256are equal, the second connector segment width262is thus equal to the second linear segment width254and equal to the third linear segment width256.

The third connector trench segment246has a third connector segment width264, measured across the third connector trench segment246to the substrate pillar250. The third connector segment width264of this example is at least as great as a minimum of the third linear segment width256and the fourth linear segment width258, and is no greater than a maximum of the third linear segment width256and the fourth linear segment width258. In this example, in which the third linear segment width256and the fourth linear segment width258are equal, the third connector segment width264is thus equal to the third linear segment width256and equal to the fourth linear segment width258.

The fourth connector trench segment248has a fourth connector segment width266, measured across the fourth connector trench segment248to the substrate pillar250. The fourth connector segment width266of this example is at least as great as a minimum of the fourth linear segment width258and the first linear segment width252, and is no greater than a maximum of the fourth linear segment width258and the first linear segment width252. In this example, in which the fourth linear segment width258and the first linear segment width252are equal, the fourth connector segment width266is thus equal to the fourth linear segment width258and is equal to the first linear segment width252.

Having the first connector segment width260, the second connector segment width262, the third connector segment width264, and the fourth connector segment width266with the ranges disclosed herein may advantageously enable consistent formation of the trench filler material224without generating excess stress in the semiconductor substrate202. The method of forming the linear trench segments232,234,236, and238and the connector trench segments242,244,246, and248may remove more of the semiconductor substrate in wider instances of the trench segments232,234,236,238,242,244,246, and248than in narrower instances. Thus, having the connector segment widths260,262,264, and266with the ranges disclosed herein may advantageously provide the connector trench segments242,244,246, and248with depths that are at least as deep as any of the linear trench segments232,234,236, and238. This may be particularly advantageous when the connector trench segments242,244,246, and248are parts of a deep trench isolation structure that connects to a buried layer in the semiconductor substrate202.

The substrate pillar250may have an area equal to 30 percent to 120 percent of a square with a side equal to a minimum of the first linear segment width252, the second linear segment width254, the third linear segment width256, and the fourth linear segment width258. Having the area of the substrate pillar250at least 30 percent of the area of the square may facilitate a photolithographic process used to form an etch mask for the first connector trench segment242, the second connector trench segment244, the third connector trench segment246, and the fourth connector trench segment248, as an area less than 30 percent may be below a resolution limit of the photolithographic process and so fail to provide consistent values for the first connector segment width260, the second connector segment width262, the third connector segment width264, and the fourth connector segment width266. Having the area of the substrate pillar250no more than 120 percent of the area of the square may enable efficient use of area in the semiconductor device200, thus advantageously reducing a fabrication cost of the semiconductor device200compared to a comparable device with a larger substrate pillar.

To attain the area of the substrate pillar250between 30 percent and 120 percent of the area of the square with the side equal to a minimum of the linear segment widths252,254,256, and258, the first connector trench segment242may follow an arced path with a first inner radius268that is 1.4 to 2.0 times the minimum of the first linear segment width252and the second linear segment width254, the second connector trench segment244may follow an arced path with a second inner radius270that is 1.4 to 2.0 times the minimum of the second linear segment width254and the third linear segment width256, the third connector trench segment246may follow an arced path with a third inner radius272that is 1.4 to 2.0 times the minimum of the third linear segment width256and the fourth linear segment width258, and the fourth connector trench segment248may follow an arced path with a fourth inner radius274that is 1.4 to 2.0 times the minimum of the fourth linear segment width258and the first linear segment width252.

Referring toFIG.2B, the second connector trench segment244and the fourth connector trench segment248extend into the semiconductor substrate202, abutting the substrate pillar250. The substrate pillar250is a part of the semiconductor substrate202. The semiconductor substrate202extends continuously under the trench intersection240and up into the substrate pillar250. The substrate pillar250includes semiconductor material of the semiconductor substrate202, which may advantageously reduce process complexity and fabrication cost compared to a similar semiconductor device having a pillar region filled with a separate material. The substrate pillar250extends to bottoms of the connector trench segments242,244,246, and248and connects with the semiconductor material of the semiconductor substrate202under the trench intersection240.

The second connector segment width262and the fourth connector segment width266are the widths of the second connector trench segment244and the fourth connector trench segment248at a top surface276of the semiconductor substrate202. The dielectric liner218and the trench filler material224may extend to the top surface276of the semiconductor substrate202. A trench filler seam226may extend along vertical middle sections of the trench filler material224, for example, as disclosed in reference toFIG.1D.

FIG.3is a top view of another example semiconductor device300with four intersecting linear trench segments. The semiconductor device300includes a semiconductor substrate302. The semiconductor device300of this example includes a deep trench structure330having a first linear trench segment332, a second linear trench segment334, a third linear trench segment336, and a fourth linear trench segment338, all in the semiconductor substrate302. The linear trench segments332,334,336, and338include a trench filler material324. The linear trench segments332,334,336, and338may include a dielectric liner, not shown inFIG.3, between the semiconductor substrate302and the trench filler material324. The first linear trench segment332is perpendicular to the second linear trench segment334and the fourth linear trench segment338, and is parallel to, and aligned with, the third linear trench segment336. The second linear trench segment334is perpendicular to the third linear trench segment336, and is parallel to, and aligned with, the fourth linear trench segment338. The third linear trench segment336is perpendicular to the fourth linear trench segment338.

The first linear trench segment332has a first linear segment width352, the second linear trench segment334has a second linear segment width354, the third linear trench segment336has a third linear segment width356, and the fourth linear trench segment338has a fourth linear segment width358. In this example, the first linear segment width352may be equal to the third linear segment width356, and the second linear segment width354may be equal to the fourth linear segment width358. In this example, the second linear segment width354and the fourth linear segment width358may be greater than the first linear segment width352and the third linear segment width356, as depicted inFIG.3.

The semiconductor device300includes a trench intersection340of the deep trench structure330. The linear trench segments332,334,336, and338each extend to the trench intersection340. The trench intersection340includes a first connector trench segment342of the deep trench structure330in the semiconductor substrate302, connecting the first linear trench segment332to the second linear trench segment334. The trench intersection340also includes a second connector trench segment344of the deep trench structure330in the semiconductor substrate302, connecting the second linear trench segment334to the third linear trench segment336. The trench intersection340of this example includes a third connector trench segment346of the deep trench structure330in the semiconductor substrate302, connecting the third linear trench segment336to the fourth linear trench segment338. The trench intersection340of this example further includes a fourth connector trench segment348of the deep trench structure330in the semiconductor substrate302, connecting the fourth linear trench segment338to the first linear trench segment332. The connector trench segments342,344,346, and348are formed concurrently with the linear trench segments332,334,336, and338. The connector trench segments342,344,346, and348have structures and compositions similar to the linear trench segments332,334,336, and338, that is, the connector trench segments342,344,346, and348include the trench filler material324, and in versions of this example in which the linear trench segments332,334,336, and338include the dielectric liner, the connector trench segments342,344,346, and348also include the dielectric liner. A substrate pillar350is located in the trench intersection340and is laterally surrounded by the connector trench segments342,344,346, and348. The substrate pillar350includes semiconductor material of the semiconductor substrate302. The substrate pillar350extends to bottoms of the connector trench segments342,344,346, and348and connects with the semiconductor material of the semiconductor substrate302under the trench intersection340, similarly to the substrate pillar250ofFIG.2B.

The first connector trench segment342has a first connector segment width360, measured across the first connector trench segment342to the substrate pillar350. The first connector segment width360is at least as great as a minimum of the first linear segment width352and the second linear segment width354, and is no greater than a maximum of the first linear segment width352and the second linear segment width354. Thus, in this example, the first connector segment width360is at least as great as the first linear segment width352and is no greater than the second linear segment width354.

The second connector trench segment344has a second connector segment width362, measured across the second connector trench segment344to the substrate pillar350. The second connector segment width362is at least as great as a minimum of the second linear segment width354and the third linear segment width356, and is no greater than a maximum of the second linear segment width354and the third linear segment width356. Thus, in this example, the second connector segment width362is at least as great as the third linear segment width356and is no greater than the second linear segment width354.

The third connector trench segment346has a third connector segment width364, measured across the third connector trench segment346to the substrate pillar350. The third connector segment width364of this example is at least as great as a minimum of the third linear segment width356and the fourth linear segment width358, and is no greater than a maximum of the third linear segment width356and the fourth linear segment width358. Thus, in this example, the third connector segment width364is at least as great as the third linear segment width356and is no greater than the fourth linear segment width358.

The fourth connector trench segment348has a fourth connector segment width366, measured across the fourth connector trench segment348to the substrate pillar350. The fourth connector segment width366of this example is at least as great as a minimum of the fourth linear segment width358and the first linear segment width352, and is no greater than a maximum of the fourth linear segment width358and the first linear segment width352. Thus, in this example, the fourth connector segment width366is at least as great as the first linear segment width352and is no greater than the fourth linear segment width358.

Having the first connector segment width360, the second connector segment width362, the third connector segment width364, and the fourth connector segment width366with the ranges disclosed herein may accrue the advantages disclosed in reference toFIG.2AandFIG.2B. The substrate pillar350may have an area equal to 30 percent to 120 percent of a square with a side equal to a minimum of the first linear segment width352, the second linear segment width354, the third linear segment width356, and the fourth linear segment width358, further accruing the advantages disclosed in reference toFIG.2AandFIG.2B. It is noted that a portion of the trench intersection340may form part of both the first and second connector trench segments342and344, both the second and third connector trench segments344and346, both the third and fourth connector trench segments346and348, or both the fourth and first connector trench segments348and342.

FIG.4AandFIG.4Bare a top view and a cross section, respectively, of an example semiconductor device400with three intersecting linear trench segments. Referring toFIG.4A, the semiconductor device400includes a semiconductor substrate402, with a deep trench structure430having a first linear trench segment432in the semiconductor substrate402, a second linear trench segment434in the semiconductor substrate402, and a third linear trench segment436in the semiconductor substrate402. The first linear trench segment432, the second linear trench segment434, and the third linear trench segment436may be formed as disclosed in reference toFIG.1AthroughFIG.1E. The first linear trench segment432, the second linear trench segment434, and the third linear trench segment436may include a dielectric liner418in contact with the semiconductor substrate402, and a trench filler material424on the dielectric liner418. The first linear trench segment432is perpendicular to the second linear trench segment434, and is parallel to, and aligned with, the third linear trench segment436. The second linear trench segment434is perpendicular to the first linear trench segment432and the third linear trench segment436. The third linear trench segment436is parallel to, and aligned with, the first linear trench segment432.

The semiconductor device400includes a trench intersection440of the deep trench structure430. The first linear trench segment432, the second linear trench segment434, and the third linear trench segment436each extend to the trench intersection440. The trench intersection440includes a first connector trench segment442of the deep trench structure430in the semiconductor substrate402, connecting the first linear trench segment432to the second linear trench segment434. The trench intersection440also includes a second connector trench segment444of the deep trench structure430in the semiconductor substrate402, connecting the second linear trench segment434to the third linear trench segment436. The trench intersection440of this example includes a third connector trench segment446of the deep trench structure430in the semiconductor substrate402, connecting the third linear trench segment436to the first linear trench segment432. The first connector trench segment442, the second connector trench segment444, and the third connector trench segment446are formed concurrently with the first linear trench segment432, the second linear trench segment434, and the third linear trench segment436, and include the dielectric liner418and the trench filler material424. It is noted that a portion of the trench intersection440may form part of both the first and second connector trench segments442and444, both the second and third connector trench segments444and446, or both the third and first connector trench segments446and442.

The first linear trench segment432has a first linear segment width452, the second linear trench segment434has a second linear segment width454, and the third linear trench segment436has a third linear segment width456. In this example, the first linear segment width452, the second linear segment width454, and the third linear segment width456may all be equal, and may be 0.5 microns to 3 microns, by way of example.

A substrate pillar450is located in the trench intersection440and is laterally surrounded by the first connector trench segment442, the second connector trench segment444, and the third connector trench segment446. The first connector trench segment442has a first connector segment width460, measured across the first connector trench segment442to the substrate pillar450. The first connector segment width460is at least as great as a minimum of the first linear segment width452and the second linear segment width454, and is no greater than a maximum of the first linear segment width452and the second linear segment width454. In this example, in which the first linear segment width452and the second linear segment width454are equal, the first connector segment width460is thus equal to the first linear segment width452and equal to the second linear segment width454.

The second connector trench segment444has a second connector segment width462, measured across the second connector trench segment444to the substrate pillar450. The second connector segment width462is at least as great as a minimum of the second linear segment width454and the third linear segment width456, and is no greater than a maximum of the second linear segment width454and the third linear segment width456. In this example, in which the second linear segment width454and the third linear segment width456are equal, the second connector segment width462is thus equal to the second linear segment width454and equal to the third linear segment width456.

The third connector trench segment446has a third connector segment width464, measured across the third connector trench segment446to the substrate pillar450. The third connector segment width464of this example is at least as great as a minimum of the third linear segment width456and the first linear segment width452, and is no greater than a maximum of the third linear segment width456and the first linear segment width452. In this example, in which the third linear segment width456and the first linear segment width452are equal, the third connector segment width464is thus equal to the third linear segment width456and equal to the first linear segment width452. Having the first connector segment width460, the second connector segment width462, and the third connector segment width464with the ranges disclosed herein may advantageously enable consistent formation of the trench filler material424without generating excess stress in the semiconductor substrate402, and may accrue the advantages disclosed in reference toFIG.2AandFIG.2B.

The substrate pillar450may have an area equal to 30 percent to 120 percent of a square with a side equal to a minimum of the first linear segment width452, the second linear segment width454, and the third linear segment width456. Having the area of the substrate pillar450from 30 percent to 120 percent of the area of the square may accrue the fabrication and area benefits disclosed in reference toFIG.1. To attain the area of the substrate pillar450between 30 percent and 120 percent of the area of the square with the side equal to a minimum of the linear segment widths452,454, and456, the first connector trench segment442may follow an arced path with a first inner radius468that is 2.4 to 3.2 times the minimum of the first linear segment width452and the second linear segment width454. Similarly, the second connector trench segment444may follow an arced path with a second inner radius470that is 2.4 to 3.2 times the minimum of the second linear segment width454. The third connector segment width464may have a straight configuration, as depicted inFIG.4A.

Referring toFIG.4B, the first connector trench segment442and the second connector trench segment444extend into the semiconductor substrate402, abutting the substrate pillar450. The substrate pillar450is a part of the semiconductor substrate402, and extends to bottoms of the connector trench segments442,444, and446, and connects with the semiconductor material of the semiconductor substrate402, which extends continuously under the trench intersection440. The substrate pillar450includes semiconductor material of the semiconductor substrate402, accruing the advantage disclosed in reference toFIG.2B. In this example, the dielectric liner418may be removed at bottoms of the deep trench structure430, and the trench filler material424may contact the semiconductor material of the semiconductor substrate402at the bottoms, as depicted inFIG.4B.

The first connector segment width460and the second connector segment width462are the widths of the first connector trench segment442and the second connector trench segment444at a top surface476of the semiconductor substrate402. The dielectric liner418and the trench filler material424may extend to the top surface476of the semiconductor substrate402. A trench filler seam426may extend along vertical middle sections of the trench filler material424, for example, as disclosed in reference toFIG.1D.

FIG.5is a top view of another example semiconductor device500with three intersecting linear trench segments in a semiconductor substrate502. The semiconductor device500of this example includes a deep trench structure530having a first linear trench segment532, a second linear trench segment534, and a third linear trench segment536, all in the semiconductor substrate502. The linear trench segments532,534, and536include a trench filler material524. The linear trench segments532,534, and536may include a dielectric liner, not shown inFIG.5, between the semiconductor substrate502and the trench filler material524. The first linear trench segment532is perpendicular to the second linear trench segment534, and is parallel to, and aligned with, the third linear trench segment536. The second linear trench segment534is perpendicular to the first linear trench segment532and to the third linear trench segment536. The third linear trench segment536is parallel to, and aligned with, the first linear trench segment532.

The first linear trench segment532has a first linear segment width552, the second linear trench segment534has a second linear segment width554, and the third linear trench segment536has a third linear segment width556. In this example, the first linear segment width552may be equal to the third linear segment width556, and greater than the second linear segment width554, as depicted inFIG.5.

The semiconductor device500includes a trench intersection540of the deep trench structure530. The first linear trench segment532, the second linear trench segment534, and the third linear trench segment536each extend to the trench intersection540. The trench intersection540includes a first connector trench segment542of the deep trench structure530in the semiconductor substrate502, connecting the first linear trench segment532to the second linear trench segment534. The trench intersection540also includes a second connector trench segment544of the deep trench structure530in the semiconductor substrate502, connecting the second linear trench segment534to the third linear trench segment536. The trench intersection540of this example includes a third connector trench segment546of the deep trench structure530in the semiconductor substrate502, connecting the third linear trench segment536to the first linear trench segment532. The connector trench segments542,544, and546are formed concurrently with the linear trench segments532,534, and536. The connector trench segments542,544, and546have structures and compositions similar to the linear trench segments532,534, and536, that is, the connector trench segments542,544, and546include the trench filler material524, and in versions of this example in which the linear trench segments532,534, and536include the dielectric liner, the connector trench segments542,544, and546also include the dielectric liner. A substrate pillar550is located in the trench intersection540and is laterally surrounded by the connector trench segments542,544, and546. The substrate pillar550includes semiconductor material of the semiconductor substrate502, accruing the advantage disclosed in reference toFIG.2B. The substrate pillar550extends to bottoms of the connector trench segments542,544, and546and connects with the semiconductor material of the semiconductor substrate502under the trench intersection540, similarly to the substrate pillar450ofFIG.4B.

The first connector trench segment542has a first connector segment width560, measured across the first connector trench segment542to the substrate pillar550. The first connector segment width560is at least as great as a minimum of the first linear segment width552and the second linear segment width554, and is no greater than a maximum of the first linear segment width552and the second linear segment width554. Thus, in this example, the first connector segment width560is at least as great as the second linear segment width554and is no greater than the first linear segment width552.

The second connector trench segment544has a second connector segment width562, measured across the second connector trench segment544to the substrate pillar550. The second connector segment width562is at least as great as a minimum of the second linear segment width554and the third linear segment width556, and is no greater than a maximum of the second linear segment width554and the third linear segment width556. Thus, in this example, the second connector segment width562is at least as great as the second linear segment width554and is no greater than the third linear segment width556.

The third connector trench segment546has a third connector segment width564, measured across the third connector trench segment546to the substrate pillar550. The third connector segment width564of this example is at least as great as a minimum of the first linear segment width552and the third linear segment width556, and is no greater than a maximum of the first linear segment width552and the third linear segment width556. Thus, in this example, in which the first linear segment width552and the third linear segment width556are equal, the third connector segment width564is equal to the first linear segment width554and equal to the third linear segment width556. It is noted that a portion of the trench intersection540may form part of both the first and second connector trench segments542and544, both the second and third connector trench segments544and546, or both the third and first connector trench segments546and542.

Having the first connector segment width560, the second connector segment width562, and the third connector segment width564with the ranges disclosed herein may accrue the advantages disclosed in reference toFIG.2AandFIG.2B. The substrate pillar550may have an area equal to 30 percent to 120 percent of a square with a side equal to a minimum of the first linear segment width552, the second linear segment width554, and the third linear segment width556, further accruing the advantages disclosed in reference toFIG.2AandFIG.2B.

Various features of the examples disclosed herein may be combined in other manifestations of example microelectronic devices. For example, the deep trench structure230ofFIG.2AandFIG.2Bmay be formed without the dielectric liner218. Similarly, the deep trench structure430ofFIG.4AandFIG.4Bmay be formed without the dielectric liner418. The deep trench structure230ofFIG.2Bmay have openings at bottoms of the connector trench segments244and248, as described in reference toFIG.4B. Similarly, the deep trench structure430ofFIG.4Bmay have a continuous liner418that isolates the trench filler material424from the semiconductor substrate402. Any of the connector trench segments242,244,246, or248ofFIG.2A, any of the connector trench segments342,344,346, or348ofFIG.3, or either of the connector trench segments442, or444ofFIG.4, may have straight portions, as depicted inFIG.5. Similarly, either of the connector trench segments442, or444ofFIG.4, may follow arced paths, as depicted inFIG.4A.

While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.