Patent ID: 12211200

DETAILED DESCRIPTION

Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

It shall be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

The terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limited to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be further understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

FIG.1is a block diagram of a wafer inspection system1in accordance with some embodiments of the present disclosure.

The wafer inspection system1may be used to inspect probe mark(s) on the device under test (DUT) (e.g., semiconductor devices or integrated circuit (IC) devices) at the wafer level. In some embodiments, the wafer inspection system1may be used in combination with a probe apparatus2for testing a device. A device being tested is often called a DUT or a unit under test (UUT).

For example, after being tested by the probe apparatus2, probe mark(s) may be left on the DUT. The DUT and/or the image of the DUT may be transferred to the wafer inspection system1to determine whether the DUT is qualified or unqualified based on the number of the probe mark(s) left on the DUT. For example, if the number of the probe mark(s) left on the DUT is less than or equal to a threshold value, the DUT is determined to be qualified. For example, if the number of the probe mark(s) left on the DUT is greater than a threshold value, the DUT is determined to be unqualified.

Referring toFIG.1, the wafer inspection system1may include a memory unit11, an image-uploading unit12, a processing unit13, an error-monitoring unit14, an auxiliary inspection unit15, a result-distribution unit16, and a communication unit17.

The memory unit11may be configured to store data, such as the image of the DUT and/or records, indexes, or parameters associated with the image. The memory unit11may be configured to receive data from a camera23of the probe apparatus2or from a camera of the wafer inspection system1.

In some embodiments where the probe apparatus2includes the camera23, the image of the DUT may be captured by the camera23and then sent to the memory unit11through the communication unit17. However, in some other embodiments where the wafer inspection system1includes a camera, the images of the DUT may be captured by the camera of the wafer inspection system1and then stored in the memory unit11.

In some embodiments, the memory unit11may include random access memory (RAM), read only memory (ROM), hard drives, as well as removable memory devices, which can include memory sticks, memory cards, flash drives, external hard drives, and so on.

The image (such as the images shown inFIGS.5A,5B,5C,5D,7A,7B, and7C) of the DUT may include one or more probe marks. The image of the DUT may be used to establish a database for training the algorithms or computer-executable instructions, and to establish a model to implement the wafer inspection system and method of the present disclosure. The image of the DUT may be used as a reference for determining whether the DUT is qualified.

The image-uploading unit12may be configured to upload the image of the DUT from the memory unit11to the process unit13. The image-uploading unit12may be configured to upload the image of the DUT to the process unit13to conduct a wafer inspection process of the present disclosure (such as the wafer inspection method40inFIG.4or the wafer inspection method60inFIG.6). In some embodiments, the image-uploading unit12may include algorithms or computer-executable instructions, such as programs, being executed by the processing unit13.

The processing unit13may be configured to receive image of the DUT from the memory unit11. The processing unit13may be configured to conduct a wafer inspection process of the present disclosure. For example, the processing unit13may be configured to determine that the DUT is qualified or unqualified based on the number of the probe mark(s) left on the DUT.

The processing unit13may be configured to analysis the image of the DUT. For example, the processing unit13may be configured to conduct an image recognition process on the image of the DUT. For example, the processing unit13may be configured to calculate the number of the probe mark(s) left on the DUT via artificial intelligence algorithms (e.g., computer vision algorithms).

For example, the processing unit13may be configured to calculate the number of the probe mark(s) left on the DUT by applying non-max suppression algorithms. For example, the processing unit13may be configured to select appropriate bounding frames or boxes for the probe mark(s) and ignore overlapping bounding frames. For example, the processing unit13may be configured to select a single entity out of many overlapping entities.

The processing unit13may be configured to execute algorithms or computer-executable instructions stored in a memory such as the memory unit11or another medium. For example, the processing unit13may be configured to cause a series of operational steps to be performed on the wafer inspection system1or other programmable apparatuses to produce a computer implemented process such that the instructions provide processes for implementing the operations specified in the flow charts (described with respect toFIG.4andFIG.6).

In some embodiments, the processing unit13may include (or may be) a processor (e.g., a central processing unit (CPU), a graphic processing unit (GPU), a micro processing unit (MCU), an application specific integrated circuit (ASIC) or the like) or a controller.

The error-monitoring unit14may be configured to monitor and/or report information such as error codes or malfunction codes. The error-monitoring unit14may be used to check, diagnose, and identify the status of the wafer inspection system1. The error-monitoring unit14may be used to debug the operational steps to improve the performance of the wafer inspection system1. In some embodiments, the error-monitoring unit14may include algorithms or computer-executable instructions, such as programs, being executed by the processing unit13.

The auxiliary inspection unit15may be configured to receive the analyzed image of the DUT (such as the image52inFIG.5Bthat has undergone the wafer inspection process of the processing unit13) from the processing unit13for an auxiliary inspection process.

For example, the auxiliary inspection unit15may be used to conduct a more careful checking to determine the accuracy of the processing unit13and the condition of the analyzed image of the DUT.

For example, if the image of the DUT does not pass the wafer inspection process of the processing unit13(i.e., the processing unit13determines that the number of the probe mark(s) on an image of the DUT is greater than a threshold value and that the DUT is unqualified), the processing unit13may send the analyzed image of the DUT to the auxiliary inspection unit15for an auxiliary inspection process. If the analyzed image of the DUT does not pass the auxiliary inspection process of the auxiliary inspection unit15(i.e., the auxiliary inspection unit15confirms that the number of the probe mark(s) on the image of the DUT is greater than the threshold value and that the DUT is unqualified), the DUT and/or the analyzed image of the DUT may be sent to a failure analysis unit18to investigate the failure and find out the root cause.

On the other hand, if the analyzed image of the DUT passes the auxiliary inspection process of the auxiliary inspection unit15(i.e., the auxiliary inspection unit15confirms that the number of the probe mark(s) on the image of the DUT is less than or equal to the threshold value and that the DUT is qualified), the DUT and/or the analyzed image of the DUT may be sent to a data server19.

If the results of the auxiliary inspection unit15and the processing unit13are different, the wafer inspection process of the processing unit13can be improved by using the results of the auxiliary inspection unit15as feedback. Therefore, the accuracy of the processing unit13can be increased.

In some embodiments, if the image of the DUT passes the wafer inspection process of the processing unit13(i.e., the processing unit13determines that the number of the probe mark(s) on an image of the DUT is less than or equal to a threshold value and that the DUT is qualified), the DUT and/or the analyzed image of the DUT may be sent to the data server19by the processing unit13without undergoing the auxiliary inspection process.

In some other embodiments, if the image of the DUT passes the wafer inspection process of the processing unit13, the processing unit13may still send the analyzed image of the DUT to the auxiliary inspection unit15for an auxiliary inspection process.

In some embodiments, the auxiliary inspection unit15may be conducted or operated manually by a user, an operator, an engineer, and the like. However, in some other embodiments, the auxiliary inspection unit15may be conducted or operated automatically by a machine, an apparatus, an equipment, and the like.

The result-distribution unit16may be configured to distribute the analyzed image of the DUT (from the processing unit13and/or from the auxiliary inspection unit15) to one or more computers, hardware, and/or software components communicated with the wafer inspection system1. The result-distribution unit16may also distribute an analysis report of the DUT. The analysis report of the DUT may include records, indexes, and parameters associated with the analyzed image.

In some embodiments, if the DUT is determined to be unqualified by the processing unit13and/or the auxiliary inspection unit15, the image and/or the analysis report of the unqualified DUT may be sent to the failure analysis unit18through the result-distribution unit16to investigate the failure and find out the root cause. Simultaneously or consequently, the image and/or the analysis report of the unqualified DUT may be sent to the data server19through the result-distribution unit16to establish a database for training the algorithms or computer-executable instructions and to establish a model to implement the wafer inspection system and method of the present disclosure.

The communication unit17may be configured to send/receive data to/from the wafer inspection system1via wired or wireless techniques (e.g., Wi-Fi, cellular networks, Bluetooth, or the like). In some embodiments, the communication unit17may include a wireless communication transceiver. For example, the communication unit17may include a transmitter, a receiver, an antenna, and so on.

Although there are seven units in the wafer inspection system1, the present disclosure is not limited thereto. For example, in some embodiments, there may be any number of units in the wafer inspection system1. In addition, in some embodiments, the wafer inspection system1may also interact with other hardware and/or software components not depicted inFIG.1. For example, the wafer inspection system1may interact with one or more external user interface devices, such as a keyboard, a mouse, a display monitor, a touchscreen, etc.

The present disclosure may be embodied as a system, method, computer program or any combination thereof. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “unit,” “module” or “system.” Furthermore, the present disclosure may take the form of a computer program embodied in any tangible medium of expression having computer usable program code embodied in the medium.

The present disclosure may be described in the general context of algorithms or computer-executable instructions, such as programs, being executed by a computer. Generally, programs include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. The present disclosure may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, programs may be located in both local and remote computer storage media including memory storage devices.

FIG.2is a schematic view of the probe apparatus2according to some embodiments of the present disclosure.

In some embodiments, the probe apparatus2may include a tester21, a probe card22, and a camera23. A DUT31of a wafer3may be disposed under the probe apparatus2.

The tester21may provide an electrical signal to test the DUT31. The electrical signal may be transfer to the DUT31by contacting one or more pads (or testing pads)31pon the DUT31with one or more pins (or probe pins)22pof the probe card22. The camera23may capture an image of the DUT31after the pads31phave been contacted by the pins22p.

In some embodiments, the camera23may include one or more lenses (such as objective lens, zoom lens, relay lens, imaging lens, condensing lens, etc.), one or more light sources (such as a low-power light source, an external light source, a near-infrared light source, etc.), a charge-coupled device (CCD), a complementary metal-oxide semiconductor (CMOS) imaging sensor, one or more signal converters (such as an analog-to-digital (A/D) converter). In some embodiments, the camera23may be omitted. For example, in some other embodiments where the wafer inspection system1includes a camera, images of the DUT may be captured by the camera of the wafer inspection system1and directly stored in the memory unit11.

The DUT31may be a die that has completed front-end fabrication. Although one DUT31is shown inFIG.2, the wafer3may include a plurality of DUTs31. Each of the DUTs31may include a plurality of pads (such as the pads31p).

In some embodiments of the present disclosure, in addition to the wafer3, another kind of DUT may be disposed under the probe apparatus2to undergo a process for testing electrical characteristics. The examples of DUT are a semiconductor package, a semiconductor substrate, a circuit, a memory cell (such as a dynamic random access memory cell (DRAM cell)), etc. The system and method of the present disclosure can be applied for any DUT in order to inspect the probe marks after the process through the probe apparatus2.

FIG.3is a schematic view of a plurality of probe mark inspection sites on the wafer3according to some embodiments of the present disclosure.

Probe mark inspections may be performed by the probe apparatus2(shown inFIG.2) on the wafer3at a substantially center region3a, a substantially left region3b, a substantially right region3c, a substantially top region3d, and a substantially bottom region3eof the wafer3to ensure proper quality inspection.

Moreover, alignment pins may be set by the probe apparatus2substantially in the regions P1, P2, P3, and P4of the wafer3. It should be noted that the configuration shown inFIG.3of the probe mark inspections performed by the probe apparatus2(shown inFIG.2) on the wafer3may be adjusted for 12-inch, 8-inch, 6-inch, or even smaller wafer applications.

FIG.4illustrates a flow chart of a wafer inspection method4in accordance with some embodiments of the present disclosure. The wafer inspection method4can be conducted by the processing unit13.

The step or operation S41is identifying a plurality of candidate regions on an image of a DUT. For example, as shown inFIG.5A, candidate regions a, b, c, d, e, and f are identified on an image51of a DUT. In some embodiments, the step S41may include framing the candidate regions with bounding frames or boxes.

The step S42is generating a confidence score for each of the plurality of candidate regions. The confidence score may represent or indicate a probability of a candidate region including a probe mark. The confidence score may be a number between 0.0 and 1.0. A score of 1.0 means the probability is high and the image is likely to include a probe mark A score of 0.0 means the probability is low and the image is likely to not include a probe mark.

In some embodiments, the step S42may include comparing each of the plurality of candidate regions on the image with training images used to train the processing unit13. For example, the step S42may include comparing each of the plurality of candidate regions on the image with training images used to train the algorithms or computer-executable instructions and to establish a model to implement the wafer inspection system and method of the present disclosure. A score of 1.0 means the image is likely to match or correspond to a training image. A score of 0.0 means the image is likely to not match or correspond to a training image.

The step S43is selecting a candidate region having the highest confidence score as a selected region. For example, as shown inFIG.5A, if the candidate region a is more likely to include a probe mark (or is more likely to match or correspond to a training image) than the other candidate regions b, c, d, e, f, the candidate region a is selected as a selected region (such as the selected region a′ on the image52of the DUT inFIG.5B).

The step S44is determining whether another candidate region in the plurality of candidate regions includes the same probe mark as the selected region.

For example, if the candidate region a inFIG.5Ais selected as the selected region a′ inFIG.5B, the candidate regions b, c, d, e, and f may each be assessed or evaluated to check if the same probe mark as the candidate region a is framed.

For example, the candidate region f includes the same probe mark as the candidate region a. The wafer inspection method4proceeds to the step S45, eliminating the candidate region f. The candidate region f is not selected as a selected region inFIG.5B.

For example, the candidate region b does not include the same probe mark as the candidate region a. The candidate region b is not eliminated and may be selected as a selected region inFIG.5Bin the following steps.

In some embodiments, the step S44includes calculating an Intersection over Union (IoU) between the candidate region a and one of the candidate regions b, c, d, e, and f In some embodiments, the step S44includes calculating a degree of similarity between the candidate region a and one of the candidate regions b, c, d, e, and f.

In some embodiments, the step S44includes setting the confidence score of one of the candidate regions b, c, d, e, and f to zero if the IoU (or the degree of similarity) therebetween is higher than a threshold value.

The wafer inspection method4proceeds to the step S46, repeating the step S43, the step S44, and the step S45until all of the plurality of candidate regions on the image are selected or eliminated.

For example, after the candidate region a is selected, the candidate region b becomes the candidate region having the highest confidence score. Then, the candidate region b is selected as a selected region (such as the selected region b′ on the image52of the DUT inFIG.5B). The candidate regions c, d, and e may each be assessed or evaluated to check if the same probe mark as the candidate region b is framed.

For example, after all of the plurality of candidate regions on the image are selected or eliminated, there are selected regions a′, b′, c′, d′, and e′ on the image52of the DUT inFIG.5B.

The step S47is calculating a number of selected regions on the image. For example, there are five selected regions on the image52of the DUT inFIG.5Band there are six selected regions on the image53of the DUT inFIG.5C.

The step S48is determining whether the DUT on the wafer is qualified based on the number of selected regions on the image. For example, assuming that the threshold value is five, the DUT inFIG.5Bis qualified and the DUT inFIG.5Cis unqualified.

The image52of the DUT inFIG.5Bis sent to a data server (such as the data server19inFIG.1) in the step S50.

The image53of the DUT inFIG.5Cis sent to an auxiliary inspection unit (such as the auxiliary inspection unit15inFIG.1) in the step S49. After the auxiliary inspection process, the image53of the DUT inFIG.5Cis sent to a data server.

In some embodiments, the wafer inspection method4further includes the step S51, determining whether the plurality of candidate regions on the image includes a punching-through probe mark.

For example, as shown inFIG.5D, a candidate region g on the image54of the DUT includes a punching-through probe mark. The punching-through probe mark includes a deeper profile than the others.

If a punching-through probe mark is detected, the DUT is determined as unqualified and is sent to an auxiliary inspection unit (such as the auxiliary inspection unit15inFIG.1) in the step S49.

If no punching-through probe mark is detected, the wafer inspection method4proceeds to the step S42.

In some embodiments, the step S51is performed before the step S48. For example, the image52of the DUT inFIG.5Bis unqualified if having a punching-through probe mark, regardless of the number of probe marks.

According to some embodiments of the present disclosure, by selecting the candidate regions having high confidence scores (such as the step43) and eliminating the other overlapping candidate regions (such as the step44and the step45), accuracy for identifying probe mark(s) on the image of the DUT on the wafer can be improved. In addition, since the probe mark(s) can be identified by artificial intelligence algorithms, time loss and human error can be avoided or minimized.

FIG.6illustrates a flow chart of a wafer inspection method6in accordance with some embodiments of the present disclosure. The wafer inspection method6can be conducted by the processing unit13.

The step or operation S61is identifying a plurality of candidate regions on an image of a DUT. For example, as shown inFIG.7A, candidate regions a, b, c, d, e, and f are identified on an image71of a DUT. The candidate regions a, b, c, d, e, and f may each include a probe mark In some embodiments, the step S61may include framing the candidate regions with bounding frames or boxes.

The step S62is comparing two candidate regions.

The step S63is generating a degree of similarity between the two candidate regions. In some embodiments, the step S63includes calculating an IoU between the two candidate regions.

The step S64is determining whether the degree of similarity (or the IoU) is greater than a threshold value. If the degree of similarity (or the IoU) is greater than a threshold value, the wafer inspection method6proceeds to the step S65, eliminating one of the two candidate regions.

For example, as shown inFIG.7B, if the degree of similarity (or the IoU) between the candidate regions b and f is greater than a threshold value k, then one of the candidate regions b and f is eliminated.

If not, the wafer inspection method6proceeds to the step S66, repeating S62, S63, S64, and S65until the degree of similarity (or the IoU) between any two candidate regions left on the image is less than or equal to the threshold value.

For example, as shown inFIG.7B, if the degree of similarity (or the IoU) between the candidate regions a and e is less than or equal to the threshold value k, both of the candidate regions a and e are left on the image. In another round, the candidate regions a and e will be compared with another candidate region.

For example, after repeating S62, S63, S64, and S65, there are candidate regions a, b, c, d, and e on the image72of the DUT inFIG.7C.

The step S67is calculating a number of the candidate regions left on the image. For example, there are five candidate regions left on the image72of the DUT inFIG.7C.

The step S68is determining whether the DUT on the wafer is qualified based on the number of candidate regions left on the image. For example, assuming that the threshold value is five, the DUT inFIG.7Cis qualified (the candidate region f is eliminated).

If the DUT is determined to be qualified, the wafer inspection method6proceeds to the step S70, sending the result to a data server (such as the data server19inFIG.1).

If the DUT is determined to be unqualified, the wafer inspection method6proceeds to the step S69, sending the result to an auxiliary inspection unit (such as the auxiliary inspection unit15inFIG.1).

In some embodiments, the wafer inspection method6further includes the step S71, determining whether the plurality of candidate regions on the image includes a punching-through probe mark. The step S71is similar to the step S51inFIG.4. In some embodiments, the step S71is performed before the step S68.

Any reference in the specification to a method should be applied mutatis mutandis to a system capable of executing the method. Any reference in the specification to a system should be applied mutatis mutandis to a method that may be executed by the system.

FIG.8is a block diagram of the processing unit13of the wafer inspection system1in accordance with some embodiments of the present disclosure.

The processing unit13may include a processor130, a network interface (I/F)131, an input/output (I/O) device132, a storage133, and a memory134communicatively coupled via a bus137or another interconnection communication mechanism.

In some embodiments, one or more operations or functionalities of the wafer inspection system1are realized by the processor130, which is programmed for performing such operations and functionalities. One or more of the I/F131, the I/O device132, the storage133, and the memory134are operable to receive instructions, data, design rules, netlists, layouts, models and other parameters for processing by the processor130.

The I/F131may be coupled to the bus137to connect the processor130to the Internet.

The I/O device132may include an input device, an output device, or a combined input/output device for enabling user interaction with the wafer inspection system1. An input device comprises, for example, a keyboard, keypad, mouse, trackball, trackpad, or cursor direction keys for communicating information and commands to the processor130. An output device includes, for example, a display, a printer, a voice synthesizer, etc., for communicating information to a user.

The storage device133, such as a magnetic disk or optical disk, may be coupled to the bus136for storing data or instructions.

The memory134may include RAM, ROM, hard drives, as well as removable memory devices, which can include memory sticks, memory cards, flash drives, external hard drives, and so on. The memory134may include a user space135and a kernel136. The memory134may be coupled to the bus137for storing data or instructions to be executed by the processor130. The memory134may be also used, in some embodiments, for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor130.

FIG.9illustrates schematic views of pads and probe marks according to some embodiments of the present disclosure.

The pads90,91and92may each include a dimension D1in an x-axis and a dimension D2in a y-axis. The dimension D1may be greater than the dimension D2, such as the pad90. The dimension D2may be greater than the dimension D1, such as the pad91. The dimension D1may be substantially equal to the dimension D2, such as the pad92.

The probe marks93and94may each include an ellipse or is oval in shape. The major axis (or the longest dimension) may be substantially parallel to the x-axis, such as the probe mark93. The major axis (or the longest dimension) may be substantially parallel to the y-axis, such as the probe mark94.

In some embodiments, the pads and probe marks of different orientations or dimensions may affect the occupied areas of the probe marks on the pads. In some embodiments, the occupied areas of the probe marks on the pads may be a criteria for determining whether the DUT on the wafer is qualified. For example, the step S68ofFIG.6may include determining whether the DUT on the wafer is qualified based on the occupied areas of the candidate regions left on the image.

In some embodiments, the pads and probe marks of different orientations or dimensions may be used to establish a database for training the algorithms or computer-executable instructions, and to establish a model to implement the wafer inspection system and method of the present disclosure.

FIG.10illustrates schematic views of analyzed images of probe marks according to some embodiments of the present disclosure.

InFIG.10(a), the probe marks93are not overlapped and the corresponding bounding frames or boxes are not overlapped.

InFIG.10(b), the probe marks93are overlapped and arranged in one direction. The corresponding bounding frames or boxes are overlapped.

InFIG.10(c), the probe marks93are overlapped and arranged in one direction. The corresponding bounding frames or boxes are not overlapped.

InFIG.10(d), the probe marks93are overlapped and randomly arranged. The corresponding bounding frames or boxes are overlapped.

InFIG.10(e), the probe marks93are overlapped and randomly arranged. The corresponding bounding frames or boxes are not overlapped.

InFIG.10(f), the probe marks93are overlapped and randomly arranged. The corresponding bounding frames or boxes are not overlapped and maximize the framed areas of the probe marks93.

InFIG.10(g), the probe marks93are overlapped and arranged along an oblique direction or disposed at an oblique angle. The corresponding bounding frames or boxes are overlapped.

InFIG.10(h), the probe marks93are overlapped and arranged along an oblique direction or disposed at an oblique angle. The corresponding bounding frames or boxes are not overlapped.

InFIG.10(i), the probe marks93are overlapped and arranged along an oblique direction or disposed at an oblique angle. The corresponding bounding frames or boxes are not overlapped and maximize the framed areas of the probe marks93.

InFIG.10(j), the probe marks93are overlapped and randomly arranged. The corresponding bounding frames or boxes are overlapped.

InFIG.10(k), the probe marks93are overlapped and randomly arranged. The corresponding bounding frames or boxes are not overlapped.

In some embodiments, the probe marks and bounding frames having different relative positions, different dimensions and different overlapping areas may be used to establish a database for training the algorithms or computer-executable instructions, and to establish a model to implement the wafer inspection system and method of the present disclosure.

One aspect of the present disclosure provides a wafer inspection system. The wafer inspection system includes a memory unit configured to store an image of a device under test (DUT) on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to: identify a plurality of candidate regions on the image; generate a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; select a first candidate region having the highest confidence score as a selected region; determine whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminate the second candidate region if the second candidate region includes the same probe mark as the first candidate region.

Another aspect of the present disclosure provides a wafer inspection system. The wafer inspection system includes a memory unit configured to store an image of a DUT on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to: identify a plurality of candidate regions on the image, wherein each of the plurality of candidate regions includes a probe mark; compare a first candidate region and a second candidate region of the candidate regions on the image; generate a degree of similarity between the first candidate region and the second candidate region of the candidate regions on the image; determine whether the degree of similarity is greater than a threshold value; and eliminate one of the first candidate region and the second candidate region if the degree of similarity is greater than the threshold value.

Another aspect of the present disclosure provides a wafer inspection method. The wafer inspection method includes identifying a plurality of candidate regions on an image of a DUT on a wafer; generating a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; selecting a first candidate region having the highest confidence score as a selected region; determining whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminating the second candidate region if the second candidate region includes the same probe mark as the first candidate region.

By selecting the candidate regions having high confidence scores and eliminating the other overlapping candidate regions, accuracy for identifying probe mark(s) on the image of the DUT on the wafer can be improved. In addition, since the probe mark(s) can be identified by artificial intelligence algorithms, time loss and human error can be avoided or minimized.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.