Patent ID: 12243786

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

According to various embodiments, hybrid fins are formed adjacent and between semiconductor fins. The hybrid fins include seams that are filled by a silicon precursor soaking process and an oxidation process. These processes simultaneously form the interfacial layer(s) under the replacement gate structures such that extra processing is not needed to fill the seams of the hybrid fins. Filling the seams of the hybrid fins prevents conductive material from subsequently formed source/drain and/or gate contacts to form in the seams. Preventing the conductive material from source/drain and/or gate contacts to form in the seams prevents the source/drains and gates from shorting to each other through the seams. Manufacturing yield of the devices may thus be improved.

FIG.1illustrates an example of Fin Field-Effect Transistors (FinFETs), in accordance with some embodiments.FIG.1is a three-dimensional view, where some features of the FinFETs are omitted for illustration clarity. The FinFETs include semiconductor fins54extending from a substrate50(e.g., a semiconductor substrate), with the semiconductor fins54acting as channel regions58for the FinFETs. Isolation regions68, such as shallow trench isolation (STI) regions, are disposed between adjacent semiconductor fins54, which may protrude above and from between adjacent isolation regions68. Although the isolation regions68are described/illustrated as being separate from the substrate50, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although the bottom portions of the semiconductor fins54are illustrated as being single, continuous materials with the substrate50, the bottom portions of the semiconductor fins54and/or the substrate50may include a single material or a plurality of materials. In this context, the semiconductor fins54refer to the portion extending from between the adjacent isolation regions68.

Gate dielectrics112are along sidewalls and over top surfaces of the semiconductor fins54. Gate electrodes114are over the gate dielectrics112. Epitaxial source/drain regions98are disposed in opposite sides of the semiconductor fins54with respect to the gate dielectrics112and gate electrodes114. The epitaxial source/drain regions98may be shared between various semiconductor fins54. For example, adjacent epitaxial source/drain regions98may be electrically connected, such as through coalescing the epitaxial source/drain regions98by epitaxial growth, or through coupling the epitaxial source/drain regions98with a same source/drain contact.

FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode114. Cross-section B-B′ is perpendicular to cross-section A-A′ and is along a longitudinal axis of a semiconductor fin54and in a direction of, for example, a current flow between the epitaxial source/drain regions98of a FinFET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions98of the FinFETs. Subsequent figures refer to these reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs.

FIGS.2-19are views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.2,3,4,5,6,7,8,9A,10A,11A,12A,13A,14A,15A,16A,17A,18A, and19are cross-sectional views illustrated along a similar cross-section as reference cross-section A-A′ inFIG.1.FIGS.9B,10B,11B,12B,13B,14B,15B,16B,17B, and18Bare cross-sectional views illustrated along a similar cross-section as reference cross-section B-B′ inFIG.1.FIGS.9C,10C,11C,12C,13C,14C,15C,16C,17C, and18Care cross-sectional views illustrated along a similar cross-section as reference cross-section C-C′ inFIG.1.

InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type impurity) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; combinations thereof; or the like.

The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs, and the p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region50N may be physically separated (not separately illustrated) from the p-type region50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P. Although one n-type region50N and one p-type region50P are illustrated, any number of n-type regions50N and p-type regions50P may be provided.

InFIG.3, fin structures52are formed in the substrate50. The fin structures52include semiconductor fins54, which are semiconductor strips. The fin structures52may be formed in the substrate50by etching trenches56in the substrate50. The etching may be any acceptable etching process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching process may be anisotropic.

The fin structures52may be patterned by any suitable method. For example, the fin structures52may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used as masks60to pattern the fin structures52. In some embodiments, the masks60(or other layer) may remain on the fin structures52.

In the illustrated embodiment, the fin structures52each have two semiconductor fins54. However, the fin structures52may each have any quantity of the semiconductor fins54, such as one, two, three, or more semiconductor fins54. Further, different fin structures52may have different quantities of semiconductor fins54. For example, fin structures52in a first region of a die (e.g., a core logic region) may have a first quantity of semiconductor fins54, and fin structures52in a second region of the die (e.g., an input/output region) may have a second quantity of semiconductor fins54, with the second quantity being different from the first quantity.

The trenches56may have different widths. In some embodiments, a first subset of the trenches56A have a smaller width than a second subset of the trenches56B. The trenches56A separate the semiconductor fins54of respective fin structures52, and the trenches56B separate the fin structures52from each other. The semiconductor fins54of respective fin structures52are spaced apart by a lesser distance than the fin structures52are spaced apart from each other. In some embodiments, the semiconductor fins54of respective fin structures52are spaced apart by a distance D1in the range of 5 nm to 100 nm, the fin structures52are spaced apart from each other by a distance D2in the range of 20 nm to 200 nm, and the distance D2is greater than the distance D1. The trenches56may be formed with different widths by patterning the masks60with a pattern having features spaced apart by different distances that correspond to the different widths of the trenches56. The widths of the trenches56defines the width of the semiconductor fins54(also referred to as the critical dimension of the semiconductor fins54). In some embodiments, the semiconductor fins54have a critical dimension in the range of 5 nm to 30 nm.

In some embodiments, the trenches56have different depths. For example, the trenches56A may have a smaller depth than the trenches56B. The trenches56may be formed with different depths as a result of pattern loading effects during etching of the trenches56, with the pattern loading effects caused by the pattern of the masks60having features spaced apart by different distances. The depths of the trenches56defines the height of the semiconductor fins54. In some embodiments, the semiconductor fins54have a height in the range of 10 nm to 100 nm.

InFIG.4, one or more layer(s) of insulation material62for isolation regions are formed over the substrate50and between adjacent semiconductor fins54. The insulation material62may include an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, and may be formed by chemical vapor deposition (CVD), a high-density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD), atomic layer deposition (ALD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material62includes a liner62A on surfaces of the substrate50and the semiconductor fins54, and a fill material62B on the liner62A. The liner62A may be amorphous silicon, silicon oxide, silicon nitride, or the like conformally deposited with a conformal deposition process such as ALD, and the fill material62B may be silicon oxide grown with a conformal growth process such as FCVD. In another embodiment, a single layer of insulation material62is formed. An anneal process may be performed once the insulation material is formed. The anneal process may be performed in an environment containing H2or O2. The liner62A can be oxidized by the anneal process so that after annealing, the liner62A is a similar material as the fill material62B. In an embodiment, the insulation material62is formed such that excess insulation material62covers the semiconductor fins54.

The thickness of the insulation material62is controlled so that the insulation material62does not fill all of the trenches56. In some embodiments, the insulation material62is deposited to a thickness T1in the range of 5 nm to 30 nm. The distances D1, D2(seeFIG.3) and the thickness T1are controlled so that the insulation material62fills the trenches56A without filling the trenches56B. For example, the dispensed volume of the insulation material62may be sufficient to completely fill (or overfill) the trenches56A, but may be insufficient to completely fill the trenches56B. The insulation material62in the trenches56B thus does not completely fill the trenches56B, but instead conformally lines the surfaces of the substrate50and the sidewalls of the semiconductor fins54that define the trenches56B.

In the illustrated embodiment, the sidewalls of the semiconductor fins54and the insulation material62are illustrated as forming right angles with the top surfaces of the substrate50and the insulation material62, respectively. In other embodiments contouring may occur during the patterning of the semiconductor fins54and the deposition of the insulation material62. Accordingly, rounded surfaces may connect the sidewalls of the semiconductor fins54to the top surfaces of the substrate50, and rounded surfaces may connect the sidewalls of the insulation material62to the top surfaces of the insulation material62.

InFIG.5, one or more dielectric layer(s)64are formed on the insulation material62. The dielectric layer(s)64fill (and may overfill) the remaining portions of the trenches56B that are not filled (e.g., are unoccupied) by the insulation material62. In some embodiments, the dielectric layer(s)64merge in the trenches56B and form seams or voids64A in the trenches56B. The seams64A may have a width W1in a range from 1 to 3 nm. The dielectric layer(s)64may be formed of one or more dielectric material(s). Acceptable dielectric materials include nitrides (e.g., silicon nitride), oxides (e.g., tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, etc.), carbides (e.g., silicon carbonitride, silicon oxycarbonitride, etc.), combinations thereof, or the like, which may be deposited by ALD, CVD, or the like. Other insulation materials formed by any acceptable process may be used. Further, the dielectric layer(s)64may be formed of a low-k dielectric material (e.g., a dielectric material having a k-value less than about 3.5), a high-k dielectric material (e.g., a dielectric material having a k-value greater than about 7.0), or multi-layers thereof. The dielectric layer(s)64are formed of material(s) that have a high etching selectivity from the etching of the insulation material62. In some embodiments, the dielectric layer(s)64include silicon nitride formed by ALD.

InFIG.6, a removal process is applied to the dielectric layer(s)64and the insulation material62to remove excess portions of the dielectric layer(s)64and the insulation material62over the semiconductor fins54(e.g., outside of the trenches56), thereby forming hybrid fins66including seams or voids66A on the insulation material62. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The dielectric layer(s)64, after the removal process, have portions left in the trenches56B (thus forming the hybrid fins66). After the planarization process, the top surfaces of the hybrid fins66, the insulation material62, and the semiconductor fins54are coplanar (within process variations) such that they are level with each other. The hybrid fins66are disposed between and are adjacent to the fin structures52. In some embodiments, after the planarization process, the seams66A of the hybrid fins66have a depth D4in the range of 60 nm to 70 nm. The hybrid fins66may also be referred to as “dielectric fins.”

InFIG.7, the insulation material62is recessed to form STI regions68. The insulation material62is recessed such that upper portions of the semiconductor fins54and the hybrid fins66protrude above and from between neighboring STI regions68. Further, the top surfaces of the STI regions68may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions68may be formed flat, convex, and/or concave by an appropriate etch. The STI regions68may be recessed using an acceptable etching process, such as one that is selective to the material(s) of the insulation material62. As will be subsequently described in greater detail, the etching process selectively etches the material(s) of the insulation material62at a faster rate than the materials of the semiconductor fins54and the hybrid fins66. The semiconductor fins54and the hybrid fins66may thus be protected from damage during formation of the STI regions68. Timed etch processes may be used to stop the etching of the insulation material62after the STI regions68reach a desired height. In some embodiments, the STI regions68have a height in the range of 10 nm to 100 nm. The STI regions68include the remaining portions of the insulation material62in the trenches56.

As previously noted, the trenches56B are deeper than the trenches56A. As a result, the STI regions68have different heights. Specifically, a first subset of the STI regions68A have a lesser height than a second subset of the STI regions68B. The STI regions68A are in the trenches56A and between and among the semiconductor fins54of respective fin structures52, and may be referred to as “inner STI regions.” The STI regions68B are in the trenches56B and between adjacent fin structures52and around the hybrid fins66(e.g., between the semiconductor fins54and the hybrid fins66), and may be referred to as “outer STI regions.” Because the trenches56B are deeper than the trenches56A, the bottom surfaces of the STI regions68B are disposed further from the top surfaces of the semiconductor fins54and the hybrid fins66than the bottom surfaces of the STI regions68A. In some embodiments, the bottom surfaces of the STI regions68B are disposed further from the top surfaces of the semiconductor fins54and the hybrid fins66than the bottom surfaces of the STI regions68A by the distance D3(previously described).

Forming the STI regions68reforms portions of the trenches56A,56B. The reformed portions of the trenches56A are between respective pairs of the semiconductor fins54, and the reformed portions of the trenches56B are between respective pairs of a semiconductor fin54and a hybrid fin66. The distances D1, D2(seeFIG.3) and the thickness T1(seeFIG.4) are controlled so that the reformed portions of the trenches56A are wider than the reformed portions of the trenches56B. In some embodiments, the reformed portions of the trenches56A have a width W1in the range of 10 nm to 30 nm, the reformed portions of the trenches56B have a width W2in the range of 5 nm to 20 nm, and the width W1is greater than the width W2.

The insulation material62may be recessed by different amounts as a result of pattern loading effects during recessing of the insulation material62, with the pattern loading effects caused by the reformed portions of the trenches56A,56B having different widths. In some embodiments, the etching of the insulation material62is performed with etching parameters (e.g., temperature, pressure, and duration) that exacerbate the pattern loading effects. As a result of the pattern loading effects, the portions of the insulation material62in the trenches56A are recessed more (e.g., by a greater depth) than the portions of the insulation material62in the trenches56B. Thus, the top surfaces of the STI regions68B are disposed further from the substrate50than the top surfaces of the STI regions68A. In other words, the STI regions68B extend above the STI regions68A, with respect to the substrate50. In some embodiments, the top surfaces of the STI regions68B are disposed further from the substrate50than the top surfaces of the STI regions68A by a distance D5in the range of 2 nm to 10 nm.

In some embodiments where the insulation material62includes silicon oxide, the insulation material62is recessed by a dry etch using hydrofluoric (HF) acid and ammonia (NH3). Each STI region68B extends along three sides (e.g., the sidewalls and the bottom surface) of a hybrid fin66. Specifically, a first portion of an STI region68B is between a hybrid fin66and a first fin structure52, a second portion of the STI region68B is between the hybrid fin66and a second fin structure52, and a third portion of the STI region68B is beneath the hybrid fin66.

The process described forFIGS.2-7is just one example of how the semiconductor fins54, the hybrid fins66, and the STI regions68may be formed. In some embodiments, the semiconductor fins54and/or the hybrid fins66may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Epitaxial structures can be epitaxially grown in some of the trenches, insulating structures can be deposited in others of the trenches, and the dielectric layer can be recessed (in a similar manner as described forFIG.7) such that the epitaxial structures protrude from the dielectric layer to form the semiconductor fins54and the insulating structures protrude from the dielectric layer to form the hybrid fins66. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together.

Further, it may be advantageous to epitaxially grow a material in n-type region50N different from the material in p-type region50P. In various embodiments, upper portions of the semiconductor fins54may be formed of silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

Further, appropriate wells (not separately illustrated) may be formed in the semiconductor fins54and/or the substrate50. The wells may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region50N and the p-type region50P. In some embodiments, a p-type well is formed in the n-type region50N, and an n-type well is formed in the p-type region50P. In some embodiments, a p-type well or an n-type well is formed in both the n-type region50N and the p-type region50P.

In embodiments with different well types, different implant steps for the n-type region50N and the p-type region50P may be achieved using a mask (not separately illustrated) such as a photoresist. For example, a photoresist may be formed over the semiconductor fins54, the hybrid fins66, and the STI regions68in the n-type region50N. The photoresist is patterned to expose the p-type region50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in the range of 1013cm−3to 1014cm−3. After the implant, the photoresist is removed, such as by any acceptable ashing process.

Following or prior to the implanting of the p-type region50P, a mask (not separately illustrated) such as a photoresist is formed over the semiconductor fins54, the hybrid fins66, and the STI regions68in the p-type region50P. The photoresist is patterned to expose the n-type region50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in the range of 1013cm−3to 1014cm−3. After the implant, the photoresist is removed, such as by any acceptable ashing process.

After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments where epitaxial structures are epitaxially grown for the semiconductor fins54, the grown materials may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

InFIG.8, a dummy dielectric layer72is formed on the semiconductor fins54, the hybrid fins66, and within the seams66A of the hybrid fins66. The dummy dielectric layer72may be formed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, which may be deposited or thermally grown according to acceptable techniques such as ALD, in-situ steam growth (ISSG), rapid thermal oxidation (RTO), or the like. The dummy dielectric layer72may fill or substantially fill the seams66A of the hybrid fins66. The dummy dielectric layer72may also include or be referred to as an interfacial layer or interfacial oxide layer. In some embodiments, the dummy dielectric layer72has a thickness in the range of 1 nm to 10 nm. A dummy gate layer74is formed over the dummy dielectric layer72, and a mask layer76is formed over the dummy gate layer74. The dummy gate layer74may be deposited over the dummy dielectric layer72and then planarized, such as by a CMP. The dummy gate layer74may be formed of a conductive or non-conductive material, such as amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), a metal, a metallic nitride, a metallic silicide, a metallic oxide, or the like, which may be deposited by physical vapor deposition (PVD), CVD, or the like. The dummy gate layer74may be formed of material(s) that have a high etching selectivity from the etching of insulation materials, e.g., the STI regions68and/or the dummy dielectric layer72. The mask layer76may be deposited over the dummy gate layer74. The mask layer76may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer74and a single mask layer76are formed across the n-type region50N and the p-type region50P. In the illustrated embodiment, the dummy dielectric layer72covers the semiconductor fins54, the hybrid fins66, and the STI regions68, such that the dummy dielectric layer72extends over the STI regions68and between the dummy gate layer74and the STI regions68. In another embodiment, the dummy dielectric layer72covers only the semiconductor fins54.

FIGS.9A-18Cillustrate various additional steps in the manufacturing of embodiment devices.FIGS.9A-18Cillustrate features in either of the n-type region50N and the p-type region50P. For example, the structures illustrated may be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are explained in the description accompanying each figure.

InFIG.9A-9C, the mask layer76is patterned using acceptable photolithography and etching techniques to form masks86. The pattern of the masks86is then transferred to the dummy gate layer74by any acceptable etching technique to form dummy gates84. The pattern of the masks86may optionally be further transferred to the dummy dielectric layer72by any acceptable etching technique to form dummy dielectrics82. The dummy gates84cover respective channel regions58of the semiconductor fins54. The pattern of the masks86may be used to physically separate adjacent dummy gates84. The dummy gates84may have lengthwise directions substantially perpendicular (within process variations) to the lengthwise directions of the semiconductor fins54. The masks86may be removed during the patterning of the dummy gate84, or may be removed during subsequent processing.

Gate spacers92are formed over the semiconductor fins54, on exposed sidewalls of the masks86(if present), the dummy gates84, and the dummy dielectrics82. The gate spacers92may be formed by conformally depositing one or more dielectric material(s) and subsequently etching the dielectric material(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like. Other insulation materials formed by any acceptable process may be used. Any acceptable etch process, such as a dry etch, a wet etch, the like, or a combination thereof, may be performed to pattern the dielectric material(s). The etching may be anisotropic. The dielectric material(s), when etched, have portions left on the sidewalls of the dummy gates84(thus forming the gate spacers92). In some embodiments the etch used to form the gate spacers92is adjusted so that the dielectric material(s), when etched, also have portions left on the sidewalls of the semiconductor fins54(thus forming fin spacers94). After etching, the fin spacers94(if present) and the gate spacers92can have straight sidewalls (as illustrated) or can have curved sidewalls (not separately illustrated).

The fin spacers94include inner fin spacers94N (disposed between the semiconductor fins54of a same fin structure52, seeFIG.8) and outer fin spacers94O (disposed between the semiconductor fins54and the hybrid fins66). In the illustrated embodiments, the inner fin spacers94N are separated after patterning, such that the STI regions68A are exposed. In another embodiment, the inner fin spacers94N are not completely separated, such that portions of the dielectric material(s) for the spacers remain over the STI regions68A. Further, because the STI regions68A have a lesser height than the STI regions68B, the inner fin spacers94N have a greater height than the outer fin spacers94O.

Further, implants may be performed to form lightly doped source/drain (LDD) regions (not separately illustrated). In the embodiments with different device types, similar to the implants for the wells previously described, a mask (not separately illustrated) such as a photoresist may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the semiconductor fins54exposed in the p-type region50P. The mask may then be removed. Subsequently, a mask (not separately illustrated) such as a photoresist may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the semiconductor fins54exposed in the n-type region50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities previously described, and the p-type impurities may be any of the p-type impurities previously described. During the implanting, the channel regions58remain covered by the dummy gates84, so that the channel regions58remain substantially free of the impurity implanted to form the LDD regions. The LDD regions may have a concentration of impurities in the range of 1015cm−3to 1019cm−3. An anneal may be used to repair implant damage and to activate the implanted impurities.

It is noted that the previous disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized, additional spacers may be formed and removed, and/or the like. Furthermore, the n-type devices and the p-type devices may be formed using different structures and steps.

InFIGS.10A-10C, source/drain recesses96are formed in the semiconductor fins54. In the illustrated embodiment, the source/drain recesses96extend into the semiconductor fins54. The source/drain recesses96may also extend into the substrate50. In various embodiments, the source/drain recesses96may extend to a top surface of the substrate50without etching the substrate50; the semiconductor fins54may be etched such that bottom surfaces of the source/drain recesses96are disposed below the top surfaces of the STI regions68; or the like. The source/drain recesses96may be formed by etching the semiconductor fins54using an anisotropic etching process, such as a RIE, a NBE, or the like. The etching process selectively etches the material(s) of the semiconductor fins54at a faster rate than the materials of the hybrid fins66and the STI regions68. The gate spacers92and the dummy gates84collectively mask portions of the semiconductor fins54during the etching processes used to form the source/drain recesses96. Timed etch processes may be used to stop the etching of the source/drain recesses96after the source/drain recesses96reach a desired depth. The fin spacers94(if present) may be etched during or after the etching of the source/drain recesses96, so that the height of the fin spacers94is reduced. The size and dimensions of the source/drain regions that will be subsequently formed in the source/drain recesses96may be controlled by adjusting the height of the fin spacers94. The hybrid fins66are not recessed, and remain between the fin structures52are the source/drain recesses96are etched.

InFIGS.11A-11C, epitaxial source/drain regions98are formed in the source/drain recesses96. The epitaxial source/drain regions98are thus disposed in the semiconductor fins54such that each dummy gate84(and corresponding channel region58) is between respective adjacent pairs of the epitaxial source/drain regions98. The epitaxial source/drain regions98thus adjoin the channel regions58. In some embodiments, the gate spacers92are used to separate the epitaxial source/drain regions98from the dummy gates84by an appropriate lateral distance so that the epitaxial source/drain regions98do not short out with subsequently formed gates of the resulting FinFETs. A material of the epitaxial source/drain regions98may be selected to exert stress in the respective channel regions58, thereby improving performance.

The epitaxial source/drain regions98in the n-type region50N may be formed by masking the p-type region50P. Then, the epitaxial source/drain regions98in the n-type region50N are epitaxially grown in the source/drain recesses96in the n-type region50N. The epitaxial source/drain regions98may include any acceptable material appropriate for n-type devices. For example, if the semiconductor fins54are silicon, the epitaxial source/drain regions98in the n-type region50N may include materials exerting a tensile strain on the channel regions58, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions98in the n-type region50N may be referred to as “n-type source/drain regions.” The epitaxial source/drain regions98in the n-type region50N may have surfaces raised from respective surfaces of the semiconductor fins54and may have facets.

The epitaxial source/drain regions98in the p-type region50P may be formed by masking the n-type region50N. Then, the epitaxial source/drain regions98in the p-type region50P are epitaxially grown in the source/drain recesses96in the p-type region50P. The epitaxial source/drain regions98may include any acceptable material appropriate for p-type devices. For example, if the semiconductor fins54are silicon, the epitaxial source/drain regions98in the p-type region50P may include materials exerting a compressive strain on the channel regions58, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions98in the p-type region50P may be referred to as “p-type source/drain regions.”The epitaxial source/drain regions98in the p-type region50P may have surfaces raised from respective surfaces of the semiconductor fins54and may have facets.

The epitaxial source/drain regions98and/or the semiconductor fins54may be implanted with impurities to form source/drain regions, similar to the process previously described for forming LDD regions, followed by an anneal. The source/drain regions may have an impurity concentration in the range of 1019cm−3to 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously described. In some embodiments, the epitaxial source/drain regions98may be in situ doped during growth.

The epitaxial source/drain regions98may include one or more semiconductor material layers. For example, the epitaxial source/drain regions98may each include a liner layer98A, a main layer98B, and a finishing layer98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source/drain regions98. In embodiments in which the epitaxial source/drain regions98include three semiconductor material layers, the liner layers98A may be grown in the source/drain recesses96, the main layers98B may be grown on the liner layers98A, and the finishing layers98C may be grown on the main layers98B. The liner layers98A, the main layers98B, and the finishing layers98C may be formed of different semiconductor materials and may be doped to different impurity concentrations. In some embodiments, the main layers98B have a greater concentration of impurities than the finishing layers98C, and the finishing layers98C have a greater concentration of impurities than the liner layers98A. Forming the liner layers98A with a lesser concentration of impurities than the main layers98B may increase adhesion in the source/drain recesses96, and forming the finishing layers98C with a lesser concentration of impurities than the main layers98B may reduce out-diffusion of dopants from the main layers98B during subsequent processing.

As a result of the epitaxy processes used to form the epitaxial source/drain regions98, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the semiconductor fins54. In some embodiments, these facets cause adjacent epitaxial source/drain regions98to merge as illustrated byFIG.11C. However, the hybrid fins66(where present) block the lateral epitaxial growth to prevent coalescing of some of the epitaxial source/drain regions98. For example, the hybrid fins66may be formed at cell boundaries to separate the epitaxial source/drain regions98of adjacent cells. Therefore, some of the epitaxial source/drain regions98are separated by the hybrid fins66. The epitaxial source/drain regions98may contact the sidewalls of the hybrid fins66. In the illustrated embodiments, the fin spacers94are formed to cover a portion of the sidewalls of the semiconductor fins54that extend above the STI regions68, thereby blocking the epitaxial growth. In another embodiment, the spacer etch used to form the gate spacers92is adjusted to not form the fin spacers94, so as to allow the epitaxial source/drain regions98to extend to the surfaces of the STI regions68.

The fin spacer94may maintain their relative heights after the fin spacers94are recessed (described forFIGS.10A-10C) and the epitaxial source/drain regions98are grown (described forFIGS.11A-11C), such that the inner fin spacers94N still have a greater height than the outer fin spacers94O. Accordingly, the outer fin spacers94O over the STI regions68B (between the hybrid fins66and the semiconductor fins54) have a first height, the inner fin spacers94N over the STI regions68A (between the semiconductor fins54) have a second height, and the second height greater than the first height. In some embodiments, the inner fin spacers94N and the outer fin spacers94O have a height in the range of 5 nm to 50 nm.

InFIGS.12A-12C, a first inter-layer dielectric (ILD)104is deposited over the epitaxial source/drain regions98, the gate spacers92, the masks86(if present) or the dummy gates84, and the hybrid fins66. The first ILD104may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used.

In some embodiments, a contact etch stop layer (CESL)102is formed between the first ILD104and the epitaxial source/drain regions98, the gate spacers92, the masks86(if present) or the dummy gates84, and the hybrid fins66. In some embodiments, the CESL102fills or substantially fills the seams66A of the hybrid fins66adjacent the source/drain regions98(see, e.g.,FIG.12C). The CESL102may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of the first ILD104. The CESL102may be formed by any suitable method, such as CVD, ALD, or the like.

InFIGS.13A-13C, a removal process is performed to level the top surfaces of the first ILD104with the top surfaces of the gate spacers92and the masks86(if present) or the dummy gates84. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process may also remove the masks86on the dummy gates84, and portions of the gate spacers92along sidewalls of the masks86. After the planarization process, the top surfaces of the first ILD104, the CESL102, the gate spacers92, and the masks86(if present) or the dummy gates84are coplanar (within process variations) such that they are level with each other. Accordingly, the top surfaces of the masks86(if present) or the dummy gates84are exposed through the first ILD104. In the illustrated embodiment, the masks86remain, and the planarization process levels the top surfaces of the first ILD104with the top surfaces of the masks86.

InFIGS.14A-14C, the masks86(if present) and the dummy gates84and dummy dielectrics82are removed in an etching process, so that recesses106are formed. The removal process removes the dummy dielectrics82from the seams66A of the hybrid fins66that were exposed with the removal of the dummy gates84. In some embodiments, the dummy dielectrics82are removed from recesses106in a first region of a die (e.g., a core logic region) and remain in recesses106in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates84are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the material of the dummy gates84at a faster rate than the materials of the first ILD104and the gate spacers92. During the removal, the dummy dielectrics82may be used as etch stop layers when the dummy gates84are etched. The dummy dielectrics82may then be removed after the removal of the dummy gates84. In some embodiments, the dummy dielectrics82are removed by an anisotropic etch process. Each recess106exposes and/or overlies a channel region58of a respective semiconductor fin54. The recesses106also expose the hybrid fins66and the seams66A of the hybrid fins66.

InFIGS.15A-16C, gate dielectrics112and gate electrodes114are formed for replacement gates. Each respective pair of a gate dielectric112and a gate electrode114may be collectively referred to as a “gate structure.” Each gate structure extends along sidewalls and a top surface of a channel region58of the semiconductor fins54. Some of the gate structures further extend along sidewalls and a top surface of a hybrid fin66.

The gate dielectrics112include two or more gate dielectric layer(s)112A and112B disposed in the recesses106, such as on the top surfaces and the sidewalls of the semiconductor fins54, on the top surfaces and the sidewalls of the hybrid fins66, and on sidewalls of the gate spacers92. The gate dielectric layer112A may be referred to as an interfacial layer and may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multi-layers thereof, or the like. The gate dielectric layer112A is formed to fill or substantially fill the seams66A in the hybrid fins66. The gate dielectric layer112A is formed in the seams66A by first soaking the structure in a silicon precursor followed by an oxidation process. In some embodiments, the silicon precursor includes SiH4, Si2H6, LTO520 (C6H17NSi), SAM24 (C8H22N2Si), the like, or a combination thereof. In some embodiments, the silicon precursor soaking process is performed at a temperature in a range from 350° C. to 490° C., for a time period in a range from 10 minutes to 30 minutes, and at a ratio of silicon precursor to carrier gas in a range from 5:1 to 10:1 with the carrier gas including N2, H2, or the like. Performing the silicon precursor soak with process conditions in these ranges followed by an oxidation process provides a sufficiently thin film (e.g., less than 10 Å), and the length, width, and height of the trench design between semiconductor fins54and hybrid fins66of the overall wafer structure is not affected.

In some embodiments, the oxidation process is an O3oxidation process. The gate dielectric layer112A within the seams66A of the hybrid fins66may have a different material composition than the gate dielectric layer112A on the semiconductor fins54. In some embodiments, the gate dielectric layer112A within the seams66A is more silicon-rich than the gate dielectric layer112A outside of the seams66A. For example, the gate dielectric layer112A within the seams66A of the hybrid fins66may have a ratio of silicon to oxygen (Si:O) in a range from 1:1 to 1:1.5 and the gate dielectric layer112A on the semiconductor fins54may have a Si:O ratio in a range from 1:1.5 to 1:2.

FIG.19illustrates a structure at a similar stage of processing asFIG.15Ain accordance with some embodiments. The formation steps and processes of this structure are similar to those described in the other embodiments and the descriptions are not repeated herein. InFIG.19, the gate dielectric layer112A is within the seams66A and on the channel regions58of the semiconductor fins54. In some embodiments, the gate dielectric layer112A is not formed on outer sidewall of the hybrid fins66as illustrated inFIG.19.

By filling the seams66A of the hybrid fins66with the interfacial layer112A, conductive material from subsequently formed source/drain and/or gate contacts is prevented from forming in the seams66A. Preventing the conductive material from source/drain and/or gate contacts to form in the seams66A prevents the source/drains and gates from shorting to each other by way of the seams66A. Manufacturing yield of the devices may thus be improved. Also, by simultaneously forming the interfacial layer(s) under the replacement gate structures and filling the seams66A, extra processing is not needed to fill the seams of the hybrid fins.

After the gate dielectric layer112A is formed, the gate dielectric layer112B is formed. The gate dielectric layer112B may include a high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material(s) of the gate dielectric layer112B may be formed by molecular-beam deposition (MBD), ALD, PECVD, or the like. The gate dielectric layer112B is not formed within the seams66A as the seams66A were already filled by the gate dielectric layer112A. In embodiments where portions of the dummy dielectrics82remain in the recesses106, the gate dielectric layers112includes a material of the dummy dielectrics82(e.g., silicon oxide). Although a dual-layered gate dielectric layers112is illustrated, the gate dielectric layers112may include any number of interfacial layers and any number of main layers.

InFIGS.16A-16C, the gate electrodes114including one or more gate electrode layer(s) are disposed over the gate dielectrics112, which fill the remaining portions of the recesses106. The gate electrodes114may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multi-layers thereof, or the like. Although single-layered gate electrodes114are illustrated, the gate electrodes114may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and a fill material.

As an example to form the gate structures, one or more gate dielectric layer(s) may be deposited in the recesses106. The gate dielectric layer(s) may also be deposited on the top surfaces of the first ILD104, the CESL102, and the gate spacers92. Subsequently, one or more gate electrode layer(s) may be deposited on the gate dielectric layer(s)112. A removal process may then be performed to remove the excess portions of the gate dielectric layer(s) and the gate electrode layer(s), which excess portions are over the top surfaces of the first ILD104, the CESL102, and the gate spacers92. The gate dielectric layer(s), after the removal process, have portions left in the recesses106(thus forming the gate dielectrics112). The gate electrode layer(s), after the removal process, have portions left in the recesses106(thus forming the gate electrodes114). In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. After the planarization process, the top surfaces of the gate spacers92, the CESL102, the first ILD104, the gate dielectrics112A and112B, and the gate electrodes114are coplanar (within process variations) such that they are level with each other.

The formation of the gate dielectrics112A and112B in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectrics112A and112B in each region are formed of the same material(s), and the formation of the gate electrodes114may occur simultaneously such that the gate electrodes114in each region are formed of the same material(s). In some embodiments, the gate dielectrics112A and112B in each region may be formed by distinct processes, such that the gate dielectrics112A and112B may include different materials and/or have a different number of layers, and/or the gate electrodes114in each region may be formed by distinct processes, such that the gate electrodes114may include different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

InFIGS.17A-17C, a second ILD124is deposited over the gate spacers92, the CESL102, the first ILD104, the gate dielectrics112A and112B, and the gate electrodes114. In some embodiments, the second ILD124is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD124is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be deposited by any suitable method, such as CVD, PECVD, or the like.

Optionally, before the formation of the second ILD124, gate masks116are formed over the gate structures (including the gate dielectrics112and the gate electrodes114). As an example to form the gate masks116, the gate structures and optionally the gate spacers92may be recessed using any acceptable etching process. One or more dielectric material(s) may then be formed in the recesses and on the top surfaces of the CESL102and the first ILD104. Acceptable dielectric materials include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like. Other insulation materials formed by any acceptable process may be used. A removal process is performed to remove the excess portions of the dielectric material(s), which excess portions are over the top surfaces of the CESL102and the first ILD104, thereby forming the gate masks116. The dielectric material(s), after the removal process, have portions left in the recesses (thus forming the gate masks116). In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. After the planarization process, the top surfaces of the CESL102, the first ILD104, and the gate masks116are coplanar (within process variations) such that they are level with each other. Gate contacts will be subsequently formed to penetrate through the gate masks116to contact the top surfaces of the gate electrodes114.

In some embodiments, an etch stop layer (ESL)122is formed between the second ILD124and the gate spacers92, the CESL102, the first ILD104, and the gate masks116(if present) or the gate dielectrics112A and112B and the gate electrodes114. The ESL122may include a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of the second ILD124.

InFIGS.18A-18C, gate contacts132and source/drain contacts134are formed to contact, respectively, the gate electrodes114and the epitaxial source/drain regions98. The gate contacts132are physically and electrically coupled to the gate electrodes114. The source/drain contacts134are physically and electrically coupled to the epitaxial source/drain regions98.

As an example to form the gate contacts132and the source/drain contacts134, openings for the gate contacts132are formed through the second ILD124, the ESL122, and the gate masks116, and openings for the source/drain contacts134are formed through the second ILD124, the ESL122, the first ILD104, and the CESL102. The openings may be formed using acceptable photolithography and etching techniques. A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD124. The remaining liner and conductive material form the gate contacts132and the source/drain contacts134in the openings. The gate contacts132and the source/drain contacts134may be formed in distinct processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the gate contacts132and the source/drain contacts134may be formed in different cross-sections, which may avoid shorting of the contacts.

Optionally, metal-semiconductor alloy regions136are formed at the interfaces between the epitaxial source/drain regions98and the source/drain contacts134. The metal-semiconductor alloy regions136can be silicide regions formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed of a metal germanide (e.g. titanium germanide, cobalt germanide, nickel germanide, etc.), silicon-germanide regions formed of both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions136can be formed before the material(s) of the source/drain contacts134by depositing a metal in the openings for the source/drain contacts134and then performing a thermal anneal process. The metal can be any metal capable of reacting with the semiconductor materials (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source/drain regions98to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal anneal process, a cleaning process, such as a wet clean, may be performed to remove any residual metal from the openings for the source/drain contacts134, such as from surfaces of the metal-semiconductor alloy regions136. The material(s) of the source/drain contacts134can then be formed on the metal-semiconductor alloy regions136.

Embodiments may achieve advantages. Filling seams66A of the hybrid fins66with the interfacial layer112A prevents conductive material from subsequently formed source/drain and/or gate contacts to form in the seams66A. Preventing the conductive material from source/drain and/or gate contacts to form in the seams66A prevents the source/drains and gates from shorting to each other by way of the seams66A. Manufacturing yield of the devices may thus be improved. In some embodiments, the seams66A are filled by a silicon precursor soaking process and an oxidation process. These processes simultaneously form the interfacial layer(s) under the replacement gate structures such that extra processing is not needed to fill the seams of the hybrid fins.

The disclosed FinFET embodiments could also be applied to nanostructure devices such as nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field-effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate structures and source/drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate structures are removed, the sacrificial layers can be partially or fully removed in channel regions. The replacement gate structures are formed in a manner similar to the above-described embodiments, the replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments.

Further, the FinFET/NSFET devices may be interconnected by metallization layers in an overlying interconnect structure to form integrated circuits. The overlying interconnect structure can be formed in a back end of line (BEOL) process, in which the metallization layers are connected to the gate contacts132and the source/drain contacts134. Additional features, such as passive devices, memories (e.g., magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), phase-change random access memory (PCRAM), etc.), or the like may be integrated with the interconnect structure during the BEOL process.

An embodiment includes a device including a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide inner portion extending downward from a top surface of the hybrid fin. The device also includes a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending above a top surface of the first isolation region, a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and source/drain regions on the first semiconductor fin on opposing sides of the gate electrode.

Embodiments may include one or more of the following features. The device where top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are level with each other. The first semiconductor fin includes an interfacial oxide layer between sidewalls of the first semiconductor fin and the high-k gate dielectric. The oxide inner portion of the hybrid fin is more silicon-rich than the interfacial oxide layer. The hybrid fin includes silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof. The device further including a third semiconductor fin adjacent the second semiconductor fin, a second isolation region between the second semiconductor fin and the third semiconductor fin, a top surface of the first isolation region disposed further from the substrate than a top surface of the second isolation region. A bottom surface of the first isolation region disposed further from top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin than a bottom surface of the second isolation region.

An embodiment includes a method including forming a first semiconductor fin and a second semiconductor fin extending from a substrate, forming an insulation material around the first semiconductor fin and the second semiconductor fin, a first portion of the insulation material disposed between the first semiconductor fin and the second semiconductor fin. The method also includes forming a hybrid fin on the first portion of the insulation material, the hybrid fin having a seam therein. The method also includes recessing the first portion of the insulation material to form a first isolation region. The method also includes forming a dummy gate structure over the first semiconductor fin, the hybrid fin, and the second semiconductor fin. The method also includes forming source/drain regions on the first semiconductor fin and the second semiconductor fin on opposing sides of the dummy gate structure. The method also includes removing the dummy gate structure to form a gate trench. The method also includes forming a first gate dielectric layer on the first semiconductor fin, the hybrid fin, and the second semiconductor fin in the gate trench, the first gate dielectric layer filling the seam in the hybrid fin. The method also includes forming a second gate dielectric layer on the first gate dielectric layer in the gate trench. The method also includes forming a gate electrode layer on the second gate dielectric layer in the gate trench.

Embodiments may include one or more of the following features. The method where forming the hybrid fin includes depositing a dielectric layer on the insulation material between the first semiconductor fin and the second semiconductor fin unoccupied by the insulation material, removing a portion of the dielectric layer. Removing the portion of the dielectric layer includes planarizing the dielectric layer, the insulation material, the first semiconductor fin, and the second semiconductor fin, where top surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are level with each other. Forming the first gate dielectric layer includes performing a silicon precursor soaking process in the gate trench, after performing the silicon precursor soaking process, performing an oxidation process in the gate trench, where after the oxidation process, the first gate dielectric layer is formed in the gate trench and in the seam of the hybrid fin. The first gate dielectric layer includes silicon oxide, and where the second gate dielectric layer includes a high-k layer. The first gate dielectric layer in the seam of the hybrid fin is more silicon-rich than the first gate dielectric layer on the first semiconductor fin. The hybrid fin includes silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof. The method further including forming an etch stop layer over the source/drain regions and the hybrid fin, the etch stop layer filling a portion of the seam in the hybrid fin outside of the gate trench, forming interlayer dielectric over the etch stop layer. The method further including forming conductive contacts through the interlayer dielectric and the etch stop layer to the source/drain regions, the conductive contacts being electrically connected to the source/drain regions.

An embodiment includes a method including forming a first semiconductor fin extending from a substrate. The method also includes forming an insulation material around the first semiconductor fin. The method also includes depositing a dielectric layer on the insulation material around the first semiconductor fin. The method also includes removing a portion of the dielectric layer to form a dielectric fin, the dielectric fin having a seam therein. The method also includes recessing the insulation material, where after recessing the insulation material, the dielectric fin extends above a top surface of the insulation material. The method also includes forming a dummy gate structure over the first semiconductor fin, the dielectric fin, and the recessed insulation material. The method also includes forming source/drain regions on the first semiconductor fin on opposing sides of the dummy gate structure. The method also includes removing the dummy gate structure to form a gate trench. The method also includes performing a silicon precursor soaking process in the gate trench. The method also includes after performing the silicon precursor soaking process, performing an oxidation process in the gate trench to form an interfacial layer on the first semiconductor fin and the dielectric fin in the gate trench, the interfacial layer filling the seam in the dielectric fin. The method also includes forming a high-k gate dielectric layer on the interfacial layer in the gate trench. The method also includes forming a gate electrode layer on the high-k gate dielectric layer in the gate trench.

Embodiments may include one or more of the following features. The method where the interfacial layer in the seam of the dielectric fin is more silicon-rich than the interfacial layer on the first semiconductor fin. The high-k gate dielectric layer is not in the seam of the dielectric fin. Removing the portion of the dielectric layer includes planarizing the dielectric layer, the insulation material, and the first semiconductor fin, where top surfaces of the dielectric fin and the first semiconductor fin are level with each other.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.