Patent ID: 12211844

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Furthermore, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

The gate all around (GAA) transistor structures described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, smaller pitches than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

Fin field effect transistors (FinFETs) are widely used in integrated circuits (ICs) including different type of devices, e.g., logic devices, memory devices (such as static random access memory (SRAM)), etc. Gate-all-around FETs (GAA FETs) can exhibit improved gate control over its channel region (e.g., low DIBL) than FinFET. The aspect of the embodiments of the present disclosure is direct to a formation method and structures that provide hybrid structures including gate-all-around field-effect transistors (GAA FETs) and FinFETs formed over the same semiconductor substrate (or chip). In addition, the embodiments of the present disclosure provide the hybrid structures including an isolation feature and gate-cut features to electrically isolate those transistors from one another. Therefore, lower processing difficulty and greater design flexibility for integrated circuits including different type of devices may be achieved by the semiconductor structure of the embodiments of the present disclosure.

FIG.1is a perspective view of a semiconductor structure, in accordance with some embodiments of the disclosure. A semiconductor structure12is provided, as shown inFIG.1, in accordance with some embodiments. The semiconductor structure12includes a substrate102, and a first fin structure118and a second fin structure120over the substrate102, in accordance with some embodiments. For example, the first fin structure118may be used to form gate-all-around field-effect transistor devices, and the second fin structure120may be used to form FinFET devices.

For a better understanding of the semiconductor structure,FIG.1illustrates an X-Y-Z coordinate reference that is used in later figures. The X-axis and Y-axis are generally orientated along the lateral directions that are parallel to the main surface of the substrate102. The Y-axis is transverse (e.g., substantially perpendicular) to the X-axis. The Z-axis is generally oriented along the vertical direction that is perpendicular to the main surface of the substrate102(or the X-Y plane).

The first fin structure118includes a lower fin element103formed from a portion of the substrate102and an upper fin element formed from an epitaxial stack including semiconductor layers104,110and112, in accordance with some embodiments. The second fin structure120includes a lower fin element103formed from a portion of the substrate102and an upper fin element formed from an epitaxial stack including semiconductor layers104and106, in accordance with some embodiments.

The fin structures118and120extend in the X direction, in accordance with some embodiments. That is, the fin structures118and120each have a longitudinal axis parallel to X direction, in accordance with some embodiments. The X direction may also be referred to as the channel-extending direction. Each of the fin structures118and120includes a channel region CH and source/drain regions SD, where the channel region CH is defined between the source/drain regions SD, in accordance with some embodiments.FIG.1shows one channel region CH and two source/drain regions SD for illustrative purpose and is not intended to be limiting. The number of the channel region CH and the source/drain region SD may be dependent on the semiconductor device design demand and/or performance consideration. Gate structures (not shown) will be formed with a longitudinal axis parallel to Y direction and extending across the channel regions CH of the fin structures118and120. Y direction may also be referred to as a gate-extending direction.

FIGS.2A to2K-4are diagrammatic views illustrating the formation of a semiconductor structure at various intermediate stages, in accordance with some embodiments of the disclosure.

FIG.2Ais a cross-sectional view of a semiconductor structure12after the formation of a first epitaxial stack, in accordance with some embodiments.

The semiconductor structure12includes a substrate102, as shown inFIG.2A, in accordance with some embodiments. The substrate102includes a first region200where gate-all-around FET devices are to be formed and a second region300where the FinFET devices are to be formed, in accordance with some embodiments. In some embodiments, the first region200is located adjacent to the second region300.

In some embodiments, the substrate102is a silicon substrate. In some embodiments, the substrate102includes an elementary semiconductor such as germanium; a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Furthermore, the substrate102may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features.

A first semiconductor layer104is formed over the substrate102, and a second semiconductor layer106is formed over the first semiconductor layer104, as shown inFIG.2A, in accordance with some embodiments. In some embodiments, the first semiconductor layer104has a thickness in a range from about 1.5 nanometers (nm) to about 20 nm. In some embodiments, the second semiconductor layer106has a thickness in a range from about 5 nm to about 300 nm.

The first semiconductor layer104has a different lattice constant than the second semiconductor layer106, in accordance with some embodiments. In some embodiments, the first semiconductor layer104and the second semiconductor layer106have different oxidation rates and/or etching selectivity. In some embodiments, the first semiconductor layer104is made of silicon germanium (SiGe), where the percentage of germanium (Ge) in the SiGe is in a range from about 20 atomic % to about 50 atomic %, and the second semiconductor layer106are made of silicon (Si). In some embodiments, the first semiconductor layer104and the second semiconductor layer106are formed using epitaxial growth processes such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE), or another suitable technique. In some embodiments, the first semiconductor layer104and the second semiconductor layer106are collectively referred to as a first epitaxial stack.

FIG.2Bis a cross-sectional view of a semiconductor structure12after the formation of a recess108, in accordance with some embodiments.

An etching process is performed on the semiconductor structure12to recess the first epitaxial stack from the first region200of the substrate102, in accordance with some embodiments. A portion of the second semiconductor layer106in the first region200is removed to form a recess108, as shown inFIG.2B, in accordance with some embodiments. In some embodiments, a patterned mask layer (not shown) is formed over the second semiconductor layer106prior to the etching process. The patterned mask layer may be a patterned photoresist layer and/or a patterned hard mask layer and is formed to cover the second region300of the substrate102while exposing the first region200of the substrate102. The etching process may be a dry etching and/or a wet etching and the first semiconductor layer104is used as an etching stop layer in the etching process. In some embodiments, the etching process is performed until portion of the first semiconductor layer104in the first region200is exposed from the recess108.

FIG.2Cis a cross-sectional view of a semiconductor structure12after the formation of a second epitaxial stack, in accordance with some embodiments.

Third semiconductor layers110and fourth semiconductor layers112are alternatingly formed over the first semiconductor layer104from the recess108, as shown inFIG.2C, in accordance with some embodiments. In some embodiments, the thickness of each of the third semiconductor layers110is in a range from about 1.5 nm to about 20 nm. In some embodiments, the thickness of each of the fourth semiconductor layers112is in a range from about 1.5 nm to about 20 nm. In some embodiments, the thicknesses of the third semiconductor layers110and the fourth semiconductor layers112are greater than the thickness of the first semiconductor layer104.

The third semiconductor layers110have a different lattice constant than the fourth semiconductor layers112and the first semiconductor layer104, in accordance with some embodiments. In some embodiments, the third semiconductor layers110has a different oxidation rate and/or etching selectivity than the fourth semiconductor layers112and the first semiconductor layer104. In some embodiments, the third semiconductor layers110are made of silicon (Si), and the fourth semiconductor layers112are made of silicon germanium (SiGe), where the percentage of germanium (Ge) in the SiGe is in a range from about 20 atomic % to about 50 atomic %. In some embodiments, the composition of the third semiconductor layers110is substantially the same as the second semiconductor layer106and the composition of the fourth semiconductor layers112is substantially the same as the first semiconductor layer104.

In some embodiments, the third semiconductor layers110and the fourth semiconductor layers112are formed using an epitaxial growth process such as MBE, MOCVD, or VPE, or another suitable technique. In some embodiments, the third semiconductor layers110, the fourth semiconductor layers112and a portion of first semiconductor layer104in the first region200are collectively referred to as a second epitaxial stack. In some embodiments, the first epitaxial stack is located over the second region300of the substrate102and the second epitaxial stack is located over the first region200of the substrate102.

A planarization process (e.g., chemical mechanical polish (CMP)) may be performed on the semiconductor structure12to remove portions of the third semiconductor layers110and the fourth semiconductor layers112formed over the upper surface of the second semiconductor layer106. The planarization process may also remove the patterned mask layer over the second semiconductor layer106to expose the second semiconductor layer106. After the planarization process, the upper surface of the uppermost third semiconductor layer110is substantially coplanar with the upper surface of the second semiconductor layer106, in accordance with some embodiments.

FIG.2D-1is a top view of a semiconductor structure12after the formation of a first fin structure118and a second fin structure120, in accordance with some embodiments.FIG.2D-2is a cross-sectional view taken along line Y1-Y1inFIG.2D-1.

The second epitaxial stack in the first region200, the first epitaxial stack in the second region300and the underlying substrate102are patterned to form a first fin structure118in the first region200and a second fin structure120in the second region300, as shown inFIGS.2D-1and2D-2, in accordance with some embodiments. The fin structures118and120are active regions of the semiconductor structure12, which are to be formed into channel regions and source/drain regions of transistors, e.g., gate-all-around FETs and FinFETs, in accordance with some embodiments. The fin structures118and120extend in the X direction and are arranged substantially parallel with one another in the Y direction, in accordance with some embodiments. That is, the fin structures118and120have longitudinal axes parallel to the X direction, in accordance with some embodiments.

In some embodiments, the patterning process includes forming a patterned mask layer (not shown) over the semiconductor structure12, and etching the semiconductor structure12uncovered by the patterned hard mask layer, thereby forming trenches122and the fin structures118and120. The patterned mask layer may be a patterned photoresist layer and/or a patterned hard mask. The etching process may be an anisotropic etching process, e.g., dry etching.

In some embodiments, after the etching process, the substrate102has portions protruding from between the trenches122to form lower fin elements103of the fin structures118and120. In some embodiments, a remainder of the second epitaxial stack (including the first semiconductor layer104, the third semiconductor layers110and the fourth semiconductor layers112in the first region200) forms an upper fin element of the first fin structure118over the lower fin element103. In some embodiments, a remainder of the first epitaxial stack (including the first semiconductor layer104and the second semiconductor layer106in the second region300) forms an upper fin element of the second fin structure120over the lower fin element103.

FIG.2E-1is a top view of a semiconductor structure12after the formation of an isolation structure124, a plurality of dummy gate structures126, source/drain features134and136, and an interlayer dielectric (ILD) layer138, in accordance with some embodiments.FIGS.2E-2,2E-3,2E-4and2E-5are cross-sectional views taken along line Y1-Y1, line X1-X1, line X2-X2and line X3-X3inFIG.2E-1. The top view ofFIG.2E-1merely illustrate the fin structures118and120, dummy gate structures126and interlayer dielectric layer138for illustrative purpose, and other features may be illustrated in the cross-sectional views ofFIGS.2E-2to2E-5.

An isolation structure124is formed over the substrate102and surrounds the lower fin element103of the first fin structure118and the lower fin element103of the second fin structure120, as shown inFIGS.2E-2and2E-3, in accordance with some embodiments. The isolation structures124is configured to electrically isolate the active regions (e.g., the first fin structure118and the second fin structure120) and is also referred to as shallow trench isolation (STI) feature, in accordance with some embodiments.

In some embodiments, the isolation structure124is made of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, multilayers thereof, and/or a combination thereof. In some embodiments, the formation of the isolation structure124includes depositing an one or more insulating materials for the isolation structure124over the semiconductor structure12to fill the trenches122(FIG.2D-2), and planarizing the insulating material to remove portions of the insulating material above the upper surfaces of the fin structures118and120. In some embodiments, the deposition process includes CVD (such as LPCVD, plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), high aspect ratio process (HARP), flowable CVD (FCVD)), atomic layer deposition (ALD), another suitable technique, and/or a combination. The planarization may be CMP.

Afterward, the insulating material is recessed using an etching process to form the isolation structure124and expose portions of the sidewalls of the fin structures118and120. A recessing depth may be controlled (e.g., by controlling an etching time) so as to result in a desired height of the exposed portion of the fin structures118and120. In some embodiments, the first semiconductor layers104of the first fin structure118and the first semiconductor layer104of the second fin structure120are exposed from the isolation structure124.

A plurality of dummy gate structures126is formed over the semiconductor structure12, as shown inFIGS.2E-1to2E-5, in accordance with some embodiments. In some embodiments, the plurality of dummy gate structures126includes dummy gate structures1261,1262,1263and1264. In some embodiments, the dummy gate structures126extend in Y direction and are arranged substantially parallel with one another along X direction. That is, the dummy gate structures126have longitudinal axes parallel to Y direction, in accordance with some embodiments. The dummy gate structures126extend across and wrap the channel regions of the fin structures118and120, in accordance with some embodiments.

The dummy gate structures126each includes a dummy gate dielectric layer128and a dummy gate electrode layer130formed over the dummy gate dielectric layer128, as shown inFIGS.2E-2to2E-5, in accordance with some embodiments. In some embodiments, the dummy gate dielectric layers128are made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, and/or a combination thereof. In some embodiments, the dielectric material is formed using ALD, CVD, thermal oxidation, physical vapor deposition (PVD), another suitable technique, and/or a combination thereof. In some embodiments, the dummy gate electrode layers130are made of a conductive material, such as polysilicon, poly-silicon germanium, and/or a combination thereof. In some embodiments, the conductive material is formed using CVD, another suitable technique, and/or a combination thereof.

In some embodiments, the formation of the dummy gate structures126includes conformally depositing a dielectric material for the dummy gate dielectric layer128over the semiconductor structure12, depositing a conductive material for the dummy gate electrode layer130over the dielectric material, planarizing the conductive material, and patterning the conductive material and dielectric material into the dummy gate structures126. The patterning process may include forming etching masks (not shown) over the conductive material to cover the channel regions of the fin structures118and120. The conductive material and dielectric material, uncovered by the etching masks, may be etched away to expose the source/drain region of the fin structures118and120.

Gate spacer layers132are formed along and cover opposite sidewalls of the dummy gate structures126, as shown inFIGS.2E-3to2E-5, in accordance with some embodiments. The gate spacer layers132are configured to offset the subsequently formed source/drain features and separate the source/drain features from the gate structure.

In some embodiments, the gate spacer layers132are made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), and/or a combination thereof. In some embodiments, the formation of the gate spacer layers132includes conformally depositing a dielectric material for the gate spacer layers132over the semiconductor structure12followed by an anisotropic etching process such as dry etching. The etching process is performed to remove horizontal portions of the dielectric material for the gate spacer layers132, while leaving vertical portions of the dielectric material on sidewalls of the dummy gate structure126to act as the gate spacer layers132.

Source/drain features134are formed over the first fin structure118, and source/drain features136are formed over the second fin structures120, as shown inFIGS.2E-4and2E-5, in accordance with some embodiments. The source/drain features134and136are formed on opposite sides of the dummy gate structure126, in accordance with some embodiments.

The formation of the source/drain features134and136includes recessing the fin structures118and120to form source/drain recesses (not shown) at the source/drain regions, in accordance with some embodiments. A recessing depth may be dependent on a desired height of the source/drain features134and136for performance consideration. Afterward, one or more semiconductor material for the source/drain features134and136are grown on the fin structures118and120from the source/drain recesses using epitaxial growth processes, in accordance with some embodiments. The epitaxial growth process may be MBE, MOCVD, or VPE, another suitable technique, or a combination thereof.

In some embodiments, the source/drain features134and136are made of any suitable material for n-type semiconductor devices and p-type semiconductor devices, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof. In some embodiments, the source/drain features134and136are doped in-situ during the epitaxial growth process. For example, the source/drain features134and136may be the epitaxially grown SiGe doped with boron (B). For example, the source/drain features134and136may be the epitaxially grown Si doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features. In some embodiments, the growth of the source/drain features134and the growth of the source/drain features136are performed in different steps.

An interlayer dielectric layer138is formed over the semiconductor structure12, as shown inFIGS.2E-1and2E-3to2E-5, in accordance with some embodiments. The interlayer dielectric layer138fills the space between dummy gate structures126to cover the source/drain features134and136, in accordance with some embodiments.

In some embodiments, the interlayer dielectric layer138is made of a dielectric material, such as un-doped silicate glass (USG), or doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and/or another suitable dielectric material. In some embodiments, a dielectric material for the interlayer dielectric layer138is deposited using such as CVD (such as HDP-CVD, PECVD, or HARP), another suitable technique, and/or a combination thereof. Afterward, the dielectric materials for the interlayer dielectric layer138above the upper surfaces of the dummy gate electrode layers130are removed using such as CMP until the upper surfaces of the dummy gate structures126are exposed. In some embodiments, the upper surface of the interlayer dielectric layer138is substantially coplanar with the upper surfaces of the dummy gate electrode layers130.

FIG.2F-1is a top view of a semiconductor structure12after the formation of a cut trench144, in accordance with some embodiments.FIGS.2F-2,2F-3,2F-4and2F-5are cross-sectional views taken along line Y1-Y1, line X1-X1, line Y2-Y2and line X2-X2inFIG.2F-1.

A cut trench144is formed through the dummy gate structure1263and the first fin structure118, as shown inFIGS.2F-1to2F-3and2F-5, in accordance with some embodiments. The cut trench144may be also referred to cut polysilicon on oxide definition edge (CPODE) pattern. The cut trench144corresponds to a cross point of the dummy gate structure1263and the first fin structure118so as to cut the dummy gate structure1263into two segments (or referred to as sub-gate structures) and the first fin structure118into two segments (or referred to as sub-active regions), in accordance with some embodiments. The cut trench144extends in Y direction, in accordance with some embodiments. That is, the cut trench144has a longitudinal axis parallel to Y direction, in accordance with some embodiments.

In some embodiments, the formation of the cut trench144includes forming a patterned mask layer140over the semiconductor structure12. In some embodiments, the patterned mask layer140has an opening142corresponding to the cut trench144. Afterword, an etching process is performed to removes portions of the dummy gate structure1263and the first fin structure118uncovered by the patterned mask layer140to form cut trench144. The etching process will be described in detail later with respect toFIGS.4A-4D.

The etching process removes the dummy gate structure1263and the first fin structure118, such that the gate spacer layers132are exposed from the cut trench144, as shown inFIG.2F-3, in accordance with some embodiments. After the dummy gate structure1263and the first fin structure118are removed, the cut trench144extends into the isolation structure124and the substrate102. Because of the difference in etching selectivity between the isolation structure124and the substrate102, the cut trench144has a first bottom surface144A exposing the isolation structure124(as shown inFIGS.2F-2and2F-3) and a second bottom surface144B exposing the substrate102(as shown inFIGS.2F-2and2F-5), which is at a deeper position than the first bottom surface144A, in accordance with some embodiments.

Portions of the first fin structure118adjacent to the cut trench144are covered by the gate spacer layers132during the etching process and therefore remain unetched, as shown inFIG.2F-5, in accordance with some embodiments. The respective unetched portions of the third semiconductor layer110, the fourth semiconductor layer112, the first semiconductor layer104and the low fin element103of the first fin structure118are denoted as a third semiconductor layer110′, a fourth semiconductor layer112′, a first semiconductor layer104′ and a low fin element103′ respectively, which collectively form a semiconductor stack adjacent to the cut trench144, as shown inFIG.2F-5, in accordance with some embodiments.

FIG.2G-1is a top view of a semiconductor structure12after the formation of an isolation feature146, in accordance with some embodiments.FIGS.2G-2,2G-3,2G-4and2G-5are cross-sectional views taken along line Y1-Y1, line X1-X1, line Y2-Y2and line X2-X2inFIG.2G-1.

An isolation feature146is formed in the cut trench144, as shown inFIGS.2G-1to2G-4and2G-5, in accordance with some embodiments. The isolation feature146includes a dielectric lining layer148and a dielectric fill layer150over the dielectric lining layer148, in accordance with some embodiments. The isolation feature146separates and electrically isolates neighboring segments of the dummy gate structure1263and neighboring segments of the first fin structure118, in accordance with some embodiments.

In some embodiments, the dielectric lining layer148is made of a dielectric material such as silicon oxide, and the dielectric fill layer150is made of a dielectric material such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, or a combination thereof. The dielectric lining layer148functions as a liner as it attaches to the first fin structure118better than the dielectric fill layer150and isolates the dielectric fill layer150from the first fin structure118to prevent unintended surface charging or stress resulting from direct contact between the dielectric fill layer150and the first fin structure118. In some embodiments, the dielectric lining layer148and the dielectric fill layer150are deposited using such as CVD (such as HDP-CVD, PECVD, or HARP), another suitable technique, and/or a combination thereof. Afterward, a planarization process, e.g., CMP, may be performed on the semiconductor structure12to removes the dielectric lining layer148and the dielectric fill layer150over the upper surface of the interlayer dielectric layer138. The planarization process may also remove the patterned mask layer140(FIG.2F-2). In some embodiments, the upper surface of the isolation feature146is substantially coplanar the upper surface of the interlayer dielectric layer138.

FIG.2H-1is a top view of a semiconductor structure12after a channel releasing process, in accordance with some embodiments.FIGS.2G-2,2G-3,2G-4,2G-5and2G-6are cross-sectional views taken along line Y1-Y1, line X1-X1, line Y2-Y2, line X2-X2and line X3-X3inFIG.2H-1.

A channel releasing process is performed on the semiconductor structure12, in accordance with some embodiments. The dummy gate structures126are first removed using an etching process to form a plurality of gate trenches152, as shown inFIGS.2H-1to2H-5, in accordance with some embodiments. The plurality of gate trenches152includes gate trenches1521,1522,1523and1524, in accordance with some embodiments. The gate trenches152expose the channel regions of the fin structures118and120, in accordance with some embodiments. In some embodiments, the gate trenches152expose the inner sidewalls of the gate spacer layers132facing the channel regions, as shown inFIGS.2H-3,2H-5and2H-6, in accordance with some embodiments. In some embodiments, the gate trenches152expose the sidewalls of the isolation feature146, as shown inFIGS.2H-1and2H-2, in accordance with some embodiments.

In some embodiments, the etching process includes one or more etching processes. For example, when the dummy gate electrode layers130are made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layers130. For example, the dummy gate dielectric layers128may be thereafter removed using a plasma dry etching, a dry chemical etching, and/or a wet etching.

The channel releasing process also includes removing the first semiconductor layer104and the fourth semiconductor layers112using an etching, in accordance with some embodiments. The first semiconductor layer104and the fourth semiconductor layers112of the first fin structure118are removed to form gaps154, as shown inFIGS.2H-4to2H-5, in accordance with some embodiments. The first semiconductor layer104of the second fin structure120is removed to form gaps156, in accordance with some embodiments.

The gaps154are formed between the neighboring third semiconductor layers110and between the lowermost third semiconductor layer110and the lower fin element103, in accordance with some embodiments. After the etching process, the four main surfaces of the third semiconductor layers110are exposed, as shown inFIG.2H-4, in accordance with some embodiments. The exposed third semiconductor layers110form nanostructures that function as channel layers of the resulting semiconductor device s (e.g., gate-all-around FETs), in accordance with some embodiments. As the term is used herein, “nanostructures” refers to semiconductor layers that have cylindrical shape, bar shaped and/or sheet shape. The nanostructures (e.g., nanowire or nanosheet structures) laterally extend between source/drain features134, in accordance with some embodiments.

The gaps156are formed between the second semiconductor layer106and the lower fin element103, in accordance with some embodiments. After forming the gap156, the second semiconductor layer106of the second fin structure120may also referred to as a floating fin element, which is floating over the lower fin element103. The floating fin element106of the second fin structures120functions as a channel layer of the resulting semiconductor devices (e.g., FinFETs), in accordance with some embodiments.

In some embodiments, the upper surface of the uppermost nanostructure110is substantially level with the upper surface of the floating fin element106. In some embodiments, the bottom surface of the lowermost nanostructure110is substantially level with the bottom surface of the floating fin element106.

In some embodiments, the etching process includes a selective wet etching process, such as APM (e.g., ammonia hydroxide-hydrogen peroxide-water mixture) etching process. In some embodiments, the wet etching process uses etchants such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine pyrocatechol (EDP), and/or potassium hydroxide (KOH) solutions.

After the channel releasing process, inner spacer layers158are formed in the gaps154and156, as shown inFIGS.2H-5and2H-6, in accordance with some embodiments. The inner spacer layers158are formed on the surfaces of the source/drain features134and136exposed by the gaps154and156, in accordance with some embodiments. The inner spacer layers158are aligned below the gate spacer layer132, in accordance with some embodiments. The inner spacer layers158, formed between the source/drain features134and136and a subsequently formed final gate stack, are configured to reduce the parasitic capacitance between the final gate stack and the source/drain features (i.e. Cgs and Cgd), in accordance with some embodiments.

In some embodiments, the inner spacer layers158are made of a dielectric material, such as silicon oxycarbide (SiOC), silicon oxide carbonitride (SiOCN), silicon carbon nitride (SiCN), and/or a combination thereof, in accordance with some embodiments. In some embodiments, the inner spacer layers158are formed using a deposition process followed by an etching process. In some embodiments, the deposition process includes CVD (such as PECVD or LPCVD), ALD, another suitable technique, and/or a combination thereof. In some embodiments, the etching process includes a plasma dry etching, a dry chemical etching, and/or a wet etching.

FIG.2I-1is a top view of a semiconductor structure12after the formation of a plurality of final gate stacks160, in accordance with some embodiments.FIGS.2I-2,2I-3,2I-4,2I-5and2I-6are cross-sectional views taken along line Y1-Y1, line X1-X1, line Y2-Y2, line X2-X2and line X3-X3inFIG.2I-1.

A plurality of final gate stacks160is formed over the semiconductor structure12, as shown inFIGS.2I-1to2I-6, in accordance with some embodiments. The plurality of final gate stacks160includes final gate stacks1601,1602,1603and1604, in accordance with some embodiments. The plurality of final gate stacks160is formed to fill the gate trenches152and the gaps154and156, in accordance with some embodiments. The plurality of final gate stacks160extend across the nanostructures110of first fin structure118and the floating fin element106of the second fin structure120, in accordance with some embodiments.

The final gate stacks1601,1602,1603and1604each include an interfacial layer162, a high-k gate dielectric layer164and the metal gate electrode layer166, as shown inFIGS.2I-2to2I-6, in accordance with some embodiments. The interfacial layers162are formed on the exposed surfaces of the nanostructures110, the floating fin element106, and the lower fin elements103, as shown inFIGS.2I-2to2I-6, in accordance with some embodiments. The interfacial layers162wrap around the nanostructures110and the floating fin element106, in accordance with some embodiments. In some embodiments, the interfacial layers162are made of a chemically formed silicon oxide. In some embodiments, the interfacial layers162are formed using one or more cleaning processes such as including ozone (O3), ammonia hydroxide-hydrogen peroxide-water mixture, and/or hydrochloric acid-hydrogen peroxide-water mixture. Therefore, portions of semiconductor material from the nanostructures110, the floating fin element106and the lower fin elements103are oxidized to form the interfacial layers162, in accordance with some embodiments.

The high-k gate dielectric layer164is formed conformally along the interfacial layer162to wrap around the nanostructures110and the floating fin element106, as shown inFIGS.2I-2to2I-6, in accordance with some embodiments. The high-k gate dielectric layer164is also conformally formed along the inner sidewalls of the inner spacer layers158facing the channel region and the inner sidewalls of the gate spacer layers124facing the channel region, as shown inFIGS.2I-5and2I-6, in accordance with some embodiments. A remainder of the lowermost gap154and a remainder of the gap156(FIGS.2H-4to2H-6) are substantially filled by the high-k gate dielectric layers164while other gaps154are partially filled by the high-k gate dielectric layers164because the first semiconductor layer104is thinner than the fourth semiconductor layer112, as shown inFIGS.2I-4to2I-6, in accordance with some embodiments. The high-k gate dielectric layer164is also conformally formed along the sidewalls of the isolation features146, as shown inFIGS.2I-1and2I-2, in accordance with some embodiments. The high-k gate dielectric layer164is also conformally formed along the upper surface of the isolation structure124, as shown inFIGS.2I-2and2I-4, in accordance with some embodiments.

In some embodiments, the high-k gate dielectric layers164are made of a dielectric material with high dielectric constant (k value), for example, greater than 3.9. In some embodiments, the high-K dielectric material includes hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfSiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides (SiON), a combination thereof, or another suitable material. The high-K gate dielectric layer164may be formed by ALD, PVD, CVD, and/or another suitable technique.

The metal gate electrode layer166is formed over the high-k gate dielectric layers164and fills remainders of gate trenches152and the gaps154, as shown inFIGS.2I-1to2I-6, in accordance with some embodiments. The metal gate electrode layer166wraps the nanostructures110and the floating fin element106, in accordance with some embodiments. In some embodiments, the metal gate electrode layer166is made of more than one conductive material, such as a metal, metal alloy, conductive metal oxide and/or metal nitride, another suitable conductive material, and/or a combination thereof. The metal gate electrode layer166may be a multi-layer structure with various combinations of a diffusion barrier layer, a work function layer with a selected work function to enhance the device performance (e.g., threshold voltage) for n-channel transistor and p-channel transistor, a capping layer to prevent oxidation of a work function layer, a glue layer to adhere the work function layer to a next layer, and a metal fill layer to reduce the resistance of the gate stack, and/or another suitable layer.

The metal gate electrode layer166may be made of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, another suitable conductive material, or multilayers thereof. The metal gate electrode layer may be formed by ALD, PVD, CVD, e-beam evaporation, or another suitable process. Furthermore, the metal gate electrode layer166may be formed separately for N-FET and P-FET which may use different gate electrode materials and/or different work function materials.

A planarization process such as CMP may be performed on the semiconductor structure12to remove the materials of the high-k gate dielectric layer164and the metal gate electrode layer166formed above the upper surface of the interlayer dielectric layer138, in accordance with some embodiments. After the planarization process, the upper surface of the metal gate electrode layer166, the upper surface of the isolation feature146and the upper surface of the interlayer dielectric layer138are substantially coplanar, in accordance with some embodiments.

The interfacial layers162, the high-k gate dielectric layers164and the metal gate electrode layers166combine to form the final gate stacks1601,1602,1603and1604, in accordance with some embodiments. The final gate stacks160may engage the channel region (i.e., the nanostructures110of the first fin structure118and the floating fin element106of the second fin structure120) of the transistors, such that current can flow between the source/drain features134and between the source/drain features136during operation. In some embodiments, the final gate stacks1601,1602,1603and1604extend in Y direction. That is, the final gate stacks1601,1602,1603and1604have longitudinal axes parallel to Y direction, in accordance with some embodiments. The final gate stacks160are arranged in the X direction. In addition, the final gate stack1603is separated into two segments (or referred to as sub-gate stacks) by the isolation feature146, as shown inFIGS.2I-1and2I-2, in accordance with some embodiments.

Portions of the final gate stacks160interposing the source/drain features134combine with the source/drain features134to form gate-all-around FETs Ti, as shown inFIGS.2I-1and2I-5, in accordance with some embodiments. That is, the gate-all-around FETs T1are formed at cross points of the first fin structures118and the final gate stack160except for the cross point of first fin structure118and the final gate stack1603where the isolation feature146occupies, in accordance with some embodiments. The isolation feature146is located between and electrically isolates two gate-all-around FETs T1, as shown inFIGS.2I-1and2I-5, in accordance with some embodiments. In addition, the semiconductor stack including the fourth semiconductor layer112′, the third semiconductor layer110′, the first semiconductor layer104′ and the low fin element103′ is located between the source/drain features134of the gate-all-around FETs T1and the isolation feature146, as shown inFIG.2I-5, in accordance with some embodiments.

Portions of the final gate stacks160interposing the source/drain features136combine with the source/drain features136to form FinFETs T2, as shown inFIGS.2I-1and2I-6, in accordance with some embodiments. That is, the FinFETs T2are formed at cross points of the second fin structure120and the final gate stacks160, in accordance with some embodiments.

FIG.2J-1is a top view of a semiconductor structure12after the formation of gate-cut openings172, in accordance with some embodiments.FIGS.2J-2,2J-3and2J-4are cross-sectional views taken along line Y1-Y1, line X1-X1and line Y2-Y2inFIG.2J-1.

A cutting process is performed on the plurality of the final gate stacks160to form gate-cut openings172, as shown inFIGS.2J-1,2J-2and2J-4, in accordance with some embodiments. The gate-cut openings172cut each of the final gate stacks160into a plurality of segments, in accordance with some embodiments. The gate-cut openings172are formed through the final gate stacks160and expose the isolation structure124, as shown inFIGS.2J-2and2J-4, in accordance with some embodiments. In some embodiments, the gate-cut openings172are substantially equal in length along Y direction to each other.

The cutting process includes forming a patterned mask layer168over the semiconductor structure12, as shown inFIGS.2J-1to2J-4, in accordance with some embodiments. In some embodiments, the patterned mask layer168has openings170which correspond to the gate-cut openings172but stagger the fin structures118and120, as shown inFIG.2J-1. Afterword, an etching process is performed to removes portions of metal gate electrode layer168and high-k gate dielectric layers166until the isolation structure124is exposed, in accordance with some embodiments. The etching process will be described in detail later with respect toFIGS.5A-5D.

In addition, the openings170of the patterned mask layer168partially overlap the isolation feature146such that two gate-cut openings172adjacent to the isolation feature146are formed through portions of the isolation feature146to remove portions of the dielectric lining layer148and the dielectric fill layer150, as shown inFIG.2J-2, in accordance with some embodiments.

FIG.2K-1is a top view of a semiconductor structure12after the formation of gate-cut features174, in accordance with some embodiments.FIGS.2K-2,2K-3and2K-4are cross-sectional views taken along line Y1-Y1, line X1-X1and line Y2-Y2inFIG.2K-1.

Gate-cut features174are formed in the gate-cut openings172, as shown inFIGS.2K-1to2K-4, in accordance with some embodiments. The gate-cut features174separate and electrically isolate neighboring segments of the final gate stacks160such that a gate-all-around FET T1and neighboring FinFET T2, which have shared the same final gate stack160, are electrically isolated from one another, in accordance with some embodiments. The gate-cut features174adjacent to the isolation feature146are in contact with both the dielectric lining layer148and the dielectric fill layer150, as shown inFIGS.2K-1and2K-2, in accordance with some embodiments. The dielectric lining layer148extends below the gate-cut features174, as shown inFIG.2K-2, in accordance with some embodiments.

In some embodiments, the gate-cut features174are made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, another suitable dielectric material, or a combination thereof. In some embodiments, the dielectric material for the gate-cut features174is deposited using such as CVD (such as HDP-CVD, PECVD, or HARP), another suitable technique, and/or a combination thereof. Afterward, a planarization process, e.g., CMP, may be performed on the semiconductor structure12to removes the dielectric material over the upper surface of the interlayer dielectric layer138. The planarization process may also remove the patterned mask layer168. In some embodiments, the upper surfaces of the gate-cut features174, the upper surfaces of the isolation feature146, the upper surface of the interlayer dielectric layer138and the upper surface of the metal gate electrode layer166are substantially coplanar.

The aspect of the embodiments of the present disclosure is direct to a formation method and structures that provide hybrid structures including gate-all-around FETs T1and FinFETs T2formed over the same semiconductor substrate. The hybrid structures also includes the isolation feature146interposing two neighboring gate-all-around FETs T1, and the gate-cut features174interposing a gate-all-around FETs T1and a neighboring FinFET T2, in accordance with some embodiments.

In some instance in which gate-cut features are formed before the dummy gate structures are replaced with final gate stacks, the fill window for a high-k gate dielectric layer and a metal gate electrode layer between the active regions and the gate-cut features may be too small to form a reliable final gate stack, leading to low yield. In some other instances in which the isolation features are formed after the metal gate structures are formed, it can be difficult to etch through the final gate stacks along with the active regions to form the cut trench for isolation features due to etching selectivity difference between various materials (metals, dielectrics, and semiconductors).

The embodiments of the present disclosure provide a method where the isolation feature is formed before the replacement process of the final gate stacks and the gate-cut features are formed after the formation of the final gate stacks. As a result, the method of the embodiments may reduce the difficulty of the etching process for forming the cut trench and enlarge the fill window of metal gate structures thereby improving device performance and production yield. Therefore, the hybrid structure provided by the embodiments of the present disclosure may allow lower processing difficulty and greater design flexibility for integrated circuits including different type of devices, e.g., logic devices, memory devices, etc.

FIG.3is a flowchart of a method1000for forming a semiconductor structure, in accordance with some embodiments of the disclosure. The method1000is used to form the semiconductor structure12as described previously with respect toFIGS.2A to2K-4, in accordance with some embodiments.

In operation1002, a substrate102is provided, as shown inFIG.2A, in accordance with some embodiments. In operation1004, a first epitaxial stack including a first semiconductor layer104and a second semiconductor layer106are formed over the substrate102, as shown inFIG.2A, in accordance with some embodiments. In operation1006, the first epitaxial stack is etched to form a recess108, as shown inFIG.2B, in accordance with some embodiments. In operation1008, a second epitaxial stack including third semiconductor layers110and fourth semiconductor layers112are formed from the recess108, as shown inFIG.2C, in accordance with some embodiments.

In operation1010, a first fin structure118and a second fin structure120are formed, as shown inFIGS.2D-1and2D-2, in accordance with some embodiments. In operation1012, an isolation structure124are formed to surround lower fin elements103of the first fin structure118and the second fin structure120, as shown inFIGS.2E-1to2E-5, in accordance with some embodiments. In operation1014, dummy gate structures126are formed across the first fin structure118and the second fin structure120and gate spacer layers132are formed along the dummy gate structure126, as shown inFIGS.2E-1to2E-5, in accordance with some embodiments. In operation1016, source/drain features134and136are formed over the first fin structure118and the second fin structure120and an interlayer dielectric layer138are formed over the source/drain features134and136, as shown inFIGS.2E-1to2E-5, in accordance with some embodiments.

In operation1018, a cut trench144is formed through the first fin structure118, as shown inFIGS.2F-1to2F-5, in accordance with some embodiments. In operation1020, an isolation feature146is formed in the cut trench144, as shown inFIGS.2G-1to2G-5, in accordance with some embodiments.

In operation1022, the dummy gate structures126are removed and a channel release process is performed to form nanostructures110of the first fin structure118and a floating fin element106of the second fin structure120, as shown inFIGS.2H-1to2H-6, in accordance with some embodiments. In operation1024, inner spacer layers158are formed, as shown inFIGS.2H-1to2H-6, in accordance with some embodiments. In operation1026, final gate stacks160are formed across the nanostructures110and the floating fin element106, as shown inFIGS.2I-1to2I-5, in accordance with some embodiments.

In operation1028, gate-cut openings170are formed through the final gate stacks160, as shown inFIGS.2J-1to2J-4, in accordance with some embodiments. In operation1030, gate-cut features174are formed in the gate-cut openings172, as shown inFIGS.2K-1to2K-4, in accordance with some embodiments.

FIGS.4A-4Dare cross-sectional views illustrating the formation of a cut trench414, in accordance with some embodiments of the disclosure. The cut trench414shown inFIG.4Dmay be similar to the cut trench144shown inFIGS.2F-1to2F-5.

The formation of the cut trench414includes forming a hard mask layer402over the dummy gate electrode layer130and the interlayer dielectric layer (not shown), and forming a tri-layer mask structure over the hard mask layer402, as shown inFIG.4A, in accordance with some embodiments. In some embodiments, the hard mask layer402is made of silicon nitride, silicon oxide, silicon oxynitride and/or a combination thereof. The tri-layer mask includes a bottom layer404, a middle layer406over the bottom layer404, and a top layer408over the middle layer406, in accordance with some embodiments. In some embodiments, the top layer408is made of a photoresist and patterned to have an opening410using a photolithography process. The photolithography process may include resist coating (for example, spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the resist, rinsing, drying (for example, hard baking), other suitable processes, or combinations thereof. In some embodiments, the middle layer406is made of an inorganic material, and the bottom layer404is a Si-doped bottom anti-reflective coating (BARC) layer.

An etching process is performed to remove portions of the middle layer406, the bottom layer404and the hard mask layer402below the opening412to form an opening410, as shown inFIG.4B; remove the tri-layer mask, as shown inFIG.4C; and remove portions of the dummy gate electrode layer130and the dummy gate dielectric layer128uncovered by the patterned hard mask layer402to form a cut trench414, as shown inFIG.4D, in accordance with some embodiments.

The etching process may be performed in a plasma etch chamber such as a Kiyo etcher available from Lam Research Corp., Fremont, Calif. The plasma etch chamber may be performed with a pulsed plasma mode including a pulse-on and a pulse-off time period. The proportion of the pulse-on time period may be defined as a duty cycle. The steps of the etching process includes: (1) a de-scum step in which the photoresist material remaining in the opening410after the photolithography process performed on the top layer408is cleaned to completely expose the middle layer406; (2) a middle-layer open step in which the middle layer406is etched; (3) a bottom-layer open step in which the bottom layer404is etched; (4) a hard-mask open step in which the hard mask layer402is etched; (5) a strip step in which the top layer408, the middle layer406and the bottom layer404are removed to expose the hard mask layer402; (6) an oxide break-through step in which a native oxide layer formed on the dummy gate electrode layer130is removed; (7) a main etching step in which the dummy gate electrode layer130, the dummy gate dielectric layer128and the first fin structure118(including the third semiconductor layer110, the fourth semiconductor layer112and the lower fin element103) are etched; (8) an over-etching step in which the cut trench414is controlled to stop at a desired depth; (9) an ashing step in which residues, polymers and/or byproducts are removed from the semiconductor structure, in accordance with some embodiments.

During the de-scum step, the etching chamber provides a bias voltage in a range from about 60 volts (V) to about 360 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from 100 watts (W) to about 600 W, in accordance with some embodiments. The de-scum step uses CF4with a flow rate in a range from about 50 standard cubic centimeter per minute (sccm) to about 300 sccm and Ar with a flow rate in a range from about 50 sccm to about 300 sccm as etching precursors, and is performed at a pressure of about 1.5 mTorr to about 9 mTorr for a duration of about 4 seconds to about 24 seconds.

During the middle-layer open step, the etching chamber provides a bias voltage in a range from about 200 V to about 1200 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 400 W to about 2400 W, in accordance with some embodiments. The middle-layer open step uses CH2F2with a flow rate in a range from about 12.5 sccm to about 75 sccm, CF4with a flow rate in a range from about 37.5 sccm to about 225 sccm, and O2with a flow rate in a range from about 1.5 sccm to about 9 sccm as etching precursors, and is performed at a pressure of about 5 mTorr to about 30 mTorr for a duration of about 15 seconds to about 90 seconds.

During the bottom-layer open step, the etching chamber provides a bias voltage in a range from about 100 V to about 600 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 500 W to about 3000 W, in accordance with some embodiments. The bottom-layer open step uses SO2with a flow rate in a range from about 50 sccm to about 300 sccm, O2with a flow rate in a range from about 12.5 sccm to about 75 sccm and He with a flow rate in a range from about 100 sccm to about 600 sccm as etching precursors, and is performed at a pressure of about 3.5 mTorr to about 21 mTorr for a duration of about 22.5 seconds to about 135 seconds.

During the hard-mask open step, the etching chamber provides a bias voltage in a range from about 200 V to about 1200 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 400 W to about 2400 W, in accordance with some embodiments. The hard-mask open step uses CHF3with a flow rate in a range from about 50 sccm to about 300 sccm, O2with a flow rate in a range from about 2.5 sccm to about 15 sccm and He with a flow rate in a range from about 100 sccm to about 600 sccm as etching precursors, and is performed at a pressure of about 2.5 mTorr to about 15 mTorr for a duration of about 10 seconds to about 60 seconds.

During the strip step, the etching chamber provides a bias voltage in a range from about 15 V to about 90 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 500 W to about 3000 W, in accordance with some embodiments. The strip step uses O2with a flow rate in a range from about 10 sccm to about 60 sccm as etching precursors, and is performed at a pressure of about 5 mTorr to about 30 mTorr for a duration of about 15 seconds to about 90 seconds.

During the oxide break-through step, the etching chamber provides a bias voltage in a range from about 30 V to about 180 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 150 W to about 900 W, in accordance with some embodiments. The oxide break-through step uses CF4with a flow rate in a range from about 10 sccm to about 60 sccm and Ar with a flow rate in a range from about 20 sccm to about 120 sccm as etching precursors, and is performed at a pressure of about 2.5 mTorr to about 15 mTorr for a duration of about 7.5 seconds to about 45 seconds.

During the main etching step, the etching chamber provides a bias voltage in a range from about 350 V to about 2100 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 700 W to about 4200 W, in accordance with some embodiments. The main etching step uses HBr with a flow rate in a range from about 150 sccm to about 900 sccm, O2with a flow rate in a range from about 5 sccm to about 30 sccm and He with a flow rate in a range from about 400 sccm to about 2400 sccm as etching precursors, and is performed at a pressure of about 40 mTorr to about 240 mTorr for a duration of about 30 seconds to about 180 seconds.

During the over-etching step, the etching chamber provides a bias voltage in a range from about 700 V to about 4200 V with a duty cycle in a range from 5% to about 8%, and an RF source power in a range from about 200 W to about 1200 W, in accordance with some embodiments. The over-etching step uses SiCH4with a flow rate in a range from about 2.5 sccm to about 15 sccm, N2with a flow rate in a range from about 25 sccm to about 150 sccm, O2with a flow rate in a range from about 25 sccm to about 150 and Cl2with a flow rate in a range from about 150 sccm to about 900 sccm as etching precursors, and is performed at a pressure of about 40 mTorr to about 240 mTorr for a duration of about 30 seconds to about 180 seconds. The duty cycle of the over-etching step is much lower than the duty cycle of the main etching step such that the etching is precisely controlled to extend the cut trench414to the desired depth, e.g., into substrate102.

During the ashing step, the etching chamber provides a bias voltage in a range from about 15 V to about 90 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 500 W to about 3000 W, in accordance with some embodiments. The ashing step uses O2with a flow rate in a range from about 10 sccm to about 60 sccm, and is performed at a pressure of about 5 mTorr to about 30 mTorr for a duration of about 15 seconds to about 90 seconds.

In some embodiments, the steps of the etching process are performed in situ in the same etching chamber to prevent the semiconductor structure from being exposed to an oxygen-containing ambient. After the etching process, the semiconductor structure may be cleaned using a sulfuric acid peroxide mixture (SPM, H2SO4+H2O2) and/or dilute hydrofluoric (dHf) acid.

FIGS.5A-5Dare cross-sectional views illustrating the formation of gate-cut openings518, in accordance with some embodiments of the disclosure. The gate-cut openings518shown inFIG.5Dmay be similar to the gate-cut openings172shown inFIGS.2J-1to2J-4.

The formation of the gate-cut openings518includes forming a metal protection layer502over the metal gate electrode layer166, the isolation feature146and the interlayer dielectric layer (not shown), forming a hard mask layer504over the metal protection layer502, and forming a tri-layer mask structure over the hard mask layer504, as shown inFIG.5A, in accordance with some embodiments. In some embodiments, the metal protection layer502protects the metal gate electrode material from being oxidized and is made of TiN. In some embodiments, the hard mask layer504is made of silicon nitride, silicon oxide, silicon oxynitride and/or a combination thereof. The tri-layer mask includes a bottom layer506, a middle layer508over the bottom layer506, and a top layer510over the middle layer508, in accordance with some embodiments. In some embodiments, the top layer510is made of a photoresist and patterned to have opening512; the middle layer508includes an inorganic material; and the bottom layer506is a Si-doped bottom anti-reflective coating layer.

A first etching process is performed to remove portions of the middle layer508, the bottom layer506and the hard mask layer504below the open512to form openings514, as shown inFIG.5B, in accordance with some embodiments.

The first etching process may be performed in a plasma etch chamber such as a Kiyo etcher. The steps of the first etching process includes: (1) a de-scum step in which the photoresist material remaining in the openings512after the photolithography process performed on the top layer510is cleaned to completely expose the middle layer508; (2) a middle-layer open step in which the middle layer508is etched; (3) a bottom-layer open step in which the bottom layer506is etched; (4) a hard-mask open step in which the hard mask layer504is etched to expose the metal protection layer502, in accordance with some embodiments.

During the de-scum step, the etching chamber provides a bias voltage in a range from about 60V to about 360 v with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from 100 W to about 600 W, in accordance with some embodiments. The de-scum step uses CF4with a flow rate in a range from about 50 sccm to about 300 sccm and Ar with a flow rate in a range from about 50 sccm to about 300 sccm as etching precursors, and is performed at a pressure of about 1.5 mTorr to about 9 mTorr for a duration of about 4 seconds to about 24 seconds.

During the middle-layer open step, the etching chamber provides a bias voltage in a range from about 200 V to about 1200 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 400 W to about 2400 W, in accordance with some embodiments. The middle-layer open step uses CH2F2with a flow rate in a range from about 12.5 sccm to about 75 sccm, CF4with a flow rate in a range from about 37.5 sccm to about 225 sccm, and O2with a flow rate in a range from about 1.5 sccm to about 9 sccm as etching precursors, and is performed at a pressure of about 5 mTorr to about 30 mTorr for a duration of about 15 seconds to about 90 seconds.

During the bottom-layer open step, the etching chamber provides a bias voltage in a range from about 100 V to about 600 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 500 W to about 3000 W, in accordance with some embodiments. The bottom-layer open step uses SO2with a flow rate in a range from about 50 sccm to about 300 sccm, O2with a flow rate in a range from about 12.5 sccm to about 75 sccm and He with a flow rate in a range from about 100 sccm to about 600 sccm as etching precursors, and is performed at a pressure of about 3.5 mTorr to about 21 mTorr for a duration of about 22.5 seconds to about 135 seconds.

During the hard-mask open step, the etching chamber provides a bias voltage in a range from about 200 V to about 1200 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 400 W to about 2400 W, in accordance with some embodiments. The hard-mask open step uses CHF3with a flow rate in a range from about 50 sccm to about 300 sccm, O2with a flow rate in a range from about 2.5 sccm to about 15 sccm and He with a flow rate in a range from about 100 sccm to about 600 sccm as etching precursors, and is performed at a pressure of about 2.5 mTorr to about 15 mTorr for a duration of about 25 seconds to about 150 seconds.

In some embodiments, the first etching process further includes a strip step after the hard-mask open step to remove to the tri-layer mask. In some embodiments, the steps of the first etching process described above are performed in situ in the same etching chamber. After the first etching process, the semiconductor structure may be cleaned using a sulfuric acid peroxide mixture and/or dilute hydrofliuric (dHf).

Because the vertical etching and the lateral etching occur concurrently during the first etching process, the openings514may be enlarged to have a greater critical dimension (CD) than the target critical dimension. In some embodiments, a dielectric layer516is conformally formed over the semiconductor structure to partially fills the opening514to recover the enlarged critical dimension of the opening514, as shown inFIG.5C, in accordance with some embodiments. The openings514after partially filled with the dielectric layer516are denoted as openings514′. In some embodiments, the dielectric layer516is made of the same material as the hard mask layer504, e.g., SiN.

A second etching process is performed to remove portions of the dielectric layer516, the metal gate electrode layer166and the high-k gate dielectric layer164below the opening514′ to form gate-cut openings518, as shown inFIG.5D, in accordance with some embodiments. In some embodiments, the second etching process may also remove portions of the isolation feature146below the opening514′.

The second etching process may be performed in a plasma etch chamber such as a Kiyo etcher. The steps of the second etching process includes: (1) a hard-mask open step in which the dielectric layer516is etched; (2) a protection-layer open step in which the metal protection layer502is etched; (3)-(6) first, second, third, and fourth main etching steps in which the gate electrode layer166and the high-k gate dielectric layer164are etched and the gate-cut openings518is controlled to stop at a desired depth. The first, second, third, and fourth main etching steps may be used to remove different materials of the final gate stack (such as metals, metal nitrides, high-k dielectrics, etc.) and may be repeated several times.

During the hard-mask open step, the etching chamber provides a bias voltage in a range from about 200 V to about 1200 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 400 W to about 2400 W, in accordance with some embodiments. The hard-mask open step uses CHF3with a flow rate in a range from about 50 sccm to about 300 sccm, O2with a flow rate in a range from about 2.5 sccm to about 15 sccm and He with a flow rate in a range from about 100 sccm to about 600 sccm as etching precursors, and is performed at a pressure of about 2.5 mTorr to about 15 mTorr for a duration of about 7.5 seconds to about 45 seconds.

During the protection-layer open step, the etching chamber provides a bias voltage in a range from about 100 V to about 600 V with a duty cycle in a range from 95% to about 100%, and an RF source power in a range from about 400 W to about 2400 W, in accordance with some embodiments. The protection-layer open step uses Cl2with a flow rate in a range from about 50 sccm to about 300 sccm, BCl3with a flow rate in a range from about 10 sccm to about 60 sccm and Ar with a flow rate in a range from about 10 sccm to about 10000 sccm as etching precursors, and is performed at a pressure of about 1.5 mTorr to about 9 mTorr for a duration of about 7.5 seconds to about 45 seconds.

During the first main etching step, the etching chamber provides a bias voltage in a range from about 150 V to about 900 V with a duty cycle in a range from 45% to about 55%, and an RF source power in a range from about 600 W to about 3600 W, in accordance with some embodiments. The first main etching step uses Cl2with a flow rate in a range from about 50 sccm to about 300 sccm, BCl3with a flow rate in a range from about 10 sccm to about 60 sccm and Ar with a flow rate in a range from about 10 sccm to about 10000 sccm as etching precursors, and is performed at a pressure of about 15 mTorr to about 90 mTorr for a duration of about 5 seconds to about 30 seconds.

During the second main etching step, the etching chamber provides a bias voltage in a range from about 300 V to about 1800 V with a duty cycle in a range from 45% to about 55%, and an RF source power in a range from about 600 W to about 3600 W, in accordance with some embodiments. The second main etching step uses Cl2with a flow rate in a range from about 50 sccm to about 300 sccm, BCl3with a flow rate in a range from about 10 sccm to about 60 sccm and Ar with a flow rate in a range from about 10 sccm to about 10000 sccm as etching precursors, and is performed at a pressure of about 30 mTorr to about 180 mTorr for a duration of about 7.5 seconds to about 45 seconds.

During the third main etching step, the etching chamber provides a bias voltage in a range from about 150 V to about 900 V with a duty cycle in a range from 45% to about 55%, and an RF source power in a range from about 600 W to about 3600 W, in accordance with some embodiments. The third main etching step uses Cl2with a flow rate in a range from about 50 sccm to about 300 sccm, BCl3with a flow rate in a range from about 10 sccm to about 60 sccm and Ar with a flow rate in a range from about 10 sccm to about 10000 sccm as etching precursors, and is performed at a pressure of about 15 mTorr to about 90 mTorr for a duration of about 5 seconds to about 30 seconds.

During the fourth main etching step, the etching chamber provides a bias voltage in a range from about 300 V to about 1800 V with a duty cycle in a range from 5% to about 20%, and an RF source power in a range from about 600 W to about 3600 W, in accordance with some embodiments. The fourth main etching step uses Cl2with a flow rate in a range from about 50 sccm to about 300 sccm, BCl3with a flow rate in a range from about 10 sccm to about 60 sccm and Ar with a flow rate in a range from about 10 sccm to about 10000 sccm as etching precursors, and is performed at a pressure of about 30 mTorr to about 180 mTorr for a duration of about 7.5 seconds to about 45 seconds. The duty cycle of the fourth main etching step is much lower than the duty cycle of the first, second and third etching steps such that the etching is precisely controlled to extend the gate-cut openings518to the desired depth.

The second etching process may further include an ashing step after the fourth main etching step of the last cycle to remove residues, polymers and/or byproducts from the semiconductor structure. In some embodiments, the steps of the second etching are performed in situ in the same etching chamber. After the second etching process, the semiconductor structure may be cleaned using dilute hydrofluoric acid and/or ammonia hydroxide-hydrogen peroxide-water mixture (standard clean1).

FIG.6-1is a top view of a semiconductor structure14which is a modification of the semiconductor structure12ofFIG.2K-1, in accordance with some embodiments of the disclosure.FIGS.6-2and6-3are cross-sectional views taken along line Y1-Y1and line X3-X3inFIG.6-1. The semiconductor structure14is similar to the semiconductor structure12except that an isolation feature146is formed through the second fin structure120, in accordance with some embodiments.

After operation1016, a cut trench (not shown) is formed through the dummy gate structure1263and the second fin structure120, and an isolation feature146is formed in the cut trench, in accordance with some embodiments. The cut trench (or isolation feature146) corresponds to a cross point of the dummy gate structure1263and the second fin structure120so as to cut the dummy gate structure (not shown) into two segments and the second fin structure120into two segments, in accordance with some embodiments. The cut trench may be formed using the steps as described with respect toFIGS.4A to4D. After operations1022-1030are performed, the isolation feature146is located between and electrically isolates two FinFETs T2, as shown inFIGS.6-1and6-3, in accordance with some embodiments.

In addition, portions of the second fin structure120adjacent to the isolation feature146are covered by the gate spacer layers132during the etching process for forming the cut trench and remain unetched, in accordance with some embodiments. The respective unetched portions of the second semiconductor layer106, the first semiconductor layer104and the low fin element103of the second fin structure120are denoted as a second semiconductor layer106′, a first semiconductor layer104′ and a low fin element103′ respectively, which collectively form a semiconductor stack adjacent to the isolation feature146, as shown inFIG.6-3, in accordance with some embodiments. The semiconductor stack including the second semiconductor layer106′, the first semiconductor layer104′ and the low fin element103′ is located between the source/drain features136of the FinFETs T2and the isolation feature146, as shown inFIG.6-3, in accordance with some embodiments.

FIG.7-1is a top view of a semiconductor structure16which is a modification of the semiconductor structure12ofFIG.2K-1, in accordance with some embodiments of the disclosure.FIGS.7-2to7-4are cross-sectional views taken along line Y1-Y1, line X2-X2and line X3-X3inFIG.6-1. The semiconductor structure16is similar to the semiconductor structure12except that an isolation feature146is formed through both the first fin structures118and the second fin structure120, in accordance with some embodiments.

After operation1016, a cut trench (not shown) is formed through the dummy gate structure1263and the fin structures118and120, and an isolation feature146is formed in the cut trench, in accordance with some embodiments. The cut trench (or isolation feature146) cut the dummy gate structure (not shown) into two segments, the first fin structure118into two segments, and the second fin structure120into two segments, in accordance with some embodiments. The cut trench may be formed using the steps as described with respect toFIGS.4A to4D. After operations1022-1030are performed, the isolation feature146is located between two gate-all-around FETs T1and between two FinFETs T2, as shown inFIGS.7-1,7-3and7-4, in accordance with some embodiments.

FIGS.8-1,9-1and10-1are top views of semiconductor structures18,20and22which are modifications of the semiconductor structures12,14and16ofFIGS.2K-1,6-1and7-1respectively, in accordance with some embodiments of the disclosure.FIGS.8-2,9-2and10-2are cross-sectional views taken along lines Y1-Y1inFIGS.8-1,9-1and10-1. The semiconductor structure18,20and22are similar to the semiconductor structures12,14and16respectively, except that no gate-cut openings formed adjacent to the isolation feature146, in accordance with some embodiments. As a result, the high-k gate dielectric layer164of the final gate stack1603is formed along and contacts the dielectric lining layer148of the isolation feature146, in accordance with some embodiments.

FIGS.11-1,12-1and13-1are top views of semiconductor structures24,26and28which are modifications of the semiconductor structures18,20and22ofFIGS.8-1,9-1and10-1respectively, in accordance with some embodiments of the disclosure.FIGS.11-2,12-2and13-2are cross-sectional views taken along lines Y1-Y1inFIGS.11-1,12-1and13-1. The semiconductor structure24,26and28are similar to the semiconductor structures18,20and22respectively, except that the high-k gate dielectric layer164of the final gate stack1603is formed along and contacts both the dielectric lining layer148and the dielectric fill layer150of the isolation feature146, in accordance with some embodiments. This is because during operation1022, portions of the dielectric lining layer148contacting the dummy gate structure1263are also removed thereby exposing the dielectric fill layer150from the gate trench1523, in accordance with some embodiments.

FIGS.14-1,15-1and16-1are top views of semiconductor structures30,32and34which are modifications of the semiconductor structures12,14and16ofFIGS.2K-1,6-1and7-1respectively, in accordance with some embodiments of the disclosure.FIGS.14-2,15-2and16-2are cross-sectional views taken along lines Y1-Y1inFIGS.14-1,15-1and16-1. The semiconductor structure30,32and34are similar to the semiconductor structures12,14and16respectively, except that gate-cut features174A adjacent to the isolation feature146are shorter in length along Y direction as compared to gate-cut features174not adjacent to the isolation feature146, in accordance with some embodiments. This is because during operation1028, portions of the dielectric lining layer148contacting the final gate stack1603remain unetched, in accordance with some embodiments. In addition,FIG.14-1illustrates that the final gate stack1604is not cut by the gate-cut feature174.FIG.14-3is a cross-sectional view taken along lines Y2-Y2inFIG.14-1, in accordance with some embodiments. In some embodiments, the final gate stack1604continuously extends and wraps around the nanostructure110of the first fin structure118and the second fin structure120, as shown inFIGS.14-1and14-3. That is, the gate-all-around FET T1and the FinFET T2share a continuous final gate stack1604.

FIGS.17-1,18-1and19-1are top views of semiconductor structures36,38and40which are modifications of the semiconductor structures30,32and34ofFIGS.14-1,15-1and16-1respectively, in accordance with some embodiments of the disclosure.FIGS.17-2,18-2and19-2are cross-sectional views taken along lines Y1-Y1inFIGS.17-1,18-1and19-1. The semiconductor structure36,38and40are similar to the semiconductor structures30,32and34respectively, except that the gate-cut features174A contacts both the dielectric lining layer148and the dielectric fill layer150of the isolation feature146, in accordance with some embodiments. This is because during operation1028, portions of the dielectric lining layer148contacting the final gate stack1603are removed while the dielectric fill layer150remains unetched, in accordance with some embodiments.

FIGS.20-1,21-1and22-1are top views of semiconductor structures42,44and46which are modifications of the semiconductor structures12,14and16ofFIGS.2K-1,6-1and7-1respectively, in accordance with some embodiments of the disclosure.FIGS.20-2,21-2and22-2are cross-sectional views taken along lines Y1-Y1inFIGS.20-1,21-1and22-1. The semiconductor structure42,44and46are similar to the semiconductor structures12,14and16respectively, except that gate-cut features174B adjacent to the isolation feature146are longer in length along Y direction as compared to gate-cut features174not adjacent to the isolation feature146, in accordance with some embodiments. This is because during operation1028, the dielectric lining layer148and the dielectric fill layer150suffer more lateral etching.

As described above, the semiconductor structure includes a hybrid structure including first and second gate-all-around FETs T1and a FinFET T2over the same substrate102. The first gate-all-around FET T1includes first nanostructures110and a first gate stack160wrapping around the nanostructures110. The second gate-all-around FET T1includes second nanostructures110and a second gate stack160wrapping around the nanostructures110. An isolation feature146interposes the first nanostructures110of the first gate-all-around FET T1and the second nanostructures110of the second gate-all-around FET T1. The FinFET T2includes a floating fin element106and a third gate stack160over the floating fin element106. A first gate-cut feature174interposes the isolation feature146and the third gate stack160of the first FinFET T2. Therefore, the hybrid structure may allow lower processing difficulty and greater design flexibility for integrated circuits (ICs) including different type of devices.

In addition, the method for forming the semiconductor structure includes forming the isolation feature146before a dummy gate structure126is replaced with a final gate stack160, and forming the gate-cut feature174after the final gate stack160is formed. As a result, the method of the embodiments may reduce the difficulty of the etching process for forming the cut trench and enlarge the fill window of metal gate structures thereby improving device performance and production yield.

Embodiments of a semiconductor structure may be provided. The semiconductor structure may include a first gate-all-around FET and a first FinFET adjacent to the first gate-all-around FET. The first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The first FinFET includes a first floating fin element and a second gate stack over the first floating fin element. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET. Therefore, lower processing difficulty and greater design flexibility for integrated circuits (ICs) including different type of devices may be achieved by the semiconductor structure of the embodiments of the present disclosure.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack wrapping around the first nanostructures. The semiconductor structure also includes a second gate-all-around FET over the substrate, and the second gate-all-around FET includes second nanostructures and a second gate stack wrapping around the second nanostructures. The semiconductor structure also includes an isolation feature interposing the first nanostructures of the first gate-all-around FET and the second nanostructures of the second gate-all-around FET. The semiconductor structure also includes a first FinFET over the substrate, and the first FinFET includes a first fin structure and a third gate stack over the first fin structure. The semiconductor structure also includes a first gate-cut feature interposing the first gate stack of the first gate-all-around FET and the third gate stack of the first FinFET.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first lower fin element extending in a first direction, a set of nanostructures vertically stack over the first lower fin element and spaced apart from one another, a first gate stack wrapping around the set of nanostructures, a source/drain feature over the first lower fin element and adjoining the set of nanostructures, an isolation feature laterally spaced apart from the source/drain feature and vertically passing through the first lower fin element, and a semiconductor stack between the source/drain feature and the isolation feature. The semiconductor stack includes alternatingly stacking first semiconductor layers and second semiconductor layers.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.