Patent ID: 12243754

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments according to the technical idea of the present invention will be described referring to the accompanying drawings. In the description ofFIGS.1to40, the same reference numerals are used for substantially the same components, and repeated description of the components will not be provided. Also, similar reference numerals are used for similar components throughout various drawings of the present invention.

Although the drawings of a semiconductor device according to some embodiments show a fin-type transistor (FinFET) including a channel region of a fin-type pattern shape, a planar transistor, a transistor including a nanowire or a nanosheet, and a MBCFET™ (Multi-Bridge Channel Field Effect Transistor) as examples, the embodiments are not limited thereto. For example, the semiconductor device according to some embodiments may include a tunneling FET or a three-dimensional (3D) transistor. In certain embodiments, the technical idea of the present invention may be applied to a transistor based on two-dimensional material (2D material based FETs) and a heterostructure thereof.

Further, the semiconductor device according to some embodiments may also include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS), or the like.

FIG.1is a layout diagram for explaining the semiconductor device according to some embodiments.FIGS.2and3are exemplary cross-sectional views taken along A-A ofFIG.1.FIGS.4to8are cross-sectional views taken along B-B, C-C, D-D, E-E, and F-F ofFIG.1, respectively. Referring toFIGS.1to8, the semiconductor device according to some embodiments may include a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, a plurality of first gate electrodes120, a plurality of second gate electrodes220, and a first gate separation structure160.

The substrate100may be a silicon substrate or an SOI (silicon-on-insulator). In contrast, although the substrate100may be a silicon substrate or may include, but is not limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide or gallium antimonide.

The first active pattern AP1, the second active pattern AP2, and the third active pattern AP3may be placed on the substrate100. The first active pattern AP1, the second active pattern AP2, and the third active pattern AP3may each extend lengthwise in a first direction D1.

An item, layer, or portion of an item or layer described as extending “lengthwise” in a particular direction has a length in the particular direction and a width perpendicular to that direction, where the length is greater than the width.

The first active pattern AP1, the second active pattern AP2, and the third active pattern AP3may be placed apart from each other in a second direction D2. For example, the first direction D1is a direction that intersects the second direction D2. For example, the first direction D1may be perpendicular to the second direction D2. The first active pattern AP1may be placed between the second active pattern AP2and the third active pattern AP3. The first active pattern AP1is adjacent to the second active pattern AP2and the third active pattern AP3in the second direction D2.

The first active pattern AP1and the third active pattern AP3may be placed between first gate separation structures160which extend lengthwise in the first direction D1. The first gate separation structure160may be placed between the first active pattern AP1and the second active pattern AP2. The features of the first gate separation structure160will be described below.

For example, the first active pattern AP1and the third active pattern AP3may be an active region included in a single standard cell. As an example, the first active pattern AP1may be a region in which PMOS is formed, and the third active pattern AP3may be a region in which NMOS is formed. As another example, the first active pattern AP1may be a region in which NMOS is formed and the third active pattern AP3may be a region in which PMOS is formed.

For example, the second active pattern AP2may be a region in which a transistor of the same conductivity type as that of the first active pattern AP1is formed. As an example, when the first active pattern AP1is a region in which PMOS is formed, the second active pattern AP2may be a region in which PMOS is formed. As another example, when the first active pattern AP1is a region in which NMOS is formed, the second active pattern AP2may be a region in which NMOS is formed.

The first active pattern AP1may include a first lower pattern110, and a plurality of first sheet patterns NS1. The second active pattern AP2may include a second lower pattern210and a plurality of second sheet patterns NS2. The third active pattern AP3may include a third lower pattern310and a plurality of third sheet patterns NS3.

The first lower pattern110, the second lower pattern210, and the third lower pattern310may each protrude from the substrate100. The first lower pattern110, the second lower pattern210, and the third lower pattern310may each extend lengthwise in the first direction D1.

The first lower pattern110may be spaced apart from the second lower pattern210and the third lower pattern310in the second direction D2. Each of the first lower pattern110, the second lower pattern210, and the third lower pattern310may be separated by a fin trench FT extending in the first direction D1.

A plurality of first sheet patterns NS1may be placed on the first lower pattern110. The plurality of first sheet patterns NS1may be spaced apart from the first lower pattern110in a third direction D3. The plurality of first sheet patterns NS1spaced apart from each other in the third direction D3may be arranged in the first direction D1along an upper surface of the first lower pattern110, e.g., as shown inFIGS.2and3. Although not shown in the drawings, the description of the third sheet patterns NS3may be substantially the same as the description of the first sheet patterns NS1. For example, the third sheet patterns NS3may have the same structure/shape as the first sheet patterns NS1.

Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

The plurality of second sheet patterns NS2may be placed on the second lower pattern210. The plurality of second sheet patterns NS2may be spaced apart from the second lower pattern210in the third direction D3. A plurality of second sheet patterns NS2spaced apart from each other in the third direction D3may be arranged in the first direction D1along the upper surface of the second lower pattern210.

Each first sheet pattern NS1may include a plurality of nanosheets sequentially placed in the third direction D3. Each second sheet pattern NS2may include a plurality of nanosheets sequentially placed in the third direction D3. Each third sheet pattern NS3may include a plurality of nanosheets sequentially placed in the third direction D3. Here, the third direction D3may be a direction that intersects the first direction D1and the second direction D2. For example, the third direction D3may be perpendicular to the first direction D1and the second direction D2. For example, the third direction D3may be a thickness direction of the substrate100.

InFIGS.2,3,4,5A and7, although each of the three first sheet patterns NS1, the three second sheet patterns NS2and the three third sheet patterns NS3is shown as being placed in the third direction D3, this is merely for convenience of explanation, and the embodiment is not limited thereto.

Each of the first lower pattern110, the second lower pattern210, and the third lower pattern310may be formed by etching a part of the substrate100, and may include an epitaxy layer that is grown from the substrate100. Each of the first lower pattern110, the second lower pattern210, and the third lower pattern310may include silicon or germanium, which is an elemental semiconductor material. Further, each of the first lower pattern110, the second lower pattern210and the third lower pattern310may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The group IV-IV compound semiconductor may include, for example, a binary compound or a ternary compound containing at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with a group IV element.

The group III-V compound semiconductor may be, for example, at least one of a binary compound, a ternary compound or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga) and indium (In) as a group III element with one of phosphorus (P), arsenic (As) and antimony (Sb) as a group V element.

Each first sheet pattern NS1may include one of silicon or germanium which is an elemental semiconductor material, a group IV-IV compound semiconductor or a group III-V compound semiconductor. Each second sheet pattern NS2may include one of silicon or germanium which is an elemental semiconductor material, a group IV-IV compound semiconductor or a group III-V compound semiconductor. Each third sheet pattern NS3may include one of silicon or germanium which is an elemental semiconductor material, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

For example, a width of the first sheet pattern NS1in the second direction D2may increase or decrease in proportion to a width of the first lower pattern110in the second direction D2.

A field insulating film105may be formed on the substrate100. The field insulating film105may fill at least a part of the fin trench FT. The field insulating film105may be placed between the first active pattern AP1and the second active pattern AP2, and between the first active pattern AP1and the third active pattern AP3.

The field insulating film105may cover the side wall of the first lower pattern110, the side wall of the second lower pattern210, and the side wall of the third lower pattern310. Unlike that shown in the drawings, a part of the first lower pattern110, a part of the second lower pattern210, and a part of the third lower pattern310may protrude in the third direction D3from an upper surface105US of the field insulating film105.

Each first sheet pattern NS1, each second sheet pattern NS2, and each third sheet pattern NS3are placed higher than the upper surface105US of the field insulating film105. The field insulating film105may include or be formed of, for example, an oxide film, a nitride film, an oxynitride film or a combination film thereof.

A plurality of first gate structures GS1may be placed on the substrate100. The plurality of first gate structures GS1may be placed between the first gate separation structures160which extend lengthwise in the first direction D1. Each first gate structure GS1may extend lengthwise in the second direction D2. Adjacent first gate structures GS1may be spaced apart from each other in the first direction D1.

The first gate structure GS1may be placed on the first active pattern AP1and the third active pattern AP3. The first gate structure GS1may intersect the first active pattern AP1and the third active pattern AP3, e.g., in a plan view. For example, each first gate structure GS1may cross the first active pattern AP1and the third active pattern AP3.

The plurality of second gate structures GS2may be placed on the substrate100. Each second gate structure GS2may extend lengthwise in the second direction D2. Adjacent second gate structures GS2may be spaced apart from each other in the first direction D1. A first gate structure GS1and A second gate structure GS2corresponding to each other may face each other with the first gate separation structure160interposed therebetween. For example, the first gate structure GS1and the second gate structure GS2corresponding to each other may be arranged in the second direction D2. For example, side surfaces of the first gate structure GS1and the second gate structure GS2corresponding to each other may be coplanar.

The second gate structure GS2may be placed on the second active pattern AP2. The second gate structure GS2may intersect the second active pattern AP2, e.g., in a plan view. For example, each second gate structure GS2may cross the second active pattern AP2.

The first gate structure GS1may include, for example, a first gate electrode120, a first gate insulating film130, a first gate spacer140and a first gate capping pattern145. The second gate structure GS2may include, for example, a second gate electrode220, a second gate insulating film230, a second gate spacer240, and a second gate capping pattern245.

The first gate electrode120may be formed on the first lower pattern110and the third lower pattern310. The first gate electrode120may intersect the first lower pattern110and the third lower pattern310, e.g., in a plan view. For example, the first gate electrode120may cross the first lower pattern110and the third lower pattern310. The first gate electrode120may wrap/surround the first sheet patterns NS1and the third sheet patterns NS3.

The second gate electrode220may be formed on the second lower pattern210. The second gate electrode220may intersect the second lower pattern210, e.g., in a plan view. For example, the second gate electrode220may cross the second lower pattern210. The second gate electrode220may wrap/surround the second sheet patterns NS2.

Although the first gate electrode120and the second gate electrode220are shown as a single metal layer in the drawings, they may be implemented as a plurality of metal layers, without being limited thereto.

Each of the first gate electrode120and the second gate electrode220may include or be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide and a conductive metal oxynitride. The first gate electrode120and the second gate electrode220may include, but are not limited to, for example, at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof. The conductive metal oxide and the conductive metal oxynitride may include, but are not limited to, an oxidized form of the above-mentioned materials.

Although four first gate electrodes120and four second gate electrodes220are shown in the drawings, this is merely for convenience of explanation, and the number thereof is not limited thereto. The numbers of the first gate electrodes120and the second gate electrodes220may be larger or smaller than four.

An upper surface120US of the first gate electrode120and an upper surface220US of the second gate electrode220may have the same height from a top surface of the substrate100. For example, the top surface of the substrate100may correspond to a bottom surface of the field insulating film105, a bottom of the first lower pattern110and/or a bottom of the second lower pattern210. For example, a height in this description may refer to a distance in the third direction D3from a horizontal plane/surface or from a reference point. For example, since the upper surface of the region adjacent to the first gate separation structure160has a flat/planar shape, a height h3of the upper surface120US of the first gate electrode120and the upper surface220US of the second gate electrode220may be the same. For example, the upper surface120US of the first gate electrode120and the upper surface220US of the second gate electrode220may be coplanar.

At the same height from the top surface of the substrate100, a width W11, in the second direction D2, of the first gate electrode120placed between the first sheet pattern NS1and the gate separation structure160is the same as a width W21, in the second direction D2, of the second gate electrode220placed between the second sheet pattern NS2and the gate separation structure160. This structure is a structure formed by a process according to an embodiment illustrated inFIG.29, which will be described below.

The first gate insulating film130may extend along the upper surface105US of the field insulating film105, the upper surface of the first lower pattern110, the upper surface of the third lower pattern310, and the side wall of the first gate separation structure160. The first gate insulating film130may wrap/surround the first sheet patterns NS1and the third sheet patterns NS3. The first gate insulating film130may be placed along the periphery of the first sheet patterns NS1and the periphery of the third sheet patterns NS3. The first gate electrode120is placed on the first gate insulating film130. For example, the first gate insulating film130may contact a bottom surface and side surfaces of the first gate electrode120.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

The first gate insulating film130may be placed and/or contact only on the upper surface of a part of the side wall of the first gate separation structure160, and may not be placed on a part of the side wall. For example, the first gate insulating film130may be placed on and/or contact a side wall of a first dam structure163to be described below, and may not be placed on a side wall of a gate separation filling film162.

A height h1of the first gate insulating film130may be placed between a height h2of uppermost surfaces of the first sheet patterns NS1and the second sheet patterns NS2, and a height h3of upper surfaces of the first gate electrode120and the second gate electrode220. For example, the height of the first gate insulating film130is higher than the height h2of the uppermost surfaces of the first sheet patterns NS1and the second sheet patterns NS2, and is lower than the height h3of the upper surfaces of the first gate electrode120and the second gate electrode220.

The second gate insulating film230may extend along the side wall of the first gate separation structure160, the upper surface105US of the field insulating film, and the upper surface of the second lower pattern210. The second gate insulating film230may wrap/surround the second sheet patterns NS2. The second gate insulating film230may be placed along the periphery of the second sheet patterns NS2. The second gate electrode220may be placed on the second gate insulating film230. For example, a bottom surface and side surfaces of the second gate electrode220may contact the second gate insulating film230.

The second gate insulating film230may be placed only on the upper surface of a part of the side wall of the first gate separation structure160, and may not be placed on a part of the side wall. For example, the second gate insulating film230may be placed on a side wall of a first dam structure163to be described below, and may not be placed on a side wall of a gate separation filling film162.

The height h1of the first gate insulating film230and the second gate insulating film230may be the same.

The first gate insulating film130and the second gate insulating film230may be formed of or may include at least one of silicon oxide, silicon oxynitride, silicon nitride or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate.

The semiconductor device according to some other embodiments may include an NC (Negative Capacitance) FET that uses a negative capacitor. For example, the first and second gate insulating films130and230may include a ferroelectric material film having ferroelectric properties, and a paraelectric material film having the paraelectric properties.

The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series, and the capacitance of each capacitor has a positive value, the entire capacitance decreases from the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the entire capacitance may be greater than an absolute value of each individual capacitance, while having a positive value.

When the ferroelectric material film having the negative capacitance and the paraelectric material film having the positive capacitance are connected in series, the entire capacitance values of the ferroelectric material film and the paraelectric material film connected in series may increase. Taking advantage of the increased overall capacitance value, a transistor including the ferroelectric material film may have a subthreshold swing (SS) below 60 mV/decade at room temperature.

The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include or be formed of, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The ferroelectric material film may further include a dopant. For example, the dopant may include or may be at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary, depending on which type of ferroelectric material is included in the ferroelectric material film.

When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include or may be, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

When the dopant is aluminum (Al), the ferroelectric material film may include 3 to 8 at % (atomic %) aluminum. Here, a ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material film may include 2 to 10 at % silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2 to 10 at % yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1 to 7 at % gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50 to 80 at % zirconium.

The paraelectric material film may have paraelectric properties. The paraelectric material film may include or be formed of at least one of, for example, a silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include or may be, but is not limited to, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has the ferroelectric properties, but the paraelectric material film may not have the ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, a crystal structure of hafnium oxide included in the ferroelectric material film is different from a crystal structure of hafnium oxide included in the paraelectric material film.

The ferroelectric material film may have a thickness having the ferroelectric properties. A thickness of the ferroelectric material film may be, but is not limited to, for example, 0.5 to 10 nm. Since a critical thickness that exhibits the ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

As an example, the first and second gate insulating films130and230may include a single ferroelectric material film. As another example, the first and second gate insulating films130and230may include a plurality of ferroelectric material films spaced apart from each other. The first and second gate insulating films130and230may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

The first gate spacer140may be placed on the side wall of the first gate electrode120. As an example, inFIG.2, the first gate spacer140placed on the first lower pattern110may include a first outer spacer141and a first inner spacer142. The first inner spacer142may be placed between the first sheet patterns NS1adjacent to each other in the third direction D3. As another example, inFIG.3, the first gate spacer140placed on the first lower pattern110does not include the first inner spacer142, and may include only the first outer spacer141.

The second gate spacer240may be placed on the side wall of the second gate electrode120. Since the first active pattern AP1and the second active pattern AP2may be transistor formation region of the same conductivity type, the second gate spacer240placed on the second lower pattern210may have the same structure as the first gate spacer140placed on the first lower pattern110. As an example, when the first gate spacer140placed on the first lower pattern110includes the first outer spacer141and the first inner spacer142, the second gate spacer240disposed on the second lower pattern210may include a second outer spacer241and a second inner spacer242. As another example, when the first gate spacer140placed on the first lower pattern110does not include the first inner spacer142, the second gate spacer240placed on the second lower pattern210may also not include the second inner spacer242.

Although not shown in the drawings, as an example, the first gate spacer140disposed on the third lower pattern310may include a first outer spacer141and a first inner spacer142. As another example, the first gate spacer140placed on the third lower pattern310may not include the first inner spacer142and may include only the first outer spacer141.

Each of the outer spacers141and241and the inner spacers142and242may include or be formed of, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

The first gate capping pattern145may be placed on the first gate electrode120and the first gate spacer140. An upper surface145US of the first gate capping pattern may be placed on the same plane as the upper surface of a first interlayer insulating film191. Unlike that shown in theFIG.2, the first gate capping pattern145may be placed between the first gate spacers140.

The second gate capping pattern245may be placed on the second gate electrode220and the second gate spacer240. An upper surface245US of the second gate capping pattern may be placed on the same plane as the upper surface of the first interlayer insulating film191. Unlike that shown inFIG.4, the second gate capping pattern245may be placed between the second gate spacers240.

The first gate capping pattern145and the second gate capping pattern245may include or be formed of, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The first gate capping pattern145and the second gate capping pattern245may include or be formed of materials having etching selectivity to the first interlayer insulating film191.

A plurality of first source/drain patterns150may be placed on the first lower pattern110. The plurality of first source/drain patterns150may be placed between the first gate electrodes120adjacent to each other in the first direction D1. Each first source/drain pattern150may be connected to the first sheet pattern NS1adjacent in the first direction D1.

A plurality of second source/drain patterns250may be placed on the second lower pattern210. The plurality of second source/drain patterns250may be placed between the second gate electrodes220adjacent to each other in the first direction D1. Each second source/drain pattern250may be connected to the second sheet pattern NS2adjacent in the first direction D1.

The first source/drain pattern150may be included in a source/drain of a transistor that uses the first sheet pattern NS1as a channel region. The second source/drain pattern250may be included in a source/drain of a transistor that uses the second sheet pattern NS2as a channel region.

Although not shown in the drawings, a source/drain contact may be placed on the first source/drain pattern150and the second source/drain pattern250. Further, a metal silicide film may be further placed between the source/drain contact and the source/drain patterns150and250.

Although the first source/drain pattern150and the second source/drain pattern250are shown to have a cross section similar to an arrow, e.g., inFIG.6, the embodiment is not limited thereto.

The first interlayer insulating film191may be placed on the field insulating film105. The first interlayer insulating film191may cover the side wall of the first gate structure GS1and the side wall of the second gate structure GS2. The first interlayer insulating film191may be formed on the first source/drain pattern150and the second source/drain pattern250. The first interlayer insulating film191may include or be formed of, for example, a silicon oxide or oxide-based insulating material.

The first gate separation structure160may be placed on the substrate100. The first gate separation structure160may be placed on the field insulating film105between the first active pattern AP1and the second active pattern AP2. The first gate separation structure160may be placed along the first direction D1.

The first gate separation structures160may be spaced apart from each other in the second direction D2. The first active pattern AP1and the second active pattern AP2may be placed between the first gate separation structures160adjacent to each other in the second direction D2. The first gate structure GS1may be placed between the first gate separation structures160adjacent to each other in the second direction D2.

In the semiconductor device according to some embodiments, the first gate separation structure160may be placed along a boundary of a standard cell. For example, the first gate separation structure160may be a standard cell separation structure.

The first gate separation structure160may separate the gate electrodes adjacent to each other in the second direction D2. The first gate structure GS1and the second gate structure GS2may be separated by the first gate separation structure160. For example, the first gate electrode120and the second gate electrode220may be separated by the first gate separation structure160.

For example, when the first gate electrode120and the second gate electrode220include an end that includes a single side wall, the first gate separation structure160may be placed between the end of the first gate electrode120and the end of the second gate electrode220. For example, the first gate separation structure160may be interposed between side walls of the first and second gate electrodes120and220facing each other.

The first gate separation structure160may be placed on the field insulating film105between the first gate structure GS1and the second gate structure GS2arranged in the second direction D2. The upper surface160US of the first gate separation structure may be placed on the same plane as the upper surface145US of the first gate capping pattern145and the upper surface245US of the second gate capping pattern245.

The first gate separation structure160may be placed in the first interlayer insulating film191on the field insulating film105. The upper surface160US of the first gate separation structure may be placed on the same plane as the upper surface of the first interlayer insulating film191.

Referring toFIG.6, a first recess insulating film191R1of the first interlayer insulating film191may be placed between the first gate separation structure160and the field insulating film105. The first recess insulating film191R1may be a portion of the first interlayer insulating film191that overlaps the first gate separation structure160in the third direction D3.

The first gate separation structure160may be placed inside the first gate separation trench160tdefined by the first interlayer insulating film191and the field insulating film105. The first gate separation structure160may fill the first gate separation trench160t. The first gate separation trench160tseparates the first gate structure GS1and the second gate structure GS2.

Referring toFIGS.5A,5B and8, the first gate separation structure160may include a first gate separation filling film162and a first dam structure163.

For ease of explanation, the first dam structure163will be described before the first gate separation filling film162.

The first dam structure163may be a substructure of the first gate filling film formed in the first gate separation structure160, and a part of the lower side wall of the first dam structure163may be in contact with the field insulating film105. A distance L1between a center line163cof the first dam structure163and the first lower pattern110in a second direction D2may be the same as a distance L2between the center line163cof the first dam structure163and the second lower pattern210in the second direction D2, and the center line163cmay vertically pass through the center of the fin trench FT, e.g., in a third direction D3. The structure of the first dam structure163may be formed by a process according to an embodiment illustrated inFIG.29, which will be described below.

The remaining upper side wall of the first dam structure163is in contact with the first and second gate insulating films130and230, and the upper surface of the first dam structure163may be in contact with the first gate separation filling film162.

The height of the upper surface of the first dam structure163may be the same as the height h1of the first and second gate insulating films130and230.

The first dam structure163may have a wedge shape in which a width W163of the first dam structure163in the second direction D2decrease in a direction downward approaching the substrate100. The width W163of the first dam structure163in the second direction D2may be in the range of 4 nm to 8 nm.

The first dam structure163may include or be formed of, for example, silicon oxide or oxide-based and silicon nitride or nitride-based insulating material.

The first gate separation trench160tmay be defined by the first interlayer insulating film191and the upper surface of the first dam structure163. The first gate separation trench160tmay be defined by the first gate electrode120, the second gate electrode220, the first gate capping pattern145, and the second gate capping pattern245.

The first gate separation filling film162may fill the first gate separation trench160t.

The first gate separation filling film162may be placed on the first interlayer insulating film191and the upper surface of the first dam structure163. The first gate separation filling film162may be in contact with the first dam structure163, the first gate electrode120, the second gate electrode220, the first gate capping pattern145, and the second gate capping pattern245.

A part of the first gate separation structure may overlap the first recess insulating film191R1of the first interlayer insulating film191, e.g., in the third direction D3. The other part of the first gate separation structure may not overlap the first interlayer insulating film191in the third direction D3.

In the semiconductor device according to some embodiments, the width of the first gate separation structure160in the first direction D1may be greater than the width of the first gate structure GS1in the first direction D1.

The first gate separation filling film162may include or be formed of, for example, silicon oxide or oxide-based insulating material.

Although the first gate separation filling film162is shown as a single layer inFIG.5A, as inFIG.5B, the first gate separation structure160may further include a first gate separation liner161. The first gate separation liner161may extend along the profile of the first gate separation trench160t. For example, the first gate separation liner161may be conformally formed on the first gate separation trench160t.

The first gate separation liner161may act as a barrier that prevents oxygen from being diffused to the first gate electrode120and the second gate electrode220. The first gate separation liner161may include or be formed of, for example, a material that prevents diffusion of oxygen. The first gate separation liner161may include, but is not limited to, for example, at least one of a polycrystalline semiconductor material, aluminum oxide (AlO), aluminum nitride (AlN), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon carbide (SiC), silicon lanthanum oxide (LaO), and high dielectric constant insulating material. The high dielectric constant insulating material may be one of the materials described in relation to the first gate insulating film130. For example, the first gate separation liner may be formed of the same material as the first gate insulating film130.

The second interlayer insulating film192may be placed on the first interlayer insulating film191. The second interlayer insulating film192may include or be formed of, but is not limited to, for example, silicon oxide, silicon nitride, silicon oxynitride, FOX (Flowable Oxide), TOSZ (Tonen SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material or a combination thereof.

A wiring line195may be placed in the second interlayer insulating film192. The wiring line195may extend in the first direction D1along the first gate separation structure160.

For example, the wiring line195may be a power lane that supplies power to an integrated circuit that includes the first active pattern AP1, the second active pattern AP2, the first gate electrode120, and the second gate electrode220. The wiring line195may include or be formed of, for example, at least one of a metal, a metal alloy, a conductive metal nitride, and a two-dimensional (2D) material.

Although not shown, the wirings that transfer the signal to the integrated circuit including the first active pattern AP1, the second active pattern AP2, the first gate electrode120and the second gate electrode220may be further placed between the first gate separation structures160in the second direction D2.

As an example, unlike that shown in the drawings, the wiring line195may be in contact with the upper surface160of the first gate separation structure.

FIGS.9to15are diagrams for explaining a semiconductor device according to some embodiments, respectively. For convenience of explanation, features different from those described referring toFIGS.1to8will be mainly described. For reference,FIGS.9,10,14and15are cross-sectional views taken along C-C ofFIG.1,FIG.11is a cross-sectional view taken along F-F ofFIG.1,FIG.12is a cross-sectional view taken along A-A ofFIG.1, andFIG.13is a cross-sectional view taken along D-D ofFIG.1.

FIG.9is an example in which the center line of the first gate separation filling film162and the center line of the first dam structure163do not match, in the semiconductor device according to some embodiments. For example, a first dam structure163′ and a first gate separation filling film162′ may be misaligned, e.g., in a certain degree.

Therefore, the height h1of the second gate insulating film230may be higher than the height h4of the first gate insulating film130. For example, at least a part of the second gate insulating film230may be placed on an upper surface163′US of the first dam structure163′, and the second gate insulating film230placed on the upper surface163′US of the first dam structure163′ may have a flat/planar shape having a constant height from a top surface of the substrate100.

Referring toFIGS.10and11, in the semiconductor device according to some embodiments, a first gate separating filling film162″ may be landed on the gate insulating film330. For example, a gate insulating film330may be placed between the first gate separation filling film162″ and the first dam structure163″, and the first gate separation filling film162″ and the gate insulating film330may be in contact with each other.

Referring toFIGS.12and13, the semiconductor device according to some embodiments may further include a first source/drain contact170on the first source/drain pattern150, and a second source/drain contact270on the second source/drain pattern250.

Although not shown inFIGS.2and4, the first source/drain contact170and the second source/drain contact270may be placed between adjacent first gate structures GS1and between the second gate structures GS2ofFIGS.2and4, e.g., as shown inFIG.12.

The first source/drain contact170may be connected to the first source/drain pattern150, and the second source/drain contact270may be connected to the second source/drain pattern250. The upper surface of the first source/drain contact170and the upper surface of the second source/drain contact270may be placed on the same plane as the upper surface of the first interlayer insulating film191and the upper surface160US of the first gate separation structure.

At least one of the first source/drain contacts170on the first source/drain pattern150may be connected to the wiring line195. A wiring plug196may connect the first source/drain contact170to the wiring line195. The wiring plug196may be placed in the second interlayer insulating film192.

A part of the first source/drain contact170may be placed inside the first gate separation structure160. For example, the first source/drain contact170may vertically overlap a portion of the first gate separation structure160. For example, the first source/drain contact170may not pass through the first gate separation structure160in the second direction D2.

A part of the first source/drain contact170may be placed on the first capping pattern145and may partially penetrate the first capping pattern145, and the first source/drain contact170and the first gate electrode120do not join. For example, the first source/drain contact170may contact the first capping pattern in certain embodiments but may not contact the first gate electrode120.

The upper surface120US of the first gate electrode120may have the same (e.g., a constant) height e.g., from a top surface of the substrate100, and the upper surface120US of the first gate electrode in a region adjacent to the first gate separation structure160may have a flat/planar shape. Therefore, this structure may be beneficial to prevent the first gate electrode120and the first source/drain contact170from forming a short circuit defect. This structure may be formed by a RMG (Replacement Metal Gate Process) like a process according to an embodiment illustrated inFIG.39.

The first source/drain contact170, the second source/drain contact270and the wiring plug196may include or be formed of, for example, at least one of metal, metal alloy, conductive metal nitride and two-dimensional (2D) material.

Referring toFIG.14, in the semiconductor device according to some embodiments, an upper surface160′″US of a first gate separation structure160′″ forms the same plane as the upper surface120US of the first gate electrode120and the upper surface220US of the second gate electrode220.

Therefore, the upper surface160′″US of the first gate separation structure160′″ may be in contact with the lower surface of the gate capping pattern45, and may not contact the second interlayer insulating film192.

Referring toFIG.15, in the semiconductor device according to some embodiments, the first gate capping pattern145and the second gate capping pattern245are not placed.

Accordingly, the upper surface120′US of the first gate electrode120′ and the upper surface220′US of the second gate electrode220′ may be in contact with the lower surface of the second interlayer insulating film192.

FIGS.16to19are diagrams for explaining a semiconductor device according to some embodiments. For convenience of explanation, features different from those described referring toFIGS.1to8will be mainly described. For reference,FIG.16is a layout diagram for explaining the semiconductor device according to some embodiments.FIGS.17to19are cross-sectional views taken along E-E, G-G, and H-H ofFIG.16, respectively.

Referring toFIGS.16to19, a semiconductor device according to some embodiments may further include a second gate separation structure165placed between the first gate separation structures160.

The second gate separation structure165may be placed on the substrate100. The second gate separation structure165may be placed on the field insulating film105.

The second gate separation structure165may be placed between the first active pattern AP1and the third active pattern AP3. The second gate separation structure165may be placed between the first lower pattern110and the third lower pattern310.

The upper surface165US of the second gate separation structure may be placed on the same plane as the upper surface160US of the first gate separation structure. In the semiconductor device according to some embodiments, the second gate separation structure165may be placed in a standard cell.

For example, the length of the first gate separation structure160in the first direction D1may be greater than the length of the second gate separation structure165in the first direction D1.

The second gate separation structure165may be placed between the first gate structures GS1intersecting the first active pattern AP1and the third active pattern AP3. For example, the second gate separation structure165may not be in contact with the first gate structures GS1, e.g., in the first direction D1. For example, both end surfaces of the second gate separation structure165in the first direction D1may be spaced apart from the first gate structures GS1. For example, the first interlayer insulating film191may be interposed between the end surfaces of the second gate separation structure165and respective first gate structures GS1in the first direction D1.

The second gate separation structure165may separate a first_1 gate electrode120_1and a first_2 gate electrode120_2arranged in the second direction D2. The first gate structure GS1may be separated by the second gate separation structure165to form the first_1 gate electrode120_1and the first_2 gate electrode120_2.

The first_1 gate electrode120_1may intersect the first active pattern AP1. The first_1 gate electrode120_1may be placed on the first lower pattern110and wrap the first sheet pattern NS1. The first and first_2 gate electrodes120_2may intersect the third active pattern AP3. The first_2 gate electrode120_2may be placed on a third lower pattern310and wrap a third sheet pattern NS3.

The first_1 gate insulating film130_1may extend along the periphery of the first sheet pattern NS1, the side wall of the first dam structure163, the upper surface of the first lower pattern110, and the side wall of the second dam structure168. The first_2 gate insulating film130_2may extend along the periphery of the third sheet pattern NS3, the side wall of the first dam structure163, the third lower pattern310and the side wall of the second dam structure168. A first_1 gate capping pattern145_1may be placed on the first_1 gate electrode120_1, and a first_2 gate capping pattern145_2may be placed on the first_2 gate electrode120_2. The upper surface145US of the first_1 gate capping pattern and the upper surface145US of the first_2 gate capping pattern may be placed on the same plane as the upper surface165US of the second gate separation structure.

The first_1 gate electrode120_1, the first_1 gate insulating film130_1, and the first_1 gate capping pattern145_1may be included in the first_1 gate structure. The first_2 gate electrode120_2, the first_2 gate insulating film130_2, and the first_2 gate capping pattern145_2may be included in the first_2 gate structure. The first_1 gate structure and the first_2 gate structure may be separated by the second gate separation structure165. The first_1 gate structure and the first_2 gate structure may be placed between the first gate structures GS1intersecting the first active pattern AP1and the third active pattern AP3.

The first source/drain pattern150may be placed on the first lower pattern110. The first source/drain pattern150may be connected to the first sheet pattern NS1adjacent in the first direction D1. The third source/drain pattern350may be placed on the third lower pattern310. The third source/drain pattern350may be connected to the third sheet pattern NS3adjacent in the first direction D1. The second gate separation structure165may be placed between the first source/drain pattern150and the third source/drain pattern350.

A second recess insulating film191R2of the first interlayer insulating film191may be placed between the second gate separation structure165and the field insulating film105. The second recess insulating film191R2may be a portion of the first interlayer insulating film191that overlaps the second gate separation structure165in the third direction D3.

The second gate separation structure165may be placed in a second gate separation trench165tdefined by the first interlayer insulating film191, the second dam structure168, the first_1 gate capping pattern145_1and the first_2 gate capping pattern145_2. A part of the second gate separation structure165may fill the second gate separation trench165t. The second gate separation trench165tand the second dam structure168may separate the first_1 gate electrode120_1and the first_2 gate electrode120_2.

The second gate separation structure165may include a second gate separation filling film167and a second dam structure168. The second gate separation filling film167may be placed on the first interlayer insulating film191and the upper surface of the second dam structure168. The second gate separation filling film167may be in contact with the second dam structure168, the first gate electrodes120_1and120_2, and the first gate capping pattern145. The second gate separation filling film167may fill the second gate separation trench165t.

Contents of the materials included in the second gate separation filling film167and the second dam structure168may be the same as the contents of the first gate separation filling film162and the first dam structure163.

FIGS.20and21are diagrams for explaining a semiconductor device according to some embodiments. For convenience of explanation, features different from those described referring toFIGS.16to19will be mainly described. For reference,FIG.20is a cross-sectional view taken along G-G ofFIG.16, andFIG.21is a cross-sectional view taken along H-H ofFIG.16.

Referring toFIGS.20and21, the semiconductor device according to some embodiments may further include a first connecting source/drain contact175placed on the first source/drain pattern150and the third source/drain pattern350.

The first connecting source/drain contact175may be connected to the first source/drain pattern150and the third source/drain pattern350. An upper surface of the first connecting source/drain contact175may be placed in the same plane as the upper surface of the first interlayer insulating film191and the upper surface165US of the second gate separation structure.

A part of the first connecting source/drain contact175may be placed inside the second gate separation structure165. For example, the second gate separation structure165may surround and contact a bottom surface and side surfaces of a portion of the first connecting source/drain contact175. The first connecting source/drain contact175may pass through the second gate separation structure165in the second direction D2. The first connecting source/drain contact175may include or be formed of, for example, at least one of a metal, a metal alloy, a conductive metal nitride and a two-dimensional (2D) material.

FIGS.22to24are diagrams for explaining a semiconductor device according to some embodiments. For convenience of explanation, features different from those described referring toFIGS.1to8will be mainly described. For reference,FIG.22is a layout diagram for explaining the semiconductor device according to some embodiments.FIGS.23and24are cross-sectional views taken along C-C ofFIG.22.

Referring toFIGS.22to23, in the semiconductor device according to some embodiments, each of the first to third active patterns AP1, AP2and AP3may be a fin-type pattern.

Each of the first to third active patterns AP1, AP2and AP3may be defined by the fin trench FT.

The first gate electrode120may cover the side wall of the first active pattern AP1protruding upward from the upper surface105US of the field insulating film. The second gate electrode220may cover the side wall of the second active pattern AP2protruding upward from the upper surface105US of the field insulating film. The first gate insulating film130may be formed along the profile of the first active pattern AP1protruding upward from the upper surface105US of the field insulating film. For example, the first gate insulating film130may be conformally formed on an exposed portion (protruding portion) of the first active pattern AP1. For example, the first gate insulating film130may cover and contact the protruding portion of the first active pattern AP1. The second gate insulating film230may be formed along the profile of the second active pattern AP2protruding upward from the upper surface105US of the field insulating film. For example, the second gate insulating film230may be conformally formed on the protruding portion of the second active pattern AP2. For example, the second gate insulating film230may cover and contact the protruding portion of the second active pattern AP2.

Referring toFIGS.22and23, each of the first to third active patterns AP1, AP2and AP3may be placed inside an active region defined by a deep trench DT. The first gate separation structure160may be placed on the field insulating film105that fills the deep trench DT.

InFIG.24, each of the first to third active patterns AP1, AP2and AP3may be placed between dummy fin-type patterns DPF adjacent to each other in the second direction D2. An upper surface of the dummy fin-type pattern DPF may be covered with the field insulating film105. For example, the upper surface and side surfaces of the dummy fin-type pattern DPF may contact the field insulating film105.

Although the number of each of the first to third active patterns AP1, AP2and AP3is shown as two, this is merely for convenience of explanation, and the number thereof is not limited thereto. The number of each of the first to third active patterns AP1, AP2and AP3may be one or three or more.

FIGS.25to40are intermediate stage diagrams for explaining a method of manufacturing the semiconductor device according to some embodiments. The first gate separation structure160described referring toFIGS.1to8may be manufactured accordingly.

FIGS.26to32,34,36,38and40are cross-sectional views taken along M-M ofFIG.25.FIGS.33,35,37and39are cross-sectional views taken along L-L ofFIG.25. In the following description of the manufacturing method, the repeated contents of those explained usingFIGS.1to24will be briefly explained or omitted.

Referring toFIGS.25and26, first and second preliminary active pattern structures AP1_pand AP2_pextending in the first direction D1, and a field insulating film105between the first and second preliminary active pattern structures AP1_pand AP2_pare formed.

The first and second preliminary active pattern structures AP1_p, AP2_pare spaced apart from each other in the second direction D2.

The first preliminary active pattern structure AP1_pmay include a first lower pattern110, and a sacrificial pattern SC_L and an active pattern ACT_L that are alternately stacked on the first lower pattern110.

The second preliminary active pattern structure AP2pmay include a second lower pattern210, and a sacrificial pattern SC_L and an active pattern ACT_L that are alternately stacked on the second lower pattern210.

For example, the sacrifice pattern SC_L may include or be formed of a silicon-germanium film. The active pattern ACT_L may include or be formed of a silicon film.

Referring toFIG.27, a dummy conductive material film PL extending along the profile of the field insulating film105and the first and second preliminary active pattern structures AP1_pand AP2_pmay be formed. For example, the dummy conductive material film PL may be conformally formed on the field insulting film105and the first and second preliminary active pattern structures AP1_pand AP2_p.

The dummy conductive material film PL may include or be formed of, but is not limited to, for example, polysilicon. The dummy conductive material film PL may be formed by, but is not limited to, an atomic layer deposition method (ALD).

Referring toFIG.28, a hard mask pattern HM may be formed on an uppermost surface PL US of the dummy conductive material film PL.

The hard mask pattern HM may include or be formed of, but is not limited to, for example, silicon nitride. Although the hard mask pattern HM is formed only on the uppermost surface PL US of the dummy conductive material film PL, using a physical vapor deposition (PVD) method, the embodiment is not limited thereto.

The hard mask pattern HM and the dummy conductive material film PL may have etching selectivity having different etch rates from each other.

Referring toFIG.29, by etching the hard mask pattern HM and the dummy conductive material film PL, using the etching selectivity between the hard mask pattern HM and the dummy conductive material film PL, a part of the field insulating film105may be etched, and a first recess R1of the field insulating film105may be formed in the field insulating film105. The etching may include or may be, but is not limited to, wet etching and dry etching.

The width of the first recess R1in the second direction D2may decrease in a downward direction approaching the substrate100.

Further, a center line Rc of the first recess R1may coincide with the center of the fin trench FT. For example, a distance L1between the center line Rc of the first recess R1and the first lower pattern110may be the same as a distance L2between the center line Rc of the first recess R1and the second lower pattern Rc. The first recess R1may be placed at the center of the first preliminary active pattern structure AP1_pand the second preliminary active pattern structure AP2pin a self-aligned manner, through etching of the hard mask pattern HM and the dummy conductive material film PL.

Referring toFIG.30, a pre sacrificial film SCp that covers the first recess R1and the dummy conductive material film PL′ may be formed. The pre sacrificial film SCp may include or may be, but is not limited to, for example, a silicon-germanium film.

Referring toFIG.31, a flattening process (e.g., CMP) may be performed on the pre sacrificial film SCp and the dummy conductive material film PL′ to form a sacrificial film pattern SCp′ from the pre sacrificial film SCp. The width of the sacrificial film pattern SCp′ in the second direction D2may decrease in a downward direction approaching the substrate100.

Referring toFIGS.32and33, a dummy gate structure DGS may be formed on the dummy conductive material film PL′ and the sacrificial film pattern SCp′.

The dummy gate structure DGS may include a dummy electrode DP, a dummy capping pattern DC, and a pre spacer141p. The dummy electrode DP may be formed on the dummy conductive material film PL′ and the sacrificial film pattern SCp′, and the dummy electrode DP may include or be formed of the same material as the dummy conductive material film PL′.

The dummy capping pattern DC may act like a mask pattern, and the dummy capping pattern DC may include or be formed of, but is not limited to, for example, silicon nitride.

The pre spacer141pmay be placed on the side walls of the dummy electrode DP and the dummy capping pattern DC, and the pre spacer141pmay include or be formed of, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

Referring toFIGS.34to37, the sacrificial film pattern SCp′ may be removed to form an empty space VR, and a first pre dam structure163′ may be formed in the empty space VR.

The first pre dam structure163′ may include or be formed of the same material as the first dam structure163inFIGS.1to24. The first dam structure163may be formed from the first pre dam structure163′.

Referring toFIG.38, the sacrificial pattern SC_L may be removed, the first sheet patterns NS1spaced from each other in the third direction D3may be formed on/above the first lower pattern110, and the second sheet patterns NS2spaced from each other in the third direction D3may be formed on/above the second lower pattern210.

Subsequently, the gate insulating film30may be formed. The gate insulating film30may wrap the first sheet patterns NS1and the second sheet patterns NS2, and extend along the upper surfaces of the first and second lower patterns110and210, the upper surface105US of the field insulating film105, and the profile of the first dam structure163. For example, the gate insulating film30may be conformally formed on the upper surfaces of the first and second lower patterns110and210, the upper surface105US of the field insulating film105, and the exposed portion of the first dam structure163. The gate insulating film30may include or be formed of the same material as those of the first and second gate insulating films130and230inFIGS.1to24.

Subsequently, the gate electrode20may be formed. The gate electrode20may wrap the first sheet patterns NS1and the second sheet patterns NS2, and cover the first and second lower patterns110and210, the field insulating film105, and the first dam structure163.

The gate electrode20may be subjected to or flattened by a flattening process (CMP), and the gate capping pattern45may be formed on the flattened gate electrode20. The material of the gate capping pattern45may include or be formed of the same material as those of the first and second gate capping patterns145and245inFIGS.1to24.

Referring toFIG.39, the gate electrode20, which overlaps the first dam structure163in a vertical direction and is placed on the upper surface of the first dam structure163, may be removed to form the gate separation trench160t.

The gate electrode20may be separated into the first gate electrode120and the second gate electrode230through the first gate separation trench160t, and the gate insulating film30may be separated into the first and second gate insulating films130and230, and the gate capping pattern45may be separated into first and second gate capping patterns145and245.

Referring toFIG.40, the first gate separation filling film162may be formed along the first gate separation trench160t, and the gate separation structure160may be formed.

According to the present invention, the substructure of the gate separation structure may be formed in a self-aligned manner to improve the separation operation efficiency of the gate electrode, and the width of the gate electrode placed between the active pattern and the gate separation structure may be kept constant to improve the operational reliability of semiconductor device, e.g., by the self-alignment process.

In addition, since a RMG process of cutting the gate electrode to form a final gate separation structure is performed, the upper surface of the gate electrode has the same height from the substrate100. In particular, since the upper surface120US of the gate electrode120in a region adjacent to the first gate separation structure160has a flat/planar shape, it is beneficial to prevent short circuit between the source/drain contact and the gate electrode and improve the reliability of semiconductor device.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.