Patent ID: 12249611

MODE FOR CARRYING OUT THE INVENTION

First Embodiment

FIG.1is a block diagram illustrating a configuration of an imaging device according to a first embodiment. An imaging device1illustrated inFIG.1is provided with a pixel array unit11, a pixel control circuit12, a pixel signal processing circuit13, a horizontal drive circuit14, a logic circuit15, a memory array unit21, a CIM input control circuit22, a CIM read circuit23, a signal processing circuit31, a memory32, and an input/output unit33.

In the pixel array unit11, a plurality of pixels is arranged in a two-dimensional manner. Each pixel generates a pixel signal S12obtained by photoelectrically converting incident light on the basis of a plurality of types of pixel control signals S11from the pixel control circuit12. Furthermore, each pixel outputs the pixel signal S12to the pixel signal processing circuit13in one direction. A circuit configuration example of the pixel will be described later.

The pixel control circuit12includes, for example, a shift register, and inputs the pixel control signal S11to each pixel of the pixel array unit11via pixel drive wiring (not illustrated inFIG.1). By the pixel control signal S11, the pixel control circuit12sequentially selects and scans the pixels of the pixel array unit11, and outputs the pixel signal S12of each pixel to the pixel signal processing circuit13.

The pixel signal processing circuit13performs correlated double sampling (CDS) processing for removing pixel-specific fixed pattern noise and analog to digital (AD) conversion processing on the pixel signals S12read from the pixel array unit11. An image signal S13processed by the pixel signal processing circuit13is input to the CIM input control circuit22.

The horizontal drive circuit14includes, for example, a shift register, and sequentially outputs horizontal scan pulses to the pixel signal processing circuit13. Therefore, for example, the image signals S13held in the pixel signal processing circuit13are sequentially output toward the CIM read circuit23.

The logic circuit15receives an externally input clock signal and data indicating an operation mode and the like, and controls an operation of an entire imaging device1. For example, the logic circuit15generates a vertical synchronization signal, a horizontal synchronization signal and the like on the basis of the input clock signal, and supplies the signals to the pixel control circuit12, the pixel signal processing circuit13, the horizontal drive circuit14, the CIM input control circuit22, the CIM read circuit23and the like.

In the memory array unit21, a plurality of memory cells is arranged in a two-dimensional manner. The memory array unit21outputs a convolution signal S15indicating a result of a product-sum operation by an analog method or a digital method using the plurality of memory cells to the CIM read circuit23in one direction. A circuit configuration example of the memory array unit21will be described later.

The CIM input control circuit22includes, for example, a shift register, and inputs a memory cell control signal S14associated with the image signal S13to each memory cell of the memory array unit21via memory cell drive wiring (not illustrated inFIG.1). By the memory cell control signal S14, the CIM input control circuit22sequentially or collectively selects and scans the memory cells of the memory array unit21, and outputs the convolution signal S15obtained by a product-sum operation using memory values of the respective memory cells to the CIM read circuit23.

The CIM read circuit23performs AD conversion processing and the like on the convolution signal S15read from the memory array unit21. A convolution signal S16processed by the CIM read circuit23is input to the signal processing circuit31. The convolution signal S16may be intermediate data at an intermediate stage of image recognition.

The signal processing circuit31performs conversion processing by an activation function, pooling processing and the like on the convolution signal S16input from the CIM read circuit23, and outputs a processing result to the input/output unit33. Note that, some processing may be performed by the memory array unit21or by the CIM read circuit23. Furthermore, in a case where the signal processing is performed a plurality of times, the CIM read circuit23may perform the signal processing of several times, and thereafter the signal processing circuit31may perform the signal processing of the remaining number of times. In this manner, by sharing the signal processing by the CIM read circuit23and the signal processing circuit31, concentration of processing loads may be avoided.

Moreover, the signal processing circuit31may cause the memory32to store parameters and the like input from an external image processing device via the input/output unit33, and may appropriately select and execute signal processing on the basis of an instruction from the external image processing device.

The memory32stores data such as parameters required for signal processing performed by the signal processing circuit31. Furthermore, the memory32may include, for example, a frame memory for storing an image signal in processing such as demosaic processing.

The input/output unit33outputs signals sequentially input from the signal processing circuit31to the external image processing device, for example, a subsequent image signal processor (ISP) and the like. Furthermore, the input/output unit33supplies signals and parameters input from the external image processing device to the signal processing circuit31and the logic circuit15. Moreover, the input/output unit33may write a data value indicating an externally provided learning result to the memory cell of the memory array unit21, and may update the learning result via the input/output unit33by reflecting a result calculated by the signal processing circuit31.

FIGS.2A to2Gare diagrams illustrating an example of a circuit layout of the imaging device1. In this embodiment, the pixel array unit11is arranged on a first substrate101, and the memory array unit21is arranged on a second substrate102. Each circuit of the imaging device1is also arranged on the second substrate102. The first substrate101and the second substrate102are, for example, silicon substrates, and are stacked so as to overlap each other. In order to minimize a substrate area, the first substrate101and the second substrate102do not need to entirely overlap each other; they are only required to at least partially overlap each other.

Note that, inFIGS.2A to2G, two directions parallel to the first substrate101and the second substrate102and orthogonal to each other are defined as an X direction and a Y direction, respectively. Furthermore, a direction orthogonal to the X direction and the Y direction, in other words, a stacking direction of the first substrate101and the second substrate102is defined as a Z direction. Furthermore, only the pixel control circuit12, the pixel signal processing circuit13, the logic circuit15, the CIM input control circuit22, and the CIM read circuit23are illustrated on the second substrate102in each drawing for convenience of space, and other circuits are not illustrated.

In this embodiment, as illustrated inFIGS.2A to2G, the pixel signal S12is output from the pixel array unit11in the X direction, and the convolution signal S15is output from the memory array unit21in the Y direction perpendicular to the X direction. That is, read wiring (output wiring) of the pixel signal S12is perpendicular to read wiring (output wiring) of the convolution signal S15. Note that, it is only required that the output direction of the pixel signal S12is a direction intersecting the output direction of the convolution signal S15.

InFIG.2A, the pixel signal processing circuit13is arranged in a direction perpendicular to the output direction of the X pixel signal S12, and the pixel control circuit12is arranged in a direction parallel to the output direction of the X pixel signal S12. That is, the pixel signal processing circuit13and the pixel control circuit12are arranged in directions perpendicular to each other. Furthermore, the CIM input control circuit22is arranged in a direction parallel to the output direction of the convolution signal S15, and the CIM read circuit23is arranged in a direction perpendicular to the output direction of the convolution signal S15. That is, the CIM input control circuit22and the CIM read circuit23are also arranged in directions perpendicular to each other. The logic circuit15is arranged between the pixel signal processing circuit13and the memory array unit21.

InFIG.2B, the position of the logic circuit15is different from that in the layout illustrated inFIG.2A. In this layout, the logic circuit15is arranged between the pixel control circuit12and the memory array unit21. However, the position of the logic circuit15is not limited to the position illustrated inFIGS.2A and2B, and this is only required to be appropriately arranged in a space in the second substrate102.

Furthermore, inFIG.2B, a shape of a plane region of the memory array unit21is different from that in the layout illustrated inFIG.2A. InFIG.2A, the plane region of the memory array unit21is a rectangle with a short side in the X direction and a long side in the Y direction. In contrast, regarding the plane region illustrated inFIG.2B, the plane region of the memory array unit21is a rectangle with a long side in the X direction and a short side in the Y direction. The plane region of the memory array unit21may be a square, and is determined according to a specification of the product-sum operation. For example, in a case where the number of convolutions (additions) of the product-sum operation is large, long read wiring is required. In this case, the rectangle of the memory array unit21illustrated inFIG.2Ais preferable.

InFIG.2C, the CIM input control circuit22is arranged between the memory array unit21and the pixel signal processing circuit13. Furthermore, the memory array unit21is arranged in a region deviated from a central region of the second substrate102in the X direction. Therefore, the center of the memory array unit21is shifted in the X direction from the center of the pixel array unit11. A center position of the pixel array unit11and a center position of the memory array unit21are only required to be optimized according to the layout of the signal wiring and power supply wiring. Therefore, the center position of each array unit does not need to be located on a straight line extending in the Z direction, and may be shifted in the X direction or the Y direction.

InFIG.2D, the output direction of the pixel signal S12is multiple directions including a +X direction and a −X direction. The −X direction is a direction rotated by 180 degrees in the X direction. Furthermore, on the second substrate102, a pixel signal processing circuit13aand a pixel signal processing circuit13bare arranged so as to be opposed to each other with the memory array unit21interposed therebetween in the X direction. The pixel signal processing circuit13aprocesses the pixel signal S12output from the pixel array unit11in the +X direction. The pixel signal processing circuit13bprocesses the pixel signal S12output from the pixel array unit11in the −X direction.

InFIG.2E, the output direction of the pixel signal S12is the multiple directions including the +X direction and the −X direction, and the output direction of the convolution signal S15is also multiple directions including a +Y direction and a −Y direction. The −Y direction is a direction rotated by 180 degrees in the Y direction. Furthermore, on the second substrate102, a pixel control circuit12aand a pixel control circuit12bare arranged so as to be opposed to each other with the memory array unit21interposed therebetween. The pixel control circuit12acontrols the pixel that outputs the pixel signal S12in the +X direction. The pixel control circuit12bcontrols the pixel that outputs the pixel signal S12in the −X direction.

Furthermore, on the second substrate102, a CIM input control circuit22aand a CIM input control circuit22bare arranged so as to be opposed to each other with the memory array unit21interposed therebetween. The CIM input control circuit22ainputs the input signal S14associated with the image signal S13processed by the pixel signal processing circuit13ato the memory array unit21. The CIM input control circuit22binputs the input signal S14associated with the image signal S13processed by the pixel signal processing circuit13bto the memory array unit21.

Moreover, a CIM read circuit23aand a CIM read circuit23bare arranged so as to be opposed to each other with the memory array unit21interposed therebetween. The CIM read circuit23aprocesses the convolution signal S15output from the memory array unit21in the −Y direction. The CIM read circuit23bprocesses the convolution signal S15output from the memory array unit21in the +Y direction.

InFIG.2F, on the first substrate101, the pixel signal S12is transmitted toward a central portion of the pixel array unit11, that is, toward a central portion of the first substrate1010. Furthermore, the pixel signal processing circuit13is arranged in a central portion of the second substrate102. Therefore, the pixel array unit11and the pixel signal processing circuit13are electrically connected to each other at the central portion of the first substrate101and the second substrate102, respectively.

FIG.2Gis an example of a layout of a so-called tiling structure in which a plurality of memory array units21is arrayed in the Y direction. In this layout, the CIM read circuit23includes a multiplexer and is shared by the plurality of memory array units21. Therefore, the convolution signals S15output from the respective memory array units21are collectively processed by the CIM read circuit23.

FIG.3Ais a diagram illustrating another example of the tiling structure. In the tiling structure illustrated inFIG.3A, the plurality of memory array units21is arrayed not only in the Y direction but also in the X direction. In other words, the plurality of memory array units21is arrayed in a two-dimensional manner. In this tiling structure also, the convolution signals S15output from the respective memory array units21are collectively processed by the CIM read circuit23.

FIG.3Bis a diagram illustrating still another example of the tiling structure. In the tiling structure illustrated inFIG.3B, the CIM read circuit23is arranged for each of the plurality of memory array units21. In this tiling structure, the convolution signals S15output from the respective memory array units21are individually processed by a plurality of CIM read circuit23, respectively.

FIG.4Ais a cross-sectional view schematically illustrating a joining mode between the first substrate101and the second substrate102. InFIG.4A, a plurality of through electrodes111formed in the first substrate101is joined to a plurality of connection terminals112formed on the second substrate102. The through electrode111and the connection terminal112may be formed by using metal such as copper, for example. Note that, a gap between the first substrate101and the second substrate102is filled with an insulating film.

The through electrode111penetrates the first substrate101and is electrically connected to the pixel array unit11via a wiring layer (not illustrated) including various types of wiring. The connection terminal112is formed on a front surface of the second substrate102(a joining surface to the first substrate101). The connection terminal112is connected to the pixel control circuit12and the pixel signal processing circuit13arranged on the second substrate102via various wiring layers (not illustrated).

In the joining mode illustrated inFIG.4A, the pixel control signal S11of the pixel control circuit12is transmitted from the connection terminal112to each pixel of the pixel array unit11via the through electrode111. Furthermore, the pixel signal S12of each pixel is transmitted from another through electrode111to the pixel signal processing circuit13through another connection terminal112.

FIG.4Bis a cross-sectional view schematically illustrating another joining mode between the first substrate101and the second substrate102. The joining mode illustrated inFIG.4Bis a so-called Cu—Cu joint in which a plurality of connection terminals121(first connection terminals) formed on the first substrate101is joined to a plurality of connection terminals112(second connection terminals) formed on the second substrate102, respectively. The connection terminal121may be formed using metal such as copper as with the connection terminal112, and is electrically connected to the pixel array unit11via wiring not illustrated. Note that, in this joining mode also, a gap between the first substrate101and the second substrate102is filled with an insulating film.

In the joining mode illustrated inFIG.4B, the pixel control signal S11of the pixel control circuit12is transmitted from the connection terminal112to each pixel of the pixel array unit11via the connection terminal121. Furthermore, the pixel signal S12of each pixel is transmitted from another connection terminal121to the pixel signal processing circuit13via another connection terminal112.

Note that, although not illustrated inFIGS.4A and4B, the pixel array unit11is formed above the through electrode111or the connection terminal121. Furthermore, a circuit group including the pixel control circuit12and the pixel signal processing circuit13is formed below the connection terminal112.

FIGS.5A to5Eare diagrams illustrating an example of an equivalent circuit diagram of pixels arrayed in the pixel array unit11. Hereinafter, a circuit configuration of the pixel illustrated in each drawing will be described.

A pixel50aillustrated inFIG.5Aincludes a photodiode51, a transfer transistor52, a reset transistor53, an amplification transistor54, and a selection transistor55.

The photodiode51is a photoelectric conversion unit that generates and accumulates a charge (signal charge) corresponding to a received light amount. An anode terminal of the photodiode51is grounded, and a cathode terminal thereof is connected to the transfer transistor52.

When turned on by a transfer signal, which is one of the pixel control signals S11, the transfer transistor52reads the charge from the photodiode51and transfers the same to the amplification transistor54. When turned on by a reset signal, which is one of the pixel control signals S11, the charge accumulated in the photodiode51is discharged to a power supply, so that the reset transistor53resets a potential of the photodiode51.

The amplification transistor54outputs the pixel signal S12according to an amount of charge accumulated in the photodiode51to the selection transistor55. When turned on by a selection signal, which is one of the pixel control signals S11, the selection transistor55outputs the pixel signal S12to read wiring56. The pixel signal S12is transmitted to the pixel signal processing circuit13via the read wiring56.

A pixel50billustrated inFIG.5Bincludes two photodiodes51aand51b. A charge generated by photoelectric conversion of the photodiode51ais temporarily held in a memory transistor57aand a capacitor58a. The held charge is transferred to the amplification transistor54by a transfer transistor52a. In contrast, a charge generated by photoelectric conversion of the photodiode51bis temporarily held in a memory transistor57band a capacitor58b. The held charge is transferred to the amplification transistor54by a transfer transistor52b.

The amplification transistor54outputs the pixel signal S12corresponding to the amount of charge transferred from the transfer transistor52aor the transfer transistor52bto the selection transistor55. The selection transistor55outputs the pixel signal S12to the read wiring56. The pixel signal S12is transmitted to the pixel signal processing circuit13via the read wiring56. A potential of each of the photodiodes51aand51bis reset by the reset transistor53.

A pixel50cillustrated inFIG.5Cis an example of a so-called pulse wide modulation (PWM) pixel. In the pixel50c, a slope signal S11a, which is one of the pixel control signals S11, is input to a gate of a P-channel MOS transistor59. The MOS transistor59is connected in series with the amplification transistor54. The selection transistor55outputs a PWM pixel signal S12indicating a comparison result between an output of the MOS transistor59and an output of the amplification transistor54to the read wiring56. The pixel signal S12is transmitted to the pixel signal processing circuit13via the read wiring56.

In a pixel50dillustrated inFIG.5D, photodiodes51ato51ceach include a photoelectric conversion film511, a transparent electrode512, and a lower electrode513. The photoelectric conversion film511is an organic photoelectric conversion film or an inorganic photoelectric conversion film. The transparent electrode512is arranged on an upper surface of the photoelectric conversion film511. The lower electrode513is arranged on the upper surface of the photoelectric conversion film511. That is, the transparent electrode512is interposed between the transparent electrode512and the lower electrode513. For example, the photoelectric conversion film511controls a voltage of the transparent electrode512to implement a global shutter.

Charges photoelectrically converted by the photoelectric conversion film511of the photodiodes51ato51care transferred to the amplification transistor54by the transfer transistors52ato52c, respectively. The amplification transistor54outputs the pixel signal S12according to an amount of charge accumulated in the photodiode51to the selection transistor55. The selection transistor55outputs the pixel signal S12to the read wiring56. The pixel signal S12is transmitted to the pixel signal processing circuit13via the read wiring56. A potential of each photodiode is reset by the reset transistor53.

A pixel50eillustrated inFIG.5Eis an example of a dynamic vision sensor (DVS) pixel that outputs a change in brightness. The pixel50eincludes a logarithmic conversion circuit510, a buffer circuit520, a subtraction circuit530, and a quantization circuit540.

The logarithmic conversion circuit510includes the photodiode51, an N-channel MOS transistor514, a P-channel MOS transistor515, and an N-channel MOS transistor516. The photodiode51and the MOS transistor514are connected in series. Furthermore, the MOS transistor515and the MOS transistor516are also connected in series. Moreover, a gate of the MOS transistor514is connected to a drain of the MOS transistor515and a drain of the MOS transistor516. In the logarithmic conversion circuit510, the charge photoelectrically converted by the photodiode51is converted into a logarithmic output voltage Vlog.

The buffer circuit520includes a P-channel MOS transistor521and a P-channel MOS transistor522. The MOS transistor521and the MOS transistor522are connected in series. The buffer circuit520outputs a source follower voltage VSF obtained by performing impedance conversion on the voltage Vlog input to a gate of the MOS transistor522.

The subtraction circuit530includes a P-channel MOS transistor531, a P-channel MOS transistor532, an N-channel MOS transistor533, and capacitors534and535. The MOS transistor532and the MOS transistor533are connected in series. The capacitor534is connected to a gate of the MOS transistor532. The MOS transistor531and the capacitor535are connected in parallel between the gate and a drain of the MOS transistor532. The subtraction circuit530outputs a differential voltage Vdiff from a previous signal.

The quantization circuit540includes a P-channel MOS transistor541, an N-channel MOS transistor542, a P-channel MOS transistor543, and an N-channel MOS transistor544. The MOS transistor541and the MOS transistor542are connected in series. Furthermore, the MOS transistor543and the MOS transistor544are also connected in series. In the quantization circuit540, the differential voltage Vdiff input to a gate of each of the MOS transistor541and the MOS transistor543is compared with two thresholds. Thereafter, a comparison result (VO(+) and VO(−)) is transmitted as the pixel signal S12to the pixel signal processing circuit13via the read wiring56. The pixel signal processing circuit13determines “+1”, “0”, and “−1” on the basis of the pixel signal S12.

The pixels arrayed in the pixel array unit11are not limited to the pixels50ato50eillustrated inFIGS.5A to5E. For example, in the pixel array unit11, a so-called convolution pixel to add the pixel signals S12of the respective pixels may be arrayed. Furthermore, in addition to the CMOS image sensor and the DVS described above, a polarization sensor or a multispectral sensor may be arrayed in the pixel array unit11.

The polarization sensor further includes a diffraction element that polarizes light incident on the photodiode51. In contrast, the multispectral sensor further includes a color filter that color-separates the light incident on the photodiode51.

FIG.6is a diagram illustrating an example of a circuit configuration of an analog to digital converter (ADC) included in the pixel signal processing circuit13. The ADC illustrated inFIG.6includes a plurality of comparators131, a plurality of counters132, and a plurality of latch circuits133.

The pixel signal S12of the pixel50corresponding to any one of the pixels50ato50edescribed above is input to a non-inverted input terminal of the comparator131. A ramp signal RAMP of a triangular wave is input to an inverted input terminal. Each comparator131outputs a comparison result between the pixel signal S12and the ramp signal RAMP. Each counter132is connected to an output terminal of the comparator131. Each counter132counts a change time of an output level of the comparator131. Each latch circuit133holds a count result of each counter132.

Note that, the ADC included in the pixel signal processing circuit13is not limited to a single-slope ADC illustrated inFIG.6. The pixel signal processing circuit13may include, for example, a pixel ADC that processes the pixel signal S12for each pixel, a column ADC that counts a comparison time of a plurality of comparators131with one counter132, a double integration ADC including an integration circuit, a successive approximation (SAR) ADC, a ΔΣ ADC or the like. Furthermore, resolution of the ADC may be appropriately selected within a range of 1 bit to 12 bits, for example.

FIG.7is a diagram illustrating a schematic circuit configuration of the memory array unit21. As illustrated inFIG.7, in the memory array unit21, a plurality of memory cells71is arranged in a two-dimensional manner. Each memory cell71is arranged in the vicinity of an intersection of signal wiring72and read wiring73. Note that, the memory cells71may be arranged in a three-dimensional manner. In this case, a plurality of memory cells71is arranged in the X direction, the Y direction, and the Z direction.

As the memory cell71, for example, a resistive random access memory (ReRAM), a phase change memory (PCM), a magnetoresistive random memory (MRAM), a ferroelectric random access memory (FeRAM) or the like may be applied. Furthermore, the memory cell71may be a static random access memory (SRAM) or a nonvolatile memory.

The memory cell71holds the memory value (for example, +1, −1, 0.5). The memory array unit21multiplies the memory value of each memory cell71by a signal value of the memory cell control signal S14input as the input signal from the CIM input control circuit22via the signal wiring72. Subsequently, the memory array unit21sequentially adds multiplication results in units of rows or columns via the read wiring73. Therefore, a digital convolution signal S15indicating a product-sum operation result is read to the CIM read circuit23. In a case where the convolution signal S15is of an analog type, the input signal via the signal wiring72is multiplied by the memory value, and then the charge is added thereto on the read wiring73, and the convolution signal S15is read to the CIM read circuit23. At that time, the input signals may be collectively input to the entire signal wiring72, and in a case where the CIM read circuit23is a column ADC, the convolution signals S15may be collectively read from the entire read wiring73.

FIG.8Ais a cross-sectional view illustrating an example of an arrangement relationship of the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15. InFIG.8A, the read wiring56is arranged on a bottom surface (rear surface) side of the first substrate101, and the read wiring73is arranged on an upper surface (front surface) side of the second substrate102. Therefore, the read wiring56and the read wiring73are arranged in such a manner that they are partially opposed to each other in the stacking direction (Z direction),

FIG.8Bis a cross-sectional view illustrating another example of an arrangement relationship of the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15. InFIG.8B, the read wiring56is arranged on the bottom surface (rear surface) side of the first substrate101, whereas the read wiring73is arranged on a bottom surface (rear surface) side of the second substrate102. Therefore, the read wiring73is arranged so as to be opposed to the read wiring56with the second substrate102interposed therebetween. InFIG.8B, in a case where the second substrate102is an insulating substrate such as a glass substrate, a shield is preferably provided. Furthermore, since the first substrate101and the second substrate102are stacked, the second substrate102is preferably thin in order to make the imaging device1compact. However, it is preferable that the second substrate102is formed by using a material suitable for shielding interference noise between the read wiring56and the read wiring73, and a thickness sufficient for noise shielding is secured.

According to this embodiment described above, the first substrate101on which the pixel array unit11is formed and the second substrate102on which the memory array unit21is formed are stacked. A transmission distance of the pixel signal S12from the pixel array unit11to the memory array unit21is shortened by a stacked arrangement of the pixel array unit11and the memory array unit21. Therefore, reduction in power of the imaging device1may be implemented. Furthermore, the above-described stacked arrangement contributes to downsizing of the layout of an entire chip, and this downsizing also contributes to the reduction in power of the imaging device1.

In contrast, when the pixel array unit11and the memory array unit21are arranged in a stacked manner, there is a possibility that interference noise occurs between the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15.

Therefore, in this embodiment, the read wiring56and the read wiring73are arranged so as to intersect each other. That is, the output direction of the pixel signal S12is made intersect the output direction of the convolution signal S15. Therefore, the interference noise between the read wiring56and the read wiring73may be reduced. As a result, a quality of both the pixel signal S12and the convolution signal S15is improved, so that operation accuracy of DNN may be improved.

Second Embodiment

Hereinafter, a second embodiment will be described focusing on differences from the first embodiment. In this embodiment, components similar to those of the first embodiment are denoted by the same reference numerals, and are not described in detail.

FIGS.9A to9Gare diagrams illustrating an example of a circuit layout of an imaging device according to the second embodiment. Note that, only the pixel control circuit12, the pixel signal processing circuit13, the logic circuit15, the CIM input control circuit22, and the CIM read circuit23are illustrated on the second substrate102in each drawing for convenience of space, and other circuits are not illustrated.

In this embodiment, as illustrated inFIGS.9A to9G, the output direction of the pixel signal S12is parallel to the output direction of the convolution signal S15. That is, the read wiring56(output wiring) of the pixel signal S12is parallel to the read wiring73(output wiring) of the convolution signal S15.

Moreover, in this embodiment, metal shield wiring81is arranged between the first substrate101and the second substrate102in order to suppress the interference noise generated between the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15. The metal shield wiring81includes metal such as aluminum (Al), copper (Cu), or tungsten (W), for example. A potential of the metal shield wiring81may be a power supply potential of the first substrate101or the second substrate102, or may be a ground potential. In consideration of power supply noise, the metal shield wiring81is preferably grounded.

Comparing the layout illustrated inFIG.9Awith the layout illustrated inFIG.2A, the position of the CIM input control circuit22and the position of the CIM read circuit23are switched on the second substrate102.

Comparing the layout illustrated inFIG.9Bwith the layout illustrated inFIG.2B, the position of the CIM input control circuit22and the position of the CIM read circuit23are switched on the second substrate102.

Furthermore, inFIG.9B, a shape of the plane region of the memory array unit21is different from that in the layout illustrated inFIG.9A. InFIG.9A, the plane region of the memory array unit21is a rectangle with a short side in the X direction and a long side in the Y direction. In contrast, regarding the plane region illustrated inFIG.9B, the plane region of the memory array unit21is a rectangle with a long side in the X direction and a short side in the Y direction.

In this embodiment also, the plane region of the memory array unit21may be a square, and is determined according to a specification of the product-sum operation. For example, in a case where the number of output channels of the convolution signal S15is large, a large number of lines of the read wiring73are required. In this case, the rectangle of the memory array unit21illustrated inFIG.9Ais preferable.

Comparing the layout illustrated inFIG.9Cwith the layout illustrated inFIG.2C, the position of the CIM input control circuit22and the position of the CIM read circuit23are switched on the second substrate102. In this layout also, the center of the memory array unit21is shifted in the X direction from the center of the pixel array unit11, but the center position of the pixel array unit11and the center position of the memory array unit21are only required to be optimized according to the layout of the signal wiring and power supply wiring.

Comparing the layout illustrated inFIG.9Dwith the layout illustrated inFIG.2D, the position of the CIM input control circuit22and the position of the CIM read circuit23are different on the second substrate102. The CIM input control circuit22is arranged in the output direction of the convolution signal S15. In contrast, the CIM read circuit23is arranged between the memory array unit21and the pixel signal processing circuit13b. In this embodiment also, the output direction of the pixel signal S12may be multiple directions including the +X direction and the −X direction. Furthermore, the processing of the pixel signal S12may be distributed to the pixel signal processing circuit13aand the pixel signal processing circuit13baccording to the output direction of the pixel signal S12.

Comparing the layout illustrated inFIG.9Ewith the layout illustrated inFIG.2E, the position of the CIM input control circuit22and the position of the CIM read circuit23are switched on the second substrate102. In this embodiment also, as illustrated in this layout, the output directions of the pixel signal S12and the convolution signal S15may be multiple directions.

InFIG.9F, as in the layout illustrated inFIG.2F, the pixel signal S12is transmitted toward a central portion of the pixel array unit11, that is, toward a central portion of the first substrate1010. Furthermore, the pixel signal processing circuit13is arranged in a central portion of the second substrate102. Therefore, the pixel array unit11and the pixel signal processing circuit13are electrically connected to each other at the central portion of the first substrate101and the second substrate102, respectively.

Comparing the layout illustrated inFIG.9Gwith the layout illustrated inFIG.2G, the position of the CIM input control circuit22and the position of the CIM read circuit23are switched on the second substrate102. In this embodiment also, a tiling structure in which a plurality of memory array units21is arrayed in the Y direction on the second substrate102may be adopted. Furthermore, in this embodiment also, a tiling structure in which the plurality of memory array units21is arrayed not only in the Y direction but also in the X direction may be adopted (refer toFIG.3A), and the CIM read circuit23may be provided for each memory array unit21(refer toFIG.3B).

FIGS.10A to10Fare cross-sectional views illustrating an example of an arrangement relationship of the metal shield wiring81with respect to the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15.

InFIG.10A, a width W1of the read wiring56is wider than a width W2of the read wiring73. Therefore, a width W3of the metal shield wiring81is the same as that of the wider read wiring56. Note that, in a case where the width W2of the read wiring73is wider than the width W1of the read wiring56, the width W3of the metal shield wiring81is the same as the width W2of the read wiring73.

InFIG.10B, the width W3of the metal shield wiring81is the widest among the read wiring56, the read wiring73, and the metal shield wiring81. In this case, the interference noise may be further reduced as compared with the read wiring73illustrated inFIG.10A.

InFIG.10C, the metal shield wiring81is multilayer wiring in which metal shield wiring81aand metal shield wiring81bare stacked. The metal shield wiring81aand the metal shield wiring81bare arranged so as to be shifted from each other in the Y direction in such a manner that they are partially overlap each other. Therefore, a gap between the metal shield wiring and the metal shield wiring is eliminated between the read wiring56and the read wiring73. In this case, the interference noise may be further reduced as compared with the read wiring73illustrated inFIG.10B. Note that, the number of layers of the metal shield wiring81is not limited to two, and may be three or more.

InFIG.10D, the number of lines of the read wiring56is larger than that of the read wiring73. Furthermore, the width W2of the read wiring73is wider than the width W1of the read wiring56. In a case where the number of lines is different between the read wiring56and the read wiring73in this manner, the width W3of the metal shield wiring81is the same as or wider than the width of the wider read wiring (the read wiring73inFIG.10D) in which the interference noise is likely to occur. As a result, the interference noise may be effectively reduced even when the number of lines is different between the read wiring56and the read wiring73.

InFIG.10E, a center pitch P1of the read wiring56is smaller than a center pitch P2of the read wiring73. Furthermore, the width W2of the read wiring73is wider than the width W1of the read wiring56. In a case where the center pitch is different between the read wiring56and the read wiring73in this manner, the width W3of the metal shield wiring81is the same as or wider than the width of the wider read wiring (the read wiring73inFIG.10E) in which the interference noise is likely to occur. Moreover, a center pitch P3of the metal shield wiring81is also the same as the center pitch of the wider read wiring. As a result, the interference noise may be effectively reduced even when the center pitch is different between the read wiring56and the read wiring73.

InFIG.10F, the width W2of the read wiring73is wider than the width W1of the read wiring56. Moreover, an interval D1between the read wiring56and the metal shield wiring81is larger than an interval D2between the read wiring73and the metal shield wiring81. In a case where the width is different between the read wiring56and the read wiring73in this manner, the metal shield wiring81is arranged near the wider read wiring (the read wiring73inFIG.10E) in which the interference noise is likely to occur. As a result, the interference noise may be more effectively reduced as compared to a case where the interval D1is equal to the interval D2, that is, as compared with a mode in which the metal shield wiring81is arranged between the read wiring56and the read wiring73.

FIG.11is a plane view illustrating another example of the arrangement relationship of the metal shield wiring81with respect to the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15.

InFIG.10Cdescribed above, the metal shield wiring81band the metal shield wiring81bextend in the X direction in parallel to the read wiring56and the read wiring73. In contrast, inFIG.11, the metal shield wiring81aand the metal shield wiring81bextend in the Y direction perpendicular to the read wiring56and the read wiring73. That is, the metal shield wiring81aand the metal shield wiring81bare perpendicular to the output direction of the image signal S13and the convolution signal S15.

Furthermore, inFIG.11, the metal shield wiring81aand the metal shield wiring81bare arranged so as to be shifted from each other in the X direction in such a manner that they are partially overlap each other. Therefore, a gap between the metal shield wiring and the metal shield wiring is eliminated between the read wiring56and the read wiring73. Accordingly, the interference noise may be further reduced.

FIG.12Ais a cross-sectional view illustrating an example of an arrangement relationship of the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15in this embodiment. InFIG.12A, the read wiring56is arranged on a bottom surface side of the first substrate101, and the read wiring73is arranged on an upper surface side of the second substrate102. Therefore, the read wiring56and the read wiring73are arranged so as to be opposed to each other in the stacking direction (Z direction) with the metal shield wiring81interposed therebetween.

FIG.12Bis a cross-sectional view illustrating another example of an arrangement relationship of the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15. InFIG.12B, the read wiring56is arranged on the bottom surface (rear surface) side of the first substrate101, whereas the read wiring73is arranged on a bottom surface (rear surface) side of the second substrate102. Therefore, the read wiring73is arranged so as to be opposed to the read wiring56with the second substrate102and the metal shield wiring81interposed therebetween. In this case also, it is preferable that the second substrate102is formed by using a material suitable for shielding the interference noise between the read wiring56and the read wiring73, and a thickness sufficient for noise shielding is secured as in the arrangement illustrated inFIG.8B.

In this embodiment described above also, since the first substrate101and the second substrate102are stacked as in the first embodiment, the transmission distance of the pixel signal S12from the pixel array unit11to the memory array unit21is shortened. Therefore, reduction in power of the imaging device1may be implemented. Furthermore, the above-described stacked arrangement contributes to downsizing of the layout of an entire chip, and this downsizing also contributes to the reduction in power of the imaging device1.

In contrast, in this embodiment, since the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15are parallel to each other, there is a possibility that interference noise occurs between the read wiring56and the read wiring73.

Therefore, in this embodiment, the metal shield wiring81is arranged between the read wiring56and the read wiring73. Therefore, interference noise between the read wiring56and the read wiring73may be reduced. As a result, a quality of both the pixel signal S12and the convolution signal S15is improved, so that operation accuracy of DNN may be improved.

Note that, the metal shield wiring81described in the second embodiment may be provided in the imaging device1according to the first embodiment described above. In this case, the interference noise between the read wiring56and the read wiring73may be further reduced.

Third Embodiment

Hereinafter, a third embodiment will be described focusing on differences from the first embodiment. In this embodiment, components similar to those of the first embodiment are denoted by the same reference numerals, and are not described in detail.

FIGS.13A to13Dare diagrams illustrating an example of a circuit layout of an imaging device according to the third embodiment.

InFIGS.13A to13D, the pixel array unit11is arranged on the first substrate101. Furthermore, on the second substrate102, the memory array unit21, the CIM input control circuit22, and the CIM read circuit23are arranged. Moreover, the imaging device according to this embodiment also includes a third substrate103. On the third substrate103, the pixel control circuit12, the pixel signal processing circuit13, and the logic circuit15are arranged.

InFIG.13A, third substrate103is stacked between the first substrate101and the second substrate102. Furthermore, the pixel signal processing circuit13includes a single-slope ADC that processes the pixel signal processing circuit13in units of pixel columns.

Also inFIG.13B, similarly toFIG.13A, the third substrate103is stacked between the first substrate101and the second substrate102. In contrast, the pixel signal processing circuit13includes a pixel ADC that processes the pixel signal processing circuit13for each pixel. Therefore, an area of the pixel signal processing circuit13in the third substrate103is larger than the area of the pixel signal processing circuit13illustrated inFIG.13A.

FIG.13Cis the same asFIG.13Aexcept that the positions of the second substrate102and the third substrate103are switched. That is, inFIG.13C, the second substrate102is stacked between the first substrate101and the third substrate103.

FIG.13Dis the same asFIG.13Bexcept that the positions of the second substrate102and the third substrate103are switched. In this embodiment, as long as the first substrate101on which the pixel array unit11is mounted is arranged in the uppermost layer, the stacking order of the second substrate102and the third substrate103may be switched.

FIG.14Ais a cross-sectional view illustrating an example of an arrangement relationship of the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15in this embodiment. As illustrated inFIGS.13A and13B, in a case where the third substrate103is stacked between the first substrate101and the second substrate102, as illustrated inFIG.14A, the read wiring56and the read wiring73are arranged in such a manner that they are partially opposed to each other in the stacking direction with the third substrate103interposed therebetween.

Furthermore, on the third substrate103, the signal wiring80for transmitting the image signal S13processed by the pixel signal processing circuit13to the CIM input control circuit22is formed. In order to reduce interference noise between the signal wiring80and the read wiring73, the signal wiring80is also preferably perpendicular to the read wiring73similarly to the read wiring56.

FIG.14Bis a cross-sectional view illustrating another example of an arrangement relationship of the read wiring56of the pixel signal S12and the read wiring73of the convolution signal S15in this embodiment. As illustrated inFIGS.13C and13D, in a case where the second substrate102is stacked between the first substrate101and the third substrate103, the read wiring56and the read wiring73are arranged in such a manner that they are partially opposed to each other in the stacking direction (Z direction). Note that, in this case also, similarly to the read wiring56, the signal wiring80is preferably perpendicular to the read wiring73. Therefore, the interference noise between the signal wiring80and the read wiring73may be reduced. Note that, in this embodiment, the circuit elements forming the imaging device may be arranged on four or more substrates stacked on one another. In this case, if the first substrate101on which the pixel array unit11is mounted is arranged in the uppermost layer, the arrangement of other substrates may be in random order.

According to this embodiment described above, since the first substrate101, the second substrate102, and the third substrate103are stacked, the transmission distance of the pixel signal S12from the pixel array unit11to the memory array unit21is shortened. Therefore, reduction in power of the imaging device1may be implemented.

Furthermore, in this embodiment, as in the first embodiment, since the read wiring56and the read wiring73intersect each other, the interference noise between the read wiring56and the read wiring73may be reduced. As a result, especially, a quality of both the pixel signal S12and the convolution signal S15is improved, so that operation accuracy of DNN may be improved.

Fourth Embodiment

FIG.15is a block diagram illustrating a configuration of an imaging device according to a fourth embodiment. An imaging device4according to this embodiment further includes a switch41in addition to the components of the imaging device1according to the first embodiment.

The switch41is arranged between the pixel signal processing circuit13and the CIM input control circuit22.

In a case where a product-sum operation is performed on image data, the switch41connects the pixel signal processing circuit13to the CIM input control circuit22on the basis of the control of the logic circuit15. Furthermore, in a case where the image signal S13is output to the outside of the imaging device4, the switch41connects the pixel signal processing circuit13to the input/output unit33on the basis of the control of the logic circuit15. In this case, the image signal S13is output to the outside via the input/output unit33. Note that, in this embodiment, the switch41is provided between the pixel signal processing circuit13and the CIM input control circuit22, but may be provided in the CIM input control circuit22.

In this embodiment described above, the switch41may switch an output destination of the image signal S13generated by the pixel signal processing circuit13to the CIM input control circuit22or the input/output unit33. Therefore, a destination of the image signal S13may be selected according to a purpose of use.

Fifth Embodiment

FIG.16is a diagram illustrating an example of a configuration of an electronic device according to a fifth embodiment. An electronic device200according to this embodiment is a camera system, and includes an imaging device210, a lens220, a drive circuit (DRV)230, and a signal processing circuit (PRC)240as illustrated inFIG.16.

Any one of the imaging devices according to the first to fourth embodiments described above may be applied to the imaging device210. The lens220forms an image of incident light (image light) on an imaging surface.

The drive circuit230includes a timing generator (not illustrated) that generates various timing signals including a start pulse and a clock pulse that drive a circuit in the imaging device210, and drives the imaging device210with a predetermined timing signal.

Furthermore, the signal processing circuit240performs predetermined signal processing on an output signal of the imaging device210. The image signal processed by the signal processing circuit240is recorded in a recording medium such as a memory, for example. Image information recorded on the recording medium is hard-copied by a printer or the like. Furthermore, the image signal processed by the signal processing circuit240is displayed as a moving image on a monitor including a liquid crystal display or the like.

According to this embodiment described above, in the electronic device200such as a digital still camera, the imaging device according to each of the embodiments described above may be mounted as the imaging device210, thereby implementing a highly accurate imaging function.

Application Example to Mobile Body

The technology according to an embodiment of the present disclosure (the present technology) may be applied to various products. For example, the technology according to an embodiment of the present disclosure may also be implemented as a device mounted on any type of mobile body such as an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot.

FIG.17is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

The vehicle control system12000includes a plurality of electronic control units connected to each other via a communication network12001. In the example depicted inFIG.17, the vehicle control system12000includes a driving system control unit12010, a body system control unit12020, an outside-vehicle information detecting unit12030, an in-vehicle information detecting unit12040, and an integrated control unit12050. Furthermore, as a functional configuration of the integrated control unit12050, a microcomputer12051, a sound/image output section12052, and an in-vehicle network interface (I/F)12053are illustrated.

The driving system control unit12010controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit12010functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

The body system control unit12020controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit12020functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit12020. The body system control unit12020receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The outside-vehicle information detecting unit12030detects information about the outside of the vehicle including the vehicle control system12000. For example, the outside-vehicle information detecting unit12030is connected with an imaging section12031. The outside-vehicle information detecting unit12030makes the imaging section12031image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit12030may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section12031is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section12031can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section12031may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit12040detects information about the inside of the vehicle. The in-vehicle information detecting unit12040is, for example, connected with a driver state detecting section12041that detects the state of a driver. The driver state detecting section12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section12041, the in-vehicle information detecting unit12040may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

The microcomputer12051can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040, and output a control command to the driving system control unit12010. For example, the microcomputer12051can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

In addition, the microcomputer12051can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040.

In addition, the microcomputer12051can output a control command to the body system control unit12020on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030. For example, the microcomputer12051can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit12030.

The sound/image output section12052transmits an output signal of at least one of a sound or an image to an output device capable of visually or auditorily notifying an occupant of the vehicle or the outside of the vehicle of information. In the example inFIG.17, an audio speaker12061, a display section12062, and an instrument panel12063are illustrated as the output device. The display section12062may, for example, include at least one of an on-board display or a head-up display.

FIG.18is a diagram depicting an example of the installation position of the imaging section12031.

InFIG.18, the imaging section12031includes imaging sections12101,12102,12103,12104, and12105.

The imaging sections12101,12102,12103,12104, and12105are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle12100as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section12101provided to the front nose and the imaging section12105provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle12100. The imaging sections12102and12103provided to the sideview mirrors obtain mainly an image of the sides of the vehicle12100. The imaging section12104provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle12100. The imaging section12105provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally,FIG.18depicts an example of photographing ranges of the imaging sections12101to12104. An imaging range12111represents the imaging range of the imaging section12101provided to the front nose. Imaging ranges1211212113respectively represent the imaging ranges of the imaging sections12102and12103provided to the sideview mirrors. An imaging range12114represents the imaging range of the imaging section12104provided to the rear bumper or the back door. A bird's-eye image of the vehicle12100as viewed from above is obtained by superimposing image data imaged by the imaging sections12101to12104, for example.

At least one of the imaging sections12101to12104may have a function of obtaining distance information. For example, at least one of the imaging sections12101to12104may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer12051can determine a distance to each three-dimensional object within the imaging ranges12111to12114and a temporal change in the distance (relative speed with respect to the vehicle12100) on the basis of the distance information obtained from the imaging sections12101to12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle12100and which travels in substantially the same direction as the vehicle12100at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer12051can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

For example, the microcomputer12051can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections12101to12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer12051identifies obstacles around the vehicle12100as obstacles that the driver of the vehicle12100can recognize visually and obstacles that are difficult for the driver of the vehicle12100to recognize visually. Then, the microcomputer12051determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer12051outputs a warning to the driver via the audio speaker12061or the display section12062, and performs forced deceleration or avoidance steering via the driving system control unit12010. The microcomputer12051can thereby assist in driving to avoid collision.

At least one of the imaging sections12101to12104may be an infrared camera that detects infrared rays. The microcomputer12051can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections12101to12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections12101to12104as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer12051determines that there is a pedestrian in the imaged images of the imaging sections12101to12104, and thus recognizes the pedestrian, the sound/image output section12052controls the display section12062so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section12052may also control the display section12062so that an icon or the like representing the pedestrian is displayed at a desired position.

An example of the vehicle control system to which the technology according to an embodiment of the present disclosure can be applied has been described above. The technology according to an embodiment of the present disclosure can be applied to, for example, the imaging section12031in the configuration described above. Specifically, the imaging devices according to the first to fourth embodiments may be applied to the imaging section12031. By applying the technology according to an embodiment of the present disclosure, an imaged image with an imaging performance of low noise may be obtained, so that an image quality may be improved.

Note that, the present technology may have the following configurations.

(1) An imaging device including:a first substrate on which a pixel array unit that outputs a pixel signal obtained by photoelectrically converting incident light in a first direction is arranged; anda second substrate on which a memory array unit that outputs a convolution signal indicating a result of a product-sum operation of an input signal based on the pixel signal in a second direction is arranged, in whichthe first substrate and the second substrate at least partially overlap each other.

(2) The imaging device according to (1), in which the first direction intersects the second direction.

(3) The imaging device according to (1), in whichthe first direction is parallel to the second direction,the imaging device further including: metal shield wiring arranged between the first substrate and the second substrate.

(4) The imaging device according to any one of (1) to (3), in which at least one of the pixel signal or the convolution signal is an analog signal.

(5) The imaging device according to any one of (1) to (4), further including:a pixel control circuit that controls the pixel array unit;a pixel signal processing circuit that processes the pixel signal read from the pixel array unit;a CIM input control circuit that controls the memory array unit; anda CIM read circuit that processes the convolution signal read from the memory array unit.

(6) The imaging device according to (5), in whichthe pixel control circuit is arranged in a direction parallel to the first direction,the pixel signal processing circuit is arranged in a direction perpendicular to the first direction,the CIM input control circuit is arranged in a direction parallel to the second direction, andthe CIM read circuit is arranged in a direction perpendicular to the second direction.

(7) The imaging device according to (5), further including: a third substrate on which the pixel control circuit and the pixel signal processing circuit are arranged.

(8) The imaging device according to (7), in which the third substrate is arranged between the first substrate and the second substrate, or the second substrate is arranged between the first substrate and the third substrate.

(9) The imaging device according to (5), in which on the second substrate, the pixel control circuit and the CIM read circuit are arranged so as to be opposed to each other with the memory array unit interposed between the pixel control circuit and the CIM read circuit, and the pixel signal processing circuit and the CIM input control circuit are arranged so as to be opposed to each other with the memory array unit interposed between the pixel signal processing circuit and the CIM input control circuit.

(10) The imaging device according to any one of (1) to (9), in which a plurality of the memory array units is arrayed in at least one of the first direction or the second direction.

(11) The imaging device according to (2), in which a plane region of the memory array unit is a rectangle, and the second direction is a long side direction of the rectangle.

(12) The imaging device according to (3), in which a plane region of the memory array unit is a rectangle, and the second direction is a short side direction of the rectangle.

(13) The imaging device according to (5), in which the pixel array unit and the pixel signal processing circuit are electrically connected to each other at a central portion of the first substrate and a central portion of the second substrate, respectively.

(14) The imaging device according to (3), in whicha width of first read wiring for reading the pixel signal is different from a width of second read wiring for reading the convolution signal, anda width of the metal shield wiring is the same as or wider than a width of wider read wiring between the first read wiring and the second read wiring.

(15) The imaging device according to (14), in which the metal shield wiring is multilayer wiring, and each metal shield wiring partially overlaps with each metal shield wiring.

(16) The imaging device according to (14), in which the metal shield wiring is arranged near wider read wiring between the first read wiring and the second read wiring.

(17) The imaging device according to claim (14), in which the metal shield wiring is perpendicular to the first read wiring and the second read wiring.

(18) The imaging device according to (5), further including:an input/output unit that inputs and outputs a signal; anda switch that switches an output destination of an image signal generated by the pixel signal processing circuit to the CIM input control circuit or the input/output unit.

(19) An electronic device including: an imaging device including a first substrate on which a pixel array unit that outputs a pixel signal obtained by photoelectrically converting incident light in a first direction is arranged, and a second substrate on which a memory array unit that outputs a convolution signal indicating a result of a product-sum operation of an input signal based on the pixel signal in a second direction is arranged, in which the first substrate and the second substrate at least partially overlap each other.

(20) A signal processing method including:outputting a pixel signal obtained by photoelectrically converting incident light in a first direction by a pixel array unit arranged on a first substrate; andoutputting a convolution signal indicating a result of a product-sum operation of an input signal based on the pixel signal in a second direction by a memory array unit arranged on a second substrate at least partially overlapping the first substrate.

REFERENCE SIGNS LIST

1,4Imaging device11Pixel array unit12Pixel control circuit13Pixel signal processing circuit21Memory array unit22CIM input control circuit23CIM read circuit33Input/output unit41Switch56Read wiring73Read wiring81Metal shield wiring101First substrate102Second substrate103Third substrate