Patent ID: 12222876

DETAILED DESCRIPTION OF THE EMBODIMENTS

The following clearly and completely describes the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely some rather than all of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without inventive efforts shall belong to the scope of protection of the present disclosure.

Disclosed in the embodiments of the present disclosure are a method and an apparatus for generating information based on a FIFO memory, a device and a medium, so as to increase the usage efficiency of the FIFO memory. For ease of understanding, the following introduces a system architecture to which the technical solutions of the present disclosure are applicable.FIG.1is a schematic structural diagram of a system for generating information based on a FIFO memory disclosed in an embodiment of the present disclosure. FromFIG.1, it can be determined that the synchronous FIFO components can be divided into the following parts when being implemented by hardware: a write address generation component Wr_addr, a read address generation component Rd_addr, a storage component Memory, a credit score generation component Credit, a component Cr_empty for generating a FIFO empty signal by means of a credit score, and a component Cr_full for generating a FIFO full signal by means of a credit score. Referring to Table 1, the interface signals of the synchronous FIFO components are described as follows:

TABLE 1Input/singaloutputwidthDescriptionClkRstclkInput[0]input clockrstInput[0]reset signal, active highData inputdinInput[width_data-1:0]write datawr_enInput[0]write data enableData outputrd_enInput[0:0]read data enabledoutoutput[width_data-1:0]read dataEmpty/full flagfulloutput[0:0]Fifo full flag signalafulloutput[0:0]Fifo almost full flag signalemptyoutput[0:0]Fifo empty flag signalaemptyoutput[0:0]Fifo almost empty flag signalCredit mechanism interfacewr_credit_user_defineinput[7:0]user defined write credit scoreunitwr_credit_1output[7:0]write credit score, with unit ofcalculation as Bytewr_credit_4output[7:0]write credit score, with unit ofcalculation as 4 Bytewr_credit_16output[7:0]write credit score, with unit ofcalculation as 16 Bytewr_credit_useroutput[7:0]write credit score, with unit ofcalculation as defined by userrd_credit_user_defineinput[7:0]user defined read credit scoreunitrd_credit_1output[7:0]read credit score, with unit ofcalculation as Byterd_credit_4output[7:0]read credit score, with unit ofcalculation as 4 Byterd_credit_16output[7:0]read credit score, with unit ofcalculation as 16 Byterd_credit_useroutput[7:0]read credit score, with unit ofcalculation as defined by user

The components inFIG.1are described below with reference to Table 1:1. write address generation component Wr_addr: this component generates, according to an input write enable wr_en signal, an address for writing data into a storage component. After the reset is completed, the write address is 0. When the wr_en is high, the data is written into the current Memory address, and the write address plus 1 is used as the data address for the next writing. Automatic zero clearing is performed when the write address reaches a maximum;2. read address generation component rd_addr: this component generates, according to an input read enable rd_en signal, an address for reading data from the storage component. After the reset is completed, the read address is 0. When the rd_en is high, the current read Memory address is assigned to the read address of the following-stage storage component, and the read address plus 1 is used as the address for the next data reading. Automatic zero clearing is performed when the read address reaches a maximum;3. storage component Memory: this component invokes or generates a synchronous dual-port static random access memory, and this storage component may be a Random Access Memory (RAM);4. credit score generation component Credit: this component executes the method for generating information described hereinafter, and generates a write credit score and a read credit score;5. component Cr_empty for generating the FIFO empty signal by means of the credit score: this component generates an empty state signal or an almost empty state signal according to the write credit score and the read credit score calculated by the credit score generation component Credit;6. component Cr_full for generating the FIFO full signal by means of the credit score: this component generates a full state signal or an almost full state signal according to the write credit score and the read credit score calculated by the credit score generation component Credit.

The method for generating information based on a FIFO memory in the present solution will be specifically described below.

FIG.2is a schematic flowchart of a method for generating information based on a FIFO memory disclosed in an embodiment of the present disclosure. The method includes:S101: a read address and a write address of a current FIFO memory are acquired;S102: a read data enable signal value and a write data enable signal value of the current FIFO memory are acquired;specifically, in this embodiment, the read address and the read data enable signal value are acquired from the read address generation component rd_addr, and the write address and the write data enable signal value are acquired from the write address generation component Wr_addr. And, the read data enable signal value is determined according to a read data enable signal rd_en, and in a case that a received data enable signal rd_en is high, the read data enable signal value is 1, in a case that the received data enable signal is not high, the read data enable signal value is 0; similarly, the write data enable signal value is determined according to a write data enable signal wr_en, and in a case that the received write data enable signal wr_en is high, the write data enable signal value is 1, in a case that the received write data enable signal is not high, the write data enable signal value is 0. In this embodiment, the case where S101is executed first and then S102is executed is merely taken as an example for description, and the execution sequence of the two steps is not specifically limited, for example, the read data enable signal value and the write data enable signal value may be acquired first, then the read address and the write address are acquired, alternatively, the read data enable signal value, the write data enable signal value, the read address and the write address may also be acquired at the same time.S103: a write credit score and a read credit score of the current FIFO memory are determined by a total capacity of the FIFO memory, and the read address, the write address, the read data enable signal value and the write data enable signal value; and the write credit score represents the number of data sets that can be written into the FIFO memory normally; and the read credit score represents the number of data sets that can be read from the FIFO memory normally;in this embodiment, after data is written into the FIFO memory, the write address is greater than the read address; however, as data is continuously written, newly written data may overwrite the written address, and at this time, the write address starts from an initial address, and the situation where the read address is greater than the write address occurs. Therefore, in this embodiment, both cases are considered sufficiently for the process of determining the write credit score and the read credit score.

In this embodiment, the process of determining the write credit score of the current FIFO memory is as follows:it is judged whether the write address is less than the read address; in a case that the write address is less than the read address, the write credit score is determined according to the read address, the write address, the read data enable signal value, the write data enable signal value and a first determination rule; in a case that the write address is not less than the read address, the write credit score is determined according to the total capacity, the read address, the write address, the read data enable signal value, the write data enable signal value and a second determination rule;In some embodiments, in the present solution, the write credit score is determined by the first determination rule, and the first determination rule is: the write credit score=the read address−the write address+the read data enable signal value−the write data enable signal value; in the present solution, the write credit score is determined by the second determination rule, and the second determination rule is: the write credit score=the total capacity−the write address+the read address+the read data enable signal value−the write data enable signal value.

In this embodiment, the process of determining the read credit score of the current FIFO memory is as follows:it is judged whether the write address is less than the read address; in the case that the write address is less than the read address, the read credit score is determined according to the total capacity, the read address, the write address, the read data enable signal value, the write data enable signal value and a third determination rule; in the case that the write address is not less than the read address, the read credit score is determined according to the read address, the write address, the read data enable signal value, the write data enable signal value and a fourth determination rule.In some embodiments, in the present solution, the read credit score is determined by the third determination rule, and the third determination rule is: the read credit score=the total capacity+the write address−the read address−the read data enable signal value+the write data enable signal value; in the present solution, the read credit score is determined by the fourth determination rule, and the fourth determination rule is: the read credit score=the write address−the read address−the read data enable signal value+the write data enable signal value.S104: the write credit score and the read credit score are sent to a preceding-stage device, so that the preceding-stage device reads and writes data according to the write credit score and the read credit score.

From the described solutions, it can be determined that, in the method and the apparatus for generating the information based on the FIFO memory, device and medium provided by the embodiments of the present disclosure, the write credit score and the read credit score of the current FIFO memory are determined by the total capacity of the FIFO memory, and the read address, the write address, the read data enable signal value and the write data enable signal value of the FIFO memory; and the write credit score represents the number of the data sets that can be written into the FIFO memory normally; and the read credit score represents the number of the data sets that can be read from the FIFO memory normally; and after sending the write credit score and the read credit score to the preceding-stage device, the preceding-stage device can learn, according to the write credit score and the read credit score, the number of the data sets that can be written into and read from the current FIFO memory normally, and read and write data according to the write credit score and the read credit score, thereby implementing traffic control of the system, ensuring that data does not overflow and is not jammed, and increasing the usage efficiency of the FIFO memory.

In this embodiment, a credit mechanism is a method for controlling data traffic. In the present solution, the write credit score represents the number of data sets that can be written into the synchronous FIFO normally, the read credit score represents the number of data sets that can be read from the synchronous FIFO normally, and a following stage feeds back, to an upper stage, the number of data which can be received or sent in real time or regularly, so as to realize traffic control of the whole system, and ensure that data does not overflow and is not jammed. Furthermore, in the present solution, the units of the data sets are different; if the unit value of the data sets is 1 Byte, it is represented in the present solution by the suffix of credit_1, and if the unit value of the data sets is 4 Byte/16 Byte, it is represented by the suffix of credit_4/credit_16; meanwhile, the present solution also supports a user to define the data size according to usage requirements, which is represented by the suffix of credit_user.

Therefore, in the present solution, when sending the write credit score and the read credit score to the preceding-stage device, the unit value of the data sets needs to be determined; the unit value is used for representing the number of bytes of data in each data set; and then the write credit score and the read credit score based on the each unit value are determined, and the write credit score and the read credit score based on the each unit value are sent to the preceding-stage device. And when determining the write credit score and the read credit score based on the each unit value, the specific scheme is to calculate a ratio of the write credit score to the each unit value, and round down the ratio to obtain the write credit score based on the each unit value, and calculate a ratio of the read credit score to the each unit value, and round down the ratio to obtain the read credit score based on the each unit value.

For example, the read address is set as rd_addr, the write address is set as wr_addr, the read data enable signal value is set as rd_en, and the write data enable signal value is set as wr_en. In addition, before a synchronous FIFO memory is used, a total capacity of the FIFO memory is defined, which is denoted as fifo_capa with the unit of byte.

1. The process of calculating a write credit score wr_credit is as follows:first, comparing the wr_addr and the rd_addr;if wr_addr=>rd_addr:wr_credit_1=fifo_capa−wr_addr+rd_addr+rd_en−wr_en.If wr_addr<rd_addr:wr_credit_1=rd_addr−wr_addr+rd_en−wr_en.

In this case, the calculated wr_credit_1 is a write credit score based on the unit value of 1, and other write credit scores are calculated in the following manners:wr_credit_4=wr_credit_¼, rounded down;wr_credit_16=wr_credit_ 1/16, rounded down; andwr_credit_user=wr_credit_1/wr_credit_user, rounded down.

2. The process of calculating a read credit score rd_credit is as follows:first, comparing the wr_addr and the rd_addr;if wr_addr=>rd_addr:rd_credit_1=wr_addr−rd_addr−rd_en+wr_en;if wr_addr<rd_addr:rd_credit_1=fifo_capa+wr_addr−rd_addr−rd_en+wr_en.

In this case, the calculated rd_credit_1 is a read credit score based on the unit value 1, and other read credit scores are calculated in the following manners:rd_credit_4=rd_credit_¼, rounded down; andrd_credit_16=rd_credit_ 1/16, rounded down; andrd_credit_user=rd_credit_1/wr_credit_user, rounded down.

It should be noted that, in this embodiment, after the write credit score and the read credit score of the current FIFO memory are determined, in a case that the read credit score is 0, an empty state signal is generated as 1, and in a case that the read credit score is 1, an almost empty state signal is generated as 1; and in a case that the write credit score is 0, a full state signal is generated as 1, and in a case that the write credit score is 1, an almost full state signal is generated as 1. It should be noted that the empty state signal, the almost empty state signal, the full state signal and the almost full state signal are all 0 by default, and are correspondingly set to be 1 only when the foregoing conditions are satisfied.

That is to say, for the Cr_empty component described above, when rd_credit_1=0 (rd_credit_1 being 0 represents that no data can be read out at this time), FIFO is in an empty state, and an empty signal is 1. When rd_credit_1=1 (rd_credit_1 being 1 represents that there is only one piece of data that can be read out at this time), FIFO is an almost empty state, and an aempty signal is 1. For the Cr_full component described above, when wr_credit_1=0 (wr_credit_1 being 0 represents that no data can be written in at this time), FIFO is in a full state, and a full signal is 1. When wr_credit_1=1 (wr_credit_1 being 1 represents that there is only one data space into which data can be written at this time), FIFO is in an almost full state, and an afull signal is 1. The empty state signal, the almost empty state signal, the full state signal and the almost full state signal generated in the present solution may also be sent to a preceding-stage device, and the preceding-stage device may still read and write data according to the foregoing signals.

In conclusion, it can be determined that the present solution essentially provides a synchronous FIFO memory having a credit mechanism interface, read and write ends generate independent credit scores and user-defined credit scores are supported. The empty and almost empty signals of the FIFO memory can be generated by means of read credit scores, and the full and almost full signals of the FIFO memory can be generated by means of write credit scores. The method allows the preceding-stage device to directly learn, by means of read and write credit scores, how many data sets can be read from and written into the FIFO memory, without the need of separate calculation by an external device, simplifying a calculation process of an external interface signal; in addition, the system, such as a PCIe, which supports a credit mechanism can be directly connected, improving the reusability and reliability of a synchronous FIFO component, increasing the development efficiency of an entire System on Chip (SOC), further improving product competitiveness.

The following describes an apparatus for generating information, a device and a medium provided in the embodiments of the present disclosure. For the apparatus for generating information, device, and medium described below and the information generation method described above, reference may be made to each other.

FIG.3is a schematic structural diagram of an apparatus for generating information based on a FIFO memory disclosed in an embodiment of the present disclosure, including a first acquisition component11, configured to acquire a read address and a write address of a current FIFO memory;a second acquisition component12, configured to acquire a read data enable signal value and a write data enable signal value of the current FIFO memory;a determination component13, configured to determine a write credit score and a read credit score of the FIFO memory by a total capacity of the FIFO memory, and the read address, the write address, the read data enable signal value and the write data enable signal value; and the write credit score represents the number of data sets that can be written into the FIFO memory normally; and the read credit score represents the number of data groups that can be read from the FIFO memory normally; anda sending component14, configured to send the write credit score and the read credit score to a preceding-stage device, so that the preceding-stage device reads and writes data according to the write credit score and the read credit score.

The determination component includes:a first judgment unit, configured to judge whether the write address is less than the read address; in a case that the write address is less than the read address, trigger a first determination unit; in a case that the write address is not less than the read address, trigger a second determination unit;the first determination unit, configured to determine the write credit score according to the read address, the write address, the read data enable signal value, the write data enable signal value and a first determination rule;the second determination unit, configured to determine the write credit score according to the total capacity, the read address, the write address, the read data enable signal value, the write data enable signal value and a second determination rule;a second judgment unit, configured to judge whether the write address is less than the read address; in the case that the write address is less than the read address, trigger a third determination unit, and in the case that the write address is not less than the read address, trigger a fourth determination unit;the third determination unit, configured to determine the read credit score according to the total capacity, the read address, the write address, the read data enable signal value, the write data enable signal value and a third determination rule; andthe fourth determination unit, configured to determine the read credit score according to the read address, the write address, the read data enable signal value, the write data enable signal value and a fourth determination rule.

The first determination unit is specifically configured to:determine the write credit score by the first determination rule, and the first determination rule is:the write credit score=the read address−the write address+the read data enable signal value−the write data enable signal value;correspondingly, the second determination unit is specifically configured to:determine the write credit score by the second determination rule, and the second determination rule is:the write credit score=the total capacity−the write address+the read address+the read data enable signal value−the write data enable signal value.

The third determination unit is specifically configured to:determine the read credit score by the third determination rule, and the third determination rule is:the read credit score=the total capacity+the write address−the read address−the read data enable signal value+the write data enable signal value;correspondingly, the fourth determination unit is specifically configured to:determine the read credit score by the fourth determination rule, and the fourth determination rule is:the read credit score=the write address−the read address−the read data enable signal value+the write data enable signal value.

The apparatus further includes:a first signal generation component, configured to generate an empty state signal as 1 in a case that the read credit score is 0, and generate an almost empty state signal as 1 in a case that the read credit score is 1; anda second signal generation component, configured to generate a full state signal as 1 in a case that the write credit score is 0, and generate an almost full state signal as 1 in a case that the write credit score is 1.

The sending component includes:a fifth determination unit, configured to determine a unit value of each of the data sets; and the unit value is used for representing the number of bytes of data in each of the data sets;a sixth determination unit, configured to determine the write credit score and the read credit score based on each unit value; anda sending unit, configured to send the write credit score and the read credit score based on the each unit value to the preceding-stage device.

The sixth determination unit includes:a first calculation subunit, configured to calculate a ratio of the write credit score to the each unit value, and round down the ratio to obtain the write credit score based on the each unit value; anda second calculation subunit, configured to calculate a ratio of the read credit score to the each unit value, and round down the ratio to obtain the read credit score based on the each unit value.

FIG.4is a schematic structural diagram of an electronic device disclosed in an embodiment of the present disclosure, including:a memory21for storing a computer program; anda processor22for implementing steps of the method for generating the information based on the FIFO memory in the foregoing embodiments when executing the computer program.

In this embodiment, the device may be a Personal Computer (PC), and may also be a terminal device such as a smart phone, a tablet computer, a palmtop computer, and a portable computer.

The device may include a memory21, a processor22and a bus23.

The memory21includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a hard disk, a multimedia card, a card-type memory (for example, an SD or DX memory), a magnetic memory, a magnetic disk, an optical disk, and so on. The memory21may in some embodiments be an internal storage unit of the device, for example, a hard disk of the device. In other embodiments, the memory21may also be an external storage device of the device, for example, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, and a Flash Card that are equipped on the device. Further, the memory21may also include both an internal storage unit of the device and an external storage device. The memory21may be used not only to store application software installed in the device and various types of data, such as a program code for executing the method for generating the information, but also to temporarily store data that has been output or is to be output.

In some embodiments, the processor22may be a Central Processing Unit (CPU), a controller, a micro controller, a microprocessor, or another data processing chip, and is configured to run a program code stored in the memory21or process data, such as a program code for executing the information generation method.

The bus23may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of representation, only one bold line is shown inFIG.4, which does not mean there is only one bus or one type of bus.

Further, the device may also include a network interface24. The network interface24may optionally include a wired interface and/or a wireless interface (such as a VVi-Fi interface and a Bluetooth interface), and is generally used to establish a communication connection between the device and another electronic device.

Optionally, the device may further include a user interface25. The user interface25may include a Display and an input unit such as a Keyboard. The user interface25may optionally further include a standard wired interface and a standard wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch liquid crystal display, an Organic Light-Emitting Diode (OLED) touch device, or the like. The display may also be appropriately referred to as a display screen or a display unit, and is configured to display information processed in the device and display a visual user interface.

FIG.4only shows a device including components21-25. A person skilled in the art may understand that the structure shown inFIG.4does not limit the device, and may include fewer or more components than those shown in the figure, or a combination of some components, or have a different component arrangement.

Further provided in the embodiments of the present disclosure is a computer readable storage medium, and the computer readable storage medium stores a computer program, and when the computer program is executed by a processor, steps of the method for generating the information based on the FIFO memory according to the described embodiments are implemented.

The storage medium may include any medium that can store program codes, such as a USB flash disk, a mobile hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The embodiments in this description are described in a progressive manner, each embodiment focuses on a part different from other embodiments, and reference may be made to each other for the same or similar parts of the embodiments.

The above descriptions of the disclosed embodiments enable a person skilled in the art to implement or use the present disclosure. Various modifications to these embodiments would have readily occurred to those skilled in the art. The general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure will not be limited to the embodiments shown herein but is to be in accord with the widest scope consistent with the principles and novel features disclosed herein.