Patent ID: 12255112

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIGS.1A through1Lare cross-sectional views schematically illustrating a process flow for fabricating SoIC structures in accordance with some embodiments of the present disclosure.

Referring toFIG.1A, a wafer10including semiconductor dies is provided. The semiconductor dies may be logic dies, System-on-Chip (SoC) dies or other suitable semiconductor dies. The wafer10may include a semiconductor substrate12(e.g., a semiconductor substrate), through substrate vias14embedded in the semiconductor substrate12, an interconnect structure16disposed on the semiconductor substrate12, and a bonding dielectric layer18adisposed on the interconnect structure16, wherein the through substrate vias14are electrically connected to the interconnect structure116. The semiconductor substrate12of the semiconductor wafer10may include a crystalline silicon wafer. The semiconductor substrate12may include various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for n-type Fin-type Field Effect Transistors (FinFETs) and/or p-type FinFETs. In some alternative embodiments, the semiconductor substrate12may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

The through substrate vias14may be formed by forming recesses in the semiconductor substrate12by, for example, etching, milling, laser techniques, a combination thereof, or the like. The through substrate vias14may be via-first TSVs, via-middle TSVs, and via-last TSVs. A thin barrier layer may be conformally deposited over the front side of the semiconductor substrate12and in the openings, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, or the like. The barrier layer may comprise a nitride or an oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, or the like. A conductive material is deposited over the thin barrier layer and in the openings. The conductive material may be formed by an electro-chemical plating process, CVD, ALD, PVD, a combination thereof, or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. Excess conductive material and barrier layer may be removed from the front side of the semiconductor substrate12by, for example, chemical mechanical polishing. Thus, in some embodiments, the through substrate vias14may comprise a conductive material and a thin barrier layer between the conductive material and the semiconductor substrate12.

The interconnect structure16may include one or more dielectric layers (for example, one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, or the like) and interconnect conductors embedded in the one or more dielectric layers, and the interconnect conductors are electrically connected to the semiconductor devices (e.g., FinFETs) formed in the semiconductor substrate12and/or the through substrate vias14. The material of the one or more dielectric layers may include silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable dielectric material. The interconnect conductors may include metallic conductors. For example, the interconnect conductors include copper conductors, copper pads, aluminum pads or combinations thereof. In some embodiments, the through substrate vias14may extend through one or more layers of the interconnect structure16and into the semiconductor substrate12.

The material of the bonding dielectric layer18amay be silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable dielectric material. The bonding dielectric layer18amay be formed by depositing a dielectric material through a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process).

Referring toFIG.1AandFIG.1B, the semiconductor wafer10is singulated by a wafer sawing process performed along scribe lines SL1such that singulated semiconductor dies20are obtained. Each of the singulated semiconductor dies20may include a semiconductor substrate12, through substrate vias14embedded in the semiconductor substrate12, an interconnect structure16disposed on the semiconductor substrate12, and a bonding dielectric layer18adisposed on the interconnect structure16. As illustrated inFIG.1B, the through substrate vias14are buried in the semiconductor substrate12and the interconnect structure16. The through semiconductor vias14are not revealed from a back surface of the semiconductor substrate12at this stage.

Referring toFIG.1C, the singulated semiconductor dies20are picked-up and placed on a carrier C1in a side-by-side manner such that front surfaces of the singulated semiconductor dies20are bonded to the carrier C1. The carrier C1may be a semiconductor wafer such as a silicon wafer. The carrier C1may have a round top-view shape and a size of a silicon wafer. For example, carrier C1may have an 8-inch diameter, a 12-inch diameter, or the like. The singulated semiconductor dies20are bonded to the carrier C1through a chip-to-wafer bonding process. A bonding process is performed to bond the bonding dielectric layers18aof the singulated semiconductor dies20with the carrier C1. The bonding process may be a direct bonding process. After performing the above-mentioned direct bonding process, a semiconductor-to-dielectric bonding interface such as silicon-to-nitride (Si—SiNx) bonding interface may be formed between the bonding dielectric layer18aand the carrier C1.

Referring toFIG.1D, an insulating encapsulation material is formed over the carrier C1to cover the singulated semiconductor dies20which are bonded with the carrier C1. The insulating encapsulation material may be a molding compound (e.g., epoxy or other suitable resin) formed through an over-molding process. The insulating encapsulation material fills the gaps between neighboring semiconductor dies20and covers back surfaces of the singulated semiconductor dies20. After forming the insulating encapsulation material over the carrier C1, the insulating encapsulation material and the semiconductor substrates12of the semiconductor dies20are partially remove such that the semiconductor substrates12of the semiconductor dies20are thinned and an insulating encapsulant22are formed to laterally encapsulate the semiconductor dies20. The insulating encapsulation material and the semiconductor substrate12of the semiconductor dies20may be partially remove through a planarization process such as a Chemical Mechanical Polish (CMP) process and/or a mechanical grinding process. After performing the above-mentioned planarization process, the thickness of the insulating encapsulant22is substantially equal to that of the semiconductor dies20. In other words, the top surface of the insulating encapsulant22is substantially level with back surfaces of the semiconductor dies20. As illustrated inFIG.1D, after performing the above-mentioned planarization process, the through semiconductor vias14are revealed from the back surfaces of the semiconductor substrates12at this stage. The through semiconductor vias14may protrude from the back surfaces of the semiconductor substrates12.

Referring toFIG.1E, a dielectric material may be formed over the back surfaces of the semiconductor substrates12and the top surface of the insulating encapsulant22to cover the revealed through semiconductor vias14. The dielectric material may be or include silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable dielectric material. A planarization process such as a Chemical Mechanical Polish (CMP) process and/or a mechanical grinding process may be performed to partially remove the dielectric material such that a planarization layer24is formed on the back surfaces of the semiconductor substrates12and the top surface of the insulating encapsulant22. The top surface of the planarization layer24is substantially level with top ends of the through semiconductor vias14.

After forming the planarization layer24, a bonding structure26including a bonding dielectric layer26aand bonding conductors26bembedded in the bonding dielectric layer26a. The material of the bonding dielectric layer26amay be silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable dielectric material, and the bonding conductors26bmay be conductive vias (e.g., copper vias), conductive pads (e.g., copper pads) or combinations thereof. The bonding structure26may be formed by depositing a dielectric material through a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process); patterning the dielectric material to form the bonding dielectric layer26aincluding openings or through holes; and filling conductive material in the openings or through holes defined in the bonding dielectric layer26ato form the bonding conductors26bembedded in the bonding dielectric layer26a. In some embodiments, the conductive material for forming the bonding conductors26bmay be formed through a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process) followed by a planarization process (e.g., a Chemical Mechanical Polish (CMP) process and/or a mechanical grinding process).

After forming the bonding structure26, semiconductor dies30are provided. The semiconductor dies30may be logic dies, System-on-Chip (SoC) dies or other suitable semiconductor dies. The semiconductor dies30and the semiconductor dies20may perform the same function or different functions. In some embodiments, the semiconductor dies30and the semiconductor dies30are System on Chip (SoC) dies. Each of the semiconductor dies30may include a semiconductor substrate32and an interconnect structure34disposed on the semiconductor substrate32respectively. Furthermore, bonding structures36may be formed on the interconnect structures34of the semiconductor dies30. The bonding structure36includes a bonding dielectric layer36aand bonding conductors36bembedded in the bonding dielectric layer36a. The material of the bonding dielectric layer36amay be silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0) or other suitable dielectric material, and the bonding conductors36bmay be conductive vias (e.g., copper vias), conductive pads (e.g., copper pads) or combinations thereof. The bonding structure36may be formed by depositing a dielectric material through a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process); patterning the dielectric material to form the bonding dielectric layer36aincluding openings or through holes; and filling conductive material in the openings or through holes defined in the bonding dielectric layer36ato form the bonding conductors36bembedded in the bonding dielectric layer36a. In some embodiments, the conductive material for forming the bonding conductors36bmay be formed through a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process) followed by a planarization process (e.g., a Chemical Mechanical Polish (CMP) process and/or a mechanical grinding process).

A bonding process (e.g., a chip-to-wafer bonding process) is performed to bond the bonding structures36formed on the semiconductor dies30with bonding regions of the bonding structure26. The bonding process may be a hybrid bonding process that includes dielectric-to-dielectric bonding and metal-to-metal bonding. After performing the above-mentioned bonding process, a dielectric-to-dielectric bonding interface is formed between the bonding dielectric layer26aand the bonding dielectric layer36a, and metal-to-metal bonding interfaces are formed between the bonding conductors26band bonding conductors36b. After performing the bonding process, the semiconductor dies30are electrically connected to the semiconductor dies20through the bonding structures36and the bonding structure26.

As illustrated inFIG.1E, the semiconductor dies30may be disposed above the semiconductor dies20. The lateral dimension (e.g., width and/or length) of the semiconductor dies20may be greater than the lateral dimension (e.g., width and/or length) of the semiconductor dies30. Since the bonding structures36are merely bonded with bonding regions of the bonding structure26, portions of the bonding dielectric layer26aare not covered by the bonding structures36. In some embodiments, at least one dummy die (not shown inFIG.1E) may be provided aside the semiconductor dies30and stacked over the semiconductor dies20.

ReferringFIG.1F, an insulating encapsulation material is formed over the semiconductor dies20and the insulating encapsulant22to cover the semiconductor dies30. The insulating encapsulation material may be a molding compound (e.g., epoxy or other suitable resin) formed through an over-molding process. The insulating encapsulation material fills the gaps between neighboring semiconductor dies30and laterally encapsulates the semiconductor dies30. After forming the insulating encapsulation material over the semiconductor dies20and the insulating encapsulant22, the insulating encapsulation material is partially removed until the semiconductor substrates32of the semiconductor dies30are revealed such that an insulating encapsulant40are formed. The insulating encapsulation material may be partially removed through a planarization process such as a Chemical Mechanical Polish (CMP) process and/or a mechanical grinding process. After performing the above-mentioned planarization process, the top surface of the insulating encapsulant40substantially levels with back surfaces of the semiconductor dies30.

Referring toFIG.1G, a carrier C2including a de-bonding layer42formed thereon is provided. In some embodiments, the carrier C2is a glass substrate, a ceramic carrier, or the like. The carrier C2may have a round top-view shape and a size of a glass substrate. For example, carrier C2may have an 8-inch diameter, a 12-inch diameter, or the like. The de-bonding layer42may be formed of a polymer-based material (e.g., a Light To Heat Conversion (LTHC) material), which may be subsequently removed along with the carrier C2. In some embodiments, the de-bonding layer42is formed of an epoxy-based thermal-release material. In other embodiments, the de-bonding layer42is formed of an ultra-violet (UV) glue. The de-bonding layer42may be dispensed as a liquid and cured. In alternative embodiments, the de-bonding layer42is a laminate film and is laminated onto the carrier C2. The top surface of the de-bonding layer42is substantially planar.

A bonding process (e.g., a wafer-to-wafer bonding process) is performed to bond the resulted structure formed on the carrier C1with the de-bonding layer42carried by the carrier C2. After the resulted structure formed on the carrier C1is bonded with the de-bonding layer42carried by the carrier C2, the top surface of the insulating encapsulant40and the back surfaces of the semiconductor dies30are in contact with the de-bonding layer42.

Referring toFIG.1GandFIG.1H, after the resulted structure formed on the carrier C1is bonded with the de-bonding layer42carried by the carrier C2, the carrier C1is de-bonded from the bonding dielectric layers18aand the insulating encapsulant22such that the bonding dielectric layers18aand the insulating encapsulant22are revealed.

Referring toFIG.1HandFIG.1I, the bonding dielectric layers18ais patterned to form openings such that the topmost interconnect conductors of the interconnect structures16are revealed by the openings formed in the bonding dielectric layers18a. The formation of the openings in the bonding dielectric layers18amay be performed through a photolithography process. A passivation layer44including openings formed therein may be formed to cover the bonding dielectric layers18asuch that the topmost interconnect conductors of the interconnect structures16revealed by the openings of the passivation layer44. The formation of the openings in the passivation layer44may be performed through a photolithography process. The width of the openings defined in the passivation layer44may be smaller than the width of the openings defined in the bonding dielectric layers18a. The passivation layer44may cover the top surfaces of the bonding dielectric layers18aand the insulating encapsulant22. The passivation layer44may further extend into the openings defined in the bonding dielectric layers18asuch that the passivation layer44is in contact with the topmost interconnect conductors of the interconnect structures16.

After forming the passivation layer44, conductive terminals46are formed over the passivation layer44. The conductive terminals46are electrically connected to the interconnect conductors of the interconnect structures16and protrude from the passivation layer44. Each of the conductive terminals46may respectively include a conductive pillar46aand a solder cap46bdisposed on the conductive pillar46a. The conductive pillars46afill the openings defined in the passivation layer44and protrude from the passivation layer44. The solder caps46bcovers the top surfaces of the conductive pillars46a. After forming the conductive terminals46, a chip probing process may be performed to measure the resistance of at least one through semiconductor via among the through semiconductor vias14such that fabrication yields can be increased. The chip probing process is described in accompany withFIGS.2A through2Cin detail. The formation of the conductive terminals46may include forming a seed layer (not shown) over the passivation layer44, forming a patterned mask (not shown) such as a photoresist layer over the seed layer, and then performing a plating process on the exposed seed layer. The patterned mask and the portions of the seed layer covered by the patterned mask are then removed, leaving the conductive terminals46. A reflow process may be further performed to re-shape the profile of the solder caps46a. In accordance with some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, Physical Vapor Deposition (PVD). The plating may be performed using, for example, electroless plating.

Referring toFIG.1IandFIG.1J, after performing the chip probing process, the solder caps46bare removed and a dielectric layer48is formed over the passivation layer44to cover the conductive pillars46a. In some embodiments, the dielectric layer48is formed of a polymer, which may be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In some other embodiments, the dielectric layer48is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or the like.

Referring toFIG.1JandFIG.1K, a frame mount process is performed such that the resulted structure carried by the carrier C2is mounted on a tape TP1carried by a frame. After performing the frame mount process, the dielectric layer48is attached on the tape TP1, and a de-bonding process is then performed such that the carrier C2is de-bonded from the semiconductor dies30and the insulating encapsulant40. After performing the de-bonding process, the back surfaces of the semiconductor dies30and the insulating encapsulant40are revealed. During the de-bonding process, the de-bonding layer42is also cleaned from the semiconductor dies30and the insulating encapsulant40. The de-bonding may be performed by irradiating a light such as UV light or laser on the de-bonding layer42to decompose the de-bonding layer42.

Referring toFIG.1KandFIG.1L, a tape TP2carried by another frame is provided, wherein an attachment film50is formed on the tape TP. The resulted structure carried by the tape TP1is transfer bonded onto the attachment film50. Then, a singulation process is performed along scribe lines SL2such that singulated SoIC structures100(i.e., device dies) are obtained. During the singulation process, the dielectric layer48, the passivation layer44, the insulating encapsulant22, the planarization layer24, the bonding structure26, the insulating encapsulant40and the attachment film50are cut along scribe lines SL2. In some embodiments, the insulating encapsulant22laterally encapsulates the semiconductor die20, wherein sidewalls of the insulating encapsulant40are substantially aligned with sidewalls of the insulating encapsulant22.

FIGS.2A through2Care diagrams schematically illustrating various test keys in accordance with some embodiments of the present disclosure.

Referring toFIG.2A, a test key60A configured to measure the resistance of the through semiconductor via14embedded in the semiconductor substrate12(shown inFIG.1I) is illustrated. The test key60A includes a first resistor62R, a first conductor62C1(e.g., a conductor wiring), a first probe pad62P, a second conductor64C1(e.g., a conductor wiring), a second probe pad64P, a third conductor66C, a third probe pad66P, a fourth conductor68C, and a fourth probe pad68P. The first probe pad62P is electrically connected to a first end (e.g., a bottom end) of the through semiconductor via14by the first resistor62R and the first conductor62C1. The second probe pad64P is electrically connected to the first end (e.g., a bottom end) of the through semiconductor via14by the second conductor64C1. The third probe pad66P is electrically connected to a second end (e.g., a top end) of the through semiconductor via14by the third conductor66C. The fourth probe pad68P is electrically connected to the second end (e.g., a top end) of the through semiconductor via14by the fourth conductor68C. In some embodiments, the first resistor62R is disposed at a first side (e.g., a back side) of the semiconductor substrate12(shown inFIG.1I), while the first probe pad62P, the second probe pad64P, the third probe pad66P and the fourth probe pad68P are disposed at a second side (e.g., a front side) of the semiconductor substrate12(shown inFIG.1I), and the first side is opposite to the second side. Furthermore, the first conductor62C1and the second conductor64C1are distributed at the first side (e.g., a back side) of the semiconductor substrate12(shown inFIG.1I), while the third conductor66C and the fourth conductor68C are distributed at the second side (e.g., a front side) of the semiconductor substrate12(shown inFIG.1I). The first probe pad62P may be electrically connected to the first conductor62C1by a conductor62C2(e.g., a through semiconductor via) penetrating through the semiconductor substrate12(shown inFIG.1I), and the second probe pad64P may be electrically connected to the second conductor64C1through a conductor64C2(e.g., a through semiconductor via) penetrating through the semiconductor substrate12(shown inFIG.1I). In some embodiments, the resistance of the first resistor62R is greater than the resistance of the through semiconductor via14. In some embodiments, the resistance of the first resistor62R is about more than 10 times of the resistance of the through semiconductor via14. For example, the resistance of the first resistor62R ranges from about 10 times to about 10000 or more times of the resistance of the through semiconductor via14. For example, the resistance of the through semiconductor via14is about 8 micro-Ohms (mΩ), and the resistance of the first resistor62R is about more than 80 mΩ.

Referring toFIG.2B, a test key60B configured to measure the resistance of the through semiconductor via14embedded in the semiconductor substrate12(shown inFIG.1I) is illustrated. The test key60B includes a first resistor62R, a first conductor62C1(e.g., a conductor wiring), a first probe pad62P, a second conductor64C1(e.g., a conductor wiring), a second probe pad64P, a third conductor66C, a second resistor66R, a third probe pad66P, a fourth conductor68C, and a fourth probe pad68P. The first probe pad62P is electrically connected to a first end (e.g., a bottom end) of the through semiconductor via14by the first resistor62R and the first conductor62C1. The second probe pad64P is electrically connected to the first end (e.g., a bottom end) of the through semiconductor via14by the second conductor64C1. The third probe pad66P is electrically connected to a second end (e.g., a top end) of the through semiconductor via14by the second resistor66R and the third conductor66C. The fourth probe pad68P is electrically connected to the second end (e.g., a top end) of the through semiconductor via14by the fourth conductor68C. In some embodiments, the first resistor62R is disposed at a first side (e.g., a back side) of the semiconductor substrate12(shown inFIG.1I), while the first probe pad62P, the second probe pad64P, the second resistor66R, the third probe pad66P and the fourth probe pad68P are disposed at a second side (e.g., a front side) of the semiconductor substrate12(shown inFIG.1I), and the first side is opposite to the second side. Furthermore, the first conductor62C1and the second conductor64C1are distributed at the first side (e.g., a back side) of the semiconductor substrate12(shown inFIG.1I), while the third conductor66C, the second resistor66R and the fourth conductor68C are distributed at the second side (e.g., a front side) of the semiconductor substrate12(shown inFIG.1I). The first probe pad62P may be electrically connected to the first conductor62C1through a conductor62C2(e.g., a through semiconductor via) penetrating through the semiconductor substrate12(shown inFIG.1I), and the second probe pad64P may be electrically connected to the second conductor64C1through a conductor64C2(e.g., a through semiconductor via) penetrating through the semiconductor substrate12(shown inFIG.1I). In some embodiments, the resistance of the first resistor62R is greater than the resistance of the through semiconductor via14. In some embodiments, the resistance of the first resistor62R is about more than 10 times of the resistance of the through semiconductor via14. For example, the resistance of the first resistor62R ranges from about 10 times to about 10000 or more times of the resistance of the through semiconductor via14. For example, the resistance of the through semiconductor via14is about 8 micro-Ohms (mΩ), and the resistance of the first resistor62R is about more than 80 mΩ. In some embodiments, the resistance of the second resistor66R is greater than the resistance of the through semiconductor via14. In some embodiments, the resistance of the second resistor66R is about more than 10 times of the resistance of the through semiconductor via14. For example, the resistance of the second resistor66R ranges from about 10 times to about 10000 or more times of the resistance of the through semiconductor via14. For example, the resistance of the through semiconductor via14is about 8 micro-Ohms (mΩ), and the resistance of the second resistor66R is about more than 80 mΩ. In some embodiments, the resistance of the first resistor62R may substantially equal to the resistance of the second resistor66R. In some other embodiments, the resistance of the first resistor62R may different from the resistance of the second resistor66R.

Referring toFIG.2C, a test key60C configured to measure the resistance of the through semiconductor via14embedded in the semiconductor substrate12(shown inFIG.1I) is illustrated. The test key60C includes a first conductor62C1(e.g., a conductor wiring), a first probe pad62P, a second conductor64C1(e.g., a conductor wiring), a second probe pad64P, a third conductor66C1, a second resistor66R, a third probe pad66P, a fourth conductor68C, and a fourth probe pad68P. The first probe pad62P is electrically connected to a first end (e.g., a bottom end) of the through semiconductor via14by the first conductor62C1. The second probe pad64P is electrically connected to the first end (e.g., a bottom end) of the through semiconductor via14by the second conductor64C1. The third probe pad66P is electrically connected to a second end (e.g., a top end) of the through semiconductor via14by the second resistor66R and the third conductor66C. The fourth probe pad68P is electrically connected to the second end (e.g., a top end) of the through semiconductor via14by the fourth conductor68C. In some embodiments, the first conductor62C1and the second conductor64C1are disposed at a first side (e.g., a back side) of the semiconductor substrate12(shown inFIG.1I), while the first probe pad62P, the second probe pad64P, the second resistor66R, the third probe pad66P and the fourth probe pad68P are disposed at a second side (e.g., a front side) of the semiconductor substrate12(shown inFIG.1I), and the first side is opposite to the second side. Furthermore, the first conductor62C1and the second conductor64C1are distributed at the first side (e.g., a back side) of the semiconductor substrate12(shown inFIG.1I), while the third conductor66C, the second resistor66R and the fourth conductor68C are distributed at the second side (e.g., a front side) of the semiconductor substrate12(shown inFIG.1I). The first probe pad62P may be electrically connected to the first conductor62C1through a conductor62C2(e.g., a through semiconductor via) penetrating through the semiconductor substrate12(shown inFIG.1I), and the second probe pad64P may be electrically connected to the second conductor64C1through a conductor64C2(e.g., a through semiconductor via) penetrating through the semiconductor substrate12(shown inFIG.1I). In some embodiments, the resistance of the through semiconductor via14can be roughly calculated based on the material (e.g., resistivity or sheet resistance) of the through semiconductor via14and the dimensions (width, height or cross-sectional area) of the through semiconductor via14, and the resistance of the second resistor66R is greater than the resistance of the through semiconductor via14. In some embodiments, the resistance of the second resistor66R is about more than 10 times of the resistance of the through semiconductor via14. For example, the resistance of the second resistor66R ranges from about 10 times to about 10000 or more times of the resistance of the through semiconductor via14. For example, the resistance of the through semiconductor via14is about 8 micro-Ohms (mΩ), and the resistance of the second resistor66R is about more than 80 mΩ.

When testing the test key60A,60B or60C (e.g., Kelvin test), two probes of a probe card contact the first probe pad62P and the third probe pad66P to supply a test voltage to the first probe pad62P. As shown inFIGS.2A through2C, a test current flows through the second probe pad64P, the through semiconductor via14, and the fourth probe pad68P. The probe card measures the test current to calculate the equivalent resistance between the first probe pad62P and the third probe pad66P. And then, the probe card measures the resistance of the through semiconductor via14according to the equivalent resistance between the first probe pad62P and the third probe pad66P. Since the equivalent resistance between the first probe pad62P and the third probe pad66P is resulted from the through semiconductor via14as well as the resistor62R and/or66R, the measurement of the resistance of through semiconductor via14can be precise.

In some embodiments, the resistor62R and/or the resistor66R may be formed in interconnect structures of stacked semiconductor dies. In some other embodiments, the resistor62R and/or the resistor66R of the test keys60A,60B and60C may be formed in an interconnect structure of a single semiconductor die. The arrangement of the62R and/or the resistor66R will be described in accompany withFIGS.3through7.

FIGS.3through7schematically illustrate various cross-sectional views of SoIC structures in accordance with some other embodiments of the present disclosure.

Referring toFIG.2AandFIG.3, the SoIC structure of the present embodiment includes a first semiconductor die20laterally encapsulated by an insulating encapsulant22, a second semiconductor die30laterally encapsulated by an insulating encapsulant40, and a test key60A (shown inFIG.2A) formed in the first semiconductor die20and the first semiconductor die30. The first semiconductor die20includes a first semiconductor substrate12, a first interconnect structure16disposed on the first semiconductor substrate12, and a through semiconductor via14embedded in the first semiconductor substrate12and the first interconnect structure16. The second semiconductor die30is disposed on and electrically connected to the first semiconductor die20. The second semiconductor die30includes a second semiconductor substrate32and a second interconnect structure34disposed on the second semiconductor substrate34. In the present embodiment, the test key60A (shown inFIG.2A) is distributed in the first interconnect structure16and the second interconnect structure34. The first conductor62C1, the first resistor62R and the second conductor64C1of the test key60A are distributed in the second interconnect structure34, and the conductor64C2of the test key60A is distributed in the first interconnect structure16. The first probe pad62P, the second probe pad64P, the third probe pad66P and the fourth probe pad68P of the test key60A are disposed over and electrically connected to the first interconnect structure16.

The first probe pad62P is electrically connected to a first end of the through semiconductor via14by the conductor64C2, the second conductor64C1as well as the first resistor62R. The conductor64C2is in the first interconnect structure16, and the second conductor64C1is in the second interconnect structure34. The second probe pad64P is electrically connected to the first end of the through semiconductor via14by at least the second conductor64C2. The third conductor66C is in the first interconnect structure16. The third probe pad66P is electrically connected to a second end of the through semiconductor via14by at least the third conductor66C. The fourth conductor68C is in the first interconnect structure16. The fourth probe pad68P is electrically connected to the second end of the through semiconductor via14by at least the fourth conductor68C.

As illustrated inFIG.3, the SoIC structure may further include a dummy die70laterally encapsulated by the insulating encapsulant40. Furthermore, Kelvin test may be performed to measure the resistance of the SoIC structure, and the Kelvin test may be performed by a probe card80.

ReferringFIG.2BandFIG.4, the SoIC structure of the present embodiment includes a first semiconductor die20laterally encapsulated by an insulating encapsulant22, a second semiconductor die30laterally encapsulated by an insulating encapsulant40, and a test key60B (shown inFIG.2B) formed in the first semiconductor die20and the first semiconductor die30. The first semiconductor die20includes a first semiconductor substrate12, a first interconnect structure16disposed on the first semiconductor substrate12, and a through semiconductor via14embedded in the first semiconductor substrate12and the first interconnect structure16. The second semiconductor die30is disposed on and electrically connected to the first semiconductor die20. The second semiconductor die30includes a second semiconductor substrate32and a second interconnect structure34disposed on the second semiconductor substrate34. In the present embodiment, the test key60B (shown inFIG.2B) is distributed in the first interconnect structure16and the second interconnect structure34. The first conductor62C1, the first resistor62R and the second conductor64C1of the test key60B are distributed in the second interconnect structure34, and the conductor64C2and the second resistor66R of the test key60B are distributed in the first interconnect structure16. The first probe pad62P, the second probe pad64P, the third probe pad66P and the fourth probe pad68P of the test key60A are disposed over and electrically connected to the first interconnect structure16.

The first probe pad62P is electrically connected to a first end of the through semiconductor via14by the conductor64C2, the second conductor64C1as well as the first resistor62R. The conductor64C2is in the first interconnect structure16, and the second conductor64C1is in the second interconnect structure34. The second probe pad64P is electrically connected to the first end of the through semiconductor via14by at least the second conductor64C2. The third conductor66C is in the first interconnect structure16. The third probe pad66P is electrically connected to a second end of the through semiconductor via14by the second resistor66R and the third conductor66C. The fourth conductor68C is in the first interconnect structure16. The fourth probe pad68P is electrically connected to the second end of the through semiconductor via14by at least the fourth conductor68C.

Referring toFIG.2CandFIG.5, the SoIC structure of the present embodiment includes a first semiconductor die20laterally encapsulated by an insulating encapsulant22, a second semiconductor die30laterally encapsulated by an insulating encapsulant40, and a test key60C (shown inFIG.2C) formed in the first semiconductor die20and the first semiconductor die30. The first semiconductor die20includes a first semiconductor substrate12, a first interconnect structure16disposed on the first semiconductor substrate12, and a through semiconductor via14embedded in the first semiconductor substrate12and the first interconnect structure16. The second semiconductor die30is disposed on and electrically connected to the first semiconductor die20. The second semiconductor die30includes a second semiconductor substrate32and a second interconnect structure34disposed on the second semiconductor substrate34. In the present embodiment, the test key60C (shown inFIG.2C) is distributed in the first interconnect structure16and the second interconnect structure34. The first conductor62C1and the second conductor64C1of the test key60B are distributed in the second interconnect structure34, and the conductor64C2and the second resistor66R of the test key60B are distributed in the first interconnect structure16. The first probe pad62P, the second probe pad64P, the third probe pad66P and the fourth probe pad68P of the test key60A are disposed over and electrically connected to the first interconnect structure16.

The first probe pad62P is electrically connected to a first end of the through semiconductor via14by the conductor64C2and the second conductor64C1. The conductor64C2is in the first interconnect structure16, and the second conductor64C1is in the second interconnect structure34. The second probe pad64P is electrically connected to the first end of the through semiconductor via14by at least the second conductor64C2. The third conductor66C is in the first interconnect structure16. The third probe pad66P is electrically connected to a second end of the through semiconductor via14by the second resistor66R and the third conductor66C. The fourth conductor68C is in the first interconnect structure16. The fourth probe pad68P is electrically connected to the second end of the through semiconductor via14by at least the fourth conductor68C.

Referring toFIG.4andFIG.6, the SoIC structure illustrated inFIG.6is similar with the SoIC structure illustrated inFIG.4except that both the first resistor62R and the second resistor66R are distributed in the second interconnect structure34.

In accordance with some other embodiments of the disclosure,

Referring toFIG.4andFIG.7, the SoIC structure illustrated inFIG.7is similar with the SoIC structure illustrated inFIG.4except that both the first resistor62R and the second resistor66R are distributed in the first interconnect structure16. In other words, the through semiconductor via14to be measured, the first resistor62R and the second resistor66R are distributed in the semiconductor die20.

Although the test keys illustrated in the above-mentioned embodiments are formed in SoIC structures, the test keys may be applied in Integrated Fan-Out (InFO) packages, Chip-on-Wafer-on Substrate (CoWoS) packages or other types of packages.

In the above-mentioned embodiments, at least one resistor (e.g., resistor62R and/or66R) with large resistance is implemented in measurement of resistance of the through semiconductor via, and the voltage drop resulted from the through semiconductor via as well as the at least one resistor. Accordingly, the at least one resistor facilitates the measurement of the resistance of the through semiconductor via, and the measurement of the resistance of through semiconductor via14can be precise.

FIG.8A through8Dschematically illustrate various cross-sectional views of a resistor in the test key in accordance with some embodiments of the present disclosure.FIG.9A through9Cschematically illustrate various top views of a resistor in the test key in accordance with some embodiments of the present disclosure.

As illustrated inFIG.8A, the resistor62R and/or66R distributed in the semiconductor die20and/or the semiconductor die30may include a single layered resistor pattern, wherein the resistor62R and/or66R may be a straight-line pattern having a constant width as shown inFIG.9A, a meandering pattern having a constant width as shownFIG.9Bor a meandering pattern having various widths D1and D2as shown inFIG.9C.

In some other embodiments, as illustrated inFIG.8B, the resistor62R and/or66R distributed in the semiconductor die20and/or the semiconductor die30may include a multi-layered resistor pattern, the multi-layered resistor pattern may include a first resistor pattern P1(e.g., a lower resistor pattern) and a second resistor pattern P2(e.g., an upper resistor pattern), wherein each the first resistor pattern P1and the second resistor pattern P2may be a straight-line pattern having a constant width as shown inFIG.9A, a meandering pattern having a constant width as shownFIG.9Bor a meandering pattern having various widths D1and D2as shown inFIG.9C. As illustrated inFIG.8B, each of the first resistor pattern P1and the second resistor pattern P2may include barrier layer B, and the material of the barrier may include Ta, TaN, Ti and/or TiN.

In another embodiments, as illustrated inFIG.8C, the resistor62R and/or66R distributed in the semiconductor die20and/or the semiconductor die30may include a multi-layered resistor pattern, the multi-layered resistor pattern may include a first resistor pattern P1(e.g., a lower resistor pattern), a second resistor pattern P2(e.g., a middle resistor pattern) and a third resistor pattern P3(e.g., an upper resistor pattern), wherein the first resistor pattern P1and the second resistor pattern P2are formed in the interconnect structure, and the third resistor pattern P3are aluminum pads or aluminum patterns formed over the interconnect structure.

In some alternative embodiments, as illustrated inFIG.8D, the resistor62R and/or66R distributed in the semiconductor die20and/or the semiconductor die30may include a multi-layered resistor pattern, the multi-layered resistor pattern may include a first resistor pattern P1(e.g., an upper resistor pattern), a second resistor pattern P2(e.g., a middle resistor pattern) and a third resistor pattern P3(e.g., a lower resistor pattern), wherein the first resistor pattern P1may include copper formed in the interconnect structure through BEOL processes, the second resistor pattern P1may include tungsten formed under the interconnect structure through (front end of line, MEOL) processes, and the third resistor pattern P3may include polysilicon formed under the interconnect structure through FEOL processes.

In accordance with some embodiments of the disclosure, a test key configured to measure resistance of a through semiconductor via in a semiconductor substrate is provided. The test key includes a first resistor, a first conductor, a first probe pad, a second conductor, a second probe pad, a third conductor, a third probe pad, a fourth conductor, and a fourth probe pad. The first probe pad is electrically connected to a first end of the through semiconductor via by the first resistor and the first conductor. The second probe pad is electrically connected to the first end of the through semiconductor via by the second conductor. The third probe pad is electrically connected to a second end of the through semiconductor via by the third conductor. The fourth probe pad is electrically connected to the second end of the through semiconductor via by the fourth conductor. In some embodiments, the first resistor is disposed at a first side of the semiconductor substrate, the first probe pad, the second probe pad, the third probe pad and the fourth probe pad are disposed at a second side of the semiconductor substrate, and the first side is opposite to the second side. In some embodiments, a resistance of the first resistor is greater than the resistance of the through semiconductor via. In some embodiments, a resistance of the first resistor is about more than 10 times of a resistance of the through semiconductor via. In some embodiments, the test key further includes a second resistor, wherein the third probe pad is electrically connected to the second end of the through semiconductor via by the second resistor and the third conductor. In some embodiments, the first resistor is disposed at a first side of the semiconductor substrate, the second resistor, the first probe pad, the second probe pad, the second resistor, the third probe pad and the fourth probe pad are disposed at a second side of the semiconductor substrate, and the first side is opposite to the second side. In some embodiments, the resistance of the second resistor is greater than the resistance of the through semiconductor via. In some embodiments, a resistance of the second resistor is about more than 10 times of a resistance of the through semiconductor via.

In accordance with some other embodiments of the disclosure, a first semiconductor die, a second semiconductor die and a test key is provided. The first semiconductor die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a through semiconductor via embedded in the first semiconductor substrate. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate and a second interconnect structure disposed on the second semiconductor substrate. The test key is in the first interconnect structure and the second interconnect structure. The test key includes a first resistor, a first conductor, a first probe pad, a second conductor, a second probe pad, a third conductor, a third probe pad, a fourth conductor and a fourth probe pad. The first resistor is in the first interconnect structure or the second interconnect structure. The first conductor is in the first interconnect structure and the second interconnect structure. The first probe pad is over the first interconnect structure, and the first probe pad is electrically connected to a first end of the through semiconductor via by the first resistor and the first conductor. The second conductor is in the first interconnect structure and the second interconnect structure. The second probe pad is over the first interconnect structure, and the second probe pad is electrically connected to the first end of the through semiconductor via by the second conductor. The third conductor is in the first interconnect structure. The third probe pad is over the first interconnect structure, and the third probe pad is electrically connected to a second end of the through semiconductor via by the third conductor. The fourth conductor is in the first interconnect structure. The fourth probe pad is over the first interconnect structure, and the fourth probe pad is electrically connected to the second end of the through semiconductor via by the fourth conductor. In some embodiments, a resistance of the first resistor is greater than a resistance of the through semiconductor via. In some embodiments, a resistance of the first resistor is about more than 10 times of a resistance of the through semiconductor via. In some embodiments, the structure further includes a second resistor in the first interconnect structure, wherein the third probe pad is electrically connected to the second end of the through semiconductor via by the second resistor and the third conductor. In some embodiments, a resistance of the second resistor is greater than a resistance of the through semiconductor via. In some embodiments, a resistance of the second resistor is about more than 10 times of a resistance of the through semiconductor via.

In accordance with some other embodiments of the disclosure, a semiconductor die, including a semiconductor substrate, an interconnect structure, a through semiconductor via and a test key is provided. The interconnect structure is disposed on the semiconductor substrate. The through semiconductor via is embedded in the semiconductor substrate and the interconnect structure. The test key is disposed in the interconnect structure. The test key includes a first resistor, a first conductor, a first probe pad, a second conductor, a second probe pad, a third conductor, a third probe pad, a fourth conductor, and a fourth probe pad. The first probe pad is electrically connected to a first end of the through semiconductor via by the first resistor and the first conductor. The second probe pad is electrically connected to the first end of the through semiconductor via by the second conductor. The third probe pad is electrically connected to a second end of the through semiconductor via by the third conductor. The fourth probe pad is electrically connected to the second end of the through semiconductor via by the fourth conductor. In some embodiments, a resistance of the first resistor is greater than a resistance of the through semiconductor via. In some embodiments, a resistance of the first resistor is about more than 10 times of a resistance of the through semiconductor via. In some embodiments, the semiconductor die further includes a second resistor in the first interconnect structure, wherein the third probe pad is electrically connected to the second end of the through semiconductor via by the second resistor and the third conductor. In some embodiments, a resistance of the second resistor is greater than a resistance of the through semiconductor via. In some embodiments, a resistance of the second resistor is about more than 10 times of a resistance of the through semiconductor via.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.