Patent ID: 12212310

DETAILED DESCRIPTION

GaN is a semiconductor process technology that has a superior figure-of-merit (FoM) compared to silicon process technology. Due to its superior FoM, a GaN-based power converter is typically operated at a much higher switching frequency to extract its full potential of achieving high power density. An electrical current-carrying path between a GaN power FET and its gate driver is the gate drive loop. At higher frequency the gate drive loop needs to be short. Higher switching frequency and fast switching characteristics of a GaN power FET require inductance of the gate drive loop to be very small. This necessitate that most of the gate drive circuit for the GaN power FET be monolithically integrated with the GaN power FET. If a semiconductor power switch and its driver are not on a same die, then parasitic elements, such as die-to-die or die-to-package inductances and capacitances limit the speed of operation. Therefore, if a GaN FET power switch and its GaN driver are made on the same die, i.e., both are fabricated in a GaN process, then potentially higher speed of operation and performance can be achieved.

Compared to a silicon-based power converter, a GaN-based power converter has a much lower limit in terms of a maximum gate voltage that it can tolerate. A conservative approach is to design the driver to operate at lower voltage such that worst-case operating voltage does not exceed the maximum gate voltage. However, the conservative approach is not a desirable approach because operating the GaN power FET at lower gate voltage relinquishes some of the benefit of GaN. The on resistance and the saturation current capability of the GaN power FET significantly suffer when the GaN power FET is operated at lower gate voltage. The above-mentioned constrains demand a low-cost monolithically-integrated GaN-based gate bias circuit for a driver with minimal external components which maintains a constant optimal gate bias voltage within the safe operating limit, and this needs to be done over process corner, temperature, and supply voltage variations.

Disclosed is a predominately GaN-based gate bias circuit for a GaN driver for a GaN power FET that is monolithically integrated with the GaN power FET. The predominately GaN-based gate bias circuit maintains optimal gate voltage over process, temperature and supply voltage variation with a minimum number of external components. In the illustrated embodiments of the predominately GaN-based gate bias circuit shown inFIGS.1-10, the components within the dotted line area108are GaN-based and are all monolithically integrated within a same die.

FIG.1is a simplified schematic of an electronic device102comprising a first embodiment of a gate bias circuit104for a GaN driver106. The GaN driver106is monolithically integrated on a single GaN die108with a GaN power FET110. The single GaN die108may be disposed in a microelectronic package (not shown). A GaN power switch120comprises the GaN driver106and the GaN power FET110.

A first embodiment of the gate bias circuit104comprises a first GaN resistor142having one end coupled to a ground supply terminal143and another end coupled to one end of a second GaN resistor144. Another end of the second GaN resistor144is coupled to a cathode of a GaN diode146and to one end of a bypass capacitor148. The other end of the bypass capacitor148is coupled to the ground supply terminal143. A first input voltage VREG149at the other end of the second GaN resistor144is coupled to the GaN driver106. An anode of the GaN diode146is coupled to a linear regulator150. The linear regulator150is coupled to a positive power supply terminal151that supplies VCCand to the ground power supply terminal143. The linear regulator150outputs a second input voltage VHI152to the GaN driver106. VHI152typically has a value of less than 30V. A fraction of VHI152occurs at a node153between the first GaN resistor142and the second GaN resistor144based on a resistance ratio of the resistors, and the fraction is fed back to the linear regulator150as a VFB154. The gate bias circuit104is composed of GaN devices on the single GaN die108except for the linear regulator150and the bypass capacitor148which are external to the single GaN die108. In one embodiment, the linear regulator150may be fabricated using silicon-based technology. In one embodiment, the linear regulator150is a low-dropout regulator.

An output terminal160of the GaN driver106is coupled to a gate terminal170of the GaN power FET110. A voltage VGATE169at the gate terminal170of the GaN power FET110needs to be maintained at a maximum allowable voltage without exceeding a safe operating limit to extract full potential of GaN technology. The GaN driver106is coupled to VHI152. The GaN driver106is also coupled to the ground supply terminal143. The GaN driver106typically receives low-voltage digital or pulse wave modulated signals from a controller (not shown). The GaN driver106creates an output signal having the same frequency and duty cycle as the signal from the controller but strong enough to handle capacitance of the GaN power FET110. The drain terminal171of the GaN power FET110is coupled to a high-voltage positive power supply terminal189that is coupled to a high-voltage supply VDD, and a source terminal173of the GaN power FET110is coupled to the ground supply terminal143. For example, VDDis between 200V and 600V.

The GaN driver106comprises a pre-driver stage180and a final stage181. The pre-driver stage180of the GaN driver106comprises high-side pre-driver182and low-side pre-driver184. The final stage181of the GaN driver106comprises a high-side GaN FET186and a low-side GaN FET188. An input terminal of the high-side pre-driver182receives a PDRV_H signal from the controller through an intermediate processing stage (not shown). The high-side pre-driver182receives VHI152generated by the gate bias circuit104. An output terminal of the high-side pre-driver182is coupled to a gate terminal190of the high-side GaN FET186of the final stage181. An input terminal of the low-side pre-driver184receives a PDRV_L signal from the controller through an intermediate processing stage (not shown). The low-side pre-driver184receives VREG149generated by the gate bias circuit104. An output terminal of the low-side pre-driver184is coupled to a gate terminal191of the low-side GaN FET188of the final stage181.

The voltage VREG149from the gate bias circuit104is coupled to a drain terminal192of the high-side GaN FET186of the final stage181of the GaN driver106. A source terminal193of the high-side GaN FET186constitutes the output terminal160of the GaN driver106. The source terminal193of high-side GaN FET186is coupled to a drain terminal194of the low-side GaN FET188and to the gate terminal170of the GaN power FET110. A source terminal195of the low-side GaN FET188is coupled to the ground supply terminal143. The GaN power FET110can be turned on and off through the GaN driver106when VREG149is high. Advantageously, the gate bias circuit104in accordance with the invention maintains VREG149constant over process, temperature and VCC151.

The GaN driver106needs a voltage VHI152that is higher than VREG149to overdrive the high-side GaN FET186of the final stage181. VHI152needs to be at least one threshold voltage VThigher than VREG149to ensure that the high-side GaN FET186is in triode region and VGATE169is close to VREG. The gate bias circuit104generates VHI152which is one diode drop higher than VREG149. VHItracks process and temperature because the GaN diode146tracks variation in process and temperature. The GaN diode146tracks variation in process and temperature because it is integrated within the single GaN die108, and in essence consists of a GaN HEMT device connected as a diode. Unlike known circuits, the gate bias circuit104in accordance with the invention includes a closed loop comprising an electrical current-carrying path from the linear regulator150through GaN diode146through GaN-die resistor144and back to the linear regulator. With the closed loop in accordance with the invention, VREG149is tightly regulated against load and temperature variations. On the other hand, with an open loop, regulation of an output voltage from a gate bias circuit is poor against load and temperature variations.

FIG.2is a simplified schematic of an electronic device202comprising a second embodiment of a gate bias circuit204for the GaN driver106. The second embodiment of the gate bias circuit304includes a linear regulator250which is the only active component outside the single GaN die108. In the second embodiment of the gate bias circuit204for a GaN driver106, the feedback voltage VFB154is equal to VREG149(6V in one example). In the second embodiment, a resistor divider (not shown) is integrated within the linear regulator250instead of within the single GaN die108. All performance characteristics are the same as the first embodiment shown inFIG.1.

FIG.3is a simplified schematic of an electronic device302comprising a third embodiment of the gate bias circuit304for the GaN driver106. The third embodiment of the gate bias circuit304includes a linear regulator350which is the only active component outside the single GaN die108. With the third embodiment of the gate bias circuit304, resistor311and resistor312are kept outside the single GaN die108such that VREG149can be varied based on requirement of the GaN process technology. The performance of the gate bias circuit304is the same as the first embodiment shown inFIG.1except that the VREG149and VGATEmay be set higher or lower by a user, by choosing the ratio of resistor311and resistor312as per the requirement of the GaN process technology.

FIG.4is a simplified schematic of an electronic device402comprising a fourth embodiment of the gate bias circuit404for a GaN driver106. The fourth embodiment of the gate bias circuit304includes a linear regulator450which is the only active component outside the single GaN die108. The fourth embodiment of the gate bias circuit304includes bypass capacitor148, GaN-die resistor411and GaN-die resistor412. Compared to the first embodiment shown inFIG.1, in the fourth embodiment there is a series460of n GaN diodes D1, . . . , Dn, and hence VHI152is n diodes above VREG149. This allows a higher overdrive voltage for the high-side GaN FET186, and hence potentially better performance. The number of diodes in the series460is carefully selected based on process technology limitations and characteristics. Specifically, care is exercised so that the gate-to-source voltage of the high-side GaN FET186does not exceed a maximum allowed value.

FIG.5is a simplified schematic of an electronic device502comprising a fifth embodiment of a gate bias circuit504for the GaN driver106. Advantageously, in the embodiment shown inFIG.5a shunt regulator520(also known as a shunt voltage regulator or as a shunt regulator diode) is the only external active component needed. The shunt regulator520is shown inFIG.5in the form of a Zener diode with a feedback input of VFB154. In one embodiment, the shunt regulator520may be fabricated using silicon-based technology. The shunt regulator520regulates a value of VREG149. Advantageously, VREG149is maintained constant over process, temperature and supply voltage. VHI152sits above VREG149in a similar fashion as with the other illustrated embodiments, but VCC-to-VHIfeeding is through a resistor R530. The capacitor540is for helping with stability of a shunt regulator520—resistor511loop, and is used if stability needs to be improved. The fifth embodiment includes bypass capacitor148, and a series560of n GaN diodes560D1, . . . , Dn. GaN-die resistor511and GaN-die resistor512are feedback voltage sense resistors, which provide a voltage at capacitor540as the feedback sense signal (VFB154) to the shunt regulator520.

FIG.6is a simplified schematic of an electronic device602comprising a sixth embodiment of a gate bias circuit604for the GaN driver106. The embodiment shown inFIG.6is a variation of the embodiment shown inFIG.5. In the sixth embodiment, a GaN HEMT610(internal to the single GaN die108) acts as a series pass element and produces VREG149at its source terminal. A gate of the GaN HEMT610is fed from a current source IBIAS615drawing current from the positive power supply voltage VCC. A voltage at the gate of the GaN HEMT610is controlled by a shunt regulator620so as to regulate VREG149even in the face of process, temperature or supply variations. The voltage at the gate of the GaN HEMT610is used as VHI152, and it is one VTabove VREG149. The sixth embodiment includes capacitor640, bypass capacitor648, GaN-die resistor611and GaN-die resistor612.

FIG.7is a simplified schematic of an electronic device702comprising a seventh embodiment of a gate bias circuit704for the GaN driver106. The seventh embodiment is a variation of the sixth embodiment shown inFIG.6. In the seventh embodiment shown inFIG.7, a shunt regulator loop is de-coupled from VREGWith the seventh embodiment, feedback is not directly taken from VREG149. The seventh embodiment includes GaN HEMT710, GaN-die resistor711, GaN-die resistor712, GaN HEMT713, current source IBIAS715, shunt regulator720, capacitor740, current source745and bypass capacitor746. The shunt regulator loop comprises an electrical current-carrying path among GaN HEMT710, GaN resistor711and capacitor740. The shunt regulator loop uses a GaN HEMT710to establish the voltage VHI152which is always one VTabove the desired value of VREG149. VHI152is used as a gate voltage of the GaN HEMT713. If load currents of GaN HEMT710and GaN HEMT713are roughly equal, the source voltage (which is VREG149) of GaN HEMT713will be roughly equal to the source voltage of GaN HEMT710. Even with a mismatch in currents within a reasonable degree, VREG149will be very close to the source of GaN HEMT710. Therefore, in effect, the shunt regulator achieves the regulation. The seventh embodiment of a gate bias circuit provides some benefits over the embodiment shown inFIG.6in terms of loop stability, but regulation of VREG149is somewhat degraded.

FIG.8is a simplified schematic of an electronic device802comprising an eighth embodiment of a gate bias circuit804for the GaN driver106with a bootstrap circuit. Here, the generation of VREG149is using the same gate bias circuit as in the embodiment ofFIG.7, but VHI152is generated using the bootstrap circuit830. The bootstrap circuit830comprises a diode840having an anode coupled to the drain terminal192of high-side GaN FET186, and a bootstrap capacitor850having one end coupled to a cathode of the diode840and another end coupled to the gate terminal170of GaN power FET110. When the low-side GaN FET188is on, the bootstrap capacitor850gets charged to (VREG-VD), i.e., one diode-drop below VREG149. When the low-side GaN FET188turns off and the high-side GaN FET186turns on, VHI152reaches to (2VREG-VD) which is sufficiently high voltage to overdrive the high-side GaN FET186. The eighth embodiment includes GaN HEMT710, GaN resistor711, GaN resistor712, GaN HEMT713, current source IBIAS715, shunt regulator720, capacitor740, current source745and capacitor746.

FIG.9is a simplified schematic of an electronic device902comprising a ninth embodiment of a gate bias circuit904for the GaN driver106. The ninth embodiment includes GaN HEMT713, current source IBIAS715, current source745and capacitor746. InFIG.9, instead of a shunt regulator, a Zener diode925is used to produce a regulated voltage. The current IBIASflows through a diode-connected GaN device955that establishes a Zener voltage VZENER963which is a regulated voltage. The diode-connected GaN device955produces VHI152which is one diode-drop (roughly VT) above VZENER963. VREG149is about VTbelow VHI152, and hence is roughly equal to VZENER963. Typically, Zener voltages do not vary much with process, temperature and bias current, and this way, VREG149is regulated. Because VHI152is one VTabove VREG149, the high-side GaN FET186continues to receive enough overdrive voltage.

FIG.10is a simplified schematic of an electronic device1002comprising a tenth embodiment of a gate bias circuit1004for the GaN driver106. InFIG.10, a positive supply voltage is generated using a pulse width modulation (PWM) signal1006. In one embodiment, the PWM signal1006could be the same signal as the input signal to the GaN pre-driver180. In another embodiment, the PWM signal1006and the input signal to the GaN pre-driver180are independent of each other. The PWM signal1006is rectified using rectifier diode1011thereby producing VHI152. One end of diode1012is coupled to rectifier diode1011. At another end of diode1012is VREG. VREG149is regulated to Zener clamp voltage which can be controlled by selecting a correct Zener voltage. The tenth embodiment includes resistor1015, Zener diode1025, capacitor1035and capacitor1045. Advantageously, VHI152tracks VTvariation of process because of the monolithically integrated diode1012. The rectifier diode1011can be internal or external to the single GaN die108.

FIG.11is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.FIG.11shows the simulation waveform of VGATE169, VREG149, VHI152and VFB154for different VTprocess.FIG.11illustrates results of a simulation showing VTsweep from fast process corner (lower VT) to slow corner (higher VT) at +25° C. and 15V of VCC. VHI152rises in order to maintain VREG149at 6V.FIG.11illustrates that VREG149is maintained at a fixed voltage (6V for the GaN process used) but VHI152tracks VTof the process such that the high-side GaN FET186is in the triode region. A goal of the gate bias circuit is for VHI152to go higher as VTgoes higher.

FIG.12is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention. The waveform shows VGATE169, VREG149, VHI152and VFB154.FIG.12illustrates results of a simulation showing a sweep of VCC151from 0V to 20V at +25° C., typical process corner. As VCC151crosses a minimum required voltage to achieve regulation, VREG149gets set at 6V and does not change with further rise in VCC.FIG.12illustrates that VREG149is maintained at 6V when VCC151is between 7.5V and 20V.

FIG.13is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.FIG.13shows the waveform over temperature.FIG.13illustrates results of a simulation showing temperature sweep from −40° C. to +150° C. at VCC15V and process being typical: VHI152rises in order to maintain VREG149at 6V. As simulation shows, at higher temperature the VTincreases, and hence VHI152is increased but VREG149is maintained at 6V.

The embodiments of the gate bias circuit in accordance with the invention advantageously insure that VGATE169is almost constant regardless of VCC151, temperature, threshold voltage or process.

All the devices (except for those devices specially identified) of the circuits in accordance with the invention are realized through only GaN HEMTs and by diodes, resistors or capacitors that can be fabricated in available GaN processes. No P-type metal oxide semiconductor device is used in the circuits in accordance with the invention.

Although most of the description herein focuses on GaN HEMT based technology, the topology of the disclosed circuits and their application are independent of the device technology platform, and can be easily extended to silicon or other present or future semiconductor platforms.

Some features of the present invention may be used in an embodiment thereof without use of other features of the present invention. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples, and exemplary embodiments of the present invention, and not a limitation thereof.

These embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.

The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

The methods as discussed above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package or in a multichip package. In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products (such as, but not limited to, an information processing system) having a display, a keyboard, or other input device, and a central processor.

Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements that such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

The terms “a” or “an”, as used herein, are defined as one as or more than one. The term plurality, as used herein, is defined as two as or more than two. Plural and singular terms are the same unless expressly stated otherwise. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The terms program, software application, and the like as used herein, are defined as a sequence of instructions designed for execution on a computer system. A program, computer program, or software application may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.

Although specific embodiments of the invention have been disclosed, those having ordinary skill in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the invention. The scope of the invention is not to be restricted, therefore, to the specific embodiments, and it is intended that the appended claims cover any and all such applications, modifications, and embodiments within the scope of the present invention.