Patent ID: 12260124

DETAILED DESCRIPTION

The following describes the technical solutions in the embodiments of the present disclosure with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Apparently, the described embodiments are merely some but not all of the embodiments of the present disclosure. Features in various embodiments may be exchanged and/or combined. Other embodiments obtained by a person skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of the present disclosure.

FIG.1schematically shows a cross-sectional view of an exemplary 3D memory device100according to embodiments of the present disclosure. The 3D memory device100may be a discrete memory device working individually. The 3D memory device100may also be a part of a memory system that has multiple memory devices100. In some embodiments, the 3D memory device100may be coupled to or embedded in a host device (not shown). In such cases, the 3D memory device100may be controlled by a controller of the host device. Host devices may include a computing device or electronic device such as a mobile phone, a smart phone, a smart watch, a tablet computer, a laptop computer, a personal computer, a data server, and a workstation, among other host devices.

Optionally, the 3D memory device100may include a memory array device110and a peripheral device120. The memory array device110may include memory cells that form one or more 3D arrays. The peripheral device120may include a circuitry as a controller to control operations of the 3D memory device100. In some embodiments, the memory array device110and the peripheral device120may be fabricated separately and then bonded together to form a stack-like structure, as shown inFIG.1. Alternatively, the memory array device110and the peripheral device120may be integrated into one device. For example, the peripheral device120may be fabricated first and then the memory array device110may be made over the peripheral device120and using the peripheral device120as a substrate. In some other embodiments, the memory array device110and the peripheral device120may be fabricated separated and then mounted side by side on a printed circuit board (PCB).

FIG.2shows a block diagram of a 3D memory device200according to embodiments of the present disclosure. The 3D memory device200may include a memory array210and a circuitry220. The memory array210may include a 3D array of memory cells (not shown). The circuitry220may contain a control circuit222, an input/output (I/O) interface224, a page register226, a row decoder228, and a column decoder230. The row decoder and column decoder may also be referred to as X-decoder and Y-decoder, respectively. Further, the circuitry220may include a Y-path circuit (not shown). The Y-path circuit is connected to the column decoder230(i.e., the Y-decoder) and arranged to allocate a bit line path according to an output transmitted from the column decoder230. The control circuit222may work as a controller that implements various functions of the 3D memory device200. For example, the control circuit222may implement read operations, write operations, and erase operations. The I/O interface224may contain an I/O circuit to receive input of command signals, address signals, and data signals to the 3D memory device200and transmit data signals and status information from the 3D memory device200to an external device (e.g., a host device). The row decoder228may select one or more word lines and the column decoder230may select one or more bit lines of the memory array210. The row decoder228and column decoder230may also receive different voltages from a voltage generator circuit (not shown) and transfer the received voltages to the selected one or more word lines and the selected one or more bit lines. The page register226may include one or more page registers and temporarily store incoming or outgoing data when the data is transferred between the I/O interface224and the memory array210at write or read operations. Optionally, the page register226may contain certain sensing devices or sense amplifiers (not shown) to sense a data state of a memory cell of the memory array210. For example, the data state of a memory cell may be detected by sensing a state of a bit line connected to the memory cell. The term “connected” as used herein indicates electrically connected. The verb “connect” as used herein indicates electrically connecting.

A 3D NAND memory device may logically include one or more NAND targets. A NAND target may contain one or more logical units (LUNs). A LUN may contain one or more planes. A plane may contain one or more blocks. A block may contain multiple pages. A page, containing a number of bytes or words, is the smallest addressable unit for read and write operations. A LUN may be the minimum unit that can execute commands and report status independently. NAND memory cells in a block can be reset together at a block erase operation.

One or more page registers (also referred to as page buffers) may be configured for and connected to each plane. Data transferred to or from a page may be temporarily stored in a page register. For example, a page register may store a portion of data while writing another portion of the data to a page. In some cases, when a write operation, which is also referred to as a program operation, is performed at a NAND target, page registers of planes of all LUNs of the NAND target are cleared or reset. In some other cases, when a write operation is performed at a NAND target, page registers of all planes of selected LUNs of the target are reset. In the above cases, page registers of planes where the page data remains unchanged are reset, which increases the number of registers that go through a reset process. Consequently, the peak power, total power, and power noise may be increased unnecessarily at write operations.

FIG.3shows schematically a top view of a configuration of a 3D array device300according to various embodiments of the present disclosure. The top view is taken over a 3D memory die301of the 3D array device300in an X-Y plane. The 3D memory die301may be divided into planes. Four planes, for example, may form a LUN. One or more LUNs may form a NAND target of the 3D array device300. As an example, the 3D array device300may include one NAND target that contains two LUNs such as LUN 0 and LUN 1. Referring toFIG.3, each LUN may have, for example, plane 0-plane 3, and each plane may be further divided into blocks such as block 0-block 3. In addition, each block may contain pages (not shown) where NAND memory cells are arranged. The numbers of the targets, LUNs, planes, and blocks as depicted above are exemplary and for description purposes. Other numbers of the targets, LUNs, planes, and blocks, larger or smaller than those depicted above, may be used for the disclosed 3D array device300according to various embodiments of the present disclosure.

FIGS.4and5show a schematic top view and a schematic cross-sectional view of a portion400of the 3D array device300at a certain stage in an exemplary fabrication process according to embodiments of the present disclosure. Referring toFIG.3, the portion400may represent a part of the block 2 of the plane 1 of the LUN 1. As shown inFIG.4, the top view is in an X-Y plane and the cross-sectional view is in a Y-Z plane. The cross-sectional view shown inFIG.5is taken along a line AA′ ofFIG.4. As shown inFIG.5, the portion400or the 3D array device300may include a substrate410, a doped region420, and a semiconductor layer430. The substrate410may include a semiconductor material, such as single crystalline silicon. In some embodiments, a top portion of the substrate410may be doped by n-type dopants via ion implantation and/or diffusion to form the doped region420. The semiconductor layer430may be formed over the doped region410and may contain, e.g., n-doped polycrystalline silicon (polysilicon). Over the semiconductor layer430, a layer stack440may be fabricated. The layer stack440may include dielectric layers441and conductor layers442, stacked alternately over each other. The dielectric layer441may contain a dielectric material (e.g., silicon oxide) and the conductor layer442may contain a conductive material (e.g., tungsten (W)). The term “conductive”, as used herein, indicates electrically conductive. The layer stack may include 64 pairs, 128 pairs, or more than 128 pairs of the dielectric layer441and conductor layer442.

Referring toFIGS.4and5, channel holes450are arranged to extend in the Z direction and form an array of a predetermined pattern in an X-Y plane. The channel holes450may have a cylinder shape or pillar shape that extends through the layer stack440, the semiconductor layer430, and partially penetrates the doped region420. The quantity, dimension, and arrangement of the channel holes450shown inFIGS.4and5and in other figures in the present disclosure are exemplary and for description purposes, although any suitable quantity, dimension, and arrangement may be used for the disclosed 3D array device300according to various embodiments of the present disclosure.

Inside a channel hole450, a functional layer451may be deposited. The functional layer451may include a blocking layer452on the sidewall and bottom of the channel hole to block an outflow of charges, a charge trap layer453on a surface of the blocking layer452to store charges during an operation of the 3D array device300, and a tunnel insulation layer454on a surface of the charge trap layer453. In some embodiments, the functional layer451may have an oxide-nitride-oxide (ONO) structure. That is, the blocking layer452may be a silicon oxide layer deposited on the sidewall of the channel hole450, the charge trap layer453may be a silicon nitride layer deposited on the blocking layer452, and the tunnel insulation layer454may be another silicon oxide layer deposited on the charge trap layer453.

Over the tunnel insulation layer454, a channel layer455may be deposited. The channel layer455is also referred to as a “semiconductor channel” and may include polysilicon in some embodiments. Like the channel holes, the channel layer455also extends through the layer stack440and into the doped region420. The semiconductor layer430may be formed on the doped region420and on certain sidewalls or side portions of the channel layers455, and connected to the doped region420and the channel layers455. In some embodiments, the semiconductor layer430may be used as an array common source. The channel hole450may be filled by an oxide material456after the channel layer455is formed. The functional layer451and channel layer455formed in a channel hole450may be considered as a channel structure.

As shown inFIG.5, a portion of each functional layer451in a channel hole450may be between a portion of a conductor layer442and a portion of a channel layer455. Each conductor layer442may connect NAND memory cells in an X-Y plane and be configured as a word line of the 3D array device300. The channel layer455formed in a channel hole450may be configured to connect a string of NAND memory cells along the Z direction. One end of the channel layer455may be connected to a bit line of the 3D array device300. As such, a portion of the functional layer451in a channel hole450in an X-Y plane, as a part of a NAND memory cell, may be arranged between a conductor layer442and a channel layer455, i.e., between a word line and a channel layer connected to a bit line. A NAND memory cell, including a portion of a conductor layer442that is around a portion of a channel hole450, may be considered as a field-effect transistor with a control gate, a source, and a drain. A portion of a conductor layer442that is around a portion of a channel hole450may function as the control gate for the transistor. The 3D array device300may be considered as including a 2D array of strings of NAND memory cells (such a string is also referred to as a “NAND string”). Each NAND string may contain multiple NAND memory cells and extend vertically toward the substrate410. The NAND strings may form a 3D array of the NAND memory cells. A NAND string may correspond to a transistor string that contains multiple field-effect transistors connected in series along a channel layer455in the Z direction. As such, the transistor strings may form a 3D array of the field-effect transistors.

FIGS.6and7show schematic cross-sectional views of the portion400of the 3D array device300at a certain stage in the exemplary fabrication process according to embodiments of the present disclosure. As shown inFIG.6, a dielectric layer457may be deposited over the layer stack440and the channel holes450. Further, vias460and461and conductive layers462may be formed for interconnect in the dielectric layer457. For example, some of the vias460may be connected to the channel layers455. Thereafter, a dielectric material may be deposited to make the dielectric layer457thicker and connecting pads463may be formed over and connected to the vias461. Some connecting pads463may be connected with the channel layers455through the vias461-462and the conductive layers463. A conductive material (e.g., W) may be used to fabricate the vias460-461, conductive layers462, and connecting pads463.

The channel structures and conductor layers442as shown in the cross-sectional view inFIG.6may represent a portion480, which is in the same block as the portion400, i.e., the block 2 of the plane 1 of the LUN 1 of the 3D array device300. The portion480, whose boundary is depicted by dashed lines inFIG.6, may contain multiple NAND strings or transistor strings. The field-effect transistors and electrical circuit of the portion480are illustrated inFIG.7schematically, where a circuit diagram replaces the diagram of the channel structures and the layer stack440. As shown inFIG.7, each NAND memory cell is replaced by a field-effect transistor. The channel layers455are connected to bit lines BL1-BL8(e.g., the vias460), respectively. The field-effect transistor whose drain is connected to a bit line may be configured as a select transistor and referred to as a top select gate (TSG). The field-effect transistor whose source is connected to the array common source may also be configured as a select transistor and referred to as a bottom select gate (BSG). The control gates of the TSGs may be connected to a select line (e.g., a conductor layer442), while the control gates of the BSGs may be connected to another select line (e.g., another conductor layer442). The word lines WL1-WLn may correspond to conductor layers442between the TSGs and BSGs.

NAND memory cells (or field-effect transistors) whose control gates are connected to a conductor layer442(i.e., a word line) may form a page. As such, there may be n pages that are connected to word lines WL1-WLn, respectively. NAND memory cells (or field-effect transistors) connected to a channel layer455that is connected with a bit line may form a NAND string or transistor string. As shown inFIG.7, transistor strings S1-S8are connected to bit line BL1-BL8, respectively. In some embodiments, a page may be considered as a row, and a NAND string may be considered as a column. The address of NAND memory may include a row address and a column address. The row address indicates the page, block, and LUN to be accessed, while the column address indicates the byte or word within a page to access.

FIG.8shows a schematic cross-sectional view of a portion470of a peripheral device according to embodiments of the present disclosure. The peripheral device may include a semiconductor substrate471such as single crystalline silicon. A control circuitry (e.g., the control circuit222with reference toFIG.2) may be fabricated on the substrate471and used for facilitating the operation of a 3D memory device. A dielectric layer472may be deposited over the substrate471and the control circuitry. Connecting pads such as connecting pads473and vias may be formed in the dielectric layer472. The connecting pads473may be configured for connection with the 3D array device300and contain a conductive material such as W.

FIG.9schematically shows a portion490of an exemplary 3D memory device at a certain fabrication stage according to embodiments of the present disclosure. The 3D memory device may include the 3D array device300shown partially inFIG.6and the peripheral device shown partially inFIG.8. The peripheral device is configured to control the array device300or the 3D memory device.

The 3D array device300and the peripheral device may be bonded by a flip-chip bonding method to form the 3D memory device, as shown schematically inFIG.9. For the 3D array device300and the peripheral device, the bottom side of the substrate410or471may be referred to as the back side, and the side with the connecting pads463or473may be referred to as the front side or face side. After the flip-chip bonding process, the connecting pads463are bonded with the connecting pads473, respectively. That is, the 3D array device300and peripheral device are bonded face to face and in electrical communication.

Thereafter, other fabrication steps or processes may be performed to complete fabrication of the 3D memory device. Details of the other fabrication steps or processes are omitted for simplicity.

FIG.10depicts a schematic organization diagram500of the 3D memory device that is partially shown inFIGS.3-9according to various embodiments of the present disclosure. As illustrated above, the 3D memory device may exemplarily have a NAND target (e.g., a NAND target510) that contains LUN 0 and LUN 1. The LUNs may be connected to a controller520that may, for example, have similar functions to that of the control circuit222with reference toFIG.2. Each LUN may exemplarily contain four planes, e.g., plane 0-plane 3. Each plane may contain four blocks, e.g., block 0-block 3. Each block may exemplarily contain a number of pages. Further, as shown inFIG.10, page registers may be connected to the planes of the LUN 0 and LUN 1, respectively. In some embodiments, one page register is connected to one plane. Optionally, more than one page register may be connected to a plane of the LUN 0 and LUN 1 in some cases. When a page register is assigned and connected to a plane, it may be considered that the page register works for the plane, and the plane includes the page register.

In some embodiments, certain write operations may be represented by a page program operation and a write command may be replaced by a page program command. For example, a page program operation may be arranged to program data to a memory array and the memory array may be programmed by page. Optionally, partial page programming may also be implemented. After a page program command is received by the controller520, there may be two scenarios. In the first scenario, after the controller520receives a page program command for the NAND target510, page registers of all LUNs of the NAND target are reset or cleared by the controller520. Referring toFIG.10, page registers of all LUNs of the NAND target510indicate all the page registers of the plane 0-plane 3 of the LUN 0 and LUN 1. Thus, all page registers of the plane 0-plane 3 of the LUN 0 and LUN 1 are reset after the page program command is obtained in the first scenario. In the second scenario, after the controller520receives a page program command for the NAND target510, all page registers of a selected LUN of the NAND target510are cleared. Referring toFIG.10, page registers of a selected LUN of the NAND target510indicate all page registers of the plane 0-plane 3 of either LUN 0 or LUN 1. For example, if the LUN 0 is selected, all page registers of the plane 0-plane 3 of the LUN 0 are reset by the controller520after the page program command is obtained in the second scenario. If the LUN 1 is selected, all page registers of the plane 0-plane 3 of the LUN 1 are reset by the controller after the page program command is obtained in the second scenario.

In many cases, however, not all planes of a LUN need to be re-programmed and some planes may keep the stored data unchanged at a page program operation. Take LUN 0 inFIG.10for example. A page program command may require a page program action (i.e., write actions) for one, two, three, but not four planes. As such, not all page registers of the plane 0-plane 3 need to be reset when less than four planes need a page program action. Resetting all planes of all LUNs (e.g., the first scenario) or all planes of one LUN (e.g., the second scenario) increase the number of page registers that are cleared by the controller520, and thus can increase the peak power, total power, and power noise of the 3D memory device during a page reset process.

FIG.11shows a schematic timing diagram1100for page program operations of the 3D memory device shown inFIG.10according to various embodiments of the present disclosure. The timing diagram1100schematically presents commands and instructions along a timeline. When a single plane is involved,80hmay represent the first cycle of a page program command, while10hmay represent the second cycle of the page program command. When multiple planes are involved,80hmay represent the first cycle of a multi-plane page program command, while11hmay represent the second cycle of the multi-plane page program command. In some embodiments of a multi-plane page program operation, two (or more) pages of different planes may have the same address and may be programmed in parallel (e.g., concurrently or within the same time period). Optionally, two (or more) pages of different planes may also be reset in parallel (e.g., concurrently or within the same time period). The planes at a multi-plane page program operation may be from a same LUN. Alternatively, the planes at a multi-plane page program operation may be from different LUNs.

As shown inFIG.11, after the controller520receives a first page program command, it may check the address, e.g., a 6-byte address and perform the first cycle80h. A plane indicated in the address, e.g., the plane 0, may be determined by the controller520. Then, the controller520may only reset the page register of the plane that is indicated in the address. If the plane indicated in the address has a single page register, only the single page register is reset. If the plane indicated in the address has multiple page registers, only the multiple page registers are reset. As such, the controller520does not reset page registers of other planes of the NAND target510and may keep the page registers of the other planes of the NAND target510unchanged. Further, a data input command may be performed by the controller520to obtain data signals for the page program operation followed by executing the second cycle of the page program command (e.g., command10h). Thereafter, the controller520may receive a second page program command that is a multi-plane page program. The multi-plane page program is about writing to multiple planes, while the multiple planes may be from LUN 0 and/or LUN 1 in various embodiments. The controller520may check the address, e.g., a 6-byte address and perform the first cycle of the multi-plane page program command80h. Planes indicated in the address, e.g., the plane 2, may be determined by the controller520. Then, the controller520may only reset page registers of the planes (e.g., planes 2 from LUN 0 and LUN 1) that are indicated in the address. Thus, the controller520does not reset page registers of other planes of the NAND target510that are not indicated in the address and may keep the page registers of the other planes of the NAND target510unchanged. Further, another data input command is performed to obtain data signals for the multi-plane page program operation and the second cycle of the page program command (e.g., command11h) is executed by the controller520. Hence, only the page register or page registers of the plane or planes that are indicated in a page program command are reset. Compared to clearing all page registers of all LUNs or clearing all page registers of selected LUNs, the peak power and the total power during a page register resetting process may be reduced. In addition, the power noise of the 3D memory device may be improved.

FIG.12shows a schematic flow chart1200for performing a page program operation at a 3D memory device according to embodiments of the present disclosure. Assuming that the 3D memory device has one or more NAND targets and each NAND target contains one or more planes. Each plane contains blocks that have pages of NAND memory cells. Each plane also includes one or more page registers.

At1210, a controller of the 3D memory device receives a page program command for a page program operation at a NAND target and starts checking or examining the page program command. The page program command may be a command set including multiple commands and communication items. At1220, the controller detects and obtains an address from the page program command. The address may be, e.g., a six-byte address that provides a location for the page program operation. The controller checks or examines the address after obtaining it. At1230, the controller identifies or determines a plane that is indicated in the address or according to the address. The indicated plane represents a location where page programming is to be implemented.

At1240, the page register of the plane indicated in the address is cleared in resetting by the controller. If the plane indicated in the address has multiple page registers, the multiple page registers may be reset. If the NAND target has a single LUN, the page register (or page registers) or only the page register (or page registers) of the plane indicated in the address is cleared, while page registers of other planes (or remaining planes) of the single LUN are not cleared and remain unchanged. That is, the controller maintains the status of page registers of other planes of the single LUN (or the NAND target) that are not indicated in the address. If the NAND target has multiple LUNs, the page register (or page registers) or only the page register (or page registers) of the plane indicated in the address is cleared, while page registers of other planes (or remaining planes) of the multiple LUNs (or the NAND target) are not cleared and remain unchanged. That is, the controller maintains the status of page registers of other planes of the NAND target that are not indicated in the address.

If the controller receives a multi-plane page program command for a multi-plane page program operation at1210, it first checks or examines the multi-plane page program command. At1220, the controller detects and obtains an address from the multi-plane page program command. Then, the controller checks or examines the address. At1230, the controller identifies or determines planes that are indicated in the address. The indicated planes represent locations where multi-plane page programming is to be implemented.

At1240, the page registers of the planes indicated in the address are cleared in resetting by the controller. If the NAND target has a single LUN, the page registers or only the page registers of the planes indicated in the address are cleared, while page registers of other planes of the single LUN (or other planes of the NAND target) are not cleared and remain unchanged. That is, the controller maintains the status of page registers of other planes of the NAND target that are not indicated in the address. If the NAND target has multiple LUNs, the page registers or only the page registers of the planes indicated in the address are cleared, while page registers of other planes of the multiple LUNs (or other planes of the NAND target) are not cleared and remain unchanged. That is, the controller maintains the status of page registers of other planes of the NAND target that are not indicated in the address.

FIG.13Aillustrates an exemplary implementation block diagram1300for a memory device consistent with the disclosed embodiments. The memory device may include a controller (not shown), e.g., the control circuit222with respect toFIG.2. As shown inFIG.13A, the implementation may include an input and output control circuitry IO_CTRL1302, a page buffer control circuitry PB_CTRL1304for each plane, and a facility circuitry1306. Other circuitry may also be included.

The IO_CTRL1302may be a single instance, while the PB_CTRL1304may be provided for each plane. The controller may transmit commands to the IO_CTRL1304. The IO_CTRL1302may receive a “80h_setcache” signal from the commands, and may generate control signals or enable signals and transmit the control signals or enable signals to the PB_CTRL1304. The PB_CTRL1304may include a reset circuitry for resetting the page registers based on the control signals from the JO CTRL1302. Further, the facility circuitry1306may provide a facility function between the JO CTRL1302and PB_CTRL1304.

Further, the input and output control circuitry JO CTRL1302may be disposed in a data path of the memory device (e.g., the controller) and the facility circuitry1306may be disposed in a Y-path of the memory device. That is, the facility circuitry1306may be disposed in the Y-path circuit of the memory device, and the JO CTROL1302may be in the data path circuit of the memory device.

Specifically, the facility circuitry1306may receive the address information sent from the controller or an address register (not shown), and may generate control signals or enable signals addr_plane_dp for individual planes and pass the control signals or enable signals addr_plane_dp to the reset circuitry of the PB_CTRL1304. Thus, the control signals or enable signals addr_plane_dp from the facility circuitry1306for individual planes may be combined with the control signal/enable signal from the IO_CTRL1302by the reset circuitry to generate proper control signals/enable signals for all the individual planes. For example, the page register reset in the PB_CTRL1304of a specific plane according to the address information may be enabled by its corresponding addr_plane_dp signal, while the page register reset in the PB_CTRL1304of any other plane is not enabled by the corresponding addr_plane_dp signal. Thus, the page register reset may be performed only on one or more page registers of a selected plane according to the addr_plane_dp signal that is based on the address information.

FIG.13Billustrates the implementation block diagram1300shown inFIG.13Awith an example of a simplified reset circuitry in the PB_CTRL1304. As shown inFIG.13B, the enable signals (e.g., row_en[5:0]) for individual planes may be generated by the PB_CTRL circuitry to enable the individual planes for page register reset. At the same time, the enable signals are combined with the signal addr_plane_dp to generate the final page register reset signal to only enable a specific plane according to the address information. The signal addr_plane_dp may use a bit map to enable/disable the enable signals row_en, or may use a single on/off signal to enable/disable the enable signals row_en.

For example, for a single plane of 16 KB and a configuration with4planes (4×16 KB), after six-byte address of page program command (80h) is received, the controller may only reset the page register of a single plane, which address is indicated by the address. Further, in the case of multi-plane page program, the controller will continue to only reset the page registers indicated by the six-byte address when executing command80hor81h. Thus, the peak power during page register reset of command80hor81hmay be reduced, the total power consumption in the case of less than four plane programming may also be reduced, and/or the power noise that could affect background page register programming may also be reduced.

Further, the controller may send the facility circuitry1306a switch signal c_vsc_pc multi for enabling or disabling the facilitation function of the facility circuitry1306. The switch signal may also be referred as a “trim” bit signal and may control whether the control signals or enable signals for individual planes can be passed onto the PB_CTRL1304of the planes. The trim bit signal may be used by the controller to switch on/off the facility function and/or to keep backward compatibility with other page program standards.

For example, as shown inFIG.13B, when the c_vsc_pc multi is ‘0’, the addr_plane_dp signal is not propagated to the PB_CTRL1304of the planes. In such case, only the control signal from JO CTRL1302is propagated to the PB_CTRL1304of the planes. In the above example of four planes (4×16 KB), all page registers in the four planes (4×16 KB) may be reset even the page program command only applies to a single plane (16 KB). Other reset mechanisms may also be used.

FIG.14shows a timing diagram1400of page register reset of a 3D memory device according to various embodiments of the present disclosure. Assuming that the 3D memory device has a NAND target that contains four LUNs, e.g., LUN 0-LUN 3. Each LUN of the 3D memory device has four planes, e.g., plane 0-plane 3 that are connected to page register 0-page register 3, respectively.

At time t1, a controller of the 3D memory device receives command and address signals. The command received includes a page program command80h. The address signals include, e.g., a 6-byte address. The controller detects that plane 0 of LUN 3 is indicated in the 6-byte address. After determining that plane 0 of LUN 3 is indicated in the address signals, the controller resets page register 0 of LUN 3 (i.e., the hatched page register ofFIG.14before time t2) that corresponds to plane 0 of LUN 3. As such, the controller does not reset the remaining page registers of LUN 0-LUN 3 (i.e., all page registers of the NAND target except page register 0 of LUN 3) and keeps or maintains the status of the remaining page registers unchanged.

At time t2, the controller receives a multi-plane page program command80hand address signals of the command. The controller detects that the address signals contain, e.g., a 6-byte address that indicates plane 2 for LUN 0-LUN 3. After determining that plane 2 and LUN 0-LUN 3 are indicated in the address signals, the controller resets page registers 2 of LUN 0-LUN 3 (i.e., the hatched page registers ofFIG.14after time t2). The four reset page registers correspond to planes 2 of LUN 0-LUN 3, respectively. Hence, the controller does not reset the remaining page registers of LUN 0-LUN 3 (i.e., all page registers of the NAND target except page registers 2 of each LUN) and keeps or maintains the status of the remaining page registers unchanged.

Therefore, page program operations and multi-plane page program operations of a 3D memory device may be implemented with less power consumed according to embodiments of the present disclosure. At a page program operation, only the page register or page registers of the plane or planes of a NAND target that are indicated in a page program command are reset. At a multi-plane page program operation, only the page registers of the planes of a NAND target that are indicated in a multi-plane page program command are reset. At page program operations and multi-plane page program operations, page registers of planes of a NAND target that are not indicated in a command are not cleared unnecessarily and remain unchanged. Thus, compared to clearing all page registers of all LUNs of a NAND target or clearing all page registers of selected LUNs of a NAND target, less peak power and less total power may be consumed during a page register resetting process. Further, the power noise of the 3D memory device may be improved.

Although the principles and implementations of the present disclosure are described by using specific embodiments in the specification, the foregoing descriptions of the embodiments are only intended to help understand the present disclosure. In addition, features of aforementioned different embodiments may be combined to form additional embodiments. A person of ordinary skill in the art may make modifications to the specific implementations and application range according to the idea of the present disclosure. Hence, the content of the specification should not be construed as a limitation to the present disclosure.