Patent ID: 12252783

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In a chemical vapor deposition (CVD) operation, a material (or a precursor of the material) that is to be deposited onto a semiconductor substrate is carried into a processing chamber by a carrier gas. The combination of the material and the carrier gas is referred to as a processing vapor. The concentration or flow rate of the material in the processing vapor directly affects the growth rate (or deposition rate) of the material onto the semiconductor substrate. In some cases, a tungsten precursor such as tungsten fluoride (e.g., a WFxsuch as tungsten hexafluoride (WF6)) may be deposited too quickly (e.g., as a result of a high flow rate or a high concentration in the processing vapor) onto a semiconductor substrate, which can result in poor uniformity of the resulting tungsten layer on the semiconductor substrate. As an example, a high flow of tungsten hexafluoride (which may include, for example, a processing vapor having a ratio of tungsten hexafluoride concentration to a carrier gas of approximately 50:7200 or greater) may result in a root means squared (RMS) surface roughness of approximately 1.6 to approximately 1.9 or greater. This can result in the formation of defects such as voids, discontinuities, pattern loading, and/or island formation in the tungsten layer. These defects may reduce device yield on the semiconductor substrate, may reduce device quality, may increase pattern leakage, and/or may increase the rate of semiconductor substrate scrapping, among other examples.

Some implementations described herein provide low-flow tungsten CVD techniques for uniform deposition of tungsten on a semiconductor substrate. In some implementations described herein, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques described herein may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD) and providing increased deposition selectivity relative to ALD. This reduces the likelihood of defect formation in the tungsten layer, increases deposition process flexibility, and/or increases the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates), among other examples.

FIGS.1A and1Bare diagrams of an example environment100in which systems and/or methods described herein may be implemented. As shown inFIG.1A, environment100may include a plurality of semiconductor processing tools102-110and a wafer/die transport tool112. The plurality of semiconductor processing tools102-110may include a deposition tool102, an exposure tool104, a developer tool106, an etch tool108, a planarization tool110, and/or another type of semiconductor processing tool. The tools included in example environment100may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and/or manufacturing facility, among other examples.

The deposition tool102is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool102includes a spin coating tool that is capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool102includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool102includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the example environment100includes a plurality of types of deposition tools102.

The exposure tool104is a semiconductor processing tool that is capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light (EUV) source, and/or the like), an x-ray source, an electron beam (e-beam) source, and/or the like. The exposure tool104may expose a photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include a pattern for forming one or more structures of a semiconductor device, may include a pattern for etching various portions of a semiconductor device, and/or the like. In some implementations, the exposure tool104includes a scanner, a stepper, or a similar type of exposure tool.

The developer tool106is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool104. In some implementations, the developer tool106develops a pattern by removing unexposed portions of a photoresist layer. In some implementations, the developer tool106develops a pattern by removing exposed portions of a photoresist layer. In some implementations, the developer tool106develops a pattern by dissolving exposed or unexposed portions of a photoresist layer through the use of a chemical developer.

The etch tool108is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool108may include a wet etch tool, a dry etch tool, and/or the like. In some implementations, the etch tool108includes a chamber that is filled with an etchant, and the substrate is placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. In some implementations, the etch tool108may etch one or more portions of the substrate using a plasma etch or a plasma-assisted etch, which may involve using an ionized gas to isotropically or directionally etch the one or more portions.

The planarization tool110is a semiconductor processing tool that is capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, a planarization tool110may include a chemical mechanical planarization (CMP) tool and/or another type of planarization tool that polishes or planarizes a layer or surface of deposited or plated material. The planarization tool110may polish or planarize a surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization tool110may utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring (e.g., typically of a greater diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate with different axes of rotation to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

Wafer/die transport tool112includes a mobile robot, a robot arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and/or another type of device that is used to transport wafers and/or dies between semiconductor processing tools102-110and/or to and from other locations such as a wafer rack, a storage room, and/or the like. In some implementations, wafer/die transport tool112may be a programmed device that is configured to travel a particular path and/or may operate semi-autonomously or autonomously.

FIG.1Billustrates an example CVD tool120, which is an example of a deposition tool102included in the environment100. The CVD tool120is configured to perform a low-flow CVD operation described herein to deposit a layer (e.g., a tungsten layer or another type of layer) on a semiconductor substrate. As shown inFIG.1B, the CVD tool120includes a processing chamber122(e.g., a CVD processing chamber) and a vapor supply system124(e.g., a CVD vapor supply system). The vapor supply system124is configured to provide a flow of a processing vapor126into the processing chamber122. The vapor supply system124includes a vapor generator128, which may include a plurality of devices and/or systems that are configured to generate a vapor from a source material (e.g., a solid or liquid source material) and mix the source material with a carrier gas to generate the processing vapor126. The flow of the processing vapor126is provided through a supply line130to a showerhead132included in the processing chamber122. The flow of the processing vapor126flows through the showerhead132and into the processing chamber122. In some implementations, the vapor supply system124includes a plasma source134that is connected to an electrical ground136. The plasma source134is configured to generate and provide a plasma to the processing chamber122to facilitate a plasma enhanced CVD operation to be performed in the processing chamber122.

The processing chamber122further includes a vent138(or port) through which the processing chamber122may be purged of oxygen, the processing vapor126, and/or one or more other gasses in the processing chamber122. A vacuum pump140is included to pump and/or otherwise remove the oxygen, the processing vapor126, and/or the one or more other gasses from the processing chamber122through the vent138.

In some implementations, the CVD tool120includes a heater142that is configured to heat a semiconductor substrate144on a chuck146. The semiconductor substrate144includes a semiconductor wafer or another type of semiconductor device on which one or more layers are to be formed in a CVD operation. The chuck146includes a vacuum chuck, an electrostatic chuck, or another type of chuck that is configured to secure the semiconductor substrate144in place during the CVD operation.

The number and arrangement of devices shown inFIGS.1A and1Bare provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or differently arranged devices than those shown inFIGS.1A and1B. Furthermore, two or more devices shown inFIGS.1A and1Bmay be implemented within a single device, or a single device shown inFIGS.1A and1Bmay be implemented as multiple, distributed devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of environment100may perform one or more functions described as being performed by another set of devices of environment100.

FIG.2is a diagram of a portion of the semiconductor substrate144described herein. The portion of the semiconductor substrate144includes an example of a memory device (e.g., a static random access memory (SRAM), a dynamic random access memory (DRAM)), a logic device, a processor, an input/output device, or another type of semiconductor device that includes one or more transistors.

As shown inFIG.2, the semiconductor substrate144includes a device substrate202, which includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a silicon germanium (SiGe) substrate, or another type of semiconductor substrate. In some implementations, a fin structure204is formed in the device substrate202. In some implementations, a plurality of fin structures204are included in the device substrate202. In this way, the transistors included on the semiconductor substrate144include fin field-effect transistors (finFETs). In some implementations, the semiconductor substrate144includes other types of transistors, such as gate all around (GAA) transistors (e.g., nanosheet transistors, nanowire transistors), planar transistors, and/or other types of transistors. The fin structures204may be electrically isolated by intervening shallow trench isolation (STI) structures (not shown). The STI structures may be etched back such that the height of the STI structures is less than the height of the fin structures204. In this way, the gate structures of the transistors may be formed around at least three sides of the fin structures204.

As shown inFIG.2, a plurality of layers are included on the device substrate202and/or on the fin structures204, including a dielectric layer206, an etch stop layer (ESL)208, and a dielectric layer210, among other examples. The dielectric layers206and210are included to electrically isolate various structures of the semiconductor substrate144. The dielectric layers206and210include interlayer dielectric layers (ILDs). For example, the dielectric layer206may include an ILD0 layer, and the dielectric layer210may include an ILD1 layer or an ILD2 layer. The dielectric layers206and210include a silicon nitride (SiNx), an oxide (e.g., a silicon oxide (SiOx) and/or another oxide material), and/or another type of dielectric material. The ESL208includes a layer of material that is configured to permit various portions of the semiconductor substrate144(or the layers included therein) to be selectively etched or protected from etching to form one or more of the structures included on the device substrate202.

As further shown inFIG.2, a plurality of gate stacks may be included over, on, and/or around a portion of the fin structure204. The gate stacks include a metal gate (MG) structure212between sidewall spacers214, a metal capping layer216over and/or on the metal gate structure212, and a dielectric capping layer218over and/or on the metal capping layer216. The metal gate structures212include a conductive metallic material (or metal alloy) such as cobalt (Co), tungsten (W), ruthenium (Ru), copper (Cu), another metallic material, and/or a combination thereof. The sidewall spacers214are included to electrically isolate the gate stacks from adjacent conductive structures included on the semiconductor substrate144. The sidewall spacers214include a silicon oxide (SiOx), a silicon nitride (SiXNy), a silicon oxy carbide (SiOC), a silicon oxycarbonitride (SiOCN), and/or another suitable material.

The metal capping layer216is included to protect the metal gate structure212from oxidization and/or etch damage during processing of the semiconductor substrate144, which preserves the low contact resistance of the metal gate structure212. The metal capping layer216includes a conductive metallic material (or metal alloy) such as cobalt (Co), tungsten (W), ruthenium (Ru), copper (Cu), another metallic material, and/or a combination thereof. The dielectric capping layer218includes a dielectric material such as a silicon nitride (SiNx), an oxide (e.g., a silicon oxide (SiOx) and/or another oxide material), and/or another type of dielectric material. The dielectric capping layer218may be referred to as a sacrificial (SAC) layer that protects the gate stacks from processing damage during processing of the semiconductor substrate144.

As further shown inFIG.2, a plurality of source/drain regions220are included on and/or around portions of the fin structure204. The source/drain regions220include p-doped and/or n-doped epitaxial (epi) regions that are grown and/or otherwise formed by epitaxial growth. In some implementations, the source/drain regions220are formed over etched portions of the fin structure204. The etched portions may be formed by strained source drain (SSD) etching of the fin structure204and/or another type etching operation.

Metal source/drain contacts (MDs)222are included over and/or on the source/drain regions220. In some implementations, a metal silicide layer (not shown) is included between the source/drain regions220and the metal source/drain contacts222. The metal silicide layer may be included to decrease contact resistance between the source/drain regions220and the metal source/drain contacts222and/or to decrease the Schottky barrier height (SBH) between the source/drain regions220and the metal source/drain contacts222. The metal source/drain contacts222include conductive metallic material (or metal alloy) such as cobalt (Co), tungsten (W), ruthenium (Ru), copper (Cu), another metallic material, and/or a combination thereof.

In some implementations, a contact etch stoper layer (CESL)224is included between the sidewalls spacers of the gate stacks and the metal source/drain contacts222. The CESL224may be included to provide etch selectivity or etch proception for the sidewall spacers214during an etch operation to form openings in which the metal source/drain contacts222are formed.

As further shown inFIG.2, the metal gate structures212(e.g., either directly or via the metal capping layer216) and the metal source/drain contacts222are electrically connected to interconnect structures. For example, a metal gate structure212may be electrically connected to a gate interconnect structure226a(e.g., a gate via or VG). The metal gate structure212may be electrically connected to the gate interconnect structure226adirectly, via the intervening metal capping layer216, and/or by a metal gate contact (MP). As another example, a metal source/drain contact222may be electrically connected to a source/drain interconnect structure226b(e.g., a source/drain via or VD). The interconnect structures (e.g., the gate interconnect structure226a, the source/drain interconnect structure226b, among other examples) electrically connect the transistors on the semiconductor substrate144and/or electrically connect the transistors to other areas and/or components of the semiconductor substrate144. In some implementations, the interconnect structures electrically connect the transistors to a back end of line (BEOL) region of the semiconductor substrate144. The gate interconnect structure226aand the source/drain interconnect structure226binclude a conductive material such as tungsten, cobalt, ruthenium, copper, and/or another type of conductive material.

As indicated above,FIG.2is provided as an example. Other examples may differ from what is described with regard toFIG.2.

FIGS.3A-3Fare diagrams of an example implementation300described herein. The example implementation300includes an example of forming one or more layers and/or structures on the semiconductor substrate144. In particular, the example implementation300includes an example dummy gate replacement process in which dummy gate structures302on the semiconductor substrate144are removed and replaced with the gate stacks (e.g., metal gate stacks) illustrated and described herein in connection withFIG.2.

As shown inFIG.3A, dummy gate structures302are included between source/drain regions220and between areas of the dielectric layer206. Moreover, the dummy gate structures302are formed and included over the fin structure204, and around the sides of the fin structure204such that the dummy gate structures302surround the fin structure204on three sides of the fin structure204. The dummy gate structures302are formed as a placeholder for the actual gate structures (e.g., replacement high-k gate or metal gate) that are to be formed for the transistors included on the semiconductor substrate144.

The dummy gate structures302include a gate dielectric layer304, a gate electrode layer306, and a hard mask layer308. The gate dielectric layer304may include a dielectric oxide layer. As an example, the gate dielectric layer304may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or another suitable method. The gate electrode layer306may include a polysilicon layer or another suitable layer. For example, the gate electrode layer306may be formed by a suitable deposition process such as a low-pressure chemical vapor deposition (LPCVD) and PECVD. The hard mask layer308may include any material suitable to pattern the gate electrode layer306with a desired feature/dimension on the semiconductor substrate144. Example materials for the hard mask layer308include silicon nitride, silicon oxynitride, silicon carbon nitride, the like, or a combination thereof, deposited by CVD, PVD, ALD, or another deposition technique.

As further shown inFIG.3A, seal spacers310are included on the sidewalls of the dummy gate structures302. The seal spacers310may be conformally deposited (e.g., by the deposition tool102) and may include a silicon oxycarbide (SiOC), a nitrogen free SiOC, or another suitable material. The seal spacers310may be formed by an ALD operation in which various types of precursor gasses including silicon (Si) and carbon (C) are sequentially supplied in a plurality of alternating cycles to form the seal spacers310.

The cycles of the ALD operation include alternating flows (or pulses) and purge operations, where each precursor is flowed (or pulsed) and subsequently purged at least once during a cycle. For example, silicon and carbon source precursor is flowed in an ALD tool chamber into which the semiconductor substrate144is transferred, and subsequently, the silicon and carbon source precursor is purged from the ALD tool chamber. In some examples, the silicon and carbon source precursor may react with reaction sites available on the semiconductor substrate144before being purged. The reactions may saturate the reaction sites, or the silicon and carbon source precursor may not react with some reaction sites available on the semiconductor substrate144, in some examples. After the silicon and carbon source precursor is purged, an oxygen source precursor is then flowed in the ALD tool chamber, and subsequently, the oxygen source precursor is purged from the ALD tool chamber. Similarly, in some examples, the oxygen source precursor may react with reaction sites available on the semiconductor substrate144before being purged. The reactions may saturate the reaction sites, or the oxygen source precursor may not react with some reaction sites available on the semiconductor substrate144, in some examples. The cycles of the pulses and the purges between the alternating silicon and carbon source precursor and the oxygen source precursor may be performed any number of times until a desired thickness of the seal spacers310is achieved.

In some implementations, the seal spacers310are treated using a plasma. The plasma surface treatment process may efficiently incorporate certain elements to react with the unsaturated bonds in the seal spacers310so as to improve the bonding energy and densify the film structure to treat the seal spacers310with relatively high film density. The higher film density resulting from treatment of the seal spacers310may prevent the interface and the film stack subsequently formed thereon from plasma damage during the dummy gate removal process. Furthermore, the treatment process may also be performed to modify the morphology and/or surface roughness of the surface of the seal spacers310to improve the adhesion and robustness.

As further shown inFIG.3A, the sidewalls spacers214(which may be referred to as bulk spacer layers) may be formed on the seal spacers310. The sidewall spacers214may be formed of similar materials as the seal spacers310. However, the sidewall spacers214may be formed without the plasma surface treatment that is used for the seal spacers310. Moreover, the sidewall spacers214may be formed to a greater thickness relative to the thickness of the seal spacers310.

The seal spacers310and the sidewall spacers214may be conformally deposited on the dummy gate structures302, respectively, and on the fin structure204. The seal spacers310and the sidewall spacers214are then patterned and etched to remove the seal spacers310and the sidewall spacers214from the tops of the dummy gate structures302, and from the fin structures204. The CESL224may be conformally deposited over the fin structure204, over source/drain regions220, over the dummy gate structures302, and on the sidewalls of the sidewall spacers214. The dielectric layer206is formed over and/or on the CESL224. The dielectric layer206fills in the areas between the dummy gate structures302over the source/drain regions220. The dielectric layer206and the CESL224may then be planarized (e.g., by the planarization tool110) to remove the dielectric layer206and the CESL224from the tops of the dummy gate structures302.

As shown inFIG.3B, the dummy gate structures302are removed from the semiconductor substrate144as part of the dummy gate replacement process. The removal of the dummy gate structures302leaves behind openings312between the sidewalls spacers214where the dummy gate structures302were removed. In some implementations, a pattern in a photoresist layer may be used to etch the dummy gate structures302to remove the dummy gate structures302. In these implementations, a spin-coating tool (e.g., a type of deposition tool102) forms the photoresist layer on the dummy gate structures302and on the dielectric layer206. The exposure tool104exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool106develops and removes portions of the photoresist layer to expose the pattern. The etch tool108etches the dummy gate structures302based on the pattern to remove the dummy gate structures302. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for removing the dummy gate structures302based on a pattern. In some implementations, the etch operation to remove the dummy gate structures302may result in a portion of the sidewall spacers214being etched or removed, as shown in the example inFIG.3B.

As shown inFIG.3C, the metal gate structures212are formed in the openings312between the sidewall spacers214and over and/or on the fin structure204. The metal gate structures212may be formed by a CVD operation, an ALD operation, an electroplating operation, and/or another deposition technique. In some implementations, the metal gate structures212are formed to thickness that occupies a portion of the height of the openings312. In some implementations, the metal gate structures212are formed to the full height of the openings312and then etched back (e.g., by the etch tool108) to a thickness that occupies a portion of the height of the openings312. In some implementations, the metal gate structures212are planarized (e.g., by the planarization tool110) prior to the etch back operation.

As shown inFIG.3D, the semiconductor substrate144is positioned in the processing chamber122(e.g., the CVD processing chamber) of the CVD tool120such that a CVD operation may be performed to form the metal capping layer216over and/or on the metal gate structures212. The semiconductor substrate144may be positioned on the chuck146and secured to the chuck146(e.g., by a vacuum, an electrostatic force, or another clamping force). The vapor supply system124(e.g., the CVD vapor supply system) generates a flow of a processing vapor126and provides the flow of the processing vapor126into the processing chamber122through the showerhead132. The metal capping layer216may be formed to include a tungsten layer. Accordingly, the flow of the processing vapor126includes a tungsten precursor such as tungsten hexafluoride (WF6) or another tungsten fluoride (WFx) and a carrier gas that carriers the tungsten hexafluoride into the processing chamber122through the showerhead132.

In some implementations, the carrier gas may include argon (Ar), nitrogen (N2), and/or another inert gas. In some implementations, the carrier gas includes a reactant gas such as hydrogen (H2). Alternatively, the tungsten hexafluoride may be carried into the processing chamber122by an inert carrier gas, and a separate reactant gas of hydrogen (or another reactant gas) may be provided into the processing chamber122. The hydrogen in the carrier gas (or the reactant gas) reacts with the tungsten hexafluoride to form the tungsten layer (the metal capping layer216). As an example, a reaction between the tungsten hexafluoride and the hydrogen during the CVD operation includes:
WF6+3H2→W+6HF
and results in the fluorine in the tungsten hexafluoride bonding with the hydrogen to form a hydrofluoric acid (HF) as a by-product, and the tungsten being deposited onto the metal gate structures212. The vacuum pump140pumps and/or otherwise removes the hydrofluoric acid from the processing chamber122through the vent138.

The CVD operation may include a selective deposition operation in which the tungsten is deposited onto the underlying metal layer (e.g., the metal gate structures212) and resists deposition onto the dielectric sidewalls of the sidewall spacers214. In this way, the metal capping layer216is deposited in a bottom-up deposition technique in which the thickness of the tungsten layer of the metal capping layer216grows or increases as a result of deposition onto the metal gate structures212and not because of growth on the sidewall spacers214(which might otherwise occur in an ALD operation).

In some implementations, the metal capping layer216is formed to a width that is in a range of approximately 20 nanometers to approximately 300 nanometers. In some implementations, the metal capping layer216is formed to a width that is in a range of approximately 500 nanometers to approximately 1500 nanometers. In some implementations, the metal capping layer216is formed to a width that is in a range of approximately 10 nanometers to approximately 40 nanometers. In some implementations, the metal capping layer216is formed to another width. In some implementations, the metal capping layer216is formed to a height or thickness that is in a range of approximately 3 nanometers to approximately 20 nanometers to achieve continuity of the metal capping layer216and to minimize the likelihood of void formation in the metal capping layer216. In some implementations, the metal capping layer216is formed to another height or thickness.

In some implementations, a ratio between a first width (e.g., an x-axis width) and a second width (e.g., a y-axis width) of the metal capping layer216is in a range of approximately 1:30 to approximately 2:1. In some implementations, a ratio between a first width (e.g., an x-axis width) and a second width (e.g., a y-axis width) of the metal capping layer216is in a range of approximately 1:150 to approximately 2:25. In some implementations, a ratio between a width (e.g., an x-axis width) and a height thickness (e.g., a z-axis dimension) of the metal capping layer216is in a range of approximately 40:3 to approximately 1:2. In some implementations, a ratio between a width (e.g., a y-axis width) and a height thickness (e.g., a z-axis dimension) of the metal capping layer216is in a range of approximately 100:1 to approximately 10:1. In some implementations, a ratio between a width (e.g., a y-axis width) and a height thickness (e.g., a z-axis dimension) of the metal capping layer216is in a range of approximately 500:1 to approximately 25:1.

The CVD operation to deposit the metal capping layer216includes performing a low-flow CVD operation to promote substantially uniform growth of the metal capping layer216(e.g., the tungsten layer). The low-flow CVD operation includes providing the flow of the processing vapor126such that the flow rate or concentration of the tungsten hexafluoride in the flow of the processing vapor126results in increased uniformity control over the growth of the metal capping layer216relative to a higher flow rate or concentration. In some implementations, the flow rate of the tungsten hexafluoride in the flow of the processing vapor126is in a range of approximately 1 standard cubic centimeter per minute (SCCM) to approximately 10 SCCM to achieve a surface uniformity performance for the CVD operation that is approximately equal to a surface uniformity performance for an ALD operation (e.g., an alternative ALD operation to form the metal capping layer216). However, other values for the flow rate are within the scope of the present disclosure.

Moreover, the concentration of the tungsten hexafluoride in the flow of the processing vapor126may be less for the low-flow CVD operation relative to a concentration of the tungsten hexafluoride in a “high-flow” CVD operation. The lesser concentration of the tungsten hexafluoride in the flow of the processing vapor126may be less for the low-flow CVD operation results in the tungsten layer being grown at a slower rate in the low-flow CVD operation than a higher flow rate of the tungsten hexafluoride in the high-flow CVD operation to promote substantially uniform growth of the metal capping layer216(e.g., the tungsten layer). In some implementations, the ratio of the tungsten hexafluoride to the carrier gas (the ratio of the flow rate of the tungsten hexafluoride to the flow rate of the carrier gas) in the flow of the processing vapor126for the low-flow CVD operation is in a range of approximately 1:7200 to approximately 10:5400 to achieve high surface uniformity for the metal capping layer216, whereas the ratio of the tungsten hexafluoride to the carrier gas for the high-flow CVD operation may be 50:7200 or greater. However, other values for the ratio of tungsten hexafluoride to the carrier gas for the low-flow CVD operation described herein are within the scope of the present disclosure. As a result of the lesser concentration of the tungsten hexafluoride in the flow of the processing vapor126, the time duration for the low-flow CVD operation (e.g., to achieve the appropriate thickness for the metal capping layer216) is greater relative to the time duration for the high-flow CVD operation. As an example, the time duration for the low-flow CVD operation may be in a range of approximately 40 seconds to approximately 100 seconds to achieve the approximate thickness for the metal capping layer216, whereas the time duration for the high-flow CVD operation may be in a range of approximately 20 seconds to approximately 50 seconds to achieve a similar thickness.

In this way, the concentration in the tungsten hexafluoride is configured to reduce island formation and pattern loading (the variation in growth rate of the metal capping layer216across a plurality of semiconductor substrates) in the metal capping layer216. Moreover, the concentration in the tungsten hexafluoride is configured to reduce the grain size of the metal capping layer216relative to the high-flow CVD operation. As an example, the concentration in the tungsten hexafluoride that is configured to reduce the grain size of the metal capping layer216for the low-flow CVD operation may be configured to achieve a grain size of approximately 130 nanometers or lower, whereas the grain size achievable with the high-flow CVD operation may be 170 nanometers grain size or greater. However, other values for the grain size of the metal capping layer216are within the scope of the present disclosure. In addition, the concentration of the tungsten hexafluoride for the low-flow CVD operation may be configured to achieve a lower fluorine concentration in the metal capping layer216(and the underlying metal layer, such as the metal gate structure212) relative to the high-flow CVD operation. For example, the fluorine concentration in the metal capping layer216resulting from the lower concentration of the tungsten hexafluoride for the low-flow CVD operation may be in a range of approximately 100 arbitrary units (a.u.) to approximately 10000 arbitrary units, whereas the high-flow CVD operation may achieve a fluorine concentration of approximately 50000 arbitrary units or more. However, other values for the fluorine concentration in the metal capping layer216are within the scope of the present disclosure. In this way, the lower fluorine concentration in the metal capping layer216reduces damage to the metal gate structure212caused by the fluorine in the tungsten hexafluoride and/or reduces the impact of the fluorine in the tungsten hexafluoride on the resistivity between the metal capping layer216and the metal gate structure212.

Moreover, the flow rate (or concentration) of tungsten hexafluoride for the low-flow CVD operation described herein enables the low-flow CVD operation to achieve similar surface uniformity performance as ALD while providing a relatively faster deposition operation than ALD. For example, the low-flow CVD operation may be achieve a surface roughness for the metal capping layer216that is in a range of approximately 0.9 RMS roughness to approximately 1.2 RMS roughness, which is comparable to ALD and less than the high-flow rate CVD operation described above (which may achieve a surface roughness that is in a range of approximately 1.6 RMS roughness to approximately 1.9 RMS roughness, for example). As another example, the low-flow CVD operation may achieve a deposition rate of approximately 3 angstroms per second, and may form the metal capping layer216in a single deposition cycle, whereas an alternative ALD operation may involve a plurality of cycles (e.g., 10 or more cycles) to form the metal capping layer216in which the deposition rate is approximately 1 angstrom per second. Moreover, the use of a CVD technique in the low-flow CVD operation provides greater deposition selectivity between metals and dielectrics relative to the alternative ALD operation, which may reduce the likelihood of void formation in the metal capping layer216and enables the use of the low-flow CVD operation for selective deposition processes.

FIG.3Eillustrates the deposited metal capping layers216on the metal gate structures212in the openings312, as formed by the low-flow CVD operation described above.

As shown inFIG.3F, the dielectric capping layers218are formed over and/or on the metal capping layers216. The dielectric capping layers218may be formed by a deposition operation (e.g., performed by a deposition tool102) such as CVD, PVD, ALD, and/or another deposition operation.

As indicated above,FIGS.3A-3Fare provided as an example. Other examples may differ from what is described with regard toFIGS.3A-3F. In some implementations, the operations and/or techniques described in connection withFIGS.3A-3Fmay be used to form a metal capping layer on a metal source/drain contact222.

FIGS.4A-4Eare diagrams of an example implementation400described herein. The example implementation400includes an example of forming one or more layers and/or structures on the semiconductor substrate144. In particular, the example implementation400includes a process in which metal source/drain contacts222are formed over and/or on the source/drain regions220of the semiconductor substrate144. TurningFIG.4A, one or more operations described in connection withFIGS.3A-3Fmay be performed to form the metal gate structures212, the metal capping layers216, the dielectric capping layers218, the dielectric layer206, and/or the CESL224.

As shown inFIG.4B, openings402are formed in the dielectric layer206between metal gate structures212. In some implementations, a pattern in a photoresist layer is used to etch the dielectric layer206to form the openings402. In these implementations, the deposition tool102forms the photoresist layer on the dielectric layer206, on portions of the CESL224, and on the dielectric capping layers218. The exposure tool104exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool106develops and removes portions of the photoresist layer to expose the pattern. The etch tool108etches the dielectric layer206based on the pattern to form the openings402in the dielectric layer206to the source/drain regions220. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for etching the dielectric layer206based on a pattern.

As shown inFIG.4C, metal silicide layers404are formed over and/or on the source/drain regions220in the openings402. The metal silicide layers404may be included to prevent oxide formation on the source/drain regions220and to reduce the contact resistance between the source/drain regions220and metal source/drain contacts that are to be formed over the source/drain regions220. The metal silicide layers404may include a titanium silicide (TiSix), a ruthenium silicide (RuSix), and/or another metal silicide. In some implementations, the deposition tool102deposits a metal layer (e.g., a titanium (Ti) layer, a ruthenium (Ru) layer, or another metal layer) on the source/drain regions220(e.g., by an ALD operation, a CVD operation, a PVD operation, or another type of deposition operation). An anneal operation is performed on the semiconductor substrate144. The anneal operation causes the metal layer to react with silicon in the source/drain regions220, thereby forming the metal silicide layers404.

As shown inFIG.4D, the semiconductor substrate144is positioned in the processing chamber122(e.g., the CVD processing chamber) of the CVD tool120such that a CVD operation may be performed to form the metal source/drain contacts222over and/or on the source/drain regions220. The CVD operation includes providing a flow of the processing vapor126into the processing chamber122to form the metal source/drain contacts222on the semiconductor substrate144. In some implementations, the metal source/drain contacts222are formed to a width that is in a range of approximately 20 nanometers to approximately 300 nanometers. In some implementations, the metal source/drain contacts222are formed to a width that is in a range of approximately 500 nanometers to approximately 1500 nanometers. In some implementations, the metal source/drain contacts222is formed to a width that is in a range of approximately 10 nanometers to approximately 40 nanometers. In some implementations, the metal source/drain contacts222are formed to another width. In some implementations, the metal source/drain contacts222are formed to a height or thickness that is in a range of approximately 30 nanometers to approximately 150 nanometers such that the top surfaces of the metal source/drain contacts222are approximately level with the top surfaces of the dielectric capping layers218. In some implementations, the metal source/drain contacts222are formed to another height or thickness.

In some implementations, a ratio between a first width (e.g., an x-axis width) and a second width (e.g., a y-axis width) of the metal source/drain contacts222is in a range of approximately 1:30 to approximately 2:1. In some implementations, a ratio between a first width (e.g., an x-axis width) and a second width (e.g., a y-axis width) of the metal source/drain contacts222is in a range of approximately 1:150 to approximately 2:25. In some implementations, a ratio between a width (e.g., an x-axis width) and a height thickness (e.g., a z-axis dimension) of the metal source/drain contacts222is in a range of approximately 4:3 to approximately 1:15. In some implementations, a ratio between a width (e.g., a y-axis width) and a height thickness (e.g., a z-axis dimension) of the metal source/drain contacts222is in a range of approximately 10:1 to approximately 2:15. In some implementations, a ratio between a width (e.g., a y-axis width) and a height thickness (e.g., a z-axis dimension) of the metal source/drain contacts222is in a range of approximately 150:3 to approximately 50:15.

The CVD operation to deposit the metal source/drain contacts222includes performing a low-flow CVD operation to promote substantially uniform growth of the metal source/drain contacts222(the tungsten layers). The low-flow CVD operation may be performed using the concentration and/or flow rate of fluorine hexafluoride as described above for the low-flow CVD operation inFIG.3D. Accordingly, the low-flow CVD operation may achieve similar properties and/or attributes for the metal source/drain contacts222as described above for the metal capping layer216. Moreover, as a result of the lesser concentration of the tungsten hexafluoride in the flow of the processing vapor126, the time duration for the low-flow CVD operation (e.g., to achieve the appropriate thickness for the metal source/drain contacts222) is greater relative to the time duration for the high-flow CVD operation described above. As an example, the time duration for the low-flow CVD operation may be in a range of approximately 150 seconds to approximately 500 seconds to achieve the approximate thickness for the metal source/drain contacts222, whereas the time duration for the high-flow CVD operation may be in a range of approximately 75 seconds to approximately 250 seconds to achieve a similar thickness.

FIG.4Eillustrates the deposited metal source/drain contacts222on the source/drain regions220, as formed by the low-flow CVD operation described above.

As indicated above,FIGS.4A-4Eare provided as an example. Other examples may differ from what is described with regard toFIGS.4A-4E.

FIGS.5A-5Eare diagrams of examples implementation500described herein. The example implementation500includes an example of forming one or more layers and/or structures on the semiconductor substrate144. In particular, the example implementation500includes a process in which a gate interconnect structure226ais formed over a metal gate structure212, and in which a source/drain interconnect structure226bis formed over and/or on a metal source/drain contact222. TurningFIG.5A, one or more operations described in connection withFIGS.3A-3Fand/orFIGS.4A-4Emay be performed to form the metal gate structures212, the metal capping layers216, the dielectric capping layers218, the dielectric layer206, the CESL224, and/or the metal source/drain contacts222.

As shown inFIG.5B, the ESL208is formed on the semiconductor substrate144, and the dielectric layer210is formed over and/or on the ESL208. In some implementations, a deposition tool102deposits the ESL208and the dielectric layer210by a CVD, ALD, PVD, and/or another deposition technique.

As shown inFIG.5C, openings502aand502bare formed in the dielectric layer210and in the ESL208. In particular, the opening502ais formed in the dielectric layer210, in the ESL208, in a dielectric capping layer218, and to a metal capping layer216over and/or on a metal gate structure212. The opening502bis formed in the dielectric layer210and in the ESL208to a metal source/drain contact222. In some implementations, the opening502ais formed directly to the metal gate structure212.

In some implementations, a pattern in a photoresist layer is used to etch the dielectric layer206to form the openings502aand502b. In these implementations, the deposition tool102forms the photoresist layer on the dielectric layer210. The exposure tool104exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool106develops and removes portions of the photoresist layer to expose the pattern. The etch tool108etches the dielectric layer210, the ESL208, and/or the dielectric capping layer218based on the pattern to form the openings502aand502b. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for etching the openings502aand502bbased on a pattern. In some implementations, the opening502aand the opening502bare formed by different patterning processes. For example, the opening502ais formed before or after the opening502b.

As shown inFIG.5D, the semiconductor substrate144is positioned in the processing chamber122(e.g., the CVD processing chamber) of the CVD tool120such that a CVD operation may be performed to form the gate interconnect structure226ain the opening502aand over a metal gate structure212. Moreover, the CVD operation may be performed to form the source/drain interconnect structure226bin the opening502band over and/or on a metal source/drain contact222. The CVD operation includes providing a flow of the processing vapor126into the processing chamber122to form the interconnect structures226aand226b. In some implementations, the interconnect structures226aand226bare each formed to a width that is in a range of approximately 10 nanometers to approximately 75 nanometers. In some implementations, the interconnect structures226aand226bare each formed to a width that is in a range of approximately 10 nanometers to approximately 20 nanometers. In some implementations, the interconnect structures226aand226bare formed to another width. In some implementations, the interconnect structure226ais formed with a different width than the interconnect structure226b. For example, the interconnect structure226amay have a larger width than the interconnect structure226b. In some implementations, the interconnect structures226aand226bare each formed to a height or thickness that is in a range of approximately 30 nanometers to approximately 150 nanometers. In some implementations, the interconnect structures226aand226bare formed to another height or thickness. In some implementations, the interconnect structure226ais formed with a different height or thickness than the interconnect structure226b. For example, the interconnect structure226amay have a larger height or thickness than the interconnect structure226b.

In some implementations, a ratio between a first width (e.g., an x-axis width) and a second width (e.g., a y-axis width) of one or more of the interconnect structures226aand226bis in a range of approximately 1:7.5 to approximately 2.5:1. In some implementations, a ratio between a width (e.g., an x-axis width) and a height thickness (e.g., a z-axis dimension) of one or more of the interconnect structures226aand226bis in a range of approximately 1:15 to approximately 5:6. In some implementations, a ratio between a width (e.g., a y-axis width) and a height thickness (e.g., a z-axis dimension) of one or more of the interconnect structures226aand226bis in a range of approximately 1:15 to approximately 15:6.

The CVD operation to deposit the interconnect structures226aand226bincludes performing a low-flow CVD operation to promote substantially uniform growth of the metal source/drain contacts222(the tungsten layers). The low-flow CVD operation may be performed using the concentration and/or flow rate of fluorine hexafluoride as described above for the low-flow CVD operation inFIG.3D. Accordingly, the low-flow CVD operation may achieve similar properties and/or attributes for the interconnect structures226aand226bas described above for the metal capping layer216. Moreover, as a result of the lesser concentration of the tungsten hexafluoride in the flow of the processing vapor126, the time duration for the low-flow CVD operation (e.g., to achieve the appropriate thickness for the interconnect structures226aand226b) is greater relative to the time duration for the high-flow CVD operation described above. As an example, the time duration for the low-flow CVD operation may be in a range of approximately 100 seconds to approximately 450 seconds to achieve the approximate thickness for the interconnect structures226aand226b, whereas the time duration for the high-flow CVD operation may be in a range of approximately 75 seconds to approximately 230 seconds to achieve a similar thickness.

FIG.5Eillustrates the deposited gate interconnect structure226aover the metal gate structure212and the source/drain interconnect structure226bover and/or on the metal source/drain contact222, as formed by the low-flow CVD operation described above. In some implementations, the deposited gate interconnect structure226aand the source/drain interconnect structure226bare formed by different patterning processes. For example, the deposited gate interconnect structure226ais formed before or after the source/drain interconnect structure226b.

As indicated above,FIGS.5A-5Eare provided as an example. Other examples may differ from what is described with regard toFIGS.5A-5E.

FIGS.6A and6Bare diagrams of example CVD deposition rates described herein.FIG.6Aillustrates an example sequence610of a high-flow CVD operation having a high deposition rate described herein. The high-flow CVD operation is performed to form a tungsten layer on a semiconductor substrate612. As shown inFIG.6A, tungsten precursors614are provided at a high concentration to achieve the high deposition rate of the high-flow CVD operation. The high deposition rate results in uneven (non-uniform) deposition of tungsten on the semiconductor substrate612, which may result in the formation of tungsten islands, discontinuities, voids, and/or poor surface uniformity of the tungsten layer on the semiconductor substrate612.

FIG.6Billustrates an example sequence620of a low-flow CVD operation, described herein, having a lower deposition rate to the high-flow CVD operation. The low-flow CVD operation is performed to form a tungsten layer on a semiconductor substrate622, which may correspond to the semiconductor substrate144. As shown inFIG.6B, tungsten precursors624are provided at a lower concentration relative to the concentration of tungsten precursors614in the high-flow CVD operation. This results in the lower deposition rate and, as a result, a slower tungsten layer formation on the semiconductor substrate622relative to the tungsten layer formation on the semiconductor substrate612. As further shown inFIG.6B, the lower deposition rate results in a more uniform deposition of tungsten on the semiconductor substrate622relative to the deposition of tungsten on the semiconductor substrate612. Moreover, the lower deposition rate may reduce the incubation time for the tungsten layer on the semiconductor substrate622relative to the higher deposition rate used to form the tungsten layer on the semiconductor substrate612.

As indicated above,FIGS.6A and6Bare provided as examples. Other examples may differ from what is described with regard toFIGS.6A and6B.

FIGS.7A and7Bare diagrams of example fluorine intensities in semiconductor devices described herein.FIG.7Aillustrates an example710of fluorine intensities in semiconductor devices on which tungsten layers are formed. The semiconductor devices include a tungsten layer (e.g., of approximately 100 angstrom thickness or another thickness) on a cobalt layer (e.g., of approximately 40 angstrom thickness or another thickness). The example710illustrates the fluorine intensities in tungsten layer and in the cobalt layer (from left to right in the data plot).

The lines in the data plot in the example710represent fluorine intensities for different tungsten hexafluoride concentrations that might be used in CVD operations to form the tungsten layers of the semiconductor devices. The line712represents the fluorine intensity in a tungsten layer on a cobalt layer of a semiconductor device for which a high tungsten hexafluoride concentration was used. The line714represents the fluorine intensity in a tungsten layer on a cobalt layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line712was used. The line716represents the fluorine intensity in a tungsten layer on a cobalt layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line714was used. The line718represents the fluorine intensity in a tungsten layer on a cobalt layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line716was used. The line720represents the fluorine intensity in a tungsten layer on a cobalt layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line718was used. The line722represents the fluorine intensity in a tungsten layer on a cobalt layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line720was used. The line724represents the fluorine intensity in a tungsten layer on a cobalt layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line722was used.

As shown inFIG.7A, the intensity (and thus, the concentration) of fluorine in the tungsten layers and the cobalt layers of the semiconductor devices generally decreases correspondingly with the decrease in hexafluoride concentration from line712to line724. Thus, the low-flow CVD operations described herein may achieve a lesser fluorine concentration, which reduces the damage (and/or the likelihood of damage) to the cobalt layers caused by the fluorine in the tungsten hexafluoride and/or reduces the impact of the fluorine in the tungsten hexafluoride on the resistivity between the tungsten layers and the cobalt layers of the semiconductor devices.

FIG.7Billustrates an example730of fluorine intensities in semiconductor devices on which tungsten layers are formed. The semiconductor devices include an upper tungsten layer (e.g., of approximately 100 angstrom thickness or another thickness) on a lower tungsten layer (e.g., of approximately 30 angstrom thickness). The example730illustrates the fluorine intensities in upper tungsten layer and in the lower tungsten layer (from left to right in the data plot).

The lines in the data plot in the example730represent fluorine intensities for different tungsten hexafluoride concentrations that might be used in CVD operations to form the upper tungsten layers of the semiconductor devices. The line732represents the fluorine intensity in an upper tungsten layer on a lower tungsten layer of a semiconductor device for which a high tungsten hexafluoride concentration was used. The line734represents the fluorine intensity in an upper tungsten layer on a lower tungsten layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line732was used. The line736represents the fluorine intensity in an upper tungsten layer on a lower tungsten layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line734was used. The line738represents the fluorine intensity in an upper tungsten layer on a lower tungsten layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line736was used. The line740represents the fluorine intensity in an upper tungsten layer on a lower tungsten layer of a semiconductor device for which a tungsten hexafluoride concentration that is lower than the tungsten hexafluoride concentration associated with line738was used.

As shown inFIG.7B, the intensity (and thus, the concentration) of fluorine in the upper tungsten layers and in a lower tungsten layers of the semiconductor devices generally decreases correspondingly with the decrease in hexafluoride concentration from line732to line740. Thus, the low-flow CVD operations described herein may achieve a lesser fluorine concentration, which reduces the damage (and/or the likelihood of damage) to the lower tungsten layers caused by the fluorine in the tungsten hexafluoride and/or reduces the impact of the fluorine in the tungsten hexafluoride on the resistivity between the upper tungsten layers and the lower tungsten layers of the semiconductor devices.

As indicated above,FIGS.7A and7Bare provided as examples. Other examples may differ from what is described with regard toFIGS.7A and7B.

FIG.8is a diagram of an example semiconductor device800described herein. The semiconductor device800includes an example of a semiconductor device that may be formed on the semiconductor substrate144. As shown inFIG.8, the semiconductor device800includes a substrate802, which may correspond to the semiconductor substrate144and/or the device substrate202. The semiconductor device800further includes a lower layer804included in the substrate802and an upper layer806on the lower layer804. The lower layer804includes metal layer (e.g., a cobalt layer, a tungsten layer), a metal silicide layer, or another type of layer. In some implementations, the lower layer804corresponds to a metal gate structure212, a metal source/drain contact222, a metal capping layer216, a metal silicide layer404, and/or a metal gate contact, among other examples. The lower layer804may include curved sides and an approximately flat bottom surface. The top surface of the lower layer804may be approximately curved.

The upper layer806includes a tungsten layer such as a metal source/drain contact222, a metal capping layer216, a metal gate contact, a gate interconnect structure226a, and/or a source/drain interconnect structure226b, among other examples. The bottom surface of the upper layer806may conform to the approximately curved top surface of the lower layer804. Moreover, the upper layer806may include approximately curved sides.

The upper layer806is formed by one or more of the low-flow CVD operations described herein. Accordingly, the top surface of the upper layer806is substantially uniform and free of voids, islands, and/or other types of discontinuities. Moreover, the top surface of the upper layer806may have relatively low surface roughness and grain size (e.g., relative to another tungsten layer formed by a high-flow CVD operation).

As indicated above,FIG.8is provided as an example. Other examples may differ from what is described with regard toFIG.8.

FIG.9is a diagram of example components of a device900. In some implementations, the deposition tool102(e.g., the CVD tool120or one or more components included in the CVD tool120described herein), the exposure tool104, the developer tool106, the etch tool108, the planarization tool110, and/or the wafer/die transport tool112may include one or more devices900and/or one or more components of device900. As shown inFIG.9, device900may include a bus910, a processor920, a memory930, an input component940, an output component950, and a communication component960.

Bus910includes one or more components that enable wired and/or wireless communication among the components of device900. Bus910may couple together two or more components ofFIG.9, such as via operative coupling, communicative coupling, electronic coupling, and/or electric coupling. Processor920includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor920is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor920includes one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

Memory930includes volatile and/or nonvolatile memory. For example, memory930may include random access memory (RAM), read only memory (ROM), a hard disk drive, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). Memory930may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable via a universal serial bus connection). Memory930may be a non-transitory computer-readable medium. Memory930stores information, instructions, and/or software (e.g., one or more software applications) related to the operation of device900. In some implementations, memory930includes one or more memories that are coupled to one or more processors (e.g., processor920), such as via bus910.

Input component940enables device900to receive input, such as user input and/or sensed input. For example, input component940may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and/or an actuator. Output component950enables device900to provide output, such as via a display, a speaker, and/or a light-emitting diode. Communication component960enables device900to communicate with other devices via a wired connection and/or a wireless connection. For example, communication component960may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

Device900may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory930) may store a set of instructions (e.g., one or more instructions or code) for execution by processor920. Processor920may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions, by one or more processors920, causes the one or more processors920and/or the device900to perform one or more operations or processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally, or alternatively, processor920may be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown inFIG.9are provided as an example. Device900may include additional components, fewer components, different components, or differently arranged components than those shown inFIG.9. Additionally, or alternatively, a set of components (e.g., one or more components) of device900may perform one or more functions described as being performed by another set of components of device900.

FIG.10is a flowchart of an example process1000relating to low flow chemical vapor deposition for uniform tungsten growth described herein. In some implementations, one or more process blocks ofFIG.10may be performed by a CVD tool (e.g., the CVD tool120, a deposition tool102). Additionally, or alternatively, one or more process blocks ofFIG.10may be performed by one or more components of device900, such as processor920, memory930, input component940, output component950, and/or communication component960.

As shown inFIG.10, process1000may include providing a flow of a processing vapor into a CVD processing chamber (block1010). For example, the CVD tool120(e.g., using the vapor supply system124) may provide a flow of a processing vapor126into a CVD processing chamber (e.g., the processing chamber122of the deposition tool102), as described herein. In some implementations, the flow of the processing vapor126includes a combination of tungsten hexafluoride (WF6) and a carrier gas.

As further shown inFIG.10, process1000may include performing a CVD operation to form a tungsten layer on a semiconductor substrate using the flow of the processing vapor (block1020). For example, the CVD tool120(e.g., using the processing chamber122) may perform a CVD operation to form a tungsten layer (e.g., the metal capping layer216, the metal source/drain contact222, the gate interconnect structure226a, and/or the source/drain interconnect structure226) on the semiconductor substrate144using the flow of the processing vapor126, as described herein. In some implementations, the flow of the processing vapor126is provided such that a flow rate of the tungsten hexafluoride in the flow of the processing vapor126results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer.

Process1000may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.

In a first implementation, the flow rate of the tungsten hexafluoride in the flow of the processing vapor126is in a range of approximately 1 SCCM to approximately 10 SCCM. In a second implementation, alone or in combination with the first implementation, the flow rate of the tungsten hexafluoride in the flow of the processing vapor126is configured to achieve a surface roughness for the tungsten layer that is in a range of approximately 0.9 RMS roughness to approximately 1.2 RMS roughness. In a third implementation, alone or in combination with one or more of the first and second implementations, the flow rate of the tungsten hexafluoride in the flow of the processing vapor126is configured to achieve a fluorine concentration in the tungsten layer that is in a range of approximately 100 arbitrary units to approximately 10000 arbitrary units.

In a fourth implementation, alone or in combination with one or more of the first through third implementations, the tungsten layer includes a metal source/drain contact222that is formed over a source/drain region220on the semiconductor substrate144, and a time duration of the CVD operation, resulting from the flow rate of the tungsten hexafluoride, is in a range of approximately 150 seconds to approximately 500 seconds. In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, the tungsten layer includes a metal capping layer216that is formed over a metal gate structure212on the semiconductor substrate144, and a time duration of the CVD operation, resulting from the flow rate of the tungsten hexafluoride, is in a range of approximately 40 seconds to approximately 100 seconds. In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, the tungsten layer includes an interconnect structure (e.g., the gate interconnect structure226a, the source/drain interconnect structure226b) that is formed over a metal gate structure212or over a metal source/drain contact222that is formed over a source/drain region220on the semiconductor substrate, and a time duration of the CVD operation, resulting from the flow rate of the tungsten hexafluoride, is in a range of approximately 100 seconds to approximately 450 seconds.

AlthoughFIG.10shows example blocks of process1000, in some implementations, process1000may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.10. Additionally, or alternatively, two or more of the blocks of process1000may be performed in parallel.

FIG.11is a flowchart of an example process1100relating to low flow chemical vapor deposition for uniform tungsten growth described herein. In some implementations, one or more process blocks ofFIG.11may be performed by a CVD tool (e.g., the CVD tool120, a deposition tool102). Additionally, or alternatively, one or more process blocks ofFIG.11may be performed by one or more components of device900, such as processor920, memory930, input component940, output component950, and/or communication component960.

As shown inFIG.11, process1100may include generating a flow of a processing vapor (126) that includes tungsten hexafluoride (WF6) and a carrier gas (block1110). For example, the CVD tool120(e.g., using the vapor supply system124) may generate a flow of a processing vapor126that includes tungsten hexafluoride (WF6) and a carrier gas, as described herein.

As further shown inFIG.11, process1100may include providing the flow of the processing vapor into a CVD processing chamber through a showerhead (block1120). For example, the CVD tool120(e.g., using the vapor supply system124) may provide the flow of the processing vapor into a CVD processing chamber (e.g., the processing chamber122) through the showerhead132, as described herein.

As further shown inFIG.11, process1100may include performing a CVD operation to form a tungsten layer on a metal layer included on a semiconductor substrate using the flow of the processing vapor (block1130). For example, the CVD tool120(e.g., using the processing chamber122) may perform a CVD operation to form a tungsten layer (e.g., a metal capping layer216, a metal source/drain contact222, a gate interconnect structure226a, and/or a source/drain interconnect structure226) on a metal layer (e.g., a metal gate structure212, a metal capping layer216, a metal source/drain contact222, and/or a metal silicide layer404) included on the semiconductor substrate144using the flow of the processing vapor126, as described herein. In some implementations, a ratio between the tungsten hexafluoride and the carrier gas in the flow of the processing vapor126results in a deposition rate for the CVD operation that is greater than a deposition rate for an ALD operation. In some implementations, the ratio between the tungsten hexafluoride and the carrier gas in the flow of the processing vapor126results in surface uniformity performance for the CVD operation that is approximately equal to a surface uniformity performance for the ALD operation. In some implementations, the tungsten layer is formed as a result of a reaction during the CVD operation that results in tungsten of the tungsten hexafluoride being deposited onto the metal layer, and results in formation of a hydrofluoric acid as a by-product. In some implementations, a concentration of the tungsten hexafluoride in the flow of the processing vapor126is configured to reduce fluorine concentration in the tungsten layer.

Process1100may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.

In a first implementation, the ratio of the tungsten hexafluoride to the carrier gas in the flow of the processing vapor126is in a range of approximately 1:7200 to approximately 10:5400. In a second implementation, alone or in combination with the first implementation, performing the CVD operation to form the tungsten layer includes performing the CVD operation to form the tungsten layer as part of a dummy gate replacement process (e.g., the process illustrated and described in connection withFIGS.3A-3F). In a third implementation, alone or in combination with one or more of the first and second implementations, the ratio between the tungsten hexafluoride and the carrier gas in the flow of the processing vapor126promotes uniform growth of the tungsten layer.

In a fourth implementation, alone or in combination with one or more of the first through third implementations, the ratio between the tungsten hexafluoride and the carrier gas in the flow of the processing vapor126is configured to reduce a grain size of the tungsten layer. In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, performing the CVD operation to form the tungsten layer includes performing the CVD operation to selectively deposit the tungsten layer on the metal layer between dielectric sidewalls (e.g., the ESL208, the dielectric layer210, a plurality of sidewall spacers214, a dielectric capping layer218, and/or the CESL224) of an opening (e.g., an opening312, an opening402a, an opening402b, an opening502a, and/or an opening502b) over the metal layer. In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, the metal layer includes at least one of a metal gate structure212, a metal capping layer216, a metal gate contact, or a metal source/drain contact222.

In a seventh implementation, alone or in combination with one or more of the first through sixth implementations, the concentration of the tungsten hexafluoride in the flow of the processing vapor126is configured to reduce island formation in the tungsten layer. In an eighth implementation, alone or in combination with one or more the first through seventh implementations, the concentration of the tungsten hexafluoride in the flow of the processing vapor126is configured to reduce pattern loading for the tungsten layer. In a ninth implementation, alone or in combination with one or more of the first through eighth implementations, the concentration of the tungsten hexafluoride in the flow of the processing vapor126is in a range of approximately 1 SCCM to approximately 10 SCCM.

In a tenth implementation, alone or in combination with one or more of the first through ninth implementations, performing the CVD operation to form the tungsten layer includes performing the CVD operation to deposit the tungsten layer on the metal layer between dielectric sidewalls of an opening over the metal layer (e.g., the ESL208, the dielectric layer210, a plurality of sidewall spacers214, a dielectric capping layer218, and/or the CESL224) of an opening (e.g., an opening312, an opening402a, an opening402b, an opening502a, and/or an opening502b), where the tungsten hexafluoride resists deposition onto the dielectric sidewalls. In an eleventh implementation, alone or in combination with one or more of the first through tenth implementations, the fluorine concentration in the tungsten layer is in a range of approximately 100 arbitrary units to approximately 10000 arbitrary units.

AlthoughFIG.11shows example blocks of process1100, in some implementations, process1100may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.11. Additionally, or alternatively, two or more of the blocks of process1100may be performed in parallel.

In this way, the low-flow tungsten CVD techniques described herein provide uniform deposition of tungsten on a semiconductor substrate. In some implementations described herein, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques described herein may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).

As described in greater detail above, some implementations described herein provide a method. The method includes providing a flow of a processing vapor into a CVD processing chamber, where the flow of the processing vapor includes a combination of tungsten hexafluoride (WF6) and a carrier gas. The method includes performing a CVD operation to form a tungsten layer on a semiconductor substrate using the flow of the processing vapor, where the flow of the processing vapor is provided such that a flow rate of the tungsten hexafluoride in the flow of the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer.

As described in greater detail above, some implementations described herein provide a method. The method includes generating, by a vapor supply system, a flow of a processing vapor that includes tungsten hexafluoride (WF6) and a carrier gas. The method includes providing, by the vapor supply system, the flow of the processing vapor into a CVD processing chamber through a showerhead. The method includes performing a CVD operation to form a tungsten layer on a metal layer included on a semiconductor substrate using the flow of the processing vapor, where a ratio between the tungsten hexafluoride and the carrier gas in the flow of the processing vapor results in a deposition rate for the CVD operation that is greater than a deposition rate for an ALD operation, and where the ratio between the tungsten hexafluoride and the carrier gas in the flow of the processing vapor results in surface uniformity performance for the CVD operation that is approximately equal to a surface uniformity performance for the ALD operation.

As described in greater detail above, some implementations described herein provide a method. The method includes generating, by a vapor supply system, a flow of a processing vapor that includes tungsten hexafluoride (WF6) and a carrier gas. The method includes providing, by the vapor supply system, the flow of the processing vapor into a CVD processing chamber through a showerhead. The method includes performing a CVD operation to form a tungsten layer on a metal layer included on a semiconductor substrate using the flow of the processing vapor, where the tungsten layer is formed as a result of a reaction during the CVD operation that results in tungsten of the tungsten hexafluoride being deposited onto the metal layer, and results in formation of a hydrofluoric acid as a by-product, and where a concentration of the tungsten hexafluoride in the flow of the processing vapor is configured to reduce fluorine concentration in the tungsten layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.