Patent ID: 12211578

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

With reference now to the Figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

The terms “computing device” and “mobile device” are used interchangeably herein to refer to any one or all of servers, personal computers, smartphones, cellular telephones, tablet computers, laptop computers, netbooks, ultrabooks, palm-top computers, personal data assistants (PDAs), wireless electronic mail receivers, multimedia Internet-enabled cellular telephones, Global Positioning System (GPS) receivers, wireless gaming controllers, and similar personal electronic devices which include a programmable processor. While the various aspects are particularly useful in mobile devices (e.g., smartphones, laptop computers, etc.), which have limited resources (e.g., processing power, battery, size, etc.), the aspects are generally useful in any computing device that may benefit from improved processor performance and reduced energy consumption.

The term “multicore processor” is used herein to refer to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions. The term “multiprocessor” is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.

The term “system on chip” (SoC) is used herein to refer to a single integrated circuit (IC) chip that contains multiple resources and/or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio-frequency functions. A single SoC may also include any number of general purpose and/or specialized processors (digital signal processors (DSPs), modem processors, video processors, etc.), memory blocks (e.g., read only memory (ROM), random access memory (RAM), flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.

Memory technologies described herein may be suitable for storing instructions, programs, control signals, and/or data for use in or by a computer or other digital electronic device. Any references to terminology and/or technical details related to an individual type of memory, interface, standard, or memory technology are for illustrative purposes only, and not intended to limit the scope of the claims to a particular memory system or technology unless specifically recited in the claim language. Mobile computing device architectures have grown in complexity, and now commonly include multiple processor cores, SoCs, co-processors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnections (e.g., buses and/or fabrics), and numerous other resources that execute complex and power intensive software applications (e.g., video streaming applications, etc.).

Certain aspects of the disclosure are applicable to input/out (I/O) circuits that provide an interface between core circuits and memory devices. Many mobile devices employ Synchronous Dynamic Random Access Memory (SDRAM), including Low-Power double data rate SDRAM, which may be referred to as low-power DDR SDRAM, LPDDR SDRAM or, in some instances, LPDDRi SDRAM where i describes the technology generation of the LPDDR SDRAM. Examples of LPDDR SDRAM include LPDDR2 SDRAM, LPDDR4 SDRAM and LPDDR4X SDRAM, where LPDDR4X SDRAM may refer to a variant of LPDDR4 SDRAM that provides improved power saving capabilities over LPDDR4 SDRAM. Later generations of LPDDR SDRAM designed to operate at higher operating frequencies may employ lower voltage levels in the core of an SoC or memory device to mitigate for increased power associated with the higher operating frequencies.

Process technology employed to manufacture semiconductor devices, including IC devices is continually improving. Process technology includes the manufacturing methods used to make IC devices and defines transistor size, operating voltages and switching speeds. Features that are constituent elements of circuits in an IC device may be referred as technology nodes and/or process nodes. The terms technology node, process node, process technology may be used to characterize a specific semiconductor manufacturing process and corresponding design rules. Faster and more power-efficient technology nodes are being continuously developed through the use of smaller feature size to produce smaller transistors that enable the manufacture of higher-density ICs. The evolution of transistor technology has led to decreased gate oxide thickness and lower operating voltages. Gate oxide thickness may be configured to be a fraction of transistor channel length. In one example, the gate oxide thickness is between 2% and 4% of the length of the transistor channel. As transistor size decreases, the corresponding reduction in gate oxide thickness reduces the maximum gate-drain, operating voltage that can be used with the device.

ICs typically provide multiple voltage domains for power saving purposes. For example, higher voltage domains provide power at higher voltage levels than lower voltage domains. Higher voltage domains are sometimes needed for interfacing with external devices, while core logic circuits can generally operate at the lower voltage levels available in lower voltage domains. For the purposes of this disclosure, a thick-oxide transistor may refer to a transistor that has a gate oxide thickness sufficient to enable the transistor to withstand and operate at the higher voltage levels in higher voltage domains and a thin-oxide transistor may refer to a transistor that has a gate oxide thickness that is insufficient to avoid electrical overstress when the transistor spans a higher voltage level in the higher voltage domains. In certain examples disclosed herein, a thin-oxide transistor may be rated for voltages up to 0.6 volts and a thick-oxide transistor may be rated for voltages greater than 0.6 volts and thick-oxide transistors may be used in a higher a high-voltage domain that provides power at 1.2 volts.

FIG.1illustrates example components and interconnections in a system-on-chip (SoC)100that may be suitable for implementing certain aspects of the present disclosure. The SoC100may include a number of heterogeneous processors, such as a central processing unit (CPU)102, a modem processor104, a graphics processor106, and an application processor108. Each processor102,104,106,108, may include one or more cores, and each processor/core may perform operations independent of the other processors/cores. The processors102,104,106,108may be organized in close proximity to one another (e.g., on a single substrate, die, integrated chip, etc.) so that the processors may operate at a much higher frequency/clock rate than would be possible if the signals were to travel off-chip. The proximity of the cores may also allow for the sharing of on-chip memory and resources (e.g., voltage rails), as well as for more coordinated cooperation between cores. As used herein, a voltage rail refers to the means by which power at a specified voltage is distributed throughout an IC.

The SoC100may include system components and resources110for managing sensor data, analog-to-digital conversions, and/or wireless data transmissions, and for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). System components and resources110may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and/or other similar components used to support the processors and software clients running on the computing device. The system components and resources110may also include circuitry for interfacing with peripheral devices, such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

The SoC100may further include a Universal Serial Bus (USB) or other serial bus controller112, one or more memory controllers114, and a centralized resource manager (CRM)116. The SoC100may also include an input/output module (not illustrated) for communicating with resources external to the SoC, each of which may be shared by two or more of the internal SoC components.

The processors102,104,106,108may be interconnected to the USB controller112, the memory controller114, system components and resources110, CRM116, and/or other system components via an interconnection/bus module122, which may include an array of reconfigurable logic gates and/or implement a bus architecture. Communications may also be provided by advanced interconnects, such as high-performance networks on chip (NoCs).

The interconnection/bus module122may include or provide a bus mastering system configured to grant SoC components (e.g., processors, peripherals, etc.) exclusive control of the bus (e.g., to transfer data in burst mode, block transfer mode, etc.) for a set duration, number of operations, number of bytes, etc. In some cases, the interconnection/bus module122may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously. The memory controller114may be a specialized hardware module configured to manage the flow of data to and from memory124via a memory interface/bus126.

The memory controller114may comprise one or more processors configured to perform read and write operations with the memory124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. In certain aspects, the memory124may be part of the SoC100. In certain aspects, the memory124may conform to specifications governing the manufacture and use of one or more types of LPDDRi SDRAM.

Certain memory devices may be configurable to operate in accordance with specifications defining the operational characteristics of multiple types of LPDDRi SDRAM. In one example, a memory device may be operated in LPDDR2 SDRAM and LPDDR4X SDRAM modes of operation, which may be referred to herein as the “LP2” and “LP4X” modes, respectively. The memory device includes double data rate input/output circuits (DDRIO) that enable the memory device to communicate with corresponding I/O circuits in the SoC100or another device coupled to the memory device. The DDRIO may be configurable for multi-mode operation. In some instances, a transmitter in the DDRIO of a memory device that supports LP2 and LP4X modes of operation may include multiple circuits that perform the same function at different voltage levels.

FIG.2illustrates an example of a transmitter200in the DDRIO of a memory device that can be operated in LP2 and LP4X modes. In the illustrated example, the transmitter200is coupled to and drives an input/output pad (the I/O pad208) using multiple driver circuits. As used herein, the term input/output pad relates to a structure that is part of a coupling that conducts signals between internal circuits of the core of an IC device and the external terminals, connectors or pins of a chip package that carries the IC device. In one example, input/output pads may be coupled to external terminals, connectors or pins through wires that are thermosonically bonded to the input/output pads. In another example, input/output pads may be coupled to external terminals, connectors or pins through solder balls that contact the input/output pads. The process technology used to manufacture the memory device that includes the transmitter200, the signaling scheme and the operating voltages may determine the type of transistor gate oxide used in the transmitter200.

In the illustrated example, the I/O pad208is coupled to an output voltage rail (VDDIO210) through one driver circuit configured as an LP2 mode pullup circuit202or through another driver circuit configured as an LP4X pullup circuit204. The LP2 mode pullup circuit202can be used to drive the I/O pad208when the transmitter200is configured for the LP2 mode of operation in which VDDIOmay provide power at 1.2 Volts. The LP4X pullup circuit204can be used to drive the I/O pad208when the transmitter200is configured for the LP4X mode of operation in which VDDIOmay provide power at 0.6 Volts. The illustrated LP2 mode pullup circuit202is implemented using only thick-oxide transistors. The illustrated LP4X pullup circuit204is implemented using a combination of thin-oxide transistors212and thick-oxide transistors214,2160-216n.

In the illustrated example, the I/O pad208is coupled to the lowest voltage rail (i.e., VSSX220) through yet another driver circuit configured as a pulldown circuit206that is used in the LP2 mode and the LP4X mode. The illustrated pulldown circuit206is implemented using a combination of thick-oxide transistors2180-218nand thin-oxide transistors222. For the purposes of this disclosure, the highest voltage power supply rail in the memory device may be referred to as VDDPX, the lowest voltage power supply rail is referred to as VSSX.

In order to operate as a combination transmitter that functions in both the LP4x and LP2 modes, the DDRIO transmitter200is required to conform to signaling schemes and voltage domains defined by the corresponding specifications and standards. To meet these requirements, the DDRIO transmitter200is implemented using a combination of thick-gate and thin-gate devices. The voltage domains in which the transmitter200operates include voltage rails that deliver power to various sections of a memory device. For example, VDDIO210is shared with SDRAM circuits and provided to the LP2 mode pullup circuit202and LP4X pullup circuit204(driver circuits) at 1.2 volts in LP2 mode and at 0.6 volts in LP4x mode. Another voltage rail (VDDA) is shared across the physical interface (PHY) of the memory device and is used to power pre-driver and logic circuits coupled to the DDRIO transmitter200. In many examples, the voltage level of VDDAis scalable and may be collapsed to improve power efficiency of the PHY.

Conventional combination transmitters do not support VDDAcollapse in which voltage of the VDDAvoltage rail is expected to drop to a zero-volt level, which correspond to the voltage level of VSSXin some instances. Some conventional combination transmitters support a “retention mode” in which the voltage level of VDDAis scaled to a lower level or intermediate level voltage. In conventional transmitters, VDDAcollapse is typically avoided to prevent electrical overstress (EOS) of thin-oxide transistors in the LP2 mode.

FIG.3illustrates certain aspects of retention mode in a combination transmitter that supports LP4X and LP2 modes. The first timing diagram300illustrates entry into retention mode when the combination transmitter is operated in the LP4X mode. Entry into retention mode commences at a point in time308at which the voltage level of VDDA302drops from 0.89 volts to 0.35 volts. The highest voltage power available to the transmitter is provided by VDDPX304, which remains at a constant voltage level. The voltage level of VDDIO306is not tied to the voltage level of VDDPX304and drops from 0.6 volts to 0 volts. In the LP4X mode, the maximum voltage across the thin-oxide transistor212upon entry into the retention mode is defined by the voltage applied to the gate of the thin-oxide transistor212, which is driven by pre-driver and logic circuits powered by VDDA302. In retention mode, the voltage of VDDA302is 0.35 volts.

The second timing diagram320illustrates entry into retention mode when the combination transmitter is operated in the LP2 mode. Certain retention mode voltages in the LP4X pullup circuit204during LP2 mode operation are illustrated in the circuit diagram340. Entry into retention mode commences at a point in time328at which the voltage level of VDDA322drops from 0.89 volts to 0.35 volts. The highest voltage power available to the transmitter is provided by VDDPX324, which remains at a constant voltage level. The voltage level of VDDIO326is tied to the voltage level of VDDPX304and remains at 1.2 volts. In the LP2 mode, the thin-oxide transistor212is inactive and turned off by a signal342that is driven to a high signaling state by pre-driver and logic circuits powered by VDDA322. In retention mode, the voltage of VDDA322is 0.35 volts. The maximum voltage across the thin-oxide transistor212upon entry into the retention mode may be calculated as 1.2−0.35=0.85 volts, which is less than the maximum voltage level of VDDA322, and which consequently lies within the maximum operating voltage level defined for the thin-oxide transistor212.

FIG.4illustrates certain aspects of voltage collapse in a combination transmitter that supports LP4x and LP2 modes. The first timing diagram400illustrates entry into voltage collapse when the combination transmitter is operated in the LP4X mode. Entry into voltage collapse commences at a point in time408at which the voltage level of VDDA402drops from 0.89 volts to 0 volts. The highest voltage power available to the transmitter is provided by VDDPX404, which remains at a constant voltage level. The voltage level of VDDIO406is not tied to the voltage level of VDDPX404and drops from 0.6 volts to 0 volts. In the LP4X mode, the maximum voltage across the thin-oxide transistor212upon entry into voltage collapse is defined by the voltage applied to the gate of the thin-oxide transistor212, which is driven by pre-driver and logic circuits powered by VDDA402. In voltage collapse, the voltage of VDDA402is 0 volts.

The second timing diagram420illustrates entry into voltage collapse when the combination transmitter is operated in the LP2 mode. Certain voltages in the LP4X pullup circuit204during voltage collapse in LP2 mode operation are illustrated in the circuit diagram440. Voltage collapse commences at a point in time428at which the voltage level of VDDA422drops from 0.89 volts to 0 volts. The highest voltage power available to the transmitter is provided by VDDPX424, which remains at a constant 1.2 V voltage level. The voltage level of VDDIO426is tied to the voltage level of VDDPX404and remains at 1.2 volts. The thin-oxide transistor212is controlled by a signal442that is received from pre-driver and logic circuits powered by VDDA422. In the LP2 mode, VDDA422is at 0 volts during voltage collapse, the signal442received from pre-driver and logic circuits can be expected to be at 0 volts during voltage collapse, and the thin-oxide transistor212is then turned on. In the LP4X mode, the maximum voltage across the thin-oxide transistor212(gate-drain and/or gate-source voltage) during voltage collapse can be expected to be 1.2 volts and may exceed the maximum operating voltage level defined for the thin-oxide transistor212, thereby causing EOS.

Certain aspects of this disclosure provide circuits, methods and techniques that enable a combination transmitter to avoid EOS during voltage collapse, including when the combination transmitter is operating in LP2 mode. In one aspect, overall system power efficiency can be improved when the combination transmitter is configured to withstand voltage collapse on VDDAand the entire PHY can enter low-power or idle states.

FIG.5illustrates an example of a DDRIO transmitter500configured in accordance with certain aspects disclosed herein. The DDRIO transmitter500includes certain features of the DDRIO transmitter200illustrated inFIG.2and may be implemented in a memory device that can be operated in LP2 and LP4X modes. The DDRIO transmitter500supports voltage collapse in both LP2 mode and LP4X mode.

In the illustrated example, the transmitter500is coupled to, and drives an input/output pad (the I/O pad508) using multiple driver circuits. The I/O pad508can be coupled to an output voltage rail (VDDIO510) through one driver circuit configured as an LP2 mode pullup circuit502or through another driver circuit configured as an LP4X pullup circuit504. In one example, the LP2 mode pullup circuit502may be used when the transmitter500is configured for the LP2 mode of operation in which VDDIOprovides power at 1.2 Volts, and the LP4X pullup circuit504may be used when the transmitter500is configured for the LP4X mode of operation in which VDDIOprovides power at 0.6 Volts. The LP2 mode pullup circuit502may be implemented using thick-oxide transistors. In the illustrated example, the LP4X pullup circuit504is implemented using a combination of thin-oxide transistors512and thick-oxide transistors514,5160-516n. The process technology used to manufacture the memory device, signaling scheme and voltage domain that includes the transmitter500may determine the type of transistor oxide used in the transmitter500.

In the illustrated example, the I/O pad508is coupled to the lowest voltage power supply rail (i.e., VSSX518) through yet another driver circuit configured as a pulldown circuit506regardless of the mode of operation of the transmitter500. The pulldown circuit506may be implemented using thick-oxide transistors.

The DDRIO transmitter500can operate as a combination transmitter that functions in both the LP4x and LP2 modes, and the DDRIO transmitter500may be configured to operate using different signaling schemes and in different voltage domains in accordance with corresponding or relevant specifications and standards. The DDRIO transmitter500may be implemented using a mix of thick-gate and thin-gate device in the pull-up paths. The voltage domains in which the transmitter500operates include voltage rails that deliver power to multiple sections of a memory device. For example, VDDIO510is shared with SDRAM circuits and provided to the LP2 mode pullup circuit502and LP4X pullup circuit504(driver circuits) at 1.2 volts in LP2 mode and at 0.6 volts in LP4x mode. Another voltage rail (VDDA) is shared across the physical interface (PHY) of the memory device and is used to power pre-driver and logic circuits coupled to the DDRIO transmitter500. In many examples, the voltage level of VDDAis scalable and may be collapsed to improve power efficiency of the PHY.

The DDRIO transmitter500supports voltage collapse in which voltages of certain voltage rails are expected to drop to a zero-volt level, or to the level of VSSX. The LP4X pullup circuit504includes a thick-oxide, gate-pull transistor522that is configured to pull the gate of the thin-oxide transistor512to VDDPX520when the DDRIO transmitter500is operated in LP2 mode. The gate-pull transistor522causes the thin-oxide transistor512to be turned off in LP2 mode. A pass gate circuit524is provided to avoid leakage between VDDPXand VDDAin LP2 mode. The pass gate circuit524, which may also be referred to as a transmission gate, is disabled when the DDRIO transmitter500is operated in LP2 mode and the pass gate circuit524remains disabled upon entry into voltage collapse mode.

FIG.6illustrates certain aspects of voltage collapse during LP4x and LP2 modes in the combination transmitter illustrated inFIG.5. The first timing diagram600illustrates entry into voltage collapse when the combination transmitter is operated in the LP4X mode. Entry into voltage collapse commences at a point in time608at which the voltage level of VDDA602drops from 0.89 volts to 0 volts. The highest voltage power available to the transmitter is provided by VDDPX604, which remains at a constant voltage level. The voltage level of VDDIO606is not tied to the voltage level of VDDPX604and drops from 0.6 volts to 0 volts. In the LP4X mode, the maximum voltage across the thin-oxide transistor512upon entry into the voltage collapse mode is defined by the voltage applied to the gate of the thin-oxide transistor512, which is driven by pre-driver and logic circuits powered by VDDA602. In voltage collapse mode, the voltage of VDDA602is 0 volts.

The second timing diagram620illustrates entry into voltage collapse when the combination transmitter is operated in the LP2 mode. Certain voltages in the LP4X pullup circuit504during voltage collapse in LP2 mode operation are illustrated in the circuit diagram640. Voltage collapse commences at a point in time628at which the voltage level of VDDA622drops from 0.89 volts to 0 volts. The highest voltage power available to the transmitter is provided by VDDPX626, which remains at a constant 1.2 V voltage level. The voltage level of VDDIO624is tied to the voltage level of VDDPX604and remains at 1.2 volts.

The gate-pull transistor522and pass gate circuit524operate to avoid EOS that could otherwise affect the thin-oxide transistor512. In one example, the gate-pull transistor522and pass gate circuit524are configured to cause all terminals of thin-oxide transistor512to be pulled to VDDIO624during LP2 mode. In LP2 mode, VDDIO624has the same voltage as the VDDPX626, resulting in no electric potential or a negligible electric potential across the thin-oxide transistor512. When the pass gate circuit524is turned on, the thin-oxide transistor512is controlled by a gating signal642that is received from pre-driver and logic circuits powered by VDDA622. In the LP2 mode, the pass gate circuit524is turned off and the gating signal642is decoupled from the gate of the thin-oxide transistor512. The voltage on the gate of the thin-oxide transistor512is then controlled by the gate-pull transistor522. The pass gate circuit524operates as a switch and can be configured to block transmission of the gating signal642to the gate of the thin-oxide transistor512.

The circuits inFIGS.5and6are provided as examples for illustrative purposes. Certain combinations of thin-oxide P-type metal-oxide-semiconductor (PMOS) transistors and thick-oxide ide N-type metal-oxide-semiconductor (NMOS) transistors are depicted. It is contemplated that the concepts disclosed herein can be implemented using other combinations of thick-oxide NMOS transistors, thin-oxide NMOS transistors, thin-oxide PMOS transistors and thick-oxide PMOS transistors.

FIG.7is a flowchart illustrating an example of a method700for operating a transmitter circuit in an IC device in accordance with certain aspects disclosed herein. The method may relate to various features and aspects of the driver circuits illustrated inFIGS.5and6. At block702, a first driver circuit is configured to drive an I/O pad in an IC device when the transmitter circuit is operated in a first mode. The first driver circuit may include a thin-oxide transistor configured to couple the I/O pad to a first voltage rail when the transmitter circuit is operated in a first mode. At block704, a gate pullup transistor is configured to couple a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level. At block706, a switch is configured to block transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.

In certain examples, a second driver circuit is configured to couple the I/O pad to the first voltage rail when the transmitter circuit is operated in a second mode. The second driver circuit may be disabled when the transmitter circuit is operated in the first mode. The first driver circuit may be disabled when the transmitter circuit is operated in the second mode. The first voltage rail may deliver power at a first voltage level when the transmitter circuit is operated in the first mode and may deliver power at a second voltage level when the transmitter circuit is operated in the second mode. The first voltage level may have a magnitude that is greater than magnitude of the second voltage level. The first voltage rail and the second voltage rail may have a same voltage level when the transmitter circuit is operated in the first mode, and may have different voltage levels when the transmitter circuit is operated in the second mode.

In one example, the switch comprises a transmission gate. In some implementations, the gating signal is provided by a circuit powered by the third voltage rail.

It is noted that the operational steps described in any of the exemplary aspects herein are described to provide examples. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering. In certain aspects, an apparatus performing certain functions disclosed herein may include means for driving an I/O pad provided in an IC device. In some examples, the means for driving the I/O pad includes a thin-oxide transistor in a first driver circuit that is active when the transmitter circuit is operated in a first mode and that is configured to couple the I/O pad to the first voltage rail when active. The apparatus may include means for pulling a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level, and means for blocking transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.

In certain implementations, the means for driving an I/O pad further includes a second driver circuit that is active when the transmitter circuit is operated in a second mode and that is configured to couple the I/O pad to the first voltage rail when active. The second driver circuit may be disabled when the transmitter circuit is operated in the first mode. The first driver circuit may be disabled when the transmitter circuit is operated in the second mode. The first voltage rail may deliver power at a first voltage level when the transmitter circuit is operated in the first mode and may deliver power at a second voltage level when the transmitter circuit is operated in the second mode. The first voltage level may have a magnitude that is greater than the magnitude of the second voltage level. The first voltage rail and the second voltage rail may have a same voltage level when the transmitter circuit is operated in the first mode and different voltage levels when the transmitter circuit is operated in the second mode.

In some instances, the means for blocking transmission of the gating signal comprises a transmission gate. In some implementations, the gating signal is provided by a circuit powered by the third voltage rail.

In one example, a transmitter circuit provided in accordance with certain aspects of this disclosure has a first driver circuit configured to drive an I/O pad in an integrated circuit device, the first driver circuit including a thin-oxide transistor configured to couple the I/O pad to a first voltage rail when the transmitter circuit is operated in a first mode. The transmitter circuit also has a gate pullup transistor configured to couple a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level, and a switch configured to block transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.

In some implementations, the transmitter circuit has a second driver circuit configured to couple the I/O pad to the first voltage rail when the transmitter circuit is operated in a second mode. The second driver circuit may be disabled when the transmitter circuit is operated in the first mode. The first driver circuit may be disabled when the transmitter circuit is operated in the second mode. The first voltage rail may deliver power at a first voltage level when the transmitter circuit is operated in the first mode and at a second voltage level when the transmitter circuit is operated in the second mode. The first voltage level may have a magnitude that is greater than magnitude of the second voltage level. The first voltage rail and the second voltage rail may have the same voltage level when the transmitter circuit is operated in the first mode, and different voltage levels when the transmitter circuit is operated in the second mode. In one example, the switch is implemented using a transmission gate. In some implementations, the gating signal is provided by a circuit that is powered by the third voltage rail.

Some implementation examples are described in the following numbered clauses:1. A transmitter circuit comprising: a first driver circuit configured to drive an input/output pad in an integrated circuit device, the first driver circuit comprising a thin-oxide transistor configured to couple the input/output pad to a first voltage rail when the transmitter circuit is operated in a first mode; a gate pullup transistor configured to couple a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level; and a switch configured to block transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.2. The transmitter circuit as described in clause 1, further comprising: a second driver circuit configured to couple the input/output pad to the first voltage rail when the transmitter circuit is operated in a second mode.3. The transmitter circuit as described clause 2, wherein the second driver circuit is disabled when the transmitter circuit is operated in the first mode, and wherein the first driver circuit is disabled when the transmitter circuit is operated in the second mode.4. The transmitter circuit as described in clause 2 or clause 3, wherein the first voltage rail delivers power at a first voltage level when the transmitter circuit is operated in the first mode, and wherein the first voltage rail delivers power at a second voltage level when the transmitter circuit is operated in the second mode.5. The transmitter circuit as described in clause 4, wherein the first voltage level has a magnitude that is greater than magnitude of the second voltage level.6. The transmitter circuit as described in any of clauses 1-5, wherein the first voltage rail and the second voltage rail have a same voltage level when the transmitter circuit is operated in the first mode, and wherein the first voltage rail and the second voltage rail have different voltage levels when the transmitter circuit is operated in the second mode.7. The transmitter circuit as described in any of clauses 1-6, wherein the switch comprises a transmission gate.8. The transmitter circuit as described in any of clauses 1-7, wherein the gating signal is provided by a circuit powered by the third voltage rail.9. An apparatus, comprising: means for driving an input/output pad provided in an integrated circuit device, including a thin-oxide transistor in a first driver circuit that is active when the apparatus is operated in a first mode and that is configured to couple the input/output pad to a first voltage rail when active; means for pulling a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level; and means for blocking transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.10. The apparatus as described in clause 9, wherein the means for driving an input/output pad further includes: a second driver circuit that is active when the apparatus is operated in a second mode and that is configured to couple the input/output pad to the first voltage rail when active.11. The apparatus as described in clause 10, wherein the second driver circuit is disabled when the apparatus is operated in the first mode, and wherein the first driver circuit is disabled when the apparatus is operated in the second mode.12. The apparatus as described in clause 10 or clause 11, wherein the first voltage rail delivers power at a first voltage level when the apparatus is operated in the first mode, and wherein the first voltage rail delivers power at a second voltage level when the apparatus is operated in the second mode.13. The apparatus as described in clause 12, wherein the first voltage level has a magnitude that is greater than magnitude of the second voltage level.14. The apparatus as described in any of clauses 9-13, wherein the first voltage rail and the second voltage rail have a same voltage level when the apparatus is operated in the first mode, and wherein the first voltage rail and the second voltage rail have different voltage levels when the apparatus is operated in the second mode.15. The apparatus as described in any of clauses 9-14, wherein the means for blocking transmission of the gating signal comprises a transmission gate.16. The apparatus as described in any of clauses 9-15, wherein the gating signal is provided by a circuit powered by the third voltage rail.17. A method for operating a transmitter circuit, comprising: configuring a first driver circuit to drive an input/output pad in an integrated circuit device when the transmitter circuit is operated in a first mode, the first driver circuit comprising a thin-oxide transistor configured to couple the input/output pad to a first voltage rail when the transmitter circuit is operated in a first mode; configuring a gate pullup transistor to couple a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level; and configuring a switch to block transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.18. The method as described in clause 17, further comprising: configuring a second driver circuit to couple the input/output pad to the first voltage rail when the transmitter circuit is operated in a second mode.19. The method as described in clause 18, wherein the second driver circuit is disabled when the transmitter circuit is operated in the first mode, and wherein the first driver circuit is disabled when the transmitter circuit is operated in the second mode.20. The method as described in clause 18 or clause 19, wherein the first voltage rail delivers power at a first voltage level when the transmitter circuit is operated in the first mode, and wherein the first voltage rail delivers power at a second voltage level when the transmitter circuit is operated in the second mode.21. The method as described in clause 20, wherein the first voltage level has a magnitude that is greater than magnitude of the second voltage level.22. The method as described in any of clauses 17-21, wherein the first voltage rail and the second voltage rail have a same voltage level when the transmitter circuit is operated in the first mode, and wherein the first voltage rail and the second voltage rail have different voltage levels when the transmitter circuit is operated in the second mode.23. The method as described in any of clauses 17-22, wherein the switch comprises a transmission gate.24. The method as described in any of clauses 17-23, wherein the gating signal is provided by a circuit powered by the third voltage rail.

As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

The present disclosure is provided to enable any person skilled in the art to make or use aspects of the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.