Patent ID: 12243741

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies.

Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

The advanced lithography process, method, and materials described in the current disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs can be processed according to the above disclosure.

When fabricating a circuit or packing a wafer, components need to be electrically connected. As demand for smaller electronic devices has increased, a need for smaller and more creative electrical connecting techniques of semiconductor structures has emerged. An example of such electrical connecting techniques is providing a conductive via disposed between and electrically connected to a first metal line and a second metal line over the first metal line.

In the present disclosure, a method of manufacturing a semiconductor structure is disclosed. In some embodiments, a semiconductor structure is manufactured by the method. In some embodiments, an interconnect structure is manufactured by the method. The method includes a number of operations and the description and illustrations are not deemed as a limitation of the sequence of the operations.

FIG.1illustrates a flowchart of a method100of manufacturing a semiconductor structure, in accordance with some embodiments. In some embodiments, as shown inFIG.1, the method100includes the following steps. Step101includes forming a first conductive line over a substrate. Step102includes forming a conductive member over the first conductive line. Step103includes forming a second conductive line over the first conductive line and the conductive member. Step104includes removing a portion of the conductive member exposed by the second conductive line to form a conductive via extending between the first conductive line and the second conductive line. The formation of the second conductive line is implemented prior to the formation of the conductive via.

FIG.2illustrates a flowchart of a method200of manufacturing a semiconductor structure, in accordance with some embodiments. Additional steps can be provided before, during, and after the steps shown inFIGS.1and2, and some of the steps described below can be replaced or eliminated in other embodiments of the method100and the method200. The order of the steps may be interchangeable.FIGS.3to14are schematic perspective views illustrating exemplary operations for the methods of manufacturing a semiconductor structure, such as the operations illustrated inFIGS.1and2, according to one embodiment of the present disclosure.

Referring toFIGS.2and3, in some embodiments, the method200includes step201, which includes providing a substrate301. The substrate301may be processed according to applicable manufacturing processes to form integrated circuits in the substrate301. In some embodiments, the substrate301is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate301may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate301includes silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. In an embodiment, the substrate301is a silicon wafer.

Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the substrate301and may be interconnected by metal layers formed by, for example, metallization patterns in one or more dielectric layers on the substrate301to form an interconnect structure.

Referring toFIGS.2and4, the method200includes step202, which includes disposing a first dielectric layer302over the substrate301. In some embodiments, the first dielectric layer302is an inter-metal dielectric (IMD).

In some embodiments, the dielectric layer302includes low-k dielectric material. The dielectric constant (k value) of the low-k dielectric material may be less than 3.0, or less than about 2.5, and the dielectric material is therefore also referred to as an extreme low-k (ELK) dielectric material. In some embodiments, the dielectric layer302includes a polymer, such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), ajinomoto buildup film (ABF), solder resist film (SR), or the like. In some embodiments, the dielectric layer302is a single layer or multiple layers stacked over each other. In some embodiments, the dielectric layer302includes a plurality of dielectric sub-layers disposed over the substrate301. In some embodiments, the materials included in the dielectric sub-layers are the same material or different materials. In some embodiments, the dielectric layer302is formed by suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like.

Referring toFIGS.2and5, the method200includes step203, which includes forming a first conductive line311and a conductive member321within the first dielectric layer302, wherein a top surface3021of the first dielectric layer302is coplanar with a top surface3211of the conductive member321. The respective process is illustrated as step101and step102in the method100as shown inFIG.1.

In some embodiments, the top surface3211of the conductive member321is exposed through the first dielectric layer302. In some embodiments, in step203, a stack307including the first conductive line311and the conductive member321over the first conductive line311is formed. In some embodiments, the conductive member321is disposed over the first conductive line311, and the first dielectric layer302surrounds the first conductive line311and the conductive member321. In some embodiments, the conductive member321overlaps and is parallel to the first conductive line311. In some embodiments, a width W2of the conductive member321is substantially equal to a width W1of the first conductive line311. In some embodiments, the first conductive line311and the conductive member321extend along a first direction X.

Each of the first conductive line311and the conductive member321may include conductive material such as aluminum or aluminum copper alloy. The first conductive line311is electrically coupled to the conductive member321. In some embodiments, the first conductive line311is electrically coupled to respective circuits of the substrate301. In some embodiments, the first conductive line311is formed on an active side of the substrate301. A shape of the first conductive line311from a top view perspective is not particularly limited, and may be, for example, a strip, an arc shape, or the like, and may be adjusted according to the actual needs. In some embodiments, a plurality of the first conductive lines311are formed over the substrate301.

Referring toFIG.6, the method200further includes disposing a multi-layer etching mask341over the first dielectric layer302and the conductive member321. The multi-layer etching mask341is formed over first dielectric layer302and the stack307. In some embodiments, the multi-layer etching mask341is a hard mask. The multi-layer etching mask341may be formed of a metallic material, such as titanium nitride, titanium, tantalum nitride, or tantalum. The multi-layer etching mask341may be formed of metal-doped carbide (e.g., tungsten carbide) or a metalloid (e.g., silicon nitride, boron nitride or silicon carbide). The multi-layer etching mask341may be formed using CVD, PVD, atomic layer deposition (ALD), or the like. In some embodiments, the multi-layer etching mask341is initially patterned and then the conductive member321is etched with the multi-layer etching mask341as an etching mask. The pattern of the multi-layer etching mask341is transferred to the conductive member321accordingly.

In some embodiments, the multi-layer etching mask341may include a lower layer342and an upper layer343. The lower layer342may include a cross-linked photoresist or a hard mask. The upper layer343may include a photoresist, which is exposed and developed to define an overlap area (not shown). In some embodiments, the multi-layer etching mask341further includes a middle layer (not shown) disposed between the lower layer342and the upper layer343and including an inorganic material such as silicon oxynitride or the like.

Referring toFIGS.2and7, the method200includes step204, which includes determining an overlap area344of the first conductive line311and a second conductive line (not shown) before formation of the second conductive line (not shown). The overlap area344overlaps the first conductive line311. A width W3of the overlap area344is greater than a width of the subsequently-formed second conductive line. In some embodiments, the width W3of the overlap area344is greater than the width W2of the conductive member321. In some embodiments, a plurality of overlap areas344overlap the first conductive line311.

In some embodiments, the method200further includes patterning the upper layer343, and the remaining portion of the upper layer343defines the overlap area344. In some embodiments, a portion of the lower layer342is exposed after patterning the upper layer343. In some embodiments, the upper layer343is patterned by an etchant. In some embodiments, the upper layer343and the middle layer are patterned. In some embodiments, the method200further includes lithography process.

Referring toFIGS.2and8, the method200further includes patterning the lower layer342, and a remaining portion of the lower layer342defines the overlap area344. In some embodiments, the lower layer342is patterned by an etchant. In some embodiments, a portion of the conductive member321disposed outside of the overlap area344is exposed. In some embodiments, the remaining portions of the lower layer342are then used to pattern the underlying conductive member321.

In some embodiments, referring toFIGS.2and9, the method200includes step205, which includes removing a portion of the conductive member321from outside of the overlap area344. In some embodiments, the remaining conductive member321is disposed in the overlap area344. In some embodiments, a portion of the first conductive line311disposed outside of the overlap area344is exposed.

In some embodiments, referring toFIG.10, the method200includes disposing a dielectric layer304over the first conductive line311. In some embodiments, the dielectric layer304is disposed outside of the overlap area344. In some embodiments, the dielectric layer304is disposed adjacent to the remaining conductive member321, and the top surface3021of the first dielectric layer302is coplanar with a top surface of the dielectric layer304. In some embodiments, the dielectric layer304includes a low-k dielectric material. In some embodiments, a material included in the dielectric layer304and a material included in the first dielectric layer302are a same material or different materials.

In some embodiments, referring toFIGS.2and11, the method200includes step206, which includes forming the second conductive line331over the first conductive line311, the conductive member321and the first dielectric layer302, wherein a portion of the second conductive line331is disposed in the overlap area344. The respective process is illustrated as step103in the method100as shown inFIG.1. In some embodiments, a portion of the conductive member321is exposed through the second conductive line331. In some embodiments, the second conductive line331is separated from the dielectric layer304. In some embodiments, a portion of the second conductive line331is disposed over the dielectric layer304.

The second conductive line331extends along a second direction Y different from the first direction X. In some embodiments, the first direction X and the second direction Y are not orthogonal to each other from a top view perspective. In some embodiments, the first conductive line311and the second conductive line331are not orthogonal to each other. In some embodiments, the first conductive line311and the second conductive line331are orthogonal to each other.

In some embodiments, a mask345is disposed over the second conductive line331. In some embodiments, the mask345is a hard mask. In some embodiments, the mask345overlaps and is parallel to the second conductive line331. The mask345may be formed by CVD, PVD, atomic layer deposition (ALD), or the like. In some embodiments, the mask345is disposed over a conductive layer (not shown) over the remaining conductive member321and the first dielectric layer302, the mask345is initially patterned, and the conductive layer (not shown) is etched with the mask345as an etching mask. The pattern of the multi-layer etching mask341is transferred to the conductive member321accordingly.

In some embodiments, referring toFIGS.2and12, the method200includes step207, which includes removing a portion of the conductive member321exposed by the second conductive line331to form a conductive via322extending between the first conductive line311and the second conductive line331. The respective process is illustrated as step104in the method100as shown inFIG.1. The formation of the second conductive line331is implemented prior to the formation of the conductive via322. The portion of the conductive member321is removed after the formation of the second conductive line331. In some embodiments, a portion312of the first conductive line311is exposed by the conductive via322. In some embodiments, the portion312surrounds the conductive via322from a top view perspective. In some embodiments, the conductive via322is isolated from the first dielectric layer302. In some embodiments, the conductive via322is in contact with the first dielectric layer302.

In some embodiments, the conductive via322is disposed in the overlap area344, and the second conductive line331is disposed over the conductive via322. In some embodiments, the conductive via322is electrically connected to the first conductive line311and the second conductive line331.

In some embodiments, referring toFIG.13, the method200further includes removing the mask345, and a top surface3311of the second conductive line331is exposed. In some embodiments, the conductive via322, the first conductive line311and the second conductive line331form an interconnect structure306of a semiconductor structure300. In some embodiments, the conductive via322, the first conductive line311and the second conductive line331can be referred to as a dual damascene structure.

In some embodiments, referring toFIGS.2and14, the method200includes step208, which includes disposing a second dielectric layer305to surround the second conductive line331and the conductive via322. In some embodiments, the second dielectric layer305is in contact with the exposed portion312of the first conductive line311. In some embodiments, a top surface of the second dielectric layer305is coplanar with the top surface3311of the second conductive line331. In some embodiments, the top surface3311of the second conductive line331is exposed through the second dielectric layer305. In some embodiments, the second dielectric layer305and the dielectric layer304are integral. In some embodiments, a material included in the second dielectric layer305and a material included in the first dielectric layer302are a same material or different materials. In some embodiments, the second dielectric layer305is formed by suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. In some embodiments, the second dielectric layer305is a single layer or multiple layers stacked over each other.

FIG.15is a perspective view of an interconnect structure of a semiconductor structure in accordance with some embodiments of the present disclosure.FIG.16is an exploded view of an interconnect structure of a semiconductor structure in accordance with some embodiments of the present disclosure. Referring toFIGS.15and16, the interconnect structure306of the semiconductor structure300includes the first conductive line311, the second conductive line331, and the conductive via322electrically connecting the first conductive line311to the second conductive line331. The first conductive line311extends along the first direction X and has a first surface313. The second conductive line331extends along the second direction Y different from the first direction X, disposed above the first conductive line311, and has a second surface332overlapping the first surface313from a top view perspective. The conductive via322extends between the first surface313and the second surface332. The conductive via322includes a first end323disposed within the first surface313, a second end324disposed within second surface332, and a cross-section325disposed between the first end323and the second end324. In some embodiments, at least two of interior angles of the cross-section325are substantially unequal to 90°.

In some embodiments, the first surface313overlaps and is conformal to the second surface332from a top view perspective. A size and a shape of the first surface313are same as those of the second surface332. In some embodiments, the first surface313is a quadrilateral. In some embodiments, the first surface313is a parallelogram.

In some embodiments, the first surface313is in contact with the first end323, and the second surface332is in contact with the second end324. In some embodiments, the cross-section325of the conductive via322is a convex polygon, a parallelogram, a trapezoid, an oval, a round shape, or a stadium shape. In some embodiments, the convex polygon includes a triangle, a quadrilateral, a pentagon, a hexagon, a heptagon, or an octagon.

In some embodiments, an area of the first surface313of the first conductive layer311is greater than an area of the first end323of the conductive via322. In some embodiments, an area of the second surface332of the second conductive layer331is greater than an area of the second end324of the conductive via322. In some embodiments, the cross-section325of the conductive via322is inwardly offset from the first surface313and/or the second surface332from a top view perspective.

In some embodiments, an area of a first interface326between the first end323and the first conductive line311is substantially equal to an area of the cross-section325. In some embodiments, the cross-section325overlaps the first interface326from a top view perspective. In some embodiments, the area of the first interface326is smaller than the area of the cross-section325. In some embodiments, the area of the first interface326is less than an area of the first surface313. In some embodiments, the first interface326is positioned within the first surface313from a top view perspective. In some embodiments, the first interface326is a convex polygon, a parallelogram, a trapezoid, an oval, a round shape, or a stadium shape. In some embodiments, the convex polygon includes a triangle, a quadrilateral, a pentagon, a hexagon, a heptagon, or an octagon.

In some embodiments, an area of a second interface327between the second end324and the second conductive line331is substantially equal to the area of the cross-section325from a top view perspective. In some embodiments, the cross-section325is overlapped by the second interface327from a top view perspective. In some embodiments, the area of the second interface327is less than the area of the cross-section325. In some embodiments, the area of the second interface327is less than the area of the second surface332. In some embodiments, the second interface327is positioned within the second surface332from a top view perspective. In some embodiments, the area of the cross-section325is greater than the area of the second interface327. In some embodiments, the second interface327is a convex polygon, a parallelogram, a trapezoid, an oval, a round shape, or a stadium shape. In some embodiments, the convex polygon includes a triangle, a quadrilateral, a pentagon, a hexagon, a heptagon, or an octagon.

FIGS.17to23are top views of an interconnect structure of a semiconductor structure in accordance with some embodiments of the present disclosure. Referring toFIG.17, in some embodiments, a cross-section325of a conductive via322is positioned to overlap an area within a first surface313or a second surface332from a top view perspective by a predetermined inset distance D1. In some embodiments, the predetermined inset distance D1is greater than 0 and less than a quarter of the width W1of the first conductive line311. In some embodiments, the predetermined inset distance D1is greater than 0 and less than a quarter of a width W4of the second conductive line331. In some embodiments, the cross-section325of the conductive via322is a stadium shape.

Referring toFIG.18, in some embodiments, the cross-section325of the conductive via322includes a first pair of sides328extending along a first direction X and a second pair of sides329extending along a second direction Y. In some embodiments, a shortest distance D2between the first pair of sides328and edges of the first surface313is predetermined. In some embodiments, a shortest distance D3between the second pair of sides329and edges of the second surface332is predetermined. In some embodiments, the cross-section325of the conductive via322includes a fillet or a chamfer adjacent to a corner of the cross-section325. In some embodiments, the distance D2is greater than 0 and less than a quarter of the width W1of the first conductive line311. In some embodiments, the distance D3is greater than 0 and less than a quarter of the width W4of the second conductive line331. The distance D2may be same as or different from the distance D3. In some embodiments, at least two of interior angles α of the cross-section325are substantially unequal to 90°. In some embodiments, all of interior angles α of the cross-section325are substantially unequal to 90°.

Referring toFIG.19, in some embodiments, the cross-section325of the conductive via322is substantially aligned with the first surface313or the second surface332from a top view perspective. In some embodiments, a size and a shape of the cross-section325of the conductive via322are same as a size and a shape of the first surface313. In some embodiments, the size and the shape of the cross-section325of the conductive via322are same as a size and a shape of the second surface332. In some embodiments, the cross-section325of the conductive via322includes the first pair of sides328extending along the first direction X and aligned with edges of a first conductive line311. In some embodiments, the cross-section325of the conductive via322includes the second pair of sides329extending along the second direction Y and aligned with edges of a second conductive line331. In some embodiments, the distance D2is equal to 0. In some embodiments, the distance D3is equal to 0.

Referring toFIG.20, in some embodiments, a width W1of the first conductive line311is different from a width W4of the second conductive line331. In some embodiments, a plurality of conductive vias322are disposed between the first conductive line311and the second conductive line331.

Referring toFIG.21, in some embodiments, the first direction X is orthogonal to the second direction Y. In some embodiments, the cross-section325of the conductive via322is a stadium shape.

Referring toFIG.22, in some embodiments, the cross-section325of the conductive via322is an oval. In some embodiments, when the width W1of the first conductive line311is different from the width W4of the second conductive line331, the cross-section325may be an oval.

Referring toFIG.23, in some embodiments, the cross-section325of the conductive via322is a pentagon. In some embodiments, the cross-section325of the conductive via322is a regular pentagon.

FIG.24illustrates a flowchart of a method400of manufacturing a semiconductor structure, in accordance with some embodiments. In some embodiments, as shown inFIG.21, the method400includes the following steps. Step401includes forming a stack including a first conductive layer and a conductive member over the first conductive layer. Step402includes patterning the first conductive layer and the conductive member to form a first conductive line and align the first conductive line with the conductive member from a top view perspective. Step403includes patterning the conductive member to form a conductive via over the first conductive layer.

FIG.25illustrates a flowchart of a method500of manufacturing a semiconductor structure, in accordance with some embodiments. Additional steps can be provided before, during, and after the steps shown inFIGS.24and25, and some of the steps described below can be replaced or eliminated in other embodiments of the method400and the method500. The order of the steps may be interchangeable.FIGS.26to34are schematic views illustrating exemplary operations for the method of manufacturing a semiconductor structure, such as the operations illustrated inFIGS.24and25, according to one embodiment of the present disclosure. In some embodiments, the methods400and500are configured to form the interconnect structure306as illustrated inFIGS.15and34.

Referring toFIGS.25and26, in some embodiments, the method500includes step501, which includes forming a stack307including a first conductive layer314and a conductive member321over the first conductive layer314. The respective process is illustrated as step401in the method400as shown inFIG.24.

In some embodiments, the method500includes step502, which includes forming a mask351over the conductive member321. Referring toFIGS.25and27, the mask351is formed over the stack307. In some embodiments, the mask351is a hard mask. In some embodiments, the mask351is a strip extending along the first direction X from a top view perspective. The mask351may be formed by CVD, PVD, atomic layer deposition (ALD), or the like.

In some embodiments, the method500includes step503, which includes patterning the first conductive layer314and the conductive member321to form a first conductive line311and to align the first conductive line311with the conductive member321from a top view perspective. The respective process is illustrated as step402in the method400as shown inFIG.24. In some embodiments, the pattern of the mask351is transferred to the conductive member321and the first conductive layer314sequentially. Referring toFIGS.25and28, a portion of the conductive member321is removed, and a remaining conductive member321is aligned with the mask351from a top view perspective. In some embodiments, the remaining conductive member321is a strip extending along a first direction X from a top view perspective. In some embodiments, a portion of the first conductive layer314is exposed through the remaining conductive member321.

Referring toFIGS.25and29, a portion of the first conductive layer314is removed, and the first conductive line311is formed. In some embodiments, the thus formed first conductive line311is disposed under the remaining conductive member321. The mask351, the remaining conductive member321and the first conductive line311are stacked and aligned with each other from a top view perspective. In some embodiments, the stack307includes the first conductive line311and the conductive member321. In some embodiments, the stack307extends along the first direction X.

In some embodiments, a width W1of the first conductive line311equals a width W2of the conductive member321. In some embodiments, the first conductive layer314and the conductive member321are patterned simultaneously.

In some embodiments, referring toFIG.30, the mask351is removed. In some embodiments, a top surface3211of the conductive member321is exposed.

In some embodiments, the method500includes step504, which includes patterning the conductive member321to form a conductive via322over the first conductive layer311. The respective process is illustrated as step403in the method400as shown inFIG.24. Referring toFIGS.25and31, in some embodiments, a mask352is disposed over the top surface3211of the conductive member321. In some embodiments, the mask352is a hard mask. The mask352may be formed by CVD, PVD, atomic layer deposition (ALD), or the like.

The mask352covers a portion of the conductive member321. In some embodiments, a position, a shape and a size of the mask352are determined according to a predetermined position, a predetermined shape and a predetermined size of the subsequently-formed conductive via322. In some embodiments, a width W5of the mask352is greater than or equal to the width W2of the conductive member321. In some embodiments, the width W5of the mask352is greater than or equal to the width W1of the first conductive line311. In some embodiments, a dielectric layer (not shown) surrounds the first conductive line311and the conductive member321.

Referring toFIG.32, a portion of the conductive member321is removed, and the conductive via322is formed over the first conductive line311. In some embodiments, a portion of the first conductive line311is exposed through the conductive via322from a top view perspective. In some embodiments, a width W6of the conductive via322is equal to or less than the width W1of the first conductive line311. In some embodiments, the width W6of the conductive via322is equal to or less than the width W5of the mask352. Referring toFIG.33, the mask352is removed, and a second end324of the conductive via322is exposed.

In some embodiments, the method500includes step505, which includes forming a second conductive line331over the conductive via322. Referring toFIG.34, in some embodiments, the second conductive line331extends along a second direction Y different from the first direction X. In some embodiments, the first conductive line311, the conductive via322and the second conductive line331are electrically connected to each other and form an interconnected structure306. In some embodiments, a dielectric layer (not shown) surrounds the interconnected structure306.

FIG.35is a top view of an interconnect structure in accordance with a first comparative embodiment. As shown inFIG.35, in the first comparative embodiment, an interconnect structure610includes first conductive lines6111and6112, second conductive lines6131and6132disposed over the first conductive lines6111and6112, and conductive vias6121,6122,6123and6124between the first conductive lines6111and6112and the second conductive lines6131and6132. The first conductive lines6111and6112and the second conductive lines6131and6132have four overlap areas611,612,613and614. Each of the overlap areas611,612,613and614is provided with a conductive via6121,6122,6123or6124respectively disposed therein. The first conductive lines6111and6112extend along a first direction X and the second conductive lines6131and6132extend along a third direction Z perpendicular to the first direction X.

In the first comparative embodiment, each of the conductive vias6121,6122,6123and6124is a square or a rectangle from a top view perspective, and interior angles of the conductive vias6121,6122,6123and6124from a top view perspective are equal to 90°. In the first comparative embodiment, the conductive vias6121,6122,6123and6124are arranged in a quadrilateral from a top view perspective, the conductive via6121and the conductive via6124are disposed on opposite corners of the quadrilateral, and the conductive via6122is disposed adjacent to the conductive via6121.

FIGS.36and37are top views of an interconnect structure of a semiconductor structure in accordance with some embodiments of the present disclosure. Referring toFIG.36, in some embodiments, an interconnect structure306includes first conductive lines3111and3112, second conductive lines3311and3312disposed over the first conductive lines3111and3112, and conductive vias3221,3222,3223and3224between the first conductive lines3111and3112and the second conductive lines3311and3312. The first conductive lines3111and3112and the second conductive lines3311and3312include four overlap areas3091,3092,3093and3094. Each of the overlap areas3091,3092,3093and3094is provided with one of the conductive vias3221,3222,3223and3224disposed therein. The first conductive lines3111and3112extend along a first direction X and the second conductive lines3311and3312extend along a second direction Y different from the first direction X.

In some embodiments, the conductive vias3221,3222,3223and3224are arranged in a quadrilateral from a top view perspective, and the conductive via3221and the conductive via3224are disposed on opposite corners of the quadrilateral. In some embodiments, each of the conductive vias3221,3222,3223and3224includes at least two interior angles substantially unequal to 90° from a top view perspective. In some embodiments, each of the conductive vias3221,3222,3223and3224has a cross-section, and the cross-section is octagonal.

Comparing the embodiment illustrated inFIG.36to the first comparative embodiment illustrated inFIG.35, it can be seen that when a distance D32between the conductive via3221and the conductive via3224is equal to a distance D62between the conductive via6121and the conductive via6124, a distance D31between the adjacent first conductive lines3111and3112is less than a distance D61between the adjacent first conductive lines6111and6112. As such, according to the adjustment of the cross-section of the conductive vias3221and3224, the distance D31between the adjacent first conductive vias3111and3112is reduced, and a density of the first conductive lines3111and3112is increased. Further, when the distance D31is equal to the distance D61, the distance D32is greater than the distance D62.

In addition, still comparing the embodiment illustrated inFIG.36to the first comparative embodiment inFIG.35, it can further be seen that when the distance D32is equal to the distance D62, a distance D33between the adjacent second conductive lines3311and3312is less than a distance D63between the adjacent second conductive line6131and6132. As such, according to the adjustment of the cross-section of the conductive vias3221and3224, the distance D33between the adjacent second conductive lines3311and3312is reduced, and a density of the second conductive lines3311and3312is increased. Further, when the distance D33is equal to the distance D63, the distance D32is greater than the distance D62.

Referring toFIG.37, in some embodiments, an interconnect structure306includes first conductive lines3111and3112, a second conductive line3311disposed over the first conductive lines3111and3112, and conductive vias3221and3222between the first conductive lines3111and3112and the second conductive line3311. The first conductive lines3111and3112and the second conductive line3311include two overlap areas3091and3092. Each overlap area3091and3092is provided with a conductive via3221and3222disposed therein. The first conductive lines3111and3112extend along a first direction X and the second conductive line3311extends along a second direction Y different from the first direction X.

In some embodiments, the conductive via3221is adjacent to the conductive via3222from a top view perspective. In some embodiments, each of the conductive vias3221and3222has a cross-section, and the cross-section is triangle. In some embodiments, hypotenuses of the triangles face toward each other.

Comparing the embodiment illustrated inFIG.37to the first comparative embodiment inFIG.35, when a distance D34between the hypotenuse of the conductive via3221and the hypotenuse of the conductive via3222is equal to a distance D64between the conductive via6121and the conductive via6122, the distance D31is less than the distance D61. As such, according to the adjustment of the cross-section of the conductive vias3221and3222, the distance D31between the adjacent first conductive vias3111and3112is reduced, and a density of the first conductive lines3111and3112is increased. Further, when the distance D31is equal to the distance D61, the distance D34is greater than the distance D64between the conductive via6121and the conductive via6122.

In accordance with some embodiments of the disclosure, a method of manufacturing a semiconductor structure includes forming a first conductive line over a substrate; forming a conductive member over the first conductive line; and forming a second conductive line over the first conductive line and the conductive member. The method further includes removing a portion of the conductive member exposed by the second conductive line to form a conductive via extending between the first conductive line and the second conductive line, wherein the formation of the second conductive line is implemented prior to the formation of the conductive via.

In accordance with some embodiments of the disclosure, a method of manufacturing a semiconductor structure includes forming a stack including a first conductive layer and a conductive member over the first conductive layer; patterning the first conductive layer and the conductive member to form a first conductive line and to align the first conductive line with the conductive member from a top view perspective; and patterning the conductive member to form a conductive via over the first conductive layer.

In accordance with some embodiments of the disclosure, a semiconductor structure includes a first conductive line extending along a first direction and having a first surface; a second conductive line extending along a second direction different from the first direction, disposed above the first conductive line, and having a second surface overlapping the first surface; and a conductive via extending between and electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section disposed between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.