Patent ID: 12255665

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. The adjustment circuit is configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value.

Hereinafter, embodiments will be described with reference to the drawings.

Note that in the following description, components having substantially the same functions and configurations are denoted by the same reference signs. In a case where elements having similar configurations are particularly distinguished from each other, different characters or numbers may be added to the end of the same reference sign.

1. Configuration

A configuration according to an embodiment will be described.

1.1 Information Processing System

First, a configuration of an information processing system including a receiver device according to the embodiment will be described.FIG.1is a block diagram illustrating an example of the configuration of the information processing system including the receiver device according to the embodiment.

The information processing system1is a system that transmits information by serial communication. The information processing system1includes a host device2and a memory system3. The memory system3is configured to be connected to the host device2via a host bus BUS.

The host device2is an information processing apparatus outside the memory system3. The host device2is, for example, a personal computer or a server installed in a data center. The host device2transmits various requests to the memory system3. When transmitting a request to the memory system3, the host device2functions as a transmitter device.

The memory system3is a storage device. The memory system3is, for example, a universal flash storage (UFS) device, a solid state drive (SSD), or a memory card such as an SD™ card. The memory system3executes a write operation, a read operation, and an erase operation of data in response to a request from the host device2. When receiving a request from the host device2, the memory system3functions as a receiver device.

1.2 Memory System

An internal configuration of the memory system according to the first embodiment will be described.

The memory system3includes a memory device4and a memory controller5.

The memory device4is, for example, a nonvolatile memory. The memory device4is, for example, a NAND flash memory. The memory device4stores data in a nonvolatile manner.

The memory controller5includes, for example, an integrated circuit such as a system-on-a-chip (SoC). The memory controller5controls the memory device4based on a request from the host device2. Specifically, for example, the memory controller5writes write data to the memory device4based on a write request from the host device2. Further, the memory controller5reads read data from the memory device4based on a read request from the host device2. Then, the memory controller5transmits the read data to the host device2.

Next, an internal configuration of the memory controller5will be described. The memory controller5includes a control unit6, a buffer memory7, a host interface circuit (host I/F)8, and a memory interface circuit (memory I/F)9. A function of the memory controller5described below can be realized by either a hardware configuration or a combination configuration of hardware resources and firmware.

The control unit6is a circuit that controls the entire memory controller5. The control unit6includes, for example, a processor such as a central processing unit (CPU), and a read only memory (ROM).

The buffer memory7is, for example, a static random access memory (SRAM). The buffer memory7buffers data transmitted between the host device2and the memory device4. The buffer memory7temporarily stores the write data and the read data.

The host interface circuit8is a semiconductor integrated circuit. The host interface circuit8manages communication between the memory controller5and the host device2. When receiving a request from the host device2, some circuits of the host interface circuit8function as a receiver circuit. The host interface circuit8is connected to the host device2via the host bus BUS. The host bus BUS conforms to, for example, a peripheral component interconnect express (PCIe™), a mobile industry processor interface (MIPI), a serial attached (small computer system interface (SCSI) SAS), a serial (advanced technology attachment (ATA) SATA), or an SD™ interface.

The memory interface circuit9is a semiconductor integrated circuit. The memory interface circuit9manages communication between the memory device4and the memory controller5. The memory interface circuit9is connected to the memory device4via a memory bus. The memory bus conforms to, for example, a single data rate (SDR) interface, a toggle double data rate (DDR) interface, or an open NAND flash interface (ONFI).

1.3 Host Interface Circuit (Receiver Circuit)

Next, an internal configuration of a part corresponding to the receiver circuit included in the host interface circuit according to the embodiment will be described.FIG.2is a block diagram illustrating an example of a configuration of the receiver circuit of the receiver device according to the embodiment;

The host interface circuit8includes pads P1and P2, an analog processing circuit10, a TI-ADC20, a digital processing circuit30, and a CDR40.

Each of the pads P1and P2is a terminal connected to the host bus BUS. In the example ofFIG.2, a case where the pads P1and P2receive signals S0and /S0, respectively, from the host device2via the host bus BUS is illustrated.

The signals S0and /S0are differential signals. Before passing through the host bus BUS, the signals S0and /S0are, for example, pulse signals. Data from the host device2is modulated to each pulse of the signals S0and /S0. A voltage level of each pulse of the signals S0and /S0corresponds to data of one or more bits. In the following description, it is assumed that 2-bit data is modulated for one pulse. Such a data transmission scheme is also referred to as a four-level pulse amplitude modulation (PAM4).

By passing through the host bus BUS, the signals S0and /S0receive a loss due to transmission characteristics (for example, frequency characteristics) of the host bus BUS. As a result, inter-symbol interference (ISI) occurs in the signals S0and /S0that have passed through the host bus BUS. Therefore, the signals S0and /S0that have passed through the host bus BUS are processed as analog signals.

The analog processing circuit10is an analog front end (AFE). The analog processing circuit10includes, for example, a continuous time linear equalizer (CTLE) and a variable gain amplifier (VGA). The CTLE is an amplifier circuit having frequency characteristics that compensate for frequency characteristics of the host bus BUS. The VGA is an amplifier circuit capable of changing a gain. The signals S0and /S0are input to the analog processing circuit10from the pads P1and P2, respectively. The analog processing circuit10executes analog processing on the signals S0and /S0using the CTLE and the VGA. The analog processing circuit10generates signals S1and /S1based on the signals S0and /S0. The analog processing circuit10outputs the signals S1and /S1to the TI-ADC20.

The TI-ADC20is a time-interleaved AD converter. The signals S1and /S1are input from the analog processing circuit10to the TI-ADC20, and a signal CLK is input from the CDR40to the TI-ADC20. The TI-ADC20converts the signals S1and /S1into a signal X0based on the signal CLK. The TI-ADC20outputs the signal X0to the digital processing circuit30.

The signal CLK includes n clock signals. n is an integer of 1 or more (for example, 32). The n clock signals of the signal CLK have phases different by, for example, at least 360°/n. Hereinafter, the n clock signals in the signal CLK may be distinguished and shown as signals CLK_1, . . . , and CLK_n. A frequency of the signal CLK may be equal to a frequency of a clock signal embedded in the signals S0and /S0by the host device2. The frequency of the signal CLK may be different from the frequency of the clock signal embedded in the signals S0and /S0by the host device2.

The signal X0is a digital signal. The signal X0includes a plurality of consecutive digital values. A value of a bit of one digital value included in the signal X0is sampled from one symbol of the signals S1and /S1based on one clock signal of the signal CLK. The one digital value is, for example, 7-bit data. A value of each bit of the n consecutive digital values included in the signal X0is sampled from n consecutive symbols of the signals S1and /S1based on the n clock signals of the signal CLK. Hereinafter, a conversion cycle of the n consecutive digital values included in the signal X0by the TI-ADC20is also simply referred to as a “cycle”. Further, the n consecutive digital values included in the signal X0are also referred to as “signals X0for one cycle”. Furthermore, the n consecutive digital values included in the signal X0may be distinguished and shown as values X0_1, . . . , and X0_n.

The digital processing circuit30includes, for example, a feed forward equalizer (FFE), a decision feedback equalizer (DFE), and a data comparator. The configuration of the digital processing circuit30will be described later. The signal X0is input to the digital processing circuit30. The digital processing circuit30executes digital processing on the signal X0using the FFE, the DFE, and the data comparator. Specifically, the digital processing circuit30generates signals X1and Xf and data A1and Af based on the signal. X0. The digital processing circuit30outputs the signal X1and the data A1to the CDR40. The digital processing circuit30outputs the signal Xf and the data Af to a subsequent circuit (not illustrated). Details of generation of the signals X1and Xf and the data A1and Af will be described later.

The CDR40is a clock data recovery circuit. The signal X1and the data A1are input to the CDR40at every cycle. The CDR40calculates a correction amount of a phase of the signal CLK based on the signal X1and the data A1. The CDR40recovers the signal CLK based on the calculated correction amount of the phase. The CDR40outputs the recovered signal CLK to the TI-ADC20at every cycle. In this manner, the CDR40recovers the signal CLK serving as a reference of the sampling timing of the subsequent signal X0of one cycle based on the signal X1and the data A1generated from the signal X0of one cycle. Such cyclical processing for each cycle by the TI-ADC20, the digital processing circuit30, and the CDR40is also referred to as a “CDR loop”.

1.4 AD Converter

Next, an internal configuration of the AD converter (TI-ADC) of the receiver circuit according to the embodiment will be described.FIG.3is a block diagram illustrating an example of the configuration of the AD converter of the receiver circuit according to the embodiment.

The TI-ADC20includes a plurality of ADCs21. The plurality of ADCs21includes n ADCs21-1,21-2,21-3, . . . ,21-n. Each of the n ADCs21-1to21-nis an AD converter that converts an analog signal into a digital signal.

The signals S1and /S1are commonly input to the n ADCs21-1to21-n. Further, the signals CLK_1to CLK_n are input to the n ADCs21-1to21-n, respectively. The n ADCs21-1to21-nsample the signals S1and /S1and convert the sampled analog signals S1and /S1to the values X0_1to X0_nbased on the signals CLK_1to CLK_n, respectively. In this manner, the n consecutive digital values X0_1to X0_nincluded in the signal X0are sampled by the different ADCs21-1to21-n, respectively.

The n ADCs21-1to21-nmay have different conversion characteristics, respectively. Specifically, for example, a minute deviation may occur in the sample timing of the signal CLK in each of the n ADCs21-1to21-n. The minute deviation of the sample timing is also referred to as skew. Further, for example, a minute deviation may occur in gains of the values X0_1to X0_noutput from the n ADCs21-1to21-n, respectively. This minute deviation of the gains is also referred to as a gain mismatch.

Therefore, in the subsequent digital processing circuit30and the CDR40, adjustment of a difference in gain occurring in the values X0_1to X0_nand adjustment of the phase of the signal CLK for correcting skew occurring in the TI-ADC20are executed.

1.5 Digital Processing Circuit

Next, an internal configuration of the digital processing circuit of the receiver circuit according to the embodiment will be described.FIG.4is a block diagram illustrating an example of the configuration of the digital processing circuit of the receiver circuit according to the embodiment.

The digital processing circuit30includes a gain calibration circuit31, a gain adaptation circuit32, a skew adaptation circuit33, an FFE34, a data comparator35, an FFE36, a DFE37, and a data comparator38.

The signal X0is input to the gain calibration circuit31. The gain calibration circuit31executes gain calibration processing for every n digital values included in the signal X0for one cycle. A gain calibration code Cg input from the gain adaptation circuit32is used for the gain calibration processing by the gain calibration circuit31. The gain calibration code Cg is a set of n digital values (codes) corresponding to the n digital values included in the signal X0for one cycle. As a result of the gain calibration processing, the gain calibration circuit31generates a signal X0′ in which a gain of the signal X0is adjusted according to the gain calibration code Cg. That is, the signal X0′ is a digital signal similarly to the signal X0. The signal X0′ for one cycle is a set of n digital values. For example, in a case where the gain calibration code Cg is positive, the gain calibration circuit31generates the signal X0′ such that the gain decreases. Further, for example, in a case where the gain calibration code Cg is negative, the gain calibration circuit31generates the signal X0′ so that the gain increases. The gain calibration circuit31outputs the signal X0′ to the gain adaptation circuit32and the skew adaptation circuit33. The signal X0′ is further output to the FFE34.

The signal X0′ is input to the gain adaptation circuit32. The gain adaptation circuit32generates the gain calibration code Cg based on the n digital values included in the signal X0′ for one cycle. The gain calibration code Cg generated by the gain adaptation circuit32is output to the gain calibration circuit31.

Note that the gain adaptation circuit32updates the gain calibration code Cg by, for example, two types of gain update processing.

In the first type of gain update processing, the gain adaptation circuit32regards one digital value among the n digital values included in the signal X0′ for one cycle as a reference value. Then, the gain adaptation circuit32updates (n−1) codes excluding one code corresponding to the reference value among the n codes included in the gain calibration code Cg. At this time, the gain adaptation circuit32does not update the one code corresponding to the reference value among the n codes included in the gain calibration code Cg.

In the second type of gain update processing, the gain adaptation circuit32first updates the (n−1) codes excluding the one code corresponding to the reference value among the n codes included in the gain calibration code Cg. Then, the gain adaptation circuit32further updates the one code corresponding to the reference value based on the updated (n−1) codes.

The signal X0′ is input to the skew adaptation circuit33. The skew adaptation circuit33generates a skew calibration code Cs based on the n digital values included in the signal X0′ for one cycle. The skew calibration code Cs is a set of n digital values (codes) corresponding to the n clock signals included in the signal CLK for one cycle. The skew calibration code Cs generated by the skew adaptation circuit33is output to the CDR40.

Note that the skew adaptation circuit33generates the skew calibration code Cs by, for example, two types of skew update processing.

In the first type of skew update processing, the skew adaptation circuit33regards one digital value among the n digital values included in the signal X0′ for one cycle as a reference value. Then, the skew adaptation circuit33updates (n−1) codes excluding one code corresponding to the reference value among the n codes included in the skew calibration code Cs. At this time, the skew adaptation circuit33does not update the one code corresponding to the digital value serving as the reference value among the n codes included in the skew calibration code Cs.

In the second type of skew update processing, the skew adaptation circuit33first updates the (n−1) codes excluding the one code corresponding to the reference value among the n codes included in the skew calibration code Cs. Then, the skew adaptation circuit33further updates the one code corresponding to the digital value serving as the reference value based on the updated (n−1) codes.

The signal X0′ is input to the FFE34. The FFE34executes arithmetic processing using a digital value to be calculated and digital values of several symbols before and after the digital value to be calculated for every n digital values included in the signal X0′ for one cycle. The FFE34generates a signal X1as a result of the arithmetic processing. That is, the signal X1is a digital signal similarly to the signals X0and X0′. The signal X1for one cycle is a set of n digital values. The FFE34outputs the signal X1to the data comparator35and the FFE36. The signal X1is further output to the CDR40.

The signal X1is input to the data comparator35. The data comparator35determines data encoded by the host device2as data A1based on the signal X1. Specifically, in a case where PAM4 is applied, the data comparator35determines 2-bit data for every n digital values included in the signal X1for one cycle. That is, the data A1has 2-bit data for every n digital values included in the signal X1for one cycle. The 2-bit data corresponds to, for example, any of “−3”, “−1”, “+1”, and “+3”. The data comparator35outputs the data A1to the CDR40.

The signal X1is input to the FFE36. Note that the signal input to the FFE36may be a signal X1′ (not illustrated) different from the signal X1input to the data comparator35and the CDR40. In this case, the signal X1′ input to the FFE36is generated based on the signal X1. The FFE36executes arithmetic processing using a digital value to be calculated and digital values of several symbols before and after the digital value to be calculated for every n digital values included in the signal X1for one cycle. The arithmetic processing by the FFE36may be different from the arithmetic processing by the FFE34. The FFE36generates a signal X2as a result of the arithmetic processing. That is, the signal X2is a digital signal similarly to the signals X0, X0′, and X1. The signal X2for one cycle is a set of n digital values. The FFE36outputs the signal X2to the DFE37.

The signal X2is input to the DFE37. The DFE37executes arithmetic processing based on a digital value to be calculated and digital values of several symbols before and after the digital value to be calculated for every n digital values included in the signal X2for one cycle. The DFE37generates and outputs a signal Xf as a result of the arithmetic processing. That is, the signal Xf is a digital signal similarly to the signals X0, X0′, X1, and X2. The signal Xf for one cycle is a set of n digital values. The signal Xf generated by the DFE37is output to the data comparator38and a subsequent circuit.

The signal Xf is input to the data comparator38. The data comparator38determines data encoded by the host device2as the data Af based on the signal Xf.

Specifically, in a case where PAM4 is applied, the data comparator38determines 2-bit data for every n digital values included in the signal Xf for one cycle. The data Af determined by the data comparator38is output to a subsequent circuit.

1.6 Clock Data Recovery Circuit

Next, an internal configuration of the clock data recovery circuit (CDR) of the receiver circuit according to the embodiment will be described.FIG.5is a block diagram illustrating an example of the configuration of the clock data recovery circuit of the receiver circuit according to the embodiment.

The CDR40includes a PD41, an LF42, a PLL43, a PI44, a skew calibration circuit45, and a clock generation circuit46.

The PD41is a MM baud rate phase detector (Mueller-Muller Baud-Rate Phase Detector). The MM baud rate phase detector uses one sampling result per symbol when detecting a phase shift related to the signal CLK. Further, the MM baud rate phase detector does not use a sampling result of an edge (boundary) of a pulse corresponding to the data encoded into the signals S0and /S0when detecting the phase shift. The signal X1and the data A1are input to the PD41from the digital processing circuit30. The PD41calculates a value PDOUT based on the signal X1and the data A1. The value PDOUT is a value corresponding to a phase shift between a current sampling timing by the signal CLK and an optimum sampling timing. The PD41outputs the value PDOUT to the LF42.

The LF42is a loop filter. The value PDOUT is input to the LF42. The LF42calculates a value LFOUT based on the value PDOUT. The value LFOUT is a value corresponding to the correction amount of the phase of the signal CLK. The LF42outputs the value LFOUT to the PI44.

The PLL43is a phase locked loop circuit. The PLL43generates a signal REF. The signal REF is a reference signal having a reference frequency in the receiver circuit. The PLL43outputs the signal REF to the PI44. In the following description, a difference between the reference frequency of the signal REF and the frequency of the clock signal embedded in the signals S0and /S0by the host device2is also referred to as a “frequency deviation”.

The PI44is a phase interpolator. The value LFOUT is input from the LF42to the PI44, and the signal REF is input from the PLL43to the PI44. The PI44generates a signal PIOUT from the signal REF based on the value LFOUT. The signal PIOUT is an n-phase signal whose phase has been corrected. The PI44outputs the signal PIOUT to the skew calibration circuit45.

The signal PIOUT is input to the skew calibration circuit45. The skew calibration circuit45executes skew calibration processing for each n-phase signal included in the signal PIOUT for one cycle. In the skew calibration processing by the skew calibration circuit45, the skew calibration code Cs input from the skew adaptation circuit33is used. As a result of the skew calibration processing, the skew calibration circuit45generates a signal PIOUT′ whose phase is adjusted according to the skew calibration code Cs. That is, the signal PIOUT′ is an n-phase signal similarly to the signal PIOUT. For example, in a case where the skew calibration code Cs is positive, the skew calibration circuit45generates the signal PIOUT′ so that the phase shifts in a negative direction. Further, for example, in a case where the skew calibration code Cs is negative, the skew calibration circuit45generates the signal PIOUT′ so that the phase shifts in a positive direction. The skew calibration circuit45outputs the signal PIOUT′ to the clock generation circuit46.

The signal PIOUT′ is input to the clock generation circuit46. The clock generation circuit46generates the signal CLK based on the signal PIOUT′. The clock generation circuit46uses, for example, a frequency divider circuit to generate the signal CLK. The clock generation circuit46outputs the signal CLK to the TI-ADC20.

1.7 Skew Adaptation Circuit

Next, an internal configuration of the skew adaptation circuit of the digital processing circuit according to the embodiment will be described. Note that, in the following description, the signal X0′ of an m-th cycle may be indicated as X0′<m>. Values corresponding to n values X0_1to X0_nof the signal X0′ are indicated as values X0′_1to X0′_n, respectively. Further, the n codes of the skew calibration codes Cs corresponding to the n values X0′_1to X0′_nare indicated as n codes Cs_1to Cs_n, respectively.

FIG.6is a block diagram illustrating an example of the configuration of the skew adaptation circuit of the digital processing circuit according to the embodiment. The skew adaptation circuit33includes a plurality of delay circuits51, a plurality of adders52, a plurality of absolute value conversion circuits53, a plurality of adders54, a plurality of moving average calculation circuits55, a plurality of multipliers56, a plurality of adders57, a plurality of delay circuits58, an adder59, and a switch60. The plurality of delay circuits51include n delay circuits51-1,51-2,51-3, . . . , and51-n. The plurality of adders52include n adders52-1,52-2,52-3, . . . , and52-n. The plurality of absolute value conversion circuits53include n absolute value conversion circuits53-1,53-2,53-3, . . . , and53-n. The plurality of adders54include (n−1) adders54-2,54-3, . . . , and54-n. The plurality of moving average calculation circuits55include (n−1) moving average calculation circuits55-2,55-3, . . . , and55-n. The plurality of multipliers56include (n−1) multipliers56-2,56-3, . . . , and56-n. The plurality of adders57include n adders57-1,57-2,57-3, . . . , and57-n. The plurality of delay circuits58include n delay circuits58-1,58-2,58-3, . . . , and58-n.

The values X0′_1<m> to X0′_n<m> are input to the n delay circuits51-1to51-n, respectively. The delay circuits51-1to51-ndelay the values X0′_1<m> to X0′_n<m> by, for example, one cycle, and output the delayed values.

The value X0′_1<m> output from the delay circuit51-1and the value X0′_2<m> output from the delay circuit51-2are input to the adder52-1. The adder52-1subtracts the value X0′_1<m> from the value X0′_2<m>. The adder52-1outputs a value (X0′_2<m>−X0′_1<m>) to the absolute value conversion circuit53-1as a calculation result.

The value X0′_2<m> output from the delay circuit51-2and the value X0′_3<m> output from the delay circuit51-3are input to the adder52-2. The adder52-2subtracts the value X0′_2<m> from the value X0′_3<m>. The adder52-2outputs a value (X0′_3<m>−X0′_2<m>) to the absolute value conversion circuit53-2as a calculation result.

The value X0′_k<m> output from the delay circuit51-kand the value X0′_(k+1)<m> output from the delay circuit51-(k+1) are input to the adder52-k. The adder52-ksubtracts the value X0′_k<m> from the value X0′_(k+1)<m>. The adder52-koutputs a value (X0′_(k+1)<m>−X0′_k<m>) to the absolute value conversion circuit53-kas a calculation result.

The description regarding the adder52-kholds for all k of 3 or more and (n−1) or less.

The value X0′_n<m> output from the delay circuit51-nand the value X0′_1<m+1> after being input to the delay circuit51-1are input to the adder52-n. The adder52-nsubtracts the value X0′_n<m> from the value X0′_1<m+1>. The adder52-noutputs a value (X0′_1<m+1>−X0′_n<m>) to the absolute value conversion circuit53-nas a calculation result.

The output values from the n adders52-1to52-nare input to the n absolute value conversion circuits53-1to53-n, respectively. The absolute value conversion circuits53-1to53-noutput absolute values of the output values from the adders52-1to52-n, respectively.

The output value from the absolute value conversion circuit53-1and the output value from the absolute value conversion circuit53-2are input to the adder54-2. The adder54-2subtracts the output value from the absolute value conversion circuit53-2from the output value from the absolute value conversion circuit53-1. The adder54-2outputs a calculation result to the moving average calculation circuit55-2.

The output value from the absolute value conversion circuit53-(k−1) and the output value from the absolute value conversion circuit53-kare input to the adder54-k. The adder54-ksubtracts the output value from the absolute value conversion circuit53-kfrom the output value from the absolute value conversion circuit53-(k−1). The adder54-koutputs a calculation result to the moving average calculation circuit55-k.

The description regarding the adder54-kholds for all k of 3 or more and n or less.

The output values from the adders54-2to54-nare input to the moving average calculation circuits55-2to55-n, respectively. The moving average calculation circuits55-2to55-noutput moving averages of the output values from the adders54-2to54-n, respectively.

The output values from the moving average calculation circuits55-2to55-nare input to the multipliers56-2to56-n, respectively. Each of the multipliers56-2to56-noutputs a value obtained by multiplying the output value from each of the moving average calculation circuits55-2to55-nby a predetermined multiplier. Note that the predetermined multipliers applied to the multipliers56-2to56-nmay be equal to or different from each other.

The output values from the multipliers56-2to56-nand the output values from the delay circuits58-2to58-nare input to the adders57-2to57-n, respectively. The adders57-2to57-nadd the output values from the multipliers56-2to56-nand the output values from the delay circuits58-2to58-n, respectively. The adders57-2to57-noutput calculation results to the delay circuits58-2to58-n, respectively. The output values from the adders57-2to57-nare further output as codes Cs_2to Cs_n to the adder59and the skew calibration circuit45of the CDR40.

The codes Cs_2to Cs_n are input to the delay circuits58-2to58-n, respectively. The delay circuits58-2to58-ndelay the codes Cs_2to Cs_n by, for example, one cycle, and output the delayed codes Cs_2to Cs_n to the adders57-2to57-n, respectively.

The codes Cs_2to Cs_n are input to the adder59. The adder59adds the codes Cs_2to Cs_n. The adder59outputs a calculation result to the adder57-1.

An addition value of the codes Cs_2to Cs_n by the adder59is input to the adder57-1. The output value from the delay circuit58-1is further input to the adder57-1. The adder57-1adds the addition value of the codes Cs_2to Cs_n by the adder59and the output value from the delay circuit58-1. The adder57-1outputs a calculation result to the delay circuit58-1. The output value from the adder57-1is further output to the switch60.

The output value of the adder57-1is input to the delay circuit58-1. The delay circuit58-1delays the output value of the adder57-1by, for example, one cycle, and outputs the delayed output value to the adder57-1.

The switch60includes a first input end60-1, a second input end60-2, and an output end60-3. The switch60is configured to switch the connection with the output end60-3to one of the first input end60-1and the second input end60-2. The output value of the adder57-1is input to the first input end60-1of the switch60. An initial value Cs_1ini is input to the second input end60-2of the switch60. The initial value Cs_1ini is, for example, “0”. A state (a state illustrated inFIG.6) in which the second input end60-2and the output end60-3of the switch60are connected corresponds to the first type of skew update processing. A state in which the first input end60-1and the output end60-3of the switch60are connected corresponds to the second type of skew update processing. The switch60is, for example, a circuit including a multiplexer or a transistor. An output value from the output end60-3of the switch60is output as the code Cs_1to the skew calibration circuit45of the CDR40. That is, the code Cs_1is fixed to the initial value Cs_1ini in the first type of skew update processing. Then, the code Cs_1is updated to a value based on the addition value of the codes Cs_2to Cs_n in the second type of skew update processing.

1.8 Gain Adaptation Circuit

Next, an internal configuration of the gain adaptation circuit of the digital processing circuit according to the embodiment will be described. Note that, in the following description, the n codes of the gain calibration codes Cg corresponding to the n values X0′_1to X0′_nare indicated as n codes Cg_1to Cg_n, respectively.

FIG.7is a block diagram illustrating an example of the configuration of the gain adaptation circuit of the digital processing circuit according to the embodiment. The gain adaptation circuit32includes a plurality of absolute value conversion circuits61, a plurality of adders62, a plurality of adders63, a plurality of delay circuits64, an adder65, and a switch66. The plurality of absolute value conversion circuits61include n absolute value conversion circuits61-1,61-2,61-3, . . . , and61-n. The plurality of adders62include (n−1) adders62-2,62-3, . . . , and62-n. The plurality of adders63include n adders63-1,63-2,63-3, . . . , and63-n. The plurality of delay circuits64include n delay circuits64-1,64-2,64-3, . . . , and64-n.

The values X0′_1to X0′_nare input to the absolute value conversion circuits61-1to61-n, respectively. The absolute value conversion circuits61-1to61-noutput absolute values of the values X0′_1to X0′_n, respectively.

The output value from the absolute value conversion circuit61-1and the output value from the absolute value conversion circuit61-2are input to the adder62-2. The adder62-2subtracts the output value from the absolute value conversion circuit61-2from the output value from the absolute value conversion circuit61-1. The adder62-2outputs a calculation result to the adder63-2.

The output value from the absolute value conversion circuit61-1and the output value from the absolute value conversion circuit61-kare input to the adder62-k. The adder62-ksubtracts the output value from the absolute value conversion circuit61-kfrom the output value from the absolute value conversion circuit61-1. The adder62-koutputs a calculation result to the adder63-k.

The description regarding the adder62-kholds for all k of 3 or more and n or less.

The output values from the adders62-2to62-nand the output values from the delay circuits64-2to64-nare input to the adders63-2to63-n, respectively. The adders63-2to63-nadd the output values from the adders62-2to62-nand the output values from the delay circuits64-2to64-n, respectively. The adders63-2to63-noutput calculation results to the delay circuits64-2to64-n, respectively. The output values from the adders63-2to63-nare further output as codes Cg_2to Cg_n to the adder65and the gain calibration circuit31of the digital processing circuit30.

The codes Cg_2to Cg_n are input to the delay circuits64-2to64-n, respectively. The delay circuits64-2to64-ndelay the codes Cg_2to Cg_n by, for example, one cycle, and output the delayed codes Cg_2to Cg_n to the adders63-2to63-n, respectively.

The codes Cg_2to Cg_n are input to the adder65. The adder65adds the codes Cg_2to Cg_n. The adder65outputs a calculation result to the adder63-1.

An addition value of the codes Cg_2to Cg_n by the adder65is input to the adder63-1. The output value from the delay circuit64-1is further input to the adder63-1. The adder63-1adds the addition value of the codes Cg_2to Cg_n by the adder65and the output value from the delay circuit64-1. The adder63-1outputs a calculation result to the delay circuit64-1. The output value from the adder63-1is further output to the switch66.

The output value of the adder63-1is input to the delay circuit64-1. The delay circuit64-1delays the output value of the adder63-1by, for example, one cycle and outputs the delayed output value to the adder63-1.

The switch66includes a first input end66-1, a second input end66-2, and an output end66-3. The switch66is configured to switch the connection with the output end66-3to one of the first input end66-1and the second input end66-2. The output value of the adder63-1is input to the first input end66-1of the switch66. An initial value Cg_1ini is input to the second input end66-2of the switch66. The initial value Cg_1ini is, for example, “0”. A state (a state illustrated inFIG.7) in which the second input end66-2and the output end66-3of the switch66are connected corresponds to the first type of gain update processing. A state in which the first input end66-1and the output end66-3of the switch66are connected corresponds to the second type of gain update processing. The switch66is, for example, a circuit including a multiplexer or a transistor. The output value from the output terminal66-3of the switch66is output as the code Cg_1to the gain calibration circuit31of the digital processing circuit30. That is, the code Cg_1is fixed to the initial value Cg_1ini in the first type of gain update processing. Then, the code Cg_1is updated to a value based on the addition value of the codes Cg_2to Cg_n in the second type of gain update processing.

2. Operation

Next, an operation of the receiver device according to the embodiment will be described.

2.1 Receiver Operation Including CDR Loop

First, a receiver operation including a CDR loop in the receiver device according to the embodiment will be described.FIG.8is a flowchart illustrating an example of a receiver operation including a CDR loop in the receiver device according to the embodiment.

When reception of the signals S0and /S0is started (start), the TI-ADC20samples and AD-converts the signals S1and /S1based on the signal CLK, and generates the signal X0for one cycle (S1). The signals S1and /S1are signals generated based on the signals S0and /S0.

The FFE34of the digital processing circuit30generates the signal X1for one cycle based on the signal X0for one cycle (S2).

The data comparator35of the digital processing circuit30determines the data A1for one cycle based on the signal X1for one cycle (S3).

The CDR40recovers the signal CLK based on the signal X1and the data A1for one cycle (S4).

The host interface circuit8determines whether or not the reception of the signals S0and /S0has been ended based on the presence or absence of the input of the signals S1and /S1(S5).

In a case where the reception of the signals S0and /S0has not been ended (S5; no), the TI-ADC20generates the signal X0of the next cycle based on the recovered signal CLK (S1). As a result, the processes of S1to S4are repeated (CDR loop) until the reception of the signals S0and /S0is ended.

In a case where the reception of the signals S0and /S0has been ended (S5; yes), the receiver operation ends (end).

2.2 Gain Adjustment Operation

Next, a gain adjustment operation according to the embodiment will be described. The gain adjustment operation is an operation including gain calibration processing by the gain calibration circuit31and gain update processing by the gain adaptation circuit32in the digital processing circuit30.FIG.9is a flowchart illustrating an example of the gain adjustment operation in the receiver device according to the embodiment.

When reception of the signals S0and /S0is started (start), the gain adaptation circuit32initializes the gain calibration codes Cg_1to Cg_n and a variable i, and selects the second input end66-2of the switch66(S11). The variable i is, for example, an integer having an initial value of 0. Accordingly, the initial value Cg_1ini is output from the gain adaptation circuit32as the gain calibration code Cg_1via the second input end66-2of the switch66.

The gain calibration circuit31calibrates the gains of the signals X0_1to X0_nbased on the gain calibration codes Cg_1to Cg_n initialized by the processing of S11(S12). That is, the gain calibration circuit31outputs the signals X0_1to X0_n(that is, the signals X0′_1to X0′_n) whose gains are calibrated based on the gain calibration codes Cg_1to Cg_n.

Based on the signals X0_1to X0_nwhose gains have been calibrated by the gain calibration processing in S12, the gain adaptation circuit32updates the gain calibration codes Cg_2to Cg_n excluding the gain calibration code Cg_1(S13). That is, in the processing of S13, the gain calibration code Cg_1is not updated from the initial value Cg_1ini.

After the processing of S13, the gain adaptation circuit32waits until the next CDR loop (S14).

After the processing of S14, the gain adaptation circuit32determines whether or not the gain calibration codes Cg_2to Cg_n have converged (S15). Whether or not the gain calibration codes Cg_2to Cg_n have converged is determined by, for example, whether or not update amounts of the gain calibration codes Cg_2to Cg_n in the processing of S13can be considered to be sufficiently small.

In a case where it is determined that the gain calibration codes Cg_2to Cg_n have not converged (S15; no), the gain calibration circuit31calibrates the gains of the signals X0_1to X0_nbased on the gain calibration code Cg_1initialized by the processing of S11and the gain calibration codes Cg_2to Cg_n updated by the processing of S13in the CDR loop one cycle before (S12). Thereafter, the subsequent processing of S13is executed. As described above, while it is determined that the gain calibration codes Cg_2to Cg_n have not converged, the gain update processing of not updating the gain calibration code Cg_1is repeatedly executed.

In a case where it is determined that the gain calibration codes Cg_2to Cg_n have converged (S15; yes), the gain adaptation circuit32selects the first input end66-1of the switch66. Then, the gain calibration circuit31calibrates the gains of the signals X0_1to X0_nbased on the gain calibration code Cg_1initialized in the processing of S11and the gain calibration codes Cg_2to Cg_n determined to be converged in the processing of S15(S16).

Based on the signals X0_1to X0_n(that is, the signals X0_1to X0′_n) whose gains have been calibrated by the gain calibration processing in S16, the gain adaptation circuit32updates the gain calibration codes Cg_2to Cg_n excluding the gain calibration code Cg_1(S17). In the processing of S17, the gain calibration code Cg_1is not updated similarly to the processing of S13.

The gain adaptation circuit32determines whether or not the variable i is greater than or equal to a threshold value (S18).

In a case where the variable i is less than the threshold value (S18; no), the gain adaptation circuit32increments the variable i (S19).

In a case where the variable i is greater than or equal to the threshold value (S18; yes), the gain adaptation circuit32resets the variable i to 0 (S20).

After the processing of S20, the gain adaptation circuit32updates the gain calibration code Cg_1based on the gain calibration codes Cg_2to Cg_n updated by the processing of S17(S21).

After the processing of S19or the processing of S21, the host interface circuit8determines whether or not the reception of the signals S0and /S0has been ended based on the presence or absence of the input of the signals S1and /S1(S22).

In a case where the reception of the signals S0and /S0has not been ended (S22; no), the gain adaptation circuit32waits until the next CDR loop (S23).

After the processing of S23, the gain calibration circuit31calibrates the gains of the signals X0_1to X0_nbased on the gain calibration code Cg_1updated in the processing of S21in the CDR loop one cycle before or whose update is postponed by the processing of S18, and the gain calibration codes Cg_2to Cg_n updated in the processing of S17in the CDR loop one cycle before (S16). Then, the subsequent processes of S17to S22are executed.

As described above, after the convergence of the gain calibration codes Cg_2to Cg_n, the update of the gain calibration code Cg_1is postponed until the variable i becomes greater than or equal to the threshold value. Then, the gain calibration code Cg_1is updated in a cycle (that is, a cycle longer than the update cycle of the gain calibration codes Cg_2to Cg_n) in which the variable i is greater than or equal to the threshold value. Then, the gain update processing of the gain calibration code Cg_1and the gain update processing of the gain calibration codes Cg_2to Cg_n are repeatedly updated in different cycles until the reception of the signals S0and /S0is ended.

In a case where the reception of the signals S0and /S0has been ended (S22; yes), the gain adjustment operation ends (end).

2.3 Skew Adjustment Operation

Next, a skew adjustment operation according to the embodiment will be described. The skew adjustment operation includes skew calibration processing by the skew calibration circuit45of the CDR40and skew update processing by the skew adaptation circuit33of the digital processing circuit30.FIG.10is a flowchart illustrating an example of the skew adjustment operation in the receiver device according to the embodiment.

When reception of the signals S0and /S0is started (start), the skew adaptation circuit33initializes the skew calibration codes Cs_1to Cs_n and a variable j, and selects the second input end60-2of the switch60(S31). The variable j is, for example, an integer having an initial value of 0. Accordingly, the initial value Cs_1ini is output from the skew adaptation circuit33as the skew calibration code Cs_1via the second input end60-2of the switch60.

Based on the signals X0_1to X0_noutput from the TI-ADC20, the skew adaptation circuit33updates the skew calibration codes Cs_2to Cs_n excluding the skew calibration code Cs_1(S32). That is, in the processing of S32, the skew calibration code Cs_1is not updated from the initial value Cs_1ini.

After the processing of S32, the skew calibration circuit45calibrates the skew of the signals PIOUT_1to PIOUT_n based on the skew calibration code Cs_1initialized by the processing of S31and the skew calibration codes Cs_2to Cs_n updated by the processing of S32(S33).

After the processing of S33, the skew adaptation circuit33waits until the next CDR loop (S34).

After the processing of S34, the skew adaptation circuit33determines whether or not the skew calibration codes Cs_2to Cs_n have converged (S35). Whether or not the skew calibration codes Cs_2to Cs_n have converged is determined by, for example, whether or not update amounts of the skew calibration codes Cs_2to Cs_n in the processing of S32can be considered to be sufficiently small.

In a case where it is determined that the skew calibration codes Cs_2to Cs_n have not converged (S35; no), the skew adaptation circuit33updates the skew calibration codes Cs_2to Cs_n excluding the skew calibration code Cs_1based on the signals X0_1to X0_noutput based on the signal CLK in which the skew has been calibrated by the processing of S33one cycle before (S32). Thereafter, the subsequent processing of S33is executed. As described above, while it is determined that the skew calibration codes Cs_2to Cs_n have not converged, the skew update processing of not updating the skew calibration code Cs_1is repeatedly executed.

In a case where it is determined that the skew calibration codes Cs_2to Cs_n have converged (S35; yes), the skew adaptation circuit33selects the first input end60-1of the switch60. Then, the skew adaptation circuit33updates the skew calibration codes Cs_2to Cs_n excluding the skew calibration code Cs_1based on the signals X0_1to X0_noutput based on the skew calibration code Cs_1initialized in the processing of S31and the skew calibration codes Cs_2to Cs_n determined to have converged in the processing of S35(S36). In the processing of S36, the skew calibration code Cs_1is not updated similarly to the processing of S32.

The skew adaptation circuit33determines whether or not the variable j is greater than or equal to a threshold value (S37).

In a case where the variable j is less than the threshold value (S37; no), the skew adaptation circuit33increments the variable j (S38).

In a case where the variable j is greater than or equal to the threshold value (S37; yes), the skew adaptation circuit33resets the variable j to 0 (S39).

After the processing of S39, the skew adaptation circuit33updates the skew calibration code Cs_1based on the skew calibration codes Cs_2to Cs_n updated by the processing of S36(S40).

After the processing of S38or the processing of S40, the skew calibration circuit45calibrates the skew of the signals PIOUT_1to PIOUT_n based on the skew calibration codes Cs_1to Cs_n (S41).

After the processing of S41, the host interface circuit8determines whether or not the reception of the signals S0and /S0has been ended based on the presence or absence of the input of the signals S1and /S1(S42).

In a case where the reception of the signals S0and /S0has not been ended (S42; no), the skew adaptation circuit33waits until the next CDR loop (S43).

After the processing of S43, the skew adaptation circuit33updates the skew calibration codes Cs_2to Cs_n based on the signals X0_1to X0_noutput based on the signal CLK calibrated in the skew calibration processing of S41in the CDR loop one cycle before (S36). Then, the subsequent processes of S37to S42are executed.

As described above, after the convergence of the skew calibration codes Cs_2to Cs_n, the update of the skew calibration code Cs_1is postponed until the variable j becomes greater than or equal to the threshold value. Then, the skew calibration code Cs_1is updated in a cycle (that is, a cycle longer than the update cycle of the skew calibration codes Cs_2to Cs_n) in which the variable j is greater than or equal to the threshold value. Then, the skew update processing of the skew calibration code Cs_1and the skew update processing of the skew calibration codes Cs_2to Cs_n are repeatedly updated in different cycles until the reception of the signals S0and /S0is ended.

In a case where the reception of the signals S0and /S0has been completed (S42; yes), the skew adjustment operation ends (end).

3. Effects According to Embodiment

According to the embodiment, the gain adaptation circuit32generates the gain calibration codes Cg_2to Cg_n based on the values X0_1to X0_n. The gain adaptation circuit32generates the gain calibration code Cg_1based on the sum of the generated gain calibration codes Cg_2to Cg_n. As a result, it is possible to adjust gain errors included in all of the n ADCs21-1to21-n. Further, the skew adaptation circuit33generates the skew calibration codes Cs_2to Cs_n based on the values X0_1to X0_n. The skew adaptation circuit33generates the skew calibration code Cs_1based on the sum of the generated skew calibration codes Cs_2to Cs_n. As a result, it is possible to adjust phase errors included in all of the n ADCs21-1to21-n.

To supplement, the n ADCs21-1to21-neach have different gain errors and different phase errors. On the other hand, these errors can be calculated as a relative amount based on a certain ADC (for example, ADC21-1). Therefore, in a case where the gain and the skew of a certain ADC are fixed as reference values, adjustment ranges of the gain calibration codes Cg_2to Cg_n and the skew calibration codes Cs_2to Cs_n are set to ranges including the errors of the initial values Cg_1ini and Cs_1ini, respectively. That is, in a case where the gain and the phase of a certain ADC are fixed as the reference values, the adjustment ranges of the gain calibration codes Cg_2to Cg_n and the skew calibration codes Cs_2to Cs_n are set to be excessively large, which is not preferable.

According to the present embodiment, the gain adaptation circuit32generates the gain calibration code Cg_1based on the sum of the generated gain calibration codes Cg_2to Cg_n. As a result, a part of the gain error included in the ADC21-1can be absorbed as an update amount of the gain calibration code Cg_1. Therefore, the influence of the gain error included in the ADC21-1on the update amount of the gain calibration codes Cg_2to Cg_n can be reduced. Further, the skew adaptation circuit33generates the skew calibration code Cs_1based on the sum of the generated skew calibration codes Cs_2to Cs_n. As a result, a part of the phase error included in the ADC21-1can be absorbed as an update amount of the skew calibration code Cs_1. Therefore, it is possible to reduce the influence of the phase error included in the ADC21-1on the update amount of the skew calibration codes Cs_2to Cs_n.

Furthermore, the gain adaptation circuit32starts updating the gain calibration code Cg_1after it is determined that the gain calibration codes Cg_2to Cg_n have converged. After it is determined that the skew calibration codes Cs_2to Cs_n have converged, the skew adaptation circuit33starts updating the skew calibration code Cs_1. As a result, after a relative value of the error between the ADC21-1and the other ADCs21-2to21-nis substantially determined, an absolute value of the error of the ADC21-1can be estimated. Therefore, in the gain update processing and the skew update processing, it is possible to suppress divergence of the updated values of the gain calibration code Cg_1and the skew calibration code Cs_1.

4. Modifications

Note that the embodiment is not limited to the above-described example, and various modifications can be applied.

In the above-described embodiment, the host interface circuit8has been described as an example of the receiver circuit, but the present invention is not limited thereto. For example, the receiver circuit may be any semiconductor integrated circuit used for serial communication.

Further, in the above-described embodiment, the gain adjustment operation and the skew adjustment operation have been described as operations independent of each other, but the present invention is not limited thereto. For example, the gain adjustment operation and the skew adjustment operation can be executed in parallel.

Furthermore, in the embodiment described above, the case where it is determined whether or not to update the gain calibration code Cg_1based on whether or not the variable i is greater than or equal to the threshold value in the processes of S18to S21of the gain adjustment operation has been described, but the present invention is not limited thereto. For example, the gain adaptation circuit32may determine whether or not to update the gain calibration code Cg_1based on whether or not the update amounts of the gain calibration codes Cg_2to Cg_n have converged.

Furthermore, in the embodiment described above, the case where it is determined whether or not to update the skew calibration code Cs_1based on whether or not the variable j is greater than or equal to the threshold value in the processes of S37to S40of the skew adjustment operation has been described, but the present invention is not limited thereto. For example, the skew adaptation circuit33may determine whether or not to update the skew calibration code Cs_1based on whether or not the update amounts of the skew calibration codes Cs_2to Cs_n have converged.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit.