Patent ID: 12238971

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

As the present disclosure allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. The effects and features of the present disclosure, and ways to achieve them will become apparent by referring to embodiments that will be described later in detail with reference to the drawings. However, the present disclosure is not limited to the following embodiments but may be embodied in various forms.

It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

In the embodiments below, the singular forms include the plural forms unless the context clearly indicates otherwise.

In the present specification, it is to be understood that the terms such as “including” or “having” are intended to indicate the existence of the features or elements disclosed in the specification, and are not intended to preclude the possibility that one or more other features or elements may be added.

In the embodiments below, it will be understood that when a portion such as a layer, an area, or an element is referred to as being “on” or “above” another portion, it can be directly on or above the other portion, or intervening portion may also be present.

Also, in the drawings, for convenience of description, sizes of elements may be exaggerated or contracted. For example, since sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

In the present specification, “A and/or B” refers to A, B, or A and B. In addition, “at least one of A and B” refers to A, B, or A and B.

In the embodiments below, when a line is described as “extending in a first direction or a second direction,” it means that the line extends not only in a straight line but also in a zigzag line or a curve in the first or second direction.

In the embodiments below, the term “on a plane” refers to a view of an object viewed from above, and “on a cross-section” refers to a view of a vertical cross-section of an object viewed from a side. In the embodiments below, when referred to as “overlapping,” this includes overlapping “on a plane” and “on a cross-section.”

Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, like reference numerals refer to like elements.

FIG.1is a view schematically illustrating a display apparatus according to an embodiment.

Referring toFIG.1, a display apparatus1according to an embodiment may be implemented as an electronic device such as a smartphone, a mobile phone, a navigation device, a game player, a TV, a head unit for vehicles, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP), a personal digital assistant (PDA), or the like. Also, the electronic device may be a flexible device.

A substrate100may be divided into a display area DA on which an image is displayed and a peripheral area PA arranged around the display area DA.

The substrate100may include various materials such as glass, metal, or plastic. In an embodiment, the substrate100may include a flexible material. The flexible material refers to a substrate that is easily bent and curved and is foldable or rollable. The substrate100including a flexible material may include super-slim glass, metal, or plastic.

Pixels PX including various display elements such as an organic light-emitting diode (OLED) may be arranged in the display area DA of the substrate100. The pixels PX are provided in a plural number, and the plurality of pixels PX may be arranged in various forms such as a stripe arrangement, a pentile arrangement, or a mosaic arrangement to realize an image.

In an embodiment, when viewing the display area DA from a top plan, the display area DA may have a rectangular shape as illustrated inFIG.1. In an embodiment, the display area DA may have a polygonal shape such as a triangle, a pentagon, a hexagon, or the like, or a circular shape, an oval shape, or an amorphous shape, or the like.

The peripheral area PA of the substrate100is an area around the display area DA, where an image is not displayed. Various lines configured to transfer an electrical signal to be applied to the display area DA, a printed circuit board or a driver integrated circuit (IC) chip may be located in the peripheral area PA.

Hereinafter, for convenience, the display apparatus1including an organic light-emitting diode as a display element will be described. However, the embodiments may be applied to a display apparatus1of various types such as a liquid crystal display apparatus, an electrophoretic display apparatus, an inorganic electroluminescent (EL) display apparatus, or the like.

FIG.2is an equivalent circuit diagram of a pixel included in a display apparatus according to an embodiment.

Referring toFIG.2, a pixel PX may include a plurality of transistors, for example, first through seventh transistors T1, T2, T3, T4, T5, T6, and T7, a first capacitor Cst, a second capacitor Cbt, an organic light-emitting diode OLED as a display element, and signal lines connected to the above elements, first and second initialization voltage lines VIL1and VIL2, and a power voltage line PL. The signal lines may include a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EL. According to an embodiment, at least one of the signal lines, the first and second initialization voltage lines VIL1and VIL2, and/or the power voltage line PL may be shared among neighboring pixels.

The power voltage line PL may be configured to transfer a first power voltage ELVDD to the first transistor T1. The first initialization voltage line VIL1may be configured to transfer, to the pixel PX, a first initialization voltage Vint1initializing a voltage of a gate electrode of the first transistor T1. The second initialization voltage line VIL2may be configured to transfer, to the pixel PX, a second initialization voltage Vint2initializing an anode (e.g., a pixel electrode) of the organic light-emitting diode OLED.

The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, and the first and second initialization voltage lines VIL1and VIL2may extend in a first direction D1and be arranged in each row and apart from each other. The data line DL and the power voltage line PL may extend in a second direction D2and be arranged in each column and apart from each other.

InFIG.2, the third transistor T3and the fourth transistor T4from among the first through seventh transistors T1, T2, T3, T4, T5, T6, and T7are implemented as an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (NMOS), and the other transistors are implemented as a p-channel MOSFET (PMOS).

The first transistor T1may be connected to the power voltage line PL via the fifth transistor T5to and electrically connected to the organic light-emitting diode OLED via the sixth transistor T6. The first transistor T1acts as a driving transistor, and may receive a data signal DATA according to a switching operation of the second transistor T2to supply a driving current bled to the organic light-emitting diode OLED.

The second transistor T2may be connected to the first scan line SL1and the data line DL and connected to the power voltage line PL via the fifth transistor T5. The second transistor T2may be turned on according to a first scan signal Sn received via the first scan line SL1to perform a switching operation of transferring the data signal DATA transferred to the data line DL, to a node N1.

The third transistor T3may be connected to the fourth scan line SL4and to the organic light-emitting diode OLED via the sixth transistor T6to be connected. The third transistor T3is turned on according to a fourth scan signal Sn′ received via the fourth scan line SL4to diode-connect the first transistor T1.

The fourth transistor T4is connected to the third scan line SL3, which is a previous scan line, and the first initialization voltage line VIL1, and is turned on according to a third scan signal Sn−1, which is a previous scan signal and received via the third scan line SL3, to transfer the first initialization voltage Vint1from the first initialization voltage line VIL1to the gate electrode of the first transistor T1, thereby initializing a voltage of the gate electrode of the first transistor T1.

The fifth transistor T5and the sixth transistor T6are connected to the emission control line EL, and are simultaneously turned on according to an emission control signal En received via the emission control line EL to form a current path such that the driving current IOLEDmay flow in a direction from the power voltage line PL to the organic light-emitting diode OLED.

The seventh transistor T7is connected to the second scan line SL2, which is a next scan line, and the second initialization voltage line VIL2, and is turned on according to a second scan signal Sn+1, which is a next scan signal and received via the second scan line SL2, to transfer, to the organic light-emitting diode OLED, the second initialization voltage Vint2from the second initialization voltage line VIL2, thereby initializing the anode (e.g., a pixel electrode) of the organic light-emitting diode OLED. According to an embodiment, the seventh transistor T7may be omitted.

The first capacitor Cst may include a first lower electrode CE1and a first upper electrode CE2. The first lower electrode CE1may be connected to the gate electrode of the first transistor T1, and the first upper electrode CE2may be connected to the power voltage line PL. The first capacitor Cst may maintain a voltage applied to the gate electrode of the first transistor T1by storing and maintaining a voltage corresponding to a difference between voltages of two ends of the power voltage line PL and the gate electrode of the first transistor T1.

The second capacitor Cbt may include a second lower electrode CE3and a second upper electrode CE4. The second lower electrode CE3may be connected to the first scan line SL1and a gate electrode of the second transistor T2. The second upper electrode CE4may be connected to the gate electrode of the first transistor T1and the first lower electrode CE1of the first capacitor Cst. The second capacitor Cbt may be a boosting capacitor, and when the first scan signal Sn of the first scan line SL1is a voltage turning off the second transistor T2, the second capacitor Cbt may increase a voltage of a node N2to reduce a voltage displaying black (a black voltage).

The organic light-emitting diode OLED may include the pixel electrode (e.g., an anode) and an opposite electrode (e.g., a cathode), and the opposite electrode may receive a second power voltage ELVSS. The organic light-emitting diode OLED may receive the driving current IOLEDfrom the first transistor T1to emit light, thereby displaying an image.

An operation of each pixel PX according to an embodiment will be described in detail below.

During a first initialization period, when the third scan signal Sn−1 is supplied via the third scan line SL3, the fourth transistor T4is turned on in accordance with the third scan signal Sn−1, and the gate electrode of the first transistor T1is initialized by the first initialization voltage Vint1supplied from the first initialization voltage line VIL1.

During a data programming period, when the first scan signal Sn and the fourth scan signal Sn′ are respectively supplied via the first scan line SL1and the fourth scan line SL4, the second transistor T2and the third transistor T3are turned on in accordance with the first scan signal Sn and the fourth scan signal Sn′. Here, the first transistor T1is diode-connected by the turned-on third transistor T3and is biased in a forward direction. Then a voltage, for which a threshold voltage Vth of the first transistor T1is compensated for in the data signal DATA supplied from the data line DL, is applied to the gate electrode of the first transistor T1. The first power voltage ELVDD and a compensated voltage are applied to both ends of the first capacitor Cst, and a charge corresponding to a voltage difference between the both ends of the first capacitor Cst is stored in the first capacitor Cst.

During a light-emission period, the fifth transistor T5and the sixth transistor T6are turned on according to the emission control signal En supplied from the emission control line EL. The driving current IOLEDaccording to a voltage difference between a voltage of the gate electrode of the first transistor T1and the first power voltage ELVDD is generated, and the driving current IOLEDis supplied to the organic light-emitting diode OLED via the sixth transistor T6.

During a second initialization period, when the second scan signal Sn+1 is supplied via the second scan line SL2, the seventh transistor T7is turned on in accordance with the second scan signal Sn+1, and the anode (e.g., the pixel electrode) of the organic light-emitting diode OLED is initialized by the second initialization voltage Vint2supplied from the second initialization voltage line VIL2.

In an embodiment, at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7may include a semiconductor layer including an oxide, and the others may include a semiconductor layer including a silicon. In detail, a first transistor that directly affects a brightness of a display apparatus is configured to include a semiconductor layer including polycrystalline silicon having high reliability, and a high-resolution display apparatus may be implemented, accordingly.

Meanwhile, an oxide semiconductor has a high carrier mobility and a low leakage current, and thus a voltage drop thereof is not great despite a long driving time. That is, even at low-frequency driving, changes in colors of an image due to a voltage drop is not great, and thus low-frequency driving may be performed. As the oxide semiconductor has a small leakage current as described above, at least one of the third transistor T3and the fourth transistor T4, which is connected to the gate electrode of the first transistor T1, may be formed of an oxide semiconductor to prevent a leakage current that may flow to the gate electrode of the first transistor T1and also reduce power consumption.

FIG.3is a schematic layout diagram showing locations of a plurality or transistors and capacitors arranged in a pair of pixel circuits of a display apparatus according to an embodiment.FIG.4is a cross-sectional view schematically illustrating a display apparatus according to an embodiment.FIG.5is a cross-sectional view schematically illustrating a display apparatus according to an embodiment.FIGS.6,7,8, and9are layout diagrams showing components that form the plurality of transistors and the capacitors ofFIG.3, in each of layers.FIG.4corresponds to a cross-sectional view of the components ofFIG.3taken alone line I-I′ ofFIG.3, andFIG.5corresponds to a cross-sectional view of the components ofFIG.3taken along line II-II′ ofFIG.3.

InFIG.3, a pair of pixels PX arranged in adjacent columns and in a same row are illustrated. InFIG.3, a pixel circuit of a pixel arranged in a left pixel area CA1and a pixel circuit of a pixel arranged in a right pixel area CA2are bilaterally symmetrical.

Referring toFIG.3, the pixel circuit may include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the first capacitor Cst, and the second capacitor Cbt.

In an embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7may include a thin-film transistor including a silicon semiconductor. The third transistor T3and the fourth transistor T4may include a thin-film transistor including an oxide semiconductor.

Semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7may be arranged on a same layer and include a same material. For example, the semiconductor layer may include a polycrystalline silicon. The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7may be connected to each other and curved in various shapes.

Each of the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7may include a channel area and a source area and a drain area on two sides of the channel area. In an embodiment, the source area and the drain area may be doped with an impurity, and the impurity may include an N-type impurity or a P-type impurity. The source area and the drain area may respectively correspond to a source electrode and a drain electrode. The source area and the drain area may be exchanged according to properties of a transistor. Hereinafter, the terms, the ‘source area’ and the ‘drain area,’ will be used instead of the source electrode or the drain electrode.

The first transistor T1may include a first semiconductor layer AS1and a first gate electrode G1. The first semiconductor layer AS1may include a first channel area A1and a first source area S1and a first drain area D1on two sides of the first channel area A1. The first semiconductor layer has a curved shape such that the first channel area A1is longer than the other channel areas A2, A3, A4, A5, A6, and A7. For example, as the first semiconductor layer has a shape with multiple bends, such as ‘S,’ ‘M,’ ‘W,’ a relatively long channel length may be formed in a relatively small space. As the first channel area A1is relatively long, a driving range of a gate voltage applied to the first gate electrode G1is extended, thereby finely controlling gradation of light emitted from the organic light-emitting diode OLED and improving display quality. In an embodiment, the first semiconductor layer may have a linear shape instead of a bent shape. The first gate electrode G1is an island type and may overlap the first channel area A1with respect to a first gate insulating layer112(seeFIG.4) disposed therebetween.

The first capacitor Cst may be arranged to overlap the first transistor T1. The first capacitor Cst may include the first lower electrode CE1and the first upper electrode CE2. The first gate electrode G1may have a function not only as a control electrode with respect to the first transistor T1but also as the first lower electrode CE1of the first capacitor Cst. That is, the first gate electrode G1and the first lower electrode CE1may be formed integrally. In an embodiment, the first gate electrode G1and the first lower electrode CE1may be included as separate components and arranged apart from each other. The first upper electrode CE2of the first capacitor Cst may be included to overlap the first lower electrode CE1with a first interlayer insulating layer113(FIG.4) therebetween. The first interlayer insulating layer113may act as a dielectric layer of the first capacitor Cst.

The second transistor T2may include a second semiconductor layer and a second gate electrode G2. The second semiconductor layer may include a second channel area A2and a second source area S2and a second drain area D2on two sides of the second channel area A2. The second source area S2may be electrically connected to the data line DL (FIG.2) or the power voltage line PL (FIG.2), and the second drain area D2may be connected to the first source area S1. The second gate electrode G2may be included as a portion of the first scan line SL1(FIG.2).

The fifth transistor T5may include a fifth semiconductor layer and a fifth gate electrode G5. The fifth semiconductor layer may include a fifth channel area A5and a fifth source area S5and a fifth drain area D5on two sides of the fifth channel area A5. The fifth source area S5may be electrically connected to the data line DL (FIG.2) or the power voltage line PL (FIG.2), and the fifth drain area D5may be connected to the first source area S1. The fifth gate electrode G5may be included as a portion of the emission control line EL (FIG.2).

The sixth transistor T6may include a sixth semiconductor layer and a sixth gate electrode G6. The sixth semiconductor layer may include a sixth channel area A6and a sixth source area S6and a sixth drain area D6on two sides of the sixth channel area A6. The sixth source area S6may be connected to the first drain area D1, and the sixth drain area D6may be electrically connected to a pixel electrode310(FIG.12) of the organic light-emitting diode OLED. The sixth gate electrode G6may be included as a portion of the emission control line EL (FIG.7).

The seventh transistor T7may include a seventh semiconductor layer and a seventh gate electrode G7. The seventh semiconductor layer may include a seventh channel area A7and a seventh source area S7and a seventh drain area D7on two sides of the seventh channel area A7. The seventh source area S7may be electrically connected to the second initialization voltage line VIL2(FIG.2), and the seventh drain area D7may be connected to the sixth drain area D6. The seventh gate electrode G7may be included as a portion of the first scan line SL1(FIG.7).

The second gate insulating layer114(FIG.4) may be arranged on the first, second, and fifth through seventh transistors T1, T2, T5, T6, and T7including a silicon semiconductor. The third and fourth transistors T3and T4including an oxide semiconductor may be arranged on the first interlayer insulating layer113(FIG.4).

The semiconductor layers of the third transistor T3and the fourth transistor T4may be arranged on a same layer and may include a same material. For example, the semiconductor layers may be formed of an oxide semiconductor.

The semiconductor layers may include a channel area and a source area and a drain area on two sides of the channel area. In an embodiment, the source area and the drain area may be areas having a carrier density increased by plasma processing. The source area and the drain area may respectively correspond to a source electrode and a drain electrode. Hereinafter, the terms the ‘source area’ and the ‘drain area’ will be used instead of the source electrode or the drain electrode.

The third transistor T3may include a third semiconductor layer including an oxide semiconductor and a third gate electrode G3. The third semiconductor layer may include a third channel area A3and a third source area S3and a third drain area D3on two sides of the third channel area A3. The third source area S3may be electrically connected to the first gate electrode G1. Also, the third source area S3may be connected to a fourth drain area D4arranged on a same layer as the source area D3. The third drain area D3may be electrically connected to the first semiconductor layer AS1of the first transistor T1and the sixth semiconductor layer of the sixth transistor T6. The third gate electrode G3may be included as a portion of the fourth scan line SL4(FIG.9).

The fourth transistor T4may include a fourth semiconductor layer including an oxide semiconductor and a fourth gate electrode G4. The fourth semiconductor layer may include a fourth channel area A4and a fourth source area S4and the fourth drain area D4on two sides of the fourth channel area A4. The fourth source area S4may be electrically connected to the first initialization voltage line VIL1, and the fourth drain area D4may be electrically connected to the first gate electrode G1. The fourth gate electrode G4may be included as a portion of the third scan line SL3(FIG.9).

The second gate insulating layer114(FIGS.4and5) may be arranged between the third semiconductor layer and the third gate electrode G3and arranged between the fourth semiconductor layer and the fourth gate electrode G4to correspond to each channel area.

The second lower electrode CE3of the second capacitor Cbt may be included as a portion of the first scan line SL1(FIG.7) to be connected to the second gate electrode G2. The second upper electrode CE4of the second capacitor Cbt may be arranged to overlap the second lower electrode CE3, and may include an oxide semiconductor. The second upper electrode CE4may be arranged on the same layer as the third semiconductor layer of the third transistor T3and the fourth semiconductor layer of the fourth transistor T4, and may be an area between the third semiconductor layer and the fourth semiconductor layer. Alternatively, the second upper electrode CE4may extend from the fourth semiconductor layer. Alternatively, the second upper electrode CE4may extend from the third semiconductor layer.

A second interlayer insulating layer115(FIGS.4and5) may be arranged on either the third transistor T3or the fourth transistor T4including an oxide semiconductor.

Hereinafter, a structure of the display apparatus1according to an embodiment will be described in detail according to a stacking order by referring toFIGS.4and5.

FIGS.4and5illustrate cross-sections of the display apparatus1corresponding to the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the first capacitor Cst, and the second capacitor Cbt illustrated inFIG.3, and some elements may be omitted therein.

The substrate100may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the substrate100is flexible or bendable, the substrate100may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

The substrate100may have a single-layer or multi-layer structure of the material, and when substrate100has a multi-layer structure, an inorganic layer may be further included. For example, the substrate100may include a first base layer101, a first barrier layer103, a second base layer105, and a second barrier layer107. The first base layer101and the second base layer105may each include a polymer resin. The first base layer101and the second base layer105may include a transparent polymer resin. The first barrier layer103and the second barrier layer107may be barrier layers preventing penetration of external foreign substances, and may be a single-layer or multi-layer structure including an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx).

A buffer layer111may be arranged on the substrate100. The buffer layer111may have a function of increasing a level of flatness of an upper surface of the substrate100, and the buffer layer111may include an oxide layer such as silicon oxide (SiOx), and/or a nitride layer such as silicon nitride (SiNx), or a silicon oxynitride (SiON).

As illustrated inFIG.6, a semiconductor layer AS of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7may be arranged on the buffer layer111.

The semiconductor layer AS may include the first channel area A1, the first source area S1, and the first drain area D1, which are a first semiconductor layer AS1of the first transistor T1, the second channel area A2, the second source area S2, and the second drain area D2, which are a second semiconductor layer of the second transistor T2, and the fifth channel area A5, the fifth source area S5, and the fifth drain area D5, which are a fifth semiconductor layer AS5of the fifth transistor T5, the sixth channel area A6, the sixth source area S6, and the sixth drain area D6, which are a sixth semiconductor layer AS6of the sixth transistor T6, and the seventh channel area A7, the seventh source area S7, and the seventh drain area D7, which are a seventh semiconductor layer of the seventh transistor T7. That is, each channel area, each source area, and each drain area of the first through seventh transistor T1through T7may be portions of the semiconductor layer AS. InFIG.6, the semiconductor layer of the seventh transistor T7may be a portion of a semiconductor layer extended from a previous row.

The first gate insulating layer112may be disposed on the semiconductor layer AS. The first gate insulating layer112may include an inorganic material including an oxide or a nitride. For example, the first gate insulating layer112may include at least one of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

As illustrated inFIG.7, the first gate electrode G1of the first transistor T1, the second gate electrode G2of the second transistor T2, the fifth gate electrode G5of the fifth transistor T5, the sixth gate electrode G6of the sixth transistor T6, and the seventh gate electrode G7of the seventh transistor T7may be arranged on the first gate insulating layer112. Also, the first scan line SL1and the emission control line EL may extend and be arranged on the first gate insulating layer112in the first direction D1. A portion of the first scan line SL1may be the second lower electrode CE3of the second capacitor Cbt. Moreover, a first conductive layer121and a second conductive layer123that include a same material as that of the first, second, fifth, sixth, and seventh gate electrodes G1, G2, G5, G6, and G7of the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7may extend and be arranged on the first gate insulating layer112in the first direction D1. A portion of the first conductive layer121overlapping a third semiconductor layer AO3of the third transistor T3may be a lower gate electrode Ga3of the third transistor T3. A portion of the second conductive layer123overlapping a fourth semiconductor layer AO4of the fourth transistor T4may be a lower gate electrode Ga4of the fourth transistor T4.

The lower gate electrode Ga3of the third transistor T3may be arranged to overlap the third semiconductor layer AO3of the third transistor T3to protect the third semiconductor layer AO3of the third transistor T3. Also, the lower gate electrode Ga4of the fourth transistor T4may be arranged to overlap the fourth semiconductor layer AO4of the fourth transistor T4to protect the fourth semiconductor layer AO4of the fourth transistor T4.

The first gate electrode G1of the first transistor T1may have an island shape. That is, the first gate electrode G1of the first transistor T1is freely floating so that first gate electrode G1of the first transistor T1is not connected with fifth gate electrode G5of the fifth transistor T5or the first conductive layer121etc. The second gate electrode G2of the second transistor T2may be a portion of the first scan line SL1crossing the semiconductor layer AS. The seventh gate electrode G7of the seventh transistor T7may be a portion of the first scan line SL1crossing the semiconductor layer AS or a portion of the second scan line SL2(FIG.3) which is a first scan line of a next row. InFIG.7, an example in which the seventh gate electrode G7of the seventh transistor T7of a pixel arranged in a previous row is a portion of the first scan line SL1crossing the semiconductor layer AS is illustrated. The fifth gate electrode G5of the fifth transistor T5and the sixth gate electrode G6of the sixth transistor T6may be portions of the emission control line EL crossing the semiconductor layer AS.

The first gate electrode G1of the first transistor T1may have a function not only as a control electrode with respect to the first transistor T1but also the first lower electrode CE1of the first capacitor Cst.

The first, second, fifth, sixth, and seventh gate electrodes G1, G2, G5, G6, and G7of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7may include aluminum (Al), platinum (Pt), and palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be formed in a single-layer or multi-layer structure including one or more of the above materials.

According to an embodiment, the first conductive layer121and the second conductive layer123may include a same material as that of the first, second, fifth, sixth, and seventh gate electrodes G1, G2, G5, G6, and G7of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6, and the seventh transistor T7.

The first interlayer insulating layer113may be arranged on the first, second, fifth, sixth, and seventh gate electrodes G1, G2, G5, G6, and G7. The first interlayer insulating layer113may include an inorganic material including an oxide or a nitride. For example, the first interlayer insulating layer113may include at least one of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

As illustrated inFIG.8, a semiconductor layer AO including an oxide semiconductor may be arranged on the first interlayer insulating layer113. The semiconductor layer AO may include a Zn oxide-based material, and may include Zn oxide, In—Zn oxide, Ga—In—Zn oxide, or the like. According to an embodiment, the semiconductor layer AO may include an In—Ga—Zn—O (IGZO), In—Sn—Zn—O (ITZO) or In—Ga—Sn—Zn—O (IGTZO) semiconductor including a metal such as indium (In), gallium (Ga), and tin (Sn) in ZnO.

Each of the third semiconductor layer AO3of the third transistor T3and the fourth semiconductor layer AO4of the fourth transistor T4may include a channel area and a source area and a drain area which are disposed on both ends of the channel area. The source area and the drain area of the third transistor T3and the fourth transistor T4may be formed by imparting conductivity to an oxide semiconductor by adjusting a carrier concentration of the oxide semiconductor. For example, the source area and drain area of each of the third transistor T3and the fourth transistor T4may be formed by increasing a carrier concentration of an oxide by performing plasma treatment on the oxide semiconductor by using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

The semiconductor layer AO may include the third channel area A3, the third source area S3, and the third drain area D3, which are the third semiconductor layer AO3of the third transistor T3, and the fourth channel area A4, the fourth source area S4, and the fourth drain area D4, which are the fourth semiconductor layer AO4of the fourth transistor T4. That is, each channel area, each source area, and each drain area of the third transistor T3and the fourth transistor T4may be portions of the semiconductor layer AO.

The semiconductor layer AO may include the second upper electrode CE4of the second capacitor Cbt. The second upper electrode CE4of the second capacitor Cbt may be located between the third semiconductor layer AO3of the third transistor T3and the fourth semiconductor layer AO4of the fourth transistor T4on a plan view. The second upper electrode CE4may extend from the third semiconductor layer AO3of the third transistor T3or the fourth semiconductor layer AO4of the fourth transistor T4. That is, the second upper electrode CE4may include an oxide semiconductor and may be arranged on the first interlayer insulating layer113. The first interlayer insulating layer113may be arranged between the second lower electrode CE3and the second upper electrode CE4of the second capacitor Cbt, and the first interlayer insulating layer113may act as a dielectric layer of the second capacitor Cbt.

Further, the first upper electrode CE2may be arranged on the first interlayer insulating layer113to overlap the first lower electrode CE1. A plurality of openings SOP is defined in the first upper electrode CE2. The opening SOP may be formed by removing a portion of the first upper electrode CE2and may have a closed shape. In an example, the opening SOP may have a square shape. However, in other examples, the opening SOP may have different shapes such as s circle or triangle.

The first interlayer insulating layer113may act as a dielectric layer of the first capacitor Cst. The first upper electrodes CE2of adjacent pixels may be connected to each other by a bridge141. The bridge141may be a portion protruding from the first upper electrode CE2in the first direction D1and may be integrally formed with the first upper electrode CE2. That is, the bridge141is connectedly disposed between two first upper electrodes CE2.

According to an embodiment, the first upper electrode CE2may include a same material as the semiconductor layer AO. According to an embodiment, the first upper electrode CE2may be provided where a conductivity is imparted thereto by adjusting a carrier concentration of an oxide semiconductor. For example, the first upper electrode CE2may be formed by increasing a carrier concentration of an oxide semiconductor through plasma treatment using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof on the oxide semiconductor.

The second gate insulating layer114may be arranged above the semiconductor layer AO and the first upper electrode CE2. The second gate insulating layer114may include an inorganic material including an oxide or a nitride. For example, the second gate insulating layer114may include at least one of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

As illustrated inFIG.9, the first initialization voltage line VIL1, the third scan line SL3, and the fourth scan line SL4may be arranged on the second gate insulating layer114. A portion of the third scan line SL3overlapping the semiconductor layer AO may be an upper gate electrode Gb3of the third transistor T3. A portion of the fourth scan line SL4overlapping the semiconductor layer AO may be an upper gate electrode Gb4of the fourth transistor T4. That is, the third transistor T3and the fourth transistor T4may have a double gate structure including control electrodes on and below the semiconductor layer, respectively.

The upper gate electrode Gb3of the third transistor T3and the upper gate electrode Gb4of the fourth transistor T4may be arranged on the second gate insulating layer114, and may have a single-layer or multi-layer structure including at least one of molybdenum (Mo), copper (Cu), titanium (Ti), and the like.

The second interlayer insulating layer115may be arranged to cover the third transistor T3and the fourth transistor T4. The second interlayer insulating layer115may be arranged on the upper gate electrode Gb3of the third transistor T3and the upper gate electrode Gb4of the fourth transistor T4.

The second interlayer insulating layer115may include an inorganic material including an oxide or a nitride. For example, the second interlayer insulating layer115may include at least one of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

FIG.10is a cross-sectional view schematically illustrating a display apparatus according to an embodiment.FIG.10is a schematic cross-sectional view of the display apparatus taken along line II′ ofFIG.3. The embodiment ofFIG.10is different from the embodiment ofFIG.4in that the second gate insulating layer114is patterned in a form corresponding to electrodes arranged thereon. InFIG.10, like reference numerals as those ofFIG.4denote like components, and thus, repeated description thereof will be omitted.

Referring toFIGS.8,9, and10, in an embodiment, the third scan line SL3and the fourth scan line SL4may be arranged to at least partially overlap the semiconductor layer AO.

The second gate insulating layer114may be arranged between the third scan line SL3and the fourth scan line SL4and the semiconductor layer AO. The second gate insulating layer114may be patterned in a shape corresponding to the third scan line SL3and the fourth scan line SL4arranged thereon.

According to an embodiment, the second gate insulating layer114may be patterned in a shape corresponding to the upper gate electrode Gb3of the third transistor T3. In addition, the second gate insulating layer114may be patterned in a shape corresponding to the upper gate electrode Gb4of the fourth transistor T4.

FIG.11is a cross-sectional view schematically illustrating a display apparatus according to an embodiment.FIG.11is a schematic cross-sectional view of the display apparatus taken along line I-I′ ofFIG.3. The embodiment ofFIG.11is different from the embodiment ofFIG.4in that a first electrode250is further arranged on the second gate insulating layer114, and the first upper electrode CE2and the first electrode250are electrically connected to each other via a second electrode260arranged on the second interlayer insulating layer115. InFIG.11, like reference numerals as those ofFIG.4denote like components, and thus, repeated description thereof will be omitted.

Referring toFIGS.8,9, and11, the first initialization voltage line VIL1, the third scan line SL3, and the fourth scan line SL4may be arranged on the second gate insulating layer114.

A portion of the third scan line SL3overlapping the semiconductor layer AO may be the upper gate electrode Gb3of the third transistor T3. A portion of the fourth scan line SL4overlapping the semiconductor layer AO may be the upper gate electrode Gb4of the fourth transistor T4. That is, the third transistor T3and the fourth transistor T4may have a double gate structure including control electrodes on and below the semiconductor layer, respectively.

The upper gate electrode Gb3of the third transistor T3and the upper gate electrode Gb4of the fourth transistor T4may be arranged on the second gate insulating layer114, and may have a single-layer or multi-layer structure including at least one of molybdenum (Mo), copper (Cu), titanium (Ti), and the like.

In addition, the first electrode250may be arranged on the second gate insulating layer114. The first electrode250may include the same material as those of the upper gate electrode Gb3of the third transistor T3and the upper gate electrode Gb4of the fourth transistor T4.

The second interlayer insulating layer115may be arranged on the upper gate electrode Gb3of the third transistor T3, the upper gate electrode Gb4of the fourth transistor T4, and the first electrode250. The second electrode260may be arranged on the second interlayer insulating layer115.

The second electrode260may have a single-layer or multi-layer structure including at least one of aluminum (Al), copper (Cu), and titanium (Ti), or the like. According to an embodiment, the second electrode260may be provided as a triple layer of titanium, aluminum, and titanium (Ti/Al/Ti) that are sequentially arranged.

An end of the second electrode260may be electrically connected to the first upper electrode CE2of the first capacitor Cst through a contact hole261formed in the second gate insulating layer114and the second interlayer insulating layer115. In addition, the other end of the second electrode260may be electrically connected to the first electrode250through a contact hole263formed in the second interlayer insulating layer115.

When a length of the first upper electrode CE2used as the first upper electrode CE2of the first capacitor Cst increases, a resistance of the first upper electrode CE2may increase. In addition, when the first upper electrode CE2includes an oxide semiconductor, to which conductivity is imparted, a resistance of the first upper electrode CE2may increase compared to when the first upper electrode CE2includes a metal material such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu).

According to an embodiment, by connecting the first electrode250including a material having high conductivity, to the first upper electrode CE2, the resistance of the first upper electrode CE2may be reduced.

FIG.12is a cross-sectional view schematically illustrating a display apparatus according to an embodiment.FIG.12is a schematic cross-sectional view of the display apparatus taken along line I-I′ ofFIG.3. In detail,FIG.12is a diagram for describing a stack structure on the second interlayer insulating layer115. InFIG.12, like reference numerals as those ofFIG.4denote like components, and thus, repeated description thereof will be omitted.

Referring toFIG.12, a third conductive layer280may be arranged on the second interlayer insulating layer115and may be in direct contact with the second interlayer insulating layer115. The third conductive layer280may be at least one of the power voltage line PL (FIG.2), the data line DL (FIG.2), a node connection line, and a connection electrode. The third conductive layer280may have a single-layer or multi-layer structure including at least one of aluminum (Al), copper (Cu), and titanium (Ti), or the like. For example, the third conductive layer280may include a triple layer of titanium, aluminum, and titanium (Ti/Al/Ti) that are sequentially arranged.

A first planarization layer118may be arranged on the third conductive layer280. A fourth conductive layer290may be arranged on the first planarization layer118and may be in direct contact with the first planarization layer118. The fourth conductive layer290may be at least one of the power voltage line PL (FIG.2), the data line DL (FIG.2), a node connection line, and a connection electrode.

According to an embodiment, the data line DL (FIG.2) may be arranged on the second interlayer insulating layer115, and the power voltage line PL (FIG.2) may be arranged on the first planarization layer118. According to an embodiment, the power voltage line PL (FIG.2) may be arranged on the second interlayer insulating layer115and the data line DL (FIG.2) may be arranged on the first planarization layer118.

A second planarization layer119may be arranged on the fourth conductive layer290. The first planarization layer118and the second planarization layer119may include an organic material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Alternatively, the first planarization layer118and the second planarization layer119may include an inorganic material. The first planarization layer118and the second planarization layer119may act as a protective layer covering the first through seventh transistors T1, T2, T3, T4, T5, T6, and T7, and upper portions of the first planarization layer118and the second planarization layer119may be flattened. The first planarization layer118and the second planarization layer119may be provided as a single layer or multiple layers.

An organic light-emitting diode OLED may be arranged on the second planarization layer119. The organic light-emitting diode OLED may include the pixel electrode310, an intermediate layer320, and an opposite electrode330.

The pixel electrode310may be arranged on the second planarization layer119and may be in direct contact with the second planarization layer119. The pixel electrode310may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode310may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. For example, the pixel electrode310may have a structure having layers including ITO, IZO, ZnO, or In2O3above or below the above-described reflective layer. In this case, the pixel electrode310may have a structure in which indium tin oxide (ITO)/silver (Ag)/indium tin oxide (ITO) are sequentially stacked.

A pixel defining layer120may be arranged on the second planarization layer119. An opening corresponding to each pixel is defined in the pixel defining layer120. That is, an opening, through which at least a portion of the pixel electrode310is exposed, thereby defining a pixel. In addition, the pixel defining layer120may increase a distance between an edge of the pixel electrode310and the opposite electrode330above the pixel electrode310to thereby perform a function of preventing an arc or the like at the edge of the pixel electrode310. The pixel defining layer120may include an organic material such as polyimide or HMDSO.

The intermediate layer320of the organic light-emitting diode OLED may include a low molecular weight organic material or a polymer organic material. When the intermediate layer320includes a low molecular weight organic material, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), or the like may be stacked in a single or complex structure, and the intermediate layer320may include various organic materials including copper phthalocyanine (CuPc), N,N-di(naphthalen-1-yl)-N,N′-di Phenyl-benzidine (N,N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine (NPB), tris-8-hydroxyquinoline aluminum (Alq3), or the like. These layers may be formed using a vacuum evaporation method.

When the intermediate layer320includes a polymer organic material, it may have a structure including an HTL and an EML. The HTL may include PEDOT, and the EML may include a polymer material such as poly-phenylvinylene (PPV)-based material and polyfluorene-based material. The intermediate layer320may be formed by screen printing, inkjet printing, laser induced thermal imaging (LITI), or the like.

The intermediate layer320, however, is not necessarily limited thereto, and may have other various structures. In addition, the intermediate layer320may include a layer that is integrally formed over the plurality of pixel electrodes310, or may include a layer patterned to correspond to each of the plurality of pixel electrodes310.

The opposite electrode330may be formed integrally with respect to a plurality of organic light-emitting diodes to correspond to the plurality of pixel electrodes310.

As the organic light-emitting diode OLED is likely damaged by moisture or oxygen from the outside, an encapsulation layer (not shown) or a sealing substrate (not shown) may be arranged on the organic light-emitting diode OLED to protect the organic light-emitting diode OLED. The encapsulation layer (not shown) may cover the display area DA and extend beyond the display area DA. The encapsulation layer may include an inorganic film layer including at least one inorganic material and an organic film layer including at least one organic material. According to an embodiment, a thin-film encapsulation layer may be provided in a structure in which a first inorganic film layer, an organic film layer, and a second inorganic film layer are sequentially stacked. The sealing substrate (not shown) may be arranged to face the substrate100and bonded to the substrate100by using a sealing member such as a sealant or frit in the peripheral area PA.

In addition, a spacer (not shown) for preventing mask imprinting may be further included on the pixel defining layer120, and various functional layers such as a polarizing layer, a black matrix, a color filter that are used to reduce external light reflection, and/or a touch screen layer including a touch electrode may be provided on the encapsulation layer.

According to an embodiment, a lower gate electrode of a second thin-film transistor including an oxide semiconductor, is arranged on a same layer as a gate electrode of a first thin-film transistor including a silicon semiconductor, and an upper electrode of a capacitor includes an oxide semiconductor, to which conductivity is imparted. Accordingly, the manufacturing costs of a display apparatus may be reduced as a number of insulating layers and lines and thus a number of masks used in a process are reduced, and also, a number of operations of the manufacturing process of the display apparatus and a process defect ratio may be reduced, accordingly.

According to an embodiment, by electrically connecting a first electrode including a material having a high conductivity, to an upper electrode including an oxide semiconductor, a resistance of the upper electrode may be reduced.

According to the embodiment as described above, as a driving circuit driving a display element is configured to include a first thin-film transistor including a silicon semiconductor and a second thin-film transistor including an oxide semiconductor, a high-resolution display apparatus with low power consumption may be provided.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.