Patent ID: 12237378

DESCRIPTION OF EMBODIMENTS

The present invention is a method for producing a SiC substrate. The term “SiC substrate” as used herein broadly includes, in addition to a so-called “SiC wafer” after being cut out from an ingot, a “SiC single crystal seed substrate” used for producing a SiC ingot, and a “SiC single crystal basesubstrate” which is a SiC single crystal substrate in a state before a “SiC single crystal seed substrate” to be used in an ingot forming step.

The present invention will be described below separately for an embodiment for producing a “SiC wafer” and an embodiment for producing a “SiC single crystal seed substrate”.

[Production Method of SiC Wafer]

A method for producing a SiC wafer of the present invention will be described in more detail with reference toFIG.1. The drawing illustrates a preferred embodiment. However, the method can be performed in many different embodiments and is not limited to the embodiments described herein.

In understanding the present invention, it is recognized that it is useful to compare with a conventional production step of a SiC wafer. Therefore, each step in the method for producing a SiC wafer of the present invention will be described with reference toFIG.11as appropriate, while comparing with each step in the conventional method for producing a SiC wafer.

For SiC single crystals, which are the base of SiC semiconductors, ingots, which are lumps of crystals, are artificially made by sublimating raw materials at a high temperature of equal to or higher than 2000° C. The material properties of SiC single crystals are considered to be the second hardest after diamond and boron carbide, and SiC single crystals have high hardness, chemical and thermal stability enough to be used as abrasives, and have crystal orientation and direction. Therefore, SiC single crystals are materials that are extremely difficult to process having the cleavage peculiar to fragile (brittle) materials.

In conventional methods, in order to form a semiconductor on the surface of the material, a planarization step S20is performed after cutting out a SiC wafer from a single crystal ingot by a slicing step S1. In conventional methods, as the planarization step S20, typically, a lapping step S21for planarizing waviness, a rough grinding step S22and a finish grinding step S23for removing the subsurface damaged layer11are performed (FIG.11).

In general, the SiC wafer that has been subjected to the planarization step S20is then subjected to a chemical mechanical polishing step S41, that is, chemical mechanical polishing (CMP), which can finally achieve strain-free processing (FIG.11).

FIG.1illustrates an outline of the method for producing a SiC wafer of the present invention. As illustrated inFIG.1, in the method for producing a SiC wafer of the present invention, after the planarization step is performed until a predetermined surface roughness is obtained, or after a planarization step is performed using an abrasive grain having a predetermined grain size or less, an etching step S31is performed.

Since such a configuration is adopted, it is not necessary to perform all the series of steps of the lapping step S21, the rough grinding step S22, and the finish grinding step S23in the present invention (right side inFIG.1).

For example, if a SiC wafer having a predetermined surface roughness can be obtained by the lapping step S21, then the etching step S31may be performed without performing the rough grinding step S22and the finish grinding step S23.

Of course, the etching step S31may be performed after all the series of steps of the lapping step S21, the rough grinding step S22, and the finish grinding step S23are performed.

Regardless of the type of processing step performed on the SiC wafer, the etching step S31may be simply performed on the SiC wafer having a predetermined surface roughness.

The SiC substrate to which the present invention can be applied includes, without limitation, those having an off-angle and those having no off-angle.

The present invention can be applied without limitation regardless of whether the SiC substrate is a polymorph of crystals such as 4H-SiC, 6H-SiC, and 3C-SiC.

A main surface (the surface to be processed) of the SiC substrate to which the present invention is applied may be a Si surface (0001) surface or a C surface (000-1) surface.

FIG.12is a conceptual diagram when a surface of a machined wafer is observed from a cross section. In general, on the surface of the SiC wafer10that has been subjected to machining as in the conventional method, an subsurface damaged layer11including a crack layer111having a large number of cracks (scratches) and a strain layer112in which strain is generated in a crystal lattice remain.

In order not to reduce the yield in the device production step, it is necessary to remove this subsurface damaged layer11. That is, it is preferable to expose a bulk layer12under the subsurface damaged layer11in which cracks and lattice strain due to surface processing are not introduced.

According to the method for producing a SiC wafer of the present invention, the bulk layer12to which cracks and lattice strain have not been introduced can be exposed by removing the subsurface damaged layer11by thermal etching.

Hereinafter, the method for producing a SiC wafer of the present invention will be described according to the steps of one embodiment.

<1> Slicing Step S1

The slicing step S1is a step of cutting out a SiC wafer from a SiC ingot. Examples of slicing means of the slicing step S1include a multi-wire saw cutting of cutting the ingot at predetermined intervals by reciprocating a plurality of wires, an electric discharge machining method of cutting by intermittently generating a plasma discharge, and cutting using a laser that emits and condenses a laser beam in the ingot to form a layer serving as a base point for cutting.

<2> Planarization Step S20

As illustrated inFIG.1, the planarization step S20in the present invention includes an aspect of planarization to a predetermined roughness or less and an aspect of planarization using an abrasive grain having a predetermined grain size or less. These aspects are correlated with each other.

First, description will be given about a mode of planarization using an abrasive grain.

(1) Mode of Planarization Using Abrasive Grain

Examples of the abrasive grain include diamond, boron carbide (B4C), silicon carbide (SiC), and alumina (Al2O3).

Examples of planarization means of the planarization step S20include a loose abrasive grain method (lapping polishing or the like) of processing while pouring fine abrasive grains on a surface plate, or a fixed abrasive grain method of processing with an abrasive stone with abrasive grains embedded in a bond material (grind grinding or the like).

Examples of a case of the fixed abrasive grain method is adopted include rough grinding and finish grinding using a diamond abrasive grain.

When the loose abrasive grain method is adopted, it is desirable that the abrasive grain is dropped as a mixed liquid (slurry) mixed with water or a dispersant.

As the processing apparatus used in this step, a general-purpose processing apparatus used in a conventional loose abrasive grain method can be adopted.

The average abrasive grain size of the abrasive grain used in the planarization step S20is preferably equal to or less than 10 μm, more preferably equal to or less than 9 μm, more preferably equal to or less than 8 μm, more preferably equal to or less than 7 μm, more preferably equal to or less than 6 μm, and more preferably equal to or less than 5 μm, more preferably equal to or less than 4 μm, more preferably equal to or less than 3 μm, still more preferably equal to or less than 2 μm, still more preferably equal to or less than 1 μm, still more preferably equal to or less than 0.8 μm, still more preferably equal to or less than 0.6 μm, still more preferably equal to or less than 0.5 μm, still more preferably equal to or less than 0.4 μm, and still more preferably equal to or less than 0.3 μm.

By performing the planarization step S320using the abrasive grain having the average abrasive grain size in the above numerical range and performing the etching step S31, it is possible to obtain a SiC wafer having a surface in which strain is removed and that is as flat as the surface that has been subjected to the chemical mechanical polishing step S41.

In particular, by performing the planarization step S20using an abrasive grain having an average abrasive grain size of equal to or less than 0.5 μm and performing the etching step S31, a SiC wafer having an extremely flat surface can be produced. Such an embodiment is also applicable to mass production processes.

There is no limit for the size of the SiC substrate to which the present invention can be applied. The present invention can be applied to a SiC substrate of preferably equal to or greater than two inches, more preferably equal to or greater than four inches.

When the surface of a SiC wafer is ground and flattened using an abrasive grain, there is a problem that the flatness varies depending on the grinding position on the same wafer. This problem is remarkable, for example, when planarizing a SiC wafer having a large diameter of equal to or greater than six inches.

According to the SiC wafer of the present invention, by the etching step S31in the succeeding step, the variation in flatness caused by the planarization step S20using an abrasive grain can be corrected.

That is, the present invention is preferable when processing a SiC wafer having a large diameter of equal to or greater than six inches, more preferably equal to or greater than eight inches.

In the description in this specification, the average abrasive grain size means the average grain size according to Japanese Industrial Standards (JIS) R6001-2: 2017.

(2) Mode of Performing Planarization Until Surface Becomes Predetermined Rough or Less

In the planarization step S20, the planarization step S20is performed so that the arithmetic average roughness (Ra) is preferably equal to or less than 100 nm, more preferably equal to or less than 90 nm, more preferably equal to or less than 80 nm, more preferably equal to or less than 70 nm, more preferably equal to or less than 60 nm, more preferably equal to or less than 50 nm, more preferably equal to or less than 45 nm, more preferably equal to or less than 40 nm, more preferably equal to or less than 35 nm, more preferably equal to or less than 30 nm, more preferably equal to or less than 25 nm, more preferably equal to or less than 20 nm, more preferably equal to or less than 18 nm, more preferably equal to or less than 15 nm, more preferably equal to or less than 12 nm, more preferably equal to or less than 10 nm, more preferably equal to or less than 9 nm, more preferably equal to or less than 8 nm, more preferably equal to or less than 7 nm, more preferably equal to or less than 6 nm, more preferably equal to or less than 5 nm, more preferably equal to or less than 4 nm, more preferably equal to or less than 3 nm, still more preferably equal to or less than 2 nm, still more preferably equal to or less than 1.5 nm, and still more preferably equal to or less than 1 nm.

By performing the planarization step S20as to achieve the surface roughness in the above numerical range and performing the etching step S31, it is possible to obtain a SiC wafer having a surface in which strain is removed and that is as flat as the surface that has been subjected to the chemical mechanical polishing step S41.

In particular, by performing the planarization step S20so that the arithmetic average roughness (Ra) is 2 nm or less and performing the etching step S31, a SiC wafer having an extremely flat surface can be manufactured. Such an embodiment is also applicable to mass production processes.

In the description of the present specification, the arithmetic average roughness (Ra) is arithmetic average roughness based on Japanese Industrial Standards (JIS) B0601-2001. The arithmetic average roughness (Ra) of the surface of the SiC substrate can be measured by an atomic force microscope (AFM) or a laser microscope.

In the present specification, the term “arithmetic average roughness (Ra)” as used in this specification refers to the arithmetic average roughness (Ra) measured by AFM.

In the planarization step S20, as a means for achieving the surface roughness in the above numerical range on the surface of the SiC wafer, preferably, the above-mentioned method using an abrasive grain having a predetermined average abrasive grain size can be mentioned.

In addition to the mode using an abrasive grain, the planarization step S20may be performed by various types of etching. Preferable examples of the planarization step S20by etching include Si vapor pressure etching.

<3> Cleaning Step S51

As illustrated inFIG.1, it is preferable to perform the cleaning step S51after the planarization step S20. By removing organic matter contamination and particle contamination, removing an oxide layer, removing ion contamination, and the like by the cleaning step S51before the etching step S31, it is possible to suppress the occurrence of abnormal etching, and contamination in the etching furnace can be prevented.

Examples of a specific method of the cleaning step S51include RCA cleaning.

<4> Etching Step S31

The etching step S31is a step of etching the SiC wafer that has been subjected to the above-mentioned planarization step S20.

A SiC wafer that has not been subjected to the planarization step S20but has a surface roughness in the above-mentioned numerical range may be subjected to the etching step S31. For example, when the surface roughness of the SiC wafer obtained by the slicing step S1is within the above-mentioned numerical range, the etching step S31may be performed after the slicing step S1without the planarization step S20.

The etching step S31is a step of etching a SiC wafer in an atmosphere containing Si element and C element.

More specifically, the etching step S31is a step of arranging the SiC wafer10and the SiC material so as to face each other, performing heating, and transporting the Si element and the C element from the SiC wafer10to the SiC material to etch the SiC wafer10.

The SiC material is composed of SiC that can receive Si element and C element from the SiC wafer10by heating the SiC material so as to face the SiC wafer10. Examples include a container made of SiC and a substrate made of SiC (SiC member). As the crystal polymorph of SiC material, any polytype can be adopted, and polycrystalline SiC may be adopted.

As a preferred embodiment, a mode in which the main container20capable of accommodating the SiC wafer10and configured to act as a SiC material by itself will be described below.

First, an apparatus configuration capable of achieving the etching step S31will be described.

As illustrated inFIG.2, the etching apparatus for the etching step S31includes: a main container20that can accommodate the SiC wafer10, and generates a vapor pressure of a gas phase species containing Si element and a gas phase species containing C element in an internal space by heating; and a heating furnace30that accommodates the main container20, generates the vapor pressure of the gas phase species containing Si element in the internal space, and performs heating so as to form a temperature gradient.

The main container20has an etching space X1formed by causing a part of the main container20arranged on the low temperature side of the temperature gradient and the SiC wafer10face each other in a state where the SiC wafer10is arranged on the high temperature side of the temperature gradient.

In the description in the present specification, the surface of the SiC wafer10on which the semiconductor element will be formed (specifically, the surface on which the epitaxial layer will be deposited) is referred to as a main surface101, and the surface facing the main surface101is referred to as a rear surface102. The main surface101and the rear surface102are collectively referred to as a front surface, and the direction of penetrating the main surface101and the rear surface102is referred to as a front and back direction.

Examples of the main surface101include a surface having an off angle of several degrees (for example, 0.4 to 8°) from the (0001) surface or the (000-1) surface. (In this specification, in the notation of the Miller index, “-” means the bar attached to the index immediately after that).

It is sufficient that the main container20has a configuration in which the SiC wafer10can be accommodated, and a vapor pressure of the gas phase species containing the Si element and the gas phase species containing the C element is generated in the internal space at the time of the heat treatment of the main container20. For example, the main container20is made of a material containing polycrystalline SiC. In the present embodiment, the entire main container20is made of polycrystalline SiC. By heating the main container20made of such a material, the vapor pressure of the gas phase species containing Si element and the gas phase species containing C element can be generated.

That is, it is desirable that the environment inside the heat-treated main container20is a vapor pressure environment of a mixed system of gas phase species containing Si element and gas phase species containing C element. Examples of the gas phase species containing the Si element include Si, Si2, Si3, Si2C, SiC2, and SiC. Examples of the gas phase species containing the C element include Si2C, SiC2, SiC, and C. That is, the SiC gas exists in the main container20.

A configuration can be adopted as long as the configuration generates a vapor pressure of the gas phase species containing the Si element and the gas phase species containing the C element in the internal space at the time of the heat treatment of the main container20. For example, a configuration in which the polycrystalline SiC is exposed on a part of the inner surface, or a configuration in which the polycrystalline SiC is separately arranged in the main container20can be noted.

As illustrated inFIG.3, the main container20is a fitting container including an upper container21and a lower container22that can be fitted to each other. A minute gap23is formed in a fitting portion between the upper container21and the lower container22, and the main container20is configured so that air exhausting (evacuation) in the main container20can be performed from this gap23.

With such a configuration, it is preferable that a semi-closed space is formed inside the main container20. The “semi-closed space” in the present specification refers to a space in which at least part of steam generated in the container can be confined, although the inside of the container can be evacuated.

The main container20has an etching space X1formed by causing a part of the main container20arranged on the low temperature side of the temperature gradient and the SiC wafer10face each other in a state where the SiC wafer10is arranged on the high temperature side of the temperature gradient. That is, at least a part of the main container20(for example, the bottom surface of the lower container22) has a temperature lower than that of the SiC wafer10due to the temperature gradient provided in the heating furnace30, and thereby, an etching space X1is formed.

The etching space X1is a space for transporting the Si atom and the C atom on the surface of the SiC wafer10to the main container20by using a temperature difference provided between the SiC wafer10and the main container20as a driving force.

For example, the SiC wafer10is arranged so that, when the temperature on the main surface101(or the rear surface102) of the SiC wafer10and the temperature on the bottom surface of the lower container22facing the main surface101are compared, the temperature on the side of the main surface101is higher and the temperature on the side of the bottom surface of the lower container22is lower (seeFIG.4). As described above, by forming a space (etching space X1) with a temperature difference between the main surface101and the bottom surface of the lower container22, the Si atom and C atom of the main surface101can be transported to the bottom surface of the lower container22by using the temperature difference as a driving force.

The main container20may have a substrate holder24provided between the SiC wafer10and the main container20.

The heating furnace30according to the present embodiment has a configuration of performing heating so as to form a temperature gradient such that the temperature decreases from the upper container21to the lower container22of the main container20. Therefore, the substrate holder24capable of holding the SiC wafer10can be provided between the SiC wafer10and the lower container22to form the etching space X1between the SiC wafer10and the lower container22.

It is sufficient that the substrate holder24has a configuration in which at least a part of the SiC wafer10can be held in a hollow of the main container20. For example, any conventional support means such as one-point support, three-point support, a configuration for supporting the outer peripheral edge, or a configuration for sandwiching a part thereof can be naturally adopted. As the material of the substrate holder24, a SiC material or a high melting pointmetal material can be adopted.

The substrate holder24may not be provided depending on the direction of the temperature gradient of the heating furnace30. For example, when the heating furnace30forms a temperature gradient so that the temperature decreases from the lower container22toward the upper container21, the SiC wafer10may be arranged on the bottom surface of the lower container22(without providing the substrate holder24).

As illustrated inFIG.2, the heating furnace30includes: a main heating chamber31capable of heating an object to be treated (SiC wafer10or the like) to a temperature of equal to or higher than 1000° C. and equal to or less than 2300° C.; a preheating chamber32capable of preheating the object to be treated to a temperature of equal to or higher than 500° C.; a refractory container40capable of accommodating the main container20; and moving means33(moving table) capable of moving the refractory container40from the preheating chamber32to the main heating chamber31.

The main heating chamber31is formed in a regular hexagonal shape in a plan sectional view, and the refractory container40is arranged inside the heating chamber31.

A heater34(mesh heater) is provided inside the main heating chamber31. A multilayer heat-reflecting metal plate is fixed to a side wall and ceiling of the main heating chamber31(not illustrated). This multilayer heat-reflecting metal plate is configured to reflect the heat of the heater34toward a substantially central portion of the main heating chamber31.

As a result, in the main heating chamber31, the heater34is arranged so as to surround the refractory container40accommodating the object to be treated, and further, the multilayer heat-reflecting metal plate is arranged outside the heater34, so that the temperature can be raised to equal to or higher than 1000° C. and equal to or less than 2300° C.

As the heater34, for example, a resistance heating type heater or a high frequency induction heating type heater can be used.

As a configuration of the heater34, a configuration capable of forming a temperature gradient in the refractory container40may be adopted. For example, the heater34may be configured so that many heaters are arranged on the upper side (or the lower side). Further, the heater34may be configured so that the width increases toward the upper side (or the lower side). Alternatively, the heater34may be configured so that the electric power supplied can be increased toward the upper side (or the lower side).

To the main heating chamber31, a vacuum forming valve35that performs air exhausting in the main heating chamber31, an inert gas injection valve36that introduces an inert gas into the main heating chamber31, a vacuum gauge37that measures the degree of vacuum in the main heating chamber31are connected.

The vacuum forming valve35is connected to an evacuation pump that exhausts and evacuates the inside of the main heating chamber31(not illustrated). With the vacuum forming valve35and the evacuation pump, the degree of vacuum in the main heating chamber31can be adjusted to, for example, equal to or less than 10 Pa, more preferably equal to or less than 1 Pa, still more preferably equal to or less than 10−3Pa. Examples of this evacuation pump include a turbomolecular pump.

The inert gas injection valve36is connected to an inert gas supply source (not illustrated). With the inert gas injection valve36and the inert gas supply source, inert gas can be introduced into the main heating chamber31in the range of 10−5to 10000 Pa. As this inert gas, Ar, He, N2and the like can be selected.

The preheating chamber32is connected to the main heating chamber31, and is configured so the refractory container40can be moved by the moving means33. The preheating chamber32of the present embodiment is configured so that the temperature can be raised by the residual heat of the heater34of the main heating chamber31. For example, when the temperature of the main heating chamber31is raised to 2000° C., the temperature of the preheating chamber32is raised to about 1000° C., and the object to be treated (SiC wafer10, main container20, refractory container40, or the like) can be degassed.

The moving means33is configured to be movable between the main heating chamber31and the preheating chamber32on which the refractory container40is placed. Since the transportation between the main heating chamber31and the preheating chamber32by the moving means33is completed in about one minute at the shortest, it is possible to raise or lower the temperature at 1 to 1000° C./min.

As described above, since the temperature can rapidly raises and lowered, it is possible to observe a surface shape that does not have a history of low-temperature growth during raising and lowering, which is difficult with conventional apparatuses.

InFIG.2, the preheating chamber32is arranged below the main heating chamber31, but the present invention is not limited to this, and the preheating chamber32may be arranged in any direction.

The moving means33according to the present embodiment is a moving table on which the refractory container40is placed. A small amount of heat is released from the contact portion between the moving table and the high melting point40. As a result, a temperature gradient can be formed in the refractory container40.

In the heating furnace30of the present embodiment, since the bottom of the refractory container40is in contact with the moving table, a temperature gradient is provided so that the temperature decreases from the upper container41to the lower container42of the refractory container40.

The direction of this temperature gradient can be set to any direction by changing the position of the contact portion between the moving table and the refractory container40. For example, when a hanging type or the like is adopted for the moving table and the contact portion is provided on the ceiling of the refractory container40, heat escapes upward. Therefore, the temperature gradient is provided so that the temperature rises from the upper container41to the lower container42of the refractory container40. It is desirable that this temperature gradient is formed along the front and back direction of the SiC wafer10.

As described above, a temperature gradient may be formed depending on the configuration of the heater34.

The vapor pressure environment of the gas phase species containing the Si element in the heating furnace30according to the present embodiment is formed by using the refractory container40and the Si vapor supply source44. For example, any method capable of forming an environment of a vapor pressure of gas phase species containing a Si element around the main container20can be adopted in the etching apparatus.

The refractory container40includes a high melting point material. Examples of such refractory material include C that is a general-purpose heat-resistant member, W, Re, Os, Ta, and Mo that are high melting point metals, Ta9C8, HfC, TaC, NbC, ZrC, Ta2C, TiC, WC, and MoC that are carbides, HfN, TaN, BN, Ta2N, ZrN, and TiN that are nitrides, and HfB2, TaB2, ZrB2, NB2, TiB2, and polycrystalline SiC that are borides.

As similar to the main container20, the refractory container40is a fitting container including an upper container41and a lower container42that can be fitted to each other, and is configured to be able to accommodate the main container20. A minute gap43is formed in the fitting portion between the upper container41and the lower container42, and is configured so that air exhausting (evacuation) in the refractory container40from this gap43.

The refractory container40has a Si vapor supply source44capable of supplying a vapor pressure of gas phase species containing a Si element in the refractory container40. The Si vapor supply source44may be configured to generate Si vapor in the refractory container40during heat treatment, and examples thereof include solid Si (a single crystal Si piece or a Si pellet of Si powder or the like) and a Si compound.

In the etching apparatus, TaC is used as the material of the refractory container40, and tantalum silicide is used as the Si vapor supply source44. That is, as illustrated inFIG.3, a tantalum silicide layer is formed inside the refractory container40, and a configuration is adopted in which a vapor pressure of a gas phase species containing Si element is supplied from the tantalum silicide layer into the container during heat treatment, thereby forming the Si vapor pressure environment.

In addition to this, any configuration can be adopted as long as a vapor pressure of a gas phase species containing Si element is formed in the refractory container40during heat treatment.

The etching apparatus described above includes: the main container20that accommodates the SiC wafer10and generates a vapor pressure of a gas phase species containing Si element and a gas phase species containing C element in an internal space by heating; and a heating furnace30that accommodates the main container20, generates a vapor pressure of a gas phase species containing Si element in an internal space, and performs heating so as to form a temperature gradient, and the main container20has a configuration including an etching space X1formed by causing a part of the main container20arranged on a low temperature side of the temperature gradient and the SiC wafer10to face each other in a state where the SiC wafer is arranged on a high temperature side of the temperature gradient.

With such a configuration, a near thermal equilibrium state can be formed between the SiC wafer10and the main container20, and a vapor pressure environment of a gas phase species containing Si element and a gas phase species containing C element in the main container20(partial pressure of gas phase species such as Si, Si2, Si3, Si2C, SiC2, SiC) can be formed. In such an environment, mass transportation occurs by using the temperature gradient of the heating furnace30as a driving force, and as a result, the SiC wafer10is etched and flattened.

By heating the main container20in a vapor pressure environment of gas phase species containing a Si element (for example, a Si vapor pressure environment), it is possible to suppress the exhaust of gas phase species containing the Si element from the main container20. That is, the environment inside the main container20can be maintained by balancing the vapor pressure of the gas phase species containing the Si element inside the main container20and the vapor pressure of the gas phase species containing the Si element outside the main container20.

The above-described etching apparatus, the main container20is composed of polycrystalline SiC. With such a configuration, when the main container20is heated by using the heating furnace30, only a vapor pressure of a gas phase species containing a Si element and a gas phase species containing C element can be generated in the main container20.

As illustrated inFIGS.3and4, in the etching step S31according to the present embodiment, the SiC wafer10is etched by accommodating the SiC wafer10in the inside of the main container20that generates a vapor pressure of a gas phase species containing Si element and a gas phase species containing C element in an internal space, and heating the main container20so as to form a temperature gradient in an environment of a vapor pressure of a gas phase species containing Si element.

FIG.4is an explanatory diagram illustrating an outline of an etching mechanism. It is considered that, by heating the main container20in which the SiC wafer10is arranged in a temperature range of 1400° C. or higher and 2300° C. or lower, the reactions 1) to 5) below are performed continuously, and as a result, the etching proceeds.
SiC(s)→Si(v)+C(s)  1)
2C(s)+Si(v)→SiC2(v)  2)
C(s)+2Si(v)→Si2C(v)  3)
Si(v)+SiC2(v)→2SiC(s)  4)
Si2C(v)→Si(v)+SiC(s)  5)

Explanation of 1): When the SiC wafer10(SiC(s)) is heated, Si atoms (Si(v)) are desorbed from the surface of the SiC wafer10by thermal decomposition (Si atom sublimation step).

Explanation of 2) and 3): When C (C(s)) remaining on the surface of the SiC wafer10due to the desorption of Si atoms (Si(v)) reacts with the Si vapor (Si(v)) in the main container20to be sublimated from the surface of the SiC wafer10as Si2C, SiC2or the like (C atom sublimation step).

Explanation of 4) and 5): Sublimated Si2C, SiC2, or the like reach the bottom surface (polycrystalline SiC) in the main container20and grow due to the temperature gradient.

That is, the etching step S31includes: a Si atom sublimation step of thermally sublimating the Si atom from the surface of the SiC wafer10; and a C atom sublimation step of causing the C atom remaining on the surface of the SiC wafer10to react with the Si vapor in the main container20to sublimate the C atom from the surface of the SiC wafer10.

The etching step S31may be performed in a state where a Si element supply source or a C element supply source other than the SiC wafer10is arranged in the inside of the main container20. There is no particular problem even if a Si element supply source/C element supply source other than the SiC wafer10exists.

When the SiC wafer10has a crack (crack layer111), it is preferable to arrange the SiC wafer10in a semi-closed space having an atomic number ratio Si/C of equal to or less than 1 and perform heating. For example, the SiC wafer10satisfying a stoichiometric ratio 1:1 and a SiC material satisfying a stoichiometric ratio 1:1 are arranged in a container (main container20) made of SiC satisfying a stoichiometric ratio 1:1, the atomic number ratio Si/C in the main container20is 1. A C vapor supply source (C pellet or the like) may be arranged to set the atomic number ratio Si/C to equal to or less than 1.

By etching the SiC wafer10in such an environment, a crack (crack layer111) can be removed at high speed.

The presence/absence and depth of the crack and the crack layer111have a correlation with the arithmetic average roughness (Ra). That is, the arithmetic average roughness (Ra) value of the surface of the SiC wafer10having a crack is equal to or greater than 10 nm, or equal to or greater than 15 nm, or equal to or greater than 20 nm, or equal to or greater than 25 nm, or equal to or greater than 30 nm, or equal to or greater than 35 nm, or equal to or greater than 40 nm.

In the etching step S31, the SiC wafer10arranged on the high temperature side of the temperature gradient and a part of the main container20arranged on the low temperature side of the temperature gradient are etched so as to face each other.

That is, by arranging the main surface101of the SiC wafer10and the bottom surface of the main container20having a temperature lower than that of the main surface101so as to face each other, the etching space X1is formed between them. In this etching space X1, mass transportation occurs by using the temperature gradient formed by the heating furnace30as a driving force, and as a result, the SiC wafer10can be etched.

The etching temperature in the etching step S31is preferably set in the range of 1400 to 2300° C., and more preferably set in the range of 1600 to 2000° C.

The etching rate in the etching step S31can be controlled in the temperature range described above and can be selected in the range of 0.001 to 2 μm/min.

The etching amount in the etching step S31is not particularly limited as long as the strain of the SiC substrate can be removed and the surface of the SiC substrate can be made to have a predetermined surface roughness or less.

Whether the strain of the SiC substrate is removed by the etching step S31can be evaluated by the following method.

The strain of the SiC substrate (more specifically, the lattice strain) can be obtained by comparing the lattice with a reference crystal lattice as a reference. As a means of measuring this lattice strain, for example, the SEM-EBSD method can be used. The SEM-EBSD method is a method (Electron Back Scattering Diffraction (EBSD)) that enables strain measurement of minute regions on the basis of the Kikuchi line diffraction pattern obtained by electron backscattering in a scanning electron microscope (SEM). In this method, the amount of lattice strain can be obtained by comparing the diffraction pattern of the reference crystal lattice as a reference with the diffraction pattern of the measured crystal lattice.

As the reference crystal lattice, for example, a reference point is set in a region where lattice strain is not considered to occur. In general, it is a well-established theory that the depth of the subsurface damaged layer introduced by machining is about 10 μm. Therefore, it is sufficient that the reference point is set at a position of the depth of about 20 to 35 μm, which is considered to be sufficiently deeper than the subsurface damaged layer.

Next, the diffraction pattern of the crystal lattice at this reference point is compared with the diffraction pattern of the crystal lattice of each measurement region measured at a pitch on the order of nanometers. This makes it possible to calculate the amount of lattice strain in each measurement region with respect to the reference point.

The case where a reference point that is considered to have no lattice strain is set as the reference crystal lattice has been described. However, it is also possible to use an ideal crystal lattice of single crystal SiC as the reference, or use a crystal lattice that occupies the majority (for example, equal to or greater than a half) of the measurement region surface as the reference.

By measuring whether lattice strain exists by this SEM-EBSD method, the presence or absence of the subsurface damaged layer can be determined. That is, when subsurface damage such as a scratch, a latent scratch introduced by machining, and strain is introduced, lattice strain occurs in the SiC substrate, and stress is observed by the SEM-EBSD method.

The “predetermined surface roughness” of the SiC substrate to be achieved by the etching step S31is, as arithmetic average roughness (Ra), preferably equal to or less than 60 nm, more preferably equal to or less than 50 nm, more preferably equal to or less than 40 nm, more preferably equal to or less than 30 nm, more preferably equal to or less than 20 nm, more preferably equal to or less than 10 nm, still more preferably equal to or less than 5 nm, still more preferably equal to or less than 4 nm, still more preferably equal to or less than 3 nm, and still more preferably equal to or less than 2 nm.

As described above, the etching amount is not particularly limited as long as it can remove the strain of the SiC substrate and achieve the surface roughness in the above-mentioned numerical range, but specifically, it is preferably equal to or greater than 0.5 μm, more preferably equal to or greater than 0.6 μm, more preferably equal to or greater than 0.7 μm, more preferably equal to or greater than 0.8 μm, more preferably equal to or greater than 0.9 μm, still more preferably equal to or greater than 1 μm, still more preferably equal to or greater than 2 μm, and still more preferably equal to or greater than 3 μm.

The etching time in the etching step S31can be set to an arbitrary time so as to have a desired etching amount. For example, when the etching rate is 1 μm/min and the etching amount is set to 1 μm, the etching time is 1 minute.

The temperature gradient in the etching planarization step S31is set in the range of 0.1 to 5° C./mm in the etching space X1.

<5> Step after Etching Step S31

The SiC wafer that has been subjected to the etching step S31has reduced strain and has an extremely smooth surface.

Therefore, a mode can be adopted in which some kind of machining is not performed again after the etching step S31. Examples of machining include chemical mechanical polishing (CMP).

In machining including CMP, scratches and strain due to machining may occur on the surface of the SiC wafer to some extent. By not performing machining after the etching step S31, it is possible to provide a higher-quality SiC wafer.

In conventional methods, after performing a mirror polishing step S40including a chemical mechanical polishing step S41, a cleaning step S52is performed in order to remove fine particles remaining on the surface of the SiC wafer. RCA cleaning is generally used as a cleaning method (FIG.11).

On the other hand, in the present invention in which strain removal and an extremely smooth surface are achieved by the etching step S31instead of the mirror polishing step S40, residual foreign matter to be removed by the cleaning step S52does not occur after the etching step S31. Therefore, it is not necessary to perform the cleaning step S52after the etching step S31(FIG.1).

As described above, in the present invention, a SiC wafer having a surface that can be subjected to epitaxial growth can be obtained by the etching step S31.

Therefore, it is effective from the viewpoint of reducing man-hours to perform the epitaxial growth step S61for forming an epi layer on the surface of the SiC wafer after the etching step S31.

Any known method can be adopted as the method of the epitaxial growth step S61performed after the etching step S31.

For example, as means for epitaxial growth, a CVD method, a PVE method, or an LPE method can be used. Here, the CVD method refers to the chemical vapor deposition method, the PVE method refers to the physical vapor epitaxy method, and the LPE method refers to the liquid phase epitaxy method.

[Production Method of SiC Single Crystal Seed Substrate]

The present invention can be applied to the production of a SiC single crystal seed substrate.FIG.5illustrates an embodiment when the present invention is applied to the production of a SiC single crystal seed substrate.

As illustrated inFIG.5, in the present embodiment, regarding the SiC single crystal base substrate, after the planarization step S20is performed until a predetermined surface roughness is obtained, or after a planarization step is performed using an abrasive grain having a predetermined grain size or less, an etching step S31is performed.

As for the specific aspect of the planarization step S20and the etching step S31, the above-mentioned description of the method for producing a SiC wafer is applicable.

The present embodiment includes an ingot forming step S62of performing crystal growth of the SiC single crystal seed substrate obtained by the etching step S31to obtain an ingot.

As a specific aspect of the ingot forming step S62, known ingot forming means can be adopted without particular limitation, and examples thereof include a sublimation method, a CVD method, and a gas growth method.

The SiC ingot thus obtained may be used as a raw material for the slicing step S1to produce a SiC wafer according to the embodiment illustrated inFIG.1.

Example

<1> Sample Preparation (Planarization Step)

A SiC substrate that was mirror-finished and had defects such as latent scratches removed was prepared.

Diamond abrasive grains with an average abrasive grain size of 15 μm, 10 μm, 1 μm, or 0.3 μm were used for this SiC substrate, and pseudo-planarization was performed by a fixed abrasive grain method to prepare samples 1 to 4.

The arithmetic average roughness (Ra) of samples 1 to 4 was measured. The arithmetic average roughness (Ra) was measured using a laser microscope for sample 1 and AFM for samples 2 to 4.

For samples 1 to 4, the average abrasive grain size and arithmetic average roughness (Ra) of the abrasive grains used for preparation are summarized in Table 1 below. For the arithmetic average roughness (Ra), the value rounded to the first decimal place is shown in the table.

TABLE 1Sample No.1234Average grain abrasive size of used151010.3abrasive grain (μm)Arithmetic average roughness (Ra) (nm)110053171
<2> Etching Step

The main container20, refractory container40, and samples 1 to 4 (SiC wafer10) as below were arranged so as to have the configurations illustrated inFIGS.2and3.

[Main Container20]

Material: Polycrystalline SiCContainer size: Diameter 60 mm×Height 4 mmSubstrate holder24material: Single crystal SiCDistance between SiC wafer10and bottom surface of main container20: 2 mm
[Refractory Container40]Material: TaCContainer size: Diameter 160 mm×Height 60 mmSi vapor supply source44(Si compound): TaSi2
[Etching Step]

Samples 1 to 4 arranged under the above conditions were heat-treated under the conditions of a temperature gradient of 1° C./mm and a main heating chamber vacuum degree of 10−5Pa.

For each sample, the test was conducted under two conditions: condition A in which a single crystal Si piece as a Si vapor supply source is arranged in the inside of the main container20and etching is performed, and condition B in which etching is performed without arranging a single crystal Si piece.

That is, condition A is a condition in which the SiC wafer10is arranged and heated in a semi-closed space having an atomic number ratio Si/C of greater than 1, and condition B is a condition in which the SiC wafer10is arranged and heated in a semi-closed space having an atomic number ratio Si/C of equal to or less than 1.

Etching was performed for each of heating temperatures of 1500° C., 1600° C., 1700° C., 1800° C. and 1900° C., under multiple conditions with different etching amounts. The etching amount can be adjusted by changing the heating time.

<3> Evaluation

<3-1> Measurement of Strain by SEM-EBSD Method

The strain existing in samples 1 to 4 before and after the etching step was observed by the SEM-EBSD method. The strain was measured by the SEM-EBSD method on the cleaved cross section of the SiC substrate of samples 1 to 4 under the following conditions using a scanning electron microscope.SEM device: Zeiss MerlineEBSD analysis: OIM crystal orientation analyzer manufactured by TSL SolutionsAcceleration voltage: 15 kVProbe current: 15 nAStep size: 200 nmReference point R depth: 20 μm

As a result of the measurement, strain was observed in samples 1 to 4 before the etching step. This is lattice strain introduced by the pseudo-planarization step performed in the sample preparation, and it can be seen that it has an subsurface damaged layer. In each case, compressive stress was observed. Specifically, strain of 5 μm in depth were observed in sample 1, 3 μm in depth in sample 3, and 1 μm in depth in sample 4.

On the other hand, no strain was observed in samples 1 to 4 after etching. This result indicates that the subsurface damaged layer was removed by the etching step.

FIG.6illustrates a cross-sectional SEM-EBSD captured image of the SiC substrate of sample 1 before and after etching.FIG.6(a)is a cross-sectional SEM-EBSD captured image of sample 1 before etching. Before this etching, it can be seen that strain is introduced from the black-and-white contrast of the image to the position of a depth of 5 μm.FIG.6(b)is a cross-sectional SEM-EBSD captured image after etching. After this etching, the black-and-white contrast as before the etching was not observed. That is, as illustrated inFIG.6, strain having a depth of 5 μm was introduced before the etching step, but this could be removed by etching.

<3-2> Surface Evaluation by SEM

The surfaces of samples 1 to 4 before and after the etching step were observed by SEM.FIG.7illustrates SEM images (magnification 3000 times) of the surfaces of the SiC substrates of samples 1 to 4 before the etching step, after etching at 3.08 μm under condition A (temperature 1800° C.), and after etching at 5 μm under condition B (temperature 1800° C.)

As illustrated inFIG.7, sample 1 had remarkable unevenness on the surface even after etching under any of the conditions A and B.

On the other hand, as illustrated inFIG.7, in samples 2 to 4, an extremely smooth surface state could be achieved by etching, and no remarkable unevenness as in sample 1 was observed.

In sample 3, after etching under the condition B, a slight pit (the part indicated by the white arrow) was observed. However, in sample 4, no pit was observed even by etching under the condition B, and it was found that a smoother surface could be obtained.

<3-3> Relationship Between Arithmetic Average Roughness (Ra) and Etching Amount

The etching amount and the arithmetic average roughness (Ra) were measured for the SiC substrates of samples 1, 3 and 4 etched under the various conditions described above. The arithmetic average roughness (Ra) was measured using a laser microscope for sample 1 and AFM for samples 3 and 4. Arithmetic average roughness (Ra) and etching amount before and after etching were plotted on the graph.

The result of sample 1 is shown inFIG.8, the result of sample 3 is shown inFIG.9, and the result of sample 4 is shown inFIG.10. In the graph showing each result, the depth of strain measured in <3-1> above is indicated by a black arrow.

As illustrated inFIG.8, for the SiC substrate of sample 1 (initial arithmetic average roughness (Ra) is about 1100 nm) processed with an abrasive grain having an average abrasive grain size of 15 μm, even if deeply etched, the arithmetic average roughness (Ra) never fell below 60 nm. In particular, for the SiC substrate etched under condition B, even a region where the surface roughness increases as the etching amount increases was observed.

This result shows that, in the SiC substrate of sample 1, strain can be removed by etching, but an extremely smooth surface cannot be achieved.

On the other hand, for the SiC substrate of sample 3 (initial arithmetic average roughness (Ra) is about 17 nm) processed with an abrasive grain with an average abrasive grain size of 1 μm, the arithmetic average roughness (Ra) fell below 5 nm at an etching amount of around 1000 nm (FIG.9).

Furthermore, it was found that the arithmetic average roughness (Ra) can be reduced to equal to or less than 2 nm by proceeding the etching beyond the depth of strain existing before etching (FIG.9).

When the SiC substrate of sample 4 (initial arithmetic average roughness (Ra) is about 0.5 nm) processed with an abrasive grain with an average abrasive grain size of 0.3 μm was etched, it was confirmed that an extremely flat surface having the arithmetic average roughness (Ra) of equal to or less than 2 nm, further, equal to or less than 1 nm was formed (FIG.10).

According toFIG.8, in sample 1 which is the SiC wafer10having a crack, it can be seen that the etching rate of the condition B is higher than the etching rate of the condition A up to the 5 μm point where the subsurface damaged layer is removed.

Therefore, when etching the SiC wafer10having a crack, by including the step (condition B) of arranging and heating the SiC wafer10in a semi-closed space where the atomic number ratio Si/C is equal to or less than 1, etching can be performed at high speed.

Specifically, when the SiC wafer10having a crack is etched, the time of the etching step of the SiC wafer10can be shortened by first etching under the condition B and then etching under the condition A.

<4> Summary

The above results indicate that, it is possible to obtain a SiC substrate in which strain is removed and having an extremely smooth surface by performing the planarization step on a SiC substrate until the arithmetic average roughness (Ra) of the surface becomes equal to or less than 100 nm, or performing the planarization step by using an abrasive grain with an average abrasive grain size of equal to or less than 10 μm, and then performing etching in an atmosphere containing Si element and C element. The SiC substrate thus obtained can be subjected to an epitaxial growth step without further machining such as CMP.

REFERENCE SIGNS LIST

10SiC substrate (SiC wafer)101Main surface11Subsurface damaged layer111Crack layer112Strain layer12Bulk layer20Main container24Substrate holder30Heating furnace40Refractory container44Si vapor supply sourceX1Etching spaceS1Slicing stepS20planarization stepS21Lapping stepS22Rough grinding stepS23Finish grinding stepS31Etching stepS40Mirror polishing stepS41Chemical mechanical polishing stepS51, S52Cleaning stepS61Epitaxial growth stepS62Ingot forming step