Patent ID: 12231833

DETAILED DESCRIPTION OF THE DRAWINGS

FIG.1shows a schematic view of a first embodiment of the sensor module with a master sensor unit1and two slave sensor units2on a common substrate3. The master sensor unit1and the slave sensor units2are integrated in three separate chips, preferably semiconductor chips. The common substrate3may be a printed circuit board or any other support for mounting the chips on. The number of slave sensor units2may be one, two or more.

Each slave sensor unit2communicates with the master sensor unit1via a digital bus interface4. The digital bus interface4is a low pin-count digital interface, preferably a two-wire or one-wire interface. The communication via the digital bus interface4comprises at least signals measured by the slave sensor units2and start/stop conditions for the measurements. It may as well comprise a clock signal for synchronizing the communication and the measurements of the master sensor unit1and the slave sensor units2. The clock signal can e.g. be generated by a quartz, which may be located internal in the master sensor unit1, or the signal of which may be supplied from external to the sensor module, and preferably to the master sensor unit1.

The master sensor unit1and the slave sensor units2are arranged in a housing5, which protects the chips and yields a robust sensor module. The housing5may be made of plastic or metal, or it may be an encapsulation, e.g. comprising a moulding compound. The housing5comprises at least one opening6for the sensor units1,2to be able to sense physical quantities of an environment of the sensor module. In one embodiment, the housing5comprises one common opening6for all sensor units1,2. In a different embodiment, there are separate openings6for several or all of the sensor units1,2in the housing.

The sensed physical quantities may comprise a variety of quantities, e.g. relative humidity, temperature, gas concentration or aerosol concentration, preferably all of the ambient. In a preferred embodiment, the master sensor unit1comprises a combined sensor for relative humidity and temperature, one slave sensor unit2comprises a 4-pixel MOX gas sensor, and the other slave sensor unit2comprises an electrochemical CO2 sensor. An extension to more slave sensor units2is possible, with e.g. an optical particle counter as additional slave sensor unit2. The described setup and communication make it possible to integrate common sensor units into the sensor module as slave sensor units2which would otherwise be difficult or impossible to be integrated in a small package together with the sensor, a processor and a memory of the master sensor unit1.

The master sensor unit1receives a power supplied from externally via one or more of pins7. The pins7are also used to receive and supply control signals and measured signals and hence represent an interface for the master sensor unit1to communicate with an external unit. In one embodiment, the master sensor unit1comprises a power management unit for generating an internal supply voltage and a supply voltage for the digital bus interface4. The internal supply voltage may also be provided to the slave sensor units2such that they do not necessarily require a separate power management unit.

FIG.2shows a block diagram of a sensor module according to an embodiment of the present invention with a master sensor unit1and one slave sensor unit2as well as their respective subunits1x,3xfor the master sensor unit1, and2xfor the slave sensor unit2. A possible extension to more than one slave sensor units2is indicated through the dashed lines at the right ofFIG.2. In this embodiment, the master sensor unit1and the slave sensor unit2are fed by a common external supply voltage8(VDDIO).

The master sensor unit1receives and transmits signals via a digital or analog input and output line9(D/A IO), also referred to as interface for the master sensor unit1. The input signals may be control signals for performing specific measurement routines. The output signals may be signals of one or more physical quantities measured by the sensor units1and2, or they comprise a combined or processed signal from more than one of the sensor units1and2, or a control signal, such as an alarm. The master sensor unit1communicates with the slave sensor unit2via a digital bus interface4. For this purpose, the master sensor unit1comprises a digital master interface30, and the slave sensor unit comprises a digital slave interface26.

The master sensor unit1may comprise an oscillator31for deriving a common clock from for the master sensor unit1and the slave sensor unit2. The common clock signal preferably is transmitted to the slave sensor unit2via the digital bus interface4. The master sensor unit1comprises a sensitive element11, which may be sensitive to relative humidity and/or temperature. In a different embodiment, the sensitive element11is a capacitive CO2 sensor. The master sensor unit1further comprises a non-volatile memory12for storing calibration data of the master sensor unit1and the slave sensor unit2, and a non-volatile memory13for storing configuration data of both the master sensor unit1and the slave sensor unit2. Non-volatile memories12and13may be represented by a common non-volatile memory having the various data stored in a common memory structure. Calibration data may be stored in the form of look-up tables which facilitate different operations on a measured signal. Accordingly, calibration data may include correcting factors for a sensor response, linearization parameters, interpolation parameters, or compensation parameters e.g. for temperature.

For processing the signals measured by the different sensor units1,2, the master sensor unit1comprises a processing unit14, which may, for example, be a hardwired logic. The processing unit14is configured to perform the operations mentioned above on the measured signal, e.g. by using look-up tables provided by the non-volatile memories12and13. The measured signal and/or the processed signal is stored in a memory18.

The master sensor unit1additionally comprises a power management unit15for generating a supply voltage for the digital bus interface4. It may also provide a supply voltage different from VDDIO for other subunits, such as the sensitive element11.

Advantageously, the master sensor unit1comprises a measurement sequence unit16for controlling a sequence of measurements by the sensor units1and2. The measurement sequence unit16may e.g. ensure a right order of measurements by the different sensor units1,2, or it may apply conditions for a specific sensor unit1,2to provide a measurement value, or it may apply different sampling rates for different sensor units1,2.

Also, the master sensor unit1preferably comprises a self-test unit17configured to execute a test sequence on at least one sensor unit1,2during manufacturing or application of the sensor module. The self-test unit17may apply a certain measurement routine to a specific sensor unit1,2, compare the measured data with a stored reference, and output a signal indicating a possible defect of the specific sensor unit1,2.

Preferably, the master sensor unit1comprises a power-on reset32generation to reset the processing unit14and/or the volatile memory18to an initial state.

In comparison with the master sensor unit1, the slave sensor unit2is of limited functionality. It is sufficient that it comprises a MEMS sensor21, e.g. a MOX gas sensor or an electrochemical gas sensor, analog front-end electronics22such as a readout for interfacing sensor signals, and an analog-to-digital converter23. Hence, the slave sensor unit2may be a common MEMS chip.

Advantageously, the slave sensor unit2comprises a non-volatile memory24for storing a unique unit identification number. This facilitates addressing each slave sensor unit2separately via the digital bus interface4.

The slave sensor unit2may also comprise a power management unit25for generating an internal supply voltage derived from the common external supply voltage8(VDDIO), for supplying power to its analog as well as its digital parts.

FIG.3illustrates a block diagram of a sensor module according to another embodiment of the present invention. The sensor module ofFIG.3only differs from the sensor module ofFIG.2in that the power supply in the slave sensor unit2is realized different. Instead of the power management unit25ofFIG.2responsible for powering analog and digital parts of the slave sensor unit2, in the embodiment ofFIG.3, a power management unit25ais provided for generating an internal supply voltage derived from the common external supply voltage8(VDDIO), but limited to supplying power to the analog parts of the slave sensor unit2only. Instead, powering of the digital parts of the slave sensor unit2is achieved by means of different power management unit25b, which derives the supply voltage for the digital parts from the digital bus interface4. Hence, in this embodiment, the power management unit15of the master sensor unit1supplies a supply voltage—preferably different from VDDIO but derived therefrom—to the slave sensor unit2via the digital bus interface4.

FIG.4illustrates the timing of clock and measurements as used in a sensor module according to an embodiment of the present invention. Such timing may be used in any of the embodiments of the sensor modules according toFIGS.1to3. A clock of the master is shown in the first graph over time. The period of the clock of the master is referred to by (2). The second graph shows a clock of a first slave sensor unit, the period of which clock is equal to the period of the master clock. The third graph shows a clock of a second slave sensor unit, the period of which clock is equal to the period of the master clock and the clock of the first slave sensor unit. Accordingly, it is preferred that all sensor units, i.e. the master sensor unit and any slave sensor unit are operated under the same clock signal, i.e. are operated under a common clock with a defined common clock period (5) and a common phase: Hence, all clocks are in phase.

As to the timing of measurements triggered or taken by the individual sensor units, reference (1) indicates such points in time of measurement strobes, i.e. all bold strokes inFIG.4represent a measurement strobe within a sequence of measurements taken by the sensor units. Accordingly, the sensor of the master sensor unit takes measurements/is triggered by the measurement sequence unit to take measurements every second clock period. The sensor of the first slave sensor unit takes measurements/is triggered by the measurement sequence unit of the master sensor unit to take measurements every third clock period. The sensor of the second slave sensor unit takes measurements/is triggered by the measurement sequence unit of the master sensor unit to take measurements every fourth clock period. Accordingly, the measurements of the various sensors in the master sensor unit and the slave sensor units are taken synchronously, i.e. based on the common clock, and of a frequency of multiple integers of the common clock period.

FIG.5shows a combined signal40for common clock and reset signal41used to derive a reset pulse42. The combined signal40is supplied from the master sensor unit to any slave sensor unit via the digital interface bus. The combined signal40may be transmitted via a single pin, which is shared for reset and clock signals. The reset pulse for the slave sensor unit is generated on-chip if the clock timing deviates from a nominal clock timing in a specific way.

FIG.5depicts a possible implementation of common clock and reset signal in one combined signal. The upper part ofFIG.5shows a situation where no reset pulse from the combined signal40is generated since the clock timing corresponds to the nominal clock timing with nominal high time Thigh,nomand nominal low time Tlow,nom.

The lower part ofFIG.5shows a situation where a high pulse in the combined signal40is longer than the nominal high time Thigh,nom, and this high pulse is directly followed by a low pulse that is shorter than the nominal low time Tlow,nom. Such sequence of a high pulse and a low pulse, called a reset sequence, is interpreted as a reset pulse42, and the slave sensor unit is reset.

FIG.6shows a block diagram of a usage of the combined signal40for the common clock43, the reset signal41and additionally a supply voltage44. Such combination or usage of signals is also called “power-over-clock”. A reset sequence detector45evaluates the combined signal40supplied to the slave sensor unit. If the reset sequence detector45detects a reset sequence, for instance defined as in depicted inFIG.5, it generates a reset pulse. In addition to the common clock43and the reset signal41, also the supply voltage44for the slave sensor unit is taken from the combined signal40. In this way, a dedicated pin for the supply voltage is not needed. Providing the supply voltage44via the combined signal40is facilitated since the combined signal40is “high” for most of the time, i.e. a cumulated duration of the high pulses is longer than a cumulated duration of the low pulses. Also the reset sequence as defined above is compatible with a “power-over-clock” scheme where the supply voltage for the slave sensor unit is provided through the combined signal together with the common clock. The combined signal may be low-pass filtered for these purposes.