Patent ID: 12212293

DETAILED DESCRIPTION

Some examples will now be explained extensively with reference to the appended figures. Further possible examples are not, however, restricted to the features of these implementations described in detail. These can exhibit modifications of the features, as well as correspondences and alternatives to the features. The terminology that is used here for the description of specific examples should not, furthermore, be restrictive for further possible examples.

Identical or similar reference signs in the full description of the figures relate to identical or similar elements or features, each of which can be implemented in an identical or modified form while providing the same or a similar function. The thicknesses of lines, layers and/or regions in the figures can, furthermore, be exaggerated for clarity.

If two elements A and B are combined using the term “or”, this is to be understood that all the possible combinations are disclosed, e.g. only A, only B, and A and B, unless this is explicitly defined otherwise in individual cases. “At least one of A and B” or “A and/or B” may be used as alternative formulations of the same combinations. Equivalent considerations apply to combinations of more than two elements.

If a singular form such as “a” and “the” is used, and if the use of only one single element is not defined either explicitly or implicitly as obligatory, further examples can also use multiple elements to implement the same function. If a function is described below as being implemented through the use of multiple elements, further examples can implement the same function using a single element or a single processing entity. It is further understood that when the terms “includes”, “including”, “comprises” and/or “comprising” are used they describe the presence of the stated features, whole numbers, steps, operations, processes, elements, components and/or a group of the same, but do not, however, exclude the presence or addition of one or a plurality of other features, whole numbers, steps, operations, processes, elements, components and/or a group of the same.

The modulation and demodulation, also referred to as chopping, performed by a chopper amplifier may cause ripples in the output signal (referred to herein as ripples or chopper ripples). Such ripples can, for example, be caused by a voltage offset in an amplifier that is used for amplification in the chopper amplifier. The amplitude of the ripple corresponds to the offset, and the frequency of the ripple corresponds to the chopper frequency.

Various techniques have been used to reduce such ripples. In at least some cases such conventional techniques are expensive to implement, and are disadvantageous in terms of the current consumption, or are limited to a specific chopper frequency.

Some implementations described herein provide improved techniques to reduce chopper ripples.

FIG.1shows an amplifier circuit100according to a first example implementation of the present disclosure. The amplifier circuit100can operate in a time-continuous mode in order to provide an offset-free output signal. This time-continuous mode is also referred to below as the “normal mode”.

The amplifier circuit100comprises a modulator circuit110clocked at a chopper frequency fchop. The modulator circuit110is configured to convert a DC input voltage originating from a signal source150into an AC input voltage. The DC input voltage can approximately be assumed to be approximately constant during a switching phase (chopper phase) PH1or PH2of the modulator circuit110. The DC input voltage can, however, also change in the course of time, but at a frequency that is significantly lower than the chopper frequency fchop. In the illustrated example implementation, the signal source150is configured as a Hall sensor that can be operated in what is known as spinning current operation. Offsets in Hall sensors can be reduced by the three-phase method or the spinning current method, in which an initial voltage current of a Hall sensor is rotated spatially around the hall sensor while the output is averaged over time. This reduces an offset and an offset drift.

During a first spinning or chopper switching phase PH1, a first current flows via the terminals151,152, so that a first Hall voltage can be accessed at the terminals153,154. During a subsequent second spinning or chopper switching phase PH2, a second current flows via the terminals153,154, so that a second Hall voltage can be accessed at the terminals151,152, and so on. It is understood that the example implementations of the present disclosure can also be operated with other signal sources that can be combined with amplifiers.

On the output side of the modulator circuit110, the amplifier circuit100further comprises an amplifier120that comprises an inverting input121and a non-inverting input122for the AC input voltage (Hall voltage, for example). The inputs121,122can also be referred to as the negative and positive inputs, and constitute a differential input. The amplifier120also comprises an inverting output123and a non-inverting output124for an amplified AC measuring voltage. The outputs123,124can in a similar way be referred to as the negative and positive output, and form a differential output. The amplifier120can, for example, be an operational amplifier. Other common implementations of amplifiers are also, however, conceivable.

An inverting output of the modulator circuit110is connected directly (e.g. without an intermediate capacitor) to the inverting input121of the amplifier120, and a non-inverting output of the modulator circuit110is directly connected to the non-inverting input122of the amplifier120. A non-inverting input of the modulator circuit100is connected directly to the signal source150(terminals151,153), and an inverting input of the modulator circuit110is connected directly to the signal source150(terminals152,154).

A demodulator circuit130clocked at the chopper frequency fchopis connected to the differential amplifier output123,124, and is configured to convert the amplified AC voltage back into an amplified DC output voltage. The inverting amplifier output123is coupled via a first capacitor141into a first signal path142to a first input131of the demodulator circuit130. The non-inverting amplifier output124is coupled via a second capacitor143into a second signal path144to a second input132of the demodulator circuit. A discharge resistor circuit160coupled between the first signal path142and the second signal path144is located at the output of the two capacitors141,143.

The demodulator circuit130is configured to convert the AC voltage amplified by the amplifier120back into an amplified DC voltage. According to example implementations of the present disclosure, the demodulator circuit130is configured to couple each of the inverting and non-inverting outputs123,124of the amplifier120capacitively (via the capacitors141,143) to an inverting input181and non-inverting input182of a comparator or differential output amplifier circuit180during different switching phases PH1, PH2. The inputs181,182constitute a first differential input of the output amplifier circuit180. In the example implementation illustrated, a first-order low-pass filter170is provided between the demodulator circuit130and the output amplifier circuit180.

The modulator circuit110and the demodulator circuit130each comprise a plurality of switches that are opened or closed in different chopper switching phases PH1, PH2. The switches of the modulator circuit110and of the demodulator circuit130are here clocked synchronously. For example, the demodulator circuit130in the example implementation shown inFIG.1is configured to couple the non-inverting output124of the amplifier120to the non-inverting input181of the output amplifier circuit180during a first switching phase PH1. The demodulator circuit130ofFIG.1is further configured to couple the inverting output123of the amplifier120to the inverting input182of the output amplifier circuit180during the first switching phase PH1. The demodulator circuit130is further configured to couple the non-inverting output124of the amplifier120to the inverting input182of the output amplifier circuit180during a second switching phase PH2. The demodulator circuit130is further configured to couple the inverting output123of the amplifier120to the non-inverting input182of the output amplifier circuit180during the second switching phase PH2.

The discharge resistor circuit160in the example implementation shown inFIG.1, comprises a first discharge resistor162coupled between an output terminal of the first capacitor141and a reference potential161. The discharge resistor circuit160further comprises a second discharge resistor163coupled between an output terminal of the second capacitor143and the reference potential161. The input terminal of the first capacitor141is coupled to the inverting amplifier output123. The input terminal of the second capacitor143is coupled to the non-inverting amplifier output124. The discharge resistor circuit160further comprises a switch arrangement164that is configured to connect the first discharge resistor162between the first capacitor141and the reference potential161, and to connect the second discharge resistor163between the second capacitor143and the reference potential161, during at least one discharge time period.

The reference potential161can, for example, be a common mode potential (DC voltage), or also a ground.

The discharge time period preferably corresponds to a time period between the first switching phase (chopper phase) PH1and the second switching phase PH2of the modulator circuit110or of the demodulator circuit130. The two switching phases PH1and PH2do not overlap in time. This is shown schematically inFIG.2. The two discharge resistors162,163are thus connected using the switch arrangement164to the reference potential161after the switching phase PH1has ended and before the switching phase PH2has started. The discharge resistors162,163, are free running during the switching phases PH1and PH2, e.g. are not connected to the reference potential161. According to some example implementations, a duty cycle of the switch arrangement164can lie in the range between 0.1%-5%. According to some example implementations, the switches of the switch arrangement164are closed outside of the switching phases PH1and PH2during a time period between the two switching phases PH1and PH2. The switches of the switch arrangement164are open during the switching phases PH1and PH2. The switching times of the switch arrangement164can, for example, also occur at the chopper frequency. In some example implementations, the clock rate of the switch arrangement164can, however, also be chosen to be pseudo-random. The switching times of switch arrangement164are thus arranged in any case in intermediate time periods between two sequential switching phases PH1and PH2, but not necessarily in each of these intermediate time periods.

Due to the capacitive coupling of the amplifier outputs123,124to the inputs of the demodulator circuit130and the discharge resistor circuit160, the DC component of a differential voltage between the non-inverting and inverting signal paths144,142can be reduced, and thereby also the chopper ripple. A low-pass filter circuit170with an order less than or equal to three (first order in this case) coupled at the output side to the demodulator circuit130is thus sufficient.

It has been found to be advantageous for the discharge resistors162,163to have relatively high resistances (for example in the range from 1 Me), so that long discharge times result. The clocked operation of the discharge resistors162,163brought about by the switch arrangement164has the effect that the resistors162,163effectively have an even greater or higher-resistance value.

The signal waveform during the two sequential switching phases PH1, PH2during the normal mode of the amplifier circuit100is described below with reference toFIGS.3A and3B.FIG.3Arelates to the first switching phase PH1.

During the first switching phase PH1a first current flows in the Hall sensor150via the terminals151,152, so that a first (DC) Hall voltage (+Vs+Voh)/2 can be accessed at the terminal153and (−Vs−Voh)/2 at the terminal154. Due to an additional offset voltage +Voh of the Hall sensor150and an offset voltage +Voa of the amplifier120, a differential input voltage of +Vs+Voh+Voa results at the differential input121,122of the amplifier120in the first switching phase PH1. With an amplification factor g of the amplifier120, an output voltage of g×(+Vs+Voh+Voa)/2 results at its non-inverting output124, and an output voltage of g×(−Vs−Voh−Voa)/2 at its inverting output123. The capacitors141,142block the DC signal components g×(Voh+Voa)/2 and g×(−Voh−Voa)/2, but allow AC signal components g×(Vs)/2 and g×(−Vs)/2 through to the output amplifier circuit180. Essentially, the amplified and offset-free Hall voltage g×Vs is obtained at the output183of the output amplifier circuit180. In the normal mode, during the discharge time period, between the first switching phase PH1and a subsequent second switching phase PH2, electrical charges corresponding to the DC signal components g×(Voh+Voa)/2 and g×(−Voh−Voa)/2 can disperse via the discharge resistor circuit160from the capacitors141,142, so that a charge equalization takes place between the capacitors141,142.

FIG.3Brelates to the second switching phase PH2in normal mode.

During the second switching phase PH2following the first switching phase, a second current flows in the Hall sensor150via the terminals153,154, so that a second (DC) Hall voltage (−Vs+Voh)/2 can be accessed at the terminal151and (+Vs−Voh)/2 at the terminal152. Due to an additional offset voltage +Voa of the amplifier120, a differential input voltage of −Vs+Voh+Voa thus results at the differential input121,122of the amplifier120in the second switching phase PH2. With an amplification factor g of the amplifier120, an output voltage of g×(−Vs+Voh+Voa)/2 results at its non-inverting output124, and an output voltage of g×(+Vs−Voh−Voa)/2 at its inverting output123. The capacitors141,142block the DC signal components g×(Voh+Voa)/2 and g×(−Voh−Voa)/2, but allow AC signal components g×(−Vs)/2 and g×(Vs)/2 through to the output amplifier circuit180. Essentially, the amplified and offset-free Hall voltage g×Vs is obtained again at the output of the output amplifier circuit180by exchanging their input terminals as compared with the first switching phase PH1. During the discharge time period in the normal mode, between the first switching phase PH2and a subsequent first switching phase PH1, electrical charges corresponding to the DC signal components g×(Voh+Voa)/2 and g×(−Voh−Voa)/2 can disperse via the discharge resistor circuit160from the capacitors141,142, so that a charge equalization takes place between the capacitors141,142. The chopper ripple can thereby be reduced.

When, in particular, the discharge resistors162,163are implemented in integrated circuits, the realization of high-value resistors can be problematic.FIG.4therefore shows an example implementation of an amplifier circuit400in which the discharge resistors162,163are realized by switched capacitors462,463. Switched capacitor filters, frequently also referred to by the abbreviation SC filters, are electronic filters in which ohmic resistors are replaced by switched capacitors. They are time-discrete filters. The filter parameters of the SC filters can be very easily changed by varying the switching frequency fswith which the capacitors462,463are switched over. The replacement of the ohmic resistors R in a given circuit such as a low-pass filter by capacitors CSthat are operated at the switching frequency fscan be calculated according to R=1/fsCS. It will be clear to the expert that the switching frequency fsof the capacitors462,463does not have to correspond to the chopper frequency fchopor to the spinning frequency.

A brief, limited charge equalization, which only equalizes the temporal mean value after several (or many) chopper phases to a differential of 0 V, can take place while the chopper demodulation phases are not overlapping in time. The continuous-time signal processing (signals can also change during the chopper phases and are passed through capacitively to the output amplifier180) that also takes place here differs from sampling switched capacitor circuits, for example, since a complete, fast charge equalization does not take place in one chopper phase. On the contrary, a charge equalization can only occur over many chopper phases, as a result of which the amplitude of the actual useful signal is essentially retained (due to negligible discharge for the useful signal within one chopper phase). The small partial discharge to a differential mean value of 0 V can be done using a small switched-capacitor circuit, which can be interpreted as, or acts as, a high-value discharge resistor. This can also be achieved using a duty-cycle resistor during the short non-overlapping phase.

A further possibility for realizing the discharge resistors162,163is shown inFIG.5. The discharge resistors are realized there by what are known as pseudo-resistors562,563.

According to some example implementations, the discharge resistor circuit160can comprise one or a plurality of voltage-controlled pseudo-resistors562,563comprising MOS transistors connected in series. Pseudo-resistors can use MOS components connected with diodes, which MOS components operate in the sub-threshold range and which use less surface area than the corresponding discrete component. As shown in the lower part ofFIG.5, one or a plurality of MOSFETs555biased in the sub-threshold range can function in a circuit as a linear resistor whose resistance is controlled by the gate voltage. A voltage between the terminals A and B of MOS pseudo resistors varies, for example, between −1 V and +1 V, and corresponding resistance changes for various gate voltages have been shown for various types of voltage-controlled pseudo-resistors. A possible structure of voltage-controlled PMOS pseudo-resistors is illustrated in the lower part ofFIG.5. In addition to PMOS or NMOS, complementary MOS pseudo-resistors are also conceivable.

Chopper ripple suppression can thus be achieved in combination with the spinning Hall concept, using an input modulator110, an amplifier120, (AC coupled) output capacitors141,143connected directly between the amplifier output and the demodulator, and a duty-cycle resistor or switched-capacitor resistor or pseudo-resistor with MOS transistors operated in the sub-threshold range. An offset-compensated chopper amplifier with low chopper ripple noise, low jitter, low signal delay (latency) and low chip area can thus be provided.

The amplifier circuits100,400,500indicated above can be operated not only in a time-continuous normal mode to acquire or measure input signals (in this case the Hall voltage), but can also be operated in a time-discontinuous or time-discrete energy-saving mode in which the input signal is amplified and sampled at a defined sampling rate.

FIG.6Ashows the amplifier circuit100in a first switching phase PH1of the energy-saving mode. In contrast to the normal mode, the amplifier circuit100in the energy-saving mode does not comprise a discharge resistor circuit.

During the first switching phase PH1of the modulator circuit100in the energy-saving mode, an output terminal of the first capacitor141of the inverting amplifier output123, and an output terminal of the second capacitor143of the non-inverting amplifier output124are connected to the common DC potential161. The switches164-1,164-2of the switch arrangement164are closed for this purpose. In comparison with the normal mode, the output terminals of the capacitors141,143are connected directly to the DC potential161during the first switching phase PH1of the energy-saving mode. The discharge resistor circuit is omitted, or its discharge resistors are short-circuited, in the energy-saving mode, so that a differential voltage Vdiff between the signal paths142,144, or between the output terminals of the capacitors141,143is 0 V.

As can be seen inFIG.6A, the output terminals of the first and second capacitors141,143are disconnected from the inputs181,182of the output amplifier180in the first switching phase PH1of the energy-saving mode. The inputs181,182of the output amplifier180can also be short-circuited using a switch184provided between the inputs181,182, so that there is no output signal from the output amplifier180.

FIG.6Bshows the amplifier circuit100in a second switching phase PH2of the energy-saving mode.

While the second switching phase PH2of the modulator circuit100is in the energy-saving mode, the output terminal of the first capacitor141is directly coupled to the input181of the output amplifier180, and the output terminal of the second capacitor143is coupled directly to the input182of the output amplifier180. The switch184between the amplifier inputs181,182is open during the second switching phase PH2, so that the amplifier inputs181,182are disconnected from one another. The switches164-1,164-2of the switch arrangement164are also open during the second switching phase PH2, so that the output terminal of the first capacitor141and the output terminal of the second capacitor143are disconnected from the common DC potential161, and the output terminals of the capacitors141,143are disconnected from one another.

It can be seen inFIG.6Cthat in the energy-saving mode, the first switching phase PH1and an (immediately) following second switching phase PH1form a switching cycle610. In the switching cycle610, the amplifier circuit100operates in the energy-saving mode as a sampling switched capacitor circuit. A sleep time period620then follows the switching cycle610with first and second switching phase PH1, PH2, until a further switching cycle610with first and second switching phase PH1, PH2follows the sleep time period620. A sleep time period620then follows again, and so on. The amplifier circuit100is thus configured to switch off a current consumption, at least of the amplifier circuit120, for a sleep time period620in the energy-saving mode between the second switching phase PH2of one switching cycle610and a first switching phase PH1of a subsequent switching cycle610. Current consumptions of output amplifiers180and/or the Hall sensor150can furthermore also be switched off during the sleep time period620, in order to reduce the energy consumption of the amplifier circuits100further.

A ratio between the sleep time period620and a duration of the switching cycle (e.g. sleep time period/switching cycle) can lie in a range between 10-10,000. The sleep time period620can, for example, be 10 ms long, while a switching cycle610with switching phases PH1, PH2can merely be 10 μs. The sleep time period620can thus be 10 to 1000 times longer than a switching cycle610with the switching phases PH1and PH2. The greater the ratio, the lower is the energy consumption. The sampling intervals, however, also increase as a result.

The signal waveform during the two sequential switching phases PH1, PH2during the energy-saving mode of the amplifier circuit100is described below with reference toFIGS.7A and7B.FIG.7Arelates to the first switching phase PH1.

During the first switching phase PH1a first current flows in the Hall sensor150via the terminals151,152, so that a first Hall voltage (+Vs+Voh)/2 can be accessed at the terminal153and (−Vs−Voh)/2 at the terminal154. Due to an additional offset voltage +Voh of the Hall sensor150and an offset voltage +Voa of the amplifier120, a differential input voltage of +Vs+Voh+Voa results at the differential input121,122of the amplifier120in the first switching phase PH1. With an amplification factor g of the amplifier120, an output voltage of g×(+Vs+Voh+Voa)/2 results at its non-inverting output124, and an output voltage of g×(−Vs−Voh−Voa)/2 at its inverting output123. Due to the fact that the capacitors141,143are connected on the output side to the common DC potential161and are disconnected from the inputs181,182of the output amplifier180, the output voltages g×(+Vs+Voh+Voa)/2 (non-inverting output124) and g×(−Vs−Voh−Voa)/2 (inverting output124) are stored (sampled) in the capacitors141,143in the first switching phase PH1.

FIG.7Brelates to the second switching phase PH2in the energy-saving mode.

During the second switching phase PH2following the first switching phase, a second current flows in the Hall sensor150via the terminals153,154, so that a second Hall voltage (−Vs+Voh)/2 can be accessed at the terminal151and (+Vs−Voh)/2 at the terminal152. Due to the additional offset voltage +Voa of the amplifier120, a differential input voltage of −Vs+Voh+Voa results at the differential input121,122of the amplifier120in the second switching phase PH2. With an amplification factor g of the amplifier120, an output voltage of g×(−Vs+Voh+Voa)/2 results at its non-inverting output124, and an output voltage of g×(+Vs−Voh−Voa)/2 at its inverting output123. In the second switching phase PH2, the output terminal of the capacitor143is connected directly to the input terminal182of the output amplifier180. In the same way, the output terminal of the capacitor141is connected directly to the input terminal181of the output amplifier180. As a result of the open switches164-1,164-2of the switch arrangement164, the output terminals of the capacitors141and143are disconnected from one another and from the DC potential161.

When changing between the first switching phase PH1and the second switching phase PH2, a dynamically coupled output change takes place at the output terminals of the capacitors141and143, so that the difference between the output voltage of the second switching phase PH2(g×(−Vs+Voh+Voa)/2) and the (saved) output voltage of the first switching phase PH1(g×(+Vs+Voh+Voa)/2), e.g. g×(−Vs), is present at the output terminal of the capacitor143. Similarly, when changing between the first and second switching phases, a dynamically coupled output change takes place at the output terminal of the capacitor141, so that the difference between the output voltage of the second switching phase PH2(g×(+Vs+Voh+Voa)/2) and the (saved) output voltage of the first switching phase PH1(g×(−Vs+Voh+Voa)/2), e.g. g×(+Vs), is present at the output terminal of the capacitor143. In the second switching phase PH2of a switching cycle in the energy-saving mode, a differential voltage of g×(−2Vs) is thus present at the differential output amplifier input181,182.

In the energy-saving mode, the amplifier circuit100can thus be operated as what is known as a correlated double-sampling switched-capacitor amplifier. Correlated double sampling is a sampling technique that also eliminates the offset. The signal+offset and signal-offset are sampled twice, and the sum then simply formed (→double output signal). Correlated double sampling can give rise to aliasing effects, e.g. can reflect high frequency interference signals or noise signals into the useful frequency range. The susceptibility to interference and noise are thus fundamentally higher than in the case of chopping. With this technique, however, the complete and offset-free signal can be obtained in only two correlated double-sampling phases, which therefore saves a large amount of energy.

In the energy-saving mode, the amplifier circuit100can thus sample the (amplified) input signal (Vs) originating from the Hall sensor150(or another signal source) in sequential switching cycles. A comparison of sequential sample values can, for example, serve as a basis for the decision as to whether to change from the energy-saving mode into the normal mode of the amplifier circuit100. For example, when using the Hall sensor150to detect rotating magnetic fields, a change in the arithmetic sign between sequential sampling values can indicate a change between magnetic half-planes or quadrants. In the energy-saving mode, the amplifier circuit100can thus be used as a magnetic quadrant or rotation counter. In addition or alternatively, it is possible, for example, to change from the energy-saving mode into the normal mode in response to a change in arithmetic sign between sequential sampling values, in order to measure the rotating magnetic field continuously in time. Expressed in different words, the amplifier circuit100can thus be configured to compare, in energy-saving mode, a first output signal of the output amplifier circuit180from the second switching phase PH2of a switching cycle610with a second output signal of the output amplifier circuit180from the second switching phase PH2of a subsequent switching cycle610and, in the event of a change in the arithmetic sign between the first and second output signals, to change from the energy-saving mode into the normal mode.

In some implementations, two Hall sensors are utilized for an angle sensor in order to acquire magnetic field components (cos (X) and sin (Y) components) of the rotating magnetic field that are offset by 90°. Such an angle sensor then comprises a first amplifier circuit100,400,500in accordance with the present disclosure coupled to a first Hall sensor (configured for spinning current operation). The angle sensor also comprises a second amplifier circuit100,400,500in accordance with the present disclosure coupled to a second Hall sensor (configured for spinning current operation). The first Hall sensor is sensitive to a first magnetic field direction. The second Hall sensor is sensitive to a second magnetic field direction (perpendicular to the first magnetic field direction). The first amplifier circuit is configured in the first operating mode to compare a first output signal of its output amplifier from the second switching phase of a switching cycle to a second output signal of its output amplifier from the second switching phase of a subsequent switching cycle to obtain a first comparison signal. The second amplifier circuit is configured in the first operating mode to compare a first output signal of its output amplifier from the second switching phase of a switching cycle to a second output signal of its output amplifier from the second switching phase of the subsequent switching cycle to obtain a second comparison signal. In the event that the first and/or the second comparison signal demonstrates a change in the arithmetic sign between the respective first and second output signals, the angle sensor is configured to change from the energy-saving mode into the normal mode. The change in arithmetic sign is an indicator for a change in the magnetic quadrant.

A change between the energy-saving mode and the normal mode is shown with reference to a switch diagram800ofFIG.8.

In the temporal sequence illustrated inFIG.8, the amplifier circuit, or the angle sensor, is initially in the energy-saving mode. A first switching cycle610-1, in whose switching phase PH2a first sampling value is provided, is followed by a sleep time period620. The sleep time period620is followed by a further switching cycle610-2, in whose switching phase PH2a second sampling value is provided. A change in the arithmetic sign is now, for example, established between the first sampling value and the second sampling value, so that the amplifier circuit changes from the energy-saving mode into the normal mode. A switching cycle610-3,610-4then directly follows the switching cycle610-2, and so on.

A mode of operation of a magnetic quadrant or rotation counter is shown inFIG.9.

In the first quadrant (0°-90°) both the X and Y components of the rotating magnetic field are positive. On changing from the first quadrant into the second quadrant (90°-180°) the X component changes its arithmetic sign from + to − (the Y component remains+), so that, for example, the arithmetic sign of an output signal of the first amplifier circuit of the angle sensor would change from + to −. On changing from the second quadrant into the third quadrant (180°-270°) the Y component changes its arithmetic sign from + to − (the X component remains −), so that, for example, the arithmetic sign of an output signal of the second amplifier circuit of the angle sensor would change from + to −. On changing from the third quadrant into the fourth quadrant (270°-360°) the X component changes its arithmetic sign from − to +(the Y component remains −), so that, for example, the arithmetic sign of an output signal of the first amplifier circuit of the angle sensor would change from − to +. On changing from the fourth quadrant into the first quadrant the Y component changes its arithmetic sign from − to +(the X component remains+), so that, for example, the arithmetic sign of an output signal of the second amplifier circuit of the angle sensor would change from − to +. A rotation counter can be incremented simultaneously at the transition from the fourth quadrant into the first quadrant.

Some implementations described herein offer circuits with double usage combined with very low area and power. Circuits can be operated in a duty-cycled, low-power, switched-capacitor comparator mode and in a time-continuous operating mode with high-speed, low jitter, and a short latency time. Some implementations enable a conditional switching between two types of operation by recognizing a change in arithmetic sign from one sample to the next sample, or after a defined period in the time-continuous operating mode. Some implementations thus enable a self-waking and/or a wake-up signal for a microprocessor (RP).

Some implementations can thus realize a very low-current sensor with a wake-up function that is capable of providing a self-awake signal in order to change into a fast, low-jitter/low-latency mode, and to provide a wake-up signal for a sleeping RP or a system in response to signal changes. In some implementations, very low current and fast operation (of, for example, a quadrant or rotation counter) are highly in conflict. Circuits that are optimized in very different ways and that require much more surface area are usually required for each of these.

The aspects and features that are described in association with a specific one of the above implementations can also be combined with one or a plurality of the further implementations in order to replace an identical or similar feature of this further implementation, or in order to introduce the feature additionally into the further implementation.

It is furthermore to be understood that the disclosure of a plurality of steps, processes, operations or functions in the description or the claims does not necessarily have to be implemented in the sequence described, unless this is explicitly stated in individual cases or is necessarily required for technical reasons. The performance of multiple steps or functions is therefore not limited to a specific sequence by the previous description. In further examples, furthermore, a single step, a single function, a single process or a single operation may include multiple partial steps, functions, processes or operations, and/or may be decomposed into these.

If individual aspects in the preceding sections have been described in connection with an apparatus or system, these aspects are also to be understood as a description of the corresponding method. For example, a block, an apparatus or a functional aspect of the apparatus or of the system can correspond here to a feature, such as a method step, of the corresponding method. In accordance with this, aspects that are described in association with a method are also to be understood as a description of a corresponding block, a corresponding element, a property or a functional feature of a corresponding apparatus or of a corresponding system.

The following claims are hereby incorporated into the detailed description by reference, while each claim can itself stand alone as a separate example. It is furthermore to be borne in mind that—although an independent claim in the claims relates to a specific combination with one or a plurality of other claims—other examples may also comprise a combination of the dependent claim with the subject matter of any of the other dependent or independent claims. Such combinations are hereby explicitly suggested, provided it is not stated in individual cases that a specific combination is not intended. Furthermore, features of one claim should also be included for every other independent claim, even when this claim is not directly defined as dependent on that other independent claim.