Patent ID: 12212317

DETAILED DESCRIPTION

In a stacked transistor configuration, the node interconnecting two transistors may float during operation of the circuit containing the stacked transistors. Further, due to parasitic capacitance between a gate and a drain of one of the transistors of the stack, the voltage on the floating node interconnecting the transistors may fall below ground (negative voltage) thereby potentially causing a drain-to-source voltage (VDS) of one of the transistors in the stack to exceed the supply voltage while the gate-to-source voltage (VGS) of the same transistor is greater than zero but below the transistor's threshold voltage (VT). Subjecting a transistor to an elevated VDS (e.g., in excess of the circuit's VDD supply voltage) while also operating the transistor in the sub-threshold region can cause non-conductive stress on the transistor possibly leading to degradation in the performance of the transistor over time and even the transistor's failure.

The described examples address this problem. The examples herein pertain to a transistor stack (two or more serially-connected transistors). Many types of circuits use transistor stacks. Examples of such circuits include NAND gates, NOR gates, and flip-flops. The described examples are directed to NAND gates for illustrative purposes, but the scope of this disclosure is not limited to NAND gates.

FIG.1shows an embodiment of a NAND gate100including transistors M1, M2, M3A, M4, and M5. Each transistor M1, M2, M3A, M4, and M5includes a control input and a pair of current terminals. In the example ofFIG.1, transistors M1and M2are n-channel metal oxide semiconductor field effect transistors (NMOS devices) and transistors M3A, M4, and M5are p-channel metal oxide semiconductor field effect transistors (PMOS devices). As such, the control inputs are the gates of the respective transistors and the current terminals are the drains and sources of the respective transistors. In other implementations, any of the transistors shown inFIG.1can be of the opposite doping type from that shown. For example, M1can be implemented as PMOS device. Further, any or all of the transistors shown inFIG.1can be implemented as bipolar junction transistors or other transistor types. As bipolar junction transistors, the control inputs are the bases of the transistors and the current terminals are the emitters and collectors.

M1and M2form a transistor stack110. The source of M1is connected to the drain of M2thereby defining an intermediate node N1. The source of M2is connected to a ground node115. The drain of M1is connected to the drains of M4and M5at node N2and the sources of M4and M5are connected to a supply voltage node120(VDD).

The gates of M1and M4are connected together and receive a control signal CTL_A. The gates of M2and M5are connected together and receive a control signal CTL_B. The output (OUT) from circuit100is the node N2interconnecting the drains of M1, M4, and M5as shown. As a NAND gate, the inputs are the control signals CTL_A and CTLB and the output is OUT. When both CTL_A and CTL_B are logic high (“1”), both NMOS devices M1and M2are on and both the PMOS device M4and M5are off. With both M1and M2being on, OUT is pulled low to ground and thus is logic low (“0”). When either or both of CTL_A or CTL_B are low, their respective NMOS device M1or M2is turned off thereby disconnecting OUT from the ground potential of the ground node115. Further, when either or both of CTL_A or CTL_B are low, their respective PMOS device M4or M5is turned on thereby pulling OUT up to the VDD potential of the power supply node120. As such, OUT is only low when both CTL_A and CTL_B are low; otherwise OUT is high.

An example of timing diagrams for the operation of NAND gate100are shown inFIG.2for CTL_A, CTL_B, the source voltage of M1(VS_M1), and the VDS of M1(VDS_M1). At130, both CTL_A and CTL_B are high, which causes both of M1and M2to be on. At time t1, CTL_A transitions from high to low, while CTL_B remains high. VS_M1is low due to M2to being on and connected to ground. Further, VDS_M1is low because M1is on.

At time t2, CTL_B transitions from high to low. Ignoring M3A for the time being, upon CTL_B transitioning from high to low, M2turns off. As M2turns off (and assuming M3A is not present in the circuit), intermediate node N1floats. With N1floating, parasitic capacitance between the gate and drain of M2(as shown by parasitic capacitance CP inFIG.1) causes the voltage on N1to fall below the ground potential and, if that were to happen, the voltage on the source of M1decreases below ground and VDS_M1increases to a voltage above VDD. In this state, M1is operating in the subthreshold region as its VGS is greater than 0 but less than its VT while its VDS is above VDD thereby causing impairment of the long-term reliability of the circuit.

The inclusion of M3A, however, solves this problem. The drain of M3A is connected to the intermediate node N1and the source of M3A is connected to the ground node115. When M3A is on, intermediate node N1is biased to ground. The gate of M3A is controlled by a control signal labeled as CTL_A_INV. CTL_A_INV is of the opposite polarity as CTL_A. In one example, an inverter can be included to invert CTL_A to produce CTLA_INV. When M1is off due to CTL_A being low, M3A is on due to CTL_A_INV being high. M3A being on thereby imposes a direct current (DC) bias voltage on N1(ground in this example). By DC biasing the intermediate node N1at the ground potential, the reduction in voltage on N1(VS_M1) due to M2turning off and the parasitic gate-to-drain capacitance of M2is significantly less than would be the case absent M3A.

AsFIG.2show, VS_M1is at 0V while CTL_B is high (which forces M2to be on). When CTL_A transitions from high to low at t1, CTL_A_INV transitions from low to high thereby turning on M3A and DC biasing N1to ground starting at t1. Node N1remains biased to ground even after CTL_B transitions low at t2turning M2off due to the continued operation of M3A in the on state. A small downward momentary drop in VS_M1may be present as indicated at150. A small and short duration increase in VDS_M1is also present as shown at160due to decrease in VS_M1at150, but the upward blip of VSS_M1is much smaller in both magnitude and duration than would have been the case had M3A not been present.

The example ofFIG.1shows a transistor stack comprising two transistors M1and M2. The described principles forFIG.1and the other figures/examples apply as well to transistor stacks comprising more than two transistors.

FIG.3shows an example of a NAND gate200including some of the same components (e.g., M1, M2, M4, and M5) as in the example ofFIG.1. The NAND gate200ofFIG.3includes a transistor M3B to impose a DC bias on intermediate node N1. In this example, M3B is a PMOS transistor whose source is connected to the supply voltage node120and whose drain is connected to intermediate node N1. The gate of M3B is connected to the gate of M2and thus is controlled by the same control signal (CTL_B) as M2. An inverter is not needed to generate the control signal for M3B. As M2is an NMOS transistor and M3B is a PMOS transistor, M2will be on and M3B off when CTL_B is high, and M2will be off and M3B on when CTL_B is low. Because M3B is connected to VDD, when M2is caused to transition from on to off, M3B is turned on thereby providing a DC bias on node N1approximately equal to VDD. This DC bias prevents the voltage on node N1(VS_M1) from becoming negative.

FIG.4shows an example of waveforms pertaining toFIG.3. As inFIG.2, CTL_A is forced low at time t1and CTL_B is forced low at time t2. Prior to t1, with both M1and M2on, VS_M1is pulled low to ground. Between t1and t2, VS_M1remains low because M2is still on. When M2is turned off at t2, M3B is turned on thereby forcing MS_M1to become high as shown at t2(405). VDS_M1is low prior to t1because M1is on prior to t1. Once M1turns off at t1, M4turns on thereby causing the drain of M1to become high. With M2still on between t1and t2, the source of M1(voltage on node N1) is low and thus VDS_M1is high between t1and t2as shown at410. Once M2also turns off at t2, the source of M1becomes high due to M3B being on. M4continues to be on due to CTL_A being low and the voltage on the drain of M1remains high. Thus, VDS_M1drops to zero again at edge420. The VDS_M1voltage does not increase above VDD thereby avoiding or at least reducing the problem noted above.

FIG.5shows an example of a NAND gate300including some of the same components (e.g., M1, M2, M4, and M5) as in the example ofFIG.1. The NAND gate300ofFIG.5includes a capacitor CS1connected between intermediate node N1and ground. CS1can be implemented as a device capacitor, a MOS transistor whose drain and source are connected together so that the gate is one terminal of the capacitor and the drain/source connection is the other terminal of the capacitor, or any other type of capacitive device. In one example, extra “dummy” transistors may be available on a semiconductor die that can be configured to be capacitor CS1.FIG.6shows an example of an implementation of the capacitor (CS1) by utilizing the dummy structures around actual transistor (M2). Gates604of the dummy structures connect to ground115(FIG.5.) and the drain and source connect to node N1(FIG.5) shared with M2.

Capacitor CS1limits the charge coupling from the gate of M2to the intermediate node N1. The size of capacitor CS1is application-specific.FIG.7shows an example of waveforms pertaining toFIG.5. As inFIG.2, CTL_A is forced low at time t1and CTL_B is forced low at time t2. Prior to t1, with both M1and M2on, VS_M1is pulled low to ground. Between t1and t2, VS_M1remains low because M2is still on. When M2is turned off at t2, the voltage on node N1(VS_M1) drops slightly (ΔV) due to the parasitic capacitance CP as shown at702. However, the drop in VS_M1voltage is not as large as would be the case without CS1. Negative charge on N1dissipates through device leakage and VS_M1then begins to increase as shown at705. VDS_M1is zero volts while M1is on; once M1turns off and M4turns on, VDS_M1increases to VDD as shown at time t1. VDS_M1remains at VDD until t2at which time M2turns off and VS_M1drops below zero at702and charges back up to zero volts at705as negative charge dissipates through device leakage. The drain of M1remains fixed at VDD, but the source of M1drops and then rises. The drop and then rise of VS_M1is thus reflected in VDS_M1as shown at710. The increase in VDS_M1above VDD also is ΔV and is less than would be the case absent CS1.

FIG.8shows an example of a NAND gate400including some of the same components (e.g., M1, M2, M4, and M5) as in the example ofFIG.1. The NAND gate400ofFIG.8includes a capacitor CS2with one terminal being connected to intermediate node N1and the other terminal receiving a control voltage CTL_B_INV (opposite polarity of CTL_B, generated, for example, by an inverter). CS2can be implemented as described above regarding CS1. Through capacitor CS2, opposite charge is provided to node N1from that caused by the parasitic capacitor CP. That is, to a certain degree, capacitor CS2provides charge balancing on node N1thereby reducing the large downward drop in voltage on N1that would otherwise be the case in the absence of CS2. The coupling efficiency is given by Cp/Ctotal, where Ctotal is the total capacitance of the intermediate node N1. In the case of CS1connected to ground, the coupling efficiency is decreased per Cp/(Cotal+CS1). In the case of CS2since the opposite terminal of CS2is also switching between VDD and GND the coupling efficiency is reduced per Cp(Cotal+2*CS2). Thus, the ratio of voltages from without either CS1or CS2as compared to inclusion of CS1or CS2is, in the case of CS1Ctotal/(Ctotal+CS1) and in the case of CS2Ctotal/(Ctotal+2*CS2).

FIG.9shows the waveforms pertaining to the operation of the NAND gate400ofFIG.8. The waveforms for CTL_A, CTL_B, VS_M1, and VDS_M1are largely the same as inFIG.2and described above. A small drop in VS_M1may be present as identified at810in the waveforms ofFIG.9. A corresponding small increase in VDS_M1also may be present as shown at915.

In this description, the term “couple” or “couples” means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.