Patent ID: 12224265

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the three-dimensional (3D) packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

It should be appreciated that the following embodiment(s) of the present disclosure provides applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiment(s) discussed herein is merely illustrative and is related to a three-dimensional (3D) integration structure or assembly, and does not limit the scope of the present disclosure. Embodiments of the present disclosure describe the exemplary manufacturing process of 3D stacking structures and the 3D stacking structures fabricated there-from. Certain embodiments of the present disclosure are related to the 3D stacking structures formed with wafer bonding structures and stacked wafers and/or dies. Other embodiments relate to 3D integration structures or assemblies including post-passivation interconnect (PPI) structures or interposers with other electrically connected components, including wafer-to-wafer assembled structures, die-to wafer assembled structures, package-on-package assembled structures, die-to-die assembled structures, and die-to-substrate assembled structures. The wafers or dies may include one or more types of integrated circuits or electrical components on a bulk semiconductor substrate or a silicon/germanium-on-insulator substrate. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure.

FIG.1illustrates a cross-sectional view of a portion of an exemplary 3D stacking structure in accordance with some embodiments of the present disclosure. InFIG.1, the 3D stacking structure20comprises at least a first die100′, a second die200′, a third die300, a fourth die400and an encapsulant500′. In some embodiments, the first die100′ includes first metallization structures104. In some embodiments, the second die200′ includes second metallization structures204. The first die100′ is stacked on a first side of the second die200′, and the first metallization structures104are connected with the corresponding second metallization structures204. The first die100′ is hybrid-bonded with the second die200′. In one embodiment, the third die300and the fourth die400are stacked on a second side of the second die200′ opposite to the first side. The third die300and the fourth die400are electrically connected with the second die200′ and the first die100′. The third die300and the fourth die400are hybrid-bonded with the second die200′. The 3D stacking structure20further comprises a redistribution layer (RDL)610disposed on the first die100′ and posts630located on the RDL610.

FIGS.2A-2Hillustrate the cross-sectional views showing various stages of the manufacturing methods for forming the 3D stacking structure according to some embodiments of the present disclosure. InFIG.2A, in some embodiments, a first wafer100is provided, and the first wafer100includes first metallization structures104formed in a first semiconductor substrate102and a first bonding film106covering the semiconductor substrate102and the first metallization structures104. In some embodiments, the first wafer100is a semiconductor wafer made of silicon (such as a silicon bulk wafer) or other semiconductor materials, such as III-V semiconductor materials. In some embodiments, the material of the first bonding film106includes silicon oxide, silicon nitride, undoped silicate glass material or a combination thereof. In some embodiment, the bonding film may be formed through performing a chemical vapor deposition (CVD) process such as low-pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and high-density plasma CVD (HDPCVD). In addition, the first wafer100may further includes semiconductor devices (not shown) and isolation structures (not shown). In some embodiments, the first wafer100includes a plurality of first dies100′ (only one is shown inFIG.2A). It is understood that the number of the first dies100′ is merely exemplary, and the first dies100′ may be the same type of dies or different type of dies. In certain embodiments, the semiconductor devices may be formed in the semiconductor wafer100during the front-end-of-line (FEOL) processes. In certain embodiments, the semiconductor devices are transistors, memories or power devices, or other devices such as capacitors, resistors, diodes, photo-diodes, sensors or fuses. In exemplary embodiments, some of the semiconductor devices may be electrically connected with the first metallization structures104.

As shown inFIG.2A, in certain embodiments, the first metallization structures104are through substrate vias (TSVs) embedded within the semiconductor substrate102. In some embodiments, the first metallization structures104include metal vias, having a critical dimension S1and extending from the top surface102a(contact surface of the substrate102and the bonding film106) of the substrate102into a first depth d1of the semiconductor substrate102. In one embodiment, the metal vias have tilted sidewalls and have a shape of truncated cones. In one embodiment, the metal vias have substantially vertical sidewalls and have a shape of cylinders. In some embodiments, the depth (length) d1of the first metallization structures104ranges from about 20 microns to 30 microns. In some embodiments, the critical dimension S1of the first metallization structures104ranges from about 0.5 microns to about 5 microns. In some embodiments, the critical dimension S1of the first metallization structures104is about 1-2 microns. In some embodiments, the first metallization structures104may be metal vias having an aspect ratio of about 5-10. In certain embodiments, the materials of the metallization structures104include aluminum (Al), aluminum alloy, copper (Cu), copper alloys, tungsten (W), or combinations thereof.

InFIG.2B, in some embodiments, a second wafer200is provided, and the second wafer200includes second metallization structures204formed in a second semiconductor substrate202and a second bonding film206covering the semiconductor substrate202. In some embodiments, the material of the second bonding film206includes silicon oxide, silicon nitride, undoped silicate glass material or a combination thereof. In some embodiment, the bonding film may be formed through performing a chemical vapor deposition (CVD) process such as low-pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and high-density plasma CVD (HDPCVD). In some embodiments, the second metallization structures204are not covered but exposed from the second bonding film206. In some embodiments, the second wafer200is a semiconductor wafer similar to the first wafer100. In some embodiments, the second wafer200is a different type of wafer from the first wafer100. In some embodiments, the second wafer200is a bulk silicon wafer, and the second wafer200may function as an interposer or a structural support. In certain embodiments, the second wafer200may further includes semiconductor devices (not shown) and isolation structures (not shown). In some embodiments, the second wafer200includes a plurality of second dies200′ (only one is shown inFIG.2B). It is understood that the number of the second dies200′ is merely exemplary, and the second dies200′ may be the same type of dies as the first dies100′ or different type of dies from the first dies100′. In exemplary embodiments, if the wafer200has semiconductor devices therein, some of the semiconductor devices may be electrically connected with the second metallization structures204.

In some embodiments, the first dies100′ and the second dies200′ have different functions. In some embodiments, the first dies100′ and the second dies200′ have the same functions. In some embodiments, the first die100′ or the second die200′ includes a memory chip such as a high bandwidth memory chip, a dynamic random access memory (DRAM) chip or a static random access memory (SRAM) chip. In some alternative embodiments, the first die100′ or the second die200′ includes an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless application chip such as a Bluetooth chip and a radio frequency chip or a voltage regulator chip.

As shown inFIG.2B, in certain embodiments, the second metallization structures204are through substrate vias (TSVs) embedded within the semiconductor substrate202. In some embodiments, the second metallization structures204include metal vias, having a critical dimension S2and extending from the top surface206aof the bonding film206into a second depth d2of the semiconductor substrate202. In one embodiment, the metal vias have tilted sidewalls and have a shape of truncated cones. In one embodiment, the metal vias have substantially vertical sidewalls and have a shape of cylinders. In some embodiments, the second metallization structures204may be metal vias having an aspect ratio of about 5-10. In some embodiments, the critical dimension S2of the second metallization structures204ranges from about 1.0 micron to about 10 microns. In some embodiments, the critical dimension S2of the second metallization structures204is about 4-6 microns. In certain embodiments, the critical dimension S2of the second metallization structures204is larger than the critical dimension S1of the first metallization structures104. In some embodiments, the depth (length) d2of the second metallization structures204ranges from about 30 microns to 40 microns. In certain embodiments, the material of the second metallization structures204is the same as that of the first metallization structures104. In certain embodiments, the material of the second metallization structures204is different from that of the first metallization structures104.

As shown inFIG.2C, the first wafer100is flipped (turned upside down) and placed on a carrier C1with the bonding film106located directly on the carrier C1. In some embodiments, the carrier C1is a semiconductor wafer, a silicon carrier or a glass carrier. Then, the first wafer100is thinned down from the backside until the ends of the first metallization structures104are exposed. In some embodiments, the thickness of the thinned first wafer100is about 20-30 microns.

Later, inFIG.2C, the second wafer200is flipped (turned upside down) and placed on the thinned first wafer100with the bonding film206located directly on the thinned first wafer100. During the placement of the second wafer200, the second metallization structures204are substantially vertically aligned with the corresponding first metallization structures104respectively. In some embodiments, the first metallization structures104are considered as the first tier (Tier 1, T1) TSVs and the second metallization structures204are considered as the second tier (Tier 2, T2) TSVs, and the T2TSVs are stacked and aligned with the T1TSVs. In some embodiments, as the critical dimension of the second metallization structure is different from that of the first metallization structure, alignment tolerance becomes larger and reliable bonding is achieved. In certain embodiments, as shown inFIG.2C, the critical dimension S2of the second metallization structure204is larger than the critical dimension S1of the first metallization structure104.

Then, in some embodiments, as shown inFIG.2C, a bonding process is performed to bond the first and second metallization structures104,204to each other so as to bond the first and second wafers. In some embodiments, the bonding process is a hybrid bonding process. In one embodiments, during the application of hybrid bonding technology, a low temperature heating process at a temperature of about 100° C. to about 200° C. is performed to heat and bond the dielectric bonding film206to the semiconductor substrate102and a high temperature heating process is performed at a temperature of about 200° C. to about 300° C. to heat the metallization structures104,204such that the conductive metallization structures104,204are bonded and the dielectric bonding film206is cured and adhered to the semiconductor substrate102. In some embodiments, the second wafer200is hybrid bonded to the thinned first wafer100through hybrid bonding. That is, as shown in the partially enlarged view at the right part ofFIG.2C, the bonding film206of the second wafer200is bonded to the semiconductor substrate102(such as silicon) of the thinned first wafer100, and the second metallization structures204are bonded with the first metallization structures104, thus achieving a hybrid bonding interface HB (represented by the dotted line inFIG.2C). In one embodiment, in addition to the metal-to metal bonding interfaces established by the first and second metallization structures104,204, the hybrid bonding interface HB includes dielectric material to semiconductor material bonding interfaces established by the semiconductor substrate102and the dielectric bonding film206. In some embodiments, the bonded first and second metallization structures104,204are further electrically connected with interconnect structures103and metallic contact pad(s)101formed in the first die(s) of the first wafer100. In addition, as shown in the partially enlarged view at the right part ofFIG.2C, the semiconductor devices1050in the device layer105are electrically connected with the first metallization structures104through the interconnect structures103in the first wafer100. Then, in some embodiments, the second wafer200is also thinned down from the backside until the ends of the second metallization structures204are exposed. In some embodiments, the thickness of the thinned second wafer200is about 30-40 microns. In some embodiments, the thinning down process of the first or second wafer may include a polishing process, an etching process or a combination thereof. In some embodiments, the second wafer200may function as an interposer or a structural support. In other embodiments, the second wafer200includes semiconductor devices (not shown), which may be electrically connected with the second metallization structure204and further electrically connected with the semiconductor devices in the first wafer100.

In embodiments, the first or second wafer or both wafers are provided with metallization structures having a higher aspect ratio (i.e. small critical dimension along with a longer length), less areas are occupied by the metallization structures and more active area are offered. After the first and second wafers are bonded together, the total thickness of the stacked first and second wafers is increased for better structural robustness. Also, due to the high aspect ratios of the first and second metallization structures, the first and second metallization structures do not occupy too much active areas, and the layout design for the semiconductor device(s) is flexible.

InFIG.2D, a third die300and a fourth die400are provided and disposed side-by side on the backside of the second wafer200. In some embodiments, the third die300and the fourth die400are provided with hybrid bonding structures310,410. In some embodiments, a bonding process is performed to bond the third die300and the fourth die400with the second wafer200. In some embodiments, the bonding process is a hybrid bonding process including performing a thermal process at a temperature ranging from 100° C. to 400° C. under a pressure of about 100˜1000 mtorr. As shown inFIG.2D, the hybrid bonding structure310includes conductive features312embedded in a dielectric material314formed on the active surface of the third die300. In some embodiments, the hybrid bonding structure410includes conductive features412embedded in a dielectric material414formed on the active surface of the fourth die400. In some embodiments, the front side of the third die300is hybrid-bonded to the backside of the second wafer200through the hybrid bonding structure310. That is, the conductive features312are bonded with the second metallization structures204, while the dielectric material314is bonded with the semiconductor material (such as silicon) of the substrate202of the second wafer200. In some embodiments, the front side of the fourth die400is hybrid-bonded to the backside of the second wafer200through the hybrid bonding structure410. That is, the conductive features412are bonded with the second metallization structures204, while the dielectric material414is bonded with the semiconductor material (such as silicon) of the substrate202of the second wafer200. In these embodiments, the metallization structure of the first and second dies or the through-substrate vias (TSVs) of the first and second dies may be considered as parts of hybrid bonding structures for establishing shorter and direct electrical paths. Also, the hybrid bonding structures of the third or fourth die described in the above embodiments are compatible with the TSVs.

Optionally, in some embodiments, the third die300or the fourth die400may be thinned down from the backside to a desirable thickness. In some embodiments, the thinning down process of the third die300or the fourth die400may include a polishing process, an etching process or a combination thereof.

Referring toFIG.2D, one third die300and one fourth die400are provided over the second wafer200. It is understood that the number of the third or fourth die may be one, two or more than two, but the disclosure is not limited thereto. In some embodiments, the third die300and the fourth die400have different functions. In some embodiments, the third die300and the fourth die400have the same function. In some embodiments, the third die300or the fourth die400includes a memory chip such as a high bandwidth memory chip, a dynamic random access memory (DRAM) chip or a static random access memory (SRAM) chip. In some alternative embodiments, the third die300or the fourth die400includes an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless application chip such as a Bluetooth chip and a radio frequency chip or a voltage regulator chip. In one embodiment, the third die300includes a memory chip, and the fourth die400includes an ASIC chip. Although not expressly shown inFIG.2D, some of the conductive features of the third die or the fourth die are electrically interconnected to one another and some of the conductive features are electrically connected with the underlying semiconductor devices in the third die or fourth die. The third die300and the fourth die400are electrically connected with the second die(s)200′ and/or the first die(s)100′.

In exemplary embodiments, the conductive features312,412are made of conductive materials, such as copper (Cu), copper alloys, aluminum (Al), aluminum alloys, nickel (Ni), solder materials or combinations thereof. In some embodiments, a material of the dielectric material314,414includes silicon oxide, silicon nitride, or silicon oxynitride (SiON).

In some embodiments, inFIG.2E, an encapsulant500is formed over the stacked structure40of the first wafer100, the second wafer200, the third die300and the fourth die400and at least laterally covers the third die300and the fourth die400mounted on the second wafer200. The encapsulant500covers the backside of the second wafer200, fills the gaps between the third die300and the fourth die400and wraps around the sidewalls of the third die300and the fourth die400. In some embodiments, the encapsulant500is formed by a molding process such as over-molding and then polished or planarized to expose the backsides of the third die300and the fourth die400. In some embodiments, the material of the encapsulant500includes epoxy resins, phenolic resins or silicon-containing resins.

InFIG.2F, the stack structure40is flipped and transferred to another carrier C2. In some embodiments, the carrier C1includes a silicon carrier and the carrier C1is removed by performing a grinding process and/or a polishing process (such as a chemical mechanical polishing process) and the bonding film106may be removed along with the carrier C1. After the carrier C1and the bonding film106are removed, the first metallization structures104are exposed. In certain embodiments, the carrier C2is a glass carrier.

InFIG.2G, in some embodiments, a redistribution layer (RDL)610is formed over the first wafer100covering the first metallization structure104. The redistribution layer (RDL)610is formed over the stack structure40and is electrically connected to the die stack structure40. In some embodiments, the RDL610includes redistribution patterns612embedded in at least one dielectric material layer614. The number of the redistribution patterns or the dielectric material layer is not limited by the disclosure. The redistribution patterns612includes routing patterns and bump pads, for example. In certain embodiments, an insulating layer620is formed on the RDL610. For example, the insulating layer620is formed with openings O1exposing some of the underlying redistribution patterns612. Then, metal posts630and glops640are formed in the openings O1. In some embodiments, the material of the dielectric material layer614or the insulating layer620includes silicon oxide, silicon nitride, benzocyclobutene (BCB), epoxy, polyimide (PI), or polybenzoxazole (PBO). In some embodiments, a material of the metal posts includes copper or cooper alloys, and a material of the glops640includes solder. Herein, the metal posts630and glops640located on the metal posts630constitute micro bump structures650. In alternative embodiments, only the metal posts630are formed in the openings O1and connected to the bump pads in the underlying redistribution patterns612.

Later, in some embodiments, after separating the stack structure40from the carrier C2, inFIG.2H, a singulation process is performed to cut the stack structure40into individual 3D stacking structures22. In some embodiments, the singulation process includes a wafer dicing process or a sawing process. Each of the stacking structures22includes at least the first die100′, the second die200′, the third die300, the fourth die400and the encapsulant500′ wrapping around the third and fourth dies. In some embodiments, through the direct bonded metallization structures and hybrid bonding structures, shorter connection path(s) is established and the reliability of the 3D stacking structures22is improved.

Although the steps of the method are illustrated and described as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. In addition, not all illustrated process or steps are required to implement one or more embodiments of the present disclosure. As the 3D stacking structure20or22includes multiple dies stacked on one another and connected with one another through hybrid bonding, the stacked dies are integrated in a compact form through direct bonding as well as hybrid bonding. In some embodiments, the 3D stacking structure20,22may be considered as an integrated circuit (IC) die or a system-on-integrated-chip (SoIC) die.

FIG.3illustrates a cross-sectional view of a portion of an exemplary 3D stacking structure in accordance with some embodiments of the present disclosure. InFIG.3, the 3D stacking structure24includes at least the first die100″, the second die200″, the third die300, the fourth die400and the encapsulant500″ wrapping around the third and fourth dies300,400. In addition, the structure24includes a redistribution layer610, an insulating layer620and micro bump structures650on the stacked structure of the first die100″ and the second die200″. Compared with the 3D stacking structure22, the main structural difference of the 3D stacking structure24lies in that a filling material33laterally wraps around the stacked structure of the first die100″ and the second die200″. In some embodiments, the material of the filling material33includes silicon oxide, and the material of the filling material33is different from that material of the encapsulant500″. Except for the similar manufacturing processes as described above, the first die100″ and the second die200″ are provided in the singulated form as individual dies, rather than being provided in the wafer form. In some embodiments, after the first die100″ and the second die200″ are stacked and hybrid-bonded through the first and second metallization structures104,204and bonding film206, a filling material33is supplied to cover first die(s)100″ and the second die(s)200″ and a planarization process may be performed to form a reconstructed wafer or panel. The other following manufacturing processes are similar or the same as those described in the previous embodiments, and details are skipped herein.

In exemplary embodiments, the 3D stacking structures20,22,24as described above may be additional processed in the subsequent processes to be connected with further connection structures before dicing, and these subsequent processes may be modified based on the product design and will not be described in details herein.

FIGS.4A-4Fillustrate enlarged cross-sectional views of hybrid bonding portions of an exemplary 3D stacking structure in accordance with various embodiments of the present disclosure.

InFIGS.4A &4B, in some embodiments, the second metallization structure204A,204B of the second die200A,200B has a critical dimension S2larger than a critical dimension S1of the first metallization104A,104B of the first die100A,100B. InFIG.4A, the second metallization structure204A penetrates through the bonding film206A1. The first metallization structure104A includes a metal bonding pad104A1embedded in the bonding film206A2and a metal via104A2connected with the metal bonding pad104A1. InFIG.4A, a hybrid bonding interface HB (represented by the dotted line) is formed between the bonding films206A1,206A2and between the first and second metallization structures204A,104A. In one embodiment, in addition to the metal-to metal bonding interfaces established by the first and second metallization structures104A,204A, the hybrid bonding interface HB includes dielectric material to dielectric material bonding interfaces established by the dielectric bonding films206A1,206A2. The materials of the bonding films206A1,206A2may be similar to the materials of the bonding film206described in the previous embodiments. In one embodiment, the material of the bonding film206A1is the same as the material of the bonding film206A2. In one embodiment, the material of the bonding film206A1is different from the material of the bonding film206A2.

InFIG.4B, the second metallization structure204B penetrates through the bonding film206B1. The first metallization structure104B includes a metal bonding pad104B1embedded in the bonding film206B2, a metal neck portion104B2embedded in the bonding film206B3and a metal via104B3. The metal neck portion104B2connects the metal bonding pad104B1and the metal via104B3. InFIG.4B, a hybrid bonding interface HB (represented by the dotted line) is formed between the dielectric bonding film206B1and dielectric bonding film206A2and between the first and second metallization structures204B,104B. In one embodiment, the material of the bonding film206B1is the same as the material of the bonding films206B2,206B3. In one embodiment, the material of the bonding film206B1is different from the material of the bonding films206B2,206B3. In one embodiment, the material of the bonding film206B1is the same as the material of the bonding film206B3and is different from the material of the bonding film206B2.

InFIGS.4C &4D, in some embodiments, the second metallization structure204C,204D of the second die200C,200D has a critical dimension S2smaller than a critical dimension S1of the first metallization104C,104D of the first die100C,100D. InFIG.4C, the second metallization structure204C penetrates through the bonding film206C. The first metallization structure104C directly connects with the second metallization structure204C. InFIG.4C, a hybrid bonding interface HB (represented by the dotted line) is formed between the bonding films206C and the semiconductor substrate (such as silicon) of the first die100C and between the first and second metallization structures204C,104C.

InFIG.4D, the second metallization structure204D penetrates through the bonding film206D1. The first metallization structure104D includes a metal bonding pad104D1embedded in the composite bonding films206D2,206D3and a metal via104D2connected to the metal bonding pad104D1. InFIG.4D, a hybrid bonding interface HB (represented by the dotted line) is formed between the film206D1and film206D2and between the first and second metallization structures204D,104D. InFIG.4D, another bonding film206D4is further included on the backside of the second die200D and another metal bonding pad205D is embedded in the bonding film206D4for subsequent bonding or connection.

InFIG.4E&FIG.4F, similar toFIG.4C&FIG.4D, the second metallization structure204E,204F has a critical dimension S2smaller than a critical dimension S1of the first metallization104E,104F, but the structures shown inFIG.4EandFIG.4Ffurther includes signal through vias. InFIG.4E, in some embodiments, the first die100E includes first signal through vias114E penetrating through the semiconductor substrate102E and directly connected with the interconnect structures103E in the device layer105E. The first signal through via114E is electrically connected with the metallic contact pad101E through the interconnect structures103E. In some embodiments, the second die200E includes second signal through vias214E penetrating through the semiconductor substrate202E and directly connected with the interconnect structures203E in the device layer255E. The second signal through via214E is electrically connected with the metallic contact pad201E through the interconnect structures203E. The second die200E also includes a third signal through via215E extending between the metallic contact pad201E and the first signal through via114E and penetrating through the bonding film206E. In some embodiments, the device layer includes semiconductor devices, and the semiconductor devices may include active devices, passive devices or the combinations thereof.

InFIG.4E, the first and second signal through vias114E,214E are electrically connected through the interconnect structure203E, the metallic contact pad201E and the signal through via215E. In some embodiments, the size (or critical dimension) of the first signal through via114E is different from that of the second signal through via214E. In some embodiments, the size (or critical dimension) of the first signal through via114E is substantially equivalent to that of the second signal through via214E. In some embodiments, the critical dimension of the signal through via is smaller than S1but larger than S2. In certain embodiments, the materials of the signal through via are similar to those of the metallization structures as describe above. InFIG.4E, the semiconductor devices (not shown) in the second die200E may be electrically connected with the semiconductor devices (not shown) in the first die100E through the electrical connection between the first and second signal through vias114E,214E and the third signal through via(s)215E.

In some embodiments, inFIG.4F, the first die100F includes first signal through vias114F penetrating through the semiconductor substrate102F and connected with the interconnect structures103F in the device layer105F. The first signal through via114F is electrically connected with the metallic contact pad101F through the interconnect structures103F. In some embodiments, the second die200F includes second signal through vias214F1penetrating through the semiconductor substrate202F and directly connected with the interconnect structures203F in the device layer255F, and third signal through via214F2connected with the metallic contact pad201F and penetrating through the bonding film206F1. InFIG.4F, metal bonding pads115F that respectively penetrate through the bonding films206F2,206F3connect the third signal through via214F2and the first signal through via114F as well as the first and second metallization structures104F,204F.

In some embodiments, inFIG.4F, the first, second and third signal through vias114F,214F1,214F2are electrically connected through the interconnect structure203F, the metallic contact pad201F and the metal bonding pad115F. The second die200F also includes metal bonding pads205F embedded in the bonding film206F4on the backside of the second die200F.

InFIG.4G, similar toFIG.4DandFIG.4F, the second metallization structure204G has a critical dimension S2smaller than a critical dimension S1of the first metallization104G. InFIG.4G, in some embodiments, the first die100G includes first signal through vias114G penetrating through the semiconductor substrate102G and directly connected with the interconnect structures103G. The first signal through via114G is electrically connected with the metallic contact pad101G through the interconnect structures103G. In some embodiments, the second die200G includes second signal through vias214G1penetrating through the semiconductor substrate202G and directly connected with the interconnect structures203G, and third signal through via214G2connected with the metallic contact pad201G and penetrating through the bonding films206G1/206G3. The second signal through via214G1is electrically connected with the metallic contact pad201G through the interconnect structures203G. InFIG.4G, metal bonding pads115G1and115G2that respectively penetrate through the bonding films206G2/206G4and206G6connect the third signal through via214G2and the first signal through via114G as well as the first and second metallization structures104G,204G.

InFIG.4G, in some embodiments, the size (or critical dimension) of the first signal through via114G is different from that of the second signal through via214G. In some embodiments, the size (or critical dimension) of the first signal through via114G is substantially equivalent to that of the second signal through via214G. In some embodiments, the critical dimension of the signal through via is smaller than S1but larger than S2. InFIG.4G, the semiconductor devices (not shown) in the second die200G may be electrically connected with the semiconductor devices (not shown) in the first die100G through the electrical connection between the first, second and third signal through vias114G,214G1and214G2.

In some embodiments, inFIG.4G, the first, second and third signal through vias114G,214G1,214G2are electrically connected through the interconnect structure203G, the metallic contact pad201G and the metal bonding pads115G1,115G2. The second die200G also includes a metal bonding pad205G1embedded in the bonding film206G5and metal bonding pads205G2embedded in the bonding films206G7/206G9on the backside of the second die200G. InFIG.4G, the second metallization structure204G extends between the metal bonding pad205G2and the metal bonding pad115G1.

InFIG.4G, a hybrid bonding interface HB (represented by the dotted line) is formed between the film206G1and film206G2, between the second metallization structure204G and the metallic bonding pad115G1and between the third signal through via214G2and the metallic bonding pad115G1.

FIG.5illustrates a cross-sectional view of a semiconductor package in accordance with some embodiments of the present disclosure. In some embodiment, the semiconductor package50includes at least one 3D stacking structure20surrounding by through interlayer vias (TIVs)51and laterally encapsulated in a molding compound52. A redistribution structure53is disposed on one side of the 3D stacking structure20and a plurality of conductive terminals55are connected to the redistribution structure53. The semiconductor package50further includes another package unit57having more than one dies or chips connected with the TIVs51through the conductive bumps58. In some embodiments, the semiconductor package50includes a package-on-package (POP) structure.

In exemplary embodiments, through the arrangement of at least two tiers of TSVs, there is no need to use very high aspect ratio TSVs and the production yield and reliability are significantly enhanced. Additionally, the design of two or more tier of TSVs leads to the formation of TSVs of smaller critical dimensions and provides more active areas for active devices.

In some embodiments of the present disclosure, a stacking structure is provided. The stacking structure includes a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and the second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and critical dimensions of the first through die vias are different from critical dimensions of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.

In some embodiments of the present disclosure, a stacking structure including a stack of a first die and a second die, third dies and an encapsulant is provided. The first die includes first through die vias. The second die stacked on the first die includes second through die vias. The first die is hybrid bonded with the second die through a bonding film located between the first and second dies and the first through die vias bonded with the second through die vias. Critical dimensions of the first through die vias are different from critical dimensions of the second through die vias. The third dies are disposed on the second die, and the third dies are bonded to the second through die via. The encapsulant laterally wraps around the third dies.

In some embodiments of the present disclosure, a method for forming a stacking structure is described. A first wafer with a first metallization structure is provided. The first metallization structure includes first through die vias. A second wafer with a second metallization structure is provided. The second metallization structure includes second through die vias. The second wafer is bonded onto the first wafer by bonding the second through die vias respectively with the first through die vias. The second wafer is thinned until ends of the second through die vias are exposed. Third dies are bonded onto the exposed second through die vias of the second wafer. A dicing process is performed to dice the bonded first and second wafers to form the stacking structures.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.