Patent ID: 12232314

DETAILED DESCRIPTION

Methods of improving adhesion between a photoresist and alternating conductive structures and insulating structures of a staircase structure are described, as are methods of forming semiconductor device structures (e.g., memory array blocks) including staircase structures that have the photoresist and the alternating conductive structures and insulating structures. The fabrication of the staircase structures includes forming a slot having large dimensions in the alternating conductive structures and insulating structures. Recesses are formed in the conductive structures or in the insulating structures, laterally adjacent to the slot. A photoresist is formed over the conductive structures and insulating structures, including within the slot and recesses. The recesses enable increased adhesion between the photoresist and materials of the conductive structures and insulating structures. The improved adhesion enables the formation of stairs and contact structures on the stairs that are aligned. The staircase structure formed by the methods of the disclosure has reduced numbers of defects in the contact structures on the stairs. Thus, failure of a device including the staircase structure is reduced or eliminated compared to a device formed by a conventional process of forming the staircase structure.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete description of a semiconductor structure or a complete process flow for manufacturing semiconductor device structures and the structures described below do not form a complete semiconductor device structure. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete semiconductor device structure may be performed by conventional techniques.

Drawings presented herein are for illustrative purposes only and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the term “configured” refers to a size, shape, material composition, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way.

As shown inFIG.6, a semiconductor structure100from which the staircase structure is to be formed may include a substrate102, and alternating conductive structures106and insulating structures108arranged in tiers110over the substrate102. For clarity and ease of understanding of the drawings and related description,FIG.6shows five (5) tiers110of the conductive structures106and the insulating structures108. A first tier110aincludes a first conductive structure106aand a first insulating structure108aover the first conductive structure106a; a second tier110boverlies the first tier110a, and includes a second conductive structure106band a second insulating structure108bover the second conductive structure106b; a third tier110coverlies the second tier110b, and includes a third conductive structure106cand a third insulating structure108cover the third conductive structure106c; a fourth tier110doverlies the third tier110c, and includes a fourth conductive structure106dand a fourth insulating structure108dover the fourth conductive structure106d; and a fifth tier110eoverlies the fourth tier110d, and includes a fifth conductive structure106eand a fifth insulating structure108eover the fifth conductive structure106e. However, the semiconductor structure100may include a different number of tiers110. For example, in additional embodiments, the semiconductor structure100may include greater than five (5) tiers110(e.g., greater than or equal to ten (10) tiers110, greater than or equal to twenty-five (25) tiers110, greater than or equal to fifty (50) tiers110, greater than or equal to one hundred (100) tiers110, greater than or equal to five hundred (500) tiers110, or greater than or equal to one thousand (1000) tiers110) of the conductive structures106and the insulating structures108, or may include less than five (5) tiers110(e.g., less than or equal to three (3) tiers110) of the conductive structures106and the insulating structures108.

As used herein, the term “substrate” means and includes a base material or construction upon which additional materials are formed. The substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. The materials on the semiconductor structure may include, but are not limited to, semiconductive materials, insulating materials, conductive materials, etc. One or more of the materials may be thermally sensitive. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOP”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

The conductive structures106may be formed of and include at least one conductive material, such as a metal (e.g., tungsten, titanium, molybdenum, niobium, vanadium, hafnium, tantalum, chromium, zirconium, iron, ruthenium, osmium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, aluminum), a metal alloy (e.g., a cobalt-based alloy, an iron-based alloy, a nickel-based alloy, an iron- and nickel-based alloy, a cobalt- and nickel-based alloy, an iron- and cobalt-based alloy, a cobalt- and nickel- and iron-based alloy, an aluminum-based alloy, a copper-based alloy, a magnesium-based alloy, a titanium-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium), or combinations thereof. In one embodiment, the conductive structures106are formed from polysilicon. The conductive structure106may, for example, be formed of and include a stack of at least two different conductive materials. The conductive structures106may each be substantially planar and may each independently exhibit any desired thickness. The thickness of each of the conductive structures106may range from about 1 nm to about 1000 nm, such as from about 1 nm to about 500 nm, from about 10 nm to about 500 nm, or from about 10 nm to about 250 nm. In one embodiment, the thickness of the conductive structures106ranges from about 10 nm to about 100 nm.

Each of the conductive structures106may be substantially the same (e.g., exhibit substantially the same material composition, average grain size, material distribution, size, and shape) as one another, or at least one of the conductive structures106may be different (e.g., exhibit one or more of a different material composition, a different average grain size, a different material distribution, a different size, and a different shape) than at least one other of the conductive structures106. As a non-limiting example, each of the first conductive structure106a, the second conductive structure106b, the third conductive structure106c, the fourth conductive structure106d, and the fifth conductive structure106emay exhibit substantially the same material composition, material distribution, and thickness. In some embodiments, each of the conductive structures106is substantially the same as each other of the conductive structures106.

The insulating structures108may be formed of and include at least one insulating material, such as an oxide material (e.g., silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, or a combination thereof), a nitride material (e.g., silicon nitride), an oxynitride material (e.g., silicon oxynitride), amorphous carbon, or a combination thereof. In one embodiment, the insulating structures108are formed from a silicon oxide, such as silicon dioxide. The insulating structure108may also, for example, be formed of and include a stack (e.g., laminate) of at least two different insulating materials. The insulating structures108may each be substantially planar and may each independently exhibit any desired thickness. The thickness of each of the insulating structures108may range from about 1 nm to about 1000 nm, such as from about 1 nm to about 500 nm, from about 10 nm to about 500 nm, or from about 10 nm to about 250 nm. In one embodiment, the thickness of the insulating structures108ranges from about 10 nm to about 100 nm.

Each of the insulating structures108may be substantially the same (e.g., exhibit substantially the same material composition, material distribution, size, and shape) as one another, or at least one of the insulating structures108may be different (e.g., exhibit one or more of a different material composition, a different material distribution, a different size, and a different shape) than at least one other of the insulating structures108. As a non-limiting example, each of the first insulating structure108a, the second insulating structure108b, the third insulating structure108c, the fourth insulating structure108d, and the fifth insulating structure108emay exhibit substantially the same material composition, material distribution, and thickness. In some embodiments, each of the insulating structures108is substantially the same as each other of the insulating structures108.

The materials of the conductive structures106and the insulating structures108may be selected such that the conductive structures106and the insulating structures108are selectively etchable relative to one another.

As shown inFIG.6, the conductive structures106and the insulating structures108are arranged in an alternating sequence on the substrate102beginning with one of the conductive structures106. However, the conductive structures106and the insulating structures108may be arranged in a different sequence, such as beginning with one of the insulating structures108. Accordingly, each of the tiers110may alternatively include one of the conductive structures106on or over one of the insulating structures108. A semiconductor device (e.g., a vertical memory device, such as a 3D NAND Flash memory device; a crosspoint memory device, such as a 3D crosspoint memory device) employing a semiconductor device structure having such a configuration may have little or no difference in terms of functionality or operability as compared to a semiconductor device employing the arrangement of the conductive structures106and the insulating structures108shown inFIG.6.

The substrate102, the conductive structures106, and the insulating structures108may each independently be formed using conventional processes including, but not limited to, physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), and/or spin-coating. PVD includes, but is not limited to, one or more of sputtering, evaporation, precursor spin-coating/calcination, and ionized PVD. Such processes are known in the art and, therefore, are not described in detail herein.

After forming the conductive structures106and the insulating structures108, a portion of the conductive structures106and the insulating structures108is removed to form a slot114having a width W3and a depth D3, as shown inFIG.7. The slot114may be formed in the center of the tiers110, similar to that shown inFIG.1. While not shown in the perspective ofFIG.7, the slot also has a length L3. The length L3of the slot114is less than the length L2of the conductive structures106and the insulating structures108. The length L3of the slot114may depend on a length of the staircase ultimately to be formed. The width W3of the slot114may be less than the width W2of the conductive structures106and the insulating structures108. The width W3of the slot114may depend on a width of the staircase ultimately to be formed. The depth D3of the slot114may be substantially equal to the depth D1of the conductive structures106and the insulating structures108. WhileFIG.7shows that the slot114is substantially centered across a width and length of the tiers110, the position of the slot114may be different depending on the desired position of the staircase(s) ultimately to be formed. The slot114is formed by conventional techniques, exposing sidewalls115of the conductive structures106and the insulating structures108, which are substantially vertical. A bottom surface117of the conductive structures106or of the insulating structures108is also exposed.

Portions of the conductive structures106or of the insulating structures108within the slot114may be selectively removed, forming recesses116in the conductive structures106, as shown inFIG.8A, or in the insulating structures108, as shown inFIG.8B. The portions of the conductive structures106a-106elaterally adjacent to the slot114may be removed to form the recesses116, creating a so-called “jagged” or “sawtooth” profile of the sidewalls115of the conductive structures106a-106eand the insulating structures108a-108e. The jagged profiles of the sidewalls115provide an increased surface area to the conductive structures106or to the insulating structures108in the slot114compared to the sidewalls115shown inFIG.1. WhileFIG.8Ashows the recesses116in the conductive structures106having substantially planar (e.g., substantially vertical) and smooth surfaces, the surfaces may be nonplanar (e.g., curved, jagged) and rough. By removing portions of the conductive structures106, the exposed surface area of the insulating structures108within the slot114is increased. Conversely, by removing portions of the insulating structures108laterally adjacent to the slot114and forming recesses in the insulating structures108, the exposed surface area of the conductive structures106within the slot114is increased.

Dimensions of the recesses116may be sized and configured such that a photoresist may enter the recesses116, as described in detail below. A width W4of the recesses116may be from about 1 nm to about 100 nm from the sidewalls115of the slot114. The dimensions of the recesses116may be optimized depending on the desired degree of adhesion between the photoresist and the conductive structures106and the insulating structures108. Without being bound by any theory, larger dimensions of the recesses116may enable increased adhesion of the photoresist to the conductive structures106and the insulating structures108by increasing the surface area of the conductive structures106and the insulating structures108to which the photoresist118adheres. A height of the recesses116may be determined by the thickness at which the conductive structures106or the insulating structures108are formed and a length of the recesses116may be determined by the length L3of the slot114. Since the height and length of the recesses116are set by the desired dimensions of the staircase structure, increasing the width W4of the recesses116increases the degree of photoresist adhesion.

The recesses116in the conductive structures106or in the insulating structures108are formed by selectively removing portions of the conductive structures106or of the insulating structures108by an etch process, such as a wet etch process or an isotropic, selective dry etch process. The selective wet etch process isotropically removes a portion of the conductive structures106or a portion of the insulating structures108adjacent to the slot114, without substantially removing the portion of the insulating structures108or of the conductive structures106, respectively. Since the wet etch process is isotropic, portions of the conductive structures106or the insulating structures108laterally adjacent to the slot114are selectively removed. The wet etch process may be conducted for an amount of time sufficient to form the recesses116at the desired width.

Conventional wet etch chemistries may be used to form the recesses116and may be selected depending on the materials used for the conductive structures106and the insulating structures108. In one embodiment, the conductive structures106are formed of polysilicon and the insulating structures108are formed of silicon dioxide. By way of example only, to form the recesses116in polysilicon, a conventional buffered oxide etch (BOE) solution followed by a conventional tetramethylammonium hydroxide (TMAH) solution may be used as the wet etchants. The BOE solution may include hydrogen fluoride (HF) and ammonium fluoride (NH4F) in water, as known in the art, and removes native oxide on the polysilicon surface. The TMAH solution removes the portions of the polysilicon, forming the recesses116in the polysilicon. The TMAH solution may include TMAH and water as known in the art. To form the recesses116in the silicon dioxide, a conventional BOE solution may be used as the wet etchant. However, other conventional wet etchants selective for polysilicon or silicon dioxide may be used in forming the recesses116.

After forming the recesses116, a photoresist118is formed over the tiers110, including within the slot114and the recesses116, as shown inFIG.9. The photoresist118may be formed over horizontal surfaces of the fifth (e.g., uppermost) tier110eof the conductive structures106eand the insulating structures108e, over vertical surfaces of the tiers110a-110dof the conductive structures106a-106dand the insulating structures108a-108dexposed within the slot114, and within the recesses116. A viscosity of the photoresist118may be such that the photoresist118flows over the tiers110and into the slot114and the recesses116. The photoresist118may be a conventional 193 nm resist, a conventional 248 nm resist, a conventional 365 nm resist, or a conventional deep ultraviolet (DUV) resist. The photoresist118may exhibit a positive tone or a negative tone.

The photoresist118may be formed over the tiers110at a thickness sufficient to conduct the repeated trim acts utilized during subsequent acts to form the staircase structure. The photoresist118may, for example, be spin-coated over the tiers110. While the photoresist118is shown as partially filling the slot114, the photoresist118may substantially fill the slot114. The pattern formed in the photoresist118, after exposure and development, may serve as a mask to enable selective removal of (e.g., etch) portions of the tiers110of the conductive structures106and the insulating structures108to form the staircase structure. The pattern in the photoresist118may be formed orthogonal to the length of the slot. A thickness of the photoresist118may range from about 1 μm to about 10 μm, such as from about 8 μm to about 11 μm. At a thickness within this range and the relatively large area over which the photoresist118is formed, a large volume of photoresist118is used, which includes a large volume of solvent that needs to be removed during the application of the photoresist118and during pattern formation in photoresist118using photolithography or other lithography methods. The large volume and thickness of photoresist118utilized during the formation of the staircase structures is believed to contribute to the shrinkage and stress in the photoresist118, causing delamination of the photoresist118from the sidewall115. The delamination may also be caused by poor adhesion properties of the photoresist118to the conductive structures106and insulating structures108. However, when the staircase structure is formed by a method according to the embodiments of the disclosure, the photoresist118may adhere to the conductive structures106and the insulating structures108. Without being bound by any theory, it is believed that the increased surface area of the recesses116in the conductive structures106or in the insulating structures108improves the adhesion of the photoresist118to the conductive structures106and the insulating structures108. The improved adhesion reduces or eliminates delamination of the photoresist118, which reduces or eliminates defectively formed stairs. Therefore, the staircase structure formed according to the embodiments of the disclosure may be substantially free of defects in the stairs of the staircase structure.

Additional process acts may be conducted to form a complete semiconductor device structure including the staircase structure. Additional process acts for fabricating the staircase structure and the complete semiconductor device structure may be conducted by conventional techniques, which are not described in detail herein. The repeated photoresist trim acts may be utilized to form the staircase structure. Generally, during each trim act, additional photoresist118is removed and the underlying conductive structures106and insulating structures108are etched using the remaining photoresist118as a mask. Following completion of the staircase structure, about 1 μm or less of the photoresist118may remain over the conductive structures106and insulating structures108and is subsequently removed. At least one contact structure may be formed on each of the stairs and coupled, such as electrically connected through a direct ohmic connection or through an indirect connection (e.g., via another structure electrically connected), to the conductive structures106of the tiers110. The contact structures may be formed and coupled to the conductive structures106by conventional techniques, which are not described in detail herein. The contact structures may be coupled (e.g., attached, connected) to routing structures and at least one string driver device as known in the art.

The adhesion of the photoresist118to the conductive structures106and the insulating structures108of the tiers110may be further improved by treating the surfaces of the conductive structures106or of the insulating structures108before forming the photoresist118thereover. The surface treatment may include, but is not limited to, cleaning the surfaces of the conductive structures106and/or the insulating structures108, forming inorganic spacers on the surfaces of the conductive structures106and/or the insulating structures108, chemically modifying the surfaces of the conductive structures106and/or the insulating structures108, nitridating the surfaces of the conductive structures106and/or the insulating structures108, applying adhesion promoters to the surfaces of the conductive structures106and/or the insulating structures108, or applying organic coating materials, such as bottom antireflective coating (B ARC), to the surfaces of the conductive structures106and/or the insulating structures108. However, the surface treatment alone (e.g., without also forming the recesses116) may not be sufficient to adhere the photoresist118to the conductive structures106or of the insulating structures108.

As shown inFIG.10A, which is a SEM of a semiconductor structure formed according to embodiments of the disclosure, the photoresist118is formed in the recesses116of the conductive structures106. There is good adhesion (e.g., no delamination) between the photoresist118and the conductive structures106and the insulating structures108. ComparingFIG.10AtoFIG.10B, which is an enlarged view ofFIG.10A, the recesses116formed according to embodiments of the disclosure enable improved adhesion of the photoresist118to the tiers110and, therefore, the photoresist118does not delaminate. A SEM of the staircase structure at a later stage in the fabrication process is shown inFIG.11. No defects in the stairs of the staircase structure are observed in the circled region. ComparingFIG.11toFIG.5, the staircase structure formed according to embodiments of the disclosure had no deformations in the stairs. Without being bound by any theory, it is believed that the increased surface area provided by the recesses116within the tiers110improves the adhesion of the photoresist118to the conductive structures106and the insulating structures108. The improved adhesion reduces or eliminates the deformation in the stairs of the staircase structure.

The method of improving photoresist adhesion may be used in 3D NAND structures having staircase structures, such as 3D NAND structures having dual decks of staircase structures. While embodiments of the disclosure describe improving adhesion between a large volume of photoresist118and materials of alternating conductive structures106and insulating structures108during the fabrication of the staircase structures, embodiments of the disclosure may be applicable to other situations in which a large volume of photoresist118is to be formed in a slot having relatively large dimensions. By way of example only, the position of the slot114may differ from that shown inFIG.7, depending on the desired position of the staircase(s) ultimately to be formed. As shown inFIG.12, a slot114′ may be formed in a peripheral region of the alternating conductive structures106and insulating structures108of the staircase structure ultimately to be formed, rather than in an array region as described above. As shown by dashed lines inFIG.12, recesses116may be formed in the conductive structures106before applying the photoresist118, as described above, to improve adhesion of the photoresist118to the insulating structures108. Alternatively, recesses116may be formed in the insulating structures108before applying the photoresist118, as described above, to improve adhesion of the photoresist118to the conductive structures106.

Embodiments of the disclosure may also be used when a large volume of a spin-on dielectric (SOD) material is to be formed in the slot114,114′. Recesses116may be formed in the conductive structures106or in the insulating structures108before applying the SOD material, as described above, to improve adhesion of the SOD material to the conductive structures106or the insulating structures108.

Additional process acts may be conducted to form the 3D NAND Flash memory device. For example, a channel material may be formed and extend through the alternating conductive structures106and the insulating structures108, and memory cells may be formed along the channel material. Such process acts to form the 3D NAND Flash memory device are known in the art and are not described in detail herein.

The method of improving photoresist adhesion may also be used in the formation of other 3D semiconductor devices, such as in a 3D crosspoint memory device, in which improved photoresist adhesion to conductive materials and insulating materials is desired.

Accordingly, a method of improving adhesion between a photoresist and conductive or insulating structures is disclosed. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot.

Accordingly, a method of improving adhesion between a spin-on dielectric material and conductive or insulating structures is disclosed. The method comprises forming a slot through tiers of conductive structures and insulating structures on a substrate. Recesses in the conductive structures or in the insulating structures are selectively formed. A spin-on dielectric material is formed over the tiers and within the slot.

Accordingly, a method of forming a staircase structure is disclosed. The method comprises forming a slot through tiers of conductive structures and insulating structures on a substrate. Recesses are selectively formed in the conductive structures or in the insulating structures. A photoresist is formed over the tiers and within the slot and recesses. Repeated trim acts of the photoresist are conducted to form stairs of the staircase structure.

While certain illustrative embodiments have been described in connection with the figures, those of ordinary skill in the art will recognize and appreciate that embodiments encompassed by the disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of embodiments encompassed by the disclosure, such as those hereinafter claimed, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the disclosure.