Patent ID: 12205663

Reference is made in the following detailed description to accompanying drawings, which form a part hereof, wherein like numerals may designate like parts throughout that are corresponding and/or analogous. It will be appreciated that the figures have not necessarily been drawn to scale, such as for simplicity and/or clarity of illustration. For example, dimensions of some aspects may be exaggerated relative to others. Further, it is to be understood that other embodiments may be utilized. Furthermore, structural and/or other changes may be made without departing from claimed subject matter. References throughout this specification to “claimed subject matter” refer to subject matter intended to be covered by one or more claims, or any portion thereof, and are not necessarily intended to refer to a complete claim set, to a particular combination of claim sets (e.g., method claims, apparatus claims, etc.), or to a particular claim. It should also be noted that directions and/or references, for example, such as up, down, top, bottom, and so on, may be used to facilitate discussion of drawings and are not intended to restrict application of claimed subject matter. Therefore, the following detailed description is not to be taken to limit claimed subject matter and/or equivalents.

IV. DETAILED DESCRIPTION

According to one implementation of the present disclosure, a circuit is disclosed. In a particular implementation, the circuit comprises: a first branch comprising a first transistor, where the first branch is configured to generate a first voltage; a second branch comprising a second transistor, where the second branch is configured to generate a second voltage; and a comparator configured to generate an output signal based on a comparison of the first and second voltages. Also, the output signal may be configured to regulate an output voltage of one or more negative charge pump circuits coupled to the circuit.

According to another implementation of the present disclosure, a method for converting negative voltages to positive voltages for voltage comparison and for generating a low power reference element is disclosed. For example, the method includes: 1) converting, by a voltage regulator circuit, a negative voltage output from one or more negative charge pump core circuits to a first voltage in the voltage regulator circuit; and 2) computing, by a comparator in the voltage regulator circuit, a voltage comparison of the first voltage and a second voltage. Also, the output value of the comparator may correspond to the negative voltage output of the one or more negative charge pump circuits.

According to another implementation of the present disclosure, a system is disclosed. The system includes: 1) a control block circuitry comprising a voltage regulator circuit, a reference current generation circuit, a direct current (DC) compensation circuit, and a ring oscillator circuit; and 2) a plurality of word-line driver decoding blocks comprising respective negative charge pump (NCP) circuits. Also, an output of the respective NCP circuits may be coupled to a common node.

According to another implementation of the present disclosure, a system is disclosed. The system includes: a voltage regulator circuit; one or more negative charge pump (NCP) circuits; and a direct current (DC) compensation circuit. In a certain implementation, an output voltage of the voltage regulator circuit may be coupled to one input of the DC compensation circuit. Also, an output voltage of the DC compensation circuit and an output voltage of the one or more negative charge pump (NCP) circuits may be coupled to a common voltage node. Moreover, the output voltage of the DC compensation circuit may be configured to prevent voltage drift.

Particular implementations of the present disclosure are described below with reference to the drawings. In the description, common features are designated by common reference numbers throughout the drawings.

In an example bit-cell, leakage current can be approximated by the subthreshold leakage current ISUB:

ISUB∝I0⁢e(VG-VS-VTHnkT⁢/⁢q).
In the above equation, I0represents a subthreshold saturation current; VGrepresents the word-line (WL) voltage; Vs is the source-line (SL) voltage; VTHrepresents the threshold voltage of an unselected access device (of a memory bit-cell); k represents the Boltzmann constant; T represents the temperature; q represents the charge of an electron; and n is a correlation factor (where 1<n<2). As seen, when the overdrive voltage (VGS-VTH) can be a constant, the leakage current of one cell increases with respect to temperature. Accordingly, the total leakage would increase not only with respect to temperature, but also with respect to the quantity of memory bit-cells. Hence, the greater the number of bit-cells, the greater the amount of current leakage.

For instance, at low power applications, the read-current can be very low (e.g., 1 μA-2 μA). At hot temperatures (e.g., temperatures>105° C.) and for a large number of memory bit-cells, the total current leakage may be in the order of a few μAs, and so, the current leakage (i.e., ILEAK, the sum of currents through all the unselected devices when the unselected devices have their WLs grounded) could be greater than the desired read-current (i.e., IBIT, the current through a selected device). Hence, there can be a reduction in a read margin and an increase in read failure at high sigma. To overcome this concern, the overdrive voltage (VGS-VTH) should be less than zero (e.g., the overdrive voltage<<0) in order to minimize the impact of the exponential term in the subthreshold leakage expression.

Advantageously, to allow for proper read operations, aspects of the present disclosure provide solutions to minimize and compensate for parasitic current (i.e., leakage current) in any type of memory bit-cells (e.g., an MRAM, etc.). For instance, in certain example implementations (as described herein), a negative voltage (i.e., generated negative voltage, negative output voltage) may be applied to gates of access devices in respective memory bit-cells (e.g., charge injections during WL deselection). To do so, one or more negative charge pumps (NCPs) (i.e., negative charge pump circuits as described with reference withFIGS.1and7-9) may be implemented in the memory organization circuit block arrangement (as shown inFIGS.1and2). Correspondingly, such generated negative voltage should be as stable as possible to avoid “ripples” on the unselected WLs.

As another advantage, the present disclosure provides for a distributed architecture for the one or more negative charge pumps (NCPs). A minimally-sized NCP core can be implemented inside each WL decoding block (i.e., WDX128). For instance, as shown with reference toFIGS.1and7-9, a minimally-sized NCP core can drive all of the WL drivers of each WL decoding block. Moreover, the output of all of the minimally-sized NCP cores can be connected together to a common node (e.g., having the generated negative voltage, Neg. VSSWL). As a result, the total load connected to the node (having the generated negative voltage) may allow for scalability with respect to greater quantities of connected word-lines.

In addition, the present disclosure also provides for a compensation circuit (as described with reference toFIG.10) that can be implemented to avoid the drift of negative voltage (Neg. VSSWL) to positive voltages based on WL switching activities, leakage through the WL drivers, or any noise in the overall circuit arrangement. Moreover, the present disclosure includes a compensation circuit that is based on a distributed capacitor inside each input/output (IO) block circuity. Advantageously, the value of the distributed capacitor can be the same order of magnitude as that of the total capacitor on a WL. Accordingly, the overall regulated negative charge pump system may provide the generation of a negative voltage at a required level regardless of the size of the memory.

In certain aspects, the generated negative output voltage of the circuit arrangement may depend on the output load of the circuit block arrangement100. Advantageously, a voltage regulator (e.g., voltage regulators300,400,500) can be used to ensure a stable negative output voltage. In various implementations, the voltage regulation would occur in a closed-loop system based on the sensing of the negative voltage followed by a comparison between the sensed voltage and a reference voltage. Advantageously, according to particular aspects, various implementations of the voltage regulator circuits include low power reference generation schemes as well as low power sensing methods. In various examples, such implementations allow for minimal circuit area occupation as well as greater speed in response time.

Referring toFIGS.1and2, schematic diagrams of a circuit block arrangement100(i.e., system, memory organization, an array) (e.g., an MRAM architecture, an MRAM compiler) are shown in different representations. As illustrated inFIG.1, the circuit block arrangement100may include a control block110(i.e., control block and clock generation circuitry), a plurality of word-line driver decoding blocks120, and a plurality of input/output (I/O) circuits130. In certain implementations, the control block110may include a voltage regulator circuit112(e.g., as described in greater in detail with respect toFIGS.3and4), a reference current generation circuit114(i.e., IREFgeneration circuit, Proportional-to-absolute-temperature/Complementary to absolute temperature (PTAT/CTAT) current generator circuit), a direct current (DC) compensation circuit116, and a ring oscillator circuit118(i.e., a ring oscillator circuit and phases generation circuit). Also, as shown inFIGS.1and2, the plurality of word-line driver decoding blocks120may include respective negative charge pump core circuits (i.e., negative charge pumps, NCPs)122for each respective word-line driver decoding block124. As illustrated inFIG.1, the circuit block arrangement100(and specifically the voltage regulator circuit112) can be configured to regulate a negative voltage115(i.e., negative VSSWL, generated negative voltage, charge injection during WL deselection) for transference to the plurality of word-line driver decoding blocks120. As an example, upon receiving the generated negative voltage115, each of the NCP circuits122can be configured to drive respective word-line driver blocks124(i.e., 128*WL drives). In such an example, each of pluralities of separate128word-lines are coupled to respective access devices of separate memory bit-cells located in memory banks140(e.g., memory banks 00, 01, 11, and 10) (as shown inFIG.2).

Referring toFIG.3, a schematic diagram of the voltage regulator circuit112(as described as voltage regulator circuit300) (i.e., reference voltage generator/voltage comparator circuit, a control circuit, a conversion circuit, closed-loop feedback circuit, voltage-level detection circuit) is shown. As depicted, the example circuit300includes a first circuit branch310(i.e., first branch), a second circuit branch320(i.e., second branch), and a comparator330. In certain implementations, the first and second branches310,320may be configured to generate first and second voltages (VSENSE, VREF), respectively. Also, the comparator330may be configured to generate an output signal (VCOMP) (i.e., an output value, output metric, a control bit of the NCPs) based on a comparison of the first and second voltages (VSENSE, VREF). Moreover, the output signal (VCOMP) (i.e., output value, output metric, control bit of an NCP) can be configured to regulate an output voltage of one or more negative charge pump (NCP) circuits122(as shown inFIGS.1and2) that is coupled to the voltage regulator circuit300. In operation, the voltage regulator circuit300may be configured to provide control (regulation, stability) of the output voltage of the one or more NCP circuits122such that this output voltage115can minimize and compensate for leakage current in memory bit-cells.

In some implementations, the first circuit branch310may include a first transistor (T1)312(i.e., a first p-channel metal-oxide-semiconductor field effect transistor (PMOS) device), and the second circuit branch310may include a second transistor322(T2) (i.e., a second PMOS device). Also, the comparator130can be coupled between the first and second branches310,320, where the respective first and second voltage inputs of the comparator (i.e., first and second voltages (VSENSE, VREF)) are voltages at first and second nodes314,324(i.e., voltage outputs) of the first and second branches310,320. Moreover, the output signal (VCOMP) can be coupled to the first branch310as a negative input voltage of the circuit300. Hence, the voltage regulation in the circuit300can include a closed-loop system based on a “sensing” of the negative voltage115, and further, provide a comparison between the sensed voltage (of the first branch310) and a reference voltage (of the second branch320).

In some instances, each of the first and second branches310,320include an additional transistor device (i.e., third and fourth transistor devices (316,326)) that can be configured to serve as current sources (i.e., first and second current sources). As shown inFIG.3, gate terminals of the third and fourth transistor devices316,326may be coupled to one another, while source terminals of the third and fourth transistor devices316,326may be coupled in series with respective first and second transistor devices312,322. Also, in certain cases, assuming negligible mismatch between the devices, because such devices can be configured to have substantially identical gate-to-source voltage, the devices316,326can generate substantially the same current (e.g., the respective first and second bias currents (IB1, IB2) would be substantially equal). (As shown inFIG.1, the first and second bias currents (IB1, IB2) can originate from the IREFgeneration circuit114.)

In one example operation, the third and fourth transistor devices316,326are configured to transmit respective first and second bias currents (IB1, IB2) on the respective first and second branches310,320. The first circuit branch310can be configured to generate the first voltage (VSENSE) in response to the first bias current (IB1) biasing the first transistor312, and the second circuit branch320is configured to generate the second voltage (VREF) in response to the second bias current (IB2) biasing the second transistor322. Furthermore, in such an operation, the first and second bias currents (IB1, IB2) would not go into the negative charge pumps122(i.e., the bias currents do not “load” the NCPs). Accordingly, the one or more NCPs122would not need to compensate for extra “current loading”, and thus, the circuit300(and the system100) may consume the least amount of power possible. Accordingly, and advantageously, upon completion, the circuit300(and the system100) can allow for low power charge pump operation.

In a particular implementation (where the first and second transistors312,322may be different sizes), with reference toFIG.3, in response to the biasing of the first transistor312, the first transistor312can be configured to “level shift-up” (i.e., a first voltage shift, transfer to a different voltage level) voltage on the first branch310(e.g., on a first node314on the first branch310) based on an input voltage (Vin)115(e.g., the output voltage of the one or more NCPs122, the gate voltage of the first transistor312), a first threshold voltage (VTP1), and a first overdrive voltage (Vov1, Veff1) (e.g., the effective voltage of the first transistor device312). Furthermore, in response to the biasing of the second transistor322, the second transistor322can be configured to level shift-up voltage (i.e., a second voltage shift) (by a different voltage quantity than the first voltage shift) on the second branch (e.g., on a second node324on the second branch320) based on a second threshold voltage (VTP2) and a second overdrive voltage (Vov2, Veff2) (e.g., the effective voltage of the of the second transistor device322). Moreover, in such an implementation, as the first and second transistor devices312,322are different sizes, the first and second overdrive voltages would be different values. Hence, at the voltage at the first node314, VSENSE(i.e., the first voltage), corresponds to Vin+VTP1+Vov1, while the voltage at the second node324, VREF(i.e., the second voltage), corresponds to VTP2+Vov2. Next, at the comparator330, a comparison of the first and second voltages (VSENSE, VREF) is performed.

In one case, if VSENSEis a greater than VREF(e.g., when Vin>Vov2−Vov1), the output of the comparator (VCOMP)330corresponds to a first value (e.g., either a digital “1” or “0”), and the example one or more NCP circuits122would be configured to decrease voltage (“pump down”) and the ring oscillator118(as shown inFIG.1) would be configured to be enabled. Alternatively, in another case, if VSENSEis less than VREF(e.g., when Vin<Vov2−Vov1), the output of the comparator330(VCOMP) corresponds to a second value (e.g., either a digital “0” or “1”), the one or more NCPs122can be configured to stop (i.e., output a zero voltage) and the ring oscillator118(as shown inFIG.1) would be configured to be disabled. This would be because the voltage regulator circuit300would have reached the regulated voltage level required to compensate for leakage current (i.e., at the equilibrium/target voltage level). As an example, the regulated voltage level (i.e., the output voltage) of the one or more NCPs122can be configured to be −200 mV. In such an example, this output voltage would be transmitted to each unselected word-line of a respective bit-cell to reduce current leakage. Also, in such an example, the difference between the first voltage and the second voltage (i.e., the differential voltage) would be substantially equal to the input voltage of the circuit300(VSENSE−VREF=Vin) (as there would be no differential in threshold voltage (i.e., VTP1-VTP2=0 and the bias currents (IB1, IB2) would not flow towards Vin). Moreover, in the implementation, the difference between the first and second overdrive voltages (Vov2−Vov1) would correspond to a voltage regulation range of the plurality of negative charge pump (NCP) circuits122. Correspondingly, at the target voltage level, the input voltage (Vin) would be substantially equal to the difference between the first and second overdrive voltages (Vov2−Vov1).

Referring toFIG.4, a schematic diagram of the voltage regulator circuit112(as described as voltage regulator circuit400) (i.e., reference voltage generator/voltage comparator circuit, a control circuit, a conversion circuit, closed-loop feedback circuit, voltage-level detection circuit) is shown. As depicted, the example circuit400may be substantially identical to the circuit300, with the exception that the first branch410may also include a voltage offset element418(i.e., voltage drop element) (e.g., resistor, transistor, etc.). In certain implementations, the voltage offset element418may be configured to generate an offset voltage to “shift down” the first voltage (VSENSE) to provide control of the output voltage (i.e., Neg. VSSWL) of the one or more NCP circuits112. In operation, the voltage regulator circuit400may be configured to provide control (regulation, stability) of the output voltage of the one or more NCP circuits122such that this output voltage115can minimize and compensate for leakage current in memory bit-cells. Moreover, as another advantage, the circuit400may be process, voltage, and temperature (PVT) independent.

In an example operation, the first and second transistor devices412,422are configured to transmit respective first and second bias currents (IB1, IB2) on the respective first and second branches410,420. The first circuit branch410can be configured to generate the first voltage (VSENSE) in response to the first bias current (IB1) biasing the first transistor412, and the second circuit branch420is configured to generate the second voltage (VREF) in response to the second bias current (IB2) biasing the second transistor422. Furthermore, in such an operation, the first and second bias currents (IB1, IB2) would not go into the negative charge pumps122(i.e., the bias currents do not “load” the NCPs). Accordingly, the one or more NCPs122would not need to compensate for extra “current loading”, and thus, the circuit400(and the system100) may consume the least amount of power possible. Accordingly, and advantageously, upon completion, the circuit400(and the system100) can allow for low power charge pump operation.

In a particular implementation (where the first and second transistors412,422may be substantially identical sizes), with reference toFIG.4, in response to the biasing of the first transistor412, the first transistor412can be configured to “level shift-up” (i.e., a first voltage shift) voltage on the first branch410based on an input voltage (Vin)115(e.g., the output voltage of the one or more NCPs122, the gate voltage of the first transistor412), a first threshold voltage (VTP1), and a first overdrive voltage (Veff1) (e.g., the effective voltage of the of the first transistor device412). Accordingly, an intermediate voltage corresponding to Vin+VTP1+Veff1can be generated. Next, as the first and second transistors412,422are the substantially the same size in the particular implementation, both the first and second threshold voltages (VTP1, VTP2) and the first and second effective voltages (Veff1, Veff2) (i.e., first and second overdrive voltages) would be substantially identical (VTF1=VTP2) (Veff1=Veff2). Accordingly, the voltage-level shifters on both the first and the second branches410,420would cancel out. Consequently, the voltage-drop across a voltage offset device418(Rx) on the first branch410(coupled between to the first transistor412and the first node414) would generate an offset voltage (i.e., voltage drop, floating voltage). Accordingly, the first voltage (VSENSE) of the circuit400may be generated based on a combination of the intermediate voltage and the generated offset voltage (e.g., 200 mV). In such an implementation, the voltage offset device (Rx)418may be configured to shift down the first voltage (VSENSE). Moreover, the second voltage (VREF) can be generated based on the first voltage shift (i.e., the level shift-up of the first transistor). Furthermore, in response to the biasing of the second transistor422, the second transistor422can be configured to level shift-up voltage (i.e., the first voltage shift) on the second branch420(e.g., on a second node424on the second branch420) based on a second threshold voltage (VTP2) and a second overdrive voltage (Veff2) (e.g., the effective voltage of the of the second transistor device422. However, because the sizes of the first and second transistor412,422are substantially identical, both the first and second threshold voltages (VTP1, VTP2) and the first and second effective voltages (Veff1, Veff2) would be substantially identical (VTP1=VTP2) (Veff1=Veff2). Accordingly, the second voltage (i.e., the reference voltage, VREF) would correspond to VTP2+Veff2+0 (i.e., the gate voltage of the second transistor422), which would also equal VTP1+Veff1. Next, at the comparator430, a comparison of the first and second voltages (VSENSE, VREF) is performed.

As an example, for the comparison of the first and second voltages (VSENSE, VREF), a “trip point” is the point where the output value of the comparator430would start to “flip” (switch) from “1 to a “0” or vice versa. In this instance, the trip point would be controlled by the second voltage, VREF. Also, to reach the trip point, the first voltage has to be substantially equal the second voltage (VSENSE=VREF) (i.e., VSENSE−VREF=0). Also, the circuit400would have to verify whether the difference between VSENSEand VREFis substantially equal to the combination of Vin and the voltage drop across the voltage offset device (Rx)418(e.g., VSENSE−VREF=Vin+0.2V). Hence, for example, at the comparator430trip point, Vin=−0.2V. Thus, in this manner, a reference voltage may be constructed.

Accordingly, in one case, if VSENSEis a greater than VREF(e.g., when Vin>−0.2V), the output of the comparator (VCOMP)430corresponds to a first value (e.g., either a digital “1” or “0”), and the example one or more NCP circuits122would be configured to decrease voltage (“pump down”) and the ring oscillator118(as shown inFIG.1) would be configured to be enabled. Alternatively, in another case, if VSENSEis less than VREF(e.g., when Vin<−0.2V), the output of the comparator430(VCOMP) corresponds to a second value (e.g., either a digital “0” or “1”), the example one or more NCPs122can be configured to stop (i.e., output a zero voltage) and the ring oscillator118(as shown inFIG.1) would be configured to be disabled. This would be because the voltage regulator circuit400would have reached the regulated voltage level required to compensate for leakage current (i.e., at the equilibrium voltage level). As discussed, the regulated voltage level (i.e., the output voltage) of the one or more NCPs122can be configured to be −200 mV. In such an example, this output voltage (i.e., Neg. VSSWL) would be transmitted to each unselected word-line of a respective bit-cell to reduce current leakage.

In certain implementations, to ensure the correct value of VSENSE, the voltage offset device418(Rx) should be trimmable. For example, the voltage offset device418can include three bits of for trimming. In one example, to target the negative output voltage115for −200 mV for a bias current (IB)=1 μA, the negative charge pump (NCP) TRIM is 100, the voltage offset device418is 200 kOhms, and the change in voltage (ΔV, change in voltage over the voltage drop element) (mV) is 200.

Referring toFIG.5, a schematic diagram of the voltage regulator circuit112(as described as voltage regulator circuit500) (i.e., reference voltage generator/voltage comparator circuit, a control circuit, a conversion circuit, closed-loop feedback circuit, voltage-level detection circuit) is shown. As depicted, the example circuit500may be substantially identical to the circuits300or400, with the exception that the first and second branches510,520may also include respective voltage offset elements518,528(i.e., voltage drop element) (e.g., resistor, transistor, etc.). In certain implementations, the voltage offset elements518,528may be configured to generate first and second offset voltages to “shift down” both the respective first and second voltages (VSENSEand VREF). In doing so, the voltage regulator circuit can provide control of the output voltage (i.e., Neg. VSSWL) of the one or more NCP circuits112. In operation, the voltage regulator circuit500may be configured to provide control (regulation, stability) of the output voltage of the one or more NCP circuits122such that this output voltage115can minimize and compensate for leakage current in memory bit-cells. Moreover, as another advantage, the circuit500may be process, voltage, and temperature (PVT) independent.

Similar to as described with reference toFIG.4, in an example operation, the first and second transistor devices512,522are configured to transmit respective first and second bias currents (IB1, IB2) on the respective first and second branches510,520. The first circuit branch510can be configured to generate the first voltage (VSENSE) in response to the first bias current (IB1) biasing the first transistor512, and the second circuit branch520is configured to generate the second voltage (VREF) in response to the second bias current (IB2) biasing the second transistor522. Furthermore, in such an operation, the first and second bias currents (IB1, IB2) would not go into the one into the negative charge pumps122(i.e., the bias currents do not “load” the NCPs). Accordingly, the one or more NCPs122would not need to compensate for extra “current loading”, and thus, the circuit500(and the system100) may consume the least amount of power possible. Accordingly, and advantageously, upon completion, the circuit500(and the system100) can allow for low power charge pump operation.

In a particular implementation (where the first and second transistors512,522may be substantially identical sizes), with reference toFIG.5, in response to the biasing of the first transistor512, the first transistor512can be configured to “level shift-up” (i.e., a first voltage shift) voltage on the first branch510based on an input voltage (Vin)115(e.g., the output voltage of the one or more NCPs122, the gate voltage of the first transistor512), a first threshold voltage (VTP1), and a first overdrive voltage (Veff1) (e.g., the effective voltage of the of the first transistor device512). Accordingly, on the first circuit branch510, a first intermediate voltage corresponding to Vin+VTP1+Veff1can be generated. Next, as the first and second transistors512,522are the substantially the same size in this particular implementation, both the first and second threshold voltages (VTP1, VTP2) and the first and second effective voltages (Veff1, Veff2) (i.e., first and second overdrive voltages) would be substantially identical (VTP1=VTP2) (Veff1=Veff2). Accordingly, the voltage-level shifters on both the first and the second branches510,520would cancel out. Consequently, the voltage-drop across a voltage offset device518(Rx) on the first branch510(coupled between to the first transistor512and the first node514) would generate an offset voltage (i.e., voltage drop, floating voltage). Accordingly, the first voltage (VSENSE) of the circuit500may be generated based on a combination of the first intermediate voltage and the generated first offset voltage.

Furthermore, in response to the biasing of the second transistor522, the second transistor522can be configured to “level shift-up” (i.e., a second voltage shift) voltage on the second branch522based on a second threshold voltage (VTP2) and a second overdrive voltage (Veff2) (e.g., the effective voltage of the of the second transistor device522). Accordingly, on the second circuit branch520, a second intermediate voltage corresponding to 0+VTP2+Veff2can be generated. Next, as the first and second transistors512,522are the substantially the same size in the particular implementation, both the first and second threshold voltages (VTP1, VTP2) and the first and second effective voltages (Veff1, Veff2) (i.e., first and second overdrive voltages) would be substantially identical (VTP1=VTP2) (Veff1=Veff2). Accordingly, the voltage-level shifters on both the first and the second branches510,520would cancel out. Consequently, the voltage-drop across a voltage offset device528(Ry) on the second branch510(coupled between to the second transistor522and the second node524) would generate a second offset voltage (i.e., voltage drop, floating voltage). Accordingly, the second voltage (VREF) of the circuit500may be generated based on a combination of the second intermediate voltage and the generated second offset voltage. In such an implementation, the difference between the output voltages of the first and second voltage offset device (Ry)528may be configured to shift down the first voltage (VSENSE). Next, at the comparator530, a comparison of the first and second voltages (VSENSE, VREF) is performed.

As an example, for the comparison of the first and second voltages (VSENSE, VREF), similar toFIG.4, inFIG.5, the trip point the comparator530would occur when VSENSE−VREF=0. Also, the circuit500would have to verify whether the difference between VSENSEand VREFis substantially equal to the combination of Vin and the difference of the voltage drop across the first voltage offset device (Rx)518and the voltage drop across the second voltage offset device (Ry)528multiplied by the bias current (IB) (e.g., VSENSE−VREF=(Rx−Ry)*IB). Hence at the comparator530trip point, Vin=−(Rx−Ry)*IB. For example, if IB=1 μA and Vin=−0.2V, then Rx−Ry=200 KΩ. Accordingly, based on the difference of the output voltages of the respective voltage offset devices518,528(Rx, Ry) of each circuit branch510,520, a reference voltage may be constructed.

Accordingly, in one case, if VSENSEis a greater than VREF(e.g., when Vin>−0.2V), the output of the comparator (VCOMP)530corresponds to a first value (e.g., either a digital “1” or “0”), and the example one or more NCP circuits122would be configured to decrease voltage (“pump down”) and the ring oscillator118(as shown inFIG.1) would be configured to be enabled. Alternatively, in another case, if VSENSEis less than VREF(e.g., when Vin<−0.2V), the output of the comparator530(VCOMP) corresponds to a second value (e.g., either a digital “0” or “1”), the example one or more NCPs122can be configured to stop (i.e., output a zero voltage) and the ring oscillator118(as shown inFIG.1) would be configured to be disabled. This would occur as result of the voltage regulator circuit500would having reached the regulated voltage level required to compensate for leakage current (i.e., at the equilibrium voltage level). As discussed, the regulated voltage level (i.e., the output voltage) of the one or more NCPs122can be configured to be 200 mV. In such an example, this output voltage (i.e., Neg. VSSWL) would be transmitted to each unselected word-line of a respective bit-cell to reduce current leakage.

Referring toFIG.6, a method flow chart600applicable for the above-mentioned voltage regulators circuits112,300,400, and500with reference toFIGS.1-5is shown. In certain examples, the method flow chart600is applicable for negative voltage to positive voltage conversion for voltage comparison as well as generating a low power reference element (i.e., VREF).

At block610, a negative output voltage from one or more negative charge pump core (NCP) circuits are converted by a voltage regulator circuit to a positive voltage component of a first voltage in the voltage regulator circuit. For example, as shown inFIGS.1-5, negative output voltage (i.e., Neg. VSSWL) from one or more negative charge pump core (NCP) circuits122are converted by a voltage regulator circuit (112,300,400,500) to a positive voltage component of a first voltage (VSENSE) in the voltage regulator circuit (112,300,400,500).

At block620, a voltage comparison of the first voltage and a second voltage is performed by a comparator in the voltage regulator circuit. Also, the output value corresponds to the negative voltage output of the negative charge pump circuit. For example, as shown inFIGS.1-5, a voltage comparison of the first voltage (VSENSE) and a second voltage (VREF) is performed by a comparator (300,400,500) in the voltage regulator circuit (112,300,400,500).

In one implementation of block610, with reference toFIG.3, converting the negative voltage comprises: 1) generating the first voltage by a first voltage shift on a first transistor of a first circuit branch of the voltage regulator circuit based on the input voltage, a first threshold voltage, and a first overdrive voltage, and 2) generating the second voltage by a second voltage shift on a second transistor of a second circuit branch based on a second threshold voltage and a second overdrive voltage.

In a second implementation of block610, with reference toFIG.4, converting the negative voltage comprises: 1) generating an intermediate voltage based on a first voltage shift on a first transistor of a first circuit branch of the voltage regulator circuit based on the input voltage, a first threshold voltage, and a first overdrive voltage; 2) generating an offset voltage of a voltage offset device coupled to the first transistor; 3) generating the first voltage based on a combination of the intermediate voltage and the offset voltage of the voltage offset device, wherein the voltage offset device is configured to shift down the first voltage; and 4) generating the second voltage based on the first voltage shift.

In a third implementation of block610, with reference toFIG.5, converting the negative voltage comprises: 1) generating a first intermediate voltage based on a first voltage shift on a first transistor of a first circuit branch of the voltage regulator circuit based on the input voltage, a first threshold voltage, and a first overdrive voltage; 2) generating a first offset voltage of a first voltage offset device coupled to the first transistor; 3) generating the first voltage based on a combination of the intermediate voltage and the offset voltage of the voltage offset device; 4) generating a second intermediate voltage based on the first voltage shift; 5) generating a second offset voltage of a second voltage offset device coupled to the second transistor; and 6) generating the second voltage based on a combination of the second intermediate voltage and the second offset voltage of the voltage offset device.

Referring toFIG.7-9, schematic diagrams of the one or more negative charge pump core circuits122(i.e., negative charge pumps, NCPs) (is described as NCP(s)700) are shown.FIG.7illustrates an expanded view of an example NCP122. As shown, the example NCP122may be implemented inside each WL decoding block124(e.g., WDX128). In certain implementations, the negative output voltage (Neg. VSSWL) can be connected to all individual WL drivers712(on both the top and bottom). As depicted, the example NCP700is integrated within each word-line (WL) decoding block124of a plurality of WL decoding blocks124in the circuit arrangement200. As shown inFIGS.7-9, each of the WL decoding blocks124(e.g., WDX128) may include 128 separate WL drivers712for a top side710and a bottom side720.FIG.8illustrates the circuit architecture of the example NCP122. As shown, the example NCP122may include capacitors and a switch network triggered by clocks (e.g., clk1, clk2 (i.e., two non-overlapping clocks) to generate a negative voltage from lower voltage (e.g., power supply) by charging and discharging the capacitors. As depicted, for greater efficiency, the example NCP122architecture may include a cross-coupled topology.FIG.9illustrates that at the input of each WL decoding block, the clock phases clk1 and clk2 can be buffered, and that the output voltage (e.g., Neg. VSSWL) of each decoding block can be coupled together.

As shown inFIGS.7-9, a distributed architecture for the one or more negative charge pumps (NCPs) is shown. Advantageously, a minimally-sized NCP core122can be implemented inside each WL decoding block124(i.e., WDX128). For instance, a minimally-sized NCP core122can drive all of the WL drivers of each WL decoding block. Moreover, the output of all of the minimally-sized NCP cores122can be connected together to a common node (e.g., having the generated negative voltage, Neg. VSSWL). As a result, the total load connected to the node (having the generated negative voltage) may allow for scalability with respect to greater quantities of connected word-lines.

Referring toFIG.10, a schematic diagram of the DC drift compensation block116(i.e., DC drift compensation circuit) (as referenced inFIG.1) is shown. In an example implementation, the DC drift compensation circuit116may be utilized to prevent drift of the voltage output of the one or more NCPs122. As the one or more NCPs122may be sized for a fixed (i.e., given) number of bit-lines (BL) and source-lines (SL), it is likely that the one or more NCPs122may not operate as desired. Moreover, during a word-line (WL) deselection, a previously selected WL (at a “high” level, for example, at the power supply) may be discharged to a lower voltage. Hence, positive charges that are stored on such a WL may be injected into the “negative rail” (of the negative voltage output of the one or more NCPs). As a result, the negative voltage (Neg. VSSWL) can drift from negative to positive values. Accordingly, to avoid such a drift of the negative voltage, the DC drift compensation circuit116can be implemented. As depicted,FIG.10illustrates one circuit implementation of the DC compensation block116.

With reference toFIG.10, to avoid negative rail DC drift over a certain time duration, the following example operation is presented. At an initial stage of the operation, as VSENSE>VREF, the output voltage of the comparator (VCOMP)=High. Hence, (as discussed in above paragraphs with reference to the voltage regulator circuit), the one or more NCPs122may be enabled and the output voltage115(i.e., Neg. VSSWL) goes to a negative voltage. Concurrently, the signal ngtp=High. Accordingly, the signal gtp_comp=Low, and the resultant voltages, S2_gtp=Low and S1_ngtp=High. Moreover, the switch SW2 is “off” while the switch SW1 is “on”. Thus, capacitor CBST would be coupled to the negative voltage output115. Next, when the negative voltage output115(i.e., Neg. VSSWL) may reach the targeted value, VSENSE<VREF, thus, making VCOMP=“Low”. As a result, the signal gtp_comp=“High”, the signal S1_ngtp=“Low”, and the signal S2_gtp=“High”. Moreover, the switch SW1 would turn “off”, while the switch SW2 would turn “on”. Hence, the voltage at node VCBST may discharge to ground.

During a WL deselection, the signal ngtp=“High”. Correspondingly, there would be “charge sharing” between selected (sel) and unselected (unsel) WLs. As a result, the voltage output115(Neg. VSSWL) increases. Next, as soon as the voltage output115crosses the targeted value, VSENSE>VREFand VCOMP=“High”. Hence, the signal gtp_comp=“Low”, and further, the signal S2_gtp=“Low” and the signal S1_ngtp=“High”. Moreover, the switch SW2 would turn “off”. while the switch SW1 would turn “on”. Thus, the capacitor CB ST would be coupled to the negative voltage output115. Consequently, the negative voltage output115would be “pulled down” again by the capacitor CBST. Furthermore, during a WL selection, the signal ngtp=“Low”, the signal gtp_comp=“High”, and further, the signal S1_ngtp=“Low” and the signal S2_gtp=“High”. Moreover, the switch SW1 would turn “off”, while the switch SW2 would turn “on”. Hence, the voltage at node VCBST may discharge to ground. Accordingly, when the negative voltage output115reaches the targeted value, the signal VCOMP=“Low”. Over a particular time-interval to prevent a negative rail DC drift, this procedure may be repeated.

Advantageously, while the disclosure has been described in the context of MRAM bit-cells, such implementations, methods, and techniques as described herein may be performed in any other type of memory cells where leakage current prevents accurate memory read operations.

In example implementations, certain circuit elements have been provided inFIGS.1-10, whose redundant description has not been duplicated in the related description of analogous circuit elements herein. It is expressly incorporated that the same circuit elements with identical symbols and/or reference numerals are included in each of embodiments based on its corresponding figure(s).

Although one or more ofFIGS.1-10may illustrate systems, apparatuses, or methods according to the teachings of the disclosure, the disclosure is not limited to these illustrated systems, apparatuses, or methods. One or more functions or components of any ofFIGS.1-10as illustrated or described herein may be combined with one or more other portions of another ofFIGS.1-10. Accordingly, no single implementation described herein should be construed as limiting and implementations of the disclosure may be suitably combined without departing form the teachings of the disclosure.

Those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or processor executable instructions depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The steps of a method or algorithm described in connection with the disclosure herein may be implemented directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transient storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.

The previous description is provided to enable a person skilled in the art to make or use the disclosed implementations. Various modifications to these implementations will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other implementations without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the implementations shown herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.