Patent ID: 12199183

DETAILED DESCRIPTION

Methods of forming a semiconductor device are described, as are related semiconductor devices, memory devices, and electronic systems. In some embodiments, a method of forming a semiconductor device comprises forming dielectric support structures over dielectric line structures overlying conductive line contact structures (e.g., source contact structures). The dielectric support structures laterally extend in a direction orthogonal to another direction in which the conductive line contact structures extend, and are separated from one another by trenches. Conductive gate structures (e.g., gate electrodes) are formed on exposed side surfaces of the dielectric support structures within the trenches. Dielectric oxide structures (e.g., gate oxide structures) are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed (e.g., uncovered) portions of the dielectric line structures are removed to form isolation structures. Semiconductive pillars (e.g., channel pillars) are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. Additional conductive contact structures (e.g., drain contact structures) are formed on upper surfaces of the semiconductive pillars. Optionally, additional dielectric oxide structures (e.g., additional gate oxide structures) and additional conductive gate structures (e.g., additional gate electrodes) may be formed over side surfaces of the semiconductive pillars prior to forming the additional conductive contact structures. In addition, air gaps may, optionally, be formed between at least some laterally neighboring conductive gate structures and/or between at least some laterally neighboring additional conductive gate structures (if any). The methods and structures of the disclosure may facilitate the formation of devices (e.g., access devices, semiconductor devices, memory devices) and systems (e.g., electronic systems) having one or more of increased performance, reduced off-state current, increased efficiency, increased reliability, and increased durability as compared to conventional devices (e.g., conventional access devices, conventional semiconductor devices, conventional memory devices) and conventional systems (e.g., conventional electronic systems).

The following description provides specific details, such as material species, material thicknesses, and processing conditions in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art will understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a semiconductor device (e.g., a memory device). The semiconductor device structures described below do not form a complete semiconductor device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form the complete semiconductor device from the semiconductor device structures may be performed by conventional fabrication techniques. Also note, any drawings accompanying the application are for illustrative purposes only, and are thus not drawn to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, the term “substrate” means and includes a base material or construction upon which additional materials are formed. The substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire (SOS) substrates and silicon-on-glass (SOG) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped. By way of non-limiting example, a substrate may comprise at least one of silicon, silicon dioxide, silicon with native oxide, silicon nitride, a carbon-containing silicon nitride, glass, semiconductor, metal oxide, metal, titanium nitride, carbon-containing titanium nitride, tantalum, tantalum nitride, carbon-containing tantalum nitride, niobium, niobium nitride, carbon-containing niobium nitride, molybdenum, molybdenum nitride, carbon-containing molybdenum nitride, tungsten, tungsten nitride, carbon-containing tungsten nitride, copper, cobalt, nickel, iron, aluminum, and a noble metal.

As used herein, the term “configured” refers to a size, shape, material composition, material distribution, orientation, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a predetermined way.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are in reference to a major plane of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by earth's gravitational field. A “lateral” or “horizontal” direction is a direction that is substantially parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction that is substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

As used herein, “vertically neighboring” or “longitudinally neighboring” features (e.g., structures, devices) means and includes features located most, vertically proximate (e.g., vertically closest) one another. In addition, as used herein, “horizontally neighboring” or “laterally neighboring” features (e.g., structures, devices) means and includes features located most horizontally proximate (e.g., horizontally closest) one another.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

FIGS.1A through14Bare simplified partial cross-sectional (FIGS.1A,2A,3A,4A,5A,6A,7A,8A,9A,10A,11A,12A,13A, and14A) and simplified partial plan (i.e.,FIGS.1B,2B,3B,4B,5B,6B,7B,8B,9B,10B,11B,12B,13B, and14B) views illustrating embodiments of a method of forming a semiconductor device structure (e.g., a memory structure) for a semiconductor device (e.g., a memory device, such as a DRAM device, an FeRAM device, an RRAM device, a conductive bridge RAM device, an MRAM device, a PCM device, a PCRAM device, a STTRAM device, an oxygen vacancy-based memory device, a programmable conductor memory device). With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein may be used in various devices. In other words, the methods of the disclosure may be used whenever it is desired to form a semiconductor device.

Referring to collectively toFIGS.1A and1B, a semiconductor device structure100may include source lines102, source line contacts104on or over the source lines102, isolation lines106on or over the source line contacts104, and linear dielectric structures108on or over the isolation lines106. The source lines102may comprise at least one electrically conductive material, such as one or more of a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively doped semiconductor material. By way of non-limiting example, the source lines102may be formed of and include one or more of tungsten (W), tungsten nitride (WN), nickel (Ni), tantalum (Ta), tantalum nitride (TaN), tantalum silicide (TaSi), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), molybdenum nitride (MoN), iridium (Jr), iridium oxide (IrOx), ruthenium (Ru), ruthenium oxide (RUOx), and conductively doped silicon. In some embodiments, the source lines102are formed of and include W. The source lines102may be positioned in, on, or over a substrate.

The source line contacts104may also comprise at least one electrically conductive material (e.g., one or more of a metal, an alloy, carbon, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively doped semiconductor material). By way of non-limiting example, the source line contacts104may comprise one or more of W, WN, Ni, Ta, TaN, TaSi, Pt, Cu, Ag, Au, Al, Mo, Ti, TiN, TiSi, TiSiN, TiAlN, MoN, Jr, IrOx, Ru, RuOx, carbon (C), indium oxide (InOx), molybdenum oxide (MoOx), and conductively doped silicon. In some embodiments, the source line contacts104are formed of and include Ru. The source line contacts104may be formed on or over the source lines102to any desired thickness, and may substantially cover upper surfaces of the source lines102.

The isolation lines106may be formed of and include at least one dielectric material, such as one or more of a dielectric oxide material (e.g., silicon dioxide; phosphosilicate glass; borosilicate glass; borophosphosilicate glass; fluorosilicate glass; aluminum oxide; high-k oxides, such as hafnium oxide (HfOx); a combination thereof), a dielectric nitride material (e.g., silicon nitride (SiN)), a dielectric oxynitride material (e.g., silicon oxynitride (SiON)), a dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), and a dielectric carboxynitride material (e.g., silicon carboxynitride (SiOCN)), and amorphous carbon. In some embodiments, the isolation lines106comprise SiN. The isolation lines106may be formed on or over the source line contacts104to any desired thickness, and may substantially cover upper surfaces of the source line contacts104.

The linear dielectric structures108may serve as support structures for additional components (e.g., additional structures, additional materials) of the semiconductor device structure100to be subsequently formed, as described in further detail below. The linear dielectric structures108may be formed of and include at least one dielectric material, such as one or more of a dielectric oxide material (e.g., silicon dioxide; phosphosilicate glass; borosilicate glass; borophosphosilicate glass; fluoro silicate glass; aluminum oxide; high-k oxides, such as hafnium oxide (HfOx); a combination thereof), a dielectric nitride material (e.g., SiN), a dielectric oxynitride material (e.g., SiON), a dielectric carbonitride material (e.g., SiCN), and a dielectric carboxynitride material (e.g., SiOCN), and amorphous carbon. A material composition of the linear dielectric structures108may be substantially the same as or may be different than that of the isolation lines106. In some embodiments, the linear dielectric structures108comprise SiN.

The linear dielectric structures108may be laterally oriented perpendicular (e.g., orthogonal) to the source lines102, the source line contacts104, and the isolation lines106. For example, as shown inFIG.1A, the source lines102, the source line contacts104, and the isolation lines106may extend in a first lateral direction (e.g., the X-direction), and the linear dielectric structures108extend in a second lateral direction (e.g., the Y-direction) perpendicular to the first lateral direction as well as in a vertical direction (e.g., the Z-direction) perpendicular to both the first and second lateral directions. The linear dielectric structures108may be laterally separated (e.g., in the X-direction) from one another by trenches110(e.g., openings). The trenches110may vertically extend (e.g., in the Z-direction) from upper surfaces of the linear dielectric structures108to upper surfaces of the isolation lines106. The semiconductor device structure100may include any desired quantities (e.g., amounts, numbers) of the linear dielectric structures108and the trenches110.

The linear dielectric structures108and the trenches110may each individually be formed to exhibit any desired dimensions and spacing. The dimensions and spacing of the linear dielectric structures108and the trenches110may be selected at least partially based on desired dimensions and desired spacing of additional components (e.g., additional structures, additional materials) of the semiconductor device structure100to be formed using the linear dielectric structures108, as described in further detail below.

The source lines102, the source line contacts104, the isolation lines106, and the linear dielectric structures108may be formed using conventional processes (e.g., conventional deposition processes, such as one or more of in situ growth, spin-on coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD); conventional material removal processes, such as conventional photolithography processes and conventional etching processes), which are not described in detail herein.

Referring to next toFIG.2A, linear gate structures112(e.g., gate electrodes) may be formed on or over opposing sidewalls of each of the linear dielectric structures108. The linear gate structures112may partially fill the trenches110, such that linear gate structures112on laterally neighboring linear dielectric structures108are separated from one another by remainders of the trenches110.FIG.2Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.2A.

The linear gate structures112may be formed of and include at least one electrically conductive material, such as one or more of a metal, a metal alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively doped semiconductor material. The linear gate structures112may, for example, be formed of and include one or more of W, WN, Ni, Ta, TaN, TaSi, Pt, Cu, Ag, Au, Al, Mo, Ti, TiN, TiSi, TiSiN, TiAlN, MoN, Jr, IrOx, Ru, RuOx, and conductively doped silicon. The material composition of the linear gate structures112may be the same as or may be different than the material composition of one or more of the source lines102and the source line contacts104. In at least some embodiments, the linear gate structures112are formed of and include TiN. In addition, the linear gate structures112may each be formed at any suitable width (e.g., lateral dimension in the X-direction). By way of non-limiting example, each of the linear gate structures112may be formed to have a width within a range of from about 5 nm to about 15 nm, such as from about 5 nm to about 10 nm, or from about 10 nm to about 15 nm. In some embodiments, each of the linear gate structures112is formed to have a width within a range of from about 5 nm to about 10 nm.

The linear gate structures112may be formed using conventional processes and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, a gate material may be conformally formed (e.g., deposited through one or more of a PVD process, a CVD process, an ALD process, and a spin-coating process) over exposed surfaces of the linear dielectric structures108and the isolation lines106, and then an anisotropic etching process may be performed to remove the gate material from upper surfaces of the linear dielectric structures108and from portions of the upper surfaces of the isolation lines106underlying central portions of the trenches110, while maintaining the gate material on the opposing sidewalls of the linear dielectric structures108to form the linear gate structures112.

Referring to next toFIG.3A, linear oxide structures114(e.g., gate oxide structures) may be formed on or over exposed (e.g., uncovered, bare) sidewalls of each of the linear gate structures112. The linear oxide structures114may further partially fill the trenches110, such that linear oxide structures114laterally adjacent laterally neighboring linear dielectric structures108are separated from one another by remainders of the trenches110. The linear oxide structures114may be formed of and include at least one dielectric oxide material, such as one or more of silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide, and a high-k oxide (e.g., hafnium oxide (HfOx), niobium oxide (NbOx), titanium oxide (TiOx)). In some embodiments, the linear oxide structures114are formed of silicon dioxide.FIG.3Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.3A.

The dimensions and spacing of the linear oxide structures114(and, hence, the dimensions and spacing of remaining portions of the trenches110) may be selected to provide desired dimensions and spacing to additional structures to be formed in the remaining portions of the trenches110. The linear oxide structures114may, for example, be laterally sized (e.g., in the X-direction) and laterally spaced (e.g., in the X-direction) to facilitate the formation of linear channel material structures exhibiting desired lateral dimensions and desired lateral spacing, as described in further detail below. By way of non-limiting example, each of the linear oxide structures114may be formed to have a width (e.g., in the X-direction) less than or equal to about 20 nm, such as less than or equal to about 10 nm, or less than or equal to about 5 nm. In some embodiments, each of the linear oxide structures114is formed to have a width within a range of from about 5 nm to about 10 nm.

The linear oxide structures114may be formed using conventional processes and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, a dielectric oxide material may be conformally formed (e.g., deposited through one or more of a PVD process, a CVD process, an ALD process, and a spin-coating process) over exposed surfaces of the linear gate structures112, the linear dielectric structures108, and the isolation lines106, and then an anisotropic etching process may be performed to remove the gate material from upper surfaces of the linear gate structures112and the linear dielectric structures108, and from portions of the upper surfaces of the isolation lines106underlying central portions of the trenches110, while maintaining the dielectric oxide material on sidewalls of the linear gate structures112to form the linear oxide structures114.

Referring next toFIG.4A, portions of the isolation lines106(FIGS.3A and3B) may be removed to form isolation structures116therefrom. As shown inFIG.4A, sidewalls of the isolation structures116may be substantially coplanar with sidewalls (e.g., laterally outermost sidewalls in the X-direction) of the linear oxide structures114thereover.FIG.4Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.4A.

At least one selective material removal process may be used to form the isolation structures116. The selective material removal process may remove exposed portions of the isolation lines106(FIGS.3A and3B) without substantially removing portions of the source lines102, the source line contacts104, the linear dielectric structures108, the linear gate structures112, and the linear oxide structures114. Suitable selective material removal processes (e.g., masking and etching processes) are known in the art, and are not described in detail herein.

Referring to next toFIG.5A, linear channel material structures118may be formed on or over exposed (e.g., uncovered, bare) sidewalls of the linear oxide structures114and the isolation structures116. As shown inFIG.5A, the linear channel material structures118may vertically extend (e.g., in the Z-direction) from upper surfaces of the source line contacts104to upper surfaces of the linear oxide structures114. The linear channel material structures118may further partially fill the trenches110, such that linear channel material structures118between laterally neighboring linear dielectric structures108are separated from one another by remainders of the trenches110.FIG.5Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.5A.

The linear channel material structures118may be formed of and include a semiconductive material including at least one region having a band gap larger than that of polycrystalline silicon, such as a band gap larger than 1.65 electronvolts (eV). For example, the linear channel material structures118may comprise an oxide semiconductor material including one or more (e.g., one, two or more, three or more) of zinc tin oxide (ZnxSnyO, commonly referred to as “ZTO”), indium zinc oxide (InxZnyO, commonly referred to as “IZO”), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly referred to as “IGZO”), indium gallium silicon oxide (InxGaySizO, commonly referred to as “IGSO”), indium tungsten oxide (InxWyO, commonly referred to as “IWO”), indium oxide (InxO), tin oxide (SnxO), titanium oxide (TixO), zinc oxide nitride (ZnxONz), magnesium zinc oxide (MgxZnyO), zirconium indium zinc oxide (ZrxInyZnzO), hafnium indium zinc oxide (HfxInyZnzO), tin indium zinc oxide (SnxInyZnzO), aluminum tin indium zinc oxide (AlxSnyInzZnaO), silicon indium zinc oxide (SixInyZnzO), aluminum zinc tin oxide (AlxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), zirconium zinc tin oxide (ZrxZnySnzO), and other similar materials. Formulae including at least one of “x,” “y,” “z,” and “a” above (e.g., ZnxSnyO, InxZnyO, InxGayZnzO, InxWyO, InxGaySizO, AlxSnyInzZnaO) represent a composite material that contains, throughout one or more regions thereof, an average ratio of “x” atoms of one element, “y” atoms of another element (if any), “z” atoms of an additional element (if any), and “d” atoms of a further element (if any) for every one atom of oxygen (O). As the formulae are representative of relative atomic ratios and not strict chemical structure, the linear channel material structures118may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds throughout the different regions thereof, and values of “x,” “y,” “z,” and “a” may be integers or may be non-integers throughout the different regions thereof. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions.

Each of the linear channel material structures118may be substantially homogeneous or may be heterogeneous. In some embodiments, the linear channel material structures118are each substantially homogeneous, such that each linear channel material structure118exhibits a substantially uniform (e.g., even, non-variable) distribution of the elements thereof. For example, amounts (e.g., atomic concentrations) of each element (e.g., one or more metals, one or more metalloids, oxygen) included in the linear channel material structure118may not vary throughout the dimensions (e.g., lateral dimensions, vertical dimensions) of the linear channel material structure118. In additional embodiments, the linear channel material structures118are each substantially heterogeneous, such that each linear channel material structure118exhibits a substantially non-uniform (e.g., non-even, variable) distribution of one or more of the elements thereof. For example, amounts (e.g., atomic concentrations) of one or more elements (e.g., one or more metals, one or more metalloids, oxygen) included in the linear channel material structure118may vary throughout at least a width (e.g., lateral dimension in the X-direction) of the linear channel material structure118.

If the linear channel material structures118are laterally heterogeneous (e.g., exhibit a substantially non-uniform distribution of one or more elements in the X-direction), each linear channel material structure118may include substantially the same elements in different lateral regions thereof, or may include different elements in at least one lateral region thereof than in at least one other lateral region thereof. In some embodiments, each linear channel material structure118individually includes substantially the same elements in each of the different lateral regions thereof, but at least one of the different lateral regions includes a different atomic concentration of one or more of the elements than at least one other of the different lateral regions. For example, each linear channel material structure118may individually comprise a laterally heterogeneous form of a single (e.g., only one) oxide semiconductor material (e.g., only one of ZnxSnyO, InxZnyO, ZnxO, InxGayZnzO, InxGaySizOa, InxWyO, InxO, SnxO, TixO, ZnxONz, MgxZnyO, InxZnyO, InxGayZnzO, ZrxInyZnzO, HfxInyZnzO, SnxInyZnzO, AlxSnyInzZnaO, SixInyZnzO, ZnxSnyO, AlxZnySnzO, GaxZnySnzO, ZrxZnySnzO, and InxGaySizO), but atomic concentrations of one or more elements of the single oxide semiconductor material (and, hence, the relative atomic ratios of the formula thereof) may be different in at least two (2) different lateral regions thereof. In additional embodiments, each linear channel material structure118individually includes one or more different elements in at least one of the different lateral regions thereof than in at least one other of the different lateral regions thereof. For example, each linear channel material structure118may comprise a lateral stack of two or more (e.g., two, three, more than three) different oxide semiconductor materials (e.g., two or more of ZnxSnyO, InxZnyO, ZnxO, InxGayZnzO, InxGaySizOa, InxO, SnxO, InxWyO, TixO, ZnxONz, MgxZnyO, InxZnyO, InxGayZnzO, ZrxInyZnzO, HfxInyZnzO, SnxInyZnzO, AlxSnyInzZnaO, SixInyZnzO, ZnxSnyO, AlxZnySnzO, GaxZnySnzO, ZrxZnySnzO, and InxGaySizO).

The linear channel material structures118may be formed using conventional processes (e.g., conventional deposition processes, conventional material removal processes), which are not described in detail herein. By way of non-limiting example, a channel material (e.g., oxide semiconductor material) may be conformally formed (e.g., conformally deposited through one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin-coating process) over exposed surfaces of the linear oxide structures114, the linear gate structures112, the linear dielectric structures108, the isolation structures116, and the source line contacts104. Thereafter, an anisotropic etching process may be performed to remove the channel material from upper surfaces of at least the linear gate structures112and the linear dielectric structures108, and from portions of the upper surfaces of the source line contacts104underlying central portions of the trenches110, while maintaining the channel material at least on sidewalls of the linear oxide structures114to form the linear channel material structures118.

Next, referring collectively toFIGS.6A and6B, a mask structure119(FIG.6B) may be provided over the semiconductor device structure100. The mask structure119may be formed of and include at least one material suitable for use as an etch mask structure to pattern portions of the linear channel material structures118, as described in further detail below. By way of non-limiting example, the mask structure119may be formed of and include at least one of amorphous carbon, silicon, a silicon oxide, a silicon nitride, a silicon oxycarbide, aluminum oxide, and a silicon oxynitride. The mask structure119may be homogeneous (e.g., may comprise a single material layer), or may be heterogeneous (e.g., may comprise a stack exhibiting at least two different material layers).

As shown inFIG.6B, the mask structure119exhibits a desired pattern to be transferred to the linear channel material structures118. For example, mask structure119may include linear mask structures120, and linear apertures121(e.g., openings) laterally intervening (e.g., in the Y-direction) between the linear mask structures120. The linear mask structures120and the linear apertures121may individually exhibit lateral dimensions, shapes, positions, and orientations facilitating desired lateral dimensions, shapes, positions, and orientations of features (e.g., pillar structures) and openings to be subsequently formed from and in the linear channel material structures118. As shown inFIG.6B, in some embodiments, each of the linear mask structures120exhibits substantially the same lateral dimensions (e.g., width, length), shape, spacing, and orientation as each other of the linear mask structures120. Referring collectively toFIGS.6A and6B, each of the linear mask structures120(FIG.6B) of the mask structure119(FIG.6B) may individually be substantially aligned with and exhibit substantially the same lateral dimensions as one of the source lines102(FIG.6A) (and, hence, one of the source line contacts104(FIG.6A)) of the semiconductor device structure100.

The mask structure119, including the linear mask structures120and the linear apertures121thereof, may be formed and positioned using conventional processes (e.g., conventional deposition processes, such as at least one of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD; conventional photolithography processes; conventional material removal processes; conventional alignment processes) and conventional processing equipment, which are not described in detail herein.

Referring next toFIG.7A, portions of the linear channel material structures118(FIGS.6A and6B) remaining uncovered by the linear mask structures120(FIG.6B) of the mask structure119(FIG.6B) may be subjected to at least one material removal process to form channel pillars122. The material removal process may transfer or extend a pattern defined by the linear apertures121(FIG.6B) in the mask structure119(FIG.6B) into the linear channel material structures118(FIGS.6A and6B). The material removal process may selectively remove the portions of the linear channel material structures118(FIGS.6A and6B) remaining uncovered by the linear mask structures120(FIG.6B) of the mask structure119(FIG.6B) relative to the linear oxide structures114, the linear gate structures112, the linear dielectric structures108, and the source line contacts104. In addition, as shown inFIG.7A, following the formation of the channel pillars122, the mask structure119(FIG.6B) may be removed to expose surfaces of the channel pillars122, the linear oxide structures114, the linear gate structures112, the linear dielectric structures108, and the source line contacts104previously covered by the linear mask structures120(FIG.6B) of mask structure119(FIG.6B).FIG.7Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.7A.

As shown inFIG.7B, the material removal process forms openings laterally intervening between (e.g., in the Y-direction) and separating laterally neighboring channel pillars122formed from the same linear channel material structures118(FIGS.6A and6B). The openings may exhibit substantially the same lateral dimensions (e.g., in the Y-direction), shapes, spacing, and orientations as the linear apertures121(FIG.6B) of the mask structure119(FIG.6B).

The material removal process employed to form the channel pillars122may comprise a conventional anisotropic etching process, which is not described in detail herein. For example, the material removal process may comprise exposing portions of the linear channel material structures118(FIGS.6A and6B) to one or more of anisotropic dry etching (e.g., reactive ion etching (RIE), deep RIE, plasma etching, reactive ion beam etching, chemically assisted ion beam etching) and anisotropic wet etching (e.g., hydrofluoric acid (HF) etching, a buffered HF etching, buffered oxide etching). In addition, remaining portions of the mask structure119(FIG.6B) (if any) may be selectively removed following the formation of the channel pillars122using one or more other conventional material removal processes (e.g., a conventional wet etching process, a conventional dry etching process), which are not described in detail herein.

Next, referring toFIG.8A, a gate oxide material124may be formed (e.g., conformally formed) on or over exposed surfaces of the channel pillars122, the linear oxide structures114, the linear gate structures112, the linear dielectric structures108, and the source line contacts104. The gate oxide material124may further partially fill the trenches110, and may also substantially fill the openings laterally intervening between (e.g., in the Y-direction) and separating laterally neighboring channel pillars122. The gate oxide material124may be formed of and include at least one dielectric oxide material, such as one or more of silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide, and a high-k oxide (e.g., HfOx, NbOx, TiOx). A material composition of the gate oxide material124may be substantially same as or may be different than a material composition of the linear oxide structures114. In some embodiments, the gate oxide material124comprises silicon dioxide.FIG.8Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.8A, wherein the gate oxide material124is depicted as transparent to show the other components of the semiconductor device structure100provided thereunder.

The gate oxide material124may be formed at any suitable thickness. The thickness of the gate oxide material124may be selected (e.g., tailored) to provide desired lateral offset in the X-direction between the channel pillars122and additional linear gate structures to be formed laterally adjacent thereto, as well as to provide desired vertical offset in the Z-direction between the additional gate structures and the source line contacts104, as described in further detail below. By way of non-limiting example, each of the gate oxide material124may be formed such that portions thereof laterally adjacent sidewalls of the channel pillars122have a width in the X-direction less than or equal to about 20 nm, such as less than or equal to about 10 nm, or less than or equal to about 5 nm. The width in the X-direction of portions of the gate oxide material124laterally adjacent sidewalls of the channel pillars122may be substantially the same as or may be different than the width in the X-direction of each of the linear oxide structures114.

Referring toFIG.8B, the gate oxide material124may intervene between laterally neighboring channel pillars122in the Y-direction. In some embodiments, the gate oxide material124substantially fills in spaces between the laterally neighboring channel pillars122, such that central regions123(shown inFIG.8Bwith dashed line) between the laterally neighboring channel pillars122are substantially occupied (e.g., filled) by the gate oxide material124. Accordingly, portions of the gate oxide material124intervening between laterally neighboring channel pillars122in the Y-direction may have greater lateral dimensions than portions of the gate oxide material124intervening between the channel pillars122and remainders of the trenches110in the X-direction. For example, lateral dimensions of portions of the gate oxide material124intervening between and separating laterally neighboring channel pillars122in the Y-direction may be about two (2) times (2X) greater than lateral dimensions of additional portions of the gate oxide material124intervening between and separating the channel pillars122and remainders of the trenches110in the X-direction. In additional embodiments, the gate oxide material124does not substantially fill in the spaces between the laterally neighboring channel pillars122, such that central regions123between the laterally neighboring channel pillars122remain at least partially unoccupied (e.g., unfilled) by the gate oxide material124. Such a configuration of the gate oxide material124may, for example, permit additional gate structures to be subsequently formed to laterally extend over multiple sides (e.g., multiple sidewalls) of each of the channel pillars122to facilitate a so-called “gate-all-around” configuration, as described in further detail below. For example, portions of the additional gate structures may be formed to laterally extend in the X-direction through the central regions123remaining at least partially unoccupied with the gate oxide material124, while additional portions of the additional gate structures are formed to laterally extend in the Y-direction (e.g., parallel to the linear gate structures112).

The gate oxide material124may be formed on or over exposed surfaces of the channel pillars122, linear oxide structures114, the linear gate structures112, the linear dielectric structures108, and the source line contacts104using conventional processes (e.g., one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD) and conventional processing equipment, which are not described in detail herein.

Referring to next toFIG.9A, additional gate structures126(e.g., additional gate electrodes) may be formed on or over portions of the gate oxide material124. The additional gate structures126may further partially fill the trenches110, such that laterally neighboring (e.g., in the X-direction) additional gate structures126are separated from one another by remainders of the trenches110.FIG.9Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.9A.

The additional gate structures126may be formed of and include at least one electrically conductive material, such as one or more of a metal, a metal alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively doped semiconductor material. The additional gate structures126may, for example, be formed of and include one or more of W, WN, Ni, Ta, TaN, TaSi, Pt, Cu, Ag, Au, Al, Mo, Ti, TiN, TiSi, TiSiN, TiAlN, MoN, Ir, IrOx, Ru, RuOx, and conductively doped silicon. The material composition of the linear gate structures112may be the same as or may be different than the material composition of one or more of the source lines102, the source line contacts104, and the linear gate structures112. In at least some embodiments, the additional gate structures126are formed of and include TiN.

At least some portions of the additional gate structures126may be laterally oriented parallel to the linear gate structures112(and, hence, the linear dielectric structures108). As shown inFIG.9B, in some embodiments, such as embodiments wherein the central regions123in the Y-direction between laterally neighboring channel pillars122are substantially filled with the gate oxide material124, the additional gate structures126and the linear gate structures112each substantially laterally extend in the Y-direction. In additional embodiments, such as embodiments wherein the central regions123are at least partially unfilled with the gate oxide material124, portions of the additional gate structures126laterally extend in the Y-direction (e.g., in parallel to the linear gate structures112), and additional portions of the additional gate structures126laterally extend in the X-direction e.g., perpendicular to the linear gate structures112).

The additional gate structures126may each be formed at any suitable lateral dimensions (e.g., lateral dimensions in the X-direction and the Y-direction). The width in the X-direction of each of the additional gate structures126may be substantially the same as or may be different than the width of each of the linear gate structures112. By way of non-limiting example, each of the additional gate structures126may be formed to have a width within a range of from about 5 nm to about 15 nm, such as from about 5 nm to about 10 nm, or from about 10 nm to about 15 nm. In some embodiments, each of the additional gate structures126is formed to have a width within a range of from about 5 nm to about 10 nm.

The additional gate structures126may be formed using conventional processes and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, a gate material may be conformally formed (e.g., deposited through one or more of a PVD process, a CVD process, an ALD process, and a spin-coating process) over exposed surfaces of the gate oxide material124, and then an anisotropic etching process may be performed to remove the gate material from surfaces of the gate oxide material124outside of the trenches110and from portions of laterally-central portions of upper surfaces of the gate oxide material124within trenches110, while maintaining the gate material on the side surface of the gate oxide material124within the trenches110to form the additional gate structures126.

Next, referring toFIG.10A, a sacrificial material127may be formed (e.g., non-conformally formed) on or over exposed surfaces of the additional gate structures126and the gate oxide material124. The sacrificial material127may substantially fill remaining portions of the trenches110(FIG.9A). For example, the sacrificial material127may substantially fill remaining portions of the trenches110(FIG.9A) intervening between (e.g., in the X-direction) laterally neighboring additional gate structures126.FIG.10Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.10A, wherein the sacrificial material127is depicted as transparent to show the other components of the semiconductor device structure100provided thereunder.

As a non-limiting example, the sacrificial material127may be formed of and include one or more of carbon and a conventional resist material, such as a conventional photoresist material (e.g., a conventional positive tone photoresist, a conventional negative tone photoresist) or a conventional thermoresist material. If the sacrificial material127comprises a photoresist material, exposing (e.g., if the photoresist material comprises a positive tone photoresist) or not exposing (e.g., if the photoresist material comprises a negative tone photoresist) the sacrificial material127to at least a minimum threshold dosage of electromagnetic radiation may cause the sacrificial material127to become at least partially soluble in a developer. If the sacrificial material127comprises a thermoresist material, exposing or not exposing the sacrificial material127to at least a minimum threshold temperature may cause the sacrificial material127to become at least partially soluble in a developer. As shown inFIG.10A, the sacrificial material127may exhibit a substantially planar upper surface. In additional embodiments, the sacrificial material127exhibits a non-planar upper surface defined by elevated regions and recessed regions.

The sacrificial material127may be formed using conventional processes (e.g., conventional deposition processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, the sacrificial material127may be formed on or over exposed surfaces of the additional gate structures126and the gate oxide material124through one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD.

Referring next toFIG.11A, upper portions of the sacrificial material127(FIG.10A), the additional gate structures126, the gate oxide material124(FIG.10A), the channel pillars122, the linear oxide structures114, the linear gate structures112, and the linear dielectric structures108may be removed through at least one planarization process, such as a conventional chemical-mechanical planarization (CMP) process. As shown inFIG.11A, the planarization process may form linear resist structures128and additional oxide structures125from the sacrificial material127(FIG.10A) and the gate oxide material124(FIG.10A), respectively. In addition, the planarization process may form uppermost surfaces (e.g., in the Z-direction) of the linear resist structures128, the additional gate structures126, the additional oxide structures125, the channel pillars122, the linear oxide structures114, the linear gate structures112, and the linear dielectric structures108to be substantially coplanar with one another about a plane130(shown inFIG.11Ausing dashed lines).FIG.11Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.11A.

Referring next toFIG.12A, upper portions of the linear gate structures112and the additional gate structures126may be selectively removed to recess upper surfaces of the linear gate structures112and the additional gate structures126relative to upper surfaces of the linear dielectric structures108, the linear oxide structures114, the channel pillars122, the additional oxide structures125, and the linear resist structures128. As shown inFIG.12A, the vertical positions (e.g., in the Z-direction) of the upper surfaces of the linear gate structures112and the additional gate structures126may be modified to be vertically below the plane130that remains shared by the upper surfaces of the linear dielectric structures108, the linear oxide structures114, the channel pillars122, the additional oxide structures125, and the linear resist structures128.FIG.12Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.12A.

The upper portions of the linear gate structures112and the additional gate structures126may be selectively removed using one or more conventional material removal processes (e.g., a conventional wet etching process, a conventional dry etching process), which are not described in detail herein.

Referring next toFIG.13A, the linear resist structures128(FIGS.12A and12B) may be selectively removed (e.g., developed), and a dielectric material132may be formed on or over exposed surfaces of the linear gate structures112and the additional gate structures126. As shown inFIG.13A, the dielectric material132may substantially fill openings resulting from the removal of the linear resist structures128(FIGS.12A and12B), and may also substantially fill open volumes (e.g., void spaces) overlying the linear gate structures112and the additional gate structures126as a result of the formation of the recessed upper surfaces thereof.FIG.13Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.13A.

The dielectric material132may comprise one or more of a dielectric oxide material (e.g., silicon dioxide; phosphosilicate glass; borosilicate glass; borophosphosilicate glass; fluorosilicate glass; aluminum oxide; high-k oxides, such as HfOx; a combination thereof), a dielectric nitride material (e.g., SiN), a dielectric oxynitride material (e.g., SiON), a dielectric carbonitride material (e.g., SiCN), and a dielectric carboxynitride material (e.g., SiOCN), and amorphous carbon. A material composition of the dielectric material132may be substantially the same as or may be different than that of one or more of the linear dielectric structures108and the isolation structures116. In some embodiments, the dielectric material132comprises SiN.

As shown inFIG.13A, in some embodiments, such as in embodiments wherein drain contact structures to be subsequently formed over the channel pillars122are to be formed using a subtractive process (e.g., as opposed to a damascene process), upper surfaces of the dielectric material132are formed to be substantially coplanar with upper surfaces of the linear dielectric structures108, the linear oxide structures114, the channel pillars122, and the additional oxide structures125. For example, the upper surfaces of the dielectric material132may be formed to be substantially coplanar with the upper surfaces of the linear dielectric structures108, the linear oxide structures114, the channel pillars122, and the additional oxide structures125about the plane130or about a different plane (e.g., another plane vertically below the plane130). In additional embodiments, such as in embodiments wherein drain contact structures to be subsequently formed are to be formed using a damascene process (e.g., as opposed to a subtractive process), the upper surfaces of the dielectric material132are formed to be substantially non-coplanar with upper surfaces of the linear dielectric structures108, the linear oxide structures114, the channel pillars122, and the additional oxide structures125. For example, in such embodiments, one or more upper surfaces of the dielectric material132may vertically overlie the upper surfaces of the linear dielectric structures108, the linear oxide structures114, the channel pillars122, and the additional oxide structures125.

The linear resist structures128may be removed and the dielectric material132may be formed using conventional processes (e.g., conventional development processes, conventional deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein. For example, the linear resist structures128may be selectively removed by developing the linear resist structures128with a developer (e.g., a positive tone developer, a negative tone developer) suitable for the material composition and exposure (e.g., photoexposure, thermoexposure) of the linear resist structures128. In addition, the dielectric material132may be formed on or over exposed surfaces of the linear gate structures112and the additional gate structures126using one or more conventional deposition processes (e.g., one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin-coating process). If desired (e.g., if drain contact structures to be subsequently formed over the channel pillars122are to be formed using a subtractive process), upper portions of the dielectric material132may then be removed using one or more conventional material removal processes, such as one or more conventional CMP processes.

Referring next toFIG.14A, drain contacts134may be formed on or over upper surfaces of the channel pillars122. In addition, the drain contacts134may be laterally separated from one another by an isolation material136.FIG.14Bis a simplified partial plan view of the semiconductor device structure100at the process stage depicted inFIG.14A.

The drain contacts134may be formed of and include at least one electrically conductive material, such as one or more of W, WN, Ni, Ta, TaN, TaSi, Pt, Cu, Ag, Au, Al, Mo, Ti, TiN, TiSi, TiSiN, TiAlN, MoN, Ir, IrOx, Ru, RUOx, and conductively doped silicon. The material composition of the drain contacts134may be the same as or may be different than the material composition of the source line contacts104. In at least some embodiments, the drain contacts134are formed of and include Ti. In addition, the drain contacts134may be formed on or over the channel pillars122to any desired thickness (e.g., to the same thickness as the source line contacts104, or to a different thickness than the source line contacts104), and may substantially cover the upper surfaces of the channel pillars122. As shown inFIG.14A, in some embodiments, portions of the drain contacts134extend beyond lateral boundaries of the channel pillars122. For example, portions of the drain contacts134may cover portions of upper surfaces of the linear oxide structures114and the additional oxide structures125laterally neighboring the channel pillars122. In additional embodiments, the drain contacts134may be substantially confined within the lateral boundaries of the channel pillars122.

The isolation material136may comprise at least one dielectric material, such as one or more of a dielectric oxide material (e.g., silicon dioxide; phosphosilicate glass; borosilicate glass; borophosphosilicate glass; fluoro silicate glass; aluminum oxide; high-k oxides, such as HfOx; a combination thereof), a dielectric nitride material (e.g., SiN), a dielectric oxynitride material (e.g., SiON), a dielectric carbonitride material (e.g., SiCN), and a dielectric carboxynitride material (e.g., SiOCN), and amorphous carbon. A material composition of the isolation material136may be substantially the same as or may be different than that of one or more of the dielectric material132, the linear dielectric structures108, and the isolation structures116. In some embodiments, such as embodiments wherein the drain contacts134are formed through a subtractive process (described in further detail below), the isolation material136is formed after the formation of the dielectric material132, and may have a material composition substantially the same as or different than that of the dielectric material132. In additional embodiments, such as embodiments wherein the drain contacts134are formed through a damascene process (also described in further detail below), the isolation material136comprises an upper region of the dielectric material132(and, hence, may be formed as part of and have substantial the same material composition as the dielectric material132).

In some embodiments, the drain contacts134are formed on or over the channel pillars122through a subtractive process. An electrically conductive material may be formed (e.g., through one or more conventional deposition processes, such as one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin-coating process) on or over upper surfaces of the channel pillars122, the linear oxide structures114, the additional oxide structures125, the linear gate structures112, the additional gate structures126, and the linear dielectric structures108. Portions of the electrically conductive material not overlying the channel pillars122may then be selectively removed (e.g., through conventional photolithographic patterning and etching processes) to form the drain contacts134. Thereafter, the isolation material136may be formed (e.g., through one or more conventional deposition processes, such as one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin-coating process) between the drain contacts134. If desired, at least the isolation material136may be then subjected to at least one planarization process (e.g., at least one CMP process) to remove portions of the isolation material136positioned vertically above upper surfaces of the drain contacts134.

In additional embodiments, the drain contacts134are formed on or over the channel pillars122through a damascene process. For example, portions of a dielectric material (e.g., portions of the dielectric material132if the dielectric material132vertically extends beyond upper surfaces of the channel pillars122; portions of another dielectric material formed on or over upper surfaces of the dielectric material132and the channel pillars122) overlying the channel pillars122may then be selectively removed to form the isolation material136. The isolation material136exhibits trenches (e.g., openings, apertures, vias) extending therethrough, the trenches each individually at least partially (e.g., substantially) laterally aligned (e.g., in the X-direction and in the Y-direction) with one of the channel pillars122. Thereafter, the trenches may be filled (e.g., through one or more conventional deposition processes, such as one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin-coating process) with an electrically conductive material, and at least one planarization process (e.g., at least one CMP process) may be used to remove portions of the electrically conductive material positioned vertically above upper surfaces of the isolation material136and form the drain contacts134.

The semiconductor device structure100at the processing stage depicted inFIG.14A(e.g., following the formation of the drain contacts134) includes multiple vertical access devices135(e.g., vertical transistors, vertical thin film transistors (TFTs)). Each vertical access device135individually includes one of the channel pillars122, one of the drain contacts134vertically above the channel pillar122, one of the source line contacts104(which is shared between at least some of the vertical access devices135) vertically below the channel pillar122, one of the linear oxide structures114laterally neighboring a side of the channel pillar122, one of the linear gate structures112laterally neighboring the linear oxide structure114, a portion of one of the additional oxide structure125laterally neighboring another side of the channel pillar122, and one of the additional gate structures126laterally neighboring the portion of the additional oxide structure125. Each vertical access device135may be considered to be “double-gated” since one of the linear gate structures112and one of the additional gate structures126laterally neighbor opposing sides of the channel pillar122of the vertical access device135.

One of ordinary skill in the art will appreciate that, in accordance with additional embodiments of the disclosure, the features and feature configurations described above in relation toFIGS.1A through14Bmay be readily adapted to the design needs of different semiconductor devices (e.g., different memory devices). As a non-limiting example, the vertical access devices135may be formed to exhibit a “single-gate” configuration wherein each vertical access device135individually includes one of the linear gate structures112laterally neighboring a side of the channel pillar122, but does not include one of the additional gate structures126laterally neighboring an opposing side of the channel pillar122. An isolation structure comprising an electrically insulating material may laterally-neighbor the opposing side of the channel pillar122instead of the additional linear gate structure126. Referring toFIG.7A, such a “single-gate” configuration of the vertical access devices135(FIG.14A) may, for example, be facilitated by forming isolation structures in remainders of the trenches110following the process stage depicted inFIG.14A; planarizing (e.g., using at least one CMP process) upper surfaces of the isolation structures, the channel pillars122, the linear oxide structures114, the linear gate structures112, and the linear dielectric structures108; and then forming the drain contacts134over the channel pillars122through a process substantially similar to that previously described with reference toFIGS.14A and14B.

Thus, in accordance with embodiments of the disclosure, a method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars.

Furthermore, a device according to embodiments of the disclosure comprises oxide semiconductor pillars on conductive contact structures overlying conductive line structures; nitride dielectric structures on the conductive contact structures and contacting lower portions of sidewalls of the oxide semiconductor pillars; oxide dielectric structures on the nitride dielectric structures and contacting upper portions of the sidewalls of the oxide semiconductor pillars; additional oxide dielectric structures on the conductive contact structures and contacting additional sidewalls of the oxide semiconductor pillars opposite the sidewalls; conductive gate structures on the nitride dielectric structures and contacting sidewalls of the oxide dielectric structures, the conductive gate structures laterally extending perpendicular to the conductive line structures; and additional conductive contact structures on upper surfaces of the oxide semiconductor pillars.

With returned reference toFIG.14A, in additional embodiments the semiconductor device structure100may be formed to include air gaps (e.g., void spaces, open volumes) between the linear gate structures112of laterally neighboring vertical access devices135and/or between the additional gate structures126of laterally neighboring vertical access devices135. The air gaps may serve as insulators having a dielectric constant (c) of about 1. The air gaps may limit capacitance and increase shorts margin between the linear gate structures112and/or the additional gate structures126of laterally neighboring vertical access devices135, and may reduce cross-talk between laterally neighboring vertical access devices135.

By way of non-limiting example,FIGS.15A through17Bare simplified partial cross-sectional (FIGS.15A,16A, and17A) and simplified partial plan (i.e.,FIGS.15B,16B, and17B) views illustrating embodiments of a method of forming a semiconductor device structure100′ including air gaps. The semiconductor device structure100′ may be formed in substantially the same manner as and may exhibit substantially the same features (e.g., structures, materials) as the semiconductor device structure100up through the processing stage previously described herein with reference toFIGS.12A and12B. Accordingly, the method of forming the semiconductor device structure100′ described hereinbelow with respect toFIGS.15A through17Bincorporates the processing stages and features previously described in relation to the formation of the semiconductor device structure100up through the processing stage previously described with reference toFIGS.12A and12B. However, the dimensions and/or spacing of one or more features of the semiconductor device structure100may be modified in relation to those previously described with references toFIGS.1A through12Bto accommodate desired feature sizes and/or spacing in the semiconductor device structure100′. For example, the linear dielectric structures108(FIGS.12A and12B) of the semiconductor device structure100′ may be formed (e.g., at the processing stage previously described with reference toFIGS.1A and1B) to exhibit reduced widths (e.g., in the X-direction) and spacing relative to the linear dielectric structures108(FIGS.12A and12B) of the semiconductor device structure100, which may effectuate changes (e.g., reductions) to at least the spacing of other features of the semiconductor device structure100′ relative to the those of the semiconductor device structure100. In some embodiments, the linear dielectric structures108(FIGS.12A and12B) of the semiconductor device structure100′ are about half as wide as the linear dielectric structures108(FIGS.12A and12B) of the semiconductor device structure100. The reductions to the widths of the linear dielectric structures108(FIGS.12A and12B) of the semiconductor device structure100′ may, for example, facilitate the formation of air gaps from the linear dielectric structures108(FIGS.12A and12B) having substantially the same lateral dimensions (e.g., widths in the X-direction) as other air gaps formed from the linear resist structures128(FIGS.12A and12B), as described in further detail below.

Referring toFIG.15A, after recessing the upper surfaces of the linear gate structures112and the additional gate structures126through the processing acts previously described with reference toFIGS.12A and12B, the linear dielectric structures108(FIGS.12A and12B) may be selectively removed to form openings137, and the linear resist structures128(FIGS.12A and12B) may be selectively removed to form additional openings139. The openings137may laterally extend between and separate the laterally neighboring linear gate structures112, and the additional openings139may laterally extend between and separate the laterally neighboring additional gate structures126. As shown inFIG.15A, if the linear dielectric structures108(FIGS.12A and12B) and the linear resist structures128(FIGS.12A and12B) are formed to exhibit substantially the same widths (e.g., in the X-directions), the openings137and the additional openings139may also exhibit substantially the same widths as one another. In additional embodiments, the openings137are formed to exhibit different widths than the additional openings139.FIG.15Bis a simplified partial plan view of the semiconductor device structure100′ at the process stage depicted inFIG.15A.

The openings137and the additional openings139may be formed using conventional material removal processes and conventional processing equipment, which are not described in detail herein. For example, the linear dielectric structures108(FIGS.12A and12B) may be selectively removed using at least one material removal process (e.g., at least one etching process, such as at least one anisotropic etching process) to form the openings137, and the linear resist structures128(FIGS.12A and12B) may be selectively removed using at least one other material removal process (e.g., at least one development process, such as the development process previously described herein with reference toFIGS.13A and13B) to form the additional openings139. The linear dielectric structures108(FIGS.12A and12B) may be selectively removed before the selective removal of the linear resist structures128(FIGS.12A and12B), or the linear dielectric structures108(FIGS.12A and12B) may be selectively removed after the selective removal of the linear resist structures128(FIGS.12A and12B).

Referring next toFIG.16A, a dielectric material142may be formed on or over portions of exposed surfaces of the linear gate structures112and the additional gate structures126. As shown inFIG.16A, the dielectric material142may partially (e.g., less than completely) fill the openings137(FIGS.15A and15B) and the additional openings139(FIGS.15A and15B) to form air gaps140and additional air gaps141, respectively. The air gaps140may each individually be formed to have a height (e.g., in the Z-direction) greater than or equal to about one-half (e.g., greater than or equal to two-thirds, greater than or equal to three-fourths) the height of the linear gate structures112laterally adjacent thereto. In addition, the additional air gaps141may each individually be formed to have a height (e.g., in the Z-direction) greater than or equal to about one-half (e.g., greater than or equal to two-thirds, greater than or equal to three-fourths) the height of the additional gate structures126laterally adjacent thereto. The dielectric material142may also substantially fill open volumes overlying the linear gate structures112and the additional gate structures126.FIG.16Bis a simplified partial plan view of the semiconductor device structure100′ at the process stage depicted inFIG.16A.

The dielectric material142comprise one or more of a dielectric oxide material (e.g., silicon dioxide; phosphosilicate glass; borosilicate glass; borophosphosilicate glass; fluorosilicate glass; aluminum oxide; high-k oxides, such as HfOx; a combination thereof), a dielectric nitride material (e.g., SiN), a dielectric oxynitride material (e.g., SiON), a dielectric carbonitride material (e.g., SiCN), and a dielectric carboxynitride material (e.g., SiOCN), and amorphous carbon. A material composition of the dielectric material142may be substantially the same as or may be different than that of one or more of the linear dielectric structures108and the isolation structures116. In some embodiments, the dielectric material142comprises SiN.

As shown inFIG.16A, in some embodiments, such as in embodiments wherein drain contact structures to be subsequently formed over the channel pillars122are to be formed using a subtractive process, upper surfaces of the dielectric material142are formed to be substantially coplanar with upper surfaces of the linear oxide structures114, the channel pillars122, and the additional oxide structures125. For example, the upper surfaces of the dielectric material142may be formed to be substantially coplanar with the upper surfaces of the linear oxide structures114, the channel pillars122, and the additional oxide structures125about the plane130or about a different plane (e.g., another plane vertically below the plane130). In additional embodiments, such as in embodiments wherein drain contact structures to be subsequently formed are to be formed using a damascene process, the upper surfaces of the dielectric material142are formed to be substantially non-coplanar with upper surfaces of the linear oxide structures114, the channel pillars122, and the additional oxide structures125. For example, in such embodiments, one or more upper surfaces of the dielectric material142may vertically overlie the upper surfaces of the linear oxide structures114, the channel pillars122, and the additional oxide structures125.

The dielectric material142may be formed using conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein. For example, the dielectric material142may be formed on or over portions of the exposed surfaces of the linear gate structures112and the additional gate structures126using one or more conventional non-conformal deposition processes (e.g., a non-conformal PVD process). If desired (e.g., if drain contact structures to be subsequently formed over the channel pillars122are to be formed using a subtractive process), upper portions of the dielectric material142may then be removed using one or more conventional material removal processes, such as one or more conventional CMP processes.

Referring next toFIG.17A, drain contacts144may be formed on or over upper surfaces of the channel pillars122. In addition, the drain contacts144may be laterally separated from one another by an isolation material146. The drain contacts144and the isolation material146may respectively be substantially similar to and may respectively be formed in substantially the same manner as the drain contacts134and the isolation material136previously described herein with reference toFIGS.14A and14B.FIG.17Bis a simplified partial plan view of the semiconductor device structure100′ at the process stage depicted inFIG.17A.

The semiconductor device structure100′ at the processing stage processing stage depicted inFIG.17A(e.g., following the formation of the drain contacts144) includes multiple vertical access devices145(e.g., vertical transistors, vertical TFTs). The vertical access devices145exhibit “double-gate” configurations, and each individually include one of the channel pillars122, one of the drain contacts144vertically above the channel pillar122, one of the source line contacts104(which is shared between at least some of the vertical access devices145) vertically below the channel pillar122, one of the linear oxide structures114laterally neighboring a side of the channel pillar122, one of the linear gate structures112laterally neighboring the linear oxide structure114, a portion of one of the additional oxide structure125laterally neighboring another side of the channel pillar122, and one of the additional gate structures126laterally neighboring the portion of the additional oxide structure125. The air gaps140of the semiconductor device structure100′ may limit capacitance and increase shorts margin between the linear gate structures112of laterally neighboring vertical access devices145of the semiconductor device structure100′, and the additional air gaps141of the semiconductor device structure100′ may limit capacitance and increase shorts margin between the additional linear gate structures126of laterally neighboring vertical access devices145of the semiconductor device structure100′. The air gaps140and the additional air gaps141of the semiconductive device structure100′ may also reduce cross-talk between laterally neighboring vertical access devices145.

FIG.18illustrates a functional block diagram of a memory device200in accordance with an embodiment of the disclosure. The memory device200may include, for example, an embodiment of a semiconductor device structure previously described herein (e.g., the semiconductor device structures100,100′). The memory device200may include at least one memory cell202between at least one data line204(e.g., bit line, data line) and at least one source line206. The memory cell202may include an access device208(e.g., a vertical access device, such as one of the vertical access devices135,145previously described herein) coupled or connected in series with a memory element210. The access device208may act as a switch for enabling and disabling current flow through the memory element210. By way of non-limiting example, the access device208may be an access device with at least one gate connected to an access line212(e.g., a word line). The access line212may extend in a direction substantially perpendicular to that of the data line204. The data line204and the source line206may be connected to logic for programming and reading the memory element210. A control multiplexer214may have an output connected to the data line204. The control multiplexer214may be controlled by a control logic line216to select between a first input connected to a pulse generator218, and a second input connection to read-sensing logic220(e.g., a sense amplifier).

During a programming operation, a voltage greater than a threshold voltage of the access device208may be applied to the access line212to turn on the access device208. Turning on the access device208completes a circuit between the source line206and the data line204by way of the memory element210. After turning on the access device208, a bias generator222may establish, by way of the pulse generator218, a bias voltage potential difference between the data line204and the source line206. During read operation, the bias generator222may establish, by way of read-sensing logic220, a read bias voltage potential difference between the data line204and the source line206. The read bias voltage may be lower than the reset bias voltage. The read bias voltage may enable current to flow through the memory element210according to a resistance state of an active material thereof. For example, for a given read bias voltage, if the active material is in a high-resistance state (e.g., a reset state), a relatively smaller current may flow through the memory element210than if the active material is in a low-resistance state (e.g., a set state). The amount of current flowing through memory element210during the read operation may be compared to a reference input by the read-sensing logic220to discriminate whether the data stored in the memory cell202is a logic “1” or a logic “0.”

Thus, a memory device according to embodiments of the disclosure comprises an access line, a data line, a source line, memory cells between the data line and the source line, and air gaps. Each memory cell comprises a vertical access device and a memory element. The vertical access device is electrically coupled to the access line and comprises channel pillar, a source contact, a drain contact, a gate electrode, and a gate dielectric material. The channel pillar comprises at least one oxide semiconductor material. The source contact is vertically between the source line and the channel pillar. The drain contact is on the channel pillar. The gate electrode laterally neighbors the channel pillar and is electrically coupled to the access line. The gate dielectric material is between the channel pillar and the gate electrode. The memory element is between the data line and the drain contact of the vertical access device. The air gaps are located between laterally neighboring gate electrodes of laterally neighboring vertical access devices of laterally neighboring memory cells.

Semiconductor device structures (e.g., the semiconductor device structures100,100′) and semiconductor devices (e.g., the memory device200) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG.19is a block diagram of an illustrative electronic system300according to embodiments of disclosure. The electronic system300may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an IPAD® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system300includes at least one memory device302. The memory device302may comprise, for example, an embodiment of one or more of a semiconductor device structure (e.g., semiconductor device structures100,100′) and a semiconductor device (e.g., the memory device200) previously described herein. The electronic system300may further include at least one electronic signal processor device304(often referred to as a “microprocessor”). The electronic signal processor device304may, optionally, include an embodiment of a semiconductor device structure (e.g., semiconductor device structures100,100′) and a semiconductor device (e.g., the memory device200) previously described herein. The electronic system300may further include one or more input devices306for inputting information into the electronic system300by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system300may further include one or more output devices308for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device306and the output device308may comprise a single touchscreen device that can be used both to input information to the electronic system300and to output visual information to a user. The input device306and the output device308may communicate electrically with one or more of the memory device302and the electronic signal processor device304.

Thus, an electronic system according to embodiments of the disclosure comprises an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device comprises at least one access device comprising a laterally heterogeneous oxide semiconductor channel vertically between a metallic source contact and a metallic drain contact, and at least one gate electrode neighboring at least one side surface of the laterally heterogeneous oxide semiconductor channel.

The methods of the disclosure may facilitate the formation of devices (e.g., access devices, semiconductor devices, memory devices) and systems (e.g., electronic systems) having one or more of increased performance, increased efficiency, increased reliability, and increased durability as compared to conventional devices (e.g., conventional access devices, conventional semiconductor devices, conventional memory devices) and conventional systems (e.g., conventional electronic systems). For example, the methods of the disclosure may facilitate improved current flow properties in channel pillars (e.g., the channel pillars122) formed through the methods of the disclosure as compared to conventional channel pillars formed through conventional processes (e.g., conventional channel pillars formed by vertically etching a bulk volume of semiconductive material using one or more conventional etch chemistries, such as conventional hydrogen-containing plasma chemistries), facilitating improved performance and reliability in devices (e.g., access devices, semiconductor devices, memory devices) and systems (e.g., electronic systems) including the channel pillars of the disclosure.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalents.