Patent ID: 12245415

DETAILED DESCRIPTION

Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

It shall be understood that when an element is referred to as being “connected to” or “coupled to” another element, the initial element may be directly connected to, or coupled to, another element, or to other intervening elements.

It shall be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limited to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be further understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

It should be noted that the term “about” modifying the quantity of an ingredient, component, or reactant of the present disclosure employed refers to variation in the numerical quantity that may occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation may occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. In yet another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

FIG.1Ais a top view of a semiconductor device100, in accordance with some embodiments of the present disclosure.

In some embodiments, the semiconductor device100can include a cell region in which a memory device, such as the structure as shown inFIGS.1A and1B, is formed. The memory device can include, for example, a dynamic random access memory (DRAM) device, a one-time programming (OTP) memory device, a static random access memory (SRAM) device, or other suitable memory devices. In some embodiments, a DRAM can include, for example, a transistor, a capacitor, and other components.

During read operation, a word line can be asserted, turning on the transistor. The enabled transistor allows the voltage across the capacitor to be read by a sense amplifier through a bit line. During a write operation, the data to be written can be provided on the bit line when the word line is asserted.

In some embodiments, the semiconductor device100can include a peripheral region (not shown) utilized to form a logic device (e.g., system-on-a-Chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) device)), a front-end device (e.g., analog front-end (AFE) devices) or other device.

As shown inFIG.1A, the semiconductor device100may include a substrate102, a plurality of metallization layers116-1and116-2, a plurality of metallization layers120-1and120-2, a plurality of gate dielectrics104-1and104-2, a plurality of channel layers106-1and106-2, as well as a dielectric layer112.

The substrate102may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate102may include an elementary semiconductor including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form, a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, any other suitable material, or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy with a gradient Ge feature in which the Si and Ge composition changes from one ratio at one location to another ratio with location of the feature. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, a SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate102may have a multilayer structure, or the substrate102may include a multilayer compound semiconductor structure.

The substrate102may have multiple doped regions (not shown) therein. In some embodiments, p type and/or n type dopants may be doped in the substrate102. In some embodiments, p type dopants include boron (B), other group III elements, or any combination thereof. In some embodiments, n type dopants include arsenic (As), phosphorus (P), other group V elements, or any combination thereof.

Each of the metallization layers116-1and116-2may extend along the Y-axis. Each of the metallization layers116-1and116-2may be parallel. In some embodiments, each of the metallization layers116-1and116-2may be physically separated. The metallization layers116-1and116-2may include conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), the like, and/or a combination thereof. In some embodiments, the metallization layers116-1and116-2may be referred to as a word line.

The metallization layer116-1may include a sidewall116s1and a sidewall116s2opposite thereto. The sidewall116s2of the metallization layer116-1may face the metallization layer116-2. In some embodiments, the metallization layer116-1may have a protruding portion116-1p. In some embodiments, the protruding portion116-1pof the metallization layer116-1may face the metallization layer116-2. In some embodiments, the sidewall116s2of the metallization layer116-1may protrude toward the metallization layer116-2, thereby defining the protruding portion116-1p.

The metallization layer116-2may include a sidewall116s3and a sidewall116s4opposite to the sidewall116s3. The sidewall116s3of the metallization layer116-2may face the metallization layer116-1. In some embodiments, the metallization layer116-2may have a protruding portion116-2p. In some embodiments, the protruding portion116-2pof the metallization layer116-2may face metallization layer116-1. In some embodiments, the sidewall116s3of the metallization layer116-2may protrude toward the metallization layer116-1, thereby defining the protruding portion116-2p.

In some embodiments, the protruding portion116-1pof the metallization layer116-1and the protruding portion116-2pof the metallization layer116-2may be staggered. In some embodiments, the protruding portion116-1pof the metallization layer116-1is misaligned with the protruding portion116-2pof the metallization layer116-2along the X-axis. In some embodiments, the protruding portion116-1pof the metallization layer116-1may be free from overlapping the protruding portion116-2pof the metallization layer116-2along the X-axis. In other embodiments, the protruding portion116-1pof the metallization layer116-1may partially overlap with the protruding portion116-2pof the metallization layer116-2along the X-axis. In some embodiments, the protruding portion116-1pand/or116-2pmay have a half-circular or a half-elliptical profile from a top view. However, the present disclosure is not intended to be limiting.

The metallization layers120-1and120-2may be disposed over the metallization layers116-1and116-2. Each of the metallization layers120-1and120-2may extend along the X-axis. Each of the metallization layers120-1and120-2may be parallel. Each of the metallization layers120-1and120-2may be physically separated. In some embodiments, the metallization layers120-1and120-2may be located at a horizontal level higher than that of the metallization layers116-1and116-2. The metallization layers120-1and120-2may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof. In some embodiments, the metallization layers120-1and120-2may be referred to as a bit line.

In some embodiments, the gate dielectrics104-1and104-2may be disposed on a sidewall (not annotated in the figures) of the word line (e.g.,116-1and116-2). In some embodiments, the gate dielectric104-1may be embedded in the metallization layer116-1. In some embodiments, the gate dielectric104-2may be embedded in the metallization layer116-2. In some embodiments, the gate dielectric104-1may be surrounded by the metallization layer116-1. In some embodiments, the gate dielectric104-2may be surrounded by the metallization layer116-2. In some embodiments, each of the gate dielectrics104-1and104-2may overlap the metallization layer120-1or120-2along the Z-axis.

In some embodiments, the gate dielectrics104-1and104-2may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer may include dielectric material(s), such as high-k dielectric material. The high-k dielectric material may have a dielectric constant (k value) greater than 4. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2) or another applicable material. Other suitable materials are within the contemplated scope of this disclosure. In some embodiments, the gate dielectrics104-1and104-2may include a ring having a circular, oval, elliptical, or other profile.

In some embodiments, each of the channel layers106-1and106-2may be disposed on a sidewall (not annotated in the figures) of the gate dielectric104-1or104-2. In some embodiments, each of the channel layers106-1and106-2may be embedded in the gate dielectric104-1or104-2. In some embodiments, each of the channel layers106-1and106-2may be surrounded by the gate dielectric104-1or104-2. In some embodiments, each of the channel layers106-1and106-2may be in contact with the gate dielectric104-1or104-2. In some embodiments, each of the channel layers106-1and106-2may overlap the metallization layer120-1or120-2along the Z-axis. In some embodiments, each of the channel layers106-1and106-2may be completely surrounded by the gate dielectric104-1or104-2from a top view.

In some embodiments, each of the channel layers106-1and106-2may be disposed on a sidewall (not annotated in the figures) of the metallization layer116-1or116-2. In some embodiments, each of the channel layers106-1and106-2may be embedded in the metallization layer116-1or116-2. In some embodiments, each of the channel layers106-1and106-2may be surrounded by the metallization layer116-1or116-2.

In some embodiments, the channel layers106-1and106-2may be staggered. In some embodiments, the channel layer106-1may be misaligned with the channel layer106-2along the X-axis. In some embodiments, the channel layer106-1may overlap the protruding portion116-1pof the metallization layer116-1along the X-axis. In some embodiments, the channel layer106-2may overlap the protruding portion116-2pof the metallization layer116-2along the X-axis.

The sidewall116s1of the metallization layer116-1and the channel layer106-1may have a distance D1there between along the X-axis. The sidewall116s2of the metallization layer116-1and the channel layer106-1may have a distance D2there between along the X-axis. In some embodiments, the distance D1may be different from the distance D2. In some embodiments, the distance D2may be greater than the distance D1.

The sidewall116s3of the metallization layer116-2and the channel layer106-2may have a distance D3there between along the X-axis. The sidewall116s4of the metallization layer116-2and the channel layer106-2may have a distance D4there between along the X-axis. In some embodiments, the distance D3may be different from the distance D4. In some embodiments, the distance D3may be greater than the distance D4.

In some embodiments, the sidewall116s1of the metallization layer116-1may have a relatively straight edge. In some embodiments, the sidewall116s4of the metallization layer116-2may have a relatively straight edge. The metallization layer116-1sof the metallization layer116-1and the sidewall116s4of the metallization layer116-2may have a distance D5there between along the X-axis. In some embodiments, the distance D5may be substantially even or invariable along the Y-axis.

The metallization layer116-2sof the metallization layer116-1and the sidewall116s3of the metallization layer116-2may have a distance D6there between along the X-axis. In some embodiments, the distance D6may vary along the Y-axis.

The material of the channel layers106-1and106-2may include an amorphous semiconductor, a poly-semiconductor and/or metal oxide. The semiconductor may include, but is not limited to, germanium (Ge), silicon (Si), tin (Sn), antimony (Sb). The metal oxide may include, but is not limited to, indium oxide; tin oxide; zinc oxide; a two-component metal oxide such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide; a three-component metal oxide such as an In—Ga—Zn-based oxide (also represented as IGZO), an In—Al—Zn-based oxide, an In—S based oxide (also represented as ITO), an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, or an In—Lu—Zn-based oxide; and a four-component metal oxide such as an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide, but the present disclosure is not limited in this regard.

In some embodiments, the dielectric layer112may be disposed on a sidewall (not annotated in the figures) of the metallization layer116-1or116-2. In some embodiments, the dielectric layer112may be disposed between the metallization layers116-1and116-2. In some embodiments, each of the gate dielectrics104-1and104-2may be physically spaced apart from the dielectric layer112. In some embodiments, each of the gate dielectrics104-1and104-2may be physically spaced apart from the dielectric layer112by the metallization layer116-1or116-2.

In some embodiments, each of the channel layer106-1or106-2may be physically spaced apart from the dielectric layer112. In some embodiments, the channel layer106-1or106-2may be physically spaced apart from the dielectric layer112by the gate dielectrics104-1and104-2as well as by the metallization layer116-1or116-2.

The dielectric layer112may include silicon oxide (SiOx, silicon nitride (SixNy), silicon oxynitride (SiON), or other suitable materials. In some embodiments, the material of the dielectric layer112may be different from that of the gate dielectrics104-1and104-2. In some embodiments, the material of the dielectric layer112may be the same as that of the gate dielectrics104-1and104-2with different quality or film density.

FIG.1Bis a cross-sectional view along line A-A′ of the semiconductor device100as shown inFIG.1A, in accordance with some embodiments of the present disclosure.

As shown inFIG.1B, the semiconductor device100may further include a plurality of capacitors108-1and108-2, a dielectric layer110, a dielectric layer114, and contact plugs118.

In some embodiments, the capacitor108-1may be electrically connected to the metallization layer120-1through the contact plug118and the channel layer106-1. In some embodiments, the capacitor108-2may be electrically connected to the metallization layer120-2through the contact plug118and the channel layer106-2.

In some embodiments, the capacitors108-1and108-2may be embedded in the substrate102. In some embodiments, each of the capacitors108-1and108-2may include a first electrode, a capacitor dielectric, and a second electrode (not annotated in the figures). In some embodiments, each of the capacitors108-1and108-2may have a circular, oval, elliptical, or similar profile from a top view. In some embodiments, the capacitor dielectric may surround the first electrode. In some embodiments, the second electrode may surround the first electrode. In some embodiments, the second electrode may surround the capacitor dielectric. In some embodiments, the capacitor dielectric may be disposed between the first electrode and the second electrode.

The first electrode and/or second electrode may include a semiconductor material or a conductive material. The semiconductor material may include polysilicon or other suitable materials. The conductive material may include tungsten, copper, aluminum, tantalum, or other suitable materials.

The capacitor dielectric may include dielectric materials, such as silicon oxide, tungsten oxide, zirconium oxide, copper oxide, aluminum oxide, hafnium oxide, or the like.

In some embodiments, the contact plug118may be disposed between the capacitor108-1and the channel layer106-1. The contact plug118may include a semiconductor material or a conductive material.

The dielectric layer110may be disposed on the substrate102. The dielectric layer110may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material (k<4), or other suitable materials. The dielectric layer110may also be referred to as a lower dielectric.

The dielectric layer114may be disposed on the metallization layers116-1and116-2. The dielectric layer114may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material (k<4), or other suitable materials. In some embodiments, the metallization layers120-1and120-2may be disposed on the dielectric layer114. The dielectric layer115may also be referred to as an upper dielectric.

In some embodiments, each of the gate dielectrics104-1and104-2may penetrate the dielectric layer114. In some embodiments, each of the gate dielectrics104-1and104-2may penetrate the dielectric layer110. In some embodiments, each of the gate dielectrics104-1and104-2may penetrate the metallization116-1or116-2.

In some embodiments, each of the channel layers106-1and106-2may penetrate the dielectric layer114. In some embodiments, each of the channel layers106-1and106-2may penetrate the dielectric layer110. In some embodiments, each of the channel layers106-1and106-2may penetrate the metallization116-1or116-2.

In some embodiments, a word line (e.g., metallization layer116-1or116-2), gate dielectric104-1or104-2, and a channel layer106-1or106-2may be included in a transistor. During a read operation, a word line (e.g., metallization layer116-1or116-2) may be asserted, turning on a transistor, which may be formed in a peripheral region. The enabled transistor allows the voltage across a capacitor (e.g., capacitor108-1or capacitor108-2) to be read by a sense amplifier through a bit line (e.g., metallization layer120-1or120-2). During a write operation, the data to be written may be provided on the bit line (e.g., metallization layer120-1or120-2) when the word line (e.g., metallization layer116-1or116-2) is asserted.

In this embodiment, the metallization layer116-1may have a protruding portion116-1p, and the channel layer106-1may be partially surrounded by the protruding portion116-1p. The protruding portion116-1pmay allow a relatively great overlay error when patterning the metallization layer116-1, which may prevent electrical leakage between the metallization layer116-1and the channel layer106-1.

In this embodiment, the protruding portion116-1pof the metallization layer116-1may face the metallization layer116-2, and the protruding portion116-2pof the metallization layer116-2may face the metallization layer116-1, thereby reducing the size of the semiconductor device100.

FIGS.2A and2Billustrate a semiconductor device200in accordance with some embodiments of the present disclosure, whereinFIG.2Ais a top view, andFIG.2Bis a cross-sectional view along line B-B′ ofFIG.2A. It should be noted that some elements or features are omitted fromFIG.2Afor brevity. The semiconductor device200is similar to the semiconductor device100as shown inFIG.1AandFIG.1B, with differences there between as follows.

As shown inFIG.2A, the semiconductor device200may include a substrate202, a plurality of metallization layers216-1and216-2, a plurality of gate dielectrics204-1and204-2, a plurality of channel layers206-1and206-2, as well as a dielectric layer212.

Each of the metallization layers216-1and216-2may extend along the Y-axis. Each of the metallization layers216-1and216-2may be parallel. In some embodiments, each of the metallization layers216-1and216-2may be physically separated. The material of the metallization layer216-1and the metallization layer216-2may be the same as or similar to that of the metallization layer116-1. In some embodiments, the metallization layers216-1and216-2may be referred to as a top word line. In some embodiments, the metallization layers116-1and116-2(shown inFIG.2B) may be referred to as a bottom word line.

In some embodiments, the material of the substrate202may be the same as or similar to that of the substrate102. In some embodiments, the substrate202may also be referred to as a top substrate. In some embodiments, the substrate102(shown inFIG.2B) may also be referred to as a bottom substrate.

The metallization layer216-1may include a sidewall216s1and a sidewall216s2opposite thereto. The sidewall216s2of the metallization layer216-1may face the metallization layer216-2. In some embodiments, the metallization layer216-1may have a protruding portion216-1p. In some embodiments, the protruding portion216-1pof the metallization layer216-1may face metallization layer216-2. In some embodiments, the sidewall216s2of the metallization layer216-1may protrude toward the metallization layer216-2, thereby defining the protruding portion216-1p.

The metallization layer216-2may include a sidewall216s3and a sidewall216s4opposite thereto. The sidewall216s3of the metallization layer216-2may face the metallization layer216-1. In some embodiments, the metallization layer216-2may have a protruding portion216-2p. In some embodiments, the protruding portion216-2pof the metallization layer216-2may face metallization layer216-1. In some embodiments, the sidewall216s3of the metallization layer216-2may protrude toward the metallization layer216-1, thereby defining the protruding portion216-2p.

In some embodiments, the protruding portion216-1pof the metallization layer216-1and the protruding portion216-2pof the metallization layer216-2may be staggered. In some embodiments, the protruding portion216-1pof the metallization layer216-1may be misaligned with the protruding portion216-2pof the metallization layer216-2along the X-axis. In some embodiments, the protruding portion216-1pof the metallization layer216-1may be free from overlapping the protruding portion216-2pof the metallization layer216-2along the X-axis. In other embodiments, the protruding portion216-1pof the metallization layer216-1may partially overlap with the protruding portion216-2pof the metallization layer216-2along the X-axis. In some embodiments, the protruding portion216-1pand/or216-2pmay have a half-circular profile or a half-elliptical profile from a top view. However, the present disclosure is not intended to be limiting.

In some embodiments, the metallization layer216-1may be disposed on the metallization layer120-1. In some embodiments, the metallization layer216-2may be disposed on the metallization layer120-2. In some embodiments, each of metallization layers216-1and216-2may be located at a horizontal level higher than that of the metallization layers120-1and120-2.

In some embodiments, the gate dielectrics204-1and204-2may be disposed on a sidewall (not annotated in the figures) of the word line. In some embodiments, the gate dielectric204-1may be embedded in the metallization layer216-1. In some embodiments, the gate dielectric204-2may be embedded in the metallization layer216-2. In some embodiments, the gate dielectric204-1may be surrounded by the metallization layer216-1. In some embodiments, the gate dielectric204-2may be surrounded by the metallization layer216-2. In some embodiments, each of the gate dielectrics204-1and204-2may overlap the metallization layer120-1or120-2along the Z-axis.

In some embodiments, the material of the gate dielectrics204-1and204-2may be the same as or similar to that of the gate dielectric104-1. In some embodiments, the gate dielectrics204-1and204-2may be referred to as a top gate dielectric layer, and the gate dielectrics104-1and104-2(shown inFIG.2B) may be referred to as a bottom gate dielectric layer.

In some embodiments, each of the channel layers206-1and206-2may be disposed on a sidewall (not annotated in the figures) of the gate dielectric204-1or204-2. In some embodiments, each of the channel layers206-1and206-2may be embedded in the gate dielectric204-1or204-2. In some embodiments, each of the channel layers206-1and206-2may be surrounded by the gate dielectric204-1or204-2. In some embodiments, each of the channel layers206-1and206-2may be in contact with the gate dielectric204-1or204-2.

In some embodiments, each of the channel layers206-1and206-2may be disposed on a sidewall (not annotated in the figures) of the metallization layer216-1or216-2. In some embodiments, each of the channel layers206-1and206-2may be embedded in the metallization layer216-1or216-2. In some embodiments, each of the channel layers206-1and206-2may be surrounded by the metallization layer216-1or216-2.

In some embodiments, the material of the channel layers206-1and206-2may be the same as or similar to that of the channel layer106-1. In some embodiments, the channel layers206-1and206-2may be referred to as a top channel layer, and the channel layers106-1and106-2(shown inFIG.2B) may be referred to as a bottom channel layer.

In some embodiments, the channel layers206-1and206-2may be staggered. In some embodiments, the channel layer206-1may be misaligned with the channel layer206-2along the X-axis. In some embodiments, the channel layer206-1may be free from overlapping the channel layer206-2along the X-axis. In some embodiments, the channel layer206-1may overlap the protruding portion216-1palong the X-axis. In some embodiments, the channel layer206-2may overlap the protruding portion216-2palong the X-axis.

In some embodiments, each of the channel layers206-1and206-2may overlap the metallization layer120-1or120-2along the Z-axis. In some embodiments, each of the channel layers206-1and206-2may be completely surrounded by the gate dielectric204-1or204-2from a top view.

The sidewall216s1of the metallization layer216-1and the channel layer206-1may have a distance D7there between along the X-axis. The sidewall216s2of the metallization layer216-1and the channel layer206-1may have a distance D8there between along the X-axis. In some embodiments, the distance D7may be different from the distance D8. In some embodiments, the distance D8may be greater than the distance D7.

The sidewall216s3of the metallization layer216-2and the channel layer206-2may have a distance D9there between along the X-axis. The sidewall216s4of the metallization layer216-2and the channel layer206-2may have a distance D10there between along the X-axis. In some embodiments, the distance D9may be different from the distance D10. In some embodiments, the distance D9may be greater than the distance D10.

In some embodiments, the sidewall216s1of the metallization layer216-1may have a relatively straight edge. In some embodiments, the sidewall216s4of the metallization layer216-2may have a relatively straight edge. The metallization layer216-1sof the metallization layer216-1and the sidewall216s4of the metallization layer216-2may have a distance D11there between along the X-axis. In some embodiments, the distance D11may be substantially even or invariable along the Y-axis.

The metallization layer216-2sof the metallization layer216-1and the sidewall216s3of the metallization layer216-2may have a distance D12there between along the X-axis. In some embodiments, the distance D12may vary along the Y-axis.

In some embodiments, the dielectric layer212may be disposed on the sidewall of the metallization layer216-1or216-2. In some embodiments, the dielectric layer212may be disposed between the metallization layers216-1and216-2. In some embodiments, each of the gate dielectrics204-1and204-2may be physically spaced apart from the dielectric layer212. In some embodiments, each of the gate dielectrics204-1and204-2may be physically spaced apart from the dielectric layer212by the metallization layer216-1or216-2. In some embodiments, the material of the dielectric layer212may be the same as or similar to that of the dielectric layer112.

In some embodiments, each of the channel layer206-1or206-2may be physically spaced apart from the dielectric layer212. In some embodiments, the channel layer206-1or206-2may be physically spaced apart from the dielectric layer212by the gate dielectrics204-1and204-2as well as by the metallization layer216-1or216-2.

As shown inFIG.2B, the semiconductor device200may include cells140-1,140-2,240-1, and240-2. Each of the cells240-1and240-2may be located at a horizontal level higher than that of the cells140-1and140-2. In some embodiments, each of the cells140-1and the140-2may also be referred to as a bottom cell. In some embodiments, each of the cells240-1and240-2may also be referred to as a top cell.

The cell140-1may include the capacitor108-1, channel layer106-1, metallization layer116-1, contact plug118-1, and metallization layer120-1.

The cell140-2may include the capacitor108-2, channel layer106-2, metallization layer116-2, contact plug118-2, and metallization layer120-2.

The cell240-1may include a capacitor208-1, channel layer206-1, metallization layer216-1, contact plug218-1and metallization layer120-1.

The cell240-2may include a capacitor208-2, channel layer206-2, metallization layer216-2, contact plug218-2, and metallization layer120-2.

In some embodiments, the protruding portion216-1pof the metallization layer216-1may partially or completely overlap the protruding portion116-1pof the metallization layer116-1along the Z-axis. In some embodiments, the protruding portion216-2pof the metallization layer216-2may partially or completely overlap the protruding portion116-2pof the metallization layer116-2along the Z-axis.

In some embodiments, the metallization layers120-1and120-2may be disposed within a dielectric layer150. In some embodiments, the metallization layer120-1may be disposed between the cells140-1and240-1. In some embodiments, the metallization layer120-1may be disposed between the channel layers106-1and206-1.

In some embodiments, the metallization layer120-1may be disposed between the channel layers106-1and206-1. In some embodiments, the metallization layer120-1may be disposed between the metallization layers116-1and216-1. In some embodiments, the metallization layer120-1may be disposed between the capacitors108-1and208-1. In some embodiments, the metallization layer120-1may be disposed between the channel layer106-1and capacitor208-1. In some embodiments, the metallization layer120-1may function as a common bit line of the cells140-1and the240-1. In some embodiments, the metallization layer120-2may function as a common bit line of the cells140-2and the240-2.

In this embodiment, the metallization layer120-1may function as a common bit line. Therefore, the size of the semiconductor device200may be reduced. Further, the capacitance of the semiconductor device200may be increased.

FIG.3is a flowchart illustrating a method300of manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.

The method300begins with operation302, in which a substrate may be provided. In some embodiments, a first capacitor and a second capacitor may be formed within the substrate. In some embodiments, contact plugs may be formed within the substrate and over the first capacitor and the second capacitor. In some embodiments, a first dielectric layer may be formed on the substrate. In some embodiments, a conductive layer may be formed on the first dielectric layer. In some embodiments, a second dielectric layer may be formed on the conductive layer.

The method300continues with operation304in which a patterning process may be performed to remove a portion of the first dielectric layer, the second dielectric layer, and the conductive layer. As a result, a first word line and a second word line are formed. A plurality of openings may be formed to expose an upper surface of the substrate.

In some embodiments, the conductive layer may be patterned to form a first protruding portion of the first word line. In some embodiments, the conductive layer may be patterned to form a second protruding portion of the second word line. In some embodiments, the first protruding portion may face the second word line. In some embodiments, the second protruding portion may face the first word line.

The method300continues with operation306in which a third dielectric layer may be formed to fill the openings.

The method300continues with operation308in which a portion of the second dielectric layer, the first word line and the second word line, and the first dielectric layer may be removed. An opening in the first word line may be formed. An opening in the second word line may be formed.

The method300continues with operation310in which a first gate dielectric and a first channel layer may be formed within the opening of the first word line. A second gate dielectric and a second channel layer may be formed within the opening of the second word line.

The method300continues with operation312in which a first bit line and a second bit line may be formed on the first channel layer and the second channel layer, respectively, thereby forming a semiconductor device.

The method300is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, or after each operation of the method300, and some operations described can be replaced, eliminated, or reordered for additional embodiments of the method. In some embodiments, the method300can include further operations not depicted inFIG.3. In some embodiments, the method300can include one or more operations depicted inFIG.3.

FIG.4AtoFIG.9AandFIG.4BtoFIG.9Billustrate one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of the present disclosure, whereinFIG.4AtoFIG.9Aare top views, andFIG.4BtoFIG.9Bare cross-sectional views along line A-A′ ofFIG.4AtoFIG.9A, respectively. It should be noted that, for brevity, some elements are illustrated in cross-sectional views but not in top views.

As shown inFIG.4AandFIG.4B, a substrate102may be provided. In some embodiments, capacitors108-1and108-2may be formed within the substrate102. In some embodiments, contact plugs118may be formed within the substrate102and over the capacitors108-1and108-2. In some embodiments, a dielectric layer110may be formed on the substrate102. In some embodiments, a conductive layer116may be formed on the dielectric layer110. In some embodiments, a dielectric layer114may be formed on the conductive layer116. The dielectric layer110and dielectric layer114may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), or other suitable processes. The conductive layer116may be formed by sputtering, PVD, or other suitable processes.

As shown inFIG.5AandFIG.5B, a patterning process may be performed to remove a portion of the dielectric layer110, dielectric layer114, and conductive layer116. As a result, metallization layers116-1and116-2are formed. A plurality of openings116r1may be formed to expose an upper surface of the substrate102. The patterning process may include lithography, etching, or other suitable processes. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include, for example, dry or wet etching.

In some embodiments, the conductive layer116may be patterned to form a protruding portion116-1pof the metallization layer116-1. In some embodiments, the conductive layer116may be patterned to form a protruding portion116-2pof the metallization layer116-2. In some embodiments, the protruding portion116-1pmay face the metallization layer116-2. In some embodiments, the protruding portion116-2pmay face the metallization layer116-1.

As shown inFIG.6AandFIG.6B, a dielectric layer112may be formed to fill the openings1160. The dielectric layer112may be formed by CVD, ALD, PVD, LPCVD, or other suitable processes.

As shown inFIG.7AandFIG.7B, a portion of the dielectric layer114, the metallization layers116-1and116-2, and the dielectric layer110may be removed. An opening116r2-1of the metallization layer116-1may be formed. An opening116r2-2of the metallization layer116-2may be formed. In some embodiments, the openings116r2-1and116r2-2may be staggered. In some embodiments, the openings116r2-1may be free from overlapping the opening116r2-2along the X-axis. In other embodiments, the openings116r2-1may partially overlap the opening116r2-2along the X-axis.

As shown inFIG.8AandFIG.8B, a gate dielectric104-1and a channel layer106-1may be formed within the opening116r2-1. A gate dielectric104-2and a channel layer106-2may be formed within the opening116r2-2. The gate dielectrics104-1and104-2as well as the channel layers106-1and106-2may be formed by CVD, ALD, PVD, LPCVD, or other suitable processes.

As shown inFIG.9AandFIG.9B, metallization layers120-1and120-2may be formed on the dielectric layer112, thereby forming the semiconductor device100. The metallization layers120-1and120-2may be formed by sputtering, PVD, or other suitable processes.

In this embodiment, the word line (e.g.,116-1and/or116-2) has a protruding portion (e.g.,116-1pand116-2p). The protruding portion may allow a relatively great overlay error when patterning the word line to form an opening (e.g.,116r2-1and/or116r2-2) within which a channel layer (e.g.,106-1and/or106-2) is formed. Therefore, electrical leakage between the word line and the channel layer may be prevented.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a dielectric layer, a first metallization layer, first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.

Another aspect of the present disclosure provides another semiconductor device. The semiconductor device includes a bottom substrate, a first bottom cell, a top substrate, a first top cell, and a common bit line. The first bottom cell includes a first bottom capacitor disposed within the bottom substrate. The first bottom cell also includes a first bottom word line disposed on the bottom substrate and extending along a first direction. The first bottom cell further includes a first bottom channel layer surrounded by the first bottom word line. The first top cell includes a first top capacitor disposed within the top substrate. The first top cell also includes a first top word line disposed on the top substrate and extending along the first direction. The first top cell further includes a first top channel layer surrounded by the first top word line. The common bit line is disposed between the first bottom cell and the first top cell and extends along a second direction substantially perpendicular to the first direction.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate. The method also includes forming a conductive layer on the substrate. The method further includes patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction. The first metallization layer has a first protruding portion protruding toward the second metallization layer. In addition, the method includes forming a first channel layer within the first metallization layer and a second channel layer within the second metallization layer.

The embodiments of the present disclosure provide a semiconductor device. The semiconductor device may include a word line with a protruding portion. The protruding portion may allow a relatively great overlay error of patterning the word line to form an opening within which a channel layer is formed, which may prevent electrical leakage between the word line and the channel layer.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above may be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.