Patent ID: 12249608

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

FIG.1is a circuit diagram of a memory array100in accordance with some embodiments of the present disclosure. The memory array100may include a plurality of unit cells, and each unit cell100A,100B,100C or100D of the memory array100of the present disclosure may include two transistors. As shown inFIG.1, a transistor T1and a transistor T2together define a unit cell100A of the memory array100. Take the unit cell100A as an example, a terminal Q1of the transistor T1is coupled to a write bit line WBL1, another terminal Q2of the transistor T1is coupled to a gate of the transistor T2, and a gate of the transistor T1is coupled to a write word line WWL1. A terminal Q3of the transistor T2is coupled to a read bit line RBL1, and another terminal Q4of the transistor T2is coupled to a read word line RWL1. In some embodiments, the transistor T1is configured to store bit information of the unit cell100A. In some embodiments, the transistor T1is configured to access the bit information contained in the transistor T2through a read or write operation.

In some embodiments, arrangements of other unit cells100B,100C and100D of the memory array100are similar to arrangement of the unit cell100A including the transistors T1and T2as illustrated above. In some embodiments, other unit cells100B,100C and100D individually include transistors T3and T4, transistors T5and T6, and transistors T7and T8. In some embodiments, a terminal Q6of the transistor T3is coupled to a gate of the transistor T4. In some embodiments, a terminal Q5is coupled to the write bit line WBL1. In some embodiments, a gate of the transistor T3and a gate of the transistor T7are coupled to a write word line WWL2. In some embodiments, a terminal Q7of the transistor T4is coupled to the read bit line RBL1. In some embodiments, a terminal Q8of the transistor T4and a terminal Q16of the transistor T8are coupled to a read word line RWL1. In some embodiments, a terminal Q9of the transistor T5and a terminal Q13of the transistor T7are coupled to a write bit line WBL2. In some embodiments, a gate of the transistor T5is coupled to the write word line WWL1. In some embodiments, a terminal Q10of the transistor T5is coupled to a gate of the transistor T6. In some embodiments, a terminal Q11of the transistor T6and a terminal Q15of the transistor T8are coupled to a read bit line RBL2. In some embodiments, a terminal Q12of the transistor T6is coupled to the read word line RWL1. In some embodiments, a terminal Q14of the transistor T7is coupled to a gate of the transistor T8.

In some embodiments, the memory array100is arranged in an interconnection structure disposed over a logic circuit or a logic device, and thus a product size can be minimized. In order to achieve the memory cell100in the interconnection structure, the present disclosure provides semiconductor structures in accordance with different embodiments of the present disclosure, and illustration is provided in the following description combined with figures.

FIG.2is a schematic diagram of a semiconductor structure200in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor structure200is part of a memory array. In some embodiments, the semiconductor structure200is disposed in an interconnection structure over a substrate (detailed illustration is provided in the following description combined withFIG.3). In some embodiments, the semiconductor structure200is disposed between two metal line layers of the interconnection structure. The semiconductor structure200may include a first transistor11, a second transistor12, a third transistor13and a fourth transistor14disposed at a same elevation. In some embodiments, at least one of the four transistors11,12,13and14include a thin-film transistor. In some embodiments, each of the four transistors11,12,13, and14includes gate structures113,123,133and143, respectively, at a same elevation. In some embodiments, the gate structures113,123,133and143are formed concurrently in a same layer. In some embodiments, the gate structures113,123,133and143include a same material. In some embodiments, the material of the gate structure113,123,133or143includes tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), other suitable conductive materials, or a combination thereof. In some embodiments, thicknesses of the gate structures113,123,133and143measured in a vertical direction are substantially different. In some embodiments, the thicknesses of the gate structures113,123,133and143are substantially equal. In some embodiments, the thicknesses of the gate structures113,123,133and143are in a range of 100 to 500 angstroms (Å).

In some embodiments, each of the four transistors11,12,13and14includes source/drain structures111and112,121and122,131and132, and141and142, respectively, at a same elevation higher than the elevation of the gate structures113,123,133and143. In some embodiments, the source/drain structures111,112,121,122,131,132,141and142are formed concurrently in a same layer. In some embodiments, the source/drain structures111,112,121,122,131,132,141and142include a same material. In some embodiments, the material of the source/drain structures111,112,121,122,131,132,141and142includes tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), other suitable conductive materials, or a combination thereof. In some embodiments, thicknesses of the source/drain structures111,112,121,122,131,132,141and142are different. In some embodiments, the thicknesses of the source/drain structures111,112,121,122,131,132,141and142are substantially equal. In some embodiments, the thicknesses of the source/drain structures111,112,121,122,131,132,141and142are in a range of 100 to 700 Å. It should be noted that each of elements111,112,121,122,131,132,141and142can be a source structure or a drain structure of a corresponding transistor. For a purpose of illustration, each of the elements111,112,121,122,131,132,141and142may be referred to as a source structure, a drain structure, or a source/drain structure in different embodiments, but such terms are not intended to limit the present disclosure.

In some embodiments, a semiconductor layer114is disposed between the source/drain structures111,112,121and122and the gate structures113and123. In other words, the source/drain structures and the gate structure of each of the transistors11and12are on two opposite sides of the semiconductor layer114. In some embodiments, the semiconductor layer114is overlapped by the source/drain structures (e.g.,111,112,121and122) of the first transistor11and the second transistor12and overlaps the gate structures (e.g.,113and123) of the first transistor11and the second transistor12. In other words, the first transistor11and the second transistor12have a common semiconductor layer114.

In some embodiments, a semiconductor layer134is disposed between the source/drain structures131,132,141and142and the gate structures133and143. In other words, the source/drain structures and the gate structure of each of the transistors13and14are on two opposite sides of the semiconductor layer134. In some embodiments, the semiconductor layer134is overlapped by the source/drain structures (e.g.,131,132,141and142) of the third transistor13and the fourth transistor14and overlaps the gate structures (e.g.,133and143) of the third transistor13and the fourth transistor14. In other words, the third transistor13and the fourth transistor14have a common semiconductor layer134. In some embodiments, the semiconductor layer114is at a same elevation as the semiconductor layer134.

In some embodiments, the semiconductor layers114and134are formed concurrently or by a same patterning operation in a layer. In some embodiments, the semiconductor layers114and134are formed in the layer after formation of the gate structures (e.g.,113,123,133and143) and prior to formation of the source/drain structures (e.g.,111,112,121,122,131,132,141and142). In some embodiments, the semiconductor layers114and134is an oxide semiconductor layer. In some embodiments, the semiconductor layers114and134include a same material. In some embodiments, the material of the semiconductor layers114and134includes indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (In2O3), gallium oxide (Ga2O3), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), aluminum zinc oxide (Al2O5Zn2), aluminum doped zinc oxide (AZO), indium tungsten oxide (IWO), titanium oxide (TiOx), semiconductor materials including III-V materials, alloys including a combination of above materials, or a combination thereof. The semiconductor layers114and134are a single layer structure or a multi-layer structure including one or more of the above-mentioned materials. In some embodiments, thicknesses of the semiconductor layers114and134are different. In some embodiments, the thicknesses of the semiconductor layers114and134are substantially equal. In some embodiments, the thickness of the semiconductor layers114or134is in a range of 30 to 200 Å. In some embodiments, a surficial area of the semiconductor layer114or134is greater than 1000 nm2. In some embodiments, a width of the semiconductor layer114or134is greater than 50 nm. In some embodiments, a length of the semiconductor layer114or134is greater than 200 nm.

In some embodiments, a gate dielectric layer115is disposed between the semiconductor layer114and the gate structures (e.g.,113and123) of the first transistor11and the second transistor12. In some embodiments, the gate dielectric layer115is overlapped by the source/drain structures (e.g.,111,112,121and122) of the first transistor11and the second transistor12and overlaps all of the gate structures (e.g.,113and123) of the first transistor11and the second transistor12. In other words, the first transistor11and the second transistor12share the gate dielectric layer115. In some embodiments, a gate dielectric layer135is disposed between the semiconductor layer134and the gate structures (e.g.,133and143) of the third transistor13and the fourth transistor14.

In some embodiments, the gate dielectric layer135is overlapped by the source/drain structures (e.g.,131,132,141and142) of the third transistor13and the fourth transistor14and overlaps all of the gate structures (e.g.,133and143) of the third transistor13and the fourth transistor14. In other words, the third transistor13and the fourth transistor14share the gate dielectric layer135. In some embodiments, the gate dielectric layer135is at a same elevation as the gate dielectric layer115. In some embodiments, the gate dielectric layer135and the gate dielectric layer115are at a same layer.

In some embodiments, the gate dielectric layers115and135are formed prior to the formation of the semiconductor layers114and134. In some embodiments, the semiconductor layers (e.g.,114and134) and the gate dielectric layers (e.g.,115and135) are defined by a same patterning operation and are formed concurrently. In some embodiments, the semiconductor layer114covers an entirety of the gate dielectric layer115, and the gate dielectric layer115is overlapped by an entirety of the semiconductor layer114. In some embodiments, the semiconductor layer134covers an entirety of the gate dielectric layer135, and the gate dielectric layer135is overlapped by an entirety of the semiconductor layer134.

The gate structure113may laterally extend farther than the semiconductor layer114on one side of the gate structure113as shown inFIG.2. In some embodiments, a portion of the gate structure113is exposed by the semiconductor layer114from a top view perspective for a purpose of electrical connection (further details are provided in the following description). In some embodiments, the semiconductor layer114overlaps an entirety of the gate structure123of the second transistor12. In some embodiments, a sidewall123S of the gate structure123is aligned with a sidewall114S of the semiconductor layer114, wherein the sidewall123S of the gate structure123is separated apart from and faces the gate structure133. The source/drain structure122may laterally extend farther than the semiconductor layer114toward the third transistor13as shown inFIG.2. In some embodiments, a protruding portion of the source/drain structure122is outside a coverage area of the semiconductor layer114from a top view perspective. In some embodiments, the protruding portion of the source/drain structure122vertically overlaps the gate structure133of the third transistor13. In some embodiments, the semiconductor layer114is overlapped by an entirety of the source/drain structures111,112, and/or121. In some embodiments, a sidewall111S of the source/drain structure111is aligned with a sidewall123S of the semiconductor layer114, wherein the sidewall111S of the source/drain structure111faces away from the transistor12.

Arrangements and detailed structures of the third transistor13and the fourth transistor14may be similar to those of the first transistor11and second transistor12, and repeated description is omitted herein. In some embodiments, the third transistor13and the fourth transistor14are considered as repetitions of the first transistor11and the second transistor12. In some embodiments, the gate structure133of the third transistor13is similar to the gate structure113of the first transistor11, and a protruding portion of the gate structure133laterally extends farther than the semiconductor layer134toward the second transistor12. Therefore, the protruding portion of the source/drain structure122vertically overlaps the protruding portion of the gate structure133of the third transistor13.

In order to realize the unit cell as described above and shown inFIG.1, the semiconductor structure200may further include a conductive via15to electrically connect a source/drain structure of a transistor to a gate structure of an adjacent transistor. In some embodiments, the conductive via15is disposed at a same elevation as the semiconductor layers114and134and the gate dielectric layers115and135. In some embodiments, the conductive via15is disposed between the protruding portion of the source/drain structure122and the protruding portion of the gate structure133. In some embodiments, the source/drain structure122of the second transistor12is electrically connected to the gate structure133of the third transistor13through the conductive via15.

The second transistor12and the third transistor13together are defined as a unit cell102of a memory array. The transistor T1inFIG.1may correspond the second transistor12inFIG.2, wherein the source/drain structure122of the second transistor12corresponds to the terminal Q2of the transistor T1. Similarly, in some embodiments, the transistor T2inFIG.1corresponds to the third transistor13inFIG.2, wherein the gate structure133of the third transistor13corresponds to the gate of the transistor T2. It should be noted that the semiconductor structure200can be repeatedly arranged to form a memory array in the interconnection structure. In some embodiments, the first transistor11is one of two transistors of a unit cell101disposed in a same row as the unit cell102and placed previous to the unit cell102. In some embodiments, the fourth transistor14is one of two transistors of a unit cell103disposed in the same row as the unit cell102and placed after the unit cell102. Repeated arrangement of the semiconductor structure200can be applied, and the memory array100as shown inFIG.1can be realized by proper electrical connections through the metal lines of the interconnection structure. In some embodiments, the third transistor13is configured to store bit information of unit cell102. In some embodiments, the second transistor12is configured to access the bit information stored in the third transistor13through a read or write operation.

FIG.3is a schematic cross-sectional diagram of the semiconductor structure200applied in an interconnection structure90over a logic device80in accordance with some embodiments of the present disclosure. In some embodiments, the logic device80is disposed in a substrate layer81and the interconnection structure90is disposed over the logic device80. In some embodiments, the logic device80includes a plurality of transistors801. In some embodiments, the substrate layer81includes a bulk substrate811, and an insulating layer812formed on the bulk substrate811and covering the transistors801. In some embodiments, the insulating layer812is a multi-layered structure. In some embodiments, the logic device80further includes a plurality of contacts802electrically connected to the plurality of transistors801. The plurality of contacts802may provide electrical connection between source/drain regions and a metal line layer M0disposed over the insulating layer812. In some embodiments, the contacts802are electrically connected to corresponding metal lines803in the metal line layer M0. In some embodiments, the metal line layer M0is a first metal line layer above the contacts802. In some embodiments, the metal line layer M0is a first metal line of the interconnection structure90over the substrate layer81. The interconnection structure90may include multiple metal line layers M0, M1, M2, . . . , Mn, Mn+1, Mn+2, . . . , and so forth, wherein n is a positive integer greater than 2. In some embodiments, one or multiple semiconductor structures200are disposed between the metal line layers Mn and Mn+1, wherein n is between 3 and 6. In some embodiments, the semiconductor structures200are disposed between the metal line layers M3and M4. In some embodiments, the semiconductor structure(s)200vertically overlap(s) at least one transistor801of the logic device80. In some embodiments, the transistors of the semiconductor structure(s)200are coupled to the metal line layers Mn, Mn+1 and Mn+2 in order to achieve electrical connections shown inFIG.1, and the memory array100can be therefore realized. The interconnection structure90may further include a plurality of metal via layers arranged alternately between the metal line layers for electrical connection between the metal line layers. In some embodiments, each metal line layer is formed of metal lines and intermetal dielectric (IMD) surrounding the metal lines. In some embodiments, each metal via layer is formed of metal vias and IMD surrounding the vias.

In order to further illustrate concepts of the present disclosure, various embodiments are provided below. For a purpose of clarity and simplicity, reference numbers of elements with same or similar functions are repeated in different embodiments. However, such usage is not intended to limit the present disclosure to specific embodiments or specific elements. In addition, conditions or parameters illustrated in different embodiments can be combined or modified to have different combinations of embodiments as long as the parameters or conditions used are not conflicted.

FIGS.4and5are schematic diagrams of a semiconductor structure300from different angles in accordance with some embodiments of the present disclosure. As described above, in order to realize the memory array ofFIG.1, proper electrical connections between the transistors through the metal lines of the interconnection structure are required. The semiconductor structure200can be repeatedly arranged to form a memory array10. In some embodiments, the semiconductor structures200are arranged into two rows as shown inFIGS.4and5, and each row includes two of the semiconductor structures200. In such embodiments, each row includes three unit cells (as shown areas enclosed in dashed lines), and the memory array10includes six unit cells.FIGS.4and5are shown for a purpose of illustration only, and are not intended to limit the present disclosure. In some embodiments,FIGS.4and5indicate only a portion of the semiconductor structure300. In other embodiments, the memory array10includes more or fewer rows of transistors and/or more or fewer transistors per row. For a purpose of illustration, only transistors11,12,13and14labelled inFIGS.4and5and related electrical connections are described in detail in the following specification. Other transistors and related electrical connections can be equivalent to the transistors11,12,13and14, and repeated description is omitted herein.

Please refer toFIGS.4and5. In some embodiments, the semiconductor structure300includes the memory array10and metal line layers20,30and40of the interconnection structure90. In some embodiments, the metal line layers20,30and40are arranged over one another. In some embodiments, the memory array10is disposed between the metal line layers20and30. Each of the metal line layers20,30and40may include multiple metal lines. The interconnection structure90may further include multiple metal via layers70alternately arranged between the multiple metal line layers (e.g.,20,30and40) to electrically connect the metal lines in different metal line layers. In some embodiments, the multiple metal via layers70at least include a metal via layer70A, a metal via layer70B and a metal via layer70C.

In some embodiments, a gate structure123of the second transistor12and a gate structure143of the fourth transistor14are disposed over and electrically connected to a metal line21in the metal line layer20. In some embodiments, the metal line21elongates or extends along an arrangement direction of the transistors11,12,13and14. In some embodiments, the arrangement direction defines a first direction. In some embodiments, the metal line21vertically overlaps gate structures of all the transistors in a same row of the memory array10. In some embodiments, the metal line21functions as a write word line (e.g., the write word line WWL1ofFIG.1). In some embodiments, the gate structure123of the second transistor12and the gate structure143of the fourth transistor14are electrically connected to the metal line21through respective metal vias71of the metal via layer70A disposed between the memory array10and the metal line layer20.

In some embodiments, the source/drain structure121is electrically connected to a metal line33ain the metal line layer30. In some embodiments, the source/drain structure121is the source structure of the second transistor12and the metal line33afunctions as a write bit line (e.g., the write bit line WBLtofFIG.1). In some embodiments, the source/drain structure131is electrically connected to a metal line31bin the metal line layer30. In some embodiments, the source/drain structure131is the source structure of the third transistor13, and the metal line31bfunctions as a read bit line (e.g., the read bit line RBL1ofFIG.1). In some embodiments, the metal line33aand the metal line31bare substantially parallel. In some embodiments, the metal line33aand the metal line31belongates or extend along a second direction, which is substantially perpendicular to the first direction. In some embodiments, each of the source/drain structures of all the transistors of the memory array10is electrically connected to a corresponding metal line in the metal line layer30through a respective metal via72of a metal via layer70B between the memory array10and the metal line layer30.

Please refer toFIG.4. In some embodiments, the source/drain structure141is electrically connected to a metal line33bin the metal line layer30. In some embodiments, the source/drain structure141is the source structure of the fourth transistor14and the metal line33bfunctions as another write bit line (e.g., the write bit line WBL2ofFIG.1). In some embodiments, the metal line33belongates or extends along the second direction. In some embodiments, the first transistor11is at a periphery region of the memory array10, and the gate structure113is not connected to a metal line. In some embodiments, the first transistor11is a dummy transistor. In some embodiments, the first transistor11is formed concurrently with other transistors of the memory array10, but does not function when the memory array10is operating.

Please refer toFIG.5. As described above, the memory array10includes repeatedly arranged semiconductor structures200, and thus at least one of the first transistors11is not in the periphery region of the memory array10, and can function normally when the memory array10is operating. The first transistor11labelled inFIG.5is disposed adjacent to the fourth transistor14labelled inFIG.4. In some embodiments, the source/drain structure111is electrically connected to a metal line31ain the metal line layer30. In some embodiments, the source/drain structure111is the source structure of the first transistor11and the metal line31afunctions as another read bit line (e.g., the read bit line RBL2ofFIG.1). In some embodiments, the metal line31aelongates or extends along the second direction. In some embodiments, the fourth transistor14is in a periphery region of the memory array10, and the drain structure142is not connected to a metal line. In some embodiments the fourth transistor14is a dummy transistor. In some embodiments, the fourth transistor14is formed concurrently with other transistors of the memory array10, but does not function when the memory array10is operating.

The metal lines functioning as bit lines may all elongate or all extend along the second direction. In some embodiments, those metal lines, being the bit lines in a memory circuit, are electrically connected to source structures of different transistors in different rows of the same layer. For instance, as shown inFIG.4, a transistor11ais aligned with the first transistor11along the second direction in a different row of the same layer. In some embodiments, a source structure111aof the transistor11ais electrically coupled to the source structure111of the first transistor11through the metal line31a. For another instance, as shown inFIG.5, a transistor14ais aligned with the fourth transistor14along the second direction in a different row of the same layer. In some embodiments, a source structure141aof the transistor14ais electrically coupled to the source structure141of the fourth transistor14through the metal line33b. Although the first transistor11inFIG.4and the fourth transistor14inFIG.5are dummy transistors, the metal line31alabelled inFIG.4and the metal line33blabelled inFIG.5can show how another bit line is electrically connected to source structures of different transistors in different rows of the same layer.

FIG.6is a schematic diagram specifically showing electrical connections between the metal line layer30and a metal line42in the metal line layer40of the semiconductor structure300in accordance with some embodiments of the present disclosure. In order to couple drain structures of different transistors in a same row (i.e., a front row10F shown inFIG.6), the drain structures112,132in the row are electrically connected to a metal line42in the metal line layer40through metal lines32aand32bin the metal line layer30and multiple metal vias72and73. The metal lines32aand32bcan be relatively short lines compared to adjacent metal lines31a,33a,31band33bfrom a top view perspective, and can be referred to as metal segments32aand32bin the following description. In some embodiments, the metal line layer40is disposed above the metal line layer30. In some embodiments, the metal vias73of the metal via layer70C are disposed between the metal line layers30and40. In some embodiments, the metal line layer40and the metal line layer20are arranged on opposite sides of the metal line layer30. In some embodiments, the metal line42elongates or extends along the first direction. The drain structure112of the first transistor11and the drain structure132of the third transistor13may be electrically connected to the metal line42in the metal line layer40. In some embodiments, the drain structure112of the first transistor11is electrically connected to the metal segment32ain the metal line layer20through a corresponding metal via72disposed between the metal line layer30and the memory array10. In some embodiments, the drain structure132of the third transistor13is electrically connected to the metal segment32bin the metal line layer30through a corresponding metal via72. In some embodiments, all of the drain structures112of the first transistor11and the drain structures132of the third transistor13in a same row are electrically coupled through the metal line42. The metal line42may be electrically connected to a metal line35ain the metal line layer30through a corresponding metal via73. The metal line35acan be disposed over a drain structure122of the second transistor12or a drain structure142of the fourth transistor14in the memory array10. In some embodiments, the metal line35ais disposed vertically over the drain structure142of the fourth transistor14. In some embodiments, the metal line35aelongates or extends along the second direction. In some embodiments, the metal line35avertically overlaps the conductive via15between the drain structure142of the fourth transistor14and the gate structure113of the adjacent first transistor11(not shown). In some embodiments, the metal line35aand/or the metal line42function(s) as a read word line (e.g., the read word line RWL1inFIG.1). Electrical signals (indicated by small arrows) from the drain structures112and132may be transmitted to the metal line42, and as the electrical signals together (indicated by a large arrow) transmitted to the metal line35a. In some embodiments, the metal line35ais electrically connected to a logic device disposed below the memory array10, and therefore the electrical signals are transmitted to the logic device.

FIG.7is a schematic diagram specifically showing electrical connections between the metal line layer30and a metal line44in the metal line layer40of the semiconductor structure300in accordance with some embodiments of the present disclosure. In some embodiments, the metal line44is substantially parallel to the metal line42in the metal line layer40. In some embodiments, the metal line44is electrically coupled to drain structures of different transistors arranged in another row (a back row10B shown inFIG.7) different from those coupled to the metal line42. It should be noted that the arrangement of the transistors in the back row10B is substantially the same as (or mirrored to) the arrangement of the transistors in the front row10F. Therefore, reference numbers of elements are repeated to indicate the elements in the back row10B aligned with corresponding elements in the front row10F of the memory array10.

Arrangements of and electrical connections between transistors, vias, metal lines in the metal line layer30, and the metal line44are similar to those as illustrated inFIG.6and the related description above. In some embodiments, the drain structures112and132of the first transistor and the third transistor in the back row10B are electrically connected to corresponding metal segments32cand32din the metal line layer30. In some embodiments, the metal segments32care aligned with the metal segments32aalong the second direction. In some embodiments, the metal segments32dare aligned with the metal segments32bin the second direction. The metal segments32cand32dmay be electrically connected to the metal line44through a corresponding via73, and the metal line44may be electrically connected to a metal line35bin the metal line layer30through another via73. In some embodiments, electrical signals from the drain structures112and132in the back row10B (indicated by small arrows inFIG.7) of the transistors are collectively transmitted (indicated by a large arrow inFIG.7) to the metal line35b. In some embodiments, the collective electrical signal is then transmitted to the logic device from the metal line35b. In some embodiments, the metal line35band/or the metal line44function(s) as a read word line (e.g., the read word line RWL2ofFIG.1). In some embodiments, the metal line35bis disposed vertically over the drain structures142of the fourth transistors14aligned with each other and placed in different rows. In some embodiments, the metal line35belongates or extends along the second direction. In some embodiments, the metal line35aelongates or extends along the second direction. In some embodiments, the metal line35avertically overlaps the conductive via15(not shown) between the drain structure142of the fourth transistor14and the gate structure113of the adjacent first transistor11in the back row10B. However, the disclosure is not limited thereto. In alternative embodiments, the metal line35bcan be disposed over the drain structures122aligned with each other and placed in different rows.

FIG.8is a schematic diagram of a semiconductor structure400in accordance with some embodiments of the present disclosure. The semiconductor structure400may be similar to the semiconductor structure300but includes a memory array10A disposed above the memory array10. The semiconductor structure400may further include metal line layers50and60, metal lines41and42, and metal vias74,75and76in different metal via layers70D,70E and70F of the interconnection structure90. In some embodiments, the semiconductor structure400is similar to two vertically stacked semiconductor structures300. In some embodiments, the memory array10A is similar to the memory array10. In some embodiments, arrangement of the metal line layer50is similar to that of the metal line layer30. In some embodiments, metal lines51a,51b,52ato52d,53a,53b,55aand55bin the metal line layer50are similar to the metal lines31a,31b,32ato32d,33a,33b,35aand35bin the metal line layer30. In some embodiments, metal lines41and43in the metal line layer40are similar to the metal lines21and22in the metal line layer20. Write word lines (e.g., the metal lines42and44) controlling the memory array10A can be integrated into the metal line layer40with the read word lines (e.g., the metal lines41and44) controlling the memory array10. In some embodiments, the metal lines41and43elongates or extend along the first direction. In some embodiments, the metal lines41and43are substantially parallel.

For a purpose of simplicity of manufacturing process and minimization of a peripheral area saved for electrical routing, metal lines34aand34bare disposed in the metal line layer30. The metal line41can be electrically connected to one of the metal lines34aand34b, and the metal line43can be electrically connected to another metal line34bor34a. Therefore, spaces in an area covered by the memory arrays10and10A can be utilized for routing to minimize a routing area. In some embodiments, the area covered by the memory arrays10and10A defines an array area, and areas vertically outside the array area define the peripheral area. In some embodiments, the peripheral area surrounds the array area. In some embodiments, the metal lines34aand34bare respectively disposed above drain structures of aligned fourth transistors14in different rows as shown inFIG.8. In some embodiments, the metal lines34aand34bare respectively disposed above drain structures of aligned second transistors12(not shown) in different rows. It should be noted that positions of the metal lines34a,34b,35aand35bare interchangeable depending on different applications. In some embodiments, the metal line41is electrically connected to the metal line34a, and the metal line43is electrically connected to the metal line34b.

In some embodiments, metal lines54aand54bsimilar to the metal lines34aand34bare disposed in the metal line layer50. In the semiconductor structure400, the metal lines54aand54bare dummy metal lines. A photomask used in formation of the metal line layer50may be the same as that used in formation of the metal line layer30, and thus a manufacturing cost can be reduced and dummy metal lines54aand54bmay be formed in the metal line layer50. In alternative embodiments, the metal lines54aand54bare absent from the metal line layer50.

The semiconductor structure400may further include metal vias74,75and76at different elevations for electrical connections between different metal line layers. In some embodiments, the metal vias74are disposed between and provide electrical connections between the metal line layer40and the memory array10A. In some embodiments, the metal vias74collectively are formed in the metal via layer70D disposed above the metal line layer40and below the memory array10A. In some embodiments, the metal vias75are disposed between and provide electrical connections between the metal line layer50and the memory array10A. In some embodiments, the metal vias75are formed in the metal via layer70E disposed below the metal line layer50and above the memory array10A. In some embodiments, the metal vias76are disposed between and provide electrical connections between the metal line layer60and the metal line layer50. In some embodiments, the metal vias76are formed in the metal via layer70F disposed above the metal line layer50and below the metal line layer60. In some embodiments, the metal line layer60includes a metal line62and a metal line64similar to the metal line42and the metal line44, and repeated description is omitted herein. In some embodiments, the metal line layer60is a topmost layer of the interconnection structure90.

FIG.8is an exemplary embodiment showing vertically stacked memory arrays. According to the concept and structures illustrated above, more than two layers of memory arrays can be provided in a semiconductor structure. Multiple layers of memory arrays can be vertically and repeatedly stacked according to the arrangement as shown inFIG.8and above illustration. A number of layers of memory arrays can be adjusted according to different applications and is not limited herein.

FIG.9is a schematic cross-sectional diagram illustrating the semiconductor structure400disposed over a logic device80in accordance with some embodiments of the present disclosure. The structure ofFIG.9can be similar to the structure ofFIG.3except that the structure ofFIG.9includes one more array (i.e.,10A) in the interconnection structure90. In some embodiments, the transistors of different memory arrays in different elevations are vertically aligned. In some embodiments, the interconnection structure90includes a plurality of dielectric layers91surrounding metal lines, vias and transistors. Repetition of other elements is omitted for a purpose of brevity.

FIG.10is a schematic diagram illustrating a semiconductor structure500in accordance with some embodiments of the present disclosure. As described above, some of metal lines of a semiconductor structure may extend toward a peripheral area for electrical routing to a logic device disposed under a memory array.FIG.10illustrates arrangement of the metal lines in a peripheral area A2in accordance with some embodiments of the present disclosure. Word lines and bit lines of the semiconductor structure500may all extend toward the peripheral area A2, disposed on a first side of an array area A1. In some embodiments, an area vertically covered by memory arrays (e.g.,10and10A) defines the array area A1, and an area vertically outside the array area A1defines the peripheral area A2. In some embodiments, the peripheral area A2is on a side of the memory arrays10and10A along the second direction as shown inFIG.10. In some embodiments, the metal lines (e.g.,21,22,41to44,62and64) extending along the first direction are disposed within the array area A1. In some embodiments, each of the metal lines21,22,41to44,62and64is disposed within the array area A1. Different metal lines (e.g.,31a,31b,33a,33b,34a,34b,35aand35b) may have same or different lengths measured along the second direction. In some embodiments, the lengths of the different metal lines are adjusted according to different applications. For instance, as shown inFIG.10, a length of the metal line31ais greater than a length of the metal line34a, and the length of the metal line34ais greater than a length of the metal line33a. In some embodiments, the length of the metal line31ais substantially equal to a length of the metal line31b. In some embodiments, the length of the metal line33ais substantially equal to a length of the metal line33b. In some embodiments, arrangement of metal lines51a,51b,53a,53band54acorresponds to arrangement of the metal lines31a,31b,33a,33band34a. Arrangement of other metal lines can be adjusted and repeated description is omitted herein.

FIG.10shows all metal lines extending in the second direction toward one side of the array area A1. However, the present invention is not limited thereto.FIG.11is a schematic diagram illustrating a semiconductor structure600in accordance with some embodiments of the present disclosure. The metal lines extending along the second direction may extend toward two opposite sides of the array area A1. In some embodiments as shown inFIG.11, routing of the metal line51ais arranged in a peripheral area A3opposite to the peripheral area A2with respect to the array area A1. Since electrical routings to different metal lines are distributed to the different peripheral areas A2and A3, an area size of each of the peripheral area A3or A2inFIG.11may be smaller than an area size of the peripheral area A2inFIG.10.FIGS.10and11are exemplary arrangements of routings according to different embodiments. Arrangement of the routings can be adjusted according to different applications.

According to the structures described above, the present disclosure also provides a manufacturing method of a semiconductor structure.FIG.12is a flow diagram of a method700for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. The method700includes a number of operations (701,702and703) and the description and illustration are not deemed as a limitation to the sequence of the operations. A substrate having a plurality of control transistors is provided in the operation701. An interconnection structure is formed over the substrate in the operation702. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. A memory unit cell including a first transistor and a second transistor disposed between the first metal line layer and the second metal line layer in the operation703. The first transistor includes a gate structure and a first source/drain structure, wherein the gate structure of the first transistor is electrically connected to the first metal line layer. The second transistor includes a source/drain structure electrically connected to the second metal line layer through the third metal line layer. In some embodiments, a gate structure of the second transistor is electrically connected to a source/drain structure of the first transistor through a conductive via disposed therebetween. In some embodiments, at least one of the first transistor and the second transistor vertically overlaps with a plurality of control transistors formed in a substrate. It should be noted that the operations of the method700may be rearranged or otherwise modified within the scope of the various aspects. Additional processes may be provided before, during, and after the method700, and some other processes may be only briefly described herein. Thus, other implementations are possible within the scope of the various aspects described herein.

The present disclosure provides a semiconductor structure including a memory array disposed in an interconnection structure and positioned vertically over a logic circuit or a logic device. The memory array includes a plurality of thin-film transistors at a same elevation, and thus the entire memory array can be disposed in a single layer between two metal line layers of the interconnection structure. In some embodiments, the memory array can include multiple layers alternately arranged between metal line layers of the interconnection structure. The memory array and the logic circuit are vertically arranged and thus an area size of a final product can be reduced. In order to further limit a peripheral area for electrical routings, an intra-array conductive via is disposed between a source/drain structure and a gate structure of two adjacent transistors. Generally, a space vertically over or below a source/drain/gate structure is utilized for a corresponding metal line for electrical connection to the source/drain/gate structure. Due to the presence of the intra-array conductive via, a space over the drain structure connecting to the intra-array conductive via is made available for word line routings or other metal line routings. Routings of word lines at a higher elevation can be arranged in an array area; therefore, a peripheral area for routings can be reduced, and manufacturing and material costs can also be reduced. In addition, the word lines and bit lines of the present invention extend out of the array area along a same direction, and thus the peripheral area for routings can be arranged at only one side or at two opposite sides of the array area. An overall area size of the final product can therefore be minimized.

In accordance with some embodiments of the disclosure, a semiconductor structure is provided. The structure includes an interconnection structure, a first transistor, and a second transistor. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. The first transistor includes a gate structure. The second transistor is disposed adjacent to the first transistor, and includes a source/drain structure. The gate structure of the first transistor is disposed over and electrically connected to the first metal line layer, and the source/drain structure of the second transistor is arranged below and electrically connected to the second metal line layer through the third metal line layer.

In accordance with some embodiments of the disclosure, a semiconductor structure is provided. The structure includes a first thin-film transistor (TFT), a second TFT, and a third TFT. The first TFT is disposed between two metal line layers of an interconnection structure. The second TFT is disposed adjacent to the first TFT, and the first TFT and the second TFT have a semiconductor layer in common. The third TFT is disposed adjacent to the second TFT, wherein a source/drain structure of the second TFT is electrically connected to a gate structure of the third TFT through a conductive via at a same elevation as the semiconductor layer of the first TFT and the second TFT.

In accordance with some embodiments of the disclosure, a method for manufacturing a semiconductor structure is provided. The method may include several operations. A substrate having a plurality of transistors is provided. An interconnection structure is formed over the substrate. The interconnection structure includes a first metal line layer, a second metal line layer and a third metal line layer arranged over one another. A first transistor is disposed between the first metal line layer and the second metal line layer. The first transistor includes a gate structure and a source/drain structure, wherein the gate structure of the first transistor is electrically connected to the first metal line layer, and the source/drain structure is arranged electrically connected to the second metal line layer through the third metal line layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.