Patent ID: 12235556

DETAIL DESCRIPTION OF EMBODIMENTS

In order to illustrate the objects, technical schemes and advantages of the embodiments of the present disclosure more clearly, the technical schemes of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It is noted that in the drawings, the thickness of the layers, films, panels, regions, etc. have been enlarged for clarity. Exemplary embodiments are described in the present disclosure with reference to the cross-sectional views of the schematic diagrams of the idealized embodiments. In this way, deviations from the shape of the figures as a result of, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described in the present disclosure should not be construed as limited to the particular shapes of regions as illustrated in present disclosure, and are to include deviations in shapes that result, for example, from manufacturing. For example, regions illustrated or described as flat may typically have rough and/or nonlinear features; the sharp corners illustrated may be rounded, etc. Thus, the regions illustrated in the figures are schematic in nature and their sizes and shapes are not intended to illustrate the precise shape of a region, not to reflect a true scale, and are merely intended to illustrate the present disclosure. The same or similar reference numerals are used throughout the drawings to refer to the same or similar elements or elements having the same or similar functions. For a clear and concise description of the embodiments of the present disclosure, a detailed description of known functions and known components is omitted from the present disclosure.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” and the like, as used in the description and the claims, are not intended to indicate any order, quantity, or importance, and rather to distinguish one component from other components. The term “including” or “including”, or the like, means that the element or item preceding the word includes the element or item listed after the word and its equivalent, and does not exclude other elements or items. The terms “connected” or “coupled” and the like are not restricted to physical or mechanical connections, and may include electrical connections, whether direct or indirect. The terms “inner”, “outer”, “upper”, “lower”, and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, it may be directly on or connected to the another element or layer, or intervening elements or layers may be present. When an element or layer is referred to as being “disposed on” a side of another element or layer, the element or layer may be directly on the side of the another element or layer, or may be directly connected to the another element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, no intervening elements or layers are present. The term “and/or” encompasses any and all combinations of one or more of the associated listed items.

The liquid crystal display devices in the existing technology include advanced super dimension switch (ADS) type liquid crystal displays, high aperture-advanced super dimension switch (HADS) type liquid crystal displays, in-plane switch (IPS) type liquid crystal displays, and vertical alignment (VA) type liquid crystal displays.FIG.1shows a display substrate of an advanced super dimension switch type liquid crystal display,FIG.2shows a display substrate of a high aperture-advanced super dimension switch type liquid crystal display,FIG.3shows a display substrate of an in-plane switch type liquid crystal display, andFIG.4shows a vertical alignment type liquid crystal display. As can be seen fromFIGS.1and4, only an inorganic insulating layer (PVX) is provided between the data line (SD) and the electrode (ITO) in a layer above the data line, resulting in a small distance between the data line (SD) and the electrode (ITO), a large coupling capacitance, and a large load on the data line. As can be seen fromFIGS.2and3, not only the inorganic insulating layer (PVX) and also an organic insulating layer (Org) is added between the data line (SD) and the electrode (ITO) in a layer above the data line, such that the distance between the data line (SD) and the electrode (ITO) in the layer above the data line is increased by the organic insulating layer (Org), thus the coupling capacitance between the data line (SD) and the electrode (ITO) in the layer above the data line is reduced and the load on the data line (SD) is decreased, however, the process for manufacturing the organic insulating layer (Org) is added, thereby increasing the process complexity.

In order to improve the above technical problems in the existing technology, an embodiment of the present disclosure provides a display substrate, as shown inFIGS.5to22, the display substrate includes:a base substrate101, where, optionally, the base substrate101is a rigid substrate made of glass or the like, or a flexible substrate made of polyimide or the like;a plurality of data lines (SD)102, which are positioned on the base substrate101, where, optionally, the data lines102are made of a material including a metal material, such as a single-layer or multi-layer structure made of molybdenum, aluminum, titanium, copper, alloy, and the like, and exemplarily, the data lines102are each of a stacked structure of titanium metal layer/aluminum metal layer/titanium metal layer;a first insulating layer103, which is positioned on a side of a layer where the data lines102are positioned away from the base substrate101, where, optionally, the first insulating layer103is a gate insulating layer (GI), and the first insulating layer103may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride;a plurality of gate lines (G)104, which are positioned on a side of the first insulating layer103away from the layer where the plurality of data lines102are positioned, and an extension direction of each of the plurality of gate lines104and an extension direction of each of the plurality of data lines102are intersected, optionally, the gate lines104are made of a material including a metal material, such as a single-layer or multi-layer structure made of molybdenum, aluminum, titanium, copper, an alloy, and the like, and exemplarily, the gate lines104are each of a stacked structure made of titanium metal layer/aluminum metal layer/titanium metal layer;a second insulating layer105, which is positioned on a side of a layer where the plurality of gate lines104are positioned away from the first insulating layer103; where, optionally, the first insulating layer103is an inorganic insulating layer (PVX), and the second insulating layer105is made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride;a first electrode106, which is positioned on a side of the second insulating layer105away from a layer where the gate lines104are positioned, an orthographic projection of the first electrode106on the base substrate101is positioned in at least an region surrounded by orthographic projections of respective data lines102on the base substrate101and orthographic projections of respective gate lines104on the base substrate101; optionally, the first electrode106may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

In the display substrate according to the embodiment of the present disclosure, by sequentially arranging a layer of data lines102, a first insulating layer103, a layer of gate lines104, a second insulating layer105and a layer of the first electrode106on the base substrate101, two insulating layers, i.e., the first insulating layer103and the second insulating layer105, are simultaneously present between the layer where the data lines102are positioned and the layer where the first electrode106is positioned that is farther away from the base substrate101. By doing so, the distance between the layer where the data lines102are positioned and the layer where the first electrode106is positioned is larger, the coupling capacitance between the data line102and the first electrode106can be reduced, the load on the data line102caused by the coupling capacitance is reduced, the pixel charging rate is favorably improved, and the temperature of a driving chip (IC) is reduced. Also, since the present disclosure reduces the coupling capacitance between the data line102and the first electrode106utilizing the first insulating layer103and the second insulating layer105in the related technology, it is not necessary to add an organic insulating layer to reduce the coupling capacitance between the data line102and the first electrode106, and based on this, the process complexity would not be increased.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, the thickness of the first insulating layer103is greater than or equal to 3500 Å and less than or equal to 4500 Å, the thickness of the second insulating layer105is greater than or equal to 2000 Å and less than or equal to 7000 Å. Optionally, the thickness of the first insulating layer103is 4500 Å and the thickness of the second insulating layer105is 7000 Å, in which case the thickness of the insulating layer between the data line102and the first electrode106may be 11500 Å, greatly reducing the load on the data lines102, and improving the pixel charging rate.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.5,7,8and10, an orthographic projection of a portion of each of at least a part of the data lines102on the base substrate101is positioned within the orthographic projection of the first electrode106on the base substrate101. The first electrode106includes a plurality of slits S, and a minimum distance d1from the slit S to the data line102in the extension direction X of the gate line104is greater than 1.5 μm, in other words, the first electrode106may include an electrode strip106′ between two slits S closest to the data line102, and an orthographic projection of the electrode strip106′ on the base substrate101exceeds by at least 1.5 μm, for example, 2.2 μm, relative to the orthographic projection of the data line102on the base substrate101. With this arrangement, the electrode strip106′ can cover the data line102even after process fluctuation occurs. In addition, in a case where the orthographic projection of the electrode strip106′ on the base substrate101exceeds by 2.2 μm relative to the orthographic projection of the data line102on the base substrate101, the optimal luminous efficiency design effect of the first electrode106can still be achieved.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.5to7,9,12,13,16,17,20,21,30,33,34,36,38,39,41to43,45to47,49to51, and53to55, the display substrate may further include a transistor107, where a gate71of the transistor107is disposed in the same layer and made of the same material as the data line102, a first electrode72and a second electrode73of the transistor107are disposed in the same layer and made of the same material as the gate line104, so that the transistor107is a bottom gate transistor, and light is shielded by the gate71of the transistor107, thereby preventing the light from irradiating the channel of the transistor107to affect the stability of the transistor107. Optionally, the gate71of the transistor107is electrically connected to a gate line104, the first electrode72of the transistor107is electrically connected to a data line102, and the second electrode73of the transistor107is electrically connected to a pixel electrode. In some embodiments, an active layer74of the transistor107may be made of a material such as amorphous silicon, polysilicon, oxide, or the like; the first electrode72of the transistor107may be a source and the second electrode73of the transistor107is a drain, or the first electrode72of the transistor107is a drain and the second electrode73is a source; the transistor107may be a P-type transistor or an N-type transistor, which is not limited herein.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.5to7,14,18,22,23,24,30,35,36,40,41,44,45,48,49,52,53, and56, the display substrate may further include a first transfer electrode108, which is disposed in the same layer and made of the same material as the first electrode106; the first transfer electrode108is electrically connected to the gate71of the transistor107through a first via V11penetrating through the first insulating layer103and the second insulating layer105, and is electrically connected to the gate line104through a second via V12penetrating through the second insulating layer105, that is, electrical connection between the gate line104and the gate71of the transistor107is achieved utilizing the first transfer electrode108. In this case, the fabrication of the first transfer electrode108can be completed at the same time of fabricating the first electrode106, thereby avoiding an additional process for fabricating the first transfer electrode108. Furthermore, a second via V12penetrating through the second insulating layer105and used for electrically connecting the first transfer electrode108and the gate line104and a first via Vu penetrating through the first insulating layer103and the second insulating layer105and used for electrically connecting the first transfer electrode108and the gate71of the transistor107can be simultaneously formed in one single patterning process, thereby avoiding an additional process of patterning the first insulating layer103. It should be understood that in some embodiments, as shown inFIG.27, the gate line104may alternatively be electrically connected to the gate71of the transistor107through a seventh via V1′ penetrating through the first insulating layer103.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and24, an orthographic projection of the first via Vu on the base substrate101is positioned within the orthographic projection of the gate71of the transistor107on the base substrate101, an aperture of the first via V11in a direction Z away from the base substrate101is gradually increased, and the first via V11includes a first port close to the base substrate101. In order to ensure a small lap resistance between the first transfer electrode108and the gate71of the transistor107and a good topography of the first via V11, a length B of the first port in an extension direction X of the gate line104may be set to be greater than or equal to 3 μm, and a width F′ of the first port in an extension direction Y of the data line102is set to be greater than or equal to 6 μm. Optionally, the length B is 5.75 μm, and the width F′ is 6 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and24, an orthographic projection of the second via V12on the base substrate101is positioned within the orthographic projection of the gate line104on the base substrate101, an aperture of the second via V12in a direction Z away from the base substrate101is gradually increased, and the second via V12includes a second port close to the base substrate101. In order to ensure a small lap resistance between the first transfer electrode108and the gate line104and a good topography of the second via V12, a length C of the second port in the extension direction X of the gate line104may be set to be greater than or equal to 3 μm, and a width F of the second port in the extension direction Y of the data line102is set to be greater than or equal to 8 μm. Optionally, the length C is 6.25 μm, and the width F is 8 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and24, the gate line104includes a protrusion41disposed side by side with the first electrode72of the transistor107, the orthographic projection of the first via V11on the base substrate101is not overlapped with an orthographic projection of the protrusion41on the base substrate101, and the orthographic projection of the second via V12on the base substrate101is positioned within the orthographic projection of the protrusion41on the base substrate101. As can be seen fromFIG.23, an area of the protrusion41is larger, which facilitates the lap joint of the protrusion41with the first transfer electrode108through the second via V12. Meanwhile, a line width of the gate line104is increased at only the protrusion41, so that an overall line width of the gate line104is avoided to be larger, and the shielding of the backlight by the gate line104is reduced, thus the transmittance is improved.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and24, to simplify the design of the via, the first via V11and the second via V12may be integrally provided as a first through hole V1. Optionally, an orthographic projection of the first through hole V1on the base substrate101is positioned within the orthographic projection of the first transfer electrode108on the base substrate101, and a one-side excess distance A/D/E/G of the orthographic projection of the first transfer electrode108on the base substrate101relative to the orthographic projection of the first through hole V1on the base substrate101in the extension direction Y of the data line102and/or the extension direction X of the gate line104is greater than or equal to 3 μm, for example, the one-side excess distances A, D, E, G are 5.55 μm, 5.75 μm, 5.5 μm, respectively. In a case where the one-side excess distance A/D/E/G of the orthographic projection of the first transfer electrode108on the base substrate101relative to the orthographic projection of the first through hole V1on the base substrate101in the extension direction Y of the data line102and/or the extension direction X of the gate line104is greater than or equal to 3 μm, even if process fluctuation occurs, the first transfer electrode108can still cover the first through hole V1well, which reduces the risk of corrosion of the protrusion41and the gate71caused by moisture contact through the first through hole V1.

In some embodiments, as shown inFIG.23, in the display substrate according to the embodiment of the present disclosure, an overlapping region OL is formed between the orthographic projection of the protrusion41on the base substrate101and the orthographic projection of the gate71of the transistor107on the base substrate101, and the overlapping region OL is relatively flat to hold a spacer (PS), so that the supporting effect for the spacer (PS) is improved, and the spacer (PS) can be prevented from sliding due to an uneven supporting surface to cause light leakage and the like phenomena. Of course, in some embodiments, the spacer (PS) may alternatively be disposed in other relatively flat regions, and in this case, as shown inFIG.5, the orthographic projection of the protrusion41on the base substrate101and the orthographic projection of the gate71of the transistor107on the base substrate101may not be overlapped.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, a minimum distance u between the first electrode72of the transistor107and the protrusion41may be greater than or equal to 5 μm, for example, 9.55 μm. Since the first electrode72of the transistor107and the protrusion41are disposed in the same layer and made of the same material, in a case where the minimum distance u between the first electrode72of the transistor107and the protrusion41is greater than or equal to 5 μm, a short circuit caused by process fluctuation, residual conductive foreign matters (particle), etc. can be avoided.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, the gate line104may further include a wiring portion42integrally provided with the protrusion41, and a line width k of the wiring portion42in the extension direction Y of the data line102is greater than or equal to 5 μm, for example, 8 μm, so as to prevent the gate line104from breaking.

In some embodiments, as shown inFIG.23, in the display substrate according to the embodiment of the present disclosure, the wiring portion42and the protrusion41form an accommodating groove AG, and the first electrode72of the transistor107is positioned in the accommodating groove AG, so as to prevent the transistor107from occupying too much pixel area, and to improve the pixel aperture ratio, and meanwhile to effectively prevent the first electrode72of the transistor107from being shorted with the gate line104disposed in the same layer and made of the same material. Optionally, an opening of the accommodating groove AG faces the pixel electrode controlled, by means of the transistor107, by the gate line104to which the accommodating groove AG belongs, so that the second electrode73of the transistor107is electrically connected to the pixel electrode at an opening side of the accommodating groove AG.

In some embodiments, in the above display substrate according to the embodiment of the present disclosure, as shown inFIG.23, the orthographic projection of the gate71of the transistor107on the base substrate101and the orthographic projection of the accommodating groove AG on the base substrate101are partially overlapped, so as to facilitate the overlapping of the orthographic projection of the gate71of the transistor107on the base substrate101and the orthographic projection of the first electrode72on the base substrate101in the accommodating groove AG, thus a channel region in a U-shaped structure of the first electrode72forms a conductive channel under the driving of the electric fields of the gate71and the first electrode72.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, the first electrode72of the transistor107includes a first subsection721extending along the extension direction X of the gate line104, an orthographic projection of the first subsection721on the base substrate101is partially overlapped with the orthographic projection of the gate71of the transistor107on the base substrate101, and is not overlapped with the orthographic projection of the data line102on the base substrate101. In order to prevent the first subsection721from being shorted with the wiring portion42that is disposed in the same layer and made of the same material, a distance j between the first subsection721and the wiring portion42may be set to be greater than or equal to 5 μm, for example, 9.25 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, in order to prevent the first subsection721from breaking, as shown inFIG.23, the width i of the first subsection721in the extension direction Y of the data line102may be set to be greater than or equal to 3 μm, for example, 6 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, a minimum distance t between the orthographic projection of the first electrode72of the transistor107on the base substrate101and the orthographic projection of the first transfer electrode108on the base substrate101is greater than or equal to 3 μm, for example, 6.55 μm, so as to prevent the first transfer electrode108from being overlapped with the channel region in the U-shaped structure of the first electrode72due to factors such as process fluctuations to influence the switching characteristics of the transistor107.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.5to7,14,18,22,23,25,30,35,36,40,41,44,45,48,49,52,53, and56, the display substrate may further include a second transfer electrode109, which is disposed in the same layer and made of the same material as the first electrode106; the second transfer electrode109is electrically connected to the data line102through a third via V21penetrating through the first insulating layer103and the second insulating layer105, and is electrically connected to the first electrode72of the transistor107through a fourth via V22penetrating through the second insulating layer105, i.e., the electrical connection of the data line102and the first electrode72of the transistor107is achieved utilizing the second transfer electrode109. In this case, the fabrication of the second transfer electrode109can be completed at the same time of fabricating the first electrode106, thereby avoiding an additional process for fabricating the second transfer electrode109. A via penetrating through the second insulating layer105and used for electrically connecting the second transfer electrode109and the first electrode72of the transistor107and a via penetrating through the first insulating layer103and the second insulating layer105and used for electrically connecting the second transfer electrode109and the data line102can be simultaneously formed by one patterning process, thereby avoiding an additional process of patterning the first insulating layer103. It should be understood that in some embodiments, as shown inFIG.28, the first electrode72of the transistor107may alternatively be electrically connected to the data line102through an eighth via V2′ penetrating through the first insulating layer103.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and25, the data line102includes a widened portion21. In order to reduce the lap resistance between the data line102and the second transfer electrode109and to ensure a good topography of the third via V21, an orthographic projection of the third via V21on the base substrate101may be positioned within an orthographic projection of the widened portion21on the base substrate101. An aperture of the third via V21in a direction Z away from the base substrate101is gradually increased. The third via V21includes a third port close to the base substrate101, a length b′ of the third port in the extension direction X of the gate line104is greater than or equal to 6 μm, and a width e of the third port in the extension direction Y of the data line102is greater than or equal to 3 μm. Optionally, the length b′ is 8 μm, and the width e is 5.75 μm. As can be seen fromFIG.23, an area of the widened portion21is relatively larger, which facilitates the lap joint of the widened portion21with the second transfer electrode109through the third via V21. Meanwhile, a line width of the data line102is increased at only the widened portion21, so that an overall line width of the data line102is avoided to be larger, and the shielding of the backlight by the data line102is reduced, thus the transmittance is improved.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and25, the first electrode72of the transistor107includes a second subsection722, an orthographic projection of the second subsection722on the base substrate101is positioned within the orthographic projection of the widened portion21on the base substrate101. In order to reduce the lap resistance between the first electrode72and the second transfer electrode109and to ensure a good topography of the fourth via V22, an orthographic projection of the fourth via V22on the base substrate101is positioned within the orthographic projection of the second subsection722on the base substrate101. An aperture of the fourth via V22in a direction Z away from the base substrate101is gradually increased. The fourth via V22includes a fourth port close to the base substrate101, a length b of the fourth port in the extension direction X of the data line104is greater than or equal to 8 μm, and a width f of the fourth port in the extension direction Y of the data line102is greater than or equal to 3 μm. Optionally, the length b is 8 μm, and the width f is 6.25 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, in order to simplify the design of the via, as shown inFIG.23, the third via V21and the fourth via V22may be integrally provided as a second through hole V2. Optionally, an orthographic projection of the second through hole V2on the base substrate101is positioned within the orthographic projection of the second transfer electrode109on the base substrate101, and a one-side excess distance a/c/d/g of the orthographic projection of the second transfer electrode109on the base substrate101relative to the orthographic projection of the second through hole V2on the base substrate101in the extension direction Y of the data line102and/or the extension direction X of the gate line104is greater than or equal to 3 μm. In the case where the one-side excess distance a/c/d/g of the orthographic projection of the second transfer electrode109on the base substrate101relative to the orthographic projection of the second through hole V2on the base substrate101in the extension direction Y of the data line102and/or the extension direction X of the gate line104is greater than or equal to 3 μm, even if process fluctuation occurs, the second transfer electrode109can still cover the second through hole V2well, which reduces the risk of corrosion of the widened portion21and the first electrode72caused by moisture contact through the second through hole V2.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, in order to prevent short circuit between the widened portion21and the gate71that is disposed in the same layer and made of the same material as the widened portion21, and to make the structure of the transistor107more compact, as shown inFIG.23, a distance h between the widened portion21and the gate71of the transistor107electrically connected to the widened portion21may be set to be greater than or equal to 4.8 μm, for example, 5 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, in the case where the wiring space is sufficient, in order to better prevent short circuit between the widened portion21and the gate71of the transistor107adjacent to and unconnected to the widened portion21, the distance between the widened portion21and the gate71of the transistor107adjacent to and unconnected to the widened portion21may be increased. For example, a distance h between the widened portion21and the gate71of the transistor107adjacent to and unconnected to the widened portion21is set to be equal to or greater than 11 μm, and optionally, the distance h is 13 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, the orthographic projection of the second transfer electrode109on the base substrate101is positioned within the orthographic projection of the widened portion21on the base substrate101, so that a sufficient overlap region is present between the data line102and the second transfer electrode109, and a good electrical connection effect between the data line102and the second transfer electrode109is ensured.

In a case where the data line102is provided with the widened portion21, if the widened portion21and the gate line104are overlapped, the coupling capacitance between the data line102and the gate line104would be large. Based on this, in order to reduce the coupling capacitance between the data line102and the gate line104and to reduce the mutual interference between signals on the data line102and the gate line104, in some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, the orthographic projection of the widened portion21on the base substrate101may be positioned within the orthographic projection of the accommodating groove AG on the base substrate101.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.5to7,11,15,19,23,24,32,36,37,40,41,44,45,48to50,52to54, and56, the display substrate may further include a second electrode110, which forms a capacitor together with the first electrode106, the capacitor being a storage capacitor (Cst) or a liquid crystal capacitor (Clc). The first electrode106of the storage capacitor (Cst) is a pixel electrode, the first electrode106or the second electrode110of the liquid crystal capacitor (Clc) is a pixel electrode (P), and the pixel electrode is electrically connected to the second electrode73of the transistor107. Optionally, the pixel electrode is positioned in a pixel region surrounded by the orthographic projection of the data lines102on the base substrate101and the orthographic projection of the gate lines104on the base substrate101. In order to facilitate the lap joint of the pixel electrode with the second electrode73of the transistor107, the orthographic projection of the second electrode73of the transistor107on the base substrate101may be configured to extend from the U-shaped structure of the base substrate101till to overlap a part of the of the pixel electrode in the pixel region.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.8,10and23, an orthographic projection of the second electrode110on the base substrate101is positioned within a region surrounded by orthographic projections of respective data lines102on the base substrate101and orthographic projections of respective gate lines104on the base substrate101, and a distance d2between the orthographic projection of the second electrode110on the base substrate101and the orthographic projection of the data line102on the base substrate101is greater than or equal to 6.4 μm. Under the condition that the distance d2between the orthographic projection of the second electrode110on the base substrate101and the orthographic projection of the data line102on the base substrate101is greater than or equal to 6.4 μm, not only the second electrode110and the data line102can be prevented from being overlapped due to process fluctuation, but also the dark region at and near the data line102can be prevented from being too large, thereby avoiding a large transmittance loss.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.8, the second electrode110and the data line102may be disposed in the same layer and made of different materials. In this case, the pattern of the second electrode110may be first formed using one mask, and then the pattern of the data line102may be formed using another mask. Optionally, to ensure the transmittance, the second electrode110is made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

In some embodiments, in the display substrate according to the embodiment of the present disclosure, after a first conductive film layer for manufacturing the second electrode110and a second conductive film layer for manufacturing the data line102are sequentially formed, a mask may be used to pattern the first conductive film layer and the second conductive film layer to form a pattern of the second electrode110and the data line102. In this case, the shielding effect of the data line102may cause the presence of the pattern of the first conductive film layer below the data line102, specifically as shown inFIG.10, the display substrate further includes a resistance reduction line111, which is disposed in the same layer and made of the same material as the second electrode110, and the resistance reduction line111is electrically connected to the data line102in a contact manner. In order to prevent short circuit between the resistance reduction line111and the second electrode110, a distance d3between an orthographic projection of the resistance reduction line111on the base substrate101and the orthographic projection of the second electrode110on the base substrate101may be set to be greater than or equal to 4.8 μm, that is, the orthographic projection of the resistance reduction line111on the base substrate101exceeds by a distance of 1.6 μm relative to one side of the orthographic projection of the data line102on the base substrate101. Optionally, to ensure the transmittance, the second electrode110is made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and26, the second electrode110is a pixel electrode, and the display substrate further includes a third transfer electrode112, which is disposed in the same layer and made of the same material as the first electrode106. The third transfer electrode112is electrically connected to the second electrode106through a fifth via V31penetrating through the first insulating layer103and the second insulating layer105, and is electrically connected to the second electrode73of the transistor107through a sixth via V32penetrating through the second insulating layer105. In this case, the fabrication of the third transfer electrode112can be completed at the same time of fabricating the first electrode106, thereby avoiding an additional process for fabricating the third transfer electrode112. Furthermore, a sixth via V32penetrating through the second insulating layer105and used for electrically connecting the third transfer electrode108and the second electrode73and a fifth via V31penetrating through the first insulating layer103and the second insulating layer105and used for electrically connecting the third transfer electrode103and the second electrode73of the transistor107can be simultaneously formed by one patterning process, thereby avoiding an additional process of patterning the first insulating layer103. It should be understood that in some embodiments, as shown inFIG.29, the second electrode110may alternatively be electrically connected to the second electrode73of the transistor107by a ninth via V3′ penetrating through the first insulating layer103.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and26, in order to ensure a small lap resistance between the third transfer electrode112and the second electrode110and a good topography of the fifth via V31, an orthographic projection of the fifth via V31on the base substrate101may be positioned within the orthographic projection of the second electrode110on the base substrate101. An aperture of the fifth via V31in the direction Z away from the base substrate101is gradually increased. The fifth via V31includes a fifth port close to the base substrate101, a length m of the fifth port in the extension direction X of the gate line104is greater than or equal to 3 μm, and a width r of the fifth port in the extension direction Y of the data line102is greater than or equal to 6 μm. Optionally, the length m is 4.75 μm, and the width r is 6 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIGS.23and26, in order to ensure a small lap resistance between the third transfer electrode112and the second electrode73of the transistor107and a good topography of the sixth via V32, the orthographic projection of the sixth via V32on the base substrate101may be positioned within an orthographic projection of the second electrode73of the transistor107on the base substrate101. An aperture of the sixth via V32in the direction Z away from the base substrate101is gradually increased. The sixth via V32includes a sixth port close to the base substrate101, a length n of the sixth port in the extension direction X of the gate line104is greater than or equal to 3 μm, and a width r′ of the sixth port in the extension direction Y of the data line102is greater than or equal to 8 μm. Optionally, the length n is 6.25 μm, and the width r′ is 8 μm.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, to simplify the design of the via, the fifth via V31and the sixth via V32may be integrally provided as a third through hole V3. Optionally, an orthographic projection of the third through hole V3on the base substrate101is positioned within the orthographic projection of the third transfer electrode112on the base substrate101, and a one-side excess distance I/o/q/s of the orthographic projection of the third transfer electrode112on the base substrate101relative to the orthographic projection of the third through hole V3on the base substrate101in the extension direction Y of the data line102and/or the extension direction X of the gate line104is greater than or equal to 3 μm. Under such condition, even if process fluctuation occurs, the third transfer electrode112can still cover the third through hole V3well, which reduces the risk of corrosion of the second electrode73caused by moisture contact through the third through hole V3.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, the first electrode106includes an avoidance slot AS. Optionally, an opening of the avoidance slot AS faces the accommodating groove AG, the third transfer electrode112is positioned in the avoidance slot AS, and a distance p between the third transfer electrode112and the avoidance slot AS is greater than or equal to 4 μm, so as to prevent short circuit between the third transfer electrode112and the first electrode106that are disposed in the same layer and made of the same material.

In some embodiments, as shown inFIG.23, the display substrate according to the embodiment of the present disclosure may further include a first connection line113, which is disposed in the same layer and made of the same material as the first electrode106, and the first connection line113is electrically connected to a non-pixel electrode (such as the first electrode106inFIG.23) in the extension direction Y of the data line102, so that the overall resistance of the non-pixel electrode in the capacitor is relatively small, and meanwhile, the voltage uniformity and stability of the non-pixel electrode in the capacitor in the extension direction Y of the data line102are also improved.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, the first connection line113may cross over the accommodating groove AG along the extension direction Y of the data line102. Optionally, the first connection line113crosses over the accommodating groove AG within a distance y, which is between the protrusion41and the widened portion21adjacent to and not electrically connected to the protrusion41. Such setting can ensure a small coupling capacitance between the first connection line113and the gate line104.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, a distance v between an orthographic projection of the first connection line113on the base substrate101and the orthographic projection of the protrusion41closest to the connection line113on the base substrate101is greater than or equal to 3 μm, so as to avoid overlapping of the first connection line113and the protrusion41caused by process fluctuation and the like.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, a distance x between the orthographic projection of the first connection line113on the base substrate101and the orthographic projection of a data line102(specifically, the widened portion21of the data line102) closest to the connection line113on the base substrate101is greater than or equal to 4 μm, so as to avoid overlapping of the first connection line113and the data line102caused by process fluctuation and the like.

In some embodiments, in the display substrate according to the embodiment of the present disclosure, as shown inFIG.23, the width w of the first connection line113in the extension direction Y of a gate line104is greater than or equal to 4 μm, so as to prevent the first connection line113from breaking.

In some embodiments, as shown inFIGS.5to7,11,14,15,18,19and22, the first electrode106and the second electrode110are overlapped in a region surrounded by the data lines102and the gate lines104to form a liquid crystal capacitor (Clc), the first electrode106is a common electrode (Com) of a slit shape, and the second electrode110is a pixel electrode of a block shape. In addition, as can be seen fromFIGS.16,18,20and22, the first electrode106may be a double domain electrode, and an extension direction of the remaining portion of the data line102other than the widened portion21may be the same as an extension direction of the double domain electrode, in which case, the extension direction Y of the data line102in the present disclosure refers to an overall extension direction of the data line102, i.e., a column direction.

In some embodiments, as shown inFIGS.30to40, the first electrode106and the second electrode110are overlapped in a region surrounded by the data lines102and the gate lines104to form a liquid crystal capacitor (Clc), the first electrode106is a pixel electrode of a slit shape, the second electrode110is a common electrode of a block shape, and the orthographic projection of the first electrode106on the base substrate101and the orthographic projection of the second electrode110on the base substrate101are both positioned in only the region surrounded by the data lines102and the gate lines104. In some embodiments, as shown inFIG.31, the second electrode110and the data line102may be disposed in the same layer with a gap therebetween, and made of different materials. Compared to a scheme where the second electrode110and the data line102are disposed in different layers, the present disclosure can reduce the number of the film layers, which is favorable for achieving a light and thin product design.

In some embodiments, as shown inFIGS.41to48, the first electrode106and the second electrode110are disposed in the same layer and made of the same material, and both the first electrode106and the second electrode110have a comb-shaped structure, and the comb-tooth portions of the first electrode106and the comb-tooth portions of the second electrode110are alternately arranged, so that the first electrode106and the second electrode110have side surfaces opposite to each other in the same layer to form a liquid crystal capacitor (Clc). Optionally, the first electrode106is a pixel electrode electrically connected to the second electrode73of the transistor107, and the second electrode110is a common electrode. In some embodiments, the orthographic projection of the first electrode106on the base substrate101is only positioned in the region surrounded by the data lines102and the gate lines104, and the orthographic projection of the second electrode110on the base substrate101is not only positioned in the region surrounded by the data lines102and the gate lines104but also covers the orthographic projection of most portion of the data line102except the widened portion21on the base substrate101, so that the area of the second electrode110is larger, and more gaps between the comb-tooth portions can be formed in the second electrode110to improve the transmittance and the luminous efficiency. Optionally, the comb-tooth portion of the first electrode106and the comb-tooth portion of the second electrode110may have a zigzag-shape, for example, a V-shape with an obtuse angle. The extension direction of the remaining portion of the data line102other than the widened portion21may be the same as the extension direction of the comb-tooth portion, in which case, the extension direction Y of the data line102in the present disclosure refers to the overall extension direction of the data line102, i.e., the column direction.

Optionally, inFIGS.5to7,30and41, the common electrodes (i.e., the first electrodes106inFIGS.5to7and the second electrodes110inFIGS.30and41) of the same row in the extension direction of the gate line104may be further connected by a second connection line114to reduce the overall resistance of the common electrodes, and meanwhile, the voltage uniformity and stability of the common electrodes in the extension direction X of the gate line104are improved. In some embodiments, as shown inFIGS.13,17,21,34,39,43,47,51, and55, the second connection line114may be disposed in the same layer and made of the same material as the gate line104. In the case where the common electrode is the first electrode106(as shown inFIGS.5to7), or the common electrode is the second electrode110and is disposed in the same layer and made of the same material as the first electrode106(as shown inFIG.41), the second connection line114is electrically connected to the common electrode through a via penetrating through the second insulating layer105. In the case where the common electrode is the second electrode110(as shown inFIG.30), the second connection line114is electrically connected to the common electrodes of the same row in the extension direction X of the gate line104through the a connection line113that is disposed in the same layer and made of the same material as the first electrode106.

In some embodiments, as shown inFIGS.49to56, the first electrode106and the second electrode110constitute a storage capacitor (Cst). The first electrode106is a slit electrode, and the first electrode106includes a cross-shaped main body portion MB, the slits of the first electrode106are distributed in four regions defined by the cross-shaped main body portion MB, the extension directions of slits in two regions in the diagonal direction are the same, and the extension directions of slits in two adjacent regions are intersected. The second electrode110and the data line102are disposed in the same layer and made of the same material, and the orthographic projection of the second electrode110on the base substrate101and an orthographic projection of the cross-shaped main body MB on the base substrate101are overlapped. In some embodiments, second electrodes110of the same row in the extension direction X of the gate line104may be electrically connected through the first connection line113, so as to reduce the overall resistance of the second electrodes110, and meanwhile, the voltage uniformity and stability of the second electrodes110in the extension direction X of the gate line104are improved.

Based on the same inventive concept, an embodiment of the present disclosure provides a display panel. As shown inFIGS.57and58, the display panel includes a display substrate001and an opposite substrate002that are oppositely arranged, and a liquid crystal layer003positioned between the display substrate001and the opposite substrate003, the display substrate001being the display substrate001according to the embodiment of the present disclosure. Since the problem-solving principle of the display panel is similar to that of the display substrate, the implementation of the display panel according to the embodiment of the present disclosure can refer to the implementation of the display substrate according to the embodiment of the present disclosure, and repeated descriptions are omitted.

In some embodiments, in the display panel according to the embodiment of the present disclosure, as shown inFIGS.57and58, the first electrode106includes an electrode strip106′, an orthographic projection of the electrode strip106′ and the orthographic projection of the data line102are overlapped. The opposite substrate002includes a black matrix201, the black matrix201including a first black matrix strip11extending along the extension direction Y of the data line102. The orthographic projection of a part of the first black matrix strip11on the base substrate101is positioned within the orthographic projection of the electrode strip106′ on the base substrate101. Since the location of the electrode strip106′ is a dark region, disposing the first black matrix strip11at the electrode strip106′ would not affect the transmittance. Optionally, the width of the first black matrix strip11in the extension direction X of the gate line104is greater than or equal to 8 μm, so that the problem of cross color at oblique viewing angles is avoided through the black matrix strip11. In some embodiments, the black matrix201may further include a second black matrix strip12extending along the extension direction X of the gate line104. Optionally, the orthographic projection of the gate line104on the base substrate101is positioned within an orthographic projection of the second black matrix strip12on the base substrate101.

In some embodiments, the display panel according to the embodiment of the present disclosure may further include a sealant surrounding the liquid crystal layer003between the display substrate001and the opposite substrate002, a first alignment layer positioned on a side of the display substrate close to the liquid crystal layer, a second alignment layer positioned on a side of the opposite substrate close to the liquid crystal layer, a first polarizer positioned on a side of the display substrate001away from the liquid crystal layer003, a second polarizer positioned on a side of the opposite substrate002away from the liquid crystal layer003, and the like, a polarization direction of the first polarizer being perpendicular to a polarization direction of the second polarizer. It should be understood by those skilled in the art that other essential components of the display panel are not described herein, and should not be construed as limitations of the present disclosure.

Based on the same inventive concept, an embodiment of the present disclosure provides a display device including the display panel according to the embodiment of the present disclosure. Since the problem-solving principle of the display device is similar to that of the display panel, the implementation of the display device according to the embodiment of the present disclosure can refer to the implementation of the display panel according to the embodiment of the present disclosure, and repeated descriptions are omitted.

In some embodiments, the display device according to the embodiment of the present disclosure may further include a backlight module, and the display panel is disposed at a light emitting side of the backlight module. The backlight module may be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include a light bar, and a reflector, a light guide plate, a diffuser, a prism group, and the like that are provided in a stacked manner, the light bar being positioned on a side of the light guide plate in the thickness direction of the light guide. The direct-lit backlight module may include a matrix light source, and a reflector, a diffuser plate, a brightness enhancement film, and the like that are provided in a stacked manner at the light-emitting side of the matrix light source, the reflector including an opening disposed directly opposite to the position of each bead in the matrix light source. The beads in the light bar and the beads in the matrix light source may be light emitting diodes (LEDs), such as micro light emitting diodes (Mini LED, Micro LED, etc.).

Like organic light emitting diodes (OLEDs), micro light emitting diodes of sub-millimeter or even micron scale belong to self-light emitting devices. Like organic light emitting diodes, the micro light emitting diodes of sub-millimeter or even micron scale have a series of advantages of high brightness, ultralow delay, overlarge visual angle and the like. Furthermore, since the inorganic light emitting diodes emit light based on a metal semiconductor with more stable property and lower resistance, the inorganic light emitting diodes have the advantages of lower power consumption, higher high temperature resistance and low temperature resistance and longer service life, as compared to organic light emitting diodes that emit light based on organic matters. When the micro light emitting diodes serve as a backlight source, a more precise dynamic backlight effect can be achieved; the problem of glare between bright and dark regions on a screen caused by traditional dynamic backlight can be solved while effectively improving the screen brightness and the contrast ratio, thereby optimizing the visual experience.

In some embodiments, the display device according to the embodiment of the present disclosure may be a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, an intelligent watch, a fitness wrist strap, a personal digital assistant and any other product or component with a display function. The display device includes and is not limited to a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, or the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), or the like. For example, the control chip may further include a memory, a power module, and the like, and power supply and signal input and output functions are realized through additionally arranged wires, signal lines, and the like. For example, the control chip may also include a hardware circuit, a computer executable code, and the like. The hardware circuit may include a conventional Very Large Scale Integration (VLSI) circuit or gate array, and conventional semiconductors such as logic chips, transistors, or other discrete components; the hardware circuit may also include a field-programmable gate array, programmable array logic, a programmable logic device, or the like. In addition, it may be understood by those skilled in the art that the above-described structure does not constitute a limitation on the above-described display device according to the embodiments of the present disclosure, in other words, the above-described display device according to the embodiments of the present disclosure may include more or less components than the components described above, or some components may be combined, or different component arrangements may be provided.

While the disclosure has described preferred embodiments, it will be understood that various changes and modifications may be made to the disclosed embodiments by those skilled in the art without departing from the spirit and scope of the disclosed embodiments. Thus, if such modifications and variations of the embodiments of the present disclosure are within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.