Patent ID: 12255201

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different nodes of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In some embodiments, the formation of a first node over or on a second node in the description that follows may include embodiments in which the first and the second nodes are formed in direct contact, and may also include embodiments in which additional nodes may be formed between the first and the second nodes, such that the first and the second nodes may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

The present disclosure will be described with respect to embodiments in a specific context, namely an electrostatic discharge (ESD) protection diode for GAA applications. The embodiments of the disclosure may also be applied, however, to a variety of ESD protection applications. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

Semiconductor devices including transistors are susceptible to extremely high voltage spikes such as an electrostatic discharge (ESD) transient. ESD is a rapid discharge that flows between two objects due to the built-up of static charge. ESD may destroy semiconductor devices because the rapid discharge can produce a relatively large current. ESD protection structures are needed for the ICs. In ESD protection, an ESD circuit is formed near integrated circuit terminals such as input and output pads, and also for power supply terminals. ESD protection circuits may provide a current discharge path so as to reduce the number of semiconductor failures that occur as a result of ESD. In other words, ESD is a major factor related to the reliability of electronic devices. Proper ESD protection is necessary to protect the electronic device from damage by electrostatic discharge.

Semiconductor devices of ICs can be damaged by ESD events. Such ESD events can occur when static electricity is suddenly discharged from a body surface to a device. For example, during the manufacturing or testing of an IC, an ESD event can occur between an engineer's finger and a semiconductor wafer on which a semiconductor device is located, causing a sudden in-rush of current or voltage to strike the semiconductor device. This sudden in-rush of current or voltage can catastrophically damage the device in a number of ways, such as blowing out a gate oxide or causing junction damage, for example. ESD protection devices or circuits are used to protect against such ESD events taking place in the IC.

FIG.1shows a top view of a electrostatic discharge (ESD) device100A, in accordance with some embodiments of the disclosure. The ESD device100A is formed over a semiconductor substrate105. The ESD device100A includes a diode (not shown) for ESD protection. In some embodiments, the semiconductor substrate105is a Si substrate. In some embodiments, the material of the semiconductor substrate105is selected from a group consisting of bulk-Si, SiP, SiGe, SiC, SiPC, Ge, SOI—Si, SOI—SiGe, III-VI material, and combinations thereof.

A P-type epitaxy region10is formed over the semiconductor substrate105, and the P-type epitaxy region10is configured as the anode of the diode. Furthermore, an N-type epitaxy region15is formed over the semiconductor substrate105, and the N-type epitaxy region15is configured as the cathode of the diode. It should be noted that the P-type epitaxy region10is separated from the N-type epitaxy region15by a junction region18. In the ESD device100A, the width of the junction region18between the P-type epitaxy region10and the N-type epitaxy region15(e.g., along the X direction) is W1.

In some embodiments, the width W21of the P-type epitaxy region10within an oxide diffusion (OD) region20along the X direction is greater than the width W1of the junction region18, i.e., W21>W1. Moreover, the width W22of the N-type epitaxy region15within the OD region20along the X direction is greater than the width W1of the junction region18, i.e., W22>W1. In some embodiments, width W21is different than width W22. In some embodiments, width W21is equal to width W22.

The P-type epitaxy region10is coupled to a ground line through a contact (not shown inFIG.1) that is formed within the OD region20and over the P-type epitaxy region10. Moreover, the N-type epitaxy region15is coupled to a power line through another contact (not shown inFIG.1) that is formed within the OD region20and over the B-type epitaxy region15. In some embodiments, the OD region20is used as an active region for an transistor. In some embodiments, the OD region is defined by the shallow trench isolation (STI) regions of the ESD device100A. In some embodiments, the contact is a metal to diffusion (MD) contact.

Multiple electrodes30are formed over the diode of the ESD device100A. In some embodiments, the material of the electrodes30is similar to the metal gate of the transistors to be protected by the ESD device100A, and the transistors and the ESD device100A are formed over the semiconductor substrate105in the same IC. Furthermore, the electrodes30are formed within the OD region20.

In some embodiments, a half of the electrodes30(labeled as30a) are formed over the junction region18and the P-type epitaxy region10. Furthermore, the remaining electrodes30(labeled as30b) are formed over the junction region18and the N-type epitaxy region15. In some embodiments, the electrodes30do not affect the function or operation of the diode of the ESD device100A. For example, the electrodes30is arranged based on process considerations for subsequent processes, such as balance for chemical mechanical polishing (CMP) of the whole IC.

In some embodiments, the electrodes30aand30bare not formed over the junction region18. For example, the electrodes30aare formed only over the P-type epitaxy region10within the OD region20, and the electrodes30bare formed only over the N-type epitaxy region15within the OD region20. In some embodiments, the electrodes30are formed outside the OD region20.

ESD current path Path1is a schematic representation to indicate how an electron diffusion current may be directed in an ESD event according to the embodiment shown inFIG.1. In the ESD device100A, the ESD current path Path1represents a current that may be generated by an ESD event. The ESD current path Path1flows from the N-type epitaxy region15which is considered to be at one electrical node, to the P-type epitaxy region10which is considered to be at another electrical node during the ESD event.

In some embodiments, when the area of the OD region20or the P-type epitaxy region10and the N-type epitaxy region15of the ESD device100A is increased, the diode size of the ESD device100A is increased. In some embodiments, the diode size of the ESD device100A is increased by mirror the ESD device100A inFIG.1along the X direction or the Y direction.

FIG.2shows a schematic cross-sectional view illustrating the ESD structure of the ESD device100A along line A-AA inFIG.1, in accordance with some embodiments of the disclosure. As described above, the P-type epitaxy region10and the N-type epitaxy region15are formed over the semiconductor substrate105.

In the junction region18, multiple semiconductor layers110and120are alternatingly stacked over the semiconductor substrate105and formed between the P-type epitaxy region10and the N-type epitaxy region15. Furthermore, one side of each semiconductor layers110is in contact with the P-type epitaxy region10, and an opposite side of each semiconductor layers110is in contact with the N-type epitaxy region15. Similarly, one side of each semiconductor layers120is in contact with the P-type epitaxy region10, and an opposite side of each semiconductor layers120is in contact with the N-type epitaxy region15.

In some embodiments, the semiconductor layers110are the silicon layers, and the semiconductor layers120are the germanium layers, e.g., the SiGe layers. In some embodiments, the semiconductor layers110are the germanium layers (e.g., the SiGe layers), and the semiconductor layers120are the silicon layers. In some embodiments, the semiconductor layers110are formed by doping Ge into the Si-base semiconductor layer or formed by epitaxially growing SiGe or Ge material on the Si-base semiconductor layers120and then annealing.

In the ESD event, the electron diffusion current flows from the N-type epitaxy region15to the P-type epitaxy region10through multiple ESD current paths Path1_aand Path1_b. In such embodiments, the ESD current path Path1_arepresents a current flowing from the N-type epitaxy region15to the P-type epitaxy region10through the semiconductor layer120during the ESD event, and the ESD current path Path1_brepresents a current flowing from the N-type epitaxy region15to the P-type epitaxy region10through the semiconductor layer110during the ESD event. Since the semiconductor layers110and120have different mobility caused by different materials, the current value and/or speed in the ESD current paths Path1_aand Path1_bare different.

In some embodiments, the P-type epitaxy region10and the N-type epitaxy region15have the same depth D2. Furthermore, a depth D1of the stacked semiconductor layers110and120is less than the depth D2of the P-type epitaxy region10and the N-type epitaxy region15.

InFIG.2, the electrode30ais formed over the interface between the junction region18and the P-type epitaxy region10, and the electrode30ais configured to partially cover the junction region18and the P-type epitaxy region10. Similarly, the electrode30bis formed over the interface between the junction region18and the N-type epitaxy region15, and the electrode30bis configured to partially cover the junction region18and the N-type epitaxy region15. The electrodes30aand30bare used to provide process empty space, and no signal is applied to the electrodes30aand30b, i.e., the electrodes30aand30bare floating.

In a traditional ESD device, the N-type well region is used to form the cathode of the diode and the P-type well region is used to form the anode of the diode. Compared with the traditional ESD device, no P-type or N-type well region is used in the ESD device100A. Therefore, the ESD device100A is suitable for the IC with the backside structure because no bulk is required for the transistors in the IC.

FIG.3shows a cross-sectional view illustrating the semiconductor structure of an IC200A with the ESD device100A, in accordance with some embodiments of the disclosure. InFIG.3, the IC200A is formed by a super power rail (SPR) process so as to form the power rail and/or the metal in the backside of semiconductor substrate105of the IC200A.

In some embodiments, after the ESD device100A is formed, the semiconductor substrate105is turned 180 degrees to make the ESD device100A face down. Next, the metal line150is formed over the backside of the semiconductor substrate105. A via155is formed over the metal line150, and then a metal line160is formed over the via155. Next, A via165is formed over the metal line160, and then a metal line170is formed over the via165.

The metal lines150,160and170are formed in different metal levels. In some embodiments, the metal line150is configured to connect a power line through the via155, the metal line160, the via165and the metal line170in sequence. In some embodiments, the metal line150is configured to connect a ground line through the via155, the metal line160, the via165and the metal line170in sequence. In some embodiments, the metal lines150,160and170and the electrode30are formed by the same conductive material.

FIG.4shows a cross-sectional view illustrating the semiconductor structure of an IC200B with the ESD device100A, in accordance with some embodiments of the disclosure. In the IC200B, the ESD device100A is capable of providing ESD protection for the transistor210. The ESD device100A is separated from the transistor210by the STI130. The transistor210is a GAA transistor. In some embodiments, a depth of the STI region130is greater than the depth D2of the P-type epitaxy region10and the N-type epitaxy region15.

InFIG.4, the transistor210is a P-type transistor. In the transistor210, two P-type epitaxy regions10are formed over the semiconductor substrate105. One of the P-type epitaxy regions10on the left is configured as the drain region of the transistor210, and the other P-type epitaxy region10is configured as the source region of the transistor210. For example, the P-type epitaxy region10on the left is configured as the drain region of the transistor210, and the P-type epitaxy region10on the right is configured as the source region of the transistor210. A channel region CH of the transistor210is formed by alternatingly stacked the semiconductor layers110and120over the semiconductor substrate105. In some embodiments, the semiconductor layers110are the silicon layers, and the semiconductor layers120are the germanium layers, e.g., the SiGe layers. In some embodiments, the semiconductor layers110are the germanium layers (e.g., the SiGe layers), and the semiconductor layers120are the silicon layers. InFIG.4, each semiconductor layer120may be a nanowire or nanosheet that forms a channel for the transistor210.

In some embodiments, the transistor210is an N-type transistor. In such embodiments, two N-type epitaxy regions15(not shown) are formed over the semiconductor substrate105in the transistor210. One of the N-type epitaxy regions15on the left is configured as the drain region of the transistor210, and the other N-type epitaxy region15is configured as the source region of the transistor210.

In the channel region CH, one side of each semiconductor layers120is in contact with the P-type epitaxy region10on the left, and an opposite side of each semiconductor layers120is in contact with the P-type epitaxy region10on the right. Compared with the ESD device100A, the semiconductor layers110of the channel region CH is separated from the P-type epitaxy regions10by the spacers115. In other words, one side of each semiconductor layers110is in contact with the spacer115on the left, and an opposite side of each semiconductor layers120is in contact with the spacer115on the right.

In the transistor210, the distance of the channel region CH between the P-type epitaxy regions15(e.g., along the X direction) is W23. In some embodiments, the width W1of the ESD device100A is equal to the distance W23of the transistor210. In some embodiments, the width W1of the ESD device100A is greater than the distance W23of the transistor210.

The transistor210further includes a gate structure140over the channel region CH. In order to simplify the description, some layers (e.g., the gate dielectric layer) of the transistor210are omitted inFIG.4. The gate structure140includes a gate electrode35and the spacers115. The gate electrode35is connected to an overlying level (not shown) through a via (not shown). Furthermore, the semiconductor layers120are wrapped by the gate electrode35.

In some embodiments, the gate electrode35and the electrode30are formed by the same conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some embodiments, the gate electrode35includes multiple material structure selected from a group consisting of poly gate/SiON structure, metals/high-K dielectric structure, Al/refractory metals/high-K dielectric structure, silicide/high-K dielectric structure, or combination.

In the IC200B, compared with the transistor210, no gate structure is formed in the ESD device100A. Furthermore, no spacer is formed in the ESD device100A. Moreover, the electrodes30(i.e.,30aand30b) are arranged to partially cover the P-type epitaxy region10and the N-type epitaxy region15of the ESD device100A. However, in the transistor210, the gate structure is completely formed over the channel region CH.

FIG.5shows a cross-sectional view illustrating the semiconductor structure of an IC200C with the ESD device100A, in accordance with some embodiments of the disclosure. In the IC200C, the ESD device100A is capable of providing ESD protection for the corresponding devices (e.g., the transistor210ofFIG.4). Moreover, the IC200C further the ESD device145that is capable of providing ESD protection for the other devices (not shown).

The ESD device100A is separated from the ESD device145by the STI130and other devices (not shown). The ESD device145has the configuration similar to the transistor210ofFIG.4. The difference between the ESD device145and the transistor210is that one of the P-type epitaxy regions10of the transistor210is replaced with the N-type epitaxy region15to form the ESD device145.

ESD current paths Path1and Path2are schematic representations that are superimposed inFIG.5to indicate how an electron diffusion current may be directed in an ESD event according to the embodiment shown inFIG.5. In the ESD device100A, the ESD current path Path1represents a current that may be generated by an ESD event. Furthermore, In the ESD device145, the ESD current path Path2represents a current that may be generated by the ESD event.

Compared with the ESD device145, no spacer115is formed on the two sides of the semiconductor layers110of the ESD device100A, i.e., the spacer115is absent in the ESD current path Path1. Thus, the current characteristics (current value or speed) in the ESD current path Path1of the ESD device100A is better than that in the ESD current path Path2of the ESD device145since the spacers115is present in the ESD current path Path2of the ESD device145. In other words, the ESD device100A is capable of providing better ESD protection.

In the ESD device145, the distance between the P-type epitaxy region10and the N-type epitaxy region (e.g., along the X direction)15is W24. In some embodiments, the width W1of the ESD device110A is equal to the distance W24of the ESD device145. In some embodiments, the width W1of the ESD device110A is greater than the distance W24of the ESD device145.

InFIG.4andFIG.5, after forming the stacked semiconductor layers110and120of the junction region18, the P-type epitaxy region10and the N-type epitaxy region15of the ESD device100A, one or more masks are used to block subsequent processes for the junction region18, e.g., no strained source/drain (SSD) etch. Thus, no spacer115is formed in the junction region18and then no gate structure is formed over the junction region18. The ESD device100A can be formed without following the GAA process, e.g., the transistor210ofFIG.4and the ESD device145ofFIG.5are formed according to the operations of the GAA process. In other words, the ESD device100A does not need to meet the specifications of GAA device. For example, the ESD device100A may has larger OD region20than the transistor210ofFIG.4and the ESD device145ofFIG.5. When the size of the OD region20of the ESD device100A is increased, the size of the diode of the ESD device100A is increased.

FIG.6shows a top view of an ESD device100B, in accordance with some embodiments of the disclosure. The ESD device100B is formed over the semiconductor substrate105. The ESD device100B includes a diode (not shown) for ESD protection. The P-type epitaxy region10is formed over the semiconductor substrate105, and the P-type epitaxy region10is configured as the anode of the diode. Furthermore, an N-type epitaxy region15is formed over the semiconductor substrate105, and the N-type epitaxy region15is configured as the cathode of the diode.

The ESD device100B ofFIG.6has the configuration similar to the ESD device100A ofFIG.1. The difference between the ESD devices100A and100B is that the contact40on the left is formed over the N-type epitaxy regions15, and the contact40on the right is formed over the P-type epitaxy regions10in the ESD device100B ofFIG.6.

The process limitation of features is described inFIG.6, and the features within the OD region20should be considered in order to determine the minimum size of the OD region20. The distance from one end of the electrode30to the boundary of the OD region20is W2. The distance from one end of the contact40to the boundary of the OD region20is W3, and the distance from the other end of the contact40to the boundary of the N-type epitaxy region15is W4. In some embodiments, distance W2is less than distance W3and distance W4. In some embodiments, distance W3and distance W4are equal.

InFIG.6, the distance from the boundary of the N-type epitaxy region15to the other end of the electrode30is W5. In some embodiments, distance W5is less than or equal to distance W2. Furthermore, a portion of the electrode30over the junction region18is shorter than the remaining portion of the electrode30over the N-type epitaxy region15or the P-type epitaxy region10. Furthermore, the electrodes30in the ESD device100B have a width of W30. The distance from electrode30ato electrode30bis W6. In some embodiments, distance W6is greater than distance W2and distance W5, and distance W6is less than distance W3and distance W4.

InFIG.6, the length of the electrodes30is W7. In some embodiments, the length W7is greater than the distance W1. In some embodiments, the width of the contact40is greater than or equal to the width W30of the electrode30, and the length of the contact40is less than the length W7of the electrode30. In some embodiments, the OD region20has a width W8and a length W25. The width W8of the OD region20is determined by adding twice the distance W2, twice the length W7, and the distance W6. Therefore, according to the minimum distance W2, the minimum length W7, and the minimum distance W6, the minimum width of the OD region20is obtained. In some embodiments, the minimum width of the OD region20is greater than the maximum width of the OD region of the GAA transistor (e.g., the transistor210ofFIG.4and ESD device145ofFIG.5).

In some embodiments, when the area of the OD region20or the P-type epitaxy region10and the N-type epitaxy region15of the ESD device100B is increased, the diode size of the ESD device100B is increased. In some embodiments, the diode size of the ESD device100B is increased by mirror the ESD device100B inFIG.6along the X direction or the Y direction.

FIG.7shows a top view of an ESD device100C, in accordance with some embodiments of the disclosure. The ESD device100C is formed over the semiconductor substrate105. The ESD device100C includes a diode (not shown) for ESD protection. A P-type epitaxy region10is formed over the semiconductor substrate105, and the P-type epitaxy region10is configured as the anode of the diode. Furthermore, an N-type epitaxy region15is formed over the semiconductor substrate105, and the N-type epitaxy region15is configured as the cathode of the diode. It should be noted that the P-type epitaxy region10is separated from the N-type epitaxy region15by a junction region18. In the ESD device100C, the distance of the junction region18from the P-type epitaxy region10to the N-type epitaxy region15is W1.

The electrodes30dand30eare formed over the diode of the ESD device100C. In some embodiments, the material of the electrodes30dand30eis similar to the metal gate of the transistors to be protected by the ESD device100C, and the transistors and the ESD device100C are formed over the semiconductor substrate105in the same IC. The electrode30cis formed over the P-type epitaxy region10, and the electrode30dis formed over the N-type epitaxy region15. In some embodiments, the electrodes30dand30edo not affect the function or operation of the diode of the ESD device100C. For example, the electrodes30dand30eis arranged based on process considerations for subsequent processes, such as balance for chemical mechanical polishing (CMP) of the IC.

The P-type epitaxy region10is coupled to a ground line through a contact (not shown inFIG.7) within the OD region20. Moreover, the N-type epitaxy region15is coupled to a power line through another contact (not shown inFIG.7) within the OD region20. In some embodiments, the OD region is used as an active region for an transistor. In some embodiments, the OD region is defined by the STI regions of the ESD device100C. In some embodiments, the contact is a metal to diffusion (MD) contact.

The OD region20has a width W26and a length W27. The distance W9between electrodes30dand30eis greater than the width W26of the OD region20. Therefore, the electrodes30dand30eare formed outside of the OD region20. Furthermore, the length of the electrodes30dand30eis greater than the length W27of the OD region20. In some embodiments, the electrodes30dand30ein the ESD device100C have a larger width than the width W30of the electrodes30of the ESD device100B inFIG.6. In the ESD device100C, no electrode30is formed within the OD region20. Thus, the size of the OD region20will not be limited by the electrodes30. In some embodiments, the OD region20of the ESD device100C is larger than the OD region20of the ESD device100B inFIG.6.

ESD current path Path3is a schematic representation to indicate how an electron diffusion current may be directed in an ESD event according to the embodiment shown inFIG.7. In the ESD device100C, the ESD current path Path3represents a current that may be generated by an ESD event. The ESD current path Path3flows from the N-type epitaxy region15which is considered to be at one electrical node, to the P-type epitaxy region10which is considered to be at another electrical node in the ESD event.

In some embodiments, when the area of the OD region20or the P-type epitaxy region10and the N-type epitaxy region15of the ESD device100C is increased, the diode size of the ESD device100C is increased. In some embodiments, the diode size of the ESD device100C is increased by mirror the ESD device100C inFIG.7along the X direction or the Y direction.

FIG.8shows a schematic cross-sectional view illustrating the structure of the ESD device100C along line B-BB inFIG.7, in accordance with some embodiments of the disclosure. As described above, the P-type epitaxy region10and the N-type epitaxy region15are formed over the semiconductor substrate105.

In the junction region18, multiple semiconductor layers110and120are alternatingly stacked over the semiconductor substrate105and between the P-type epitaxy region10and the N-type epitaxy region15. In some embodiments, the semiconductor layers110are the silicon layers, and the semiconductor layers120are the germanium layers, e.g., the SiGe layers. In some embodiments, the semiconductor layers110are the germanium layers (e.g., the SiGe layers), and the semiconductor layers120are the silicon layers. In some embodiments, the semiconductor layers110are formed by doping Ge into the Si-base semiconductor layer or formed by epitaxially growing SiGe or Ge material on the Si-base semiconductor layers120and then annealing. Furthermore, one side of each semiconductor layers110is in contact with the P-type epitaxy region10, and an opposite side of each semiconductor layers110is in contact with the N-type epitaxy region15. Similarly, One side of each semiconductor layers120is in contact with the P-type epitaxy region10, and an opposite side of each semiconductor layers120is in contact with the N-type epitaxy region15.

When the ESD event is present, the electron diffusion current flows from the N-type epitaxy region15to the P-type epitaxy region10through multiple ESD current paths Path3_aand Path3_b. In such embodiments, the ESD current path Path3_arepresents a current flowing through the semiconductor layer120during the ESD event, and the ESD current path Path3_brepresents a current flowing through the semiconductor layer110during the ESD event. Since the semiconductor layers110and120have different mobility caused by different materials, the current value and/or speed in the ESD current paths Path3_aand Path3_bare different.

InFIG.8, the electrode30cis formed over the P-type epitaxy region10, and the electrode30dis formed over the N-type epitaxy region15. The electrodes30cand30dare used to provide process empty space, and no other signal is applied to the electrodes30cand30d, i.e., the electrodes30cand30dare floating. Similarly, no P-type or N-type well region is used in the ESD device100C. Therefore, the ESD device100C is suitable for the IC with the backside structure because no bulk is required for the GAA transistors in the IC.

FIG.9shows a top view of an ESD device100D, in accordance with some embodiments of the disclosure. The ESD device100D is formed over the semiconductor substrate105. The ESD device100D includes a diode (not shown) for ESD protection. The P-type epitaxy region10is formed over the semiconductor substrate105, and the P-type epitaxy region10is configured as the anode of the diode. Furthermore, an N-type epitaxy region15is formed over the semiconductor substrate105, and the N-type epitaxy region15is configured as the cathode of the diode.

The ESD device100D ofFIG.9has the configuration similar to the ESD device100C ofFIG.7. The difference between the ESD devices100C and100D is that the contact40bis formed over the N-type epitaxy regions15within the OD region20, and the contact40ais formed over the P-type epitaxy regions10within the OD region20.

The process limitation of features is described inFIG.9, and the features should be considered in order to determine the minimum size of the OD region20. The distance from the electrode30dto the boundary of the OD region20is W11, and the distance from the electrode30cto the boundary of the OD region20is W12. In some embodiments, distance W11is less than distance W12. In some embodiments, distance W11is equal to distance W12. In some embodiments, the width W14of the P-type epitaxy region10within the OD region20is greater than or equal to the width W1of the junction region18, i.e., W14≥W1. Moreover, the width W13of the N-type epitaxy region15within the OD region20is greater than or equal to the width W1of the junction region18, i.e., W13≥W1. In some embodiments, width W13is different than width W14. In some embodiments, width W13is equal to width W14.

InFIG.9, the width W28of the OD region20is determined by the widths W13, W1and W14. In some embodiments, the electrodes30cand30dand the OD region20are the same length W16. Furthermore, the width of the electrodes30cand30dis W15. In some embodiments, the width W15of the electrodes30cand30dis greater than the width W30of the electrodes30inFIG.6. In some embodiments, the minimum width of the OD region20is obtained according to the minimum widths W13, W1and W14. As described above, the minimum width of the OD region20is greater than the maximum width of the OD region of the GAA transistor.

In some embodiments, when the area of the OD region20or the P-type epitaxy region10and the N-type epitaxy region15of the ESD device100D is increased, the diode size of the ESD device100D is increased. In some embodiments, the diode size of the ESD device100D is increased by mirroring the ESD device100D inFIG.9along the X direction or the Y direction.

Embodiments of the ESD device are provided. In the ESD device (e.g., the ESD device100A-100D) of the embodiments, no gate structure is formed, thereby decreasing the gated parasitic capacitance for the ESD device. The parasitic capacitance will seriously interfere with the signal transmission and thus affect the performance of the IC. Furthermore, no spacer is formed in the ESD device, and the electron diffusion current caused by the ESD event will not be affected by the inner spacer in a traditional ESD device. Compared with a traditional ESD device that is similar to the GAA transistor, the ESD devices of the embodiments have a larger OD region, so as to provide a larger diode for ESD protection.

In some embodiments, an electrostatic discharge (ESD) structure is provided. The ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, a plurality of semiconductor layers, a first conductive feature, a second conductive feature, a third conductive feature, and a fourth conductive feature. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. The first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. The second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. The fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features. A width between the first conductive feature and the oxide diffusion region is greater than or equal to a width between the second conductive feature and the oxide diffusion region.

In some embodiments, an electrostatic discharge (ESD) structure is provided. The ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, a plurality of semiconductor layers, a first conductive feature formed over the first epitaxy region and outside an oxide diffusion region, and a second conductive feature formed over the first epitaxy region and within the oxide diffusion region. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. The ESD structure further includes a third conductive feature formed over the second epitaxy region and outside the oxide diffusion region, and a fourth conductive feature formed over the second epitaxy region and within the oxide diffusion region. The first conductive feature is floating, and the second conductive feature is configured to couple a ground line or a power line to the first epitaxy region. A width between the first conductive feature and the oxide diffusion region is greater than or equal to a width between the third conductive feature and the oxide diffusion region.

In some embodiments, an electrostatic discharge (ESD) structure is provided. The ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, a junction region over the semiconductor substrate and between the first and second epitaxy regions, a first electrode formed over the first epitaxy region and outside an oxide diffusion region, a second electrode formed over the first epitaxy region and within the oxide diffusion region, a third electrode formed over the second epitaxy region and outside the oxide diffusion region, and a fourth electrode formed over the second epitaxy region and within the oxide diffusion region. An interface between the junction region and the semiconductor substrate is higher than an interface between the first epitaxy region and the semiconductor substrate. The first and third electrodes are longer than the second and fourth electrodes.

The foregoing outlines nodes of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.