Patent ID: 12218065

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG.1Ais a sectional view of a semiconductor package according to some example embodiments.FIG.1Bis an enlarged view of a portion A ofFIG.1A.FIG.1Cis an enlarged view of a portion B ofFIG.1A.

Referring toFIG.1A, the semiconductor package may include a base structure BS. The base structure BS may include lower pads110, a lower protective layer120, a wiring layer130, a substrate140, through vias150, upper pads160, and an upper protective layer170.

The substrate140may have the form of a plate extending along a plane defined by a first direction D1and a second direction D2. The first direction D1and the second direction D2may intersect each other. For example, the first direction D1and the second direction D2may perpendicularly intersect each other. In some embodiments, the substrate140may be a semiconductor substrate. For example, the substrate140may include silicon, germanium, silicon-germanium, GaP, or GaAs. In some embodiments, the substrate140may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The substrate140may be provided on the wiring layer130. The wiring layer130may be provided under the substrate140. The wiring layer130may include wirings, and an insulating layer surrounding the wirings. The wirings of the wiring layer130may include a conductive material. For example, semiconductor devices such as a memory device or a logic device may be provided between the substrate140and the wiring layer130. The wirings of the wiring layer130may be electrically connected to the semiconductor devices.

The wiring layer130may be provided on the lower protective layer120. The lower protective layer120may be provided under the wiring layer130. The lower protective layer120may function to protect the wiring layer130. The lower protective layer120may cover a bottom surface of the wiring layer130. The lower protective layer120may include an insulating material.

The upper protective layer170may be provided on the substrate140. The upper protective layer170may function to protect the substrate140. The upper protective layer170may cover a top surface of the substrate140. The upper protective layer170may include an insulating material.

The through via150may be electrically connected to the wiring of the wiring layer130while extending through the substrate140. The through via150may include a conductive material.

The lower pads110may be surrounded by the lower protective layer120. The lower pad110may be electrically connected to the wiring of the wiring layer130. The lower pads110may include a conductive material.

The upper pads160may be surrounded by the upper protective layer170. The upper pad160may be connected to the through via150. The upper pads160may include a conductive material.

Although the base structure BS has been shown and described as including the lower pads110, the lower protective layer120, the wiring layer130, the substrate140, the through vias150, the upper pads160, and the upper protective layer170, the structure of the base structure BS is not limited thereto. In some embodiments, the base structure BS may be a semiconductor chip structure including semiconductor devices. In some embodiments, the base structure BS may be an interposer.

Terminals TE may be provided under the base structure BS. The terminal TE may be connected to the lower pad110of the base structure BS. The terminals TE may include a conductive material.

A first semiconductor chip SC1, a second semiconductor chip SC2, a third semiconductor chip SC3, and a fourth semiconductor chip SC4may be sequentially provided over the base structure BS. The base structure BS, the first semiconductor chip SC1, the second semiconductor chip SC2, the third semiconductor chip SC3, and the fourth semiconductor chip SC4may be sequentially arranged in a third direction D3. The base structure BS and the first to fourth semiconductor chips SC1, SC2, SC3and SC4may overlap each other in the third direction D3. The third direction D3may intersect the first direction D1and the second direction D2. For example, the third direction D3may perpendicularly intersect the first direction D1and the second direction D2. For example, the first direction D1and the second direction D2may be horizontal directions, and the third direction D3may be a vertical direction. The fourth semiconductor chip SC4may be an uppermost semiconductor chip.

The base structure BS and the first semiconductor chip SC1may be spaced apart from each other in the third direction D3. The first semiconductor chip SC1and the second semiconductor chip SC2may be spaced apart from each other in the third direction D3. The second semiconductor chip SC2and the third semiconductor chip SC3may be spaced apart from each other in the third direction D3. The third semiconductor chip SC3and the fourth semiconductor chip SC4may be spaced apart from each other in the third direction.

Each of the first to fourth semiconductor chips SC1, SC2, SC3and SC4may include, for example, semiconductor devices such as a memory device or a logic device. The number of semiconductor chips SC1, SC2, SC3and SC4included in the semiconductor package is not limited to four.

Similar to the base structure BS, the first to third semiconductor chips SC1, SC2and SC3may include lower pads110, a lower protective layer120, a wiring layer130, a substrate140, through vias150, upper pads160, and an upper protective layer170. However, the structure of the first to third semiconductor chips SC1, SC2and SC3is not limited to the above-described structure. The fourth semiconductor chip SC4may include lower pads110, a lower protective layer120, a wiring layer130, and a substrate140. However, the structure of the fourth semiconductor chip SC4is not limited to the above-described structure.

The width of the base structure BS in the first direction D1may be greater than the widths of the first to fourth semiconductor chips SC1, SC2, SC3and SC4in the first direction D1.

Bumps BP may be provided. The bumps BP may be provided between the base structure BS and the first semiconductor chip SC1, between the first and second semiconductor chips SC1and SC2, between the second and third semiconductor chips SC2and SC3, or between the third and fourth semiconductor chips SC3and SC4. The bumps BP may be connected to the base structure BS and the first to fourth semiconductor chips SC1, SC2, SC3and SC4. The bumps BP may be connected to the lower pads110and, as such, may electrically interconnect the base structure BS and the first to fourth semiconductor chips SC1, SC2, SC3and SC4. The bumps BP may include a conductive material.

An adhesive layer AD may be provided over the base structure BS. The adhesive layer AD may bond the first to fourth semiconductor chips SC1, SC2, SC3and SC4and the base structure BS to one another. The adhesive layer AD may include a first interposition portion IN1interposed between the base structure BS and the first semiconductor chip SC1, a second interposition portion IN2interposed between the first and second semiconductor chips SC1and SC2, a third interposition portion IN3interposed between the second and third semiconductor chips SC2and SC3, a fourth interposition portion IN4interposed between the third and fourth semiconductor chips SC3and SC4, and a side portion SD connected to the first to fourth interposition portions IN1, IN2, IN3and IN4. Although the first to fourth interposition portions IN1, IN2, IN3and IN4and the side portion SD of the adhesive layer AD are described as being divided from one another, for convenience of description, the first to fourth interposition portions IN1, IN2, IN3and IN4and the side portion SD of the adhesive layer AD may be interconnected without having any boundary and, as such, may have an integrated structure. The number of interposition portions IN1, IN2, IN3and IN4included in the adhesive layer AD is not limited to four.

The first to fourth interposition portions IN1, IN2, IN3and IN4may be portions overlapping with the first to fourth semiconductor chips SC1, SC2, SC3and SC4in the third direction D3. The side portion SD may be a portion not overlapping with the first to fourth semiconductor chips SC1, SC2, SC3and SC4in the third direction D3. The side portion SD may contact side surfaces of the first to fourth semiconductor chips SC1, SC2, SC3and SC4. In some embodiments, the adhesive layer AD may include two side portions SD disposed at opposite sides of the first to fourth semiconductor chips SC1, SC2, SC3and SC4. In some embodiments, the adhesive layer AD may include one side portion SD surrounding the first to fourth semiconductor chips SC1, SC2, SC3and SC4.

The adhesive layer AD may include an adhesive polymer material. For example, the adhesive layer AD may include a non-conductive film (NCF).

A molding layer MD surrounding the base structure BS, the first to fourth semiconductor chips SC1, SC2, SC3and SC4and the adhesive layer AD may be provided. The molding layer MD may cover the base structure BS, the first to fourth semiconductor chips SC1, SC2, SC3and SC4and the adhesive layer AD. The molding layer MD may expose a top surface of the fourth semiconductor chip SC4.

The molding layer MD may include a polymer material. For example, the molding layer MD may include an epoxy molding compound (EMC). The coefficient of thermal expansion (CTE) of the molding layer MD may be different from the coefficient of thermal expansion of the adhesive layer AD. The coefficient of thermal expansion of the molding layer MD may be lower than the coefficient of thermal expansion of the adhesive layer AD. For example, the coefficient of thermal expansion of the molding layer MD may be 10 to 15 ppm/° C., and the coefficient of thermal expansion of the adhesive layer AD may be 35 to 40 ppm/° C.

Referring toFIG.1B, a top surface SD_1of the side portion SD of the adhesive layer AD may be curved. The top surface SD_1of the side portion SD may contact a side surface SC4_1of the fourth semiconductor chip SC4. The molding layer MD may include a curved surface MD_1contacting the top surface SD_1of the side portion SD. The curved surface MD_1of the molding layer MD may be curved to correspond to the top surface SD_1of the side portion SD.

An outer side surface SD_2of the side portion SD of the adhesive layer AD may extend in the third direction D3. For example, the outer side surface SD_2of the side portion SD may extend in the vertical direction. The outer side surface SD_2of the side portion SD may be flat. The level of the top surface SD_1of the side portion SD may gradually increase as the top surface SD_1extends from the side surface SC4_1of the fourth semiconductor chip SC4to the outer side surface SD_2of the side portion SD. A portion of the side portion SD, where the top surface SD_1and the outer side surface SD_2of the side portion SD intersect, may be an uppermost portion SD_3of the side portion SD. The level of the top surface SD_1of the side portion SD may gradually increase as the top surface SD_1extends from the side surface SC4_1of the fourth semiconductor chip SC4to the uppermost portion SD_3of the side portion SD. The uppermost portion SD_3of the side portion SD may be spaced apart from the side surface SC4_1of the fourth semiconductor chip SC4. The molding layer MD may include an inner side surface MD_2contacting the outer side surface SD_2of the side portion SD. The inner side surface MD_2of the molding layer MD may extend in the third direction D3. For example, the inner side surface MD_2of the molding layer MD may extend in the vertical direction. The inner side surface MD_2of the molding layer MD may be flat.

A top surface MD_3of the molding layer MD may be coplanar with a top surface SC4_2of the fourth semiconductor chip SC4. The level of the top surface MD_3of the molding layer MD may be equal to the level of the top surface SC4_2of the fourth semiconductor chip SC4.

The width of the side portion SD of the adhesive layer AD in the first direction D1may be defined as a first width W1. The distance in the first direction D1between the outer side surface SD_2of the side portion SD and the side surface of each of the first to fourth semiconductor chips SC1, SC2, SC3and SC4may be equal to the first width W1. For example, the distance in the first direction D1between the side surface SC4_1of the fourth semiconductor chip SC4and the outer side surface SD_2of the side portion SD may be equal to the first width W1, and the distance in the first direction D1between a side surface SC3_1of the third semiconductor chip SC3and the outer side surface SD_2of the side portion SD may be equal to the first width W1. For example, the first width W1may be 50 μm.

The distance in the first direction D1between the inner side surface MD_2of the molding layer MD and the side surface of each of the first to fourth semiconductor chips SC1, SC2, SC3and SC4may be equal to the first width W1. For example, the distance in the first direction D1between the side surface SC4_1of the fourth semiconductor chip SC4and the inner side surface MD 2 of the molding layer MD may be equal to the first width W1, and the distance in the first direction D1between the side surface SC3_1of the third semiconductor chip SC3and the inner side surface MD_2of the molding layer MD may be equal to the first width W1.

The width of the base structure BS in the first direction D1may be equal to a value obtained by adding double the first width W1to the width in the first direction D1of any one of the first to fourth semiconductor chips SC1, SC2, SC3and SC4.

The inner side surface SD_4of the side portion SD of the adhesive layer AD may contact the side surfaces of the first to fourth semiconductor chips SC1, SC2, SC3and SC4. For example, the inner side surface SD_4of the side portion SD may contact the side surface SC4_1of the fourth semiconductor chip SC4and the side surface SC3_1of the third semiconductor chip SC3. The first to fourth interposition portions IN1, IN2, IN3and IN4of the adhesive layer AD may be connected to the inner side surface SD_4of the side portion SD.

Referring toFIG.1C, the inner side surface MD_2of the molding layer MD may contact a side surface BS_1of the base structure BS. The entire the side surface BS_1of the base structure BS may contact the inner side surface MD_2of the molding layer MD.

The outer side surface SD_2of the side portion SD may be coplanar with the side surface BS_1of the base structure BS. The outer side surface SD_2of the side portion SD may overlap with the side surface BS_1of the base structure BS in the third direction D3.

An outer portion BS_2of the top surface of the base structure BS contacting a bottom surface SD_5of the side portion SD may be defined. The side portion SD may overlap with the outer portion BS_2of the top surface of the base structure BS in the third direction D3. The entirety of the outer portion BS_2of the top surface of the base structure BS may contact the bottom surface SD_5of the side portion SD. The outer portion BS_2of the top surface of the base structure BS may be a portion connected to the side surface BS_1of the base structure BS. The outer portion BS_2of the top surface of the base structure BS may be a portion of the top surface of the base structure BS defined at an outermost side.

A triple point, at which the side portion SD of the adhesive layer AD, the molding layer MD and the base structure BS are in contact, may be a point at which the outer surface SD_2and the bottom surface SD_5of the side portion SD are interconnected, and may be a point at which the side surface BS_1and the outer portion BS_2of the top surface of the base structure BS are interconnected.

The bottom surface MD_4of the molding layer MD may be coplanar with a bottom surface BS_3of the base structure BS. The bottom surface MD_4of the molding layer MD may overlap with the bottom surface BS_3of the base structure BS in the first direction D1The level of the bottom surface MD_4of the molding layer MD may be equal to the level of the bottom surface BS_3of the base structure BS.

In the semiconductor package according to example embodiments, the width of the side portion SD of the adhesive layer AD may be relatively small. Accordingly, the size of the adhesive layer AD, which has a relatively high coefficient of thermal expansion, may be relatively small and, as such, warpage caused by thermal expansion may be minimized.

In the semiconductor package according to some example embodiments, the triple point, at which the molding layer MD, the adhesive layer AD and the base structure BS are in contact, may be disposed between the outer portion BS_2of the top surface of the base structure BS and the side surface BS_1of the base structure BS. Accordingly, even when torsion is generated at the semiconductor package, no stress may be concentrated at the triple point and, as such, formation of a crack among the molding layer MD, the adhesive layer AD and the base structure BS may be limited and/or prevented.

FIGS.2A,2B,2C,2D,2E and2Fare sectional views explaining a method for manufacturing a semiconductor package in accordance with some example embodiments.

Referring toFIG.2A, a first glue layer300may be formed on a first carrier substrate200, and a preliminary base structure pBS may be attached to the first glue layer300. The preliminary base structure pBS may include lower pads, a lower protective layer, a wiring layer, a substrate, through vias, upper pads, and an upper protective layer. Terminals TE connected to the preliminary base structure pBS may be formed before attachment of the preliminary base structure pBS to the first glue layer300. For example, the first glue layer300may include an acrylic polymer.

First semiconductor chips SC1, second semiconductor chips SC2, third semiconductor chips SC3, fourth semiconductor chips SC4, bumps BP, and preliminary adhesive layers pAD may be formed over the preliminary base structure pBS. First partial adhesive layers (not shown) may be respectively formed under the first semiconductor chips SC1, to which bumps BP are connected, and the first partial adhesive layers may then be attached to the preliminary base structure pBS. Second partial adhesive layers (not shown) may be respectively formed under the second semiconductor chips SC2, to which bumps BP are connected, and the second partial adhesive layers may then be attached to the first semiconductor chips SC1, respectively. Third partial adhesive layers (not shown) may be respectively formed under the third semiconductor chips SC3, to which bumps BP are connected, and the third partial adhesive layers may then be attached to the second semiconductor chips SC2, respectively. Fourth partial adhesive layers (not shown) may be respectively formed under the fourth semiconductor chips SC4, to which bumps BP are connected, and the fourth partial adhesive layers may then be attached to the third semiconductor chips SC3, respectively.

In an attachment process of the first to fourth partial adhesive layers, the shapes of the first to fourth partial adhesive layers may be deformed and, as such, the first to fourth partial adhesive layers may be merged. A merged structure of the first to fourth partial adhesive layers may be defined as a preliminary adhesive layer pAD. The preliminary adhesive layer pAD may be curved at a top surface pAD_1and an outer side surface pAD_2thereof.

Referring toFIG.2B, a first sawing process may be performed. For example, the first sawing process may be a blade sawing process. The first sawing process may include cutting the preliminary adhesive layers pAD and the preliminary base structure pBS. The preliminary adhesive layer pAD and the preliminary base structure pBS may be simultaneously cut through one process.

As the preliminary adhesive layers pAD are cut, adhesive layers AD may be formed. Outer side surfaces of the adhesive layers AD may be flat. As the preliminary base structure pBS is cut, base structures BS may be formed. The preliminary base structure pBS may be separated into a plurality of base structures BS. The preliminary adhesive layer pAD and the preliminary base structure pBS may be cut such that the outer side surface of the adhesive layer AD is coplanar with a side surface of the base structure BS.

Referring toFIG.2C, the base structures BS and the terminals TE may be detached from the first glue layer300on the first carrier substrate200. Thereafter, the detached base structures BS and terminals TE may be attached to a second glue layer500on a second carrier substrate400. A bottom surface of the base structure BS may contact a top surface of the second glue layer500. The first to fourth semiconductor chips SC1, SC2, SC3and SC4, the adhesive layers AD and the bumps BP may be disposed over the second carrier substrate400and the second glue layer500.

Referring toFIG.2D, a preliminary molding layer pMD may be formed on the second glue layer500. The preliminary molding layer pMD may surround the base structures BS, the first to fourth semiconductor chips SC1, SC2, SC3and SC4, and the adhesive layers AD. A bottom surface of the preliminary molding layer pMD may contact the top surface of the second glue layer500.

Referring toFIG.2E, an upper portion of the preliminary molding layer pMD may be removed. For example, the upper portion of the preliminary molding layer pMD may be removed by a grinding process. As the upper portion of the preliminary molding layer pMD is removed, top surfaces of the fourth semiconductor chips SC4(that is, uppermost semiconductor chips) may be exposed.

Referring toFIG.2F, a second sawing process may be performed. For example, the second sawing process may be a blade sawing process. The second sawing process may include cutting the preliminary molding layer pMD. As the preliminary molding layer pMD is cut, molding layers MD may be formed. The preliminary molding layer pMD may be separated into a plurality of molding layers MD. A bottom surface of the molding layer MD may contact the top surface of the second glue layer500. After formation of the molding layers MD, the base structure BS and the molding layers MD may be detached from the second glue layer500on the second carrier substrate400.

In the semiconductor package manufacturing method according to example embodiments, the adhesive layer AD, which has a flat outer side surface, may be formed by cutting the preliminary adhesive layer pAD. Accordingly, it may be possible to limit and/or prevent the adhesive layer AD from being exposed in a process of cutting the preliminary molding layer pMD and, as such, formation of a crack caused by an exposed adhesive layer AD may be limited and/or prevented.

FIG.3is an enlarged sectional view of a portion of a semiconductor package according to some embodiments.

Referring toFIG.3, an adhesive layer ADa of the semiconductor package may include a side portion SDa. A top surface SDa_1of the side portion SDa may contact a side surface USCa_1of an uppermost semiconductor chip USCa. The top surface SDa_1of the side portion SDa may be defined between the side surface USCa_1of the uppermost semiconductor chip USCa and an outer side surface SDa_2of the side portion SDa.

The level of the top surface SDa_1of the side portion SDa may gradually increase as the top surface SDa_1extends from the side surface USCa_1of the uppermost semiconductor chip USCa to an uppermost portion SDa_3of the side portion SDa. The level of the top surface SDa_1of the side portion SDa may be gradually lowered as the top surface SDa_1extends from the uppermost portion SDa_3of the side portion SDa to the outer side surface SDa_2of the side portion SDa. The uppermost portion SDa_3of the side portion SDa may be a portion of the top surface SDa_1of the side portion SDa.

FIG.4is a sectional view of a semiconductor package according to some example embodiments.

Referring toFIG.4, the semiconductor package may include a base structure BSb, and semiconductor chips SCb disposed over the base structure BSb. Although the number of semiconductor chips SCb is shown as being eight, example embodiments are not limited thereto. An adhesive layer ADb, which is disposed on the base structure BSb while surrounding the semiconductor chips SCb, may be provided. A molding layer MDb, which surrounds the base structure BSb, the semiconductor chips SCb and the adhesive layer ADb, may be provided.

FIG.5is a sectional view of a semiconductor package according to some example embodiments.

Referring toFIG.5, the semiconductor package may include a package substrate600. For example, the package substrate600may be a printed circuit board (PCB). First terminals610electrically connected to the package substrate600may be provided. The semiconductor package may be mounted on an external device (for example, a main board) via the first terminals610.

An interposer700may be provided over the package substrate600. Second terminals710electrically interconnecting the package substrate600and the interposer700may be provided. The second terminals710may be provided between the package substrate600and the interposer700.

A processor chip800may be provided over the interposer700. For example, the processor chip800may be a graphics processing unit (GPU) or a central processing unit (CPU). Third terminals810electrically interconnecting the processor chip800and the interposer700may be provided. The third terminals810may be provided between the processor chip800and the interposer700.

A base structure BSc and semiconductor chips SCc may be provided over the interposer700. The base structure BSc and the semiconductor chips SCc may be spaced apart from the processor chip800in a first direction D1. Fourth terminals TEc electrically interconnecting the base structure BSc and the interposer700may be provided. The fourth terminals TEc may be provided between the base structure BSc and the interposer700.

An adhesive layer ADc surrounding the semiconductor chips SCc may be provided over the base structure BSc. A first molding layer MD1csurrounding the base structure BSc, the semiconductor chips SCc and the adhesive layer ADc may be provided.

A second molding layer MD2csurrounding the interposer700, the processor chip800, the base structure BSc and the semiconductor chips SCc may be provided over the package substrate600. The second molding layer MD2cmay include the same material as the first molding layer MD1c. In some embodiments, an underfill layer may be provided in at least one of a region between the package substrate600and the interposer700, a region between the processor chip800and the interposer700or a region between the base structure BSc and the interposer700.

A semiconductor package according to some example embodiments may limit and/or prevent formation of a crack caused by concentration of stress and, as such, reliability of the semiconductor package may be enhanced.

One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

While some example embodiments have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of inventive concepts and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.