Patent ID: 12243787

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1Aillustrates a top schematic view of a wafer in accordance with some embodiments of the present disclosure.FIG.1Billustrates a top schematic view of a mask in accordance with some embodiments of the present disclosure.

Reference is made toFIG.1A. Shown there is a semiconductor wafer10. The semiconductor wafer10may be held by a wafer holder or a chuck during processing the semiconductor wafer10. In some embodiments, the semiconductor wafer10includes a semiconductor material, such as silicon. In other embodiments, the semiconductor wafer10may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. In some embodiments, the semiconductor wafer100may be a p-type semiconductor substrate (acceptor type) or an n-type semiconductor substrate (donor type).

Reference is made toFIG.1B. Shown there is a mask20. In some embodiments, the mask20is a reflective mask. For example, the mask20includes a mask image region21and a mask frame region22. The mask image region21is an area of the mask20that includes a pattern (or design) of a layer of an integrated circuit device. The mask frame region22is an area of the mask20that does not include the pattern of the layer of the integrated circuit device. The mask frame region22may include alignment marks (also referred to as fiducial marks). The mask frame region22surrounds the mask image region21, defining the mask image region21of the mask20.

The mask20is used to transfer the pattern of the mask image region21to a wafer, such as the wafer10as shown inFIG.1A. In some embodiments where the mask20is a phase shift mask, the mask20may include absorptive regions, which absorb light incident thereon, and reflective regions, which reflect light incident thereon. The reflective regions can be configured to reflect light incident thereon with a phase different than light reflected by the reflective regions, such that resolution and image quality of the pattern transferred to the wafer10can be enhanced. The reflective and absorptive regions of the mask20are patterned such that light reflected from the reflective regions (and, in some cases, the absorptive regions) projects onto the wafer10and transfers the pattern of the mask image region21of the mask20to the wafer10. For example, during an exposure process, light (radiation) is projected onto the mask20, and a portion of the light is transmitted to the wafer10, thereby transferring the pattern of the mask image region21to the wafer10. In some embodiments, the wafer10is exposed to extreme ultraviolet (EUV) radiation (light) using the mask20.

The mask image region21can be transferred to the wafer10multiple times using multiple exposures with the mask20. For example, as shown inFIG.1A, the mask20ofFIG.1Bis used in multiple exposure processes to pattern the wafer10, such that the pattern of the mask image region21is transferred to various fields12of the wafer10. Each field12corresponds to at least one chip or die. Here, the field12can also be referred to as an exposure field, which represents an area of the wafer10that will undergo each exposure process in a given time. For example, an exposure tool (such as a stepper or a scanner) processes one field (such as exposing a field12of the wafer10by the mask20), then processes the next field (such as exposing another field12of the wafer10by the mask20), and so on. In some embodiments, the wafer10may include a resist layer disposed over a substrate, where the pattern of the mask image region21is transferred to the resist layer.

FIG.1Cis a schematic view of field12ofFIG.1Ain accordance with some embodiments of the present disclosure. In greater details,FIG.1Cis an enlarged view of region D1as shown inFIG.1A. In some embodiments, each field12includes one die region31(or chip region31). The area of each die region31is defined by a plurality of first scribe line regions SL1and second scribe line regions SL2. In some embodiments, the first scribe line regions SL1extend along a first direction and the second scribe line regions SL2extend along a second direction that is perpendicular to the first direction. After the fabrication and testing processes for the die region31are completed, the die region31will be singulated into individual die through the first scribe line regions SL1and the second scribe line regions SL2.

A plurality of testing pads32are formed on the wafer10in the first scribe line regions SL1and second scribe line regions SL2, and surround the die region31. Here, the testing pads32may be exposed conductive pads of topmost layer of testing patterns, which will be discussed later. In some embodiments, during the semiconductor fabrication process, every processing step is performed across the wafer10, so that testing pattern, which is made by the same processes as those for fabricating the semiconductor devices (or integrated circuits) in the die region31, are also formed in the first scribe line regions SL1and the second scribe line regions SL2. Because the fabrication instructions and environments for forming the semiconductor devices in the die region31and the testing pattern are nearly the same, a defect found in the testing pattern is likely to be found in the semiconductor devices in the die region31. As a result, the testing pattern is suitable for serving as an indicator of the fabricating process condition before a thorough testing is conducted. The design parameters of the testing pattern may be determined as reflecting the electrical performance of the semiconductor devices in the die region31fabricated on the wafer10.

FIG.1Dis a schematic view of field12ofFIG.1Ain accordance with some embodiments of the present disclosure. In greater details,FIG.1Dis an enlarged view of region D1as shown inFIG.1A.FIG.1Dis different fromFIG.1C, in that each field12includes a plurality of die regions33A,33B,33C,33D. For example, shown there are four die regions33A,33B,33C,33D arranged in a 2×2 matrix. However, the number of die regions33in each field12is not limited thereto. Each field12may include more or less die regions in other embodiments. In some embodiments, the die regions33A,33B,33C,33D may be the same, or may be different. For example, the die regions33A,33B,33C,33D may include the same semiconductor devices having the same circuit function, or may include different same semiconductor devices with different circuit functions. The die regions33A,33B,33C,33D in each field12are separated by a plurality of first scribe line regions SL1and second scribe line regions SL2. In some embodiments, the first scribe line regions SL1extend along a first direction and the second scribe line regions SL2extend along a second direction that is perpendicular to the first direction. After the fabrication and testing processes for the die regions33A,33B,33C,33D are completed, the die regions33A,33B,33C,33D will be singulated into individual dies through the first scribe line regions SL1and the second scribe line regions SL2.

A plurality of testing pads34A,34B,34C,34D are formed on the wafer10in the first scribe line regions SL1and second scribe line regions SL2, and surround the die regions33A,33B,33C,33D, respectively. For example, the testing pads34A are disposed in the first scribe line regions SL1and second scribe line regions SL2and surround the die regions33A, the testing pads34B are disposed in the first scribe line regions SL1and second scribe line regions SL2and surround the die regions33B, the testing pads34C are disposed in the first scribe line regions SL1and second scribe line regions SL2and surround the die regions33C, and the testing pads34D are disposed in the first scribe line regions SL1and second scribe line regions SL2and surround the die regions33D.

With respect to the segment of the first scribe line region SL1between the die regions33A and33C, testing pads34A and34C are alternately arranged in the first direction along the segment of the first scribe line region SL1between the die regions33A and33C. With respect to the segment of the first scribe line region SL1between the die regions33B and33D, testing pads34B and34D are alternately arranged in the first direction along the segment of the first scribe line region SL1between the die regions33B and33D.

On the other hand, with respect to the segment of the second scribe line region SL2between the die regions33A and33B, testing pads34A and34B are alternately arranged in the second direction along the segment of the second scribe line region SL2between the die regions33A and33B. With respect to the segment of the second scribe line region SL2between the die regions33C and33D, testing pads34A and34B are alternately arranged in the second direction along the segment of the second scribe line region SL2between the die regions33C and33D.

As mentioned above, the die regions33A,33B,33C, and33D may include different semiconductor devices with different circuit functions. Furthermore, the testing pads34A,34B,34C, and34D are exposed conductive pads of the testing patterns associated with the die regions33A,33B,33C, and33D. In some embodiments, during the semiconductor fabrication process, every processing step is performed across the wafer10, so that testing patterns, which are made by the same processes as those for fabricating the semiconductor devices (or integrated circuits) in the die regions33A,33B,33C, and33D, are also formed in the first scribe line regions SL1and the second scribe line regions SL2. Because the fabrication instructions and environments for forming the semiconductor devices in the die regions33A,33B,33C, and33D and the corresponding testing patterns associated with the die regions33A,33B,33C, and33D are nearly the same, defects found in the testing patterns are likely to be found in the semiconductor devices in the die regions33A,33B,33C, and33D. As a result, the testing patterns are suitable for serving as indicators of the fabricating process condition before a thorough testing is conducted. The design parameters of the testing patterns associated with the die regions33A,33B,33C, and33D may be determined as reflecting the electrical performance of the semiconductor devices in the die regions33A,33B,33C, and33D fabricated on the wafer10.

FIG.2illustrates a method M1for testing a wafer in accordance with some embodiments of the present disclosure. Although the method M1is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

Reference is made toFIGS.2and3. The method M1begins at block S101, in which integrated circuits and testing patterns are formed over a wafer. As shown inFIG.3, a wafer100is provided. The wafer100may be similar to the wafer10as discussed inFIGS.1A to1D. In some embodiments, the wafer100may include a substrate102. Generally, the substrate102may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulator layer below a thin semiconductor layer that is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include the crystalline semiconductor material silicon, but may include one or more other semiconductor materials such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs and the like), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like) or combinations thereof. The semiconductor materials may be doped or undoped. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

The layers and/or structures of the discussed below can be formed by several photolithography processes. In some embodiments, layers may be deposited blanket over the substrate102, and then be patterned, for example, by using the mask20as discussed inFIG.1B. For example, a material layer may be deposited over the substrate102. Then, a photoresist is formed over the material layer. An exposure process is performed by projecting light (radiation) onto a mask (e.g., the mask20ofFIG.1B), and a portion of the light is transmitted to the photoresist. In some embodiments, the exposure process is performed to an exposure field (e.g., the field12ofFIG.1A) over the wafer once a time. After the exposure process performed to a field is completed, another exposure process is then performed to another field over the wafer. Once all fields over the wafer undergo the exposure processes, the photoresist across the wafer are exposed. The photoresist is then patterned based on the pattern transmitted from the mask via a development process. Afterwards, the material layer is etched by using the patterned photoresist as an etch mask. As a result, the pattern of the mask is transferred to the material layer.

Semiconductor devices112and114are formed over the substrate102. Furthermore, testing semiconductor devices116and118are formed over the substrate102. In some embodiments, the semiconductor devices112and114are formed over a die region102A of the substrate102, while the testing semiconductor devices116and118are formed over a scribe line region102B over the substrate102. Here, the die region102A may be similar to the die region31as described inFIG.1C, or may be similar to the die regions33A to33D as described inFIG.1D. The scribe line region102B may be similar to the scribe line regions SL1, SL2as described inFIGS.1C and1D.

Isolation regions105are formed in the substrate102. In some embodiments, the isolation regions may separate the semiconductor devices112and114from each other, and may separate the testing semiconductor devices116and118from each other. Each of the isolation regions105may be formed by recessing the substrate102to form trenches, and then depositing one or more dielectric materials (e.g., silicon oxide) to fill the trenches. The dielectric materials of the isolation regions105may be deposited using a high density plasma chemical vapor deposition (HDP-CVD), a low-pressure CVD (LPCVD), sub-atmospheric CVD (SACVD), a flowable CVD (FCVD), spin-on, and/or the like, or a combination thereof. After the deposition, an anneal process or a curing process may be performed.

In some embodiments, the semiconductor devices112and114each may include a gate structure120and source/drain regions122on opposite sides of the gate structure120. On the other hand, the testing semiconductor device116includes a gate structure130and source/drain regions132on opposite sides of the gate structure130. Furthermore, the testing semiconductor device118includes a gate structure140and source/drain regions142on opposite sides of the gate structure140. Gate spacers124are formed on opposite sidewalls of the gate structures120,130, and140, respectively.

In some embodiments, the gate structures120,130, and140are high-k, metal gate (HKMG) gate structures that may be formed using a gate-last process flow. In a gate last process flow, sacrificial dummy gate structures (not shown) is formed after forming the isolation regions105. The dummy gate structures each may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, or the like) may be deposited. Next a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, or the like) may be deposited over the dummy gate dielectric and then planarized (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, or the like) may be formed over the dummy gate material. The dummy gate structures are then formed by patterning the hard mask and transferring that pattern to the dummy gate dielectric and dummy gate material using suitable photolithography and etching techniques. As described in greater detail below, the dummy gate structures may be replaced by the HKMG gate structures120,130, and140, respectively. In some embodiments, the gate structures120,130, and140each may include a gate dielectric and a gate metal over the gate dielectric. The materials used to form the dummy gate structure and hard mask may be deposited using any suitable method such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD) or the like, or by thermal oxidation of the semiconductor surface, or combinations thereof.

Gate spacers124may be formed by deposition and anisotropic etch of a spacer dielectric layer performed after the dummy gate patterning is complete. The spacer dielectric layer may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof. The anisotropic etch process removes the spacer dielectric layer from over the top of the dummy gate structures leaving the spacers124along the sidewalls of the dummy gate structures.

Source and drain regions122,132, and142are semiconductor regions over the substrate102. In some embodiments, the source and drain regions122,132, and142may be doped regions. Generally, the heavily-doped regions are spaced away from the dummy gate structures using the spacers124, and may be formed, for example, by implanting dopants (e.g., As, P, B, In, or the like) using an ion implantation process. The source and drain regions122,132, and142may also be epitaxially grown regions. For example, after forming the spacers124, the source and drain regions122,132, and142may be formed by first etching the substrate102to form recesses, and then depositing a crystalline semiconductor material in the recess by a selective epitaxial growth (SEG) process that may fill the recess. The crystalline semiconductor material may be elemental (e.g., Si, or Ge, or the like), or an alloy (e.g., Si1-xCx, or Si1-xGex, or the like). The SEG process may use any suitable epitaxial growth method, such as e.g., vapor/solid/liquid phase epitaxy (VPE, SPE, LPE), or metal-organic CVD (MOCVD), or molecular beam epitaxy (MBE), or the like.

Interconnection structure148is formed over the substrate102and over the semiconductor devices112and114and the testing semiconductor devices116and118. The interconnect structure148may include one or more layers of conductive features150formed in one or more stacked dielectric layers160. Each of the stacked dielectric layers160may include a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. The dielectric layers160may be deposited using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like.

Conductive features150may include conductive lines154and conductive vias152interconnecting the layers of conductive lines154. The conductive vias152may extend through respective ones of the dielectric layers160to provide vertical connections between layers of conductive lines154. Here, the term “conductive vias” may be the structure in the conductive features150having longest dimensions extending vertically, and the term “conductive lines” may be the structure in the conductive features150having longest dimensions extending laterally. The conductive features150may be formed through any acceptable process, such as, a damascene process, a dual damascene process, or the like.

In some embodiments, the conductive lines154and the conductive vias152may be made of Al, Si, Cu, Ti, Ta, N, O, C, Ni, Co, W, or the like. In some embodiments, the dielectric layers160may be made of silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. In some embodiments, the dielectric layers160may include porous structure. In some embodiments, the dielectric layers160may include an etch stop layer made of SiN, SiCN, SiC, SiOCN, or the like.

For example, the conductive features150may be formed using a damascene process in which a respective dielectric layer160is patterned utilizing a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of the conductive features150. An optional diffusion barrier and/or optional adhesion layer may be deposited and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer includes titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the conductive features150may be formed by depositing a seed layer of copper or a copper alloy, and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the respective dielectric layer160and to planarize the surface for subsequent processing.

In some embodiments, the topmost layer of the conductive lines154may include exposed conductive pads172,174,176, and178. For example, the conductive pad172is electrically connected to semiconductor device112through the underlying layers of the conductive features150. The conductive pad174is electrically connected to semiconductor device114through the underlying layers of the conductive features150. The conductive pad176is electrically connected to the testing semiconductor device116through the underlying layers of the conductive features150. The conductive pad178is electrically connected to the testing semiconductor device118through the underlying layers of the conductive features150.

In some embodiments, the semiconductor devices112,114, and their overlying conductive features150can be collectively referred to as an integrated circuit180. The integrated circuit180is disposed within the die region102A of the substrate102. That is, after the manufacturing process, a singulation process may be performed to singulate the die region102A of the substrate102into individual die through the scribe line region102B of the substrate102.

As mentioned above, the testing semiconductor devices116and118are formed in scribe line region102B over the substrate102of the wafer100. Furthermore, the fabrication instructions and environments for forming the semiconductor devices112and114, and the testing semiconductor devices116and118are nearly the same, defects found in the semiconductor devices112and114are likely to be found in the testing semiconductor devices116and118. As a result, during a testing process, the testing semiconductor devices116and118are suitable for serving as indicators of the fabricating process condition. The design parameters of the testing semiconductor devices116and118may be determined as reflecting the electrical performance of the semiconductor devices112and114.

The conductive pads176and178are connected to the testing semiconductor devices116and118, respectively, and the conductive pads176and178may be functioned as testing pads during a testing process discussed in following steps. Accordingly, the conductive pads176and178may also be referred to as testing pads176and178, respectively. The testing semiconductor device116and its overlying conductive features150, which include the conductive pad176, may be collectively referred to as a testing pattern192. Furthermore, the testing semiconductor device118and its overlying conductive features150, which include the conductive pad178, may be collectively referred to as a testing pattern194. In some embodiments, the testing pads176and178may be similar to the testing pad32as described inFIG.1C, or may be similar to the testing pads34A-34D as described inFIG.1D.

In some embodiments, the testing semiconductor devices116and118may be the same. That is, the testing semiconductor devices116and118may be formed with the same fabrication process as the semiconductor devices112and114, and may include substantially the same electrical properties and/or electrical functionalities as the semiconductor devices112and114. As a result, by performing a testing process to the testing semiconductor devices116and118, the electrical performance of the semiconductor devices112and114can be determined.

However, in some other embodiments, the testing semiconductor devices116and118are different. For example, the testing semiconductor device116may be formed with the same fabrication process as the semiconductor devices112and114within the die region102A of the substrate102, and may include substantially the same electrical properties and/or electrical functionalities as the semiconductor devices112and114. On the other hand, the testing semiconductor device118may be formed with a different fabrication process, which is used to fabricate other semiconductor devices within other die region of the substrate102. As a result, the testing pad176may be associated with the semiconductor devices112and114within the die region102A of the substrate102, while the testing pad178may be associated with the other semiconductor devices within other die region of the substrate102. For example, if the testing pad176is the testing pad34A as described inFIG.1D, the testing pad178may be one of the testing pads34B,34C, and34D as described inFIG.1D. Stated another way, the testing pads176and178are associated with different semiconductor devices.

Referring back toFIG.2, the method M1proceeds to block S102, in which a testing module is picked up. Reference is made toFIG.4A, shown there is a schematic view of a testing module200.FIGS.4B,4C, and4Dare cross-sectional views of the testing module200in accordance with some embodiments of the present disclosure. In greater details,FIGS.4B,4C, and4Dillustrate different examples of cross-sectional views of region D2of the testing module200ofFIG.4A.

The testing module200is picked up by a gripper600. In some embodiments, the gripper600may include suitable type of effector used for grasping or holding an object, such as the testing module200. For example, the effector may be a pressure gripper (e.g., gripping by applying pressure to an object, such as with a pincer type motion), an envelope gripper (e.g., gripping by surrounding an object to be manipulated), a vacuum gripper (e.g., gripping by suction force), and a magnetic gripper (e.g., gripping by use of electromagnetic forces).

In some embodiments, the testing module200is a die and/or a chip, and can also be referred to as a testing die and/or a testing chip, which is formed by a semiconductor fabrication process, and may include semiconductor materials. Reference is made toFIG.4B. The testing module200may include a substrate202. The substrate202may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulator layer below a thin semiconductor layer that is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include the crystalline semiconductor material silicon, but may include one or more other semiconductor materials such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs and the like), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like) or combinations thereof. The semiconductor materials may be doped or undoped. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates. In some other embodiments, the substrate202may also include molding compound, polyimide, resin, composite insulation film, or the like.

The testing module200further includes a first semiconductor device212and a second semiconductor device214over the substrate202. In some embodiments, the first semiconductor device212and the second semiconductor device214are transistors, and can also be referred to as a first transistor212and a second transistor214, respectively. In some embodiments, the first semiconductor device212may be different from the second semiconductor device214. For example, the first semiconductor device212may be an N-type device, while the second semiconductor device214may be a P-type device, and vice versa.

In some embodiments, the first semiconductor device212may include a gate structure222and source and drain regions232on opposite sides of the gate structure222. The second semiconductor devices214may include a gate structure224and source and drain regions234on opposite sides of the gate structure224. Gate spacers240are disposed on opposite sidewalls of the gate structures222and224, respectively.

The gate structure222of the first semiconductor device212includes a gate dielectric222A and a gate metal222B over the gate dielectric222A. Similarly, the gate structure224of the second semiconductor device214includes a gate dielectric224A and a gate metal224B over the gate dielectric224A.

In some embodiments, the gate dielectrics222A and224A may include silicon oxide (SiO2). In some embodiments, the gate dielectrics222A and224A may include high-k dielectric materials, such as metal oxides, transition metal-oxides, or the like. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or other applicable dielectric materials.

In some embodiments, the gate metals222B and224B may include a work function metal layer and a filling metal. The work function metal layer may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. The filling metal may include tungsten (W), aluminum (Al), copper (Cu), or another suitable conductive material(s).

In some embodiments, the gate spacers240may be formed of silicon oxide, silicon nitride, silicon oxynitride, combinations thereof. In some embodiments, the source and drain regions232and234may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material, and may be doped with N-type dopants or P-type dopants. In some embodiments, the source/drain regions232and234are epitaxially grown over the substrate202, and may also be referred to as source/drain epitaxial structures.

Although the embodiments ofFIG.4Billustrate one first semiconductor device212and one second semiconductor device214, the present disclosure is not limited thereto. In some other embodiments, the testing module200may include a plurality of first semiconductor devices212and a plurality of second semiconductor devices214. In such embodiments, the group of the first semiconductor devices212may collectively perform a certain function, while the group of the second semiconductor devices214may collectively perform a certain function.

The testing module200further includes an interconnection structure248over the substrate202, and over the first semiconductor device212and the second semiconductor device214. The interconnect structure248may include one or more layers of conductive features250formed in one or more stacked dielectric layers260. Each of the stacked dielectric layers260may include a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like.

Conductive features250may include conductive lines254and conductive vias252interconnecting the layers of conductive lines254. The conductive vias252may extend through respective ones of the dielectric layers260to provide vertical connections between layers of conductive lines254. In some embodiments, the conductive lines254and the conductive vias252may be made of Al, Si, Cu, Ti, Ta, N, O, C, Ni, Co, W, or the like. In some embodiments, the dielectric layers260may be made of silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. In some embodiments, the dielectric layers260may include porous structure. In some embodiments, the dielectric layers260may include an etch stop layer made of SiN, SiCN, SiC, SiOCN, or the like.

The testing module200further includes a plurality of conductive vias272and274extending through the substrate202. In some embodiments where the substrate202is made of silicon, the vias272and274can be referred to as through-silicon-vias (TSVs). The vias272and274extend into the interconnection structure248, and may be in contact with corresponding conductive vias254of the conductive features250. In some other embodiments, the vias272and274may be in contact with corresponding conductive lines252of the conductive features250. In some embodiments, the vias272and274may be made of Al, Si, Cu, Ti, Ta, N, O, C, Ni, Co, W, or the like.

In some embodiments, the width of the conductive vias272and274may be in a range from about 3 μm to about 40 μm. In some embodiments, the conductive vias272and274may include circular top-view profiles, and the diameter of the conductive vias272and274may be in a range from about 3 μm to about 40 μm.

The vias272and274have top surfaces higher than the top surface of the gate structure222of the first semiconductor device212and the top surface of the gate structure222of the first semiconductor device212. The vias272and274protrude from the bottom surface of the substrate202. That is, the bottom surfaces of the vias272and274are lower than the bottom surface of the substrate202. Furthermore, the top surfaces of the vias272and274are higher than the top surface of the substrate202.

The testing module200further includes a guard ring structure258. In some embodiments, the guard ring structure258is a portion of the conductive features250that is laterally between the conductive vias272and274. For example, the guard ring structure258includes a plurality of conductive lines254and conductive vias242interconnecting the layers of conductive lines254. The guard ring structure258can prevent crosstalk issue between the conductive vias272and274. In some embodiments, the bottommost surface of the guard ring structure258is higher than the top surface of the substrate202, and is higher than the bottom surface of the conductive vias272and274.

Reference is made toFIG.4C. Some elements ofFIG.4Care similar to those ofFIG.4B, such elements are labeled the same, and thus relevant details will not be repeated for brevity.FIG.4Cis different fromFIG.4B, in that the first semiconductor device212and the second semiconductor device214ofFIG.4Bare omitted inFIG.4C. That is, the testing module ofFIG.4Cis free of semiconductor devices (or transistors).

Reference is made toFIG.4D. Some elements ofFIG.4Dare similar to those ofFIG.4B, such elements are labeled the same, and thus relevant details will not be repeated for brevity.FIG.4Dis different fromFIG.4B, in that the bottom surfaces of the vias272and274are substantially level with the bottom surface of the substrate202. Furthermore, the testing module ofFIG.4Dincludes conductive pads282and284disposed on the bottom surface of the substrate202, and in contact with the vias272and274, respectively. In some embodiments, the conductive pads282and284may be made of Al, Si, Cu, Ti, Ta, N, O, C, Ni, Co, W, or the like. Although semiconductor devices212and214ofFIG.4Bare omitted inFIG.4D, while the semiconductor devices212and214ofFIG.4Bmay also presents in the embodiments ofFIG.4D.

Referring back toFIG.2, the method M1proceeds to block S103, in which the testing module is aligned to a testing target of the wafer. Reference is made toFIG.5A, the gripper600move the testing module200to a position above the wafer10. Then, the testing module200is aligned to a testing target of the wafer10. Here, the testing target may be the semiconductor devices (or integrated circuit) in a die region and testing pads of the testing patterns around the die region as described above. During the alignment process, the testing module200may be moved, by the gripper600, to a position vertically overlaps the field12of the wafer10. In such embodiments, the size (or area) of the testing module200may be substantially the same as the size (or area) the field12of the wafer10, such that the testing module200can cover an entirety of the field12of the wafer10. That is, the testing module200is aligned to a target field12of the wafer10.

Reference is made toFIGS.1A,1C, and5A. As discussed with respect toFIGS.1A and1C, each field12of the wafer10includes one die region31. In such embodiments, the testing target is the die region31and the testing pads32surrounding the die region31. Accordingly, the testing module200ofFIG.5Acovers a field12of the wafer10, which includes one die region31and testing pads32surrounding the die region31. In some embodiments, the testing module200may cover an entirety of the die region31and the testing pads32. In such embodiments, the size of the testing module200can cover only one die region31. That is, the area of the testing module200may be slighter larger than the area of the die region31, and may be less than two times the area of the die region31.

Reference is made toFIGS.1A,1D, and5A. As discussed with respect toFIGS.1A and1D, each field12of the wafer10includes die regions33A,33B,33C, and33D. In such embodiments, the testing target is the die regions33A to33D and the testing pads34A to34D surrounding the die regions33A to33D, respectively. Accordingly, the testing module200ofFIG.5Acovers a field12of the wafer10, which includes the die regions33A to33D and the testing pads34A to34D surrounding the die regions33A to33D. In some embodiments, the testing module200may cover an entirety of the die regions33A,33B,33C, and33D. In such embodiments, the size of the testing module200can cover more than one die regions.

Reference is made toFIG.5B. In greater details, the testing module200is aligned to the testing patterns192and194of the substrate102. For example, the vias272and274are aligned with the testing pads176and178, respectively. In some embodiments, the alignment process is performed such that the vias272and274are vertically above the scribe line region102B of the substrate102. In some embodiments, although the testing module200may vertically overlap the die region102A of the substrate102, the vias272and274do not vertically overlap the die region102A of the substrate102.

Reference is made toFIG.5C. Some elements ofFIG.5Care similar to those ofFIG.5B, such elements are labeled the same, and thus relevant details will not be repeated for brevity.FIG.5Cis different fromFIG.5B, in that the first semiconductor device212and the second semiconductor device214ofFIG.5Bare omitted inFIG.4C.

Reference is made toFIG.5D. Some elements ofFIG.5Dare similar to those ofFIG.5B, such elements are labeled the same, and thus relevant details will not be repeated for brevity.FIG.5Dis different fromFIG.5B, in that the conductive pads282and284are aligned with the conductive pads176and178, respectively. In some embodiments, the alignment process is performed such that the conductive pads282and284are vertically above the scribe line region102B of the substrate102. In some embodiments, although the testing module200may vertically overlap the die region102A of the substrate102, the conductive pads282and284do not vertically overlap the die region102A of the substrate102.

Referring back toFIG.2, the method M1proceeds to block S104, in which the testing module is moved down to the testing target of the wafer. Reference is made toFIG.6A, the gripper600moves that the testing module200downwardly to the wafer10, such that the testing module200is in contact with the wafer10, and may be electrically connected to the testing target (e.g., testing pads of the testing patterns) of the wafer10.

Reference is made toFIG.6B. In greater details, the testing module200moved downwardly to the wafer100, such that the vias272and274are in contact with the conductive pads176and178, respectively. In some embodiments, the bottom surface of the substrate202of the testing module200is separated from the wafer100.

Reference is made toFIG.6C. Some elements ofFIG.6Care similar to those ofFIG.6B, such elements are labeled the same, and thus relevant details will not be repeated for brevity.FIG.6Cis different fromFIG.6B, in that the first semiconductor device212and the second semiconductor device214ofFIG.6Bare omitted inFIG.6C.

Reference is made toFIG.6D. Some elements ofFIG.6Dare similar to those ofFIG.6B, such elements are labeled the same, and thus relevant details will not be repeated for brevity.FIG.6D is different fromFIG.6B, in that the testing module200moved downwardly to the wafer100, such that the conductive pads282and284are in contact with the conductive pads176and178, respectively.

Referring back toFIG.2, the method M1proceeds to block S105, in which a testing process is performed. In some embodiments ofFIG.7A, the testing process may be a circuit probing (CP) test. For example, a probe (e.g., the conductive vias272and274ofFIGS.7B and7C, or the conductive pads282and284ofFIG.7D) may be used to electrically couple to a testing pad (e.g., the testing pads176,178ofFIGS.7B to7D) of a wafer for die testing to check whether a die is a good die. In some embodiments, the testing pad of the testing pattern serves as an indicator to check whether the corresponding die is a good die. The die may be selected to test different electrical properties and/or electrical functionalities, such as leakage current, breakdown voltage, threshold voltage and effective channel length, saturation current, contact resistance and connections. That is, the testing results of the testing pattern can reflect the condition of the associated die. In some embodiments, if the die passes the CP test, the die may be referred to as a known good die (KGD).

Reference is made toFIG.7B. The topmost layer of the conductive lines254of the conductive features250in the testing module200may include exposed conductive pads292,294,296, and298. The conductive pads292,294,296, and298are electrically connected to a processor300. Accordingly, the electrical properties and/or the electrical functionalities of the testing patterns192and194may be detected by the processor300through the testing module200, and the processor300may be configured to determine whether the electrical properties and/or the electrical functionalities of the testing patterns192and194pass the CP test. For example, if the electrical properties and/or the electrical functionalities of the testing pattern192(or194) are within a predetermined value, the testing pattern192(or194) may be indicated as passing the CP test, and the die region102A including the integrated circuit180associated with the testing patterns192(and/or194) may be indicated as passing the CP test, and may be indicated as a good die. However, if the electrical properties and/or the electrical functionalities are not within the predetermined value, the testing pattern192(or194) does not pass the CP test, the die region102A including the integrated circuit180associated with the testing patterns192(and/or194) may be discarded or repaired.

The electrical properties and/or the electrical functionalities of the testing pattern192can be detected by the processor300through the components in the testing module200. In some embodiments, the conductive via272may be electrically connected to the first semiconductor device212through the conductive feature250, and the electrical signal from the testing pad176may be transmitted to the processor300through the conductive via272, the conductive feature250, and the first semiconductor device212.

On the other hand, the electrical properties and/or the electrical functionalities of the testing pattern194can be detected by the processor300through the components in the testing module200. In some embodiments, the conductive via274may be electrically connected to the second semiconductor device214through the conductive feature250, and the electrical signal from the testing pad178may be transmitted to the processor300through the conductive via274, the conductive feature250, and the second semiconductor device214.

In some embodiments, the first semiconductor device212and the second semiconductor device214can act as switches that control signal transmissions from the testing patterns192and194to the processor300. For example, if the testing patterns192and194are associated with different semiconductor devices (or integrated circuit) in different die regions, the testing process can be performed to the testing patterns192and194individually. That is, during the processor300detects electrical properties and/or the electrical functionalities of the testing pattern192, the first semiconductor device212is turned on, while the second semiconductor device214is turned off. As a result, signal transmission is allowed from the testing pad176of the testing pattern192to the processor300through the first semiconductor device212. However, signal transmission is forbidden from the testing pad178of the testing pattern194to the processor300, because the second semiconductor device214is turned off. Similarly, during the processor300detects electrical properties and/or the electrical functionalities of the testing pattern194, the first semiconductor device212is turned off, while the second semiconductor device214is turned on, relevant details will not be repeated for brevity.

In some embodiments, the processor300can be general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, or microcontroller. A processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

FIGS.7C and7Dare similar toFIG.7B, and thus relevant details will not be repeated for brevity. The difference betweenFIG.7CandFIG.7Bis that the first semiconductor device212and the second semiconductor device214are omitted inFIG.7C. The difference betweenFIG.7DandFIG.7Bis that the first semiconductor device212and the second semiconductor device214are omitted inFIG.7D, and the conductive vias272and274are electrically connected to the testing pads176and178through the conductive pads282and284, respectively.

Referring back toFIG.2, the method M1proceeds to block S106, in which the testing module is detached from the wafer. InFIG.8, when the testing process as discussed inFIGS.7A to7Dis completed, the testing module200is detached from the wafer10. In some embodiments, the gripper600may move the testing module200upwardly to break the electrical connection between the testing module200and the wafer10. In some embodiments, the gripper600may move the testing module200to another field12, and then performing another testing process to the die in another field12. The above operation may be repeated until all testing targets in the fields12on the wafer10undergo the processes as discussed in blocks S102to S106. Afterward, the gripper600may move the testing module200to a recycling area. Here, the recycling area can be a space or a container for placing a testing module200.

Referring back toFIG.2, the method M1proceeds to block S107, in which a cleaning process is performed to the testing module. After performing several times of testing processes discussed above, the testing module200may include contaminations on exposed surface of the testing module200. For example, the bottom surface of the substrate202, the exposed surfaces of the conductive vias272and274, or the exposed surfaces of the conductive pads282and284may include contaminations. The contaminations may deteriorate the accuracy of the testing process once the testing module200is used again. Accordingly, a cleaning process may be performed to remove contaminations from the bottom surface of the substrate202, the exposed surfaces of the conductive vias272and274, or the exposed surfaces of the conductive pads282and284.

Referring back toFIG.2, the method M1proceeds to block S108, an interconnection structure is formed over the integrated circuit. As shown inFIG.9, after the testing module200is detached from the wafer100, an interconnection structure348is formed over the interconnection structure148.

The interconnect structure348may include one or more layers of conductive features350formed in one or more stacked dielectric layers360. Conductive features350may include conductive lines354and conductive vias352interconnecting the layers of conductive lines354. The conductive vias352may extend through respective ones of the dielectric layers360to provide vertical connections between layers of conductive lines354. The materials and formation methods of the interconnect structure348can be similar to the interconnect structure148, and thus relevant details will not be repeated for brevity.

In some embodiments, the conductive features350of the interconnect structure348may be in contact with the conductive pads172,174,176, and178of the interconnect structure148, respectively. In greater details, the conductive features350may be electrically connected to the integrated circuit180, and may be electrically connected to the semiconductor device112and114.

Referring back toFIG.2, the method M1proceeds to block S109, a singulation process is performed. In some embodiments, after the interconnect structure348is formed, a singulation process may be performed. The singulation process is achieved by a saw that is used to cut completely through the wafer along each of the scribe line regions (e.g., the scribe line region102B shown inFIG.9), and the resulting structure is shown inFIG.10, in which the die region102A is singulated into an individual die400. Because testing patterns192and194are formed over scribe line region102B (seeFIG.9), the testing patterns192and194are destroyed during the singulation process. The singulation process is a wafer dicing process including mechanical sawing, laser cutting, or a combination thereof.

According to some embodiments of the present disclosure, because the semiconductor devices become smaller and smaller, the gross die per wafer (GDPW) will increase. If the GDPW is greater than 10K, the testing process becomes an issue for smaller device. The present disclosure provides a method by performing a testing process to a wafer prior to forming a final interconnection structure, which provides an early check to the semiconductor devices over the wafer. Furthermore, the testing module used in the testing process is formed through a semiconductor fabrication process, which will also shrink the dimension of the conductive features in the testing module, and is beneficial for connecting the testing module to the testing patterns over the wafer. The present disclosure provides a robust early sanity check through the testing module and the testing process, which will reduce manufacturing cost and processing time, and will further improve the manufacturing efficiency.

FIGS.11to14Bare cross-sectional views of intermediate stages in the manufacturing of a testing module, in accordance with some embodiments.

Reference is made toFIG.11, a first semiconductor device212and a second semiconductor device214are formed over a substrate202. In some embodiments, the semiconductor device212includes a gate structure222and source/drain regions232on opposite sides of the gate structure222. On the other hand, the semiconductor device214includes a gate structure224and source/drain regions234on opposite sides of the gate structure224.

In some embodiments, the gate structures222and224are high-k, metal gate (HKMG) gate structures that may be formed using a gate-last process flow. In a gate last process flow, sacrificial dummy gate structures (not shown) is formed after forming the isolation regions105. The dummy gate structures each may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, or the like) may be deposited. Next a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, or the like) may be deposited over the dummy gate dielectric and then planarized (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, or the like) may be formed over the dummy gate material. The dummy gate structures are then formed by patterning the hard mask and transferring that pattern to the dummy gate dielectric and dummy gate material using suitable photolithography and etching techniques. As described in greater detail below, the dummy gate structures may be replaced by the HKMG gate structures222and224, respectively. The materials used to form the dummy gate structure and hard mask may be deposited using any suitable method such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD) or the like, or by thermal oxidation of the semiconductor surface, or combinations thereof.

Gate spacers240may be formed by deposition and anisotropic etch of a spacer dielectric layer performed after the dummy gate patterning is complete. The spacer dielectric layer may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof. The anisotropic etch process removes the spacer dielectric layer from over the top of the dummy gate structures leaving the gate spacers240along the sidewalls of the dummy gate structures.

After the source and drain regions232and234are formed, dummy gate structures may be replaced with gate structures222and224. For example, the dummy gate structures may be removed by etching process to form gate trenches between gate spacers240. Then, gate dielectrics222A and224A are deposited in in the gate trenches, and gate metals222B and224B are deposited over the gate dielectrics222A and224A. Afterward, a CMP process is performed to remove excess materials of the gate dielectrics222A and224A and the gate metals222B and224B to form the gate structures222and224.

Reference is made toFIG.12. Interconnection structure248is formed over the substrate202and over the semiconductor devices212and214. The interconnect structure148may include one or more layers of conductive features250formed in one or more stacked dielectric layers260. Each of the stacked dielectric layers260may include a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. The dielectric layers260may be deposited using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like.

Conductive features250may include conductive lines254and conductive vias252interconnecting the layers of conductive lines254. The conductive vias252may extend through respective ones of the dielectric layers260to provide vertical connections between layers of conductive lines254. The conductive features250may be formed through any acceptable process, such as, a damascene process, a dual damascene process, or the like. In some embodiments, the conductive lines254and the conductive vias252may be made of Al, Si, Cu, Ti, Ta, N, O, C, Ni, Co, W, or the like.

Reference is made toFIG.13. Vias272and274are formed through the substrate202. For example, the structure ofFIG.12may be flipped over, and then etching the substrate202to form openings extending through the substrate202and exposing at least portions of the conductive features. Then, conductive materials, such as metal, may be deposited in the openings. Afterward, a CMP process is performed to remove excess materials of the conductive materials until the bottom surface of the substrate202is exposed.

Reference is made toFIG.14A, in whichFIG.14Aillustrate a method for forming vias272and274as discussed inFIGS.4B and4C. After the process shown inFIG.13is completed, an etching back process may be performed to the substrate202to pull back the bottom surface of the substrate202, such that the vias272and274protrude from the bottom surface of the substrate202.

Reference is made toFIG.14B, in whichFIG.14Billustrate a method for forming conductive pads282and284as discussed inFIG.4D. After the process shown inFIG.13is completed, conductive pads282and284are formed on the bottom surface of the substrate202, and are in contact with the vias272and274, respectively. The conductive pads282and284may be formed by, for example, depositing a metal layer over the bottom surface of the substrate202, and then patterning the metal layer to form the conductive pads282and284.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the present disclosure provides a method by performing a testing process to a wafer prior to forming a final interconnection structure, which provides an early check to the semiconductor devices over the wafer. Furthermore, the testing module used in the testing process is formed through a semiconductor fabrication process, which will also shrink the dimension of the conductive features in the testing module, and is beneficial for connecting the testing module to the testing patterns over the wafer. The present disclosure provides a robust early sanity check through the testing module and the testing process, which will reduce manufacturing cost and processing time, and will further improve the manufacturing efficiency.

According to some embodiments of the present disclosure, a method includes forming an integrated circuit and a testing pattern over a die region of a wafer and a scribe line region of the wafer, respectively, in which the integrated circuit and the testing pattern are formed by a same fabrication process; connecting a via of a testing chip to a testing pad of the testing pattern; performing a testing process to the die region by detecting electrical properties of the testing pattern through the testing chip; after the testing process is completed, forming an interconnection structure over the integrated circuit, in which the interconnection structure includes conductive features electrically connected to the integrated circuit; and after the interconnection structure is formed over the integrated circuit performing an singulation process through the scribe line region of the wafer, such that the die region of the wafer is singulated into an individual die.

In some embodiments, the testing chip includes a semiconductor substrate, and the via of the testing chip extends through the semiconductor substrate and protrudes from a bottom surface of the semiconductor substrate.

In some embodiments, a top surface of the via is higher than a top surface of the semiconductor substrate.

In some embodiments, the testing chip further includes a transistor over the semiconductor substrate, and the transistor is electrically connected to the via.

In some embodiments, the method further includes performing an alignment process such that the testing chip covers an entirety of the die region of the wafer.

In some embodiments, the via of the testing chip is electrically connected to the testing pad of the testing pattern through a conductive pad in contact with a bottom surface of the testing chip.

In some embodiments, the method further includes performing a cleaning process by removing contaminations from the via of the testing chip after the testing process is completed.

According to some embodiments of the present disclosure, a method includes forming an integrated circuit and a testing pattern over a die region of a wafer and a scribe line region of the wafer, respectively, in which the integrated circuit and the testing pattern are formed simultaneously; moving a testing chip to a position above the die region and the scribe line region of the wafer, in which the testing chip includes a semiconductor substrate, a first interconnection structure over the semiconductor substrate, in which the first interconnection structure includes first conductive features, and a via extending through the semiconductor substrate and electrically connected to the first conductive features; electrically connecting the via of the testing chip to a testing pad of the testing pattern; performing a testing process to the die region by detecting electrical properties of the testing pattern through the testing chip; and after the testing process is completed, performing an singulation process through the scribe line region of the wafer, such that the die region of the wafer is singulated into an individual die.

In some embodiments, the method further includes forming a second interconnection structure over the integrated circuit after performing the testing process and prior to performing the singulation process.

In some embodiments, the testing chip is moved by a gripper.

In some embodiments, the method further includes performing a cleaning process to remove contaminations from a bottom surface of the semiconductor substrate of the testing chip and the via of the testing chip.

In some embodiments, an area of the testing chip is greater than an area of the die region of the wafer and is smaller than twice the area of the die region.

In some embodiments, the method further includes aligning the via of the testing chip with the testing pad of the testing pattern; and moving down the testing chip such that the via of the testing chip is in contact with the testing pad of the testing pattern.

In some embodiments, during performing the testing process, the testing chip covers an entirety of the die region.

According to some embodiments of the present disclosure, a method includes picking up a testing chip by a gripper, in which the testing chip includes a semiconductor substrate and first and second vias protruding from a bottom surface of the semiconductor substrate; moving the testing chip to a position over a wafer, the wafer comprising a first die region, a second die region, a scribe line region between the first die region and the second die region, and a first testing pad and a second testing pad in the scribe line region, in which the first testing pad is associated with a first semiconductor device in the first die region, and the second testing pad is associated with a second semiconductor device in the second die region; moving down the testing chip, such that the first via of the testing chip is electrically connected to the first testing pad, and a second via of the testing chip is electrically connected to the second testing pad; performing a testing process to the first and second die regions through the testing chip; and after the testing process is completed, performing a singulation process through the scribe line region of the wafer.

In some embodiments, the testing chip further includes a first transistor and a second transistor over the semiconductor substrate.

In some embodiments, the first transistor is electrically connected to the first via, and the second transistor is electrically connected to the second via, and in which during testing the first die region, the second transistor is turned off, while during testing the second die region, the first transistor is turned off.

In some embodiments, the testing chip further includes a guard ring structure laterally between the first and second vias, and a bottom surface of the guard ring structure is higher than bottom surfaces of the first and second vias.

In some embodiments, the method further includes forming an interconnection structure over the wafer after the testing process is completed and prior to performing the singulation process.

In some embodiments, the method further includes performing an alignment process such that the testing chip covers the first and second die regions.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.