Patent ID: 12237863

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or one or more intervening elements may be present.

Radio Frequency (RF) switching devices are provided to alternatively couple an antenna to either a transmitter amplifier or a receiver amplifier to switching between transmitting and receiving of a signal. This disclosure presents various embodiments of a RF switch module and methods to fabricate and operate such RF switch to alternatively couple an antenna to either a transmitter transmission line or a receiver transmission line to realize lower distortion of a signal at high frequencies with improved insertion loss and without affecting isolation.

FIG.1illustrates an exemplary block diagram of a Radio Frequency (RF) transceiver system100, in accordance with some embodiments of the present disclosure. In the illustrated embodiment, the RF transceiver system100comprises at least one antenna102, an RF switch104, a receiver (Rx) filter106, a transceiver unit108, a data processing unit110, a power amplifier (PA) module112, a power supply114, and a low-pass filter (LPF)116. Accordingly, it is understood that additional functional blocks may be provided within the RF transceiver system100for signal process, and that some other functional blocks may only be briefly described herein.

In some embodiments, the RF switch104is used to direct the signal from the antenna102to the receiver filter106or from the LPF116output to the antenna102. The RF switch must have low loss (<0.1 dB) so as to not to add to the system noise or attenuate the transmit signal.

In some embodiments, the Rx filter106is to filter signals to eliminate out-of-band signals so that they will not be amplified or impact the linearity of the transceiver processor108. In some embodiments, the transceiver processor108further comprises at least one of the following signal processing elements, including a low noise amplifier, an RF filter, a mixer, a demodulator, a digital-to-analog converter, an analog-to-digital converter, and a modulator. Received data120is further transmitted to a data processing unit. In some embodiments, transmit data122from the data processing unit110is processed by the transceiver processor108, is amplified by the PA module112and filtered by the LPF116before transmitted to the RF switch104and further to the antenna102.

In the illustrated embodiment, the RF switch104shares one antenna in transmission and reception and is configured and controlled to switch the signal path. In some embodiments, the RF switch104has the following characteristics such as low loss, low power consumption.

FIG.2Aillustrates a circuit diagram of an RF switch module200in a Radio Frequency (RF) transceiver system100, in accordance with some embodiments of the present disclosure. In the illustrated embodiments, the RF switch200comprises 3 ports, including an antenna port204, a transmitter port206, and a receiver port208. It should be noted that an RF switch200can comprise any numbers of transmitter ports or receiver ports, which are within the scope of this invention.

In the illustrated embodiment, the transmitter port206is coupled to the antenna port204through a first capacitance switch202-1; and the receiver port208is also coupled to the antenna port204through a second capacitance switch202-2. Each of the first capacitance switch202-1and the second capacitance switch202-2is a varactor diode, wherein the varactor diode exhibits a voltage-dependent capacitance. As discussed in detail below, the varactor diode used in the capacitance switch202is constructed based on a Complementary Metal-Oxide Semiconductor (CMOS) Field Effect Transistor (FET) with inhomogeneous layered dielectrics as the gate stack. In some embodiments, each of the capacitance switch202comprises at least 2 layers of dielectrics, wherein the at least two layers of dielectrics comprises at least one layer of high-k dielectric material and at least one layer of a negative-capacitance material. The stacked dielectric in the capacitance switch202provide an overall capacitance (Ceq) equivalent to at least two capacitances connected in series, including a first capacitance C1from the high-k dielectric and a second capacitance C2from the negative-capacitance dielectric. Using 1 layer of a high-k dielectric material and 1 layer of a negative-capacitance material as an example, the overall capacitance Ceq is determined by the following equation: Ceq=(C1−1+C2−1)−1=C1C2/(C1+C2).

In the illustrated embodiment, each of the three ports, i.e., the antenna port204, the transmitter port206, and the receiver port208is coupled to a power supply unit214. Specifically, the antenna port204is coupled to a first power supply unit214-1; the transmitter port206is coupled to a second power supply unit214-2; and the receiver port208is coupled to a third power supply unit214-3. Each of the power supply units214comprises a DC power supply212and at least one resistor210. In some embodiments, the DC power supply212and the at least one resistor210are coupled in series between each of the corresponding ports and ground (GND).

In the illustrated embodiment, when the DC voltage provided from the DC power supply212-2is low or no bias, a large capacitance value and thus a low RF impedance from the varactor202-1can be achieved in the signal line on the transmitter port206, allowing the RF signal from the transmitter to be transmitted to the antenna port204. Meanwhile, when the DC voltage (VDD) provided from the DC power supply212-3is large, a small capacitance value and thus a large RF impedance from the varactor202-2can be achieved in the signal line on the receiver port208, blocking the RF signal from entering the receiver port208. In this case, the capacitance switch202-1is on and the capacitance switch202-2is off, so that the RF switch200is in a transmitter mode. In some embodiments, a DC voltage across the gate and one of the source or drain terminals of the FET in a range of ±1˜±2 Volt is applied to turn on the capacitance switch202.

Similarly, when the DC voltage provided from the DC power supply212-3is low or no bias, a large capacitance value and thus a low RF impedance from the varactor202-2can be achieved in the signal line on the receiver port208, allowing the RF signal received on the antenna port204entering the receiver port208. Meanwhile, when the DC voltage (VDD) provided from the DC power supply212-2is large, a small capacitance value and thus a large RF impedance from the varactor202-1can be achieved in the signal line on the transmitter port206, blocking the RF signal from the transmitter to be transmitted to the antenna port204. In this case, the capacitance switch202-2is on and the capacitance switch202-1is off, so that the RF switch200is in a receiver mode. In some embodiments, a DC voltage across the gate and one of the source or drain terminals of the FET in a range of ±1˜±2 Volt can be used to turn on the capacitance switch202.

As shown inFIG.2B, in some embodiments, a DC voltage for switching on or off the capacitance switch202is applied on the gate terminal, while the drain terminal is grounded, the body terminal is grounded through a large resistor (e.g., with a resistance value of 100 kOhm) and the source terminal remains open. In some other embodiments, a DC voltage for switching on or off the capacitance switch202is applied on the gate terminal, while the source terminal is grounded, the body terminal is ground through a large resistor (e.g., with a resistance value of 100 kOhm), and the drain terminal remains open.

FIGS.3A-3Billustrate exemplary cross-sectional view and top view of a negative-capacitance field effect transistor (FET)300for a capacitance switch in an RF switch200, in accordance with some embodiments of the present disclosure. In some embodiments, the negative-capacitance FET300comprises two highly-doped conductive regions304-1and304-2as the source and drain terminals, a conductive gate310, a stacked gate dielectrics308/306, and metallic contacts312-S,312-D and312-G. The negative-capacitance FET300is fabricated on a semiconductor substrate302and embedded in a dielectric layer314.

In the illustrated embodiment, the stacked gate dielectrics is inhomogeneous in the y direction comprising 2 stacked dielectric materials, i.e., a first dielectric layer306and a second dielectric layer308. The inhomogeneous capacitor with two dielectrics between the gate terminal and the source terminal can be modelled as two capacitors in series, i.e., a first capacitor C1316in the first dielectric layer306and a second capacitor C2318in the second dielectric layer308. The overall capacitance Ceq is determined by the following equation: Ceq=(C1−1+C2−1)−1=C1C2/(C1+C2).

In some embodiments, the first dielectric layer306comprises a conventional dielectric material with high dielectric constant (i.e., a high-k dielectric material) for improved reliability and high capacitance values. In some embodiments, the first dielectric layer306comprises one of the following materials, including hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), silicon oxynitride (Si2ON2), and nitride hafnium silicates (HfSiON).

In some embodiments, a first thickness320of the first dielectric layer306is in a range of 0.1-200 nanometers. In some embodiments, the first dielectric layer306is deposited using plasma enhanced chemical vapor deposition (PECVD) with a silane gas as a precursor gas. In some other embodiments, the first dielectric layer306is deposited using one of the following: an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process.

In some embodiments, the second dielectric layer308is formed on the top surface of the first dielectric layer306, wherein the second dielectric layer308exhibit a negative capacitance (i.e., C2<0) in a certain range of an applied bias. In some embodiments, the second dielectric layer308comprises HfO2 doped with various elements including Y, Sr, Gd, Zr, Al, Lu, Ta, Nb, and Si, wherein the doped HfO2 dielectric in the second dielectric layer308exhibits ferroelectric properties. In some embodiments, the doped HfO2 dielectric in the second dielectric layer308is ascribed to the metastable, non-centrosymmetric, orthorhombic phase being stabilized by the dopants. In some embodiments, the doped HfO2 dielectric in the second dielectric layer308can be easily integrated with the CMOS process. In some other embodiments, the second dielectric layer308further comprises ZrO2 doped with Ta and Ti. In some further embodiments, the second dielectric layer308comprises a ferroelectric material, including BaTiO3, SrRuO3, and PbZr1-xTixO3.

In some embodiments, a second thickness322of the second dielectric layer308is in a range of 0.1-200 nanometers. In the illustrated embodiments, the second dielectric layer308has a length of332in the z direction and a width of334in the x direction, which has the same area as the conductive gate310. In some embodiments, a ratio between the area of a top surface of the second dielectric layer308and the area of the transistor channel is in a range of 0.1-5. In some embodiments, the second dielectric layer308is deposited using plasma enhanced chemical vapor deposition (PECVD) with a silane gas as a precursor gas. In some other embodiments, the second dielectric layer308is deposited using one of the following: an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process. In some embodiments, the second dielectric layer308is deposited at a temperature in a range of 0-1000 degree Celsius. In some embodiments, after deposition of the second dielectric layer308and before forming the conductive gate310, the second dielectric layer308is annealed through a rapid thermal annealing (RTA) process at a temperature in a range of 100-1000 degree Celsius for a time period in a range of 1-600 second.

Although in the exemplary embodiment, the second dielectric layer308is configured above the first dielectric layer306, wherein the first dielectric layer306is in direct contact with the substrate302, the second dielectric layer308can be configured between the first dielectric layer306and the substrate302, which is also within the scope of this invention. Although only 2 dielectric layers in the stacked gate dielectrics are shown, the exemplary embodiment is for discussion purposes. It should be noted that the stacked gate dielectrics can comprise any numbers of alternating dielectric layers, e.g., negative-capacitance dielectric layer—conventional dielectric layer superlattices, which are within the scope of the invention.

In some embodiments, the substrate302is a silicon substrate. Alternatively, the substrate302may include other elementary semiconductor material such as, for example, germanium. The substrate302may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate302may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate302includes an epitaxial layer. For example, the substrate302may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate302may include a semiconductor-on-insulator (SOI) structure. For example, the substrate302may include a buried oxide (BOX) layer folioed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.

In some embodiments, the substrate302also includes various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, lightly doped region (LDD), heavily doped source and drain (S/D) terminals304-1/304-2, and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a CMOS field-effect transistor (CMOS-FET), imaging sensor, and/or light emitting diode (LED). The substrate302may further include other functional features such as a resistor or a capacitor formed in and on the substrate. The substrate302further includes lateral isolation features provided to separate various devices formed in the substrate302, for example shallow trench isolation (STI). The various devices in the substrate302further include silicide disposed on S/D terminals, gate terminal and other device features for reduced contact resistance and enhance process compatibility when coupled between devices through metal contacts312-S/312-D/312-G.

In some embodiment, at least one conductive feature is included in the substrate302. In some embodiments, the at least one conductive feature can be a source304-1, drain304-2, or gate terminals310. Alternatively, the at least one conductive feature may be a silicide feature disposed on a source, drain or gate electrode typically from a sintering process introduced by at least one of the processes including thermal heating, laser irradiation or ion beam mixing. The silicide feature may be formed on polysilicon gate (typically known as “polycide gate”) or on source/drain (typically known as “salicide”) by a self-aligned silicide technique. In another embodiment, the at least one conductive feature may include an electrode of a capacitor or one end of a resistor. In the illustrated embodiment, at least three metal contacts312-G are configured to make electrical contact to the conductive gate310. In some embodiments, each of the at least three metal contacts has a width324and an enclosure distance326, wherein the enclosure distance326is defined as a distance between the edge of the metal contacts312-G to the edge of the conductive gate310. The at least three metal contacts312-G are configured in a row with a spacing330between two of the neighboring metal contacts. In some embodiments, a first ratio between the spacing330and the first thickness320of the first dielectric layer306is in a range of 0.01-100; a second ratio between the spacing330and the second thickness322of the second dielectric layer308is in a range of 0.1-10000; a third ratio between the spacing330and the channel width334is in a range of 0.1-10000; a fourth ratio between the spacing330and the channel length332is in a range of 0.00001-1; a fifth ratio of the enclosure distance326and the second thickness322of the second dielectric layer308is in a range of 0.1-10000; a sixth ratio of the enclosure distance326and the channel width334is in a range of 0.1-10000; and a seventh ratio of the enclosure distance326and the channel length332is in a range of 0.1-10000. In some embodiments, the at least three metal contacts can be arranged in an array configured in at least two rows and at least two columns.

FIG.4illustrates a flow chart of a method400to form a semiconductor device, in accordance with some embodiments of the present disclosure. It is noted that the method400is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method400ofFIG.4, and that some other operations may only be briefly described herein. In some embodiments, operations of the method400may be associated with cross-sectional views of a semiconductor device at various fabrication stages as shown inFIGS.5A-5J, respectively, which will be discussed in further detail below.

Referring now toFIG.4, the method400starts with operation402in which a substrate is provided according to some embodiments. In some embodiments, the substrate comprises conductive features. The method400continues with operation404in which a first dielectric layer is deposited on the surface of the substrate according to some embodiments. In some embodiments, the first dielectric layer comprises a high-k dielectric material. The method400continues with operation406in which a second dielectric layer is deposited on the surface of the first dielectric layer according to some embodiments. In some embodiments, the second dielectric layer comprises a negative-capacitance dielectric material, which exhibits a negative capacitance in a certain range of an applied bias. The method400continues with operation408in which a first conductive layer is deposited on the surface of the second dielectric layer according to some embodiments. In some embodiments, the first conductive layer comprises polycrystalline silicon (polySi). The method400continues with operation410in which the first dielectric layer, the second dielectric layer and the first conductive layer are patterned according to some embodiments. In some embodiments, the patterned first dielectric layer and the second dielectric layer are sandwiched between the patterned first conductive layer to form a stacked gate dielectric. The method400continues with operation412in which a third dielectric layer is deposited according to some embodiments. In some embodiments, the third dielectric layer is first deposited to embed the patterned first dielectric layer, the patterned second dielectric layer, the first conductive layer and exposed surfaces of the substrate. The method400continues with operation414in which at least three metal contacts are formed to make electric contacts to the first conductive layer according to some embodiments. In some embodiments, prior to forming the metal contacts, the third dielectric layer is further polished to form a planar surface. In some embodiments, metal contacts to the conductive features in the substrate can be also formed.

As mentioned above,FIGS.5A-5Iillustrate, in a cross-sectional view, a portion of a semiconductor device500at various fabrication stages of the method400ofFIG.4. The semiconductor device500may be included in an integrated circuit (IC). Also,FIGS.5A-5Iare simplified for a better understanding of the concepts of the present disclosure. Although the figures illustrate the semiconductor device500, it is understood the IC may comprise a number of other devices such as resistors, capacitors, inductors, fuses, etc., which are not shown inFIGS.5A-5I, for purposes of clarity of illustration.

FIG.5Ais a cross-sectional view of the semiconductor device500including a substrate302at one of the various stages of fabrication corresponding to operations402ofFIG.4, in accordance with some embodiments of the present disclosure. In some embodiments, the substrate302is a silicon substrate. Alternatively, the substrate302may include other elementary semiconductor material such as, for example, germanium. The substrate302may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate302may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate302includes an epitaxial layer. For example, the substrate302may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate302may include a semiconductor-on-insulator (SOI) structure. For example, the substrate302may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.

In some embodiments, the substrate302also includes various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, lightly doped region (LDD), heavily doped source and drain (S/D) terminals304-1/304-2, and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a CMOS field-effect transistor (CMOS-FET), imaging sensor, and/or light emitting diode (LED). The substrate302may further include other functional features such as a resistor or a capacitor formed in and on the substrate. The substrate302further includes lateral isolation features provided to separate various devices formed in the substrate302, for example shallow trench isolation (STI). The various devices in the substrate302further include silicide disposed on S/D terminals, gate terminal and other device features for reduced contact resistance and enhance process compatibility when coupled between devices through metal contacts312-S/312-D/312-G.

In some embodiment, at least one conductive feature is included in the substrate302. In some embodiments, the at least one conductive feature can be a source304-1, drain304-2, or gate terminals310. Alternatively, the at least one conductive feature may be a silicide feature disposed on a source, drain or gate electrode typically from a sintering process introduced by at least one of the processes including thermal heating, laser irradiation or ion beam mixing. The silicide feature may be formed on polysilicon gate (typically known as “polycide gate”) or on source/drain (typically known as “salicide”) by a self-aligned silicide technique. In another embodiment, the at least one conductive feature may include an electrode of a capacitor or one end of a resistor.

FIG.5Bis a cross-sectional view of the semiconductor device500including the first substrate302and a first dielectric layer306at one of the various stages of fabrication that corresponds to operation404ofFIG.4, in accordance with some embodiments of the present disclosure. In some embodiments, the first dielectric layer306comprises a conventional dielectric material with high dielectric constant (i.e., a high-k dielectric material) for improved reliability and high capacitance values. In some embodiments, the first dielectric layer306comprises one of the following materials, including hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), silicon oxynitride (Si2ON2), and nitride hafnium silicates (HfSiON).

In some embodiments, a first thickness320of the first dielectric layer306is in a range of 0.1-200 nanometers. In some embodiments, the first dielectric layer306is deposited using plasma enhanced chemical vapor deposition (PECVD) with a silane gas as a precursor gas. In some other embodiments, the first dielectric layer306is deposited using one of the following: an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process.

FIG.5Cis a cross-sectional view of the semiconductor device500including a second dielectric layer308over the surface of the first dielectric layer306at one of the various stages of fabrication that corresponds to operations406ofFIG.4, in accordance with some embodiments of the present disclosure. In some embodiments, the second dielectric layer308is formed on the top surface of the first dielectric layer306, wherein the second dielectric layer308exhibit a negative capacitance (i.e., C2<0) in a certain range of an applied bias. In some embodiments, the second dielectric layer308comprises HfO2 doped with various elements including Y, Sr, Gd, Zr, Al, Lu, Ta, Nb, and Si, wherein the doped HfO2 dielectric in the second dielectric layer308exhibits ferroelectric properties. In some embodiments, the doped HfO2 dielectric in the second dielectric layer308is ascribed to the metastable, non-centrosymmetric, orthorhombic phase being stabilized by the dopants. In some embodiments, the doped HfO2 dielectric in the second dielectric layer308can be easily integrated with the CMOS process. In some other embodiments, the second dielectric layer308further comprises ZrO2 doped with Ta and Ti. In some further embodiments, the second dielectric layer308comprises a ferroelectric material, including BaTiO3, SrRuO3, and PbZr1-xTixO3.

In some embodiments, a second thickness322of the second dielectric layer308is in a range of 0.1-200 nanometers. In the illustrated embodiments, the second dielectric layer308has a length of332in the z direction and a width of334in the x direction, which has the same area as the conductive gate310. In some embodiments, a ratio between the area of a top surface of the second dielectric layer308and the transistor channel is in a range of 0.1-5. In some embodiments, the second dielectric layer308is deposited using plasma enhanced chemical vapor deposition (PECVD) with a silane gas as a precursor gas. In some other embodiments, the second dielectric layer308is deposited using one of the following: an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process. In some embodiments, the second dielectric layer308is deposited at a temperature in a range of 0-1000 degree Celsius. In some embodiments, after deposition of the second dielectric layer308and before forming the conductive gate310, the second dielectric layer308is annealed through a rapid thermal annealing (RTA) process at a temperature in a range of 100-1000 degree Celsius for a time period in a range of 1-600 second.

FIG.5Dis a cross-sectional view of the semiconductor device500in which a first conductive layer310is deposited over the surface of the second dielectric layer308at one of the various stages of fabrication that corresponds to operations408ofFIG.4, in accordance with some embodiments of the present disclosure. In some embodiments, the first conductive layer310comprises polycrystalline silicon (polySi). In some embodiments, the first conductive layer has a thickness in a range of 0.1-100,000 nanometers.

FIG.5Eis a cross-sectional view of the semiconductor device500in which a photoresist layer502is coated on the surface of the first conductive layer310at one of the various stages of fabrication that corresponds to operation410ofFIG.4, in accordance with some embodiments of the present disclosure. As described below, the patterned photoresist layer502is used to mask an etching of the first conductive layer310, the second dielectric layer308, and the first dielectric layer306to form a stacked-dielectric gate terminal on the substrate302. In some embodiments, the stacked-dielectric gate terminal is configured between the conductive features304-1/304-2in the substrate302, forming a MOSFET structure.

In some embodiments, an initial photoresist layer502before the patterning process may include a negative or positive tone photoresist layer that is patternable in response to a photolithography light source. In some alternative embodiments, the initial photoresist layer502may include an e-beam (electron beam) resist layer (e.g., poly methyl methacrylate, methyl methacrylate, etc.) that is patternable in response to an e-beam lithography energy source. In some embodiments, the initial photoresist layer502is formed over the second dielectric layer308using a deposition process known in the art such as spin-coating, spray-coating, dip-coating, roller-coating, or the like.

FIG.5Fis a cross-sectional view of the semiconductor device500in which a photoresist layer502is patterned on the surface of the first conductive layer310at one of the various stages of fabrication that corresponds to operation410ofFIG.4, in accordance with some embodiments of the present disclosure. Accordingly, in some embodiments, the patterned photoresist layer502is formed after a conventional patterning (e.g., photolithography) process, to align the stacked-dielectric gate terminal to the conductive features304-1/304-2in the substrate302. The initial photoresist layer502is patterned in a lithography process that may involve various exposure, developing, baking, stripping, etching, and rinsing processes. As a result, the patterned photoresist layer502is formed such that at least a portion of the top surface of the first conductive layer310is exposed, as shown inFIG.5F.

FIG.5Gis a cross-sectional view of the semiconductor device500in which the first conductive layer310, the second dielectric layer308and the first dielectric layer306are patterned at one of the various stages of fabrication that corresponds to operation410ofFIG.4, in accordance with some embodiments of the present disclosure. In some embodiments, the pattered photoresist layer502is used as a hard mask during the patterning process. In some embodiments, the first conductive layer310, the second dielectric layer308, and the first dielectric layer306are etched by a dry and/or wet etching process.

In some embodiments, the patterned photoresist layer502is further removed. In some embodiments, the patterned photoresist layer502may be removed by one or more chemical cleaning processes using acetone, 1-Methyl-2-pyrrolidon (NMP), Dimethyl sulfoxide (DMSO), or other suitable removing chemicals. In some embodiments, the chemicals used may need to be heated to temperatures higher than room temperature to effectively dissolve the patterned photoresist layer502. The selection of the remover is determined by the type and chemical structure of the patterned photoresist layer502, the first conductive layer310, the second dielectric layer308, the first dielectric layer306, as well as the substrate302to assure the chemical compatibility of these layers with the chemical cleaning process. In some embodiments, this cleaning process is then followed by a rinsing process using isopropyl alcohol or the like, followed by rinsing using deionized water. As a result of this process, the stacked-dielectric gate terminal is formed on the substrate302.

FIG.5His a cross-sectional view of the semiconductor device500in which a third dielectric layer314is formed to cover exposed portions of the substrate302and embed the stacked-dielectric gate terminal at one of the various stages of fabrication that corresponds to operation412ofFIG.4, in accordance with some embodiments of the present disclosure. In some embodiments, the third dielectric layer314comprises silicon oxide. In some embodiments, the third dielectric layer314is further polished to achieve a planar surface.

FIG.5Iis a cross-sectional view of the semiconductor device500in which metal contacts are formed in the third dielectric layer314at one of the various stages of fabrication that corresponds to operation414ofFIG.4, in accordance with some embodiments of the present disclosure. In some embodiments, at least three metal contacts312-G are formed to make electrical contact to the first conductive layer310, as discussed inFIG.3B. In some embodiments, metal contacts312-S and312-D are also formed simultaneously making electrical contacts to the conductive features304-1and304-2, respectively. An exemplary top view of the semiconductor device500after operation414is illustrated and discussed inFIG.3B.

FIGS.6A-6Cillustrate exemplary perspective view, cross-sectional view, and top view of a semiconductor device600, in accordance with some embodiments of the present disclosure. The negative-capacitance FET structure in this present disclosure can be also implemented in a non-planar Fin field effect transistor (FinFET). The FinFET are fabricated with a thin vertical “fin” of “fin structure”602extending from a substrate302with a channel formed in this vertical fin and a conductive gate310over the fin602. Advantages of the FinFET includes reducing the short channel effect and higher current flow.

In the illustrated embodiment, conductive features304-1and304-2are fabricated in the fin602separated by a channel length614. The conductive gate310is deposited over the fin602covering the top surface and the sidewalls of the fin602. Specifically, the gate terminal310is also partially on the surface of the substrate302separated by a dielectric layer604; and the gate terminal310is separated from the fin602by stacked gate dielectrics. In some embodiments, the top surface of the fin602to the top surface of the dielectric layer604has a height612and the fin602has a fin width610, resulting in a channel width which equals the fin width610+2× fin height610.

In the illustrated embodiment, the stacked gate dielectrics separating the fin602and the conductive gate310is inhomogeneous comprising 2 stacked dielectric materials, i.e., a first dielectric layer306and a second dielectric layer308. The inhomogeneous capacitor with two dielectrics between the gate terminal and the source terminal can be modelled as two capacitors in series, i.e., a first capacitor C1316in the first dielectric layer306and a second capacitor C2318in the second dielectric layer308. The overall capacitance Ceq is determined by the equation below
Ceq=(C1−1+C2−1)−1=C1C2/(C1+C2).

When C2=−1.1C1, Ceq=11C1. Therefore, a negative-capacitance material in the second dielectric layer308significantly increases the equivalent capacitance and thus in order to obtain the same capacitance, such device structure presented in this present disclosure occupies a smaller area than the device with just a high-k dielectric layer.

In some embodiments, the first dielectric layer306comprises a conventional dielectric material with high dielectric constant (i.e., a high-k dielectric material) for improved reliability and high capacitance values. In some embodiments, the first dielectric layer306comprises one of the following materials, including hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), silicon oxynitride (Si2ON2), and nitride hafnium silicates (HfSiON).

In some embodiments, a first thickness320of the first dielectric layer306is in a range of 0.1-200 nanometers. In some embodiments, the first dielectric layer306is deposited using plasma enhanced chemical vapor deposition (PECVD) with a silane gas as a precursor gas. In some other embodiments, the first dielectric layer306is deposited using one of the following: an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process.

In some embodiments, the second dielectric layer308is formed on the top surface of the first dielectric layer306, wherein the second dielectric layer308exhibit a negative capacitance (i.e., C2<0) in a certain range of an applied bias. In some embodiments, the second dielectric layer308comprises HfO2 doped with various elements including Y, Sr, Gd, Zr, Al, Lu, Ta, Nb, and Si, wherein the doped HfO2 dielectric in the second dielectric layer308exhibits ferroelectric properties. In some embodiments, the doped HfO2 dielectric in the second dielectric layer308is ascribed to the metastable, non-centrosymmetric, orthorhombic phase being stabilized by the dopants. In some embodiments, the doped HfO2 dielectric in the second dielectric layer308can be easily integrated with the CMOS process. In some other embodiments, the second dielectric layer308further comprises ZrO2 doped with Ta and Ti. In some further embodiments, the second dielectric layer308comprises a ferroelectric material, including BaTiO3, SrRuO3, and PbZr1-xTixO3.

In some embodiments, a second thickness322of the second dielectric layer308is in a range of 0.1-200 nanometers. In the illustrated embodiments, the first dielectric layer306and the second dielectric layer308each has a length of 614 in the z direction and a width which equals the channel width. In some embodiments, the second dielectric layer308is deposited using plasma enhanced chemical vapor deposition (PECVD) with a silane gas as a precursor gas. In some other embodiments, the second dielectric layer308is deposited using one of the following: an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process. In some embodiments, the second dielectric layer308is deposited at a temperature in a range of 0-1000 degree Celsius. In some embodiments, after deposition of the second dielectric layer308and before forming the conductive gate310, the second dielectric layer308is annealed through a rapid thermal annealing (RTA) process at a temperature in a range of 100-1000 degree Celsius for a time period in a range of 1-600 second.

Although in the exemplary embodiment, the second dielectric layer308is configured above the first dielectric layer306, wherein the first dielectric layer306is in direct contact with the fin602, the second dielectric layer308can be configured between the first dielectric layer306and the fin602, which is also within the scope of this invention. Although only 2 dielectric layers in the stacked gate dielectrics are shown, the exemplary embodiment is for discussion purposes. It should be noted that the stacked gate dielectrics can comprise any numbers of alternating dielectric layers, e.g., negative-capacitance dielectric layer—conventional dielectric layer superlattices, which are within the scope of the invention.

In some embodiments, the substrate302is a silicon substrate. Alternatively, the substrate302may include other elementary semiconductor material such as, for example, germanium. The substrate302may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate302may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate302includes an epitaxial layer. For example, the substrate302may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate302may include a semiconductor-on-insulator (SOI) structure. For example, the substrate302may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.

In some embodiments, the substrate302also includes various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, lightly doped region (LDD), heavily doped source and drain (S/D) terminals, and various channel doping profiles configured to form various integrated circuit (IC) devices. The substrate302may further include other functional features such as a resistor or a capacitor formed in and on the substrate. The substrate302further includes lateral isolation features provided to separate various devices formed in the substrate302, for example shallow trench isolation (STI).

In some embodiments, the fin602is fabricated in the substrate302. In some embodiment, at least one conductive feature is included in the fin602. In some embodiments, the at least one conductive feature can be the source terminal304-1, the drain terminal304-2, or the conductive gate310. Alternatively, the at least one conductive feature may be a silicide feature disposed on a source, drain or gate electrode typically from a sintering process introduced by at least one of the processes including thermal heating, laser irradiation or ion beam mixing. The silicide feature may be formed on polysilicon gate (typically known as “polycide gate”) or on source/drain (typically known as “salicide”) by a self-aligned silicide technique. In another embodiment, the at least one conductive feature may include an electrode of a capacitor or one end of a resistor.

In the illustrated embodiment, at least three metal contacts312-G are configured to make electrical contact to the conductive gate310. In some embodiments, each of the at least three metal contacts has a width324and an enclosure distance326, wherein the enclosure distance326is defined as a distance between the edge of the metal contacts312-G to the edge of the conductive gate310. The at least three metal contacts312-G are configured in a row with a spacing330between two of the neighboring metal contacts. In some embodiments, a first ratio between the spacing330and the first thickness320of the first dielectric layer306is in a range of 0.01-100; a second ratio between the spacing330and the second thickness322of the second dielectric layer308is in a range of 0.1-10000; a third ratio between the spacing330and the channel width334is in a range of 0.1-10000; a fourth ratio between the spacing330and the channel length332is in a range of 0.00001-1; a fifth ratio of the enclosure distance326and the second thickness322of the second dielectric layer308is in a range of 0.1-10000; a sixth ratio of the enclosure distance326and the channel width334is in a range of 0.1-10000; and a seventh ratio of the enclosure distance326and the channel length332is in a range of 0.1-10000.

FIG.7illustrates a flow chart of a method700operate a Radio Frequency (RF) switch module200, in accordance with some embodiments of the present disclosure. It is noted that the method700is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method700ofFIG.7, and that some other operations may only be briefly described herein.

The method700starts with operation702, in which a DC voltage is applied between a gate terminal and a drain terminal of a field effect transistor (FET), according to some embodiments. In some embodiments, the FET comprises stacked gate dielectrics. In the illustrated embodiment, the stacked gate dielectrics is inhomogeneous in the y direction comprising 2 stacked dielectric materials, i.e., a first dielectric layer306and a second dielectric layer308. The inhomogeneous capacitor with two dielectrics between the gate terminal and the source terminal can be modelled as two capacitors in series, i.e., a first capacitor C1316in the first dielectric layer306and a second capacitor C2318in the second dielectric layer308. The overall capacitance Ceq is determined by the following equation: Ceq=(C1−1+C2−1)−1=C1C2/(C1+C2).

When C2=−1.1C1, Ceq=11C1. Therefore, a negative-capacitance material in the second dielectric layer308significantly increases the equivalent capacitance and thus in order to obtain the same capacitance, such device structure presented in this present disclosure occupies a smaller area than the device with just a high-k dielectric layer.

In some embodiments, the first dielectric layer306comprises a conventional dielectric material with high dielectric constant (i.e., a high-k dielectric material) for improved reliability and high capacitance values. In some embodiments, the first dielectric layer306comprises one of the following materials, including hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), silicon oxynitride (Si2ON2), and nitride hafnium silicates (HfSiON).

In some embodiments, a first thickness320of the first dielectric layer306is in a range of 0.1-200 nanometers. In some embodiments, the first dielectric layer306is deposited using plasma enhanced chemical vapor deposition (PECVD) with a silane gas as a precursor gas. In some other embodiments, the first dielectric layer306is deposited using one of the following: an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process.

In some embodiments, the second dielectric layer308is formed on the top surface of the first dielectric layer306, wherein the second dielectric layer308exhibit a negative capacitance (i.e., C2<0) in a certain range of an applied bias. In some embodiments, the second dielectric layer308comprises HfO2 doped with various elements including Y, Sr, Gd, Zr, Al, Lu, Ta, Nb, and Si, wherein the doped HfO2 dielectric in the second dielectric layer308exhibits ferroelectric properties. In some embodiments, the doped HfO2 dielectric in the second dielectric layer308is ascribed to the metastable, non-centrosymmetric, orthorhombic phase being stabilized by the dopants. In some embodiments, the doped HfO2 dielectric in the second dielectric layer308can be easily integrated with the CMOS process. In some other embodiments, the second dielectric layer308further comprises ZrO2 doped with Ta and Ti. In some further embodiments, the second dielectric layer308comprises a ferroelectric material, including BaTiO3, SrRuO3, and PbZr1-xTixO3.

In some embodiments, a second thickness322of the second dielectric layer308is in a range of 0.1-200 nanometers. In the illustrated embodiments, the second dielectric layer308has a length of332in the z direction and a width of334in the x direction, which has the same area as the conductive gate310. In some embodiments, a ratio between the area of a top surface of the second dielectric layer308and the transistor channel is in a range of 0.1-5. In some embodiments, the second dielectric layer308is deposited using plasma enhanced chemical vapor deposition (PECVD) with a silane gas as a precursor gas. In some other embodiments, the second dielectric layer308is deposited using one of the following: an atomic layer deposition (ALD) process, and a physical vapor deposition (PVD) process. In some embodiments, the second dielectric layer308is deposited at a temperature in a range of 0-1000 degree Celsius. In some embodiments, after deposition of the second dielectric layer308and before forming the conductive gate310, the second dielectric layer308is annealed through a rapid thermal annealing (RTA) process at a temperature in a range of 100-1000 degree Celsius for a time period in a range of 1-600 second.

Although in the exemplary embodiment, the second dielectric layer308is configured above the first dielectric layer306, wherein the first dielectric layer306is in direct contact with the substrate302, the second dielectric layer308can be configured between the first dielectric layer306and the substrate302, which is also within the scope of this invention. Although only 2 dielectric layers in the stacked gate dielectrics are shown, the exemplary embodiment is for discussion purposes. It should be noted that the stacked gate dielectrics can comprise any numbers of alternating dielectric layers, e.g., negative-capacitance dielectric layer—conventional dielectric layer superlattices, which are within the scope of the invention.

In some embodiments, the substrate302is a silicon substrate. Alternatively, the substrate302may include other elementary semiconductor material such as, for example, germanium. The substrate302may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate302may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate302includes an epitaxial layer. For example, the substrate302may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the substrate302may include a semiconductor-on-insulator (SOI) structure. For example, the substrate302may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.

In some embodiments, the substrate302also includes various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, lightly doped region (LDD), heavily doped source and drain (S/D) terminals304-1/304-2, and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a CMOS field-effect transistor (CMOS-FET), imaging sensor, and/or light emitting diode (LED). The substrate302may further include other functional features such as a resistor or a capacitor formed in and on the substrate. The substrate302further includes lateral isolation features provided to separate various devices formed in the substrate302, for example shallow trench isolation (STI). The various devices in the substrate302further include silicide disposed on S/D terminals, gate terminal and other device features for reduced contact resistance and enhance process compatibility when coupled between devices through metal contacts312-S/312-D/312-G. In some embodiments, the distance between the source and the drain terminal is the channel length328.

In some embodiment, at least one conductive feature is included in the substrate302. In some embodiments, the at least one conductive feature can be a source304-1, drain304-2, or gate terminals310. Alternatively, the at least one conductive feature may be a silicide feature disposed on a source, drain or gate electrode typically from a sintering process introduced by at least one of the processes including thermal heating, laser irradiation or ion beam mixing. The silicide feature may be formed on polysilicon gate (typically known as “polycide gate”) or on source/drain (typically known as “salicide”) by a self-aligned silicide technique. In another embodiment, the at least one conductive feature may include an electrode of a capacitor or one end of a resistor.

In the illustrated embodiment, at least three metal contacts312-G are configured to make electrical contact to the conductive gate310. In some embodiments, each of the at least three metal contacts has a width324and an enclosure distance326, wherein the enclosure distance326is defined as a distance between the edge of the metal contacts312-G to the edge of the conductive gate310. The at least three metal contacts312-G are configured in a row with a spacing330between two of the neighboring metal contacts. In some embodiments, a first ratio between the spacing330and the first thickness320of the first dielectric layer306is in a range of 0.01-100; a second ratio between the spacing330and the second thickness322of the second dielectric layer308is in a range of 0.1-10000; a third ratio between the spacing330and the channel width334is in a range of 0.1-10000; a fourth ratio between the spacing330and the channel length332is in a range of 0.00001-1; a fifth ratio of the enclosure distance326and the second thickness322of the second dielectric layer308is in a range of 0.1-10000; a sixth ratio of the enclosure distance326and the channel width334is in a range of 0.1-10000; and a seventh ratio of the enclosure distance326and the channel length332is in a range of 0.1-10000.

The method700continues with operation704, in which the DC voltage is adjusted so as to tune the equivalent capacitance (Ceq) according to some embodiments. In one embodiment, a Radio Frequency (RF) switch module, includes, a switch circuit for switching between transmitting first signals from a transmitter unit to an antenna and transmitting second signals from the antenna to the receiver unit, wherein the switch circuit comprises a plurality of field effect transistors (FETs), wherein each of the plurality of FETs comprises stacked gate dielectrics and at least three metal contacts to a conductive gate, wherein the stacked gate dielectrics comprises at least one first dielectric layer, wherein the first dielectric layer comprises a negative-capacitance material.

In another embodiment, a semiconductor device, includes, a field effect transistor (FET), wherein the FET comprises stacked gate dielectrics and at least three metal contacts to a conductive gate, wherein the stacked gate dielectrics comprises at least one first dielectric layer, wherein the first dielectric layer comprises a negative-capacitance material.

In another embodiment, a method for operating a semiconductor device for alternately sending and receiving with an antenna, includes, transmitting first Radio Frequency (RF) signals from a transmitter unit to an antenna through a transmitter transmission line; and receiving second RF signals from the antenna to a receiver unit through a receiver transmission line, wherein each of the transmitting and receiving further includes, adjusting DC voltages on corresponding gate terminals of a plurality of field effect transistors (FETs) in an Radio Frequency (RF) switch; grounding corresponding body terminals of the plurality of FETs to ground; maintaining corresponding source terminals open; and coupling corresponding drain terminals to ground.

The foregoing outlines features of several embodiments so that those ordinary skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.