Patent ID: 12209009

Like reference numerals in different figures indicate like elements.

DETAILED DESCRIPTION

The application, in various aspects, addresses deficiencies associated with the fabrication and/or structure of MEMS devices.

In various aspects, the systems, devices, and methods result from or use vHF etching to etch away part of the silicon oxide in the BEOL of a CMOS process, thus releasing material existing in the BEOL that will constitute the MEMS device. The inventive approaches use a bottom metal plane and a top metal plane with an array of small holes to allow the vHF to go inside the MEMS cavity. A key inventive concept is to limit the overall MEMS size on the layout to between 50 μm and 150 μm, and preferably to less than 100 μm. For a given curvature radius of a MEMS device or element, the total curvature height depends on the horizontal size. Therefore, if the device is small enough, the curvature height will be limited, despite having a large vertical stress gradient.

A second inventive concept is the design of the springs. In order to have good performance with such small devices, small and soft springs are needed, while keeping also a small curvature height. These seem to be contradictory requirements. Short springs means that they will be very stiff, so sensitivity (performance) of the MEMS sensors will be reduced. To have soft springs we will need to minimize their thickness, which means minimizing metal stacking or not using it at all. But this will increase the vertical stress gradient, thus increasing quickly the total curvature height.

A preferred inventive solution to the spring design problem is to use not one but a set of at least three springs, distributed evenly around the device, rotated around the device central axis, so that by symmetry the MEMS device cannot be tilted after being released with the vHF etching.

In the case of an inertial sensor, the MEMS device includes a central proof mass, made with several metal stack up, so that it is quite flat compared to the springs around it. This proof mass may also be larger than the springs, in order to have enough sensitivity. If the spring or springs that hold it are curved, then if the proof mass is tilted, it will end up having a large curvature height, despite of the proof mass itself being relatively flat. However, if the springs are located evenly around it, and there are at least 3 of them, then the proof mass will experience a small vertical displacement due to the curvature of the springs, but it will be flat, hence not contributing to the total vertical height with its large size.

FIG.1shows a central and/or proof mass100of a MEMS device having three springs102,104, and106made and/or connected to and spaced evenly around its circumference. The proof mass100also includes an array of etching holes108. In some implementations, the central mass100will have a circular shape, and the springs102,104, and106around it will have a spiral shape, and be made with only one metal layer or a stack-up of just two metal layers, or more than two layers. Using circular and rounded shapes for the proof mass100, the springs102,104, and106, and in general for all or as many parts of the MEMS device as possible, avoids the high mechanical stress that would otherwise be accumulated on the straight angles of the device geometry. These rounded shapes then facilitate a balance of the stress on the springs102,104, and106, which leads to a horizontal tilt that we need for the central mass100when we use an array of at least three evenly distributed springs102,104, and106around it.

Although the number of springs can be increased, so that we can use four or more, and this would further help in achieving the horizontal tilt of the central proof mass100, certain implementations have only three springs, because otherwise the overall stiffness of the MEMS device would increase proportionally to the number of springs, thus reducing its sensitivity.

Within this application, we will use the term “inertial sensor” to refer to a variety of devices that sense acceleration. This may include at least an accelerometer, a motion detector and a bone conduction sensor. Their physical principle of operation is the same, but their difference is in the frequencies that they detect. So their bandwidth and whether they need to sense direct current (DC) or not, and also their resolution and/or sensitivity requirements.

Another implementation may use straight pairs of springs, located at opposite sides of the proof mass100, so that each pair of springs lies on the same straight line. This solution works because the residual stress of the metal lines is found to be tensile in most. CMOS processes, sometimes with the exception of the top most metal layer. This way the curvature height is minimized. However, this solution leads to a relatively high stiffness, which is also highly dependent on the device temperature. Therefore, it is a solution that may be applicable to some MEMS devices, especially when a high mechanical resonant frequency is needed, and when temperature dependence of the spring stiffness is not critical.

If the proof mass (e.g., in the case of a inertial sensor) or the central part of the MEMS devices attached to the springs, is thicker than the springs, thus being made of a larger stack-up of metal layers, then an preferred implementation is for the springs to be made using the upper metal layers, if we connect the central part of the MEMS or proof mass to the top metal plane. This will minimize the parasitic capacitance of the springs and the supporting external rings towards the lower metal plate.

FIG.2is an exploded view of the metal and via layers of a MEMS device200without showing the SiO2, passivation, and substrate.FIG.2describes an out-of-plane inertial sensor. It is built using a 6 metal BELL CMOS process. Metal layers are numbered M1 (bottom) to M6 (top). There are 5 via layers, numbered V1 (between M1 and M2) up to V5 (between M5 and M6), although V1 is not used in this particular design. The proof mass has a circular structure, it has three spiral springs evenly placed around it, and the diameter of the proof mass plus the springs is 50 μm. The proof mass is made with a stack-up of metal layers M2 to M5, and the springs stacking up metal layers M4 and M5. The proof mass has concentric rings, stopped at the etching holes that go vertically across it, made with via layers V2 to V4.

The top metal plane has the same diameter plus an external ring of 20 μm width around it, which is equivalent of a circle having 90 μm of diameter. There is an array of 0.8 μm holes spaced approximately 5 μm between the center of each two holes in both X and Y directions. The springs have a surrounding ring of 20 μm width around them, built on the same layers M4 and M5. There is an array of concentric vias joining these rings and the top metal plane on these rings. That is, they are implemented at layers V4 and V5.

There is a circular bottom metal plane made with M1, with a diameter of also 50 μm plus an exterior ring of 6 μm width, so smaller than the external rings of the top layers for the top metal plane and the support of the springs. Together the internal circle and the external ring are equivalent to a circle of 62 μm diameter. The difference between the internal circle and the external ring comes from the fact that after the vHF etching, the external ring is partially etched and the edges keep buried (and subjected) to the silicon oxide. The top passivation is opened with a circular shape of 50 μm, which is above the MEMS device.

MEMS device200includes M6 layer202, V5 layer204, M5 layer206, V4 layer208, M4 layer210, V3 layer212, M3 layer214, V2 layer216, M2 layer218, and M1 layer220. M6 layer202includes a top plate222with etching holes arranged in an array and a connection to an ASIC. V5 layer204includes an array of concentric via rings224extending over the outer metal. M5 layer206includes a proof mass top lid226with array of etching holes. Layer206also includes a portion of spiral springs228and an outer metal ring230. V4 layer208includes array232of concentric via rings extending over the outer metal, a portion of the spiral springs228that extends in the V4 layer208, and array236of concentric via rings extending over the proof mass and stopping at the etching hole locations while surrounding the hole locations with square rings. M4 layer210includes a proof mass plane238with an etching hole array, a portion of spiral springs228, and a portion of outer metal ring230. V3 layer212includes an array of concentric via rings244extending over the proof mass and stopping at the etching hole locations while surrounding the hole locations with square rings. M3 layer214includes proof mass metal plane246with an etching hole array. V2 layer216includes an array248of concentric via rings extending over the proof mass, stopping at the etching hole locations and surrounding them with square rings. M2 layer218include proof mass metal bottom lid250including an etching hole array. M1 layer220includes bottom metal plane252including a connection to an ASIC.

A preferred implementation for an accelerometer, using a 6 metal layer process, where M1 layer220is the bottom layer and M6 layer202is the top one, would be as follows. M1 layer220would be used to implement the bottom plane and M6 layer202the top metal plane, which would be shorted to the proof mass and springs. The proof mass would be implemented using a stack-up of M2 layer218to M5 layer206. And the springs228would be implemented using either only M5 layer206or a stack-up of M4 layer210and M5 layer206.

If we set the total diameter of the proof mass plus the springs, then there is an optimum for the length or maximum angle that the springs rotate. Longer springs (longer total angle) means that they will be softer, but the proof mass will be smaller. Shorter springs will allow for a larger proof mass but the springs will be stiffer. Therefore there is always an optimum, which will depend on the specific design and process properties. In general however it is difficult to build reliable devices and with good yield with springs having angles of more than 360°. That is, preferably each individual spring will not complete a turn around the circular proof mass.

Another parameter that affects design yield, performance and reliability is the spacing around the springs. That is, the horizontal spacing or gap existing at each point of the springs without any other spring, proof mass, anchor or any part of the device (except at the edges of the spring, as they start and end up being fused with the outer ring or anchor/wall and the proof mass or other MEMS part). This obviously needs to be at least equal to the minimum spacing set by the process design rule checking (DRC). However in practice we will set it to a higher value, between ×2 and ×10 of this minimum spacing set by the DRC of the process. A preferred value is ×5. For instance with a 180 nm process having a minimum gap DRC between metals of 300 nm, we will preferably set this horizontal spacing for the springs as 1.5 μm. The trade-off here is that for very large spacing we will reduce sensitivity and/or performance, because we will reduce more the proof mass area and hence mass for the same spring length (hence to achieve a given softness/stiffness for the springs). But reducing this horizontal spacing between the springs it will lead to poor yield and reliability.

Another key aspect of the springs, especially important when they are soft, such as in the case when we use a set of three or more spiral springs evenly distributed around a central proof mass, is to make them short enough, compared to the displacement (both vertical, so out-of-plane, and horizontal, so in-plane). Since we have small proof mass and we want very soft springs in order to achieve enough sensitivity, this would in principle be prone to stiction issues, which would lead to very poor reliability for these MEMS devices.

FIG.3is a zoomed view300of the M4 layer210of the MEMS device ofFIG.2. M4 layer210includes a 50 μm circle metal plane302inside the proof mass, spiral springs306, an external 20 μm width ring304partially buried into silicon oxide at the outside part after vHF etching to support the springs and hence the proof mass, and array308of etching holes going through the proof mass.

FIG.4is a zoomed view400of the M5 layer206of the MEMS device ofFIG.2. M5 layer400includes proof mass top lid402having an array of etching holes, spiral springs404, and outer metal ring406.

FIG.5is a zoomed view500of the V4 layer208of the MEMS device ofFIG.2. V4 layer500includes an array502of concentric via rings extending over the proof mass, stopping at each etching hole504location and surrounding each hole504with a square ring. Layer500also includes an array508of the concentric via rings extending over the outer metal.

FIG.6is a non exploded 3D view600of the metal layers (so without showing the remaining silicon oxide, passivation and substrate) such as M6 layer202including etching holes of the MEMS device ofFIG.2. Layer202includes an array602of etching holes, an outer ring604, a connection606to the ASIC (upper electrode and proof mass). M1 layer220includes a lower electrode connection608to the ASIC.

FIG.7shows a side view700of the metal layers M1-M6 and via layers V2-V5 (because V1 is empty) of the MEMS device ofFIG.2including connection702to the ASIC (upper electrode and proof mass), top metal plane704, outer ring706, proof mass708, bottom metal plane710, and lower electrode connection712to the ASIC.

FIG.8is cross-sectional schematic diagram800of the MEMS device ofFIGS.2,6, and7. Diagram800shows passivation layer802, passivation opening804, springs806, etching hole array808, outer metal ring810, M6 layer812, V5 layer814. M5 layer816, V4 layer818, M4 layer820, SiO2 deposits 822, M1 layer824. V3 layer826, M3 layer828, V2 layer830, M2 layer832, bottom metal plane834, proof mass836, array838of concentric via rings inside proof mass836, and array840of concentric via rings along the outer metal ring810.

MEMS devices are designed to operate in the linear region. This is because they have large dimensions, with large springs to make them soft enough despite their thickness, and the maximum displacement they can have, covering all the gap they have above, below, in front of or on a side, is very small. This way the MEMS spring obeys the Hook law, having a constant stiffness, that is generating a mechanical restoring force that is proportional with the displacement.

In certain instances, given that the displacement is large compared to the spring length, the mechanical restoring force starts being proportional to the displacement, but after a given initial displacement it is no longer linear and it increases faster. This way, although the springs are soft for small displacements around the equilibrium point, which is where the sensor will operate thus having very good sensitivity, in case that the proof mass experiences a larger displacement, for instance if submitted to a shock or strong vibration, touching the surrounding walls, roof or floor, the mechanical restoring force would be much larger at that point. This way the MEMS devices go back to the equilibrium position and detach from the stiction forces thanks to this increased mechanical restoring force at the point of contact.

In a more detailed view of this phenomenon, all springs are non-linear. However while other MEMS devices experience only small displacements, the devices described herein may experience larger displacements so that they enter into the non-linear region of the mechanical restoring force versus displacement before touching the surrounding walls, roof or floor.

We can count the length of the spring in two ways. One is the straight distance from one end to the other. The second measure is the whole distance along all of the length of the spring, following its meanders and curves. We will consider the longest of these measurements to be the “length” of the spring. In the implementations described herein, the shortest ratio between the minimal displacement that can lead to the spring touching a surrounding wall, roof or floor, and the length of any spring, is at least 1%, while in some designs it may be 5% or even 10%. This principle can also work for lower ratios, but then the robustness may not be sufficient. However, 0.5% or even 0.1% may provide sufficient results depending on the particular process and overall implementation. Such a short ratio is a factor to the MEMS devices described herein, not found in other MEMS designs, which allows for implementations of soft springs and short gaps to realize high performance devices able to be packaged with all packaging technologies, including WLCSP, while at the same time having high yield and reliability.

Another inventive concept includes the design of the vertical walls, or more precisely, the definition of the MEMS area, or the limit of the lateral etching of the silicon oxide, and the mechanical anchors or supports of the MEMS. As explained before, other designs use vertical metal walls or anchors.

On the first case, using vertical metallic walls, we cannot use a top metal layer and/or a bottom metal layer to seal the device from the top and/or bottom. This means that we will need a special CMOS process without doped silicon below the lowest metal layer of the BEOL, and/or a special, more expensive packaging technique like a laminate substrate to properly protect the MEMS cavity from the top, and usually also a more expensive post processing etching sequence. This may be avoided totally or partially if the MEMS device is allowed to have the top and bottom metal planes electrically shorted with the surrounding walls, which usually would not be possible.

The second option, using anchors, although it disconnects electrically the top and bottom metal layers, it creates a large parasitic electrical capacitance between them, that degrades the device performance. Furthermore, any attempt to improve the performance reducing this parasitic capacitance, by means of reducing the anchor structure or increasing the vHF etching time, reduces the yield and reliability of the device.

The present inventive devices have neither the vertical metal walls connecting the top and bottom metal planes, nor the capacitive anchors. Instead there are two different solutions that these devices use. One solution is to extend the parts of the MEMS device located in between the top and bottom metal planes or electrodes, such as the springs, but it can also be other electrodes, so that they end up buried into the silicon oxide, sufficiently spaced away in the horizontal direction that the vHF does not reach there. In practice, we have seen that there is no need for a long distance. For a 180 nm CMOS node, it is enough to have 20 μm of metal around the MEMS device. Hence, there is metal placed around the MEMS device that is released, which holds it because the outer edge of it has silicon oxide around and/or adjacent to it that it is not etched way. Preferably this surrounding metal has a circular shape on its outer edge, but other shapes would be implemented.

In the previous solution, we had at least three electrical disconnected parts, where the top metal plane, the bottom metal plane and the part of the MEMS device in between them, are electrically disconnected, and more parts could be made electrically disconnected. An alternative implementation may be applied where, instead of having three or more electrically disconnected parts, there are only two. In this instance, part of the MEMS device may be attached in between the top and bottom metal planes to one of them by means of a vertical metal wall, but not to the other. In some implementations, the MEMS device is connected to the top one. This is because the top metal layer is usually less flat and more curved than the bottom metal layer. This is because the bottom metal layer is not detached from the underlying silicon oxide. In order to increase the mechanical consistency of these external rings, we can use an array of vias to join them. To make them even more robust, we can use instead of a regular square via array, an array of concentric via rings, like those used inside the proof mass. However in this case there will be no holes going through the external rings as it happens with the proof mass, and hence the rings will not have to be disrupted and they can be continuous.

Another implementation aspect that may be applied for these last two options, is that, since we do not use neither vertical metal walls shorting the top and bottom metal planes, nor we join them with capacitive anchors, we can then reduce the size of the bottom metal plane, compared to the size of the top metal plane that will be larger. The reason for this is that the lateral over-etching will be larger for the top metal than for the bottom metal layer, because in order to etch the bottom metal layer, vHF needs to etch down first to get there first. The lateral over-etching is the distance that goes from the outermost edge of the passivation opening window above the MEMS device that we need to release, until the outermost location where there is silicon oxide etched after the vHF post processing step. That is, since we do not use metal vertical walls shorting from top to bottom nor use capacitive anchors, but instead we surround the MEMS device by metal area that extends into the silicon oxide around, part of this metal area will have its surrounding silicon oxide etched away during the vHF step while beyond some point it will no longer be etched.

With this approach, we reduce the parasitic capacitance between the top and bottom metal planes, which is also the parasitic capacitance between the top or bottom metal planes and the moveable part of the MEMS device, in case of using the second approach disclosed above, that is when we shorten the part between the top and bottom metal planes with one of these vertical planes or connections. This reduction of the parasitic capacitance results in improved device sensitivity or performance.

The size for a reduction of the width of the external ring at the lower metal plate compared to the top one will depend on the CMOS process and overall design. But, in some implementations, it will be between 10% and 50%, with a preferred value of 30%. In some implementations, a width for the outer ring at the top metal plate is 20 μm, which means that the external ring width at the bottom metal plate may have a preferred size of 6 μm. If the central disc (proof mass plus springs) has a diameter of 50 μm, then the total size of the top plate may have a diameter of 90 μm, and the diameter for the whole bottom plate may have a diameter of 62 μm.

If we anchor the part in between the top and bottom metal planes with metal areas extending around this part that end up buried into the unetched silicon oxide, then we can also make them with a size that is smaller than the top metal plane but larger than the bottom metal plane. Because in this case their over-etching, it will be somewhat in between the top and bottom metal planes. In some implementations, the external ring width for this middle plate or plates it will be between 30%© and 70% the width of the ring for the top metal plane. In one implementation, the value would be 50%. However it will ultimately depend on the specific CMOS process and the overall design. If the top metal plane has a circular shape, it may include an internal disc adjacent to an external ring surrounding it. The internal disc may have an array of holes in it to allow the vHF to go inside the MEMS cavity, while the external ring is solid (with the possible exception explained below for building a trench to isolate most of this external ring electrically).

The extension of the internal disc is in principle the extension of the MEMS that we want to release with the vHF. However another inventive concept is to reduce the extension of the inner disc, thus not placing release holes around the outer part of the MEMS that needs to be released. Since vHF can travel a relatively long distance, all the MEMS will be released and we will minimize the over-etching on the external ring in all the metal layers, thus being able to reduce the sizes of these external rings. This will reduce the parasitic capacitance between the top and bottom metal plates, thus improving the performance of the MEMS, In case of using this reduced extension for the release holes, the passivation opening can be reduced also, since we only need to open it above the area having the array of holes.

The reduction of the internal disc that we can be implemented will depend on the CMOS process, but in certain implementations it will be between 2 μm and 20 μm on each side, with a preferred value of 6 μm. That is the disc diameter will be reduced between 4 μm and 40 μm, with a preferred diameter reduction of 12 μm. Implementing this reduction of the internal disc can reduce the external ring to the same value at all the metal layers that have such external ring. For clarification, although the internal disc and external ring is discussed, in practice the layout of the top metal layer will be a single disc. Then the etching holes array will be located in the center, covering an area that is defined by the size of the internal disc. Hence, the surrounding solid area without etching holes may be referred to as the external ring. Also for clarification, when we say that we reduce the internal disc, this does not affect the size for the proof mass, springs or other parts of the MEMS device that need to be released. The internal disc here it defines only the area above the MEMS device or parts that need to be released, that have an array of etching holes.

The above descriptions are valid also in the case of having several electrically disconnected parts in between the top and bottom metal layers. In such instances, each one will have its own metal extensions buried into the silicon oxide, and they will all be electrically disconnected between them, although there will always be some electrical parasitic capacitances.

Although the preferred approach is to have this exterior metal area to support the MEMS parts in between the top and bottom metal planes, surrounding all the released MEMS inside, to provide better mechanical consistency, it is not strictly necessary. This can be useful especially in the case disclosed above where there are two or more electrically disconnected MEMS parts in between the top and bottom metal layers. One example of this is for an in-plane inertial sensor, where there are several lateral electrodes positioned to sense acceleration in different directions.

Another variant that reduces the parasitic electrical capacitance between the top metal plane (and also the middle part of the MEMS device if electrically shorted to it by means of for example a vertical metal connection to it) and the bottom metal plane, is to add a very short trench around all of the top metal plane at a certain distance from the MEMS that needs to be released. In some implementations, this trench is located at half of the over-etching distance. In one configuration, this is at about 10 μm, as the overall length of this metal area around the MEMS is of about 20 μm. But the distance can be made shorter, down to 5 μm or even less, than to zero. Preferably it will be located at a distance between 5 μm and 15 μm. And the extension of the top metal plate may be a distance of about 20 μm. But, it could be between 5 μm and 30 μm, depending on the specific CMOS process properties, and the overall MEMS design and the required vHF properties and recipe.

The width of the trench should be minimal, as allowed by the process. This width may be 0.8 μm but, in some implementations, will fall between 0.5 μm and 2 μm, depending on the process and especially the thickness of the top metal layer. A metal ring may be implemented beyond this trench to sustain the passivation. With this trench, the outer ring is divided into two parts, one inside the other, that will be electrically disconnected, and mechanically disconnected as well. Although there will be some parasitic electrical capacitance between them and also they will ultimately be connected to the silicon oxide and hence they will not move relative one to the other.

Hence, it could be questioned why we need to keep the outside part of this divided outer ring. The reason is that there will be over-etching during the vHF post processing step, so that the silicon oxide located between the passivation and this top metal layer will be etched away, leaving the passivation very fragile. For this reason, it is better to keep the outer most metal ring, in case the passivation breaks so that it can be supported. However, depending on the process properties and overall design, it might be possible just to remove this external part of the outer ring, and instead of building a trench for the outer ring, just reduce its diameter. This would reduce the parasitic capacitances even more.

A preferred implementation will have a short vertical metal wall surrounding the MEMS device and connected to the top metal plane. This vertical metal wall may or may not be connected to a moving part of the MEMS located in between the top and the bottom metal planes, such as the spring anchors. The purpose of this short (i.e. not going down to the bottom metal plane) wall is to block the vHF from etching horizontally under the top metal plane towards the outer edges of it, forcing the vHF to go down the vertical wall first and then back upwards to be able to etch under the top metal plane towards the outer edges. Depending on the implementation, this short vertical metal wall can also provide mechanical consistency and/or an electrical connection to other parts of the MEMS device, such as for instance the anchors of the springs.

Another implementation to achieve a mechanical connection without electrically shorting two parts of the MEMS without using the capacitive anchors, is to use a MIM layer in the MEMS process. This layer is usually not etched away with vHF, or at least etched slowly, although it depends on the specific CMOS process. This provides a more compact solution than the capacitive anchors. However the electrical capacitance tends to be larger, and the mechanical robustness may not be adequate. However it might still be useful in some implementations, depending on the MEMS device, process and overall design. For some implementations, it may also be useful to use horizontal capacitive anchors instead of vertical capacitive anchors. In some configurations, a mixed design may be implemented, while implementing feedthroughs to pass connections across MEMS metal walls or planes using the same design principle like capacitive anchors of any type or a combination of types.

The array of holes at the top metal plane222will be as small as possible. They may be smaller than what is allowed by the DRC of the process, but big enough to make sure that they are open through all the top metal thickness. This minimum size will depend on the specific CMOS process and especially on the top metal thickness. In some implementations, the size is 0.8 μm in width. Below this it is usually difficult that they open completely, which would lead to a low yield in production. Larger values may not be properly filled when we apply the sealing layer as explained later. So there is a trade-off and we cannot have neither too small holes that would not open when patterning the top metal layer during the CMOS process, nor too big that would not be properly sealed later during the packaging. Hence, in some implementations, the hole size will be between 0.5 μm and 1.5 μm, with a preferred value of 0.8 μm. However depending on the CMOS process, the top metal thickness, and the sealing material, thickness and process being used, the etching hole size may vary. Given that the holes are so small in some implementations, they will be drawn as square holes, because in reality any other shape would not make any difference, as we will be forcing the resolution of the process, and they will be partially rounded anyway during the manufacturing of the device.

The separation between the holes on the top metal plane, e.g., top plate222, may be similar to the vertical length of the vertical distance from the top to the bottom metal layers M1 to M6. In some configurations, the etching holes are spaced horizontally on the top metal layer222up to a distance of at least twice this vertical distance between M1 and M6. In some implementations, the distance may be greater, given that vHF etches slowly in the vertical direction compared to the horizontal direction, due to the multiple oxide sublayers with different densities and etching speeds. Because the goal is to make sure that we etch properly all the volume inside the MEMS cavity, the holes may be placed close enough, but at the same time as much as possible to prevent formation of a weak top metal plane with so many holes and little metal remaining, which may not be able to withstand the sealing on top of it when the device is packaged, as explained later herein.

We have found experimentally that a sufficient value is to have the etching holes spaced a distance between 50% and 200% of the height of the metal stack. This height is counted from the lowest point of the bottom metal layer M1 up to the highest point of the top metal layer, e.g., M6. A preferred value is to separate the holes a distance equal to this height (e.g., 100%). The hole distance is measured from the center of one hole to the center of another hole in both the horizontal (X) and vertical (Y) directions.

In order to allow the vHF to go down to the lowest level of silicon oxide so that all the silicon oxide that needs to be removed is properly etched in all the cavity, the same array of holes is implemented that goes through all the MEMS device inside the cavity. This might be shifted laterally with respect to the holes on the top metal plane, although the preferred implementation will be just to place them at the same locations. If these holes go through structures that do have silicon oxide trapped inside, such as the proof mass, these holes may be surrounded with via walls, to avoid the vHF going inside through these holes and etching away the silicon oxide that we want to keep unetched. Given the small size of these holes, which may be made preferably with square shapes, these via barriers may be implemented as square rings.

A fourth inventive concept is the usage of the sealing layer existing in the WLCSP process, also referred to as repassivation, which is typically made with Polyimide (PI), but it could also be Benzocyclobuten (BCB) or others, to seal the MEMS cavity. This avoids the need for a specific aluminum sputtering and patterning process, reducing the complexity and cost of the post-processing, which is further reduced only to the vHF etching and post backing. In addition to this, using PI or BCB has been seen to offer a better seal, covering better the array of holes on the top metal layer. In contrast aluminum sputtering requires a very thick deposition, and even then, due to the conformality of the deposition, some holes may not be properly sealed. This does not happen with PI, which seals all the holes very well. In instances involving another type of package not being WLCSP, a process could still apply a PI or BCB or other coating and patterning (even aluminum sputtering, although it would not be ideal, but it could be done with enough thickness and the proper set of parameters), and then proceed with whatever packaging process.

Another key inventive concept includes not using metal filling structures within the MEMS cavity. In order to compensate for the metal residual stress, CMOS designs need to have a constant metal density across all the area of the ASIC. In order to achieve this, once the ASIC design is finalized, an automatic process called “metal filling” is performed, which fills all the empty areas with random small metal shapes, in order to achieve the required target metal density. This metal filing must not be performed within the MEMS cavity. Otherwise after applying the vHF all these tiny metal filing structures would be released and they would attach by stiction to the MEMS devices, preventing it from working properly, or not letting it to work at all.

All the explanations given in this application can be applied to different CMOS nodes, to different metal stacks and even different solid state semiconductor processes. Also when we describe the top metal layer and the bottom metal layer, these are usually the top most and the bottom most metal layers in the process layer stack. However, it may be applicable to other metal layers. In the case of building an inertial sensor in a 6 metal layer process, we will usually need all the metal layers available in order to maximize the thickness and hence the mass of the sensor proof mass. However if the process has more metal layers available, or if we build another type of MEMS device, or even for a inertial sensor if we can manage to get the required specifications, we may not need to use all the metal layers available in the metal stack. In this case, we will preferably use those located on the top, thus leaving the metal layers located at the bottom to be used for the ASIC to make electrical connections into the ASIC. In this case, there would not be any dedicated area to implement the MEMS, but instead the MEMS would be implemented above the ASIC.

In all cases, the active area (FEOL) below the MEMS may be used to implement the ASIC. However if there are no metal layers available to be used for the connections, because they are all used to implement the MEMS, then it will be difficult to implement a useful part of the ASIC below the MEMS. But, depending on the process and the specific ASIC design, it may be useful to implement large transistors or other circuitry requiring little wiring, and/or polysilicon lines if available may be used for this wiring. When not all the metal layers of the process stack are used to implement the MEMS, then all the explanations of this application should be understood in the following way. The “top” and the “bottom” metal layers are not then the top most and bottom most of the metal stack, but they are then the top most and the bottom most of the metal layers used to implement the MEMS device. Although the preferred embodiment includes using circular and round shapes, the disclosed inventions can be applied to other types of shapes.

Yet another key inventive concept includes the sensing electronics to interface the MEMS, when they are capacitive MEMS sensors such as, without limitation, accelerometers, bone conduction sensors, motion detectors, ultra-sound sensors or any other capacitive sensor. In certain implementations, the MEMS capacitive sensors herein include a uniquely small capacitance. This is because of the small size unique feature, and also the minimal parasitic capacitance, resulting from the several concepts explained previously. Also, because of the proximity of the ASIC, attached to the MEMS edge, and without needing to wire the MEMS to another die where the ASIC would be located, and not even having to be connected to the top of the wafer where the ASIC would be placed in a wafer bonding scheme, or in the case of building the MEMS above the ASIC CMOS wafer.

In some implementations, the capacitance of the present MEMS sensors is in the order of 10 fF to 100 fF, or about 50 fF. This is about 100 times smaller than commercial MEMS devices for consumer electronics. This allows for implementation of a completely different sensing scheme that would not be feasible with other MEMS devices because it would imply too much power consumption.

In some configurations, the sensing of the MEMS capacitance is done by means of building a ring oscillator, where at least one of the capacitances of the loop is a MEMS device as described herein. This ring oscillator will feed a counter that will be read and reset every sample period. The output of the counter will already be digital and it will output the value of the capacitance. This approach has many technical advantages. First, it simplifies the analog design, being all digital, with the only exception of the ring oscillator. This means that there are many analog blocks that we would otherwise be needed, that is avoided here, such as a transconductance amplifier, programmable gain amplifier, A/D converter, analog filters, chopper and capacitance mismatch compensation, among others. This simplification has many technical advantages: smaller ASIC area, so lower cost in production, reduced design time so faster time to market and lower development cost, easy porting to other CMOS nodes and processes, and lower power consumption.

The lower power consumption results from avoiding so many analog blocks that would be power hungry. In exchange for these blocks, however, the process will include charging and discharging continuously the MEMS sensor capacitance at a very high frequency, which may be between 10 MHz to 100 MHz, but depend on the MEMS design, CMOS process, and target specs for the sensor. This would consume too much power for the usual capacitances in the order of several pF. But for the present MEMS sensors having capacitances in the order of ×100 times or more lower, this will not imply more but actually less power consumption, making the inventive sensors very power efficient, in addition to the other advantages mentioned above for this sensing schema.

The ring oscillator may vary its frequency depending on many factors like supply voltage and its noise, temperature, and also process variations. To compensate for this, a second ring oscillator may be implemented that uses another MEMS device built very close to the first one, so that it will see almost the same process, voltage and temperature variations. This second MEMS device (or devices if more than one MEMS is included into the ring oscillator loop), will be slightly different, with a stiffer spring. Preferably, this will be made using a wider and/or thicker (i.e., using more metal stack-up) spring. This way the capacitance reading from the counter connected to this second sensor will move very little due to the magnitude that the sensor measures (e.g., acceleration in the case of an accelerometer), but it will change in the same way as the first one due to all the other factors, like supply voltage, process and temperature variations.

In one implementation, the two ring oscillators actuate a different counter each, until the second one reaches a predetermined value. In that case, we will read the first counter, which will give us the value of the magnitude being sensed, and then we will reset the two counters and start counting again. This predetermined value may be programmable, so that we can define different sampling frequencies. When the sampling frequency is low, the ring oscillators and/or the counters will be disabled between samples, thus minimizing power consumption. In some implementations, a third digital counter is included, with a very slow digital clock, to activate the device every time that a new sample needs to be acquired.

In some implementations, to increase the proof mass without increasing its size, metal walls are built and/or formed around all the perimeter of the MEMS device. In this way, silicon oxide is trapped inside the proof mass, and it is not etched away by the vHF. Furthermore, the proof mass with plenty of vias because these are made with tungsten, which has a higher density than silicon oxide and aluminum, which is the material of the metal layers. In order to further increase the effective density and the total mass of the proof mass, larger and closer via arrays may be implemented than what is allowed by the DRC of the process. In the case of a circular shaped proof mass, we can use also concentric via rings, spaced with the same distance than the thickness of the rings, preferably making this distance and rings width equal to the via size and via spacing defined by the CMOS process DRCs. It happens that although the vias of a CMOS process typically need to be squares of a fixed size, in practice we can extend these vias in one dimension, but at least we need to keep the specified via size in the other dimension. Otherwise the wafer would not be properly manufactured. Since we will need to make holes across the proof mass, these circular rings may have to be interrupted around the holes. Other shapes may be implemented for both the proof mass and the rings or via filing structures inside it.

Another key inventive concept includes modification of the pads. This is because there will be passivation openings not only above the MEMS devices, but also above each of the pads, i.e., vertically aligned with the pads. That is a reason why there is a passivation opening in the CMOS process. This means that when the vHF is applied post processing, the oxide under the passivation (i.e., between the passivation and the top metal layer) will be etched away. If the top metal layer at the pad is not large enough, the silicon etching will go beyond it and etch under the passivation without metal underneath. If this happens a lot of silicon oxide around the pad will be etched away, and the top passivation will end up having no oxide below. As a consequence the passivation can break and also a lot of silicon oxide can be etched away, ruining part of the ASIC electronic circuitry. An implementation to solve this technical problem is to extend at least the top metal layer (and if we extend more or all the other metal layers even better to provide better consistency) more than with a conventional pad design. This extension will depend on the details of the specific process and vHF etching that is applied. In some implementations, the metal will have a lateral extension of between 15 μm and 25 μm beyond the passivation opening in all directions. In one implementation, this extension will be 20 μm. There is no need to use rounded shapes, so, in various implementations, the pad will keep having a square design for the passivation opening, and so also the metals that define it. However other shapes would also be implemented.

Most of the inventive concepts disclosed herein can be applied to many different devices, including, but not limited to, inertial sensors, gyroscopes, pressure sensors, ultra-sound sensors and transducers like CMUTs, loudspeakers, magnetometers and compasses, microphones, RF switches, tunable capacitors, RF inductors, temperature sensors, and many more. To avoid requiring a CMOS foundry to increase the silicon content of the passivation, we can use, for example, a special recipe and/or equipment developed by, for example, Memsstar (Scottland). After the vHF etching step we bake the wafer, in order to sublimate the fluorine residues.

Thanks to the smaller size and cost, and higher performance of the MEMS devices disclosed herein, plus their high volume production capability and short time to market, the present inventive concepts enable building of smaller and higher performance smartphones, wearabies and earbuds, having more functionality and longer life and autonomy thanks to having more space for a larger battery. These sensors are also an enabler for many Internet of Things (IoT) applications, where there is a requirement for ultra low cost and small sensors, produced in very large volumes, while having very low power consumption (high performance). Another application example would be RFIDs with sensors embedded.

FIG.9is an exploded view of the metal and via layers of an MEMS device900including lateral electrodes.FIG.9shows a variant of the implementation ofFIG.2to sense in plane acceleration including lateral electrodes around the bottom part of the proof mass where there are no springs. That is, the proof mass is made up with 4 metal layers, M2 to M5. The springs are made with metal layers M4 and M5, having outer metallic rings to support them. Therefore, the proof mass does not use the metals around it at layers M2 and M3. This way we can use layers M2 and M3 to build lateral electrodes for the proof mass. The shape of these lateral electrodes is essentially like the outer rings of the above metal layers (M4 and M5), but instead of a whole ring, there are two half rings. Each of these half rings is made with the two available metal layers (M2 and M3), stacked up together, which means that there is plenty of vias inside to join them. These vias are shaped as an array of concentric half rings.

The external diameter of these lateral electrodes is shorter than the outer ring of the upper metal layers. In this design it is made shorter also than the bottom metal plane, but an improvement would be to make the bottom metal plane diameter smaller than the outer diameter of these lateral electrodes.

Since we keep having the bottom metal plane, we can still sense out-of-plane acceleration as well. Therefore, the MEMS device has several electrodes, which allow for the sensing of 1, 2 or even the 3 axis altogether with the same device. This is enabled if instead of dividing these lateral electrodes in half rings, they are divided into quarter rings. Furthermore, for the X and Y axis (i.e., in-plane acceleration), differential capacitances may be implemented. While this design is for an inertial sensor, the same design principle (electrodes, springs supports, and so on) may be used to implement other types of capacitive sensors and actuators.

MEMS device900includes M6 layer902, V5 layer904, M5 layer906, V4 layer908, M4 layer910, V3 layer912, M3 layer914, V2 layer916, M2 layer918, and M1 layer920. M6 layer902includes a top plate922with etching holes arranged in an array and a connection to an ASIC. V5 layer904includes an array of concentric via rings924extending over the outer metal. M5 layer906includes a proof mass top lid926with array of etching holes. Layer906also includes a portion of spiral springs928and an outer metal ring930. V4 layer908includes array932of concentric via rings extending over the outer metal, a portion of the spiral springs928that extends in the V4 layer908, and an array of concentric via rings936extending over the proof mass stopping at the etching hole locations and surrounding them with square rings. M4 layer910includes a proof mass plane938, a portion of spiral springs928, and a portion of outer metal ring930. V3 layer912includes an array of concentric via rings944extending over the proof mass and stopping at the etching hole locations while surrounding the hole locations with square rings. M3 layer914includes proof mass metal plane946with an etching hole array and lateral electrodes954with connections to the ASIC. V2 layer916includes an array948of concentric via rings extending over the proof mass, stopping at the etching hole locations and surrounding them with square rings. V2 layer916also includes array956of concentric via half rings extending over the lateral electrodes. M2 layer918includes proof mass metal bottom lid950having an etching hole array. M2 layer918also includes lateral electrodes958. M1 layer920includes bottom metal plane952including a connection to an ASIC.

Elements or steps of different implementations described may be combined to form other implementations not specifically set forth previously. Elements or steps may be left out of the systems or processes described previously without adversely affecting their operation or the operation of the system in general. Furthermore, various separate elements or steps may be combined into one or more individual elements or steps to perform the functions described in this specification.

Other implementations not specifically described in this specification are also within the scope of the following claims.