Patent ID: 12192663

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

In order for the content of the disclosure to be more comprehensible, the following specific embodiments are given as examples according to which the disclosure can indeed be implemented. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and the embodiments represent the same or similar parts.

FIG.1is a schematic circuit diagram of an image sensor according to an embodiment of the disclosure. Referring toFIG.1, the image sensor includes a timing controller110, multiple pixel driving circuit groups120_1to120_n, a pixel array130, multiple inverters140_0_0to140_0_7and141_0to141_n, and multiple potential droppers150_0to150_n, where n is an integer greater than or equal to 0. The pixel driving circuit group120_1includes pixel driving circuits121_0_0to121_0_7. The number of pixel driving circuits of one pixel driving circuit group may be 8. By analogy, the pixel driving circuit group120_nincludes pixel driving circuits121_n_0to121_n_7. In the embodiment, the timing controller110is coupled to the pixel driving circuits121_0_0to121_0_7, the inverters140_0_0to140_0_7and141_0to141_n, and the potential droppers150_0to150_nthrough multiple signal lines. The pixel driving circuits121_0_0to121_0_7are respectively coupled to multiple pixel circuits in the pixel array130to drive the pixel circuits.

In the embodiment, the timing controller110outputs multiple first enabling signals tx_en_p<0> to tx_en_p<8n+7> to the pixel driving circuits121_0_0to121_n_7through multiple signal lines, and outputs multiple second enabling signals tx_en_m<0> to tx_en_m<8n+7> to the pixel driving circuits121_0_0to121_n_7by the inverters140_0_0to140_0_7. In the embodiment, the timing controller110also outputs multiple first original control signals tg_gnd_p<0> to tg_gnd_p<n> to the potential droppers150_0to150_nthrough other signal lines, and also outputs multiple second original control signals n_tg_gnd_p<0> to n_tg_gnd_p<n> to the potential droppers150_0to150_nby the inverters141_0to141_n.

In the embodiment, the potential droppers150_0to150_nmay generate multiple first control signals tg_gnd<0> to tg_gnd<n> and multiple second control signals n_tg_gnd<0> to n_tg_gnd<n> to the pixel driving circuits121_0_0to121_n_7according to the first original control signals tg_gnd_p<0> to tg_gnd_p<n> and the second original control signals n_tg_gnd_p<0> to n_tg_gnd_p<n>. Signal waveforms of the first control signals tg_gnd_p<0> to tg_gnd_p<n> are respectively inverted to signal waveforms of the corresponding second control signals n_tg_gnd_p<0> to n_tg_gnd_p<n>. In the embodiment, each of the potential droppers150_0to150_nmay be coupled to multiple pixel driving circuits. Taking the potential dropper150_0as an example, the potential dropper150_0may provide the first control signal tg_gnd<0> and the second control signal n_tg_gnd<0> to the pixel driving circuits121_0_0to121_0_7.

In the embodiment, the pixel driving circuits121_0_0to121_n_7may generate driving signals tx_drv<0> to tx_drv<8n+7> according to the first enabling signals tx_en_p<0> to tx_en_p<7>, the second enabling signals tx_en_m<0> to tx_en_m<7>, the first control signals tg_gnd_p<0> to tg_gnd_p<n>, and the second control signals n_tg_gnd_p<0> to n_tg_gnd_p<n>, and output the driving signals tx_drv<0> to tx_drv<8n+7> to the pixel circuits in the pixel array130to drive the pixel circuits in the pixel array130.

Taking the pixel driving circuit121_0_0as an example, the timing controller110outputs the first enabling signal tx_en_p<0> to the pixel driving circuit121_0_0, and outputs the second enabling signal tx_en_m<0> to the pixel driving circuit121_0_0by the inverter140_0_0. The timing controller110also outputs the first original control signal tg_gnd_p<0> to the potential dropper150_0, and also outputs the second original control signal n_tg_gnd_p<0> to the potential dropper150_0by the inverter141_0. The potential droppers150_0to150_nmay generate the first control signal tg_gnd<0> and the second control signal n_tg_gnd<0> to the pixel driving circuit121_0_0according to the first original control signal tg_gnd_p<0> and the second original control signal n_tg_gnd_p<0>. Therefore, the pixel driving circuit121_0_0may generate the driving signal tx_drv<0> according to the first enabling signal tx_en_p<0>, the second enabling signal tx_en_m<0>, the first control signal tg_gnd_p<0>, and the second control signal n_tg_gnd_p<0>, and output the driving signal tx_drv<0> to the pixel circuit in the pixel array130to drive the pixel circuit in the pixel array130.

FIG.2is a schematic circuit diagram of a pixel driving circuit according to an embodiment of the disclosure. Referring toFIG.2, the pixel driving circuit of the disclosure may be implemented as a pixel driving circuit200shown inFIG.2. In the embodiment, the pixel driving circuit200may be a level shifter circuit. The pixel driving circuit200includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. A first terminal of the first transistor T1is coupled to a first voltage +V1(for example, +4 volts (V)). A control terminal of the first transistor T1is coupled to a second terminal of the first transistor T1. A first terminal of the second transistor T2is coupled to the first voltage +V1, and a control terminal of the second transistor T2is coupled to the control terminal of the first transistor T1and the second terminal of the first transistor T1. A first terminal of the third transistor T3is coupled to the second terminal of the first transistor T1, and a second terminal of the third transistor T3is coupled to a ground voltage agnd (for example, 0V). A first terminal of the fourth transistor T4is coupled to a second terminal of the second transistor T2and an output terminal of the pixel driving circuit200. A first terminal of the fifth transistor T5is coupled to a second terminal of the fourth transistor T4, and a second terminal of the fifth transistor T5is coupled to a second voltage −V2(for example, −1.2V). A first terminal of the sixth transistor T6is coupled to the second terminal of the fourth transistor T4. A second terminal of the sixth transistor T6is coupled to the ground voltage agnd. In the embodiment, the output terminal of the pixel driving circuit200is coupled to the pixel circuit, and the output terminal outputs a driving signal tx_drv to the pixel circuit.

In the embodiment, the first voltage +V1may be greater than the ground voltage agnd, and the second voltage −V2may be less than the ground voltage agnd. In the embodiment, the first transistor T1and the second transistor T2are P-type transistors (for example, P-type metal-oxide-semiconductor field-effect transistors (P-type MOSFETs)). The third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6are N-type transistors (for example, N-type MOSFETs).

FIG.3is a signal timing diagram of a driving signal and a ramp signal according to an embodiment of the disclosure. Referring toFIG.2andFIG.3, in the embodiment, the timing controller ofFIG.1may provide a first enabling signal tx_en_p to a control terminal of the third transistor T3, and provide a second enabling signal tx_en_m to a control terminal of the fourth transistor T4, wherein a signal waveform of the first enabling signal tx_en_p is inverted to a signal waveform of the second enabling signals tx_en_m. In the embodiment, the potential dropper ofFIG.1may provide a first control signal tg_gnd to a control terminal of the fifth transistor T5, and provide a second control signal n_tg_gnd to a control terminal of the sixth transistor T6, wherein a signal waveform of the first control signal tg_gnd is inverted to a signal waveform of the second control signal n_tg_gnd. In the embodiment, the pixel driving circuit200may generate the driving signal tx_drv shown inFIG.3according to the first enabling signal tx_en_p, the second enabling signal tx_en_m, the first control signal tg_gnd, and the second control signal n_tg_gnd. In the embodiment, swings of the first enabling signal tx_en_p and the second enabling signal tx_en_m are from the ground voltage (for example, 0V) to a third voltage. The third voltage is less than the first voltage +V1. In an embodiment, third voltage may, for example, be +1.2 volts (+1.2V).

As shown inFIG.3, the driving signal includes the same driving waveforms, and the driving waveforms respectively have a second-order voltage change. The second-order voltage change is sequentially a sequential voltage change result of the second voltage (−1.2V), the ground voltage (0V), the first voltage (4V), the ground voltage (0V), and the second voltage (−1.2V). Before time t0, during a period from time t3to time t4, and after time t7, the driving signal tx_drv is the second voltage (−1.2V). During a period from time t0to time t1, a period from time t2to time t3, a period from time t4to time t5, and a period from time t6to time t7, the driving signal tx_drv is the ground voltage (0V). During a period from time t1to time t2and a period from time t5to time t6, the driving signal tx_drv is the first voltage (4V).

FIG.4is a schematic circuit diagram of a potential dropper according to an embodiment of the disclosure. Referring toFIG.4, the potential reducer of the embodiment may be implemented as a potential reducer400shown inFIG.4. The potential dropper400includes transistors Ta, Tb, Tc, Td, Te, and Tf and inverters401and402. In the embodiment, a first terminal of the transistor Ta is coupled to a reference voltage LV (1.2V) with a low voltage potential. A control terminal of the transistor Ta receives a first original control signal tg_gnd_p. A first terminal of the transistor Tb is coupled to the reference voltage LV (1.2V) with a low voltage potential. A control terminal of the transistor Tb receives a second original control signal n_tg_gnd_p. A control terminal of the transistor Tc receives the first original control signal tg_gnd_p. A first terminal of the transistor Tc is coupled to a second terminal of the transistor Ta. A control terminal of the transistor Td receives the second original control signal n_tg_gnd_p. A first terminal of the transistor Td is coupled to a second terminal of the transistor Tb. A first terminal of the transistor Te is coupled to a second terminal of the transistor Tc. A control terminal of the transistor Te is coupled to the second terminal of the transistor Tb and the first terminal of the transistor Td. A second terminal of the transistor Te is coupled to a negative voltage NV (−1.2V). A first terminal of the transistor Tf is coupled to a second terminal of the transistor Td. A control terminal of the transistor Tf is coupled to the second terminal of the transistor Ta and the first terminal of the transistor Tc. A second terminal of the transistor Tf is coupled to the negative voltage NV (−1.2V). An input terminal of the inverter401is coupled to the second terminal of the transistor Tc and the first terminal of the transistor Te. An output terminal of the inverter401outputs the first control signal tg_gnd. An input terminal of the inverter402is coupled to the second terminal of the transistor Td and the first terminal of the transistor Tf. An output terminal of the inverter402outputs the second control signal n_tg_gnd. In the embodiment, the transistor Ta and the transistor Tb are P-type transistors, and the transistors Tc, Td, Te, and Tf are N-type transistors.

FIG.5is a schematic circuit diagram of a pixel circuit according to an embodiment of the disclosure. Referring toFIG.5, the pixel circuit of the disclosure may be implemented as a pixel circuit500shown inFIG.5. The pixel circuit500includes a pixel unit PD, a seventh transistor T7(emission transistor), an eighth transistor T8(source follower transistor), a ninth transistor T9(reset transistor), a tenth transistor T10(selection transistor), and a ramp capacitor Cr. In the embodiment, a first terminal of the seventh transistor T7is coupled to a terminal of the pixel unit PD, and a control terminal of the seventh transistor T7is coupled to the output terminal of the pixel driving circuit to receive the driving signal tx_drv. The other terminal of the pixel unit PD is coupled to the ground voltage agnd. A control terminal of the eighth transistor T8is coupled to a second terminal of the seventh transistor T7through a floating diffusion (FD) node NA. A first terminal of the eighth transistor T8is coupled to an input terminal sfd of a comparator. A second terminal of the eighth transistor T8is also coupled to a first terminal of the tenth transistor T10. A control terminal of the ninth transistor T9is coupled to a reset signal RST. A second terminal of the ninth transistor T9is coupled to the second terminal of the seventh transistor T7through the floating diffusion node NA. A first terminal of the ninth transistor T9is coupled to an operating voltage avdd. A control terminal of the tenth transistor T10is coupled to a selection signal SEL. A second terminal of the tenth transistor T10is coupled to a reference node sfs of the comparator. A terminal of the ramp capacitor Cr is coupled to the second terminal of the seventh transistor T7through the floating diffusion node NA. The other terminal of the ramp capacitor Cr receives a ramp signal RS. In the embodiment, the pixel unit PD may, for example, be a photodiode. The seventh transistor T7, the eighth transistor T8, and the ninth transistor T9may respectively be an N-type transistor.

Referring toFIG.3andFIG.5, the pixel circuit500may receive the driving signal tx_drv and the ramp signal RS shown inFIG.3. Before time t0, the driving signal tx_drv is at a negative voltage level (−1.2V) to effectively turn off the seventh transistor T7to prevent leakage current. During the period from time t0to time t1, the driving signal tx_drv is at a 0 voltage level to precharge the control terminal of the seventh transistor T7. During the period from time t1to time t2, the ninth transistor T9may be turned on according to the reset signal RST (for example, the reset signal RST is switched from a low voltage level to a high voltage level), and the driving signal tx_drv is a 4V pulse signal to quickly turn on the seventh transistor T7to reset the floating diffusion node NA. Then, during the period from time t2to time t3, the driving signal tx_drv returns to the 0 voltage level to turn off the seventh transistor T7. During the period from time t3to time t4, the driving signal tx_drv returns to the negative voltage level (−1.2V), and the ramp signal RS generates a small ramp waveform to read out a reset result (corresponding to a background noise) of the floating diffusion node NA (a voltage signal of the reset result is read out from the input terminal sfd of the comparator).

Then, during the period from time t4to time t5, the driving signal tx_drv is at the 0 voltage level to precharge the control terminal of the seventh transistor T7. During the period from time t5to time t6, the driving signal tx_drv is a 4V pulse signal to quickly turn on the seventh transistor T7to quickly transmit the sensing result of the pixel unit PD to the reset floating diffusion node NA. Then, during the period from time t6to time t7, the driving signal tx_drv returns to the 0 voltage level to turn off the seventh transistor T7. After time t7, the driving signal tx_drv returns to the negative voltage level (−1.2V), and the tenth transistor T10may be turned on according to the selection signal SEL (for example, the selection signal SEL is switched from a low voltage level to a high voltage level), and the ramp signal RS generates a large ramp waveform to read out the sensing result of the floating diffusion node NA (the voltage signal of the sensing result is read out from the input terminal sfd of the comparator). In this way, a back-end digital processing circuit may perform background noise removal processing on the sensing result according to the reset result corresponding to the background noise to obtain an accurate sensing result.

FIG.6is a schematic circuit diagram of a pixel circuit according to another embodiment of the disclosure. Referring toFIG.6, the pixel circuit of the disclosure may be implemented as a pixel circuit600shown inFIG.6. The pixel circuit600includes multiple pixel units PD0to PD3, multiple emission transistors TX0to TX3, the ramp capacitor Cr, a reset transistor Trst, a source follower transistor Tsf, and a selection transistor Tsel. In the embodiment, the pixel units PD0to PD3share the same floating diffusion node NA, and functions of the emission transistors TX0to TX3, the reset transistor Trst, the source follower transistor Tsf, and the ramp capacitor Cr may respectively correspond to those of the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the ramp capacitor Cr of the embodiment shown inFIG.5. The pixel units PD0to PD3may, for example, be photodiodes. The emission transistors TX0to TX3, the reset transistor Trst, the source follower transistor Tsf, and the selection transistor Tsel may respectively be an N-type transistor.

In the embodiment, a first terminal of the source follower transistor Tsf is coupled to a first input terminal sfd_inp of the comparator. A (first terminal) control terminal (gate) of the source follower transistor Tsf is coupled to the floating diffusion node NA. A first terminal of the selection transistor Tsel is coupled to a second terminal of the source follower transistor Tsf. A second terminal of the selection transistor Tsel is coupled to the reference node sfs of the comparator. A control terminal of the selection transistor Tsel receives a selection signal sel. A first terminal of the reset transistor Trst is coupled to the operating voltage avdd. A second terminal of the reset transistor Trst is coupled to the floating diffusion node NA. A control terminal of the reset transistor Trst receives a reset signal rst. The first terminal of the ramp capacitor Cr receives an up ramp signal RS_up. A second terminal of the ramp capacitor Cr is coupled to the floating diffusion node NA. First terminals of the pixel units PD0to PD3are coupled to the ground voltage agnd. Second terminals of the pixel units PD0to PD3are respectively coupled to first terminals of the emission transistors TX0to TX3. Second terminals of the emission transistors TX0to TX3are coupled to the floating diffusion node NA. Control terminals of the emission transistor TX0to TX3respectively receive emission signals tx<0> to tx<3>.

In the embodiment, the emission signals tx<0> to tx<3> may sequentially turn on the emission transistors TX0to TX3to sequentially transmit sensing signals of the pixel units PD0to PD3to the floating diffusion node NA. When the selection signal sel turns on the selection transistor Tsel, the source follower transistor Tsf may read out the sensing signal stored in the floating diffusion node NA to the first input terminal sfd_inp of the comparator in conjunction with the up ramp signal RS_up provided by the ramp capacitor Cr. In addition, during multiple respective periods when the sensing signals of the pixel units PD0to PD3are sequentially read out, the reset signal rst may turn on the reset transistor Trst at intervals to reset a voltage level of the floating diffusion node NA. Therefore, the pixel circuit600of the embodiment can effectively save the circuit area of the pixel circuit by the pixel units PD0to PD3sharing one floating diffusion node NA.

FIG.7is a schematic circuit diagram of a pixel circuit according to yet another embodiment of the disclosure. Referring toFIG.7, an image sensor700includes pixel groups710and720, a (first-stage) differential amplifier730, a (second-stage) amplifier740, capacitors751and752, and switches S1and S2. The pixel group710is coupled to a first input terminal (for example, a forward input terminal) sfd_inp and a reference node sfs of the differential amplifier730. The pixel group720is coupled to the reference node sfs and a second input terminal (for example, a reverse input terminal) sfd_inm of the differential amplifier730. A first output terminal output1of the differential amplifier730is coupled to a first input terminal of the amplifier740through the capacitor751, and a second output terminal output2of the differential amplifier730is coupled to the first input terminal of the amplifier740through the capacitor752. A first output terminal outp2of the amplifier740is coupled to the switch S1, and a second output terminal outn2of the amplifier740is coupled to the switch S2.

In the embodiment, the image sensor700adopts a differential correlated double sampling (CDS) circuit architecture. In the embodiment, the pixel group710includes pixels P0to P3, and the pixel group720includes pixels P4to P7. The pixel groups710and720may respectively implement the circuit of the pixel circuit600shown inFIG.6, and the only difference is that the pixel group710receives the up ramp signal RS_up, and the pixel group720receives a down ramp signal RS_dow. In the embodiment, the pixel group710may receive a selection signal sel<0>, a reset signal rst<0>, emission signals tx<0> to tx<3>, and the up ramp signal RS_up, and receive the operating voltage avdd through a signal line. The pixel group720may receive the selection signal sel<0>, a reset signal rst<1>, and emission signals tx<4> to tx<7>, the down ramp signal RS_down, and receive the operating voltage avdd through a signal line.

FIG.8is a signal timing diagram of multiple signals according to the embodiment ofFIG.7of the disclosure. Referring toFIG.7andFIG.8, multiple signals of the image sensor700ofFIG.7may implement the signal timing diagram shown inFIG.8, and reference may also be made to the corresponding embodiment above for the implementation details of each circuit and signal. Firstly, the timing controller provides the first enabling signals tx_en_p<0> to tx_en_p<7> to the pixel driving circuits of the pixels P0to P7. The first enabling signals tx_en_p<0> to tx_en_p<7> respectively include a pulse signal. The timing controller provides the original control signal tg_gnd_p<0> to the potential dropper, so that the potential dropper generates a control signal tg_gnd<0> to the pixel driving circuits of the pixels P0to P7. Moreover, the pixel driving circuits of the pixels P0to P7may respectively generate the driving signals tx_drv<0> to tx_drv<7>, and provide the driving signals tx_drv<0> to tx_drv<7> to the pixels P0to P7.

In the embodiment, during a reset period from time t0to time t4, the selection signal sel<0> is at a low voltage level. Between time t0and time t3, the original control signal tg_gnd_p<0> provided by the timing controller is switched from a low voltage level of 0V to a high voltage level of 1.2V, and the control signal tg_gnd<0> provided by the potential dropper is switched from a low voltage level of −1.2V to a high voltage level of 1.2V. During the period from time t1to time t2, the reset signals rst<0> and rst<1> are respectively switched from a low voltage level to a high voltage level. A pulse signal of the first enabling signal tx_en_p<0> also occurs during the period from time t1to time t2. Moreover, the driving signal tx_drv<0> is switched to a voltage level of 0V, and a pulse signal of the driving signal tx_drv<0> also occurs during the period from time t1to time t2. A signal waveform relationship of the reset signals rst<0> and rst<1>, the first enabling signals tx_en_p<1> to tx_en_p<7>, and the driving signals tx_drv<0> to tx_drv<7> may be deduced by analogy. In this regard, during the reset period from time t0to time t4, the pixels P0to P7may sequentially perform reset operations.

Then, during a readout period from time t4to time t8, the selection signal sel<0> is switched to a high voltage level to read out a sensing result. Between time t5and time t8, the original control signal tg_gnd_p<0> provided by the timing controller is switched from a low voltage level of 0V to a high voltage level of 1.2V, and the control signal tg_gnd<0> provided by the potential dropper is switched from a low voltage level of −1.2V to a high voltage level of 1.2V. During the period from time t4to time t5, the reset signals rst<0> and rst<1> are respectively switched from a low voltage level to a high voltage level to reset the voltage level of the floating diffusion node. The pulse signal of the first enabling signal tx_en_p<0> occurs during the period from time t5to time t6. Moreover, the driving signal tx_drv<0> is switched to a voltage level of 4V, and the pulse signal of the driving signal tx_drv<0> occurs during the period from time t5to time t6. Moreover, the period from time t6to time t7may be an analog-to-digital readout period of the back-end digital processing circuit to sequentially read out sensing results of the pixels P0to P7. The signal waveform relationship of the reset signals rst<0> and rst<1>, the first enabling signals tx_en_p<1> to tx_en_p<7>, and the driving signals tx_drv<1> to tx_drv<7> may be deduced by analogy. In this regard, during the readout period from time t4to time t8, the sensing results of the pixels P0to P7may be sequentially read out. Readout results of the pixels P0-P3and the pixels P4-P7may be respectively used as a differential input signal of the differential amplifier730, so that the back-end digital processing circuit can obtain an accurate signal readout result.

FIG.9is a flowchart of an operation method of an image sensor according to an embodiment of the disclosure. Referring toFIG.1andFIG.9, the respective operation methods of the pixel driving circuits121_0_0to121_n_7of the image sensor100may include Steps S910to S930below, and the pixel driving circuits121_0_0to121_n_7may be respectively implemented as the pixel driving circuit200shown inFIG.2. Taking the pixel driving circuit121_0_0as an example, in Step S910, the timing controller110may provide the first enabling signal tx_en_p<0> to the control terminal of the third transistor (T3), and provide the second enabling signal tx_en_m<0> to the control terminal of the fourth transistor (T4), wherein the signal waveform of the first enabling signal tx_en_p<0> is inverted to the signal waveform of the second enabling signal tx_en_m<0>. In Step S920, the potential dropper150_0may provide the first control signal tg_gnd<0> to the control terminal of the fifth transistor (T5), and the second control signal n_tg_gnd<0> to the control terminal of the sixth transistor (T6), wherein the signal waveform of the first control signal tg_gnd<0> is inverted to the signal waveform of the second control signal n_tg_gnd<0>. In Step S930, the output terminal coupled to the first terminal of the fourth transistor (T4) outputs the driving signal to the pixel circuit. Therefore, the operation method of the image sensor of the embodiment may generate the driving signal with a voltage swing from a positive voltage potential to a negative voltage potential to effectively drive the pixel unit.

In addition, reference may be made to the descriptions of the embodiments ofFIG.1toFIG.8for the operation manners and circuit implementation details of other image sensors of the embodiment, and details are not repeated here.

In summary, the image sensor, the level shifter circuit, and the operation method thereof of the disclosure can generate the driving signal with the voltage swing from the positive voltage potential to the negative voltage potential and can implement the pixel driving circuit with fewer transistors (effectively reducing the number of potential converters and transistors) to effectively prevent light banding in an image output by the image sensor (that is, when the pixel array of the image sensor is illuminated, the image output by the image sensor may produce the phenomenon of distinct stripes). Moreover, since the number of transistors of the pixel driving circuit is reduced, and the driving circuit area occupied on an entire image sensor chip can be effectively reduced, the image sensor of the disclosure can reduce the layout area of the pixel driving circuit and can effectively save overall power consumption.

Although the disclosure has been disclosed in the above embodiments, the embodiments are not intended to limit the disclosure. Persons skilled in the art may make some changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the disclosure shall be defined by the appended claims.