Patent ID: 12189995

Corresponding reference characters indicate corresponding components throughout the several figures of the drawings. Elements in the several figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures might be emphasized relative to other elements for facilitating understanding of the various presently disclosed embodiments. In addition, common, but well-understood, elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present disclosure.

DETAILED DESCRIPTION

With the ever-increasing capacities of storage devices and the required random performance for the latest generation of storage devices, the number of control table data entries needs to be increased to be able to store more updates occurred as a result of spike in number of read and/or write operations. As a direct result of such a spike in read and/or write operations, performing the search operation has become increasingly time-consuming. To tackle this issue, various embodiments of the disclosure designate a specific position for each control table set and store updates to such control table set in the designated position.

With the multiple layers of read/write operations available, it becomes necessary to decide the operations which result into lower latencies for the incoming commands and also take less processing time which is also important for the overall throughput of a storage device. Thus, in several embodiments, methods for data management are disclosed by determining the data to be kept in the volatile memory, such as SRAM, and determining the data to be evicted from the volatile memory to the non-volatile memory, such as NAND. Further, various embodiments of the disclosure are directed on determining when the read/write operations should be performed using the volatile memory, and when it is preferred from the non-volatile memory. Such determinations can be decided dynamically and based on the storage device state and incoming workload, so that the future operations result into overall low latencies.

Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, or the like) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “function,” “module,” “apparatus,” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer-readable storage media storing computer-readable and/or executable program code. Many of the functional units described in this specification have been labeled as functions, in order to emphasize their implementation independence more particularly.

Functions may also be implemented at least partially in software for execution by various types of processors. An identified function of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions that may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified function need not be physically located together but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the function and achieve the stated purpose for the function.

Indeed, a function of executable code may include a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, across several storage devices, or the like. Where a function or portions of a function are implemented in software, the software portions may be stored on one or more computer-readable and/or executable storage media. Any combination of one or more computer-readable storage media may be utilized. A computer-readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing, but would not include propagating signals. In the context of this document, a computer readable and/or executable storage medium may be any tangible and/or non-transitory medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, processor, or device.

Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object-oriented programming language such as Python, Java, Smalltalk, C++, C #, Objective C, or the like, conventional procedural programming languages, such as the “C” programming language, scripting programming languages, and/or other similar programming languages. The program code may execute partly or entirely on one or more of a user's computer and/or on a remote computer or server over a data network or the like.

A component, as used herein, comprises a tangible, physical, non-transitory device. For example, a component may be implemented as a hardware logic circuit comprising custom VLSI circuits, gate arrays, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. A component may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the functions and/or modules described herein, in certain embodiments, may alternatively be embodied by or implemented as a component.

A circuit, as used herein, comprises a set of one or more electrical and/or electronic components providing one or more pathways for electrical current. In certain embodiments, a circuit may include a return pathway for electrical current, so that the circuit is a closed loop. In another embodiment, however, a set of components that does not include a return pathway for electrical current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return pathway for electrical current) or not. In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a set of integrated circuits, a set of non-integrated electrical and/or electrical components with or without integrated circuit devices, or the like. In one embodiment, a circuit may include custom VLSI circuits, gate arrays, logic circuits, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device such as field programmable gate array, programmable array logic, programmable logic device, or the like (e.g., as firmware, a netlist, or the like). A circuit may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the functions and/or modules described herein, in certain embodiments, may be embodied by or implemented as a circuit.

Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to”, unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise.

Further, as used herein, reference to reading, writing, storing, buffering, and/or transferring data can include the entirety of the data, a portion of the data, a set of the data, and/or a subset of the data. Likewise, reference to reading, writing, storing, buffering, and/or transferring non-host data can include the entirety of the non-host data, a portion of the non-host data, a set of the non-host data, and/or a subset of the non-host data.

Lastly, the terms “or” and “and/or” as used herein are to be interpreted as inclusive or meaning any one or any combination. Therefore, “A, B or C” or “A, B and/or C” mean “any of the following: A; B; C; A and B; A and C; B and C; A, B and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or acts are in some way inherently mutually exclusive.

Aspects of the present disclosure are described below with reference to schematic flowchart diagrams and/or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the disclosure. It will be understood that each block of the schematic flowchart diagrams and/or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams and/or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor or other programmable data processing apparatus, create means for implementing the functions and/or acts specified in the schematic flowchart diagrams and/or schematic block diagrams block or blocks.

It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated figures. Although various arrow types and line types may be employed in the flowchart and/or block diagrams, they are understood not to limit the scope of the corresponding embodiments. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment.

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements of proceeding figures. Like numbers may refer to like elements in the figures, including alternate embodiments of like elements.

Referring toFIG.1, a schematic block diagram of a host-computing device110with a storage system suitable for control table set determination in accordance with an embodiment of the disclosure is shown. The control table set determination system100may comprise one or more storage devices120of a storage system102within a host-computing device110in communication via a controller126. The host-computing device110may include a processor111, volatile memory112, and a communication interface113. The processor111may include one or more central processing units, one or more general-purpose processors, one or more application-specific processors, one or more virtual processors (e.g., the host-computing device110may be a virtual machine operating within a host), one or more processor cores, or the like. The communication interface113may include one or more network interfaces configured to communicatively couple the host-computing device110and/or controller126of the storage device120to a communication network115, such as an Internet Protocol (IP) network, a Storage Area Network (SAN), wireless network, wired network, or the like.

The storage device120, in various embodiments, may be disposed in one or more different locations relative to the host-computing device110. In one embodiment, the storage device120comprises one or more non-volatile memory devices123, such as semiconductor chips or packages or other integrated circuit devices disposed on one or more printed circuit boards, storage housings, and/or other mechanical and/or electrical support structures. For example, the storage device120may comprise one or more direct inline memory module (DIMM) cards, one or more expansion cards and/or daughter cards, a solid-state-drive (SSD) or other hard drive device, and/or may have another memory and/or storage form factor. The storage device120may be integrated with and/or mounted on a motherboard of the host-computing device110, installed in a port and/or slot of the host-computing device110, installed on a different host-computing device110and/or a dedicated storage appliance on the network115, in communication with the host-computing device110over an external bus (e.g., an external hard drive), or the like.

The storage device120, in one embodiment, may be disposed on a memory bus of a processor111(e.g., on the same memory bus as the volatile memory112, on a different memory bus from the volatile memory112, in place of the volatile memory112, or the like). In a further embodiment, the storage device120may be disposed on a peripheral bus of the host-computing device110, such as a peripheral component interconnect express (PCI Express or PCIe) bus such, as but not limited to a NVM Express (NVMe) interface, a serial Advanced Technology Attachment (SATA) bus, a parallel Advanced Technology Attachment (PATA) bus, a small computer system interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, or the like. In another embodiment, the storage device120may be disposed on a communication network115, such as an Ethernet network, an Infiniband network, SCSI RDMA over a network115, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and/or wireless network115, or the like.

The host-computing device110may further comprise computer-readable storage medium114. The computer-readable storage medium114may comprise executable instructions configured to cause the host-computing device110(e.g., processor111) to perform steps of one or more of the methods disclosed herein. Additionally, or in the alternative, the buffering component150may be embodied as one or more computer-readable instructions stored on the computer-readable storage medium114.

A device driver and/or the controller126, in certain embodiments, may present a logical address space134to the host clients116. As used herein, a logical address space134refers to a logical representation of memory resources. The logical address space134may comprise a plurality (e.g., range) of logical addresses. As used herein, a logical address refers to any identifier for referencing a memory resource (e.g., data), including, but not limited to: a logical block address (LBA), cylinder/head/sector (CHS) address, a file name, an object identifier, an inode, a Universally Unique Identifier (UUID), a Globally Unique Identifier (GUID), a hash code, a signature, an index entry, a range, an extent, or the like.

A device driver for the storage device120may maintain metadata135, such as a logical to physical address mapping structure, to map logical addresses of the logical address space134to media storage locations on the storage device(s)120. A device driver may be configured to provide storage services to one or more host clients116. The host clients116may include local clients operating on the host-computing device110and/or remote clients117accessible via the network115and/or communication interface113. The host clients116may include, but are not limited to: operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

In many embodiments, the host-computing device110can include a plurality of virtual machines which may be instantiated or otherwise created based on user-request. As will be understood by those skilled in the art, a host-computing device110may create a plurality of virtual machines configured as virtual hosts which is limited only on the available computing resources and/or demand. A hypervisor can be available to create, run, and otherwise manage the plurality of virtual machines. Each virtual machine may include a plurality of virtual host clients similar to host clients116that may utilize the storage system102to store and access data.

The device driver may be further communicatively coupled to one or more storage systems102which may include different types and configurations of storage devices120including, but not limited to: solid-state storage devices, semiconductor storage devices, SAN storage resources, or the like. The one or more storage devices120may comprise one or more respective controllers126and non-volatile memory channels122. The device driver may provide access to the one or more storage devices120via any compatible protocols or interface133such as, but not limited to, SATA and PCIe. The metadata135may be used to manage and/or track data operations performed through the protocols or interfaces133. The logical address space134may comprise a plurality of logical addresses, each corresponding to respective media locations of the one or more storage devices120. The device driver may maintain metadata135comprising any-to-any mappings between logical addresses and media locations.

A device driver may further comprise and/or be in communication with a storage device interface139configured to transfer data, commands, and/or queries to the one or more storage devices120over a bus125, which may include, but is not limited to: a memory bus of a processor111, a peripheral component interconnect express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (ATA) bus, a parallel ATA bus, a small computer system interface (SCSI), FireWire, Fibre Channel, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, a network115, Infiniband, SCSI RDMA, or the like. The storage device interface139may communicate with the one or more storage devices120using input-output control (IO-CTL) command(s), IO-CTL command extension(s), remote direct memory access, or the like.

The communication interface113may comprise one or more network interfaces configured to communicatively couple the host-computing device110and/or the controller126to a network115and/or to one or more remote clients117(which can act as another host). The controller126is part of and/or in communication with one or more storage devices120. AlthoughFIG.1depicts a single storage device120, the disclosure is not limited in this regard and could be adapted to incorporate any number of storage devices120.

The storage device120may comprise one or more non-volatile memory devices123of non-volatile memory channels122, which may include but is not limited to: ReRAM, Memristor memory, programmable metallization cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, ovonic unified memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon-oxide based sub-10 nanometer process memory, graphene memory, Silicon Oxide-Nitride-Oxide-Silicon (SONOS), programmable metallization cell (PMC), conductive-bridging RAM (CBRAM), magneto-resistive RAM (MRAM), magnetic storage media (e.g., hard disk, tape), optical storage media, or the like. The one or more non-volatile memory devices123of the non-volatile memory channels122, in certain embodiments, comprise storage class memory (SCM) (e.g., write in place memory, or the like).

While the non-volatile memory channels122is referred to herein as “memory media,” in various embodiments, the non-volatile memory channels122may more generally comprise one or more non-volatile recording media capable of recording data, which may be referred to as a non-volatile memory medium, a non-volatile memory device, or the like. Further, the storage device120, in various embodiments, may comprise a non-volatile recording device, a non-volatile memory array129, a plurality of interconnected storage devices in an array, or the like.

The non-volatile memory channels122may comprise one or more non-volatile memory devices123, which may include, but are not limited to: chips, packages, planes, die, or the like. A controller126may be configured to manage data operations on the non-volatile memory channels122, and may comprise one or more processors, programmable processors (e.g., FPGAs), ASICs, micro-controllers, or the like. In some embodiments, the controller126is configured to store data on and/or read data from the non-volatile memory channels122, to transfer data to/from the storage device120, and so on.

The controller126may be communicatively coupled to the non-volatile memory channels122by way of a bus127. The bus127may comprise an I/O bus for communicating data to/from the non-volatile memory devices123. The bus127may further comprise a control bus for communicating addressing and other command and control information to the non-volatile memory devices123. In some embodiments, the bus127may communicatively couple the non-volatile memory devices123to the controller126in parallel. This parallel access may allow the non-volatile memory devices123to be managed as a group, forming a non-volatile memory array129. The non-volatile memory devices123may be partitioned into respective logical memory units (e.g., logical pages) and/or logical memory divisions (e.g., logical blocks). The logical memory units may be formed by logically combining physical memory units of each of the non-volatile memory devices123.

The controller126may organize a block of word lines within a non-volatile memory device123, in certain embodiments, using addresses of the word lines, such that the word lines are logically organized into a monotonically increasing sequence (e.g., decoding and/or translating addresses for word lines into a monotonically increasing sequence, or the like). In a further embodiment, word lines of a block within a non-volatile memory device123may be physically arranged in a monotonically increasing sequence of word line addresses, with consecutively addressed word lines also being physically adjacent (e.g., WL0, WL1, WL2, . . . WLN).

The controller126may comprise and/or be in communication with a device driver executing on the host-computing device110. A device driver may provide storage services to the host clients116via one or more interfaces133. A device driver may further comprise a storage device interface139that is configured to transfer data, commands, and/or queries to the controller126over a bus125, as described above.

The storage system102may also include an energy recycling module140. In various embodiments, the energy recycling module140may be disposed within a storage system, such as the embodiment depicted inFIG.1. However, it is contemplated that many embodiments comprise at least one energy recycling module140disposed within the storage device120itself. As described in further detail below, the energy recycling module can be configured to capture excess heat and generate electricity that can be stored or utilized to power other components within the storage device120and/or storage system102. The energy recycling module140may also be configured to operate in a cooling mode that can receive a power supply and cool one or more surfaces of various components within the storage device120or storage system102. It should also be noted that the energy recycling module140may be similar to the energy recycling modules discussed throughout this disclosure such as those described inFIGS.2-10.

Referring toFIG.2, a schematic block diagram of a storage device120suitable for control table set determination in accordance with an embodiment of the disclosure is shown. The controller126may include a front-end module208that interfaces with a host via a plurality of high priority and low priority communication channels, a back-end module210that interfaces with the non-volatile memory devices123, and various other modules that perform various functions of the storage device120. In some examples, each module may just be the portion of the memory that comprises instructions executable with the processor to implement the features of the corresponding module without the module including any other hardware. Because each module includes at least some hardware even when the included hardware comprises software, each module may be interchangeably referred to as a hardware module.

The controller126may include a buffer management/bus control module214that manages buffers in random access memory (RAM)216and controls the internal bus arbitration for communication on an internal communications bus217of the controller126. A read only memory (ROM)218may store and/or access system boot code. Although illustrated inFIG.2as located separately from the controller126, in other embodiments one or both of the RAM216and the ROM218may be located within the controller126. In yet other embodiments, portions of RAM216and ROM218may be located both within the controller126and outside the controller126. Further, in some implementations, the controller126, the RAM216, and the ROM218may be located on separate semiconductor dies. As discussed below, in one implementation, the submission queues and the completion queues may be stored in a controller memory buffer, which may be housed in RAM216.

Additionally, the front-end module208may include a host interface220and a physical layer interface222that provides the electrical interface with the host or next level storage controller. The choice of the type of the host interface220can depend on the type of memory being used. Example types of the host interfaces220may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface220may typically facilitate transfer for data, control signals, and timing signals.

The back-end module210may include an error correction controller (ECC) engine224that encodes the data bytes received from the host and decodes and error corrects the data bytes read from the non-volatile memory devices123. The back-end module210may also include a command sequencer226that generates command sequences, such as program, read, and erase command sequences, to be transmitted to the non-volatile memory devices123. Additionally, the back-end module210may include a RAID (Redundant Array of Independent Drives) module228that manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the storage device120. In some cases, the RAID module228may be a part of the ECC engine224. A memory interface230provides the command sequences to the non-volatile memory devices123and receives status information from the non-volatile memory devices123. Along with the command sequences and status information, data to be programmed into and read from the non-volatile memory devices123may be communicated through the memory interface230. A flash control layer232may control the overall operation of back-end module210.

Additional modules of the storage device120illustrated inFIG.2may include a media management layer238, which performs wear leveling of memory cells of the non-volatile memory devices123. The storage device120may also include other discrete components240, such as energy recycling modules, external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller126. In alternative embodiments, one or more of the RAID modules228, media management layer238and buffer management/bus control module214are optional components that may not be necessary in the controller126.

Finally, the controller126may also comprise a control table set determination logic234. In many embodiments, the control table set determination logic234can be configured to monitor the state of control table sets within the storage device120. For example, the control table set determination logic234may configure and operate the control table cache and/or the control table change lists. The control table set determination logic234can direct which control table sets should be transferred into and out of the control table cache. Likewise, the control table change lists can be allocated, managed, and deleted by the control table set determination logic234.

Referring toFIG.3, a conceptual illustration of a control table set300in the translation and data management system in accordance with an embodiment of the disclosure is shown. Typically, a control table set300can include a set of control table data entries310including data entries 0 to N312a,312b, . . . ,312N. Each control table data entry312a,312b, . . . ,312N can store a particular set of logical to physical address map updates. In the control table set300shown inFIG.3, the control table set300includes N+1 control table data entries 0-N. In an embodiment, upon receiving a new set of logical to physical address map updates (hereinafter “entry”) a new control data table entry can be added to the end of the control table set300, at which the new entry can be stored. Once a search command is received from the host computer, e.g., a read or write command, the control table set300can be searched, i.e., scanned, from the first end, i.e., control table data entry312a, to the last end, i.e., control table data set312N. While, the search operation can be performed sequentially, a person skilled in the art will understand that a binary search operation can also be performed to find the desired entry. In an embodiment, even if the desired entry is found, the search operation can continue to the last end to find the most recent occurrence of the desired entry.

Currently, most read/write operations, e.g., translation operations, are performed based on a fixed order scheme which may not provide the benefit in all the cases/workloads and also the volatile memory, e.g., the SRAM, may not have the enough data to perform the translations. To tackle this issue, the translation and data management system can include several main features/steps. Such features/steps can include (i) dynamic data management for an upload layer to determine how much data should be stored in the upload layer of the storage device and when the data is evicted based on the workload range and fragmentation of the storage device; (ii) determining the read-write operations, e.g., translation operations order, to reduce latencies based on determining when the data should be translated from storage portions of the host device and when the data should be translated from the upload layer of the storage device, if the data is residing at both the places based on a state of the storage device; and (iii) updating the stale storage portions of the host device whenever there is an opportunity, e.g., CPU is idle or there is less traffic on bus, to reduce the upload layer search overheads.

Referring toFIG.4, a conceptual illustration of a control table set400in a fragmented upload layer of the storage device, in accordance with an embodiment of the disclosure is shown. In various embodiments, the amount of data that should be translated can impact several operational features of the storage device, such as the consolidation time and subsequent reads translation time when these are translated via the upload layer of the storage device. In some embodiments, the translation and data management system can use the average search time and the average consolidation time to determine the amount of data which can reside in the upload layer of the storage device. Further, the translation and data management system can determine the average search time based on the number of entries for the given range and determine the average consolidation time based on the amount of data for a set of control table sets. This can result in a determination to keep the entries based on a balanced threshold in both cases. In the control table set as shown inFIG.4, the control table set400includes a fragmented upload layer, which indicates that the upload layer includes particular positions to store the entries410,420,430,440,450,460which are typically significantly smaller size compared to a non-fragmented upload layer. As a non-limiting example, the fragmented upload layer may include entries with the sizes 4 KB, 8 KB, 32 KB, etc. In such fragmented range upload layers, the search time is usually high.

Referring toFIG.5, a conceptual illustration of a control table set500in a non-fragmented upload layer of the storage device, in accordance with an embodiment of the disclosure is shown. In control table set500as shown inFIG.5, the control table set500includes a non-fragmented upload layer, with entries510and520that are considerably larger in size than the fragmented upload layer as shown inFIG.4. As a non-limiting example, the non-fragmented upload layer500may include entries with the sizes 16 MB, 8 MB, etc. In such non-fragmented upload layers, the search time is usually low, while the consolidation time is high.

In some embodiments, the translation and data management system can reduce latencies. The translation and data management system can determine whether the translation needs to be done using the upload layer of the storage device or the storage portions of the host device. The translation and data management system can make such determination based on the number of entries, so that if the number of entries exceeds a threshold, then the translation and data management system performs the translations from the storage portions o the host device. Otherwise, if the number of entries does not exceed the threshold, then the translation and data management system performs the translations from the upload layer of the storage device.

In other words, if the data was written sequentially, then the translation and data management system performs the translations in the storage portions of the host device. Alternatively, if the data is written randomly, then the translation and data management system performs the translations in the upload layer of the storage device. In several embodiments, the translation and data management system can make a decision based on the state of the upload layer of the storage device and once the entries are stored based on exceeding the threshold as discussed above. Thus, in case of the fragmented upload layer, the translation and data management system can perform the translation operation in the storage portion of the host device. Alternatively, in case of the non-fragmented upload layer, the translation and data management system can perform the translation operation in the upload layer of the storage device.

In some embodiments, the storage portions of the host device do not include the latest version of an entry, and the latest version of the is only stored in the upload layer of the storage device. In such embodiments, the translation and data management system can update/sync the storage portions of the host device by copying the latest version of entries from the upload layer of the storage device whenever there is an opportunity. As a non-limiting example, the translation and data management system can sync the storage portions of the host device when less intense workloads occurs such as when CPU's usage is below a certain threshold, or the CPU is idle. The translation and data management system can store copies of the lates versions of entries in the storage portions of the host device subsequently. Subsequent translation operations can be performed in the storage portions f the host device which has lower search time compared to the upload layer of the storage device.

Referring toFIG.6now, a flowchart depicting a process600for performing a write or relocation command in accordance with an embodiment of the disclosure is shown. In many embodiments, the process600can start at block610where the process600receives a command from a host device. The received command can be a write command or a relocation command. The received command can be associated with logical to physical address mapping updates.

In an embodiment, the process600can determine a control table set among a plurality of control table sets which is associated with the received command, as shown in block620. In some embodiments, the process600can determine a first search time based on a number of data entries for a range of data associated with the determined control table set, as shown by block630. In some embodiments, the process600can determine a second search time based on an amount of data entries in each of the plurality of control table sets, as shown by block640.

In additional embodiments, the process600can determine whether the first and second search times exceed a threshold, as shown by block650. Upon a determination that the first and second search times do not exceed the threshold, the process600stores the received command in the upload layer of the storage device, as shown by block660. Alternatively, upon a determination that the first and second search times exceed the threshold, the process600stores the received command in the storage portions of the host device, i.e., a cached memory, as shown by block670.

Referring toFIG.7, a flowchart depicting a process700for performing a read command in accordance with an embodiment of the disclosure is shown. The process700can begin at block710where the process700receive a read command. The received read command can be associated with logical to physical address mapping updates.

In an embodiment, the process700can determine the first search time based on the number of data entries for a range of data associated with the control table set associated with the read command, and the second search time based on the amount of data entries in each of the plurality of control table sets. The process700can then determine whether the first and second search times exceed a threshold, as shown by block720. Upon a determination that the first and second search times do not exceed the threshold, the process700performs the read operation in the upload layer of the storage device, as shown by block730. Alternatively, upon a determination that the first and second search times exceed the threshold, the process700performs the read operation in the storage portions of the host device, i.e., the cached memory, as shown by block740.

Information as herein shown and described in detail is fully capable of attaining the above-described object of the present disclosure, the presently preferred embodiment of the present disclosure, and is, thus, representative of the subject matter that is broadly contemplated by the present disclosure. The scope of the present disclosure fully encompasses other embodiments that might become obvious to those skilled in the art, and is to be limited, accordingly, by nothing other than the appended claims. Any reference to an element being made in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described preferred embodiment and additional embodiments as regarded by those of ordinary skill in the art are hereby expressly incorporated by reference and are intended to be encompassed by the present claims.

Moreover, no requirement exists for a system or method to address each and every problem sought to be resolved by the present disclosure, for solutions to such problems to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. Various changes and modifications in form, material, workpiece, and fabrication material detail can be made, without departing from the spirit and scope of the present disclosure, as set forth in the appended claims, as might be apparent to those of ordinary skill in the art, are also encompassed by the present disclosure.