Patent ID: 12190243

DETAILED DESCRIPTION

The present invention may be understood more readily by reference to the following detailed description of the preferred embodiments of the invention. It is to be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. It is further to be understood that unless specifically defined herein, the terminology used herein is to be given its traditional meaning as known in the relevant art.

It has been recognized by the inventors that learning machines can be improved if additional dedicated hardware structures are integrated with or otherwise made available to the architectures that implement the learning machine. One such improvement that can be made includes structures and acts that implement an arithmetic unit as described herein. The inventive arithmetic unit of the present disclosure may be implemented on a wide variety of learning machines. For brevity, however, the present disclosure includes implementations of the inventive arithmetic unit in a particular deep convolutional neural network disclosed in U.S. patent application Ser. No. 15/423,272 to DESOLI et aI., and entitled DEEP CONVOLUTIONAL NETWORK HETEROGENEOUS ARCHITECTURE, which application is incorporated by reference into the present application. This particular deep convolutional network heterogeneous architecture learning machine discloses a system on chip (SoC) having a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.

FIGS.3-6and the accompanying detailed description thereof illustrate and present elements of an exemplary system on chip (SoC)110configurable as a high-performance, energy efficient hardware accelerated DCNN processor.FIGS.7A-7Fand the accompanying detailed description thereof illustrate and present structures and data flow diagrams of arithmetic units for deep learning acceleration700integrated with the hardware accelerated DCNN processor ofFIGS.3-6. The exemplary SoC110, which is particularly useful for machine learning applications, implements an image and DCNN co-processor subsystem400(FIG.4), which may interchangeably be referred to as a configurable accelerator framework; an architecturally efficient stream switch500(FIG.5), which creates data locality at previously unprecedented levels; a set of convolution accelerators600(FIG.6), which perform a convolution of input feature data with kernel data derived from the training of the neural network; and a set of arithmetic units particularly arranged for deep learning acceleration700(FIG.7).

FIG.3is an exemplary mobile device100having integrated therein a DCNN processor embodiment illustrated as a block diagram. The mobile DCNN processor is arranged as a system on chip (SoC)110, however other arrangements are also contemplated (e.g., multiple chips, several chip die in a single integrated circuit, and the like). The illustrated SoC110includes a plurality of SoC controllers120, a configurable accelerator framework (CAF)400(e.g., an image and DCNN co-processor subsystem), an SoC global memory126, an applications (e.g., a host) processor128, and a plurality of DSPs138, each of which are communicatively coupled, directly or indirectly, to a primary (e.g., system) communication bus132and a secondary communications (e.g., DSP) bus166.

The configurable accelerator framework (CAF)400is communicatively coupled to the system bus166, which provides a mechanism for convolution accelerators of the CAF400to access the SoC global memory126as needed and to communicate with the DSPs138as needed. The CAF400is illustrated in more detail inFIG.4.

The SoC110includes various SoC controllers120, some of which control the SoC110, and others of which control one or more peripheral devices. SoC controllers120include an applications (e.g., a host) processor128(e.g., an ARM processor or some other host processor), a clock generator168(e.g., a clock manager), a reset controller170, and a power manager172to provide additional support, control, and management of various timing, power consumption, and other aspects of the SoC110and other components. Other SoC controllers120that control peripherals include a low speed peripheral I/O interface130and an external memory controller174to communicate with or otherwise access external chips, components, or memory of the exemplary device100in which the SoC110is embedded.

The applications processor128may act as an intermediate module or as an interface to other programs or components of the exemplary electronic device100with which the SoC110is integrated. In some embodiments, the applications processor128may be referred to as an applications processor core. In various embodiments, the applications processor128loads an SoC configuration file at boot time and configures DSPs138and the CAF400according to the configuration file. As the SoC110processes one or more batches of input data (e.g., an image), the applications processor128may coordinate the reconfiguration of the CAF400or DSPs138based on the configuration file, which itself may be based on the DCNN layers and topology.

The SoC110also includes a primary communications bus132(e.g., an AXI—Advanced eXtensible Interface) that facilitates communications between the SoC controllers120and the DSPs138and between the SoC controllers120and the CAF400. For example, the DSPs138or the CAF400can communicate, via the primary communications bus132with the applications processor128, one or more peripheral controllers/peripheral communications interface (low speed peripheral I/O)130, an external memory (not shown) via an external memory controller174, or other components. The SoC controllers120may also include other supporting and cooperative devices such as a clock manager (e.g., a clock generator)168, a reset controller170, a power manager172to provide additional timing and power management to the SoC110, and other components.

In some embodiments, and as illustrated inFIG.3, the plurality of DSPs138are arranged in a plurality of DSP clusters, such as a first DSP cluster122, a second DSP cluster140, and several other DSP clusters that are not referenced for simplification of the illustration.

Each DSP cluster122,140includes a plurality (e.g., two) of DSPs142,152, a plurality (e.g., two) of local DSP crossbar switches144,154, and a DSP cluster crossbar switch145,155. Each DSP142,152in a particular cluster is capable of communicating with other DSP's142,152via the DSP cluster crossbar switch145,155. Each DSP142,152has access to a corresponding instruction cache146,156, and local DSP memory148,158via its corresponding local DSP crossbar switch144,154. In one non-limiting embodiment, each instruction cache146,156is a 4-way 16 kB instruction cache and each local DSP memory148,158is 64 kB of local RAM storage for its corresponding DSP. Each DSP cluster122,140also includes a shared DSP cluster memory160,159and a cluster DMA162,164for accessing the SoC global memory160,159.

Each DSP cluster122,140is communicatively coupled to a global DSP cluster crossbar switch150via the DSP cluster crossbar switch145,155to enable each DSP142,152in each DSP cluster122,140to communicate with one another and other components on the SoC110. The global DSP cluster crossbar switch150enables each DSP to communicate with other DSPs in the plurality of DSP clusters138.

Additionally, the global DSP cluster crossbar switch150is communicatively coupled to a system bus166(e.g., secondary communications bus, xbar—SoC crossbar switch, or the like), which enables each DSP to communicate with other components of the SoC110. For example, each DSP142,152can communicate with one or more components (e.g., one or more convolution accelerators) of the CAF400or access an SoC global memory126via the system bus166. In some embodiments, each DSP142,152can communicate with the SoC memory126via the DMA162,164of its corresponding DSP cluster122,140. Moreover, DSP142,152may communicate with the controllers120or other modules of the SoC110as needed via the system bus166. Each DSP accesses the system bus166via its local DSP crossbar switch144,154, its DSP cluster crossbar switch145,155, and the global DSP cluster crossbar switch150.

The plurality of DSPs138can be assigned or allocated to perform specific instructions to accelerate other operations of the DCNN. These other operations may include non-convolutional operations performed during a DCNN process, which are in some cases primarily performed by the CAF400. Examples of these non-convolutional operations include, but are not limited to, max or average pooling, nonlinear activation, cross-channel response normalization, classification representing a small fraction of the total DCNN computation but more amenable to future algorithmic evolutions, or other operations, e.g., Min, Max, Sqrt, Mac, Butterfly, Average, 2-4 SIMD ALU. In some cases, operations that previously have been performed using one or more of the DSPs138are now performed using the arithmetic unit for deep learning acceleration structures described herein with reference toFIG.7. Accordingly, improved operations of the processors and their associated computing devices described herein may be realized by the arithmetic unit structures described herein.

DSPs138can operate concurrently (e.g., in parallel) with the operations of CA's in the CAF400and concurrently (e.g., in parallel) with data transfers, which may be synchronized by way of interrupts, mailboxes, or some other synchronization mechanism for concurrent execution.

In various embodiments, the SoC memory126includes a plurality of memory components for storing data that is accessible to the components of the CAF400or the DSPs138. In at least one embodiment, the SoC memory126is configured in a hierarchical-type memory structure. In one non-limiting example, the SoC memory126includes four SRAM banks each with 1 Mbyte of storage space.

In at least one embodiment, the configurable accelerator framework (CAF)400may be organized as an image and DCNN co-processor subsystem of the SoC110. As described herein, the CAF400includes a reconfigurable dataflow accelerator fabric connecting high-speed camera interfaces with any one or more of arithmetic units for deep learning acceleration (FIG.6), sensor processing pipelines, croppers, color converters, feature detectors, video encoders, eight channel digital microphone interface, streaming DMAs, and a plurality of convolution accelerators.

Additional details regarding the CAF400are described in conjunction withFIG.4. Briefly, the CAF400receives incoming data (e.g., image data inFIG.4, but other types of streaming data in different embodiments), such as from the camera interface, or other sensors, and distributes the incoming data to the various components of the CAF400(e.g., convolution accelerators, which are described in more detail in conjunction withFIG.6, arithmetic units for deep learning acceleration700described in more detail in conjunction withFIG.7, and the like) and/or one or more of the plurality of DSPs138to employ the DCNN and recognize objects in the incoming images.

The CAF400utilizes unidirectional links to transport data streams via a configurable, fully connected switch to or from different kinds of source or sink components. For example, the configurable fully connected switch, which is described in more detail in conjunction withFIG.5, can transport data via direct memory accesses (DMAs) to the SoC global memory126, I/O interfaces (e.g., cameras), and various types of accelerators (e.g., convolution accelerator (CA)600, arithmetic units for deep learning acceleration700, etc.). In some cases, the CAF400is configured at boot time based on information received from a particular SoC configuration tool, and the CAF400is re-configured during run time based on defined DCNN layers and topology or information received from one or more DSPs138, applications processor128, or the like.

The CAF400allows for the definition of a selectable number of concurrent, virtual processing chains at run time. The CAF400also includes a full featured back pressure mechanism to control data flow to the various components of the framework. The CAF400is arranged for stream multicasting operations, which enable the reuse of a data stream at multiple block instances. Linked lists control the fully autonomous processing of an entire convolution layer. Multiple accelerators, grouped or chained together, handle varying sizes for feature maps data and multiple kernels in parallel. Grouping the convolutional accelerators (CA's)600to achieve larger computational entities enables choosing an acceptably optimal balancing of the available data bandwidth, budget power, and available processing resources. Each CA600includes a line buffer to fetch up to a predetermined number (e.g., 12) of feature map data words in parallel with a single memory access. Further supporting the CA600structures are the arithmetic units for deep learning acceleration700, which perform math functions conformable to the formula of Equation 1 with a data locality heretofore unknown.
AX+BY+C→Output  (1)

Rather than passing data for interim math functions out of the CAF400to a separate device such as a DSP, data is retained within the CAF400architecture thereby achieving significant speed and data throughput gains.

In each CA (600), a register-based kernel buffer provides multiple read ports (e.g., 36 read ports), while multiple fixed-point multiply-accumulate (MAC) units (e.g., 36 16-bit MAC units) perform multiple MAC operations per clock cycle (e.g., up to 36 operations per clock cycle). An adder tree accumulates MAC results for each kernel column. The overlapping, column based calculation of the MAC operations allows an acceptably optimal reuse of the feature maps data for multiple MACs, thereby reducing power consumption associated with redundant memory accesses.

Kernel sets are partitioned in batches processed sequentially and intermediate results can be stored in the SoC global memory126. Various kernel sizes (e.g., up to 12×12), various batch sizes (e.g., up to 16), and parallel kernels (e.g., up to 4) can be handled by a single CA600instance but any size kernel can be accommodated with the accumulator input.

The configurable batch size and a variable number of parallel kernels enable acceptably optimal trade-offs for the available input and output bandwidth sharing across different units and the available computing logic resources.

A different acceptably optimal configuration of CA's600in the CAF400is determined for each DCNN layer. These configurations may be determined or adjusted using a holistic tool that starts with a DCNN description format, such as Caffe' or TensorFlow. The CA600supports on-the-fly kernel decompression and rounding when the kernel is quantized nonlinearly with 8 or fewer bits per weight with top-1 error rate increases up to 0.3% for 8 bits.

FIG.4is an embodiment depicting a configurable accelerator framework (CAF)400, such as the image and deep convolutional neural network (DCNN) co-processor subsystem400ofFIG.3. The CAF400may be configured for image processing, audio processing, prediction analysis (e.g., games of skill, marketing data, crowd behavior prediction, weather analysis and prediction, genetic mapping, disease diagnosis, and other scientific, commercial, consumer, and such processing) or some other type of processing; particularly processing that includes convolutional operations.

The CAF400is also arranged with a number of configurable modules. Some modules are optional, and some modules are required. Many optional modules are commonly included in embodiments of a CAF400. One required module of a CAF400is, for example, the stream switch500. The stream switch500provides a design time parametric, run-time reconfigurable accelerator interconnect framework to support dataflow based processing chains. Another required module is, for example, a set of CAF control registers402. Other modules may be required as well. Optional modules of the CAF400include a system bus interface module404, a selected number of DMA engines406(e.g., DMA controllers), a selected number of external device interfaces408, a selected number of processing modules410, a selected number of convolution accelerators (CA's)600, and a selected number of arithmetic units for deep learning acceleration700.

The stream switch500is a reconfigurable unidirectional interconnection structure formed with a plurality of unidirectional “stream links.” The stream links are arranged to transport multibit data streams from accelerators, interfaces, and other logic modules to the stream switch500and from the stream switch500to accelerators, interfaces, and other logic modules.

In addition to the stream switch500, the CAF400may also include a system bus interface module404. The system bus interface module404provides an interface to other modules of SoC110. As shown in the exemplary embodiment ofFIG.3, the CAF400is coupled to the secondary communication bus166. In other cases, the CAF400may be coupled to the primary communication bus132or some other communication mechanism. Control information may be passed unidirectionally or bidirectionally through the system bus interface module404of the CAF400. Such interface is used to provide a host processor (e.g., DSP of DSP cluster130, applications processor128, or another processor) access to all of the CAF control registers402, which are used to control, operate, or otherwise direct particular features of the framework. In some embodiments, each DMA engine406, external device interface408, processing module410, convolution accelerator600, and arithmetic unit for deep learning acceleration700has an interface to the configuration network with a defined set of configuration registers (e.g., formed in CAF control registers402).

The CAF400includes a plurality of DMA engines406. InFIG.4, sixteen DMA engines406ato406pare illustrated, but some other number of DMA engines may be included in other embodiments of SoC110according to one or more choices made by a semiconductor practitioner at design time. The DMA engines406are arranged to provide bidirectional channels for input data flow, output data flow, or input and output data flow. In these cases, substantial quantities of data are passed into the CAF400, out from the CAF400, or into and out from the CAF400. For example, in some cases, one or more DMA engines406are used to pass streaming video data from memory or from a data source device (e.g., a high-definition (HD) video camera) that produces substantial quantities of video data. Some or all of the video may be passed in from the source device, in from or out to SoC global memory126, and the like.

In one exemplary embodiment, one or more DMA engines406are connected to the stream switch500with one input port504(FIG.5) and one output stream port516(FIG.5). The DMA engines406can be configured in either input or output mode. The DMA engines406can be configured to pack and send data to any address location accessible on the primary communication bus132, the secondary communication bus166, or some other address location. The DMA engines406can also additionally or alternatively be configured to unpack fetched data and translate the unpacked data into a data stream.

The CAF400ofFIG.4includes a design-time selectable, run-time configurable plurality of external device interfaces408. The external device interfaces408provide a connection to external devices which produce (i.e., source devices) or consume (i.e., sink devices) data. In some cases, the data that passes through an external device interface408includes streaming data. The amount of streaming data that is passed through an external device interface408may be predetermined in some cases. Alternatively, the amount of streaming data passed through an external device interface408may be indeterminate, and in such cases, the external device may simply produce or consume data whenever the particular external device is enabled and so directed. External devices coupled through the external device interfaces408may include image sensors, digital microphones, display monitors, or other source and sink devices. InFIG.4, external device interface408includes a digital visual interface (DVI) external device interface408a, a first image sensor interface and image signal processor (ISP) external device interface408b, and a second image sensor interface and ISP external device interface408c. Other interfaces are also contemplated, though for simplicity in illustration, only three external device interfaces408are shown.

A plurality of processing modules410are integrated in the CAF400. Three processing modules410are illustrated for simplicity, but another selected number (e.g., two, four, eight, sixteen) of processing modules410may also be integrated in a CAF400at design time by a semiconductor practitioner. A first processing module410is an MPEG/JPEG processing module410aarranged to perform certain video (i.e., MPEG) processing and certain image (i.e., JPEG) processing. A second processing module410is an H264 processing module410b, which is arranged to perform particular video encoding/decoding operations. A third processing module410is a color converter processing module410n, which is arranged to perform color-based operations on certain multimedia data.

In many cases, the DMA controllers406, the external device interfaces408, the processing modules410, the convolution accelerators600, the arithmetic units for deep learning acceleration700, and other modules integrated in a CAF400are IP modules selected from a library by a semiconductor practitioner at design time. The semiconductor practitioner may specify the number of modules, features of particular modules, bus widths, power parameters, layout, memory availability, bus access, and many other parameters.

Table 2 is a non-exhaustive exemplary list of IP modules in a library; any of which may be incorporated into CAF400by a semiconductor practitioner. In many cases, as new modules are designed, and as existing modules are modified, the new IPs will be added to a library such as the library of Table 2.

TABLE 2CAF Library of IP modulesFunctional UnitApplicationRGB/YUV Sensor InterfaceInterfaceBayer Sensor InterfaceInterfaceVideo Out Interface (DVI)InterfaceFunctional UnitApplicationEnhanced I/O (Sensor Interface,InterfaceVideo Out, Overlay)ISP (Image Signal Processor)Signal ProcessingMini ISP (Image Signal Processor)Signal Processing (Bayer -> RGB)GP Color Converter UnitGeneral PurposeImage Cropper and Resizer UnitGeneral PurposeMorph Filter UnitGeneral PurposeBackground Remove Unit (+shadowBackground/Foregroundremove)segmentationReference Frame Update UnitBackground/ForegroundsegmentationJPEG EncoderEncoderJPEG DecoderDecoderH264 EncoderEncoderH264 EncoderEncoder (Baseline, Intra Only)Rectification and Lens DistortionStereo VisionCorrectionCensus Transformation Unit (BRIEF)Stereo VisionStereo Vision Depth Map GeneratorStereo VisionFeature Point Detector (FAST)Feature DetectionFeature Detection (Viola Jones)Face Detection (e.g.. IntegralImage, ISA Extension)Feature Detection (Optical Flow)Facial TrackingFeature Point ExtractorFeature Detection - Difference of(DoG + SIFT)Gaussian plus Scale InvariantFeature TransformFeature ExtractionEdge Extraction (Sobel, Canny)Clock and Interrupt ManagerSystem ControlDebug Support UnitDebugGP IO UnitGeneral Purpose3D convolution accelerator forProcessingneural networksFunctional UnitApplicationArithmetic Units for Deep LearningProcessing SupportAcceleration

In the configurable accelerator framework (CAF)400ofFIG.4, eight convolution accelerators600are represented, CA0 to CA7. In other CAF400embodiments, a different number of convolution accelerators are formed. The number of convolution accelerators600and the particular features available in each convolution accelerator600are, in some cases, based on parameter values selected by a semiconductor practitioner at design time.

The convolution accelerators (CA's)600are data processing units with a selected number (e.g., one, two, four, eight) of input and output stream link ports. One or more configuration registers (e.g., a set of configuration registers) are arranged to control operations of the CA600. In some cases, configuration registers are included in the CAF control registers402, and in these or other cases, certain configuration registers are formed as part of the CA600.

One or more convolution accelerator template modules may be included in an IP modules library such as the library described with respect to Table 2. In these cases, data stored in the IP modules library includes relevant building blocks that reduce the work required to build a new accelerator that implements an accelerator's core functionality. A predefined set of configuration registers can be extended. Configurable FIFOs formed or otherwise located at the stream link ports can be used to absorb data rate fluctuations and provide some buffering margin required to relax certain flow control constraints in a processing chain.

Typically, each CA600either consumes data, generates data, or both consumes data and generates data. Data that is consumed passes through a first stream link of the reconfigurable stream switch500, and data that is streamed passes through a second stream link of the stream switch500. In at least some embodiments, CA's have no direct access to memory address space accessible by the primary communications bus132(FIG.3), the secondary communications bus166(FIG.3), or other bus addresses. However, if random memory access to data passed on a system bus is required, a CA600may also use an optional bus port interface, which may be along the lines of the system bus interface module404ofFIG.4, which is used for several things including permitting DMA engines to access memory locations on the system bus. As discussed above, some CA600implementations are part of a library, which can be used in other CAF400embodiments to simply instantiate the CA600in a global system definition file.

One or more arithmetic unit for deep learning acceleration template modules may also be included in the IP modules library such as the library described with respect to Table 2. Here, the predefined set of configuration registers can be further extended to provide parameter storage for configuration of the included arithmetic units. The parameters are associated with configuration of any desirable number of multiplexor circuits, multiplier circuits, adder circuits, temporary storage circuits, data shift circuits, and other circuits.

Each arithmetic unit for deep learning acceleration700is solely dedicated to execution of the formula in Equation 1. Scalar data, vector data, streaming data, constant data, interleaved data, and any other desirable data available within the CAF400framework may be passed into the arithmetic units for deep learning acceleration as operands, and generated resultant data will be passed out from the respective arithmetic unit. The data passed into the arithmetic unit for deep learning acceleration700may be sourced from a stream switch500, a memory inside or outside of the CAF400frame work, a sensor or particular interface, or from some other source. Along these lines, each of these types of data sources may, in some cases, consume the data generated in the arithmetic unit. As discussed herein, some arithmetic unit for deep learning acceleration700implementations are part of a library, which can be used in other CAF400embodiments to simply instantiate the arithmetic unit in a global system definition file.

System level programmers of machine learning systems desire flexibility to choose a desirable programming model for their particular implementation. To support this high level of flexibility, the CAF400is arranged with a reconfigurable stream switch500. As described in the present disclosure, the stream switch500acts as a data transfer fabric to improve logic block (IP) reuse, data reuse, and the reuse of other components and logic, which in turn allows a reduction of on-chip and off-chip memory traffic, and which provides a much greater flexibility to leverage the same logic blocks in different application use cases. Integrated in the stream switch500is a plurality of unidirectional links arranged to transport data streams via a configurable fully connected switch to, from, and to and from different kinds of data sources, data sinks, and data sources and data sinks such as direct memory access (DMA) controllers, I/O interfaces (e.g., cameras), and various types of accelerators.

The transported data may take any desired format such as a stream of raster scan image frames, a stream of macroblock oriented images, audio streams, raw data blocks, a stream of input or output arithmetic unit values, or any other format. The stream switch500can also transport messages, commands, or other like control information along a processing chain forwarded by each unit to one or more or more targeted units where the control information is processed. The control information may be used to signal events, to reconfigure the processing chain itself, or to direct other operations.

FIG.5is a stream switch embodiment500in more detail. The stream switch500includes a user-selectable, design-time configurable first number of stream link input ports504and a user-selectable, design-time configurable second number of stream link output ports516. In some cases, there is the same number of input ports as there are output ports. In other cases, there are more input ports than output ports, and in still other cases, there are more output ports than input ports. The number of input ports and the number of output ports are defined at design time.

In the stream switch500embodiment ofFIG.5, one stream link502embodiment is shown in detail. Other stream links502a,502b, are also illustrated without detail for simplicity in the illustration. The stream links502a,502bare generally arranged along the lines of the stream link502, and for the sake of clarity in the disclosure any of the illustrated stream links may be identified as stream link502.

At run-time, stream switch500communicatively couples input stream link ports to output stream link ports through a stream link502according to configuration data written to certain ones of the CAF control registers402(FIG.4). In the embodiment, one or more of the input stream link ports504may be desirably arranged to concurrently forward received data streams to one or multiple (multicast) output ports516on the same clock cycle. Thus, one input stream link port can be communicatively coupled (e.g., electrically connected for the passage of data) to one or more output stream link interfaces, which results in a physical replication of the input data stream. The stream link502provides a straightforward, unidirectional interface to transport data streams and control information associated with the data streams. In such embodiments, a single control signal, which may in some cases be propagated on a single dedicated or shared data path, provides flow control.

Some conductors of the stream link are used to pass data; some other conductors may include a data validity indicator, a first pixel indicator, a last pixel indicator, a line type definition, and a stall signal. The stall signal is used as a back pressure (e.g., flow control) mechanism. In some embodiments of the stream link, image data, command data, control information, messages, and the like are passed in a frame-based protocol along the processing chain though the stream switch500.

In the stream switch500, each output port516is associated with a particular stream link502. InFIG.5, for example, output port X is associated with stream link502. In addition, one or more input ports504are associated with each stream link. In some cases, for example, each and every input port504is associated with each and every stream link502. In this way, each input port504may pass data to any and all output ports516at the same time or at different times.

Individual communication path conduits of the stream link are unidirectional. That is, signals on each communication path conduit flow in only one direction. In some cases, a plurality of communication path conduits unidirectionally accept data received from an input port and pass the data to one or more output ports. In these cases, and in other cases, a single communication path conduit unidirectionally receives command information (e.g., flow control information) from an output port and passes the command information to one or more input ports. In some other cases, the command information received from an output port and passed to one or more input ports is passed on two or more communication path conduits.

As shown in the detailed stream link502ofFIG.5, the set of unidirectional communication path conduits from a plurality of input ports504are passed into a data switch506. In some cases, the set of unidirectional communication path conduits from every input port504are passed into the data switch506. In other cases, the unidirectional communication path conduits of one or more, but less then all, input ports504are passed into a data switch506of a particular stream link502. The data switch506may include multiplexor logic, demultiplexor logic, or some other form of switching logic.

As shown inFIG.5, data passed into stream link502from a plurality of input ports504may be concurrently present at input nodes of the data switch506. A selection mechanism508is arranged to determine which input data is passed through the data switch506. That is, based on the selection mechanism508, the input data from one of input ports A, B, C, D is passed through the data switch506to an output of the data switch506. The output data will be passed on NA . . . Dunidirectional communication path conduits, which will match the number of unidirectional communication path conduits of the selected input port.

The selection mechanism508is directed according to stream switch configuration logic510. The stream switch configuration logic510determines at run time which input port504shall supply data to the associated output port, and based on the determination, the stream switch configuration logic510forms an appropriate selection signal that is passed to the data switch506. The stream switch configuration logic510operates at run time and in real time. The stream switch510may take direction from CAF control registers, from a DSP of the DSP cluster122(FIG.3), from the application processor128, or from some other control device. In addition, the stream switch configuration logic510may also take direction from message/command logic512.

In some embodiments, data is passed uniformly through each particular stream link502. That is, in some cases, one stream link502is configured (e.g. stream switch configuration logic510, CAF control registers, or the like) to cooperatively pass any number N of first datums (e.g., bits, bytes, words, nibbles, tuples, or some other data samples, etc.), and one or more other stream links502are similarly configured to pass corresponding second datums. In this configuration, for each datum passed through the first stream link502, there is a corresponding datum passed through each of the other one or more stream links502.

In other embodiments, data is not passed uniformly through each particular stream link502. Data may be interleaved, for example, or passed in another non-uniform way. In an interleaved embodiment, the various stream links502may be configured to interleave data. In one such interleaved example, a first stream link502may be arranged to pass “M” datums from a first source (e.g., input port504), and then the first stream link502may be arranged to pass “N” datums from a second source (e.g., a different input port504).

Alternatively, in yet one more interleaving embodiment, two stream links502may be arranged to pass different numbers of datums in a non-uniform way. That is, while a first stream link502is passing “M” datums, a second stream link502is simultaneously or concurrently passing “N” datums. In the examples, described herein, “M” and “N” are integers. In some cases, “M” and “N” are different integers.

In some stream switch500embodiments, certain specific messages that are passed through an input port504, for example by an interface or an accelerator, are recognized by command logic512in one or more stream links502of the stream switch500and used to reprogram one or more stream links502in real time. In these or in other embodiments, the stream switch500is configured to merge data streams according to fixed patterns. For example, in at least one case, a stream switch500may be arranged to select and pass data to an output port516by switching between input streams passed on two or more input ports504. For example, after each line, each frame, each N transactions, or by some other measure, the stream switch500may be configured to pass data from a different input port504to a selected output port516.

Data passed from the data switch506may, in some cases, pass through one or more optional output synchronization logic stages514. The output synchronization logic stages514may be used to store or otherwise buffer a selected amount (e.g., one or more bits, a few or many bytes, etc.) of data passed from a data source coupled to an input port504toward a data sink device coupled to an output port516. Such buffering, synchronizing, and other such operations may be implemented when data source devices and data sink devices operate at different rates, different phases, using different clock sources, or in other manners that may be asynchronous to each other.

The stream switch500includes a back pressure stall signal mechanism, which is used to pass flow control information from a sink device to a source device. The flow control information is passed from a sink device to inform a data stream source device to lower its data rate. Lowering the data rate will help to avoid a data overflow in the sink device.

One portion of the back pressure stall signal mechanism includes a back pressure stall signal path that is included in each input port. The back pressure stall signal path is arranged as a back pressure unidirectional communication path conduit. InFIG.5, four back pressure input port mechanisms are illustrated, BPA, BPB, BPC, BPD; one each for each of the illustrated input ports. In other embodiments, the back pressure mechanism of each input port may include one or more unidirectional communication path conduits. In some embodiments, the back pressure mechanism of each input port has the same number of unidirectional communication path conduits, which may be, for example, a single conduit. In these cases, for example, when a data source device coupled to the particular input port detects that a signal on the back pressure mechanism is asserted, the particular data source device will slow or stop the amount of data passed to the associated input port.

Each output port516includes another portion of a back pressure mechanism. One output port back pressure mechanism for each of the three illustrated output ports X, Y, Z, ofFIG.5are illustrated, BPX, BPY, BPZ. In some cases, each output port back pressure mechanism includes a same number of unidirectional communication path conduits (e.g., one). In other cases, at least one output port has a back pressure mechanism with a different number of unidirectional communication path conduits than another back pressure mechanism of another output port.

The output port back pressure mechanism conduits are passed to combinatorial back pressure logic518in each stream link502. InFIG.5, back pressure logic518receives back pressure control signals BPX, BPY, BPZ. The combinatorial back pressure logic518also receives control information from the stream switch configuration logic510. The combinatorial back pressure logic518is arranged to pass relevant flow control information back through the input port back pressure mechanism of an input port504to a particular data source device.

FIG.6is a convolution accelerator (CA) embodiment600. The CA600may be implemented as any one or more of the convolution accelerators600ofFIG.4.

The CA600includes three input data interfaces and one output data interface that are each arranged for coupling to a stream switch500(FIG.5). A first CA input data interface602is arranged for coupling to a first stream switch output port516, a second CA input data interface604is arranged for coupling to a second stream switch output port516, and a third CA input data interface606is arranged for coupling to a third stream switch output port516. A CA output data interface608is arranged for coupling to a selected stream switch input port504. The specific stream switch500port that each CA input data interface602,604,606and output data interface608is coupled to may be determined by default, at boot time, or at run time, and the specific coupling may be programmatically changed at run time.

In an exemplary embodiment, the first CA input data port602is arranged to pass a stream of batch data into the CA600, the second CA input data port604is arranged to pass a stream of kernel data into the CA600, and the third CA input data port606is arranged to pass a stream of feature data into the CA600. The output data port608is arranged to pass an output data stream from the CA600.

The CA600includes several internal memory buffers. The internal memory buffers may share a common memory space in some embodiments. In other embodiments, some or all of the internal memory buffers may be separate and distinct from each other. The internal memory buffers may be formed as registers, flip flops, static or dynamic random access memory (SRAM or DRAM), or in some other structural configuration. In some cases, the internal memory buffers may be formed using a multiport architecture that lets, for example, one device perform data “store” operations in the memory while another device performs data “read” operations in the memory.

A first CA internal buffer610is physically or virtually arranged in line with the first CA input data interface602. In this way, batch data streamed into the CA600may be automatically stored in the first CA internal buffer610until the data is passed to a particular math unit in the CA600such as an adder tree622. The first CA internal buffer610may be fixed with a size that is determined at design time. Alternatively, the first CA internal buffer610may be defined with a variable size that is determined programmatically at boot time or run time. The first CA internal buffer610may be 64 bytes, 128 bytes, 256 bytes, or some other size.

A second CA internal buffer612and a third CA internal buffer614are formed along the lines of the first CA internal buffer610. That is, the second and third CA internal buffers612,614may each have their own fixed size that is determined at design time. Alternatively, the second and third CA internal buffers612,614may have a variable size that is determined programmatically at boot time or run time. The second and third CA internal buffers612,614may be 64 bytes, 128 bytes, 256 bytes, or some other size. The second CA internal buffer612is physically or virtually arranged in line with the second CA input data interface604to automatically store streamed kernel data until the kernel data is passed to a dedicated fourth CA internal buffer616that is dedicated to storing kernel buffer data. The third CA internal buffer614is physically or virtually arranged in line with the adder tree622to automatically store summed data until it can be passed through the CA output interface604.

The fourth CA internal buffer616is a dedicated buffer arranged to desirably store kernel data and apply the stored kernel data to a plurality of CA multiply-accumulate (MAC) units620.

The fifth CA internal buffer618is a feature line buffer that is arranged to receive streamed feature data passed through the third CA input interface606. Once stored in the feature line buffer, the feature data is applied to the plurality of CA MAC units620. Feature and kernel buffer data applied to the CA MAC units620is mathematically combined according to the convolutional operations described herein, and the resulting output products from the CA MAC units620are passed to the CA adder tree622. The CA adder tree622mathematically combines (e.g., sums) the incoming MAC unit data and batch data passed through the first CA input data port.

In some cases, the CA600also includes an optional CA bus port interface624. The CA bus port interface624, when it is included, may be used to pass data into or out from the CA600from SoC global memory126or some other location. In some cases, the applications processor128, a DSP of the DSP cluster122, or some other processor directs the passage of data, commands, or other information to or from the CA600. In these cases, the data may be passed through the CA bus port interface624, which may itself be coupled to the primary communications bus132, the secondary communication bus166, or some other communications structure.

In some cases, the CA600may also include CA configuration logic626. The CA configuration logic626may be fully resident with the CA600, partially resident with the CA600, or remote from the CA600. The configuration logic600may, for example, be fully or partially embodied in the CAF control registers402, the SoC controllers120, or some other structures of the SoC110.

FIGS.7A-7Fmay collectively be referred to herein asFIG.7.

Embodiments of an arithmetic unit for deep learning acceleration700, configured in one way or another for a particular purpose, may be interchangeably referred to herein as any one of arithmetic unit for deep learning acceleration700A to700F.

FIG.7Ais a first high level block diagram700A illustrating certain data paths supported by arithmetic units for deep learning acceleration700in a neural network. It has been recognized that many supporting operations in a neural network, and particularly in a convolutional neural network arranged for deep learning, can be accomplished with one or more affine transformations. In such transformations, a plurality of related and co-equal data points organized as a frame are co-linearly transformed and translated by a scalar, a vector, a plurality of scalars or vectors, or the like. These transformations may be applied, for example, in image processing to accomplish rotation, scale, shear, or the like. And along these lines, these affine transformations may be applied to support deep learning sub-processes such as biasing, batch normalization, scaling, mean subtraction, element-wise addition, and other linear combinations of vector type operations such as max-average pooling, and the like.

InFIG.7A, an arithmetic unit for deep learning acceleration700is structured in hardware circuitry to perform Equation 1.
AX+BY+C→Output  (1)

The arithmetic unit for deep learning acceleration700can be configured and directed to perform certain data path computational operations that support memory bandwidth intensive state-of-the-art convolutional neural network algorithms. Rather than performing these operations with digital signal processors (DSPs), for example, which has heretofore been conventional, these data path computations can instead be merged and mapped onto one or more arithmetic units for deep learning acceleration700. The arithmetic unit for deep learning acceleration700executes the affine transformation according to the algorithm that defines the operations of the convolutional neural network.

The hardware circuitry of the arithmetic unit for deep learning acceleration700includes dedicated circuits to retrieve data, accept data, route data, multiply operands to produce products, add values to produce sums, shift values right or left by any number of places, combine data, serialize data, interleave data, and perform other like operations. The arithmetic unit for deep learning acceleration700may include registers, volatile memory arrays, non-volatile memory arrays, buffers, and other types of data repositories. Each arithmetic unit for deep learning acceleration700may have one or more circuits to perform the operations. For example, Equation 1 calls out two multiplication operations. An arithmetic unit for deep learning acceleration700in some embodiments may include a single multiplication circuit that is used and re-used to carry out the two multiplication operations. Alternatively, the arithmetic unit for deep learning acceleration700in other embodiments may include two or more multiplication units. Along these lines some embodiments of the arithmetic unit for deep learning acceleration700may include a single adder circuit, and other embodiments include two or more adder circuits.

InFIG.7A, the arithmetic unit for deep learning acceleration700is arranged with a first stream input X702and a second stream input Y704. The first and second stream inputs702,704may be selectively coupleable through the stream switch500to any type of streaming data source such as a convolutional accelerator600, an external device interface408(e.g., an image sensor interface), a direct memory access (DMA) engine406, or some other streaming data source. As illustrated inFIG.7A, the first and second stream inputs702,704are arranged to provide scalar data, vector data, or scalar and vector data that are processed as the “X” and “Y” operands, respectively, in Equation 1.

In some cases, the arithmetic unit for deep learning acceleration700is arranged to receive constant vector data from a vector constant memory706. The constant vector data may be provided once per iteration of Equation 1, and in other cases the vector constant data may be provided multiple times such as once for each iteration of Equation 1. That is, the constant vector data may be provided statically or as a stream of data that corresponds to streaming data X, streaming data Y, streaming data X and Y, interleaved data X and Y, or in some other way. In some cases, constant vector data is provided on one or more inputs as a single static datum for multiple iterations of Equation 1, and other constant vector data is provided on one or more inputs as streaming dynamic constant data across the multiple iterations of Equation 1.

In the embodiment ofFIG.7A, a first constant input A706A passes the constant vector data that is processed as the “A” operand in Equation 1, a second constant input B706B passes the constant vector data that is processed as the “B” operand in Equation 1, and a third constant input C706C passes the constant vector data that is processed as the “C” operand in Equation 1.

The vector constant memory706may, in some cases, be coupled to address generation circuitry708. The address generation circuitry708is arranged to provide timed and sequenced addresses in the vector constant memory706repository so that constant vector data may be timely provided to the arithmetic unit for deep learning acceleration700at vector constant inputs A, B, C,706A,706B,706C, respectively. The address generation unit708may include auto-sequencing circuitry to increment addresses, decrement addresses, offset addresses, apply constant or variable strides, interleave or generate addresses in some other pattern, or perform still other memory address configuration operations.

A set of configuration parameter circuits710are provided in the first high level block diagram700A ofFIG.7A. The configuration parameter circuits710may include memory, registers, buffers, and other repository circuitry that direct operations of the arithmetic unit for deep learning acceleration700. In some cases, the configuration parameter circuits710are arranged as part of the CAF control registers402(FIG.4).

Exemplary parameter repositories (e.g., sub-circuits of configuration parameter circuits710) include a repository for fixed point arithmetic shift constants710A, a repository for an operating mode710B, and a repository for scalar constants A, B, C,710C.

The fixed point arithmetic shift constants710A may include any number of right-shift values, left-shift values, or some other shift arrangement. The shift operations may be performed on multiply values, divide values, align values, scale values, sums, products, or shift data for another reason.

The operation mode710B may include circuitry that directs operations of the address generation unit708. Alternatively, or in addition, the operation mode710B repository stores data that directs operations of the arithmetic unit for deep learning acceleration700. The operation mode may include one or more parameters. The one or more parameters may, for example, direct selections lines of multiplexor circuits, provide constant values to various circuits in the arithmetic unit, direct operations of shift circuits (e.g., direction, number of positions, and the like), provide directions to combinatorial logic (e.g., input values, inversion circuitry, or the like), support these modules in different ways, and support other modules within the arithmetic unit for deep learning acceleration700.

The operation mode710B configuration parameter circuits may be arranged to work cooperatively with the address generation unit708in ways that flexibly support convolution operations of a machine learning algorithm. For example, operation mode710B parameters can be arranged to support feature input streams of any desirable shape. Because of this support, the feature volume is not limited to specific Width-by-Height-by-Depth (W×H×D) shapes as in at least some conventional cases. Instead, the operation mode710B configuration parameter circuits can direct the address generation unit708to support nearly any scalable and flexible three-dimensional (3D) tiling scheme and feature volume ‘walking’ scheme. By specifying the input geometry (i.e., W×H×D) of the feature volume, and by specifying the width-by-height-by-depth (w×h×d) dimensions of the 3D tile, and by specifying the walking order, the 3D tile can be walked through the feature volume in any order. For example, in one case, the 3D tile is walked through the feature volume across depth, followed by width, followed by height. In another case, the 3D tile is walked through the feature volume across width, followed by depth, followed by height. In a third case, the 3D tile is walked through the feature volume across depth, followed by height, followed by width. As evident in the examples of 3D tile walking, the feature volume can be navigated in many different ways by setting appropriate parameters in the operation mode710B configuration parameter circuits. Hence, the arithmetic unit for deep learning acceleration700can operate with incoming data in nearly any particular format. The address generation unit708is arranged to properly address the “A,” “B,” and “C” values to apply to the incoming data as specified by the input 3D tile walking order, the 3D tile geometry, and the feature volume geometry.

One advantage of the cooperative configuration parameter circuits710and the address generation unit708is that the convolution accelerator600that feeds the arithmetic unit can operate at any desirable granularity of data that is most acceptably optimal in terms of balancing performance, power, memory bandwidth, and data reuse; and in these cases, the convolution accelerator600can feed data directly to the arithmetic unit through stream switch500without any need to rearrange or reassemble the data in any other way. The machine learning algorithm specifies the expected 3D tile and feature volume input geometry using, for example, registers of the configuration parameter circuits710that cooperate with the address generation unit708.

In some cases, the address generation unit708may be implemented with a plurality of auto-reloading counters (e.g., four auto-reloading counters). The counters may be prioritized, cascaded, interleaved, or the counters may cooperate in other ways. Each of the counters may, for example, be used to “count” the directional walking of the 3D tile through the feature volume. For example, addresses can be auto-generated in the address generation unit708using values from the counters. By configuring the counters to cooperatively provide output values in a desired arrangement, a 3D tile can be controlled to “walk” across the height, width, and depth of the feature volume in the order specified by the machine learning algorithm.

Scalar constants A, B, C,710C may include bits, bytes, nibbles, words, or differently formed scalar values for application within the arithmetic unit for deep learning acceleration700. The scalar constants A, B, C,710C may include values stored in memory, buffers, registers, or some other repository. The circuitry forming the scalar constants A, B, C,710C may include timing circuitry, latches, interface structures, and the like. The scalar constants710C may be provided into the deep learning accelerator700in any desirable relationship with the streaming data X, Y, provided at first and second stream inputs702,702, respectively, and with vector constant data provided at vector constant inputs A, B, C,706A,706B,706C.

An output712of the arithmetic unit for deep learning acceleration700is arranged to pass sums, products, or other data generated in the arithmetic unit for deep learning acceleration700. The output712may pass discrete values. Alternatively in these or other embodiments, the output712may pass a stream of values.

Having now described the arithmetic unit for deep learning acceleration700and supporting circuit modules arranged around the arithmetic unit for deep learning acceleration700in some embodiments, the disclosure now describes a non-limiting set of use-cases for the unit. There are many uses for the arithmetic unit for deep learning acceleration700in machine learning systems, however cases described herein are directed to deep learning for convolutional networks for brevity. In these cases, the arithmetic units for deep learning acceleration700are not used for convolution, but they are instead used to support the convolutional features with increased data locality. In this way, data remains streaming rather than moving into and out of memory, which is an improvement over known convolutional systems. That is, as convolutional processes are carried out in the convolution accelerators600, data is streamed from and to one or more CA600structures, through stream switch500, and in to or out from one or more arithmetic units for deep learning acceleration700.

For example, some operations used in deep learning using convolutional neural networks include, biasing operations, batch normalization operations, scaling operations, mean subtraction operations, element-wise addition operations, and other linear combinations of vector-type operations used in max-average pooling operations, for example. An exemplary biasing operation is depicted in Equation 2; an exemplary batch normalization operation is depicted in Equation 3; an exemplary scaling operation is depicted in Equation 4; an exemplary mean subtraction operation is depicted in Equation 5; an exemplary element-wise addition operation is depicted in Equation 6, and an exemplary max-average pooling operation is depicted in Equation 7.

X+bias→Output(2)(X-mean)vari⁢a⁢n⁢c⁢e→Output(3)(X*scale_factor)+scale_bias→Output(4)(X-mean)*mean_scaling⁢_factor→Output(5)X⁢1+X⁢2→Output(6)(A*X)+(B*Y)→Output(7)

The nature of the operations represented in Equations 2-7 are vector operations depicted with “X” and “Y,” while constants such as “A,” “B,” “bias,” “mean,” “variance,” “scale_factor,” and the like can be vectors, scalars, or a both vectors and scalars. What is more, considering the nature of the transformations involved in deep learning and supported by the arithmetic unit for deep learning acceleration700, the inventors have recognized that substantial benefits may be achieved by combining multiple operations into a single affine transform operating on one or two input streams. In this way, data is not processed in a first operation, stored, and the retrieved for a second operation. Instead, a first operation is performed on first data that passes through the stream switch500, and the second data that is output from the operation is passed through the stream switch500directly into a second operation.

For example, a first linear operation is depicted in Equation 8, where operands in the linear operation are formed by the sub-operations of Equations 9 and 10.

(A*X)+B→Output(8)(scale_factor)vari⁢a⁢n⁢c⁢e→A(9)((bias-m⁢ean)*A)+scale_bias→B(10)

In this case, the affine transform realizes significant time savings because data is processed in a plurality of operations without requiring temporary storage of interim values. Instead, the “interim values” are passed through stream switch500into a concurrently operating arithmetic unit for deep learning acceleration700. In this way, several modes of operation are supported by the arithmetic units for deep learning acceleration700. That is, the arithmetic unit for deep learning acceleration700is structured for substantial flexibility providing any type of desirable constants, such as passing A, B, and C as vectors, scalars, or vectors and scalars in various use-cases. In one biasing case, for example, A and C are scalar constants where A is equal to one (i.e., A=1) and C is equal to zero (i.e., C=0), and B is a vector. This use case may, for example, be implemented where “length” is equal to the “depth” of an input feature three-dimensional (3D) volume. In another machine learning convolutional processing case where batch normalization is performed, C is equal to zero (i.e., C=0), and A and B are vectors. In mean subtraction embodiments with scaling, A and B are scalar constants and C is equal to zero (i.e., C=0). And in yet one more machine learning operation, that implements element-wise addition operations, scalar constants A and B are equal to one (i.e., A=1; B=1), so output is simply achieved as vector addition of X and Y (i.e., X+Y).

Various test cases have been performed by the inventors where, for example, vector data has been pre-loaded into vector constant memory706and scalar data is preloaded into the scalar constants A, B, C,710C repository. In other test cases, vector data is streamed in via stream switch500via vector constant input A706A, vector constant input B706B, and vector constant input C706C. In various ones of these test cases, where normalization, scaling, and biasing operations were performed, the inventors have realized two and one-half times (i.e., 2.5×) savings in parameter storage memory, faster execution of neural network convolutional operations, and reduced power consumption realized by avoiding intermediate memory storage of temporary data. Rather than storing five vectors, for example, only two vectors are stored and other parameters are streamed through the arithmetic units for deep learning acceleration700.

FIG.7Bis a second high level block diagram700B illustrating certain data paths supported by arithmetic units for deep learning acceleration700in a neural network. An algorithm implementing a deep learning program operating on an SoC110(FIG.3) embedded in a mobile device100configures the configurable accelerator framework400to cooperatively perform certain affine transformations using one or more arithmetic units for deep learning acceleration700to support concurrent convolution operations performed by one or more convolution accelerators600. Data locality is provided by passing data to and from the convolution accelerators600through stream switch500, and by concurrent processing in an arithmetic unit for deep learning acceleration700using data also passed through the stream switch500. One portion of the deep learning program inFIG.7Brepresents data paths to implement a max-average pooling operation.

A camera sensor, in one embodiment, provides a stream of image data150passed through a first image sensor interface and image signal processor (ISP) external device interface408band to a convolution accelerator600A via stream switch500. The convolution accelerator600A walks kernels of known data through the images in the stream of image data750. The data may be further processed in any number of additional convolution processes via convolution accelerator600A, another convolution accelerator, or some other structure of the CAF400. For the sake of simplifying the pertinent portions of the algorithm now under discussion, it is described that a stream of filtered image data752is passed from convolution accelerator600back through the stream switch500to a max pooling accelerator600B and an average pooling accelerator600C.

The max pooling accelerator600B produces a stream of max pooled image data754that is passed into the arithmetic unit for deep learning acceleration700, and the average pooling accelerator600C produces a stream of average pooled image data756that is also passed into the arithmetic unit for deep learning acceleration700. Both the stream of max pooled image data754and the stream of average pooled image data756are streams of vector data. In some embodiments, the stream of max pooled image data754corresponds to information passed on stream input X702(FIG.7A). In these or other embodiments, the stream of average pooled image data756corresponds to information passed on stream input Y704(FIG.7A).

In some cases, the streams of input data on stream input X and stream input Y are passed uniformly. That is, for each portion (e.g., datum) of max pooled image data754passed through stream input X702, a corresponding portion of average pooled image data756is passed through input Y704. In other cases, it may be desirable to pass data through stream inputs X, Y702,704, non-uniformly. In at least one case, “M” data samples are passed through stream input X702, and “N” data samples are passed through stream input Y704. In this interleaved way, selected datums from the max pooled image data754can be desirably processed with selected datums from the average pooled image data756. Many other non-uniform data flow arrangements are contemplated; such non-uniformity may be enabled by parameters stored, for example, in CAF control registers402(FIG.4), configuration parameter circuits710, or some other source.

The configuration parameter circuits710, which may include a repository for vector constants A, B, C,706A,706B,706C or for scalar constants A, B, C710A,710B,710C, pass constant data758into the arithmetic unit for deep learning acceleration700. To assist the present discussion, exemplary data passed into arithmetic unit for deep learning acceleration700is represented as Equations 11-14. Specifically, the exemplary stream of max pooled image data754is depicted in Equation 11; the exemplary stream of average pooled image data756is depicted in Equation 12; and the constant data758is depicted in Equations 13 and 14.
MaxPoolingImageData={mp1,mp2, . . .mpn}(11)
AveragePoolingImageData={av1,av2, . . .avn}(12)
(ConstantDataA)={a1,a2, . . . an}(13)
(ConstantDataB)={b1,b2, . . .bn}(14)

To further assist the present discussion, the exemplary resulting data (i.e., the stream of max-average pooled data760) that is generated by, and passed from, arithmetic unit for deep learning acceleration700is represented as Equation 15. In some embodiments, the stream of max-average pooled data760corresponds to information streamed on output712(FIG.7A).
MaxAvgPooledData={(a1*mp1+b1*av1),(a2*mp2+b2*av2) . . . ,(an*mpn+bn*avn)}  (15)

FIG.7Cis a third high level block diagram700C illustrating convolutional accelerators and an arithmetic unit arranged for an exemplary branch-merge operation in a neural network. It has been recognized by the inventors that in some cases, known network topologies may often include branches in machine learning algorithm. Considering image recognition, for example, one first set of convolution operations may process feature map data with kernels devoted to a first color, and one second set of convolution operations may process the same feature map data with kernels devoted to a second color. By taking advantage of the configurable accelerator framework400, the convolution operations for both colors can occur in parallel. What is even more efficient, if the machine learning algorithm later desires to merge the convolution streams back together, the arithmetic unit for deep learning acceleration700can be used concurrently with the convolution operations to rejoin the streams as represented, for example, inFIG.7C.

In the third high level block diagram700C, a camera sensor408bprovides streaming data to at least two convolution accelerators600A,600B, which perform convolution processing. In other cases, the input the convolution accelerators600may come from a different sensor, a different convolution accelerator600, memory, or some other device. In still other cases, any number of convolution accelerators600(FIG.6) may receive the input streaming data, or any other number of different devices may be communicatively coupled to the stream switch500to receive streaming data. InFIG.7C, output752A,752B from the convolution accelerators600A,600B, respectively, is passed through stream switch500to the arithmetic unit for deep learning acceleration700. The arithmetic unit for deep learning acceleration700also receives input from vector constant memory706(FIG.7A), configuration parameter circuits710(FIG.7A), or some other data source (e.g., control registers402(FIG.4)). Upon receiving input stream data from the plurality of branched sources, the arithmetic unit for deep learning acceleration700combines the data according to the particular formula described herein (i.e., AX1+BY2+C) and streams the resulting data761back through the stream switch500. It is shown that the streaming data is passed into a stream engine DMA engine406in the embodiment ofFIG.7C, but data may be streamed to other destinations in other cases. For example, in cases where more than two branches are merged, the output from the arithmetic unit for deep learning acceleration700may be streamed through the stream switch500to a second arithmetic unit for deep learning acceleration700, which also receives data streamed from a third branch.

The branch-merge operations illustrated inFIG.7Cclearly illustrate more efficient operations than previously known. The branch-merge operation is performed with a single unit, and concurrently to other operations (e.g., convolution, bias, normalization, scaling, and any other operations) before the merge operation is conducted. In this way, data is re-used without having to be streamed into a remote memory device and streamed back out from the remote memory device. These operations save power, on-chip area, time, and the like. Desirably, the operations scale to perform as many concurrent operations as permitted by the available resources.

FIG.7Dis a first data flow diagram700D illustrating structures configurable to execute a single dedicated formula (i.e., AX+BY+C) with a arithmetic unit for deep learning acceleration700in a neural network. In view of the operations illustrated and described in the present disclosure, it can be appreciated that the arithmetic unit for deep learning acceleration700is highly configurable, and based on the configuration parameters, the arithmetic unit for deep learning acceleration700is capable of configuration for bias operations (e.g., (AX+C)), mean subtraction operations (e.g., (AX−C)), scaling/batch normalization operations (e.g., (AX+C)), element-wise addition/subtraction operations (e.g., (X+Y), (X−Y)), max-average pooling operations (e.g., (AX+BY)), branch-merge operation (e.g., (AX+BY+C)) and many other operations. The configuration may, for example, be supported using one or more of the configuration parameter circuits710(FIG.7A) such as the operation mode710B repositories.

The arithmetic unit for deep learning acceleration700inFIG.7Dis solely dedicated to performance of a plurality of parallel operations wherein each one of the plurality of parallel operations carries out a portion of a formula, the formula being: output=AX+BY+C. The arithmetic unit includes a plurality of inputs762that are selectively coupleable to any one or more of the stream switch500(FIG.4), control registers402(FIG.4), vector constant memory706(FIG.7A), configuration parameter circuits710(FIG.7A), or some other data source. The arithmetic unit for deep learning acceleration700also includes multiplexor circuitry764, multiplier circuitry766, temporary storage circuitry768, data shift circuitry770, adder circuitry772, and post summation circuitry that may include latch circuitry774and configurable direction shift circuitry776. Information is streamed or otherwise passed from the arithmetic unit for deep learning acceleration700via an output712. In some cases, the resultant output data from the arithmetic unit is passed via output712to the stream switch500, a memory, or some other circuitry.

In some embodiments, the arithmetic unit for deep learning acceleration700circuitry ofFIG.7Dis formed in an integrated circuit. In some embodiments, the integrated circuit is arranged for convolutional neural network operations. The arithmetic unit circuitry may be formed in the same integrated circuit as the stream switch500and other circuits of the configurable accelerator framework400(FIG.4). In addition, or in the alternative, embodiments of the arithmetic unit for deep learning acceleration circuitry ofFIG.7Dmay be formed in the same integrated circuit as other circuits of SoC100(FIG.3).

The arithmetic unit for deep learning acceleration700circuitry has one or more multi-input selection circuits764(e.g., multiplexors, multiplexor circuitry, multiplexor circuits, or the like) communicatively coupled to the plurality of inputs762. In the data flow diagram ofFIG.7D, a first multiplexor circuit764A is communicatively coupled to receive scalar data A from a scalar repository such as a register (e.g., scalar constants A, B, C,710C), and vector data A from a vector repository such as vector constant memory706, stream switch500, or some other vector data source. A selection input A-Type is directed to pass either the scalar data A or the vector data A through the first multiplexor circuit764A toward a first multiplier766A. The selection input A-Type may be communicatively coupled to and directed by data in the CAF control registers402(FIG.4), the configuration parameter circuits710(FIG.7A), or some other selection information source.

Also in the data flow diagram ofFIG.7D, a second multiplexor circuit764B is communicatively coupled to receive scalar data B from a scalar repository such as a register (e.g., scalar constants A, B, C,710C), and vector data B from a vector repository such as vector constant memory706, stream switch500, or some other vector data source. A selection input B-Type is directed to pass either the scalar data B or the vector data B through the second multiplexor circuit764B toward a second multiplier766B. The selection input B-Type may be communicatively coupled to and directed by data in the CAF control registers402(FIG.4), the configuration parameter circuits710(FIG.7A), or some other selection information source.

The data flow diagram ofFIG.7Dalso depicts a third multiplexor circuit764C communicatively coupled to receive scalar constant data (e.g., “0”, “1”, or some other constant scalar data), scalar data C from a scalar repository such as a register (e.g., scalar constants A, B, C,710C), vector constant data (e.g., “0,0”; “0,1”; “1,0”; or some other constant vector data), and vector data C from a vector repository such as vector constant memory706, stream switch500, or some other vector data source. A selection input C-Type is directed to pass either the constant or variable scalar data C or the constant or variable vector data C through the third multiplexor circuit764C toward third data shift circuitry770C. The selection input C-Type may be communicatively coupled to and directed by data in the CAF control registers402(FIG.4), the configuration parameter circuits710(FIG.7A), or some other selection information source.

Based on the operation that the arithmetic unit for deep learning acceleration700is directed to perform, the plurality of inputs762are arranged to pass vector data into the arithmetic unit, scalar data into the arithmetic unit, or a combination of vector data and scalar data into the arithmetic unit.

The multiplier circuitry766is arranged as a plurality of multiplier circuits. A first multiplier circuit766A, and a second multiplier circuit766B are represented inFIG.7D, but some other number of multiplier circuits may instead be formed. For example, in some cases, a single multiplier circuit is arranged in the arithmetic unit that is shared or otherwise used. In other cases, a plurality of three or more multiplier circuits is included. Each multiplier circuit is arranged to accept multiplicand data, multiplier data, or both multiplicand data and multiplier data from the multiplexor circuitry. In some cases, such as in the embodiment ofFIG.7D, multiplicand data, multiplier data, or both multiplicand data and multiplier data is passed directly into the multiplier circuitry766without first passing through the multiplexor circuitry764. The multiplier circuitry766is arranged to perform at least some multiplication operations of the formula implemented by the arithmetic unit for deep learning acceleration700. As arranged inFIG.7D, a first multiplier circuit766A receives either scalar A data or vector A data and stream input X vector data, which may come, for example, from stream switch500(FIG.5). As further arranged inFIG.7D, a second multiplier circuit766B receives either scalar B data or vector B data and stream input Y vector data, which may come, for example, from stream switch500(FIG.5). The multiplier circuitry766produces a product when so provided with multiplicand and multiplier data.

The product data produced by the multiplier circuitry766is passed into temporary storage circuitry768. The temporary storage circuitry768may be arranged as one or a plurality of temporary storage repositories. For example, product data from multiplier766A is passed into a temporary storage circuit768A, which may be a register, and product data from multiplier766B is passed into a temporary storage circuit768B, which may be a register.

Data passed through the third multiplexor circuit764C is received at third data shift circuitry770C. Based on the operations directed in the particular machine learning algorithm, the data received at third data shift circuitry770C may be shifted by a particular amount passed via input C-Shift. The parameter data passed into C-Shift may be retrieved from CAF registers402(FIG.4), configuration parameter circuits710, or some other source. In some cases, where the “C” operand in the formula (e.g., AX+BY+C) is constant, the third data shift circuitry770C may be disabled, optionally left out of the arithmetic unit, or otherwise rendered out of the data path. Shifted or otherwise desirable data passed through the third multiplexor circuit764C is optionally stored in a third temporary storage circuit768C. The optional storage may be implemented or otherwise used to align data operations according to a pipeline structure, a sequencing model, or for some other reasons.

Product data from the first multiplier circuit766A may be optionally stored in a first temporary storage circuit768A, and product data from the second multiplier circuit766B may be optionally stored in a second temporary storage circuit768B. The optional storage may be implemented or otherwise used to align data operations according to a pipeline structure, a sequencing model, or for some other reasons. In the data path ofFIG.7D, data passed from the first multiplier represents the “AX” product in the formula (e.g., AX+BY+C), and data passed from the second multiplier represents the “BY” product in the formula (e.g., AX+BY+C).

The data passed from first and second multipliers766A,766B, respectively, and through optional first and second temporary storage circuits768A,768B, respectively, is received at first and second data shift circuitry770A,770B, respectively. The product data may be shifted by a particular amount passed via input AX-Shift and BY-Shift inputs, respectively. The parameter data passed into AX-Shift and BY-Shift inputs may be retrieved from CAF registers402(FIG.4), configuration parameter circuits710, or some other source.

Adder circuitry772is arranged to sum data from the AX data path, the BY data path, and the C data path. The adder circuitry772may be formed as a single summing circuit, cascaded summing circuits, sequenced summing circuits, or in any other arrangement. In the data path ofFIG.7D, adder circuitry772nis communicatively coupled to receive data from first data shift circuitry770A, second data shift circuitry770B, and third temporary storage circuitry768C. The adder circuitry772nmay be directed by an algorithm to perform at least some summation operations of the (AX+BY+C) formula.

In some cases, the sum data from the adder circuitry772is directly passed out from the arithmetic unit for deep learning acceleration700. In other cases, determined post-summation circuitry may be included in the arithmetic unit. In the data path ofFIG.7D, the post-summation circuitry includes latch circuitry774and directional shift circuitry776. These circuits may be optional. In some cases, the data produced by a formula that is implemented in the arithmetic unit is captured in a latch circuit774nfor timing purposes, alignment purposes, sequencing purposes, or for other purposes. And a directional shift circuit776nis arranged to bit-wise align the output data from the adder circuitry772n, which may have optionally been captured in latch774n.

The directional shift circuitry776may be directed by shift direction parameters (i.e., “Shift-Direction” inFIG.7D) and shift amount parameters (i.e., “Result-Shift” inFIG.7D). The directional shift of the output sum data may be for timing alignment, bit-wise data alignment, normalization, scaling, or for some other reason. Data passed from the post-summation circuitry is communicated via output712through stream switch500, memory, or some other circuitry.

In some cases, the shift values (e.g., Result-Shift, Shift-Direction) are used to shift intermediate values (e.g., any one or more of AX, BY, C) and additionally or alternatively used to shift final values to provide flexible fixed point computations. With these parameters, the machine learning algorithm can flexibly use nearly any fixed point math format with selectable or variable integer and fractional parts for each value that is input to or passed out from the arithmetic units for deep learning acceleration700. The shift values permit alignment of intermediate results (e.g., any one or more of AX, BY, C) before the mathematical operation. In these or other cases, Result-Shift parameter permits generation of values the meet the output fixed point format directed by the machine learning algorithm. In some embodiments of the data flows ofFIGS.7D-7F, internal values are limited to “left” shifting, but in other embodiments, the shift direction may be selected.

In one exemplary case of use, a plurality of the arithmetic units for deep learning acceleration700are arranged according to an (AX+BY+C) data path. The data path is implemented as a set of acts of a particular machine learning method. For example, the method may be a portion of a deep convolutional neural network procedure or otherwise arranged to implement such a procedure. The procedure may be carried out by SoC100to identify at least one feature in certain input data, such as, for example, identifying a particular feature in an image or set of images to an acceptable level of certainty.

In the procedure to identify a feature in a set of streaming image sensor data, a feature volume is defined in the image sensor data. The feature volume has a feature volume height, a feature volume width, and a feature volume depth. An input tile is also defined having an input tile height, an input tile width, and an input tile depth. The input tile is walked through the feature volume. Such a process includes streaming the image sensor data through the reconfigurable stream switch500to a convolution accelerator unit600. In the convolution accelerator unit600, the image sensor data is convolved to produce a stack of kernel maps.

Also in the procedure, a first convolution accelerator600is configured to perform a max pooling operation, a second convolution accelerator600is configured to perform an average pooling operation, and an arithmetic unit for deep learning acceleration700is configured to perform a max-average pooling operation (e.g., AX+BY+0). The arithmetic unit is solely dedicated to performance of the mathematical operations that can be implemented according to the (AX+BY+C) formula. In yet other cases, the arithmetic units for deep learning acceleration700may be configured to perform bias operations, mean operations, scaling operations, branch merge operations, or still other operations.

Continuing the procedure, the stack of kernel maps is streamed through the reconfigurable stream switch500to the first and second convolution accelerators600. The max pooling operation is performed with the first convolution accelerator600, and max pool data is streamed through the reconfigurable stream switch500as the input data to the arithmetic unit for deep learning acceleration700. The average pooling operation is performed with the second convolution accelerator600, and average pool data is streamed through the reconfigurable stream switch500as the input data to the arithmetic unit for deep learning acceleration700. The arithmetic unit for deep learning acceleration700performs the max-average pooling operation, and streaming max-average pool data is passed through the reconfigurable stream switch.

In more detail, considering the procedures now under discussion, streaming input data is passed through a reconfigurable stream switch500(FIG.5) to convolution accelerators600and to the arithmetic units for deep learning acceleration700. The arithmetic units are solely dedicated to performance of a formula, the formula being: output=AX+BY+C. Streaming data passed into the arithmetic unit may be, for example, streaming image sensor data (e.g., camera sensor data408B inFIG.7B) from an image sensor coupled to the stream switch500, interim data generated during a machine learning process (e.g., during a convolution process), or some other data.

FIG.7Eis a second data flow diagram700E illustrating one-by-one (1×1) support operations of an arithmetic unit for deep learning acceleration700in a neural network. Final stage circuitry778at the output of the second data flow diagram700E is represented inFIG.7F.

FIG.7Fis a third data flow diagram700F illustrating operations of an arithmetic unit for deep learning acceleration700in a neural network in a final stage778of a convolutional process.

The final stage circuitry778inFIG.7Eis in, at least some embodiments, a second arithmetic unit for deep learning acceleration700cascaded to the first arithmetic unit for deep learning acceleration700depicted inFIG.7E. This second arithmetic unit depicted inFIG.7Fis configured differently from the first arithmetic unit depicted inFIG.7E.

A description of structures inFIG.7Ethat correspond to structures inFIG.7Dmay be introduced without repeating a further detailed description for brevity. The arithmetic unit includes a plurality of inputs762that are selectively coupleable to the stream switch500(FIG.4) or another data source. The arithmetic unit for deep learning acceleration700includes multiplexor circuitry764, multiplier circuitry766, temporary storage circuitry768, data shift circuitry770, and final stage circuitry778. Other circuitry of the arithmetic unit (e.g., adder circuitry, post summation circuitry, latch circuitry, and the like) are optionally not used in the one-by-one support operations and not shown inFIG.7E. Information is streamed or otherwise passed from the arithmetic unit for deep learning acceleration700via output712to the stream switch500, a memory, or some other circuitry.

Two additional multiplexor circuits764D,764E inFIG.7Eare arranged to selectively pass, uniformly (i.e., data at stream X has a one-to-one correspondence with data at stream Y) or non-uniformly (e.g., interleaved or some other non-uniform arrangement), streaming vector data, such as from stream input X702and stream input Y704, to respective multiplier circuitry766. Based on an algorithm that selects which products are directed for generation, an XY-Mode selection signal will direct passage of either constant data A or streaming vector data Y through multiplexor circuit764D to multiplier766A. Along these lines, the same or a different machine learning algorithm can select which products are directed for generation, using a Cony-Mode selection signal to direct passage of either streaming vector data X or streaming vector data Y to multiplier766B. Yet additional programming choices are available to a machine learning algorithm that will direct product generation in a multiplier circuit766C of constant scalar or vector data with streaming vector data X. The algorithm may further direct, via the Conv-Mode signal, whether the product data from multiplier circuit766C or whether the constant scalar or vector data will be passed through a multiplexor circuit764F to the third temporary storage circuitry768C.

In the arithmetic unit ofFIG.7E, multiplier-produced product data will be stored in the first and second temporary storage circuitry768A,768B. Shift circuitry770coupled to the temporary storage circuits768is controlled by a machine learning algorithm to arrange the data in any desired way. In some cases, of course, no shifting is necessary. The data from the shift circuitry770is passed through final stage circuitry778before passage on output712to the stream switch500(FIG.5), a storage repository such as a memory arranged for vector storage, or some other circuitry.

A description of structures in the arithmetic unit for deep learning acceleration700ofFIG.7Fthat correspond to structures inFIG.7Dmay be introduced without repeating a further detailed description for brevity. The arithmetic unit includes a plurality of inputs762that are selectively coupleable to the stream switch500(FIG.4) or another data source. Parametric inputs, for example, such as XY-Mode and Conv-Mode, may be sourced from CAF control registers402, configuration parameter circuits710, or another source. The arithmetic unit for deep learning acceleration700ofFIG.7Fincludes multiplexor circuitry764, adder circuitry772, temporary storage circuitry768, data shift circuitry770, and serializer circuitry780. Other circuitry of the arithmetic unit are optionally not used in the embodiment ofFIG.7F.

In the third data flow embodiment ofFIG.7F, parametric input including an XY-Mode signals, a Conv-Mode signals, Result-Shift signals, Shift-Direction signals, Active Kernel Count signals, and other such parametric information is made via inputs762. The inputs may draw information from a machine learning algorithm, CAF control registers402, configuration parameter circuits710, or some other source. InFIG.7F, combinatorial logic782, and in at least one embodiment a logical OR-gate782n, is arranged to pass signal information representative of the XY-Mode and Cony-Mode parameters. The signal information is used in multiplexor circuitry764. Based on the XY-Mode and Cony-Mode parameters, a streaming input representing certain dot product values (BY) or cached recurring data are passed through multiplexor circuit764G to adder circuitry772G. The same XY-Mode and Cony-Mode signal information is also used as selection information for multiplexor circuit764nto selection values that will be passed through output712of the final stage778circuitry.

The Conv-Mode signal information is applied to selection inputs of multiplexor circuit764H and multiplexor circuit764I. The Cony-Mode signal here determines whether constant information (e.g., zero) or cached recurring data from temporary storage circuitry768H is passed through multiplexor circuit764H to adder circuitry772H. And the Cony-Mode signal also determines whether summation data from adder circuit772G or recurring data from temporary storage circuitry768I is passed through multiplexor circuit764I to adder circuitry772I.

Adder circuits772in the final stage778ofFIG.7Fperform summing operations according to a machine learning algorithm and pass output data to temporary storage circuits768. More specifically, the output of adder circuits772G,772H, and772I is respectively loaded into temporary storage circuits768G,768H, and768I, respectively. Data from the temporary storage circuits768is passed through optional shift circuitry770before being passed to serializer circuitry780. More specifically, the data from temporary storage circuits768G,768H, and768I is loaded into data shift circuits770G,770H, and770I, respectively. A serializer circuit780ngroups, packetizes, or otherwise forms the output data that will be selective passed through multiplexor circuit764nto output712.

In at least one instance of the second and third data flow diagrams ofFIGS.7E,7F, a stream of constant vectors enters the arithmetic unit for deep learning acceleration700in data flow700E ofFIG.7E. The stream of constant vectors enters on the stream input Y, and a stream of vector data enters the arithmetic unit on the stream input X. The arithmetic unit is directed by a machine learning algorithm to perform a one-by-one (1×1) convolution or dot-product operation. Various parameters are programmed by the machine learning algorithm into the CAF control registers402, the configuration parameter circuits710, or another structure. These parameters are used to direct the operations of the arithmetic units for deep learning acceleration700in accordance with the first and second data flows ofFIGS.7E and7F.

Still considering processing in the second data flow700E ofFIG.7E, for example, the XY-Mode parameter is arranged to specify a one-by-one (1×1) convolution operation using both X and Y inputs, and the Conv-Mode parameter is arranged to specify one-by-one (1×1) convolution using vector data passed on stream input X and kernel vectors stored in vector constant memory706(FIG.7A) or scalar constants A, B, C, stored in configuration parameter circuits710(FIG.7A).

In a non-limiting example, when XY-Mode is “1,” and when vector data is streamed on input X from stream switch500, and when convolution kernel weight vectors are streamed on input Y from stream switch500, the arithmetic unit will perform a one-by-one (1×1) convolution of the data, which may be streamed through output712back into stream switch500and into the third data flow700F ofFIG.7F. What is more, if Conv-Mode is “1,” it is possible to cache/load the kernel weights in local memory such as vector constant memory706(FIG.7A) and pass the constants via vector constant inputs706A,706B,706C (FIG.7A) so that up to three one-by-one-by-D kernels can be cached, wherein “D” is the line length of the internal line buffers for storing A, B and C constants. Further still, in a heretofore unavailable way, the cached data can be reused if needed to operate on the vector data streamed on input X and corresponding to convolution feature data. In this way, the operations selectively performed in the second data flow700E ofFIG.7Ecan include those identified in Equation 16.
output=(X*Y)|(A*X)|(B*X)|(C*X)  (16)

The equations performed depend on settings of the XY-Mode and Cony-Mode parameters. The performance of the formula may also include use of internal accumulators for to store partial convolution results before generating the output.

The present disclosure refers to a “semiconductor practitioner.” A semiconductor practitioner is generally one of ordinary skill in the semiconductor design and fabrication arts. The semiconductor practitioner may be a degreed engineer or another technical person or system having such skill as to direct and balance particular features of a semiconductor fabrication project such as geometry, layout, power use, included intellectual property (IP) modules, and the like. The semiconductor practitioner may or may not understand each detail of the fabrication process carried out to form a die, an integrated circuit, or other such device.

FIGS.7A-7Finclude data flow diagrams illustrating non-limiting processes that may be used by embodiments of the mobile computing device100. In this regard, each described process may represent a module, segment, or portion of software code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some implementations, the functions noted in the process may occur in a different order, may include additional functions, may occur concurrently, and/or may be omitted.

The figures in the present disclosure illustrate portions of one or more non-limiting computing device embodiments such as mobile device100. The computing devices may include operative hardware found in conventional computing device apparatuses such as one or more processors, volatile and non-volatile memory, serial and parallel input/output (I/O) circuitry compliant with various standards and protocols, wired and/or wireless networking circuitry (e.g., a communications transceiver), one or more user interface (UI) modules, logic, and other electronic circuitry.

Amongst other things, the exemplary mobile devices of the present disclosure (e.g., mobile device100ofFIG.3) may be configured in any type of mobile computing device such as a smartphone, a tablet, a laptop computer, a wearable device (e.g., eyeglasses, jacket, shirt, pants, socks, shoes, other clothing, hat, helmet, other headwear, wristwatch, bracelet, pendant, other jewelry), vehicle-mounted device (e.g., train, plane, helicopter, unmanned aerial vehicle, unmanned underwater vehicle, unmanned land-based vehicle, automobile, motorcycle, bicycle, scooter, hover-board, other personal or commercial transportation device), industrial device (e.g., factory robotic device, home-use robotic device, retail robotic device, office-environment robotic device), or the like. Accordingly, the mobile devices include other components and circuitry that is not illustrated, such as, for example, a display, a network interface, memory, one or more central processors, camera interfaces, audio interfaces, and other input/output interfaces. In some cases, the exemplary mobile devices may also be configured in a different type of low-power device such as a mounted video camera, an Internet-of-Things (IoT) device, a multimedia device, a motion detection device, an intruder detection device, a security device, a crowd monitoring device, or some other device.

Processors, as described herein, include central processing units (CPU's), microprocessors, microcontrollers (MCU), digital signal processors (DSP), application specific integrated circuits (ASIC), state machines, and the like. Accordingly, a processor as described herein includes any device, system, or part thereof that controls at least one operation, and such a device may be implemented in hardware, firmware, or software, or some combination of at least two of the same. The functionality associated with any particular processor may be centralized or distributed, whether locally or remotely. A processors may interchangeably refer to any type of electronic control circuitry configured to execute programmed software instructions. The programmed instructions may be high-level software instructions, compiled software instructions, assembly-language software instructions, object code, binary code, micro-code, or the like. The programmed instructions may reside in internal or external memory or may be hard-coded as a state machine or set of control signals. According to methods and devices referenced herein, one or more embodiments describe software executable by the processor, which when executed, carries out one or more of the method acts.

In some cases, the processor or processors described in the present disclosure, and additionally more or fewer circuits of the exemplary mobile devices described in the present disclosure, may be provided in an integrated circuit. In some embodiments, all of the elements shown in the processors of the present figures (e.g., SoC110) may be provided in an integrated circuit. In alternative embodiments, one or more of the arrangements depicted in the present figures (e.g., SoC110)6may be provided by two or more integrated circuits. Some embodiments may be implemented by one or more dies. The one or more dies may be packaged in the same or different packages. Some of the depicted components may be provided outside of an integrated circuit or die.

The processors shown in the present figures and described herein may be fixed at design time in terms of one or more of topology, maximum available bandwidth, maximum available operations per unit time, maximum parallel execution units, and other such parameters. Some embodiments of the processors may provide re-programmable functionality (e.g., reconfiguration of SoC modules and features to implement a DCNN) at run-time. Some or all of the re-programmable functionality may be configured during one or more initialization stages. Some or all of the re-programmable functionality may be configured on the fly with no latency, maskable latency, or an acceptable level of latency.

As known by one skilled in the art, a computing device as described in the present disclosure, and mobile device100being such a computing device, has one or more memories, and each memory comprises any combination of volatile and non-volatile computer-readable media for reading and writing. Volatile computer-readable media includes, for example, random access memory (RAM). Non-volatile computer-readable media includes, for example, read only memory (ROM), magnetic media such as a hard-disk, an optical disk, a flash memory device, and/or the like. In some cases, a particular memory is separated virtually or physically into separate areas, such as a first memory, a second memory, a third memory, etc. In these cases, it is understood that the different divisions of memory may be in different devices or embodied in a single memory. The memory in some cases is a non-transitory computer medium configured to store software instructions arranged to be executed by a processor.

In the present disclosure, memory may be used in one configuration or another. The memory may be configured to store data. In the alternative or in addition, the memory may be a non-transitory computer readable medium (CRM) wherein the CRM is configured to store instructions executable by a processor. The instructions may be stored individually or as groups of instructions in files. The files may include functions, services, libraries, and the like. The files may include one or more computer programs or may be part of a larger computer program. Alternatively or in addition, each file may include data or other computational support material useful to carry out the computing functions of the systems, methods, and apparatus described in the present disclosure.

The computing devices illustrated and described herein, of which mobile device100is one example, may further include operative software found in a conventional computing device such as an operating system or task loop, software drivers to direct operations through I/O circuitry, networking circuitry, and other peripheral component circuitry. In addition, the computing devices may include operative application software such as network software for communicating with other computing devices, database software for building and maintaining databases, and task management software where appropriate for distributing the communication and/or operational workload amongst various processors. In some cases, the computing device is a single hardware machine having at least some of the hardware and software listed herein, and in other cases, the computing device is a networked collection of hardware and software machines working together in a server farm to execute the functions of one or more embodiments described herein. Some aspects of the conventional hardware and software of the computing device are not shown in the figures for simplicity, but are well understood by skilled practitioners.

When so arranged as described herein, each computing device may be transformed from a generic and unspecific computing device to a combination device comprising hardware and software configured for a specific and particular purpose. Along these lines, the features of the combination device bring improvements to the technological computing arts heretofore unseen and unknown.

Database structures, if any are present in the mobile devices or supporting network devices described herein, may be formed in a single database or multiple databases. In some cases hardware or software storage repositories are shared amongst various functions of the particular system or systems to which they are associated. A database may be formed as part of a local system or local area network. Alternatively, or in addition, a database may be formed remotely, such as within a “cloud” computing system, which would be accessible via a wide area network or some other network.

In at least one embodiment, mobile devices described herein may communicate with other devices via communication over a network. The network may involve an Internet connection or some other type of local area network (LAN) or wide area network (WAN). Non-limiting examples of structures that enable or form parts of a network include, but are not limited to, an Ethernet, twisted pair Ethernet, digital subscriber loop (DSL) devices, wireless LAN, WiFi, cellular-based networks, or the like.

Buttons, keypads, computer mice, memory cards, serial ports, bio-sensor readers, touch screens, and the like may individually or in cooperation be useful to an operator of the mobile device or other such devices as described herein. The devices may, for example, input control information into the system. Displays, printers, memory cards, LED indicators, temperature sensors, audio devices (e.g., speakers, piezo device, etc.), vibrators, and the like are all useful to present output information to the operator of these mobile devices. In some cases, the input and output devices are directly coupled to the control systems described herein and electronically coupled to a processor or other operative circuitry. In other cases, the input and output devices pass information via one or more communication ports (e.g., RS-232, RS-485, infrared, USB, etc.)

Unless defined otherwise, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the present invention, a limited number of the exemplary methods and materials are described herein.

In the foregoing description, certain specific details are set forth to provide a thorough understanding of various disclosed embodiments. However, one skilled in the relevant art will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with electronic and computing systems including client and server computing systems, as well as networks, have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the embodiments.

Unless the context requires otherwise, throughout the specification and claims which follow, the word “comprise,” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense, e.g., “including, but not limited to.”

Reference throughout this specification to “one embodiment” or “an embodiment” and variations thereof means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content and context clearly dictates otherwise. It should also be noted that the conjunctive terms, “and” and “or” are generally employed in the broadest sense to include “and/or” unless the content and context clearly dictates inclusivity or exclusivity as the case may be. In addition, the composition of “and” and “or” when recited herein as “and/or” is intended to encompass an embodiment that includes all of the associated items or ideas and one or more other alternative embodiments that include fewer than all of the associated items or ideas.

In the present disclosure, conjunctive lists make use of a comma, which may be known as an Oxford comma, a Harvard comma, a serial comma, or another like term. Such lists are intended to connect words, clauses or sentences such that the thing following the comma is also included in the list.

The headings and Abstract of the Disclosure provided herein are for convenience only and do not limit or interpret the scope or meaning of the embodiments.

The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, application and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.