Patent ID: 12211770

DETAILED DESCRIPTION

Embodiments of a semiconductor package design that enables downward scaling of the package footprint while maintaining high electrical isolation of the semiconductor die or dies are disclosed herein. The lead frame of the semiconductor package is devoid of a die pad. That is, there is no large metal structure in a central region of the semiconductor package with a die attach surface that accommodates the mounting of one or more semiconductor dies completely thereon. Instead, the lead frame comprises elongated lead structures that are configured to accommodate the mounting of the semiconductor dies directly on these leads. These leads extend past other leads on the same side of the package so as to provide a gap that extends directly between these leads. Different to a lead frame that utilizes a die pad, the leads only support a fraction of the overall area of the semiconductor die, with the remaining surface area laterally overhanging past the leads. By omitting the die pad, a space reduction is made possible because there is no need to satisfy chip to die paddle clearance requirements. Moreover, this concept can be used to accommodate two semiconductor dies in a semiconductor package, wherein the omission of two die pads allows for a package size reduction by eliminating the need to provide an isolation area between the two die pads.

Referring toFIG.1, a semiconductor package100comprises an encapsulant body102. The encapsulant body102comprises an electrically insulating material such as a mold compound, epoxy, resin, ceramic, etc. The encapsulant body102comprises an upper surface104and a lower surface106opposite from the upper surface104. The encapsulant body102further comprises outer edge sides110extending between the upper and lower surfaces104,106. The semiconductor package100further comprises a number of leads112protruding from the outer edge sides of the encapsulant body102. The leads112provide externally accessible points of electrical contact to the semiconductor die or dies that are encapsulated by the encapsulant body102. As shown, the semiconductor package100has a so-called surface mount device (SMD) configuration wherein the package leads112bend downward and comprise a contact surface that is substantially coplanar with the lower surface of the encapsulant body102. More generally, the concepts described herein are applicable to a variety of semiconductor package100types, e.g., through-hole package types, no-lead package types (DFN, QFN, etc.).

The semiconductor package100may be configured as a discrete power device. A discrete power device refers to a single packaged device that is configured to block high voltages and and/or to conduct high currents as between two load terminals. Generally speaking, a discrete power device may be rated to block voltages of at least 100V, and more commonly on the order of 250V, 500V, 600V, 1,200V, 2,000V and/or may be rated to conduct currents of 10A, 50A, 100A, 500A or more. For example, the semiconductor package100may be configured as a discrete transistor package, e.g., a discrete MOSFET (Metal Oxide Semiconductor Field Effect Transistor) die, a discrete IGBT (Insulated Gate Bipolar Transistor) die, a discrete HEMT (High Electron Mobility Transistors) die, a discrete JFET (Junction Field Effect Transistors) die, etc. In addition to a switching device, the semiconductor package100may comprise additional elements integrated therein. For example, the semiconductor package100may comprise a driver die that is configured to control the switching operation of the switching device and/or may include a diode die that is configured as a reverse conduction diode. The semiconductor package100may also be configured as a power conversion circuit, such as a half-bridge circuit with multiple transistor dies that form the high-side switch and the low-side switch of the half-bridge circuit.

Referring toFIG.2, an example of a lead frame200that is used to produce the semiconductor package100is depicted, according to an embodiment. The lead frame200is a metal structure formed from electrically conductive metals such as copper, nickel, aluminum, palladium, gold, and alloys or combinations thereof. The lead frame200can be provided from a substantially uniform thickness piece of sheet metal, e.g., a sheet comprising any one or more of the above listed metals, and the various features of the lead frame200depicted and described herein can be formed by performing metal processing techniques such as stamping, punching, etching, bending, etc., on this planar sheet of metal. The lead frame200can comprise a core of low-resistance metal, e.g., copper, aluminum, and one or more coatings, e.g., adhesion promotors, anti-oxidation coatings, etc. The lead frame200comprises a plurality of leads112. Each of the leads112comprise an interior end114that faces a central region116of the lead frame200, and outer sidewalls118that are opposite from one another, extend away from the interior ends114, and extend towards a dambar structure120of the lead frame200. The lead frame200additionally comprises a peripheral ring122that surrounds the features of the lead frame200and is attached to the leads112. The basic geometry shown inFIG.2may be repeated multiple times in a lead frame strip that allows for the production of multiple ones of the semiconductor package100in parallel.

The lead frame200comprises a first group124of the leads112. The leads112from the first group124are configured such that a gap126is disposed between the outer sidewalls118of immediately adjacent ones of the leads112from the first group124. The leads112from the first group124may be longer than all other leads112that are connected to the same dambar structure120so that the outer sidewalls118of the leads112from the first group124may define the boundaries of the gap126. That is, the outer sidewalls118of the leads112from the first group124directly face one another and define the gap126. This gap126provides an area for a semiconductor die to be mounted without contacting other ones of the leads112on the same side of the semiconductor package100as the first group124of the leads112. According to an embodiment, a total area of the gap126is at least 1 mm2(square millimeter), and may be in the range of 1 mm2-5 mm2, for example.

As shown, the first group124of leads112comprises a first one of the leads112and a second one of the leads112. The first and second ones of the leads112define a gap126that extends between a first one of the outer sidewalls118from the first one of the leads112and a first one of the outer sidewalls118from the second one of the leads112. According to an embodiment, the separation distance between the first one of the outer sidewalls118from the first one of the leads112and a first one of the outer sidewalls118from the second one of the leads112is least 1 mm (millimeter), and may be in the range of 1 mm-5 mm. The first one of the outer sidewalls118from the first one of the leads112lead may be parallel to the first one of the outer sidewalls118from the second one of the leads. Moreover, these outer sidewalls118may intersect with the interior ends114of the respective leads so as to define a gap126that is rectangular. Alternatively, the outer sidewalls118of the leads112from the first group124may have different geometries from what is shown. For example, the leads112from the first group124may have locally widened geometries, tapered geometries, etc. such that the gap126is not necessarily rectangular.

The lead frame200comprises a second group128of the leads112. The second group128of the leads112are arranged in a row between the first and second ones of the leads112of the first group124, and are connected to the same dambar structure120as the leads112from the first group124. The second group128of the leads112may comprise locally widened regions at the interior ends114of these leads112so as to facilitate the attachment of bond wires thereon.

The number and configuration of the leads112from the first group124and/or the leads112from the second group128may vary from the specifically depicted embodiment. For instance, the second group128of the leads112can comprise different numbers of leads112from what is shown, e.g., two of the leads112, four of the leads112, etc. Additionally or alternatively, the first group124of the leads112may comprise additional leads112, e.g., three, four, five, wherein one of the gaps126is between immediately adjacent pairs of leads112from the first group124. In that case, additional ones or groups of the leads112may be provided between each immediately adjacent pair of leads112from the first group124. Additionally or alternatively, additional ones of the leads112may be provided outside of the outermost ones of the leads112from the first group124.

The lead frame200additionally comprises a third group130of the leads112and a fourth group132of the leads112. The third and fourth groups130,132of the leads112are disposed on an opposite side of the lead frame200and are connected to a different dambar structure120as the first and second groups124,128of the leads112. The leads112from the third group130are configured such that a second gap126is disposed between the outer sidewalls118of immediately adjacent ones of the leads112from the second group130in a similar manner as the first group124of the leads112. As shown, the third group130of the leads112may comprise first and second ones of the leads112that are arranged to define the second gap126in a similar manner as the first and second leads112from the first group124defining the first gap126. Moreover, the leads112from the fourth group132are arranged in a row between the first and second ones of the leads112of the third group130in a similar manner as the leads112from the second group128relative to the first group124. In the depicted embodiment, the lead frame200has a symmetrical configuration wherein each of the leads112on one side of the semiconductor package100(i.e., the first and second groups of124,128of the leads112) mirror the geometry of each of the leads112on the opposite side of the semiconductor package100(i.e., the third and fourth groups130,132of the leads112). Alternatively, the lead frame200may have an asymmetric configuration wherein the third group130of the leads112(if present) and/or the fourth group of the132of leads112(if present) may have a different configuration as the first and second groups124,128of the leads112, respectively. These configurations include any of the previously described configurations of the leads112from the first and second groups124,128.

As can be appreciated fromFIG.2, the lead frame200used to produce the semiconductor package100is devoid of a die pad structure. Instead, the lead frame200only includes lead structures, i.e., elongated structures that are arranged in a row and connected with the dambar portions120of the lead frame200. This allows for a reduction in package footprint by eliminating a structure that occupies a substantial amount of area, i.e., the die pad or die pads. In the case of a lead frame200with two die pads disposed on opposite halves of the device, the ability to shrink this structure may be limited by a minimum separation distance that must exist between the interior edge sides of the die pads that face one another. The lead frame configuration disclosed herein substantially reduces the overlap length between two conductive structures that are connected to two different dies and directly face one another. Thus, improved electrical isolation between two dies within a semiconductor package can be improved.

Referring toFIG.3, the semiconductor package100comprises a first semiconductor die134mounted on the first group124of the leads112. The first semiconductor die134is mounted such that a lower surface136of the first semiconductor die134faces and overlaps with each of the leads112from the first group124. Thus, the first semiconductor die134is physically supported by the leads112from the first group124.

According to an embodiment, the portions of the first group124of the leads112that extend to the interior end114of the leads112from the first group124are non-overlapping with the lower surface136of the first semiconductor die134. That is, the first semiconductor die134is mounted such that the leads112from the first group124extend across opposite facing outer edge sides of the first semiconductor die134. Alternatively, the interior ends114of the leads112from the first group124may be disposed directly underneath the first semiconductor die134. The first semiconductor die134may comprise a first terminal (not shown) disposed on the lower surface136of the first semiconductor die134that is electrically connected to at least one of the first and second leads112from the first group124, e.g., in the case that the first semiconductor die134is a vertical device. Alternatively, the first and second leads112from the first group124may exclusively serve as support structures, e.g., in the case that the first semiconductor die134is a lateral device. According to an embodiment the second one of the leads112from the first group124(the leftmost one of the leads112inFIG.3) is electrically inactive. That is, no electrical connection is provided between the first semiconductor die134and this lead112. In that case, the portion of the second one of the leads112from the first group124may be trimmed during the lead trimming process (to be described in further detail below) such that this lead112does not protrude out from the encapsulant body102. Alternatively, the second one of the leads112may be used to provide redundant electrical connectivity with the first one of the leads112.

According to an embodiment, the first semiconductor die134comprises a second group of terminals138disposed on an upper surface140of first semiconductor die134that is opposite from the lower surface136of first semiconductor die134. At least some of the terminals138on the upper surface140of the first semiconductor die134are electrically connected to the leads112from the second group128of. As shown, these electrical connections are provided by bond wires. Alternatively, other types of electrical interconnect features such as clips, ribbons, etc. may be used to effectuate these electrical connections.

As shown, the semiconductor package100may further comprise a second semiconductor die135. The second semiconductor die135is mounted on the third group130of the leads112such that a lower surface136of the second semiconductor die135faces and overlaps with each of the leads112from the third group130. The second semiconductor die135may comprise a first terminal (not shown) disposed on the lower surface136of the second semiconductor die135that is electrically connected to at least one of the first and second ones of the leads112from the third group130, e.g., in the case that the second semiconductor die135is a vertical device. Alternatively, the first and second leads112from the third group130may exclusively serve as support structures, e.g., in the case that the second semiconductor die135is a lateral device. The second semiconductor die135may comprises a second group of terminals138disposed on an upper surface140of second semiconductor die135that is opposite from the lower surface136of second semiconductor die135. At least some of second group of terminals138from the second semiconductor die135may be electrically connected to the leads112from the fourth group132. Moreover, at least some of the terminals138from the second semiconductor die135may be electrically connected to the terminals138from the first semiconductor die134. As shown, these electrical connections are provided by bond wires. Alternatively, other types of electrical interconnect features such as clips, ribbons, etc. may be used to effectuate these electrical connections.

Generally speaking, the first and second semiconductor dies134,135can have a wide variety of device configurations. For example, the first and second semiconductor dies134,135can be configured as discrete devices, e.g., Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), HEMTs (High Electron Mobility Transistors), diodes, etc. Alternatively or in combination, first and second semiconductor dies134,135can be configured as integrated circuit devices, e.g., drivers, controllers, etc. The first and second semiconductor dies134,135can include IV semiconductor materials, e.g., silicon, silicon germanium, silicon carbide, etc., and/or type III-V semiconductor materials, e.g., gallium nitride, gallium arsenide, etc. One or both of the first and second semiconductor dies134,135can be configured as a vertical device, which refers to a device that is configured to current flowing between a main surface and an opposite facing rear surface of the semiconductor die. Alternatively, one or both of the first and second semiconductor dies134,135can be configured as a lateral device, which refers to a device that is configured to current parallel to a main surface of the semiconductor die.

According to an embodiment, at least one of the first and second semiconductor dies134,135are configured as discrete power transistors. A discrete power transistor is a switching device that is rated to accommodate voltages of at least 100 V (volts) and more commonly on the order of 600 V, 1200V or more and/or is rated to accommodate currents of at least 1 A (amperes) and more commonly on the order of 10 A, 50 A, 100 A or more. Exemplary device types of discrete power transistors include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and HEMTs (High Electron Mobility Transistors), for example.

According to an embodiment the first semiconductor die134is configured as a power transistor die and the second semiconductor die135is configured as driver die. The power transistor die comprises first and second load terminals and a control terminal. One of the first and second load terminals and the control terminal may be provided by the terminals138on the upper surface140of the first semiconductor die134and the other one of the first and second terminals may be provided on the lower surface136of the first semiconductor die134, for example. The driver die comprises an output terminal, which may be provided by the terminals138on the upper surface140of the second semiconductor die135. The driver die is configured to control a switching operation of the power transistor die through a connection between the output terminal of the driver die and the control terminal of the power transistor die.

Referring toFIG.3C, a view of the lower surface136of the first semiconductor die134is provided, i.e., from the opposite perspective as the view ofFIG.3A. As can be seen, a significant percentage of the overall area of first semiconductor die134is unsupported by any structure. This unsupported area includes a first areal portion142of the lower surface136of the first semiconductor die134that extends over the gap126between the leads112from the first group124. The first areal portion142may be at least 50 percent of the overall area of the lower surface136of the first semiconductor die134, and may be at least 60 percent the of the overall area, at least 70 percent the of the overall area, or more. Moreover, as shown, additional portions of the lower surface136of the first semiconductor die134outside of the gap126may be unsupported such that the overall unsupported area may be between at least 50 percent and at least 95 percent of the of the overall area of the lower surface136of the first semiconductor die134in various embodiments. The lower surface136of the second semiconductor die135may likewise extend across the third group130of the leads112in a similar manner with the same areal portions of the lower surface136of the second semiconductor die135being unsupported.

Forming the semiconductor package100may include the following process steps. The lead frame200as shown and described with reference toFIG.2may be provided on a carrier. Subsequently, the first semiconductor die134may be mounted on the first group124of the leads112and the second semiconductor die135may be mounted on the third group130of leads112. In the case that an electrical connection is provided between a first terminal of the first semiconductor die134and the first group124of the leads112and/or between a first terminal of the second semiconductor die135and the third group130of leads112, the mounting may comprise a soldering or sintering process. In the case that no electrical connection is provided, a non-conductive an adhesive such as glue or tape may be provided between the lower surface136of the first semiconductor die134and the first group124of the leads112and/or between the lower surface136of the second semiconductor die135and the second group128of the leads112. The solder material and/or non-conductive adhesive maintains the position of the first and second semiconductor dies134,135during subsequent assembly steps before forming the encapsulant body102such that the first and second semiconductor dies134,135are secured in place and do not laterally slide or slip off of the leads112. After securing the semiconductor dies, the electrical connections between the upper surface terminals138of the first and second semiconductor dies134,135may be completed, e.g., by performing a wire bonding process, clip attachment, etc. Subsequently, the encapsulant body102may be formed by a molding process such injection molding, transfer molding, compression molding, etc. Subsequently, a lead trimming process may be performed to detach each of the leads112from the peripheral ring122and the dam bar structures120. Finally, the outer portions of the leads112may be bent, e.g. to have the depicted surface mount device configuration.

Referring toFIG.4, a semiconductor package100with a first semiconductor die134mounted on the leads112from the first and third groups124,130of the leads112is depicted, according to an embodiment. In this embodiment, the lower surface136of the first semiconductor die134extends across the gap126between the first and second ones of the leads112from the first group124and additionally extends across the second gap126between the first and second ones of the leads112from the third group130. Moreover, the first semiconductor die134extends across a central region116of the lead frame200that is between the interior ends114of the leads112from the first group124and the interior ends114of the leads112from the third group130. Generally speaking, the overall unsupported area may be at least 50 percent of the overall area of the lower surface136of the first semiconductor die134, and may be between 60 and 95 percent of the overall area of the lower surface136of the first semiconductor die134in various embodiments. By providing support at all four outer corners of the first semiconductor die134, the amount of overlap with the leads112can be minimized and the separation distance between the interior ends114of the leads112from the first group124and the interior ends114of the leads112from the third group130can advantageously be made higher. As can also be seen inFIG.4, the first and third groups130of the leads112may have a downset configuration wherein sections of these leads112that extend to the respective interior ends114are vertically below central sections of these leads112. This may aid in maintaining the position of the semiconductor die134during assembly and before encapsulation.

Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second,” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.