Patent ID: 12261564

FIG.1shows the basic circuit diagram of a drive circuit for a DC motor M, which can be connected to a supply voltage VS via a bridge circuit4. In the exemplary embodiment illustrated, the bridge circuit4here has two half-bridges, each of which is formed with two switches connected in series, the series circuits being connected in parallel with one another. In this case, the first half-bridge is formed with a first switch T1and a second switch T2connected in series therewith, which, in the exemplary embodiment illustrated, are realized with field effect transistors having in each case a substrate diode D1and D2, respectively. The second half-bridge likewise has two switches connected in series, the third switch S1and the fourth switch S2merely being indicated schematically. The third and fourth switches S1, S2can also be formed with field effect transistors having substrate diodes.

By way of example, if the first switch T1and the fourth switch S2are switched on, then a current flows from the high potential of the supply voltage VS through the DC motor M to the low potential of the supply voltage VS, which is usually a ground terminal.

If the DC motor M is turned off again by the first switch T1being switched off, then a current path—a so-called freewheeling path—must be present which makes a current possible such that the magnetic energy stored in the coils of the DC motor M can dissipate again. This can be effected for example via the substrate diode D2of the second switch T2. However, such substrate diodes D1, D2have a relatively high on-state resistance, and so a high power loss is generated in this way. It is better for the freewheeling path also to be embodied with a switched element, for example a transistor, which is effected by means of the second switch T2in the exemplary embodiment illustrated inFIG.1.

However, the first switch T1and the second switch T2must be prevented from being switched on simultaneously, since otherwise the supply voltage VS would be short-circuited.

The switches T1, T2, S1, S2of the bridge circuit4are driven by a circuit arrangement3, which is preferably realized in an integrated circuit optimized for the operation of bridge circuits4, for the purpose of controlling DC motors M. Such a circuit arrangement3embodied in an integrated circuit only needs to receive a control signal from a control unit2, preferably formed with a microprocessor or a microcontroller, said control signal specifying the bridge circuit voltage VB which is intended to be set at the DC motor M.

The bridge circuit voltage VB is set by way of a pulse width modulation of the drive signal for either the first switch T1or, for reverse operation, the second switch T2, such that an average bridge supply voltage VB is established at the DC motor M depending on the duty cycle of said drive signal. The switching frequency for the drive signal of the switches of the bridge circuit4is in the range of 15 to 20 kHz in the case of small motors, thus accordingly resulting in a period duration of said drive signal of approximately 50 to 67 μs.

FIG.2illustrates a period of such a drive signal for, by way of example, the first transistor T1of the bridge circuit4in the upper signal profile. A period duration TPWM has a first phase T1on, in which the first transistor T1is switched on, and a second phase, in which said transistor is switched off. During this switch-off phase, a current flows through the motor M and ensures that the magnetic energy in the motor M can dissipate, either through the substrate diode D2of the second switch T2or, if the latter is switched on, through the switch T2itself. This is illustrated in the second signal profile inFIG.2.

In that case, after the first switch T1has been turned off, firstly there is a wait during a drive pause tCCP, in which none of the switches is actuated, and then the second switch T2is switched on during a time duration T2on. There must also be a drive pause tCCP between turning off the second switch T2and switching the first switch T1on again, in order that the first and second switches T1, T2are not simultaneously in the on state, since otherwise, as already explained above, a short-circuit current would flow.

The lower signal profile inFIG.2illustrates the voltage VB at the junction point between the first and second transistors T1, T2, which voltage, during a period duration TPWM, firstly during the switch-on time T1on of the first which T1, virtually corresponds to the value of the supply voltage VS and, during the succeeding drive pause tCCP, assumes a floating value and then, during the drive time T2on of the second switch T2, virtually corresponds to the potential of the ground terminal and, finally, during the drive pause tCCP, once again assumes a floating state.

The ratio between the switch-on time T1on of the first switch T1and the period duration TPWM is usually referred to as the duty cycle and, on the basis of the example of the bridge circuit4inFIG.1, determines the average voltage VB at the DC motor M, said average voltage being established at the junction point between the first and second switches T1, T2. This will be elucidated once again inFIG.3.

The latter, too, once again illustrates a period of the drive signal for the first switch T1with a period duration TPWM, the upper signal profile illustrating only a short switch-on time, such that only a low bridge supply voltage VB results from the average value of the time in which the first switch T1is switched on and the time in which said first switch is switched off. If a significantly longer switch-on time is chosen, as is illustrated in the lower signal profile of the drive signal for the first switch T1, then a significantly higher bridge supply voltage VB correspondingly results. However, the switch-on time cannot be chosen to be equal to the period duration TPWM, since the drive pauses tCCP prevent this. The maximum switch-on time ton_max is correspondingly depicted in the lower signal profile inFIG.3. This maximum switch-on time for the first switch T1thus results in a maximum bridge supply voltage VB, which is illustrated inFIG.4.

FIG.4illustrates a drive sequence for the DC motor M in which the motor is firstly switched on and the bridge supply voltage VB is increased until it reaches a maximum voltage VBDTY_max on account of the maximum switch-on time of the first switch T1in the case of a maximum duty cycle DTY_max.

On account of the request from the control unit1(FIG.1), the bridge supply voltage VB should rise, but that cannot take place on account of the problem outlined above. It is only if the requested bridge supply voltage VB falls below the maximum bridge supply voltage VBDTY_max again that the set voltage can again correspond to the required voltage. This becomes particularly problematic if on account of the circumstances in a motor vehicle with a greatly varying supply voltage VS, the maximum bridge supply voltage VBDTY_max then established is no longer sufficient for operating the DC motor M.

In order to avoid this problem, the circuit arrangement3embodied as an integrated circuit is designed, as an alternative to driving the switching transistor T1by pulse width modulation, to operate said switching transistor in the so-called DC mode, in which the motor M is connected to the supply voltage VS during the entire period duration TPWM. This is illustrated inFIG.5, the switchover into this DC mode being effected when the maximum duty cycle DTY_max is reached. However, as can be seen fromFIG.5, an abrupt jump results, which leads to problematic regulation conditions.

In order to avoid this problem, in the manner according to the invention, during the time duration in which the required supply voltage for the DC motor M is greater than the maximum bridge supply voltage VBDTY_max possible in pulse-modulated operation, a number of drive time durations TPWM_SLOW are now generated, during which a number Ns of control time durations TSZD succeed one another, either a number of pulse-width-modulated period durations TPWM or switching over into the DC mode being effected during these control time durations TSZD.

This is illustrated inFIG.6. The latter illustrates in the upper diagram a drive time duration TPWM_SLOW having a number Ns of 16 control time durations TSZD in the example illustrated. In the exemplary embodiment illustrated, this drive time duration TPWM_SLOW has 15 successive control time durations TSZD, which are filled for example with a number of period durations of a signal with 20 kHz in the illustrated example, which have the maximum duty cycle TDY_max. This example illustrates just one control time duration TSZD in the DC mode at the end of the drive time duration TPWM_SLOW.

As an alternative thereto, the middle signal profile illustrates the situation when only a number nDZ equalling 10 successive control time durations TSZD with a maximum duty cycle of the drive signal are effected, while that is followed by six succeeding control time durations TSZD in the DC mode. In the third example, just one control time duration TSZD with pulse-width-modulated period durations is illustrated, while 15 control time durations in the DC mode are illustrated. Correspondingly, the average voltage resulting from this driving would become greater and greater, and so it is evident that as a result of this method the bridge supply voltage VB is nevertheless possible even in the case where exclusively pulse-width-modulated driving is effected.

FIG.7illustrates, with the aid of a table and a corresponding diagram, that in the case of a number Ns of 16 control time durations TSZD during a drive time duration TPWM_SLOW, a setting of the resultant duty cycle for the drive time duration can be set in percentage steps.

If the phases of the control time durations TSZD with pulse width modulation and the phases of the control time durations TSZD in the DC mode, as illustrated inFIG.6and inFIG.8, are applied to the first switch T1of the bridge circuit4for a number nDC of 8 in each case in succession, then this results in a periodic drive signal having a fundamental which is at a frequency which is perceptible as unpleasant humming.

In order to avoid this, in one advantageous development of the method according to the invention, as is illustrated inFIG.9, an arbitrary or, as also illustrated inFIG.9, an approximately uniform distribution of the phases with pulse width modulation and the phases in the DC mode can be distributed within a control time duration TSZD. In the case of a uniform distribution, although a fundamental can once again arise, this fundamental is in a significantly higher frequency range and has a smaller amplitude.