Patent ID: 12241946

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

This disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The particular embodiments are merely illustrative of specific configurations and do not limit the scope of the claimed embodiments. Features from different embodiments may be combined to form further embodiments unless noted otherwise.

Variations or modifications described to one of the embodiments may also apply to other embodiments. Further, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

While inventive aspects are described primarily in the context of a reserve capacitor of a supplemental restraint system (SRS), the inventive aspects may be similarly applicable to any electronic device that can benefit from a measurement of a capacitor of the electronic device. Such devices can profit from the measurement of a voltage drop over an unknown voltage baseline to determine the proper functioning of the capacitor.

Generally, a vehicle's supplemental restraint system includes one or more reserve capacitors that provide an alternative energy source for the system if the primary energy source (e.g., vehicle's primary battery) becomes disabled or inaccessible. During regular operation, a charging circuit charges the reserve capacitor through, for example, the vehicle's primary battery. Typically, the reserve capacitor is isolated from the deployment circuit to minimize the load on the charging circuit. In the event of a crash and the absence of the primary energy source, an isolation circuit detects vehicle ignition voltage loss and connects the reserve capacitor to the deployment circuit for the continued operation of the supplemental restraint system.

An airbag control module of the supplemental restraint system cyclically evaluates for hardware failures and communicates any errors with the vehicle's diagnostic computer through a diagnostic trouble code (DTC). In response, the vehicle's dash panel displays errors through, for example, a flashing airbag warning light to the user.

Embodiments of this disclosure can be used to determine the capacitance of the reserve capacitor and its equivalent series resistor (ESR). Once the capacitance and equivalent series resistor values are computed, the health of the reserve capacitor can be determined. A diagnostic trouble code (DTC) is generated if the reserve capacitor is determined to be faulty based on the computation. The diagnostic trouble code generates a warning signal that alerts the vehicle owner of the supplemental restraint system issues.

Embodiments of this disclosure provide an application-specific integrated or standalone circuit used in combination with a circuit implemented in a standard supplemental restraint system. In combination, the circuits provide various functions, such as power management, deployment functionality for drivers (e.g., supporting both squib and low-energy actuator loads), deployment functionality for regulators, remote sensor interfaces (e.g., supporting Peripheral Sensor Interface 5 (PSI5) satellite sensors), diagnostic functionality, deployment arming, hall-effect sensor interfaces, switch sensor interfaces, general-purpose low-side drivers, watchdog functionality, local internet network (LIN) interface, and the like.

Aspects of this disclosure include an improved technique over existing circuits. In embodiments, the systems and methods disclosed herein improve the measurement accuracy, minimize dissipation associated with measurements, and minimize component count used to make measurements. In particular embodiments, the measurement techniques provide an improved system and method to measure the health of a reserve capacitor used in a supplemental restraint system.

In an embodiment, a discharge resistor is coupled to a terminal of the reserve capacitor to dissipate power during a discharge phase of the circuit. A switch is arranged in series between the reserve capacitor and the discharge resistor, which is activated and deactivated in response to a control signal associated with the discharge phase.

In an embodiment, during a single discharge routine from time t1, to time t2, a difference in voltage at the terminal of the reserve capacitor between time t1, and time t2is measured. The discharge routine includes sinking a current through the discharge resistor from time t1, to time t2. During the same discharge routine phase, an integration of a difference in voltage at terminals of the discharge resistor is measured. Once the difference in voltage and the integration values are measured, because the resistance value of the discharge resistor is known, a logic circuit can compute the capacitance value of the reserve capacitor. Based on the difference between the computed capacitance value and a threshold value, the health of the reserve capacitor can be determined.

In another embodiment, during a single discharge routine, a discharge resistor is coupled to a terminal of the reserve capacitor. A difference in voltage at the terminal of the reserve capacitor during time t1, and a second difference in voltage at the terminal of the reserve capacitor during time t2is measured. A difference in voltage across terminals of the discharge resistor at time t1is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the discharge resistor from time t1to time t2. At time t2, a second difference in voltage across the terminals of the discharge resistor is measured. Once the various parameters are measured, the equivalent series resistor value of the reserve capacitor is computed. Based on the difference between the computed equivalent series resistor value and a threshold value, the health of the reserve capacitor can be determined.

In such an embodiment, the difference in voltage at the terminal of the reserve capacitor during time t1corresponds to a sharp voltage drop at the terminal from about 64 microseconds before time t1and approximately 64 microseconds after time t1. Further, the difference in voltage at the terminal during time t2corresponds to a sharp voltage jump at the terminal from about 64 microseconds before time t2and about 64 microseconds after time t2. Time t1corresponds to the time at which the discharge circuit coupled to the reserve capacitor is enabled. Time t2corresponds to the time at which the discharge circuit is disabled.

In an embodiment, the difference in voltage at the terminal of the reserve capacitor during time t1is a difference between the steady-state voltage and a voltage corresponding to a first change in slope of the voltage at the reserve capacitor after time t1. Thus, the difference in voltage is a difference between the steady-state voltage value before the discharge circuit is enabled and the voltage immediately before the first change in slope of the voltage after the discharge circuit is enabled.

In an embodiment, the difference in voltage at the terminal during time t2is a difference in voltage at the terminal of the reserve capacitor immediately before a second change in slope and the voltage immediately before a third change in slope. The second change in slope being caused by the disabling of the discharge circuit.

It is noted that in embodiments, the health of the reserve capacitor can be determined based on more than one relationship between the computed measurements. Thus the determination of the health of the reserve capacitor is not limited to a one-to-one relationship between the computed values and an expected capacitance or equivalent series resistor value. For example, the health of the reserve capacitor can be determined by a complex relationship between the measured values, expected values, with various possible ranges corresponding to the manufacturing type, tolerances, operating ranges of the reserve capacitor, or the like.

In embodiments, the computation is at the system level, external to the circuit. At the system level, analysis of the capacitor's health can be based on a relationship between the capacitance value and the equivalent series resistor of the capacitor. In an exemplary circuit, having a reserve capacitor of 2.2 microfarads with an accuracy of ±30%, a microcontroller or processor at the system level can determine that the value of the reserve capacitor is outside of the expected range and set a flag accordingly.

In embodiments, the various parameters are measured during a single discharge routine to minimize the total power dissipation used to compute the capacitance and equivalent series resistor (ESR) values. These and other details are discussed in greater detail below.

FIG.1aillustrates a circuit model100of an embodiment reserve capacitor102, which in addition to the model capacitor104, includes an equivalent series resistor106. In embodiments, the reserve capacitor102is an auxiliary source used to power a vehicle's supplemental restraint system as an alternative power source to the primary vehicle battery.

It is desirable to periodically monitor the reserve capacitor102for proper operation. At set intervals, the equivalent series resistor and capacitance values of reserve capacitor102are measured during a discharge routine of reserve capacitor102through the discharge circuit108. Discharge circuit108provides a controllable (e.g., serial peripheral interface (SPI), etc.), low-ohmic path that allows reserve capacitor102to discharge during a discharge routine of reserve capacitor102.

A charge circuit120is coupled to reserve capacitor102. The charge circuit120provides a controllable (e.g., serial peripheral interface (SPI), etc.), low-ohmic path that, when enabled, allows reserve capacitor102to charge during a charge routine of reserve capacitor102.

Discharge circuit108includes a discharge switch no. A discharge resistor112is coupled to discharge circuit108. When discharge switch no is activated, for example, during a discharge routine, current is dissipated through discharge resistor112. The arrangement of components shown inFIG.1amay (or may not) be arranged as shown. Further, discharge circuit108may include additional or fewer components as shown with the purpose of having a discharge path being provided for reserve capacitor102when discharge switch no is in the closed position.

In embodiments, discharge switch no is a metal-oxide-semiconductor field-effect transistor (MOSFET). Optionally, discharge circuit108may include a diode in series between discharge switch no and discharge resistor112. Although, as shown, discharge circuit108is arranged between discharge resistor112and a reference voltage, in embodiments, the discharge resistor112is coupled in series between discharge switch no and a reference voltage.

In embodiments, discharge resistor112is located away from the circuit model100to minimize power dissipation and reduce circuit temperature during a discharge phase. In embodiments, discharge resistor112is advantageously utilized as a sensing resistor during the discharge phase of the circuit.

FIG.1billustrates a timing diagram150for the VERvoltage at the terminal of the reserve capacitor102during a discharge routine. Before time t1, discharge circuit108is disabled, and the VERvoltage corresponds to the steady-state voltage value VSTART.

At time t1, discharge circuit108is enabled through discharge switch110. In response, reserve capacitor102is immediately discharged to a voltage value VSTART_t1+. The sharp drop in voltage at time t1generally corresponds to the non-zero equivalent series resistor value of reserve capacitor102.

From time t1until time t2, while discharge circuit108remains enabled, reserve capacitor102is constantly discharged until it reaches a voltage value VSTOP_t2−.

At time t2discharge circuit108is disabled, and charge circuit120is enabled. In response, reserve capacitor102is immediately charged to an initial voltage value VSTOP. Gradually thereafter, reserve capacitor102is recharged to the steady-state voltage value VEND.

In embodiments, the voltage of the fully charged reserve capacitor102is between 20 and 33 Volts (V). In such an embodiment, the voltage drop between time t1and t2is approximately 600 millivolts (mV).

FIG.2illustrates a prior art circuit200used to measure the capacitance of reserve capacitor102. Circuit200includes an analog-to-digital converter (ADC)202, discharge circuit108, R1resistor204a, and R2resistor204b.

The arrangement of R1and R2resistors204a-bprovides a resistor divider at the input of analog-to-digital converter202. At time t1and t2the ratioed VERvoltage is converted to a digital value using analog-to-digital converter202. The capacitance value (CER) of reserve capacitor102can, thus, be computed using the equation:

CER=2×I×(t2-t1)VSTART⁢_⁢t⁢1++VEND-2×VSTOP,
where I is the current value discharged through discharge circuit108when enabled, t2−t1is the time during which discharge circuit108is enabled, VSTART_t1+is the voltage at node VERat time t1after discharge circuit108is enabled, VSTOPis the voltage at node VERat time t2after discharge circuit108is disabled and charge circuit120is enabled, and VENDis the voltage at node VERafter charge circuit120is enabled and reserve capacitor120is recharged.

In circuit200, the voltage at node VERis measured when charge circuit120and discharge circuit108are disabled (i.e., no current is flowing through reserve capacitor102) to obtain an accurate capacitance value measurement and avoid error contributions from equivalent series resistor106. Thus, the charge and discharge timing must be carefully synchronized—challenging to do, and reserve capacitor102selectively chosen based on its electrical parameters to maximize differential voltage at times t2and t1and improve measurement accuracy.

The amount of current discharged through discharge circuit108must be well defined to compute the capacitance value (CER). Further, additional circuit components are required to accurately measure the current, which negatively affects the overall circuit footprint and increases energy consumption—in the form of wasted current through discharge circuit108. At a minimum, a sequence of charge and discharge of reserve capacitor102is required for capacitance computation. For all these reasons, it is challenging to make an accurate measurement of capacitance using circuit200.

FIG.3illustrates a prior art circuit300used to measure the equivalent series resistor106of reserve capacitor102. Circuit300includes multiple transistors and resistors, which are selectively enabled and disabled to measure equivalent series resistor106. By enabling and disabling various switches (e.g., transistors) in various sequences and sampling the output of transistors S1, S2, and S3, the value (RESR) of the equivalent series resistor106can be computed using the equation:

RESR=((VS⁢2-VS⁢1)-(VS⁢2-VS⁢3))3×I,
where I is the current value discharged via discharge circuit108when enabled, VS1, is the voltage sampled at the S1 transistor, VS2is the voltage sampled at the S2 transistor, and Vs3is the voltage sampled at the S3 transistor. The sample voltages (i.e., VS1, VS2, and VS3) are digitized through an analog-to-digital converter (not shown) coupled to the output of the sample/hold circuit.

Disadvantageously, circuit300requires at least a capacitor and switch for each sample that is to be held, which can significantly increase the footprint of circuit300. Further, leakages at various switches can significantly undermine voltage drop measurement accuracy. Finally, errors inherent in the circuit used to measure the voltage across discharge resistor112can add additional errors in the computation of the value of equivalent series resistor106.

FIG.4aillustrates an embodiment circuit400used to measure the capacitance and the equivalent series resistor values of reserve capacitor102. The accurate measurement of these values allows circuit400to monitor the health of reserve capacitor102. Circuit400simultaneously measures the capacitance and equivalent series resistor values of reserve capacitor102by enabling discharge circuit108, measuring the voltage drop at node VER, and measuring the discharge current (IDCH) flowing across the discharge resistor112.

In embodiments, discharge resistor112is an existing resistor of an integrated circuit of an airbag system coupled to the reserve capacitor. In embodiments, discharge resistor112is sufficiently separated from circuit400to minimize an increase in temperature of circuit400while power is being dissipated through discharge resistor112.

FIG.4billustrates an embodiment timing diagram450for the VERvoltage during a discharge routine of reserve capacitor102. Referring to circuit400and the timing diagram450, the relationship between the capacitance value (CER) of reserve capacitor102, the current (I(t)) flowing through discharge resistor112during a discharge routine (i.e., discharge circuit108enabled), and the voltage drop (VSTART−VSTOP)) from time t1(i.e., discharge circuit enabled) until time t2(i.e., discharge circuit108disabled) follows the equation:

CER=∫t1t2⁢i⁡(t)⁢dtVSTART-VSTOP.
Reformulating the equation to replace the current I(t) flowing through discharge resistor112during the discharge routine (using Ohm's law), we have the following equation:

CER=∫t1t2[VER(t)-VDCH(t)]⁢dtVSTART-VSTOP×1RDCH,
where RDCHis the resistance value of discharge resistor112.

Because the resistance value (RDCH) of discharge resistor112is known, the values of VSTART−VSTOPand ∫t1t2[VER(t)−VDCH(t)]dt allow the computation of the capacitance value (CER) value of reserve capacitor102. Because the discharge current (IDCH) is much larger than any leakage current at reserve capacitor102, the leakage value can be excluded from the equation above with minimal errors—worst-case contributing error being less than 1%.

The equivalent series resistor value (ESR) of reserve capacitor102follows the equation:

ESR=(VSTART-VSTART⁢_⁢t⁢1+)+(VSTOP-VSTOP⁢_⁢t⁢2-)I⁡(t1)+I⁡(t2).
Reformulating the equation to replace the current flowing through discharge resistor112during the discharge routine (using Ohm's law), we have the following equation:

ESR=RDCH×ΔVSTART+ΔVSTOP[VER(t1)-VDCH(t1)]+[VER(t2)-VDCH(t2)],
where ΔVSTARTis equal to VSTART−VSTART_t1+, and where ΔVSTOPis equal to VSTOP−VSTOP_t2−.

As shown inFIG.4b, immediately after discharge circuit108is enabled at time t1, the VERvoltage drops from VSTARTto VSTART_t1+. The sharp drop is generally due to the non-zero equivalent series resistor value of reserve capacitor102. The value of VSTARTcan be measured at any time before discharge circuit108is disabled. For example, the value of VSTARTcan be measured at time t1A, which is about 64 microseconds before time t1. The value of VSTART_t1+can be measured after the discharge circuit108is enabled.

Optimally, the value of VSTART_t1+is measured at time t1. However, the measurement of VSTART_t1+is likely to be completed between time t1and time t1Bgiven the constraints of measurements systems. For example, a circuit that utilizes a sigma-delta type amplifier would measure the value of VSTART_t1+between time t1and time t1B—a period extending, for example, about 64 microseconds. It should be noted that the voltage measured towards time t1Bis slightly lower than the value of VSTART_t1+. However, by setting t1bto a time close to time t1, the voltage difference becomes negligible—particularly because the discharge at the reserve capacitor102is with a constant current sink. The resulting measurement of VSTART_t1+is, thus, an average value of the voltage between time Land time t1B.

Further, as the discharge of the capacitor corresponds to a constant current, the discharge waveform being linear. It is preferred to take the measurement at time t1due to the time used by the sigma-delta to collect a sample—the measurement falling between time t1and t1Bwith the sigma-delta, which may cause a lower voltage than ideal to be measured. Similarly, it is preferred to take a measurement at time t2due to time used by the sigma-delta to acquire a sample—the measurement falling between time t2aand time t2with the sigma-delta, which may cause a higher voltage higher than ideal to be measured. However, the average between the two measurements by the sigma-delta provides an identical measurement to the ideal condition due to consistencies with the measurement time by the sigma-delta and the linear form of the discharge waveform.

It is noted that the approximate 64 microseconds associated with the timing of the measurements corresponds to an operation of an exemplary sigma-delta type amplifier and is not limiting.

In an embodiment, the various components of circuit400are synchronized using a clock signal. Thus, the various voltage measurements can be performed with sufficient accuracy to time the measurement of values VSTARTand VSTART_t1+, for example, 64 microseconds before and after the enabling of discharge circuit108.

In another embodiment, the difference between VSTARTand VSTART_t1+is measured by monitoring the slope (change in voltage at VERnode in reference to time). As shown, the slope at time t1(i.e., sharp drop) is different from the slope between times t1and t2(i.e., linear, gradual drop). By continuously monitoring VERover time, the difference between VSTARTand VSTART_t1+is set to the value before the occurrence of the change in slope.

Similarly and as shown inFIG.4b, immediately after the discharge circuit108is disabled at time t2, the VERvoltage jumps from VSTOPt_t2−to VSTOP. As before, the sharp change in voltage is generally due to the non-zero equivalent series resistor value of reserve capacitor102. The value of VSTOPcan be measured after discharge circuit108is disabled, and before charge circuit120is enabled. For example, the value of VSTOPcan be measured at time t2B, which is about 64 microseconds after time t2. The value of VSTOP_t2−is measured before discharge circuit108is disabled. For example, the value of VSTOP_t2−can be measured at time t2A, which is about 64 microseconds before time t2. It should be noted that the voltage measured at time t2Ais slightly higher than the value of VSTOP_t2−. However, by setting t2Ato a time close to time t1, the difference in voltage becomes negligible.

In an embodiment, the various components of circuit400are synchronized using a clock signal. Thus, the various voltage measurements can be performed with sufficient accuracy to time the measurement of values VSTOP_t2−and VSTOP, for example, in reference to the time corresponding to the disabling of discharge circuit108.

In another embodiment, the difference between VSTOP_t2−and VSTOPis measured by monitoring the slope (change in voltage at VERnode in reference to time). As shown, the slope between times t1and t2(i.e., linear, gradual drop), the slope at time t2(i.e., sharp jump), and the slope after time t2(i.e., steady) are different in value. By continuously monitoring VERover time, the difference between VSTOP_t2−and VSTOPis set to the boundary values corresponding to the change from time t1to t2and after time t2.

Because the resistance value (RDCH) of the discharge resistor112is known, the values of ΔVSTART, ΔVSTOP, VER(t1)−VDCH(t1), and VER(t2)−VDCH(t2) allow the computation of the equivalent series resistor (ESR) value of reserve capacitor102.

In embodiments, the capacitance value of the reserve capacitor102is between 2.2 milliFarads (mF) and 52 mF, the equivalent series resistor value of reserve capacitor102is between 0.2 Ohms and 0.6 Ohms, the resistor value of discharge resistor112is approximately 20 Ohms, the voltage at node VERis between 20 and 33 volts, and the discharge current (IDCH) flowing through discharge resistor112during a discharge routine is between 1 amp to 1.65 amps—in comparison, the leakage at the reserve capacitor102is minimal (e.g., 10 mA). The drop in VERvoltage (VSTART_t1+−VSTOP_t2−) from time t1to time t2is approximately 0.5 Volts in an embodiment.

FIG.5is a flowchart of an embodiment method 500 for measuring the values for the various parameters: VSTART−VSTOP, ∫t1t2[VER(t)−VDCH(t)]dt, ΔVSTART, ΔvSTOP, VER(t1)−VDCH(t1), and VER(t2)−VDCH(t2). These parameter values, once measured, can be used to compute the capacitance (CER) and the equivalent series resistor (ESR) values of reserve capacitor102.

At step502and before time t1, the steady-state voltage value VSTARTat node VERis measured. At step504, discharge circuit108is enabled, and reserve capacitor102begins discharging. As soon as discharge circuit108is enabled at time t1, the voltage value VSTART_t1+at node VERis measured. The difference between the voltages measured at node VERat step502(e.g., VSTART) and at step504(e.g., VSTART_t1+) provides the value for the parameter ΔVSTART.

At step506at time t1, the voltages at nodes VERand VDCHare measured to compute the value corresponding to the parameter VER(t1)−VDCH(t1).

At step508, the integration ∫t1t2[VER(t)−VDCH(t)]dt begins at time t1.

At step510, time t2is determined corresponding to a voltage drop at node VERbeing greater than or equal to a threshold voltage (e.g., 1.2 volts). In embodiments, the voltage at node VERis continuously monitored and subtracted from the steady-state voltage value VSTARTuntil the threshold voltage is reached.

At step512and at time t2, the voltages at nodes VERand VDCHare again measured to compute the value corresponding to the parameter VER(t2)−VDCH(t2). At step514, the integration ∫t1t2[VER(t)−VDCH(t)]dt ends at time t2.

At step516and at time t2, the voltage value VSTOP_t2−at node VERis measured. At step518, discharge circuit108is disabled, and charge circuit120is enabled. As soon as charge circuit120is enabled, the voltage value VSTOPat node VERis measured. The difference between the voltages measured at node VERat step518(e.g., VSTOP) and at step516(e.g., VSTOP_t2−) provides the value for the parameter ΔVSTOP.

At step520, the difference in voltage measured at node VERat step518(e.g., VSTOP) and at step502(e.g., VSTART) provides the value for the parameter VSTART−VSTOP. At step522, the measurement sequence ends.

In embodiments, if the computed values for the capacitance (CER) and the equivalent series resistor (ESR) of reserve capacitor102falls outside a corresponding threshold value, an error signal is generated from a microcontroller circuit of the supplemental restraint system (SRS) to the vehicle computer. The error signal alerts the driver that the reserve capacitor of the supplemental restraint system (SRS) is outside of the normal operating range and that the system requires service.

It is noted that the order of steps shown inFIG.5is not absolutely required, so in principle, the various steps may be performed out of the illustrated order. Also, certain steps may be skipped, different steps may be added or substituted, or selected steps or groups of steps may be performed in a separate application.

FIG.6illustrates a diagram of an embodiment circuit600used to measure the values for the various parameters: VSTART−VSTOP, ∫t1t2[VER(t)−VDCH(t)]dt, ΔVSTART, ΔvSTOP, VER(t1)−VDCH(t1), and VER(t2)−VDCH(t2) to compute the capacitance (CER) and the equivalent series resistor (ESR) values of reserve capacitor102.

As shown, circuit600, in addition to the components previously described with respect to circuit400, includes first circuitry602and second circuitry610. First circuitry602includes a sigma-delta (Σ-Δ) analog-to-digital converter604, a controller, and a controllable current sink608. The input of the first circuitry602is coupled to the VERnode, and the output of the first circuitry602is the digital signal BSOUT1.

Second circuitry610includes an amplifier612, a differential sigma-delta (Σ-Δ) analog-to-digital converter614, and a digital integrator616. The input of the second circuitry610is coupled to the VERand VDCHnodes at the terminals of discharge resistor112(RDCH). The output of the second circuitry610is the digital signal BSOUT2.

Parameters VSTART−VSTOP, and ΔVSTART, and ΔVSTOPare computed using the first circuitry602, which is optimized to measure voltage variations at the VERnode. The digital output signal (BSOUT1) is filtered and computed by a logic circuit (not shown) coupled to the output of the first circuitry602.

Parameters ∫t1t2[VER(t)−VDCH(t)]dt, VER(t1)−VDCH(t1) and VER(t2)−VDCH(t2) are computed using the second circuitry610. The digital output signal (BSOUT2) is filtered and computed by a logic circuit (not shown) coupled to the output of the second circuitry610.

Once the value for parameters VSTART−VSTOP, ΔVSTART, ΔvSTOP, ∫t1t2[VER(t)−VDCH(t)]dt, VER(t1)−VDCH(t1), and VER(t2)−VDCH(t2) are computed, a logic circuit or a processor computes the capacitance (CER) and the equivalent series resistor (ESR) values of reserve capacitor102using the equations:

CER=∫t1t2[VER(t)-VDCH(t)]⁢dtVSTART-VSTOP×1RDCH,and⁢ESR=RDCH×ΔVSTART+ΔVSTOP[VER(t1)-VDCH(t1)]+[VER(t2)-VDCH(t2)].

Embodiments of this disclosure advantageously limit the computation of the capacitance (CER) and the equivalent series resistor (ESR) values to a single discharge routine. As such, the amount of dissipation to make the various measurements, in contrast to the prior art, is advantageously minimized.

In embodiments, circuit600is embedded in the supplemental restraint system (SRS) and is self-managed. As soon as a capacitive measurement is requested, the embodiments of this disclosure provide a limited discharge voltage at the VERnode with a fast execution time (e.g., single discharge phase).

It is noted that the various measurements are a function of the discharge current (IDCH) sunk through discharge circuit108. Discharge switch no operates in the linear region in a low-power dissipation mode. The use of discharge circuit108to measure the various parameters, advantageously, is a repurposing of existing components within the supplemental restraint system (SRS). As such, the number of components to measure the various parameters is minimized.

Unless otherwise specified, when reference is made to two elements electrically connected together, this means that the elements are directly connected with no intermediate element other than conductors. When reference is made to two elements electrically coupled together, this means that the two elements may be directly coupled (connected) or coupled via one or a plurality of other elements.

Although the description has been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. The same elements are designated with the same reference numbers in the various figures. Moreover, the scope of the disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from this disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

The specification and drawings are, accordingly, to be regarded simply as an illustration of the disclosure as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present disclosure.