Patent ID: 12249911

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

FIG.1Ais an example diagram of an apparatus that includes flying capacitor startup circuit for multi-level voltage converters in one embodiment. An apparatus100is shown inFIG.1. Apparatus100can be, for example, a semiconductor device implementing a voltage regulator that receives an input voltage Vin and output an output voltage Vout. Apparatus100can include a circuit102and a multi-level voltage converter104, where multi-level voltage converter104can be a three-level buck converter. Multi-level voltage converter104can include four transistors Q1, Q2, Q3, Q4, an inductor L, and a flying capacitor Cfly. Transistors Q1, Q4can be referred to as the outer transistors, and transistors Q2, Q3can be referred to as inner transistors.

In an embodiment shown inFIG.1D, circuit102can also be implemented for an apparatus150that includes a multi-level boost converter, such as a three-level boost converter152. In an embodiment shown inFIG.1E, more than one circuit102can be implemented for an apparatus160that includes a four-level boost converter. In an embodiment shown inFIG.1F, more than one circuit102can also be implemented for an apparatus170that includes a N-level buck converter. In an embodiment shown inFIG.1G, more than one circuit102can also be implemented for an apparatus180that includes a N-level boost converter.

Transistors Q1, Q2, Q3, Q4can be switched at different timings to generate a desired voltage level and output the desired voltage level as output voltage Vout. In an aspect, a first complementary signal including signals S1, S4can drive outer transistors Q1, Q4with a duty cycle D=Vout/Vin. A second complementary signal including signals S2, S3having equal duty cycle can drive inner transistors Q2, Q3, and the second complementary signal can be phase-shifted from the first complementary signal by 180 degrees. The timing and duty cycle of the first and second complementary signals can maintain a flying capacitor voltage (e.g., a voltage on flying capacitor Cfly) at half the input voltage Vin, such as Vin/2. By maintaining the flying capacitor voltage at Vin/2, voltage at a switch node VLX between inner transistors Q2, Q3can alternate between Vin, Vin/2, and ground (GND).

Circuit102can be a startup circuit configured to initialize and maintain the flying capacitor voltage at a target voltage, where in the case of a three-level voltage converter, the target voltage can be Vin/2. The target voltage being maintain by circuit102can be an intermediate voltage that has a voltage level between Vin and ground. In one or more embodiments, more than one copy of circuit102can be implemented for N-level voltage converters, and each copy of circuit102can maintain an individual flying capacitor at a respective target voltage. As shown by the embodiment inFIG.1E, one copy of circuit102can be implemented to maintain a first flying capacitor Cfly1at an intermediate voltage Vin/3, and another copy of circuit102can be implemented to maintain a second flying capacitor Cfly2at another intermediate voltage 2 Vin/3.

Circuit102can include one or more circuits or circuit blocks configured to perform different tasks or functions of circuit102. Referring to an embodiment inFIG.1B, apparatus100can be a part of a system110that includes apparatus100, a controller120and a gate driver122. Controller120can be configured to provide one or more pulse width modulation (PWM) signals to gate driver122. Gate driver122can be configured to drive transistors Q1, Q2, Q3, Q4by generating and providing the first and second complementary signals that include signals S1, S2, S3, S4. Generation of the signals S1, S2, S3, S4can be based on the PWM signals provided by controller120. In the embodiment shown inFIG.1B, circuit102can be a standalone circuit or hardware component separated from controller120and gate driver122. In another embodiment shown inFIG.1C, circuit102can be a part of gate driver122.

In an aspect, If the flying capacitor voltage maintained at, or approximately, Vin/2, then the voltage across any one of transistors Q1, Q2, Q3, Q4can be less than Vin/2. Hence, one of transistors Q1, Q2, Q3, Q4can be selected with maximum operating voltage near Vin/2. When controller120is shut down, multi-level voltage converter104is idle and not outputting power, and the flying capacitor voltage is not being maintained at Vin/2. Hence, to startup multi-level voltage converter104from an idle state, the flying capacitor voltage needs to reach Vin/2 (either from a charged or discharged state) relatively quickly to avoid overvoltage on transistors Q1, Q2, Q3, Q4.

Circuit102can be implemented as a startup circuit to initialize and maintain the flying capacitor voltage at Vin/2 when controller120is shut down. By maintaining the flying capacitor voltage at Vin/2 when controller120is shut down (and when multi-level voltage converter104is idle), overvoltage on transistors Q1, Q2, Q3, Q4can be prevented for any allowed ramp rate on Vin at startup. Further, circuit102may require relatively low current to operate since circuit102is enabled when multi-level voltage converter104is idle and not outputting power. Further, when circuit102is enabled, inner transistors Q2, Q3can be turned off to disconnect Vout, and current through the body diodes of transistors Q2, Q3to Vout should be avoided. Furthermore, circuit102is implemented as a standalone circuit separated from controller120such that circuit102can be enabled when controller120is shut down.

FIG.2is an example diagram of a flying capacitor startup circuit for multi-level voltage converters in one embodiment. In an embodiment shown inFIG.2, circuit102can include a plurality of switched current sources i_chrg, i_dis, and Δi. Current source i_chrg can be switched by a switch labeled as CHRG, current source i_dis can be switched by a switch labeled as DIS, and current source Δi can be switched by switches labeled as UP and DOWN.

Circuit102can perform a pulse mode algorithm to control the flying capacitor voltage across flying capacitor Cfly. If the flying capacitor voltage is determined to be low (the determination will be described below), then switch CHRG can be enabled and current i_chrg can be applied at nodes Vc+ and Vc− to increase the flying capacitor voltage across Cfly until it reaches a target of Vin/2. Node Vc+can be connected to a positive terminal of Cfly and node Vc− can be connected to a negative terminal of Cfly. If the flying capacitor voltage is determined to be high (the determination will be described below), then switch DIS can be enabled and current i_dis can be applied at nodes Vc+ and Vc− to decrease the flying capacitor voltage across Cfly until it reaches the target of Vin/2. In response to the flying capacitor voltage reaching Vin/2, or reaching a value close to Vin/2, circuit102automatically goes into a low current sleep mode to preserve power.

To avoid conducting current through body diodes of transistors Q1, Q2, Q3, Q4, current source Δi can be switched to control a common-mode voltage of flying capacitor Cfly based on Vout. If Vout is less than Vin/2, then switch DOWN can be enabled and current Δi can be applied to node Vc− to pull Vc−, or the negative terminal of Cfly, down to GND while Vc+, or the positive terminal of Cfly, is charged or discharged to Vin/2. If Vout is greater than Vin/2, switch UP can be enabled and Δi can be applied to node Vc+ to pull Vc+, or the positive terminal of Cfly, to Vin while node Vc−, or the negative terminal of Cfly, is pulled up or down to Vin/2.

FIG.3is an example diagram of a circuit300for controlling a common-mode voltage of a flying capacitor in a multi-level voltage converter in one embodiment. Circuit300can be a circuit block in circuit102shown inFIG.1AtoFIG.2. Circuit300can include resistors R1, R2, R3, comparators302,304, OR gate306, and AND gates308,310. Circuit300can receive input voltage Vin. Resistor R1can scale input voltage Vin to generate a first scaled voltage (Vin/2)+ΔVo, where ΔVo is a voltage offset. Resistor R2can further scale the first scaled voltage (Vin/2)+ΔVo to a second scaled voltage (Vin/2)−ΔVo.

A non-inverting input of comparator302can receive output voltage Vout, and an inverting input of comparator302can receive the first scaled voltage (Vin/2)+ΔVo. Comparator302can compare Vout with the first scaled voltage (Vin/2)+ΔVo and if Vout reaches the first scaled voltage (Vin/2)+ΔVo, then signal UP can be set to HIGH to enable switch UP of circuit102shown inFIG.2. A non-inverting input of comparator304can receive the second scaled (Vin/2)−ΔVo and an inverting input of comparator304can receive output voltage Vout. Comparator304can compare Vout with the second scaled voltage (Vin/2)−ΔVo and if Vout reaches the second scaled voltage (Vin/2)−ΔVo, then signal DOWN can be set to HIGH to enable switch DOWN of circuit102shown inFIG.2.

If output voltage Vout is between the first scaled voltage (Vin/2)+ΔVo and the second scaled voltage (Vin/2)−ΔVo, then neither UP or DOWN signal is set HIGH and the common-mode voltage will depend on a mismatch of pull-up and pull-down currents. Further, when circuit102is disabled, the signals CHRG and DIS can be zero, hence OR gate306can output a zero. Since the output of OR gate306is zero, AND gates308,310will also output zeroes and the signals UP and DOWN will be set to LOW regardless of the outputs of comparators302,304.

FIG.4is an example diagram of a circuit400for controlling a flying capacitor voltage in a hysteretic mode in one embodiment. Circuit400can be a circuit block in circuit102(shown inFIG.1AtoFIG.2) that can be implemented when circuit102is in a hysteretic mode, where the hysteretic mode is when sleep mode of circuit102is disabled. Circuit400can include a resistors R4, R5, R6, R7and comparators402,404,406. A flying capacitor voltage Vcfly can be measured from nodes Vc+ and Vc− (seeFIG.2). Circuit400can receive Vin and resistor R4can scale Vin to the first scaled voltage (Vin/2)+ΔVo. Resistor R5can further scale the first scaled voltage (Vin/2)+ΔVo to Vin/2. Resistor R6can further scale Vin/2 to the second scaled voltage (Vin/2)−ΔVo. The non-inverting inputs of comparators402,404,406can receive Vcfly. Inverting input of comparator402can receive the first scaled voltage (Vin/2)+ΔVo. Inverting input of comparator404can receive Vin/2. Inverting input of comparator406can receive the second scaled voltage (Vin/2)−ΔVo. Output of comparator402can be connected to the switch DIS shown inFIG.2and output of comparator406can be connected to the switch CHRG shown inFIG.2. In one embodiment, output of comparator404can cause circuit102(seeFIG.1AtoFIG.2) to be enabled or disabled. By way of example, if Vcfly is equivalent to Vin/2, or is within a predetermined tolerance percentage from Vin/2, then the output from comparator404can disable circuit102and put circuit102into a low current sleep mode.

Circuit400can perform a pulse mode algorithm to control the flying capacitor voltage Vcfly by determining whether to charge or discharge flying capacitor Cfly. In one embodiment, Vcfly can be determined as being low when Vcfly reaches the second scaled voltage (Vin/2)−ΔVo. If Vcfly reaches the second scaled voltage (Vin/2)−ΔVo, comparator406can output a voltage to set CHRG to HIGH such that switch CHRG can be enabled. When switch CHRG is enabled, flying capacitor Cfly can be charged by current source i_chrg (seeFIG.2). In one embodiment, Vcfly can be determined as being high when Vcfly reaches the first scaled voltage (Vin/2)+ΔVo. If Vcfly reaches the first scaled voltage (Vin/2)+ΔVo, comparator402can output a voltage to set DIS to HIGH such that switch DIS can be enabled. When switch DIS is enabled, flying capacitor Cfly can be discharged via current source i_dis (seeFIG.2). Circuit400can continue to monitor and measure Vcfly from nodes Vc+ and Vc− as flying capacitor Cfly is being charged or discharged. In response to Vcfly reaching Vin/2, or reaching a value close to Vin/2, the output from comparator404can trigger a monitor mode where circuit102continues to monitor Vcfly until Vcfly reaches the first scaled voltage (Vin/2)+ΔVo or the second scaled voltage (Vin/2)−ΔVo.

FIG.5is an example state diagram500showing operations of a flying capacitor startup circuit in a hysteretic mode in one embodiment. State diagram500can include states S0, S1, S2, S3, and S4. State S0can be an initial state where circuit102(seeFIG.1AtoFIG.2) starts up or is being reset. State S0can transition to state S1. At state S1, circuit102(e.g., or circuit400shown inFIG.4) can compare flying capacitor voltage Vcfly with Vin/2. In response to Vcfly being less than Vin/2, state S1can transition to state S2. In response to Vcfly being greater than Vin/2, state S1can transition to state S3.

At state S2, circuit102can charge flying capacitor Cfly (seeFIG.1AtoFIG.2). Note that Vcfly being less than Vin/2 can indicate that flying capacitor Cfly needs to be charged to increase Vcfly to Vin/2. Referring toFIG.2, Cfly can be charged by enabling switch CHRG to switch in current source i_chrg. In response to Vcfly being increased to Vin/2, state S2can transition to state S4. At state S3, circuit102can discharge flying capacitor Cfly. Note that Vcfly being greater than Vin/2 can indicate that flying capacitor Cfly needs to be discharged to decrease Vcfly to Vin/2. Referring toFIG.2, Cfly can be discharged by enabling switch DIS to switch in current source i_dis. In response to Vcfly being decreased to Vin/2, state S3can transition to state S4.

At state S4, circuit102can continue to monitor Vcfly and determine whether to continuing charging or discharging Cfly. At state S4, if Vcfly decreases to the second scaled voltage (Vin/2)−ΔVo, then state S4can transition back to state S2to charge Cfly. At state S4, if Vcfly increases to the first scaled voltage (Vin/2)+ΔVo, then state S4can transition back to state S3to discharge Cfly. At state S4CHRG and DIS are both set low, and the charging current (i_chrg) and the discharging current (i_dis) are both off.

FIG.6Ais an example diagram showing a flying capacitor voltage during a hysteretic mode of a flying capacitor startup circuit for multi-level voltage converters in one embodiment. A waveform600is shown inFIG.6Aand waveform600corresponds to the hysteretic mode implementation of state diagram500inFIG.5. Waveform600corresponds to scenarios where the flying capacitor Cfly is fully discharged (e.g., Vcfly is zero or close to zero) during a startup of circuit102(seeFIG.1AtoFIG.2) at a time t0. Since flying capacitor Cfly is fully discharged at time t0, circuit102can switch current source i_chrg to charge flying capacitor Cfly. Flying capacitor Cfly can be charged until Vcfly reaches Vin/2 (or close to Vin/2).

In response to Vcfly reaching Vin/2 at time t1, circuit102can continue to monitor Vcfly until Vcfly decreases to the second scaled voltage (Vin/2)−ΔVo. In an aspect, flying capacitor voltage Vcfly can vary, such as increase or decrease due to various variations (e.g., temperature, environmental, leakage current). In waveform600, in response to Vcfly decreasing to the second scaled voltage (Vin/2)−ΔVo at time t2, circuit102can charge Cfly until Vcfly reaches Vin/2 at t3. In response to Vcfly reaching Vin/s at time t3, circuit102can continue to monitor Vcfly until Vcfly decreases to the second scaled voltage (Vin/2)−ΔVo again.

FIG.6Bis another example diagram showing a flying capacitor voltage during a hysteretic mode of a flying capacitor startup circuit for multi-level voltage converters in one embodiment. A waveform610is shown inFIG.6Band waveform610corresponds to the hysteretic mode implementation of state diagram500inFIG.5. Waveform610corresponds to scenarios where the flying capacitor Cfly is fully charged during a startup of circuit102(seeFIG.1AtoFIG.2) at a time t0. Since flying capacitor Cfly is fully charged at time t0, circuit102can switch current source i_dis to discharge flying capacitor Cfly. Flying capacitor Cfly can be discharged until Vcfly reaches Vin/2 (or close to Vin/2).

In response to Vcfly reaching Vin/2 at time t1, circuit102can continue to monitor Vcfly until Vcfly increases to the first scaled voltage (Vin/2)+ΔVo. In an aspect, flying capacitor Cfly can vary, such as increase or decrease due to various variations (e.g., temperature, environmental, leakage current). In waveform610, in response to Vcfly increasing to the first scaled voltage (Vin/2)+ΔVo at time t2, circuit102can discharge Cfly until Vcfly reaches Vin/2 at t3. In response to Vcfly reaching Vin/s at time t3, circuit102can continue to monitor Vcfly until Vcfly increases to the first scaled voltage (Vin/2)+ΔVo again. The voltage offset Vo can impose voltage window that varies between (Vin/2)−Vo and (Vin/2)+Vo to bound a value of Vcfly.

In one embodiment, the voltage offset ΔVo can be programmable and can vary with an amount of tolerable leakage voltage ripple. If relatively large voltage ripple is tolerable, then ΔVo can be programmed to be higher. If relatively small voltage ripple is tolerable, then Vo can be programmed to be lower. Setting ΔVo higher when more voltage ripple is tolerable can preserve power since circuit102can be enabled less frequently.

FIG.7is an example diagram of a circuit700for controlling a flying capacitor voltage in a constant-off time mode in one embodiment. Circuit700can be a circuit block in circuit102(shown inFIG.1AtoFIG.2) that can be implemented when circuit102is in a constant-off time mode, where the constant-off time mode is when sleep mode of circuit102is enabled. In one embodiment, circuit700can be a part of circuit400shown inFIG.4. In one embodiment, circuit102can include a register configured to store a register bit indicating whether circuit400shall operate in hysteretic mode or constant-off time mode (e.g., constant-off time mode of circuit400is implemented by circuit700). The modes can be selected by changing the register bit such that, for example, if the register bit is set to ‘1’ then the constant off-time mode is active or enabled, and if the register bit is set to ‘0’ then the hysteretic mode is active or enabled.

In one embodiment, when the register bit is set to ‘1’ to enable constant-off time mode, some components such as resistors R5, R6and comparators402,406of circuit400can be disconnected and the remaining connected components can implement circuit700. As shown inFIG.7, circuit700can include resistors R4, R7and comparator404. The non-inverting input of comparator404can receive Vcfly and the inverting input of comparator404can receive Vin/2. Output of comparator output of comparator404can cause circuit102(seeFIG.1AtoFIG.2) to enter or exit sleep mode. By way of example, if Vcfly is equivalent to Vin/2, or is within a predetermined tolerance percentage from Vin/2, then the output from comparator404can put circuit102into a low current sleep mode where all components are shut down except for a timer in circuit102. Output of comparator404can also be connected to a timer to trigger a start of the timer, where the timer can be programmed to a predetermined amount of time.

Circuit700can perform a pulse mode algorithm to control the flying capacitor voltage Vcfly by determining whether to charge or discharge flying capacitor Cfly. In one embodiment, Vcfly can be determined as being low when Vcfly falls below Vin/2 for the predetermined amount of time, and can be determined as being high when Vcfly is above Vin/2 for the predetermined amount of time. Circuit700can monitor and measure Vcfly from nodes Vc+ and Vc− as flying capacitor Cfly is being charged or discharged. In response to Vcfly reaching Vin/2, or reaching a value close to Vin/2, the output from comparator404can cause circuit102to go into a low current sleep mode to preserve power and to start the timer in circuit102. When the timer expires, circuit700can measure Vcfly again to determine whether Cfly needs to be charged or discharged.

FIG.8is an example state diagram800showing operations of a flying capacitor startup circuit in a constant-off time mode in one embodiment. State diagram800can include states S0, S1, S2, S3, and S4. State S0can be an initial state where circuit102(seeFIG.1AtoFIG.2) starts up or is being reset. State S0can transition to state S1. At state S1, circuit102(e.g., or circuit400shown inFIG.4) can compare flying capacitor voltage Vcfly with Vin/2. In response to Vcfly being less than Vin/2, state S1can transition to state S2. In response to Vcfly being greater than Vin/2, state S1can transition to state S3.

At state S2, circuit102can charge flying capacitor Cfly (seeFIG.1AtoFIG.2). Note that Vcfly being less than Vin/2 can indicate that flying capacitor Cfly needs to be charged to increase Vcfly to Vin/2. Referring toFIG.2, Cfly can be charged by enabling switch CHRG to switch in current source i_chrg. In response to Vcfly being increased to Vin/2, state S2can transition to state S4. At state S3, circuit102can discharge flying capacitor Cfly. Note that Vcfly being greater than Vin/2 can indicate that flying capacitor Cfly needs to be discharged to decrease Vcfly to Vin/2. Referring toFIG.2, Cfly can be discharged by enabling switch DIS to switch in current source i_dis. In response to Vcfly being decreased to Vin/2, state S3can transition to state S4.

At state S4, circuit102be put into a sleep mode where all components of circuit102can be disabled except for a timer programmed to a predetermined amount of time. At state S4, in response to the timer expiring (or a lapse of the predetermined amount of time), state S4can transition back to state S1to enable circuit102for comparing Vcfly with Vin/2.

FIG.9Ais an example diagram showing a flying capacitor voltage during a constant-off time mode of a flying capacitor startup circuit for multi-level voltage converters in one embodiment. A waveform900is shown inFIG.9Aand waveform900corresponds to the constant-off time mode implementation of state diagram800inFIG.8. Waveform900corresponds to scenarios where the flying capacitor Cfly is fully discharged (e.g., Vcfly is zero or close to zero) during a startup of circuit102(seeFIG.1AtoFIG.2) at a time t0. Since flying capacitor Cfly is fully discharged at time t0, circuit102can switch current source i_chrg to charge flying capacitor Cfly. Flying capacitor Cfly can be charged until Vcfly reaches Vin/2 (or close to Vin/2).

In response to Vcfly reaching Vin/2 at time t1, circuit102can go into sleep mode for a predetermined amount of time labeled as Toff. When circuit102is in sleep mode, flying capacitor voltage Vcfly can vary, such as increase or decrease due to various variations (e.g., temperature, environmental, leakage current). After a lapse of Toff, such as at a time t2, circuit102can be enabled again and measure Vcfly to determine whether flying capacitor Cfly needs to be charged or discharged. In the example shown by waveform900, circuit102can charge Cfly at time t2and Vcfly can reach Vin/2 at time t3. Hence, at time t3, circuit102can go into sleep mode again until the lapse of Toff ends at time t4.

FIG.9Bis another example diagram showing a flying capacitor voltage during a constant-off-time mode of a flying capacitor startup circuit for multi-level voltage converters in one embodiment. A waveform910is shown inFIG.9Band waveform910corresponds to the constant off-time mode implementation of state diagram800inFIG.8. Waveform910corresponds to scenarios where the flying capacitor Cfly is fully charged during a startup of circuit102(seeFIG.1AtoFIG.2) at a time t0. Since flying capacitor Cfly is fully charged at time t0, circuit102can switch current source i_dis to discharge flying capacitor Cfly. Flying capacitor Cfly can be discharged until Vcfly reaches Vin/2 (or close to Vin/2).

In response to Vcfly reaching Vin/2 at time t1, circuit102can go into sleep mode for a predetermined amount of time labeled as Toff. When circuit102is in sleep mode, flying capacitor voltage Vcfly can vary, such as increase or decrease due to various variations (e.g., temperature, environmental, leakage current). After a lapse of Toff, such as at a time t2, circuit102can be enabled again and measure Vcfly to determine whether flying capacitor Cfly needs to be charge or discharged. In the example shown by waveform900, circuit102can discharge Cfly at time t2and Vcfly can reach Vin/2 at time t3. Hence, at time t3, circuit102can go into sleep mode again until the lapse of Toff ends at time t4.

In one embodiment, the predetermined amount of time Toff can be programmable. By way of example, Toff can vary with an amount of expected leakage current. If relatively small leakage current is expected, then Toff can be programmed to be higher. If relatively large leakage current is expected, then Toff can be programmed to be lower. Setting Toff higher when less leakage current is expected can preserve power since circuit102can be enabled less frequently.

FIG.10is an example diagram of a circuit1000for implementing current sources in a flying capacitor startup circuit for multi-level voltage converters in one embodiment. In an embodiment shown inFIG.10, current sources such as i_chrg, i_dis, Δi, shown inFIG.2, can be connected to node Vc+ and can be implemented as P-type metal-oxide-semiconductor (PMOS) current mirrors driven by ground reference switched N-type metal-oxide-semiconductor (NMOS current sources). The switches UP, DOWN, CHRG, DIS shown inFIG.2can be driven by a control block702that can be a low voltage control circuit block including comparators, timers, and digital logic. Control block1002can receive Vin, Vout, and voltages at nodes Vc+ and Vc− as inputs. In one embodiment, control block1002can include, for example, circuits300,400,700inFIG.3andFIG.4, respectively.

FIG.11is a flow diagram illustrating a process to implement a flying capacitor startup circuit for multi-level voltage converters in one embodiment. The process can include one or more operations, actions, or functions as illustrated by one or more of blocks1102,1104, and/or1106. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, performed in different order, or performed in parallel, depending on the desired implementation.

Process1100can be performed by a circuit (e.g., circuit102inFIG.1) to operate a multi-level voltage converter. Process1100can begin at block1102. At block1102, the circuit can measure a flying capacitor voltage across a flying capacitor of a multi-level voltage converter. Process1100can proceed from block1102to block1104. At block1104, the circuit can compare the flying capacitor voltage with a voltage level equivalent to an intermediate voltage that is between ground and an input voltage being provided to the multi-level voltage converter. Process1100can proceed from block1104to block1106. At block1106, the circuit can switch a current source among the plurality of current sources to maintain the flying capacitor voltage at the intermediate voltage.

In one embodiment, in response to the flying capacitor voltage being lower than the intermediate voltage, the circuit can switch a first current source in the circuit to charge the flying capacitor. In response to the flying capacitor voltage being greater than the intermediate voltage, the circuit can switch a second current source in the circuit to discharge the flying capacitor.

In one embodiment, in response to the flying capacitor voltage being lower than the intermediate voltage, the circuit can switch a first current source in the circuit to charge the flying capacitor until the flying capacitor voltage reaches the intermediate voltage. In response to the flying capacitor voltage being greater than the intermediate voltage, the circuit can switch a second current source in the circuit to discharge the flying capacitor until the flying capacitor voltage reaches the intermediate voltage.

In one embodiment, in response to the flying capacitor voltage being lower than the intermediate voltage, the circuit can switch a first current source in the circuit to charge the flying capacitor until the flying capacitor voltage reaches the intermediate voltage. In response to the flying capacitor voltage being greater than the intermediate voltage, the circuit can switch a second current source in the circuit to discharge the flying capacitor until the flying capacitor voltage reaches the intermediate voltage. In response to the flying capacitor voltage reaching the intermediate voltage, the circuit can activate a sleep mode of the circuit. In response to a lapse of a predetermined amount of time, the circuit can deactivate the sleep mode of the circuit.

In one embodiment, in response to the flying capacitor voltage being lower than the intermediate voltage, switching a first current source in the circuit to charge the flying capacitor until the flying capacitor voltage reaches the intermediate voltage. In response to the flying capacitor voltage being greater than the intermediate voltage, the circuit can switch a second current source in the circuit to discharge the flying capacitor until the flying capacitor voltage reaches the intermediate voltage. In response to the flying capacitor voltage reaching the intermediate voltage, the circuit can activate a monitor mode to disconnect the first current source and the second current source from the flying capacitor. In response to the flying capacitor voltage reaching a lower bound of a predetermined voltage window, the circuit can switch the first current source in the circuit to charge the flying capacitor until the flying capacitor voltage reaches the intermediate voltage. In response to the flying capacitor voltage reaching an upper bound of a predetermined voltage window, the circuit can switch the second current source in the circuit to discharge the flying capacitor until the flying capacitor voltage reaches the intermediate voltage.

In one embodiment, the circuit can measure an output voltage of the multi-level voltage converter. The circuit can compare the output voltage with the intermediate voltage to determine whether the output voltage is greater than or less than the intermediate voltage. In response to the output voltage being less than the intermediate voltage, the circuit can switch a first current source in the circuit to pull a voltage at a negative terminal of the flying capacitor to ground and to pull a positive terminal of the flying capacitor to the intermediate voltage. In response to the output voltage being greater than the intermediate voltage, the circuit can switch a second current source in the circuit to pull a voltage at a negative terminal of the flying capacitor to the intermediate voltage and to pull a positive terminal of the flying capacitor to the input voltage.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The disclosed embodiments of the present invention have been presented for purposes of illustration and description but are not intended to be exhaustive or limited to the invention in the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.