Patent ID: 12224724

DETAILED DESCRIPTION

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

As previously discussed, LCMF-based amplifiers may be susceptible to voltage overshoot. To address this issue, at least some resistors in a LCMF may be arranged in parallel to a metal oxide semiconductor (MOS) resistor that is made of a positive-channel MOS (PMOS) and a negative-channel MOS (NMOS). The MOS resistor being arranged in parallel with the resistors is used to dynamically tune the amplifier gain across different process corners to reduce overshoot of the amplifier output. In other words, the MOS resistor may reduce the equivalent resistance for gain at high gain process corners to reduce the overshoot. For instance, the overshoot may be reduced to a lower value (e.g., 30 mV) from a higher value (e.g., 160 mV) that may occur without the MOS resistor while maintaining the fast response and low current benefits of the LCMF-based amplifier for lower gain process corners.

Turning now to the figures,FIG.1is a simplified block diagram illustrating certain features of an electronic device10having one or more power amplifiers12. Specifically, the block diagram ofFIG.1is a functional block diagram illustrating only certain functionality of the electronic device10. The power amplifiers12amplify signals/voltages/currents to a desired amplified level. In accordance with one embodiment, the electronic device10may be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device or a double data rate type four synchronous dynamic random access memory (DDR4 SDRAM). Additionally or alternatively, the electronic device10may include any type of electronic device that includes the one or more power amplifiers12. The one or more power amplifiers12receive an input power level14(e.g., voltage and/or current) and output an amplified power level16that is transmitted to target circuitry18that utilizes the amplified power level16. The target circuitry18may include any circuitry in the electronic device10that performs one or more functions using the amplified power level16. For example, the amplified power level16may include an array voltage provided to the target circuitry18as a memory array of the electronic device10. Furthermore, the amplified power level16may be delivered using a power bus. For instance, the array voltage may be provided to the memory array via an array voltage bus.

FIG.2is a circuit diagram of an operational transconductance amplifier (OTA)20that may be implemented as one of the power amplifiers12in the electronic device10. Although the OTA20is illustrated, the power amplifier(s)12may be implemented using any suitable amplifier scheme. As illustrated, the OTA20receives inputs22and24(In1 and In2) and outputs an OTA output26(Out). For instance, the inputs22and24may be opposite polarities (e.g., differential inputs). The inputs22and24are input to a transistor pair28that includes a first transistor30that receives the input22at a gate of the first transistor30and a second transistor32that receives the input24at a gate of the second transistor32. The first transistor30and the second transistor32may both be NMOS transistors, as illustrated. The transistor pair28is also coupled to biasing circuitry34via sources of the respective transistors. The biasing circuitry34provides bias voltages to the transistor pair28used in the OTA20. The drain of the first transistor30is coupled to node A, and the drain of the second transistor32is coupled to node B.

A current mirror36is coupled to node A. The current mirror36includes a transistor38that has a source coupled to a voltage supply (e.g., VPERI) and a gate coupled to a transistor40. The gates of the transistors38and40are both tied to the drain of the transistor40. With the gate and drain of the transistor40tied together, the transistor40acts like a diode connection along path41. Furthermore, since this diode connection has negligible resistance, little to no amplification occurs via the transistor40. Furthermore, the transistors38and40may be sized relatively the same thereby causing a 1:1 ratio between the currents through the transistors38and40.

A current mirror42is coupled to node B. The current mirror42includes a transistor46that has a source coupled to a voltage supply (e.g., VPERI) and a gate coupled to a transistor44. The gates of the transistors46and44are both tied to the drain of the transistor44. With the gate and drain of the transistor44tied together, the transistor44acts like a diode connection similar to the transistor42. Furthermore, the transistors46and44may be sized relatively the same thereby causing a 1:1 ratio between the currents through the transistors46and44.

The drains of transistors38and46are both coupled to legs of a current mirror48. The current mirror48includes transistor50that has its gate and drain coupled to drain of the transistors38. The current mirror48also includes transistor52that has its drain coupled to the drain of the transistor46and its gate coupled to the gate of the transistor50. The sources of the transistors50and52are coupled to ground. The transistors50and52may have sizes that are approximately equal, thereby causing the currents through the transistors50and52to be approximately equal.

To enhance amplification in the OTA20, at least part of the OTA20may be replaced with a local command mode feedback (LCMF). For instance,FIG.3shows a portion60of an OTA similar to the OTA20. The portion60includes an LCMF62coupled to the transistor pair28via Nodes A and B. The LCMF62utilizes a common connection64between gates of transistors66and68. The transistors66and68may include PMOS transistors with sources tied to voltage supplies (e.g., VPERI). The drain of the transistor66is coupled to the common connection64via a resistor72, and the drain of the transistor68is coupled to the common connection64via a resistor74. Since the respective gates and drains of the transistors66and68are tied together via respective resistors72and74, the connections are functionally equivalent to a diode with resistance. For instance, connection70may be equivalent to a diode plus resistance. This resistance enables the power amplifier12to provide a larger gain due to the LCMF62.

FIG.4is a schematic diagram of an embodiment of an LCMF resistor100that may be used to implement the resistors72and74. As illustrated, the LCMF resistor100is coupled to the Node A via an input102and coupled to the Node B via an input104. The LCMF resistor100is also coupled to the common connection64. The LCMF resistor100is illustrated in a common centroid layout.

The input102is coupled to a resistor106that may be selectively bypassed with a switch108. The resistor106, when optioned in using the switch108, is coupled in series to a resistor110as long as the resistor is not bypassed via a switch112. The resistor110, when optioned in using the switch112, is coupled in series with resistors114,116,118, and120. The resistor118may be bypassed using a switch119, and the resistor120may be bypassed using a switch121. The resistor120and/or the switch121are coupled to the common connection64. In summary, the amount of resistance between the input102and the common connection64may be adjusted by dynamically bypassing the resistor106via the switch108, dynamically bypassing the resistor110via the switch112, dynamically bypassing the resistor118via the switch119, and/or dynamically bypassing the resistor120via the switch121. Accordingly, the resistors106,110,114,116,118, and120may be used to implement the resistor72while providing flexibility of various resistances via the switches108,112,119, and121. In some embodiments, the resistors106,110,114,116,118, and120may each have a common resistance unit (e.g., 20 kΩ or 12 kΩ). In such embodiments, the maximum resistance when no resistors are bypassed may be 6× (e.g., 120 kΩ) of the unit resistance (e.g., 20 kΩ). The minimum resistance when resistors106,110,118, and120are bypassed is 2× (e.g., 40 kΩ) of the unit resistance (e.g., 20 kΩ). A default value (e.g., 80 kΩ) may include bypassing some (e.g., 2 resistors) while not bypassing others (e.g., 4 resistors).

The input104is coupled to a resistor122that may be selectively bypassed with a switch124. The resistor122, when optioned in using the switch124, is coupled in series to a resistor126as long as the resistor is not bypassed via a switch128. The resistor126, when optioned in using the switch128, is coupled in series with resistors130,132,134, and136. The resistor134may be bypassed using a switch135, and the resistor136may be bypassed using a switch137. The resistor136and/or the switch137are coupled to the common connection64. In summary, the amount of resistance between the input104and the common connection64may be adjusted by dynamically bypassing the resistor122via the switch124, dynamically bypassing the resistor126via the switch128, dynamically bypassing the resistor134via the switch135, and/or dynamically bypassing the resistor136via the switch137. Accordingly, the resistors122,126,130,132,134, and136may be used to implement the resistor74while providing flexibility of various resistances via the switches124,128,133, and135. In some embodiments, the resistors122,126,130,132,134, and136may each have a common resistance unit (e.g., 20 kΩ or 12 kΩ). In such embodiments, the maximum resistance when no resistors are bypassed may be 6× (e.g., 120 kΩ) of the unit resistance (e.g., 20 kΩ). The minimum resistance when resistors106,110,118, and120are bypassed is 2× (e.g., 40 kΩ) of the unit resistance (e.g., 20 kΩ). A default value (e.g., 80 kΩ) may include bypassing some (e.g., 2 resistors) while not bypassing others (e.g., 4 resistors).

The LCMF resistor100may include 1 or more dummy resistors. For instance, an embodiment of the LCMF resistor100includes a first dummy resistor138and a second dummy resistor140. Dummy resistors may be used in testing, used for electromagnetic (EM) isolation, or other situations. In some embodiments the dummy resistors may be omitted from the LCMF resistor100.

FIG.5is a graph150of voltages and currents in the OTA20and LCMF before, during, and after the OTA20is enabled over time152. The graph150includes a line156that corresponds to a voltage level for the amplifier. The graph150also includes a line158that corresponds to a current input to/output from the amplifier. The graph150also includes a line160that corresponds to a voltage of an amplify enable signal used to enable amplification via the OTA20. The graph150also includes a line162that corresponds to a voltage at the Node A, a line164that corresponds to a voltage at the Node B, and a line166that corresponds to a voltage at the Node B, and a line166that corresponds to a voltage at the OTA output26.

At time168, the amplifier is enabled via a pulse of the amplifier enable signal corresponding to the line160. At time170, after the pulse, the lines156,162,164, and166show corresponding changes with rapid slopes resulting in an overshoot172of the voltage output by the amplifier. Specifically, the lines162and164show sinks at the respective Nodes A and B. The overshoot172may be due to large gain of the amplifier and the large PMOSes used in the amplifier in response to loading/demand pull downs on the PMOS(es).

In some implementations, the overshoot172may be relatively large. For example, the overshoot172may be 160 mV to a total voltage of 1.12V. The amount of voltage overshot in the overshoot172is proportional to the amount of resistance in the LCMF. A smaller LCMF resistance causes a smaller overshoot. However, the smaller LCMF resistance also causes a smaller gain. Additionally, the smaller LCMF resistance causes a larger current. This overshoot172is more pronounced for amplifiers with high gain (e.g., fast FF) process corners than for lower gain (e.g., SS or TT) process corners. Furthermore, the overshoot is related to a step response/pulse while the overshoot does not occur in a continuous response.

To address such potential for overshoots, the LCMF resistor100may be enhanced/replaced with an LCMF resistor that utilizes a MOS resistor that selectively bypasses resistances for high gain process corners while not bypassing the same resistances for low gain process corners.FIG.6illustrates an LCMF resistor200that may be used to mitigate and/or eliminate overshoot in the LCMF-based amplifier. As illustrated, the LCMF resistor200is coupled to the Node A via the input102. The input102is coupled to resistors202,204, and206in series. The resistor206may be coupled to a resistor208that is coupled between the resistor206and the common connection64.

The LCMF resistor200also includes a MOS resistor216, also referred to as a pass gate, which is coupled in parallel with the resistors202,204, and206between nodes210and212. In other words, the MOS resistor216may be used to bypass a portion (e.g., resistors202,204, and206) of the string of resistors in the LCMF resistor200. The MOS resistor216includes a transistor214that has its gate coupled to a voltage supply (e.g., VPERI), its source coupled to the node210, and its drain coupled to the node212. As illustrated, the transistor214may be an NMOS transistor but may include any other suitable transistor type. The MOS resistor216also includes a transistor217that has its gate coupled to ground, its drain coupled to the node210, and its source coupled to the node212. As illustrated, the transistor217may be a PMOS transistor but may include any other suitable transistor type.

The MOS resistor216is process dependent with the amount of resistance provided via the MOS resistor216dependent upon the process corner applied to the MOS resistor216. For example, at a fast FF process corner, the resistance through the MOS resistor216provides a lower resistance path between the nodes210and212through the MOS resistor216to effectively bypass the resistors202,204, and206. With the lower resistance path, the LCMF resistor200provides a lower level of gain than if the path through the resistors202,204, and206were used.

For a slow SS process corner, the resistance through the MOS resistor216is relatively high causing the lower resistance path between the nodes210and212to be through the resistors202,204, and206rather than through the MOS resistor216. This routing through the resistors202,204, and206increases effective resistance between nodes210and212relative to the fast FF corner. By increasing the effective resistance, the slow SS process corner experiences more gain than the slow SS corner. For intermediate TT process corners, the path through the resistors202,204, and206and through the MOS resistor216may be substantially similar and may provide the least resistance between the nodes210and212through the resistors202,204, and206and/or through the MOS resistor216.

As illustrated, the LCMF resistor200is coupled to the Node B via the input104. The input104is coupled to resistors218,220, and222in series. The resistor222may be coupled to a resistor224that is coupled between the resistor222and the common connection64.

The LCMF resistor200also includes a MOS resistor232, which is similar to the MOS resistor216and is also referred to as a pass gate. The MOS resistor232is coupled in parallel with the resistors218,220, and222between nodes226and228. The MOS resistor232includes a transistor230that has its gate coupled to a voltage supply (e.g., VPERI), its source is coupled to the node226, and its drain is coupled to the node228. As illustrated, the transistor230may be an NMOS transistor but may include any other suitable transistor type. The MOS resistor232also includes a transistor234that has its gate coupled to ground, its drain coupled to the node226, and its source coupled to the node228. As illustrated, the transistor234may be a PMOS transistor but may include any other suitable transistor type.

The MOS resistor232is process dependent with the amount of resistance provided via the MOS resistor232depending on the process corner being applied to the MOS resistor232. For example, at a fast FF process corner, the resistance through the MOS resistor232provides a lower resistance path between the nodes226and228through the MOS resistor232to effectively bypass the resistors218,220, and222. With the lower resistance path, the LCMF resistor200provides a lower level of gain than if the path through the resistors218,220, and222were used.

For a slow SS process corner, the resistance through the MOS resistor232is relatively high causing the lower resistance path between the nodes226and228to be through the resistors218,220, and222rather than through the MOS resistor232. This routing through the resistors218,220, and222increases effective resistance between nodes226and228relative to the fast FF corner. By increasing the effective resistance, the slow SS process corner experiences more gain than the slow SS corner. For intermediate TT process corners, the path through the resistors218,220, and222and through the MOS resistor232may be substantially similar and may provide the least resistance between the nodes226and228through the resistors218,220, and222and/or through the MOS resistor232.

Since the fast FF process corner is more susceptible to overshoot than slower process corners (e.g., TT and SS), this reduction of gain reduces gain only where it is most likely to cause overshoot while maintaining a higher gain for the slower process corners that are less susceptible to overshoot.

In some embodiments, the resistors202,204,206,208,218,220,222, and224may each have the same resistance unit. In certain embodiments, the MOS resistors216and232may be used to bypass at least 1 resistor in the LCMF resistor100implemented using a common centroid layout.

Although the foregoing discusses various logic-low and/or logic-high assertion polarities, at least some of these polarities may be inverted in some embodiments. While the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. For instance, PMOS and NMOS transistors may be swapped and polarities of voltages may be reversed. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the following appended claims.

The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . ” or “step for [perform]ing [a function] . . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).