Patent ID: 12219767

DETAILED DESCRIPTION

In one embodiment, a semiconductor device includes a first substrate including a first region and a second region on a surface of the first substrate. The device further includes a first control circuit provided on the first substrate in the first region, a first memory cell array provided above the first control circuit in the first region and electrically connected to the first control circuit, and a first pad provided above the first memory cell array in the first region and electrically connected to the first control circuit. The device further includes a second control circuit provided on the first substrate in the second region, a second memory cell array provided above the second control circuit in the second region and electrically connected to the second control circuit, and a second pad provided above the second memory cell array in the second region and electrically connected to the second control circuit. The device further includes a connection line provided above the first memory cell array and the second memory cell array and electrically connecting the first pad to the second pad.

Embodiments will now be explained with reference to the accompanying drawings. InFIGS.1to21, same or similar components are denoted by the same reference symbols, and redundant description thereof will be omitted.

First Embodiment

FIG.1is a sectional view showing a structure of a semiconductor device of a first embodiment. The semiconductor device ofFIG.1is a three-dimensional memory in which an array chip1is bonded to a circuit chip2.

The array chip1includes a memory cell array11including plural memory cells, an insulating layer12on the memory cell array11, a substrate13on the insulating layer12, an insulating layer14on the substrate13, an inter layer dielectric15under the memory cell array11, and a first insulating layer16under the inter layer dielectric15. The insulating layers12and14are, for example, silicon oxide films or silicon nitride films. The substrate13is, for example, a semiconductor substrate such as a silicon substrate.

The circuit chip2is provided under the array chip1. Reference symbol S denotes a bonding surface between the array chip1and circuit chip2. The circuit chip2includes a second insulating layer17, an inter layer dielectric18under the second insulating layer17, and a substrate19under the inter layer dielectric18. The substrate19is, for example, a semiconductor substrate such as a silicon substrate.

FIG.1shows an X direction and Y direction perpendicular to each other and parallel to surfaces S1and S2of the substrate13and surfaces S3and S4of the substrate19as well as a Z direction perpendicular to surfaces S1and S2of the substrate13and surfaces S3and S4of the substrate19. In the present specification, a +Z direction is treated as an upward direction and −Z direction is treated as a downward direction. For example, the memory cell array11is located above the substrate19and below the substrate13. The −Z direction may or may not coincide with the gravity direction.

As an electrode layer in the memory cell array11, the array chip1includes plural word lines WL, a source-side selection gate SGS, a drain-side selection gate SGD, and a source line SL.FIG.1shows a staircase structure21of the memory cell array11. As shown inFIG.1, each of the word lines WL is electrically connected with a word interconnection layer23via a contact plug22and the source-side selection gate SGS is electrically connected with source-side selection gate interconnection layers25via contact plugs24. Furthermore, the drain-side selection gate SGD is electrically connected with a drain-side selection gate interconnection layer27via a contact plug26and the source line SL is electrically connected with a source interconnection layer30via a contact plug29. Each columnar portion CL penetrating the word lines WL, source-side selection gate SGS, drain-side selection gate SGD, and source line SL is electrically connected with a bit line BL via a plug28and electrically connected with the substrate13.

The circuit chip2includes plural transistors31. The transistors31include respective gate electrodes32provided on the substrate19via gate insulators as well as non-illustrated source diffusion layers and drain diffusion layers provided in the substrate19. The circuit chip2further includes plural plugs33provided on the source diffusion layers or drain diffusion layers of the transistors31, an interconnection layer34provided on the plugs33and including plural interconnections, and an interconnection layer35provided on the interconnection layer34and including plural interconnections. The circuit chip2further includes plural via plugs36provided on the interconnection layer35and plural second metal pads37provided on the via plugs36in the second insulating layer17. The circuit chip2functions as a control circuit (logic circuit) adapted to control the array chip1.

The array chip1includes plural first metal pads41provided on the second metal pads37in the first insulating layer16, plural via plugs42provided on the first metal pads41, and an interconnection layer43provided on the via plugs42and including plural interconnections. The word lines WL and bit lines BL of the present embodiment are electrically connected with corresponding interconnections in the interconnection layer43. The array chip1further includes a first plug44provided on the interconnection layer43as well as being provided in the inter layer dielectric15and insulating layer12, a second plug46provided on the first plug44as well as being provided in the substrate13and insulating layer14via an insulating layer45, and a pad47provided on the insulating layer14and second plug46. The pad47is an external connecting pad (bonding pad) of the semiconductor device of the present embodiment and is connectable to a mounting substrate or another device via a soldering ball, metal bump, bonding wire, or the like.

Although in the present embodiment, the first insulating layer16is formed on a lower surface of the inter layer dielectric15, the first insulating layer16may be included in and integrated with the inter layer dielectric15. Similarly, although the second insulating layer17is formed on an upper surface of the inter layer dielectric18the second insulating layer17may be included in and integrated with the inter layer dielectric18.

FIG.2is a sectional view showing a structure of the columnar portion CL included in the semiconductor device of the first embodiment.

As shown inFIG.2, the memory cell array11includes plural word lines WL and plural insulating layers51stacked alternately on the inter layer dielectric15. Each of the word lines WL is, for example, a W (tungsten) layer. Each of the insulating layers51is, for example, a silicon oxide film.

The columnar portion CL includes in order of a block insulator52, a charge storage layer53, a tunnel insulator54, a channel semiconductor layer55, and a core insulator56. The charge storage layer53is, for example, a silicon nitride film, and is formed on side faces of the word lines WL and insulating layers51via a block insulator52. The channel semiconductor layer55is, for example, a silicon layer and is formed on a side face of the charge storage layer53via the tunnel insulator54. Examples of the block insulator52, tunnel insulator54, and core insulator56include silicon oxide films and metal insulators.

FIG.3is a sectional view showing a method of manufacturing the semiconductor device of the first embodiment.FIG.3shows an array wafer W1including plural array chips1and a circuit wafer W2including plural circuit chips2. The array wafer W1is also called a memory wafer and the circuit wafer W2is also called a CMOS wafer.

First, the array wafer W1is bonded to the circuit wafer W2by mechanical pressure. Consequently, the first insulating layer16is adhered to the second insulating layer17. Next, the array wafer W1and the circuit wafer W2are annealed at 400 degrees C. Consequently, the first metal pads41are joined to the second metal pads37.

Subsequently, the substrates13and19are thinned by CMP (Chemical Mechanical Polishing), and then the array wafer W1and the circuit wafer W2are diced into plural chips. In this way, the semiconductor device ofFIG.1is manufactured. The insulating layer14, insulator45, second plug46, and the pad47are formed on or in the substrate13, for example, after the thinning of the substrate13.

Although the array wafer W1is bonded to the circuit wafer W2in the present embodiment, the array wafer W1may be bonded to another array wafer W1instead. The description given above with reference toFIGS.1to3and description to be given later with reference toFIGS.4to18are also applicable to bonding between array wafers W1.

Also, whileFIG.1shows a boundary surface between the first insulating layer16and second insulating layer17as well as a boundary surface between the first metal pads41and second metal pads37, generally these boundary surfaces become unobservable after the annealing. However, locations where the boundary surfaces existed can be estimated by detecting, for example, inclinations of side faces of the first metal pads41and side faces of the second metal pads37or displacement between the side faces of the first metal pads41and the second metal pads37.

FIG.4is another sectional view showing the structure of the semiconductor device of the first embodiment.FIG.4shows a section of the semiconductor device as withFIG.1, but the structure of the semiconductor device is shown from a different perspective fromFIG.1.

According to the present embodiment, the array wafer W1and the circuit wafer W2after the bonding but before dicing include plural dual chips C, each of which includes a first single chip C1and second single chip C2(FIG.4). Each of the first single chip C1and second single chip C2corresponds to one semiconductor device shown inFIG.1.

The array wafer W1and the circuit wafer W2after the bonding may be diced into individual single chips C1and C2or into individual dual chips C.FIG.4shows a semiconductor device manufactured by dicing an array wafer into individual dual chips C. Consequently, the semiconductor device ofFIG.4is made up of one dual chip C including a first single chip C1and second single chip C2.

The semiconductor device ofFIG.4includes the array chip1and circuit chip2in the first single chip C1as well as the array chip1and circuit chip2in the second single chip C2. The memory cell array11and circuits such as a logic circuit in the first single chip C1are provided on the side of the surface S1of the substrate13, between the surface S1of the substrate13and surface S3of the substrate19. Similarly, the memory cell array11and circuits such as a logic circuit in the second single chip C2are provided on the side of the surface S1of the substrate13, between the surface S1of the substrate13and surface S3of the substrate19. The memory cell array11and logic circuit in the first single chip C1are examples of a first memory array and first control circuit, respectively. The memory cell array11and logic circuit in the second single chip C2are examples of a second memory array and second control circuit, respectively. The substrate19is an example of a first substrate and the substrate13is an example of a second substrate. Also, a region of the first single chip C1on the substrate19is an example of a first region and a region of the second single chip C2on the substrate19is an example of a second region.

The first single chip C1includes a first plug44electrically connected with the memory cell array11and logic circuit in the first single chip C1, a second plug46provided on the first plug44, and the pad47provided on the second plug46. In the first single chip C1, the second plug46penetrates the substrate13and the pad47is provided on the side of a surface S2of the substrate13. The pad47is an example of a first pad.

Also, the second single chip C2includes a first plug44electrically connected with the memory cell array11and logic circuit in the second single chip C2, a second plug46provided on the first plug44, and the pad47provided on the second plug46. In the second single chip C2, the second plug46penetrates the substrate13and the pad47is provided on the side of a surface S2of the substrate13. The pad47is an example of a second pad.

FIG.4further shows an interconnection layer20formed on the insulating layer14on the side of a surface S2of the substrate13. The interconnection layer20is a metal conductive layer such as an Al (aluminum) layer. The interconnection layer20includes an interconnection (routing interconnection)48configured to electrically connect the pad47in the first single chip C1with the pad47in the second single chip C2. The interconnection48is an example of a connection line and the interconnection layer20is an example of a metal layer.

The interconnection layer20of the present embodiment includes not only the interconnection48, but also the pad47in the first single chip C1and the pad47in the second single chip C2. That is, the pads47and interconnection48of the present embodiment are formed of the same interconnection layer20. This makes it possible to form the pads47and interconnection48in a simple manner. AlthoughFIG.4shows a step between upper surfaces of the pads47and interconnection48for ease of understanding, such a step does not need to be provided. The pad47in the first single chip C1, the pad47in the second single chip C2, and the interconnection48make up the interconnection layer20by being continuous with one another.

The pad47in the first single chip C1is used as an external connecting pad of the first single chip C1when the array wafer W1and the circuit wafer W2are diced into individual single chips. Also, the pad47in the second single chip C2is used as an external connection pad of the second single chip C2when the array wafer W1and the circuit wafer W2are diced into individual single chips.

On the other hand, in dicing the array wafer W1and the circuit wafer W2into individual dual chips, only either of the pad47in the first single chip C1and the pad47in the second single chip C2is used as an external connecting pad common to the first and second single chips C1and C2. According to the present embodiment, only the pad47in the second single chip C2is used as an external connecting pad.

The interconnection48of the present embodiment is provided for use in dicing the array wafer W1and the circuit wafer W2into individual dual chips. Specifically, input current and input voltage to the pad47in the second single chip C2are supplied not only to circuits in the second single chip C2, but also to circuits in the first single chip C1via the interconnection48. On the other hand, output current and output voltage to the pad47in the second single chip C2, are supplied not only from the circuits in the second single chip C2, but also from the circuits in the first single chip C1via the interconnection48.

FIG.4further shows a passivation film49formed on the interconnection layer20on the side of the surface S2of the substrate13. The passivation film49is, for example, an insulator such as a silicon oxide film. The passivation film49may have openings P on the pads47in both the first and second single chips C1and C2or may have an opening P on the pad47in one of the first and second single chips C1and C2. According to the present embodiment, since only the pad47in the second single chip C2is used as an external connecting pad, an opening P is provided only on the pad47in the second single chip C2.

The semiconductor device ofFIG.4further includes a dicing line50for use in dicing the first single chip C1and second single chip C2. The first single chip C1and second single chip C2ofFIG.4are adjacent to each other in the X direction, and consequently the dicing line50extends in the Y direction. Because the semiconductor device ofFIG.4is manufactured by dicing the array wafer W1and the circuit wafer W2into individual dual chips, the dicing line50eventually remains unused for dicing.

The interconnection48of the present embodiment is formed to cross the dicing line50, i.e., formed at a position where the interconnection48overlaps with the dicing line50in the Z direction. Therefore, when the array wafer W1and the circuit wafer W2are diced into individual single chips, the dicing line50is cut, thereby cutting the interconnection48. According to the present embodiment, when the array wafer W1and the circuit wafer W2are diced into individual single chips, because there is no need to use the interconnection48, there is no problem even if the interconnection48is cut as described above.

When the dicing line50ofFIG.4is cut, an end face of the substrate13in the first single chip C1is formed on the dicing line50. The interconnection48in the first single chip C1extends from the pad47in the first single chip C1to right above the end face. Therefore, when the array wafer W1and the circuit wafer W2are diced into individual single chips, the interconnection48in the first single chip C1has a shape such that the interconnection48extends to a position where the interconnection48overlaps with the end face of the substrate13in the Z direction to be electrically open. Similarly, the interconnection48in the second single chip C2also has a shape such that the interconnection48extends to a position where the interconnection48overlaps with the end face of the substrate13in the Z direction to be electrically open. The Z direction is an example of a first direction.

Other than the interconnection48, the dual chip C of the present embodiment does not include an interconnection electrically connecting the first single chip C1and second single chip C2to cross the dicing line50ofFIG.4. Consequently, even if the dicing line50is cut, no interconnection is cut except the interconnection48. Therefore, the first single chip C1and second single chip C2of the present embodiment function as semiconductor chips even if cut off from each other. To put it another way, according to the present embodiment, no interconnection other than the interconnection48is provided on the dicing line50such that the first single chip C1and second single chip C2can function as semiconductor chips even if cut off from each other.

FIGS.5A and5Bare plan views showing first and second examples of the semiconductor device of the first embodiment.

As a first example,FIG.5Ashows a semiconductor device equipped with the first and second single chips C1and C2cut off from each other. Straight lines X1, X1′, X2, Y1, and Y2indicate the dicing lines50to be cut. It should be noted that the dicing line50between the first single chip C1and second single chip C2is cut as indicated by the straight line X1′.

As a second example,FIG.5Bshows a semiconductor device equipped with the dual chip C, i.e., the first and second single chips C1and C2not cut off from each other. Straight lines X1, X2, Y1, and Y2indicate the dicing lines50to be cut. It should be noted that the dicing line50between the first single chip C1and second single chip C2is not cut as seen from the fact that the straight line X1′ is not shown.

As shown in each ofFIGS.5A and5B, the first single chip C1includes eight pads47denoted by reference symbols A to H and the second single chip C2includes ten pads47denoted by reference symbols A to H, X, and Y. Hereinafter these pads47will be referred to as “pad A,” “pad B,” “pad C,” and the like as appropriate.

The pads47in the first single chip C1correspond to the pads47denoted by the same reference symbols in the second single chip C2. That is, the pads A to H in the first single chip C1correspond to the pads A to H in the second single chip C2. Therefore, as shown inFIG.5B, the pads A, C, D, F, G, and H in the first single chip C1are electrically connected to the pads A, C, D, F, G, and H in the second single chip C2, respectively, by the interconnections48. On the other hand, by way of exception, the pads B and E in the first single chip C1are electrically connected to the pads X and Y in the second single chip C2, respectively, by the interconnections48. InFIG.5A, all of these interconnections48are cut.

FIGS.6A and6Bare other plan views showing the first and second examples of the semiconductor device of the first embodiment.

FIG.6Acorresponds to the first example inFIG.5A. InFIG.6A, the pads A to H in the second single chip C2are connected to non-illustrated terminals inside or outside the semiconductor device by bonding wires61. For reference symbols of the pads47, refer toFIG.5A.

Also, the pads A, C, D, F, G, and H in the first single chip C1are connected to the pads A, C, D, F, G, and H in the second single chip C2, respectively, by bonding wires62. This allows the pads A, C, D, F, G, and H in the first single chip C1to have the same functions as the pads A, C, D, F, G, and H in the second single chip C2, respectively.

Furthermore, the pads B and E in the first single chip C1are connected to non-illustrated terminals inside or outside the semiconductor device by bonding wires63as with the pads B and E in the second single chip C2. This allows the pads B and E in the first single chip C1to have the same functions as the pads B and E in the second single chip C2, respectively. InFIG.6A, the pads X and Y in the second single chip C2are not used.

FIG.6Bcorresponds to the second example inFIG.5B. InFIG.6B, the pads A to H, X, and Y in the second single chip C2are connected to non-illustrated terminals inside or outside the semiconductor device by the bonding wires61. For reference symbols of the pads47, refer toFIG.5B.

Here, inFIG.6B, the pads A, C, D, F, G, and H in the first single chip C1are connected to the pads A, C, D, F, G, and H in the second single chip C2, respectively, by the interconnections48. This allows the pads A, C, D, F, G, and H in the first single chip C1to have the same functions as the pads A, C, D, F, G, and H in the second single chip C2, respectively.

Furthermore, inFIG.6B, the pads B and E in the first single chip C1are connected to the pads X and Y in the second single chip C2, respectively, by the interconnections48. Therefore, just as the pad B in the second single chip C2is connected to a non-illustrated terminal inside or outside the semiconductor device by the bonding wire61, the pad B in the first single chip C1is also connected to non-illustrated terminals inside or outside the semiconductor device by the interconnections48, the pad X in the second single chip C2, and the bonding wire61of the pad X. Also, just as the pad E in the second single chip C2is connected to a non-illustrated terminal inside or outside the semiconductor device by the bonding wire61, the pad E in the first single chip C1is also connected to non-illustrated terminals inside or outside the semiconductor device by the interconnection48, the pad Y in the second single chip C2, and the bonding wire61of the pad Y. This allows the pads B and E in the first single chip C1to have the same functions as the pads B and E in the second single chip C2, respectively.

Examples of the pads B and E include a pad47for a chip enable signal. Generally, the chip enable signals have to be supplied separately to the first single chip C1and second single chip C2. Therefore, the pads B and E of the present embodiment are implemented in a form different from the pad A, C, D, F, G, and H.

In this way, the semiconductor device of the present embodiment may be configured as with the first example or configured as with the second example. In the first example, the bonding wires61,62, and63are bonded to both the pads47in the first single chip C1and the pads47in the second single chip C2. On the other hand, in the second example, the bonding wire61is bonded only to the pads47in the second single chip C2out of the pads47in the first single chip C1and the pads47in the second single chip C2. However, in the second example, since the pads47in the first single chip C1and the pads47in the second single chip C2are electrically connected by the interconnections48, the semiconductor device of the second example can function in a manner similar to the first example.

In the first and second examples, a semiconductor device having a storage capacity twice as large as one single chip can be manufactured in a simple manner.

FIGS.7A and7Bare sectional views showing the first and second examples of the semiconductor device of the first embodiment.

FIG.7Ashows a variation of the first example shown inFIGS.5A and6B. The semiconductor device ofFIG.7Aincludes four first single chips C1stacked one on top of another. The pads47in the first single chips C1are interconnected by the bonding wires61. Consequently, a semiconductor device having a storage capacity four times as large as one single chip can be manufactured in a simple manner.

FIG.7Bshows a variation of the second example shown inFIGS.5A and6B. The semiconductor device ofFIG.7Bincludes four first dual chips C stacked one on top of another. In each of the dual chips C, the pads47in the first single chip C1and the pads47in the second single chip C2are interconnected by the interconnections48. Furthermore, the pads47in the first single chips C1of different dual chips C are interconnected by the bonding wires61. Consequently, a semiconductor device having a storage capacity eight times as large as one single chip can be manufactured in a simple manner.

FIG.8is another plan view showing the second example of the semiconductor device of the first embodiment.

FIG.8shows the second example ofFIG.5Band the like in more detail, and more specifically, shows four dual chips C. According to the present embodiment, the dicing line50between the first single chip C1and second single chip C2of the same dual chip C has a small width Δ1and the dicing line50between the dual chips C has a large width Δ2. The width Δ1is an example of a first width and the width Δ2is an example of a second width.

Straight lines X1, X2, X3, Y1, Y2, and Y3ofFIG.8indicate dicing lines50to be cut in the second example. In the second example, the dicing lines50with the width Δ1are not cut and only the dicing lines50with the width Δ2are cut. The interconnections48are configured to cross the dicing lines50with the width Δ1, but not to cross the dicing lines50with the width Δ2. Consequently, in the second example, the interconnections48are not cut by dicing.

FIG.9is another plan view showing the first example of the semiconductor device of the first embodiment.

FIG.9shows the first example ofFIG.5Aand the like in more detail, and more specifically, shows four sets of the first and second single chips C1and C2. The widths Δ1and Δ2of the dicing lines50are set as in the case of the second example. Straight lines X1, X1′, X2, X2′, X3, Y1, Y2, and Y3ofFIG.9indicate dicing lines50to be cut in the first example. In the first example, both the dicing lines50with the width Δ1and the dicing lines50with the width Δ2are cut. Consequently, in the first example, the interconnections48are cut by dicing. In this way, according to the present embodiment, the dicing line50between the first single chip C1and second single chip C2of the same dual chip C has a small width Δ1. This makes it possible to reduce the area of the dual chip C.

FIGS.10A and10Bare plan views for explaining a yield of the semiconductor device of the first embodiment.

FIG.10Acorresponds to the first example inFIG.6A. According to the present embodiment, a predetermined number of memory cells are treated as one block and the memory cells in the memory cell array11are treated on a block by block basis. Also, in manufacturing plural single chips as semiconductor devices, it is determined whether a given single chip is a non-defective chip (conforming chip) based on whether the number of defective blocks (non-conforming blocks) in the single chip is in a predetermined range. The predetermined range is an example of a first range. Specifically, when the number of defective blocks in a given single chip is less than eight, the single chip is determined to be a non-defective chip. On the other hand, when the number of defective blocks in a given single chip is eight or more, the single chip is determined to be a defective chip (non-conforming chip).

InFIG.10A, the number of defective blocks in the first single chip C1is ten, and therefore the first single chip C1is determined to be a defective chip. On the other hand, the number of defective blocks in the second single chip C2is two, and therefore the second single chip C2is determined to be a non-defective chip.

FIG.10Bcorresponds to the second example inFIG.6B. InFIG.10B, the number of defective blocks in the first single chip C1is ten and the number of defective blocks in the second single chip C2is two. Therefore, if the same determination criterion as the first example is adopted, the first single chip C1is determined to be a defective chip and the second single chip C2is determined to be a non-defective chip.

However, according to the present embodiment, it is determined whether a dual chip C is a non-defective chip, based on the average number of defective blocks across the single chips in the dual chip C. For example, when the average number of defective blocks in a dual chip C is less than eight, the dual chip C is determined to be a non-defective chip. On the other hand, when the average number of defective blocks in a dual chip C is eight or above, the dual chip C is determined to be a defective chip.

InFIG.10B, the average number of defective blocks across the single chips in the dual chip C is six (=(10+2)/2). Since the average number is less than 8, the dual chip C is determined to be a non-defective chip. In other words, this determination criterion involves “determining whether the total number of defective blocks in the dual chip C is 16 or above.”

In this way, according to the present embodiment, it is determined whether a dual chip C is a non-defective chip, based on the average number of defective blocks in the dual chip C. Consequently, even if either of the first and second single chips C1and C2is treated as a defective chip, the dual chip C can be treated as a non-defective chip. This makes it possible to increase a yield of the dual chip C.

Generally, a semiconductor device works to replace any defective block with a normal block called a redundant block. Such replacements are often carried out by a controller in the semiconductor device. When the semiconductor device of the present embodiment is a dual chip C, a defective block in one of the first and second single chips C1and C2may sometimes be replaced with a redundant block in the other of the first and second single chips C1and C2. According to the present embodiment, the controller is designed to be capable of carrying out such a replacement between single chips. Such a controller is mounted, for example, in the circuit chip2.

FIGS.11to16are sectional views showing the method of manufacturing the semiconductor device of the first embodiment, where the method shown inFIG.3is shown here in more detail.

FIG.11shows the array wafer W1and the circuit wafer W2as withFIG.3. This array wafer W1has already been provided with the first plug44, but has not been provided with the insulator45, second plug46, pad47, interconnection48, or passivation film49. Furthermore, the substrate13includes a well13aand other parts13b.

First, the array wafer W1is bonded to the circuit wafer W2by mechanical pressure followed by annealing (FIG.1). Next, the substrate13is thinned, thereby removing the parts13bother than the well13afrom the substrate13(FIG.12).

Next, the insulating layer14is formed on the substrate13, and an opening H penetrating the insulating layer14and substrate13is formed by RIE (Reactive Ion Etching) (FIG.13). Consequently, the first plug44is exposed in the opening H.

Next, the insulator45is formed on an inner surface of the opening H (FIG.14). Next, the interconnection layer20is formed on surfaces of the first plugs44, insulator45, and insulating layer14(FIG.15). Consequently, the interconnection layer20is formed on the inner surface and bottom surface of the opening H and on an upper surface of the insulating layer14. The interconnection layer20on the inner surface and bottom surface of the opening H functions as the second plug46. On the other hand, the interconnection layer20on the upper surface of the insulating layer14functions as the pad47.

In this way, in the present method, both the second plug46and the pad47are formed by the interconnection layer20. Also, in the present method, the second plug46is formed on plural first plugs44rather than one first plug44. However, the second plug46may be formed by a layer other than the interconnection layer20and may be formed on one first plug44.

Next, the passivation film49including the first insulator49aand second insulator49bis formed on the entire surface of the substrate13(FIG.16). Next, the opening P penetrating the passivation film49is formed by RIE (FIG.16). Consequently, the pad47is exposed in the opening.

Subsequently, the substrate19is thinned, and the array wafer W1and the circuit wafer W2are diced into individual single chips or dual chips. Both single chips and dual chips may be manufactured from the set of the array wafer W1and the circuit wafer W2. Furthermore, bonding wires may be bonded to the pads47. In this way, the semiconductor device of the present embodiment is manufactured.

FIGS.17and18are sectional views showing details of the method of manufacturing the semiconductor device of the first embodiment.

FIG.17shows details ofFIG.15. The interconnection layer20ofFIG.17includes not only the second plug46and the pad47, but also the interconnection48. In this way, both the pad47and the interconnection48of the present embodiment are formed by the interconnection layer20.

FIG.18shows details ofFIG.16. It should be noted that the interconnection layer20includes the interconnection48covered with the passivation film49. When the array wafer W1and the circuit wafer W2are diced into individual single chips, the dicing is done such that the interconnection48will be cut. On the other hand, when the array wafer W1and the circuit wafer W2are diced into individual dual chips, the dicing is done such that the interconnection48will not be cut.

FIG.19is a circuit diagram showing a configuration of the semiconductor device of the first embodiment. WhileFIG.19shows a configuration of the first single chip C1, the second single chip C2also has the configuration as shown inFIG.19.

As shown inFIG.19, the first single chip C1has the memory cell array11in the array chip1and has an I/O (Input/Output) control circuit71, a logic control circuit72, a status register73, an address register74, a command register75, a control circuit76, a ready/busy circuit77, a voltage generator78, a row decoder81, a sense amplifier82, a data register83, and a column decoder84in the circuit chip2.

The I/O control circuit71exchanges input signals and output signals with a controller (not shown) via data lines DQ0-0to DQ7-0. The logic control circuit72receives a chip enable signal BCE-0, a command latch enable signal CLE-0, an address latch enable signal ALE-0, a write enable signal BWE-0, and read enable signals RE-0and BRE-0, and controls operations of the I/O control circuit71and control circuit76of these signals.

The status register73is used to store status of a read operation, write operation, and erase operation and notify the controller of completion of these operations. The address register74is used to store address signals received by the I/O control circuit71from the controller. The command register75is used to store the command signals received by the I/O control circuit71from the controller.

The control circuit76performs read operations, write operations, and erase operations by controlling the status register73, ready/busy circuit77, voltage generator78, row decoder81, sense amplifier82, data register83, and column decoder84of command signals from the command register75.

The ready/busy circuit77transmits a ready/busy signal RY/BBY-0to the controller of operating conditions of the control circuit76. This makes it possible to indicate whether or not the control circuit76is ready to receive a command. The voltage generator78generates voltages needed for a read operation, write operation, and erase operation.

The row decoder81applies voltages to the word lines WL of the memory cell array11. The sense amplifier82detects data read out to the bit lines BL of the memory cell array11. The data register83is used to store data from the I/O control circuit71and sense amplifier82. The column decoder84decodes a column address, and selects a latch circuit in the data register83based on a decoding result. The row decoder81, sense amplifier82, data register83, and column decoder84function as interfaces for read operations, write operations, and erase operations with respect to the memory cell array11.

Details of the first single chip C1, second single chip C2, and dual chip C of the present embodiment will be described below.

According to the present embodiment, the first single chip C1and the second single chip C2have the same capacity while the dual chip C has twice the capacity of each single chip. The dual chip C is manufactured, for example, when a memory with a capacity equal to that of two single chips is needed.

Generally, single chips and dual chips are manufactured using different mask sets, and therefore, it is troublesome to manufacture both the single chips and the dual chips. However, according to the present embodiment, the array wafer W1and the circuit wafer W2used to manufacture the first and second single chips C1and C2can be configured to have the same structures as the array wafer W1and the circuit wafer W2used to manufacture the dual chip C. Consequently, the first and second single chips C1and C2and the dual chip C of the present embodiment can be manufactured with the same mask set. Therefore, the present embodiment allows the first and second single chips C1and C2and the dual chip C to be manufactured efficiently.

Generally, when plural mask sets are prepared, there are problems in that manufacturing cost of the semiconductor device increases, that throughput at the time of manufacturing the semiconductor device decreases, and/or that improvement in mass production yield of the semiconductor device is hindered. By manufacturing the first and second single chips C1and C2and the dual chip C in the manner described above, the present embodiment can solve these problems.

Whereas a chip (dual chip) including two single chips is manufactured in the present embodiment, a chip including three or more single chips may be manufactured. In that case, desirably the pads47in different single chips are electrically connected by the interconnections48.

Also, the pad47of the present embodiment is formed on the side of the surface S2of the substrate13, but may be formed on the side of the surface S4of the substrate19instead. Also, the semiconductor device of the present embodiment is manufactured from two wafers (the array wafer W1and the circuit wafer W2), but may be manufactured from one wafer instead. Also, the semiconductor device of the present embodiment may be a device other than a semiconductor memory.

The interconnection48of the present embodiment is formed on the side of the surface S2of the substrate13as with the pad47. If the interconnection48is formed between the surface S1of the substrate13and the surface S3of the substrate19, the interconnection48may reduce the degree of freedom of layout of other interconnections. Therefore, desirably the interconnection48is formed on the side of the surface S2of the substrate13. Also, since the pad47and the interconnection48of the present embodiment are formed of the same interconnection layer20, the pad47and the interconnection48can be formed in a simple manner.

As described above, the present embodiment can efficiently manufacture semiconductor chips of different types, specifically, the first and second single chips C1and C2and the dual chip C.

FIG.20is a sectional view showing a structure of a first variation of the semiconductor device of the first embodiment.

FIG.20shows a sectional view corresponding toFIG.4. The interconnection layer20of the present variation includes neither the pad47in the first single chip C1nor the interconnection (routing interconnection)48. Instead, the interconnection layer35of the present variation includes an interconnection (routing interconnection)35aconfigured to electrically connect an interconnection in the first single chip C1with an interconnection in the second single chip C2. According to the present variation, a role played by the interconnection48can be played by the interconnection35ainstead.

The routing interconnection of the present variation is provided in the circuit chip2, but may be provided in the array chip1instead.

FIG.21is a sectional view showing a structure of a second variation of the semiconductor device of the first embodiment.

FIG.21shows a sectional view corresponding toFIGS.4and20. According to the present variation, the interconnection layer20does not include the interconnection (routing interconnection)48and the interconnection layer35does not include the interconnection (routing interconnection)35aeither. According to the present variation, current and voltage are supplied to the circuits in the first single chip C1from the pad47in the first single chip C1and current and voltage are supplied to the circuits in the second single chip C2from the pad47in the second single chip C2. Therefore, the passivation film49of the present variation has an opening P not only on the pad47in the second single chip C2, but also on the pad47in the first single chip C1.

The structure of the present variation is adopted when it is known before dicing that the first single chip C1and the second single chip C2shown inFIG.21are used exclusively as single chips. However, if it is determined, after the structure shown inFIG.21is manufactured, to use the structure as the dual chip C, the pad47in the first single chip C1and the pad47in the second single chip C2may be electrically connected by a bonding wire or the like.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.