Patent ID: 12224710

DETAILED DESCRIPTION

FIG.1shows a currently well known crystal oscillator circuit10having a crystal12having an input terminal XTALIN and an output terminal XTALOUT. The circuit includes a current source18coupled to a terminal of a first current mirror transistor20—that is coupled to a second current mirror transistor22. The second current mirror transistor22supplies a current that is a multiple of the current source18to drive a transistor24. A resistor26is coupled in parallel to the crystal12. A first capacitor28is coupled between the crystal and ground or low power supply. A second capacitor30is coupled between the crystal and ground.

The transistor24provides transconductance to start and maintain oscillation of the crystal. The resistor26is a bias resistor. The first capacitor28, and the second capacitor provide harmonic resonance to maintain the crystal oscillation. An output signal is measured at the crystal output terminal XTALOUT. To maintain oscillation, the transistor24must be operated to provide negative resistance. The higher the value of gm, the more stable the oscillator circuit operates. There exists a minimum acceptable value of gm for which a crystal oscillator is stable. However, the higher the value of gm the higher the current transistor24requires, resulting in higher power consumption.

The present disclosure is directed to providing an oscillating circuit that increases the effective value of gm without increasing current consumption.

FIG.2is a low power crystal oscillator circuit210having a crystal212having an input terminal XTALIN and an output terminal XTALOUT. The circuit includes a current source218coupled to a terminal of a first current mirror transistor220which is coupled to a second current mirror transistor222by their gate terminals. The current source218will ensure that the selected current as provided by the current source passes through transistor220. In one embodiment, a current of 1.0 nA is provided by the current source218. The second current mirror transistor222supplies a current that is a multiple of the current source218to drive a transistor224. The amount of current passing through transistor222will be amplified from the current through current source218based on the ratio of the W/L of transistor222to the W/L of transistor220. By making the W/L of transistor222larger than the W/L of transistor220, the amount of current used to drive the crystal can be larger than the value of the current source218by some selected amount. In various embodiments, it might be in the range of 20 to 200 times greater. A resistor226is coupled in parallel to the crystal212. A first capacitor228is coupled between the crystal input XTALIN and a low power supply. A second capacitor230is coupled between the crystal output XTALOUT and the low power supply.

The circuit further having a third current mirror transistor32coupled to the first and second current mirror transistor220,222by sharing their gate terminals. A first startup control transistor34is coupled to the third current mirror transistor32. A second startup control transistor36is coupled to the first startup transistor34. The shared terminal between the first startup transistor34and the second startup transistor36is coupled to the crystal output XTALOUT. A fourth current mirror transistor38is coupled between the second startup transistor36and the low power supply. The gate terminal of the fourth current mirror transistor is coupled to the gate terminal of transistor224, which is also coupled to the crystal input XTALIN.

The circuit further includes a second current source40coupled to a fifth current mirror transistor42, which is coupled to a sixth current mirror transistor44by their gate terminals. The gate terminal of the sixth current mirror transistor44is coupled to the crystal input XTALIN by a third capacitor48. A third startup control transistor46is coupled between the sixth current mirror transistor44and the crystal output XTALOUT. A fourth startup control transistor56is coupled to the third startup control transistor46by both coupling to the crystal output XTALOUT. The fourth startup control transistor56is coupled to and powered by a seventh current mirror transistor54.

A gate terminal of the seventh current mirror transistor is coupled to an eighth current mirror transistor52that is coupled to a third current source50. A fourth capacitor58couples a gate terminals of the eighth current mirror transistor52and the seventh current mirror transistor54to the crystal input XTALIN of the transistor224which provides transconductance to start and maintain oscillation of the crystal. The resistor226is a bias resistor. The first capacitor228and second capacitor230provide harmonic resonance to maintain the crystal oscillation. Transistor52is biased by current source50and the value of current source50is much lower than the value of current source218that is used to start up the crystal212and start its initial operation. In one embodiment, the value of current source50is five times lower than the value of current source218, therefore, after the crystal has been started in proper operation using the larger current based on the current source218, the startup signal is disabled, which for a P-channel transistor34goes high, and the oscillation of the crystal continues based on the much lower bias current provided by current source50.

In an embodiment, the value of the width to length ratio of the second current mirror transistor222is the same as that of the first current mirror transistor220and the transistor224. That value is called X. In one embodiment, the width to length ratios of the third current mirror transistor32and the fourth current mirror transistor38are 200X. In other embodiments, it might be 300X or 400X. In some embodiments, the width to length ratio of the third current mirror32might be different from, such as larger than, the width to length ratio of the fourth current mirror transistor38. For example, in some embodiments, the ratios might be 300X and 200X respectively, but this not the standard embodiment and in most embodiments, they have the same width to length ratios. The third current mirror transistor32supplies current to maintain normal operation of the first startup control transistor34, the second startup control transistor36and the fourth current mirror transistor38. A gate terminal of the first startup control transistor34is connected to receive a startup signal STARTUP. A gate terminal of the second startup control transistor36is connected to receive an inverse startup signal STARTUPB which is the logic opposite of the startup signal STARTUP. A second terminal of the first startup control transistor34is connected to a second terminal of the second startup control transistor36. The second terminal of the first startup control transistor34and the second terminal of the second startup control transistor36are coupled with the crystal output XTALOUT.

The pair of first and second startup control transistors34and36operates as a logical switch. When startup voltage at STARTUP is at the value of logic low, the fourth current mirror transistor38is coupled to XTALOUT and provides transconductance to the crystal12in addition to the transistor224. The third current mirror transistor32is uncoupled to XTALOUT. When startup voltage at STARTUP is at the value of logic high, the fourth current mirror transistor38is uncoupled from XTALOUT and becomes inactive.

In one embodiment, the width to length ratios of the sixth current mirror transistor44and the seventh current mirror transistor54are smaller than those of the third current mirror transistor32and the fourth current mirror transistor38. In particular, the value of the width to length ratios of the sixth and seventh current mirror transistors44and54in one embodiment are both40Y. The width to length ratio of the fifth current mirror transistor42is Y.

The gate terminal of the fifth current mirror transistor42is connected to a second terminal of the fifth current mirror transistor42. The second terminal of the fifth current mirror transistor42is coupled to the second current source40. The gate terminal of the sixth current mirror transistor44is coupled to the gate terminal of the fifth current mirror transistor42. The gate terminal of the sixth current mirror transistor44is coupled to a first terminal of the third capacitor48. A second terminal of the third capacitor48connects to the crystal input terminal XTALIN. The width to length ratio of the eighth current mirror transistor52is X. The gate terminal of the eighth current mirror transistor52is connected to a second terminal of the eighth current mirror transistor52. The second terminal of the eighth current mirror transistor52is coupled to the third current source50. The gate terminal of the seventh current mirror transistor54is coupled to a first terminal of the fourth capacitor58.

A second terminal of the fourth capacitor58connects to the crystal input terminal XTALIN. A gate terminal of the third startup control transistor46is connected to receive the startup signal STARTUP. A gate terminal of the fourth startup control transistor56is connected to receive the inverse startup signal STARTUPB. A second terminal of the third startup control transistor46is connected to a second terminal of the fourth startup control transistor56. The second terminal of the fourth startup control transistor56and the second terminal of the third startup control transistor46are coupled with the crystal output XTALOUT. A third terminal of the fourth startup control transistor56is connected to a second terminal of the seventh current mirror transistor54. A third terminal of the third startup control transistor46is connected to a second terminal of the sixth current mirror transistor44.

The pair of the third and fourth startup control transistors46and56operates as a logical switch. When startup voltage at STARTUP is at the value of logic high, the sixth current mirror transistor44and the seventh current mirror transistor54are coupled to XTALOUT via the third capacitor48and the fourth capacitor58and provide extra transconductance to the crystal12. When startup voltage is at the value of logic low, the sixth current mirror transistor44and the seventh current mirror transistor54become inactive. Transconductance required for operation of the crystal12is less than that required for starting up oscillation. Transistors52and42are biased by current sources50and40, respectively. The value of these current sources50and40is much lower than the value of current source218that is used to start up the crystal212and start its initial operation. Therefore, much lower power is expended to drive the crystal212after the startup phase.

In one embodiment, the value of current sources40and50is five times lower than the value of current source218, therefore, after the crystal has been started in proper operation using the larger current based on the current source218, the startup signal is disabled, which for a P-channel transistor34goes high, and the oscillation of the crystal continues based on the much lower bias current provided by current sources40and50.

In some embodiments, but not in all, another way of using lower power to drive the crystal212after start up can be achieved. In these other embodiments, the ratio of the W/L of the seventh current mirror transistor54to the W/L of transistor52can be less than the ratio of the W/L of transistor32to the transistor220. Similarly, the ratio of the W/L of the sixth current mirror transistor44to the W/L of transistor42can be less than the ratio of the W/L of transistor32to the transistor220. Therefore the bias current provided by current source50(and current source40, if present) is not amplified as much as the bias current provided by current source218. In some embodiments, this can be another design choice to cause the current consumption to be less when the crystal oscillator circuit210operates after startup mode ends.

Transconductance is only required for an AC signal during oscillation. The sixth current mirror transistor44and the seventh current mirror transistor54are DC-isolated by the third capacitor48and the fourth capacitor58, which further reduces the voltage, and therefore the power consumption of the crystal after start up.

As noted above, in one embodiment the first current source218supplies a current of 1.0 nA and the second and third current source40and50each supply a current of 0.2 nA.

FIG.3is another embodiment of a low power crystal oscillator circuit310that includes a crystal312coupled between an input XTALIN and an output XTALOUT. A first transistor324is coupled between XTALOUT and a low power supply, which may be a ground. A resistor326is coupled in parallel between the input and output of the crystal312. A first capacitor328is coupled between the crystal input XTALIN and the low power supply. A second capacitor330is coupled between the crystal output XTALOUT and the low power supply. A gate terminal of the first transistor324is coupled to the crystal input. The first transistor324provides transconductance to the crystal312during operation of the oscillator circuit.

A first current source318is coupled to provide the bias current for a first current mirror transistor320. A gate terminal of the first current mirror transistor320is coupled to a second terminal of the first current mirror transistor320. The gate terminal of the first current mirror transistor320is coupled to a gate terminal of a second current mirror transistor322. A second terminal of the second current mirror transistor is coupled to the crystal output and a second terminal of the first transistor324. The second current mirror transistor322provides a current that is a multiple of that of the first current source318to provide power and maintain operation of the first transistor324and aid to drive the crystal312in the startup mode when it begins its oscillation.

A third current mirror transistor332is also coupled to the first current mirror transistor320. A gate terminal of the third current mirror transistor332is coupled to the gate terminal of the second current mirror transistor322. A first startup control transistor334is coupled to the third current mirror transistor332. A gate terminal of the first startup control transistor is coupled to receive a startup signal STARTUP. A first terminal of the first startup control transistor is coupled to a first terminal of the third current mirror transistor332. A second terminal of the first startup control transistor334is coupled to the crystal output XTALOUT. The third current mirror transistor332provides a current that is a multiple of the current supplied by the first current mirror transistor320to provide power to the first startup control transistor334.

A second current source350is coupled to provide the bias current for a fourth current mirror transistor352. A gate terminal of the fourth current mirror transistor is coupled to a first terminal of the fourth current mirror transistor352. The first terminal of the fourth current mirror transistor352is coupled to a terminal of the second current source350. The gate terminal of the fourth current mirror transistor352is coupled to a gate terminal of a fifth current mirror transistor354. A first terminal of the fifth current mirror transistor is coupled to a first terminal of a second startup control transistor356. A second terminal of the second startup control transistor356is coupled to the crystal output XTALOUT. A gate terminal of the second startup control transistor is coupled to receive an inverse startup signal STARTUPB which is the logical opposite of the startup signal STARTUP.

A third capacitor358couples the gate terminals of the fourth and fifth current mirror transistors352and354to the crystal input XTALIN.

The first and second startup control transistors334and356work as logical switches. When the startup signal STARTUP has a voltage of logic low, meaning the inverse startup signal STARTUPB ha a voltage of logic high, the third current mirror transistor is coupled to the crystal output XTALOUT and provides transconductance in addition to the transconductance supplied by the first transistor324. When the startup signal STARTUP has a value of logic high, meaning the inverse startup signal STARTUPB has a voltage of logic low, the third current mirror transistor332is uncoupled from the crystal output XTALOUT and the fifth current mirror transistor354is coupled to the crystal output XTALOUT to provide transconductance.

In one embodiment, the width to length ratio of the first and second current mirror transistor322and332has the value of X. The width to length ratio of the third current mirror transistor332has the value of 200X. This means that the third current mirror transistor332carries a current 200 times that of the first current source318. The fourth current mirror transistor352has a width to length ratio of X and the fifth current mirror transistor354has a width to length ratio of 40X, which is smaller than that of the third current mirror transistor. In one embodiment, the first current source318supplies a current of 1.0 nA and the second current source350supplies a current of 0.2 nA.

The transconductance required for operation of the crystal312is less than that required for starting up oscillation. Having a smaller width to length ratio means that current consumption is less to operate the fifth current mirror transistor354than the third current mirror transistor332. The crystal oscillator circuit can initialize oscillation at startup with higher power consumption and maintain low power consumption after startup.

Transconductance is only required for an AC signal during oscillation. The fifth current mirror transistor354are DC-isolated by the third capacitor358, which further reduces power consumption required for DC gain on the fifth current mirror transistor354.

FIG.4Ashows the voltage level of the startup signal with respect to time. Startup is initially at logic low. At 18 ms, startup is set to logic high.

FIG.4Bshows the voltage measured at the crystal input node XTALIN with respect to time. The crystal212starts oscillating once power is applied. Oscillation is stable by about 8 ms and remains fully stable for another 10 ms, until at about 18 ms the startup signal is disable, as this circuit is brought to logic high level. At time, the current used the drive the crystal212is provide based on the current source50in the embodiment ofFIG.2or the current source350in the embodiment ofFIG.3. The current sources218and318ofFIGS.2and3, respectively, are turned off and the total current consumed by the crystal is much lower. The amount of current consumed is now based on the current source50(or350), which is much lower than the value of the current source218(or318). By driving the crystal212(or312) based on a lower biasing current from a different current source after start up and shutting off the startup current source and it associate current mirror, substantial power is saved.

The voltage at XTALIN also reduces as the circuit transitions to operate with low power. The circuit reaches stable oscillation with a reduced voltage around 35 ms at the lower voltage, as can be seen inFIGS.4B and4C. In preferred embodiments, the voltage output at long term stable operation is half the voltage at start-up. This can be seen by looking at the relative reduction in voltage inFIGS.4B and4Cfrom startup to after the startup is completed.FIG.4Cshows the voltage measured at the crystal input node XTALOUT with respect to time. Similar toFIG.4B, the voltage output is high at startup. Once the startup signal is brought to logic high, the output voltage at XTALOUT reduced as the crystal oscillator circuit transitions to stable operation with low power.

The power consumed by a circuit is a multiple of the current and voltage, P=IV. Since the current is greatly reduced after start up and the voltage is also reduced, the total power is significantly reduced. In one embodiment, the current consumed by the crystal circuit during the standard operation mode, after startup, is reduced by 20 to 25 times the current used during the startup mode. Further, the voltage is reduced by about half, so the total power consumed will be in the range of 40 to 50 times less during standard operation mode than in startup mode. In other embodiments, the reduction in power can be two orders of magnitude, namely about 100 times from the startup mode to standard operation mode. This can be obtained based on the selection of value of the current sources used to bias the circuit during start up as compared to the value of the current source used to bias the circuit during standard operation mode, together with selection of the relative transistor ratios of transistors in the respective current mirrors.

FIG.4D1shows the current consumption of the embodiment presented inFIG.3. Initially the current consumption is around 1.0 nA. Once startup is brought to high, transistor332shuts off and the circuit switches to low power mode, operating with transistor354, consuming only 0.4 nA.

FIG.4D2shows the current consumption of the embodiment presented inFIG.2. Initially the current consumption is around 1.0 nA. Once startup is brought to high, transistor32and transistor38shut off and the circuit switches to low power mode, operating with transistor44and transistor54, consuming only 0.2 nA.

FIG.4Eshows a typical power consumption of the low power crystal oscillator circuit presented in this application. The stable operation power consumption is 100 times less than the startup power consumption.

FIG.5shows a flow chart500of the various phases a low power crystal oscillator circuit operates. At a step510, a startup signal is set with a voltage level of logic low. At a step512, the crystal oscillator circuit operates using high power. At a step514, the crystal reaches stable oscillation. At a step516, the startup phase ends and the startup signal is set to a voltage level of logic high. At a step518, the crystal oscillator transitions to use very low power to maintain operation.

FIG.6shows a schematic block diagram of a low power crystal oscillator circuit600according to the present disclosure. A crystal612is coupled to a switch614. The switch614couples the crystal612to a high power circuit618or a low power circuit620. The low power circuit620is also coupled to the crystal612by a capacitor616. The high power circuit618and low power circuit620are configured to provide transconductance for the operation of the oscillator circuit. The capacitor616further DC-isolates the low power circuit620during operation of the oscillator.

In one embodiment the switch614comprises a plurality of startup control transistors which are configured to receive a startup signal and an inverse startup signal. In one embodiment, the high power circuit618and the low power circuit620utilize current mirror transistors of different width to length ratios to regulate power consumption. In one embodiment, the low power circuit620is DC coupled to the crystal612by the switch614, but also AC coupled to the crystal612by capacitor616.

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.