Patent ID: 12218096

DETAILED DESCRIPTION

Hereinafter, terms used to distinguish the components of the semiconductor package from each other may be replaced with other terms with reference to the drawings. For example, terms such as “upper” and “lower” or terms such as “front” and “rear” may be replaced with other terms, for example, “first” and “second”, or the like to be used to describe elements. Terms such as “first” and “second” may be used to describe various elements, but the elements are not limited by the terms, and “first element” may be referred to as “second element”. In addition, terms such as ‘top’, ‘upper portion’, ‘upper surface’, ‘bottom’, ‘lower portion’, ‘lower surface’, and ‘side surface’ in the following can be understood as being referred based on the drawings, except in cases indicated by reference numerals and designated separately.

FIG.1is a plan view illustrating an example of a semiconductor package according to an exemplary embodiment, andFIG.2is a cross-sectional view illustrating an example of a semiconductor package according to an exemplary embodiment.FIG.2is a cross-sectional view illustrating a partial region ofFIG.1, for example, a region taken along line I-I′.

Referring toFIGS.1and2, a semiconductor package according to an exemplary embodiment may include a semiconductor chip3. The semiconductor chip3has a front side5S1and a back side5S2opposing each other, and may include a semiconductor substrate5having a chip area CA and a dummy area DA surrounding the chip area CA.

The semiconductor substrate5may be a silicon substrate. However, exemplary embodiments are not limited thereto. For example, the semiconductor substrate5may include a group IV semiconductor formed of a material such as germanium or silicon-germanium, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

The semiconductor chip3may further include a front structure FS below the front side5S1of the semiconductor substrate5, and a rear structure BS on the back side5S2of the semiconductor substrate5.

The front structure FS may include an internal circuit10, a guard pattern30, an internal connection pattern20, and a front insulating structure40, below the front side5S1of the semiconductor substrate5.

The internal circuit10and the internal connection pattern20may be disposed below the chip area CA of the semiconductor substrate5. The guard pattern30may be disposed below the chip area CA of the semiconductor substrate5adjacent to the dummy area DA.

The guard pattern30may include a first guard layer29a, intermediate guard layers29bbelow the first guard layer29a, and a second guard layer29cbelow the intermediate guard layers29b. The intermediate guard layers29bmay include a plurality of layers positioned at different height levels, between the first guard layer29aand the second guard layer29c. The guard pattern30may be formed of a conductive material.

The guard pattern30may have a ring shape surrounding the internal circuit10and the internal connection pattern20. The guard pattern30may serve to prevent moisture from entering from the side surface of the semiconductor chip3or to protect the chip area CA in the semiconductor chip3from cracks occurring during a sawing process for separating a plurality of semiconductor chips from a single semiconductor wafer.

The dummy area DA may serve to protect the chip area CA in the semiconductor chip3from cracks occurring during a sawing process for separating a plurality of semiconductor chips from one semiconductor wafer, together with the guard pattern30.

The internal circuit10may include a semiconductor integrated circuit such as a transistor including a gate9aand a source/drain9b.

The internal connection pattern20may include a first connection layer19a, intermediate connection layers19bbelow the first connection layer19a, and a second connection layer19cbelow the intermediate insulating layers19b. The intermediate insulating layers19bmay include a plurality of layers positioned at different height levels, between the first connection layer19aand the second connection layer19c. The internal connection pattern20may be formed of a conductive material.

At least a portion of the internal circuit10and at least a portion of the internal connection pattern20may be disposed in the front insulating structure40. At least a portion of the internal circuit10and at least a portion of the internal connection pattern20may be buried in the front insulating structure40.

The front structure FS may further include a front protective layer45below the front insulating structure40. The front protective layer45may be formed of an insulating material.

The rear structure BS may be disposed on the back side5S2of the semiconductor substrate5, to include a rear protective layer70overlapping the chip area CA and the dummy area DA and a rear protrusion pattern80disposed over the rear protective layer70and overlapping the dummy area DA.

As an example, the rear protective layer70may be formed as a single layer formed of silicon oxide. In another example, the rear protective layer70may be formed of multiple layers including different materials (e.g., silicon oxide and silicon nitride). In another example, the rear protective layer70may include a polymer material such as polyimide.

The back side5S2of the semiconductor substrate5may be substantially flat.

The rear protrusion pattern80may have a flat upper surface substantially parallel to the back side5S2of the semiconductor substrate5.

As an example, the rear protrusion pattern80may be formed as a single layer. For example, the rear protrusion pattern80may include an insulating material such as silicon oxide or silicon nitride, or a polymer material such as polyimide.

In another example, the rear protrusion pattern80may include at least two insulating material layers79aand79bsequentially stacked. For example, the rear protrusion pattern80may include a first insulating material layer79aand a second insulating material layer79bsequentially stacked. From the at least two insulating material layers79aand79bof the rear protrusion pattern80, the first insulating material layer79ain contact with the rear protective layer70may include a material different from that of the rear protective layer70in contact with the rear protrusion pattern80.

The first insulating material layer79aand the second insulating material layer79bmay include different materials. For example, the first insulating material layer79amay include silicon nitride, and the second insulating material layer79bmay include silicon oxide.

The semiconductor chip3may further include a through-electrode structure75that penetrates through the chip area CA of the semiconductor substrate5and the rear protective layer70and that is electrically connected to the internal connection pattern20of the front structure FS. The through-electrode structure75may include a through-electrode75band an insulating spacer75acovering at least a side surface of the through-electrode75b.

The semiconductor chip3may further include a front bump60penetrating through the front protective layer45, electrically connected to the internal connection pattern20and extending to a lower portion of the front protective layer45.

The semiconductor chip3may further include a connection pattern65electrically connected to the front bump60and disposed below the front bump60. The connection pattern65may include a solder material.

The semiconductor chip3may further include a rear pad85electrically connected to the through-electrode structure75, on the rear protective layer70, and the through-electrode structure75, and spaced apart from the rear protrusion pattern80.

The rear pad85may include a first rear layer84aand a second rear layer84bon the first rear layer84a.

As an example, the thickness of the semiconductor substrate5may be in a range of about 25 μm to about 100 μm.

As an example, a thickness Ta of the rear pad85may be in a range of about 2 μm to about 5 μm.

As an example, the thickness Ta of the rear pad85may be twice or more than the thickness of the rear protective layer70.

As an example, the thickness of the rear structure BS may be about 4 μm or less. For example, the thickness of the rear structure BS may be about 3.15 μm.

As an example, the rear protective layer70may have a thickness of about 1 μm or less. For example, the rear protective layer70may have a thickness of about 0.6 μm.

As an example, a thickness Tb of the rear protrusion pattern80may be in a range of about 1 μm to about 4 μm. The rear protrusion pattern80may form a step difference of about 1 μm to about 4 μm with the rear protective layer70.

As an example, in the rear protrusion pattern80, the first insulating material layer79amay be thicker than the second insulating material layer79b. The first insulating material layer79aof the rear protrusion pattern80may have a thickness of about 1.58 μm, and the second insulating material layer79bmay have a thickness of about 0.97 μm, but the exemplary embodiments thereof are not limited to the numerical values given above.

As an exemplary embodiment, the semiconductor chip3may be adhered to another component below the back side5S2of the semiconductor chip3by an adhesive material layer, thereby forming a semiconductor package. In such case, the rear protrusion pattern80may contact the adhesive material layer, and may serve to prevent the adhesive material layer from excessively protruding to the outside of the semiconductor chip3due to overflow. An example of the role of the rear protrusion pattern80will be described again with reference toFIGS.8A and8B.

InFIG.2, the thickness Ta of the rear pad85is illustrated to be substantially the same as the thickness Tb of the rear protrusion pattern80, but the exemplary embodiment is not limited thereto. Hereinafter, modified examples of the thickness Ta of the rear pad85and the thickness Tb of the rear protrusion pattern80ofFIG.2will be described with reference toFIGS.3A and3B, respectively.FIGS.3A and3Bare cross-sectional views illustrating modifications of the thickness Ta of the rear pad85and the thickness Tb of the rear protrusion pattern80in the cross-sectional view ofFIG.2, respectively.

In a modified example, referring toFIG.3A, a semiconductor chip3bmay include a rear protrusion pattern80ahaving a thickness Tb greater than the thickness Tal of the rear pad85. For example, the rear protrusion pattern80ofFIG.2may be replaced with the rear protrusion pattern80aofFIG.3A.

In a modified example, referring toFIG.3B, a semiconductor chip3cmay include a rear protrusion pattern80bhaving a thickness Tb2greater than the thickness Ta of the rear pad85. For example, the rear protrusion pattern80ofFIG.2may be replaced with the rear protrusion pattern80bofFIG.3B.

Next, with reference toFIGS.4A and4B, respectively, modifications of the rear protrusion pattern80described with reference toFIG.2will be described.FIGS.4A and4Bare cross-sectional views respectively illustrating modifications of the rear protrusion pattern80illustrated in the cross-sectional view ofFIG.2.

In a modified example, referring toFIG.4A, a semiconductor chip3dmay include a rear protrusion pattern80cthat may replace the rear protrusion pattern80ofFIG.2. The rear protrusion pattern80cmay extend from a portion positioned in the dummy area DA onto the chip area CA to vertically overlap the guard pattern30.

In a modified example, referring toFIG.4B, the semiconductor chip3dmay include a rear protrusion pattern80dthat may replace the rear protrusion pattern80ofFIG.2. The rear protrusion pattern80dmay include a first portion80d_1positioned on the dummy area DA, and a second portion80d_2vertically overlapping a portion of the internal circuit10in the chip area CA.

Next, a modified example of the semiconductor chip3described with reference toFIG.2will be described with reference toFIG.5.FIG.5is a cross-sectional view illustrating a modified example of the semiconductor chip3described inFIG.2.

In a modified example, referring toFIG.5, a semiconductor chip3emay include a front structure FS further including chipping dams33. For example, the semiconductor chip3emay further include the chipping dams33as compared to the semiconductor chip3ofFIG.2.

The chipping dams33may be disposed in the front insulating structure40, below the dummy area DA of the semiconductor substrate5.

The chipping dams33may be disposed spaced apart from each other on the outside of a ring-shaped guard pattern30.

The dummy area DA and the chipping dams33may serve to protect the chip area CA in the semiconductor chip3from cracks occurring during a sawing process for separating a plurality of semiconductor chips from one semiconductor wafer.

The chipping dams33may include a first dam layer32a, intermediate dam layers32bbelow the first dam layer32a, and a second dam layer32cbelow the intermediate dam layers32b. The intermediate dam layers32bmay include a plurality of layers positioned at different height levels between the first dam layer32aand the second dam layer32c. The chipping dams33may be formed of a conductive material.

Next, modified examples of the rear protrusion pattern80described inFIG.1will be described with reference toFIGS.6A and6B, respectively.FIGS.6A and6Bare plan views illustrating modifications of the rear protrusion pattern80described above referring to the plan view ofFIG.1, respectively.

In a modified example, referring toFIG.6A, the semiconductor chip3eexample may include a rear protrusion pattern80ethat may replace the rear protrusion pattern80inFIG.1. The rear protrusion pattern80emay include a first portion80e_1overlapping the dummy area DA, and a second portion80e_2overlapping the chip area CA.

The first portion80e_1may have a ring shape. The second portion80e_2may extend from the first portion80e_1.

In an exemplary embodiment, the second portion80e_2is not limited to the shape illustrated inFIG.6A. For example, the second portion80e_2may be formed to be spaced apart from the first portion80e_1.

In a modified example, referring toFIG.6B, a semiconductor chip3gmay include a rear protrusion pattern80fthat may replace the rear protrusion pattern80inFIG.1.

The rear protrusion pattern80fmay include a plurality of first portions80f_1overlapping the dummy area DA and spaced apart from each other. In the dummy area DA, the rear protective layer70, not covered by the first portions80f_1, may be exposed.

The rear protrusion pattern80fmay further include a second portion80e_2overlapping the chip area CA. The second portion80f_2may extend from the first portions80f_1, but exemplary embodiments are not limited thereto. For example, the second portion80f_2may be formed to be spaced apart from at least one of the first portions80f_1.

Next, a modified example of the semiconductor chip3described with reference toFIG.2will be described with reference toFIG.7.FIG.7is a cross-sectional view illustrating a modified example of the semiconductor chip3described inFIG.2.

In a modified example, referring toFIG.7, a semiconductor chip3hmay include a front structure FS further including a front protrusion pattern47. For example, the semiconductor chip3hmay further include a front protrusion pattern47compared to the semiconductor chip3ofFIG.2.

The front protrusion pattern47may contact the front protective layer45, below the front protective layer45. The front protrusion pattern47may vertically overlap the dummy area DA of the semiconductor substrate5. At least a portion of the front protrusion pattern47may vertically overlap at least a portion of the rear protrusion pattern80.

The front protrusion pattern47may be formed of an insulating material. The front protrusion pattern47may be formed as a single layer or in multiple layers.

In an exemplary embodiment, the semiconductor chip3may be adhered to another component below the front side5S1of the semiconductor chip3by an adhesive material layer, thereby constituting a semiconductor package. In this case, the front protrusion pattern47may contact the adhesive material layer, and may serve to prevent the adhesive material layer from excessively protruding out of the semiconductor chip3. An example of the role of the front protrusion pattern47will be described again with reference toFIGS.10A and10B.

Next, an example of a semiconductor package according to an exemplary embodiment will be described with reference toFIGS.8A and8B.FIG.8Ais a cross-sectional view illustrating an example of a semiconductor package according to an exemplary embodiment, andFIG.8Bis a partially enlarged view of an area indicated by ‘A’ ofFIG.8A.

Referring toFIGS.8A and8B, a semiconductor package1aaccording to an exemplary embodiment may include a base203, a plurality of semiconductor chips103a,103b,103cand103d, connection patterns165a,165b,165cand165d, adhesive material layers190a,190b,190cand190d, and a mold layer195.

The plurality of semiconductor chips103a,103b,103c, and103dmay be vertically stacked on the base203.

The plurality of semiconductor chips103a,103b,103c, and103dare illustrated as including four semiconductor chips, but exemplary embodiments are not limited thereto. For example, the plurality of semiconductor chips may include fewer than four semiconductor chips or may include more than four semiconductor chips.

Although the plurality of semiconductor chips103a,103b,103c, and103dare illustrated as having the same shape, exemplary embodiments are not limited thereto. For example, the plurality of semiconductor chips103a,103b,103c, and103dmay include different types of semiconductor chips or semiconductor chips having different shapes.

The plurality of semiconductor chips103a,103b,103c, and103dmay include a first semiconductor chip103a, a second semiconductor chip103b, a third semiconductor chip103c, and a fourth semiconductor chip103dthat are sequentially stacked.

The connection patterns165a,165b,165c, and165dmay include a first connection pattern165aelectrically connecting the first semiconductor chip103aand the base203, between the first semiconductor chip103aand the base203, a second connection pattern165belectrically connecting the first semiconductor chip103aand the second semiconductor chip103b, between the first semiconductor chip103aand the second semiconductor chip103b, a third connection pattern165celectrically connecting the second semiconductor chip103band the third semiconductor chip103c, between the second semiconductor chip103band the third semiconductor chip103c, and a fourth connection pattern165delectrically connecting the third semiconductor chip103cand the fourth semiconductor chip103c, between the third semiconductor chip103cand the fourth semiconductor chip103d. The connection patterns165a,165b,165c, and165dmay include a solder material.

The adhesive material layers190a,190b,190cand190dmay include a first adhesive material layer190afilling between the first semiconductor chip103aand the base203and surrounding a side surface of the first connection pattern165a, a second adhesive material layer190bfilling between the first semiconductor chip103aand the second semiconductor chip103band surrounding a side surface of the second connection pattern165b, a third adhesive material layer190cfilling between the second semiconductor chip103band the third semiconductor chip103cand surrounding a side surface of the third connection pattern165c, and a fourth adhesive material layer190dfilling between the third semiconductor chip103cand the fourth semiconductor chip103cand surrounding a side surface of the fourth connection pattern165d.

The adhesive material layers190a,190b,190c, and190dmay cover side surfaces of the plurality of semiconductor chips103a,103b,103c, and103d, and may be connected to each other on the side surfaces of the plurality of semiconductor chips103a,103b,103c, and103d.

The adhesive material layers190a,190b,190c, and190dmay be non-conductive material layers formed of an epoxy-based material. For example, the adhesive material layers190a,190b,190c, and190dmay be a non-conductive film (NCF), however, this exemplary embodiment is not limited thereto.

At least one of the plurality of semiconductor chips103a,103b,103c, and103dmay have a structure substantially the same as or similar to that of the semiconductor chip3described with reference toFIGS.1and2. For example, each of the first to fourth semiconductor chips103a,103b,103c, and103dmay include the front structure FS described with reference toFIGS.1and2. For example, in each of the first to third semiconductor chips103a,103b, and103c, the front structure FS may include an internal circuit110, a guard pattern130, an internal connection pattern120, a front insulating structure140, and a front protective layer145corresponding to the internal circuit10, the guard pattern30, the internal connection pattern20, the front insulating structure40, and the front protective layer45described with reference toFIG.2, respectively.

Each of the first to third semiconductor chips103a,103b, and103cmay further include the front structure FS and the rear structure BS described with reference toFIGS.1and2. The rear structure BS may include a rear protective layer170and a rear protrusion pattern180corresponding to the rear protective layer70and the rear protrusion pattern80described with reference toFIG.2, respectively.

Each of the first to fourth semiconductor chips103a,103b,103cand103dmay further include a semiconductor substrate105, a front protective layer170, and a front bump160corresponding to the semiconductor substrate5, the front protective layer70and the front bump60described with reference toFIGS.1and2, respectively.

Each of the first to third semiconductor chips103a,103b, and103cmay further include a through-electrode structure175and a rear pad185corresponding to the through-electrode structure75and the rear pad85described with reference toFIGS.1and2, respectively.

In some exemplary embodiments, each of the plurality of semiconductor chips103a,103b,103c, and103dmay include a chip area CA and a dummy area DA similarly to those described with reference toFIGS.1and2.

In exemplary embodiments, to distinguish the components of the first to fourth semiconductor chips103a,103b,103c, and103dfrom each other, the components of the first semiconductor chip103amay be described as first components. In addition, components of the second semiconductor chip103bmay be described as second components, and components of the third semiconductor chip103cmay be described as third components. For example, in the first semiconductor chip103a, the front structure FS, the rear structure BS, the semiconductor substrate105, the through-electrode structure175, the front protective layer170, the front bump160and the rear pad185may be referred to and described as a first front structure FS, a first rear structure BS, a first semiconductor substrate105, a first through-electrode structure175, a first front protective layer170, a first front bump160, and a first rear pad185, respectively, and in the second semiconductor chip103b, the front structure FS, the rear structure BS, the semiconductor substrate105, the through-electrode structure175, the front protective layer170, the front bump160, and the rear pad185may be referred to as and described as a second front structure FS, a second rear structure BS, a second semiconductor substrate105, a second through-electrode structure175, a second front protective layer170, a second front bump160, and a second rear pad185, respectively.

In an exemplary embodiment, due to the rear protrusion pattern180of the first semiconductor chip103ahaving a stepped and protruding shape, the space between the chip area CA of the first semiconductor chip103aand the chip area CA of the second semiconductor chip103bmay be sufficiently secured, and the second adhesive material layer190bfilling the secured space between the chip area CA of the first semiconductor chip103aand the chip area CA of the second semiconductor chip103bmay be stably and reliably formed without excessively protruding to out of the first and second semiconductor chips103aand103b. The rear protrusion patterns180of the second and third semiconductor chips103band103cand the upper protrusion pattern280of the base203may serve substantially the same function as the rear protrusion pattern180of the first semiconductor chip103a. Accordingly, the rear protrusion patterns180of the first to third semiconductor chips103a,103band103cmay prevent the second to fourth adhesive material layers190b,190cand190dfrom excessively protruding out of the first to fourth semiconductor chips103a,103b,103cand103ddue to overflow. In addition, the upper protrusion pattern280of the base203may prevent the first adhesive material layer190afrom excessively protruding out of the first semiconductor chip103adue to overflow. In addition, due to the rear protrusion patterns180of the first to third semiconductor chips103a,103band103cand the upper protrusion pattern280of the base203, the adhesive material layers190a,190b,190c, and190dmay be formed stably and reliably.

The base203may be a buffer semiconductor chip or a logic semiconductor chip. The base203may have a greater width or a larger size than each of the plurality of semiconductor chips103a,103b,103c, and103d.

The base203may include a chip body205, a lower protective layer245disposed on a lower surface of the chip body205, an upper protective layer270disposed on an upper surface of the chip body205, an upper protrusion pattern280vertically overlapping the rear protrusion pattern180, on the upper protective layer270and extending to a region not overlapping the plurality of semiconductor chips103a,103b,103c, and103d.

The upper protrusion pattern280may include a first layer279aand a second layer279bthat are sequentially stacked. However, the exemplary embodiment is not limited thereto. For example, the upper protrusion pattern280may be formed as a single layer. The upper protrusion pattern280may be formed of an insulating material.

The base203may further include a through-electrode structure275penetrating through at least a portion of the chip body205and the upper protective layer270, an upper pad285electrically connected to the through-electrode structure275, on the upper protective layer270, and a lower bump260penetrating through the lower protective layer245, extending downwardly of the lower protective layer245and electrically connected to the through-electrode structure275.

The semiconductor package1amay further include a lower connection pattern265contacting the lower bump260, below the base203.

In exemplary embodiments, the rear protrusion pattern180may be replaced with rear protrusion patterns (80ainFIG.3A,80binFIG.3B,80cinFIG.4A,80dinFIG.4B,80einFIG.6A,80finFIG.6B).

At least one of the plurality of semiconductor chips103a,103b,103c, and103dmay be a memory semiconductor chip such as a DRAM, or a memory semiconductor chip such as a NAND flash. The types of the plurality of semiconductor chips103a,103b,103c, and103dare not limited to the aforementioned DRAM or NAND flash. For example, at least one of the plurality of semiconductor chips103a,103b,103c, and103dmay be a PRAM, a resistive change memory (ReRAM), or a magnetoresistive memory (MRAM).

The plurality of semiconductor chips103a,103b,103c, and103dmay be semiconductor chips of the same type, for example, a memory semiconductor chip such as a DRAM.

The plurality of semiconductor chips103a,103b,103c, and103dmay include different types of semiconductor chips. For example, any one of the plurality of semiconductor chips103a,103b,103c, and103dmay be a logic semiconductor chip or a processor chip, and one or a plurality of the other chips may be a memory semiconductor chip. For example, the plurality of semiconductor chips103a,103b,103c, and103dmay include a chip that may be a logic semiconductor chip or a processor chip, and one or a plurality of memory semiconductor chips that are disposed on the lower chip.

Next, a modified example of the semiconductor package according to an exemplary embodiment will be described with reference toFIGS.9A and9B.FIG.9Ais a cross-sectional view illustrating a modified example of a semiconductor package according to an exemplary embodiment, andFIG.9Bis a partially enlarged view of an area indicated by ‘B’ inFIG.9A.

In a modified example, referring toFIGS.9A and9B, a semiconductor package1bmay further include chipping dams133as compared to the semiconductor package1adescribed inFIGS.8A and8B. For example, in the semiconductor package1b, the chipping dams133may be disposed in the front insulating structure140of each of the plurality of semiconductor chips103a,103b,103c, and103ddescribed with reference toFIGS.8A and8B. The chipping dams133disposed in each of the plurality of semiconductor chips103a,103b,103c, and103dmay be substantially the same as the chipping dams33described with reference toFIG.5.

Next, a modified example of the semiconductor package according to an exemplary embodiment will be described with reference toFIGS.10A and10B.FIG.10Ais a cross-sectional view illustrating a modified example of a semiconductor package according to an exemplary embodiment, andFIG.10Bis a partially enlarged view of an area indicated by ‘C’ inFIG.10A.

In a modified example, referring toFIGS.10A and10B, a semiconductor package1cin the modified example may further include a front protrusion pattern147as compared to the semiconductor package1adescribed inFIGS.8A and8B. For example, in the semiconductor package1c, the front protrusion pattern147may be disposed below the front protective layer145of each of the plurality of semiconductor chips103a,103b,103c, and103ddescribed with reference toFIGS.8A and8B. The front protrusion pattern147disposed in each of the plurality of semiconductor chips103a,103b,103c, and103dmay be substantially the same as the front protrusion pattern47described with reference toFIG.7.

In an exemplary embodiment, the front protrusion pattern147disposed in each of the plurality of semiconductor chips103a,103b,103c, and103dand having a stepped and protruding shape may perform substantially the same function as the rear protrusion patterns180described with reference toFIGS.8A and8B. For example, the front protrusion pattern147disposed in each of the plurality of semiconductor chips103a,103b,103c, and103dmay prevent the first to fourth adhesive material layers190a,190b,190c, and190dfrom excessively protruding out of the first to fourth semiconductor chips103a,103b,103c, and103d.

Next, an example of a semiconductor package according to an exemplary embodiment will be described with reference toFIGS.11A to11C.FIG.11Ais a plan view illustrating an example of a semiconductor package according to an exemplary embodiment,FIG.11Bis a cross-sectional view taken along line II-II′ ofFIG.11A, andFIG.11Cis a cross-sectional view illustrating partial configurations ofFIG.11B.

Referring toFIGS.11A to11C, a semiconductor package1000according to an exemplary embodiment may include a package substrate500, an interposer600, and at least one memory structure300. Also, the semiconductor package1000may further include a logic chip or a processor chip400disposed adjacent to the memory structure300, on the interposer600. The memory structure300may be one of the semiconductor packages1a,1b, and1cdescribed with reference toFIGS.9A to11C. For example, the memory structure300may be the semiconductor package1adescribed with reference toFIGS.9A and9B.

In some exemplary embodiments, the memory structure300may be referred to and described as a first chip structure, a stacked chip structure, or a first semiconductor package, and the logic chip or processor chip400may be referred to as and described as a second chip structure or a second semiconductor package, and hereinafter, may be referred to and described as the logic chip400.

The package substrate500may include a lower pad512disposed on a lower surface of a body, an upper pad511disposed on an upper surface of the body, and a redistribution circuit513electrically connecting the lower pad512and the upper pad511. The package substrate500may be a support substrate on which the interposer600, the logic chip400, and the memory structure300are mounted, and may be a substrate for a semiconductor package, including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, or the like.

The body of the package substrate500may include different materials depending on the type of the substrate. For example, when the package substrate500is a printed circuit board, the body of the package substrate500may have a form in which a wiring layer is additionally laminated on one side or both sides of a body copper clad laminate or a copper clad laminate. A solder resist layer may be formed on a lower surface and an upper surface of the package substrate500, respectively. The lower and upper pads512and511and the redistribution circuit513may form an electrical path connecting a lower surface and an upper surface of the package substrate500. The lower and upper pads512and511and the redistribution circuit513may include a metallic material, for example, at least one of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C), or an alloy including two or more metals. The redistribution circuit513may include multiple redistribution layers and vias connecting the multiple redistribution layers. An external connection terminal520connected to the lower pad512may be disposed on a lower surface of the package substrate500. The external connection terminal520may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and/or or an alloy thereof.

The interposer600may include a substrate601, a lower protective layer603, a lower pad605, an interconnection structure610, a bump620, and a through-electrode630. The interconnection structure610may be referred to as a wiring structure. The memory structure300and the logic chip400may be stacked on the package substrate500via the interposer600. The interposer600may electrically connect the memory structure300and the logic chip400to each other. In the interposer600, the substrate601may be formed of, for example, any one of silicon, an organic material, a plastic, and a glass substrate. For example, when the substrate601is a silicon substrate, the interposer600may be referred to as a silicon interposer. In the interposer600, for example, when the substrate601is an organic substrate, the interposer600may be referred to as a panel interposer. The lower protective layer603may be disposed on the lower surface of the substrate601, and the lower pad605may be disposed below the lower protective layer603. The lower pad605may be connected to the through-electrode630. The memory structure300and the logic chip400may be electrically connected to the package substrate500through the bumps620disposed below the lower pad605.

The interconnection structure610is disposed on the upper surface of the substrate601and may include an insulating layer611and a single-layer or multilayer interconnection structure612. For example, when the interconnection structure610has a multilayer interconnection structure, wirings on different layers may be connected to each other through vertical contacts.

The through-electrode630may extend from an upper surface to a lower surface of the substrate601to penetrate through the substrate601. The through-electrode630may extend into the interconnection structure610to be electrically connected to wirings of the interconnection structure610. In the case in which the substrate601is formed of silicon, the through-electrode630may be referred to as a TSV. According to an exemplary embodiment, the interposer600may include only a wiring layer therein, but may not include a through-electrode.

The interposer600may be used for converting or transferring an input electrical signal, between the package substrate500and the memory structure300or the logic chip400. Accordingly, the interposer600may not include elements such as active elements or passive elements. Also, according to an exemplary embodiment, the interconnection structure610may be disposed below the through-electrode630. For example, the positional relationship between the interconnection structure610and the through-electrode630may be relative.

The bump620may be disposed on the lower surface of the interposer600and may be electrically connected to the wiring of the interconnection structure610. The interposer600may be stacked on the package substrate500through the bump620. The bump620may be connected to the wiring612of the interconnection structure610through the through-electrode630and the lower pad605. In an example, some pads605used for power or grounding among the lower pads605may be integrated and connected to the bump620, and thus, the number of the lower pads605may be greater than the number of the bumps620.

The interposer600may include upper pads685and upper protrusion patterns680on the interconnection structure610. The upper pads685may include a first upper pad680aand a second upper pad680a. The upper protrusion patterns680may include a first upper protrusion pattern680_1and a second upper protrusion pattern680_2.

The logic chip400may include, for example, a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific IC (ASIC), and the like. According to the types of devices included in the logic chip400, the semiconductor package1000may be classified as a server-oriented semiconductor package or a mobile-oriented semiconductor package.

The semiconductor package1000may include a first connection pattern710adisposed between the memory structure300and the interposer600to electrically connect the memory structure300and the interposer600, and a second connection pattern710bdisposed between the logic chip400and the interposer600to electrically connect the logic chip400and the interposer600.

The semiconductor package1000may include a first underfill material layer700afilling the space between the memory structure300and the interposer600and surrounding a side surface of the first connection pattern710a, and a second underfill material layer700bfilling the space between the logic chip400and the interposer600and surrounding a side surface of the second connection pattern710b.

In the interposer600, the upper protrusion patterns680may perform substantially the same function as the upper protrusion pattern280of the base203described with reference toFIGS.8A and8B. For example, the first upper protrusion pattern680_1of the upper protrusion patterns680may serve to provide stable and reliable formation of the first underfill material layer700aand prevent the first underfill material layer700afrom excessively protruding to out of the memory structure300. In addition, the second upper protrusion patterns680_2of the upper protrusion patterns680may serve to provide stable and reliable formation of the second underfill material layer700band prevent the second underfill material layer700bfrom excessively protruding out of the logic chip400.

Next, a method of forming a semiconductor package according to an exemplary embodiment will be described with reference toFIGS.12to15, as an example.FIG.12is a plan view of a semiconductor wafer illustrated to describe a method of forming a semiconductor package according to an exemplary embodiment, andFIGS.13to15are cross-sectional views illustrating areas taken along lines I-I′ and III-III′ ofFIG.12.

Referring toFIGS.12and13, a semiconductor wafer WF may be formed. A front structure FS may be formed on the front side of the semiconductor wafer WF. The front structure FS may be the front structure FS as described with reference toFIG.2.

The semiconductor wafer WF may be a semiconductor substrate4. A through-electrode structure75may be formed. For example, after forming a portion of the front structure FS, the through-electrode structure75may be formed to penetrate through a portion of the front structure FS and extend into the semiconductor wafer WF and4.

The front bump60and the connection pattern65as described with reference toFIG.2may be formed below the front structure FS of the semiconductor wafer WF. The connection pattern65may include a solder material.

The front structure FS may further include the chipping dams (refer to33ofFIG.5) as described with reference toFIG.5. The semiconductor wafer WF may further include the front protrusion pattern (refer to47ofFIG.7) as described with reference toFIG.7.

The through-electrode structure75may not penetrate the semiconductor wafer, for example, the semiconductor substrate4. The through-electrode structure75may include a through-electrode75band an insulating spacer75acovering at least a side surface of the through-electrode75b.

The semiconductor substrate (WF,4) may include a plurality of chip areas CA, and a scribe lane area SA between the plurality of chip areas CA.

The scribe lane area SA may include dummy areas DA surrounding each of the plurality of chip areas CA in a ring shape, and a cutting area CT between the dummy areas DA.

Referring toFIGS.12,14and15, a process for reducing the thickness of the semiconductor substrate4, for example, a back grinding process, may be performed to form the semiconductor substrate5having a reduced thickness. The semiconductor substrate5having a reduced thickness may have a front side5S1and a back side5S2, and a portion of the through-electrode structure75may be formed to have a shape protruding from the back side5S2of the semiconductor substrate5.

A rear structure BS including a rear protective layer70, a rear protrusion pattern80, and a rear alignment key AK may be formed on the back side5S2of the semiconductor substrate5. Forming the rear protective layer70may include forming an insulating layer on the back side5S2of the semiconductor substrate5, and then, planarizing the insulating layer until the through-electrode75bof the through-electrode structure75is exposed.

The rear protrusion pattern80and the back side alignment key AK may be simultaneously formed on the rear protective layer70on the scribe lane area SA. The rear protrusion pattern80and the rear alignment key AK may include first and second insulating material layers79aand79bsequentially stacked.

The rear protrusion pattern80may be formed in various shapes as described with reference toFIGS.1to6.

In another example, forming the rear protective layer70, the rear protrusion pattern80, and the rear alignment key AK may include forming a plurality of insulating layers on the back side5S2of the semiconductor substrate5, and patterning the plurality of insulating layers by performing a photo and etching process. For example, forming a plurality of insulating layers on the back side5S2of the semiconductor substrate5, performing a photo and etching process to remove a portion of the plurality of insulating layers in the chip area CA, and forming the alignment key AK in the stripe lane area SA may be included. In this case, the plurality of remaining insulating layers may be formed as the rear protrusion pattern80, and an insulating layer remaining in a lower portion among the plurality of insulating layers may be formed as the rear protective layer70.

A rear pad85electrically connected to the through-electrode75bof the through-electrode structure75may be formed on the rear protective layer70. The rear pad85may include a first rear layer84aand a second rear layer84bon the first rear layer84a, sequentially stacked.

Again, referring toFIGS.1and2, by performing a sawing process, the semiconductor wafer, for example, the semiconductor substrate5may be cut along the cutting area CT of the scribe lane area SA to form a plurality of semiconductor chips3. Accordingly, the plurality of chip areas (CA ofFIG.12) may be separated from each other. The rear alignment key AK may be removed while cutting the semiconductor wafer. Each of the semiconductor chips3may include the front structure FS, the rear protective layer70, and the rear protrusion pattern80.

The dummy areas (DA ofFIG.12) surrounding each of the plurality of chip areas (CA ofFIG.12) may remain. Accordingly, the semiconductor chip3including one chip area CA and one dummy area DA surrounding the one chip area CA may be formed as illustrated inFIG.1.

Again, referring toFIGS.8A and8B, the semiconductor chips3may include a first semiconductor chip and a second semiconductor chip. A first adhesive material layer may be attached to a lower portion of the front structure of the first semiconductor chip, a second adhesive material layer may be attached to a lower portion of the front structure of the second semiconductor chip, and a base203may be prepared. The first semiconductor chip to which the first adhesive material layer is attached may be attached to the base, thereby forming the first semiconductor chip103aand the first adhesive material layer190aas inFIGS.8A and8B. The second semiconductor chip to which the second adhesive material layer is attached may be attached onto the first semiconductor chip103a, thereby forming the second semiconductor chip103band the second adhesive material layer190bas inFIGS.8A and8B. This process may be repeated.

The first adhesive material layer190amay be disposed between the first semiconductor chip103aand the base103ato be in contact with the first semiconductor chip103aand the base203. The second adhesive material layer190bmay be disposed between the first semiconductor chip103aand the second semiconductor chip103bto be in contact with the first semiconductor chip103aand the second semiconductor chip103b.

After repeatedly attaching the semiconductor chip to which the adhesive material layer is attached onto the base203, a mold layer195may be formed, and the mold layer195and the base203may be cut to form the semiconductor package1aas illustrated in FIGS.FIG.8AandFIG.8B. The mold layer195may be formed of an epoxy mold compound (EMC).

In some exemplary embodiments, the rear protrusion patterns180may prevent the adhesive material layers190a,190b,190c,190cand190dfrom excessively protruding outwardly of the semiconductor chips103a,103b,103c, and103d. For example, by the rear protrusion pattern80of the first semiconductor chip103a, the second adhesive material layer190bmay be stably and reliably filled between the first semiconductor chip103aand the second semiconductor chip103b. In addition, the second adhesive material layer190bmay serve to prevent excessive protrusion of the first and second semiconductor chips103aand103boutwardly.

As set forth above, according to exemplary embodiments, a semiconductor package having improved reliability may be provided by disposing a rear protrusion pattern for stably and reliably forming an adhesive material layer on the back side of a semiconductor chip.

While exemplary embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.