Patent ID: 12261179

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to make a person skilled in the art better understand the technical solutions of the present disclosure, the following detailed description is given with reference to the accompanying drawings and the embodiments.

The inventors found that at least the following problems exist in the related art: the silicon oxide layer is high in hardness and low in dielectric constant, and is easy to break down due to voltages on the gate electrode and the metal layer, and therefore the display effect of a display product is affected.

The interlayer insulating layer provided in the embodiments of the present disclosure is mainly described in an example of a thin film transistor. The thin film transistor is generally a top-gate thin film transistor or a bottom-gate thin film transistor, and in the present embodiment, the top-gate thin film transistor is taken as an example for description.FIG.1is a schematic structural diagram of a top-gate thin film transistor, and as shown inFIG.1, the top-gate thin film transistor includes: an active layer102, a gate insulating layer103, a gate electrode104, an interlayer insulating layer105, and a source and drain electrodes106and107disposed on the same layer, which are sequentially provided on the substrate101, the source electrode106is coupled to the active layer102by a source electrode contact hole108penetrating the interlayer insulating layer105, and the drain electrode107is coupled to the active layer102by a drain electrode contact hole109penetrating the interlayer insulating layer105. In the related art, the interlayer insulating layer105may be composed of a composite layer having a double-layer structure of a silicon oxide layer and a silicon nitride layer, and the double-layer structure is generally prepared by chemical vapor deposition, low-temperature deposition, and the like. In the silicon nitride layer formed in the above manner, hydrogen atoms generally remain in the layer in the form of Si—H, Si—O or N—H bonds, and the hydrogen content has a great influence on the structure, stress, and corrosion resistance of the interlayer insulating layer105, and at the same time, the hydrogen content has a great influence on the stability of the active layer102. In order to solve the problem, at present, the interlayer insulating layer105is mainly prepared by depositing two silicon oxide layers, the hydrogen content in the reaction gas in the preparation process of the silicon oxide layers is low, so that the influence on the stability of the active layer102in the thin film transistor can be reduced, but the two silicon oxide layers are hard in texture and low in resistance to breakdown, and are easy to break down to cause short circuit in a practical application. This embodiment provides a method for preparing an interlayer insulating layer having a double-layer structure of a silicon oxide layer and a silicon nitride layer, and a method for manufacturing a thin film transistor including the interlayer insulating layer.

It should be noted herein that, the materials of the silicon oxide layer and the silicon nitride layer themselves do not contain hydrogen, and the hydrogen content in the silicon oxide layer or the hydrogen content in the silicon nitride layer in the embodiment of the present disclosure refer to the hydrogen content remaining in the layer as Si—H, Si—O or N—H bonds from the reaction gas used during the preparation of the layer.

According to an aspect of the present disclosure, a method for preparing an interlayer insulating layer is provided.FIG.2is a schematic structural diagram of an interlayer insulating layer according to an embodiment of the disclosure, and as shown inFIG.2, the interlayer insulating layer is composed of a silicon oxide layer201and a silicon nitride layer202. The method for preparing the interlayer insulating layer provided by the embodiment of the present disclosure can be used for preparing the interlayer insulating layer shown inFIG.2. The method for preparing the interlayer insulating layer comprises the following steps: forming a silicon oxide layer with a first reaction gas and forming a silicon nitride layer with a second reaction gas such that the hydrogen content in the formed silicon nitride layer is less than or equal to the hydrogen content in the formed silicon oxide layer.

In the embodiment of the present disclosure, first, the silicon oxide layer201may be formed with the first reaction gas, and generally, the formed silicon oxide layer201contains a relatively low hydrogen content, which may reduce the influence of the hydrogen content in the entire interlayer insulating layer105on the stability of the active layer102. Then, the silicon nitride layer202is formed on the silicon oxide layer201with the second reaction gas, the formed silicon nitride layer202also has a relatively low hydrogen content, and the hydrogen content in the formed silicon nitride layer202is less than or equal to the hydrogen content in the silicon oxide layer201. It should be understood that, the hydrogen content in the formed silicon oxide layer201is generally low, and the hydrogen content in the silicon nitride layer202formed in the embodiment of the present disclosure is lower than the hydrogen content in the silicon oxide layer201, so that the formed silicon nitride layer202can be ensured to contain a lower hydrogen content, and therefore the overall interlayer insulating layer105contains a relatively low hydrogen content, and further, the influence on the stability of the active layer102can be reduced. Meanwhile, due to the material characteristics of the silicon nitride layer202, the silicon nitride layer is soft in texture, high in dielectric constant and high in resistance to breakdown, so that the resistance to breakdown of the overall interlayer insulating layer can be improved, the yield of the display products can be effectively improved, and the display effect of the display product can be further improved.

It should be understood that, the interlayer insulating layer105prepared by the method for preparing an interlayer insulating layer provided by the embodiment of the present disclosure includes the silicon oxide layer201and the silicon nitride layer202, and may also include multiple silicon oxide layers201and multiple silicon nitride layers202formed alternately, and at least one of the two outermost layers of the entire interlayer insulating layer105is the silicon oxide layer201. Of course, a sequence for preparing the silicon oxide layer201and the silicon nitride layer202may be selected according to actual requirements.

In the embodiment of the present disclosure, the method for preparing an interlayer insulating layer is described by taking the interlayer insulating layer having a double-layer structure of a silicon oxide layer201and a silicon nitride layer202as an example.FIG.3is a flowchart of a method for preparing an interlayer insulating layer according to an embodiment of the present disclosure, and as shown inFIG.3, the method for preparing an interlayer insulating layer includes the following steps:

S301, a silicon oxide layer is formed by deposition with methylsilane (SiH4) and nitrous oxide (N2O).

It should be noted that, methylsilane and nitrous oxide may be used as the first reaction gas, methylsilane and nitrous oxide gases may be fed into the reaction chamber at a temperature of 300 degrees centigrade (° C.) at corresponding flow rates, and in an environment at a pressure of 1.0 Torr, molecules of methylsilane and nitrous oxide gases are ionized into atoms by an electric field, and the atoms react with each other, thereby forming the silicon oxide layer by deposition. It is understood that, the flow rates at which methylsilane and the nitrous oxide are fed into the reaction chamber may be adjusted to form a uniform silicon oxide layer according to practical applications, and for example, the flow rates may be 1 to 100 slm (liters per minute), as in the related art, which is not limited herein. The residual hydrogen content in the silicon oxide layer201formed by deposition with methylsilane and nitrous oxide in the embodiment of the present disclosure is low, and the influence on the stability of the active layer102may be reduced.

S302, a silicon nitride layer is formed by deposition with Trisilylamine (TSA) and nitrogen.

It should be noted that, in the related art, the silicon nitride layer may be formed by chemical vapor deposition with three gases, i.e., methylsilane, ammonia, and nitrogen. However, in the procedure of forming the silicon nitride layer by deposition using the three gases, much hydrogen is easily introduced into the silicon nitride layer, so that a higher hydrogen content remains in the formed silicon nitride layer, and will affect the stability of the active layer102. In order to reduce the hydrogen content in the formed silicon nitride layer202, trisilylamine and nitrogen may be used in the embodiment of the present disclosure, and trisilylamine and nitrogen gases may be introduced into the reaction chamber at a temperature of 200 to 350° C. (e.g., 250° C.), trisilylamine gas may be introduced at a flow rate of 3 slm (liters per minute) to 9 slm and nitrogen may be introduced at a flow rate of 0.1 slm to 6 slm, and molecules of trisilylamine and nitrogen gases are ionized into atoms by an electric field in an environment at a pressure of 2 to 4 torr (e.g., 3 torr), and the atoms react with each other, thereby forming the silicon nitride layer202. As known to those skilled in the art, the above-mentioned temperature, flow rates of the gases, pressure and electric field strength may be selected according to the size of the reaction chamber and the thickness and quality requirements of the silicon nitride layer to be formed. It is understood that, the flow rates of trisilylamine and nitrogen gases may be adjusted to form a uniform silicon nitride layer202. In the embodiment of the present disclosure, the silicon nitride layer202formed by deposition with trisilylamine and nitrogen has a relatively low hydrogen content than the silicon nitride layer formed by deposition with methylsilane, ammonia, and nitrogen in the related art, and the influence on the stability of the active layer102can be reduced by the silicon nitride layer202formed by the method provided in the embodiment of the present disclosure. Meanwhile, the formed silicon nitride layer202is soft in texture, high in dielectric constant and high in resistance to breakdown, so that the resistance to breakdown of the entire interlayer insulating layer105can be improved, and the yield of display products can be improved. The chemical structure of trisilylamine is as follows:

It should be noted that, the sequence to perform steps S301and S302is related to the application scenario of the interlayer insulating layer. For example, when an oxide thin film transistor is formed, the interlayer insulating layer is formed after an oxide active layer is formed. Therefore, step S301needs to be performed first to form a silicon oxide layer, and then step S302needs to be performed to form a silicon nitride layer. If the interlayer insulating layer is formed before the oxide active layer is formed, step S302needs to be performed first to form a silicon nitride layer, and step S301is then performed to form a silicon oxide layer.

Alternatively, the hydrogen content (atomic percent of hydrogen) in the silicon oxide layer is 1% to 2%; the hydrogen content (atomic percent of hydrogen) in the silicon nitride layer is 1% to 2%. Optionally, the refractive index (RI) of the silicon nitride layer reflecting the stress characteristics ranges between 2.0 and 2.1.

In an embodiment,FIG.4is a diagram illustrating results of testing hydrogen content in the formed layers according to an embodiment of the present disclosure. As shown inFIG.4, the hydrogen content in the silicon nitride layer202formed with trisilylamine and nitrogen is 1.8%, the hydrogen content in the silicon oxide layer201formed with methylsilane and nitrous oxide is 1.9%, and the hydrogen content in the silicon nitride layer formed with methylsilane, ammonia and nitrogen in the related art is 22%. Therefore, it can be seen that, the silicon oxide layer201and the silicon nitride layer202formed with the method provided by the embodiment of the present disclosure have lower hydrogen contents, and therefore, the overall interlayer insulating layer105has lower hydrogen content, and the influence on the stability of the active layer102can be reduced.

Optionally, the dielectric constant of the silicon nitride layer202is higher than that of the silicon oxide layer201.

It should be noted that, the dielectric constant is an important parameter for characterizing the electrical properties of a dielectric or insulating material, and the higher the dielectric constant of the layer material is, the stronger the resistance to breakdown thereof is. In the embodiment of the present disclosure, the dielectric constant of the silicon nitride layer202is higher than that of the silicon oxide layer201, so that the silicon nitride layer with a higher dielectric constant can improve the resistance to breakdown of the entire interlayer insulating layer105, thereby improving the yield of the display products.

Optionally, the thickness of the silicon oxide layer201is greater than 2500 angstroms, and the thickness of the silicon nitride layer202is greater than 2500 angstroms.

It should be noted that, the double-layer or multi-layer structure formed by the silicon oxide layer201and the silicon nitride layer202may constitute a thicker overall interlayer insulating layer105to achieve a good insulating effect, so as to prevent the interlayer insulating layer105from being broken down by the electric field formed on both sides. The interlayer insulating layer105generally has a thickness of greater than 5000 angstroms, the silicon oxide layer may be greater than 2500 angstroms thick, and the silicon nitride layer may be greater than 2500 angstroms thick. The interlayer insulating layer105having a multi-layer structure in which the silicon oxide layer201and the silicon nitride layer202are alternately arranged may be formed as needed. It is understood that, the silicon oxide layer201and the silicon nitride layer202may have other thicknesses in practical applications.

According to another aspect of the present disclosure, a method for manufacturing a thin film transistor is provided, and this embodiment will take a top-gate thin film transistor as an example, and further describe in detail the method for manufacturing a thin film transistor provided in the present disclosure with reference to the accompanying drawings. The interlayer insulating layer105is a double-layer structure formed by the method for preparing an interlayer insulating layer provided in the above embodiments.FIG.5is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure, and as shown inFIG.5, the method for manufacturing a thin film transistor includes the following steps (where steps S5021and S5022are steps of the method for preparing an interlayer insulating layer as shown inFIG.3):

Step S501, an active layer, a gate insulating layer and a gate electrode are sequentially formed on a substrate.

In step S501, patterns of the active layer102, the gate insulating layer103, and the gate electrode104may be formed on the substrate101by a single patterning process. For example, the substrate101may be initially cleaned during the preparation process, and as shown inFIG.6a, a material layer of the active layer102may be deposited on the substrate101. A material of the active layer102may be a semiconductor material, and for example may be a metal oxide material such as indium zinc oxide or indium tin oxide. Then, as shown inFIG.6b, a material layer of the gate insulating layer103is deposited to at least cover the active layer102. The gate insulating layer103may be a silicon oxide layer to insulate the active layer102from the gate electrode104thereon, thereby preventing a voltage on the gate electrode104from affecting the active layer102. Finally, as shown inFIG.6c, a metal layer of the gate electrode104is deposited on the gate insulating layer103, and a photoresist layer is coated on the metal layer of the gate electrode104. The gate electrode104may be made of a conductor such as copper, and the active layer102, the gate insulating layer103and the gate electrode104may be patterned by performing exposure, development, post-baking, etching, and photoresist stripping processes on the metal layer of the gate electrode104.

Step S502, an interlayer insulating layer consisting of a silicon oxide layer and a silicon nitride layer is formed on the gate electrode.

In step S502, a silicon oxide layer and a silicon nitride layer are deposited on the gate electrode104, and the interlayer insulating layer105having a double-layer structure including the silicon oxide layer201and the silicon nitride layer202is formed. When the thin film transistor is an oxide thin film transistor, the active layer102includes an oxide active layer, which may comprise metal oxide such as indium zinc oxide or indium tin oxide. When the thin film transistor is an oxide thin film transistor, the step S502may include the following sub-steps:

Sub-step S5021, a silicon oxide layer is formed by deposition with methylsilane and nitrous oxide.

Particularly, as shown inFIG.6d, a silicon oxide layer201may be deposited on the gate electrode104using methylsilane and nitrous oxide as the first reaction gas, and the silicon oxide layer201formed with methylsilane and nitrous oxide has a relatively low hydrogen content, which may reduce the influence on the stability of the oxide active layer.

Sub-step S5022, a silicon nitride layer is formed by deposition with Trisilylamine (TSA) and nitrogen.

Particularly, as shown inFIG.6e, a silicon nitride layer202may be deposited on the silicon oxide layer201using trisilylamine and nitrogen as the second reaction gas, and the hydrogen content in the silicon nitride layer202formed with trisilylamine and nitrogen is low, which may reduce the influence on the stability of the oxide active layer. Meanwhile, the formed silicon nitride layer202has a relatively soft texture, a relatively high dielectric constant, and a relatively high resistance to breakdown, so that the resistance to breakdown of the entire interlayer insulating layer105can be improved.

When the thin film transistor is an oxide thin film transistor, the sequence to perform the sub-steps S502021and S52is first performing the sub-step S5021to form the silicon oxide layer covering the gate electrode104, and then performing the sub-step S5022to form the silicon nitride layer202on the silicon oxide layer201.

Step S503, a source electrode contact hole and a drain electrode contact hole penetrating through the silicon oxide layer and the silicon nitride layer are formed by a patterning process.

Particularly, as shown inFIG.6f, a photoresist layer is coated on the silicon nitride layer202, and after exposure, development and post-baking processes are performed on the photoresist layer, an etching process is performed on the silicon oxide layer201and the silicon nitride layer202in the interlayer insulating layer105, and then the photoresist layer is stripped off, such that the source electrode contact hole108corresponding to the source electrode106and the drain electrode contact via hole109corresponding to the drain electrode107are formed.

Step S504, a source electrode and a drain electrode are formed on the silicon nitride layer such that the source electrode is coupled to the active layer through the source electrode contact hole, and the drain electrode is coupled to the active layer through the drain electrode contact hole.

Particularly, as shown inFIG.6g, a source electrode106and a drain electrode107are deposited on the silicon nitride layer202, and both the source electrode106and the drain electrode107each are a metal layer and made of a conductive metal material. The source electrode106may be coupled to the active layer102through the source electrode contact hole108penetrating the silicon oxide layer201and the silicon nitride layer202, and the drain electrode107may be coupled to the active layer102through the drain electrode contact hole109penetrating the silicon oxide layer201and the silicon nitride layer202. Therefore, the thin film transistor is completed. Gate lines and data lines (not shown) may be previously formed in the thin film transistor to facilitate wiring when the thin film transistor is applied to an array substrate. The gate line and the gate electrode104may be disposed in a same layer, and the gate line and the gate electrode104are electrically coupled to each other, and may be made of a same material and formed by a single patterning process. The data line is disposed in a same layer as the source electrode106, and the data line and the source electrode106are electrically coupled to each other, and may be formed of a same material and formed by a single patterning process. A gate voltage may be inputted to the gate electrode104through the gate line, a data voltage may be inputted to the source electrode106through the data line, and the interlayer insulating layer105between the gate electrode104and the source electrode106may insulate the gate electrode104from the source electrode106to prevent a short circuit. In the embodiment of the present disclosure, the silicon nitride layer202can improve the resistance to breakdown of the entire interlayer insulating layer105, and avoid the breakdown of the entire interlayer insulating layer105due to the electric field between the gate electrode104and the source electrode106or the drain electrode107, thereby improving the yield of the display products and further improving the display effect. Meanwhile, the hydrogen content in the formed silicon oxide layer201and the silicon nitride layer202is low, so that the influence of the hydrogen content in the entire interlayer insulating layer105on the stability of the active layer102can be avoided.

It will be understood that, the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these changes and modifications are to be considered within the scope of the disclosure.