Patent ID: 12191824

DETAILED DESCRIPTION OF SOME EMBODIMENTS

The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

FIG.1depicts a system1010that includes a wearable audio device1002in communication with a host device1008. Such communication, depicted as1007inFIG.1, can be supported by, for example, a wireless link such as a short-range wireless link in accordance with a common industry standard, a standard specific for the system1010, or some combination thereof. In some embodiments, the wireless link1007includes digital format of information being transferred from one device to the other (e.g., from the host device1008to the wearable audio device1002).

InFIG.1, the wearable device1002is shown to include an audio amplifier circuit1000that provides an electrical audio signal to a speaker1004based on a digital signal received from the host device1008. Such an electrical audio signal can drive the speaker1004and generate sound representative of a content provided in the digital signal, for a user wearing the wearable device1002.

InFIG.1, the wearable device1002is a wireless device; and thus typically includes its own power supply1006including a battery. Such a power supply can be configured to provide electrical power for the audio device1002, including power for operation of the audio amplifier circuit1000. It is noted that since many wearable audio devices have small sizes for user-convenience, such small sizes places constraints on power capacity provided by batteries within the wearable audio devices.

In some embodiments, the host device1008can be a portable wireless device such as, for example, a smartphone, a tablet, an audio player, etc. It will be understood that such a portable wireless device may or may not include phone functionality such as cellular functionality. In such an example context of a portable wireless device being a host device,FIGS.2and3show more specific examples of wearable audio devices1002ofFIG.1.

For example,FIG.2shows that the wearable audio device1002ofFIG.1can be implemented as a device (1002aor1002b) configured to be worn at least partially in an ear canal of a user. Such a device, commonly referred to as an earbud, is typically desirable for the user due to compact size and light weight.

In the example ofFIG.2, a pair of earbuds (1002aand1002b) can be provided—one for each of the two ears of the user—and each earbud can include its own components (e.g., audio amplifier circuit, speaker and power supply) described above in reference toFIG.1. In some embodiments, such a pair of earbuds can be operated to provide, for example, stereo functionality for left (L) and right (R) ears.

In another example,FIG.3shows that the wearable audio device1002ofFIG.1can be implemented as part of a headphone1003configured to be worn on the head of a user, such that the audio device (1002aor1002b) is positioned on or over a corresponding ear of the user. Such a headphone is typically desirable for the user due to audio performance.

In the example ofFIG.3, a pair of audio devices (1002aand1002b) can be provided—one for each of the two ears of the user. In some embodiments, each audio device (1002aor1002b) can include its own components (e.g., audio amplifier circuit, speaker and power supply) described above in reference toFIG.1. In some embodiments, one audio device (1002aor1002b) can include an audio amplifier circuit that provides outputs for the speakers of both audio devices. In some embodiments, the pair of audio devices1002a,1002bof the headphone1003can be operated to provide, for example, stereo functionality for left (L) and right (R) ears.

FIG.4shows that in some embodiments, the audio amplifier circuit1000ofFIG.1can include a number of functional blocks. More particularly, inFIG.4, an audio amplifier circuit1000is shown to include a digital logic circuit block1020, an amplifier block1022, a power management block1024, and an ancillary block1026. Examples related to such blocks are described herein in greater detail.

InFIG.4, the audio amplifier circuit1000is shown to further include various interfaces to allow the audio amplifier circuit1000to interact with other devices external to the audio amplifier circuit1000. More particularly, an interface indicated as1030can be configured to support input/output (I/O) functionality with respect to a host device (e.g.,1008inFIG.1). An interface indicated as1034can be configured to support providing of electrical audio signals to a speaker (e.g.,1004inFIG.1). An interface indicated as1032can be configured to support providing of electrical power to various parts of the audio amplifier circuit1000. One or more ground pins collectively indicated as1036(GND) can be configured to provide a grounding connection for the audio amplifier circuit1000relative to, for example, the audio device1002ofFIG.1.

FIG.5shows a block diagram of an audio amplifier circuit1000that is a more specific example of the audio amplifier circuit1000ofFIG.4. InFIG.5, a digital logic circuit block, generally indicated as1020, can include a number of more specific functional blocks; an amplifier block, generally indicated as1022, can include a number of more specific functional blocks; a power management block, generally indicated as1024, can include a number of more specific functional blocks; and an ancillary block, generally indicated as1026, can include a number of more specific functional blocks. Similarly, an interface indicated as1030can include a number of pins to support input/output (I/O) functionality with respect to a host device; an interface indicated as1034can include a number of pins to support providing of electrical audio signals to a speaker; an interface indicated as1032can include a number of pins to support providing of electrical power to various parts of the audio amplifier circuit1000; and one or more ground pins collectively indicated as1036(GND) can be implemented to provide a grounding connection for the audio amplifier circuit1000.

Referring to the example ofFIG.5, the digital logic circuit block1020can include a receiver (Rx) block1040configured to receive, for example, a pulse-density modulation (PDM) signal through a DATA pin of the interface1030. The PDM Rx block1040is shown to also receive a clock signal through a CLK pin of the interface1030. The PDM Rx block1040is shown to provide an output based on the input PDM signal.

It will be understood that while various examples are described herein in the context of pulse-density modulation of signals, one or more features of the present disclosure can also be implemented utilizing other types of modulations including other types of pulse modulations.

InFIG.5, the digital logic circuit block1020can further include a digital audio path block1042. Such a block is shown to receive the output of the PDM Rx block1040and route the received signal to the amplifier block1022. Additional examples related to the digital audio path block1042are described herein in greater detail.

As shown inFIG.5, the digital logic circuit block1020can also include various blocks for providing control and calibration functionalities. For example, amplifier controller1090, resistance network control block1064, amplifier operating mode (e.g., HOR/ZOR mode) control block1062, inter-integrated circuit (I2C) auxiliary block1092, registers block1094, PDM detect block1060and loudness protection block1066can provide and/or support various control functionalities described herein. In another example, current ratio measurement calibration block1068and gain calibration block1070can provide calibration functionalities described herein. More particularly, the current ratio measurement calibration block1068can support generation of a reference signal for a loop circuit as described herein, and the gain calibration block1070can provide various functionalities for gain calibration as described herein.

Referring to the example ofFIG.5, the amplifier block1022is shown to include a pulse-width modulation (PWM) controller1050configured to receive a feedforward digital signal from the digital audio path block1042of the digital logic circuit block1020(through a path indicated as1043) and generate control signals for an H-bridge driver1052. The H-bridge driver1052provides analog electrical audio signals HPN, HPP as outputs. Such electrical audio signals can be provided to a speaker through respective pins of the interface1034.

In the example ofFIG.5, the amplifier block1022is configured as a digital PWM Class D amplifier. In addition to the H-bridge driver1052being pulse-width modulated by the PWM controller1050based on the feedforward digital signal from the digital audio path block1042, a closed-loop architecture is provided. Such a closed loop is shown to include an input resistance network1080coupled to the HPN and HPP outputs of the H-bridge driver1052, with the input resistance network1080being coupled to a loop filter1046through summing nodes1081,1083. An analog output from the loop filter1046is shown to be converted into a digital signal by an analog-to-digital converter (ADC)1048such as a successive approximation register (SAR) ADC. The digital signal from the SAR ADC1048is provided to the PWM controller1050.

In the example ofFIG.5, the amplifier block1022is configured to provide a reference analog signal for the foregoing closed-loop circuit. More particularly, a digital signal from the digital audio path block1042is shown to be provided to a digital-to-analog converter (DAC)1044(through a path indicated as1045), and the resulting analog signal is provided to the summing nodes1081,1083. The summing nodes1081,1083are also shown to be provided with respective signals from a common-mode-limit (CML) amplifier1082.

In the example ofFIG.5, the audio amplifier circuit1000is shown to include a gain calibration feature. Such a feature is shown to include a calibration ADC1084coupled to the HPN and HPP outputs of the H-bridge driver1052to provide a digital signal representative of the analog output signals of the H-bridge driver1052. The digital signal from the calibration ADC1084is shown to be provided to the gain calibration block1070of the digital logic circuit block1020.

In the example ofFIG.5, the H-bridge driver1052shown to be provided with multiple levels of supply voltages (e.g., VBAT, VDD_A, VDD_B, VDD_D, VDD_E). Such multiple voltage levels can allow the H-bridge driver1052to operate with improved power efficiency.

Additional examples concerning the amplifier block1022are described herein in greater detail.

InFIG.5, the power management block1024can include a number of functional blocks configured to provide and/or support providing of power to various parts of the audio amplifier circuit1000. For example, the power management block1024can be configured to provide routing of multiple supply voltage levels (e.g., VBAT, VDD_A, VDD_B, VDD_D, VDD_E) to the H-bridge driver1052of the amplifier block1022. For the example supply voltage levels, VBAT>VDD_A>VDD_B>VDD_D>VDD_E.

Such supply voltages can be provided from source(s) external to the audio amplifier circuit1000, from internal source(s), or some combination thereof. In the example ofFIG.5, supply voltages VBAT, VDD_A and VDD_B are provided from external source(s); VDD_D may be provided from an external source or from an internal source implemented as a low drop out (LDO) regulator1130; and VDD_E is provided from an internal source implemented as a low voltage monitor (LVM) supply1132.

Some or all of the foregoing voltages can be monitored by one or more voltage monitors. For example, a supply voltage monitor (SVM)1120is shown to monitor the voltages VBAT, VDD_A, VDD_B and VDD_D. Such an SVM can include low power low resolution ADCs that monitor the supply voltages and produce respective digital outputs representative of the supply voltages; and such monitored digital outputs can be utilized by other digital circuitry to control various functionalities of the audio amplifier circuit1000. In another example, the voltage VDD_E is shown to be self-monitored by the LVM supply1132.

Referring to the example ofFIG.5, the power management block1024is shown to further include a reference (Ref) block1110. Such a reference block can be implemented as a low voltage, low power bandgap reference circuit configured to operate with a supply voltage (e.g., VDD_B) to produce a low reference voltage as an output. Such a reference voltage can be utilized for operation of an analog LDO regulator1112and a digital LDO regulator1114, as well as other functional blocks of the audio amplifier circuit1000. The analog LDO regulator1112can be implemented as a lower power linear regulator configured to provide a desired voltage for a number of circuits of the audio amplifier circuit1000. The digital LDO regulator1114can be implemented as a low power linear regulator configured to provide a desired voltage for various digital logic and digital core circuits of the audio amplifier circuit1000.

Referring to the example ofFIG.5, the power management block1024is shown to further include a low power oscillator (LPO)1118. Such an LPO can be configured to support operation of the audio amplifier circuit1000. The power management block1024is shown to further include a sensor block1116such as a temperature sensor. Such a sensor can be configured to detect operating condition(s) (e.g., temperature) of some or all of the audio amplifier circuit1000; and such sensed condition(s) can be utilized to support one or more functionalities (e.g., fault protection) for the audio amplifier circuit1000.

InFIG.5, the ancillary block1026is shown to include a power-on-reset (POR) block1100. Such a POR block can be implemented to provide a number of functionalities. For example, power-on reset functionality can be provided by the POR block1100, where the POR block1100monitors the RESET_B pin and supply voltage conditions to control and/or support power-on sequencing of various regulators, clock system and wall level shifters utilizing respective control signals (Pups). Once such power-on sequencing is achieved and the controlled components are operating in a stable manner, a release signal (Dig_reset_B) is provided to allow operation of various digital blocks.

The POR block1100can also control and/or support a power-down sequence. Such a power-down sequence can be achieved in response to a control signal from a host device (e.g., setting RESET_B to a initiate power-down), or based on detection of one or more conditions. Such conditions can include, for example, a brownout detection and various fault detections.

InFIG.5, the ancillary block1026is shown to include a one-time programmable memory (OTP)1102and a block1104providing control and register functionalities for the OTP block1102. Such functionalities can include issuing of a control signal (I2C address) to the120block1092to load appropriate registers of the Registers block1094during a boot process.

FIG.6shows a block diagram that includes a digital audio path block1042that is a more specific example of the digital audio path block1042ofFIG.5. InFIG.6, a pulse-density modulation (PDM) receiver (Rx) block1040is shown to receive a PDM signal DATA and a clock signal CLK, and provide a PDM digital signal to the digital audio path block1042.

More particularly, the PDM digital signal from the PDM Rx block1040is shown to be provided to a digital low-pass filter (PDM LPF)1140. Such a filter block can be configured to, for example, attenuate out-of-band noise in the received PDM digital signal (e.g., noise resulting from a transmit (Tx) modulation in a host device). The PDM LPF block1140ofFIG.6can also be configured to convert the PDM input signal into an output digital signal having pulse-code modulation (PCM).

InFIG.6, the filtered PCM signal from the PDM LPF block1140is shown to be provided to an equalizer (EQ) block1142. Such an EQ block can be configured to support gain and mute functionalities, as well as high-output resistance (HOR) and/or zero-output resistance (ZOR) operating modes. The EQ block1142provides an output PCM signal to a calibration tone mixer1144. Additional details concerning the EQ block1142are provided herein.

Referring toFIG.6, the calibration tone mixer1144is shown to mix a calibration tone signal from a gain calibration block1070with the output PCM signal from the EQ block1142. Such mixing functionality can be provided during a calibration process such as an HOR/ZOR gain calibration process. Additional details concerning the HOR/ZOR gain calibration process are provided herein.

InFIG.6, the output of the calibration tone mixer1144is also shown to be processed through a number of blocks before being provided a digital-to-analog converter (DAC)1044(also1044inFIG.5) through a path1045for a closed-loop circuit as described herein. More particularly, the output (PCM signal) of the calibration tone mixer1144is shown to be provided to a signal limiter block1146. Such a signal limiter can be configured to maintain a threshold limit for a DAC modulator (e.g., delta sigma modulator (DSM))1148and also improve handling of low supply voltage operating conditions (e.g., when a HOR mode load reactance causes supply voltage requirements of an H-bridge drive to increase beyond a pure resistive load condition).

Referring toFIG.6, it is noted that for the foregoing low voltage operating conditions, a SAR ADC (e.g.,1048inFIG.5) in the closed-loop circuit can be driven into saturation if the power supply is insufficient to provide the required peak voltage for the H-bridge driver (1052inFIG.5) needed to develop an output voltage at the load. If such a SAR ADC is saturated, the corresponding loop filter (1046inFIG.5) is saturated and is slow to recover from such overload conditions, resulting in undesirable audio artifacts. Thus, it is desirable to have the SAR ADC and loop filter prevented from entering saturation. Such saturation-prevention can be accomplished by limiting the digital audio signal in digital path of the closed-loop circuit to prevent the closed-loop circuit from trying to generate an unachievable output voltage and thereby push the SAR ADC and loop filter into saturation.

Referring toFIG.6, the signal limiter1146can be configured to prevent the SAR ADC and loop filter from being in saturation due to insufficient supply voltage while trying to produce an output voltage from the corresponding digital input signal. The signal limiter1146can limit (e.g., by clipping the digital audio signal to a clip level) based on either or both of loop filter saturation detection signal (LF Sar. Det.) and SAR ADC output level (SAR ADC out) to keep the SAR ADC and the loop filter from overloading. It is noted that the SAR ADC output level can be monitored to have the signal limiter to clip the digital audio signal when the SAR ADC output level is close to saturation.

InFIG.6, the signal limiter block1146is shown to provide an output signal to a DAC modulator (e.g., delta sigma modulator (DSM))1148. As described above, such an output of the signal limiter block1146can be clipped to avoid the SAR ADC and loop filter from being in saturation. The output of the signal limiter block1146can also prevent the DAC DSM1148from overloading.

In the example ofFIG.6, the DAC DSM block1148can be configured to re-modulate a higher-bit input signal (e.g., 24-bit signal), through delta-sigma modulation, into a lower-bit signal (e.g., 9-bit signal) that is appropriate for a dynamic element matching (DEM) block1150. Accordingly, the example 9-bit DSM output signal drives the DEM block1150which can be implemented as a digital block configured to, for example, randomize a pattern of 512-bit cell drive to the DAC1044in a manner to linearize the DAC's response for use as a multi-bit delta-sigma DAC. Such a configuration can provide a desirable reference audio signal for the closed-loop circuit described herein.

InFIG.6, a feedforward signal is shown to be provided to a PWM controller (1050inFIG.5) from an output of the signal limiter1146through a path1043. As described herein, such a feedforward signal may or may not include a calibration tone signal mixed therein, depending on operating status of the gain calibration process.

In addition to the PDM LPF block1140, EQ block1142, mixer1144, signal limiter block1146, DSM block1148and DEM block1150that can be generally referred to as the digital audio path block1042,FIG.6also shows a number of blocks that support various functionalities of the audio amplifier circuit (1000inFIG.5). For example, a PDM detection block1060(also1060inFIG.5) is shown to be coupled to the PDM Rx block1040. The PDM detection block1060can be configured to detect one or more states of PDM digital audio interface, including one or more fault conditions, to support operation and control of the audio amplifier circuit1000.

In another example, a loudness protection block1066(also1066inFIG.5) is shown to be coupled to the PDM Rx block1040. The loudness protection block1066can be configured to monitor both of two output channels (main channel and auxiliary channel) of the PDM Rx block1040. Upon loudness detection (e.g., digital audio signal exceeding a threshold), the loudness protection block1066can issue a fault signal to provide a muting or fault condition functionality.

InFIG.6, the loudness protection block1066can include a pair of filter stages for the two output channels of the PDM Rx block1040. Each filter stage can include a cascaded low-pass filter and high-pass filter structure configured to approximate a frequency response such as an A-weighted frequency response. The filtered outputs can be provided to respective absolute value circuits, and outputs thereof can then be provided to comparator circuits and compared against a programmed threshold for each of the main channel, auxiliary channel and main-minus-auxiliary values. Logic outputs of the comparators can be sent to a multiplexer that can trigger a fault signal depending on a combination of the three comparator outputs.

InFIG.6, a number of functional blocks are shown to be coupled to and/or be related to one or more functional blocks of the digital audio path block1042. For example, a digital-to-analog converter (DAC)1044is shown to be coupled to an output of the DEM block1150. Such a DAC can be utilized to provide a reference signal for a closed-loop architecture of the audio amplifier circuit (1000inFIG.5). Additional details concerning the closed-loop architecture are described herein.

In another example, a HOR/ZOR state control block1062is shown to be coupled to the EQ block1142. Such a control block, along with a resistance control (Rout ctrl) block1064and a resistance network1080, can be utilized to provide various functionalities associated with high-output resistance (HOR) and zero-output resistance (ZOR) operating modes. Additional details concerning such operating modes are described herein.

In yet another example, a gain calibration block1070is shown to provide a calibration tone to the mixer1144based on inputs from signal limiter1146and a calibration ADC1084. Additional details concerning gain calibration of the audio amplifier circuit (1000inFIG.5) are described herein.

InFIG.6, operations of various functional blocks are shown to be supported by audio path registers1094. Such registers can be a part of or associated with the registers block1094ofFIG.5and be configured in a similar manner.

FIG.7shows a block diagram of an amplifier block1022that is a more specific example of the amplifier block1022ofFIG.5. The amplifier block1022ofFIG.7includes a digital PWM synthesis class D amplifier architecture. It is noted that unlike a purely analog class D amplifier architecture where pulse-width modulation (PWM) is analog, the amplifier architecture of the amplifier block1022includes pulse width modulation of H-bridge drivers being developed via digital pulse-width modulation by a digital PWM controller1050. The amplifier architecture of the amplifier block1022also includes a closed-loop control feature having a high loop gain error amplifier and an ADC digitizer.

As described in reference toFIG.6, a feedforward digital signal is provided to the PWM controller1050from the digital audio path1042of the digital logic circuit1020. More particularly, the feedforward digital signal is provided to the PWM controller1050from an output of the signal limiter block1146, through a signal path1043. InFIG.7, such a signal path is also indicated as1043.

As also described in reference toFIG.6, the digital signal from the output of the signal limiter block1146is also provided to the DAC1044through the DSM block1148and the DEM block1150. An analog signal from the output of the DAC1044is utilized as a reference audio signal for the above-referenced closed-loop of the amplifier block1022ofFIG.7.

Referring toFIG.7, it is noted that the feedforward digital audio signal that is provided to the PWM controller1050(through the path1043) is utilized to create most of a signal that determines pulse modulation for the H-bridge driver1052. More particularly, the PWM controller1050is shown to include a pulse generator1166that generates control signals HPP_ctrl, HOR_ctrl, HPN_ctrl based mostly on the feedforward digital audio signal provided through the path1043and a mixer1164. The control signal HPP_ctrl is provided to a ZOR HPP driver1170to generate an analog audio signal HPP when in a ZOR mode; the control signal HOR_ctrl is provided to an HOR driver1172to generate an analog audio signal HPP when in an HOR mode; and the control signal HPN_ctrl is provided to a ZOR/HOR HPN driver1174to generate an analog audio signal HPN when in either of the ZOR and HOR modes. The analog signals HPP and HPN are shown to drive a speaker1004to generate sound.

Referring toFIG.7, it is also noted that an error signal generated by the closed-loop is utilized to develop the remainder of the signal that determines pulse modulation for the H-bridge driver1052. Such an error signal is shown to be provided to the pulse generator1166from a successive approximation register (SAR) ADC1048through a digital loop filter (DLF)1162and the mixer1164. Such an error signal resulting from the closed-loop provides improved audio performance of the amplifier circuit. Examples related to such a closed-loop are described herein in greater detail.

In the example ofFIG.7, the H-bridge driver1052is shown to include a ZOR HPP driver1170, an HOR driver1172and a ZOR/HOR HPN driver1174, and a resistance network1080(also1080inFIG.6) is shown to include a sense resistance (Rs), HOR feedback resistances (Rh1, Rh2) and ZOR feedback resistances (Rz_p, Rz_n). With such drivers, a ZOR mode can be implemented so that the ZOR HPP (1170) and ZOR/HOR HPN (1174) drivers directly drive the speaker1004(with signals through HPP and HPN nodes), and the ZOR feedback resistances (Rz_p, Rz_n) of the resistance network1080directly sense the voltage across the speaker load (HPP and HPN). Accordingly, the ZOR HPP (1170) and ZOR/HOR HPN (1174) drivers are directly connected to the HPP and HPN nodes, and thus the speaker load, during the ZOR mode.

Referring toFIG.7, an HOR mode can be implemented so that the HOR feedback resistances (Rh1, Rh2) sense a voltage across the sense resistance Rs (e.g., an on-chip current sense resistor), where Rs can be adjusted to be same or close to the resistance (RL) of the speaker load. With such a configuration, the closed-loop operation can force the voltage signal across the sense resistance Rs to be representative of the input signal provided to the H-bridge driver1052. Accordingly, the resulting current through the speaker load causes an output voltage of the H-bridge driver1052to be equal to or representative of the input signal provided to the H-bridge driver1052times the speaker impedance.

It is noted that during the foregoing HOR mode operation, the ZOR HPP driver1170is turned off. It is also noted that the resistance Rs is in series with the HOR driver1172and the HPP node. Accordingly, the speaker load is driven through the high impedance of the HPP node. The ZOR/HOR HPN driver1174drives the other side of the speaker load.

It is noted that the foregoing HOR mode can be utilized to address a low-level electromagnetic-coupled noise problem. For example, the high output resistance mode can attenuate the noise at the speaker load. More particularly, in the HOR mode, the speaker load is driven in a high-output-impedance mode as a current source mode output instead of a voltage source mode output. Accordingly, the H-bridge driver1052forces a high-fidelity audio current waveform into the speaker load, regardless of load impedance, nonlinearities and/or noise injections.

The foregoing HOR mode can be calibrated an adjustment of the sense resistance Rs and a digital HOR calibration gain factor applied in one or more calibration blocks. In some embodiments, such gain calibration can be achieved periodically to equal the gain in the ZOR mode. Examples related to such gain calibration are described herein in greater detail.

In the example ofFIG.7, the PWM amplifier1022utilizes modulation frequency and supply voltage scheme to provide high performance and efficient operation of the H-bridge driver1052. The modulation frequency can have a value of several MHz for a pulse width update rate to provide an update period. Such an update period is divided into N ticks utilizing a clock signal. An output pulse width can range from 1 to M times the tick width. Accordingly, the output pulse width can have a minimum value of 1×(tick width) and a maximum value of M×(tick width).

Referring toFIG.7, the foregoing supply voltage scheme can include utilization of multiple supply voltages for the output pulses. For example, voltages VBAT>VDD_A>VDD_B>VDD_D>VDD_E can be provided to an H-bridge driver supply circuit1160for the output voltages. Such multiple voltages provided to the output pulses can provide improved efficiency during operations at different signal levels. For example, for lower level signals, lower voltages can be utilized; and for higher level signals, higher voltages can be utilized. To achieve such functionality, the H-bridge driver1052can include multiple driver transistors configured to allow dynamic switching of voltages to any of the multiple values based on encoded control signals from the PWM controller1050.

For example, and referring toFIG.7, the ZOR HPP and ZOR/HOR HPN drivers (1170,1174) are utilized for ZOR mode, and the HOR and ZOR/HOR HPN drivers (1172,1174) are utilized for HOR mode. Depending on the mode of operation (ZOR or HOR), amplitude of input signal and PWM encoding rules, the PWM controller1050connects the respective drivers to one of the available supplies provided through the H-bridge driver supply circuit1160to create a zero, positive or negative differential drive across the output load nodes HPP and HPN.

As described above, the PWM amplifier1022utilizes modulation frequency such that a pulse width update is provided during a corresponding period. Thus, the PWM controller1050can select the supply voltages and pulse width for the respective drivers. For example, the PWM controller1050can select the largest pulse width and lowest supply possible during each update period. Such selections of pulse width and supply voltage level can result in the lowest or reduced PWM quantization error and best or improved power efficiency.

Configured in the foregoing manner, the output of the H-bridge driver1052can be taken from the differential voltage on the HPP and HPN nodes and directly drive the speaker1004. It is noted that such an output differs from traditional class D amplifiers in that the foregoing output appears as high frequency, multi-voltage-level stepping/switching activity. Such voltage stepping activity is a notable property of the architecture of the PWM amplifier1022. For the ZOR mode of operation and for audio signals such as sine waves, the voltage level stepping can follow the envelope of the audio signal. In the HOR mode of operation, the HPP and HPN single-ended output switching appears different than in the ZOR mode. The behavior of the signal on the HPP and HPN nodes can depend on the polarity of the output signal. When measuring the HPP and HPN nodes single-ended to ground, during parts of the output signal cycle, the HPP and HPN waveforms may not resemble the audio envelope in the same way as in the ZOR mode. Such a difference can result from the HOR mode's selection of HPP node voltage that forces the PWM controller1050to produce switching behavior that holds the HPP node high. Therefore, the HPP node is held high for a significant part of the waveform cycle while the HPN node is switching.

In the PWM amplifier1022ofFIG.7, the closed-loop can be configured and operated as follows. As described herein, such a closed-loop can provide an error signal that is utilized for development of a signal that determines pulse modulation for the H-bridge driver1052, thereby providing improved audio performance of the amplifier circuit.

Referring toFIG.7, the outputs HPP and HPN of the H-bridge driver1052can be fed back to the summing nodes1081,1083through the resistance network1080. More particularly, the output node HPP is shown to be coupled to the summing node1081through a resistance Rz_p and a respective mixer also being provided with a ZOR mode signal as an input. Thus, the output of the mixer is shown to be added with a respective reference output of the DAC1044at the summing node1081; and the summed signal is shown to be provided to the loop filter1046. Similarly, the output node HPN is shown to be coupled to the summing node1083through a resistance Rz_n and a respective mixer also being provided with a ZOR mode signal as an input, such that the output of the mixer is shown to be added with a respective reference output of the DAC1044at the summing node1083; and the summed signal is shown to be provided to the loop filter1046.

Configured in the foregoing manner, the loop filter1046is provided with a signal representative of a differential error between the outputs (HPP, HPN) of the H-bridge driver1052and the reference signal provided by the DAC1044. In the example ofFIG.7, the each of the summing nodes1081,1083is shown to be provided with a signal from the common-mode limiting (CML) amplifier1082. Such signals from the CML amplifier1082can be utilized to limit the input common-mode voltage of the loop filter1046.

In the example ofFIG.7, the loop filter1046can include a 5th order high gain loop filter to provide an output to a low-power, high-speed SAR ADC1048to digitize the loop filter output. The digitized output of the SAR ADC1048is shown to be provided to the PWM controller1050, where it is utilized by the PWM controller1050along with the feedforward signal (provided through the path1043) to generate PWM control signals for the H-bridge driver1052.

Referring toFIG.7, it is noted that in the foregoing closed-loop, without any compensation, an inductance of the speaker's driver element can lead to significant differences in the open-loop frequency response at high frequencies (e.g., greater than 100 KHz) between the HOR and ZOR modes. Such an effect is due to the current-mode drive of the sense resistance working into the frequency dependent impedance of the speaker inductance during the HOR mode of operation.

In the closed-loop circuit ofFIG.7, the loop includes the loop filter1046, SAR ADC1048, PWM controller1050, H-bridge driver1052and resistance network1080. In addition to such components, a digital loop filter (DLF)1162can be provided to provide compensation for loop stability in situations where processing delays are present. In some embodiments, such a DLF can be configured to provide compensation by insertion of a programmable digital filter that includes parallel arrangement of finite impulse response (FIR) and infinite impulse response (IIR) sections, between the SAR ADC1048and the normal input location (mixer1164inFIG.7). Such a DLF can be configured to provide a response that includes phase compensation in response to the effect of the inductor in the HOR mode, as well as shaping of one or more characteristics of the closed-loop.

As described herein, when the PWM amplifier1022ofFIG.7is in ZOR mode, the gain is determined by the resistances of the resistance network1080working against the DAC (1044) output current. The feedback resistances (Rz_p, Rz_n) sense the voltage across the HPP and HPN nodes, and provides feedback to the loop filter inputs. The closed-loop with such a feedback can force the output of the PWM amplifier1022to be adjusted to equal or approximately equal the digital input with a net gain (e.g., G=1 such that a 0 dBFS input produces a 0 dBv output).

In HOR mode, however, the gain is determined differently, since the HOR mode utilizes a current-mode output where the signal current is produced across the sense resistance (Rs) and forced through the load resistance (Rload) of the speaker (1004inFIG.7). The HOR feedback resistances (Rh1, Rh2) sense the voltage across the sense resistance Rs, and such a sensed voltage works against the DAC output current. The closed-loop with such a feedback can force the output current gain of the PWM amplifier1022to be adjusted to be G=1/Rs. If there is no further adjustment, then the net end-to-end gain in the HOR mode would be G=Rload/Rs. If Rs and Rload are not equal to each other, then the HOR gain will not be equal to the gain in ZOR mode (G=1). To address such an effect, an audio amplifier circuit as described herein can configured to include an HOR gain calibration functionality utilizing, for example, adjustment of the sense resistance and a digital gain term to make the gain in HOR mode equal to or approximately equal to the gain in the ZOR mode. Examples related to such a gain calibration functionality are described herein in greater detail.

FIG.8shows a block diagram of a digital logic circuit block1020that is a more specific example of the digital logic circuit block1022ofFIG.5, implemented to operate with the H-bridge driver1052ofFIG.7to provide functionalities including mode switching between HOR and ZOR modes. Such mode switching can be achieved as follows.

It is noted that the audio amplifier circuit as described herein can provide dynamic switching between HOR and ZOR modes. Such mode-switching operation can include switching of the feedback resistance configurations of the resistance network (1080inFIG.8) between the output nodes (HPP, HPN) to the loop filter block (1046). Such mode-switching operation can be achieved in a dynamic manner with low audio artifacts. However, when switching between modes, because of the complex impedance of the speaker driver element and the current-mode operation in the HOR mode, the end-to-end frequency response of the system may change. If such a difference in frequency response is not compensated, the change may result in audible artifacts. To compensate for the change in frequency response, the audio amplifier circuit as described herein can include a digital EQ filter to allow compensation of the frequency response difference between the two modes.

In addition, to minimize the audible artifacts during HOR/ZOR transitions, the audio amplifier circuit as described herein can include a number of features. For example, the resistance network1080can be controlled to provide stepped output resistance Rout. In another example, a HOR/ZOR EQ block1142can be configured to operate with the stepped Rout values. In yet another example, a HOR/ZOR state control block1062can be provided and configured to control the HOR/ZOR transitions.

It is noted that an abrupt transition in the output resistance Rout seen by the speaker driver during HOR/ZOR transitions can cause a sufficiently large phase shift to be audible. To reduce or eliminate such audible artifacts, an amplifier equivalent Rout can be made to transition more gradually by moving through a series of Rout steps (e.g., six Rout steps) during a transition between HOR and ZOR modes. A set of particular Rout step values can be selected by selected values of feedback resistances Rh and Rz of the resistance network1080. Such Rout step values can be selected to produce approximately equal phase artifacts error per step. Further, time duration per step can be programmable over a modest range. Given a non-linear relationship between phase error and step size, Rout stepping as described herein can provide a significant impact on the reduction in the audibility of the artifacts.

As described in reference toFIG.6, an HOR/ZOR EQ block1142can be provided as part of the digital audio path1042.FIG.8shows that such an HOR/ZOR EQ block (also1142) can be implemented to operate with the foregoing Rout stepping functionality.

Referring toFIG.8, the HOR/ZOR EQ block1142is shown to be driven by the output of the PDM LPF block1140. The HOR/ZOR EQ block1142can be configured to provide filtering to compensate for the difference between the HOR and ZOR mode frequency responses driving the speaker transducer. The HOR/ZOR EQ block1142is shown to include an EQ filter bank, gain compute block and cross-fading functionality.

More particularly, the EQ filter bank is shown to include three parallel filter sections1200(Spare BQ),1202(Shelving) and1204(Bandpass) configured to compensate the frequency response in the speaker transducer. The filter section1200(Spare BQ) can be implemented as a low frequency 2nd order (biquad) bandpass filter section (e.g., up to 1 KHz). The filter section1202(Shelving) can be implemented as a 4th order finite impulse response (FIR) shelving filter. The filter1204(Bandpass) can be implemented as a 2nd order general purpose biquad filter.

Referring toFIG.8, the EQ block1142can be configured to optionally provide filtering to compensate for the difference between the HOR and ZOR mode frequency responses driving the speaker transducer. In addition to the foregoing EQ filter bank and the cross-fading functionality, the EQ block1142can also include a gain compute block1212.FIG.9shows a more specific configuration of such a gain compute block.

Referring toFIGS.8and9, the EQ block1142is shown to provide tapered in and out via a crossfading mixing structure of gains G1 and G2 (through mixers1208,1210) and an output adder1214.

More particularly, gain G1 is shown to be associated with mixing of an unfiltered output of the PDM LPF block1140with a non-EQ gain signal from the gain compute block1212at the mixer1208, and gain G2 is shown to be associated with mixing of a summed filtered signal with an EQ gain signal from the gain compute block1212at the mixer1210. The foregoing summed filtered signal is shown to be obtained by outputs of the filter sections1200,1202,1204being added by an adder1206. The input to each of the filter sections1200(Spare BQ) and the filter section1202(Shelving) is shown to be provided from the output of the PDM LPF block1140, and the input to the filter section1204(Bandpass) is shown to be provided from the input of the PDM LPF block1140.

Referring toFIGS.8and9, the gain value G1 is associated with a non-filtered signal, and the gain value G2 is associated with a filtered signal. The gains G1 and G2 can be values ranging from 0 to 1, where G1+G2=1, and in the example context of Rout having six steps, each of G1 and G2 can have six discrete step values of 0, 0.2, 0.4, 0.6, 0.8 and 1. As described herein, such gain values can be stepped with the Rout stepping of the audio amplifier circuit.

Referring toFIG.9, the gain compute block1212is shown to be configured to generate the non-EQ gain signal (to the mixer1208inFIG.8) and the EQ gain signal (to the mixer1210) based on a number of inputs. For example, the gain compute block1212can handle slowly changing gain parameters such as HOR/ZOR gain, user gain, HOR calibration gain, and EQ biquad gain. Based on some or all of such inputs, and depending on the operating mode (ZOR or HOR), the gain compute block1212can compute net EQ path gain and non-EQ path gain values and provide such gain values as outputs.

More particularly, the user gain is shown to be processed through a gain ramp1220and provided to a mode gain multiplexer1222that also receives a HOR mode signal. The mode gain multiplexer1222is shown to generate ZOR gain and HOR gain and provide such outputs to a multiplexer1226, with the latter being mixed with a HOR calibration gain value by a mixer1224. The multiplexer1226is shown to provide the non-EQ gain and EQ gain values based on the ZOR gain and HOR gain values, along with an EQ select input. The EQ gain value is shown to result from mixing of the respective output of the multiplexer1226with the EQ biquad gain by a mixer1228.

Configured in the foregoing manner, the gain compute block1212can provide some or all of the following functionalities: provide a gain stage for digital audio gain adjustment, provide an amplifier state initiated gain ramp-up after start of audio, provide an amplifier initiated gain ramp-down before shutdown of audio, provide a gain stage for HOR/ZOR fine gain calibration (e.g., HOR calibration gain) where the fine gain calibration can be applied in all HOR modes (full and partial), provide gain control for a programmable ramp time, and provide a test mode programmable volume gain register to mute gain block with a variable attenuation step size to provide a desired dynamic range.

Configured as described above in reference toFIGS.8and9, the HOR/ZOR EQ block1142can provide some or all of the following functionalities: enabling or bypassing of EQ functionality, compensating for transducer impedance vs frequency with a multi-section filter, switching in and out of the audio path with minimal or reduced audio artifacts, tracking of output resistance Rout, programmable filter coefficients, minimized or reduced latency, and provide EQ filtering active for HOR or ZOR mode and off for the other.

FIG.8also shows an HOR/ZOR state control block1062that can be a more specific example of the HOR/ZOR state control block1062ofFIGS.5and6. In the example ofFIG.8, the HOR/ZOR state control block1062can determine when to switch between HOR and ZOR modes by observing the audio signal path. Such a switching can be controlled so that audible artifacts due to switching are minimized or reduced. In some embodiments, HOR/ZOR switching can be configured to maximize or increase time in the ZOR mode for efficiency, but prioritize HOR mode when audio signal is low in order to minimize or reduce injected interference. The HOR/ZOR state control block1062can include an HOR/ZOR Rout mode control block1190that utilizes, for example, psychoacoustic principles, to mask or reduce transient artifacts during mode switching operations.

Referring toFIG.8, the HOR/ZOR state control block1062can provide some or all of the following functionalities. First, the audio amplifier circuit can be placed in HOR mode when amplitude of the digital audio signal (e.g., obtained from the input side of the PDM LPF1140) is low in order to minimize or reduce injected interference. Second, the audio amplifier circuit can be placed in ZOR mode when amplitude of the digital audio signal is high in order to improve efficiency. Third, transition time from ZOR to HOR mode can be made to be within a selected time duration. Fourth, Rout transitions can be made without or reduced audible artifacts. Fifth, HOR/ZOR target mode can be determined by an average audio level. Sixth, HOR/ZOR switching time can be set to be when the transition will be inaudible as determined by a combination of configurable factors such as crest factor, audio signal level being below a threshold value, and time from the last Rout change. Seventh, HOR/ZOR output impedance can have multiple (e.g., 6) steps corresponding to the Rout modes (e.g., Rour0, Rout1, Rout2, Rout3, Rout4, Rout5). Eighth, HOR/ZOR impedance steps can be controlled by moving from current impedance step toward the target impedance step when transitions are determined to be inaudible. Ninth, HOR/ZOR transitions can be programmable to step through discrete output impedances in order to minimize or reduce switching transients (e.g., output impedance step controls being implemented to correspond to output impedance steps of the audio amplifier). Tenth, HOR/ZOR transitions can be independently configured to occur with a minimum or reduced time between switching. Eleventh, HOR/ZOR mode can have a manual override configured by resister access, and such an override can be configured to allow setting of all mode and/or Rout settings.

In the example ofFIG.8, switching between HOR and ZOR modes can be achieved as follows. Switching between HOR and ZOR modes can include operations of the resistance network1080, the HOR/ZOR EQ block1142, and the HOR/ZOR state control block1062.

Referring toFIG.8and the foregoing HOR/ZOR switching functionality, the resistance network108can be utilized to provide an Rout stepping functionality as described herein. It is noted that an abrupt transition in Rout seen by the speaker driver during HOR/ZOR transitions can cause a sufficiently large phase shift to be audible. To reduce such audible artifacts, an amplifier equivalent Rout can be made to transition more gradually be moving through a number of Rout steps (e.g., 6 steps) during a transition between HOR and ZOR modes. Such stepped Rout values can be achieved through selection of resistance values for Rh and Rz implemented as, for example, variable resistors. The equivalent Rout steps can be selected to produce approximately equal phase artifact error per step, and the time per step can be programmed over a selected range. Given the non-linear relationship between phase error and step size, Rout stepping functionality can provide a significant impact on the reduction in the audibility of the artifacts during HOR/ZOR transitions.

Referring toFIG.8and the foregoing HOR/ZOR switching functionality, the HOR/ZOR EQ block1142can be configured to provide EQ filtering functionality including EQ filtering functionality for compensation of the difference in frequency responses between HOR and ZOR modes as described herein. The HOR/ZOR EQ block1142can be configured to operate with such EQ filtering functionality during the HOR or ZOR mode. In some embodiments, some or all of the EQ block1142can be disabled in the HOR mode to save power, and be enable during the ZOR mode if desired or needed. It is noted that if the foregoing Rout stepping functionality is utilized, the EQ filter response can be synchronized to be gradually stepped with a corresponding change in the Rout.

Referring toFIG.8and the foregoing HOR/ZOR switching functionality, the HOR/ZOR state control block1062can be configured to decide when to switch between HOR and ZOR modes by monitoring the audio signal path. For example, audio signal path before and after the PDM LPF block1140can be monitored.

Referring toFIG.8, the node on the input side of the PDM LPF block1140is shown to be coupled to a decimation circuit1180configured decimate the sampled signal by N (e.g., N=128). The decimated signal is then shown to be provided to a block1182for low audio detection, a block1184for generating a target mode, and a block1186for selecting an Rout step. Outputs of the blocks1182,1184,1186are shown to be provided to a HOR/ZOR Rout mode control block1190. Referring toFIG.8, the node on the output side of the PDM LPF block1140is shown to be coupled to an audio switch block1188that provides its output to the HOR/ZOR Rout mode control block1190.

Configured in the foregoing manner, the HOR/ZOR state control block1062can determine when to switch between HOR and ZOR modes. Such determination can be based on some or all of a number of conditions. For example, an average of the sampled input signal can be obtained and compared to a threshold value. More particularly, a determination of whether the average of the sampled signal is greater than a HOR-to-ZOR threshold value can be made when in HOR mode, or whether the average of the sampled signal is less than a ZOR-to-HOR threshold value can be made when in ZOR mode. In another example, a determination of whether the input signal has a very low level can be made. In yet another example, the input signal can be passed through a high-pass filter, and a peak in such a filtered signal can be compared to a product of an average of the filtered signal and a crest factor. If the peak value is greater than the product, and if the input signal is at or near a zero crossing, a determination can be made to perform a mode-switching operation.

It is noted that the foregoing HOR-to-ZOR threshold value and ZOR-to-HOR threshold value may or may not be different.

For a HOR-to-ZOR transition, determination can be made as to whether the input signal level has crossed a respective threshold level, and whether a favorable transition condition (e.g., high crest factor, higher frequency masking event and a subsequent zero crossing). If so, the HOR-to-ZOR transition can be made to proceed. For a ZOR-to-HOR transition, determination can be made as to whether the input signal level has crossed a respective threshold level or has become sufficiently small, and whether a favorable transition condition (e.g., high crest factor, higher frequency masking event and a subsequent zero crossing). If so, the ZOR-to-HOR transition can be made to proceed. The foregoing transition techniques allow the audio amplifier to operate to deliver full output power in either HOR or ZOR modes, thus enabling the audio amplifier to remain in either mode until a favorable transition condition is present to thereby avoid audible artifacts.

As described herein, HOR mode gain is determined differently than ZOR mode gain. However, it is desirable to operate an audio amplifier circuit as described herein so that a net gain in the HOR mode is equivalent to a net gain in the ZOR mode. In some embodiments, HOR gain can be adjusted so to be equivalent to ZOR gain. In various examples described herein, such a ZOR gain can be considered to have a gain G=1; thus, HOR gain can be calibrated to also provide a gain G=1. Such a HOR gain calibration can be achieved as follows.

FIG.10shows various functional blocks of the audio amplifier circuit1000ofFIG.5, where such blocks can form an HOR gain calibration sub-system. More particularly, such a sub-system can include a gain calibration block1070, a gain calibration ADC1084, an Rout controller1064, a resistance network1080, and an HOR/ZOR EQ block1142.FIG.11shows a more detailed example of the gain calibration block1070ofFIG.10.

Referring toFIGS.10and11, the gain calibration block1070can be implemented as a digital block that includes a gain calibration processor1230and a gain calibration controller1238. The gain calibration processor1230can be configured to perform gain estimation computation for HOR mode, and based on such gain estimation, desired sense resistance (Rs inFIGS.7and8) value and digital gain correction value can be determined. The gain calibration controller1238can handle overall management of the gain calibration sub-system, including determining when to calibrate and/or determining conditions for a valid calibration.

Referring toFIGS.10and11, the gain calibration ADC1084can be implemented as an analog block that digitizes the differential amplifier output HPP-HPN during a calibration cycle to use by the foregoing gain calibration processor1230. The gain calibration ADC1084can be configured (e.g., with delta-sigma modulation) to handle large audio signals at the output (HPP, HPN) and have a sufficiently large dynamic range to detect the relatively lower amplitude calibration tone signal.

Referring toFIG.11, the gain calibration processor1230is shown to include a calibration tone generator1232configured to generate an ultrasonic calibration tone (Cal. tone) which is mixed into the digital audio stream with the mixer1144before the signal limiter block1146. The tone generator1232can also be configured to provide programmable frequency and amplitude functionalities. In some embodiments, the tone generator1232can produce a sinusoidal output modulated with, for example, a 2nd order cascaded integrator-comb (CIC) filtered pulse to prevent audible energy during turning on and off of the tone generator1232.

Referring toFIGS.10and11, the Rout controller1064can be implemented as a digital block that performs computations to determine and control the sense resistance (Rs) setting in the analog resistance network1080. The Rout controller1064can also perform computations to determine a digital fine gain value that is provided to the HOR/ZOR EQ block1142for use in a fine gain adjustment.

Referring toFIGS.10and8, the resistance network1080can be implemented as an analog block that includes a programmable sense resistance (Rs) network, and programmable ZOR and HOR Rout mode feedback resistances (Rz and Rh). Such a resistance network is shown to be controlled by the Rout controller1064.

Referring toFIGS.10and11, and as described above, the HOR/ZOR EQ block1142and its gain compute block (1212inFIGS.8and9) can provide a gain multiplier functionality where HOR digital calibration gain is applied. Such an application of the HOR digital calibration gain can be based on a control signal (HOR Cal fine gain) provided by the Rout controller1064.

Configured in the foregoing manner, the gain calibration processor1230can compute a gain mismatch between HOR and ZOR modes by introducing a calibration tone (e.g., an ultrasonic tone at ˜25 KHz) into the digital audio stream at the mixer1144before the signal limiter block1146. The digital audio stream with the calibration tone mixed therein is passed through the signal limiter block1146. At the output of the signal limiter block1146, the digital audio stream is routed through path1043to the PWM controller (1050inFIG.8) to be processed and amplified by the H-bridge driver1052to provide an output at HPP and HPN. Also at the output of the signal limiter block1146, the digital audio stream is obtained for the gain calibration processor1230as a reference signal. Thus, the magnitude and phase of the output signal at the output (HPP, HPN) can be compared relative to the magnitude and phase of the reference signal.

To achieve the foregoing comparison of the output signal (analog signal) with the reference signal (digital signal), the gain calibration ADC1084can sample the output voltage across the load (HPP-HPN) and provide a delta-sigma ADC output to the gain calibration processor1230. Measurement and computation of the HOR and ZOR gains can be performed by the gain calibration processor1230(e.g., with a gain compute block1236) utilizing an estimation algorithm where the reference signal X and the digitized output signal Y are downconverted with a tone at the same frequency as the calibration tone (e.g., 25 KHz). The downconverted signals X and Y can be filtered (e.g., single-bin fast Fourier transform (FFT) with a discrete Fourier transform (DFT) block1234) to provide respective complex downconverted values x and y. A ratio of the two complex downconverted values can be obtained, where Ratio=y/x. It is noted that complex values can be utilized so that the load inductance does not significantly affect the gain calculation; however, the real component of the Ratio is utilized.

The foregoing Ratio=y/x is an expression of a transfer function gain from the digital input to the amplifier output, and can be designed to be tolerant to out-of-band interference. Ratio can be computed for each of the HOR and ZOR modes, such that Ratio(HOR)=y/x in the HOR mode, and Ratio(ZOR)=y/x in the ZOR mode.

The calibration processor1230can then compute another ratio Relative_HOR_gain=Ratio(HOR)/Ratio(ZOR) which is representative of the HOR gain relative to the ZOR gain. Ideally, this ratio Relative_HOR_gain has a value of 1.

Referring toFIG.11, the computed Relative_HOR_gain value is shown to be provided to the Rout control block1064by the gain calibration controller1238. Based on such a computed Relative_HOR_gain value, the Rout control block1064can determine an adjustment to the sense resistance (Rs) and a fine gain (HOR Cal fine gain inFIG.10) control signal to be applied to the digital path by the gain compute block1212of the HOR/ZOR EQ block1142.

More particularly, the Rout control block1064can obtain the Relative_HOR_gain value and perform computations to determine how to change the sense resistance (Rs) relative to its present setting. Based on the change it makes to the sense resistance (Rs) setting, the Rout control block1064can compute the digital fine gain adjustment needed to make the Relative_HOR_gain value to be 1.

A PWM amplifier as described herein can be configured to operate with multiple supply voltages to provide desired performance for both low and high level signals. For example, the H-bridge driver1052of the PWM amplifier1022in each ofFIGS.5and7is shown to be provided with supply voltages VBAT, VDD_A, VDD_B, VDD_D and VDD_E, with VBAT>VDD_A>VDD_B>VDD_D>VDD_E. In such an example PWM amplifier, the four larger voltages (VBAT, VDD_A, VDD_B, VDD_D) can be obtained from one or more external sources, and the smallest voltage (VDD_E) can be obtained from an internal source.

In some embodiments, the foregoing internal source voltage (VDD_E) can be obtained from a low voltage monitor (LVM) block indicated as1132in each ofFIGS.5and7. In some embodiments, such a voltage (VDD_E) can be provided to the H-bridge driver1052. In some embodiments, the voltage VDD_E can also be provided to an external location through a voltage node indicated as VDD_E.

FIG.12shows a circuit diagram of a low voltage system100that can be utilized in an audio amplifier having one or more features as described herein. In some embodiments, such a system can include a low voltage monitoring circuit102(1132inFIG.7), a controller110(1050inFIG.7), an H-bridge driver circuit112(1052inFIG.7), and a capacitor C. As described herein, such a system can allow low voltage operation of an audio amplifier, such as the PWM amplifier1022ofFIG.7, without a need for an external low voltage supply. It will be understood that while various examples are described herein in the context of such a PWM amplifier, one or more features of the present disclosure can also be implemented with other types of amplifiers, including other types of audio amplifiers.

InFIG.12, the H-bridge driver112is shown to be provided with a supply voltage VDD1. As described herein, such a voltage (VDD1) can be the lowest supply voltage (VDD_E inFIG.7). In some embodiments, such a supply voltage (VDD1) can be maintained with use of the capacitor C and charging/discharging of the capacitor C based on monitoring of the supply voltage VDD1as described herein.

FIG.12shows that in some embodiments, the low voltage monitoring circuit102can include a comparator106that compares a voltage at an output node120of a P/N driver104with a reference voltage Vref. The output node120is also shown to be connected to the supply voltage node VDD1.

InFIG.12, the P/N driver104is shown to include an arrangement of a PMOS device having its source coupled to a supply voltage (VDD2) node and its drain coupled to the drain of an NMOS device. The source of the NMOS device is shown to be coupled to a ground. The gate of the PMOS device is shown to be provided with a control signal UP, and the gate of the NMOS device is shown to be provided with a control signal DN. Thus, the P/N driver104can provide an output voltage at the node120based on the control signals UP and DN.

In the example ofFIG.12, the supply voltage VDD2for the P/N driver104is greater than the supply voltage VDD1.

Referring toFIG.12, an output of the comparator106is shown to be provided to the PWM controller110. Such a controller is shown to provide the UP and DN control signals to the P/N driver104based on the output of the comparator106.

InFIG.12, the PWM controller110is also shown to provide control signal Ctrl_R for controlling a resistance R of a variable resistor of a reference voltage circuit. Such a reference voltage circuit is shown to include a current source108coupled to ground through the resistor R, with the reference voltage Vref being obtained from a node between the current source108and the resistor R.

InFIG.12, the PWM controller110is also shown to provide a control signal (PWM code) to the H-bridge driver112. The H-bridge driver112is shown to be coupled to the supply node VDD1(which is also the output node120of the P/N driver104) so as to allow the speaker114to be driven according to the control signal (PWM code).

InFIG.12, the capacitor C is shown to couple the output node120of the P/N driver104to ground. In some embodiments, the capacitor C can be an external capacitor that is outside of a die having the PWM amplifier. In some embodiments, the capacitor C can be implemented as part of a die having the PWM amplifier.

Configured in the foregoing manner, the low voltage system100ofFIG.12can provide a low voltage supply for use in low level operation of the H-bridge driver112. Such a functionality reduces the power consumption associated with regulation of a low voltage, since the power that would normally be lost in regulation is output to the load instead. It is noted that PWM Class D operation on a low supply reduces switching losses proportional to CV2, and also reduces noise in the system.

In the system100ofFIG.12, low voltage regulation can be achieved by monitoring the voltage on the capacitor C (at the output node120) and configuring switching operations of the H-bridge driver112to charge or discharge the capacitor C, depending on whether the monitored voltage is higher or lower than a selected value representative of a desired value for the supply voltage VDD1. Such a selected value can be programmable and/or dynamic if desired. In some embodiments, a programmable selected value can allow control of an idle output common mode of the amplifier.

As described herein, the low voltage monitoring circuit102monitors the voltage of the capacitance C at the output node120to determine if it is higher or lower than the reference voltage Vref. In some embodiments, such a reference voltage can be a voltage from a software controllable reference source.

In an example operation, during each PWM cycle, the programmable reference voltage can be stepped to track the voltage on the capacitor C in real or approximately real time. The reference voltage Vref can be realized with a fixed current into the variable resistance R that, in some embodiments, can be implemented as a programmable resistor ladder; and such a fixed current through the resistance R can generate the reference voltage Vref being provided to the comparator106.

If the voltage on the capacitor C is high, next output pulse can be generated by connecting the load between the capacitor C and ground, thereby reducing the voltage on the capacitor C. If the voltage on the capacitor is low, the next output pulse can be generated by connecting the load between the capacitor C and the lowest available supply (VDD1), thereby increasing the voltage on the capacitor C.

In some embodiments, an extension on the foregoing operation can add a programmable amount to any “charge pulse” to deliver more charge to the capacitor C per pulse, which improves the ratio of charge delivered vs power dissipated switching the output stage.

In the example ofFIG.12, the foregoing charging and discharging of the capacitor C can be achieved by application of the respective pulses (e.g., PWM codes) to the H-bridge driver112. Accordingly, the charging and discharging of the capacitor C to maintain a desire value of the supply voltage VDD1are collectively indicated as122.

FIG.13shows the low voltage system100ofFIG.12being operated with specific example settings. InFIG.13, the capacitor C has a capacitance value of approximately 300 nF, the PMOS device has an effective resistance of approximately 200 ohm, and the NMOS device has an effective resistance of approximately 25 ohms.

FIG.14shows examples of various signal traces during the operation of the low voltage system100ofFIG.13.

Referring toFIGS.13and14, examples of switching operation can involve some or all of the following situations. If a positive drive is needed and the capacitor C needs to be charged, the amplifier's positive output (out+) can be connected to the lowest available external supply, and the negative output (out−) can be connected to the capacitor C. InFIG.14, such an operating configuration is depicted on the left side of the charging case, where the example lowest available external supply is VDD_D, with VDD_D>VDD_E.

If a negative drive is needed and the capacitor C needs to be charged, out− can be connected to the lowest available external supply, and out+ can be connected to the capacitor C. InFIG.14, such an operating configuration is depicted on the right side of the charging case.

If a positive drive is needed and the capacitor C needs to be discharged, out+ can be connected to the capacitor C, and out− can be connected to ground. InFIG.14, such an operating configuration is depicted on the left side of the discharging case.

If a negative drive is needed and the capacitor needs to be discharged, out− can be connected to the capacitor C, and out+ can be connected to ground. InFIG.14, such an operating configuration is depicted on the right side of the discharging case.

In some situations, the system may require additional decision making criteria, not all switching options may be available at all times, and the low voltage operation cannot be guaranteed to stay within regulation limits over all conditions. To ensure that the supply voltage stays within a desired range, a pullup or pulldown switch can be activated to return the system to regulation.

In some embodiments, if the pullup or pulldown is activated for too many cycles in a row, the system can be assumed to have lost regulation. In such a situation, the low voltage operation can be automatically disabled, and the lowest externally available supply can be utilized.

In some situations, there may be output conditions that move the voltage on the capacitor C faster than the reference can track. In some embodiments, a modified mode of the low voltage system can allow the reference to be moved by more than one code per cycle in order to track the voltage when high current is in the load. If the code needs to change in the same direction for a programmable number of consecutive cycles, the modified mode can be enabled and the code can be changed by a programmable amount each cycle until the reference catches up.

The present disclosure describes various features, no single one of which is solely responsible for the benefits described herein. It will be understood that various features described herein may be combined, modified, or omitted, as would be apparent to one of ordinary skill. Other combinations and sub-combinations than those specifically described herein will be apparent to one of ordinary skill, and are intended to form a part of this disclosure. Various methods are described herein in connection with various flowchart steps and/or phases. It will be understood that in many cases, certain steps and/or phases may be combined together such that multiple steps and/or phases shown in the flowcharts can be performed as a single step and/or phase. Also, certain steps and/or phases can be broken into additional sub-components to be performed separately. In some instances, the order of the steps and/or phases can be rearranged and certain steps and/or phases may be omitted entirely. Also, the methods described herein are to be understood to be open-ended, such that additional steps and/or phases to those shown and described herein can also be performed.

Some aspects of the systems and methods described herein can advantageously be implemented using, for example, computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software can comprise computer executable code stored in a computer readable medium (e.g., non-transitory computer readable medium) that, when executed, performs the functions described herein. In some embodiments, computer-executable code is executed by one or more general purpose computer processors. A skilled artisan will appreciate, in light of this disclosure, that any feature or function that can be implemented using software to be executed on a general purpose computer can also be implemented using a different combination of hardware, software, or firmware. For example, such a module can be implemented completely in hardware using a combination of integrated circuits. Alternatively or additionally, such a feature or function can be implemented completely or partially using specialized computers designed to perform the particular functions described herein rather than by general purpose computers.

Multiple distributed computing devices can be substituted for any one computing device described herein. In such distributed embodiments, the functions of the one computing device are distributed (e.g., over a network) such that some functions are performed on each of the distributed computing devices.

Some embodiments may be described with reference to equations, algorithms, and/or flowchart illustrations. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented as computer program products either separately, or as a component of an apparatus or system. In this regard, each equation, algorithm, block, or step of a flowchart, and combinations thereof, may be implemented by hardware, firmware, and/or software including one or more computer program instructions embodied in computer-readable program code logic. As will be appreciated, any such computer program instructions may be loaded onto one or more computers, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer(s) or other programmable processing device(s) implement the functions specified in the equations, algorithms, and/or flowcharts. It will also be understood that each equation, algorithm, and/or block in flowchart illustrations, and combinations thereof, may be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer-readable program code logic means.

Furthermore, computer program instructions, such as embodied in computer-readable program code logic, may also be stored in a computer readable memory (e.g., a non-transitory computer readable medium) that can direct one or more computers or other programmable processing devices to function in a particular manner, such that the instructions stored in the computer-readable memory implement the function(s) specified in the block(s) of the flowchart(s). The computer program instructions may also be loaded onto one or more computers or other programmable computing devices to cause a series of operational steps to be performed on the one or more computers or other programmable computing devices to produce a computer-implemented process such that the instructions which execute on the computer or other programmable processing apparatus provide steps for implementing the functions specified in the equation(s), algorithm(s), and/or block(s) of the flowchart(s).

Some or all of the methods and tasks described herein may be performed and fully automated by a computer system. The computer system may, in some cases, include multiple distinct computers or computing devices (e.g., physical servers, workstations, storage arrays, etc.) that communicate and interoperate over a network to perform the described functions. Each such computing device typically includes a processor (or multiple processors) that executes program instructions or modules stored in a memory or other non-transitory computer-readable storage medium or device. The various functions disclosed herein may be embodied in such program instructions, although some or all of the disclosed functions may alternatively be implemented in application-specific circuitry (e.g., ASICs or FPGAs) of the computer system. Where the computer system includes multiple computing devices, these devices may, but need not, be co-located. The results of the disclosed methods and tasks may be persistently stored by transforming physical storage devices, such as solid state memory chips and/or magnetic disks, into a different state.

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

The disclosure is not intended to be limited to the implementations shown herein. Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention provided herein can be applied to other methods and systems, and are not limited to the methods and systems described above, and elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.