Patent ID: 12218128

DETAILED DESCRIPTION

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIGS.1and2A-2Dillustrate structure of a bidirectional switching device11according to some embodiments of the present invention.FIG.1is a partial layout of the bidirectional switching device11showing a relationship among some elements that can constitute parts of transistors in the bidirectional switching device11.FIGS.2A-2Dare cross-sectional views taken along lines A-A′, B-B′, C-C′ and D-D′ inFIG.1respectively. More structural details of the bidirectional switching device11are provided as follows.

Referring toFIGS.1and2A-2D, the bidirectional switching device11may include a substrate102, a first nitride-based semiconductor layer104, a second nitride-based semiconductor layer106, gate structures110, S/D electrodes116, a first passivation layer124, a second passivation layer126, a third passivation layer128, one or more first conductive vias132, one or more second conductive vias136, one or more first conductive traces142, one or more second conductive traces146, a protection layer154and one or more through gallium vias (TGV)162and conductive pads170.

The substrate102may be a semiconductor substrate. The exemplary materials of the substrate102can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI), or other suitable semiconductor materials. In some embodiments, the substrate102can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the substrate102can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The nitride-based semiconductor layer104is disposed over the substrate102. The exemplary materials of the nitride-based semiconductor layer104can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(1−x−y)N where x+y≤1, AlyGa(1−y)N where y≤1. The exemplary structures of the nitride-based semiconductor layer104can include, for example but are not limited to, multilayered structure, superlattice structure and composition-gradient structures.

The nitride-based semiconductor layer106is disposed on the nitride-based semiconductor layer104. The exemplary materials of the nitride-based semiconductor layer106can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(1−x−y)N where x+y≤1, AlyGa(1−y)N where y≤1.

The exemplary materials of the nitride-based semiconductor layers104and106are selected such that the nitride-based semiconductor layer106has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer104, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer104is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer106can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers104and106can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. Accordingly, the bidirectional switching device is available to include one or more GaN-based high-electron-mobility transistors (HEMT).

In some embodiments, the bidirectional switching device11may further include a buffer layer, a nucleation layer, or a combination thereof (not illustrated). The buffer layer can be disposed between the substrate102and the nitride-based semiconductor layer104. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate102and the nitride-based semiconductor layer104, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

The nucleation layer may be formed between the substrate102and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate102and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to MN or any of its alloys.

The gate structures110are disposed on/over/above the second nitride-based semiconductor layer. Each of the gate structures110may include an optional gate semiconductor layer112and a gate metal layer114. The gate semiconductor layer112and the gate metal layer114are stacked on the nitride-based semiconductor layer106. The gate semiconductor layer112are between the nitride-based semiconductor layer106and the gate metal layer114. The gate semiconductor layer112and the gate metal layer144may form a Schottky barrier. In some embodiments, the bidirectional switching device11may further include an optional dielectric layer (not illustrated) between the p-type doped III-V compound semiconductor layer112and the gate metal layer114.

The nitride-based bilateral transistor Qm, the first substrate-coupling transistor Q1and the second substrate-coupling transistor Q2may be enhancement mode devices, which are in a normally-off state when their gate electrodes114are at approximately zero bias. Specifically, the gate semiconductor layer112may be a p-type doped III-V compound semiconductor layer. The p-type doped III-V compound semiconductor layer112may create at least one p-n junction with the nitride-based semiconductor layer106to deplete the 2 DEG region, such that at least one zone of the 2 DEG region corresponding to a position below the corresponding gate structure110has different characteristics (e.g., different electron concentrations) than the rest of the 2 DEG region and thus is blocked. Due to such mechanism, the bidirectional switching device11has a normally-off characteristic. In other words, when no voltage is applied to the gate electrodes114or a voltage applied to the gate electrodes114is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate structures110), the zone of the 2 DEG region below the gate structures110is kept blocked, and thus no current flows therethrough. Moreover, by providing the p-type doped III-V compound semiconductor layers112, gate leakage current is reduced and an increase in the threshold voltage during the off-state is achieved.

In some embodiments, the p-type doped III-V compound semiconductor layers112can be omitted, such that the bidirectional switching device11is a depletion-mode device, which means the transistors are in a normally-on state at zero gate-source voltage.

The exemplary materials of the p-type doped III-V compound semiconductor layers112can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.

In some embodiments, the nitride-based semiconductor layer104includes undoped GaN and the nitride-based semiconductor layer106includes AlGaN, and the p-type doped III-V compound semiconductor layers112are p-type GaN layers which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2 DEG region, so as to place the bidirectional switching device11into an off-state condition.

In some embodiments, the gate electrodes114may include metals or metal compounds. The gate electrodes114may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the gate electrodes114may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiOxlayer, a SiNxlayer, a high-k dielectric material (e.g., HfO2, Al2O3, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, etc), or combinations thereof.

The S/D electrodes116are disposed on the nitride-based semiconductor layer106. The “S/D” electrode means each of the S/D electrodes116can serve as a source electrode or a drain electrode, depending on the device design. The S/D electrodes116can be located at two opposite sides of the corresponding gate structure110although other configurations may be used, particularly when plural source, drain, or gate electrodes are employed in the device. Each of the gate structure110can be arranged such that each of the gate structure110is located between the at least two of the S/D electrodes116. The gate structures110and the S/D electrodes116can collectively act as at least one nitride-based/GaN-based HEMT with the 2 DEG region.

In the exemplary illustration, the adjacent S/D electrodes116are symmetrical about the gate structure110therebetween. In some embodiments, the adjacent S/D electrodes116can be optionally asymmetrical about the gate structure110therebetween. That is, one of the S/D electrodes116may be closer to the gate structure110than another one of the S/D electrodes116.

In some embodiments, the S/D electrodes116can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the S/D electrodes116can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The S/D electrodes116may be a single layer, or plural layers of the same or different composition. In some embodiments, the S/D electrodes116may form ohmic contacts with the nitride-based semiconductor layer106. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the S/D electrodes116. In some embodiments, each of the S/D electrodes116is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The passivation layer124is disposed over the nitride-based semiconductor layer106. The passivation layer124can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements). The passivation layer124covers a top surface of the nitride-based semiconductor layer106. The passivation layer124may cover the gate structures110. The passivation layer124can at least cover opposite two sidewalls of the gate structures110. The S/D electrodes116can penetrate/pass through the passivation layer124to contact the nitride-based semiconductor layer106. The exemplary materials of the passivation layer124can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, nitrides, poly(2-ethyl-2-oxazoline) (PEOX), or combinations thereof. In some embodiments, the passivation layer124can be a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

The passivation layer126is disposed above the passivation layer124and the S/D electrodes116. The passivation layer126covers the passivation layer124and the S/D electrodes116. The passivation layer126can serve as a planarization layer which has a level top surface to support other layers/elements. The exemplary materials of the passivation layer126can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof. In some embodiments, the passivation layer126is a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

The conductive vias132are disposed within the passivation layer126and passivation layer124. The conductive vias132penetrate the passivation layer126and passivation layer124. The conductive vias132extend longitudinally to electrically couple with the gate structure110and the S/D electrodes116, respectively. The upper surfaces of the conductive vias132are free from coverage of the passivation layer126. The exemplary materials of the conductive vias132can include, for example but are not limited to, conductive materials, such as metals or alloys.

The conductive traces142are disposed on the passivation layer126and the conductive vias132. The conductive traces142are in contact with the conductive vias132. The conductive traces142may be formed by patterning a conductive layer disposed on the disposed on the passivation layer126and the conductive vias132. The exemplary materials of the conductive traces142can include, for example but are not limited to, conductive materials. The conductive traces142may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The passivation layer128is disposed above the passivation layer126and the conductive traces142. The passivation layer128covers the passivation layer126and the conductive traces142. The passivation layer128can serve as a planarization layer which has a level top surface to support other layers/elements. The exemplary materials of the passivation layer128can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof. In some embodiments, the passivation layer128is a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

The conductive vias136are disposed within the passivation layer128. The conductive vias136penetrate the passivation layer128. The conductive vias136extend longitudinally to electrically couple with the conductive traces142. The upper surfaces of the conductive vias136are free from coverage of the passivation layer136. The exemplary materials of the conductive vias136can include, for example, but are not limited to, conductive materials, such as metals or alloys.

The conductive traces146are disposed on the passivation layer128and the conductive vias136. The conductive traces146are is in contact with the conductive vias136. The conductive traces146are may be formed by patterning a conductive layer disposed on the passivation layer128and the conductive vias136. The exemplary materials of the conductive layer146can include, for example but are not limited to, conductive materials. The conductive layer146may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The TGVs162are formed to extend longitudinally from the second conductive layer146and penetrate into the substrate102. The upper surfaces of the TGVs162are free from coverage of the third passivation layer128. In some embodiments, the TGVs162may be formed to extend longitudinally from the first conductive layer142and penetrate into the substrate102. The upper surfaces of the TGVs162are free from coverage of the second passivation layer126. The exemplary materials of the TGVs162can include, for example, but are not limited to, conductive materials, such as metals or alloys.

The protection layer154is disposed above the passivation layer128and the conductive layer146. The protection layer154covers the passivation layer128and the conductive layer146. The protection layer154can prevent the conductive layer146from oxidizing. Some portions of the conductive layer146can be exposed through openings in the protection layer154to form the conductive pads170, which are configured to electrically connect to external elements (e.g., an external circuit).

The conductive pads170may include a control pad CTRL configured to act as the control node, a first power/load pad P/L1configured to act as the first power/load node, a second power/load pad P/L2configured to act as the second power/load node and a reference pad REF configured to act as the reference node.

Conductive traces142or146, conductive vias132or136, and TGVs162can be configured to electrically connect different layers/elements to form the nitride-based bilateral transistor Qm, the first substrate-coupling transistor Q1and the second substrate-coupling transistor Q2.

Different stages of a method for manufacturing the bidirectional switching device11are shown inFIGS.3A-3Kand described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes. The process for forming the passivation layers serving as a planarization layer generally includes a chemical mechanical polish (CMP) process. The process for forming the conductive vias generally includes forming vias in a passivation layer and filling the vias with conductive materials. The process for forming the conductive traces generally includes photolithography, exposure and development, etching, other suitable processes, or combinations thereof.

Referring toFIG.3A, a substrate102is provided. Nitride-based semiconductor layers104and106can be formed over the substrate102in sequence by using the above-mentioned deposition techniques. A 2 DEG region is formed adjacent to a heterojunction interface between the first nitride-based semiconductor layer104and the second nitride-based semiconductor layer106.

Referring toFIG.3B, A blanket p-type doped III-V compound semiconductor layer111and a blanket gate electrode layer113can be formed above the nitride-based semiconductor layer106in sequence by using the above-mentioned deposition techniques.

Referring toFIG.3C, the blanket p-type doped III-V compound semiconductor layer111and the blanket gate electrode layer113are patterned to form a plurality of gate structures110over the nitride-based semiconductor layer106. Each of the gate structures110includes a p-type doped III-V compound semiconductor layer112and a gate metal layer114. A passivation layer124can then be formed to cover the of the gate structures110by using the above-mentioned deposition techniques.

Referring toFIG.3D, some S/D regions160are formed by removing some portions of the passivation layer124. At least one portion of the nitride-based semiconductor layer106is exposed from the S/D regions160. A blanket conductive layer115is formed to cover the nitride-based semiconductor layer106and the passivation layer124, and fill the S/D regions160, thereby contacting with the nitride-based semiconductor layer106.

Referring toFIG.3E, S/D electrodes116are formed by patterning the blanket conductive layer115. Some portions of the blanket conductive layer115are removed, and rest of the blanket conductive layer115within the S/D regions160remains to serve as the S/D electrodes116. A passivation layer126can then be formed on the passivation layer124to cover the S/D electrodes116by using the above-mentioned deposition techniques.

Referring toFIG.3F, conductive vias132are formed to penetrate the passivation layers126and124. A blanket conductive layer141is deposited on the passivation layer126by using the above-mentioned deposition techniques.

Referring toFIG.3G, the blanket conductive layer141is patterned form conductive traces142over the passivation layer126and electrically coupled with the conductive vias132. A passivation layer128can then be formed on the passivation layer126to cover the conductive traces142by using the above-mentioned deposition techniques.

Referring toFIG.3H, conductive vias136are formed in the passivation layer128. A blanket conductive layer145is deposited on the passivation layer128by using the above-mentioned deposition techniques.

Referring toFIG.3I, a plurality of TGV162may also be formed to extending from the passivation layer128and penetrating into the substrate before depositing the blanket conductive layer145.

Referring toFIG.3J, the blanket conductive layer145is patterned to form conductive traces146over the passivation layer128and electrically coupled with the conductive vias136. A protection layer154can then be formed on the passivation layer128to cover the conductive traces146by using the above-mentioned deposition techniques.

Referring toFIG.3K. the protection layer154can then be patterned to form one or more openings to expose one or more conductive pads170.

FIG.4is a circuit block diagram for a bidirectional switching device6with substrate potential management capability according to some embodiments of the present invention.

As shown inFIG.4, the bidirectional switching device6has a control node CTRL, a first power/load node P/L1and a second power/load node P/2and a main substrate.

The bidirectional switching device6comprises a nitride-based bilateral transistor Qm and a substrate potential management circuit configured for managing a potential of the main substrate of the bidirectional switching device6.

The bilateral transistor Qm may have a main gate terminal Gm electrically connected to the control node, a first source/drain terminal S/D1electrically connected to the first power/load node, a second source/drain terminal S/D2electrically connected to the second power/load node; and a main substrate terminal SUB electrically connected to the main substrate.

The substrate potential management circuit may comprise a first potential stabilizing element F1having a control terminal electrically connected to the control node, a first conduction terminal electrically connected to the first power/load node; a second conduction terminal electrically connected to the main substrate and a substrate terminal electrically connected to the main substrate.

The substrate potential management circuit may further comprise a second potential stabilizing element F2having a first conduction terminal connected to the main substrate and a second conduction terminal connected to the control node.

When a high-level voltage is applied to the control node, the first potential stabilizing element F1may have a first resistance lower than a second resistance of the second potential stabilizing element F2such that a potential of the main substrate is substantially equal to a lower one of potentials of the first and second power/load nodes.

When a low-level voltage is applied to the control node, the first resistance may be higher than the second resistance such that the potential of the main substrate is substantially equal to the low-level voltage.

FIG.5depicts a circuit diagram of a bidirectional switching devices61according to some embodiments.

Referring toFIG.5. The first potential stabilizing element F1may comprise a first substrate-coupling transistor Q1having a first gate terminal G1electrically connected to the control node, a first drain terminal D1electrically connected to the first power/load node and a first source terminal S1electrically connected to the main substrate.

The first substrate-coupling transistor Q1may be constructed with various types of transistors, including but not limited to, GaN HEMT, Si MOSFET, insulated gate bipolar transistor (IGBT), junction gate field-effect transistor (JFET) and static induction transistor (SIT).

The second potential stabilizing element F2may be a non-rectifying element, such as a resistor R1, having a first terminal connected to the main substrate and a second terminal connected to the control node.

FIGS.6A and6Bdepict the operation mechanism of the bidirectional switching devices61under a first operation mode in which the first power/load node is biased at a voltage VHhigher than a voltage VLapplied to the second power/load node.

Referring toFIG.6A. When a high-level voltage VONis applied to the control node such that the bilateral transistor Qm and the first substrate-coupling transistor Q1are turned on, a current flows through the resistor R1from the control node to the second power/load node, the potential of the substrate Vsub is then given by Vsub=VL+Vm,on+(VON−VL−Vm,on)*Rs1,on/(Rs1,on+R), where R is the resistance of the resistor R1, Rs1,on is the on-resistance of the first substrate-coupling transistor Q1, Vm,on is a drain-source voltage of the bilateral transistor Qm when it is turned on. As Rs1,on is much smaller than R and Vm,on is very small, Vsub is substantially equal to the voltage VLapplied to the second power/load node.

Referring toFIG.6B. When a low-level voltage VOFFis applied to the control node such that the bilateral transistor Qm and the first substrate-coupling transistor Q1are turned off, a current flows through the resistor R1from the first power/load node to the control node, the potential of the substrate Vsub is given by Vsub=VOFF+(VH−VOFF)*R/(R+Rs1,off), where Rs1,off is the off-resistance of the first substrate-coupling transistor Q1. As Rs1,off is much larger than R, the potential of the substrate Vsub is substantially equal to the low-level voltage VOFFapplied to the control node.

FIGS.6C and6Ddepict the operation mechanism of the bidirectional switching devices61under a second operation mode in which the second power/load node is biased at a voltage VHhigher than a voltage VLapplied to the first power/load node.

Referring toFIG.6C. When a high-level voltage VONis applied to the control node such that the bilateral transistor Qm and the first substrate-coupling transistor Q1are turned ON, a current flows through the resistor R1from the control node to the first power/load node, the potential of the substrate Vsub is given by Vsub=VL+(VON−VL)*Rs1,on/(Rs1,on+R). As Rs1,on is much smaller than R, the potential of the substrate Vsub is substantially equal to the voltage VLapplied to the first power/load node.

Referring toFIG.6D. When a low-level voltage VOFFis applied to the control node such that the bilateral transistor Qm and the first substrate-coupling transistor Q1are turned off, a current flows through the resistor R1from the second power/load node to the control node, the potential of the substrate Vsub is given by Vsub=VOFF+(VH−Vm,off−VOFF)*R/(Rs1,off+R), where Vm,off is a drain-source voltage of the bilateral transistor Qm when it is turned off. As Rs1,off is much larger than R, the potential of the substrate Vsub is substantially equal to the low-level voltage VOFFapplied to the control node.

The bidirectional switching device61ofFIG.5may be formed by integrating the nitride-based bilateral transistor Qm, the first substrate-coupling transistor Q1and the resistor R1in an IC chip.

FIGS.7and8A-8Eillustrate structure of a bidirectional switching device61abased on the circuit diagram ofFIG.5.FIG.7is a partial layout of the bidirectional switching device61ashowing a relationship among some elements that can constitute parts of transistors and the resistor in the bidirectional switching device61a.FIGS.8A-8Eare cross-sectional views taken along lines A-A′. B-B′, C-C′, D-D′ and E-E′ inFIG.7respectively. The bidirectional switching device61ahas a layered structure similar to that of the bidirectional switching device11. For conciseness, identical elements are given the same reference numerals and symbols and will not be described in details.

Referring toFIGS.7and8A-8E, the bidirectional switching device61amay include a substrate102, a first nitride-based semiconductor layer104, a second nitride-based semiconductor layer106, gate structures110, S/D electrodes116, a first passivation layer124, a passivation layer126, a third passivation layer128, one or more first conductive vias132, one or more second conductive vias136, one or more first conductive traces142, one or more second conductive traces146, a protection layer154, one or more through gallium vias (TGV)162and one or more conductive pads170, which are configured to electrically connect to external elements (e.g., an external circuit).

Conductive traces142or146, conductive vias132or136, and TGVs162can be configured to electrically connect different layers/elements to form the nitride-based bilateral transistor Qm, the first substrate-coupling transistor Q1and the resistor R1.

The conductive pads170may include a control pad CTRL configured to act as the control node, a first power/load pad P/L1configured to act as the first power/load node and a second power/load pad P/L2configured to act as the second power/load node.

Referring toFIG.8A. The S/D electrodes116may include at least one first S/D electrode116aelectrically connected to the first power/load pad and configured to act as the first source/drain terminal of the nitride-based bilateral transistor Qm and the drain terminal of the first substrate-coupling transistor Q1. The first S/D electrode116amay be connected to the first power/load pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

Referring toFIG.8B. The S/D electrodes116may include at least one second S/D electrode116belectrically connected to the second power/load pad and configured to act as the second source/drain terminal of the nitride-based bilateral transistor Qm. The second S/D electrode116bmay be connected to the second power/load pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

Referring toFIG.8C. The gate structures110may include at least one first gate structure110aelectrically connected to the control pad and configured to act as the main gate terminal of the nitride-based bilateral transistor Qm. The first gate structure110amay be connected to the control pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

The gate structures110may further include at least one second gate structure110belectrically connected to the control pad and configured to act as the gate terminal of the first substrate-coupling transistor Q1. The second gate structure110bmay be connected to the control pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

Referring toFIG.8D. The S/D electrodes116may include at least one third S/D electrode116celectrically connected to the substrate102and configured to act as the source terminal of the first substrate-coupling transistor Q1. The third S/D electrode116cmay be electrically connected to the substrate through at least one conductive via132, at least one conductive trace142, at least one conductive via136, at least one conductive trace146and at least one TGV162.

Preferably, the second S/D electrode116bis adjacent to the first S/D electrode116aand the first gate structure110ais between the first S/D electrode116aand the second S/D electrode116b.

Preferably, the third S/D electrode116cis adjacent to the first S/D electrode116a; and the second gate structure110bis between the first S/D electrode116aand the third S/D electrode116c.

Referring toFIG.7andFIG.8E. The bidirectional switching device61amay further comprise a resistive element180a. The resistive element180acomprises a first end181aelectrically connected to the substrate102to act as the first terminal of the resistor R1; and a second end182aelectrically connected to the control pad to act as the second terminal of the resistor R1.

The resistive element180amay be disposed at the same layer of the 2 DEG region adjacent to the heterojunction interface between the first nitride-based semiconductor layer104and the second nitride-based semiconductor layer106. The first end181amay be electrically coupled to the substrate102through at least one ohmic contact116e, at least one first conductive via132, at least one first conductive trace142, at least one conductive via136, at least one conductive trace146and at least one TGV162. The second end182amay be electrically connected to the control pad through at least one ohmic contact116e, at least one first conductive via132, at least one first conductive trace142, at least one second conductive via136and at least one second conductive trace146.

The manufacturing method for the bidirectional switching device61amay include stages illustrated inFIGS.3A-3Kexcept for that between the stages illustrated inFIG.3AandFIG.3B, the 2 DEG region adjacent to the heterojunction interface between the first nitride-based semiconductor layer104and the second nitride-based semiconductor layer106is patterned by ion-implantation to form the resistive element180a.

FIG.9andFIG.10illustrate structure of a bidirectional switching device61baccording to another embodiment based on the circuit diagram ofFIG.5.FIG.9is a partial layout of the bidirectional switching device61bshowing a relationship among some elements that can constitute parts of transistors and the resistor in the bidirectional switching device61b. The cross-section views taken along lines A-A′, B-B′, C-C′ and D-D′ inFIG.9are the same as those taken along lines A-A′, B-B′ and C-C′ and D-D′ inFIG.7, thus can be referred toFIGS.8A-8D. The cross-section view taken along line E-E′ inFIG.9is illustrated inFIG.10. For conciseness, identical structural elements inFIGS.7,8A-8E, andFIGS.9,10are given the same reference numerals and symbols and will not be further described in details.

Referring toFIG.9andFIG.10. The bidirectional switching device61bcomprises a resistive element180b. The resistive element180bcomprises a first end181belectrically connected to the substrate102to act as the first terminal of the resistor R1; and a second end182belectrically connected to the control pad to act as the second terminal of the resistor R1.

The bidirectional switching device61bis similar to the bidirectional switching device61aexcept for that the resistive element180bis disposed on the second nitride-based semiconductor layer106and made of the same materials as the gate structures110. The first end181bmay be electrically coupled to the substrate102through at least one first conductive via132, at least one first conductive trace142, at least one conductive via136, at least one conductive trace146and at least one TGV161. The second end182bmay be electrically connected to the control pad through at least one first conductive via132, at least one first conductive trace142, at least one second conductive via136and at least one second conductive trace146.

The manufacturing method for the bidirectional switching device61bmay include stages illustrated inFIGS.3A-3Kexcept for that at the stage illustrated inFIG.3C, the blanket semiconductor layer111and the blanket gate electrode layer113are patterned to form the gate structures110and the resistive element180bsimultaneously.

FIG.11andFIG.12illustrate structure of a bidirectional switching device61caccording to another embodiment based on the circuit diagram ofFIG.15.FIG.11is a partial layout of the bidirectional switching device61cshowing a relationship among some elements that can constitute parts of transistors and the resistor in the bidirectional switching device61c. The cross-section views taken along lines A-A′, B-B′, C-C′ and D-D′ inFIG.11are the same as those taken along lines A-A′, B-B′ and C-C′ and D-D′ inFIG.7, thus can be referred toFIGS.8A-8D. The cross-section view taken along line E-E′ inFIG.11is illustrated inFIG.12. For conciseness, identical structural elements inFIGS.7,8A-8E, andFIGS.11,12are given the same reference numerals and symbols and will not be further described in details.

Referring toFIG.11andFIG.12. The bidirectional switching device61ccomprises a resistive element180c. The resistive element180ccomprises a first end181celectrically connected to the substrate102to act as the first terminal of the resistor R1; and a second end182celectrically connected to the control pad to act as the second terminal of the resistor R1.

The bidirectional switching device61cis similar to the bidirectional switching device61aexcept for that the resistive element180cmay be disposed on the first passivation layer124and made of the same materials as the S/D electrodes116. The first end181cmay be electrically coupled to the substrate102through at least one first conductive via132, at least one first conductive trace142, at least one conductive via136, at least one conductive trace146and at least one TGV162. The second end182cmay be electrically connected to the control pad through at least one first conductive via132, at least one first conductive trace142, at least one second conductive via136and at least one second conductive trace146.

The manufacturing method for the bidirectional switching device61cmay include stages illustrated inFIGS.3A-3Kexcept for that at the stage illustrated inFIG.3E, the blanket conductive layer115is patterned to form the S/D electrodes116and the resistive element180csimultaneously.

FIG.13andFIG.14illustrate structure of a bidirectional switching device61daccording to another embodiment based on the circuit diagram ofFIG.5.FIG.13is a partial layout of the bidirectional switching device61dshowing a relationship among some elements that can constitute parts of transistors and the resistor in the bidirectional switching device61d. The cross-section views taken along lines A-A′, B-B′, C-C′ and D-D′ inFIG.13are the same as those taken along lines A-A′, B-B′ and C-C′ and D-D′ inFIG.7, thus can be referred toFIGS.8A-8D. The cross-section view taken along line E-E′ inFIG.13is illustrated inFIG.14. For conciseness, identical structural elements inFIGS.7,8A-8E, andFIGS.13,14are given the same reference numerals and symbols and will not be further described in details.

Referring toFIG.13andFIG.14. The bidirectional switching device61dcomprises a resistive element180d. The resistive element180dcomprises a first end181delectrically connected to the substrate102to act as the first terminal of the resistor R1; and a second end182delectrically connected to the control pad to act as the second terminal of the resistor R1.

The bidirectional switching device61dis similar to the bidirectional switching device61aexcept for that the resistive element180dis disposed within passivation layer126. The passivation layer126is split into a lower layer126abelow the resistive element180dand an upper layer126babove the resistive element180d. In other words, the resistive element180dis sandwiched between the first layer126aand the lower layer126aand the upper layer126b. The first end181dmay be electrically coupled to the substrate102through at least one third conductive via134, at least one first conductive trace142, at least one conductive via136, at least one conductive trace146and at least one TGV162. The second end182emay be electrically connected to the control pad through at least one third conductive via134, at least one first conductive trace142, at least one second conductive via136and at least one second conductive trace146.

The manufacturing method for the bidirectional switching device61dmay include stages illustrated inFIGS.3A-3Kexcept for that a lower passivation layer126ais deposited on the passivation layer124; a blanket metal/metal compound layer143is deposited on the passivation layer126aand patterned to form the resistive element180d; an upper passivation layer126bis deposited over the lower passivation layer126ato cover the resistive element180d; one or more third conductive vias134are formed in the upper passivation layer126bto electrically couple the resistive element180d.

FIG.15andFIG.16illustrate structure of a bidirectional switching device61eaccording to another embodiment based on the circuit diagram ofFIG.15.FIG.15is a partial layout of the bidirectional switching device61eshowing a relationship among some elements that can constitute parts of transistors and the resistor in the bidirectional switching device61e. The cross-section views taken along lines A-A′, B-B′, C-C′ and D-D′ inFIG.15are the same as those taken along lines A-A′, B-B′ and C-C′ and D-D′ inFIG.7, thus can be referred toFIGS.8A-8D. The cross-section view taken along line E-E′ inFIG.15is illustrated inFIG.16. For conciseness, identical structural elements inFIGS.7,8A-8E, andFIGS.15,16are given the same reference numerals and symbols and will not be further described in details.

Referring toFIG.15andFIG.16. The bidirectional switching device61ecomprises a resistive element180e. The resistive element180ecomprises a first end181eelectrically connected to the substrate102to act as the first terminal of the resistor R1; and a second end182eelectrically connected to the control pad to act as the second terminal of the resistor R1.

The bidirectional switching device61eis similar to the bidirectional switching device61aexcept for that the resistive element180eis disposed on the second passivation layer126and made of the same materials as the conductive traces142. The first end181emay be electrically coupled to the substrate102through at least one second conductive via136, at least one second conductive trace146and at least one TGV162. The second end182emay be electrically connected to the control pad through at least one second conductive via136and at least one second conductive trace146.

The manufacturing method for the bidirectional switching device61emay include stages illustrated inFIGS.3A-3Kexcept for that at the stage illustrated inFIG.3G, the blanket conductive layer141is patterned to form the conductive traces142and the resistive element180esimultaneously.

FIG.17andFIG.18illustrate structure of a bidirectional switching device61faccording to another embodiment based on the circuit diagram ofFIG.5.FIG.17is a partial layout of the bidirectional switching device61fshowing a relationship among some elements that can constitute parts of transistors and the resistor in the bidirectional switching device61f. The cross-section views taken along lines A-A′, B-B′, C-C′ and D-D′ inFIG.17are the same as those taken along lines A-A′, B-B′ and C-C′ and D-D′ inFIG.7, thus can be referred toFIGS.8A-8D. The cross-section view taken along line E-E′ inFIG.17is illustrated inFIG.18. For conciseness, identical structural elements inFIGS.7,8A-8E, andFIGS.17,18are given the same reference numerals and symbols and will not be further described in details.

Referring toFIG.17andFIG.18. The bidirectional switching device61fcomprises a resistive element180e. The resistive element180ecomprises a first end181eelectrically connected to the substrate102to act as the first terminal of the resistor R1; and a second end182eelectrically connected to the control pad to act as the second terminal of the resistor R1.

The bidirectional switching device61fis similar to the bidirectional switching device61aexcept for that the resistive element180fmay be disposed on the third passivation layer128and made of the same materials as the conductive traces146. The first end181fmay be electrically coupled to the substrate102through at least one TGV162. The second end182fmay be electrically connected to the control pad.

The manufacturing method for the bidirectional switching device61fmay include stages illustrated inFIGS.3A-3Kexcept for that at the stage illustrated inFIG.3J, the blanket conductive layer145is patterned to form the conductive traces146and the resistive element180fsimultaneously.

FIG.19Adepicts a circuit diagram of a bidirectional switching devices62according to some embodiments.

Referring toFIG.19A. The first potential stabilizing element F1may comprise a first substrate-coupling transistor Q1having a first gate terminal G1electrically connected to the control node, a first drain terminal D1electrically connected to the first power/load node and a first source terminal S1electrically connected to the main substrate.

The first substrate-coupling transistor Q1may be constructed with various types of transistors, including but not limited to, GaN HEMT, Si MOSFET, insulated gate bipolar transistor (IGBT), junction gate field-effect transistor (JFET) and static induction transistor (SIT).

The second potential stabilizing element F2may be a rectifying element, such as a diode D1, having a positive terminal connected to the main substrate and a negative terminal connected to the control node.

Referring toFIG.19B. The diode D1may be replaced with a rectifying transistor Q3to form a bidirectional switching device63. The rectifying transistor Q3may have a gate terminal G3and a source terminal S3both connected to the main substrate and a drain terminal D3connected to control node.

FIGS.20A and20Bdepict the operation mechanism of the bidirectional switching devices62under the first operation mode in which the first power/load node is biased at a voltage VHhigher than a voltage VLapplied to the second power/load node.

Referring to20A. When a high-level voltage VONis applied to the control node such that the bilateral transistor Qm and the first substrate-coupling transistor Q1are turned on, the diode D1is reverse biased as a current flows through the diode D1from the control node to the second power/load node, the potential of the substrate Vsub is then given by Vsub=VL+Vm,on+(VON−VL−Vm,on)*Rs1,on/(Rs1,on+RRV), where RRVis the reverse resistance of the diode D1, Rs1,on is the on-resistance of the first substrate-coupling transistor Q1, and Vm,on is a drain-source voltage of the bilateral transistor Qm when it is turned on. As Vm,on is very small and RRVis much larger than Rs1,on, the potential of the substrate Vsub is substantially equal to the voltage VLapplied to the second power/load node.

Referring to20B. When a low-level voltage VOFFis applied to the control node such that the bilateral transistor Qm and the first substrate-coupling transistor Q1are turned off, the diode D1is forward biased as a current flows through the diode D1from the first power/load node to the control node, the potential of the substrate Vsub is then given by Vsub=VOFF+(VH−VOFF)*RFW/(RFW+Rs1,off), where RFWis the forward resistance of the diode D1. As RFWis much smaller than Rs1,off, the potential of the substrate Vsub is substantially equal to the low-level voltage VOFFapplied to the control node.

FIGS.20C and20Ddepict the operation mechanism of the bidirectional switching devices62under the second operation mode in which the second power/load node is biased at a voltage VHhigher than a voltage VLapplied to the first power/load node.

Referring toFIG.20C. When a high-level voltage VONis applied to the control node such that the bilateral transistor Qm and the first substrate-coupling transistor Q1are turned on, the diode D1is forward biased as a current flows through the diode D1from the control node to the first power/load node, the potential of the substrate Vsub is then given by VSUB=VL+(VON−VL)*Rs1,on/(Rs1,on+RRV). As Rs1,on is much smaller than RRV, the potential of the substrate Vsub is substantially equal to the voltage VLapplied to the first power/load node.

Referring toFIG.20D. When a low-level voltage VOFFis applied to the control node such that the bilateral transistor Qm and the first substrate-coupling transistor Q1are turned off, the diode D1is reverse biased as a current flows through the diode D1from the second power/load node to the control node, the potential of the substrate Vsub is given by Vsub=VOFF+(VH−Vm,off−VOFF)*RFW/(Rs1,off+RFW), where Vm,off is a drain-source voltage of the bilateral transistor Qm when it is turned off. As Rs1,off is much larger than RFW, the potential of the substrate Vsub is substantially equal to the low-level voltage VOFFapplied to the control node.

FIGS.21and22A-22Dillustrate structure of the bidirectional switching device62/63based on the circuit diagram ofFIG.19A/19B.FIG.21is a partial layout of the bidirectional switching device62/63showing a relationship among some elements that can constitute parts of transistors in the bidirectional switching device62/63.FIGS.22A-22Dare cross-sectional views taken along lines A-A′, B-B′, C-C′ and D-D′ inFIG.21respectively. For conciseness, identical structural elements are given the same reference numerals and symbols and will not be further described in details.

Referring toFIGS.21and22A-22D, the bidirectional switching device62/63may include a substrate102, a first nitride-based semiconductor layer104, a second nitride-based semiconductor layer106, gate structures110, S/D electrodes116, a first passivation layer124, a passivation layer126, a third passivation layer128, one or more first conductive vias132, one or more second conductive vias136, one or more first conductive traces142, one or more second conductive traces146, a protection layer171and one or more through gallium vias (TGV)162and conductive pads170.

The conductive pads170may include a control pad CTRL configured to act as the control node, a first power/load pad P/L1configured to act as the first power/load node and a second power/load pad P/L2configured to act as the second power/load node.

Conductive traces142or146, conductive vias132or136, and TGVs162can be configured to electrically connect different layers/elements to form the nitride-based bilateral transistor Qm, the first substrate-coupling transistor Q1and the diode D1/rectifying transistor Q3.

Referring toFIG.22A. The S/D electrodes116may include at least one first S/D electrode116aelectrically connected to the first power/load pad and configured to act as the first source/drain terminal of the nitride-based bilateral transistor Qm and the drain terminal of the first substrate-coupling transistor Q1. The first S/D electrode116amay be connected to the first power/load pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

In this exemplary structure, the same S/D electrode is shared by the nitride-based bilateral transistor Qm and the first substrate-coupling transistor Q1such that the chip size can be minimized. In some embodiments, different S/D electrodes can be used to act as the first source/drain terminal of the nitride-based bilateral transistor Qm and the drain terminal of the first substrate-coupling transistor Q1.

Referring toFIG.22B. The S/D electrodes116may include at least one second S/D electrode116belectrically connected to the second power/load pad and configured to act as the second source/drain terminal of the nitride-based bilateral transistor Qm. The second S/D electrode116bmay be connected to the second power/load pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

Referring toFIG.22C. The gate structures110may include at least one first gate structure110aelectrically connected to the control pad and configured to act as the main gate terminal of the nitride-based bilateral transistor Qm. The first gate structure110amay be connected to the control pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

The gate structures110may further include at least one second gate structure110belectrically connected to the control pad and configured to act as the gate terminal of the first substrate-coupling transistor Q1. The second gate structure110bmay be connected to the control pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

The S/D electrodes116may further include at least one fourth S/D electrode116delectrically connected to the control pad and configured to act as the drain terminal of the rectifying transistor Q3(or the negative terminal of the diode D1). The third S/D electrode116cmay be connected to the control pad through at least one conductive via132, at least one conductive trace142, at least one conductive via136and at least one conductive trace146.

Referring toFIG.22D. The S/D electrodes116may include at least one third S/D electrode116celectrically connected to the substrate102and configured to act as the source terminal of the first substrate-coupling transistor Q1and the source terminal of the rectifying transistor Q3. The third S/D electrode116cmay be electrically connected to the substrate through at least one conductive via132, at least one conductive trace142, at least one conductive via136, at least one conductive trace146and at least one TGV162.

The gate structures110may further include at least one third gate structure110celectrically connected to the substrate and configured to act as the gate terminal of the rectifying transistor Q3. The third gate structure110cmay be connected to the substrate through at least one conductive via132, at least one conductive trace142, at least one conductive trace146and at least one TGV162.

In other words, the third S/D electrode116cand the third gate structure110cmay be electrically shorted to form the positive terminal of diode D1.

Preferably, the second S/D electrode116bis adjacent to the first S/D electrode116aand the first gate structure110ais between the first S/D electrode116aand the second S/D electrode116b.

Preferably, the third S/D electrode116cis adjacent to the first S/D electrode116a; and the second gate structure110bis between the first S/D electrode116aand the third S/D electrode116c.

Preferably, the third S/D electrode116cis adjacent to the fourth S/D electrode116d; and the third gate structure110cis between the fourth S/D electrode116dand the third S/D electrode116c.

The manufacturing method for the bidirectional switching device62/63may include stages illustrated inFIGS.3A-3K.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms “substantially,” “substantial,” “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the figures and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto.

While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.