Patent ID: 12199586

DETAILED DESCRIPTION

FIG.1shows a system100having a capacitively isolated communication channel102between a first circuit104, and a second circuit106. In the illustrated embodiment, the first and second circuits104,106have different voltage domains on different die which require the isolated communication channel102to exchange data. In the illustrated embodiment, the communication channel102includes a first capacitor112(C1) coupled between a driver114on the first circuit104and a receiver116on the second circuit106. In an example embodiment, the receiver116includes a resistor118(R) coupled to ground GNDS for the second circuit.

The driver114outputs a voltage waveform120, such as a digital pulse, to the first capacitor112(C1), which provides the isolation barrier between the first and second systems104,106. A current waveform122is produced in response to the voltage waveform120. The current122flows into the resistor118on the second circuit106and creates a voltage waveform124.

FIG.2shows the system ofFIG.1except the driver114is no longer actively sending data121, and the primary ground GNDP on the second circuit106is now being pulsed123causing common mode movement. The resistor118is coupled to local or secondary ground GNDS on the second circuit106. This pulsing may be normal for a high side driver circuit in noisy environments and the pulses can result in voltages changing at rates in the order of 200V/nS. As a result of the pulse123to the ground GNDP, the first capacitor112experiences a current waveform125similar to the data pulse inFIG.1. This current from the pulse123flows into the resistor118and creates a voltage waveform127similar to voltage waveform124inFIG.1corresponding to the data pulse on the communication channel. The pulse123creates common mode movement in the form of the current signal125due to rate of change of the potential difference between the driver114, which is coupled to ground GNDP, and the secondary ground GNDS of the receiver116on the second circuit106.

In example applications, the second system106may comprise a motor controller for driving motor phases with signals that may be in the order of 600V, for example, with a frequency in the hundreds of kHz. The first and second systems can form part of a motor controller IC package for controlling three-phase motors. The second system106may be subject to common mode movements of 600V over 2 ns. Currents generated as capacitors charge/discharge may be computed as capacitance C times the rate of change in voltage V, i.e., i=C(ΔV/Δt). Data signals over a communication channel between systems may comprise digital signals with pulses in the order of 0 to 3V. It is desirable to make the digital communication channel impervious to common mode movement on the second system, for example. It is understood that the first and second systems can comprise a wide range of devices, such as motor drivers, rectifiers, half and full bridge circuits, inverters, DC-DC converters, and the like.

Thus, it can be seen that the signal (124or127) across the resistor118may be the result of a data pulse120(FIG.1) from the driver114or pulsing123associated with common mode movement experienced by the high side circuit106. Thus, it is desirable to extract the data signal provided by the driver in the presence of the noise induced by the common mode movement.

FIG.3shows an example system300that has some commonality with the systems ofFIGS.1and2with the addition of a second capacitor313(C2) coupled between the first circuit304and a suppression module301on the second circuit306. A driver314on the first circuit304is connected to a receiver316on the second circuit306via a communication channel302. The receiver316includes a resistor318connected to a secondary ground GNDS of the second circuit306. The second circuit306may be susceptible to pulses323on primary ground GNDP.

In the illustrated embodiment, the suppression module301has an input320coupled to primary ground GNDP on the first circuit304via the second capacitor313and an output322coupled to a node between the first capacitor312(C1) and the resistor318. The suppression module301is referenced to the potential of GNDS.

In the illustrated embodiment, the first capacitor312has no data stimulus as the driver314is not transmitting pulses. Current flow325across the first capacitor312is caused by common mode movement in the second (high side) circuit306due to common mode pulse(s)323. The suppression circuit301measures the current flow327which arrives on the input port320and returns the same level of current on the output port322. If the first and second capacitors C1, C2have equal capacitance, the current flow through the first and second capacitors312,313will be the same. If the suppression circuit301sends back the same current on the output port322that was taken from the input port320then current from the output port will exactly supply the common mode movement current in the first capacitor312. That is, the net current change into the resistor is zero and thus the suppression circuit301effectively cancels the current generated by the common mode voltage change. Because none of the common mode movement current induced in the first capacitor312passes through the resistor318the voltage across the resistor318is not impacted by the common mode voltage movement. The current created in the first capacitor312as a result of the data driver314is not affected by the suppression circuit301and thus the resulting data signal is not affected.

FIG.4shows an example embodiment of a suppression circuit400, such as the suppression circuit301ofFIG.3, having a current mirror formed with first and second PMOS transistors402a,b. The first transistor402acorresponds to an input port404of the suppression circuit and second transistor402bcorresponds to an output port406so that current being pulled from the input is supplied back out through the output. As will be readily appreciated, and described above, a signal on the input404is mirrored on the output406of the current mirror. With this arrangement, the current mirror400supplies the first capacitor312(FIG.3) with the common mode movement current induced in the second capacitor313and thus, zero voltage across the resistor318as a result of common mode voltage movement in the first circuit306. The illustrated suppression circuit400can provide a very fast response, e.g., in the order of tens or hundreds of picoseconds.

It is understood that any configuration of suitable technology devices, such as diodes and/or transistors, can be used to from a current mirror. In addition, a variety of circuits can be used to detect an input current and generate a proportional output current for common mode movement suppression.

FIG.5shows an example embodiment of common mode signal suppression in a differential configuration with MOSFET current mirrors in place to negate the impact of the common mode current noise. The data signal is sent across the communication channel using drivers D+ and D− with the input to these drivers being the Boolean NOT of each other. This results in an enhanced differential signal across the differential resistors RL and RR, across which a differential voltage VL-VR appears.

The differential system500includes a communication channel502connecting first and second systems504,506with common mode noise suppression. A differential driver507on the first system504includes a positive driver507aand a negative driver507beach referenced to ground GND and coupled to a receiver508of the second system506via respective driver coupling capacitors510a,b. In the illustrated embodiment, the receiver508comprises a resistor divider network that includes resistors RL and RR and is coupled to the drivers507a,bto generate differential voltages VL, VR.

A first suppression module512is coupled between ground and the first driver507aoutput and a second suppression module514is coupled between ground and the second driver507boutput via respective coupling capacitors516,518. In the illustrated embodiment, the first and second suppression modules512,514comprises MOSFET transistor-based current mirrors.

In the illustrated embodiment, voltage on the high side circuit506is ramping positively, which creates displacement currents ID in the coupling capacitors510a,b,516,518. If the capacitors are the same size, a similar displacement current ID flows in each of the coupling capacitors. Because of the direction of this current, in the first current mirror512the P-channel device520develops an overdrive to supply this current. Devices521and522then mirror device520to supply current ID to nodes VL and VR. Because of this mirroring, the current ID demanded by the driver capacitors510a,bis supplied by the mirror and does not need to be sourced from supply voltage VC through resistors RL and RR and thus, the displacement current does not create a common mode voltage movement in the nodes VL and VR. With fast movement of the high side voltage, the resulting common mode movement of nodes VL and VR (without cancelation scheme) can compromise the function of a follow on differential amplifier.

If a negative voltage ramp is experienced by the high side circuit506the displacement current ID flows in the opposite direction. In this case the N-channel device531accepts the displacement current ID from capacitor518and mirrors it to devices532and533. These devices now accept the displacement current ID from the driver capacitors510a,band again these currents do not flow through resistors RL and RR, so as to suppress common mode movement.

FIG.6shows the embodiment500ofFIG.5with the addition of a MOSFET523in the first current mirror512and a MOSFET534in the second mirror514. The additional MOSFET523is to supply current demanded by coupling capacitor518during a positive ramp of the second system506, which can comprise the circuit. This allows the drain node of device531to maintain its voltage during common mode events. If this device523is not included, it can delay the response of the N-channel mirrors when needed for the negative ramp. It can take nanoseconds to change from a below ground starting point. Similarly, the N-channel device534supplies current to the drain of device520keeping it within the voltage supply rails and speeds up response when needed.

FIG.7shows the embodiment ofFIG.6with the addition of another data channel503. In addition to drivers511a,band resistor network509, current mirror pairs524,525and535,536are also added.

It should be noted that in the example configuration the structure of the matching of devices521,522,532,533,524,525and535,536is a factor for proper operation. During fabrication, for example, device matching can be achieved by pumping DC current through the diode connected devices520and531and then trimming the matched pairs until they are equal. Trimming may also be achieved by diverting the current from the pairs to off-chip matched resistors and trimming until the voltages match.

FIG.8shows an example system with bidirectional communication channels800,802having common mode noise suppression.

In embodiments, coupling capacitors can be matched to each other within some defined amount so that displacement currents are equal in the systems. In other embodiments, devices, such as devices520,522can be trimmed to compensate for mismatched coupling capacitors.

Example isolator embodiments having common mode noise suppression with current mirrors, for example, may provide a 20× reduction in common mode movement produced by the common mode current that occurs due to a low side to high side common mode voltage movement over conventional configurations. This allows the communications channels to work in the presence of large low-to high side common mode voltage transients.

Example signal isolator configurations and applications are shown and described in U.S. Pat. Nos. 9,998,301, and 10,074,939 and 10,074,713 and 10,236,932 and 11,115,244 and 11,342,288, all of which are incorporated herein by reference.

Processing described above may be implemented in hardware, software, or a combination of the two. Processing may be implemented in computer programs executed on programmable computers/machines that each includes a processor, a storage medium or other article of manufacture that is readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and one or more output devices. Program code may be applied to data entered using an input device to perform processing and to generate output information.

The system can perform processing, at least in part, via a computer program product, (e.g., in a machine-readable storage device), for execution by, or to control the operation of, data processing apparatus (e.g., a programmable processor, a computer, or multiple computers). Each such program may be implemented in a high-level procedural or object-oriented programming language to communicate with a computer system. However, the programs may be implemented in assembly or machine language. The language may be a compiled or an interpreted language and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program may be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network. A computer program may be stored on a storage medium or device (e.g., CD-ROM, hard disk, or magnetic diskette) that is readable by a general or special purpose programmable computer for configuring and operating the computer when the storage medium or device is read by the computer. Processing may also be implemented as a machine-readable storage medium, configured with a computer program, where upon execution, instructions in the computer program cause the computer to operate.

Processing may be performed by one or more programmable processors executing one or more computer programs to perform the functions of the system. All or part of the system may be implemented as, special purpose logic circuitry (e.g., an FPGA (field programmable gate array) and/or an ASIC (application-specific integrated circuit)).

Having described exemplary embodiments of the invention, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may also be used. The embodiments contained herein should not be limited to disclosed embodiments but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.

Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable sub combination. Other embodiments not specifically described herein are also within the scope of the following claims.