Patent ID: 12237820

DETAILED DESCRIPTION OF SOME EMBODIMENTS

The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

Disclosed herein are various examples of circuits, devices and methods related to attenuators that can be utilized in, for example, radio-frequency (RF) applications. Although various examples are described herein in the context of RF applications, it will be understood that such circuits, devices and methods related to attenuators can be utilized in other electronic applications.

FIG.1depicts an attenuator circuit100configured to receive an RF signal at an input node (IN) and generate an attenuated RF signal at an output node (OUT). Such an attenuator circuit can include one or more features as described herein so as to provide desirable functionalities such as phase shift compensation, gain compensation, and low loss bypass capability. As described herein, such phase compensation can provide, for example, an approximately zero phase shift resulting from an attenuation block and/or the attenuator circuit itself. As also described herein, such gain compensation can provide, for example, an approximately flat gain over a frequency range.

It is noted that phase variation and gain slope are generally not desired when an input signal passes through an attenuator, since such effects can cause performance degradation in a communication link. In some embodiments, the attenuation circuit100ofFIG.1can include a global compensation scheme and/or a local compensation scheme to address the phase variation problem. As described herein, such compensation schemes can be configured to address sources of such phase variations. As also described herein, such compensation schemes can also provide an approximately flat gain over a relatively wide frequency range. As also described herein, such compensation schemes can also provide a bypass path having relatively low loss which is desirable for keeping signal attenuation to a minimum under some situations (e.g., when an attenuation path is not being used).

For the purpose of description, an attenuation circuit can also be referred to as an attenuator assembly or simply an attenuator. Description of such an attenuation circuit, attenuator assembly, attenuator, etc. can apply to one or more attenuation blocks (also referred to herein as local attenuation), overall attenuation circuit (also referred to herein as global attenuation), or any combination thereof.

FIG.2shows a block diagram of an attenuation circuit100configured to receive an RF signal at its input node (IN) and provide an output RF signal at its output node (OUT). Such an output RF signal can be attenuated by one or more attenuation values, or be substantially the same as the input RF signal (e.g., through bypass functionality) when attenuation is not desired. Examples of how such attenuation values and bypass functionality can be implemented are described herein in greater detail. Also described herein are examples of how phase compensation can be implemented at a local attenuation level, at a global level, or any combination thereof.

In the example ofFIG.2, the input (IN) and output (OUT) nodes of the attenuation circuit100can be coupled through one or more attenuation blocks102a,102b,102c, or through a bypass path106. To achieve the former, each of two switches S1, S2can be closed, and the bypass path106can be configured appropriately. To achieve the latter, each of the switches S1, S2can be opened, and the bypass path106can be configured appropriately. Examples of such attenuation blocks and bypass path are described herein in greater detail.

In the example ofFIG.2, as well as in other figures, an attenuation path is depicted as having three example attenuation blocks A, B and C. However, it will be understood that one or more features of the present disclosure can also be implemented in attenuation circuits having more or less numbers of attenuation blocks. It will also be understood that attenuation circuits having one or more features as described herein can operate in reverse.

Referring toFIG.2, the first example attenuation block102ais shown to provide A dB attenuation. Similarly, the second and third attenuation blocks102b,102care shown to provide B dB and C dB attenuations, respectively. Thus, a number of total attenuation values (e.g., A dB, B dB, C dB, A+B dB, A+C dB, B+C dB, A+B+C dB) can be achieved utilizing such attenuation blocks.

In the example ofFIG.2, each of the attenuation blocks102a,102b,102cis shown to include a respective local phase compensation circuit (104a,104bor104c). Examples related to such local phase compensation circuits are described herein in greater detail. In the example ofFIG.2, all of the attenuation blocks are shown to have respective local phase compensation circuits. However, it will be understood that in some embodiments, one or more attenuation blocks may or may not have such local phase compensation circuit(s).

In the example ofFIG.2, the attenuation circuit100is also shown to include a global phase compensation circuit108. Such a global phase compensation circuit can be implemented between nodes that are before (110) and after (112) the attenuation blocks (102a,102b,102c). Examples related to such a global phase compensation circuit are described herein in greater detail.

In some embodiments, attenuation blocks (e.g.,102a,102b,102cofFIG.2) having one or more features as described herein can be implemented in a binary-weighted configuration. Examples related to such a binary-weighted configuration are described in U.S. patent application Ser. No. 15/687,476, entitled BINARY-WEIGHTED ATTENUATOR HAVING COMPENSATION CIRCUIT, the disclosure of which is filed on even date herewith and hereby incorporated by reference herein in its entirety and to be considered part of the specification of the present application.

FIG.3shows an attenuation circuit100that can be a more specific example of the attenuation circuit100ofFIG.2. In the example ofFIG.3, switches S1and S2can be implemented as, for example, field-effect transistors (FETs). Accordingly, S1can be implemented between the input node (IN) and a first node110, and S2can be implemented between the output node (OUT) and a second node112.

In the example ofFIG.3, each of three attenuation blocks102a,102b,102cis shown to include a pi-attenuator configuration and a local bypass path (105a,105bor105c). For example, the first attenuation block102ais shown to include resistances R1A, R2A, R3Aarranged in a pi-configuration. The resistance R1Ais shown to be implemented between input and output nodes of the first attenuation block102a. The resistance R2Ais shown to be implemented between the input node and ground; similarly, the resistance R3Ais shown to be implemented between the output node and ground.

In the pi-configuration of the first attenuation block102aofFIG.3, a switching FET M2Acan be provided between the input node and one end of the resistance R2A, with the other end of the resistance R2Abeing coupled to ground. Similarly, a switching FET M3Acan be provided between the output node and one end of the resistance R3A, with the other end of the resistance R3Abeing coupled to ground. Such switching FETs (M2Aand M3A) can be turned ON when attenuation is enabled for the first attenuation block102a, and be turned OFF when attenuation is bypassed through the local bypass path105a. Such a local bypass path (105a) can include, for example, a switching FET M1Awhich can be turned OFF when attenuation is enabled for the first attenuation block102a, and be turned ON when attenuation is bypassed through the local bypass path105a.

In the pi-configuration of the first attenuation block102aofFIG.3, a capacitance C2Acan be provided so as to be electrically parallel with the resistance R2A. Similarly, a capacitance C3Acan be provided so as to be electrically parallel with the resistance R3A. As described herein, such capacitances can be selected to compensate for phase-shifting that occurs when an RF signal is passed through the attenuation block. As also described herein, such capacitances can also allow the attenuation block to provide a desirably flat gain profile over a relatively wide frequency range.

In the example ofFIG.3, the second attenuation block102bis shown to include resistances R1B, R2B, R3Barranged in a pi-configuration. The resistance R1Bis shown to be implemented between input and output nodes of the second attenuation block102b. The resistance R2Bis shown to be implemented between the input node and ground; similarly, the resistance R3Bis shown to be implemented between the output node and ground.

In the pi-configuration of the second attenuation block102bofFIG.3, a switching FET M2Bcan be provided between the input node and one end of the resistance R2B, with the other end of the resistance R2Bbeing coupled to ground. Similarly, a switching FET M3Bcan be provided between the output node and one end of the resistance R3B, with the other end of the resistance R3Bbeing coupled to ground. Such switching FETs (M2Band M3B) can be turned ON when attenuation is enabled for the second attenuation block102b, and be turned OFF when attenuation is bypassed through the local bypass path105b. Such a local bypass path (105b) can include, for example, a switching FET M1Bwhich can be turned OFF when attenuation is enabled for the second attenuation block102b, and be turned ON when attenuation is bypassed through the local bypass path105b.

In the pi-configuration of the second attenuation block102bofFIG.3, a capacitance C2Bcan be provided so as to be electrically parallel with the resistance R2B. Similarly, a capacitance C3Bcan be provided so as to be electrically parallel with the resistance R3B. As described herein, such capacitances can be selected to compensate for phase-shifting that occurs when an RF signal is passed through the attenuation block. As also described herein, such capacitances can also allow the attenuation block to provide a desirably flat gain profile over a relatively wide frequency range.

In the example ofFIG.3, the third attenuation block102cis shown to include resistances R1C, R2C, R3Carranged in a pi-configuration. The resistance R1Cis shown to be implemented between input and output nodes of the third attenuation block102c. The resistance R2Cis shown to be implemented between the input node and ground; similarly, the resistance R3Cis shown to be implemented between the output node and ground.

In the pi-configuration of the third attenuation block102cofFIG.3, a switching FET M2Ccan be provided between the input node and one end of the resistance R2C, with the other end of the resistance R2Cbeing coupled to ground. Similarly, a switching FET M3Ccan be provided between the output node and one end of the resistance R3C, with the other end of the resistance R3Cbeing coupled to ground. Such switching FETs (M2Cand M3C) can be turned ON when attenuation is enabled for the third attenuation block102c, and be turned OFF when attenuation is bypassed through the local bypass path105c. Such a local bypass path (105c) can include, for example, a switching FET M1Cwhich can be turned OFF when attenuation is enabled for the third attenuation block102c, and be turned ON when attenuation is bypassed through the local bypass path105c.

In the pi-configuration of the third attenuation block102cofFIG.3, a capacitance C2Ccan be provided so as to be electrically parallel with the resistance R2C. Similarly, a capacitance C3Ccan be provided so as to be electrically parallel with the resistance R3C. As described herein, such capacitances can be selected to compensate for phase-shifting that occurs when an RF signal is passed through the attenuation block. As also described herein, such capacitances can also allow the attenuation block to provide a desirably flat gain profile over a relatively wide frequency range.

In each of the attenuation blocks102a,102b,102c, the presence of the capacitances C2and C3in parallel with their respective resistances R2and R3allows phase compensation as described herein. As also described herein, such phase compensation can also depend on values of the resistances R2and R3, as well as on-resistance values (Ron) of the switching transistors M2and M3. Accordingly, it will be understood that a box indicated as104a,104bor104cincludes some or all of circuit elements of a respective local phase compensation circuit, or includes some or all of circuit elements that can influence such local phase compensation.

In the example ofFIG.3, a bypass path106can be provided between the input node (IN) and the output node (OUT) so as to allow an RF signal to bypass the foregoing attenuation blocks (102a,102b,102c). Preferably, such a bypass path also bypasses the switches S1and S2to not incur any losses that may be associated with such switches.

In some embodiments, the bypass path106can include a switching FET SBypassimplemented to be turned ON when bypassing of the attenuation blocks (102a,102b,102c) is desired. In such a state, each of the switches S1and S2can be turned OFF. The switching FET SBypasscan be turned OFF when attenuation through one or more of the attenuation blocks is desired. In such a state, each of the switches S1and S2can be turned ON.

In the example ofFIG.3, a global phase compensation circuit108can be provided to compensate for a phase shift that can result from the foregoing bypass circuit106. For example, when the switching FET SBypassis in the OFF state (in the attenuation mode), an off-capacitance value Coff is present; and such Coff can cause a phase shift in the RF signal being attenuated.

In some embodiments, the global phase compensation circuit108can include first and second resistances RG1and RG2implemented between the first and second nodes110,112. Further, a capacitance CGcan be provided between ground and a node between RG1and RG2. Examples of how such resistance values and capacitance value can be selected to provide desirable phase compensation are described herein in greater detail.

In the example ofFIG.3, some or all of the various switching FETs can be implemented as, for example, silicon-on-insulator (SOI) devices. It will be understood that while such various switching FETs are depicted as being NFETs, one or more features of the present disclosure can also be implemented utilizing other types of FETs. It will also be understood that the various switches in the example ofFIG.3can also be implemented as other types of transistors, including non-FET transistors.

FIGS.4and5show an example of how phase compensation can be implemented for a given local attenuation block102.FIGS.6and7show an example of how global phase compensation can be implemented.

FIG.4shows an individual local attenuation block102, and such an attenuation block can represent each of the three example attenuation blocks102a,102b,102cofFIG.3. Accordingly, reference numerals of the various elements of the attenuation block102are shown without subscripts.

In the example ofFIG.4, the local attenuation block102is in its attenuation mode, such that an RF signal received at the local input node (IN) is attenuated and provided at the local output node (OUT). Accordingly, the local bypass switching FET M1of the local bypass path105is OFF, and each of the switching FETs M2and M3of the circuit104is ON.

FIG.5shows a circuit representation120of the example attenuation block102ofFIG.4, in which the various switching FETs are represented as either off-capacitance(s) or on-resistance(s). For example, the OFF state of M1is represented as an off-capacitance Coff, and the ON state of each of M2and M3is represented as an on-resistance Ron. For the purpose of description, it is assumed that the pi-attenuator configuration ofFIG.4is generally symmetric. Accordingly, M2can be similar to M3, such that Ron of M2is approximately the same as Ron of M3; hence,FIG.5depicts each of M2and M3as Ron. Similarly, the resistances R2and R3inFIG.4are assumed to be approximately the same; hence,FIG.5depicts each of R2and R3as having a resistance R2. Similarly, the capacitances C2and C3inFIG.4are assumed to be approximately the same; hence,FIG.5depicts each of C2and C3as having a compensation capacitance of Cc.

InFIG.5, the circuit representation120is shown to have a source impedance Rs at the local input (IN), and a load impedance RL at the local output (OUT). Such impedance values may or may not be the same. For the purpose of description, however, values of Rs and RL are assumed to be the same at a characteristic impedance Z0 (e.g., at 50Ω).

With the foregoing assumption, values of R1and R2in the example ofFIG.5can be obtained as follows:

R1=z02·K-1K+1(1)R2=Z0·K+1K-1.(2)
In Equations 1 and 2, the parameter K represents the attenuation value of the attenuation block120. It is noted that as attenuation becomes larger, R1generally increases, and R2generally decreases.

Referring toFIG.5, and assuming that the on-resistance Ron of each of M2and M3is approximately zero, a portion of the attenuation block120, indicated as Network 1, can contribute to forward gain and phase shift (e.g., phase lead) of the attenuation block120as:

VoutVin=RL⁡(1+sR1⁢Coff)(RL+R1)+sRL⁢R1⁢Coff(3)ϕ=tan-1⁡(ω⁢⁢R1⁢Coff)-tan-1⁡(ω⁡(R1⁢RLR1+RL)⁢Coff).(4)

InFIG.5, a portion of the attenuation block120, indicated as Network 2, can contribute to forward gain and phase shift (e.g., phase lag) of the attenuation block120as:

VoutVin=R2′(R2′+R1)+sR2′⁢R1⁢Cc(5)ϕ=-tan-1⁡(ω⁢⁢R1⁢R2′⁢CcR1+R2′).(6)
In Equations 3-6, ω=2πf, where f is frequency, and R2′ is a resistance value of parallel arrangement of R2and RL.

Referring toFIGS.4and5, and Equations 4 and 6, it is noted that the parameters ω, RL, Coff, R1and R2are typically set for a given frequency, characteristic impedance, switching FET configuration, and attenuation value. However, in some embodiments, the value of the compensation capacitance Cc can be adjusted such that the phase lag of Equation 6 compensates for the phase lead of Equation 4. Such phase compensation can allow the phase associated with the attenuation block102/120ofFIGS.4and5to be at or near a desired value. For example, the compensated phase associated with the attenuation block102/120can have substantially the same phase variation as in a reference mode.

Referring toFIGS.4and5, it is noted that since Coff is in parallel arrangement with R1, its impedance 1/(jωCoff) will make an equivalent series impedance between the input and output nodes become smaller as frequency increases, resulting in less attenuation at a higher frequency. Inversely, higher attenuation can result at a lower frequency.

It is further noted that the compensation capacitance Cc is arranged parallel to the corresponding shunt resistance R2. Thus, the impedance (1/(jωCC)) of the compensation capacitance Cc will make an equivalent impedance of the shunt arm become less, resulting in more attenuation for the attenuation block. Thus, in some embodiments, the compensation capacitance Cc can be selected to compensate for the impact of Coff on gain, and thereby achieve a desired gain profile (e.g., approximately flat profile) for the attenuation block over a wide frequency range. In some embodiments, the compensation capacitance Cc can be selected to provide at least some phase compensation described herein, as well as to provide at least some gain compensation as described herein, for the attenuation block.

FIG.6shows an attenuation circuit similar to the example ofFIG.3, but with the local attenuation blocks collectively indicated as102for simplicity. The bypass path106and the global phase compensation circuit108are substantially the same as in the example ofFIG.3.

In the example ofFIG.6, the attenuation circuit can be in its attenuation mode, such that an RF signal received at the global input node (IN) is attenuated and provided at the global output node (OUT). In such an attenuation mode, the global bypass switching FET SBypassof the bypass path106can be OFF to provide a global off-capacitance of Coff.

FIG.7shows a circuit representation130of the global bypass path106and the global phase compensation circuit108ofFIG.6. For the purpose of description, it is assumed that the resistances RG1and RG2of the global phase compensation circuit108are substantially the same.

InFIG.7, the circuit representation130is shown to have a source impedance Rs at the global input (IN), and a load impedance RL at the global output (OUT). Such impedance values may or may not be the same. For the purpose of description, however, values of Rs and RL are assumed to be the same at a characteristic impedance Z0 (e.g., at 50Ω). Further, the resistance RG1(and thus RG2in the foregoing assumption) is also assumed to have a value of 50Ω.

With the foregoing assumptions, a portion of the circuit130, indicated as Network 1, can contribute to forward gain and phase shift (e.g., phase lead) of the circuit130as:

VoutVin=1+2⁢⁢sRG⁢⁢1⁢Coff3+2⁢⁢sRG⁢⁢1⁢Coff(7)ϕ=tan-1⁡(2⁢ω⁢⁢RG⁢⁢1⁢Coff)-tan-1⁡(23⁢ω⁢⁢RG⁢⁢1⁢Coff).(8)

InFIG.7, a portion of the circuit130, indicated as Network 2, can contribute to forward gain and phase shift (e.g., phase lag) of the circuit130as:

VoutVin=13+2⁢⁢sRG⁢⁢1⁢CG(9)ϕ=tan-1⁡(23⁢ω⁢⁢RG⁢⁢1⁢CG).(10)

Referring toFIGS.6and7, and Equations 8 and 10, it is noted that the parameters ω, RLand Coffare typically set for a given frequency, characteristic impedance, and global bypass switch FET (SBypass) configuration. However, in some embodiments, either or both of the values of the global compensation resistance RG1and compensation capacitance CGcan be adjusted such that the phase lag of Equation 10 compensates for the phase lead of Equation 8. Such phase compensation can allow the phase associated with the circuit130ofFIGS.6and7to be at or near a desired value.

Referring toFIGS.6and7, it is noted that since Coff is in parallel arrangement with 2RG1, its impedance 1/(jωCoff) will make an equivalent series impedance between the input and output nodes become smaller as frequency increases, resulting in less attenuation at a higher frequency. Inversely, higher attenuation can result at a lower frequency.

It is further noted that the global compensation capacitance CGis by itself as a shunt capacitance. Thus, the impedance (1/(jωCG)) of the global compensation capacitance CGwill make an equivalent impedance of the shunt arm become less, resulting in more attenuation for the global attenuation circuit. Thus, in some embodiments, the global compensation capacitance CGcan be selected to compensate for the impact of Coff on gain, and thereby achieve a desired gain profile (e.g., approximately flat profile) for the global attenuation circuit over a wide frequency range. In some embodiments, the global compensation capacitance CGcan be selected to provide at least some phase compensation described herein, as well as to provide at least some gain compensation as described herein, for the global attenuation circuit.

In some embodiments, a phase compensation circuit having one or more features as described herein can be configured to account for process variations. By way of an example,FIG.8shows a circuit representation120that is similar to the circuit representation120ofFIG.5(which corresponds to the example attenuation block102ofFIG.4). As described herein, the off-capacitance (Coff) of the bypass capacitance results in a phase change that can be compensated by the compensation capacitances Cc. The off-capacitance (Coff) in the example ofFIG.8results from the OFF state of a bypass switch transistor which can suffer from process variation (e.g., among a number of such devices fabricated together on a wafer). Thus, one or more electrical properties, including Coff, of the bypass switch transistor can vary due to such process variation. Accordingly, the phase change due to such Coff (e.g., as in Equations 4 or 8) can also vary.

FIG.8shows that such process variation and related effects in Coff can be accounted for in the phase compensation circuit. For example, the compensation capacitances Cc in the shunt arms can be configured to be affected by process variation similar to that of the bypass switch transistor (Coff). In some embodiments, such compensation capacitances Cc can be configured as a transistor or transistor-like device, such that any process variation affecting the bypass switch transistor (Coff) also affects the compensation capacitances Cc. For example, if the bypass switch transistor having a Coff property is implemented as a MOSFET device, each of the compensation capacitances Cc can be implemented as a MOSFET or MOSFET-like device. Accordingly, any process-related variation in the bypass switch MOSFET also affects the MOSFET devices of the compensation capacitances Cc, thereby substantially removing or reducing the dependence of the compensation capacitances Cc on process variation (e.g., on the process variation manifested in the bypass switch MOSFET).

InFIG.8, the foregoing common process variation among the bypass switch MOSFET (Coff) and the MOSFET devices is collectively depicted as124. Such common process variation among various resistances can also be implemented. For example, resistances R1, R2(collectively depicted as122) can be implemented as same type of resistors subject to same process variations.

In the example ofFIG.8, the circuit representation120and related process variations are described in the context of an individual attenuation block and its bypass path. It will be understood that such phase compensation generally independent of process variation can also be implemented in the global bypass path and the corresponding global phase compensation circuit.

FIG.9shows an example of how process variation can impact phase changes in an attenuator circuit, and how such phase changes can be compensated. InFIG.9, phase-lead (e.g., as in Equation 4) as a function of frequency is depicted for three different example RC values resulting from three different process corners FF, TT, SS.

As described herein, such phase-lead typically depends on some combination of resistance and capacitance (e.g., RC). Thus, and as described in reference toFIG.8, removing or reducing process dependence of capacitances and resistances among a given bypass circuit and the corresponding phase compensation circuit can allow the resulting phase compensation to be more effective. In the example ofFIG.9, the removal or reduction of process dependence can allow the resulting phase compensation in the form of phase lag (dashed lines) being more symmetric with the corresponding phase lead, relative to the frequency axis. In some embodiments, a given phase lead due to the bypass path and the resulting phase lag due to the compensation circuit can be substantially symmetric, such that the net phase change is approximately zero for a range of frequency. For example, the FF phase lead and the FF phase lag can be substantially symmetric about the frequency axis, such that the net phase change in a given attenuation block is approximately zero for a range of frequency. In another example, the TT phase lead (which is different than the FF phase lead due to process variation) can be compensated by the TT phase lag to provide a substantially zero phase change over a range of frequency.

FIGS.10-12show examples of different operating modes that can be implemented for the attenuation circuit100ofFIG.3. InFIG.10, the attenuation circuit100is shown to be in a global bypass mode, in which the global bypass switch SBypassis ON, and each of the switches S1and S2is OFF. Accordingly, an RF signal is shown to be routed as indicated by path140. In such a mode, the RF signal is generally not subjected to a Coff capacitance; thus, undesirable phase shifting generally does not occur.

InFIG.11, the attenuation circuit100is shown to be in an attenuation mode in which A dB attenuation is being provided by the first attenuation block, and each of the second and third attenuation blocks is being bypassed. Accordingly, the global bypass switch FET SBypassis OFF, and each of the switches S1and S2is ON. Further, the first local bypass switch FET M1Ais OFF, and each of the shunt arm switch FETs M2A, M3Ais ON, while each of the second and third local bypass switch FETs M1B, M1Cis ON.

In such a mode, the global bypass switch FET SBypasspresents a global Coff, and the resulting global phase shift can be compensated as described herein by the global phase compensation circuit108. At the local level, the first local bypass switch FET M1Apresents a local Coff, and the resulting local phase shift can be compensated as described herein by the local phase compensation circuit generally indicated as104a.

InFIG.12, the attenuation circuit100is shown to be in an attenuation mode in which B+C dB attenuation is being provided by the second and third attenuation blocks, and the first attenuation block is being bypassed. Accordingly, the global bypass switch FET SBypassis OFF, and each of the switches S1and S2is ON. Further, each of the second and third local bypass switch FETs M1B, M1Cis OFF, and each of the shunt arm switch FETs M2B, M3B, M2C, M3Cis ON, while the first local bypass switch FET M1Ais ON.

In such a mode, the global bypass switch FET SBypasspresents a global Coff, and the resulting global phase shift can be compensated as described herein by the global phase compensation circuit108. At the local level, each of the first and second local bypass switch FETs M1B, M1Cpresents a respective local Coff, and the resulting local phase shift can be compensated as described herein by the respective local phase compensation circuit generally indicated as104bor104c.

FIGS.13-16show examples of how a global bypass switch FET (SBypass) as described herein (e.g.,FIGS.3and10-12) can be configured to provide desired performance when in the global bypass mode and when in the attenuation mode. For example,FIG.13shows that in some embodiments, the global bypass switch FET (SBypass) can have width (W) and length (L) dimensions, and for a given L, insertion loss at the global bypass switch FET (when ON) generally decreases when the quantity W/L increases (as shown by a plot150). Thus, if low insertion loss is desired during the global bypass mode, the global bypass switch FET can be relatively large. For example, in some embodiments, a width W of the global bypass switch FET can be as large as about 1 to 2 mm.

In some embodiments, the global bypass switch FET can be a relatively large device, and thus can provide a relatively large parasitic capacitance when in the OFF state (e.g., in the attenuation mode). Such a parasitic capacitance can cause some undesirable effects if not compensated.

For example,FIG.14shows that a mismatch level of the attenuation circuit (e.g.,100inFIG.3) can vary significantly from some uniform level when the size (e.g., W/L, for a given L) of the global bypass switch FET increases. In the example ofFIG.14, such a deviation from the uniform level is depicted by a curve152.

As described herein, use of a bypass compensation capacitance CG(e.g., inFIG.3) can also provide a more uniform mismatch level, as shown by a curve154. Such a compensation for mismatch is shown to be more significant as the global bypass switch FET gets larger.

Based on the examples ofFIGS.13and14, one can see that in an attenuation circuit having one or more features as described herein, a bypass switch FET such as the global bypass switch FET can be implemented to be relatively large to reduce insertion loss. With use of such a large FET, any increased mismatch level can be compensated by a phase compensation circuit such as the global phase compensation circuit.

As described herein, an attenuation circuit such as the example ofFIG.3can provide compensation for phase variation, as well as for gain variation. In some embodiments, such a gain variation can be at least in part due to a parasitic capacitance of the global bypass switch FET (SBypass). Viewed another way, an attenuation level provided by the attenuation circuit (when in the attenuation mode) can vary from a desired level as the size (e.g., W/L, for a given L) varies.

For example,FIG.15shows a plot156of an attenuation level that decreases from a desired level, as the FET size (W/L) increases. Such an effect typically occurs when an attenuation circuit is operating without global bypass compensation. When an attenuation circuit includes a global bypass compensation circuit as described herein, attenuation provided by the attenuation circuit remains significantly more uniform (as depicted by a plot158) as the FET size (W/L) increases.

It is noted that since the foregoing attenuation effect is at least in part due to the off-state capacitance of the global bypass switch FET, such an attenuation effect can also vary with frequency of a signal being attenuated.FIG.16shows that in some embodiments, an attenuation level can decrease from a desired level sooner as the FET size is increased, for a higher frequency. Suppose that operating frequencies f1, f2, f3and f4have values such that f1<f2<f3<f4. In such a situation, and as indicated as160, the largest frequency (f4) signal will have its attenuation begin to deviate first as the FET size is increased. The next largest frequency (f3) will begin to deviate next as the FET size is increased. The third largest frequency (f2) followed by the smallest frequency (f1) will begin to deviate similarly as the FET size is increased.

Thus, in some embodiments, and as shown in the example ofFIG.16, an attenuation level can remain significantly more uniform for a wide range of operating frequencies, when an attenuation circuit operates with a global bypass compensation circuit as described herein. Such an approximately uniform attenuation level over a range of frequencies and a range of FET sizes is depicted as a plot162.

As described herein, a local compensation circuit (e.g.,104a,104b,104cinFIG.3) can include a local compensation capacitance (e.g., C2A, C3A, C2B, C3B, C2C, C3CinFIG.3, and Cc inFIG.8).FIG.17Ashows a local compensation path170that includes such a local compensation capacitance (indicated as C2). Such a local compensation path is also shown to have a resistance R2in parallel with C2.

FIG.17Bshows that in some embodiments, the capacitance C2ofFIG.17Acan be implemented as a FET device172(e.g., as a MOSFET device) configured to provide a desired capacitance value of C2. For example, source and drain of the FET device172can be connected to the two ends of the resistance R2, and a gate of the FET device172can be grounded without a gate bias, such that the FET device172acts as a capacitance similar to that of C2ofFIG.17A.

When the local compensation capacitance is implemented as in the example ofFIG.17B, a number of desirable features can be achieved. For example, the local compensation capacitance elements can be fabricated essentially together with the various FETs (e.g., local bypass FETs M1A, M1B, M1CinFIG.3). In another example, and assuming the foregoing fabrication process commonality, the FET devices172acting as capacitances are affected by essentially the same process variations that affect the other FETS (including the local bypass FETs M1A, M1B, M1C). Accordingly, process independence can be achieved among, for example, the FET devices172and the other FETs.

FIG.18shows that in some embodiments, an attenuation circuit100(e.g., such as the attenuation circuit100ofFIG.2) having one or more features as described herein can be controlled by a controller180. Such a controller can provide various control signals to, for example, operate the various switches to achieve a bypass mode (e.g., as inFIG.10), or to provide various attenuation modes (e.g., as inFIGS.11and12). In some embodiments, the controller180can be configured to include MIPI (Mobile Industry Processor Interface) functionality.

FIG.19shows that in some embodiments, some or all of an attenuation circuit100having one or more features as described herein can be implemented on a semiconductor die200. Such a die can include a substrate202, and at least some of a phase/gain compensation circuit204(e.g., either or both of global phase compensation circuit108and local phase compensation circuits104a,104b,104cofFIG.3) can be implemented on the substrate202. For example, some or all of global compensation capacitance CGand local compensation capacitances C2A, C3A, C2B, C3B, C2C, C3Ccan be implemented as on-die capacitors.

FIGS.20and21show that in some embodiments, some or all of an attenuation circuit100having one or more features as described herein can be implemented on a packaged module300. Such a module can include a packaging substrate302configured to receive a plurality of components such as one or more die and one or more passive components.

FIG.20shows that in some embodiments, the packaged module300can include a semiconductor die200that is similar to the example ofFIG.19. Accordingly, such a die can include some or all of the attenuation circuit100, with at least some of a phase/gain compensation circuit204(e.g., either or both of global phase compensation circuit108and local phase compensation circuits104a,104b,104cofFIG.3) being implemented on the die200.

FIG.21shows that in some embodiments, the packaged module300can include a first semiconductor die210having some of the attenuation circuit100, while the rest of the attenuation circuit100is implemented on another die212, outside of a die (e.g., on the packaging substrate302), or any combination thereof. In such a configuration, some of a phase/gain compensation circuit204(e.g., either or both of global phase compensation circuit108and local phase compensation circuits104a,104b,104cofFIG.3) can be implemented on the first die210, and the rest of the phase/gain compensation circuit204can be implemented on another die212, outside of a die (e.g., on the packaging substrate302), or any combination thereof.

FIG.22shows non-limiting examples of how an attenuator having one or more features as described herein can be implemented in an RF system400. Such an RF system can include an antenna402configured to facilitate reception and/or transmission of RF signals. In the context of reception, an RF signal received by the antenna402can be filtered (e.g., by a band-pass filter410) and passed through an attenuator100before being amplified by a low-noise amplifier (LNA)412. Such an LNA-amplified RF signal can be filtered (e.g., by a band-pass filter414), passed through an attenuator100, and routed to a mixer440. The mixer440can operate with an oscillator (not shown) to yield an intermediate-frequency (IF) signal. Such an IF signal can be filtered (e.g., by a band-pass filter442) and passed through an attenuator100before being routed to an intermediate-frequency (IF) amplifier416. Some or all of the foregoing attenuators100along the receive path can include one or more features as described herein.

In the context of transmission, an IF signal can be provided to an IF amplifier420. An output of the IF amplifier420can be filtered (e.g., by a band-pass filter444) and passed through an attenuator100before being routed to a mixer446. The mixer446can operate with an oscillator (not shown) to yield an RF signal. Such an RF signal can be filtered (e.g., by a band-pass filter422) and passed through an attenuator100before being routed to a power amplifier (PA)424. The PA-amplified RF signal can be routed to the antenna402through an attenuator100and a filter (e.g., a band-pass filter426) for transmission. Some or all of the foregoing attenuators100along the transmit path can include one or more features as described herein.

In some embodiments, various operations associated with the RF system400can be controlled and/or facilitated by a system controller430. Such a system controller can include, for example, a processor432and a storage medium such as a non-transient computer-readable medium (CRM)434. In some embodiments, at least some control functionalities associated with the operation of one or more attenuators100in the RF system400can be performed by the system controller430.

In some embodiments, an attenuation circuit having one or more features as described herein can be implemented along a receive (Rx) chain. For example, a diversity receive (DRx) module can be implemented such that processing of a received signal can be achieved close to a diversity antenna.FIG.23shows an example of such a DRx module.

InFIG.23, a diversity receiver module300can be an example of the modules300ofFIGS.20and21. In some embodiments, such a DRx module can be coupled to an off-module filter513. The DRx module300can include a packaging substrate501configured to receive a plurality of components and a receiving system implemented on the packaging substrate501. The DRx module300can include one or more signal paths that are routed off the DRx module300and made available to a system integrator, designer, or manufacturer to support a filter for any desired band.

The DRx module300ofFIG.23is shown to include a number of paths between the input and the output of the DRx module300. The DRx module300is also shown to include a bypass path between the input and the output activated by a bypass switch519controlled by the DRx controller502. AlthoughFIG.23depicts a single bypass switch519, in some implementations, the bypass switch519may include multiple switches (e.g., a first switch disposed physically close to the input and a second switch disposed physically close to the output). As shown inFIG.23, the bypass path does not include a filter or an amplifier.

The DRx module300is shown to include a number of multiplexer paths including a first multiplexer511and a second multiplexer512. The multiplexer paths include a number of on-module paths that include the first multiplexer511, a bandpass filter613a-613dimplemented on the packaging substrate501, an amplifier614a-614dimplemented on the packaging substrate501, and the second multiplexer512. The multiplexer paths include one or more off-module paths that include the first multiplexer511, a bandpass filter513implemented off the packaging substrate501, an amplifier514, and the second multiplexer512. The amplifier514may be a wide-band amplifier implemented on the packaging substrate501or may also be implemented off the packaging substrate501. In some embodiments, the amplifiers614a-614d,514may be variable-gain amplifiers and/or variable-current amplifiers.

A DRx controller502can be configured to selectively activate one or more of the plurality of paths between the input and the output. In some implementations, the DRx controller502can be configured to selectively activate one or more of the plurality of paths based on a band select signal received by the DRx controller502(e.g., from a communications controller). The DRx controller502may selectively activate the paths by, for example, opening or closing the bypass switch519, enabling or disabling the amplifiers614a-614d,514, controlling the multiplexers511,512, or through other mechanisms. For example, the DRx controller502may open or close switches along the paths (e.g., between the filters613a-613d,513and the amplifiers614a-614d,514) or by setting the gain of the amplifiers614a-614d,514to substantially zero.

In the example DRx module300ofFIG.23, some or all of the amplifiers614a-614d,514can be provided with an attenuation circuit100having one or more features as described herein. For example, each of such amplifiers is shown to have an attenuation circuit100implemented on its input side. In some embodiments, a given amplifier can have an attenuation circuit on its input side and/or on its output side.

In some implementations, an architecture, device and/or circuit having one or more features described herein can be included in an RF device such as a wireless device. Such an architecture, device and/or circuit can be implemented directly in the wireless device, in one or more modular forms as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, a wireless router, a wireless access point, a wireless base station, etc. Although described in the context of wireless devices, it will be understood that one or more features of the present disclosure can also be implemented in other RF systems such as base stations.

FIG.24depicts an example wireless device700having one or more advantageous features described herein. As described in reference toFIGS.22and23, one or more attenuators having one or more features as described herein can be implemented in a number of places in such a wireless device. For example, in some embodiments, such advantageous features can be implemented in a module such as a diversity receive (DRx) module300having one or more low-noise amplifiers (LNAs). Such a DRx module can be configured as described herein in reference toFIGS.20,21and23. In some embodiments, an attenuator having one or more features as described herein can be implemented along an RF signal path before and/or after an LNA.

In the example ofFIG.24, power amplifiers (PAs) in a PA module712can receive their respective RF signals from a transceiver710that can be configured and operated to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver710is shown to interact with a baseband sub-system708that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver710. The transceiver710is also shown to be connected to a power management component706that is configured to manage power for the operation of the wireless device700. Such power management can also control operations of the baseband sub-system708and other components of the wireless device700.

The baseband sub-system708is shown to be connected to a user interface702to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system708can also be connected to a memory704that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

In the example ofFIG.24, the DRx module300can be implemented between one or more diversity antennas (e.g., diversity antenna730) and the ASM714. Such a configuration can allow an RF signal received through the diversity antenna730to be processed (in some embodiments, including amplification by an LNA) with little or no loss of and/or little or no addition of noise to the RF signal from the diversity antenna730. Such processed signal from the DRx module300can then be routed to the ASM through one or more signal paths.

In the example ofFIG.24, a main antenna720can be configured to, for example, facilitate transmission of RF signals from the PA module712. In some embodiments, receive operations can also be achieved through the main antenna.

A number of other wireless device configurations can utilize one or more features described herein. For example, a wireless device does not need to be a multi-band device. In another example, a wireless device can include additional antennas such as diversity antenna, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS.

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

While some embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.