Patent ID: 12189457

The features and advantages of the disclosed technologies will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

DETAILED DESCRIPTION

I. Introduction

The following detailed description refers to the accompanying drawings that illustrate exemplary embodiments of the present invention. However, the scope of the present invention is not limited to these embodiments, but is instead defined by the appended claims. Thus, embodiments beyond those shown in the accompanying drawings, such as modified versions of the illustrated embodiments, may nevertheless be encompassed by the present invention.

References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” or the like, indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art(s) to implement such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Descriptors such as “first”, “second”, “third”, etc. are used to reference some elements discussed herein. Such descriptors are used to facilitate the discussion of the example embodiments and do not indicate a required order of the referenced elements, unless an affirmative statement is made herein that such an order is required.

II. Example Embodiments

Example embodiments described herein are capable of reducing latency of changing an operating state of a processor from a low-power state to a normal-power state. The low-power state is configured to cause the processor to consume a first amount of power. For instance, low-power state may be achieved by reducing a frequency at which the processor operates, reducing a voltage domain of the processor, and/or turning off components of the processor. The normal-power state is configured to cause the processor to consume a second amount of power that is greater than the first amount. For instance, the normal-power state may be achieved by increasing the frequency at which the processor operates, increasing a voltage domain of the processor, and/or turning on components of the processor that were turned off during the low-power state.

Example techniques described herein have a variety of benefits as compared to conventional techniques for bringing a processor out of a low-power state. For instance, the example techniques may be capable of reducing a latency associated with bringing the processor out of the low-power state. The example techniques may be capable of reducing an amount of power consumed by the processor while reducing the latency. In a first example, a notification (e.g., a hint) may be provided to the processor to exit a power saving mode, which may enable the processor to transition to a normal-power mode before latency-sensitive traffic enters the processor. For instance, arrival of a network packet at a serializer/de-serializer (SerDes) of a hardware component may trigger the hardware component to provide the notification to the processor. Even if the network packet is directed to only internal functions of the hardware component, arrival of the network packet at the hardware component may trigger the hardware component to provide the notification to the processor. In a second example, the processor may exit the low-power state immediately upon receipt of a packet and/or without taking into consideration how much the processor is being utilized. By reducing the latency, the example techniques may increase efficiency of the processor and/or a computing system that includes the processor.

The example techniques may reduce an amount of time and/or resources (e.g., processor cycles, memory, network bandwidth) that is consumed to change an operating state of a processor from a low-power state to a normal-power state. For example, by providing a notification (e.g., a hint) to the processor (or receiving the notification by the processor), indicating that a transaction layer packet subsequently will be provided to the processor, the example techniques may enable the processor to avoid consuming the time and resources that would have been consumed to change the operating state of the processor after the transaction layer packet is received by the processor. For instance, providing the notification to the processor (or receiving the notification by the processor) may enable the processor to change its state from the low-power state to the normal-power state prior to the transaction layer packet being received by the processor. In another example, by changing the operating state of the processor from the low-power state to the normal-power state immediately upon receipt of a transaction layer packet by the processor and/or without taking into consideration how much the processor is being utilized, the example techniques may enable the processor to avoid consuming the time and resources that would have been consumed to change the operating state of the processor during a delay associated with the conventional techniques (e.g., while waiting for a utilization threshold to be reached or while waiting for a transition from one C-state to another C-state to occur).

FIG.1is a block diagram of an example latency reduction system100in accordance with an embodiment. Generally speaking, the latency reduction system100operates to provide information between a first computing system102and a second computing system106. For instance, the latency reduction system100may provide information to a user of the first computing device102in response to requests (e.g., hypertext transfer protocol (HTTP) requests) that are received from the user. The information may include documents (Web pages, images, audio files, video files, etc.), output of executables, and/or any other suitable type of information. The information is included in network packet(s)116. In accordance with example embodiments described herein, the latency reduction system100reduces latency of changing an operating state of a processor (e.g., processor system110) from a low-power state to a normal-power state. Detail regarding techniques for reducing latency of changing an operating state of a processor from a low-power state to a normal-power state is provided in the following discussion.

As shown inFIG.1, the latency reduction system100includes the first computing device102, a network104, and a second computing device106. Communication between the first computing device102and the second computing device106is carried out over the network104using well-known network communication protocols. The network104is a packet-switched network. For instance, the network104may be a wide-area network (e.g., the Internet), a local area network (LAN), another type of network, or a combination thereof.

The first computing device102is a processing system that is capable of communicating with the second computing system106. An example of a processing system is a system that includes at least one processor that is capable of manipulating data in accordance with a set of instructions. For instance, a processing system may be a computer, a personal digital assistant, etc. The first computing device102is configured to provide requests to the second computing device106for requesting information stored on (or otherwise accessible via) the second computing device106. For instance, a user may initiate a request for executing a computer program (e.g., an application) using a client (e.g., a Web browser, Web crawler, or other type of client) deployed on the first computing device102that is owned by or otherwise accessible to the user. In accordance with some example embodiments, the first computing device102is capable of accessing domains (e.g., Web sites) hosted by the second computing device106, so that the first computing device102may access information that is available via the domains. Such domain may include Web pages, which may be provided as hypertext markup language (HTML) documents and objects (e.g., files) that are linked therein, for example.

The first computing device102may include any client-enabled system or device, including but not limited to a desktop computer, a laptop computer, a tablet computer, a wearable computer such as a smart watch or a head-mounted computer, a personal digital assistant, a cellular telephone, an Internet of things (IoT) device, or the like.

The second computing device106is a processing system that is capable of communicating with the first computing device102. The second computing device106is configured to provide information to a user of the first computing device102in response to receiving requests from the user. For instance, the second computing device106may execute computer program(s) that provide the information. The information may include documents (Web pages, images, audio files, video files, etc.), output of executables, or any other suitable type of information. Any one or more of the computer programs may be a cloud computing service. A cloud computing service is a service that executes at least in part in the cloud. The cloud may be a remote cloud, an on-premises cloud, or a hybrid cloud. It will be recognized that an on-premises cloud may use remote cloud services. Examples of a cloud computing service include but are not limited to Microsoft 365® (or Excel® or Word™ therein) developed and distributed by Microsoft Corporation, Google Docs Editors™ (or Google Sheets™ or Google Docs™ therein) developed and distributed by Google Inc., and iWork® (or Numbers™ or Pages™ therein) developed and distributed by Apple Inc. In accordance with some example embodiments, the second computing device106is configured to host Web site(s), so that the Web site(s) are accessible to a user of the first computing device102.

The second computing device106is shown to include a hardware system108and a processor system110. The hardware system108is a system that includes hardware and that is configured to generate transaction layer packet(s)120based on receipt of network packet(s)116. For instance, the hardware system108may convert the network packet(s)116into the transaction layer packet(s)120. A network packet is a packet that is received via a packet-switched network. For instance, the network packet may be configured in accordance with the network layer (i.e., layer 3) of the Open Systems Interconnection (ISO) model. A transaction layer packet is a packet that is configured in accordance with a bus standard. Examples of a bus standard include but are not limited to the Peripheral Component Interconnect™ (PCI™) bus standard and the Accelerated Graphics Port™ (AGP™) bus standard, each of which was developed by Intel Corporation; the PCI eXtended™ (PCI-X®) bus standard, which was developed jointly by International Business Machines Corporation (IBM), HP Inc., and Compaq Computer Corporation; and the PCI Express™ (PCIe®) bus standard, which was developed jointly by Intel Corporation, Dell Inc., HP Inc., and IBM. The transaction layer packet may be further configured in accordance with a Compute Express Link (CXL) open standard, which was developed primarily by Intel Corporation, though the example embodiments are not limited in this respect. In an example, the transaction layer packet may include an interrupt. For instance, the interrupt may request that the processor system110provide data to the hardware system108. In another example, the transaction layer packet may include an instruction to read data from a store and/or to write data to a store.

The hardware system108includes latency reduction logic122. The latency reduction logic122is configured to reduce latency of changing an operating state of the processor system110from a low-power state to a normal-power state. In an example implementation, the latency reduction logic122receives the network packet(s)116via the network104. Based at least in part on receipt of the network packet(s)116, prior to transaction layer packet(s)120that are based at least in part on the network packet(s)116being provided to the processor system110by the latency reduction logic122, the latency reduction logic122triggers a change of an operating state of the processor system110from a low-power state to a normal-power state by asynchronously providing a notification118to the processor system110at a first time instance. The notification118indicates that the transaction layer packet(s)120are to be provided to the processor system110at a second time instance that temporally follows the first time instance. The low-power state is configured to cause the processor system110to consume a first amount of power. The normal-power state is configured to cause the processor system110to consume a second amount of power that is greater than the first amount. The latency reduction logic122causes the transaction layer packet(s)120to be processed in the normal-power state by providing the transaction layer packet(s)120to the processor system110at the second time instance.

The hardware system108includes a PCIe WAKE #pin112via which the latency reduction logic122may provide the notification118to the processor system110. For instance, the latency reduction logic122may provide the notification118to the processor system110via an out-of-band connection (i.e., via a connection that is different from the connection via which the latency reduction logic122provides the transaction layer packet(s)120to the processor system110).

The processor system110is a system that includes at least one processor and that is configured to process transaction layer packets (e.g., the transaction layer packet(s)120that are received from the hardware system108).

The processor system110includes latency reduction logic124. The latency reduction logic124is configured to reduce latency of changing the operating state of the processor system110from the low-power state to the normal-power state. In a first example implementation, the latency reduction logic124receives the notification118from the hardware system108at a first time instance. In accordance with this implementation, the notification indicates that the transaction layer packet(s)120, which are based at least in part on the network packet(s)116, are to be received by the processor system110from the hardware system108at a second time instance that temporally follows the first time instance. Based at least in part on receipt of the notification118, the operating state of the processor system110is changed from the low-power state to the normal-power state. The low-power state is configured to cause the processor system110to consume a first amount of power. The normal-power state is configured to cause the processor system110to consume a second amount of power that is greater than the first amount. If the processor system110is already in the normal-power state at the first time instance, the latency reduction logic124may ignore the notification118. The latency reduction logic124receives the transaction layer packet(s)120from the hardware system108at the second time instance. The latency reduction logic124processes the transaction layer packet(s)120in the normal-power state based at least in part on receipt of the transaction layer packet(s)120at the second time instance.

In a second example implementation, the latency reduction logic124receives the transaction layer packet(s)120, which are based at least in part on the network packet(s)116, from the hardware system108. Based at least in part on receipt of the transaction layer packet(s)120and without taking into consideration an extent to which the processor system110is utilized, the latency reduction logic124triggers a change of the operating state of the processor system110from the low-power state to the normal-power state. The low-power state is configured to cause the processor system110to consume a first amount of power. The normal-power state is configured to cause the processor system110to consume a second amount of power that is greater than the first amount. The latency reduction logic124processes the transaction layer packet(s)120in the normal-power state.

The processor system110includes a PCIe WAKE #pin114via which the latency reduction logic124may receive the notification118from the hardware system108. For instance, the latency reduction logic124may receive the notification118from the hardware system108via an out-of-band connection (i.e., via a connection that is different from the connection via which the latency reduction logic124receives the transaction layer packet(s)120from the hardware system108). It will be recognized that each of the PCIe WAKE #pin112and the PCIe WAKE #pin114may be a PCIe-compliant general-purpose input/output (GPIO) pin.

The latency reduction logic122and/or the latency reduction logic124may be implemented in various ways to reduce latency of changing the operating state of the processor system110from the low-power state to the normal-power state, including being implemented in hardware, software, firmware, or any combination thereof. For example, the latency reduction logic122and/or the latency reduction logic124may be implemented as computer program code configured to be executed in one or more processors. In another example, at least a portion of the latency reduction logic122and/or the latency reduction logic124may be implemented as hardware logic/electrical circuitry. For instance, at least a portion of the latency reduction logic122and/or the latency reduction logic124may be implemented in a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip system (SoC), a complex programmable logic device (CPLD), etc. Each SoC may include an integrated circuit chip that includes one or more of a processor (a microcontroller, microprocessor, digital signal processor (DSP), etc.), memory, one or more communication interfaces, and/or further circuits and/or embedded firmware to perform its functions.

It will be recognized that the hardware system108need not necessarily include the PCIe WAKE #pin112and/or the latency reduction logic122. Furthermore, the hardware system108may include components in addition to or in lieu of the PCIe WAKE #pin112and/or the latency reduction logic122. It will be further recognized that the processor system110need not necessarily include the PCIe WAKE #pin114and/or the latency reduction logic124. Furthermore, the processor system110may include components in addition to or in lieu of the PCIe WAKE #pin114and/or the latency reduction logic124.

FIG.2is a block diagram of a computing device200, which is an example implementation of the second computing device106shown inFIG.1, in accordance with an embodiment. As shown inFIG.2, the computing device200includes a plurality of hardware systems208A-208N, a Boolean OR gate226, and a processor system210. Each of the hardware systems208A-208N is configured to operate in a manner similar to the hardware system108shown inFIG.1. For instance, the first hardware system208A may receive and process a first portion of the packet(s)116; the second hardware system208B may receive and process a second portion of the packet(s)116that is different from the first portion, and so on. Each of the hardware systems208A-208N is configured to provide a notification to the processor system210upon receipt of a network packet. The first hardware system208A is shown to generate a notification218to indicate that the first hardware system208A has received a network packet. Each of the hardware systems208A-208N may be a PCIe-compliant device and/or may operate in accordance with a Non-Volatile Memory Express (NVMe) open logical-device interface specification, which was developed by Intel Corporation, though the example embodiments are not limited in this respect.

The hardware systems208A-208N are shown to include respective PCIe WAKE #pins212A-212N for illustrative purposes. For instance, the hardware systems208A-208N may send their notifications to the processor system210via the respective PCIe WAKE #pins212A-212N.

The Boolean OR gate226is configured to perform a Boolean OR operation on the outputs of the hardware systems208A-208N. The Boolean OR gate226forwards a notification that is received from any of the hardware systems208A-208N to the processor system210such that a notification from any of the hardware systems208A-208N triggers the processor system210to change its operating system from a low-power state to a normal-power state.

The processor system210is configured to operate in a manner similar to the processor system110shown inFIG.1. For instance, based at least in part on receipt of a notification (e.g., notification218) from any of the hardware systems208A-208N via the Boolean OR gate226, the processor system210changes its operating state from the low-power state to the normal-power state.

The processor system210is shown to include a PCIe WAKE #pin214for illustrative purposes. For instance, the processor system210may receive notifications from the Boolean OR gate226via the PCIe WAKE #pin214.

FIG.3is an example activity diagram300for reducing latency of changing an operating state of a processor system310from a low-power state to a normal-power state in accordance with an embodiment.FIG.3depicts a first computing system302and a second computing system306. The first computing system302includes first hardware324. The second computing system306includes second hardware308, the processor system310, and third hardware326. Activities330,332,334,336,338,340,342, and344will now be described with reference to the first hardware324, the second hardware308, the processor system310, and the third hardware326.

In activity330, the first hardware324provides a network packet to the second hardware308.

In activity332, the second hardware308provides a notification to the processor system310(e.g., based on receipt of the network packet in activity330). The notification indicates that transaction layer packet(s) will be provided to the processor system310at a future (e.g., subsequent) time. By providing the notification to the processor system310, the second hardware308may trigger the processor system310to change an operating state of the processor system310from a low-power state to a normal-power state. In the low-power state, the processor system310operates in a manner that consumes a relatively low amount of power. For instance, in the low-power state, selected portions of the functionality of the processor system310may be turned off, frequencies of clock signals of the processor system310may be reduced (e.g., an operating frequency of the processor system310may be reduced), and/or voltages that are used for clock signals of the processor system310may be reduced. In the normal-power state, the processor system310operates in a manner that consumes a relatively high amount of power. For instance, in the normal-power state, portions of the functionality of the processor system310that were turned off in the low-power state may be turned on, frequencies of clock signals of the processor system310may be increased (e.g., an operating frequency of the processor system310may be increased), and/or voltages that are used for clock signals of the processor system310may be increased.

In activity334, the processor system310changes its state from the low-power state to the normal-power state based at least in part on receipt of the notification from the second hardware308. The processor system310may ensure that its state is changed from the low-power state to the normal-power state on or before the future time. For example, the notification may specify the future time at which the transaction layer packet(s) will be provided to the processor system310. In accordance with this example, the processor system310may schedule aspects of its functionality to be turned on, frequencies of clock signals to be increased, and/or voltages of clock signals to be increased at times early enough to ensure that the transition from the low-power state to the normal-power state is completed by the future time.

In activity336, the second hardware308processes the network packet. For instance, the second hardware308may decrypt the network packet and/or decompress the network packet.

In activity338, the second hardware308generates transaction layer packet(s) based on the network packet. For instance, the second hardware308may divide the network packet into portion(s) and format those portion(s) in accordance with a bus standard, such as the PCIe® bus standard, to generate the respective transaction layer packet(s). The second hardware308may perform any of a variety of operations on the transaction layer packet(s) in preparation for the transaction layer packet(s) to be sent to another entity, such as the third hardware326. For instance, the second hardware308may encode the transaction layer packet(s) and/or encrypt the transaction layer packet(s).

In activity340, the second hardware308provides the transaction layer packet(s) to the processor system310. It will be recognized that the operating state of the processor system310may be changed from the low-power state to the normal-power state in activity334before the transaction layer packet(s) are received by the processor system310upon completion of activity340. For instance, activity334may be completed while any one or more of the activities336,338, and/or340are being performed.

In activity342, the processor system310processes the transaction layer packet(s). For instance, the processor system310may decrypt the transaction layer packet(s) and/or decode the transaction layer packet(s). Decoding each transaction layer packet may include identifying the header of the packet, the body of the packet, the prefix(es) of the packet, the suffix(es) of the packet, and so on.

In activity344, the processor system310forwards the transaction their packet(s) to the third hardware326. By forwarding the transaction layer packet(s) to the third hardware326, the processor system310may enable the third hardware326to process the transaction layer packet(s). It will be recognized that the third hardware326and the second hardware308may be the same, though the example embodiments are not limited in this respect.

In some example embodiments, one or more of the activities330,332,334,336,338,340,342, and/or344of the activity diagram300may not be performed. Moreover, activities in addition to or in lieu of the activities330,332,334,336,338,340,342, and/or344may be performed.

FIG.4depicts a flowchart400of an example method for reducing latency of changing an operating state of a processor from a low-power state to a normal-power state in accordance with an embodiment. Flowchart400may be performed by the hardware system108shown inFIG.1, for example. For illustrative purposes, flowchart400is described with respect to a hardware system500shown inFIG.5, which is an example implementation of the hardware system108. The hardware system500may be any suitable type of hardware system, including but not limited to a network interface controller (NIC), an accelerator, storage (e.g., memory, such as a solid-state drive (SSD)), or a graphical processing unit (GPU). As shown inFIG.5, the hardware system500includes latency reduction logic522. The latency reduction logic522includes a state controller552, packet conversion logic554, time determination logic556, and time selection logic558. Further structural and operational embodiments will be apparent to persons skilled in the relevant art(s) based on the discussion regarding flowchart400.

As shown inFIG.4, the method of flowchart400begins at step402. In step402, a network packet is received via a network. In an example implementation, the state controller552receives a network packet516.

At step404, a change of the operating state of the processor from the low-power state to the normal-power state is triggered by asynchronously providing a notification to the processor at a first time instance. The change of the operating state is triggered based at least in part on the network packet being received at step402. The change of the operating state is triggered prior to a transaction layer packet that is based at least in part on the network packet being provided to the processor. For instance, the processor may be triggered to change the operating state of the processor in anticipation of the transaction layer packet being provided to the processor. The notification indicates that the transaction layer packet is to be provided to the processor at a second time instance that temporally follows the first time instance. The low-power state is configured to cause the processor to consume a first amount of power. The normal-power state is configured to cause the processor to consume a second amount of power that is greater than the first amount. In an example implementation, the state controller552triggers the change of the operating state of the processor by asynchronously providing a notification518to the processor at the first time instance. For instance, state controller552may trigger the change as a result of receiving the network packet516. The notification518indicates that a transaction layer packet520is to be provided to the processor at the second time instance.

Triggering the change of the operating state of the processor at step404may reduce latency with regard to changing the state of the processor from the low-power state to the normal-power state. Triggering the change of the operating state of the processor at step404may increase efficiency of the processor and/or the computing system that includes the processor. Triggering the change of the operating state of the processor at step404may enable the processor to reduce power consumption without delaying an exit from the low-power state to the normal-power state.

In an example embodiment, the notification indicates an amount of time between the first time instance at which the notification is asynchronously provided to the processor and the second time instance at which the transaction layer packet is to be provided to the processor. For example, the notification may include a first time stamp that indicates the first time instance and a second time stamp that indicates the second time instance. In another example, the notification specifies a difference between the first time instance and the second time instance without including a first time stamp that indicates the first time instance and/or a second time stamp that indicates the second time instance.

In another example embodiment, triggering the change of the operating state of the processor at step404includes triggering the processor to increase a frequency at which the processor operates (i.e., the operating frequency) by asynchronously providing the notification to the processor at the first time instance. For example, the processor may be triggered to increase the operating frequency from a first frequency (e.g., 0.7 GHz) to a second frequency (e.g., 2.0 GHz) that is greater than the first frequency. In another example, increasing the operating frequency may include increasing a rate at which a clock that is used to perform operations by the processor operates (e.g., oscillates).

In yet another example embodiment, triggering the change of the operating state of the processor at step404includes triggering the processor to increase a voltage of a clock that is used to perform operations by the processor by asynchronously providing the notification to the processor at the first time instance. For instance, the processor may be triggered to increase the voltage of the clock from a first voltage to a second voltage that is greater than the first voltage.

In still another example embodiment, triggering the change of the operating state of the processor at step404includes triggering the processor to switch a portion of the processor from an off state to an on state by asynchronously providing the notification to the processor at the first time instance. For example, the processor may be triggered to turn on voltages that were turned off while the processor was in the low-power state. In another example, the processor may be triggered to reverse clock gating that was performed by the processor in the low-power state to turn the portion of the processor off. Clock gating is a power-saving technique that switches off circuit(s) and/or portion(s) thereof to reduce dynamic power consumption.

In another example embodiment, triggering the change of the operating state of the processor at step404includes asynchronously providing the notification to the processor via a Peripheral Component Internet Express (PCIe) WAKE #pin of the hardware system at the first time instance.

In yet another example embodiment, triggering the change of the operating state of the processor at step404includes, at the first time instance, asynchronously providing the notification to the processor via a first connection that is included in a plurality of connections that connect a plurality of respective hardware systems to the processor via a Boolean OR gate.

At step406, the transaction layer packet, which is based at least in part on the network packet, is caused to be processed in the normal-power state by providing the transaction layer packet to the processor at the second time instance. For instance, the transaction layer packet may be provided to the processor via a PCIe connection. A PCI3 connection is a connection that operates in accordance with the PCIe® bus standard. In an example implementation, the packet conversion logic54causes the transaction layer packet520to be processed in the normal-power state by providing the transaction layer packet520to the processor at the second time instance. For instance, the state controller552may forward the network packet516to the packet conversion logic554to enable the packet conversion logic554to generate the transaction layer packet520based at least in part on the network packet516. For example, the packet conversion logic554may convert the network packet516into one or more transaction layer packets, which include the transaction layer packet520. In accordance with this example, the packet conversion logic554may process the network packet516(e.g., by decrypting and/or decompressing the network packet516) prior to converting the network packet516into the one or more transaction layer packets. The packet conversion logic554may provide the transaction layer packet520to the processor in response to generating the transaction layer packet520.

In some example embodiments, one or more steps402,404, and/or406of flowchart400may not be performed. Moreover, steps in addition to or in lieu of steps402,404, and/or406may be performed. For instance, in an example embodiment, the notification is asynchronously provided to the processor at step404prior to completion of processing of the network packet by the hardware system. The processing of the network packet includes generating the transaction layer packet based at least in part on the network packet. The processing of the network packet may include other types of processing, such as decrypting the network packet and/or decompressing the network packet, though the example embodiments are not limited in this respect.

In a first aspect of this embodiment, the method of flowchart400further includes determining an amount of time that is to be consumed to complete the processing of the network packet by the hardware system. In an example implementation, the time determination logic556determines the amount of time that is to be consumed to complete the processing of the network packet516by the packet conversion logic554. For example, the time determination logic556may monitor how long the packet conversion logic554takes to complete processing of network packets. In accordance with this example, the time determination logic556may determine the amount of time that is to be consumed to complete the processing of the network packet516based on historical measurements indicating how long the packet conversion logic554has taken in the past to complete processing of the network packets. The time determination logic556may generate a time estimation560to indicate the amount of time that is to be consumed to complete the processing of the network packet516by the packet conversion logic554. In accordance with the first aspect, the method of flowchart400further includes selecting the first time instance at which the notification is provided to the processor based at least in part on the amount of time. For instance, the first time instance may be selected based at least in part on a difference between the first time instance and the second time instance being equal to the amount of time that is to be consumed to complete the processing of the network packet by the hardware system. In an example implementation, the time selection logic558selects the first time instance based at least in part on the amount of time, as indicated by the time estimation560. The time selection logic558may generate a time indicator562to indicate the first time instance, which may enable the state controller552to determine the first time instance at which to provide the notification518to the processor.

In a second aspect of this embodiment, the method of flowchart400further includes completing the processing of the network packet to generate the transaction layer packet. In an example implementation, the packet conversion logic554completes the processing of the network packet516to generate the transaction layer packet520. In accordance with the second aspect, the transaction layer packet is provided to the processor at the second time instance based at least in part on the processing of the network packet being completed.

It will be recognized that the hardware system500may not include one or more of the state controller552, the packet conversion logic554, the time determination logic556, and/or the time selection logic558. Furthermore, the hardware system500may include components in addition to or in lieu of the state controller552, the packet conversion logic554, the time determination logic556, and/or the time selection logic558.

FIG.6depicts a flowchart600of another example method for reducing latency of changing an operating state of a processor system from a low-power state to a normal-power state in accordance with an embodiment. Flowchart600may be performed by the processor system110shown inFIG.1, for example. For illustrative purposes, flowchart600is described with respect to a processor system700shown inFIG.7, which is an example implementation of the processor system110. As shown inFIG.7, the processor system700includes latency reduction logic724. The latency reduction logic724includes a state controller772, attribute selection logic774, and packet processing logic776. Further structural and operational embodiments will be apparent to persons skilled in the relevant art(s) based on the discussion regarding flowchart600.

As shown inFIG.6, the method of flowchart600begins at step602. In step602, a notification is received from a hardware system at a first time instance. The notification indicates that a transaction layer packet, which is based at least in part on a network packet, is to be received by the processor system from a hardware system at a second time instance that temporally follows the first time instance. The hardware system may be any suitable type of hardware system, including but not limited to a network interface controller (NIC), an accelerator, storage (e.g., memory, such as a solid-state drive (SSD)), or a graphical processing unit (GPU). In an example implementation, the state controller772receives a notification718at the first time instance. The notification718indicates that a transaction layer packet720, which is based at least in part on a network packet, is to be received by the processor system700from a hardware system at a second time instance that temporally follows the first time instance.

In an example implementation, the notification is received from the hardware system at step602via a Peripheral Component Internet Express (PCIe) WAKE #pin of the processor system at the first time instance.

In another example implementation, the notification is received from the hardware system at step602at the first time instance via a first connection that is included in a plurality of connections that connect a plurality of respective hardware systems to the processor system via a Boolean OR gate.

At step604, the operating state of the processor system is changed from the low-power state to the normal-power state based at least in part on receipt of the notification. The low-power state is configured to cause the processor system to consume a first amount of power. The normal-power state is configured to cause the processor system to consume a second amount of power that is greater than the first amount. In an example implementation, the state controller772changes the operating state of the processor system700from the low-power state to the normal-power state based at least in part on receipt of the notification718. The low-power state is configured to cause the processor system700to consume a first amount of power. The normal-power state is configured to cause the processor system700to consume a second amount of power that is greater than the first amount.

Receiving the notification at step602and/or changing the operating state of the processor system at step604may reduce latency with regard to changing the state of the processor system from the low-power state to the normal-power state. Receiving the notification at step602and/or changing the operating state of the processor system at step604may increase efficiency of the processor system and/or the computing system that includes the processor system. Receiving the notification at step602and/or changing the operating state of the processor system at step604may enable the processor system to reduce power consumption without delaying an exit from the low-power state to the normal-power state.

In an example embodiment, changing the operating state of the processor system at step604is performed before the transaction layer packet is received from the hardware system at the second time instance.

In another example embodiment, changing the operating state of the processor system at step604includes increasing a frequency at which the processor system operates, increasing a voltage of a clock that is used by the processor system to perform operations, and/or switching a portion of the processor system from an off state to an on state.

At step606, the transaction layer packet is received from the hardware system at the second time instance. In an example implementation, the packet processing logic776receives the transaction layer packet720from the hardware system at the second time instance.

At step608, the transaction layer packet is processed in the normal-power state (e.g., based at least in part on receipt of the transaction layer packet at the second time instance). For instance, processing the transaction layer packet may include decrypting the transaction layer packet and/or decoding the transaction layer packet. In an example implementation, the packet processing logic776processes the transaction layer packet720in the normal-power state based at least in part on receipt of the transaction layer packet720at the second time instance.

In an example embodiment, processing the transaction layer packet at step608includes instructing the hardware system to perform a designated task based at least in part on receipt of the transaction layer packet. For example, the designated task may include processing a designated image and displaying the designated image. In another example, the designated task may include processing a designated audio file and playing the designated audio file.

In some example embodiments, one or more steps602,604,606, and/or608of flowchart600may not be performed. Moreover, steps in addition to or in lieu of steps602,604,606, and/or608may be performed. For instance, in an example embodiment, the notification indicates an amount of time between the first time instance at which the notification is received by the processor system from the hardware system and the second time instance at which the transaction layer packet is to be received by the processor system from the hardware system. In accordance with this embodiment, the method of flowchart600further includes selecting an attribute of the processor system from a plurality of attributes of the processor system to be changed based at least in part on the processor system being capable of changing the attribute from a first value to a second value within the amount of time between the first time instance and the second time instance. In an example implementation, the attribute selection logic774selects an attribute of the processor system700to be changed from a plurality of attributes of the processor system700. For instance, the state controller772may generate a time estimation778, which indicates the amount of time between the first instance and the second instance. The attribute selection logic774may analyze the time estimation778to determine the amount of time. The attribute selection logic774may determine an amount of time that the processor system700consumes to change each of the plurality of attributes. The attribute selection logic774may further determine which of the plurality of attributes can be changed simultaneously. Based on the determined amount of time that the processor system700consumes to change each of the plurality of attributes and further based on which of the plurality of attributes can be changed simultaneously, the attribute selection logic774may determine which of the plurality of attributes the processor system700is capable of changing within the amount of time indicated by the time estimation778. The attribute selection logic774may select the attribute of the processor system700to be changed from the attribute(s) the processor system700is capable of changing within the amount of time indicated by the time estimation778. In further accordance with this embodiment, changing the operating state of the processor system at step604includes changing the selected attribute of the processor system from the first value to the second value.

In an aspect of this embodiment, selecting the attribute includes selecting a first subset of the plurality of attributes and not selecting a second subset of the plurality of attributes based at least in part on the processor system being capable of changing each attribute in the first subset from a respective first value to a respective second value within the amount of time between the first time instance and the second time instance. In accordance with this aspect, changing the operating state of the processor system at step604includes changing each attribute in the first subset from the respective first value to the respective second value.

It will be recognized that the processor system700may not include one or more of the state controller772, the attribute selection logic774, and/or the packet processing logic776. Furthermore, the processor system700may include components in addition to or in lieu of the state controller772, the attribute selection logic774, and/or the packet processing logic776.

FIG.8is another example activity diagram800for reducing latency of changing an operating state of a processor system810from a low-power state to a normal-power state in accordance with an embodiment.FIG.8depicts a first computing system802and a second computing system806. The first computing system802includes first hardware824. The second computing system806includes second hardware808, the processor system810, and third hardware826. Activities830,834,836,838,840,842, and844will now be described with reference to the first hardware824, the second hardware808, the processor system810, and the third hardware826.

In activity830, the first hardware824provides a network packet to the second hardware808.

In activity836, the second hardware808processes the network packet. For instance, the second hardware808may decrypt the network packet and/or decompress the network packet.

In activity838, the second hardware808generates transaction layer packet(s) based on the network packet. For instance, the second hardware808may divide the network packet into portion(s) and format those portion(s) in accordance with a bus standard, such as the PCIe® bus standard, to generate the respective transaction layer packet(s). The second hardware808may perform any of a variety of operations on the transaction layer packet(s) in preparation for the transaction layer packet(s) to be sent to another entity, such as the third hardware826. For instance, the second hardware808may encode the transaction layer packet(s) and/or encrypt the transaction layer packet(s).

In activity840, the second hardware808provides the transaction layer packet(s) to the processor system810.

In activity834, the processor system810changes its state from the low-power state to the normal-power state based at least in part on receipt of the transaction layer packet(s) from the second hardware808. The processor system810may change its state form the low-power state to the normal-power state without taking into consideration an extent to which the processor system810is utilized. For instance, the processor system810may change its state independently from whether utilization of the processor system810is greater than or equal to a utilization threshold. The utilization of the processor system810may indicate a number of processor cycles of the processor system810that are consumed within a designated period of time, a number of tasks that are performed by the processor system810within a designated period of time, and/or a proportion of the resources of the processor system810that are consumed at a time instance or within a designated period of time (e.g., the proportion being greater than a proportion threshold at the time instance or greater than the proportion threshold for a duration of time that is greater than a duration threshold).

In the low-power state, the processor system810operates in a manner that consumes a relatively low amount of power. For instance, in the low-power state, selected portions of the functionality of the processor system810may be turned off, frequencies of clock signals of the processor system810may be reduced (e.g., an operating frequency of the processor system810may be reduced), and/or voltages that are used for clock signals of the processor system810may be reduced. In the normal-power state, the processor system810operates in a manner that consumes a relatively high amount of power. For instance, in the normal-power state, portions of the functionality of the processor system810that were turned off in the low-power state may be turned on, frequencies of clock signals of the processor system810may be increased (e.g., an operating frequency of the processor system810may be increased), and/or voltages that are used for clock signals of the processor system810may be increased.

In activity842, the processor system810processes the transaction layer packet(s). For instance, the processor system810may decrypt the transaction layer packet(s) and/or decode the transaction layer packet(s).

In activity844, the processor system810forwards the transaction their packet(s) to the third hardware826. By forwarding the transaction layer packet(s) to the third hardware826, the processor system810may enable the third hardware826to process the transaction layer packet(s). It will be recognized that the third hardware826and the second hardware808may be the same, though the example embodiments are not limited in this respect.

In some example embodiments, one or more of the activities830,834,836,838,840,842, and/or844of the activity diagram800may not be performed. Moreover, activities in addition to or in lieu of the activities830,834,836,838,840,842, and/or844may be performed.

FIG.9depicts a flowchart900of another example method for reducing latency of changing an operating state of a processor system from a low-power state to a normal-power state in accordance with an embodiment. Flowchart900may be performed by the processor system110shown inFIG.1, for example. For illustrative purposes, flowchart900is described with respect to a processor system1000shown inFIG.10, which is another example implementation of the processor system110. As shown inFIG.10, the processor system1000includes latency reduction logic1024. The latency reduction logic1024includes a state controller1072and packet processing logic1076. Further structural and operational embodiments will be apparent to persons skilled in the relevant art(s) based on the discussion regarding flowchart900.

As shown inFIG.9, the method of flowchart900begins at step902. In step902, a transaction layer packet is received from a hardware system. The transaction layer packet is based at least in part on a network packet. The hardware system may be any suitable type of hardware system, including but not limited to a network interface controller (NIC), an accelerator, storage (e.g., memory, such as a solid-state drive (SSD)), or a graphical processing unit (GPU). In an example implementation, the state controller1072receives a transaction layer packet1020, which is based at least in part on a network packet, from the hardware system.

At step904, without taking into consideration an extent to which the processor system is utilized, a change of the operating state of the processor system from the low-power state to the normal-power state is triggered. Triggering the change of the operating state may be based at least in part on receipt of the transaction layer packet. The low-power state is configured to cause the processor system to consume a first amount of power. The normal-power state is configured to cause the processor system to consume a second amount of power that is greater than the first amount. In an example implementation, the state controller1072triggers a change of the operating state of the processor system1000from the low-power state to the normal-power state without taking into consideration an extent to which the processor system1000is utilized.

Triggering the change of the operating state of the processor system at step904may reduce latency with regard to changing the state of the processor system from the low-power state to the normal-power state. Triggering the change of the operating state of the processor system at step904may increase efficiency of the processor system and/or the computing system that includes the processor system. Triggering the change of the operating state of the processor system at step904may enable the processor system to reduce power consumption without delaying an exit from the low-power state to the normal-power state.

In an example embodiment, changing the operating state of the processor system includes increasing a frequency at which the processor system operates, increasing a voltage of a clock that is used by the processor system to perform operations, and/or switching a portion of the processor system from an off state to an on state.

In another example embodiment, triggering the change of the operating state of the processor system at step904is performed prior to decoding the transaction layer packet by the processor system.

At step906, the transaction layer packet is processed in the normal-power state. In an example implementation, the packet processing logic10776processes the transaction layer packet1020in the normal-power state.

In an example embodiment, processing the transaction layer packet at step906includes instructing the hardware system to perform a designated task based at least in part on receipt of the transaction layer packet. For example, the designated task may include processing a designated image and displaying the designated image. In another example, the designated task may include processing a designated audio file and playing the designated audio file.

In some example embodiments, one or more steps902,904, and/or906of flowchart900may not be performed. Moreover, steps in addition to or in lieu of steps902,904, and/or906may be performed.

It will be recognized that the processor system1000may not include one or more of the state controller1072and/or the packet processing logic1076. Furthermore, the processor system1000may include components in addition to or in lieu of the state controller1072and/or the packet processing logic1076.

FIG.11is a system diagram of an exemplary mobile device1100including a variety of optional hardware and software components, shown generally as1102. Any components1102in the mobile device may communicate with any other component, though not all connections are shown, for ease of illustration. The mobile device1100may be any of a variety of computing devices (e.g., cell phone, smartphone, handheld computer, Personal Digital Assistant (PDA), etc.) and may allow wireless two-way communications with one or more mobile communications networks1104, such as a cellular or satellite network, or with a local area or wide area network.

The mobile device1100may include a processor1110(e.g., signal processor, microprocessor, ASIC, or other control and processing logic circuitry) for performing such tasks as signal coding, data processing, input/output processing, power control, and/or other functions. An operating system1112may control the allocation and usage of the components1102and support for one or more applications1114(a.k.a. application programs). The applications1114may include common mobile computing applications (e.g., email applications, calendars, contact managers, web browsers, messaging applications) and any other computing applications (e.g., word processing applications, mapping applications, media player applications).

The mobile device1100may include memory1120. The memory1120may include non-removable memory1122and/or removable memory1124. The non-removable memory1122may include RAM, ROM, flash memory, a hard disk, or other well-known memory storage technologies. The removable memory1124may include flash memory or a Subscriber Identity Module (SIM) card, which is well known in GSM communication systems, or other well-known memory storage technologies, such as “smart cards.” The memory1120may store data and/or code for running the operating system1112and the applications1114. Example data may include web pages, text, images, sound files, video data, or other data sets to be sent to and/or received from one or more network servers or other devices via one or more wired or wireless networks. Memory1120may store a subscriber identifier, such as an International Mobile Subscriber Identity (IMSI), and an equipment identifier, such as an International Mobile Equipment Identifier (IMEI). Such identifiers may be transmitted to a network server to identify users and equipment.

The mobile device1100may support one or more input devices1130, such as a touch screen1132, microphone1134, camera1136, physical keyboard1138and/or trackball1140and one or more output devices1150, such as a speaker1152and a display1154. Touch screens, such as the touch screen1132, may detect input in different ways. For example, capacitive touch screens detect touch input when an object (e.g., a fingertip) distorts or interrupts an electrical current running across the surface. As another example, touch screens may use optical sensors to detect touch input when beams from the optical sensors are interrupted. Physical contact with the surface of the screen is not necessary for input to be detected by some touch screens. For example, the touch screen1132may support a finger hover detection using capacitive sensing, as is well understood in the art. Other detection techniques may be used, including but not limited to camera-based detection and ultrasonic-based detection. To implement a finger hover, a user's finger is typically within a predetermined spaced distance above the touch screen, such as between 0.1 to 0.25 inches, or between 0.25 inches and 0.5 inches, or between 0.5 inches and 0.75 inches, or between 0.75 inches and 1 inch, or between 1 inch and 1.5 inches, etc.

The mobile device1100may include latency reduction logic1192. The latency reduction logic1192is configured to reduce latency of changing an operating state of the processor1110from a low-power state to a normal-power state in accordance with any one or more of the techniques described herein. The latency reduction logic1192may be incorporated into suitable component(s)1102. For instance, the latency reduction logic1192may be incorporated partially or entirely in the processor1110, the non-removable memory1122, the operating system1112, etc.

Other possible output devices (not shown) may include piezoelectric or other haptic output devices. Some devices may serve more than one input/output function. For example, touch screen1132and display1154may be combined in a single input/output device. The input devices1130may include a Natural User Interface (NUI). An NUI is any interface technology that enables a user to interact with a device in a “natural” manner, free from artificial constraints imposed by input devices such as mice, keyboards, remote controls, and the like. Examples of NUI methods include those relying on speech recognition, touch and stylus recognition, gesture recognition both on screen and adjacent to the screen, air gestures, head and eye tracking, voice and speech, vision, touch, gestures, and machine intelligence. Other examples of a NUI include motion gesture detection using accelerometers/gyroscopes, facial recognition, 3D displays, head, eye, and gaze tracking, immersive augmented reality and virtual reality systems, all of which provide a more natural interface, as well as technologies for sensing brain activity using electric field sensing electrodes (EEG and related methods). Thus, in one specific example, the operating system1112or applications1114may include speech-recognition software as part of a voice control interface that allows a user to operate the mobile device1100via voice commands. Furthermore, the mobile device1100may include input devices and software that allows for user interaction via a user's spatial gestures, such as detecting and interpreting gestures to provide input to a gaming application.

Wireless modem(s)1170may be coupled to antenna(s) (not shown) and may support two-way communications between the processor1110and external devices, as is well understood in the art. The modem(s)1170are shown generically and may include a cellular modem1176for communicating with the mobile communication network1104and/or other radio-based modems (e.g., Bluetooth® 1174 and/or Wi-Fi1172). At least one of the wireless modem(s)1170is typically configured for communication with one or more cellular networks, such as a GSM network for data and voice communications within a single cellular network, between cellular networks, or between the mobile device and a public switched telephone network (PSTN).

The mobile device may further include at least one input/output port1180, a power supply1182, a satellite navigation system receiver1184, such as a Global Positioning System (GPS) receiver, an accelerometer1186, and/or a physical connector1190, which may be a USB port, IEEE 1394 (FireWire) port, and/or RS-232 port. The illustrated components1102are not required or all-inclusive, as any components may be deleted and other components may be added as would be recognized by one skilled in the art.

Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth herein. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed methods may be used in conjunction with other methods.

Any one or more of the latency reduction logic122, the latency reduction logic124, the latency reduction logic522, the state controller552, the packet conversion logic554, the time determination logic556, the time selection logic558, the latency reduction logic724, the state controller772, the attribute selection logic774, the packet processing logic776, the latency reduction logic1024, the state controller1072, the packet processing logic1076, activity diagram300, flowchart400, flowchart600, activity diagram800, and/or flowchart900may be implemented in hardware, software, firmware, or any combination thereof.

For example, any one or more of the latency reduction logic122, the latency reduction logic124, the latency reduction logic522, the state controller552, the packet conversion logic554, the time determination logic556, the time selection logic558, the latency reduction logic724, the state controller772, the attribute selection logic774, the packet processing logic776, the latency reduction logic1024, the state controller1072, the packet processing logic1076, activity diagram300, flowchart400, flowchart600, activity diagram800, and/or flowchart900may be implemented, at least in part, as computer program code configured to be executed in one or more processors.

In another example, any one or more of the latency reduction logic122, the latency reduction logic124, the latency reduction logic522, the state controller552, the packet conversion logic554, the time determination logic556, the time selection logic558, the latency reduction logic724, the state controller772, the attribute selection logic774, the packet processing logic776, the latency reduction logic1024, the state controller1072, the packet processing logic1076, activity diagram300, flowchart400, flowchart600, activity diagram800, and/or flowchart900may be implemented, at least in part, as hardware logic/electrical circuitry. Such hardware logic/electrical circuitry may include one or more hardware logic components. Examples of a hardware logic component include but are not limited to a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip system (SoC), a complex programmable logic device (CPLD), etc. For instance, a SoC may include an integrated circuit chip that includes one or more of a processor (e.g., a microcontroller, microprocessor, digital signal processor (DSP), etc.), memory, one or more communication interfaces, and/or further circuits and/or embedded firmware to perform its functions.

III. Further Discussion of Some Example Embodiments

(A1) An example hardware system (FIG.1,108;FIG.2,208A-208N;FIG.3,308;FIG.5,500;FIG.12,1250) to reduce latency of changing an operating state of a processor (FIG.1,110;FIG.2,210;FIG.3,310;FIG.7,700;FIG.11,1110;FIG.12,1202) from a low-power state to a normal-power state comprises a memory (FIG.11,1120;FIG.12,1204,1208,1210) and a processing system (FIG.11,1110;FIG.12,1202) coupled to the memory. The processing system is configured to, based at least in part on receipt of a network packet (FIG.1,116;FIG.5,516) via a network (FIG.1,104), prior to a transaction layer packet (FIG.1,120;FIG.5,520) that is based at least in part on the network packet being provided to the processor by the hardware system, trigger (FIG.3,332;FIG.4,404) a change of the operating state of the processor from the low-power state to the normal-power state by asynchronously providing a notification (FIG.1,118;FIG.2,218;FIG.5,518) to the processor at a first time instance. The notification indicates that the transaction layer packet is to be provided to the processor at a second time instance that temporally follows the first time instance. The low-power state is configured to cause the processor to consume a first amount of power. The normal-power state is configured to cause the processor to consume a second amount of power that is greater than the first amount. The processing system is further configured to cause (FIG.3,340;FIG.4,406) the transaction layer packet to be processed in the normal-power state by providing the transaction layer packet to the processor at the second time instance.

(A2) In the example hardware system of A1, wherein the notification indicates an amount of time between the first time instance at which the notification is asynchronously provided to the processor and the second time instance at which the transaction layer packet is to be provided to the processor.

(A3) In the example hardware system of any of A1-A2, wherein the processor system is configured to: asynchronously provide the notification to the processor prior to completion of processing of the network packet by the hardware system.

(A4) In the example hardware system of any of A1-A3, wherein the processor system is further configured to: determine an amount of time that is to be consumed to complete the processing of the network packet by the hardware system; and select the first time instance at which the notification is provided to the processor based at least in part on the amount of time.

(A5) In the example hardware system of any of A1-A4, wherein the processor system is configured to: complete the processing of the network packet to generate the transaction layer packet; and based at least in part on the processing of the network packet being completed, provide the transaction layer packet to the processor at the second time instance.

(A6) In the example hardware system of any of A1-A5, wherein the processor system is configured to: trigger the processor to increase a frequency at which the processor operates by asynchronously providing the notification to the processor at the first time instance.

(A7) In the example hardware system of any of A1-A6, wherein the processor system is configured to: trigger the processor to increase a voltage of a clock that is used to perform operations by the processor by asynchronously providing the notification to the processor at the first time instance.

(A8) In the example hardware system of any of A1-A7, wherein the processor system is configured to: trigger the processor to switch a portion of the processor from an off state to an on state by asynchronously providing the notification to the processor at the first time instance.

(A9) In the example hardware system of any of A1-A8, further comprising: a Peripheral Component Internet Express (PCIe) WAKE #pin; wherein the processor system is configured to: asynchronously provide the notification to the processor via the PCIe WAKE #pin at the first time instance.

(A10) In the example hardware system of any of A1-A9, wherein the processor system is configured to: at the first time instance, asynchronously provide the notification to the processor via a first connection that is included in a plurality of connections that connect a plurality of respective hardware systems to the processor via a Boolean OR gate.

(B1) A first example computing system (FIG.1,106;FIG.2,200;FIG.3,300;FIG.11,1102;FIG.12,1200) to reduce latency of changing an operating state of a processor system (FIG.1,110;FIG.2,210;FIG.3,310;FIG.7,700;FIG.11,1110;FIG.12,1202) from a low-power state to a normal-power state comprises a memory (FIG.11,1120;FIG.12,1204,1208,1210) and the processor system coupled to the memory. The processor system is configured to receive (FIG.3,332;FIG.6,602) a notification (FIG.1,118;FIG.2,218;FIG.5,518) from a hardware system (FIG.1,108;FIG.2,208A-208N;FIG.3,308;FIG.5,500;FIG.12,1250) at a first time instance. The notification indicates that a transaction layer packet (FIG.1,120;FIG.5,520), which is based at least in part on a network packet (FIG.1,116;FIG.5,516), is to be received by the processor system from the hardware system at a second time instance that temporally follows the first time instance. The processor system is further configured to, based at least in part on receipt of the notification, change (FIG.3,334;FIG.6,604) the operating state of the processor system from the low-power state to the normal-power state. The low-power state is configured to cause the processor system to consume a first amount of power. The normal-power state is configured to cause the processor system to consume a second amount of power that is greater than the first amount. The processor system is further configured to receive (FIG.3,340;FIG.6,606) the transaction layer packet from the hardware system at the second time instance. The processor system is further configured to process (FIG.3,342;FIG.6,608) the transaction layer packet in the normal-power state based at least in part on receipt of the transaction layer packet at the second time instance.

(B2) In the example computing system of B1, wherein the processor system is configured to: change the operating state of the processor system from the low-power state to the normal-power state before the transaction layer packet is received from the hardware system at the second time instance.

(B3) In the example computing system of any of B1-B2, wherein the notification indicates an amount of time between the first time instance at which the notification is received by the processor system from the hardware system and the second time instance at which the transaction layer packet is to be received by the processor system from the hardware system; and wherein the processor system is configured to: select an attribute of the processor system from a plurality of attributes of the processor system to be changed based at least in part on the processor system being capable of changing the attribute from a first value to a second value within the amount of time between the first time instance and the second time instance; and change the operating state of the processor system from the low-power state to the normal-power state by changing the selected attribute of the processor system from the first value to the second value.

(B4) In the example computing system of any of B1-B3, wherein the processor system is configured to: based at least in part on receipt of the notification, change the operating state of the processor system by increasing a frequency at which the processor system operates.

(B5) In the example computing system of any of B1-B4, wherein the processor system is configured to: based at least in part on receipt of the notification, change the operating state of the processor system by increasing a voltage of a clock that is used by the processor system to perform operations.

(B6) In the example computing system of any of B1-B5, wherein the processor system is configured to: based at least in part on receipt of the notification, change the operating state of the processor system by switching a portion of the processor system from an off state to an on state.

(B7) In the example computing system of any of B1-B6, wherein the processor system comprises: a Peripheral Component Internet Express (PCIe) WAKE #pin; and wherein the processor system is configured to: receive the notification from the hardware system via the PCIe WAKE #pin at the first time instance.

(B8) In the example computing system of any of B1-B7, wherein the processor system is configured to: at the first time instance, receive the notification from the hardware system via a first connection that is included in a plurality of connections that connect a plurality of respective hardware systems to the processor system via a Boolean OR gate.

(B9) In the example computing system of any of B1-B8, wherein the processor system is configured to: instruct the hardware system to perform a designated task based at least in part on receipt of the transaction layer packet.

(C1) A second example computing system (FIG.1,106;FIG.2,200;FIG.8,806;FIG.11,1102;FIG.12,1200) to reduce latency of changing an operating state of a processor system (FIG.1,110;FIG.2,210;FIG.8,810;FIG.10,1000;FIG.11,1110;FIG.12,1202) from a low-power state to a normal-power state comprises a memory (FIG.11,1120;FIG.12,1204,1208,1210) and the processor system coupled to the memory. The processor system is configured to receive (FIG.8,840;FIG.9,902) a transaction layer packet (FIG.1,120;FIG.10,1020), which is based at least in part on a network packet (FIG.1,116), from a hardware system (FIG.1,108;FIG.2,208A-208N;FIG.8,808;FIG.12,1250). The processor system is further configured to, based at least in part on receipt of the transaction layer packet and without taking into consideration an extent to which the processor system is utilized, trigger (FIG.8,834;FIG.9,904) a change of the operating state of the processor system from the low-power state to the normal-power state. The low-power state is configured to cause the processor system to consume a first amount of power. The normal-power state is configured to cause the processor system to consume a second amount of power that is greater than the first amount. The processor system is further configured to process (FIG.8,842;FIG.9,906) the transaction layer packet in the normal-power state.

(C2) In the example computing system of C1, wherein the processor system is configured to: trigger the change of the operating state of the processor system by increasing a frequency at which the processor system operates.

(C3) In the example computing system of any of C1-C2, wherein the processor system is configured to: trigger the change of the operating state of the processor system by increasing a voltage of a clock that is used by the processor system to perform operations.

(C4) In the example computing system of any of C1-C3, wherein the processor system is configured to: trigger the change of the operating state of the processor system by switching a portion of the processor system from an off state to an on state.

(C5) In the example computing system of any of C1-C4, wherein the processor system is configured to: trigger the change of the operating state of the processor system from the low-power state to the normal-power state prior to decoding the transaction layer packet by the processor system.

(C6) In the example computing system of any of C1-05, wherein the processor system is configured to: instruct the hardware system to perform a designated task based at least in part on receipt of the transaction layer packet.

(D1) A first example method of reducing latency of changing an operating state of a processor (FIG.1,110;FIG.2,210;FIG.3,310;FIG.7,700;FIG.11,1110;FIG.12,1202) from a low-power state to a normal-power state. The method is implemented by a hardware system (FIG.1,108;FIG.2,208A-208N;FIG.3,308;FIG.5,500;FIG.12,1250). The method comprises receiving (FIG.3,330;FIG.4,402) a network packet (FIG.1,116;FIG.5,516) via a network (FIG.1,104). The method further comprises, based at least in part on receipt of the network packet, prior to a transaction layer packet (FIG.1,120;FIG.5,520) that is based at least in part on the network packet being provided to the processor by the hardware system, triggering (FIG.3,332;FIG.4,404) a change of the operating state of the processor from the low-power state to the normal-power state by asynchronously providing a notification (FIG.1,118;FIG.2,218;FIG.5,518) to the processor at a first time instance. The notification indicates that the transaction layer packet is to be provided to the processor at a second time instance that temporally follows the first time instance. The low-power state is configured to cause the processor to consume a first amount of power. The normal-power state is configured to cause the processor to consume a second amount of power that is greater than the first amount. The method further comprises causing (FIG.3,340;FIG.4,406) the transaction layer packet to be processed in the normal-power state by providing the transaction layer packet to the processor at the second time instance.

(D2) In the method of D1, wherein the notification indicates an amount of time between the first time instance at which the notification is asynchronously provided to the processor and the second time instance at which the transaction layer packet is to be provided to the processor.

(D3) In the method of any of D1-D2, wherein asynchronously providing the notification to the processor comprises: asynchronously providing the notification to the processor prior to completion of processing of the network packet by the hardware system.

(D4) In the method of any of D1-D3, further comprising: determining an amount of time that is to be consumed to complete the processing of the network packet by the hardware system; and selecting the first time instance at which the notification is provided to the processor based at least in part on the amount of time.

(D5) In the method of any of D1-D4, further comprising: completing the processing of the network packet to generate the transaction layer packet; wherein the transaction layer packet is provided to the processor at the second time instance based at least in part on the processing of the network packet being completed.

(D6) In the method of any of D1-D5, wherein triggering the change of the operating state of the processor comprises: triggering the processor to increase a frequency at which the processor operates by asynchronously providing the notification to the processor at the first time instance.

(D7) In the method of any of D1-D6, wherein triggering the change of the operating state of the processor comprises: triggering the processor to increase a voltage of a clock that is used to perform operations by the processor by asynchronously providing the notification to the processor at the first time instance.

(D8) In the method of any of D1-D7, wherein triggering the change of the operating state of the processor comprises: triggering the processor to switch a portion of the processor from an off state to an on state by asynchronously providing the notification to the processor at the first time instance.

(D9) In the method of any of D1-D8, wherein triggering the change of the operating state of the processor from the low-power state to the normal-power state comprises: asynchronously providing the notification to the processor via a Peripheral Component Internet Express (PCIe) WAKE #pin of the hardware system at the first time instance.

(D10) In the method of any of D1-D9, wherein triggering the change of the operating state of the processor from the low-power state to the normal-power state comprises: at the first time instance, asynchronously providing the notification to the processor via a first connection that is included in a plurality of connections that connect a plurality of respective hardware systems to the processor via a Boolean OR gate.

(E1) A second example method of reducing latency of changing an operating state of a processor system (FIG.1,110;FIG.2,210;FIG.3,310;FIG.7,700;FIG.11,1110;FIG.12,1202) from a low-power state to a normal-power state. The method is implemented by the processor system. The method comprises receiving (FIG.3,332;FIG.6,602) a notification (FIG.1,118;FIG.2,218;FIG.5,518) from a hardware system (FIG.1,108;FIG.2,208A-208N;FIG.3,308;FIG.5,500;FIG.12,1250) at a first time instance. The notification indicates that a transaction layer packet (FIG.1,120;FIG.5,520), which is based at least in part on a network packet (FIG.1,116;FIG.5,516), is to be received by the processor system from the hardware system at a second time instance that temporally follows the first time instance. The method further comprises, based at least in part on receipt of the notification, changing (FIG.3,334;FIG.6,604) the operating state of the processor system from the low-power state to the normal-power state, wherein the low-power state is configured to cause the processor system to consume a first amount of power, wherein the normal-power state is configured to cause the processor system to consume a second amount of power that is greater than the first amount. The method further comprises receiving (FIG.3,340;FIG.6,606) the transaction layer packet from the hardware system at the second time instance. The method further comprises processing (FIG.3,342;FIG.6,608) the transaction layer packet in the normal-power state based at least in part on receipt of the transaction layer packet at the second time instance.

(E2) In the method of E1, wherein changing the operating state of the processor system comprises: changing the operating state of the processor system from the low-power state to the normal-power state before the transaction layer packet is received from the hardware system at the second time instance.

(E3) In the method of any of E1-E2, wherein the notification indicates an amount of time between the first time instance at which the notification is received by the processor system from the hardware system and the second time instance at which the transaction layer packet is to be received by the processor system from the hardware system; wherein the method further comprises: selecting an attribute of the processor system from a plurality of attributes of the processor system to be changed based at least in part on the processor system being capable of changing the attribute from a first value to a second value within the amount of time between the first time instance and the second time instance; and wherein changing the operating state of the processor system comprises: changing the operating state of the processor system from the low-power state to the normal-power state by changing the selected attribute of the processor system from the first value to the second value.

(E4) In the method of any of E1-E3, wherein changing the operating state of the processor system comprises: increasing a frequency at which the processor system operates.

(E5) In the method of any of E1-E4, wherein changing the operating state of the processor system comprises: increasing a voltage of a clock that is used by the processor system to perform operations.

(E6) In the method of any of E1-E5, wherein changing the operating state of the processor system comprises: switching a portion of the processor system from an off state to an on state.

(E7) In the method of any of E1-E6, wherein receiving the notification from the hardware system comprises: receiving the notification from the hardware system via a Peripheral Component Internet Express (PCIe) WAKE #pin of the processor system at the first time instance.

(E8) In the method of any of E1-E7, wherein receiving the notification from the hardware system comprises: at the first time instance, receiving the notification from the hardware system via a first connection that is included in a plurality of connections that connect a plurality of respective hardware systems to the processor system via a Boolean OR gate.

(E9) In the method of any of E1-E8, wherein processing the transaction layer packet comprises: instructing the hardware system to perform a designated task based at least in part on receipt of the transaction layer packet.

(F1) A third example method of reducing latency of changing an operating state of a processor system (FIG.1,110;FIG.2,210;FIG.8,810;FIG.10,1000;FIG.11,1110;FIG.12,1202) from a low-power state to a normal-power state. The method is implemented by the processor system. The method comprises receiving (FIG.8,840;FIG.9,902) a transaction layer packet (FIG.1,120;FIG.10,1020), which is based at least in part on a network packet (FIG.1,116), from a hardware system (FIG.1,108;FIG.2,208A-208N;FIG.8,808;FIG.12,1250). The method further comprises, based at least in part on receipt of the transaction layer packet and without taking into consideration an extent to which the processor system is utilized, triggering (FIG.8,834;FIG.9,904) a change of the operating state of the processor system from the low-power state to the normal-power state. The low-power state is configured to cause the processor system to consume a first amount of power. The normal-power state is configured to cause the processor system to consume a second amount of power that is greater than the first amount. The method further comprises processing (FIG.8,842;FIG.9,906) the transaction layer packet in the normal-power state.

(F2) In the method of F1, wherein triggering the change of the operating state of the processor system comprises: increasing a frequency at which the processor system operates.

(F3) In the method of any of F1-F2, wherein triggering the change of the operating state of the processor system comprises: increasing a voltage of a clock that is used by the processor system to perform operations.

(F4) In the method of any of F1-F3, wherein triggering the change of the operating state of the processor system comprises: switching a portion of the processor system from an off state to an on state.

(F5) In the method of any of F1-F4, wherein triggering the change of the operating state of the processor system comprises: triggering the change of the operating state of the processor system from the low-power state to the normal-power state prior to decoding the transaction layer packet by the processor system.

(F6) In the method of any of F1-F5, wherein processing the transaction layer packet comprises: instructing the hardware system to perform a designated task based at least in part on receipt of the transaction layer packet.

(G1) A first example computer program product (FIG.11,1124;FIG.12,1218,1222) comprising a computer-readable storage medium having instructions recorded thereon for enabling a processor-based system (FIG.1,106;FIG.2,200;FIG.8,806;FIG.11,1102;FIG.12,1200) to reduce latency of changing an operating state of a processor (FIG.1,110;FIG.2,210;FIG.3,310;FIG.7,700;FIG.11,1110;FIG.12,1202), which is included in the processor-based system, from a low-power state to a normal-power state by performing operations. The operations comprise receiving a network packet (FIG.1,116;FIG.5,516) at a hardware system (FIG.1,108;FIG.2,208A-208N;FIG.3,308;FIG.5,500;FIG.12,1250), which is included in the processor-based system, via a network (FIG.1,104). The operations further comprise, based at least in part on receipt of the network packet at the hardware system, prior to a transaction layer packet (FIG.1,120;FIG.5,520) that is based at least in part on the network packet being provided to the processor by the hardware system, triggering (FIG.3,332;FIG.4,404) a change of the operating state of the processor from the low-power state to the normal-power state by asynchronously providing a notification (FIG.1,118;FIG.2,218;FIG.5,518) to the processor at a first time instance. The notification indicates that the transaction layer packet is to be provided to the processor at a second time instance that temporally follows the first time instance. The low-power state is configured to cause the processor to consume a first amount of power. The normal-power state is configured to cause the processor to consume a second amount of power that is greater than the first amount. The operations further comprise causing (FIG.3,340;FIG.4,406) the transaction layer packet to be processed in the normal-power state by the processor by providing the transaction layer packet from the hardware system to the processor at the second time instance.

(H1) A second example computer program product (FIG.16,1618,1622) comprising a computer-readable storage medium having instructions recorded thereon for enabling a processor-based system (FIG.1,106;FIG.2,200;FIG.3,300;FIG.11,1102;FIG.12,1200) to reduce latency of changing an operating state of a processor (FIG.1,110;FIG.2,210;FIG.3,310;FIG.7,700;FIG.11,1110;FIG.12,1202), which is included in the processor-based system, from a low-power state to a normal-power state by performing operations. The operations comprise receiving (FIG.3,332;FIG.6,602) a notification (FIG.1,118;FIG.2,218;FIG.5,518) at the processor from a hardware system (FIG.1,108;FIG.2,208A-208N;FIG.3,308;FIG.5,500;FIG.12,1250) at a first time instance. The notification indicates that a transaction layer packet (FIG.1,120;FIG.5,520), which is based at least in part on a network packet (FIG.1,116;FIG.5,516), is to be received by the processor from the hardware system at a second time instance that temporally follows the first time instance. The operations further comprise, based at least in part on receipt of the notification at the processor, changing (FIG.3,334;FIG.6,604) the operating state of the processor from the low-power state to the normal-power state. The low-power state is configured to cause the processor to consume a first amount of power. The normal-power state is configured to cause the processor to consume a second amount of power that is greater than the first amount. The operations further comprise receiving (FIG.3,340;FIG.6,606) the transaction layer packet at the processor from the hardware system at the second time instance. The operations further comprise processing (FIG.3,342;FIG.6,608) the transaction layer packet in the normal-power state by the processor based at least in part on receipt of the transaction layer packet by the processor at the second time instance.

(I1) A third example computer program product (FIG.16,1618,1622) comprising a computer-readable storage medium having instructions recorded thereon for enabling a processor-based system (FIG.1,106;FIG.2,200;FIG.8,806;FIG.11,1102;FIG.12,1200) to reduce latency of changing an operating state of a processor (FIG.1,110;FIG.2,210;FIG.8,810;FIG.10,1000;FIG.11,1110;FIG.12,1202), which is included in the processor-based system, from a low-power state to a normal-power state by performing operations. The operations comprise receiving (FIG.8,840;FIG.9,902) a transaction layer packet (FIG.1,120;FIG.10,1020), which is based at least in part on a network packet (FIG.1,116), by the processor from a hardware system (FIG.1,108;FIG.2,208A-208N;FIG.8,808;FIG.12,1250). The operations further comprise, based at least in part on receipt of the transaction layer packet by the processor and without taking into consideration an extent to which the processor is utilized, triggering (FIG.8,834;FIG.9,904) a change of the operating state of the processor from the low-power state to the normal-power state. The low-power state is configured to cause the processor to consume a first amount of power. The normal-power state is configured to cause the processor to consume a second amount of power that is greater than the first amount. The operations further comprise processing (FIG.8,842;FIG.9,906) the transaction layer packet in the normal-power state by the processor.

IV. Example Computer System

FIG.12depicts an example computer1200in which embodiments may be implemented. Any one or more of the first computing device102and/or the second computing device106shown inFIG.1; the computing device200shown inFIG.2; the first computing device302and/or the second computing device306shown inFIG.3; and/or the first computing device802and/or the second computing device806shown inFIG.8may be implemented using computer1200, including one or more features of computer1200and/or alternative features. Computer1200may be a general-purpose computing device in the form of a conventional personal computer, a mobile computer, or a workstation, for example, or computer1200may be a special purpose computing device. The description of computer1200provided herein is provided for purposes of illustration, and is not intended to be limiting. Embodiments may be implemented in further types of computer systems, as would be known to persons skilled in the relevant art(s).

As shown inFIG.12, computer1200includes a processing unit1202, a system memory1204, and a bus1206that couples various system components including system memory1204to processing unit1202. Bus1206represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. System memory1204includes read only memory (ROM)1208and random access memory (RAM)1210. A basic input/output system1212(BIOS) is stored in ROM1208.

Computer1200also has one or more of the following drives: a hard disk drive1214for reading from and writing to a hard disk, a magnetic disk drive1216for reading from or writing to a removable magnetic disk1218, and an optical disk drive1220for reading from or writing to a removable optical disk1222such as a CD ROM, DVD ROM, or other optical media. Hard disk drive1214, magnetic disk drive1216, and optical disk drive1220are connected to bus1206by a hard disk drive interface1224, a magnetic disk drive interface1226, and an optical drive interface1228, respectively. The drives and their associated computer-readable storage media provide nonvolatile storage of computer-readable instructions, data structures, program modules and other data for the computer. Although a hard disk, a removable magnetic disk and a removable optical disk are described, other types of computer-readable storage media can be used to store data, such as flash memory cards, digital video disks, random access memories (RAMs), read only memories (ROM), and the like.

A number of program modules may be stored on the hard disk, magnetic disk, optical disk, ROM, or RAM. These programs include an operating system1230, one or more application programs1232, other program modules1234, and program data1236. Application programs1232or program modules1234may include, for example, computer program logic for implementing any one or more of (e.g., at least a portion of) the latency reduction logic122, the latency reduction logic124, the latency reduction logic522, the state controller552, the packet conversion logic554, the time determination logic556, the time selection logic558, the latency reduction logic724, the state controller772, the attribute selection logic774, the packet processing logic776, the latency reduction logic1024, the state controller1072, the packet processing logic1076, activity diagram300(including any activity of activity diagram300), flowchart400(including any step of flowchart400), flowchart600(including any step of flowchart600), activity diagram800(including any activity of activity diagram800), and/or flowchart900(including any step of flowchart900), as described herein.

A user may enter commands and information into the computer1200through input devices such as keyboard1238and pointing device1240. Other input devices (not shown) may include a microphone, joystick, game pad, satellite dish, scanner, touch screen, camera, accelerometer, gyroscope, or the like. These and other input devices are often connected to the processing unit1202through a serial port interface1242that is coupled to bus1206, but may be connected by other interfaces, such as a parallel port, game port, or a universal serial bus (USB).

A display device1244(e.g., a monitor) is also connected to bus1206via an interface, such as a video adapter1246. In addition to display device1244, computer1200may include other peripheral output devices (not shown) such as speakers and printers.

Computer1200is connected to a network1248(e.g., the Internet) through a network interface or adapter1250, a modem1252, or other means for establishing communications over the network. Modem1252, which may be internal or external, is connected to bus1206via serial port interface1242.

As used herein, the terms “computer program medium” and “computer-readable storage medium” are used to generally refer to media (e.g., non-transitory media) such as the hard disk associated with hard disk drive1214, removable magnetic disk1218, removable optical disk1222, as well as other media such as flash memory cards, digital video disks, random access memories (RAMs), read only memories (ROM), and the like. A computer-readable storage medium is not a signal, such as a carrier signal or a propagating signal. For instance, a computer-readable storage medium may not include a signal. Accordingly, a computer-readable storage medium does not constitute a signal per se. Such computer-readable storage media are distinguished from and non-overlapping with communication media (do not include communication media). Communication media embodies computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wireless media such as acoustic, RF, infrared and other wireless media, as well as wired media. Example embodiments are also directed to such communication media.

As noted above, computer programs and modules (including application programs1232and other program modules1234) may be stored on the hard disk, magnetic disk, optical disk, ROM, or RAM. Such computer programs may also be received via network interface1250or serial port interface1242. Such computer programs, when executed or loaded by an application, enable computer1200to implement features of embodiments discussed herein. Accordingly, such computer programs represent controllers of the computer1200.

Example embodiments are also directed to computer program products comprising software (e.g., computer-readable instructions) stored on any computer-useable medium. Such software, when executed in one or more data processing devices, causes data processing device(s) to operate as described herein. Embodiments may employ any computer-useable or computer-readable medium, known now or in the future. Examples of computer-readable mediums include, but are not limited to storage devices such as RAM, hard drives, floppy disks, CD ROMs, DVD ROMs, zip disks, tapes, magnetic storage devices, optical storage devices, MEMS-based storage devices, nanotechnology-based storage devices, and the like.

It will be recognized that the disclosed technologies are not limited to any particular computer or type of hardware. Certain details of suitable computers and hardware are well known and need not be set forth in detail in this disclosure.

V CONCLUSION

Although the subject matter has been described in language specific to structural features and/or acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as examples of implementing the claims, and other equivalent features and acts are intended to be within the scope of the claims.