Patent ID: 12245437

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms such as “first” and “second” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first”, “second”, and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

FIG.1is a flow chart illustrating a method for manufacturing a semiconductor device according to various aspects of one or more embodiments of the present disclosure. The method100begins with operation110in which a substrate is received. The method100continues with operation120in which a first conductive wiring is formed over the substrate. The method100proceeds with operation130in which at least one first dielectric layer is formed over the first conductive wiring. The method100continues with operation140in which at least one second dielectric layer is formed over the at least one first dielectric layer, wherein a dielectric constant of the at least one second dielectric layer is higher than a dielectric constant of the at least one first dielectric layer. The method100proceeds with operation150in which a second conductive wiring is formed over the at least one second dielectric layer.

The method100is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method100, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method.

FIG.2A,FIG.2BandFIG.2Care schematic views at one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. As depicted inFIG.2A, a substrate10is received. In some embodiments, the substrate10includes a semiconductor substrate. By way of example, the material of the substrate10may include elementary semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide or indium arsenide; or combinations thereof.

In some embodiments, a first low-k dielectric layer12is formed over the substrate10. In some embodiments, the first low-k dielectric layer12is a low-k dielectric or an extreme low-k (ELK) dielectric having a dielectric constant equal to or less than about 3. In some embodiments, the material of the first low-k dielectric layer12may include, but is not limited to, a carbon-doped silicon oxide such as Black Diamond, CORAL or AURORA; a mixture of organic material and silicon oxide such as HOSP; Nanoglass; aluminum fluoride; bromine fluoride; combinations thereof; or other low-k or ELK dielectric materials. In some embodiments, the thickness of the first low-k dielectric layer12is ranging from about 1000 angstroms to about 1500 angstroms, but not limited thereto.

A first conductive wiring14is formed in the first low-k dielectric layer12. In some embodiments, the first low-k dielectric layer12surrounds an edge of the first conductive wiring14, and an upper surface of the first conductive wiring14is exposed from the first low-k dielectric layer12. The first conductive wiring14is formed from conductive material such as metal or alloy. For example, the material of the first circuit layer includes copper, but not limited thereto.

As depicted inFIG.2B, at least one first dielectric layer16is formed over the first low-k dielectric layer12. The dielectric constant of the at least one first dielectric layer16is higher than the dielectric constant of the first low-k dielectric layer12. In some embodiments, the dielectric constant of the at least one first dielectric layer16is ranging from about 3.5 to about 4.5, but not limited thereto. In some embodiments, the material of the at least one first dielectric layer16may include silicon oxide, silicon carbide, zinc oxide, titanium oxide, tantalum oxide, combinations thereof or the like. In some embodiments, the thickness of the at least one first dielectric layer16is ranging from about 50 angstroms to about 600 angstroms. In some embodiments, the at least one first dielectric layer16is a single-layered structure. In some embodiments, the at least one first dielectric layer16includes a first dielectric161and a second dielectric162stacked to each other and formed from different dielectric materials. In some embodiments, the first dielectric161is configured to improve adhesion with the underlying first low-k dielectric layer12, and the second dielectric162is configured to improve adhesion with an overlying layer. In some embodiments, the thickness of the first dielectric161is ranging from about 50 angstroms to about 300 angstroms, and the thickness of the second dielectric162is ranging from about 50 angstroms to about 300 angstroms.

At least one second dielectric layer18is formed over the at least one first dielectric layer16. In some embodiments, the dielectric constant of the at least one second dielectric layer18is higher than the dielectric constant of the at least one first dielectric layer16. In some embodiments, the dielectric constant of the at least one second dielectric layer18is ranging from about 4 to about 7, but not limited thereto. In some embodiments, the material of the at least one second dielectric layer18may include silicon nitride, silicon oxynitride, aluminum oxide, asbestos, chloroform, tantalum oxide, combination thereof, or the like. In some embodiments, the at least one second dielectric layer18is a multi-layered dielectric. By way of example, the at least one second dielectric layer18may include oxide/nitride/oxide (ONO). The at least one second dielectric layer18may be single-layered or multi-layered. In some embodiments, the thickness of the at least one second dielectric layer18is ranging from about 500 angstroms to about 1000 angstroms.

In some embodiments, a conductive via19is formed in the at least one first dielectric layer16and the at least one second dielectric layer18. The conductive via19penetrates through the at least one first dielectric layer16and the at least one second dielectric layer18to electrically connect a portion of the first conductive wiring14. The conductive via19is formed from conductive material such as metal or alloy. For example, the material of the first circuit layer includes copper, but not limited thereto.

As depicted inFIG.2C, at least one third dielectric layer20is formed over the at least one second dielectric layer18. In some embodiments, the dielectric constant of the at least one third dielectric layer20is lower than the dielectric constant of the at least one second dielectric layer18. In some embodiments, the dielectric constant of the at least one third dielectric layer20is ranging from about 3.5 to about 4.5, but not limited thereto. In some embodiments, the material of the at least one third dielectric layer20may include silicon oxide, silicon carbide, zinc oxide, titanium oxide, tantalum oxide, combinations thereof or the like. In some embodiments, the thickness of the at least one third dielectric layer20is ranging from about 50 angstroms to about 600 angstroms. In some embodiments, the at least one third dielectric layer20is a single-layered structure. In some embodiments, the at least one third dielectric layer20includes a first dielectric201and a second dielectric202stacked to each other and formed from different dielectric materials. In some embodiments, the first dielectric201is configured to improve adhesion with the underlying second dielectric layer18, and the second dielectric202is configured to improve adhesion with an overlying layer. In some embodiments, the thickness of the first dielectric201is ranging from about 50 angstroms to about 300 angstroms, and the thickness of the second dielectric202is ranging from about 50 angstroms to about 300 angstroms.

In some embodiments, a second low-k dielectric layer22is formed over the at least one third dielectric layer20. The dielectric constant of the second low-k dielectric layer22is lower than the dielectric constant of the at least one third dielectric layer20. In some embodiments, the second low-k dielectric layer22is a low-k dielectric or an extreme low-k dielectric having a dielectric constant equal to or less than about 3. In some embodiments, the material of the second low-k dielectric layer22may include, but is not limited to, a carbon-doped silicon oxide such as Black Diamond, CORAL or AURORA; a mixture of organic material and silicon oxide such as HOSP; Nanoglass; aluminum fluoride; bromine fluoride; combinations thereof; or other low-k dielectric materials. In some embodiments, the thickness of the second low-k dielectric layer22is ranging from about 100 angstroms to about 900 angstroms, but not limited thereto.

In some embodiments, a second conductive wiring24is formed over the at least one second dielectric layer18. The second conductive wiring24is formed from conductive material such as metal or alloy. For example, the material of the second conductive wiring24includes copper, but not limited thereto. In some embodiments, the at least one third dielectric layer20and the second low-k dielectric layer22surround an edge of the second conductive wiring24, and an upper surface of the second conductive wiring24is exposed from the second low-k dielectric layer20. In some embodiments, a portion of the second conductive wiring24is electrically connected to the first conductive wiring14through the conductive via19.

In some embodiments, at least one fourth dielectric layer26is formed over the second low-k dielectric layer22to form a semiconductor device1. The dielectric constant of the at least one fourth dielectric layer26is lower than the dielectric constant of the second low-k dielectric layer22. In some embodiments, the dielectric constant of the at least one fourth dielectric layer26is ranging from about 3.5 to about 4.5, but not limited thereto. In some embodiments, the material of the at least one fourth dielectric layer26may include silicon oxide, silicon carbide, zinc oxide, titanium oxide, tantalum oxide, combinations thereof or the like. In some embodiments, the thickness of the at least one fourth dielectric layer26is ranging from about 50 angstroms to about 600 angstroms. In some embodiments, the at least one fourth dielectric layer26includes a first dielectric261and a second dielectric262stacked to each other and formed from different dielectric materials. In some embodiments, the first dielectric261is configured to improve adhesion with the underlying second low-k dielectric layer22, and the second dielectric262is configured to improve adhesion with an overlying layer. In some embodiments, the thickness of the first dielectric261is ranging from about 50 angstroms to about 300 angstroms, and the thickness of the second dielectric262is ranging from about 50 angstroms to about 300 angstroms.

The semiconductor device of the present disclosure is not limited to the above-mentioned embodiments, and may have other different embodiments. To simplify the description and for the convenience of comparison between each of the embodiments of the present disclosure, the identical components in each of the following embodiments are marked with identical numerals. For making it easier to compare the difference between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

FIG.3is a schematic cross-sectional view of a semiconductor device according to one or more embodiments of the present disclosure. As shown inFIG.3, different from the semiconductor device1illustrated inFIG.2C, the at least second dielectric layer18of the semiconductor device2includes a first layer181and a second layer182stacked to each other and formed from different dielectric materials. In some embodiments, the first dielectric181is configured to improve adhesion with the underlying first dielectric layer16, and the second dielectric182is configured to improve adhesion with the overlying third dielectric layer20.

FIG.4A,FIG.4B,FIG.4CandFIG.4Dare schematic views at one of various operations of manufacturing an semiconductor device according to one or more embodiments of the present disclosure. As depicted inFIG.4A, a substrate10is received. The substrate10includes a first region101and a second region102. In some embodiments, the first region101is configured to accommodate an electronic device such as a memory device, and the second region102is configured to accommodate a logic device such as a stacked conductive wiring device.

In some embodiments, a first low-k dielectric layer12is formed over the substrate10in the first region101and in the second region102. In some embodiments, the first low-k dielectric layer12is a low-k dielectric or an extreme low-k dielectric having a dielectric constant equal to or less than about 3. In some embodiments, the material of the first low-k dielectric layer12may include, but is not limited to, carbon-doped silicon oxide such as Black Diamond, CORAL or AURORA; mixture of organic material and silicon oxide such as HOSP; Nanoglass; aluminum fluoride; bromine fluoride; combinations thereof; or other low-k dielectric materials. In some embodiments, the thickness of the first low-k dielectric layer12is ranging from about 1000 angstroms to about 1500 angstroms, but not limited thereto.

In some embodiments, a first conductive structure13is formed in the first low-k dielectric layer12in the first region101and a first conductive wiring14is formed in the first low-k dielectric layer12in the second region102. In some embodiments, the first conductive structure13and the first conductive wiring14can be formed by the same conductive layer. In some embodiments, the first low-k dielectric layer12surrounds an edge of the first conductive wiring14and an edge of the first conductive structure13, and an upper surface of the first conductive wiring14and an upper surface of the first conductive structure13are exposed from the first low-k dielectric layer12.

As depicted inFIG.4B, at least one first dielectric layer16is formed over the first low-k dielectric layer12. The dielectric constant of the at least one first dielectric layer16is higher than the dielectric constant of the first low-k dielectric layer12. In some embodiments, the dielectric constant of the at least one first dielectric layer16is ranging from about 3.5 to about 4.5, but not limited thereto. In some embodiments, the material of the at least one first dielectric layer16may include silicon oxide, silicon carbide, zinc oxide, titanium oxide, tantalum oxide, combinations thereof, or the like. In some embodiments, the thickness of the at least one first dielectric layer16is ranging from about 50 angstroms to about 600 angstroms. In some embodiments, the at least one first dielectric layer16includes a first dielectric161and a second dielectric162stacked to each other and formed from different dielectric materials. In some embodiments, the first dielectric161is configured to improve adhesion with the underlying first low-k dielectric layer12, and the second dielectric162is configured to improve adhesion with an overlying layer. In some embodiments, the thickness of the first dielectric161is ranging from about 50 angstroms to about 300 angstroms, and the thickness of the second dielectric162is ranging from about 50 angstroms to about 300 angstroms.

As depicted inFIG.4C, an electronic device is formed in the first region101. In some embodiments, the electronic device includes a memory device. In some embodiments, a magnetic random access memory (MRAM) device is exemplarily illustrated as an example. A bottom electrode via32is formed in the first region101and electrically connected to the exposed first conductive structure141. A bottom electrode34is formed over the bottom electrode via32. A magnetic tunnel junction (MJT)36is formed over the bottom electrode34. A top electrode38is formed over the MJT26. In some embodiments, at least one second dielectric layer18is formed over the at least one first dielectric layer16. In some embodiments, the at least one second dielectric layer18includes a first layer181and a second layer182. In some embodiments, the first layer181is configured as a spacer layer surrounding edges of the bottom electrode34, the MJT36and the top electrode38of the MRAM device in the first region101, and extending to the second region102. In some embodiments, a top electrode via40is formed in the second layer182of the at least one second dielectric layer18of the first region101. In some embodiments, a conductive via19is formed in the at least one first dielectric layer16and the at least one second dielectric layer18of the second region102.

As depicted inFIG.4D, at least one third dielectric layer20is formed over the at least one second dielectric layer18. In some embodiments, the dielectric constant of the at least one third dielectric layer20is lower than the dielectric constant of the at least one second dielectric layer18. In some embodiments, the dielectric constant of the at least one third dielectric layer20is ranging from about 3.5 to about 4.5, but not limited thereto. In some embodiments, the material of the at least one third dielectric layer20may include silicon oxide, silicon carbide, zinc oxide, titanium oxide, tantalum oxide, combinations thereof or the like. In some embodiments, the thickness of the at least one third dielectric layer20is ranging from about 50 angstroms to about 600 angstroms. In some embodiments, the at least one third dielectric layer20includes a first dielectric201and a second dielectric202stacked to each other and formed from different dielectric materials. In some embodiments, the thickness of the first dielectric201is ranging from about 50 angstroms to about 300 angstroms, and the thickness of the second dielectric202is ranging from about 50 angstroms to about 300 angstroms.

In some embodiments, a second low-k dielectric layer22is formed over the at least one third dielectric layer20. The dielectric constant of the second low-k dielectric layer22is lower than the dielectric constant of the at least one third dielectric layer20. In some embodiments, the second low-k dielectric layer22is a low-k dielectric or an extreme low-k dielectric having a dielectric constant equal to or less than about 3. In some embodiments, the material of the second low-k dielectric layer22may include, but is not limited to, a carbon-doped silicon oxide such as Black Diamond, CORAL or AURORA; a mixture of organic material and silicon oxide such as HOSP; Nanoglass; aluminum fluoride; bromine fluoride; combinations thereof; or other low-k dielectric materials. In some embodiments, the thickness of the second low-k dielectric layer22is ranging from about 100 angstroms to about 900 angstroms, but not limited thereto.

In some embodiments, a top electrode42is formed over the at least one second dielectric layer18of the first region101, and a second conductive wiring24is formed over the at least one second dielectric layer18of the second region102. In some embodiments, the top electrode42and the second conductive wiring24can be formed by the same conductive layer. In some embodiments, the at least one third dielectric layer20and the second low-k dielectric layer22surround an edge of the top electrode42and an edge of the second conductive wiring24, and an upper surface of the top electrode42and an upper surface of the second conductive wiring24are exposed from the second low-k dielectric layer20. In some embodiments, a portion of the second conductive wiring24is electrically connected to the first conductive wiring14through the conductive via19.

In some embodiments, at least one fourth dielectric layer26is formed over the second low-k dielectric layer22to form a semiconductor device3. The dielectric constant of the at least one fourth dielectric layer26is lower than the dielectric constant of the second low-k dielectric layer22. In some embodiments, the dielectric constant of the at least one fourth dielectric layer26is ranging from about 3.5 to about 4.5, but not limited thereto. In some embodiments, the material of the at least one fourth dielectric layer26may include silicon oxide, silicon carbide, zinc oxide, titanium oxide, tantalum oxide, combinations thereof or the like. In some embodiments, the thickness of the at least one fourth dielectric layer26is ranging from about 50 angstroms to about 600 angstroms. In some embodiments, the at least one fourth dielectric layer26includes a first dielectric261and a second dielectric262stacked to each other and formed from different dielectric materials. In some embodiments, the thickness of the first dielectric261is ranging from about 50 angstroms to about 300 angstroms, and the thickness of the second dielectric262is ranging from about 50 angstroms to about 300 angstroms.

In some embodiments, the material and/or thickness of the dielectric layers such as the first dielectric layer16and the second dielectric layer18are configured to meet the capacitance requirement for a stacked conductive wiring device such as a logic device in a peripheral region. The dielectric layers such as the first dielectric layer16and the second dielectric layer18are not low-k dielectric layers, and thus can be used as dielectric for both the electronic device such as a MRAM device and a stacked conductive wiring device such as a logic device in a peripheral region. Accordingly, the operation s of forming the dielectric layers for the electronic device such as a MRAM device and a stacked conductive wiring device such as a logic device in a peripheral region can be integrated, and thus the method for manufacturing a semiconductor device can be simplified.

FIG.5is a schematic cross-sectional view of a semiconductor device according to a comparative embodiment of the present disclosure. As shown inFIG.5, the semiconductor device50of the comparative embodiment includes a first conductive wiring14, a first dielectric layer54, a second dielectric layer56, a low-k dielectric layer58and a second conductive wiring24. The dielectric constant of the low-k dielectric layer58is lower than 3, and the dielectric constant of the first dielectric layer54and the second dielectric layer56is ranging from 3.5 to 4.5. The thickness of the first dielectric layer54is between 50 angstroms and 300 angstroms, and the thickness of the second dielectric layer56is between 50 angstroms and 300 angstroms. The thickness of the low-k dielectric layer58under the second conductive wiring60i.e. the gap between the lower surface of the second conductive wiring60and the upper surface of the second dielectric layer56is between 200 angstroms and 300 angstroms.

FIG.6is an equivalent circuit diagram of a stacked conductive wiring device. As shown inFIG.6, a capacitance Cab exists between the first conductive wiring14and the second conductive wiring24in a perpendicular direction, and two capacitances Cfb exist between the first conductive wiring14and the second conductive wiring24in two oblique directions, respectively. Refer to Table 1. Table 1 shows a simulation of capacitance between the first conductive wiring and the second conductive wiring.

TABLE 1ThicknessOverallof secondcapacitancedielectric(Cab + 2*Cfb)Cfblayer (Å)(fF/um)Cab(fF/um)ab(fF/um)Comparative4.27E−021.73E−021.27E−02embodimentEmbodiments8114.28E−021.62E−021.33E−02of the present7614.47E−021.71E−021.38E−02disclosure7464.54E−021.73E−021.40E−02Offset8110.2%−6.4%4.7%7614.7%−1.2%8.7%7466.3%0.0%10.2%

From the simulation result in Table 1, the dielectric layers such as the first dielectric layer and the second dielectric layer, which are not low-k dielectric materials, are able to generate a capacitance between the first conductive wiring and the second conductive wiring similar to a low-k dielectric material. The first dielectric layer and the second dielectric layer not only can meet the capacitance requirement for a stacked conductive wiring device such as a logic device in a peripheral region, but also can be integrated with the inter-metal dielectric (IMD) in the electronic device such as a MRAM device. Accordingly, the method for manufacturing a semiconductor device can be simplified, and the planarization of the semiconductor device is improved.

In one exemplary aspect, a semiconductor device is provided. The semiconductor device includes a bottom electrode via, a top electrode via over the bottom electrode via, a memory cell between the bottom electrode via and the top electrode via, a first dielectric layer over the memory cell, and a second dielectric layer over the first dielectric layer, and a via structure separated from the memory cell. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell, and a height of the top electrode via. The first dielectric layer partially surrounds a first portion of the via structure, and the second dielectric layer partially surrounds a second portion of the via structure. A height of the second portion of the via structure is greater than a height of the first portion of the via structure.

In another aspect, a semiconductor device is provided. The semiconductor device includes a first dielectric layer, a second dielectric layer over the first dielectric layer, a bottom electrode via in the first dielectric layer, a top electrode in the second dielectric layer, a memory cell between the bottom electrode via and the top electrode via, a spacer layer, and a via structure separated from the memory cell. The spacer layer is between the memory cell and the second dielectric layer, and between the first dielectric layer and the second dielectric layer. The first dielectric layer partially surrounds a first portion of the via structure, the second dielectric layer partially surrounds a second portion of the via structure, and the third dielectric layer partially surrounds a third portion of the via structure. A height of the third portion is greater than a height of the first portion, and greater than a height of the second portion.

In yet another aspect, a semiconductor device is provided. The semiconductor device includes an adhesive layer, a first dielectric layer over the first adhesive layer, a bottom electrode via in the first adhesive layer and the first dielectric layer, a second dielectric layer over the first dielectric layer, a top electrode via in the second dielectric layer, a memory cell between the bottom electrode via and the top electrode via, a second adhesive layer between the second dielectric layer and the first dielectric layer, and a via structure in the first adhesive layer, the first dielectric layer, the second adhesive layer and the second dielectric layer. The via structure is separated from the bottom electrode via, the memory cell and the top electrode via. A height of the via structure is substantially equal to a sum of a height of the bottom electrode via, a height of the memory cell and a height of the top electrode via.

The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.