Patent ID: 12254810

DETAILED DESCRIPTION OF THE INVENTION

The following is a detailed description of various embodiments to illustrate the principles of the invention. The embodiments are provided to illustrate aspects of the invention, but the invention is not limited to any embodiment. The scope of the invention encompasses numerous alternatives, modifications, and equivalents. The scope of the invention is limited only by the claims.

While numerous specific details are set forth in the following description to provide a thorough understanding of the invention, the invention may be practiced according to the claims without some or all of these specific details.

Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes and are not intended to limit the scope of the claims.

For purposes of the detailed description of the present invention, the method of addressing a display using the present invention is referred to as “diagonal addressing”. To differentiate between the present invention and prior art, the addressing of a display not using the present invention is referred to as “standard addressing” or “Cartesian addressing”. The pixel layout and interconnection used for diagonal addressing according to the present invention is referred to as “diagonal pixel layout” in contrast to the prior art which is referred to as “standard pixel layout” or “Cartesian layout.” A standard pixel layout or Cartesian layout with respect to the pixel layout shall mean pixels are defined by substantially parallel lines forming intersecting horizontal rows and vertical columns of pixels, intersecting each other substantially at a right angle, where a pixel can be defined uniquely by its row and column position.

FIG.1shows prior art touch sensor100according to the '487 Patent comprising a plurality of conductive elements111,112,113,114,115,116,117, and118connected to connector104arranged in a diagonal pattern such that one group of conductive elements (i.e.,111,113,115, and117) follows one diagonal while another group of conductive elements (i.e.,112,114,116,118) follows another diagonal. When conductive elements111,112,113,114,115,116,117, and118reach the left side120or right side122of the touch sensor100, conductive elements111,112,113,114,115,116,117, and118bend in area102to follow the other diagonal until reaching the top124of the touch sensor100.

The conductive elements111,112,113,114,115,116,117, and118form nodes105at their intersection within central area103. The central area103is the active area of touch sensor100. The '487 Patent teaches that such layout has the advantages of less terminal connections per node and lack of “feed lines”, which are the connections running up and down the sides120and122of touch sensor100having horizontally and vertically arranged conductive elements111,112,113,114,115,116,117, and118.

The '487 Patent further teaches the need for disambiguation techniques in capacitive touch sensing and that such techniques can be used to identify one or multiple finger locations. It further teaches that, depending on a finger position, several conductive elements111,112,113,114,115,116,117, and118may respond simultaneously and with different intensity to the presence of a finger in various methods of capacitive sensing, such as self-capacitive and mutual-capacitive sensing.

While this kind of a layout is possible and advantageous for capacitive touch sensing, it is not readily applicable for driving displays as neither any form of ambiguity nor effects on other lines are acceptable for displays. Ambiguity would lead to an incorrect image representation, while effects on other lines would lead to cross talk. An electronic display cannot make use of disambiguation and hence must drive each pixel to an exact target state, without impacting the other pixels in the display.

FIG.2shows a typical pixel layout200for a prior art monochrome electronic display. Square picture element pixels201are arranged in a Cartesian grid to form rows202and columns203of square pixels201. The square pixels201are oriented parallel to the grid axes. In this illustration a square area with only ten rows202and ten columns203is shown. This may be a portion of a larger array with many more rows202and columns203. The pixel layout200as described above may further be subdivided into color sub-pixels. For example, it is common practice to subdivide a square pixel201into three vertical stripes of red, green, and blue colored sub-pixels211as illustrated inFIG.2. Pixels201can have other shapes as well or be subdivided in more than three sub-pixels211. Common to all these layouts is that pixels201are defined and addressed by substantially horizontal rows202and substantially vertical columns203.

FIG.3shows the same pixel layout200where the square pixels201are resized and rotated by forty-five degrees. This leaves holes204in the pixel layout200.

FIG.4shows a diagonal pixel arrangement210where the holes204are filled in with additional pixels205to completely fill the diagonal pixel arrangement210with as many total pixels201and205as possible. For the illustrated ten rows202by ten columns203area with one-hundred original pixels201, eighty-one additional pixels205can be fitted into the array as a result of resizing and rotating the square pixels201by forty-five degrees. In general, for N rows202and M columns203, the number of additional pixels205(Pa) is given by
Pa=(N−1)×(M−1)  (1)

In such a diagonal pixel arrangement210, two principal variations exist.FIG.5shows an alternative arrangement220of the same size pixels201and205in the same size area. However, this arrangement220can fit one less pixel than prior arrangement210. Either layout or a combination can be used, but the following descriptions of the invention shall be limited for simplicity reasons to the layout210ofFIG.4, without limiting the scope of the invention to that layout. Common to the layout inFIGS.4and5is that the additional pixels205must be electrically connected to the edge of the display. This can either be done without the benefit of this invention by adding additional rows206and additional columns207, or by using traces208and209connecting the pixels diagonally, which leads to benefits of this invention.

In the following sections for simplicity, the concept of the invention will be explained on the simplest case of a monochrome passive matrix liquid crystal display. However, the invention is in no way limited to the case of monochrome passive matrix displays. For example, the invention applies to color displays and to active matrix displays as well.

In the simplest case of a monochrome passive matrix display, the prior art array ofFIG.2can be formed by overlapping row traces300and column traces301on either side of the liquid crystal layer as shown inFIG.6, forming the pixel capacitors that activate the liquid crystal. The row traces300can be on one substrate and are connected on the left, while the column traces301are on the other substrate and are connected from the bottom. Pixels303are formed by the overlapping area of a row300and a column301. The same can be done with the diagonal layout ofFIG.4only here the electrode traces must be arranged diagonally on the panel as illustrated inFIG.7. Diagonal traces305on first substrate310are along the diagonal from lower left to upper right. Diagonal traces305on the second substrate311are along the diagonal from lower right to upper left. Where two diagonal traces305cross, a pixel312is formed by the overlap area. All diagonal traces305are connected from the bottom. All diagonal traces305on either first substrate310or second substrate311must reflect at the edges313and340and continue in the other diagonal on the opposite substrate when they reach either side of the array. This can be achieved with conductive crossover contacts314that bridge the cell gap of the display. Preferably, further conductive crossover dots315are arranged at the bottom edge325so that all traces can be connected on the same substrate.

An integrated driver circuit (not shown) attached to the bottom edge325provides both the row and column driver functionality in such a way that each driver output is capable of providing the scanning row signal and while it is not scanning it provides the data signal to the display contacts330. Further, depending on the aspect ratio of the array, each driver output provides a reference voltage or a high impedance state as it may not address any existing pixels312during a given time slot.

The layout and electrode arrangement320ofFIG.7can be used for square displays and displays with aspect ratio (horizontal dimension/vertical dimension) greater than one. This means landscape format, not portrait format assuming the contacts are on the top or bottom edge. In other words, the contacts must always be on one of the longer sides. This limitation is caused by the requirement to eliminate two pixels being addressed by the same pair of driver outputs.

Further referring toFIG.7, there are neither contacts to driver integrated circuits on the edge313and340, nor are there a multitude of parallel traces connecting row electrodes with a driver located at the top or bottom of the display. All that is required are the crossover spots and space for the perimeter seal that seals the two substrates together. In typical displays such electrical crossover is achieved by adding conductive particles (i.e., polymer spheres coated with nickel and gold) into the perimeter seal. Therefore, no additional space is required other than the space needed for the perimeter seal. This is the case for three sides of the display and hence allows the design of “frameless displays”.

FIG.7also illustrates that the number of display contacts330and hence the number of driver outputs required is twice the number of pixels312along the edge340. In this example two times ten pixels312means twenty driver outputs. For a square display with one hundred and eighty-one pixels312using standard addressing, the number of display contacts330and hence driver outputs would be two times the square root of one-hundred eighty-one, which equals twenty-seven driver outputs. In reality, the closest display would have to be not quite square with thirteen rows times fourteen columns, which equals one-hundred and eighty-two pixels312.

The new layout allows driving an almost identical number of pixels312with twenty-six percent less driver outputs. As mentioned above, display drivers are pad limited. As most outputs are arranged along the long edge of a driver, twenty-six percent less outputs means a driver that is approximately twenty-six percent shorter and hence requires approximately twenty-six percent less silicon area. It means more drivers per silicon wafer and a lower cost per driver.

The same advantage can be expressed as a gain in the number of pixels312for a given number of display contacts330. In the example of ten rows202plus ten columns203, which equals twenty display contacts330as shown inFIG.2andFIG.4, one hundred and eighty-one pixels312can be addressed respectively, an eighty-one percent (81%) gain when using the diagonal addressing scheme.

The gain in addressable pixels312for diagonal addressing compared to standard addressing increases with an increasing number of pixels312and approaches one-hundred percent (100%) asymptotically for displays with an aspect ratio of one (square displays). This gain is a function of the aspect ratio. If (Xr) and (Yr) are the number of columns and rows in standard layout, (Xd) is the number of pixels in the row that is connected to the driver, and (Yd) is the number of pixels in the first column with a pixel that is connected to a driver, then the gain (or loss) in the number of Pixels (Gpix) is given by:

Gpix=Xd*Yd+(Xd-1)*Yd-1)Xr*Yr-1(2)

FIG.8Illustrates the gain or loss (Gpix) as a function of aspect ratio (Xd/Yd) of the diagonally addressed matrix. The nearest match is used for the aspect ratio (Xr/Yr) for the closest standard arrangement. Curves are shown for (Xd=10, 50, 100, and 2000). With increasing numbers of pixels, which is equivalent to increasing (Xd) for a given aspect ratio, the curves approach a limit that is very close to the curve for (Xd=2000). Also shown inFIG.8are dash-dotted lines indicating the popular aspect ratios of (4:3) and (16:9). The highest gain approaching one-hundred percent (100%) is achieved for square displays. The pixel gain (Gpix) at (4:3) aspect ratio is about fifty percent (50%) and at (16:9) aspect ratio (Gpix) is twenty percent (20%). Once the aspect ratio exceeds two, (Gpix) becomes negligible and eventually turns into a net loss of addressable pixels. A slight loss in the number of addressable pixels may be acceptable if a “frameless display” design is a design requirement.

FIG.9shows exemplary waveforms forms501for Outputs One, Two, and Five and resulting waveforms502for the pixels formed by the overlap of traces Five and Two, as well as Five and One. The common pulse503is applied during a first time period by Output One, during a second time period by Output Two, during a fifth time period by Output Five. During all other times the outputs present either a segment voltage504with the same or opposite polarity of the common pulse depending on the desired state of the pixel, or a no-data voltage505whenever there is no crossing between the two traces in the given layout. The resulting waveform506at the overlap of traces connected to Outputs Two and Five has a high selection voltage507, which may drive a pixel into a selected state. The resulting waveform508at the overlap of traces connected to Outputs One and Five has a low selection voltage509, which may drive a pixel into a non-selected state.

If the aspect ratio exceeds two, two scan pulses or row signals can simultaneously be scanned through the display as the respective diagonals do not meet each other. While the pixel array is continuous, electrically it is as if two separate displays are being addressed simultaneously.FIG.10shows a diagonal pixel array600with an aspect ratio of (25:7=3.57). When Output One601applies the common signal, Outputs Two through Twenty-Six602are providing the data voltage for the pixels selected by the common signal on Output One601. As can be seen, Outputs Twenty-Seven604and higher603are completely independent from any pixel addressed by Output One601. Therefore, Output Twenty-Seven604can apply a common signal simultaneously with Output One601and Outputs Twenty-Eight and higher603can apply data voltages for the common signal on output604without impact on any pixels being addressed by Outputs One601and Two trough Twenty-Six. Subsequently Outputs Two and Twenty-Eight, then Three and Twenty-Nine, and so on can apply simultaneous common signals.

The time to address one frame, meaning apply one scan pulse to each output, is the number of scanned outputs times the slot time, or scan pulse duration allowed, for each output. In case of standard addressing the frame time (Ts) is a function of the slot time in standard addressing (ts) and the number of rows (Ys). In diagonal addressing the frame time (Td) is a function of the slot time in diagonal addressing (td) and either the number of outputs, which equals twice the number of pixels connected to the driver (i.e. 2*Xd) or four times the number of pixels in the first column (Yd) minus 2, whichever is smaller:
Ts=Ys*ts(3)
Td=Min[2*Xd,4*Yd−2]*td(4)

In standard addressing each pixel gets scanned once during one frame, a frame being a scan through all row driver outputs. In diagonal addressing each pixel gets scanned twice during one frame. Hence (td) can be half the duration of (ts) for the same effect on the liquid crystal medium. The resulting increase in scan time (S) using diagonal addressing compared to standard addressing is therefore:

S=TdTs=Min[2*Xd,4*Yd-2]*12⁢tsYs*ts(5)

FIG.11shows a graphical representation of function (5) for Xd=10, 50, 100, and 2000 as a function of aspect ratio (Xd/Yd) of the diagonally addressed pixel matrix. Again, the nearest match is used for the aspect ratio (Xr/Yr) for the closest standard arrangement. For square displays (i.e., aspect ratio=1) the frame time for standard addressing and diagonal addressing is the same. The relative frame time for diagonal addressing increases to one-hundred and fifty percent at an aspect ratio of two, before decreasing again to the same frame time as for standard addressing at higher aspect ratios.

Some display media such as liquid crystals in twisted nematic (TN) or super twisted nematic (STN) displays respond to the root mean square (RMS) voltage of the resulting waveform at the overlap of two traces. Due to the square function, polarity does not matter, only amplitude matters. In a standard addressing scheme, the resulting pixel waveform is made up from (N-1) time periods of segment voltage, where N is the number of rows and one time period of either a selection pulse, which is the common voltage plus the segment voltage, or a non-selection pulse, which is the common voltage minus the segment voltage. It is known to one of skill in the art that the highest possible ratio of the RMS voltages of a selected pixel divided by the RMS voltage for a non-selected pixel depends only on the number of rows (N) being addressed. This is known as the selection ratio (S) at the multiplex limit as given by:

S=Max⁢(V⁢r⁢m⁢s,selV⁢r⁢m⁢s,nsel)=[N+1N-1]12(6)

The maximum selection ratio occurs when the ratio between the common voltage and the segment voltage, called the bias ratio (B) equals the square root of the number of rows (N):

B=V⁢commonV⁢segment=N(7)

The RMS voltage of the resulting waveform of each pixel is independent of the state the other pixels are being driven to. Therefore, a liquid crystal arrangement that has a threshold RMS voltage under which it does not respond and a steep enough response to the applied RMS voltage, steeper than the ratio in function (6), can be addressed with this standard multiplex method. Because the RMS voltage of one pixel is independent of all other pixels, it is also possible to drive the display to intermediate voltage levels allowing for a gray scale.

However, in diagonal multiplex addressing, the resulting waveform at a crossover of two traces can have additional voltage levels compared to standard multiplex addressing. This is due to the fact that each pixel gets selected with a common pulse twice and because there are time periods when no pixels that is connected with the current common electrode needs to be addressed. The additional voltage levels are 0V and two times the segment voltage (Vd). The resulting RMS voltage depends on the position of the pixel in the array at a distance from the corners and on the state of other pixels in the image. The selection ratio (S) needs to be replaced with a new selection ratio (S sub d) for diagonal addressing for the worst-case position, which are the corners, and the worst-case image content as follows:

S⁢sub⁢d=Min⁢(V⁢rms⁢sel)Max⁢(V⁢rms⁢nsel)(8)

The resulting RMS voltage on a pixel in diagonal addressing can be calculated by examining the voltage levels that are possible during the individual time slots of a scan as a function of image content, position of the pixel, and number of rows N in the array. The relationship between the selection time (td) and the frame time (Td) is given in function (4). For a single scan there are two selection pulses, either with +/− select voltage (Vs) or with +/− non-select voltage (Vns). For the number of driver outputs (P=2*Xd), there will remain (P-2) time slots, at which the pixels experiences either 0V, the segment voltage +/−(Vd), or twice the segment voltage +/−(2*Vd). 0V can be the result of both outputs not addressing any physical pixels at this time or both having the same polarity of the segment voltage (Vd). The segment voltage (Vd) results from one output applying a positive or negative segment voltage, while the other is not addressing a physical pixel and puts out 0V. Twice the segment voltage results from the two outputs having opposite polarity in their segment voltage (Vd).

It is characteristic that the RMS voltage of the corner pixels in a diagonal addressing array is impacted the most by the image content of the other pixels in the array. Hence it is necessary to find the selection ratio for a diagonal array (Sd) as shown in function (8) for corner pixels. In addition to the two time slots with selection pulses, each corner pixel will also have one time slot with +/−(Vd) and several timeslots with +/−(2Vd), which can appear (0 to N-2 times), where (N) is the number of rows in the array. The balance is always time slots with 0V.

Therefore function 8 becomes:

S⁢sub⁢d=Min⁢(V⁢rms⁢sel)Max⁢(V⁢rms⁢nsel)=Vd2+2⁢(VS+Vd)2PVd2+2⁢(VS-Vd)2+(n-2)⁢(2⁢Vd)∧2P(9)

The bias ratio (B sub d) for diagonal addressing defines the relationship between (VS) and (B sub d) as follows:

B⁢sub⁢d=VSVd(10)

The selection ratio is a function of (B sub d). The maximum selection ratio is achieved at a specific value of (B sub d (n)), which is a function of the number of rows (n):

S⁢sub⁢d=Vd2+2⁢(Bd⁢Vd+Vd)2PVd2+2⁢(Bd⁢Vd-Vd)2+(n-2)⁢(2⁢Vd)2P=2⁢Bd2+4⁢Bd+32⁢Bd2-4⁢Bd+4⁢n-5(11)

FIG.12shows the dependence of the maximum selection ratio (S sub dmax) as a function of the number of rows (n) and the corresponding bias ratio (B sub d). All the values for the selection ratio are greater than one, hence this scheme can address liquid crystal configurations responding to RMS voltage levels. However, due to the fact that each pixel RMS voltage can fall within a range of values determined by the states of all the other pixels (crosstalk), this embodiment is limited to black and white displays that can be driven into saturation.

FIG.13illustrates the reason for the limitation to black and white displays. The electro-optic response curve901, which is brightness as a function of RMS voltage, remains at a constant bright level902and then transitions through the gray shades903to a constant dark level904. One of skill in the art will know that equivalent optical configurations can be chosen where the transition is from dark to bright. A voltage range905in the low voltage domain does not result in a variation of bright level902, nor does a voltage range on the high voltage domain906change the dark level904. However, a voltage range in the transition domain907will lead to a gray level range908.

FIG.14illustrates the pixel wave form on the example of a smaller (11×5) diagonal pixel array1000. Pixel1001is driven by outputs1002and1003. The resulting waveform at pixel1001is shown in the diagram1004for the overall pattern as indicated in diagonal pixel array1000. The second frame is shown for the same image and is an option to balance out any DC voltage by inverting the second frame. There is a small DC component in a single frame due to the 4V pulse1005. All other pulses cancel each other. The selection pulses1006and1007for both states of a pixel have different amplitudes to drive select and non-select states, but always have the same sequence of polarity, e.g., first positive than negative in the first frame for all pixels of the display, independent of information content. This means that diagonal addressing scheme is suitable for any display technology requiring a certain polarity of the addressing pulses, such as ferroelectric displays, electrochromic displays, redox displays, displays switching based on the electroclinic effect including ZBD displays, and electrophoretic displays, e.g., all displays where the applied voltage or electric field causes the electrooptic effect, rather than the RMS voltage as in TN/STN type displays. The only condition is that the technology must have a threshold voltage under which the applied signal does not affect the outcome of the switching. The threshold voltage range must be larger than the voltage range of the chatter1008from addressing the other pixels.

In another embodiment, this invention can also be used to control elements in a pixel circuit that allows a current to flow when a large enough pulse is applied, but not if a smaller pulse is applied. Similarly, the current may flow only in one direction or in both directions depending on polarity of the pulse. This allows addressing light emitting diode displays, such as OLED or any type of solid-state LED displays.

One example of such a display with a large threshold that responds to the polarity of the applied signal is a zero-field zenithal bistable display (ZBD). In a ZBD, the bi-stability is created by a competition of preferred liquid crystal alignments on a grating structure, which forces discontinuities, referred to as ‘defects’, in the liquid crystal director configuration that are stable, meaning anchored to a location on the surface. The type and location of these defects can be controlled via the electroclinic effect. That is, after applying a sufficiently large positive pulse the liquid crystal relaxes into one stable state, e.g., the black state, while after application of a sufficiently large negative pulse the liquid crystal relaxes into another stable state, e.g., the white state. The pixels that have to change to white can be driven with a sufficiently large pules in the first frame, which ends with a negative pulse, while pixels that need to be changed to black are driven with a sufficiently large pulse in the second frame, which ends with a positive pulse. Pixels that don't need to change are addressed with small pulses only. In other embodiments, other methods can be used to drive such a display. For example, the display can be driven all white and/or black first, then only the pixels that need to change are driven. One or several outputs ahead of the one that is being selected currently can be driven with a signal forcing all pixels that will soon be addressed into one defined state.

A display medium without an inherent threshold can still be driven with diagonal addressing if a threshold is created by an active switching element in the pixel, such as a diode like a metal-insulator-metal diode or a thin film transistor. This concept is widely applied in active matrix displays (TFT displays) where the rows are connected to the gate of the thin film transistor and the columns are connected to the source. The drain is connected to the pixel that forms a capacitor with a common electrode. In diagonal addressing, each output can be the row and the column output. Hence there are suitably two transistors in a pixel arranged such that they alternate when being addressed.

A pixel1100with first transistor1101and second transistor1103is illustrated inFIG.15. First transistor1101is arranged such that its gate1108is connected to trace A1102, while its source1110is connected to trace B1104. The second transistor1103is arranged such that its gate1112is connected to trace B1104, while its source1114is connected to trace A1102. Depending on the characteristics of the transistor there may also need to be diodes1105and1106between the gates1108and1112and the traces1102and1104. The drains of both transistors are connected to the pixel, or, in case of a current display, to the current driver circuit.

If trace A1102carries the gate signal, first transistor1101becomes conductive, and the source signal of trace B1104is applied to the pixel1100. If trace B1104carries the gate signal, second transistor1103becomes conductive, and the source signal of trace A1102is applied to the pixel1100. Such arrangement can be used for a display technology lacking a sufficient threshold, for example an electrophoretic display where charged particles will move in any applied field.

FIG.16shows an alternative approach to create a threshold in pixel1100. This is the application of thin film diode technology (TFD) to diagonal addressing. Pixel1100comprises a bidirectional diode1107, such as a metal-insulator-metal diode, connected to trace A1102, and a second bidirectional diode1108connected to trace B1104. Both bidirectional diodes1107and1108are connected to the pixel1100. The effect of such an arrangement is that only sufficiently large voltages of either polarity can pass, while smaller voltages are blocked by the bidirectional diodes1107and1108. Both bidirectional diodes1107and1108are necessary as either trace may carry the selection pulse.

In case of such an active matrix implementation of diagonal addressing, the signal lines may all be on the same substrate but on different levels separated by an insulator. The bridging from one substrate to the other at the edge of the display when reflecting into the opposite diagonal is replaced by vias through the insulating layer. The concept of reflection into the opposite diagonal remains, only without the electric contact being transferred to the other substrate.

Diagonal addressing is compatible with color displays. Rather than subdividing standard arrangement pixels into stripes of color, here color filters are suitably arranged in diagonal format as well.FIG.17shows four examples of suitable arrangements of color filters for a diagonal pixel array, which are meant as examples of embodiments, not as limiting options. R, G, and B inFIG.17stand for red, green, and blue. X stands for a 4thcolor, which for example, can be white or a second, different shade of green.

It is possible to arrange pixels in image capturing equipment in a diagonal fashion as well, but most image sources are in a standard, or Cartesian, grid arrangement. This requires scaling and mapping of the source image to a diagonal pixel grid which can be done using existing graphics computing algorithms and hardware. Independent of any such image mapping and scaling, a second mapping step is required as pixels are no longer addressed by a row and column. This mapping step is specific to the display layout and hence suitably implemented in programmable display drivers. A display layout specific look-up table or transformation function is necessary to relate a row and column address of a pixel in the source image into the two driver outputs that will address this pixel. Such a look-up table or transformation function can be added to a driver for diagonal addressing, for example, in a one-time programmable memory.FIG.18shows an example of the lookup table for the array fromFIG.7. The look-up table shows that for this display a pixel at the Cartesian location 10,8 (column 10, row 8) would be addressed with outputs 2 and 19.

As mentioned above, display drivers for diagonal addressing must have the capability for each output to assume either the row driver characteristic, the column driver characteristic, or a third state that is applied when the output is not addressing an existing pixel. The third state may be a fixed voltage, such as 0V or any other voltage, or it may be a high impedance state, causing the respective trace to float to a voltage defined by capacitive effects in the display. Such capability may be added to existing display driver designs by adding an output switch stage that can connect the physical outputs of a driver chip with either the internal row or column driver outputs and either a high impedance state or a fixed voltage. Common display drivers may either be dedicated row and dedicated column drivers or they may be integrated drivers having blocks of outputs for rows and for columns, respectively. Integrated drivers often also contain a timing controller, image memory, and other functions. For diagonal addressing, drivers would always be integrated row/column drivers and driver/controllers would suitably also incorporate the look-up function.

FIG.19shows an exemplary simplified block diagram for an integrated passive matrix liquid crystal display driver-controller1400according to the prior art. Ancillary functions such as temperature compensation and a temperature sensor are omitted. Data and commands are received by the timing controller1410via the interface1412. The timing controller1410interprets the commands and stores the image data1422in the memory1414. The timing controller1410also generates timing signals. The voltage generator1420creates the voltage levels required for the display1430including the row signal1401. Row drivers1416are essentially shift registers that apply the row signal1401to one output at a time, shifting to the next output with each clock pulse1402received from the timing controller1410. Column drivers1418receive image data1422from the timing controller1410for each output and apply the voltage levels1403from the voltage generator1420according to the image data1422for the row currently being addressed.

FIG.20illustrates an exemplary simplified block diagram for an integrated driver-controller1450, which is capable of diagonal addressing according to the present invention. Ancillary functions such as temperature compensation and a temperature sensor are omitted. Data and commands are received by the timing controller1410via the interface1412. The timing controller1410interprets the commands and stores the image data1422in the memory1414. The timing controller1410also generates timing signals. The voltage generator1420creates the voltage levels required for the display1430including the row signal1411and all necessary voltage levels for the data drivers1432, which also include a voltage level for no-data signals1409. The timing controller1410takes image data1422from the memory1414and translates it via the look-up table (LUT)1434into image data suitable for the display1430that is being addressed. Alternatively, the timing controller may apply the look up table when receiving image data and storing it in the memory in the format suitable for the diagonal display. The data drivers1432apply voltages1413to their outputs according to the image content, and voltage1409if no pixel is being addressed by the respective output. The data driver1432outputs are connected to the display1430via the output switch1436, which can assume at least two states for each output. The output switch1436comprises a shift register that connects one output at a time to the row signal1411and shifts that output to a neighbor with every pulse of the clock signal1407. All other outputs that are not actively driving a row signal are connected with the respective data driver outputs. Optionally, the output switch1436may also set the respective IC outputs to high impedance whenever the data drivers apply no-data voltage1414.

FIG.21shows one exemplary embodiment of an output switch1500which can be used as output switch1436inFIG.20with multiple channels1510and chip outputs1530. Each chip output1530is connected with a switching element1501, which is controlled by shift register1502. Optionally, comparators1503may be added to compare the data driver outputs1540with the no-data signal. Switch1501can assume at least two positions, Position A1514and Position C1516, and optionally a third Position B1518, which is not connected to anything and hence allows the chip output to float. The presence of a bit1515in the corresponding shift register element1512causes switch1501to assume Position A1514, thereby connecting the chip output1530with the row signal. Absence of a bit1515causes switch1501to assume Position C1516that connects the chip output1530with the data driver output1540providing the image dependent signal. Optionally, comparator1503may compare the data driver output1540with the no-data signal and if the levels are the same, the comparator output1515may cause the switch1501to assume the high impedance Position B1518.

FIG.22shows an exemplary display system1600with diagonal addressing. The electronic display1602of the display system1600is surrounded by a frame1601that is very narrow on three sides due to the lack of feeder lines running up and down the sides of the display system1600. The electronic display1602is formed by pixels1603that have a higher count than the pixel count of a comparable Cartesian display with the same number of driver outputs. The pixels1603are formed by or connected with substantially diagonal electrodes1604and1605, which are formed on substrates1609and1610. The electrodes1604and1605connect only on the bottom edge1630of the electronic display1602to a driver chip1607and reflect when reaching either side of the electronic display1602to continue in the opposite diagonal and on the opposite substrate. Electric connection between electrodes1604and1605on either substrate is bridged by conductive particles in perimeter seal1606. In various embodiments, electronic display1602can comprise a passive matrix display, an active matrix display, an emissive display, a transmissive display, a partially reflective display, an electrophoretic display a liquid crystal display, or a zenithal bi-stable display.

Driver chip1607is a driver chip capable of diagonal addressing, e.g., having functions as described inFIGS.20and21. Substrates1609and1610may have additional active elements such as transistors or diodes, and other layers as required by the display medium1606. Between substrates1609and1610and enclosed by perimeter seal1606is a display medium1614, which fulfills the requirements for diagonal addressing. Display medium1614may be a liquid crystal, an electrophoretic medium, a light emitting medium, or other similar medium. On the outside of the substrates are further layers1611and1612, which improve optical performance of the display system1600. Such layer may for example be polarizers and reflectors. The connections to the driver1607are on the larger substrate1610. The driver chip is connected to the display system electronics1613via a flexible circuit1608.

FIG.23shows electronic display with a display driver integrated circuit addressing method2300. Starting at step2310, a display driver integrated circuit comprising a plurality of driver outputs is provided, and an electronic display is provided comprising an image area of a plurality of pixels and a plurality of electrodes connected to the plurality of pixels and the plurality of driver outputs. Then, at step2320, a common signal is applied to one of the plurality of electrodes using one of the plurality of driver outputs while applying a data signal to each one of the other plurality of electrodes using one or more of the remaining plurality of driver outputs. At step2330, the common signal is re-applied at least once per update of the image area to one of the plurality of electrodes using one of the plurality of driver outputs until each one of the plurality of pixels of the image area have been addressed.

In one embodiment, the plurality of electrodes provided in step2310are a plurality of diagonally arranged electrodes. In other embodiments, the electronic display provided in step2310can be a passive matrix display, an active matrix display, a zenithal bi-stable display, or an electrophoretic display.

While the invention has been specifically described in connection with certain specific embodiments thereof, it is to be understood that this is by way of illustration and not of limitation. Reasonable variations and modifications are possible within the scope of the foregoing disclosure and drawings without departing from the spirit of the invention.