Patent ID: 12205998

DETAILED DESCRIPTION

In the following description, many thicknesses and materials are described for various layers and structures within a semiconductor device. Specific dimensions and materials are given by way of example for various embodiments. Those of skill in the art will recognize, in light of the present disclosure, that other dimensions and materials can be used in many cases without departing from the scope of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present description. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”

The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.

Reference throughout this specification to “some embodiments” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least some embodiments. Thus, the appearances of the phrases “in some embodiments”, “in an embodiment”, or “in some embodiments” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

Embodiments of the present disclosure provide a semiconductor device having improved performance due at least in part to a reduced electrical resistance through source/drain regions. In some embodiments, the semiconductor device includes one or more nanostructure transistors having a plurality of semiconductor nanostructures arranged in a stack overlying a substrate. The nanostructures act as channel regions of the nanostructure transistor. Each nanostructure transistor includes source/drain regions in contact with the nanostructures. A silicide is formed on the source/drain regions and may wrap around or contact at least three surfaces (e.g., an upper and opposite side surfaces) of the source/drain regions. Source/drain contacts are disposed in contact with the silicide. The silicide extends along the side surfaces of the source/drain regions and on an intermediate surface of one or more hybrid fin structures. A portion of the source/drain contact extends downward along side surfaces of the silicide and contacts the intermediate surface of the hybrid fin structures. As such, there is a relatively small distance between each nanostructure and the silicide.

Due to the presence of the wrap around silicide, the electrical resistance between the lowest nanostructures and the silicide is greatly reduced with respect to configurations in which the silicide is formed only at the top of the source/drain regions, resulting in reduced power consumption. Moreover, a large number of nanostructures can be formed without negatively impacting the electrical resistance between lower nanostructures and the silicide. With larger numbers of nanostructures, currents can be conducted through nanostructure transistors without generating excessive amounts of heat. Accordingly, a semiconductor device in accordance with principles of the present disclosure consumes less power and generates less heat. The reduction in heat can also prevent damage to the semiconductor device from overheating. Thus, principles of the present disclosure provide substantial benefits to transistor function and overall semiconductor device function.

FIG.1Ais a cross-sectional view illustrating a semiconductor device100andFIG.1Bis a cross-sectional view of the semiconductor device100taken along the cut line B ofFIG.1A, in accordance with some embodiments. The semiconductor device100includes a semiconductor substrate102. The semiconductor device also includes first and second transistors104a,104bon the semiconductor substrate102. As set forth in more detail below, the semiconductor device100utilizes a silicide layer that wraps around the source/drain regions to improve the performance of the transistors104a,104b.

Each of the transistors104a,104bincludes a respective stack of semiconductor nanostructures106, a gate electrode108, and source/drain regions110. A silicide172is in contact with the source/drain regions110. Source/drain contacts114are in contact with the silicide172. The semiconductor nanostructures106act as channel regions of the transistors104a,104b. The transistors104a,104bcan be operated by applying voltages to the gate electrodes108and the source/drain contacts114in order to enable or prevent current flowing through the semiconductor nanostructures106between the source/drain regions110.

The semiconductor nanostructures106each extend between the neighboring source/drain regions110. The semiconductor nanostructures106can include a monocrystalline semiconductor material such as silicon, silicon germanium, or other semiconductor materials. The semiconductor nanostructures106may be an intrinsic semiconductor material or may be a doped semiconductor material. The semiconductor nanostructures may include nanosheets, nanowires, or other types of nanostructures.

The gate electrode108includes one or more conductive materials. The gate electrode108can include one or more of tungsten, aluminum, titanium, tantalum, copper, gold, or other conductive materials. In some embodiments, the gate electrode108surrounds (e.g., surrounds at least four sides) the nanostructures106such that each semiconductor nanostructure106extends through the gate electrode108between the source/drain regions110. A gate dielectric surrounds the nanostructures106and acts as a dielectric sheath between the nanostructures106and the gate electrode108. Accordingly, the transistor104may be considered a gate all around nanostructure transistor. While examples illustrated herein primarily utilized gate all around transistors, other types of transistors can be utilized without departing from the scope of the present disclosure.

As shown inFIG.1A, the gate dielectric may include an interfacial dielectric layer165and a high-K gate dielectric layer166positioned on the interfacial dielectric layer165.

Each of the transistors104a,104bincludes source/drain regions110in contact with opposite sides of the semiconductor nanostructures106. The source/drain can include semiconductor material such as silicon or silicon germanium doped with N-type dopants species or P-type dopant species depending on the type of the transistors104a,104b.

As shown inFIG.1A, the transistors104a,104binclude inner spacers154at lateral sides of each of the semiconductor nanostructures106. The inner spacers154are dielectric regions that physically and electrically separate the gate electrode108from the source/drain regions110. The inner spacers154can include silicon nitride, SiCN, SiOCN, or other suitable dielectric materials.

As shown inFIG.1B, a hybrid fin structure133is disposed between adjacent source/drain regions110along the Y-axis direction. As such, the source/drain regions110are adjacent to the semiconductor nanostructures106along a first direction (e.g., the X-axis direction), and the hybrid fin structure133is disposed adjacent to the source/drain regions110along a second direction (e.g., the Y-axis direction) that is transverse to the first direction. The hybrid fin structures133include a first dielectric layer134and a second dielectric layer136. In some embodiments, the first dielectric layer134is formed of a dielectric material, which may be a low-K dielectric material. In some embodiments, the first dielectric layer134may include silicon nitride. In some embodiments, the first dielectric layer134is formed of a dielectric material, which may include silicon oxide. The first dielectric layer134may be formed on and in contact with the shallow trench isolation regions130.

As shown inFIG.1B, the hybrid fin structures133may have a “L” shape or backward “L” shape which is formed by a recess in the first and second dielectric layers134,136. For example, as shown, each of the first and second dielectric layers134,136may have a top surface (which may be covered by a dielectric layer158) and an intermediate surface203that is substantially parallel to the top surface and which is covered by and contacted by the source/drain contacts114. In some embodiments, the intermediate surface203may be at a level that is substantially equal to or less than half of the height of the source/drain regions110. The source/drain contacts114extend into the recessed region or portion of the hybrid structures113and cover the intermediate surface203of the hybrid fin structures113.

The silicide172acts as an interface between the semiconductor material of the source/drain region110, and the metal or conductive material of the source/drain contacts114. The silicide172is formed on top of the source/drain regions110and on side surfaces of the source/drain regions110, between the side surfaces of the source/drain regions110and the source/drain contacts114. In some embodiments, the silicide172may be a “wrap around” silicide that covers and contacts at least the top surface and two side surfaces of each of the source/drain regions110. This increases a contact area between the silicide172and the source/drain regions110.

The silicide172may include any suitable silicide. In some embodiments, the silicide172includes one or more of titanium silicide, cobalt silicide, ruthenium silicide, aluminum silicide, nickel silicide, or other silicides.

The contact between the wrap around silicide172and the source/drain regions110reduces a contact resistance along a current path through the source/drain regions110to the semiconductor nanostructures106, as the relatively high resistance source/drain material is substantially surrounded (e.g., along at least three sides in some embodiments) by the highly conductive silicide172.

In some embodiments, the silicide172has a thickness (e.g., along the X-axis direction) between 1 nm and 10 nm. In some embodiments, the silicide172has a thickness (e.g., along the X-axis direction) between 3 nm and 10 nm. The silicide172can have other dimensions and shapes without departing from the scope of the present disclosure.

In some embodiments, the silicide172may include both the semiconductor material of the source/drain region110and a metal. In some embodiments, the silicide172includes one or more of titanium silicide, cobalt silicide, ruthenium silicide, aluminum silicide, nickel silicide, or other silicides. The silicide172is highly conductive compared to the source/drain regions106.

The source/drain contacts114may be metal plugs or conductive vias through which voltages are applied to the source/drain regions110. The source/drain contacts114can include tungsten, aluminum, titanium, copper, or other suitable conductive materials. The source/drain contacts114are positioned above the source/drain regions110. The source/drain contacts114are in direct contact with the silicide172, for example, at an upper surface of the silicide172. Accordingly, the source/drain contacts114apply voltages to the source/drain regions110via the silicide172. Similarly, currents flow between the source/drain contacts114and the source/drain regions110via the silicide172.

The semiconductor nanostructures106are arranged in a vertical stack above the substrate102. A vertically lowest nanostructure106corresponds to the semiconductor nanostructure106closest to the substrate102. A vertically highest nanostructure106is closest to the source/drain contacts114.

As shown inFIG.1B, in some embodiments a lateral distance201between a recessed side surface204of the second dielectric layer136of the hybrid fin structures133and a lateral side surface of the corresponding underlying shallow trench isolation region130may be less than 100 nm. In some embodiments, the lateral distance201may be less than 50 nm. In some embodiments, the lateral distance201may be greater than 10 nm. In some embodiments, the lateral distance201is within a range from about 10 nm to 100 nm, which may advantageously provide good electrical contact between the source/drain contacts114and side surfaces of the silicide172which cover corresponding side surfaces of the source/drain regions110.

As shown inFIG.1B, in some embodiments a lateral distance202between an outer surface of the second first dielectric layer134and a recessed lateral side surface204of the second dielectric layer136of the hybrid fin structures133may be less than 100 nm. In some embodiments, the lateral distance202may be less than 50 nm. In some embodiments, the lateral distance202may be less than 10 nm. In some embodiments, the lateral distance202is within a range from about 5 nm to 10 nm, which may advantageously provide sufficient width of the hybrid fin structures133in a recessed region of the hybrid fin structures in which the source/drain contacts114extend and contact side surfaces of the silicide172.

Moreover, as shown inFIG.1B, since the silicide172extends into a recessed region at which the hybrid fin structures133are laterally recessed, a lateral width of the transistors (e.g., along the X-axis direction) may be reduced. That is, additional space is not provided for the silicide172, since the silicide172may be disposed within the recessed portion of the hybrid fin structures133. Indeed, as shown inFIGS.1B and2X, a portion of the sides of the source/drain regions110contact lower side surface portions of the first dielectric layer134of the hybrid fin structures133. As such, the hybrid fin structures133are not entirely spaced laterally apart from the source/drain regions110in order to accommodate the silicide172, but instead, the silicide172may be disposed in the recessed portion of the hybrid fin structures133.

Current that flows through the bottom semiconductor nanostructure106has a longer path than current that flows to the top semiconductor nanostructure106. In a situation in which the silicide172does not extend downward along the lateral side surfaces of the source/drain regions110, then current that flows through the bottom semiconductor nanostructure106will take a relatively long path through the source/drain regions110. The source/drain regions110are not as conductive as the silicide172. Accordingly, a longer path through the source/drain regions106corresponds to a larger electrical resistance, greater power dissipation, and greater heat generation. However, the transistors104a,104bofFIGS.1A and1Binclude silicide172that extends downward along the lateral side surfaces of the source/drain regions110. The result is that there is a relatively small distance between the lowest semiconductor nanostructures106and the silicide172. Because the silicide172is highly conductive compared to the source/drain regions110, current that flows through the lowest nanostructures106will primarily flow through the path of least resistance downward through the silicide172and then laterally through the source/drain regions110to the lowest nanostructures106. This reduces the overall resistance, power dissipation, and heat generation in comparison to a situation in which the silicide172is positioned only and the top surfaces of the source/drain regions110.

FIGS.1A and1Billustrate four semiconductor nanostructures106in each of the transistors104a,104b. However, the configuration of the silicide172enables the use of more semiconductor nanostructures106without undue electrical resistance and corresponding power dissipation and heat generation. Accordingly, the transistors104a,104bcan include larger numbers of semiconductor nanostructures106than shown inFIGS.1A and1B. However, the transistors104a,104bcan include fewer or more semiconductor nanostructures106than shown without departing from the scope of the present disclosure.

FIGS.2A-3Dare cross-sectional views of an semiconductor device100at various stages of processing, according to some embodiments.FIGS.2A-3Dillustrate an exemplary process for producing an semiconductor device that includes nanostructure transistors.FIGS.2A-3Dillustrate how these transistors can be formed in a simple and effective process in accordance with principles of the present disclosure. Other process steps and combinations of process steps can be utilized without departing from the scope of the present disclosure. The nanostructure transistors can include gate all around transistors, multi-bridge transistors, nanosheet transistors, nanowire transistors, or other types of nanostructure transistors.

The nanostructure transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructure structure.

FIGS.2A-2Xalso each include axes that indicate the orientation of the cross-sectional view of that figure. The axes include lateral axes X and Y, and vertical axis Z. All axes are mutually orthogonal with each other. Figures in which the X-axis extends from right to left will be referred to as “X-Views.” Figures in which the Y-axis goes from right to left will be referred to as “Y-Views.”

As shown inFIG.2A, the semiconductor device100includes a semiconductor substrate102. In some embodiments, the substrate102includes a single crystalline semiconductor layer on at least a surface portion. The substrate102may include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In the example process described herein, the substrate102includes Si, though other semiconductor materials can be utilized without departing from the scope of the present disclosure.

The substrate102may include in its surface region, one or more buffer layers (not shown). The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. The substrate102may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants may be, for example, boron (BF2) for an n-type transistor and phosphorus for a p-type transistor.

The semiconductor device100includes a plurality of semiconductor layers116, which may form the semiconductor nanostructures106. The semiconductor nanostructures106are layers of semiconductor material. The semiconductor layers116are formed over the substrate102. The semiconductor layers116may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some embodiments, the semiconductor layers116are formed of the same semiconductor material as the substrate102. Other semiconductor materials can be utilized for the semiconductor layers116without departing from the scope of the present disclosure. In a primary non-limiting example described herein, the semiconductor layers116and the substrate102are silicon.

Sacrificial semiconductor layers118are disposed between the semiconductor layers116. The sacrificial semiconductor layers118include a different semiconductor material than the semiconductor layers116. In an example in which the semiconductor layers116include silicon, the sacrificial semiconductor layers118may include SiGe. In one example, the silicon germanium sacrificial semiconductor layers118may include between 20% and 30% germanium, though other concentrations of germanium can be utilized without departing from the scope of the present disclosure. The concentration of germanium in the silicon germanium sacrificial semiconductor layers118is selected to be different than the concentration of germanium in a subsequently formed SiGe sacrificial cladding. The compositions of the sacrificial semiconductor layers118and the sacrificial cladding are selected to result in different etching characteristics. The purpose and benefits of this will be described in further detail below.

In some embodiments, the semiconductor layers116and the sacrificial semiconductor layers118are sequentially and alternately formed, for example, by alternating epitaxial growth processes on the semiconductor substrate102. For example, a first epitaxial growth process may result in the formation of the lowest sacrificial semiconductor layer118on the top surface of the substrate102. A second epitaxial growth process may result in the formation of the lowest semiconductor layer116on the top surface of the lowest sacrificial semiconductor layer118. A third epitaxial growth process results in the formation of the second lowest sacrificial semiconductor layer118on top of the lowest semiconductor layer116. Alternating epitaxial growth processes may be performed until a selected number of semiconductor layers116and sacrificial semiconductor layers118have been formed.

A layer120is formed on top of the uppermost semiconductor layer116. In some embodiments, the layer120can be a same semiconductor material as the sacrificial semiconductor layers118. Alternatively, the layer120can include a dielectric material or other types of materials. In the example semiconductor device100illustrated inFIG.2A, four semiconductor layers116are included. However, in various embodiments, the semiconductor device100may include more or fewer semiconductor layers116. In some embodiments, the semiconductor device100may include only a single semiconductor layer116that is spaced apart from the substrate102by a single sacrificial semiconductor layer118.

In some embodiments, the vertical thickness of the semiconductor layers116may be between 2 nm and 15 nm. In some embodiments, the thickness of the sacrificial semiconductor layers118may be between 5 nm and 15 nm. Other thicknesses and materials can be utilized for the semiconductor layers116and the sacrificial semiconductor layers118without departing from the scope of the present disclosure.

In some embodiments, the sacrificial semiconductor layers118correspond to a first sacrificial epitaxial semiconductor region having a first semiconductor composition. In subsequent steps, the sacrificial semiconductor layers118will be removed and replaced with other materials and structures. For this reason, the layers118are described as sacrificial. As will be described further below, the semiconductor layers116will be patterned to form the semiconductor nanostructures106of transistors104.

As shown inFIG.2B, trenches126are formed and extend through the sacrificial semiconductor layers118, the semiconductor layers116, and at least partially into the substrate102. The trenches126define fin structures124, each of which includes a respective stack of semiconductor layers116and sacrificial semiconductor layers118. WhileFIG.2Billustrates formation of two fin structures124, it will be readily appreciated that in various embodiments, more or fewer than two fin structures may be formed in the semiconductor device100.

The trenches126may be formed utilizing any suitable technique. In some embodiments, the trenches126may be formed by depositing a hard mask layer on the layer120. In some embodiments, the layer120may itself be a hard mask layer, and in other embodiments a hard mask layer may be formed over the layer120and may be patterned and etched using standard photolithography processes. After the hard mask layer has been patterned and etched, portions of the sacrificial semiconductor layers118, the semiconductor layers116, and the substrate102that are not covered by the hard mask layer are selectively removed, for example, by an etching process. The etching process results in formation of the trenches126. The etching process can include a single etching step. Alternatively, the etching process can include multiple etching steps. For example, a first etching step can etch the top sacrificial semiconductor layer118. A second etching step can etch the top semiconductor layer116. These alternating etching steps may be repeated until all of the sacrificial semiconductor layers118and semiconductor layers116are etched at the exposed regions. A final etching step may etch at least partially into the substrate102.

As shown inFIG.2C, shallow trench isolation regions130may be formed in the trenches126. In some embodiments, an upper surface of the shallow trench isolation regions130is disposed below a level of the lowest sacrificial semiconductor layer118or below a level of an upper surface of the substrate102. The shallow trench isolation regions130may be formed of any suitable technique. For example, in some embodiments, the shallow trench isolation regions130are formed by depositing a dielectric material in the trenches126and by recessing the deposited dielectric material so that a top surface of the dielectric material is lower than the lowest sacrificial semiconductor layer118.

The shallow trench isolation regions130can be utilized to separate individual transistors or groups of transistors groups of transistors formed in conjunction with the semiconductor substrate102. The dielectric material for the shallow trench isolation regions130may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma enhanced-CVD or flowable CVD. Other materials and structures can be utilized for the shallow trench isolation regions130without departing from the scope of the present disclosure.

As shown inFIG.2D, a cladding layer132may be formed on side surfaces of the fin structures124. For example, the cladding layer132may be deposited on the on the sides of the semiconductor layers116and the sacrificial semiconductor layers118and on the layer120. In some embodiments, the cladding layer132can be formed by an epitaxial growth from one or more of the semiconductor layers116, the sacrificial semiconductor layers118, and the layer120. Alternatively, the cladding layer132can be deposited by a chemical vapor deposition (CVD) process. Other processes can be utilized for depositing the cladding layer132without departing from the scope of the present disclosure.

In some embodiments, the cladding layer132includes SiGe. In particular, the cladding layer132may include SiGe with a different concentration of germanium than the sacrificial semiconductor layers118. The cladding layer132can include other concentrations, materials, or compositions without departing from the scope of the present disclosure.

As shown inFIG.2E, hybrid fin structures133are formed in the gaps between the cladding layers132. The hybrid fin structures133include a first dielectric layer134and a second dielectric layer136.

In some embodiments, the first dielectric layer134is formed of a dielectric material, which may be a low-K dielectric material. In some embodiments, the first dielectric layer134may include silicon nitride. In some embodiments, the first dielectric layer134is formed of a dielectric material, which may include silicon oxide. The first dielectric layer134can be deposited on the shallow trench isolation130and on side surfaces of the cladding layers132.

The second dielectric layer136can be deposited on the first dielectric layer134in the trenches filling the remaining space between the fins124. The first dielectric layer134and the second dielectric layer136can be deposited by any suitable technique, including CVD, atomic layer deposition (ALD), or by other suitable deposition processes. After deposition of the first and second dielectric layers134and136, the hybrid fin structures133may be planarized by a chemical mechanical planarization (CMP) process. Other materials and deposition processes can be utilized to form the hybrid fin structures133without departing from the scope of the present disclosure.

As shown inFIG.2F, the hybrid fin structures133are recessed. For example, an etching process may be performed to recess the top surface of the hybrid fin structures133. In some embodiments, a timed etch may be performed to reduce the top surface of the hybrid fin structures133to a level that is substantially equal to or lower than the bottom of the layer120. The etching process can include a wet etch, dry etch, or any suitable etch for recessing the hybrid fin structures133to a selected depth.

InFIG.2F, a high-K dielectric layer138has been deposited on the hybrid fin structures133. The high-K dielectric layer138can include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The high-K dielectric layer138may be formed by CVD, ALD, or any suitable method. A planarization process, such as a CMP process, may be performed to planarize the top surface of the high-K dielectric layer138. The high-K dielectric layer138may be termed a helmet layer for the hybrid fin structures133. Other processes and materials can be utilized for the high-K dielectric layer138without departing from the scope of the present disclosure.

As shown inFIG.2G, portions of the layer120and to recess the cladding layer132are selectively removed. For example, in some embodiments, an etching process may be performed to remove the layer120and to recess the cladding layer132. The etching process can be performed in one or more steps. The one or more steps selectively etch the layer120and the materials of the cladding layer132with respect to the material of the high-K dielectric layer138. Accordingly, inFIG.2G, the high-K dielectric layer138remains protruding above substantially unchanged while other layers have been recessed or removed. The one or more etching steps can include wet etches, dry etches, timed etches, or other types of etching processes.

As shown inFIG.2H, a thin dielectric layer140has been deposited on the top surface of the cladding layer132, the top semiconductor layer116, and on the high-K dielectric layer138. In some embodiments, the thin dielectric layer140may have a thickness between 1 nm and 5 nm. The thin dielectric layer140may be formed of any dielectric material, and in some embodiments, the thin dielectric layer140may include silicon oxide. Other materials, deposition processes, and thicknesses can be utilized for the thin dielectric layer140without departing from the scope of the present disclosure.

InFIG.2H, a polysilicon layer142has been deposited on the dielectric layer140. The polysilicon layer142may have a thickness between 20 nm and 100 nm. The polysilicon layer142may be formed by any suitable technique, including by an epitaxial growth, a CVD process, a physical vapor deposition (PVD) process, or an ALD process. Other thicknesses and deposition processes can be used for depositing the polysilicon layer142without departing from the scope of the present disclosure.

InFIG.2H, a dielectric layer144has been formed, e.g., by deposition, on the polysilicon layer142. A dielectric layer146has been formed on the dielectric layer144. In one example, the dielectric layer144includes silicon nitride. In one example, the dielectric layer146includes silicon oxide. The dielectric layers144and146can be deposited by CVD in some embodiments, although any suitable technique for forming the dielectric layers144,146may be utilized in various embodiments. The dielectric layer144can have a thickness between 5 nm and 15 nm in some embodiments. The dielectric layer146can have a thickness between 15 nm and 50 nm in some embodiments. Other thicknesses, materials, and deposition processes can be utilized for the dielectric layers144and146without departing from the scope of the present disclosure.

The dielectric layers144and146may be patterned and etched to form a mask for the polysilicon layer142. The dielectric layers144and146can be patterned and etched using standard photolithography processes. After the dielectric layers144and146have been patterned and etched to form the mask, the polysilicon layer142is etched so that only the polysilicon directly below the dielectric layers144and146remains. The resulting structure is a polysilicon fin.

FIG.2Iis a cross-sectional view of the semiconductor device100taken along cut line I shown inFIG.2H. InFIGS.2A-2Hthe X-axis is the lateral axis going left to right on the drawing sheet, while the Y-axis goes in and out of the sheet. InFIGS.2J through2L, the Y-axis is the lateral axis going left to right on the sheet, while the X-axis goes in and out of the sheet.

As shown inFIG.2I, the layers146,144,142, and140have been patterned and etched to form dummy gate structures147. Formation of the dummy gate structures147can be accomplished using standard photolithography processes including forming a photoresist mask in the desired pattern of the dummy gate structures147and then performing an etching process in the presence of the mask. The photolithography process can also include formation of a hard mask.

As shown inFIG.2J, a gate spacer layer148has been deposited on the top surfaces of the top semiconductor layer116, as well as on the sides thin dielectric layer140, the polysilicon layer142, and the dielectric layers144and146. In one example, the gate spacer layer148includes SiCON. The gate spacer layer148can be deposited by CVD, PVD, or ALD. Other materials and deposition processes can be utilized for the gate spacer layer148without departing from the scope of the present disclosure.

As shown inFIG.2K, recesses150are formed extending through the semiconductor layers116, the sacrificial semiconductor layers118, and at least partially into the substrate102. The recesses150may be formed by any suitable technique, including by selectively removing portions of the semiconductor layers116, the sacrificial semiconductor layers118, and the substrate102. In some embodiments, the recesses150may be formed by etching the semiconductor layers116, the sacrificial semiconductor layers118, and the substrate102using the dummy gate structures147as a mask. The formation of recesses150concurrently forms or defines the semiconductor nanostructures106from the remaining portions of the semiconductor layers116. Similarly, sacrificial semiconductor nanostructures151are formed or defined by the remaining portions of the sacrificial semiconductor layers118.

Each dummy gate structure147corresponds to a position at which a transistor104will be formed. More particularly, gate electrodes108will eventually be formed in place of the dummy gate structures147and the sacrificial semiconductor nanostructures151. Each stack of semiconductor nanostructures106will correspond to the channel regions of a respective transistor104.FIG.2Killustrates the locations of two transistors104. The two transistors104will share a common source/drain region110as will be set forth in further detail below.

As shown inFIG.2L, lateral portions of the sacrificial semiconductor nanostructures151are removed and replaced with inner spacers154. The lateral portions of the sacrificial semiconductor nanostructures151may be removed by any suitable technique, including, for example, by an etching process to laterally recess the sacrificial semiconductor nanostructures151with respect to the semiconductor nanostructures106. The etching process can be performed by a chemical bath that selectively etches the sacrificial semiconductor nanostructures151with respect to the semiconductor nanostructures106. The etching process is timed so that the sacrificial semiconductor nanostructures151are recessed but not entirely removed. The recessing process is utilized to enable the formation of an inner spacer layer between the semiconductor nanostructures106at the locations where the sacrificial semiconductor nanostructures151have been recessed.

The inner spacers154are formed by any suitable technique (e.g., by deposition) at the sides of the semiconductor nanostructures106. The inner spacers154can be deposited by an ALD process, a CVD process, or other suitable processes. In one example, the inner spacers154includes silicon nitride.

FIG.2Mis a Y-view of the semiconductor device100, andFIG.2Nis an X-view of the semiconductor device100taken along the cut line N ofFIG.2M.

As shown inFIG.2Msource/drain regions110have been formed. The source/drain regions110include semiconductor material. In some embodiments, the source/drain regions110may be grown epitaxially from the semiconductor nanostructures106. The source/drain regions110can be epitaxially grown from the semiconductor nanostructures106and from the substrate102. The source/drain regions110can be doped with N-type dopants species in the case of N-type transistors, and can be doped with P-type dopant species in the case of P-type transistors. The doping can be performed in-situ during the epitaxial growth. In some embodiments, the source/drain regions110may have a thickness between 2 nm and 10 nm. The source/drain regions110may be in direct contact with the semiconductor nanostructures106.

As shown inFIG.2N, the source/drain regions110extend between adjacent hybrid fin structures133. In some embodiments, the source/drain regions110may have a top surface that extends to a level that is higher than a level of an upper surface of the hybrid fin structures133. As shown, the high-K dielectric layer138may remain on the hybrid fin structures133during formation of the source/drain regions110.

FIG.2Ois a Y-view of the semiconductor device100, andFIG.2Pis an X-view of the semiconductor device100taken along the cut line P ofFIG.2O. As shown inFIG.2P, the high-K dielectric layer138is removed. The high-K dielectric layer138may be removed by any suitable process, which in some embodiments may include by an etching process. After removal of the high-K dielectric layer138, upper surfaces of the hybrid fin structures133are exposed. For example, upper surfaces of the first and second dielectric layers134,136may be exposed by the removal of the high-K dielectric layer138.

FIG.2Qis a Y-view of the semiconductor device100, andFIG.2Ris an X-view of the semiconductor device100taken along the cut line R ofFIG.2Q.

As shown inFIG.2Q, a dielectric layer158has been deposited on sidewalls of the gate spacer layers148and on top of the source/drain regions110. The dielectric layer158can include silicon nitride or another suitable material and can be deposited by ALD, CVD, or PVD. A dielectric layer160has been deposited on the dielectric layer158. The dielectric layer160can include silicon oxide or another suitable material and can be deposited by ALD, CVD, or PVD. Other materials and deposition processes can be utilized for the dielectric layers158and160without departing from the scope of the present disclosure.

As shown inFIG.2P, the dielectric layers158and160are deposited on the hybrid fin structures133.

In some embodiments, the semiconductor device100may be planarized, for example by CMP, resulting in a planarized upper surface. The planarization may remove the dielectric layers144and146, and may remove corresponding portions of the gate spacer layer148. The planarization may expose an upper surface of the polysilicon layer142. In some embodiments, upper surfaces of the dielectric layers158and160, the gate spacer layer148, and the polysilicon layer142may be substantially coplanar with one another.

FIG.2Sis a Y-view of the semiconductor device100, andFIG.2Tis an X-view of the semiconductor device100taken along the cut line T ofFIG.2S.

As shown inFIG.2S, a metal gate135is formed, and the metal gate135includes a gate electrode108and a gate dielectric layer166. Further, as shown inFIG.2S, the dummy gates147have been removed. The dummy gates147may be removed by any suitable technique, and in some embodiments, the dummy gates147may be removed by one or more etching steps. The etching steps may include etching steps to remove the dielectric layer146, then the dielectric layer144, then the polysilicon layer142, then the dielectric layer140. Various other processes can be performed to remove the dummy gate structures147without departing from the scope of the present disclosure.

As shown inFIG.2S, the sacrificial semiconductor nanostructures151have been removed. The sacrificial semiconductor nanostructures151can be removed after removal of the dummy gates147. The sacrificial semiconductor nanostructures151can be removed with an etching process that selectively etches the sacrificial semiconductor nanostructures151with respect to the semiconductor nanostructures106and the inner spacers154. Various other processes can be utilized to remove the sacrificial semiconductor nanostructures151without departing from the scope of the present disclosure.

As shown inFIG.2S, an interfacial dielectric layer165is formed on exposed surfaces of the semiconductor nanostructures106. The interfacial dielectric layer165may be formed by any suitable technique, including, for example, by a deposition process.

The interfacial dielectric layer165may include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interfacial dielectric layer165may include a comparatively low-K dielectric with respect to high-K dielectric such as hafnium oxide or other high-K dielectric materials that may be used in gate dielectrics of transistors.

The interfacial dielectric layer165may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. In some embodiments, the interfacial dielectric layer165may have a thickness between 0.5 nm and 2 nm. One consideration in selecting a thickness for the interfacial dielectric layer is to leave sufficient space between the nanosheets106for gate metals, as will be explained in more detail below. Other materials, deposition processes, and thicknesses can be utilized for the interfacial dielectric layer without departing from the scope of the present disclosure.

As shown inFIG.2S, a gate dielectric is formed. The gate dielectric may include the interfacial dielectric layer165and a high-K gate dielectric layer166positioned on the interfacial dielectric layer165. Together, the interfacial dielectric layer165and the high-K gate dielectric layer166form a gate dielectric for the gate all around nanosheet transistors.

The high-K gate dielectric layer166and the interfacial dielectric layer165physically separate the semiconductor nanostructures106from the gate metals that will be deposited in subsequent steps. The high-K gate dielectric layer166and the interfacial dielectric layer165isolate the gate metals from the semiconductor nanostructures106that correspond to the channel regions of the transistors.

The high-K gate dielectric layer166may include one or more layers of a dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The high-K gate dielectric layer166may be formed by CVD, ALD, or any suitable method. In some embodiments, the high-K gate dielectric layer166is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each semiconductor nanosheet106. In some embodiments, the thickness of the high-k dielectric166is in a range from about 1 nm to about 3 nm. Other thicknesses, deposition processes, and materials can be utilized for the high-K gate dielectric layer166without departing from the scope of the present disclosure. The high-K gate dielectric layer166may include a first layer that includes HfO2with dipole doping including La and Mg, and a second layer including a higher-K ZrO layer with crystallization.

After forming the gate dielectric by, for example, deposition of the high-K gate dielectric layer166, the gate electrode108is formed, for example, by depositing a gate metal in the voids formed by removal of the dummy gate structures147. The gate electrode108surrounds the semiconductor nanostructures106. In particular, the gate electrode108is in contact with the gate dielectric, e.g., with the high-K gate dielectric layer166. The gate electrode108is positioned between semiconductor nanostructures106. In other words, the gate electrode108is positioned all around the semiconductor nanostructures106. For this reason, the transistors formed in relation to the semiconductor nanostructures106are called gate all around transistors.

Although the gate electrode108is shown as a single metal layer, in practice the gate electrode108may include multiple metal layers. For example, the gate electrode108may include one or more very thin work function layers in contact with the gate dielectric. The thin work function layers can include titanium nitride, tantalum nitride, or other conductive materials suitable for providing a selected work function for the transistors. The gate electrode108can further include a gate fill material that corresponds to the majority of the gate electrode108. The gate fill material can include cobalt, tungsten, aluminum, or other suitable conductive materials. The layers of the gate electrode108can be deposited by PVD, ALD, CVD, or other suitable deposition processes.

In some embodiments, one or more conductive layers may be formed on the gate electrodes108. For example, a metal layer (not shown) may be formed (e.g., by deposition) on the gate electrodes108. The metal layer can include tungsten, aluminum, titanium, copper, gold, tantalum, or other suitable conductive materials. The metal layer can be deposited by ALD, PVD, or CVD. Other materials and deposition processes can be utilized for the metal layer. In some embodiments, a cap layer (not shown) may be formed on the metal layer, for example, by deposition. The cap layer can include one or more of SiCN, SiN, or SICON. The cap layer can be deposited by CVD, ALD, or other suitable processes.

FIG.2Uis a Y-view of the semiconductor device100, andFIG.2Vis an X-view of the semiconductor device100taken along the cut line V ofFIG.2U.

As shown inFIGS.2U and2V, portions of the dielectric layer160, the dielectric layer158, the first dielectric layer134, and the second dielectric layer136are removed. The layers may be removed by any suitable process. For example, in some embodiments, an etching process may be performed to remove the portions of the dielectric layer160, the dielectric layer158, the first dielectric layer134, and the second dielectric layer136. The etching process can be performed in one or more steps. The one or more steps selectively etch the portions of the dielectric layer160, the dielectric layer158, the first dielectric layer134, and the second dielectric layer136with respect to the material of the source/drain regions110. Accordingly, as shown inFIG.2V, portions of the source/drain regions110remain protruding substantially unchanged while corresponding lateral portions of the first and second dielectric layers134,136have been removed. The one or more etching steps can include wet etches, dry etches, timed etches, or other types of etching processes.

Gaps171are formed between the side surfaces of the first dielectric layer134of the hybrid fin structures133and side surfaces of the source/drain regions110, as shown inFIG.2V. In some embodiments, the gaps171may extend along the side surfaces of the source/drain regions110to a level that is deeper than at least one-half of the height of the source/drain regions110. For example, as shown inFIG.2V, the source/drain regions110may have side surfaces that are exposed by the gaps171for at least one-half of the height of the source/drain regions110.

Upper surfaces of the source/drain regions110may be exposed by the removal of the portions of the dielectric layer160, the dielectric layer158, the first dielectric layer134, and the second dielectric layer136, as shown.

FIG.2Wis a Y-view of the semiconductor device100, andFIG.2Xis an X-view of the semiconductor device100taken along the cut line X ofFIG.2W.

As shown inFIGS.2W and2X, a silicide172has been formed on the source/drain regions110. The silicide172is formed on top of the source/drain regions110and on side surfaces of the source/drain regions110in the gaps171. The silicide172extends over top surfaces of the source/drain regions110and extends along the side surfaces of the source/drain regions110. In some embodiments, the silicide172may be a “wrap around” silicide that covers and contacts at least the top surface and two side surfaces of each of the source/drain regions110. This increases a contact area between the silicide172and the source/drain regions110. In some embodiments, the silicide172contacts an upper surface of the first dielectric layer134in the gaps171.

The silicide172can include any suitable silicide. In some embodiments, the silicide172includes one or more of titanium silicide, cobalt silicide, ruthenium silicide, aluminum silicide, nickel silicide, or other silicides. The silicide172may be formed using any suitable technique. In some embodiments, the silicide172can be grown by performing a high-temperature annealing process in the presence of the metal and the silicon from which the silicide172is formed. The result of the silicide growth process is that silicide172grows from all exposed surfaces of the source/drain regions110. The silicide172can include other materials and deposition processes without departing from the scope of the present disclosure.

The contact between the wrap around silicide172and the source/drain regions110reduces a contact resistance along a current path through the source/drain regions110to the semiconductor nanostructures106, as the relatively high resistance source/drain material is substantially surrounded (e.g., along at least three sides in some embodiments) by the highly conductive silicide172. Further details regarding the benefits of the silicide172will be discussed below.

In some embodiments, the silicide172has a thickness (e.g., along the X-axis direction) between 1 nm and 10 nm. In some embodiments, the silicide172has a thickness (e.g., along the X-axis direction) between 3 nm and 10 nm. The silicide172can have other dimensions and shapes without departing from the scope of the present disclosure.

As shown inFIGS.2W and2X, source/drain contacts114have been formed on the silicide172. The source/drain contacts114can include conductive material such as tungsten, cobalt, copper, titanium, aluminum, or other suitable conductive materials by which voltages can be applied to the source/drain regions110. The source/drain contacts114can be formed by PVD, CVD, ALD, or other suitable deposition processes. Other materials and deposition processes can be utilized for the source/drain contacts114without departing from the scope of the present disclosure.

As shown inFIG.2X, the source/drain contacts114may substantially fill the gaps171and may extend laterally between a side surface of the silicide172(e.g., which is on a side surface of the source/drain region110) and a side surface of the second dielectric layer136that is formed by the removal of portions of the second dielectric layer136. In some embodiments, the source/drain contacts114may contact a surface (e.g., a recessed upper surface) of the first and second dielectric layers134,136at a level that is below a level of the upper surface of the source/drain region110, as shown.

The semiconductor device100shown inFIGS.2W and2Xillustrate the transistors104a,104bafter processing of the transistors104a,104bis complete. As such,FIGS.2W and2Xcorrespond withFIGS.1A and1B. The first transistor104aincludes the semiconductor nanostructures106and the gate electrode108on the left side. The second transistor104bincludes the semiconductor nanostructures106and the gate electrode108on the right side. The first and second transistors104aand104bshare a central source/drain region110. The source/drain region110on the left is a source/drain region110of the transistor104a. The source/drain region110on the right is a source/drain region110of the transistor104b.

The gate all around transistors104a,104bfunction by applying biasing voltages to the gate electrode108and to the source and drain contacts114. The biasing voltages cause a channel current to flow through the semiconductor nanostructures106between the source/drain regions110. Accordingly, the semiconductor nanostructures106correspond to channel regions of the gate all around transistors104a,104b.

The formation of the wrap around silicide172results in various benefits. In one example, when a transistor104a,104bis enabled, current flows from a source/drain contact114through the silicide172, through the source/drain region110and into the semiconductor nanostructures106.

Current that flows through the bottom semiconductor nanostructure106has a longer path than current that flows through the top semiconductor nanostructure106. In a situation in which the silicide172does not extend downward along the lateral side surfaces of the source/drain regions110, then current that flows through the bottom semiconductor nanostructure106will take a relatively long path through the source/drain regions110. The source/drain regions110are not as conductive as the silicide172. Accordingly, a longer path through the source/drain regions106corresponds to a larger electrical resistance, greater power dissipation, and greater heat generation. However, the transistors104a,104bofFIGS.1A and1Binclude silicide172that extends downward along the lateral side surfaces of the source/drain regions110. The result is that there is a relatively small distance between the lowest semiconductor nanostructures106and the silicide172. Because the silicide172is highly conductive compared to the source/drain regions110, current that flows through the lowest nanostructures106will primarily flow through the path of least resistance downward through the silicide172and then laterally through the source/drain regions110to the lowest nanostructures106. This reduces the overall resistance, power dissipation, and heat generation in comparison to a situation in which the silicide172is positioned only and the top surfaces of the source/drain regions110.

Moreover, since the silicide172extends into a recessed region at which the hybrid fin structures133are laterally recessed, a lateral width of the transistors (e.g., along the X-axis direction) may be reduced. That is, additional space is not provided for the silicide172, since the silicide172may be disposed within the recessed portion of the hybrid fin structures133. Indeed, as shown inFIGS.1B and2X, a portion of the sides of the source/drain regions110contact lower side surface portions of the first dielectric layer134of the hybrid fin structures133. As such, the hybrid fin structures133are not entirely spaced laterally apart from the source/drain regions110in order to accommodate the silicide172, but instead, the silicide172may be disposed in the recessed portion of the hybrid fin structures133.

Embodiments of the present disclosure provide a semiconductor device having improved performance due at least in part to a reduced electrical resistance through source/drain regions. In some embodiments, the semiconductor device includes one or more nanostructure transistors having a plurality of semiconductor nanostructures arranged in a stack overlying a substrate. The nanostructures act as channel regions of the nanostructure transistor. Each nanostructure transistor includes source/drain regions in contact with the nanostructures. A silicide is formed on the source/drain regions and may wrap around or contact at least three surfaces (e.g., an upper and opposite side surfaces) of the source/drain regions. The silicide contacts an intermediate or recessed surface of a dielectric fin structure that is disposed adjacent to and in contact with the source/drain regions. Source/drain contacts are disposed in contact with the silicide and with the intermediate surface of the dielectric fin structure. As such, there is a relatively small distance between each nanostructure and the silicide.

Due to the presence of the wrap around silicide, the electrical resistance between the lowest nanostructures and the silicide is greatly reduced with respect to configurations in which the silicide is formed only at the top of the source/drain regions, resulting in reduced power consumption. Moreover, a large number of nanostructures can be formed without negatively impacting the electrical resistance between lower nanostructures and the silicide. With larger numbers of nanostructures, currents can be conducted through nanostructure transistors without generating excessive amounts of heat. Accordingly, a semiconductor device in accordance with principles of the present disclosure consumes less power and generates less heat. The reduction in heat can also prevent damage to the semiconductor device from overheating. Thus, principles of the present disclosure provide substantial benefits to transistor function and overall semiconductor device function.

In one or more embodiments, a device includes a substrate and a first channel region of a first transistor overlying the substrate. A source/drain region is adjacent to the first channel region along a first direction and is disposed in contact with the first channel region. The source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

In one or more embodiments, a method includes forming a first channel region of a first transistor. A source/drain region is formed in contact with the first channel region, and the source/drain region is adjacent to the first channel region along a first direction. A dielectric fin structure is formed adjacent to the source/drain region along a second direction that is transverse to the first direction. The dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is formed on a top surface of the source/drain region, a side surface of the source/drain region, and the intermediate surface of the dielectric fin structure.

In one or more embodiments, a device includes a substrate and a first transistor on the substrate. The first transistor includes a plurality of first semiconductor nanostructures corresponding to a channel region of the first transistor. A second transistor is disposed on the substrate, and the second transistor includes a plurality of second semiconductor nanostructures corresponding to a channel region of the second transistor. A source/drain region is in contact with the plurality of first semiconductor nanostructures and the plurality of second semiconductor nanostructures along a first direction. A first dielectric fin structure and a second dielectric fin structure are disposed adjacent to opposite sides of the source/drain region along a second direction that is transverse to the first direction. Each of the first and second dielectric fin structures includes a respective upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is on a top surface and side surfaces of the source/drain region, and the silicide layer is disposed on the intermediate surfaces of each of the first and second dielectric fin structures.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.