Patent ID: 12228962

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

The present disclosure will be described with respect to preferred embodiments in a specific context, namely a clock signal skew calibration apparatus for reducing clock skews of 4-phase clock signals. The disclosure may also be applied, however, to a clock signal skew calibration apparatus for reducing clock skews of multi-phase clock signals. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

FIG.1illustrates a block diagram of a clock signal skew calibration circuit in accordance with various embodiments of the present disclosure. As shown inFIG.1, the clock skew calibration circuit120is configured to be coupled to a multi-phase clock generator110through a plurality of delay lines111,112,113and114.

The multi-phase clock generator110is configured to generate a plurality of multi-phase clock signals. In some embodiments, the multi-phase clock generator110is configured to generate 4-phase clock signals, namely a 0-degree clock signal PHO, a 90-degree clock signal PH90, a 180-degree clock signal PH180and a 270-degree clock signal PH270as shown inFIG.1. PHO, PH90, PH180and PH270generated by the multi-phase clock generator110are four-phase clock signals having their phases mutually separated by 90 degrees respectively.

In some embodiments, PHO, PH90, PH180and PH270are 4-phase clock signals having a frequency of 5 GHz. The 4-phase clock signals PHO, PH90, PH180and PH270are used for 20 Gbps (billions of bits per second) data-transfer applications. The detailed implementation of the multi-phase clock generator110will be described below with respect toFIG.2.

As shown inFIG.1, a first delay line111is configured to receive the 0-degree clock signal PHO and a predetermined reference signal Vref1. Based on the predetermined reference signal Vref1, the first delay line111adds a predetermined delay into the 0-degree clock signal. As shown inFIG.1, PH0D is generated by the first delay line111.

In some embodiments, the 0-degree clock signal PH0D is a reference clock signal of the 4-phase clock signals. As such, in the skew calibration process, the delay added into PHO is not adjusted. The skews of other clock signals (e.g., the 180-degree clock signal) are determined with reference to the reference clock signal PH0D. The skews of other clock signals can be reduced through adjusting the delays added into respective clock signals.

As shown inFIG.1, a second delay line112is configured to receive the 180-degree clock signal PH180and a first control signal VC1. VC1is generated by the clock skew calibration circuit120. VC1is used to determine the delay added into the 180-degree clock signal PH180. Through adjusting the delay added into the 180-degree clock signal, the skew of the 180-degree clock signal is reduced accordingly. As shown inFIG.1, the second delay line112receives PH180and generates PH180D through adding an initial delay. Both PH180and PH180D are the 180-degree clock signals having a delay between them. During the calibration process of the 180-degree clock signal, the initial delay is adjusted to become a first delay determined by the first control signal VC1. Once the initial delay has been changed to the first delay, PH180C is generated at the output of the second delay line112. PH180C is a calibrated 180-degree clock signal. In other words, the phase difference between the reference clock signal PH0D and PH180C is 180 degrees.

As shown inFIG.1, a third delay line113is configured to receive the 90-degree clock signal PH90and a second control signal VC2. VC2is generated by the clock skew calibration circuit120. VC2is used to determine the delay added into the 90-degree clock signal PH90. Through adjusting the delay added into the 90-degree clock signal, the skew of the 90-degree clock signal is reduced accordingly. As shown inFIG.1, the third delay line113receives PH90and generates PH90D through adding an initial delay. Both PH90and PH90D are the 90-degree clock signals having a delay between them. During the calibration process of the 90-degree clock signal, the initial delay is adjusted to become a second delay determined by the second control signal VC2. Once the initial delay has been changed to the second delay, PH90C is generated at the output of the third delay line113. PH90C is a calibrated 90-degree clock signal. In other words, the phase difference between the reference clock signal PH0D and PH90C is 90 degrees.

As shown inFIG.1, a fourth delay line114is configured to receive the 270-degree clock signal PH270and a third control signal VC3. VC3is generated by the clock skew calibration circuit120. VC3is used to determine the delay added into the 270-degree clock signal PH270. Through adjusting the delay added into the 270-degree clock signal, the skew of the 270-degree clock signal is reduced accordingly. As shown inFIG.1, the fourth delay line114receives PH270and generates PH270D through adding an initial delay. Both PH270and PH270D are the 270-degree clock signals having a delay between them. During the calibration process of the 270-degree clock signal, the initial delay is adjusted to become a third delay determined by the third control signal VC3. Once the initial delay has been changed to the third delay, PH270C is generated at the output of the fourth delay line114. PH270C is a calibrated 270-degree clock signal. In other words, the phase difference between the reference clock signal PH0D and PH270C is 270 degrees.

The clock skew calibration circuit120comprises a PH180calibration unit121, a PH90calibration unit122and a PH270calibration unit123. Throughout the description, the PH180calibration unit121is alternatively referred to as a first clock skew calibration unit121. The PH90calibration unit122is alternatively referred to as a second clock skew calibration unit122. The PH270calibration unit123is alternatively referred to as a third clock skew calibration unit123.

In some embodiments, the first clock skew calibration unit121comprises a frequency doubler, a frequency divider and a delay line control circuit. The detailed structure of the first clock skew calibration unit121will be described below with respect toFIG.4.

In operation, the first clock skew calibration unit121and the second delay line112form a closed loop control system. This closed loop control system determines the first control signal VC1based on the skew of the 180-degree clock signal, and adjust the delay added into the 180-degree clock signal to reduce or eliminate the skew of the 180-degree clock signal. As a result, the skew of the 180-degree clock signal is calibrated.

In operation, the first clock skew calibration unit121is configured to receive a plurality of multi-phase clock signals including PH0D, PH90D, PH180D and PH270D as shown inFIG.1. Based on the plurality of multi-phase clock signals PH0D, PH90D, PH180D and PH270D, the frequency doubler generates a clock signal. The frequency divider is configured to receive the clock signal and generate a reduced frequency signal based on the clock signal. The reduced frequency signal having a duty cycle indicating a skew of a first multi-phase clock signal (e.g., the 180-degree clock signal). The delay line control circuit is configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate the first control signal VC1. The first control signal VC1is employed to adjust a first delay applied to the first multi-phase clock signal (e.g., the 180-degree clock signal) until a calibrated signal of the first multi-phase clock signal is achieved. Once the skew calibration process finishes, PH180C generated by the second delay line112is the calibrated signal of the 180-degree clock signal.

In some embodiments, the second clock skew calibration unit122comprises a first logic gate, a second logic gate and a first comparator. The detailed structure of the second clock skew calibration unit122will be described below with respect toFIG.10.

In operation, the second clock skew calibration unit122and the third delay line113form a closed loop control system. This closed loop control system determines the second control signal VC2based on the skew of the 90-degree clock signal, and adjust the delay added into the 90-degree clock signal to reduce or eliminate the skew of the 90-degree clock signal. As a result, the skew of the 90-degree clock signal is calibrated.

In operation, the second clock skew calibration unit122is configured to receive PH0D, PH90D and PH180C. In some embodiments, PH0D is a reference multi-phase clock signal. PH180C is the calibrated signal of the first multi-phase clock signal. PH90D is a second multi-phase clock signal.

The first logic gate is configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal (PH180C) and the second multi-phase clock signal (PH90D). The second logic gate configured to perform a second AND operation on the reference multi-phase clock signal (PH0D) and the second multi-phase clock signal (PH90D). The first comparator is configured to compare an output of the first logic gate with an output of the second logic gate, and generate the second control signal VC2. The second control signal VC2is employed to adjust a second delay applied to the second multi-phase clock signal (the 90-degree clock signal) until a calibrated signal of the second multi-phase clock signal is achieved. Once the skew calibration process finishes, PH90C generated by the third delay line113is the calibrated signal of the 90-degree clock signal.

In some embodiments, the third clock skew calibration unit123comprises a third logic gate, a fourth logic gate and a second comparator. The detailed structure of the second clock skew calibration unit123will be described below with respect toFIG.12.

In operation, the third clock skew calibration unit123and the fourth delay line114form a closed loop control system. This closed loop control system determines the third control signal VC3based on the skew of the 270-degree clock signal, and adjust the delay added into the 270-degree clock signal to reduce or eliminate the skew of the 270-degree clock signal. As a result, the skew of the 270-degree clock signal is calibrated.

In operation, the third clock skew calibration unit123is configured to receive PH0D, PH180C and PH270D. In some embodiments, PH0D is a reference multi-phase clock signal. PH180C is the calibrated signal of the first multi-phase clock signal. PH270D is a third multi-phase clock signal.

The third logic gate is configured to perform a third AND operation on the calibrated signal of the first multi-phase clock signal (PH180C) and the third multi-phase clock signal (PH270D). The fourth logic gate configured to perform a fourth AND operation on the reference multi-phase clock signal (PH0D) and the third multi-phase clock signal (PH270D). The second comparator is configured to compare an output of the first logic gate with an output of the second logic gate, and generate the third control signal VC3. The third control signal VC3is employed to adjust a third delay applied to the third multi-phase clock signal (the 270-degree clock signal) until a calibrated signal of the third multi-phase clock signal is achieved. Once the skew calibration process finishes, PH270C generated by the fourth delay line114is the calibrated signal of the 270-degree clock signal.

FIG.2illustrates a schematic diagram of the multi-phase clock generator shown inFIG.1in accordance with various embodiments of the present disclosure. In some embodiments, the multi-phase clock generator110is implemented as a 4-phase clock generator as shown inFIG.2. The multi-phase clock generator110comprises a first oscillator211, a second oscillator212, a third oscillator213and a fourth oscillator214connected in cascade.

As shown inFIG.2, an inverting output of the first oscillator211is connected to a non-inverting input of the second oscillator212. The inverting output of the first oscillator211is configured to generate the 270-degree clock signal PH270. A non-inverting output of the first oscillator211is connected to an inverting input of the second oscillator212. An inverting output of the second oscillator212is connected to a non-inverting input of the third oscillator213. The inverting output of the second oscillator212is configured to generate the 180-degree clock signal PH180. A non-inverting output of the second oscillator212is connected to an inverting input of the third oscillator213.

An inverting output of the third oscillator213is connected to a non-inverting input of the fourth oscillator214. The inverting output of the third oscillator213is configured to generate the 90-degree clock signal PH90. A non-inverting output of the third oscillator213is connected to an inverting input of the fourth oscillator214. An inverting output of the fourth oscillator214is connected to a non-inverting input of the first oscillator211. The inverting output of the fourth oscillator214is configured to generate the 0-degree clock signal PHO. A non-inverting output of the fourth oscillator214is connected to an inverting input of the first oscillator211.

The operating principle of the 4-phase clock generator shown inFIG.2is well known in the art, and hence is not discussed herein to avoid repetition.

FIG.3illustrates a schematic diagram of the delay line shown inFIG.1in accordance with various embodiments of the present disclosure. The four delay lines shown inFIG.1may have the same structure. The second delay line112is used as an example to illustrate the structure and operating principles of the delay lines shown inFIG.1.

The second delay line112comprises a biasing circuit and a plurality of inverting legs. The biasing circuit comprising an upper transistor M41and a lower transistor M42connected in series between a supply voltage VDD and ground. The plurality of inverting legs is connected in parallel between the supply voltage VDD and ground. Each inverting leg comprises a first transistor, a second transistor, a third transistor and a fourth transistor connected in series. As shown inFIG.2, a first inverting leg of the plurality of inverting legs comprises transistors M11, M12, M13, M14connected in series between VDD and ground. A second inverting leg of the plurality of inverting legs comprises transistors M21, M22, M23, M24connected in series between VDD and ground. A last inverting leg of the plurality of inverting legs comprises transistors M31, M32, M33, M34connected in series between VDD and ground. In some embodiments, M11, M12, M21, M22, M31, M32and M41are p-type transistors. M13, M14, M23, M24, M33, M34and M42are n-type transistors.

As shown inFIG.3, gates of transistors M11, M21and M31are connected to a gate of the upper transistor M41. In the first inverting leg, a gate of M12and a gate of M13are connected together and function as an input of the first inverting leg. A midpoint VM1of the first inverting leg functions as an output of the first inverting leg. In the second inverting leg, a gate of M22and a gate of M23are connected together and function as an input of the second inverting leg. A midpoint VM2of the second inverting leg functions as an output of the second inverting leg. In the last inverting leg, a gate of M32and a gate of M33are connected together and function as an input of the last inverting leg. A midpoint VM3of the last inverting leg functions as an output of the last inverting leg. Gates of transistors M14, M24and M34are connected to a gate of the lower transistor M42.

As shown inFIG.3, an input of the first inverting leg is configured to receive the first multi-phase clock signal PH180. An output of the first inverting leg is connected to an input of the second inverting leg. An output of the second inverting leg is connected to an input of an adjacent inverting leg (not shown). An input of the last inverting leg is connected to an output of an adjacent inverting leg (not shown). An output of the last inverting leg is configured to generate PH180D as shown inFIG.3. Once the calibration process of the first multi-phase clock signal PH180finishes, the output of the last inverting leg is configured to generate the calibrated signal of the first multi-phase clock signal (PH180C).

In operation, each inverting leg functions as a current-starved inverter. The second delay line112is configured to receive the first control signal VC1at the gate of M42. The current-starved inverters are able to convert the first control signal VC1into a voltage-controlled delay. In each inverting leg, the uppermost transistor (e.g., M11) and the lowermost transistor (e.g., M14) function as current sources. Two middle transistors (e.g., M12and M13) function as an inverter. In response to the first control signal VC1, the current sources (e.g., M11and M14) are able to control the current supplied to the inverters (e.g., M12and M13). In particular, the currents supplied to the inverters are determined by the biasing circuit formed by M41and M42. The current through M42is proportional to the gate-to-source voltage of M42(VC1). Therefore, the greatest current results in the shortest delay. As such, when VC1is increased, the delay is reduced. On the other hand, the smaller the current, the greater the delay. As such, when VC1is decreased, the delay is increased. The second delay line112is able to add an adjustable delay into PH180in response to VC1. Once an appropriate delay has been added into PH180, the second delay line112generates PH180C. PH180C is a calibrated signal of PH180.

FIG.4illustrates a block diagram of the first clock skew calibration unit shown inFIG.1in accordance with various embodiments of the present disclosure. The first clock skew calibration unit121comprises a frequency doubler402, a frequency divider404, a latch circuit406, a buffer408, a delay line control circuit410and a filter412.

As shown inFIG.4, the frequency doubler402is configured to receive a plurality of multi-phase clock signals PH0D, PH90D, PH180D and PH270D. Based on the plurality of multi-phase clock signals, the frequency doubler402generates a clock signal CLKOUT. The frequency divider404is configured to receive the clock signal CLKOUT and generate a reduced frequency signal CLKDIV2based on the clock signal CLKOUT. The frequency of CLKDIV2is one half of the frequency of CLKOUT. The reduced frequency signal CLKDIV2has a duty cycle indicating a skew of a first multi-phase clock signal PH180D.

The reduced frequency signal CLKDIV2is fed into the date input of the latch circuit406. The 90-degree clock signal PH90is fed into the clock input of the latch circuit406through the buffer408. The latch circuit406is configured to generate a direction control signal SEL.

The filter412is configured to receive the reduced frequency signal CLKDIV2, and generate a dc signal VDUTY. The voltage of VDUTY is proportional to the duty cycle of the reduced frequency signal CLKDIV2.

The delay line control circuit410is configured to receive VDUTY, SEL and a predetermined reference voltage Vref. The delay line control circuit410is configured to compare the duty cycle of the reduced frequency signal CLKDIV2with a predetermined duty cycle. In some embodiments, VDUTY represents the duty cycle of the reduced frequency signal CLKDIV2. Vref represents the predetermined duty cycle. In some embodiments, the predetermined duty cycle is equal to 50%.

In operation, based on VDUTY, Vref and SEL, the delay line control circuit410generates the first control signal VC1to adjust the skew of the first multi-phase clock signal PH180through adjusting a first delay applied to the first multi-phase clock signal PH180until a calibrated signal of the first multi-phase clock signal is achieved.

FIG.5illustrates a schematic diagram of the frequency doubler shown inFIG.4in accordance with various embodiments of the present disclosure. The frequency doubler402comprises a first transmission gate501and a second transmission gate502. The frequency doubler402is configured to receive PH0D, PH90D, PH180D and PH270D, and generate the clock signal CLKOUT.

An input of the first transmission gate501is configured to receive the 0-degree clock signal PH0D. An output of the first transmission gate501is connected to an output of the frequency doubler402. A first control terminal of the first transmission gate501is configured to receive the 90-degree clock signal PH90D. A second control terminal of the first transmission gate501is configured to receive the 270-degree clock signal PH270D.

An input of the second transmission gate502is configured to receive the 180-degree clock signal PH180D. An output of the second transmission gate502is connected to the output of the frequency doubler402. A first control terminal of the second transmission gate502is configured to receive the 270-degree clock signal PH270D. A second control terminal of the second transmission gate502is configured to receive the 90-degree clock signal PH90D.

The operating principle of the frequency doubler shown inFIG.5is well known in the art, and hence is not discussed herein to avoid repetition.

FIG.6illustrates a schematic diagram of the frequency divider shown inFIG.4in accordance with various embodiments of the present disclosure. The frequency divider404is implemented as a latch circuit602. The clock signal CLKOUT is fed into the clock input of the latch circuit602. The date input and the Q-bar output of the latch circuit602are connected together. The Q output of the latch circuit602is configured to generate the reduced frequency signal CLKDIV2.

The operating principle of the frequency divider shown inFIG.6is well known in the art, and hence is not discussed herein to avoid repetition.

FIG.7illustrates a schematic diagram of the filter shown inFIG.4in accordance with various embodiments of the present disclosure. The filter412comprises a resistor R1and a capacitor C1. One terminal of R1is the input of the filter412. A common node of R1and C1is the output of the filter412. The filter412is a low-pass filter configured to convert the reduced frequency signal CLKDIV2into a de signal VDUTY. The voltage of the de signal VDUTY is proportional to the duty cycle of the reduced frequency signal CLKDIV2.

FIG.8illustrates a schematic diagram of the delay line control circuit shown inFIG.4in accordance with various embodiments of the present disclosure. The delay line control circuit410comprises an inverter804, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4and a comparator802.

As shown inFIG.8, the inverter804is configured to receive the direction control signal SEL, and generate an inverted signal SELB of the direction control signal SEL. A first drain/source terminal of the first switch S1is configured to receive the de signal VDUTY. A second drain/source terminal of the first switch S1is connected to a non-inverting input of the comparator802. A gate of the first switch S1is controlled by the direction control signal SEL.

A first drain/source terminal of the second switch S2is configured to receive the reference voltage Vref. A second drain/source terminal of the second switch S2is connected to the non-inverting input of the comparator802. A gate of the second switch S2is controlled by the inverted signal SELB of the direction control signal SEL.

A first drain/source terminal of the third switch S3is configured to receive the dc signal VDUTY. A second drain/source terminal of the third switch S3is connected to an inverting input of the comparator802. A gate of the third switch S3is controlled by the inverted signal SELB of the direction control signal SEL.

A first drain/source terminal of the fourth switch S4is configured to receive the reference voltage Vref. A second drain/source terminal of the fourth switch S4is connected to the inverting input of the comparator802. A gate of the fourth switch S4is controlled by the direction control signal SEL.

In operation, SEL and SELB control the on and off of switches S1, S2, S3and S4. When SEL is of a logic high state, VDUTY is fed into the non-inverting input of the comparator802, and Vref is fed into the inverting input of the comparator802. On the other hand, When SEL is of a logic low state, VDUTY is fed into the inverting input of the comparator802, and Vref is fed into the non-inverting input of the comparator802. The output of the comparator802is configured to generate the first control signal VC1.

FIG.9illustrates various waveforms associated with of the first clock skew calibration unit in accordance with various embodiments of the present disclosure. The horizontal axis ofFIG.9represents intervals of time. There may be eight rows inFIG.9. The first row represents PH0D. The second row represents PH90D. The third row represents PH180D. The fourth row represents PH270D. The fifth row represents the clock signal CLKOUT. The sixth row represents a first reduced frequency signal CLKDIV2A. The seventh row represents a second reduced frequency signal CLKDIV2B. The eighth row represents the direction control signal SEL.

Referring back toFIG.1, the multi-phase clock generator110is configured to generate PHO, PH90, PH180and PH270. After PHO, PH90, PH180and PH270pass through respective delay lines, PH0D, PH90D, PH180D and PH270D are generated and fed into the clock signal skew calibration circuit. In some embodiments, there is a skew at PH180D. This skew is indicated by the dashed line between t2and t3.

The clock signal CLKOUT is generated based on PH0D, PH90D, PH180D and PH270D. As shown inFIG.9, at t1, in response to the leading edge of PH90D and the falling edge of PH270D, CLKOUT changes from a logic high state to a logic low state. At t3, in response to the leading edge (dashed line) of PH180D, CLKOUT changes from a logic low state to a logic high state (dashed line). At t4, in response to the leading edge of PH270and the falling edge of PH90D, CLKOUT changes from a logic high state to a logic low state. At t5, in response to the leading edge of PH0D, CLKOUT changes from a logic low state to a logic high state.

There are two reduced frequency signals CLKDIV2A and CLKDIV2B. As shown inFIG.9, the rising edge of CLKDIV2A is aligned with the rising edge of PHO. The rising edge of CLKDIV2B is aligned with the rising edge of PH180D. When PH180D lags, the duty cycle of CLKDIV2A is greater than 50%, and the duty cycle of CLKDIV2B is less than 50%. As such, the skew calibration process has two opposite directions.

Referring back toFIG.8, when the rising edge of the reduced frequency signal is aligned with the rising edge of PHO, SEL has a logic high state. When the rising edge of the reduced frequency signal is aligned with the rising edge of PH180, SEL has a logic low state. When SEL has a logic high state and PH180D lags, the duty cycle of the reduced frequency signal is greater than 50%. When SEL has a logic low state and PH180D lags, the duty cycle of the reduced frequency signal is less than 50%.

Referring back toFIG.8, when SEL has a logic high state, VDUTY is connected to the non-inverting input of the comparator802and Vref is connected to the inverting input of the comparator802. Since the duty cycle of the reduced frequency signal is greater than 50%, VDUTY is greater than Vref. VC1increases. Referring back toFIG.3, the increased VC1reduces the delay added into PH180. As a result, the skew of PH180is reduced. When SEL has a logic low state, VDUTY is connected to the inverting input of the comparator802and Vref is connected to the non-inverting input of the comparator802. Since the duty cycle of the reduced frequency signal is less than 50%, VDUTY is less than Vref. VC1increases. Referring back toFIG.3, the increased VC1reduces the delay added into PH180. As a result, the skew of PH180is reduced.

In operation, the skew calibration process has two opposite directions. The direction of the skew calibration process can be determined through sampling the reduced frequency signal using PH90D. For example, PH90D is used to sample CLKDIV2A, and the result is a logic high state. This logic high state indicates that the rising edge of CLKDIV2A is aligned with PH0D. The duty cycle of CLKDIV2A is greater than 50%. After knowing this direction of the skew calibration process, the delay line control circuit is able to reduce the delay added into PH180D so as to make the duty cycle of CLKDIV2A equal to 50%. Once the duty cycle of CLKDIV2A is equal to 50%, the corresponding delay is an appropriate delay added into PH180. Under this appropriate delay, the output PH180C is the calibrated signal of PH180.

One advantageous feature of the skew calibration control scheme shown inFIG.9is that through adjusting the delay added into PH180, the duty cycle of the reduced frequency signal (e.g., CLKDIV2A) is set at 50%. Once the duty cycle of the reduced frequency signal (e.g., CLKDIV2A) is set at 50%, the phase difference between PH0D and PH180C is equal to 180 degrees.

FIG.10illustrates a schematic diagram of the second clock skew calibration unit shown inFIG.1in accordance with various embodiments of the present disclosure. The second clock skew calibration unit122comprises a first logic gate1011, a second logic gate1021, a first filter1012, a second filter1022and a first comparator1002. The first logic gate1011and the second logic gate1021are implemented as AND gates.

The first logic gate1011is configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal. As shown inFIG.10, the calibrated signal of the first multi-phase clock signal is PH180C. The second multi-phase clock signal is PH90D.

The second logic gate1021is configured to perform a second AND operation on a reference multi-phase clock signal and the second multi-phase clock signal. As shown inFIG.10, the reference multi-phase clock signal is PH0D.

The output of the first logic gate1011is fed into the non-inverting input of the first comparator1002through the first filter1012. The output of the second logic gate1021is fed into the inverting input of the first comparator1002through the second filter1022. Both filters1012and1022are RC filters similar to the filter412described above with respect toFIG.7.

The first comparator1002is configured to compare the output of the first logic gate1011with an output of the second logic gate1021, and generate the second control signal VC2to adjust the skew of the second multi-phase clock signal PH90D through adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal PH90C of the second multi-phase clock signal is achieved.

FIG.11illustrates various waveforms associated with of the second clock skew calibration unit in accordance with various embodiments of the present disclosure. The horizontal axis ofFIG.11represents intervals of time. There may be five rows inFIG.11. The first row represents PH0D. The second row represents PH90D. The third row represents PH180C. The fourth row represents a result after an AND operation performed on PH0D and PH90D. The fifth row represents a result after an AND operation performed on PH90D and PH180C.

PH90D is the clock signal to be calibrated. There is a skew at PH90D. This skew is indicated by the dashed line between t1and t2. The output of the second logic gate1021(PH0D&PH90D) has a logic high state from t2to t3. The output of the first logic gate1011(PH90D&PH180C) has a logic high state from t3to t4. When PH90D lags, the duty cycle of the output of the first logic gate1011is greater than the duty cycle of the output of the second logic gate1021. This duty cycle difference can be used to generate the second control signal VC2as shown inFIG.10. For example, in response to VC2, the delay added into PH90D is reduced so as to make the duty cycle of the output of the first logic gate1011equal to the duty cycle of the output of the second logic gate1021. Once these two duty cycles are equal, the corresponding delay is an appropriate delay added into PH90. Under this appropriate delay, the output PH90C is the calibrated signal of PH90.

FIG.12illustrates a schematic diagram of the third clock skew calibration unit shown inFIG.1in accordance with various embodiments of the present disclosure. The third clock skew calibration unit123comprises a third logic gate1211, a fourth logic gate1221, a third filter1212, a fourth filter1222and a second comparator1202. The third logic gate1211and the fourth logic gate1221are implemented as AND gates.

The third logic gate1211is configured to perform a third AND operation on a reference multi-phase clock signal and a third multi-phase clock signal. As shown inFIG.12, the reference multi-phase clock signal is PH0D. The third multi-phase clock signal is PH270D.

The fourth logic gate1221is configured to perform a fourth AND operation on calibrated signal of the first multi-phase clock signal and the third multi-phase clock signal. As shown inFIG.12, the calibrated signal of the first multi-phase clock signal is PH180C.

The output of the third logic gate1211is fed into the non-inverting input of the second comparator1202through the third filter1212. The output of the fourth logic gate1221is fed into the inverting input of the second comparator1202through the fourth filter1222. Both filters1212and1222are RC filters similar to the filter412described above with respect toFIG.7.

The second comparator1202is configured to compare the output of the third logic gate1211with an output of the fourth logic gate1221, and generate the third control signal VC3to adjust the skew of the third multi-phase clock signal PH270through adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.

FIG.13illustrates various waveforms associated with of the third clock skew calibration unit in accordance with various embodiments of the present disclosure. The horizontal axis ofFIG.13represents intervals of time. There may be five rows inFIG.13. The first row represents PH0D. The second row represents PH180C. The third row represents PH270D. The fourth row represents a result after an AND operation performed on PH0D and PH270D. The fifth row represents a result after an AND operation performed on PH180C and PH270D.

PH270D is the clock signal to be calibrated. There is a skew at PH270D. This skew is indicated by the dashed line between t1and t2. The output of the third logic gate1211(PH0D&PH270D) has a logic high state from t3to t4. The output of the fourth logic gate1221(PH180C&PH270D) has a logic high state from t2to t3. When PH270D lags, the duty cycle of the output of the third logic gate1211is greater than the duty cycle of the output of the fourth logic gate1221. This duty cycle difference can be used to generate the third control signal VC3as shown inFIG.12. For example, in response to VC3, the delay added into PH270is reduced so as to make the duty cycle of the output of the fourth logic gate1221equal to the duty cycle of the output of the third logic gate1211. Once these two duty cycles are equal, the corresponding delay is an appropriate delay added into PH270. Under this appropriate delay, the output PH270C is the calibrated signal of PH270.

FIG.14illustrates a flow chart of controlling the clock signal skew calibration circuit shown inFIG.1in accordance with various embodiments of the present disclosure. This flowchart shown inFIG.14is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated inFIG.14may be added, removed, replaced, rearranged and repeated.

Referring back toFIG.1, the clock signal skew calibration circuit comprises a first clock skew calibration unit121, a second clock skew calibration unit122and a third clock skew calibration unit123. Referring back toFIG.4, the first clock skew calibration unit121comprises a frequency doubler402, a frequency divider404, a latch circuit406, a buffer408, a delay line control circuit410and a filter412.

At step1402, a clock signal is generated by a frequency doubler based on a plurality of multi-phase clock signals.

At step1404, a reduced frequency signal is generated, by a frequency divider, based on the clock signal. The reduced frequency signal has a duty cycle indicating a skew of a first multi-phase clock signal.

At step1406, the duty cycle of the reduced frequency signal is compared with a predetermined duty cycle.

At step1408, a first control signal is generated by a delay line control circuit. The first control signal is used to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

The method further comprises performing a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal, performing a second AND operation on a reference multi-phase clock signal and the second multi-phase clock signal, and comparing a result of the first AND operation with a result of the second AND operation, and based on a comparison result from the step of comparing the result of the first AND operation with the result of the second AND operation, generating a second control signal to adjust a skew of the second multi-phase clock signal through adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved.

The method further comprises performing a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal, performing a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signal, and comparing a result of the third AND operation with a result of the fourth AND operation, and based on a comparison result from the step of comparing the result of the third AND operation with the result of the fourth AND operation, generating a third control signal to adjust a skew of the third multi-phase clock signal through adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.

The method further comprises generating, by a multi-phase clock generator, 4-phase clock signals comprising a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal and a 270-degree clock signal, wherein the reference multi-phase clock signal is the 0-degree clock signal, the first multi-phase clock signal is the 180-degree clock signal, the second multi-phase clock signal is the 90-degree clock signal, and the third multi-phase clock signal is the 270-degree clock signal.

In some embodiments, the multi-phase clock generator comprises a first oscillator, a second oscillator, a third oscillator and a fourth oscillator connected in cascade, and wherein an inverting output of the first oscillator is connected to a non-inverting input of the second oscillator, wherein the inverting output of the first oscillator is configured to generate the 270-degree clock signal, a non-inverting output of the first oscillator is connected to an inverting input of the second oscillator, an inverting output of the second oscillator is connected to a non-inverting input of the third oscillator, wherein the inverting output of the second oscillator is configured to generate the 180-degree clock signal, a non-inverting output of the second oscillator is connected to an inverting input of the third oscillator, an inverting output of the third oscillator is connected to a non-inverting input of the fourth oscillator, wherein the inverting output of the third oscillator is configured to generate the 90-degree clock signal, a non-inverting output of the third oscillator is connected to an inverting input of the fourth oscillator, an inverting output of the fourth oscillator is connected to a non-inverting input of the first oscillator, wherein the inverting output of the fourth oscillator is configured to generate the 0-degree clock signal, and a non-inverting output of the fourth oscillator is connected to an inverting input of the first oscillator.

In some embodiments, the frequency divider is a latch circuit, and the frequency doubler comprises a first transmission gate and a second transmission gate, and wherein an input of the first transmission gate is configured to receive the 0-degree clock signal, an output of the first transmission gate is connected to an output of the frequency doubler, a first control terminal of the first transmission gate is configured to receive the 90-degree clock signal, a second control terminal of the first transmission gate is configured to receive the 270-degree clock signal, an input of the second transmission gate is configured to receive the 180-degree clock signal, an output of the second transmission gate is connected to the output of the frequency doubler, a first control terminal of the second transmission gate is configured to receive the 270-degree clock signal, and a second control terminal of the second transmission gate is configured to receive the 90-degree clock signal.

The method further comprises converting the reduced frequency signal into a dc signal, wherein a voltage of the dc signal is proportional to the duty cycle of the reduced frequency signal, and comparing the voltage of the dc signal with a reference voltage proportional to the predetermined duty cycle to obtain the first control signal.

In some embodiments, the delay line control circuit comprises an inverter, a first switch, a second switch, a third switch, a fourth switch and a third comparator, and wherein the inverter is configured to receive a direction control signal and generate an inverted signal of the direction control signal, a first drain/source terminal of the first switch is configured to receive the de signal, a second drain/source terminal of the first switch is connected to a non-inverting input of the third comparator, a gate of the first switch is controlled by the direction control signal, a first drain/source terminal of the second switch is configured to receive the reference voltage proportional to the predetermined duty cycle, a second drain/source terminal of the second switch is connected to the non-inverting input of the third comparator, a gate of the second switch is controlled by the inverted signal of the direction control signal, a first drain/source terminal of the third switch is configured to receive the de signal, a second drain/source terminal of the third switch is connected to an inverting input of the third comparator, a gate of the third switch is controlled by the inverted signal of the direction control signal, a first drain/source terminal of the fourth switch is configured to receive the reference voltage proportional to the predetermined duty cycle, a second drain/source terminal of the fourth switch is connected to the inverting input of the third comparator, a gate of the fourth switch is controlled by the direction control signal, and an output of the third comparator is configured to generate the first control signal.

Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.