Patent ID: 12231587

It should be understood that the dimensions of various parts shown in the accompanying drawings are not necessarily drawn according to actual proportional relations. In addition, the same or similar components are denoted by the same or similar reference signs.

DETAILED DESCRIPTION

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The following description of the exemplary embodiments is merely illustrative and is in no way intended as a limitation to the present disclosure, its application or use. The present disclosure may be implemented in many different forms, which are not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art. It should be noticed that: relative arrangement of components and steps, material composition, numerical expressions, and numerical values set forth in these embodiments, unless specifically stated otherwise, should be explained as merely illustrative, and not as a limitation.

The use of the terms “first”, “second” and similar words in the present disclosure do not denote any order, quantity or importance, but are merely used to distinguish between different parts. A word such as “comprise”, “have” or variants thereof means that the element before the word covers the element(s) listed after the word without excluding the possibility of also covering other elements. The terms “up”, “down”, or the like are used only to represent a relative positional relationship, and the relative positional relationship may be changed correspondingly if the absolute position of the described object changes.

In the present disclosure, when it is described that a specific component is disposed between a first component and a second component, there may be an intervening component between the specific component and the first component or between the specific component and the second component. When it is described that a specific part is connected to other parts, the specific part may be directly connected to the other parts without an intervening part, or not directly connected to the other parts with an intervening part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as the meanings commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms as defined in general dictionaries, unless explicitly defined herein, should be interpreted as having meanings that are consistent with their meanings in the context of the relevant art, and not to be interpreted in an idealized or extremely formalized sense.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, these techniques, methods, and apparatuses should be considered as part of this specification.

FIG.1is a schematic structural view showing a PUF device according to an embodiment of the present disclosure.

As shown inFIG.1, the PUF device comprises a first signal generating circuit11, a second signal generating circuit12, an output circuit13and a control circuit14.

The first signal generating circuit11is configured to generate a first clock signal of n-th period according to a control signal of the n-th period and an input signal of the n-th period. Here, n is an integer greater than or equal to 2. In some embodiments, the control signal comprises a control word. It can be understood that, the control word may be an integer, or may comprise an integer part and a decimal part.

In some embodiments, the first signal generating circuit11comprises a first TAF-DPS (Time-Average-Frequency Direct Period Synthesis) circuit11. For example, the first TAF-DPS circuit selects one of a plurality of clock signals as the input signal of the n-th period, and the first clock signal of the n-th period is obtained after the input signal of the n-th period passes through a TFF (toggle Flip Flop, flip flip-flop) in the first TAF-DPS circuit. For example, the first TAF-DPS circuit11selects one of a plurality of clock signals as the input signal of the n-th period according to the control word of the n-th period.

The second signal generating circuit12is configured to generate a second clock signal of the n-th period according to the control signal of the n-th period and the input signal of the n-th period.

In some embodiments, the second signal generating circuit12comprises a second TAF-DPS circuit. Similarly, for example, the second TAF-DPS circuit selects one of a plurality of clock signals as the input signal of the n-th period, and the first clock signal of the n-th period is obtained after the input signal of the n-th period passes through a TFF in the second TAF-DPS circuit.

The output circuit13is configured to output an output signal of the n-th period according to the first clock signal of the n-th period and the second clock signal of the n-th period.

In some embodiments, the output circuit13may determine whether the logic level of the output signal of each period is 0 or 1 according to the time when the first clock signal and the second clock signal reach the output circuit13, which will be described in detail hereinafter in conjunction with different implementations. It can be understood that, the time when the first clock signal of the n-th period and the second clock signal of the n-th period reach the output circuit13is unpredictable, so the logic level of the output signal is also unpredictable, that is, random.

The control circuit14is configured to process an initial control signal of the n-th period according to a reference value to obtain the control signal of the n-th period. Here, the reference value comprises at least the logic level of the output signal of (n−1)-th period. In some embodiments, the probability that the logic level of the output signal is a first logic level is 0.5, the probability that the logic level of the output signal is a second logic level is 0.5. The first logic level and the second logic level have opposite logics. For example, the first logic level is 0 and the second logic level is 1, vice versa.

For example, the initial control signal is generated by the control circuit14. It should be noted that, initial control signals of different periods may be the same or different. For example, the initial control signals of some periods are the same, and different from the initial control signals of other periods. For another example, the initial control signals of all periods are the same, that is, the initial control signals are no longer changed once generated.

In some embodiments, the reference value comprises only the logic level of the output signal of the (n−1)-th period. In this case, the control circuit14processes the initial control signal of the n-th period only according to the logic level of the output signal of the previous period to obtain the control signal of the current period.

In other embodiments, the reference value also comprises other values other than the logic level of the output signal of the (n−1)-th period. For example, the reference value also comprises the logic level of the output signal of the (n−2)-th period, the logic level of the output signal of the (n−3)-th period, or the like. In this case, the control circuit14may process the initial control signal of the n-th period according to the logic levels of output signals of a plurality of periods before the current period to obtain the control signal of the current period.

In some embodiments, the initial control signal comprises an initial control word. For example, the processing to the initial control word of the n-th period may comprise various mathematical operations, for example, multiplication operation, addition operation, or the like.

In the above embodiments, the control circuit processes the initial control signal of the current period according to the reference value comprising the logic level of the output signal of the previous period to obtain the control signal of the current period. The logic level of the output signal of the PUF device is unpredictable. The logic level of the output signal of the previous period is introduced into the control signal of the current period, which increases the unpredictability of the control signal of the current period. In this way, the unpredictability of the first clock signal and the second clock signal generated based on the control signal of the current period is increased, thereby increasing the randomness and unpredictability of the output signal of the current period, and improving the security of the PUF device.

It should be understood that, the first signal generating circuit11and the second signal generating circuit12may be implemented in different ways. In some embodiments, the first signal generating circuit11comprises a first TAF-DPS circuit, and the second signal generating circuit12comprises a second TAF-DPS circuit. Correspondingly, the control signal may comprise a control word, and the initial control signal may comprise an initial control word. With the TAF-DPS circuit as the signal generating circuit, the randomness and unpredictability of the output signal is further increased, and the security of the PUF device is further improved.

Some implementations of processing the initial control word according to the reference value will be described below in conjunction with different embodiments.

In some embodiments, the initial control word C=F+r, where F is an integer, and r is a decimal greater than 0 and smaller than 1. The control word C(n) of the n-th period is obtained by performing mathematical operation on the reference value and at least one of F or r. Here, it can be understood that, r will affect the periods of the first clock signal and the second clock signal.

In some embodiments, each of the first clock signal and the second clock signal has a first period with a probability of r and a second period with a probability of 1−r. The first period is F+1, and the second period is F. The larger r is, the higher the proportion of the first period will be.

As some implementations, the control word C(n) of the n-th period is obtained by performing mathematical operation on the reference value and each of F and r. In other words, the control word C(n) of the n-th period is obtained after F and r are both mathematically operated with the reference value.

As other implementations, the control word C(n) of the n-th period is obtained by performing mathematical operation on the reference value and one of F and r. For example, the control word of the n-th period is C(n)=M+N, where M is one of F and r, and N is obtained by performing mathematical operation on the reference value and the other of F and r. In this way, the security of the PUF device is enhanced with less cost.

In some cases, the area occupied by the PUF device is restricted. In some embodiments, in order to enhance much more security using the PUF device in the case of limited area, M is F, and N is obtained by performing mathematical operation on r and the reference value. In other words, the reference value only affects the value of the decimal part of the initial control word, and not affects the value of the integer part of the initial control word. In this way, the control circuit14can be implemented with a simple structure. On one hand, the security of the PUF device can be improved; on the other hand, due to the simple structure, the area occupied by the control circuit14in the PUF device and the power consumption of the PUF device both can be reduced.

In a case where the control word of the n-th period C(n)=F+N, the above mathematical operation may comprise a multiplication operation. Some implementations of calculating N will be provided below.

In some implementations, N=B└A(n-1)┘×r. In this case, the control word of the n-th period C(n)=F+B└A(n-1)┘×r. Here, B└A(n-1)┘is the logic level of the output signal of the (n−1)-th period.

In other implementations, N=Σi=1mB└A (n-i)┘·ri. In this case, the control word of the n-th period C(n)=F+Σi=1mB└A(n-i)┘·ri.

Here, m is the number of digits of r after decimal point, ri=0·p, p is the last i digit in r, and B└A(n-i)┘represents the logic level of the output signal of the n−ith period. Further, in a case where n−i is smaller than or equal to 0, B└A(n-i)┘=0. As an example, if r=0.125, then r1=0.5, r2=0.25, and r3=0.125.

In this way, the randomness and unpredictability of the output signal of the PUF device can be further improved, thereby further improving the security of the PUF device.

In some embodiments, in the case where the control word C(n)=F+N of the n-th period, r=0.5. In this way, the randomness and unpredictability of the output signal of the PUF device can be still further improved, thereby still further improving the security of the PUF device.

In some embodiments, each of the first TAF-DPS circuit11and the second TAF-DPS circuit12is configured to determine the input signal of the n-th period according to the control word of the n-th period. In this way, the control word of the n-th period is random, so that the input signal of the n-th period is also random.

FIG.2is a schematic structural view showing a PUF device according to another embodiment of the present disclosure.

Compared toFIG.1, the PUF device shown inFIG.2also comprises a ring oscillator15. In addition, the first signal generating circuit11comprises a first TAF-DPS circuit, and the second signal generating circuit11comprises a second TAF-DPS circuit. The first TAF-DPS circuit comprises a first accumulator111, a first multiplexer112and a first register113, and the second TAF-DPS circuit comprises a second accumulator121, a second multiplexer122and a second register123.

The ring oscillator15is configured to generate K clock signals with a same frequency, where K is an integer greater than or equal to two. There is a same time interval between the j-th clock signal and the (j−1)-th clock signal, where j is any one integer between 2 and K. For example, in a case where K is 4, j may be 2, 3 and 4.

For example, the time interval between the first clock signal and the second clock signal, the time interval between the second clock signal and the third clock signal . . . and the time interval between the K-th clock signal and the (K−1)-th clock signal are the same. In some embodiments, the control circuit14is further configured to provide the same frequency. The ring oscillator15generates corresponding K clock signals according to the same frequency provided by the control circuit14.

The first accumulator111is configured to calculate the accumulated value A1(n) of the n-th period in the first accumulator111according to the formula 1 below:
A1(n)=(A1(n−1)+C(n))(modK)  (formula 1).

Here, A1(n−1) is the accumulated value of the (n−1)-th period in the first accumulator111. In some embodiments, an initial value of the accumulated value in the first accumulator111is 0, and the accumulated value of the first period in the first accumulator is A1(1) which equals to the initial control word. For example, the control circuit14generates the initial control word and then provides the initial control word to the first accumulator111.

C(n) is the control word of the n-th period, and C(n) is greater than or equal to 2 and smaller than or equal to 2K−1. C(n) may be determined according to multiple ways introduced above, which will not be described in detail here.

For the formula 1, there are positive integers q1 and f1 such that A1(q1) is constantly equal to A1(f1)(mod K), and f1 is greater than q1. That is, the f1 can be regarded as the recursive period of the chaotic recursive equation shown in the formula 1.

The first register113is configured to control the first multiplexer112to select one of the K clock signals as the input signal of the n-th period according to the integer in A1(n). For example, if the integer in A1(3) is 3, the first multiplexer112may select the fourth clock signal as the input signal of the third period.

The second accumulator121is configured to calculate the accumulated value A2(n) of the n-th period in the second accumulator121according to the following formula 2:
A2(n)=(A2(n−1)+C(n))(modK)  (formula 2).

Here, A2(n−1) is the accumulated value of the (n−1)-th period in the second accumulator121. In some embodiments, an initial value of the accumulated value in the second accumulator121is 0, and the accumulated value of the first period in the second accumulator121is A2(1)=A1(1), which equals to the initial control word.

Likewise, for the formula 2, there are positive integers q2 and f2 such that A2(q2) is constantly equal to A2(f2)(mod K). The f2 can be regarded as the recursive period of the chaotic recursive equation shown in the formula 2.

The second register123is configured to control the second multiplexer122to select one of the K clock signals as the input signal of the n-th period according to the integer in A2(n). In some embodiments, the clock signal selected by the second multiplexer122is the same as the clock signal selected by the first multiplexer112.

In the above embodiments, since the logic level of the output signal of the previous period is random, the control word of the current period is also random, so that the accumulated values in the first accumulator and the second accumulator are random, and the clock signals selected by the first multiplexer and the second multiplexer are random. Finally, the first clock signal and the second clock signal are also random, thereby increasing the randomness and unpredictability of the output signal and improving the security of the PUF device.

In some embodiments, A2(1)=A1(1), A2(n)=A1(n), q2=q1, and f2=f1. In this case, for each period, the values accumulated in the first accumulator111and the second accumulator121are the same, so that the recursive periods of the chaotic recursive equations shown in the formulas 1 and 2 are the same. In this way, the clock signal selected by the second multiplexer122is the same as the clock signal selected by the first multiplexer112. Accordingly, the logic level of the output signal output by the PUF device based on the same input signal is more random, and the randomness of the output signal of the PUF output device is further improved, thereby further improving the security of the PUF device.

In some embodiments, the control circuit14is further configured to provide an initial value; and the first register113and the second register123are further configured to control the first multiplexer112and the second multiplexer to select a same clock signal from the K clock signals as the input signal of the first period respectively, according to the initial value provided by the control circuit14. It should be understood that, the first register113is configured to control the first multiplexer112to select the same clock signal from the K clock signals as the input signal of the first period according to the initial value provided by the control circuit14, and the second register123is configured to control the second multiplexer122to select the same clock signal from the K clock signals as the input signal of the first period according to the initial value provided by the control circuit14.

It should be noted that, the initial value here may be set according to actual conditions. For example, the initial value is 1, and each of the first multiplexer112and the second multiplexer122may select the second clock signal as the input signal of the first period.

In some embodiments, the first signal generating circuit11is further configured to generate a first clock signal of the first period according to a control signal of the first period and an input signal of the first period; the second signal generating circuit12is further configured to generate a second clock signal of the first period according to the control signal of the first period and the input signal of the first period; and the output circuit13is further configured to generate an output signal of the first period according to the first clock signal of the first period and the second clock signal of the first period. For example, the control word of the first period is the initial control word generated by the control circuit14.

FIGS.3A and3Bshow variations of accumulated values of the first accumulator and the second accumulator under different conditions according to some embodiments of the present disclosure. Here, it is assumed that the accumulated values of the control word in the first accumulator and the second accumulator are the same, the number of the clock signals is K=32, the integer of the initial control word is F=42, and the initial value provided by the control circuit14is 0.

The horizontal ordinate corresponding to the position of each arrow inFIGS.3A and3Bis the accumulated value of the current period, and the vertical ordinate corresponding to the position of each arrow is the accumulated value of the next period.

In the case shown inFIG.3A, the initial control word is not processed according to the reference value, and the accumulated value each time is the same. It can be seen fromFIG.3Athat, the accumulated value changes regularly. When the accumulated value becomes the initial value of 0 again, the accumulated value will change cyclically according to the regularity shown inFIG.3A, with a constant period.

In the case shown inFIG.3B, the initial control word is processed according to the reference value, and the value accumulated each time is random. It can be seen fromFIG.3Bthat, the accumulated value changes randomly, and changes more complicated, and the period is no longer constant. The accumulated value entering the cycle (rhombus point) is not necessarily the initial value of 0.

It can be known from the above comparative analysis that, with the PUF device according to the embodiments of the present disclosure, the response to the excitation of the control word becomes more unpredictable and has the enhanced complexity and randomness.

It should be noted that, the output circuit13inFIGS.1and2may be implemented by different structures, for example, a D flip-flop, a bang-bang frequency discriminator, or the like. It can be understood that, due to the deviation in the process, for the same input signal, the first clock signal and the second clock signal obtained after processing the same input signal by the first TAF-DPS11and the second TAF-DPS12with the same structure reach the output circuit13at different times. Therefore, the output circuit13can encode accordingly.

The implementations of determining the logic level of the output signal of the n-th period by the output circuit13will be described below in conjunction with some embodiments.

In some embodiments, the c-th rising edge of the first clock signal reaches the output circuit13at a first time, and the c-th rising edge of the second clock signal reaches the output circuit13at a second time, where c is an integer greater than or equal to 1. In this case, the output circuit13is configured to determine the logic level of the output signal of the n-th period according to at least the first time and the second time. For example, the output circuit13may comprise a D flip-flop.

For example, if the difference between the second time and the first time is greater than or equal to 0, the logic level of the output signal of the n-th period is 1; and if the difference between the second time and the first time is smaller than 0, the logic level of the output signal of the n-th period is 0.

In other embodiments, the c-th rising edge of the first clock signal reaches the output circuit13at a first time, the c-th rising edge of the second clock signal reaches the output circuit13at a second time, the (c+1)-th rising edge of the first clock signal reaches the output circuit13at a third time, and the (c+1)-th rising edge of the second clock signal reaches the output circuit13at a fourth time. In this case, the output circuit13is configured to determine the logical level of the output signal of the n-th period according to a first difference between the third time and the first time, and a second difference between the fourth time and the second time. For example, the output circuit13may comprise a bang-bang frequency discriminator.

For example, in a case where the first difference is greater than or equal to the second difference, the logic level of the output signal of the n-th period is 1; and in a case where the first difference is smaller than the second difference, the logic level of the output signal of the n-th period is 0.

It should be understood that, the above coding manner is not restrictive, and the output circuit14may also perform coding according to other manners, which will not be exhaustive here.

FIG.4is a schematic flowchart showing an operation method of a PUF device according to an embodiment of the present disclosure.

At step402, an initial control signal of n-th period is processed by a control circuit, according to a reference value to obtain a control signal of the n-th period. Here, the reference value comprises the logic level of an output signal of the (n−1)-th period, where n is an integer greater than or equal to 2.

At step404, a first clock signal of the n-th period is generated by a first signal generating circuit, according to the control signal of the n-th period and an input signal of the n-th period.

At step406, a second clock signal of the n-th period is generated by the second signal generating circuit, according to the control signal of the n-th period and the input signal of the n-th period.

At step408, an output signal of the n-th period is output by an output circuit, according to the first clock signal of the n-th period and the second clock signal of the n-th period.

It should be understood that, the PUF device may perform operation in the method described above, and will not be described in detail here.

In the above embodiments, the control circuit processes the initial control signal of the current period according to the reference value comprising the logic level of the output signal of the previous period to obtain the control signal of the current period. The logic level of the output signal of the PUF device is unpredictable. The logic level of the output signal of the previous period is introduced into the control signal of the current period, which increases the unpredictability of the control signal of the current period. In this way, the unpredictability of the first clock signal and the second clock signal generated based on the control signal of the current period is increased, thereby increasing the randomness and unpredictability of the output signal of the current period, and improving the security of the PUF device.

The embodiments of the present disclosure also provide an encryption method comprising encrypting data to be encrypted using the output signal of the PUF device according to any of the above embodiments. Here, the data to be encrypted may be any data to be encrypted. For example, the data to be encrypted may be encrypted using the output signal of the PUF device as a key.

The embodiments of the present disclosure also provide an electronic device comprising the physical unclonable function device according to any of the above embodiments. In some embodiments, the electronic device comprises a display device. For example, the display device may be any product or component with a display function, such as a mobile terminal, an IoT (Internet of Things) terminal, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or an electronic paper.

Some examples will be provided below to explain the variation of the recursion period f in the formulas 1 and 2 mentioned above.

Table 1 shows the distribution of the recursion period f of the formulas 1 and 2 in a case where the number of clock signals is K=4, the decimal part of the initial control word is 0.5, and the integer part of the initial control word is F ranging from 2 to 7.

TABLE 1K = 4, r = 0.5FqProbabilityExpectation221/45.2541/1653/1661/873/1683/16341/166.687551/1661/473/881/4411/22.812531/451/871/1681/16533/8543/1651/1673/1683/16621/45.2541/1653/1661/873/1683/16741/166.687551/1661/473/881/4F ∈ {2, 3, 4, 5, 6, 7}15.28125

FIGS.5A-5Fshow distribution of recursive cycles according to some embodiments of the present disclosure. In these embodiments, the number of clock signals is K=32, the decimal part of the initial control word is 0.5, and the integer part of the initial control word corresponding toFIGS.5A-5Fis F which is 2 to 7 respectively.

InFIGS.5A-5F, the horizontal ordinate represents the recursive period f, and the vertical ordinate represents the probability that the recursive period f is a corresponding value.

It can be seen from Table 1 andFIGS.5A-5Fthat, in a case where F is a different value, the recursive period f changes randomly, not as a constant value.

In practical applications, the changing complexity of the recursive period f can be adjusted by adjusting the value of r. For example, the output signal of the PUF device constitutes K bits as a key, and when the recursive period f satisfies √{square root over (f)}≥K, it can be considered that the PUF device is safe.

Hereto, various embodiments of the present disclosure have been described in detail. Some details well known in the art are not described to avoid obscuring the concept of the present disclosure. According to the above description, those skilled in the art would fully know how to implement the technical solutions disclosed herein.

Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for the purpose of illustration and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that modifications to the above embodiments and equivalently substitution of part of the technical features can be made without departing from the scope and spirit of the present disclosure. The scope of the disclosure is defined by the following claims.