Patent ID: 12218661

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a”, “an”, and “the” includes plural reference, and the meaning of “in” includes “in” and “on”. Titles or subtitles can be used herein for the convenience of a reader, which shall have no influence on the scope of the present disclosure.

The terms used herein generally have their ordinary meanings in the art. In the case of conflict, the present document, including any definitions given herein, will prevail. The same thing can be expressed in more than one way. Alternative language and synonyms can be used for any term(s) discussed herein, and no special significance is to be placed upon whether a term is elaborated or discussed herein. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms is illustrative only, and in no way limits the scope and meaning of the present disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given herein. Numbering terms such as “first”, “second” or “third” can be used to describe various components, signals or the like, which are for distinguishing one component/signal from another one only, and are not intended to, nor should be construed to impose any substantive limitations on the components, signals or the like.

Reference is made toFIGS.1to4, in whichFIG.1is a schematic diagram of a driver circuit of a display device supplying power generated from a high-side input voltage according to a first embodiment of the present disclosure.

The driver circuit of the present disclosure is applicable to the display device such as, but not limited to an electronic paper.

As shown inFIG.1, the driver circuit of the display device of the first embodiment of the present disclosure may include a high-side transistor TH, a high-side voltage drop suppressor circuit DVH, a low-side voltage drop suppressor circuit DVL, a low-side transistor TL and a control circuit CTR.

A first terminal of the high-side transistor TH is coupled to a high-side input voltage VGH. A first terminal of the high-side voltage drop suppressor circuit DVH is connected to a second terminal of the high-side transistor TH. A second terminal of the high-side voltage drop suppressor circuit DVH is connected to an output terminal PNout of the driver circuit of the display device of the present disclosure.

A first terminal of the low-side voltage drop suppressor circuit DVL is connected to the output terminal PNout of the driver circuit of the display device of the present disclosure and the second terminal of the high-side voltage drop suppressor circuit DVH. A first terminal of the low-side transistor TL is coupled to a low-side input voltage VGL. A second terminal of the low-side transistor TL is connected to the first terminal of the low-side voltage drop suppressor circuit DVL.

The control circuit CTR is connected to a control terminal of the high-side transistor TH and a control terminal of the low-side transistor TL. The control circuit CTR is also connected to a control terminal of the high-side voltage drop suppressor circuit DVH and a control terminal of the low-side voltage drop suppressor circuit DVL.

For example, in the first embodiment of the present disclosure, the high-side transistor TH is a P-type metal oxide semiconductor field effect transistor (PMOS) and the low-side transistor TL is an N-type metal oxide semiconductor field effect transistor (NMOS), but the present disclosure is not limited thereto.

When the output terminal PNout of the driver circuit of the display device supplies power (such as an output voltage Vout reaching 35V as shown inFIG.2) generated from the high-side input voltage VGH as shown inFIG.1, the control circuit CTR outputs a high-side control signal CRH (at a low level as shown inFIG.2) to the control terminal of the high-side transistor TH for turning on the high-side transistor TH and outputs a low-side control signal CRL (at a low level as shown inFIG.2) to the control terminal of the low-side transistor TL for turning off the low-side transistor TL. At the same time, the control circuit CTR may output a high-side voltage drop suppressing signal to the high-side voltage drop suppressor circuit DVH for turning on and controlling an operation of the high-side voltage drop suppressor circuit DVH. At this time, the low-side voltage drop suppressor circuit DVL may be turned off.

For example, as shown inFIG.1, the control circuit CTR modulates a voltage of the high-side control signal CRH outputted to the control terminal of the high-side transistor TH between the high-side input voltage VGH (such as 35V as shown inFIG.2) and a high-side modulation voltage VS (such as 0V as shown inFIG.2).

When the high-side transistor TH and the high-side voltage drop suppressor circuit DVH are turned on, a current sequentially flows through the high-side transistor TH and the high-side voltage drop suppressor circuit DVH to the output terminal PNout of the driver circuit of the display device of the present disclosure as shown inFIG.1.

When the high-side transistor TH and the high-side voltage drop suppressor circuit DVH are turned on at the same time, a voltage drop between the high-side input voltage VGH (such as 35V) and a voltage (such as −35V) of the output terminal PNout of the driver circuit of the display device are divided into two voltages that are withstood respectively by the high-side transistor TH and the high-side voltage drop suppressor circuit DVH. As a result, a voltage drop across the first terminal and the second terminal of the high-side transistor TH is reduced to be not higher than a withstand voltage of the high-side transistor TH.

Therefore, only the high-side transistor TH having a low withstand voltage instead of a high withstand voltage needs to be disposed in the driver circuit of the display device of the present disclosure, under the condition that the driver circuit is able to supply sufficient power and the high-side transistor TH can avoid being damaged due to overvoltage.

When the output terminal PNout of the driver circuit of the display device of the present disclosure supplies power (such as the output voltage Vout reaching −35V as shown inFIG.4) generated from the low-side input voltage VGL as shown inFIG.3, the control circuit CTR outputs the high-side control signal CRH (at a high level as shown inFIG.4) to the control terminal of the high-side transistor TH for turning off the high-side transistor TH and outputs the low-side control signal CRL (at a high level as shown inFIG.4) to the control terminal of the low-side transistor TL for turning on the low-side transistor TL. At the same time, the control circuit CTR may output the high-side voltage drop suppressing signal to the low-side voltage drop suppressor circuit DVL for controlling an operation of the low-side voltage drop suppressor circuit DVL. At this time, the high-side voltage drop suppressor circuit DVH may be turned off.

For example, as shown inFIG.3, the control circuit CTR may modulate a voltage of the low-side control signal CRL between a low-side modulation voltage VDD (such as 3V as shown inFIG.4) and the low-side input voltage VGL (such as −35V as shown inFIG.4).

When the low-side transistor TL and the low-side voltage drop suppressor circuit DVL are turned on, a current sequentially flows through the low-side transistor TL and the low-side voltage drop suppressor circuit DVL to the output terminal PNout of the driver circuit of the display device of the present disclosure as shown inFIG.3.

When the low-side transistor TL and the low-side voltage drop suppressor circuit DVL are turned on at the same time, a voltage drop between the low-side input voltage VGL (such as −35V) and a voltage (such as 35V) of the output terminal PNout of the driver circuit of the display device are divided into two voltages that are withstood respectively by the low-side transistor TL and the low-side voltage drop suppressor circuit DVL. As a result, a voltage drop across the first terminal and the second terminal of the low-side transistor TL is reduced to be not higher than a withstand voltage of the low-side transistor TL.

Therefore, only the low-side transistor TL having a low withstand voltage instead of a high withstand voltage needs to be disposed in the driver circuit of the display device of the present disclosure, under the condition that the driver circuit is able to supply sufficient power and the low-side transistor TL can avoid being damaged due to overvoltage.

Reference is made toFIG.5, which is a circuit diagram of a driver circuit of a display device according to a second embodiment of the present disclosure. The descriptions of the second embodiment of the present disclosure that are the same as the descriptions of the first embodiment of the present disclosure are not repeated herein.

In the second embodiment of the present disclosure, a high-side voltage drop suppressor circuit DVH1of the driver circuit of the display device of the present disclosure includes a transistor as a high-side suppression transistor TEH1as described herein.

A first terminal of the high-side suppression transistor TEH1is connected to the second terminal of the high-side transistor TH. A second terminal of the high-side suppression transistor TEH1is connected to the output terminal PNout of the driver circuit of the display device of the present disclosure. A control terminal of the high-side suppression transistor TEH1may be coupled to the high-side modulation voltage VSS, or may be connected to the control circuit CTR and receive the high-side modulation voltage VSS from the control circuit CTR.

When the output terminal PNout of the driver circuit of the display device supplies power generated from the high-side input voltage VGH, the control circuit CTR outputs the high-side control signal CRH to the control terminal of the high-side transistor TH for turning on the high-side transistor TH. At the same time, the control circuit CTR outputs the high-side voltage drop suppressing signal (having the high-side modulation voltage VSS as shown inFIG.5) to the high-side suppression transistor TEH1for turning on the high-side suppression transistor TEH1.

In the second embodiment of the present disclosure, a low-side voltage drop suppressor circuit DVL1of the driver circuit of the display device of the present disclosure includes a transistor as a low-side suppression transistor TEL1.

A first terminal of the low-side suppression transistor TEL1is connected to the output terminal PNout of the driver circuit of the display device of the present disclosure and the second terminal of the high-side suppression transistor TEH1. A second terminal of the high-side suppression transistor TEH1is connected to the first terminal of the low-side transistor TL. A control terminal of the high-side suppression transistor TEH1may be coupled to the low-side modulation voltage VDD, may be connected to the control circuit CTR and receive the low-side modulation voltage VDD from the control circuit CTR.

When the output terminal PNout of the driver circuit of the display device supplies power generated from the low-side input voltage VGL, the control circuit CTR outputs the low-side control signal CRL to the control terminal of the low-side transistor TL for turning on the low-side transistor TL. At the same time, the control circuit CTR outputs the low-side voltage drop suppressing signal (having the low-side modulation voltage VDD as shown inFIG.5) to the control terminal of the low-side suppression transistor TEL1for turning on the low-side suppression transistor TEL1.

Reference is made toFIG.6, which is a circuit diagram of a driver circuit of a display device according to a third embodiment of the present disclosure. The descriptions of the third embodiment of the present disclosure that are the same as that of the first embodiment of the present disclosure are not repeated herein.

In the third embodiment of the present disclosure, a high-side voltage drop suppressor circuit DVH includes N transistors as N high-side suppression transistors TEH1to TEHn, wherein N is an integer value being larger than 1 and may depend on the withstand voltage of the high-side transistor TH and other requirements.

The first terminal of the high-side transistor TH is coupled to the high-side input voltage VGH. The second terminal of the high-side transistor TH is connected to the first terminal of the high-side suppression transistor TEH1. The second terminal of the high-side suppression transistor TEH1is connected to a first terminal of the high-side suppression transistor TEH2, a second terminal of the high-side suppression transistor TEH2is connected to a first terminal of the high-side suppression transistor TEH3, and so on. A second terminal of the high-side suppression transistor TEHn is connected to the output terminal PNout of the driver circuit of the display device of the present disclosure. A control terminal of each of the high-side suppression transistors TEH1to TEHn may be connected to the control circuit CTR and controlled by the control circuit CTR.

When the output terminal PNout of the driver circuit of the display device supplies power generated from the high-side input voltage VGH, the control circuit CTR outputs the high-side control signal CRH to the control terminal of the high-side transistor TH for turning on the high-side transistor TH. At the same time, the control circuit CTR outputs the high-side voltage drop suppressing signal to each of the high-side suppression transistors TEH1to TEHn for turning on each of the high-side suppression transistors TEH1to TEHn. As a result, the voltage drop across the first terminal and the second terminal of the high-side transistor TH is reduced.

In the driver circuit of the display device of the third embodiment of the present disclosure, a low-side voltage drop suppressor circuit DVL2includes N transistors as N low-side suppression transistors TEL1to TELn as described herein, wherein N is an integer value being larger than 1 and may depend on the withstand voltage of the low-side transistor TL and other requirements.

The first terminal of the low-side transistor TL is coupled to the low-side input voltage VGL. The second terminal of the low-side transistor TL is connected to the first terminal of the low-side suppression transistor TEL1. A second terminal of the low-side suppression transistor TEL1is connected to a first terminal of the low-side suppression transistor TEL2, a second terminal of the low-side suppression transistor TEL2is connected to a first terminal of the low-side suppression transistor TEL3, and so on. A second terminal of the low-side suppression transistor TELn is connected to the output terminal PNout of the driver circuit of the display device of the present disclosure and the second terminal of the high-side suppression transistor TEHn. A control terminal of each of the low-side suppression transistors TEL1to TELn may be connected to the control circuit CTR and controlled by the control circuit CTR.

When the output terminal PNout of the driver circuit of the display device supplies power generated from the high-side input voltage VGH, the control circuit CTR outputs the low-side control signal CRL to the control terminal of the low-side transistor TL for turning on the low-side transistor TL. At the same time, the control circuit CTR outputs the low-side voltage drop suppressing signal to each of the low-side suppression transistors TEL1to TELn for turning on each of the low-side suppression transistors TEL1to TELn. As a result, the voltage drop across the first terminal and the second terminal of the low-side transistor TL is reduced.

Reference is made toFIG.7, which is a circuit diagram of a driver circuit of a display device according to a fourth embodiment of the present disclosure. The descriptions of the fourth embodiment of the present disclosure that are the same as the descriptions of the first embodiment of the present disclosure are not repeated herein.

The driver circuit of the display device of the fourth embodiment of the present disclosure may further include a high-side voltage modulating circuit MUH.

A first terminal of the high-side voltage modulating circuit MUH may be connected to a high-side voltage source. A voltage that is received from the high-side voltage source by the high-side voltage modulating circuit MUH may be equal to the high-side modulation voltage VSS. The first terminal of the high-side voltage modulating circuit MUH may be coupled to the high-side modulation voltage VSS.

A second terminal of the high-side voltage modulating circuit MUH is connected to a high-side node between the second terminal of the high-side transistor TH and the first terminal of the high-side suppression transistor TEH1.

When the output terminal PNout of the driver circuit of the display device supplies power generated from the low-side input voltage VGL, the control circuit CTR controls the high-side voltage modulating circuit MUH to use the voltage (such as the high-side modulation voltage VSS) supplied by the high-side voltage source to reduce a voltage of the high-side node between the second terminal of the high-side transistor TH and the first terminal of the high-side voltage drop suppressor circuit DVH as shown inFIG.7(or the high-side suppression transistor TEH1as shown inFIG.6). As a result, the voltage drop across the first terminal and the second terminal of the low-side transistor TL is reduced. Therefore, only the low-side transistor TL having the low withstand voltage instead of the high withstand voltage needs to be disposed in the driver circuit of the display device of the present disclosure, thereby reducing circuit costs.

The driver circuit of the display device of the fourth embodiment of the present disclosure may further include a low-side voltage modulating circuit MUL.

A first terminal of the low-side voltage modulating circuit MUL may be connected to a low-side voltage source. The second terminal of the low-side voltage modulating circuit MUL is connected to a low-side node between the second terminal of the low-side transistor TL and the first terminal of the low-side suppression transistor TEL1.

When the output terminal PNout of the driver circuit of the display device supplies power generated from the high-side input voltage VGH, the control circuit CTR controls the low-side voltage modulating circuit MUL to use the voltage (such as the low-side modulation voltage VDD) supplied by the low-side voltage source to increase the voltage of the low-side node between the second terminal of the low-side transistor TL and the first terminal of the low-side voltage drop suppressor circuit DVL as shown inFIG.7(or the low-side suppression transistor TEL1as shown inFIG.6). As a result, the voltage drop across the first terminal and the second terminal of the high-side transistor TH is reduced. Therefore, only the high-side transistor TH having the low withstand voltage instead of the high withstand voltage needs to be disposed in the driver circuit of the display device of the present disclosure, thereby reducing circuit costs.

Reference is made toFIG.8, which is a circuit diagram of a driver circuit of a display device according to a fifth embodiment of the present disclosure. The descriptions of the fifth embodiment of the present disclosure that are the same as the descriptions of the fourth embodiment of the present disclosure are not repeated herein.

In the fifth embodiment, a high-side voltage modulating circuit MUH1of the driver circuit of the display device of the present disclosure includes a transistor as a high-side modulating transistor TMH1as described herein.

A first terminal of the high-side modulating transistor TMH1is connected to the high-side voltage source and receive a modulation voltage (such as the high-side modulation voltage VSS) from the high-side voltage source, or is coupled to the modulation voltage (such as the high-side modulation voltage VSS).

A second terminal of the high-side modulating transistor TMH1is connected to the high-side node between the second terminal of the high-side transistor TH and the first terminal of the high-side suppression transistor TEH1. A control terminal of the high-side modulating transistor TMH1is connected to the control circuit CTR.

When the output terminal PNout of the driver circuit of the display device supplies power generated from the low-side input voltage VGL, the control circuit CTR outputs a high-side modulation signal CMH1to the control terminal of the high-side modulating transistor TMH1for turning on the high-side modulating transistor TMH1.

When the high-side modulating transistor TMH1is turned on, the voltage of the high-side node between the second terminal of the high-side transistor TH and the first terminal of the high-side suppression transistor TEH1is reduced to be equal to or approximate to a modulation voltage (such as the high-side modulation voltage VSS). At this time, the voltage drop across the first terminal and the second terminal of the low-side transistor TL is not higher than the withstand voltage of the low-side transistor TL, and a voltage drop across the first terminal and the second terminal of the low-side suppression transistor TEL1is not higher than a withstand voltage of the low-side suppression transistor TEL1. Therefore, the low-side transistor TL and the low-side suppression transistor TEL1are not damaged due to overvoltage.

In the fifth embodiment of the present disclosure, the high-side voltage modulating circuit MUH1of the driver circuit of the display device of the present disclosure includes a transistor such as a low-side modulating transistor TML1as described herein.

A first terminal of the low-side modulating transistor TML1is connected to the low-side voltage source and receive a modulation voltage (such as the low-side modulation voltage VDD) from the low-side voltage source, or is coupled to the modulation voltage (such as the low-side modulation voltage VDD).

A second terminal of the low-side modulating transistor TML1is connected to the low-side node between the second terminal of the low-side transistor TL and the first terminal of the low-side suppression transistor TEL1. A control terminal of the low-side suppression transistor TEL1is connected to the control circuit CTR.

When the output terminal PNout of the driver circuit of the display device supplies power generated from the high-side input voltage VGH, the control circuit CTR outputs a low-side modulation signal CML1to the control terminal of the low-side modulating transistor TML1for turning on the low-side modulating transistor TML1.

When the low-side modulating transistor TML1is turned on, the voltage of the low-side node between the second terminal of the low-side transistor TL and the first terminal of the low-side suppression transistor TEL1is directly modulated to be equal to or approximate to the modulation voltage (such as the low-side modulation voltage VDD). At this time, the voltage drop across the first terminal and the second terminal of the high-side transistor TH is not higher than the withstand voltage of the high-side transistor TH. A voltage drop across the first terminal and the second terminal of the high-side suppression transistor TEH1is not higher than a withstand voltage of the high-side suppression transistor TEH1. Therefore, the high-side transistor TH and the high-side suppression transistor TEH1are not damaged due to overvoltage.

Reference is made toFIG.9, which is a circuit diagram of a driver circuit of a display device according to a sixth embodiment of the present disclosure. The descriptions of the sixth embodiment of the present disclosure that are the same as the descriptions of the fifth embodiment of the present disclosure are not repeated herein.

As shown inFIG.8, in the fifth embodiment, the first terminal of the high-side modulating transistor TMH1is coupled to the high-side modulation voltage VSS that is a constant voltage, or is connected to a constant voltage source and receives the high-side modulation voltage VSS that is the constant voltage from the constant voltage source.

As shown inFIG.9, in the sixth embodiment, the first terminal of the high-side modulating transistor TMH1is connected to a high-side voltage source PSH that is a variable voltage source. The high-side voltage source PSH may determine the high-side modulation voltage supplied to the first terminal of the high-side modulating transistor TMH1according to the low-side input voltage VGL, the withstand voltage of the low-side transistor TL and other requirements. If necessary, the control circuit CTR may be connected to the high-side voltage source PSH and control the high-side voltage source PSH to supply the high-side modulation voltage to the first terminal of the high-side modulating transistor TMH1.

As shown inFIG.8, in the fifth embodiment, the first terminal of the low-side modulating transistor TML1is coupled to the low-side modulation voltage VDD that is a constant voltage, or is connected to a constant voltage source and receives the low-side modulation voltage VDD that is the constant voltage from the constant voltage source.

As shown inFIG.9, in the sixth embodiment, the first terminal of the low-side suppression transistor TEL1is connected to a low-side voltage source PSL that is a variable voltage source. The low-side voltage source PSL determines the low-side modulation voltage VDD that is supplied from the low-side voltage source PSL to the first terminal of the low-side modulating transistor TML1according to the low-side input voltage VGL and the withstand voltage of the high-side transistor TH and other requirements. If necessary, the control circuit CTR may be connected to the low-side voltage source PSL and may control the low-side voltage source PSL to supply the low-side modulation voltage VDD to the first terminal of the low-side modulating transistor TML1.

Reference is made toFIG.10, which is a circuit diagram of a driver circuit of a display device according to a seventh embodiment of the present disclosure. The descriptions of the seventh embodiment that are the same as the descriptions of the fifth embodiment are not repeated herein.

In the driver circuit of the display device of the seventh embodiment of the present disclosure, a high-side voltage modulating circuit MUH2includes a plurality of high-side modulating transistors TMH1to TMHn, and a low-side voltage modulating circuit MUL2includes a plurality of low-side modulating transistors TML1to TMLn.

If necessary, the driver circuit of the display device of the present disclosure may further include a plurality of high-side switching components SWH1to SWHn and a plurality of low-side switching components SWL1to SWLn.

First terminals of the plurality of high-side modulating transistors TMH1to TMHn may be connected to a plurality of high-side voltage sources supplying different high-side modulation voltages VMH1to VMHn, respectively. Second terminals of the plurality of high-side modulating transistors TMH1to TMHn may be connected to first terminals of the plurality of high-side switching components SWH1to SWHn respectively. A second terminal of each of the plurality of low-side switching components SWL1to SWLn may be connected to the high-side node between the second terminal of the high-side transistor TH and the first terminal of the high-side suppression transistor TEH1.

First terminals of the plurality of low-side modulating transistors TML1to TMLn may be connected to a plurality of low-side voltage sources supplying different low-side modulation voltages VML1to VMLn, respectively. Second terminals of the plurality of low-side modulating transistors TML1to TMLn may be connected to first terminals of the plurality of low-side switching components SWL1to SWLn respectively. A second terminal of each of the plurality of low-side switching components SWL1to SWLn may be connected to the low-side node between the second terminal of the low-side transistor TL and the first terminal of the low-side suppression transistor TEL1.

The control circuit CTR may be connected to a control terminal of each of the plurality of high-side modulating transistors TMH1to TMHn and a control terminal of each of the plurality of low-side modulating transistors TML1to TMLn. The control circuit CTR may output a plurality of high-side modulation signals CMH1to CMHn respectively to the control terminals of the plurality of high-side modulating transistors TMH1to TMHn for controlling operations of the plurality of high-side modulating transistors TMH1to TMHn. The control circuit CTR may output a plurality of low-side modulation signals CML1to CMLn respectively to the control terminals of the plurality of low-side modulating transistors TML1to TMLn for controlling operations of the plurality of low-side modulating transistors TML1to TMLn.

The control circuit CTR may be connected to the control terminal of each of the plurality of high-side switching components SWH1to SWHn and the control terminal of each of the plurality of low-side switching components SWL1to SWLn. The control circuit CTR may control operations of the plurality of high-side switching components SWH1to SWHn and the plurality of low-side switching components SWL1to SWLn.

The control circuit CTR may, according to the withstand voltage of the low-side transistor TL and other requirements, determine which one of the plurality of high-side switching components SWH1to SWHn to turn on, so as to determine which one of the low-side modulation voltages VML1to VMLn that the voltage of the low-side node between the second terminal of the low-side transistor TL and the first terminal of the low-side suppression transistor TEL1is to be reduced to be equal to or approximately equal to.

The control circuit CTR may, according to the withstand voltage of the high-side transistor TH and other requirements, determine which one of the plurality of low-side switching components SWL1to SWLn to turn on so as to determine which one of the high-side modulation voltages VMH1to VMHn that the voltage of the high-side node between the second terminal of the high-side transistor TH and the first terminal of the high-side suppression transistor TEH1is to be reduced to be equal to or approximately equal to.

In practice, the plurality of high-side switching components SWH1to SWHn may be replaced with other switching components such as a multiplexer or other selector circuits, and the plurality of low-side switching components SWL1to SWLn may also be replaced with other switching components such as a multiplexer or other selector circuits, but the present disclosure is not limited thereto.

In conclusion, in the driver circuit of the display device of the present disclosure, the voltage drop suppressor circuits (and the voltage modulating circuits) are disposed for reducing the voltage drop across the first terminal and the second terminal of the transistors. As a result, the transistors of the driver circuit of the display device of the present disclosure are prevented from being damaged to cause abnormalities to the operations of the driver circuit of the display device (such as, but not limited to, the electronic paper) due to overvoltage. Therefore, only the transistors having the low withstand voltages instead of the high withstand voltages need to be disposed in the driver circuit of the display device of the present disclosure, thereby reducing circuit costs.

The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.