Patent ID: 12190961

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments. In the drawings, like reference numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical and electrical changes may be made without departing from the scope of the present disclosure. Unless expressly defined, elements, waveforms and/or other representations of the various figures may not be drawn to scale. The following detailed description is, therefore, not to be taken in a limiting sense.

The term “semiconductor” used herein can refer to, for example, a layer of material, a wafer, or a substrate, and includes any base semiconductor structure. “Semiconductor” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOT) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a semiconductor in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying layers containing such regions/junctions.

The term “conductive” as used herein, as well as its various related forms, e.g., conduct, conductively, conducting, conduction, conductivity, etc., refers to electrically conductive unless otherwise apparent from the context. Similarly, the term “connecting” as used herein, as well as its various related forms, e.g., connect, connected, connection, etc., refers to electrically connecting unless otherwise apparent from the context.

FIG.1is a simplified block diagram of a first apparatus, in the form of a memory (e.g., memory device)100, in communication with a second apparatus, in the form of a processor130, as part of a third apparatus, in the form of an electronic system, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and the like. The processor130, e.g., a controller external to the memory device100, may be a memory controller or other external host device.

Memory device100includes an array of memory cells104logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (commonly referred to as a word line) while memory cells of a logical column are typically selectively connected to the same data line (commonly referred to as a bit line). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells (not shown inFIG.1) of at least a portion of array of memory cells104are capable of being programmed to one of at least two target data states.

A row decode circuitry108and a column decode circuitry110are provided to decode address signals. Address signals are received and decoded to access the array of memory cells104. Memory device100also includes input/output (I/O) control circuitry112to manage input of commands, addresses and data to the memory device100as well as output of data and status information from the memory device100. An address register114is in communication with I/O control circuitry112and row decode circuitry108and column decode circuitry110to latch the address signals prior to decoding. A command register124is in communication with I/O control circuitry112and control logic116to latch incoming commands.

A controller (e.g., the control logic116internal to the memory device100) controls access to the array of memory cells104in response to the commands and generates status information for the external processor130, i.e., control logic116is configured to perform access operations (e.g., sensing operations [which may include read operations and verify operations], programming operations and/or erase operations) on the array of memory cells104, and might be configured to perform methods in accordance with embodiments. The control logic116is in communication with row decode circuitry108and column decode circuitry110to control the row decode circuitry108and column decode circuitry110in response to the addresses.

Control logic116is also in communication with a cache register118. Cache register118latches data, either incoming or outgoing, as directed by control logic116to temporarily store data while the array of memory cells104is busy writing or reading, respectively, other data. During a programming operation (e.g., write operation), data may be passed from the cache register118to the data register120for transfer to the array of memory cells104; then new data may be latched in the cache register118from the I/O control circuitry112. During a read operation, data may be passed from the cache register118to the I/O control circuitry112for output to the external processor130; then new data may be passed from the data register120to the cache register118. The cache register118and/or the data register120may form (e.g., may form a portion of) a page buffer of the memory device100. A page buffer may further include sensing devices (not shown inFIG.1) to sense a data state of a memory cell of the array of memory cells104, e.g., by sensing a state of a data line connected to that memory cell. A status register122may be in communication with I/O control circuitry112and control logic116to latch the status information for output to the processor130.

Memory device100receives control signals at control logic116from processor130over a control link132. The control signals might include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, a write enable WE #, a read enable RE #, and a write protect WP #. Additional or alternative control signals (not shown) may be further received over control link132depending upon the nature of the memory device100. Memory device100receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from processor130over a multiplexed input/output (I/O) bus134and outputs data to processor130over I/O bus134.

For example, the commands may be received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and may then be written into command register124. The addresses may be received over input/output (I/O) pins [7:0] of I/O bus134at I/O control circuitry112and may then be written into address register114. The data may be received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry112and then may be written into cache register118. The data may be subsequently written into data register120for programming the array of memory cells104. For another embodiment, cache register118may be omitted, and the data may be written directly into data register120. Data may also be output over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device. Although reference may be made to I/O pins, they may include any conductive node providing for electrical connection to the memory device100by an external device (e.g., processor130), such as conductive pads or conductive bumps as are commonly used.

It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device100ofFIG.1has been simplified. It should be recognized that the functionality of the various block components described with reference toFIG.1may not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component ofFIG.1. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component ofFIG.1.

Additionally, while specific I/O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I/O pins (or other I/O node structures) may be used in the various embodiments.

FIG.2Ais a schematic of a portion of an array of memory cells200A, such as a NAND memory array, as could be used in a memory of the type described with reference toFIG.1, e.g., as a portion of array of memory cells104. Memory array200A includes access lines, such as word lines2020to202N, and data lines, such as bit lines2040to204M. The word lines202may be connected to global access lines (e.g., global word lines), not shown inFIG.2A, in a many-to-one relationship. For some embodiments, memory array200A may be formed over a semiconductor that, for example, may be conductively doped to have a conductivity type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

Memory array200A might be arranged in rows (each corresponding to a word line202) and columns (each corresponding to a bit line204). Each column may include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings2060to206M. Each NAND string206might be connected (e.g., selectively connected) to a common source (SRC)216and might include memory cells2080to208N. The memory cells208may represent non-volatile memory cells for storage of data. Some of the memory cells208might represent dummy memory cells, e.g., memory cells not intended to store user data. Dummy memory cells are typically not accessible to a user of the memory, and are typically incorporated into the NAND string206for operational advantages, as are well understood.

The memory cells208of each NAND string206might be connected in series between a select gate210(e.g., a field-effect transistor), such as one of the select gates2100to210M(e.g., that may be source select transistors, commonly referred to as select gate source), and a select gate212(e.g., a field-effect transistor), such as one of the select gates2120to212M(e.g., that may be drain select transistors, commonly referred to as select gate drain). Select gates2100to210Mmight be commonly connected to a select line214, such as a source select line (SGS), and select gates2120to212Mmight be commonly connected to a select line215, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates210and212may utilize a structure similar to (e.g., the same as) the memory cells208. The select gates210and212might represent a plurality of select gates connected in series, with each select gate in series configured to receive a same or independent control signal. A control gate of each select gate210might be connected to select line214. A control gate of each select gate212might be connected to select line215.

The select gates210for each NAND string206might be connected in series between its memory cells208and a GIDL (gate-induced drain leakage) generator gate218(e.g., a field-effect transistor), such as one of the GIDL generator (GG) gates2180to218M. The GG gates2180to218Mmight be referred to as source GG gates. The source GG gates2180to218Mmight each be connected (e.g., directly connected) to the source216, and selectively connected to their respective NAND strings2060to206M. Alternatively, a source select gate210and its GG gate218might represent a single gate, e.g., connected (e.g., directly connected) to the source216, and connected (e.g., directly connected) to a respective NAND string206. The select gates212of each NAND string206might be connected in series between its memory cells208and a GG gate220(e.g., a field-effect transistor), such as one of the GG gates2200to220M. The GG gates2200to220Mmight be referred to as drain GG gates. The drain GG gates2200to220Mmight be connected (e.g., directly connected) to their respective data lines2040to204M, and selectively connected to their respective NAND strings2060to206M. Alternatively, a drain select gate212and its GG gate220might represent a single gate, e.g., connected (e.g., directly connected) to a respective data line204, and connected (e.g., directly connected) to a respective NAND string206.

GG gates2180to218Mmight be commonly connected to a control line222, such as an SGS_GG control line, and GG gates2200to220Mmight be commonly connected to a control line224, such as an SGD_GG control line. Although depicted as traditional field-effect transistors, the GG gates218and220may utilize a structure similar to (e.g., the same as) the memory cells208. The GG gates218and220might represent a plurality of GG gates connected in series, with each GG gate in series configured to receive a same or independent control signal. In general, the GG gates218and220may have threshold voltages different than (e.g., lower than) the threshold voltages of the select gates210and212, respectively. Threshold voltages of the source GG gates218might be different than (e.g., higher than) threshold voltages of the drain GG gates220. Threshold voltages of the GG gates218and220may be of an opposite polarity than, and/or may be lower than, threshold voltages of the select gates210and212. For example, the select gates210and212might have positive threshold voltages (e.g., 2V to 4V), while the GG gates218and220might have negative threshold voltages (e.g., −1V to −4V). The GG gates218and220might be provided to assist in the generation of GIDL current into a channel region of their corresponding NAND string206during an erase operation, for example.

A source of each GG gate218might be connected to common source216. The drain of each GG gate218might be connected to a select gate210of the corresponding NAND string206. For example, the drain of GG gate2180might be connected to the source of select gate2100of the corresponding NAND string2060. Therefore, in cooperation, each select gate210and GG gate218for a corresponding NAND string206might be configured to selectively connect that NAND string206to common source216. A control gate of each GG gate218might be connected to control line222.

The drain of each GG gate220might be connected to the bit line204for the corresponding NAND string206. For example, the drain of GG gate2200might be connected to the bit line2040for the corresponding NAND string2060. The source of each GG gate220might be connected to a select gate212of the corresponding NAND string206. For example, the source of GG gate2200might be connected to select gate2120of the corresponding NAND string2060. Therefore, in cooperation, each select gate212and GG gate220for a corresponding NAND string206might be configured to selectively connect that NAND string206to the corresponding bit line204. A control gate of each GG gate220might be connected to control line224.

The memory array inFIG.2Amight be a quasi-two-dimensional memory array and might have a generally planar structure, e.g., where the common source216, NAND strings206and bit lines204extend in substantially parallel planes. Alternatively, the memory array inFIG.2Amight be a three-dimensional memory array, e.g., where NAND strings206may extend substantially perpendicular to a plane containing the common source216and to a plane containing the bit lines204that may be substantially parallel to the plane containing the common source216.

Typical construction of memory cells208includes a data-storage structure234(e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate236, as shown inFIG.2A. The data-storage structure234may include both conductive and dielectric structures while the control gate236is generally formed of one or more conductive materials. In some cases, memory cells208may further have a defined source/drain (e.g., source)230and a defined source/drain (e.g., drain)232. Memory cells208have their control gates236connected to (and in some cases form) a word line202.

A column of the memory cells208may be a NAND string206or a plurality of NAND strings206selectively connected to a given bit line204. A row of the memory cells208may be memory cells208commonly connected to a given word line202. A row of memory cells208can, but need not, include all memory cells208commonly connected to a given word line202. Rows of memory cells208may often be divided into one or more groups of physical pages of memory cells208, and physical pages of memory cells208often include every other memory cell208commonly connected to a given word line202. For example, memory cells208commonly connected to word line202Nand selectively connected to even bit lines204(e.g., bit lines2040,2042,2044, etc.) may be one physical page of memory cells208(e.g., even memory cells) while memory cells208commonly connected to word line202Nand selectively connected to odd bit lines204(e.g., bit lines2041,2043,2045, etc.) may be another physical page of memory cells208(e.g., odd memory cells). Although bit lines2043-2045are not explicitly depicted inFIG.2A, it is apparent from the figure that the bit lines204of the array of memory cells200A may be numbered consecutively from bit line2040to bit line204M. Other groupings of memory cells208commonly connected to a given word line202may also define a physical page of memory cells208. For certain memory devices, all memory cells commonly connected to a given word line might be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) might be deemed a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as all memory cells connected to word lines2020-202N(e.g., all NAND strings206sharing common word lines202). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells.

Although the example ofFIG.2Ais discussed in conjunction with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS or other data storage structure configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

FIG.2Bis another schematic of a portion of an array of memory cells200B as could be used in a memory of the type described with reference toFIG.1, e.g., as a portion of array of memory cells104. Like numbered elements inFIG.2Bcorrespond to the description as provided with respect toFIG.2A.FIG.2Bprovides additional detail of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array200B may incorporate vertical structures which may include semiconductor pillars where a portion of a pillar may act as a body and a channel region of the memory cells of NAND strings206. The NAND strings206may be each selectively connected to a bit line2040-204Mby a select transistor212(e.g., that may be drain select transistors, commonly referred to as select gate drain) and to a common source216by a select transistor210(e.g., that may be source select transistors, commonly referred to as select gate source). Multiple NAND strings206might be selectively connected to the same bit line204. Subsets of NAND strings206can be connected to their respective bit lines204by biasing the select lines2150-215Kto selectively activate particular select transistors212each between a NAND string206and a bit line204. The select transistors210can be activated by biasing the select line214. Each word line202may be connected to multiple rows of memory cells of the memory array200B. Rows of memory cells that are commonly connected to each other by a particular word line202may collectively be referred to as tiers.

The three-dimensional NAND memory array200B might be formed over peripheral circuitry226. The peripheral circuitry226might represent a variety of circuitry for accessing the memory array200B. The peripheral circuitry226might include complementary circuit elements. For example, the peripheral circuitry226might include both n-channel and p-channel transistors formed on a same semiconductor substrate, a process commonly referred to as CMOS, or complementary metal-oxide-semiconductors. Although CMOS often no longer utilizes a strict metal-oxide-semiconductor construction due to advancements in integrated circuit fabrication and design, the CMOS designation remains as a matter of convenience.

FIG.3is a cross-sectional view of strings of series-connected memory cells as could be used in a memory of the type described with reference toFIG.1. Three-dimensional memory arrays are typically fabricated by forming alternating layers of conductors and dielectrics, forming holes in these layers, forming additional materials on sidewalls of the holes to define gate stacks for memory cells and other gates, and subsequently filling the holes with a semiconductor material to define a pillar to act as bodies (e.g., channel regions) of the memory cells and select gates. To improve conductivity of pillars and an adjacent semiconductor material, e.g., upon which they are formed, a conductive (e.g., conductively-doped) portion is typically formed in the hole at an interface with the adjacent semiconductor material. These conductive portions are typically formed of a different conductivity type than the pillar and adjacent semiconductor material. For example, if the pillar is formed of a P-type semiconductor material, the conductive portion might have an N-type conductivity.FIG.3depicts a basic structure of strings of series-connected memory cells formed in this manner. InFIG.3, two strings of series-connected memory cells (e.g., NAND strings) are depicted in the cross-sectional view. It is noted that the spaces between various elements of the figure may represent dielectric material.

With reference toFIG.3, a first NAND string includes a first pillar3400. The first pillar3400may be formed of a semiconductor material of a first conductivity type, such as a P-type polysilicon. Conductive portion3420may be formed at the bottom of the pillar3400, with the conductive portion3420electrically connected to the source216. The conductive portion3420may be formed of a semiconductor material of a second conductivity type different than the first conductivity type. For the example where the first pillar3400might be formed of a P-type polysilicon, the conductive portion3420might be formed of an N-type semiconductor material, such as an N-type polysilicon. In addition, the conductive portion3420might have a higher conductivity level than the pillar3400. For example, the conductive portion3420might have an N+ conductivity. Alternatively, the conductive portion3420may be formed of a conductor, e.g., a metal or metal silicide.

The pillar3400is electrically connected to the data line204through a conductive plug3440. The conductive plug3440, in this example, might also be formed of a semiconductor material of the second conductivity type, and may likewise have a higher conductivity level than the pillar3400. Alternatively, the conductive plug3440may be formed of a conductor, e.g., a metal or metal silicide. The first NAND string further includes a source GG gate at an intersection of the control line222and the pillar3400, and a drain GG gate at an intersection of the control line2240and the pillar3400. The first NAND string further includes a source select gate at an intersection of the source select line214and the pillar3400, and a drain select gate at an intersection of the drain select line2150and the pillar3400. The first NAND string further includes a memory cell at an intersection of each of the access lines2020-2027and the pillar3400. These memory cells further include data-storage structures23400-23470. While the structure ofFIG.3is depicted to include only eight access lines202in an effort to improve readability of the figure, a typical NAND structure might have significantly more access lines202.

Although not all numbered, for clarity ofFIG.3, data-storage structures234are depicted on both sides of the pillars340. Individual data-storage structures234may wrap completely around their respective pillar340, thus defining a data-storage structure234for a single memory cell. Alternatively, structures are known having segmented data-storage structures234, such that more than one (e.g., two) memory cells are defined at each intersection of an access line202and a pillar340. Embodiments described herein are independent of the number of memory cells defined around a pillar340. However, an example of a segmented data storage structure might be found in U.S. Pat. No. 7,906,818 to Pekny.

With further reference toFIG.3, a second NAND string includes the second pillar3401. The second pillar3401may be formed of a semiconductor material of the first conductivity type, such as a P-type polysilicon. Conductive portion3421may be formed at the bottom of the pillar3401with the conductive portion3421electrically connected to the source216. The conductive portion3421may be formed of a semiconductor material of the second conductivity type. For the example where the pillar3401might be formed of a P-type polysilicon, the conductive portion3421might be formed of an N-type semiconductor material, such as an N-type polysilicon. In addition, the conductive portion3421might have a higher conductivity level than the pillar3401. For example, the conductive portion3421might have an N+ conductivity.

The pillar3401is electrically connected to the data line204through a conductive plug3441. The conductive plug3441, in this example, might also be formed of a semiconductor material of the second conductivity type, and may likewise have a higher conductivity level than the pillar3401. Alternatively, the conductive plug3441may be formed of a conductor, e.g., a metal or metal silicide. The second NAND string further includes a source GG gate at an intersection of the control line222and the pillar3401, and a drain GG gate at an intersection of the control line2241and the pillar3401. The second NAND string further includes a source select gate at an intersection of the source select line214and the pillar3401, and a drain select gate at an intersection of the drain select line2151and the pillar3401. The second NAND string further includes a memory cell at an intersection of each of the access lines2020-2027and the pillar3401. These memory cells further include data-storage structures23401-23471.

Forming holes through multiple layers typically produces holes of decreasing diameter toward the bottom of the holes due to the nature of the removal processes commonly used in the semiconductor industry. To mitigate against the holes becoming too narrow, formation of arrays of the type described with reference toFIGS.2A-2B, might be segmented, such that the layers for forming a first portion of the NAND string may be formed, then portions may be removed to define holes, and the remaining structures may be formed within the holes. Following formation of the first portion of the NAND string, a second portion of the NAND string might be formed over the first portion in a similar manner. Although the embodiments are not dependent on the nature of the array structure, an example of a segmented array structure might be found in U.S. Pat. No. 10,049,750 to Sakui et al.

Typically, an erase operation on memory cells of NAND strings includes a series of erase pulses (e.g., Pulse 1, Pulse 2, Pulse 3, . . . ) applied to the NAND strings through their respective data lines204and source216while voltages are applied to the access lines202having a polarity and magnitude expected to remove charge from the data storage structures of the memory cells while the erase pulse is applied to the NAND strings. An erase verify operation may be performed between pulses to determine if the memory cells have been sufficiently erased (e.g., have threshold voltages at or below some target value). If the erase verify is failed, another erase pulse, typically having a higher voltage level, may be applied.

Erase operations typically utilize GIDL (gate-induced drain leakage) to provide current to the pillars340, e.g., to the bodies of the memory cells, sufficient to sustain the erase operation. GIDL current might be produced by applying a voltage level of the control lines222and/or224that is less than the voltage levels applied to the data lines204and the source216. Due to differing characteristics at opposing ends of the NAND string, the voltage level applied to the control line222for the source GG gate may be different than the voltage level applied to the control line224for the drain GG gate, even where the data line204and the source216receive the same voltage level.

Although different voltage levels might be applied to the control line222and the control line224, the voltage differential from the source216and the data line204, respectively, might be chosen to be substantially equal (e.g., equal) to facilitate similar (e.g., equal) levels of GIDL current. For example, the voltage level applied to the control line222might be 5V less than the voltage level applied to the source216, and the voltage levels applied to the control line224might be 5V less than the voltage level applied to the data line204. Voltage levels applied to select lines214or215might be selected to reduce stress during the erase operation, and thus might have some value between the voltage level applied to the control line for the corresponding GG gate, e.g., control lines222or224, respectively, and the voltage level applied to the source216or data line204, respectively. Selection of the various voltage levels may generally be dependent upon the array architecture, materials of construction and/or processing conditions, and is within the abilities of one of ordinary skill in the art of semiconductor fabrication. Table 1 provides some example voltage levels that might be used with embodiments.

TABLE 1Pulse 1Pulse 2Pulse 3Data Line 20415 V17 V19 VControl Line 22410 V12 V14 VAccess Lines 2021 V1 V1 VControl Line 22210 V12 V14 VSource 21615 V17 V19 V

While the example of Table 1 shows the same voltage differences being applied between the source216and the control line222, and between the data lines204and the control line224for each erase pulse, due to the differing characteristics, the voltage differences for opposing ends of the NAND string might be different. For example, the voltage difference between the voltage level applied to the control line222and the voltage level applied to the source216might be different than (e.g., greater than) the voltage difference between the voltage level applied to the control line224and the voltage level applied to a data line204.

The GIDL current generated by the voltage differential between the source216and control line222, and/or between the data line204and the control line224, might depend exponentially on the magnitude of the voltage differential, which may be referred to as offset. For example, higher offset might produce higher levels of GIDL current. However, higher levels of offset might also lead to degradation of the GG gates.

FIG.4Aconceptually depicts waveforms of voltage levels for generating GIDL current of the related art. InFIG.4A, the waveform460might represent the voltage level applied to the source216(or data line204), the waveform462might represent the voltage level applied to the control line222(or control line224), and the waveform464might represent the voltage difference between the waveform462and the waveform460. The waveform460might represent an erase pulse of an erase operation.

At time t0, the voltage level of the waveform460might begin increasing (e.g., ramping) from an initial voltage level463(e.g., ground or 0V) while the voltage level of the waveform462might remain at the initial voltage level. As a result, the voltage difference of the waveform464might begin increasing in magnitude. After time period466, the voltage difference of the waveform464might reach a target (e.g., desired) magnitude461, and the voltage level of the waveform462might begin increasing from the initial voltage level at a same rate (e.g., a same ramp rate) as the rate of increase of the voltage level of the waveform460to maintain the magnitude461of the voltage difference of the waveform464.

After time period468, the voltage level of the waveform460might reach a target (e.g., desired) voltage level467to perform the erase operation. At this time, the voltage levels of the waveforms460and462might be maintained, e.g., by ceasing increasing their respective voltage levels. In reference toFIG.4A, the desired levels of GIDL current might only be produced after the end of time period466when the magnitude461of the voltage difference of the waveform464reaches its target level.

During the time period466, the GG gates might develop high longitudinal E-fields to compensate for displacement current, which might be equal to the ramp rate of the voltage level of the waveform460times a capacitance of its corresponding semiconductor pillar340. To reduce damage from such E-fields, the ramp rate can be reduced. Once the magnitude461of the voltage difference of the waveform464reaches its target level, desired levels of GIDL current can be produced with lower longitudinal fields and the voltage level of the corresponding semiconductor pillar340can more easily follow the voltage level of the source216(or data line204).

FIG.4Bconceptually depicts waveforms of voltage levels for generating GIDL current in accordance with an embodiment. InFIG.4B, the waveform470might represent the voltage level applied to the source216(or data line204), the waveform472might represent the voltage level applied to the control line222(or control line224), and the waveform474might represent the voltage difference between the waveform472and the waveform470.

At time t0, the voltage level of the waveform470might begin increasing (e.g., ramping) from a first (e.g., initial) voltage level473(e.g., ground or 0V). The voltage level of the waveform472might begin increasing from a second (e.g., initial) voltage level475, lower than the first voltage level473of the waveform470, e.g., a negative voltage level. The voltage difference between the second voltage level475and the first voltage level473might be selected to be substantially equal to (e.g., equal to) the desired level of offset. As a result, the voltage difference of the waveform474might reach its target (e.g., desired) magnitude471at, or near, time0. The voltage level of the waveform472might begin increasing from the second voltage level475at a same rate (e.g., a same ramp rate) as the rate of increase of the voltage level of the waveform470to maintain the magnitude471of the voltage difference of the waveform474.

After time period478, the voltage level of the waveform470might reach a target (e.g., desired) voltage level477to perform the erase operation. At this time, the voltage levels of the waveforms470and472might be maintained, e.g., by ceasing increasing their respective voltage levels. In reference toFIG.4B, the desired levels of GIDL current might be produced for an entire duration of an erase pulse, or for a longer portion of the duration of the erase pulse as compared to the example ofFIG.4A. As such, exposure to high longitudinal E-fields might be mitigated. This might further facilitate higher ramp rates of the erase pulse, and/or higher levels of offset, which could shorten the duration of an erase operation

Voltage levels of the type discussed with reference toFIG.4Bare often generated using voltage generation systems using digital to analog conversion. For example, a ramping voltage level might be produced responsive to a counter.FIG.5is a depiction of a ramped voltage level546for use with various embodiments. The ramped (e.g., increasing) voltage level has a voltage level (e.g., changing voltage level) that is responsive to a count. For example, as values of the counts increase, the voltage level of the ramped voltage level increases in response. The ramped voltage level546may approximate, or more closely approximate, a linear response by increasing the number of counts used to generate a same ranges of voltage levels.

FIG.6is a block diagram of a voltage generation system for generating a ramped voltage level of the type depicted inFIG.5for use with various embodiments. The voltage generation system ofFIG.6includes a counter641for producing a count. As an example, the counter641may have an output643for providing a bit pattern representative of the count. A voltage generation circuit645, e.g., a digital-to-analog converter (DAC), might produce an analog voltage level responsive to the output643of the counter641, e.g., the count. The DAC645might provide this voltage level at the output647. The output647of the DAC645might be connected (e.g., selectively connected) to a source216and/or a data line204.

FIG.7Aconceptually depicts waveforms of voltage levels for generating GIDL current in accordance with another embodiment.FIG.7Amight represent voltage levels applied during an erase operation. InFIG.7A, the waveform770might represent the voltage level applied to the source216(or data line204), and the waveform772might represent the voltage level applied to the control line222(or control line224). The waveform770might represent an erase pulse of the erase operation. The source216and the data lines204might each be referred to as a node selectively connected a string of series-connected memory cells, while the GG gates corresponding to the control line222and224, respectively, might be referred to as being connected between their corresponding node (e.g., the source216or a data line204, respectively) and their corresponding string of series-connected memory cells, which might include being connected to (e.g., directly connected to) their corresponding node (e.g., the source216or a data line204, respectively) and selectively connected to their corresponding string of series-connected memory cells.

At time t0, waveform770and waveform772might each be at an initial voltage level, e.g., 0V. Also at time t0, for the time period t0-t1, the voltage level of the waveform770might be increased to a voltage level7800, which might have a magnitude782above the initial voltage level, and the voltage level of the waveform772might be decreased to a voltage level7840, which might have a magnitude786below the initial voltage level. A sum of the magnitude782and the magnitude786might be equal to the desired offset for the erase operation.

At time t1, for the time period t1-t2, the voltage level of the waveform770might be increased to a voltage level7801and the voltage level of the waveform772might be increased to a voltage level7841. The magnitude of the voltage level increase of the waveform770for the time period t1-t2might be equal to a difference between the voltage level7801and the voltage level7800, while the magnitude of the voltage level increase of the waveform772for the time period t1-t2might be equal to a difference between the voltage level7841and the voltage level7840. The magnitude of the voltage level increase of the waveform770for the time period t1-t2might be equal to the magnitude of the voltage level increase of the waveform772for the time period t1-t2, such that the rate of increase might be deemed to be the same.

At time t2, for the time period t2-t3, the voltage level of the waveform770might be increased to a voltage level7802and the voltage level of the waveform772might be increased to a voltage level7842. The magnitude of the voltage level increase of the waveform770for the time period t2-t3might be equal to a difference between the voltage level7802and the voltage level780\1, while the magnitude of the voltage level increase of the waveform772for the time period t2-t3might be equal to a difference between the voltage level7842and the voltage level7841. The magnitude of the voltage level increase of the waveform770for the time period t2-t3might be equal to the magnitude of the voltage level increase of the waveform772for the time period t2-t3, such that the rate of increase might be deemed to be the same.

At time t3, for the time period t3-t4, the voltage level of the waveform770might be increased to a voltage level780Xand the voltage level of the waveform772might be increased to a voltage level784X. The magnitude of the voltage level increase of the waveform770for the time period t3-t4might be equal to a difference between the voltage level780Xand the voltage level7802, while the magnitude of the voltage level increase of the waveform772for the time period t3-t4might be equal to a difference between the voltage level784Xand the voltage level784X. The magnitude of the voltage level increase of the waveform770for the time period t3-t4might be equal to the magnitude of the voltage level increase of the waveform772for the time period t3-t4, such that the rate of increase might be deemed to be the same. The steps of the waveforms770and772for the time period t3-t4are depicted as dashed lines to represent that more than one step of the applied voltage level might occur between time t3and time4

At time t4, for the time period t4-t5, the voltage level of the waveform770might be increased to a voltage level780N-2and the voltage level of the waveform772might be increased to a voltage level784N-2. The magnitude of the voltage level increase of the waveform770for the time period t4-t5might be equal to a difference between the voltage level780N-2and the voltage level780X, while the magnitude of the voltage level increase of the waveform772for the time period t4-t5might be equal to a difference between the voltage level784N-2and the voltage level784X. The magnitude of the voltage level increase of the waveform770for the time period t4-t5might be equal to the magnitude of the voltage level increase of the waveform772for the time period t4-t5, such that the rate of increase might be deemed to be the same.

At time t5, for the time period t5-t6, the voltage level of the waveform770might be increased to a voltage level780N-1and the voltage level of the waveform772might be increased to a voltage level784N-1. The magnitude of the voltage level increase of the waveform770for the time period t5-t6might be equal to a difference between the voltage level780N-1and the voltage level780N-2, while the magnitude of the voltage level increase of the waveform772for the time period t5-t6might be equal to a difference between the voltage level784N-1and the voltage level784N-2. The magnitude of the voltage level increase of the waveform770for the time period t5-t6might be equal to the magnitude of the voltage level increase of the waveform772for the time period t5-t6, such that the rate of increase might be deemed to be the same.

At time t6, for the time period t6-t7, the voltage level of the waveform770might be increased to a voltage level780Nand the voltage level of the waveform772might be increased to a voltage level784N. The magnitude of the voltage level increase of the waveform770for the time period t6-t7might be equal to a difference between the voltage level780Nand the voltage level780N-1, while the magnitude of the voltage level increase of the waveform772for the time period t6-t7might be equal to a difference between the voltage level784Nand the voltage level784N-1. The magnitude of the voltage level increase of the waveform770for the time period t6-t7might be equal to the magnitude of the voltage level increase of the waveform772for the time period t6-t7, such that the rate of increase might be deemed to be the same.

At time t7, when the waveform770has the voltage level780N, increases in the voltage levels of the waveforms770and772might be ceased. During the time period t7-t8, a voltage level might be applied to a control gate of a memory cell208of a string of series-connected memory cells selectively connected to the source216(or a data line204) that might be expected to remove charge from a data storage structure of the memory cell, e.g., in conjunction with the voltage level780Napplied to the source216(or a data line204). At time t8, voltage levels of the waveforms770and772might be discharged, e.g., to the initial voltage level. An erase verify operation might then be performed to determine whether the memory cells are sufficiently erased, or whether another, e.g., higher, erase pulse might be applied.

The slope of a voltage level increase for a particular time period, e.g., t1-t2, t2-t3, t3-t4, etc. between time t1and time t7, might be defined as the magnitude of the voltage level increase for that time period divided by a duration of that time period. The slopes of the voltage level increases for the successive time periods t1-t2, t2-t3, t3-t4, etc., might be equal, such that the rate of increase might be deemed to be constant. For some embodiments, the magnitudes and durations of these time periods might also be equal. Alternatively, the slopes of the voltage level increases for the successive time periods t1-t2, t2-t3, t3-t4, etc., might include a plurality of different slope values, such that the rate of increase might be deemed to be variable.

FIG.7Bconceptually depicts waveforms of voltage levels for generating GIDL current in accordance with a further embodiment.FIG.7Bmight represent voltage levels applied during an erase operation. InFIG.7B, the waveform770might represent the voltage level applied to the source216(or data line204), and the waveform772might represent the voltage level applied to the control line222(or control line224). The waveform770might represent an erase pulse of the erase operation. The source216and the data lines204might each be referred to as a node selectively connected a string of series-connected memory cells, while the GG gates corresponding to the control line222and224, respectively, might be referred to as being connected to (e.g., directly connected to) their corresponding node (e.g., the source216or a data line204, respectively) and selectively connected to their corresponding string of series-connected memory cells.

At time ti, waveform770and waveform772might each be at an initial voltage level, e.g., 0V. Also at time ti, for the time period ti-t0, the voltage level of the waveform770might be maintained at the initial voltage level, and the voltage level of the waveform772might be decreased to a voltage level784i, which might have a magnitude771below the initial voltage level. The magnitude771might be equal to the desired offset for the erase operation.

At time to, for the time period t0-t1, the voltage level of the waveform770might be increased to a voltage level7800, which might have a magnitude782above the initial voltage level, and the voltage level of the waveform772might be increased to a voltage level7840, which might have the magnitude782above the voltage level784i, such that the rate of increase of the waveforms770and772might be deemed to be the same for the time period t0-t1.

At time t1, for the time period t1-t2, the voltage level of the waveform770might be increased to a voltage level780, and the voltage level of the waveform772might be increased to a voltage level7841. The magnitude of the voltage level increase of the waveform770for the time period t1-t2might be equal to a difference between the voltage level780, and the voltage level7800, while the magnitude of the voltage level increase of the waveform772for the time period t1-t2might be equal to a difference between the voltage level7841and the voltage level7840. The magnitude of the voltage level increase of the waveform770for the time period t1-t2might be equal to the magnitude of the voltage level increase of the waveform772for the time period t1-t2, such that the rate of increase might be deemed to be the same.

At time t2, for the time period t2-t3, the voltage level of the waveform770might be increased to a voltage level7802and the voltage level of the waveform772might be increased to a voltage level7842. The magnitude of the voltage level increase of the waveform770for the time period t2-t3might be equal to a difference between the voltage level7802and the voltage level780\1, while the magnitude of the voltage level increase of the waveform772for the time period t2-t3might be equal to a difference between the voltage level7842and the voltage level7841. The magnitude of the voltage level increase of the waveform770for the time period t2-t3might be equal to the magnitude of the voltage level increase of the waveform772for the time period t2-t3, such that the rate of increase might be deemed to be the same.

At time t3, for the time period t3-t4, the voltage level of the waveform770might be increased to a voltage level780Xand the voltage level of the waveform772might be increased to a voltage level784X. The magnitude of the voltage level increase of the waveform770for the time period t3-t4might be equal to a difference between the voltage level780Xand the voltage level7802, while the magnitude of the voltage level increase of the waveform772for the time period t3-t4might be equal to a difference between the voltage level784Xand the voltage level784X. The magnitude of the voltage level increase of the waveform770for the time period t3-t4might be equal to the magnitude of the voltage level increase of the waveform772for the time period t3-t4, such that the rate of increase might be deemed to be the same. The steps of the waveforms770and772for the time period t3-t4are depicted as dashed lines to represent that more than one step of the applied voltage level might occur between time t3and time4

At time t4, for the time period t4-t5, the voltage level of the waveform770might be increased to a voltage level780N-2and the voltage level of the waveform772might be increased to a voltage level784N-2. The magnitude of the voltage level increase of the waveform770for the time period t4-t5might be equal to a difference between the voltage level780N-2and the voltage level780X, while the magnitude of the voltage level increase of the waveform772for the time period t4-t5might be equal to a difference between the voltage level784N-2and the voltage level784X. The magnitude of the voltage level increase of the waveform770for the time period t4-t5might be equal to the magnitude of the voltage level increase of the waveform772for the time period t4-t5, such that the rate of increase might be deemed to be the same.

At time t5, for the time period t5-t6, the voltage level of the waveform770might be increased to a voltage level780N-1and the voltage level of the waveform772might be increased to a voltage level784N-1. The magnitude of the voltage level increase of the waveform770for the time period t5-t6might be equal to a difference between the voltage level780N-1and the voltage level780N-2, while the magnitude of the voltage level increase of the waveform772for the time period t5-t6might be equal to a difference between the voltage level784N-1and the voltage level784N-2. The magnitude of the voltage level increase of the waveform770for the time period t5-t6might be equal to the magnitude of the voltage level increase of the waveform772for the time period t5-t6, such that the rate of increase might be deemed to be the same.

At time t6, for the time period t6-t7, the voltage level of the waveform770might be increased to a voltage level780Nand the voltage level of the waveform772might be increased to a voltage level784N. The magnitude of the voltage level increase of the waveform770for the time period t6-t7might be equal to a difference between the voltage level780Nand the voltage level780N-1, while the magnitude of the voltage level increase of the waveform772for the time period t6-t7might be equal to a difference between the voltage level784Nand the voltage level784N-1. The magnitude of the voltage level increase of the waveform770for the time period t6-t7might be equal to the magnitude of the voltage level increase of the waveform772for the time period t6-t7, such that the rate of increase might be deemed to be the same.

At time t7, when the waveform770has the voltage level780N, increases in the voltage levels of the waveforms770and772might be ceased. During the time period t7-t8, a voltage level might be applied to a control gate of a memory cell208of a string of series-connected memory cells selectively connected to the source216(or a data line204) that might be expected to remove charge from a data storage structure of the memory cell, e.g., in conjunction with the voltage level780Napplied to the source216(or a data line204). At time t8, voltage levels of the waveforms770and772might be discharged, e.g., to the initial voltage level. An erase verify operation might then be performed to determine whether the memory cells are sufficiently erased, or whether another, e.g., higher, erase pulse might be applied.

The slope of a voltage level increase for a particular time period, e.g., t0-t1, t1-t2, t2-t3, etc. between time t0and time t7, might be defined as the magnitude of the voltage level increase for that time period divided by a duration of that time period. The slopes of the voltage level increases for the successive time periods t0-t1, t1-t2, t2-t3, etc., might be equal, such that the rate of increase might be deemed to be constant. Alternatively, the slopes of the voltage level increases for the successive time periods t0-t1, t1-t2, t2-t3, etc., might include a plurality of different slope values, such that the rate of increase might be deemed to be variable. For some embodiments, the magnitudes and durations of these time periods might vary. For example, the slope of the voltage level increase for the time period t0-t1(e.g., a first time period of a plurality of successive time periods) might be different than (e.g., greater than) the slope of the voltage level increase for the time period t1-t2. For some embodiments, the slope of each time period of the plurality of successive time periods other than the first time period of the plurality of successive time periods might be equal.

FIG.8is a flowchart of a method of operating a memory in accordance with an embodiment. For example, the method ofFIG.8might represent a portion of an erase operation.

At801, a positive first voltage level might be applied to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected to the first node and selectively connected to the string of series-connected memory cells. As an example, with reference toFIG.2A, the first voltage level might be applied to the source216while the second voltage level might be applied to the control line222. Alternatively, the first voltage level might be applied to the data line2040while the second voltage level might be applied to the control line224. A voltage difference between the first voltage level and the second voltage level might be equal to the desired offset for the erase operation. This action might correspond to the voltage level of waveform770at time t1ofFIG.7AorFIG.7B, and to the voltage level of waveform772at time t1ofFIG.7AorFIG.7B, for example.

While it will be understood that the method ofFIG.8might be performed with respect to the source216and the control line222, and/or with respect to a data line204(e.g., or a plurality of data lines204) and the control line224, the remaining discussion ofFIG.8will be described with reference to the source216corresponding to the first node selectively connected to a string of series-connected memory cells, and the control line222corresponding to the voltage level applied to the control gate of a transistor218connected to the first node and selectively connected to the string of series-connected memory cells.

At803, the voltage level applied to the first node, e.g., applied to the source216, might be increased to a third voltage level, e.g., higher than the first voltage level, while the voltage level applied to the control gate of the transistor, e.g., applied to the control line222, might be increased to a fourth voltage level lower than the third voltage level and higher than the first voltage level. A voltage difference between the third voltage level and the fourth voltage level might be equal to the desired offset for the erase operation. This action might correspond to the time period t1-t7ofFIG.7AorFIG.7B, for example. A rates of increase of the voltage levels of the waveforms770and772might be equal during the time period t1-t7ofFIG.7AorFIG.7B. For some embodiments, in addition to being equal, the rates of increase of the voltage levels of the waveforms770and772might be constant or variable during the time period t1-t7ofFIG.7AorFIG.7B.

At805, while the voltage level applied to the first node, e.g., applied to the source216, is at the third voltage level, a particular voltage level might be applied to a control gate of a memory cell of the string of series-connected memory cells that might be expected to remove charge from a data storage structure of the memory cell. This action might correspond to the time period t7-t8ofFIG.7AorFIG.7B, for example. For some embodiments, this particular voltage level might further be applied before the voltage level applied to the first node is at the third voltage level, e.g., while the voltage level applied to the first node is increasing to the third voltage level. For example, the particular voltage level might be applied at time t0ofFIG.7AorFIG.7B.

FIG.9is a flowchart of a method of operating a memory in accordance with another embodiment. For example, the method ofFIG.9might represent a portion of an erase operation.

At911, a negative first voltage level might be applied to a control gate of a transistor connected between a first node and a string of series-connected memory cells, which might be directly connected to the first node and connected (e.g., selectively or directly) to the string of series-connected memory cells. As an example, with reference toFIG.2A, the first voltage level might be applied to the control line222. Alternatively, the first voltage level might be applied to the control line224. The first voltage level might have a magnitude equal to the desired offset for the erase operation. This action might correspond to the voltage level of waveform772at time t1ofFIG.7A, or to the voltage level of waveform772at time t0ofFIG.7B, for example.

While it will be understood that the method ofFIG.9might be performed with respect to the source216and the control line222, and/or with respect to a data line204(e.g., or a plurality of data lines204) and the control line224, the remaining discussion ofFIG.9will be described with reference to the source216corresponding to the first node selectively connected to a string of series-connected memory cells, and the control line222corresponding to the voltage level applied to the control gate of a transistor218connected to the first node and selectively connected to the string of series-connected memory cells.

At913, a voltage level applied to the first node, e.g., applied to the source216, might be increased at a particular rate while the voltage level applied to the control gate of the transistor, e.g., applied to the control line222, might be increased at the particular rate, e.g., concurrently. The particular rate of increase might represent a constant rate of increase, or a variable rate of increase. In this manner, a voltage difference between the voltage level applied to the first node and the voltage level applied to the control gate of the transistor might be deemed to be maintained at a constant value, e.g., equal to the desired offset of the erase operation. This action might correspond to the time period t1-t7ofFIG.7A, or to the time period t0-t7ofFIG.7B, for example. As used herein, multiple acts being performed concurrently will mean that each of these acts is performed for a respective time period, and each of these respective time periods overlaps, in part or in whole, with each of the remaining respective time periods. In other words, those acts are concurrently performed for at least some period of time.

At915, when the voltage level applied to the first node, e.g., applied to the source216, reaches a particular voltage level, increases to the voltage levels applied to the first node, and increases to the voltage levels applied to the control gate of the transistor, e.g., applied to the control line222, might be ceased. This action might correspond to time t7ofFIG.7A, orFIG.7B, for example.

At917, while the voltage level applied to the first node, e.g., applied to the source216, is at the particular voltage level, a voltage level might be applied to a control gate of a memory cell of the string of series-connected memory cells that might be expected to remove charge from a data storage structure of the memory cell. This action might correspond to the time period t7-t8ofFIG.7AorFIG.7B, for example.

FIG.10is a flowchart of a method of operating a memory in accordance with a further embodiment. For example, the method ofFIG.10might represent a portion of an erase operation.

At1021, a first voltage level might be applied to a first node selectively connected to a string of series-connected memory cells while applying the first voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, which might be directly connected to the first node and connected (e.g., selectively or directly) to the string of series-connected memory cells. As an example, with reference toFIG.2A, the first voltage level might be applied to the source216and to the control line222. Alternatively, the first voltage level might be applied to the data line2040and to the control line224. This action might correspond to time t0ofFIG.7A, for example. The first voltage level might correspond to a ground or 0V, for example.

While it will be understood that the method ofFIG.10might be performed with respect to the source216and the control line222, and/or with respect to a data line204(e.g., or a plurality of data lines204) and the control line224, the remaining discussion ofFIG.10will be described with reference to the source216corresponding to the first node selectively connected to a string of series-connected memory cells, and the control line222corresponding to the voltage level applied to the control gate of a transistor218connected to the first node and selectively connected to the string of series-connected memory cells.

At1023, the voltage level applied to the first node, e.g., applied to the source216, might be increased to a second voltage level while the voltage level applied to the control gate of a transistor, e.g., applied to the control line222, might be decreased to a third voltage level. A voltage difference between the second voltage level and the third voltage level might be equal to the desired offset for the erase operation. This action might correspond to the voltage level increase of waveform770at time t0ofFIG.7Aand to the voltage level decrease of waveform772at time t0ofFIG.7A, for example.

At1025, for each of a plurality of successive time periods, the voltage level applied to the first node, e.g., applied to the source216, might be increased by a corresponding magnitude for that time period, and the voltage level applied to the control gate of the transistor, e.g., applied to the control line222, might be increased by the corresponding magnitude for that time period. This action might correspond to the voltage level increases of waveforms770and772for the successive time periods, e.g., t1-t2, t2-t3, t3-t4, etc. of time period t1-t7, ofFIG.7A, for example, where7801minus7800might equal7841minus7840,7802minus7801might equal7842minus7841,780Xminus7802might equal784Xminus7842, etc.

At1027, after a last time period of the plurality of successive time periods, e.g., time period t6-t7, a voltage level might be applied to a control gate of a memory cell of the string of series-connected memory cells that might be expected to remove charge from a data storage structure of the memory cell. This action might correspond to the time period t7-t8ofFIG.7A, for example.

FIG.11is a flowchart of a method of operating a memory in accordance with a still further embodiment. For example, the method ofFIG.11might represent a portion of an erase operation.

At1131, a first voltage level might be applied to a first node selectively connected to a string of series-connected memory cells while applying the first voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, which might be directly connected to the first node and connected (e.g., selectively or directly) to the string of series-connected memory cells. As an example, with reference toFIG.2A, the first voltage level might be applied to the source216and to the control line222. Alternatively, the first voltage level might be applied to the data line2040and to the control line224. This action might correspond to time tiofFIG.7B, for example. The first voltage level might correspond to a ground or 0V, for example.

While it will be understood that the method ofFIG.11might be performed with respect to the source216and the control line222, and/or with respect to a data line204(e.g., or a plurality of data lines204) and the control line224, the remaining discussion ofFIG.11will be described with reference to the source216corresponding to the first node selectively connected to a string of series-connected memory cells, and the control line222corresponding to the voltage level applied to the control gate of a transistor218connected to the first node and selectively connected to the string of series-connected memory cells.

At1133, the voltage level applied to the first node, e.g., to the source216, might be maintained at the first voltage level while the voltage level applied to the control gate of the transistor, e.g., applied to the control line222, might be decreased to a second voltage level. A magnitude of the second voltage level might be equal to the desired offset for the erase operation. This action might correspond to the voltage level decrease of waveform772for the time period ti-t0ofFIG.7B, for example.

At1135, for each of a plurality of successive time periods, the voltage level applied to the first node, e.g., applied to the source216, might be increased by a corresponding magnitude for that time period, and the voltage level applied to the control gate of the transistor, e.g., applied to the control line222, might be increased by the corresponding magnitude for that time period. This action might correspond to the voltage level increases of waveforms770and772for the successive time periods, e.g., t0-t1, t1-t2, t2-t3, etc. of time period t0-t7, ofFIG.7B, for example, where7800might equal7840minus784i, where7801minus7800, might equal7841minus7840,7802minus7801might equal7842minus7841,780Xminus7802might equal784Xminus7842, etc.

At1137, after a last time period of the plurality of successive time periods, e.g., time period t6-t7, a voltage level might be applied to a control gate of a memory cell of the string of series-connected memory cells that might be expected to remove charge from a data storage structure of the memory cell. This action might correspond to the time period t7-t8ofFIG.7B, for example.

CONCLUSION

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the embodiments will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the embodiments.