Patent ID: 12225286

DETAILED DESCRIPTION I/F THE EMBODIMENTS

Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

FIG.1is a block diagram of an image processing device10according to an example embodiment. The image processing device10may be implemented by an electronic device which shoots an image, displays the shot image, or performs an operation based on the shot image. The image processing device10may be implemented as, for example, a personal computer (PC), an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device may include a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable device, etc. In addition, the image processing device10may be mounted as a component in electronic equipment, such as a drone and an advanced drivers assistance system (ADAS), or a vehicle, furniture, manufacturing facilities, doors, various measurement equipment, etc.

Referring toFIG.1, the image processing device10may include an image sensor100, a processor200, and a clock generator300. The image processing device10may further include other components not shown, such as a display, a user interface, and a power management integrated circuit (PMIC). For example, the clock generator300may further include an oscillator generating a clock source signal.

The image sensor100may convert an optical signal of an object, which is incident through an optical lens, into an electrical signal and generate and output image data IDT based on the electrical signal. The image sensor100may include, for example, a pixel array including a plurality of pixels arranged in two dimensions and a read-out circuit, and the pixel array may convert received optical signals into electrical signals. The pixel array may be implemented as a photoelectric conversion element, for example, a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) and may be implemented as various types of photoelectric conversion elements. The read-out circuit may generate raw data based on the electrical signal provided by the pixel array and may output, as image data IDT, the raw data or the raw data on which a pre-processing, such as bad pixel elimination, has been performed. The image sensor100may be implemented as a semiconductor chip or a semiconductor package including the pixel array and the read-out circuit.

According to an example embodiment, the image sensor100may include a dynamic vision sensor (DVS), and in this case, may output the image data IDT only when there is a change in pixel units.

The image sensor100may include a control circuit110, a status register120, a first interface circuit (I/F_1)130, and a second interface circuit (I/F_2)140. The control circuit110may control the overall operation of the image sensor100. For example, when a command CMD is received from the processor200, a series of operations according to the command CMD may be performed. In an embodiment, the control circuit110may perform an operation of detecting a movement of an object, when a motion detection command (for example, CMD_MD inFIG.3) is received from the processor200. The control circuit110may generate an indication of whether there has been a movement of the object as data and store the generated data in a memory (not illustrated). The motion detection operation may be performed repeatedly according to a certain period and may be continued until a stop command is received from the processor200. In an embodiment, the control circuit110may shoot an object and generate the image data IDT, when a face detection command (for example, CMD_FD inFIG.6) is received from the processor200. The face detection command may be performed repeatedly for a certain number of times.

The control circuit110may generate the image data IDT by using a result of a series of operations and may generate status information STS after a status of the image sensor100according to the operations is identified. The status information STS may mean various flags indicating statuses of the image sensor100. For example, the status information STS may indicate a status in which the image sensor100is in operation due to a first command, a status in which the image sensor100is in operation due to a second command, and a status in which the image sensor100has terminated an operation, and in addition, the status information STS may indicate a status in which an operation mode of the image sensor100is changed. For example, the operation mode of the image sensor100may include an active mode, a sleep mode, a power off mode, etc. The active mode may mean a status in which a power signal (for example, PWR_S inFIG.11) and a clock signal CLK_S have been input and the image sensor100is ready to perform an operation, and the sleep mode may mean a status in which only the power signal has been input but the clock signal CLK_S has not been input. The sleep mode may be referred to as an idle mode or a ready mode. In addition, the power off mode may mean a status in which the power signal and the clock signal CLK_S have not been input to the image sensor100, and the image sensor100may additionally include various operation modes.

In addition, the control circuit110may generate a signal indicating a change in the status information STS. In an embodiment, the control circuit110may generate an interrupt signal INT, when the image sensor100has performed an operation according to the first command and completed performing the operation. In an embodiment, the control circuit110may generate the interrupt signal INT, when the operation mode of the image sensor100is changed from a first operation mode to a second operation mode. For example, when the operation mode of the image sensor100is changed from the active mode to the sleep mode, the control circuit110may generate the interrupt signal INT. When the control circuit110generates the interrupt signal INT in this manner, a change in status information STS of the image sensor100may be provided to the processor200.

The status register120may store the status information STS generated by the control circuit110. The status information STS may be of a flag byte type, but is not limited thereto.

The image sensor100may communicate with the processor200via the IF_1and IF_2130and140. For example, the IF_1and IF_2130and140may communicate with the processor200based on a communication protocol such as serial peripheral interface (SPI), inter-integrated circuit (I2C), improved inter-integrated circuit (I3C), and general purpose input/output (GPIO). In an embodiment, different communication protocols from each other may be applied to the IF_1and IF_2130and140. For example, a protocol based on the I2C may be applied to the IF_1130and a protocol based on the GPIO may be applied to the IF_2140.

The image sensor100may receive the command CMD from the processor200via the IF_1130and may transmit to the processor200the image data IDT and/or the status information STS, which have been generated as a result of an operation according to the command CMD. In addition, the image sensor100may transmit, to the processor200, the interrupt signal INT via the IF_2140.

The processor200may control the overall operation of the image processing device10and may control components of the image processing device10, for example, the image sensor100and the clock generator300.

The processor200may control the clock generator300and then control generation of the clock signal CLK_S, which is provided to the image sensor100, and may control the overall operation of the image sensor100. The processor200may provide the command CMD to the image sensor100and may detect a movement of an object based on the received data as a result or detect a face of an object.

For example, the processor200may control the image processing device10to operate in an always on camera (AoC) mode in which a shootable status is maintained. The AoC mode may mean a mode in which the image sensor100is maintained at a turn-on status so that the image processing device10may always capture images. In the AoC mode, the processor200may operate the image sensor100for shooting even during a status in which a display (not illustrated) or the user interface (not illustrated) of the image processing device10is not activated.

The processor200may control various functions of the image processing device10based on the captured image. In an embodiment, the processor200may release the screen lock of the image processing device10based on images. The processor200may detect whether a movement occurs outside the image processing device10by using the image sensor100. To this end, the image sensor100may perform the motion detection operation periodically and repeatedly. When a motion detection succeeds, the face detection operation may be performed. The image sensor100may generate the image data IDT by periodically capturing images, and the processor200may detect a face included in the image data IDT by using the image data IDT. When a face detection succeeds, the face recognition operation may be performed. When the image sensor100provides the image data IDT to the processor200, the processor200may determine whether the detected face is a face registered in the image processing device10. When the face detection fails, the processor200may repeatedly perform the face detection operation for a certain number of times. The processor200may perform the face detection operation for the certain number of times and, when the face detection finally fails, may perform the motion detection operation again. In the AoC mode, the image sensor100may perform the motion detection operation and the face detection operation according to a certain period.

The processor200may include a low-power controller250. The low-power controller250may control generation of the clock signal CLK_S provided to the image sensor100so that the image sensor100operating in the AoC mode may implement low power. The low-power controller250may transmit a clock control signal CTRL_CLKS to the clock generator300, based on the image data IDT, the status information STS, and the interrupt signal INT, which are received from the image sensor100. In an embodiment, the low-power controller250may block the clock signal CLK_S provided to the image sensor100, by setting the clock control signal CTRL_CLKS at a first level, and may provide the clock signal CLK_S to the image sensor100, by setting the clock control signal CTRL_CLKS at a second level.

The processor200may be implemented as a single semiconductor chip or a plurality of semiconductor chips. The processor200may include a central processing unit (CPU), a microprocessor, an advanced reduced instruction set computer (RISC) machine (ARM) processor, an X86 processor, a microprocessor without interlocked pipeline stages (MIPS) processor, a graphics processing unit (GPU), a general GPU, or a certain other processor configured to perform program commands stored in a memory.

The clock generator300may generate the clock signal CLK_S provided to the image sensor100. The clock generator300may also generate various clock signals used by the image processing device10. For example, the clock generator300may also generate a clock signal provided to the processor200.

The clock signal CLK_S generated by the clock generator300may be provided to the image sensor100via the processor200. The clock generator300may generate the clock signal CLK_S provided to the image sensor100in response to the clock control signal CTRL_CLKS of the processor200. In an embodiment, the clock generator300may terminate generation of the clock signal CLK_S or may not transmit the clock signal CLK_S to the processor200, according to the clock control signal CTRL_CLKS of the first level. In addition, the clock generator300may generate the clock signal CLK_S and transmit the clock signal CLK_S to the processor200, according to the clock control signal CTRL_CLKS of the second level.

InFIG.1, the clock generator300is illustrated as a separate component from the processor200, but is not limited thereto, and in an embodiment, the clock generator300may be equipped inside the processor200.

The image processing device10may further include an oscillator generating a clock source signal, which is a basis of the clock signal CLK_S. The oscillator may include a crystal oscillator. In an embodiment, the oscillator may be equipped outside the image sensor100and the processor200. In an embodiment, the oscillator may provide the clock source signal to the clock generator300equipped inside the processor200. The clock generator300may generate the clock signal CLK_S based on the clock source signal.

According to a comparative example, when an image processing device operates in an AoC mode, because an image sensor needs to maintain a sensing operation, the clock signal CLK_S may be continuously provided to the image sensor. In addition, even when the image sensor completes an operation earlier than a certain period, because a processor may not know of an operation completion of the image sensor, the processor may provide a clock signal to a sensor until the certain period is over. Accordingly, in the image sensor, consumed power due to toggling of the clock signal may be increased.

However, according to an embodiment, when the sensing operation of the image sensor100is completed, the image sensor100may generate the interrupt signal INT and provide the interrupt signal INT to the processor200, and the processor200may block the clock signal CLK_S provided to the image sensor100in response to the interrupt signal INT. In addition, when the image data IDT is received from the image sensor100according to the command CMD, the processor200may consider the operation of the image sensor100to be completed and may block the clock signal CLK_S provided to the image sensor100. In this manner, the image processing device10operating with low power may be implemented.

On the other hand, in the disclosure, it is described that the image sensor100performs the motion detection operation, but a subject performing the motion detection operation may not necessarily be limited to the image sensor. The subject performing the motion detection operation may be another sensor capable of sensing a movement of the object and, for example, at least one of an inertia measurement unit (IMU) using an accelerometer and an angular speedometer, a photoresistor sensor, and a voice sensor may perform the motion detection operation.

FIG.2is a block diagram illustrating the processor200according to an example embodiment.

Referring toFIG.2, the processor200may include an interface circuit (I/F)210, a face detection module220, a face recognition module230, and the low-power controller250.

The processor200may transmit the command CMD to the image sensor (100inFIG.1) via the I/F210, and may receive the image data IDT and the status information STS from the image sensor100. A communication protocol corresponding to the IF_1130of the image sensor100may be applied to the I/F210.

The face detection module220and the face recognition module230may operate based on a face detection algorithm and a face recognition algorithm, respectively. For example, the face detection algorithm may include a knowledge-based method, a feature-based method, a template-matching method, an appearance-based method, etc. In addition, examples of the face recognition algorithm may include principal component analysis (PCA), fisher discriminant analysis (FDA), independent component analysis (ICA), scale invariant feature transform (SIFT), a speeded up robust features (SURF), etc. However, the face detection algorithm and the face recognition algorithm are not limited thereto.

The face detection module220may generate the face detection command and receive the image data IDT from the image sensor100. A face may be detected from the received image data IDT. According to the face detection command, the face detection operation may be performed periodically for a number of times.

When the face detection operation succeeds, the face recognition module230may perform face recognition by using the corresponding image data IDT.

When the motion detection operation has preceded and a motion has been detected, the face detection module220may perform the face detection operation, and when a face has been detected, the face recognition module230may perform the face recognition operation.

The low-power controller250may provide the clock signal CLK_S to the image sensor100for low-power driving of the image sensor100. To this end, the interrupt signal INT may be received from the image sensor100, and based on the interrupt signal INT, provision of the clock signal CLK_S to the image sensor100may be controlled.

On the other hand, to receive the interrupt signal INT, the processor200may include a separate interface circuit corresponding to the second interface circuit140of the image sensor100. The interface circuit may include, for example, GPIO. The image processing device10may sequentially perform the motion detection operation, the face detection operation, and the face recognition operation. Below, each operation will be individually described.

FIG.3is a conceptual diagram of a motion detection operation of a processor200a, according to an example embodiment. The processor200ainFIG.3may perform the motion detection operation.

Referring toFIG.3, the low-power controller250may provide the clock signal CLK_S to the image sensor100for operating the image sensor100. In addition, the low-power controller250may control generation of the clock signal CLK_S provided to the image sensor100, by providing the clock control signal CTRL_CLKS to the clock generator300. In this manner, the low-power controller250may control the image sensor100to operate with low power. The clock signal CLK_S may be received from the clock generator300.

In addition, the low-power controller250may generate a motion detection command CMD_MD for performing the motion detection operation and provide the motion detection command CMD_MD to the image sensor100via the I/F210. The image sensor100may perform the motion detection operation in response to the received motion detection command CMD_MD. When the motion detection operation is completed, the image sensor100may generate a first interrupt signal INT_MD and provide the first interrupt signal INT_MD to the processor200. The processor200may read a first status information STS_MD stored in the status register120of the image sensor100, by receiving the first interrupt signal INT_MD. The first status information STS_MD may include information about whether a motion detection has been made. The first status information STS_MD may be provided to the low-power controller250via the I/F210. In an embodiment, when the first interrupt signal INT_MD is received, the processor200may request status information from the image sensor100and the image sensor100may transmit the first status information STS_MD stored in the status register120to the processor200in response to a request of the low-power controller250.

Because the first interrupt signal INT_MD means completion of the motion detection operation of the image sensor100, the low-power controller250may block the clock signal CLK_S provided to the image sensor100by receiving the first interrupt signal INT_MD. The low-power controller250may stop generation of the clock signal CLK_S by transmitting the clock control signal CTRL_CLKS of the first level to the clock generator300, which generates the clock signal CLK_S.

When the image processing device10operates in the AoC mode, the motion detection operation may be repeatedly performed. Accordingly, signals described above may be repeatedly generated in every period in which the motion detection operation is performed.

FIG.4is a flowchart of an operation of an image processing device, according to an example embodiment, andFIG.5is a timing diagram of an operation mode of the image sensor100, according to an example embodiment. The image processing device may correspond to the image processing device10ofFIG.1and may perform the motion detection operation.

Referring toFIGS.3and4, the processor200amay transmit the clock control signal CTRL_CLKS of the first level to the clock generator300(S101). In this manner, the clock generator300may activate the clock signal CLK_S by generating the clock signal CLK_S (S102). For example, the first level may be a logic high level. The image sensor100may be in a state in which the image sensor100has been activated ahead of operation S101.

The processor200amay receive the clock signal CLK_S from the clock generator300(S103) and may provide the clock signal CLK_S to the image sensor100(S104). For example, the clock signal CLK_S may be provided to the image sensor100via the low-power controller250.

In this case, referring toFIG.5, when the clock signal CLK_S is provided, the operation mode of the image sensor100may be changed from the sleep mode to the active mode. Thereafter, the image sensor100may operate in the active mode until the clock signal CLK_S is stopped.

Referring toFIG.4again, to perform the motion detection operation, the processor200amay generate the motion detection command CMD_MD and provide the motion detection command CMD_MD to the image sensor100(S105). The processor200amay estimate the time during which the image sensor100performs the motion detection operation. A period T of the motion detection operation based on the estimated time may be determined.

The image sensor100may perform the motion detection operation in response to the motion detection command CMD_MD (S106). In an embodiment, when the image sensor100includes a complementary metal-oxide semiconductor (CMOS) sensor, the image sensor100may generate the image data IDT and detect a movement of an object by using a motion detection algorithm. In an embodiment, when the image sensor100includes a DVS, the image sensor100may perform the motion detection operation by sensing an occurrence of an event according to a change of light.

When the motion detection operation is completed, the image sensor100may store a motion detection result in the status register120(S107). The first status information STS_MD stored in the status register120may include the motion detection result and the operation mode of the image sensor100.

On the other hand, the image sensor100may complete an operation earlier than the time that has been previously estimated by the processor200a. For example, an operation time of the image sensor100may vary according to a surrounding environment. For example, the time required for the motion detection in an environment of a sufficient amount of light may be relatively shorter than the time required for the motion detection in an environment of an insufficient amount of light.

When the motion detection operation is terminated, the image sensor100may generate the first interrupt signal INT_MD and transmit the generated first interrupt signal INT_MD to the processor200a(S108). The first interrupt signal INT_MD may be used to inform the processor200aof a termination of the operation of the image sensor100. The processor200amay determine that the operation of the image sensor100has been terminated by receiving the first interrupt signal INT_MD, regardless of the pre-estimated time.

The processor200amay read the first status information STS_MD stored in the image sensor100in response to the first interrupt signal INT_MD (S109) and may transmit the clock control signal CTRL_CLKS of the second level to the clock generator300(S110). For example, the second level may be logic low level. The clock generator300may deactivate the clock signal CLK_S in response to the clock control signal CTRL_CLKS of the second level (S111).

Referring toFIG.5, when the clock signal CLK_S is blocked, the operation mode of the image sensor100may set from the active mode to the sleep mode. Thereafter, the image sensor100may maintain the sleep mode until the clock signal CLK_S is provided again.

Referring toFIG.4again, the processor200amay identify whether the motion detection has been made based on the received first status information STS_MD (S112). When the motion detection has been detected, the face detection operation, as a next operation, may be performed (S113); but when the motion detection has not been made, operation S101may be performed again. On the other hand, the motion detection operation described with reference toFIG.4may be repeatedly performed according to the period T.

According to an embodiment, the image sensor100may receive the clock signal CLK_S only in the active mode in which an operation of the image sensor100is performed, but may not receive the clock signal CLK_S in the sleep mode thereof, and thus, power consumption due to the clock signal CLK_S may be reduced.

Although it is described in the disclosure that the image sensor100directly performs the motion detection operation, the processor200amay perform the motion detection operation when the image sensor100provides the image data IDT to the processor200a. In this case, when the image sensor100transmits the image data IDT to the processor200a, the processor200amay determine that the operation of the image sensor100has been completed+ and may block the clock signal CLK_S.

FIG.6is a conceptual diagram of a face detection operation of a processor200b, according to an example embodiment. The processor200binFIG.6may perform the face detection operation when the motion detection operation succeeds.

Referring toFIG.6, the low-power controller250may provide the clock signal CLK_S for operating the image sensor100. In addition, the low-power controller250may control the clock signal CLK_S provided to the image sensor100by using the clock control signal CTRL_CLKS. In this manner, the image sensor100may be controlled to operate with low power. The clock signal CLK_S may be received from the clock generator300.

The face detection module220may be provide a face detection command CMD_FD to the interface circuit210for performing the face detection operation. Thereafter, in response to the face detection command CMD_FD, the image sensor100may generate the image data IDT and provide the image data IDT to the low-power controller250via the I/F210.

Because the face detection operation may be performed by the processor200b, the image sensor100may terminate an operation by transmitting the image data IDT. Thus, the low-power controller250may receive the image data IDT and block the clock signal CLK_S that is provided to the image sensor100. Generation of the clock signal CLK_S may be blocked by transmitting the clock control signal CTRL_CLKS of the first level to the clock generator300, which generates the clock signal CLK_S.

FIG.7is a flowchart of an operation of an image processing device, according to an example embodiment. Operations inFIG.7may include the face detection operation corresponding to operation S111inFIG.4.

Referring toFIG.7, the processor200bmay transmit the clock control signal CTRL_CLKS of the first level to the clock generator300(S201). For example, the first level may be logic high level. In this manner, the clock generator300may activate the clock signal CLK_S (S202).

The processor200bmay receive the clock signal CLK_S from the clock generator300(S203) and may provide the clock signal CLK_S to the image sensor100(S204). For example, the clock signal CLK_S may be provided via the low-power controller250. When the clock signal CLK_S is provided to the image sensor100, the operation mode of the image sensor100may be set to the active mode.

To perform the face detection operation, the processor200bmay generate the face detection command CMD_FD and provide the face detection command CMD_FD to the image sensor100(S205). For example, the face detection module220may generate the face detection command CMD_FD. The image sensor100may generate the image data IDT and transmit the image data IDT to the processor200bin response to the face detection command CMD_FD.

The processor200bmay estimate the time required by the image sensor100to generate the image data IDT. In this case, by receiving the image data IDT, the processor200bmay determine that the operation of the image sensor100has been terminated regardless of the estimated time. Accordingly, thereafter, to block the clock signal CLK_S provided to the image sensor100, the clock control signal CTRL_CLKS of the second level may be transmitted to the clock generator300(S207). For example, the second level may be logic low level. The clock generator300may deactivate the clock signal CLK_S (S208). When provision of the clock signal CLK_S is blocked, the operation mode of the image sensor100may be changed to the sleep mode.

The processor200bmay perform the face detection operation based on the received image data IDT (S209). An algorithm used for the face detection operation is not limited to any algorithm. When a face is detected (S210), the face recognition operation may be performed (S211), and when a face is not detected (S210), operation S201may be performed again.

On the other hand, when face detection fails, the processor200bmay perform operations S201through S210repeatedly for a certain critical number of times. When the critical number of times is exceeded, the motion detection operations inFIG.4may be performed.

FIG.7discloses that the processor200bperforms the face detection operation, but the image sensor100may directly perform the face detection operation for the image data IDT. In this case, the image sensor100may provide only the face detection result to the processor200b. This issue will be described with reference toFIGS.8through10.

FIG.8is a block diagram of an image sensor100caccording to an example embodiment.

The image sensor100cofFIG.8may be a modified example of the image sensor100inFIG.1. Accordingly, duplicate descriptions of the image sensor100inFIG.1will be omitted. The image sensor100cofFIG.8may directly perform not only the motion detection operation but the face detection operation by including a face detection module150.

Referring toFIG.8, in an embodiment of the motion detection operation, the control circuit110may receive the motion detection command CMD_MD and generate the first status information STS_MD by performing the motion detection operation. The first status information STS_MD may include information about whether the motion detection has been made. In addition, when the motion detection operation is completed, the control circuit110may generate the first interrupt signal INT_MD and transmit the first interrupt signal INT_MD to the processor (for example,200cofFIG.9) via the second interface circuit140. Hereinafter, the first status information STS_MD and the first interrupt signal INT_MD may be referred to as being generated by the motion detection operation and second status information STS_FD and a second interrupt signal INT_FD may be referred to as being generated by the face detection operation. Next, the processor200cmay read the first status information STS_MD stored in the status register120via the IF_1130. Next, when the motion detection succeeds, the face detection operation may be performed.

In an embodiment, in the case of the face detection operation, the image sensor100cmay receive the face detection command CMD_FD and the face detection module150may generate the second status information STS_FD by using various algorithms. The second status information STS_FD may indicate whether the face detection succeeds. When the face detection operation is completed, the control circuit110may generate the second interrupt signal INT_FD and transmit the second interrupt signal INT_FD to the processor200cvia the second interface circuit140. Next, the processor200cmay read the second status information STS_FD stored in the status register120via the IF_1130. Next, when the motion detection succeeds, the face recognition operation may be performed.

On the other hand, inFIG.8, it is illustrated that the control circuit110performing the motion detection and the face detection module150performing the face detection are included inside the image sensor100c, but the embodiment is not limited thereto. In an embodiment, a circuit performing the motion detection and the face detection module150may be included in sensors of different types. For example, the control circuit110performing the motion detection may be included in a photoresistor sensor or a DVS and the face detection module150may be included in the image sensor100c.

In an embodiment, the face detection module150may be included inside the control circuit110. In this case, the control circuit110may sequentially perform the motion detection operation and the face detection operation.

FIG.9is a block diagram of a portion of the processor200c, according to an example embodiment.

The processor200cofFIG.9may illustrate a modified embodiment of the processor200b. Accordingly, duplicate descriptions with reference toFIG.6will be omitted. The processor200cofFIG.9may not directly perform the face detection operation, and accordingly, generated signals may be changed.

Referring toFIG.9, the low-power controller250may generate the face detection command CMD_FD and provide the face detection command CMD_FD to the image sensor (100cofFIG.8) via the I/F_210.

In response to the face detection command CMD_FD, the image sensor100cmay perform the face detection operation, and when the face detection operation is completed, may generate the second interrupt signal INT_FD. By receiving the second interrupt signal INT_FD, the processor200cmay read the second status information STS_FD stored in the status register120of the image sensor100c. The second status information STS_FD may indicate whether the face detection succeeds. The second status information STS_FD may be provided to the low-power controller250via the I/F_210.

On the other hand, to receive the second interrupt signal INT_FD, the processor200cmay include an I/F corresponding to the IF_2140of the image sensor100c. The I/F may include, for example, GPIO.

Because the second interrupt signal INT_FD means completion of the face detection operation of the image sensor100c, the low-power controller250may block the clock signal CLK_S provided to the image sensor100cby receiving the second interrupt signal INT_FD. Generation of the clock signal CLK_S may be blocked by transmitting the clock control signal CTRL_CLKS of the first level to the clock generator300, which generates the clock signal CLK_S.

FIG.10is a flowchart of an operation of an image processing device, according to an example embodiment. The image processing device10may include the image sensor100cofFIG.8and the processor200cofFIG.9and may perform the face detection operation.

Referring toFIG.10, the processor200cmay transmit the clock control signal CTRL_CLKS of the first level to the clock generator300(S301). For example, the first level may be logic high level. In this manner, the clock generator300may activate the clock signal CLK_S (S302).

The processor200cmay receive the clock signal CLK_S from the clock generator300(S303) and may provide the clock signal CLK_S to the image sensor100c(S304). When the clock signal CLK_S is provided to the image sensor100c, the operation mode of the image sensor100cmay be set to the active mode.

Because the image sensor100cincludes the face detection module150, the processor200cmay generate the face detection command CMD_FD and provide the face detection command CMD_FD to the image sensor100c(S305), and the image sensor100cmay perform the face detection operation (S306).

When the face detection operation is completed, the image sensor100cmay store a face detection result in the status register120(S307). The second status information STS_FD stored in the status register120may include the face detection result and the operation mode of the image sensor100.

In addition, when the face detection operation is terminated, the image sensor100cmay generate the second interrupt signal INT_FD and transmit the second interrupt signal INT_FD to the processor200c(S308). The processor200cmay identify that the operation of the image sensor100chas been terminated by using the second interrupt signal INT_FD.

The processor200cmay read the second status information STS_FD stored in the image sensor100c(S309) and may transmit the clock control signal CTRL_CLKS of the second level to the clock generator300(S310). For example, the second level may be logic low level. The clock generator300may deactivate the clock signal CLK_S by blocking generation of the clock signal CLK_S (S311). When the clock signal CLK_S provided to the image sensor100cis blocked, the operation mode of the image sensor100cmay be set to the sleep mode.

Thereafter, the processor200cmay identify whether the face detection has been made, based on the received second status information STS_FD (S312). When a face has been detected, an operation of face recognition may be performed as a next operation (S313). When a face has not been detected, operation S301may be performed again.

FIG.11is a block diagram of an image processing device20according to an example embodiment. The image processing device20may include a image sensor400and a processor500. The image sensor400may include a control circuit410, a status register420, a first interface circuit (I/F_1)430, and a second interface circuit (I/F_2)440. Accordingly, duplicate descriptions of the image sensor100inFIG.1will be omitted.

According to an embodiment, a processor500may implement a low power operation of an image sensor400by controlling not only the clock signal CLK_S but a power signal PWR_S provided to the image sensor400. The processor500may identify that an operation of the image sensor400has been completed and may block the clock signal CLK_S and the power signal PWR_S provided to the image sensor400. Hereinafter, duplicate descriptions with reference toFIG.1will be omitted.

Referring toFIG.11, an image processing device20may further include a PMIC700. The PMIC700may generate the power signal PWR_S that is input to the processor500and the image sensor400. For example, the power signal PWR_S may be a power voltage.

The PMIC700may generate the power signal PWR_S provided to the image sensor400. The PMIC700may also generate various clock signals used by the image processing device20. For example, the PMIC700may generate the power signal provided to the processor500.

The power signal PWR_S generated by the PMIC700may be provided to the image sensor400via the processor500. The PMIC700may generate the power signal PWR_S provided to the image sensor400according to a power control signal CTRL_PWRS of the processor500. In an embodiment, according to the power control signal CTRL_PWRS of the first level, the PMIC700may not generate the power signal PWR_S or may not transmit the power signal PWR_S to the processor500. For example, the first level may be logic low level. In addition, the PMIC700may transmit the power signal PWR_S to the processor500according to the power control signal CTRL_PWRS of the second level. For example, the second level may be logic high level. Below, blocking the power signal PWR_S by the processor500by transmitting the power control signal CTRL_PWRS of the first level to the PMIC700may be referred to as turning off the power signal PWR_S. In addition, generating the power signal PWR_S by the processor500by transmitting the power control signal CTRL_PWRS of the second level to the PMIC700may be referred to as turning on the power signal PWR_S.

The image processing device20may selectively provide power to the image sensor400by controlling the power signal PWR_S provided to the image sensor400based on signals received from the image sensor400, for example, an interrupt signal and/or the image data IDT. Accordingly, because the power is not provided when the image sensor400does not operate, power consumption may be reduced.

FIG.12is a flowchart of an operation of the image processing device20, according to an example embodiment, andFIG.13is a timing diagram of an operation mode of the image sensor400, according to an example embodiment. The operations of the image processing device20may be similar to the operations inFIG.4, and thus, duplicate descriptions thereof will be omitted.

Referring toFIGS.11and12, the processor500may transmit the clock control signal CTRL_CLKS to a clock generator600(S401) and may transmit the power control signal CTRL_PWRS of the first level to the PMIC700(S402). Accordingly, the clock generator600may activate the clock signal CLK_S (S403) and the PMIC700may activate the power signal PWR_S (S404).

The processor500may receive the clock signal CLK_S (S405), may receive the power signal PWR_S (S406), and may provide the clock signal CLK_S and the power signal PWR_S to the image sensor400(S407). Operations S401and S402may be simultaneously performed, or operation S402may be performed in advance and then, operation S401may be performed. In addition, operations S405and S406may be simultaneously performed, or operation S406may be performed in advance and then operation S405may be performed. In this case, referring toFIG.13, when the image sensor400receives the clock signal CLK_S and the power signal PWR_S, the mode of the image sensor400may be changed from the power off mode to the active mode.

Thereafter, the processor500may generate the motion detection command CMD_MD and provide the motion detection command CMD_MD to the image sensor400for performing the motion detection operation (S408), and the image sensor400may perform the motion detection operation (S409). When the motion detection operation is completed, the image sensor400may generate the first status information STS_MD, including the motion detection result, and store the first status information STS_MD in the status register420(S410). In addition, the image sensor400may generate the first interrupt signal INT_MD indicating completion of the motion detection operation and transmit the first interrupt signal INT_MD to the processor500(S411).

The processor500may receive the first interrupt signal INT_MD and read the first status information STS_MD stored in the image sensor400(S412). Thereafter, the operation of the image sensor400may be determined as being completed and the image sensor400may be turned off. The processor500may transmit the clock control signal CTRL_CLKS of the second level to the clock generator600(S413) and may transmit the power control signal CTRL_PWRS of the second level to the PMIC700(S414). Accordingly, the clock generator600may deactivate the clock signal CLK_S (S415) and the PMIC700may deactivate the power signal PWR_S (S416). Operations S413and S414may be simultaneously performed, or operation S414may be performed in advance and then, operation S413may be performed. When the clock signal CLK_S and the power signal PWR_S are blocked, the operation mode of the image sensor400may be set to the power off mode.

Thereafter, the processor500may identify whether the face detection has been made, based on the received first status information STS_MD (S417). When a motion has been detected, an operation of face detection may be performed as a next operation (S418). When a motion has not been detected, operation S401may be performed again. Operations S401through S417may be performed repeatedly according to the period T.

FIG.14is a flowchart of an operation of the image processing device20, according to an example embodiment. Operations inFIG.14may include the face detection operation corresponding to operation S418inFIG.13. The processor500may include a face detection module (not illustrated). The operation of the image processing device20may be similar to operations inFIG.7, and duplicate descriptions thereof may be omitted.

Referring toFIG.14, the processor500may transmit the clock control signal CTRL_CLKS of the first level to the clock generator600(S501) and may transmit the power control signal CTRL_PWRS of the first level to the PMIC700(S502). Accordingly, the clock generator600may activate the clock signal CLK_S (S503) and the PMIC700may activate the power signal PWR_S (S504).

The processor500may receive the clock signal CLK_S (S505), may receive the power signal PWR_S (S506), and may provide the clock signal CLK_S and the power signal PWR_S to the image sensor400(S507). Operations S501and S502may be simultaneously performed or a sequence thereof may be changed. In addition, operations S505and S506may be simultaneously performed or a sequence thereof may be changed. When the image sensor400receives the clock signal CLK_S and the power signal PWR_S, the mode of the image sensor400may be changed from the power off mode to the active mode.

To perform the face detection operation, the processor500may generate the face detection command CMD_FD and provide the face detection command CMD_FD to the image sensor400(S508). The image sensor400may generate the image data IDT and transmit the image data IDT to the processor500in response to the face detection command CMD_FD (S509).

The processor500may identify that the operation of the image sensor400has been terminated, by receiving the image data IDT, and may transmit the clock control signal CTRL_CLKS of the second level to the clock generator600(S510) and may transmit the power control signal CTRL_PWRS of the second level to the PMIC700(S511).

The clock generator600may deactivate the clock signal CLK_S (S512), and the PMIC700may deactivate the power signal PWR_S (S513). Accordingly, the image sensor400may be set to the power off mode. In other words, because the image processing device20generates the clock signal CLK_S and the power signal PWR_S only in a period in which the image sensor400generates the image data IDT, consumed power may be reduced by discontinuing a clock signal and power in a period in which the image sensor400does not operate.

The processor500may perform the face detection operation based on the received image data IDT (S514). When a face is detected (S515), the face recognition operation may be performed (S516). When a face is not detected (S515), operation S501may be performed again.

FIG.15is a flowchart of an operation of an image processing device, according to an example embodiment.

On the other hand, the face detection operation may be performed by an image sensor400a. The image sensor400amay mean that a face detection module (not illustrated) is included in the image sensor400inFIG.11. Operations inFIG.15may be similar to operations inFIG.10.

Referring toFIG.15, a processor500amay transmit the clock control signal CTRL_CLKS of the first level to the clock generator600(S601) and may transmit the power control signal CTRL_PWRS of the first level to the PMIC700(S602). Accordingly, the clock generator600may activate the clock signal CLK_S (S603) and the PMIC700may activate the power signal PWR_S (S604).

The processor500may receive the clock signal CLK_S (S605), may receive the power signal PWR_S (S606), and may provide the clock signal CLK_S and the power signal PWR_S to the image sensor400(S607). In operation S607, the image sensor400amay be set to the active mode. The sequence of operations S601and S602is not be limited thereto, and the sequence of operations S605and S606is not limited thereto.

To perform the face detection operation, the processor500amay generate the face detection command CMD_FD and provide the face detection command CMD_FD to the image sensor400a(S608). The image sensor400amay directly perform the face detection operation (S609) and may store the second status information STS_FD, which has been generated as a result thereof, to the status register420(S610). When the face detection operation is completed, the image sensor400amay generate the second interrupt signal INT_FD and transmit the second interrupt signal INT_FD to the processor500a(S611). The processor500amay read the second status information STS_FD stored in the image sensor400a(S612).

In addition, the processor500may identify that the operation of the image sensor400ahas been terminated by using the second interrupt signal INT_FD, may transmit the clock control signal CTRL_CLKS of the second level to the clock generator600(S613), and may transmit the power control signal CTRL_PWRS of the second level to the PMIC700(S614). The clock generator600may deactivate the clock signal CLK_S (S615), and the PMIC700may deactivate the power signal PWR_S (S616). In operation S616, the image sensor400amay be set to the power off mode.

Thereafter, the processor500amay identify whether the face detection has been made, based on the received second status information STS_FD (S617). When a face has been detected, an operation of face recognition may be performed as a next operation (S618). When a face has not been detected, operation S601may be performed again.

FIG.16is a block diagram of an electronic device1000including a multi-camera module1100, according to an example embodiment.FIG.17is a detailed block diagram of a camera module1100binFIG.16. Referring toFIG.16, the electronic device1000may include the camera module group1100, an application processor1200, a PMIC1300, and an external memory1400.

The camera module group1100may include a plurality of camera modules1100a,1100b, and1100c. Although the drawing illustrates an embodiment in which three camera modules1100a,1100b, and1100care arranged, the embodiment is not limited thereto. In some embodiments, the camera module group1100may be modified to include only two camera modules. In addition, in some embodiments, the camera module group1100may be modified and embodied to include n (n is a natural number equal to or greater than 4) camera modules.

Hereinafter, referring toFIG.17, detailed configurations of the camera module1100bwill be described, but the descriptions below may be identically applied to other camera modules1100aand1100caccording to embodiments.

Referring toFIG.17, the camera module1100bmay include a prism1105, an optical path folding element (hereinafter, referred to as OPFE)1110, an actuator1130, and an image sensing device1140, and a storage1150.

The prism1105may change a path of light L incident from the outside by including a reflective surface1107of a light reflecting material.

In some embodiments, the prism1105may change a path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism1105may rotate the reflective surface1107of the light reflecting material to a direction A with a center axis1106as a center or change the path of the light L incident in the first direction X to the second direction Y by rotating the center axis1106to a direction B. In this case, the OPFE1110may also be moved to a third direction Z perpendicular to the first direction X and the second direction Y.

In some embodiments, as illustrated, the maximum rotation angle in a direction A of the prism1105may be equal to or less than about 15 degrees in a plus (+) direction A and greater than about 15 degrees in a minus (−) direction A, but the embodiments are not limited thereto.

In some embodiments, the prism1105may be moved within about 20 degrees, between about 10 degrees and about 20 degrees, or between about 15 degrees and about 20 degrees in a plus (+) or minus (−) direction B; in this case, the movement degrees may be the same degrees in the plus (+) or the minus (−) direction B or almost similar degrees thereto within a range of about 1 degree.

In some embodiments, the prism1105may move the reflecting surface1107to a third direction (for example, the Z direction) in parallel with an extended direction of the center axis1106.

The OPFE1110may include, for example, an optical lens including m (m is a natural number) groups. The m lenses may move in the second direction Y and change an optical zoom ratio of the camera module1100b. For example, when a basic optical zoom ratio of the camera module1100bis defined as Z and m groups included in the OPFE1110are moved, the optical zoom ratio of the camera module1100bmay be changed to an optical zoom ratio of 3Z or 5Z or 5Z or more.

The actuator1130may move the OPFE1110or the optical lens (hereinafter, referred to as an optical lens) to a certain position. For example, the actuator1130may adjust a location of the optical lens so that the image sensor1142is positioned at a focal length of the optical lens for an accurate sensing.

The image sensing device1140may include a sensor, for example image sensor1142, a logic, for example control logic1144, and a memory1146. The image sensor1142may sense an image of a sensing object by using the light L provided through the optical lens. The control logic1144may control the overall operation of the camera module1100b. For example, the control logic1144may control an operation of the camera module1100baccording to a control signal provided via a control signal line CSLb.

The memory1146may store information required for operations of the camera module1100b, such as calibration data1147. The calibration data1147may include information required by the camera module1100for generating image data by using the light L provided from the outside. The calibration data1147may include, for example, information about the degree of rotation described above, information about a focal length, information about an optical axis, etc. When the camera module1100bis implemented in a multi-state camera type in which a focal length varies according to a position of the optical lens, the calibration data1147may include information about a focal length value per position (or per state) of the optical lens and information about auto-focusing.

The storage1150may store the image data sensed by the image sensor1142. The storage1150may be arranged outside the image sensing device1140and may be implemented in a form in which the storage1150is stacked with a sensor chip constituting the image sensing device1140. In some embodiments, the storage1150may be implemented as an electrically erasable programmable read-only memory (EEPROM), but the embodiments are not limited thereto.

Referring toFIGS.16and17together, in some embodiments, each of the plurality of camera modules1100a,1100b, and1100cmay include the actuator1130. Accordingly, each of the plurality of camera modules1100a,1100b, and1100cmay include identical or different calibration data1147to or from each other, according to an operation of the actuator1130included therein.

In some embodiments, one camera module (for example,1100b) of the plurality of camera modules1100a,1100b, and1100cmay include a folded lens-type camera module including the prism1105and the OPFE1110described above and the remaining camera modules (for example,1100aand1100c) may include a vertical-type camera module that does not include the prism1105and the OPFE1110, but the embodiments are not limited thereto.

In some embodiments, one camera module (for example,1100c) of the plurality of camera modules1100a,1100b, and1100cmay include a depth camera of a vertical type in which depth information is extracted by using, for example, an infrared ray (IR). In this case, the application processor1200may generate a three-dimensional (3D) depth image by merging image data provided by the depth camera with image data provided by another camera module (for example,1100aor1100b).

In some embodiments, at least two camera modules (for example,1100aand1100b) of the plurality of camera modules1100a,1100b, and1100cmay have different fields of view from each other. In this case, for example, the optical lenses of at least two camera modules (for example,1100aand1100b) of the plurality of camera modules1100a,1100b, and1100cmay be different from each other, but the embodiments are not limited thereto.

In addition, in some embodiments, the fields of view of each of the plurality of camera modules1100a,1100b, and1100cmay be different from each other. In this case, the optical lenses included in each of the plurality of camera modules1100a,1100b, and1100cmay also be different from each other, but the embodiments are not limited thereto.

In some embodiments, each of the plurality of camera modules1100a,1100b, and1100cmay be arranged physically apart from each other. In other words, a sensing area of one image sensor1142may not be divided and used by the plurality of camera modules1100a,1100b, and1100c, but the image sensor1142may be arranged independently inside each of the plurality of camera modules1100a,1100b, and1100c.

Referring again toFIG.16, the application processor1200may include an image processing device1210, a memory controller1220, and an internal memory1230. The application processor1200may be implemented separate from the plurality of camera modules1100a,1100b, and1100c. For example, the application processor1200and the plurality of camera modules1100a,1100b, and1100cmay be implemented as being separated from each other in separate semiconductor chips.

The image processing device1210may include a plurality of sub-image processors1212a,1212band1212c, an image generator1214, and a camera module controller1216.

The image processing device1210may include the plurality of sub-image processors1212a,1212b, and1212chaving the number thereof corresponding to the number of the plurality of camera modules1100a,1100b, and1100c.

Image data generated by each of the plurality of camera modules1100a,1100b, and1100cmay be provided to the corresponding plurality of sub-image processors1212a,1212b, and1212cvia image signal lines ISLa, ISLb, and ISLc, which are separate from each other. For example, the image data generated by the camera module1100amay be provided to the sub-image processor1212avia the image signal line ISLa, the image data generated by the camera module1100bmay be provided to the sub-image processor1212bvia the image signal line ISLb, and the image data generated by the camera module1100cmay be provided to the sub-image processor1212cvia the image signal line ISLc. Transmission of the image data may be performed by using, for example, a camera serial interface (CSI) based on a mobile industry processor interface (MIPI), but the embodiments are not limited thereto.

On the other hand, in some embodiments, one sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor1212aand the sub-image processor1212cmay not be implemented as separate from each other as illustrated but may be implemented as integrated into one sub-image processor and the image data provided by the camera module1100aand the camera module1100cmay, after being selected by a select element (for example, a multiplexer), be provided to the integrated sub-image processor.

The image data provided to each of the plurality of sub-image processors1212a,1212b, and1212cmay be provided to the image generator1214. The image generator1214may generate an output image by using the image data provided by each of the plurality of sub-image processors1212a,1212b, and1212caccording to image generating information or a mode signal.

The image generator1214may generate an output image by merging at least some of the image data generated by the plurality of camera modules1100a,1100b, and1100chaving different fields of view from each other, according to the image generation information or the mode signal. In addition, the image generator1214may generate an output image by selecting at least one of the image data generated by the plurality of camera modules1100a,1100b, and1100chaving different fields of view from each other, according to the image generation information or the mode signal.

In some embodiments, the image generating information may include a zoom signal or a zoom factor. In addition, in some embodiments, the mode signal may include, for example, a signal based on a mode selected by a user.

When the image generating information includes the zoom signal (zoom factor) and each of the plurality of camera modules1100a,1100b, and1100chas different fields of view from each other, the image generator1214may perform different operations from each other according to a type of the zoom signal. For example, when the zoom signal includes the first signal, after merging the image data output by the camera module1100awith the image data output by the camera module1100c, the image generator1214may generate an output image by using the image data output by the camera module1100bwhich has not been used in the merging with the merged image signal. When the zoom signal includes the second signal different from the first signal and the second signal, the image generator1214may not perform merging of the image data, but may generate the output image by selecting any one of the image data output by each of the plurality of camera modules1100a,1100b, and1100c. However, the embodiments are not limited thereto, and a method of processing the image data may be modified and performed as necessary.

In some embodiments, by receiving a plurality of image data having different exposure times from each other from at least one of the plurality of sub-image processors1212a,1212b, and1212cand performing a high dynamic range (HDR) processing on the plurality of image data, the image generator1214may generate the merged image data with an increased dynamic range.

The camera module controller1216may provide a control signal to each of the plurality of camera modules1100a,1100b, and1100c. The control signal generated by the camera module controller1216may be provided to the corresponding plurality of camera modules1100a,1100b, and1100cvia control signal lines CSLa, CSLb, and CSLc, which are separated from each other, respectively.

Any one of the plurality of camera modules1100a,1100b, and1100cmay be designated as a master camera (for example,1100b) according to the image generating information including the zoom signal or the mode signal, and the other camera modules (for example,1100aand1100c) may be designated as slave cameras. This piece of information may be included in the control signal and may be provided to the corresponding plurality of camera modules1100a,1100b, and1100cvia the control signal lines CSL1, CSLb, and CSLc, which are separated from each other, respectively.

According to the zoom factor or an operation mode signal, camera modules operating as the master camera or the slave cameras may be changed. For example, when the field of view of the camera module1100ais wider than the field of view of the camera module1100band indicates a zoom ratio having a low zoom factor, the camera module1100bmay operate as the master camera and the camera module1100amay operate as the slave camera. To the contrary, when the field of view indicates a zoom ratio having a high zoom ratio, the camera module1100amay operate as the master camera and the camera module1100bmay operate as the slave camera.

In some embodiments, the control signal provided by the camera module controller1216to each of the plurality of camera modules1100a,1100b, and1100cmay include a sync enable signal. For example, when the camera module1100bis the master camera and the camera modules1100aand1100care the slave cameras, the camera module controller1216may transmit the sync enable signal to the camera module1100b. The camera module1100bhaving received the sync enable signal may generate a sync signal based on the received sync enable signal and provide the generated sync signal to the camera modules1100aand1100cvia a sync enable signal line SSL. The camera module1100band the camera modules1100aand1100cmay be synchronized to the sync signal and transmit the image data to the application processor1200.

In some embodiments, the control signal provided by the camera module controller1216to the plurality of camera modules1100a,1100b, and1100cmay include mode information according the mode signal. Based on the mode information, the plurality of camera modules1100a,1100b, and1100cmay operate in a first operation mode and second operation mode with respect to a sensing speed.

The plurality of camera modules1100a,1100b, and1100cmay, in the first operation mode, generate the image signal at a first speed (for example, generate the image signal at a first frame rate), encode the image signal at a second speed higher than the first speed (for example, encode the image signal at a second frame rate greater than the first frame rate), and transmit the encoded image signal to the application processor1200. In this case, the second speed may be equal to or less than about 30 times the first speed.

The application processor1200may store the received image signal, that is, the encoded image signal, in the internal memory1230equipped therein or the storage1400outside the application processor1200and then read and decode the encoded signal from the internal memory1230or the storage1400and may display the image data generated based on the decoded image signal. For example, a corresponding sub-processor of the plurality of sub-processors1212a,1212b, and1212cof the image processing device1210may perform decoding and in addition, may perform image processing on the decoded image signal.

The plurality of camera modules1100a,1100b, and1100cmay, in the second operation mode, generate the image signal at a third speed lower than the first speed (for example, generate the image signal at a third frame rate less than the first frame rate) and transmit the image signal to the application processor1200. The image signal provided to the application processor1200may include an un-encoded signal. The application processor1200may perform the image processing on the received image signal or store the received image signal in the internal memory1230or the storage1400.

The PMIC1300may provide power, for example, a power voltage to each of the plurality of camera modules1100a,1100b, and1100c. For example, the PMIC1300may, under the control of the application processor1200, provide a first power to the camera module1100avia a power signal line PSLa, provide a second power to the camera module1100bvia a power signal line PSLb, and provide a third power to the camera module1100cvia a power signal line PSLc.

The PMIC1300may, in response to a power control signal PCON from the application processor1200, generate power corresponding to each of the plurality of camera modules1100a,1100b, and1100cand, in addition, may adjust a level of the generated power. The power control signal PCON may include a power adjustment signal per operation mode of the plurality of camera modules1100a,1100b, and1100c. For example, the operation mode may include a low power mode and, in this case, the power control signal PCON may include information about a camera module operating at the low power mode and information about a set power level. The levels of power provided to each of the plurality of camera modules1100a,1100b, and1100cmay be identical to or different from each other. In addition, the level of power may be dynamically changed.

As described above with reference toFIGS.1through15, the application processor1200may identify the operation statuses of the plurality of camera modules1100a,1100b, and1100c. When the operation has been completed, the application processor1200may generate the power control signal PCON for blocking power provided to the plurality of camera modules1100a,1100b, and1100c.

The electronic device1000may further include a clock generator (not illustrated). The clock generator may correspond to the clock generator described above (300inFIG.1, and600inFIG.11) with reference toFIGS.1through15. The clock generator may provide a clock signal (CLK_S inFIG.1) to the plurality of camera modules1100a,1100b, and1100caccording to a control of the application processor1200. In other words, the application processor1200may identify the operation status of the plurality of camera modules1100a,1100b, and1100cand when the operation has been completed, may generate a clock control signal (CTRL_CLKS inFIG.1) for blocking the clock signal CLK_S provided to the plurality of camera modules1100a,1100b, and1100c.

FIG.18is a schematic block diagram of an electronic device2000according to an example embodiment. The electronic device2000ofFIG.18may include a mobile terminal.

Referring toFIG.18, the electronic device2000may include an application processor2100, a camera module2200, a working memory2300, a storage2400, a display device2600, a user interface2700, and a wireless transceiver2500.

The application processor2100may control the overall operation of the electronic device2000and may be implemented as a system on chip (SoC) driving application programs, operating systems, etc. The application processor2100may provide the image data provided by the camera module2200to the display device2600or store the image data in the storage2400. The application processor2100may include a low-power controller2110controlling low-power implementation of the camera module2200.

A processor described with reference toFIGS.1through15may correspond to the application processor2100and an image sensor may be applied to the camera module2200. The camera module2200may include a control circuit2210, and the control circuit2210may generate an interrupt signal indicating completion of an operation of the camera module2200and transmit the interrupt signal to the application processor2100. The application processor2100may identify an operation status of the camera module2200based on the interrupt signal and may control a clock signal and a power signal provided to the camera module2200.

The working memory2300may be implemented as a volatile memory, such as dynamic random access memory (RAM) (DRAM) and static RAM (SRAM), or a resistive non-volatile memory, such as ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase change RAM (RRAM). The working memory2300may store programs and/or data, which the application processor2100executes or processes.

The storage2400may be implemented as a non-volatile memory, such as, a NAND flash memory and resistive memory, and the storage2400may be provided as, for example, a memory card (a multi-media card (MMC), an embedded MMC (eMMC), a secure card (SD), and a micro SD), etc. The storage2400may store image data received from the camera module2200or data processed or generated by the application processor2100.

The user interface2700may be implemented as various devices capable of receiving a user input, such as a keyboard, a curtain key panel, a touch panel, a finger-print sensor, and a microphone. The user interface2700may receive the user input and provide to the application processor2100a signal corresponding to the received user input.

The wireless transceiver2500may include a transceiver2510, a modem2520, and an antenna2530.

As is traditional in the field, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the disclosure. An aspect of an embodiment may be achieved through instructions stored within a non-transitory storage medium and executed by a processor.

While the disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.