Patent ID: 12224006

DESCRIPTION OF THE EMBODIMENTS

In order to make the purpose, technical solution and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present disclosure, not to limit the present disclosure. In addition, the technical features involved in the various embodiments of the present disclosure described below can be combined with each other as long as they do not conflict with each other.

The high-speed and large-current adjustable pulse circuit includes a clamping structure, a current mirror structure and a leakage current shutdown structure.

The clamping structure includes a clamping operational amplifier and a first MOS transistor. The non-inverting input terminal of the clamping operational amplifier is configured to connect to a control pulse voltage, an inverting input terminal is grounded through a reference resistor, and the output terminal is connected to a gate of the first MOS transistor. The source terminal of the first MOS transistor is connected with the inverting input terminal of the clamping operational amplifier.

The current mirror structure includes second to fifth MOS transistors. The source terminal of the fourth MOS transistor is connected to the voltage source, the drain terminal thereof is connected to the source terminal of the second MOS transistor, the drain terminal of the second MOS transistor is connected to the drain terminal of the first MOS transistor, the source terminal of the fifth MOS is connected to the voltage source, and the drain terminal thereof is connected to the source terminal of the third MOS transistor. The drain terminal of the third MOS transistor serves as the output terminal of the adjustable pulse circuit, the gate of the second MOS transistor is connected to the gate of the third MOS transistor, and the gate of the fourth MOS transistor is connected to the gate of the fifth MOS transistor. The gate of the second MOS transistor is connected to the drain terminal, and the gate of the fourth MOS transistor is connected to the drain terminal.

The leakage current shutdown structure includes a sixth MOS transistor, a seventh MOS transistor and a buffer. The gates of the sixth MOS transistor and the seventh MOS transistor are respectively connected to the control pulse voltage through the buffer, the gate of the fifth MOS transistor is connected to the voltage source through the sixth MOS transistor, the gate of the third MOS transistor is connected to the voltage source through the seventh MOS transistor. The buffer serves to output and turn off the shutdown voltage of the sixth MOS transistor and the seventh MOS transistor when the control pulse occurs, and output and turn on the turn-on voltage of the sixth MOS transistor and the seventh MOS transistor when the control pulse does not occur.

In the high-speed and large-current adjustable pulse circuit, when the control pulse voltage is applied, the voltage at the inverting input terminal of the operational amplifier is clamped to the same magnitude as the control pulse voltage, and the clamped voltage is applied to the reference resistor Rref to generate a reference current Iref. A current mirror structure is formed by connecting the gate terminals of the second to fifth MOS transistors. By setting the aspect ratio of the MOS transistors inside the current mirror structure, the Iout output from the output terminal of the current mirror structure and the reference current Iref obtained from the input terminal may be in a certain proportion to realize adjustable current.

In the meantime, in the leakage current shutdown structure consisting of the sixth MOS transistor, the seventh MOS transistor and the buffer Buffer, when a control pulse occurs, the output of the Buffer turns off the voltage, and the sixth MOS transistor and the seventh MOS transistor are turned off through the shutdown voltage; the current mirror structure works normally. When the control pulse disappears, the Buffer outputs the turn-on voltage, the sixth MOS transistor and the seventh MOS transistor are turned on through the turn-on voltage, and the gate voltage of the fifth MOS transistor and the third MOS transistor are pulled to the voltage source, which is able to make the third MOS transistor and the fifth MOS transistor to be turned off. In this way, it is possible to significantly reduce the quiescent current at the Iout terminal while accelerating the falling edge of the pulse, thereby facilitating rapid annealing of the phase-change memory cell.

The connected control pulse voltage described above may be a positive pulse voltage Vpulse1or a negative pulse voltage Vpulse2. When the applied control pulse voltage is the positive pulse voltage Vpulse1and the connected voltage source is the positive voltage source VDD, the corresponding first MOS transistor is N-type, and the second to fifth MOS transistors are P-type. When the applied control pulse voltage is negative pulse voltage Vpulse2and the connected voltage source is negative voltage source VSS, the corresponding first MOS transistor is P-type, and the second to fifth MOS transistors are N-type.

As shown inFIG.1, the applied control pulse voltage is positive pulse voltage Vpulse1, the connected voltage source is positive voltage source VDD, the corresponding first MOS transistor M1is N-type, and the second to fifth MOS transistors M2˜M5are P type. When the positive pulse voltage Vpulse1occurs, the drain terminal of the first MOS transistor M1generates a reference current Iref, the buffer Buffer outputs a shutdown voltage, the sixth MOS transistor M6and the seventh MOS transistor M7are turned off, and the current mirror structure works normally. According to the reference current Iref, a proportional output current Iout1is output from the drain terminal of the third MOS transistor M3. When the positive pulse voltage Vpulse1disappears, the buffer Buffer outputs a turn-on voltage, the sixth MOS transistor M6and the seventh MOS transistor M7are turned on the gates of the third MOS transistor M3and the fifth MOS transistor M5are pulled to the voltage source VDD to turn off the MOS transistor. In this way, it is possible to significantly reduce the quiescent current at the Iout terminal while accelerating the falling edge of the pulse, thereby facilitating rapid annealing of the phase-change memory cell.

Similarly, the applied control pulse voltage may be the negative pulse voltage Vpulse2, the connected voltage source is the negative voltage source VSS, the corresponding first MOS transistor is P-type, and the second to fifth MOS transistors are N-type. When the negative pulse voltage Vpulse2occurs, the drain terminal of the first MOS transistor generates a reference current Iref, the buffer Buffer outputs a shutdown voltage, the sixth MOS transistor and the seventh MOS transistor are turned off, and the current mirror structure works normally. According to the reference current Iref, a proportional output current Iout2is output from the drain terminal of the third MOS transistor. When the negative pulse voltage Vpulse2disappears, the buffer Buffer outputs a turn-on voltage, the sixth MOS transistor and the seventh MOS transistor are turned on, and the gates of the third MOS transistor and the fifth MOS transistor are pulled to the voltage source VSS to make the MOS transistor to be turned off. In this way, the quiescent current at the Iout terminal may be considerably reduced, which facilitates rapid annealing of the phase-change memory cell.

In an embodiment, the sixth MOS transistor and the seventh MOS transistor are P-type, under the circumstances, the shutdown voltage output by the buffer Buffer is at high voltage level, and the output turn-on voltage is at low voltage level. When a control pulse occurs, the buffer Buffer outputs a high voltage level, and the sixth MOS transistor and the seventh MOS transistor are turned off. When the control pulse disappears, the buffer Buffer outputs a low voltage level, and the sixth MOS transistor and the seventh MOS transistor are turned on.

In an embodiment, the aspect ratio of the fifth MOS transistor in the current mirror structure is n times the aspect ratio of the fourth MOS transistor, and the aspect ratio of the third MOS transistor is n times the aspect ratio of the second MOS transistor. In this way, the output current may be n times the reference current, and the output current may be adjusted by changing the value of n.

FIG.2is a pulse current waveform diagram of a high-speed and large-current adjustable pulse circuit inFIG.1under a specific condition in the disclosure. The period of the control pulse voltage Vpulse is 200 ns, the amplitude is 2V, the duty cycle is 50%, the reference resistance is set to 200062, the aspect ratio of the second MOS transistor M2is three times that of the third MOS transistor, and the aspect ratio of the four MOS transistor M4is three times that of the fifth MOS transistor. The circuit simulation waveform shows that the reference current IRref on the reference resistor is 1 mA, the output current Iout is 0.33 mA, and the rising edge is about 10 ns.

FIG.3is a pulse current waveform diagram of a high-speed and large-current adjustable pulse circuit inFIG.1under another specific condition in the disclosure. The period of the control pulse voltage Vpulse is 200 ns, the amplitude is 2V, the duty cycle is 50%, and the reference resistance is set to 400Ω. The aspect ratio of the second MOS transistor M2is three times the aspect ratio of the third MOS transistor. The aspect ratio of the fourth MOS transistor M4is three times that of the fifth MOS transistor. The circuit simulation waveform shows that the reference current IRref on the reference resistor is 5 mA, the output current Iout is 1.67 mA, and the rising edge is about 4 ns. In actual implementation of the disclosure, the reference resistance and the input voltage pulse may be changed according to requirements, so as to realize outputting pulse current with different duty ratios and current amplitudes.

Correspondingly, the present disclosure further relates to an operating circuit of a phase-change memory, as shown inFIG.4. The operating circuit includes the first current source and the second current source respectively connected to the two electrodes of the phase-change memory cell PCM. Both the first current source and the second current source adopt the high-speed and large-current adjustable pulse circuit described above. In the first current source, the first MOS transistor is N-type, the second to fifth MOS transistors are P-type, the connected control pulse voltage is positive pulse voltage Vpulse1, the connected voltage source is positive voltage VDD, and the output current is Iout1; in the second current source, the first MOS transistor is P-type, the second to fifth MOS transistors are N-type, the connected control pulse voltage is negative pulse voltage Vpulse2, the connected voltage source is negative voltage VSS, and the output current is Iout2.

For ease of distinction, the first to seventh MOS transistors in the first current source are sequentially marked as M1to M7, and the first to seventh MOS transistors in the second current source are sequentially marked as M8to M14. Among them, M1is N type, M2˜M5are P type, M8is P type, and M9˜M12are N type. In an embodiment, M6, M7, M13, and M14are P-type. In an embodiment, VDD=−VSS, the positive pulse voltage Vpulse1and the negative pulse voltage Vpulse2have the same amplitude and the same frequency. In an embodiment, the first current source and the second current source are integrated in the same semiconductor substrate, and the first current source adopts a deep N-well DNW process to realize electrical isolation of the two power sources.

In the operation circuit of the phase-change memory, the power supply voltage of the first current source on the left is VDD to GND, and the power supply voltage of the second current source on the right is GND to VSS. The combination of the two circuits allows the working voltage of the pulse current to reach VSS˜VDD. Preferably, the magnitude of the VSS voltage is equal to −VDD in value. In actual practice, the output terminal Iout1of the first current source and the output terminal Iout2of the second current source are connected to the phase-change memory cell. By properly selecting the VDD voltage, it may be ensured that all MOS transistors in the circuit structure are in the normal working voltage range. In the meantime, the phase-change memory may also obtain a relatively large operating voltage.

Correspondingly, the present disclosure further relates to an operating method of a phase-change memory, which includes: connecting the operating circuit of the phase-change memory to the phase-change memory cell; connecting the positive pulse voltage Vpulse1to the non-inverting input terminal of the clamping operational amplifier in the first current source, and simultaneously connecting the negative pulse voltage Vpulse2to the non-inverting input terminal of the clamping operational amplifier in the second current source.

As shown inFIG.5.FIG.5is the simulation result of a high-voltage circuit in an embodiment of the present disclosure, in which VDD and VSS are set to 3.3V and −3.3V respectively, and the phase-change memory cell is connected between the Iout1port and the Iout2port. A pulse voltage of 1V is applied to the Vpulse1terminal, a pulse voltage of −1V is applied to the Vpulse2terminal, and the two reference resistors Rref in the circuit are both set to 5KΩ. The resistance value of the phase-change memory serves as a variable for circuit simulation scanning, and thus obtaining the simulation result shown inFIG.5. Vout1indicates the output voltage of the Iout1terminal, and Vout2indicates the output voltage of the Iout2terminal. In the initial stage of erasing and writing operations, the phase-change memory has a relatively large resistance. Under the circumstances, a large voltage is applied to the phase-change memory, and the current value is relatively small as this stage is heat accumulation stage. When the phase-change memory cell enters the variable resistance region after heat accumulation, the resistance value of the phase-change memory is about hundreds of Ω. In the simulation results, it may be seen that in this resistance range, the circuit is able to provide a relatively stable current output.

FIG.6is a pulse current waveform diagram of an operating circuit in an embodiment of the present disclosure. VDD and VSS are respectively set to 3.3V and −3.3V, and a phase-change memory cell is connected between the Iout1port and the Iout2port. A pulse voltage of 1V is applied to the Vpulse1terminal, a pulse voltage of −1V is applied to the Vpulse2terminal, and the two reference resistors Rref in the circuit are both set to 5KΩ. The aspect ratio of M3/M2. M5/M4, M9/M10, and M11/M12is set to five times. The current simulation waveform shows that the reference current IRref on the reference resistor is about 200 uA, and the output current Iout is about 1 mA. The rising edge is about 10 ns, and the falling edge is about 4 ns.

FIG.7is a comparison diagram of simulation results of the leakage current shutdown structure in an embodiment of the present disclosure. The solid line in the figure is the simulation result of the non-leakage current shutdown module, and the dashed line is the simulation result of the leakage current shutdown module. The simulation results of the non-leakage current shutdown module show that the pulse falling edge thereof is about 15 ns, and the leakage current is at the uA level. After adding the leakage current shutdown mechanism, the pulse falling edge may be shortened to about 3.5 ns, and the leakage current is at the pA level. Therefore, it can be obtained that this module significantly speeds up the falling edge of the pulse current source and reduces the leakage current by 6 orders of magnitude. Therefore, the problem of serious leakage and long falling edge of the pulse is solved to a great extent. In this way, the problem generated from the high-amplitude narrow pulse requirement on operating circuit design in the Reset operation may be overcome.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure should all be included within the scope to be protected by the present disclosure.