Patent ID: 12213299

DESCRIPTION OF THE EMBODIMENTS

FIG.1is a top view illustrating a DRAM according to an embodiment of the invention.FIG.2AtoFIG.2Hare cross-sectional views illustrating a manufacturing process of the DRAM along section line I-I′ inFIG.1. In order to clearly illustrate the relationship between the components, some components in the cross-sectional view ofFIG.2Hare omitted in the top view ofFIG.1.

Referring toFIG.1andFIG.2A, a substrate100is provided. The substrate100may be a semiconductor substrate such as a silicon substrate. There may be an isolation structure102in the substrate100. The isolation structure102is, for example, a shallow trench isolation (STI) structure. The material of the isolation structure102is, for example, silicon oxide. In addition, the word line WL passing through the active region AA may be formed. The word line WL may be isolated from the active region AA of the substrate100by a dielectric material (not shown). The word line WL may be a buried word line located in the substrate100, but the invention is not limited thereto. The material of the buried word line is, for example, tungsten (W). Furthermore, the desired doped regions (not shown) may be formed in the substrate100according to requirements.

A bit line stack structure104is formed on the substrate100. The bit line stack structure104includes a bit line structure106and a hard mask layer108. The bit line structure106is located on the substrate100. Moreover, a portion of the bit line structure106may be located on the isolation structure102, and a portion of the bit line structure106may be located on the active region AA to electrically connected to the doped region in the substrate100. The hard mask layer108is located on the bit line structure106. The material of the hard mask layer108is, for example, silicon nitride.

The bit line structure106includes a conductive line110. The conductive line110is located on the substrate100. The material of the conductive line110is, for example, metal such as tungsten. The bit line structure106may further include at least one of a contact112and a barrier layer114. The contact112is located between the conductive line110and the substrate100. In the active region AA ofFIG.1, the contact112of the bit line structure106can electrically connect the conductive line110to the doped region in the substrate100. The contact112may be strip-shaped or column-shaped. In the present embodiment, the contact112is, for example, strip-shaped, so that the contact112can extend above the active region AA and the isolation structure102. In other embodiments, when the contact112is column-shaped, the contact112is located in the active region AA, but not located above the isolation structure102. The material of the contact112is, for example, doped polysilicon. In addition, a dielectric layer116may be formed between the contact112and the isolation structure102. The material of the dielectric layer116is, for example, silicon oxide. The barrier layer114is located between the conductive line110and the contact112. The material of the barrier layer114is, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof. Furthermore, a spacer118may be formed on the sidewall of the bit line stack structure104. The material of the spacer118is, for example, silicon nitride.

Moreover, an active region contact120may be formed on the substrate100on one side of the bit line stack structure104to electrically connect the capacitor contact130a(FIG.2G) subsequently formed over the active region contact120to the doped region (active region AA) in the substrate100. The top surface of the active region contact120may be equal to or higher than the top surface of the contact112. In the present embodiment, the top surface of the active region contact120is, for example, higher than the top surface of the contact112, but the invention is not limited thereto. The material of the active region contact120is, for example, doped polysilicon. Furthermore, the spacer118may be located between the bit line structure106and the active region contact120.

Referring toFIG.2B, an isolation material layer122is conformally formed on the hard mask layer108and the active region contact120. The material of the isolation material layer122is, for example, silicon oxide. The method of forming the isolation material layer122is, for example, an ultra low temperature oxide (ULTO) deposition method.

An etch stop material layer124is conformally formed on the isolation material layer122. The material of the etch stop material layer124is different from the material of the isolation material layer122. The material of the etch stop material layer124is, for example, silicon nitride. The method of forming the etch stop material layer124is, for example, low pressure chemical vapor deposition (LPCVD).

Referring toFIG.2C, a dielectric layer126is formed on the etch stop material layer124. The dielectric layer126may be a single-layer structure or a multilayer structure. For example, the dielectric layer126may be a multilayer structure including a dielectric layer126a, a dielectric layer126b, and a dielectric layer126c. The material of the dielectric layer126ais, for example, silicon oxide. The method of forming the dielectric layer126ais, for example, LPCVD. The material of the dielectric layer126bis, for example, silicon oxide. The method of forming the dielectric layer126bis, for example, high-density plasma chemical vapor deposition (HDPCVD). The material of the dielectric layer126cis, for example, silicon nitride. The method of forming the dielectric layer126cis, for example, chemical vapor deposition (CVD). In the present embodiment, although the dielectric layer126is, for example, a three-layer structure, the invention is not limited to this.

An opening OP is formed in the dielectric layer126. The opening OP exposes the etch stop material layer124located on the sidewall of the hard mask layer108and located above the active region contact120. The method of forming the opening OP is, for example, patterning the dielectric layer126by a lithography process and an etching process. The etching process is, for example, a dry etching process. In addition, the etching process for forming the opening OP may be stopped at the etch stop material layer124, thereby preventing the isolation material layer122from being damaged during the etching process.

Referring toFIG.2D, a portion of the etch stop material layer124exposed by the opening OP is removed to form an etch stop layer124aand to cause the opening OP to expose the isolation material layer122located on the sidewall of the hard mask layer108and located on the active region contact120. The method of removing the portion of the etch stop material layer124is, for example, a wet etching method. When the material of the etch stop material layer124is silicon nitride, the etchant used in the wet etching method is, for example, phosphoric acid.

Referring toFIG.2E, a portion of the isolation material layer122located on the active region contact120is removed to form an isolation layer122aand to cause the opening OP to expose the active region contact120. The isolation layer122ais located on a portion of the top surface of the active region contact120. That is, the width of the bottom surface of the opening OP is smaller than the width of the top surface of the active region contact120. The method of removing the portion of the isolation material layer122is, for example, a dry etching method.

Referring toFIG.2F, a barrier material layer128may be conformally formed on the surface of the opening OP. The material of the barrier material layer128is, for example, Ti, TiN, or a combination thereof. The method of forming the barrier material layer128is, for example, physical vapor deposition (PVD) or atomic layer deposition (ALD).

A conductive layer130filled in the opening OP may be formed. The conductive layer130may be located on the barrier material layer128. The material of the conductive layer130is, for example, metal such as tungsten. The method of forming the conductive layer130is, for example, PVD or CVD.

Referring toFIG.2G, the conductive layer130located outside the opening OP is removed, and a capacitor contact130ais formed in the opening OP to electrically connect the active region contact120to the capacitor136(FIG.2H) subsequently formed above the capacitor contact130a. The method of removing the conductive layer130outside the opening OP is, for example, chemical mechanical polishing (CMP).

In addition, after removing the conductive layer130located outside the opening OP, the barrier material layer128located outside the opening OP is removed to form a barrier layer128a. The barrier layer128a, the capacitor contact130a, and the dielectric layer126may be coplanar. The barrier layer128amay be located on the surface of the opening OP and may be located between the capacitor contact130aand the active region contact120. The method of removing the barrier material layer128outside the opening OP is, for example, CMP.

In this way, a contact structure132may be formed on the substrate100on one side of the bit line stack structure104by the above method. The contact structure132may include the active region contact120and the capacitor contact130a. The contact structure132may further include the barrier layer128a. The active region contact120is located on the substrate100. The capacitor contact130ais located on the active region contact120. The barrier layer128amay be located between the capacitor contact130aand the active region contact120. In addition, the isolation layer122amay be formed between the capacitor contact130aand the bit line stack structure104by the above method. Specifically, the isolation layer122amay be formed on the top surface and the sidewall of the hard mask layer108. Since the isolation layer122ais located between the capacitor contact130aand the bit line stack structure104, the isolation layer122acan isolate the bit line structure106from the capacitor contact130a, thereby effectively preventing the problem of the short circuit between the bit line structure106and the capacitor contact130a. Furthermore, the isolation layer122aand the etch stop layer124amay be formed between the hard mask layer108and the dielectric layer126used to define the opening OP by the above method. In the present embodiment, although the method of forming the isolation layer122a, the etch stop layer124a, and the contact structure132is exemplified by the above method, the invention is not limited thereto.

After the above structure is formed, other subsequent processes may also be performed. For example, as shown inFIG.2H, after the steps described inFIG.2G, an interlayer dielectric layer134and a capacitor136located in the interlayer dielectric layer134may be formed. The capacitor136may include a lower electrode136a, a capacitor dielectric layer136b, and an upper electrode136c. The structure of the capacitor136is for example only, and the invention is not limited thereto. The lower electrode136aof the capacitor136is connected to the capacitor contact130a, so that the capacitor136can be electrically connected to the substrate100via the capacitor contact130aand the active region contact120. Since the processes for forming the interlayer dielectric layer134and the capacitor136are well known to one of ordinary skill in the art, the description thereof is omitted here.

Hereinafter, the DRAM10of the present embodiment is described with reference to FIG.1andFIG.2H. In the present embodiment, although the method of forming the DRAM10is described by taking the above method as an example, the invention is not limited thereto.

Referring toFIG.1andFIG.2H, the DRAM10includes the substrate100, the bit line stack structure104, the dielectric layer126, the contact structure132, the isolation layer122a, and the etch stop layer124a. The DRAM10may further include the spacer118. The bit line stack structure104includes the bit line structure106and the hard mask layer108. The bit line structure106is located on the substrate100. The bit line structure106includes the conductive line110located on the substrate100. In addition, the bit line structure106may further include at least one of the contact112and the barrier layer114. The contact112is located between the conductive line110and the substrate100. The barrier layer114is located between the conductive line110and the contact112. The hard mask layer108is located on the bit line structure106. The dielectric layer126is located on the bit line stack structure104and has the opening OP. The contact structure132is configured to electrically connect the capacitor136to the active region AA of the substrate100. The contact structure132is located on the substrate100on the side of the bit line stack structure104. The contact structure132includes the active region contact120and the capacitor contact130a. The contact structure132may further include the barrier layer128a. The active region contact120is located on the substrate100. The top surface of the active region contact120is exposed by the opening OP. The top surface of the active region contact120may be equal to or higher than the top surface of the contact112. The capacitor contact130ais located in the opening OP over the active region contact120. The barrier layer128ais located between the capacitor contact130aand the active region contact120. The isolation layer122ais located between the hard mask layer108and the dielectric layer126and located between the capacitor contact130aand the bit line stack structure104to electrically isolate the capacitor contact130afrom the bit line stack structure104. Specifically, the isolation layer122ais located on the top surface and the sidewall of the hard mask layer108, and the isolation layer122amay be further located on a portion of the top surface of the active region contact120, so that the width of the bottom surface of the capacitor contact130ais smaller than the width of the top surface of the active region contact120. The etch stop layer124ais located between the dielectric layer126and the isolation layer122a. The area of the isolation layer122aexposed by the opening OP is greater than the area of the etch stop layer124aexposed by the opening OP. The material of the etch stop layer124ais different from the material of the isolation layer122a. For example, the material of the isolation layer122amay be silicon oxide, and the material of the etch stop layer124amay be silicon nitride. The spacer118is located on the sidewall of the bit line stack structure104and may be located between the bit line structure106and the contact structure132.

The remaining components in the DRAM10can refer to the description of the above embodiment. In addition, the material, the arrangement, the formation method, and the effect of each component in the DRAM10have been described in detail in the aforementioned embodiments, and the description thereof is not repeated here.

Based on the above embodiment, in the DRAM10and the manufacturing method thereof, the isolation layer122ais located between the capacitor contact130aand the bit line stack structure104. In this way, the isolation layer122acan be used to isolate the bit line stack structure104from the capacitor contact130a, so that the problem of the short circuit between the bit line structure106and the capacitor contact130acan be effectively prevented, thereby improving the reliability of the DRAM. Furthermore, the isolation layer122aand the etch stop layer124aare formed between the hard mask layer108and the dielectric layer126used to define the opening OP, so that the problem of the short circuit between the adjacent active region contacts120can be prevented, thereby improving the reliability of the DRAM.

Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.