Patent ID: 12205995

DESCRIPTION OF THE EMBODIMENTS

This disclosure relates to a semiconductor device and a method for fabricating the same. The semiconductor device is, for example, a structure of a high-voltage transistor. In an embodiment, the high-voltage transistor includes a field plate to assist in operating a gate structure to control a channel region in a substrate.

In an embodiment, a structure of a transistor may be achieved by using a fabrication process that is compatible with a fabrication process of a general device in other regions, which can improve an insulation capability between the field plate and the substrate in a drain region.

Some exemplary embodiments are listed below to illustrate the disclosure, but the disclosure is not limited thereto. Appropriate combinations between the multiple embodiments are also allowed.

FIG.1is a schematic diagram of a cross-sectional structure of a semiconductor device that is being looked into according to an embodiment of the disclosure. With reference toFIG.1, the disclosure looks into the performance of, for example, a LDMOS transistor. A gate structure100of the transistor is disposed on a substrate50. The gate structure100includes a gate insulating layer102and a gate layer (G)104. As usual, there will be some doped regions corresponding to the conductivity type in the substrate50, which would not be described here. The doped region of the disclosure is not limited to a specific structure. With regards to the control of the gate, a field plate layer108is formed on the gate structure100at a drain end based on the need for a high-voltage operation. The field plate108is above the gate structure100and the substrate50, and insulation is provided by a dielectric layer106. In addition, a gap wall110, for example, may also be formed on a side wall of the structure.

The field plate layer108and the gate layer104are connected to a same gate voltage VG. A part of the field plate layer108is shown on the substrate50to provide assistance to a control function of a channel. The drain region of the gate structure100abuts the field plate layer108and receives a drain voltage VD. A source region of the gate structure100receives a source voltage VS.

A dielectric layer106provides an insulation capability between the field plate layer108and the substrate50. As per the looking into by the disclosure, if a thickness of the dielectric layer106is insufficient, for example, as illustrated by a marked area112, it may generate an excessively high electric field and prone to causing a collapse. In the disclosure, the insulation capability between the field plate layer108and the substrate50is being improved under a condition that is compatible with the fabrication process of the devices in the other regions, after looking into the structure of the transistor as shown inFIG.1.

FIG.2is a schematic diagram of a cross-sectional structure of a semiconductor device according to another embodiment. With reference toFIG.2, in an embodiment, an overall gate insulating layer may include a first gate insulating layer102and a second gate insulating layer102a. The first gate insulating layer102abuts the second gate insulating layer102a, and both layers are disposed on the substrate50. A thickness of the second gate insulating layer102ais, for example, greater than a thickness of the first gate insulating layer102.

The gate layer104is formed on the first gate insulating layer102and the second gate insulating layer102a. The gate layer104has a first part gate104aon the first gate insulating layer102. The gate layer104also has a second part gate104bon the second gate insulating layer102a. In this way, the gate layer104and the substrate50will achieve a greater insulation capability near the drain end. The second gate insulating layer102ais, for example, a structure of a field oxide layer, so as to obtain a greater thickness, but is not limited thereto.

In an embodiment, for example, both the first gate insulating layer102and the second gate insulating layer102aare oxides. In an embodiment, a dielectric layer102bthat is an oxide may also be formed on the substrate50first according to a change in the fabrication process. The dielectric layer102bis configured to provide insulation between the substrate50and a subsequently formed field plate layer206.

In an embodiment, the dielectric layer102bmay be a part of an overall dielectric layer200. In an embodiment, the dielectric layer200includes a top dielectric layer200acovering the gate layer104, such as covering the second part gate104b. The dielectric layer200also includes a bottom dielectric layer200ccovering the substrate50. The dielectric layer200also includes a vertical layer200bat a side wall of the gate layer104, which connects the bottom dielectric layer200cand the top dielectric layer200a. As mentioned previously, the bottom dielectric layer200cincludes the bottom dielectric layer102b.

In an embodiment, the dielectric layer200is, for example, a nitride or an oxide, and the top dielectric layer200a, the vertical layer200b, and the bottom dielectric layer200cmay be formed together. The dielectric layer102bmay be formed first during the process of forming other devices, but is not limited thereto.

In an embodiment, both the top dielectric layer200aand the vertical layer200bare nitride layers, and the bottom dielectric layer200cis a stacked layer of an oxide and a nitride.

In an embodiment, the field plate layer206is formed on the dielectric layer200. It should be noted here that a material of the field plate layer206, in an embodiment, forms a doped layer202such as a doped silicon layer or a doped polysilicon layer according to, for example, a deposition manner or an epitaxial growth manner. In addition, the depleted region204may be formed in the field plate layer206according to the technology of the doping process. The depleted region204may, for example, also be an undoped region or at a level close to being undoped. A function of the depleted region204may be to provide the insulation capability. Therefore, in actual effect, the depleted region204is formed through the control of the doping technology during the process of forming the field plate layer206, so as to substantially provide the function of an insulating layer. In such an embodiment, the bottom dielectric layer200cof the dielectric layer200may not need to form an insulating layer to increase thickness, so as to achieve the insulation capability. The insulation capability may be provided by the depleted region204of the field plate layer206. The depleted region204may provide an additional insulating layer in the substantial effect.

The formation of the depleted region204may be controlled or adjusted by, for example, an implanting process. In an embodiment, when the depleted region204uses an epitaxial growth process, it may be formed by controlling the dopants during the growth process. The formation of the depleted region204is not limited to a specific manner.

FIG.3is a schematic diagram of a cross-sectional structure of a semiconductor device according to yet another embodiment of the disclosure. With reference toFIG.3, in an embodiment, the formation of the depleted region204may also be to cover the dielectric layer200completely. The formation of the dielectric layer200is as described previously and will not be reiterated here.

FIG.4is a schematic diagram of a cross-sectional structure of a semiconductor device according to still another embodiment. With reference toFIG.4, in an embodiment, the dielectric layer200may be a single-layer structure of the same material according to a change in the fabrication process. The bottom dielectric layer200cis, for example, an oxide or a nitride, instead of a stacked layer of an oxide and a nitride.

The dielectric layer200of the disclosure may be compatibly formed according to the fabrication process of the devices in the other regions. The depleted region204is formed during the formation of the field plate layer206, under a condition of a thickness that the dielectric layer200may be formed, which may further provide the function of an insulating layer to improve the insulation capability at the drain end, thereby increasing the collapse voltage.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the disclosure, and are not intended to limit them. Although the disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still make changes and modifications to the technical solutions described in the foregoing embodiments, or equivalently replace some or all of the technical features without departing from the spirit and the scope of the disclosure. Accordingly, the scope of the disclosure is defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated.