Patent ID: 12199004

DETAILED DESCRIPTION

Techniques disclosed herein relate generally to electronic packages that include one or more gallium nitride power transistors. More specifically, techniques disclosed herein relate to electronic packages that enable efficient cooling of electronic packages that include gallium nitride power transistors that have electrically biased substrates. Various inventive embodiments are described herein, including methods, processes, systems, devices, and the like.

Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part hereof. The ensuing description provides embodiment(s) only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the embodiment(s) will provide those skilled in the art with an enabling description for implementing one or more embodiments. It is understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and description are not intended to be restrictive. The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

FIG.1illustrates a simplified partial cross-sectional view of an electronic package100that includes a pair of gallium nitride (GaN) semiconductor die and top-sided cooling, according to embodiments of the disclosure. As shown inFIG.1electronic package100includes first and second GaN die105,110, respectively, that are arranged to form a portion of a half-bridge power converter, however, in other embodiments a greater number or fewer number of GaN die may be used and may be employed for different circuit functions. In this particular example embodiment, first GaN die105is a high side transistor and second GaN die110is a low side transistor of a synchronous buck converter circuit. First and second GaN die,105,110, respectively, are attached to a substrate115in a flip-chip configuration, that is with the active device and interconnect side of each die facing the substrate. Electrical interconnects120are formed between first and second GaN die,105,110, respectively, and substrate115which in one embodiment are copper pillars that are soldered to the substrate, however in other embodiments the interconnects can comprise solder balls, solder pads or can be any other suitable interconnect structure. The flip-chip configuration leaves a back surface125of each of first and second GaN die,105,110, respectively exposed which will be discussed in more detail below.

An integral heatsink130includes a layer of non-electrically conductive ceramic135(e.g., Al2O3, AlN, BeO, etc.) sandwiched between a top and a bottom layer of copper,140a,140b, respectively. In some embodiments integral heatsink130may be a direct-bonded copper (DBC) substrate or insulated metal substrate (IMS) assembly, however other suitable configurations can be used. Both DBC and IMS substrates typically employ a ceramic-containing layer sandwiched between a top and a bottom metal layer. As defined herein a ceramic containing layer includes a layer formed entirely or partially of ceramic, including a polymer ceramic composite that is commonly used in IMS substrates. In some embodiments the metals are copper, aluminum, a combination thereof or other suitable materials. In some embodiments, bottom layer140bof copper can be divided into two electrically isolated regions with a first isolated region145aattached to the exposed back side125of first GaN die105and a second isolated region145battached to the exposed back side125of second GaN die110using electrically conductive epoxy, solder, silver, fully and/or partially sintered silver or other suitable electrically conductive material. Each of first and second isolated regions145a,145b, respectively can be electrically coupled to substrate115via one or more extended copper pillars150(e.g., 100 micron or other suitable height) that can be attached with solder or other suitable electrically conductive material (e.g., solder or electrically conductive adhesive). In further embodiments other suitable interconnect structures can be used such as, but not limited to leads, wires, clips, wings or components (e.g., resistor, capacitor, etc. that is vertically oriented between bottom layer145aand substrate115). First and second isolated regions145a,145bcan be independently electrically biased via substrate115to apply appropriate voltage biases to a bulk substrate of each of first and second GaN die105,110, respectively.

In some embodiments top layer of copper140ais continuous which enables efficient lateral spreading of thermal energy produced by first and second GaN die105,110, respectively, and thus enables a reduced thermal power density at a top surface155of the electronic package100. Top layer140aof copper can be substantially exposed at top surface155of electronic package100so it can be directly thermally coupled to a cold plate165, heat sink or other apparatus via a thermal interface material160to efficiently transfer thermal energy from each of first and second GaN die,105,110, respectively, through bottom layer140bof copper, through ceramic135through thermal interface material160and to coldplate165. Ceramic135within integral heatsink130provides electrical isolation between top layer of copper140aand the bulk substrates of first and second GaN die145a,145b, respectively, and also provides electrical isolation between each of the bulk substrates of each GaN die. In some embodiments ceramic135is approximately 250 microns thick and top layer140aand bottom layer140bof copper are each approximately 300 microns thick, however other suitable thicknesses can be used.

In some embodiments one or more control and/or isolation ICs170can be attached to substrate115and configured to provide control signals and/or drive transistors formed in first and second GaN die105,110, respectively. Control and/or isolation ICs170can be electrically coupled to substrate115using wirebonds, flip-chip technology or other suitable interconnects. Control and/or isolation ICs170can provide isolation, short circuit protection, control of switching waveforms, overshoot protection, fault reporting, over temperature protection, ESD protection and/or other features and functions as described in greater detail below.

As described herein, in this particular embodiment first and second GaN die105,110form a portion of a half-bridge buck converter circuit where substrate115includes a VIN terminal151, a switch-node terminal153and a ground terminal157. The close proximity of first GaN die105and second GaN die110along with the large cross-sectional area of copper forming the switch-node terminal153connecting first GaN die105and second GaN die110(formed within substrate115in this embodiment) can enable package100to have ultra-low gate loop inductance and ultra-low commutation loop inductance enabling increased switching speeds and improved circuit stability.

One or more integrated passive electronic components175(e.g., resistors, capacitors, inductors) can be attached to substrate115along with other discrete active components (e.g., diodes, thyristors, etc.). In some embodiments the one or more passives175can be combined with a switching function in control and/or isolation ICs170to provide a bootstrap circuit. In some embodiments substrate115is a multilayer organic-based substrate such as, but not limited to a four layer BT substrate with a plurality of copper layers interconnected by a plurality of vias, however, in further embodiments other suitable materials and numbers of electrical routing layers can be used. Electronic package100can be encapsulated with a mold compound180or other suitable material that is substantially co-planar with the top layer140aof copper, or sub-flush, such that the top layer of copper can be in intimate contact with thermal interface material160and the cold plate165.

FIG.2illustrates a simplified bottom plan view of package100illustrated inFIG.1. As shown inFIG.2substrate115includes a land-grid array with three large power connections including a Vin pad205(Vin terminal151) coupled to the first GaN die105(e.g., functioning as a high side die in the half-bridge circuit), a SW (switch-node) pad210(switch-node terminal153) coupled to the interconnect formed between the first and second GaN dies,105,110, respectively, and a PGND pad215(ground terminal157) coupled to the second GaN die110(e.g., functioning as a low side die in the half-bridge circuit). Substrate115also includes a plurality of I/O connections220that can couple signals into and out of package100, such as gate control signals, fault signals, logic power signals and the like.FIG.2is one example of the electrical connections that can be formed on package100and further embodiments can have other suitable arrangements, sizes and configurations of connections.

FIG.3illustrates a simplified top view of package100illustrated inFIGS.1and2. As shown inFIG.3top layer of copper140aof integral heatsink130is exposed and is surrounded by mold compound180. In some embodiments top layer of copper140ais coplanar with the mold compound however in other embodiments the mold compound is sub-flush so the copper extends slightly out of the top of the package to facilitate forming a reliable interface with a thermal interface material. In some embodiments top surface165can be anodized, plated or coated with a paint, thermal interface material or other suitable material.

FIG.4illustrates a simplified partial cross-sectional view of an electronic package400that has similar features as electronic package100illustrated inFIGS.1-3(with similar reference numbers indicating similar features), however electronic package400includes two ePads in place of integral heatsink130used in electronic package100. In some embodiments ePads405,410can be made primarily from copper that is plated with one or more metals, however other embodiments may comprise copper tungsten alloys, copper beryllium alloys, silver, gold, aluminum, ceramic, diamond, silicon-carbide or other suitable material. As shown inFIG.4package400includes high side and low side GaN dies105,110, respectively, that are each coupled to a separate copper ePad405,410, respectively that are each approximately 200 microns thick. ePads405,410are electrically isolated from each other and are electrically coupled to the respective GaN die bulk substrates,105,110and to substrate115. Substrate115can apply a separate bias voltage to a bulk substrate of each die105,110. In some embodiments an electrically insulative thermal interface material460is used between ePads405,410and cold plate165to insure electrical isolation. In some embodiments package400may have a reduced thermal impedance as compared to electronic package100illustrated inFIGS.1-3because of the removal of the ceramic interlayer which can have a lower thermal conductivity than that of copper. However, in other embodiments package100may have a reduced thermal impedance provided the integral heatsink is large enough to reduce the power density to efficiently traverse the thermal interface material.

FIG.5illustrates a simplified bottom view of electronic package400illustrated inFIG.4and shows a land grid array similar to the interconnect layout of electronic package100.

FIG.6illustrates a simplified top view of electronic package400illustrated inFIGS.4and5. As shown inFIG.6, there are two separate electrically biased ePads405,410exposed at a top surface415of electronic package400.

FIG.7illustrates a simplified partial cross-sectional view of an electronic package700that has similar features as electronic package100illustrated inFIGS.1-3(with similar reference numbers indicating similar features), however electronic package700includes GaN and silicon die in intermediate packages705,710. As shown inFIG.7, electronic package700includes high side and low side GaN die715,720that are each in separate intermediate electronic packages,705,710, respectively. In this particular embodiment, GaN die715,720have back surfaces725that are each attached to leadframe portions727,729(also called paddles) using electrically conductive epoxy, solder, silver, fully and/or partially sintered silver or other suitable electrically conductive material. Leadframe portions727,729are attached to isolated regions145a,145bof integral heat sink130using electrically conductive epoxy, solder, silver, fully and/or partially sintered silver or other suitable electrically conductive material.

As further shown inFIG.7, in this embodiment, intermediate electronic packages705,710each include a separate control die730,735, respectively, that can be silicon, GaN or other semiconductor device that is coupled to GaN die715,720, respectively. GaN die715,720and control die730,735can be electrically connected to intermediate electronic packages705,710via wirebonds, flip-chip or other suitable interconnect method and overmolded with molding material740. In some embodiments bulk substrates of GaN die715,720can be electrically biased via intermediate package connections and/or via external connections similar to extended copper pillars150(seeFIG.1). In this embodiment intermediate electronic packages705,710are dual-flat no-lead (DFN) packages, however, the intermediate packages can be any suitable wirebond, flip-chip, chip-scale or other package and can include a metallic pad to which one or more GaN and/or silicon die are attached.

In some embodiments the use of intermediate electronic packages705,710can enable improved yield of electronic package700because of the ability to test the intermediate electronic packages705,710before integration. Further, the use of intermediate electronic packages705,710may enable simplified assembly of electronic package700due to the increased feature size of the intermediate electronic packages and the reduced cleanliness and handling procedures as compared to those required when processing bare die.

In some embodiments mold compound180can be selected to act as an underfill material that fills in gaps between intermediate electronic packages705,710and electronic package700. In various embodiments the coefficient of thermal expansion (CTE) of the mold compounds180,740and the integral heatsink130can be selected to be approximately the same to minimize internal stresses.

FIG.8illustrates a plan view of bottom layer of copper140bof integral heatsink130. As shown inFIG.8, in some embodiments interface region805between first isolated region145aand second isolated region145bcan be arranged in an irregular, stair-step, saw-tooth or other suitable geometry to increase adhesion of the copper to the ceramic.

FIG.9illustrates a simplified partial cross-sectional view of an electronic package900that has similar features as electronic package700illustrated inFIG.7(with similar reference numbers indicating similar features), however electronic package900includes a two-phase architecture as compared to electronic package700that has a single-phase architecture. As shown inFIG.9, electronic package900includes a first phase half-bridge circuit905and a second phase half-bridge circuit910. Each phase can include separate high-side and low-side GaN-based transistors as explained in more detail herein. Other embodiments can include three-phase, four-phase or a greater number of phases within a single electronic package.

As further shown inFIG.9, electronic package900includes through-hole pins915positioned within substrate920. Through-hole pins915can be configured to be soldered into vias of a receiving board, connected to a socket or press-fit into vias of a receiving board. Any of the electronic packages disclosed herein can use the thru-hole configuration and similarly, electronic package900can also be configured as a land-grid array as shown inFIGS.1-2.

FIG.10illustrates a simplified partial cross-sectional view of an electronic package1000that has similar features as electronic package700illustrated inFIG.7(with similar reference numbers indicating similar features), however electronic package1000is a bottom-cooled architecture with inverted intermediate electronic packages. As shown inFIG.10, electronic package1000includes two intermediate electronic packages1005,1010that each include a GaN transistor1015,1020, respectively attached to a leadframe portion1025,1030of each respective intermediate electronic package. In some embodiments each intermediate electronic package1005,1010can include one or more control devices, as described herein. However, in this embodiment, control device1035is shown outside of intermediate electronic packages and attached to substrate1040. In some embodiments substrate1040can be what is commonly referred to as an insulated metal substrate (IMS) that has a relatively high thermal conductivity enabling thermal energy to be coupled from GaN transistors1015,1020to a cold plate1040via a thermal interface material1045.

FIG.11illustrates a simplified partial cross-sectional view of an electronic package1100that has similar features as electronic package900illustrated inFIG.9(with similar reference numbers indicating similar features), however electronic package1100includes a two-phase architecture within a through-hole module1100. As shown inFIG.11, module1100includes a plastic body1105including a plurality of through-hole pins1110that can either be a solder-in configuration or a press-fit configuration. Plastic body1105can include a cavity1115that receives substrate1120coupled to pins1110. Substrate1120can includes four GaN based transistors1125a-1125dthat are all coupled to a unitary integral heatsink1130. GaN-based transistors1125a-1125dcan be placed within intermediate packages as shown, for example inFIG.7or can be bare die as shown, for example inFIGS.1and4. Integral heatsink1130can have any of the configurations shown herein or any other suitable configuration. Cavity1115can be filled in with a fill material1135that can be any type of gel, filler, mold-compound, underfill or any other suitable material. One or more control die can be attached to substrate1120or positioned within intermediate electronic packages as disclosed herein. A greater number or a lesser number of phases can be formed within module1100as appreciate by one of ordinary skill in the art having the benefit of this disclosure.

FIG.12illustrates a simplified electrical schematic of a single-phase half-bridge circuit1200that can be employed in any of the electronic packages shown herein. A first GaN die1205is a high side GaN transistor and second GaN die1210is a low side GaN transistor that are coupled together in a half-bridge configuration forming a switch node (Vsw)1215between the two die. First GaN die1205can be coupled to a first control die1220and second GaN die1210can be coupled to a second control die1225. Control die1220,1225can each include one or more of the following circuits: gate driver, under voltage lock out, dV/dt detection and protection, power regulation, over temperature protection, level-shifting, boot strap power supply, isolation, over current protection, trim functions and/or protection circuitry. Each control die1220,1225can be arranged to receive a control signal from a controller1230via an optional isolator device1235that can be, for example an optically coupled, digitally coupled, magnetically coupled or other suitable type of isolation device. In other embodiments isolator device1235may not be used. In some embodiments isolator1235, control die1220,1225and first and second GaN die,1205,1210, respectively, can be integrated within a single electronic package1240, however, other embodiments may have one or more of these devices integrated within the electronic package.

FIG.13illustrates steps associated with a method1300of forming an electronic package, according to embodiments of the disclosure. Step1305includes the formation of a substrate. In some embodiments the substrate may be a multilayer printed circuit board however in other embodiments it may only have one layer and/or may be made from other materials such as, for example ceramics, metals, dielectrics and the like.

Step1310includes the formation of one or more GaN die. In some embodiments each GaN die can include one or more transistors, however, in other embodiments each GaN die can include one or more logic, driver and/or control circuits. In some embodiments each GaN die can have an active surface that includes the one or more transistors, positioned opposite of a back surface which is a portion of the bulk semiconductor substrate.

Step1315includes the attachment of the one or more GaN die to the substrate. In some embodiments the one or more GaN die are attached to the substrate in a flip-chip configuration wherein the active surface of the die faces the substrate, however in other embodiments the die can be attached where the back side attaches to the substrate and the active surface is electrically coupled to the substrate via wirebonds.

Step1320includes the formation of an integral heatsink. In some embodiments the integral heatsink includes a layer of ceramic sandwiched between two layers of copper an may be known as a direct-bonded copper (DBC) or insulated metal substrate (IMS). In other embodiments the integral heatsink may include one or more layers of relatively high thermal conductivity materials such as copper, aluminum, ceramic, diamond and the like.

Step1325includes the attachment of the integral heatsink to the one or more GaN die and electrically coupling the integral heatsink to the substrate. In some embodiments the integral heatsink can be electrically and thermally coupled to the one or more GaN die with solder, electrically conductive adhesive, sintered silver, diffusion bonding or other suitable technique. In various embodiments the integral heatsink can be electrically coupled to the substrate such that the substrate can apply an electrical bias via the integral heatsink to the bulk semiconductor substrate. In some embodiments a column, lead or other interconnect can be used to apply an electrical bias voltage from the substrate to each GaN die.

Step1330includes the encapsulation of the one or more GaN die and at least a portion of the integral heatsink. In some embodiments a mold compound is used however in other embodiments any type of gel, underfill or other suitable material can be used.

It will be appreciated that process1300is illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

Although the GaN die discussed in the preceding embodiments are described as forming half-bridge circuits one of ordinary skill in the art having the benefit of this disclosure will appreciate that single GaN devices as well as any number of GaN devices can be used for different electrical purposes and can be employed according to one or more of the disclosed embodiments. For example, in one embodiment a series of GaN devices can be employed in a multi-phase motor driver circuit while in another embodiment a plurality of GaN devices can be used for a high speed, high power multiplexing switch matrix. Any of these embodiments can be integrated in one or more of the packaging configurations disclosed herein.

For simplicity, various peripheral components, such as capacitors, resistors, diodes and the like are not shown in the figures and the electrical schematics.

In some embodiments the GaN-based die can include one or more gallium nitride and/or other layers formed on a silicon-based substrate, where the active device(s) are formed in the one or more gallium nitride layers and the silicon acts as a bulk substrate for the die. The GaN transistors can include a two-degree electron gas region in which a conductive channel may be formed.

In the foregoing specification, embodiments of the disclosure have been described with reference to numerous specific details that can vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the disclosure, and what is intended by the applicants to be the scope of the disclosure, is the literal and equivalent scope of the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. The specific details of particular embodiments can be combined in any suitable manner without departing from the spirit and scope of embodiments of the disclosure.

Additionally, spatially relative terms, such as “bottom or “top” and the like can be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as a “bottom” surface can then be oriented “above” other elements or features. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Terms “and,” “or,” and “an/or,” as used herein, may include a variety of meanings that also is expected to depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, the term “at least one of” if used to associate a list, such as A, B, or C, can be interpreted to mean any combination of A, B, and/or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

Reference throughout this specification to “one example,” “an example,” “certain examples,” or “exemplary implementation” means that a particular feature, structure, or characteristic described in connection with the feature and/or example may be included in at least one feature and/or example of claimed subject matter. Thus, the appearances of the phrase “in one example,” “an example,” “in certain examples,” “in certain implementations,” or other like phrases in various places throughout this specification are not necessarily all referring to the same feature, example, and/or limitation. Furthermore, the particular features, structures, or characteristics may be combined in one or more examples and/or features.

In some implementations, operations or processing may involve physical manipulation of physical quantities. Typically, although not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, or otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, or the like. It should be understood, however, that all of these or similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, as apparent from the discussion herein, it is appreciated that throughout this specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” or the like refer to actions or processes of a specific apparatus, such as a special purpose computer, special purpose computing apparatus or a similar special purpose electronic computing device. In the context of this specification, therefore, a special purpose computer or a similar special purpose electronic computing device is capable of manipulating or transforming signals, typically represented as physical electronic or magnetic quantities within memories, registers, or other information storage devices, transmission devices, or display devices of the special purpose computer or similar special purpose electronic computing device.

In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of appended claims, and equivalents thereof.