Patent ID: 12189765

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

FIG.2is a block diagram of a memory system200in accordance with various embodiments of the present invention.FIG.2shows only a portion directly related to an address in the memory system200.

Referring toFIG.2, the memory system200may include a memory controller210and a memory module220.

The memory controller210may control the operations of the memory module220such as an active operation, a read operation, and a write operation according to a request of a host. The memory controller210may transfer an address ADD for selecting an area to be accessed in the memory module220to the memory module220.

The memory module220may include a plurality of memories221to229. The memories221to229may be one of different types of memories, such as a Dynamic Random Access Memory (DRAM), a Phase Change Random Access Memory (PCRAM), a flash memory and the like. The memories221to229may respectively include cell arrays231to239, and an area designated by an address ADD may be accessed in the cell arrays231to239.

The memory module220may be a Dual In-Line Memory Module (DIMM) type. The memories221to229may share the same address ADD and may simultaneously perform the same operation. For example, a total of 576 bits of information including 512 bits of data and 64 bits of ECC code may be written into the memory module220during a write operation. Herein, 576 bits of the data and the ECC code may be divided such that 64 bits of information may be written to each of the memories221to229. Similarly, during a read operation, 64-bit information may be outputted from each of the memories221to229so that 576-bit information (which includes 512-bit data and 64-bit ECC code) may be transferred to the memory controller210.

In the memory system200ofFIG.2, all of the memories221to229may share the same address ADD, which may increase the vulnerability of the memory module220to a low hammer. For example, when an Athword line is accessed many times over within a short period of time and then an (A+1)thword line is accessed in the memories221to229, a probability that an error occurs may be increased in all of the memories221to229. When the probability that an error occurs in all the memories221to229increases, the number of errors may increase, accordingly. Therefore, the possibility of exceeding the number of errors that are correctable by an ECC circuit in the memory controller210may increase, which may cause a malfunction of the system200.

FIG.3is a block diagram of a memory system300in accordance with various embodiments of the present invention.FIG.3shows only a portion directly related to an address in the memory system300.

Referring toFIG.3, the memory system300may include a memory controller310and a memory module320.

The memory controller310may control the operations of the memory module320such as an active operation, a read operation, and a write operation according to a request of a host. The memory controller310may transfer an address ADD for selecting an area to be accessed in the memory module320to the memory module320.

The memory module320may include a plurality of memories321to329. The memories321to329may be one of different types of memories, such as a Dynamic Random Access Memory (DRAM), a Phase Change Random Access Memory (PCRAM), a flash memory and the like. The memories321to329may respectively include scrambling circuits341to349and cell arrays331to339.

The scrambling circuits341to349of the memories321to329may scramble an address ADD to generate scrambled addresses ADD_S0 to ADD_S8. The scrambling circuits341to349may receive the same address ADD. However, the scrambling results, which are the scrambled addresses ADD_S0 to ADD_S8, may be different from each other.

The cell arrays331to339of the memories321to329may be accessed based on the scrambled addresses ADD_S0 to ADD_S8.

Since the cell arrays331to339can be accessed by different scrambled addresses ADD_S0 to ADD_S8, different areas may be accessed in the cell arrays331to339.

The memory module320may be a Dual In-Line Memory Module (DIMM) type. The memories may share the same address ADD and may simultaneously perform the same operation. For example, a total of 576 bits of information including 512 bits of data and 64 bits of ECC code may be written into the memory module320during a write operation. Herein, 576 bits of the data and the ECC code may be divided such that 64 bits of information can be written to each of the memories321to329. Similarly, during a read operation, 64-bit information may be outputted from each of the memories321to329so that 576-bit information (which includes 512-bit data and 64-bit ECC code) may be transferred to the memory controller310.

The memory module320may be types other than the DIMM. For example, the memories321to329and the memory controller310may be attached onto the same Printed Circuit Board (PCB) substrate. The memory system300may have diverse forms of a physical structure.

The scrambling circuits341to349of the memories321to329may operate to reduce the influence of an error occurring due to row hammering in the memory system300. The scrambling circuits341to349may perform a scrambling operation such that the neighboring word lines, adjacent to a word line selected by a first address received from the memory controller310, may be selected at most in one memory among the memories321to329by a second address received from the memory controller310.

Herein, active commands along with an N address ADD are applied from the memory controller310to the memory module320several times. In this case, different words lines may be activated several times by the scrambling circuits341to349in the memories321to329. In other words, an Athword line may be activated a plurality of times in the memory321, and a Bthword line may be activated a plurality of times in the memory322, and a Cthword line may be activated a plurality of times in the memory323, and a Dthword line may be activated a plurality of times in the memory324, and an Ethword line may be activated a plurality of times in the memory325, and an Fthword line may be activated a plurality of times in the memory326, and a Gthword line may be activated a plurality of times in the memory327, and an Hthword line may be activated a plurality of times in the memory328, and an Ithword line may be activated a plurality of times in the memory329(where A to I are different arbitrary integers that are equal to or greater than 0). In this case, the data of the (A+1)thand (A−1)thword lines may be deteriorated by row hammering in the memory321, and the data of the (B+1)thand (B−1)thword lines may be deteriorated by row hammering in the memory322, and the data of the (C+1)thand (C−1)thword lines may be deteriorated by row hammering in the memory323, and the data of the (D+1)thand (D−1)thword lines may be deteriorated by row hammering in the memory324, and the data of the (E+1)thand (E−1)thword lines may be deteriorated by row hammering in the memory325, and the data of the (F+1)thand (F−1)thword lines may be deteriorated by row hammering in the memory326, and the data of the (G+1)thand (G−1)thword lines may be deteriorated by row hammering in the memory327, and the data of the (H+1)thand (H−1)thword lines may be deteriorated by row hammering in the memory328, and the data of the (I+1)thand (I−1)thword lines may be deteriorated by row hammering in the memory329.

Subsequently, herein an active command is applied from the memory controller310to the memory module320along with an M address ADD, and a read operation is performed. In this case, when a word line adjacent to the word line that is activated by the N address ADD may be activated at most in one memory among the memories321to329by the scrambling circuits341to349, the number of memories that output the data affected by the row hammering may be at most one among the memories321to329.

For example, if the (C+1)thword line that is affected by row hammering is selected in the memory323based on the M address ADD, word lines that are not affected by the row hammering may be selected in the remaining memories321,322, and324to329. When the data affected by the row hammering are outputted from at most one memory among the nine memories321to329during a read operation, the ECC circuit of the memory controller310may easily correct the errors because the amount of the errors is small. In short, the data deterioration caused by row hammering may not affect the operation of the memory system300at all.

FIG.4illustrates a scrambling method of the scrambling circuits341to349shown inFIG.3.FIG.4describes one example of the scrambling methods for allowing neighboring word lines at most in one memory of the memories321to329to be selected based on two arbitrary addresses ADD.FIG.4exemplarily shows an address ADD of 17 bits. A<0> to A<16> in the figure may represents the 17 bits constituting the address ADD.

The scrambling circuits341to349may scramble the address ADD through a scrambling method of selectively inverting X bits (X is a positive integer) among the remaining bits of the address ADD excluding lower X bits of the address ADD in response to the lower X bits of the address ADD. Also, at least one of the positions (number of digits) of the X bits that is selectively inverted may be different for each scrambling circuit. InFIG.4, it is exemplarily illustrated that the scrambling circuits341to349may selectively invert three bits among the remaining bits A<3> to A<16> excluding lower three bits A<0> to A<2> of the address ADD in response to the lower three bits A<0> to A<2> of the address ADD.

Referring toFIG.4, it may be seen that INV(0) corresponds to A<3> of the address ADD inputted to the scrambling circuit341, and INV(1) corresponds to A<4> of the address ADD inputted to the scrambling circuit341, and INV(2) corresponds to A<5> of the address ADD inputted to the scrambling circuit341. This shows that the scrambling circuit341selectively inverts INV(0) corresponding to the A<3> bit of the address ADD according to a logic level of the A<0> bit of the address ADD, selectively inverts INV(1) corresponding to the A<4> bit of the address ADD according to a logic level of the A<1> bit of the address ADD, and selectively inverts INV(2) corresponding to the A<5> bit of the address ADD according to a logic level of the A<2> bit of the address ADD. That is, INV(0) corresponding to A<3> may be inverted when the logic level of A<0> is ‘1’, while INV(0) corresponding to A<3> may not be inverted when the logic level of A<0> is ‘0’. Likewise, INV(1) corresponding to A<4> may be or may not be inverted according to whether the logic level of A<1> is ‘1’ or ‘0’, and INV(2) corresponding to A<5> may be or may not be inverted according to whether the logic level of A<2> is ‘1’ or ‘0’.

Also, as shown inFIG.4, the scrambling circuit342may selectively invert INV(0) to INV(2) corresponding to A<4> to A<6> according to the logic levels of A<0> to A<2>; the scrambling circuit343may selectively invert INV(0) to INV(2) corresponding to A<5> to A<7> according to the logic levels of A<0> to A<2>; the scrambling circuit344may selectively invert INV(0) to INV(2) corresponding to A<6> to A<8> according to the logic levels of A<0> to A<2>; the scrambling circuit345may selectively invert INV(0) to INV(2) corresponding to A<7> to A<9> according to the logic levels of A<0> to A<2>; the scrambling circuit346may selectively INV(0) to INV(2) corresponding to invert A<8> to A<10> according to the logic levels of A<0> to A<2>; the scrambling circuit347may selectively invert INV(0) to INV(2) corresponding to A<9> to A<11> according to the logic levels of A<0> to A<2>; the scrambling circuit348may selectively invert INV(0) to INV(2) corresponding to A<10> to A<12> according to the logic levels of A<0> to A<2>; and the scrambling circuit349may selectively invert INV(0) to INV(2) corresponding to A<11> to A<13> according to the logic levels of A<0> to A<2>.

As shown inFIG.4, when the scrambling circuits341to349perform a scrambling operation, neighboring word lines, adjacent to a word line selected by a first address received from the memory controller310, may be selected at most in one memory among the memories321to329by a second address received from the memory controller310.

FIGS.5and6illustrate the scrambling circuits341to349scrambling the address ADD to generate scrambled addresses ADD_S0 to ADD_S8 in the scrambling method ofFIG.4.

Referring toFIG.5, it may be seen that since the lower 3 bits A<0> to A<2> of the address ADD are A<0>=0, A<1>=1, and A<2>=1, the bits corresponding to INV(1) and INV(2) inFIG.4are inverted and as a result, the scrambled addresses ADD_S0 to ADD_S8 are generated. For example, it may be seen that the scrambled address ADD_S3 is generated by inverting INV(1) and INV(2) corresponding to A<7> and A<8> of the address ADD.

Referring toFIG.6, it may be seen that since the lower 3 bits A<0> to A<2> of the address ADD are A<0>=1, A<1>=0, and A<2>=0, the bit corresponding to INV(0) inFIG.4is inverted and as a result, the scrambled addresses ADD_S0 to ADD_S8 are generated. For example, it may be seen that the scrambled address ADD_S6 is generated by inverting INV(0) corresponding to A<9> of the address ADD.

FIG.7is a schematic diagram illustrating the scrambling circuit341.FIG.7illustrates a structure of inverting or non-inverting a #thbit in the scrambling circuit341. The scrambling circuit341may include a plurality of the structures ofFIG.7.

Referring toFIG.7, a structure for inverting an A<#>thbit may include an inverter701and multiplexers703and705.

The inverter701may invert and output a #thbit of the address ADD (A<#> of ADD). When a logic level of a select signal SEL is ‘0’, the multiplexer703may output the #thbit of the address ADD (A<#> of ADD) as a #thbit of the scrambled address ADD_S0 (A<#> of ADD_S0). When the logic level of a select signal SEL is ‘1’, the multiplexer703may output the output of the inverter701as a #thbit of the scrambled address ADD_S0 (A<#> of ADD_S0). The multiplexer705may select one among A<0> of ADD, A<1> of ADD, A<2> of ADD, and a ground voltage VSS according to test mode signals TM<0> to TM<3> and output the selected one as the selection signal SEL.

The test mode signals TM<0> to TM<3> may be signals whose logic levels are determined according to how the signals are set, and the test mode signals TM<0> to TM<3> may be set in such a manner that one of the test mode signals TM<0> to TM<3> is activated. When the test mode signal TM<0> is activated, A<0> of ADD may serve as the selection signal SEL. Therefore, A<#> of ADD may be inverted/non-inverted according to the logic level of A<0> of ADD to become A<#> of ADD_S0. Likewise, when the test mode signal TM<2> is activated, A<2> of ADD may serve as the selection signal SEL. Therefore, A<#> of ADD may be inverted/non-inverted according to the logic level of A<2> of ADD to become A<#> of ADD_S0. When the test mode signal TM<3> is activated, the ground voltage VSS (VSS=0) may serve as the selection signal SEL. Therefore, A<#> of ADD may become A<#> of ADD_S0 as it is (non-inverted).

In other words, based on how to set the scrambling circuit, the scrambling circuit ofFIG.7may output an #thbit of the address ADD as it is, or may selectively invert and output the #thbit of the address ADD according to the logic level of A<0>, or may selectively invert and output the #thbit of the address ADD according to the logic level of A<1>, or may selectively invert and output the #thbit of the address ADD according to the logic level of A<2>.

The remaining scrambling circuits342to349may also include a plurality of structures shown inFIG.7.

FIG.8is a block diagram of a memory system800in accordance with various embodiments of the present invention. InFIG.8, only a portion directly related to an address in the memory system800is illustrated.

Referring toFIG.8, the memory system800may include a memory controller810and a memory module820.

The memory controller810may control the operations of the memory module820, such as an active operation, a read operation, and a write operation, according to a request of the host. The memory controller810may transfer an address ADD for selecting an area to be accessed in the memory module820to the memory module820.

The memory module820may include a plurality of scrambling circuits841to849and a plurality of memories821to829.

The scrambling circuits841to849may be formed and operate in the same way as the scrambling circuits341to349described with reference toFIGS.3to7. The scrambling circuits841to849may be slightly different from the scrambling circuits341to349in that the scrambling circuits841to849may be placed at the outside of the memories821to829, instead of the inside of the memories821to829. Also, the memories821to829may be formed and operate in the same way as the memories321to329, except that the memories821to829do not include the scrambling circuits841to849.

In short, the memory system800ofFIG.8may be formed and operate in the same way as the memory system300ofFIG.3, except that only the positions of the scrambling circuits841to849are changed.

According to the embodiments of the present invention, it is possible to reduce the influence of an error occurring due to row hammering in a memory system.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.