Patent ID: 12237388

DETAILED DESCRIPTION

Overview

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

For purposes of illustrating transistor arrangements with one or more stacked trench contacts and/or one or more gate straps, proposed herein, it might be useful to first understand phenomena that may come into play in such arrangements. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications. While some of the following descriptions may be provided for the example of transistors being implemented as FinFETs, embodiments of the present disclosure are equally applicable to transistor arrangements employing transistors of other architectures, such as nanoribbon or nanowire transistors, as well as to planar transistors.

As described above, recently, FETs with non-planar architectures, such as FinFETs and nanoribbon/nanowire transistors, have been extensively explored as alternatives to transistors with planar architectures.

In a FinFET, a semiconductor structure shaped as a fin extends away from a base (e.g., from a semiconductor substrate), and a gate stack may wrap around the upper portion of the fin (i.e., the portion farthest away from the base), potentially forming a gate on 3 sides of the fin. The portion of the fin around which the gate stack wraps around is referred to as a “channel” or a “channel portion” of a FinFET. A semiconductor material of the channel portion is commonly referred to as a “channel material” of the transistor. A source region and a drain region are provided in the fin on the opposite sides of the gate stack, forming, respectively, a source and a drain of a FinFET.

In a nanoribbon transistor, a gate stack may be provided around a portion of an elongated semiconductor structure called “nanoribbon”, forming a gate on all sides of the nanoribbon. The “channel” or the “channel portion” of a nanoribbon transistor is the portion of the nanoribbon around which the gate stack wraps around. A source region and a drain region are provided in the nanoribbon on each side of the gate stack, forming, respectively, a source and a drain of a nanoribbon transistor. In some settings, the term “nanoribbon” has been used to describe an elongated semiconductor structure that has a substantially rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe a similar structure but with a substantially circular transverse cross-section.

Taking FinFETs as an example, oftentimes, fabrication of an IC device having an array of FinFETs involves, first, providing a plurality of fins (typically parallel to one another), and then providing metal gate lines that cross over multiple fins (the metal gate lines often, but not always, being substantially perpendicular to the lengths, or longitudinal axes, of the fins, the metal gate lines provided in a plane substantially parallel to the plane of the support structure on which the fins are formed). A metal gate line crossing a first fin of the plurality of fins may form a gate of a transistor in the first fin, while the metal gate line crossing an adjacent second fin may form a gate of a transistor in the second fin. Since the metal gate line crosses over both the first and the second fins, the metal gate line is electrically continuous over the first and second fins, thereby providing an electrical coupling between the gate of the transistor in the first fin and the gate of the transistor in the second fin. In a later part of a fabrication process, it may be desirable to disrupt this continuity, e.g., if the design is such that it requires that the gate of the transistor in the first fin is decoupled from the gate of the transistor in the second fin. Also in a later part of a fabrication process, trench contacts are formed, where, as used herein, the term “trench contact” refers to a structure that is supposed to provide electrical connectivity to (i.e., is a contact) to source or drain (S/D) contacts of a transistor. In addition, gate contacts are formed, where the term “gate contact” refers to a structure that is supposed to provide electrical connectivity to (i.e., is a contact) to a gate (i.e., to a gate metal line) of a transistor.

For the past several decades, the scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant and such optimization is far from trivial.

One challenge that arises with the ever-decreasing dimensions of ICs is that the overlay between the electrically conductive structures of trench contacts and metal gates, as well as the overlay between the electrically conductive structures of trench contacts and adjacent gate contacts generally need to be controlled to high tolerances. To that end, the term “edge placement error margin” refers to a measure of how much misalignment between these electrically conductive structures may be tolerated. On one hand, etch selectivity between different materials may be used to ensure that proper contacts between different electrically conductive structures are made, where two materials may be described as “sufficiently etch-selective” if etchants used to etch one material do not substantially etch the other material, and vice versa. However, as the transistor dimensions become even smaller over time, etch selectivity may not be enough to allow adequate over-etch to ensure no open contacts or shorts at small dimensions. On the other hand, complex fabrication processes may be implemented where multiple mask and polish processes are used, and where an intricate series of fabrication steps involving multiple liners and helmets may allow addressing the edge placement error margin issues, but such fabrication processes may not always be sufficiently cost-efficient. Another challenge with the ever-decreasing dimensions of ICs is that gate resistance may be relatively large.

Described herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a S/D contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts.

In some optional implementations, the electrically conductive material of the first trench contact may also be deposited over the gate electrodes of transistors to advantageously reduce gate resistance. A structure of the electrically conductive material of the first trench contact provided over a gate electrode of a transistor is referred to herein as a “gate strap.” The electrically conductive material of such a gate strap would typically have a lower resistance than that of a gate electrode material of a transistor, thereby reducing the overall gate resistance to a resistance of two circuit components with different resistances connected in series. In other implementations, gate straps may be implemented without implementing the stacked trench contacts in the manner described herein (e.g., the gate straps as described herein may be combined with any conventional ways to provide trench contacts).

While descriptions provided herein refer to FinFETs, these descriptions are equally applicable to embodiments any other non-planar FETs besides FinFETs, e.g., to nanoribbon transistors, nanowire transistors, or transistors such as nanoribbon/nanowire transistors but having transverse cross-sections of any geometry (e.g., oval, or a polygon with rounded corners).

IC structures as described herein, in particular transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein, may be used for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Further, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,FIGS.4A-4B, such a collection may be referred to herein without the letters, e.g., as “FIG.4.”

In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Furthermore, although a certain number of a given element may be illustrated in some of the drawings (e.g., a certain number of stacked trench contacts, a certain number of gate contacts, a certain number of metal gate lines, etc.), this is simply for ease of illustration, and more, or less, than that number may be included in a transistor arrangement with one or more stacked trench contacts and/or one or more gate straps as described herein. Still further, various views shown in some of the drawings are intended to show relative arrangements of various elements therein. In other embodiments, various transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein, or portions thereof, may include other elements or components that are not illustrated (e.g., transistor portions, various components that may be in electrical contact with any of the metal lines, etc.). Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g., Physical Failure Analysis (PFA) would allow determination of presence of transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side” to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

For example, some descriptions may refer to a particular source or drain region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because under certain operating conditions, designations of source and drain are often interchangeable. Therefore, descriptions provided herein may use the term of a “S/D” region/contact to indicate that the region/contact can be either a source region/contact, or a drain region/contact.

In another example, if used, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die,” the term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an electrically conductive material” may include one or more electrically conductive materials.

In another example, if used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide.

In yet another example, a term “interconnect” may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the “interconnect” may refer to both trench contacts (also sometimes referred to as “lines”) and vias. In general, a term “trench contact” may be used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such trench contacts are typically arranged in several levels, or several layers, of metallization stacks. On the other hand, the term “via” may be used to describe an electrically conductive element that interconnects two or more trench contacts of different levels. To that end, a via may be provided substantially perpendicularly to the plane of an IC chip and may interconnect two trench contacts in adjacent levels or two trench contacts in not adjacent levels. A term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip.

Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.

Example FinFET

FIG.1is a perspective view of an example FinFET100, according to some embodiments of the disclosure. The FinFET100illustrates one example of transistors that may be implemented in various transistor arrangements described herein, e.g., in the transistor arrangements shown inFIG.3andFIGS.5-8. The FinFET100shown inFIG.1is intended to show relative arrangement(s) of some of the components therein. In various embodiments, the FinFET100, or portions thereof, may include other components that are not illustrated (e.g., any further materials, such as e.g. spacer materials, surrounding the gate stack of the FinFET100, electrical contacts to the S/D regions of the FinFET100, etc.).

As shown inFIG.1, the FinFET100may be provided over a base102, where the term “base” may refer to any suitable support structure on which a transistor may be built, e.g., a substrate, a die, a wafer, or a chip. As also shown inFIG.1, the FinFET100may include a fin104, extending away from the base102. A portion of the fin104that is closest to the base102may be enclosed by an insulator material106, commonly referred to as a “shallow trench isolation” (STI). The portion of the fin104enclosed on its' sides by the STI106is typically referred to as a “subfin portion” or simply a “subfin.” As further shown inFIG.1, a gate stack108that includes at least a layer of a gate electrode material112and, optionally, a layer of a gate dielectric110, may be provided over the top and sides of the remaining upper portion of the fin104(e.g., the portion above and not enclosed by the STI106), thus wrapping around the upper-most portion of the fin104. The portion of the fin104over which the gate stack108wraps around may be referred to as a “channel portion” of the fin104because this is where, during operation of the FinFET100, a conductive channel may form. The channel portion of the fin104is a part of an active region of the fin104. A first S/D region114-1and a second S/D region114-2(also commonly referred to as “diffusion regions”) are provided on the opposite sides of the gate stack108, forming source and drain terminals of the FinFET100.

In general, implementations of the present disclosure may be formed or carried out on a support structure such as a semiconductor substrate, composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein may be built falls within the spirit and scope of the present disclosure. In various embodiments, the base102may include any such substrate material that provides a suitable surface for forming the FinFET100.

As shown inFIG.1, the fin104may extend away from the base102and may be substantially perpendicular to the base102. The fin104may include one or more semiconductor materials, e.g. a stack of semiconductor materials, so that the upper-most portion of the fin (namely, the portion of the fin104enclosed by the gate stack108) may serve as the channel region of the FinFET100. Therefore, as used herein, the term “channel material” of a transistor may refer to such upper-most portion of the fin104, or, more generally, to any portion of one or more semiconductor materials in which a conductive channel between source and drain regions may be formed during operation of a transistor.

As shown inFIG.1, the STI material106may enclose the sides of the fin104. A portion of the fin104enclosed by the STI106forms a subfin. In various embodiments, the STI material106may be a low-k or high-k dielectric including, but not limited to, elements such as hafnium, silicon, oxygen, nitrogen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Further examples of dielectric materials that may be used in the STI material106may include, but are not limited to silicon nitride, silicon oxide, silicon dioxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

Above the subfin portion of the fin104, the gate stack108may wrap around the fin104as shown inFIG.1. In particular, the gate dielectric110may wrap around the upper-most portion of the fin104, and the gate electrode112may wrap around the gate dielectric110. The interface between the channel portion of the fin104and the subfin portion of the fin104is located proximate to where the gate electrode112ends.

The gate electrode112may include one or more gate electrode materials, where the choice of the gate electrode materials may depend on whether the FinFET100is a P-type metal-oxide-semiconductor (PMOS) transistor or an N-type metal-oxide-semiconductor (NMOS) transistor. For a PMOS transistor, gate electrode materials that may be used in different portions of the gate electrode112may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, gate electrode materials that may be used in different portions of the gate electrode112include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode112may include a stack of a plurality of gate electrode materials, where zero or more materials of the stack are workfunction (WF) materials and at least one material of the stack is a fill metal layer. Further materials/layers may be included next to the gate electrode112for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.

If used, the gate dielectric110may include a stack of one or more gate dielectric materials. In some embodiments, the gate dielectric110may include one or more high-k dielectric materials. In various embodiments, the high-k dielectric materials of the gate dielectric110may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric110may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric110during manufacture of the FinFET100to improve the quality of the gate dielectric110.

In some embodiments, the gate stack108may be surrounded by a dielectric spacer, not specifically shown inFIG.1but shown, e.g., inFIG.5Aas a gate spacer538. The dielectric spacer may be configured to provide separation between the gate stacks108of different FinFETs100which may be provided along a single fin (e.g., different FinFETs provided along the fin104, althoughFIG.1only illustrates one of such FinFETs), as well as between the gate stack108and the source/drain contacts disposed on each side of the gate stack108. Such a dielectric spacer may include one or more low-k dielectric materials. Examples of the low-k dielectric materials that may be used as the dielectric spacer include, but are not limited to, silicon dioxide, carbon-doped oxide, silicon nitride, fused silica glass (FSG), and organosilicates such as silsesquioxane, siloxane, and organosilicate glass. Other examples of low-k dielectric materials that may be used as the dielectric spacer include organic polymers such as polyimide, polynorbornenes, benzocyclobutene, perfluorocyclobutane, or polytetrafluoroethylene (PTFE). Still other examples of low-k dielectric materials that may be used as the dielectric spacer include silicon-based polymeric dielectrics such as hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ). Other examples of low-k materials that may be used in a dielectric spacer include various porous dielectric materials, such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly 1. When such a dielectric spacer is used, then the lower portions of the fin104, e.g., the subfin portion of the fin104, may be surrounded by the STI material106which may, e.g., include any of the high-k dielectric materials described herein.

In some embodiments, the fin104may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the fin104may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the fin104may include a combination of semiconductor materials where one semiconductor material is used for the channel portion and another material, sometimes referred to as a “blocking material,” is used for at least a portion of the subfin portion of the fin104. In some embodiments, the subfin and the channel portions of the fin104are each formed of monocrystalline semiconductors, such as e.g. Si or Ge. In a first embodiment, the subfin and the channel portion of the fin104are each formed of compound semiconductors with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). The subfin may be a binary, ternary, or quaternary III-V compound semiconductor that is an alloy of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

For some example N-type transistor embodiments (i.e., for the embodiments where the FinFET100is an NMOS), the channel portion of the fin104may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel portion of the fin104may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel portion of the fin104may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel portion of the fin104, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion of the fin104may be relatively low, for example below 1015dopant atoms per cubic centimeter (cm−3), and advantageously below 1013cm−3. The subfin portion of the fin104may be a III-V material having a band offset (e.g., conduction band offset for N-type devices) from the channel portion. Example materials include, but are not limited to, GaAs, GaSb, GaAsSb, GaP, InAlAs, GaAsSb, AlAs, AIP, AlSb, and AlGaAs. In some N-type transistor embodiments of the FinFET100where the channel portion of the fin104is InGaAs, the subfin may be GaAs, and at least a portion of the subfin may also be doped with impurities (e.g., P-type) to a greater impurity level than the channel portion. In an alternate heterojunction embodiment, the subfin and the channel portion of the fin104each include group IV semiconductors (e.g., Si, Ge, SiGe). The subfin of the fin104may be a first elemental semiconductor (e.g., Si or Ge) or a first SiGe alloy (e.g., having a wide bandgap).

For some example P-type transistor embodiments (i.e., for the embodiments where the FinFET100is a PMOS), the channel portion of the fin104may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel portion of the fin104may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel portion may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel portion of the fin104, for example to further set a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 1015cm−3, and advantageously below 1013cm−3. The subfin of the fin104may be a group IV material having a band offset (e.g., valance band offset for P-type devices) from the channel portion. Example materials include, but are not limited to, Si or Si-rich SiGe. In some P-type transistor embodiments, the subfin of the fin104is Si and at least a portion of the subfin may also be doped with impurities (e.g., N-type) to a higher impurity level than the channel portion.

Turning to the first S/D region114-1and the second S/D region114-2on respective different sides of the gate stack108, in some embodiments, the first S/D region114-1may be a source region and the second S/D region114-2may be a drain region. In other embodiments this designation of source and drain may be interchanged, i.e., the first S/D region114-1may be a drain region and the second S/D region114-2may be a source region. Although not specifically shown inFIG.1, the FinFET100may further include S/D electrodes (also commonly referred to as “S/D contacts”), formed of one or more electrically conductive materials, for providing electrical connectivity to the S/D regions114, respectively. In some embodiments, the S/D regions114of the FinFET100may be regions of doped semiconductors, e.g., regions of doped channel material of the fin104, so as to supply charge carriers for the transistor channel. In some embodiments, the S/D regions114may be highly doped, e.g. with dopant concentrations of about 1·1021cm−3, in order to advantageously form Ohmic contacts with the respective S/D electrodes, although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the S/D regions114of the FinFET100are the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in a region of the semiconductor channel material between the first S/D region114-1and the second S/D region114-2, and, therefore, may be referred to as “highly doped” (HD) regions.

In some embodiments, the S/D regions114may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the one or more semiconductor materials of the upper portion of the fin104to form the S/D regions114. An annealing process that activates the dopants and causes them to diffuse further into the fin104may follow the ion implantation process. In the latter process, the one or more semiconductor materials of the fin104may first be etched to form recesses at the locations for the future source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material (which may include a combination of different materials) that is used to fabricate the S/D regions114. In some implementations, the S/D regions114may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions114may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. Although not specifically shown in the perspective illustration ofFIG.1, in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain contacts (i.e., electrical contacts to each of the S/D regions114).

The FinFET100may have a gate length, GL, (i.e. a distance between the first S/D region114-1and the second S/D region114-2), a dimension measured along the fin104in the direction of the x-axis of the example reference coordinate system x-y-z shown inFIG.1, which may, in some embodiments, be between about 5 and 40 nanometers, including all values and ranges therein (e.g. between about 10 and 35 nanometers, or between about 15 and 25 nanometers). The fin104may have a thickness, a dimension measured in the direction of the y-axis of the reference coordinate system x-y-z shown inFIG.1, that may, in some embodiments, be between about 4 and 15 nanometers, including all values and ranges therein (e.g. between about 5 and 10 nanometers, or between about 7 and 12 nanometers). The fin104may have a height, a dimension measured in the direction of the z-axis of the reference coordinate system x-y-z shown inFIG.1, which may, in some embodiments, be between about 30 and 350 nanometers, including all values and ranges therein (e.g. between about 30 and 200 nanometers, between about 75 and 250 nanometers, or between about 150 and 300 nanometers).

Although the fin104illustrated inFIG.1is shown as having a rectangular cross-section in a z-y plane of the reference coordinate system shown inFIG.1, the fin104may instead have a cross-section that is rounded or sloped at the “top” of the fin104, and the gate stack108(including the different portions of the gate dielectric110) may conform to this rounded or sloped fin104. In use, the FinFET100may form conducting channels on three “sides” of the channel portion of the fin104, potentially improving performance relative to single-gate transistors (which may form conducting channels on one “side” of a channel material or substrate) and double-gate transistors (which may form conducting channels on two “sides” of a channel material or substrate).

WhileFIG.1illustrates a single FinFET100, in some embodiments, a plurality of FinFETs may be arranged next to one another (with some spacing in between) along the fin104.

Example IC Structures with Stacked Trench Contacts and Gate Straps

FIGS.2and3provide top-down views (i.e., the views of the x-y plane of the example reference coordinate system shown inFIG.1) of an example IC structure in which transistor arrangements with one or more stacked trench contacts and/or one or more gate straps according to various embodiments of the disclosure may be implemented. In particular,FIG.2illustrates an IC structure200without any stacked trench contacts, whileFIG.3illustrates an IC structure300with stacked trench contacts, according to some embodiments of the disclosure. The transistor arrangements shown inFIGS.2and3are intended to show relative arrangement(s) of some of the components therein and in various embodiments, the IC structures shown inFIGS.2and3, or portions thereof, may include other components that are not illustrated (e.g., any further materials, such as spacer materials, STI, S/D regions or electrical contacts thereto, etc.). Same holds for subsequent drawings of the present disclosure.

A legend provided within a dashed box at the bottom ofFIGS.2and3illustrates colors/patterns used to indicate some portions or materials of some of the elements shown inFIGS.2and3, so that these drawings are not cluttered by too many reference numerals (the same holds for subsequent drawings of the present disclosure that include a legend at the bottom of the drawings). For example,FIGS.2and3use different colors/patterns to identify a channel material204(e.g., the channel material of the fins104), a dielectric material206, and a gate electrode material212of metal gate lines. In addition,FIG.3further uses different colors/patterns to identify a first trench contact material (referred to in the following as “TCN1 material”302), a second trench contact material (referred to in the following as “TCN2 material”)304, a gate contact via material (referred to in the following as “VCG material”)306, a gate cap308, and a dielectric liner material310.

The IC structures shown inFIGS.2and3, and in some of the subsequent drawings, are examples of how a plurality of the FinFETs100may be arranged in an IC device. Therefore, the IC structures shown inFIGS.2-3and in some of the subsequent drawings illustrate some elements labeled with the same reference numerals as those used inFIG.1to indicate similar or analogous elements in these drawings, so that, in the interests of brevity, descriptions of a given element provided with reference to one drawing does not have to be repeated again for other drawings. For example,FIGS.2and3illustrate the fin104(in particular, a plurality of such fins), and example S/D regions114for one example FinFET of the IC structures ofFIGS.2and3. The same holds for subsequent drawings of the present disclosure—elements with reference numerals used in one drawing and shown again in another drawing refer to similar or analogous elements so that their descriptions do not have to be repeated for each drawing.

As shown inFIG.2, the IC structure200may include a channel material204shaped into a plurality of fins104, which, in some embodiments, may extend substantially parallel to one another. Different instances of the fins104are shown inFIG.2with a dash and a different reference numeral after the reference numeral for the fin,104(the same notation is used for other elements in other drawings). The IC structure200illustrates an example of8fins104, labeled as fins104-1through104-8, but, in other embodiments, any other number of two or more fins104may be implemented in the IC structure200.

Once the fins104are fabricated, metal gate lines212may be provided over the fins104, crossing multiple fins104. In some embodiments, the metal gate lines212may extend substantially perpendicular to the length of the fins104. For example, if the fins104extend in the direction of the x-axis of the example coordinate system used in the present drawings, as shown inFIG.2(i.e., if each of the fins104may have a long axis substantially parallel to the support structure over which they are provided (e.g., the base102) and different fins104may extend substantially parallel to one another), then the metal gate lines212may extend in the direction of the y-axis, as is shown inFIG.2. In some embodiments, the metal gate lines212may be shaped as ridges, substantially perpendicular to the length of the fins104and enclosing different portions of the fins104. At least portions of the metal gate lines212provided over the fins104, i.e., where gates of FinFETs may be formed, as described with reference toFIG.1, may include the gate electrode material112, thus forming gate stacks108, described above. In some embodiments, all of the metal gate lines212(i.e., also between the fins104) are formed of one or more of the gate electrode material112. In some embodiments, the gate electrode material112used in one portion of a given metal gate line212may have a material composition that is different from the material composition of the gate electrode material112used in another portion of that particular metal gate line212. For example, the material composition of a portion of a given metal gate line212crossing the fins104in which NMOS transistors are to be formed may be different from the material composition of a portion of that metal gate line212crossing the fins104in which PMOS transistors are to be formed. For example, the fins104-1and104-2may be fins in which NMOS transistors can be formed, while the fins104-3and104-4may be fins in which PMOS transistors can be formed.

A dashed contour shown inFIG.2illustrates an example of a FinFET202formed in one of the fins104, namely, in the fin104-5. The FinFET202may be an example of the FinFET100, described above.FIG.2illustrates the S/D regions114-1and114-2for the FinFET202, and a portion of the metal gate line212crossing the fin104-5forms the gate stack108of the FinFET202. A plurality of other such FinFETs are also shown inFIG.2, although they are not specifically labeled with reference numerals in order to not clutter the drawings.

In some embodiments, a plurality of FinFETs202may be arranged to form a cell unit (or, simply, a “cell”) with a particular logic function/functionality, and such cells may then be provided multiple times in an array form. Of course, in other embodiments of the IC structure200, the FinFETs202may be arranged in ways that do not include repeating cell units.

FIG.2further illustrates that portions of the IC structure200surrounding the upper portions of the fins104may be enclosed by a dielectric material206, which may include one or more of the dielectric spacer materials, described above. Although the top-down view ofFIG.2illustrates the tops of the fins104in the portions where the metal gate lines212are not crossing the fins, in some embodiments, the dielectric material206may cover the tops of the fins104in those portions (in which case the fins104would not be visible in the top-down view of the IC structure200).

FIG.3is a top-down view of an IC structure300that is similar to the IC structure200ofFIG.2, further illustrating an example transistor arrangement with stacked trench contacts, according to some embodiments of the disclosure. A transistor arrangement320, shown inFIG.3to be included within a dashed box, is a portion of the IC structure300in which one or more stacked trench contacts and/or one or more gate straps may be implemented, according to some embodiments of the disclosure. In particular, the top-down view of the transistor arrangement320as shown inFIG.3illustrates the TCN1 material302, the TCN2 material304, the VCG material306, the dielectric liner material310, and the TCN2 material304in an opening537to form a GCN contact, which will be described in greater detail below with reference to the manufacturing method and resulting devices. A gate cap provided over portions of the metal lines as described below is not specifically shown inFIG.3. One example of the FinFET202similar to that shown inFIG.2is labeled in the transistor arrangement320, although the transistor arrangement320includes several FinFETs such as the FinFET202. Although not specifically shown inFIG.3outside of the dashed box illustrating the transistor arrangement320in order to not clutter the drawing, the transistor arrangement320as described herein may also be included in other portions of the IC structure300.

Example Fabrication Method

FIGS.4A-4Bprovide a flow diagram of an example method400of manufacturing an IC structure with a transistor arrangement with one or more stacked trench contacts and/or one or more gate straps, according to one embodiment of the disclosure. For example, the method400may be used to manufacture an IC structure such as the IC structure300, with a transistor arrangement such as the transistor arrangement320, described herein.

Although the operations of the method400are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein will be included.

In addition, the example manufacturing method400may include other operations not specifically shown inFIG.4, such as various cleaning or planarization operations as known in the art. For example, in some embodiments, a support structure, as well as layers of various other materials subsequently deposited thereon, may be cleaned prior to, after, or during any of the processes of the method400described herein, e.g., to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g., a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the arrangements/devices described herein may be planarized prior to, after, or during any of the processes of the method400described herein, e.g., to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface.

Various operations of the method400may be illustrated with reference to the example embodiments shown inFIGS.5-8, illustrating cross-sectional side views for various stages in the manufacture of an example IC structure with a transistor arrangement with one or more stacked trench contacts and/or one or more gate straps, in accordance with various embodiments, but the method400may be used to manufacture any other suitable IC structures having one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps according to any embodiments of the present disclosure. In particular,FIGS.5-8illustrate cross-sectional side views of various embodiments of the transistor arrangement320ofFIG.3, with the cross-sections of the transistor arrangement320taken along the length of the fin104-5(i.e., cross-sections along the x-z planes that contain the fin104-5). Similar toFIGS.2-3, a number of elements referred to in the description ofFIGS.5-8with reference numerals are illustrated in these figures with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of each drawing page containingFIGS.5-8.

The method400may begin with a process402that includes performing gate and TCN1 patterning.

The process402is shown inFIG.4A, and an example result of this process is illustrated with an IC structure502, shown inFIG.5A. The process402may include, first, providing one or more (typically, a plurality) of fins over a support structure, then providing one or more (typically, a plurality) of metal gate lines as ridges crossing and wrapping around upper portions of the fins, and then performing TCN1 patterning in regions between the adjacent metal gate lines. The IC structure502illustrates a support structure532and a channel material534of one of the fins104(e.g., of the fin104-5, shown inFIG.3), extending away from the support structure532. The IC structure502further illustrates three gates536(labeled as gates536-1,536-2, and536-3) enclosing the upper portion of the channel material534, the three gates corresponding to the three metal gate lines212crossing the fin104-5in the transistor arrangement320ofFIG.3, with a gate spacer538provided on the sidewalls of the adjacent gates536, as is known in the art. The IC structure502also illustrates S/D contacts542, provided in the fin104between the adjacent gates536. The support structure532may be implemented as the base102, described above. The channel material534may be implemented as described above with reference to the channel portion of the fin104. Each of the gates536may include any of the gate electrode materials as described above with reference to the gate electrode112, and, optionally, also a gate dielectric material as described above with reference to the gate dielectric110. The gate spacer538may be implemented as described above with reference to the gate spacer surrounding the gate stack108. The S/D contacts542may be implemented as described above with reference to the S/D regions114. Methods for providing the fins104, the gates536with the gate spacers538, and the S/D contacts542are known in the art and, therefore, are not described here in detail.

What is different in the IC structure from conventional implementations of fins with gates is that the gates536are not only enclosed by the gate spacer538on their sidewalls, but also with a gate cap540, provided over the sidewalls and over the tops of the gates536. The S/D contacts542may then be provided between the instances of the gate cap540associated with adjacent gates536. A TCN1 material544may then be provided above the S/D contacts542(e.g., to be in contact with the S/D contacts542), in between the instances of the gate cap540associated with adjacent gates536. A dielectric material (e.g., an interlayer dielectric (ILD))546may be provided over other portions of the IC structure, e.g., as shown on the left side ofFIG.5A. The gate cap540may include any of the materials described above with reference to the gate spacer surrounding the gate stack108, although the exact material composition of the gate spacer538and the gate cap540may be different in some embodiments. The gate cap540may be provided to reduce or eliminate the probability of the TCN2 material, provided in a later process of the method400, shorting (i.e., making an electrical connection or a short circuit) to the gate electrode material of the gates536, e.g., if the gate spacer538is too thin or becomes worn out with time (because dielectric materials may break down over time, causing reliability issues). The ILD material546may be implemented as the dielectric material206shown inFIG.3. An etch-stop material535may be provided, e.g., as a thin layer, between a portion of the channel material534of the fin and the ILD material546. In some embodiments, the etch-stop material535may include the gate cap540. In other embodiments, the etch-stop material535may include materials such as silicon nitride, or silicon carbon nitride. The TCN1 material544may be implemented as the TCN1 material304shown inFIG.3, and may include any suitable electrically conductive material, such as one or more metals or metal alloys with metals such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, molybdenum, and aluminum. In some embodiments, the TCN1 material544may include one or more electrically conductive alloys, oxides (e.g., conductive metal oxides), carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), or nitrides (e.g. hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, and aluminum nitride) of one or more metals.

Performing gate and TCN1 patterning in the process402may include using any suitable patterning techniques to define the locations and the dimensions of the gates536and the TCN2 material544, such as, but not limited to, photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with the use of one or more masks. Various dielectric materials as described herein, e.g., the gate cap540, may be deposited using any suitable deposition technique such as spin-coating, dip-coating, physical vapor deposition (PVD) (e.g., evaporative deposition, magnetron sputtering, or e-beam deposition), or chemical vapor deposition (CVD). Various conductive materials as described herein, e.g., the TCN1 material544, may be deposited using any suitable deposition technique such as PVD, CVD, or atomic layer deposition (ALD). The process402may also include using any suitable polishing techniques such as CMP to ensure that the upper surface of the TCN1 material544is flush with the upper surface of the gate cap540. The etch-stop material535may be deposited using any suitable deposition technique such as ALD, CVD, etc.

The method400may then proceed with a process404that includes recessing the TCN1 material544provided above the S/D contacts542in the process402so that the upper surface of the TCN1 material544is below the upper surfaces of the gate electrode material of the gates536. The process404is shown inFIG.4A, and an example result of this process is illustrated with an IC structure504, shown inFIG.5B, where recesses533are illustrated. In particular, a recess533-1may be between the gates536-1and536-2, and a recess533-2may be between the gates536-2and536-3. In some embodiments, the recesses533may have a depth535of at least about 5 nanometers, including all values and ranges therein, e.g., at least about 10 nanometers, e.g., between about 5 and 20 nanometers. The recesses533may be provided to reduce or eliminate the probability of the VCG material, provided in a later process of the method400, shorting to the TCN1 material544, e.g., if a liner material that will also be provided in a later process of the method400to separate the VCG material and the TCN1 material544is too thin or becomes worn out with time. In some embodiments, the recesses533may be formed in the process404using any suitable etch-selective process that etches the electrically conductive material of the TCN1 material544without substantially etching the dielectric materials of the gate cap540and the dielectric546since conductive materials and dielectric materials are sufficiently etch-selective (where two materials may be described as “sufficiently etch-selective” if etchants used to etch one material do not substantially etch the other material, and vice versa).

The method400may further include a process406, in which an etch-stop layer and an ILD material are provided over the IC structure formed in the process404. The process406is shown inFIG.4A, and an example result of this process is illustrated with an IC structure506, shown inFIG.5C, where a new layer of the etch-stop material535(labeled as “535-2”) is illustrated to be provided over all upper surfaces of the IC structure504ofFIG.5Band then the ILD material546is provided over the etch-stop material535-2.

In case the design of the transistor arrangement320is such that a gate of one transistor is coupled to a S/D contact of another (i.e., for the optional embodiments of gate-to-S/D coupling for one of the transistors of the transistor arrangement320), the method400may also include a process408, in which an opening is patterned for a gate contact (GCN) for such a gate-to-S/D coupling. The process408is shown inFIG.4A, and an example result of this process is illustrated with an IC structure508ofFIG.5D, showing an opening537formed to in the ILD material546to expose a portion of the gate536-3. In some embodiments, the process408may include performing an anisotropic etch, possibly using a sequence of different etchants, to selectively etch through the ILD material546above the etch-stop material535-2, then through the etch-stop material535-2, and, finally, through the gate cap540to expose at least a portion of the upper surface of the gate electrode material of the gate536-3(e.g., the etch of the process408may be etch-selective with respect to the gate electrode material of the gate536-3). Ideally, it may be desirable to provide the opening537directly over and aligned with the gate electrode material of the gate536-3, e.g., using a suitable mask. However, such alignment may be difficult to achieve in practice. Therefore,FIG.5Dillustrates a result of performing the process408if the opening537is somewhat misaligned with the gate electrode material of the gate536-3. In particular, the opening537is shifted to the left with respect to the center of the gate electrode material of the gate536-3, resulting in the opening537extending down on the side of the gate electrode material of the gate536-3(due to the anisotropic etch process that is etch-selective with respect to the gate electrode material of the gate536-3). Also the width of the opening537(a dimension measured along the x-axis of the example coordinate system shown inFIG.5) may, but does not have to be, the same as the width of the gate electrode material of the gate536-3.

In some embodiments, the anisotropic etch of any of the processes of the method400may include an etch that uses etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (CI) based chemistries. In some embodiments, during the anisotropic etch of any of the processes of the method400, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface. In some embodiments, the anisotropic etch of any of the processes of the method400may include a dry etch, such as radio frequency (RF) reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE. Although not specifically shown in the present drawings, in various embodiments, any suitable patterning techniques may be before performing the anisotropic etch of any of the processes of the method400to define the locations and the dimensions of the openings to be etched.

The method400may further include a process410, in which one or more openings are patterned for a second trench contact (TCN2) and filled with a TCN2 material. The process410is shown inFIG.4A, and an example result of this process is illustrated with an IC structure510ofFIG.5E, showing openings539-1and539-2, filled with a TCN2 material548. The opening539-1is, ideally, provided directly over and aligned with the S/D contact542between the gates536-1and536-2, while the opening539-2is, ideally, provided directly over and aligned with the S/D contact542between the gates536-2and536-3(the individual ones of the gates536not specifically labeled inFIG.5Ein order to not clutter the drawing). However, such alignment may be difficult to achieve in practice and, therefore,FIG.5Eillustrates a result of performing the process410if the openings539were somewhat misaligned with respect to said S/D contacts542(in particular, similar to the opening537, both of the openings539are shifted to the left, although the misalignment of the openings537and/or539may be different in other embodiments of the method400). As shown inFIG.5E, each of the openings539may expose at least a portion of the TCN1 material544provided over said S/D contacts542and, in general, the width of the openings539(a dimension measured along the x-axis of the example coordinate system shown inFIG.5) may, but does not have to be, the same as the width of the S/D contacts542. For the embodiments where the opening537was formed in the process408, the opening539-2may overlap with the opening537, thus forming one combined opening. In some embodiments, the process410may include performing an anisotropic etch, possibly using a sequence of different etchants, to selectively etch through the ILD material546above the etch-stop material535-2, then through the etch-stop material535-2, and, finally, through the ILD material546between the gates536, to expose at least a portion of the TCN1 material544. In some embodiments, the anisotropic etch of the process410may be etch-selective with respect to the gate cap540so that, if the openings539are misaligned (e.g., as shown inFIG.5E) so that a portion of the gate cap540is exposed when the etch-stop material535-2is removed at the top of the gate cap540, then the exposed gate cap540is not substantially etched. In some embodiments, the etch-stop material535-2may be a thin highly selective metal oxide material which may be physically sputtered away during the etch of the process410, so only its thickness is removed with little penetration into the gate cap540, as is shown inFIG.5E. As shown inFIG.5E, some of the etch-stop material535-2may remain on the sidewalls of the gate cap540within the openings539, being one of the features in the final product, indicative of the use of the method400.

FIG.5Efurther illustrates the TCN2 material548, which may include any of the electrically conductive materials described above, and which may, but does not have to, have the same material composition as the TCN1 material544, provided in the openings539formed in the process410and also in the opening537if the process408was performed. By virtue of the opening537being combined with the opening539-2and, together, filled with the TCN2 material548, an electrical connection is made between the gate electrode material of the gate536-3and the S/D contact542between the gates536-2and536-3, thus realizing the gate-to-S/D coupling in the transistor arrangement320. A portion of the TCN2 material548in the opening539-2(i.e., over the S/D contact542between the gates536-2and536-3) forms a trench contact TCN2 to said S/D contact542, while a portion of the TCN2 material548provided in the opening537(i.e., over the gate electrode material of the gate536-3) forms a gate contact GCN for the gate536-3, where the gate contact GCN is coupled to the trench contact TCN2. A portion of the TCN2 material548in the opening539-1forms a trench contact TCN2 to the S/D contact542between the gates536-1and536-2. The gate cap540may help reduce or eliminate the probability of the portion of the TCN2 material548in the opening539-1shorting to the gate electrode material of the gate536-1(i.e., the gate cap540is between, and, therefore, electrically isolates, the TCN2 material548in the opening539-1and the gate electrode material of the gate536-1, which is characteristic of the use of the method400). Trench contacts TCN1 and TCN2 are labeled inFIG.5E. Thus,FIG.5Eillustrates two instances of stacked trench contacts: one is a stack of trench contacts TCN1 and TCN2 to electrically couple to the S/D contact542between the gates536-1and536-2and another stack of trench contacts TCN1 and TCN2 is to electrically couple to the S/D contact542between the gates536-2and536-3.FIG.5Ealso illustrates that the gate contact GCN (also labeled inFIG.5E) may be provided of the same material as the TCN2 to electrically couple to the S/D contact542between the gates536-2and536-3, which is a feature that is characteristic of the use of the method400.

The method400may further include a process412, in which another etch-stop layer and another layer of an ILD material are provided over the IC structure formed in the process410. The process412is shown inFIG.4A, and an example result of this process is illustrated with an IC structure512, shown inFIG.5F, where a new layer of the etch-stop material535(labeled as “535-3”) is illustrated to be provided over all upper surfaces of the IC structure510ofFIG.5Eand then the ILD material546is provided over the etch-stop material535-3.

The method400may then proceed with an optional process414that includes patterning a top opening for a future gate via over the gate536-2and lining the top opening with a first liner material. The process414is shown inFIG.4A, and an example result of this process is illustrated with an IC structure514, shown inFIG.5G, where an opening541is illustrated, which opening is referred to as a “top opening” because it is provided in the ILD material546above the etch-stop material535-3, breaking through the etch-stop material535-3, and only partially extending into the ILD material546above the etch-stop material535-2. The sidewalls of the opening541are lined with a first liner material550, which may include any of the dielectric spacer materials described above. The first liner material550may be used to reduce or eliminate the probability of the VCG material, provided in a later process of the method400, shorting to the TCN2 material548, e.g., if a second liner material that will be provided in a later process of the method400to separate the VCG material and the TCN2 material548is too thin or becomes worn out with time. In some embodiments, the top opening541may be formed in the process414using a suitable anisotropic etch process (e.g., etch-selective with respect to the TCN2 material548). In some embodiments, the sidewalls of the opening541may be lined with the first liner material550using any suitable conformal deposition process, such as ALD. However, in other embodiments, any other suitable deposition techniques may be used to line the sidewalls of the opening541with the first liner material550, such as spin-coating, dip-coating, PVD, or CVD. In some embodiments, the process414may include depositing the first liner material550on sidewalls and bottom of the opening541(as well as on the upper surfaces of the IC structure514), followed by an anisotropic etch to remove the first liner material550from the bottom of the opening541and to remove excess of the first liner material550from the upper surfaces of the IC structure514(similar to the process described below for the second liner material552).

The method400may then proceed with a process416that includes patterning a full opening for a future gate via over the gate536-2. The process416is shown inFIG.4B, and an example result of this process is illustrated with an IC structure516, shown inFIG.5H, where an opening543is illustrated, which opening is referred to as a “full opening” because it is provided in the ILD material546above the etch-stop material535-3, breaking through the etch-stop material535-3, extending through all of the ILD material546above the etch-stop material535-2, breaking through the etch-stop material535-2, and removing whatever the dielectric materials are exposed after the etch-stop material535-2has been removed. In some embodiments, the process416may include performing an anisotropic etch, possibly using a sequence of different etchants, to selectively etch through these materials to expose at least a portion of the upper surface of the gate electrode material of the gate536-2(e.g., the etch of the process416may be etch-selective with respect to the gate electrode material of the gate536-2). Ideally, it may be desirable to provide the opening543directly over and aligned with the gate electrode material of the gate536-2, e.g., using a suitable mask. However, such alignment may be difficult to achieve in practice. Therefore,FIG.5Hillustrates a result of performing the process416if the opening543is somewhat misaligned with the gate electrode material of the gate536-2. In particular, the opening543is shifted to the left with respect to the center of the gate electrode material of the gate536-2, resulting in the opening543extending down on the side of the gate electrode material of the gate536-2(due to the anisotropic etch process that is etch-selective with respect to the gate electrode material of the gate536-2). Also the width of the opening543(a dimension measured along the x-axis of the example coordinate system shown inFIG.5) may, but does not have to be, the same as the width of the gate electrode material of the gate536-2. If the process414was performed, then the process416may include performing an anisotropic etch that is etch-selective with respect to the gate electrode material of the gate536-2through the opening541formed in the process414. In some embodiments, such an etch process may be etch-selective with respect to the first liner material550provided in the opening541formed in the process414.

The method400may then proceed with a process418that includes lining the opening formed in the process416with a second liner material. The process418is shown inFIG.4B, and an example result of this process is illustrated with an IC structure518, shown inFIG.5I, where sidewalls and bottom of the opening543are lined with a second liner material552, thus forming a lined VCG opening545(which is an opening smaller than the opening543). The second liner material552may include any of the dielectric spacer materials described above and may have material composition similar to, or different from, the material composition of the first liner material550. When the opening543formed in the process416is misaligned as was described above, deposition of the second liner material552may result in formation of a seam547near the bottom of the lined VCG opening545. The seam547may be seen as an interface where materials being deposited on both two sides of a trench or cavity structure, when the material thickness is greater than about half of the trench or cavity width. The seam547may not be there is the misalignment of the opening543is not large enough. In some embodiments, the second liner material552may be deposited in the process418using a conformal deposition technique such as ALD. However, in other embodiments, any other suitable deposition techniques may be used to line the sidewalls and bottom of the opening543with the second liner material552, such as spin-coating, dip-coating, PVD, or CVD.

The method400may then proceed with a process420that includes removing the second liner material that was deposited at the bottom of the opening formed in the process416. The process420is shown inFIG.4B, and an example result of this process is illustrated with an IC structure520, shown inFIG.5J, illustrating that the second liner material552is removed from the bottom of the lined VCG opening545. In some embodiments, the process420may include removing the second liner material552from all horizontal surfaces of the IC structure518, i.e., also from the upper surfaces of the IC structure518. In some embodiments, the process420may include an anisotropic etch process that may be etch-selective with respect to the gate electrode material of the gate536-2. As shown inFIG.5J, the process420opens the bottom of the lined VCG opening545, thus exposing the gate electrode material of the gate536-2so that a gate via contact may be made thereto in a process422.

Finally, the method400may include a process422, which includes filling the lined VCG opening545that resulted from the process420with an electrically conductive material for the VCG of the transistor arrangement320and, optionally, performing any suitable polishing process to remove excess of the VCG material. The process420is shown inFIG.4B, and an example result of this process is illustrated with an IC structure522, shown inFIG.5K, illustrating that the opening545has been filled with the VCG material554, which may include any of the electrically conductive materials described with reference to the TCN1 material544. In various embodiments, material composition of the VCG material554may be the same or different from that of the TCN1 material544and/or that of the TCN2 material548. The VCG material554in the opening545forms a gate contact via VCG, by being in contact with the gate electrode material of the gate536-2. The gate contact via VCG (formed by the VCG material554in the opening545), the gate contact GCN (formed by the TCN2 material548in the opening537, as described above), and stacked trench contacts TCN2 and TCN1 (formed by the, respectively, TCN2 material548and the TCN1 material544, as described above) are labeled inFIG.5K, as well as the gates536-1,536-2, and536-2.

As described above, the process414of the method400is optional. Example stages in the manufacture of a transistor arrangement using the method400without performing the process414are shown with the cross-sectional side views ofFIGS.6A-6D, according to other embodiments of the present disclosure.

An IC structure616, shown inFIG.6A, is an example result of the process416performed on the IC structure512that resulted from the process412(i.e., the process414was not performed). In the IC structure616, the opening643is similar to the opening543except that the opening643is formed without the first liner material550guiding the etch. As a consequence of not having the first liner material550covering the upper right corner of the TCN2 material548, that corner may be clipped in the etch of the process416, as is illustrated inFIG.6Awith a slanted profile of the TCN material548to which the opening643is aligned to (i.e., the substantially square corner of the IC structure512may be clipped in the process416to result in a slanted profile as shown inFIG.6A).

An IC structure618, shown inFIG.6B, is an example result of the process418performed on the IC structure616, described above. The IC structure618illustrates an opening645, similar to the opening545, that is a result of lining the opening formed in the process416with the second liner material552. Except for the differences described with respect to the IC structure616, descriptions of the IC structure518are applicable to the IC structure618and, therefore, in the interests of brevity, are not repeated.

An IC structure620, shown inFIG.6C, is an example result of the process420performed on the IC structure618, described above. Except for the differences described with respect to the IC structure616, descriptions of the IC structure520are applicable to the IC structure620and, therefore, in the interests of brevity, are not repeated.

An IC structure622, shown inFIG.6D, is an example result of the process422performed on the IC structure620, described above. Except for the differences described with respect to the IC structure616, descriptions of the IC structure522are applicable to the IC structure622and, therefore, in the interests of brevity, are not repeated.

Manufacturing transistor arrangements as was described with reference to the method400may leave several characteristic features in the final IC structure. Some of these characteristic features were described above. Other characteristic features will now be described with reference to the IC structure522, shown inFIG.5K, although these features are also applicable to the IC structure622, shown inFIG.6D, as well as to the IC structures with gate straps as shown inFIGS.7and8and described below.

One characteristic feature is that the gate contact via VCG is provided in an opening lined with at least one dielectric material, namely, the second liner material552. Another characteristic feature is that such dielectric material (i.e., the second liner material552) is between and, therefore, electrically isolates, the VCG material554and the TCN2 material548. Furthermore, such dielectric material (i.e., the second liner material552) at the bottom of the via opening for the gate contact via VCG is between, and, therefore, electrically isolates, the VCG material554and the TCN1 material544provided over the S/D contact542between the gates536-1and536-2.

Another characteristic feature is that the via opening for the gate contact via VCG is self-aligned to the TCN2 material548provided over the S/D contact542between the gates536-1and536-2. This self-alignment is a result of the opening for the gate contact via VCG being formed after the deposition of, and using an etch process that is selective to, the TCN2 material548provided over the S/D contact542between the gates536-1and536-2(e.g., as described herein with reference to the formation of the opening543in the process416of the method400).

There are other features related to the alignment of the via opening for the gate contact via VCG that are characteristic of the use of the method400. For example, one such feature is that the lowest portion at the bottom of the via opening for the gate contact via VCG may be aligned with the top of the TCN1 material544provided over the S/D contact542between the gates536-1and536-2(i.e., aligned with the recess of the TCN1). Another such feature is that, besides being on top of, e.g., in contact with, the gate electrode material of the gate536-2, the VCG material554may also wrap around, e.g., be in contact with, the side of said gate electrode material that is closest to the TCN2 material548provided over the S/D contact542between the gates536-1and536-2.

The presence of the gate cap540, as described above, is also characteristic of the use of the method400. For example, the presence of a portion of the gate cap540between, and, therefore, electrically isolating, the TCN2 material548in the opening539-1and the gate electrode material of the gate536-1may be characteristic of the method400. In another example, the presence of a portion of the gate cap540between the gate electrode material of the gate536-1and the TCN1 material544over the S/D contact542between the gates536-1and536-2may be characteristic of the method400.

The presence of the etch-stop material535in certain portions of the IC structures, as described above, may also be characteristic of the use of the method400. For example, the etch-stop material535-2may be present over a top of a portion of the gate cap540that is not between the TCN2 material548in the opening539-1and the gate electrode material of the gate536-1.

Still other characteristic features include the presence of the seam547in the dielectric material552and having the TCN1 material544provided above the S/D contacts542being recessed with respect to the upper surfaces of the gate electrode material of the gates536, if the misalignment is sufficiently large, as described above. The seam547may not be present is the misalignment of the opening543is not large enough (e.g., if the TCN2 misalignment to TCN1 or VCG misalignment to gate is not large enough).

The method400as described above may provide improvements in terms of increasing the edge placement error margin when forming trench and gate contacts of transistor arrangements. In further embodiments, some processes the method400may be extended to also reduce the gate resistance of the gates536. In such embodiments, the TCN1 material544may be deposited over the gate electrodes of transistors to advantageously reduce gate resistance. An example of that is shown with a cross-sectional side view of an IC structure702, illustrated inFIG.7A. The IC structure702is similar to the IC structure502, described above, and provides another example result of the process402. The difference is that the IC structure702further includes portions703of the TCN1 material544provided over the upper surface, e.g., in contact with, the gate electrode material of the gates536, where the portions703are gate straps that aim to reduce the gate resistance of the gates536. The gate straps703provided over different ones of the gates536-1,536-2, and536-3are labeled inFIG.7Aas, respectively, gate straps703-1,703-2, and703-3. The TCN1 material544of the gate straps703would typically have a lower resistance than that of the gate electrode materials of the gates536, thereby advantageously reducing the equivalent gate resistance for the transistors of the transistor arrangement of the IC structure702.

The method400may then proceed with processes404-422as described above but performed starting with the IC structure702instead of the IC structure502. An IC structure722, shown inFIG.7B, is an example result of the process422, described above, but starting from the result of the process402being the IC structure702. Except for the differences described with respect to the IC structure702(namely, the presence of the gate straps703), descriptions of the IC structure522are applicable to the IC structure722and, therefore, in the interests of brevity, are not repeated. Another alternative implementation is shown inFIG.8, illustrating an IC structure822, which is an example result of the process422, described above, but starting from the result of the process402being the IC structure702and proceeding with the method400that does not include the optional process414(i.e., the IC structure822is a combination of the embodiments described with reference toFIG.7where the gate straps703are implemented and the embodiments described with reference toFIG.6where the process414was omitted). Except for the differences described with respect to the IC structure702, descriptions of the IC structure622are applicable to the IC structure822and, therefore, in the interests of brevity, are not repeated.

The IC structures722and822illustrate that, some of the gate straps703may be in contact with other electrically conductive materials. For example, the TCN1 material544of the gate strap703-2may be in contact with the VCG material545, while the TCN1 material544of the gate strap703-3may be in contact with the TCN2 material548of the GCN. On the other hand, the TCN1 material544of the gate strap703-1may be electrically isolated from the TCN2 material548by virtue of the etch-stop material535-2.

WhileFIGS.7and8illustrate the gate straps703implemented in transistor arrangements fabricated using the method400, in other embodiments, gate and trench contacts may be provided for the IC structure702using any other method. In other words, in other embodiments, transistor arrangements with the gate straps703may be implemented without implementing the stacked trench contacts in the manner described herein (e.g., the gate straps703may be combined with any conventional ways to provide trench contacts).

Variations and Implementations

The IC structures illustrated in and described with reference toFIGS.1-8do not represent an exhaustive set of assemblies in which one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein may be integrated, but merely provide examples of such arrangements. For example, while descriptions and drawings provided herein refer to FinFETs, these descriptions and drawings are equally applicable to embodiments any other non-planar FETs besides FinFETs that are formed on the basis of an elongated structure of a suitable channel material, e.g., to nanoribbon transistors, nanowire transistors, or transistors such as nanoribbon/nanowire transistors but having transverse cross-sections of any geometry (e.g., oval, or a polygon with rounded corners). In another example, although particular arrangements of materials are discussed with reference toFIGS.1-8, intermediate materials may be included in various portions of these drawings. Additionally, whileFIGS.1-8may illustrate various elements, e.g., various openings shown inFIG.5, the gate electrode material of the gates536, etc., as having perfectly straight sidewall profiles, i.e., profiles where the sidewalls extend perpendicularly to the support structure532, these idealistic profiles may not always be achievable in real-world manufacturing processes. Namely, while designed to have straight sidewall profiles, real-world openings which may be formed as a part of fabricating various elements of the transistor arrangements illustrated inFIGS.1-8may end up having either so-called “non-re-entrant” profiles, where the width at the top of the opening is larger than the width at the bottom of the opening, or “re-entrant” profiles, where the width at the top of the opening is smaller than the width at the bottom of the opening. Oftentimes, as a result of a real-world opening not having perfectly straight sidewalls, imperfections may form within the materials filling the opening. For example, typical for re-entrant profiles, a void may be formed in the center of the opening, where the growth of a given material filling the opening pinches off at the top of the opening. Therefore, descriptions of various embodiments of transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as provided herein are equally applicable to embodiments where various elements of IC structures including such transistor arrangements look different from those shown in the drawings due to manufacturing processes used to form them.

Example Electronic Devices

The IC structures with transistor arrangements with one or more stacked trench contacts and/or one or more gate straps, disclosed herein, may be included in any suitable electronic device. For example, in various embodiments, the transistor arrangement320may be a part of at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.FIGS.9-12illustrate various examples of apparatuses that may include one or more of the transistor arrangements with one or more stacked trench contacts and/or one or more gate straps disclosed herein.

FIGS.9A-9Bare top views of a wafer2000and dies2002that may include one or more IC structures with one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps in accordance with any of the embodiments disclosed herein. In some embodiments, the dies2002may be included in an IC package, in accordance with any of the embodiments disclosed herein. For example, any of the dies2002may serve as any of the dies2256in an IC package2200shown inFIG.10. The wafer2000may be composed of semiconductor material and may include one or more dies2002having IC structures formed on a surface of the wafer2000. Each of the dies2002may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more layers of an IC structure with at least one transistor arrangement with one or more stacked trench contacts and/or one or more gate straps as described herein), the wafer2000may undergo a singulation process in which each of the dies2002is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as disclosed herein may take the form of the wafer2000(e.g., not singulated) or the form of the die2002(e.g., singulated). The die2002may include supporting circuitry to route electrical signals to various memory cells, transistors, capacitors, as well as any other IC components. In some embodiments, the wafer2000or the die2002may implement or include a memory device (e.g., a static RAM (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die2002. For example, a memory array formed by multiple memory devices may be formed on a same die2002as a processing device (e.g., the processing device2402ofFIG.12) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG.10is a side, cross-sectional view of an example IC package2200that may include one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package2200may be a system-in-package (SiP).

The package substrate2252may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face2272and the face2274, or between different locations on the face2272, and/or between different locations on the face2274.

The package substrate2252may include conductive contacts2263that are coupled to conductive pathways2262through the package substrate2252, allowing circuitry within the dies2256and/or the interposer2257to electrically couple to various ones of the conductive contacts2264(or to other devices included in the package substrate2252, not shown).

The IC package2200may include an interposer2257coupled to the package substrate2252via conductive contacts2261of the interposer2257, first-level interconnects2265, and the conductive contacts2263of the package substrate2252. The first-level interconnects2265illustrated inFIG.10are solder bumps, but any suitable first-level interconnects2265may be used. In some embodiments, no interposer2257may be included in the IC package2200; instead, the dies2256may be coupled directly to the conductive contacts2263at the face2272by first-level interconnects2265.

The IC package2200may include one or more dies2256coupled to the interposer2257via conductive contacts2254of the dies2256, first-level interconnects2258, and conductive contacts2260of the interposer2257. The conductive contacts2260may be coupled to conductive pathways (not shown) through the interposer2257, allowing circuitry within the dies2256to electrically couple to various ones of the conductive contacts2261(or to other devices included in the interposer2257, not shown). The first-level interconnects2258illustrated inFIG.10are solder bumps, but any suitable first-level interconnects2258may be used. As used herein, a “conductive contact” may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

In some embodiments, an underfill material2266may be disposed between the package substrate2252and the interposer2257around the first-level interconnects2265, and a mold compound2268may be disposed around the dies2256and the interposer2257and in contact with the package substrate2252. In some embodiments, the underfill material2266may be the same as the mold compound2268. Example materials that may be used for the underfill material2266and the mold compound2268are epoxy mold materials, as suitable. Second-level interconnects2270may be coupled to the conductive contacts2264. The second-level interconnects2270illustrated inFIG.10are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects2270may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects2270may be used to couple the IC package2200to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference toFIG.11.

The dies2256may take the form of any of the embodiments of the die2002discussed herein (e.g., may include any of the embodiments of the IC structures with transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein). In embodiments in which the IC package2200includes multiple dies2256, the IC package2200may be referred to as a multi-chip package (MCP). The dies2256may include circuitry to perform any desired functionality. For example, one or more of the dies2256may be logic dies (e.g., silicon-based dies), and one or more of the dies2256may be memory dies (e.g., high bandwidth memory). In some embodiments, any of the dies2256may include one or more IC structures with one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as discussed above; in some embodiments, at least some of the dies2256may not include any transistor arrangements with one or more stacked trench contacts and/or one or more gate straps.

The IC package2200illustrated inFIG.10may be a flip chip package, although other package architectures may be used. For example, the IC package2200may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package2200may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies2256are illustrated in the IC package2200ofFIG.10, an IC package2200may include any desired number of the dies2256. An IC package2200may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face2272or the second face2274of the package substrate2252, or on either face of the interposer2257. More generally, an IC package2200may include any other active or passive components known in the art.

FIG.11is a cross-sectional side view of an IC device assembly2300that may include components having one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps in accordance with any of the embodiments disclosed herein. The IC device assembly2300includes a number of components disposed on a circuit board2302(which may be, e.g., a motherboard). The IC device assembly2300includes components disposed on a first face2340of the circuit board2302and an opposing second face2342of the circuit board2302; generally, components may be disposed on one or both faces2340and2342. In particular, any suitable ones of the components of the IC device assembly2300may include any of one or more IC structures with one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly2300may take the form of any of the embodiments of the IC package2200discussed above with reference toFIG.10(e.g., may include one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps provided on a die2256).

In some embodiments, the circuit board2302may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board2302. In other embodiments, the circuit board2302may be a non-PCB substrate.

The IC device assembly2300illustrated inFIG.11includes a package-on-interposer structure2336coupled to the first face2340of the circuit board2302by coupling components2316. The coupling components2316may electrically and mechanically couple the package-on-interposer structure2336to the circuit board2302, and may include solder balls (e.g., as shown inFIG.11), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure2336may include an IC package2320coupled to an interposer2304by coupling components2318. The coupling components2318may take any suitable form for the application, such as the forms discussed above with reference to the coupling components2316. The IC package2320may be or include, for example, a die (the die2002ofFIG.9B), an IC device, or any other suitable component. In particular, the IC package2320may include one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps as described herein. Although a single IC package2320is shown inFIG.11, multiple IC packages may be coupled to the interposer2304; indeed, additional interposers may be coupled to the interposer2304. The interposer2304may provide an intervening substrate used to bridge the circuit board2302and the IC package2320. Generally, the interposer2304may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer2304may couple the IC package2320(e.g., a die) to a BGA of the coupling components2316for coupling to the circuit board2302. In the embodiment illustrated inFIG.11, the IC package2320and the circuit board2302are attached to opposing sides of the interposer2304; in other embodiments, the IC package2320and the circuit board2302may be attached to a same side of the interposer2304. In some embodiments, three or more components may be interconnected by way of the interposer2304.

The interposer2304may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer2304may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer2304may include any number of metal lines2310, vias2308, and through-silicon vias (TSVs)2306. The interposer2304may further include embedded devices2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer2304. The package-on-interposer structure2336may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly2300may include an IC package2324coupled to the first face2340of the circuit board2302by coupling components2322. The coupling components2322may take the form of any of the embodiments discussed above with reference to the coupling components2316, and the IC package2324may take the form of any of the embodiments discussed above with reference to the IC package2320.

The IC device assembly2300illustrated inFIG.11includes a package-on-package structure2334coupled to the second face2342of the circuit board2302by coupling components2328. The package-on-package structure2334may include an IC package2326and an IC package2332coupled together by coupling components2330such that the IC package2326is disposed between the circuit board2302and the IC package2332. The coupling components2328and2330may take the form of any of the embodiments of the coupling components2316discussed above, and the IC packages2326and2332may take the form of any of the embodiments of the IC package2320discussed above. The package-on-package structure2334may be configured in accordance with any of the package-on-package structures known in the art.

FIG.12is a block diagram of an example computing device2400that may include one or more components with one or more transistor arrangements with one or more stacked trench contacts and/or one or more gate straps in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device2400may include a die (e.g., the die2002, shown inFIG.9B) implementing transistor arrangements with one or more stacked trench contacts and/or one or more gate straps in accordance with any of the embodiments disclosed herein. Any of the components of the computing device2400may include an IC package2200(e.g., as shown inFIG.10). Any of the components of the computing device2400may include an IC device assembly2300(e.g., as shown inFIG.11).

A number of components are illustrated inFIG.12as included in the computing device2400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device2400may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system on a chip (SoC) die.

Additionally, in various embodiments, the computing device2400may not include one or more of the components illustrated inFIG.12, but the computing device2400may include interface circuitry for coupling to the one or more components. For example, the computing device2400may not include a display device2406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device2406may be coupled. In another set of examples, the computing device2400may not include an audio input device2418or an audio output device2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device2418or audio output device2408may be coupled.

The computing device2400may include a processing device2402(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device2402may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device2400may include a memory2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory2404may include memory that shares a die with the processing device2402.

In some embodiments, the computing device2400may include a communication chip2412(e.g., one or more communication chips). For example, the communication chip2412may be configured for managing wireless communications for the transfer of data to and from the computing device2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

The communication chip2412may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip2412may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip2412may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip2412may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip2412may operate in accordance with other wireless protocols in other embodiments. The computing device2400may include an antenna2422to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip2412may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip2412may include multiple communication chips. For instance, a first communication chip2412may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip2412may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip2412may be dedicated to wireless communications, and a second communication chip2412may be dedicated to wired communications.

The computing device2400may include battery/power circuitry2414. The battery/power circuitry2414may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device2400to an energy source separate from the computing device2400(e.g., AC line power).

The computing device2400may include a display device2406(or corresponding interface circuitry, as discussed above). The display device2406may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device2400may include an audio output device2408(or corresponding interface circuitry, as discussed above). The audio output device2408may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device2400may include an audio input device2418(or corresponding interface circuitry, as discussed above). The audio input device2418may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device2400may include a GPS device2416(or corresponding interface circuitry, as discussed above). The GPS device2416may be in communication with a satellite-based system and may receive a location of the computing device2400, as known in the art.

The computing device2400may include an other output device2410(or corresponding interface circuitry, as discussed above). Examples of the other output device2410may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device2400may include an other input device2420(or corresponding interface circuitry, as discussed above). Examples of the other input device2420may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The computing device2400may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device2400may be any other electronic device that processes data.

Select Examples

The following paragraphs provide various examples of the embodiments disclosed herein.

Example 1 provides a transistor arrangement that includes a channel material; a gate electrode material (e.g., the gate electrode material536, shown in the present drawings) provided over a gate portion of the channel material; a source or drain (S/D) contact material (e.g., the S/D contact material542, shown in the present drawings) provided in a portion of the channel material adjacent to the gate portion of the channel material; a first electrically conductive material (TCN1 material) (e.g., the first trench contact material544, shown in the present drawings) provided over the S/D contact material; a second electrically conductive material (TCN2 material) (e.g., the second trench contact material548, shown in the present drawings) provided over the TCN1 material; and a gate contact via (VCG) provided over a portion of the gate electrode material as a via opening provided over a portion of the gate electrode material, the via opening having a dielectric material (e.g., the dielectric material552, shown in the present drawings) at sidewalls of the via opening and at least a portion of a bottom of the via opening, and further having a third electrically conductive material (VCG material) (e.g., the VCG material554, shown in the present drawings) filling at least a portion of the via opening with the dielectric material. In such a transistor arrangement, the dielectric material at a sidewall of the via opening closest to the TCN2 material is between, and, therefore, electrically isolates, the VCG material and the TCN2 material. Furthermore, the dielectric material at the bottom of the via opening is between, and therefore, electrically isolates, the VCG material and the TCN1 material provided over the S/C-S/D contact material.

Example 2 provides the transistor arrangement according to example 1, where the via opening is self-aligned to the TCN2 material.

Example 3 provides the transistor arrangement according to examples 1 or 2, where the dielectric material has a seam (e.g., the seam547, described herein) in a portion of the via opening between a sidewall of the via opening that is closest to the TCN2 material and a sidewall of the gate electrode material, i.e., proximate to the bottom of the via opening.

Example 4 provides the transistor arrangement according to any one of the preceding examples, where the TCN1 material is recessed with respect to the gate electrode material.

Example 5 provides the transistor arrangement according to example 4, where a distance between a top of the TCN1 material and a top of the gate electrode material (i.e., the recess of the TCN1 material with respect to the gate electrode material) is at least about 5 nanometers, e.g., at least about 10 nanometers, e.g., between about 5 and 20 nanometers.

Example 6 provides the transistor arrangement according to examples 4 or 5, where a lowest portion at the bottom of the via opening is aligned with a top of the TCN1 material.

Example 7 provides the transistor arrangement according to any one of the preceding examples, where the VCG material is in contact with a portion of a top of the gate electrode material and a portion of a sidewall of the gate electrode material.

Example 8 provides the transistor arrangement according to any one of the preceding examples, where the gate portion of the channel material is a first gate portion and where the transistor arrangement further includes the gate electrode material provided over a second gate portion of the channel material, different from the first gate portion (e.g., the gate electrode material provided over the first gate portion of the channel material is the gate electrode material of the gate536-2, while the gate electrode material provided over the second gate portion of the channel material is the gate electrode material of the gate536-1). Furthermore, the dielectric material is a first dielectric material, the transistor arrangement further includes a second dielectric material (e.g., the dielectric material of the additional gate spacer540, shown in the present drawings) provided over a top of the gate electrode material provided over the second gate portion (e.g., provided over the gate563-1of the present drawings), and a portion of the second dielectric material is between, and, therefore, electrically isolates, the TCN2 material and the gate electrode material provided over the second gate portion.

Example 9 provides the transistor arrangement according to example 8, further including an etch-stop material (e.g., the etch-stop material535-2, shown in the present drawings) provided over a portion of the second dielectric material that is not between the TCN2 material and the gate electrode material provided over the second gate portion.

Example 10 provides the transistor arrangement according to examples 8 or 9, further including the second dielectric material between the gate electrode material provided over the second gate portion and the TCN1 material.

Example 11 provides the transistor arrangement according to any one of examples 8-10, further including the TCN1 material in contact with a top portion of the gate electrode material provided over the second gate portion.

Example 12 provides the transistor arrangement according to any one of examples 8-11, further including the TCN1 material in contact with a top portion of the gate electrode material provided over the first gate portion.

Example 13 provides the transistor arrangement according to example 12, where the TCN1 material in contact with the top portion of the gate electrode material provided over the first gate portion is further in contact with the VCG material.

Example 14 provides the transistor arrangement according to any one of the preceding examples, where the channel material is shaped as a fin or as a nanoribbon.

Example 15 provides the transistor arrangement according to any one of the preceding examples, where the transistor arrangement is a part of at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.

Example 16 provides an IC package that includes an IC die, including a transistor arrangement; and a further IC component, coupled to the IC die. The transistor arrangement includes a channel material, a gate electrode material (e.g., the gate electrode material536, shown in the present drawings) provided over a gate portion of the channel material, a source or drain (S/D) contact material (e.g., the S/D contact material542, shown in the present drawings) provided in a portion of the channel material adjacent to the gate portion of the channel material, a first electrically conductive material (TCN1 material) (e.g., the first trench contact material544, shown in the present drawings) provided over the S/D contact material, a second electrically conductive material (TCN2 material) (e.g., the second trench contact material548, shown in the present drawings) provided over the TCN1 material, and a gate contact via (VCG) provided over a portion of the gate electrode material as a via opening provided over a portion of the gate electrode material, the via opening having a dielectric material (e.g., the dielectric material552, shown in the present drawings) at sidewalls of the via opening and at least a portion of a bottom of the via opening, and further having a third electrically conductive material (VCG material) (e.g., the VCG material554, shown in the present drawings) filling at least a portion of the via opening with the dielectric material, where a lowest portion in the bottom of the via opening is aligned with a top of the TCN1 material.

Example 17 provides the IC package according to example 16, where the further IC component includes one of a package substrate, an interposer, or a further IC die.

Example 18 provides the IC package according to examples 16 or 17, where the IC die includes, or is a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.

Example 19 provides a method of fabricating a transistor arrangement, the method including providing a channel material; providing a gate electrode material (e.g., the gate electrode material536, shown in the present drawings) provided over a gate portion of the channel material; providing a source or drain (S/D) contact material (e.g., the S/D contact material542, shown in the present drawings) provided in a portion of the channel material adjacent to the gate portion of the channel material; providing a first electrically conductive material (TCN1 material) (e.g., the first trench contact material544, shown in the present drawings) provided over the S/D contact material; providing a second electrically conductive material (TCN2 material) (e.g., the second trench contact material548, shown in the present drawings) provided over the TCN1 material; and providing a gate contact via (VCG) provided over a portion of the gate electrode material as a via opening provided over a portion of the gate electrode material, the via opening having a dielectric material (e.g., the dielectric material552, shown in the present drawings) at sidewalls of the via opening and at least a portion of a bottom of the via opening, and further having a third electrically conductive material (VCG material) (e.g., the VCG material554, shown in the present drawings) filling at least a portion of the via opening with the dielectric material. In such method, the dielectric material at a sidewall of the via opening closest to the TCN2 material is between, and, therefore, electrically isolates, the VCG material and the TCN2 material, and the dielectric material at the bottom of the via opening is between, and, therefore, electrically isolates, the VCG material and the TCN1 material.

Example 20 provides the method according to example 19, further including self-aligning the via opening to the TCN2 material.

In further examples, the method according to any one of examples 19-20 may further include processes for forming the transistor arrangement and/or the IC package according to any one of the preceding examples.

Example 21 provides a transistor arrangement that includes a channel material; a gate electrode material (e.g., the gate electrode material536, shown in the present drawings) provided over a gate portion of the channel material; a source or drain (S/D) contact material (e.g., the S/D contact material542, shown in the present drawings) provided in a portion of the channel material adjacent to the gate portion of the channel material; a first electrically conductive material (TCN1 material) (e.g., the first trench contact material544, shown in the present drawings) provided over (e.g., in contact with) the S/D contact material; and the TCN1 material in contact with a top portion of the gate electrode material, where the TCN1 material in contact with the top portion of the gate electrode material is electrically isolated from the TCN1 material provided over the S/D contact material.

Example 22 provides the transistor arrangement according to example 21, further including a first gate spacer material provided over sidewalls of the gate electrode material; and a second gate spacer material provided over sidewalls of the TCN1 material in contact with the top portion of the gate electrode material.

Example 23 provides the transistor arrangement according to example 22, where the second gate spacer material is further provided over the sidewalls of the gate electrode material so that the first gate spacer material is between the gate electrode material and the second gate spacer material.

Example 24 provides the transistor arrangement according to example 23, where the second gate spacer material is between the first gate spacer material and the TCN1 material provided over the S/D contact material.

Example 25 provides the transistor arrangement according to examples 23 or 24, where the first gate spacer material is between the gate electrode material and the TCN1 material provided over the S/D contact material.

Example 26 provides the transistor arrangement according to any one of examples 21-25, where the channel material is shaped as a fin or as a nanoribbon.

Example 27 provides the transistor arrangement according to any one of examples 21-26, where the transistor arrangement is a part of at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.

Example 28 provides an IC package that includes an IC die, including a transistor arrangement according to any one of examples 21-27; and a further IC component, coupled to the IC die.

Example 29 provides the IC package according to example 28, where the further IC component includes one of a package substrate, an interposer, or a further IC die.

Example 30 provides the IC package according to examples 28 or 29, where the IC die includes, or is a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.

Example 31 provides a method of fabricating a transistor arrangement, the method including providing a channel material; providing a gate electrode material (e.g., the gate electrode material536, shown in the present drawings) provided over a gate portion of the channel material; providing a source or drain (S/D) contact material (e.g., the S/D contact material542, shown in the present drawings) provided in a portion of the channel material adjacent to the gate portion of the channel material; providing a first electrically conductive material (TCN1 material) (e.g., the first trench contact material544, shown in the present drawings) provided over (e.g., in contact with) the S/D contact material; and providing the TCN1 material in contact with a top portion of the gate electrode material, where the TCN1 material in contact with the top portion of the gate electrode material is electrically isolated from the TCN1 material provided over the S/D contact material.

Example 32 provides the method according to example 31, further including processes for forming the transistor arrangement according to any one of examples 21-27 and/or the IC package according to any one of examples 28-30.

Example 33 provides an electronic device that includes a carrier substrate; and an IC die coupled to the carrier substrate, where the IC die includes the transistor arrangement according to any one of examples 1-15 or any one of examples 21-27, or is included in the IC package according to any one of examples 16-18 or any one of examples 28-30.

Example 34 provides the electronic device according to example 33, where the electronic device is a wearable electronic device (e.g., a smart watch) or handheld electronic device (e.g., a mobile phone).

Example 35 provides the electronic device according to examples 33 or 34, where the electronic device further includes one or more communication chips and an antenna.

Example 36 provides the electronic device according to any one of examples 33-35, where the carrier substrate is a motherboard.

Example 37 provides the electronic device according to any one of examples 33-36, where the electronic device is an RF transceiver.

Example 38 provides the electronic device according to any one of examples 33-37, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g. of an RF transceiver.

Example 39 provides the electronic device according to any one of examples 33-38, where the electronic device is included in a base station of a wireless communication system.

Example 40 provides the electronic device according to any one of examples 33-38, where the electronic device is included in a user equipment device (i.e., a mobile device) of a wireless communication system.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.