Patent ID: 12204213

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The technical solution in the embodiment of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are merely some embodiments of the present application instead of all embodiments. According to the embodiments in the present application, all other embodiments obtained by those skilled in the art without making any creative effort shall fall within the protection scope of the present application.

In addition, it should be understood that the specific embodiments described here are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the used orientation terminologies such as “upper” and “lower”, when are not specified to the contrary explanation, usually refer to the upper and lower states of the device in actual use or working conditions, specifically according to the direction of the figures in the drawings. Furthermore, “inner” and “outer” refer to the outline of the device.

The embodiment of the present application provides a pixel unit of a display panel, a lower substrate of a display panel, and a display panel to solve a technical issue of a excessive parasitic capacitor between a main pixel electrode of a pixel unit and a data signal line in a conventional display panel further causing serious color crosstalk and vertical crosstalk.

With reference toFIGS.2,3aand3b, the pixel unit3of the display panel provided by the embodiment of the present application comprises: a scan signal line SL, a data signal line DL, a common signal line CL, a pixel electrode P, and a transparent shielding electrode element20.

Agate electrode G is formed on the scan signal line SL.

The data signal line DL perpendicularly intersects the scan signal line SL. An aperture region OA is formed in an intersection location between the scan signal line SL and the data signal line DL, as shown inFIG.3b.

The common signal line CL is disposed to be parallel to the scan signal line SL, and a common electrode C is formed on the common signal line CL.

The pixel electrode P is disposed in the aperture region OA and can comprise a main pixel electrode portion M and a sub-pixel electrode portion S.

The transparent shielding electrode element20is connected to the common signal line CL and extends from the common signal line CL into the aperture region OA, and an orthogonal projection of the transparent shielding electrode element20on a plane where the common signal line CL is located at least partially overlaps the common signal line CL. In particular, a part of the common signal line CL covers a part of the transparent shielding electrode element20, or a part of the transparent shielding electrode element20covers a part of the common signal line CL.

In particular, the transparent shielding electrode element20serves as an electrode for extending a shielding effect of the common signal line CL to further lower the parasitic capacitor between the main pixel electrode portion M and the data signal line DL to further prevent the issues of color crosstalk and vertical crosstalk. In a preferred embodiment of the present application, a material of the transparent shielding electrode element20can be indium tin oxide (ITO).

With reference toFIGS.3a,3b, and4, in an embodiment of the present application, the transparent shielding electrode element20is U-shaped, comprises 1 first shielding section21and two second shielding sections22. The two second shielding sections22extend from the common electrode C into the aperture region OA. An end of each of the second shielding sections22is connected to the common signal line CL, and another end of each of the second shielding sections22is connected to an end of the first shielding section21. An orthogonal projection of each of the second shielding sections22on the plane where the common signal line CL is located at least partially overlap the common signal line CL. Furthermore, the two second shielding sections22are located near the data signal line DL of the pixel unit and another data signal line DL of an adjacent pixel unit further included by the display panel and the two second shielding sections22can located on two sides of main pixel electrode portion M of the pixel electrode P to further lower the parasitic capacitor between the main pixel electrode portion M and the data signal line DL.

With reference toFIGS.5and6, in another embodiment of the present application, the transparent shielding electrode element20acomprises two shielding bars23. The two shielding bars23are individual and spaced from each other, extend from the common signal line CL into the aperture region OA, and an end of each of the shielding bars23is connected to the common signal line CL. An orthogonal projection of each of the shielding bars23on the plane where the common signal line CL is located at least partially overlap the common signal line CL. Furthermore, the two shielding bars23are located near the data signal line DL of the pixel unit and another data signal line DL of an adjacent pixel unit further included by the display panel, and the two shielding bars23can be located on two sides of main pixel electrode portion M of the pixel electrode P to further lower the parasitic capacitor between the main pixel electrode portion M and the data signal line DL.

In some embodiments of the present application, the transparent shielding electrode element20and the common signal line CL are located in different material layers, are elements being individual and separated from each other, and contact and are connected to each other. Alternatively, in some embodiments of the present application, both the transparent shielding electrode element20and the common signal line CL are disposed on a surface of the glass substrate10, and a part of the common electrode C covers a part of the transparent shielding electrode element20, or a part of the transparent shielding electrode element20covers a part of the common electrode C.

With reference toFIGS.2,3a, and3b, the lower substrate of the display panel1provided by the embodiment of the present application, comprises a glass substrate10, and a first metal layer M1, a second metal layer M2, and a first transparent conductive layer30sequentially stacked on the glass substrate10, wherein the lower substrate1further comprises: a scan signal line SL, a data signal line DL, a common signal line CL, pixel electrode P, and a transparent shielding electrode element20.

The scan signal line SL is formed by patterning the first metal layer M1, and a gate electrode G is formed on the scan signal line SL.

The data signal line DL is formed by patterning the second metal layer M2, perpendicularly intersects the scan signal line SL, an aperture region OA is formed in an intersection location between the scan signal line SL and the data signal line DL.

The common signal line CL is disposed in a same layer with the scan signal line SL and is parallel to the scan signal line SL. A common electrode C is formed on the common signal line CL.

The pixel electrode P is formed by patterning the first transparent conductive layer30, is disposed in the aperture region OA, and can comprise a main pixel electrode portion M and a sub-pixel electrode portion S.

The transparent shielding electrode element20is connected to the common signal line CL, extends from the common signal line CL into the aperture region, and an orthogonal projection of the transparent shielding electrode element20on the plane where the common signal line CL is located at least partially overlap the common signal line CL.

In particular, the transparent shielding electrode element20serves as a shielding electrode to shield the common signal line CL to further lower a parasitic capacitor between the main pixel electrode portion M and the data signal line DL, and further prevent the issues of color crosstalk and vertical crosstalk. In a preferred embodiment of the present application, a material of the transparent shielding electrode element20can be indium tin oxide (ITO).

With reference toFIGS.3a,3b, and4, in an embodiment of the present application, the transparent shielding electrode element20is U-shaped and comprises a first shielding section21and two second shielding sections22. The two second shielding sections22extend from the common signal line CL into the aperture region. An end of each of the second shielding sections22is connected to the common signal line CL, and another end of each of the second shielding sections22is connected to an end of the first shielding section21. An orthogonal projection of each of the second shielding sections22on the plane where the common signal line CL is located at least partially overlap the common signal line CL. Furthermore, the two second shielding sections22are located near the data signal line DL of the pixel unit and another data signal line DL of an adjacent the pixel unit further included by the display panel, and the two second shielding sections22can be located on two sides of the main pixel electrode portion M of the pixel electrode P respectively to further lower a parasitic capacitor between the main pixel electrode portion M and the data signal line DL.

In particular, the lower substrate of the display panel1provided by the embodiment of the present application further comprises an insulation layer GI, semiconductor layer (not shown), a first passivation layer PV1, a color photoresist layer CF, and a second passivation layer PV2. The glass substrate10, the first metal layer M1, the insulation layer GI, the semiconductor layer, the second metal layer M2, the first passivation layer PV1, the color photoresist layer CF, the second passivation layer PV2, and the first transparent conductive layer30are sequentially stacked on one another to form the lower substrate1.

With reference toFIGS.5and6, in another embodiment of the present application, the transparent shielding electrode element20comprises two shielding bars23. The two shielding bars23are individual and spaced from each other, and extend from the common signal line CL into the aperture region. An end of each of the shielding bars23is connected to the common signal line CL, and an orthogonal projection of each of the shielding bars23on the plane where the common signal line CL is located at least partially overlap the common signal line CL. Furthermore, the two shielding bars23are located near the data signal line DL of the pixel unit and another data signal line DL of an adjacent pixel unit further included by the display panel, and the two shielding bars23can be located two sides of the main pixel electrode portion M of the pixel electrode P respectively to further lower the parasitic capacitor between the main pixel electrode portion M and the data signal line DL.

In some embodiments of the present application, the transparent shielding electrode element20is formed by patterning the second transparent conductive layer. In particular, the second transparent conductive layer is disposed between the glass substrate10and the first metal layer M1. The transparent shielding electrode element20is formed by patterning the second transparent conductive layer with a lithography process.

In another aspect, the display panel provided by the embodiment of the present application comprises: the lower substrate1of the above embodiment, an upper substrate2disposed opposite to the lower substrate1, and a liquid crystal layer LC disposed between the upper substrate2and the lower substrate1. In particular, upper substrate2further comprises a black matrix BM to define the aperture region OA. Furthermore, the upper substrate2further comprises an upper substrate common electrode CC and a top cover CG, as shown inFIG.2.

The following comparison table is for comparison between a parasitic capacitor of the above pixel unit before increasing the transparent shielding electrode element20and after increasing the transparent shielding electrode element20. It can be understood from the comparison table that after the U-shaped transparent electrode is increased, the parasitic capacitor of the main pixel electrode portion M can be decreased to 12% of an original value, and the parasitic capacitor/total capacitor is reduced from 1.24% to 0.15%, which indicates that the transparent shielding electrode element20has a parasitic capacitor reduction effect. When an area of the transparent shielding electrode element20is sufficiently increased, the parasitic capacitor/total capacitor would be smaller.

Before increase ofAfter increase of theAfter increase ofthe transparentU-shaped transparent11-shaped transparentMain pixel electrodeshielding electrodeshielding electrodeshielding electrodeportion Melement 20element 20element 20Parasitic capacitor [fF]4.0700.4860.561Total capacitor [fF]327.560333.259331.566Parasitic1.24%0.15%0.17%capacitor/Totalcapacitor

The present application at least comprises advantages as follows:

The pixel unit of the display panel, the lower substrate1of the display panel, and the display panel provided by the present application, by disposing a transparent shielding electrode element20connected to a common electrode C and extending into the aperture region and making an orthogonal projection of the transparent shielding electrode element20on a plane where the common signal line CL is located at least partially overlap the common signal line CL, extends a shielding effect provided by the common signal line CL such that a parasitic capacitor between the pixel electrode and the data line is lowered to solve the technical issue of a excessive parasitic capacitor between a main pixel electrode portion M of a pixel unit and a data signal line in a conventional display panel further causing serious color crosstalk and vertical crosstalk. Furthermore, because the transparent shielding electrode element20and the pixel electrode P of the present application are transparent conductive electrodes, therefore the transparent shielding electrode element20extending into the aperture region would not reduce an aperture rate and a transmittance of the pixel unit to prevent reduction of the aperture rate and the transmittance of a shielding metal of the conventional pixel unit located in the aperture region.

In the specification, the specific examples are used to explain the principle and embodiment of the present application. The above description of the embodiments is only used to help understand the method of the present application and its spiritual idea. Meanwhile, for those skilled in the art, according to the present the idea of invention, changes will be made in specific embodiment and application. In summary, the contents of this specification should not be construed as limiting the present application.