Patent ID: 12210404

DETAILED DESCRIPTION

It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment of the invention. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.

Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

Events such as noise, aborted packets, or other unexpected events on the eUSB or USB bus lead, on occasion, to a simple repeater design becoming confused and potentially locking up in a state that prevents the repeater from further operating correctly in the repeating mode. A lockup detection circuit is described herein that provides a small circuit to detect eUSB repeater lockup conditions and provides error recovery to allow correct operation afterwards.

The eUSB2 Specification describes a supplement to USB 2.0 for low voltage, embedded use that operates in all three speed modes of USB 2.0: USB 1.0 Low Speed; USB 1.1 Full Speed; and USB 2.0 High Speed. Low Speed and Full Speed use single-ended signaling in eUSB2, while High Speed (sometimes called Hi-Speed) uses differential signaling in eUSB2. The eUSB2 Specification refers to repeater mode as eUSB2 to USB2 or as USB2 to eUSB2 regardless of the speed mode. In the present description “eUSB” will be used to refer to any modes of eUSB2 or any other suitable single-ended signaling system and “USB” will be used to refer to any modes of USB 2.0 or any other suitable modes of differential signaling. While the present description is presented in the context of Universal Serial Bus structures and methods, the structure and methods herein may be applied to translations between other single-ended and differential signaling systems. While the present description is presented in the context of Low Speed and High Speed mode, the present description may be applied to other modes and to successors of these modes, notwithstanding changes to the naming conventions that are used. It should be noted that USB has been implemented without consistently enforced naming conventions and that even these inconsistent naming conventions may be changed retroactively. Thus, it may happen that “USB 2.0” may soon be referred to primarily as “USB2.”

FIG.1is a block diagram of a system on a chip (SoC)102that is coupled to multiple peripheral devices using eUSB. The SoC102is coupled to a first eUSB device104through an eUSB connection114, which may be a single-ended connection in at least some modes. The SoC has a downstream eUSB2 port in native mode (eDSPn). The device has an upstream eUSB2 port in native mode (eUSPn). The eUSB connection114between these ports has lines with an eUSB2 data+ pin (eD+) and an eUSB2 data− pin (eD−). The eUSB connection114may be through PCB traces, wire lines, or any other suitable internal or embedded connection. An nth eUSB device106is coupled through an nth eUSB connection116.

The SoC102is also coupled to one or more legacy USB devices120. The SOC has a downstream eUSB2 port facing host repeater (eDSPr). That is connected through an eUSB connection118to an upstream eUSB2 port of the host repeater (eUSPh) at an eUSB2 repeater108. The eUSB2 repeater108connects through a USB2 connection122to one or more legacy USB devices120.

As shown, the SOC102operates in two modes of operation: native mode and repeater mode. The native mode refers to a host port, eDSPn) of the SoC102communicating directly to native eUSB devices104,106through a device port, eUSPn, both implementing an eUSB PHY and communicating based on eUSB signaling, for example eUSB2 signaling. Native mode eUSB is particularly suitable for inter-chip interconnect.

Repeater mode refers to an eUSB port, eDSPr, of the SoC102communicating with a USB port of a legacy USB device120through a repeater108that translates between eUSB signaling and USB signaling, for example eUSB2 and USB 1.0, USB 1.1 or USB 2.0 signaling.

FIG.2is a block diagram of a host SoC222coupled to a peripheral SoC242connected through a USB line228, for example a cable or PCB traces. In this example, the host SoC222is coupled through an eUSB link206with eD+/eD− lines to a host repeater224. The peripheral SoC242is coupled through an eUSB link246with eD+/eD− lines to a peripheral repeater244. The host repeater224and the peripheral repeater244are connected together using the USB line228with D+/D− lines. The host repeater224and the peripheral repeater244communicate with each other in a repeater mode, indicated as eUSB-USB. This configuration may be suitable for when two eUSB devices are connected through a USB line228, for example a cable and USB connectors or ports at both sides of the device ports. The host SoC222and the peripheral SoC242are able to communicate using the lower voltage single-ended signaling that is more suitable for the physical construction of ICs while being connected using the more robust, higher voltage, USB differential signaling through the USB line228. The host SoC and peripheral SoC may also be coupled to other devices (not shown) in native mode and in repeater mode.

FIG.3is a signal timing diagram of a Full Speed packet being sent from an eUSB Host302to an eUSB Device308through a Host eUSB repeater304and a Device eUSB repeater306. Full Speed mode, originally introduced with USB 1.1. is supported as a legacy mode in USB 2.0 and with a few changes from USB 1.1 in eUSB2. The top portion of the signal timing diagram shows the Host side eUSB bus303, between the eUSB Host302and the Host eUSB repeater304. The middle portion of the signal timing diagram shows the USB bus305between the Host eUSB repeater304and the Device eUSB repeater306. The bottom portion of the signal timing diagram shows the Device side eUSB bus307between the Device eUSB repeater306and the eUSB Device308.

The eUSB Host302initiates a Full Speed packet on the Host side eUSB bus303. The packet from the eUSB Host302is shown on the top portion of the timing signal diagram. The majority of the packet is sent on the eUSB bus eD− signal. The packet starts with the typical USB packet SYNC pattern310, KJKJKJKK, and then is followed by the normal packet data312. The packet ends with an End of Packet (EOP) pattern314, toggling on the eUSB bus eD+ signal.

The middle portion of the timing signal diagram ofFIG.3shows how the Full Speed packet from the eUSB Host302gets translated by the Host eUSB Repeater304and generated onto the USB bus305. The Host eUSB repeater304first translates the single-ended signaling on eD− to differential signaling on the USB bus305. This happens to translate the SYNC pattern320and to translate the packet data322. When the EOP pattern314occurs on the host side eUSB eD+ signal, the eUSB Repeater converts that to a USB formatted EOP for the USB bus. The first rising edge on eD+342causes the eUSB repeater to drive an SE0324signal (Single-Ended Zero) on the differential lines in which the signal on both lines of the USB bus305are low. The second rising edge on eD+344causes the eUSB Repeater to drive the USB bus305to a differential data J state326. The last falling edge on eD+346then causes the eUSB Repeater to tristate the USB bus and let the USB pullup and pulldown resistors hold the bus in an Idle J state. The SE0324condition provides a time gap between data packets.

For a digital data line with two voltage states, high and low, a tristate is a third state for which the line is set to a high impedance (high Z) with no particular applied voltage. As a result, any other device connected to the line is able to control the state of the line.

The Device eUSB repeater306translates the signals on the USB bus305into eUSB single-ended signaling as shown on the Device side eUSB bus307on the bottom section of the timing signal diagram. The SYNC pattern320on USB bus305causes the Device eUSB repeater306to drive the device side eUSB eD− line with the SYNC pattern330. The packet data322on the USB bus305is translated as a data pattern332on the eUSB eD− line. The EOP on the USB bus305which is an SE0324followed by data J and idle J causes the Device eUSB repeater306to drive the eUSB eD+ line high to generate an EOP signal334during the USB bus SE0 condition and then low afterwards.

USB Full Speed packets are also sent from the eUSB Device308to the eUSB Host302through the Device eUSB repeater306and the Host eUSB repeater304. The packet and EOP signals from the eUSB Device308are the same as those from the eUSB Host302and translated through the repeaters in the same way but in the opposite direction. These signals are defined in the eUSB2 Specification and there is a reciprocity that applies to signals so that they are the same regardless of direction.

WhileFIG.3shows USB Full Speed mode packets in eUSB, USB Low Speed mode is also supported and may be used for packets from the Host to the Device and vice versa. In Low Speed mode the eUSB signals are swapped from how they are sent during Full Speed mode. Instead of using eD− on the single-ended line, it is eD+ which carries the SYNC signal and the packet data. Instead of eD+, it is eD− which carries the packet's EOP signals. Otherwise, the repeaters perform the same functions. The differential signals of the USB signal are the same except with reversed polarity. For example, a Full Speed J is transmitted as D+ being high while D− is low. A Low Speed J is transmitted as D− being high while D+ is low. In repeater mode, also referred to as transparent mode, the repeaters facilitate the passing of packets from each bus to the other bus, converting the single-ended signals to differential signals and vice versa as shown inFIG.3. At an eUSB Repeater, if eD+ rises before eD−, then this indicates the start of a Low Speed mode packet. If eD− rises before eD+, then this indicates the start of a Full Speed mode packet.

Considering the idle signal316from the eUSB Host302or conversely from the eUSB Device308, the single-ended line eD− is driven low for at least a certain duration before the eUSB Host302tristates the line eD−. This is shown as a dotted line348which extends beyond the diagram. The low state may last for 20-70 ns. In some examples, the line may be driven strongly low for 20-70 ns. After that the line may be tristated with pulldown resistors or some other means holding the value.

On the USB bus305, there is a string of transitions during the SYNC pattern320and the packet data322. At any of the data bit transitions on the USB bus305from J to K or K to J, there may be a period of time during which both of the two input lines D+/D− are low before finally transitioning to the next bit state. This low state is referred to as SE0 (Single-Ended Zero). Instead of a clean J to K transition, the USB bus305may, for example, transition from J to SE0 and then from SE0 to K. This SE0 period is supposed to be less than 14 ns for USB Full Speed mode timing and less than 210 ns for USB Low Speed mode timing. An eUSB Repeater304,306translating the packet from USB to eUSB filters out the temporary SE0 conditions.

The operation of the repeater may be summarized as facilitating the passing of packets from each bus to the other bus, converting the single-ended packets to differential packets and the differential packets to single-ended packets. In order to provide small, fast, low-cost repeaters that can still parse the structure of the packets, state machines or simple logic architectures may be used. However, if there is noise on one of the busses, then these state machine-based designs may parse the input signal as a SYNC bit and enable the other side of the repeater to pass the packet through. If only noise was received, the eUSB repeater will not receive more signaling which looks like a packet. Therefore, it may get stuck. Another situation which could happen is if the host or device (or USB2 hub) aborts a packet transmission for some reason. This is not expected, but if it does occur then the same error condition could occur. The eUSB repeater may have received packet SYNC bits and some amount of data, but never receives the packet EOP. The repeater will be stuck waiting for the EOP signal, all while still driving the destination bus. If the repeater gets in a stuck state, then it cannot facilitate further packet delivery and may cause contention on one of its busses that is stuck in a driving state while another device may want to drive data.

The described Lockup Detection circuit allows state-based eUSB repeater PHY designs to recover from unexpected error conditions on the eUSB or USB2 buses which may look like packet data. Examples are noise on either bus or partially sent packets which are aborted before the EOP is sent. The Lockup Detection circuit senses enable signals to determine when the repeater is enabling the eUSB transmitter for a prolonged time while the USB2 bus receiver is set to an idle J or when the USB2 transmitter is enabled for a prolonged time while the eUSB bus is idle, for example in an SE0 condition. When the time is too long a lockup condition is declared and the internal state flip-flops in the eUSB to USB2 Repeating Mode Logic and in the USB2 to eUSB Repeating Mode Logic are reset. While flip-flops are described and shown, any other type of state machine may be used. Resetting the eUSB repeater may be performed by applying reset signal to the state elements of the eUSB repeater that control the signal paths through the repeater. The Lockup Detection circuit may modify the detection approach when the repeater is in full speed or low speed modes.

In operation, for incoming eUSB packets, the repeater will look for the start of a packet as the presence of the first SYNC bit of the SYNC pattern and enable the other side of the eUSB repeater, the USB2 full speed driver, to pass the incoming packet from eUSB to USB2. The drivers will then pass the SYNC bits and packet data carried on the eUSB data line (eD− for full speed mode and eD+ for low speed mode) to the USB2 bus. Once the end of the packet arrives on the eUSB control line (eD+ for full speed mode and eD− for low speed mode), then the repeater will use the first portion of the EOP (high going pulse on eUSB control line followed by low period) to drive an SE0 condition on the USB2 bus. The repeater then uses the end of the EOP (second high going pulse on eUSB control line) to drive the USB2 bus to a data J condition before releasing the bus.

In the reverse direction from USB2 to eUSB. The repeater uses the same strategy to pass packets from USB2 to eUSB converting from differential signaling to single ended signaling. First the USB2 SYNC bit is detected at the start of the incoming USB2 packet then the eUSB data line is enabled to convert the differential SYNC bits and packet data bits from USB2 to single ended signaling on the eUSB data line. When the SE0 of the EOP is received on the USB2 bus, the eUSB control line can be driven high. Lastly when the EOP ends on the USB2 side, the eUSB lines may be released.

Since the repeater is looking for a very precise and specific behavior, the repeater may lock up any time that the input signal in either direction does not match specific patterns. As a first example, consider a host packet that is aborted during the SYNC or packet data part. When the eUSB repeater sees only the first few SYNC bits, it may get stuck in a state where the host side repeater is driving the USB bus with the FS/LS driver and the device side repeater is stuck in a state driving the eUSB bus eD− (for FS mode). The repeater may be unstuck when a port reset occurs, or when the host sends another packet. The host repeater should unlock as soon as the next packet has its EOP; this should also free up the device side repeater. The same may apply when there is high noise on the eUSB bus or when a packet is aborted on the USB receive bus.

As a second example, consider noise on the host side eUSB bus that causes both repeaters to lock up, and during this lockup condition the device starts sending a packet to the host. Since the device repeater is locked up in the USB to eUSB direction, it will be stuck driving eD− but will not drive USB. Since the host repeater is locked up, it is driving USB to active J. Using the lockup detection circuit herein, the repeaters will eventually be reset. After the device repeater is reset, it will start transmitting the device packet to the host, although the packet will be incomplete since it missed the start of the packet.

FIG.4is a block diagram of a lockup detection circuit410in the context of a repeater400, for example any single-ended to differential repeater or any eUSB to USB repeater. The repeater400has a eUSB transceiver402with a dp single-ended receiver output driver420to generate a received dp signal ana_eusb_rx_dp and a dm single-ended receiver output driver422to generate a received dm signal ana_eusb_rx_dm. In repeater mode, the receive signals are provided to an eUSB to USB Repeating Mode Logic406which provides, in response, transmit signals to a differential transceiver404. The transmit signals are usb_tx_data, that carries the data as described above, and usb_txse0, that provides EOP and SE0 information as shown inFIG.3. An enable signal, usb_tx_en is also provided, and all three are coupled to a transmitter output driver428of the differential transceiver404. The transmitter output driver428generates differential signals for the USB bus as described above.

Referring toFIG.4, the differential transceiver404has a dp single-ended receiver output driver430to generate a received dp signal ana_usb_rx_dp and a dm single-ended receiver output driver432to generate a received dm signal ana_usb_rx_dm. Both of these signals are provided to a USB to eUSB Repeating Mode Logic408which provides, in response, transmit signals to the eUSB transceiver402. The transmit signals are data and enable signals for single-ended transmitter output drivers. A dp transmitter output driver424receives an eD+ signal, ana_eusb_tx_dp and a corresponding enable signal ana_eusb_tx_dp_en. A dm transmitter output driver426receives an eD− signal, ana_eusb_tx_dm and a corresponding enable signal ana_eusb_tx_dm_en.

The signals at the eUSB transceiver402and at the differential transceiver404are monitored by the lockup detection circuit410. When a lockup is detected, then the lockup detection circuit410sends a force reset signal to the respective repeating mode logic or both. In addition, high level logic412is coupled to the lockup detection circuit410and to other parts of the repeater400(not shown). For the eUSB to USB Repeating Mode Logic406, the Lockup Detection circuit410may receive a rst_eusb_2_usb signal from the high level logic412at a reset OR gate472or a force_reset signal generated by the lockup detection circuit410. If either of these are high, then the reset OR gate472generates a force_rst_eusb_2_usb signal to the eUSB to USB Repeating Mode Logic406. In a similar way for the USB to eUSB Repeating Mode Logic408, the Lockup Detection circuit410may receive a rst_usb_2_eusb signal from the High Level Logic412at a reset OR gate470or the force_reset signal generated by the lockup detection circuit410. If either of these are high, then the reset OR gate470generates a force_rst_usb_2_eusb signal to the USB to eUSB Repeating Mode Logic406. Note that the same force_reset flag is an input to both of the OR gates470,472so that both directions of the repeater receive the force reset signal if there is a lockup detected in either direction.

The lockup detection circuit410receives the receive and transmit signals from the transceivers and is able to determine whether the repeater is transmitting an output signal in either direction without receiving a corresponding input signal. The received input signals are applied to the center left side of the lockup detection circuit410and the transmitted output enable signals are applied to the upper and lower left side of the lockup detection circuit410. These are compared over a selected delay time to generate the force_reset signal.

In particular, on the eUSB translator side, the inverse of the received eUSB signals ana_eusb_rx_dp and ana_eusb_rx_dm are applied from the single-ended analog transceiver to an eUSB received logic gate440, in this case an AND gate so that if the eD+ and eD− are both low, then no data is being received on eUSB and the eUSB received logic gate440generates an idle signal eUSB is idle. This corresponds to an idle period, such as an SE0 period or a transmission failure period. The failure may happen when the eUSB sender, e.g., the host, aborts a packet. For the corresponding transmit side, the enable signal, usb_tx_en, for the transmitter output driver428may be used to determine whether data is being transmitted on USB at D+ and D−. This enable signal is provided to an eUSB lockup logic gate442, in this case an AND gate together with the idle signal, el/SB is idle. If there is no received data and the transmitter output driver428is enabled, then there is possibly a lockup on the eUSB repeater side of the repeater400. The eUSB lockup logic gate442generates a psbl_lock_from_eusb signal526.

For the USB translator side, the received USB signals ana_usb_rx_dp and ana_usb_rx_dm are applied to respective USB detection logic gates450,452. Due to the nature of the differential signals on the USB bus, a first fs detection logic gate450, e.g., an AND gate, receives the D+ signal, ana_usb_rx_dp, and the inverse of the D− signal, ana_usb_rx_dm. If the output of the D+ and the inverse of the D− are both high, then, according to the function of the AND gate, the first fs detection logic gate450generates a first idle signal to indicate that the receive side of the USB bus is idle as detected in full-speed mode, usb_fs_is_idle. A second ls detection logic gate452, e.g., an AND gate, receives the D− signal, ana_usb_rx_dm, and the inverse of the D+ signal, ana_usb_rx_dp. If the output of the D− and the inverse of the D+ are both high, then, according to the function of the AND gate, the second Is detection logic gate452generates a signal to indicate that the receive side of the USB bus is idle as detected in low-speed mode, usb_ls_is_idle.

The output of the first FS detection logic gate450and the second LS detection logic gate are both applied to a logic gate454together with a mode selector signal, dig_fsls_mode, from the high level logic412to generate an idle signal usb_is_idle, when the active mode, fs or ls, is idle. The logic gate454selects either the first idle signal or the second idle signal as the output usb_is_idle signal in response to the selector signal, dig_fsls_mode.

For the corresponding transmit side, there is an enable signal for eD+ and eD− signals applied to the transmit output drivers424,426for eUSB. The enable signal, ana_eusb_tx_dp_en, for the for dp transmit output driver424and the enable signal, ana_eusb_tx_dm_en, for the dm transmit output driver426are both applied to an eUSB enable logic gate456together with the mode input, dig_fsls_mode, signal from the high level logic412. The output signal transmitting_on_eusb is coupled to a USB lock gate458. If the usb_is_idle signal and the transmitting_on_eusb signal are both high at the USB lock gate458, then there is possibly a lockup condition on the USB repeater side and the USB lock gate458generates a psbl_lock_from_usb signal. The psbl_lock_from_usb signal indicates that there is no received data and yet the transmitter output drivers424,426are enabled.

The lockup detection circuit monitors when the transmit or output side of the bus is being actively driven but the receive or input side is idle. If this lasts longer than some predetermined amount of time, for example 10 Low Speed unit intervals (UI), then a lockup condition is declared and force reset signal is sent to the repeating mode “eUSB to USB” and “USB to eUSB” logic. These are then reset in some way to clear the lockup condition. In some embodiments, there are flip-flops in the logic that are cleared by the force reset signal. The logic then starts over from an initial state. The force reset signal resets flip-flops or any other state elements that control the signal paths through the repeater in the eUSB to USB logic and the USB to eUSB logic.

FIG.5Ais a timing signal diagram of an error on a host eUSB bus causing a lockup and a reset on a USB bus.FIG.5Bis a timing signal diagram of an error on a USB bus causing a lockup and a reset on a device side eUSB bus. The eUSB bus502signals are represented on eD+ and eD−. The USB bus504signals are differential and are represented by two lines with opposite polarity. The signals on the signal lines ofFIG.4are shown on the signal timing diagram ofFIGS.5A and5B.

Referring toFIG.5A, in operation, the first activity512for FS mode is on the eD− line of the host side eUSB bus502at the eUSB analog transceiver which is the eUSB transceiver402. In LS mode, the first activity will be on the eD+ line of the host side eUSB bus502. In response, the host side eUSB repeater immediately enables its USB side driver, the transmitter output driver428, with the usb_tx_en signal524to pass the eUSB activity to the USB bus504through the USB analog transceiver which is the differential transceiver404. This is shown by the usb_tx_en signal524going high and the USB bus transitioning516with the data.

If, after a few bits, the host aborts514the packet on the eD− line and releases the eUSB bus502, then the host side repeater continues to drive the USB bus even after the host aborts its packet transmission. The lockup detection circuit410monitors the state of the USB bus as well as the state of the eUSB bus. Since the input eUSB bus502is idle due to the aborted packet, but the USB bus is still being driven by the repeater, then the lockup detection logic detects this as a potential lockup. The eusb_is_idle signal522combines the eUSB eD+ and eD− input states to determine when the eUSB bus is idle, for example in an SE0 state. The psbl_lock_from_eusb signal526is generated by the logic based on looking at this as well as the USB transmit drivers to determine when there is a possible lockup.

In the illustrated embodiment, a usb_tx_en signal524is used to detect whether the logic is attempting to drive data on the USB bus504at the USB transceiver. In other logic configurations, a different signal may be used to detect whether the logic is attempting to drive data on the USB bus. As a further alternative, the state of the USB bus may be monitored, for example a state at the output terminals D+, D−.

Referring toFIG.5B, on the device side with the first activity of the bus transitioning516on the USB bus504, the device side eUSB repeater immediately enabled its eUSB side driver to pass the USB activity to the eUSB bus506(driving eD−). This is shown by the ana_eusb_tx_dm_en signal532going high and the eUSB bus transitioning518with the data. But with an aborted packet, the USB bus is left in a prolonged J state520after only a few bits. The device side repeater watches the state of the eUSB bus506(the device side repeater is driving the eUSB bus even after the host aborts its packet transmission) as well as the state of the USB bus504. Since the input bus is idle due to the aborted packet when the host aborts514but the eUSB bus is still being driven by the repeater, then the lockup detection logic detects this as a potential lockup. The usb_is_idle signal534combines the USB D+ and D− input states to determine when the USB bus is idle, for example stuck in a prolonged J state520. The psbl_lock_from_usb signal536is based on receiving the usb_is_idle signal522as well as the eUSB Tx driver signals to determine when there is a possible lockup state.

The two possible lockup signals, the psbl_lock_from_eusb signal526and the psbl_lock_from_usb signal536, are both connected to an OR gate446, the output of which is coupled to a reset test AND gate448. If either or both signals are high, then a high value is applied to the AND gate. The second input is a reset signal from the high level logic412. If the high level logic is not driving a reset or any other suitable activity, then the reset test AND gate448generates a potential_error_condition signal538. The high level logic412may generate a rst_eusb_2_usb signal, rst_usb_2_eusb signal, or another signal that is applied through an OR gate474and inverter to prevent the potential_error_condition signal538. In this way the high level logic preempts any action that is taken or commanded by the lockup detection circuit.

The potential_error_condition signal538is synchronized at a sync logic device460. The sync logic device460may take any of a variety of different forms, for example back-to-back flip-flops. The sync logic device460is coupled to the reset test AND gate448to allow use by a counter464. A force reset logic gate462is coupled to the force_reset flag554and resets the counter464for a force reset. During the time when the USB bus is driven by the host side eUSB repeater but the input eUSB lines are both low, the potential_error_condition signal538is high. The potential_error_condition signal indicates a possible lockup from the USB bus or the eUSB bus or both and the counter is started in response to the possible lockup signal. Upon beings started the counter464increments. The incrementing counter550increments up to reach a pre-configured count stored in a threshold register466, e.g., 10 UI. The counter464and the threshold register466form a timer. The timer duration is determined by the threshold register466. If the eUSB bus becomes a non-SE0 state, then that implies packet activity and so the counter464is cleared to get ready for the next potential lockup condition. If the lockup condition persists and the incrementing counter550has incremented to reach the pre-configured count stored as a timeout value or timer duration in the threshold register466connected to the counter464, then the timer has expired and a lockup_error flag552is asserted by the threshold register466as the timer output. The lockup_error flag552is coupled to a reset flip-flop468to register the lockup_error flag552and create a force_reset flag554. The threshold for the counter may be set based on the operation of the signaling protocols and the repeater. In some embodiments, the threshold value provides at least 10 Low Speed UI worth of lockup condition.

The reset flip-flop468is registered to provide the force_reset flag554for a predetermined amount of time. In some embodiments, the reset flip-flop468is also connected to a system clock, sys_clk, to count some number of clocks worth of reset. Once the force_reset flag554is asserted, then both the force_rst_usb_2_eusb signal556, and the force_rst_eusb_2_usb signal558are asserted and routed to the repeating mode logic of the repeater to reset any flip-flops or other state elements in those circuits to unstick the lockup condition. The two force_reset signals the force_rst_usb_2_eusb signal556and the force_rst_eusb_2_usb signal558are received at the USB to eUSB Repeating Mode Logic408and the eUSB to USB Repeating Mode Logic406, respectively.

The force_reset flag554from the reset flip-flop468is connected to three different logic gates470,472,474. The first logic gate is a reset OR gate470that is also coupled to the rst_usb_2_eusb signal from the high level logic412. If this signal is high, then a reset is already in progress and the force_reset signal is not sent to the USB to eUSB Repeating Mode Logic408. The second logic gate is a reset OR gate472that is also coupled to a rst_eusb_2_usb signal from the high level logic412. If this signal is high, then a reset is already in progress and the force_reset signal is not sent to the eUSB to USB Repeating Mode Logic406.

After the force_reset flag554is asserted the counter464may be cleared at560. At this point in time, the lockup condition is resolved, the detection circuit is ready to detect future lockup conditions, and the repeater is ready to process future packets from either side of the repeater.

While the possible lock up condition signals, the psble_lock_from_usb signal536, and the psble_lock_from_eusb signal526, are routed together through an OR gate446to the reset test AND gate448, this is not required. The counter and threshold tests may be made independent and each generate an independent force_reset. As an example, a psbl_lock_from_usb signal536may be applied to a counter and if a lock is determined then only a force_reset_usb_2_eusb signal542is generated. The counter464or the threshold register466may also be changed based on the Full Speed or Low Speed mode. The signals may be re-routed or the operations changed in response to the mode, for example in response to the fsls_mode signal.

As described above, the lockup detection circuit is able to catch a potential lockup while not interfering with normal operation. The operation is fast but not so fast as to declare a normal packet as an error condition. The operation is tolerant of resumes, wakes, and disconnects. The repeater is in non-repeating mode during wake and resume, and even if the repeater uses repeating mode for some reason in the transition from wake or resume to L0, resume still has an EOP signal at the end. So, any possible stuck condition would probably correct itself due to the nature of the end of resume signaling. In a similar way the lockup detection circuit is tolerant of Control Messages and RAP and is configured to support LS Keep Alive message.

The lockup detection circuit takes bit stuffing into account. With bit stuffing, static data is sent for up to 6 bit times. The 7th bit should always be a different bit. In FS mode bit stuff errors may be forced in some circumstances. As an example, 7 binary “1” bits may be sent in a row with no line state change for 7 bits without bit stuffing followed by an FS EOP. This looks to the logic like 7 bit times of static data. Accordingly, the counter464of the lockup detection circuit may be configured to consider at least 8 bits of static data before declaring an error condition.

The lockup detection circuit also takes into account that Low Speed packets may occur even during Full Speed mode. This occurs when there is a low Speed device beneath a Full Speed hub. In this case the Full Speed hub passes the Low Speed packets to and from its Full Speed USB bus with Low Speed timing but with Full Speed polarity and Full Speed drivers.

FIG.6is a block diagram of a repeater for use in converting differential signaling on a USB bus to single-ended signaling on an eUSB bus. The repeater600may be used with the lockup detection circuit410described above and provides an example of how a force reset signal may be used to reset a repeater. The lockup detection circuit410may alternatively be used with a variety of other repeater configurations. The illustrated repeater600is provided as one of many possible examples. The illustrated configuration of the repeater600is for Full Speed mode on eUSB and USB. For Low Speed mode, the data and control lines are reversed. An fs_ls_mode signal from high level logic608may be used to cause the repeater to reverse the data and control lines and make any other suitable configuration changes. The mode may be determined in an initial setup or configuration operation. The repeater600has USB to eUSB logic614with an analog USB receiver602with a D+ input port603and a D− input port605. Power and other signals of the USB bus are routed to other parts of the system. The USB to eUSB logic614has an analog eUSB transmitter604with an eD+ output port607and an eD− output port609for eUSB signaling. Digital logic606of the USB to eUSB logic614connects the analog USB receiver602to the analog eUSB transmitter604.

The digital logic606is coupled to high level logic608. The high level logic608may include logic to handle non-repeating mode operations such as clock/reset generation, Host state machine (SM), Device SM, control message handling and register access protocol (RAP) reception. The control functions may include circuit startup, connection, suspend, resume, wake, bus reset, port reset detection, etc.

The digital logic606is also coupled to eUSB to USB logic610for processing eUSB to USB packets. The eUSB to USB logic610performs a similar function as the USB to eUSB logic614. In the case of Full Speed and Low Speed modes, those functions include an analog USB receiver, digital logic, and an analog eUSB transmitter operating in the opposite direction and translating data signals from eUSB to USB. There are two signals coupled with this logic, a driving_eusb_bus signal and a driving_usb_bus signal. The driving_eusb_bus signal is an indication from the USB to eUSB logic that it is processing a packet from the USB bus and passing it to the eUSB bus. When this is true, this causes the eUSB to USB logic610to ignore the activity it sees on the eUSB bus. The driving_usb_bus signal is an indication to the USB to eUSB logic614, in particular the digital logic606, that a packet is being passed from the eUSB bus to the USB bus and so the USB to eUSB logic614should not act on USB bus activity.

A lockup detection circuit650is also coupled to the digital logic606of the USB to eUSB logic614and to the eUSB to USB logic610. The lockup detection circuit612detects when a failure has occurred and generates a force_reset signal to the logic core620of the digital logic606. The force_reset signal causes a reset as described in more detail below. The reset allows the USB to eUSB logic614and the eUSB to USB logic610to come out of the lockup condition to start repeating data packets again. In one example, the force_reset signal causes flip-flops associated with maintaining states on the data and control lines to be reset. This causes the repeater to tristate the eUSB and USB data lines.

The analog USB receiver602converts the differential USB Full Speed mode signaling and Low Speed mode signaling into eUSB signaling for application to the digital logic606. The analog USB receiver602has a D+ output driver622that is coupled to the D+ input port603and a D− output driver624that is coupled to the D− input port605. The D+ output driver622and the D− output driver624are connected to the digital logic of the logic core620. The D+ output driver622generates a dp (D positive) signal labeled as the ana_usb_rx_dp signal and the D-output driver624generates a dm (D minus) signal labeled as the ana_usb_rx_dm signal. In addition, the receiver output drivers convert the voltage of the USB data signal to a lower voltage for the eUSB data signal.

Typically, in use the eUSB input, the ana_usb_rx_rcv signal, is high whenever D+ at the D+ input port603is greater than or equal to D− at the D− input port605. For Full Speed mode, this means that a J condition (D+ high, D− low) results in the output of the analog USB receiver as “1” and that a K condition (D− high, D+ low) results in the output being “0.” For Low Speed mode this means that a J condition (D− high, D+ low) results in the output of the analog USB receiver being “0” and that a K condition (D+ high, D− low) results in the output being “1.” A USB receiver626receives the USB input signals from the D+ port603and inverted from the D− port605and an enable signal, the ana_usb_rx_rcv_en signal, from the high level logic608. The USB receiver626then generates an eUSB data signal, the ana_usb_rx_rcv signal, that is connected to the logic core620. The analog USB receiver602also maintains its previous state in the event an SE0 is present on the USB bus.

The digital logic606includes a logic core620that receives the output signals from the analog USB receiver602. These signals are the ana_usb_rx_dp signal, the ana_usb_rx_dm signal, and the ana_usb_rx_rcv signal. Using these output signals as input signals to the logic core620, the logic core620generates an eUSB Control Line output signal, an eUSB Data Line output signal and enable signals for each output, an eUSB Control Line Enable signal, and an eUSB Data Line Enable signal. For Full Speed mode, the eUSB Control Line output signal is coupled to an eD+ output driver634of the analog eUSB transmitter604that drives the eD+ signal at the eD+ output port607. The eUSB data line output is coupled to an eD− output driver636of the analog eUSB transmitter604that drives the eD− signal at the eD− output port609. For Low Speed mode, the polarity is reversed. The output drivers convert the voltage of the eUSB data line to the higher voltage or the lower voltage for the eUSB, if necessary.

When the repeater600stops driving either eD+ or eD−, it first drives the respective line low for 20-70 ns before releasing it. In some embodiments, a delay cell630is used which transmits the eUSB Control Line Enable signal when it occurs and continues until the end of a delayed interval, for example for 20-70 ns. The delay cell630output is coupled to the eD+ output driver634so that the eD+ output driver634is enabled as long as the delay cell630is high. When enabled, the eD+ output driver634drives the eD+ output port607with the eUSB Control Line signal.

A second delay cell632is coupled to the eUSB Data Line Enable signal in the same or a similar way so that the delay cell632transmits the eUSB Control Line Enable signal when it occurs and continues until the end of the delay, for example for 20-70 ns. The second delay cell632output is coupled to the eD− output driver636so that the eD− output driver636is enabled as long as the second delay cell632is high. When enabled, the eD− output driver636drives the eD− output port609with the eUSB Data Line signal.

The digital logic606also connects the eUSB Control Line Enable signal to an inverter640and a switched pulldown resistor642. The switched pulldown resistor642is coupled to the eD+ output port607when the eUSB Control Line Enable signal is low to pull down the eD+ output port when there are no Control signals being driven by the eUSB repeater on the Control Line Enable. Similarly, the eUSB Data Line Enable signal is connected to an inverter644and a switched pulldown resistor646. The switched pulldown resistor646is coupled to the eD− output port609to pull down the eD− output port when the eUSB Data Line enable signal is low which is when there are no data signals being driven by the eUSB repeater on the eUSB Data Line. The enable signals for the eUSB pulldown resistors642,646on the eD+ and eD− lines are labeled as the ana_eusb_dp_pdn_en signal and the ana_eusb_dm_pdn_en signal, respectively.

The digital logic606also connects the eUSB Control Line Enable signal and the eUSB Data Line Enable signal as inputs to a logic gate652, for example an OR gate. The OR gate652output indicates whether either signal is high and this output is provided to the eUSB to USB logic610. This provides an indication that the repeater600is currently passing an incoming USB packet to eUSB.

FIG.7is a block diagram of a logic core702suitable for use as the logic core620of the repeater600for Full Speed (FS) mode. As described above, the eUSB Data Line carries the single-ended translation of the data from the analog USB receiver602that provides the ana_usb_rx_rcv signal for data detection from the analog USB receiver602to the analog eUSB transmitter604. The analog USB receiver also provides the ana_usb_rx_dp signal and the ana_usb_rx_dm signal for detection of EOP. During Full Speed mode, the data is received in inverted form. A USB “J” comes in as a “1” and so the signal is inverted to translate to the eUSB bus. When a Full Speed USB packet starts, the USB bus will go from Idle J to data K. The data from the USB receiver626, the ana_usb_rx_rcv signal is inverted during Full Speed mode at an inverter732. For Low Speed mode another inverter720is coupled to a logic gate, for example an AND gate722.

The inverter732output, the usb_rx_data_not signal, is also connected to an enable flip-flop728. The enable flip-flop is part of an enable control circuit724that includes the enable flip-flop728and a reset gate726that is coupled to the reset port of the enable flip-flop728and determines when to reset the enable flip-flop728. At the start of a Full Speed packet the inverter732causes a “0” to “1” transition on the clock input to the enable flip-flop728. The enable flip-flop728is a rising edge flip-flop and generates an output signal, labeled the eusb_rep_txdm_enable signal. This output signal is set until an SE0 (single-ended zero) condition that occurs at the EOP.

The enable flip-flop output, the eusb_rep_txdm_enable signal, causes the eUSB data line to be enabled. The enable flip-flop728output causes the eUSB data line to be enabled at the output driver636shown inFIG.6to start driving packet data onto the eUSB bus. The eUSB Data Line determines the data that is driven onto the eUSB bus. The eUSB Data Line is driven by a path that starts from the ana_usb_rx_rcv signal output of the analog USB receiver602, through a delay cell734, the inverter732and the AND gate722. The delay cell734delays the eUSB data signal based on a delay applied in the input filter circuit712that is after an SE0 condition of the Full Speed packet ends on the USB data signal.

As shown inFIG.3, at the end of a packet, the EOP signaling includes the USB bus transitioning from data to a prolonged SE0 (with a duration of at least 1 UI) followed by a J condition. Upon detection of a valid SE0 the repeater600will stop driving the eUSB Data Line and drive the eUSB Control Line high.

A filtered SE0 indication, the usb_rx_se0 signal, from an input filter circuit712is applied through an AND gate that forms the reset gate726of the enable control circuit724to generate a reset signal, the rst_eusb_rep_tx_en_n signal, that is coupled to the enable flip-flop728and resets the enable flip-flop728. The enable flip-flop728generates a reset eusb_rep_txdm_enable signal to disable the eUSB output driver636. When this occurs, the eusb_rep_txdm_enable signal is then deasserted causing the eUSB data driver to be disabled.

The lockup detection circuit650detects when something has gone wrong. Any of the failures discussed above may be detected. As an example, the repeater600may be driving the eUSB bus with USB2 data but yet the USB2 input has not changed in a while. This indicates a stuck condition which could have occurred due to noise on the USB2 bus, an aborted packet on the eUSB bus, etc. The lockup detection circuit612detects this and allows the repeater600to recover by first generating a force_reset signal to the reset gate726of the enable control circuit724. The force_reset signal is able to cause a reset of the enable flip-flop728.

The eUSB to USB logic610determines, as a part of its operation, whether there is an SE1 (Single-Ended One) condition present on the eUSB bus. When that occurs, it generates a reset signal, labeled as the eUSB_rxse1_extended signal, to the enable control circuit724. The SE1 condition occurs when an incoming USB packet is being passed to the eUSB bus at the same time that the eUSB host or device is trying to generate a Port Reset or a Control Message. Setting the eusb_rxse1_extended signal resets the enable flip-flop728and disables the eUSB Data Line to prevent the error. The eUSB to USB logic610may also generate a driving_usb_bus signal that is also coupled to the reset gate726. The driving_usb_bus signal provides an indication that other circuitry is currently passing an incoming eUSB packet to the USB bus.

The high level logic608may also generate a rst_usb_2_eusb signal to reset the enable flip-flop728. This is a general reset signal for the USB to eUSB logic and could be part of the normal power on operation or for some other reason. The high level logic608may also generate a rst_eusb_2_usb signal (not shown) to reset a similar flip-flop in the eUSB to USB logic610.

The output of the reset gate726is labeled as the rst_eusb_rep_tx_en_n signal. This is the reset for the enable flip-flop728. It will be asserted low at the end of a packet by the filtered SE0 indication. It will also be asserted low for any error detection detected by four other inputs to the reset gate726. As explained above these include a force_reset signal, any eUSB SE1 conditions due to possible port reset or control messages as indicated by the eusb_rxse1_extended signal, any reset from the high level logic608possibly including power on reset, resets during control message reception, resets during non-repeating modes, etc., and any time the design is passing an eUSB packet to the USB bus.

Returning to the input filter circuit712, the output filtered SE0 indication signal, the usb_rx_se0 signal, is also applied through an inverter720to AND gate722that is coupled to the eUSB Data Line. The output of the AND gate722is the eUSB Data Line. The outgoing eUSB data is the other input to the AND gate722so that the eUSB Data Line is forced low. The eUSB Data Line is forced low because the actual eUSB data driver will be kept enabled for 20-70 ns to drive the line low before releasing it. The filtered SE0 indication signal, the usb_rx_se0 signal, also enables the eUSB Control Line via a complex gate744in the logic core702that is coupled to the eUSB Control Line Enable. The eUSB Control Line driver data output is driven high upon the filtered SE0 indication using a “long” version of the SE0 status.

The end of USB packet's end of packet (EOP) signaling may be detected when the USB bus goes from the EOP's SE0 state to the J state. Upon detecting the end of the EOP, the repeater600stops driving the eUSB control line. The eUSB Control Line may be released after the SE0 condition ends. In some embodiments this is done using the eUSB Control Line Enable signal and the eUSB Control Line value. The eUSB Control Line Enable line will stop being driven after a time duration TSE0_Filtafter the end of the SE0 condition by use of the complex gate744. The eUSB Control Line value will be held high during SE0 on the eUSB Control Line and will go low after a time duration TSE0_Filtafter the end of the SE0 condition by use of an OR gate718that is connected between the input filter circuit712and the eUSB Data Line.

The first AND gate714of the input filter circuit712is used to detect an unfiltered SE0 condition. The two single-ended input lines from the USB receiver, the ana_usb_rx_dp signal and the ana_usb_rx_dm signal are coupled as inverted signals to the first AND gate714. A driving_usb_bus signal from the eUSB to USB logic610is also coupled to the first AND gate714. The driving_usb_bus signal provides an indication to the first AND gate714that other circuitry is currently passing an incoming eUSB packet to the USB bus. When this signal is low, it indicates that an eUSB repeater side of the repeater600is not in the process of passing a packet from an eUSB bus to the USB bus as indicated by the driving_usb_bus signal. When this signal is low and the eUSB input lines are low, then the AND condition is satisfied and the first AND gate714output goes high. This indicates an SE0 condition is present on the USB bus for an incoming packet.

This output is applied to a first input of a second AND gate716of the input filter circuit712. The second input of the second AND gate is an analog delay cell713. The second AND gate goes high when the first AND gate is high and the delay has been reached. This output is a signal labeled the usb_rx_se0 signal. The analog delay cell713may be set to 14 ns or more to allow filtering of the false SE0 conditions. This delay is the value TSE0_Filtreferred to herein. The second AND gate716simply ANDs the unfiltered SE0 indication from the first AND gate714with the delayed version from the delay cell713. This produces the usb_rx_se0 signal, which is the filtered SE0. It will be asserted after a delay time TSE0_Filtafter the valid SE0 condition and de-asserted as soon as the SE0 condition ends. This means that it will shorten the actual SE0 condition.

The delay cell713of the input filter circuit712that generates the usb_rx_rcv_delayed signal may be configured to match the SE0 filtering delay or any other suitable criterion. In one embodiment, the SE0 filtering delay is selected as 20 ns, the data delay is 10 ns, and the actual delay of the usb_rx_rcv_delayed signal is therefore 10 ns, although different amounts may be used.

The missing time caused by shortening the actual SE0 condition is recovered by using the output of the delay cell713as a signal for the simple delayed version of SE0 labeled the usb_rx_se0_delayed signal to extend the time that the eUSB control line is enabled. The filtered SE0 indication, the usb_rx_se0 signal, also enables the eUSB Control Line via a complex gate744in the logic core702. The eUSB Control Line Enable is the output of the complex gate744.

The complex gate744has an output from an OR gate746that is coupled to a three-terminal AND gate748. The OR gate746inputs are coupled to the usb_rx_se0 signal and to the output of the three-terminal AND gate748. The output of the complex gate744is high when either the usb_rx_se0 signal is high or when the three-terminal AND gate748is high. The three-terminal AND gate746has a first input coupled to the usb_rx_se0_delayed signal from the delay cell713, a second input coupled to a usb_rx_deassertion_delayed signal described below, and a third input coupled to the inverse of the eusb_rep_txdm_enable signal described above which is the eUSB Data Line Enable. When the first two are high and the eUSB Data Line Enable is low then the eUSB Control Line Enable is extended beyond the time of the usb_rx_se0 signal. This provides the “long” version of the SE0 status.

Even though the logic core702stops driving the eUSB data for a time duration, TSE0_Filt, after the SE0 for the EOP starts, and even though the logic core702stops driving the eUSB control line after the time duration, TSE0_Filt, after the SE0 condition ends, the delay cells630,632for the eUSB Data Line Enable and the eUSB Control Line Enable hold the lines enabled for a little longer. The delay time indicated as TSE0_Filtis the delay applied to the usb_rx_se0 signal from the input filter circuit712, which is the filtered SE0. The usb_rx_se0 signal is asserted at a time equal to this delay time after the valid SE0 condition and the usb_rx_se0 signal is de-asserted as soon as the SE0 condition ends. The delay cells630,632balance out the delay caused in the input data at the delay cell734applied to the input data, the ana_usb_rx_rcv signal.

The usb_rx_se0_deassertion_delayed signal is generated in a set of three back-to-back flip-flops740. This usb_rx_se0_deassertion_delayed signal is only asserted for a valid SE0 from an incoming USB packet's EOP. It is de-asserted some amount of time after the SE0 condition has gone away. It may be held longer than the value TSE0_Filtto ensure that the eUSB Control Line is asserted long enough after the EOP.

FIG.8is a block diagram of a logic core802suitable for use as the logic core620of the repeater600for Low Speed (LS) mode on the differential USB bus. The logic core802includes an input filter circuit812, an enable control circuit824, an AND gate822at the eUSB Data Line, and a complex gate844. These components have the same structure and operation as described above with respect to the logic core702for FS mode. The logic core802for LS mode also receives the same control and reset messages from the high level logic608, the eUSB to USB logic610and the lockup detection circuit612. These messages operate in the same way as described above.

The logic core802is coupled to and receives data from the USB receiver626of the analog USB receiver602and is coupled to and sends data to the analog eUSB transmitter604. As described above, the eUSB Data Line carries the eUSB translation of the data from the USB receiver626. The analog USB receiver602also provides the ana_usb_rx_dp signal and the ana_usb_rx_dm signal for detection of EOP. In contrast to Full Speed mode, in Low Speed mode, the eUSB control line is eD− and the eUSB data line is eD+. During Full Speed mode, the data is received in inverted form but during Low Speed mode, the data is not inverted. A USB “K” comes in as a “1.” When a Low Speed USB packet starts, the USB bus will go from Idle K to data J. The data from the analog USB receiver602is inverted also during Low Speed mode at an inverter832. The inverter832is coupled through another inverter821to an AND gate822. The AND gate822output produces the non-inverted eUSB Data Line as described above with respect toFIG.4.

The start of a packet in LS is a “0” to “1” transition on the output of the analog USB receiver602. Because this goes through the inverter832, it becomes a “1” to “O” transition. The usb_rx_data_not signal from the inverter832is provided to the AND gate822and also to the enable flip-flop828of the enable control circuit824. However, in contrast to the rising edge enable flip-flop728ofFIG.7, the enable flip-flop828for LS mode is configured to trigger on the falling edge. This may be the same flip-flop as is used for the FS logic core702that is configured to operate in different modes or a different flip-flop that is switched in to change USB modes.

In the logic core802, the SE0 filtering is larger for LS mode because the possible SE0 that may be seen during data transitions is as long as 210 ns as defined by the USB specification. The recommended filter delay is about 250 ns. Over process, voltage, and temperature (PVT) variations this will be greater than 210 ns as long as the delay elements are fabricated to an accuracy of within a +/−15% variation. The maximum delay requirement from the USB specification indicates that the maximum delay through a hub should be less than 300 ns during LS mode. The SE0 filtering is performed within the input filter circuit812that has a delay element813. This delay element generates the usb_rx_se0_delayed signal that is used to extend the usb_rx_se0 signal. As described above the usb_rx_se0 signal is connected as an input to the enable control circuit824, the complex gate844, and the AND gate822at the eUSB Data Line. The usb_rx_se0_delayed signal is a part of the input filter circuit and is connected as an input to the eUSB Control Line, the complex gate844, and the set of three flip-flops840that generate the usb_rx_se0_deassertion_delayed signal.

The data delay may be adjusted to match the SE0 filter delay of as described above for FS mode using about 10 ns for the delay labeled as TSE0_Filt. For LS mode, the filter mode is configured to accommodate the SE0 delay of about 250 ns. Using the 10 ns difference described above the SE0 filter delay would be about 240 ns. Different values may be selected to meet different circumstances. This delay is implemented using a delay cell834between the input signal the ana_usb_rx_rcv signal and the inverter832at the data input that generates the signal the usb_rx_data_not signal. The output of the delay cell834is a signal labeled as the usb_rxrcv_delayed signal.

As in the example ofFIG.7, the lockup detection circuit612is coupled to the eUSB to USB logic610and to the logic core802of the USB to eUSB logic614. As described above with reference toFIG.4andFIG.5, the lockup detection circuit612detects activity on the USB and eUSB busses and generates one or more force_reset signals which are then coupled to the eUSB to USB logic610and to the USB to eUSB logic614as a single signal or two different and unique signals. The force_reset signal is coupled through an OR gate as an input to a reset input of the enable flip-flop828of the enable control circuit824. This allows the lockup detection circuit to reset the data line enable signal. This causes the repeater to tristate the data and control lines.

While the lockup detection circuit650has only been shown having a connection to the USB to eUSB logic614and only in LS mode and FS mode. A similar connection may be made to reset flip-flops of the eUSB to USB logic610and to operate in other modes including High-Speed (HS) mode. The force_reset signal may be coupled to more or different circuits in a repeater to accommodate different repeater configurations.

FIG.9is a process flow diagram of the operation of a lockup detection circuit in a USB to eUSB or eUSB to USB repeater having a simple physical structure as shown and described above. In particular the method may be performed to reset a USB to eUSB signal repeater and a eUSB to USB signal repeater in the event of a lockup. The lockup detection circuit may be reset when either the USB or eUSB bus is active. From a reset, the process begins at902with detecting received data at an analog receiver of the USB repeater.

At904the process continues with detecting an enable signal for an analog transmitter of the USB repeater.

At906the process continues with detecting an idle condition of the analog receiver after detecting the enable signal. In some embodiments, detecting the idle condition includes detecting that two input lines to the analog receiver are both low. In some embodiments, detecting the idle condition includes detecting that one input line is high and one input line is low. In some embodiments, the process includes determining a speed mode of the repeater and adjusting the detecting the idle condition based on the speed mode.

At908the process continues with setting a timer for an appropriate duration. The timer duration is longer than any normal messaging that is expected for the particular protocol, but otherwise as short as possible. With USB 10 Low Speed UI or more is suitable. The timer may be set before or after the idle condition is detected. The running of the timer does not start until after the idle condition is detected.

At910the process includes determining that the timer has elapsed. In the event that the idle condition does not last until the timer elapses, then the process returns to the beginning and there is no reset at912. In common circumstances, the lockup condition circuit detects that the analog receiver is receiving an eUSB SE0 idle signal or USB idle signal.

At912the process ends with resetting the USB repeater after the timer has elapsed while an idle condition is detected and the enable signal is detected. The process may also include resetting the timer so that the lockup detection circuit is ready to repeat the process.

In the following description and claims, the term “coupled” along with its derivatives, may be used. “Coupled” is used to indicate that two or more elements have a connection that permits interaction but that there may be intervening physical or electrical components between them. “Electrically coupled” is used to indicate that the interaction is electrical as compared to physical, magnetic, or another form of interaction. As used in the claims, unless otherwise specified, the use of the ordinal adjectives “first,” “second,” “third,” etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.