Patent ID: 12211878

DESCRIPTION OF EMBODIMENTS

First Embodiment

FIG.1is a cross-sectional view schematically illustrating a configuration of an image-capturing apparatus including an image sensor according to a first embodiment. The image-capturing apparatus1includes an image-capturing optical system2, an image sensor3, a control unit4, a lens driving unit5, and a display unit6.

The image-capturing optical system2forms an object image on an image-capturing plane of the image sensor3. The image-capturing optical system2includes a lens2a, a focusing lens2b, and a lens2c. The focusing lens2bis a lens for adjusting a focal point of the image-capturing optical system2. The focusing lens2bcan be driven in an optical axis O direction.

The lens driving unit5has an actuator (not shown). Using the actuator, the lens driving unit5drives the focusing lens2bin the optical axis O direction by a desired amount. The image sensor3captures the object image to output an image signal. The control unit4controls the image sensor3and other components. The control unit4performs image processing or other processing on an image signal outputted by the image sensor3, and then records the processed image signal in a recording medium (not shown) or displays an image on the display unit6. The display unit6is a display device having a display member such as a liquid crystal panel.

FIG.2is a cross-sectional view of the image sensor3.FIG.2illustrates only a part of the entire image sensor3in cross section. The image sensor3is a so-called backside illumination image sensor. The image sensor3photoelectrically converts incident light that is incident from above in the figure. The image sensor3includes a first semiconductor substrate7and a second semiconductor substrate8.

The first semiconductor substrate7includes at least a PD layer71and a wiring layer72. The PD layer71is arranged on a back surface side of the wiring layer72. A plurality of photodiodes31, which are pinned (embedded) photodiodes, are two-dimensionally arranged in the PD layer71. A surface of the PD layer71on the wiring layer72side (i.e., a surface opposite to the incident light side) therefore has a conductivity type opposite to that of the PD layer71. For example, if the PD layer71is an N-type semiconductor layer, a P-type semiconductor layer having a high concentration and a small thickness is arranged on the surface of the PD layer71on the wiring layer72side. A ground voltage (GND) is applied to the first semiconductor substrate7as a substrate voltage. The second semiconductor substrate8has a variety of circuits arranged thereon at least for reading signals from the photodiode31. Specifically, a part of a pixel driving unit307described later (i.e., a transfer signal supply unit307aand a second reset signal supply unit307cthat handle negative voltage) is arranged in the second semiconductor substrate8. A voltage VTxL (described later) is applied to the second semiconductor substrate8as a substrate voltage.

A plurality of color filters73, each corresponding to its individual photodiode among a plurality of the photodiodes31, are provided on the incident light side of the PD layer71. Different types of color filters73are available, which transmit different wavelength ranges corresponding to red (R), green (G), and blue (B), for example. Three types of color filters73corresponding to red (R), green (G), and blue (B), for example, are here arranged in a Bayer array.

A plurality of microlenses74, each corresponding to its individual color filter among a plurality of the color filters73, are provided on the incident light side of the color filter73. The microlens74converges the incident light toward the corresponding photodiode31. After having passed through the microlens74, the incident light is filtered by the color filter73to transmit only a part of the wavelength range of the incident light. The filtered light is then incident on the photodiode31. The photodiode31photoelectrically converts the incident light to generate an electric charge.

A plurality of bumps75are arranged on a surface of the wiring layer72. A plurality of bumps76corresponding to a plurality of the bumps75are arranged on a surface of the second semiconductor substrate8opposing to the wiring layer72. A plurality of the bumps75and a plurality of the bumps76are bonded together. The first semiconductor substrate7and the second semiconductor substrate8are electrically connected via a plurality of the bumps75and a plurality of the bumps76.

The image sensor3has a plurality of pixels30. Details thereof will be described later. One pixel30includes a first pixel30xprovided in the first semiconductor substrate7and a second pixel30yprovided in the second semiconductor substrate8. One first pixel30xincludes one microlens74, one color filter73, one photodiode31, and other components. The first pixel30xadditionally includes a variety of circuits (described later) provided in the first semiconductor substrate7. The second pixel30yincludes a variety of circuits (described later) provided in the second semiconductor substrate8.

FIG.3is a block diagram schematically illustrating a configuration of the pixel30. The pixel30includes an analog circuit unit301, an A/D conversion unit302, a sampling unit303, a pixel value saving unit304, a pixel driving unit307, an individual pixel control unit306, and a calculation unit305.

The analog circuit unit301photoelectrically converts incident light to output the resulting signal as an analog signal to the A/D conversion unit302. The A/D conversion unit302samples the analog signal outputted by the analog circuit unit301to output a digital signal multiplied by a predetermined gain. The A/D conversion unit302repeatedly samples a pixel reset signal and a pixel signal and individually outputs a sampling result of the pixel reset signal and a sampling result of the pixel signal as digital signals.

The sampling unit303calculates and saves an integral value of the sampling result of the pixel reset signal and the sampling result of the pixel signal. The sampling unit303includes a first adder308and a first memory309for the pixel reset signal, and a second adder310and a second memory311for the pixel signal.

The sampling unit303adds the sampling result of the pixel reset signal outputted by the A/D conversion unit302and the integral value of previous sampling results saved in the first memory309, by means of the first adder308. The sampling unit303stores the resulting sum in the first memory309. The sampling unit303updates the value stored in the first memory309every time a sampling result of the pixel reset signal is outputted by the A/D conversion unit302.

The sampling unit303adds the sampling result of the pixel signal outputted by the A/D conversion unit302and the integral value of previous sampling results saved in the second memory311, by means of the second adder310. The sampling unit303stores the resulting sum in the second memory311. The sampling unit303updates the value stored in the second memory311every time a sampling result of the pixel signal is outputted by the A/D conversion unit302.

In this way, the A/D conversion unit302repeatedly samples the pixel reset signal and the pixel signal and the sampling unit303executes a process of integrating the sampling results. This process is a process known as a correlated multiple sampling.

Once a predetermined number of samplings, which has been determined by the individual pixel control unit306, has been completed, the sampling unit303outputs a digital value to the pixel value saving unit304, the digital value being based on the value stored in the first memory309and the value stored in the second memory311. The pixel value saving unit304stores the digital value as a photoelectric conversion result in the pixel30. The pixel value saving unit304is connected to a signal line340. The digital value stored in the pixel value saving unit304is externally readable via the signal line340.

The calculation unit305calculates the number of repetitions, an exposure time, a gain, and other parameters in the correlated multiple sampling process, based on an externally determined exposure time and the last photoelectric conversion result saved in the pixel value saving unit304. The individual pixel control unit306outputs the number of repetitions and the gain calculated by the calculation unit305to the A/D conversion unit302. The individual pixel control unit306outputs the exposure time and the gain calculated by the calculation unit305to the pixel driving unit307. The pixel driving unit307outputs a variety of signals (described later) to the analog circuit unit301. The signals drive the elements of the analog circuit unit301.

FIG.4is a circuit diagram of the analog circuit unit301, the individual pixel control unit306, and the pixel driving unit307. For the sake of convenience,FIG.4illustrates only parts of the individual pixel control unit306and the pixel driving unit307. The parts of the individual pixel control unit306are denoted by reference numerals306a,306b, and so on and the parts of the pixel driving unit307are denoted by reference numerals307a,307b, and so on.

The analog circuit unit301includes a photodiode31, a transfer transistor Tx, a floating diffusion FD, a first reset transistor RST1, a second reset transistor RST2, an amplification transistor AMI, a selection transistor SEL, a capacitance expansion transistor FDS, and a capacitor C1.

The photodiode31is a photoelectric conversion unit that photoelectrically converts incident light to generate an amount of electric charge depending on a light amount of the incident light. The transfer transistor Tx is a transfer unit that transfers the electric charge generated by the photodiode31to the floating diffusion FD in response to a transfer signal supplied from a transfer signal supply unit307a(described later). The floating diffusion FD is an accumulation unit that accumulates the electric charge transferred by the transfer transistor Tx. The amplification transistor AMI outputs a signal depending on an amount of the electric charge accumulated in the floating diffusion FD. When the selection transistor SEL is on, the signal outputted by the amplification transistor AMI is inputted to the A/D conversion unit302.

The analog circuit unit301includes two reset transistors: a first reset transistor RST1and a second reset transistor RST2. When the floating diffusion FD is reset, the first reset transistor RST1is supplied with a first reset signal from a first reset signal supply unit307b(described later). The first reset signal supply unit307b(described later) supplies a signal representing the voltage VDD as the first reset signal. The first reset transistor RST1resets the floating diffusion FD in response to the first reset signal. When the photodiode31is reset, the second reset transistor RST2is supplied with a second reset signal from a second reset signal supply unit307c(described later). The second reset signal supply unit307c(described later) supplies a signal representing the voltage VDD as the second reset signal. The second reset transistor RST2resets the photodiode31in response to the second reset signal.

The capacitance expansion transistor FDS switches a connection between the floating diffusion FD and the capacitor C1in response to a capacitance expansion signal supplied from a capacitance expansion signal supply unit307d(described later). For example, if an incident light amount to the photodiode31is large and the floating diffusion FD could be saturated, the capacitance expansion transistor FDS is turned on to connect the floating diffusion FD and the capacitor C1. This substantially increases the capacitance of the floating diffusion FD by an amount equal to the capacitance of the capacitor C1, which allows the floating diffusion FD to handle a larger light amount.

The first reset signal supply unit307bis a CMOS circuit including a pMOS transistor Tr7and an nMOS transistor Tr8. Based on an output signal of a first reset control unit306b, the first reset signal supply unit307bsupplies a gate of the first reset transistor RST1with either the voltage VDD or the voltage GND as the first reset signal. As described above, the first reset control unit306bis a part of the individual pixel control unit306and the first reset signal supply unit307bis a part of the pixel driving unit307. It should be noted that, for an overdrive, the first reset control unit306bsupplies the gate of the first reset transistor RST1with a voltage VRST1H higher than the voltage VDD, instead of the voltage VDD.

The capacity expansion signal supply unit307dis a CMOS circuit including a pMOS transistor Tr11and an nMOS transistor Tr12. Based on an output signal of a capacitance expansion control unit306d, the capacitance expansion signal supply unit307dsupplies a gate of the capacitance expansion transistor FDS with either the voltage VDD or the voltage GND as the capacitance expansion signal. As described above, the capacity expansion control unit306dis a part of the individual pixel control unit306and the capacity expansion signal supply unit307dis a part of the pixel driving unit307. It should be noted that, for an overdrive, the capacity expansion signal supply unit307dsupplies the gate of the capacity expansion transistor FDS with a voltage VFDSH higher than the voltage VDD, instead of the voltage VDD.

The transfer signal supply unit307aincludes an nMOS transistor Tr1, an nMOS transistor Tr2, a pMOS transistor Tr3, an nMOS transistor Tr4, an nMOS transistor Tr5, and a pMOS transistor Tr6.

The nMOS transistor Tr2and the pMOS transistor Tr3constitute a CMOS circuit. A predetermined power supply applies a voltage VTxH to a source of the pMOS transistor Tr3. A transfer control unit306asupplies gates of the nMOS transistor Tr2and the pMOS transistor Tr3with a transfer control signal. A source of the nMOS transistor Tr2is connected to a drain of the nMOS transistor Tr1. A predetermined power supply applies a voltage VTxL to a source of the nMOS transistor Tr1. The voltage VTxH is higher than the ground voltage that is the substrate voltage of the first semiconductor substrate7(i.e., the voltage VTxH is a positive voltage), while the voltage VTxL is lower than the ground voltage that is the substrate voltage of the first semiconductor substrate7(i.e., the voltage VTxL is a negative voltage).

The nMOS transistor Tr5and the pMOS transistor Tr6constitute a CMOS circuit. A predetermined power supply applies a voltage VTxH to a source of the pMOS transistor Tr6. The transfer control unit306asupplies gates of the nMOS transistor Tr5and the pMOS transistor Tr6with a signal having high and low levels that are inverted with respect to those of the transfer control signal. A source of the nMOS transistor Tr5is connected to a drain of the nMOS transistor Tr4. A predetermined power supply applies a voltage VTxL to a source of the nMOS transistor Tr4.

Agate of the nMOS transistor Tr4is connected to drains of the nMOS transistor Tr2and the pMOS transistor Tr3. A gate of the nMOS transistor Tr is connected to drains of the nMOS transistor Tr5and the pMOS transistor Tr6. The transfer transistor Tx is supplied with a voltage from the drains of the nMOS transistor Tr5and the pMOS transistor Tr6as the transfer signal.

In other words, the pMOS transistor Tr6functions as a first power supply unit that supplies the gate of the transfer transistor Tx with the voltage VTxH higher than the substrate voltage of the first semiconductor substrate7. The nMOS transistor Tr4and the nMOS transistor Tr5function as a second power supply unit that supplies the gate of the transfer transistor Tx with the voltage VTxL lower than the substrate voltage of the first semiconductor substrate7.

The transfer signal supply unit307aincludes not only the nMOS transistor Tr5and the pMOS transistor Tr6constituting the CMOS, but also the nMOS transistor Tr, the nMOS transistor Tr2, the pMOS transistor Tr3, and the nMOS transistor Tr4. The reason for this will be explained below.

The inverted transfer control signal supplied by the unit306ais a signal having a voltage VDD as its high level and a ground voltage GND as its low level. The nMOS transistor Tr5must be turned off when a low level signal (i.e., the ground voltage) is applied to the gate thereof.

Given a circuit with the nMOS transistor Tr4omitted and the voltage VTxL applied to the source of the nMOS transistor Tr5, the nMOS transistor Tr5is turned off when a gate-source voltage VGS is lower than a gate threshold voltage Vth. The gate-source voltage VGS becomes larger than zero by an amount equal to VTxL (VGS=0−VTxL) when the low level signal (i.e., the ground voltage) is applied to the gate of the nMOS transistor Tr5. In this circuit, the nMOS transistor Tr5is therefore not completely turned off for the gate threshold voltage Vth smaller than −VTxL, even if the gate of the nMOS transistor Tr5is supplied with the low level signal. This makes the circuit unstable. The circuit used in the present embodiment allows the nMOS transistor Tr4to shut off the supply of the voltage VTxL to the source of the nMOS transistor Tr5, even if the nMOS transistor Tr5is not completely turned off. The above-described problem concerning the gate threshold voltage Vth can thus be avoided. It should be noted that the nMOS transistor Tr, the nMOS transistor Tr2, the pMOS transistor Tr3, and the nMOS transistor Tr4may be omitted as long as the gate threshold voltage Vth of the nMOS transistor Tr5can be sufficiently increased.

The transfer signal supply unit307aconfigured in the above-described manner supplies the gate of the transfer transistor Tx with either the voltage VTxH or the voltage VTxL as the transfer signal, based on the output signal of the transfer control unit306a. As described above, the transfer control unit306ais a part of the individual pixel control unit306and the transfer signal supply unit307ais a part of the pixel driving unit307. It should be noted that the voltage VTxL lower than the substrate voltage of the first semiconductor substrate7is applied to the gate of the transfer transistor Tx in order to prevent the electric charge from being transferred from the photodiode31to the floating diffusion FD when the transfer transistor Tx is off.

The second reset signal supply unit307cincludes an nMOS transistor Tr21, an nMOS transistor Tr22, a pMOS transistor Tr23, an nMOS transistor Tr24, an nMOS transistor Tr25, and a pMOS transistor Tr26. Based on an output signal of a second reset control unit306c, the second reset signal supply unit307csupplies a gate of the second reset transistor RST2with either the voltage VTxH or the voltage VTxL as the second reset signal. The configuration of the second reset signal supply unit307cis the same as that of the transfer signal supply unit307aand the description thereof will thus be omitted. As described above, the second reset control unit306cis a part of the individual pixel control unit306and the second reset signal supply unit307cis a part of the pixel driving unit307.

FIG.5is a view schematically illustrating a well structure of the first semiconductor substrate7and the second semiconductor substrate8. Incident light is incident onto the first semiconductor substrate7from above in the figure. The first semiconductor substrate7is a P-type semiconductor substrate. The substrate voltage of the first semiconductor substrate7is set to the ground voltage GND. The second semiconductor substrate8is a P-type semiconductor substrate. The substrate voltage of the second semiconductor substrate8is set to a voltage corresponding to VTxL.

Among the units illustrated inFIG.4, the analog circuit unit301, the transfer control unit306a, the first reset control unit306b, and the first reset signal supply unit307bare arranged in the first semiconductor substrate7. Among the units illustrated inFIG.4, a transfer signal supply unit307ais arranged in the second semiconductor substrate8. Although not illustrated inFIG.5, other components are arranged in the first semiconductor substrate7.

FIG.6is a timing chart illustrating an image-capturing sequence using the image sensor3. The image sensor3can selectively perform multiple exposure and the correlated multiple sampling. First, a multiple exposure control will be described with reference toFIG.6(a).

FIG.6(a)is a timing chart in the multiple exposure for each pixel30. The horizontal axis inFIG.6(a)denotes time, and time proceeds to right. Rectangles marked as “Dark” inFIG.6(a)indicate timings at which the A/D conversion unit302samples the pixel reset signals. Rectangles marked as “Sig” inFIG.6(a)indicate timings at which the A/D conversion unit302samples the pixel signals. Rectangles marked as “Out” inFIG.6(a)indicate timings at which the pixel value saving unit304outputs the digital value (the photoelectric conversion result) stored therein to peripheral circuits via the signal line340. InFIG.6(a), in performing the multiple exposure, the pixels30are classified into four pixels30ato30ddepending on an amount of the incident light.

An operation of resetting the photodiode31and the floating diffusion FD at a start time t0of an exposure period T1is the same for all pixels30. In the pixel30athat receives an extremely small amount of incident light, the floating diffusion FD is then reset at a time t3to sample the pixel reset signal. The time t3is a time obtained by subtracting a time required for resetting the floating diffusion FD and sampling the pixel reset signal from an end time t4of the exposure period T1. At the end time t4of the exposure period T1, the electric charge that has been generated in a period from the time t0to the time t4and accumulated in the photodiode31is transferred to the floating diffusion FD to sample the pixel signal. Then, at a time t5, the photoelectric conversion result is stored in the pixel value saving unit304.

In the pixel30bthat receives a slightly small amount of incident light, the externally determined exposure period T1is equally divided into two periods T2and T3to perform the above-described operation twice. Specifically, at the times t1and t3, the floating diffusion FD is reset to sample the pixel reset signal. The time t1is a time obtained by subtracting a time required for resetting the floating diffusion FD and sampling the pixel reset signal from an end time t2of the period T2. Then, at the time t2, the electric charge accumulated in the photodiode31is transferred to the floating diffusion FD to sample the pixel signal. The operation during a period from the time3to the time t5is the same as in the case of the pixel30a.

In the pixel30cthat receives a slightly large amount of incident light, the externally determined exposure period T1is equally divided into four periods to perform the above-described operation four times. In the pixel30dthat receives an extremely large amount of incident light, the externally determined exposure period T1is equally divided into eight periods to perform the above-described operation eight times.

In this way, the multiple exposure control enables the exposure time to individually vary for the pixels30receiving a large amount of incident light and the pixels30receiving a small amount of incident light in order to capture an image. Subdividing the exposure time and repeating the image-capturing allow a dynamic range to be extended, even if the incident light amount is so large that the floating diffusion FD would be saturated in a common image-capturing.

Next, the correlated multiplex sampling control will be described with reference toFIG.6(b).FIG.6(b)is a timing chart in the correlation multiple sampling control for each pixel30. The horizontal axis inFIG.6(b)denotes time, and time proceeds to right. Rectangles marked as “Dark” inFIG.6(b)indicate timings at which the A/D conversion unit302samples the pixel reset signals. Rectangles marked as “Sig” inFIG.6(b)indicate timings at which the A/D conversion unit302samples the pixel signals. Rectangles marked as “Out” inFIG.6(b)indicate timings at which the A/D conversion unit302outputs the sampling results to the sampling unit303. InFIG.6(b), in performing the correlation multiple sampling, the pixels30are classified into four pixels30ato30ddepending on an amount of the incident light.

The pixel30ahas the longest exposure time and the pixel30dhas the shortest exposure time. In the correlated multiple sampling control, the floating diffusion FD is reset at an earlier time as the pixel30has a longer exposure time. It thus takes a longer time until the pixel signal is sampled after resetting the floating diffusion FD, as the pixel30has a longer exposure time. During that period, the pixel reset signal is repeatedly sampled.

For example, inFIG.6(b), the pixel30ahas the longest exposure time. The floating diffusion FD is reset at a time t7that is earlier than an end time t6of an exposure time T4of the pixel30aby a period T5. As a result, the pixel reset signal is sampled four times before the time t6. The pixel signal is then repeatedly sampled during a period from the end of the exposure time T4to the end of the next exposure time T6.

A long exposure time translates into a small amount of the incident light and thus a large influence of noises on the pixel signal caused by the amplification transistor AMI, the selection transistor SEL, and the A/D conversion unit302. In other words, the number of samplings of the pixel reset signal and the pixel signal to be performed is larger for the pixel30influenced to a greater extent by the noises described above, which enables a more sensitive image-capturing to be performed.

The image sensor3performs the above-described operations on all the pixels30in parallel. In other words, the pixels30perform in parallel the operations from the photoelectric conversion in the photodiode31to the storage of the digital value into the pixel value saving unit304. The image-capturing results are sequentially read out from the pixel value saving unit304from one pixel30to another.

In this way, the image sensor3in the present embodiment can control the exposure time for each pixel. In order to control the exposure time for each pixel, the timing of turning on and off the transfer transistor Tx must be controlled for each pixel. In other words, the voltage (in the present embodiment, the voltage VTxH and the voltage VTxL) to be supplied to the gate of the transfer transistor Tx must be controlled for each pixel. Accordingly, the first power supply unit for supplying the voltage VTxH and the second power supply unit for supplying the voltage VTxL must be provided for each pixel. Since the voltage handled by the first semiconductor substrate7is different from the voltage VTxH and the voltage VTxL, the first power source unit and the second power source unit would occupy a large area if they would be provided in the pixel30. The first power supply unit particularly requires a triple well structure to avoid a forward bias with respect to the substrate, since the first power supply unit handles the voltage VTxL lower than the substrate voltage. The first power supply unit therefore requires a particularly large area. As a result, an area occupied by the photodiode31in the pixel30would substantially be reduced. This causes a substantially reduced fill factor of the photodiode31, which can make miniaturization of the image sensor difficult. In the present embodiment, providing the first power supply unit and the second power supply unit in the second semiconductor substrate8allows the exposure time to be controlled for each pixel, without providing the first power supply unit and the second power supply unit in the vicinity of the photodiode31of the first semiconductor substrate7, i.e., without decreasing the fill factor of the photodiode31.

According to the above-described embodiment, the following operational advantages can be obtained.

(1) The first semiconductor substrate7is provided with the photodiode31that photoelectrically converts incident light and the transfer transistor Tx that transfers the electric charge generated by the photodiode31to the floating diffusion FD in response to the transfer signal. However, the transfer signal supply unit307athat supplies the gate electrode of the transfer transistor TX with the transfer signal is not arranged in the first semiconductor substrate7. The second semiconductor substrate8is provided with the transfer signal supply unit307athat supplies the gate of the transfer transistor Tx with either the voltage VTxL lower than the ground voltage or the voltage VTxH higher than the ground voltage as the transfer signal. This enables the transfer transistor Tx to be reliably turned off and thus prevents an increase in the dark current. Further, since no circuit handling a negative power supply is provided in the first semiconductor substrate7, there is no need to provide a diffusion layer or another layer that handles the negative power supply in the first semiconductor substrate7, which can improve the fill factor of the photodiode31. The same effect can be obtained also for the second reset transistor RST2.

(2) The first semiconductor substrate7includes a plurality of the photodiodes31, a plurality of the floating diffusions FD, and a plurality of the transfer transistors Tx. The second semiconductor substrate8includes a plurality of the transfer signal supply units307a. Some of a plurality of the transfer signal supply units307atransfer the electric charge generated by the photodiodes31during the first period to the floating diffusions FD. Others of the transfer signal supply units307atransfer the electric charge generated by the photodiodes31during the second period to the floating diffusions FD, the second period having a length different from that of the first period. This enables the exposure time to individually vary for different pixels30, which results in an extended dynamic range of the image sensor3.

(3) The image-capturing sequence is set so that the end time of the first period is the same as the end time of the second period. This can achieve a simple image-capturing control.

(4) While the substrate voltage of the first semiconductor substrate7is set to the ground voltage, the substrate voltage of the second semiconductor substrate8is set to a voltage corresponding to the voltage VTxL that is different from the ground voltage. In this way, a variation range of the signal voltage of the transfer signal supplied to the gate of the transfer transistor Tx can be set to a voltage that is different from the other drive signals, without any additional diffusion layers. The same effect can be obtained also for the second reset transistor RST2.

(5) The voltage VTxL, which is one of the voltages (i.e., the voltage VTxL and the voltage VTxH) of the transfer signal, is a voltage based on the substrate voltage of the second semiconductor substrate8. In this way, a variation range of the signal voltage of the transfer signal supplied to the gate of the transfer transistor Tx can be set to a voltage that is different from the other drive signals, without any additional diffusion layers. The same effect can be obtained also for the second reset transistor RST2.

(6) The first reset transistor RST1is provided in the first semiconductor substrate7to reset the electric charge accumulated in the floating diffusion FD in response to the first reset signal. The first reset signal supply unit307bis provided in the first semiconductor substrate7, instead of the second semiconductor substrate8, and supplies the first reset transistor RST1with either the ground voltage or the voltage VDD higher than the ground voltage as the first reset signal. In this way, the variation range of the signal voltage of the transfer signal includes an negative voltage, while the variation range of the signal voltage of the first reset signal may be a regular range including no negative voltage.

(7) The ground voltage, which is one of the voltages (i.e., the ground voltage and the voltage VDD) of the first reset signal, is a voltage based on the substrate voltage of the first semiconductor substrate7. This eliminates the need for an additional diffusion layer for providing the first reset signal supply unit307b.

(8) The A/D conversion unit302and the sampling unit303perform an analog/digital conversion on the analog signal based on the amount of the electric charge accumulated in the floating diffusion FD, by the correlated multiplex sampling process. In this way, the S/N ratio of the image-capturing signal is enhanced.

(9) The second reset transistor RST2is provided to reset the electric charge accumulated in the photodiode31. In this way, the exposure time can vary for different pixels30.

(10) The image sensor3includes a plurality of the pixels30each including the photodiode31, the floating diffusion FD, the transfer transistor Tx, and the transfer signal supply unit307a. Each of the transfer signal supply units307aincluded in some of a plurality of the pixels30supplies a transfer signal that transfers the electric charge generated by the photodiode31during the first period to the floating diffusion FD. Each of the transfer signal supply units307aincluded in others of a plurality of the pixels30supplies a transfer signal that transfers the electric charge generated by the photodiode31during the second period to the floating diffusion FD, the second period having a length different from that of the first period. This enables the exposure time to individually vary for different pixels30, which results in an extended dynamic range of the image sensor3.

In the first embodiment described above, the second semiconductor substrate8includes both a pMOS transistor Tr6(the first power supply unit) for supplying the voltage VTxH corresponding to the high level of the transfer signal, and an nMOS transistor Tr4and an nMOS transistor Tr5(the second power supply unit) for supplying the voltage VTxL corresponding to the low level of the transfer signal, as illustrated inFIG.5. However, only one of them may be provided in the second semiconductor substrate8and the other may be provided in the first semiconductor substrate7. In this case, it is preferable to provide the nMOS transistor Tr4and the nMOS transistor Tr5(the second power supply unit) having a larger area in the second semiconductor substrate8, and provide the pMOS transistor Tr6(the first power supply unit) having a smaller area in the first semiconductor substrate7.

FIG.10is a view illustrating an example in which the pMOS transistor Tr6(the first power supply unit) is provided in the first semiconductor substrate7. The example illustrated inFIG.10provides not only the pMOS transistor Tr6(the first power supply unit), but also the pMOS transistor Tr3in the first semiconductor substrate7. In the configuration illustrated inFIG.10, the circuit configuration and operation are the same as those in the first embodiment described above.

Second Embodiment

The image sensor3according to the first embodiment has the first semiconductor substrate7and the second semiconductor substrate8. An image sensor3according to a second embodiment further includes a third semiconductor substrate9. The following description describes the image sensor3according to the second embodiment and mainly differences from the image sensor3according to the first embodiment. The same components as those of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted herein.

FIG.7is a view schematically illustrating a well structure of the first semiconductor substrate7, the second semiconductor substrate8, and the third semiconductor substrate9. In the present embodiment, the first semiconductor substrate7is not provided with the first reset control unit306band the first reset signal supply unit307b. Instead, the third semiconductor substrate9is provided with the first reset control unit306band the first reset signal supply unit307b. The third semiconductor substrate9is a P-type semiconductor substrate having a substrate voltage that is set to the ground voltage.

According to the above embodiment, the following operational advantages can further be obtained, in addition to the operational advantages described in the first embodiment.

(11) The image sensor3further includes the third semiconductor substrate9having the same substrate voltage (the ground voltage) as that of the first semiconductor substrate7. The first reset signal supply unit307bis provided in the third semiconductor substrate9. In this way, the number of circuits occupying the first semiconductor substrate7is smaller than that in the first embodiment, so that the opening of the photodiode31can be increased. In other words, the light use efficiency of the photodiode31is further improved.

In the second embodiment described above, the second semiconductor substrate8includes both an nMOS transistor Tr6(the first power supply unit) for supplying the voltage VTxH corresponding to the high level of the transfer signal, and a pMOS transistor Tr4and a pMOS transistor Tr5(the second power supply unit) for supplying the voltage VTxL corresponding to the low level of the transfer signal, as illustrated inFIG.7. However, only one of them may be provided in the second semiconductor substrate8and the other may be provided in the first semiconductor substrate7. In this case, it is preferable to provide the pMOS transistor Tr4and the pMOS transistor Tr5(the second power supply unit) having a larger area in the second semiconductor substrate8, and provide the nMOS transistor Tr6(the first power supply unit) having a smaller area in the first semiconductor substrate7.

In the second embodiment described above, the pMOS transistor Tr1, the pMOS transistor Tr2, the nMOS transistor Tr3, the pMOS transistor Tr4, the pMOS transistor Tr5, and the nMOS transistor Tr6, which are included in the transfer signal supply unit307a, are all provided in the second semiconductor substrate8, as illustrated inFIG.7. Some of these transistors may be provided in the first semiconductor substrate7or the third semiconductor substrate9.

Third Embodiment

The image sensor3according to the first embodiment has the second semiconductor substrate8configured as a P-type semiconductor substrate. An image sensor3according to a third embodiment has a second semiconductor substrate8configured as an N-type semiconductor substrate. The following description describes the image sensor3according to the third embodiment and mainly differences from the image sensor3according to the first embodiment. The same components as those of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted herein.

FIG.8is a view schematically illustrating a well structure of the first semiconductor substrate7and the second semiconductor substrate8. The second semiconductor substrate8is an N-type semiconductor substrate having a substrate voltage that is set to a voltage corresponding to the voltage VDD. In the present embodiment, the first semiconductor substrate7is not provided with the transfer control unit306a, the first reset control unit306b, the transfer signal supply unit307a, and the first reset signal supply unit307b. Instead, the second semiconductor substrate8is provided with the transfer control unit306a, the first reset control unit306b, the transfer signal supply unit307a, and the first reset signal supply unit307b. Although not illustrated inFIG.8, it is desirable to also arrange other components of the individual pixel control unit306and the pixel driving unit307in the second semiconductor substrate8.

The transfer control unit306a, the first reset control unit306b, the transfer signal supply unit307a, and the first reset signal supply unit307bhave the same configuration as in the first embodiment, but the polarity of the diffusion layer is different from that in the first embodiment since the second semiconductor substrate8is an N-type semiconductor substrate. Accordingly, for the transistors constituting the components, the nMOS transistors in the first embodiment are replaced by pMOS transistors and the pMOS transistors in the first embodiment are replaced by nMOS transistors.

The transfer signal supply unit307ain the present embodiment supplies the gate of the transfer transistor Tx with either the voltage VDD or the voltage VTxL as the transfer signal, based on the output signal of the transfer control unit306a. Since the substrate voltage of the second semiconductor substrate8is a voltage corresponding to the voltage VDD, an increase in circuit scale (an addition of a further diffusion layer or the like) can be avoided by using the voltage VDD, instead of the voltage VTxH.

According to the above embodiment, the following operational advantages can further be obtained, in addition to the operational advantages described in the first embodiment.

(12) The second semiconductor substrate8is configured as an N-type semiconductor substrate and provided with the individual pixel control unit306and the pixel driving unit307. In this way, the number of circuits occupying the first semiconductor substrate7is smaller than that in the first or second embodiment, so that the opening of the photodiode31can be increased. In other words, the light use efficiency of the photodiode31is further improved. Further, unlike the second embodiment, no additional semiconductor substrate is required. A material cost can thus be reduced and an increase in thickness of the image sensor3can be minimized.

In the third embodiment described above, the second semiconductor substrate8includes both an nMOS transistor Tr6(the first power supply unit) for supplying the voltage VTxH corresponding to the high level of the transfer signal, and a pMOS transistor Tr4and a pMOS transistor Tr5(the second power supply unit) for supplying the voltage VTxL corresponding to the low level of the transfer signal, as illustrated inFIG.8. However, only one of them may be provided in the second semiconductor substrate8and the other may be provided in the first semiconductor substrate7. In this case, it is preferable to provide the pMOS transistor Tr4and the pMOS transistor Tr5(the second power supply unit) having a larger area in the second semiconductor substrate8, and provide the nMOS transistor Tr6(the first power supply unit) having a smaller area in the first semiconductor substrate7.

Fourth Embodiment

An image sensor3according to a fourth embodiment has an individual pixel control unit306and a pixel driving unit307provided in a second semiconductor substrate8, as is the image sensor3according to the third embodiment. However, the fourth embodiment is different from the third embodiment in that the second semiconductor substrate8is configured as a P-type semiconductor substrate. The following description describes the image sensor3according to the third embodiment and mainly differences from the image sensor3according to the first embodiment. The same components as those of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted herein.

FIG.9is a view schematically illustrating a well structure of the first semiconductor substrate7and the second semiconductor substrate8. The second semiconductor substrate8is a P-type semiconductor substrate and has a substrate voltage that is set to the ground voltage, as is the first semiconductor substrate7.

In the present embodiment, N-type diffusion layers81and82are provided in the second semiconductor substrate8for the purpose of providing the transfer signal supply unit307a, which handles the voltage VTxH and the voltage VTxL, in the second semiconductor substrate8. A transfer signal supply unit307ais arranged in the diffusion layers81and82, in which the nMOS transistors in the first embodiment are replaced by pMOS transistors and the pMOS transistor in the first embodiment are replaced by nMOS transistors as in the third embodiment. Since the N-type diffusion layers81and82electrically separate the transistors from the P-type substrate, the transfer signal supply unit307acan handle the voltage VTxH and the voltage VTxL.

According to the above embodiment, the following operational advantages can be obtained.

(13) The photodiode31photoelectrically converts incident light. The transfer transistor Tx transfers the electric charge as a result of the photoelectric conversion by the photodiode31to the floating diffusion FD in response to the transfer signal. The transfer signal supply unit307asupplies the gate of the transfer transistor Tx with the transfer signal. The first reset transistor RST1resets the electric charge accumulated in the floating diffusion FD in response to the first reset signal. The first reset signal supply unit307bsupplies the first reset transistor RST1with the reset signal. The photodiode31and the transfer transistor Tx are provided in the first semiconductor substrate7. The second semiconductor substrate8is provided with the first reset signal supply unit307barranged in the N-type diffusion layer and the transfer signal supply unit307aarranged in the P-type diffusion layer. In this way, the number of circuits occupying the first semiconductor substrate7is smaller than that in the first or second embodiment, so that the opening of the photodiode31can be increased as in the third embodiment. In other words, the light use efficiency of the photodiode31is further improved. Further, unlike the second embodiment, no additional semiconductor substrate is required. A material cost can thus be reduced and an increase in thickness of the image sensor3can be minimized.

In the first embodiment described above, the second semiconductor substrate8includes both an nMOS transistor Tr6(the first power supply unit) for supplying the voltage VTxH corresponding to the high level of the transfer signal, and a pMOS transistor Tr4and a pMOS transistor Tr5(the second power supply unit) for supplying the voltage VTxL corresponding to the low level of the transfer signal, as illustrated inFIG.9. However, only one of them may be provided in the second semiconductor substrate8and the other may be provided in the first semiconductor substrate7. In this case, it is preferable to provide the pMOS transistor Tr4and the pMOS transistor Tr5(the second power supply unit) having a larger area in the second semiconductor substrate8, and provide the nMOS transistor Tr6(the first power supply unit) having a smaller area in the first semiconductor substrate7.

FIG.11is a view illustrating an example in which the pMOS transistor Tr4and the pMOS transistor Tr5(second power supply unit) are provided in the first semiconductor substrate7. The example illustrated inFIG.11provides not only the pMOS transistor Tr4and the pMOS transistor Tr5(the second power supply unit), but also the pMOS transistor Tr1and the pMOS transistor Tr2in the first semiconductor substrate7. In the configuration illustrated inFIG.11, the circuit configuration and operation are the same as those in the fourth embodiment described above.

The following variations are also contemplated within the scope of the present invention, and one or more variations may be combined with the above embodiments.

First Variation

Circuits different from the circuits described in the above embodiments may be provided in the second semiconductor substrate8or the third semiconductor substrate9. For example, the circuits that are mounted in the first semiconductor substrate7in the above embodiments may be provided in the second semiconductor substrate8or the third semiconductor substrate9. This can form a larger space for the photodiode31to more efficiently capture light.

While various embodiments and variations have been described above, the present invention is not limited to these. Other embodiments contemplated within the technical idea of the present invention are also included within the scope of the present invention.

The above embodiments and variations also include the following image-capturing apparatus and electronic camera.

(1) An image sensor comprising: a first semiconductor substrate provided with a pixel, including a photoelectric conversion unit that photoelectrically converts incident light to generate an electric charge, an accumulation unit that accumulates the electric charge generated by the photoelectric conversion unit, and a transfer unit that transfers the electric charge generated by the photoelectric conversion unit to the accumulation unit; and a second semiconductor substrate provided with a supply unit for the pixel, the supply unit supplying the transfer unit with a transfer signal to transfer the electric charge from the photoelectric conversion unit to the accumulation unit.

(2) In the image sensor as described in (1), a first substrate voltage applied to the first semiconductor substrate and a second substrate voltage applied to the second semiconductor substrate are different from each other.

(3) In the image sensor as described in (2), the supply unit includes a first power supply unit and a second power supply unit; and at least one of the first power supply unit and the second power supply unit is provided in the second semiconductor substrate.

(4) In the image sensor as described in (3), the first power supply unit supplies a first voltage higher than the first substrate voltage; and the second power supply unit supplies a second voltage lower than the first substrate voltage.

(5) In the image sensor as described in (4), the transfer unit electrically connects the photoelectric conversion unit and the accumulation unit and transfers the electric charge generated by the photoelectric conversion unit to the accumulation unit; and the supply unit supplies the transfer unit with the transfer signal for electrically connecting or disconnecting the photoelectric conversion unit and the accumulation unit.

(6) In the image sensor as described in (5), the transfer unit electrically connects the photoelectric conversion unit and the accumulation unit if the first voltage is supplied as the transfer signal, and electrically disconnects the photoelectric conversion unit and the accumulation unit if the second voltage is supplied as the transfer signal.

(7) In the image sensor as described in (4) to (6), the supply unit supplies the transfer signal for transferring the electric charge generated by the photoelectric conversion unit during a first period to the accumulation unit or the transfer signal for transferring the electric charge generated by the photoelectric conversion unit during a second period to the accumulation unit, the second period having a length different from that of the first period.

(8) In the image sensor as described in (7), an end time of the first period is the same as an end time of the second period.

(9) In the image sensor as described in (4) to (8), one of the first voltage and the second voltage is the second substrate voltage.

(10) The image sensor as described in (4) or (5) further comprises: a first reset unit that is provided in the first semiconductor substrate and resets an electrical charge accumulated in the accumulation unit based on a reset signal; a reset signal supply unit that is provided in a semiconductor substrate different from the second semiconductor substrate and supplies the first reset unit with either a third voltage not less than the first substrate or a fourth voltage higher than the third voltage as the reset signal.

(11) In the image sensor as described in (10), one of the third voltage and the fourth voltage is the first substrate voltage.

(12) The image sensor as described in (10) further comprises: a third semiconductor substrate to which the first substrate voltage is applied, wherein: the reset signal supply unit is provided in the third semiconductor substrate.

(13) In the image sensor as described in (1) to (6), comprises: a plurality of the pixels, wherein: the supply unit included in one of a plurality of the pixels supplies the transfer signal that transfers the electric charge generated by the photoelectric conversion unit during a first period to the accumulation unit and the supply unit included in others of a plurality of the pixels supplies the transfer signal that transfers the electric charge generated by the photoelectric conversion unit during a second period to the accumulation unit, the second period having a length different from that of the first period.

(14) An image sensor comprising: a photoelectric conversion unit that photoelectrically converts incident light to generate an electric charge; a transfer unit that transfers an electric charge generated by the photoelectric conversion unit to an accumulation unit based on a transfer signal; a transfer signal supply unit that supplies the transfer unit with the transfer signal; a first reset unit that resets the electric charge accumulated in the accumulation unit based on a reset signal; a reset signal supply unit that supplies the first reset unit with the reset signal, a first semiconductor substrate provided with the photoelectric conversion unit, the transfer unit, and the first reset unit; and a second semiconductor substrate provided with the reset signal supply unit arranged in a first diffusion layer and the transfer signal supply unit arranged in a second diffusion layer having a polarity different from that of the first diffusion layer.

(15) The image sensor as described in (1) to (14) further comprises: an A/D conversion unit that performs an analog/digital conversion on an analog signal based on an amount of electric charge accumulated in the accumulation unit, by a correlated multiplex sampling process.

(16) The image sensor as described in (1) to (15) further comprises: a second reset unit that resets the electric charge accumulated in the photoelectric conversion unit.

(17) In the image sensor as described in (1) to (16), the photoelectric conversion unit is a pinned photodiode.

(18) An electronic camera comprising the image sensor as described in (1) to (16).

The above-described embodiments and variations further include the following image sensors.

(1) An image sensor comprising: a first semiconductor substrate provided with a photoelectric conversion unit that photoelectrically converts incident light and a transfer unit that transfers an electric charge generated by the photoelectric conversion unit to an accumulation unit based on a transfer signal; and a second semiconductor substrate provided with a transfer signal supply unit that supplies either one of a first voltage lower than a ground voltage and a second voltage higher than the ground voltage as the transfer signal to the transfer unit.

(2) In the image sensor as described in (1), the first semiconductor substrate has a plurality of the photoelectric conversion units, a plurality of the accumulation units, and a plurality of the transfer units; and the second semiconductor substrate has a plurality of the transfer signal supply units, wherein: some of a plurality of the transfer signal supply units transfer the electric charge generated by the photoelectric conversion unit during a first period to the accumulation unit and others of a plurality of the transfer signal supply units transfer the electric charge generated by the photoelectric conversion unit during a second period to the accumulation unit, the second period having a length different from that of the first period.

(3) In the image sensor as described in (2), an end time of the first period is the same as an end time of the second period.

(4) In the image sensor as described in (1) to (3), a first substrate voltage at the first semiconductor substrate is different from second substrate voltage at the second semiconductor substrate.

(5) In the image sensor as described in (4), one of the first voltage and the second voltage is a voltage based on the second substrate voltage.

(6) The image sensor as described in (4) or (5) further comprises: a first reset unit that is provided in the first semiconductor substrate and resets an electrical charge accumulated in the accumulation unit in response to a reset signal; a reset signal supply unit that is provided in a semiconductor substrate different from the second semiconductor substrate and supplies the first reset unit with either a third voltage not less than a ground voltage or a fourth voltage higher than the third voltage as the reset signal.

(7) In the image sensor as described in (6), one of the third voltage and the fourth voltage is a voltage based on the first substrate voltage.

(8) The image sensor as described in (6) further comprises: a third semiconductor substrate for which the first substrate voltage is set, wherein: the reset signal supply unit is provided in the third semiconductor substrate.

(9) The image sensor as described in (1) comprises a plurality of pixels, each including the photoelectric conversion unit, the accumulation unit, the transfer unit, and the transfer signal supply unit, wherein each of the transfer signal supply units included in some of a plurality of the pixels supplies the transfer signal that transfers the electric charge generated by the photoelectric conversion unit during a first period to the accumulation unit and each of the transfer signal supply units included in others of a plurality of the pixels supplies the transfer signal that transfers the electric charge generated by the photoelectric conversion unit during a second period to the accumulation unit, the second period having a length different from that of the first period.

(10) An image sensor comprising: a photoelectric conversion unit that photoelectrically converts incident light; a transfer unit that transfers an electric charge photoelectrically converted by the photoelectric conversion unit to an accumulation unit in response to a transfer signal; a transfer signal supply unit that supplies the transfer unit with the transfer signal; a first reset unit that resets the electric charge accumulated in the accumulation unit in response to a reset signal; a reset signal supply unit that supplies the first reset unit with the reset signal; a first semiconductor substrate provided with the photoelectric conversion unit, the transfer unit, and the first reset unit; and a second semiconductor substrate provided with the reset signal supply unit arranged in a first diffusion layer and the transfer signal supply unit arranged in a second diffusion layer having a polarity different from that of the first diffusion layer.

(11) The image sensor as described in (1) to (10) further comprises: an A/D conversion unit that performs an analog/digital conversion on an analog signal based on an amount of electric charge accumulated in the accumulation unit, by a correlated multiplex sampling process.

(12) The image sensor as described in (1) to (11) further comprises: a second reset unit that resets the electric charge accumulated in the photoelectric conversion unit.

(13) In the image sensor as described in (1) to (12), the photoelectric conversion unit is a pinned photodiode.

The disclosure of the following priority application is herein incorporated by reference:

Japanese Patent Application No. 2015-195280 (filed Sep. 30, 2015)

REFERENCE SIGNS LIST

3. . . image sensor,7. . . first semiconductor substrate,8. . . second semiconductor substrate,30. . . pixel,31. . . photodiode,301. . . analog circuit unit302. . . A/D conversion unit,303. . . sampling unit,306. . . individual pixel control unit,307. . . pixel driving unit