Patent ID: 12261519

DETAILED DESCRIPTION

Circuits and related techniques disclosed herein relate generally to gallium nitride (GaN) power conversion devices. More specifically, devices, circuits and related techniques disclosed herein relate to GaN integrated circuits where a gate driver integrated circuit (IC) can be utilized to harvest energy from an input pulse width modulated (PWM) signal for powering the gate driver IC, eliminating a need for a power supply for the gate driver IC. In some embodiments, the gate driver IC can be integrated with a GaN power transistor in a package to form an integrated GaN power device where the integrated GaN power device can be a pin to pin compatible replacement for a discrete silicon power MOSFET and its driving circuits. In various embodiments, the gate driver IC can store the harvested energy from the PWM signal and continue to function and drive the GaN power transistor even when the PWM signal is in a low state as explained further inFIG.1.

In some embodiments, the gate driver IC can include various protection circuits to keep the GaN power transistor in its safe operating area as summarized here and described in more detail below. More specifically, in some embodiments, the IC may include a pull-down transistor for pulling down the gate voltage of the GaN power transistor. The pull-down transistor may be integrated into the IC or integrated within the same die as the GaN transistor. The IC may drive the gate of the pull-down transistor as explained further inFIG.2.

In various embodiments, the IC can include a pull-up transistor. The pull-up transistor can enable a PWM signal to drive the gate of the GaN power transistor to a high state. In some embodiments, the IC may include clamping circuits that can protect the GaN power transistor and the internal circuitry of the IC. The clamping circuits can enable relatively high operating voltages for the PWM, for example 10 to 30 V, while allowing the gate of the GaN transistor to be kept within its safe operating region, for example, below 6.0 V. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, the operating voltages can be set to any suitable value. The operation of the pull-up transistor and the clamping circuits are described in greater detail inFIG.2.

In some embodiments, the IC may include a saturation current protection circuit. The saturation current protection circuit may sense a voltage at the drain of the GaN power transistor and trigger a protection circuit to prevent the GaN transistor from entering or staying into its saturation region. As understood by those skilled in the art, the GaN transistor may operate normally in its linear operating region, however if the GaN transistor enters into its saturation operating region, the drain current can increase with a corresponding drain voltage increase, which is undesirable in power conversion applications. In some embodiments, the saturation protection circuit can use a depletion mode (D-mode) GaN transistor to sense the drain voltage of the GaN transistor and shut down the GaN transistor when saturation is sensed. The saturation protection circuit is discussed in detail inFIGS.4-6.

In various embodiments, the IC may include a turn-on dv/dt control circuit by utilizing an external resistor in series with the PWM signal. DV/dt control circuits are discussed in detail inFIGS.7A-Cand8. In various embodiments, the IC may include a turn-off dI/dt control circuit by utilizing package bondwire inductances. The gate of the GaN transistor can be kept in its safe operating area by the use of the turn-off dI/dt control circuit where stress voltage on the gate of the GaN transistor can be kept to relatively minimal values. The turn-off dI/dt control circuit is described in more detail inFIG.9.

In some embodiments, the IC may include a gate driving voltage generation circuit with hysteresis in order to control a gate voltage of the GaN transistor to reduce power consumption and improve operational speed. The gate driving voltage generation circuit with hysteresis is described in more detail inFIGS.10-11.

As appreciated by one of ordinary skill in the art having the benefit of this disclosure, any portion of and/or any combination of the features described herein can be integrated within the IC, can be integrated within the GaN transistor or the features can be partially integrated within the IC and partially integrated within the GaN transistor. In various embodiments, the integrated GaN power device can operate at relatively higher frequencies than the silicon power MOSFET it replaces. Further, the IC can be formed in silicon, silicon-carbide, GaN or any other suitable semiconductor material. In various embodiments, the integrated power device can be used in high current and/or high voltage power conversion applications such as (but not limited to) AC to DC converters, and applications such as solar power conversion, automotive and battery charging applications.

Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part hereof. The ensuing description provides embodiment(s) only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the embodiment(s) will provide those skilled in the art with an enabling description for implementing one or more embodiments. It is understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and description are not intended to be restrictive. The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

Integrated GaN Power Package

FIG.1illustrates an integrated GaN power device100according to an embodiment of the disclosure. As shown inFIG.1, integrated GaN power device100can include a GaN power transistor114and a gate driver integrated circuit (IC)112in a semiconductor package110. By integrating the GaN power transistor114and the gate driver IC into a single semiconductor package110, a majority of package parasitic elements can be eliminated, allowing the use of the integrated GaN power device100in high current and high power applications. The integrated GaN power device100can include a top slab118. A drain of the GaN power transistor114can be coupled to the top slab118through multiple bondwires120, where the top slab118is coupled to multiple pins102to form a drain of the integrated GaN power device100. The integrated GaN power device100can further include a die pad116.

A source of the GaN power transistor114can be coupled to the die pad116through multiple bondwires122. The die pad116can be coupled to multiple pins104to form a source of the integrated GaN power device100. A ground terminal of the IC112can be coupled to pin106through bondwire126to form a low parasitic (kelvin) source connection for the IC. An input terminal of the IC can be connected to input pin108through bondwire124to form an input for a drive signal into the integrated GaN power device100. In some embodiments, the input pin108can be coupled to a pulse width modulated (PWM) signal to drive the IC112. The IC can be coupled to the GaN power transistor114through bondwires128. In numerous embodiments, the IC can be coupled to the GaN power transistor114by clips, for example copper clips. In some embodiments, the IC can be coupled to the GaN power transistor114by bumps. In various embodiments, the IC112can drive the GaN power transistor114and can include various features for driving the GaN power transistor and to keep the GaN power transistor in its safe operating area. In the illustrated embodiment, the integrated GaN power device100can be used to replace a silicon power MOSFET in various applications. It will be understood by those skilled in the art that the gate driver IC112can be utilized to drive GaN high electron mobility transistors (HEMT) as well as other power transistors such as (but not limited to) isolated gate bipolar transistors (IGBT) and silicon MOSFETs.

In various embodiments, gate driver IC112can operate without a need for a power supply (Vdd). This feature can eliminate a need for extra pins for Vdd in the package110and allow pin-to-pin compatibility of the integrated GaN power device100so it is interchangeable with discrete silicon power MOSFETs or other packaged semiconductor devices. In some embodiments, the energy for operation of the IC112can be drawn from an input PWM signal when the PWM signal is in a high state and the IC can store the energy on its internal components. The IC can continue to function when the PWM signal is in a low state by utilizing the stored energy. Further, even when the energy stored in the IC has dissipated, the IC can continue to actively pull down the gate of the GaN power transistor114in order to prevent a dv/dt event causing an involuntary turn-on.

In the illustrated embodiment, the input pin108of the package110may draw relatively low amounts of current similar to a gate of a discrete silicon power MOSFET it replaces. Similar to the gate of the silicon power MOSFET, the PWM signal can have two logic states of low and high. For example, in the low state the PWM signal can be at zero volt, while its high state value can be 10 to 30 V. The IC112can drive the gate of the GaN power transistor114at appropriate voltage values, for example, between 0 to 6 V, even when the PWM signal varies between 0 to 10-30 V. In this way, the IC112can keep the gate of the GaN power transistor114in its safe operating area even when the PWM signal is above the safe operating voltage of the GaN transistor and prevent damage to the gate of the GaN transistor. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, the value for operating voltages can be set to any suitable value as appropriate for specific applications.

In some embodiments, during power-up the IC112can turn on and perform power-up functions to such that the GaN power transistor114is kept in its safe operating area during the power-up. The IC112can drive the gate of the GaN power transistor114while monitoring a status of the GaN power transistor114by sensing various characteristics of the GaN transistor such as, but not limited to, over-current, over-voltage characteristics and over-temperature. To eliminate a need for a power pin such as a Vdd pin, the IC112may draw power from the input PWM signal and store the energy within its internal capacitors228. The stored energy can be used by the IC112to function even when the PWM signal is in a low state and the GaN transistor114has been turned off. During the PWM low state, the IC112can continue to function and can actively keep the gate of the GaN power transistor114in a low state to prevent the gate from turning on due to a dv/dt event, which may cause damage to the GaN transistor.

In some embodiments, the integrated GaN power device100can have little to no leakage current into its input terminal during a stand-by state. In various embodiments, semiconductor packages such as, but not limited to, dual-flat no-leads (DFN) or TO-247can be utilized to integrate the IC112and the GaN power transistor114in order to form a pin-to-pin replacement for a discrete silicon power MOSFETs, silicon carbide (SiC) FETs, or other power devices without a need to modify a printed circuit board (PCB) layout. As understood by those skilled in the art, in some applications it can be difficult to use GaN power transistors in transistor outline (TO-type) power packages, such as three-terminal or four-terminal TO-247or TOLL package, due to the relatively high parasitic inductance of the package that can cause excessive ringing and oscillations in high current applications. In the illustrated embodiment, the GaN power transistor114can be used in a TO-type packages, such as but not limited to three-terminal TO-247, four terminal TO-247and TOLL package, by integrating the gate driver IC112into the TO package along with the GaN power transistor114where various features of the gate driver IC, such as, but not limited to, dv/dt control and dI/dt control, can enable the use of GaN power transistors in a TO package. Further, the integrated GaN power device100can be used for pin-to-pin replacement of discrete power MOSFETs, silicon carbide (SiC) FETs, or other power devices without a need to modify a printed circuit board (PCB) layout. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, other suitable semiconductor packages may be used for the integration of the GaN power transistor114and gate driver IC112, as appropriate for specific applications.

Energy Harvesting Circuits, Integrated Pull-Up and Pull-Down Transistor Circuits, and Voltage Clamping Circuits

FIG.2illustrates schematic of a circuit200with energy harvesting, integrated pull-up and pull-down transistors, and voltage clamping features according to embodiments of the disclosure. In some embodiments, circuit200can be used in the integrated GaN power device100. As shown inFIG.2, circuit200can include a GaN power transistor202having a gate208, a drain204and a source206. In some embodiments, the GaN power transistor202is similar to the GaN power transistor114. Drain204may be coupled to a pin277, and the source206may be coupled to a pin279. In some embodiments, the drain204and source206may not be coupled to pins, instead they may be coupled to other circuit nodes that are monolithically integrated with the GaN power transistor202. Circuit200can further include an input terminal pin257that is configured to receive a signal278. In some embodiments, the signal278can be a pulse width modulated (PWM) signal. The input terminal pin257can be connected to a pull-up transistor210with a collector254, a base216, and a source214. In various embodiments, the pull-up transistor210can be a bipolar NPN transistor, while in other embodiments it can be a P-MOSFET. In some embodiments, pull-up transistor210can be a N-MOSFET. In various embodiments, pull-up transistor210can be formed in a compound semiconductor substrate, or any other suitable substrate. In some embodiments, the pull-up transistor210can be integrated within the gate driver IC112. In various embodiments, the pull-up transistor can be a GaN-based transistor and integrated in the same die as that of the GaN power transistor202.

The source214can be connected to a gate208of a GaN power transistor202. In some embodiments, the GaN power transistor202along with circuit200can be arranged to be used in a low-side configuration. In various embodiments, the GaN power transistor202along with circuit200can be arranged to be used in a half-bridge configuration. In some embodiments, the GaN power transistor202along with circuit200can be arranged to be used in a high-side configuration. When signal278is in a high state, pull-up transistor210can be turned-on, thereby allowing a current to flow into the gate208, thus charging a capacitance of the gate208. This can cause the GaN power transistor202to turn on. In various embodiments, the pull-up transistor210can be a bipolar NPN transistor, while in other embodiments pull-up transistor210can be a P-MOSFET. In some embodiments, transistor210can be a N-MOSFET. In various embodiments, transistor210can be formed in a compound semiconductor substrate, or any other suitable substrate. The pull-up transistor210can be integrated within the gate driver IC112, or it can be a GaN-based transistor and integrated into the same die as that of the GaN power transistor202.

The signal278can provide power to the base216of the pull-up transistor210through resistor252. When the signal278goes high, pull-up transistor210can pull up the gate208of the GaN power transistor202high by providing a current to charge the gate208. Circuit200can include a substrate terminal248which can be connected to a substrate280of the IC112die. In various embodiments, the substrate280can be connected to ground. Circuit200can include a pull-down transistor230with a gate terminal236, a source terminal234and a drain terminal232. The drain terminal232of the pull-down transistor230can be connected to the gate208of the GaN power transistor202and the source terminal234of the pull-down transistor230can be connected to the source206of the GaN power transistor202and substrate248. The pull-down transistor is arranged to pull down the gate208of the GaN power transistor202when PWM signal is in a low state. The gate terminal236of the pull-down transistor230can be connected to a logic circuit289and be driven by a signal Vptg2generated by the logic circuit289. When PWM signal goes low, signal Vptg2can go high which can turn on the pull-down transistor230resulting in the drain terminal232going low and pulling down the gate208of the GaN power transistor202. The pull-down transistor230can be formed within the same die as the gate driver circuit, or can be GaN-based and formed within the same die as the GaN power transistor202and integrated in the same die as that of the GaN power transistor202. The pull-down transistor230can be a relatively large transistor in order to provide a solid pull down of the gate208of the GaN power transistor202.

In some embodiments, circuit200can include a clamping circuit295. The clamping circuit295can clamp the gate208of the GaN power transistor202to such that the gate stays within its safe operating area. The clamping circuit295can enable the PWM signal to have a wide range of operating voltages, for example 10 to 30 V, while keeping the gate208of the GaN power transistor202within its safe operating area, for example, below 6.0 V. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, the operating voltages can be set to any suitable value. The clamping circuit295can include a Zener diode250, and two diode-connected NPN transistors,262and272.

Source266of transistor262can be connected to the Zener diode250. Collector268can be connected to base of the transistor262and to the source264of transistor272. Transistor272can have a collector274connected to its base276, where the collector274is also connected to the base216of the pull-up transistor210. The Zener diode250can generate a voltage (Vz) at its cathode233. The value of Vzcan be, for example, 5.2 V. The diode-connected transistors262and272can generate a voltage drop of, for example, 0.7 V each across their collector to source terminals. Thus, a voltage at the base216of transistor210can be Vz+2Vbe. It will be understood by those skilled in the art that the order that these three devices are connected can be different, while the generated voltage is Vz+2Vbe. The voltage at the gate208for the GaN power transistor202can be one Vbebelow the voltage at the base216. Therefore, the voltage the gate208of the GaN power transistor202can be Vz+Vbe. This voltage can have a value, for example, 5.9 V, thus clamping the gate208to voltages below 6.0 V, preventing the gate208from exceeding its safe operating voltage.

Circuit200can include a clamping circuit295. The clamping circuit295can clamp the gate208of the GaN power transistor202such that the gate208stays within its safe operating area. The clamping circuit295can enable the PWM signal to have a wide range of operating voltage, for example 10 to 30 V, while keeping the gate208of the GaN power transistor202within its safe operating area, for example, below 6.0 V. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, the PWM operating voltages can be set to any suitable value. The clamping circuit295can include a Zener diode250, and two diode-connected NPN transistors,262and272. Transistor262has a source266which can be connected to the Zener diode250and has a collector268which can be connected to the base of the transistor262and to the source264of transistor272.

Transistor272can have a collector274which can be connected to the base216of the pull-up transistor210. The Zener diode can generate a voltage Vz at its cathode233, which can be, for example, 5.2 V. The diode-connected transistors262and272can generate a voltage drop of, for example, 0.7 V each across their collector to source terminals. Thus, a voltage at the base216can be Vz+2Vbe. The voltage at the gate208for the GaN power transistor202can be one Vbebelow the voltage at the base216of transistor210. Therefore, the voltage at the gate208of the GaN power transistor202can be Vz+Vbe. This voltage can have a value, for example, 5.9 V. Thus, the clamping circuit295can clamp the gate208to voltages below 5.9 V and prevent the gate208from exceeding its safe operating voltage. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, the output voltage of the clamping circuit can be set to any suitable value. In some embodiments, transistor262can be an NPN bipolar transistor that is diode-connected. The diode-connected transistor262can mitigate temperature variations of Vz. In various embodiments, transistor272can mitigate manufacturing process variations as well as temperature variations of characteristics of transistor210. It will be understood by those skilled in the art that the order that transistors262and272are connected can be different, while the mitigating temperature and manufacturing process variations.

Circuit200can include an energy harvesting and storage circuit299. Storage circuit299can include a transistor218connected in series with an energy storing capacitor228. In some embodiments, transistor218can be a configured as a diode-connected transistor. In various embodiments, a diode may be used instead of transistor218. Transistor218can have a collector terminal220, a source terminal222and a base terminal226. The collector terminal220can be connected to base terminal226. Source terminal222can be connected to the capacitor228. When PWM signal goes high, transistor210can turn on causing transistor218to turn on as well. The capacitor228can charge up and store energy from the PWM signal. Thus, a voltage can develop at source terminal222of transistor218equal to Vz, because while voltage at source214of transistor210is Vz+Vbe, the voltage at source terminal222of transistor218can be one Vbebelow the voltage at source214of transistor210. The voltage at source terminal222of transistor218can be, for example, 5.2 V. This voltage can be used to power up the circuitry within the IC112, even when the PWM signal goes low. In some embodiments, the present disclosure includes methods for generating a voltage at the gate of the GaN power transistor202and storing a regulated voltage in a storage element, such as capacitor228.

Circuit200can include a transistor240which can be used to turn off the charging of the gate208of the GaN power transistor202when PWM goes low. The drain242of transistor240can be connected to the base216of pull-up transistor210and the source244of transistor240can be connected to the substrate248. The gate246of the transistor240can be configured to receive a signal Vptg2. When signal278goes low, signal Vptg2246can go high and turn on both transistors230and240. Pull-down transistor230can pull down the gate of GaN power transistor202and transistor240can pull down the base216of the pull-up transistor210, thus turning it off. By turning off the pull-up transistor210, the charging of the gate208of the GaN power transistor202can be stopped.

FIG.3shows a graph300of a quiescent current at input terminal pin257of circuit200inFIG.2and a graph310showing a gate voltage of the GaN power transistor202of circuit200inFIG.2. Graph308, showing the quiescent current, graph310showing gate voltage have been plotted as a function of PWM voltage306. As shown inFIG.3, as PWM voltage306increases, the gate voltage of the GaN power transistor increases linearly as the gate charges. The gate voltage increases to about 6.0 V and is clamped at that voltage because the clamping circuit295clamps the gate208of the GaN power transistor202. Further, graph308shows that there is no static current flowing into the PWM terminal prior to the gate getting clamped. There is no current until the clamping circuit295is activated. When the gate208gets clamped, the quiescent current increases linearly. In some embodiments this feature can make the integrated GaN power device100compatible with discrete power applications since its stand-by gate current is zero.

Saturation Current Protection Circuits

FIG.4Aillustrates schematic of a circuit400A with saturation current protection feature according to an embodiment of the disclosure. As shown inFIG.4A, circuit400A can include a GaN power transistor440with a gate412, a drain422and a source428. The drain422can be connected to a load. Circuit400A can be utilized to detect when the GaN power transistor440enters its saturation operating region. Operation in a saturation region can occur when the drain current of a transistor increases while its drain-to-source voltage stays relatively constant.

As shown inFIG.4A, the source428of the GaN power transistor440can be connected to a ground node430. Circuit400A can monitor a drain voltage of the GaN power transistor by using a GaN transistor442. In some embodiments, transistor442can be a depletion mode GaN transistor. While the GaN power transistor440can be a high voltage transistor, with operational voltages of, for example, 400 V, circuit400A can be a low voltage circuit for monitoring the GaN power transistor440and prevent it from operating in the saturation region. In the illustrated embodiment, a voltage at the drain422of the GaN power transistor440can be monitored and when that voltage exceeds a threshold, for example 8 V, circuit400A can turn off the GaN power transistor440to protect it from getting damaged, thus preventing damage to the power converter. More specifically, in some embodiments, circuit400A can use a depletion mode (D-mode) GaN transistor442, where the drain422of the GaN power transistor440is connected to the drain421of transistor442. The gate426of transistor442can be connected to ground node430. A source424of transistor442can be connected to a resistor divider419.

Circuit400A can include a comparator406and logic circuits408. In some embodiments, resistor divider419, comparator406and logic circuits408can be formed in low voltage silicon technology. In various embodiments, resistor divider419, comparator406and logic circuits408can be formed in a GaN technology and integrated within the same die as the GaN power transistor440. In some embodiments, resistor divider419can include two resistors402and404connected in series. An output416of the resistor divider can be connected to a first input499of comparator406, while a second input414of the comparator406can be connected to a reference voltage (Vref)415. Reference voltage415can have a value, for example, 2.5 V. An output418of the comparator can be connected to logic circuits408. A voltage at drain422of the GaN power transistor440can vary, for example, from 0 to 400 V. The source424of D-mode GaN transistor442can be clamped at its pinch-off voltage, for example, 15 V.

The source424of D-mode GaN transistor442follows the drain voltage of GaN power transistor440until its pinch-off voltage is reached. After that, the source424of D-mode GaN transistor442is clamped at a pinch-off voltage, for example 15 V. In some embodiments, the source voltage of the D-mode GaN transistor442follows its drain voltage until the source voltage reaches the pinch-off voltage of the transistor. At that point, the source voltage gets clamped to the pinch-off voltage and stays constant at that voltage. In this way, the D-mode GaN transistor442can enable connection of its source424to resistor divider419, while the drain421of the D-mode GaN transistor442can operate at high voltage, for example up to 400 V. When the voltage at source424of D-mode GaN transistor442passes a preset value, for example 8 V, it can cause a shutdown of the GaN power transistor440.

Resistor divider419can provide an output416which tracks its input at node423, but at a lower voltage level. The output voltage of the resistor divider419can be compared to a reference voltage415, for example 2.5 V, which is a threshold of the comparator406. When the voltage at input499of the comparator exceeds Vref, comparator406can switch and its output418voltage can go from a low state to high state. The output418of the comparator406can be connected to logic circuits408. When the output418of the comparator goes to a high state, the output420of the logic circuits408turns off the gate of the GaN power transistor440and shuts down the GaN power transistor440. It will be understood by those skilled in the art, that transistor442can be a D-mode GaN transistor which can be integrated within the same die as that of GaN power transistor440. In some embodiments, transistor442can be an enhancement-mode GaN transistor. In various embodiments, transistor442can be a silicon transistor.

FIG.4Billustrates a graph400B showing voltages of nodes within circuit400A as a function of time. Graph422ashows drain voltage of GaN power transistor440where that voltage can go from 0 volt to 400 V. Graph424ashows source voltage of D-mode GaN transistor442following the drain voltage of GaN power transistor440(graph422a). As shown in graph424a, the source voltage goes from 0 V to 15 V, where the source of the D-mode GaN transistor442is clamped at 15 V. Graph416ashows the output416voltage of the resistor divider419. Graph415ashows the value of Vrefat 2.5 V. Finally, graph418ashows the output voltage of comparator406, where the comparator switches from a low state to high state when416a(output of the resistor divider) crosses415a(Vref). As appreciated by one of skill in the art, the voltages shown in graph400B are for example only and other embodiments may have different operating characteristics.

FIG.5illustrates a schematic of a circuit500that includes a saturation current protection feature, according to an embodiment of the disclosure. Circuit500is similar to circuit400A except gate526of transistor542is connected to gate512of the GaN power transistor540. This enables the use of low pinch-off, for example 5 V, D-mode GaN transistors for sensing a drain voltage at the drain522of the GaN power transistor540. In order to monitor a drain voltage of GaN power transistor540using D-mode GaN transistor542with a low pinch-off voltage, dynamic biasing of the gate526can be used in order to allow for proper operation of the D-mode GaN transistor. Dynamic biasing can increase a gate voltage of the D-mode GaN transistor542and provide for the gate-to-source voltage of the D-mode GaN transistor to vary instead of being fixed.

Circuit500can be used to detect when the GaN power transistor440enters its saturation operating region. The source528of the GaN power transistor540can be connected to a ground node530. Circuit500can monitor a drain voltage of the GaN power transistor by using a transistor542. While the GaN power transistor540can be a high voltage transistor with operational voltage of, for example 400 V, circuit500can utilize low voltage circuits to monitor the GaN power transistor and prevent it from operating in the saturation region. In some embodiments, this can be done by monitoring a voltage at the drain522of the GaN power transistor540and when the voltage exceeds a threshold, for example 8 V, circuit500can turn off the GaN power transistor to protect it from getting damaged. More specifically, circuit500can use a D-mode GaN transistor542, where the drain522of the GaN power transistor540is connected to the drain521of transistor542. Circuit500can include a comparator506and logic circuits508.

In some embodiments, resistor divider519, comparator506and logic circuits508can be formed in low voltage silicon technology. In various embodiments, resistor divider519, comparator506and logic circuits508can be formed in a GaN technology and integrated within the same die as the GaN power transistor540. Resistor divider519can include two resistors502and504connected in series. An output516of the resistor divider can be connected to a first input of comparator506, while a second input514of the comparator506can be connected to a reference voltage (Vref)515. Reference voltage515can have a value, for example, 2.5 V. An output518of the comparator can be connected to logic circuits508. A voltage at drain522of the GaN power transistor540can vary, for example, from 0 to 400 V. The source524of the transistor542is clamped at its pinch-off voltage, for example, 15 V. The source524of transistor542follows the drain voltage of GaN power transistor540until its pinch-off voltage is reached. After that, the source524of transistor542is clamped at the pinch-off voltage, for example 15 V. Transistor542has a characteristic that its source voltage follows its drain voltage until the source voltage reaches the pinch-off voltage of the transistor. At that point, the source voltage gets clamped to the pinch-off voltage and stays constant at that voltage. In this way, the D-mode GaN transistor542can enable connection of its source524to the low voltage resistor divider519, while the drain521of the D-mode GaN transistor542can operate at high voltage, for example up to 400 V. When the voltage at source524of transistor542passes a preset value, for example 8 V, it can cause a shutdown of the GaN power transistor540.

Resistor divider519can provide an output at516which tracks its input at node523, but at a lower voltage level. The output voltage of the resistor divider519can be compared to a reference voltage515, for example 2.5 V, which is a threshold of the comparator506. When the voltage at input599of the comparator exceeds Vref, comparator506can switch its output voltage at518from a low state to high state. The output518of the comparator506can be connected to logic circuits508. When the output518goes to a high state, the output520of the logic circuits508turns off the gate of the GaN power transistor540and shuts down the GaN power transistor540. It will be understood by those skilled in the art, that transistor542can be a D-mode GaN transistor which can be integrated within the same die as that of GaN power transistor540. In some embodiments, transistor542can be an enhancement-mode GaN transistor. In various embodiments, transistor542can be a silicon transistor.

FIG.6illustrates schematic of a circuit600with a saturation current protection feature, according to an embodiment of the disclosure. Circuit600is similar to circuit400A except gate626of transistor642is connected to an output of logic circuits608and is independently controlled by the logic circuits608. This enables the use of low pinch-off, for example 5 V, D-mode GaN transistors for sensing a drain voltage at the drain622of the GaN power transistor640. In order to monitor a drain voltage of GaN power transistor640using D-mode GaN transistor642with a low pinch-off voltage, independent biasing of the gate626can be used in order to allow for proper operation of the D-mode GaN transistor. Dynamic biasing can increase a gate voltage of the D-mode GaN transistor642and provide for the gate-to-source voltage of the D-mode GaN transistor to vary instead of being fixed.

Circuit600can be used to detect when the GaN power transistor640enters its saturation operating region. The source628of the GaN power transistor640can be connected to a ground node630. Circuit600can monitor a drain voltage of the GaN power transistor by using a transistor642. While the GaN power transistor640can be a high voltage transistor, with operational voltage of for example 400 V, circuit600can utilize low voltage circuits to monitor the GaN power transistor and prevent it from operating in the saturation region. This can be done by monitoring a voltage at the drain622of the GaN power transistor640and when the voltage exceeds a threshold, for example 8 V, circuit600can turn off the GaN power transistor to protect it from getting damaged. More specifically, circuit600can use a D-mode GaN transistor642, where the drain622of the GaN power transistor640is connected to the drain621of transistor642.

Circuit600can include a comparator606and logic circuits608. In some embodiments, resistor divider619, comparator606and logic circuits608can be formed in low voltage silicon technology. In various embodiments, resistor divider619, comparator606and logic circuits608can be formed in a GaN technology and integrated within the same die as the GaN power transistor640. Resistor divider619can include two resistors602and604connected in series. An output616of the resistor divider can be connected to a first input of comparator606, while a second input614of the comparator606can be connected to a reference voltage (Vref)615. Reference voltage615can have a value, for example, 2.5 V. An output618of the comparator can be connected to logic circuits608.

A voltage at drain622of the GaN power transistor640can vary, for example, from 0 to 400 V. The source624of transistor642is clamped at its pinch-off voltage, for example, 15 V. The source624of transistor642follows the drain voltage of GaN power transistor640until its pinch-off voltage is reached. After that, the source624of transistor642is clamped at the pinch-off voltage, for example 15 V. Transistor642has a characteristic that its source voltage follows its drain voltage until the source voltage reaches the pinch-off voltage of the transistor. At that point, the source voltage gets clamped to the pinch-off voltage and stays constant at that voltage. In this way, the D-mode GaN transistor642can enable connection of its source624to the resistor divider619, while the drain621of the D-mode GaN transistor642can operate at high voltage, for example up to 400 V. When the voltage at source624of transistor642passes a preset value, for example 8 V, it can cause a shutdown of the GaN power transistor640.

Resistor divider619can provide an output at616which tracks its input at node623, but at a lower voltage level. The output voltage of the resistor divider619can be compared to a reference voltage615, for example 2.5 V, which is a threshold of the comparator606. When the voltage at input699of the comparator exceeds Vref, comparator606can switch the output618voltage from a low state to high state. The output618of the comparator606can be connected to logic circuits608. When the output618goes to a high state, the output620of the logic circuits608turns off the gate612of the GaN power transistor640and shuts down the GaN power transistor640. It will be understood by those skilled in the art, that transistor642can be a D-mode GaN transistor which can be integrated within the same die as that of GaN power transistor640. In some embodiments, transistor642can be an enhancement-mode GaN transistor. In various embodiments, transistor642can be a silicon transistor.

Turn-on dv/dt Control

FIG.7Aillustrates schematic of a circuit700A with turn-on dv/dt control feature according to an embodiment of the disclosure. Circuit700A can be used to mitigate the relatively high parasitic inductances of electronic packages such as, but not limited to, TO-247or TOLL packages. Circuit700A illustrate a variation of circuit200. Circuit700A illustrates a GaN power transistor202along with a driver IC710and turn-on dV/dt control circuits. Circuit700A can include an impedance element704. In some embodiments, circuit200may be coupled to an impedance element704. Impedance element may be external to the integrated GaN power device100. In various embodiments, impedance element704can include one or more passive components. In some embodiments, impedance element704can be a resistive element, while in other embodiments impedance element704can include a resistive element and a capacitive element, where the capacitive element is coupled in parallel to the resistive element. In various embodiments, the impedance element704may include a network of resistive and capacitive elements. Impedance element704can be coupled to the input terminal pin257. Impedance element704can be configured to receive a signal278. Impedance element704can be utilized to control rate of change of voltage as a function of time (dV/dt) for the GaN power transistor202. As discussed above inFIG.1, integrated GaN power device100may be used as a pin-to-pin replacement for discrete silicon power MOSFETs, therefore a capability to control the dV/dt at the drain204of the GaN power transistor202can be beneficial. In absence of a dV/dt control circuit, spurious dV/dt may cause ringing and oscillations at the drain204that may couple onto the gate208and create a false turn-on of the GaN power transistor202.

A GaN power transistor202turn-on dV/dt control can be achieved by utilizing an impedance element704. The impedance element704can be used to slow down a relatively rapid rate of change of voltage as a function of time at the input terminal pin257. Gate drive node730can be connected to gate208of the GaN power transistor202. Capacitors712and718, and inductor716are package parasitic elements. Substrate can be grounded at node706and connected to source206of the GaN power transistor202. In some embodiment, impedance element704can be integrated in the gate driver IC. In various embodiments, a current through input terminal pin257flowing to the gate of the GaN power transistor202can be limited by limiting a current of the pull-up transistor210in order to control turn-on dv/dt. This can be achieved by reducing a gate drive of the pull-up transistor210.

FIG.7Billustrates a graph700B showing PWM voltage740as a function of time748and a rate of change of drain-to-source (Vas)742at turn-on of GaN power transistor202as a function of time. As can be seen inFIG.7B, as resistance of the impedance element704is increased, a slope of drain turn-on falling edge decreases, indicating a reduction in dv/dt. Circuit200can enable this feature because when signal278goes high, a current that charges the gate208of GaN power transistor202passes through the impedance element704which is in series with pull-up transistor210. In this way, dv/dt at the drain204can be controlled and electromagnetic interference (EMI) of the power convert can be reduced.FIG.7Cillustrates a graph showing dv/dt770as a function of resistance of778impedance element704of circuit700A. Graphs772,774and776show dv/dt as a function of resistance778for PWM high values of 8 V, 10 V and 12 V, respectively. As resistance value is increased from, for example, few ohms to few kilo ohms, dv/dt values can decrease from, for example, 100 V/ns to 10 V/ns.

FIG.8illustrates a schematic of a circuit800that includes turn-on dv/dt control and gate clamping features, according to an embodiment of the disclosure. Circuit800shows a gate driver and control circuit883coupled to a GaN-based circuit889. Circuit800can be used to mitigate ringing and oscillations caused by relatively high parasitic inductances of electronic packages such as, but not limited to, TO-247or TOLL packages that may be used as described inFIG.1. GaN-based circuit889can include GaN power transistor202having a gate208, a drain204and a source206. GaN-based circuit889may further include a pull-down transistor822having a drain824, a gate828, and a source826. Drain824can be connected to gate208, while source826may be connected to a ground node840. In some embodiments, GaN-based circuit889may be used in a high-side arrangement, where the source826may be connected to a switch node (Vsw) of a half-bridge. Gate driver and control circuit883may include a pull-up transistor814having a gate816, a drain818and the source820. Gate208may be coupled to the source820. Pull-up transistor814may include a body diode819. Drain818can be coupled to an input terminal pin855. In some embodiments, gate driver and control circuit883can be formed on a silicon-based die while the GaN-based circuit889is formed on a GaN-based die. In various embodiments, gate driver and control circuit883may formed on the same die as the GaN-based circuit889. In some embodiments, while gate driver and control circuit883is formed on a separate die than the GaN-based circuit883, the pull-up transistor may be formed on the same die as the GaN-based circuit889. In various embodiments, input terminal pin855may be connected to external components.

Circuit800can further include an impedance element804, a unidirectional current conductor806, an impedance element808and a unidirectional current conductor810. An impedance element may include one or more passive components. In some embodiments, impedance element can be a resistive element, while in other embodiments impedance element can include a resistive element and a capacitive element, where the capacitive element is coupled in parallel to the resistive element. In various embodiments, the impedance element may include a network of resistive and capacitive elements. A unidirectional current conductor may include, but not limited to, a diode. Impedance element804may be coupled to node802. Node802can be configured to receive a signal278. In some embodiments, impedance element804, unidirectional current conductor806, impedance element808and unidirectional current conductor810can be external to the integrated GaN power device100ofFIG.1. In various embodiments, impedance element804, unidirectional current conductor806, impedance element808and unidirectional current conductor810can be external can be internal to integrated GaN power device100. Source820can be connected to the gate208. Pull-up transistor814may be a bipolar transistor, or a MOSFET. In some embodiments, pull-up transistor814can be a N-MOSFET, while in other embodiments pull-up transistor814may be a P-MOSFET.

Gate driver and control circuit883may include a logic circuit and control circuit812, that is coupled to the gate828. The control and logic circuit812can be configured to control a conductivity of the pull-down transistor822. In some embodiments, pull-down transistor822can be GaN-based and formed on the same die as GaN power transistor202. In various embodiments, pull-down transistor822can be formed on a separate die. In some embodiments, pull-down transistor822can be formed in silicon, or other suitable semiconductor substrates. Circuit800may further include a clamp circuit853. In some embodiments, circuit800may not include the clamp circuit853. Circuit800may further include a control circuit869that is arranged to control a conductivity state of the gate816. In some embodiments, circuit800may not include a control circuit gate816, instead gate816may be connected to input terminal pin855through an impedance element.

When signal278goes high, pull-up transistor814can turn on. Thus, a current can flow through impedance element804, unidirectional current conductor806and transistor pull-up814to the gate208. In this way, a capacitance of the gate208can be charged causing the GaN power transistor202to go into a conductive state. By setting a value for the impedance element804, a user can control a turn-on dV/dt of the GaN power transistor202. In this way, ringing and oscillations can be prevented, thereby keeping the GaN power transistor202in its safe operating area (SOA). The pull-up transistor814can act as a clamp to keep the GaN power transistor202in its SOA. The clamp circuit853can set a voltage at the gate816in such a way that a large portion of the input signal voltage may drop across the drain818to source820. For example, a GaN power transistor may have a 7 V rating. The disclosed dV/dt control circuit can keep the GaN power transistor in its SOA when the input signal278may be, for example, at 10 to 20 V. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, disclosed turn-on dV/dt control circuits can control the dV/dt for other voltage values at the input signal, for example, 1 to 50 V. Further, as appreciated by one of ordinary skill in the art, disclosed turn-on dV/dt control circuits may utilize external impedance elements to control the dV/dt. In various embodiments, the impedance element can include one or more passive components. In some embodiments, the impedance element can be a resistive element, while in other embodiments impedance element can include a resistive element and a capacitive element, where the capacitive element is coupled in parallel to the resistive element. In various embodiments, the impedance element may include a network of resistive and capacitive elements. In some embodiments, gate816may be controlled by other logic circuits instead of the clamp circuit853. In various embodiments, clamp circuit853can be similar to the clamping circuit295.

When signal278goes low, a charge on the gate208can discharge through the body diode819, impedance element808and unidirectional current conductor810. In this way, the charge of the gate208can be discharged, thus a voltage at the gate208can go low causing the GaN power transistor202to go into a non-conductive state. By setting a value for the impedance element808, a user can control a turn-off dV/dt of the GaN power transistor202. In this way, ringing and oscillations can be prevented, thereby keeping the GaN power transistor in the non-conductive state. Furthermore, the logic and control circuit812can sense a voltage at the gate208. When the voltage drops to a value below a threshold, the logic and control circuit812may turn on the pull-down transistor822after a relatively small period. In this way, the gate208is kept in a low state and prevented from turning the GaN power transistor202from false turn-on. In some embodiments, circuit800can be used in a high-side configuration. In various embodiments, circuit800may be used in a half-bridge configuration. In some embodiments, circuit800can be used in a low-side configuration.

Turn-Off dI/dt Control

FIG.9illustrates schematic of a circuit900with turn-off dI/dt control feature according to an embodiment of the disclosure. Circuit900can be used to mitigate the relatively high parasitic inductances of TO-247or TOLL packages. Circuit900can include a GaN power transistor926with a source928, a gate924and a drain922. In some embodiments, the GaN power transistor can be connected within its package by connecting bondwires between GaN transistor die and its package. The bondwires can have inductances associated with them. Circuit900shows an inductance920of a bondwire with an inductance value L. For example, bondwire inductance can be created by a down-bond between a source928of the GaN power transistor926and a package pad. Element918represents inductance of package to the printed circuit board. The bondwire inductance L of920can be utilized to sense rate of change of current as a function of time (dI/dt) in the source of the GaN power transistor926. When the GaN power transistor is turned off, the current through the source of the GaN power device decreases. This can cause a value of a voltage across inductance920, which is given by L×dI/dt to change rapidly. The voltage across inductance920is sensed by impedance elements914and916. Impedance element914is connected a cathode919of a diode912and impedance element916is connected to an anode917of diode912.

The sensed voltage is fed back into a source910of a transistor904. A drain902of the transistor904can be connected to a gate924of the GaN power transistor926. In some embodiments, the transistor904can be a silicon transistor, while in other embodiments, it can a GaN transistor, which can be integrated within the same die as that of the GaN power transistor926. A voltage at the source910of the transistor904can increase when a voltage across inductance920increases because the voltage across inductance920is fed back into source910with a positive polarity. When the voltage at source910of the transistor904increases, the gate-to-source voltage (Vgs) can decrease, which can cause pull transistor904to have less drive. This in turn can reduce a turn-off speed of the GaN power transistor926. The more voltage that is developed across inductance920, the less drive transistor904can have, which in turn can slow down the turn-off of the GaN power transistor926. It will be understood by those skilled in the art that transistor904, impedance elements914and916and diode912can be formed in GaN and integrated within the same die as that of GaN power transistor926, or can be form in silicon, or some components may be formed in GaN while other components are formed in silicon.

In some embodiments, feedback of voltage across inductance920can be used to modulate a voltage on gate906of the transistor904in order to reduce the pull down drive and to slow down turn-off of GaN power transistor926. The source910of transistor904can be connected to source928of GaN power transistor926, while a voltage at gate906of transistor904is modulated in order to adjust the drive capability of the transistor904. In various embodiments, inductance L of inductance920can vary because of manufacturing variations. Circuit900can compensate for the variations of the value of inductance L. For example, if value of inductance L decrease, the signal developed across inductance920decreases as well, however this signal will be adequate to provide a feedback into the transistor904since the value of L×dI/dt of the GaN power transistor has decreased also.

In some embodiments, the turn-off dI/dt control can control a voltage spike across the driver as well as across drain-source of the power transistor926. The turn-off dI/dt control can mitigate these spikes irrespective of the value of the inductance L. For example, if value of inductance L decrease, then turn-off dI/dt control system can mitigate higher dI/dt. The turn-off dI/dt control can mitigate the voltage spikes so long as L×dI/dt turns on the feedback loop which includes impedance element916, diode912and impedance element914. In various embodiments, diode912can provide feedback of the positive voltage across the bondwire inductance920(i.e., node930being positive relative to node932). In this way, the turn-off dI/dt control system can prevent voltage ringing being feedback into the system, which can cause high frequency oscillation. It will be understood by those skilled in the art that the described turn-off dI/dt control system and circuit can be utilized in any power conversion circuit including a power transistor, including, but not limited t, GaN and/or silicon power transistors when a bondwire inductance920is available.

Gate Driver Circuit with Hysteresis

FIG.10illustrates schematic of a gate driver circuit1000with hysteresis according to an embodiment of the disclosure. Circuit1000can be used within circuit200to provide a gate driving with hysteresis technique that can be utilized to drive the GaN power transistor202. Circuit1000can include a GaN power transistor1024with a source1030, a gate1026and a drain1028. Circuit1000can include a rail1020that is configured to receive PWM signal1011. When PWM signal1011is high, it can turn on Transistor1010, which can start charging the gate1026of the GaN power transistor1024. A source1012of Transistor1010can be connected to the rail1020which is connected to the input PWM signal1011. A Zener diode1018can be connected to the gate1014of Transistor1010to clamp a voltage at the gate1014of Transistor1010. The gate of the GaN power transistor1024can be connected to a feedback and hysteresis circuit1050. The feedback and hysteresis circuit can include a resistor divider formed by resistors1052,1054and1056, and a transistor1070. A comparator1094can have its first input1096connected to an output1049of the resistor divider formed by resistors1052,1054and1056. Comparator1094can monitor a voltage at the gate of the GaN power transistor1024through the resistor divider. When gate of the GaN power transistor1024is low, a drain1016of Transistor1010is low, thus Transistor1010can turn on and charge the gate of the GaN power transistor1024. The voltage at the gate1026of the GaN power transistor goes high when it is charged.

Comparator1094can detect a high state of the gate of the GaN power transistor1024by comparing a voltage at its first input1096and a reference voltage Vrefat node1077. When the voltage at the first input1096goes high, the comparator1094switches and its output1098can go high. Output1098can then turn on transistor1005through buffer1015. Transistor1005can be connected to gate1006of PMOS transistor1004through resistor1092. When transistor1005turns on, a voltage at gate1006of a PMOS transistor1004goes low, turning on PMOS transistor1004. A source1002of PMOS transistor1004can be connected to the rail1020and a drain1008can be connected to a gate1014of transistor1010. A Zener diode1022can be connected to the gate1006of PMOS transistor1004to clamp its gate voltage and prevent damage to its gate. When PMOS transistor1004turns on, it can turn off Transistor1010. Thus, the gate of the GaN power transistor can stay at a high state. If the voltage at the gate of the GaN power transistor drops due to leakage through parasitic elements, the comparator1094can turn back on due to hysteresis and turn Transistor1010back on and charge the gate of the GaN power transistor.

Circuit1000can enable use of PWM signals with wide range of voltage variations, for example from 5 V to 30 V, by utilizing a pull-up transistor1010. When pull-up transistor1010is introduced into circuit1000, its gate1014can be controlled by utilizing the feedback and hysteresis circuit1050. Circuit1000can include a buffer1019which can control a gate1080of transistor1086and a gate1076of transistor1070. When the gate of GaN power transistor1024is in high state, an inverted output1017of the comparator1094is in high state. The inverted output1017drives gate1080of transistor1086through buffer1019and turns transistor1086off, which can allow a voltage at drain1082, which is connected to resistor1090, to move up towards a voltage at a rail1020to enable turn-off of transistor1010. At the same time, transistor1005can turn on, resulting in a turn off of the transistor1004. Transistors1032,1060, and1042in combination with Zener diode1040form a clamping circuit for the gate1026of the GaN power transistor1024in order to prevent the gate voltage from exceeding its safe operating region. Circuit1000enables driving of the gate of the GaN power transistor1024at relatively low PWM voltages, while enabling the driving of the gate of the GaN power transistor1024at relatively high PWM voltages as well.

FIG.11illustrates a graph1100showing voltages at various nodes within circuit1000. Graph1102shows PWM signal going high. Graph1104shows comparator input voltage at first input1096going high. Graph1106shows comparator output1098voltage going high. Graph1108shows the voltage at the gate of the GaN power transistor1024going high.

In various embodiments, hysteresis can be implemented, for example, within the comparator1094itself. The comparator can have hysteresis, or the comparator may use two different levels of reference voltages. In some embodiments, the gate driver circuit with hysteresis can control the pull-up transistor1010transistor in various ways. In some embodiments, the gate driver with hysteresis can function without having the gate clamping circuit which includes transistors1032,1060, and1042. The gate driver circuit with hysteresis can function with or without the clamping circuit. In various embodiments, gate driver with hysteresis can be used in numerous gate driver applications. In addition, gate driver with hysteresis circuit may be used as a voltage regulator as illustrated inFIG.12.

FIG.12illustrates schematic of a voltage regulator1200in accordance with an embodiment of the disclosure. Voltage regulator1200can regulate a gate voltage of the transistor1010of circuit1000. The drain1016may be connected to a capacitor1220and a load1218. Resistors1208and1210can form a resistor divider arranged to provide feedback signal. The feedback signal can be generated at node1206that feeds into an input of a comparator1204. Comparator1204can have hysteresis. Comparator1204can compare the voltage at node1206to a reference voltage Vref and provide a voltage at node1227to a controller circuit1202. The controller circuit1202can regulate a gate voltage of the transistor1010.

FIG.13illustrates an integrated GaN power device1300according to an embodiment of the disclosure. As shown inFIG.13, integrated GaN power device1300can use a TO-247package in order to integrate the gate driver IC112and the integrated GaN power transistor114. The integrated GaN power device1300can include a source terminal1302, a drain terminal1304and a PWM terminal1306. The integrated GaN power device1300can be a compatible replacement for a power MOSFET in a TO-247package and its driving circuits.

FIG.14Aillustrates an integrated GaN power device1400A according to an embodiment of the disclosure. As shown inFIG.14A, integrated GaN power device1400A can use a TO-247or TO-leadless (TOLL) package in order to integrate the gate driver IC112and the GaN power transistor114. In the illustrated embodiment, the integrated GaN power device1400A can include a source terminal1404, a drain terminal1402, a PWM terminal1408and kelvin source1406. In some embodiments, the integrated GaN power device1400A may not include a kelvin source and may use a three-terminal TO-247package or a three-terminal TOLL package. In various embodiments, the integrated GaN power device1400A can be a compatible replacement for a power MOSFET in a three-terminal or a four-terminal TO-247package and its driving circuits. In numerous embodiments, the integrated GaN power device1400A can be a compatible replacement for a power MOSFET in a three-terminal or a four-terminal TOLL package and its driving circuits.FIG.14Billustrates an integrated GaN power device1400B in a four-terminal TO-247package according to an embodiment of the disclosure.FIG.14Cillustrates an integrated GaN power device1400C in a TOLL package according to an embodiment of the disclosure.

Although integrated power devices with energy harvesting gate drivers are described and illustrated herein with respect to one particular configuration of GaN integrated power device, embodiments of the disclosure are suitable for use with other configurations of GaN devices and non-GaN devices. For example, any semiconductor device can be used with embodiments of the disclosure. In some instances, embodiments of the disclosure are particularly well suited for use with silicon and other compound semiconductor devices.

For simplicity, various internal components, such as the details of the substrate, various lead frame, and other components of integrated GaN power device100(seeFIG.1) are not shown in the figures.

In the foregoing specification, embodiments of the disclosure have been described with reference to numerous specific details that can vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the disclosure, and what is intended by the applicants to be the scope of the disclosure, is the literal and equivalent scope of the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. The specific details of particular embodiments can be combined in any suitable manner without departing from the spirit and scope of embodiments of the disclosure.

Additionally, spatially relative terms, such as “bottom or “top” and the like can be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as a “bottom” surface can then be oriented “above” other elements or features. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Terms “and,” “or,” and “an/or,” as used herein, may include a variety of meanings that also is expected to depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, the term “at least one of” if used to associate a list, such as A, B, or C, can be interpreted to mean any combination of A, B, and/or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

Reference throughout this specification to “one example,” “an example,” “certain examples,” or “exemplary implementation” means that a particular feature, structure, or characteristic described in connection with the feature and/or example may be included in at least one feature and/or example of claimed subject matter. Thus, the appearances of the phrase “in one example,” “an example,” “in certain examples,” “in certain implementations,” or other like phrases in various places throughout this specification are not necessarily all referring to the same feature, example, and/or limitation. Furthermore, the particular features, structures, or characteristics may be combined in one or more examples and/or features.

In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of appended claims, and equivalents thereof.