Patent ID: 12211774

DETAILED DESCRIPTION

Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package. In one or more embodiments, the inactive leads provide additional stabilization during assembly, such as during die attach and wire bond processing.

FIG.1Ashows an isometric view of a semiconductor package10in accordance with one embodiment. The semiconductor package10is a chip-on-lead (COL) semiconductor package.FIG.1Bis a bottom view of the semiconductor package10, andFIG.1Cis a side view of the semiconductor package10.

The semiconductor package10includes an upper surface12a, a lower surface12b, and side surfaces12c. The semiconductor package10includes a plurality of leads14having inner portions16a(FIG.4C) that support a semiconductor die or chip18and outer portions16bthat extend to the side surfaces12cof the semiconductor package10.

The semiconductor die18is made from semiconductor material, such as silicon, and includes an active surface integrating one or more electrical components, such as integrated circuits. The active surface of the semiconductor die18includes conductive bond pads that are electrically connected to one or more of the electrical components.

The semiconductor die18is coupled to the inner portions16aof the plurality of leads14by a material configured to hold the semiconductor die18in place during assembly. In one embodiment, the semiconductor die18is coupled to the inner portions16aof the plurality of leads14by an adhesive material, such as glue, paste, tape and the like. In other embodiments, the semiconductor die18is coupled to a die pad (not shown) that supports the semiconductor die and the plurality of leads are located around and spaced apart from the die pad as is well known in the art.

The plurality of leads14may be symmetrically arranged about one or more axes and may be symmetrically arranged about an axis of the semiconductor die18. The plurality of leads14includes both active leads14aand inactive leads14b.

Although the semiconductor die18is coupled to both the active leads14aand the inactive leads14bfor support, the active surface of the semiconductor die18is electrically coupled only to the active leads14a. In particular, the bond pads of the semiconductor die18are electrically coupled to surfaces of the active leads14aby conductive wires20, respectively. For example, a first end22of a conductive wire20is coupled to a bond pad of the semiconductor die18, and a second end24of the conductive wire20is coupled to a first surface of the active lead14a.

As previously mentioned, the inactive leads14bof the plurality of leads14are not electrically coupled to the active surface of the semiconductor die18. Thus, the active leads14aare electrically coupled to the integrated circuits of the active surface of the semiconductor die18, while the inactive leads14bare electrically decoupled from the integrated circuits of the active surface of the semiconductor die18.

In other embodiments, the active surface of the semiconductor die18may be electrically coupled to the active leads14aby other techniques, such as flip chip as is well known in the art. In such an embodiment, the semiconductor die is flipped over and faces the leads and conductive bumps are located between the active leads and the bond pads of the semiconductor die.

A package body30covers the semiconductor die18and the conductive wires20and portions of the leads14. The package body30is an insulating material, such as an encapsulation material, that protects the electrical components of the semiconductor die and conductive wires from damage, such as corrosion, physical damage, moisture damage, or other causes of damage to electrical devices and materials. In some embodiment, the package body30is at least one of a polymer, silicone, resin, polyimide, and epoxy. The package body30is shown inFIG.1Aas transparent so that inner details of the semiconductor package10can be readily seen. The package body is, however, typically made of an opaque material.

With reference toFIG.1B, the active leads14ahave second surfaces that are exposed from the package body30at the lower surface12bof the semiconductor package10to form lands. Remaining portions of the active leads14aare covered by the package body30. The inactive leads14bare not exposed from the package body30at the lower surface12bof the semiconductor package10as best shown inFIG.1B. Rather, the package body30covers the inactive leads14bat the lower surface.

With reference toFIG.1C, both the inactive leads14band the active leads14ahave surfaces that are exposed at side surfaces12cof the semiconductor package10. The surfaces of the inactive leads14band the active leads14amay be flush with a surface of the package body30. The surfaces of the active leads14aextend along the respective side surface12cof the semiconductor package10to the lower surface12bof the semiconductor package10, while the surfaces of the inactive leads14bdo not extend to the lower surface12bof the semiconductor package10. That is, the package body30is between the exposed surfaces of the inactive leads14band the lower surface12bof the semiconductor package10. As previously mentioned, the package body30covers surfaces of the inactive leads14bat the lower surface12bof the semiconductor package10so that surfaces of the inactive leads14bare not exposed at the lower surface12bof the semiconductor package10.

As best shown inFIG.1C, thicknesses of the active leads14aand inactive leads14bare different from each other. In at least one embodiment, the inactive leads14bhave a thickness that is about one half, such as between 40% to 60%, the thickness of the outer portions of the active leads14a. As will be explained in more detail below, the inactive leads14bprovide stability during assembly of the semiconductor package10. In at least one embodiment, the inactive leads14band the active leads14aprovide suitable support for the semiconductor die18during wire bonding.

The number and combination of active leads14amay be different than is shown. Any number or combination of active leads14amay be selected, including active leads being located along two sides, such as opposing sides, or along only one side of the semiconductor package. In general, which leads14are to be active leads14ais determined by the application for the semiconductor package, typically based on customer specifications.

The active leads14ahave first and second thicknesses. The first thickness is at the inner portions16aof the active leads14aand the second thickness is at the outer portions16bof the active leads14a, which is best shown inFIG.4F. The first thickness is less than the second thickness. In some embodiments, the first thickness is between 40% and 60%, and in one embodiment about 50%, the second thickness. As previously mentioned, the lower surfaces of the outer portions16bof the active leads14aform lands for coupling the semiconductor package to another device.

The inactive leads14bhave a constant thickness, which may be the same thickness as the first thickness of the active leads. The outer portions16bof the inactive leads14bhave the first thickness, while the outer portions16bof the active leads14ahave the second thickness, which is greater than the first thickness. The package body30covers the lower surfaces of the inactive leads14band the portions of the active leads14ahaving the first thicknesses.

FIG.2Ashows an upper surface of a leadframe array34used for forming semiconductor packages, such as the semiconductor package10ofFIGS.1A-1C, according one embodiment.FIG.2Bshows a lower surface of the leadframe array34ofFIG.2A. The leadframe array34is made of conductive material, such as a metal. In at least one embodiment the leadframe array34is made of copper or a copper alloy. The leadframe34is shown with stippling to provide clarity as to which portions form the leadframe and which portions do not form the leadframe, and to show depth. In particular, the bottom view of the leadframe34includes thicker stippling to indicate thicker portions of the leadframe34.

The leadframe array34includes a plurality of individual leadframes34aarranged in columns and rows, each for forming a respective semiconductor package. The leads14of adjacent individual leadframes34aare coupled together by connecting bars36. In at least one embodiment, the leads14are arranged in a symmetrical arrangement about one or more axes, such as a central axis, of the individual leadframes34a.

During assembly, the leads14of adjacent individual leadframes34aprovide suitable stabilization of any active leads during the wire bonding process. Active leads of adjacent individual leadframes may oppose each other at the connecting bars36or an inactive lead may oppose an active lead. Furthermore, by providing more leads than are used as active leads in the final semiconductor package, the assembly of the package is improved. In particular, the inactive leads provide stability during the wire bonding process.

FIGS.3A and3Bshow close up views of the upper and lower surfaces, respectively, of an individual leadframe34a. With reference toFIG.3A, the upper surfaces of the leads14, including active leads and inactive leads, of the individual leadframe34are in a same plane as indicated by the same volume of stippling. With reference toFIG.3B, the lower surfaces of the inactive leads14band first portions of the active leads14aof the individual leadframe34are in a same plane as indicated by the same volume of stippling. Outer portions of the active leads14aare in a different plane as indicated by the increased volume of stippling. In particular, the outer portions of the active leads14aare thicker and have surfaces in a plane that extends out of the page, relative to the inner portions of the active leads14a.

FIGS.4A and4Billustrate various stages of manufacturing the leadframe array34ofFIGS.2A and2B. The leadframe array34ofFIG.4Aalready has leads, however, the inactive leads have not yet been formed.

As shown inFIG.4A, outers portions of the active leads14athat are to form lands31of the active leads14aare covered with a material so that the rest of the leads may be etched. In one embodiment, the active leads14aare plated with one or more metal materials, such as Au, Ag, Ni/Pd/Ag, Ni/Pd/Au—Ag alloy, or Ni/Pd/Au/Ag, which thereby form the lands of the active leads14a. In another embodiment, the outer portions of the active leads14aare patterned with light sensitive materials as is well known in the art.

With reference toFIG.4B, lower surfaces of the leads14, of both the active leads14aand inactive leads14b, are etched using standard semiconductor etching techniques. In particular, inner portions of the active leads14are etched that do not include plated metal material or light sensitive material and entire surfaces of the inactive leads14bare etched. The etching occurs to a depth of about one half the original thickness of the leadframe, also referred to as half etched. In one embodiment, the etching occurs to about 50% the original thicknesses of the leads. In other embodiments, the etching occurs to between 40% to 60% of the original thicknesses of the leads. After etching, each individual leadframe34aof the leadframe array34includes an active lead14aand an inactive lead14bas shown inFIG.1B.

FIGS.4C-4Fillustrate various stages of assembling the semiconductor package ofFIG.1Ain accordance with one embodiment. In particular, as shown inFIG.4C, semiconductor dice18are coupled to inner portions16aof the leads14. In particular, the semiconductor dice18are coupled to inner portions16aof the active leads14aand inactive leads14b. By providing both active leads14aand inactive leads14bfor supporting each semiconductor die18, the supporting structure for the semiconductor die is improved. Further, the symmetrical arrangement of the plurality of leads provides improved support for the semiconductor dice18during dice attachment. Additionally, leads of adjacent individual leadframes34aare coupled together by connecting bars36and are able to provide improved support to each other during dice attachment.

With reference toFIG.4D, the semiconductor dice18are electrically coupled to the active leads14ain a bonding process. In particular, first ends22of conductive wires20are coupled to bond pads of the semiconductor die18, and second ends24of the conductive wires20are coupled to outer portions16bof the active leads14a. The bonding process of coupling the conductive wires20may involve heat and ultrasonic energy. Although only one conductive wire is shown for each individual leadframe, it is to be understood that conductive wires are being coupled to other active leads and bond pads of the semiconductor dice not shown inFIG.4D.

During the bonding process of coupling the conductive wires20to the active leads14a, all of the leads14, both the active leads14aand the inactive leads14b, provide stabilization. For instance, while ultrasonic energy is being applied during the bonding process, the stability of the leadframe that is created in part by the inactive leads, eliminates or reduces any bouncing effect the ultrasonic energy may introduce. In that regard, stronger bonds may be provided between the active leads14aand the conductive wires20.

As previously mentioned the quantity and location of active leads may be identified by a particular application for the semiconductor package, such as by a customer. However, the number of inactive leads may be selected by the amount of stabilization that is desired during manufacturing.

As shown inFIG.4E, a package body30is formed on the semiconductor dice18, the conductive wires20, and portions of the plurality of leads14to form semiconductor packages. In at least one embodiment, the package body30is formed in a mold. In particular, the leadframe array34is placed in a mold and molding material, such as a resin, is introduced into the mold, as is well known in the art. In at least one embodiment, the molding material hardens in a curing step to form the package body30.

As shown inFIG.4E, the package body30forms over upper and lower surfaces of the inactive leads14b. Outer portions16bof the active leads14aremain exposed from the package body30to form lands, while inner portions16aof the active leads14aat the lower surface are covered by the package body30.

The assembly process further includes separating the semiconductor packages into individual packages10. In particular, the dicing occurs at locations as indicated by the arrows as shown inFIG.4Eand separates the connected semiconductor packages into individual semiconductor packages10as shown inFIG.4F. The dicing cuts through the connecting bars36, the package body30, and the leads to separate the semiconductor packages10. The dicing method may be any method suitable to separate the semiconductor packages, including sawing and laser. Although not shown, the connected semiconductor packages may be secured to a support structure, such as tape, during the dicing step, as is well known in the art.

Upon dicing side surfaces of both the active and inactive leads14a,14bare exposed at the side surface of the individual semiconductor packages as shown inFIG.1C.

The stages of manufacturing and assembly may occur in a different order as well. For instance, the leads may be half etched after the semiconductor die is coupled to the leadframe. Further, although the embodiments shown in the figures show the leads supporting the semiconductor, in other embodiments, the leadframe package includes a die pad that supports the semiconductor die.

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.