Patent ID: 12228768

Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. The discussion of elements inFIGS.1A-1D and2-45with the same annotations applies to each other, unless mentioned otherwise.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.

As used herein, the term “high refractive index” refers to a refractive index that is equal to or greater than 2.0.

As used herein, the term “low refractive index” refers to a refractive index that is equal to or less than 2.0.

In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.

Optical fibers can have a relatively large core in comparison to waveguides on Si-PICs, resulting in a larger optical mode field than the mode associated with the waveguides on the Si-PICs. Direct optical coupling between the optical fibers and the waveguides can result in high optical coupling losses and high optical signal losses due to the optical mode size mismatch and the refractive index mismatch between the optical fibers and the waveguides. To reduce such mismatches, optical coupling devices (also referred to as “couplers”) are used to optically couple the optical fibers to the waveguides on the Si-PICs. The couplers serve as optical mode size converters to improve optical coupling efficiency between the optical fibers and the waveguides.

The waveguides and couplers can include semiconductor and/or dielectric materials with a high refractive index disposed within dielectric materials with a low refractive index. The high refractive index materials can include Si, silicon nitride (SiN), aluminum oxide (Al2O3), hafnium oxide (HfO2), or other suitable high refractive index materials within the scope of the present disclosure. The low refractive index materials can include silicon oxide (SiO2) or other suitable low refractive index materials within the scope of the present disclosure.

One of the challenges of fabricating the waveguides and couplers is the patterning of the high refractive index materials to achieve minimal edge roughness (e.g., roughness less than 1 nm) and/or line width variation (e.g., variation less than 1 nm) in the patterned features of the waveguides and couplers. For example, fabricating SiN based waveguides and/or couplers with thick SiN layers (e.g., thickness of about 200 nm or greater or thickness between about 300 nm to about 1000 nm) to achieve the optimal device performance is challenging because depositing a high quality thick SiN layer leads to bowing of the substrate along with the SiN layer, which makes the patterning of the deposited SiN layer challenging. Deposition of the thick SiN layers can also lead to cracks in the substrate of the SiN based waveguides and/or couplers due to accumulated stress in the SiN layers. Further, patterning the thick SiN layers requires complex processing steps, such as multiple coating, patterning, etching, and/or polishing processes, which makes it difficult to accurately control the line width, side wall slope, and/or edge roughness of the patterned SiN features. The difficulty in process control also makes it difficult to pattern the SiN based waveguides and/or couplers with small features, such as sharp tapered features and small gaps in the waveguides and/or couplers.

The performance of the waveguides and couplers depends on the patterning process control. For example, the optical loss and/or power consumption in the waveguides can be high if the edge roughness and/or line width uniformity of the patterned features of the waveguides are poorly controlled during the fabrication process. Thus, the challenges of patterning the high refractive index materials used for the waveguides and couplers limits the minimum optical mode size mismatch and the maximum optical coupling efficiency that can be achieved between the optical fibers and the waveguides and couplers.

The present disclosure provides examples methods of fabricating waveguides and couplers with improved process control in patterning high refractive index materials. In some embodiments, the example methods use a patterned layer of a relatively lower refractive index material (e.g., SiO2) as a template to pattern thick layers of the high refractive index materials. The low refractive index material used for the patterned template layer has a less complex patterning process and a better critical dimension control of the patterned features than the high refractive index materials. The use of the patterned template layer with the low refractive index materials eliminates the complex deposition, etching, and polishing processes required for patterning thick layers of high refractive index materials. As a result, the use of the patterned template layer mitigates the stress related damages to the substrate of the waveguides and couplers and reduces the complexities of fabricating waveguides and couplers with thick layers of the high refractive index materials.

Further, the use of the patterned template layer provides better control over the edge roughness, surface roughness, and/or line width uniformity of the features patterned with the high refractive index materials. The smoother surfaces lead to low optical losses in the waveguides and couplers. In some embodiments, the example methods can reduce the surface roughness to about 1 nm or less, which leads to propagation loss in Si-based waveguides to be about 1 dB/cm or less and in SiN-based waveguides to about 0.2 dB/cm or less.

FIG.1Aillustrates a cross-sectional view of an optical device100with a waveguide102and an optical coupling device104(also referred to as a “grating coupler104”), according to some embodiments.

Optical device100can include a substrate106, a thermal oxide layer108disposed on substrate106, a patterned template layer110disposed on thermal oxide layer108, and a cladding layer112disposed on patterned template layer110. Substrate106can be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, other suitable semiconductor materials, and a combination thereof. Thermal oxide layer108can include a thermally grown SiO2, a thermally grown oxide of the material of substrate106, or other suitable thermally grown oxide materials with a low refractive index. Patterned template layer110can include a chemically deposited SiO2or other suitable chemically deposited oxide materials with a low refractive index. The chemically deposited SiO2or other oxide materials can be deposited by a chemical vapor deposition (CVD) process, a low pressure CVD (LPCVD) process, or a plasma enhanced CVD (PECVD) process and can be referred to as “CVD oxide materials” or “non-thermal oxide materials.” The CVD oxide materials are included in patterned template layer110instead of thermally grown oxide materials because CVD oxide materials are easier and faster to etch during the fabrication of patterned template layer110than the thermally grown oxide materials. Cladding layer112can include a material similar to the material of patterned template layer110or other suitable dielectric materials with a low refractive index.

Waveguide102and grating coupler104can be disposed on thermal oxide layer108. In some embodiments, waveguide102can include a rib portion102A disposed within patterned template layer110and a slab portion102B disposed on rib portion102A and within cladding layer112. Both rib portion102A and slab portion102B can include a semiconductor or a dielectric material with a high refractive index, such as Si, SiN, Al2O3, HfO2, and other suitable materials with a high refractive index. Rib portion102A can have a thickness T1along a Z-axis and a width W1along an X-axis, and slab portion102B can have a thickness T2along a Z-axis and a width W2along an X-axis. Width W2is greater than width W1. A ratio of W2:W1can range from about 1:1 to about 100:1 for optimal performance of waveguide102(e.g., for negligible propagation loss). In some embodiments, thickness T1can range from about 200 nm to about 2000 nm or can be other suitable dimensions and thickness T2can range from about 1 nm to about 1000 nm or can be other suitable dimensions.

In some embodiments, waveguide102can have an isometric view as shown inFIG.1B. The cross-sectional view of waveguide102inFIG.1Acan be along line A-A ofFIG.1B.FIG.1Billustrates waveguide102disposed on thermal oxide layer108, which is disposed on substrate106.FIG.1Bfurther illustrates rib portion102A disposed within patterned template layer110and slab portion102B disposed on rib portion102A. Cladding layer112on slab portion102B is not shown inFIG.1Bfor simplicity. In some embodiments, waveguide102can further include a tapered portion102C in physical contact with rib portion102A and disposed within patterned template layer110and under slab portion102B, as shown inFIG.1B. Tapered portion102C can be a material similar to rib portion102A. The base of tapered portion102C can be in physical contact with a side of rib portion102A, as shown inFIG.1B, and the width and thickness of the base of tapered portion102C can be equal to width W1and thickness T1of rib portion102A, as shown inFIG.1C.FIG.1Cillustrates a cross-sectional view along line B-B (i.e., along the base of tapered portion102C) ofFIG.1B. The tip of tapered portion102C can be spaced apart from the edge of slab portion102B by a distance D1, as shown inFIG.1B. In some embodiments, distance D1can range from about 1 nm to about 10 μm for optimal performance of waveguide102with tapered portion102C. The tip of tapered portion102C can have a thickness T1and a width W5, as shown inFIG.1D.FIG.1Dillustrates a cross-sectional view along line C-C (i.e., along the tip of tapered portion102C) ofFIG.1B. In some embodiments, a ratio of W1:W5can range from about 1:1 to about 10:1 for optimal performance of waveguide102with tapered portion102C.

Referring back toFIG.1A, grating coupler104can be configured to optically couple waveguide102to an optical fiber (not shown) in a Si-PIC. In some embodiments, grating coupler104can be a dual layered grating coupler with an array of bottom grating lines104A disposed with patterned template layer110and an array of top grating lines104B disposed within cladding layer112. Patterned template layer110can electrically isolate bottom grating lines104A from each other and cladding layer112can electrically isolate top grating lines104A from each other. In some embodiments, the array of top grating lines104B can be non-overlapping with the array of bottom grating lines, as shown inFIG.1A. In some embodiments, one or more of top grating lines104B can partially or fully overlap one or more of bottom grating lines (not shown). The arrays of bottom and top grating lines104A-104B can include a semiconductor or a dielectric material with a high refractive index, such as Si, SiN, Al2O3, HfO2, and other suitable materials with a high refractive index. In some embodiments, the arrays of bottom and top grating lines104A-104B can have a material similar to or different from each other.

Each of bottom grating lines104A can have a thickness T3along a Z-axis and a width W3along an X-axis, and each of top grating lines104B can have a thickness T4along a Z-axis and a width W4along an X-axis. Thickness T3can be greater than thickness T4, and widths W3-W4can be equal to or different from each other. A ratio of T3:T4can range from about 1:4 to about 4:1 for optimal performance of grating coupler104. In some embodiments, thickness T3can range from about 50 nm to about 1000 nm or can be other suitable dimensions and thickness T4can range from about 1 nm to about 1000 nm or can be other suitable dimensions. In some embodiments, thickness T3-T4can be substantially equal to thickness T1-T2, respectively.

FIG.2is a flow diagram of an example method200for fabricating optical device100with waveguide102and grating coupler104, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.2will be described with reference to the example fabrication process for forming optical device100with waveguide102and grating coupler104as illustrated inFIGS.3-8. The operations can be performed in a different order or not performed depending on specific applications. Method200may not produce a complete optical device100. Accordingly, additional processes can be provided before, during, and after method200, and that some other processes may only be briefly described herein. Elements inFIGS.3-8with the same annotations as elements inFIGS.1A-1Dare described above.

In operation205, a thermal oxide layer is formed on a substrate. For example, as shown inFIG.3, thermal oxide layer108is formed on substrate106. In some embodiments, substrate can include Si and a thermal SiO2layer108can be formed on substrate106. In some embodiments, the formation of thermal oxide layer108can include forming a thermal oxide layer with a thickness of about 10 nm to about 10 μm on substrate106by annealing substrate106at a temperature of about 600° C. to about 1100° C. in an oxygen ambient or in a steam and oxygen ambient. During the annealing process (also referred to as “thermal oxidation process”), a top portion of substrate106is oxidized to form thermal oxide layer108.

In some embodiments, instead of forming thermal oxide layer108on substrate106, an SOI substrate can be provided, followed by the removal of top Si layer of the SOI substrate to expose the buried oxide layer of the SOI substrate (not shown). The buried oxide layer can be thermal oxide layer108.

Referring toFIG.2, in operation210, a patterned template layer is formed on the thermal oxide layer. For example, as described withFIGS.3-4, patterned template layer110with trenches414-416are formed on thermal oxide layer108. In subsequent processing, trench414defines the structure and dimensions of rib portion102A of waveguide102and trenches416define the structure and dimensions of the array of bottom grating lines104A of grating coupler104. The dimensions of trench414can depend on the dimensions of rib portion102A and the dimension of trenches416can depend on the dimensions of bottom grating lines104A. Height H1and width W6of trench414can be substantially equal to thickness T1and width W1, respectively, of rib portion102A. Height H2and width W7of trenches416can be substantially equal to thickness T3and width W3, respectively, of bottom grating lines104A.

The formation of patterned template layer110can include sequential operations of (i) depositing an oxide layer110* on thermal oxide layer108, as shown inFIG.3, and (ii) patterning oxide layer110* to form trenches414-416, as shown inFIG.4. The deposition of oxide layer110* can include depositing a layer of SiO2or other suitable oxide materials with a low refractive index on thermal oxide layer108using a CVD process, an LPCVD process, a PECVD, or other suitable chemical deposition processes. In some embodiments, oxide layer110* can be deposited using a precursor, such as tetraethylorthosilicate (TEOS), in a CVD process at a temperature of about 650° C. to about 750° C. or in an LPCVD process at a temperature of about 400° C. to about 750° C.

The patterning of oxide layer110* can include using a lithography process and dry or wet etch processes. In some embodiments, the dry etch process can include using etchants having a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), or combinations thereof. In some embodiments, the wet etch process can include etching in diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), or combinations thereof. The processes included in the patterning of oxide layer110* can be adequately controlled to achieve trenches414-416with well-defined sidewall profiles (e.g., substantially linear profiles) and minimal surface roughness (e.g., less than 1 nm).

Referring toFIG.2, in operation215, a waveguide and a grating coupler are formed on the patterned template layer. For example, as described withFIGS.5-7, waveguide102and grating coupler104are formed on patterned template layer110. The formation of waveguide102and grating coupler104can include sequential operations of (i) depositing a high refractive index material layer518on patterned template layer110to form a layer portion518A within trenches414-416and a layer portion518B on the top surface of patterned template layer110, as shown inFIG.5, (ii) performing a chemical mechanical polishing (CMP) process on layer portion518B to form a polished layer620extending out of trenches414-416, as shown inFIG.6, and (iii) patterning polished layer620to form slab portion102B and top grating lines104B, as shown inFIG.7.

Layer portion518A disposed within trench414(FIG.4) forms rib portion102A of waveguide102, and layer portion518A disposed within trenches416(FIG.4) forms the array of bottom grating lines104A of grating coupler104. As a result, the well-defined sidewall profiles (e.g., substantially linear profiles) of trenches414-416with minimal surface roughness (e.g., less than 1 nm) are transferred to the sidewall profiles of rib portion102A and bottom grating lines104A. Thus, with the use of patterned template layer110, rib portion102A and bottom grating lines104A can be formed with thick (e.g., greater than 200 nm) layers of high refractive index materials in a process that is less complicated than other methods of forming waveguides and/or grating couplers with thick layers of high refractive index materials. Also, with the use of patterned template layer110, rib portion102A and bottom grating lines104A can be formed with smoother surfaces (e.g., surface roughness less than 1 nm) and better defined sidewall profiles than other waveguides and/or grating couplers formed without a patterned template layer.

The deposition of layer518can include depositing a layer of high refractive index material (e.g., SiN) with a thickness of about 200 nm to about 1000 nm in an LPCVD process at a high temperature ranging from about 600° C. to about 800° C., in a PECVD process at a low temperature ranging from about 100° C. to about 400° C., or in other suitable deposition processes for high refractive index materials. The layer of high refractive index material deposited in the LPCVD process can have a lower concentration of hydrogen bonds compared to that deposited in the PECVD process. The high temperature of the LPCVD process helps to break and remove the hydrogen bonds in layer518. The presence of hydrogen bonds negatively impacts the optical quality of the layer of high refractive index material in layer518. As a result, in some embodiments, layer518can be deposited using the LPCVD process instead of the PECVD process to form the layer of high refractive index material with a higher optical quality. On the other hand, in some embodiments, layer518can be deposited using the PECVD process instead of the LPCVD process if the high temperature processing of the LPCVD process is not compatible with the other processes included in the formation of optical device100.

The CMP process can include polishing layer portion518B to form polished layer620with a thickness less than about 300 nm (e.g., about 50 nm, about 100 nm, or about 150 nm). If the thickness of polished layer620is greater than about 300 nm, the subsequent patterning process can require complex processes due to the challenges of patterning high refractive index material with a thickness greater than 300 nm, as discussed above. The patterning of polished layer620can include using a lithography process and dry or wet etch processes. In some embodiments, the dry etch process can include using etchants having a fluorine-containing gas (e.g., HF, F2). In some embodiments, the wet etch process can include etching in phosphoric acid (H3PO4).

Referring toFIG.2, in operation220, a cladding layer is formed on the waveguide and grating coupler. For example, as shown inFIG.8, cladding layer112is formed on waveguide102and grating coupler104. The formation of cladding layer112can include depositing a layer of SiO2or other suitable oxide materials with a low refractive index using a CVD process, an LPCVD process, a PECVD, or other suitable chemical deposition processes, followed by a CMP process. In some embodiments, the a layer of SiO2can be deposited using a precursor, such as tetraethylorthosilicate (TEOS), in a CVD process at a temperature of about 650° C. to about 750° C. or in an LPCVD process at a temperature of about 400° C. to about 750° C.

In some embodiments, instead of or after performing operation220on the structure ofFIG.7, operations210-215can be repeated after operation215to form stacks of waveguide102and grating coupler104on the structure ofFIG.7.

FIG.9is a flow diagram of an example method900for fabricating optical device100with waveguide102and grating coupler104, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.9will be described with reference to the example fabrication process for forming optical device100with waveguide102and grating coupler104as illustrated inFIGS.10-17. The operations can be performed in a different order or not performed depending on specific applications. Method900may not produce a complete optical device100. Accordingly, additional processes can be provided before, during, and after method900, and that some other processes may only be briefly described herein. Elements inFIGS.10-17with the same annotations as elements inFIGS.1A-1D and3-8are described above.

In operation905, a thermal oxide layer is formed on a substrate. For example, as shown inFIG.10, thermal oxide layer108is formed on substrate106in an operation similar to operation205described with reference toFIG.3.

Referring toFIG.9, in operation910, a polish stop layer and a patterned template layer are formed on the thermal oxide layer. For example, as described withFIGS.10-13, a polish stop layer1022and patterned template layer110with trenches414-416are formed on thermal oxide layer108. The formation of polish stop layer1022and patterned template layer110can include sequential operations of (i) depositing oxide layer110* on thermal oxide layer108, as shown inFIG.10, (ii) depositing a polish stop layer1022on oxide layer110*, as shown inFIG.10, (iii) patterning polish stop layer1022to form the structure ofFIG.11, (iv) forming a patterned masking layer1224(e.g., photoresist layer) with openings414*-416* on the structure ofFIG.11to form the structure ofFIG.12, (v) etching oxide layer110* through openings414*-416* to form respective trenches414-416, as shown inFIG.13.

The deposition and etching of oxide layer110* can be similar to the deposition and etching processes described in operation210. The deposition of polish stop layer1022can include depositing a layer of metallic material or insulating material different from the material of oxide layer110* using a CVD process or other suitable chemical deposition processes. The thickness of polish stop layer1022depends on thicknesses T2and T4of subsequently-formed slab portion102B and top grating lines104B. Polish stop layer1022can control the thickness T2and T4during formation of slab portion102B and top grating lines104B, which is described in further detail below. The patterning of polish stop layer1022can include using a lithography process and dry or wet etch processes.

Referring toFIG.9, in operation915, a waveguide and a grating coupler are formed on the patterned template layer. For example, as described withFIGS.14-17, waveguide102and grating coupler104are formed on patterned template layer110. The formation of waveguide102and grating coupler104can include sequential operations of (i) depositing high refractive index material layer518on the structure ofFIG.13, as shown inFIG.14, (ii) performing a chemical mechanical polishing (CMP) process on layer portion518B to form a polished layer620extending out of trenches414-416, as shown inFIG.15, (iii) removing polish stop layer1022to form the structure ofFIG.16, and (iv) patterning polished layer620to form slab portion102B and top grating lines104B, as shown inFIG.17.

The deposition of layer518and the patterning of polished layer620can be similar to the deposition and patterning processes described in operation215. The CMP process can include polishing layer portion518B until a top surface of polished layer620is substantially coplanar with a top surface of polish stop layer1022. The removal of polish stop layer1022after the CMP process can include a dry or wet etch process for removing metallic materials or insulation materials.

Referring toFIG.9, in operation920, a cladding layer is formed on the waveguide and grating coupler. For example, as shown inFIG.17, cladding layer112is formed on waveguide102and grating coupler104in an operation similar to operation220described with reference toFIG.8.

In some embodiments, instead of or after performing operation920on the structure ofFIG.17, operations910-915can be repeated after operation915to form stacks of waveguide102and grating coupler104.

In some embodiments, optical device100can include an etch stop layer1926(as shown inFIG.21) between thermal oxide layer108and patterned template layer110to protect thermal oxide layer108during formation of patterned template layer110.FIG.18is a flow diagram of an example method1800for fabricating optical device100with etch stop layer1926, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.18will be described with reference to the example fabrication process for forming optical device100with etch stop layer1926as illustrated inFIGS.19-21. The operations can be performed in a different order or not performed depending on specific applications. Method1800may not produce a complete optical device100. Accordingly, additional processes can be provided before, during, and after method1800, and that some other processes may only be briefly described herein. Elements inFIGS.19-21with the same annotations as elements inFIGS.1A-1D,3-8, and10-17are described above.

In operation1805, a thermal oxide layer is formed on a substrate. For example, as shown inFIG.19, thermal oxide layer108is formed on substrate106in an operation similar to operation205described with reference toFIG.3.

Referring toFIG.18, in operation1810, an etch stop layer is formed on the thermal oxide layer. For example, as shown inFIG.19, etch stop layer1926is formed on thermal oxide layer108. The formation of etch stop layer1926can include depositing a layer of insulating material, such as silicon nitride (SiNx), silicon oxynitride (SiON), silicon carbide (SiC), nitrogen doped silicon carbide (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), and combinations thereof using a CVD process or other suitable deposition processes for insulation materials.

Referring toFIG.18, in operation1815, a patterned template layer is formed on the etch stop layer. For example, as shown inFIG.20, patterned template layer110is formed on etch stop layer1926in an operation similar to operation210described with reference toFIGS.3-4.

Referring toFIG.18, in operation1820, a waveguide and a grating coupler are formed on the patterned template layer. For example, as shown inFIG.21, waveguide102and grating coupler104are formed on patterned template layer110in an operation similar to operation215described with reference toFIGS.5-7.

Referring toFIG.18, in operation1825, a cladding layer is formed on the waveguide and grating coupler. For example, as shown inFIG.21, cladding layer112is formed on waveguide102and grating coupler104in an operation similar to operation220described with reference toFIG.8.

In some embodiments, instead of or after performing operation1825, operations1815-1820can be repeated after operation1820to form stacks of waveguide102and grating coupler104.

FIG.22illustrates a cross-sectional view of an optical device2200with waveguide102and an optical coupling device2204(also referred to as a “grating coupler2204”), according to some embodiments.

Optical device2200can include substrate106, thermal oxide layer108disposed on substrate106, patterned template layer110disposed on thermal oxide layer108, and cladding layer112disposed on patterned template layer110. Waveguide102and grating coupler2204can be disposed on thermal oxide layer108. Grating coupler2204can be configured to optically couple waveguide102to an optical fiber (not shown) in a Si-PIC. In some embodiments, grating coupler2204can be a dual layered grating coupler with an array of bottom grating lines2204A disposed with patterned template layer110and an array of top grating lines2204B disposed within cladding layer112. The arrays of bottom and top grating lines2204A-2204B can be vertically spaced apart from each other by a distance D2and can be electrically isolated from each other by patterned template layer110. Patterned template layer110can also electrically isolate bottom grating lines2204A from each other and cladding layer112can electrically isolate top grating lines2204A from each other. The arrays of bottom and top grating lines104A-104B can include a semiconductor or a dielectric material with a high refractive index, such as Si, SiN, Al2O3, HfO2, and other suitable materials with a high refractive index. In some embodiments, the arrays of bottom and top grating lines104A-104B can have a material similar to or different from each other. In some embodiments, the materials of waveguide102and top grating lines104B can be similar to each other and different from the material of bottom grating lines104A.

Each of bottom grating lines2204A can have a thickness T8along a Z-axis and a width W8along an X-axis, and each of top grating lines2204B can have a thickness T9along a Z-axis and a width W9along an X-axis. Thickness T8can be greater than thickness T9and widths W3-W4can be equal to or different from each other. In some embodiments, thickness T8can range from about 50 nm to about 500 nm or can be other suitable dimensions and thickness T9can range from about 100 nm to about 1000 nm or can be other suitable dimensions.

Optical device2200can further include an image sensor2228and an isolation device2230. In some embodiments, image sensor2228can include a substrate layer2232disposed on thermal oxide layer108, a germanium (Ge) layer2234disposed partly within substrate layer2232and partly within patterned template layer110, a capping layer2236disposed on Ge layer2234, an n-type doped region2238and a p-type doped region2240disposed partly within Ge layer2234and partly within capping layer2236, and a passivation layer2242disposed on patterned template layer110. In some embodiments, capping layer2236can include Si and passivation layer2242can include a material similar to the material of waveguide102and/or top grating lines104B. In some embodiments, isolation device2230can include an n-type doped region2248and a p-type doped region2250disposed within patterned template layer110. The dopant concentrations of doped regions2248-2250can be substantially to the dopant concentrations of doped regions2238-2240, respectively. Optical device2200can further include contact structures2244-2246disposed on doped regions2238-2240and2248-2250, and via structures2252-2254disposed on contact structures2244-2246.

FIG.23is a flow diagram of an example method2300for fabricating optical device2200, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.23will be described with reference to the example fabrication process for forming optical device2200as illustrated inFIGS.24-36. The operations can be performed in a different order or not performed depending on specific applications. Method2300may not produce a complete optical device2200. Accordingly, additional processes can be provided before, during, and after method2300, and that some other processes may only be briefly described herein. Elements inFIGS.24-36with the same annotations as elements inFIGS.1A-1D,3-8,10-17, and22are described above.

In operation2305, a thermal oxide layer is formed on a substrate. For example, as shown inFIG.24, thermal oxide layer108is formed on substrate106in an operation similar to operation205described with reference toFIG.3.

Referring toFIG.23, in operation2310, a patterned semiconductor layer with an array of bottom grating lines of a grating coupler is formed on the thermal oxide layer. For example, as described withFIGS.24-25, a patterned semiconductor layer2456with array of bottom grating lines2204A is formed on thermal oxide layer108. The formation of patterned semiconductor layer2456can include sequential operations of (i) depositing a semiconductor layer2456* on thermal oxide layer108, as shown inFIG.24, and (ii) patterning semiconductor layer2456* using a lithography process and dry or wet etch process to form the structure ofFIG.25. After the formation of patterned semiconductor layer2456, oxide layer110* can be formed on the structure ofFIG.25, as shown inFIG.26

In some embodiments, an SOI substrate can be provided instead of forming the structure ofFIG.24and the silicon layer of the SOI substrate can be patterned as patterned semiconductor layer2456to form the structure ofFIG.25. In some embodiments, patterned semiconductor layer2456has (i) a first portion that forms the array of bottom grating lines2204A, (ii) a second portion that forms a sacrificial structure2258, which defines rib portion102A of waveguide102in subsequent processing, (iii) a third portion that forms substrate layer2232of image sensor2228, and (iv) a fourth portion that forms a semiconductor structure2260, which are doped in subsequent processing to form doped regions2248-2250.

Referring toFIG.23, in operation2315, an image sensor is formed on a portion of the patterned semiconductor layer. For example, as described withFIGS.26-30, image sensor228is formed on a portion of patterned semiconductor layer2456. The formation of image sensor2228can include sequential operations of (i) forming a trench2262in substrate layer2232by selectively etching through an opening in a masking layer2264(e.g., a photoresist layer), as shown inFIG.26, (ii) epitaxially growing Ge layer2234in trench2262, as shown inFIG.27, (iii) performing a CMP process on Ge layer2234to substantially coplanarize top surface of Ge layer2234with top surface of oxide layer110*, as shown inFIG.28, (iv) selectively depositing capping layer2236on Ge layer2234, as shown inFIG.28, (v) depositing an oxide layer110**, similar in material to oxide layer110*, on the structure ofFIG.28, as shown inFIG.29, (vi) forming n-type doped region2238in Ge layer2234and capping layer2236by ion implanting n-type dopants through an opening2966in a masking layer2968(e.g., a photoresist layer), as shown inFIG.29, (vii) forming p-type doped region2240in Ge layer2234and capping layer2236by ion implanting p-type dopants through an opening3070in a masking layer3072(e.g., a photoresist layer), as shown inFIG.30, and (viii) depositing passivation layer2242on oxide layer110**, as shown inFIG.31.

In some embodiments, doped region2248can be formed in semiconductor structure2260by ion implanting n-type dopants through an opening2967in masking layer2968during the formation of n-type doped region2238, as shown inFIG.29. Similarly, doped region2250can be formed in semiconductor structure2260by ion implanting p-type dopants through an opening3071in masking layer3072during the formation of p-type doped region2240, as shown inFIG.30.

Referring toFIG.23, in operation2320, a waveguide and an array of top grating lines of the grating coupler are formed on another portion of the patterned semiconductor layer. For example, as described withFIGS.31-34, waveguide102and array of top grating lines2204B are formed on another portion of the patterned semiconductor layer2256. The formation of waveguide102can include sequential operations of (i) forming a trench3274by selectively etching passivation layer2236, oxide layers110*-110**, and sacrificial structure2258through an opening in a masking layer3276(e.g., a photoresist layer), as shown inFIG.32, (ii) depositing a high refractive index material layer3318on the structure ofFIG.32after removing masking layer3276to form a layer portion3318A within trench3274and a layer portion3318B extending out of trench3274, as shown inFIG.33, (iii) performing a CMP process on layer portion3318B to form a polished layer3420, as shown inFIG.34, and (iv) patterning polished layer3420and passivation layer2236to form slab portion102B on patterned template layer110, as shown inFIG.35. During the patterning of polished layer3420and passivation layer2236, slab portion102B can be formed with one portion of polished layer3420and passivation layer2236and top grating lines2204B can be formed with another portion of polished layer3420and passivation layer2236, as shown inFIG.35.

Layer portion3318A disposed within trench3274(FIG.32) forms rib portion102A of waveguide102. As a result, the well-defined sidewall profiles (e.g., substantially linear profiles) of trench3274with minimal surface roughness (e.g., less than 1 nm) are transferred to the sidewall profiles of rib portion102A. The deposition of layer3318can include depositing a layer of high refractive index material (e.g., SiN) with a thickness of about 300 nm to about 1000 nm in a low temperature (e.g., temperature at or below about 400° C.) deposition process, such as a PECVD process at a low temperature ranging from about 100° C. to about 400° C., or in other suitable low temperature deposition processes for high refractive index materials. The deposition of high refractive index material layer3318is performed in low temperature deposition processes because the structures of image sensor2228(e.g., Ge layer334or doped regions2238-2240) and/or isolation device2230are susceptible to thermal damages at high temperatures (e.g., temperatures greater than 400° C.).

The CMP process can include polishing layer portion3318B to form polished layer3420with a thickness less than about 300 nm (e.g., about 50 nm, about 100 nm, or about 150 nm). If the thickness of polished layer3420is greater than about 300 nm, the subsequent patterning process can require complex processes due to the challenges of patterning high refractive index material with a thickness greater than 200 nm, as discussed above. The patterning of polished layer3420and passivation layer2236can include using a lithography process and dry or wet etch processes. In some embodiments, the dry etch process can include using etchants having a fluorine-containing gas (e.g., HF, F2). In some embodiments, the wet etch process can include etching in phosphoric acid (H3PO4).

Referring toFIG.23, in operation2325, a cladding layer is formed on the waveguide, grating coupler, and image sensor. For example, as shown inFIG.35, cladding layer112is formed on the structure ofFIG.35, as shown inFIG.36in an operation similar to operation220described with reference toFIG.8.

Referring toFIG.23, in operation2330, contact structures and via structures are formed within the cladding layer. For example, as shown inFIG.36, contact structures2244-2246and via structures2252-2254are formed within cladding layer112. In some embodiments, contact structures2244-2246can be formed at the same time and via structures2252-2254can be formed on contact structures2244-2246at the same time. Contact structures2244-2246and via structures2252-2254can include metallic materials.

FIG.37is a flow diagram of an example method3700for fabricating optical device2200with waveguide102and grating coupler2204that has materials with higher optical quality and lower optical propagation loss than that formed in method2300, according to some embodiments. In method2300, due to the low temperature deposition of high refractive index material layer3318, which subsequently-formed waveguide102and top grating lines2204B, the optical quality of the high refractive index material may not be adequate for the optimal performance of waveguide102and grating coupler2204. To improve the optical quality, high refractive index material layer3318can be formed in a high temperature (e.g., temperature above about 400° C.) deposition process. However, since image sensor2228and/or isolation device2230are susceptible to thermal damages at high temperatures, method3700can be used, instead of method2300, to form optical device2200with waveguide102and grating coupler2204that has materials with higher optical quality. In contrast to method2300, method3700forms image sensor2228and isolation device2230after the formation of waveguide102and top grating lines2204B to prevent thermal damages to image sensor2228and/or isolation.

For illustrative purposes, the operations illustrated inFIG.37will be described with reference to the example fabrication process for forming optical device2200as illustrated inFIGS.24-36. The operations can be performed in a different order or not performed depending on specific applications. Method2300may not produce a complete optical device2200. Accordingly, additional processes can be provided before, during, and after method2300, and that some other processes may only be briefly described herein. Elements inFIGS.24-36with the same annotations as elements inFIGS.1A-1D,3-8,10-17,22, and24-36are described above.

In operation3705, a thermal oxide layer is formed on a substrate. For example, as shown inFIG.38, thermal oxide layer108is formed on substrate106in an operation similar to operation205described with reference toFIG.3.

Referring toFIG.37, in operation3710, a patterned semiconductor layer with an array of bottom grating lines of a grating coupler is formed on the thermal oxide layer. For example, as shown inFIG.38, a patterned semiconductor layer2456with array of bottom grating lines2204A is formed on thermal oxide layer108in an operation similar to operation2310described with reference toFIGS.24-25.

Referring toFIG.37, in operation3715, a waveguide and an array of top grating lines of the grating coupler are formed on a portion of the patterned semiconductor layer. For example, as described withFIGS.39-41, waveguide102and array of top grating lines2204B are formed on a portion of the patterned semiconductor layer2256. The formation of waveguide102can include sequential operations of (i) forming trench3274by selectively etching oxide layer110* and sacrificial structure2258through an opening in masking layer, as shown inFIG.39, (ii) depositing high refractive index material layer3318in a high temperature deposition process, such as a LPCVD process at a high temperature ranging from about 700° C. to about 900° C., or in other suitable high temperature deposition processes for high refractive index materials, (iii) performing CMP process in an operation similar to operation2320described with reference toFIG.34to form a polished layer3420, as shown inFIG.40, and (iv) patterning polished layer3420in an operation similar to operation2320described with reference toFIG.35to form slab portion102B, as shown inFIG.41. During the patterning of polished layer3420, slab portion102B can be formed with one portion of polished layer3420and top grating lines2204B can be formed with another portion of polished layer3420, as shown inFIG.41. In some embodiments, as shown inFIG.41, a dielectric layer4278can be deposited on the structure ofFIG.40to protect waveguide102and top grating lines2204B from subsequent processing. Dielectric layer4278can include a material similar to oxide layer110and/or cladding layer112.

Referring toFIG.37, in operation3720, an image sensor is formed on another portion of the patterned semiconductor layer. For example, as described withFIGS.43-44, image sensor228is formed on another portion of patterned semiconductor layer2456. The formation of image sensor2228can include sequential operations of (i) forming Ge layer2234and capping layer2236, as shown inFIG.43, in an operation similar to operation2315described with reference toFIGS.26-28, and (ii) forming doped regions2238-2240, as shown inFIG.44, in an operation similar to operation2315described with reference toFIGS.29-30. In some embodiments, doped regions2248-2250, as shown inFIG.44, can be formed in an operation similar to operation2315described with reference toFIGS.29-30.

Referring toFIG.37, in operation3725, a cladding layer is formed on the waveguide, grating coupler, and image sensor. For example, as shown inFIG.44, cladding layer112is formed on the structure ofFIG.43, as shown inFIG.44in an operation similar to operation2325described with reference toFIG.36.

Referring toFIG.37, in operation3730, contact structures and via structures are formed within the cladding layer. For example, as shown inFIG.44, contact structures2244-2246and via structures2252-2254are formed within cladding layer112in an operation similar to operation2330described with reference toFIG.36.

The present disclosure provides examples methods (e.g., methods200,900,1800,2300, and3700) of fabricating waveguides (e.g., waveguide102) and couplers (e.g., grating couplers104and2204) with improved process control in patterning high refractive index materials. In some embodiments, the example methods use a patterned layer of a relatively lower refractive index material (e.g., Si or SiO2) as a template to pattern thick layers of the high refractive index materials. The low refractive index material used for the patterned template layer (e.g., patterned template layer110) has a less complex patterning process and a better critical dimension control of the patterned features than high refractive index materials. The use of the patterned template layer with the low refractive index materials eliminates the complex deposition, etching, and polishing processes required for patterning thick layers of high refractive index materials. As a result, the use of the patterned template layer mitigates the stress related damages to the substrate of the waveguides and couplers and reduces the complexities of fabricating waveguides and couplers with thick layers of the high refractive index materials.

Further, the use of the patterned template layer provides better control over the edge roughness, surface roughness, and/or line width uniformity of the features patterned with the high refractive index materials. The smoother surfaces lead to low optical losses in the waveguides and couplers. In some embodiments, the example methods can reduce the surface roughness to about 1 nm or less, which leads to propagation loss in Si-based waveguides to be about 1 dB/cm or less and in SiN-based waveguides to about 0.2 dB/cm or less.

In some embodiments, a method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.

In some embodiments, a method includes forming a thermal oxide layer on a substrate and forming a patterned semiconductor layer on the thermal oxide layer. A first portion of the patterned semiconductor layer forms a bottom grating line of a coupler, a second portion of the patterned semiconductor layer forms a sacrificial layer, and a third portion of the patterned semiconductor layer forms a substrate layer. The method further includes forming an image sensor on the substrate layer, forming a patterned template layer with a trench on the thermal oxide layer, forming a rib portion of a waveguide within the trench, wherein the image sensor is adjacent to the waveguide, forming a slab portion of the waveguide and a top grating line of the coupler on a top surface of the patterned template layer, and depositing a cladding layer on the slab portion, the top grating line, and the image sensor.

In some embodiments, an optical device includes a substrate, a thermal oxide layer disposed on the substrate, a non-thermal oxide layer disposed on the thermal oxide layer, and a waveguide disposed on the thermal oxide layer. The waveguide includes a rib portion and tapered portion disposed within the non-thermal oxide layer and a slab portion disposed on the rib portion and the tapered portion. The optical device further includes a grating coupler disposed on the thermal oxide layer and a cladding layer disposed on the waveguide and grating coupler. The grating coupler includes a bottom grating line disposed within the non-thermal oxide layer and a top grating line disposed on a top surface of the non-thermal oxide layer. The top and bottom grating lines are non-overlapping with respect to each other.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.