Patent ID: 12218662

DETAILED DESCRIPTION

Aspects of the present disclosure relate to line drivers with high over-voltage protection. A line driver circuit fabricated using a CMOS technology should be able to operate at supply voltages that are typically substantially higher than the junction breakdown voltages of the P-channel MOS (PMOS) and N-channel MOS (NMOS) transistors disposed in the line driver circuit. For example, for USB 2.0, the line voltage is defined as 3.3±10% volts (V). This results in a supply voltage that may reach nearly 3.63V under some conditions. Such a supply voltage is substantially higher than the typical breakdown voltage (e.g., 1.5V) of PMOS and NMOS transistors fabricated using a 5 nm CMOS process.

A typical line driver circuit includes a number of PMOS and NMOS transistors adapted to drive an output load. However, as the breakdown voltages of such transistors continue to scale down at a faster rate than the corresponding supply voltages, the transistors disposed in a typical line driver may be exposed to excessively high junction voltages that cause the transistors to degrade and become inoperable over time.

Embodiments of the present disclosure overcome the aforementioned challenges by forming, in part, a line driver having disposed therein a multitude of PMOS and NMOS transistors. A number of the PMOS and NMOS transistors receive level-converted voltages as well as reference voltages. Among technical advantages of the present disclosure are a line driver circuit having PMOS and NMOS transistors that are not subject to junction voltages exceeding their respective breakdown voltages, and that may be readily adapted to operate at different supply voltages.

FIG.1is a transistor schematic diagram of a line driver circuit100, in accordance with one embodiment of the present disclosure. Line driver100is shown as including, in part, a first stage160and a second stage170. Line driver100is also shown as including, in part, a first voltage level converter140, a second voltage level converter145, and a third voltage level converter150. First stage160is shown as including a cascade of PMOS transistors102,104,106,108, and a cascade of NMOS transistors112,114,116,118. Second stage170is shown as including a diode-connected PMOS transistor170, and a pair of diode-connected NMOS transistors125,130.

PMOS transistor102has a source terminal receiving the supply voltage Vp, and a gate terminal receiving the output voltage V1of voltage level converter140. PMOS transistor104has a source terminal coupled to the drain terminal of PMOS transistor102, and a gate terminal receiving a first reference voltage VREF1. PMOS transistor106has a source terminal coupled to the drain terminal of PMOS transistor104and a gate terminal receiving the output voltage V2of level converter145. PMOS transistor108has a source terminal coupled to the drain terminal of PMOS transistor106, a gate terminal receiving the output voltage V2of level converter145, and a drain terminal coupled to output terminal OUT that is terminated with a resistor164that typically has a resistance of 50 Ohms.

NMOS transistor112has a drain terminal coupled to the output terminal OUT, and a gate terminal receiving the output voltage V3of voltage level converter150. NMOS transistor114has a drain terminal coupled to the source terminal of transistor112, and a gate terminal receiving the output voltage V3of voltage level converter150. NMOS transistor116has a drain terminal coupled to the source terminal of transistor114and a gate terminal receiving a second reference voltage VREF2. NMOS transistor118has a drain terminal coupled to the source terminal of transistor116, a gate terminal receiving the data input signal DataIN, and a source terminal coupled to the ground voltage. Data input signal DataINis also applied to the input terminals of voltage level converters (alternatively referred to herein as level converters)140,145and150.

PMOS transistor120of second stage170has a source terminal coupled to the source terminal of transistor108, and gate and drain terminals coupled to the output terminal OUT. NMOS transistor125of second stage170has gate and drain terminals that are coupled to the output terminal OUT, and a source terminal coupled to the drain and gate terminals of NMOS transistor130. The source terminal of NMOS transistor130is coupled to the source terminal of transistor112.

As is described herein, line driver circuit100is adapted to receive input data DATAINand generate, in response, an output voltage at the output terminal OUT that varies between the ground voltage and supply voltage Vp. Line driver circuit100maintains the gate-to-source and gate-to-drain voltages of the transistors disposed therein below their respective junction breakdown voltages. The junction breakdown voltage of the NMOS and PMOS transistors disposed in line driver circuit100is alternatively referred to as BV. Supply voltage Vp of line driver circuit100typically has a value that may range from 3.3 volts to 3.63 volts.

When the input data DATAINis at a logic low level (i.e., 0 volts), voltage converter140generates a voltage V1having a value defined by (Vp-BVX). Voltage BVX is an intermediate voltage that is smaller than voltage BV by an offset to ensure that the transistors in the line driver circuit do not enter the breakdown region. For example, in one embodiment, if BV is 1.5 volts, BVX may be set to 1.2 volts. Because V1is at (Vp-BVX), PMOS transistor102is in a conductive (on) state, thereby causing the drain of PMOS transistor104to receive supply voltage Vp. Reference voltage VREF1also has a value defined by (Vp-BVX). Accordingly, when input data DATAINis at a logic low level, PMOS transistor104is also on, thus causing the drain of PMOS transistor104to be pulled up to the supply voltage Vp. Therefore, the gate-to-source and the gate-to-drain voltages of PMOS transistors102and104do not exceed their respective junction breakdown voltages.

When the input data DATAINis at a logic low level, voltage converter145generates a voltage V2having a value defined by (VP-BVX). Therefore, because the source of transistor106is at Vp volts, and the gate of transistor106is at (Vp-BVX) volts, the gate-to-source and gate-to-drain voltages of PMOS transistor106do not exceed their respective junction breakdown voltages. Furthermore, because the gate terminals of transistors106and108are coupled to one another, and further, because the source of transistor108receives the supply voltage Vp, the gate-to-source and gate-to-drain voltages of PMOS transistor106do not exceed their respective junction breakdown voltages. Consequently, when the input data DATAINapplied to line driver100is at a logic low level, the gate-to-source and gate-to-drain voltages of PMOS transistors102,1046,106, and108are below their respective junction breakdown voltages. Moreover, as described above, when the input data DATAINis at a logic low level, the output voltage OUT receives voltage Vp. In one example, when Vp is set to 3.63 volts and BV is at 1.2 volts, the gate voltages of transistors M1, M2, M3and M4receive 2.43 volts, and the source of transistors M1, M2, M3and M4receive 3.63 volts.

When the input data DATAINis at a logic low level, voltage converter150generates a voltage V3having an intermediate value defined by nearly (2BVX-Voffset). Voltage Voffset is selected to provide a margin of safety to prevent the transistors from entering into a breakdown region. For example, in one embodiment, when VP and BVX are at 3.63 and 1.2 volts respectively, Voffset may be selected to have a value to 0.3 volts, thereby causing V2to be set to 2.1 volts.

Therefore, when the input data DATAINis at a logic low level, the gate terminals of transistors112and114is at (2BVX-Voffset) volts. Because (2BVX-Voffset) is smaller than VP, both transistors112and114are off. To ensure that the gate-to-source voltage of transistor112does not exceed the breakdown voltage, diode-connected transistors125and130pull the source of transistor112to two transistor threshold voltages below the VP voltage, namely to (Vp-2VT), where VT is the threshold voltage of the transistors; this ensures that transistor112, while remaining off, does not enter the breakdown region. For example, in one embodiment, if voltages VP, and Vt are 3.63 volts and 0.5 volts respectively, the source of transistor114is at 2.63 volts.

Because, the drain of transistor114receives the voltage (Vp-2VT), and its gate receives voltage (2BVX-Voffset), the voltage at source of transistor116is one threshold voltage below its gate voltage. For example, if voltages VP, (2BVX-Voffset), and Vt are at 3.63 volts, 2.1 volts, and 0.5 volts respectively, and the source of transistor114is at 2.63 volts, then the source of transistor114is nearly at 1.63 volts.

The reference voltage VREF2applied to the gate of transistor116is at BVX volts, therefore the voltage at source of transistor116is one threshold voltage below its gate voltage. For the example described above, and assuming VREF2is 1.2 volts, then the source of transistor116is at 0.7 volts. Transistor118is off when input data DATAINis at a logic low-level. However, because the drain terminal of transistor18is coupled to the source of transistor116and the source terminal of transistor18receives the ground potential, transistor118is also inhibited from entering a breakdown region. For the example provided above, the drain terminal of transistor118is at 0.7 volts. Therefore, in accordance with embodiments of the present disclosure, all PMOS and NMOS transistors in line driver circuit100operate safely in the normal active region of operation and without entering the breakdown region.

When the input data DATAINapplied to line driver circuit100is at a logic high level (i.e., 1.2 volts), NMOS transistor118is on, thereby causing the drain of NMOS transistor118to be pulled to the ground voltage. Because voltage VREF2is larger than VT, transistor116is also on, thus pulling the drain voltage of transistor116to the ground voltage. When the input data DATAINis at a logic high level, voltage V3generated by level converter150is defined by BVX. Accordingly, both transistors114and112are also on, thereby pulling the output voltage OUT to the ground potential. Accordingly, all NMOS transistors118,116,114and112of line driver100operate safely in the normal active region of operation and without entering the breakdown region. Resistor162is a current limiting resistor that ensure the gate-to-source diode of transistor102is not forward biased.

When the input data DATAINis at a logic high level, voltage V1generated by voltage converter140is at supply voltage Vp. Therefore, because both the gate and source terminals of PMOS transistor102are at voltage Vp, PMOS transistor102is off. However, the charges (equivalent to the full Vp voltage) that were present at the drain node of PMOS transistor102when DATAINwas previously at a logic low level, get redistributed between the remaining cascade of PMOS transistors due to voltages (Vp-BVX) and (VP-2BVX+Voffset) applied respectively to the gate terminals of transistors104,106, and108. For example, the source of PMOS transistor104remains one threshold voltage above voltage (Vp-BVX), and the source of PMOS transistor106remains one threshold voltage above voltage (VP-2BVX+Voffset). Diode-connected PMOS transistor120raises the voltage at the source of PMOS transistor108by threshold voltage above the output pad voltage, which is 0 when DATAINis at a logic high level.

In one example, when Vp is 3.63 volts, BVX is 1.2 volts, and Voffset is 0.3 volts, as was also described above, reference voltage VREF1is at 2.43 volts and voltage V2generated by the level converter145is at 1.53 volts. This causes the sources of transistor104to be at 2.73 volt, and the source of transistor108to be at 1.83 volts. The source of transistor108is maintained above the ground potential by the threshold voltage of diode-connected transistor120. Accordingly, because the gate-to-source and gate-to-drain voltages of each of PMOS transistors102,104,106and108is less than BV, PMOS transistors102,104,106and108are inhibited from entering the breakdown region.

FIG.2illustrates an example set of processes700used during the design, verification, and fabrication of an article of manufacture such as an integrated circuit to transform and verify design data and instructions that represent the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term ‘EDA’ signifies the term ‘Electronic Design Automation.’ These processes start with the creation of a product idea710with information supplied by a designer, information which is transformed to create an article of manufacture that uses a set of EDA processes712. When the design is finalized, the design is taped-out734, which is when artwork (e.g., geometric patterns) for the integrated circuit is sent to a fabrication facility to manufacture the mask set, which is then used to manufacture the integrated circuit. After tape-out, a semiconductor die is fabricated736and packaging and assembly processes738are performed to produce the finished integrated circuit740.

Specifications for a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. A high-level of abstraction may be used to design circuits and systems, using a hardware description language (‘HDL’) such as VHDL, Verilog, System Verilog, SystemC, MyHDL or Open Vera. The HDL description can be transformed to a logic-level register transfer level (‘RTL’) description, a gate-level description, a layout-level description, or a mask-level description. Each lower abstraction level that is a less abstract description adds more useful detail into the design description, for example, more details for the modules that include the description. The lower levels of abstraction that are less abstract descriptions can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of abstraction language for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. Descriptions at each level of abstraction are enabled for use by the corresponding tools of that layer (e.g., a formal verification tool). A design process may use a sequence depicted inFIG.2. The processes described by be enabled by EDA products (or tools).

During system design714, functionality of an integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or lines of code), and reduction of costs, etc. Partitioning of the design into different types of modules or components can occur at this stage.

During logic design and functional verification716, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, the components of the circuit may be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification may use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components referred to as ‘emulators’ or ‘prototyping systems’ are used to speed up the functional verification.

During synthesis and design for test718, HDL code is transformed to a netlist. In some embodiments, a netlist may be a graph structure where edges of the graph structure represent components of a circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by an EDA product to verify that the integrated circuit, when manufactured, performs according to the specified design. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit may be tested to verify that the integrated circuit satisfies the requirements of the specification.

During netlist verification720, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning722, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing.

During layout or physical implementation724, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of the circuit components by multiple conductors) occurs, and the selection of cells from a library to enable specific logic functions can be performed. As used herein, the term ‘cell’ may specify a set of transistors, other components, and interconnections that provides a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flipflop or latch). As used herein, a circuit ‘block’ may refer to two or more cells. Both a cell and a circuit block can be referred to as a module or component and are enabled as both physical structures and in simulations. Parameters are specified for selected cells (based on ‘standard cells’) such as size and made accessible in a database for use by EDA products.

During analysis and extraction726, the circuit function is verified at the layout level, which permits refinement of the layout design. During physical verification728, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithographic constraints, and that circuitry function matches the HDL design specification. During resolution enhancement730, the geometry of the layout is transformed to improve how the circuit design is manufactured.

During tape-out, data is created to be used (after lithographic enhancements are applied if appropriate) for production of lithography masks. During mask data preparation732, the ‘tape-out’ data is used to produce lithography masks that are used to produce finished integrated circuits.

A storage subsystem of a computer system (such as computer system900ofFIG.6) may be used to store the programs and data structures that are used by some or all of the EDA products described herein, and products used for development of cells for the library and for physical and logical design that use the library.

FIG.3illustrates an example machine of a computer system900within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine may operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system900includes a processing device902, a main memory904(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), a static memory906(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device918, which communicate with each other via a bus930.

Processing device902represents one or more processors such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device902may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device902may be configured to execute instructions926for performing the operations and steps described herein.

The computer system900may further include a network interface device908to communicate over the network920. The computer system900also may include a video display unit910(e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device912(e.g., a keyboard), a cursor control device914(e.g., a mouse), a graphics processing unit922, a signal generation device916(e.g., a speaker), graphics processing unit922, video processing unit928, and audio processing unit932.

The data storage device918may include a machine-readable storage medium924(also known as a non-transitory computer-readable medium) on which is stored one or more sets of instructions926or software embodying any one or more of the methodologies or functions described herein. The instructions926may also reside, completely or at least partially, within the main memory904and/or within the processing device902during execution thereof by the computer system900, the main memory904and the processing device902also constituting machine-readable storage media.

In some implementations, the instructions926include instructions to implement functionality corresponding to the present disclosure. While the machine-readable storage medium924is shown in an example implementation to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processing device902to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

In the foregoing disclosure, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of implementations of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular tense, more than one element can be depicted in the figures and like elements are labeled with like numerals. The disclosure and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.