Patent ID: 12199581

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described.

FIG.1illustrates a simplified version of an envelope tracking power amplifier system10according to one embodiment of the present disclosure. The envelope tracking power amplifier system10includes transceiver circuitry12, an envelope tracking integrated circuit (ETIC)14coupled to the transceiver circuitry12, and radio frequency (RF) power amplifier circuitry16coupled to the ETIC14such that the ETIC is coupled between the transceiver circuitry12and the RF power amplifier circuitry16. In addition to other functions that are not directly pertinent to the present disclosure and thus not discussed herein, the transceiver circuitry12is configured to generate a time-variant target voltage signal Vtargetindicative of a power envelope of an RF input signal RFin, which is an RF signal to be amplified by the RF power amplifier circuitry16. The ETIC14is configured to produce a time-variant envelope tracking supply voltage Vccfor the RF power amplifier circuitry16based on the target voltage signal Vtargetsuch that the envelope tracking supply voltage Vcctracks the power envelope of the RF input signal RFin. The RF power amplifier circuitry16is configured to amplify the RF input signal RFinbased on the envelope tracking supply voltage Vccto provide an RF output signal RFout, which may then subsequently be transmitted from an antenna (not shown).

Those skilled in the art will appreciate that the RF power amplifier circuitry16may operate with improved efficiency and linearity when the envelope tracking supply voltage Vccaccurately tracks the power envelope of the RF input signal RFin. This is achieved when the envelope tracking supply voltage Vccis temporally aligned with the target voltage signal Vtarget. Temporal alignment between the envelope tracking supply voltage Vccand the target voltage signal may be complicated by the load presented by the RF power amplifier circuitry16to the ETIC14and stray inductances caused by signal lines (e.g., circuit board traces) located between the ETIC14and the RF power amplifier circuitry16.

To illustrate this,FIG.2shows a simplified equivalent circuit for the load presented to the ETIC14by the RF power amplifier circuitry16. An output inductance of the ETIC14is illustrated as LETIC, an inductance caused by circuit board traces between the ETIC14and the RF power amplifier circuitry16is illustrated as Ltrace, a capacitance of the RF power amplifier circuitry16as presented to the ETIC14is illustrated as CPA, and a resistance of the RF power amplifier circuitry16as presented to the ETIC14is illustrated as RPA. As discussed above, the ETIC provides the envelope tracking supply voltage Vccto the RF power amplifier circuitry16. Due to the load presented by the RF power amplifier circuitry16, a load current Iloadis also generated. The load current Iloadis based on the envelope tracking supply voltage Vcc. A transfer function H(s) can be calculated for the equivalent circuitry shown inFIG.2. A transfer function of a system (in the s-domain) can be expressed according to Equation 1:

H⁡(s)=N⁡(s)D⁡(s)(1)
where N(s) and D(s) are simple polynomials that define one or more zeros and one or more poles of the transfer function, respectively, and s=j2πƒ. The one or more zeros are the roots of the polynomial equation N(s) and can be determined by solving the equation N(s)=0. The order of the polynomial N(s) determines the number of zeros of the transfer function H(s). Each zero corresponds to a zero output of the transfer function H(s). The polynomial N(s) is a zero-order polynomial when N(s) represents a constant value, is a first-order polynomial when N(s)=1+b0s (where b0is a constant), is a second-order polynomial when N(s)=1+b0s+b1s2(where b1is a constant), and so on. When N(s) is a second-order polynomial, the transfer function H(s) is referred to herein as a second-order complex-zero transfer function.

In contrast to the zeros, the one or more poles are the roots of the polynomial D(s) and can be determined by solving the equation D(s)=0. The order of the polynomial D(s) determines the number of poles of the transfer function H(s). Each pole corresponds to an infinite output of the transfer function H(s). The polynomial D(s) is a zero-order polynomial when D(s) represents a constant value, is a first-order polynomial when D(s)=1+a0s (where a0is a constant), is a second-order polynomial when D(s)=1+a0s+a1s2(where a1is a constant), and so on. When D(s) is a second-order polynomial, the transfer function H(s) is referred to herein as a second-order complex-pole transfer function.

Turning back to the equivalent circuit shown inFIG.2, the transfer function H(s) of the equivalent circuit can be calculated according to Equation 2:

H⁡(s)=11+(LERPA)⁢s+(LE*CPA)⁢s2(2)
where LE=LETIC+Ltrace. The transfer function H(s) provided by the load presented by the RF power amplifier circuitry16has two complex poles that are complex conjugates, and thus is referred to as a second-order complex-pole transfer function. A graph of the transfer function H(s) over frequency is illustrated inFIG.3for given values LE=4 nH, CPA=250 pF, and RPA=6Ω. As shown, the complex pole pair causes peaking at around 141 MHz, and a steep decline thereafter. Ideally, this curve would remain flat throughout the entire bandwidth. Going back to the envelope tracking power amplifier system discussed with respect toFIG.1, the above means that the envelope tracking supply voltage Vccwill not accurately track the power envelope of the RF input signal RFinin some situations, which may lead to decreased performance and/or efficiency.

In an effort to solve the aforementioned issues,FIG.4illustrates an ETIC18according to one embodiment of the present disclosure. The ETIC18includes equalizer circuitry20, signal processing circuitry22coupled to the equalizer circuitry20, and a parallel amplifier24coupled to the signal processing circuitry22such that the signal processing circuitry22is coupled between the equalizer circuitry20and the parallel amplifier24. The equalizer circuitry20is configured to receive the target voltage signal Vtargetand provide an equalized target voltage signal Vte, which compensates for the poles in the transfer function introduced by the load of the RF power amplifier circuitry16discussed above. The details of how this is accomplished are discussed below.

The signal processing circuitry22may perform further signal processing on the equalized target voltage signal Vte, such as anti-aliasing or other digital signal processing, to provide a processed target voltage signal Vtp. The processed target voltage Vtpis provided to the parallel amplifier24, which amplifies a battery voltage Vbatbased on the processed target voltage signal Vtpto provide the envelope tracking supply voltage Vccto the RF power amplifier circuitry16. Notably, the ETIC14illustrated inFIG.4is simplified in order to more clearly illustrate the principles of the present disclosure. In practice, the ETIC14will include additional circuitry in order to effectively generate the envelope tracking supply voltage Vcc. Such additional circuitry is contemplated by the present disclosure but not shown to avoid obscuring the concepts described herein.

As discussed above, the equalizer circuitry18is provided to equalize the target voltage signal Vtargetto effectively cancel the transfer function H(s) provided by the load presented by the RF power amplifier circuitry16discussed above with respect toFIGS.2and3. To do so, the equalizer circuitry18should provide a transfer function equal to Equation 3:

H⁡(s)=A*(1+(LERPA)⁢s+(LE*CPA)⁢s2)(3)
where A is a constant value or gain. The above transfer function H(s) is a second-order polynomial in the numerator, and is therefore referred to as a second-order complex-zero transfer function. Notably, the numerator of the transfer function H(s) of Equation 3 effectively cancels the denominator of the transfer function H(s) of Equation 2. The transfer function H(s) of Equation 3 is graphed along with the transfer function H(s) of Equation 2 inFIG.5, where the solid line is the transfer function H(s) of Equation 3 and the dashed line is the transfer function H(s) of Equation 2 for given values LE=4 nH, CPA=250 pF, and RPA=6Ω. As shown, the transfer functions are essentially equal but opposite, thereby cancelling one another out and effectively resulting in a flat response across the entirety of the bandwidth. As discussed above, this is desirable so that the envelope tracking supply voltage Vcccan accurately track the power envelope of the RF input signal RFin, thereby allowing the RF power amplifier circuitry16to accurately and efficiently amplify the signal to provide the RF output signal RFout.

Conventional designs for equalizer circuitry capable of providing a second-order complex-zero transfer function such as the one shown in Equation 3 above are complex and consume a large amount of power. Accordingly, they are generally unsuitable for mobile devices or other applications in which power consumption is a design concern. Further, conventional designs may require a large number of components, thereby making them large and thus again unsuitable for mobile devices or other applications in which size is a design concern.

Accordingly,FIG.6shows equalizer circuitry20according to one embodiment of the present disclosure. Before diving into the details of the equalizer circuitry20, it is important to note that while the target voltage signal Vtargetis shown being provided to the equalizer circuitry20as a single-ended signal inFIGS.1and4, the target voltage signal Vtargetis actually generally provided from the transceiver circuitry12as a differential voltage including a target voltage signal Vtarget(p)and an inverted target voltage signal Vtarget(m), where the letter “p” refers to a “plus” target voltage and the letter “m” refers to a “minus” target voltage. Accordingly, the equalizer circuitry20is shown including a target voltage input26including a target voltage input node26P and an inverted target voltage input node26M. It is important that the target voltage signal Vtargetis provided as a differential signal in order for the equalizer circuitry to provide the desired second-order complex-zero transfer function discussed above using only two operational amplifiers.

The equalizer circuitry20includes a first operational amplifier OPA1and a second operational amplifier OPA2. The first operational amplifier OPA1includes a first inverting input node28, a first non-inverting input node30, and a first output node32. The first inverting input node28is coupled to the target voltage input node26P via a first resistor R1 and a first capacitor C1, which are coupled in parallel with one another. A second resistor R2 is coupled between the first inverting input node28and the first output node32. The first non-inverting input node30is coupled to ground. The second operational amplifier OPA2includes a second inverting input node34, a second non-inverting input node36, and a second output node38. The second inverting input node34is coupled to the first output node32via a second capacitor C2. Further, the second inverting input node34may be coupled to the inverted target voltage input node26M via a third resistor R3, and additionally may be coupled to the second output node38via a fourth resistor R4. The second non-inverting input node36is coupled to ground. The second output node38may be coupled to an equalized target voltage output40, and specifically to an equalized target voltage output node40P in the equalized target voltage output40. While the equalized target voltage output40is shown as a single-ended output including only the equalized target voltage output node40P, it may also include an inverted equalized target voltage output node (not shown) in some embodiments such that the equalized target voltage output40is a differential output as illustrated in additional embodiments below.

In operation, the first operational amplifier OPA1receives the target voltage signal Vtarget(p)and provides an intermediate signal Vi, which is based on the target voltage signal Vtarget(p). The second operational amplifier OPA2receives the intermediate signal Viand the inverted target voltage signal Vtarget(m)and provides an equalized target voltage signal Vteto the equalized target voltage output40. A transfer function between the target voltage input node26P and the equalized target voltage output node40P can be provided as in Equation 4:

H⁡(s)=R⁢4R⁢3*[1+R⁢3*(R⁢2R⁢1)*C⁢2*s*(1+R⁢1*C⁢1*s)](4)
Those skilled in the art will appreciate that the transfer function H (s) of Equation 4 is a second-order complex-zero transfer function. By appropriately adjusting the values of R1-R4, C1, and C2, the equalizer circuitry20may be designed to effectively cancel the load presented by the RF power amplifier circuitry16to the ETIC18, thereby allowing the envelope tracking supply voltage Vccto accurately track the power envelope of the RF input signal RFinover a wide bandwidth and improving the performance of the RF power amplifier circuitry16. Further, the values of the R1-R4, C1, and C2 may be chosen such that the zeros in the transfer function H(s) are complex conjugates. Notably, the second-order complex-zero transfer function is achieved using only two operational amplifiers. This is accomplished by exploiting the differential nature of the target voltage signal Vtarget. Providing a second-order complex-zero transfer function in such a simplified circuit topology results in a reduced footprint of the equalizer circuitry as well as improved efficiency and bandwidth. While not shown, any of R1-R4, C1, and C2 may be adjustable components that are adjusted by control circuitry that is internal or external to the equalizer circuitry20and may be adjusted based on one or more operational conditions of the equalizer circuitry the ETIC18, and/or the RF power amplifier circuitry16.

FIG.7shows the equalizer circuitry20according to an additional embodiment of the present disclosure. The equalizer circuitry20shown inFIG.7is substantially similar to that shown inFIG.6, but further includes a third capacitor C3 coupled between the target voltage input node26P and the second inverting input node34. The equalizer circuitry20inFIG.7will operate similarly to that shown inFIG.6, but will provide a transfer function between the target voltage input node26P and the equalized target voltage output node as in Equation 5:

H⁡(s)=R⁢4R⁢3*[1+(R⁢3*(R⁢2R⁢1)*C⁢2-R⁢3*C⁢3)*s+R⁢3*C⁢2*R⁢2*C⁢1*s2](5)
Once again, the equalizer circuitry20provides a second-order complex-zero transfer function. By appropriately adjusting the values of R1-R4 and C1-C3, the equalizer circuitry20may be designed to effectively cancel the load presented by the RF power amplifier circuitry16to the ETIC18, thereby allowing the envelope tracking supply voltage Vccto accurately track the power envelope of the RF input signal RFinover a wide bandwidth and improving the performance of the RF amplifier circuitry16. As in the above, the values of R1-R4 and C1-C3 may be chosen such that the zeros in the transfer function H(s) are complex conjugates. The equalizer circuitry20shown inFIG.7thus provides the same benefits as discussed above with respect toFIG.6. While not shown, any of R1-R4 and C1-C3 may be adjustable components that are adjusted by control circuitry that is internal or external to the equalizer circuitry20and may be adjusted based on one or more operational conditions of the equalizer circuitry20, the ETIC18, and/or the RF power amplifier circuitry16.

FIG.8shows the equalizer circuitry20according to an additional embodiment of the present disclosure. The equalizer circuitry20shown inFIG.8is substantially similar to that shown in the figures above, except for the interconnections between the operational amplifiers and the passive components. Specifically, the first inverting input28is coupled to the target voltage input node26P via a first capacitor C1. The first inverting input28is also coupled to the first output32via a first resistor R1. The first non-inverting input is coupled to ground. The second inverting input34is coupled to the first output32via a second resistor R2 and a second capacitor C2, which are coupled in parallel with one another. The second inverting input node34is also coupled to the inverted target voltage node26M via a third resistor R3, and additionally is coupled to the second output node38via a fourth resistor R4. The second non-inverting input36is coupled to ground. The second output is coupled to the equalized target voltage output node40P of the equalized target voltage output40.

The equalizer circuitry20shown inFIG.8operates in a substantially similar manner to that discussed above with respect toFIGS.6and7, but provides a different transfer function as shown in Equation 6:

H⁡(s)=R⁢4R⁢3*[1+R⁢3*(R⁢1R⁢2)*C⁢1*s*(1+R⁢2*C⁢2*s)](6)
Once again, the equalizer circuitry20provides a second-order complex-zero transfer function. By appropriately adjusting the values of R1-R4, C1, and C2, the equalizer circuitry20may be designed to effectively cancel the load presented by the RF power amplifier circuitry16to the ETIC18, thereby allowing the envelope tracking supply voltage Vccto accurately track the power envelope of the RF input signal RFinover a wide bandwidth and improving the performance of the RF amplifier circuitry16. As in the above, the values of R1-R4, C1, and C2 may be chosen such that the zeros in the transfer function H(s) are complex conjugates. The equalizer circuitry20shown inFIG.8thus provides the same benefits as discussed above with respect toFIG.6. While not shown, any of R1-R4, C1, and C2 may be adjustable components that are adjusted by control circuitry that is internal or external to the equalizer circuitry20and may be adjusted based on one or more operational conditions of the equalizer circuitry20, the ETIC14, and/or the RF power amplifier circuitry16.

FIG.9shows the equalizer circuitry20according to an additional embodiment of the present disclosure. The equalizer circuitry20shown inFIG.9is substantially similar to that shown in the figures above, except for the interconnections between the operational amplifiers and the passive components. Specifically, the first inverting input node28is coupled directly to the first output node32. The first non-inverting input node30is coupled to the target voltage input node26P via a first capacitor C1, and to ground via a first resistor R1. The second inverting input node34is coupled to the first output32via a second resistor R2 and a second capacitor C2, which are coupled in parallel with one another. The second inverting input node34is also coupled to the inverting target voltage input node26M via a third resistor R3 and a third capacitor C3, which are coupled in series with one another, to the target voltage input node26P via a fourth resistor R4, and to the second output node38via a fifth resistor R5. The second output node38is coupled to the equalized target voltage output node40P of the equalized target voltage output40.

The equalizer circuitry20shown inFIG.9operates in a substantially similar manner to that discussed above with respect toFIGS.6through8, except that the first operational amplifier OPA1acts as a buffer stage, which may allow for a wider bandwidth of the equalizer circuitry20. A transfer function of the equalizer circuitry20ofFIG.9is as shown in Equation 7:

H⁡(s)=R⁢5R⁢4*1+(R⁢4R⁢2*R⁢1*C⁢1-R⁢4*C⁢3)*s+R⁢1*C⁢1*R⁢4*C⁢2*s2)1+R⁢1*C⁢1*s(7)
Once again, the equalizer circuitry20provides a second-order complex-zero transfer function. By appropriately adjusting the values of R1-R5 and C1-C3, the equalizer circuitry20may be designed to effectively cancel the load presented by the RF power amplifier circuitry16to the ETIC18, thereby allowing the envelope tracking supply voltage Vccto accurately track the power envelope of the RF input signal RFinover a wide bandwidth and improving the performance of the RF power amplifier circuitry16. As in the above, the values of R1-R4 and C1-C3 may be chosen such that the zeros in the transfer function H(s) are complex conjugates. The equalizer circuitry20inFIG.9thus provides the same benefits as discussed above with respect toFIG.6. While not shown, any of R1-R4 and C1-C3 may be adjustable components that are adjusted by control circuitry that is internal or external to the equalizer circuitry20and may be adjusted based on one or more operational conditions of the equalizer circuitry the ETIC18, and/or the RF power amplifier circuitry16.

FIG.10shows the equalizer circuitry20according to an additional embodiment of the present disclosure. The equalizer circuitry20inFIG.10is substantially similar to that shown inFIG.9, except that it further includes a sixth resistor R6 between the first inverting input node28and the first output node32and a seventh resistor R7 between the first inverting input node28and ground. This change effectively provides a gain on the first operational amplifier OPA1equal to 1+k where

k=R⁢6R⁢7.
The equalizer circuitry operates in a substantially similar way to that discussed above with respect toFIG.9, but provides a transfer function as shown in Equation 8:

H⁡(s)=R⁢5R⁢4*1+((1+k)*R⁢4R⁢2*R⁢1*C⁢1-R⁢4*C⁢3)*s+(1+k)*R⁢1*C⁢1*R⁢4*C⁢2*s2)(1+R⁢1*C⁢1*s)(8)
where, as discussed above,

k=R⁢6R⁢7.
By appropriately adjusting the values of R1-R7 and C1-C3, the equalizer circuitry20may be designed to effectively cancel the load presented by the RF power amplifier circuitry16to the ETIC18, thereby allowing the envelope tracking supply voltage Vccto accurately track the power envelope of the RF input signal RFinover a wide bandwidth and improving the performance of the RF power amplifier circuitry16. As in the above, the values of R1-R7 and C1-C3 may be chosen such that the zeros in the transfer function H (s) are complex conjugates. The equalizer circuitry20inFIG.10thus provides the same benefits as discussed above with respect toFIG.6. While not shown, any of R1-R7 and C1-C3 may be adjustable components that are adjusted based on one or more operational conditions of the equalizer circuitry the ETIC18, and/or the RF power amplifier circuitry16.

As discussed above, while only the equalized target voltage signal output node40P is shown inFIGS.6-10, the equalized target voltage output40may be a differential output that further includes an inverted equalized target voltage signal output node40M.FIG.11thus shows the equalizer circuitry20designed for providing a differential output signal using differential operational amplifiers. As shown, the first operational amplifier OPA1includes the first inverting input node28, the first non-inverting input node30, a first inverting output node42, and a first non-inverting output node44. Similarly, the second operational amplifier OPA2includes the second inverting input node34, the second non-inverting input node36, a second inverting output node46, and a second non-inverting output node48. The inverted target voltage input node26M is coupled to the second non-inverted input node36via a first resistor R1a and a first capacitor C1a, which are coupled in parallel with one another. The second non-inverting input node36is also coupled to the second inverting output node46via a second resistor R2a. The second inverting output node46is coupled to the inverted equalized target voltage output node40M. The first inverting output node42is coupled to the second non-inverting input node36via an intermediate capacitor CIa. The first non-inverting input node30is coupled to the first inverting output node42via a third capacitor C3a and a third resistor R3a, which are coupled in parallel with one another. The first non-inverting input node30is also coupled to the target voltage input node26via a fourth resistor R4a, a fourth capacitor C4a, and a direct current (DC) blocking capacitor CDCB, wherein the fourth resistor R4a and the DC blocking capacitor CDCBare coupled in series and the fourth capacitor C4a is coupled in parallel with the series combination of the fourth resistor R4a and the DC blocking capacitor CDCB.

Due to the differential topology of the equalizer circuitry20shown inFIG.11, the bottom half of the circuit essentially mirrors the top half. This is why the components discussed above are post-fixed with “a” and the components discussed below are post-fixed with “b”. Similar to the above, the target voltage input node26P is coupled to the second inverted input node34via a first additional resistor R1b and a first additional capacitor C1b, which are coupled in parallel with one another. The second inverted input node34is also coupled to the second non-inverting output node48via a second additional resistor R2b. The first non-inverting output node44is coupled to the second inverting output node34via an additional intermediate capacitor CIb. The first inverting input node28is coupled to the first non-inverting output node44via a third additional resistor R3b and a third additional capacitor C3b, which are coupled in parallel with one another. The first inverting input node28is also coupled to the inverted target voltage input node26M via a fourth additional resistor R4b, a fourth additional capacitor C4b, and an additional DC blocking capacitor CDCB, wherein the fourth additional resistor R4b and the additional DC blocking capacitor CDCBare coupled in series and the fourth additional capacitor C4b is coupled in parallel with the series combination of the fourth additional resistor R4b and the additional DC blocking capacitor CDCB.

Resistors and capacitors having the same numbering (e.g., R1a and R1b) may have the same component values in various embodiments. With this in mind, the equalizer circuitry20may operate in a substantially similar manner as that discussed above with respect toFIGS.6-10, but in a differential fashion such that two signal paths exist through the equalizer circuitry20. The equalizer circuitry20may thus provide a transfer function as defined in Equation 9:

H⁡(s)=R⁢2R⁢1*(1+R⁢3*R⁢1*CIR⁢4⁢s+R⁢3*R⁢1*C⁢4*CI*s2)(9)
where the values for each resistor (e.g., R1a and R1b) are defined by a single value (e.g., R1) in the equation. Once again, the equalizer circuitry20provides a second-order complex-zero transfer function. By appropriately adjusting the values of R1-R4, CI, and C1, C3, and C4, the equalizer circuitry20may be designed to effectively cancel the load presented by the RF power amplifier circuitry16to the ETIC18, thereby allowing the envelope tracking supply voltage Vccto accurately track the power envelope of the RF input signal RFinover a wide bandwidth and improving the performance of the RF power amplifier circuitry16. As in the above, the values of R1-R4, CI, and C1, C3, and. C4 may be chosen such that the zeros in the transfer function H(s) are complex conjugates. The equalizer circuitry inFIG.11thus provides the same benefits as discussed above with respect toFIG.6. While not shown, any of R1-R4, CI, and C1, C3, and C4 may be adjustable components that are adjusted based on one or more operational conditions of the equalizer circuitry20, the ETIC18, and/or the RF power amplifier circuitry16. For example, the values of any of R1-R4, CI, and C1, C3, and C4 may be adjusted to provide certain desired zeros, which may be any combination of complex and real.

While not shown in the transfer functions above, in some embodiments the equalizer circuitry20may generate poles in addition to zeros. The values of any of the passive components in the equalizer circuitry20may be adjusted in order to tailor these poles as desired while maintaining the desired zeros discussed above. Further, while the equalizer circuitry20discussed above as always providing a second-order complex-zero transfer function, those skilled in the art will appreciate that the values of the passive components as well as the connections between the first operational amplifier OPA1and the second operational amplifier OPA2may be adjusted in order to provide additional zeros and poles as desired, which may be any combination of complex and real. In general, the present disclosure contemplates the use of only two operational amplifiers to generate a second-order transfer function having two zeros, which may be any combination of complex and real. As discussed above, this is done by exploiting the differential nature of an input signal provided to the equalizer circuitry20. Providing equalizer circuitry20in this manner allows for the creation of a transfer function with a desired complexity while maintaining simplicity and reducing both footprint and power consumption.

In some embodiments such as RF power amplifier systems for fifth generation (5G) millimeter wave (mmWave) applications, an ETIC may provide separate envelope tracking supply voltages to several RF power amplifiers simultaneously. Accordingly, it may be desirable for the equalizer circuitry20to simultaneously provide multiple equalized target voltage signals, each with a different transfer function, gain, or both. Accordingly,FIG.12shows the equalizer circuitry20according to an additional embodiment of the present disclosure. The equalizer circuitry20shown inFIG.12is substantially similar to that shown inFIG.8, but further includes a third operational amplifier OPA3and a fourth operational amplifier OPA4. The third operational amplifier OPA3includes a third inverting input node50, a third non-inverting input node52, and a third output node54. The fourth operational amplifier OPA4includes a fourth inverting input node56, a fourth non-inverting input node58, and a fourth output node60. The third inverting input node50is coupled to the first output node32via a fifth resistor R5 and a fifth capacitor C5, which are coupled in parallel with one another. The third inverting input node50is also coupled to the inverted target voltage input node26M. The fourth inverting input node56is coupled to the first output node32via a sixth resistor R6 and a sixth capacitor C6, which are coupled in parallel with one another. The fourth inverting input node56is also coupled to the inverted target voltage input node26M. The third non-inverting input node52is coupled to ground. The third output node54is coupled to the third inverting input node50via a seventh resistor R7. The fourth non-inverting input node58is coupled to ground. The fourth output node60is coupled to the fourth inverting input node56via an eighth resistor R8.

While only three stages are shown in the equalizer circuitry20inFIG.12, those skilled in the art will readily appreciate that any number of operational amplifiers can be added in the same parallel fashion to create additional stages and thus independent outputs. In operation, the first operational amplifier OPA1and the second operational amplifier OPA2operate as described above to generate the equalized target voltage signal Vteat the equalized target voltage output node40P. The third operational amplifier OPA3operates similar to the second operational amplifier OPA2to generate a first additional equalized target voltage signal Vte(1)at a first additional equalized target voltage output node40P(1), which is part of a first additional equalized target voltage output40(1). The values of the fifth resistor R5, the fifth capacitor C5, and the seventh resistor R7 will determine the transfer function between the target voltage input26and the first additional equalized target voltage output40(1), which can be adjusted as necessary to create a desired response. Notably, the transfer function will similarly be a second-order complex-zero function. Similarly, the fourth operational amplifier OPA4generates a second additional equalized target voltage signal Vte(2)at a second additional equalized target voltage output node40P(2), which is part of a second additional equalized target voltage output40(2). The values of the sixth resistor R6, the sixth capacitor C6, and the eighth resistor R8 will determine the transfer function between the target voltage input and the second additional equalized target voltage output40(2), which can be adjusted as necessary to create a desired response. Again, the transfer function will be a second-order complex-zero function. Accordingly, the equalizer circuitry20can provide multiple equalized target voltage signals for multiple RF power amplifiers, which, as discussed, may be particularly useful in 5G mmWave applications.

It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.