Patent ID: 12205926

SUMMARY

Representative techniques and devices are disclosed, including process steps for preparing various microelectronic devices for bonding, such as for direct bonding without adhesive. In various embodiments, techniques may be employed to mitigate the potential for delamination due to metal expansion, particularly when a TSV or a bond pad over a TSV is presented at the bonding surface of one or both devices to be bonded. For example, in one embodiment, the TSV may extend partially or fully through the substrate of the device, and at least one end of the TSV is exposed at a bonding surface of the device. For instance, the exposed end of the TSV is prepared and used as a bonding surface or in place of a bonding pad for the device.

When using surface preparation processes such as CMP to prepare the bonding surface of the substrate, an exposed metal end of the TSV at the bonding surface can become recessed relative to the dielectric, due to the softer material of the TSV relative to the material of the dielectric. A larger diameter TSV may become recessed to a greater degree (e.g., a deeper recess) than a smaller diameter TSV. In such an embodiment, the recess of the end surface of the TSV provides room for the metal expansion of the TSV during heated annealing, which can reduce or eliminate delamination that could occur otherwise.

In various implementations, an example process includes providing a conductive via through a first substrate having a first bonding surface. The conductive via extends from the first bonding surface at least partially through the first substrate. The process includes exposing the conductive via from a surface opposite the first bonding surface, and forming a second bonding surface with the conductive via at or recessed relative to the second bonding surface.

In various embodiments, the process includes reducing or eliminating delamination of bonded microelectronic components by selecting the conductive via and using at least one end of the conductive via as a bonding contact surface for direct bonding (e.g., DBI).

Additionally or alternatively, the back side of the first substrate may also be processed for bonding. One or more insulating layers of preselected materials may be deposited on the back side of the first substrate to provide stress relief when the back side of the first substrate is to be direct bonded.

Further, the conductive via, as well as other conductive vias within the first substrate may be used to direct or transfer heat within the first substrate and/or away from the first substrate. In some implementations, the thermal transfer conductive vias may extend partially or fully through a thickness of the first substrate and may include a thermally conductive barrier layer. In such examples, barrier layers normally used around the conductive vias that tend to be thermally insulating may be replaced with thermally conductive layers instead. In various implementations, some conductive vias may be used for signal transfer and thermal transfer.

In an embodiment, a microelectronic assembly comprises a first substrate having a front side and a back side, where the back side has a bonding surface comprising a nonconductive bonding layer and a conductive via. A second substrate has a front side and a back side, and the front side includes a nonconductive bonding layer and a conductive feature. The front side of the second substrate is direct bonded to the back side of the first substrate such that the conductive pad contacts to the conductive feature. An exposed end of the conductive via comprises a contact surface suitable for direct metal-to-metal bonding without an intervening material.

Various implementations and arrangements are discussed with reference to electrical and electronics components and varied carriers. While specific components (i.e., dies, wafers, integrated circuit (IC) chip dies, substrates, etc.) are mentioned, this is not intended to be limiting, and is for ease of discussion and illustrative convenience. The techniques and devices discussed with reference to a wafer, die, substrate, or the like, are applicable to any type or number of electrical components, circuits (e.g., integrated circuits (IC), mixed circuits, ASICS, memory devices, processors, etc.), groups of components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), and the like, that may be coupled to interface with each other, with external circuits, systems, carriers, and the like. Each of these different components, circuits, groups, packages, structures, and the like, can be generically referred to as a “microelectronic component.” For simplicity, unless otherwise specified, components being bonded to another component will be referred to herein as a “die.”

This summary is not intended to give a full description. Implementations are explained in more detail below using a plurality of examples. Although various implementations and examples are discussed here and below, further implementations and examples may be possible by combining the features and elements of individual implementations and examples.

DETAILED DESCRIPTION

Overview

Referring toFIG.1A(showing a cross-sectional profile view) andFIG.1B(showing a top view), patterned metal and oxide layers are frequently provided on a die, wafer, or other substrate (hereinafter “die102”) as a hybrid bonding, or DBI®, surface layer. A representative device die102may be formed using various techniques, to include a base substrate104and one or more insulating or dielectric layers106. The base substrate104may be comprised of silicon, germanium, glass, quartz, a dielectric surface, direct or indirect gap semiconductor materials or layers or another suitable material. The insulating layer106is deposited or formed over the substrate104, and may be comprised of an inorganic dielectric material layer such as oxide, nitride, oxynitride, oxycarbide, carbides, carbonitrides, diamond, diamond like materials, glasses, ceramics, glass-ceramics, and the like.

A bonding surface108of the device wafer102can include conductive features such as contact pads110, traces112, and other interconnect structures, for example, embedded into the insulating layer106and arranged so that the conductive features110from respective bonding surfaces108of opposing devices can be mated and joined during bonding, if desired. The joined conductive features110can form continuous conductive interconnects (for signals, power, etc.) between stacked devices.

Damascene processes (or the like) may be used to form the embedded conductive features110in the insulating layer106. The conductive features110may be comprised of metals (e.g., copper, etc.) or other conductive materials, or combinations of materials, and include structures, traces, pads, patterns, and so forth. In some examples, a barrier layer may be deposited in the cavities for the conductive features110prior to depositing the material of the conductive features110, such that the barrier layer is disposed between the conductive features110and the insulating layer106. The barrier layer may be comprised of tantalum, for example, or another conductive material, to prevent or reduce diffusion of the material of the conductive features110into the insulating layer106. After the conductive features110are formed, the exposed surface of the device wafer102, including the insulating layer106and the conductive features110can be planarized (e.g., via CMP) to form a flat bonding surface108.

Forming the bonding surface108includes finishing the surface108to meet dielectric roughness specifications and metallic layer (e.g., copper, etc.) recess specifications, to prepare the surface108for direct bonding. In other words, the bonding surface108is formed to be as flat and smooth as possible, with very minimal surface topology variance. Various conventional processes, such as chemical mechanical polishing (CMP), dry or wet etching, and so forth, may be used to achieve the low surface roughness. These processes provides the flat, smooth surface108that results in a reliable bond.

In the case of double-sided dies102, a patterned metal and insulating layer106with prepared bonding surfaces108may be provided on both sides of the die102. The insulating layer106is typically highly planar (usually to nm-level roughness) with the metal layer (e.g., embedded conductive features110) at or recessed just below the bonding surface108. The amount of recess below the surface108of the insulating layer106is typically determined by a dimensional tolerance, specification, or physical limitation. The bonding surfaces108are often prepared for direct bonding with another die, wafer, or other substrate using a chemical-mechanical polishing (CMP) step and/or other preparation steps.

Some embedded conductive features or interconnect structures may comprise metal pads110or conductive traces112that extend partially into the dielectric substrate106below the prepared surface108. For instance, some patterned metal (e.g., copper) features110or112may be about 0.5-2 microns thick. The metal of these features110or112may expand as the metal is heated during annealing. Other conductive interconnect structures may comprise metal (e.g., copper) through silicon vias (TSVs)114or the like, that extend normal to the bonding surface108, partly or fully through the substrate102and include a larger quantity of metal. For instance, a TSV114may extend about 50 microns, depending on the thickness of the substrate102. The metal of the TSV114may also expand when heated. Pads110and/or traces112may or may not be electrically coupled to TSVs114, as shown inFIG.1A.

Referring toFIG.2, dies102may be direct bonded, for instance, without adhesive to other dies102with metal pads110, traces112, and/or TSVs114. If a metal pad110is positioned over a TSV114(overlapping and physically and electrically coupled to the TSV114), the expansion of the TSV114metal can contribute to the expansion of the pad110metal. In some cases, the combined metal expansion can cause localized delamination202of the bonding surfaces at the location of the TSV114(or TSV114/pad110combination), as the expanding metal rises above the bonding surface108. For instance, the expanded metal can separate the bonded dielectric surfaces108of the stacked dies102.

Example Embodiments

Referring toFIGS.3A-6, in various embodiments, techniques may be employed to mitigate the potential for delamination due to metal expansion. For example, in one embodiment, as shown inFIGS.3A and3B, a TSV114may be extended through the base layer104of the die102, and through one or more insulating layers106to at least one bonding surface108. An end302(or both ends302) of the TSV114may be exposed at the bonding surface(s)108of the die102and used as a contact surface for direct bonding (e.g., DBI). In other words, the contact surface302of the TSV can be exposed through the dielectric layer106at the bonding surface, prepared (e.g., planarized, etc.), and used in place of a direct bonding pad (instead of a contact pad110).

Referring toFIG.4, in various implementations, using an end surface302of the TSV114as a bonding surface can reduce or eliminate delamination of bonded dies102, when the dies102are heat annealed and the metal of the TSV114and the contact pads110expand. In the implementations, the metal expansion of the TSV114may be taken into consideration, based on the volume of the TSV114. Accordingly, a predetermined recess “d” in the end surface302of the TSV114(as shown inFIG.5, for example) can be sufficient to provide room for the material expansion of the TSV114.

In various embodiments, TSVs114used as direct bonding contact structures may have diameters that are larger or smaller by a preselected amount, than other TSVs114disposed elsewhere within the die102. In an embodiment, the size of the TSVs114are selected or formed by estimating an amount that the material of the TSV114will expand when heated to a preselected temperature (˜300°), based on a volume of the material of the TSV114and a coefficient of thermal expansion (CTE) of the material of the TSV114, and predicting an amount that the material of the TSV114will expand when heated to the preselected temperature.

Referring toFIG.5, in an embodiment, the end302of the TSV114is planarized along with the bonding surface108of the dielectric layer106, including recessing the end302of the TSV114to have a predetermined recess depth (“d”) relative to the bonding surface108, based on an expansion of the TSV114material at the predetermined temperature. In other words, the recess depth is determined based on the volume of the material of the TSV114and the coefficient of thermal expansion (CTE) of the material of the TSV114.

In one embodiment, the end302of a TSV114may be selectively etched (via acid etching, plasma oxidation, etc.) to provide the desired recess depth “d” (to accommodate a predicted metal expansion). In another example, as shown atFIG.6, the end302of a corresponding TSV114may be selected, formed, or processed to have an uneven top surface as an expansion buffer. For example, referring toFIG.6, the end surface302of the TSV114may be formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat to allow additional space602for material expansion.

The additional space602may be determined and formed based on the amount that the material of the TSV114will expand when heated. In various implementations, the end surface302of the TSV114may be formed to be uneven during deposition, or may be etched, grinded, polished, or otherwise made uneven after forming the TSV114. In some cases, the end surface302of the TSV114may be made uneven during CMP of the bonding surface108.

Additionally or alternately, the dielectric106at the bonding surface108around the TSV114can be formed or shaped to allow room for the metal of the TSV114to expand. In one example, a CMP process can be used to shape the surface108of the dielectric106around the TSV114, or in other examples other processes can be used, so that the dielectric106around the TSV114includes a recess or other gap that provides room for metal expansion. In an embodiment, the dielectric106can be recessed (e.g., with CMP) while the bonding surface108is being prepared. In the embodiment, the TSV114and the dielectric106may be recessed concurrently (but at different rates). For instance, the process may form erosion in the dielectric106around the edges of the TSV114while recessing the metal TSV114.

In various embodiments, the TSV114is comprised of copper, a copper alloy, or the like. In a further embodiment, the materials of the TSV114may be varied to control metal expansion and potential resulting delamination. For instance, in some embodiments, the TSV114may be comprised of different conductive materials, perhaps with lower CTEs. In some embodiments the TSV114may be comprised of a different conductive material (with a lower CTE) than the contact pads110. For example, the TSV114may be comprised of tungsten, an alloy, or the like.

In other embodiments the volume of material of the TSV114may be varied to control metal expansion and the potential for resulting delamination. For instance, in some embodiments, a TSV114with a preselected material volume (e.g., less volume of material) may be used, when this is allowable within the design specifications. The preselection of volume of the TSV114may be based on anticipated material expansion of the TSV114.

Referring back toFIG.4, after preparation of the bonding surface108(e.g., by CMP) the die102may be direct bonded, for instance, without adhesive to other dies102with metal pads110, traces112, and/or TSVs114. The material of the TSVs114expand during heated annealing as mating TSVs114of opposite dies102bond to form a single conductive interconnect. However, the metal expansion does not cause delamination of the bonding surfaces when an adequate predetermined recess is provided as discussed, since the expanding metal of the TSV114does not exceed the space provided by the recess at the end surface302of the TSV114.

For instance, if the end surface302of the TSVs114are sufficiently recessed, the expanding metal of the TSVs114fills the recess(es) without separating the bonded dielectric surfaces108of the stacked dies102. When using surface preparation processes such as CMP to prepare the bonding surface108of the die102, the TSVs114exposed at the bonding surface108can become recessed (intentionally or unintentionally) relative to the dielectric106, due to the softness of the TSVs114(which may comprise copper, for instance) relative to the dielectric106(which may comprise an oxide, for example).

In various embodiments, the amount of recessing of a TSV114may be predictable, based on the surface preparation technique used (e.g., the chemical combination used, the speed of the polishing equipment, etc.), the materials of the dielectric layer106and the TSV114, the spacing or density of the TSVs114(and metal pads110), and the size (e.g., area or diameter) of the TSVs114. In the embodiments, the area or diameter of the TSVs114may be selected (e.g., for a particular material) to avoid delamination of bonded dies102based on the recess desired and the expected metal expansion of the TSVs114. For example, in some cases, larger diameter TSVs114may be selected when increased recessing is desired. This technique can result in reduced or eliminated delamination, as well as dependable mechanical coupling of the dielectric106and metal structures (e.g., TSVs114) at the bonding surfaces108and reliable electrical continuity of the bonded metal structures.

Additional Embodiments

FIGS.7-13illustrate examples of backside die102processing, according to various embodiments. In some implementations, where dies102are stacked and direct bonded without adhesive, the backside702of the die102may receive different preparation than the topside bonding surface108, when the backside702is prepared for direct bonding. Instead of forming the dielectric layer106on the backside702of the die102, the backside702may be prepared differently to reduce process steps, reduce manufacturing costs, or for other reasons.

In one implementation, the backside702is prepared so that the TSV114is exposed, to be used as a contact surface302for bonding to a conductive pad, interconnect, or other conductive bonding surface. The preparation may include depositing a thin layer of insulating material and planarizing (via CMP, for example) the backside702(which may include planarizing the insulating material and/or the base substrate104) to reveal the TSV114. In some cases, however, the expansion of the material of the TSV114during heated annealing can cause the insulating material and/or the substrate104to become damaged.

In an embodiment, as shown inFIGS.7-13, one or more layers of material may be deposited on the backside702as a stress relief to prevent or eliminate damage to the substrate104and the die102. The layers of material can be planarized and otherwise prepared as a bonding surface on the backside702of the die102.

As shown atFIG.7the TSV114is disposed within the die102, transverse to the bonding surface108of the die102. The TSV114may initially extend beyond the surface of the backside702of the die102. A diffusion barrier and oxide liner704surrounds the TSV114to prevent diffusion of the metal of the TSV114(e.g., copper) into the material of the base substrate104(e.g., silicon). In an embodiment, as shown atFIG.7, another diffusion barrier706is deposited on the surface of the backside702of the die102. In an example, the diffusion barrier706comprises a dielectric, such as a nitride or the like.

In various embodiments, one or more insulating layers are then deposited onto the backside702of the die102to prevent damage to the die102when the material of the TSV114expands. For example, a first layer708, comprising a first low temperature dielectric, such as an oxide, may be deposited over the backside702, including over the diffusion layer706. The first oxide layer708may comprise a low temperature oxide bonding layer. For instance,FIG.7shows this scenario, and includes a formed contact pad110on the front side bonding surface108over the TSV114.

As shown atFIG.8, the backside702is planarized (via CMP, for example), including the one or more insulating layers708to form a flat, smooth bonding surface for direct bonding. The remaining dielectric layer708can assist with warpage control, balancing with the front side of the die102. The TSV114is exposed by the planarizing, including a revealed contact surface302of the TSV114.

Notably, when some types of low temperature oxide (e.g., silox, etc.) are used, the oxide may be less rigid and the TSV114may be more prone to breaking during planarization. Once planarized, the oxide is more stable. When other types of low temperature oxide (e.g., TEOS, etc.) are used, the oxide may give better support to the TSV114, but the oxide may also relax, leaving the area around the TSV114higher (˜1-10 nm) than the bonding surface, which can cause problems with direct bonding (e.g., DBI). As a solution to this issue, the DBI bonding layer (the layer708, for example) is added on top of the TSV114, as shown inFIG.7.

A second die802similar or identical to the die102is also shown atFIG.8, in dashed lines. The illustration ofFIG.8shows an example of a front-to back direct bonding arrangement (without adhesive), where the second die802is bonded (dielectric-to-dielectric) at the front side108of the second die802to the backside702of the first die102. As shown, in such an arrangement, the surface302of the revealed TSV114at the backside702of the first die102is bonded (metal-to-metal) to the conductive pad110at the second die802. In alternate embodiments, the dies102and802may be bonded front-to-front, or back-to-back.

In an embodiment, as shown atFIGS.9-10, multiple layers may be added to the backside702to reduce metal expansion stress at the TSV114and to form a backside702bonding surface for the die102. As shown atFIG.9, after deposition of the first low temperature oxide layer708(which also comprises the bonding layer in some implementations), a second dielectric layer902(which may comprise a low temperature oxide) may be deposited over the first layer708. No barrier or adhesion layer is needed between the two oxide layers (708and902). In various implementations, the first layer708and the second layer902are comprised of similar or the same materials (in varying thicknesses). In other implementations, the first layer708and the second layer902are comprised of different materials. The second oxide layer902may have a similar or a different residue stress characteristic than the first layer708(for example, the first layer708may be compressive and the second layer902may be tensile, or vice versa, or both layers708and902may be compressive or tensile with similar or different values). In alternate implementations, additional insulating layers may also be deposited over the first708and second902layers.

As shown atFIG.10, the layers708and902are planarized (e.g., CMP), revealing the TSV114and the end surface302, which can function in place of a bonding pad. In an implementation, part of the second layer902may be left on the die102for warpage control.

In some embodiments, as shown inFIG.11, the end surface302at the backside702may be formed to have an uneven or non-flat surface topology. For example, the end surface302may be selected, formed, or processed to have an uneven surface topology as an expansion buffer. For example, referring toFIG.11, the end surface302of the TSV114may be formed or selectively etched to be rounded, domed, convex, concave, irregular, or otherwise non-flat to allow additional space1102for material expansion.

The additional space1102may be determined and formed based on the prediction of the amount that the material of the TSV114will expand when heated. In various implementations, the end surface302of the TSV114may be formed to be uneven during deposition, or may be etched, grinded, polished, or otherwise made uneven after forming the TSV114. In some cases, the end surface302of the TSV114may be made uneven during CMP of the backside702bonding surface.

FIGS.12-13illustrate examples of processing the backside702of the die102, when an offset contact pad110is disposed on the front side108, according to various embodiments. As shown inFIGS.12and13, the offset contact pad110may be coupled to the TSV114using one or more traces112, or the like. As discussed above, one or more oxide stress layers (such as layer708, for example) may be deposited on the backside702after depositing a diffusion barrier layer706over the backside702. The stress layer708may also comprise a direct bonding layer when it is the final layer on the backside702.

As shown inFIG.13, the layer708is planarized to form a bonding surface and to reveal the TSV114with a smooth contact surface302. In alternate embodiments, multiple stress layers may be deposited and planarized at the backside702in preparation for direct bonding.

In other embodiments, alternate techniques may be used to reduce or eliminate delamination due to metal feature expansion, and remain within the scope of the disclosure.

In various embodiments, as illustrated atFIG.14, one or more of the TSVs114of a set of stacked dies102may be used to conduct heat in addition to or instead of electrical signals. For example, in some cases, it may not be practical or possible to attach a heat sink (or other heat transfer device) to a die102of a set of stacked dies102to alleviate heat generated by the die102. In such cases, other techniques may be looked-for to transfer heat as desired.

In the embodiments, as shown atFIG.14, various configurations of TSVs114, including TSVs114that extend partially or fully through a die102, may be employed to conduct heat away from the dies102(or away from a heat-generating portion of the dies102). The TSVs114of one die102may be used in conjunction with TSVs114, contact pads110, traces112, and the like, of the second die102to complete heat transfer from one die102to the other die102, and so forth. The TSVs114of the first die102can be direct bonded (e.g., DBI) to the TSVs114, contact pads110, traces112, and the like of the second die102for high performance thermal conductivity.

In an implementation, some of the TSVs114, contact pads110, traces112, and the like are electrically floating or “dummy” structures, which can be used for thermal transfer. These structures may conduct heat away from a high power die102to another die102or substrate as desired. Dummy contact pads110may be coupled to via last or via mid thermal TSVs114for thermal conduction.

In the embodiments, diffusion barrier layers704, which surround the TSVs114and can be thermally restrictive or thermal barriers may be replaced by diffusion barriers of a different material having some thermal conductivity (such as metal or alloy barriers, or the like).

Example Process

FIG.15illustrates a representative process1500for preparing various microelectronic components (such as dies102, for example) for bonding, such as for direct bonding without adhesive, while reducing or eliminating the potential for delamination due to metal expansion of embedded structures at the bonding surface. For instance, through-silicon vias (TSVs) at the bonding surface may cause delamination, particularly when coupled to contact pads, as the material of the TSVs and the contact pads expands during heated annealing. The process refers toFIGS.1-14.

The order in which the process is described is not intended to be construed as limiting, and any number of the described process blocks in the process can be combined in any order to implement the process, or alternate processes. Additionally, individual blocks may be deleted from the process without departing from the spirit and scope of the subject matter described herein. Furthermore, the process can be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein. In alternate implementations, other techniques may be included in the process in various combinations and remain within the scope of the disclosure.

In various implementations, a die, wafer, or other substrate (a “substrate”) is formed using various techniques to include a base substrate and one or more dielectric layers. In an implementation, at block1502, the process1500includes providing a conductive via (such as TSV114, for example) through a first substrate having a first bonding surface (such as bonding surface108, for example), the conductive via extending from the first bonding surface at least partially through the first substrate. In an implementation, the first via extends at least partially through the first substrate, normal to the first bonding surface. In one example, the first via extends through the first substrate to one or both surfaces of the first substrate.

At block1504, the process includes exposing the conductive via from a surface opposite the first bonding surface. In an implementation, the process includes forming a recess in an exposed end of the conductive via extending a predetermined depth below the second bonding surface. For example, the recess compensates for the expansion of the conductive via during a bonding process.

In one example, the process includes forming the exposed end of the conductive via such that there is a sloped gap between the conductive via and the second bonding surface. In various examples, the uneven topology creates space for via metal expansion during heated annealing.

At block1506, the process includes forming a second bonding surface with the conductive via at or recessed relative to the second bonding surface.

In an implementation, the process includes providing a second substrate and direct bonding the second bonding surface of the first substrate to the second substrate without an intervening adhesive. In an implementation, the process includes direct bonding the first substrate to the second substrate using a direct dielectric-to-dielectric, non-adhesive bonding technique at a bonding surface of the first substrate.

In an implementation, the second substrate further includes a conductive via extending at least partially therethrough. In another implementation, the second substrate further includes a pad over the conductive via of the second substrate, the pad contacting the conductive via of the first substrate. In an embodiment, the conductive via of the first substrate is substantially aligned with the conductive via of the second substrate.

In an alternate implementation, the conductive via is configured to remove heat from the first substrate.

In various embodiments, some process steps may be modified or eliminated, in comparison to the process steps described herein.

The techniques, components, and devices described herein are not limited to the illustrations ofFIGS.1-15, and may be applied to other designs, types, arrangements, and constructions including with other electrical components without departing from the scope of the disclosure. In some cases, additional or alternative components, techniques, sequences, or processes may be used to implement the techniques described herein. Further, the components and/or techniques may be arranged and/or combined in various combinations, while resulting in similar or approximately identical results.

CONCLUSION

Although the implementations of the disclosure have been described in language specific to structural features and/or methodological acts, it is to be understood that the implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing example devices and techniques.