Patent ID: 12218106

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A three-dimensional (3D) integrated circuit (IC) may include a first IC die bonded to a second IC die. The first and second IC dies may each comprise a semiconductor substrate, a semiconductor device integrated on the semiconductor substrate, and an interconnect structure comprising conductive wires and vias embedded in a dielectric structure. In some embodiments, the first IC die comprises a first bonding structure, and the second IC die comprises a second bonding structure. The first IC die and the second IC die may be bonded to one another through the first bonding structure and the second bonding structure. If the first IC die and the second IC die are bonded in at least a front-to-back (F2B) or in a back-to-back (B2B) orientation, heat generated from the semiconductor device of the first IC die and/or from the semiconductor device of the second IC die may become trapped due to insufficient heat dissipation by surrounding dielectric layers. In some embodiments, the trapped heat may be concentrated in the semiconductor substrates of the first and/or second IC dies and may damage the first and/or second IC dies. Further, if a 3D IC comprises more than two IC dies with similar or same designs (e.g., size/position of semiconductor device(s), interconnect structure, etc.), heat build-up in the semiconductor substrates of the IC dies may be even greater and thus, more damaging to the 3D IC.

In some embodiments, to facilitate thermal dissipation away from the semiconductor substrates and the semiconductor devices, the first and/or second IC die may comprise a through substrate via (TSV). In some embodiments, the TSV also electrically couples the first IC die to the second IC die. However, the TSV takes up a large area on a semiconductor substrate, and thus, increasing a number of TSVs in an IC die to improve heat dissipation would reduce the number of other semiconductor devices (e.g., transistors) that could be integrated on the semiconductor substrate and/or require a change in the existing layout of 3D ICs.

Various embodiments of the present disclosure present a 3D IC comprising a first IC die vertically bonded to a second IC die. In some embodiments, the second IC die comprises a second semiconductor device arranged on a frontside of a second semiconductor substrate, and a backside contact arranged on a backside of the second semiconductor substrate. When the backside of the second semiconductor substrate is arranged above the frontside of the second semiconductor substrate, the backside contact may be arranged directly above the second semiconductor device to increase heat dissipation away from the second semiconductor device. The backside contact may be arranged far enough away from the second semiconductor device to avoid electrical interference with the second semiconductor device. In some embodiments, the backside contact has a topmost surface that is below topmost surfaces of any TSVs on the second semiconductor substrate when the backside of the second semiconductor substrate is above the frontside of the second semiconductor substrate. Thus, the backside contact does not increase the vertical dimensions of the 3D IC. Additionally, the backside contact does not interfere with the existing layout of the second semiconductor device on the second semiconductor substrate. Further, in some embodiments, the backside contact is coupled to an interconnect structure of the first and/or second IC die. Thus, during operation of the second semiconductor device on the second semiconductor substrate, generated heat may dissipate through the backside contact and away from the second semiconductor device, thereby preventing heat build-up and eventual performance degradation of the 3D IC.

FIG.1illustrates a cross-sectional view100of some embodiments of a three-dimensional (3D) integrated circuit (IC) stack comprising a backside contact.

The 3D IC stack of the cross-sectional view100includes a first IC die102, a second IC die104arranged below the first IC die102, and a third IC die106arranged below the second IC die104. Thus, in some embodiments, the second IC die104may be arranged between and bonded to the first IC die102and the third IC die106. Each of the first, third, and second IC dies102,104,106comprise a semiconductor substrate, a semiconductor device (e.g., transistor, capacitor, diode, etc.) on a frontside of the semiconductor substrate, an interconnect structure arranged over the frontside of the semiconductor substrate and the semiconductor device, and a bonding structure arranged over the interconnect structure and the frontside of the semiconductor substrate. For example, the first IC die102comprises a first substrate108a, a first semiconductor device110a, a first interconnect structure112a, and a first bonding structure120a; the second IC die104comprises a second substrate108b, a second semiconductor device110b, a second interconnect structure112b, and a second bonding structure120b; and the third IC die106comprises a third substrate108c, a third semiconductor device110c, a third interconnect structure112c, and a third bonding structure120c. In some embodiments, more than one of the semiconductor devices (110a,110b,110c) may be arranged on each of the substrates (108a,108b,108c). Each of the interconnect structures (e.g.,112a,112b,112c) may comprise a network of interconnect wires114and interconnect vias116surrounded by an interconnect dielectric structure118. The network of interconnect wires114and interconnect vias116of the first interconnect structure112a, the second interconnect structure112b, and the third interconnect structure112care electrically coupled to the first semiconductor device110a, the second semiconductor device110b, and the third semiconductor device110c, respectively. In some embodiments, each of the first, second, and third bonding structures120a,120b,120cmay comprise bonding vias123and bonding wire layers122embedded within a bonding dielectric structure124. In some embodiments, the bonding structures (e.g.,120a,120b,120c) may be, for example, hybrid bond (HB) structures. In some embodiments, the second bonding structure120bis bonded to the third bonding structure120c, and the first bonding structure120ais bonded to an additional bonding structure126of the second IC die104.

In some embodiments, the additional bonding structure126of the second IC die104may also be a HB structure, for example. In some embodiments, the additional bonding structure126may comprise bonding vias123, bonding wire layers122, interconnect vias116, and/or interconnect wires114embedded within the bonding dielectric structure124. The additional bonding structure126is disposed on a backside108bsof the second substrate108bof the second IC die104. A through substrate via (TSV)132may extend from the backside108bsto a frontside108bfof the second substrate108b, in some embodiments. The TSV132may be electrically coupled to the second interconnect structure112band to conductive components (e.g., interconnect wires114, interconnect vias116, bonding wire layers122, bonding vias123) of the additional bonding structure126. Thus, the TSV132may comprise a first material that is electrically conductive and thus, electrically couples the first, second, and/or third IC dies102,104,106to one another, in some embodiments.

In some embodiments, the additional bonding structure126may further comprise a first backside contact128. The first backside contact128may extend from a bonding via123of the additional bonding structure126towards the backside108bsof the second substrate108b. In some embodiments, the first backside contact128extends into the backside108bsof the second substrate108b. In some embodiments, when the backside108bsof the second substrate108bis facing in an “up” direction (i.e., the backside108bsis above the frontside108bfof the second substrate108b), as in the cross-sectional view100ofFIG.1, the first backside contact128may be arranged directly over one of the second semiconductor devices110b. Further, the first backside contact128may be spaced apart from active areas of the second semiconductor device(s)110bto avoid electrical interference with the second semiconductor device110b. In some embodiments, the first backside contact128is coupled to the first interconnect structure112aof the first IC die102through the first bonding structure120aand the additional bonding structure126. In some embodiments, the additional bonding structure126may also comprise a second backside contact130. In some embodiments, the second backside contact130may be laterally spaced apart from the first backside contact128. In some embodiments, the first and second backside contacts128,130may comprise a second material that is different than the first material of the TSV132. Further, in some embodiments, the first and second backside contacts128,130may be arranged below a topmost surface132tof the TSV132when the backside108bsof the second substrate108bis facing in an “up” direction. Thus, the addition of the first and second backside contacts128,130in the additional bonding structure126may not increase the vertical dimensions of the second IC die104. In some embodiments, the first and/or second backside contacts128,130may be formed before the formation of the TSV132such that the first and/or second backside contacts128,130do not extend above the topmost surface132tof the TSV132.

It will be appreciated that during operation of the first semiconductor device110aheat may be generated, and the generated heat may dissipate away from the first semiconductor device110aand out of the 3D IC stack through a backside108abof the first substrate108a. Further, it will be appreciated that during operation of the second semiconductor device110b, heat may be generated. Thus, in some embodiments, a heat dissipation path134may include the first and/or second backside contacts128,130that are arranged near the second semiconductor device110bto allow any heat within the second substrate108bto dissipate away from the second semiconductor device110band out of the second substrate108b. Generated heat may travel along the heat dissipation paths134along the bonding wire layers122, the bonding vias123of the first bonding structure120aand the additional bonding structure126; along the interconnect wires114and interconnect vias116of the first interconnect structure112a; and finally dissipate out of the 3D IC stack through at least the first substrate108a.

Thus, the heat travels faster through the bonding wire layers122, the bonding vias123, the interconnect wires114, and the interconnect vias116than through the bonding dielectric structures124or the interconnect dielectric structures118. Because the first and second backside contacts128,130are arranged in closer proximity to the second semiconductor device110bthan the TSV132and because the first and second backside contacts128,130have a higher thermal conductivity than the TSV132, heat will dissipate more quickly into the first and second backside contacts128,130than into the TSV132. Therefore, the heat dissipation paths134that include the first and/or second backside contacts128,130are more efficient than a heat dissipation path (not shown) that includes the TSV132. In other words, in some embodiments, the heat dissipations paths134that include the first and/or second backside contacts128,130do not include the TSV132. Thus, the first and/or second backside contacts128,130may provide a more efficient heat dissipation path134to reduce thermal degradation to the 3D IC stack, thereby improving the lifetime of the 3D IC stack without increasing the dimensions and/or changing the layout of the 3D IC stack.

FIG.2illustrates a cross-sectional view200of some embodiments that correspond to box A in the cross-sectional view100ofFIG.1to highlight features of the first and second backside contacts128,130, the TSV132, and the second semiconductor device110b, in some embodiments.

In some embodiments, the first and second backside contacts128,130may each be surrounded by a glue layer216to promote adhesion between the between the first and second backside contacts128,130and the second substrate108b. In some embodiments, the first and second backside contacts128,130may comprise, for example tungsten, and the glue layer216may comprise, for example, titanium or titanium nitride. In some embodiments, the glue layer216may have a thickness in a range of between, for example, approximately 20 angstroms and approximately 300 angstroms. In some embodiments, the glue layer216separates the first and/or second backside contacts128,130from directly contacting the second substrate108b.

In some embodiments, the TSV132may also be surrounded by one or more layers. For example, in some embodiments, the TSV132comprises a TSV lining214that surrounds sidewalls of the TSV132. In some embodiments, the TSV lining214comprises a dielectric material (e.g., silicon nitride, silicon dioxide) to prevent the TSV132from electrically leaking into the second substrate108band near the second semiconductor device110b. In some embodiments, the TSV lining214may have a thickness in a range of between, for example, approximately 200 angstroms and approximately 2000 angstroms. In some embodiments, a bottommost surface132band the topmost surface132tof the TSV132may be uncovered by the TSV lining214to allow electrical signals to travel through the TSV132from the bottommost surface132bto the topmost surface132tsuch that the TSV132is electrically coupled to at least the second interconnect structure (112bofFIG.1). Further, in some embodiments, the TSV132may be in direct contact with a chemical barrier layer212to prevent the TSV132from chemically leaking (e.g., diffusing) into the second substrate108b. In some embodiments, the chemical barrier layer212may comprise, for example, tantalum nitride. In some embodiments, the chemical barrier layer212may have a thickness in a range of between, for example, approximately 50 angstroms and approximately 500 angstroms. In some embodiments, the chemical barrier layer212may be arranged directly on the bottommost surface132bof the TSV132.

In some embodiments, the second semiconductor device110bmay be, for example, a metal oxide semiconductor field effect transistor (MOSFET). In such example embodiments, the second semiconductor device110bmay comprise a doped well region210within the second substrate108b, wherein the doped well region210is more heavily doped and/or has a different doping type than the second substrate108b. Source/drain regions202may reside in the doped well region210, and a gate electrode206over a gate dielectric layer208may be arranged on the frontside108bfof the second substrate108b. The first backside contact128may have a bottommost surface128b, which may be defined by a bottommost surface of the glue layer216, that is spaced apart from the second semiconductor device110bsuch that the first backside contact128does not electrically interfere with the second semiconductor device110b. Therefore, in some embodiments, the glue layer216and the first backside contact128contact an area of the second substrate108bthat has a different doping concentration and/or different doping type than active areas (e.g., doped well region210, source/drain regions202) of the second semiconductor device110bin the second substrate108b. In some embodiments, the bottommost surface128bof the first backside contact128extends into the backside108bsof the second substrate108bby a first distance d1. In some embodiments, the first distance d1may be in a range of between approximately 100 angstroms and approximately 700 angstroms, for example.

Further, in some embodiments, the topmost surface128tof the first backside contact128is arranged below the topmost surface132tof the TSV132by a second distance d2. Thus, the first backside contact128takes up less space than a TSV132. For example, the TSV132penetrates through the entire second substrate108b, whereas the first backside contact128penetrates the second substrate108bby the first distance d1. Thus, n some embodiments, the bottommost surface128bof the first backside contact128is arranged above the bottommost surface132bof the TSV132. Further, the topmost surface132tof the TSV132is higher than the topmost surface128tof the first backside contact128. Thus, the first backside contact128does not increase the vertical dimensions of the overall 3D IC stack. Further, in some embodiments, the TSV132comprises copper and the first backside contact128comprises tungsten. Thus, in some embodiments, the first backside contact128has a higher thermal conductivity than the TSV132and is more effective at removing heat away the one or more second semiconductor devices110bin the second substrate108bthan the TSV132.

FIG.3illustrates a cross-sectional view300of some alternative embodiments of the cross-sectional view200ofFIG.2.

As illustrated in the cross-sectional view300ofFIG.3, in some embodiments, more than one or two backside contacts (e.g.,128,130) may be arranged on the second substrate108b. For example, in some embodiments, a first backside contact128and a second backside contact130are arranged directly over a first one of the second semiconductor devices110bon the second substrate108b, and a third backside contact302and a fourth backside contact304are arranged over a second one of the second semiconductor devices110bon the second substrate108b. In some other embodiments, more or less than two backside contacts may be arranged over a semiconductor device. Nevertheless, by increasing the number of backside contacts (e.g.,128,130,302,304) on the second substrate108b, heat generated by the second semiconductor device(s)110bmay have more heat dissipation paths (e.g.,134ofFIG.1) to travel through such that the heat to dissipates away from the second semiconductor device(s)110b.

Further, as shown inFIG.3, in some embodiments, the additional bonding structure126may include bonding vias123and not bonding wire layers (122ofFIG.2). In such embodiments, by omitting bonding wire layers (122ofFIG.2), some steps, and thus, time and costs, of the manufacturing process may be reduced. However, in such embodiments, bonding the additional bonding structure126to, for example, the first bonding structure (120aofFIG.1) may be less reliable because the bonding vias123have a smaller surface area for bonding than the bonding wire layers (122ofFIG.2).

FIG.4illustrates a cross-sectional view400of some embodiments that correspond to box B in the cross-sectional view300ofFIG.3to highlight alternative features of the first and second backside contacts128,130, in some embodiments.

As shown inFIG.4, in some embodiments, the first and/or second backside contacts128,130may have substantially curved outer sidewalls. For example, in some embodiments, the second backside contact130may have an outermost sidewall130sthat is substantially curved. In such embodiments, an outermost sidewall216sof the glue layer216that surrounds the second backside contact130may also be substantially curved.

FIG.5illustrates a cross-sectional view500of some other embodiments of a 3D IC stack comprising a backside contact, wherein the 3D IC stack comprises a backside of a first IC die bonded to a backside of a second IC die.

As shown inFIG.5, in some embodiments, a backside108abof the first substrate108aof the first IC die102may face the backside108bsof the second substrate108bof the second IC die104. In some embodiments, the additional bonding structure126is arranged on the backside108bsof the second substrate108band bonded to a second additional bonding structure526arranged on the backside108abof the first substrate108a. In such embodiments, the second additional bonding structure526may include a third backside contact528and/or a fourth backside contact530that extend into the backside108abof the first substrate108a. Further, in some embodiments, the first IC die102may comprise a first additional TSV532that extends completely through the first substrate108a. In such embodiments, for heat to dissipate away from the first and second semiconductor devices110a,110bduring operation, the first through fourth backside contacts128,130,528,530may be coupled to the TSV132and/or the first additional TSV532such that a first heat dissipation path534may be directed through the first interconnect structure112aand that a second heat dissipation path536may be directed through the second interconnect structure112b. In some embodiments, the first and/or second interconnect structures112a,112bmay be coupled to other IC dies, external bonding contacts, or some other device. It will be appreciated that in such embodiments, if the first through fourth backside contacts128,130,528,530were not coupled to the first and/or second interconnect structures112a,112bthrough the TSV132and/or the first additional TSV532, any heat generated from the first and/or second semiconductor devices110a,110bwould not be able to effectively dissipate away from the first and/or second semiconductor devices110a,110band thus, the generated heat may damage the first and/or second semiconductor devices110a,110b.

FIG.6illustrates a cross-sectional view600of yet some other embodiments of a 3D IC stack comprising a backside contact, wherein the 3D IC stack comprises a backside of a first IC die bonded to a frontside of a second IC die.

As shown inFIG.6, in some embodiments, the backside108abof the first substrate108amay face the frontside108bfof the second substrate108b. In such embodiments, the second interconnect structure112bmay be arranged over the frontside108bfof the second substrate108b, and the additional bonding structure126may be arranged over the second interconnect structure112b. In some embodiments, multiple second semiconductor devices110bmay be arranged on the second substrate108band laterally spaced apart by isolation structures605. For example, in some embodiments the isolation structures605may be or comprise shallow trench isolation (STI) structures.

In some embodiments, the additional bonding structure126of the second IC die104may further comprise second bond pads608band second bond pad vias606b. In such embodiments, the second bond pads608band the second bond pad vias606bmay comprise a same or a different conductive material than the bonding wire layers122, the bonding vias123, the interconnect vias116, and/or the interconnect wires114. For example, in some embodiments, the second bond pads608band the second bond pad vias606bcomprise aluminum, copper, or some other suitable conductive material. Further, in some embodiments, the bonding wire layers122, the bonding vias123, the interconnect vias116, the interconnect wires114, the TSV132and/or the first additional TSV532may comprise copper or some other suitable conductive material. In some embodiments, the third backside contact528arranged on the backside108abof the first substrate108amay comprise tungsten or some other suitable electrically and thermally conductive material.

Further, the second additional bonding structure526of the first IC die102may be arranged on the backside108abof the first substrate108a, in some embodiments, and the second additional bonding structure526is bonded to the additional bonding structure126. In such embodiments, heat generated by the second semiconductor device(s)110bmay escape through the backside108bsof the second substrate108b. Further, in some embodiments, the first IC die102may be electrically coupled to the second IC die104through a first additional TSV532and/or a second additional TSV632, wherein the first additional TSV532and the second additional TSV632extend completely through the first substrate108a. In some embodiments, the first interconnect structure112amay be arranged on the frontside108afof the first substrate108a, and an upper bonding structure604may be arranged over and coupled to the first interconnect structure112a. In such embodiments, the upper bonding structure604may comprise first bond pads608aand first bond pad vias606aembedded within the bonding dielectric structure124of the upper bonding structure604. In some embodiments, solder bumps610may be arranged over the first bond pads608asuch that the first and second IC dies102,104may be coupled to some external feature (e.g., printed circuit board, another IC die, wires, etc.).

In some embodiments, the first semiconductor devices110ain the first substrate108aare surrounded by the second additional bonding structure526and the first interconnect structure112a. In such embodiments, the third backside contact528may be arranged on the backside108abof the first substrate108ato promote heat dissipation away from the first semiconductor devices110a. In some embodiments, through, for example, a first heat dissipation path634and a second heat dissipation path636, generated heat from the first semiconductor device(s)110amay dissipate away from the first semiconductor device(s)110a. In some embodiments, heat may dissipate along the first heat dissipation path634that includes the third backside contact528and not the second additional TSV632. In some embodiments, heat may dissipate along the second heat dissipation path636that includes the second additional TSV632and not the third backside contact528. In other embodiments, heat may dissipate through the third backside contact528and the second additional TSV632by way of some other heat dissipation path (not shown). In some embodiments, the second heat dissipation path636may allow heat to escape through the second substrate108bor through the solder bumps610. In some embodiments, the solder bumps610may comprise aluminum, copper, or some other suitable conductive material.

Because the third backside contact528comprises a material that has a higher thermal conductivity than the second additional TSV632, heat is more likely to travel through the first heat dissipation path634than the second heat dissipation path636. Thus, the third backside contact528increases the efficiency of heat dissipation, and increasing the number of backside contacts on the first substrate108awill further increase the efficiency of heat dissipation away from the first semiconductor devices110a.

FIGS.7-22illustrate cross-sectional views700-2200of some embodiments of a method of forming a backside contact on a backside of a substrate and directly over a semiconductor device within the substrate. AlthoughFIGS.7-22are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.7-22are not limited to such a method, but instead may stand alone as structures independent of the method.

As shown in cross-sectional view700ofFIG.7, a semiconductor substrate108is provided. In some embodiments, the semiconductor substrate108may comprise any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, SOI, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. In some embodiments, the semiconductor substrate108may have a thickness in a range of between, for example, approximately 2.4 micrometers and approximately 3 micrometers. On a frontside108fof the semiconductor substrate108, a semiconductor device110may be deposited. In some embodiments, the semiconductor device110may be, for example, a transistor, a capacitor, a resistor, or the like. An interconnect structure112may be deposited over the semiconductor device110and on the frontside108fof the semiconductor substrate108, the interconnect structure112comprising interconnect vias116and interconnect wires114embedded within an interconnect dielectric structure118. In some embodiments, the interconnect structure112may have a thickness in a range of between, for example, approximately 5 micrometers and approximately 8 micrometers.

In some embodiments, the interconnect vias116and interconnect wires114comprise a same material that is conductive. For example, in some embodiments, the interconnect vias116and interconnect wires114comprise copper. In other embodiments, the interconnect vias116and interconnect wires114may comprise other conductive materials such as, for example, tungsten, aluminum, or the like. In some embodiments, the interconnect dielectric structure118may comprise a dielectric material, such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like. Further, a bonding structure120may be formed over the interconnect structure112. In some embodiments, the bonding structure120may comprise bonding vias123and bonding wire layers122embedded within a bonding dielectric structure124. In some embodiments, the bonding vias123, the bonding wire layers122, and the bonding dielectric structure124comprise the same materials as the interconnect vias116, the interconnect wires114, and the interconnect dielectric structure118, respectively. In some embodiments, the interconnect wires114may be coupled to the bonding vias123. In some embodiments, the bonding structure120may have a thickness is a range of between, for example, approximately 1.5 micrometers and approximately 2 micrometers.

As shown in cross-sectional view800ofFIG.8, the semiconductor substrate108is flipped such that a backside108sof the semiconductor substrate108may be processed. A first dielectric layer802may be deposited on the backside108sof the semiconductor substrate108. The first dielectric layer802may comprise a dielectric material, such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like. In some embodiments, the first dielectric layer802may comprise a same material as the bonding dielectric structure124. The first dielectric layer802may be formed by way deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). In some embodiments, the first dielectric layer802may have a thickness in a range of between, for example, approximately 2 kiloangstroms and approximately 4 kiloangstroms.

As shown in cross-sectional view900ofFIG.9, a first opening902may be formed that extends from the first dielectric layer802into the backside108sof the semiconductor substrate108. The first opening902may expose a first surface904of the semiconductor substrate108, wherein the first surface904of the semiconductor substrate108is arranged below the backside108sof the semiconductor substrate108by a first distance d1. In some embodiments, the first distance d1may be in a range of between, for example, approximately 100 angstroms and approximately 700 angstroms. Further, in some embodiments, the first opening902has a first width w1. In some embodiments, the first width w1is in a range of between, for example, approximately 1.5 micrometers and approximately 2.5 micrometers. It will be appreciated that other values for the first distance d1and the first width w1are also within the scope of the disclosure.

In some embodiments, the first opening902directly overlies the semiconductor device110, but the first opening902does not expose any active areas of the semiconductor device110. Thus, the first opening902is spaced apart from the semiconductor device110by the semiconductor substrate108. In some embodiments, the first opening902may be formed through photolithography and removal (e.g., etching processes) processes. For example, in some embodiments, a masking structure (not shown) may be formed over the first dielectric layer802, an opening may be formed in the masking structure by way of photolithography and removal processes, and then a removal process may be performed according to the opening in the masking structure to form the first opening902in the first dielectric layer802and the semiconductor substrate108. In some embodiments, a dry etching process may be used to form the first opening902, for example.

As shown in cross-sectional view1000ofFIG.10, a conformal glue layer1002and a first conductive material1004are formed over the first dielectric layer802and within the first opening (902ofFIG.9). In some embodiments, the conformal glue layer1002comprises, for example, titanium or titanium nitride, and has a thickness in a range of between, for example, approximately 20 angstroms and approximately 300 angstroms. In some embodiments, the first conductive material1004comprises, for example, tungsten. The conformal glue layer1002and/or the first conductive material1004may be deposited by way of, for example, a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.).

As shown in cross-sectional view1100ofFIG.11, the first conductive material (1004ofFIG.10) and the conformal glue layer (1002ofFIG.10) disposed over a topmost surface of the first dielectric layer802are removed, thereby forming a first backside contact128surrounded by a glue layer216and extending into the backside108sof the semiconductor substrate108. In some embodiments, the first conductive material (1004ofFIG.10) and the conformal glue layer (1002ofFIG.10) are removed by a planarization process (e.g., CMP), and thus, the first backside contact128may have a top surface that is substantially coplanar with the first dielectric layer802. In some embodiments, the first backside contact128may have a height in a range of between, for example, approximately 0.1 micrometers and approximately 0.4 micrometers.

As shown in cross-sectional view1200ofFIG.12, a first etch stop layer1202may be formed over the first dielectric layer802and the first backside contact128. In some embodiments, the first etch stop layer1202may comprise, for example, a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. In some embodiments, the first etch stop layer1102may be deposited by way of, for example, a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.).

As shown in cross-sectional view1300ofFIG.13, a second opening1302may be formed that extends through the first etch stop layer1202, the first dielectric layer802, the semiconductor substrate108, and a portion of the interconnect dielectric structure118to expose an upper surface1304of one of the interconnect wires114. In some embodiments, the second opening1302may be formed through a selective patterning process by forming a masking structure through photolithography and performing a removal process (e.g., etching) to form the second opening1302according to the masking structure. The second opening1302is spaced from the semiconductor device110to avoid interfering with and/or damaging the semiconductor device110. Thus, in some embodiments, the second opening1302is spaced apart from the first backside contact128. Further, the first backside contact128remains covered by the first etch stop layer1202during the formation of the second opening1302.

As shown in cross-sectional view1400ofFIG.14, an electrical insulator layer1402is deposited over the first etch stop layer1202and along surfaces of the second opening (1302ofFIG.13) defined by inner sidewalls of the first dielectric layer802and the semiconductor substrate108and by the upper surface1304of one of the interconnect wires114. In some embodiments, the electrical insulator layer1402may comprise, for example, silicon dioxide, silicon nitride, aluminum oxide, or some other electrical insulator material. In some embodiments, the electrical insulator layer1402may be deposited by way of a deposition process (e.g., CVD, PE-CVD, PVD, ALD, etc.). In some embodiments, the electrical insulator layer1402may have a thickness in a range of between, for example, approximately 200 angstroms and approximately 2000 angstroms.

As shown in cross-sectional view1500ofFIG.15, horizontal portions of the electrical insulator layer (1402ofFIG.14) are removed, thereby forming a TSV lining214within the second opening (1302ofFIG.13) and covers inner sidewalls of the first dielectric layer802, the semiconductor substrate108, and portions of the interconnect dielectric structure118. In some embodiments, the horizontal portions of the electrical insulator layer (1402ofFIG.14) may be removed using a vertical etching process (e.g., vertical dry etch), such that a masking layer is not needed. The TSV lining214does not completely cover the upper surface1304of the one of the interconnect wires114after the vertical etching process, in some embodiments.

As shown in cross-sectional view1700ofFIG.17, the second opening (1302ofFIG.13) is filled with a second conductive material to formed a TSV132. In some embodiments, a chemical barrier layer212is deposited first in the second opening (1302ofFIG.13) by way of, for example, a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.). The chemical barrier layer212may comprise, for example, tantalum or tantalum nitride and have a thickness in a range of between, for example, approximately 50 angstroms and approximately 500 angstroms. Then, in some embodiments, the second conductive material is formed over the chemical barrier layer212within the second opening (1302ofFIG.13) by way of, for example, a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.). In some embodiments, the second conductive material, and thus the TSV132comprises, for example, copper. Then, in some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) may be used to remove excess second conductive material and any excess material of the chemical barrier layer212that is arranged over the first etch stop layer1202. Thus, the TSV132and the chemical barrier layer212have upper surfaces substantially coplanar with the first etch stop layer1202. In some embodiments, the chemical barrier layer212may prevent the TSV132from diffusing in to the semiconductor substrate108, and the TSV lining214may prevent any electrical signals traveling through the TSV132during operation from leaking into the semiconductor substrate108. Thus, both the chemical barrier layer212and the TSV lining214prevent the TSV132from damaging and/or interfering with the semiconductor device110. Further, the TSV132is electrically coupled to the interconnect structure112. In some embodiments, the TSV132may have a height that is in a range of between, for example, approximately 0.7 micrometers and approximately 3.2 micrometers. Because the TSV132extends completely through the semiconductor substrate108, the TSV132has a height that is greater than the thickness of the semiconductor substrate108.

Further, because the TSV132is formed after the first backside contact128, the topmost surface132tof the TSV132is arranged above a topmost surface128tof the first backside contact128. In some embodiments, a bottommost surface132bof the TSV132is also below a bottommost surface128bof the first backside contact128, Therefore, forming the first backside contact128to aid in thermal dissipation of generated heat away from the semiconductor device110during operation of the semiconductor device110does not increase the vertical dimensions of the overall device. In some embodiments, the difference in height between the topmost surface132tof the TSV132and the topmost surface128tof the first backside contact128is equal to a second distance d2. In some embodiments, the second distance d2is equal to the thickness of the first etch stop layer1202. Thus, in some embodiments, the second distance d2is in a range of between, for example, approximately 10 angstroms and approximately 8000 angstroms.

As shown in cross-sectional view1800ofFIG.18, in some embodiments, a second etch stop layer1802may be formed over the first etch stop layer1202and over the TSV132. Further, multiple dielectric and/or etch stop layers may be formed over the first etch stop layer1202. For example, in some embodiments, a second dielectric layer1804is formed over the second etch stop layer1802; a third etch stop layer1806is formed over the second dielectric layer1804; a third dielectric layer1808is formed over the third etch stop layer1806; and a bonding dielectric layer1810is formed over the third dielectric layer1808. In some embodiments, the second and third etch stop layers1802,1806may comprise, for example, a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like; may be deposited by way of, for example, a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.); and may each have a thickness in a range of between approximately 500 angstroms and approximately 1000 angstroms, for example. Further, in some embodiments, the second and third dielectric layers1804,1808and the bonding dielectric layer1810may comprise, for example, a dielectric material, such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like; may be deposited by way of, for example, a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.); and may each have a thickness in a range of between approximately 2 kiloangstroms and approximately 4 kiloangstroms for example. Further, in other embodiments, the bonding dielectric layer1810may have a thickness in a range of between, for example, approximately 10 angstroms and approximately 8000 angstroms.

As shown in cross-sectional view1900ofFIG.19, a third opening1902and a fourth opening1904may be formed to expose the TSV132and the first backside contact128, respectively. Thus, in some embodiments, the third opening1902may extend through the bonding dielectric layer1810, the third dielectric layer1808, the third etch stop layer1806, the second dielectric layer1804, and the second etch stop layer1802to expose the TSV132. Thus, in some embodiments, the fourth opening1904may extend through the bonding dielectric layer1810, the third dielectric layer1808, the third etch stop layer1806, the second dielectric layer1804, the second etch stop layer1802, and the first etch stop layer1202to expose the first backside contact128. In such embodiments, the fourth opening1904extends through one more layer than the third opening1902; for example, in some embodiments, the fourth opening1904extends through the first etch stop layer1202, whereas the third opening1902does not extend through the first etch stop layer1202. In some embodiments, the third opening1902and the fourth opening1904may be formed by a selective patterning process according to a masking structure using photolithography and removal (e.g., etching) processes. In some embodiments, the third and fourth openings1902,1904each have a second width w2.

As shown in cross-sectional view2000ofFIG.20, in some embodiments, a fifth opening2002is formed over the third opening (1902ofFIG.19), and a sixth opening2004is formed over the fourth opening (1904ofFIG.19). In such embodiments, the fifth opening2002and the sixth opening2004may extend from the bonding dielectric layer1810, the third dielectric layer1808, and the third etch stop layer1806. In some embodiments, the fifth opening2002and the sixth opening2004may also extend partially into the second dielectric layer1804. The fifth opening2002and the sixth opening2004may directly overlie the third opening (1902ofFIG.19) and the fourth opening (1904ofFIG.19), respectively, in some embodiments. In some embodiments, the fifth opening2002and the sixth opening2004may be formed by a selective patterning process according to a masking structure using photolithography and removal (e.g., etching) processes. In some embodiments, the fifth and sixth openings2002,2004each have a third width w3that is greater than the second width w2. Thus, in some embodiments, the fifth and sixth openings2002,2004essentially widen upper portions of the third and fourth openings (1902,1904ofFIG.19). In some other embodiments, to reduce manufacturing steps and thus, time and costs, the steps ofFIG.20may be omitted. Thus, in some embodiments, the method may proceed fromFIG.19toFIG.21, thereby skippingFIG.20.

As shown in cross-sectional view2100ofFIG.21, a third conductive material is deposited into the openings (e.g.,1902ofFIG.19,1904ofFIG.19,2002ofFIG.20,2004ofFIG.20) in the first etch stop layer1202, the second etch stop layer1802, the second dielectric layer1804, the third etch stop layer1806, the third dielectric layer1808, and the bonding dielectric layer1810thereby forming bonding vias123and bonding wire layers122coupled to the TSV132and the first backside contact128. In such embodiments, the bonding vias123and the bonding wire layers122embedded within the first etch stop layer1202, the second etch stop layer1802, the second dielectric layer1804, the third etch stop layer1806, the third dielectric layer1808, and the bonding dielectric layer1810may form an additional bonding structure126arranged on the backside108sof the semiconductor substrate108. Further, in some embodiments, the first dielectric layer802, the first etch stop layer1202, the second etch stop layer1802, the second dielectric layer1804, the third etch stop layer1806, the third dielectric layer1808, and the bonding dielectric layer1810may be collectively referred to as a bonding dielectric structure of the additional bonding structure126.

In some embodiments, the third conductive material, and thus the bonding vias123and the bonding wire layers122comprise copper or some other suitable conductive material. In some embodiments, the bonding vias123of the additional bonding structure126have the second width w2, and the bonding wire layers122of the additional bonding structure126have the third width w3. Further, in some embodiments, the bonding wire layers122and the bonding vias123of the additional bonding structure126are formed by depositing the third conductive material by way of a deposition process (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.) and subsequently planarized by way of a planarization process (e.g., chemical mechanical planarization (CMP)). Thus, in some embodiments, the formation of the bonding vias123and the bonding wire layers122in the additional bonding structure126inFIGS.19-21may be representative of a dual damascene process. In some embodiments, the cross-sectional view2100ofFIG.21illustrates a second IC die104configured to be bonding to other IC dies by way of the additional bonding structure126and the bonding structure120.

As shown in cross-sectional view2200ofFIG.22, in some embodiments, a bonding process2202may be conducted to form a 3D IC stack, wherein the second IC die104is bonded to a first IC die102through the additional bonding structure126and is bonded to a third IC die106through a second bonding structure120b(120ofFIG.21). In some embodiments, the first IC die102comprises a first substrate108a, a first semiconductor device110aarranged on the first substrate108a, a first interconnect structure112aarranged on the first substrate108a, and a first bonding structure120aarranged on the first interconnect structure112a. In some embodiments, the first bonding structure120aof the first IC die102may be bonded to the additional bonding structure126of the second IC die104. Further, in some embodiments, the second IC die104may comprise a second substrate108b(108ofFIG.21) arranged between the additional bonding structure126and a second interconnect structure112b(112ofFIG.21), a second semiconductor device110b(110ofFIG.21) arranged on the second substrate108b, and a second bonding structure120barranged on the second interconnect structure112b. In some embodiments, the second bonding structure120bof the second IC die104is bonded to a third bonding structure120cof the third IC die106. In some embodiments, the third IC die106may comprise a third substrate108c, a third semiconductor device110carranged on the third substrate108c, a third interconnect structure112carranged on the third substrate108c, and the third bonding structure120carranged on the third interconnect structure112c. In some embodiments, the bonding process2202may be or comprise a fusion bonding process, a eutectic bonding process, a metallic bonding process, and/or a combination thereof. Thus, in some embodiments, the bonding process2202may be a hybrid bonding process.

In some embodiments, a first and third substrates108a,108cof the first and third IC dies102,106may each have a thickness in a range of between approximately 750 micrometers and approximately 800 micrometers. Thus, in some embodiments, the second substrate108bof the second IC die104may be thinner than each of the first and third substrates108a,108c. In some embodiments, the TSV132extends completely through the second substrate108band may electrically couple the first IC die102to the second IC die104. The first substrate108aand the third substrate108cmay respectively define the lowermost and uppermost surfaces of the 3D IC stack. Thus, during operation of the 3D IC stack, any generated heat from the semiconductor devices (e.g.,110a,110b,110c) may dissipate away from the semiconductor devices (e.g.,110a,110b,110c) and exit the 3D IC stack through the first and third substrates108a,108c. Further, because of the first backside contact128in the second IC die104, heat generated in the second substrate108bmay efficiently dissipate through the first backside contact128and towards the first and/or third substrates108a,108dthrough the bonding structures (e.g.,120a,120b,120c), the additional bonding structure126, and/or the interconnect structures (e.g.,112a,112b,112c) to mitigate thermal damage to the semiconductor devices (e.g.,110a,110b,110c) without increasing the overall height of the second IC die104, and thus, the overall 3D IC stack ofFIG.22.

FIG.23illustrates a flow diagram of some embodiments of a method2300corresponding toFIGS.7-22.

While method2300is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At act2302, a semiconductor device is formed on a frontside of a semiconductor substrate.FIG.7illustrates cross-sectional view700of some embodiments corresponding to act2302.

At act2304, a first dielectric layer is formed over a backside of the semiconductor substrate.FIG.8illustrates cross-sectional view800of some embodiments corresponding to act2304.

At act2306, a first opening in the first dielectric layer is formed to expose a surface of the backside of the semiconductor substrate.FIG.9illustrates cross-sectional view900of some embodiments corresponding to act2306.

At act2308, a backside contact is formed within the first opening and comprises a first material, wherein the backside contact has an upper surface substantially coplanar with an upper surface of the first dielectric layer.FIGS.10and11illustrate cross-sectional views1000and1100, respectively, of some embodiments corresponding to act2308.

At act2310, a second dielectric layer is formed over the first dielectric layer and the backside contact.FIG.12illustrates cross-sectional view1200of some embodiments corresponding to act2310.

At act2312, a second opening is formed that extends completely through the first dielectric layer, the second dielectric layer, and the semiconductor substrate.FIG.13illustrates cross-sectional view1300of some embodiments corresponding to act2312.

At act2314, a through substrate via is formed in the second opening and comprises a second material.FIG.17illustrates cross-sectional view1700of some embodiments corresponding to act2314.

At act2316, bonding dielectric layers, bonding vias, bonding wire layers are deposited over the second dielectric layer, wherein the backside contact is coupled to the bonding vias and the bonding wire layers.FIGS.18-21illustrates cross-sectional views1800-2100of some embodiments corresponding to act2316.

Therefore, the present disclosure relates to a method of forming a backside contact on a backside of a semiconductor substrate before a through substrate via such that the backside contact may aid in heat dissipation away from the semiconductor substrate without increasing dimensions of an overall 3D IC stack comprising the through substrate via and the backside contact.

Accordingly, in some embodiments, the present disclosure relates to a three-dimensional (3D) integrated circuit (IC) stack comprising: a first IC die comprising a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure; a second IC die comprising a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate, wherein the second bonding structure faces the first bonding structure; and a first backside contact extending from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first interconnect structure or the second interconnect structure.

In other embodiments, the present disclosure relates to an integrated circuit (IC) die comprising: a semiconductor substrate; a semiconductor device integrated on a frontside of the semiconductor substrate; an interconnect structure arranged on the frontside of the semiconductor substrate, coupled to the semiconductor device, and comprising interconnect vias and interconnect wires embedded within dielectric layers; a first bonding structure arranged on the interconnect structure; a second bonding structure arranged on a backside of the semiconductor substrate and comprising bonding wire layers and bonding vias within a bonding dielectric structure; a backside contact arranged within the second bonding structure and coupled to the bonding wire layers and the bonding vias of the second bonding structure, wherein a bottommost surface of the backside contact is thermally coupled to the backside of the semiconductor substrate, wherein a topmost surface of the backside contact is arranged above a bottommost surface of the semiconductor substrate; and a through substrate via (TSV) extending through the semiconductor substrate and from the second bonding structure to the interconnect structure, wherein a topmost surface of the TSV is above the topmost surface of the backside contact.

In yet other embodiments, the present disclosure relates to a method of forming an integrated circuit, the method comprising: forming a semiconductor device on a frontside of a semiconductor substrate; depositing a first dielectric layer over a backside of the semiconductor substrate; patterning the first dielectric layer to form a first opening in the first dielectric layer, wherein the first opening exposes a surface of the backside of the semiconductor substrate; filling the first opening with a first material; performing a first removal process to remove the first material arranged over the first dielectric layer to form a backside contact comprising the first material in the first opening of the first dielectric layer; depositing a second dielectric layer over the first dielectric layer and the backside contact; patterning the second dielectric layer and the first dielectric layer to form a second opening that extends completely through the first dielectric layer, the second dielectric layer, and the semiconductor substrate; filling the second opening with a second material; performing a second removal process to form a through substrate via (TSV) comprising the second material in the second opening; and forming more dielectric layers, bonding vias, and bonding wire layers over the second dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, wherein the backside contact is coupled to the bonding vias and the bonding wire layers.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.