Patent ID: 12238936

DETAILED DESCRIPTION

The embodiments will be described in detail with reference to the drawings. The description will use the same reference signs for elements or components having the same or substantially the same functions and configurations.

For each embodiment below, where multiple elements or components of the same type may be involved (e.g., circuits, interconnects, a variety of voltages and signals, and so on), the description may add different numerals or alphabetic letters to the ends of the respective reference signs for discrimination therebetween. If discrimination between elements or components is not required, the description will omit such additional numerals or alphabetic letters (so that the elements, etc. are denoted only by the corresponding reference signs).

In general, according to one embodiment, a memory device includes: a switching element including a first conductive layer, a second conductive layer, and a variable resistive layer between the first conductive layer and the second conductive layer; and a memory element electrically connected in series with the switching element, wherein at least one of the first conductive layer or the second conductive layer includes a first layer, a second layer between the first layer and the variable resistive layer, and a third layer between the first layer and the second layer, each of the first layer and the second layer is selected from a layer including carbon, a layer including nitrogen and carbon, a layer including nitrogen and titanium, a layer including nitrogen and tantalum, a layer including tungsten, a layer including nitrogen and tungsten, and a layer including platinum, and the third layer includes at least one selected from lithium, sodium, magnesium, calcium, titanium, or lanthanum.

(1) Embodiments

A memory device100according to an embodiment will be described with reference toFIGS.1to16.

[a] Examples of Configurations

FIGS.1to12will be referred to for describing exemplary configurations, etc. associated with the memory device100according to the embodiment.

(a-1) Overall Configuration

FIG.1is a diagram showing an exemplary configuration of the memory device100according to the embodiment.

As shown inFIG.1, the memory device100according to the embodiment is connected to a device900located outside the memory device100(hereinafter, an “external device900”).

The external device900sends a command CMD, an address ADR, and a control signal CNT to the memory device100. Data DT is transferred between the memory device100and the external device900. For write operations, the external device900sends data to be written in the memory device100(hereinafter, “write data”) to the memory device100. For read operations, the external device900receives data read at the memory device100(hereinafter, “read data”) from the memory device100.

The memory device100according to the present embodiment includes a memory cell array110, a row control circuit120, a column control circuit130, a write circuit140, a read circuit150, a voltage generation circuit160, an input/output circuit170, and a control circuit180.

The memory cell array110includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL.

The multiple memory cells MC are associated with multiple rows and columns in the memory cell array110. Each memory cell MC is connected to a corresponding one of the multiple word lines WL. Also, each memory cell MC is connected to a corresponding one of the multiple bit lines BL.

The row control circuit120is connected to the memory cell array110via the word lines WL. The row control circuit120receives a row address of the address ADR (or a decoding result for a row address) in the memory cell array110. The row control circuit120controls the multiple word lines WL based on the decoding results for row addresses. The row control circuit120, in this manner, sets each of the multiple word lines WL (multiple rows) to either a selected state or a non-selected state. Hereinafter, a word line WL set to the selected state will be called a “selected word line WL”, and the word lines WL other than the selected word line WL will be called “non-selected word lines WL”.

The column control circuit130is connected to the memory cell array110via the bit lines BL. The column control circuit130receives a column address of the address ADR (or a decoding result for a column address) in the memory cell array110. The column control circuit130controls the multiple bit lines BL based on the decoding results for column addresses. The column control circuit130, in this manner, sets each of the multiple bit lines BL (multiple columns) to either a selected state or a non-selected state. Hereinafter, a bit line BL set to the selected state will be called a “selected bit line BL”, and the bit lines BL other than the selected bit line BL will be called “non-selected bit lines BL”.

The write circuit140writes data in the memory cells MC. The write circuit140applies a voltage (or a current) for data write to each of the selected word line WL and the selected bit line BL. Accordingly, selected memory cells MC are supplied with a given write voltage (or a given write current). The write circuit140is adapted to supply one of various write voltages to the selected memory cell MC according to the write data. For example, such various write voltages may each have a polarity (a bias direction) according to corresponding write data. In one example, the write circuit140includes components such as a write driver (not illustrated) and a write sink (not illustrated).

The read circuit150reads data from the memory cells MC. The read circuit150amplifies a signal that has been output to the selected bit line BL from the selected memory cell MC. The read circuit150specifies data in the memory cell MC based on the amplified signal. In one example, the read circuit150includes components such as a preamplifier (not illustrated), a sense amplifier (not illustrated), a read driver (not illustrated), and a read sink (not illustrated).

The voltage generation circuit160uses a source voltage from the external device900to generate voltages for the memory cell array110to perform various operations. In one instance, the voltage generation circuit160generates various voltages for use in write operations. The voltage generation circuit160outputs generated voltages to the write circuit140. In another instance, the voltage generation circuit160generates various voltages for use in read operations. The voltage generation circuit160outputs generated voltages to the read circuit150.

The input/output circuit170functions as an interface circuit between the memory device100and the external device900for each of the signals such as ADR, CMD, CNT, and DT. The input/output circuit170passes the address ADR from the external device900to the control circuit180. The input/output circuit170passes the command CMD from the external device900to the control circuit180. The input/output circuit170allows the control signal CNT, which may be of various contents, to be communicated between the external device900and the control circuit180. The input/output circuit170passes write data DT from the external device900to the write circuit140. The input/output circuit170passes data DT from the read circuit150as read data to the external device900.

The control circuit180(also called a “sequencer”, a “state machine”, or an “internal controller”) decodes the command CMD. Based on the result of decoding the command CMD, and also based on the control signal CNT, the control circuit180controls operations of the components in the memory device100, including the row control circuit120, the column control circuit130, the write circuit140, the read circuit150, the voltage generation circuit160, and the input/output circuit170. The control circuit180decodes the address ADR. The control circuit180sends the result of decoding the address ADR to the row control circuit120, the column control circuit130, etc. In one example, the control circuit180includes components such as a register circuit (not illustrated) for temporary storage of the command CMD and the address ADR. Note that such a register circuit, a circuit for decoding the command CMD (a command decoder), and a circuit for decoding the address ADR (an address decoder) may be disposed outside the control circuit180and within the memory device100.

(a-2) Memory Cell Array

FIGS.2to5will be referred to for describing an exemplary configuration, etc. of the memory cell array110in the memory device100according to the embodiment.

FIG.2is an equivalent circuit diagram showing an exemplary configuration of the memory cell array110in the memory device100according to the embodiment.

As shown inFIG.2, multiple memory cells MC in the memory cell array110are arranged in a matrix pattern. Each memory cell MC is connected to a corresponding one of multiple bit lines BL (BL<0>, BL<1>, . . . BL<i−1>) and a corresponding one of multiple word lines WL (WL<0>, WL<1>, . . . WL<j−1>). Here, i and j are each an integer equal to or greater than 2.

The memory cells MC each include a memory element1and a switching element2.

The memory element1is, for example, a variable resistive element. The memory element1changes its resistive state to one of multiple resistive states (e.g., a low resistive state and a high resistive state) according to a supplied voltage (or current). The memory element1can store data by associating the resistive state of the element1with data (e.g., data “0” or data “1”).

The switching element2(also called a “selector element” or simply a “selector”) functions as a selecting element for the respective memory cell MC. The switching element2functions to control the supply of a voltage (or a current) to the corresponding memory element1for operations of writing data to this memory element1and reading data from this memory element1.

In one example, when a voltage applied to a given memory cell MC is lower than the threshold voltage of the switching element2in this memory cell MC, the switching element2is set to an off state (a high resistive state, a non-conductive state). The switching element2here blocks the supply of a voltage (a current) to the memory element1. When a voltage applied to a given memory cell MC is equal to or higher than the threshold voltage of the switching element2in this memory cell MC, the switching element2is set to an on state (a low resistive state, a conductive state). The switching element2here supplies a voltage (a current) to the memory element1.

The switching element2is adapted to switch between allowing and not allowing a current flow in the corresponding memory cell MC according to the size of the voltage applied to the memory cell MC, regardless of the direction of the current flowing in the memory cell MC.

The switching element2is, for example, a two-terminal type element.

FIGS.3to5are diagrams for explaining exemplary structures of the memory cell array110in the memory device100according to the embodiment.FIG.3is an overhead view for explaining an exemplary structure of the memory cell array110.FIG.4is a schematic sectional view showing a sectional structure of the memory cell array110, taken along a first direction (a first axis).FIG.5is a schematic sectional view showing a sectional structure of the memory cell array110, taken along a second direction (a second axis). In the examples shown inFIGS.3to5, the first direction conforms to a Y direction, and the second direction conforms to an X direction.

As shown inFIGS.3to5, the memory cell array110is provided above the top face of a substrate90.

The X direction is a direction parallel to the top face of the substrate90. The Y direction is a direction parallel to the top face of the substrate90and orthogonal to the X direction. Hereinafter, a plane parallel to the top face of the substrate90will be called an X-Y plane. A direction (an axis) perpendicular to the X-Y plane will be called a Z direction (a Z axis). A plane extending along the X direction and the Z direction will be called an X-Z plane. A plane extending along the Y direction and the Z direction will be called a Y-Z plane.

Multiple interconnects50(conductive layers) are provided above the top face of the substrate90in the Z direction via an insulation layer91. The interconnects50are arranged along the Y direction. The interconnects50each extend in the X direction. The interconnects50function as, for example, respective word lines WL.

Multiple interconnects51(conductive layers) are provided above the multiple interconnects50in the Z direction. The interconnects51are arranged along the X direction. The interconnects51each extend in the Y direction. The interconnects51function as, for example, respective bit lines BL.

Multiple memory cells MC are provided between the interconnects50and the interconnects51. The memory cells MC are arranged in a matrix pattern within the X-Y plane.

The memory cells MC arranged along the X direction are disposed on one interconnect50. The memory cells MC arranged along the X direction are thus connected to the common word line WL.

The memory cells MC arranged along the Y direction are disposed under one interconnect51. The memory cells MC arranged along the Y direction are thus connected to the common bit line BL.

In one example where the memory cell array110has a circuit configuration as shown inFIG.2, each switching element2is provided below the corresponding memory element1in the Z direction. The switching element2here is arranged between the memory element1and the interconnect (word line)50. The memory element1is arranged between the interconnect (bit line)51and the switching element2.

As such, each memory cell MC is constituted as a stack of the memory element1and the switching element2. With such memory cells MC, the memory cell array110has a stack type structure. Note that the memory cells MC may have a tapered sectional shape according to the processes (e.g., an etching method) employed for forming the memory cell array110.

FIGS.4and5assume an example where the insulation layer91is disposed between the multiple interconnects50and the substrate90. If the substrate90is a semiconductor substrate, one or more field-effect transistors (not illustrated) may be provided on one or more semiconductor regions of the top face of the substrate90. The field-effect transistors are covered by the insulation layer91. The field-effect transistors on the substrate90are circuit components of the row control circuit120, etc. The field-effect transistors are connected to the memory cell array110via contact plugs (not illustrated) and interconnects (not illustrated) formed in the insulation layer91. Such circuits for controlling operations of the memory cell array110may be provided below the memory cell array110in the Z direction. Note that if the substrate90is a substrate with an insulating property, the multiple interconnects50may be disposed directly on the top face of the substrate90without the intervening insulation layer91.

The stack type memory cell array110is not limited to the exemplary circuit configurations and structures shown inFIGS.2to5. The circuit configuration and structure of the memory cell array110may be discretionarily modified according to the connections of the memory element1and the switching element2to the corresponding bit line BL and the corresponding word line WL. For example, the memory cell array110having a circuit configuration as shown inFIG.2may adopt a structure other than the exemplary structures shown inFIGS.3to5. As one example, each switching element2may be provided above the corresponding memory element1in the Z direction. In this case, the interconnects50are used as bit lines BL and the interconnects51are used as word lines WL.

(a-3) Memory Cell

FIG.6is a sectional view showing an exemplary structure of a memory cell MC in the memory device100according to the embodiment.

As shown inFIG.6, in the memory cell MC as a stack, the memory element1and the switching element2are arranged along the Z direction. The description of this embodiment assumes that the memory element1is disposed above the switching element2in the Z direction.

In one exemplary implementation, the variable resistive element serving as the memory element1is a magnetoresistive effect element. In such an implementation, the memory device100according to the embodiment is a magnetic memory as represented by a magnetoresistive random access memory (MRAM).

<Exemplary Structure of Magnetoresistive Effect Element>

In one example, the magnetoresistive effect element1at least includes two magnetic layers11and13and a non-magnetic layer12. The non-magnetic layer12is arranged between the two magnetic layers11and13in the Z direction. In the example shown inFIG.6, these layers are arranged in the order of the magnetic layer11, the non-magnetic layer12, and the magnetic layer13along the Z direction from the side of the word line WL (i.e., the interconnect50) toward the side of the bit line BL (i.e., the interconnect51).

The two magnetic layers11and13and the non-magnetic layer12form a magnetic tunnel junction (MTJ). Hereinafter, the magnetoresistive effect element1including this MTJ will also be called an “MTJ element1”. The non-magnetic layer12in the MTJ element1will also be called a “tunnel barrier layer12”.

Examples of the magnetic layers11and13include a ferromagnetic layer including (containing), for example, cobalt (Co), iron (Fe), and/or boron (B), etc. The magnetic layers11and13may each be a mono-layer film (e.g., an alloy film) or a multi-layer film (e.g., an artificial lattice film). Examples of the tunnel barrier layer12include an insulation layer including (containing) magnesium oxide. The tunnel barrier layer12may be a mono-layer film or a multi-layer film.

The present embodiment assumes that the MTJ element1is a magnetoresistive effect element of a perpendicular magnetization type.

For example, the magnetic layers11and13each have a perpendicular magnetic anisotropy. The direction of easy magnetization axis of the magnetic layers11and13is perpendicular to the layer faces (film surfaces) of the magnetic layers11and13. The magnetic layers11and13each have a magnetization perpendicular to the layer faces of the magnetic layers11and13. The magnetization direction of each of the magnetic layers11and13is parallel to the direction (Z direction) in which the magnetic layers11and13are arranged.

One of the two magnetic layers11and13has an invariable magnetization direction, while the other has a variable magnetization direction. The MTJ element1is adapted to take multiple resistive states (resistance values) according to the relative relationship (magnetization alignment) between the magnetization direction of one magnetic layer and the magnetization direction of the other magnetic layer.

In the example shown inFIG.6, the magnetization direction of the magnetic layer13is variable. The magnetization direction of the magnetic layer11is invariable (in a fixed state). Hereinafter, the magnetic layer13having a variable magnetization direction will be called a “storage layer13”. The magnetic layer11having an invariable (fixed) magnetization direction will be called a “reference layer11”. There are other terms for the storage layer13, such as a “free layer”, a “free magnetization layer”, and a “variable magnetization layer”. There are other terms for the reference layer11, such as a “pin layer”, a “pinned layer”, an “invariable magnetization layer”, and a “fixed magnetization layer”.

In the context of this embodiment, an invariable or a fixed-state magnetization direction of the reference layer (one magnetic layer) means that a current or a voltage supplied to the MTJ element1for changing the magnetization direction of the storage layer13does not entail a change in the magnetization direction of the reference layer11before and after the supply of the current or the voltage.

When the magnetization direction of the storage layer13conforms to the magnetization direction of the reference layer11(namely, when the magnetization alignment state of the MTJ element1is a parallel alignment state), the MTJ element is in a first resistive state. When the magnetization direction of the storage layer13differs from the magnetization direction of the reference layer11(namely, when the magnetization alignment state of the MTJ element1is an anti-parallel alignment state), the MTJ element is in a second resistive state different from the first resistive state. The MTJ element1in the second resistive state (the anti-parallel alignment state) has a resistance value higher than that of the MTJ element1in the first resistive state (the parallel alignment state). Hereinafter, for the magnetization alignment state of the MTJ element1, the parallel alignment state may also be called a “P state”, and the anti-parallel alignment state may also be called an “AP state”.

In one example, the MTJ element1includes two electrodes19A and19B. The magnetic layers11and13and the tunnel barrier layer12are arranged between the two electrodes19A and19B in the Z direction. The reference layer11is arranged between the electrode19A and the tunnel barrier layer12. The storage layer13is arranged between the electrode19B and the tunnel barrier layer12.

For exemplary implementation, a shift cancellation layer (not illustrated) may be provided within the MTJ element1. In such an implementation, the shift cancellation layer is arranged between the reference layer11and the electrode19A. The shift cancellation layer is a magnetic layer for mitigating the influence of a stray magnetic field from the reference layer11. When the MTJ element1includes the shift cancellation layer, a non-magnetic layer (not illustrated) is provided between the shift cancellation layer and the reference layer11. The non-magnetic layer is, for example, a metal layer such as a ruthenium (Ru) layer. The shift cancellation layer is anti-ferromagnetically bonded to the reference layer11via the non-magnetic layer. Accordingly, the stack including the reference layer11and the shift cancellation layer forms a synthetic anti-ferromagnetic (SAF) structure. In the SAF structure, the shift cancellation layer has a magnetization direction opposite to the magnetization direction of the reference layer11. The SAF structure contributes to the stable fixation of the magnetization direction of the reference layer11. Note that the two magnetic layers and the non-magnetic layer, together forming the SAF structure, may be collectively called a “reference layer”.

For exemplary implementation, the MTJ element1may include at least one of a base layer (not illustrated) and/or a cap layer (not illustrated). The base layer is arranged between the magnetic layer11(the reference layer in this example) and the electrode19A. The base layer is a non-magnetic layer, such as a conductive compound layer. The base layer is a layer for improving the properties (e.g., crystallinity and/or magnetic characteristics) of the magnetic layer11adjacent to the base layer. The cap layer is arranged between the magnetic layer13(the storage layer in this example) and the electrode19B. The cap layer is a non-magnetic layer, such as a conductive compound layer. The cap layer is a layer for improving the properties (e.g., crystallinity and magnetic characteristics) of the magnetic layer13adjacent to the cap layer. Note that the base layer and the cap layer may be handled as parts of the respective electrodes19(19A and19B).

<Exemplary Structure of Switching Element>

When the switching element2is a two-terminal type element as shown inFIG.6, the switching element2at least includes a variable resistive layer20(also called a “switching layer20” or a “selector layer20” below) and two electrodes21A and21B (electrode layers). The switching layer20is provided between the two electrodes21A and21B in the Z direction. The switching layer20is adapted to take multiple resistive states.

In the example shown inFIG.6, the electrode21A is arranged below the switching layer20in the Z direction, and the electrode21B is arranged above the switching layer20in the Z direction. In one example, the electrode21A is arranged between the interconnect50and the switching layer20. The electrode21B is arranged between the switching layer20and the MTJ element1.

The switching layer20is connected to the interconnect50via the electrode21A. Also, the switching layer20is connected to the MTJ element1via the electrode21B.

Hereinafter, among the two electrodes21A and21B included in the switching element2, the electrode21A arranged on the side closer to the substrate90may also be called a “lower electrode21A”. Among the two electrodes21A and21B, the electrode21B arranged above the lower electrode21A in the Z direction (that is, the electrode on the side opposite the substrate90) may also be called an “upper electrode21B”.

The switching layer20changes its resistive state to a high resistive state (a non-conductive state) or a low resistive state (a conductive state) according to the voltage applied to the switching element2(the memory cell MC). The switching layer20being in the high resistive state represents the switching element2being in an off state. The switching layer20being in the low resistive state represents the switching element2being in an on state.

When the corresponding memory cell MC is set to the selected state, the switching element2is turned on, and therefore, the resistive state of the switching layer20is in the low resistive state. When the corresponding memory cell MC is set to the non-selected state, the switching element2is turned off, and therefore, the resistive state of the switching layer20is in the high resistive state. Note that the changes in the resistive state of the switching layer20may be made dependent on a current flowing in the switching element2(the memory cell MC), e.g., the size of the current, according to the materials of the switching layer20.

In the present embodiment, the electrodes21A and21B of the switching element2each have a stack structure including multiple layers210(210aor210b),211(211aor211b), and212(212aor212b). In each of the electrodes21A and21B, the layer210is arranged between the layer211and the layer212. The layers210,211, and212are, for example, conductive layers.

In the present embodiment, the layer210includes (contains) a material that can adsorb and/or store hydrogen (hereinafter, the material will be called a “hydrogen storing material”). For discriminating purposes, the description may also call the layer210a “hydrogen storing layer210”.

The layers211and212include (contain) a material that can prevent other layers (e.g., the hydrogen storing layer210) from causing chemical reactions (e.g., oxidation or nitriding). In exemplary implementations, the layers211and212prevent oxidation of the hydrogen storing layer210. For discriminating purposes, the description may call the layers211and212“oxidation preventing layers211and212” (or “reaction preventing layers211and212”).

The lower electrode21A includes a hydrogen storing layer210aand two oxidation preventing layers211aand212a. The hydrogen storing layer210aand the two oxidation preventing layers211aand212aare stacked in the Z direction. One of the two oxidation preventing layers211aand212a, namely, the oxidation preventing layer212a, is provided below the switching layer20in the Z direction. The hydrogen storing layer210ais arranged between the oxidation preventing layer212aand the switching layer20. The oxidation preventing layer212ais arranged between the hydrogen storing layer210aand the interconnect50. The other oxidation preventing layer211ais provided between the hydrogen storing layer210aand the switching layer20.

The lower electrode21A closely contacts the switching layer20via the entire interface between the lower electrode21A and the switching layer20. For example, the oxidation preventing layer211ais in direct contact with the entire bottom face of the switching layer20without any voids occurring between the oxidation preventing layer211aand the switching layer20.

The upper electrode21B includes a hydrogen storing layer210band two oxidation preventing layers211band212b. The hydrogen storing layer210band the two oxidation preventing layers211band212bare stacked in the Z direction. One of the two oxidation preventing layers211band212b, namely, the oxidation preventing layer212b, is provided above the switching layer20in the Z direction. The oxidation preventing layer212bis arranged between the hydrogen storing layer210band the MTJ element1(the electrode19A). The hydrogen storing layer210bis arranged between the oxidation preventing layer212band the switching layer20. The other oxidation preventing layer211bis provided between the hydrogen storing layer210band the switching layer20.

The upper electrode21B closely contacts the switching layer20via the entire interface between the upper electrode21B and the switching layer20. For example, the oxidation preventing layer211bis in direct contact with the entire upper face of the switching layer20without any voids occurring between the oxidation preventing layer211band the switching layer20.

As such, in each electrode21of the switching element2, the hydrogen storing layer210is sandwiched between the two oxidation preventing layers211and212. The hydrogen storing layer210is adjacent to the switching layer20via the oxidation preventing layer211.

FIG.7will be referred to for describing materials used for the switching element2in the MRAM100according to the embodiment.FIG.7shows examples of the materials employed for the respective layers20,210,211, and212of the switching element2in the MRAM100according to the embodiment.

As shown inFIG.7, the switching layer20includes, as its constituting element or elements, at least one selected from phosphorus (P), arsenic (As), sulfur (S), selenium (Se), antimony (Sb) and/or tellurium (Te).

The switching layer20is formed of a material which is, for example, an insulator containing a dopant (an impurity).

One example of such an insulator used for the switching layer20is a silicon oxide. The dopant added to the insulator of the switching layer20is an impurity that contributes to the electrical conduction in the insulator. If the material of the switching layer20is a silicon oxide, the dopant added to the silicon oxide is phosphorus, arsenic, sulfur, selenium, antimony and tellurium. Note that types or kinds of the dopant added to the silicon oxide serving as the switching layer20are not limited to these exemplary elements.

The switching layer20therefore includes at least one of phosphorus, arsenic, sulfur, selenium, antimony and/or tellurium.

Note that as long as the switching layer20includes at least one of phosphorus, arsenic, sulfur, selenium, antimony and/or tellurium, the switching layer20may be formed of a material other than this exemplary material, and such other material may be a conductive or insulating oxide, a conductive or insulating nitride, or a semiconductor.

Each of the hydrogen storing layers210(210aand210b) is a layer including at least one selected from lithium (Li), sodium (Na), magnesium (Mg), calcium (Ca), titanium (Ti), and/or lanthanum (La). The hydrogen storing layer210may be a layer made of a single element, such as a lithium layer, a sodium layer, a magnesium layer, a calcium layer, a titanium layer, or a lanthanum layer. The hydrogen storing layer210may be a lithium alloy layer, a sodium alloy layer, a magnesium alloy layer, a calcium alloy layer, a titanium alloy layer, or a lanthanum alloy layer. The hydrogen storing layer210may instead be a lithium compound layer, a sodium compound layer, a magnesium compound layer, a calcium compound layer, a titanium compound layer, or a lanthanum compound layer. Note that the hydrogen storing layer210, when it is a layer made of a single element, does not need to have a purity (an element concentration) of 100%.

Examples which may be used as each hydrogen storing layer210include a magnesium layer, a magnesium-nickel (Ni) alloy layer (such as an Mg2Ni layer), and a magnesium-copper (Cu) alloy layer (such as an Mg2Cu layer). The magnesium layer serving as the hydrogen storing layer210does not need to contain magnesium at a purity of 100%, but it may contain unintended impurities as long as the chemical characteristics of magnesium (e.g., capability of adsorbing and/or storing hydrogen) are retained.

Each hydrogen storing layer210may include multiple layers. In this case, at least one of these multiple layers of the hydrogen storing layer210includes at least one selected from lithium, sodium, magnesium, calcium, titanium, and/or lanthanum.

The hydrogen storing layer210adsorbs hydrogen or stores hydrogen within the layer210.

As such, the hydrogen storing layer210may further include hydrogen (H) in addition to at least one selected from lithium, sodium, magnesium, calcium, titanium, and/or lanthanum described above. The hydrogen storing layer210may also contain a compound (a hydrogen compound) of hydrogen with an element or elements used for the hydrogen storing layer210described above, i.e., at least one selected from lithium, sodium, magnesium, calcium, titanium, and/or lanthanum.

The hydrogen storing layer210varies its properties according to the types or kinds of elements and materials described above.

For example, the quantity of hydrogen that can be stored in the hydrogen storing layer210varies according to the element and material used for this hydrogen storing layer210.

The hydrogen storing layer210made of the above element or elements and material may have reversibility in terms of the hydrogen adsorbing and/or storing behavior. For example, the hydrogen storing layer210could release stored hydrogen under a given condition (e.g., an ambient temperature condition). To prevent the release of hydrogen due to temperature conditions, the hydrogen storing layer210preferably has a high hydrogen-releasing temperature. This enables the hydrogen storing layer210to prevent hydrogen from being detached from the hydrogen storing layer210, and to accordingly maintain its hydrogen storing state.

Note that since the hydrogen storing layer210is a constituting member (a part) of the corresponding electrode21, it is preferable that the hydrogen storing layer210be conductive also in the state where hydrogen is contained in its layer210.

The oxidation preventing layers211and212are each constituted by at least one selected from a layer including (containing) carbon (C) (e.g., a carbon layer), a layer including nitrogen (N) and carbon (e.g., a carbon nitride layer), a layer including nitrogen and titanium (e.g., a titanium nitride (TiN) layer), a layer including nitrogen and tantalum (Ta) (e.g., a tantalum nitride (TaN) layer), a layer including tungsten (W) (e.g., a tungsten layer), a layer including nitrogen and tungsten (e.g., a tungsten nitride (WN) layer), and/or a layer including platinum (Pt) (e.g., a platinum layer). Each of the oxidation preventing layers211and212may include multiple layers.

The oxidation preventing layers211and212prevent and suppress oxidation of the hydrogen storing layer210.

The switching layer20has a thickness t0in the Z direction (a dimension in the Z direction). The hydrogen storing layer210has a thickness t1in the Z direction (a dimension in the Z direction). The oxidation preventing layer211has a thickness t2in the Z direction (a dimension in the Z direction). The oxidation preventing layer212has a thickness t3in the Z direction (a dimension in the Z direction).

For example, when the thickness t0of the switching layer20is a value within the range of 5 nm to 40 nm, it is preferable that the thickness t1of the hydrogen storing layer210be a value within the range of 1 nm to 20 nm and also equal to or smaller than the thickness t0. In this case, each of the thicknesses t2and t3of the respective oxidation preventing layers211and212is preferably a value within the range of 1 nm to 5 nm and also equal to or smaller than the thickness t1.

In an exemplary implementation, when the thickness t0of the switching layer20is 10 nm, the thickness t1of the hydrogen storing layer210is 5 nm. The thicknesses t2and t3of the respective oxidation preventing layers211and212in this case are each 3 nm.

Note that the thickness t2of the oxidation preventing layer211may be different from the thickness t3of the oxidation preventing layer212. Also, the thickness t1of the oxygen storing layer210ain the lower electrode21A may be equal to or different from the thickness t1of the oxygen storing layer210bin the upper electrode21B. The thickness t2of the oxidation preventing layer211ain the lower electrode21A may be equal to or different from the thickness t2of the oxidation preventing layer211bin the upper electrode21B. The thickness t3of the oxidation preventing layer212ain the lower electrode21A may be equal to or different from the thickness t3of the oxidation preventing layer212bin the upper electrode21B.

The hydrogen storing layer210could deteriorate or lose the hydrogen adsorbing and/or storing function due to oxidation or nitriding of its constituting member (e.g., magnesium). The elements that may be used for the hydrogen storing layer210described above, such as lithium, sodium, magnesium, calcium, titanium, and lanthanum, are, according to their electronegativity, easily bonded to oxygen (O) (or nitrogen (N)).

According to the embodiment, the oxidation preventing layers211and212are arranged adjacent to the hydrogen storing layer210in the electrode21so that the oxidation preventing layers211and212can prevent the oxidation (or nitriding) of the hydrogen storing layer210.

Therefore, the MRAM100according to the embodiment can secure the hydrogen adsorbing and/or storing function of the hydrogen storing layer210.

The MRAM100according to the embodiment, with the electrode21including the hydrogen storing layer210, can suppress the bonding between the constituting element or elements in the switching layer20(phosphorus, arsenic, selenium, etc.) and hydrogen.

Consequently, the MRAM100according to the embodiment can suppress the degradation of characteristics of the switching element2, and also defects in the switching element2.

<Hydrogen Storage Model>

FIG.8will be referred to for describing an exemplary model of the hydrogen adsorption and storage in hydrogen storing layer210of the switching element2in the MRAM100according to the embodiment. InFIG.8, illustrations (a), (b), and (c) show the mechanism of how the hydrogen storing layer210adsorbs and stores hydrogen in the MRAM100according to the embodiment.

Processes performed during the manufacture of the MRAM100, for example, formation of insulation layers60and61or an organic substance layer, often cause hydrogen generation.

In the switching element2in the MRAM100according to the embodiment, the hydrogen storing layer210in the electrode21is capable of adsorbing and storing the generated hydrogen.

As shown in (a) ofFIG.8, the hydrogen storing layer210adsorbs hydrogen79(79aand79b). For example, the hydrogen storing layer210dissociates molecular hydrogen79a(i.e., a hydrogen molecule) into atomic hydrogen79b(i.e., hydrogen atoms) by the action of a constituting atom or atoms (or a constituting element or elements)70of the hydrogen storing layer20on the surface of the layer210.

The hydrogen storing layer210adsorbs the hydrogen79bon its surface, or takes in the hydrogen79b.

As shown in (b) ofFIG.8, each hydrogen atom79bis placed inside the crystal lattice of the constituting atoms70(e.g., at the interstitial site) in the hydrogen storing layer210. The hydrogen atom79bmay instead be placed near the constituting atom70by the attractive force occurring between this constituting atom70and the hydrogen atom79b.

This forms a solid solution of the hydrogen atoms79band the constituting atoms70in the hydrogen storing layer210.

As a result, the hydrogen atoms79bcan be relatively stably present in the hydrogen storing layer210without being detached from the vicinity of, or the inside of the crystal lattice of, the corresponding constituting atoms70, by the hydrogen adsorbing and storing effect of the hydrogen storing layer210exhibited according to the characteristics of the materials of the hydrogen storing layer210under the ambient conditions (e.g., a dissociating pressure, a temperature, etc.) of the hydrogen storing layer210.

When the hydrogen concentration in the hydrogen storing layer210increases, a chemical reaction between the constituting atoms70and the hydrogen atoms79btakes place in the solid solution. This can cause the hydrogen atoms79bto be chemically bonded to the constituting atoms70.

Accordingly, as shown in (c) ofFIG.8, a hydrogen compound (metal hydride) is formed from the hydrogen atoms79and the constituting atoms70(e.g., metal atoms) in the hydrogen storing layer210.

Note that the hydrogen atoms79band the constituting atoms70may be bonded to each other to form metal hydride without undergoing the above processes shown inFIGS.8(a) and (b).

With the hydrogen adsorption and storage model as above, the hydrogen storing layer210can adsorb and store hydrogen79in the switching element2in the MRAM100according to the embodiment.

FIGS.9to12schematically show hydrogen storing states which the electrodes21can take in the switching element2in the MRAM100according to the embodiment.

As shown inFIG.9, one implementation is that each hydrogen storing layer210(210aor210b) is converted in its entirety from a metal layer (e.g., an Mg layer) into a hydrogen compound layer219A (e.g., an MgH2layer). In such an implementation, the hydrogen compound layer219A is sandwiched between the oxidation preventing layers211and212in each electrode21.

Note that, in the example shown inFIG.9, the hydrogen atoms79may form a solid solution state by being dispersed throughout the inside of the hydrogen storing layer210without chemically reacting with the constituting atoms70. In this case, the hydrogen storing layer210includes, in the entirety of the layer210, a region219A where the hydrogen is dispersed to form a solid solution (hereinafter, a “hydrogen dispersed region”).

There are also implementations where, as shown in each ofFIGS.10,11, and12, a hydrogen-containing region is formed in a part or parts of the hydrogen storing layer210.

As shown inFIG.10, a hydrogen compound layer219B (or a hydrogen dispersed region219B) may be formed along each exposed surface of the hydrogen storing layer210(e.g., the side surface or surfaces of the hydrogen storing layer210in the X and/or Y directions).

As another implementation, a hydrogen compound layer or layers219C (or a hydrogen dispersed region or regions219C) may be randomly formed in the hydrogen storing layer210as shown inFIG.11.

As yet another implementation, a hydrogen compound layer219D (or a hydrogen dispersed region219D) in a layered profile may be formed in the hydrogen storing layer210as shown inFIG.12. For example, the hydrogen compound layer219D may be formed along the interface between the corresponding hydrogen storing layer210and oxidation preventing layer212, in a manner similar to the hydrogen compound layer219D in the lower electrode21A shown in the figure.

Note that, in contrast to the examples shown inFIGS.9to11, it is also possible to form the hydrogen compound layer219in only one of the two electrodes21A and21B instead of forming it in both of the electrodes21A and21B in the switching element2. Also, it is possible for the two electrodes21A and21B to adopt different respective arrangement conditions (formation conditions) of the hydrogen compound layers219.

With the electrodes21including the above hydrogen storing layer210in the switching element2, the MRAM100according to the embodiment can prevent and suppress the chemical reactions (compound formation) between the hydrogen79and the components or constituting members (constituting elements) of the switching layer20.

It is additionally noted that the MRAM100according to the embodiment may perform write operations and read operations using known techniques. The description will therefore omit explanations of the write operations and read operations of the MRAM100according to the embodiment.

[b] Manufacturing Method

FIGS.13to16will be referred to for describing a method for manufacturing the MRAM100according to the embodiment.

Each ofFIGS.13,14, and15is a sectional view of the memory cell array110taken along the Y direction (the Y-Z plane) and shows one of the steps in the method for manufacturing the MRAM100according to the embodiment.FIG.16is a sectional view of the memory cell array110taken along the X direction (the X-Z plane) and shows one of the steps in the method for manufacturing the MRAM100according to the embodiment.

As shown inFIG.13, the insulation layer91is formed on the substrate90. If the substrate90is a semiconductor substrate, circuitry components in the MRAM100, such as the row control circuit120and the column control circuit130, may be formed on the semiconductor substrate90. The insulation layer91covers the circuitry components formed on the semiconductor substrate90.

A conductive layer50X is formed on the insulation layer91by a sputtering method. The conductive layer50X is a layer for word lines (bit lines).

A stack300is formed on the conductive layer50X by a sputtering method or a chemical vapor deposition (CVD) method.

More specifically, multiple layers constituting the stack300are formed in the following manner.

A conductive layer21Xa is formed on the conductive layer50X. The conductive layer21Xa is a layer for the lower electrode in the switching element2.

A layer20X is formed on the conductive layer21Xa. The layer20X is, for example, a compound layer. The layer20X will serve as a switching layer (a variable resistive layer or a selector layer) in the switching element2. The switching layer20X includes (contains) at least one of phosphorus, arsenic, sulfur, selenium, antimony and/or tellurium.

A conductive layer21Xb is formed on the switching layer20X. The conductive layer21Xb is a layer for the upper electrode in the switching element2.

In the present embodiment, the conductive layers21Xa and21Xb each have a stack structure constituted by multiple layers210x,211x, and212x.

The layers211xand212xinclude at least one of a layer including carbon (e.g., a carbon layer), a layer including nitrogen and carbon (e.g., a carbon nitride layer), a layer including nitrogen and titanium (e.g., a titanium nitride layer), a layer including nitrogen and tantalum (e.g., a tantalum nitride layer), a layer including tungsten (e.g., a tungsten layer), a layer including nitrogen and tungsten (e.g., a tungsten nitride layer), and/or a layer including platinum (e.g., a platinum layer). The layers211xand212xserve as respective oxidation preventing layers.

The layer210xincludes at least one of lithium, sodium, magnesium, calcium, titanium, and/or lanthanum. The layer210xis a layer employing a hydrogen storing material (that is, serves as a hydrogen storing layer). The hydrogen storing layer210xis formed between the two oxidation preventing layers211xand212xin the Z direction.

With the oxidation preventing layers211xand212x, the hydrogen storing layer210xcan be prevented from being oxidized during manufacture. The oxidation preventing layer211xis formed between the hydrogen storing layer210xand the switching layer20X. In one example, when the switching layer20X is formed of a material containing oxygen, the oxidation preventing layer211xcan prevent oxygen from entering (diffusing into) the hydrogen storing layer210xduring the formation of the switching layer20X.

Therefore, the hydrogen storing layer210xcan be prevented from being oxidized.

A stack1X (also called an “MTJ stack1X” below) for forming the MTJ element is formed on the conductive layer21Xb.

A conductive layer19Xa is formed on the conductive layer21Xb. A magnetic layer11X is formed on the conductive layer19Xa. A non-magnetic layer12X is formed on the magnetic layer11X. A magnetic layer13X is formed on the non-magnetic layer12X. A conductive layer19Xb is formed on the magnetic layer13X.

In an example, the magnetic layer11X will serve as a reference layer. The magnetic layer13X will serve as a storage layer. The non-magnetic layer12X will serve as a tunnel barrier layer. The conductive layers19Xa and19Xb will serve as electrodes in the MTJ element.

Note that layers other than the layers11X,12X,13X,19Xa, and19Xb (e.g., a magnetic layer for forming a shift cancellation layer, a non-magnetic layer for forming a cap layer or a buffer layer, etc.) may also be formed in the MTJ stack1X.

For example, the oxidation preventing layer212xin the conductive layer21Xb can prevent the hydrogen storing layer210xfrom being oxidized during the formation of the MTJ stack1X.

Multiple mask layers80with a given pattern are formed on the stack300by a lithography process. In an example, the mask layers80each have a linear shape extending in the X direction. A slit (an opening) is formed between the mask layers80that are next to each other in the Y direction. The multiple mask layers80are arranged along the Y direction at predetermined pitches (intervals).

The mask layers80each include a hard mask (e.g., a silicon oxide layer or a silicon nitride layer) and/or a resist layer (e.g., an organic substance layer). The formation of the mask layers80tends to cause hydrogen generation. Since hydrogen has a relatively small atomic radius, the generated hydrogen enters the stack300and moves inside the stack300.

In the present embodiment as described above and with reference toFIG.8, the hydrogen79generated during manufacture is adsorbed by the hydrogen storing layer210xand stored in the hydrogen storing layer210x. For example, hydrogen-containing portions219(hydrogen compound layers, solid solution regions, or the like) are formed in each hydrogen storing layer210x. The hydrogen storing layer210xincludes the hydrogen compound layers219, or the solid solution regions219formed of hydrogen atoms and constituting atoms (e.g., magnesium).

Therefore, the embodiment can prevent the hydrogen79from entering the switching layer20X and chemically reacting with the constituting elements (e.g., phosphorus, arsenic, sulfur, selenium, antimony and/or tellurium) of the switching layer20X. For example, the embodiment can suppress generation of volatile products (such as PH3, AsH3, SbH3, H2S, H2Se, H2Te etc.) from the reaction between the hydrogen and the switching layer20X. Consequently, the embodiment can suppress the occurrence of events where the volatile products are volatilized and become gaseous products to trigger the separation between the switching layer20X and each conductive layer21X (21Xa or21Xb) or to form a gap between the switching layer20X and each conductive layer21X.

The embodiment can also prevent variations in characteristics of the switching element which could result from the detachment of constituting elements due to the chemical reactions between the hydrogen79and the switching layer20X or the formation of hydrogen compounds in the switching layer20X, or the like.

Note also that the oxidation preventing layers211xand212xare provided so that the hydrogen79adsorbed and/or stored by the hydrogen storing layer210xcan be prevented from moving (or diffusing) into the switching layer20X.

Moreover, the hydrogen storing layer210xcontributes to the prevention of the chemical reactions between the constituting members of the MTJ stack1X and the hydrogen79.

Subsequently, the stack300and the conductive layer50X are etched by, for example, an ion milling technique based on the pattern of the mask layers80. After etching the stack300and the conductive layer50X, the mask layers80are removed.

By subjecting the structure shown inFIG.13to the etching step, multiple interconnects50(e.g., word lines) each extending in the X direction are formed on the insulation layer91as shown inFIG.14. Multiple stacks300Y each extending in the X direction are formed on the respective interconnects50.

Each stack300Y includes an MTJ stack1Y extending in the X direction. A switching layer20Y and conductive layers21Ya and21Yb extend in the X direction. Each of the conductive layers21Ya and21Yb includes a hydrogen storing layer210yand oxidation preventing layers211yand212ywhich all extend in the X direction. The Y-direction side surfaces of the hydrogen storing layer210y, and also the Y-direction side surfaces of the oxidation preventing layers211yand212yare exposed.

An insulation layer60is formed in the spaces between the interconnects50next to each other in the Y direction as well as in the spaces between the stacks300Y next to each other in the Y direction.

Chemical reactions caused by a raw gas for forming the insulation layer60could generate hydrogen79(H) together with the synthesis of the insulation layer60. The hydrogen79generated during the formation of the insulation layer60is adsorbed and/or stored by the hydrogen storing layer210y.

After forming the insulation layer60, the top face of the insulation layer60is flattened by conducting, for example, chemical mechanical polishing with the top faces of the MTJ stacks1Y (conductive layers) used as stoppers, as shown inFIGS.15and16.

Subsequently, a conductive layer51Y is formed on the insulation layer60and the stacks300Y by a sputtering method.

Multiple mask layers81with a given pattern are formed on the conductive layer51Y by a lithography process. In an example, the mask layers81each have a linear shape extending in the Y direction. A slit is formed between the mask layers81that are next to each other in the X direction. The multiple mask layers81are arranged along the X direction at predetermined pitches (intervals).

As in the process explained with reference toFIG.13, the formation of the mask layers81would generate hydrogen79. The hydrogen79generated during the formation of the mask layers81is adsorbed and/or stored by the hydrogen storing layer210y.

Subsequently, the conductive layer51Y and the stacks300yare etched by, for example, an ion milling technique based on the pattern of the mask layers81. This etching divides each of the conductive layer51Y and the stacks300Y into two or more segments in the X direction.

Accordingly, multiple memory cells MC are formed above the substrate90as shown inFIGS.3to5. Multiple interconnects51(e.g., bit lines) each extending in the Y direction are formed above the memory cells MC. Due to this etching, the X-direction side surfaces of the hydrogen storing layer210, and also the X-direction side surfaces of the oxidation preventing layers211and212are exposed.

Subsequently, an insulation layer61is formed between the memory cells MC that are next to each other in the X direction, in a manner similar to the process explained with reference toFIG.14. Here, the hydrogen storing layer210adsorbs and/or stores hydrogen generated by the formation of the insulation layer61.

As an outcome of the manufacturing method described above, one or more hydrogen compound layers219(or one or more hydrogen dispersed regions219) can be formed in the hydrogen storing layer210as shownFIGS.9to12.

Subsequently, an insulation layer62is formed on the interconnects51and the insulation layers60and61.

By undergoing the above steps, the memory cell array110in the MRAM100according to the embodiment is fabricated.

Thereafter, known manufacturing processes are performed as appropriate to complete the MRAM100according to the embodiment.

[c] In Sum

An MRAM manufacturing process involves steps where a constituting member of the switching element in a memory cell could be exposed to a hydrogen-containing gas atmosphere.

A constituting member (e.g., a switching layer) of the switching element often includes a material or materials that can easily react with hydrogen.

The constituting element or elements (e.g., phosphorus, arsenic, sulfur, selenium, antimony and tellurium) contained in the switching layer reacts with hydrogen to generate a hydrogen compound.

In the event where a highly volatile hydrogen compound (a compound that can easily gasify, such as PH3, AsH3, SbH3, H2S, H2Se or H2Te) is generated, a hydrogen compound gas could be generated in the switching layer and discharged from the switching layer. This hydrogen compound gas could trigger the separation between the switching layer and a conductive layer (an electrode), or the formation of a gap (or a hydrogen compound gas region) between the switching layer and the conductive layer. As a result, a defect such as an opening or clearance between the electrode and the switching layer (that is, a failure in conduction between them) can occur in the switching element.

Once the constituting elements are detached from the switching layer due to generation of the hydrogen compound gas, or once the hydrogen compound is generated in the switching layer, the concentration of the constituting elements that contribute to the characteristics of the switching layer decreases. This could alter the characteristics of the switching element from the desired characteristics.

In the MRAM100according to the embodiment, the hydrogen storing layer210is provided in each electrode21of the switching element2. The hydrogen storing layer210is formed using a hydrogen storing material. The hydrogen storing layer210is a layer including, for example, at least one of lithium, sodium, magnesium, calcium, titanium, and/or lanthanum.

The hydrogen storing layer210has high hydrogen adsorbing and storing functions as compared to the switching layer20as well as to other constituting members in the MRAM100.

Therefore, the MRAM100according to the embodiment can prevent hydrogen from entering the switching layer20and chemically reacting with the constituting members of the switching layer20.

In an exemplary implementation, the hydrogen storing layer210may include hydrogen as a result of the hydrogen adsorbing and/or storing behavior. In the MRAM100according to the embodiment, therefore, one or more hydrogen compound layers219(or one or more hydrogen dispersed regions219) may be randomly provided to the hydrogen storing layer210.

According to the embodiment, the hydrogen storing layer210is sandwiched between two oxidation preventing layers211and212in each electrode21. The oxidation preventing layers211and212include at least one selected from a layer including carbon (e.g., a carbon layer), a layer including nitrogen and carbon (e.g., a carbon nitride layer), a layer including nitrogen and titanium (e.g., a titanium nitride layer), a layer including nitrogen and tantalum (e.g., a tantalum nitride layer), a layer including tungsten (e.g., a tungsten layer), a layer including nitrogen and tungsten (e.g., a tungsten nitride layer), and/or a layer including platinum (e.g., a platinum layer). The oxidation preventing layers211and212can prevent and suppress the oxidation (or nitriding) of the hydrogen storing layer210.

If the constituting member of the hydrogen storing layer210is oxidized or nitrided, the hydrogen storing layer210could lose or deteriorate its hydrogen adsorbing and/or storing functions.

When the oxidation preventing layers211and212are arranged adjacent to the hydrogen storing layer210as in the embodiment, the MRAM100can prevent the deterioration, etc., of the functions of the hydrogen storing layer210which could occur due to oxidation or nitriding of the hydrogen storing layer210.

Thus, according to the embodiment, the hydrogen storing layer210can keep adsorbing and storing hydrogen with a relatively high efficiency without losing or deteriorating such functions.

As described above, the MRAM100, i.e., a memory device according to the embodiment, can prevent and suppress the occurrence of separation between the electrode and the switching layer, or the formation of a gap between the electrode and the switching layer, which could be triggered by highly volatile hydrogen compounds.

Moreover, the MRAM100according to the embodiment can prevent and suppress variations in characteristics of the switching element which could be triggered by the formation of hydrogen compounds in the switching layer.

Therefore, the memory device according to the embodiment realizes enhanced reliability.

(2) Modifications

FIGS.17to19will be referred to for describing exemplary modifications of the memory device100according to the embodiment.

FIG.17is a sectional view showing an example of a modification of the switching element2in the memory cell MC of the memory device (e.g., the MRAM100) according to the embodiment.

As shown inFIG.17, the switching element2A includes two electrodes21B and28, and only the electrode21B may include a hydrogen storing layer210band oxidation preventing layers211band212b. The other electrode28(which is, for example, a mono-layered or multi-layered conductive layer) is a metal layer or a conductive compound layer.

FIG.18is a sectional view showing an example of a modification of the switching element2in the memory cell MC of the MRAM100according to the embodiment.

The example shown inFIG.17has assumed a structure where only the upper electrode21B in the switching element2A includes the hydrogen storing layer210band the oxidation preventing layers211band212b.

However, as shown inFIG.18, the switching element2B may adopt a structure in which only the lower electrode21A has a stack structure including a hydrogen storing layer210aand oxidation preventing layers211aand212a, while no hydrogen storing layer210is included in the upper electrode27(which is, for example, a mono-layered or multi-layered conductive layer) of the switching element2B. As one example, a conductive layer29is provided between the lower electrode21A and the interconnect50. Each of the upper electrode27and the conductive layer29is, for example, a metal layer or a conductive compound layer.

FIG.19is a sectional view showing an example of a modification of the switching element2in the memory cell MC of the MRAM100according to the embodiment.

As shown inFIG.19, the switching element2C includes electrodes21C and21D and each of these electrodes21C and21D may include multiple hydrogen storing layers210(210aand210b) and215(215aand215b).

In the lower electrode21C, the hydrogen storing layer215ais arranged between an oxidation preventing layer212aand the interconnect50. In the upper electrode21D, the hydrogen storing layer215bis arranged between an oxidation preventing layer212band the MTJ element1.

Each hydrogen storing layer215may be formed of a material different from the material of the hydrogen storing layers210. In one example, the material of the hydrogen storing layer215is palladium (Pd). Such a palladium layer25may be provided between the hydrogen storing layer210and the oxidation preventing layer211, or between the hydrogen storing layer210and the oxidation preventing layer212.

The MRAM100that includes the switching elements2A,2B, and/or2C of the respective modifications described with reference toFIGS.17to19can realize the same effects as in the foregoing embodiments.

(3) Others

The description has assumed an MRAM to be an example of the memory device100according to each embodiment. Note, however, that the memory device100according to each embodiment is not limited to an MRAM but may be any memory device that employs a switching element including a hydrogen storing layer sandwiched by two oxidation preventing layers.

For example, the memory device100according to each embodiment may be any one of various types of memory devices, including a memory device whose memory element is a transition metal oxide element having variable resistive characteristics (e.g., a resistance-change memory such as a resistive random access memory (ReRAM)), a memory device whose memory element is a phase-change element (e.g., a phase-change memory such as a phase change random access memory (PCRAM)), and a memory device whose memory element is a ferroelectric element (e.g., a ferroelectric memory such as a ferroelectric random access memory (FeRAM)).

The memory device100according to each embodiment, even in the form of a memory device other than an MRAM, can likewise realize the advantages as explained in the foregoing description.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.