Patent ID: 12238923

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the stated numerical value. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.

FIG.1is a flowchart of a method of forming a dielectric layer and a barrier layer on a silicon oxide film in accordance with some example embodiments.FIGS.2A and2Bare concept views schematically shown to explain the method ofFIG.1.

Referring toFIGS.1,2A and2B, the method may include providing a semiconductor substrate including a silicon oxide (e.g., SiO2) film200to an interior of a chamber (S10), and performing a plasma enhanced chemical vapor deposition (PECVD) process on the silicon oxide film200(S20). Though the semiconductor substrate is illustrated as including silicon oxide, in some example embodiments, the semiconductor substrate may include other oxides. For example, the oxide may be an insulating oxide of the semiconductor included in semiconductor substrate.

The PECVD process S20may include supplying TiCl4and H2, which are source gases, to an interior of the chamber (S21), and igniting a plasma, thereby forming a barrier layer204(S22). In some example embodiments, the supply of TiCl4and H2, which are source gases, to the interior of the chamber may include forming a dielectric layer202on the silicon oxide film200. For example, before forming the barrier layer204(which may be a Ti layer) the source gases (e.g., TiCl4and H2) may be supplied to the interior of the chamber (e.g., before plasma ignition). The PECVD process S20may be performed at about 400° C. or more. When the source gases, are supplied to the interior of the chamber, which is maintained at 400° C. or more, TiCl4and H2may react with the silicon oxide film200and, as such, a TiO2layer (e.g., the dielectric layer202) may be formed on the silicon oxide film200in accordance with Reaction Formula 1 as follows:
2Si—OH+TiCl4→2Si—Cl+TiO2+2HCl  [Reaction Formula 1]

In these cases, the thickness of the formed TiO2layer may be varied in accordance with a partial pressure of TiCl4supplied to the interior of the chamber. For example, the thickness of the TiO2layer may be thin when the partial pressure of TiCl4supplied to the interior of the chamber is low and constant. As variations in the partial pressure of TiCl4supplied to the interior of the chamber increases, and the partial pressure of TiCl4increases, the resulting TiO2layer may be formed to be thicker.

When a TiO2layer, which is a high dielectric material, is formed to a thickness not smaller than a determined (or alternatively a predetermined) thickness upon formation of a contact used in a semiconductor device, resistance-capacitance (RC) delay of the resultant semiconductor device may become excessively greater than a required (and/or otherwise determined) value. As a result, there may be a problem in reliability of the semiconductor device. To this end, the partial pressure of TiCl4supplied upon supply of the source gases may be adjusted to a determined (or alternatively a predetermined) level and, as such, the thickness of the TiO2layer may be adjusted to a desired thickness. In accordance with adjustment of the partial pressure of TiCl4, it may be possible to adjust the thickness of the TiO2layer within about 3 Å to 6 Å. For example, in order to form the TiO2layer to have a thickness of about 3 Å to 6 Å, the partial pressure of TiCl4may be adjusted such that the partial pressure ratio TiCl4/H2of TiCl4and H2is in a range of 1/750 to 1/250.

After the TiO2layer (e.g., the dielectric layer202) is formed on the silicon oxide film200, and as TiCl4and H2, which are source gases, are being supplied to the interior of the chamber, a plasma may be formed through plasma ignition of the residual TiCl4not taking part in the reaction forming the TiO2layer. As the plasma is formed using the source gases (e.g., TiCl4and H2) a Ti layer (e.g., the barrier layer204) may be deposited on TiO2.

FIG.3is a flowchart of a method for forming a dielectric layer and a barrier layer on a silicon oxide film in accordance with some example embodiments.FIGS.4A,4B,4C, and4Dare concept views schematically shown to explain the method ofFIG.3.

Referring toFIG.3, the method may further include subjecting a surface of the silicon oxide film200(e.g., as described with reference toFIGS.1,2A and2B) to plasma nitrification treatment before execution of the plasma enhanced chemical vapor deposition (PECVD) process on the silicon oxide film200(S15). The plasma nitrification treatment for the silicon oxide film200may be performed before execution of the PECVD process (S20) (e.g., before the formation of the barrier layer204). In some example embodiments, for example, the plasma nitrification treatment of the silicon oxide film200may be performed before the source gases (e.g., TiCl4and H2) are supplied to the interior of the chamber (and/or before a TiO2layer is formed).

The plasma nitrification treatment for the surface of the silicon oxide film200may be induction of SiO2—N coupling through mixture of the silicon oxide film200and nitrogen. For example, the plasma nitrification treatment may be performed in a direct plasma manner at a temperature of 400° C. to 500° C. and a pressure of 4 to 6 Torr in an atmosphere containing NH3, Ar, and H2as source gases in a reaction space of the chamber.

After the surface of the silicon oxide film200is subjected to the plasma nitrification treatment (S15), the PECVD process described with reference toFIG.1may be performed (S20). For example, first, TiCl4and H2may be supplied to the interior of the chamber (S21).

Although a TiO2layer, which is the dielectric layer202, may be formed through reaction of TiCl4with the silicon oxide film200, as described above, the reaction amount between the silicon oxide film200and TiCl4may be reduced because the surface of the silicon oxide film200has been subjected to the nitrification treatment. As shown inFIG.4B, the nitrogen coupled to the surface of the silicon oxide film200may function as a protective layer for the surface of the silicon oxide film200, thereby suppressing reaction between the silicon oxide film200and TiCl4. As a result, the thickness of the formed TiO2layer may be reduced.

In some example embodiments, after the plasma nitrification treatment of the surface of the silicon oxide film200, the partial pressures of TiCl4and H2may be controlled to be determined (or alternatively a predetermined) levels while being constant, as described with reference toFIG.1, and the resultant TiCl4and H2may be supplied to the interior of the chamber. In these cases, when TiCl4and H2are supplied under the condition that the partial pressure ratio TiCl4/H2of TiCl4and H2is in a range of 1/750 to 1/250, the thickness of the TiO2layer may be adjusted to be in a range of about 0 to 2.5 Å. For example, when the partial pressure ratio of TiCl4and H2is adjusted after the plasma nitrification treatment, it may be possible to reduce the thickness of the TiO2layer to 2.5 Å or less and/or to completely prevent formation of TiO2. As such, it may be possible to minimize RC delay by preventing formation of a TiO2layer and/or reducing the thickness of the TiO2layer upon forming a contact of a semiconductor device.

In some example embodiments, after the plasma nitrification treatment for the surface of the silicon oxide film200, TiCl4may be supplied without adjustment of the partial pressure thereof. When TiCl4is supplied without adjustment of the partial pressure thereof, the partial pressure of TiCl4in the chamber may be varied without being constant during a period from a time immediately after TiCl4is supplied to a time before plasma ignition occurs. Furthermore, the partial pressure ratio TiCl4/H2of TiCl4and H2may be between 1/250 to 1/750. For example, when the partial pressure of TiCl4is not adjusted, the partial pressure ratio TiCl4/H2of TiCl4and H2supplied to the interior of the chamber may be 1/250 to 1/150. In these cases, the thickness of the formed TiO2may be about 3 to 8 Å.

Thereafter, plasma ignition may be performed for residual TiCl4and H2, thereby depositing the barrier layer204(e.g., a Ti layer) on the dielectric layer202(e.g., a TiO2layer), and/or the silicon oxide film200(S22).

Referring toFIGS.4C and4D, in some example embodiments, a silicon oxynitride (“SiON”) layer201may be further formed on the silicon oxide film200by plasma nitrification treatment. After the plasma nitrification treatment, a dielectric layer202(e.g., a TiO2layer) may be formed on the SiON layer201by supplying TiCl4and H2. Subsequently, a barrier layer204(e.g., a Ti layer) may be deposited through plasma ignition. In some example embodiments, when the dielectric layer202is not formed, the barrier layer204may be deposited on the SiON layer201.

FIG.5is a flowchart explaining a method for forming a contact of a semiconductor device in accordance with some example embodiments.FIGS.6to11are sectional views explaining the method ofFIG.5.

Referring toFIGS.5to9, the method may include forming an interlayer insulating layer200on a semiconductor substrate100(S100), forming a contact hole H (S200), performing plasma nitrification treatment (S300), supplying a source gas (S400), forming barrier layers204and206(S500), and forming a metal layer208(S600).

Referring toFIGS.5and6, the interlayer insulating layer200may be formed by depositing an oxide (e.g., silicon oxide) on the semiconductor substrate100(S100). Although omitted fromFIGS.6to9, for convenience of description, the semiconductor substrate100may be provided with a structure such as a transistor having impurity regions as a source region and a drain region. A structure, such as a bit line, a bit line contact, a storage node contact, a landing pad, and/or a capacitor, which is electrically to the transistor, may be provided on the semiconductor substrate100. The interlayer insulating layer200may be formed on the above-described structures.

A contact hole H, which exposes a lower conductive layer ST, may be formed by etching the interlayer insulating layer200(S200). For example, the lower conductive layer ST may be a source/drain contact connected to a source/drain region of a transistor provided at the semiconductor substrate100, a wiring layer such as a bit line, and/or a plate electrode (and/or an upper electrode) included in a capacitor.

Plasma nitrification treatment may be performed on the interlayer insulating layer200formed with the contact hole H (S300). The plasma nitrification treatment may be performed in the same manner as the plasma nitrification treatment described with reference toFIGS.3and4A. For example, nitrogen in a plasma state may be introduced to a surface of the interlayer insulating layer200(which may be, e.g., a silicon oxide film), and, as such, a SiO2—N coupling may be induced. In some example embodiments, the plasma nitrification treatment may be performed in a direct plasma manner at a temperature of 400° C. to 500° C. and a pressure of 4 to 6 Torr in an atmosphere containing NH3, Ar, and H2in a reaction space of the chamber.

Referring toFIGS.5and7, a source gas for a PECVD process (S20) may be supplied in the chamber and/or onto the interlayer insulating layer200, the surface of which has been subjected to the plasma nitrification treatment. Supply of the source gas may be performed in the same manner as described with reference toFIG.1or3. For example, TiCl4and H2may be supplied onto the interlayer insulating layer200subjected to the plasma nitrification treatment, as source gases of the PECVD process. As TiCl4is supplied to the interior of the chamber before formation of a plasma, and the internal temperature of the chamber is maintained at 400° C. or more, TiCl4may react with the interlayer insulating layer200, and, as such, a dielectric layer202(e.g., a TiO2layer) may be formed.

In some example embodiments, when TiCl4and H2are supplied to the interior of the chamber under the condition that the partial pressure ratio TiCl4/H2of TiCl4and H2is adjusted to be 1/750 to 1/250, after the plasma nitrification treatment for the surface of the interlayer insulating layer200, the TiO2layer, which is the dielectric layer202, may be formed to have a thickness of 0 to 2.5 Å. For example, the dielectric layer202may not be formed or may be formed to have a thickness exceeding 0 Å, but not more than 2.5 Å.

In some example embodiments, formation of the dielectric layer202may not include adjusting the partial pressure of TiCl4. When TiCl4is supplied without adjustment of the partial pressure thereof, the partial pressure of TiCl4in the chamber may be varied during a period from a time immediately after TiCl4is supplied to a time before plasma ignition occurs. Furthermore, the partial pressure ratio TiCl4/H2of TiCl4and H2may be between 1/750 to 1/250. For example, when the partial pressure of TiCl4is not adjusted, the partial pressure ratio TiCl4/H2of TiCl4and H2supplied to the interior of the chamber may be 1/250 to 1/150. In these cases, the thickness of the formed TiO2may be about 3 Å to 8 Å. As such, it may be possible to minimize RC delay occurring due to a TiO2layer, which is included in a contact in a semiconductor device using the contact, by preventing formation of the TiO2layer and/or reducing the thickness of the TiO2layer.

Referring toFIGS.5and8, barrier layers204and206may be formed on the dielectric layer202. Formation of the barrier layers204and206may include forming a first barrier layer204, and forming a second barrier layer206. Formation of the first barrier layer204may be performed in the same manner as formation of the barrier layer204described with reference toFIGS.1and3. A plasma may be formed through plasma ignition of residual TiCl4not taking part in reaction for formation of the TiO2layer. As the plasma is formed using TiCl4and H2as source gases, a Ti layer, which may be at least one of barrier layer202and/or204, may be deposited on TiO2. In some example embodiments, the dielectric layer202may be omitted, and the first barrier layer204may be directly formed on the interlayer insulating layer200.

The second barrier layer206may be formed on the first barrier layer204, and the second barrier layer206, which may be a TiN layer, may be formed through thermal chemical vapor deposition (CVD).

Referring toFIGS.5and9, a metal layer208may be formed on the barrier layers204and206. The metal layer208, may be a W layer, may be formed, e.g., through atomic layer deposition (ALD) and/or chemical vapor deposition (CVD). Thereafter, node separation among contacts may be performed through a chemical mechanical polishing (CMP) process.

Referring toFIGS.5,10, and11, in some example embodiments, an SiON layer201may be further formed on the interlayer insulating layer200through plasma nitrification treatment. Subsequently, a dielectric layer202, which is a TiO2layer, a first barrier layer204, which is a Ti layer, a second barrier layer206, which is a TiN layer, and a metal layer208, which is a W layer, may be sequentially stacked on the SiON layer201by performing the processes described with reference toFIGS.7to9after the plasma nitrification treatment. In an embodiment, the dielectric layer202, which is a TiO2layer, may not be formed. In this case, the first barrier layer204, which is a Ti layer, may be directly formed on the SiON layer201.

FIG.12is a flowchart explaining a method for forming a contact of a semiconductor device in accordance with an exemplary embodiment of the disclosure.

Referring toFIG.12, the method may omit the plasma nitrification treatment performed in the contact formation method described with reference toFIG.5. That is, the method may adjust the thickness of a TiO2layer, which is a dielectric layer202, by supplying TiCl4onto an interlayer insulating layer200, which is silicon oxide, under the condition that the partial pressure of TiCl4is adjusted. For example, the TiO2layer may be formed to have a thickness of about 3 to 6 Å by adjusting the partial pressure of TiCl4such that the partial pressure ratio TiCl4/H2of TiCl4and H2in a chamber is in a range of 1/750 to 1/250.

FIG.13is a schematic plan view of a semiconductor device including a contact according to an exemplary embodiment of the disclosure.FIG.14is a cross-sectional view taken along line I-I′ inFIG.13. For convenience of description, the plan view ofFIG.13is shown in a state in which a contact is omitted.FIGS.15and16are enlarged views of a portion P1ofFIG.14.

Referring toFIGS.13and14, the semiconductor device may include a semiconductor substrate100, a word line WL, a buffer layer110, a bit line structure BLS, a direct contact DC, an insulating spacer130, a buried contact BC, a landing pad LP, an insulating structure140, a gate structure GS, a contact plug170, a first interlayer insulating layer165, a lower electrode191, a supporter layer192, a capacitor dielectric layer193, an upper electrode194, a second interlayer insulating layer200, -contacts201c1/201c2, and a wiring layer220.

The semiconductor substrate100may include a cell area CELL and a peripheral circuit area PERI. The cell area CELL may be an area in which a memory cell of a DRAM device is disposed, and the peripheral circuit area PERI may be a core/peri area. The semiconductor substrate100may include a semiconductor material. For example, the semiconductor substrate100may be and/or include a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator (SDI) substrate, and/or the like.

The semiconductor substrate100may include a first active region AR1, a second active region AR2, and an element isolation layer105. The element isolation layer105may be an insulating layer buried in the semiconductor substrate100, and may define first active regions AR1in the cell area CELL. The first active region AR1may have the form of an island surrounded by the element isolation layer105. The first active regions AR1may have the form of bars having a shorter axis and a longer axis while being spaced apart from one another. The element isolation layer105may define the second active region AR2in the peripheral circuit area PERI. The element isolation layer105may distinguish the cell area CELL and the peripheral circuit area PERI from each other.

Word lines WL may be disposed in parallel while being spaced apart from one another in a first direction D1, and each of the word lines WL may extend in a second direction D2perpendicularly intersecting the first direction D1. The first direction D1and the second direction D2may perpendicularly intersect each other on a plane parallel to a top surface of the semiconductor substrate100. The word lines WL may intersect the first active regions AR1. For example, two word lines WL may intersect one first active region AR1. The word lines WL may be buried in the semiconductor substrate100.

The buffer layer110may be disposed between the semiconductor substrate100and the bit line structure BLS. The buffer layer110may cover a portion of the top surface of the semiconductor substrate100and a portion of a top surface of the element isolation layer105. For example, the buffer layer110may include silicon nitride.

Bit line structures BLS may extend in the first direction D1while being disposed in parallel and spaced apart from one another in the second direction D2. The bit line structure BLS may include a conductive layer121, a first capping layer122, an insulating liner123and a second capping layer124which are sequentially stacked on the buffer layer110. Although the conductive layer121is shown as being a single layer, for convenience of description, the conductive layer121may include multiple layers. The first capping layer122may be disposed on the conductive layer121, and the conductive layer121and the first capping layer122may have the same width in the second direction D2. The insulating liner123may cover the first capping layer122in the cell area CELL, and may extend to the peripheral circuit area PERI. The second capping layer124may cover at least a portion of the insulating liner123. The second capping layer124may extend to the peripheral circuit area PERI. The conductive layer121may include, e.g., at least one of polysilicon, TiN, TiSiN, W, tungsten silicide, and/or the like. Each of the first capping layer122, the insulating liner123, and the second capping layer124may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, and/or the like.

The direct contact DC may be disposed at a lower portion of the bit line structure BLS in a region where the bit line structure BLS contacts the first active region AR1. For example, the direct contact DC may fill a portion of a recess formed at the top surface of the substrate100. When viewed in a top (and/or plan) view, the direct contact DC may overlap with a central portion of the first active region AR1. The direct contact DC may electrically interconnect the first active region AR1and the bit line structure BLS. For example, the direct contact DC may include a conductive material, e.g., polysilicon.

Insulating spacers130may be disposed at opposite side surfaces of the bit line structures BLS, respectively, and may extend along corresponding ones of the bit line structure BLS in the first direction D1, respectively. A portion of the insulating spacer130may extend into the recess of the semiconductor substrate100, and may cover a side surface of the direct contact DC. The insulating spacers130may include a single layer and/or multiple layers and may comprise an insulating material.

The buried contact BC may be disposed among the bit line structures BLS. The buried contact BC may be disposed among the insulating spacers130. A lower portion of the buried contact BC may extend into the semiconductor substrate100and, as such, may contact the first active region AR1. For example, the buried contact BC may include a conductive material, e.g., polysilicon.

The landing pad LP may be connected to an upper end of the buried contact BC, and a portion of the land pad LP may be disposed on the bit line structure BLS. The landing pad LP may be electrically connected to the first active region AR1via the buried contact BC. Insulating structures140may be disposed among landing pads LP. The insulating structures140may electrically insulate the landing pads LP from one another. Top surfaces of the insulating structures140may be coplanar with a top surface of the landing pad LP. For example, the landing pad LP may include a conductive material, e.g., tungsten, and the insulating structure140may include an insulating material, e.g., silicon oxide.

The gate structure GS may be disposed on the second active region AR2in the peripheral circuit area PERI. A source/drain region S/D may be disposed at a top surface of the second active region AR2adjacent to the gate structure GS. The gate structure GS may include a gate dielectric layer151, a gate electrode152, and a gate capping layer153which are sequentially stacked on the second active region AR2. Although the gate electrode152is shown as being a single layer, the gate electrode152may include multiple layers, and may include the same material as the conductive layer121of the bit line structure BLS.

Gate spacers160may be disposed on side walls of the gate structure GS. When viewed in a plan view, the gate spacer160may surround the gate structure GS. The gate spacer160and the gate structure GS may be covered by the insulating liner123extending from the cell area CELL. The gate spacer160may include an insulating material, e.g., silicon oxide, silicon nitride, silicon oxynitride, and/or a combination thereof.

The first interlayer insulating layer165may be disposed on the insulating liner123in the cell area CELL and the peripheral circuit area PERI. The first interlayer insulating layer165may be disposed under the second capping layer124. The interlayer insulating layer165may be disposed on a side surface of the gate spacer160. The first interlayer insulating layer165may include an insulating material, e.g., silicon oxide, silicon nitride, silicon oxynitride, and/or a combination thereof.

In the peripheral circuit area PERI, the contact plug170may be disposed adjacent to the gate structure GS. The contact plug170may extend through the first interlayer insulating layer165and the second capping layer124and, as such, may contact the second active region AR2. A top surface of the contact plug170may be disposed at the same level as the top surface of the landing pad LP. The contact plug170may include the same material as the landing pad LP. Upper portions of contact plugs170may have the form of lines extending in a horizontal direction or islands spaced apart from one another. The insulating structures140may electrically insulate the contact plugs170.

An etch stop layer180may be disposed on the landing pad LP, the insulating structure140, and the contact pug170. For example, the etch stop layer180may include an insulating material, e.g., silicon nitride. The etch stop layer180may have etch selectivity, for example, compared to the insulating structure140.

A capacitor structure may be disposed on the landing pad LP in the cell area CELL. The capacitor structure may include a lower electrode191, a supporter layer192, a capacitor dielectric layer193, and an upper electrode194. Lower electrodes191may extend through the etch stop layer180and, as such, may be connected to corresponding ones of the landing pads LP, respectively. The lower electrode191may have a cylindrical shape, a cup shape, a pillar shape, and/or a hybrid shape (e.g., including both the cylindrical shape and the pillar shape). The lower electrode191may include, e.g., a conductive materials such as a metal (e.g., Ti, W, Ni and/or Co) and/or a metal nitride (e.g., TiN, TiSiN, TiAlN, TaN, TaSiN, WN, etc.). The supporter layer192may be connected to portions of side surfaces of the lower electrodes191and, as such, may prevent (and/or mitigate the potential for) a collapse of the lower electrodes191. The supporter layer192may include an insulating material, e.g., silicon nitride.

The capacitor dielectric layer193may be conformally formed along surfaces of the lower electrode191and the supporter layer192. The capacitor dielectric layer193may include and insulating material such as a metal oxide (e.g., at least one of HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and/or TiO2), a dielectric material having a perovskite structure (e.g., SrTiO3(STO), BaTiO3, lead-zirconium-titanate (“PZT”) and/or lead-lanthanum-zirconium-titanate (“PLZT”)), and/or a combination thereof.

The upper electrode194may be disposed on the capacitor dielectric layer193and, as such, may cover the lower electrode191. The upper electrode194may include a conductive material, and SiGe covering the conductive material. The conductive material may include, for example, a metal (such as Ti, W, Ni and Co) and/or a metal nitride) such as TiN, TiSiN, TiAlN, TaN, TaSiN, WN, etc.).

The second interlayer insulating layer200may be disposed on the etch stop layer180in the cell area CELL and the peripheral circuit area PERI. The second interlayer insulating layer200may cover the upper electrode194. The second interlayer insulating layer200may include an insulating material, e.g., silicon oxide.

The contacts201c1/201c2may be electrically connected to a transistor in the cell area CELL and/or the peripheral circuit area PERI. The contacts201c1/201c2may include a first contact201c1and a second contact201c2. The first contact201c1may extend through the second interlayer insulating layer200in the cell area CELL and, as such, may be connected to the upper electrode194. The second contact201c2may extend through the second interlayer insulating layer200and the etch stop layer180in the peripheral circuit area PERI and, as such, may be connected to the contact plug170. The first contact201c1and the second contact201c2may be made of the same material, and may have the same configuration.

Wiring layers220may be disposed on the second interlayer insulating layer200and respective contacts201c1and201c2. Although not shown, a third contact may be electrically connected to the bit line structure BLS. The third contact may be formed using the same material as the first and second contacts201c1and201c2, and may have the same configuration as the first and second contacts201c1and201c2. The contact201c1/201c2may be formed through any one of the contact formation methods described with reference toFIGS.5to12.

Referring toFIGS.14and15, the second contact201c2may include a dielectric layer202being a TiO2layer, a first barrier layer204(e.g., a Ti layer), a second barrier layer206(e.g., a TiN layer), and a metal layer208(e.g., a W layer) which are sequentially stacked on a second interlayer insulating layer200. Here, when plasma nitrification treatment and adjustment of the partial pressure of TiCl4are performed upon forming the contact201c1/201c2, the thickness of the dielectric layer202may be 2.5 Å or less, and/or the dielectric layer202may not be formed at all. When only the plasma nitrification treatment is performed without adjustment of the partial pressure of TiCl4, the dielectric layer202may be formed to have a thickness of 3 to 8 Å. When adjustment of the partial pressure of TiCl4is performed without plasma nitrification treatment, the dielectric layer202may be formed to have a thickness of 3 to 6 Å.

Referring toFIG.16, in some example embodiments, the second contact201c2may further include an SiON layer201. The SiON layer201may be interposed between the second interlayer insulating layer200and the dielectric layer202.

In accordance with the example embodiments of the disclosure, the thickness of a dielectric layer formed by plasma enhanced chemical vapor deposition (PECVD) for formation of a barrier layer, upon forming a contact of a DRAM device, may be adjusted and, as such, it may be possible to adjust RC delay of the DRAM device.

While the example embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the disclosure and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.