Patent ID: 12216160

DETAILED DESCRIPTION

In DSM processes, defects like high impedance metal, high impedance shorts, and cross talk may not be detectable by traditional stuck-at fault tests, and may only show-up as timing failures via at-speed tests during testing. At-speed tests include transition fault testing and path delay fault testing. During a transition fault test, a mode of operation (e.g., an initialization cycle, a launch cycle, and/or a capture cycle, etc.) may be based on a state (e.g., a state ‘0’ or a state ‘1’) of a scan enable signal. The at-speed scan enable signal controls the mode of operation (e.g., the initialization/shift cycle/phase, the launch phase, and/or the capture phase, etc.). Both of the above at-speed tests input test patterns by scanning them into shift register(s) of a digital logic circuit at a slow speed during the shift phase at a clock frequency that is slower than the functional clock frequency applied during the launch and capture phase. After the test pattern is scanned in during the shift phase, clock pulses are applied at full speed during the launch and capture phases. One clock pulse launches a transition timing operation and a second clock pulse clocks a capture of the output transition for a respective path. The captured result can be scanned out during another shift phase, usually at slow speed and compared with an expected response or programmed value.

Generally, clock shaper circuits (such as clock leaker circuits) are logic circuits that provide a clock pulse or a set of clock pulses (e.g., in a test operation). These clock pulses are useful for transition fault testing or stuck-at fault testing of an integrated circuit-under-test (e.g., a cluster of flip-flops in a SoC) during the test operation. In some examples, clock shaper circuits are useful to provide a single clock pulse during stuck-at fault testing or a set of clock pulses during transition fault testing. In an example, for at-speed transition fault testing, the logic circuits provide the clock pulses to the integrated circuit-under-test (CUT) having a functional clock frequency of the integrated CUT. In an example, the logic circuits may be implemented together with the integrated CUT in a SoC. Further, in a shift phase, the clock shaper circuit receives a logic high scan enable signal that is also provided to the integrated CUT. In the launch and capture phase, the scan enable signal transitions to a logic low to cause the clock shaper circuit to provide a set of clock pulses to the integrated CUT in order to perform transition fault testing on the integrated CUT.

In an at-speed transition fault test of the integrated CUT, automatic test equipment (ATE) (e.g., a tester) loads a test pattern that includes programmed data vectors/scan vectors (e.g., data stream of ‘1’ and ‘0’ bits) into the integrated CUT in the shift phase. The ATE may load each data bit into the integrated CUT at a slow speed responsive to providing a shift clock frequency to the integrated CUT. As used herein, a ‘slow speed’ indicates clock signals that operate at a lower frequency than a functional clock frequency of clock signals (e.g., from a phase-locked loop (PLL) clock) provided to the integrated CUT and that corresponds to the operating frequency of the integrated CUT. In the shift phase, the ATE also applies a logic high (e.g., logic 1) scan enable signal to a clock shaper circuit and to the integrated CUT. Once the test pattern is loaded into the integrated CUT, the scan enable signal transitions to a logic low signal and begins the launch and capture phase. In an example, the clock shaper circuit provides the set of clock pulses to the integrated CUT for transition fault testing by the ATE in the launch and capture phase.

In at-speed transition fault testing of the integrated CUT, the logic circuits of the clock shaper circuit operate at the functional clock frequency of the integrated CUT while providing the clock pulses to the integrated CUT such as, for example, clock pulses at the clock frequency of a PLL clock. Further, responsive to the ATE providing the scan enable signal to the integrated CUT, the clock shaper circuit provides, during the launch and capture phase, the clock pulses to the integrated CUT. Therefore, to provide the clock pulses at-speed (e.g., at the functional clock frequency of the integrated CUT) after the scan enable signal is applied to the integrated CU, minimum wait cycles are inserted into the clock shaper circuit that cause the scan enable signal to be applied to the integrated CUT before the clock pulses are applied to the integrated CUT. If the scan enable signal is provided to the integrated CUT before or about the same time the clock pulses are provided to the integrated CUT, the ATE may not be able to perform transition fault testing of the integrated CUT.

Generally, minimum wait cycles in a timing path provide a delay between the time the scan enable signal reaches the integrated CUT and the time the clock pulses are applied to the integrated CUT. A minimum wait cycle for at-speed transition delay fault testing may be implemented by logic circuits that operate at the clock frequency of the integrated CUT. In an example, minimum wait cycles are implemented by pulse generators (e.g., a finite state machine (FSM) or clock cycles from a PLL) in a clock shaper circuit. These FSM or PLL circuits insert timing delays in a timing path of the clock shaper circuit for providing the clock pulses (e.g., clock pulse timing path) after the scan enable signal reaches the integrated CUT. The timing delays delay a time at which the clock shaper circuit initiates generation of the clock pulses based on a trigger signal to later than the time the scan enable is applied to the integrated CUT. In an example, the trigger signal may be a scan enable signal from the ATE. As used herein, the clock pulse timing path is the path between an input and an output with the maximum delay to cause the clock shaper circuit to provide the clock pulses to the integrated CUT and that does not require more time to provide the clock pulses than the available clock cycle. However, clock shaper circuits with FSM or PLL circuits add additional logic depth in the clock pulse timing path. As used herein, logic depth is the sum of the logic gates in the clock pulse timing path which receive the scan enable signal from the ATE as a trigger signal that causes the clock shaper circuit to provide the clock pulses to the integrated CUT. In integrated CUTs with 45 nanometer (nm) CMOS technology (e.g., DSM CMOS technology), the operating frequency is generally in the range of about 1.5 gigahertz (GHz) to about 2.0 GHz. clock shaper circuits with FSMs or PLLs are generally able to provide the clock pulses for at-speed testing of an integrated CUT that operates up to about 1.2 GHz. However, to perform at-speed testing of integrated CUT in the frequency range of about 1.5 GHz to about 2.0 GHz, logic gates may be useful that operate at these higher frequencies. In an example, in the clock pulse timing path, each logic gate may have a programmed delay to the propagating signal of about 100 picoseconds (ps). However, the clock shaper circuits may have to provide the clock pulses in the launch and capture phase with a programmed delay that does not exceed about 500 ps (e.g., for an integrated CUT operating at about 2 GHz). At least some clock shaper circuits based on FSMs or PLLs for at-speed testing at these higher frequencies add additional wait cycles in the clock pulse timing path, causing the logic depth in the clock pulse timing path to exceed 5 (and thereby causing the programmed delay to exceed 500 ps). Further, the logic depth of clock of shaper circuits with FSMs or PLLs at the higher frequencies of about 1.5 GHz to about 2 GHz may not be able to synchronize the scan enable signal with the clock pulses, which can impede at-speed transition fault testing of an integrated CUT in the frequency range of about 1.5 GHz to about 2.0 GHz.

Disclosed herein are examples of a clock shaper circuit that provides clock pulses for at-speed transition fault testing of an integrated CUT. In an example, a clock shaper circuit may provide two clock pulses or multiple clock pulses for transition delay fault testing or a single clock pulse for other fault testing of an integrated CUT. The clock shaper circuit includes logic circuits that operate at a functional clock frequency in the range of about 1.5 GHz to about 2 GHz, such as the functional clock frequency of an integrated CUT. In an example, the clock shaper circuit receives a logic high scan enable signal from an ATE in the shift phase that is useful to load (scan in) test vectors into an integrated CUT, to load clock configuration vectors into the clock shaper circuit, and to provide a synchronized scan enable signal to the integrated CUT. Once the test vectors are loaded, the scan enable signal transitions to a logic low that begins a launch and capture phase of transition fault testing. In an example, the scan enable signal may transition its output to a logic low signal that is useful in the launch and capture phase to trigger the clock shaper circuit to provide a set of clock pulses to the integrated CUT at the functional clock frequency of the integrated CUT. In an example, the synchronizing circuit includes logic circuits that have a logic depth in a clock pulse timing path that may not exceed 2. In an example, the clock shaper circuit provides a number of wait cycles during the launch and capture phase such that the synchronized scan enable signal is provided to the integrated CUT in the shift phase before the set of clock pulses are provided to the integrated CUT in the launch and capture phase.

FIG.1is a block diagram of a clock shaper circuit100(e.g., a logic circuit) for providing clock pulses, in accordance with various examples. In an example, the clock shaper circuit100may provide two clock pulses in a test operation that are applied to an integrated CUT. The clock pulses may correspond to a functional clock frequency of the integrated CUT. While the clock shaper circuit100described herein is useful for generating two clock pulses that are applied to an integrated CUT, in various examples any number of clock pulses may be provided by the clock shaper circuit100for performing testing of the integrated CUT. In various examples, the clock shaper circuit100is implemented as a standalone device (e.g., implemented on its own substrate, enclosed within its own chip package, etc.) or is implemented with the integrated CUT and other electrical devices in a SoC. In an example, the clock shaper circuit100provides a two-clock pulse for at-speed transition fault testing of an integrated CUT that operates in a frequency range of about 1.5 GHz to about 2 GHz from signals that are applied to the clock shaper circuit100from an external tester103(e.g., ATE).

As shown inFIG.1, the clock shaper circuit100includes a synchronizing circuit104, an integrated clock gating (ICG) circuit106, a clock leaker circuit108, an AND gate110, a shaping ICG circuit112, a multiplexer (MUX)114, an AND gate116, a MUX118, and inverters120,122,124, and150. In some examples, the synchronizing circuit104, an ICG circuit106, clock leaker circuit108, AND gate110, shaping ICG circuit112, MUX114, AND gate116, MUX118, and inverters120-124and150are electrically coupled together by way of wires, metal traces on a printed circuit board, metal routing on a silicon substrate, or any other suitable form of conductive coupling. In an example, the clock shaper circuit100may receive signals from the external tester103(e.g., ATE), which may be coupled to the clock shaper circuit100for providing the two clock pulses that are applied to an integrated CUT, such as integrated CUT102. In some examples, the signals from the external tester103may include a shift clock signal (SHIFT_CLK) having a shift frequency, clock signal (PLL_CLK) having a functional clock frequency that is greater than the shift frequency and that corresponds to an operating frequency of the integrated CUT, clock pulse configuration vectors (CONF_VECTORS), a scan enable signal (SCAN_EN), and transition fault test enable signal (TFT_EN) that may be received by the clock shaper circuit100via independent couplings from the external tester103to the clock shaper circuit100.

As shown inFIG.1, the synchronizing circuit104may be coupled to the inverters120,122, and124, and the MUX118. In an example, the synchronizing circuit104includes shift registers126,128,130, and132(which may be referred to herein as shift registers1-M) that are arranged as a cascade of flip-flops. In an example, while the synchronizing circuit104is shown with shift registers1-M, additional shift registers may be implemented. In an example, the shift registers126,128,130, and132may be D flip-flops. However, other types of flip-flops may be suitable, such as S-R or J-K type flip-flops. In an example, each output node (e.g., the Q node) of a respective shift register of the shift registers126-132is coupled to an input node (e.g., the D node) of an immediately adjacent downstream shift register of the shift registers128-132. In an example, the output node of shift register126is coupled to the input node of shift register128, the output node of shift register128is coupled to the input node of shift register130, and the output node of shift register130is coupled to the input node of shift register132. While synchronizing circuit104is shown with shift registers126-132, in some examples, additional shift registers similar to the shift registers126-132may be included. As explained further below, the shift registers126-132are coupled so that an output of the last shift register in the synchronizing circuit104(e.g., shift register132) provides a signal SCAN_EN_SYNC[M] that is based on the SCAN_EN provided by the tester103and delayed by a number of cycles of the PLL_CLK equal to the number of shift registers126-132. This signal SCAN_EN_SYNC[M] is useful to control a clock (LKR_SHIFT_CLK) applied to the clock leaker circuit108.

The output of the first shift register126in the chain of shift registers126-132is also coupled to an input of the MUX118to provide a signal SCAN_EN_SYNC[0] that is based on SCAN_EN being provided by the tester103and delayed by a cycle of the PLL_CLK. In an example, the MUX118may be implemented as a 2-to-1 multiplexer with a high-side input node (e.g., input ‘1’), a low-side input node (e.g., input ‘0’), a select input node, and an output node. In an example, the logic value at low-side input node will be reflected at the output node in response to the select input node being held to a logic low (e.g., logic 0). In an example, the logic value at high-side input node will be reflected at the output node in response to the select input node being held at a logic high (e.g., logic 1). In an example, the output node of shift register126is coupled to the inverters122and124, and to the high-side input node of the MUX118. The output node of the shift register132is coupled to the input node of the inverter120. In an example, each of the shift registers126-132receives PLL_CLK from a PLL or another clock circuit (not shown) coupled to the external tester103. In an example, PLL_CLK has a same frequency as the functional clock frequency of the integrated CUT. In an example, the PLL_CLK is configured to drive the shift registers126-132in the synchronizing circuit104. In an example, SCAN_EN is applied to the shift register126via a scan enable signal line, to the low-side input node of the MUX118, and to the AND gate116via the inverter150.

In an example, each shift register126-132inserts a programmed delay into the clock pulse timing path such that an output signal that is provided from a respective shift register126-132meets the timing requirements for generating the two clock pulses in the launch and capture phase. In an example, based on the timing requirements, SCAN_EN is applied to the clock shaper circuit100in the shift phase to initiate providing of the two clock pulses during the launch and capture phase. Further, in an example, a synchronized scan enable signal HS_SCAN_EN is provided by the clock shaper circuit100to the integrated CUT102before the two clock pulses are provided to the integrated CUT102. In an example, the clock pulse timing path from the synchronizing circuit104to the clock leaker circuit108includes the programmed delays in logic gates including the shift register126and the inverter124, or the programmed delays in other logic gates including the shift register132and the inverter120.

In an example, the shift register126adds a programmed delay to an output signal from the shift register126in response to SCAN_EN that is applied at an input node of the shift register126. In an example, the logic high SCAN_EN initiates loading/shifting the CONF_VECTORS into the clock shaper circuit100during the shift phase. In another example, the shift registers128-132add additional programmed delays to the output signals that are provided from a respective shift register to an adjacent and downstream shift register128-132. In an example, each of the shift registers126-132provides a programmed delay in lieu of other solutions that include FSMs or PLLs to provide the timing requirements during the launch and capture phases, increasing the logic depth of the clock pulse timing path.

In an example, the clock leaker circuit108includes shift registers134,136,138, and140(which may be referred to herein as shift registers1-N) that are arranged as a cascade of parallel-input, serial-output shift registers. In an example, while the clock leaker circuit108is shown with shift registers1-N, additional shift registers may be included. In an example, shift registers134,136,138, and140may be implemented as D flip-flops. However, other types of flip-flops such as S-R flip-flops, J-K flip-flops, or a combination of D, S-R, and J-K flip-flops may be included. In an example, each input node (e.g., the D node) of the shift registers134-140is coupled to an output node of a respective MUX of the MUXs142-148and each output node (e.g., the Q node) of the shift registers134-140is coupled to an input node of an adjacent MUX of a downstream shift register. In some examples, the input node of the shift register134is coupled to the output node of the MUX142, and the output node of the shift register134is coupled to the low-side input node of the MUX144, the input node of the shift register136is coupled to output node of the MUX144, and output node of the shift register136is coupled to low-side input node of the MUX146, and the input node of the shift register138is coupled to output node of the MUX146, and the output node of the shift register138is coupled to low-side input node of the MUX148. In an example, an input node of shift register140is coupled to the output node of the MUX148, and the output node of shift register140is coupled to the AND gate110. In an example, the MUXs142-148may be implemented as 2-to-1 multiplexers substantially similar to the MUX118with a high-side input node (e.g., input ‘D1’), a low-side input node (e.g., input ‘D0’), a select input node (e.g., select ‘S0’), and an output node.

In an example, the high-side input nodes of the MUXs142-148are coupled to a data line to receive CONF_VECTORS as ‘1’ or ‘0’ data bits. In an example, CONF_VECTORS include a programmed sequence of data bits having ‘1’ and ‘0’ in which two consecutive ‘1’ bits (e.g., two consecutive logic high bits sequence with leading and trailing zeros may be ‘001100’) may provide the two clock pulses responsive to the CONF_VECTORS that are shifted out of the clock leaker circuit108into the shaping ICG circuit112. In an example, the leading zeros of CONF_VECTORS provide a programmed delay to the shifting out the consecutive ‘1’ bits by clock leaker circuit108during the launch and capture phase. The trailing zero may indicate an end to the operation for providing the clock pulses. In an example, other clock pulses may be provided (e.g., a one clock pulse, three clock pulses, or any number of clock pulses) based on a number of the programmed consecutive ‘1’ bits that are to be loaded into the shift registers134-140according to CONF_VECTORS. In an example in which three-clock pulses are provided by the clock shaper circuit100, data vectors that include three consecutive ‘1’ data bits after a set of leading zeros in the CONF_VECTORS may be loaded into the clock leaker circuit108. In an example, the CONF_VECTORS may provide the two clock pulses responsive to being loaded into the MUXs142-148and shifted out based on a clock signal that is applied to the MUXs142-148.

In an example, the MUXs142-148may provide CONF_VECTORS into each of the shift registers134-140based on output clock pulses (LKR_SHIFT_CLK), as received at the clock inputs of the MUXs142-148. In an example, each of the shift registers134-140is coupled to an output node of the ICG circuit106and receives LKR_SHIFT_CLK from the ICG circuit106. LKR_SHIFT_CLK drives the shift registers in the clock leaker circuit108to load the CONF_VECTORS into the clock leaker circuit108and provide the two pulses (e.g., LKR_CLK_OUT) from the clock shaper circuit100based on the programmed sequence of data bits.

In an example, the ICG circuit106receives PLL_CLK at an input node and receives an enable signal at an enable node from an output of the inverter120. In an example, the PLL_CLK is configured to drive the shift registers134-140in the clock leaker circuit108such that clock pulses from the PLL_CLK serially shift the CONF_VECTORS through the shift registers134-140in response to a clock gating signal that is deasserted at the clock leaker circuit108. In an example, the ICG circuit106is clock gated (e.g., clock gating signal is asserted) with a logic low enable signal (e.g., ICG circuit106is turned OFF with a logic low signal) such that LKR_SHIFT_CLK is not provided at the output node of the ICG circuit106(e.g., ICG circuit106is clock gated). Clock gating the ICG circuit106prevents the LKR_SHIFT_CLK from being applied to the clock nodes of the shift registers134-140and prevents serially shifting the data bits through the shift registers134-140. In an example, the ICG circuit106may be ungated with a logic high enable signal to initiate generation of the two clock pulses. In an example, applying a logic high enable signal to the enable node of ICG circuit106ungates the ICG circuit106(e.g., ICG circuit106is turned ON with a logic high signal) and causes LKR_SHIFT_CLK to propagate to the output node of the ICG circuit106.

In an example, a first input of the AND gate110is coupled to the output node of the shift register126via the inverter124, a second input of the AND gate110is coupled to the output node of the shift register140, and a third input of the AND gate110is coupled to a transition fault testing signal line to receive a transition fault test enable signal (TFT_EN). In an example, a first input of the AND gate116is coupled to the scan enable signal line via the inverter150and receives an inverted output of SCAN_EN. In an example, a second input of the AND gate116is coupled to the transition fault testing signal line to receive TFT_EN. In an example, TFT_EN is held high during the shift phase and during the launch and capture phase, and does not change its state during at-speed transition fault testing of the integrated CUT102. In an example, TFT_EN is held low for another test mode such as stuck-at fault testing. In an example, the shaping ICG circuit112is coupled at a first input node to the output of the AND gate110for receiving an enable signal (LKR_SHAPE_EN) and at a second input node to a clock circuit for receiving the PLL_CLK. The output of the shaping ICG circuit112is coupled to a high-side input node of the MUX114. The low-side input node of the MUX114is coupled to a signal line for receiving a SHIFT_CLK, and the output node of the MUX114is coupled to the integrated CUT102. In an example, the MUX114may be implemented as a 2-to-1 multiplexer that is substantially similar to the MUX118with a high-side input node (e.g., input ‘D1’), a low-side input node (e.g., input ‘D0’), a select input node (e.g., select ‘S0’), and an output node. In an example, SHIFT_CLK is a “slow” clock (e.g., having a clock frequency that is lower than a frequency of PLL_CLK). In an example, SHIFT_CLK is configured to shift the CONF_VECTORS into the clock leaker circuit108during the shift phase. In an example, the high-side input node of the MUX118is coupled to the output node of the shift register126of the synchronizing circuit104, the low-side input node of the MUX118is coupled to the scan enable signal line to receive SCAN_EN, and the output of the MUX118is coupled to the integrated CUT102.

In an example operation, the clock shaper circuit100may receive the SCAN_EN. During a shift phase where the SCAN_EN is high, the MUX114provides the SHIFT_CLK to the integrated CUT102as LKR_CLK_OUT for use in loading (scanning in) a test pattern into latches of the integrated CUT102. Once the test pattern is loaded into the integrated CUT102, the SCAN_EN signal transitions and begins a launch and capture phase of, for example, transition fault testing. In an example, the SCAN_EN may transition its output state from a high state (e.g., logic high) to a low state (e.g., logic low) to trigger the clock leaker circuit108to provide the set of functional frequency clock pulses as LKR_CLK_OUT. The clock shaper circuit100provides the clock pulses in a launch and capture phase after a synchronized scan enable signal (HS_SCAN_EN) is provided to the integrated CUT102in the shift phase. In an example, the clock pulses are useful for an external tester to perform transition fault testing of the integrated CUT. In an example, during a transition fault testing mode, a logic high TFT_EN is applied to the AND gate110during the shift phase and maintained at logic high during the transition fault testing. In an example, other inputs to the AND gate110are at a logic high in the launch and capture phase. The logic high inputs to the AND gate110causes the AND gate110to provide a logic high signal to the shaping ICG circuit112, which triggers the shaping ICG circuit112to provide LKR_CLK_OUT with the two clock pulses responsive to the PLL_CLK during the duration of the logic high enable signal LKR_SHAPE_EN at the shaping ICG circuit112. In an example, for stuck-at fault testing of an integrated CUT102based on two clock pulses not being useful for testing the integrated CUT102, the TFT_EN is held at logic low and the SCAN_EN is held at logic high, which is inverted by the inverter150to provide a logic low signal to an input of the AND gate116. The output node of the AND gate116is coupled to the MUX114. In an example, in response to the SCAN_EN being held at logic high, the AND gate116provides a logic low signal to the MUX114. In an example, the logic low signal to MUX114causes the PLL_CLK to be bypassed while the SHIFT_CLK is propagated to the integrated CUT102. The clock shaper circuit100disclosed herein is configured to provide a minimum number of wait cycles in a synchronizing circuit based on a scan enable signal that is received such that two clock pulses are provided to an integrated CUT before a synchronized scan enable signal is provided to the integrated CUT102. In an example, the clock shaper circuit100disclosed herein includes logic gates in a clock pulse timing path that does not exceed a logic depth of 2 and provides the two clock pulses that is useful for at-speed transition fault testing of the integrated CUT102in the frequency range of about 1.5 GHz to about 2 GHz.

FIG.2is a waveform diagram200that shows a test operation of the clock shaper circuit100ofFIG.1, in accordance with various examples. In an example, the test operation includes a shift phase202in which a set of test vectors are shifted into shift registers of an integrated CUT102according to a scan clock LKR_SHIFT_CLK and provided by a clock shaper circuit100to the integrated CUT102as a set of clock pulses LKR_CLK_OUT. In an example, the test operation may include loading clock configuration vectors CONF_VECTORS into a clock leaker circuit108of the clock shaper circuit100. The test operation further includes a launch and capture phase204in which a set of clock pulses206specified by CONF_VECTORS are provided by the clock shaper circuit100via LKR_CLK_OUT and based on a transition of SCAN_EN. In an example, an external ATE (e.g., tester103inFIG.1) may provide signals to the clock shaper circuit100for implementing the test operation of the clock shaper circuit100described herein.

With continued reference toFIG.1, in the shift phase202, SCAN_EN is held at a logic high and applied to the clock leaker circuit108to shift a set of test vectors into the integrated CUT102and to load CONF_VECTORS into the clock leaker circuit108. In an example, CONF_VECTORS are applied to the clock leaker circuit108and the PLL_CLK is applied to the ICG circuit106. Low frequency pulses from SHIFT_CLK are applied to low-side input node of the MUX114during the shift phase202. In an example, a logic high SCAN_EN is inverted by the inverter150, which causes the MUX114to provide the SHIFT_CLK based on a logic low signal at the select input node of the MUX114. In an example, CONF_VECTORS are shifted into the MUXs142-148of the clock leaker circuit108responsive to the SCAN_EN being applied to the synchronizing circuit108. In an example, the SCAN_EN is a logic high signal and the TFT_EN is a logic high signal. In an example, the logic high SCAN_EN is applied to an input node of the shift register126and to the low-side input node of the MUX118. Further, PLL_CLK is applied to the shift registers126-132and to the ICG circuit106. In an example, PLL_CLK is applied to the clock input of the shift registers126-132and to the input node of the ICG circuit106.

In an example, applying a logic high SCAN_EN to the shift register126produces an output signal (SCAN_EN_SYNC[0]), which is a logic high signal at the output node of the shift register126responsive to PLL_CLK being applied to the clock input of the shift register126. In the shift phase202, the SCAN_EN_SYNC[0] is applied to the input of the inverters122and124, and to the high-side input node of the MUX118, and TFT_EN is held high. In an example, TFT_EN is applied to the select input node of the MUX118. A logic high TFT_EN causes SCAN_EN_SYNC[0] at the high-side input node of the MUX118to be provided from the output node of the MUX118as synchronized scan enable signal HS_SCAN_EN. In an example, based on programmed delays that are configured into the synchronizing circuit104and the clock leaker circuit108, HS_SCAN_EN is provided to the integrated CUT102in the shift phase202before SCAN_EN that is applied to the clock shaper circuit100in the launch and capture phase204provides the two clock pulses LKR_CLK_OUT206that is provided from the MUX114.

In an example, in the shift phase202, the inverters122and124invert the logic high SCAN_EN_SYNC[0] to a logic low signal. The logic low signals are applied to the select input node of MUXs142-148and to the AND gate110. Applying the logic low signals from inverter122to the MUXs142-148cause CONF_VECTORS to be loaded into the shift registers134-140. The data bits in the shift registers134-140is not shifted into the shift registers134-140until LKR_SHIFT_CLK is applied to each clock input of the shift registers134-140. As a logic low signal is applied to the enable node of the ICG circuit106, the ICG circuit106is gated OFF and LKR_SHIFT_CLK is not applied as clock signals to the shift registers134-140which prevents CONF_VECTORS at the input nodes of the shift registers134-140from being serially shifted from the shift register134to the shift register140and then to the AND gate110.

In an example, SCAN_EN_SYNC[0] is an output signal at the output node of the first shift register126that propagates through shift registers128-132during each clock pulse of PLL_CLK. SCAN_EN being logic high causes each shift register126-132to output a logic high signal at their respective output nodes with shift register132providing a logic high signal SCAN_EN_SYNC[M] at the output node of shift register132(e.g., Mthshift register). In an example, SCAN_EN_SYNC[M] is a trigger signal that starts the two clock pulse generation by the clock leaker circuit108.

In an example, the logic high signal at the input node of shift register128propagates through the shift registers128-132based on receiving clock cycles from PLL_CLK. Each input logic high signal that is provided by the shift registers128-132is delayed by a programmed delay by a respective shift register of the shift registers128-132in the synchronizing circuit104. The shift register126inserts one programmed delay to the logic high SCAN_EN_SYNC[0] at the output node of the shift register126, which is applied to the MUX118. Further, the shift registers128-132may add three additional programmed delays to the logic high SCAN_EN_SYNC[M] that is provided at the output node of the shift register132. The logic high SCAN_EN_SYNC[M] is inverted by the inverter120, which causes the ICG circuit106to be gated OFF and prevents the ICG circuit106from providing LKR_SHIFT_CLK.

In an example, during the launch and capture phase204, SCAN_EN is transitioned from a high state (e.g., logic high) to a low state (e.g., logic low). In an example, a logic low signal is applied at the input node of the shift register126that causes SCAN_EN_SYNC[0] at the output node of shift register126to transition from a logic high to a logic low during the rising edge of PLL_CLK. After the first cycle (e.g., rising edge) of PLL_CLK, the shift register126outputs a logic low SCAN_EN_SYNC[0], which is applied to the input of inverter122. The inverters122and124invert the logic low SCAN_EN_SYNC[0] to a logic high signal. The logic high signal from the inverter122is applied to the select input nodes of the MUXs142-148as an enable signal to shift out the data bits from the shift registers134-138. The logic high signal from the inverter124is applied to the AND gate110. The logic low SCAN_EN_SYNC[0] at the output node of the shift register126propagates through the shift registers128-132based on each rising edge of the PLL_CLK. In an example, after the fourth cycle of PLL_CLK, the output node of the shift register132provides a logic low SCAN_EN_SYNC[M]. Each logic low signal that is provided by a respective shift register128-132is delayed by a programmed delay in the synchronizing circuit104. The logic low SCAN_EN_SYNC[0] is inverted to a logic high enable signal by the inverter120, and is applied to the enable node of the ICG circuit106as an ungating signal. In an example, the ungating signal at the ICG circuit106triggers the clock leaker circuit108to shift the CONF_VECTORS to the next shift register in the clock leaker circuit108to provide the two clock pulses for transition fault testing in response to a LKR_SHIFT_CLK that is provided to the shift registers134-140.

In an example, applying ungating signals (e.g., logic high signal) to the enable node of the ICG circuit106causes the ICG circuit106to provide LKR_SHIFT_CLK. LKR_SHIFT_CLK are clock pulses from PLL_CLK. In an example, the timing requirement for applying ungating signal to the enable node of the ICG circuit106may include programmed delays to the signals that propagate through the shift registers126-132. In an example, the inverter120and the ICG circuit106may add further propagation delays to the ungating signal applied to the ICG circuit106. In an example, LKR_SHIFT_CLK that is applied to the clock leaker circuit108to provide LKR_CLK_OUT206is delayed by a programmed delay based on each delay of the shift registers128-132.

In an example, LKR_SHIFT_CLK is applied to the clock nodes of shift registers134-140. Each rising edge of LKR_SHIFT_CLK causes CONF_VECTORS (e.g., data bits ‘1’ or ‘0’) at the input nodes of the shift registers134-140to be serially shifted from the shift register134to the adjacent shift registers downstream of the shift register and out of the shift register140. The CONF_VECTORS may be shifted out of the clock leaker circuit108into a first input node of the AND gate110. In an example, the other input nodes of the AND gate110receive a logic high signal from the output of inverter124and a logic high TFT_EN. In an example, based on consecutive logic high CONF_VECTORS that are provided by clock leaker circuit108and while other inputs to the AND gate110are logic high, a logic high enable signal LKR_SHAPE_EN is provided at the enable node of the shaping ICG circuit112, which ungates the shaping ICG circuit112and causes PLL_CLK to propagate to the high-side input node of the MUX114for the duration of the logic high LKR_SHAPE_EN. In an example, two consecutive logic high data bits in CONF_VECTORS cause the LKR_SHAPE_EN to be logic high for two clock cycles of PLL_CLK and provide two logic high signals to the high-side input node of the MUX114.

In an example, the inputs of the AND gate116receive an inverted output of SCAN_EN and receives TFT_EN. In the launch and capture phase, SCAN_EN is held low while TFT_EN is held high, which causes a logic high signal to be provided from the AND gate116to the select input node of the MUX114. In an example, PLL_CLK at the high-side input node of MUX114is reflected on the output node of MUX114for the duration of logic high LKR_SHAPE_EN at high side input node of the MUX114in response to the select input node of the MUX114being at logic high. In an example, in response to consecutive logic ‘1’ CONF_VECTORS being shifted out of the clock leaker circuit108, a logic high LKR_SHAPE_EN is provided at the enable node of the shaping ICG circuit112and causes the MUX114to provide two clock pulses of PLL_CLK from the high-side input node of the MUX114in response to the select input node of the MUX114being at logic high. In an example, the LKR_SHAPE_EN is logic high for two clock cycles of PLL_CLK, which causes the MUX114to provide LKR_CLK_OUT as the two clock pulses206. In an example, the launch and capture phase204is followed by another shift phase208whereby additional CONF_VECTORS are loaded into the clock shaper circuit100and additional two clock pulses are provided based on another launch and capture phase substantially similar to launch and capture phase204. The clock shaper circuit100disclosed herein is configured to provide a minimum number of wait cycles in the launch and capture phase204in response to the SCAN_EN that is received such that two clock pulses LKR_CLK_OUT are provided to an integrated CUT102before a synchronized scan enable signal HS_SCAN_EN is provided to the integrated CUT102. In an example, the clock shaper circuit100disclosed herein includes logic gates in a clock pulse timing path that does not exceed a logic depth of 2 and provides the two clock pulses that is useful for at-speed transition fault testing of the integrated CUT102in the frequency range of about 1.5 GHz to about 2 GHz.

FIG.3is a flow diagram of a method300implemented on an integrated circuit, in accordance with various examples. In an example, the method300implements a clock leaker operation for generating a set of clock pulses in an integrated circuit. In an example, the integrated circuit is clock shaper circuit100that was shown and described inFIG.1.

With continued reference toFIGS.1and2, in step302, data vectors are provided to the clock shaper circuit100. In an example, an external tester103(e.g., automatic test equipment) may provide the clock configuration vectors (e.g., CONF_VECTORS inFIG.1) to the MUXs142-148of a clock leaker circuit108in the clock shaper circuit100during a shift phase.

In step304, a logic high scan enable signal is applied to the clock shaper circuit100. In an example, the logic high scan enable signal SCAN_EN is applied to a shift register126of a synchronizing circuit104and clock pulses PLL_CLK are applied to the clock nodes of the shift registers126-132in a shift phase. The logic high SCAN_EN causes the shift register126to provide a logic high output signal at the output node of the shift register126on a clock pulse PLL_CLK. The logic high output signal provided at the output node of the shift register126is inverted by the inverter122to a logic low output signal and provided to select input nodes of the MUXs142-148. The logic low output signal loads CONF_VECTORS into the shift registers134-140of the clock leaker circuit108. In an example, the logic high output signal from the shift register126is provided to the high-side input node of the MUX118. In an example, a logic high TFT_EN in the shift phase causes a logic high output signal at the high-side input node of the MUX118to be provided from the output node of MUX118as HS_SCAN_EN. In an example, HS_SCAN_EN is applied to the integrated CUT102before LKR_CLK_OUT provides the set of clock pulses206in the launch and capture phase204.

In step306, a logic low scan enable signal is provided at the input to the clock shaper circuit100to shift the data bits in the clock leaker circuit108. In an example, the logic low scan enable signal SCAN_EN is applied to the shift register126of the synchronizing circuit104and PLL_CLK is applied to the clock nodes of the shift registers126-132. After the first cycle (e.g., rising edge) of PLL_CLK, the shift register126provides a logic low output signal, which is inverted by the inverter122to a logic high signal and provided to the select input node of the MUXs142-148. The logic high signal from the inverter122is provided to the select input nodes of the MUXs142-148as a gating signal for the MUXs142-148. A logic low output signal is provided by the shift register132based on the fourth cycle of PLL_CLK as a logic low SCAN_EN_SYNC[M] and is inverted to a logic high SCAN_EN_SYNC[M] by the inverter120. The logic high SCAN_EN_SYNC[M] is provided to the enable node of the ICG circuit106as an ungating signal. In an example, LKR_SHIFT_CLK is applied to the clock nodes of the shift registers134-140in response to the logic high SCAN_EN_SYNC[M] from the inverter120being provided to the enable node of the ICG circuit106. Each rising edge of LKR_SHIFT_CLK causes CONF_VECTORS (e.g., data bits ‘1’ or ‘0’) at the input nodes of the shift registers134-140to be serially shifted from the shift register134to the adjacent shift registers downstream of the shift register134and out of the shift register140.

In step308, LKR_SHAPE_EN is provided to an integrated clock generator (e.g., ICG circuit112) to cause the clock shaper circuit100to provide the two clock pulses. In an example, in response to the CONF_VECTORS being provided to the AND gate110as consecutive logic high inputs, a logic high enable signal LKR_SHAPE_EN is provided at the enable node of the shaping ICG circuit112, which ungates the shaping ICG circuit112for two clock cycles of PLL_CLK. In an example, two consecutive logic high data bits in CONF_VECTORS causes the LKR_SHAPE_EN to be logic high for two clock cycles of PLL_CLK and provide two logic high signals to the high-side input node of the MUX114. In an example, the inputs of the AND gate116receive logic high signals. In an example, an input to the AND gate116is a logic high signal based on inverting the logic low SCAN_EN by the inverter150and another input to the AND gate116is a logic high TFT_EN, which causes a logic high signal to be provided from the AND gate116to the select input node of the MUX114. In an example, in response to the select input node of the MUX114being kept at logic high, the PLL_CLK at the high-side input node is provided on the output node of the MUX114for the duration of the logic high LKR_SHAPE_EN. In an example, the LKR_SHAPE_EN is a logic high for two clock cycles of PLL_CLK, which causes the MUX114to provide LKR_CLK_OUT as the set of clock pulses206.

FIG.4is a block diagram of an electronic system400in accordance with various examples. For example, the electronic system400is, or is incorporated into, or is coupled to, a system such as an automobile, or any type of electronic system operable to process information. In some examples, the electronic system400includes a computing device402that includes a clock shaper circuit404, a central processing unit (CPU)406, a power supply408, an input-output (I/O) port410, a display412, a user interface (UI)414, a storage416(e.g., a random-access memory (RAM)), and a networked devices418.

In some examples, the clock shaper circuit404is clock shaper circuit100that was described inFIG.1and may be configured to receive clock signals and scan enable signals to provide a set of clock pulses for performing transition fault testing of an integrated CUT.

In some examples, the CPU406is a CISC-type (complex instruction set computer) CPU, RISC-type (reduced instruction set computer) CPU, MCU-type (microcontroller unit) CPU, or a digital signal processor (DSP). The CPU406includes one or more processor cores. The one or more processor cores are arranged to execute code for transforming the one or more processors into a special-purpose machine or improving the functions of other components in the electronic system400to provide a programmed output without performing similar operations on the one or more other processor cores. The CPU406includes memory and logic that store information frequently accessed from storage416.

The CPU406and the power supply408are coupled to the I/O port410. In an example, the I/O port410provides an interface that is configured to receive input from (and/or provide output to) the networked devices418.

In an example, a user controls the computing device402via the user interface (UI)414. In an example, during execution of software application420, a user provides inputs to the computing device402via the UI414, and receives outputs from the computing device402. In some examples, the outputs are provided via the display412, indicator lights, a speaker, vibrations and the like. The input is received as audio and/or video inputs (e.g., via voice or image recognition), and electrical and/or mechanical devices such as keypads, switches, proximity detectors, gyros, accelerometers, and the like.

In some examples, the storage416is memory such as on-processor cache, off-processor cache, RAM, flash memory, or disk storage for storing one or more software applications420(e.g., embedded application), that performs functions associated with the computing device402that are described herein in response to executing the one or more software applications420by the CPU406.

The networked device418can include any device (including test equipment) capable of point-to-point and/or networked communications with the computing device402. The computing device402is often coupled to peripherals and/or computing devices, including tangible, non-transitory media (such as flash memory) and/or cabled or wireless media. These and other input and output devices are selectively coupled to the computing device402by external devices via wireless or cabled connections. The storage416is accessible by the networked devices418. The CPU406, the storage416, and the power supply408are also optionally coupled to an external power supply (not shown), which is configured to receive power from a power source (such as a battery, solar cell, “live” power cord, inductive field, fuel cell, capacitor, and the like). While not shown inFIG.4, the power supply408includes power generating components. Power generating components include one or more power switches. Each of the power switches is independently controlled for generating power to supply power at various input voltages to various components of the computing device402. The computing device402operates in various power-saving modes wherein individual voltages are supplied (and/or turned off) by the power switches in accordance with a selected power-saving mode and the various components arranged within a specific power domain.

The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end-user and/or a third-party.

While certain components may be described herein as being of a particular process technology, these components may be exchanged for components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.