Patent ID: 12243781

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

The present disclosure is generally related to semiconductor devices and the fabrication thereof. Due to the scaling down of the semiconductor device, the geometry size between different components of the semiconductor device is getting smaller and smaller which may cause some issues and degrade the performance of the semiconductor device. For example, in a conventional fabrication of a continuous gate via layout, some of the metal lines may be very short due to the pitch size constraint of the continuous gate via scheme. Or, some of the metal lines may be shift away from the gate vias landed below them. The short metal lines may cause risk of high resistance, the shift away metal line may cause open issue. Thus, the layout density is lowered, and the time dependent dielectric breakdown (TDDB) and the reliability of the semiconductor device are reduced.

The present disclosure provides an L-shape gate via scheme to extend the gate via contact path for a half pitch, thereby can enlarge the metal line size, reduce the resistance, and mitigate the open issue. In the present disclosure, slot type etching and metal etching back processes are used to form the L-shape gate via. A dielectric feature (i.e. a hard mask) is formed over the removed corner of the L-shape gate via to improve the isolation between the gate via and the adjacent metal line. Therefore, the layout density is increased, the TDDB and the reliability of the semiconductor device can be improved. Of course, these advantages are merely exemplary, and no particular advantage is required for any particular embodiment.

FIG.1illustrates a flow chart of a method100for forming a semiconductor device200(hereafter called “device200” in short) in accordance with some embodiments of the present disclosure. Method100is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be performed before, during, and after method100, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. Method100is described below in conjunction with other figures, which illustrate various three-dimensional and cross-sectional views of device200during intermediate steps of method100. In particular,FIG.2illustrates a three-dimensional view of device200.FIGS.3-29,30A,30B, and31-33illustrate cross-sectional views of device200taken along plane A-A′ shown inFIG.2(that is, along an X-direction).

Device200may be an intermediate device fabricated during processing of an integrated circuit (IC), or a portion thereof, that may comprise static random-access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), fin-like FETs (FinFETs), metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other memory cells. Device200can be a portion of a core region (often referred to as a logic region), a memory region (such as a static random access memory (SRAM) region), an analog region, a peripheral region (often referred to as an input/output (I/O) region), a dummy region, other suitable region, or combinations thereof, of an integrated circuit (IC). In some embodiments, device200may be a portion of an IC chip, a system on chip (SoC), or portion thereof. The present disclosure is not limited to any particular number of devices or device regions, or to any particular device configurations. For example, though device200as illustrated is a three-dimensional FET device (e.g., a FinFET), the present disclosure may also provide embodiments for fabricating planar FET devices.

Referring toFIGS.1and2, at operation102, method100provides a device200comprising one or more semiconductor fins204(hereinafter fins204) and one or more gate structures210disposed over a substrate202. Fins204protruding from substrate202and separated by an isolation structure208. Gate structures210disposed over substrate202and fins204. Gate structures210define channel regions (such as C1, C2, C3), source regions and drain regions (such as SD1, SD2, SD3, SD4, all referred to as source/drain (S/D) regions) of fins204. Gate structures210may include metal gate stacks212and gate spacers214disposed along sidewalls of metal gate stacks212. Each metal gate stack212may include a metal gate electrode, a gate dielectric layer between the metal gate electrode and fins204, and a hard mask layer over the metal gate electrode. In some embodiments, each metal gate stack212may include one or more of a barrier layer, a glue layer, a capping layer, other suitable layers, or combinations thereof. Each metal gate stack212has a gate length GL in the X-direction, which defines the channel length of device200. Device200may also include S/D features220epitaxially grown over S/D regions of fins204. Device200may also include interlayer dielectric (ILD) layer230disposed over substrate202and fins204, and between gate structures210. It is understood components included in device200are not limited to the numbers and configurations as shown inFIG.2. More or less components, for example, more or less fins and gate structures, may be included in device200. In some other embodiments, device200may be a metal-oxide-semiconductor field-effect transistor (MOSFET) device without fin structures.FIG.3illustrate a cross-sectional view along plane A-A′ shown inFIG.2of device200(that is, along the X-direction).

In the depicted embodiment, substrate202is a bulk substrate that includes silicon. Alternatively or additionally, the bulk substrate includes another elementary semiconductor, a compound semiconductor, an alloy semiconductor, or combinations thereof. Alternatively, substrate202is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, substrate202may include n-type or p-type doped regions.

Semiconductor fins204are formed over substrate202. Each fin204may be suitable for providing an n-type FET or a p-type FET. Fins204are oriented substantially parallel to one another, for example, in the X-direction. Each of fins204has at least one channel region and at least one S/D region defined along their length in the X-direction, where the at least one channel region is covered by gate structures and is disposed between the S/D regions. In some embodiments, fins204are portions of substrate202(such as a portion of a material layer of substrate202). For example, in the depicted embodiment, where substrate202includes silicon, fins204include silicon. Alternatively, in some embodiments, fins204are defined in a material layer, such as one or more semiconductor material layers, overlying substrate202. For example, fins204can include a semiconductor layer stack having various semiconductor layers (such as a heterostructure) disposed over substrate202. The semiconductor layers can include any suitable semiconductor materials, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. The semiconductor layers can include same or different materials, etching rates, constituent atomic percentages, constituent weight percentages, thicknesses, and/or configurations depending on the design requirement of device200. Fins204are formed by any suitable process including various deposition, photolithography, and/or etching processes.

Isolation structure208is formed over substrate202and separates the lower portions of fins204. Isolation structure208electrically isolates active device regions and/or passive device regions of device200. Isolation structure208can be configured as different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, or combinations thereof. Isolation structure208includes an isolation material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), other suitable isolation material, or combinations thereof. Isolation structure208is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), PECVD, low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable deposition process, or combinations thereof. In some embodiments, isolation structure208is formed before fins204are formed (an isolation-first scheme). In some other embodiments, fins204are formed before isolation structure208is formed (a fin-first scheme). A planarization process, such as a chemical mechanical polishing (CMP) process, can be performed on isolation structure208.

In the depicted embodiment ofFIGS.2and3, various gate structures210are formed over fins204. Gate structures210extend along the Y-direction and traverse respective fin(s)204. Gate structures210may be formed by a gate replacement process. For example, first, dummy gate stacks are formed to wrap the channel regions of respective fins204. Each dummy gate stack may include a dummy gate electrode comprising polysilicon and various other layers, for example, a hard mask layer disposed over dummy gate electrode, and an interfacial layer disposed over fins204and substrate202, and below the dummy gate electrode.

Thereafter, spacers214are disposed along the sidewalls of the dummy gate stacks. Spacers214may comprise one or more dielectric layers. The dielectric layer may include any suitable dielectric material, such as silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof, and may be formed by any suitable method, such as ALD, CVD, PVD, other suitable methods, or combinations thereof. Top portions of the dielectric layer(s) may be removed by an etching process (such as dry etching, wet etching, or combinations thereof) or any other suitable process. The remaining portions of the dielectric layer(s) along the sidewalls of the dummy gate stacks form spacers214.

After the formation of epitaxial S/D features220as well as ILD layer230(will be discussed later), the dummy gate stacks are removed along spacers214using one or more etching processes (such as wet etching, dry etching, or combinations thereof), therefore leaving openings over the channel regions of fins204in place of the removed dummy gate stacks. Metal gate stacks212are then formed in the openings. For example, the opening is first filled with a high-k (K>3.9) dielectric material to form gate dielectric layer(s) by various processes, such as ALD, CVD, PVD, and/or other suitable process. Metal gate materials are then deposited over the gate dielectric layer to form the metal gate electrodes. In some embodiments, the metal gate electrodes include a work function metal and a fill metal. The work functional metal is configured to tune a work function of its corresponding FET to achieve a desired threshold voltage Vt. The fill metal is configured to serve as the main conductive portion of the functional gate structure. The metal gate electrodes are formed by various deposition processes, such as ALD, CVD, PVD, and/or other suitable process. A CMP process can be performed to remove any excess material of metal gate stacks212and/or spacers214to planarize gate structures210. As depicted inFIG.3, metal gate stacks212has a gate length GL in the X-direction.

Still referring toFIGS.2and3, device200also includes epitaxial S/D features220formed in the S/D regions of fins204. In some embodiments, first, S/D trenches are formed in the S/D regions of fins204. The S/D trenches may be formed by an etching process along the sidewalls of spacers214. Subsequently, semiconductor material (such as silicon germanium (SiGe), silicon phosphide (SiP) or silicon carbide (SiC)) is epitaxially grown in the S/D trenches over fins204, forming epitaxial S/D features220. In some embodiments, epitaxial S/D features220grow separately over each fin204, as depicted inFIG.2. In some other embodiments, epitaxial S/D features220extend (grow) laterally along the Y-direction, such that epitaxial S/D features220are merged and span more than one fin. In some embodiments, epitaxial S/D features220include partially merged portions and/or fully merged portions. An epitaxy process can implement CVD deposition techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. In some embodiments, epitaxial S/D features220are doped with n-type dopants and/or p-type dopants depending on a type of FET fabricated in their respective FET device region. In some embodiments, epitaxial S/D features220include materials and/or dopants that achieve desired tensile stress and/or compressive stress in the channel regions.

Device200also comprises an interlayer dielectric (ILD) layer230formed over substrate202, including isolation structure208and epitaxial S/D features220, and between gate structures210. ILD layer230includes a dielectric material including, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), tetraethylorthosilicate (TEOS) formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric material, other suitable dielectric material, or combinations thereof. In some embodiments, ILD layer230has a multilayer structure having multiple dielectric materials. In some embodiments, an ILD layer230may be formed by a deposition process (such as CVD, FCVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof) to cover isolation structure208, epitaxial S/D features220and the dummy gate stacks. Subsequent to the deposition of ILD layer230, a CMP process and/or other planarization process may be performed to expose the dummy gate stacks. Thereafter, the aforementioned metal gate replacement process may be implemented to replace the dummy gate stacks with metal gate stack212.

Now referring toFIGS.1and4, at operation104, metal gate structures210are recessed. In some embodiments, both metal gate stacks212and spacers are recessed. And, metal gate stacks212are further recessed such that top surfaces of metal gate stacks212are below top surfaces of spacers214, and both are below top surface of ILD layer230. Operation104may include various etching processes. For example, first, metal gate stacks212are recessed to a thickness H1by a selective etching process due to the different materials of metal gate stacks212and spacers214. Thereafter, spacers214are also selectively etched back to the thickness of H1. Then, metal gate stacks212are further selectively etched back to a thickness H2. The selective etching process may be selective dry etch, selective wet etch, other suitable etching process, or combinations thereof. In some embodiments, the thickness H1is about 2 nm to about 70 nm, and the thickness H2is about 1 nm to about 50 nm, which is about 10% to about 70% of H1. If the ratio of the thickness H2to H1is greater than 70%, it may reduce the volume of the bottom portion of the later formed via280A, thereby increase the resistance in some instances; and if the ratio of the thickness H2to H1is less than 10%, it may cause undesired short circuitry between the source/drain contacts, in some instances.

Now referring toFIGS.1,5, and6, at operation106, a hard mask240is deposited over substrate202. Referring toFIG.5, hard mask240is deposited over ILD layer230, gate structures210and epitaxial S/D features220. Hard mask240includes a different material from that of spacers214, such that hard mask240and spacers214can provide different etching selectivity in the following selective etching processes. In some embodiments, hard mask240may include one or more layers of material such as SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, other suitable materials, or combinations thereof. In some embodiments, hard mask240is disposed by a deposition processes, such as ALD, CVD, PVD, and/or other suitable process. Referring toFIG.6, a CMP process or other planarization process is performed to remove the excess material of hard mask240. In some embodiments, a portion of ILD layer230is also removed. In the depicted embodiment ofFIG.6, hard mask240has a thickness H3such that a top surface of hard mask240is above a top surface of spacer214(H2+H3>H1). In other words, hard mask240covers spacers214. In some embodiments, a thickness H3of hard mask240is about 10 nm to about 50 nm.

Now referring toFIGS.1and7-10, at operation108, S/D contacts248are formed over specific S/D regions (for example, SD2, SD3, and SD5) according to the design requirement of device200. Forming of S/D contacts248comprises multiple processes including various photolithography, etching, and/or deposition processes. For example, referring toFIGS.7and8, a photolithography process is performed. The photolithography process may include forming a photoresist layer (resist) overlying device200, exposing the resist to a pattern241, performing a post-exposure bake process, and developing the resist to form a masking element242including the resist. Masking element242is designed to expose specific S/D regions according to the design requirement of device200. Masking element242is then used to selectively remove ILD layer230over the specific S/D regions to form S/D contact openings244which expose top surfaces of epitaxial S/D features220in the specific S/D regions. The selectively removing process can include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, other suitable etching process, or combinations thereof.

As depicted inFIG.8, silicide layers246are then formed on the top surface of the exposed epitaxial S/D features220to reduce the S/D parasitic resistance. In some embodiments, a metal material is deposited on the exposed epitaxial S/D features220. An annealing process is then performed to cause constituents of the top surfaces of the exposed epitaxial S/D features220to react with the metal material. Silicide layers246thus include the metal material and a constituent of epitaxial S/D features220. Subsequently, any unreacted metal materials are removed (e.g. by etching), and the remained reacted material form silicide layer246.

Then, referring toFIGS.9and10, a conductive material is filled in S/D contact openings244to form S/D contacts248. In some embodiments, the conductive material includes tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), other conductive material, or combinations thereof. In some embodiments, the conductive material can be deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. Thereafter, one or more polishing processes (for example, CMP) may be performed to remove any excess conductive materials and planarize the top surface of device200. Masking element242can be removed before or after the filling of the conductive material.

Now referring toFIGS.1and11-13, at operation110, S/D contacts248are recessed and a hard mask250is deposited over the recessed S/D contacts248. Referring toFIG.11, top portions of S/D contacts248are removed by a selective etching process. In some embodiments, S/D contacts248are recessed to a thickness H4which is less than thickness H1of spacers214. In other words, top surfaces of S/D contacts248are below top surfaces of spacers214. In some embodiments, thickness H4of S/D contacts248is about 1 nm to about 50 nm which is about 10% to 70% of thickness H1of spacers214. Then, referring toFIGS.12and13, a hard mask250is formed over the recessed S/D contacts248. Hard mask250includes a material that can provide a different etching selectivity from the material of hard mask240. In some embodiments, hard mask250may include one or more layers of material such as SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, other suitable materials, or combinations thereof. In some embodiments, hard mask250is disposed by a deposition processes, such as ALD, CVD, PVD, and/or other suitable process. And, a CMP process or other planarization process is performed to remove the excess material of hard mask250and expose top surfaces of hard mask240and ILD layer230. In some embodiments, a thickness H5of hard mask250is about 10 nm to about 50 nm.

Now referring toFIGS.1and14-16, at operation112, ILD layer230in other S/D regions (such as SD1and SD4) of fins204is recessed and a hard mask260is deposited over the recessed ILD layer230over the other S/D regions. Referring toFIG.14, a top portion of ILD layer230in S/D regions SD1and SD4is removed by a selective etching process. In some embodiments, ILD layer230is recessed to a thickness H6which is less than thickness H1of spacers214. In some embodiments, H6is about 1 nm to about 50 nm which is about 10% to 70% of H1. In some embodiments, thickness H6of the recessed ILD layer230is substantially equal to thickness H2of the recessed metal gate stacks214. In some other embodiments, thickness H6of the recessed ILD layer230may be different from thickness H2of the recessed metal gate stacks214.

Thereafter, referring toFIGS.15and16, a hard mask260is formed over the recessed ILD layer230. In some embodiments, hard mask260includes the same material as hard mask250, which is different from the material of hard mask240and the material of ILD layer230, such that hard masks250and260have different etching selectivities than hard mask240and the material of ILD layer230during the formation of via trenches272and272′ (FIGS.21and22). In some embodiments, hard mask260may include one or more layers of material such as SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, other suitable materials, or combinations thereof. In some embodiments, hard mask250is disposed by a deposition processes, such as ALD, CVD, PVD, and/or other suitable process. And, a CMP process or other planarization process is performed to remove the excess material of hard mask260and expose top surfaces of hard mask240and hard mask250. In some embodiments, a thickness H7of hard mask250is about 10 nm to about 50 nm. As depicted inFIG.16, a combined thickness of the recessed metal gate stack212and hard mask240(i.e. H2+H3), a combined thickness of the recessed S/D contact248and hard mask250(i.e. H4+H5), and a combined thickness of the recessed ILD layer230and hard mask260(i.e. H6+H7) substantially equal to each other; and all are greater than thickness H1of spacers214. Since thickness H2of metal gate stack212and thickness H6of ILD layer230are less than thickness H1of spacer214, during the later gate via formation (where spacer214between metal gate stack212over C1and ILD layer230over SD1is also recessed), a conductive material can land on both metal gate stack212over C1and ILD layer230over SD1, thereby a conductive path of the gate via can be extended for a half pitch distance to ILD layer230over SD1. Therefore, the open issue between the gate via and the metal line can be solved and the reliability can be improved.

Now referring toFIGS.1and17, at operation114, an etch stop layer (ESL)262and a ILD layer264are deposited over device200. ESL262is deposited before the deposition of ILD layer264. In some embodiments, ESL262includes a material of SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, other suitable materials, or combinations thereof. In some embodiments, ILD layer264includes a dielectric material such as SiC, LaO, AlO, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, LaO, SiO, other dielectric material, or combinations thereof. The deposition of ESL262and ILD layer264may include any proper deposition process (such as CVD, PVD, ALD, etc.) and a CMP is performed to planarize the top surface of the layer(s).

Now referring toFIGS.1,18-22, at operation116, via trenches are formed for device200. First, referring toFIGS.18and19, a gate slot etching is performed to form via trenches over channel regions (such as C1, C2, and C3) of fins204. Referring toFIG.18, a patterned photoresist mask266is formed over ILD layer264. Photoresist mask266is patterned according to the design requirement of device200. In some embodiments, photoresist mask266includes slots over continuous channel regions. For example, slots266A,266B, and266C over continuous channel regions C1, C2, and C3, respectively. Chanel region C1is adjacent to S/D region SD1covered by ILD layer230and S/D region SD2covered by S/D contact248. Channel region C2is adjacent to S/D regions SD2and SD3, both are covered by S/D contacts248. Channel region C3is adjacent to S/D region SD3covered by S/D contact248and S/D region SD4covered by ILD layer230. In the depicted embodiment, a width W1of slot266A (one of the side slot of three continuous via slots) is greater than a width W2of slot266B (the middle slot of three continuous via slots), such that slot266A is also over spacer214-1between ILD layer230over SD1and metal gate stack212over C1. Although, in the depicted embodiment, the width W1is greater than W2which is substantially equal to W3, it is understood that base on the design requirement of the semiconductor device, it could be another side slot (such as slot266C) has a width W3greater than width W1and W2. Whether it's266A or266C, the side slot is over a channel region that is adjacent to a S/D region covered by ILD layer and is away from the middle slot.

Referring toFIG.19, one or more etching processes (including dry etch, wet etch, or combinations thereof) are performed along sidewalls of the patterned photoresist mask266to form gate via trenches268and268′ over continuous channel regions of fins204. For example, a first anisotropic etching process is performed to remove portions of ILD layer264along Z-direction. Subsequently, a second anisotropic etching process is performed to remove portions of ESL262along Z-direction, thereby to expose hard mask240. Thereafter, a third anisotropic selective etching process is performed to remove hard mask240to form via trenches268and268′. Since the materials of spacer214-1and hard mask260are different from that of hard mask240, spacer214-1and hard mask260remain substantially unchanged during the formation of via trench268. In the depicted embodiment, due to the greater slot width, via trench268not only expose metal gate stack212, but also expose spacer214-1. Via trenches268′ are formed over channel regions C2and C3continuous with channel region C1. Via trenches268′ only expose metal gate stack212.

Referring toFIGS.1,20-22, still at operation116, a S/D slot etching is performed to form via trenches over S/D regions (such as SD1and SD5) of fins204. Referring toFIG.20, a patterned photoresist mask270is formed over ILD layer264as well as within via trenches268and268′. Photoresist mask270is patterned according to the design requirement of device200. In the depicted embodiments, photoresist mask270includes at least a slot270A over the S/D region SD1covered by ILD layer230and is overlapped with via trench268. Photoresist mask270may also include a slot270B over another S/D region SD5. In some embodiments, a width W3of slot270A is greater than a width W4of slot270B and is over spacer214-1.

Thereafter, referring toFIGS.21and22, one or more etching processes (including dry etch, wet etch, or combinations thereof) are performed along sidewalls of the patterned photoresist mask270to form via trenches272and272′ over S/D regions of fins204. For example, portions of ILD layer264and ESL262may be removed by various anisotropic etching processes, such that hard masks250and260are exposed from the top surface of device200, as depicted inFIG.21. A top surface and a sidewall of spacer214-1are exposed in via trench272. Thereafter, a selective etching process is performed to remove hard masks250and260. The exposed portion of spacer214-1is also lost (from both top and side) during the etching process to remove hard mask260. In the depicted embodiment ofFIG.22, ILD layer230, recessed spacer214-1, and metal gate stack212exposed in via trench272are of a substantially (for example, a difference less than 20%) same thickness. In some other embodiments, top surfaces of ILD layer230, spacer214-1, and metal gate stack212exposed in via trench272may be of different thicknesses, but all are less than thickness H1of spacers214not exposed in Via trench272, such that a conductive material can be deposited over all top surfaces of metal gate stack212, spacer214-1, and ILD layer230exposed in via trench272, thereby can extend a conductive path of gate via over channel region C1over ILD layer230.

Now referring toFIGS.1,23and24, at operation118, vias280A,280B,280C, and280D (all referred to as vias280) are formed in via trenches272,272′ and268′. In the depicted embodiment, vias280A,280B, and280C land on metal gate stacks212, and thus are gate vias; via280D lands on S/D contact248, thus is a S/D via. Vias280are formed by various deposition and planarization processes. Vias280includes a conductive material served as a main functional metal of the vias. In some embodiments, vias280may also include a barrier layer providing diffusion barrier properties, which can prevent diffusion of the conductive material into ILD layer. And, the barrier layer is optional (not necessary) for the vias. As depicted inFIG.23, optionally, a barrier layer282, including a material such as Ta, TaN, Ti, TiN, other suitable material, or combinations thereof, is deposited in via trenches272,272′, and268′ and over ILD layer264. In some embodiments, barrier layer282has a thickness of less than about 5 nm. A conductive material284is then deposited over barrier layer282within via trenches272,272′,268′ and over ILD layer264by CVD, PVD, ALD, plating, other suitable process, or combinations thereof. Conductive material284includes W, Ru, Co, Cu, Mo, Ni, other conductive materials, or combinations thereof. Subsequently, referring toFIG.24, a planarization process (such as a CMP) is performed to remove top portion of conductive material284(and top portion of barrier layer282if available). In some embodiments, a top portion of ILD layer264is also removed. The remained portions of conductive material284(and barrier layer282if available) form vias280. Referring toFIG.24, via280A is landed on metal gate stack212, extends over spacer214-1, and further extends on ILD layer230. Thus, via280A extends the conductive path from metal gate stack212over channel region C1to ILD layer230over S/D region SD1. Vias280B and280C land on metal gate stacks212over channel regions C2and C3, respectively; and via280D land on S/D contact248over S/D region SD5. Referring toFIG.24, gate via280A has a thickness H8and a width W8. Width W8of gate via280A is greater than a width W6of gate vias280B or a width W7of S/D via280D. Thickness H8of gate via280A is substantially equal to thicknesses of gate vias280B and S/D via280D. In some embodiments, the thickness H8is about 2 nm to about 70 nm, and the width W8is about is about 10 nm to about 60 nm.

Now referring toFIGS.1,25, and26, at operation120, a top corner portion of via280A is removed such that via280A turns into an L-shape via. Referring toFIG.25, a patterned photoresist mask286is formed over device200. Photoresist mask286includes an opening exposing a portion of the top surface of via280A over metal gate stack212in channel region C1. An etching process is then performed through the opening of photoresist mask286to remove a top corner portion280P of via280A. Due to the different selectivities between the conductive material of via280A and the dielectric materials of ILD layer264, ESL262, and hard mask240, a selective metal etching process is implemented to remove the top corner portion280P. In the case that via280A include a barrier layer, both barrier layer282and conductive material284in the top corner portion280P are moved. For example, the selective metal etching process may include an oxygen base etchant with a flow rate of about 5 sccm to about 200 sccm and a plasma power of about 50 W to about 250 W, and under a pressure of about 1 mTorr to about 100 mTorr. Thereby, via280A turns into L-shape after the selective metal etching process, as depicted inFIG.26. In some embodiments, the removed top corner portion280P has a width W9which is about 10% to about 90% of the width W8of via280A, and a thickness H9is about 10% to about 90% of the thickness H8of via280A. If the removed top corner portion280P is too big (for example, W9is more than 90% of W8, or H9is more than 90% of H8), the L-shape via280A may be too thin, thereby cause large resistance or even a break out between the conductive features in some instances; or if the removed top corner portion280P is too small (for example, W9is less than 10% of W8, or H9is less than 10% of H8), the later formed patterned dielectric layer292A may not have a enough width, thereby cause undesired short circuitry between the metal lines296A and296B in some instances. In some embodiments, the width W9is about 1 nm to about 50 nm, and the thickness H9is about 1 nm to about 50 nm. Referring toFIG.26, L-shape via280A includes a first portion280-1and a second portion280-2. The first portion280-1contacts a top surface of metal gate stack212over channel region C1and the second portion280-2contacts a top surface of ILD layer230over S/D region SD1. A top surface of the first portion280-1is below a top surface of the second portion280-2for a distance H9which is about 10% to about 90% of a thickness H8of the second portion280-2. If the distance H9is greater than 90%, the first portion280-1may be too thin which is easy to be break out or cause large resistance between the conductive features; if the distance H9is less than 10%, high capacitance may occur between the via280A and the upper level adjacent metal lines, or even a short circuitry may occur therebetween. In other words, the first portion280-1has a thickness H8-H9, which is about 10% to about 90% of a thickness H8of the second portion280-2. The first portion280-1has a width W9which is about 10% to about 90% of the combined width W8of the first portion280-1and the second portion280-2. In some embodiments, depends on the width W9, the first portion280-1may also contact a top surface of spacer214and/or a portion of a top surface of ILD layer230. In some embodiments, depends on the width W9, the second portion280-2may also contact the top surface of spacer214and/or a portion of the top surface of metal gate stack214. In some embodiments, a sidewall of the first portion280-1away from the second portion280-2may contact hard mask240and/or spacer214, ESL262, and ILD layer264, and a sidewall of the second portion280-2away from the first portion280-1may contact ESL262, ILD layer264, spacer214, and/or hard mask240.

In the case that vias280include a barrier layer282, the barrier layer282around via280A extends along a sidewall of the first portion280-1away from the second portion280-2, to a bottom surface of L-shape via280A (including bottom surfaces of the first portion280-1and the second portion280-2), and further extends to a sidewall of the second portion280-2away from the first portion280-1. Top surfaces of the first portion280-1and second portion280-2are free of barrier layer282. And, a sidewall of the second portion280-2towards the first portion280-1is also free of barrier282.

Now referring toFIGS.1,27, and28, at operation122, a dielectric feature290(also referred to as a hard mask290) is formed in the place of the removed top corner portion280P of via280A. Dielectric feature290includes a low-K dielectric material (K<3.9) such as SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, other suitable materials, or combinations thereof. In some embodiments, the material of dielectric feature290is disposed over the removed top corner portion280P of via280A and over ILD layer264by a suitable deposition processes, such as ALD, CVD, PVD, and/or other suitable process. Thereafter, a CMP process or other planarization process is performed to remove the excess material of dielectric feature290. Referring toFIG.28, a bottom surface of dielectric feature290contacts the top surface of the first portion280-1of via280A. In the case that via280A includes a barrier layer282, the bottom surface of dielectric feature290contacts both top surfaces of the conductive material284and barrier layer282. A sidewall of dielectric feature290contacts the sidewall of the second portion280-2towards the first portion280-1of via280A. A top surface of dielectric feature290is substantially coplanar with the top surface of the second portion280-2of via280A. In some embodiments, dielectric feature290has a width W9and a thickness H9. Wherein, W9is about 1 nm to about 50 nm which is about 10% to about 90% of a width W8of via280A, and H9is about 1 nm to about 50 nm which is about 10% to about 90% of a thickness H8of via280A.

Now referring toFIGS.1,29,30A,30B,31, and32, at operation124, other processes (such as back-end-of-line (BEOL) fabrication) are performed to complete the fabrication of device200. For example, referring toFIG.29, a dielectric layer292is deposited over device200, specifically over ILD layer264, vias280, and dielectric feature290. Thereafter, as depicted inFIGS.30A and30B, the dielectric layer292is patterned through a photoresist mask294to form a patterned dielectric layer292(also referred to as cut ending) including different portions such as292A,292B,292C, and more, to define the positions of later formed metal lines296. In some embodiments, as depicted inFIG.30A, patterned dielectric layer292exposes top surfaces of vias280and covers the top surface of dielectric feature290. In some other embodiments, as depicted inFIG.30B, patterned dielectric layer292A can overlap with the second portion280-2of via280A. That is, patterned dielectric layer292A can be in direct contact with the second portion280-2of via280A, dielectric feature290, and ILD layer264. Patterned dielectric layer292A in different embodiments can cause different contacting areas between the later formed metal lines296A and via280A. AlthoughFIGS.31-33are described base on the embodiment of the patterned dielectric layer292A ofFIG.30A, it is understood that a shifting of metal line296A position may occur according to the patterned dielectric layer292A as depicted inFIG.30B.

Referring toFIGS.31and32, metal lines296A,296B,296C, and296D (all referred to as metal lines296) are formed over ILD layer264and vias280. In some embodiments, metals lines296includes a conductive material such as W, Ru, Co, Cu, Mo, Ni, other conductive material, or combinations thereof. Formation of metal lines296includes one or more deposition processes (such as CVD, PVD, ALD, plating, etc.) followed by a planarization process (such as CMP). Similar as the vias280, metal lines296may or may not include a barrier layer having a material of Ti, TiN, Ta, or TaN disposed around the conductive material of the metal lines296. Thereafter, other dielectric layers and conductive features may be formed to finish the fabrication of device200.

As depicted inFIG.32, all metal lines296connects to metal gate stacks212. Metal line296A contacts the top surface of the second portion280-2of via280A disposed on ILD layer230over S/D region SD1. And, the conductive path is extended to the first portion280-1of via280A to metal gate stack212over channel region C1. Metal line296B contacts a top surface of via280B disposed on metal gate stack212over channel region C2. Metal line296C contacts a top surface of via280C disposed on metal gate stack212over channel region C3. Patterned dielectric layer portions292A and292B are disposed between the metal lines296A and296B, and between the metal lines296B and296C, respectively.

In some embodiments, each of vias280may include a metal capping layer288on the top of via280. Referring toFIG.33, capping layer288of via280A is over the second portion280-2and contacts metal line296A. The first portion280-1of via280A is free of capping layer288. In the depicted embodiment, capping layers288of vias280B,280C, and280D cover the entire conductive surface thereof. In some embodiments, capping layer288includes a material such as Al, Ru, Co, Ta, Ti, Cu, other metal material, or a combination thereof and is deposited over the second portion280-2of via280A and the entire conductive surfaces of vias280B,280C, and280D.

Due to the challenge of the size scaling down in semiconductor industry, in a conventional continuous gate via scheme where no L-shape gate via is formed over the continuous channel regions (or metal gate stacks), distance between the gate vias over the adjacent channel regions may be very short. Since the pitch size between the metal lines (minimum center to center distance between the adjacent metal lines) is decided by the size of the cut ending (for example, portions of the patterned dielectric layer), the middle one of the metal lines over the continuous channel regions may be very short, thus may cause high resistance and degrade the performance of the semiconductor device. Or, if the side gate via over the continuous channel regions is landed below the dielectric cut ending and separate from the metal line, an open issue will occur to the side gate via, which may reduce the reliability of the semiconductor device.

However, in the present disclosure, the side gate via280A (in a continuous gate via scheme) is formed in an L-shape which extends the conductive path to a S/D region covered by a dielectric material (ILD layer230) and is away from the middle gate via280B. In other words, a conductive path of gate via280A extends from metal gate stack212over channel region C1to ILD layer230over S/D region SD1and connects to metal line296A via the first portion280-1over channel region C1and the second portion280-2over S/D region SD1. Thereby, the pitch size between metal line296A and296B is enlarged, for example, for a half pitch. Therefore, metal line296A over gate via280A can shifted away from gate via280B. As a result, the size of the middle metal line296B is no need to be reduced, and the contacting between the side metal line296A and the side gate via280A are enhanced. Dielectric feature290further ensure the isolation between gate via280A and metal line296B, thereby to mitigate the shortage issue that may happen therebetween. Therefore, the reliability and performance of the semiconductor device can be increased.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and a formation process thereof. For example, embodiments of the present disclosure provide a semiconductor device includes an L-shape conductive feature (for example, a gate via) which extends the conductive path away from an adjacent same level conductive feature (for example, an adjacent gate via), such that the pitch size of the higher level conductive features (for example, metal lines) can be enlarged. The present disclosure mitigates the high resistance and open issue of the conventional semiconductor device and increases the performance and reliability of the semiconductor device.

The present disclosure provides for many different embodiments. Semiconductor device having L-shape conductive feature and methods of fabrication thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

In some embodiments, the semiconductor device further comprises a first dielectric feature disposed on the first conductive portion of the first conductive feature, wherein a bottom surface of the first dielectric feature contacts a top surface of the first conductive portion of the first conductive feature, and a first sidewall of the first dielectric feature connects an upper portion of the first sidewall of the second conductive portion of the first conductive feature. In some embodiments, the first conductive feature of the first conductive feature includes a barrier layer having a first portion along a second sidewall of the first conductive portion of the first conductive feature, a second portion along a second sidewall of the second conductive portion of the first conductive feature, and a third portion below bottom surfaces of the first conductive portion and the second conductive portion of the first conductive feature. In some further embodiments, the first and second sidewalls of the first dielectric feature is free of the barrier layer.

In some embodiments, a thickness of the first dielectric feature is about 10% to about 90% of a thickness of the second conductive portion of the first conductive feature. In some embodiments, a width of the first dielectric feature is about 10% to about 90% of a total width of the first conductive portion and the second conductive portion of the first conductive feature. In some embodiments, a top surface of the second conductive portion of the first conductive feature contacts a bottom surface of a second conductive feature; and a top surface of the first dielectric feature contacts a bottom surface of a second dielectric feature disposed besides the second conductive feature. In some embodiments, the second conductive portion of the first conductive feature is away from the metal gate structure.

In some embodiments, the semiconductor device further comprises a spacer disposed between the first ILD layer and the metal gate structure, wherein a top surface of the spacer contacts at least one of a bottom surface of the first conductive portion of the first conductive feature and a bottom surface of the second conductive portion of the first conductive feature.

An exemplary method includes forming a semiconductor fin over a substrate; forming a metal gate structure over a channel region of the semiconductor fin; forming a first interlayer dielectric (ILD) layer over a source/drain (S/D) region next to the channel region of the semiconductor fin; forming a conductive feature on the metal gate structure and the first ILD layer; removing a top corner portion of the conductive feature to form an L-shape conductive feature, wherein the top corner portion is over at least a portion of the metal gate structure; and filling the top corner portion of the L-shape conductive feature with a first dielectric feature.

In some embodiments, the method further comprises forming a higher-level conductive feature contacting a top surface of the L-shape conductive feature; and a second dielectric feature contacting a top surface of the first dielectric feature.

In some embodiments, the method further comprises forming a second ILD layer over the metal gate structure and the first ILD layer before forming the conductive feature on the metal gate structure and the first ILD layer. In some further embodiments, the forming the conductive feature on the metal gate structure and the ILD layer includes forming a first trench through the second ILD layer to expose the metal gate structure; forming a second trench through the second ILD layer to expose the first ILD layer; depositing a conductive material over the first ILD layer and the metal gate structure in the first trench and the second trench; and planarizing the conductive material and the second ILD layer to form the conductive feature.

In some embodiments, the removing the top corner portion of the conductive feature to form the L-shape conductive feature includes forming a patterned photoresist layer over the conductive feature to expose the top corner portion of the conductive feature, wherein a width of the top corner portion is about 10% to about 90% of a width of the conductive feature; and etching the top corner portion of the conductive feature to form the L-shape conductive feature. In some embodiments, a depth of the top corner portion is about 5 nm to about 50 nm.

Another exemplary method includes forming a semiconductor fin over a substrate; forming a metal gate structure over a channel region of the semiconductor fin; forming a first interlayer dielectric (ILD) layer over a first source/drain (S/D) region next to the channel region of the semiconductor fin; forming a first conductive feature over the metal gate structure and the first ILD layer, wherein the first conductive feature includes a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion contacts a lower portion of a first sidewall of the second conductive portion; and forming a dielectric feature on a top surface of the first conductive portion of the first conductive feature.

In some embodiments, the method further comprises forming a first hard mask over the metal gate structure; and forming a second hard mask over the ILD layer, wherein a material of the second hard mask is different from a material of the first hard mask.

In some embodiments, the forming the L-shape conductive feature includes forming a second ILD layer over the first hard mask and the second hard mask; forming a first slot in the second ILD layer to expose at least a portion of the first hard mask; removing the exposed portion of the first hard mask through the first slot to expose at least a portion of the metal gate structure; forming a second slot in the second ILD layer to expose at least a portion of the second hard mask; removing the exposed portion of the second hard mask through the second slot to expose at least a portion of the first ILD layer; depositing a first conductive material on the exposed portions of the first ILD layer and the metal gate structure through the first and the second slots; planarizing top portions of the first conductive material and the second ILD layer; and removing a top corner portion of the first conductive material to form the first conductive feature.

In some embodiments, the method further comprises forming a spacer between the metal gate structure and the first ILD layer, wherein forming the first and the second slots in the second ILD layer expose the spacer; removing a top portion of the space when removing the exposed portion of the fourth hard mask; and depositing the conductive material on the spacer.

In some embodiments, the method further comprises depositing a dielectric layer over the second ILD layer and the dielectric feature; patterning the dielectric layer to form openings, wherein the openings expose at least a portion of the first conductive feature; depositing a second conductive material in the openings; and removing a top portion of the second conductive material to form a second conductive feature.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.