Patent ID: 12205646

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Hereinafter, embodiments of the inventive concept will be described with reference to NAND flash memory. However, the inventive concept is not limited to NAND flash memory. The inventive concept may be applied to various non-volatile memory devices such as electrically erasable and programmable read only memory (ROM) (EEPROM), a NOR flash memory device, phase-change random access memory (RAM) (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

FIG.1is a block diagram illustrating a memory device100according to an embodiment of the inventive concept.

Referring toFIG.1, the memory device100may include a memory cell array110, a page buffer circuit120, a control logic130, a voltage generator140, an address decoder150, and a data input and output circuit160. In addition, the control logic130may include a coarse-fine verification control module132operated according to embodiments of the inventive concept, as described later. The memory device100may further include other various function blocks related to a memory operation. The coarse-fine verification control module132may be implemented by hardware logic or software logic. In addition, the coarse-fine verification control module132may be included in a memory controller.

The memory cell array110may include a plurality of strings (or cell strings) arranged on a substrate in rows and columns. Each of the plurality of strings may include a plurality of memory cells stacked in a direction perpendicular to the substrate. In other words, the plurality of memory cells may be stacked in the direction perpendicular to the substrate and may configure a three-dimensional structure. Each of the plurality of memory cells may be of a cell type such as a single level cell, a multilevel cell, a triple level cell, or a quadruple level cell. The inventive concept may be flexibly applied in accordance with each of the various cell types of each of the plurality of memory cells.

According to an embodiment of the inventive concept, as examples of the memory cell array110, the disclosures of U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Publication No. 2011/0233648, which describe a three-dimensional memory cell array that has a plurality of levels and word lines WL and/or bit lines BL are shared among the plurality of levels, are incorporated by reference herein in their entireties. In addition, the disclosures of U.S. Patent Publication Nos. 2012-0051138 and 2011-0204420 are incorporated by reference herein in their entireties.

The plurality of memory cells of the memory cell array110may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. The memory cell array110may be connected to the address decoder150through the word lines WL, the string selection lines SSL, and the ground selection lines GSL and may be connected to the page buffer circuit120through the bit lines BL.

The page buffer circuit120may temporarily store data to be programmed to the memory cell array110and read data from the memory cell array110. The page buffer circuit120may include a plurality of page buffers (or a plurality of latch units). For example, each of the plurality of page buffers may include a plurality of latches respectively corresponding to the plurality of bit lines BL and may store data in units of pages. In some embodiments of the inventive concept, the page buffer circuit120may include a sensing latch unit and the sensing latch unit may include a plurality of sensing latches respectively corresponding to the plurality of bit lines BL. In addition, each of the plurality of sensing latches may be connected to a sensing node for sensing data through a corresponding bit line.

The control logic130may control an overall operation of the memory device100and, for example, may output various internal control signals for programming data to the memory cell array110, reading data from the memory cell array110, or erasing data stored in the memory cell array110based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller.

The various internal control signals output from the control logic130may be provided to the page buffer circuit120, the voltage generator140, and the address decoder150. For example, the control logic130may provide a voltage control signal CS_vol to the voltage generator140. The voltage generator140may include one or more pumps and may generate voltages VWL having various levels in accordance with a pumping operation based on the voltage control signal CS_vol. In addition, the control logic130may provide a row address X_ADD to the address decoder150and may provide, to the page buffer circuit120, a column address Y_ADD and a page buffer control signal PB_CS for controlling the page buffer circuit120. Hereinafter, an operation of the coarse-fine verification control module132will be described. The control logic130may generate internal control signals conforming to the operation of the coarse-fine verification control module132and may output the generated internal control signals to the respective function blocks of the memory device100.

The control logic130may control first and second step program operations of the memory device100in response to a program command CMD. The first step program operation may let the plurality of memory cells of the memory cell array110form a plurality of first threshold voltage distributions. The plurality of first threshold voltage distributions, which are approximately formed before the second step program operation is performed, may be referred to as a plurality of approximate threshold voltage distributions. The second step program operation may let the plurality of memory cells form the plurality of second threshold voltage distributions respectively corresponding to the plurality of program states subsequent to the first step program operation. The plurality of second threshold voltage distributions, which are correctly formed to distinguish a program state, may be referred to as a plurality of target threshold voltage distributions. For example, a number of the approximate threshold voltage distributions resulting from the first step program operation may be different from or equal to a number of the target threshold voltage distributions resulting from the second step program operation. For example, when the number of approximate threshold voltage distributions is 8 and the number of target threshold voltage distributions is 16, the first and second step program operations may be referred to as ‘8-16’ step program operations. In another example, when the number of approximate threshold voltage distributions is 16 and the number of target threshold voltage distributions is 16, the first and second step program operations may be referred to as ‘16-16’ step program operations.

According to an embodiment of the inventive concept, the second step program operation may include a program loop, a coarse verification operation, and a fine verification operation. The memory device100may repeat the program loop until the plurality of memory cells form the plurality of target threshold voltage distributions through the coarse verification operation and the fine verification operation in the second step program operation. For example, in the second step program operation, among memory cells included in a predetermined threshold voltage distribution, memory cells having a threshold voltage of no less than a coarse verification voltage pass the coarse verification operation and the program loop may be repeated for memory cells having a threshold voltage less than the coarse verification voltage. In other words, memory cells with a threshold voltage greater than the coarse verification voltage pass the coarse verification operation, while memory cells having a threshold voltage less than the coarse verification voltage fail and thus the program loop is repeated for the failing memory cells. When all the memory cells included in the predetermined threshold voltage distribution pass the coarse verification operation, the fine verification operation is performed thereon, and memory cells having a threshold voltage of no less than a fine verification voltage pass the fine verification operation and the program loop may be repeated for memory cells having a threshold voltage less than the fine verification voltage. Therefore, in the second step program operation, the predetermined threshold voltage distribution may move to a target threshold voltage distribution. For example, a level of the coarse verification voltage used for the coarse verification operation and a level of the fine verification voltage used for the fine verification operation may vary in accordance with a program state to be verified.

According to an embodiment of the inventive concept, the coarse-fine verification control module132may control the coarse verification operation and the fine verification operation included in the second step program operation. The operation of the coarse-fine verification control module132, as described hereinafter, may be referred to as an operation of the control logic130. The coarse-fine verification control module132may control the coarse verification operation and the fine verification operation by using the coarse verification voltage and the fine verification voltage based on offset information including a plurality of offsets in accordance with characteristics by target threshold voltage distribution.

The offset may be a difference between the coarse verification voltage and the fine verification voltage and may refer to a level difference between the coarse verification voltage and the fine verification voltage or a length difference between a first develop interval using the coarse verification voltage and a second develop interval using the fine verification voltage. In the first or second develop interval, a voltage of a sensing node corresponding to a bit line connected to a corresponding memory cell in the page buffer circuit120is developed from a predetermined precharge voltage to verify a program state of the memory cell.

The characteristics by target threshold voltage distribution may be referred to as estimated moving distances through the second step program operation from the plurality of approximate threshold voltage distributions formed through the first step program operation in a direction in which a threshold voltage increases. For example, the target threshold voltage distributions may include first and second target threshold voltage distributions and, in the second target threshold voltage distribution, an estimated moving distance through the second step program operation may be greater than that in the first target threshold voltage distribution. In this case, an offset between the coarse verification voltage and the fine verification voltage for forming the second target threshold voltage distribution may be greater than an offset between the coarse verification voltage and the fine verification voltage for forming the first target threshold voltage distribution. In some embodiments of the inventive concept, the characteristics by target threshold voltage distribution may be referred to as distribution speeds of the plurality of target threshold voltage distributions in the second step program operation. For example, a distribution speed of the second target threshold voltage distribution may be greater than a distribution speed of the first target threshold voltage distribution in the second step program operation. In this case, the offset between the coarse verification voltage and the fine verification voltage for forming the second target threshold voltage distribution may be greater than the offset between the coarse verification voltage and the fine verification voltage for forming the first target threshold voltage distribution.

According to an embodiment of the inventive concept, the coarse-fine verification control module132may control the coarse verification operation and the fine verification operation by using the coarse verification voltage and the fine verification voltage having a previously determined offset by target threshold voltage distribution with reference to the offset information. According to an embodiment of the inventive concept, the offset information may be stored in a predetermined region of the memory cell array110or an electronic fuse circuit included in the memory device100. Specific embodiments of the offset information will be described later.

In addition, according to an embodiment of the inventive concept, the offset information may include offsets respectively corresponding to a plurality of program methods. The control logic130may control the first and second step program operations based on a program method selected from the plurality of program methods. The program method may vary in accordance with a cell type of a memory cell in accordance with the number of bits of program data and a program sequence for memory cells. According to an embodiment of the inventive concept, the coarse-fine verification control module132may control the coarse verification operation and the fine verification operation by obtaining offsets corresponding to program methods applied to the current first and second step program operations from the offset information. According to an embodiment of the inventive concept, the offset information may be previously generated in a process of mass producing or testing the memory device100.

The memory device100according to an embodiment of the inventive concept may increase intervals among the target threshold voltage distributions as much as possible by performing the coarse verification operation and the fine verification operation considering the characteristics by target threshold voltage distribution in the second step program operation. As a result, the memory device100may guarantee increased data reliability.

FIG.2Ais a diagram illustrating the memory cell array110ofFIG.1,FIG.2Bis a perspective view of the memory cell array110ofFIG.1, andFIG.2Cis a view illustrating an equivalent circuit of a first memory block BLK1ofFIG.2A.

Referring toFIGS.1and2A, the memory cell array110may include a plurality of memory blocks BLK1to BLKz. Each of the plurality of memory blocks BLK1to BLKz may have a three-dimensional structure (or a vertical structure). For example, each of the plurality of memory blocks BLK1to BLKz may include structures extending in first to third directions. Each of the plurality of memory blocks BLK1to BLKz may include a plurality of cell strings extending in the second direction. The plurality of cell strings may be apart from one another in the first and third directions. Cell strings of one memory block are connected to a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of word lines WL, one ground selection line or a plurality of ground selection lines GSL, and a common source line. The cell strings of the plurality of memory blocks BLK1to BLKz may share the plurality of bit lines BL. For example, the plurality of bit lines BL may extend in the second direction and may be shared by the plurality of memory blocks BLK1to BLKz.

The plurality of memory blocks BLK1to BLKz may be selected by the address decoder150illustrated inFIG.1. For example, the address decoder150may select a memory block corresponding to the received address ADDR among the plurality of memory blocks BLK1to BLKz. Programming, reading, and erasing may be performed by the selected memory block. In addition, the first and second step program operations according to embodiments of the inventive concept may be performed by the selected memory block; however, this is merely an example. For example, the inventive concept is not limited thereto, and thus, the first and second step program operations may be performed in units of memory sub-blocks or predetermined memory groups.

Referring toFIG.2Bfurther, a substrate111is provided. The substrate111may be a first conductive-type well. In the substrate111, a plurality of common source regions CSR extending in the first direction and apart from one another in the second direction may be provided. The plurality of common source regions CSR may be commonly connected to configure a common source line. The plurality of common source regions CSR have a second conductive type that is different from the first conductive type of the substrate111.

Between two adjacent common source regions of the plurality of common source regions CSR, a plurality of insulating materials112and112amay be sequentially provided on the substrate111in the third direction (e.g., perpendicular to the substrate111). The plurality of insulating materials112and112amay be apart from one another in the third direction. The plurality of insulating materials112and112amay extend in the first direction.

Between the two adjacent common source regions, a plurality of pillars PL sequentially arranged in the first direction and passing through the plurality of insulating materials112and112ain the second direction may be provided. The plurality of pillars PL may contact the substrate111through the plurality of insulating materials112and112a. Between the two adjacent common source regions, the plurality of pillars PL may be apart from one another in the first direction. The plurality of pillars PL may be arranged in line in the first direction.

The plurality of pillars PL may include a plurality of materials. For example, the plurality of pillars PL may include channel layers114and internal materials115. The channel layers114may include a first conductive-type semiconductor material (for example, silicon). The channel layers114may include a semiconductor material (for example, silicon) having the same conductive type as that of the substrate111. The channel layers114may include an intrinsic semiconductor that does not have a conductive type.

The internal materials115may include an insulating material. For example, the internal materials115may include an insulating material such as silicon oxide. For example, the internal materials115may include an air gap. Between the two adjacent common source regions, information storage layers116may be provided on exposed surfaces of the plurality of insulating materials112and112aand the plurality of pillars PL. The information storage layers116may store information by capturing or draining charges.

Between the two adjacent common source regions and among the plurality of insulating materials112and112a, first, second, third, fourth, fifth, sixth, seventh and eighth conductive materials CM1, CM2, CM3, CM4, CM5, CM6, CM7and CM8are provided on exposed surfaces of the information storage layers116. The first to eighth conductive materials CM1to CM8may extend in the first direction. On the plurality of common source regions CSR, the first to eighth conductive materials CM1to CM8may be separated by word line cuts WL_Cut. The word line cuts WL_Cut may expose the plurality of common source regions CSR. The word line cuts WL_Cut may extend in the first direction. The first to eighth conductive materials CM1to CM8may include a metallic conductive material. The first to eighth conductive materials CM1toy CM8may include a non-metallic conductive material such as polysilicon.

The information storage layers116provided on an upper surface of the insulating material in the uppermost portion of the plurality of insulating materials112and112amay be removed. The information storage layers116provided on a side surface facing the plurality of pillars PL among side surfaces of the plurality of insulating materials112and112amay be removed.

A plurality of drains320may be provided on the plurality of pillars PL. The plurality of drains320may include a second conductive-type semiconductor material (for example, silicon). For example, the plurality of drains320may include an N conductive-type semiconductor material (for example, silicon).

On the plurality of drains320, the plurality of bit lines BL extending in the second direction and apart from one another in the first direction may be provided. The plurality of bit lines BL are connected to the plurality of drains320. The plurality of drains320may be connected to the plurality of bit lines BL through contact plugs. First and second bit lines BL1and BL2(seeFIG.2Cor BL inFIG.2B) may include metallic conductive materials. The first and second bit lines BL1and BL2may include non-metallic conductive materials such as polysilicon. The first to eighth conductive materials CM1to CM8may have first to eighth heights in this order from the substrate111.

The plurality of pillars PL may form the plurality of strings together with the information storage layers116and the first to eighth conductive materials CM1to CM8. Each of the plurality of pillars PL may configure one string together with the information storage layers116and adjacent conductive materials of the first to eighth conductive materials CM1to CM8. On the substrate111, the plurality of pillars PL may be provided in rows and columns. The eighth conductive material CM8may configure rows. Pillars connected to the same eighth conductive material may configure one row. The plurality of bit lines BL may configure columns. Pillars connected to the same bit line may configure one column. The plurality of pillars PL configure the plurality of strings arranged in rows and columns together with the information storage layers116and the first to eighth conductive materials CM1to CM8. Each of the plurality of strings may include a plurality of cell transistors (or memory cells) stacked in a direction perpendicular to the substrate111.

Referring toFIG.2C, cell strings CS11, CS12, CS21, and CS22may be between the first and second bit lines BL1and BL2and a common source line CSL. The cell strings CS11and CS21may be connected between the first bit line BL1and the common source line CSL. The cell strings CS12and CS22may be connected between the second bit line BL2and the common source line CSL. The plurality of common source regions CSR (refer toFIG.2B) may be commonly connected and may configure the common source line CSL.

Memory cells with the same height are commonly connected to one word line and, when a voltage is supplied to a word line with a specific height, the voltage may be supplied to all the strings CS11, CS12, CS21, and CS22. Strings in different rows may be respectively connected to first and second string selection lines SSL1and SSL2. By selecting or not selecting the first and second string selection lines SSL1and SSL2, the strings CS11, CS12, CS21, and CS22may be selected or may not be selected in units of rows. For example, the strings CS11and CS12or CS21and CS22connected to the string selection line SSL1or SSL2that is not selected may be electrically separated from the first and second bit lines BL1and BL2. The strings CS21and CS22or CS11and CS12connected to the selected string selection line SSL2or SSL1may be electrically connected to the first and second bit lines BL1and BL2.

The strings CS11, CS12, CS21, and CS22may be connected to the first and second bit lines BL1and BL2in units of columns. The strings CS11and CS21may be connected to the first bit line BL1and the strings CS12and CS22may be connected to the second bit line BL2. By selecting or not selecting the first and second bit lines BL1and BL2, the strings CS11, CS12, CS21, and CS22may be selected or may not be selected in units of columns.

The first memory block BLK1may further include a plurality of memory cells MC1to MC6respectively connected to a plurality of word lines WL1to WL6, a ground selection transistor GST connected to a ground selection line GSL and a string selection transistor SST connected to one of the first or second string selection lines SSL1and SSL2.

FIG.3is a flowchart illustrating a method of operating a memory device, according to an embodiment of the inventive concept.

Referring toFIG.3, in operation S100, the memory device may perform a first step program operation on a plurality of memory cells. The memory device may form a plurality of approximate threshold voltage distributions through the first step program operation. In operation S120, the memory device may perform a second step program operation on a plurality of memory cells by using a coarse verification voltage and a fine verification voltage conforming to characteristics of target threshold voltage distributions. For example, the target threshold voltage distributions include first and second target threshold voltage distributions and, when characteristics of the first target threshold voltage distribution are different from characteristics of the second target threshold voltage distribution, the memory device may control an offset between a coarse verification voltage and a fine verification voltage used for forming the first target threshold voltage distribution to be different from an offset between a coarse verification voltage and a fine verification voltage used for forming the second target threshold voltage distribution.

FIGS.4A to4Care views illustrating various program methods based on memory cell types according to embodiments of the inventive concept.

Referring toFIG.4A, when a memory cell type is a multilevel cell, memory cells may form a target threshold voltage distribution E corresponding to an erase state and target threshold voltage distributions P1to P3respectively corresponding to first to third program states as a result of performing first and second step program operations according to embodiments of the inventive concept.

Referring toFIG.4B, when a memory cell type is a triple level cell, memory cells may form a target threshold voltage distribution E corresponding to an erase state and target threshold voltage distributions P1to P7respectively corresponding to first to seventh program states as a result of performing first and second step program operations according to embodiments of the inventive concept.

Referring toFIG.4C, when a memory cell type is a quadruple level cell, memory cells may form a target threshold voltage distribution E corresponding to an erase state and target threshold voltage distributions P1to P15respectively corresponding to first to fifteenth program states as a result of performing first and second step program operations according to embodiments of the inventive concept.

The embodiments illustrated inFIGS.4A to4Care merely examples, and thus, the inventive concept is not limited thereto and may also be applied to various memory cell types that are not illustrated inFIGS.4A to4C.

FIGS.5A and5Bare views illustrating a program method of first and second step program operations of a memory device according to an embodiment of the inventive concept. Hereinafter, for convenience sake, a threshold voltage distribution corresponding to an erase state is omitted and it is premised that a memory cell type is a triple level cell, for ease of understanding. Embodiments of the inventive concept are not limited thereto.

Referring toFIG.5A, the memory device may form first to fourth approximate threshold voltage distributions P1_1to P4_1by performing the first step program operation on memory cells. The memory device may form first to seventh target threshold voltage distributions P1to P7by performing the second step program operation on the memory cells subsequent to the first step program operation. For example, the first and second target threshold voltage distributions P1and P2may be moved from the first approximate threshold voltage distribution P1_1. The third and fourth target threshold voltage distributions P3and P4may be moved from the second approximate threshold voltage distribution P2_1. The fifth and sixth target threshold voltage distributions P5and P6may be moved from the third approximate threshold voltage distribution P3_1. The seventh target threshold voltage distribution P7may be moved from the fourth approximate threshold voltage distribution P4_1.

According to an embodiment of the inventive concept, characteristics of the second, fourth, and sixth target threshold voltage distributions P2, P4, and P6respectively corresponding to even program states may be different from characteristics of the first, third, fifth, and seventh target threshold voltage distributions P1, P3, P5, and P7respectively corresponding to odd program stages. For example, the movement distance of the second target threshold voltage distribution P2from the first approximate threshold voltage distribution P1_1may be greater than the movement distance of the first target threshold voltage distribution P1from the first approximate threshold voltage distribution P1_1. In addition, a distribution speed of the second target threshold voltage distribution P2may be greater than a distribution speed of the first target threshold voltage distribution P1. The movement distance may be a distance between the minimum threshold voltage or the maximum threshold voltage of an approximate threshold voltage distribution and the minimum threshold voltage or the maximum threshold voltage of a target threshold voltage distribution. The minimum threshold voltage of the first approximate threshold voltage distribution P1_1may refer to the leftmost side of the first approximate threshold voltage distribution P1_1, and the maximum threshold voltage of the first approximate threshold voltage distribution P1_1may refer to the rightmost side of the first approximate threshold voltage distribution P1_1.

According to an embodiment of the inventive concept, the memory device may control a coarse verification voltage and a fine verification voltage so that a first offset for forming the second, fourth, and sixth target threshold voltage distributions P2, P4, and P6is greater than a second offset for forming the first, third, fifth, and seventh target threshold voltage distributions P1, P3, P5, and P7. In other words, the memory device may form the second, fourth, and sixth target threshold voltage distributions P2, P4, and P6by using the coarse verification voltage and the fine verification voltage having the first offset considering fast distribution characteristics or long estimated movement distances of the second, fourth, and sixth target threshold voltage distributions P2, P4, and P6. The memory device may form the first, third, fifth, and seventh target threshold voltage distributions P1, P3, P5, and P7by using the coarse verification voltage and the fine verification voltage having the second offset considering slow distribution characteristics or short estimated movement distances of the first, third, fifth, and seventh target threshold voltage distributions P1, P3, P5, and P7.

Referring toFIG.5B, the memory device may form first to seventh approximate threshold voltage distributions P1_1to P7_1by performing the first step program operation on memory cells. The memory device may form first to seventh target threshold voltage distributions P1to P7by performing the second step program operation on the memory cells subsequent to the first step program operation. For example, the first to seventh target threshold voltage distributions P1to P7may be moved from the first to seventh approximate threshold voltage distributions P1_1to P7_1.

According to an embodiment of the inventive concept, characteristics of some of the first to seventh target threshold voltage distributions P1to P7may be the same as one another and characteristics of the other ones of the first to seventh target threshold voltage distributions P1to P7may be different from one another. For example, the first and second target threshold voltage distributions P1and P2may have the same characteristics and the third target threshold voltage distribution P3may have difference characteristics from the first and second target threshold voltage distributions P1and P2. The second step program operation may be performed considering the characteristics of the first to seventh target threshold voltage distributions P1to P7, which are different from or the same as one another.

FIGS.6A and6Bare views illustrating first and second step program operations of a memory device according to an embodiment of the inventive concept. Hereinafter, for convenience sake, only some of a plurality of target threshold voltage distributions are illustrated and described. In addition, a description hereinafter is an example for describing the inventive concept and the inventive concept is not limited thereto.FIG.6Acorresponds to the embodiment described with reference toFIG.5AandFIG.6Bcorresponds to the embodiment described with reference toFIG.5B. Hereinafter, a description previously given with reference toFIGS.5A and5Bmay be omitted.

Referring toFIG.6A, a memory device may form a first target threshold voltage distribution P1from a first approximate threshold voltage distribution P1_1by performing a second step program operation using a coarse verification voltage V_c11having a first level and a fine verification voltage V_f11having a second level. An offset os11between the coarse verification voltage V_c11and the fine verification voltage V_f11used for forming the first target threshold voltage distribution P1may be referred as a first offset. The memory device may form a second target threshold voltage distribution P2from the first approximate threshold voltage distribution P1_1by performing the second step program operation using a coarse verification voltage V_c12having a third level and a fine verification voltage V_f12having a fourth level. An offset os12between the coarse verification voltage V_c12and the fine verification voltage V_f12used for forming the second target threshold voltage distribution P2may be referred as a second offset. According to an embodiment of the inventive concept, the second offset os12may be greater than the first offset os11, which may be a result obtained by considering a characteristic in which the second target threshold voltage distribution P2has a faster distribution or a longer estimated movement distance than the first target threshold voltage distribution P1in the second step program operation. This is an example embodiment, and the inventive invention is not limited thereto. For example, the first offset os11may be greater than the second offset os12in accordance with characteristics by target threshold voltage distributions.

The memory device may form a third target threshold voltage distribution P3from a second approximate threshold voltage distribution P2_1by performing the second step program operation using a coarse verification voltage V_c21having a fifth level and a fine verification voltage V_f21having a sixth level. An offset os21between the coarse verification voltage V_c21and the fine verification voltage V_f21used for forming the third target threshold voltage distribution P3may be referred as a third offset. The memory device may form a fourth target threshold voltage distribution P4from the second approximate threshold voltage distribution P2_1by performing the second step program operation using a coarse verification voltage V_c22having a seventh level and a fine verification voltage V_f22having an eighth level. An offset os22between the coarse verification voltage V_c22and the fine verification voltage V_f22used for forming the fourth target threshold voltage distribution P4may be referred as a fourth offset. According to an embodiment of the inventive concept, the fourth offset os22may be greater than the third offset os21, which may be a result obtained by considering a characteristic in which the fourth target threshold voltage distribution P4has a faster distribution or a longer estimated movement distance than the third target threshold voltage distribution P3in the second step program operation. This is an example embodiment, and the inventive invention is not limited thereto. For example, the third offset os21may be greater than the fourth offset os22in accordance with characteristics by target threshold voltage distributions.

According to an embodiment of the inventive concept, the first and third offsets os11and os21may be the same as or similar to each other and the second and fourth offsets os12and os22may be the same as or similar to each other. In addition, it is illustrated inFIG.6Athat the first to fourth offsets os11, os12, os21, and os22correspond to a level difference between the coarse verification voltage and the fine verification voltage. However, the inventive concept is not limited thereto, and the first to fourth offsets os11, os12, os21, and os22may correspond to a length difference between a develop interval using the coarse verification voltage and a develop interval using the fine verification voltage.

Referring toFIG.6B, a memory device may form a first target threshold voltage distribution P1from a first approximate threshold voltage distribution P1_1by performing a second step program operation using a coarse verification voltage V_c1having a first level and a fine verification voltage V_f1having a second level. An offset os1between the coarse verification voltage V_c1and the fine verification voltage V_f1used for forming the first target threshold voltage distribution P1may be referred as a first offset. The memory device may form a second target threshold voltage distribution P2from a second approximate threshold voltage distribution P2_1by performing the second step program operation using a coarse verification voltage V_c2having a third level and a fine verification voltage V_f2having a fourth level. An offset os2between the coarse verification voltage V_c2and the fine verification voltage V_f2used for forming the second target threshold voltage distribution P2may be referred as a second offset. According to an embodiment of the inventive concept, the second offset os2may be greater than the first offset os1, which may be a result obtained by considering a characteristic in which the second target threshold voltage distribution P2has a faster distribution or a longer estimated movement distance than the first target threshold voltage distribution P1in the second step program operation. This is an example embodiment, and the inventive invention is not limited thereto. For example, the first offset os1may be greater than the second offset os2in accordance with characteristics by target threshold voltage distributions.

FIGS.7A and7Bare views illustrating a program method in accordance with a program sequence among various program methods according to embodiments of the inventive concept;FIGS.7C and7Dare views illustrating a high speed program (HSP) method among various program methods according to embodiments of the inventive concept.

Referring toFIG.7A, a memory block BLK_1may include a plurality of memory cells MC connected to first to third string selection lines SSL1to SSL3and first to third word lines WL1to WL3. According to an embodiment of the inventive concept, the memory device may perform a program sequence in accordance with address scrambles 1->2->3 . . . ->9 when first and second step program operations are performed on the plurality of memory cells MC connected to first to third word lines WL1to WL3. The memory device may sequentially perform a program operation on the memory cells connected to the same word line in a predetermined order. According to an embodiment of the inventive concept, the memory device may perform the program operation on the memory cells connected to the same word line in the order of the memory cell connected to the first string selection line SSL1, the memory cell connected to the second string selection line SSL2, and the memory cell connected to the third string selection line SSL3.

Referring toFIG.7B, a memory block BLK_1may include a plurality of memory cells MC connected to first to third string selection lines SSL1to SSL3and first to third word lines WL1to WL3. According to an embodiment of the inventive concept, the memory device may perform a program sequence in accordance with address scrambles 1->2->3 . . . ->6 when first and second step program operations are performed on the plurality of memory cells MC connected to first to third word lines WL1to WL3based on a shadow program method.

Hereinafter, inFIGS.7C and7D, for convenience sake, in a current program operation, it is assumed that a selected word line is a first word line and an unselected word line is a second word line. Reference numerals are used for distinguishing the word lines from each other and do not mean physical positions of the word lines.

For convenience sake, it is assumed that a previous page PDp is stored in the first word line. For example, before a program operation is performed on the first word line, a program operation may be performed on a 0thword line. In the program operation performed on the 0thword line, the 0thword line may be a selected word line, the first word line may be an unselected word line, and at least one (for example, PDp) of a plurality of pages corresponding to the 0thword line may be non-selection programmed to the first word line. In other words, at a point in time at which the program operation starts to be performed on the first word line, the previous page PDp programmed in the previous non-selection program operation may be stored in the first word line.

Referring toFIGS.7C and7D, the memory device may receive first, second, and third pages PD11, PD12, and PD13corresponding to the first word line. According to an embodiment of the inventive concept, the first, second, and third pages PD11, PD12, and PD13may be stored in a page buffer of the memory device.

The memory device may program one (for example, the third page PD13) of the first, second, and third pages PD11, PD12, and PD13corresponding to the first word line to the second word line that is the unselected word line. In other words, the memory device may perform a non-selection program operation PGM_unsel on the second word line.

For example, as illustrated inFIG.7D, the memory device may perform the non-selection program operation PGM_unsel on the second word line so that each of the memory cells connected to the second word line is in one of an erase state E and a non-selection program state P01. According to an embodiment of the inventive concept, in the non-selection program operation PGM_unsel, in order to verify the non-selection program state P01, a non-selection verification voltage VF01may be used. When the non-selection program operation PGM_unsel is performed on the second word line, the third page PD13corresponding to the first word line is stored in the second word line and the previous page PDp is stored in the first word line.

According to an embodiment of the inventive concept, when the number of pages corresponding to a selected word line is n (n is a positive integer) and the non-selection program operation PGM_unsel is performed on the unselected word line, memory cells connected to the unselected word line may form threshold voltage distributions in a number less than 2n.

Then, the memory device may read the previous page PDp by performing a previous page read operation RD_pre on the first word line. For example, as illustrated inFIG.7D, each of the memory cells of the first word line in which the previous page PDp is stored may be in one of the erase state E and the non-selection program state P01. The memory device may read the previous page PDp by performing the previous page read operation RD_pre by using a read voltage VRD01.

According to an embodiment of the inventive concept, the previous page PDp read by the previous page read operation RD_pre may be stored in a specific latch of the page buffer. The specific latch may indicate a data latch in which the programmed page (e.g., the third page PD13) is stored in the unselected word line. In other words, after the previous page read operation RD_pre is performed, the page buffer of the memory device may store the first and second pages PD11and PD12corresponding to the first word line and the previous page PDp corresponding to the other word line.

Then, the memory device may perform a selection program operation PGM_sel on the first word line based on the first and second pages PD11and PD12and the previous page PDp. For example, as described above, after the previous page read operation RD_pre is performed, the page buffer of the memory device may store the first and second pages PD11and PD12and the previous page PDp. The memory device may perform the selection program operation PGM_sel on the first word line based on the first and second pages PD11and PD12and the previous page PDp stored in the page buffer.

By performing the selection program operation PGM_sel, memory cells in the erase state E among the memory cells of the first word line may be in one of the erase state E and first to third program states P1to P3and memory cells in the non-selection program state P01may be in one of fourth to seventh program states P4to P7. In the selection program operation PGM_sel, in order to verify the first to seventh program states P1to P7, first to seventh verification voltages VF1to VF7may be used. Such a program operation may be referred to as a 2-8 HSP method, and the inventive concept may be applied during the above program operation, which is an example embodiment. The inventive concept is not limited thereto and may also be applied a 4-8 HSP method.

When the selection program operation PGM_sel is performed on the first word line, the first word line may store the previous page PDp and the first and second pages PD11and PD12corresponding to the first word line and the second word line may store the third page PD13corresponding to the first word line.

Because the embodiment ofFIGS.7A to7Dis an example, the inventive concept is not limited thereto and may also be applied to a sun-who program method.

FIG.8is a flowchart illustrating a method of generating and storing offset information according to an embodiment of the inventive concept. For example, the memory device may be connected to an external test device and may generate offset information under control of the external test device. In another example, the memory device may generate offset information through an internal built-in self-test (BIST) circuit. Hereinafter, an embodiment in which the offset information is generated by the memory device will be mainly described. However, the inventive concept is not limited thereto, and the offset information according to the inventive concept may be generated in various methods to include a plurality of offsets considering characteristics by threshold voltage distributions for the memory cells of the memory device.

Referring toFIG.8, in operation S210, the memory device may perform first and second step program operations in a kth (k is an integer of no less than 1) program method. In operation S220, the memory device may measure movement distances in accordance with the second step program operation of a plurality of target threshold voltage distributions respectively corresponding to a plurality of program states. For example, the memory device may determine distribution speeds of the plurality of target threshold voltage distributions by measuring the movement distances from a plurality of approximate threshold voltage distributions formed in the first step program operation to the plurality of target threshold voltage distributions in the second step program operation. In operation S230, the memory device may determine an offset between a coarse verification voltage and a fine verification voltage by target threshold voltage distributions based on the measurement result of operation S220. For example, the memory device may determine a first offset between a coarse verification voltage and a fine verification voltage used for forming a first target threshold voltage distribution corresponding to a first program state and a second offset between a coarse verification voltage and a fine verification voltage used for forming a second target threshold voltage distribution corresponding to a second program state. The first offset may be different from the second offset. In operation S240, the memory device may determine whether ‘k’ is equal to ‘n’ when the number of supportable program methods is n (n is an integer of no less than 1) and may check whether offsets corresponding to all the supportable program methods are generated. When it is determined in operation S240that ‘k’ is not equal to ‘n’, operation S250is subsequently performed so that the memory device may count up to ‘k’ and operation S210may be subsequently performed. When it is determined in operation S240that ‘k’ is equal to the memory device may store offset information including offsets respectively corresponding to a plurality of program methods in a predetermined region in the memory device.

FIGS.9A and9Bare table diagrams illustrating offset information according to an embodiment of the inventive concept.

Referring toFIG.9A, a first table Table_1as an implementation example of the offset information may include first to nth offset data items OS_DATA1to OS_DATAn respectively corresponding to first to nth program methods M1to Mn. In some embodiments of the inventive concept, the memory device may support a limited number of program methods. In this case, the offset information of the memory device may include only offset data corresponding to a supportable program method. For example, the first program method M1may correspond to a quadruple level cell QLC in a cell type and an ‘8-16’ shadow program method. On the other hand, each of the first to nth offset data items OS_DATA1to OS_DATAn may include offsets applied to a plurality of threshold voltage distributions, as described in detail inFIG.9B.

Referring toFIG.9B, a second table Table_2as an implementation example of the first offset data OS_DATA1of the first table Table_1ofFIG.9Amay include first to fifteenth offsets OS1to OS15for forming first to fifteenth target threshold voltage distributions P1to P15respectively corresponding to first to fifteenth program states. For example, the memory device may perform a second step program operation by using a coarse verification voltage and a fine verification voltage having the first offset OS1to form the first target threshold voltage distribution P1. In addition, the memory device may perform the second step program operation by using a coarse verification voltage and a fine verification voltage having the second offset OS2to form the second target threshold voltage distribution P2. Further, the memory device may perform the second step program operation by using a coarse verification voltage and a fine verification voltage having the fifteenth offset OS15to form the fifteenth target threshold voltage distribution P15.

FIGS.10A to10Fare views illustrating a second step program operation using an offset according to an embodiment of the inventive concept. InFIGS.10A to10F, description is given based on an embodiment in which the offset is implemented by a length difference between a develop interval using a coarse verification voltage and a develop interval using a fine verification voltage. Hereinafter, a description is given based on the second step program operation for forming first and second target threshold voltage distributions and it is premised that the second target threshold voltage distribution corresponds to higher program state than the first target threshold voltage distribution, the second target threshold voltage distribution has a distribution speed greater than that of the first target threshold voltage distribution, and a second offset corresponding to the second target threshold voltage distribution is greater than a first offset corresponding to the first target threshold voltage distribution.

Referring toFIG.10A, levels of the coarse verification voltage V_c1and the fine verification voltage V_f1for forming the first target threshold voltage distribution may be the same as each other as a first level or similar to each other. Levels of the coarse verification voltage V_c2and the fine verification voltage V_f2for forming the second target threshold voltage distribution may be the same as each other as a second level or similar to each other. The second level may be higher than the first level.FIG.10Ais merely an example embodiment. The inventive concept is not limited thereto, and the coarse verification voltages V_c1and V_c2and the fine verification voltages V_f1and V_f2may be implemented to have various levels conforming to the second step program operation.

Referring toFIG.10B, a memory device200may include a memory cell array210and a page buffer circuit220. The memory cell array210and the page buffer circuit220illustrated inFIG.2may be an example of the memory cell array110and the page buffer circuit120illustrated inFIG.1.

The memory cell array210may include a plurality of string selection transistors SST1to SSTq, a plurality of memory cells MC1qto MCpq, and a plurality of ground selection transistors GST1to GSTq. The plurality of memory cells MC1qto MCpq may be connected between the plurality of string selection transistors SST1to SSTq and the plurality of ground selection transistors GST1to GSTq, and control gates of the plurality of memory cells MC1qto MCpq may be respectively connected to a plurality of word lines WL1to WLp.

Drains of the plurality of string selection transistors SST1to SSTq may be respectively connected to a plurality of bit lines BL1to BLq, and gates of the plurality of string selection transistors SST1to SSTq may be connected to a plurality of string selection lines SSL. In addition, sources of the plurality of ground selection transistors GST1to GSTq may be connected to a common source line CSL and gates of the plurality of ground selection transistors GST1to GSTq may be connected to a ground selection line GSL. One string selection transistor SST1, one ground selection transistor GST1, and the plurality of memory cells MC1qto MCpq connected between the string selection transistor SST1and the ground selection transistor GST1may be referred to as one string.

The page buffer circuit220may include a plurality of page buffers221_1to221_q respectively corresponding to the plurality of bit lines BL1to BLq. The plurality of page buffers221_1to221_q may include a plurality of bit line connection units223_1to223_q, a plurality of precharge units225_1to225_q, and a plurality of data latch units227_1to227_q. The plurality of precharge units225_1to225_q may be connected to a sensing node SN and may precharge the sensing node SN in response to a precharge control signal in a precharge interval by a predetermined voltage. The plurality of data latch units227_1to227_q may read data of a selected memory cell by sensing a voltage level of the sensing node SN or may output data received from the outside to the plurality of bit line connection units223_1to223_q through the sensing node SN.

Referring toFIG.10C, the memory device200may precharge the sensing node SN by a predetermined voltage VPRE in a precharge interval T1_1abetween a first time t1aand a second time t2awhen a coarse verification operation for forming the first target threshold voltage distribution is performed. Then, in a first develop interval T1_2abetween the second time t2aand a third time t3a, the coarse verification voltage V_c1is applied to the plurality of word lines WL1to WLp so that a voltage of the sensing node SN may be maintained when a threshold voltage of the selected memory cell is greater than the coarse verification voltage V_c1and may be reduced when the threshold voltage of the selected memory cell is less than the coarse verification voltage V_c1. After the first develop interval T1_2a, the selected memory cell passes the coarse verification operation when the voltage of the sensing node SN is no less than a reference voltage VREF and fails the coarse verification operation when the voltage of the sensing node SN is less than the reference voltage VREF. In other words, when the voltage of the sensing node SN is greater than the reference voltage VREF, the selected memory cell pass the coarse verification operation, and when the voltage of the sensing node SN is less than the reference voltage VREF, the selected memory cell fails the coarse verification such that a program loop may be repeatedly performed on the selected memory cell. For example, the selected memory cell may pass the coarse verification operation in a first case and may fail the coarse verification operation in a second case causing the program loop to repeat.

Referring toFIG.10D, the memory device200may precharge the sensing node SN by the predetermined voltage VPRE in a precharge interval between a fourth time t1band a fifth time t2bwhen a fine verification operation for forming the first target threshold voltage distribution is performed. Then, in a second develop interval T2_1bbetween the fifth time t2band a sixth time t3b, the fine verification voltage V_f1is applied to the plurality of word lines WL1to WLp so that the voltage of the sensing node SN may be maintained when the threshold voltage of the selected memory cell is greater than the fine verification voltage V_f1and may be reduced when the threshold voltage of the selected memory cell is less than the fine verification voltage V_f1. After the second develop interval T1_2b, the selected memory cell passes the fine verification operation when the voltage of the sensing node SN is no less than the reference voltage VREF and fails the fine verification operation when the voltage of the sensing node SN is less than the reference voltage VREF so that a program loop may be repeatedly performed on the selected memory cell. For example, the selected memory cell may pass the fine verification operation in a first case and may fail the fine verification operation in a second case. According to an embodiment of the inventive concept, a first length difference tdiff1may exist between the first develop interval T1_2aand the second develop interval T1_2bfor forming the first target threshold voltage distribution.

Referring toFIG.10E, the memory device200may precharge the sensing node SN by the predetermined voltage VPRE in a precharge interval T2_1abetween a seventh time t1cand an eighth time t2cwhen a coarse verification operation for forming the second target threshold voltage distribution is performed. Then, in a first develop interval T2_2abetween the eighth time t2cand a ninth time t3c, the coarse verification voltage V_c2is applied to the plurality of word lines WL1to WLp so that the voltage of the sensing node SN may be maintained when the threshold voltage of the selected memory cell is greater than the coarse verification voltage V_c2and may be reduced when the threshold voltage of the selected memory cell is less than the coarse verification voltage V_c2. After the first develop interval T2_2a, the selected memory cell passes the coarse verification operation when the voltage of the sensing node SN is no less than the reference voltage VREF and fails the coarse verification operation when the voltage of the sensing node SN is less than the reference voltage VREF so that a program loop may be repeatedly performed on the selected memory cell. For example, the selected memory cell may pass the coarse verification operation in a first case and may fail the coarse verification operation in a second case unlike inFIG.10C.

Referring toFIG.10F, the memory device200may precharge the sensing node SN by the predetermined voltage VPRE in a precharge interval T2_1bbetween a tenth time t1dand an eleventh time t2dwhen a fine verification operation for forming the second target threshold voltage distribution is performed. Then, in a second develop interval T2_2bbetween the eleventh time t2dand a twelfth time t3b, the fine verification voltage V_f2is applied to the plurality of word lines WL1to WLp so that the voltage of the sensing node SN may be maintained when the threshold voltage of the selected memory cell is greater than the fine verification voltage V_f2and may be reduced when the threshold voltage of the selected memory cell is less than the fine verification voltage V_f2. After the second develop interval T2_2b, the selected memory cell passes the fine verification operation when the voltage of the sensing node SN is no less than the reference voltage VREF and fails the fine verification operation when the voltage of the sensing node SN is less than the reference voltage VREF so that a program loop may be repeatedly performed on the selected memory cell. For example, the selected memory cell may pass the fine verification operation in a first case and may fail the fine verification operation in a second case. According to an embodiment of the inventive concept, a second length difference tdiff2may exist between the first develop interval T2_2aand the second develop interval T2_2bfor forming the second target threshold voltage distribution.

According to an embodiment of the inventive concept, the second length difference tdiff2may be greater than the first length difference tdiff1. In other words, the memory device may make the first develop interval T2_2ausing the coarse verification voltage V_c2shorter than the first develop interval T1_2ausing the coarse verification voltage V_c1considering that the second target threshold voltage distribution is faster than the first target threshold voltage distribution. Therefore, the memory device may increase the number of memory cells passing the coarse verification operation when the second target threshold voltage distribution is formed considering characteristics of the second target threshold voltage distribution.

The memory device according to an embodiment of the inventive concept may control the number of memory cells passing a coarse verification operation considering characteristics of a target threshold voltage distribution and, as a result, may improve data reliability and performance of the memory device by forming optimal target threshold voltage distributions.

FIGS.11A to11Care views illustrating a second step program operation using an offset according to an embodiment of the inventive concept. InFIGS.11A to11C, the description is given based on an embodiment in which the offset is implemented by a level difference between a coarse verification voltage and a fine verification voltage. Hereinafter, the description is given based on the second step program operation for forming first and second target threshold voltage distributions and it is premised that the second target threshold voltage distribution corresponds to a higher program state than the first target threshold voltage distribution, the second target threshold voltage distribution has a distribution speed greater than that of the first target threshold voltage distribution, and a second offset corresponding to the second target threshold voltage distribution is greater than a first offset corresponding to the first target threshold voltage distribution.

Referring toFIG.11A, the coarse verification voltage V_c1for forming the first target threshold voltage distribution is at a first level and the fine verification voltage V_f1may be at a second level. The second level may be greater than the first level. The level difference between the coarse verification voltage V_c1and the fine verification voltage V_f1may correspond to a first level difference Ldiff1. The coarse verification voltage V_c2for forming the second target threshold voltage distribution may be at a third level and the fine verification voltage V_f2may be at a fourth level. The fourth level may be greater than the third level. The level difference between the coarse verification voltage V_c2and the fine verification voltage V_f2may correspond to a second level difference Ldiff2. The second level difference Ldiff2may be greater than the first level difference Ldiff1.FIG.11Ais an example embodiment. The inventive concept is not limited thereto, and the coarse verification voltages V_c1and V_c2and the fine verification voltages V_f1and V_f2may be implemented to have various levels conforming to the second step program operation.

Referring toFIGS.10B and11B, the memory device200may precharge the sensing node SN by the predetermined voltage VPRE in a precharge interval T1abetween a first time t1cand a second time t2ewhen a coarse verification operation for forming the first target threshold voltage distribution is performed. Then, in a first develop interval T2abetween the second time t2eand a third time t3e, the coarse verification voltage V_c1may be applied to the plurality of word lines WL1to WLp.

Referring toFIGS.10B and11C, the memory device200may precharge the sensing node SN by the predetermined voltage VPRE in a precharge interval T1bbetween a fourth time t1fand a fifth time t2fwhen a fine verification operation for forming the first target threshold voltage distribution is performed. Then, in a second develop interval T2bbetween the fifth time t2fand a sixth time t3f, the fine verification voltage V_f1may be applied to the plurality of word lines WL1to WLp. According to an embodiment of the inventive concept, a predetermined length difference tdiff may exist between the first develop interval T2aand the second develop interval T2bfor forming the first target threshold voltage distribution and a length difference between the first develop interval and the second develop interval for forming the second target threshold voltage distribution may correspond to the predetermined length difference tdiff. In other words, the predetermined length difference tdiff between the first develop interval T2aand the second develop interval T2bfor forming the first target threshold voltage distribution and the length difference between the first develop interval and the second develop interval for forming the second target threshold voltage distribution may be the same.

On the other hand, in some embodiments of the inventive concept, the memory device may control the level difference between the coarse verification voltage and the fine verification voltage and the length difference between the first develop interval using the coarse verification voltage and the second develop interval using the fine verification voltage to vary by target threshold voltage distributions. In other words, the embodiment described with reference toFIGS.10A to10Fmay be combined with the embodiment illustrated described with reference toFIGS.11A to11Cso that the combination may be implemented by the memory device.

FIG.12Ais a block diagram illustrating an implementation example of a memory device200aperforming a second step program operation according to an embodiment of the inventive concept andFIG.12Bis a block diagram illustrating the electronic fuse circuit260aofFIG.12A. Hereinafter, for convenience sake, the description previously given for overlapping elements with reference toFIG.1may be omitted. The memory device200aofFIG.12Amay perform the operation described with reference toFIGS.10A to10F.

Referring toFIG.12A, the memory device200amay further include the electronic fuse circuit260ain comparison with the memory device100ofFIG.1. The electronic fuse circuit260amay include first to nth fuse cell regions262a_1to262a_n. In each of the first to nth fuse cell regions262a_1to262a_n, offset information conforming a corresponding program method may be stored. For example, in the first fuse cell region262a_1, offset information conforming to a first program method may be stored. In accordance with the number of program methods that may be supported by the memory device200a, the number of fuse cell regions included in the electronic fuse circuit260amay vary.

According to an embodiment of the inventive concept, a coarse-fine verification control module232amay generate a fuse address F_ADD based on a program method applied to the second step program operation and may provide the fuse address F_ADD to the electronic fuse circuit260a. One of the first to nth fuse cell regions262a_1to262a_n may be activated in response to the fuse address F_ADD and a develop control signal. DT_CS for controlling a develop interval of the second step program operation may be generated. The electronic fuse circuit260amay provide the develop control signal DT_CS to the page buffer circuit220aand may control connection of a sensing node so that a length difference between a coarse verification interval and a fine verification interval varies in accordance with characteristics by target threshold voltage distributions. In addition, a control logic230amay provide a voltage control signal CS_vol_a to a voltage generator240aso that the voltage generator240agenerates a coarse verification voltage V_c and a fine verification voltage V_f conforming a coarse verification operation and a fine verification operation using the electronic fuse circuit260a. Hereinafter, inFIG.12B, a detailed description of the first fuse cell region262a_1included in the electronic fuse circuit260ais described assuming that the program method corresponding to the first fuse cell region262a_1is a quadruple level cell.

Referring toFIG.12B, the electronic fuse circuit260amay include a control circuit264aand the first fuse cell region262a_1. The first fuse cell region262a_1may include first to fifteenth fuse cells262a_1to262a_115. In the first to fifteenth fuse cells262a_11to262a_115, offsets for forming first to fifteenth target threshold voltage distributions may be respectively stored. For example, a first offset for forming the first target threshold voltage distribution may be stored in the first fuse cells262a_1and a second offset for forming the second target threshold voltage distribution may be stored in the second fuse cells262a_11. The control circuit264amay generate an enable signal EN for selectively activating one of the first to fifteenth fuse cells262a_11to262a_115in response to the fuse address F_ADD. When the first to fifteenth fuse cells262a_11to262a_115are activated, the first to fifteenth fuse cells262a_11to262a_115may respectively output first to fifteenth develop control signals DT_CS1to DT_CS15.

Control of the develop interval using the electronic fuse circuit260aillustrated inFIGS.12A and12Bis merely an example. The inventive concept is not limited thereto and various embodiments for controlling the develop interval may be applied to the memory device200a.

FIG.13is a block diagram illustrating another implementation example of a memory device200bperforming a second step program operation according to an embodiment of the inventive concept. Hereinafter, for convenience sake, the description previously given for overlapping elements with reference toFIG.1may be omitted. The memory device200bofFIG.13may perform the operation described with reference toFIGS.11A to11C.

Referring toFIG.13, a memory cell array210bmay include a redundant cell region212b. In the redundant cell region212b, offset information according to embodiments of the inventive concept may be stored. A control logic230bmay receive offset information OS_I from the redundant cell region212bthrough a page buffer circuit220b. The control logic230bmay generate a voltage control signal CS_vol_b based on the offset information OS_I. A voltage generator240bmay generate the coarse verification voltage V_c and the fine verification voltage V_f having a level difference in accordance with characteristics by target threshold voltage distributions in response to the voltage control signal CS_vol_b.

FIG.14is a flowchart illustrating a method of operating a memory device, according to an embodiment of the inventive concept.

Referring toFIG.14, in operation S200, the memory device may perform a first step program operation. In operation S220, the memory device may perform a second step program operation by using a coarse verification voltage and a fine verification voltage conforming to characteristics by target threshold voltage distributions considering an operation condition thereof. The operation condition of the memory device may include a temperature condition, an interference condition, a noise condition, and a program/erase (P/E) cycle condition under which the memory device currently performs a memory operation. Memory cell characteristics may change in accordance with the operation condition of the memory device so that characteristics of the above-described target threshold voltage distributions may change. According to an embodiment of the inventive concept, the memory device updates offset information to be adaptive to a change in characteristics of current target threshold voltage distributions based on the operation condition thereof and may perform the second step program operation based on the updated offset information.

FIG.15is a flowchart illustrating a method of operating a memory system, according to an embodiment of the inventive concept.

Referring toFIG.15, the memory system may include a memory controller310and a memory device320. The memory controller310may periodically or non-periodically monitor an operation condition of the memory device320, may generate operation condition information based on the monitoring result, and may update the operation condition information. In operation S300, the memory controller310may transmit the operation condition information to the memory device320. In operation S310, the memory device320may update offset information based on the operation condition information. In operation S320, the memory controller310may transmit a program command to the memory device320. In operation S330, the memory device320may perform a program operation including the first and second step program operations using the updated offset information in response to the program command.

FIG.16is a flowchart illustrating an operation of a memory device updating offset information based on P/E cycle information in operation S310ofFIG.15.FIGS.17A and17Bare views illustrating an operation of updating offset information in accordance with a P/E cycle of a memory device.

Referring toFIG.16, in operation S311, the memory device may receive the P/E cycle information representing the P/E cycle thereof from a memory controller. In some embodiments of the inventive concept, the memory device may directly manage the P/E cycle information. At this time, the P/E cycle information stored in the memory device may be read. In operation S312, the memory device may determine whether the P/E cycle exceeds a threshold value. When it is determined in operation S312that the P/E cycle does not exceed the threshold value, operation. S311may be subsequently performed. When it is determined in operation S312that the P/E cycle exceeds the threshold value, operation S313may be subsequently performed so that the memory device may update the offset information.

Referring toFIG.17A, memory cells of the memory device may have a first threshold voltage distribution D1when the memory device reaches a first P/E cycle P/E Cycle1and may have a second threshold voltage distribution D2when the memory device reaches a second P/E cycle P/E Cycle2. As illustrated inFIG.17A, as the P/E cycle increases, a cell speed of the memory cells of the memory device may increase; however, this is merely an example. In some embodiments of the inventive concept, as the P/E cycle increases, the cell speed of the memory cells of the memory device may be reduced.

Referring toFIG.17B, it is assumed that the first offset os11between the coarse verification voltage V_c11and the fine verification voltage V_f11for forming the first target threshold voltage distribution P1from the first approximate threshold voltage distribution P1_1and the second offset os12between the coarse verification voltage V_c12and the fine verification voltage V_f12for forming the second target threshold voltage distribution P2from the first approximate threshold voltage distribution P1_1inFIG.6Amay be used under a condition of the first P/E cycle P/E Cycle1. Under a condition of the second P/E cycle P/E Cycle2, the memory device updates the first and second offsets os11and os12to be greater than previous ones and may form the first and second target threshold voltage distributions P1and P2by using updated first and second offsets os11′ and os12′.FIG.17Bis merely an example embodiment. The inventive concept is not limited thereto and the offsets may be updated in various methods. As described above, the memory device may form optimal target threshold voltage distributions during a program operation by updating offset information in accordance with a change in characteristics of a memory cell.

FIG.18is a block diagram illustrating a memory system400according to an embodiment of the inventive concept. Hereinafter, the description previously given for overlapping elements with reference toFIG.1may be omitted.

Referring toFIG.18, the memory system400may include a memory controller410and a memory device420. The memory controller410may control the memory device420to read data items stored in the memory device420or to write data in the memory device420in response to a write/read request from a host. For example, the memory controller410may control a program or write, read, and erase operations for the memory device420by providing a command CMD, an address ADD, and a control signal CTRL to the memory device420. In addition, data DATA to be written and read data DATA may be transmitted and received between the memory controller410and the memory device420. The memory device420may include a memory cell array421and a control logic423.

According to an embodiment of the inventive concept, the memory controller410may include a coarse-fine verification control module412and the coarse-fine verification control module412may control the second step program operation of the memory device420considering characteristics by target threshold voltage distributions. Embodiments of the inventive concept described with reference toFIGS.1to17Bmay be applied to the coarse-fine verification control module412.

FIG.19is a block diagram illustrating a solid state drive (SSD) system430according to an embodiment of the inventive concept.

Referring toFIG.19, the SSD system430may include a host431and an SSD432. The SSD432may transmit and receive a signal to and from the host431through a signal connector and may receive power through a power connector. The SSD432may include an SSD controller433, an auxiliary power supply434, and first to sth memory devices435_1to435_s. The embodiments described with reference toFIGS.1to18may be applied to the first to sth memory devices435_1to435_s. The first to sth memory devices435_1to435_s may respectively store first to sth offset information items OS_Info.1˜OS_Info.s.s). The first to sth memory devices435_1to435_s may perform the second step program operation by using the first to sth offset information items OS_Info.1˜OS_Info.s.s). The host431and SSD432may communicate with each other via signal lines SGL and the host431may provide power to the SSD via power line PWR. The first to sth memory devices435_1to435_s may be coupled to the SSD controller433via a plurality of channels Ch1to CHs.FIG.20is a view illustrating a chip to chip (C2C) structure applied to a memory device1000according to an exemplary embodiment of the inventive concept. The memory device1000is an implementation of the memory device100ofFIG.1.

Referring toFIG.20, the memory device1000may have a chip to chip (C2C) structure. In the C2C structure, after manufacturing an upper chip including a cell area CELL on a first wafer and manufacturing a lower chip including a peripheral circuit area PERI on a second wafer different from the first wafer, the upper chip and the lower chip are connected to each other in a bonding method. For example, in the bonding method, a bonding metal formed in the uppermost metal layer of the upper chip is electrically connected to a bonding metal formed in the uppermost metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding method may be a Cu—Cu bonding method and the bonding metal may include aluminum (Al) or tungsten (W).

Each of the peripheral circuit area PERI and the cell area CELL of the memory device1000may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit area PERI may include a first substrate510, an interlayer insulating layer515, a plurality of circuit elements520a,520b, and520cformed on the first substrate510, first metal layers530a,530b, and530crespectively connected to the plurality of circuit elements520a,520b, and520c, and second metal layers540a,540b, and540cformed on the first metal layers530a,530b, and530c. In an embodiment of the inventive concept, the first metal layers530a,530b, and530cmay include W having high resistance and the second metal layers540a,540b, and540cmay include Cu having low resistance.

InFIG.20, only the first metal layers530a,530b, and530cand the second metal layers540a,540b, and540care illustrated and described. However, the inventive concept is not limited thereto, and at least one metal layer may be further formed on the second metal layers540a,540b, and540c. At least a part of the at least one metal layer formed on the second metal layers540a,540b, and540cmay include AI having lower resistance than Cu that the second metal layers540a,540b, and540cinclude.

The interlayer insulating layer515may be arranged on the first substrate510to cover the plurality of circuit elements520a,520b, and520c, the first metal layers530a,530b, and530c, and the second metal layers540a,540b, and540cand may include an insulating material such as silicon oxide or silicon nitride

Lower bonding metals571band572bmay be formed on the second metal layer540bof the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals571band572bof the peripheral circuit area PERI may be electrically connected to upper bonding metals671band672bof the cell area CELL in a bonding method and the lower bonding metals571band572band the upper bonding metals671band672bmay include Al, Cu, or W.

The cell area CELL may provide at least one memory block. The cell area CELL may include a second substrate610and a common source line620. A plurality of word lines631to638(630) may be stacked on the second substrate610in a direction (a Z axis direction) perpendicular to an upper surface of the second substrate610. String selection lines may be arranged on the plurality of word lines631to638and a ground selection line may be arranged under the plurality of word lines631to638and the plurality of word lines631to638may be arranged between the string selection lines and the ground selection line.

In the bit line bonding area BLBA, a channel structure CH may extend in the direction perpendicular to the upper surface of the second substrate610and may pass through the plurality of word lines631to638, the string selection lines, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulation layer and the channel layer may be electrically connected to a first metal layer650cand a second metal layer660c. For example, the first metal layer650cmay be a bit line contact and the second metal layer660cmay be a bit line. In an embodiment of the inventive concept, the second metal layer660cmay extend in a first direction (a Y direction) parallel with the upper surface of the second substrate610.

In the embodiment illustrated inFIG.20, an area in which the channel structure CH and the second metal layer660care arranged may be referred to as the bit line bonding area BLBA. The second metal layer660cin the bit line bonding area BLBA may be electrically connected to circuit elements520cincluded in a page buffer693in the peripheral circuit area PERI. For example, the second metal layer660cmay be connected to upper bonding metals671cand672cin the peripheral circuit area PERI and the upper bonding metals671cand672cmay be connected to lower bonding metals571cand572cconnected to the circuit elements520cof the page buffer693.

In the word line bonding area WLBA, the plurality of word lines631to638may extend in a second direction (an X axis direction) parallel with the upper surface of the second substrate610and may be connected to a plurality of cell contact plugs641to647(640). The plurality of word lines631to638may be connected to the plurality of cell contact plugs641to647in pads in which at least some of the plurality of word lines631to638extend with different lengths. A first metal layer650band a second metal layer660bmay be sequentially connected onto the plurality of cell contact plugs641to647connected to the plurality of word lines631to638. The plurality of cell contact plugs641to647may be connected to the peripheral circuit area PERI through the upper bonding metals671band672bof the cell area CELL and the lower bonding metals571band572bof the peripheral circuit area PERI in the word line bonding area WLBA.

The plurality of cell contact plugs641to647may be electrically connected to the circuit elements520bincluded in a row decoder694in the peripheral circuit area PERI. In an embodiment of the inventive concept, an operation voltage of the circuit elements520bincluded in the row decoder694may be different from an operation voltage of the circuit elements520cincluded in the page buffer693. For example, the operation voltage of the circuit elements520cincluded in the page buffer693may be greater than the operation voltage of the circuit elements520bincluded in the row decoder694.

In an external pad bonding area PA, a common source line contact plug680may be arranged. The common source line contact plug680may include a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to the common source line620. On the common source line contact plug680, a first metal layer650aand a second metal layer660amay be sequentially stacked. For example, an area in which the common source line contact plug680, the first metal layer650a, and the second metal layer660aare arranged may be referred to as the external pad bonding area PA.

In addition, first and second input and output pads505and605may be arranged in the external pad bonding area PA. A lower insulating layer501covering a lower surface of the first substrate510may be formed under the first substrate510and the first input and output pad505may be formed on the lower insulating layer501. The first input and output pad505may be connected to at least one of the plurality of circuit elements520a,520b, and520carranged in the peripheral circuit area PERI through a first input and output contact plug503and may be separated from the first substrate510by the lower insulating layer501. In addition, between the first input and output contact plug503and the first substrate510, a side insulating layer may be arranged to electrically isolate the first input and output contact plug503from the first substrate510.

An upper insulating layer601covering the upper surface of the second substrate610may be formed on the second substrate610and a second input and output pad605may be arranged on the upper insulating layer601. The second input and output pad605may be connected to at least one of the plurality of circuit elements520a,520b, and520carranged in the peripheral circuit area PERI through a second input and output contact plug603.

According to embodiments of the inventive concept, in an area in which the second input and output contact plug603is arranged, the second substrate610and the common source line620may not be arranged. In addition, the second input and output pad605may not overlap the plurality of word lines631to638in a third direction (the Z axis direction). The plurality of word lines631to638may be separated from the second substrate610in a direction parallel with the upper substrate of the second substrate610and may be connected to the second input and output pad605through an interlayer insulating layer615of the cell area CELL.

According to embodiments of the inventive concept, the first input and output pad505and the second input and output pad605may be selectively formed. For example, the memory device1000may include only the first input and output pad505arranged on the first substrate501or the second input and output pad605arranged on the second substrate601. Alternatively, the memory device1000may include both the first input and output pad505and the second input and output pad605.

In the external pad bonding area PA and the bit line bonding area BLBA respectively included in the cell area CELL and the peripheral circuit area PERI, a metal pattern of the uppermost metal layer is provided as a dummy pattern or the uppermost metal layer may be empty.

In the external pad bonding area PA of the memory device1000, to correspond to an upper metal pattern672aformed in the uppermost metal layer of the cell area CELL, a lower metal pattern573ain the same form as the upper metal pattern672aof the cell area CELL may be formed in the uppermost metal layer of the peripheral circuit area PERI. The lower metal pattern573aformed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to an additional contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, to correspond to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit area PERI, an upper metal pattern in the same form as the lower metal pattern of the peripheral circuit area PERI may be formed in the upper metal layer of the cell area CELL.

On the second metal layer540bof the word line bonding area WLBA, the lower bonding metals571band572bmay be formed. In the word line bonding area WLBA, the lower bonding metals571band572bof the peripheral circuit area PERI may be electrically connected to the upper bonding metals671band672bof the cell area CELL.

In addition, in the bit line bonding area BLBA, to correspond to a lower metal pattern552formed in the uppermost metal layer of the peripheral circuit area PERI, an upper metal pattern692in the same form as the lower metal pattern552of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL. On the upper metal pattern692formed in the uppermost metal layer of the cell area CELL, a contact may not be formed.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.