Patent ID: 12255196

DESCRIPTION OF THE EMBODIMENTS

The following disclosure provides many different embodiments or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

Embodiments of the present disclosure describe the exemplary manufacturing process of package structures and the package structures fabricated there-from. Certain embodiments of the present disclosure are related to the package structures formed with a heat dissipating structure. The wafers or dies may include one or more types of integrated circuits or electrical components on a bulk semiconductor substrate or a silicon/germanium-on-insulator substrate. The embodiments are intended to provide further explanations but are not to be used to limit the scope of the present disclosure.

FIG.1AthroughFIG.1Lshow schematic cross-sectional views illustrating structures produced at various stages of a manufacturing method of a semiconductor package10shown inFIG.1L. Referring toFIG.1A, a temporary carrier TC having a de-bonding layer DB formed thereon is provided. In some embodiments, the temporary carrier TC is a glass substrate, a metal plate, a plastic supporting board or the like, but other suitable substrate materials may be used as long as the materials are able to withstand the subsequent steps of the process. In some embodiments, the de-bonding layer DB includes a light-to-heat conversion (LTHC) release layer, which facilitates peeling the temporary carrier TC away from the semiconductor package when required by the manufacturing process.

In some embodiments, referring toFIG.1A, a redistribution structure100is formed over the carrier TC. In some embodiments, the redistribution structure100is formed on and temporarily attached with the de-bonding layer DB. In some embodiments, the redistribution structure100includes at least one dielectric layer110and at least one redistribution conductive layer120. The redistribution conductive layer120may be constituted by a plurality of redistribution conductive patterns. For simplicity, the dielectric layer110is illustrated as one single layer of dielectric layer and the redistribution conductive layer120is illustrated as embedded in the dielectric layer110inFIG.1A. Nevertheless, from the perspective of the manufacturing process, the dielectric layer110is constituted by at least two dielectric layers and the redistribution conductive layer112is sandwiched between two adjacent dielectric layers. In some embodiments, a material of the redistribution conductive layer120includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. The redistribution conductive layer120may be formed by, for example, electroplating, deposition, and/or photolithography and etching. In some embodiments, the material of the dielectric layer110includes polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable polymer-based dielectric material. The dielectric layer110, for example, may be formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. It should be noted that the number of the redistribution conductive layers120and the number of the dielectric layers110illustrated inFIG.1Aare merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, more layers of the redistribution conductive layer120and more layers of the dielectric layer110may be formed depending on the circuit design. When the redistribution structure100includes multiple redistribution conductive layers120and multiple dielectric layers110, these redistribution conductive layers120and these dielectric layers110are stacked alternately, and the redistribution conductive layers120may be interconnected with one another by conductive vias (not shown).

In some embodiments, the topmost dielectric layer110has a plurality of contact openings OP1formed therein, and the contact openings OP1expose portions of the redistribution conductive layer120. In some embodiments, a plurality of conductive structures200physically contacts the redistribution conductive layer120through the contact openings OP1to establish electrical connection. In some embodiments, the conductive structures200are conductive pillars formed on the redistribution conductive layer120by a photolithography process, a plating process, a photoresist stripping processes, and/or any other suitable processes. For example, a mask pattern (not shown) covering the redistribution structure100with openings exposing the contact openings OP1is formed. Thereafter, a metallic material (not shown) is filled into the openings and the contact openings OP1by electroplating or deposition. Then, the mask pattern is removed to obtain the conductive structures200. However, the disclosure is not limited thereto, and other suitable methods may be utilized in the formation of the conductive structures200. In some embodiments, the material of the conductive structures200includes a metal material such as copper, copper alloys, or the like. It should be noted that four conductive structures200are presented inFIG.1Afor illustrative purposes; however, more or fewer conductive structures200may be formed in some alternative embodiments. The number of the conductive structures200may be selected based on design and production requirements.

Referring toFIG.1B, a semiconductor die300is provided on the redistribution structure100. In some embodiments, the semiconductor die300is placed beside and between the conductive structures200. For example, the conductive structures200may be arranged to surround the semiconductor die300. In some embodiments, the semiconductor die300is placed onto the redistribution structure100through a pick-and-place method. Even though only one semiconductor die300is presented inFIG.1Afor illustrative purposes, it is understood that a plurality of semiconductor dies300are provided on the redistribution structure100for wafer-level packaging technology. In some embodiments, the semiconductor die300includes a semiconductor substrate310, a plurality of contact pads320and a passivation layer330. The contact pads320may be formed on a top surface310tof the semiconductor substrate310. The passivation layer330may cover the top surface310tand have a plurality of openings that exposes at least a portion of each contact pad320. In some embodiments, the semiconductor die300may further include a plurality of conductive posts340filling the openings of the passivation layer330and electrically connected to the contact pads320, and a protective layer350surrounding the conductive posts340. In some embodiments, as the semiconductor die300is placed on the redistribution structure100in a face-up configuration (active surface300aof the semiconductor die300facing upward inFIG.1B), the redistribution structure100is referred to as a back-side redistribution structure.

In some embodiments, the semiconductor substrate310may be made of semiconductor materials, such as semiconductor materials of the groups III-V of the periodic table. In some embodiments, the semiconductor substrate310includes elementary semiconductor materials such as silicon or germanium, compound semiconductor materials such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide or alloy semiconductor materials such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate310includes active components (e.g., transistors or the like) and optionally passive components (e.g., resistors, capacitors, inductors, or the like) formed therein. The semiconductor die300may be or include a logic die, such as a central processing unit (CPU) die, a graphic processing unit (GPU) die, a micro control unit (MCU) die, an input-output (I/O) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, the semiconductor die300includes a memory die such as a high bandwidth memory die. In certain embodiments, the contact pads320include aluminum pads, copper pads, or other suitable metal pads. In some embodiments, the passivation layer330may be a single layer or a multi-layered structure, including a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, a dielectric layer formed by other suitable dielectric materials or combinations thereof. In some embodiments, the material of the conductive posts340includes copper, copper alloys, or other conductive materials, and may be formed by deposition, plating, or other suitable techniques.

In some embodiments, the semiconductor die300has an active surface300aand a back surface300bopposite to the active surface300a. In some embodiments, as illustrated inFIG.1B, the semiconductor die300is attached to the redistribution structure100through an adhesive layer360. In other words, the back surface300bof the semiconductor die300is attached to the adhesive layer360. In some embodiments, the adhesive layer360may include a die attach film. In some embodiments, the semiconductor die300is disposed in a die attach region DAR of the redistribution structure100, whilst the conductive structure200are formed in a fan-out region FOR surrounding the die attach region DAR. In some embodiments, the conductive structures200are formed prior to the placement of the semiconductor die300.

Referring toFIG.1B, an encapsulation material400ais formed over the redistribution structure100above the carrier TC to at least encapsulate the semiconductor die(s)300and the conductive structures200. In some embodiments, not only the semiconductor die(s)300but also the conductive structures200are fully covered and not revealed by the encapsulation material400a. In some embodiments, the encapsulation material400amay be a molding compound, a molding underfill, a resin (such as an epoxy resin), or the like. In some embodiments, the encapsulation material400ais formed by an over-molding process. In some embodiments, the encapsulation material400ais formed by a compression molding process.

Referring toFIG.1BandFIG.1C, in some embodiments, the encapsulation material400ais partially removed by a planarization process until the conductive posts340of the semiconductor die(s)300are exposed. That is, the active surface300aof the semiconductor die300is exposed. In some embodiments, upper portions of the conductive structures200amay be removed during the planarization process. Planarization of the encapsulation material400amay produce an encapsulant400located over the redistribution structure100to surround the conductive structures200and the semiconductor dies300, but top surfaces200tof the conductive structures200and the active surface300aof the semiconductor die300are exposed from the encapsulant400. In some embodiments, the planarization of the encapsulation material400aincludes performing a mechanical grinding process and/or a chemical mechanical polishing (CMP) process. After the grinding process or the polishing process, the top surfaces200tof the conductive structures200may be substantially coplanar with a top surface400tof the encapsulant400.

As shown inFIG.1D, in some embodiments, a redistribution structure500is subsequently formed over the encapsulant400and formed above the conductive structures200and the semiconductor die(s)300. As shown inFIG.1D, the redistribution structure500includes one or more dielectric layers510, one or more conductive layers520, and a plurality of interconnecting vias530. The interconnecting vias530and the conductive layers520are embedded in the dielectric layers510. In some embodiments, the redistribution structure500facing the active surface300aof the semiconductor die300is referred to as a front-side redistribution structure. In some embodiments, the manufacturing process and the materials used to fabricate the front-side redistribution structure500are the same or similar to what previously described for the back-side redistribution structure100, and a detailed description thereof is omitted for the sake of brevity. It should be noted that the number of the conductive layers520and the number of the dielectric layers510may be adapted according to the design requirement, and do not constitute a limitation of the disclosure. In some alternative embodiments, more or fewer conductive layers520and more or fewer dielectric layers510may be formed depending on the circuit design.

Referring toFIG.1D, at least portions of the conductive vias530exposed from a bottom surface500bof the redistribution structure500are connected to the conductive structures200and to the semiconductor die300. In some embodiments, a plurality of connective terminals600is disposed on the topmost conductive layer520of the redistribution structure500, and the connective terminals600are electrically connected with the redistribution structure500. Furthermore, a plurality of under bump metallurgies (not shown) may be provided between the conductive terminals600and the topmost conductive layer520for better adhesion and connection reliability. In some embodiments, the connective terminals600include ball grid array (BGA) balls or solder balls. In some embodiments, the connective terminals600may be placed on the under-bump metallurgies through a ball placement process. With the formation of the connective terminals600, a bottom package structure BP is obtained. In some embodiments, the bottom package structure BP is in a form of a reconstructed wafer RW, and the reconstructed wafer RW includes a plurality of bottom package units BPU. InFIG.1D, only a single bottom package unit BPU is shown for simplicity. In other words, the exemplary processes may be performed at a reconstructed wafer level, so that multiple bottom package units BPU are processed in the form of the reconstructed wafer RW.

In some embodiments, the reconstructed wafer RW is overturned and placed onto a supporting frame SF, as shown inFIG.1E. Referring to both ofFIG.1DandFIG.1E, the de-bonding layer DB and the temporary carrier TC are detached from the reconstructed wafer RW and then removed. In some embodiments, the de-bonding layer DB (e.g., the LTHC release layer) is irradiated with a UV laser so that the carrier TC and the de-bonding layer DB are easily peeled off from the bottom package units BPU. Nevertheless, the de-bonding process is not limited thereto, and other suitable de-bonding methods may be used in some alternative embodiments.

The reconstructed wafer RW may be disposed on the supporting frame SF with the front-side redistribution structure500facing the supporting frame SF, and the back-side redistribution structure100may be exposed and available for further processing.

As shown inFIG.1F, a plurality of openings OP2may be formed in the now exposed dielectric layer110of the redistribution structure100, partially revealing the redistribution conductive layer120. In some embodiments, one or more top packages700A,700B are provided and disposed on the back-side redistribution structure100. In some embodiments, the top packages700A,700B are electrically connected with the bottom package unit BPU through the back-side redistribution structure100, the conductive structures200and the front-side redistribution structure500. In some embodiments, as shown inFIG.1F, two top packages700A,700B are connected to one bottom package unit BPU. It should be noted that the number of top packages connected to the bottom package units BPU is not limited to two according to the exemplary embodiments of the present disclosure. In some alternative embodiments, fewer or more than two top packages may be provided and connected to the bottom package unit BPU.

In some embodiments, the top package700A includes a first chip710A. The first chip710A has a plurality of contact pads715A and is electrically connected to a redistribution structure720A. In some embodiments, the top package700B includes a second chip710B having a plurality of contact pads715B electrically connected to a redistribution structure720B. In some embodiments, each of the chips710A,710B may be independently disposed in a face-up configuration, and electrical connection with the corresponding redistribution structure720A or720B may be established through a plurality of conductive wires730A or730B. In some embodiments, a material of the conductive wires730A or730B includes copper, gold, or alloy thereof. In some embodiments, a die attach film740A or740B is disposed between the chip710A or710B and the corresponding redistribution structure720A or720B. An encapsulant750A or750B may be disposed over the corresponding redistribution structure720A or720B to embed the chip710A or710B and the conductive wires730A or730B. In some embodiments, the top packages700A and700B are the same type packages and the chips710A and710B belongs to the same type of chips or perform the same or similar functions. In some embodiments, the top packages700A and700B are different types of packages and the chips710A and710B are different types of chips or perform different functions. In some embodiments, the chip710A or710B may be or include a memory die. In some alternative embodiments, the chip710A or710B may be or include a logic die. A plurality of conductive balls760may electrically connect the redistribution structures720A,720B of the top packages700A,700B and the back-side redistribution structure100. In some embodiments, the conductive balls760include BGA balls or solder bumps, and the top packages700A,700B are flip-chip bonded to the redistribution structure100of the bottom package unit BPU through the conductive balls760. In some embodiments, as shown inFIG.1F, the top packages700A and700B are arranged side by side with a gap G separating the two top packages700A,700B.

With reference toFIG.1G, an underfill800may be provided to fill the interstices between the top packages700A,700B and the back-side redistribution structure100. The underfill800may at least partially fill the gap G (seeFIG.1F) between the top packages700A,700B. The underfill800may help protect the conductive balls760against thermal or physical stresses. In some embodiments, a material for the underfill800includes polymeric materials or resins. In some embodiments, the underfill800is formed by capillary underfill filling (CUF). A dispenser (not shown) may apply a filling material (not shown) along the perimeter of the top packages700A,700B. In some embodiments, the underfill800is formed by molding. In some embodiments, heating may be applied to let the filling material penetrate in the interstices defined by the conductive balls760between the top packages700A,700B and the redistribution structure100by capillarity. In some embodiments, a curing process is performed to consolidate the underfill800. It should be noted that whilst inFIG.1Gthe underfill800is shown to almost entirely fill the gap G in between the top packages700A,700B, in some embodiments a height level reached by the underfill800(i.e., a degree of filling of the gap G), may be a function of the distance between the two top packages, as from said distance might depend the capillary forces experienced by the underfill material during the capillary underfill filling step. In some embodiments, the underfill800may reach a lower height level than the one shown inFIG.1G. The height level reached by the underfill is not to be construed as a limitation of the disclosure.

In some embodiments, as shown inFIG.1H, a hole H is formed in the underfill800in the region corresponding to the gap G (seeFIG.1F) between the top packages700A,700B. In some embodiments, the hole H is opened via laser drilling. By tuning the power of the laser, it is possible to remove a portion of the underfill800until reaching the back-side redistribution structure100. In some embodiments, the laser drills through the underfill800and the topmost dielectric layer110of the redistribution structure100until reaching the conductive layer120. In some embodiments, the conductive layer120includes a conductive pattern embedded in the back-side redistribution structure100and located above the semiconductor die300. In some embodiments, the laser drilling for opening the hole H stops at the conductive pattern (i.e. laser drilling stops when the conductive pattern is exposed). In some embodiments, the conductive pattern includes a conductive ground plane GR or functions as a conductive ground plane for the package. In some embodiments, as shown inFIG.1H, the hole H exposes at least a portion of the conductive ground plane GR. It should be noted that whilst inFIG.1Hthe hole H is shown to extend for only a portion of the gap G between the two top packages700A,700B, the disclosure is not limited thereto. In some alternative embodiments, the hole H can extend up to the entire gap G. Furthermore, while the hole H is shown having a somewhat tapered profile defined by the underfill800, the disclosure is not limited thereto. In some embodiments, the inner side surfaces of the underfill800defining the hole H may have a substantially vertical profile.

Whilst inFIG.1Hthe hole H is shown to extend in the gap G (shown inFIG.1F) between the two top packages700A,700B, the disclosure is not limited thereto. InFIG.2AtoFIG.2Care illustrated schematic top views of manufacturing intermediates corresponding to the stage illustrated inFIG.1Haccording to some embodiments of the present disclosure. InFIG.2Ais illustrated a top view of the manufacturing intermediate ofFIG.1H. Referring simultaneously toFIG.2AandFIG.1H, the reconstructed wafer RW is shown disposed on the supporting frame SF. According toFIG.2A, four bottom package units BPU are shown in the reconstructed wafer RW, but, of course, this is for illustrative purposes only, and the disclosure is not limited by the number of bottom package units BPU being produced in the reconstructed wafer RW. The outlined area labeled as300corresponds to the position of the semiconductor die300within each of the bottom package units BPU. Similarly, the outlined areas labeled as700A and700B correspond to the positions of to the top packages700A and700B, respectively. The area labelled as GR corresponds to the position of the conductive ground plane GR in the redistribution structure100, and, similarly, the area labelled as H corresponds to the position of the hole H. As shown inFIG.2A, viewing from the top view along the vertical direction (the thickness direction Z inFIG.1H), the position of the hole H overlaps with the conductive ground plane GR and overlaps with the semiconductor die300of the bottom package unit BPU. In some embodiments, a vertical projection of the outline of the hole H falls entirely within the span of the semiconductor die300, but the disclosure is not limited thereto. Furthermore, whilst two top packages700A,700B are shown, in some alternative embodiments only one top package (for example,700A), is included in the finished semiconductor device. Even when only one top package700A is included over the bottom package unit BPU, the top package would not entirely cover the position of the semiconductor die300, so that the hole H can overlap with the semiconductor die300.

In some embodiments, the hole H exposes a portion of the conductive ground plane GR. In alternative embodiments, the hole H penetrates through the conductive ground plane GR and exposes the back surface of the underlying semiconductor die300.

InFIG.2Bis shown a top view of a manufacturing intermediate according to some embodiments of the present disclosure. Referring toFIG.1HandFIG.2B, the manufacturing intermediate ofFIG.2Bdiffers from the manufacturing intermediate ofFIG.2Aas two holes, H1and H2, are formed in the underfill800over the semiconductor die300. As for the hole H ofFIG.2A, each one of the holes H1and H2overlaps with the position of the semiconductor die300.

InFIG.2Cis shown a top view of a manufacturing intermediate according to some embodiments of the present disclosure. Referring toFIG.1HandFIG.2C, the manufacturing intermediate ofFIG.2Cdiffers from the manufacturing intermediate ofFIG.2Afor the relative disposition of the semiconductor die300, the top packages700A,700B, the conductive ground plane GR and the hole H. More specifically, the conductive ground plane GR and the hole H are disposed at or around a first corner Cl of the bottom package units BPU, with the two top packages700A and700B disposed along the remaining edges of the bottom package units BPU. In other words, according to some embodiments illustrated inFIG.2C, the hole H is disposed beside the two top packages700A,700B rather than in between. In some embodiments, as shown inFIG.2C, the hole H has a pair of side surfaces S1and S2having a common edge, and the side surface S1faces the top package700A, while the side surface S2faces the top package700B.

Referring toFIG.1I, in some embodiments, an adhesion layer910is blanketly formed on the exposed surfaces of the top packages700A,700B and the reconstructed wafer RW. In some embodiments, the adhesion layer910covers the exposed surfaces of the top packages700A,700B, the underfill800, and the portions of the back-side redistribution structure that are covered neither by the top packages700A,700B nor by the underfill800. In some embodiments, the adhesion layer910is conformally formed covering the sidewalls700sand the top surfaces700tof the top packages700A,700B and covering the side surfaces of the hole H and the exposed conductive ground plane GR. That is, the adhesion layer910extends along the side surfaces of the hole H to contact the conductive ground plane GR. Whilst inFIG.1Ithe adhesion layer910is shown to reach the back-side redistribution structure100, at the edges of the reconstructed wafer RW it may even reach the front-side redistribution structure500. The adhesion layer910may be formed through, for example, a sputtering process, a physical vapor deposition (PVD) process, or the like. In some embodiments, the adhesion layer910includes, for example, copper, tantalum, titanium-copper alloys, or other suitable metallic materials. In some embodiments, the adhesion layer910includes, for example, polymers, hybrid materials or other suitable materials. In some embodiments, the formation of the adhesion layer910is optional and may be skipped.

Referring toFIG.1J, in some embodiments, a heat dissipating structure900is formed over the top packages700A,700B and the reconstructed wafer RW by applying a thermally conductive material (not shown) and then following a curing step. In some embodiments, where an adhesion layer910is included, the heat dissipating structure900is formed directly on the adhesion layer910by distributing the thermally conductive material on and over the adhesion layer910. In some alternative embodiments, the formation of adhesive layer910is omitted, and the thermally conductive material is applied over the exposed surfaces of the top packages700A,700B and the reconstructed wafer RW, and the heat dissipating structure900is in direct contact with the exposed surfaces of the top packages700A,700B, the underfill800, and the redistribution structure100. In some embodiments, the thermally conductive material includes metals, metal alloys or other thermal conductive metallic materials. In some embodiments, the thermally conductive material is a silver paste. In some alternative embodiments, a solder-based paste is used as thermally conductive material. In some embodiments, the thermally conductive material includes eutectic solder containing lead or lead-free. In some embodiments, the thermally conductive material includes solder containing Sn—Ag, Sn—Cu, Sn—Ag—Cu, or similar soldering alloys. In some embodiments, the thermally conductive material includes non-eutectic solder. In some embodiments, the thermally conductive material includes ceramics, carbon fiber, graphene, hybrid polymers or other thermal conductive materials. In some embodiments, the thermally conductive material has a thermal conductivity equivalent to or larger than 1.5 watts per kelvin-meter (W/(K m)). The choice of the thermally conductive material may be dictated by considerations of desired performances and production costs.

In some embodiments, as shown inFIG.1J, the heat dissipating structure900includes at least a thermal relaxation block920disposed within and filling the hole H. In some embodiments, the thermal relaxation block920is disposed on the adhesion layer910and surrounded by the adhesion layer910and the thermal relaxation block920extends vertically towards the back-side redistribution structure100of the bottom package structure BP. In some embodiments, when the formation of the adhesion layer910is omitted, the thermal relaxation block920contacts the side surfaces of the hole H and reaches and contacts the conductive ground plane GR of the back-side redistribution structure100. As the thermal relaxation block920is formed by filling the hole H, a vertical projection of the thermal relaxation block920falls within the span of the semiconductor die300of the bottom package structure BP. In some embodiments, a vertical projection of the thermal relaxation block920overlaps with the active surface300aof the semiconductor die300. The thermal relaxation block920provides an efficient dissipation channel for the heat produced by the operation of the semiconductor die300. In some embodiments, the heat dissipating structure900may further include a wall portion930covering the outer side surfaces700sof the top packages700A,700B, but the disclosure is not limited thereto. In some embodiments, the heat dissipating structure900further includes a cap portion940extending over the thermal relaxation block920and the top surfaces700tof the top packages700A,700B. In some embodiments, the several portions of the heat dissipating structure900are formed during the same production step. In some embodiments, a material of the wall portion930and cap portion940is the same as a material of the thermal relaxation block920, but the disclosure is not limited thereto. In some alternative embodiments, a material of the cap portion940is different from a material of the thermal relaxation block920. In some embodiments, the wall portion930and the cap portion940of the heat dissipating structure900help to increase the thermal relaxation rate of the produced semiconductor package.

In some embodiments, as shown inFIG.1KandFIG.1L, a singulation step is performed to separate the individual packages10, for example, by cutting through the reconstructed wafer RW along the scribing lanes SP arranged between bottom package units BPU. Side portions of the heat dissipating structure900may also be removed during the singulation step. As shown inFIG.1K, in some embodiments adjacent packages10may be separated by cutting through the scribing lanes SP of the reconstructed wafer RW and, optionally, the adhesion layer910during the singulation step. In some embodiments, the singulation process typically involves performing a wafer dicing process with a rotating blade and/or a laser beam.

After the singulation step, a plurality of semiconductor packages10are obtained. An exemplary cross-sectional view of the semiconductor package10according to some embodiments of the disclosure is illustrated inFIG.1L. Based on the above, the semiconductor package10includes the bottom package BP1(similar to the bottom package unit BPU), one or more top packages700A,700B, and the heat dissipating structure900. The bottom package BP1includes the semiconductor die300sandwiched between the front-side redistribution structure500and the back-side redistribution structure100. The conductive structures200provide electrical connection between the front-side redistribution structure500and the back-side redistribution structure100. The semiconductor die300and the conductive structure200are embedded in the encapsulant400. In some embodiments, connective terminals600are disposed on the front-side redistribution structure500for electrically connecting the semiconductor package10with other electronic devices (not shown). In some embodiments, an underfill800is disposed between the top packages700A,700B and the bottom package BP. In some embodiments, the underfill800may present one or more holes H extending towards the back-side redistribution structure100. A first portion of the heat dissipating structure900may fill the holes H, forming one or more thermal relaxation blocks920. In some embodiments, the heat dissipating structure900further includes a wall portion930covering the side surfaces700sof the top packages700A and700B. In some embodiments, the heat dissipating structure900includes a cap portion940extending over the thermal relaxation block920and the top packages700A,700B. Because the heat dissipating structure900is in direct contact with the bottom package BP, and the thermal relaxation block920overlaps with the semiconductor die300, a heat path can be directly formed at the back surface300bof the semiconductor die300. As such, the semiconductor package10can efficiently dissipate the heat generated during its operation, and operation with powers of above 5 W can be achieved.

According to some embodiments, the semiconductor package10may be connected to a circuit substrate1000such as a motherboard, a printed circuit board, or the like, as shown inFIG.1M.

InFIG.3is shown a schematic cross-sectional view of a semiconductor package20according to some embodiments of the present disclosure. The semiconductor package20ofFIG.3may contain similar components to the semiconductor package10ofFIG.1L, and the same or similar reference numerals are used to indicate analogous components between the two packages10and20. The semiconductor package20differs from the semiconductor package10as the heat dissipating structure further includes a heat spreader950connected to the cap portion940. In some embodiments, the heat spreader950is attached to cap portion940through a thermal interface material layer (not shown), an adhesive (not shown), or a combination thereof. In some embodiments, the heat spreader950consists of a block of thermally conductive material that promotes dissipation of the heat produced while operating the semiconductor die300or the top packages700A,700B. In some embodiments, the heat spreader950is a laminated structure comprising a plurality of different metallic or thermally conductive layers.

InFIG.4is shown a cross-sectional view of a semiconductor package30according to some embodiments of the present disclosure. The semiconductor package30ofFIG.4may contain similar components to the semiconductor package10ofFIG.1L, and the same or similar reference numerals are used to indicate analogous components between the two packages10and30. The semiconductor package30ofFIG.4differs from the semiconductor package10of FIG.1L as the semiconductor die300in the bottom package BP′ is disposed in a face-up configuration. That is, an active surface300aof the semiconductor die300is closer to the top packages700A,700B than to the connective terminals600. In some embodiments, production of the bottom package BP′ may include the following steps. The redistribution structure500′, that may now be referred to as a back-side redistribution structure, may be produced first over a temporary carrier (not shown). The conductive structures200and the semiconductor die300may be produced over the redistributions structure500′. The semiconductor die300may be disposed in a face-up configuration over the redistribution structure500′. The die300and the conductive structure200may be embedded in the encapsulant400, and the redistribution structure100′, that may now be referred to as a front-side redistribution structure, may be subsequently formed.

In some embodiments, the underfill800is disposed between the top packages700A,700B and the bottom package BP′. In some embodiments, the underfill800may present one or more holes H extending towards the front-side redistribution structure100′. Each hole H may expose a conductive pattern of the front-side redistribution structure100′. In some embodiments, the conductive pattern includes a conductive ground plane GR or functions as a conductive ground plane for the package. A first portion of the heat dissipating structure900may fill each hole H, forming one or more thermal relaxation blocks920. In some embodiments, a thermal connection is established between the semiconductor die300and the thermal relaxation block920. In some embodiments, the heat dissipating structure900further includes a wall portion930covering the side surfaces700sof the top packages700A and700B. In some embodiments, the heat dissipating structure900includes a cap portion940extending over the thermal relaxation block920and the top packages700A,700B. In some embodiments, the thermal relaxation block920, the wall portion930and the cap portion940are disposed on an optional adhesion layer910. Because the heat dissipating structure900can establish an efficient thermal exchange with the bottom package BP′, a heat path can be formed reaching the active surface300aof the semiconductor die300. As such, the semiconductor package30can efficiently dissipate the heat generated during operation, and working powers of 5 W or above can be reliably achieved.

FIG.5AthroughFIG.5Cshow schematic cross-sectional views illustrating structures produced at various stages of a manufacturing method of a semiconductor package40shown inFIG.5C. The manufacturing intermediate shown inFIG.5Amay be formed following similar steps as previously described with reference toFIG.1F, and a detailed description thereof is omitted herein. Briefly, the manufacturing intermediate ofFIG.5Aincludes a bottom package structure BP and one or more top packages700A,700B. In some embodiments, multiple bottom package units BPU are formed in a reconstructed wafer RW disposed over a supporting frame SF. Each bottom package structure BP includes a semiconductor die300sandwiched between a front-side redistribution structure500and a back-side redistribution structure100. Conductive structures200provide electrical connection between the front-side redistribution structure500and the back-side redistribution structure100. The semiconductor die300and the conductive structures200are embedded in an encapsulant400. A difference between the structure shown inFIG.5Aand the corresponding structure shown inFIG.1Fis the presence of an additional opening OP3in the back-side redistribution structure100where a conductive ball1100has been placed. In some embodiments the conductive ball1100is a solder ball, but the disclosure is not limited thereto. In some embodiments, the opening OP3exposes a conductive pattern of the back-side redistribution structure100. In some embodiments, the conductive pattern includes a conductive ground plane GR or functions as a conductive ground plane for the package, and the conductive ball1100is in contact with the conductive ground plane GR.

In some embodiments, as shown inFIG.5B, an underfill800may be produced between the top packages700A,700B and the back-side redistribution structure100, and may also be disposed in between the top packages700A and700B. A material and a production method of the underfill800may be similar to what previously described with reference toFIG.1Gand a detailed description thereof is omitted herein. In some embodiments, a hole H is opened in the underfill to expose the conductive ball1100. In some embodiments, the hole H is opened via lased drilling, and material is removed from the underfill800until the conductive ball1100is reached. In some embodiments, an upper portion of the conductive ball1100may also be removed. In some embodiments, an adhesion layer910is formed, similarly to what previously described with reference toFIG.1I, and a detailed description thereof is omitted herein. In some embodiments, the adhesion layer910is not formed. Similarly to what described with reference toFIG.1JtoFIG.1L, distribution of a thermally conductive material (not shown), followed by a curing step, a singulation step and removal from the supporting frame SF produces the semiconductor package40shown inFIG.5C.

Based on the above, a semiconductor package40includes the bottom package BP2, one or more top packages700A,700B, and the heat dissipating structure900. The bottom package BP2includes the semiconductor die300sandwiched between the front-side redistribution structure500and the back-side redistribution structure100. The conductive structures200provide electrical connection between the front-side redistribution structure500and the back-side redistribution structure100. The semiconductor die300and the conductive structure200are embedded in the encapsulant400. In some embodiments, the underfill800is disposed between the top packages700A,700B and the bottom package BP2. In some embodiments, the underfill800may present one or more holes H extending towards the back-side redistribution structure100. Each hole H may expose a conductive ball1100connected to a conductive pattern GR of the redistribution structure100. A first portion of the heat dissipating structure900may fill each hole H, forming one or more thermal relaxation blocks920. In some embodiments, a thermal connection is established between the bottom package BP2and the thermal relaxation block920through the conductive ball1100. In some embodiments, the heat dissipating structure900further includes a wall portion930covering the side surfaces700sof the top packages700A and700B. In some embodiments, the heat dissipating structure900includes a cap portion940extending over the thermal relaxation block920and the top packages700A,700B. Because the heat dissipating structure900can establish an efficient thermal exchange with the bottom package BP2through the conductive ball1100, and the thermal relaxation block920overlaps with the semiconductor die300, a heat path can be directly formed at the back surface300bof the semiconductor die300. As such, the semiconductor package40can efficiently dissipate the heat generated during its operation, and operation with powers of 5 W or above can be achieved.

FIG.6AandFIG.6Bshow schematic cross-sectional views illustrating structures produced at various stages of a manufacturing method of a semiconductor package50shown inFIG.6B. The manufacturing intermediate shown inFIG.6Amay be formed following similar steps as previously described with reference toFIG.1AtoFIG.1I, and a detailed description thereof is omitted herein. Briefly, the manufacturing intermediate ofFIG.6Aincludes a bottom package structure BP and one or more top packages700A,700B. In some embodiments, multiple bottom package units BPU are formed in a reconstructed wafer RW disposed over a supporting frame SF. Each bottom package structure BP includes a semiconductor die300sandwiched between a front-side redistribution structure500and a back-side redistribution structure100. Conductive structures200provide electrical connection between the front-side redistribution structure500and the back-side redistribution structure100. The semiconductor die300and the conductive structures200are embedded in an encapsulant400. An underfill800is formed between the top packages700A,700B and the back-side redistribution structure100. The underfill800may have originally extended in between the top packages700A,700B, before a hole H was opened therein. In some embodiments, the hole H is opened via laser drilling. A difference between the structure shown inFIG.6Aand the corresponding structure shown in FIG.1I is the fact that the hole H exposes the semiconductor die300. In other words, the drilling step was performed in such a way to stop only when the back surface300bof the die300was reached. In some embodiments, the back-side redistribution structure100includes a conductive pattern. In some embodiments, the conductive pattern includes a conductive ground plane GR or functions as a conductive ground plane for the package. In some embodiments, the conductive ground plane GR is disposed along the drilling direction, so that the laser may perforate the conductive ground plane GR while opening the hole H. In some embodiments, an adhesion layer910is blanketly formed over the reconstructed wafer RW. Distribution of the thermally conductive material (not shown), followed by a curing step, a singulation step, and removal from the supporting frame SF produces the semiconductor package50shown inFIG.6B.

Based on the above, a semiconductor package50shown inFIG.6Bincludes the bottom package BP3, one or more top packages700A,700B, and the heat dissipating structure900. The bottom package BP3includes the semiconductor die300sandwiched between the front-side redistribution structure500and the back-side redistribution structure100. The conductive structures200provide electrical connection between the front-side redistribution structure500and the back-side redistribution structure100. The semiconductor die300and the conductive structure200are embedded in the encapsulant400. In some embodiments, the underfill800is disposed between the top packages700A,700B and the bottom package BP3. In some embodiments, the underfill800may present one or more holes H extending towards the back-side redistribution structure100. Each hole H may expose the back surface300bof the semiconductor die300. A first portion of the heat dissipating structure900may fill each hole H, forming one or more thermal relaxation blocks920. In some embodiments, a thermal connection is directly established between the semiconductor die300and the thermal relaxation block920. In some embodiments, the heat dissipating structure900further includes a wall portion930covering the side surfaces700sof the top packages700A and700B. In some embodiments, the heat dissipating structure900includes a cap portion940extending over the thermal relaxation block920and the top packages700A,700B. In some embodiments, the thermal relaxation block920, the wall portion930and the cap portion940are disposed on an optional adhesion layer910. Because the heat dissipating structure900can establish an efficient thermal exchange with the bottom package BP3, and the thermal relaxation block920directly contacts the semiconductor die300, a heat path can be formed reaching the back surface300bof the semiconductor die300. As such, the semiconductor package50can efficiently dissipate the heat generated during operation, and working powers of 5 W or above can be reliably achieved.

In light of the present disclosure, when stacking semiconductor packages, formation of a heat dissipating structure contacting a bottom package ensures efficient dissipation of the heat produced during operation of the bottom package. As such, semiconductor devices that include the heat dissipating structure of the present disclosure can operate at higher working powers. As such, thermal performance and reliability of the semiconductor devices are also improved.

In some embodiments of the present disclosure, a semiconductor package includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.

In some embodiments of the present disclosure, a semiconductor package includes a bottom package, a plurality of top packages, and a heat dissipation module. The bottom package includes: a die, a redistribution structure, a back-side redistribution layer and a conductive structure. The die has an active surface and a back surface opposite to the active surface. The redistribution structure is disposed on the active surface of the die and is electrically connected with the die. The back-side redistribution layer is disposed on the back surface of the die. The conductive structure electrically connects the redistribution structure and the back-side redistribution layer. The plurality of top packages is disposed on the bottom package. Top packages of the plurality of top packages are arranged side by side and separated from each other. The heat dissipation module includes a top layer and a thermally conductive block. The top layer is disposed over and covers the plurality of top packages. The thermally conductive block is disposed between at least two top packages of the plurality of top packages, and extends in a vertical direction from the top layer toward the back-side redistribution layer.

In some embodiments of the present disclosure, a manufacturing method of a semiconductor package includes at least the following steps. A bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to the die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

In some embodiments of the present disclosure, a manufacturing method of a semiconductor package includes at least the following steps. A bottom package comprising a semiconductor die is provided. A top package is disposed on the bottom package. The top package is electrically connected to the bottom package by a plurality of conductive balls. An underfill is disposed between the top package and the bottom package. The underfill surrounds the conductive balls and is further disposed on a side of the top package. A portion of the underfill is removed to form a hole. The hole is located at the side of the top package. A thermally conductive material is disposed within the hole and over the top package. The thermally conductive material disposed within the hole and over the top package is cured.

In some embodiments of the present disclosure, a manufacturing method of a semiconductor package includes at least the following steps. A redistribution structure is formed. The redistribution structure is electrically connected to an encapsulated semiconductor die. A first package and a second package are connected to the redistribution structure via a plurality of conductive balls. The first package and the second package are separated from each other by a gap. An adhesion layer is disposed over the redistribution structure, on the first package and the second package, and in the gap. A thermally conductive material is applied on the adhesion layer. The thermally conductive material is cured after the thermally conductive material is applied on the adhesion layer.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.