Patent ID: 12211823

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

A package structure and the method of forming the same are provided in accordance with various embodiments. In some embodiments, the package structure is a System on Integrated Chip (SoIC) package. The intermediate stages of forming the SoIC package are illustrated in accordance with some embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is appreciated that although the formation of SoIC packages is used as examples to explain the concept of the embodiments of the present disclosure, the embodiments of the present disclosure are readily applicable to other package structures and packaging methods in which redistribution layer is connected to through vias.

FIG.1AtoFIG.1Lare schematic cross-sectional views illustrating a method of forming a package structure according to some embodiments of the disclosure.

Referring toFIG.1A, in some embodiments, a die20is electrically bonded to a die10. The die20and the die10may respectively be an application-specific integrated circuit (ASIC) chip, an System on Chip (SoC), an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip, a logic die such as a Central Processing Unit (CPU) die, a Micro Control Unit (MCU) die, a BaseBand (BB) die, an Application processor (AP) die, or a memory chip such as a Dynamic Random Access Memory (DRAM) die or a Static Random Access Memory (SRAM) die, or the like, other types of die, for example. The die20and the die10may be the same types of dies or different types of dies, and the types of the dies are not limited in the disclosure. Various suitable bonding techniques may be applied for the bonding of the die20to the die10. For example, the die20may be bonded to the die10through hybrid bonding, fusion bonding, or the like, or combinations thereof. Although one die10and one die20are shown in the figures, the number of the dies10and20are not limited in the disclosure.

The die10may be a chip included in a semiconductor wafer in the present stage. Although one die10is shown, it is understood that the semiconductor wafer includes a plurality of dies10each of which locates within a die region of the wafer and spaced from each other by scribe regions. The singulation of the dies10may be performed in subsequent processes (FIG.1L). The die20may be a die which have been singulated from another semiconductor wafer and mounted on the die through pick-and-place processes. In some embodiments, the die10and the die20have similar structures, and the detailed structure of the dies will be described below taken the die10as an example.

In some embodiments, the die10includes a substrate100, devices101, an interconnection structure104, a passivation layer106, pad(s)107and a bonding structure112. In some embodiments, the substrate100is a semiconductor substrate made of silicon and/or other semiconductor materials. Alternatively or additionally, the substrate100includes other elementary semiconductor materials such as germanium, gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substrate100may further include other features such as various doped regions, buried layer(s), and/or epitaxy layer(s). Moreover, in some embodiments, the substrate100is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Furthermore, the substrate100may be a semiconductor on insulator such as silicon on insulator (SOI) or silicon on sapphire.

In some embodiments, a plurality of devices101are formed in and/or on the substrate100. The devices101may also be referred to as integrated circuit devices. In some embodiments, the devices101include active devices, passive devices, or combinations thereof. The devices101may include, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or the like, or combinations thereof. The details of the devices101are not illustrated herein for the sake of brevity.

The interconnection structure104is formed on the substrate100to electrically connect the various devices101to form a functional circuit. The interconnection structure104may include a metallization structure (conductive structure)103embedded in a dielectric structure102. The dielectric structure102may include a plurality of dielectric layers, such as inter-layer dielectric layers (ILDs) and inter-metal dielectric layers (IMDs). In some embodiments, the dielectric structure102is an inorganic dielectric structure. Additionally or alternatively, the dielectric structure102may include organic dielectric material. For example, the material of the dielectric structure102may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-K dielectric material, such as un-doped silicate glass (USG), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), fluorinated silica glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like.

The metallization structure103includes a plurality of conductive features interconnected to each other and embedded in the dielectric structure102. The conductive features may include multi-layers of conductive lines, conductive vias, and conductive contacts. The conductive contacts may be formed in the ILDs to electrically connect the conductive lines to the devices101; the conductive vias may be formed in the IMDs to electrically connect the conductive lines in different layers. The conductive features of the metallization structure103may include metal, metal alloy or a combination thereof. For example, the conductive features may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. In some embodiments, the topmost conductive features of the metallization structure103have top surfaces substantially coplanar with a top surface of the dielectric structure102, but the disclosure is not limited thereto.

In some embodiments, the passivation layer106is formed on the interconnection structure104to cover the dielectric structure102and the metallization structure103. The passivation layer106may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In an embodiment, the material of the passivation layer106is different from an underlying dielectric layer of the dielectric structure102. For example, the topmost dielectric layer of the dielectric structure102includes silicon oxide, while the passivation layer106includes silicon nitride. However, the disclosure is not limited thereto.

The pad107is formed on and penetrating through the passivation layer106to electrically connect to a top conductive feature of the interconnection structure104, and further electrically connected to the devices101through the interconnection structure104. The pad107includes conductive materials such as metal or metal alloy, such as aluminum, copper, nickel, or alloys thereof. In an embodiment, the pad107is an aluminum pad. In some embodiments, the pad107includes a via portion embedded in and penetrating through the passivation layer106to be in electrical and physical contact with the topmost conductive feature of the interconnection structure104, and a protruding portion on the via portion and the passivation layer106. Although one pad107is illustrated in the figures, the die10may include a plurality of pads107, and the number of the pads107is not limited in the disclosure.

In some embodiments, the bonding structure112is formed over the interconnection structure104, the pads107and the passivation layer106and connected to the metallization structure103and/or the pad107. The bonding structure112may include a dielectric structure108and a plurality of bonding conductors110embedded in the dielectric structure108. The dielectric structure108may include oxide such as silicon oxide, nitride such as silicon nitride, oxynitride such as silicon oxynitride, undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), or a combination thereof. The material of the dielectric structure108may be the same as or different from the material of the passivation layer106. The dielectric structure108may be formed by a suitable process such as spin coating, chemical vapor deposition (CVD) or the like. The bonding conductor110may be formed of aluminum, copper, nickel, gold, silver, tungsten, or combinations thereof and formed by single damascene process(es) or dual-damascene process.

In some embodiments, the dielectric structure108covers the sidewalls and top surfaces of the pads107, and the top surface of the passivation layer106. The dielectric structure108may include a single layer or multiple layers. In some embodiments, the dielectric structure108has a multi-layer structure including a first dielectric layer108aand a second dielectric layer108bon the first dielectric layer108a. The materials of the first dielectric layer108aand the second dielectric layer108bmay be the same or different. In some embodiments, both of the first dielectric layer108aand the second dielectric layer108binclude oxide such as silicon oxide. In some embodiments, the thickness of the first dielectric layer108ais larger than the thickness of the second dielectric layer108b. In some other embodiments, more than two dielectric layers may be included in the dielectric structure108, and the number of the layers of the dielectric layers is not limited in the disclosure.

In some embodiments, the bonding conductors110penetrate through the dielectric structure108and the passivation layer106to be in electrical and physical contact with the metallization structure130of the interconnection structure104. In an embodiment, the bonding conductors110are landing on a topmost conductive feature of the metallization structure130, but the disclosure is not limited thereto. In alternative embodiments, some or all of the bonding conductors110may land on the pads107. In other words, the bonding conductors110may land on the metallization structure130(such as topmost conductive feature thereof), the pads107or combinations thereof.

In some embodiments, the bonding conductor110includes a conductive via110aand a bonding pad110belectrically connected to each other. In the embodiment in which the bonding conductor110is formed by dual-damascene process, the conductive via110aand the bonding pad110bare simultaneously formed and there is free of interface therebetween. In alternative embodiments in which the bonding conductor110is formed by single damascene process, the conductive via110aand the bonding pad110bare separately formed and an interface may be existed therebetween. The materials of the conductive via110aand the bonding pad110bmay be the same or different. The cross-section shapes of the conductive via110aand the bonding pad110bmay respectively be square, rectangle, trapezoid, or the like. The sidewalls of the conductive via110aand the bonding pad110bmay respectively be straight or inclined, but the disclosure is not limited thereto. The cross-section shape of the bonding conductor110may be T-shaped or the like.

In some embodiments in which the bonding conductor110lands on topmost conductive feature of the metallization structure103, the conductive via110ais embedded in and penetrating through the first dielectric layer108aand the passivation layer106to connect to the topmost conductive feature. In alternative embodiments in which the bonding conductor110lands on the pad107, the conductive via110awould be embedded in the dielectric layer108awithout penetrating through the passivation layer106.

The bonding pad110bis embedded in the second dielectric layer108band in physical and electrical contact with the conductive via110a. In some embodiments, the top surfaces of the bonding pads110bare substantially coplanar with the top surface of the dielectric layer108b.

In some embodiments, the bonding conductors110include bonding conductor(s)110A used for bonding to the die20and bonding conductor(s)110B used for through via landing in subsequent process.

Still referring toFIG.1A, in some embodiments, the die20includes a structure similar to the die10. For example, the die20includes a substrate200, devices201, an interconnection structure204including a metallization structure203embedded in a dielectric structure202, a passivation layer206, pad(s)207, and a bonding structure212including bonding conductors210embedded in a dielectric structure208. In some embodiments, the dielectric structure208includes a first dielectric layer208aand a second dielectric layer208b, the bonding conductor210includes a conductive via210aand a bonding pad210b. The materials and configurations of the substrate200, the devices201, the interconnection structure204, the passivation layer206, the pad(s)207, and the bonding structure212of the die20may be substantially similar to those described above regarding the die10, which are not described again here.

In some embodiments, the die20further includes conductive via(s)209formed in the substrate102and electrically connected to the interconnection structure204. The conductive vias209may extend into the interconnection structure204to be in physical and electrical contact with the conductive features of the interconnection structure204. In some embodiments, the conductive via209includes liner(s) DL covering surface thereof. The liner DL is disposed between conductive via209and the substrate200to separate the conductive via209from the substrate102. The liner DL may surround the sidewalls and/or top surface of the conductive via209. The conductive via209may include copper, copper alloys, aluminum, aluminum alloys, Ta, TaN, Ti, TiN, CoW or combinations thereof. The liner DL may include dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or the like, or combinations thereof.

In some embodiments, the die20is bonded to the die10through a hybrid bonding process, and the hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding such as dielectric-to-dielectric bonding, for example. In some embodiments, the bonding pads210bof the die20are bonded to the bonding pads110bof the die10through metal-to-metal bonding, while the dielectric layer208bof the die20is bonded to the dielectric layer108bof the die10through dielectric-to-dielectric bonding. In some embodiments, the bonding process may be performed as below: first, to avoid the occurrence of the unbonded areas (i.e. interface bubbles), the to-be-bonded surfaces of the die20and the die10(that is, the surfaces of the bonding structures208and108) are processed to be sufficiently clean and smooth. Then, the die20is picked-and-placed on the die10, the die20and the die10are aligned and placed in physical contact at room temperature with slight pressure to initiate a bonding operation. Thereafter, a thermal treatment such as an annealing process at elevated temperatures is performed to strengthen the chemical bonds between the to-be-bonded surfaces of the die20and the die10and to transform the chemical bonds into covalent bonds.

In other words, a bonding interface is existed the bonding structure108of the die10and the bonding structure208of the die20. In some embodiments, the bonding interface is a hybrid bonding interface including a metal-to-metal bonding interface between the bonding pads210band the bonding pads110band a dielectric-to-dielectric bonding interface between the dielectric layer208band the dielectric layer108b.

In some embodiments, the die20is bonded to the die10in a face-to-face configuration. That is, the front surface of the die20faces the front surface of the die10. However, the disclosure is not limited thereto. In alternative embodiments, the die20may be bonded to the die10in a face-to-back configuration, or a back-to-back configuration. In other words, the front surface of the one of the dies10and20may face the back surface of the other one of the dies10and20, or the back surface of the die20may face the back surface of the die10. Throughout the specification, a “front surface” of a die refers to a surface close to pads, and may also be referred to as an active surface; a “back surface” of a die is a surface opposite to the front surface and may be a surface of the substrate, which may also be referred to as a rear surface.

In some embodiments, after the die20is bonded to the die10, a backside grinding process may be performed to thin the die20, and the conductive vias209may be revealed after the backside grinding process. As shown inFIG.1A, in some embodiments, the conductive vias209may extend through the substrate200and be revealed from the top surface (i.e. back surface) of the die20, the top surfaces of the conductive via209and the liner DL may be substantially coplanar with the top surface (i.e. back surface) of the substrate200. In such embodiment, the conductive via209may also be referred to as a through substrate via (TSV). However, the disclosure is not limited thereto. In some other embodiments, the conductive vias209are not revealed at this time, and the backside grinding is stopped when there is a thin layer of substrate200covering the conductive via209(shown as the dashed line). In yet another embodiment, the backside grinding process may be skipped. In some embodiments, the conductive vias209may be revealed in the step shown inFIG.1C.

Referring toFIG.1B, a dielectric material layer300is formed on the die10to cover sidewalls and top surface of the die20. In some embodiments, the dielectric material layer300includes silicon oxide, or TEOS, while other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxy-carbo-nitride, PSG, BSG, BPSG, or the like may also be used. The dielectric material layer300may be formed using CVD, High-Density Plasma Chemical Vapor Deposition (HDPCVD), Flowable CVD, spin-on coating, or the like. In alternative embodiments, the dielectric material layer300may include a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like, and the dielectric material layer300may be formed by a molding process, a molding underfilling (MUF) process, or the like. In the embodiments in which the dielectric material layer300formed by molding process, the dielectric material layer300may have a substantially flat top surface (not shown).

Referring toFIG.1BandFIG.1C, a planarization process is performed to remove a portion of the dielectric material layer300over the top of the die20, and a dielectric layer300ais formed laterally aside the die20. The planarization process may include a chemical mechanical polishing (CMP) process. In some embodiments in which the conductive via209is not revealed in the step ofFIG.1A, the planarization process may further remove a portion of the substrate200and the liner DL over the top of the conductive via209to reveal the conductive via209.

Referring toFIG.1C, the dielectric layer300acovers a portion of the top surface of the die10and the sidewalls of the die20. In some embodiments, the top surface of the dielectric layer300ais substantially coplanar with the top surface of the die20. In an embodiment, the top surface of the dielectric layer300ais substantially coplanar with the top surface (i.e. back surface) of the substrate200and the top surface of the TSV209of the die20. In some embodiments, the dielectric layer300amay also be referred to as a gap-filling dielectric layer or an insulation structure or a dielectric structure.

Referring toFIG.1CandFIG.1D, in some embodiments, the substrate200is recessed such that the TSVs209protrudes from the substrate200, and recesses RC are formed across the substrate200. In some embodiments, the dielectric layer300aand TSV209(e.g. the liner DL of the TSV209) define sidewalls of the recess RC. For example, a portion of the substrate200laterally aside the TSV209may be removed by an etching process, such as wet etching process, dry etching process, or a combination thereof. The etching process may a high etching selectivity ratio between the substrate200and other adjacent materials (i.e. the dielectric layer300, the TSV209and its liner DL). In some embodiments, the dielectric layer300aand the liner DL may be substantially not removed by the etching process, but the disclosure is not limited thereto. In alternative embodiments, a portion of the dielectric layer300aand/or a portion of the liner DL may also be removed by the etching process.

Still referring toFIG.1D, after the recessing process is performed, the top surface of the substrate200is lower than the top surface of the TSV209and the top surface of the dielectric layer300. In other words, the TSV209has a portion protruded from the top surface of the substrate200.

Referring toFIG.1E, an isolation material layer216is formed on die20and the dielectric layer300to cover the top surfaces of the substrate200, top surfaces of the TSV209and the top surface of the dielectric layer300a. In some embodiments, the isolation material layer216is a conformal layer, that is, the isolation material layer216has a substantially equal thickness extending along the region on which the isolation material layer216is formed. The isolation material layer216may include a dielectric material such as silicon nitride, although other dielectric materials such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, a polymer, which may be a photo-sensitive material such as PBO, polyimide, or BCB, a low-K dielectric material such as PSG, BPSG, FSG, SiOxCy, SOG, spin-on polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like may also be used for the isolation material layer216. The isolation material layer216may be formed using a suitable deposition process, such as CVD, atomic layer deposition (ALD), or the like.

In some embodiments, the isolation material layer216is formed to have a thickness at least equal to the height of the recess RC (i.e. the thickness of the portion of the TSV209protruded from the substrate200). In other words, the isolation material layer216fully fills the recess RC.

Referring toFIG.1EandFIG.1F, a planarization process is performed to remove a portion of the isolation material layer216aover the top of the TSV209, so as to reveal the TSV209, and an isolation layer216ais formed. The planarization process may include a CMP process.

Referring toFIG.1F, the isolation layer216ais located on the substrate200and laterally aside the TSV209. In some embodiments, the isolation layer216ais laterally between the TSV209and the dielectric layer300a. The top surface of the isolation layer216amay be substantially coplanar with the top surface of the TSV209and the top surface of the dielectric layer300a. In some other embodiments, the formation of the isolation layer216ashown inFIG.1DtoFIG.1Fmay be omitted. In yet another embodiment, the isolation layer may be formed before forming the dielectric layer300a, and the isolation layer may be formed extending along the top surface and sidewalls of the die20and the top surface of the die10. In yet alternative embodiment, the isolation layer may further extend to cover the top surface of the dielectric layer300a.

Referring toFIG.1G, a dielectric layer302is formed on the die20and the dielectric layer300ato cover the top surfaces of the die20and the dielectric layer300a. The dielectric layer302may include an oxide such as silicon oxide, a nitride such as silicon nitride, USG, or the like, or combinations thereof. The dielectric layer302may be formed by a suitable deposition process such as CVD.

FIG.1HthroughFIG.1Killustrates the formation of through dielectric via310and redistribution layer312according to some embodiments of the disclosure. In some embodiments, the through dielectric via310and the redistribution layer312are formed through dual-damascene process and are formed after forming the dielectric layer302.

Referring toFIG.1H, a patterning process is performed to form via hole(s)303ain the dielectric layer300aand trench(s)303bin the dielectric layer302. The via hole303aand the trench303bmay be together referred to as a recess or an opening formed in the dielectric layer302and the dielectric layer300a. The patterning process removes a portion of the dielectric layer302and a portion of the dielectric layer300ato expose a top surface of the bonding pad110bof the bonding conductor110B of the die10and a top surface of the TSV209of the die20. The pattering process may include multiple photolithograph and etching processes.

The via hole303apenetrates through the dielectric layer300ato expose a portion of the top surface of the bonding pad110bof the bonding conductor110B of the die10. The trench303bpenetrates through the dielectric layer302to be in spatial communication with the via hole303aand expose a portion of the top surface of the dielectric layer300aand/or a portion of the top surface of the die20. In some embodiments, the trench303bexposes the top surface of the TSV209and a portion of the top surface of the isolation layer216aof the die20. The sidewalls of the via hole303aand the trench303bmay be straight or inclined, respectively.

Referring toFIG.1I, a barrier material layer305and a seed material layer306are sequentially formed along the surfaces of the via hole303aand the trench303band the top surface of the dielectric layer302. The barrier material layer305may also be referred to as a diffusion barrier layer. In some embodiments, the barrier material layer305may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed by ALD, CVD, Physical Vapor Deposition (PVD), or the like. The seed material layer306may be a metal seed layer such as a copper seed layer. In some embodiments, the seed material layer306includes a first metal layer such as a titanium layer and a second metal layer such as a copper layer over the first metal layer. The seed material layer306may be formed by a sputtering process, or the like. The seed material layer306may be optionally formed and may be omitted in some other embodiments.

In some embodiments, the barrier material layer305and the seed material layer306fills a portion of the via hole303aand the trench303b. The barrier material layer305covers (or lines) the surfaces of the via hole303aand the trench303band the top surface of the dielectric layer302. The seed material layer306covers the surfaces of the barrier material layer305. In some embodiments, the barrier material layer305is conformal with the via hole303aand the trench303band the dielectric layer302, and the seed material layer306is conformal with the barrier material layer305.

Referring toFIG.1J, conductive material308is formed on the seed material layer306to fill the via hole303aand the trench303b. The conductive material308includes a suitable metallic material, such as copper or copper alloy. The conductive material308fills remaining portions of the via hole303aand the trench303bnot filled by the barrier material layer305and the seed material layer306and further protrudes from the top surface of the dielectric layer302. In some embodiments, the forming method of the conductive material308may include a plating process such as electroplating process or electro-chemical plating, or a suitable deposition process such as CVD, PVD, or the like.

Referring toFIG.1JandFIG.1K, thereafter, a planarization process such as a CMP process is performed to remove excess portions of the conductive material308, the seed material layer306and the barrier material layer305, until the dielectric layer302is exposed, and a barrier layer305a, a seed layer306aand a conductor308aare remained in the via hole303aand the trench303b. In some embodiments, after the planarization process is performed, the top surfaces of the conductor308a, the seed layer306aand the barrier layer305aare substantially coplanar with the top surface of the dielectric layer302. The seed layer306ais sandwiched between and in contact with the barrier layer305aand the conductor308a.

As shown inFIG.1K, the barrier layer305aextends continuously along surfaces of the dielectric layer302and the dielectric layer (insulation structure)300a. The seed layer306aand the barrier layer305asurrounds periphery (sidewalls and bottom surfaces) of the conductor308aand are not interposed in the conductor308a. Portions of the barrier layer305aand portions of the seed layer306aare laterally between the conductor308aand the dielectric layer300aand laterally between the conductor308aand the dielectric layer302.

In some embodiments, the conductor308a, the seed layer306aand the barrier layer305ain the via hole303aconstitute a conductive via which may also be referred to as a through via or a through dielectric via (TDV)310, while the conductor308a, the seed layer306aand the barrier layer305ain the trench303bconstitute a redistribution layer (RDL)312. In some embodiments, a first portion of the conductor308ain the via hole303amay also be referred to as a conductive post, and a second portion of the conductor308in the trench303bmay also be referred to as a conductive layer.

The TDV310is embedded in and penetrating through the dielectric layer300ato be in physical and electrical contact with the top surface of the bonding pad110bof the bonding conductor110B of the die10. The RDL312is embedded in and penetrating through the dielectric layer302to be in electrical and physical contact with the TDV310and the TSV209of the die20. The RDL312is extending and routing on the top surface of the dielectric layer300aand the top surface of the die20. The RDL312may include a plurality of trace sections interconnected to each other. In some embodiments, the RDL312may also be referred to as traces or conductive lines.

Still referring toFIG.1K, in the embodiments of the disclosure, the TDV310and the RDL312are simultaneously formed after the via hole303aand the trench303bbeing formed in the dielectric layers302and300a. Therefore, there is free of interface between the TDV310and the RDL312, and the conductive post (i.e. first portion of the conductor308a) of the TDV310is in direct physical and electrical contact with the conductive layer (i.e. second portion of the conductor308a) of the RDL312without a barrier layer interposed therebetween. As such, the conductivity between the RDL312and the TDV310is improved.

The barrier layer305aof the TDV310and the barrier layer305aof the RDL312are continuous, and there is free of interface therebetween; the seed layer306aof the TDV310and the seed layer306aof the RDL312are continuous, and there is free of interface therebetween; the conductive post308aof the TDV310and the conductive layer308aof the RDL312are continuous, and there is free of interface therebetween. In other words, the TDV310and the RDL312share a barrier layer305a, a seed layer306aand a conductor308a. The conductive layer308aof the RDL312is electrically connected to and in physical contact with the conductive post308aof the TDV310, and there is free of seed layer or barrier layer (vertically) between the conductive layer308aof the RDL312and the conductive post308aof the TDV310.

In some embodiments, the area of the bottom surface of the barrier layer305aof the RDL312(i.e. the area of the bottom surface of the barrier layer305ain the trench303b) is less than the area of the bottom surface of the conductor308aof the RDL312(i.e. the area of the bottom surface of the conductor308ain the trench303b). In other words, in some embodiments, the area of the orthogonal projection of the barrier layer305aof the RDL312on the plane of the top surfaces of dielectric layer300aand the die20is less than the area of the orthogonal projection of the conductive layer308aof the RDL312on the said plane.

In some embodiments, the barrier layer305aof the RDL312(i.e. the barrier layer305ain the trench303b) is not overlapped with the conductive post308aof the TDV310in a direction perpendicular to the top surface of the die20or the top surface of the dielectric layer300a. That is, an area of an orthogonal projection of the barrier layer305aof the RDL312on a top surface of the conductive post308aof the TDV310is zero. Therefore, an area of an orthogonal projection of the barrier layer305aof the RDL312(i.e. the barrier layer305ain the trench303b) on the top surface of the TDV310is less than an area of an orthogonal projection of the conductive layer308aof the RDL312((i.e. the conductor308ain the trench303b)) on the top surface of the TDV310.

In some embodiments, the RDL312is also electrically connected to the TSV209of the die20. An interface is existed between the RDL312and the TSV209of the die20. Portions of the seed layer306aand the barrier layer305aare located between the conductor308aof the RDL312and the TSV209. In other words, the conductive layer308aof the RDL312is separated from the TSV209by the seed layer306aand the barrier layer305atherebetween.

FIG.4AandFIG.4Billustrates top views of the RDL312and the TDV310according to some embodiments of the disclosure.

Referring toFIG.1K,FIG.4AandFIG.4B, in some embodiments, the sidewalls of the TDV310and the RDL312may be straight or inclined, respectively. The cross-sectional shape of the TDV310may be rectangle or tapered. The top view of the TDV310may be round, elliptical or the like or any other suitable shaped. The cross-sectional shape of the RDL312may be strip shaped, rectangle, trapezoid, or the like, and the top view of the RDL312may be strip shaped or the like. Trace sections of the RDL312are shown in the top viewsFIG.3AandFIG.3B. It is noted that, although the trace sections of the RDL312are not shown to be connected, it should be understood that, they are connected to each other by other routing traces (not shown).

FIG.1Lillustrates the formation of passivation layers, conductive pads, and overlying dielectric layers. Referring toFIG.1L, in some embodiments, a passivation layer314(sometimes referred to as passivation-1) is formed over the dielectric layer302and the RDL312, and vias315are formed in the passivation layer314to electrically connect to the RDL312. Conductive pads317are formed on the passivation layer314and the vias315, and are electrically coupled to RDLs312through the vias315. The material of the conductive pad317and the via315may respectively include a suitable metallic material, such as aluminum, copper, alloys thereof, or combinations thereof. In some embodiments, the conductive pads317may be aluminum pads or aluminum-copper pads, and other metallic materials may be used. The vias315and the conductive pads317may be formed separately with an interface therebetween, or formed simultaneously without an interface therebetween.

In some embodiments, a passivation layer316(sometimes referred to as passivation-2) is formed over the passivation layer316to partially cover the conductive pads317. The passivation layers314and316may respectively be a single layer or a composite layer, and may be formed of a non-porous material. In some embodiments, each of the passivation layers314and316may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, one or both of passivation layers314and316is a composite layer including a silicon oxide layer (not shown separately), and a silicon nitride layer (not shown separately) over the silicon oxide layer. The passivation layers314and316may also be formed of other non-porous dielectric materials such as Un-doped Silicate Glass (USG), silicon oxynitride, and/or the like, or combinations thereof.

In some embodiments, the passivation layer316is patterned with a plurality of openings exposing portions of the conductive pads317. For example, portions of the top surfaces of the conductive pads317are exposed by the passivation layer316for further connection.

In some embodiments, the structure underlying conductive pads317are free from organic materials (such as polymer layers), so that the process for forming the structures underlying conductive pads317may adopt the process used for forming device dies, and fine-pitches RDLs (such as312) having small pitches and line widths are made possible. However, the disclosure is not limited thereto. In some other embodiments, polymer materials may also be used.

In some embodiments, a plurality of conductive patterns318are formed on and electrically connected to the conductive pads317exposed by the passivation layer316, and a plurality of conductive terminals320are formed on and electrically connected to the conductive patterns318. In some embodiments, the conductive patterns318may be conductive pillars such as copper pillars. The material of the conductive terminal320may include copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). In some embodiments, the conductive terminals320may be formed of a Sn—Ag alloy, a Sn—Cu alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free or lead-containing. The conductive terminal320may be formed by a suitable process such as evaporation, plating, ball dropping, screen printing and reflow process, a ball mounting process or the like. In some embodiments, the conductive terminals320include solder materials and may also be referred to as solder caps or micro bumps.

In some embodiments, thereafter, a singulation process such as a die saw process may be performed to form a plurality of singulated package structures PKG1, and one of the package structures PKG1is shown inFIG.1L. The package structure PKG1is also referred to as a SoIC package structure. In some embodiments, the package structure PKG1includes the die20and the die10bonded to each other, the dielectric layer300a, the TDV310, the RDL312, the dielectric layer302, the passivation layers314and316, the vias315, the conductive pads317and the conductive terminals320. The conductive terminal320is electrically connected to the dies10and20through the conductive pattern318, the conductive pads317, the RDL312and the TDV310. In the embodiments of the disclosure, the TDV310and the RDL312are formed simultaneously by dual-damascene process.

FIG.2illustrates a package structure PKG1′ according to alternative embodiments of the disclosure. Referring toFIG.2, in some alternative embodiments, a post-passivation layer319may further be formed on the passivation layer316. The post-passivation layer319includes a polymer material such as, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB) or the like, or combinations thereof. The conductive patterns318penetrate through the post-passivation layer319and the passivation layer316to connect to the conductive pads317. In such embodiments, the conductive patterns318may also be under-bump metallurgies (UBMs), and the conductive terminals320may be solder balls, controlled collapse chip connection (C4) bumps, ball grid array (BGA) connectors, or the like.

In some other embodiments, after the passivation layer316is formed, more than one polymer layer are formed over the passivation layer316and post-passivation interconnects (PPI) (not shown) may be formed in the polymer layer(s) and electrically connected to the conductive pads317. The post-passivation interconnects include a plurality of conductive vias and traces interconnected to each other, which may also be referred to as RDLs. The conductive patterns318and the conductive terminals320may be formed over the polymer layers and the post-passivation interconnects to connect to the conductive pads317.

FIG.3illustrates a package structure PKG2according to some other embodiments of the disclosure. The package structure PKG2is similar to the package structure PKG1, except that more TDVs are shown in the package structure PKG2. It is noted that, some components of the package structure PKG2are not specifically shown inFIG.3for the sake of brevity.

Referring toFIG.3, in some embodiments, a plurality of TDVs310are embedded in the dielectric layer300aand landing on the bonding pads110bof the bonding conductor110B. In some embodiments, the bonding pads110bmay be connected to more than one conductive via110a. For example, as shown inFIG.3, the bonding pad110bmay be electrically connected to two conductive vias110a. The number of the conductive vias110corresponding to one bonding pad110bis not limited in the disclosure. In some embodiments, the TDVs310have inclined sidewalls, respectively. For example, the sidewalls of the TDVs310may be tapered toward the die10. The TDVs310and the RDL312are formed simultaneously and have the same features as those of the package structure PKG1described above. The other features of the package structure PKG2may be substantially the same as those of the package structure PKG1, which are not described again here.

In accordance with some embodiments of the disclosure, a package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.

In accordance with alternative embodiments of the disclosure, a package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer, and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via is laterally aside the second die and embedded in the insulation structure. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer penetrates through the dielectric layer to connect to the through via. The through via and the redistribution layer share a barrier layer and a conductor over the barrier layer.

In accordance with some embodiments of the disclosure, a method of manufacturing a package structure includes the following processes. A second die is bonded to a first die. An insulation structure is formed on the first die and laterally aside the second die. A dielectric layer is formed on the second die and the insulation structure. A through via is formed to penetrate through the insulation structure to electrically connect to the first die. A redistribution layer is formed to be embedded in dielectric layer and electrically connected to the through via. The through via is formed after forming the dielectric layer.

In accordance with some embodiments of the disclosure, a package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die and includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via, wherein the redistribution layer comprises a first barrier layer and a conductive layer on the first barrier layer. The conductive layer of the redistribution layer is in contact with a conductive post of the through via, the through substrate via is electrically connected to the redistribution layer, and the conductive layer of the redistribution layer is separated from the through substrate via by the first barrier layer therebetween.

In accordance with alternative embodiments of the disclosure, a package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer, and a redistribution layer. The second die is electrically bonded to the first die and includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via is laterally aside the second die and embedded in the insulation structure. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer penetrates through the dielectric layer to connect to the through via. A portion of the redistribution layer is located on and electrically connected to the through substrate via of the second die, and there is an interface between the redistribution layer and the through substrate via.

In accordance with some embodiments of the disclosure, a method of manufacturing a package structure includes the following processes. A second die is bonded to a first die, and the second die includes a through substrate via. An insulation structure is formed on the first die and laterally aside the second die. A dielectric layer is formed on the second die and the insulation structure. A through via is formed to penetrate through the insulation structure to electrically connect to the first die. A redistribution layer is formed to be embedded in dielectric layer and electrically connected to the through via. A portion of the redistribution layer is located on and electrically connected to the through substrate via of the second die, and there is an interface between the redistribution layer and the through substrate via.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.