Patent ID: 12253953

DETAILED DESCRIPTION

Hereinafter, embodiments are described in detail with reference to the accompanying drawings. Like components are denoted by like reference numerals throughout the specification, and repeated descriptions thereof are omitted. Embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto, and may be realized in various other forms. Each embodiment provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the present disclosure.

FIG.1Ais a block diagram of a storage system SS according to an embodiment.

Referring toFIG.1A, the storage system SS may include a storage device10and a host20, and may thus be referred to as a host-storage system. The storage device10may include a storage controller11, first non-volatile memory (or NVM1)12, and second non-volatile memory (or NVM2)13. According to an embodiment, the storage controller11may be referred to as a controller, a memory controller, or a non-volatile memory controller. According to an embodiment, the first non-volatile memory12and the second non-volatile memory13may be respectively referred to as a first storage region and a second storage region.

The storage controller11may include a central processing unit (CPU)111and a memory112. The CPU111may generally control operations of the storage controller11. For example, the CPU111may be implemented in a controller chip. In an embodiment, the CPU111may include a multi-core processor, for example, a dual-core processor or a quad-core processor. The memory112may be used as a buffer memory or a working memory. For example, the memory112may be implemented in a dynamic random access memory (DRAM) chip or a static RAM (SRAM) chip. In an embodiment, the CPU111and the memory112may be implemented by separate chips from each other. However, embodiments are not limited thereto. The CPU111and the memory112may be implemented by one chip.

The first non-volatile memory12may store mapping data between a logical address and a physical address, i.e., logical-to-physical (L2P) mapping data D1. The logical address may refer to an address received from the host20, and the physical address may refer to an address actually used to store data in the second non-volatile memory13. The second non-volatile memory13may store user data D2. The second non-volatile memory13may further store metadata.

FIG.2illustrates L2P mapping data according to an embodiment.

Referring toFIGS.1A and2, the first non-volatile memory12may store the L2P mapping data D1, which may include a plurality of pieces of mapping data, e.g., first to fourth mapping data MAP1 to MAP4. In an embodiment, each of the first to fourth mapping data MAP1 to MAP4 may be stored in a cell string (e.g., CS inFIG.5).

The first mapping data MAP1 may include a first logical address and a first physical address mapped to the first logical address. In detail, the first mapping data MAP1 may include a first logical address value L1 corresponding to the first logical address and a first physical address value P1 corresponding to the first physical address. For example, the first mapping data MAP1 may be stored in a first cell string. In an embodiment, the first non-volatile memory12may store data obtained by encoding the first logical address value L1 and data obtained by encoding the first physical address value P1.

The second mapping data MAP2 may include a second logical address and a second physical address mapped to the second logical address. In detail, the second mapping data MAP2 may include a second logical address value L2 corresponding to the second logical address and a second physical address value P2 corresponding to the second physical address. For example, the second mapping data MAP2 may be stored in a second cell string. In an embodiment, the first non-volatile memory12may store data obtained by encoding the second logical address value L2 and data obtained by encoding the second physical address value P2.

The third mapping data MAP3 may include a third logical address and a third physical address mapped to the third logical address. In detail, the third mapping data MAP3 may include a third logical address value L3 corresponding to the third logical address and a third physical address value P3 corresponding to the third physical address. For example, the third mapping data MAP3 may be stored in a third cell string. In an embodiment, the first non-volatile memory12may store data obtained by encoding the third logical address value L3 and data obtained by encoding the third physical address value P3.

The fourth mapping data MAP4 may include a fourth logical address and a fourth physical address mapped to the fourth logical address. In detail, the fourth mapping data MAP4 may include a fourth logical address value L4 corresponding to the fourth logical address and a fourth physical address value P4 corresponding to the fourth physical address. For example, the fourth mapping data MAP4 may be stored in a fourth cell string. In an embodiment, the first non-volatile memory12may store data obtained by encoding the fourth logical address value L4 and data obtained by encoding the fourth physical address value P4.

Referring back toFIG.1A, in an embodiment, the host20may transmit, to the storage device10, a read request REQ_READ including a logical address, e.g., a logical block address (LBA). In response to the read request REQ_READ received from the host20, the storage controller11may transmit the logical address, e.g., the LBA, to the first non-volatile memory12. The first non-volatile memory12may search for a physical address, e.g., a physical block address (PBA), corresponding to the logical address and transmit a found physical address, e.g., a PBA, to the storage controller11.

Subsequently, the storage controller11may generate a read command CMD_READ based on the physical address, e.g., the PBA, and transmit, to the second non-volatile memory13, the read command CMD_READ including the physical address, e.g., the PBA. The second non-volatile memory13may read data based on the physical address, e.g., the PBA, and transmit the data to the storage controller11. The storage controller11may transmit the data to the host20.

As described above, the first non-volatile memory12may store the L2P mapping data D1 and perform an operation, i.e., an L2P operation, of searching for a physical address corresponding to a logical address in the L2P mapping data D1. Accordingly, it may not be necessary to load the L2P mapping data D1 to the memory112of the storage controller11, and the number of read operations performed on the first non-volatile memory12to load the L2P mapping data D1 to the memory112and the data traffic between the first non-volatile memory12and the memory112may be reduced. In addition, the storage controller11may not need to perform an L2P operation, and the load of the storage controller11may be reduced.

Accordingly, even when the capacity of the memory112is not sufficient to store mapping data for each of the first non-volatile memory12and the second non-volatile memory13, the storage device10may reduce the decrease in an operating speed while providing high-capacity storage. Consequently, the storage device10may increase the performance of memory operations, such as a write operation and a read operation.

The storage device10may include storage media for storing data at the request of the host20. For example, the storage device10may include at least one selected from the group consisting of a solid-state drive (SSD), an embedded memory, and a removable external memory. When the storage device10is an SSD, the storage device10may comply with a non-volatile memory express standard. When the storage device10is an embedded memory or an external memory, the storage device10may comply with a universal flash storage (UFS) standard or an embedded multimedia card (eMMC) standard. Each of the host20and the storage device10may generate and transmit packets according to the standard protocol thereof.

FIG.1Bis a block diagram of a storage system SS' according to an embodiment.

Referring toFIG.1B, the storage system SS' may include a storage device10′, which includes a storage controller11′, the first non-volatile memory12, and the second non-volatile memory13. The storage controller11′ may correspond to a modification of the storage controller11inFIG.1A, and the descriptions given above with reference toFIG.1Amay also applied to the storage system SS′. The storage controller11′ may further include an encoding/decoding unit113. In an embodiment, the first non-volatile memory12may transmit an encoded physical address to the storage controller11′, and the encoding/decoding unit113may generate an original physical address, i.e., a decoded physical address, by decoding the encoded physical address. In an embodiment, the first non-volatile memory12may transmit an encoded logical address to the storage controller11′, and the encoding/decoding unit113may generate an original logical address, i.e., a decoded logical address, by decoding the encoded logical address. The descriptions given above may also be applied to embodiments below.

FIG.3Ais a detailed diagram of the storage device10inFIG.1A, according to an embodiment.

Referring toFIG.3A, the storage device10may include the storage controller11, the first non-volatile memory12, and the second non-volatile memory13. According to an embodiment, the first non-volatile memory12and the second non-volatile memory13may be implemented by separate memory chips, separate memory dies, or separate memory planes from each other. In an embodiment, the first non-volatile memory12may be implemented by a first memory chip, the second non-volatile memory13may be implemented by a second memory chip, and the first and second memory chips may be included in one package. In an embodiment, the first non-volatile memory12may be implemented by a first memory die, the second non-volatile memory13may be implemented by a second memory die, and the first and second memory dies may be included in one chip or one package. In an embodiment, the first non-volatile memory12may be implemented by a first memory plane, the second non-volatile memory13may be implemented by a second memory plane, and the first and second memory planes may be included in one die, one chip, or one package. In an embodiment, the first non-volatile memory12may be implemented by a first memory block, the second non-volatile memory13may be implemented by a second memory block, and the first and second memory blocks may be included in one die, one chip, or one package.

The first non-volatile memory12may include a decoder121, a memory cell array122, and a page buffer circuit123. The decoder121may generate data corresponding to a logical address value LAV, e.g., an LBA, which is received from the storage controller11, by encoding the logical address value LAV and providing word line voltages corresponding to the data to the memory cell array122. The memory cell array122may store logical address values LAVs and physical address values PAVs. For example, the memory cell array122may store data encoded from the logical address values LAVs and data encoded from the physical address values PAVs. The page buffer circuit123may buffer a physical address value PAV read from the memory cell array122.

In an embodiment, the first non-volatile memory12may store encoded data of a logical address value LAV in a plurality of single-level cells (SLCs). In an embodiment, the first non-volatile memory12may duplicately store the encoded data of the logical address value LAV in memory cells of a plurality of cell strings respectively corresponding to a plurality of bit lines. In an embodiment, the first non-volatile memory12may store the logical address value LAV in at least one multi-level cell (MLC). For example, the MLC may store at least two bits of data.

In an embodiment, the first non-volatile memory12may store encoded data of a physical address value PAV in a plurality of SLCs. In an embodiment, the first non-volatile memory12may duplicately store the encoded data of the physical address value PAV in memory cells of a plurality of cell strings respectively corresponding to a plurality of bit lines. In an embodiment, the first non-volatile memory12may store the physical address value PAV in at least one MLC.

In an embodiment, the first non-volatile memory12may generate the logical address value LAV by decoding the encoded data of the logical address value LAV and providing the logical address value LAV to the storage controller11. In an embodiment, the first non-volatile memory12may generate the physical address value PAV by decoding the encoded data of the physical address value PAV and providing the physical address value PAV to the storage controller11. The second non-volatile memory13may include a decoder131, a memory cell array132, and a page buffer circuit133. The decoder131may decode the read command CMD_READ received from the storage controller11and provide a word line voltage to a selected word line corresponding to the physical address value PAV, e.g., a PBA. The memory cell array132may store user data DATA_U and/or metadata DATA_M. The page buffer circuit133may buffer the user data DATA_U and/or the metadata DATA_M, which is read from the memory cell array132.

FIG.3Bis a detailed diagram of the storage device10′ inFIG.1B, according to an embodiment.

Referring toFIG.3B, the storage controller11′ may further include the encoding/decoding unit113. The storage controller11′ may correspond to a modification of the storage controller11inFIG.3A, and the descriptions given above with reference toFIG.3Amay also applied to the storage device10′. In an embodiment, the first non-volatile memory12may provide encoded data of the logical address value LAV to the storage controller11′, and the encoding/decoding unit113of the storage controller11′ may generate the logical address value LAV by decoding the encoded data of the logical address value LAV. In an embodiment, the first non-volatile memory12may provide encoded data of the physical address value PAV to the storage controller11′, and the encoding/decoding unit113of the storage controller11′ may generate the physical address value PAV by decoding the encoded data of the physical address value PAV.

FIG.4is a block diagram of a non-volatile memory40according to an embodiment.

Referring toFIG.4, the non-volatile memory40may include a memory cell array41, a control logic42, a voltage generator43, a row decoder44, and a page buffer circuit45. The non-volatile memory40may correspond to an implementation of the first non-volatile memory12inFIG.3A. For example, the control logic42, the voltage generator43, and the row decoder44may correspond to the decoder121inFIG.3A. For example, the memory cell array41and the page buffer circuit45may respectively correspond to the memory cell array122and the page buffer circuit123inFIG.3A.

The memory cell array41may include a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz may include a plurality of cell strings. Each of the cell strings may include a plurality of memory cells connected in series to each other. The memory cell array41may be connected to the page buffer circuit45through bit lines BL and connected to the row decoder44through word lines WL, string select lines SSL, and ground select lines GSL.

In an embodiment, the memory cell array41may include a three-dimensional (3D) memory cell array. The 3D memory cell array may include a plurality of cell strings. Each cell string may include memory cells respectively connected to word lines vertically stacked on a substrate. The disclosures of U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application No. 2011/0233648 are incorporated herein in their entirety by reference.

In an embodiment, the memory cell array41may include flash memory. The flash memory may include a two-dimensional (2D) NAND memory array or a 3D (or vertical) NAND (V-NAND) memory array. In an embodiment, the memory cell array41may include magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), or other various types of memory.

At least some of the memory blocks BLK1 to BLKz may store logical address values, physical address values, and/or validity information that indicates validity of a mapping relationship between a logical address and a physical address. In an embodiment, a logical address value may be set to a certain value and thus be invalidated, and invalidation of a mapping relationship may be indicated by applying a certain voltage to a word line. In an embodiment, pieces of mapping information respectively corresponding to different logical addresses may be stored in the memory blocks BLK1 to BLKz.

Referring toFIGS.2and4, for example, the first logical address value L1 and the first physical address value P1 corresponding thereto may be stored in the memory block BLK1, the second logical address value L2 and the second physical address value P2 corresponding thereto may be stored in the memory block BLK2, and the third logical address value L3 and the third physical address value P3 corresponding thereto may be stored in the memory block BLK3. In some embodiments, user data may be stored in the other memory blocks BLK4 to BLKz.

Referring back toFIG.4, the control logic42may generally control various operations of the non-volatile memory40. The control logic42may output various control signals in response to a command CMD, an address ADDR, and/or a control signal CTRL. For example, the control logic42may output a voltage control signal CTRL_vol, a row address X_ADDR, and a column address Y_ADDR. In an embodiment, the control logic42may include an encoder EN. The encoder EN may generate data by encoding a logical address value, which may be received from the storage controller11. The encoder EN may also generate data by encoding a physical address value, which may be received from the storage controller11. The control logic42may further include a decoder corresponding to the encoder EN. The decoder may generate a logical address value and/or a physical address value by decoding data received from the page buffer circuit45.

The voltage generator43may generate various voltages for performing program, read, and erase operations, based on the voltage control signal CTRL_vol. For example, the voltage generator43may generate a program voltage, a read voltage, a program verify voltage, an erase voltage, and the like from a word line voltage VWL. The row decoder44may select at least one of the word lines WL in response to the row address X_ADDR and select one of the string select lines SSL. For example, in a program operation, a search operation, or read operation, the row decoder44may apply the word line voltage VWL to the selected word line. The page buffer circuit45may select at least one of the bit lines BL in response to the column address Y_ADDR. The page buffer circuit45may operate as a write driver or a sense amplifier according to an operation mode. The page buffer circuit45may include a plurality of page buffers PB1 to PBm respectively connected to the bit lines BL, where “m” is a positive integer.

The second non-volatile memory13inFIGS.1A and3Amay be implemented in a manner similar to the non-volatile memory40. For example, the second non-volatile memory13may include the memory cell array41, the control logic42, the voltage generator43, the row decoder44, and the page buffer circuit45. For example, the row decoder44may correspond to the decoder131inFIG.3A. For example, the memory cell array41and the page buffer circuit45may respectively correspond to the memory cell array132and the page buffer circuit133inFIG.3A. The control logic42included in the second non-volatile memory13may not include the encoder EN.

FIG.5is a circuit diagram of a memory block BLK according to an embodiment.

Referring toFIG.5, the memory block BLK may correspond to one of the memory blocks BLK1 to BLKz. The memory block BLK may include a plurality of cell strings CS. Each of the cell strings CS may include a string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST, which are connected in series to one another. The string select transistor SST, the memory cells MC1 to MC8, and the ground select transistor GST, which are included in each cell string CS, may be stacked on a substrate in a vertical direction.

The string select transistor SST may be connected to one of first to third string select lines SSL1 to SSL3. The memory cells MC1 to MC8 may be respectively connected to word lines WL1 to WL8. The ground select transistor GST may be connected to one of ground select lines GSL1 to GSL3. The string select transistor SST may be connected to one of bit lines BL1 to BL3, and the ground select transistor GST may be connected to a common source line CSL. Here, the numbers of cell strings CS, word lines, bit lines, ground select lines, and string select lines may vary with embodiments.

In an embodiment, the memory block BLK may include a plurality of logical address value storage regions R_LA1 to R_LA3 and a plurality of physical address value storage regions R_PA1 to R_PA3. For example, the logical address value storage regions R_LA1 to R_LA3 may include SLCs that store encoded data of a logical address value. For example, the physical address value storage regions R_PA1 to R_PA3 may include SLCs that store encoded data of a physical address value.

For example, the logical address value storage region R_LA1 may include memory cells, which correspond to the first string select line SSL1 and are connected to the word lines WL1 to WL4, and the physical address value storage region R_PA1 may include memory cells, which correspond to the first string select line SSL1 and are connected to the word lines WL5 to WL8. For example, the logical address value storage region R_LA2 may include memory cells, which correspond to the second string select line SSL2 and are connected to the word lines WL1 to WL4, and the physical address value storage region R_PA2 may include memory cells, which correspond to the second string select line SSL2 and are connected to the word lines WL5 to WL8. For example, the logical address value storage region R_LA3 may include memory cells, which correspond to the third string select line SSL3 and are connected to the word lines WL1 to WL4, and the physical address value storage region R_PA3 may include memory cells, which correspond to the third string select line SSL3 and are connected to the word lines WL5 to WL8.

FIG.6is a table showing address values and data corresponding to the address values, according to an embodiment.

Referring toFIGS.1A to4andFIG.6, the control logic42may generate data by encoding a logical address value. In an embodiment, the non-volatile memory40may receive a logical address value in decimal from the storage controller11, and the control logic42may convert the logical address value in decimal into a first value in binary and generate data by encoding the first value. For example, the encoder EN may generate data by encoding “0” in the first value into “01” and “1” in the first value into “10”. For example, logical address value “0” may be converted into first value “00”, and the encoder EN may generate data “0101” by encoding the first value “00”. For example, logical address value “2” may be converted into first value “10”, and the encoder EN may generate data “1001” by encoding the first value “10”. For example, logical address value “1” may be converted into first value “01”, and the encoder EN may generate data “0110” by encoding the first value “01”. For example, logical address value “3” may be converted into first value “11”, and the encoder EN may generate data “1010” by encoding the first value “11”.

However, embodiments are not limited thereto. The non-volatile memory40may receive a logical address value in binary from the storage controller11, and the control logic42may generate data by encoding the binary logical address value. For example, the encoder EN may generate data by encoding “0” in the logical address value into “01” and “1” in the logical address value into “10”.

In an embodiment, the non-volatile memory40may receive a physical address value in decimal from the storage controller11, and the control logic42may convert the physical address value in decimal into a first value in binary and generate data by encoding the first value. The encoder EN may generate data by encoding “0” in the first value into “01” and “1” in the first value into “10”. However, embodiments are not limited thereto. The non-volatile memory40may receive a physical address value in binary from the storage controller11, and the control logic42may generate data by encoding the binary physical address value. For example, the encoder EN may generate data by encoding “0” in the physical address value into “01” and “1” in the physical address value into “10”.

FIG.7Aillustrates threshold voltage distributions of memory cells, according to an embodiment.

Referring toFIG.7A, the threshold voltage distribution of memory cells may be expressed as the number of memory cells with respect to a threshold voltage VT. Each memory cell may correspond to an SLC that stores data “1” or “0”. A memory cell storing data “1” may have a threshold voltage corresponding to a first threshold voltage range, and a memory cell storing data “0” may have a threshold voltage corresponding to a second threshold voltage range. The upper limit of the first threshold voltage range may be lower than a voltage level of a first voltage VL. The lower limit of the second threshold voltage range may be higher than the voltage level of the first voltage VL, and the upper limit of the second threshold voltage range may be lower than a voltage level of a second voltage VH.

FIG.7Billustrates a data search method according to an embodiment.

Referring toFIG.7B, data corresponding to an address value may be stored by using memory cells MCa and MCb connected in series to each other. For example, data “10” corresponding to address value “1” may be stored in the memory cells MCa and MCb by storing data “1” in the memory cell MCa and data “0” in the memory cell MCb. For example, data “01” corresponding to address value “0” may be stored in the memory cells MCa and MCb by storing data “0” in the memory cell MCa and data “1” in the memory cell MCb. For example, data “00” indicating no data may be stored in the memory cells MCa and MCb by storing data “0” in the memory cell MCa and data “0” in the memory cell MCb.

FIG.7Cis a table showing a current flow according to data stored in a memory cell, according to an embodiment.

Referring toFIGS.7B and7C, for example, to search for a logical address value LAV of 1 (i.e., “01”), the first voltage VLmay be applied to a word line connected to the memory cell MCa, and the second voltage VHmay be applied to a word line connected to the memory cell MCb. When the logical address value LAV stored in the memory cells MCa and MCb is 1 (i.e., “01”), current may flow through the memory cells MCa and MCb. On the other hand, when the logical address value LAV stored in the memory cells MCa and MCb is not 1 (i.e., not “01”), current may not flow through the memory cells MCa and MCb. For example, to search for a logical address value LAV of 0 (i.e., “00”), the second voltage VHmay be applied to a word line connected to the memory cell MCa, and the first voltage VLmay be applied to a word line connected to the memory cell MCb. When the logical address value LAV stored in the memory cells MCa and MCb is 0 (i.e., “00”), current may flow through the memory cells MCa and MCb. On the other hand, when the logical address value LAV stored in the memory cells MCa and MCb is not 0 (i.e., not “00”), current may not flow through the memory cells MCa and MCb. When the second voltage VHis applied to word lines respectively connected to the memory cells MCa and MCb, current may flow through the memory cells MCa and MCb regardless of the logical address value LAV stored in the memory cells MCa and MCb.

FIG.8illustrates a non-volatile memory80storing a logical address value and a physical address value, according to an embodiment.

Referring toFIG.8, the non-volatile memory80may store logical address values and physical address values. The non-volatile memory80may correspond to an example of the first non-volatile memory12inFIGS.1A and3Aor an example of the non-volatile memory40ofFIG.4. The non-volatile memory80may include a plurality of memory cells MC respectively in regions in which the word lines WL1 to WL8 intersect with bit lines BL1 to BL4.

For example, logical address values may be stored in first memory cells connected to a first group of the word lines WL1 to WL4, and physical address values may be stored in second memory cells connected to a second group of the word lines WL5 to WL8. For example, each of the first and second memory cells may correspond to an SLC. The numbers of word lines in the first group and first memory cells corresponding to a logical address value may vary with embodiments. The numbers of word lines in the second group and second memory cells corresponding to a physical address value may also vary with embodiments.

In an embodiment, the non-volatile memory80may include a plurality of cell strings, e.g., first to fourth cell strings CS1 to CS4, respectively connected to the bit lines BL1 to BL4. For example, the first to fourth cell strings CS1 to CS4 may be included in one memory block. However, embodiments are not limited thereto. The first to fourth cell strings CS1 to CS4 may be divided into a plurality of groups, which may be included in different memory blocks.

The first cell string CS1 may include first memory cells, which store the first logical address value L1 and are respectively connected to the word lines WL1 to WL4 in the first group, and second memory cells, which store the first physical address value P1 and are respectively connected to the word lines WL5 to WL8 in the second group. For example, the first logical address value L1 may be 0 and the first physical address value P1 may be 2. The second cell string CS2 may include first memory cells, which store the second logical address value L2 and are respectively connected to the word lines WL1 to WL4 in the first group, and second memory cells, which store the second physical address value P2 and are respectively connected to the word lines WL5 to WL8 in the second group. For example, the second logical address value L2 may be 2 and the second physical address value P2 may be 1.

The third cell string CS3 may include first memory cells, which store the third logical address value L3 and are respectively connected to the word lines WL1 to WL4 in the first group, and second memory cells, which store the third physical address value P3 and are respectively connected to the word lines WL5 to WL8 in the second group. For example, the third logical address value L3 may be 1 and the third physical address value P3 may be 3. The fourth cell string CS4 may include first memory cells, which store the fourth logical address value L4 and are respectively connected to the word lines WL1 to WL4 in the first group, and second memory cells, which store the fourth physical address value P4 and are respectively connected to the word lines WL5 to WL8 in the second group. For example, the fourth logical address value L4 may be 3 and the fourth physical address value P4 may be 0. The descriptions of the first to fourth cell strings CS1 to CS4 given above may also be applied to embodiments below.

In an embodiment, the non-volatile memory80may include a plurality of memory blocks and apply word line voltages corresponding to a logical address value to more than one of the memory blocks at the same time. Accordingly, an address search operation or an L2P operation may be performed in parallel on a plurality of memory blocks, and the time taken for the address search operation or the L2P operation may be reduced.

FIG.9illustrates a non-volatile memory90programmed with data corresponding to a logical address value and data corresponding to a physical address value, according to an embodiment.

Referring toFIGS.3A and9, first memory cells storing logical address values may be respectively implemented by first SLCs, and second memory cells storing physical address values may be respectively implemented by second SLCs. For example, the control logic42may generate data “0101” by encoding 0 corresponding to the first logical address value L1 and generate data “1001” by encoding 2 corresponding to the first physical address value P1. Accordingly, the first logical address value L1 may be stored as the data “0101” in first SLCs and the first physical address value P1 may be stored as the data “1001” in second SLCs. For example, the control logic42may generate data “1001” by encoding 2 corresponding to the second logical address value L2 and generate data “0110” by encoding 1 corresponding to the second physical address value P2. Accordingly, the second logical address value L2 may be stored as the data “1001” in first SLCs and the second physical address value P2 may be stored as the data “0110” in second SLCs.

For example, the control logic42may generate data “0110” by encoding 1 corresponding to the third logical address value L3 and generate data “1010” by encoding 3 corresponding to the third physical address value P3. Accordingly, the third logical address value L3 may be stored as the data “0110” in first SLCs and the third physical address value P3 may be stored as the data “1010” in second SLCs. For example, the control logic42may generate data “1010” by encoding 3 corresponding to the fourth logical address value L4 and generate data “0101” by encoding 0 corresponding to the fourth physical address value P4. Accordingly, the fourth logical address value L4 may be stored as the data “1010” in first SLCs and the fourth physical address value P4 may be stored as the data “0101” in second SLCs.

A physical address value search operation of the non-volatile memory90is described below. In an embodiment, the physical address value search operation of the non-volatile memory90may include a two-stage read operation. In detail, the two-stage read operation may include a first stage of searching for a cell string that stores a logical address value LAV and a second stage of reading a physical address value PAV from the found cell string.

In the first stage, to search for the cell string that stores the logical address value LAV received from the storage controller11, word lines voltages corresponding to the logical address value LAV may be applied to the word lines WL1 to WL4 in the first group, and accordingly, only first memory cells that store the logical address value LAV may be turned on. In an embodiment, a pass voltage may be applied to the word lines WL5 to WL8 in the second group, and accordingly, all of the second memory cells may be turned on regardless of data stored therein. Accordingly, current may flow only in the cell string that stores the logical address value LAV among the first to fourth cell strings CS1 to CS4, and the cell string storing the logical address value LAV may be found.

However, embodiments are not limited to those described above. In some embodiments, the word lines voltages corresponding to the logical address value LAV may be applied to the word lines WL1 to WL4 in the first group, but the pass voltage may not be applied to the word lines WL5 to WL8 in the second group. In a state where only the first memory cells storing the logical address value LAV are turned on, the voltage level of each of the bit lines BL1 to BL4 may be reduced by charge sharing. A cell string corresponding to a bit line having the reduced voltage level that is greater than or equal to a reference level among the bit lines BL1 to BL4 may be determined to be the cell string that stores the logical address value LAV. Alternatively, a cell string corresponding to a bit line having the greatest reduced voltage level among the bit lines BL1 to BL4 may be determined to be the cell string that stores the logical address value LAV.

In the second stage, a normal read operation may be performed only on the cell string that stores the logical address value LAV to read the physical address value PAV. In an embodiment, when only the bit line storing the logical address value LAV is activated, the physical address value PAV may be read from the second memory cells of the selected cell string. In an embodiment, when the cell string connected to the bit line having the reduced voltage level that is greater than or equal to the reference level is selected, only the cell string storing the logical address value LAV may be selected and a voltage may be applied to the bit line connected to the selected cell string. Cell strings that do not store the logical address value LAV are not selected, and accordingly, a voltage may not be applied to bit lines respectively connected to the unselected cell strings. As a result, power consumption caused by a read operation may be reduced. The physical address value read operation of a non-volatile memory is described in detail with reference toFIGS.10to13below.

The logical address value search operation of the non-volatile memory80may also include a two-stage read operation. In detail, the two-stage read operation may include a first stage of searching for a cell string that stores the physical address value PAV and a second stage of reading the logical address value LAV from the found cell string. The logical address value read operation of a non-volatile memory is described in detail with reference toFIG.14below.

FIG.10illustrates a read operation of a non-volatile memory100when the logical address value LAV is 0, according to an embodiment. For example, the non-volatile memory100may correspond to an example of the first non-volatile memory12inFIG.1A.

Referring toFIGS.3A and10, when the logical address value LAV received from the storage controller11is 0, the non-volatile memory100may encode the logical address value LAV “0” into data “0101”. Subsequently, to search for a cell string corresponding to the logical address value LAV “0”, word line voltages, i.e., VH, VL, VH, and VL, corresponding to the data “0101” may be respectively applied to the word lines WL1 to WL4 in the first group. First memory cells storing data “0” among first memory cells connected to the word line WL2 may be turned off, and first memory cells storing data “0” among first memory cells connected to the word line WL4 may be turned off. In addition, first memory cells storing the first logical address value L1 corresponding to the logical address value LAV “0” may be turned on, and accordingly, current may flow in the first cell string CS1, current may not flow in the second to fourth strings CS2 to CS4, and the first cell string CS1 may be selected as the cell string that stores the logical address value LAV.

Subsequently, a normal read operation may be performed on the second memory cells of the first cell string CS1 that has been selected. Read voltages applied to the word lines WL5 to WL8 in the second group may be changed, and data stored in the second memory cells of the selected first cell string CS1 may be read. The data read from the second memory cells of the first cell string CS1 may correspond to the first physical address value P1, e.g., 2, and may be stored in a first page buffer PB1. The first physical address value P1 stored in the first page buffer PB1 may be transmitted to the storage controller11.

The normal read operation performed on the second memory cells of the first cell string CS1 is described in detail below. In an embodiment, a read operation may be sequentially performed on the second memory cells respectively connected to the word lines WL5 to WL8 by sequentially applying a read voltage to the word lines WL5 to WL8, and data sequentially read from the second memory cells may be stored in the first page buffer PB1. The data stored in the first page buffer PB1 may be decoded into a physical address value, and the physical address value may be transmitted to the storage controller11.

For example, a read voltage may be applied to the word line WL5 so that data “1” may be read from the second memory cell connected to the word line WL5 and stored in the first page buffer PB1. Subsequently, a read voltage may be applied to the word line WL6 so that data “0” may be read from the second memory cell connected to the word line WL6 and stored in the first page buffer PB1. Subsequently, a read voltage may be applied to the word line WL7 so that data “0” may be read from the second memory cell connected to the word line WL7 and stored in the first page buffer PB1. Subsequently, a read voltage may be applied to the word line WL8 so that data “1” may be read from the second memory cell connected to the word line WL8 and stored in the first page buffer PB1. As described above, the data “1001” sequentially read from the second memory cells may be decoded into physical address value “2”. For example, the control logic42may receive the data “1001” from the first page buffer PB1, decode the data “1001” into the physical address value “2”, and transmit the physical address value “2” to the storage controller11.

However, embodiments are not limited to those described above. In some embodiments, a read operation may be performed on the second memory cells of the first to fourth cell strings CS1 to CS4 in units of pages, and a page buffer circuit102may store data of the entire page. For example, only the data stored in the first cell string CS1 that has been selected may be decoded into a physical address value, and the physical address value may be transmitted to the storage controller11.

In an embodiment, the non-volatile memory100may include a plurality of memory blocks and apply word lines voltages corresponding to data “0101” to more than one of the memory blocks at the same time, thereby reducing the time taken for searching for cell strings that store the logical address value LAV “0”.

FIG.11illustrates a read operation of the non-volatile memory100when the logical address value LAV is 2, according to an embodiment.

Referring toFIGS.3A and11, when the logical address value LAV received from the storage controller11is 2, the non-volatile memory100may encode the logical address value LAV “2” into data “1001”. Subsequently, to search for a cell string corresponding to the logical address value LAV “2”, word line voltages, i.e., VL, VH, VH, and VL, corresponding to the data “1001” may be respectively applied to the word lines WL1 to WL4 in the first group. First memory cells storing data “0” among first memory cells connected to the word line WL1 may be turned off, and first memory cells storing data “0” among first memory cells connected to the word line WL4 may be turned off. Moreover, first memory cells storing the second logical address value L2 corresponding to the logical address value LAV “2” may be turned on, and accordingly, current may flow in the second cell string CS2, current may not flow in the first, third and fourth strings CS1, CS3 and CS4, and the second cell string CS2 may be selected as the cell string that stores the logical address value LAV.

Subsequently, a normal read operation may be performed on the second memory cells of the second cell string CS2 that has been selected. Read voltages applied to the word lines WL5 to WL8 in the second group may be changed, and data stored in the second memory cells of the selected second cell string CS2 may be read. The data read from the second memory cells of the second cell string CS2 may correspond to the second physical address value P2, e.g.,1, and may be stored in a second page buffer PB2. The second physical address value P2 stored in the second page buffer PB2 may be transmitted to the storage controller11.

The normal read operation performed on the second memory cells of the second cell string CS2 is described in detail below. For example, a read voltage may be applied to the word line WL5 so that data “0” may be read from the second memory cell connected to the word line WL5 and stored in the second page buffer PB2. Subsequently, a read voltage may be applied to the word line WL6 so that data “1” may be read from the second memory cell connected to the word line WL6 and stored in the second page buffer PB2. Subsequently, a read voltage may be applied to the word line WL7 so that data “1” may be read from the second memory cell connected to the word line WL7 and stored in the second page buffer PB2. Subsequently, a read voltage may be applied to the word line WL8 so that data “0” may be read from the second memory cell connected to the word line WL8 and stored in the second page buffer PB2. As described above, the data “0110” sequentially read from the second memory cells may be decoded into physical address value “1”. For example, the control logic42may receive the data “0110” from the second page buffer PB2, decode the data “0110” into the physical address value “1”, and transmit the physical address value “1” to the storage controller11.

However, embodiments are not limited to those described above. In some embodiments, a read operation may be performed on the second memory cells of the first to fourth cell strings CS1 to CS4 in units of pages, and the page buffer circuit102may store data of the entire page. For example, only the data stored in the second cell string CS2 that has been selected may be decoded into a physical address value, and the physical address value may be transmitted to the storage controller11.

In an embodiment, the non-volatile memory100may include a plurality of memory blocks and apply word lines voltages corresponding to data “1001” to more than one of the memory blocks at the same time, thereby reducing the time taken for searching for cell strings that store the logical address value LAV “2”.

FIG.12illustrates a read operation of the non-volatile memory100when the logical address value LAV is 1, according to an embodiment.

Referring toFIGS.3A and12, when the logical address value LAV received from the storage controller11is 1, the non-volatile memory100may encode the logical address value LAV “1” into data “0110”. Subsequently, to search for a cell string corresponding to the logical address value LAV “1”, word line voltages, i.e., VH, VL, VL, and VH, corresponding to the data “0110” may be respectively applied to the word lines WL1 to WL4 in the first group. First memory cells storing data “0” among first memory cells connected to the word line WL2 may be turned off, and first memory cells storing data “0” among first memory cells connected to the word line WL3 may be turned off. First memory cells storing the third logical address value L3 corresponding to the logical address value LAV “1” may be turned on, and accordingly, current may flow in the third cell string CS3, current may not flow in the first, second and fourth strings CS1, CS2 and CS4, and the third cell string CS3 may be selected as the cell string that stores the logical address value LAV. Subsequently, a normal read operation may be performed on the second memory cells of the third cell string CS3 that has been selected. Read voltages applied to the word lines WL5 to WL8 in the second group may be changed, and data stored in the second memory cells of the selected third cell string CS3 may be read. The data read from the second memory cells of the third cell string CS3 may correspond to the third physical address value P3, e.g., 3, and may be stored in a third page buffer PB3. The third physical address value P3 stored in the third page buffer PB3 may be transmitted to the storage controller11.

The normal read operation performed on the second memory cells of the third cell string CS3 is described in detail below. For example, a read voltage may be applied to the word line WL5 so that data “1” may be read from the second memory cell connected to the word line WL5 and stored in the third page buffer PB3. Subsequently, a read voltage may be applied to the word line WL6 so that data “0” may be read from the second memory cell connected to the word line WL6 and stored in the third page buffer PB3. Subsequently, a read voltage may be applied to the word line WL7 so that data “1” may be read from the second memory cell connected to the word line WL7 and stored in the third page buffer PB3. Subsequently, a read voltage may be applied to the word line WL8 so that data “0” may be read from the second memory cell connected to the word line WL8 and stored in the third page buffer PB3. As described above, the data “1010” sequentially read from the second memory cells may be decoded into physical address value “3”. For example, the control logic42may receive the data “1010” from the third page buffer PB3, decode the data “1010” into the physical address value “3”, and transmit the physical address value “3” to the storage controller11.

However, embodiments are not limited to those described above. In some embodiments, a read operation may be performed on the second memory cells of the first to fourth cell strings CS1 to CS4 in units of pages, and the page buffer circuit102may store data of the entire page. For example, only the data stored in the third cell string CS3 that has been selected may be decoded into a physical address value, and the physical address value may be transmitted to the storage controller11.

In an embodiment, the non-volatile memory100may include a plurality of memory blocks and apply word lines voltages corresponding to data “0110” to more than one of the memory blocks at the same time, thereby reducing the time taken for searching for cell strings that store the logical address value LAV “1”.

FIG.13illustrates a read operation of the non-volatile memory100when the logical address value LAV is 3, according to an embodiment.

Referring toFIGS.3A and13, when the logical address value LAV received from the storage controller11is 3, the non-volatile memory100may encode the logical address value LAV “3” into data “1010”. Subsequently, to search for a cell string corresponding to the logical address value LAV “3”, word line voltages, i.e., VL, VH, VL, and VH, corresponding to the data “1010” may be respectively applied to the word lines WL1 to WL4 in the first group. For example, first memory cells storing data “0” among first memory cells connected to the word line WL1 and first memory cells connected to the word line WL3 may be turned off. First memory cells storing the fourth logical address value L4 may be turned on, and accordingly, current may flow in the fourth cell string CS4, current may not flow in the first to third strings CS1 to CS3, and the fourth cell string CS4 may be selected as the cell string that stores the logical address value LAV.

Subsequently, a normal read operation may be performed on the second memory cells of the fourth cell string CS4 that has been selected. Read voltages applied to the word lines WL5 to WL8 in the second group may be changed, and data stored in the second memory cells of the selected fourth cell string CS4 may be read. The data read from the second memory cells of the fourth cell string CS4 may correspond to the fourth physical address value P4, e.g., 0, and may be stored in a fourth page buffer PB4. The fourth physical address value P4 stored in the fourth page buffer PB4 may be transmitted to the storage controller11.

The normal read operation performed on the second memory cells of the fourth cell string CS4 is described in detail below. For example, a read voltage may be applied to the word line WL5 so that data “0” may be read from the second memory cell connected to the word line WL5 and stored in the fourth page buffer PB4. Subsequently, a read voltage may be applied to the word line WL6 so that data “1” may be read from the second memory cell connected to the word line WL6 and stored in the fourth page buffer PB4. Subsequently, a read voltage may be applied to the word line WL7 so that data “0” may be read from the second memory cell connected to the word line WL7 and stored in the fourth page buffer PB4. Subsequently, a read voltage may be applied to the word line WL8 so that data “1” may be read from the second memory cell connected to the word line WL8 and stored in the fourth page buffer PB4. As described above, the data “0101” sequentially read from the second memory cells may be decoded into physical address value “0”. For example, the control logic42may receive the data “0101” from the fourth page buffer PB4, decode the data “0101” into the physical address value “0”, and transmit the physical address value “0” to the storage controller11.

However, embodiments are not limited to those described above. In some embodiments, a read operation may be performed on the second memory cells of the first to fourth cell strings CS1 to CS4 in units of pages, and the page buffer circuit102may store data of the entire page. For example, only the data stored in the fourth cell string CS4 that has been selected may be decoded into a physical address value, and the physical address value may be transmitted to the storage controller11.

In an embodiment, the non-volatile memory100may include a plurality of memory blocks and apply word lines voltages corresponding to data “1010” to more than one of the memory blocks at the same time, thereby reducing the time taken for searching for cell strings that store the logical address value LAV “3”.

FIG.14illustrates a read operation of a non-volatile memory140when the physical address value PAV is 0, according to an embodiment. For example, the non-volatile memory140may correspond to an example of the second non-volatile memory13inFIG.1A.

Referring toFIGS.3A and14, when the physical address value PAV received from the storage controller11is 0, the non-volatile memory140may encode the physical address value PAV “0” into data “0101”. Subsequently, to search for a cell string corresponding to the physical address value PAV “0”, word line voltages, i.e., VH, VL, VH, and VL, corresponding to the data “0101” may be respectively applied to the word lines WL5 to WL8 in the second group. For example, second memory cells storing data “0” among second memory cells connected to the word line WL6 may be turned off, and second memory cells storing data “0” among second memory cells connected to the word line WL8 may be turned off. Second memory cells storing the fourth physical address value P4 corresponding to the physical address value PAV “0” may be turned on, and accordingly, current may flow in the fourth cell string CS4, current may not flow in the first to third strings CS1 to CS3, and the fourth cell string CS4 may be selected as the cell string that stores the physical address value PAV.

Subsequently, a normal read operation may be performed on the first memory cells of the fourth cell string CS4 that has been selected. For example, read voltages applied to the word lines WL1 to WL4 in the first group may be changed, and data stored in the first memory cells of the selected fourth cell string CS4 may be read. The data read from the first memory cells of the fourth cell string CS4 may correspond to the fourth logical address value L4, e.g., 3, and may be stored in the fourth page buffer PB4. The fourth logical address value L4 stored in the fourth page buffer PB4 may be transmitted to the storage controller11.

The normal read operation performed on the first memory cells of the fourth cell string CS4 is described in detail below. In an embodiment, a read operation may be sequentially performed on the first memory cells respectively connected to the word lines WL1 to WL4 by sequentially applying a read voltage to the word lines WL1 to WL4, and data sequentially read from the first memory cells may be stored in the fourth page buffer PB4. The data stored in the fourth page buffer PB4 may be decoded into a logical address value, and a decoded logical address value may be transmitted to the storage controller11.

For example, a read voltage may be applied to the word line WL1 so that data “1” may be read from the first memory cell connected to the word line WL1 and stored in the f fourth page buffer PB4. Subsequently, a read voltage may be applied to the word line WL2 so that data “0” may be read from the first memory cell connected to the word line WL2 and stored in the fourth page buffer PB4. Subsequently, a read voltage may be applied to the word line WL3 so that data “1” may be read from the first memory cell connected to the word line WL3 and stored in the fourth page buffer PB4. Subsequently, a read voltage may be applied to the word line WL4 so that data “0” may be read from the first memory cell connected to the word line WL4 and stored in the fourth page buffer PB4. As described above, the data “1001” sequentially read from the second memory cells may be decoded into physical address value “2”. For example, the control logic42may receive the data “1010” from the fourth page buffer PB4, decode the data “1010” into the logical address value “3”, and transmit the logical address value “3” to the storage controller11.

However, embodiments are not limited to those described above. In some embodiments, a read operation may be performed on the first memory cells of the first to fourth cell strings CS1 to CS4 in units of pages, and a page buffer circuit142may store data of the entire page. For example, only the data stored in the fourth cell string CS4 that has been selected may be decoded into a logical address value, and a decoded logical address value may be transmitted to the storage controller11.

FIG.15illustrates a non-volatile memory150storing user data, according to an embodiment.

Referring toFIG.15, the non-volatile memory150may include a memory cell array151, which stores user data and/or metadata, and a page buffer circuit152. The non-volatile memory150may correspond to an example of the second non-volatile memory13inFIGS.1A and3A. The non-volatile memory150may include a plurality of memory cells MC respectively in regions in which the word lines WL1 to WL8 intersect with the bit lines BL1 to BL4.

For example, when each memory cell MC is an SLC, each word line may correspond to a single page. For example, when each memory cell MC is an MLC, each word line may correspond to two pages. For example, when each memory cell MC is a triple-level cell (TLC), each word line may correspond to three pages. For example, when each memory cell MC is a quadruple-level cell (QLC), each word line may correspond to four pages.

Referring toFIGS.3A and15, the non-volatile memory150may receive the read command CMD_READ including a physical address value PAV from the storage controller11. For example, the physical address value PAV may correspond to the word line WL4 of the memory cell array151. In this regard, the word line WL4 may correspond to a selected word line WLsel, and the word lines WL1 to WL3 and WL5 to WL8 may correspond to unselected word lines. In response to the read command CMD_READ, the non-volatile memory150may perform a read operation on a selected page PAGE_sel connected to the word line WL4 corresponding to the selected word line WLsel. Data stored in the selected page PAGE_sel may be stored in the first to fourth page buffers PB1 to PB4. The data stored in the first to fourth page buffers PB1 to PB4 may be transmitted to the storage controller11.

FIG.16is a circuit diagram of a memory block BLK′ according to an embodiment.

Referring toFIG.16, the memory block BLK′ may correspond to a modification of the memory block BLK ofFIG.5, and the descriptions made with reference toFIG.5above may also be applied to the memory block BLK′. In an embodiment, the memory block BLK′ may include a plurality of logical address value storage regions R_LA1 to R_LA3 and a plurality of physical address value storage regions R_PA1 to R_PA3. For example, the logical address value storage regions R_LA1 to R_LA3 may include SLCs that store encoded data of a logical address value. For example, the physical address value storage regions R_PA1 to R_PA3 may include MLCs, TLCs, or QLCs, which store a physical address value.

For example, the logical address value storage region R_LA1 may include memory cells, which correspond to the first string select line SSL1 and are connected to the word lines WL1 to WL4, and the physical address value storage region R_PA1 may include memory cells, which correspond to the first string select line SSL1 and are connected to the word line WL5. For example, the logical address value storage region R_LA2 may include memory cells, which correspond to the second string select line SSL2 and are connected to the word lines WL1 to WL4, and the physical address value storage region R_PA2 may include memory cells, which correspond to the second string select line SSL2 and are connected to the word line WL5. For example, the logical address value storage region R_LA3 may include memory cells, which correspond to the third string select line SSL3 and are connected to the word lines WL1 to WL4, and the physical address value storage region R_PA3 may include memory cells, which correspond to the third string select line SSL3 and are connected to the word line WL5.

FIG.17illustrates a memory cell array171, which stores logical address values and physical address values, and a page buffer circuit172, according to an embodiment.

Referring toFIG.17, a non-volatile memory170may include the memory cell array171, which stores logical address values and physical address values, and the page buffer circuit172. For example, the non-volatile memory170may correspond to an example of the first non-volatile memory12inFIG.1A. The memory cell array171may include a plurality of cell strings, e.g., first to eighth cell strings CS1 to CS8, which are respectively connected to a plurality of bit lines BL1 to BL8. The page buffer circuit172may include a plurality of page buffers, e.g., first to eighth page buffers PB1 to PB8, which are respectively connected to the first to eighth cell strings CS1 to CS8.

Each of the first to eighth cell strings CS1 to CS8 may include first and second memory cells connected in series to each other. The first memory cells may be respectively connected to the word lines WL1 to WL4 in the first group and may store a logical address value. For example, the first memory cells may store encoded data of the logical address value. The second memory cell may be connected to the word line WL5 in the second group and may store a physical address value. For example, the second memory cell may store the physical address value as it is without being encoded. In an embodiment, the first memory cells may include SLCs, which each may store one bit of data. In an embodiment, second memory cells may include MLCs, which each may store at least two bits of data. For example, the second memory cells may include TLCs, but embodiments are not limited thereto.

The first to fourth cell strings CS1 to CS4 may store the first logical address value L1 and the first physical address value P1. The first logical address value L1 may be stored in first memory cells and duplicately stored in memory cells of the first to fourth cell strings CS1 to CS4. For example, the first memory cells of each of the first to fourth cell strings CS1 to CS4 may store encoded data of the first logical address value L1 “0”. The first physical address value P1 may be stored in the second memory cells of the first to fourth cell strings CS1 to CS4. For example, the second memory cells of the first to fourth cell strings CS1 to CS4 may store the first physical address value P1 “000000000010”.

The fifth to eighth cell strings CS5 to CS8 may store the second logical address value L2 and the second physical address value P2. The second logical address value L2 may be stored in first memory cells and duplicately stored in memory cells of the fifth to eighth cell strings CS5 to CS8. For example, the first memory cells of each of the fifth to eighth cell strings CS5 to CS8 may store encoded data of the second logical address value L2 “2”. The second physical address value P2 may be stored in the second memory cells of the fifth to eighth cell strings CS5 to CS8. For example, the second memory cells of the fifth to eighth cell strings CS5 to CS8 may store the second physical address value P2 “010110111110”.

Referring toFIGS.3A and17, in an embodiment, when a logical address value LAV received from the storage controller11is 0, the non-volatile memory170may encode the logical address value LAV “0” into data “0101”. Subsequently, to search for a cell string corresponding to the logical address value LAV “0”, word line voltages, i.e., VH, VL, VH, and VL, corresponding to the data “0101” may be respectively applied to the word lines WL1 to WL4 in the first group, and a pass voltage may be applied to the word line WL5 in the second group. In this case, current may flow in the first to fourth cell strings CS1 to CS4, and the first to fourth cell strings CS1 to CS4 may be selected as cell strings that store the logical address value LAV.

Subsequently, a normal read operation may be performed on the second memory cells of the first to fourth cell strings CS1 to CS4 that have been selected. For example, a read voltage may be applied to the word line WL5 in the second group so that data stored in the second memory cells of the selected first to fourth cell strings CS1 to CS4 may be read. The data read from the second memory cells of the first to fourth cell strings CS1 to CS4 may correspond to the first physical address value P1 and may be stored in the first to fourth page buffers PB1 to PB4. The first physical address value P1 stored in the first to fourth page buffers PB1 to PB4 may be transmitted to the storage controller11.

FIG.18illustrates a memory cell array181, which stores logical address values and physical address values, and a page buffer circuit182, according to an embodiment.

Referring toFIG.18, a non-volatile memory180may include the memory cell array181, which stores logical address values and physical address values, and the page buffer circuit182. For example, the non-volatile memory180may correspond to an example of the first non-volatile memory12inFIG.1A. The memory cell array181may include a plurality of cell strings, e.g., the first to eighth cell strings CS1 to CS8, which are respectively connected to the bit lines BL1 to BL8. The page buffer circuit182may include a plurality of page buffers, e.g., the first to eighth page buffers PB1 to PB8, which are respectively connected to the first to eighth cell strings CS1 to CS8. The non-volatile memory180may correspond to a modification of the non-volatile memory170ofFIG.17, and redundant descriptions thereof are omitted below.

Each of the first to eighth cell strings CS1 to CS8 may include first to fourth memory cells connected in series to one another. The first memory cells may be respectively connected to the word lines WL1 to WL4 in the first group and may store a logical address value, and the third memory cells may be respectively connected to word lines WL6 to WL9 in a third group and may store a logical address value. For example, the first memory cells may store encoded data of a logical address value, and the third memory cells may store encoded data of a logical address value. The second memory cell may be connected to the word line WL5 in the second group and may store a physical address value, and the fourth memory cell may be connected to a word line WL10 in a fourth group and may store a physical address value. For example, each of the second and fourth memory cells may store the physical address value as it is without being encoded. In an embodiment, the first and third memory cells may include SLCs, which each may store one bit of data. In an embodiment, the second and fourth memory cells may include MLCs, which each may store at least two bits of data. For example, the second and fourth memory cells may include TLCs, but embodiments are not limited thereto.

The first to fourth cell strings CS1 to CS4 may store the first logical address value L1, the first physical address value P1, the third logical address value L3, and the third physical address value P3. The third logical address value L3 may be stored in the third memory cells and duplicately stored in memory cells of the first to fourth cell strings CS1 to CS4. For example, the third memory cells of each of the first to fourth cell strings CS1 to CS4 may store encoded data of the third logical address value L3 “1”. The third physical address value P3 may be stored in the respective fourth memory cells of the first to fourth cell strings CS1 to CS4. For example, the respective fourth memory cells of the first to fourth cell strings CS1 to CS4 may store the third physical address value P3 “000000000010”.

The fifth to eighth cell strings CS5 to CS8 may store the second logical address value L2, the second physical address value P2, the fourth logical address value L4, and the fourth physical address value P4. The fourth logical address value L4 may be stored in the third memory cells and duplicately stored in memory cells of the fifth to eighth cell strings CS5 to CS8. For example, the third memory cells of each of the fifth to eighth cell strings CS5 to CS8 may store encoded data of the fourth logical address value L4 “3”. The fourth physical address value P4 may be stored in the respective fourth memory cells of the fifth to eighth cell strings CS5 to CS8. For example, the respective fourth memory cells of the fifth to eighth cell strings CS5 to CS8 may store the fourth physical address value P4 “010110111110”.

Referring toFIGS.3A and18, in an embodiment, when a logical address value LAV received from the storage controller11is 1, the non-volatile memory180may encode the logical address value LAV “1” into data “0110”. Subsequently, to search for a cell string corresponding to the logical address value LAV “1”, word line voltages, i.e., VH, VL, VL, and VH, corresponding to the data “0110” may be respectively applied to the word lines WL6 to WL9 in the third group, and a pass voltage may be applied to the word lines WL1 to WL4 in the first group, the word line WL5 in the second group, and the word line WL10 in the fourth group. In this case, current may flow in the first to fourth cell strings CS1 to CS4, and the first to fourth cell strings CS1 to CS4 may be selected as cell strings that store the logical address value LAV.

Subsequently, a normal read operation may be performed on the fourth memory cells of the first to fourth cell strings CS1 to CS4 that have been selected. For example, a read voltage may be applied to the word line WL10 in the fourth group so that data stored in the fourth memory cells of the selected first to fourth cell strings CS1 to CS4 may be read. The data read from the fourth memory cells of the first to fourth cell strings CS1 to CS4 may correspond to the third physical address value P3 and may be stored in the first to fourth page buffers PB1 to PB4. The third physical address value P3 stored in the first to fourth page buffers PB1 to PB4 may be transmitted to the storage controller11.

FIG.19illustrates a memory cell array191, which stores logical address values and physical address values, and a page buffer circuit192, according to an embodiment.

Referring toFIG.19, a non-volatile memory190may include the memory cell array191, which stores logical address values and physical address values, and the page buffer circuit192. For example, the non-volatile memory190may correspond to an example of the first non-volatile memory12inFIG.1A. The memory cell array191may include a plurality of cell strings, e.g., the first to eighth cell strings CS1 to CS8, which are respectively connected to the bit lines BL1 to BL8. The page buffer circuit192may include a plurality of page buffers, e.g., the first to eighth page buffers PB1 to PB8, which are respectively connected to the first to eighth cell strings CS1 to CS8.

Each of the first to eighth cell strings CS1 to CS8 may include first to fourth memory cells connected in series to one another. The first memory cells may be respectively connected to the word lines WL1 to WL4 in the first group and may store encoded data of a logical address value. The second memory cell may be connected to the word line WL5 in the second group and may store a physical address value. The third memory cells may be respectively connected to the word lines WL6 to WL9 in the third group and may store encoded data of a logical address value. The fourth memory cell may be connected to the word line WL10 in the fourth group and may store a physical address value. In an embodiment, the first and third memory cells may include SLCs, which each may store one bit of data. In an embodiment, the second and fourth memory cells may include MLCs, which each may store at least two bits of data. For example, the second and fourth memory cells may include TLCs, but embodiments are not limited thereto.

The first and second cell strings CS1 and CS2 may store the first logical address value L1 and the first physical address value P1. The first logical address value L1 may be stored in the first and third memory cells and duplicately stored in memory cells of the first and second cell strings CS1 and CS2. For example, the first memory cells of each of the first and second cell strings CS1 and CS2 may store encoded data “0101” of the first logical address value L1 “0”, and the third memory cells of each of the first and second cell strings CS1 and CS2 may store the encoded data “0101” of the first logical address value L1 “0”. The first physical address value P1 may be stored in the second and fourth memory cells of the first and second cell strings CS1 and CS2. For example, the respective second memory cells of the first and second cell strings CS1 and CS2 may store the first physical address value P1 “2”, and the respective fourth memory cells of the first and second cell strings CS1 and CS2 may store the first physical address value P1 “2”.

The third and fourth cell strings CS3 and CS4 may store the second logical address value L2 and the second physical address value P2. In detail, the second logical address value L2 may be stored in the first and third memory cells and duplicately stored in memory cells of the third and fourth cell strings CS3 and CS4. For example, the first memory cells of each of the third and fourth cell strings CS3 and CS4 may store encoded data “0110” of the second logical address value L2 “1”, and the third memory cells of each of the third and fourth cell strings CS3 and CS4 may store the encoded data “0110” of the second logical address value L2 “1”. The second physical address value P2 may be stored in the second and fourth memory cells of the third and fourth cell strings CS3 and CS4. For example, the respective second memory cells of the third and fourth cell strings CS3 and CS4 may store the second physical address value P2 “3”, and the respective fourth memory cells of the third and fourth cell strings CS3 and CS4 may store the second physical address value P2 “3”.

Memory cells of the fifth and sixth cell strings CS5 and CS6 may store the third logical address value L3 and the third physical address value P3. In detail, the third logical address value L3 may be stored in the first and third memory cells and duplicately stored in memory cells of the fifth and sixth cell strings CS5 and CS6. For example, the first memory cells of each of the fifth and sixth cell strings CS5 and CS6 may store encoded data “1001” of the third logical address value L3 “2”, and the third memory cells of each of the fifth and sixth cell strings CS5 and CS6 may store the encoded data “1001” of the third logical address value L3 “2”. The third physical address value P3 may be stored in the second and fourth memory cells of the fifth and sixth cell strings CS5 and CS6. For example, the respective second memory cells of the fifth and sixth cell strings CS5 and CS6 may store the third physical address value P3 “1”, and the respective fourth memory cells of the fifth and sixth cell strings CS5 and CS6 may store the third physical address value P3 “1”.

Memory cells of the seventh and eighth cell strings CS7 and CS8 may store the fourth logical address value L4 and the fourth physical address value P4. In detail, the fourth logical address value L4 may be stored in the first and third memory cells and duplicately stored in memory cells of the seventh and eighth cell strings CS7 and CS8. For example, the first memory cells of each of the seventh and eighth cell strings CS7 and CS8 may store encoded data “1010” of the fourth logical address value L4 “3”, and the third memory cells of each of the seventh and eighth cell strings CS7 and CS8 may store the encoded data “1010” of the fourth logical address value L4 “3”. The fourth physical address value P4 may be stored in the second and fourth memory cells of the seventh and eighth cell strings CS7 and CS8. For example, the respective second memory cells of the seventh and eighth cell strings CS7 and CS8 may store the fourth physical address value P4 “0”, and the respective fourth memory cells of the seventh and eighth cell strings CS7 and CS8 may store the fourth physical address value P4 “0”.

Referring toFIGS.3A and19, in an embodiment, when a logical address value LAV received from the storage controller11is 0, the non-volatile memory190may generate data “0101” from the logical address value LAV “0”. Subsequently, to search for a cell string corresponding to the logical address value LAV “0”, word line voltages, i.e., VH, VL, VH, and VL, corresponding to the data “0101” may be applied to the word lines WL1 to WL4, respectively, in the first group and the word lines WL6 to WL9, respectively, in the third group, and a pass voltage may be applied to the word line WL5 in the second group and the word line WL10 in the fourth group. In this case, current may flow in the first and second cell strings CS1 and CS2, and the first and second cell strings CS1 and CS2 may be selected as cell strings that store the logical address value LAV.

Subsequently, a normal read operation may be performed on the second and fourth memory cells of the first and second cell strings CS1 and CS2 that have been selected. For example, a read voltage may be applied to the word line WL5 in the second group and the word line WL10 in the fourth group so that data stored in the second and fourth memory cells of the selected first and second cell strings CS1 and CS2 may be read. The data read from the second and fourth memory cells of the first and second cell strings CS1 and CS2 may correspond to the first physical address value P1, e.g., 2, and may be stored in the first and second page buffers PB1 and PB2. The first physical address value P1 stored in the first and second page buffers PB1 and PB2 may be transmitted to the storage controller11.

FIG.20illustrates a memory cell array201, which stores logical address values and physical address values, and a page buffer circuit202, according to an embodiment.

Referring toFIG.20, a non-volatile memory200may include the memory cell array201, which stores logical address values, physical address values, and validity information, and the page buffer circuit202. For example, the non-volatile memory200may correspond to an example of the first non-volatile memory12inFIG.1A. Here, the validity information may indicate the invalidity or validity of the mapping relationship between a logical address and a physical address. For example, when a physical address corresponding to a logical address is changed, the mapping relationship between the logical address and the physical address may be invalid. For example, when a physical address corresponding to a logical address is not changed, the mapping relationship between the logical address and the physical address may be valid.

Each of the first to eighth cell strings CS1 to CS8 may include first to third memory cells connected in series to one another. The first memory cells may be respectively connected to the word lines WL1 to WL4 in the first group and may store encoded data of a logical address value. The second memory cells may be respectively connected to the word lines WL5 to WL8 in the second group and may store encoded data of a physical address value. The third memory cells may be respectively connected to the word lines WL9 and WL10 in the third group and store validity information. For example, when the third memory cells respectively connected to the word lines WL9 and WL10 in the third group are programmed to “10”, the validity information may indicate “invalid”. For example, when the third memory cells respectively connected to the word lines WL9 and WL10 in the third group are programmed to “01”, the validity information may indicate “valid”. For example, when the third memory cells respectively connected to the word lines WL9 and WL10 in the third group are programmed to “11”, the validity information may indicate “free”. For example, when the third memory cells respectively connected to the word lines WL9 and WL10 in the third group are programmed to “00”, the validity information may indicate “no data”. In an embodiment, the first to third memory cells may include SLCs, which each may store one bit of data. However, embodiments are not limited thereto. At least one of the first to third memory cells may include MLCs, which each may store at least two bits of data.

For example, the second cell string CS2 may include first memory cells storing the second logical address value L2, second memory cells storing the second physical address value P2, and third memory cells storing validity information12, which indicates whether the mapping relationship between a second logical address and a second physical address is invalid. For example, when the second physical address mapped to the second logical address is changed from 3, which is the second physical address value P2, to another physical address value, the current mapping relationship between the second logical address and the second physical address will be invalid, and the third memory cells may be programmed to “10” indicating the invalidity of the mapping relationship.

For example, the fourth cell string CS4 may include first memory cells storing the fourth logical address value L4, second memory cells storing the fourth physical address value P4, and third memory cells storing validity information14, which indicates whether the mapping relationship between a fourth logical address and a fourth physical address is invalid. For example, when the fourth physical address mapped to the fourth logical address is maintained as 0, which is the fourth physical address value P4, the current mapping relationship between the fourth logical address and the fourth physical address will be valid, and the third memory cells may be programmed to “01” indicating the validity of the mapping relationship.

Referring toFIGS.3A and20, the non-volatile memory200may search for a cell string storing a logical address value corresponding to a logical address value LAV received from the storage controller11and perform a read operation on the second memory cells of a found cell string, thereby reading a physical address value. For example, when the logical address value LAV is 4, the found cell string may be the fifth cell string CS5. For example, the non-volatile memory200may check validity information in the third memory cells of the fifth cell string CS5 and transmit physical information stored in the fifth cell string CS5 to the storage controller11.

However, embodiments are not limited thereto. In some embodiments, validity information may be represented without using third memory cells. For example, invalidity may be indicated by programming first memory cells, which store encoded data of a logical address value, to “11”. For example, invalidity may be indicated by programming a first memory cell, which stores a logical address value, to a program state that is higher than the highest program state.

FIG.21illustrates a memory cell array including memory blocks211and212, which store logical address values and physical address values, and a page buffer circuit213, according to an embodiment.

Referring toFIG.21, a non-volatile memory210may include the memory block211, which stores the first to fourth logical address values L1 to L4 and the first to fourth physical address values P1 to P4, and the memory block212, which stores fifth to eighth logical address values L5 to L8 and fifth to eighth physical address values P5 to P8. For example, updated information in the L2P mapping data D1 inFIG.2may be stored in the new memory block212. However, embodiments are not limited thereto. The updated information in the L2P mapping data D1 may be stored in the old memory block211. For example, a physical address value mapped to logical address “0” may be updated from 2 to 6. For example, the mapping relationship between logical address “0” and physical address “2” may be changed into the mapping relationship between the logical address “0” and physical address “6”, the first cell string CS1 storing the logical address “0” and the physical address “2” may be changed into an invalid string, and the eighth cell string CS8 storing the logical address “0” and the physical address “6” may be updated in the L2P mapping data D1.

FIG.22is a block diagram of a storage device10A according to an embodiment.

Referring toFIG.22, the storage device10A may include the storage controller11, a buffer chip14, a first non-volatile memory12A, and a plurality of second non-volatile memories13A. The storage device10A may correspond to a modification of the storage device10ofFIG.3A. The descriptions made with reference toFIGS.2to21above may also be applied to the storage device10A, and redundant descriptions thereof are omitted below. The storage controller11may be substantially similar to the storage controller11inFIG.3A. The first non-volatile memory12A may include the memory cell array122and the page buffer circuit123, and each of the second non-volatile memories13A may include the memory cell array132and the page buffer circuit133. According to an embodiment, the first non-volatile memory12A may be implemented by a plurality of memory chips, memory dies, or memory planes.

The buffer chip14may be connected between the storage controller11and each of the first and second non-volatile memories12A and13A, and may be referred to as a frequency boosting interface (FBI) chip. The buffer chip14may be connected to the storage controller11through a first channel. The buffer chip14may receive a read request and a logical address, e.g., an LBA, from the storage controller11through the first channel and transmit data to the storage controller11through the first channel. The buffer chip14may be connected to the first non-volatile memory12A through a second channel. The buffer chip14may transmit a logical address value LAV to the first non-volatile memory12A through the second channel and receive a physical address value PAV from the first non-volatile memory12A through the second channel. The buffer chip14may be connected to the second non-volatile memories13A through a third channel. The buffer chip14may transmit the read command CMD_READ including a physical address to the second non-volatile memories13A through the third channel and receive data from the second non-volatile memories13A through the third channel.

The buffer chip14may include a decoder14a. The decoder14amay receive a read request, which includes a logical address, e.g., an LBA, from the storage controller11. In response to the read request including the LBA, the decoder14amay select the first non-volatile memory12A, which stores L2P mapping data, among the first non-volatile memory12A and the second non-volatile memories13A. In an embodiment, the decoder14amay transmit the logical address value LAV, which corresponds to the logical address received from the storage controller11, to the first non-volatile memory12A. In an embodiment, the decoder14amay encode the logical address value LAV corresponding to the logical address received from the storage controller11, thereby generating data corresponding to the logical address, and may transmit the data to the first non-volatile memory12A.

The first non-volatile memory12A may include the memory cell array122, which stores logical address values LAVs and physical address values PAVs, and the page buffer circuit123. In an embodiment, the memory cell array122may store encoded data corresponding to each of the logical address values LAVs. In an embodiment, the memory cell array122may store encoded data corresponding to each of the physical address values PAVs. In an embodiment, the first non-volatile memory12A may receive the logical address value LAV from the buffer chip14, generate data by encoding the logical address value LAV, search for a cell string storing the data, and read a physical address value PAV from a found cell string. In an embodiment, the first non-volatile memory12A may receive data corresponding to the logical address value LAV from the buffer chip14, search for a cell string storing the data, and read a physical address value PAV from a found cell string.

In response to the physical address value PAV received from the first non-volatile memory12A, the buffer chip14may select one of the second non-volatile memories13A. Subsequently, the buffer chip14may transmit, to the selected second non-volatile memory13A, the read command CMD_READ including the physical address value PAV. The selected second non-volatile memory13A may perform a read operation on at least one page corresponding to the physical address value PAV in response to the read command CMD_READ and transmit read data to the buffer chip14. For example, the read data may include the user data DATA_U and/or the metadata DATA_M. The buffer chip14may transmit, to the storage controller11, the data received from the selected second non-volatile memory13A.

In an embodiment, the buffer chip14and the first and second non-volatile memories12A and13A may be implemented in a single package, and may be referred to as a memory device or a non-volatile memory device. For example, the first non-volatile memory12A and the second non-volatile memories13A may be implemented in separate memory chips, and the buffer chip14, the first non-volatile memory12A, and the second non-volatile memories13A may be connected to one another by wire bonding in one package. For example, the first non-volatile memory12A and the second non-volatile memories13A may be implemented by a stack package having a stack structure.

FIG.23is a flowchart of an operating method of a storage device, according to an embodiment.

Referring toFIG.23, the operating method of a storage device may be performed by, for example, the storage device10inFIG.1Aand may correspond to a method of performing a read operation in response to a read request from a host. The descriptions made with reference toFIGS.1A to22above may also be applied to the current embodiment, and redundant descriptions thereof are omitted below.

The storage device10may receive the read request REQ_READ including a logical address from the host20in operation S110. The storage controller11may transmit the logical address to the first non-volatile memory12in operation S120. The first non-volatile memory12may search for a physical address corresponding to the logical address in operation S130. The storage controller11may transmit, to the second non-volatile memory13, a read command including the physical address in operation S140. The second non-volatile memory13may read data based on the physical address in operation S150. The storage controller11may transmit the data to the host20in operation S160.

FIG.24illustrates operating methods of a host, a storage controller, a first non-volatile memory, and a second non-volatile memory, according to an embodiment.

Referring toFIG.24, the host20may issue a read request including a logical address, e.g., an LBA, in operation S200. The host20may transmit the read request including the LBA to the storage controller11in operation S210. The storage controller11may transmit the LBA to the first non-volatile memory12in operation S220. The first non-volatile memory12may perform a read operation to search for a physical address, e.g., a PBA, which corresponds to the LBA, in operation S230. The first non-volatile memory12may transmit the PBA to the storage controller11in operation S240.

The storage controller11may issue a read command including the PBA in operation S250. The storage controller11may transmit a read command including the PBA to the second non-volatile memory13in operation S260. The second non-volatile memory13may perform a read operation based on the PBA in operation S270. The second non-volatile memory13may transmit data, which has been read, to the storage controller11in operation S280. The storage controller11may transmit the data to the host20in operation S290.

FIG.25is a flowchart of an operating method of a non-volatile memory device, according to an embodiment.

Referring toFIG.25, the operating method of a non-volatile memory device may correspond to a method of performing, by the non-volatile memory device, an address search operation on a non-volatile memory, which stores logical address values and physical address values, and may be performed on, for example, the first non-volatile memory12inFIGS.1A and3Aor the first non-volatile memory12A inFIG.22. The descriptions made with reference toFIGS.1A to22above may also be applied to the current embodiment, and redundant descriptions thereof are omitted below.

The non-volatile memory device may receive a logical address value in operation S310. For example, the non-volatile memory device may receive the logical address value from a memory controller or a buffer chip. The non-volatile memory device may generate data by encoding the logical address value and searching for a cell string storing the logical address value by applying, to word lines in a first group, word line voltages based on the data in operation S320. The non-volatile memory device may perform a normal read operation on a found cell string to read a physical address value in operation S330. The non-volatile memory device may transmit the physical address value in operation S340. For example, the non-volatile memory device may transmit the physical address value to the memory controller or the buffer chip.

FIG.26is a flowchart of an operating method of a non-volatile memory device, according to an embodiment.

Referring toFIG.26, the operating method of a non-volatile memory device may correspond to a method of performing, by the non-volatile memory device, an address search operation on a non-volatile memory, which stores logical address values and physical address values, and may be performed on, for example, the first non-volatile memory12inFIGS.1A and3Aor the first non-volatile memory12A inFIG.22. The descriptions made with reference toFIGS.1A to22above may also be applied to the current embodiment, and redundant descriptions thereof are omitted below.

The non-volatile memory device may receive a physical address value in operation S410. For example, the non-volatile memory device may receive the physical address value from a memory controller or a buffer chip. The non-volatile memory device may generate data by encoding the physical address value and searching for a cell string storing the physical address value by applying, to word lines in a first group, word line voltages based on the data in operation S420. The non-volatile memory device may perform a normal read operation on a found cell string to read a logical address value in operation S430. The non-volatile memory device may transmit the logical address value in operation S440. For example, the non-volatile memory device may transmit the logical address value to the memory controller or the buffer chip.

FIG.27illustrates operating methods of a storage controller, a buffer chip, a first non-volatile memory, and a second non-volatile memory, according to an embodiment.

Referring toFIG.27, the storage controller11may receive a read request including a logical address, e.g., an LBA, in operation S500. The storage controller11may transmit the read request including the LBA to the buffer chip14in operation S510. The buffer chip14may generate a logical address value LAV from the LBA in operation S520. The buffer chip may transmit the logical address value LAV to the first non-volatile memory12A in operation S525. The first non-volatile memory12A may perform a read operation to search for a physical address value PAV corresponding to the logical address value LAV in operation S530. The first non-volatile memory12A may transmit the physical address value PAV to the buffer chip14in operation S540.

The buffer chip14may issue a read command including the physical address value PAV in operation S550. The buffer chip may transmit, to the second non-volatile memory13A, the read command including the physical address value PAV in operation S560. The second non-volatile memory13A may perform a read operation based on the physical address value PAV in operation S570. The second non-volatile memory13A may transmit data, which has been read, to the buffer chip14in operation580. The buffer chip14may transmit the data to the storage controller11in operation S585. The storage controller11may transmit the data to the host20in operation S590.

FIG.28is a diagram of a system1000to which a storage device is applied, according to an embodiment. The system1000ofFIG.28may be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of things (IoT) device. However, the system1000ofFIG.28is not necessarily limited to the mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (e.g., a navigation device).

Referring toFIG.28, the system1000may include a main processor1100, memories (e.g.,1200aand1200b), and storage devices (e.g.,1300aand1300b). In addition, the system1000may include at least one of an image capturing device1410, a user input device1420, a sensor1430, a communication device1440, a display1450, a speaker1460, a power supplying device1470, and a connecting interface1480.

The main processor1100may control all operations of the system1000, more specifically, operations of other components included in the system1000. The main processor1100may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor1100may include at least one CPU core1110and further include a controller1120configured to control the memories1200aand1200band/or the storage devices1300aand1300b. In some embodiments, the main processor1100may further include an accelerator1130, which is a dedicated circuit for a high-speed data operation, such as an artificial intelligence (AI) data operation. The accelerator1130may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and be implemented as a chip that is physically separate from the other components of the main processor1100.

The memories1200aand1200bmay be used as main memory devices of the system1000. Although each of the memories1200aand1200bmay include a volatile memory, such as SRAM and/or DRAM, each of the memories1200aand1200bmay include non-volatile memory, such as a flash memory, PRAM, and/or RRAM. The memories1200aand1200bmay be implemented in the same package as the main processor1100.

The storage devices1300aand1300bmay serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have larger storage capacity than the memories1200aand1200b. The storage devices1300aand1300bmay respectively include storage controllers (STRG CTRL)1310aand1310band non-volatile memories1320aand1320bconfigured to store data via the control of the storage controllers1310aand1310b. Although the non-volatile memories1320aand1320bmay include flash memories having a 2D structure or a 3D V-NAND structure, the NVMs1320aand1320bmay include other types of NVMs, such as PRAM and/or RRAM.

The storage devices1300aand1300bmay be physically separated from the main processor1100and included in the system1000or implemented in the same package as the main processor1100. In addition, the storage devices1300aand1300bmay have types of solid-state devices (SSDs) or memory cards and be removably combined with other components of the system100through an interface, such as the connecting interface1480that will be described below. The storage devices1300aand1300bmay be devices to which a standard protocol, such as a UFS, an eMMC, or a non-volatile memory express (NVMe), is applied, without being limited thereto.

The image capturing device1410may capture still images or moving images. The image capturing device1410may include a camera, a camcorder, and/or a webcam.

The user input device1420may receive various types of data input by a user of the system1000and include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor1430may detect various types of physical quantities, which may be obtained from the outside of the system1000, and convert the detected physical quantities into electric signals. The sensor1430may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device1440may transmit and receive signals between other devices outside the system1000according to various communication protocols. The communication device1440may include an antenna, a transceiver, and/or a modem.

The display1450and the speaker1460may serve as output devices configured to respectively output visual information and auditory information to the user of the system1000.

The power supplying device1470may appropriately convert power supplied from a battery embedded in the system1000and/or an external power source, and supply the converted power to each of components of the system1000.

The connecting interface1480may provide connection between the system1000and an external device, which is connected to the system1000and capable of transmitting and receiving data to and from the system1000. The connecting interface1480may be implemented by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, a universal serial bus (USB) interface, a secure digital (SD) card interface, an MMC interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

In some embodiments, each of the components represented by a block as illustrated inFIGS.1A,1B,3A,3B,4and22may be implemented as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to example embodiments. For example, at least one of these components may include various hardware components including a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), transistors, capacitors, logic gates, or other circuitry using use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc., that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components may include a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Also, at least one of these components may further include or may be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Functional aspects of example embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements, modules or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.

While aspects of example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.