Patent ID: 12232260

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments will be described in detail with reference to the attached drawings. The present invention may be embodied in many different forms, and should not be construed as limited to the exemplary embodiments set forth herein.

Like reference numerals may designate like elements throughout the specification. In the flowcharts described with reference to the drawings in this specification, the operation order may be changed, various operations may be merged, certain operations may be divided into multiple operations, and certain operations might not be performed.

In the drawings, various thicknesses, lengths, and angles are shown and while the arrangement shown does indeed represent an embodiment, it is to be understood that modifications of the various thicknesses, lengths, and angles may be possible within the spirit and scope and the present invention is not necessarily limited to the particular thicknesses, lengths, and angles shown.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present between the element and the other element. The word “on” or “above” means positioned on or below the object portion, and does not necessarily mean positioned on the upper side of the object portion based on a gravitational direction.

The phrase “on a plane” means viewing the object portion from the top unless indicated otherwise, and the phrase “on a cross-section” means viewing a cross-section of which the object portion is vertically cut from the side.

An electronic device and a method for manufacturing the same according to an embodiment will now be described with reference to accompanying drawings.

FIG.1shows a plan layout view of components of an electronic device according to an embodiment.

Referring toFIG.1, the electronic device10includes a base substrate100, a plurality of semiconductor chips200attached to the base substrate100, and an input/output portion300.

According to an embodiment, the base substrate100may be a printed circuit board PCB. For example, the base substrate100may be a multilayered PCB. A plurality of conductive patterns410and420may be disposed on the base substrate100. For example, conductive patterns410and420may be positioned on one side and/or both sides of layers in the base substrate100. According to an embodiment, the conductive patterns410and420may be disposed on an upper side and/or a lower side of the base substrate100.

The semiconductor chips200may be mounted on the base substrate100. For example, a plurality of semiconductor chips200may be mounted on the base substrate100by using wires, lead frames, and/or solder balls. The semiconductor chips200may be spaced from each other. The semiconductor chips200may be electrically connected to the conductive patterns410and420of the base substrate100.

The semiconductor chips200may include a plurality of memory semiconductor chips210and at least one controller chip220.

The memory semiconductor chips210may be volatile memory devices and/or non-volatile memory devices. The volatile memory devices may, for example, be dynamic RAMs (DRAM), static RAMs (SRAM), synchronous DRAMs (SDRAM), double data rates (DDR) RAMs, or Rambus DRAMs (RDRAM), and the present invention is not limited thereto. The non-volatile memory devices may be flash memories, phase-change RAMs (PRAM), resistive RAMs (RRAM), ferroelectric RAMs (FeRAM), or magnetic RAMs (MRAM), and the present invention is not limited thereto. The flash memories may, for example, be NAND flash memories. The flash memories may, for example, be V-NAND flash memories. The non-volatile memory devices may be made of a semiconductor die, or may be a stack of multiple semiconductor dies.

The controller chip220may control the memory semiconductor chips210. For example, a controller may be installed in the controller chip220. The controller may control access to data stored in the memory semiconductor chips210. The controller may control access to the memory cell of the memory semiconductor chips210and writing and/or reading operations according to signal (e.g., commands (CMD), addresses (ADD), control signals, and clock signals) transmitted from an external host. The controller may be configured with an application specific integrated circuit (ASIC). For example, when the electronic device10is connected to the external host, the controller may be designed to be automatically executed by an operating system of the external host.

The controller chip220may be a buffer chip such as a register clock driver (RCD). The buffer chip may buffer the signal (e.g., commands (CMD), addresses (ADD), control signals, and clock signals) transmitted from the external host and may provide the same to the memory semiconductor chips210.

The controller chip220may include data buffers that are connected to corresponding memory semiconductor chips210. The data buffer may buffer data input/output signals that are input/output to/from the memory semiconductor chips210. The data buffers may be positioned between the memory semiconductor chips210and the input/output portion300.

The input/output portion300may include a plurality of input/output terminals310. The input/output portion300is shown to be a connector, and is not limited thereto. The input/output terminals310may transmit/receive electrical signals (e.g., commands (CMD), addresses (ADD), control signals, dock signals, data signals (DQ), data strobe signals (DQS), etc.,) to/from an external device. For example, one side of the input/output terminals310may be inserted into a mother board socket and may be electrically connected to the mother board. Another side of the input/output terminals310may be electrically connected to the conductive patterns410and420of the base substrate100. The input/output terminals310may be directly connected to a mother board slot, and may be directly/indirectly connected to the conductive patterns410and420of the base substrate100. Commands/address signal input pins, no connection pins, and data input/output signal pins may be allocated to the input/output terminals310.

The conductive patterns410may electrically connect spaces among the semiconductor chips200, and the conductive patterns420may electrically connect spaces among the input/output terminals310and the semiconductor chips200. For example, the conductive patterns410may electrically connect semiconductor chips200to each other, and the conductive patterns420may electrically connect input/output terminals310to corresponding semiconductor chips200.

As the conductive patterns410and420are positioned on internal layers of the base substrate100, the conductive patterns410and420are connected to the semiconductor chip200and/or the input/output terminals310through vias. For example, the semiconductor chip200may be electrically connected to the conductive patterns410and420through conductive vias320and322penetrating part of the base substrate100. The input/output terminal310may be electrically connected to the conductive pattern420through conductive vias324and326penetrating part of the base substrate100. For example, an input/output end of the memory semiconductor chip210is connected to a pad connected to the conductive via326, and the input/output terminal310is connected to the conductive via324so the input/output end of the memory semiconductor chip210and the input/output terminal310may be electrically connected to the conductive pattern420.

There may be a problem in that the via stub, which remains after the conductive vias320,322,324, and326are connected to the conductive patterns410and420, acts as a capacitor for a high-frequency signal, causing signal reflection, and reducing a channel bandwidth.

Compared to this, open stubs are included in the conductive patterns410and420of the electronic device according to an embodiment of the present inventive concept. The conductive patterns410and420may configure a low pass filter LPF by the open stubs and the via stubs. For example, by forming the open stubs, influences caused by the via stubs may be removed, and signal transmission characteristics in a low frequency bandwidth may be improved.

The conductive patterns410and420with a 3rd-order low pass filter will now be described in detail with reference toFIG.2toFIG.4.

FIG.2shows a layout of conductive patterns on a base substrate of an electronic device according to an embodiment.

As shown in (a) ofFIG.2, the conductive pattern410may include a first conductive via412, a second conductive via414, a conductive line416connected to the first conductive via412and the second conductive via414, and an open stub418connected to the conductive line416. Here, the first conductive via412and the second conductive via414may be connected to a plurality of semiconductor chips200.

For example, the conductive line416and the open stub418may be configured in a microstrip and/or strip line form. Here, the stub represents a piece or a strip, and is used as a term for referring to an additionally connected path for the purpose of an impedance matching as well as a signal transmission purpose in the microstrip and/or strip line circuit. When the stub is not connected to the conductive line, this may be referred to as the open stub418, and when the stub is connected to a ground line, this may be referred to as a short-circuited stub.

The first conductive via412is spaced from the second conductive via414. The conductive line416may be connected to the first conductive via412and the second conductive via414. The first conductive via412and the second conductive via414may be connected to the conductive line416on a layer on which the conductive line416is positioned.

The open stub418is connected to a connector TP of the conductive line416between the first conductive via412and the second conductive via414. For example, the connector TP and the open stub418are positioned between the first conductive via412and the second conductive via414. A first end of the open stub418is connected to the connector TP, and a second end thereof may be opened. For example, the open stub418might not be connected to other elements on the base substrate100, but may be connected to the conductive line416. The open stub418may extend in a direction different from which the conductive line416extends. For example, the open stub418may be substantially perpendicular to the conductive line416.

The connector TP may be substantially positioned in the middle of the conductive line416. For example, when a width of the conductive line416is substantially constant, the connector TP may be a point for substantially dividing the conductive line416into two equal portions. A length of the conductive line416between the first conductive via412and the connector TP may be substantially equivalent to a length of the conductive line416between the second conductive via414and the connector TP. An impedance value of the conductive line416between the connector TP and the first conductive via412may be substantially equivalent to an impedance value of the conductive line416between the connector TP and the second conductive via414.

An impedance value of the open stub418relates to the impedance value of the conductive line416. For example, the impedance value of the conductive line416may be a multiple of the impedance value of the open stub418. For example, the impedance value of the open stub418may be about ½ of the entire impedance value of the conductive line416. Hence, a length L1and a width W1of the open stub418relates to the impedance value of the conductive line416. An electrical length of the open stub418may be less than ¼λ (λ is a wavelength corresponding to a center frequency) and greater than 0.

An input/output impedance value of the semiconductor chip200that is connected to the first conductive via412may be substantially equivalent to an input/output impedance value of the semiconductor chip200that connected to the second conductive via414.

The open stub418may extend to cross a direction in which the conductive line416extends. For example, the open stub418may be bifurcated from the conductive line416, The open stub418may be a conductive line including a same material as the conductive line416. However, the present invention is not limited thereto. For example, the open stub418and the conductive line416may include different material from each other.

The conductive line416and the open stub418may be positioned on the same layer, and the conductive line416and the open stub418may be positioned on different layers, which will be described in a later portion of the present specification with reference toFIG.6.

As shown in (b) ofFIG.2, the conductive pattern420amay include a first conductive via422, a second conductive via424, a conductive line426connected to the first conductive via422and the second conductive via424, and an open stub428connected to the conductive line426. The second conductive via424may be connected to the input/output terminal310.

As shown in (c) ofFIG.2, the conductive pattern420bmay include a first conductive via422, a second conductive via424, a third conductive via432, a conductive line426, a resistor430, and a conductive line434. The conductive line426may be connected to the first conductive via422and the second conductive via424. The resistor430may be connected to the second conductive via424and the third conductive via432, and the conductive line434may be connected to the third conductive via432and the input/output terminal310.

Descriptions regarding the open stub428in (b) ofFIG.2and (c) ofFIG.2correspond to the above-provided description on the open stub418in (a) ofFIG.2, so no description regarding the open stub428will be provided.

In (b) ofFIG.2and (c) ofFIG.2, the impedance value of the conductive line426may be equivalent to the input/output impedance value of the semiconductor chip200connected to the first conductive via422and the input/output impedance value of the input/output terminal310connected to the second conductive via424.

A structure of the conductive pattern410will now be described with reference toFIG.3andFIG.4.

FIG.3shows a cross-sectional view of an electronic device ofFIG.2with respect to a line II-II′, andFIG.4shows a cross-sectional view of an electronic device ofFIG.2with respect to a line III-III′.

As shown inFIG.3, conductive vias412and414and a conductive line416, which are for electrically connecting connection pads412c,412d,414c, and414d, may be positioned on the base substrate100a.

The base substrate100amay include a substrate base110. For example, the substrate base110may be made of at least one material of a phenol resin, an epoxy resin, and/or a polyimide.

In an embodiment, an upper side solder resist layer122and a lower side solder resist layer124for covering at least part of substrate bases110_1and110_5, respectively, may be formed on an upper side and a lower side of the base substrate100a, respectively. The connection pads412c,412d,414c,414d,412c, and414c, that are not covered by the upper side solder resist layer122and/or the lower side solder resist layer124and are exposed, may be disposed on the upper side and/or the lower side of the base substrate100a. The connection pads412c,412d,414c, and414dmay be electrically connected to the semiconductor chips200through a chip connecting member. The chip connecting member may be a solder ball or a bump, and without being limited thereto; for example, the chip connecting member may be a bonding wire.

The base substrate100amay be a multilayered substrate on which a plurality of substrate bases110_1, . . . ,110_5are stacked on each other. A conductive line416may be positioned between two adjacent stacked substrate bases110. For example, the conductive line416may be positioned between substrate base110_3and substrate base110_4. In an embodiment of the present inventive concept, the conductive line416may be positioned between the substrate base110_1and the solder resist layer122and/or between the substrate base110_5and the lower side solder resist layer124.

The connection pads412cand414cmay be disposed on the substrate base110_1. The connection pads412dand414dmay be disposed on the substrate base110_5. For example, the conductive line416may be disposed on the upper side of the substrate base110_4and the lower side of the substrate base110_1. However, the present invention is not limited thereto; for example, the conductive line416may be disposed on the upper side of the substrate base110_1and/or the lower side of the substrate base110_5. The conductive line416may be disposed on at least one of the two adjacent stacked substrate bases110. Referring toFIG.3, the conductive line416will be described to be disposed between the substrate base110_3and the substrate base110_4. Also, an additional conductive line may be further positioned on the upper side of the substrate base110_1between the substrate base110_1and the substrate base110_2, between the substrate base110_2and the substrate base110_3, between the substrate base110_3and the substrate base110_4, between the substrate base110_4and the substrate base110_5, and on the lower side of the substrate base110_5.

In an embodiment, a ground plane layer may be disposed on at least one of the upper side of the substrate base110_1, between the substrate base110_1and the substrate base110_2, between the substrate base110_2and the substrate base110_3, between the substrate base110_3and the substrate base110_4, between the substrate base110_4and the substrate base110_5, and on the lower side of the substrate base110_5.

To electrically connect the connection pads412c,412d,414c, and414dand the conductive line416, or conductive lines disposed among different substrate bases, a plurality of conductive vias412and414penetrating at least part of the substrate base110may be further included, Some of the conductive vias may be electrically connected to the ground plane layer.

The conductive line416, the conductive vias412and414, and/or the ground plane layer may be made of a conductive material, for example, copper, nickel, stainless steel, or beryllium copper.

A first end of the conductive line416may be electrically connected to the connection pad412cthrough the first conductive via412, and a second end of the conductive line416may be electrically connected to the connection pad414cthrough the second conductive via414. The first conductive via412and the second conductive via414may each penetrate the substrate bases110_1, . . . ,110_5.

A first portion412aof the first conductive via412penetrates the substrate bases110_1,110_2, and110_3and is connected to the conductive line416between the substrate base110_3and the substrate base110_4. A first portion414aof the second conductive via414penetrates the substrate bases110_1,110_2, and110_3and is connected to the conductive line416between the substrate base110_3and the substrate base110_4.

A second portion412bof the conductive via412penetrates the substrate bases110_4and110_5and is connected to the conductive line416, A second portion414bof conductive via412penetrates the substrate bases110_4and110_5and is connected to the conductive line416. In addition, the second portion412bof the conductive via412and the second portion414bof the conductive via414are via stubs, which may be removed by a process such as a back drilling. However, a manufacturing cost by the additional process may be increased. According to an embodiment, the process for removing the via stubs412band414bmay be omitted by connecting the open stub to the conductive line416.

Referring toFIG.4, the conductive line416may be connected to the open stub418on the connector TP. The open stub418extends by a predetermined length L1from the connector TP. The open stub418may be positioned between the substrate base110_3and the substrate base110_4.

According to an embodiment of the present inventive concept, by forming a low pass filter by connecting the open stub418to the conductive pattern410for connecting the conductive vias412and414to each other, the influence caused by the via stubs412band414bmay be reduced, and transmission of a low-frequency component of a signal through the conductive pattern410may be increased.

The low pass filter will now be described with reference toFIG.5.

FIG.5shows a filter of an electronic device according to an embodiment.

Referring toFIG.5, conductive vias412and414, a conductive line416, and an open stub418form a 3rd-order low pass filter.

A terminal202of the first semiconductor chip may be connected to a terminal204of the second semiconductor chip by a conductive pattern410.

The impedance value toward the terminal202of the first semiconductor chip from the conductive pattern410may be Z01, and the impedance value for the terminal204of the second semiconductor chip may be Z02on the conductive pattern410. Z01and Z02may have substantially equivalent values to each other.

The impedances of the conductive vias412and414are Za1and Zb1which may have substantially equivalent values to each other. Here, Za1, Zb1, Z01, and Z02may have substantially equivalent values to each other.

The impedance of the conductive line416may be divided into Z11and Z12with reference to a node to which the open stub418is connected. The impedance Z11and the impedance Z12may be substantially 1:1. The impedance Z11and the impedance Z12may have about twice the impedance Z01or Z02. The impedance Z2of the open stub418may have about ½ of the value of the impedance Z01or Z02. The impedance relationship may be expressed as in Equation 1.

Z⁢01=Z⁢02,(Equation⁢1)Za⁢1=Zb⁢1=Z⁢01Z⁢11=Z⁢12=2⁢Z⁢01,Z⁢2=12⁢Z⁢0⁢1

The impedance Z2of the open stub418, the impedance Z11or Z12of the conductive line416divided by the open stub418, and the impedances Za1and Zb1of the via stub have been described in the above, and when the respective impedances do not satisfy Equation 1, the open stub418is connected to the conductive line416of which both ends the via stub is connected to, thereby realizing a 3rd-order Butterworth filter.

Conductive patterns according to an embodiment will now be described with reference toFIG.6andFIG.7.

FIG.6shows a layout of conductive patterns on a base substrate of an electronic device according to an embodiment.

As shown in (a) ofFIG.6, the conductive pattern410amay include a first conductive via412, a second conductive via414, a conductive line416connected to the first conductive via412and the second conductive via414, and an open stub419connected to the conductive line416.

The first conductive via412, the second conductive via414, and the conductive line416shown inFIG.6are similar to the first conductive via412, the second conductive via414, and the conductive line416described with reference toFIG.2, so no detailed descriptions thereof will be provided to prevent providing repetitive descriptions.

The open stub419may be a conductive via positioned in the connector TP of the conductive line416between the first conductive via412and the second conductive via414. The connector TP may be positioned substantially in the middle of the conductive line416.

For example, the connector TP may be a point for substantially dividing the conductive line416into two portions. For example, the two portions of the conductive line416may be substantially equal to each other. The impedance value of the conductive line416between the connector TP and the first conductive via412may be substantially equivalent to the impedance value of the conductive line416between the connector TP and the second conductive via414.

The open stub419may be electrically connected to the conductive line416. This will be described with reference toFIG.7.

FIG.7shows a cross-sectional view of an electronic device ofFIG.6with respect to a line IV-IV.

As shown inFIG.7, a conductive line416for electrically connecting spaces between the connection pads412c,412d,414c, and414dmay be positioned on the base substrate100b.

The base substrate100b, the connection pads412c,412d,414c, and414d, the first conductive via412, the second conductive via414, and the conductive line416are respectively similar to the base substrate100a, the connection pads412c,412d,414c, and414d, the first conductive via412, the second conductive via414, and the conductive line416described with reference toFIG.3, so no detailed descriptions thereof will be provided to prevent providing repetitive descriptions.

The conductive line416may be connected to the open stub419at the connector TP. The open stub419may be a conductive via penetrating the substrate bases110_1, . . . ,110_5. A depth of the open stub419in a third direction DR3may be equivalent to that of the first conductive via412and the second conductive via414. The conductive line416may be disposed on one side of the substrate base110_4and may be connected to the open stub419.

The impedance value of the open stub419relates to the impedance value of the conductive line416. For example, the impedance value of the conductive line416may be a multiple of the impedance value of the open stub419. For example, the impedance value of the open stub419may be about ½ the entire impedance value of the conductive line416. Hence, a cross-section of the open stub419relates to the impedance value of the conductive line416.

As shown in (b) ofFIG.6, the conductive pattern410may include a first conductive via412, a second conductive via414, a conductive line416connected to the first conductive via412and the second conductive via414, and an open stub418connected to the conductive line416.

The open stub418may be connected to the connector TP of the conductive line416between the first conductive via412and the second conductive via414. The open stub418may include a first open stub418aand a second open stub418bextending in different directions with respect to each other. The first open stub418aand the second open stub418bmay be impedances coupled in parallel to the conductive line416at the connector TP.

The impedance values of the first open stub418aand the second open stub418brelate to the impedance value of the conductive line416. For example, the impedance value of the conductive line416may be a multiple of a combined impedance value of the first open stub418aand the second open stub418b. For example, the combined impedance value of the first open stub418aand the second open stub418bmay be ½ of the entire impedance value of the conductive line416. Therefore, respective lengths and widths of the first open stub418aand the second open stub418brelate to the impedance value of the conductive line416.

The respective lengths and widths of the first open stub418aand the second open stub418bmay be identical to each other so that the first open stub418aand the second open stub418bmay have the same impedance value. However, when the first open stub418aand the second open stub418bhave substantially equivalent impedance values, the lengths and the widths of the first open stub418aand the second open stub418bmay be different from each other.

The first open stub418aand the second open stub418bmay extend in the direction that crosses the direction in which the conductive line416extends. The first open stub418aand the second open stub418bmay extend in opposite directions with respect to each other, and an angle between the first open stub418aand the second open stub418bmay be greater than 0 degrees and equal to or less than 180 degrees.

The conductive line416, the first open stub418a, and the second open stub418bmay be positioned on a same layer.

A conductive pattern according to an embodiment will now be described with reference toFIG.8andFIG.9.

FIG.8shows a layout of conductive patterns on a base substrate of an electronic device according to an embodiment.

As shown inFIG.8, the conductive line816may be disposed near at least one of the conductive lines826and836. The open stub818may extend in a direction that crosses the direction in which the conductive line816extends from the connector TP of the middle of the conductive line816. The open stub818may then extend to be spaced from the conductive line provided nearest the connector TP. For example, the open stub818may be spaced apart from at least one of the conductive lines826or836.

For example, when a distance to the conductive line826from the connector TP is given as D1, and a distance to the conductive line836from the connector TP is given as D2(D1>D2), the open stub818may extend in an opposite direction to the direction that faces the conductive line836at the connector TP. Here, the open stub818extends in a direction that forms the angle of 180 degrees with respect to the direction that faces the conductive line836, and depending on embodiments, the open stub818may extend in a direction that forms the angle of about 90 degrees to about 270 degrees with respect to the direction that faces the conductive line836.

When the conductive line816is disposed near one conductive line836, the open stub818may extend to be spaced from one conductive line836at the connector TP in a similar way.

As the open stub818is spaced from the adjacent conductive line836, an influence of signal coupling caused by the conductive line836may be minimized.

FIG.9shows a layout of conductive patterns on a base substrate of an electronic device according to an embodiment.

As shown inFIG.9, the conductive line916may be disposed near at least one of the conductive lines926and936. When a length of the open stub918is greater than the distances D3and D4to the respective conductive lines926and936from the connector TP (e.g., a first connector TP′) of the middle of the conductive line916, the open stub918may be positioned on the other connector TP′ (e.g., a second connector TP′) of the conductive line916.

The impedance value of the conductive line916abetween the connector TP′ and the first conductive via912may be substantially equivalent to the impedance value of the conductive line916bbetween the connector TR′ and the second conductive via914. As a length of the conductive line916ais less than a length of the conductive line916b, a width W1of the conductive line916amay be less than a width W2of the conductive line916b.

A signal transmission characteristic of a conductive pattern of an electronic device according to an embodiment will now be described with reference toFIG.10.

FIG.10shows a graph of signal transmission characteristics of conductive patterns of an electronic device according to an embodiment.

As shown inFIG.10, it is found that the signal transmission characteristic of the conductive pattern according to an embodiment is improved compared to the conductive pattern for connecting the conductive via with no conventional open stub in the low frequency bandwidth (e.g., 0 to 4 GHz). As bandwidths that are above about 4 GHz are not the bandwidths in which actual electronic devices are operated, their signal transmission characteristic may be deteriorated compared to prior art.

Table 1 expresses comparison of signal transmission characteristics of the conductive pattern according to an embodiment and a conventional conductive pattern by using eye parameters.

TABLE 1Speed5.2 Gbps6 GbpsEye parametersEyeEyeEyeEyeHeight (mV)Width (ps)Height (mV)Width (ps)Conventional438.3136425.6114.8Proposed501.8142.2465.8114.1

As expressed in Table 1, it is found that eye width E is partly reduced at 6 Gbps regarding the conductive pattern according to an embodiment, and it is found in another case that the parameters of eye height (EH) and EW are improved compared to the conventional conductive pattern. According to the present embodiment, as a channel bandwidth of the conductive pattern is increased through a simple structure and quality of a received signal is improved so manufacturing time and cost may be reduced.

A conductive pattern according to an embodiment will now be described with reference toFIG.11andFIG.12.

FIG.11shows a layout of conductive patterns on a base substrate of an electronic device according to an embodiment.

As shown inFIG.11, the conductive pattern1110may include a first conductive via1112, a second conductive via1114, a conductive line1116connected to the first conductive via1112and the second conductive via1114, and a plurality of open stubs1118a,1118b, and1118cconnected to the conductive line1116.

When the conductive line1116is longer than the open stub1118, the length and the width of the open stub1118, which are for satisfying the impedance of the open stub1118that is determined based on the impedance of the conductive line1116, have big values. Accordingly, it may be difficult to realize the low pass filter through one open stub on the base substrate of which an area is limited and on which other conductive patterns are integrated.

A 5thorder low pass filter is realized by connecting the open stubs1118a,1118b, and1118cto the conductive line1116. The open stubs1118a,1118b, and1118care spaced from each other. Of the open stubs1118a,1118b,1118c, the impedances of the open stubs1118aand1118cdisposed closest to the first conductive via1112and the second conductive via1114, respectively, may be equivalent to each other, and may be greater than that of the open stub1118b.

A length of the conductive line1116between the first conductive via1112and the first connector T1may be substantially equivalent to a length of the conductive line1116between the third connector T3and the second conductive via1114. A length of the conductive line1116between the first connector T1and the second connector T2may be substantially equivalent to a length of the conductive line1116between the second connector T2and the third connector T3.

When the length of the conductive line1116between the first conductive via1112and the first connector T1, the length of the conductive line1116between the first connector T1and the second connector T2, the length of the conductive line1116between the second connector T2and the third connector T3, and the length of the conductive line1116between the third connector T3and the second conductive via1114are substantially equivalent to each other, each of the width of the conductive line1116between the first conductive via1112and the first connector T1and the width of the conductive line1116between the third connector T3and the second conductive via1114may be greater than each of the width of the conductive line1116between the first connector T1and the second connector T2and the width of the conductive line1116between the second connector T2and the third connector T3.

The open stubs1118a,1118b, and1118cmay be connected to a plurality of connectors T1, T2, and T3of the conductive line1116between the first conductive via1112and the second conductive via1114. The impedance value of the conductive line1116between the first conductive via1112and the first connector T1may be substantially equivalent to the impedance value of the conductive line1116between the third connector T3and the second conductive via1114. The impedance value of the conductive line1116between the first connector T1and the second connector T2may be substantially equivalent to the impedance value of the conductive line1116between the second connector T2and the third connector T3.

The impedance values of the open stubs1118a,1118b, and1118crelate to the impedance value of the conductive line1116. This will be described in a later portion of the present specification with reference toFIG.12.

An input/output impedance value of the semiconductor chip200connected to the first conductive via1112may be substantially equivalent to an input/output impedance value of the semiconductor chip200connected to the second conductive via1114.

A low pass filter configured with the conductive pattern1110will now be described with reference toFIG.5.

FIG.12shows a filter of an electronic device according to an embodiment.

Referring toFIG.5, the terminal202of the first semiconductor chip may be connected to the terminal204of the second semiconductor chip by the conductive pattern1110.

The impedance value toward the terminal202of the first semiconductor chip from the conductive pattern1110may be Z01, and the impedance value toward the terminal204of the second semiconductor chip from the conductive pattern1110may be Z02. Z01and Z02may have substantially equivalent values.

The impedances of the conductive vias1112and1114are Za2and Zb2which may have substantially equivalent values.

The impedance of the conductive line1116may be divided into Z11, Z12, Z13, and Z14with reference to a node to which the open stubs1118a,1118b, and1118care connected. The impedance Z11and the impedance Z14may be substantially 1:1. The impedance Z12and the impedance Z13may be substantially 1:1, and may have about twice the impedance Z21and the impedance Z23. The impedance Z21of the open stub1118aand the impedance Z23of the open stub1118cmay be substantially 1:1. The impedance Z22418may have about ½ of the value of the impedance Z01or the impedance Z02. The impedance relationship may be expressed as in Equation 2.

Z⁢01=Z⁢02,(Equation⁢2)Za⁢2=Zb⁢2=3.618Z⁢01Z⁢11=Z⁢14=1.38Z⁢01,Z⁢12=Z⁢13=1.84Z⁢01,Z⁢21=Z⁢23=0.92Z⁢01,Z⁢22=12⁢Z⁢01

Lengths of the open stubs1118a,1118b, and1118cmay be substantially equivalent to each other, and widths of the open stubs1118a,1118b, and1118cmay be different from each other depending on a relationship of Equation 2. Widths of the open stubs1118a,1118b, and1118cmay be substantially equivalent to each other, and lengths of the open stubs1118a,1118b, and1118cmay be different from each other depending on a relationship of Equation 2.

The lengths and the widths of the conductive line1116between the first conductive via1112and the first connector T1, the conductive line1116between the first connector T1and the second connector T2, the conductive line1116between the second connector T2and the third connector T3, and the conductive line1116between the third connector T3and the second conductive via1114may have different values from each other depending on the relationship of Equation 2.

The impedances Z21, Z22, and Z23of the open stubs1118a,1118b, and1118c, the impedances Z11, Z12, Z13, and Z14of the conductive line1116divided by the open stubs1118a,1118b, and1118c, and the impedances Za2and Zb2of the via stub have been described in the above, and when the respective impedances do not satisfy Equation 2, a 5th-order Butterworth filter may be realized by connecting the open stubs1118a,1118b, and1118cto the conductive line1116of which both ends the via stub is connected to. A Butterworth filter of a 7thorder or more than that may be realized according to the above-noted method for realizing the 3rd-order Butterworth filter and the 5th-order Butterworth filter.

A conductive pattern of a main board according to an embodiment will now be described with reference toFIG.13andFIG.14.

FIG.13shows a perspective view of an electronic device according to an embodiment.

As shown inFIG.13, the electronic device1300includes a main board1310and at least one memory module1320connected to the main board1310.

The main board1310includes a base substrate1312, and a controller chip1350connected to the base substrate1312. The base substrate1312may, for example, have a similar configuration to those of the base substrates100aand100bdescribed with reference toFIG.3,FIG.4, andFIG.7, so no detailed descriptions thereof will be provided to prevent providing repetitive descriptions.

A plurality of conductive patterns1340may be disposed in the base substrate1312, The controller chip1350may be at least one of various processing units such as a central processing unit (CPU), an application processor (AP), or a graphics processing unit (GPU).

At least one memory slot1330connected to the base substrate1312may be attached to the main board1310. At least one memory module1320may be fastened to at least one memory slot1330and may be connected to the main board1310. The memory module1320may, for example, be the electronic device10shown inFIG.1.

The controller chip1350may be connected to the at least one memory slot1330through the conductive patterns1340.

A configuration of the conductive pattern1340will now be described with reference toFIG.14.

FIG.14shows a cross-sectional view of an electronic device ofFIG.13with respect to a line V-V′.

As shown inFIG.14, the electronic device includes a base substrate1312, a controller chip1350attached to the base substrate1312, and at least one memory slot1330. The memory slot1330may include a terminal portion1332and a slot body portion1334for supporting the terminal portion1332. The memory module1320shown inFIG.13may be electrically connected to the terminal portion1332, may be supported by the slot body portion1334, and may be connected to the main board1310.

A plurality of connection pads1342aof the base substrate1312may be electrically connected to a plurality of chip connection pads1352of the controller chip1350through a chip connecting member1354. For example, chip connecting member1354may be a solder ball or a bump, and without being limited thereto, for example, the chip connecting member1354may be a bonding wire.

A conductive line1346, which electrically connects the connection pad1342aand the terminal portion1332to each other, may be positioned on the base substrate1310. The conductive line1346may have at least one open stub, which is similar to the configuration of the open stub described with reference toFIG.2,FIG.6,FIG.8,FIG.9, andFIG.11, and will not be described to prevent providing repetitive descriptions.

A method for manufacturing an electronic device according to an embodiment will now be described with reference toFIG.15andFIG.16.

FIG.15shows a flowchart of a method for manufacturing an electronic device according to an embodiment.

A first substrate base is provided (S1500). A conductive line is formed on an upper side and/or a lower side of the first substrate base (S1510). The conductive line may be formed by stacking a metal layer on one side of the first substrate base and partly removing the same. The conductive line is formed to connect conductive vias to each other, and the conductive vias are to be formed in a next process.

A second substrate base may be stacked in a thickness direction on one side of the first substrate base (S1520). A conductive line having at least one open stub is formed on one side of the second substrate base (S1530). When the open stub is formed, the lengths of the conductive line portions divided by the connector on which the open stub is formed may be substantially equivalent to each other. The impedances of the divided conductive line portions may be substantially equivalent to each other. For example, when one open stub is formed, the open stub may be formed in the middle of the conductive line, and the impedances of the two portions of the conductive lines divided by the open stub are substantially equivalent to each other.

A third substrate base is stacked in the thickness direction on one side of the second substrate base (S1540). A conductive line is formed on an upper side of the third substrate base (S1550).

An external layer is formed (S1560), For example, a solder resist layer is formed. Conductive vias are formed so that they may be connected to the conductive lines formed by at least one of the stages S1510, S1530, and S1550(S1570). The conductive vias may penetrate the first to third substrate bases and the solder resist layer.

By the above-noted method, an open stub bifurcated from the conductive line may be formed on a same layer as the conductive line connecting two conductive vias.

FIG.16shows a flowchart of a method for manufacturing an electronic device according to an embodiment.

The stage S1600, the stage S1610, the stage S1620, the stage S1640, the stage S1650, and the stage S1660are similar to the stage S1500, the stage S1510, the stage S1520, the stage S1540the stage S1550, and the stage S1560ofFIG.15so no descriptions thereof will be provided to prevent providing repetitive descriptions.

After the stage S1620, a conductive line is formed on the substrate base without forming an additional open stub (S1630).

After the stage S1660, an open stub and conductive vias are formed to be respectively connected to the conductive lines formed in at least one of the stage S1616, the stage S1630, and the stage S1650(S1670). The lengths of the conductive line portions divided by the connector on which the open stub is formed may be substantially equivalent to each other. The impedances of the divided conductive line portions may be substantially equivalent to each other. For example, when one open stub is formed, the open stub may be formed in the middle of the conductive line, and the impedance of the two portions of the conductive line divided by the open stub may be substantially equivalent to each other.

By the above-noted method, the open stub may be formed with the conductive via penetrating the layer on which the conductive line, which connects the two conductive vias to each other, may be formed.

According to an embodiment, a reflection of signals by conductive vias used in a multilayered board may be prevented.

According to an embodiment, an influence of a signal coupling among conductive lines on a multilayered board may be reduced.

While the present invention has been shown and described with reference to the embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope.