Patent ID: 12205847

DETAILED DESCRIPTION OF THE INVENTION

In the following description of the preferred embodiment, reference is made to a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

Overview

The present invention discloses a method for removing a III-nitride based substrate from epitaxially-grown III-nitride based semiconductor layers using a foreign or hetero-substrate as a support substrate, and specifically, a method of removing a III-nitride based substrate from III-nitride based semiconductor layers with a cleaving technique, so that the III-nitride based substrate can be recycled.

As long as it enables growth of a III-nitride layer through a growth restrict mask, any III-nitride based substrate, such as GaN, may be used. In alternative embodiments, a foreign or hetero-substrate, such as sapphire (Al2O3), SiC, LiAlO2, Si, etc., may be substituted for the III-nitride based substrate.

The III-nitride based semiconductor layers and the III-nitride based substrate refer to any composition or material related to (B, Al, Ga, In)N semiconductors having the formula BwAlxGayInzN where 0≤w≤1, 0≤x≤1, 0≤y≤1, 0≤z≤1, and w+x+y+z=1. Further, compositions and materials within the scope of the invention may further include quantities of dopants and/or other impurity materials and/or other inclusional materials such as Mg, Si, O, C, H, etc.

Island-like III-nitride based semiconductor layers are epitaxially grown on the III-nitride based substrate at an opening area and/or through an intermediate layer at the opening area. The quality of the III-nitride based semiconductor layers is extremely high, and a device comprised of the III-nitride based semiconductor layers is of extremely high quality. However, it is hard to separate the III-nitride based semiconductor layers from the III-nitride based substrate.

It has been discovered that the III-nitride based semiconductor layers can be removed from the III-nitride based substrate very easily using a cleaving technique at a cleaving point on a surface of the III-nitride based substrate.

One technique is to use a growth restrict mask, which is a dielectric film or refractory metal, such as SiO2, SiN, HfO2, Al2O3, MgF, AlN, etc., in this substrate removal technique. It is possible to use a multi-layer structure selected from the above materials, such as Si2/AlN, AlN/SiO2, SiO2/SiN, SiN/SiO2. The interface between the growth restrict mask and any subsequent III-nitride based semiconductor layers grown by ELO on the mask has a weak bonding strength.

The bonding area between the III-nitride based semiconductor layers and the III-nitride based substrate is controlled so that it is less than the device size. Thus, it is easy to remove the layers from the substrate.

Furthermore, the island-like III-nitride based semiconductor layers do not coalesce with each other, and internal strain is released. This is to avoid any occurrences of cracks.

In addition, these methods use characteristics of cleaving at an m-plane, which is the easiest plane among GaN planes to cleave. In alternative embodiments, other planes of the substrate may be used.

This method also determines the cleaving point to use at the start of the cleaving technique. In one embodiment, the cleaving point is at an edge of the growth restrict mask on the substrate.

This method also dissolves the mask using a hydrofluoric acid (HF), buffered HF (BHF), or another etchant, before removing the substrate. Thereafter, the III-nitride based semiconductor layers are bonded to a support substrate using a low temperature melted metal and/or solder, wherein the metal is later dissolved by an etchant.

It is possible to use support substrates which have a thermal expansion different from the III-nitride based substrate. Both substrates are then heated after bonding. Stress is applied to the III-nitride based semiconductor layers, which are bonded to the support substrate, due to the differences in thermal expansion between the substrates.

If a film is used to remove the III-nitride based semiconductor layers from the substrate, the film is not always bonded to the III-nitride based semiconductor layers. The removal can be achieved by at least contacting the film with the semiconductor layers. The film may be a polymer film, which has already been commercialized for dicing. Using the film, the removal process can be performed repeatedly. In other words, even if the semiconductor layers cannot be removed in one step, this step can be performed several times. Many other removal methods are not repeatable.

This stress is applied at the cleaving point between the III-nitride based semiconductor layers and the III-nitride based substrate. The cleaving starts from one side of the cleaving point, which is at an edge of the growth restrict mask, and proceeds to the opposite side of cleaving point.

The chip size, which is the width of the island-like III-nitride based semiconductor layers, generally is wider than the cleaving length along the cleaving surface. As a result, less force or pressure can be used to remove the semiconductor layers. This avoids degradation of the device and reduction in yields.

The cleaving technique uses a trigger to start the cleaving technique. The trigger may be the stress resulting from the differences in thermal expansion, but other triggers may be used as well. For example, mechanical force, such as ultra-sonic waves, can be used as the trigger for the cleaving technique.

If mechanical forces are used, removal of the III-nitride based substrate is achieved quickly and with very weak stress due to cleaving of the m-plane. Furthermore, the cleaving point may be a wedge shape, which simplifies the cleaving. The shape of the cleaving point is important to achieve a high yield.

Moreover, when the III-nitride based semiconductor layers are removed from the substrate, force can be applied using the differences of the thermal expansion between the film or support substrate and the semiconductor layers. This has the following advantages: 1) the force is applied uniformly; and 2) the strength and speed of the force can be controlled by changing the temperature. Thus, this method can be easily adopted for mass production.

Another aspect that must be considered when using the cleavability to remove the semiconductor layers from the substrate is how to apply the impact uniformly and adequately to the semiconductor layers. Even if the cleave length is wide, a device removed utilizing the cleavability of the GaN crystal needs the impact to start cleaving. It is effective to utilize the differences of the thermal expansion coefficient, so that the force can be applied uniformly to the semiconductor epilayer. If polymer films are used, the differences in the thermal expansion coefficient between the polymer film and the semiconductor layer are large, which makes the force strong.

Another way to use polymer films is that the polymer films can be expanded in one direction in order to remove the semiconductor layer without temperature change. Expanding the polymer films can apply the impact to the cleaving point.

Using these methods, device layers can be easily removed from the III-nitride based substrates and wafers, including wafers of large size, e.g., over 2 inches. For devices needing AlGaN layers, this is very useful, especially in the case of high Al content layers.

First Embodiment

Generally, the present invention describes a III-nitride based semiconductor device and a method for manufacturing the III-nitride based semiconductor device.

In a first embodiment, the method comprises the steps of: forming a growth restrict mask with a plurality of opening areas directly or indirectly upon a substrate, wherein the substrate is a III-nitride based semiconductor; growing a plurality of island-like III-nitride based semiconductor layers upon the substrate using the growth restrict mask, such that the growth extends in a direction parallel to the opening areas of the growth restrict mask, wherein each of the island-like III-nitride based semiconductor layers form a device; depositing p-electrodes on an exposed surface of the devices; bonding the p-electrodes of the devices to a support substrate or contacting the p-electrode to a film; at least partially dissolving the growth restrict mask using a wet etching technique; separating the III-nitride based substrate from the devices using thermal expansion and a cleaving technique; depositing n-electrodes on a surface of the devices exposed by the cleaving; and separating the devices by dividing the support substrate. The end results comprise one or more III-nitride based semiconductor devices, which may be opto-electronic devices, as well as a III-nitride based substrate that may be recycled and reused.

Specifically, the method includes the following steps:

1. Substrate, ELO+III-Nitride Based Semiconductor Layers

This step is described inFIG.1, which illustrates providing a III-nitride based substrate101, such as a bulk GaN substrate101. In this embodiment, the GaN-based substrate101has a growth surface that is an m-plane with a 1 degree mis-cut towards the (000-1) direction.

A growth restrict mask102is formed on or above the GaN-based substrate101. Specifically, the growth restrict mask102is disposed directly in contact with the substrate101, or is disposed indirectly through an intermediate layer grown by metalorganic chemical vapor deposition (MOCVD), etc., made of a III-nitride based semiconductor deposited on the substrate101.

The growth restrict mask102can be formed from an insulator film, for example, an SiO2film deposited upon the base substrate101, for example, by a plasma chemical vapor deposition (CVD) method, sputter, ion beam deposition (IBD), etc., wherein the SiO2film is then patterned by photolithography using a predetermined photo mask and etching to include opening areas103, as well as no-growth regions104(which may or may not be patterned).

Epitaxial III-nitride layers105, such as GaN-based layers105, are grown by ELO on the GaN substrate101and the growth restrict mask102. The growth of the ELO GaN-based layers105occurs first in the opening areas103, on the GaN-based substrate101, and then laterally from the opening areas103over the growth restrict mask102. The growth of the ELO GaN-based layers105is stopped or interrupted before the ELO GaN-based layers105at adjacent opening areas103can coalesce on top of the growth restrict mask102. This interrupted growth results in the no-growth regions104between adjacent ELO GaN-based layers105.

Additional III-nitride semiconductor device layers106are deposited on or above the ELO GaN-based layers105, and may include an active region106a, an electron blocking layer (EBL)106b, and a cladding layer106c, as well as other layers.

The ELO GaN-based layers105and the additional III-nitride based semiconductor device layers106separated by no-growth regions104are referred to as island-like III-nitride based semiconductor layers109. Each of the island-like III-nitride semiconductor layers109may be processed into a separate device110.

2. Dissolving the Growth Restrict Mask by Wet Etching.

FIG.2(a)is another view of the ELO GaN-based layers105grown on or above the GaN-based substrate101and then laterally over the growth restrict mask102. As shown inFIG.2(b), some or all of the SiO2-based growth restrict mask102is optionally dissolved using a chemical solution, such as BHF, HF or another etchant. This allows the devices110to cleave from the GaN substrate101more easily, as described in more detail below.

3. p-Electrode Deposition.

As show inFIG.2(c), a Transparent Conductive Oxide (TCO) cladding layer202may be deposited on the devices110, followed by the deposition of a ZrO2current limiting layer203and p-electrode204.

4. Bonding the Support Substrate.

As shown inFIG.2(d), the devices110are flip-chip bonded to a support substrate201using metal-metal bonding or soldering techniques with the p-electrodes204. In one embodiment, the support substrate201is a Cu substrate, and patterned Ti/Au electrodes may be fabricated on the Cu substrate201by electron beam evaporation, sputter, thermal heat evaporation, etc., for subsequent bonding to the p-electrodes204.

5. Removing the Substrate by Cleaving and Optional Thermal Expansion.

As shown inFIG.2(e), the support substrate201is optionally heated so that thermal expansion210exposes cleaving points205, and a cleaving technique is used to remove the devices110from the substrate101at the cleaving points205along a cleaving length206, which may be less than the device size207. The cleaving technique exposes a cleaving surface208of the device110, as well as a cleaving surface209of the substrate101. The cleaving surfaces208,209may include an m-plane facet, or the cleaving surfaces208,209as a whole may be m-plane, and/or the cleaving surfaces208,209may include facets other than m-plane.

6. Deposition of an n-Electrode.

As shown inFIG.2(f), n-electrodes211, which may be comprised of TCO and Ti/Al, Ti/Au, Hf/Al/Mo/Au, etc., are deposited on the back-side of the devices110.

7. Separating the Devices

Chip scribing may be performed to separate the devices110.

These and other aspects of the present invention are described in more detail below.

Definitions of Terms

In this invention, the following terms are defined:

III-Nitride Based Substrate

In one embodiment, the III-nitride based substrate101is a GaN-based substrate101. However, as long as a III-nitride based substrate101enables growth of ELO III-nitride based layers105through a growth restrict mask102, any III-nitride based substrate101may be used.

Moreover, the III-nitride based substrate101may be sliced on a {1-100}, {20-21}, or {20-2-1} plane, or any other plane, from a bulk III-nitride based crystal, such as a nonpolar (1-100) m-plane GaN substrate101sliced from a bulk GaN crystal.

Growth Restrict Mask

The growth restrict mask102comprises a dielectric layer, such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, etc., or a refractory metal, such as W, Mo, Ta, Nb, Pt, etc. The growth restrict mask102may be a laminate structure selected from the above materials. The growth restrict mask102also may be a stacking layer structure chosen from the above materials.

In one embodiment, the thickness of the growth restrict mask102is about 0.05-3 μm. The width of the mask102is preferably larger than 20 μm, and more preferably, the width is larger than 40 μm.

Two examples of the growth restrict mask102are shown inFIGS.3(a) and3(b).

As noted above, the growth restrict mask102is patterned into stripes102aand includes opening areas103between the stripes102a. In one embodiment shown in FIG.3(a), the opening areas103have a length a and a width b. The length a of each of the opening areas103is in a first direction parallel to the 1-100 direction of the GaN-based substrate101and the width b of each of the opening areas103is in a second direction parallel to the 11-20 direction of the GaN-based substrate101, with the opening areas103spaced apart periodically at a first interval p1, extending in the second direction. The width b of each of the opening areas103is typically constant, but may be changed as necessary. The width L of each of the stripes102aof the growth restrict mask102is L=p1−b.

In another embodiment shown inFIG.3(b), the length and width of each of the opening areas103are arranged in similar directions asFIG.3(a), but the lengths a may be different and adjacent opening areas103are offset in the first direction by a second interval p2 and are shifted in the second direction by a half of the first interval p1, in a manner such that end portions of adjacent opening areas103overlap lengthwise for a predetermined distance q in the first direction. This arrangement prevents embossment of both end portions of the opening areas103in the 1-100 direction of the GaN-based substrate101.

In both of these embodiments, the length a of the opening area103is about 200 to 2000 μm; the width b is about 0.5 to 20 μm; the intervals p1 and p2 of the opening areas103are about 6 to 120 μm; the width of the mask portion L is p1−b, so that, in the case of p1=55 μm and b=5 μm, L is 50 μm; and the overlapping length q of the end portions each other of the opening areas103is about 35 to 40 μm. However, other values may be used.

ELO III-Nitride Based Layers

In one embodiment, the ELO III-nitride based layers105are ELO GaN-based layers105. However, any III-nitride based semiconductor may be used as the ELO III-nitride based layers105.

FIGS.4(a) and4(b)illustrate the growth of the ELO GaN-based layers105using the growth restrict masks102ofFIGS.3(a) and3(b), respectively.

Using the growth restrict mask102, the ELO GaN-based layers105are grown in an island-like shape in the (0001) plane orientation by a vapor-phase deposition method, for example, a MOCVD method.

The surface of the GaN-based substrate101is exposed in the opening areas103of the growth restrict mask102, and the ELO GaN-based layers105are selectively grown thereon, continuously in both vertical and lateral directions relative to the growth restrict mask102. The growth is stopped before the ELO GaN-based layers105coalesce with adjacent ELO GaN-based layers105on the growth restrict mask102, resulting on no-growth regions104between the adjacent ELO GaN-based layers105.

For (0001) plane growth of a GaN-based semiconductor, the lateral growth rate parallel to the plane is the largest in the 11-20 direction and is the smallest in the 1-100 direction. In the growth restrict mask102shown inFIGS.3(a) and3(b), as the longitudinal direction of the opening area103is the 1-100 direction, the growth rate of the GaN-based semiconductor is small at both ends of the opening area103, the ELO GaN-based layers105opposing each other in the 1-100 direction do not coalesce and remain separated from each other. The length of the ELO GaN-based layers105in the 1-100 direction becomes nearly equal with the length a of the opening area103.

The thickness of the ELO GaN-based layers105is important, because it determines the width of one or more flat surface regions107and layer bending regions108at the edges thereof adjacent the no-growth regions104. The width of the flat surface region107is preferably at least 5 μm, and more preferably is 10 μm or more, and most preferably is 20 μm or more.

The growth ratio of the ELO GaN-based layers105is the ratio of the growth rate of the lateral direction parallel to the 11-20 axis of the GaN-based substrate101to the growth rate of the vertical direction parallel to the 0001 axis of the GaN-based substrate101. Preferably, the growth ratio of the ELO GaN-based layers105is high, wherein, by optimizing the growth conditions, the growth ratio of the ELO GaN-based layers105can be controlled from 0.2 to 4. In the c-plane case, where the ratio of the ELO GaN-based layers105is 4, the ELO GaN-based layers105are only about 5 μm in thickness, but obtain a width of the flat surface region107of 20 μm. On the other hand, in the m-plane case, the ratio of the ELO GaN-based layers105is less than the c-plane, e.g., about 0.2-2. The present invention makes it possible to remove the epilayer in both cases.

In order to obtain a high ratio for the ELO GaN-based layers105, the growth temperature of the ELO GaN-based layers105is preferably higher than about 950° C. and the pressure in the MOCVD chamber is preferably lower than about 100 Torr. Also, in order to promote the migration of Ga atoms, the V/III ratio is preferably high.

When the distance between the ELO GaN-based layers105on opposing planes with lowest growth rates is large, the following disadvantages occur. In the mask portion of the growth restrict mask102at the regions between the ELO GaN-based layers105in the 1-100 direction of which the growth rate is the lowest, raw gas is not consumed, and therefore, the gas concentration increases, and a concentration gradient in the 1-100 direction is generated, and by diffusion according to the concentration gradient, a large amount of the gas is supplied at the edge portions in the 1-100 direction of the ELO GaN-based layers105. As the result, the thickness of the edge portions in the 1-100 direction of the ELO GaN-based layers105increases in comparison with other portions, and results in a raised shape. The raised shape causes not only structural inconveniences in the devices, but also creates problems in the following manufacturing processes of photolithography, etc.

To prevent the raised shape, the ELO GaN-based layers105come as close as possible, and thus it is necessary not to create in-plane uniformity of the raw gas from the beginning of the growth. In the growth restrict mask102shown inFIG.3(b), the opening areas103adjacent to each other in the 11-20 direction are formed in a manner such that the opening areas103overlap at opposing end portions for the length q.

As a result, the in-plane uniformity of gas concentration is obtained by consumption of the raw gas caused by growing the ELO GaN-based layers105. Finally, this results in a uniformity in the thickness of the island-like III-nitride based semiconductor layers109.

Additional III-Nitride Based Semiconductor Layers

The growth conditions of the additional III-nitride based semiconductor layers106can use the same MOCVD conditions as the ELO III-nitride based layers105. For example, the growth of GaN layers is at the temperature of 950-1150° C. and the pressure of 30 kPa. For the growth of a GaN layers, trimethylgallium (TMGa) and ammonia (NH3) are used as the raw gas, and hydrogen (H2) and nitrogen (N2) are used as the carrier gas; for the growth of an AlGaN layers, triethylaluminium (TMAl) is used as the raw gas; and for the growth of an InGaN layers, trimethylindium (TMIn) is used as the raw gas.

Flat Surface Region

The flat surface region107is bounded on both sides by the layer bending regions108. Furthermore, the flat surface region107is on or above the growth restrict mask102and the opening areas103.

Fabrication of the semiconductor devices110is mainly performed on the flat surface region107. The flat surface region107has a high uniformity of the thickness of each semiconductor layer105,106in the flat surface region107.

It is not a problem if the fabrication of the semiconductor device110is partially performed on the layer bending region108. More preferably, the layer bending layer108is removed by etching before the device110is completed.

Layer Bending Region

As shown inFIG.5, the layer bending region108may result in a bended active region501remaining in the device110, following growth of the additional III-nitride semiconductor device layers106.

If the layer bending region108that includes a bended active region501remains in the device110that is an LED chip, a portion of the emitted light from the active region is reabsorbed. As a result, it may be preferable to remove the layer bending region108.

If the layer bending region108that includes a bended active region501remains in the device110that is an LD chip, the laser mode may be affected by the layer bending region108due to a low refractive index (e.g., when it is an InGaN layer). As a result, it may be preferable to remove the layer bending region108.

If the layer bending region108remains in the device110that is an LD chip, the edge of a ridge stripe structure should be at least 1 μm or more from the edge of the layer bending region108.

From another point of view, an epitaxial layer of the flat surface region107, except for the opening area103, has a lesser defect density than an epitaxial layer of the opening area103. Therefore, the ridge stripe structure should be in the flat surface region107, except for the opening area103.

Island-Like III-Nitride Based Semiconductor Layers

As noted above, the III-nitride based semiconductor layers include ELO III-nitride based layers105and additional III-nitride based semiconductor layers106, and are collectively referred to as island-like III-nitride based semiconductor layers109.

The sides of the island-like III-nitride based semiconductor layers109are typically formed with the (1-10a) plane (where a is an arbitrary integer), the (11-2b) plane (where b is an arbitrary integer), or planes crystallographically equivalent to these, or the sides of the island-like III-nitride based semiconductor layers include the (1-10a) plane (where a is an arbitrary integer).

The island-like III-nitride based semiconductor layers109generally comprise more than two layers, including at least one layer among an n-type layer, an undoped layer and a p-type layer. The island-like III-nitride based semiconductor layers109specifically may comprise GaN layers, AlGaN layers, AlGaInN layers, InGaN layers, etc.

In cases where the device110has a plurality of the island-like III-nitride based semiconductor layers109, the distance between the island-like III-nitride based semiconductor layers109adjacent to each other is generally 30 μm or less, and preferably 10 μm or less, but is not limited to these values. The distance between the island-like III-nitride based semiconductor layers109is preferably the width of the no-growth region104.

The combined thickness of the ELO GaN-based layers105and the additional III-nitride based semiconductor device layers106may range from 1 to 70 μm, for example, but is not limited to these values. The combined thickness of the ELO GaN-based layers105and additional III-nitride based semiconductor device layers106is measured from the surface of growth restrict mask102to the upper surface of the additional III-nitride based semiconductor device layers106.

Devices

The semiconductor devices110may comprise, for example, a Schottky diode, a light-emitting diode, a semiconductor laser diode, a photodiode, a transistor, etc., but are not limited to these devices. This invention is particularly useful for micro-LEDs and laser diodes, such as edge-emitting lasers and vertical cavity surface-emitting lasers (VCSELs).

FIG.6is a sectional view of one embodiment of the device110, which in this example comprise a laser diode. Specifically, the III-nitride semiconductor laser diode is comprised of the following layers, laid one on top of another in the order mentioned, the growth restrict mask102, the ELO GaN-based layers105, a 5× InGaN/GaN multiple quantum well (MQW) active region106a, an AlGaN EBL106b, a p-GaN cladding layer106c, a ZrO2current limiting layer203, and a p-electrode204. Note that the semiconductor layers105,106may be formed of any nitride-based III-V group compound semiconductor grown in the above order.

The sectional view ofFIG.6shows the laser bar along a direction perpendicular to an optical resonator, which is comprised of a ridge stripe structure. The ridge stripe structure is comprised of the p-GaN cladding layer106cand p-electrode204, and provides optical confinement in a horizontal direction. The width of the ridge stripe structure is of the order of 1.0 to 20 μm, and typically is 10 μm.

In one embodiment, the p-electrode204may be comprised of one or more of the following materials: Pd, Ni, Ti, Pt, Mo, W, Ag, Au, etc. For example, the p-electrode204may comprise Pd—Ag—Ni—Au (with thicknesses of 3-50-30-300 nm). These materials may be deposited by electron beam evaporation, sputter, thermal heat evaporation, etc. It can also use an ITO electrode on the p-GaN layer.

Facets

FIGS.7(a) and7(b)illustrate the method of making facets for a laser diode device110.

FIG.7(a)shows the no-growth region104, the ELO GaN-based layer105, the flat surface region107and layer bending region108, based on the growth restrict mask102ofFIG.3(a).FIG.7(b)is an enlarged view of the circled portion ofFIG.7(a), and shows a ridge stripe structure701and etched mirror region702, on the ELO GaN-based layer105inFIG.7(a). The etched mirror region702is located based on optical resonance length.

The etching process for GaN etching uses an Ar ion beam and Cl2ambient gas. The etching depth is from about 1 μm to about 4 μm. The etched mirror facet702may be coated by a dielectric film selected from the group of the following: SiO2, Al2O3, AlN, AlON, SiN, SiON, TiO2, Ta2O5, Nb2O5, Zr2O, etc. The etching process can be adopted for single-layer and multi-layer structures that are selected above materials.

The facets can also be made by a cleaving method, which is utilized for conventional laser diodes.

Support Substrate

The support substrate201may be comprised of elemental semiconductor, compound semiconductor, metal, alloy, nitride-based ceramics, oxide-based ceramics, diamond, carbon, plastic, etc., and may comprise a single layer structure, or a multilayer structure made of these materials. A metal, such as solder, etc., or an organic adhesive, may be used for the bonding of the support substrate201to the devices110, and is selected as necessary.

Conventional bonding techniques can be adopted for bonding the support substrate201to the devices110.

In general, the most common types of flip-chip bonding are thermal compression bonding and wafer fusion/bonding. Wafer fusion has been popularly employed in InP-based devices. However, thermal compression bonding is generally much simpler than wafer fusion, as it uses metal-to-metal bonding, and has the benefit of also greatly improving thermal conductivity.

An Au—Au compression bond is by far the simplest bond and results in a fairly strong bond. An Au—Sn eutectic bond offers a much greater bond strength.

It is preferable to perform an activation of the surfaces of the devices110before compression bonding. The activation of the surfaces is achieved by using a plasma process of Ar and/or O2. The III-nitride based devices110are then bonded to the support substrate201at 150-300° C. under pressure.

Additional Support Substrates

In another embodiment, a second support substrate (not shown) may be used in the removal of the GaN-based substrate101from the devices110. This method comprises the steps of bonding the first support substrate201to the exposed surface of the devices110, and bonding the second support substrate to an exposed surface of the GaN-based substrate101, before or after removing the GaN-based substrate101from the devices110. Typically, the second support substrate bonded to the GaN-based substrate101later can be removed by dissolving low-temperature melted metal and/or solder bonding layers between the second support substrate and the GaN-based substrate101using an appropriate etchant.

Like the first support substrate201, the second support substrate may be comprised of elemental semiconductor, compound semiconductor, metal, alloy, nitride-based ceramics, oxide-based ceramics, diamond, carbon, plastic, etc., and may comprise a single layer structure, or a multilayer structure made of these materials. A metal, such as solder, etc., or an organic adhesive, may be used for the bonding of the second support substrate to the substrate101, and is selected as necessary.

Substrate Removal

There are two techniques that can be used to remove the GaN-based substrate101from the island-like III-nitride based semiconductor layers109.

One technique is to use just the support substrate201. The interface between the growth restrict mask102and the ELO GaN-based layers105has a weak bonding strength. Thus, it is easy to peel the island-like III-nitride based semiconductor layers109from the GaN-based substrate101using the support substrate201.

Another technique is to dip the structure into a solvent for wet etching to remove the substrate101. In one embodiment, the growth restrict mask102is SiO2, which is dissolved using BHF, HF, or another etchant, before removing the GaN-based substrate101. The merit of this technique is that there is no mechanical damage when the substrate101is removed (very gently), and a wide area of SiO2is dissolved by the solvent very easily and quickly.

Thereafter, the structure is heated to separate the support substrate201and devices110from the III-nitride based substrate101. For example, a Cu support substrate201has a larger coefficient of thermal expansion (CTE) than the GaN substrate101. As shownFIG.2(e), the more expansion of the support substrate201due to heating, the stronger the stress applied to a cleaving point205. Thereafter, cleaving starts at the cleaving point205towards the opposite side of the island-like III-nitride based semiconductor layers109for the length of the cleaving surface206, which is less than the device size207.

The removal process may also occur when the temperature decreases. It does not matter when the cleaving process starts.

FIG.8shows a SEM image of the nonpolar (1-100) m-plane surface of the GaN-based substrate101indicated by the dashed circles, after the cleaving has been performed to remove the ELO GaN-based layers105.FIG.8also shows a SEM image of a polar (0001) c-plane surface as a reference. A few atomic steps can be seen on the nonpolar (1-100) m-plane surface; however, it can be seen that the surface morphology of the nonpolar (1-100) m-plane surface after the cleaving has been performed is smoother than the polar (0001) c-plane surface.

FIG.9(a)is a SEM image of the island-like III-nitride based semiconductor layers109, which is a bar with length over 300 μm after being removed from the GaN-based substrate101.FIG.9(b)is a SEM image of the cleaving surface208of the device110, following removal of the island-like III-nitride based semiconductor layers109, wherein the cleaving surface208of the device110essentially matches the opening area103and the cleaving surface208has a smooth surface morphology.

FIG.10(a)illustrates a ±15 degree miscut of a nonpolar (1-100) plane, which results in growth along semipolar (20-21) and (20-2-1) planes, respectively, andFIGS.10(b),10(c) and10(d)are images of the surface of the GaN-based substrate101after island-like III-nitride based semiconductor layers109grown on a nonpolar (1-100) m-plane, semipolar (20-21) plane, and semipolar (20-2-1) plane, respectively, have been removed.

These SEM images of the cleaving surface209of the GaN-based substrate101correspond to the opening area103, which results in very high flatness. Note that there are a higher number of step features on the surfaces of the two semipolar (20-21) and (20-2-1) substrates.

Furthermore, using a surface of a GaN-based substrate101that is not m-plane, such as a surface that is a semipolar (20-21), (20-2-1), (30-31), (30-3-1), (1-101), (1-10-1), etc., plane, also results in a cleaving surface209that is at least partially a nonpolar (1-100) m-plane.

As shown inFIG.10(e), the cleaved surface angle is measured by laser microscope. In the (20-21) case, the small flat portion shown in this image with an arrow shows an angle of 15°, i.e., (20-21) is inclined 15° from the m-plane, with a fluctuation in the range of about ±3°. Thus, the small flat portion is m-plane. Also, the small flat portion is aligned along the opening area103. It is easy to remove the semiconductor layers from substrate using cleaving in this case.

As shown inFIG.10(f), the size of the small flat portion is changed depending on the width of the opening area103. When the width of opening area103is wider, the length of the small flat portion is longer. Although the width of opening area103wider, it can be removed using the same method.

The images inFIG.10(g)show the cleaved surface of the various planes after removal.

FIG.10(h)illustrates the use of the polar c-plane surface of the GaN crystal for a cleaving plane. As noted above inFIG.8, the surface morphology of the nonpolar (1-100) m-plane surface after the cleaving has been performed is smoother than the polar (0001) c-plane surface shown as a reference. Nonetheless, the polar c-plane surface may be used for cleaving, and optimization of the method described herein should improve the surface morphology.

Therefore, even if a GaN-based substrate101other than m-plane is used, it is easy to remove the island-like III-nitride based semiconductor layers109from the GaN-based substrate101using a cleaving technique with a cleaving surface209that is an m-plane of the GaN-based substrate101. The m-plane of III-nitride is a stable plane and easily to cleave. Since island-like III-nitride based semiconductor layers109can be cleaved before excessive stress is applied, destruction of the island-like III-nitride based semiconductor layers109can be suppressed. Using this method achieves a high yield for removing island-like III-nitride based semiconductor layers109from a GaN-based substrate101.

Moreover, the III-nitride based substrate101can be recycled after the island-like III-nitride based semiconductor layers109are removed, wherein the surface of substrate101may be re-polished by a polisher. The recycling process can be done repeatedly, which lowers the cost of fabricating III-nitride based semiconductor devices.

Support Film

In another embodiment as shown inFIGS.11(a) and11(b), a support film1101may be used as an alternative to the support substrate201. In this embodiment, a layer of tape1101, which may be a polyimide tape, polymer tape, adhesive tape, UV tape, etc., with a thickness of 20-200 μm, is roll-applied to the surface of the p-electrodes layer204, as shown inFIG.11(a), and a fracture occurs at the cleaving point205upon gently pulling the tape1101away from the GaN-based substrate101for a cleaving length of206to expose cleaving surfaces208and209, as shown inFIG.11(b). To prevent excessive bending of the island-like III-nitride based semiconductor layers109comprising the device110after spalling, the outer portions of the tape1101may be used to secure the island-like III-nitride based semiconductor layers109to a frame (not shown).

FIG.11(c)is a SEM image of the island-like III-nitride based semiconductor layers109after being removed from the GaN-based substrate101using the tape1101.

In using the support film1101to remove the semiconductor layers109, the temperature cannot exceed, for example, about 150 degrees; otherwise, the support film1101may be melted and softened. However, the temperature can be decreased, for example, below about 0 degrees or more, so that the support film1101becomes hard and shrinks, which can apply strong stress to the semiconductor layers109from the differences in the thermal co-efficient between the semiconductor layers109and the support film1101.

In one embodiment, wherein the support film1101is a polymer film, the structure of the polymer film may comprise double or triple layers or more. In one example, the polymer film may have a thickness of about 80 μm, and may be comprised of polyvinyl chloride (PVC). The polymer film may have a backing material, for example, having a thickness of about 38 μm, and may be made of polyethylene terephthalate (P.E.T.). The polymer film may have an adhesive layer, for example, having a thickness of about 15 μm, and may be made of acrylic UV-sensitive adhesive. When the UV-sensitive adhesive is exposed the UV light, the stickiness of the adhesive is drastically reduced. For example, after removing the III-nitride based devices110from the substrate101, the UV-sensitive adhesive may be exposed by the UV light, which makes the support film1101easy to remove.

Deposition of n-Electrodes

Referring again toFIG.2(f), the n-electrode211is placed on the back side of the island-like III-nitride based semiconductor layers109. Typically, the n-electrode211is comprised of the following materials: Ti, Hf, Cr, Al, Mo, W, Au, but is not limited these materials.

For example, the n-electrode211may be comprised of Ti—Al—Pt—Au (with a thickness of 30-100-30-500 nm), but is not limited to those materials. The deposition of these materials may be performed by electron beam evaporation, sputter, thermal heat evaporation, etc.

Another option is to use ITO and ZnO for the electrode211, but the electrode211is not limited those materials.

Chip Division Method

Referring again toFIGS.7(a) and7(b), the chip division method has two steps. The first step is to scribe the island-like III-nitride based semiconductor layers109. The second step is to divide the support substrate201using a laser scribe, etc.

As shown inFIGS.7(a) and7(b), the chip scribe line703is fabricated by a diamond scribing machine or laser scribe machine. The chip scribe line703is fabricated on the back side of the island-like III-nitride based semiconductor layers109. The chip scribe line703may be a solid line or a dashed line.

Next, the support substrate201is divided by laser scribing as well to obtain an LD device110. It is better to avoid the ridge strip structure when the chip scribe line is fabricated.

Second Embodiment

A second embodiment is similar to the first embodiment, except for the plane of the substrate101. This embodiment is described in terms of using planes other than the nonpolar (1-100) m-plane as the growth surface on the substrate101. For example, a semipolar substrate101having a semipolar (20-21) or (20-2-1) plane as a growth surface may be used, for example, as shown inFIGS.10(c) and10(d). Thereafter, the devices110are removed from the semipolar substrate101using the same method as the first embodiment.

In other embodiments, other planes, such as (30-31), (30-3-1), (10-11), (10-1-1), etc., may be used as well.

This method also can be utilized when a hetero-substrate is used, instead of a III-nitride based substrate101. The hetero-substrate may include, but is not limited to, sapphire (m-plane), LiAlO2(LAO), m-plane SiC, Si, etc.

Third Embodiment

A third embodiment is similar to the first embodiment, except for the composition of the ELO III-nitride based layer105. Specifically, this embodiment uses AlGaN as the ELO III-nitride based layer105, as shown inFIGS.12(a)-12(i).

FIGS.12(a)-12(f)comprise SEM images of stripes along the nonpolar (1-100) plane and the semipolar (20-21) and (20-2-1) planes. All samples shown use a GaN substrate101. In these examples, the ELO AlGaN layer105has a 2-3% Al composition, a thickness of 8-12 μm, and no cracks after being grown.

FIG.12(g)is a schematic of a structure used for a near-UV LED device, including an m-plane GaN substrate101, growth restrict mask102, and ELO n-AlGaN layers105. The device structure also includes an active region106a, electron blocking layer106band p-AlGaN cladding layer106c.

FIG.12(h)is a schematic of the structure ofFIG.12(g)after removing the GaN based substrate101and depositing the n-electrode211. This embodiment can utilize a high quality and low defect density GaN-based substrate101and the ELO n-AlGaN layers105to obtain low defect density and high crystal quality semiconductor layers105,106.

By using m-plane cleaving, the GaN-based substrate101then can be removed from the near-UV device110. This is preferred with near-UV or UV devices, because a GaN-based substrate101absorbs UV light.

FIG.12(i)is a schematic of the ELO AlGaN layers105grown using a growth restrict mask102comprised of SiN on an m-plane AlN-based substrate101. In this case, the ELO AlGaN layers105have a high Al content.

Since the ELO AlGaN layers105do not coalesce, strain which is applied from the difference in thermal expansion is efficiently released by the ELO AlGaN layers105. Thereafter, the island-like AlGaN layers109(not shown) can be removed at an interface of the ELO AlGaN layers105, for example, with an AlGaN/GaN substrate101.

The ELO AlGaN layers105would be useful for near-UV or deep-UV LEDs. However, a GaN-based substrate101would absorb light that is shorter than 365 nm, due to the band-gap of GaN, and thus would not be suitable for near-UV and deep-UV LEDs. Since this method can remove the GaN-based substrate101, which absorbs UV light, this would be suitable for UV and near-UV LEDs. Further, this method can be utilized with an AlN-based substrate101, which would be suitable for a deep-UV LED.

Fourth Embodiment

A fourth embodiment differs from the first embodiment in that the ELO III-nitride layers105coalesce with each other. The process steps are shown inFIGS.13(a),13(b) and13(c), wherein the island-like III-nitride based semiconductor layers109are comprised of at least ELO GaN-based layers105, a III-nitride active region106a, and a p-AlInGaN layer106cdeposited on an m-plane GaN substrate101.

This embodiment uses a growth restrict layer (GRL)1301of small size, e.g., less than or equal to 1 μm, which is a variant of the growth restrict mask102, because it is easy to bury the GRL1301. Thicker ELO GaN-based layers105are necessary to bury a GRL1301of larger size, e.g., greater than 1 μm

The GRL1301of small size may have following dimensions: width is about 0.8-5 μm and thickness is about 0.1-1 μm. By forming the GRL1301of small size, the thickness of the ELO GaN-based layers105can be made as thin as 1 μm or less.

A thin ELO GaN-based layer105is useful for VCSELs and other devices. For example, the VCSEL1401ofFIG.14is comprised of a first distributed Bragg reflector (DBR1)1402, ELO GaN-based layers1403, active region1404, p-AlInGaN layers1405, SiO2layer1406, ITO layer1407, second DBR21408and n-electrode1409. Moreover, the VCSEL1401has a cavity length1410that is preferably short in order to avoid large optical loss.

In this regard, the opening area103is extremely flat due to the cleaving technique. A very flat surface is required where a DBR is deposited. Utilizing cleavability of the m-plane is preferable. Therefore, it is preferable that the location for depositing the DBR should include at least a part of the cleaving surface205.

Before cleaving, it may be better to etch the island-like III-nitride based semiconductor layers109, as described inFIG.13(b). In this example, the etch has exposed the GRL1301. Laser ablation can also be used to expose the GRL1301.

Using this embodiment, the island-like III-nitride based semiconductor layers109can be removed from the GaN-based substrate101in an easy manner. As shown inFIG.13(c), tape1101can be used when removing the epitaxial layers109. Thereafter, as shown inFIG.14, the VCSEL1401can be fabricated by conventional methods.

Fifth Embodiment

A fifth embodiment is similar to the fourth embodiment, except without using a GRL1301or ELO III-nitride based layers105. The process steps are shownFIGS.15(a),15(b)15(c),15(d),15(e) and15(f).

After growing the III-nitride based semiconductor layers106on an m-plane surface of the GaN-based substrate101, as shown inFIG.15(a). The p-electrodes204are deposited on the III-nitride based semiconductor layers106, as shown inFIG.15(b). The III-nitride based semiconductor layers106are etched1501, as shown inFIG.15(c). The tape1101is attached to the p-electrodes204, as shown inFIG.15(d), and the III-nitride based semiconductor layers106are removed from the substrate101by peeling the tape1101at the cleaving point205, as shown inFIG.15(e). By forming such a structure, a strong strain concentration1502is applied to the cleaving point205shown inFIG.15(e).

In order to obtain a high yield when removing the GaN-based substrate101, an angled dry etching1501can be used, as shown inFIGS.15(c),15(d) and15(e). The angled dry etching1501can be performed by positioning the structure in a tilted manner in a dry etching chamber, as shown inFIG.15(f).

This embodiment is very useful for a VCSEL, dual dielectric cladding laser, etc., because this method can determine a cleaving point205by the depth of the etching1501.

Sixth Embodiment

A sixth embodiment is similar to the first, second, and third embodiments, except for the shape of the opening area103. This embodiment is used to fabricate micro-LEDs.

Patterned substrates101are shownFIGS.16(a) and16(b). The patterned substrates101can include small size opening areas103, such as hexagonal holes, or other shapes, such as circular, triangular, rectangular, etc., holes. In this example, the patterned substrates101are obtained using a growth restrict mask102with a plurality of openings103.

FIG.16(a)illustrates the diameter d1of the opening areas103(i.e., of the hexagonal shape forming the opening) in one embodiment. In this embodiment, the value of d1is 0.5-20 μm, and more preferably, the value for d1is about 2 μm.

FIG.16(b)illustrates the diameter d2of the opening areas103(i.e., of the hexagonal shape forming the opening) in another embodiment. In this embodiment, the value of d2is 5-60 μm, and more preferably, the value for d1is about 15 μm.

An LED fabrication process can be used in the method which describes the above embodiment.

Seventh Embodiment

A seventh embodiment is similar to the third embodiment, except for the use of a photo-electro-chemical (PEC) etching technique. This embodiment is illustrated inFIGS.17(a)-17(f), which describe a method for manufacturing a semiconductor device comprising the steps of: providing a III-nitride substrate101; growing one or more InAlGaN-based layers1701on the III-nitride based substrate101; growing one or more InAlGaN sacrificial layers1702on the InAlGaN-based layers1701; growing one or more additional InAlGaN-based semiconductor layers1703,1704and1705to form a semiconductor device110; processing the devices110; etching the InAlGaN-based layers1701to expose the InAlGaN sacrificial layers1702; forming an undercut notch1706in the sacrificial InAlGaN layers1702; bonding the InAlGaN-based layers1703,1704,1705to a support substrate201; and removing the III-nitride substrate101by cleaving.

Specifically, the method includes the following steps:1. Expose the InAlGaN sacrificial layers1702. As shown inFIG.17(a), the InAlGaN sacrificial layers1702are grown between the InAlGaN layers1701and1703. The semiconductor devices110are comprised of InAlGaN layers1703,1704,1705. For example, the devices110may comprise LEDs comprised of n-type GaN, InGaN/GaN multiple quantum wells (MQWs) and p-type GaN.2. Etching to expose InAlGaN sacrificial layers1702. As shown inFIG.17(b), dry etching is performed to expose the InAlGaN sacrificial layers1702. In addition, angle etching is better for cleaving.3. Forming an undercut notch1706in the InAlGaN sacrificial layers1702. As shown inFIG.17(c), the InAlGaN sacrificial layers1702are partially but not fully etched and an undercut notch1706is formed.4. Bonding the support substrate201to the devices110using bonding materials. As shown inFIG.17(d), p-electrodes1707of the devices110are flip-chip bonded to a support substrate201, such as a carrier wafer comprised of Si, Cu, etc., using metal-metal bonding or soldering techniques. Support films1101may also be used.5. Cleaving to remove the III-nitride based substrate101. As shown inFIG.17(e), cleaving is performed at a cleaving point205to remove the devices110from the III-nitride based substrate101along a cleaving length206, which is less than the device size207. At least part of an m-plane is used for cleaving.FIG.17(f)shows the device110with the substrate101removed.
InAlGaN Sacrificial Layers

In this embodiment, the InAlGaN sacrificial layers1702include In, Al, Ga, N, as well as impurities, such as Mg, Si, Zn, O, C, H, etc. The InAlGaN sacrificial layers1702have a band-gap larger than wavelength of an ultraviolet (UV) light source. For example, a 405 nm UV light is used and the band-gap of the sacrificial layers1702is larger than 3.06 eV. In this case, the sacrificial layers1702can absorb the UV light to generate the electrons and holes during PEC etching.

Etching Sacrificial Layers

In this embodiment, the etching region is the place which is etched by dry etching and/or wet etching to expose the InAlGaN sacrificial layer1702. Angle etching is performed, since it can be helpful for the cleaving.

Undercut Notch in the InAlGaN Sacrificial Layers

In this embodiment, the undercut notch1706in the InAlGaN sacrificial layers1702can be formed by band-gap-selective PEC etching.

Also in this embodiment, the cleaving plane for the III-nitride materials is a nonpolar m-plane or a semipolar plane. Therefore, at least a partial m-plane is used for cleaving, which helps the cleaving occur easily, as well as result in a smooth surface.

Removing the Substrate by PEC Etching

As shown inFIG.17(a), a bulk III-nitride substrate101with a nonpolar m-plane or semipolar plane orientation is provided. Growth is performed on the substrate101using MOCVD to fabricate n-type InAlGaN1701, InxAlyGa1−(x+y)N sacrificial layers1702, n-type InAlGaN1703, an InGaN/GaN MQW active region1704, and p-type InAlGaN1705.

Trimethylgallium (TMGa), trimethylindium (TMIn) and triethylaluminium (TMAl) are used as the group-III elements source. Ammonia (NH3) is used as the raw gas to supply Nitrogen. Hydrogen (H2) and nitrogen (N2) are used as carrier gases. Saline and Bis(cyclopentadienyl)magnesium (Cp2Mg) are used as the n-type and p-type dopants. The pressure is set to be 50 to 760 Torr. The GaN growth temperature ranges from 900 to 1250° C. and the InAlGaN sacrificial layer growth temperature is from 800 to 1150° C.

The thickness of the InxAlyGa1−(x+y)N sacrificial layers1702is from 1 to 100 nm. The composition of x and y is from 0 to 1 and x+y also ranges from 0 to 1, as determined by the PEC etching.

For example, a 405 nm ultraviolet (UV) LED array may be used for PEC etching. Therefore, a band-gap of the InxAlyGa1−(x+y)N sacrificial layer1702of less than 3.06 V is desired, so that the sacrificial InxAlyGa1−(x+y)N layer1702can absorb the UV light to generate the electrons and holes during PEC etching.

InxAlyGa1−(x+y)N/GaN stacks could be used as the sacrificial layers1702as well. For example, a 5 nm thick In0.08Ga0.92N layer can be used as the sacrificial layer1702.

Another example is to form the undercut notch1706using laser ablation. A 405 nm laser may be used in this example, and the sample is exposed to the laser source by carefully controlling the wafer position.

Angle etching may be performed by dry etching, such as reactive-ion etching (RIE), etc. For example, SiCl4may be used as the etching gas for RIE. The etching angle is from 0 to 90 degrees, which is useful for the cleaving process. The etching depth is from 10 nm to 20 μm, to expose the InxAlyGa1−(x+y)N sacrificial layer1702.

PEC etching is performed to form an undercut notch1706in the region of the InGaN sacrificial layers1702. The samples are dipped in a KOH solution and absorb the light from the 405 nm UV LEDs array. Then, the InAlGaN sacrificial layer1702would start to decompose by PEC. The InAlGaN sacrificial layer1702is partially but not fully etched to form the undercut notch1706. For example, the width of the device is 100 μm and the size of the undercut notch1706in the InAlGaN sacrificial layer1702may range from 1 to 45 μm.

In this embodiment, as shownFIG.17(e), the chip size is wider than cleaving length. This allows the semiconductor layers to be easily removed, even with less force or pressure. The use of less force or pressure avoids degradation of the device and reduction in the yield.

Process Steps

FIG.18is a flowchart that illustrates the method of removing III-nitride based substrates from III-nitride based semiconductor layers, after forming devices from the III-nitride based semiconductor layers, so that the III-nitride based substrates can be recycled, according to one embodiment of the present invention.

Block1801represents the step of providing a base substrate101. In one embodiment, the base substrate101is a III-nitride based substrate101, such as a GaN-based substrate101.

Block1802represents an optional step of depositing an intermediate layer on the substrate101. In one embodiment, the intermediate layer is a III-nitride based layer, such as a GaN-based layer.

Block1803represents the step of forming a growth restrict mask102on or above the substrate101, i.e., on the substrate101itself or on the intermediate layer. The growth restrict mask102is patterned to include a plurality of stripes102aand opening areas103.

Block1804represents the step of growing one or more III-nitride based layers105on or above the growth restrict mask102using epitaxial lateral overgrowth, wherein the epitaxial lateral overgrowth of the III-nitride layers105extends in a direction parallel to the opening areas103of the growth restrict mask102, and the epitaxial lateral overgrowth is stopped before the III-nitride layers105coalesce on the stripes102aof the growth restrict mask102. In one embodiment, the ELO III-nitride based layer105is an ELO GaN-based layer105.

Block1805represents the step of growing one or more additional III-nitride based semiconductor layers106on the ELO III-nitride based layer105. These additional III-nitride based semiconductor layers106, along with the ELO III-nitride based layer105, create one or more of the island-like III-nitride based semiconductor layers109.

Block1806represents the step of bonding the island-like III-nitride based semiconductor layers109to a support substrate201or film1101. The island-like III-nitride based semiconductor layers109are flip-chip bonded to a support substrate201with metal or solder204deposited thereon using metal-metal bonding or soldering techniques with p-electrodes204, while the film1101is roll-applied to the p-electrodes204.

Block1807represents the step of removing the island-like III-nitride based semiconductor layers109from the substrate101using a cleaving technique on a surface of the substrate101, which includes mechanically separating or peeling the island-like III-nitride based semiconductor layers109from the substrate101.

The surface of the substrate101on which the cleaving technique is performed is an m-plane surface209of the substrate101, and the island-like III-nitride based semiconductor layers109have a cleaved surface208after being removed from the substrate101, wherein the cleaved surface208at least comprises an m-plane surface. The island-like III-nitride based semiconductor layers109are also at least partially comprised of m-plane layers.

The cleaving technique is performed on the surface of the substrate101at a cleaving point205for a cleaving length206, and the cleaving length206may be narrower than a size207of a device110formed from the island-like III-nitride based semiconductor layers109.

The growth restrict mask102may be at least partially dissolved by a solvent, before the cleaving technique is performed. In addition, this step may include applying stress to the island-like III-nitride based semiconductor layers109due to differences in thermal expansion between the substrate101and the support substrate201or film1101bonded to the island-like III-nitride based semiconductor layers109to expose the cleaving point205.

Block1808represents the step of depositing n-electrodes211on the back side of the island-like III-nitride based semiconductor layers109, which is exposed by the lift-off of the substrate101.

Block1809represents the step of chip scribing to separate the devices110. This step may also include the etching of facets for laser diode devices110.

Block1810represents the resulting product of the method, namely, one or more III-nitride based semiconductor devices fabricated according to this method, as well as a substrate101that has been removed from the devices and is available for recycling and reuse.

Advantages and Benefits

The present invention provides a number of advantages and benefits:Utilizing the cleavage of the m-plane of III-nitride achieved a high yield when removing III-nitride based semiconductor layers109from the substrate101.Expensive III-nitride based substrates101can be reused after the substrates101are removed from the device110layers.High quality device110layers may be obtained using a substrate101of the same or similar materials, with a very low defect density.Using the same or similar materials for both the substrate101and the device layers108can reduce the strain in the device110layers.Using materials with the same or similar thermal expansion for both the substrate101and the device110layers can reduce bending of the substrate101during epitaxial growth.Slicing the substrate101from a bulk crystal with a miscut orientation maintains the uniformity of thickness between the device110layers and produces a higher yield.Layers105grown by ELO are of high quality.The ELO layers105do not coalesce with each other, and internal strain is released, which helps to avoid any occurrences of cracks. For device110layers that are AlGaN layers, this is very useful, especially in the case of high Al content layers.The island-like III-nitride based semiconductor layers109are formed in isolation, so tensile stress or compressive stress does not fall upon other island-like III-nitride based semiconductor layers109.Also, the growth restrict mask102and the ELO layers105are not bonded chemically, so the stress in the ELO layers105and additional layers106can be relaxed by a slide caused at the interface between the growth restrict mask102and the ELO layers105.The existence of the no-growth regions104between each of the island-like III-nitride based semiconductor layers109provides flexibility, and the substrate101is easily deformed when external force is applied and can be bended. Therefore, even if there occurs a slight warpage, curvature, or deformation in the substrate101, this can be easily corrected by a small external force, to avoid the occurrence of cracks. As a result, the handling of the substrates101by vacuum chucking is possible, which makes the manufacturing process of the semiconductor devices more easily carried out.The no-growth region104makes it is easy to dissolve a large area of the growth restrict mask102.Device110layers of high quality semiconductor crystal can be grown by suppressing the curvature of the substrate101, and further, even when the device110layers are very thick, the occurrences of cracks, etc., can be suppressed, and thereby a large-area semiconductor device can be easily realized.Thermal management of the devices110improve significantly due to the flip-chip bonding on the support substrate201.The device110size is reduced by about 10 times when compared to the commercially available devices.The fabrication method can also be easily adopted to large size wafers (>2 inches).
Modifications and Alternatives

A number of modifications and alternatives can be made without departing from the scope of the present invention.

For example, the present invention may be used with III-nitride based substrates of other orientations. Specifically, the substrates may be basal nonpolar m-plane {1 0 −1 0} families; and semipolar plane families that have at least two nonzero h, i, or k Miller indices and a nonzero 1 Miller index, such as the {2 0 −2 −1} planes. Semipolar substrates of (20-2-1) are especially useful, because of the wide area of flattened ELO growth.

According to the present invention, the crystallinity of the island-like III-nitride based semiconductor layers laterally growing upon the growth restrict mask from a striped opening of the growth restrict mask is very high, and III-nitride based semiconductor layers made of high quality semiconductor crystal can be obtained.

Furthermore, two advantages may be obtained using a III-nitride based substrate. One advantage is that a high-quality island-like III-nitride based semiconductor layer can be obtained, such as with a very low defects density than using a sapphire substrate. Another advantage, by using a similar or same material for both the epilayer and the substrate, is that it can reduce the strain in the epitaxial layer. Also, thanks to a similar or same thermal expansion, the method can reduce the amount of bending of the substrate during epitaxial growth. The effect, as above, is that the production yield can be high in order to improve the uniformity of temperature.

On the other hand, a foreign or hetero-substrate, such as sapphire (m-plane), LiAlO2, SiC, Si, etc., can be used to grow the III-nitride based semiconductor layers. A foreign or hetero-substrate is easy to remove due to weak bonding strength at the cleaving point.

Consequently, the present invention discloses: a substrate comprised of a III-nitride based semiconductor; a growth restrict mask with one or more striped openings disposed directly or indirectly upon the substrate; and one or more island-like III-nitride based semiconductor layers grown upon the substrate using the growth restrict mask in the (1-100) plane orientation, wherein the striped openings of the growth mask extend in a direction parallel to the 0001 direction of the III-nitride based semiconductor layer.

Slicing the substrate from the GaN bulk crystal with a mis-cut orientation maintains the uniformity of thickness between the island-like III-nitride based layers.

In one embodiment, the growth restrict mask is deposited by sputter or electron beam evaporation or PECVD (plasma-enhanced chemical vaper deposition), but is not limited to those methods.

Also, when a plurality of island-like III-nitride based semiconductor layers are grown, these layers are separated from each other, that is, formed in isolation, so tensile stress or compressive stress generated in each III-nitride based semiconductor layer is limited within the III-nitride based semiconductor layer, and the effect of the tensile stress or compressive stress does not fall upon the other III-nitride based semiconductor layers. However, it is not necessary that the island-like III-nitride based semiconductor layers be separated.

Also, as the growth restrict mask and the III-nitride based semiconductor layer are not bonded chemically, the stress in the III-nitride based semiconductor layer can be relaxed by a slide caused at the interface between the growth restrict mask and the III-nitride based semiconductor layer.

Also, the existence of gaps between each of the island-like III-nitride based semiconductor layers results in the substrate having rows of a plurality of island-like III-nitride based semiconductor layers, which has flexibility, and therefore, it is easily deformed when external force is applied and can be bended.

Therefore, even if there occurs a slight warpage, curvature, or deformation in the substrate, this can be easily corrected by a small external force, to avoid the occurrence of cracks. As a result, the handling of substrates by vacuum chucking is possible, which makes the manufacturing process of the semiconductor devices more easily carried out.

As explained, island-like III-nitride based semiconductor layers made of high quality semiconductor crystal can be grown by suppressing the curvature of the substrate, and further, even when the III-nitride based semiconductor layer is very thick, the occurrences of cracks, etc., can be suppressed, and thereby a large area semiconductor device can be easily realized.

Finally, the present invention may be used to fabricate different opto-electronic device structures, such as a light-emitting diode (LED), laser diode (LD), Schottky barrier diode (SBD), or metal-oxide-semiconductor field-effect-transistor (MOSFET). The present invention may also be used to fabricate other opto-electronic devices, such as micro-LEDs, vertical cavity surface emitting lasers (VCSELs), edge-emitting laser diodes (EELDs), and solar cells.

Conclusion

This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.