Patent ID: 12255540

DETAILED DESCRIPTION

A fly-back converter including a fly-back synchronous rectifier (SR) controller with a circuit for rapidly turning off a SR to avoid cross-conduction between the SR and power switch on the primary side during continuous conduction mode (CCM) operation, and methods of operating the same are disclosed for improving efficiency and reliability across a wide range of loads and power delivery applications. The system and methods of the present disclosure are particularly useful in Universal Serial Bus Power Delivery (USB-PD) applications with wide output power applications ranging from 5 W to 100 W, and output voltages from 3.3V to 21.5V (or up to 28V, if Extended Power Range, or EPR, specification is followed).

An embodiment of a fly-back converter including a secondary or Synchronous Rectifier (SR)-controller operable to substantially eliminate cross-conduction when operating in CCM without receiving turn-on information from a primary side or power-switch (PS)-controller in accordance with the present disclosure will now be described with reference toFIG.3.

Referring toFIG.3, the fly-back converter300generally includes a transformer302having a primary winding (NP) on a primary side304electrically connected or coupled to an AC input, and a secondary winding (NS) on a secondary side306coupled to a DC output.

On the primary side304a rectifying circuit, such as a bridge rectifier308, and one or more input filters coupled to a first terminal302aof the transformer302rectify an AC input voltage and supply input power to the primary winding of the transformer302. The input filters can include a first input filter310having a capacitor (C1) coupled to or across an output of the rectifier308, and a snubber312, including a resistor or resistive element (R1) and a capacitor (C2) coupled in parallel between the first terminal302aof the transformer302and a cathode of a diode or rectifier (D1) having an anode coupled to a second terminal302bof the transformer. Generally, as in the embodiment shown, the fly-back converter300further includes a primary or power switch (PS314), such as a primary field effect transistor (PR_FET), having a first or drain node coupled to the second terminal302bof the transformer302, a second or gate node coupled to a primary-side or PS controller316, and a third or source node coupled to the PS-controller and, through a current sensing element, such as a resistive element (RCS) to ground to sense a primary side current (I_primary) flowing through the primary winding when the PS314is closed or conducting. The PS controller316is further coupled to the first terminal302aof the transformer302through a resistive element (Rin) to receive a voltage or signal equal or proportional to the rectified AC input voltage.

On the secondary side306the fly-back converter300includes a secondary-switch or synchronous rectifier (SR318), such as a synchronous rectifier field effect transistor (SR_FET), coupled between a fourth terminal302dof the transformer302and the ground terminal of the DC output. The first or drain node of the SR318is coupled to the fourth terminal302dof the transformer302and through an external resistor (Rext) a SR sense pin (SR_PIN) on the secondary-side or SR-controller320; a second or gate node coupled to a SR gate drive pin (SR_GDRV) on the SR-controller to drive or control the SR; and a third or source node coupled to the ground terminal of the DC output.

The fly-back converter300further includes on the secondary side306a filter or output capacitor322coupled between a third terminal302cof the transformer302and the ground terminal to provide a DC output voltage to an output interface or connector324. Although not shown, the output connector324is generally further coupled to the SR-controller320through a number of communication channels to support various charging protocols. Suitable output connectors324can include those compatible with and supporting standard and proprietary charging protocols including Universal Serial Bus Power Delivery USB PD2.0 and USB PD3 with Programmable Power Supply (PPS), Qualcomm® Quick Charge, Samsung® AFC, and Apple® charging protocols. For example, the connector can include a Universal Serial Bus type C (USB-C) compatible connector where the PSC fly-back converter300is compliant with the USB protocol to provide a DC output voltage of about 3.3 VDC to about 21.5 VDC at a current of from about 0 to about 5000 milliamps (mA).

It is noted that the PS-controller316and the SR-controller320may be integrally formed on a single integrated circuit (IC) chip, or as separate IC chips either discretely packaged or packaged together as part of a multichip module.

It is further noted that unlike in conventional fly-back converters, such as shown inFIG.1, there is no connection through an electrical isolation circuit for coupling turn-on information for the PS314from the PS-controller316on the primary side304to the SR-controller, or any direct, high-voltage connection between the drain of the SR_FET318and the SR-controller320for sensing the voltage on the drain thereof. By direct it is meant connection other than through a resistive element such as the external resistor Rext.

In accordance with a first embodiment of the present disclosure SR-controller320of the fly-back converter300includes an active clamping circuit operable to turn OFF the SR318to minimize or substantially eliminate cross-conduction when operating in CCM.

FIG.4is a schematic block diagram depicting a partial schematic of a fly-back converter400including one such embodiment of a SR-controller402with an active clamping circuit404. As with the fly-back converter described above with respect toFIG.3, the fly-back converter400includes in addition to the SR-controller402a transformer406having a primary winding coupled to a rectified AC input through a PS, and a secondary winding coupled to a DC output taken across an output capacitor408through a synchronous rectifier (SR410), such as an SR_FET. The SR410has a drain coupled to the secondary winding of the transformer406and, through an external resistor (Rext) to a SR pad or pin (SR_PIN) on the SR-controller402, a source coupled to the output capacitor408and DC output, and a gate coupled to a gate drive pad or pin (SR_GDRV) on the SR-controller.

Referring toFIG.4, the SR-controller402includes in addition to the active clamping circuit404, a negative-sensing (NSN) comparator412, zero-crossing detector (ZCD) comparator414, and a gate drive circuit or gate driver416coupled to the gate of the SR410through the SR_GDRV pad or pin.

The NSN comparator412has a first, inverting input coupled to the drain of the SR410through the SR_PIN and resistor Rext, and a second, non-inverting input coupled to a reference voltage (NSN_REF), generally from −700 millivolts (mV) to +200 mV, and is operable to signal the gate driver416to turn-on the SR410when a voltage on the drain (SR-drain-voltage) changes from positive to negative.

The ZCD comparator414includes a first, inverting input coupled to a reference voltage (ZCD_REF) set at a predetermined voltage below the zero-crossing, generally about −5 mV, and a second, non-inverting input coupled through the SR_PIN and Rext to the to the drain of the SR410. The ZCD comparator414is operable to signal the gate driver416to turn-off the SR410when a voltage on the SR_PIN (Vpin) has or is about to cross zero-crossing due to a change in SR-drain-voltage caused by cross conduction or turning on of the PS314(not shown in this figure) in the primary side in CCM mode or due to current through SR410reaching OA in DCM mode.

The gate driver416generally includes a number of transistors and voltage supplies including at least a first transistor configured or operable to receive a signal from the NSN comparator412to apply a voltage to the gate of the SR_FET to turn on the SR410, and a second transistor operable to couple the gate of the SR_FET to turn off the SR in response to the signal output by the ZCD comparator414.

A parasitic internal capacitance (CPARA418) shown inFIG.4coupled between the SR_PIN and ground represents a total stray and parasitic capacitance of components and wiring or leads on SR_PIN in the SR-controller402. This parasitic capacitance is also present in conventional secondary fly-back controllers in which it is particularly problematic because when the SR-drain-voltage goes up above 0V due to the PS on the primary turning on, the capacitor CPARAmust charge up before the voltage on the SR_PIN (Vpin) rises sufficiently to cause the ZCD comparator414to signal the gate driver416to turn off the SR410, causing cross-conduction between a PS in the primary side and the SR, resulting a high negative current in the secondary side and consequentially a reduced efficiency as well as possible damage to the fly-back converter.

In contrast, in the SR-controller402of the present disclosure the active clamping circuit404coupled to the SR_PIN is configured or operable to clamp the voltage on the SR_PIN (Vpin) when the SR410is turned on to a clamping voltage (Vclamp) below a predetermined voltage immediately below a ZCD threshold voltage at which the ZCD comparator signals the gate driver416to turn off the SR410. As a result, the active clamping circuit404, the ZCD comparator414and the gate driver416are capable of quickly turning off the SR410following a rise of a SR-drain-voltage caused by turning on the PS before current drawn from the secondary side of the transformer406is completely discharged, thereby minimizing or eliminating cross-conduction between the PS and the SR when the fly-back converter400is operating in the CCM. Because the capacitor CPARA418only has to charge up from, for example, from −10 mV to 0V, instead of from −200 mV as in a conventional SR controller lacking an active clamping circuit, the voltage on the SR_PIN (Vpin) is able to cross the ZCD threshold within very fast time for example, about 20 nanoseconds (ns), which is detected by ZCD comparator414and signal the gate driver416to turn off the SR410. Preferably, the active clamping circuit404, the ZCD comparator414and the gate driver416are operable to turn off the SR410within very short time for example, about 50 ns, from a sharp rise of the SR-drain-voltage above 0V.

Referring again toFIG.4, in the embodiment shown the active clamping circuit404, includes an n-channel field effect transistor (NFET420) with a drain coupled to a voltage supply (VDD), a source coupled to the SR_PIN, and a gate coupled to a differential amplifier (OPAMP422). The OPAMP422includes a first, inverting input coupled to the SR_PIN, a second, non-inverting input coupled to a reference voltage, ground or 0V in the embodiment shown, and implements an offset voltage internally to clamp voltage on the SR_PIN (Vpin) when the SR410is turned on to the clamping voltage (Vclamp). When Vpin begins to drop below Vclamp and a difference between Vpin and the reference voltage (ground) the OPAMP422turns on the NFET420, coupling the SR_PIN to VDDdrawing a greater current through and a greater voltage across resistor Rext, clamping Vpin to Vclamp. When Vpin rises above Vclamp due to the PS turning on, the OPAMP422is operable to turn off the NFET420, CPARA418rapidly charges from Vclamp to the ZCD threshold voltage, and the ZCD comparator414signals the gate driver416to turn off the SR410.

A method of operating a fly-back converter400with a SR-controller402including an active clamping circuit404to minimize or substantially eliminate cross-conduction when operating in CCM will now be described with reference to the flowchart ofFIG.5, and the graphs and timing diagrams ofFIGS.6A to6C.

Referring toFIGS.5and6A, the method begins with turning off of Primary FET causing the SR-drain-voltage602and Vpin604to quickly drop to a negative voltage (step502) which is detected and SR is turned-on on the secondary side of the transformer. In a conventional SR controller lacking an active clamping circuit, the voltage on the SR_PIN (conventional Vpin606) closely follows the drop in the SR-drain-voltage602to a substantial negative voltage, for example −200 mV. In the SR controller ofFIGS.3and4however, as noted above when Vpin reaches Vclamp608the OPAMP turns on the NFET, coupling the SR_PIN to VDDdrawing a greater current through and a greater voltage across resistor Rext, clamping Vpin to Vclamp (step504).

Next, there is a gradual rise in SR-drain-voltage602at a first slope beginning at time to as a current is drawn from the secondary side of the transformer through the SR (step506). This continues until the secondary side of the transformer is completely discharged, or in continuous conduction mode (CCM) until the PS on the primary side of the transformer is turned on the before the current drawn from the secondary side of the transformer is completely discharged causing a change in the rise of the SR-drain-voltage602to a second slope greater than the first slope beginning at time t1(step508).

Referring toFIGS.5,6A and6B, as the SR-drain-voltage602rises above Vclamp608, Vpin604also begins to rise to a ZCD threshold610, causing the ZCD comparator to pass a signal612to the gate driver to quickly turn off the SR, minimizing or substantially eliminating cross-conduction between the PS and the SR (step510). As noted previously because the Vpin604is clamped to Vclamp only slightly below the ZCD threshold610the voltage on the SR_PIN (Vpin) is able to cross the ZCD threshold within very fast time for example, about 20 ns, and the active clamping circuit, the ZCD comparator and the gate driver are operable to turn off the SR within very short time for example about 50 ns.

Referring toFIGS.6A and6C, in a conventional SR controller lacking an active clamping circuit, the voltage on the SR_PIN (conventional Vpin606) must begin rising from a lower, or greater negative voltage, increasing the time required to charge the parasitic capacitor (CPARA) taking a significantly greater time of 200 ns for Vpin606to cross the ZCD threshold610, and the ZCD comparator to pass a signal614to the gate driver to turn off the SR.

In another embodiment the SR-controller320of the fly-back converter300includes a closed-loop differentiator circuit operable to detect the change in a rise of a SR-drain-voltage, and to generate a PS-on-detection (PS_det) signal to the gate driver, turning off the SR eliminating cross-conduction between the PS and the SR when operating in CCM.

FIG.7is a schematic block diagram depicting a partial schematic of a fly-back converter700including one such embodiment of a SR-controller702with a closed-loop differentiator circuit704. As with the fly-back converter described above with respect toFIG.3, the fly-back converter700includes in addition to the SR-controller702a transformer706having a primary winding coupled to a rectified AC input through a PS, and a secondary winding coupled to a DC output taken across an output capacitor708through a synchronous rectifier (SR710), such as an SR_FET. The SR710has a drain coupled to the secondary winding of the transformer706and, through an external resistor (Rext) to a SR pad or pin (SR_PIN) on the SR-controller702, a source coupled to the output capacitor708and DC output, and a gate coupled to a gate drive pad or pin (SR_GDRV) on the SR-controller.

Referring toFIG.7, the SR-controller702includes in addition to the closed-loop differentiator circuit704, a negative-sensing (NSN) comparator712, zero-crossing detector (ZCD) comparator714, and a gate drive circuit or gate driver716coupled to the gate of the SR710through the SR_GDRV pad or pin.

As with the SR-controller402described above with reference toFIG.4, the NSN comparator712has a first, inverting input coupled to the drain of the SR710through the SR_PIN and resistor Rext, and a second, non-inverting input coupled to a reference voltage (NSN_REF), generally from −700 millivolts (mV) to +200 mV, and is operable to signal the gate driver716to turn-on the SR710when a voltage on the drain (SR-drain-voltage) changes from positive to negative.

The ZCD comparator714includes a first, inverting input coupled to a reference voltage (ZCD_REF) set a predetermined voltage below the zero-crossing, generally about −5 mV, and a second, non-inverting input coupled through the SR_PIN and Rext to the to the drain of the SR710. Unlike the ZCD comparator414described above with reference toFIG.4, the ZCD comparator714is a discontinuous conduction mode ZCD comparator operable to signal the gate driver716to turn-off the SR710when a voltage on the SR_PIN (Vpin) has or is about to cross zero-crossing due to a completed discharge of the secondary side of the transformer706.

The gate driver716generally includes a number of transistors and voltage supplies including at least a first transistor configured or operable to receive a signal from the NSN comparator712to apply a voltage to the gate of the SR_FET to turn on the SR710, and a second transistor operable to couple the gate of the SR_FET to turn off the SR in response to the signal output by the ZCD comparator714or the PS_det signal output by the closed-loop differentiator circuit704.

A capacitor (CPARA718) shown inFIG.7coupled between the SR_PIN and ground represents a total stray and parasitic capacitance of components and wiring or leads in the SR-controller702.

Referring again toFIG.7, in the embodiment shown the closed-loop differentiator circuit704, includes a high pass filter through which a first, inverting input of a differentiator is coupled to the SR_PIN, the high pass filter is operable to generate a first derivative of a change in the rise of the Vpin and to couple the first derivative (Deriv1) to a first, inverting input of a differentiator720. The high pass filter includes a first internal capacitor C1through which the SR_PIN is coupled to ground, and an output node to the first input of a differentiator between the resistor R1and capacitor C1. The closed-loop differentiator circuit704further includes a first PFET transistor (MP1) with a gate coupled to an output of the differentiator720, a drain coupled to a voltage supply (VDD), and a source coupled to a second, non-inverting input of the differentiator to form a closed loop. The source of transistor MP1is further coupled to ground through a second capacitor (C2) to generate a first reference current (IREF), and the transistor MP1is operable to charge the capacitor C2so that a voltage coupled to the second input of the differentiator720approaches or forms a copy (Dervi1_copy) of the first derivative coupled to the first input.

The closed-loop differentiator circuit704further comprises a second PFET transistor (MP2) with a gate coupled to the output of the differentiator720, a drain coupled to VDD, and a source coupled to ground to via a second reference current (IREF+1′) and to a logic buffer722. The second transistor MP2is operable to generate a second derivative (Deriv2) of the change in the rise of Vpin, and to couple the second derivative to the logic buffer, which is operable to generate and couple the PS_det signal to the gate driver716.

A method of operating a fly-back converter700with a SR-controller702including a closed-loop differentiator circuit704to minimize or substantially eliminate cross-conduction between a PS on the primary side and a SR on the secondary when operating in CCM will now be described with reference to the flowchart ofFIG.8, and the graphs and timing diagrams ofFIGS.9A to9E.

Referring toFIGS.8and9A, the method begins with turning off of Primary FET causing the SR-drain-voltage902and Vpin904to quickly drop to a negative voltage (step802) which is detected and SR is turned-on on the secondary side of the transformer. As there is no clamping circuit, the voltage on the Vpin904) closely follows the drop in the SR-drain-voltage902to a substantial negative voltage, for example −200 mV.

Next, there is a gradual rise in SR-drain-voltage902at a first slope beginning at time to as a current is drawn from the secondary side of the transformer through the SR, causing the high pass filter formed by C1and R1to produce or generate a first derivative (Deriv1906inFIG.9B) of the Vpin, and the differentiator720following to produce a second derivative (Deriv2908) of the Vpin (step804). During time t0to t1, Vpin904is following SR-drain-voltage generating a constant current in Cpara718and C1, resulting in a constant non-zero value of Deriv1906. Hence, Deriv1_copy settles at the same constant value and I(C2)=0. Deriv1is equal to or represented by A*d(Vpin)/dt, where A is _R1*C1, and Deriv2is equal to or represented by I(c2), which is equal to C2*d(Deriv1)/dt.

At t1, as the slope of the SR-drain-voltage902changes, although Vpin904changes slowly, current through C1increases immediately, causing Deriv1906to shoot up above its constant value. The differentiator720starts pumping current into C2through MP1in an attempt to make Deriv1_copy on the second non-inverting input of the differentiator equal to Deriv1906(step806). The current through MP2, I (MP2) or Deriv2908, which is equal to N*I (MP1), is compared against current IREF+1′910to generate the detection signal (Prim_det912), and the signal coupled through buffer722to the gate driver716(step808). After the SR710turns off and SR-drain-voltage902becomes constant, IREF slowly discharges derive1_copy to 0V. The current IREF at time t0is designed such that, for a positive value of Deriv1(for example, less than 1 mV) the signal Prim_det912does not trip the differentiator720.

Thus, a fly-back converter including a SR controller to minimize or substantially eliminate cross-conduction between a PS on a primary side and a SR on a secondary side when operating in CCM have been disclosed. Embodiments of the present invention have been described above with the aid of functional and schematic block diagrams illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

It is to be understood that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.

The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.