Patent ID: 12189253

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in various aspects without departing from the gist thereof, and is not to be construed as being limited to the description of the embodiments exemplified below. In addition, in order to make the description clearer with respect to the drawings, the width, thickness, shape, and the like of each part may be schematically represented in comparison with actual embodiments, but the schematic drawings are merely examples, and do not limit the interpretation of the present invention. Further, in the present specification and the drawings, the same or similar elements as those described with respect to the above-described drawings are denoted by the same reference signs, and redundant description may be omitted. In addition, in the specification and the like, ordinal numbers are given for convenience in order to distinguish parts, members, and the like, and do not indicate priority or order.

In an embodiment of the present invention, in the case where a plurality of films is formed by processing a single film, the plurality of films may have different functions and roles. However, the plurality of films is derived from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, the plurality of films is defined as being present in the same layer. In addition, in the case where the plurality of films is formed by processing a certain film, in the present specification and the like, the films may be described separately using −1, −2, and the like.

In the specification and the like, expressions such as “above” and “below” represent a relative positional relationship between a structure of interest and another structure. In the present specification and the like, in a side view, a direction from a first substrate to a pixel electrode, which will be described later, is defined as “above”, and a reverse direction thereof is defined as “below”. In the specification and claims, the expression “above” in describing the manner of arranging another structure on a certain structure shall include both arranging another structure directly above a certain structure and arranging another structure over a certain structure via yet another structure, unless otherwise specified.

In the specification and the like, a bottom-gate drive is one in which on/off is controlled by a gate electrode arranged below a semiconductor layer. In addition, in the specification and the like, a top-gate drive is one in which on/off is controlled by a gate electrode arranged above the semiconductor layer. Further, in the present specification, a dual-gate drive is one in which on/off is controlled by inputting the same control signal to the gate electrode arranged above and below the semiconductor layer.

First Embodiment

A display device10according to an embodiment of the present invention will be described with reference toFIG.1toFIG.13.

[Outline of Display Device]

FIG.1shows a perspective view of the display device10according to an embodiment of the present invention. The display device10includes a display panel102including an array substrate150(also referred to as a first substrate), a counter substrate152(also referred to as a second substrate), a liquid crystal layer (not shown) between the array substrate150and the counter substrate152, a gate driving circuit28, and a source driving circuit38, a light source104, and a first transparent substrate151A and a second transparent substrate151B sandwiching the display panel102. In the following explanation referring toFIG.1, one direction on the plane of the display panel102is referred to as a direction D1, a direction orthogonal to the direction D1is referred to as a direction D2, and a direction orthogonal to a D1-D2plane is referred to as a direction D3.

The array substrate150and the counter substrate152have light transmittance. The array substrate150and the counter substrate152are preferably transparent to visible light. The counter substrate152is arranged in the direction D3so as to face the array substrate150. The array substrate150and the counter substrate152are bonded to each other with a seal member154while being arranged opposite to each other with a gap therebetween. A liquid crystal layer (not shown) is arranged in the gap between the array substrate150and the counter substrate152.

The display panel102has a display region12and a peripheral region14outside the display region12. A plurality of pixels PIX is arranged in a row direction and a column direction in the display region12. In this case, the row direction refers to a direction parallel to the direction D1, and the column direction refers to a direction parallel to the direction D2. The display region12includes m pixels arranged in the row direction and n pixels are arranged in the column direction. The values of m and n are appropriately set in accordance with a display resolution in the vertical direction and a display resolution in the horizontal direction. A gate wiring (also referred to as a scanning signal line) is arranged in the direction D1and a source wiring (also referred to as a data signal line) is arranged in the direction D2in the display region12.

The gate driving circuit28and the source driving circuit38are arranged in the peripheral region14of the array substrate150.FIG.1shows an embodiment in which the gate driving circuit28and the source driving circuit38are arranged in an integrated circuit (IC) and implemented in a COG (Chip on Glass) method in the array substrate150. The gate driving circuit28and the source driving circuit38are not limited to the illustrated embodiments, and may be implemented in a COF (Chip on Film) method or may be formed by a thin film transistor (TFT) of the array substrate150.

A gate wiring region32, a common wiring region22, and a source wiring region42are arranged in the peripheral region14. The gate wiring region32is a region where a pattern formed by a wiring connecting the gate driving circuit28and a gate wiring GL arranged in the display region12is arranged. The common wiring region22is a region where a pattern formed by a common wiring is arranged. The common wiring region22is used as a wiring for applying a common voltage to a common electrode218(seeFIG.7) arranged in the counter substrate152. The source wiring region42is a region where a pattern formed by a wiring connecting the source driving circuit38and a data signal line SL arranged in the display region12is arranged.

The light source104has a structure along the direction D1. For example, the light source104is configured by a light-emitting diode (LED) arranged along the direction D1. A detailed structure of the light source104is not limited and may include an optical member such as a reflector, a diffuser, a lens, and the like, in addition to a light-emitting diode arranged in the direction D1. The light source104and a light emission control circuit110for controlling the light source104may be arranged as a separate member independent of the display panel102. In addition, the light source104may be one in which light emission timing is controlled by the light emission control circuit110synchronized with the gate driving circuit28and the source driving circuit38. Similar to the light source104, the light emission control circuit110for controlling the light source104may be arranged as a separate member from the display panel102, may be mounted on the array substrate150as a separate component, or may be incorporated in the gate driving circuit28or the source driving circuit38.

The first transparent substrate151A and the second transparent substrate151B are arranged so as to sandwich the display region12and the peripheral region14. The first transparent substrate151A and the second transparent substrate151B have a function as a protective member of the display panel102. In addition, as described with respect toFIG.2, the first transparent substrate151A and the second transparent substrate151B function as a light guide plate for introducing light emitted from the light source104into the display panel102.

FIG.2shows a cross-sectional structure of the display device10corresponding to A1-A2shown inFIG.1. As shown inFIG.2, the first transparent substrate151A is arranged on the array substrate150side of the display panel102, and the second transparent substrate151B is arranged on the counter substrate152side. The first transparent substrate151A and the second transparent substrate151B may be a glass substrate or a plastic substrate. The first transparent substrate151A and the second transparent substrate151B preferably have refractive indices equivalent to those of the array substrate150and the counter substrate152. The array substrate150, the first transparent substrate151A, and the counter substrate152and the second transparent substrate151B are bonded to each other with a transparent adhesive (not shown).

The display panel102is arranged such that the array substrate150and the counter substrate152face each other, and a liquid crystal layer210is arranged therebetween. The array substrate150is larger than the counter substrate152and has a size such that part of the peripheral region14is exposed from the counter substrate152. A driving circuit (the source driving circuit38inFIG.2) is arranged in the array substrate150. In addition, a flexible printed circuit34is attached to the periphery of the array substrate150.

The light source104is arranged adjacent to one side of the first transparent substrate151A or the second transparent substrate151B.FIG.2shows a configuration in which the light source104is arranged along one side of the second transparent substrate151B. In addition, althoughFIG.2shows a configuration in which the light source104is attached to the array substrate150, the configuration is not limited to the configuration in which the light source104is arranged, and an attachment configuration is not limited as long as an attachment position can be fixed. For example, the light source104may be supported by a housing surrounding the display panel102.

As shown inFIG.2, the light source104is arranged along a first side15C of the second transparent substrate151B. As shown inFIG.2, the light source104irradiates the first side surface15C of the second transparent substrate151B with light L. The light source104may also be referred to as a side light source because it emits the light L toward the first side15C. The first side surface15C of the second transparent substrate151B facing the light source104serves as a light incident surface.

As schematically shown inFIG.2, the light L incident from the first side15C of the second transparent substrate151B propagates in a direction away from the first side15C (the direction D2) while being reflected by a second plane15B of the second transparent substrate151B and a first plane15A of the first transparent substrate151A. When the light L is directed to the outside from the first plane15A of the first transparent substrate151A and the second plane15B of the second transparent substrate151B, the light L proceeds from a medium having a large refractive index to a medium having a small refractive index. In this case, if an incident angle of the light L incident on the first plane15A and the second plane15B is larger than the critical angle, the light L is totally reflected, and is guided to the direction D2while being reflected by the first plane15A and the second plane15B.

The liquid crystal layer210is formed of a polymer-dispersed liquid crystal. In the liquid crystal layer210formed of the polymer-dispersed liquid crystal, a scattering state and a non-scattering state are controlled for each pixel PIX (seeFIG.1). As shown inFIG.2, at least part of the light L propagating while being reflected by the first plane15A and the second plane15B is scattered, when there is a pixel in which the liquid crystal layer210is in a scattered state, an incident angle of the scattered light becomes an angle smaller than the critical angle, scattered lights LA and LB are emitted to the outside from the first plane15A and the second plane15B, respectively, and the emitted scattered lights LA and LB are observed by an observer. In the display panel102, in a region except for the region where the scattered lights LA and LB are emitted, the array substrate150, the counter substrate152, the first transparent substrate151A, and the second transparent substrate151B have light transmittance (transparent to visible light) and are substantially transparent because the liquid crystal layer210is in a non-scattering state, thereby allowing the observer to view a backside through the display panel102.

FIG.3is a plan view illustrating a configuration of the array substrate150of the display device10according to an embodiment of the present invention. As shown inFIG.3, the array substrate150includes the display region12and the peripheral region14.

The display region12includes the plurality of pixels PIX arranged in a matrix. Each of the plurality of pixels PIX includes a plurality of transistors and liquid crystal elements.

The peripheral region14is arranged to surround the display region12. The peripheral region14refers to a region from the display region12to an edge of the array substrate150in the array substrate150. In other words, the peripheral region14shall refer to a region except for the region where the display region12is arranged on the array substrate150(that is, a region outside the display region12).

In addition to the gate driving circuit28and the source driving circuit38, the gate wiring region32, the source wiring region42, common wirings16and18, terminal portions26and36, flexible printed circuits24and34, and various inspection circuits are arranged in the peripheral region14. The terminal portions26and36are arranged along one side of the array substrate150.

The flexible printed circuit24is connected to the terminal portion26. The flexible printed circuit24outputs various signals to the gate driving circuit28, the common wirings16and18, an ESD protective circuit59, and a QD pad56. The gate driving circuit28is connected to a plurality of gate wirings GL, and each of the plurality of gate wirings GL is electrically connected to each of the plurality of pixels PIX in the display region12. InFIG.3, a region where the plurality of gate wirings GL is arranged is shown as the gate wiring region32, and a detailed arrangement of the plurality of gate wirings GL is omitted. The number of gate wirings GL connected to the two gate driving circuits28corresponds to the number of rows of pixels PIX in the display region12. InFIG.3, although a configuration in which the gate wiring region32is arranged apart from the display region12is shown, actually the gate wiring GL and the pixel PIX are electrically connected to each other.

The flexible printed circuit34is connected to the terminal portion36. The flexible printed circuit34outputs a video signal to the source driving circuit38. The source driving circuit38is connected to a plurality of source wirings SL, and each of the plurality of source wirings SL is electrically connected to each of the plurality of pixels PIX in the display region12. InFIG.3, a region where the plurality of source wirings SL is arranged is shown as the source wiring region42, and a detailed arrangement of the plurality of source wirings SL is omitted. The number of source wirings SL connected to the eight source driving circuits38corresponds to at least three times the number of columns of pixels PIX in the display region12. This embodiment will explain an example where the number of source wirings SL is four times the number of rows of pixels PIX arranged in the display region12. InFIG.3, although a configuration in which the source wiring region42is arranged apart from the display region12is shown, actually the source wiring SL and the pixel PIX are electrically connected to each other.

The common wiring18, an ESD protective circuit46, a gate inspection circuit48, and an inspection line54are arranged between the gate wiring region32and the display region12. The common wiring18, the ESD protective circuit46, a source inspection circuit52, and the inspection line54are arranged between the source wiring region42and the display region12. The inspection line54is connected to an ESD protective circuit58and the QD pad56. In addition, the common wiring18is connected to the ESD protective circuit59.

The common wiring16is arranged so as to surround the peripheral region14in the array substrate150, and a signal is supplied from the two flexible printed circuits24. In addition, the common wiring16is electrically connected to the mesh-shaped common wiring region22.

The display device10is not limited to a high-speed driving panel such as a transparent display shown inFIG.1andFIG.2. The display device10can be applied to a large panel used in a display device that is not the transparent display.

[Pixel Circuit]

FIG.4is a diagram illustrating a pixel circuit of the pixel PIX included in the display device10according to an embodiment of the present invention. In the present embodiment, the display device10in which an on-voltage is simultaneously supplied to four gate wirings GL and four pixels PIX arranged in the column direction can be simultaneously charged by four source wirings SL will be described. As a result, one horizontal period can be made longer than a horizontal period in line order. In other words, it is possible to reduce the time required for scanning all the pixel lines arranged in the display region12to ¼. Therefore, the charging period for the pixel PIX can be sufficiently secured in a high-speed driving panel such as the transparent display or a large-sized panel. Hereinafter, a configuration of the pixel PIX according to the present embodiment will be described in detail.

InFIG.4, four pixels PIX1to PIX4are arranged in the column direction (direction D2). Each of the four pixels PIX1to PIX4is electrically connected to each of the four gate wirings GL1to GL4. In addition, each of the four pixels PIX1to PIX4is electrically connected to each of four source wirings SL1to SL4. Each of the four pixels PIX1to PIX4is connected to a capacitance wiring CW. In the following explanation, in the case where the pixels PIX1to PIX4are not distinguished from each other, they are referred to as the pixel PIX. In the case where the gate wirings GL1to GL4and the source wirings SL1to SL4are not distinguished from each other, they are referred to as the gate wiring GL and the source wiring SL.

The pixel PIX includes a transistor Tr, a liquid crystal element LE, and a storage capacitor C. A gate of the transistor Tr is connected to the gate wiring GL, a source of the transistor Tr is connected to the source wiring SL, and a drain of the transistor Tr is connected to one electrode of the liquid crystal element LE and one electrode of the storage capacitor C. The other electrode of the liquid crystal element LE is connected to the common electrode218(FIG.7). The other electrode of the storage capacitor C is connected to the capacitance wiring CW.

The transistor Tr has a function of controlling the writing time of the video signal supplied from the source wiring SL to the pixel PIX by switching between the on-state and the off-state. When the transistor Tr is turned on, a potential corresponding to the video signal supplied from the source wiring SL can be written to the storage capacitor C electrically connected to the transistor Tr. In addition, when the transistor Tr is turned off, the potential held in the storage capacitor C can be held.

FIG.5is a timing chart of the display device10according to an embodiment of the present invention. Normally, the gate wiring GL sequentially charges the pixel columns arranged in the direction D2by using the same source wiring SL by supplying the on-voltage row by row. On the other hand, in the present embodiment, the on-voltage is simultaneously supplied to the four gate wirings GL, so that the transistor Tr of each of the four pixels PIX are simultaneously turned on. In this state, the video signal is simultaneously supplied to the different source wirings SL1to SL4. As a result, the four pixels arranged in the direction D2can be driven simultaneously.

[Planar Layout of Pixel]

A planar layout of pixels PIX in the display device10according to an embodiment of the present invention will be described with reference toFIG.6.FIG.6shows a configuration in which PIX-A1, PIX-A2, PIX-B1, and PIX-B2are in a plan view.

As shown inFIG.6, gate wirings GLn−1 to GLn+1 are arranged along the direction D1. In addition, the source wirings SL1to SL4are arranged along the direction D2. In this case, an opening region of the pixel PIX-B1is a region surrounded by the adjacent gate wiring GLn−1, a gate wiring GLn, the source wiring SL1, and the source wiring SL4.

As shown inFIG.6, the source wiring SL1and the source wiring SL3, and the source wiring SL2and the source wiring SL4are arranged so as to sandwich one column of the pixels PIX-B1and PIX-B2. In other words, the four source wirings SL1to SL4are arranged between one column of the pixels PIX-A1and PIX-A2and one column of the pixels PIX-B1and PIX-B2.

The transistor Tr is arranged in a region250where the gate wiring GL and the source wirings SL1to SL4intersect. In addition, the transistor Tr is connected to a pixel electrode. The pixel electrode is arranged in the opening region of the pixel PIX-B1. As shown inFIG.6, a plurality of spacers SP is arranged at intersections of the pixel PIX arranged in a matrix. Alternatively, the plurality of spacers SP is arranged so as to have regularity with respect to the intersections of the pixel PIX arranged in a matrix.

For example, the plurality of spacers may be arranged in every other row and column of the pixel PIX. In other words, the spacer SP may not be arranged at the intersection adjacent to the intersection where the spacer SP is arranged.

The source wiring SL2and the source wiring SL4are adjacent to the pixel PIX-A1and the pixel PIX-A2, and the source wiring SL1and the source wiring SL3are adjacent to the pixel PIX-B1and the pixel PIX-B2, in the region250shown inFIG.6where the gate wiring GL gate and the source wirings SL1to SL4intersect with each other. To describe the position where the spacer SP is arranged, a spacer SP overlaps the source wiring SL3adjacent to the pixel PIX-B1and the pixel PIX-B2, and the source wiring SL2adjacent to the pixel PIX-A1and the pixel PIX-A2. A spacer SP overlaps the source wiring SL4adjacent to a pixel PIX-B2and a pixel PIX-B3(not shown), and the source wiring SL3adjacent to a pixel PIX-C2and a pixel PIX-C3(not shown).

The spacer SP intersects the gate wiring GL and is arranged above two source wirings sandwiched between two source wirings adjacent to the pixel among the source wirings SL1to SL4arranged adjacent to each other.

FIG.7is a cross-sectional view in the display device10. InFIG.7, the stacking order of the layers when the display device10is viewed in a cross-section will be described.

As shown inFIG.7, a conductive layer202-1is arranged above the array substrate150. A gate insulating film203is arranged above the conductive layer202-1. An oxide semiconductor layer204-1is arranged above the gate insulating film203. The oxide semiconductor layer204-1is arranged to face the conductive layer202-1via the gate insulating film203. Conductive layers206-3and206-4are arranged above the oxide semiconductor layer204-1. An insulating film205is arranged above the conductive layers206-3and206-4. A conductive layer208-1is arranged above the insulating film205.

In the present embodiment, the conductive layer202-1functions as the gate wiring GL (gate electrode). The conductive layer206-3functions as a drain electrode, and the conductive layer206-4functions as the source wiring SL (source electrode). The conductive layer208-1functions as a back gate. The conductive layer202-1, the oxide semiconductor layer204-1, the insulating film205, and the conductive layers206-3and206-4function as the transistor Tr. In the present embodiment, although the transistor Tr is described as a bottom-gate-driven transistor, the present invention is not limited to this, and may be a top-gate-driven transistor or a dual-gate-driven transistor.

In the present embodiment, the gate insulating film203includes a stacked nitride insulating film203aand an oxide insulating film203b. The insulating film205includes a stacked oxide insulating film205aand a nitride insulating film205b. In addition, the oxide semiconductor layer204-1is sandwiched between the oxide insulating film203band the oxide insulating film205a. Oxygen is released from the oxide insulating film203band the oxide insulating film205awhile processing the oxide insulating film205aand the oxide insulating film203b. The released oxygen may be supplied to the oxide semiconductor layer204-1. This is preferable because oxygen defects in the oxide semiconductor layer204-1can be repaired.

A planarization film207is arranged above the conductive layer208-1and the insulating film205. The planarization film207is arranged to alleviate the unevenness of various wiring constituting the transistor Tr. In the case where the display device10is applied to the transparent display, the planarization film207is preferably removed in the opening region of the pixel PIX. As a result, it is possible to suppress the planarization film207from absorbing light in the opening region. Therefore, the planarization film207is arranged at a position overlapping the gate wirings GLn−1 to GLn+1 and the source wirings SL1to SL4inFIG.6. The planarization film207is arranged in a region overlapping the conductive layer206-4and the transistor Tr inFIG.7. In addition, since the planarization film207is removed in the opening region of the pixel PIX, the planarization film207is not arranged between the conductive layer206-3and a pixel electrode216-1.

A transparent conductive layer212is arranged above the planarization film207. A conductive layer214is arranged in contact with the transparent conductive layer212. The transparent conductive layer212and the conductive layer214function as the capacitance wiring CW. The transparent conductive layer212and the conductive layer214are arranged at positions overlapping the gate wirings GLn−1 to GLn+1 and the source wirings SL1to SL4shown inFIG.6. In addition, the conductive layer214also functions as a light-shielding layer. In the present embodiment, although a configuration in which the conductive layer214is arranged above the transparent conductive layer212is described, a configuration in which the transparent conductive layer212is arranged above the conductive layer214is also possible. An insulating film209is arranged above the conductive layer214. Since the planarization film207is removed in the opening region, the insulating film209is in contact with the insulating film205in the opening region. The pixel electrode216-1is arranged above the insulating film209. The pixel electrode216-1is connected to the conductive layer206-3via a contact hole arranged in the insulating films205and209. The pixel electrode216-1is arranged in the opening region of the pixel PIX. The pixel electrode216-1does not cover the source wiring SL and the transistor Tr, but covers part of the conductive layer206-3.

As shown inFIG.7, an end portion of the transparent conductive layer212is arranged between an end portion of the conductive layer214and the pixel electrode216-1above the planarization film207overlapping the transistor Tr. With this arrangement, the transistor Tr can be shielded from light and the transmittance of light in the opening region can be improved.

The counter substrate152is arranged to face the array substrate150. A light-shielding layer219, the common electrode218, and an insulating film221are arranged in the counter substrate152. The light-shielding layer219functions as a black matrix. In the structure shown inFIG.7, the light-shielding layer219is arranged in a region overlapping the conductive layer206-4inFIG.8. The light-shielding layer219is arranged in a grid pattern so as to cover the gate wirings GLn−1 to GLn+1 and the source wirings SL1to SL4. The common electrode218has a size that extends over the entire surface of the display region12. The light-shielding layer219may be formed of a metal film, and functions as an auxiliary electrode by being arranged in contact with the common electrode218formed of a transparent conductive film. The liquid crystal layer210is arranged between the array substrate150and the counter substrate152and is sealed with the seal member154(seeFIG.1). The liquid crystal element LE is configured by the pixel electrode216-1, the liquid crystal layer210, and the common electrode218.

As described above, unevenness may occur on the outermost surface of the array substrate150by stacking the conductive layers having various thicknesses on the array substrate150in the display device. Since the plurality of spacers arranged in the counter substrate152contacts the unevenness on the outermost surface of the array substrate150, variations in a cell gap occur. As a result, the display quality of the display device decreases.

In addition, the planarization film207is thickly formed in the display region in order to suppress parasitic capacitance from being formed by the gate wiring GL, the source wiring SL, and the conductive layer214. The planarization film207is arranged in a lattice pattern so as to cover the gate wiring GL and the source wiring SL. That is, the planarization film207is removed in the opening region of the pixel. If the thickness of the planarization film207is greater than 2 μm and when a resist is applied as a mask for processing the conductive film or the insulating film formed on the planarization film207, the applied resist may flow from above the planarization film207to the opening region. As a result, the thickness of the resist arranged on an upper portion of the planarization film207is reduced, thereby causing coating unevenness of the resist. When the conductive film or the insulating film is processed using such a resist mask, a process defect occurs in the conductive film or the insulating film.

In order to suppress the coating unevenness of the resist formed on the upper portion of the planarization film207, it is possible to suppress the flow of the resist from the upper portion of the planarization film207to the opening region by increasing the thickness of the resist. As a result, the upper portion of the planarization film207can be covered with the resist. However, it is difficult to remove the resist having a large thickness, and it is also difficult to miniaturize the pattern. Further, applying the thick resist changes the concentration of the solvent in the resist depending on the thickness direction. For example, the concentration of the solvent is low at a surface of the resist, and high at a bottom surface. Since the resist becomes harder when the concentration of the solvent is low, it is difficult to remove the resist, and the resist becomes softer when the concentration of the solvent is high, so that the resist is easily removed. Therefore, in the case where the concentration of the solvent changes according to the thickness direction of the resist, the shape of the mask is deteriorated by exposing and developing the resist. If the concentration of the solvent contained in the resist is decreased when the resist is applied thickly, unevenness in the concentration of the solvent in the thickness direction of the resist is suppressed. It is possible to improve the shape of the resist by reducing the concentration of the solvent contained in the resist and extending the vacuum drying time after applying the resist. However, since the processing tact of the photolithography process becomes long, it is not suitable for mass production.

As described above, it is difficult to accurately form the resist mask on the upper portion of the processed planarization film having a large thickness. In addition, a defective shape of the resist mask may cause defective processing of the conductive film and the insulating film, which may cause a defective display of the display device.

Furthermore, in the case where an oxide semiconductor layer is used as the transistor in the display device, the transistor performance deteriorates when moisture contained in the planarization film207enters the oxide semiconductor layer. Therefore, moisture contained in the planarization film needs to be removed.

In the display device10according to an embodiment of the present invention, the planarization film207reduces parasitic capacitance between the gate wiring and the source wiring and the conductive layer214and improves the transmittance of the opening region. In this case, a protrusion part protruding above the surface of the transparent conductive layer arranged on the planarization film is arranged in the planarization film207, and the protrusion part functions as a spacer. The protrusion part maintains the cell gap between the array substrate150and the counter substrate152.

As a result, the spacers formed on the array substrate150and having the reduced effects of the unevenness of the conductive layer having various thicknesses can be contacted with the counter substrate152. Therefore, it is possible to suppress the variations in the cell gap caused by the unevenness of the outermost surface of the array substrate150. As a result, it is possible to improve the display quality of the display device. Further, the spacer forming step in the counter substrate152can be omitted.

In addition, since the protrusion part is arranged in the planarization film207, even if the resist is applied, the resist is not applied to the upper portion of the protrusion part, and the resist is applied to regions other than the protrusion part. The upper portion of the protrusion part can be exposed from the conductive film or the insulating film by removing the conductive film or the insulating film on the upper portion of the protrusion part using such a resist mask. As a result, moisture contained in the planarization film207can be released from the upper portion of the exposed protrusion part during the heat treatment in the manufacturing process of the display device. As a result, it is possible to suppress moisture contained in the planarization film from entering the oxide semiconductor layer and to suppress deterioration of the characteristics of the transistor Tr.

In the following explanation, the region250where the gate wiring GL intersects the source wirings SL1to SL4will be described with reference toFIG.8toFIG.13. InFIG.8toFIG.13, the source wirings SL2and SL4are wirings of a column for driving the pixels PIX-A1and PIX-A2, and the source wirings SL1and SL3are wirings of a column for driving the pixels PIX-B1and PIX-B2.

FIG.8is a planar layout of the conductive layers202-1to202-9, the oxide semiconductor layers204-1to204-4, and conductive layers206-1to206-11in the region250. The conductive layers202-1to202-9are arranged above the array substrate150. The conductive layer202-1has a region that extends in the direction D1but branches in the direction D2. In addition, the conductive layers202-2to202-9extend in the direction D2. The oxide semiconductor layers204-1to204-4are arranged above the conductive layer202-1via the gate insulating film203(seeFIG.7). The oxide semiconductor layers204-1to204-4are arranged side by side in the direction D2. In the present embodiment, an example in which the five oxide semiconductor layers204-1to204-4are used to form the transistor Tr is shown. The oxide semiconductor layer may be separately arranged in the plurality of oxide semiconductor layers204-1to204-4to reduce the effect of heat generation. The number of oxide semiconductor layers is not particularly limited. In the oxide semiconductor layers204-1to204-4, light guided from the conductive layer202-1side to the glass substrate (the array substrate150) toward the oxide semiconductor layers204-1to204-4is reflected by the conductive layer202-1, and light leakage is less likely to occur in the oxide semiconductor layers204-1to204-4. The conductive layers206-1to206-11are arranged above the gate insulating film203and the oxide semiconductor layers204-1to204-4. The conductive layers206-1,206-2, and206-11extend in the direction D1and the conductive layers206-3to206-10extend in the direction D2.

The conductive layer202-1overlaps the conductive layers206-1,206-2, and206-11. The conductive layer202-1is connected to the conductive layer206-1via a contact hole213-1arranged in the gate insulating film203, and is connected to the conductive layer206-2via a contact hole213-2arranged in the gate insulating film203. A region of the conductive layer202-1extending in the direction D1functions as the gate wiring. In addition, a region of the conductive layer202-1extending in the direction D2functions as the gate electrode.

The conductive layers202-2and202-3overlap the conductive layer206-4. The conductive layer202-2is connected to the conductive layer206-4via a contact hole213-3arranged in the gate insulating film203. The conductive layer202-3is connected to the conductive layer206-4via a contact hole213-4arranged in the gate insulating film203. The conductive layer206-4intersects the conductive layer202-1. The conductive layer206-4functions as the first source wiring SL1. In addition, a region of the conductive layer206-4that does not overlap the conductive layers202-2and202-3functions as a source electrode of the transistor Tr. The conductive layer206-3functions as a drain electrode of the transistor Tr.

The conductive layer202-4overlaps the conductive layer206-5and is connected to the conductive layer206-5via a contact hole213-5arranged in the gate insulating film203. The conductive layer202-5overlaps the conductive layer206-6and is connected to the conductive layer206-6via a contact hole213-6arranged in the gate insulating film203. The conductive layer206-5is connected to the conductive layer206-6via the conductive layer208-2(seeFIG.9). As a result, the conductive layer206-5, the conductive layer206-6, and the conductive layer208-2function as the third source wiring SL3.

The conductive layer202-6overlaps the conductive layer206-7and is connected to the conductive layer206-7via a contact hole213-7arranged in the gate insulating film203. The conductive layer202-7overlaps the conductive layer206-8and is connected to the conductive layer206-8via a contact hole213-8arranged in the gate insulating film203. The conductive layer206-7is connected to the conductive layer206-8via the conductive layer208-3(seeFIG.9). The conductive layer206-7, the conductive layer206-8, and the conductive layer208-3function as the second source wiring SL2.

The conductive layer202-8overlaps the conductive layer206-9and is connected to the conductive layer206-9via a contact hole213-9arranged in the gate insulating film203. The conductive layer202-9overlaps the conductive layer206-9and the conductive layer206-10. The conductive layer202-9is connected to the conductive layer206-9via a contact hole213-10arranged in the gate insulating film203. The conductive layer202-9is connected to the conductive layer206-10via a contact hole213-11arranged in the gate insulating film203. The conductive layer206-9has a region that intersects the conductive layer202-1. The conductive layer206-9and the conductive layer206-10function as the fourth source wiring SL4.

In addition, the conductive layer202-1overlaps the conductive layer206-11and is connected to the conductive layer206-11via a contact hole213-12arranged in the gate insulating film203.

The conductive layer202-9and the conductive layer206-8have a bent region. The conductive layer202-9has a region that overlaps and intersects the conductive layer206-8. That is, the second source wiring SL2and the fourth source wiring SL4have a region intersecting each other.

Although not described in detail, as shown inFIG.6, the conductive layer202-2and the conductive layer206-5have a bent region. The conductive layer202-2has a region that overlaps and intersects the conductive layer206-5. That is, the first source wiring SL1has a region that intersects the third source wiring SL3.

As shown inFIG.8, the gate wiring GLn is formed by stacking the conductive layer202-1and the conductive layers206-1and206-2. The conductive layer202-1extends along the direction D1. The gate wiring GLn is only the conductive layer202-1in a region where the source wirings SL1to SL4intersect, and the conductive layer206-1and the conductive layer206-2are separated from each other. In addition, the source wiring SL1is formed by stacking the conductive layers202-2and202-3and the conductive layer206-4. In the source wiring SL1, in a region that intersects the gate wiring GLn, only the conductive layer206-4is arranged, and the conductive layer202-2and the conductive layer202-3are separated from each other. As a result, even if static electricity is generated in the manufacturing process of the display region12and the peripheral region14in the array substrate150, the static electricity can be released, and the generation of defects caused by the static electricity can be suppressed.

FIG.9is a planar layout of the conductive layers206-1through206-11and the conductive layers208-1to208-3in the region250. The conductive layers206-1to206-11are as described inFIG.8. The conductive layers208-1to208-3are arranged above the insulating film205(seeFIG.7). The conductive layer208-1has a region extending in the direction D2and a region extending in the direction D1. The region extending in the direction D2overlaps the oxide semiconductor layers204-1to204-4. In addition, the region extending in the direction D1overlaps the conductive layer206-11and is connected to the conductive layer206-11via a contact hole215-7arranged in the insulating film205. The conductive layer208-2extends in the direction D2. The conductive layer208-2overlaps the conductive layer206-5and the conductive layer206-6, and is connected to the conductive layer206-5and the conductive layer206-6via contact holes215-3and215-4arranged in the insulating film205. The conductive layer208-3extends in the direction D2. The conductive layer208-3overlaps the conductive layer206-7and the conductive layer206-8, and is connected to the conductive layer206-7and the conductive layer206-8via contact holes215-5and215-6arranged in the insulating film205.

FIG.10is a planar layout of the planarization film207, the transparent conductive layer212, and the conductive layer214in the region250. The planarization film207has been removed in the opening regions of the pixels PIX1to PIX4as shown inFIG.7. That is, the planarization film207is arranged above the wiring region. The transparent conductive layer212is arranged above the planarization film207. In addition, the conductive layer214is arranged above the transparent conductive layer212. The transparent conductive layer212and the conductive layer214function as the capacitance wiring CW. The transparent conductive layer212is arranged above the conductive layers206-1to206-11via the planarization film207. Therefore, since the source wirings SL1to SL4and the capacitance wiring CW are arranged so as to be separated from each other, it is less likely to be affected by the potential from the capacitance wiring CW. In addition, the electrical resistance of the conductive layer214is smaller than the electrical resistance of the transparent conductive layer212. Therefore, variation in the potential of the capacitance wiring CW due to the position where the pixel PIX is located in the display region12is suppressed. In addition, the transparent conductive layer212has an opening223and the conductive layer214has an opening225. The opening223and the opening225are arranged so as to overlap each other. The planarization film207is exposed and the spacer SP is arranged inside the opening223.

The transparent conductive layer212and the conductive layer214are arranged in a grid pattern so as to cover the gate wiring GLn and the source wirings SL1to SL4. This reduces the storage capacitance C between the region without the transparent conductive layer212and the pixel electrode216. The storage capacitor C is adjusted by the size of the region without the transparent conductive layer212. In addition, the transparent conductive layer212may not be in the grid pattern, but may be arranged on the entire surface. In addition, the conductive layer214is arranged so as to cover the transistor Tr. As a result, optical leakage of the transistor Tr can be suppressed.

Although an example in which the conductive layer214is arranged above the transparent conductive layer212is shown, it may be arranged below the transparent conductive layer212. The conductive layer214may be stacked with the transparent conductive layer212. The conductive layer214has a light-shielding effect. Therefore, the wiring region can be shielded from light. A width of the conductive layer214is arranged so as to be larger than a combined width of the source wirings SL1to SL4in a plan view. In addition, the width of the conductive layer214is arranged so as to be larger than a width of the gate wiring GL in a plan view. As a result, it is possible to suppress a display panel11from emitting the reflected light reflected by the edges of the source wirings SL1to SL4. In addition, the width of the conductive layer214or the combined width of the source wirings SL1to SL4refer to lengths in the direction (direction D1) intersecting the direction in which the source wirings SL1to SL4extend. Further, the width of the gate wiring GL refers to a length in the direction (direction D2) intersecting the direction in which the gate wiring GL extends.

FIG.11is a planar layout of the conductive layers206-1to206-11and the pixel electrodes216-1to216-4in the region250. The conductive layers206-1to206-11are as described inFIG.8. The pixel electrodes216-1to216-4are arranged above the insulating film209. The pixel electrodes216-1to216-4are arranged in the opening region of the pixel PIX. The pixel electrode216-1is connected to the conductive layer206-3via contact holes217-1and217-2arranged in the insulating film209and contact holes215-1and215-2(seeFIG.9) arranged in the insulating film205. In addition, the insulating film209has a contact hole217-3. The contact hole217-3is arranged so as to overlap the opening223and the opening225(seeFIG.10). The openings223,225, and217-3on the planarization film207allow moisture contained in the planarization film207to be released from the exposed planarization film207.

The conductive layer202and the conductive layer206are arranged so as to be stacked on each other as the gate wirings GL1to GL4and the source wirings SL1to SL4in the display region12. Since the source wirings SL1to SL4are arranged so that the conductive layer202and the conductive layer206are stacked and extended, resistance of the source wirings SL1to SL4can be made uniform and wiring capacitance can be made uniform. In addition, the source wiring SL1and the source wiring SL3can be arranged to intersect each other, and the source wiring SL2and the source wiring SL4can be arranged to intersect each other.

FIG.12is a diagram in which the conductive layer202, the conductive layer206, the conductive layer208, the conductive layer214, and the spacer SP in the region250overlap.FIG.13is a cross-sectional view at a line B1-B2shown inFIG.12in the display region.FIG.14shows a cross-sectional view at the C1-C2line shown inFIG.12in the display region. At the intersection of the gate wiring GLn and the source wiring SL where the spacer SP is placed, the gate wiring GLn is composed of the conductive layer202-1with a thick film thickness, while the source wiring SL is composed of the conductive layers208-2and208-3with a thin film thickness compared to the conductive layer202and conductive layer206, without providing a conductive layer with a thick film thickness. The source wiring SL is composed of conductive layers208-2and208-3, which are thinner than the conductive layers202and206. This allows the gate wiring GL and the source wiring SL to cross each other without the thick conductive layers crossing each other.

As shown inFIG.13andFIG.14, the spacer SP is arranged in the region where the conductive layer202-1intersects the conductive layers208-2and208-3. The spacer SP is part of the planarization film207and is arranged so that part of the planarization film207protrudes upward from the surface of the transparent conductive layer212. The opening223is arranged to surround the spacer SP in the transparent conductive layer212. The opening225is arranged to surround the spacer SP in the conductive layer214. In this case, an end portion of the opening225is located outside of an end portion of the opening223. The opening217-3is arranged to surround the spacer SP in the insulating film209. The insulating film209is in contact with a side surface of the spacer SP. In this case, an area of the opening217-3is smaller than an area of the openings223and225. In the planarization film207, a thickness from a surface of the nitride insulating film205bto the upper surface of the protrusion part is defined as a thickness T1. In addition, a thickness from the surface of the nitride insulating film205bto the transparent conductive layer212is defined as a thickness T2. The thickness T1is about 3 μm, and the thickness T2is about 2 μm.

The spacer SP is arranged to be in contact with a surface of the counter substrate152. The spacer SP may be in contact with the counter substrate152via a conductive film or an insulating film. The light-shielding layer219is arranged in the counter substrate152. The common electrode218is arranged in contact with the light-shielding layer219. In addition, the insulating film221is arranged in contact with the common electrode218. The opening232is arranged in the insulating film221. The opening232is arranged in the insulating film221, and the common electrode218is in contact with the spacer SP inside the opening232, so that the adhesion between the spacer SP and the common electrode218can be improved. In addition, an area of the opening232may be larger than the area of the opening217-3.

As shown inFIG.8andFIG.12, the source wiring SL3has a region where the conductive layer202-4overlaps the conductive layer206-5and a region where the conductive layer202-5overlaps the conductive layer206-6. The conductive layer206-5is connected to the conductive layer202-4via the contact hole213-5arranged in the gate insulating film203. The conductive layer206-6is connected to the conductive layer202-5via the contact hole213-6arranged in the gate insulating film203. In this case, the spacer SP is preferably arranged in a region that does not overlap the conductive layers206-5,206-6,206-7, and206-8.

Further, the spacer SP does not overlap the transistor Tr of the pixel PIX-B1adjacent to the region where the conductive layer202-1intersects the conductive layers208-2and208-3. The transistor Tr is composed of the gate wiring GLn, the source wiring SL1, the conductive layer206-3(drain electrode), and the oxide semiconductor layer204. Therefore, when the gate wiring GLn, the source wiring SL1, and the oxide semiconductor layer204overlap each other, unevenness occurs on the surface of the planarization film207arranged on the transistor Tr. Since the spacer SP is not arranged on the transistor Tr, variations in the cell gap can be reduced.

Although the example in which the plurality of spacers SP is arranged for all intersections of the pixels arranged in a matrix has been described in the present embodiment, an embodiment of the present invention is not limited to this. The plurality of spacers SP may be arranged so as to have regularity with respect to the intersections of the pixels arranged in a matrix. For example, the spacer SP may be regularly arranged so as to be arranged at one of the plurality of intersections. In addition, the spacer SP may be arranged in the region other than the intersection of the pixels. A height of the plurality of spacers SP may be the same height, or a spacer SP having a different height among the plurality of spacers SP may be arranged. For example, the main spacer SP contacting the counter substrate152side and a sub-spacer SP having a height smaller than the cell gap may be arranged.

[Peripheral Region]

Next, a spacer arranged in the peripheral region14of the display device10will be described with reference toFIG.15andFIG.16.

FIG.15is a cross-sectional view of the display device10when the seal material154arranged in the vicinity of the common wiring area22is cut in the direction D1in the peripheral region14.

InFIG.15, conductive layers202-21,202-22, and202-23are arranged on the array substrate150. The nitride insulating film203a, the oxide insulating film203b, the oxide insulating film205a, and the nitride insulating film205bare arranged on the conductive layers202-21,202-22, and202-23. The planarization film207is arranged in a region overlapping the conductive layers202-21,202-22, and202-23, and protrusion parts functioning as spacers SP-1, SP-2, and SP-3are arranged in the planarization film207. Each of the spacers SP-1to SP-3protrudes beyond the surface of the transparent conductive layer212. An opening of the transparent conductive layer212is arranged so as to surround the spacer SP-1of the planarization film207, and an opening of the conductive layer214is arranged. In addition, an opening is arranged in the transparent conductive layer212so as to surround the spacer SP-2, and an opening is arranged in the transparent conductive layer212so as to surround the spacer SP-3. The spacers SP-1, SP-2, and SP-3are in contact with the common electrode218. The spacer SP-1is arranged at a position where the seal material154is arranged.

FIG.16is a cross-sectional view of the display device10when the seal material154arranged in the vicinity of the terminal portion36is cut in the direction D2in the peripheral region14.

InFIG.16, conductive layers202-24,202-25,202-26, and202-27are arranged on the array substrate150. The nitride insulating film203a, the oxide insulating film203b, the oxide insulating film205a, and the nitride insulating film205bare arranged on the conductive layers202-24,202-25,202-26, and202-27. A difference from the planarization film207shown inFIG.15is that the planarization film207is arranged so as to overlap the plurality of conductive layers202-24,202-25, and202-26. In addition, protrusion parts functioning as a spacer SP-4and a spacer SP-5are arranged in the planarization film207overlapping the conductive layers202-24to202-26. Each of the spacer SP-4and the spacer SP-5protrudes upward from the surface of the transparent conductive layer212. Two openings are arranged in the transparent conductive layer212so as to surround the spacers SP-4and SP-5of the planarization film207, and two openings are arranged in the conductive layer214. A protrusion part functioning as the spacer SP-5is arranged in the planarization film207overlapping the conductive layer202-27. An opening is arranged in the transparent conductive layer212so as to surround the spacer SP-5.

InFIG.15andFIG.16, the planarization film207, the transparent conductive layer212, and the conductive layer214are arranged in a lattice pattern on various wirings. The planarization film207may be formed in one layer or may be divided into a plurality of layers on the array substrate150. Similarly, each of the transparent conductive layer212and the conductive layer214may be formed in one layer or may be divided into a plurality of layers.

Although the case where the spacers SP arranged in the peripheral region are formed to substantially the same height has been described in the present embodiment, the present embodiment is not limited to this. The spacer SP having a different height among the plurality of spacers SP may be arranged in the peripheral region. For example, the main spacer SP contacting the counter substrate152side and a sub-spacer SP having a height smaller than the cell gap may be arranged.

Usually, a display device is manufactured using a large mother substrate. In this case, a plurality of display regions are formed on the mother substrate, and then a seal material is applied and bonded to a counter substrate. After that, the individual display panels are cut out by cutting the mother substrate and the counter substrate between the adjacent display regions. In this case, a planarization film and a protrusion part are formed by using an organic resin along a cut line for cutting the mother substrate and the counter substrate. Both the planarization film and the protrusion part arranged along the cut line are, for example, line-shaped. Alternatively, the planarization film may be line-shaped, and the protrusion part may be dot-shaped. Arranging the planarization film and the protrusion part along the cut line serves as a liquid crystal contamination barrier wall.

[Method for Forming Planarization Film and Spacer]

Next, a method for manufacturing a display device according to an embodiment of the present invention will be described with reference toFIG.17AtoFIG.20B. Specifically, a method for forming the planarization film207and the spacer SP to form the transparent conductive layer212, the conductive layer214, the insulating film209, and the pixel electrode216will be described. First, a method for forming the planarization film207and the spacer SP using an organic resin will be described with reference toFIG.17AandFIG.18A.

FIG.17AtoFIG.18Aare diagrams describing a process of performing multi-gradation exposure by applying an organic resin242that becomes the planarization film207on the array substrate150. A conductive layer, an insulating film, and an oxide semiconductor layer arranged below the organic resin242are omitted from the drawings. As shown inFIG.17A, the organic resin242is applied on the array substrate150. A positive organic resin is used as the organic resin242functioning as the planarization film207. The positive organic resin softens by irradiation with light (mainly ultraviolet rays). In this case, a thickness of the organic resin242is about 3.0 μm.

As shown inFIG.17B, a multi-gradation mask240is used to expose the organic resin242. A gray tone mask or a halftone mask may be used as the multi-gradation mask240. The gray tone mask includes a light-shielding portion, a transmission portion, and a gray tone portion. The gray tone portion has a function of adjusting the amount of light transmission by arranging a slit having a resolution equal to or less than the resolution of the exposure apparatus. The halftone mask has a function of adjusting the amount of light transmission by a semi-transparent film. An unexposed region244, a middle-exposed region246, and an exposed region248can be formed on the organic resin242by performing exposure using the multi-gradation mask240. In this case, the unexposed region244corresponds to the region where the spacer SP is formed, and the middle-exposed region246corresponds to the region where the planarization film207is formed. A thickness of 25% or more and 30% or less is exposed from the surface of the organic resin242in the middle-exposed region246.

Next, by developing the exposed organic resin242, the organic resin in the middle-exposed region246and the organic resin of the exposed region248can be removed. As a result, as shown inFIG.18A, the spacer SP having a part protruding from the planarization film207can be formed. In this case, in the planarization film207, the thickness T1is about 3 μm, the thickness T2of the region covering the gate wiring GL and the source wiring SL is about 2 μm, and a thickness T3of the protrusion part functioning as the spacer SP is about 1 μm.

In an embodiment of the present invention, the method for forming the planarization film207and the spacer SP is not limited to the method using the multi-gradation masking240. For example, exposure may be performed twice such that the organic resin242may be exposed by a mask having an opening corresponding to the shape of the spacer, and then exposed by the mask having an opening corresponding to the shape of the planarization film. Alternatively, after the planarization film207is formed using the first layer of organic resin, two photolithography steps such that a second layer of organic resin is further coated on the planarization film207and a spacer is formed on the planarization film207using the second layer of organic resin may be performed.

Next, a method for forming the transparent conductive layers212to the pixel electrode216will be described with reference toFIG.18BandFIG.20B.

FIG.18Bis a diagram illustrating a process of forming the transparent conductive layer212and the conductive layer214. First, the transparent conductive layer212is formed on the insulating film205and the planarization film207. An opening is formed in the transparent conductive layer212so as to surround the spacer SP. The conductive layer214is formed on the transparent conductive layer212. An opening is formed in the conductive layer214so as to surround the spacer SP. In addition, after the transparent conductive layer212is formed, a heat treatment may be performed in a state where a conductive film is formed, or a heat treatment may be performed after the conductive layer214is formed by etching the conductive film. Moisture can be released from the region where the planarization film207is exposed.

FIG.19Ais a diagram illustrating a process of forming the insulating film209so as to cover the transparent conductive layer212, the conductive layer214, and the spacer SP. The insulating film209is formed so as to cover the side surface and the upper portion of the spacer SP. Although not shown, the insulating film209has a region in contact with the insulating film205. In other words, the insulating film209is in contact with the insulating film205in the opening region of the pixel.

FIG.19Bis a diagram illustrating a process of forming a resist mask252on the insulating film209. As described above, depending on the thickness of the resist mask252, there may be a region where the upper portion of the insulating film209is not formed and a region where it is formed. In the present embodiment, the resist mask252formed on the spacer SP is removed to expose the insulating film209on the spacer SP.

FIG.20Ais a diagram illustrating a process of performing an etching process using the resist mask252. The exposed insulating film209on the spacer SP can be removed by performing an etching process. As a result, the upper portion of the spacer SP can be exposed. Thereafter, the resist mask252is removed. The opening of the transparent conductive layer212, the opening of the conductive layer214, and an opening of the insulating film209are arranged so as to surround the spacer SP. Performing the heat treatment in this condition makes it possible to release moisture contained in the planarization film207from the exposed region of the spacer SP.

FIG.20Bis a diagram illustrating a process of forming the pixel electrode216on the insulating film209. The pixel electrode216is arranged in the opening region of the pixel. In other words, the pixel electrode216is arranged in the region where the planarization film207has been removed. After the pixel electrode216is formed, a heat treatment may be performed to release moisture contained in the planarization film207from the exposed region of the spacer SP. Finally, a post-bake may be performed.

As described above, a protrusion part functioning as the spacer SP can be formed in the planarization film207. The transparent conductive layer212, the conductive layer214, and the insulating film209formed on the planarization film207block moisture contained in the planarization film207. Therefore, exposing the upper portion of the spacer SP makes it possible to release moisture contained in the planarization film207by repeated heat treatment. As a result, it is possible to suppress moisture from entering the oxide semiconductor layer formed below the planarization film207. Therefore, deterioration of the characteristics of the transistor can be suppressed.

[Materials of Each Member of Display Device10]

A rigid substrate having light transmittance and no flexibility such as a glass substrate, a quartz substrate, and a sapphire substrate can be used the array substrate150and the counter substrate152. On the other hand, in the case where the array substrate150and the counter substrate152need to have flexibility, a flexible substrate containing a resin and having flexibility such as a polyimide substrate, an acryl substrate, a siloxane substrate, or a fluororesin substrate can be used as the array substrate150and the counter substrate152. In order to improve the heat resistance of the array substrate150and the counter substrate152, impurities may be introduced into the resin. In addition, in the case where the display device10is applied to a transparent display or a large display, a glass substrate is preferably used as the array substrate150and the counter substrate152. Further, the first transparent substrate151A and the second transparent substrate151B are arranged to protect the array substrate150and the counter substrate152. For this reason, for example, it is preferable to use a glass substrate, a plastic substrate, or the like having light transmittance.

A single layer or a stacked structure of silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum nitride (AlNx), aluminum nitride oxide (AlNxOy), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), and aluminum oxynitride (AlOxNy) is used as the gate insulting film203, the insulating film205, and the insulating film209. In the present embodiment, the gate insulating film203is configured by a stacked structure of the nitride insulating film203aand the oxide insulating film203b. In addition, the insulating film205is configured by the oxide insulating film205aand the nitride insulating film205b. Silicon nitride is used as the nitride insulating films203aand205band the insulating film209. For example, the silicon nitride film is formed by a sputtering method. In addition, silicon oxide is used as the insulating films203band205a.

SiOxNyand AlOxNyare a silicon compound and aluminum compound containing a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiNxOyand AlNxOyare a silicon compound and aluminum compound containing a smaller proportion of oxygen than nitrogen (x>y).

An organic insulating material such as a polyimide resin, an acryl resin, an epoxy resin, a silicone resin, a fluororesin, or a siloxane resin can be used as the planarization film207.

Common metal materials can be used as the conductive layers202,206, and208and the conductive layer214. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and an alloy or compound thereof are used as these members. The above-described material may be used in a single layer or in a stacked layer as the above members.

An oxide semiconductor having semiconductor characteristics can be used as the oxide semiconductor layers204. The oxide semiconductor layer204has light transmittance. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer204. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used as the oxide semiconductor layer204. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 may be used. However, the oxide semiconductor layer204used in the present embodiment is not limited to the above-described compositions, and an oxide semiconductor having compositions other than those described above can also be used.

A mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used as the transparent conductive layer212, the pixel electrode216, and the common electrode218. A material other than the above may be used as the transparent conductive layer. The light-shielding layer219used for a black matrix BM may be formed of a black resin or metal material. The black matrix BM is formed in contact with the common electrode218(seeFIG.8). While the common electrode218is formed of a transparent conductive film, and the black matrix BM is formed of a metal material, it is possible to provide a function as an auxiliary electrode for reducing resistance dissipation. The black matrix BM may be formed of a single layer or a stacked layer of chrome, molybdenum, titanium, or the like having relatively low reflectance with respect to aluminum.

In the case where the display device10is applied to a transparent display, a polymer-dispersed liquid crystal is preferably used as the liquid crystal layer210. The polymer-dispersed liquid crystal includes bulk and fine particles. The orientation of the fine particles changes in the bulk depending on the potential difference between the pixel electrode216and the common electrode218. The degree of at least one of light transmission and distribution is controlled for each pixel PIX by individually controlling the potential of the pixel electrode216for each pixel PIX. The degree of scatter of the liquid crystal layer (fine particles) is controlled depending on the voltage of the pixel electrode216and the voltage of the common electrode218. For example, a polymer-dispersed liquid crystal in which the degree of scattering increases as the voltage between each pixel PIX and the common electrode218increases, or a polymer-dispersed liquid crystal in which the degree of scattering increases as the voltage between each pixel electrode216and the common electrode218decreases may be used as the liquid crystal layer.

The ordinary refractive indices of the bulk and the fine particles are equal to each other in the liquid crystal layer210. In the case where no voltage is applied between the pixel electrode216and the common electrode218, the refractive index difference between the bulk and the fine particles is zero in all directions. The liquid crystal layer210is in the non-scattering state, in which the light emitted from the light source is not scattered. The light emitted from the light source propagates away from a light source3(light-emitting unit) while being reflected on the first main surface of the first the array substrate150and the first main surface of the counter substrate152. In the case where the liquid crystal layer210is in the non-scattering state, in which the light L emitted from a light source is not scattered, the background of the counter substrate152can be visually recognized from the array substrate150and the background of the array substrate150can be visually recognized from the counter substrate152.

Between the energized pixel electrode216and the common electrode218, the optical axis of the fine particles will be tilted by the electric field generated between the pixel electrode216and the common electrode218. Since the optical axis of the bulk does not change depending on the electric field, the orientations of the optical axis of the bulk and the optical axis of the fine particles are different from each other. The light emitted from the light source is scattered in the pixel PIX having the pixel electrode216to which the voltage is applied. Light in which part of the light emitted from the light source and scattered as described above is emitted to the outside from the first main surface of the array substrate150or the first main surface of the counter substrate152is observed by the observer.

The background of the first main surface of the counter substrate152is visually recognized from the first main surface of the array substrate150, and the background of the first main surface of the array substrate150is visually recognized from the first main surface of the counter substrate152, in the pixel PIX having the pixel electrode216with no voltage applied. Then, in the display device10of the present embodiment, when a video signal is input, a voltage is applied to the pixel electrode216of the pixel PIX on which an image is displayed, and an image based on the video signal is visually recognized together with the background. In this way, when the polymer-dispersed liquid crystal is in the scattering state, an image is displayed in the display region.

While preferred embodiments have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the spirit of the present invention. Appropriate changes that have been made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention.