Patent ID: 12245417

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a semiconductor-element-including memory device (hereinafter called a dynamic flash memory) according to embodiments of the present invention will be described with reference to the drawings.

First Embodiment

The structure and operation mechanisms of a dynamic flash memory cell according to a first embodiment of the present invention will be described with reference toFIG.1toFIGS.5BA to5BC. The structure of the dynamic flash memory cell will be described with reference toFIG.1. An effect attained in a case where the gate capacitance of a first gate conductor layer5aconnected to a plate line PL is made larger than the gate capacitance of a second gate conductor layer5bto which a word line WL is connected will be described with reference toFIGS.2A to2C. A mechanism of a data write operation will be described with reference toFIGS.3AA to3ACandFIG.3B, a mechanism of a data erase operation will be described with reference toFIG.4AtoFIG.4G, and a mechanism of a data read operation will be described with reference toFIGS.5AA to5ACandFIGS.5BA to5BC.

FIG.1illustrates the structure of the dynamic flash memory cell according to the first embodiment of the present invention. On the top and the bottom of a silicon semiconductor column2(the silicon semiconductor column is hereinafter referred to as “Si column”) (which is an example of “semiconductor body” in the claims) of the P or i (intrinsic) conductivity type formed on a substrate, N+layers3aand3b(which are examples of “first impurity layer” and “second impurity layer” in the claims), one of which functions as the source and the other functions as the drain, are formed respectively. The part of the Si column2between the N+layers3aand3bthat function as the source and the drain functions as a channel region7(which is an example of “channel semiconductor layer” in the claims). Around the channel region7, a first gate insulator layer4a(which is an example of “first gate insulator layer” in the claims) and a second gate insulator layer4b(which is an example of “second gate insulator layer” in the claims) are formed. The first gate insulator layer4aand the second gate insulator layer4bare in contact with or in close vicinity to the N+layers3aand3bthat function as the source and the drain respectively. Around the first gate insulator layer4aand the second gate insulator layer4b, the first gate conductor layer5a(which is an example of “first gate conductor layer” in the claims) and the second gate conductor layer5b(which is an example of “second gate conductor layer” in the claims) are formed respectively. The first gate conductor layer5aand the second gate conductor layer5bare isolated from each other by an insulating layer6(which is also referred to as “first insulating layer”). The channel region7between the N+layers3aand3bis constituted by a first channel Si layer7asurrounded by the first gate insulator layer4aand a second channel Si layer7bsurrounded by the second gate insulator layer4b. Accordingly, the N+layers3aand3bthat function as the source and the drain, the channel region7, the first gate insulator layer4a, the second gate insulator layer4b, the first gate conductor layer5a, and the second gate conductor layer5bconstitute a dynamic flash memory cell10. The N+layer3athat functions as the source is connected to a source line SL (which is an example of “source line” in the claims), the N+layer3bthat functions as the drain is connected to a bit line BL (which is an example of “bit line” in the claims), the first gate conductor layer5ais connected to the plate line PL (which is an example of “plate line” in the claims), and the second gate conductor layer5bis connected to the word line WL (which is an example of “word line” in the claims). As illustrated inFIG.1, the word line WL, the plate line PL, and the source line SL are disposed in parallel, and the bit line BL is disposed in a direction perpendicular to the word line WL, the plate line PL, and the source line SL. Desirably, the dynamic flash memory cell has a structure in which the gate capacitance of the first gate conductor layer5aconnected to the plate line PL is larger than the gate capacitance of the second gate conductor layer5bconnected to the word line WL.

InFIG.1, to make the gate capacitance of the first gate conductor layer5aconnected to the plate line PL larger than the gate capacitance of the second gate conductor layer5bto which the word line WL is connected, the gate length (the length of the gate in the central-axis direction of the Si semiconductor column2) of the first gate conductor layer5ais made longer than the gate length of the second gate conductor layer5b. Alternatively, instead of making the gate length of the first gate conductor layer5alonger than the gate length of the second gate conductor layer5b, the thicknesses of the respective gate insulator layers may be made different such that the thickness of the gate insulating film of the first gate insulator layer4ais thinner than the thickness of the gate insulating film of the second gate insulator layer4b. Alternatively, the dielectric constants of the materials of the respective gate insulator layers may be made different such that the dielectric constant of the gate insulating film of the first gate insulator layer4ais higher than the dielectric constant of the gate insulating film of the second gate insulator layer4b. The gate capacitance of the first gate conductor layer5aconnected to the plate line PL may be made larger than the gate capacitance of the second gate conductor layer5bto which the word line WL is connected, by a combination of any of the lengths of the gate conductor layers5aand5band the thicknesses and dielectric constants of the gate insulator layers4aand4b.

FIGS.2A to2Care diagrams for explaining an effect attained in a case where the gate capacitance of the first gate conductor layer5aconnected to the plate line PL is made larger than the gate capacitance of the second gate conductor layer5bto which the word line WL is connected.

FIG.2Ais a simplified structural diagram of the dynamic flash memory cell according to the first embodiment of the present invention and illustrates only main parts. To the dynamic flash memory cell, the bit line BL, the word line WL, the plate line PL, and the source line SL are connected, and the potential state of the channel region7is determined by the voltage states of the lines.

FIG.2Bis a diagram for explaining the capacitance relationships of the respective lines. The capacitance CFBof the channel region7is equal to the sum of the capacitance CWLbetween the gate conductor layer5bto which the word line WL is connected and the channel region7, the capacitance CPLbetween the gate conductor layer5ato which the plate line PL is connected and the channel region7, the junction capacitance CSLof the PN junction between the source N+layer3ato which the source line SL is connected and the channel region7, and the junction capacitance CBLof the PN junction between the drain N+layer3bto which the bit line BL is connected and the channel region7, and is expressed as follows.
CFB=CWL+CPL+CBL+CSL(1)
Therefore, the coupling ratio βWLbetween the word line WL and the channel region7, the coupling ratio BPL between the plate line PL and the channel region7, the coupling ratio βBLbetween the bit line BL and the channel region7, and the coupling ratio βSLbetween the source line SL and the channel region7are expressed as follows.

βWL=CWL/(CWL+CPL+CBL+CSL)(2)βPL=CPL/(CWL+CPL+CBL+CSL)(3)βBL=CBL/(CWL+CPL+CBL+CSL)(4)βSL=CSL/(CWL+CPL+CBL+CSL)(5)
Here, CPL>CWLholds, and therefore, this results in BPL>βWL.

FIG.2Cis a diagram for explaining a change in the voltage VFBof the channel region7when the voltage VWLof the word line WL rises at the time of a read operation or a write operation and subsequently drops. Here, the potential difference ΔVFBwhen the voltage VFBof the channel region7transitions from a low-voltage state VFBLto a high-voltage state VFBHin response to the voltage VWLof the word line WL rising from 0 V to a high-voltage state VWLHis expressed as follows.

Δ⁢VFB=VFBH-VFBL=βWL×VWLH(6)
The coupling ratio βWLbetween the word line WL and the channel region7is small and the coupling ratio βPLbetween the plate line PL and the channel region7is large, and therefore, ΔVFBis small, and the voltage VFBof the channel region7negligibly changes even when the voltage VWLof the word line WL changes at the time of a read operation or a write operation.

FIGS.3AA to3ACandFIG.3Billustrate a page write operation (which is an example of “page write operation” in the claims) of the dynamic flash memory cell according to the first embodiment of the present invention.FIG.3AAillustrates a mechanism of the write operation, andFIG.3ABillustrates operation waveforms of the bit line BL, the source line SL, the plate line PL, the word line WL, and the channel region7that functions as a floating body FB. At time T0, the dynamic flash memory cell is in a “0” erase state, and the voltage of the channel region7is equal to VFB“0”. Vss is applied to the bit line BL, the source line SL, and the word line WL, and VPLLis applied to the plate line PL. Here, for example, Vss is equal to 0 V and VPLLis equal to 2 V. Subsequently, from time T1to time T2, when the bit line BL rises from Vss to VBLH, in a case where, for example, Vss is equal to 0 V, the voltage of the channel region7becomes equal to VFB“0”+βBL×VBLHdue to capacitive coupling between the bit line BL and the channel region7.

The description of the write operation of the dynamic flash memory cell will be continued with reference toFIGS.3AA and3AB. From time T3to time T4, the word line WL rises from Vss to VWLH. Accordingly, when the threshold voltage for “0” erase of a second N-channel MOS transistor region that is a region in which the second gate conductor layer5bto which the word line WL is connected surrounds the channel region7is denoted by VtWL“0”, as the voltage of the word line WL rises, in a range from Vss to VtWL“0”, the voltage of the channel region7becomes equal to VFB“0”+βBL×VBLH+βWL×VtWL“0” due to second capacitive coupling between the word line WL and the channel region7. When the voltage of the word line WL rises to VtWL“0” or above, an inversion layer12bin a ring form is formed in the channel region7on the inner periphery of the second gate conductor layer5band interrupts the second capacitive coupling between the word line WL and the channel region7.

The description of the write operation of the dynamic flash memory cell will be continued with reference toFIGS.3AA and3AB. From time T3to time T4, for example, a fixed voltage VPLL=2 V is applied to the first gate conductor layer5ato which the plate line PL is connected, and the second gate conductor layer5bto which the word line WL is connected is increased to, for example, VWLH=4 V. As a result, as illustrated inFIG.3AA, an inversion layer12ain a ring form is formed in the channel region7on the inner periphery of the first gate conductor layer5ato which the plate line PL is connected, and a pinch-off point13is present in the inversion layer12a. As a result, a first N-channel MOS transistor region including the first gate conductor layer5aoperates in the saturation region. In contrast, the second N-channel MOS transistor region including the second gate conductor layer5bto which the word line WL is connected operates in the linear region. As a result, a pinch-off point is not present in the channel region7on the inner periphery of the second gate conductor layer5bto which the word line WL is connected, and the inversion layer12bis formed on the entire inner periphery of the gate conductor layer5b. The inversion layer12bthat is formed on the entire inner periphery of the second gate conductor layer5bto which the word line WL is connected substantially functions as the drain of the second N-channel MOS transistor region including the second gate conductor layer5b. As a result, the electric field becomes maximum in a first boundary region of the channel region7between the first N-channel MOS transistor region including the first gate conductor layer5aand the second N-channel MOS transistor region including the second gate conductor layer5bthat are connected in series, and an impact ionization phenomenon occurs in this region. This region is a source-side region when viewed from the second N-channel MOS transistor region including the second gate conductor layer5bto which the word line WL is connected, and therefore, this phenomenon is called a source-side impact ionization phenomenon. By this source-side impact ionization phenomenon, electrons flow from the N+layer3ato which the source line SL is connected toward the N+layer3bto which the bit line is connected. The accelerated electrons collide with lattice Si atoms, and electron-positive hole pairs are generated by the kinetic energy. Although some of the generated electrons flow into the first gate conductor layer5aand into the second gate conductor layer5b, most of the generated electrons flow into the N+layer3bto which the bit line BL is connected (not illustrated).

As illustrated inFIG.3AC, a generated group of positive holes9(which is an example of “group of positive holes” in the claims) are majority carriers in the channel region7, with which the channel region7is charged to a positive bias. The N+layer3ato which the source line SL is connected is at 0 V, and therefore, the channel region7is charged up to the built-in voltage Vb (about 0.7 V) of the PN junction between the N+layer3ato which the source line SL is connected and the channel region7. When the channel region7is charged to a positive bias, the threshold voltages of the first N-channel MOS transistor region and the second N-channel MOS transistor region decrease due to a substrate bias effect.

The description of the write operation of the dynamic flash memory cell will be continued with reference toFIG.3AB. From time T6to time T7, the voltage of the word line WL drops from VWLHto Vss. During this period, although the second capacitive coupling is formed between the word line WL and the channel region7, the inversion layer12binterrupts the second capacitive coupling until the voltage of the word line WL drops from VWLHto a threshold voltage VtWL“1” of the second N-channel MOS transistor region or below when the voltage of the channel region7is equal to Vb. Therefore, the capacitive coupling between the word line WL and the channel region7is substantially formed only during a period from when the word line WL drops to VtWL“1” or below to when the word line WL drops to Vss. As a result, the voltage of the channel region7becomes equal to Vb-βWL×VtWL“1”. Here, VtWL“1” is lower than VtWL“0” described above, and βWL×VtWL“1” is small.

The description of the page write operation of the dynamic flash memory cell will be continued with reference toFIG.3AB. From time T8to time T9, the bit line BL drops from VBLHto Vss. The bit line BL and the channel region7are capacitively coupled with each other, and therefore, the “1” write voltage VFB“1” of the channel region7becomes as follows at the end.
VFB“1”=Vb−βWL×VtWL“1”−βBL×VBLH(7)
Here, the coupling ratio βBLbetween the bit line BL and the channel region7is also small. Accordingly, as illustrated inFIG.3B, the threshold voltage of the second N-channel MOS transistor region of the second channel region7bto which the word line WL is connected decreases. The memory write operation in which the voltage VFB“1” in the “1” write state of the channel region7is assumed to be a first data retention voltage (which is an example of “first data retention voltage” in the claims) is performed to assign logical storage data “1”. In the “0” erase state of the channel region7, the threshold voltage of the first N-channel MOS transistor region of the first channel region7ato which the plate line PL is connected and that of the second N-channel MOS transistor region of the second channel region7bto which the word line WL is connected increase, and therefore, when the voltage applied to the plate line PL is set to the threshold voltage or below, a cell current Icell does not flow even when the voltage of the word line WL is increased.

At the time of the write operation, electron-positive hole pairs may be generated by an impact ionization phenomenon in a second boundary region between the first impurity layer3aand the first channel semiconductor layer7aor in a third boundary region between the second impurity layer3band the second channel semiconductor layer7binstead of the first boundary region, and the channel region7may be charged with the generated group of positive holes9.

Note that the conditions of voltages applied to the bit line BL, the source line SL, the word line WL, and the plate line PL and the potential of the floating body described above are examples for performing the write operation, and other operation conditions based on which the write operation can be performed may be employed.

A mechanism of a page erase operation (which is an example of “page erase operation” in the claims) will be described with reference toFIG.4AtoFIG.4G.

FIG.4Ais a circuit diagram of a memory block for explaining the page erase operation. Although nine memory cells C00to C22in three rows and three columns in plan view are illustrated, the actual memory block is larger than this matrix. When memory cells are arranged in a matrix, one of the directions of the arrangement is called “row direction” (or “in rows”) and the direction perpendicular to the one of the directions is called “column direction” (or “in columns”). To each of the memory cells, a corresponding one of the source line SL0to SL2, a corresponding one of the bit lines BL0to BL2, a corresponding one of the plate lines PL0to PL2, and a corresponding one of the word lines WL0to WL2are connected. The source lines SL0to SL2, the plate lines PL0to PL2, and the word lines WL0to WL2are disposed in parallel, and the bit lines BL0to BL2are disposed in a direction perpendicular to the source lines SL0to SL2, the plate lines PL0to PL2, and the word lines WL0to WL2. For example, it is assumed that the memory cells C10to C12, in a certain page (which is an example of “page” in the claims) P1, to which the plate line PL1, the word line WL1, and the source line SL1are connected are selected in this block and a page erase operation is performed.

FIG.4Bis an operation waveform diagram of the page erase operation. A case where the page erase operation starts and, for example, selective erasing for the page P1is performed will be described. At a first time T1, the word line WL1and the plate line PL1rise from a ground voltage (which is an example of “ground voltage” in the claims) Vss to a first voltage V1and a second voltage V2respectively. Here, the ground voltage Vss is equal to, for example, 0 V. The first voltage V1and the second voltage V2are equal to, for example, 1 V. Next, at a second time T2, the source line SL1drops from the ground voltage Vss to a third voltage V3. Here, the third voltage V3is a negative voltage (which is an example of “negative voltage” in the claims) and is equal to, for example, −1 V. As a result, the PN junction between the first impurity layer3a, which is an N+layer, and the channel region7, which is a P layer, is forward biased, and the group of positive holes9accumulated in the channel region7are discharged to the first impurity layer3a. When the discharge of the group of positive holes9accumulated in the channel region7approaches saturation, at a third time T3, the source line SL1returns from the third voltage V3to the ground voltage Vss, and at a fourth time T4, the word line WL1and the plate line PL1respectively return from the first voltage V1and the second voltage V2to the ground voltage Vss, and the page erase operation ends. The page erase operation in which the voltage VFB“0” in the “0” erase state of the channel region7is assumed to be a second data retention voltage (which is an example of “second data retention voltage” in the claims) is performed to assign logical storage data “0”.

Note that one of the word line WL1or the plate line PL1may rise from the ground voltage Vss to the first voltage V1or the second voltage V2before or after the first time T1. The source line SL1may drop from the ground voltage Vss to the third voltage V3before the first time T1. One of the word line WL1or the plate line PL1may return from the first voltage V1or the second voltage V2to the ground voltage Vss before or after the fourth time T4. The source line SL1may return from the third voltage V3to the ground voltage Vss after the fourth time T4.

When the source line SL1drops from the ground voltage Vss to the third voltage V3at the second time T2, a current flows to the source line SL1from the bit lines BL0to BL2. As a result, in a portion of the channel region7, which is a P layer, adjacent to the second impurity layer3b, which is an N+layer, an impact ionization phenomenon occurs and electron-positive hole pairs are generated. At this time, the group of positive holes9that are generated in the channel region7and the group of positive holes9that are discharged to the first impurity layer3aare in balance, which is a saturation state, and the page erase operation ends.

The state of the semiconductor body during the erase operation will be described with reference toFIGS.4CA to4CC.FIG.4CAillustrates a state before the erase operation, in which the group of positive holes9generated by impact ionization are accumulated in the channel region7. When the page erase operation starts, the PN junction between the source N+layer3aand the channel region7is in a forward bias state as illustrated inFIG.4CB, and the group of positive holes9in the channel region7are discharged to the source N+layer3a. As a result, the voltage VFBof the channel region7becomes equal to the built-in voltage Vb of the PN junction formed by the source N+layer3aand the P-layer channel region7.

Subsequently, when the word line WL and the plate line PL for selective erasing returns from the first voltage V1and the second voltage V2to the ground voltage Vss, the voltage VFBof the channel region7changes from Vb to VFB“0” due to capacitive coupling between the word line WL and the channel region7and between the plate line PL and the channel region7. This state is illustrated inFIG.4CC.

Note that the conditions of voltages applied to the bit line BL, the source line SL, the word line WL, and the plate line PL and the potential of the floating body described above are examples for performing the page erase operation, and other operation conditions based on which the page erase operation can be performed may be employed.

FIG.4Dis an operation waveform diagram in a case where the voltage of the source line SL is set to a positive voltage (“which is an example of “positive voltage” in the claims) in the page erase operation. A case where the page erase operation starts and, for example, selective erasing for the page P1is performed will be described. At the first time T1, the word line WL1and the plate line PL1rise from the ground voltage Vss to a fourth voltage V4and a fifth voltage V5respectively. Here, the ground voltage Vss is equal to, for example, 0 V. The fourth voltage V4and the fifth voltage V5are equal to, for example, 1 V. Next, at the second time T2, the source line SL1rises from the ground voltage Vss to a sixth voltage V6. Here, the sixth voltage V6is equal to, for example, 0.5 V. As a result, a current flows from the source line SL1to the bit lines BL0to BL2, and a group of electrons are poured into the channel region7, which is a Player, from the second impurity layer3b, which is an N+layer. The group of electrons are recombined with the group of positive holes9accumulated in the channel region7, and the group of positive holes9in the channel region7become extinct. When the extinction of the group of positive holes9accumulated in the channel region7approaches saturation, at the third time T3, the source line SL1returns from the sixth voltage V6to the ground voltage Vss, and at the fourth time T4, the word line WL1and the plate line PL1respectively return from the fourth voltage V4and the fifth voltage V5to the ground voltage Vss, and the page erase operation ends. The page erase operation in which the voltage VFB“0” in the “0” erase state of the channel region7is assumed to be the second data retention voltage is performed to assign logical storage data “0”.

Note that one of the word line WL1or the plate line PL1may rise from the ground voltage Vss to the fourth voltage V4or the fifth voltage V5before or after the first time T1. The source line SL1may rise from the ground voltage Vss to the sixth voltage V6before the first time T1. One of the word line WL1or the plate line PL1may return from the fourth voltage V4or the fifth voltage V5to the ground voltage Vss before or after the fourth time T4. The source line SL1may return from the sixth voltage V6to the ground voltage Vss after the fourth time T4.

When the source line SL1rises from the ground voltage Vss to the sixth voltage V6at the second time T2, a current flows from the source line SL1to the bit lines BL0to BL2. As a result, in a portion of the channel region7, which is a P layer, adjacent to the first impurity layer3a, which is an N+layer, an impact ionization phenomenon occurs and electron-positive hole pairs are generated. At this time, the group of positive holes9that are generated in the channel region7and the group of positive holes9that are extinct in the channel region7are in balance, which is a saturation state, and the page erase operation ends.

FIG.4Eis a circuit diagram of a memory block in a case where the source line SL is disposed so as to be shared between pages adjacent to each other. A source line SL01of two pages P0and P1is shared, and a source line SL23of two pages P2and P3is shared.

FIG.4Fis a circuit diagram of a memory block in a case where the plate line PL is disposed so as to be shared between at least two or more pages adjacent to each other. The plate line PL of three pages P0to P2is shared.

FIG.4Gis a diagram of a memory block including main circuits. The word lines WL0to WL2, the plate lines PL0to PL2, and the source lines SL0to SL2are connected to a row decoder circuit RDEC (which is an example of “row decoder circuit” in the claims), the row decoder circuit receives a row address RAD (which is an example of “row address” in the claims), and selection from the pages P0to P2is made in accordance with the row address RAD. The bit lines BL0to BL2are connected to a sense amplifier circuit SA (which is an example of “sense amplifier circuit” in the claims), the sense amplifier circuit SA is connected to a column decoder circuit CDEC (which is an example of “column decoder circuit” in the claims), the column decoder circuit CDEC receives a column address CAD (which is an example of “column address” in the claims), and the sense amplifier circuit SA is selectively connected to an input/output circuit IO (which is an example of “input/output circuit” in the claims) in accordance with the column address CAD.

FIGS.5AA to5ACandFIGS.5BA to5BCare diagrams for explaining a read operation of the dynamic flash memory cell according to the first embodiment of the present invention. With reference toFIGS.5AA to5AC, determination as to whether or not a memory cell current flows, that is, determination of logical “1” or logical “0”, based on the AND logic regarding the word line WL and the plate line PL will be described. As illustrated inFIG.5AA, the levels of the threshold voltages of the word line WL and the plate line PL are determined on the basis of the voltage of the floating body FB. The presence or absence of a memory cell current is determined on the basis of whether the voltages of the word line WL and the plate line PL become equal to their respective threshold voltages or above and whether the word line WL and the plate line PL are conducting or non-conducting. That is, as illustrated inFIG.5AB, the memory cell current Icell is expressed by expression (8) based on the AND logic regarding whether the word line WL is conducting “1” or non-conducting “0” and whether the plate line PL is conducting “1” or non-conducting “0”.
Icell=WL·PL(8)

As illustrated inFIG.5BA, when the channel region7is charged up to the built-in voltage Vb (about 0.7 V), the threshold voltage of the second N-channel MOS transistor region including the second gate conductor layer5bto which the word line WL is connected decreases due to a substrate bias effect. This state is assigned to logical storage data “1”. As illustrated inFIG.5BB, a memory block selected before writing is in an erase state “0” in advance, and the voltage VFBof the channel region7is equal to VFB″O″. With a write operation, a write state “1” is stored at random. As a result, logical storage data of logical “0” and that of logical “1” are created for the word line WL. As illustrated inFIG.5BC, the level difference between the two threshold voltages of the word line WL is used to perform reading by a sense amplifier.

Note that the conditions of voltages applied to the bit line BL, the source line SL, the word line WL, and the plate line PL and the potential of the floating body described above are examples for performing the read operation, and other operation conditions based on which the read operation can be performed may be employed.

Regardless of whether the horizontal cross-sectional shape of the Si column2illustrated inFIG.1is a round shape, an elliptic shape, or a rectangular shape, the operations of the dynamic flash memory described in the embodiment can be performed. Further, a dynamic flash memory cell having a round shape, a dynamic flash memory cell having an elliptic shape, and a dynamic flash memory cell having a rectangular shape may coexist on the same chip.

With reference toFIG.1, the dynamic flash memory element including, for example, an SGT in which the first gate insulator layer4aand the second gate insulator layer4bthat surround the entire side surface of the Si column2standing on the substrate in the vertical direction are provided and which includes the first gate conductor layer5aand the second gate conductor layer5bthat entirely surround the first gate insulator layer4aand the second gate insulator layer4bhas been described. As indicated in the description of the embodiment, the dynamic flash memory element needs to have a structure that satisfies the condition that the group of positive holes9generated by an impact ionization phenomenon are retained in the channel region7. For this, the channel region7needs to have a floating body structure isolated from the substrate. Accordingly, even when the semiconductor body of the channel region is formed horizontally along the substrate (such that the central-axis direction of the semiconductor body is parallel to the substrate) by using, for example, GAA (Gate All Around, see, for example, J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B-G. Park: “Design Optimization of Gate-All-Around (GAA) MOSFETs”, IEEE Trans. Electron Devices, vol. 5, no. 3, pp. 186-191, May 2006) technology, which is one type of SGT, or nanosheet technology (see, for example, N. Loubet, et al.: “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET”, 2017 IEEE Symposium on VLSI Technology Digest of Technical Papers, T17-5, T230-T231, June 2017), the above-described operations of the dynamic flash memory can be performed. The dynamic flash memory element may have a structure in which a plurality of GAA transistors or nanosheets formed in the horizontal direction are stacked. Alternatively, the dynamic flash memory element may have a device structure using SOI (Silicon On Insulator) (see, for example, J. Wan, L. Rojer, A. Zaslavsky, and S. Critoloveanu: “A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration”, Electron Device Letters, Vol. 35, No. 2, pp. 179-181 (2012), T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory design using a one-transistor gain cell on SOI”, IEEE JSSC, vol. 37, No. 11, pp. 1510-1522 (2002), T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, A. Nitayama: “Floating Body RAM Technology and its Scalability to 32 nm Node and Beyond”, IEEE IEDM (2006), and E. Yoshida and T. Tanaka: “A Design of Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory”, IEEE IEDM (2003)). In this device structure, the bottom portion of the channel region is in contact with an insulating layer of the SOI substrate, and the other portion of the channel region is surrounded by a gate insulator layer and an element isolation insulating layer. With such a structure, the channel region also has a floating body structure. Accordingly, the dynamic flash memory element provided in the embodiment needs to satisfy the condition that the channel region has a floating body structure. Even with a structure in which a Fin transistor (see, for example, H. Jiang, N. Xu, B. Chen, L. Zeng1, Y. He, G. Du, X. Liu and X. Zhang: “Experimental investigation of self-heating effect (SHE) in multiple-fin SOI FinFETs”, Semicond. Sci. Technol. 29 (2014) 115021 (7pp)) is formed on an SOI substrate, as long as the channel region has a floating body structure, the dynamic flash operations can be performed.

Expressions (1) to (11) provided in the specification and in the drawings are expressions used to qualitatively explain the phenomena, and are not intended to limit the phenomena.

Although the reset voltages of the word line WL, the bit line BL, and the source line SL are specified as Vss in the descriptions ofFIGS.3AA to3ACandFIG.3B, the reset voltages of the respective lines may be set to different voltages.

AlthoughFIG.4AtoFIG.4Gand the descriptions thereof illustrate example conditions of the page erase operation, the voltages applied to the source line SL, the plate line PL, the bit line BL, and the word line WL may be changed as long as a state in which the group of positive holes9in the channel region7are discharged through either the N+layer3aor the N+layer3bor both the N+layer3aand the N+layer3bcan be attained. Further, in the page erase operation, a voltage may be applied to the source line SL of a selected page, and the bit line BL may be put in a floating state. In the page erase operation, a voltage may be applied to the bit line BL of a selected page, and the source line SL may be put in a floating state.

InFIG.1, in a direction perpendicular to the substrate, in a portion of the channel region7surrounded by the insulating layer6that is the first insulating layer, the potential distribution of the first channel region7aand that of the second channel region7bare connected and formed. Accordingly, the first channel region7aand the second channel region7bthat constitute the channel region7are connected in the vertical direction in the region surrounded by the insulating layer6that is the first insulating layer.

Note that inFIG.1, it is desirable to make the length of the first gate conductor layer5a, in the vertical direction, to which the plate line PL is connected further longer than the length of the second gate conductor layer5b, in the vertical direction, to which the word line WL is connected to attain CPL>CWL. However, when only the plate line PL is added, the coupling ratio (CWL/(CPL+CWL+CBL+CSL)), of capacitive coupling, of the word line WL to the channel region7decreases. As a result, the potential change ΔVFBof the channel region7that is a floating body decreases.

Note that in the specification and the claims, the meaning of “cover” in a case of “for example, a gate insulator layer or a gate conductor layer covers, for example, a channel” also includes a case of surrounding entirely as in an SGT or GAA, a case of surrounding except a portion as in a Fin transistor, and a case of overlapping a flat object as in a planar transistor.

Although the first gate conductor layer5aentirely surrounds the first gate insulator layer4ainFIG.1, a structure may be employed in which the first gate conductor layer5apartially surrounds the first gate insulator layer4ain plan view. The first gate conductor layer5amay be divided into at least two gate conductor layers, and the gate conductor layers may each be operated as a plate line PL electrode. Similarly, the second gate conductor layer5bmay be divided into two or more gate conductor layers, and the gate conductor layers may each function as a conductive electrode of the word line and may be operated synchronously or asynchronously. Accordingly, the operations of the dynamic flash memory can be performed.

InFIG.1, the first gate conductor layer5amay be connected to the word line WL and the second gate conductor layer5bmay be connected to the plate line PL. In this case, the above-described operations of the dynamic flash memory can also be performed.

The embodiment has the following features.

Feature 1

The dynamic flash memory cell of the embodiment is constituted by the N+layers3aand3bthat function as the source and the drain, the channel region7, the first gate insulator layer4a, the second gate insulator layer4b, the first gate conductor layer5a, and the second gate conductor layer5b, which are formed in a columnar form as a whole. The N+layer3athat functions as the source is connected to the source line SL, the N+layer3bthat functions as the drain is connected to the bit line BL, the first gate conductor layer5ais connected to the plate line PL, and the second gate conductor layer5bis connected to the word line WL. A structure is employed in which the gate capacitance of the first gate conductor layer5ato which the plate line PL is connected is larger than the gate capacitance of the second gate conductor layer5bto which the word line WL is connected, which is a feature. In the dynamic flash memory cell, the first gate conductor layer and the second gate conductor layer are stacked in the vertical direction. Accordingly, even when the structure is employed in which the gate capacitance of the first gate conductor layer5ato which the plate line PL is connected is larger than the gate capacitance of the second gate conductor layer5bto which the word line WL is connected, the memory cell area does not increase in plan view. Accordingly, a high-performance and highly integrated dynamic flash memory cell can be implemented.

Feature 2

In the dynamic flash memory cell according to the first embodiment of the present invention, the source line SL, the word line WL, and the plate line PL are disposed parallel to each page P. The bit line BL is disposed in a direction perpendicular to the pages P. As a result, the word line WL, the plate line PL, and the source line SL for controlling each page P can be controlled independently on a page-by-page basis. At the time of the page erase operation, an erase voltage is applied to only the source line SL of a page P for which selective erasing is performed, and the ground voltage Vss can be applied to the source line SL of a non-selected page. Accordingly, a disturbance to the non-selected page P created by the selected page P in the page erase operation can be satisfactorily prevented. Therefore, even when a specific page P is selected a plurality of times and the stored data in the memory cells of the page P is repeatedly rewritten, the memory cells of the other pages P are not affected by a disturbance, and a highly reliable memory device having significantly strong resilience to a disturbance cycle can be provided.

Feature 3

In terms of the roles of the first gate conductor layer5ato which the plate line PL is connected in the dynamic flash memory cell according to the first embodiment of the present invention, in the write operation and in the read operation performed by the dynamic flash memory cell, the voltage of the word line WL changes. At this time, the plate line PL assumes the role of decreasing the capacitive coupling ratio between the word line WL and the channel region7. As a result, an effect on changes in the voltage of the channel region7when the voltage of the word line WL changes can be substantially suppressed. Accordingly, the difference between the threshold voltages of the SGT transistor of the word line WL indicating logical “0” and logical “1” can be increased. This leads to an increased operation margin of the dynamic flash memory cell.

OTHER EMBODIMENTS

Although the Si column is formed in the present invention, a semiconductor column made of a semiconductor material other than Si may be formed. The same applies to other embodiments according to the present invention.

To write “1”, electron-positive hole pairs may be generated by an impact ionization phenomenon using a gate-induced drain leakage (GIDL) current described in E. Yoshida and T. Tanaka: “A Design of Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory”, IEEE IEDM (2003) and E. Yoshida, and T. Tanaka: “A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory”, IEEE Transactions on Electron Devices, Vol. 53, No. 4, pp. 692-69, April 2006, and the floating body FB may be filled with the generated group of positive holes. The same applies to other embodiments according to the present invention.

Even with a structure in which the polarity of the conductivity type of each of the N+layers3aand3band the P-layer Si column2inFIG.1is reversed, the operations of the dynamic flash memory can be performed. In this case, in the Si column2that is of N-type, the majority carriers are electrons. Therefore, a group of electrons generated by impact ionization are accumulated in the channel region7, and a “1” state is set.

The Si columns of the memory cells may be arranged in two dimensions in a square lattice or in a diagonal lattice to form a memory block. When the Si columns are disposed in a diagonal lattice, the Si columns connected to one word line may be disposed in a zigzag pattern or a serrated pattern in which each segment is constituted by a plurality of Si columns. The same applies to other embodiments.

Various embodiments and modifications can be made to the present invention without departing from the spirit and scope of the present invention in a broad sense. The above-described embodiments are intended to explain examples of the present invention and are not intended to limit the scope of the present invention. Any of the above-described embodiments and modifications can be combined. Further, the above-described embodiments from which some of the configuration requirements are removed as needed are also within the scope of the technical spirit of the present invention.

With the semiconductor-element-including memory device according to the present invention, a high-density and high-performance dynamic flash memory that is an SGT-including memory device can be obtained.