Patent ID: 12225737

DETAILED DESCRIPTION

Embodiments of the present invention are now described with reference toFIGS.1-16, it being appreciated that the figures illustrate the subject matter not to scale or to measure. Many figures describe process flows for building devices. These process flows, which are essentially a sequence of steps for building a device, have many structures, numerals and labels that are common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step's figure may have been described in previous steps' figures.

FIG.1A-1Dshows that JLTs that can be 3D stacked fall into four categories based on the number of gates they use: One-side gated JLTs as shown inFIG.1A, two-side gated JLTs as shown inFIG.1B, three-side gated JLTs as shown inFIG.1C, and gate-all-around JLTs as shown inFIG.1D. The JLTS shown may include n+Si102, gate dielectric104, gate electrode106, n+ source region108, n+ drain region110, and n+ region under gate112. As the number of JLT gates increases, the gate gets more control of the channel, thereby reducing leakage of the JLT at 0V. Furthermore, the enhanced gate control can be traded-off for higher doping (which improves contact resistance to source-drain regions) or bigger JLT cross-sectional areas (which is easier from a process integration standpoint). However, adding more gates typically increases process complexity.

Some embodiments of this invention may involve floating body DRAM. Background information on floating body DRAM and its operation is given in “Floating Body RAM Technology and its Scalability to 32 nm Node and Beyond,”Electron Devices Meeting,2006. IEDM '06. International, vol., no., pp. 1-4, 11-13 Dec. 2006 by T. Shino, N. Kusunoki, T. Higashi, et al., Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond, Solid-State Electronics, Volume 53, Issue 7, Papers Selected from the 38th European Solid-State Device Research Conference—ESSDERC'08, July 2009, Pages 676-683, ISSN 0038-1101, DOI: 10.1016/j.sse.2009.03.010 by Takeshi Hamamoto, Takashi Ohsawa, et al., “New Generation of Z-RAM,”Electron Devices Meeting,2007. IEDM2007. IEEE International, vol., no., pp. 925-928, 10-12 Dec. 2007 by Okhonin, S.; Nagoga, M.: Carman, E, et al. The above publications are incorporated herein by reference.

FIG.2A-Kdescribe a process flow to construct a horizontally-oriented monolithic 3D DRAM. This monolithic 3D DRAM utilizes the floating body effect and double-gate transistors. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D DRAM concept shown inFIG.2A-K, and all other masks are shared between different layers. The process flow may include several steps in the following sequence.Step (A): Peripheral circuits with tungsten wiring202are first constructed and above this a layer of silicon dioxide204is deposited.FIG.2Ashows a drawing illustration after Step (A).Step (B):FIG.2Billustrates the structure after Step (B). A wafer of p− Silicon208has an oxide layer206grown or deposited above it. Following this, hydrogen is implanted into the p− Silicon wafer at a certain depth indicated by214. Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer208forms the top layer210. The bottom layer212may include the peripheral circuits202with oxide layer204. The top layer210is flipped and bonded to the bottom layer212using oxide-to-oxide bonding.Step (C):FIG.2Cillustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane3014using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide218is then deposited atop the p− Silicon layer216. At the end of this step, a single-crystal p− Si layer216exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.Step (D):FIG.2Dillustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple p− silicon layers220are formed with silicon oxide layers in between.Step (E):FIG.2Eillustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure, including layer regions of p− silicon221and associated isolation/bonding oxides222.Step (F):FIG.2Fillustrates the structure after Step (F). Gate dielectric226and gate electrode224are then deposited following which a CMP is done to planarize the gate electrode224regions. Lithography and etch are utilized to define gate regions.Step (G):FIG.2Gillustrates the structure after Step (G). Using the hard mask defined in Step (F), p− regions not covered by the gate are implanted to form n+ silicon regions228. Spacers are utilized during this multi-step implantation process and layers of silicon present in different layers of the stack have different spacer widths to account for lateral straggle of buried layer implants. Bottom layers could have larger spacer widths than top layers. A thermal annealing step, such as a RTA or spike anneal or laser anneal or flash anneal, is then conducted to activate n+ doped regions.Step (H):FIG.2Hillustrates the structure after Step (H). A silicon oxide layer230is then deposited and planarized. For clarity, the silicon oxide layer is shown transparent, along with word-line (WL)232and source-line (SL)234regions.Step (I):FIG.2Iillustrates the structure after Step (I). Bit-line (BL) contacts236are formed by etching and deposition. These BL contacts are shared among all layers of memory.Step (J):FIG.2Jillustrates the structure after Step (J). BLs238are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”VLSI Technology,2007IEEE Symposium on, vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.: Yahashi, K.: Oomura, M.: et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (J) as well.
FIG.2Kshows cross-sectional views of the array for clarity. Double-gated transistors may be utilized along with the floating body effect for storing information.
A floating-body DRAM has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.

With the explanations for the formation of monolithic 3D DRAM with ion-cut in this section, it is clear to one skilled in the art that alternative implementations are possible. BL and SL nomenclature has been used for two terminals of the 3D DRAM array, and this nomenclature can be interchanged. Each gate of the double gate 3D DRAM can be independently controlled for better control of the memory cell. To implement these changes, the process steps inFIG.2may be modified. Moreover, selective epi technology or laser recrystallization technology could be utilized for implementing structures shown inFIG.2A-K. Various other types of layer transfer schemes that have been described in Section 1.3.4 of the parent application (Ser. No. 12/901,890, U.S. Pat. No. 8,026,521) can be utilized for construction of various 3D DRAM structures. Furthermore, buried wiring, i.e. where wiring for memory arrays is below the memory layers but above the periphery, may also be used. In addition, other variations of the monolithic 3D DRAM concepts are possible.

While many of today's memory technologies rely on charge storage, several companies are developing non-volatile memory technologies based on resistance of a material changing. Examples of these resistance-based memories include phase change memory, Metal Oxide memory, resistive RAM (RRAM), memristors, solid-electrolyte memory, ferroelectric RAM, MRAM, etc. Background information on these resistive-memory types is given in “Overview of candidate device technologies for storage-class memory,”IBM Journal of Research and Development, vol. 52, no. 4.5, pp. 449-464, July 2008 by Burr, G. W.: Kurdi, B. N.; Scott, J. C.; Lam, C. H.; Gopalakrishnan, K.: Shenoy, R. S.

FIGS.3A-3Jdescribe a novel memory architecture for resistance-based memories, and a procedure for its construction. The memory architecture utilizes junction-less transistors and has a resistance-based memory element in series with a transistor selector. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown inFIG.3A-J, and all other masks are shared between different layers. The process flow may include several steps that occur in the following sequence.Step (A): Peripheral circuits302are first constructed and above this a layer of silicon dioxide304is deposited.FIG.3Ashows a drawing illustration after Step (A).Step (B):FIG.3Billustrates the structure after Step (B). A wafer of n+ Silicon308has an oxide layer306grown or deposited above it. Following this, hydrogen is implanted into the n+ Silicon wafer at a certain depth indicated by314. Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted n+ Silicon wafer308forms the top layer310. The bottom layer312may include the peripheral circuits302with oxide layer304. The top layer310is flipped and bonded to the bottom layer312using oxide-to-oxide bonding.Step (C):FIG.3Cillustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane314using either an anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide318is then deposited atop the n+ Silicon layer316. At the end of this step, a single-crystal n+Si layer316exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.Step (D):FIG.3Dillustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple n+ silicon layers320are formed with silicon oxide layers in between.Step (E):FIG.3Eillustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure, including layer regions of n+ silicon321and associated bonding/isolation oxides322.Step (F):FIG.3Fillustrates the structure after Step (F). Gate dielectric326and gate electrode324are then deposited following which a CMP is performed to planarize the gate electrode324regions. Lithography and etch are utilized to define gate regions.Step (G):FIG.3Gillustrates the structure after Step (G). A silicon oxide layer330is then deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity, along with word-line (WL)332and source-line (SL)334regions.Step (H):FIG.3Hillustrates the structure after Step (H). Vias are etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material336is then deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, well known to change resistance by applying voltage. An electrode for the resistance change memory element is then deposited (preferably using ALD) and is shown as electrode/BL contact340. A CMP process is then conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with junctionless transistors are created after this step.Step (I):FIG.3Iillustrates the structure after Step (I). BLs338are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”VLSI Technology,2007IEEE Symposium on, vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.: Kido, M.: Yahashi, K.: Oomura, M.: et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be achieved in steps prior to Step (I) as well.
FIG.3Jshows cross-sectional views of the array for clarity.
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates that are simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.

FIGS.4A-4Kdescribe an alternative process flow to construct a horizontally-oriented monolithic 3D resistive memory array. This embodiment has a resistance-based memory element in series with a transistor selector. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D resistance change memory (or resistive memory) concept shown inFIGS.4A-4K, and all other masks are shared between different layers. The process flow may include several steps as described in the following sequence.Step (A): Peripheral circuits with tungsten wiring402are first constructed and above this a layer of silicon dioxide404is deposited.FIG.4Ashows a drawing illustration after Step (A).Step (B):FIG.4Billustrates the structure after Step (B). A wafer of p− Silicon408has an oxide layer406grown or deposited above it. Following this, hydrogen is implanted into the p− Silicon wafer at a certain depth indicated by414. Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer408forms the top layer410. The bottom layer412may include the peripheral circuits402with oxide layer404. The top layer410is flipped and bonded to the bottom layer412using oxide-to-oxide bonding.Step (C):FIG.4Cillustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane414using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide418is then deposited atop the p− Silicon layer416. At the end of this step, a single-crystal p− Si layer416exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.Step (D):FIG.4Dillustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple p− silicon layers420are formed with silicon oxide layers in between.Step (E):FIG.4Eillustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure, including layer regions of p− silicon421and associated bonding/isolation oxide422.Step (F):FIG.4Fillustrates the structure on after Step (F). Gate dielectric426and gate electrode424are then deposited following which a CMP is done to planarize the gate electrode424regions. Lithography and etch are utilized to define gate regions.Step (G):FIG.4Gillustrates the structure after Step (G). Using the hard mask defined in Step (F), p− regions not covered by the gate are implanted to form n+ silicon regions428. Spacers are utilized during this multi-step implantation process and layers of silicon present in different layers of the stack have different spacer widths to account for lateral straggle of buried layer implants. Bottom layers could have larger spacer widths than top layers. A thermal annealing step, such as a RTA or spike anneal or laser anneal or flash anneal, is then conducted to activate n+ doped regions.Step (H):FIG.4Hillustrates the structure after Step (H). A silicon oxide layer430is then deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity, along with word-line (WL)432and source-line (SL)434regions.Step (I):FIG.4Iillustrates the structure after Step (I). Vias are etched through multiple layers of silicon and silicon dioxide as shown in the figure. A resistance change memory material436is then deposited (preferably with atomic layer deposition (ALD)). Examples of such a material include hafnium oxide, which is well known to change resistance by applying voltage. An electrode for the resistance change memory element is then deposited (preferably using ALD) and is shown as electrode/BL contact440. A CMP process is then conducted to planarize the surface. It can be observed that multiple resistance change memory elements in series with transistors are created after this step.Step (J):FIG.4Jillustrates the structure after Step (J). BLs438are then constructed. Contacts are made to BLs, WLs and SLs of the memory array at its edges. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”VLSI Technology,2007IEEE Symposium on, vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.: Kido, M.; Yahashi, K.: Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (I) as well.
FIG.4Kshows cross-sectional views of the array for clarity.
A 3D resistance change memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut.

While explanations have been given for formation of monolithic 3D resistive memories with ion-cut in this section, it is clear to one skilled in the art that alternative implementations are possible. BL and SL nomenclature has been used for two terminals of the 3D resistive memory array, and this nomenclature can be interchanged. Moreover, selective epi technology or laser recrystallization technology could be utilized for implementing structures shown inFIG.3A-3JandFIG.4A-4K. Various other types of layer transfer schemes that have been described in Section 1.3.4 of the parent application can be utilized for construction of various 3D resistive memory structures. One could also use buried wiring, i.e. where wiring for memory arrays is below the memory layers but above the periphery. Other variations of the monolithic 3D resistive memory concepts are possible.

While resistive memories described previously form a class of non-volatile memory, others classes of non-volatile memory exist. NAND flash memory forms one of the most common non-volatile memory types. It can be constructed of two main types of devices: floating-gate devices where charge is stored in a floating gate and charge-trap devices where charge is stored in a charge-trap layer such as Silicon Nitride. Background information on charge-trap memory can be found in “Integrated Interconnect Technologies for3D Nanoelectronic Systems”, Artech House, 2009 by Bakir and Meindl (“Bakir”) and “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. The architectures shown inFIG.5A-5Gare relevant for any type of charge-trap memory.

FIGS.5A-5Gdescribes a memory architecture for single-crystal 3D charge-trap memories, and a procedure for its construction. It utilizes junction-less transistors. No mask is utilized on a “per-memory-layer” basis for the monolithic 3D charge-trap memory concept shown inFIG.5A-5G, and all other masks are shared between different layers. The process flow may include several steps as described in the following sequence.Step (A): Peripheral circuits502are first constructed and above this a layer of silicon dioxide504is deposited.FIG.5Ashows a drawing illustration after Step (A).Step (B):FIG.5Billustrates the structure after Step (B). A wafer of n+ Silicon508has an oxide layer506grown or deposited above it. Following this, hydrogen is implanted into the n+ Silicon wafer at a certain depth indicated by514. Alternatively, some other atomic species such as Helium could be implanted. This hydrogen implanted n+ Silicon wafer508forms the top layer510. The bottom layer512may include the peripheral circuits502with oxide layer504. The top layer510is flipped and bonded to the bottom layer512using oxide-to-oxide bonding.Step (C):FIG.5Cillustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) is cleaved at the hydrogen plane514using either a anneal or a sideways mechanical force or other means. A CMP process is then conducted. A layer of silicon oxide518is then deposited atop the n+ Silicon layer516. At the end of this step, a single-crystal n+Si layer516exists atop the peripheral circuits, and this has been achieved using layer-transfer techniques.Step (D):FIG.5Dillustrates the structure after Step (D). Using methods similar to Step (B) and (C), multiple n+ silicon layers520are formed with silicon oxide layers in between.Step (E):FIG.5Eillustrates the structure after Step (E). Lithography and etch processes are then utilized to make a structure as shown in the figure.Step (F):FIG.5Fillustrates the structure after Step (F). Gate dielectric526and gate electrode524are then deposited following which a CMP is done to planarize the gate electrode524regions. Lithography and etch are utilized to define gate regions. Gates of the NAND string536as well gates of select gates of the NAND string538are defined.Step (G):FIG.5Gillustrates the structure after Step (G). A silicon oxide layer530is then deposited and planarized. It is shown transparent in the figure for clarity. Word-lines, bit-lines and source-lines are defined as shown in the figure. Contacts are formed to various regions/wires at the edges of the array as well. SL contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”VLSI Technology,2007IEEE Symposium on, vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.: Kido, M.; Yahashi, K.; Oomura, M.: et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be performed in steps prior to Step (G) as well.
A 3D charge-trap memory has thus been constructed, with (1) horizontally-oriented transistors—i.e. current flowing in substantially the horizontal direction in transistor channels, (2) some of the memory cell control lines—e.g., bit lines BL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. This use of single-crystal silicon obtained with ion-cut is a key differentiator from past work on 3D charge-trap memories such as “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. that used polysilicon.

WhileFIGS.5A-5Ggive two examples of how single-crystal silicon layers with ion-cut can be used to produce 3D charge-trap memories, the ion-cut technique for 3D charge-trap memory is fairly general. It could be utilized to produce any horizontally-oriented 3D monocrystalline-silicon charge-trap memory.

While the 3D DRAM and 3D resistive memory implementations in Section 3 and Section 4 have been described with single crystal silicon constructed with ion-cut technology, other options exist. One could construct them with selective epi technology. Procedures for doing these will be clear to those skilled in the art.

FIGS.6A-6Bshow it is not the only option for the architecture to have the peripheral transistors, such as periphery602, below the memory layers, including, for example, memory layer604, memory layer606, and/or memory layer608. Peripheral transistors, such as periphery610, could also be constructed above the memory layers, including, for example, memory layer604, memory layer606, and/or memory layer608, and substrate or memory layer612, as shown inFIG.6B. This periphery layer would utilize technologies described in this application: parent application and incorporated references, and could utilize transistors, for example, junction-less transistors or recessed channel transistors.

The monolithic 3D integration concepts described in this patent application can lead to novel embodiments of poly-silicon-based memory architectures as well. Poly silicon based architectures could potentially be cheaper than single crystal silicon based architectures when a large number of memory layers need to be constructed. While the below concepts are explained by using resistive memory architectures as an example, it will be clear to one skilled in the art that similar concepts can be applied to NAND flash memory and DRAM architectures described previously in this patent application.

FIGS.7A-7Eshow one embodiment of the current invention, where polysilicon junction-less transistors are used to form a 3D resistance-based memory. The utilized junction-less transistors can have either positive or negative threshold voltages. The process may include the following steps as described in the following sequence:Step (A): As illustrated inFIG.7A, peripheral circuits702are constructed above which a layer of silicon dioxide704is made.Step (B): As illustrated inFIG.7B, multiple layers of n+ doped amorphous silicon or polysilicon706are deposited with layers of silicon dioxide708in between. The amorphous silicon or polysilicon layers706could be deposited using a chemical vapor deposition process, such as LPCVD or PECVD.Step (C): As illustrated inFIG.7C, a Rapid Thermal Anneal (RTA) is conducted to crystallize the layers of polysilicon or amorphous silicon deposited in Step (B). Temperatures during this RTA could be as high as 700° C. or more, and could even be as high as 800° C. The polysilicon region obtained after Step (C) is indicated as710. Alternatively, a laser anneal could be conducted, either for all layers706at the same time or layer by layer. The thickness of the oxide704would need to be optimized if that process were conducted.Step (D): As illustrated inFIG.7D, procedures similar to those described inFIGS.3E-3Hare utilized to construct the structure shown. The structure inFIG.7Dhas multiple levels of junction-less transistor selectors for resistive memory devices. The resistance change memory is indicated as736while its electrode and contact to the BL is indicated as740. The WL is indicated as732, while the SL is indicated as734. Gate dielectric of the junction-less transistor is indicated as726while the gate electrode of the junction-less transistor is indicated as724, this gate electrode also serves as part of the WL732. Silicon oxide is indicated as730.Step (E): As illustrated inFIG.7E, bit lines (indicated as BL738) are constructed. Contacts are then made to peripheral circuits and various parts of the memory array as described in embodiments described previously.

FIG.8A-Fshow another embodiment of the current invention, where polysilicon junction-less transistors are used to form a 3D resistance-based memory. The utilized junction-less transistors can have either positive or negative threshold voltages. The process may include the following steps occurring in sequence:Step (A): As illustrated inFIG.8A, a layer of silicon dioxide804is deposited or grown above a silicon substrate without circuits802.Step (B): As illustrated inFIG.8B, multiple layers of n+ doped amorphous silicon or polysilicon806are deposited with layers of silicon dioxide808in between. The amorphous silicon or polysilicon layers806could be deposited using a chemical vapor deposition process, such as LPCVD or PECVD abbreviated as above.Step (C): As illustrated inFIG.8C, a Rapid Thermal Anneal (RTA) or standard anneal is conducted to crystallize the layers of polysilicon or amorphous silicon deposited in Step (B). Temperatures during this RTA could be as high as 700° C. or more, and could even be as high as 1400° ° C. The polysilicon region obtained after Step (C) is indicated as810. Since there are no circuits under these layers of polysilicon, very high temperatures (such as 1400° C.) can be used for the anneal process, leading to very good quality polysilicon with few grain boundaries and very high mobilities approaching those of single crystal silicon. Alternatively, a laser anneal could be conducted, either for all layers806at the same time or layer by layer at different times.Step (D): This is illustrated inFIG.8D. Procedures similar to those described inFIG.32E-Hof incorporated parent reference U.S. Pat. No. 8,026,521, are utilized to obtain the structure shown inFIG.8Dwhich has multiple levels of junctionless transistor selectors for resistive memory devices. The resistance change memory is indicated as836while its electrode and contact to the BL is indicated as840. The WL is indicated as832, while the SL is indicated as834. Gate dielectric of the junction-less transistor is indicated as826while the gate electrode of the junction-less transistor is indicated as824, this gate electrode also serves as part of the WL832. Silicon oxide is indicated as830Step (E): This is illustrated inFIG.8E. Bit lines (indicated as BL838) are constructed. Contacts are then made to peripheral circuits and various parts of the memory array as described in embodiments described previously.Step (F): Using procedures described in Section 1 and Section 2 of this patent application's parent, peripheral circuits898(with transistors and wires) could be formed well aligned to the multiple memory layers shown in Step (E). For the periphery, one could use the process flow shown in Section 2 where replacement gate processing is used, or one could use sub-400° C. processed transistors such as junction-less transistors or recessed channel transistors. Alternatively, one could use laser anneals for peripheral transistors' source-drain processing. Various other procedures described in Section 1 and Section 2 could also be used. Connections can then be formed between the multiple memory layers and peripheral circuits. By proper choice of materials for memory layer transistors and memory layer wires (e.g., by using tungsten and other materials that withstand high temperature processing for wiring), even standard transistors processed at high temperatures (>1000)° ° C. for the periphery could be used.

Section 1, of incorporated parent reference U.S. Pat. No. 8,026,521, described the formation of 3D stacked semiconductor circuits and chips with sub-400° ° C. processing temperatures to build transistors and high density of vertical connections. In this section an alternative method is explained, in which a transistor is built with any replacement gate (or gate-last) scheme that is utilized widely in the industry. This method allows for high temperatures (above 400 C) to build the transistors. This method utilizes a combination of three concepts:Replacement gate (or gate-last) high k/metal gate fabricationFace-up layer transfer using a carrier waferMisalignment tolerance techniques that utilize regular or repeating layouts. In these repeating layouts, transistors could be arranged in substantially parallel bands.
A very high density of vertical connections is possible with this method. Single crystal silicon (or monocrystalline silicon) layers that are transferred are less than 2 um thick, or could even be thinner than 0.4 um or 0.2 um.

The method mentioned in the previous paragraph is described inFIG.9A-9F. The procedure may include several steps as described in the following sequence:Step (A): After creating isolation regions using a shallow-trench-isolation (STI) process2504, dummy gates2502are constructed with silicon dioxide and poly silicon. The term “dummy gates” is used since these gates will be replaced by high k gate dielectrics and metal gates later in the process flow, according to the standard replacement gate (or gate-last) process. Further details of replacement gate processes are described in “A 45 nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging,” IEDM Tech. Dig., pp. 247-250, 2007 by K. Mistry, et al. and “Ultralow-EOT (5 Å) Gate-First and Gate-Last High Performance CMOS Achieved by Gate-Electrode Optimization,” IEDM Tech. Dig., pp. 663-666, 2009 by L. Ragnarsson, et al.FIG.9Aillustrates the structure after Step (A).Step (B): Rest of the transistor fabrication flow proceeds with formation of source-drain regions2506, strain enhancement layers to improve mobility, high temperature anneal to activate source-drain regions2506, formation of inter-layer dielectric (ILD)2508, etc.FIG.9Billustrates the structure after Step (B).Step (C): Hydrogen is implanted into the wafer at the dotted line regions indicated by2510.FIG.9Cillustrates the structure after Step (C).Step (D): The wafer after step (C) is bonded to a temporary carrier wafer2512using a temporary bonding adhesive2514. This temporary carrier wafer2512could be constructed of glass. Alternatively, it could be constructed of silicon. The temporary bonding adhesive2514could be a polymer material, such as a polyimide. A anneal or a sideways mechanical force is utilized to cleave the wafer at the hydrogen plane2510. A CMP process is then conducted.FIG.9Dillustrates the structure after Step (D).Step (E): An oxide layer2520is deposited onto the bottom of the wafer shown in Step (D). The wafer is then bonded to the bottom layer of wires and transistors2522using oxide-to-oxide bonding. The bottom layer of wires and transistors2522could also be called a base wafer. The temporary carrier wafer2512is then removed by shining a laser onto the temporary bonding adhesive2514through the temporary carrier wafer2512(which could be constructed of glass). Alternatively, an anneal could be used to remove the temporary bonding adhesive2514. Through-silicon connections2516with a non-conducting (e.g. oxide) liner2515to the landing pads2518in the base wafer could be constructed at a very high density using special alignment methods described in at leastFIG.26A-DandFIG.27A-Fof incorporated parent reference U.S. Pat. No. 8,026,521.FIG.9Eillustrates the structure after Step (E).Step (F): Dummy gates2502are etched away, followed by the construction of a replacement with high k gate dielectrics2524and metal gates2526. Essentially, partially-formed high performance transistors are layer transferred atop the base wafer (may also be called target wafer) followed by the completion of the transistor processing with a low (sub 400° C.) process.FIG.9Fillustrates the structure after Step (F). The remainder of the transistor, contact, and wiring layers are then constructed.

It will be obvious to someone skilled in the art that alternative versions of this flow are possible with various methods to attach temporary carriers and with various versions of the gate-last process flow.

FIGS.10A-10D(andFIG.45A-Dof incorporated parent reference U.S. Pat. No. 8,026,521) show an alternative procedure for forming CMOS circuits with a high density of connections between stacked layers. The process utilizes a repeating pattern in one direction for the top layer of transistors. The procedure may include several steps in the following sequence:Step (A): Using procedures similar toFIG.9A-F, a top layer of transistors4404is transferred atop a bottom layer of transistors and wires4402. Landing pads4406are utilized on the bottom layer of transistors and wires4402. Dummy gates4408and4410are utilized for nMOS and pMOS. The key difference between the structures shown inFIG.9A-Fand this structure is the layout of oxide isolation regions between transistors.FIG.10Aillustrates the structure after Step (A).Step (B): Through-silicon connections4412are formed well-aligned to the bottom layer of transistors and wires4402. Alignment schemes to be described inFIG.45A-Dof incorporated parent reference U.S. Pat. No. 8,026,521 are utilized for this purpose. All features constructed in future steps are also formed well-aligned to the bottom layer of transistors and wires4402.FIG.10Billustrates the structure after Step (B).Step (C): Oxide isolation regions4414are formed between adjacent transistors to be defined. These isolation regions are formed by lithography and etch of gate and silicon regions and then fill with oxide.FIG.10Cillustrates the structure after Step (C).Step (D): The dummy gates4408and4410are etched away and replaced with replacement gates4416and4418. These replacement gates are patterned and defined to form gate contacts as well.FIG.10Dillustrates the structure after Step (D). Following this, other process steps in the fabrication flow proceed as usual.

FIGS.11A-11Gillustrate using a carrier wafer for layer transfer.FIG.11Aillustrates the first step of preparing transistors with dummy gates4602on first donor wafer (or top wafer)4606. This completes the first phase of transistor formation.

FIG.11Billustrates forming a cleave line4608by implant4616of atomic particles such as H+.FIG.11Cillustrates permanently bonding the first donor wafer4606to a second donor wafer4626. The permanent bonding may be oxide to oxide wafer bonding as described previously.

FIG.11Dillustrates the second donor wafer4626acting as a carrier wafer after cleaving the first donor wafer off potentially at face4632: leaving a thin layer4606with the now buried dummy gate transistors4602.FIG.11Eillustrates forming a second cleave line4618in the second donor wafer4626by implant4646of atomic species such as H+.

FIG.11Fillustrates the second layer transfer step to bring the dummy gate transistors4602ready to be permanently bonded on top of the bottom layer of transistors and wires4601. For the simplicity of the explanation we left out the now obvious steps of surface layer preparation done for each of these bonding steps.

FIG.11Gillustrates the bottom layer of transistors and wires4601with the dummy gate transistor4602on top after cleaving off the second donor wafer and removing the layers on top of the dummy gate transistors. Now we can proceed and replace the dummy gates with the final gates, form the metal interconnection layers, and continue the 3D fabrication process.

An interesting alternative is available when using the carrier wafer flow described inFIG.11A-11G. In this flow we can use the two sides of the transferred layer to build NMOS on one side and PMOS on the other side. Timing properly the replacement gate step such flow could enable full performance transistors properly aligned to each other. As illustrated inFIG.12A, an SOI (Silicon On Insulator) donor (or top) wafer4700may be processed in the normal state of the art high k metal gate gate-last manner with adjusted thermal cycles to compensate for later thermal processing up to the step prior to where CMP exposure of the polysilicon dummy gates4704takes place.FIG.12Aillustrates a cross section of the SOI donor wafer substrate4700, the buried oxide (BOX)4701, the thin silicon layer4702of the SOI wafer, the isolation4703between transistors, the polysilicon4704and gate oxide4705of n-type CMOS transistors with dummy gates, their associated source and drains4706for NMOS, NMOS transistor channel regions4707, and the NMOS interlayer dielectric (ILD)4708. Alternatively, the PMOS device may be constructed at this stage. This completes the first phase of transistor formation.

At this step, or alternatively just after a CMP of layer4708to expose the polysilicon dummy gates4704or to planarize the oxide layer4708and not expose the dummy gates4704, an implant of an atomic species4710, such as H+, is done to prepare the cleaving plane4712in the bulk of the donor substrate, as illustrated inFIG.12B.

The SOI donor wafer4700is now permanently bonded to a carrier wafer4720that has been prepared with an oxide layer4716for oxide to oxide bonding to the donor wafer surface4714as illustrated inFIG.12C. The details have been described previously. The donor wafer4700may then be cleaved at the cleaving plane4712and may be thinned by chemical mechanical polishing (CMP) and surface4722may be prepared for transistor formation. The donor wafer layer4700at surface4722may be processed in the normal state of the art gate last processing to form the PMOS transistors with dummy gates. During processing the wafer is flipped so that surface4722is on top, but for illustrative purposes this is not shown in the subsequentFIGS.12E-12G.

FIG.12Eillustrates the cross section with the buried oxide (BOX)4701, the now thin silicon layer4700of the SOI substrate, the isolation4733between transistors, the polysilicon4734and gate oxide4735of p-type CMOS dummy gates, their associated source and drains4736for PMOS, PMOS transistor channel regions4737and the PMOS interlayer dielectric (ILD)4738. The PMOS transistors may be precisely aligned at state of the art tolerances to the NMOS transistors due to the shared substrate4700possessing the same alignment marks. At this step, or alternatively just after a CMP of layer4738to expose the PMOS polysilicon dummy gates or to planarize the oxide layer4738and not expose the dummy gates, the wafer could be put into high temperature cycle to activate both the dopants in the NMOS and the PMOS source drain regions.

Then an implant of an atomic species4740, such as H+, may prepare the cleaving plane4721in the bulk of the carrier wafer substrate4720for layer transfer suitability, as illustrated inFIG.12F. The PMOS transistors are now ready for normal state of the art gate-last transistor formation completion.

As illustrated inFIG.12G, the inter layer dielectric4738may be chemical mechanically polished to expose the top of the polysilicon dummy gates4734. The dummy polysilicon gates4734may then be removed by etch and the PMOS hi-k gate dielectric4740and the PMOS specific work function metal gate4741may be deposited. An aluminum fill4742may be performed on the PMOS gates and the metal CMP′ed. A dielectric layer4739may be deposited and the normal gate4743and source/drain4744contact formation and metallization.

The PMOS layer to NMOS layer via4747and metallization may be partially formed as illustrated inFIG.12Gand an oxide layer4748is deposited to prepare for bonding.

The carrier wafer and two sided n/p layer is then permanently bonded to bottom wafer having transistors and wires4799with associated metal landing strip4750as illustrated inFIG.12H.

The carrier wafer4720may then be cleaved at the cleaving plane4721and may be thinned by chemical mechanical polishing (CMP) to oxide layer4716as illustrated inFIG.12I.

The NMOS transistors are now ready for normal state of the art gate-last transistor formation completion. As illustrated inFIG.12J, the oxide layer4716and the NMOS inter layer dielectric4708may be chemical mechanically polished to expose the top of the NMOS polysilicon dummy gates4704. The dummy polysilicon gates4704may then be removed by etch and the NMOS hi-k gate dielectric4760and the NMOS specific work function metal gate4761may be deposited. An aluminum fill4762may be performed on the NMOS gates and the metal CMP′ed. A dielectric layer4769may be deposited and the normal gate4763and source/drain4764contact formation and metallization. The NMOS layer to PMOS layer via4767to connect to4747and metallization may be formed.

As illustrated inFIG.12K, the layer-to-layer contacts4772to the landing pads in the base wafer are now made. This same contact etch could be used to make the connections4773between the NMOS and PMOS layer as well, instead of using the two step (4747and4767) method inFIG.12H.

Using procedures similar toFIG.12A-K, it is possible to construct structures such asFIG.13where a transistor is constructed with front gate4902and back gate4904. The back gate could be utilized for many purposes such as threshold voltage control, reduction of variability, increase of drive current and other purposes.

FIG.14A-14Jdescribes a process flow for forming four-side gated JLTs in 3D stacked circuits and chips. Four-side gated JLTs can also be referred to as gate-all around JLTs or silicon nanowire JLTs. They offer excellent electrostatic control of the channel and provide high-quality I-V curves with low leakage and high drive currents. The process flow inFIG.14A-14Jmay include several steps in the following sequence:Step (A): On a p− Si wafer902, multiple n+Si layers904and908and multiple n+ SiGe layers906and910are epitaxially grown. The Si and SiGe layers are carefully engineered in terms of thickness and stoichiometry to keep defect density due to lattice mismatch between Si and SiGe low. Some techniques for achieving this include keeping thickness of SiGe layers below the critical thickness for forming defects. A silicon dioxide layer912is deposited above the stack.FIG.14Aillustrates the structure after Step (A) is completed.Step (B): Hydrogen is implanted at a certain depth in the p− wafer, to form a cleave plane920after bonding to bottom wafer of the two-chip stack. Alternatively, some other atomic species such as He can be used.FIG.14Billustrates the structure after Step (B) is completed.Step (C): The structure after Step (B) is flipped and bonded to another wafer on which bottom layers of transistors and wires914are constructed. Bonding occurs with an oxide-to-oxide bonding process.FIG.14Cillustrates the structure after Step (C) is completed.Step (D): A cleave process occurs at the hydrogen plane using a sideways mechanical force. Alternatively, an anneal could be used for cleaving purposes. A CMP process is conducted till one reaches the n+ Si layer904.FIG.14Dillustrates the structure after Step (D) is completed.Step (E): Using litho and etch, Si918and SiGe916regions are defined to be in locations where transistors are required. Oxide920is deposited to form isolation regions and to cover the Si/SiGe regions916and918. A CMP process is conducted.FIG.14Eillustrates the structure after Step (E) is completed.Step (F): Using litho and etch, Oxide regions920are removed in locations where a gate needs to be present. It is clear that Si regions918and SiGe regions916are exposed in the channel region of the JLT.FIG.14Fillustrates the structure after Step (F) is completed.Step (G): SiGe regions916in channel of the JLT are etched using an etching recipe that does not attack Si regions918. Such etching recipes are described in “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” inProc. IEDM Tech. Dig.,2005, pp. 717-720 by S. D. Suk, S.-Y. Lee, S.-M. Kim, et al. (“Suk”).FIG.14Gillustrates the structure after Step (G) is completed.Step (H): This is an optional step where a hydrogen anneal can be utilized to reduce surface roughness of fabricated nanowires. The hydrogen anneal can also reduce thickness of nanowires. Following the hydrogen anneal, another optional step of oxidation (using plasma enhanced thermal oxidation) and etch-back of the produced silicon dioxide can be used. This process thins down the silicon nanowire further.FIG.14Hillustrates the structure after Step (H) is completed.Step (I): Gate dielectric and gate electrode regions are deposited or grown. Examples of gate dielectrics include hafnium oxide, silicon dioxide, etc. Examples of gate electrodes include polysilicon, TiN, TaN, etc. A CMP is conducted after gate electrode deposition. Following this, rest of the process flow for forming transistors, contacts and wires for the top layer continues.FIG.14Iillustrates the structure after Step (I) is completed.
FIG.14Jshows a cross-sectional view of structures after Step (I). It is clear that two nanowires are present for each transistor in the figure. It is possible to have one nanowire per transistor or more than two nanowires per transistor by changing the number of stacked Si/SiGe layers.

Note that top-level transistors are formed well-aligned to bottom-level wiring and transistor layers. Since the top-level transistor layers are very thin (preferably less than 200 nm), the top transistors can be aligned to features in the bottom-level. While the process flow shown inFIG.14A-14Jgives the key steps involved in forming a four-side gated JLT with 3D stacked components, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to junctionless transistors can be added. Furthermore, more than two layers of chips or circuits can be 3D stacked. Also, there are many methods to construct silicon nanowire transistors and these are described in “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,”Electron Devices Meeting(IEDM), 2009IEEE International, vol., no., pp. 1-4, 7-9 Dec. 2009 by Bangsaruntip, S.: Cohen, G. M.; Majumdar, A.: et al. (“Bangsaruntip”) and in “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” inProc. IEDM Tech. Dig.,2005, pp. 717-720 by S. D. Suk, S.-Y. Lee, S.-M. Kim, et al. (“Suk”). Contents of these publications are incorporated herein by reference. Techniques described in these publications can be utilized for fabricating four-side gated JLTs without junctions as well.

Most of the figures described thus far in this document assumed the transferred top layer of silicon is very thin (preferably <200 nm). This enables light to penetrate the silicon and allows features on the bottom wafer to be observed. However, that is not always the case.FIG.15A-15Cshows a process flow for constructing 3D stacked chips and circuits when the thickness of the transferred/stacked piece of silicon is so high that light does not penetrate the transferred piece of silicon to observe the alignment marks on the bottom wafer. The process to allow for alignment to the bottom wafer may include several steps as described in the following sequence.Step (A): A bottom wafer2312is processed to form a bottom transistor layer2306and a bottom wiring layer2304. A layer of silicon oxide2302is deposited above it.FIG.15Aillustrates the structure after Step (A).Step (B): A wafer of p− Si2310has an oxide layer2306deposited or grown above it. Using lithography, a window pattern is etched into the p− Si2310and is filled with oxide. A step of CMP is done. This window pattern will be used inStep (C) to allow light to penetrate through the top layer of silicon to align to circuits on the bottom wafer2312. The window size is chosen based on misalignment tolerance of the alignment scheme used while bonding the top wafer to the bottom wafer in Step (C). Furthermore, some alignment marks also exist in the wafer of p− Si2310.FIG.15Billustrates the structure after Step (B). Step (C): A portion of the p− Si2310from Step (B) is transferred atop the bottom wafer2312using procedures similar toFIG.2A-Eof incorporated by reference U.S. Pat. No. 8,026,521 issued on Sep. 27, 2011. It can be observed that the window2316can be used for aligning features constructed on the top wafer2314to features on the bottom wafer2312. Thus, the thickness of the top wafer2314can be chosen without constraints.FIG.15Cillustrates the structure after Step (C).

FIG.16A-16Hdescribe a process flow to construct a horizontally-oriented monolithic 3D DRAM. Two masks are utilized on a “per-memory-layer” basis for the monolithic 3D DRAM concept shown inFIG.16A-16H, while other masks are shared between all constructed memory layers. The process flow may include several steps in the following sequence.Step (A): A p− Silicon wafer2901is taken and an oxide layer2902is grown or deposited above it.FIG.16Aillustrates the structure after Step (A).Step (B): Hydrogen is implanted into the p− wafer2901at a certain depth denoted by2903.FIG.16Billustrates the structure after Step (B).Step (C): The wafer after Step (B) is flipped and bonded onto a wafer having peripheral circuits2904covered with oxide. This bonding process occurs using oxide-to-oxide bonding. The stack is then cleaved at the hydrogen implant plane2903using either an anneal or a sideways mechanical force. A chemical mechanical polish (CMP) process is then conducted. Note that peripheral circuits2904are such that they can withstand an additional rapid-thermal-anneal (RTA) and still remain operational, and preferably retain good performance. For this purpose, the peripheral circuits2904may be such that they have not had their RTA for activating dopants or they have had a weak RTA for activating dopants. Also, peripheral circuits2904utilize a refractory metal such as tungsten that can withstand high temperatures greater than 400° C.FIG.29Cillustrates the structure after Step (C).Step (D): The transferred layer of p− silicon after Step (C) is then processed to form isolation regions using a STI process. Following, gate regions2905are deposited and patterned, following which source-drain regions2908are implanted using a self-aligned process. An inter-level dielectric (ILD) constructed of oxide (silicon dioxide)2906is then constructed. Note that no RTA is done to activate dopants in this layer of partially-depleted SOI (PD-SOI) transistors. Alternatively, transistors could be of fully-depleted SOI type.FIG.16Dillustrates the structure after Step (D).Step (E): Using steps similar to Step (A)-Step (D), another layer of memory2909is constructed. After all the desired memory layers are constructed, a RTA is conducted to activate dopants in all layers of memory (and potentially also the periphery).FIG.16Eillustrates the structure after Step (E).Step (F): Contact plugs2910are made to source and drain regions of different layers of memory. Bit-line (BL) wiring2911and Source-line (SL) wiring2912are connected to contact plugs2910. Gate regions2913of memory layers are connected together to form word-line (WL) wiring.FIG.16Fillustrates the structure after Step (F).FIG.16Gand FIG.16H describe array organization of the floating-body DRAM: BLs2916in a direction substantially perpendicular to the directions of SLs2915and WLs2914.

It will also be appreciated by persons of ordinary skill in the art that the invention is not limited to what has been particularly shown and described hereinabove. For example, drawings or illustrations may not show n or p wells for clarity in illustration. Further, combinations and sub-combinations of the various features described hereinabove may be utilized to form a 3D IC based system. Rather, the scope of the invention includes both combinations and sub-combinations of the various features described hereinabove as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by the appended claims.