Patent ID: 12206383

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the present disclosure are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing exemplary embodiments of the present disclosure. Thus, exemplary embodiments of the present disclosure may be embodied in many alternate forms and should not be construed as limited to exemplary embodiments of the present disclosure set forth herein.

Accordingly, while the present disclosure is capable of various modifications and alternative forms, specific exemplary embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the present disclosure to the particular forms disclosed, but on the contrary, the present disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure. Like numbers refer to like elements throughout the description of the figures.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

In exemplary embodiments of the present disclosure, “at least one of A and B” may refer to “at least one of A or B” or “at least one of combinations of one or more of A and B”. In addition, “one or more of A and B” may refer to “one or more of A or B” or “one or more of combinations of one or more of A and B”.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (i.e., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, exemplary embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings. In order to facilitate general understanding in describing the present disclosure, the same components in the drawings are denoted with the same reference signs, and repeated description thereof will be omitted.

An orthogonal signal is generated based on the way of generating phase signals of +45 degrees and −45 degrees, respectively, between P2and P3based on an input P1in an LC/CL resonator, and splitting an orthogonal phase signal between output nodes.

FIGS.2A to2Dare views for describing a basic structure of a resonance circuit of an I/Q quadrature signal generator based on an LC/CL polyphase filter that may be adopted in a dual-band phase shifter according to one embodiment of the present disclosure.

Referring toFIGS.2A to2D, most resonance circuits used in a polyphase filter inside the I/Q generator (seeFIG.1) include a capacitor C0and an inductor L0. The present embodiment is based on changing the capacitor C0to a series resonance circuit of a first capacitor C1and a first inductor L1, and changing the inductor L0to a parallel resonance circuit of the first capacitor C1and the first inductor L1.

The basic configuration and operating principle of the orthogonal signal generator based on the LC/CL polyphase scheme are described in Related Art Document 1.

Meanwhile, in the structure of the existing polyphase filter, a phase is exactly 90 degrees only at one frequency and the amplitude occurs at the same frequency. This structure typically operates in a wide band and defines the operating range according to the specification of amplitude and phase errors.

In addition, in order to achieve wider band operation, the wide band operation may be implemented by controlling a capacitance with a variable capacitor in the structure of the existing polyphase filter. In this case, however, a decrease in an image rejection ratio (IRR) caused by insertion loss has to be tolerated.

Accordingly, in the present embodiment, without using the variable capacitor, a capacitor in the polyphase filter is changed to an LC series resonance circuit and an inductor in the polyphase filter is changed to an LC parallel resonance circuit. When this polyphase filter structure is used, a dual-band circuit is implemented without an additional control circuit.

FIGS.3A to3Dare views for describing a polyphase filter-based orthogonal signal generator that may be adopted in the dual-band phase shifter according to one embodiment of the present disclosure and an operating principle thereof.

Referring toFIGS.3A to3D, the orthogonal signal generated inside the orthogonal signal generator is generated by generating phase signals of +45° and −45°, respectively, between P2and P3based on an input P1in the LC/CL resonator and splitting an orthogonal phase signal between the output nodes.

Here, in order to change the capacitor C0to the LC series resonance circuit, a first terminal of the inductor L0may be connected to a second terminal of the capacitor C0in a structure in which the inductor L0is connected to the capacitor C0in parallel when viewed from an output terminal P3. A first terminal of the capacitor C0is connected to an input terminal P1, and a resistor R0may be disposed between a second terminal of the inductor L0and the ground. In that case, the orthogonal signal generator may operate so that a phase of one of output nodes thereof has a +45° direction, as illustrated in a graph of expressing a gain at the frequency of a gigahertz (GHz) frequency band (seeFIGS.3A and3B).

Similarly, in order to change the inductor L0to the LC parallel resonance circuit, the first terminal of the capacitor C0may be connected to the second terminal of the inductor L0in a structure in which the capacitor C0is connected to the inductor L0in parallel when viewed from an output terminal P2. The first terminal of the inductor L0is connected to the input terminal P1, and another resistor R0may be connected between the second terminal of the capacitor C0and the ground. In this case, the orthogonal signal generator may operate so that a phase of one of output nodes thereof has a −45° direction, as illustrated in a graph of expressing a gain at the frequency of the gigahertz (GHz) frequency band (seeFIGS.3C and3D).

When a dual-band frequency required in this case is defined as f1, f2, and input/output load resistance is defined as RS, RL, a center frequency (f0) can be calculated using Equations (1) to (3) below.

f0=f1×f2〈Equation⁢(1)〉C1=1-(f1f0)22⁢π⁢f1×RS×RL〈Equation⁢(2)〉L1=1(2×π×f0)2×C1〈Equation⁢(3)〉

When each of the values calculated by applying Equations (1) to (3) is applied to each of C1, L1, a dual-band polyphase filter may be implemented as illustrated inFIGS.4A to4D.

FIGS.4A to4Dare views for describing a resonance circuit of the dual-band polyphase filter that may be adopted in the dual-band phase shifter according to one embodiment of the present disclosure and an operating principle thereof.

Referring toFIGS.4A and4B, the orthogonal signal generated inside the orthogonal signal generator may operate to generate dual-band phase signals of +45° and −45° between output nodes P3based on an input of an input node P1in the dual-band phase shifter circuit to sequentially output the orthogonal phase signals from the output node P3.

Herein, a series resonance circuit of the first capacitor C1and the first inductor L1may be connected at the position of the existing capacitor C0, and a parallel resonance circuit of another first capacitor C1and another first inductor L1may be connected at the position of the existing inductor L0.

According to such a structure, as illustrated in a graph curve of expressing a gain at the frequency of the gigahertz (GHz) frequency band, the orthogonal signal generator may operate to output a signal whose phase is in a +45° direction at a first frequency f1and a signal whose phase is in a −45° direction at a second frequency f2.

In addition, referring toFIGS.4C and4D, the orthogonal signal generated inside the orthogonal signal generator may operate to generate dual-band phase signals of −45° and +45° between output nodes P2based on the input of the input node P1in the dual-band phase shifter circuit to sequentially output the orthogonal phase signals in the output node P2.

Here, a parallel resonance circuit of the first capacitor C1and the first inductor L1may be connected at the position of the existing inductor L0, and a series resonance circuit of another first capacitor C1and another first inductor L1may be connected at the position of the existing capacitor C0.

According to such a structure, as illustrated by a graph curve of expressing a gain at the frequency of the gigahertz (GHz) frequency band, the orthogonal signal generator may operate to output a signal whose phase is in a −45° direction at the first frequency f1and a signal whose phase is in a +45° direction at the second frequency f2.

FIG.5is a circuit diagram of a polyphase filter with a 1.5-stage structure that may be adopted in the dual-band phase shifter according to one embodiment of the present disclosure.

As illustrated inFIG.5, the polyphase filter with the 1.5-stage structure of the present embodiment may include first to fourth capacitors C1to C4, first to fourth inductors L1to L4, first to fourth resistors R1to R4, and a combination relationship thereof.

In more detail, in the circuit structure of the polyphase filter, a first terminal of the first capacitor C1, a first terminal of the first inductor L1and a first terminal of the first resistor R1are commonly connected to a first input Ip. A second terminal of the first resistor R1, a second terminal of the second capacitor C2and a second terminal of the second inductor L2are commonly connected to a first output OIp.

A first terminal of the third inductor L3, a first terminal of the third capacitor C3and a first terminal of the fourth resistor R4are commonly connected to a second input In. Furthermore, a second terminal of the fourth resistor R4, a second terminal of the fourth inductor L4, and a second terminal of the fourth capacitor C4are commonly connected to a second output OIn.

A second terminal of the first capacitor C1, a second terminal of the third inductor L3, and a second terminal of the third resistor R3are commonly connected to a third output OQp. A first terminal of the third resistor R3is commonly connected to a first terminal of the second inductor L2and a first terminal of the fourth capacitor C4.

A second terminal of the first inductor L1, the second terminal of the third capacitor C3, and the second terminal of the second resistor R2are commonly connected to a fourth output OQn. A first terminal of the second resistor R2is commonly connected to a first terminal of the second capacitor C2and a first terminal of the fourth inductor L4.

When each value is optimized at a center frequency of 25 GHz in the polyphase filter described above, values of inductances L of each inductor, capacitances C of each capacitor, and resistance R of each resistor can be obtained.

FIGS.6and7are graphs illustrating results of simulating gains and phase changes for each output using the values realized in the polyphase filter ofFIG.5.FIG.8is a graph illustrating a result of simulating a phase difference and a gain error between I/Q signals in the polyphase filter ofFIG.5.

As can be seen fromFIGS.6and7, as a result of the simulation, it can be seen that each of the outputs of dB(S(5,1)), dB(S(4,1)), dB(S(3,1)) and dB(S(2,1)) operates normally in a band of 22 GHz to 31 GHz.

In addition, as can be seen fromFIG.8, it can be seen that a phase (phase_1) difference and a gain (gain_1) error between the I/Q signals are in a normal range.

FIG.9is a circuit diagram of a dual-band polyphase filter that may be adopted in the dual-band phase shifter according to another embodiment of the present disclosure.

As illustrated inFIG.9, the polyphase filter that may be adopted in the dual-band phase shifter of the present embodiment may include first to eighth capacitors C11, C12, C21, C22, C31, C32, C41and C42, first to eighth inductors L11, L12, L21, L22, L31, L32, L41and L42, and first to fourth resistors R1to R4, and a combination relationship thereof.

When describing the combination relationship between the components of the polyphase filter in more detail, based on the polyphase filter ofFIG.5, the first capacitor C1ofFIG.5is changed to a series resonance circuit of the first capacitor C11and the second inductor L12, the first inductor L1ofFIG.5is changed to a parallel resonance circuit of the second capacitor C12and the first inductor L11, the second capacitor C2ofFIG.5is changed to a series resonance circuit of the third capacitor C21and the fourth inductor L22, and the second inductor L2ofFIG.5is changed to a parallel resonance circuit of the fourth capacitor C22and the third inductor L21.

In addition, based on the polyphase filter ofFIG.5, the third inductor L3ofFIG.5is changed to a parallel resonance circuit of the sixth capacitor C32and the fifth inductor L31, the third capacitor C3ofFIG.5is changed to a series resonance circuit of the fifth capacitor C31and the sixth inductor L32, the fourth inductor L4ofFIG.5is changed to a parallel resonance circuit of the eighth capacitor C42and the seventh inductor L41, and the fourth capacitor C4ofFIG.5is changed to a series resonance circuit of the seventh capacitor C41and the eighth inductor L42.

In addition, the combination relationship between a first input Ipand a second input In, the resistors R1to R4and first to fourth outputs OIp, OIn, OQpand OQnmay be substantially the same as that of the polyphase filter ofFIG.5.

FIGS.10and11are graphs illustrating results of simulating gains and phase changes for each output using the values obtained in the polyphase filter ofFIG.9.FIG.12is a graph illustrating a result of simulating a phase difference and a gain error between I/Q signals in the full frequency band of the polyphase filter ofFIG.9.

As can be seen fromFIGS.10and11, as a result of the simulation, it can be seen that each of the outputs of dB(S(5,1)), dB(S(4,1)), dB(S(3,1)) and dB(S(2,1)) operates normally in two bands, i.e., a low frequency band of 8 GHz to 11 GHz and a high frequency band of 21 GHz to 29 GHz, based on a center frequency of 15 GHz.

In addition, as can be seen from the simulation results ofFIG.12, it can be seen that, in the full frequency band, the phase (phase_1) difference and the gain (gain_1) error between the I/Q signals are in a normal range.

Meanwhile, the structure according to the present embodiment has a disadvantage in that the phases of the I/Q signals operating in the dual bands which are two frequency bands, are changed. However, since it is known that the phase varies depending on the band used by the signal processing stage, it can be easily corrected via a digital stage or a lookup table (LUT).

As described above, the present embodiment can provide a dual-band phase shifter that is applicable to a multi-channel RFIC of a phase array system.

FIG.13is a graph illustrating a result of simulating whether a phase shifter of the comparative example with the existing structure including the analog differential adder and a matching circuit ofFIG.1is shifted to a 360-degree phase.FIG.14is a graph illustrating a simulation a result of simulating whether the analog differential adder and a matching circuit is coupled to the phase shifter of the present embodiment including the polyphase filter ofFIG.9and the phase shifter is shifted to a 360-degree phase.

As can be seen from the simulation results of the comparative example and the present embodiment ofFIGS.13and14, it may be confirmed that 360-degree phase characteristics are maintained in the dual-band phase shifter of the present embodiment.

The operations of the method according to the exemplary embodiment of the present disclosure can be implemented as a computer readable program or code in a computer readable recording medium. The computer readable recording medium may include all kinds of recording apparatus for storing data which can be read by a computer system. Furthermore, the computer readable recording medium may store and execute programs or codes which can be distributed in computer systems connected through a network and read through computers in a distributed manner.

The computer readable recording medium may include a hardware apparatus which is specifically configured to store and execute a program command, such as a ROM, RAM or flash memory. The program command may include not only machine language codes created by a compiler, but also high-level language codes which can be executed by a computer using an interpreter.

Although some aspects of the present disclosure have been described in the context of the apparatus, the aspects may indicate the corresponding descriptions according to the method, and the blocks or apparatus may correspond to the steps of the method or the features of the steps. Similarly, the aspects described in the context of the method may be expressed as the features of the corresponding blocks or items or the corresponding apparatus. Some or all of the steps of the method may be executed by (or using) a hardware apparatus such as a microprocessor, a programmable computer or an electronic circuit. In some embodiments, one or more of the most important steps of the method may be executed by such an apparatus.

In some exemplary embodiments, a programmable logic device such as a field-programmable gate array may be used to perform some or all of functions of the methods described herein. In some exemplary embodiments, the field-programmable gate array may be operated with a microprocessor to perform one of the methods described herein. In general, the methods are preferably performed by a certain hardware device.

The description of the disclosure is merely exemplary in nature and, thus, variations that do not depart from the substance of the disclosure are intended to be within the scope of the disclosure. Such variations are not to be regarded as a departure from the spirit and scope of the disclosure. Thus, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope as defined by the following claims.