Patent ID: 12188151

DETAILED DESCRIPTION

To begin with, a relevant technology will be described only for understanding the embodiments of the present disclosure.

In a SiC wafer, although it has been proposed to form a damage layer on a other surface of a base wafer opposite to a surface on which an epitaxial layer is formed in order to suppress the warp of the SiC wafer by the Twyman effect, the damage layer is formed by increasing the surface roughness of the other surface of the base wafer, that is, by forming unevenness on the other surface of the base wafer.

However, if the surface roughness of the other surface of the base wafer is increased, foreign matter tends to adhere to the other surface of the base wafer. Further, the foreign matter is likely to scatter in subsequent processing steps after the SiC wafer is formed, and there is a possibility that the yield will decrease.

The present disclosure provides a SiC wafer and a method for manufacturing the same, in which the amount of warp is controlled and adhesion of foreign matter is suppressed.

According to an aspect of the present disclosure, a silicon carbide wafer includes: a base wafer that is made of SiC, doped with an n-type impurity, and has a first main surface and a second main surface opposite to the first main surface; and an epitaxial layer that is made of SiC, doped with an n-type impurity, and arranged on the first main surface of the base wafer. A thickness of the base wafer is referred to as t1, and a thickness of the epitaxial layer is referred to as t2. An average impurity concentration of the base wafer is referred to as n1, and an average impurity concentration of the epitaxial layer is referred to as n2. A ratio of the thickness t2 of the epitaxial layer to the thickness t1 of the base wafer is referred to as a thickness ratio t2/t1, and a ratio of the average impurity concentration n2 of the epitaxial layer to the average impurity concentration n1 of the base wafer is referred to as an average impurity concentration ratio n2/n1. The base wafer and the epitaxial layer are configured so that the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 satisfy a mathematical formula 1.
−0.0178<0.012+(t2/t1)×0.057−(n2/n1)×0.029−{(t2/t1)−0.273}×{(n2/n1)−0.685}×0.108<0.0178  [Formula 1]

According to such a configuration, since the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 are adjusted, it is possible to suppress the amount of warp, that is, the absolute value of a curvature of the SiC wafer from being excessively increased. As a result, transfer errors and manufacturing defects can be suppressed. Moreover, since it is not necessary to increase the surface roughness of the SiC wafer, adhesion of foreign matter can be suppressed.

According to another aspect of the present disclosure, a method for manufacturing a SiC wafer comprising: preparing a base wafer that is made of SiC, has a first main surface and a second main surface opposite to the first main surface, and is doped with an n-type impurity; and arranging an epitaxial layer on the first main surface of the base wafer, the epitaxial layer being made of SiC and doped with an n-type impurity. In the arranging of the epitaxial layer, the epitaxial layer is arranged so as to satisfy a mathematical formula 2.
−−0.0178<0.012+(t2/t1)×0.057−(n2/n1)×0.029−{(t2/t1)−0.273}×{(n2/n1)−0.685}×0.108<0.0178  [Formula 2]

In the mathematical formula 2, t1 represents a thickness of the base wafer, t2 represents a thickness of the epitaxial layer, t2/t1 represents a ratio of the thickness t2 of the epitaxial layer to the thickness t1 of the base wafer. Also, n1 represents an average impurity concentration of the base wafer, n2 represents an average impurity concentration of the epitaxial layer, and n2/n1 represents a ratio of the average impurity concentration n2 of the epitaxial layer to the average impurity concentration n1 of the base wafer.

According to such a method, since the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 are adjusted, the SiC wafer in which the amount of warp, that is, the absolute value of the curvature is suppressed from being excessively increased can be manufactured. Therefore, it is possible to suppress occurrences of transfer errors in subsequent processing steps, manufacturing defects, and the like. Moreover, since it is not necessary to increase the surface roughness of the SiC wafer, adhesion of foreign matter can be suppressed.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the embodiment described hereinafter, the same or equivalent parts are denoted by the same reference numerals.

First Embodiment

A first embodiment will be described with reference to the drawings. A silicon carbide (SiC) wafer of the present embodiment is, for example, used to form a SiC semiconductor device having a semiconductor element such as a metal oxide semiconductor field effect transistor (MOSFET), or an insulated gate bipolar transistor (IGBT). First, a configuration of the SiC wafer of the present embodiment will be described.

As shown inFIG.1, a SiC wafer10of the present embodiment includes a base wafer20made of SiC and an epitaxial layer30made of SiC. The epitaxial layer30is arranged on the base wafer20.

The base wafer20of the present embodiment is made of a 4H-type SiC single crystal wafer having a first main surface20aand a second main surface20b, and has a size of, for example, 6 inches. Further, the base wafer20of the present embodiment is an n-type by being doped with an n-type impurity such as nitrogen. The epitaxial layer30is arranged on the first main surface20aof the base wafer20and is an n-type by being doped with an n-type impurity such as nitrogen. The thickness and the impurity concentration of the epitaxial layer30are adjusted based on the thickness and the impurity concentration of the base wafer20, although the details will be described later. Hereinafter, a surface of the SiC wafer10on the epitaxial layer30side is referred to as one surface10aof the SiC wafer10, and an opposite surface of the SiC wafer10on the base wafer20side is referred to as the other surface10bof the SiC wafer10. The other surface10bof the SiC wafer10is provided by the second main surface20bof the base wafer20.

The SiC wafer10of the present embodiment is configured such that a curvature p is within a range described hereinafter. First, as shown inFIGS.2A and2B, when the SiC wafer10is placed on a plane S so that the other surface10bof the SiC wafer10faces the plane S, the difference in height between the highest position and the lowest position of the one surface10awith respect to the plane S is referred to as the amount of warp h. Then, as shown inFIG.2A, a state in which the one surface10aof the SiC wafer10has the highest position substantially in the center is referred to as an upwardly convex state. Further, as shown inFIG.2B, a state in which the one surface10aof the SiC wafer10has the highest position at an outer end is referred to as a downwardly convex state.

Further, as shown inFIGS.2A and2B, a virtual circle VS including the one surface10aof the SiC wafer10as an arc is defined. In this case, the amount of warp h is expressed as h=r×(1−cos (θ/2)), in which r is the radius of the virtual circle VS, and θ is the central angle defined by the one surface10a, that is, by the arc provided by the one surface10aof the SiC wafer10included in the virtual circle VS.

Further, the diameter of SiC wafer10, that is, the length of the arc provided by the one surface10aof the SiC wafer10included in the virtual circle VS is defined as L. Thus, the diameter L is expressed as L=r×θ.

In this case, the curvature ρ is provided by the reciprocal of the radius r of the virtual circle VS whose arc is the diameter of the SiC wafer10, and is expressed as ρ=1/r. When semiconductor chips are manufactured by using the SiC wafer10as described above, it is desirable that the amount of warp h of the SiC wafer10is 50 μm or less in order to reduce the transfer errors, manufacturing defects, and the like. Therefore, it is desired that the curvature ρ be in a range from −0.0178 to 0.0178 (1/m). In other words, it is desired that the curvature ρ have an absolute value of 0.0178 (1/m) or less. The curvature ρ takes a positive value when the SiC wafer10is warped in the upwardly convex state. Further, the curvature ρ takes a negative value when the SiC wafer10is warped in the downwardly convex state. Also, the curvature ρ does not change even if the diameter (that is, inches) of the SiC wafer10is changed.

The inventors of the present disclosure conducted intensive studies to make the SiC wafer10having the curvature ρ within a range of −0.0178 to 0.0178 (1/m), and obtained the following results. Hereinafter, as shown inFIG.1, the thickness of the base wafer20is referred to as t1, the thickness of the epitaxial layer30is referred to as t2, the average impurity concentration of the base wafer20is referred to as n1, and the average impurity concentration of the epitaxial layer30is referred to as n2. The thickness t1 of the base wafer20can also be referred to as a dimension of the base wafer20in a layered direction in which the base wafer20and the epitaxial layer30are layered. Similarly, the thickness t2 of the epitaxial layer30can also be referred to as a dimension of the epitaxial layer30in the layering direction of the base wafer20and the epitaxial layer30. In the following, the ratio of the thickness t2 of the epitaxial layer30to the thickness t1 of the base wafer20is referred to as a thickness ratio t2/t1, and the ratio of the average impurity concentration n2 of the epitaxial layer30to the average impurity concentration n1 of the base wafer20is referred to as an average impurity concentration ratio n2/n1.

First, in a configuration where the epitaxial layer30is grown on the base wafer20, as shown inFIG.3, it is appreciated that the curvature ρ increases as the thickness ratio t2/t1 increases. That is, it is appreciated that the curvature ρ increases as the thickness of the epitaxial layer30increases. Note thatFIG.3shows the results when the average impurity concentration ratio n2/n1 is constant at 0.001.

Moreover, in the configuration where the epitaxial layer30is grown on the base wafer20, as shown inFIG.4, it is appreciated that the curvature ρ decreases as the average impurity concentration ratio n2/n1 increases. That is, it is appreciated that the curvature ρ decreases as the average impurity concentration of the epitaxial layer30increases. Note thatFIG.4shows the results when the thickness ratio t2/t1 is 0.56 to 0.59.

In addition, the inventors of the present disclosure measured the curvature ρ while changing the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1, and obtained the results shown inFIG.5. Then, the inventors of the present disclosure performed a primary regression analysis based on the results shown inFIG.5, and found that the curvature ρ in the range of −0.0178 to 0.0178 (1/m) was achieved by the followings. That is, the inventors of the present disclosure have found that the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 should be adjusted so as to satisfy the following mathematical formula 3.
−0.0178<0.012+(t2/t1)×0.057−(n2/n1)×0.029−{(t2/t1)−0.273}×{(n2/n1)−0.685}×0.108<0.0178  [Formula 3]

Therefore, in the present embodiment, the thickness ratio t2/t1 and the average impurity concentration ration n2/n1 of the SiC wafer10are adjusted based on the mathematical formula 3 so that the curvature ρ is in the range of −0.0178 to 0.0178 (1/m). That is, the thickness t2 and the average impurity concentration n2 of the epitaxial layer30are adjusted based on the thickness t1 and the average impurity concentration n1 of the base wafer20, so that the curvature ρ is in the range of −0.0178 to 0.0178 (1/m).

In order to set the curvature ρ in the range of −0.0178 to 0.0178 (1/m), the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 are adjusted in the hatched range inFIG.6. Further, the SiC wafers10were produced by changing the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1, and the curvatures p were measured as the measurement curvatures. Also, by using those thickness ratios t2/t1 and those average impurity concentration ratios n2/n1, the curvatures p were calculated based on the mathematical formula 3.FIG.7shows the relationship between the measurement curvature ρ and the curvature ρ derived from the mathematical formula 3. As shown inFIG.7, it is appreciated that the measured curvature ρ and the curvature ρ derived from the mathematical formula 3 are substantially the same.

The configuration of the SiC wafer10of the present embodiment has been described hereinabove. Next, a method for manufacturing a semiconductor chip including a method of manufacturing the SiC wafer10will be described.

First, as shown inFIG.8A, a base wafer20having a first main surface20aand a second main surface20band in the form of a bulk wafer is prepared. The base wafer20is made of SiC and is an n-type by being doped with an n-type impurity to have a predetermined impurity concentration. The thickness of the base wafer20is arbitrary, but is for example about 325 μm to 525 μm. In the base wafer20of the present embodiment, the first main surface20ais a Si surface and the second main surface20bis a C surface. Further, since the base wafer20is irradiated with a laser beam L from the second main surface20bside in the process ofFIG.8Edescribed later, the second main surface20bis mirror-finished by mirror finishing or the like. The mirror finishing is performed, for example, by polishing using a grinder or polishing such as chemical mechanical polishing (CMP).

In addition, the base wafer20of the present embodiment has a c-axis21(that is, <0001> direction) extending from the first main surface20ato the second main surface20band a c-plane22(that is, {0001} plane) perpendicular to the c-axis21. Further, in the present embodiment, the c-axis21is inclined with respect to a perpendicular line23to the first main surface20a, and the c-plane22and the first main surface20adefine a predetermined off angle α therebetween. The off angle α is, for example, approximately 4°. However, the off angle α is not limited to this example, and is appropriately set according to semiconductor elements to be manufactured. For example, the off angle α is appropriately set in a range of less than 10°.

Further, the base wafer20of the present embodiment can also be prepared by reusing a recycle wafer80produced in the process ofFIG.8F, which will be described later. Therefore, if necessary, a protective film made of an oxide film or the like may be formed on the second main surface20bof the SiC wafer10or the like. InFIG.8Band subsequent figures, the illustrations of the c-axis21, the c-plane22, and the perpendicular line23are omitted for the ease of understanding in the figures.

Next, as shown inFIG.8B, an epitaxial layer30is formed on the first main surface20aof the base wafer20, which is the n-type as being doped with an n-type impurity. Thus, the SiC wafer10having the one surface10aand the other surface10bis produced. In the present embodiment, by adjusting the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 based on the mathematical formula 3 described above, the SiC wafer10having the curvature ρ in the range of −0.0178 to 0.0178 (1/m) is provided.

As described above, the SiC wafer10shown inFIG.1is produced. In this case, since the curvature ρ is in the range of −0.0178 to 0.0178 (1/m), it is possible to suppress the occurrence of transfer errors during subsequent transfer and the occurrence of manufacturing defects during manufacturing. Further, in the present embodiment, the curvature ρ, that is, the amount of warp h is adjusted by adjusting the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1. Therefore, it is not necessary to increase the surface roughness of the other surface10bof the SiC wafer10. Therefore, it is possible to suppress foreign matter from adhering to the other surface10bof the SiC wafer10, and to suppress the decrease in yield in subsequent processing steps.

The SiC wafer10produced as described above has a chip formation region RA, in which semiconductor elements are to be formed, on the one surface10aside. In addition, the epitaxial layer30provides a part in which a first surface-side element constituent portion42constituting a semiconductor element is formed. The first surface-side element constituent portion42, for example, includes a diffusion layer, and will be described later.

Next, as shown inFIG.8C, general semiconductor manufacturing processes are performed. Namely, processes for forming the first surface-side element constituent portion42of the semiconductor element, such as a gate electrode41, a diffusion layer (not shown), a surface electrode (not shown), a wiring pattern (not shown), or a passivation film (not shown), are formed in each chip formation region RA. It should be noted that the semiconductor element used herein may have various configurations, and may be a power device, for example. Thereafter, a surface protection film made of a resist or the like is formed on the one surface10aside of the SiC wafer10, if necessary.

Subsequently, as shown inFIG.8D, a holding member50is arranged on the one surface10aside of the SiC wafer10. As the holding member50, for example, a dicing tape having a base material51and an adhesive52is used. The base material51is made of a material that does not easily warp during the manufacturing process. For example, the base material51is made of glass, a silicon substrate, ceramics, or the like. The adhesive52is made of a material whose adhesive strength is changeable. For example, the adhesive52is made of an adhesive whose adhesive force changes depending on temperature or light. In this case, the adhesive52is made of, for example, an ultraviolet curable resin, wax, double-sided tape, or the like. Note that the adhesive52is made of a material that maintains its adhesive force even when a second surface-side element constituent portion44ofFIG.8G, which will be described later, is formed.

Next, as shown inFIG.8E, the laser beam L is applied in a normal direction to the other surface10bof the SiC wafer10to form a modified layer11at a predetermined depth H from the other surface10bof the SiC wafer10along a planar direction of the SiC wafer10. In the present embodiment, the predetermined depth H for forming the modified layer11is set according to the ease of handling of a chip-constituent wafer70, which will be described later, a breakdown voltage of the semiconductor chip100, which will be described later, and the like. In the present embodiment, for example, the modified layer11is formed at the boundary between the base wafer20and the epitaxial layer30. Here, the depth corresponds to the dimension measured from the other surface10bin the direction from the other surface10btoward the one surface10a, and also corresponds to the dimension in the depth direction, which is the direction normal to the other surface10b.

Here, the process of forming the modified layer11will be described. When the modified layer11is formed, first, a laser apparatus including a laser beam source, a mirror, a condensing lens (i.e., a condensing optical system), a displaceable stage, and the like is prepared. The laser light source oscillates the laser beam L, and the mirror is arranged to change the direction of the optical axis (that is, the optical path) of the laser beam L. The condensing lens is provided to condense the laser beam L. To form the modified layer11, the SiC wafer10is then placed on the stage, and the laser beam L is applied from the other surface10bside of the SiC wafer10. In this case, the position of the sage and the like are adjusted so that the focal point of the laser beam L is moved relative to the SiC wafer10along the planar direction of the SiC wafer10while keeping the focal point at the predetermined depth H.

Thus, inside the SiC wafer10, SiC is separated into amorphous Si and amorphous C by being irradiated with the laser beam L, and the amorphous C after separation absorbs the laser beam L to form an altered layer. Also, cracks propagating from the altered layer along the c-plane22is formed. As a result, the modified layer11composed of the altered layer and the cracks is formed inside the SiC wafer10.

In the present embodiment, for example, to form the modified layer11, the laser beam L is applied with the laser output of 2.0 W, the feed rate of 785 mm/s, and the processing time of about 15 minutes. However, these conditions are only an example, and the inventors of the present disclosure have confirmed that the modified layer11can be appropriately formed by adjusting respective conditions even when the laser output is higher or lower than 2.0 W.

Next, as shown inFIG.8F, an auxiliary member60is arranged on the other surface10bside of the SiC wafer10. For example, the auxiliary member60includes a base material61and an adhesive62whose adhesive force is changeable, similarly to the holding member50. In this case, the base material61of the auxiliary member60is made of, for example, glass, a silicon substrate, ceramics, or the like. Also, the adhesive62of the auxiliary member60is made of, for example, an ultraviolet curable resin, wax, double-sided tape, or the like. Then, the holding member50and the auxiliary member60are held and a tensile force or the like is applied in the thickness direction of the SiC wafer10, so that the SiC wafer10is separated into the chip-constituent wafer70and the recycle wafer80at the modified layer11as a boundary, that is, a starting point of separation.

Hereinafter, the surface of the chip-constituent wafer70on which the first surface-side element constituent portion42is formed is referred to as a first surface70a, and the surface of the chip-constituent wafer70from which the recycle wafer80has been separated is referred to as a second surface70b. Also, the surface of the recycle wafer80from which the chip-constituent wafer70has been separated is referred to as the one surface80a. Further, inFIG.8Fand subsequent figures, illustrations of the modified layer11remaining on the second surface70bof the chip-constituent wafer70and on the one surface80aof the recycle wafer80are omitted as appropriate.

Thereafter, as shown inFIG.8G, general semiconductor manufacturing processes are performed. For example, a process of forming the second surface-side element constituent portion44of the semiconductor element on the second surface70bof the chip-constituent wafer70is performed. The second surface-side element constituent portion44is a portion constituting the semiconductor element on the second surface70bside, and includes, for example, a metal film43forming a back surface electrode.

Before the process of forming the second surface-side element constituent portion44, a process of flattening the second surface70bof the chip-constituent wafer70by a chemical mechanical polishing (CMP) method or the like may be performed as necessary.FIG.8Gshows the chip-constituent wafer70in which the second surface70bof the chip-constituent wafer70has been flattened. After performing the process of forming the second surface-side element constituent portion44, a heat treatment such as a laser annealing or the like may be performed in order to make an ohmic contact between the metal film43and the second surface70bof the chip-constituent wafer70as necessary.

Thereafter, as shown inFIG.8H, a support member90is arranged on the second surface70bside of the chip-constituent wafer70, that is, on the metal film43side. The support member90may be made of, for example, a dicing tape or the like. In the present embodiment, the support member90includes a base material91and an adhesive92whose adhesive force is changeable, similar to the holding member50. In the case where the support member90includes the base material91and the adhesive92, the base material91is made of, for example, glass, a silicon substrate, or ceramics, and the adhesive92is made of, for example, an ultraviolet curable resin, wax, or double-sided tape.

Next, as shown inFIG.8I, the adhesive force of the adhesive52of the holding member50is weakened, and the holding member50attached to the first surface70aof the chip-constituent wafer70is peeled off. For example, in a case where the adhesive52is made of an ultraviolet curable resin, the holding member50is peeled off by applying ultraviolet rays.

Subsequently, as shown inFIG.8J, the chip-constituent wafer70is diced into pieces, that is, into chip units by a dicing saw, laser dicing, or the like. Thus, respective semiconductor chips100are produced. In the present embodiment, in this case, the dicing depth is adjusted so that the base material91of the support member90remains connected without being cut while the chip-constituent wafer70is divided into chip units.

Although the subsequent processes are not shown, the support member90is expanded to widen the intervals between the semiconductor chips100at the dicing cut portions. Thereafter, the adhesive force of the adhesive92is weakened by a heat treatment or irradiation with light, and the semiconductor chips100are picked up. In this way, the semiconductor chips100are manufactured.

The recycle wafer80produced in the process shown inFIG.8Fis reused as the base wafer20for the processes afterFIG.8A. Thus, the base wafer20can be used multiple times to produce the semiconductor chips100. In this case, the one surface80aof the recycled wafer80(that is, the base wafer20) is preferably polished by a polishing apparatus, dry etching, or the like so that the one surface80ais flat and the modified layer11does not remain.

According to the present embodiment described above, the SiC wafer10is adjusted so that the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 satisfy the mathematical formula 3 described above. Therefore, it is possible to suppress the amount of warp h (that is, the absolute value of the curvature ρ) from being excessively large, and it is possible to suppress the occurrence of transfer errors, manufacturing defects, and the like.

In the present embodiment, the amount of warp h (that is, the curvature ρ) is adjusted by adjusting the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 of the SiC wafer10. As such, it is not necessary to increase the surface roughness of the other surface10bof the SiC wafer10. As a result, it is possible to suppress foreign matter from adhering to the other surface10bof the SiC wafer10, and to suppress the decrease in yield in subsequent processing steps.

Second Embodiment

A second embodiment of the present disclosure will be described hereinafter. In the present embodiment, the impurity concentration of the epitaxial layer30is adjusted with respect to the first embodiment. The other configurations are the same as those of the first embodiment, and therefore descriptions of the same configurations will not be repeated hereinafter.

In the SiC wafer10of the present embodiment, as shown inFIG.9, the epitaxial layer30is composed of a first epitaxial layer31and a second epitaxial layer32layered on top of another. Hereinafter, the thickness of the first epitaxial layer31is referred to as t2a, and the average impurity concentration of the first epitaxial layer31is referred to as n2a. Also, the thickness of the second epitaxial layer32is referred to as t2b and the average impurity concentration of the second epitaxial layer32is referred to as n2b.

In the present embodiment, the average impurity concentration n2a of the first epitaxial layer31is higher than the average impurity concentration n1 of the base wafer20, and the average impurity concentration n2b of the second epitaxial layer32is lower than the average impurity concentration n1 of the base wafer20. Note that the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 of the base wafer20and the epitaxial layer30are adjusted as a whole so that the curvature ρ of the SiC wafer10is in the range of −0.0178 to 0.0178 (1/m). For example, when the thickness t1 of the base wafer20is 210 μm and the average impurity concentration n1 of the base wafer20is 5×1018cm−3, the first epitaxial layer31and the second epitaxial layer32are configured as follows. That is, the first epitaxial layer31is configured so that the thickness t2a is 40 μm and the average impurity concentration n2a is 2×1019cm−3, and the second epitaxial layer32is configured so that the thickness t2b is 100 μm and the average impurity concentration n2b is 5×1014cm−3. Such an epitaxial layer30is formed by growing the first epitaxial layer31while doping the impurity at a predetermined amount, and then growing the second epitaxial layer32while doping the impurity at a reduced amount.

According to the present embodiment described above, the SiC wafer10is adjusted so that the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 satisfy the mathematical formula 3 described above. Therefore, the similar effects to those of the first embodiment can be obtained.

(1) In the present embodiment, the epitaxial layer30includes the first epitaxial layer31having the average impurity concentration n2a higher than the average impurity concentration n1 of the base wafer20and the second epitaxial layer32having the average impurity concentration n2b lower than the average impurity concentration n1 of the base wafer20. The second epitaxial layer32is layered on the first epitaxial layer31. Therefore, in forming the semiconductor chips100, the semiconductor chips100having desired characteristics can be easily formed. For example, when a MOSFET is formed so that the drain region includes the first epitaxial layer31and the drift layer includes the second epitaxial layer32, the breakdown voltage can be easily increased.

Modifications of Second Embodiment

The second embodiment may be modified in various ways. For example, as a modification of the second embodiment, as shown inFIG.10, the epitaxial layer30may be configured so that the impurity concentration of the second epitaxial layer32gradually decreases as a function of distance from the portion adjacent to the first epitaxial layer31, in place of the configuration in which the impurity concentration sharply changes at the boundary between the first epitaxial layer31and the second epitaxial layer32. Such an epitaxial layer30is formed by gradually reducing the amount of impurity doped at the boundary between the first epitaxial layer31and the second epitaxial layer32when growing the epitaxial layer30. According to such a configuration, since the impurity concentration in the second epitaxial layer32gradually decreases, introduction of defects into the epitaxial layer30can be suppressed, as compared to the configuration in which the impurity concentration sharply changes at the boundary portion between the first epitaxial layer31and the second epitaxial layer32.

Further, as long as the thickness ratio t2/t1 and the average impurity concentration ratio n2/n1 satisfy the mathematical formula 3, the magnitude relationship of the average impurity concentration n2a of the first epitaxial layer31and the average impurity concentration n2b of the second epitaxial layer32can be changed as appropriate. For example, both the average impurity concentration n2a of the first epitaxial layer31and the average impurity concentration n2b of the second epitaxial layer32may be higher than the average impurity concentration n1 of the base wafer20.

In the second embodiment described above, the epitaxial layer30exemplarily have the two layered structure including the first epitaxial layer31and the second epitaxial layer32. However, the epitaxial layer30may have multi-layered structure including three or more epitaxial layers.

Other Embodiments

Although the present disclosure has been described in accordance with the embodiments and examples, it is understood that the present disclosure is not limited to such embodiments and examples. The present disclosure encompasses various modifications and variations within the scope of equivalents. In addition, various combinations and configurations, as well as other combinations and configurations that include only one element, more, or less of the embodiments and examples are within the scope and spirit of the present disclosure.

In each of the embodiments described above, it is exemplified that the base wafer20is made of a 4H-type, 6-inch SiC single crystal wafer. As other examples, the base wafer20may be a 3C-type or 6H-type with the size of 2 inches or 8 inches.