Patent ID: 12191267

DESCRIPTION

Overview

This disclosure describes a nanowire bonding interconnect for fine-pitch microelectronics. In an implementation, vertical nanowire pins or posts are created on conductive pads of a microelectronics device, or on an entire surface of a chip, wafer, or device to provide a thin debris-tolerant bonding layer that can form interconnects between conductive pads that are less than 5 μm across and laid out at fine-pitch, even in the presence of trace amounts of tiny debris particles. The nanowire bonding interface described herein can be used under ideal conditions, but can also be used in some circumstances when conductive pads or leads to be bonded together are not ideal candidates for conventional direct bonding, due to lesser quality of the conductive surfaces being bonded, variance in the flatness needed for direct bonding, or imperfect surface preparation for conventional direct bonding techniques.

Nanowires with a diameter less than 200 nanometers (nm) and a horizontal spacing from each other of 1 μm or less enable conductive contact or direct metal-to-metal bonding between pads that have dimensions under 5 μm and comparable line and pitch (spacing) distances. The small diameter of the nanowires at 200 nm or less enables conductive pads much smaller than 5 μm to still have at least 3-4 nanowires100on their surface. The nanowires may be grown from a nanoporous medium with a height between approximately 200-1000 nanometers, for example, and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads under applied pressure, thereby providing a desirable compression of the nanowires and contact pressure for making electrical interconnects and for direct metal-to-metal bonding of the nanowires to the opposing conductive pads or vias. The nanowire bonding interconnects may be used to join surfaces with or without tinning, solders, or adhesives, depending on implementation. Some embodiments use flowable joining materials, solder, or an adhesive to join devices, dies, or surfaces on either side of the vertically disposed nanowires.

The nanowire bonding layer can be implemented on conductive pads only, or can be implemented on an entire surface of a semiconductor wafer, silicon substrate, semiconductor die, chip, package, assembly, dielectric, or even just on a surface that has electrical contacts. The nanowire bonding layer can also be embodied in a two-sided interposer that can bond chips and wafers on both sides of the two-sided interposer.

Techniques for forming the nanowire bonding interface are also described. An example method creates a nanoporous layer of a nonmetal, for example, on each conductive pad of a surface to be bonded. Nanowires are plated, deposited, or otherwise formed within the pores of the nanoporous layer, and then at least a part of the nanoporous layer may be removed, or recessed, to reveal a layer of bondable nanowire ends that may be less than 1 μm in height for direct metallic-bonding between opposing pads or between opposing vias, in one example process.

Dimensions of the nanowires for their diameter and height may be selected so that a pressure force needed to electrically interconnect two opposing pads and collapse the nanowires into a slightly compressed state is less than the yielding force of the same bulk materials used.

Example Bonding Interfaces

Dimensions of members and elements shown in the Figures are not to scale and not in proportion relative to each other, but are shown in a manner that aids in understanding the description of features.

FIG.1shows example nanowires100(“pins” or “posts”) making up an example nanowire bonding interface102. The nanowire bonding interface102may be used to make a microelectronics package104that includes a die-to-die, die-to-wafer, or wafer-to-wafer interface between two components of the microelectronic package104. The nanowires100are grown from a nanoporous medium106, for example made of a dielectric material, and may be formed or grown only on conductive pads108to be bonded, or may be formed across the entire surface to be bonded or joined. In an implementation, the nanowires100may be grown on conductive pads108on opposing surfaces to be bonded, and the nanowires100on each side bond to the conductive pads108and nanowires100on the opposing side of the bond.

The nanowires100can be made of copper, nickel, aluminum, silver, tungsten, alloy, or another suitable electrical conductor. The nanowires100can also be covered, coated, alloyed, or amalgamated with other metals, such as gold or other metals attractive for bonding, soldering, or making a multi-metal intermetallic bonding interface between conductors that are being joined into an interconnect.

In an implementation, formation of the nanowires100uses a nanoporous film or layer106. This nanoporous starting layer106can be made of porous silicon, oxidized alumina, silicon dioxide, ceramic, or a host of other materials, such as various dielectric materials. Moreover, the nanoporous starting layer106does not need to be porous from the outset. A suitable material is applied to the chip, wafer, or other surface, and the pores can be created by various techniques, such as electrochemical etching, chemical vapor deposition, sputtering, alkali corrosion, and many other processes for creating nanoporous films and surfaces.

In an implementation, the nanowires100are formed, plated, deposited, or grown in the pores of the nanoporous layer106. This formation process may include depositing a film of insulator material on the walls of the pores, in the event that the nanoporous layer106itself is conductive, or is semiconductive, as in the case of silicon. The nanowire formation process may also include cleaning the bottom of the pores, in order for the nanowires100being created to make electrical contact with the conductive pads underlying the nanoporous layer106. Once nanowires100of a desired vertical height are formed, the nanoporous layer106may be partially or completely removed, or recessed, providing “free” ends of the nanowires100for bonding with an opposing conductive pad108, or another opposing instance of the nanowire bonding interface102, on the opposing side of the bond. The nanowires100can be made any height or length, but a useful height in one example implementation is between approximately 200-1000 nanometers (e.g., up to 1 μm). The free ends of the nanowires100can make conductive contact via simple physical contact or by direct metal bonding of the ends to a conductive surface. Optionally a flowable joining material such as a solder may be used. In an implementation, the nanowires100can be held in contact with permanent adhesive that is placed elsewhere on the surfaces being joined away from the nanowires100, or in an implementation, the adhesive may be mixed in with the nanowires100in areas where the nanowires100make electrical contact with an opposing pad108. The nanowires100may bend, kink, and/or conform to small debris particles, leaving the remaining nanowires100to bond. The bonding nanowires100compress to a degree, provide some contact pressure against the opposing pad108for electrical contact and for direct metal bonding.

The completed nanowire bonding interface102, including both the nanowires100and the nanoporous layer106, may sometimes be only 1 μm or less in vertical height. This height, or a similar height, is enough to provide a more forgiving bonding approach when micro-particles are present than conventional surface-to-surface direct bonding, which uses ultra-flat and ultra-clean prepared bonding surfaces that are flatly planar.

In an implementation, since the nanowires100, on average, are only about 1 μm apart from each other horizontally, and sometimes much less, the nanowire bonding interface102can form interconnects at pitches much smaller than 5 μm.

FIG.2shows an implementation of the nanowire bonding interface102, in which nanowires100and a nanoporous layer106have been created on an entire surface200to be bonded. Coating an entire surface200with the nanowires100can sometimes be easier than the scenario ofFIG.1, in which the nanowires100are only grown on conductors108that make an electrical interconnect between conductive pads on opposing surfaces being joined. Coating an entire surface with the nanowires100, as inFIG.2, can also be used to make stronger cumulative bonds between two surfaces being joined, and can allow full physical bonding between surfaces, even with conductive pads that have some vertical misalignment with respect to their electrical interconnection.

FIG.3shows example nanowires100formed on pads108, on through-silicon-vias (TSVs)302, or on both pads108and TSVs302. Moreover, the TSVs302can also be outfitted with TSV pads304of their own, at the bonding interface. Nanowires100that do not connect vertically with an opposing pad108, TSV302, or opposing TSV pad304merely kink, bend, collapse, or break against an opposing surface of insulator or dielectric.

FIG.4shows an example implementation in which additional metal pads402that are not necessarily involved in circuitry or conductive connection can be designed onto a surface, horizontally between the conductive pads108in order to form a stronger vertical bond between surfaces being joined, using the nanowires100at both types of pads, pads108and pads402. The extra “dummy” pads402may also be used for heat-sinking, as the nanowires100are excellent conduits for flowing thermal energy generated by an integrated circuit of a die or heat generated within the larger microelectronics package104to a heat sink or to a dissipating structure.

FIG.5shows another implementation of an example bonding interface, in which the nanowires100are formed or “embedded”502in a surface500of the die itself, with no extra nanoporous layer106added in the nanowire100formation process. This can be accomplished by performing one of the nanopore-creating techniques described above, directly on the silicon semiconductor material or on a substrate material of a die, wafer, or other surface. A layer of adhesive504that has less height than the vertical height of the nanowires100may be added for joining the surfaces together. The joining may be made under pressure, so that the nanowires100can contact opposing pads108under some compression and contact pressure, while the adhesive504sets or hardens, making the contact between nanowires100and the contact pads108permanent.

FIG.6shows an implementation of the nanowire bonding interface102in which the nanoporous layer106used to form the nanowires100has been removed after the nanowires100are formed. This configuration allows the metal of the nanowires100to direct-bond with the same metal used in an opposing contact pad108, with no other material between conductive pads108besides the nanowires100, and air. Such direct metal bonds make the electrical interconnects between conductive pads108and can also provide the physical joining bond or mechanical connection between the two surfaces, such as between dies, or between die and wafer. In implementations where the nanoporous layer106is to be removed, a removable material is used. Removal of the nanoporous layer106depends on what substance is used as the nanoporous layer106. A masking material, or other etchable material can be used, such as an organic photoresist, silicon, or silicon dioxide, for example. Chemical, photo, or plasma etching may be used, depending on material, leaving the nanowires100freestanding, although only approximately a micron in height. Some forms of alumina (aluminum oxide) can be made removable. In this implementation, the joined package602has no remaining nanoporous layer106(FIG.1).

FIG.7shows the nanowires100before and after bonding with an opposing pad702. When the conductive pads108&702are small, such as less than 5 μm in length or diameter, then each pad108&702may still have 2-4 nanowires100, since the nanowires100may have a diameter of 200 nm, and a spacing of less than 1 μm, with the average height of the nanowires100approximately 1 μm or less. The two surfaces to be joined are brought together with enough pressure to press the nanowires100down to a common level of the lowest nanowires100in vertical height. The nanowires100may vary in height between 5-10%. When pressed, the nanowires100collapse slightly under the compression. This compressed state gives the nanowires100a measure of springlike contact pressure against the opposing conductive pad702. This implementation may be used with (FIG.8) or without an adhesive that makes the join permanent, including the compressed nanowires100. The compressed nanowires100with their contact pressure against the opposing conductive pad702may form their own direct metal-to-metal bonds with the opposing conductive pad702. The two surfaces may be held together by the direct bonds formed between the nanowires100and the opposing conductive pad702, or alternatively or in addition the surfaces may be held together by mechanical force or by an adhesive (as inFIG.8).

FIG.8shows the nanowires100before and after bonding with an opposing pad802. In this implementation, the joining is made permanent with an adhesive804. The height of the shortest nanowire100should be greater in height over the top dielectric surface of its die or wafer than the thickness of the dielectric or adhesive804layer on the opposing chip, in order for the nanowire100to reach the opposing conductive pad802. Overall, the average height of the nanowires100may be approximately 1 μm or less. The conductive pads108&802on each side of the join may be horizontally smaller than 5 μm in length or diameter, but each pad108&802still has at least several of the nanowires100, since the nanowires100can have diameters of 200 nm or less, and a spacing of 1 μm or less from each other. The two surfaces to be joined are brought together with pressure enough to compress the nanowires100down to a level of the lowest nanowires100in vertical height. The nanowires100may vary in height between 5-10%. When pressured, the nanowires100compress slightly under the pressure. This compressed state provides contact pressure for the nanowires100against the opposing conductive pad802. InFIG.8, the adhesive804is placed only between areas of both surfaces that do have nanowires100to be bonded. The adhesive804then sets or hardens under compression, fixing the nanowires100against the opposing conductive pad802in their compressed state. The nanowires100may make direct metal-to-metal bonds in their own right, with the opposing contact pad802, regardless of the adhesive804holding the surfaces together.

FIG.9shows the nanowires100before and after bonding with an opposing pad902, with both adhesive904and a flowable joining material such as solder906present. The height of the smallest nanowire100should be higher above than the top dielectric surface of its die or wafer than the height or thickness of the dielectric, adhesive904, or solder layer906on the opposing surface, in order to reach the opposing conductive pad902. The average height of the nanowires100may be approximately 1 μm or less. The conductive pads108&902on each side of the join may be smaller than 5 μm, but each pad108&902still has at least several of the nanowires100, since the nanowires100are small too, with diameters less than 200 nm, and a spacing of approximately 1 μm or less from each other.

The two surfaces to be joined are brought together with pressure enough to penetrate the nanowires100through the solder layer906or other flowable joining material and to compress the nanowires100down to a level of the tops of the lowest nanowires100in vertical height. If the temperature is to be raised as part of the specific process, then the solder906or other joining metal flows over the nanowires100, and optionally over the pad108beneath the nanowires100. The nanowires100may vary in height between 5-10%. When pressured, the nanowires100compress slightly under the pressure. This compressed state provides contact pressure for the nanowires100against the opposing conductive pad902. The adhesive904may be placed only between areas of both surfaces that do have nanowires100to be bonded. The adhesive904then sets or hardens under compression, fixing the nanowires100against the opposing conductive pad902in their compressed state.

The nanowires100may make direct metal-to-metal bonds in their own right, with the opposing contact pad902, regardless of the adhesive904holding the surfaces together. The compressed nanowires100and their contact pressure against the opposing conductive pad902may be made solid with the solder906, or with a nickel-solder interface, when the solder906or other flowable joining material is mixed with the nanowires100, or placed as a layer on top of the nanowires100, or placed on the opposing chip, die, or wafer. Other flowable joining materials and combinations of flowable joining materials may also be used.

For nanowire bonding interfaces that include a solder906, the nanowires100may penetrate the malleable solder and may enter into the metal-metal bond formed by the solder and the conductive pad902being bonded, while the nanowires100horizontally outside the confines of the conductive pads902merely conform to the non-metal part of the surface by yielding, including bending, kinking, or breaking. The yielding nanowires100up against a nonmetal do not enter into formation of an electrical interconnect.

In an example joining process, the opposing surfaces are aligned until the nanowires100touch the opposing conductive pads902, the temperature is raised, optionally until the joining metal flows, then the backs of the two chips, dies, or wafers are pressed until the adhesive904joins the top dielectric surfaces of the chips, dies, or wafers.

FIG.10shows an example nanowire bonding interface with nanowires100to be bonded to an opposing conductive pad1002. An adhesive layer1004is placed across an entire area of the surface to be bonded, including in the areas of the nanowires100and likewise over areas that have no nanowires100. The adhesive layer1004is of lesser height than the average height of the nanowires100, so that the ends of the nanowires100may contact the opposing conductive pads1002without much interference of the adhesive layer1004, and to prevent an excess volume of the adhesive1004interfering with the joining. The adhesive layer1004may initially be placed on the same surface as the nanowires100, or may be placed on the opposing surface, as shown.

FIG.11shows an example fabrication process1100in steps. In one implementation of a fabrication process, a thin layer1102of a material is deposited on a surface of a die, wafer, or substrate, including upon conductive areas that are to become one or more conductive interconnects. If TSVs are present, then a conductive surface of each TSV is exposed, from the back of the wafer, for example. Pads, such as pads304inFIG.3, may be added to the surface aspect of TSVs302, if needed.

Pores1104are then formed in the deposited material1102, if the deposited material1102is not already nanoporous. If needed, a film of insulator material1106is deposited on the walls of the pores1104, when the deposited material1102is a conductor or semiconductor.

Also, if needed, the bottoms1108of the pores1104are then cleaned as needed, to prepare for good electrical conduction between pads108and the conductive nanowires100to be formed next.

Next, the pores1104are plated or otherwise filled with a metal, such as copper to make the nanowires100. The nanowires100may be formed by deposition, electrolytic plating, electroless plating, crystal growth, and so forth. The nanowires100may be grown to an average height, and then planarized if desired to average heights that are within 5-10% of each other. If greater uniformity of height is desired than is present after nanowire growth, the nanowires may be lapped, for example, and ends further plated on the nanowires100by electroless plating or other techniques.

Next, the nanoporous layer1102may be at least partially removed1110or recessed1110to expose at least some of the vertical length of the nanowires100, for bonding, if such ends are not already exposed. The nanoporous layer1102may be recessed or removed by chemical means, electrochemical means, or physical means, depending on the material1102used.

FIG.12shows an example process of creating nanowires100through a combination lithography process. A chip, die, or wafer1200has conductive traces1202, onto which a film of polymer1204or other material is spread for becoming a nanoporous layer for creating the nanowires100. The polymer1204may be baked, if needed.

A seed layer1206of a first metal is deposited over conductors or pads where the nanowires100are to be present for bonding to an opposing conductive pad on another surface.

A photoresist layer1208is deposited over the seed layer1206and over the polymer layer1204. Photolithography of the photoresist layer1208makes nanopores1210in the photoresist layer1208. Alternatively, the photoresist layer1208is just a resist that is etched in another manner to make the nanopores1210, without light. The nanopores may be 200 nm in diameter, or smaller.

Copper metal, or another metal, is plated or otherwise grown on the seed layer1206, forming the nanowires100. In an implementation, the metal plated or deposited as the nanowires100is a different metal than the first metal of the seed layer1206. This is to provide selectivity for stripping or cleaning the copper metal or other metal used for the nanowires100, so that the stripping or cleaning does not remove the attachment of the nanowires100from their seed layer1206, which should be impervious to the stripper or cleaner.

The photoresist layer1208is stripped away1212leaving exposed nanowires100, ready for compression against an opposing conductive pad and for direct metal bonding with the opposing conductive pad. The polymer layer1204may be partly removed1214, depending on implementation.

FIG.13shows another example process of creating nanowires100through a combination lithography process. In this process, the nanoporous layer is completely removed, with nanowires100grown directly on pads or traces to be bonded.

A chip, die, or wafer1300has conductive traces1302, onto which a film of polymer1304or other material is spread for becoming a nanoporous layer for creating the nanowires100. The polymer layer1304may be baked, if needed.

A photoresist layer1306is deposited over the polymer layer1304. Photolithography of the photoresist layer1306makes nanopores1308in the photoresist layer1306. Alternatively, the photoresist layer1306is just a resist that is etched in another manner to make the nanopores1308, without light. The nanopores may be 200 nm in diameter, or smaller.

The nanopores1308in the photoresist layer1306are used to etch through the polymer layer1304, to make extended nanopores1310down to the conductive pad1302of the chip, die, or wafer1300.

Copper metal, or another metal, is plated or otherwise grown on the conductive pads1302, forming the nanowires100.

The photoresist layer1306is stripped away1312leaving exposed nanowires100, ready for compression against an opposing conductive pad and for direct metal bonding with the opposing conductive pad. The nanoporous polymer layer1304is then removed1314, leaving only conductive pads1302and the nanowires100.

FIG.14shows an example nanowire bonding interface102in which the nanowires100are surmounted or mixed with a flowable joining material, such as tin metal (Sn)1402or a combination solder alloy. The “tinned” nanowires100may bond by elevating a temperature to the melting point of the tin or solder, or by compressive pressure when the solder or alloy is malleable, or by both raised temperature and applied pressure.

In an implementation, the nanowires100may be coated with the flowable joining material, such as a solder, and then heat and/or pressure may be applied to cause the solder or other flowable joining material on the nanowires100or opposing conductive pad to flow, making a solder bond.

In an implementation, the nanowire bonding interface102also includes a layer or film of a second metal besides tin, such as a nickel (Ni) layer1404. A given microelectronics package104may use one of many different intermetallic compounds formed during solidifying of solders and during their reactions with the surfaces being soldered. The intermetallics may form distinct phases as inclusions in a ductile solid solution matrix or can form the matrix itself with metal inclusions, or can form various crystalline structures with different intermetallics. When the nanowires100are made of copper metal, a range of intermetallics may form between the copper metal and the tin or solder, with increasing proportion of the copper metal, such as Cu—Cu3Sn—Cu6Sn5—Sn, and so forth. Gold or palladium may be used as a coating to facilitate bonding because they readily dissolve in solders. Copper and nickel1404tend to form intermetallic layers during soldering processes, forming Ni3Sn4, for example, in the solder-nickel intermetallic interface.

In a variation, the example nanowires100are formed on the conductive pads108of one surface1406to be bonded, while the tin1402or solder alloy, and/or nickel1404are coated or formed on opposing conductive pads108′ that have no nanowires100, on the opposing surface1408.

FIG.15shows an implementation of the nanowire bonding interface1500, used in this scenario to make a flat top surface1500on a die, wafer, or device that has an uneven top surface1502. The flat nanowire bonding interface1500may used for direct bonding, or other bonding, or may be used to create a spacer or interposer between dies, for example. The uneven surface1502of the die, wafer, or device is covered with a material1504, which is then optionally flattened1506. Pores are created in the material1504, to make a nanoporous layer1508. Nanowires100are then grown in the pores. Instead of the nanoporous layer1508being at least partially removed or recessed as in previously described implementations, the top surface1500of the nanoporous layer1508is flattened1510, lapped, or polished by CMP or other planarizing techniques for direct bonding, or other bonding. The flat surface1500has planar cross-sectional ends of the nanowires100that have been grown in the pores of the nanoporous material1508and subsequently planarized1510, and has remaining areas that consist of the flattened nanoporous material1504. At this point, the flat surface1500can be direct-bonded through DBI® or other direct bonding techniques to conductive pads of an opposing surface1514.

FIG.16shows another implementation of the nanowire bonding interface102in which the flat surface1500ofFIG.15is used as a base to further grow the nanowires100to a greater vertical height1602by electroless plating of the same or a different metal, such as copper, nickel, gold, etc., or by metallic crystal growth, vapor deposition crystal growth, and so forth, on top of the existing nanowires100.

FIG.17shows an example interposer1700, with nanowires100disposed through the substrate1702, in one implementation. The substrate1702may be porous silicon or oxidized alumina, ceramic, or other materials. The example interposer1700has a first side and a second side, wherein the nanowires100penetrate through the interposer1700to make respective layers of nanowire ends1704&1706on opposing sides of the interposer1700. One or both sides of the nanowire ends1704&1706may be tinned or primed with solder or tin metal1708and/or another metal1710, such as nickel, or alloy. The example two-sided interposer1700can bond a chip or wafer, or both chips and wafers, on both of its sides1704&1706. The interposer1700, including the respective layers of nanowire ends1704&1706, may have a total thickness of approximately 100 μm or less.

Example Method

FIG.18shows an example method1800of creating a nanowire bonding interface. In the flow diagram ofFIG.18, operations of the example method1800are shown in individual blocks.

At block1802, a material is deposited on at least a conductive pad of a bonding surface.

At block1804, pores are created in the material deposited on the conductive pad to create a nanoporous layer.

At block1806, nanowires of a metal are grown in the pores of the nanoporous layer.

At block1808, at least a partial thickness of the nanoporous layer is removed or recessed to expose the nanowires for bonding with an opposing conductive pad.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some instances, the terminology and symbols may imply specific details that are not required to practice those embodiments. For example, any of the specific dimensions, quantities, material types, fabrication steps and the like can be different from those described above in alternative embodiments. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. The terms “example,” “embodiment,” and “implementation” are used to express an example, not a preference or requirement. Also, the terms “may” and “can” are used interchangeably to denote optional (permissible) subject matter. The absence of either term should not be construed as meaning that a given feature or technique is required.

Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments can be applied in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

While the present disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations there from. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the disclosure.