Patent ID: 12230318

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification.

Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.

Reference throughout the specification to “one embodiment,” “an embodiment,” or “some embodiments” means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment of the present disclosure. Thus, uses of the phrases “in one embodiment” or “in an embodiment” or “in some embodiments” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments.

In this document, the term “coupled” may also be termed as “electrically coupled”, and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

Furthermore, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used throughout the description for ease of understanding to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The structure may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, “around”, “about”, “approximately” or “substantially” shall generally refer to any approximate value of a given value or range, in which it is varied depending on various arts in which it pertains, and the scope of which should be accorded with the broadest interpretation understood by the person skilled in the art to which it pertains, so as to encompass all such modifications and similar structures. In some embodiments, it shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about”, “approximately” or “substantially” can be inferred if not expressly stated, or meaning other approximate values.

FIG.1illustrates a circuit diagram of a memory device100, in accordance with some embodiments of the present disclosure. Bit cells BC0, BC1, . . . , and BCn are arranged in a same column and respective rows R[0], R[1], . . . , and R[n]. For simplicity of illustration, only one column and few bit cells BC0, BC1, . . . , and BCn are shown inFIG.1, the memory device100may include other bit cells arranged in other columns and rows. Also, only one bit line BL and one complementary bit line BLB are shown inFIG.1for illustration. Each of the bit cells BC0, BC1, . . . , and BCn are coupled to the bit line BL and the complementary bit line BLB, and are also coupled to respective word lines WL0, WL1, . . . , and WLn. For simplicity, each of the bit cells BC0, BC1, and BCn is referenced as BC hereinafter for illustration, because the bit cells BC0, BC1, . . . , and BCn operate in a similar way in some embodiments. Based on the similar reasons, the each of the WL0, WL1, . . . , and WLn is referenced as WL hereinafter.

Each of the bit cells BC includes a pair of invertors and two transistors. The pair of invertors in each of the bit cells BC are coupled together and also coupled to the transistors. The transistors in each of the bit cells BC are further coupled to the bit line BL, the complementary bit line BLB and the corresponding word line WL. In some embodiments, for each of the bit cells, the pair of invertors are configured to store bit data. The transistors are configured to activate the pair of invertors and to write or read the bit data, in response to a word line signal and a bit line signal. The word line signal is transmitted through the corresponding word line WL, and the bit line signal is transmitted through the bit line BL and the complementary bit line BLB. In some other embodiments, each of the bit cells BC is a static random access memory (SRAM) cell formed by six transistors (6T-SRAM). In various embodiments, each of the bit cells BC is implemented by a single port SRAM cell. In alternative embodiments, each of the bit cells BC is implemented by a dual port SRAM cell. Each of the bit cells BC can be formed by other equivalent SRAM cells, and various configurations of the bit cells BC are within the contemplated scope of the present disclosure.

Each of the word lines WL is split among various levels of the memory device100, in some embodiments. For each of the word lines WL, the separated portions are formed in different metal layers of the memory device100, and are coupled together to transmit the corresponding word line signal. By arranging separated portions of the word lines WL among various metal layers, at least one of the separated portions in one of the metal layers is widened to have a broaden area, in compliance with a design rule for generating a layout design of the memory device100. In some embodiments, two adjacent word lines WL are considered as a group having a specific configuration of these separated portions. For example, as illustrated inFIG.1, the word lines WL0and WL1are considered as one group, and the word lines WL2and WL3(not shown) are considered as another group. Each of the groups has the same configuration for arranging the corresponding separated portions of the word lines WL, and such configuration is further illustrated in cross-section diagrams and layout diagrams as discussed below.

Reference is made toFIGS.2A and2B.FIGS.2A and2Bare cross-section schematic diagrams of parts of a memory device200corresponding to the memory device100shown inFIG.1, in accordance with some embodiments of the present disclosure. For ease of understanding, the embodiments with respect toFIG.2Aare discussed with reference toFIG.2B. With respect to the embodiments ofFIG.1, like elements inFIGS.2A and2Bare designated with the same reference numbers for ease of understanding.

As illustrated inFIG.2A, the bit cell BC0is coupled to the word line WL0. The bit cell BC0corresponds to the bit cell BC0shown inFIG.1, and the word line WL0corresponds to the word line WL0shown inFIG.1, in some embodiments. The word line WL0has portions WL0-1, WL0-2, WL0-3aand WL0-3band vias VA. These portions WL0-1, WL0-2, WL0-3aand WL0-3bare separated and disposed in continuous metal layers M1, M2and M3. The vias VA are disposed between two adjacent of the metal layers M1-M3to couple the portions WL0-1, WL0-2, WL0-3aand WL0-3btogether. For simplicity of illustration, only one via VA is labeled inFIG.2Aor other respective figures illustrated in some embodiments of the present disclosure. The portions of the corresponding word lines WL illustrated in some embodiments of the present disclosure are also referred to as segments hereinafter.

The segment WL0-1is formed in the M1layer. The segments WL0-3aand WL0-3bare formed in the M2layer above the M1layer. The segment WL0-2is formed in the M3layer above the M2layer. The segment WL0-1is coupled to the transistors of the bit cell BC0, and is further coupled through vias VA to the segments WL0-3aand WL0-3b. The segments WL0-3aand WL0-3bare coupled through vias VA to the segment WL0-2. In some embodiments, the segment WL0-3bis identical to the segment WL0-3athat having the same structure configurations. With such configurations, the segments WL0-1, WL0-3aand WL0-3b, and WL0-2are coupled in parallel with one another.

As illustrated inFIG.2B, the bit cell BC1is coupled to the word line WL1. The bit cell BC1corresponds to the bit cell BC1shown inFIG.1, and the word line WL1corresponds to the word line WL1shown inFIG.1, in some embodiments. The word line WL1has segments WL1-1, WL1-2, WL1-3a, WL1-3b, WL1-4, WL1-5aand WL1-5b, and the vias VA, V3-1, V3-2, V4-1and V4-2. The segments WL1-1, WL1-2, WL1-3a, WL1-3b, WL1-4, WL1-5aand WL1-5bof the word line WL1are disposed in continuous metal layers M1-M5and are coupled together. The vias VA are disposed between the M1and the M2layers, and between the M2and the M3layers. The vias V3-1and V3-2are disposed between the M3and the M4layers. The vias V4-1and V4-2are disposed between the M4and the M5layers.

The segment WL1-1is formed in the M1layer. The segments WL1-3aand WL1-3bare separated and are formed in the M2layer. The segment WL1-4is formed in the M3layer. The segments WL1-5aand WL1-5bare separated and are formed in the M4layer above the M3layer. The segment WL1-2is formed in the M5layer above the M4layer. The segment WL1-1is coupled to the transistors of the bit cell BC1, and is further coupled through vias VA to the segments WL1-3aand WL1-3b. The segments WL1-3aand WL1-3bare coupled through vias VA to the segment WL1-4. The segment WL1-4is coupled through vias V3-1and V3-2to the segments WL1-5aand WL1-5b. The segments WL1-5aand WL1-5bare coupled through vias V4-1and V4-2to the segment WL1-2. With such configurations, the segments WL1-1, WL1-3aand WL1-3b, WL1-4, WL1-5aand WL1-5b, and WL1-2are coupled in parallel with one another.

In some embodiments, the segment WL1-3bis identical to the segment WL1-3a. The segments WL1-5aand WL1-5bhave structure configurations that are the same; the vias V3-1and V3-2have the same structure configurations; and the vias V3-1and V3-2also have the same structure configurations.

The number and arrangement of the metal layers M1-M5shown inFIGS.2A and2Bare given for illustrative purposes. Various numbers and arrangements of the metal layers M1-M5to implement the memory device200inFIGS.2A and2Bare within the contemplated scope of the present disclosure. For example, in some embodiments, only one segment WL0-3aof the word line WL0is in the M2layer, for coupling the remaining segments WL0-1and WL0-2together.

Reference is made toFIG.3.FIG.3is a schematic layout diagram300of parts of a memory device corresponding to the memory device200shown inFIGS.2A and2B, in accordance with some embodiments of the present disclosure. The cross line A-A′ corresponds to the cross line A-A′ shown inFIG.2A, and the cross line B-B′ corresponds to the cross line B-B′ shown inFIG.2B, in some embodiments. For ease of understanding, the embodiments with respect toFIG.3are discussed with reference toFIGS.2A and2B, and only illustrate elements that are associated with the word lines WL0-WL3. With respect to the embodiments ofFIGS.2A and2B, like elements inFIG.3are designated with the same reference numbers for ease of understanding.

As illustrated inFIG.3, the layout diagram300illustrates a plan view, viewing a part of the memory device formed in the M3-M5layers. The word lines WL0, WL1, WL2and WL3are arranged in a same column and the rows R[0], R[1], R[2] and R[3] respectively. As illustrated inFIG.3, cross section views of the layout diagram300along the cross-line A-A′ and the cross-line B-B′ correspond to the structures formed above the M3layers as discussed above inFIG.2Aand inFIG.2B, respectively. In some embodiments, a length along an X direction of the word lines WL0-WL3shown inFIG.3is substantially equal to a cell width of the bit cells BC as shown inFIG.1. A width along a Y direction of each of the rows R[0], R[1], R[2] and R[3] shown inFIG.3is substantially equal to a cell height of the bit cells BC as shown inFIG.1. The layout diagram300further includes other columns that extend along the X direction and other rows that extend along the Y direction. For simplicity of illustration, only one column and few rows R[0]-R[3] are illustrated inFIG.3. In some embodiments, the word lines WL0and WL2have similar configurations for arranging their own separated segments and vias, and the word lines WL1and WL3have similar configurations of the same. As such, similar configurations are not further detailed herein.

In the M3layer, the segments WL0-2of the word line WL0and WL1-4of the word line WL1extend along the X direction, and are separated from each other in the Y direction. In the M4layer, the segments WL1-5aand WL1-5bof the word line WL1extend along the Y direction, and are separated from each other in the X direction. Edges of the segments WL1-5aand WL1-5balong the Y direction are substantially overlapped and aligned with boundaries of the corresponding bit cells BC as shown inFIG.1, in some embodiments. In the M5layer, the segments WL1-2of the word line WL1extends along the X direction. Between the M3and M4layer, the vias V3-1and V3-2are shaped as squares, and are separated from each other in the X direction. Between the M4and M5layer, the vias V4-1and V4-2are shaped as squares, and are separated from each other in the X direction. In the Y direction, the via V4-1is further separated from the via V3-1, and the via V4-2is further separated from the via V3-2.

With reference toFIGS.2B and3, the segment WL1-2is disposed above the remaining segments and vias of the word line WL1. In a layout view inFIG.3, in some embodiments, the segment WL1-2is partially overlapped with the segments WL1-4, WL1-5aand WL1-5b. The segment WL1-2is further partially overlapped with the segment WL0-2of the word line WL0. Alternatively stated, the segment WL1-2is overlapped with the segments WL1-4of the word line WL1and the segments WL0-2of the word line WL0with an offset along the Y direction. Also, the segment WL1-2is overlapped with parts of the segments WL1-5aand WL1-5bof the word line WL1. In addition, the segment WL1-2is overlapped with the parts of the vias V3-1and V3-2, and is overlapped with the entire vias V4-1and V4-2.

Furthermore, the segment WL1-5ais partially overlapped with the segments WL0-2and WL1-4, and is entirely overlapped with the vias V3-1and V4-1. The segment WL1-5bis partially overlapped with the segments WL0-2and WL1-4, and is entirely overlapped with the vias V3-2and V4-2.

The configuration of the word lines WL0-WL3shown inFIG.3is given for illustrative purposes. Various configurations of the word lines WL0-WL3shown inFIG.3are within the contemplated scope of the present disclosure.

Reference is made toFIGS.4A and4B.FIGS.4A and4Bare cross-section schematic diagrams of parts of a memory device400corresponding to the memory device illustrated as the layout diagram300shown inFIG.3, in accordance with some embodiments of the present disclosure. The memory device illustrated as the layout diagram300shown inFIG.3also corresponds to the memory device200shown inFIGS.2A and2B, thereby like elements inFIGS.4A and4Bbeing designated with the same reference numbers with respect to the embodiments ofFIGS.2A-3, for ease of understanding.

FIG.4Aillustrates a cross section view, viewing at a cross line C-C′ shown inFIG.3, and only illustrates elements that are associated with the word line WL0. As illustrated inFIG.4A, the segments WL0-1, WL0-3aand WL0-2are formed in the M1-M3layers respectively, and contact through vias VA together, as discussed above with reference toFIG.2A. The segments WL0-2is disposed above and overlapped with the segments WL0-3aand WL0-1entirely.

FIG.4Billustrates a cross section view, viewing at a cross line D-D′ shown inFIG.3, and only illustrates elements that are associated with the word line WL1. As illustrated inFIG.4B, the segments WL1-1, WL1-3b, WL1-4, WL1-5band WL1-2are formed in the M1-M5layers respectively, and contact through vias VA, V3-2and V4-2together, as discussed above with reference toFIG.2B. The segments WL1-2is disposed above and offset the segments WL1-1, WL1-3b, WL1-4and WL1-5b, thereby partially overlapped with these segments as discussed above with reference toFIG.3.

In some embodiments, as the segments shown inFIGS.2A-4Bhave heights along a Z direction (not shown) that are the same, sizes of the segments are referred to as areas. With reference back toFIGS.3and4A, since the cross line C-C′ extends along the Y direction, a length of the segment WL0-2along the cross line C-C′ shown inFIG.4Acorresponds to a width of the segment WL0-2along the Y direction shown inFIG.3, in some embodiments. Thereby, a width of the segment WL0-2is greater than a width of the segments WL0-3aor WL0-1, in some embodiments. Similarly, with reference back toFIGS.3and4B, since the cross line D-D′ extends along the Y direction, a length of the segment WL1-2along the cross line D-D′ shown inFIG.4Bcorresponds to a width of the segment WL1-2along the Y direction shown inFIG.3, in some embodiments. A width of the segment WL1-2is greater than a width of at least one of the segments WL1-1, WL1-3b, WL1-4and WL1-5b, in some embodiments.

The segments WL0-1and WL1-1in the M1layer is coupled to the corresponding bit cells BC0and BC1, as discussed with reference toFIGS.2A-2B. In some embodiments, with reference toFIGS.2A to4B, these segments of the word lines WL0-1and WL1-1that contact with the corresponding bit cell BC0or BC1are indicated as base segments. The base segment is referred to as a portion of the corresponding word lines WL0or WL1that is formed in the lowest metal layer and contacts to the bit cells BC0or BC1. In addition, the segments WL0-2in the M3layer and WL1-2in the M5layer are indicated as roof segments. The roof segment is referred to as a portion of the corresponding word lines WL0or WL1that is formed in the highest metal layer. The remaining segments including, for example, the segments WL0-3a, WL0-3b, WL1-3aand WL1-3bin the M2layer, the segments WL1-4in the M3layer, and the segments WL1-5aand WL1-5bin the M4layer, are indicated as interconnection segments. The interconnection segment is referred to as a portion of the corresponding word lines WL0or WL1that is formed between the highest and the lowest metal layers, and coupled between the base segment and the roof segment. Sizes/areas of the base segment, the interconnection segment, and the roof segment of the word line WL0or WL1are further detailed below, in various embodiments.

In some embodiments, at least two segments of the word lines in various metal layers have sizes/areas that are different from each other. For each of the word lines, at least two of the interconnection segment, the base segment, and the roof segment have sizes/areas that are different from each other, as discussed below.

For each of the word lines, in some embodiments, the interconnection segment has an area that is different from an area of the roof segment, and is further different from an area of the base segment. For example, with reference toFIGS.2A to4B, for the word line WL0, lengths of the segments WL0-1, WL0-2, and WL0-3a, along the X direction are substantially the same, as illustrated inFIG.2A. A width of the segment WL0-3aalong the Y direction is smaller than a width of each of the segments WL0-1and WL0-2, as illustrated inFIG.4A. Thereby, an area of the segment WL0-3ais smaller than an area of the segment WL0-1, and is also smaller than an area of the segment WL0-2. Alternatively stated, an area of at least one of the interconnection segments is smaller than an area of the base segment or the roof segment. In another way to explain, the base segment or the roof segment has a size that is greater than a size of each of the interconnection segments, as these segments have the same height along the Z direction (not illustrated). As such, the size of the segment of the embodiments of the present disclosure is referred to as the area hereinafter.

Furthermore, in some embodiments, for the word line WL1, lengths of the segments WL1-1, WL1-2and WL1-4along the X direction are substantially the same, as illustrated inFIG.2B. A width of the segment WL1-4along the Y direction is smaller than a width of each of the segments WL1-1and WL1-2, as illustrated inFIG.4B. Thereby, an area of the segment WL1-4is smaller than an area of the segment WL1-1or WL1-2. In addition, a length of each of the segments WL1-3band WL1-5balong the Y direction is smaller than a length of the segment WL1-1or WL1-2, as illustrated inFIG.4B. A width of each of the segments WL1-3band WL1-5balong the X direction is smaller than a width of the segment WL1-1or WL1-2, as illustrated inFIG.2B. Thereby, an area of the segment WL1-3bor WL1-5bis smaller than an area of the segment WL1-1or WL1-2.

In some embodiments, the interconnection segment disposed between the lowest and the highest metal layers is also indicated as an internal contact portion of the word line, for coupling the base segment and the roof segment. For example, as illustrated inFIG.2A, the segments WL0-3aand WL0-3bare configured to couple the segment WL0-1and the segment WL0-2. In another example, as illustrated inFIG.2B, the segments WL1-3a, WL1-3b, WL1-4, WL1-5aand WL1-5bare configured to couple the segment WL1-1and the segment WL1-2. With such configurations, the interconnection segment is further configured to adjust an internal resistance of the corresponding word line by having various areas. Alternatively stated, an equivalent resistance of each of the word line is adjusted by the area of the interconnection segment. The word line including, for example, the word lines WL0and WL1, have equivalent resistances that are substantially the same with adjustments of respective interconnection segments, in some embodiments.

For each of the word lines, in some embodiments, the base segment has an area that is different from an area of the roof segment. For example, with reference toFIGS.2A to4B, for the word line WL0, a width of the segment WL0-1along the Y direction is smaller than a width of the segment WL0-2, as illustrated inFIG.4A. Thereby, the segments WL0-1and WL0-2have areas that are different from one another, with having the same length as discussed above. Similarly, for the word line WL1, a width of the segment WL1-2along the Y direction is greater than a width of the segment WL1-1, as illustrated inFIG.4B, thereby, the segments WL1-1and WL1-2having different areas. Alternatively stated, the base segment and the roof segment have sizes that are different from one another.

For two adjacent word lines, in some embodiments, the respective roof segments have areas that are different from each other. For example, as illustrated inFIG.3, the segment WL0-2has an area that is greater than an area of the segment WL1-2.

In some embodiments, the base segments of the respective word lines are disposed in a same metal layer which is also indicated as a base metal layer. For example, with reference toFIGS.2A and2B, the segments WL0-1and WL1-1are both formed in the M1layer. In other embodiments, the roof segments of the respective word lines are disposed in a different metal layers which are also indicated as roof metal layers. For example, with reference toFIGS.2A and2B, the segment WL0-2is formed in the M3layer, and the segment WL1-2is formed in the M5layer. With such configurations, both of the base segment and the roof segment are also indicated as two main structures coupled with the interconnection segment, for transmitting the corresponding word line signal.

For each of the word lines, in some embodiments, in a same metal layer, at least two segments are separated from each other and have areas that are substantially the same. For example, with reference toFIG.2A, for the word line WL0, in the M2layer, the segments WL0-3aand WL0-3bare separated and have areas that are substantially the same. With reference toFIG.2A, for the word line WL1, the separated segments WL1-3aand WL1-3bin the M2layer have the same areas. In other examples, with reference toFIGS.2B and3, for the word line WL1, the separated segments WL1-5aand WL1-5bin the M4layer are disposed in parallel to each other. In addition, the segments WL1-5aand WL1-5bhave the same areas.

For two adjacent word lines, in some embodiments, in a same metal layer, at least two segments of the corresponding word lines are separated from each other and have areas that are substantially the same. For example, for the word lines WL0-WL3, in the M1layer, the segments WL0-1and WL1-1, and the base segments of the word lines WL2and WL3(not illustrated) are separated from each other evenly, and have areas that are substantially the same.

For two adjacent word lines, in some embodiments, in a same metal layer, at least two segments of the corresponding word lines are separated from each other and have areas that are different from each other. For example, as illustrated inFIG.3, in the M3layer, an area of the segment WL0-2of the word line WL0is greater than an area of the segment WL1-4of the word line WL1.

In some approaches, word lines included in a memory device are formed in the same metal layer, and are arranged in rows sequentially, for transmitting the word line signals to respective bit cells. As such, areas of the word lines are restricted to the row height (i.e., the cell height), and the equivalent resistances of the word lines depend on these areas with negative correlations. Accordingly, the performance of the word lines is affected by the equivalent resistances of the word liens.

Compared to the above approaches, in the embodiments of the present disclosure, for example with reference toFIGS.2A-4B, separated portions of each of the word lines WL0-WL1are formed in multiple metal layers. The equivalent resistance of the word lines WL0or WL1is reduced because the separated portions of the respective word line WL0or WL1are coupled in parallel. Furthermore, portions of the word lines WL0and WL1that indicate as the roof segments have a greater area than an area of at least one of the remaining segments of the word lines WL0and WL1. Thereby, these portions have various areas and also have a certain scheme of arrangements and configurations. Accordingly, for each of the word lines WL0and WL1, the equivalent resistance is optimized and is able to be adjusted or further reduced.

Reference is made toFIG.5.FIG.5is a schematic layout diagram500of parts of a memory device corresponding to the memory device200shown inFIGS.2A and2B, in accordance with some embodiments of the present disclosure. The cross line A5-A5′ corresponds to the cross line A-A′ shown inFIG.2A, and the cross line B5-B5′ corresponds to the cross line B-B′ shown inFIG.2B, in some embodiments. The layout diagram500illustrated inFIG.5is an alternative embodiment of the layout diagram300illustrated inFIG.3, as such, similar configurations are not disclosed herein. With respect to the embodiments ofFIGS.2A-3, like elements inFIG.5are designated with the same reference numbers for ease of understanding.

Compared toFIG.3, in the layout diagram500shown inFIG.5, the word line WL0has multiple segments WL0-1(not shown) in the M1layer, WL0-3aand WL0-3b(not shown) in the M2layer, WL0-4in the M3layer, WL0-5aand WL0-5bin the M4layer, and the WL0-2in the M5layer. The word line WL0further includes vias VA (not shown) between the M1and M2layers, and between the M2and M3layers, and also includes vias V3-1and V3-2between the M3and M4layers, and the vias V4-1and V4-2between the M4and M5layers. The word line WL0has a configuration for arranging the segments WL0-1, WL0-2, WL0-3a, WL0-3b, WL0-4, WL0-5aand WL0-5b, and the vias VA, V3-1, V3-2, V4-1and V4-2. This configuration is as same as that of the word line WL1as illustrated inFIG.2B, for arranging the segments WL1-1, WL1-2, WL1-3a, WL1-3b, WL1-4, WL1-5aand WL1-5b, and the vias VA, V3-1, V3-2, V4-1and V4-2. As such, similar configurations are not disclosed herein.

Furthermore, compared toFIG.3, the word line WL1in the layout diagram500has segments WL1-1(not shown) in the M1layer, WL1-3aand WL1-3b(not shown) in the M2layer, and WL1-2in the M3layer. The word line WL1further includes vias VA (not shown) between the M1and M2layers. The word line WL1has a configuration for arranging the segments WL1-1, WL1-2, WL1-3aand WL1-3b, and the vias VA. This configuration is as same as that of the word line WL0as illustrated inFIG.2A, for arranging the segments WL0-1, WL0-2, WL0-3aand WL0-3b, and the vias VA. As such, similar configurations are not disclosed herein.

As illustrated inFIG.5, in some embodiments, in the M3layer, an area of the segment WL0-4is smaller than an area of the segment WL1-2. For the word line WL0, the segment WL0-4in the M3layer has an area that is further smaller than an area of the segment WL0-2in the M5layer.

Reference is made toFIG.6.FIG.6is a cross-section schematic diagram of parts of a memory device600corresponding to the memory device100shown inFIG.1, in accordance with some embodiments of the present disclosure. The memory device600illustrated inFIG.6is an alternative embodiment of the memory device200illustrated inFIGS.2A-2B, as such, similar configurations are not disclosed herein. With respect to the embodiments ofFIGS.1-2B, like elements inFIG.6are designated with the same reference numbers for ease of understanding.

As illustrated inFIG.6, the word line WL1contacting to the bit cell BC1has various segments and vias in the M1-M5layers. Compared toFIG.2B, in the memory device600shown inFIG.6, two segments WL1-4aand WL1-4bare formed in the M3layer, and are separated from each other. Alternatively stated, in the M3layer, the segment WL1-4illustrated inFIG.2Bis split into multiple segments WL1-4aand WL1-4billustrated inFIG.6. In some embodiments, the segments WL1-4aand WL1-4bare two identical metal structures. In various embodiments, the segments WL1-4aand WL1-4bare indicated as interconnection segments, for coupling the segments WL1-1and WL1-2, as discussed above.

Reference is made toFIG.7.FIG.7is a schematic layout diagram700of parts of a memory device corresponding to the memory device600shown inFIG.6and the memory device200shown inFIG.2A, in accordance with some embodiments of the present disclosure. The cross line A-A′ corresponds to the cross line A-A′ shown inFIG.2A, and the cross line B6-B6′ corresponds to the cross line B6-B6′ shown inFIG.6, in some embodiments. The layout diagram700illustrated inFIG.7is an alternative embodiment of the layout diagram300illustrated inFIG.3, as such, similar configurations are not disclosed herein. With respect to the embodiments ofFIGS.2A,3and6, like elements inFIG.7are designated with the same reference numbers for ease of understanding.

Compared toFIG.3, in the layout diagram700shown inFIG.7, the segments WL1-4aand WL1-4bextend along the X direction, and are separated from each other in the X direction. The segment WL1-4a, the segment WL1-5aand the via V3-1are overlapped. The segment WL1-4b, the segment WL1-5band the via V3-2are overlapped. The segment WL1-2is partially overlapped with the segments WL0-2of the word line WL0, the segments WL1-4a, WL1-4b, WL1-5aand WL1-5bof the word line WL1, and a space between the segments WL1-4aand WL1-4b.

As illustrated inFIG.7, in some embodiments, the segments WL1-4aand WL1-4bhave areas that are substantially the same. Specifically, in the X direction, a length of the segment WL1-4ais substantially equal to a length of the segment WL1-4b. In the Y direction, a width of the segment WL1-4ais substantially equal to a width of the segment WL1-4b. In some other embodiments, along the X direction, the segments WL1-4aand WL1-4band the space between the segments WL1-4aand WL1-4bhave lengths that are substantially the same. Alternatively stated, a length of the segment WL1-4aor WL1-4bis substantially equal to one cell width of the bit cells BC as shown inFIG.1divided by three, in some embodiments. It is also substantially equal to one cell width subtracted a specific length of the blank space between the segments WL1-4aand WL1-4b, and then divided by an amount of the segments WL1-4aand WL1-4b, in other embodiments. In another way to explain, a length of the segment WL1-4aor WL1-4bat least depends on the cell width and an amount of these segments in the M3layer.

In some embodiments, in another column that is disposed next to the column as illustrated inFIG.7, the word lines WL0-WL3have the same arrangements and configurations. Alternatively stated, along the X direction, the word lines WL0-WL3extend and are duplicated. With such configurations, an amount of the segment WL1-4aor WL1-4bin the M3layer is substantially equal to an amount of the bit cells arranged in one column and one of the rows R[0]-R[4]. With reference toFIG.7, an amount of the segment WL1-4aor WL1-4bis one. An amount of the bit cells arranged in such column and the row R[1], which is, the bit cell BC1shown inFIG.6, is also be one. Thereby, an amount of the segment WL1-4aor WL1-4bis equal to an amount of the column and the row R[1]. In some other embodiments, an amount of the split segments of one word line in a same layer is greater than an amount of the bit cells arranged in one of the rows R[0]-R[4]. For example, with reference toFIG.7, an amount of the split segments WL1-4a, WL1-4b, and other duplicated segments (not illustrated) of the word line WL1in the M3layer is greater than an amount of the bit cells arranged in the row R[1].

Reference is made toFIG.8.FIG.8is a cross-section schematic diagram of parts of a memory device800corresponding to the memory device100shown inFIG.1, in accordance with some embodiments of the present disclosure. The memory device800illustrated inFIG.8is an alternative embodiment of the memory device600illustrated inFIG.6, as such, similar configurations are not disclosed herein. With respect to the embodiments ofFIGS.1and6, like elements inFIG.8are designated with the same reference numbers for ease of understanding.

Compared toFIG.6, in the memory device800shown inFIG.8, one part WL0-2pof the word line WL0is illustrated as a segment, and is formed in the M3layer. The segment WL0-2pis disposed between the segments WL1-4aand WL1-4b, and is separated from the segments WL1-4aand WL1-4b.

Reference is made toFIG.9.FIG.9is a schematic layout diagram900of parts of a memory device corresponding to the memory device800shown inFIG.8, and the memory device200shown inFIG.2A, in accordance with some embodiments of the present disclosure. The cross line A-A′ corresponds to the cross line A-A′ shown inFIG.2A, and the cross line B8-B8′ corresponds to the cross line B8-B8′ shown inFIG.8, in some embodiments. The layout diagram900illustrated inFIG.9is an alternative embodiment of the layout diagram700illustrated inFIG.7, as such, similar configurations are not disclosed herein. With respect to the embodiments ofFIGS.2A,7and8, like elements inFIG.9are designated with the same reference numbers for ease of understanding.

Compared toFIG.7, in the layout diagram900shown inFIG.9, the segment WL0-2of the word line WL0further has a protruding part WL0-2pthat extends along the Y direction. The segment WL0-2is shaped as an alphabet “T”, in some embodiments. As illustrated inFIG.9, the protruding part WL0-2pis disposed between the segments WL1-4aand WL1-4b. The segment WL1-2is partially overlapped with the protruding part WL0-2pof the word line WL0, the segments WL1-4a, WL1-4b, WL1-5aand WL1-5bof the word line WL1, and is also partially overlapped with the spaces that is disposed between the segments WL1-4a, WL1-4band the protruding part WL0-2p.

In a same metal layer, in some embodiments, an area of the segments of the word line WL0is different from an area of the segments of the word line WL1. Specifically, as illustrated inFIG.9, in the M3layer, a total area of the segment WL0-2is greater than a total area of the segments WL1-4aand WL1-4b. In addition, compared to the embodiments illustrated inFIG.7, the roof segment of the word line WL0, which is the segment WL0-2, has a greater area. With such configurations, the word line WL0has a less equivalent resistance due to a broaden area of the segment WL0-2.

Reference is made toFIG.10.FIG.10is a schematic layout diagram1000of parts of a memory device corresponding to the memory device200shown inFIG.2B, in accordance with some embodiments of the present disclosure. The cross line B10-B10′ corresponds to the cross line B-B′ shown inFIG.2B, and the cross line B-B′ also corresponds to the cross line B-B′ shown inFIG.2B, in some embodiments. The layout diagram1000illustrated inFIG.10is an alternative embodiment of the layout diagram300illustrated inFIG.3or the layout diagram500illustrated inFIG.5, as such, similar configurations are not disclosed herein. With respect to the embodiments ofFIGS.2B,3and5, like elements inFIG.10are designated with the same reference numbers for ease of understanding.

Compared toFIG.3, in the layout diagram1000shown inFIG.10, the word line WL0has a segment WL0-4in the M3layer, segments WL0-5aand WL0-5bin the M4layer, and a segment WL0-2in the M5layer. The segments WL0-4and WL0-2extend along the X direction, and the segments WL0-5aand WL0-5bextend along the Y direction. The word line WL0further has vias V3-1, V3-2, V4-1and V4-2that have similar configurations as the same included in the word line WL1. The segment WL0-5ais overlapped with the vias V3-1and V4-1, and the segment WL0-5bis overlapped with the vias V3-2and V4-2. The segment WL0-2is disposed above and overlapped with the segments WL0-5a, WL0-5band WL0-4, and the vias V3-1, V3-2, V4-1and V4-2, without offset.

Furthermore, the word lines WL0and WL1have similar configurations, in some embodiments. For example, as illustrated inFIG.10, the segment WL1-2is also disposed above and overlapped with the segments WL0-5a, WL0-5band WL0-4, and the vias V3-1, V3-2, V4-1and V4-2, without offset.

As illustrated inFIG.10, in some embodiments, for the word line WL0, the segment WL0-2has an area that is smaller than an area of the segment WL0-4. In some embodiments, a length of the segment WL0-5aor WL0-5balong the Y direction is substantially equal to a width of the segment WL0-2along the Y direction. Alternatively stated, short edges of the segment WL0-5aor WL0-5bis parallel with and overlapped with long edges of the segment WL0-2. The word line WL1has similar configurations of the word line WL0, which is not detailed herein. Alternatively stated, in a same metal layer, for two adjacent word lines, the segments of the corresponding word lines have substantially the same areas, in some embodiments. For example, as illustrated inFIG.10, the segments WL0-4and WL1-4in the M3layer have substantially the same areas, and the segments WL0-2and WL1-2in the M5layer have substantially the same areas as well.

Reference is made toFIG.11.FIG.11is a schematic layout diagram1100of parts of a memory device corresponding to the memory device200shown own inFIG.2B, in accordance with some embodiments of the present disclosure. The cross line B11-B11′ corresponds to the cross line B-B′ shown inFIG.2B, and the cross line B-B′ also corresponds to the cross line B-B′ shown inFIG.2B, in some embodiments. The layout diagram1100illustrated inFIG.11is an alternative embodiment of the layout diagram500illustrated inFIG.5combined with the layout diagram1000illustrated inFIG.10, as such, similar configurations are not disclosed herein. With respect to the embodiments ofFIGS.2B,5and10, like elements inFIG.11are designated with the same reference numbers for ease of understanding.

Compared toFIG.10, in the layout diagram1100shown inFIG.11, the vias V3-1and V4-1of the word line WL0are separated from each other, and the vias V3-2and V4-2of the word line WL0are separated from each other. The segment WL0-4is directly overlapped with the vias V3-1and V3-2without offset, and is partially overlapped with the segments WL0-5aand WL0-5bwith offset. The segment WL0-2is directly overlapped with the remaining segments of the word line WL0including, for example, the segments WL0-4, WL0-5aand WL0-5band the vias V3-1, V3-2, V4-1and4-2. The segment WL0-2is further partially overlapped with the segment WL1-4of the word line WL1. Furthermore, the segment WL1-2of the word line WL1is overlapped with a part of the segment WL1-4.

As illustrated inFIG.11, in some embodiments, in the M3layer, the segment WL0-4has an area that is smaller than an area of the segment WL1-4, which is similar to the embodiments illustrated inFIG.5. In the M4layer, the segments WL0-5aand WL0-5bhave substantially the same areas, and the segments WL1-5aand WL1-5bhave substantially the same areas, which is similar to the embodiments illustrated in at leastFIG.5or10. Furthermore, an area of the segment WL0-5aor WL0-5bis greater than an area of the segment WL1-5aor WL1-5b. In the M5layer, the segment WL0-2has an area that is greater than an area of the segment WL1-2.

In some embodiments, the word line WL0illustrated inFIGS.2A-11is also indicated as an original even word line, and the word line WL1illustrated inFIGS.2A-11is also indicated as an original odd word line. The other word lines arranged in even rows including, for example, the row R[2] and R[4], have the separated segments. These separated segments of the corresponding word lines are arranged in configurations that are the same as the original even word line WL0. Similarly, the other word lines arranged in odd rows including, for example, the row R[3] and R[5], have the separated segments. These separated segments of the corresponding word lines are arranged in configurations that are the same as the original odd word line WL1. Alternatively stated, two adjacent word lines are considered as a group, for forming respective split segments in multiple metal layers, with various areas or shapes that discussed with reference toFIGS.2A-11.

Reference is made toFIG.12.FIG.12is a flow chart of a method1200for generating a memory device corresponding to at least one of the memory device100shown inFIG.1, the memory device200shown inFIGS.2A and2B, the memory device400shown inFIGS.4A and4B, the memory device600shown inFIG.6, or the memory device800shown inFIG.8, in accordance with some embodiments of the present disclosure. Following illustrations of the method1200inFIG.12with reference to the memory device200shown inFIGS.2A and2Binclude exemplary operations. However, the operations inFIG.12are not necessarily performed in the order shown. Alternatively stated, operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure.

In operation S1210, a first portion of a first word line and a first portion of a second word line are formed in a base metal layer. The base metal layer corresponds to the M1layer as illustrated inFIGS.2A-2B, in the following embodiments. For illustration, as shown inFIGS.2A and2B, the segment WL0-1of the word line WL0and the segment WL1-1of the word line WL1are formed in the M1layer.

In operation S1220, a second portion of the first word line and a second portion of the second word line are formed in a first metal layer above the base metal layer. The first metal layer corresponds to the M3layer that is above the M1layer as illustrated inFIGS.2A-10, in the following embodiments. For illustration, as shown inFIGS.2A and2B, the segment WL0-2of the word line WL0is formed in the M3layer. The segment WL1-4of the word line WL1is also formed in the M3layer.

In operation S1230, third portions of the second word line are formed in a second metal layer between the first metal layer and a third metal layer that is above the first metal layer. The second metal layer corresponds to the M4layer, and the third metal layer corresponds to the M5layer, wherein the M4layer is between the M3layer and the M5layer as illustrated inFIGS.2A-10, in the following embodiments. For illustration, as shown inFIG.2B, the segments WL1-5aand WL1-5bof the word line WL1are formed in the M4layer.

In operation S1240, a fourth portion of the second word line is formed in the third metal layer. The third metal layer corresponds to the M5layer that is above the M1layer as illustrated inFIGS.2A-10, in the following embodiments. For illustration, as shown inFIG.2B, the segment WL1-2of the word line WL1is formed in the M5layer.

In some embodiments, the method1200further includes the following operations. A third portion of the first word line is formed in the second metal layer. For illustration, in some embodiments, with reference toFIG.11, the segment WL0-2of the word line WL0, corresponding to the third portion, is formed in the M5layer, and the segment WL0-4of the word line WL0, corresponding to the second portion as illustrated in operation S1220, is formed in the M3layer.

In some embodiments, the method1200further includes the following operations. Fourth portions of the first word line are formed in a third metal layer between the first metal layer and the second metal layer. The third metal layer corresponds to the M4layer that is between the M3layer and the M5layer as illustrated inFIGS.2A-10, in the following embodiments. For illustration, in some embodiments, with reference toFIG.11, the segments WL0-5aand WL0-5bof the word line WL0are formed in the M4layer.

Reference is now made toFIG.13.FIG.13is a block diagram of an electronic design automation (EDA) system1300for designing the integrated circuit layout design, in accordance with some embodiments of the present disclosure. EDA system1300is configured to implement one or more operations of the method1200disclosed inFIG.12, and further explained in conjunction withFIGS.2A-11. In some embodiments, EDA system1300includes an APR system.

In some embodiments, EDA system1300is a general purpose computing device including a hardware processor1320and a non-transitory, computer-readable storage medium1360. Storage medium1360, amongst other things, is encoded with, i.e., stores, computer program code (instructions)1361, i.e., a set of executable instructions. Execution of the computer program code (instructions)1361by hardware processor1320represents (at least in part) an EDA tool which implements a portion or all of, e.g., the method1200.

The processor1320is electrically coupled to computer-readable storage medium1360via a bus1350. The processor1320is also electrically coupled to an I/O interface1310and a fabrication tool1370by bus1350. A network interface1330is also electrically connected to processor1320via bus1350. Network interface1330is connected to a network1340, so that processor1320and computer-readable storage medium1360are capable of connecting to external elements via network1340. The processor1320is configured to execute computer program code1361encoded in computer-readable storage medium1360in order to cause EDA system1300to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor1320is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium1360is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium1360includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium1360includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).

In one or more embodiments, storage medium1360stores computer program code1361configured to cause EDA system1300(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1360also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1360stores library1362of standard cells including such standard cells as disclosed herein, for example, a cell including word lines WL discussed above with respect toFIG.1.

EDA system1300includes I/O interface1310. I/O interface1310is coupled to external circuitry. In one or more embodiments, I/O interface1310includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor1320.

EDA system1300also includes network interface1330coupled to processor1320. Network interface1330allows EDA system1300to communicate with network1340, to which one or more other computer systems are connected. Network interface1330includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more EDA systems1300.

EDA system1300also includes the fabrication tool1370coupled to the processor1320. The fabrication tool1370is configured to fabricate integrated circuits, including, for example, the memory device100illustrated inFIG.1, the memory device200illustrated inFIGS.2A-2B, the memory device400illustrated inFIGS.4A-4B, the memory device600illustrated inFIG.6, and the memory device800illustrated inFIG.8, based on the design files processed by the processor1320and/or the IC layout designs as discussed above.

EDA system1300is configured to receive information through I/O interface1310. The information received through I/O interface1310includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor1320. The information is transferred to processor1320via bus1350. EDA system1300is configured to receive information related to a UI through I/O interface1310. The information is stored in computer-readable medium1360as user interface (UI)1363.

In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system1300. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.

In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, for example, one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.

FIG.14is a block diagram of IC manufacturing system1400, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using IC manufacturing system1400.

InFIG.14, IC manufacturing system1400includes entities, such as a design house1410, a mask house1420, and an IC manufacturer/fabricator (“fab”)1430, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1440. The entities in IC manufacturing system1400are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1410, mask house1420, and IC fab1430is owned by a single larger company. In some embodiments, two or more of design house1410, mask house1420, and IC fab1430coexist in a common facility and use common resources.

Design house (or design team)1410generates an IC design layout diagram1411. IC design layout diagram1411includes various geometrical patterns, for example, an IC layout design depicted inFIGS.3,5,7and/orFIGS.9-11designed for an IC device1440, for example, integrated circuits including the memory device200,400,600and800discussed above with respect toFIGS.2A-2B,FIGS.4A-4B,FIG.6, and/orFIG.8. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1440to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1411includes various IC features, such as an active region, gate electrode, source and drain, conductive segments or vias of an interlayer interconnection, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1410implements a proper design procedure to form IC design layout diagram1411. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1411is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1411can be expressed in a GDSII file format or DFII file format.

Mask house1420includes mask data preparation1421and mask fabrication1422. Mask house1420uses IC design layout diagram1411to manufacture one or more masks1423to be used for fabricating the various layers of IC device1440according to IC design layout diagram1411. Mask house1420performs mask data preparation1421, where IC design layout diagram1411is translated into a representative data file (“RDF”). Mask data preparation1421provides the RDF to mask fabrication1422. Mask fabrication1422includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1423or a semiconductor wafer1433. The IC design layout diagram1411is manipulated by mask data preparation1421to comply with particular characteristics of the mask writer and/or requirements of IC fab1430. InFIG.14, data preparation1421and mask fabrication1422are illustrated as separate elements. In some embodiments, data preparation1421and mask fabrication1422can be collectively referred to as mask data preparation.

In some embodiments, data preparation1421includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram1411. In some embodiments, data preparation1421includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, data preparation1421includes a mask rule checker (MRC) that checks the IC design layout diagram1411that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1411to compensate for limitations during mask fabrication1422, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, data preparation1421includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1430to fabricate IC device1440. LPC simulates this processing based on IC design layout diagram1411to create a simulated manufactured device, such as IC device1440. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1411.

It should be understood that the above description of data preparation1421has been simplified for the purposes of clarity. In some embodiments, data preparation1421includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1411according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1411during data preparation1421may be executed in a variety of different orders.

After data preparation1421and during mask fabrication1422, a mask1423or a group of masks1423are fabricated based on the modified IC design layout diagram1411. In some embodiments, mask fabrication1422includes performing one or more lithographic exposures based on IC design layout diagram1411. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1423based on the modified IC design layout diagram1411. Mask1423can be formed in various technologies. In some embodiments, mask1423is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (for example, photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1423includes a transparent substrate (for example, fused quartz) and an opaque material (for example, chromium) coated in the opaque regions of the binary mask. In another example, mask1423is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1423, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1422is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1433, in an etching process to form various etching regions in semiconductor wafer1433, and/or in other suitable processes.

IC fab1430includes wafer fabrication1432. IC fab1430is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1430is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

IC fab1430uses mask(s)1423fabricated by mask house1420to fabricate IC device1440. Thus, IC fab1430at least indirectly uses IC design layout diagram1411to fabricate IC device1440. In some embodiments, semiconductor wafer1433is fabricated by IC fab1430using mask(s)1423to form IC device1440. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram1411. Semiconductor wafer1433includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer1433further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

In some embodiments, a memory device is disclosed. The memory device includes a first word line and a second word line. The first word line is configured to transmit a first word line signal to a first set of memory cells. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. The third portion of the first word line is overlapped with the second portion of the first word line. The second word line is configured to transmit a second word line signal to a second set of memory cells. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.

In some embodiments, the third metal layer is between the first metal layer and the second metal layer.

In some embodiments, a width of the third portion of the first word line is smaller than a width of the second portion of the first word line.

In some embodiments, the width of the third portion of the first word line is smaller than a width of the first portion of the first word line.

In some embodiments, the second portion of the second word line includes a plurality of segments that are separated from each other. The at least one part of the second portion of the first word line is disposed between two of the plurality of segments, in a layout view.

In some embodiments, widths of the plurality of segments of the second portion of the second word line are substantially equal to each other.

In some embodiments, the widths of the plurality of segments of the second portion of the second word line is smaller than a width of the first portion of the second word line.

Also disclosed is a memory device which includes a first word line, a second word line, a third word line and a fourth word line. The first word line is configured to transmit a first word line signal to a first set of memory cells arranged in a first row. A first portion of the first word line is formed in a first metal layer, and a second portion of the first word line is formed in a second metal layer above the first metal layer. The second word line is configured to transmit a second word line signal to a second set of memory cells arranged in a second row. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. A third portion of the second word line is formed in a third metal layer above the second metal layer. Fourth portions of the second word line are formed in a fourth metal layer between the second metal layer and the third metal layer. The third word line is configured to transmit a third word line signal to a third set of memory cells arranged in a third row. A first portion of the third word line is formed in the first metal layer, and a second portion of the third word line is formed in the second metal layer. The fourth word line is configured to transmit a fourth word line signal to a fourth set of memory cells arranged in a fourth row. A first portion of the fourth word line is formed in the first metal layer. A second portion of the fourth word line is formed in the second metal layer. A third portion of the fourth word line is formed in the third metal layer.

In some embodiments, the fourth portions of the second word line are separated from each other in a first direction and extend along a second direction.

In some embodiments, the fourth portions of the second word line are disposed in parallel to each other.

In some embodiments, the fourth portions of the second word line have the same areas.

In some embodiments, the second portion of the second word line includes a plurality of segments that are separated from each other.

In some embodiments, an amount of the plurality of segments is substantially equal to or greater than an amount of the first set of memory cells or the second set of memory cells arranged in a column and the first row or the second row.

In some embodiments, the plurality of segments of the second portion of the second word line extend in a first direction. A protruding part of the second portion of the first word line extends in a second direction, and is disposed between two of the plurality of segments, in a layout view.

In some embodiments, in the layout view, the protruding part of the second portion of the first word line and the plurality of segments are partially overlapped with the third portion of the second word line.

In some embodiments, the first portion and the second portion of the first word line have sizes that are different from each other. The first portion, the second portion and the third portion of the second word line have sizes that are different from each other. The first portion and the second portion of the third word line have sizes that are different from each other. The first portion, the second portion and the third portion of the fourth word line have sizes that are different from each other. Sizes of the second portion of the first word line and the second portion of the third word line are substantially the same, and are different from sizes of the second portion of the second word line and the second portion of the fourth word line that are substantially the same. The first word line, the second word line, the third word line, and the fourth word line have equivalent resistances that are substantially the same.

In some embodiments, the fourth portions of the second word line are partially overlapped with the second portion of the first word line, the second portion of the second word line, and the third portion of the second word line, in a layout view.

Also disclosed is a memory device which includes a first portion of a first word line, a first portion of a second word line, a second portion of the first word line, a second portion of the second word line, third portions of the second word line, and a fourth portion of the second word line. The first portion of the first word line and the first portion of the second word line are formed in a first metal layer. The second portion of the first word line and the second portion of the second word line are formed in a second metal layer above the first metal layer. The third portions of the second word line are formed in a third metal layer between the second metal layer and a fourth metal layer that is above the second metal layer. The fourth portion of the second word line is formed in the fourth metal layer. The first portion and the second portion of the first word line have sizes that are different from each other, and at least two of the first portion, the second portion, the third portions and the fourth portion of the second word line have sizes that are different from each other. At least one part of the second portion of the first word line is disposed between two segments of the second portion of the second word line that are separated from each other.

In some embodiments, widths of the two segments of the second portion of the second word line are substantially equal to each other.

In some embodiments, the two segments of the second portion of the second word line extend in a first direction, and the at least one part of the second portion of the first word line extends in a second direction, in a layout view. The second direction and the first direction are perpendicular to each other.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.