Patent ID: 12243933

The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schematically and not to scale. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.

DETAILED DESCRIPTION

FIG.4shows a top view of the first exemplary embodiment of a semiconductor transistor cell1.FIGS.5A-Bshow more specific details in cross sections at different cut lines as depicted inFIG.4, in form of a punch through insulated gate bipolar transistor (IGBT) with a four-layer structure (pnpn). The layers are arranged between an emitter electrode3on an emitter side31and a collector electrode2on a collector side21, which is arranged opposite of the emitter side31in a first direction X. The IGBT transistor cell comprises an (n−) doped drift layer4, which is arranged between the emitter side31and the collector side21, and a p doped first base layer9arranged on the emitter side31of the drift layer4, and extending into the drift layer4in the X direction. The transistor cell1also comprises an n doped source region7, which is arranged at the emitter side31embedded into the first base layer9, and directly contacting the emitter electrode3. The source region7has a higher doping concentration than the drift layer4. Both the source region7and the first base layer9are shaped as a square in a top view plane defined by the Y-Z directions.

The innovative power semiconductor transistor cell1further comprises a p doped second base layer8, which is arranged between the first base layer9and the emitter electrode3, which second base layer8is in direct electrical contact to the emitter electrode3. The second base layer8has a higher doping concentration than the first base layer9. The second base layer8extends in the X direction deeper than the source region, and is shaped as a square in the same top plane view. In the direction Y, the first edge of the second base layer is spaced apart by a separation region60from the singular point100of the source region7. The separation region60has a length that can be substantially 0 as represented inFIG.5A, can be larger than 0 as represented inFIG.17A, or can be negative (not shown).

Furthermore, a plurality of first gate electrodes11are embedded in corresponding trench recesses, each electrode11being electrically insulated from the first base layer9, the second base layer8, the source region7and the drift layer4by a first insulating layer12′. The first gate electrodes11extend both in the Y and Z directions, and are arranged at an angle of 90 degrees with respect to the sides of the square cell, when observed in the top view plane. The trench recesses intersect both the source region7and the second base layer8, i.e. the first end trench wall90of the first gate electrodes is arranged in the source region7.

A second insulation layer12is arranged on the emitter side31, protecting the surface of the drift layer4, of the first base layer9and of the source region7. The layer12can also be used as a masking layer for the implantation of ions forming the source region7and the first base layer9.

The first base layer9and the source region7are usually formed by subsequent steps of implanting ion dopants through a mask such as the polysilicon gate cell opening. Each ion implant step is followed by thermal annealing and activation of the dopants. Because the two layers7and9have opposite dopant types, the out-diffusion of dopants will locally compensate in all three directions X, Y, Z leading to the formation of a main p-n junction.

For silicon-based drift layers, this is depicted schematically inFIG.5A, where it can be seen that the source region7will feature a singular point100closest to the edge of the second insulating layer12, which is used as masking layer for implanting ions of the source region7and first base layer9. At the singular point100, the surface doping concentration of the source region7reaches a maximum value, after which is starts to decrease towards the p-n junction it forms with the first base layer9. The singular point100is a key feature of the power semiconductor device, as it defines the source region7and first base layer9, and subsequently other key MOS parameters such as the channel width, channel length, threshold voltage, and the maximum doping concentration for supplying the electron charge carriers from the source region7.

Additionally, gate runners11′ are formed outwards of the first base layer9, with the purpose of interconnecting the first gate electrodes11. The gate runners11′ can be formed with trench recesses, similar or different than the trench recesses of the first gate electrodes11. The gate runners11′ can also be formed with planar electrodes, as will be described at a later point.

The power semiconductor device according to the first exemplary embodiment further comprises a p-doped collector layer6arranged between a buffer layer5and the collector electrode2, which collector layer6is in direct electrical contact to the collector electrode2. An n-doped buffer layer5is arranged between the collector layer6, and the drift region4. A third insulation layer13is arranged between the emitter electrode3, the first gate electrodes11, and the gate runners11′.

The emitter electrode3and the insulating layer13are omitted in most of the Figures showing top plane views, in order to better facilitate the visualisation of the underlaying structures.

In the first exemplary embodiment depicted inFIG.4, and cross sectionsFIG.5A-B, a voltage applied on the first gate electrodes11initiates the formation of an inversion layer in the first base layer9. If a positive voltage is applied, with a value above a threshold value, the inversion channel is formed only on the active lateral trench walls40, except in the regions abutting the highly doped second base layer8, which has higher dopant concentration than the first base layer9. No surface inversion layer is formed on the emitter side31of the first base layer9. This aspect represents a paradigm shift in the design and functionality of power semiconductors, as it changes the rules known to, and used by, the experts in the field, in relation to MOS channel sizing and its operation.

In the first embodiment, at least one of the following features or any combination of features is included:the gate runners11′ are embedded in trench recesses formed on the emitter side31simultaneously with the first gates11, therefore having similar geometry of the trench recesses, and similar electrode and insulating layers as shown inFIG.5A-B; or,the gate runners11′ are embedded in trench recesses formed with different processes than the first gates11, therefore having different geometry of the trench recesses, and different electrode and insulating layers (not shown); or,the gate runners11′ are formed as planar electrodes on the emitter side31of the drift layer4, and separated from the drift layer4by the second insulating layer12, as shown inFIG.6A-B.

In a second exemplary embodiment shown inFIG.7, the dimension81of the square shape of the source region7is much larger than the width80of the trench recesses of the first gate electrodes11. Consequently, a plurality of first gate electrodes11can be formed on each side of the square cell, and furthermore, a different number of first gate electrodes can be formed in the Y and Z directions if needed. Such an arrangement permits minimizing the separation between trench regions to sub-micron dimensions, which in turn, is expected to increase the electron-hole plasma concentration in the active transistor cell.

In a third exemplary embodiment shown inFIG.8, the dimension81of the square form shaping the source region7is further miniaturized, limited only by the capabilities of the current lithography systems. At a certain point, the dimension81of the source region7becomes comparable with the width80of the trench recesses, so that only one first gate electrode11can be formed on each side of the source region7. This method of ultimate miniaturization of the transistor cell can open up new design approaches, not only for power semiconductors, but also for ICs.

In a fourth exemplary embodiment shown inFIG.9, a second gate electrode10is formed on the emitter side31of the drift layer4, separated from the drift layer4, the first base layer9, and the source region7by a second insulating layer12. The second gate electrode10can then ensure the electrical connectivity between the first gate electrodes11, so that no additional gate runners11′ are required. The advantage of this fourth exemplary embodiment resides in the formation of an additional planar MOS channel in the transistor cell, which can be better understood inFIG.10A-B. However, it may be that in certain designs it is desirable to electrically disconnect some of the first gate electrodes11from portions of the second gate electrodes10, in order to optimize certain static or dynamic functional parameters. In this case, additional gate runners11′ are required, and can be formed as described previously (not shown). Another advantage of the fourth exemplary embodiment resides in simplifying the manufacturing process, in particular reducing the number of masks needed to structure the source region7and the first base layer9. This is because the second gate electrode10can be used as a mask for ion implantation.

A further fifth exemplary embodiment is shown inFIG.11wherein, the source region7, the first base layer8, and the second base layer9are formed in the shape of elongated rectangles, i.e., one side of the rectangle is substantially larger than the other side of the rectangle. The first gate electrodes11are formed with stripes that can be interrupted or continuous over the stripes of the source region7. The electrode of the additional gate runners11′ can contact the first gate electrodes11at the cross points thereof. Not all first gate electrodes11must be contacted by the gate runner11′. As described previously in the first exemplary embodiment, the gate runner11′ can be formed as a trench recess embedding an electrode, or as a planar electrode.

FIG.12Adepicts a sixth exemplary embodiment, wherein a planar second gate electrode10is formed on the emitter surface31of the drift layer4. The second gate electrode10acts as an interconnecting layer for the plurality of first gate electrodes11, thus no additional gate runners11′ are required. The trench regions embedding the first gate electrodes11can be continuous as depicted inFIG.12A, meaning that both trench end walls90of the trench regions are abutting source regions7. The trench regions embedding the first gate electrodes11can also be interrupted, as depicted inFIG.12Bshowing a seventh exemplary embodiment, wherein a first end90of the trench region is abutting a source region7, and the second end90′ of the same trench region is formed in the drift layer4. The main advantage of having interrupted first gate electrodes11resides in reducing the overall capacitance of the semiconductor device.

A further eighth exemplary embodiment is depicted inFIG.13A, wherein the multi-cell arrangement includes source regions7shaped as stripes, and first gate electrodes11interrupted in their longitudinal direction. This arrangement is more clearly understood inFIG.13Band reduces the gate-collector capacitance of the multi-cell transistor arrangement. Similar as the trench end wall90, the trench end wall90′ can be also formed within the first base layer9as depicted inFIGS.13C-F. The additional variations indicated in theFIG.13C to13Fdepict arrangements of the gate runners11′ as planar electrodes, contacting the first gate electrodes11, and overlapping the first base layer9in different configurations.

A ninth exemplary embodiment depicted inFIG.14, wherein the source regions7are shaped with stripes, the first gate electrodes11are interrupted along their longitudinal direction, and a planar second gate electrode10is formed on the emitter side31interconnecting the plurality of first gate electrodes11.

With respect to theFIGS.13A and14, the critical design aspects are the dimension Wtor mesa between the trenches in the Z direction, as well as the dimension Wprepresenting the distance from a trench end wall90of a first gate electrode11to a trench end wall90of the adjacent first gate electrode in the Y direction. Improved carrier storage/reduced hole drainage is expected as the dimensions Wtand Wpare reduced. The value of Wtmay be in a range from about 5 μm to below 0.1 μm, more preferably from 1 μm to 0.1 μm—which is achievable with the proposed design because no additional structures have to be lithographically defined in between the trench recesses of the first gate electrodes11. Also, improved carrier storage/reduced hole drainage is expected by reducing the distance Wp. More specifically, Wpcould extend approximately in a range from about 20 μm to about 1 μm, preferably from 5 μm to 1 μm, and more preferably from 2 μm to 1 μm.

Previous exemplary embodiments depicted the use of gate runners11′ formed outside of the first base layer9, i.e., not abutting the first base layer9. However, it would be possible to have a layout wherein, the gate runner11′ is formed abutting the first base layer9, as depicted in the tenth exemplary embodiment ofFIG.15. This is more clearly understood in the cross sections depicted inFIGS.16A and16B, for the case where the gate runner11′ is formed with a trench recess. It is also possible to substantially embed the trench recess of the gate runner11′ in the first base layer9by reducing its geometrical dimensions (not shown).

FIGS.17A-Bdepict cross sections through an eleventh exemplary embodiment of the invention, wherein a separation region60with a length greater than zero spaces apart, in the Y direction, the first edge of the second base layer8, from the singular point100of the source region7. As explained previously, this distance can be negative or positive. When it is positive, it means that the second base layer8does not fully protect the bottom side of the source region7as indicated in theFIG.17A. In this eleventh embodiment, the trench recesses of the first gate electrodes11abut the source region7, but not the second base layer8. In a similar manner to the first exemplary embodiment, an inversion layer can be formed on the lateral trench walls40, and on the first end wall90of the trench regions in contact with the first base layer9. This significantly increases the width of the MOS channel. However, when the length of the separation region60is greater than 0, the highly doped second base layer8does not fully protect the bottom side of the source region7, which may create issues with the Reverse Blocking Safe Operating Area (RB-SOA), i.e., the source region7may become forward biased, and may inject electron charge carriers in the drift layer4, leading to a latch up phenomena.

In previous exemplary embodiments, the first end90of the trench recesses of the first gate electrodes11was abutting the source region7. It is also possible that the first end90of the trench recesses does not abut the source region7.FIG.18shows a twelfth exemplary embodiment, wherein an additional planar extension region11″ of the first gate electrodes11is required to ensure the formation of a MOS channel between the source region7, the first base layer9, and the drift layer7. The additional gate runner11′ is used to ensure the electrical connectivity between the plurality of the first gate electrodes11.

Alternatively, and requiring a simplified method of processing as for the twelfth embodiment, theFIG.19shows a thirteenth exemplary embodiment, wherein a planar second gate electrode10is formed on the emitter side31of the drift layer4, and connects electrically the first gate electrodes11. The advantage of the thirteenth exemplary embodiment is better understood inFIG.20A-B, depicting cross sections of an active cell with a planar MOS channel15, in addition to MOS channels formed on the lateral walls of the trench recesses of the first gate electrodes11. The planar second gate electrode10can be used as a mask for ion implantation steps when forming the first base layer9and the source region7.

FIG.21depicts a fourteenth exemplary embodiment, which is similar to the first exemplary embodiment with the exception of the direction of the first gate electrodes11. In the fourteenth exemplary embodiment, the first gate electrodes11are formed in such a manner that they intersect the corners of the square shape defining the source region7in the top view plane. This may provide certain benefits if the drift layer4is formed of materials with strong dependence between their electrical properties and the crystallographic directions, such as Silicon Carbide.FIG.22depicts a fifteenth exemplary embodiment, wherein a planar second gate electrode10is formed on the surface of the emitter side31, and replaces the additional gate runners11′ fromFIG.21.

FIG.23shows a sixteenth exemplary embodiment of a transistor active cell, wherein the gate runner11′ abuts two adjacent, non-interrupted first gate electrodes11. However, it should be understood that the first gate electrodes11can be interrupted in a region further away from the active cell, i.e., further away from the source region7, first base layer9, and second base layer8.FIG.24depicts a seventeenth exemplary embodiment, wherein a planar second gate electrode10is formed on the surface of the emitter side31, and replaces the additional gate runner11′ fromFIG.23.

As explained previously, multiple active cells must be arranged on a semiconductor wafer of a starting material to form a fully functional semiconductor device. In addition to the active cells, the fully functional semiconductor device may comprise other regions, such as a junction termination region required for achieving voltage blocking capabilities.

In terms of arranging multiple active cells, various layouts can be considered. For example, in addition to the stripe layouts depicted inFIG.13A,FIG.14, it can be possible to arrange square cells according to the first exemplary embodiment, in a regular cellular layout as depicted inFIG.25, orFIG.27, depending on, whether or not the first end90of the first gate electrodes11abuts the source region7. Similarly,FIG.26andFIG.28depict square cell layouts for the case of using a planar second gate electrode10, depending on whether or not the first end90of the first gate electrodes11abuts the source region7, respectively.

Furthermore,FIG.29,31,33show other exemplary embodiments of multi-cell arrangements of octagonal or hexagonal transistor cells, interconnected by an additional gate runner11′. One of the benefits of such arrangements resides in the increased number of first gate electrodes11, and implicitly an increase of the MOS channels that can be formed per unit area. InFIG.31for example, the number of octagonal active cells is reduced in comparison withFIG.29, in order to better control the short circuit capability.

FIGS.30,31and34show further exemplary embodiments of multi-cell arrangements of octagonal or hexagonal transistor cells, interconnected by a planar second electrode10which substantially covers the regions in between the active cells. Due to the presence of the second gate electrode10, there will be additional planar MOS channels15formed at the emitter side31in the first base layer9. However, the gate-collector capacitance of the device may be increased due to the large area of the second gate electrode10. It is nonetheless understood, that the second gate electrode10does not have to be a layer uniformly covering the emitter side31of the device, as depicted inFIG.30, or32or34. The second gate electrode10can also be omitted in regions where it does not overlap significantly with, for example, the first base layer9.

In order to address possible short circuit operating conditions, it may also be possible to structure the transistor active cells1in such a manner, that the source region7is omitted in between multiple adjacent trench regions of first gate electrodes11.

A further embodiment is a reverse conducting type of power semiconductor, wherein the collector layer2may be formed of alternating regions of p doped6and n doped18material. In this case, there will be a diode formed in parallel with the transistor in the same cell. The performance of the diode part will be heavily influenced by the emitter side structure of the transistor cell. With the embodiments disclosed in this patent application, it will be possible to better control the trade-off performance curves for the diode part, without negatively affecting the transistor part.

In a further embodiment, an n doped enhancement layer17may be arranged between the drift layer4and the first base layer9, with the purpose of further enhancing the electron-hole plasma concentration at the emitter side31. To achieve this effect, the doping of the layer17may be larger than the doping of the drift layer4.

The second gate electrode10may be grounded or left floating. Consequently, no inversion layer can be formed at the emitter side31of the first base layer9, under the second gate electrode10. Because there is no electrical connection to the first gate electrodes11, the operation of the first gate electrodes11remains independent from second gate electrodes10, and follows the same phenomenon as a described previously, with the electrons flowing along the lateral walls40of the trench regions when the voltage applied to the gate electrodes11is greater than a threshold value.

In other embodiments, the material of the drift layer may be different than Silicon, for example it may be made of Silicon Carbide, Gallium Nitride, Gallium Oxide, Zinc Oxide or the like. In this case, the same embodiments as described above can be applied, however the specific dimensions and dopant profiles have to be adjusted accordingly by means known to those expert in the field. More specifically, if the drift layer is made of Silicon material, the trench regions may extend vertically to a depth approximately in a range from about 2 μm to about 7 μm. The trench width may range from about 3 μm to about 0.5 μm. However, if the drift layer comprises wide band gap materials such as Silicon Carbide or Gallium Nitride or Gallium Oxide or Zinc Oxide, the depth and width of the trench recesses have different dimensions than above, for example the depth can be also smaller than 2 μm.

In addition, for some of the additional embodiments comprising wide bandgap materials, the buffer layer5and the collector layer6may be omitted, in particular if the power semiconductor device is a MOSFET device with unipolar conduction i.e., majority charge carriers only.

Furthermore, in other embodiments it may be possible that the power semiconductor is made of a multitude of different transistor cells, but not all cells may be of the same design. For example, the power semiconductor device may be formed with some transistor cells having the first exemplary embodiment, and with some transistor cells having a different design covered in the previous embodiments, or in the prior art.

It is also possible to apply the invention to power semiconductor devices, in which the conductivity type of all layers is reversed, i.e., with a lightly p doped drift layer etc.

In most applications, power semiconductors are not used in bare die form. Therefore, in a further embodiment to this patent application, multiple power semiconductors of any of the previous embodiments may be mounted as single or parallel connected chips on a substrate using techniques such as soldering or sintering. An additional enclosure, protective layers, sensors, and internal/external metal connectors are usually added to form the basis for a power module, with the role of protecting the power semiconductors from damaging environmental factors (mechanical pressure, humidity, high temperatures, electrical discharges etc).

The power modules may be subsequently used in power converters that control the flow of electrical current between a source and a load. The source may be a DC type battery for example, and the load may be an electrical motor. Typical converter topologies that could make use of semiconductor devices with transistor cells according to any previous exemplary embodiments are two-, three- or other multi-level converters, H-bridge or resonant switching.

REFERENCE LIST

1: inventive power semiconductor device cell layout3: emitter metallization (electrode)31: emitter side2: collector metallization (electrode)21: collector side4: drift layer, substrate5: buffer layer6: collector layer7: n source layer8: p second base layer9: p first base layer10: second gate electrode, electrically conductive layer10′: only when the second gate electrode is formed, represents the first gate electrode regions not covered by the second gate electrode11: first gate electrode, electrically conductive layer11′: gate runner, electrically conductive layer11″: planar extension of the first gate electrode, electrically conductive layer12: second insulating layer12′: first insulating layer13: third insulating layer14: emitter contact opening15: horizontal channel for planar gate16: vertical channel for trench gate17: enhancement layer18: collector shorts40: active lateral trench wall i.e., inversion layer is formed, and there is contact with the source region50: separation region between the singular point100and the highest doping concentration region in the first base layer (in the Y dimension)60: separation region between the singular point100and the first edge of the second base layer (in the Y dimension)80: trench width81: width of transistor cell side90: first end trench wall90′: second end trench wall100: singular point close to the edge of the mask for source region ion implantation, where the surface doping concentration in the source region reaches a maximum value200,201: planar MOS cell power semiconductor devices (prior art)300,301,302: trench MOS cell power semiconductor devices (prior art)