Patent ID: 12199033

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “top metal layer” may be used herein to refer to the metal layer of an integrated circuit chip (or simply “chip”) most distal a substrate of the chip, and/or the metal layer of the chip above which no further metal layers are formed. The term “bottom metal layer” may be used herein to refer to the metal layer of the chip most proximal the substrate, and/or the metal layer of the chip having no metal layer between itself and the substrate. The term “intermediate metal layer” may be used herein to refer to any metal layer between the top metal layer and the bottom metal layer.

The term “upper conductive via” may be used herein to refer to any conductive via in direct contact with the top metal layer. The term “intermediate conductive via” may be used herein to refer to any conductive via not having a direct contact with the top metal layer.

On-chip inductor quality factor is closely correlated with various desirable performance metrics in integrated circuit design, including but not limited to radio frequency sideband rejection and voltage controlled oscillator phase noise reduction. Substrate loss and self-resonance are two environmental challenges that obstruct designers' ability to produce on-chip inductors exhibiting high quality factor. Increase in oxide capacitance Cox, the capacitance between the inductor and the substrate over which it is formed, effectively reduces both the substrate loss and the self-resonance. Oxide capacitance Coxis inversely proportional to oxide thickness tox, suggesting that quality factor can be increased by increasing oxide thickness toxof the inductor.

Various embodiments of integrated circuit structures and process flows directed toward increasing oxide thickness toxwith a view to reducing substrate loss factor and self-resonance factor to increase quality factor of on-chip inductors are described below. In some embodiments, oxide thickness toxis increased by extending an upper conductive via through at least two dielectric layers. In some embodiments, the oxide thickness is further increased by extending the upper conductive via through at least one etch stop layer positioned between the at least two dielectric layers. Q factor for a 0.5 nano-Henry on-chip inductor is greater than about 22 when using the structures and processes described herein.

FIG.1is a top view of inductor circuit10in accordance with some embodiments. Inductor circuit10is an on-chip inductor in a chip. Inductor circuit10is fabricated in an integrated circuit fabrication process. Inductor circuit10is on a substrate of the chip. In some embodiments, the substrate is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped with a p-type or an n-type dopant or undoped. In some embodiments, the substrate is a wafer, such as a silicon wafer. An SOI substrate generally includes a layer of semiconductor material formed on an insulator layer. In some embodiments, the insulator layer is a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. In some embodiments, a multi-layered or gradient substrate is used. In some embodiments, the semiconductor material of the substrate includes silicon and/or germanium. In some embodiments, the semiconductor material is a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. In some embodiments, the substrate is an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. Combinations of the above may be utilized as the substrate in some embodiments.

The substrate will generally include integrated circuit devices (not shown). In some embodiments, the integrated circuit devices include transistors, diodes, capacitors, resistors, the like, or combinations thereof formed in and/or on the substrate. The integrated circuit devices may be formed using any suitable methods.

The inductor circuit10includes an inductor100having any suitable shape or architecture. In some embodiments, the inductor100may be a symmetrical or generally symmetrical spiral inductor100having an octagonal-shaped coil (or simply “coil”)130. First trace141and first pad142, and second trace143and second pad144provide input and output electrical signal connection to coil130. In some embodiments, first guard ring segment110and second guard ring segment120partially surround spiral inductor100, as shown inFIG.1. In some embodiments, the first guard ring segment110and/or second guard ring segment120may be omitted. In some embodiments, coil130is formed at least partially in the top metal layer of the chip. Forming coil130in the top metal layer can reduce parasitic capacitances, which are generally inversely proportional to the distance, or “oxide thickness” (tox), between the coil and the substrate over which the coil is formed.

Throughout the description, reference to inductor circuit10is not limited to the symmetrical spiral inductor architecture shown inFIG.1. Other inductor architectures including at least asymmetrical spiral inductors may be utilized as the inductor100in the inductor circuit10in various embodiments, and the techniques described for improving inductor Q factor are applicable to the other inductor architectures without significant modification envisioned. Symmetrical spiral inductors generally trade off lower self-resonant frequency against higher inductance, higher Q factor and lower series resistance.

Other inductor shapes including at least hexagonal, square or circular may be utilized as the inductor100in the inductor circuit10in various embodiments, and the techniques described for improving inductor Q factor are applicable to the other inductor shapes without significant modification envisioned. Whereas circle-shaped inductors exhibit favorable Q factor, few or no semiconductor fabrication processes support shapes employing curved sides. Square-shaped inductors are generally more compact, easily manufactured, and exhibit higher inductance for a given area, but suffer lower Q factor. Octagonal-shaped and hexagonal-shaped inductors strike a desirable balance between manufacturability, Q factor and inductance. Again, any of the shapes will benefit from application of the Q factor enhancing techniques described herein. Other examples of a substantially closed geometric pattern would include a box-within-a-box pattern (square or rectangular) or other polygon spiral pattern, an irregularly shaped spiral pattern, nested parallelogram or polygon patterns, and the like.

In some embodiments, inductor circuit10has a Q factor of greater than about 21, greater than about 22, greater than about 23, or greater than about 24. In some embodiments, inductor circuit10has inductance of less than about 1 nano-Henry, less than about 0.5 nano-Henries, or less than about 0.1 nano-Henries. Lower inductance can be desirable to achieve higher operating frequency.

Spiral inductor100of inductor circuit10includes coil130, first trace141, first pad142, second trace143and second pad144.

First coil segment131of coil130is a first outer ring segment of coil130. In some embodiments, first coil segment131includes at least 3 bends, at least 4 bends or at least 5 bends. A “bend” as described herein can refer to a change in direction of a segment of the coil130. A circular inductor would thereby have infinite bends, and a polygonal inductor would have some finite number of bends. In some embodiments, first coil segment131is monolithically formed with first trace141. In some embodiments, first coil segment131is electrically connected to first trace141by way of a conductive via.

Second coil segment132is an inner ring segment of coil130. In some embodiments, second coil segment132includes at least 4 bends, at least 6 bends or at least 8 bends. In some embodiments, second coil segment132is monolithically formed with first coil segment131and/or first trace141, or electrically connected thereto by way of a conductive via.

Third coil segment133is a first bridge segment electrically connected to first coil segment131and second coil segment132. In some embodiments, third coil segment133is monolithically formed with first coil segment131and second coil segment132, or electrically connected thereto by way of a conductive via.

Fifth coil segment135is a second outer ring segment of coil130. In some embodiments, fifth coil segment135includes at least 3 bends, at least 4 bends, or at least 5 bends. In some embodiments, fifth coil segment135is monolithically formed with second trace143. In some embodiments, fifth coil segment135is electrically connected to second trace143by way of a conductive via.

Fourth coil segment134is a second bridge segment electrically connected to fifth coil segment135and second coil segment132. Fourth coil segment134crosses under third coil segment133, and is electrically isolated from third coil segment133. In some embodiments, fourth coil segment134is formed in at least one intermediate metal layer.

Sixth coil segment136is a first intermetal connection region partially overlapping second coil segment132and fourth coil segment134. In some embodiments, sixth coil segment136includes one or more conductive vias and one or more metal contacts extending from second coil segment132to fourth coil segment134. Sixth coil segment136establishes an electrical connection between second coil segment132and fourth coil segment134.

Seventh coil segment137is a second intermetal connection region partially overlapping fifth coil segment135and fourth coil segment134. In some embodiments, seventh coil segment137includes one or more conductive vias and one or more metal contacts extending from fifth coil segment135to fourth coil segment134. Seventh coil segment137establishes an electrical connection between fifth coil segment135and fourth coil segment134.

In some embodiments, first pad142, first trace141, first coil segment131, third coil segment133, second coil segment132, fifth coil segment135, second trace143and second pad144(“the segments”) are formed in the top metal layer of the chip. In some embodiments, the segments are further formed in at least one intermediate metal layer and/or the bottom metal layer, the included metal layers in the segments being interconnected by conductive vias. Forming the segments in more than one metal layer reduces series resistance of spiral inductor100by effectively increasing cross-sectional area of the current path through the spiral inductor100(resistance is inversely proportional to cross-sectional area), which is desirable in some circuit applications.

In some embodiments, any of first pad142, first trace141, first coil segment131, third coil segment133, second coil segment132, fifth coil segment135, second trace143and second pad144includes at least one upper conductive via extending from the top metal layer through at least two dielectric layers. Each upper conductive via in spiral inductor100is a single, continuous structure. In some embodiments, formation of upper conductive vias is accomplished using no more than one electroless copper plating step.

First guard ring segment110and second guard ring segment120form a guard ring around coil130. The guard ring attenuates radio frequency noise emitted by coil130. The attenuation protects nearby circuits which may be sensitive to such electromagnetic interference generated by coil130.

FIG.2is a perspective view of adjacent bends of the inductor ofFIG.1in accordance with some embodiments.FIG.3is a circuit diagram of the inductor ofFIG.1in accordance with some embodiments. Two metal layers are shown inFIG.2for ease of illustration. Other embodiments may include more than two metal layers.

Inductor section20includes substrate240and dielectric layer230on a first side of substrate240. Portions of first coil segment131and second coil segment132are shown inFIG.2, as well as front and side cutaways. Equivalent circuit components including inductance330, resistance331, capacitance332, capacitance340, resistance350, and capacitance360are also shown overlaid on the perspective view inFIG.2for ease of description.

Equivalent circuit30shown inFIG.3is a pi-type lumped physical model for approximating electrical behavior of on-chip inductors, such as spiral inductor100.

Inductance330models series inductance of spiral inductor100. A first terminal of inductance330is electrically connected to a first terminal of capacitance332, a first terminal of capacitance340, and first interface terminal310. A second terminal of inductance330is electrically connected to a first terminal of resistance331.

Resistance331models series resistance of spiral inductor100. A first terminal of resistance331is electrically connected to the second terminal of inductance330. A second terminal of resistance331is electrically connected to a second terminal of capacitance332, a first terminal of capacitance341, and second interface terminal320.

Capacitance332represents series capacitance of spiral inductor100. Capacitance332generally models capacitive coupling in spiral inductor100. One type of capacitive coupling is shown inFIG.2between first coil segment131and second coil segment132. Overall capacitive coupling represented by capacitance332is generally thought to be dominated by the crossover of third coil segment133and fourth coil segment134of coil130shown inFIG.1. A first terminal of capacitance332is electrically connected to first interface terminal310, the first terminal of inductance330, and the first terminal of capacitance340. A second terminal of capacitance332is electrically connected to the second terminal of resistance331, the first terminal of capacitance341, and second interface terminal320.

Capacitance340and capacitance341model oxide capacitance of spiral inductor100distributed at first interface terminal310and second interface terminal320, respectively. The oxide capacitance of spiral inductor100is generally modeled as equally distributed: Cox1=Cox2=Cox. Capacitance340and capacitance341represent capacitance of dielectric layer230between first coil segment131and substrate240, and second coil segment132and substrate240, respectively.

Resistance350and resistance351model resistance of substrate240from dielectric layer230to biasing terminal370, corresponding to resistance from the second terminal of capacitance340to biasing terminal370and from the second terminal of capacitance341to biasing terminal370, respectively. Capacitance360and capacitance361model capacitance of substrate240from dielectric layer230to biasing terminal370, corresponding to capacitance from the second terminal of capacitance340to biasing terminal370and from the second terminal of capacitance341to biasing terminal370, respectively. Resistance350and resistance351are generally modeled as equally distributed: Rsub1=Rsub2=Rsub. Capacitance360and capacitance361are generally modeled as equally distributed: Csub1=Csub2=Csub.

Q factor of spiral inductor100is approximated by equivalent circuit30as:

Q=ω⁢LsRs×RpRp+[(ω⁢LsRs)2]⁢Rs×[1-Rs2(Ci+Cp)Ls-ω2⁢Ls(Ci+Cp)](1)Rp=1ω2⁢Cox2⁢Rsub+Rsub(Cox+Csub)2Cox2(2)Cp=Cox⁢1+ω2(C-ox+Csub)⁢Csub⁢Rsub21+ω2(Cox+Csub)2⁢Rsub2(3)

The middle term of (1) denotes what is generally known as the substrate loss factor, which is a number less than unity that approaches one as parasitic Rpdominates the second term in the denominator. Parasitic resistance Rpis expanded as (2). From (2), decreasing Coxincreases Rp. Increased Rpraises the substrate loss factor closer to one, which improves Q factor.

The third term of (1) denotes what is generally known as the self-resonance factor, which is also a loss factor less than unity. Parasitic capacitance Cpis expanded as (3). The self-resonance factor is increased if Cpis decreased. From (3), Cpis decreased when Coxis decreased.

Coxis generally obtained by:

Cox=12⁢lw⁢εoxtox(4)

From (4), Coxis directly proportional to inductor area lw and oxide permittivity εox, and inversely proportional to oxide thickness tox. Increased oxide thickness toxdecreases Cox, which reduces the substrate loss factor and the self-resonance factor, thereby increasing the Q factor. “Oxide thickness” generally refers to thickness of oxide, or other suitable dielectric, between spiral inductor100and the substrate. Oxide thickness may be measured as distance between a surface of spiral inductor100proximal the substrate and the substrate itself. One measure of oxide thickness in accordance with various embodiments is shown inFIG.4, labeled “tox.”

Use of an extended (e.g., taller or deeper) upper conductive via effectively increases oxide thickness toxby increasing distance between the inductor100and the substrate. To enhance inductor quality factor and overall device performance, in some embodiments, oxide thickness toxis increased by extending an upper conductive via through at least two dielectric layers. In some embodiments, the oxide thickness is further increased by extending the upper conductive via through at least one etch stop layer positioned between the at least two dielectric layers.

Structure210and structure220, each of which includes such an upper conductive via, are highlighted inFIG.2. Positioning of via213, an upper conductive via, among first metal line211and second metal line212of first coil segment131is shown inFIG.2.FIG.5nshows structure210in accordance with at least one embodiment. In some embodiments, first coil segment131includes at least ten, at least one hundred or more structures210distributed throughout first coil segment131. Structure220is included in second coil segment132. Structure220is highlighted to illustrate at a conceptual level positioning of via223among third metal line221and fourth metal line222of second coil segment132. In some embodiments, second coil segment132includes at least ten, at least one hundred or more structures220distributed throughout second coil segment132. In some embodiments, structures similar to structure210or structure220are included in first pad142, first trace141, third coil segment133, fifth coil segment135, second trace143and/or second pad144.

In some embodiments, an array of structures210or structures220is distributed throughout spiral inductor100, each structure210or structure220having width of about 0.1 micrometers to about 10 micrometers, length of about 0.1 micrometers to about 10 micrometers, and the array having pitch/spacing of about 0.1 micrometers to about 10 micrometers. Other embodiments may utilize greater or lesser length, width and/or array pitch/spacing. In some embodiments, structures210or structures220are distributed non-uniformly in one or more regions of spiral inductor100or inductor circuit10.

Via213is an upper conductive via. Via213is in direct contact with first metal line211and in direct contact with second metal line212. In some embodiments, via213is or comprises a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable method.

Via223is an upper conductive via. Via223is in direct contact with third metal line221and in direct contact with fourth metal line222. In some embodiments, via223is or comprises a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable method.

Various embodiments of integrated circuit structures and process flows directed toward increasing oxide thickness with a view to reducing substrate loss factor and self-resonance factor to increase quality factor of an on-chip inductor are described below. In some embodiments, oxide thickness is increased by extending an upper conductive via through at least two dielectric layers to increase distance between the inductor100and the substrate. In some embodiments, the oxide thickness is further increased by extending the upper conductive via through at least one etch stop layer positioned between the at least two dielectric layers. Q factor for an on-chip inductor of 0.5 nano-Henries is greater than about 22 when using the structures and processes described herein.

FIG.4is a diagram of a conductive stack40in accordance with some embodiments. Stack40is depicted showing metal features211,212,422,432,442,452,462,472,482, dielectric layers400,410,415,420,425,430,435,440,445,450,455,460,465,470,475,480,485, substrate240, and conductive vias213,421,431,441,451,461,471,481from a bottom metal layer, through various intermediate metal layers, to a top metal layer. Seven intermediate metal layers are shown inFIG.4. In some embodiments, fewer or more intermediate metal layers are utilized.

Seventeen dielectric layers are shown inFIG.4. For clarity of illustration, intervening functional layers, including etch stop layers, anti-reflective layers, and the like, are not depicted inFIG.4. In some embodiments, one or more functional layers are included between one or more of the dielectric layers. In some embodiments, dielectric layer410comprises at least dielectric layers511,512and functional layers501,502,503shown inFIG.5n. In some embodiments, dielectric layers420,430,440,450,460,470,480each have thickness less than thickness of dielectric layer410. In some embodiments, dielectric layers420,430,440,450,460,470,480have thickness less than 7 kilo-Angstroms.

Conductive feature482is a bottom metal layer contact in dielectric layer485. Via481is a bottom metal layer via in dielectric layer480and directly contacting conductive feature482. Via481and dielectric layer485are on substrate240. In some embodiments, no intervening metal layer exists between the surface of conductive feature482facing substrate240and substrate240.

Conductive feature472is a first intermediate layer contact in dielectric layer475. Conductive feature472is in direct contact with via481. Conductive features462,452,442,432,422and second metal line212are second, third, fourth, fifth, sixth and seventh intermediate layer conductive features, respectively. In some embodiments, conductive features432,442,452,462,472have substantially the same thickness. In some embodiments, conductive feature422has substantially the same thickness as second metal line212. In some embodiments, thickness of conductive features432,442,452,462,472is different from thickness of conductive feature422and second metal line212. In some embodiments, conductive feature422and second metal line212are thicker than conductive features432,442,452,462,472. Second metal line212and conductive features422,432,442,452,462,472,482are or comprise at least one conductive material. In some embodiments, the at least one conductive material is or comprises a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable method.

Via471is a first intermediate layer via in dielectric layer470. Via471is in direct contact with conductive feature472and conductive feature462. Via461is a second intermediate layer via in direct contact with conductive feature462and conductive feature452. Via451is a third intermediate layer via in direct contact with conductive feature452and conductive feature442. Via441is a fourth intermediate layer via in direct contact with conductive feature442and conductive feature432. Via431is a fifth intermediate layer via in direct contact with conductive feature432and conductive feature422. Via421is a sixth intermediate layer via in direct contact with conductive feature422and second metal line212. In some embodiments, vias421,431have substantially the same thickness. In some embodiments, vias441,451,461,471,481have substantially the same thickness. In some embodiments, thickness of vias441,451,461,471,481is different from thickness of vias421,431. In some embodiments, vias421,431are thicker than vias441,451,461,471,481.

Via213is an upper conductive via. Thickness of via213is labeled “t” inFIG.4. Thickness of via213is greater than thickness of any intermediate conductive via between the surface of via213facing substrate240and substrate240.

In some embodiments, thickness of via213is greater than about 8 kilo-Angstroms. In some embodiments, thickness of via213is in a range of about 8 kilo-Angstroms to about 30 kilo-Angstroms. Below 8 kilo-Angstroms, via213may not be thick enough to provide sufficient power-handling capability, and may also introduce excessive intermetal capacitance between first metal line211and second metal line212. Formation of via213through a single oxide layer having thickness in excess of 30 kilo-Angstroms may adversely affect process uniformity when etching an opening for via213through the single oxide layer in which the via213is formed.

In some embodiments, via213is extended through at least two dielectric layers of dielectric layer410to further increase the oxide thickness by further increasing distance between the inductor100and the substrate. Use of two dielectric layers separated by an etch stop layer allows for a thicker via213while avoiding adverse effects on process uniformity by etching the two dielectric layers in two distinct etching operations. In some embodiments, thickness of via213extending through at least two dielectric layers is in a range of about 16 kilo-Angstroms to 60 kilo-Angstroms. In some embodiments, via213has thickness of about 48 kilo-Angstroms. Via213having thickness much greater than 8 kilo-Angstroms effectively increases tox, thereby reducing Coxand increasing quality factor. Further dielectric layers and etch stop layers may be introduced to further increase thickness of via213. Via213having excessive thickness may introduce unwanted stress on the lower metal layers, which may lead to delamination.

FIG.5atoFIG.5nare diagrams showing intermediate semiconductor structures illustrating a method of fabricating structure210ofFIG.2andFIG.4in accordance with some embodiments.FIG.6is a flow chart of the method of fabricating the structure210in accordance with some embodiments.FIG.5atoFIG.5jgenerally relate to formation of via213.FIG.5ktoFIG.5ngenerally relate to formation of first metal line211.

InFIG.5a, second metal line212is provided. In some embodiments, second metal line212is a contact or trace in an intermediate metal layer. In some embodiments, formation of second metal line212is achieved by at least defining a feature in a lithography process, removing dielectric material to form an opening substantially corresponding to the feature, depositing or plating a conductive material in and over the opening, and planarizing and/or polishing the conductive material and the dielectric layer. In some embodiments, the at least one conductive material is or comprises a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable method. In some embodiments, a barrier seed layer is formed in the opening prior to depositing or plating the conductive material in the opening.

FIG.5bshows an intermediate semiconductor structure after performing operation600of the flowchart60shown inFIG.6. InFIG.5b, functional layer501is formed on second metal line212. In some embodiments, functional layer501is a first functional layer. In some embodiments, functional layer501is a first etch stop layer. For example, as shown inFIG.6, operation600may include forming functional layer501by deposition of a first etch stop layer (ESL1). Generally, an etch stop layer (ESL) provides a mechanism to stop an etch process when forming conductive features, such as contacts or vias. An ESL may be formed of a dielectric material having a different etch selectivity from adjacent layers or components. In some embodiments, functional layer501comprises or is silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, silicon carbide, the like, or a combination thereof deposited by an appropriate deposition process. In some embodiments, thickness of functional layer501is in a range of about 300 Angstroms to 1000 Angstroms. In some embodiments, functional layer501is formed of silicon carbide and has thickness of about 750 Angstroms. It may be advantageous to use a thick functional layer501both to avoid forming voids in the functional layer501and to increase thickness of via213and oxide thickness tox. An excessively thick functional layer501may increase etching time and volume of etchant consumed to etch through functional layer501.

FIG.5cshows an intermediate semiconductor structure after performing operation601ofFIG.6. InFIG.5c, functional layer502is formed on functional layer501. In some embodiments,502is a second functional layer. In some embodiments, functional layer502is a second etch stop layer similar to the first etch stop layer. For example, as shown inFIG.6, operation601may include forming functional layer502by deposition of a second etch stop layer (ESL2). In some embodiments, functional layer502comprises or is silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, silicon carbide, the like, or a combination thereof deposited by an appropriate deposition process on functional layer501. In some embodiments, thickness of functional layer502is in a range of about 300 Angstroms to 1000 Angstroms. In some embodiments, functional layer502is formed of the same material as functional layer501. In some embodiments, functional layer502is formed of silicon carbide and has thickness of about 750 Angstroms. It may be advantageous to use a thick functional layer502both to avoid forming voids in the functional layer502and to increase thickness of via213and oxide thickness tox. An excessively thick functional layer502may increase etching time and volume of etchant consumed to etch through functional layer502.

FIG.5dshows an intermediate semiconductor structure after performing operation602ofFIG.6. InFIG.5d, dielectric layer511is formed on functional layer502. In some embodiments, dielectric layer511is a first dielectric layer. In some embodiments, dielectric layer511is formed of a dielectric material deposited, by an appropriate deposition process, on the functional layer502. In some embodiments, the dielectric material may comprise or be silicon dioxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than silicon dioxide), silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof. For example, as shown inFIG.6, operation602may include forming dielectric layer511by deposition of a first oxide layer (OX1). In some embodiments, thickness of dielectric layer511is in a range of about 4 kilo-Angstroms to about 30 kilo-Angstroms. In some embodiments, thickness of dielectric layer511is in a range of about 20 kilo-Angstroms to about 30 kilo-Angstroms. In some embodiments, dielectric layer511is formed of USG and has a thickness of about 25 kilo-Angstroms. A thicker dielectric layer511is advantageous to increase thickness of via213and oxide thickness tox. An excessively thick dielectric layer511will consume more time and material in production and may also adversely impact process uniformity.

FIG.5eshows an intermediate semiconductor structure after performing operation603ofFIG.6. InFIG.5e, functional layer503is formed on dielectric layer511. In some embodiments, functional layer503is a third functional layer. In some embodiments, functional layer503is a third etch stop layer. For example, as shown inFIG.6, operation603may include forming functional layer503by deposition of a third etch stop layer (ESL3). In some embodiments, functional layer503is formed of a dielectric material. In some embodiments, functional layer503comprises or is silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, silicon carbide, the like, or a combination thereof deposited by an appropriate deposition process on dielectric layer511. In some embodiments, thickness of functional layer503is in a range of about 200 Angstroms to 1000 Angstroms. In some embodiments, functional layer503is formed of a different material as the first and second etch stop layers. In some embodiments, functional layer503is formed of silicon nitride and has thickness of about 500 Angstroms. It may be advantageous to use a thick functional layer503both to avoid forming voids in the functional layer503and to increase thickness of via213and oxide thickness tox. An excessively thick functional layer503may increase etching time and volume of etchant consumed to etch through functional layer503.

FIG.5fshows an intermediate semiconductor structure after performing operation604ofFIG.6. InFIG.5f, dielectric layer512is formed on functional layer503. In some embodiments, dielectric layer512is a second dielectric layer. In some embodiments, dielectric layer512is deposited, by an appropriate deposition process, on functional layer503. In some embodiments, dielectric layer512is formed of a dielectric material. In some embodiments, dielectric layer512comprises or is silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof. For example, as shown inFIG.6, operation604may include forming dielectric layer512by deposition of a second oxide layer (OX2). In some embodiments, thickness of dielectric layer512is in a range of about 4 kilo-Angstroms to about 30 kilo-Angstroms. In some embodiments, thickness of dielectric layer512is greater than about 5 kilo-Angstroms, greater than about 10 kilo-Angstroms, greater than about 20 kilo-Angstroms or greater than about 30 kilo-Angstroms. In some embodiments, the dielectric layer512is formed of a same material as the dielectric layer511. In some embodiments, the dielectric layer512is formed of USG and has a thickness of about 26 kilo-Angstroms. In some embodiments, dielectric layer512is formed of USG and has a thickness of about 25 kilo-Angstroms. A thicker dielectric layer512is advantageous to increase thickness of via213and oxide thickness tox. An excessively thick dielectric layer512will consume more time and material in production and may also adversely impact process uniformity. The combination of dielectric layers511,512and functional layer503allows for greater thickness of via213, while splitting etching of the dielectric layers511,512into two separate operations, which may improve uniformity and yield.

FIG.5gshows an intermediate semiconductor structure after performing operation605ofFIG.6. InFIG.5g, functional layer504is formed on dielectric layer512. In some embodiments, functional layer504is a fourth functional layer. In some embodiments, functional layer504is a first anti-reflective layer. For example, as shown inFIG.6, operation605may include forming functional layer503by deposition of a first anti-reflective layer (AR1). The first anti-reflective layer is used to mitigate reflections from underlying layers which are reflective to light used in a subsequent lithographic process. In some embodiments, functional layer504comprises or is silicon oxide, silicon oxycarbide, silicon oxynitride, hydrocarbon-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, titanium containing material, tantalum containing material, an organic material, or any combination thereof. In some embodiments, functional layer504comprises or is a nitrogen-free material, such as a nitrogen-free oxide. In some embodiments, functional layer504comprises or is a nitrogen-free silicon oxycarbide. Functional layer504is deposited on dielectric layer512by any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), spin-on coating process, or the like. In some embodiments, thickness of functional layer504is in a range of about 300 Angstroms to 1000 Angstroms. In some embodiments, functional layer504is formed of silicon oxynitride and has a thickness of about 600 Angstroms. Thickness of the functional layer504may be chosen to be thick enough to prevent voids to provide a uniform anti-reflective function, while also being thin enough to account for material and deposition cost of the layer, as well as etchant material and time cost for etching the layer, and slurry material and time cost for planarizing/removing the layer.

FIG.5hshows an intermediate semiconductor structure formed after performing operation606ofFIG.6. At operation606, opening541is formed. Opening541is formed through functional layer504, dielectric layer512, functional layer503, dielectric layer511, functional layer502and functional layer501. Opening541can be formed using a patterned photoresist layer that defines an opening pattern followed by a suitable etching process. For example, as shown inFIG.6, operation606may include forming opening541by at least one first lithography operation and at least one first etch operation (Litho+Etch 1). The patterned photoresist layer is then removed using any suitable stripping process. Opening541exposes a portion of the top surface of second metal line212to provide an electrical connection.

FIG.5ishows an intermediate semiconductor structure after performing operation607ofFIG.6. InFIG.5i, conductive plug531is formed in opening541, and on functional layer504. For example, as shown inFIG.6, operation607may include forming conductive plug531by a first electroless copper plating process (ECP 1). Conductive plug531substantially fills the removed portions of functional layer504, dielectric layer512, functional layer503, dielectric layer511, functional layer502and functional layer501which comprise opening541, and directly contacts second metal line212. In some embodiments, conductive plug531is formed of at least one conductive material. In some embodiments, the at least one conductive material is or comprises a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable method. In some embodiments, conductive plug531is formed using a dual damascene process. In some embodiments, the plating process is an electroless copper plating (ECP) process. In some embodiments, the electroless copper plating process is preceded by forming a seed layer on sidewalls of the removed portions. In some embodiments, the seed layer is a barrier seed layer.

FIG.5jshows an intermediate semiconductor structure after performing operation608ofFIG.6. InFIG.5j, conductive plug531is planarized and/or polished to form first metal line211. For example, as shown inFIG.6, operation608may include polishing and/or planarizing conductive plug531by a first chemical mechanical polishing process (CMP1). In some embodiments, after conductive plug531is formed and filled in the opening541, a chemical mechanical polishing (CMP) operation removes any excess material of conductive plug531, and any remaining mask, such as functional layer504to have a top surface of conductive plug531substantially coplanar with a top surface of dielectric layer512, as shown inFIG.5j. In some embodiments, thickness of dielectric layer512is reduced after performing operation608by about 20%. The thickness of the dielectric layer512may be reduced by less than about 20% if sufficient planarity may be achieved while polishing away less material of the dielectric layer512.

FIG.5kshows an intermediate semiconductor structure after performing operation609, operation610, operation611and operation612ofFIG.6. Operation609includes forming functional layer505. In some embodiments, functional layer505is a fifth functional layer. In some embodiments, functional layer505is an etch stop layer. For example, as shown inFIG.6, operation609may include forming functional layer505by deposition of a fourth etch stop layer (ESL4). In some embodiments, functional layer505is formed of a dielectric material. In some embodiments, functional layer505comprises or is silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, silicon carbide, the like, or a combination thereof deposited by an appropriate deposition process on functional layer512and conductive via213. In some embodiments, thickness of functional layer505is in a range of about 200 Angstroms to 1000 Angstroms. In some embodiments, functional layer505is formed of a different material as the first and second etch stop layers. In some embodiments, functional layer505is formed of silicon nitride and has thickness of about 500 Angstroms. It may be advantageous to use a thick functional layer505both to avoid forming voids in the functional layer505. An excessively thick functional layer505may increase etching time and volume of etchant consumed to etch through functional layer505.

Operation610of the flowchart60ofFIG.6includes forming functional layer506. In some embodiments, functional layer506is a sixth functional layer. In some embodiments, functional layer506is an anti-reflective layer deposited on functional layer505. For example, as shown inFIG.6, operation610may include forming functional layer506by deposition of a second anti-reflective layer (AR2). In some embodiments, functional layer506is formed of a dielectric material. In some embodiments, functional layer506comprises or is silicon oxide, silicon oxycarbide, silicon oxynitride, hydrocarbon-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, titanium containing material, tantalum containing material, an organic material, or any combination thereof. In some embodiments, functional layer506comprises or is a nitrogen-free material, such as a nitrogen-free oxide. In some embodiments, functional layer506comprises or is a nitrogen-free silicon oxycarbide. Functional layer506is deposited on functional layer505by any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), spin-on coating process, or the like. In some embodiments, thickness of functional layer506is in a range of about 200 Angstroms to 1000 Angstroms. In some embodiments, functional layer506is formed of silicon oxynitride, and has thickness of about 600 Angstroms. Thickness of the functional layer506may be chosen to be thick enough to prevent voids to provide a uniform anti-reflective function, while also being thin enough to account for material and deposition cost of the layer, as well as etchant material and time cost for etching the layer, and slurry material and time cost for planarizing/removing the layer.

Operation611includes forming dielectric layer513. In some embodiments, dielectric layer513is a third dielectric layer deposited on functional layer506. In some embodiments, dielectric layer513comprises or is silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof. For example, as shown inFIG.6, operation611may include forming dielectric layer513by deposition of a third oxide layer (OX3). In some embodiments, thickness of dielectric layer513is in a range of about 4 kilo-Angstroms to about 30 kilo-Angstroms. In some embodiments, thickness of dielectric layer513is greater than about 5 kilo-Angstroms, greater than about 10 kilo-Angstroms, greater than about 20 kilo-Angstroms, greater than about 30 kilo-Angstroms or greater than about 40 kilo-Angstroms. In some embodiments, dielectric layer513is formed of USG, and has thickness of about 38 kilo-Angstroms. Thickness of dielectric layer513may be similar to or slightly greater than desired thickness of the top metal layer. Excessive thickness of dielectric layer513will increase planarization time and consumed materials, e.g. slurry, to achieve the desired thickness of the top metal layer. An excessively thick top metal layer may cause unwanted stress that may lead to delamination in the intermediate or bottom metal layer/layers.

Operation612includes forming functional layer507. In some embodiments, functional layer507is a seventh functional layer deposited on dielectric layer513. In some embodiments, functional layer507is an anti-reflective layer. For example, as shown inFIG.6, operation612may include forming functional layer507by deposition of a third anti-reflective layer (AR3). In some embodiments, functional layer507comprises or is silicon oxide, silicon oxycarbide, silicon oxynitride, hydrocarbon-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, titanium containing material, tantalum containing material, an organic material, or any combination thereof. In some embodiments, functional layer507comprises or is a nitrogen-free material, such as a nitrogen-free oxide. In some embodiments, functional layer507comprises or is a nitrogen-free silicon oxycarbide. Functional layer507is deposited on functional layer507by any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), spin-on coating process, or the like. In some embodiments, thickness of functional layer507is in a range of about 200 Angstroms to 1000 Angstroms. Thickness of the functional layer507may be chosen to be thick enough to prevent voids to provide a uniform anti-reflective function, while also being thin enough to account for material and deposition cost of the layer, as well as etchant material and time cost for etching the layer, and slurry material and time cost for planarizing/removing the layer.

FIG.5lshows an intermediate semiconductor structure after performing operation613ofFIG.6. At operation613, opening542is formed. Opening542is formed through functional layer507, dielectric layer513, functional layer506, and functional layer505. Opening542can be formed using a patterned photoresist layer that defines an opening pattern followed by a suitable etching process. For example, as shown inFIG.6, operation613may include forming opening542by at least one second lithography operation and at least one second etch operation (Litho+Etch 2). The patterned photoresist layer is then removed using any suitable stripping process. Opening542exposes a portion of the top surface of conductive via213to provide an electrical connection.

FIG.5mshows an intermediate semiconductor structure after performing operation614ofFIG.6. InFIG.5m, conductive plug532is formed in opening542, and on functional layer507. For example, as shown inFIG.6, operation614may include forming conductive plug532by a second electroless copper plating process (ECP 2). Conductive plug532substantially fills the removed portions of functional layer507, dielectric layer513, functional layer506and functional layer505which comprise opening542, and directly contacts conductive via213. In some embodiments, conductive plug532is formed of at least one conductive material. In some embodiments, the at least one conductive material is or comprises a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or other suitable method. In some embodiments, conductive plug532is formed using a dual damascene process. In some embodiments, the plating process is an electroless copper plating (ECP) process. In some embodiments, the electroless copper plating process is preceded by forming a seed layer on sidewalls of the removed portions. In some embodiments, the seed layer is a barrier seed layer.

FIG.5nshows structure210after performing operation615ofFIG.6. InFIG.5n, conductive plug532is planarized and/or polished to form first metal line211. For example, as shown inFIG.6, operation615may include polishing and/or planarizing conductive plug532by a second chemical mechanical polishing process (CMP2). In some embodiments, after conductive plug532is formed and filled in opening542, a chemical mechanical polish (CMP) removes any excess material of conductive plug532, and any remaining mask, such as functional layer507to have a top surface of conductive plug532substantially coplanar with a top surface of dielectric layer513, as shown inFIG.5n. In some embodiments, thickness of dielectric layer513is reduced after performing operation615.

FIG.6is explained above with reference toFIG.5atoFIG.5n. In some embodiments, the flowchart60includes more or fewer processes than depicted inFIG.6. In some embodiments, forming functional layer502, which corresponds to operation601is omitted. In some embodiments, operation614includes at least two electroless copper plating operations. In some embodiments, a baking operation is performed after operation613and prior to operation614and/or after operation614and prior to operation615. Other embodiments may include further functional layer deposition operations and/or baking.

FIG.7is a circuit block diagram of passive radio frequency device70in accordance with some embodiments. In some embodiments, the passive radio frequency device70is a radio frequency identification (RFID) transceiver of an RFID tag. Any RFID tag having no internal power supply is considered “passive.” Passive RFID tags harvest power from received radio frequency signals, typically from an RFID reader device, and reuse the harvested power to transmit a response to the RFID reader device.

The passive radio frequency device70may include terminal720for receiving radio frequency signals. In some embodiments, terminal720is electrically connected to or otherwise includes an antenna.

Terminal730of passive radio frequency device70is an output terminal for emitting radio frequency signals. In some embodiments, terminal730includes an antenna. In some embodiments, terminal730and terminal720include the same antenna.

Circuitry700of passive radio frequency device70is electrically connected to terminal720and terminal730. In some embodiments, circuitry700includes one or more of a modulator, a demodulator, power recovery/harvesting circuitry, a clock, control circuitry, processing circuitry, coding circuitry, decoding circuitry, or memory.

Passive radio frequency device70includes inductor circuit10. In some embodiments, inductor circuit10is used to receive the radio frequency signals. Inductor circuit10is electrically connected to circuitry700. Inductor circuit10includes at least via213in dielectric layer513, and first metal line211substantially directly contacting via213and extended through dielectric layer511, dielectric layer512, and functional layer503. Inductor circuit10has enhanced quality factor due to reduced Coxby increased upper conductive via thickness, as described above with respect to at leastFIG.3. Passive radio frequency device70including inductor circuit10has improved sensitivity when receiving the radio frequency signals, and also improved ability to reject unwanted radio frequency signals.

FIG.8is a circuit block diagram of active radio frequency device80in accordance with some embodiments. In some embodiments, active radio frequency device80is a radio frequency identification (RFID) transceiver of an RFID tag. Any RFID tag having an internal power supply is considered “active.” Active RFID tags generally do not need to harvest power from received radio frequency signals, typically from an RFID reader device, and use power from the internal power supply to transmit a response to the RFID reader device. As such, while active radio frequency device80may include many similar electronic components to passive radio frequency device70, configuration of the electronic components in active radio frequency device80may differ significantly from the configuration in passive radio frequency device70. As such, different reference numerals are used throughoutFIG.8.

Terminal820of active radio frequency device80is an input terminal for receiving radio frequency signals. In some embodiments, terminal820includes an antenna.

Terminal830of active radio frequency device80is an output terminal for emitting radio frequency signals. In some embodiments, terminal830includes an antenna. In some embodiments, terminal830and terminal820include the same antenna.

Circuitry800of active radio frequency device80is electrically connected to terminal820and terminal830. In some embodiments, circuitry800includes one or more of a modulator, a demodulator, a clock, control circuitry, processing circuitry, coding circuitry, decoding circuitry, or memory.

Power source810of active radio frequency device80is electrically connected to circuitry800. Power source810provides power to circuitry800. In some embodiments, power source810includes at least a battery. In some embodiments, power source810includes power management circuitry.

Active radio frequency device80includes inductor circuit10. In some embodiments, inductor circuit10is used to receive the radio frequency signals. Inductor circuit10is electrically connected to circuitry800. Inductor circuit10includes at least via213in dielectric layer513, and first metal line211substantially directly contacting via213and extended through dielectric layer511, dielectric layer512, and functional layer503. Inductor circuit10has enhanced quality factor due to reduced Cox, by increased upper conductive via thickness, as described above with respect to at leastFIG.3. Active radio frequency device80including inductor circuit10has improved sensitivity when receiving the radio frequency signals, and also improved ability to reject unwanted radio frequency signals.

FIG.9is a circuit block diagram of voltage controlled oscillator device90in accordance with some embodiments. Voltage controlled oscillator device90outputs a first clock at terminal920and a second clock at terminal930substantially the inverse of the first clock, both at a frequency controlled by a control voltage at terminal970. Voltage controlled oscillator device90ofFIG.9illustrates a voltage controlled oscillator including inductor circuit10. In some embodiments, inductor circuit10is utilized as an on-chip inductor in a voltage controlled oscillator device utilizing a different architecture than that shown inFIG.9.

Inverter900of voltage controlled oscillator device90outputs a first output signal at terminal930that is substantially the inverse of the first clock at terminal920. An input terminal of inverter900for receiving the first clock is electrically connected to an output terminal of inverter910, a first terminal of inductor circuit10, a first terminal of capacitor940, and a first terminal of variable capacitor950. An output terminal of inverter900for outputting the second clock is electrically connected to an input terminal of inverter910, a second terminal of inductor circuit10, a second terminal of capacitor940, and a first terminal of variable capacitor960.

Inverter910of voltage controlled oscillator device90outputs the first clock at terminal920that is substantially the inverse of the second clock at terminal930. An input terminal of inverter910for receiving the second clock is electrically connected to an output terminal of inverter900, the second terminal of inductor circuit10, the second terminal of capacitor940, and the first terminal of variable capacitor960. An output terminal of inverter910for outputting the first clock is electrically connected to the input terminal of inverter900, the first terminal of inductor circuit10, the first terminal of capacitor940, and the first terminal of variable capacitor950.

Inductor circuit10, capacitor940, variable capacitor950and variable capacitor960form a variable LC tank circuit that is tuned by the control voltage at terminal970. The first terminal of inductor circuit10is electrically connected to the input terminal of inverter900, the output terminal of inverter910, the first terminal of capacitor940, and the first terminal of variable capacitor950. The second terminal of inductor circuit10is electrically connected to the output terminal of inverter900, the input terminal of inverter910, the second terminal of capacitor940, and the first terminal of variable capacitor960.

Inductor circuit10includes at least via213in dielectric layer513, and first metal line211substantially directly contacting via213and extended through dielectric layer511, dielectric layer512, and functional layer503. Inductor circuit10has enhanced quality factor due to reduced Coxby increased upper conductive via thickness, as described above with respect to at leastFIG.3. Voltage controlled oscillator device90has improved phase noise due to the enhanced quality factor.

Capacitor940of the LC tank circuit is a fixed capacitor. In some embodiments, capacitor940is a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or the like. The first terminal of capacitor940is electrically connected to the input terminal of inverter900, the first terminal of inductor circuit10, the first terminal of variable capacitor950, and the output terminal of inverter910. The second terminal of capacitor940is electrically connected to the output terminal of inverter900, the second terminal of inductor circuit10, the first terminal of variable capacitor960and the input terminal of inverter910.

Variable capacitor950of the LC tank circuit is a variable capacitor. In some embodiments, variable capacitor950is a metal-oxide-semiconductor (MOS) capacitor. The first terminal of variable capacitor950is electrically connected to the input terminal of inverter900, the first terminal of inductor circuit10, the first terminal of capacitor940, and the output terminal of inverter910. A second terminal of variable capacitor950is electrically connected to a second terminal of variable capacitor960and terminal970.

Variable capacitor960of the LC tank circuit is a variable capacitor. In some embodiments, variable capacitor960is a metal-oxide-semiconductor (MOS) capacitor. The first terminal of variable capacitor960is electrically connected to the output terminal of inverter900, the second terminal of inductor circuit10, the second terminal of capacitor940, and the input terminal of inverter910. The second terminal of variable capacitor960is electrically connected to the second terminal of variable capacitor950and terminal970.

In addition, an integrated circuit device may include active devices located in or on the substrate240and interconnects directly or indirectly coupling at least one of the active device or the inductor100. A complementary metal-oxide-semiconductor (CMOS) device, and other active and/or passive devices may be included in an integrated circuit device and/or coupled directly or indirectly to the inductor100. The inductor100may be advantageous in high frequency applications of the integrated circuit device. Moreover, implementation of the inductor100into existing fabrication processes may be simple and cost effective. For example, fabrication of the inductor100may be achieved by employing existing fabrication techniques as future-developed techniques may also be employed. In addition, one or more of the via213or the first metal line211may be formed simultaneously with other existing metallization layers, such that incorporation of the inductor100into existing designs may not require additional process steps.

Various embodiments of integrated circuit structures and process flows directed toward increasing oxide thickness toxwith a view to reducing substrate loss factor and self-resonance factor to increase quality factor of on-chip inductors are described. Further embodiments of devices, including both passive and active radio frequency identification (RFID) transceivers and a voltage controlled oscillator (VCO), are also described. To enhance inductor quality factor and overall device performance, in some embodiments, oxide thickness toxis increased by extending an upper conductive via through at least two dielectric layers. In some embodiments, the oxide thickness is further increased by extending the upper conductive via through at least one etch stop layer positioned between the at least two dielectric layers. Q factor for a 0.5 nano-Henry on-chip inductor is greater than about 22 when using the structures and processes described herein. Sensitivity of the RFID transceivers or phase noise of the VCO is improved due to the excellent quality factor of the inductor.

An embodiment of a device comprises a substrate, a first conductive layer, a first conductive via, a plurality of second conductive layer, and a plurality of second conductive vias. The first conductive layer is on the substrate. The first conductive via is between the first conductive layer and the substrate, and is electrically connected to the first conductive layer. The first conductive via has thickness greater than about 8 kilo-Angstroms. The plurality of second conductive layers is between the first conductive via and the substrate. The plurality of second conductive vias is between the first conductive via and the substrate.

An embodiment of a method includes forming a first dielectric layer on a first conductive layer. A second dielectric layer is formed on the first dielectric layer. A conductive via extending through the first dielectric layer and the second dielectric layer is formed. A third dielectric layer is formed on the second dielectric layer. At least a first conductive portion of an inductor is formed in the third dielectric layer and in direct contact with the conductive via.

Another embodiment of a device includes a first dielectric layer, a second dielectric layer, a first etch stop layer, a third dielectric layer, and an inductor. The second dielectric layer is on the first dielectric layer. The first etch stop layer is between the first dielectric layer and the second dielectric layer. The third dielectric layer is on the second dielectric layer. The inductor includes a conductive trace in the third dielectric layer, and a conductive via substantially directly contacting the conductive trace and extended through the first dielectric layer, the second dielectric layer, and the first etch stop layer. Circuitry is electrically coupled to the inductor.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.