Patent ID: 12205944

DETAILED DESCRIPTION

Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.

Also, the terms “coupled to” or “couples with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “couples” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.

As noted above, disclosed embodiments recognize for processes such as BiCMOS having drain extended MOS (DEMOS) transistors, low voltage complementary metal oxide semiconductor (CMOS) and bipolar transistors when the p-epi layer is relatively thick (e.g., about 9 μm) the n-type drift region diffusions provided in the process may not be deep enough to reach the NBL. As a result, it is not possible to junction isolate two neighboring p-epi regions in a common tank using these diffusions. In some previous process nodes, the p-epi layer is thinner so that it is possible to reach from the top of the p-epi layer surface down to NBL using diffusions provided in the process.

Disclosed embodiments provide methods to form a “wall” of n-type doping connecting respective sides of an outer DT ring providing junction isolation for neighboring p-epi regions in a common DEEPN+ NBL tank despite a thick p-epi layer to provide isolation of neighboring p-epi regions in the same DEEPN+ NBL tank. In disclosed embodiments, a plurality of inner DT structures are placed in a row (or otherwise positioned, seeFIGS.2A-2Cdescribed below) spanning one side to another side of a conventional outer DT ring that surrounds the DEEPN/NBL n-tank. The inner DTs structures are placed sufficiently close to one another so that the neighboring DEEPN diffusions emanating from these inner DTs after high temperature annealing provided in the process will merge into a continuous wall of n-type material that prevents direct connection between the neighboring p-epi regions on respective side of the wall. The NBL of the respective p-EPI regions remains connected, however, so that current may pass between the two neighboring n-tank regions through the NBL without having to reach the surface through the relatively resistive DEEPN diffusions. No additional masks or processing is needed to implement disclosed isolation structures for ICs with epi regions sharing the same tank.

FIG.1Ashows an outer DT ring120with a line of fifteen (15) inner DT structures1251to12515extending from the left side to the right side of the outer DT ring120before a DEEPN diffusion process, on an p-epi layer115on a substrate105, according to an example embodiment. The outer DT ring120an inner DT structures1251to12515comprise at least a dielectric sidewall that can be entirely dielectric filled, or dielectric lined and filled with another material, such as polysilicon which can be doped to provide electrical contact to the p-epi layer115below the NBL (see NBL110within p-epi layer115inFIGS.1C and1Ddescribed below).

FIG.1Bshows the outer DT ring120with the line of inner DT structures shown inFIG.1Aafter a deep n-type (DEEPN) diffusion process to provide a DEEPN diffusion120afor the outer DT ring120configured to provide and outer ring (DEEPN ring) in the p-epi layer115region contacting the dielectric sidewalls extending downward from a topside a surface n-type region on the topside of the p-epi layer115to the NBL110to enclose a portion of the p-epi layer115to define an enclosed p-epi region within. The DEEPN diffusion process also forms DEEPN diffusion regions125afor each of the plurality of inner DT structures1251to12515.

The plurality of inner DT structures1251to12515have a sufficiently small inner DT structure spacing so that adjacent ones of the DEEPN diffusion regions125aas shown overlap to form the continuous wall of n-type material which extends continuously from the left side to the right side of the outer DT ring120to divide the enclosed p-epi region into a first p-epi region1151and a second p-epi region1152, wherein the NBL in the first p-epi region connects to the NBL in the second p-epi region (see NBL110inFIG.1C). A first ESD device160is shown in the first p-epi region1151and a second ESD device170is shown in the second p-epi region1152connected to one another through the NBL110, with the overall structure shown identified as ESD cell100. The first and second ESD devices160and170in one embodiment are both NPN devices.

FIG.1Cis a vertical cross section derived from the ESD cell100shownFIG.1Bshowing a portion of a DEEPN wall with DEEPN diffusion region125ashown provided adjacent to inner DT structures with an arrow associated with inner DT structure1258shown for separating the first and second p-epi regions1151and1152, according to an example embodiment. Although not shown, in one typical example a two level metal stack with dielectric and vias through the dielectrics can be used for contact to contact regions shown between the shallow trench isolation (STI)112at the surface of the p-epi layer115. The p-epi layer115can optionally include boron implant(s) which locally increase the p-type doping in the p-epi layer115shown as115aand115babove115a. Surface nwell regions are shown as121.

The outer DT ring120is shown having an optional p-doped filler. The surface nwell region121together with the DEEPN diffusion120aconnect the top surface of the p-epi layer115shown as contacts at the top of115bto the NBL110, including a p+ contact131to the p-doped filler of the outer DT ring120which provides a connection to the p-epi layer115below the NBL110, n+ contact132to the surface nwell region121adjacent to the outer DT ring120, n+ contact133to the emitter, n+ contact134to the surface nwell region121of the inner DT structure1258, and p+ contact135to surface pwell regions126.

FIG.1Dis a horizontal cross section derived from the ESD cell100shownFIG.1Bshowing structure of the15example inner DT structures1251to12515in a line providing a merged DEEPN diffusion regions125a, according to an example embodiment. The outer structures are provided by the outer DT ring120including the DEEPN diffusions120a. The inner DT structures1251to12515each can be dielectric lined and filled with a p+ material, such as p+ doped polysilicon, or be entirely dielectric filled.

FIGS.2A,2B,2Cshow various examples inner DT structures within an outer DT ring120to divide a p-epi layer115into first and second p-epi regions1151and1152, shown as a circle125′, a rectangle or square125″, and an L-shape125′″, respectively. Many other shapes can be envisioned.

FIG.3illustrates a high level depiction of a construction of an IC300into which disclosed ESD cells shown as ESD cells100functioning as ESD protection devices are incorporated to protect one or more terminals of the IC300, according to an example embodiment. The “T” indicated at the top of the respective ESD cells100inFIG.3represents an input responsive to an ESD event provided by a suitable trigger circuit.

IC300includes functional circuitry324, which is integrated circuitry that realizes and carries out desired functionality of IC300, such as that of a digital IC (e.g., digital signal processor) or analog IC (e.g., amplifier or power converter). The capability of functional circuitry provided by IC300may vary, for example ranging from a simple device to a complex devoice. The specific functionality contained within functional circuitry324is not of importance to disclosed embodiments.

IC300also includes a number of external terminals, by way of which functional circuitry324carries out its function. A few of those external terminals are illustrated inFIG.3. It is to be understood that the number of terminals and their function can also vary widely. In the example of IC300shown inFIG.3, two terminals shown operate as common input and output terminals (I/O), by way of which functional circuitry324can receive incoming signals and can generate outputs, as well known in the art. A dedicated input terminal IN is also shown inFIG.3for IC, as is a dedicated output terminal OUT. Each of terminals IN, OUT are also connected to functional circuitry324. Power supply terminal Vdd receives a positive power supply voltage in this example, while ground terminal Vss is provided to receive a reference voltage, such as system ground. Although not shown, the ground shown connected to the ESD cells100is coupled to VSS, such as resistively coupled or shorted together.

IC300includes an instance of a disclosed ESD cells100connected to each of its terminals. Each ESD cell100is connected to its corresponding terminal in parallel with the functional circuitry324. ESD cells100are also connected to power supply and reference voltage terminals VDD, VSS, in parallel with functional circuitry324. However, in some applications, some pins of the IC300being protected will be self-protecting, such as diode protected power supply pins. Pins also can be protected against different levels of ESD strike (Human Body Model (HBM), Charged Device Model (CDM), IEC, etc.). The functional circuitry324in IC300can be BiMOS circuitry having bipolar transistors and MOSFETs.

Disclosed embodiments include methods of isolating devices within a common tank. A blanket NBL is formed into a p-epi layer on a substrate that defines a buried portion of the p-epi layer (buried p-epi) below the NBL110, generally using an n+ implant with a high temperature drive. At least a dielectrically lined outer deep trench isolation ring (outer DT ring120) is formed including forming a trench, lining the trench with a dielectric liner to form dielectric sidewalls and filling the trench with a dielectric or polysilicon, then n-type implanting along the dielectric sidewalls of the p-epi layer115and annealing to form a DEEPN diffusion120acontacting the dielectric sidewalls and extending downward from a topside of the p-epi layer to the NBL configured in a ring (DEEPN ring). The DEEPN ring encloses a portion of the p-epi layer115to define an enclosed p-epi region within.

Simultaneously while forming the outer DT ring120(so that no processing is added) a plurality of inner DT structures (e.g.,1251to12515) are formed within the enclosed p-epi region each comprising at least dielectric sidewalls having a DEEPN diffusion125acontacting the dielectric sidewalls and extending downward from the topside surface of the p-epi layer115to the NBL110. The plurality of inner DT structures have a sufficiently small inner DT structure spacing so that adjacent ones of the DEEPN diffusion regions125aoverlap to form continuous wall of n-type material which extends from a first side to a second side of said outer DT ring120to divide the enclosed p-epi region115into a first p-epi region1151and a second p-epi region1152, wherein the NBL110in the first p-epi region1151connects to the NBL110in the second p-epi region1152.

A depth of the outer DT ring120and plurality of inner DT structures can be greater than a junction depth of the NBL110, and the method can further comprise filling an inside of the outer DT ring120and an inside of the plurality of inner DT structures with polysilicon, and doping the polysilicon p-type to provide electrical contact to the buried p-epi layer under the NBL110. The plurality of inner DT structures (e.g.,1251to12515) collectively by themselves can form a closed shape inside the outer DT ring.

The method can further comprise forming a first NPN ESD device in the first p-epi region1151and a second NPN ESD device in the second p-epi region1152connected to one another through the NBL110, such as to provide either a bidirectional EDS cell or a back-to-back ESD cell. A center-to-center spacing between adjacent ones of the inner DT structures can be between 1.5 μm and 3 μm, and a width of the plurality of inner DT structures can be between 2 μm and 3 μm. The substrate105can comprise p-doped silicon having a doping level from 1×1016to 1×1019cm−3, the p-epi layer115can comprise silicon that is 6 μm to 12 μm thick, and at least the buried p-epi layer can have a boron doping level from 3×1014cm−3to 3×1016cm−3. The entire p-epi layer can have this doping level, or the surface portion can receive one or more additional p-type implants as described above.

Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.