Patent ID: 12249518

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments will now be described with respect to a particular embodiment which utilizes a system on integrated substrate (SoIS) with multiple substrates attached for increased package sizes. However, the ideas presented herein are not intended to be limited to the details recited below and may be used in a wide variety of applications. Each of these applications is fully intended to be included within the scope of the embodiments presented.

FIG.1illustrates a cross-sectional view of a redistribution structure200formed in an redistribution layer (RDL) build up process150in an intermediate step in forming a system package, in accordance with some embodiments. In particular, the RDL build up process150(designated by the directional arrow) includes forming the redistribution structure200on a carrier substrate102, in accordance with some embodiments. The carrier substrate102comprises, for example, silicon-based materials, such as a silicon substrate (e.g., a silicon wafer), a glass material, silicon oxide, or other materials, such as aluminum oxide, the like, or a combination. In some embodiments, the carrier substrate102may be a panel structure, which may be, for example, a supporting substrate formed from a suitable dielectric material, such as a glass material or an organic material, and which may have a rectangular shape. The carrier substrate102may be planar in order to accommodate the formation of additional features subsequently formed thereon.

According to some embodiments, an adhesive layer (not shown) is formed on the carrier substrate102to facilitate a subsequent debonding of the carrier substrate102. The adhesive layer may be formed of a polymer-based material, which may be removed along with the carrier substrate102from the overlying structures that will be formed in subsequent steps. In some embodiments, the adhesive layer is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a Light-to-Heat-Conversion (LTHC) release coating. In other embodiments, the adhesive layer may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV light. However, other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, or the like, may also be used. The adhesive layer may be placed onto the carrier substrate102in a semi-liquid or gel form, which is readily deformable under pressure. According to some embodiments, the top surface of the adhesive layer may be leveled and may have a high degree of co-planarity.

According to some embodiments, a polymer layer105is placed over the adhesive layer and is utilized in order to provide protection to, e.g., the subsequently formed structures. In an embodiment the polymer layer105may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, Solder Resistance (SR), or Ajinomoto build-up film (ABF) may be utilized. The polymer layer105may be placed using, e.g., a spin-coating process to a thickness of between about 2 μm and about 15 μm, such as about 5 μm, although any suitable method and thickness may be used.

Once the polymer layer105has been formed, contact pads104are formed over the polymer layer105. In accordance with some embodiments, the contact pads104may be formed by initially forming a first seed layer (not shown) of one or more thin layers of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. The first seed layer may comprise a layer of titanium created using processes such as sputtering, evaporation, or PECVD processes, depending upon the desired materials. A photoresist (also not shown) may then be formed and patterned to cover the first seed layer using, e.g., a spin coating technique. Once the photoresist has been formed and patterned, a conductive material may be formed on the first seed layer. The conductive material may be a material such as copper, titanium, tungsten, aluminum, another metal, the like, or a combination thereof. The conductive material may be formed through a deposition process such as electroplating or electroless plating, or the like. Once the conductive material has been formed, the photoresist may be removed through a suitable removal process such as ashing or chemical stripping. Additionally, after the removal of the photoresist, those portions of the first seed layer that were covered by the photoresist may be removed through, for example, a suitable wet etch process or dry etch process, which may use the conductive material as an etch mask. The remaining portions of the first seed layer and conductive material form the contact pads104.

Once the contact pads104have been formed, a redistribution structure210is formed over the contact pads104and the carrier substrate102, in accordance with some embodiments. The redistribution structure210shown includes insulating layers208A-F (e.g., insulating layer208A, insulating layer208B, insulating layer208C, insulating layer208D, insulating layer208E, and insulating layer208F), and includes redistribution layers209A-F (e.g., redistribution layer209A, redistribution layer209B, redistribution layer209C, redistribution layer209D, redistribution layer209E, and redistribution layer209F). Furthermore, the redistribution structure210may have any suitable number of insulating layers or redistribution layers.

Still referring toFIG.1, the insulating layer208A is formed over the contact pads104and the carrier substrate102. The insulating layer208A may be made of one or more suitable dielectric materials such as prepreg, resin coated copper (RCC), an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a photo image dielectric (PID), a polymer material such a PBO, a photosensitive polymer material, a molding material, a polyimide material, a low-k dielectric material, another dielectric material, the like, or a combination thereof. The insulating layer208A may be formed by a process such as lamination, coating, (e.g., spin-coating), CVD, the like, or a combination thereof. The insulating layer208A may have a thickness of between about 5 μm and about 50 μm, such as about 15 μm, although any suitable thickness may be used.

Openings into the insulating layer208A may be formed using a suitable photolithographic mask and etching process in order to expose the underlying contact pads104. For example, a photoresist may be formed and patterned over the insulating layer208A, and one or more etching processes (e.g., a wet etching process or a dry etching process) are utilized to remove portions of the insulating layer208A. In other embodiments in which the insulating layer208A is formed of a photosensitive polymer such as PBO, polyimide, BCB, or the like, the openings may be patterned directly using an exposure and development process.

The redistribution layer209A may then be formed to provide additional routing. In an embodiment, the redistribution layer209A may be formed using materials and processes similar to the contact pads104. For example, a second seed layer (not shown) may be formed, a photoresist placed and patterned on top of the second seed layer in a desired pattern for the redistribution layer209A, and conductive material (e.g., copper, titanium, or the like) may then be formed in the patterned openings of the photoresist using e.g., a plating process. The photoresist may then be removed and the second seed layer etched, forming redistribution layer209A. In this manner, the redistribution layer209A may form electrical connections to the contact pads104.

Additional insulating layers209B-F and redistribution layers209B-F may then be formed over the redistribution layer209A and insulating layer208A to provide additional routing. The insulating layers209B-F and redistribution layers209B-F may be formed in alternating layers, and may be formed using processes and materials similar to those used for the insulating layer208A or the redistribution layer209A. For example, an insulating layer (e.g., insulating layer208B) may be formed over a redistribution layer (e.g., redistribution layer209A), and then openings made through the insulating layer to expose portions of the underlying redistribution layer using a suitable photolithographic mask and etching process. A third seed layer (not shown) may be formed over the insulating layer and conductive material formed on portions of the third seed layer, forming an overlying redistribution layer (e.g., redistribution layer209B). These steps may be repeated to form the redistribution structure210having a suitable number and configuration of insulation layers and redistribution layers. The insulating layers208B-F may be formed to each have a thickness of between about 5 μm and about 50 μm, such as about 15 μm. In some embodiments, the redistribution structure210is a fan-out structure. In other embodiments, the redistribution structure210may be formed in a different process than described herein.

In a particular embodiment the insulating layer208E and insulating layer208F may be formed differently from the underlying insulating layer208A, insulating layer208B, insulating layer208C, and insulating layer208D. For example, in an embodiment the insulating layer208A, the insulating layer208B, the insulating layer208C, and the insulating layer208D may be formed of a material such as PBO. However, the insulating layer208E and the insulating layer208F may be formed from a different material and/or a different thickness, such as by being formed of an Ajonomoto build up film or a prepreg material to a larger thickness. However, any combination of materials and thicknesses may be utilized.

Turning toFIG.2A, this figure illustrates mounting an interconnect structure300over the redistribution structure200, in accordance with some embodiments. In some embodiments, under-bump metallization structures (UBMs, not shown) are first formed on portions of the topmost redistribution layer of the redistribution structure210(e.g., redistribution layer209F inFIG.1). The UBMs may, for example, include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, other arrangements of materials and layers may be used, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBMs. Any suitable materials or layers of material that may be used for the UBMs are fully intended to be included within the scope of the current application. The UBMs may be created by forming each layer of the UBMs over the redistribution structure210. The forming of each layer may be performed using a plating process, such as electroplating or electroless plating, although other processes of formation, such as sputtering, evaporation, or PECVD process, may be used depending upon the desired materials. Once the desired layers have been formed, portions of the layers may then be removed through a suitable photolithographic masking and etching process to leave the UBMs in a desired shape, such as a circular, octagonal, square, or rectangular shape, although any desired shape may alternatively be formed.

Still referring toFIG.2A, external connectors212are formed over the redistribution structure210. The external connectors212may be formed over the UBMs, if present. The external connectors212may be, for example, contact bumps or solder balls, although any suitable types of connectors may be utilized. In an embodiment in which the external connectors212are contact bumps, the external connectors212may include a material such as tin, or other suitable materials, such as silver, lead-free tin, or copper. In an embodiment in which the external connectors212are tin solder bumps, the external connectors212may be formed by initially forming a layer of tin using such a technique such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once a layer of tin has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shape for the external connectors212. In some embodiments, the external connectors212may have a thickness between about 2 μm and about 500 μm. In some embodiments, the external connectors212may have a pitch between about 25 μm and about 1250 μm.

In some embodiments, the interconnect structure300may be, for example, an interposer or a “semi-finished substrate” which could either have active and passive devices or else may be free from active and passive devices. The interconnect structure300can also provide stability and rigidity to the attached redistribution structure200, helping to reduce warping. In an embodiment the interconnect structure300comprises a core substrate302having conductive layers disposed on opposite surfaces. In some embodiments, the core substrate302may include a material such as a pre-impregnated composite fiber (prepreg) material, an epoxy, a molding compound, Ajinomoto build-up film (ABF), an epoxy molding compound, fiberglass-reinforced resin materials, printed circuit board (PCB) materials, silica filler, polymer materials, polyimide materials, paper, glass fiber, non-woven glass fabric, glass, ceramic, other laminates, the like, or combinations thereof. In other embodiments, the core substrate302may be a double-sided copper-clad laminate (CCL) substrate or the like. The core substrate302may have a second height H2of between about 30 μm and about 2000 μm, such as about 250 μm or about 500 μm. However, any suitable height may be used.

Referring toFIG.2A, openings are formed in the core substrate302within which through vias306are formed (described below). In some embodiments, the openings are formed by, for example, a laser drilling technique. Other processes, e.g., mechanical drilling, etching, or the like, may also be used in other embodiments.

Once the openings have been formed, conductive material is deposited to form the routing layer308on a side of the core substrate302and through vias306within the openings in the core substrate302. In some embodiments, the routing layer308and through vias306are formed from a conductive material such as copper, aluminum, or combinations of these, or the like, using a deposition process such as photoresist patterning and plating; blanket chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these or the like. The deposition process lines or fills the openings to form the through vias306, as well as forming the routing layer308. Once the conductive material has been deposited, the conductive material may be patterned (in embodiments in which a blanket deposition was performed) or else the patterned photoresist may be removed (in embodiments in which a plating process is utilized). However, any suitable deposition and/or patterning process may be utilized.

Once the routing layer308has been formed, a similar process may then be performed on the opposite side of the core substrate302to form the routing layer309(and/or remaining portions of through vias306) on the opposite side of the core substrate302. In this manner, the conductive material may be used to form the routing layer308and the routing layer309on opposite sides of the core substrate302and through vias306extending through the core substrate302.

Optionally, in some embodiments in which the deposition of the conductive material does not fully fill the openings, a remainder of the openings may then be filled with a dielectric material307. The dielectric material307may provide structural support and protection for the conductive material formed along the sidewalls. In some embodiments, the dielectric material307may be a material such as a molding material, epoxy, an epoxy molding compound, a resin, the like, or a combination thereof. The dielectric material307may be formed or placed using, e.g., a molding process, a spin-on process or another process.

Continuing withFIG.2A, dielectric layers and additional routing layers may be formed over the routing layers308and309to form routing structures312and316. The routing structures312and316are formed on opposite sides of the core substrate302and may provide additional electrical routing within the interconnect structure300. The routing structure312is electrically connected to the routing layer308and includes alternating dielectric layers310A-C and routing layers311A-C. The routing structure316is electrically connected to the routing layer309and includes alternating dielectric layers314A-C and routing layers315A-C. Each of the routing structures312or316may have any suitable number of dielectric layers or routing layers, including more or fewer than shown inFIG.2A. In some embodiments, one or both of routing structures312or316may be omitted. In some embodiments, the number of layers of routing structure312may be different than the number of layers of routing structure316.

In some embodiments, the routing structure312is formed by forming the dielectric layer310A over the routing layer308and the core substrate302. In some embodiments, the dielectric layer310A may be a material such as a build-up material, ABF, a prepreg material, a laminate material, another material similar to those described above for the core substrate302, the like, or combinations thereof. The dielectric layer310A may be formed by a lamination process, a coating process, or another suitable process. In some embodiments, the dielectric layer310A may have a first thickness Th1of between about 5 μm and about 50 μm. Openings are formed in the dielectric layer310A that expose portions of the routing layer308for subsequent electrical connection. In some embodiments, the openings are formed by, for example, an etching process, a laser drilling technique, or the like. Other processes, e.g., mechanical drilling or the like, may also be used in other embodiments. In some embodiments, an optional surface preparation process (e.g., a desmear process or the like) may be performed after the openings are formed.

A conductive material is then deposited to form routing layer311A on the dielectric layer310A and within the openings in the dielectric layer310A. In some embodiments, the routing layer311A is formed by first forming a seed layer and a patterned mask over the dielectric layer310A. The patterned mask may be, for example, a patterned photoresist layer. Openings in the patterned mask may expose portions of the seed layer on which conductive material will subsequently be formed. The conductive material may then be deposited on the exposed regions of the dielectric layer310A and within the openings in the dielectric layer310A using, for example, a plating process, an electroless plating process, or another process. In some embodiments, the conductive material is deposited having a thickness of between about 1 μm and about 50 μm. After depositing the conductive material, the patterned mask layer (e.g., the photoresist) may be removed using a wet chemical process or a dry process (e.g., an ashing process). In this manner, an additional routing layer (e.g., routing layer311A) is formed over and electrically connected to the routing layer308.

Additional dielectric layers310B-C and routing layers311B-C may then be formed adjacent to the routing layer311A and dielectric layer310A to provide additional routing along with electrical connection within the routing structure312. The dielectric layers310B-C and routing layers311B-C may be formed in alternating layers, and may be formed using processes and materials similar to those used for the dielectric layer310A or the routing layer311A. These steps may be repeated to form a routing structure312having any suitable number and configuration of dielectric layers and routing layers.

In some embodiments, dielectric layers314A-C and routing layers315A-C may be formed adjacent to the routing layer309to form the routing structure316. The routing structure316may be formed using a process similar to that of the routing structure312, described above. However, any suitable process may be utilized.

In some embodiments, a protection layer320is formed over the routing structures312and316of interconnect structures300. The protection layer320may be e.g., a solder resist material or a PBO material, and may be formed to protect the surfaces of the routing structures312or316. In some embodiments, the protection layer320may be a photosensitive material formed by printing, lamination, spin-coating, or the like. The photosensitive material may then be exposed to an optical pattern and developed, forming openings in the photosensitive material. In other embodiments, the protection layer320may be formed by depositing a non-photosensitive dielectric layer (e.g., silicon oxide, silicon nitride, the like, or a combination), forming a patterned photoresist mask over the dielectric layer using suitable photolithography techniques, and then etching the dielectric layer using the patterned photoresist mask using a suitable etching process (e.g., wet etching or dry etching). The protection layer320may be formed and patterned over the routing structure312and the routing structure316using the same techniques. Other processes and materials may also be used.

The interconnect structures300may be formed with one or both of the routing structures312and316. The interconnect structure300may be formed with the protection layer320formed and patterned over one or both of the routing structures312and316. As such, the interconnect structures300may be formed to a third height H3of between about 200 μm and about 3,000 μm, such as about 1,500 μm, according to some embodiments. However any suitable height may be used.

FIG.2Afurther illustrates a mounting process250(designated by the directional arrow), such as a substrate mounting process, including placement of a plurality of the interconnect structures300into electrical connection with the redistribution structure200, in accordance with some embodiments. In an embodiment, the interconnect structures300are placed into physical contact with the external connectors212on the redistribution structure200using, e.g., a pick and place process. The interconnect structures300may be placed such that exposed regions of a topmost routing layer are aligned with corresponding connectors of the external connectors212on the redistribution structure200. Once in physical contact, a reflow process may be utilized to bond the external connectors212of the redistribution structure200to the interconnect structures300. In some embodiments, external connectors are formed on the interconnect structures300instead of or in addition to the external connectors212formed on the redistribution structure200.

In the embodiment shown inFIG.2A, the interconnect structures300may be placed such that a first gap201is present between them. In some embodiments, the spacing of adjacent redistribution structures may be controlled such that the first gap201is a certain distance or within a certain range of distances. For example, the first gap201may be a first distance D1of between about 40 μm and about 5000 μm. However, any suitable distance may be used. In some cases, the first gap201distance may be controlled in order to avoid collision between the interconnect structures300during placement. Furthermore, a second gap203is formed between the protection layer320of the interconnect structure300and the top insulating layer of the redistribution structure200. According to some embodiments, the second gap203has a second distance D2of between about 10 μm and about 300 μm. However, any suitable distance may be used. According to some embodiments, the distance of the first gap201and the distance of the second gap203may be controlled to accommodate a subsequent deposition of a molding compound (e.g., dispense molding underfill (DMUF)), as discussed in greater detail below.

FIG.2Billustrates a top-down view of an intermediate structure after mounting of the interconnect structures300using a panel process, in accordance with some embodiments. As illustrated inFIG.2B, the interconnect structures300may have rectangular shapes and may be formed using the carrier substrate102having a rectangular shape, and the carrier substrate102may be referred to as a panel. Any of the processes and procedures suitable for placing the interconnect structures300on the carrier substrate102(e.g., wafer) having the round shape panel may be used to place the interconnect structures300using the carrier substrate102(e.g., panel) having the rectangular shape. Although nine of the interconnect structures300are illustrated inFIG.2B, any number of interconnect structures300may be formed on the panel carrier substrate.

Each of the interconnect structures300may similarly sized and shaped, although in other embodiments the separate interconnect structures300may be different sizes and shapes. In a particular embodiment each of the interconnect structures300may have an interconnect width WI of between about 40 mm and about 210 mm, such as about 90.6 mm, while each of the interconnect structures300may have an interconnect length Li of between about 40 mm and about 210 mm, such as about 90.6 mm. However, any suitable length and width may be utilized.

FIG.2Cillustrates a top-down view of an intermediate structure after the mounting of the interconnect structures300using a wafer form process instead of a panel form process (as described above with respect toFIG.2B), in accordance with other embodiments. As illustrated inFIG.2C, a plurality of the interconnect structures300having rectangular shapes are placed on a single wafer carrier substrate having a round shape, such as a circular shape. The carrier substrate102having the round shape, may be referred to herein as a wafer carrier substrate. Although four of the package substrates400are illustrated inFIG.2C, any number of the interconnect structures300may be formed on the wafer carrier substrate, such as from a single package substrate to thousands of package substrates. Any suitable number may be utilized.

FIG.3Aillustrates a molding process350(designated by the directional arrow) for encapsulating the interconnect structures300attached to the redistribution structure200, in accordance with some embodiments. As shown in the highlighted section330, the underfill402is deposited to fill the voids in between external connectors212within the second gap203and to encapsulate the interconnect structures300within the underfill402, wherein the underfill402at least partially fills the first gap201between the interconnect structures300. According to some embodiments, the underfill402is placed to fill the voids within the second gap203in between external connectors212connecting the redistribution structure200and the interconnect structures300and forms along sidewalls of the interconnect structures300to a first width W1to align with an outer perimeter of the redistribution structure200. According to some embodiments, the underfill402is formed to the first width W1of between about 40 μm and about 5,000 μm, such as about 200 μm. However, any suitable width and any suitable thickness may be used for the first width W1of the underfill402.

FIG.3Billustrates a magnified view of the highlighted section330inFIG.3A, in accordance with some embodiments. As can be seen, in some embodiments the underfill402is deposited to partially fill in the first gap201from the top insulating layer (e.g.,208F) of the redistribution structure200to a fourth height H4at a point between sidewalls of the interconnect structures300. In some embodiments, the underfill402partially fills the first gap201to the fourth height H4of between about 500 μm and about 1,700 μm, such as about 1,600 μm. However, any suitable thickness may be used for the fourth height H4.

A remaining portion of the first gap201forms a void within the first gap201from the underfill402to a top of the protection layer320. According to some embodiments, the void within the first gap201has a fifth height H5of between about 0 μm and about 1,200 μm, such as about 100 μm. According to some embodiments, the underfill402is formed such that a ratio of the fifth height H5of the void in the first gap201to the fourth height H4of the underfill402in the first gap201is between about 0.1:1 and about 4:1, such as about 0.2:1.

Depending on the fourth height H4of the underfill402within the first gap201, the underfill402forms a first interface extending along one or more sections of a first sidewall of a first interconnect structure300A facing the first gap201and forms a second interface extending along one or more sections of a second sidewall of a second interconnect structure300B facing the first gap201. According to some embodiments, the first sidewall interface extends along a first section of the first sidewall comprising the protection layer320of the first interconnect structure300A and the second sidewall interface extends along a first section of the second sidewall comprising the protection layer320of the second interconnect structure300B. In some embodiments, the first sidewall interface extends along the first section and a second section of the first sidewall, the second section of the first sidewall comprising the routing structure316of the first interconnect structure300A and the second sidewall interface extends along the first section and a second section of the second sidewall, the second section of the second sidewall comprising the routing structure316of the second interconnect structure300B. In some embodiments, the first sidewall interface extends along the first and second sections and a third section of the first sidewall, the third section of the first sidewall comprising the core substrate302of the first interconnect structure300A and the second sidewall interface extends along the first and second sections and a third section of the second sidewall, the third section of the second sidewall comprising the core substrate302of the second interconnect structure300B.

According to some embodiments, the underfill402may be a material such as a molding compound, an epoxy, an underfill, a dispense molding underfill (DMUF), a resin, or the like. The underfill402may be dispensed using, e.g., a molding process, such as a transfer molding process, an injection process, combinations of these, or the like. The underfill402can protect the external connectors212and can provide structural support for the redistribution structure200. In some embodiments, the underfill402may be cured after placement.

FIG.4illustrates the formation of a package substrate400(e.g., integrated substrate (IS)), in accordance with some embodiments. In particular,FIG.4illustrates a debonding process450(designated by the directional arrow) of the carrier substrate102and formation of conductive connectors404on the contact pads104for the package substrate400. The carrier substrate102may be debonded from the redistribution structure200using, e.g., a thermal process to alter the adhesive properties of the adhesive layer (not shown) disposed on the carrier substrate102. In a particular embodiment an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser, is utilized to irradiate and heat the adhesive layer until the adhesive layer loses at least some of its adhesive properties. Once performed, the carrier substrate102and the adhesive layer may be physically separated and removed from the redistribution structure200. Once the carrier substrate102and the adhesive layer have been removed, the resulting structure may be flipped over, and the interconnect structures300may be attached to a temporary substrate (not shown), such as a tape, wafer, panel, frame, ring, or the like for further processing.

FIG.4additionally illustrates a patterning of the polymer layer105in order to expose the contact pads104. In an embodiment the polymer layer105may be patterned using, e.g., a laser drilling method. In such a method a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax layer (not separately illustrated inFIG.4) is first deposited over the polymer layer105. Once protected, a laser is directed towards those portions of the polymer layer105which are desired to be removed in order to expose the underlying contact pads104.

In another embodiment, the polymer layer105may be patterned by initially applying a photoresist (not individually illustrated inFIG.4) to the polymer layer105and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern, and the underlying exposed portion of the polymer layer105are removed with, e.g., a dry etch process. However, any other suitable method for patterning the polymer layer105may be utilized.

Once the contact pads104have been exposed, the conductive connectors404may be formed over the contact pads104making electrical connection to the redistribution structure200. In some embodiments, an optional solderability treatment (e.g., pre-soldering treatment) may be performed on the exposed surfaces of the contact pads104prior to forming the conductive connectors404. The conductive connectors404may be, for example, contact bumps or solder balls (e.g., C4 balls, ball grid array (BGA)), although any suitable type of connectors may be utilized. In an embodiment in which the conductive connectors404are contact bumps, the conductive connectors404may include a material such as tin, or other suitable materials, such as silver, lead-free tin, or copper. In an embodiment in which the conductive connectors404are tin solder bumps, the conductive connectors404may be formed by initially forming a layer of tin using such a technique such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once a layer of tin has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shape for the conductive connectors404. In some embodiments, the conductive connectors404may be similar to external connectors212described above.

FIG.5Aillustrates a placement process550(designated by the directional arrow) for the formation of a system package600(e.g., system on integrated substrate (SoIS)), in accordance with some embodiments. A packaged semiconductor device500is placed on the conductive connectors404of the redistribution structure210, making electrical connection between the packaged semiconductor device500and the redistribution structure210of the package substrate400. The packaged semiconductor device500may be placed on the conductive connectors404using a placement process550such as a pick-and-place process. The packaged semiconductor device500may include one or more devices, which may include devices designed for an intended purpose such as a memory die (e.g., a DRAM die, a stacked memory die, a high-bandwidth memory (HBM) die, etc.), a logic die, a central processing unit (CPU) die, an I/O die, a system-on-a-chip (SoC), a component on a wafer (CoW), an integrated fan-out structure (InFO), a package, the like, or a combination thereof. In an embodiment, the packaged semiconductor device500includes integrated circuit devices, such as transistors, capacitors, inductors, resistors, metallization layers, external connectors, and the like, therein, as desired for a particular functionality. In some embodiments, the packaged semiconductor device500may include more than one of the same type of device, or may include different devices.FIG.5Ashows three semiconductor devices encapsulated and connected with redistribution structures and contact pads, but in other embodiments one, two, or more than three semiconductor devices may be attached to the conductive connectors404.

The packaged semiconductor device500may be placed such that the contact pads are aligned with the conductive connectors404of the package substrate400. Once in physical contact, a reflow process may be utilized to bond the conductive connectors404of the redistribution structure200to the packaged semiconductor device500. In some embodiments, external connectors are formed on the packaged semiconductor device500instead of or in addition to the conductive connectors404formed on the redistribution structure200. In some embodiments, the conductive connectors404are not formed on the redistribution structure200, and the packaged semiconductor device500is bonded to the redistribution structure200using a direct bonding technique such as thermocompression bonding, hybrid bonding, metal-to-metal bonding, or the like. However, any suitable bonding technique may be utilized.

As shown inFIG.5A, in embodiments which utilize the conductive connectors404, once the package semiconductor device500has been bonded an underfill502may be deposited along the sidewalls of the gap between the packaged semiconductor device500and the redistribution structure200. The underfill502may also at least partially surround some conductive connectors404. The underfill502may be a material such as a molding compound, an epoxy, an underfill, a molding underfill (MUF), a resin, or the like, and may be similar to underfill402described previously.

FIG.5Aalso illustrates that a ring structure127is attached to the redistribution structure200surrounding the packaged semiconductor device500, in accordance with some embodiments. The ring structure127may be attached to protect the packaged semiconductor device500, to add stability to the package substrate400, and/or to dissipate heat from the packaged semiconductor device500and the package substrate400. The ring structure127may be formed from a material having a high thermal conductivity, such as steel, stainless steel, copper, aluminum, combinations thereof, or the like. In some embodiments, the ring structure127may be a metal coated with another metal, such as gold. According to some embodiments, the ring structure127comprises materials suitable for providing a thermal path from the redistribution structure200to an overlying heat extraction device (not shown) for transferring heat away from the packaged semiconductor device500. Heat extraction devices include, but are not limited to, devices such as vapor chamber lids, heatsinks, and the like. In other embodiments, the ring structure127may not be thermally coupled to an overlying heat extraction device and may provide a distributed heat transfer from the redistribution structure200to the environment. An adhesive (not shown), for example, a thermal interface material (TIM) adhesive may be used to secure the ring structure127to the redistribution structure200. Thus, the ring structure127and the thermal interface material (TIM) may provide increased effectiveness and efficiency of heat transfer away from the redistribution structure200.

According to some embodiments, the ring structure127is formed to a third width W3to match a width of the package substrate400and is formed to a sixth height H6to match a height of the packaged semiconductor device500over the package substrate400. In some embodiments, the third width W3is between about 10 mm and about 500 mm, such as about 30 mm or, for example, about 12 mm and the sixth height H6is between about 50 μm and about 5,000 μm, such as about 2,000 μm. However, any suitable widths and heights may be used for the ring structure127. For example, if the package substrate400has a width of about 12 mm, a ring structure127having a third width W3of about 12 mm and a sixth height H6of about 2,000 μm may be applied to the package substrate400to appropriately control the package warpage to within 250 μm.

FIG.5Afurther illustrates external connectors406that are formed over and electrically connected to the interconnect structures300. The external connectors406may be formed as any suitable connector (e.g., BGAs, C4 balls, contact bumps, solder balls, or the like) using any suitable process for forming the external connectors212or the conductive connectors404, as set forth above. However, any suitable connectors and any suitable process may also be utilized. The external connectors406(e.g., ball grid array (BGA)) may be formed via a suitable BGA ball mount process on exposed portions of the outermost routing layer of the routing structure312. In some embodiments, the external connectors406may have a thickness between about 2 μm and about 1000 μm. In some embodiments, the external connectors406may have a pitch W2of between about 100 μm and about 1,500 μm.

FIG.5Billustrates a bottom view of the system package600(e.g., SoIS), in accordance with some embodiments. In the bottom view, the package substrate400(e.g., integrated substrate (IS)) is illustrated as a grouping of four of the interconnect structures300embedded in the underfill402separated by the first gap201. In the bottom view ofFIG.5B, the external connectors406are illustrated as a ball grid array (BGA) configuration formed over the protection layer320of each of the interconnect structures300. Although the package substrate400is illustrated as a group of four (e.g., 2×2) interconnect structures300, the package substrate400may comprise a group of any suitable number (e.g., 2×2, 3×2, 4×3, 4×4, etc.) of discrete substrates embedded in the underfill402and may be separated by any suitable gap distance. Furthermore, the external connectors406of the interconnect structures300may comprise any suitable number of connectors and may be arranged in any suitable configuration.

FIG.6illustrates a cross-sectional view of intermediate steps in mounting the system package600to a support substrate135(e.g., printed circuit board (PCB)). In an embodiment the support substrate135may be a printed circuit board such as a laminate substrate formed as a stack of multiple thin layers (or laminates) of a polymer material such as bismaleimide triazine (BT), FR-4, ABF, or the like. However, any other suitable substrate, such as a silicon interposer, a silicon substrate, organic substrate, a ceramic substrate, or the like, may also be utilized, and all such redistributive substrates that provide support and connectivity to the structure including the external connectors406of the interconnect structures300are fully intended to be included within the scope of the embodiments. In an embodiment the system package600may be placed into contact with the support substrate135and a reflow process may be performed to bond the system package600to the support substrate135.

FIG.7Aillustrates, in accordance with some other embodiments, a cross-sectional view of mounting a single package interconnect substrate700to the redistribution structure200in an intermediate step in forming the package substrate400. In an embodiment the single package interconnect substrate700is the only interconnect substrate bonded to the underlying redistribution structure200, and there are no other interconnect structures (e.g., there are not multiple ones of the interconnect structures300as described in previous embodiments).

FIG.7Aadditionally illustrates, according to some embodiments, the placing, mounting, and electrically connecting the single package interconnect substrate700to the redistribution structure200. According to some embodiments, the single package interconnect substrate700may be formed on another carrier substrate (not shown) using any of the materials and the processes suitable for forming and mounting the interconnect structures300, as set forth above. Once formed on the other carrier, the single package interconnect substrate700may be placed, mounted, and electrically connected to the redistribution structure200using, for example, the external connectors212, as set forth above. However, any suitable materials and any suitable process for mounting the single package interconnect substrate700to the redistribution structure200may also be used.

FIG.7Aadditionally illustrates an encapsulation of the single package interconnect substrate700with the underfill402once the single package interconnect substrate700has been bonded to the redistribution structure200. In an embodiment the single package interconnect substrate700may be encapsulated as described above with respect toFIGS.3A-3B. However, as there is no first gap201(seeFIG.3A-3B) within the single package interconnect substrate700, the underfill402covers the sidewalls of the single package interconnect substrate700but does not interpose between different portions of the single package interconnect substrate700.

FIG.7Billustrates a dicing process750(indicated by the directional arrow) in an intermediate step in forming the package substrate400, in accordance with some other embodiments. Once the underfill402has been placed, the dicing process750(e.g., a “pre-cut” process, a singulation process, or the like) may be used to form the first gap201to separate the single package interconnect substrate700into a plurality of the interconnect structures300, in accordance with some embodiments, without cutting into the redistribution structure210. According to some embodiments, the single package interconnect substrate700may be separated into an array of the interconnect structures300(e.g., 2×2 array, 3×3 array, etc.). The dicing process750may be performed using any suitable dicing tool725(e.g., a blade, a saw, a laser drill, an etching process, and the like, or combinations thereof) to cut through and/or remove materials of the different layers of single package interconnect substrate700to form the first gap201. However, any suitable techniques may be used to form the first gap201between the interconnect structures300.

By placing the single package interconnect substrate700and then separating the single package interconnect substrate700into the individual interconnect structures300, a single pick and place process may be performed to connect the single package interconnect substrate700to the redistribution structure200and the first gap201may still be formed. In this embodiment, however, the underfill402does not extend up into the first gap201. Additionally, although not explicitly illustrated inFIG.7B, in some embodiments the dicing process750will also extend the first gap201into the underfill402.

Additionally, in other embodiments, once the gap201has been formed, a portion of the first gap201may be refilled with the underfill402. For example, once the gap201has been formed, the underfill402may be dispensed, injected, or otherwise placed into a portion of the first gap201. The dispensing may be performed so that the underfill402covers a portion of the sidewalls of the gap201as described above with respect toFIGS.3A-3B.

In yet another embodiment, the order of the dicing process750and the placement of the underfill402may be switched, so that the single package interconnect substrate700is separated into the separate interconnect structures300first. Once separated, the underfill402may then be dispensed as described above with respect toFIGS.3A-3B. Any suitable order of steps may be utilized to place the single package interconnect substrate700, separate the single package interconnect substrate700into separate interconnect structures300, and dispensing the underfill402may be utilized, and all such order of steps are fully intended to be included within the scope of the embodiments.

By utilizing multiple ones of the interconnect structures300separated by the first gap201, stresses that are present in larger single interconnect structures are reduced or eliminated. As such, the multiple ones of the interconnect structures300with the first gap201allows for the reduction or elimination of warpage in the system package600(e.g., system on integrated substrate (SoIS)) and mitigates board level reliability challenges (e.g., ball-grid array (BGA) strain) associated with fabricating super-sized system packages. As such, the electrical performance and the board level reliability of the system package600may be improved.

By utilizing the embodiments described herein, the embodiments provide excellent electrical performance with reduced board level reliability risks even for super large package size (e.g., >90 mm2or >100 mm2) designs used, for example, in HPC (high performance computing) applications (e.g., artificial intelligence (AI)) that require high data rate processing, increased bandwidth demands, and/or low latency communications. For example, the embodiments described herein provide reliable electrical performance for high data rate/high bandwidth applications and with reduced board level reliability risks. Also, a simplified process flow due to a conventional assembly process is integrated into a wafer form process.

According to embodiments described herein the package substrate400reduces package warpage in the system package600(e.g., system on integrated substrate (SoIS)) and mitigates board level reliability challenges (e.g., ball-grid array (BGA) strain) associated with fabricating super-sized system packages (e.g., “super PKG size”) having dimensions greater than about 90 mm2, or even greater than about 100 mm2while still providing a thin core thickness with low inductance and low resistance in a system package. Furthermore, reduced costs may be achieved using multiple discrete substrates for the interconnect structures300to form the package substrate400as compared with fabricating a full-sized interconnect substrate for super-sized system packages. As such, the system package600provides for low cost and highly reliable solutions for chip package integration (CPI) used in high-performance computing (HPC) applications including advanced networking and server products (e.g., artificial intelligence (AI)) that require high data rates processing, increased bandwidth demands, and/or low latency communication.

In accordance with an embodiment, a method includes: forming a redistribution structure on a carrier; attaching a first interconnect structure and a second interconnect structure on a first side of the redistribution structure, wherein after the attaching a first gap is disposed between a sidewall of the first interconnect structure and a sidewall of the second interconnect structure; and depositing a molded underfill material around the first interconnect structure, the molded underfill material having a first height within the first gap and having a second height on an opposite side of the first interconnect structure from the second interconnect structure, the second height being greater than the first height. In an embodiment, the redistribution structure is part of a system on integrated substrate with a package size of greater than 90 mm2. In an embodiment the method further includes mounting a semiconductor device adjacent to a second side of the redistribution structure that is opposite the first side of the redistribution structure. In an embodiment, the attaching the first interconnect structure and the second interconnect structure includes: attaching the first interconnect structure; and separately attaching the second interconnect structure. In an embodiment, the attaching the first interconnect structure and the second interconnect structure includes: attaching a single package interconnect structure to the redistribution structure; and separating the single package interconnect structure into the first interconnect structure and the second interconnect structure after the attaching the single package interconnect structure. In an embodiment, the carrier is a wafer. In an embodiment, the carrier is a panel.

In accordance with another embodiment, a method includes: forming a polymer layer on a carrier substrate; forming a first contact pad on the polymer layer; forming a redistribution structure on the first contact pad; mounting an interconnect substrate to the redistribution structure; dispensing an underfill between the redistribution structure and the interconnect substrate; sawing the interconnect substrate after the mounting the interconnect substrate without sawing the redistribution structure; and electrically connecting a semiconductor device to the first contact pad, the semiconductor device being located on an opposite side of the first contact pad than the redistribution structure. In an embodiment the redistribution structure is part of a package, the package having a width of between about 30 mm and about 500 mm. In an embodiment the package is a system on integrated substrate package. In an embodiment the underfill covers a sidewall of the interconnect substrate. In an embodiment the method further includes attaching a ring to the redistribution structure. In an embodiment the semiconductor device is a packaged semiconductor device. In an embodiment the mounting the interconnect substrate further comprises forming the interconnect substrate, the forming the interconnect substrate includes: forming an opening through a core substrate; depositing a conductive material into the opening; forming a first routing layer on a first side of the core substrate; and forming a second routing layer on a second side of the core substrate, the second routing layer in electrical connection with the first routing layer through the conductive material.

In accordance with yet another embodiment, a semiconductor package includes: a redistribution structure; a first interconnect structure electrically connected to a first side of the redistribution structure; a second interconnect structure electrically connected to the first side of the redistribution structure, wherein the second interconnect structure is spaced apart from the first interconnect structure by a first region; a molded underfill material located at least partially within the first region, wherein the molded underfill material covers a first sidewall of the first interconnect structure within the first region less than the molded underfill material covers a second sidewall of the first interconnect structure outside of the first region; and a semiconductor device electrically connected to a second side of the redistribution structure opposite the first interconnect structure. In an embodiment the semiconductor package is a system on integrated substrate package. In an embodiment the molded underfill material has an interface with a protection layer of the first interconnect structure. In an embodiment the vertical sidewall interface has an interface with a routing layer of the first interconnect structure. In an embodiment the vertical sidewall interface has an interface with a core substrate of the first interconnect structure. In an embodiment the molded underfill material covers all of the second sidewall.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.