Patent ID: 12254202

DETAILED DESCRIPTION

FIG.1is a diagram illustrating an electronic device100according to an embodiment of the present invention. As shown inFIG.1, the electronic device100comprises a host device110and a plurality of storage devices120_1-120_B. Each storage device (e.g., storage device120_1) includes a flash memory controller122and a flash memory module124. In the present embodiment, each of the plurality of storage devices120_1-120_B can be a SSD or any storage device having a flash memory module. The host device110can be a central processing unit or other electronic devices or components that can be used to access the storage devices120_1-120_B. The electronic device100can be a server, a personal computer, a laptop computer or any portable electronic device. It should be noticed that although a plurality of storage devices120_1-120_B are shown inFIG.1, in some embodiments, the electronic device100may have a single storage device120_1.

FIG.2is a diagram illustrating the storage device120_1according to an embodiment of the present invention. As shown inFIG.2, the flash memory controller122comprises a microprocessor212, a read only memory (ROM)212M, a control logic214, a buffer memory216and an interface logic218. The read only memory212M is configured to store a code212C, and the microprocessor212is configured to execute the code212C to control access of the flash memory module124. The control logic214includes an encoder232and a decoder234, wherein the encoder232is configured to encode data which is written in the flash memory module124to generate a corresponding check code (also known as an error correction code (ECC)), and the decoder234is configured to decode data read from the flash memory module124.

In a general situation, the flash memory module124includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks. The flash memory controller122performs a block-based erase operation upon the flash memory module124. In addition, a block has a specific number of pages, wherein the flash memory controller122performs a page-based write operation upon the flash memory module124. In the present embodiment, the flash memory module124is a 3D NAND-type flash memory module.

In practice, through the microprocessor212executing the code212C, the flash memory controller122may use its own internal components to perform many control operations. For example, the flash memory controller122uses the control logic214to control access of the flash memory module124(especially access of at least one block or at least one page), uses the buffer memory216to perform a required buffering operation, and uses the interface logic218to communicate with a host device110. The buffer memory216is implemented by a random access memory (RAM). For example, the buffer memory216may be a static RAM (SRAM), but the present invention is not limited thereto. In addition, the flash memory controller122is coupled to a dynamic random access memory (DRAM)240. It should be noticed that a DRAM240may also be included in the flash memory controller122. For example, the DRAM240and the flash memory controller122may coexist in the same package.

In one embodiment, the storage device120_1conforms to the NVMe specification. That is, the interface logic218conforms to a specific communication specification such as a peripheral component interconnect (PCI) specification a PCI-Express (PCIe) or specification, and performs communication according to the specific communication specification. For example, the interface logic218communicates with the host device110via a connector.

FIG.3is a diagram illustrating a block200of the flash memory module124according to an embodiment of the present invention, wherein the flash memory module124is a 3D NAND-type flash memory module. As shown inFIG.3, the block200includes a plurality of memory cells, such as floating gate transistors202shown inFIG.3or other charge trapping components. A 3D NAND-type flash memory structure is formed through a plurality of bit lines (only BL1-BL3 are shown inFIG.3) and a plurality of word lines (e.g., WL0-WL2 and WL4-WL6 shown inFIG.3). Taking a top plane inFIG.3as an example, all floating gate transistors on the word line WL0 form at least one page, all floating gate transistors on the word line WL1 form at least another one page, all floating gate transistors on the word line WL2 form at least yet another one page, and so on. In addition, the definition between the word line WL0 and the page (logic page) may vary depending on a writing method of the flash memory. In detail, when data are stored using a single-level cell (SLC) means, all floating gate transistors on the word line WL0 correspond to only one logic page; when data are stored using a multi-level cell (MLC) means, all floating gate transistors on the word line WL0 correspond to two logic pages; when data are stored using a triple-level cell (TLC) means, all floating gate transistors on the word line WL0 correspond to three logic pages; and when data are stored using a quad-level cell (QLC) means, all floating gate transistors on the word line WL0 correspond to four logic pages. The 3D NAND-type flash memory structure and the relationship between word lines and pages are obvious to those skilled in the art. For simplification, no further illustration is provided.

In the present embodiment, the host device110can configure at least a part of the flash memory module124as a zoned namespace by sending a settling command set, such as a zoned namespace command set. Referring toFIG.4, the host device110can send a settling command set to the flash memory controller122, such that the flash memory module124has at least one zoned namespace (in the present embodiment, taking the zoned namespaces410_1and410_2as examples) and at least one general storage space (in this embodiment, taking the general storage spaces420_1and420_2as examples). The zoned namespace410_1is divided into multiple zones for access, and the host device110must perform a logical block address (LBA)-based data writing operation in the zoned namespace410_1. A logical block address (or logical address in brief) can represent one 512-byte data or one 4-kilobyte data, and the host device110needs to write data with consecutive logical addresses to a zone. Specifically, referring toFIG.5, the zoned namespace410_1is divided into multiple zones (e.g., zones Z0, Z1, Z2, Z3, etc.), where the size of the zone is set by the host device110, but the size of each zone is the same. The logical addresses within each zone must be continuous, and there will be no overlapping logical addresses between the zones, that is, one logical address can only exist in one zone. For example, if the size of each zone is “x” logical addresses, and the starting logical address of the zone Z3 is LBA k, then the zone Z3 is used to store data with the logical addresses LBA k, LBA (k+1), LBA (k+2), LBA (k+3), . . . , LBA (k+x−1). In one embodiment, the logical addresses of adjacent zones are also continuous. For example, the zone Z0 is used to store data with logical addresses LBA_1-LBA_2000, the zone Z1 is used to store data with logical addresses LBA_2001-LBA_4000, the zone Z2 is used to store data with logical addresses LBA_4001-LBA_6000, the zone Z3 is used to store data with logical addresses LBA_6001-LBA_8000, and so on. In addition, the amount of data corresponding to a logical address can be determined by the host device110. For example, the amount of data corresponding to one logical address can be 4 kilobytes (KB).

In addition, when being written in each zone, the data is written according to the sequence of the logical addresses of the data. In detail, the flash memory controller122sets a write point according to the written data to control the writing sequence of the data. In detail, assuming that the zone Z1 is used to store data with logical addresses LBA_2001-LBA_4000, after the host device110transmits the data corresponding to the logical addresses LBA_2001-LBA_2051to the flash memory controller122, the flash memory controller122sets the write point to the next logical address LBA_2052. If the host device110subsequently transmits data belonging to the same zone but does not have the logical address LBA_2052, for example, the host device110transmits data with the logical address LBA_3000, the flash memory controller122rejects the data writing operation and returns the message of writing failure to the host device110; in other words, only when the logical address of the received data is the same as the logical address pointed to by the write point, the flash memory controller122allows the data writing operation. In addition, if data in multiple zones are written alternately, each zone can have its own write point.

In order to make the zoned namespace410_1and410_2work well under the control of the host device110and the storage device120_1, a size of the each zone needs to be properly determined.FIG.6is a flowchart of an initialization procedure of the storage device120_1according to a first embodiment of the present invention. In Step600, the flow starts, and the flash memory module124has not yet started configuration. In Step602, the host device110starts to activate the storage device120_1, and the host device110sends a settling command set to the flash memory controller122. In Step604, the flash memory controller122starts to configure the flash memory module124based on a best performance or bandwidth setting, to generate parameter information. Specifically, assuming that the flash memory module124comprises plurality of channels CH_1-CH_N, and each of the channels CH_1-CH_N correspond to a plurality of logical units (LUN) that are enabled by using chip enable signals CE_1-CE_M. For example, the channel CH_1corresponds to the LUNs710_1-710_M that are enabled by using the chip enable signals CE_1-CE_M, and the channel CH_N corresponds to the LUNs710(M*(N−1)+1)-710_(M*N) that are enabled by using the chip enable signals CE_1-CE_M. In this embodiment, the channels CH_1-CH_N can be processed in parallel to access one of the corresponding LUNs simultaneously. For example, when the chip enable signal CE_1is enabled and the other chip enable signals are disabled, the first LUN of each channel is allowed to be accessed by the host device110; and when the chip enable signal CE_2is enabled and the other chip enable signals are disabled, the second LUN of each channel is allowed to be accessed by the host device110, and so on. In addition, each one of the LUNs can be a die within the flash memory module124, or a die may comprise two or more LUNs.

In one embodiment, quantity of the channels and quantity of the chip enable signals can be determined according to designer's consideration, for example, the storage device120_1may have sixteen channels and four chip enable signals (i.e., N is equal to “16”, and M is equal to “4”).

Because the flash memory module124supports the plurality of channels CH_1-CH_N, and the plurality of channels CH_1-CH_N can be accessed simultaneously, the flash memory controller122can configure the flash memory module124based on the number of channels supported by the flash memory module124.

FIG.8is a diagram illustrating a super block configuration of the flash memory module124according to one embodiment of the present invention. As shown inFIG.8, each of the LUNs710_1-710_(M*N) comprises a plurality of blocks B1-BK. In the process of the super block configuration, the flash memory controller122configures blocks B1of all LUNs710_1-710_(M*N) as a super block810_1, configures blocks B2of all LUNs710_1-710_(M*N) as a super block810_2, configures blocks B3of all LUNs710_1-710_(M*N) as a super block810_3, . . . , and configures blocks BK of all LUNs710_1-710_(M*N) as a super block810_K. The super block is a logical collection block set by the flash memory controller122to facilitate management of the storage device120_1, and is not a physical collection block. InFIG.8, the super block810_1comprises M*N blocks, and the flash memory controller122treats the super block810_1as a normal block when accessing the super block810_1. For example, the super block810_1itself is an erasing unit, that is, although the M*N blocks B1of the super block810_1can be erased separately, the flash memory controller122must erase the M*N blocks B1together. In this embodiment, the flash memory controller122can temporarily determine the zone whose size is equal to the size of one superblock.

FIG.9is a diagram illustrating a super page configuration of the flash memory module124according to one embodiment of the present invention. Taking the super block810_1as an example, each of the blocks B1comprises a plurality of pages P1-PA. In the process of the super page configuration, the flash memory controller122configures pages P1of blocks B1of all LUNs710_1-710_(M*N) as a super page910_1, configures pages P2of blocks B1of all LUNs710_1-710_(M*N) as a super page910_2, configures pages P3of blocks B1of all LUNs710_1-710_(M*N) as a super page910_3, . . . , and configures pages PA of blocks B1of all LUNs710_1-710_(M*N) as a super page910A. In addition, regarding the data writing of the super block810_1, the super pages910_1-910A are written by the flash memory controller122sequentially, in other words, the flash memory controller122does not start data writing of the super page910_2until data writing of the super page910_1is completed.

After the above configurations of the flash memory module124are completed, the flash memory controller122generates the parameter information, wherein the parameter information comprises a zone size (i.e., a size of one super block), a block size, a page size, a super page size, a number of pages in one block, a number of LUNs corresponding to one super block, a number of zones supported by the flash memory module124(i.e., a number of super blocks within the zoned namespace, that is the number “K” inFIG.8).

In Step606, the flash memory controller122transmits the parameter information to the host device110.

In Step608, the host device110receives the parameter information from the flash memory controller122, and uses the parameter information for the setting of the zone. For example, the host device110directly uses the zone size (i.e., the size of one super block) provided by the flash memory controller122as the subsequent setting when transmitting data of the zone (s).

In the embodiment shown inFIGS.6-9, by using the flash memory controller122to actively detect the number of channels of the flash memory module124to determine the zone size with the best performance or bandwidth, and the flash memory controller122directly notifies the host device110to use this zone size for the subsequent zone setting and data transmission, the host device110can access the storage device120_1with better efficiency and performance.

FIG.10is a flowchart of an initialization procedure of the storage device120_1according to a second embodiment of the present invention. In Step1000, the flow starts, and the flash memory module124has not yet started configuration. In Step1002, the host device110starts to activate the storage device120_1, and the host device110sends a settling command set to the flash memory controller122. In Step1004, the flash memory controller122transmits a plurality of configuration settings to the host device110, wherein the plurality of configuration settings comprise at least two different zone sizes.

In one embodiment, one of the plurality of configuration settings may be the super block configuration shown inFIG.8and the super page configuration shown inFIG.9, that is, the configuration setting comprises zone size (size of super block) equal to M*N blocks. In addition, the configuration setting may further comprises a block size, a page size, a super page size, a number of pages in one block, a number of LUNs corresponding to one super block, a number of zones supported by the flash memory module124(i.e., the number “K” inFIG.8).

In one embodiment, the plurality of configuration settings may have a super block configuration that only corresponds to a portion of channels. TakingFIG.11as an example, each of the LUNs710_1-710_(M*N/2) corresponding to the channels CH_1-CH (N/2) comprises a plurality of blocks B1-BK. In the process of the super block configuration, the flash memory controller122configures blocks B1of all LUNs710_1-710_(M*N/2) as a super block1110_1, configures blocks B2of all LUNs710_1-710_(M*N/2) as a super block1110_2, configures blocks B3of all LUNs710_1-710_(M*N/2) as a super block1110_3, . . . , and configures blocks BK of all LUNs710_1-710_(M*N/2) as a super block1110_K. In addition, each of the LUNs710_(M*N/2+1)-710_(M*N) corresponding to the channels CH (N/2+1)-CH_(N) comprises a plurality of blocks B1-BK, and the flash memory controller122configures blocks B1of all LUNs710_(M*N/2+1)-710_(M*N) as a super block1210_1, configures blocks B2of all LUNs710_(M*N/2+1)-710_(M*N) as a super block1210_2, configures blocks B3of all LUNs710_(M*N/2+1)-710_(M*N) as a super block1210_3, . . . , and configures blocks BK of all LUNs710_(M*N/2+1)-710_(M*N) as a super block1210_K. InFIG.11, the super block1110_1comprises M*N/2 blocks, and the flash memory controller122treats the super block1110_1as a normal block when accessing the super block1110_1. For example, the super block1110_1itself is an erasing unit, that is, although the M*N/2 blocks B1of the super block1110_1can be erased separately, the flash memory controller122must erase the M*N/2 blocks B1together. In this embodiment, the flash memory controller122can temporarily determine the zone whose size is equal to the size of one superblock.

FIG.12is a diagram illustrating a super page configuration of the flash memory module124according to one embodiment of the present invention. Taking the super block1110_1as an example, each of the blocks B1comprises a plurality of pages P1-PA. In the process of the super page configuration, the flash memory controller122configures pages P1of blocks B1of all LUNs710_1-710_(M*N/2) as a super page1210_1, configures pages P2of blocks B1of all LUNs710_1-710_(M*N/1) as a super page1210_2, configures pages P3of blocks B1of all LUNs710_1-710_(M*N/2) as a super page1210_3, . . . , and configures pages PA of blocks B1of all LUNs710_1-710_(M*N/2) as a super page1210_A. In addition, regarding the data writing of the super block1110_1, the super pages1210_1-1210_A are written by the flash memory controller122sequentially, in other words, the flash memory controller122does not start data writing of the super page1210_2until data writing of the super page1210_1is completed.

In this embodiment, one of the plurality of configuration settings may be the super block configuration shown inFIG.10and the super page configuration shown inFIG.11, that is, the configuration setting comprises zone size (size of super block) equal to M*N/2 blocks. In addition, the configuration setting may further comprises a block size, a page size, a super page size, a number of pages in one block, a number of LUNs corresponding to one super block, a number of zones supported by the flash memory module124(i.e., “2K”, wherein “K” is the number shown inFIG.8).

In other embodiments, the plurality of configuration settings may have a super block configuration that corresponds to different number of channels. For example, each super block may comprises blocks of two or three channels, that is the zone size may be equal to 2*M blocks or 3*M blocks.

In Step1006, after receiving the configuration settings from the flash memory controller122, the host device110selects one of the configuration settings according to its application. For example, if the host device110generally writes data with continuous logical addresses into the storage device120_1, the host device110may select the configuration setting with higher bandwidth such as the embodiments shown inFIG.8andFIG.9; and if the host device110generally writes random data into the storage device120_1, the host device110may select the configuration setting with smaller zone size such as the embodiments shown inFIG.11andFIG.12. Then, the host device110sends a response indicating which one of the configuration settings is selected to the flash memory controller122.

In Step1008, the flash memory controller122receives the response from the host device110, and uses the selected configuration setting to start to configure the flash memory module124. For example, if the host device110selects the above configuration setting whose zone size is equal to M*N blocks, the flash memory controller122may configure the flash memory module124as the embodiments shown inFIG.8andFIG.9. If the host device110selects the above configuration setting whose zone size is equal to M*N/2 blocks, the flash memory controller122may configure the flash memory module124as the embodiments shown inFIG.11andFIG.12.

In the embodiment shown inFIGS.10-12, by using the flash memory controller122to provide a plurality of configuration settings, the host device110can select the most suitable configuration setting based on its application, for the flash memory controller122to perform the super block configuration and super page configuration. Therefore, the host device110can access the storage device120_1with better efficiency and performance.

FIG.13is a flowchart of an initialization procedure of the storage device120_1according to a third embodiment of the present invention. In Step1300, the flow starts, and the flash memory module124has not yet started configuration. In Step1302, the host device110starts to activate the storage device120_1, and the host device110sends a settling command set to the flash memory controller122. In Step1304, the flash memory controller122starts to configure the flash memory module124based on a best performance or bandwidth setting, to generate parameter information. For example, the flash memory controller122configures the flash memory module124as the embodiments shown inFIG.8andFIG.9. After the above configurations of the flash memory module124are completed, the flash memory controller122generates the parameter information, wherein the parameter information comprises a zone size (i.e., a size of one super block), a block size, a page size, a super page size, a number of pages in one block, a number of LUNs corresponding to one super block, a number of zones supported by the flash memory module124(i.e., the number “K” inFIG.8).

In Step1306, the flash memory controller122transmits the parameter information to the host device110.

In Step1308, the flash memory controller122transmits a plurality of configuration settings to the host device110, wherein the plurality of configuration settings comprise at least two different zone sizes. The contents of plurality of configuration settings can refer to the above embodiment show inFIG.10.

In Step1310, the host device110determines if directly using the parameter information or selecting one configuration settings whose zone size is different from the parameter information. If the host device110selects one of configuration settings, the flow enters Step1312; otherwise, the flow enters Step1314.

In Step1312, the host device110sends a response indicating which one of the configuration settings is selected to the flash memory controller122, and the flash memory controller112formats the zoned namespace such as410_1, and uses the selected configuration setting to configure the zoned namespace of the flash memory module124. For example, the super block configuration shown inFIG.8is formatted, and a new super block configuration shown inFIG.11is performed.

In Step1314, the host device110receives the parameter information from the flash memory controller122, and uses the parameter information for the setting of the zone. For example, the host device110directly uses the zone size (i.e., the size of one super block) provided by the flash memory controller122as the subsequent setting when transmitting data of the zone (s).

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.