Patent ID: 12230622

DETAILED DESCRIPTION

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Packaging of an integrated circuit (IC) chip can involve attaching the IC chip to a substrate (e.g., a packaging substrate) which, among other things, provides mechanical support and electrical connections between the chip and other electronic components of a device. Substrate types include, for example, cored substrates, including thin core, thick core (laminate bismaleimide-triazine resin (BT resin) or FR-4 type fibrous board material), and laminate core, as well as coreless substrates. Cored package substrates, for example, can be built up layer by layer around a central core, with layers of conductive material (usually copper) separated by layers of insulating dielectric, with interlayer connections being formed with through holes or microvias (vias).

High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM). HBM achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4 or GDDR5. This is achieved by stacking up to eight dynamic random-access memory (DRAM) dies and an optional base die which can include buffer circuitry and test logic. The stack is often connected to the memory controller on a GPU or CPU through a substrate, such as a silicon interposer. Alternatively, the memory die could be stacked directly on the CPU or GPU chip. Within the stack the die are vertically interconnected by through-silicon vias (TSVs) and microbumps. The HBM DRAM uses wide-interface architecture to achieve high-speed, low-power operation.

FIG.1is a schematic, cross-sectional diagram showing an exemplary electronic device1with stacked printed circuit boards (PCBs) in accordance with one embodiment of the disclosure. In some embodiments, the electronic device1may serve as a three-dimensional (3D) assembly including at least two vertically stacked PCBs respectively mounted on opposite sides of a semiconductor package. As shown inFIG.1, the electronic device1comprises a main PCB assembly10including, but not limited to, a bottom PCB PB and a semiconductor package CP mounted on an upper surface S1of the bottom PCB PB. In some embodiments, for example, the semiconductor package CP may comprise a substrate100and a semiconductor die101, such as a logic die, mounted on a top surface (die-attach surface)100aof the substrate100. The semiconductor die101may comprise a flip-chip die, a wire-bonding die, or a fan-out die. The semiconductor die101may be connected to the top surface100aof the substrate100via a plurality of connecting elements111such as bumps or metal pillars, but not limited thereto. The semiconductor die101and the top surface100aof the substrate100may be encapsulated by a molding compound120such as epoxy resin.

According to an embodiment, for example, additional components103and105may be mounted on the surfaces of the bottom PCB PB. The additional components103and105may comprise active or passive components such as IC chips, capacitors, resistors or inductors. Although the semiconductor die101is shown to be mounted on the top surface100aof the substrate100in a flip-chip manner, it is understood that in some embodiments the semiconductor die101may be mounted on the substrate100by using wire-bonding techniques. In some embodiments, the semiconductor package CP may include a fan-out die.

In some embodiments, the semiconductor package CP may include one or more logic dies, including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SOC), a field-programmable gate array (FPGA), a microcontroller unit (MCU), a power management integrated circuit (PMIC) die, a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), or the like, or any combinations thereof.

According to an embodiment, for example, the substrate100may be a wiring substrate and may be formed of polymer materials such as bismaleimide triazine (BT) laminates and/or build-up films known in the art. In some embodiments, the substrate100may be a re-distribution layer (RDL) substrate comprising dielectric layers and conductive layers, and may have a thinner thickness compared to conventional package substrates. It is to be understood that the substrate100may be a single layer or a multi-layer structure.

According to an embodiment, for example, the substrate100may comprise a plurality of connection pads100pdisposed on or near the top surface100aof the substrate100. According to an embodiment, for example, the substrate100may comprise a plurality of conductive traces100tinterconnecting the plurality of connection pads100pwith a plurality of ball pads100sdistributed on or near a bottom surface100bof the substrate100. Solder balls SB are disposed on the ball pads100s, respectively. In some embodiments, at least one passive device PE may be mounted on the bottom surface100bof the substrate100using surface mount technique (SMT).

According to an embodiment, a plurality of through mold vias (TMVs)122may be disposed in the molding compound120. The TMVs122penetrate through the entire thickness of the molding compound120, thereby forming terminals122ton the top surface S2of the semiconductor package CP. According to an embodiment, for example, a PCB assembly50and a PCB60may be mounted on the corresponding terminals122ton the top surface S2of the semiconductor package CP through connecting elements502and602, respectively. According to an embodiment, for example, the connecting elements502and602may comprise solder balls or any suitable conducive joints known in the art. According to an embodiment, for example, the PCB assembly50may comprise a PCB52and components503and505such as, memory devices, antenna devices or radio-frequency (RF) devices mounted on opposite sides of the PCB52. According to an embodiment, the PCB assembly50is physically separated from the PCB60and disposed on the top surface S2of the semiconductor package CP in a side-by-side manner.

It is advantageous to use the present disclosure because by connecting some signals to the PCB assembly50and the PCB60through the TMVs122, the bottom ball count and the size of the semiconductor package CP can both be reduced.

FIG.2is a schematic, cross-sectional diagram showing an exemplary electronic device2with stacked PCBs in accordance with another embodiment of the disclosure, wherein like regions, layers or elements are designated by like numeral numbers or labels. In some embodiments, the electronic device2may serve as a 3D assembly including at least two vertically stacked PCBs respectively mounted on opposite sides of a semiconductor package. As shown inFIG.2, likewise, the electronic device2comprises a main PCB assembly10including, but not limited to, a bottom PCB PB and a semiconductor package CP mounted on an upper surface S1of the bottom PCB PB. In some embodiments, for example, the semiconductor package CP may comprise a substrate100and a semiconductor die101, such as a logic die, mounted on a top surface (die-attach surface)100aof the substrate100. The semiconductor die101may be connected to the top surface100aof the substrate100via a plurality of through silicon vias (TSVs)110that penetrates through the entire thickness of the semiconductor die101. The peripheral sidewalls of the semiconductor die101and the top surface100aof the substrate100may be encapsulated by a molding compound120such as epoxy resin.

According to an embodiment, for example, additional components103and105may be mounted on the surfaces of the bottom PCB PB. The additional components103and105may comprise active or passive components such as IC chips, capacitors, resistors or inductors.

In some embodiments, the semiconductor package CP may include one or more logic dies, including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SOC), a field-programmable gate array (FPGA), a microcontroller unit (MCU), a power management integrated circuit (PMIC) die, a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), or the like, or any combinations thereof.

According to an embodiment, for example, the substrate100may be a wiring substrate and may be formed of polymer materials such as bismaleimide triazine (BT) laminates and/or build-up films known in the art. In some embodiments, the substrate100may be a re-distribution layer (RDL) substrate comprising dielectric layers and conductive layers, and may have a thinner thickness compared to conventional package substrates. It is to be understood that the substrate100may be a single layer or a multi-layer structure.

According to an embodiment, for example, the substrate100may comprise a plurality of connection pads100pdisposed on or near the top surface100aof the substrate100. According to an embodiment, for example, the substrate100may comprise a plurality of conductive traces100tinterconnecting the plurality of connection pads100pwith a plurality of ball pads100sdistributed on or near a bottom surface100bof the substrate100. Solder balls SB are disposed on the ball pads100s, respectively. In some embodiments, at least one passive device PE may be mounted on the bottom surface100bof the substrate100using surface mount technique (SMT).

According to an embodiment, the semiconductor die101is mounted on the top surface100aof the substrate100. According to an embodiment, the semiconductor die101has a top surface (or active surface)101aand a passive rear surface101b. The circuit elements such as transistors are fabricated on or near the top surface101aof the semiconductor die101. According to an embodiment, the passive rear surface101bof the semiconductor die101may be coupled to the top surface100aof the substrate100by using methods known in the art, for example, SMT or adhesion. That is, the semiconductor die101is mounted on the top surface100aof the substrate100with a “face-up” configuration. According to an embodiment, the semiconductor die101may be electrically connected to the substrate100and the solder balls SB on the bottom surface100bof the substrate100through the TSVs110, which are mainly for power/ground connection of the semiconductor die101or HBM. According to an embodiment, for example, the TSVs110may be power or ground TSVs for transmitting power or ground signals.

According to an embodiment, the electronic device2further comprises a middle re-distribution layer (RDL) structure200on the semiconductor die101. According to an embodiment, the middle RDL structure200may comprise dielectric layers210and interconnect structures220. The interconnect structures220may be electrically connected to a plurality of RDL pads230. According to an embodiment, the top surface101aof the semiconductor die101is electrically connected to the middle RDL structure200through connecting elements BP such as micro-bumps, metal pillars, or the like. According to an embodiment, the gap between the middle RDL structure200and the top surface101aof the semiconductor die101may be filled with an underfill material UF such as an epoxy resin, but is not limited thereto. According to an embodiment, a plurality of through mold vias (TMVs)122may be disposed in the molding compound120. The TMVs122may be electrically connected to the interconnect structures220of the middle RDL structure200.

According to an embodiment, for example, a PCB assembly50and a PCB60may be mounted on the corresponding RDL pads230of the middle RDL structure200. According to an embodiment, for example, the PCB assembly50may comprise a PCB52and components503and505mounted on opposite sides of the PCB52through connecting elements502and602, respectively. According to an embodiment, for example, the connecting elements502and602may comprise solder balls or any suitable conducive joints known in the art. According to an embodiment, the PCB assembly50is physically separated from the PCB60and disposed on the middle RDL structure200with the PCB60in a side-by-side manner.

According to an embodiment, a memory component300is directly mounted on the middle RDL structure200and may be disposed between the PCB60and the PCB assembly50. According to an embodiment, the memory component300may protrude from top surfaces of the PCB60and the PCB assembly50. According to an embodiment, the memory component300may comprise a High-Bandwidth Memory (HBM) including multiple DRAM dies301stacked on one another and the stacked DRAM dies301are vertically interconnected by through silicon vias (TSVs)310and microbumps BT. According to an embodiment, the memory component300may further comprise a DRAM base302which can include buffer circuitry and test logic. In some embodiments, the DRAM base302may include a DRAM controller.

According to an embodiment, the memory component300may be aligned with the underlying semiconductor die101and disposed at or near the center of the semiconductor die101when viewed from above. That is, the center of the memory component300may be aligned with the center of the semiconductor die101. When viewed from above, the memory component300completely overlaps with the underlying semiconductor die101. According to an embodiment, the DRAM base302is electrically coupled to the middle RDL structure200and signals such as power or ground may be transmitted to the solder balls SB on the bottom surface100bof the substrate100via the shorter conductive path comprised at least of the interconnect structures220of the middle RDL structure200, the connecting elements BP, the TSVs110of the semiconductor die101, and the conductive traces100tof the substrate100. Optionally, some of the power or ground signals may be transmitted to the solder balls SB on the bottom surface100bof the substrate100via the connecting elements BP, the interconnect structures220of the middle RDL structure200, the TMVs122, and the conductive traces100tof the substrate100.

FIG.3is a schematic, cross-sectional diagram showing an exemplary electronic device3with stacked PCBs in accordance with still another embodiment of the disclosure, wherein like regions, layers or elements are designated by like numeral numbers or labels. One difference between the electronic device3inFIG.3and the electronic device2inFIG.2is that a heat sink80is mounted on the middle RDL structure200around the memory component300to improve thermal performance and the robustness of the electronic device3. According to an embodiment, the heat sink80may have an annular shape and surround the memory component300, but not limited thereto.

FIG.4is a schematic, cross-sectional diagram showing an exemplary electronic device4with stacked PCBs in accordance with still another embodiment of the disclosure, wherein like regions, layers or elements are designated by like numeral numbers or labels. In some embodiments, the electronic device4may serve as a 3D assembly including at least two vertically stacked PCBs respectively mounted on opposite sides of a semiconductor package. As shown inFIG.4, likewise, the electronic device4comprises a main PCB assembly10including, but not limited to, a bottom PCB PB and a semiconductor package CP mounted on an upper surface S1of the bottom PCB PB. In some embodiments, for example, the semiconductor package CP may comprise a substrate100and a semiconductor die101, such as a logic die, mounted on a top surface100aof the substrate100. The semiconductor die101may be connected to the top surface100aof the substrate100via a plurality of TSVs110that penetrates through the entire thickness of the semiconductor die101. The peripheral sidewalls of the semiconductor die101and the top surface100aof the substrate100may be encapsulated by a molding compound120such as epoxy resin.

According to an embodiment, for example, additional components103and105may be mounted on the surfaces of the bottom PCB PB. The additional components103and105may comprise active or passive components such as IC chips, capacitors, resistors or inductors.

In some embodiments, the semiconductor package CP may include one or more logic dies, including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SOC), a field-programmable gate array (FPGA), a microcontroller unit (MCU), a power management integrated circuit (PMIC) die, a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), or the like, or any combinations thereof.

According to an embodiment, for example, the substrate100may be a wiring substrate and may be formed of polymer materials such as BT laminates and/or build-up films known in the art. In some embodiments, the substrate100may be a RDL substrate comprising dielectric layers and conductive layers, which have thinner thickness compared to conventional package substrates. It is to be understood that the substrate100may be a single layer or a multi-layer structure.

According to an embodiment, for example, the substrate100may comprise a plurality of connection pads100pdisposed on or near the top surface100aof the substrate100. According to an embodiment, for example, the substrate100may comprise a plurality of conductive traces100tinterconnecting the plurality of connection pads100pwith a plurality of ball pads100sdistributed on or near a bottom surface100bof the substrate100. Solder balls SB are disposed on the ball pads100s, respectively. In some embodiments, at least one passive device PE may be mounted on the bottom surface100bof the substrate100using SMT.

According to an embodiment, the semiconductor die101is mounted on the top surface100aof the substrate100. According to an embodiment, the semiconductor die101has a top surface (or active surface)101aand a passive rear surface101b. The circuit elements such as transistors are fabricated on or near the top surface101aof the semiconductor die101. According to an embodiment, the passive rear surface101bof the semiconductor die101may be coupled to the top surface100aof the substrate100by using methods known in the art, for example, SMT or adhesion. That is, the semiconductor die101is mounted on the top surface100aof the substrate100with a “face-up” configuration. According to an embodiment, the semiconductor die101may be electrically connected to the substrate100and the solder balls SB on the bottom surface100bof the substrate100through the TSVs110, which are mainly for power/ground connection of the semiconductor die101or HBM. According to an embodiment, for example, the TSVs110may be power or ground TSVs for transmitting power or ground signals.

According to an embodiment, likewise, the electronic device4comprises a middle RDL structure200on the semiconductor die101. According to an embodiment, the middle RDL structure200may comprise dielectric layers210and interconnect structures220. The interconnect structures220may be electrically connected to a plurality of RDL pads230. According to an embodiment, the top surface101aof the semiconductor die101is electrically connected to the middle RDL structure200through connecting elements BP such as micro-bumps, metal pillars, or the like. According to an embodiment, the gap between the middle RDL structure200and the top surface101aof the semiconductor die101may be filled with an underfill material UF such as an epoxy resin, but is not limited thereto. According to an embodiment, a plurality of TMVs122may be disposed in the molding compound120. The TMVs122may be electrically connected to the interconnect structures220of the middle RDL structure200.

According to an embodiment, a memory package30is directly mounted on the middle RDL structure200. According to an embodiment, the memory package30comprises a memory component300comprising a HBM including multiple DRAM dies301stacked on one another and the stacked DRAM dies301are vertically interconnected by TSVs310and microbumps BT. According to an embodiment, the memory component300may further comprise a DRAM base302which can include buffer circuitry and test logic. In some embodiments, the DRAM base302may include a DRAM controller. According to an embodiment, the memory component300is packaged by a molding compound320.

According to an embodiment, the memory component300may be aligned with the underlying semiconductor die101and disposed at or near the center of the semiconductor die101when viewed from above. That is, the center of the memory component300may be aligned with the center of the semiconductor die101. When viewed from above, the memory component300completely overlaps with the underlying semiconductor die101. According to some embodiments, the memory component300may not be aligned with the underlying semiconductor die101.

According to an embodiment, the DRAM base302is electrically coupled to the middle RDL structure200and signals such as power or ground may be transmitted to the solder balls SB on the bottom surface100bof the substrate100via the shorter conductive path comprised at least of the interconnect structures220of the middle RDL structure200, the connecting elements BP, the TSVs110of the semiconductor die101, and the conductive traces100tof the substrate100. Optionally, some of the power or ground signals may be transmitted to the solder balls SB on the bottom surface100bof the substrate100via the connecting elements BP, the interconnect structures220of the middle RDL structure200, the TMVs122, and the conductive traces100tof the substrate100.

According to an embodiment, for example, a PCB assembly50and a PCB60may be mounted on the memory package30in a side-by-side manner. According to an embodiment, for example, the PCB assembly50and the PCB60may be electrically connected to the corresponding RDL pads230of the middle RDL structure200via the TMVs322in the molding compound320. According to an embodiment, for example, the PCB assembly50may comprise a PCB52and components503and505mounted on opposite sides of the PCB52, respectively.

FIG.5is a schematic, cross-sectional diagram showing an exemplary electronic device5with stacked PCBs in accordance with still another embodiment of the disclosure, wherein like regions, layers or elements are designated by like numeral numbers or labels. In some embodiments, the electronic device5may serve as a 3D assembly including at least two vertically stacked PCBs respectively mounted on opposite sides of a semiconductor package. As shown inFIG.5, likewise, the electronic device5comprises a main PCB assembly10including, but not limited to, a bottom PCB PB and a semiconductor package CP mounted on an upper surface S1of the bottom PCB PB. In some embodiments, for example, the semiconductor package CP may comprise a substrate100and a semiconductor die101, such as a logic die, mounted on a top surface100aof the substrate100. The semiconductor die101may be connected to the top surface100aof the substrate100via a plurality of TSVs110that penetrates through the entire thickness of the semiconductor die101. The peripheral sidewalls of the semiconductor die101and the top surface100aof the substrate100may be encapsulated by a molding compound120such as epoxy resin.

According to an embodiment, for example, additional components103and105may be mounted on the surfaces of the bottom PCB PB. The additional components103and105may comprise active or passive components such as IC chips, capacitors, resistors or inductors.

In some embodiments, the semiconductor package CP may include one or more logic dies, including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SOC), a field-programmable gate array (FPGA), a microcontroller unit (MCU), a power management integrated circuit (PMIC) die, a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), or the like, or any combinations thereof.

According to an embodiment, for example, the substrate100may be a wiring substrate and may be formed of polymer materials such as BT laminates and/or build-up films known in the art. In some embodiments, the substrate100may be a RDL substrate comprising dielectric layers and conductive layers, which have thinner thickness compared to conventional package substrates. It is to be understood that the substrate100may be a single layer or a multi-layer structure.

According to an embodiment, for example, the substrate100may comprise a plurality of connection pads100pdisposed on or near the top surface100aof the substrate100. According to an embodiment, for example, the substrate100may comprise a plurality of conductive traces100tinterconnecting the plurality of connection pads100pwith a plurality of ball pads100sdistributed on or near a bottom surface100bof the substrate100. Solder balls SB are disposed on the ball pads100s, respectively. In some embodiments, at least one passive device PE may be mounted on the bottom surface100bof the substrate100using SMT.

According to an embodiment, the semiconductor die101is mounted on the top surface100aof the substrate100with a “face-down” configuration with its top surface (or active surface)101adirectly facing the substrate100. According to an embodiment, the semiconductor die101may be electrically connected to the substrate100and the solder balls SB on the bottom surface100bof the substrate100via the TSVs110, which are mainly for power/ground connection of the semiconductor die101or HBM. According to an embodiment, for example, the TSVs110may be power or ground TSVs for transmitting power or ground signals.

According to an embodiment, a memory component300such as HBM is directly mounted on the semiconductor die101. According to an embodiment, the memory component300may be electrically connected to the semiconductor die101through the connecting elements BM such as micro-bumps or metal pillars. According to an embodiment, the memory component300may comprise multiple DRAM dies301stacked on one another. The stacked DRAM dies301are vertically interconnected by TSVs310and microbumps BT. According to an embodiment, the memory component300may further comprise a DRAM base302which can include buffer circuitry and test logic. In some embodiments, the DRAM base302may include a DRAM controller. According to an embodiment, the semiconductor die101and the memory component300may be packaged in one unified molding compound320.

According to an embodiment, the memory component300may be offset from the center of the underlying semiconductor die101, That is, the center of the memory component300is not aligned with and is deviated from the center of the semiconductor die101. According to an embodiment, signals such as power or ground may be transmitted to the solder balls SB on the bottom surface100bof the substrate100via the shorter conductive path comprised of the connecting elements BM, the TSVs110of the semiconductor die101, and the conductive traces100tof the substrate100.

According to an embodiment, for example, a PCB assembly50and a PCB60may be mounted on the memory package30in a side-by-side manner. According to an embodiment, for example, the PCB assembly50and the PCB60may be electrically connected to the substrate100via the TMVs322in the molding compound320. According to an embodiment, for example, the PCB assembly50may comprise a PCB52and components503and505mounted on opposite sides of the PCB52, respectively.

FIG.6is a schematic, cross-sectional diagram showing an exemplary electronic device6with stacked PCBs in accordance with yet another embodiment of the disclosure, wherein like regions, layers or elements are designated by like numeral numbers or labels. In some embodiments, the electronic device6may serve as a 3D assembly including at least two vertically stacked PCBs respectively mounted on opposite sides of a semiconductor package.

As shown inFIG.6, the electronic device6comprises a main PCB assembly10including, but not limited to, a bottom PCB PB and a semiconductor package CP mounted on an upper surface S1of the bottom PCB PB. In some embodiments, for example, the semiconductor package CP may comprise a substrate100and a semiconductor die101, such as a logic die, mounted on a top surface (die-attach surface)100aof the substrate100. The semiconductor die101may comprise a flip-chip die, a wire-bonding die, or a fan-out die. The semiconductor die101may be connected to the top surface100aof the substrate100via a plurality of connecting elements111such as bumps or metal pillars, but not limited thereto. The semiconductor die101and the top surface100aof the substrate100may be encapsulated by a molding compound120such as epoxy resin.

According to an embodiment, for example, additional components103and105may be mounted on the surfaces of the bottom PCB PB. The additional components103and105may comprise active or passive components such as IC chips, capacitors, resistors or inductors. Although the semiconductor die101is shown to be mounted on the top surface100aof the substrate100in a flip-chip manner, it is understood that in some embodiments the semiconductor die101may be mounted on the substrate100by using wire-bonding techniques. In some embodiments, the semiconductor package CP may include a fan-out die.

In some embodiments, the semiconductor package CP may include one or more logic dies, including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SOC), a field-programmable gate array (FPGA), a microcontroller unit (MCU), a power management integrated circuit (PMIC) die, a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), or the like, or any combinations thereof.

According to an embodiment, for example, the substrate100may be a wiring substrate and may be formed of polymer materials such as bismaleimide triazine (BT) laminates and/or build-up films known in the art. In some embodiments, the substrate100may be a re-distribution layer (RDL) substrate comprising dielectric layers and conductive layers, and may have a thinner thickness compared to conventional package substrates. It is to be understood that the substrate100may be a single layer or a multi-layer structure.

According to an embodiment, for example, the substrate100may comprise a plurality of connection pads100pdisposed on or near the top surface100aof the substrate100. According to an embodiment, for example, the substrate100may comprise a plurality of conductive traces100tinterconnecting the plurality of connection pads100pwith a plurality of ball pads100sdistributed on or near a bottom surface100bof the substrate100. Solder balls SB are disposed on the ball pads100s, respectively. In some embodiments, at least one passive device PE may be mounted on the bottom surface100bof the substrate100using surface mount technique (SMT).

According to an embodiment, the electronic device6may further comprise a middle re-distribution layer (RDL) structure200on the semiconductor die101. According to an embodiment, the middle RDL structure200may comprise dielectric layers210and interconnect structures220. The interconnect structures220may be electrically connected to a plurality of RDL pads230. According to an embodiment, a plurality of through mold vias (TMVs)122may be disposed in the molding compound120. The TMVs122may be electrically connected to the interconnect structures220of the middle RDL structure200.

According to an embodiment, for example, a PCB assembly50and a PCB60may be mounted on the corresponding RDL pads230of the middle RDL structure200through connecting elements502and602, respectively. According to an embodiment, for example, the PCB assembly50may comprise a PCB52and components503and505mounted on opposite sides of the PCB52. According to an embodiment, for example, the components503and505may comprise memory devices, antenna devices or radio-frequency (RF) devices. According to an embodiment, for example, the connecting elements502and602may comprise solder balls or any suitable conducive joints known in the art. According to an embodiment, the PCB assembly50is physically separated from the PCB60and disposed on the middle RDL structure200with the PCB60in a side-by-side manner.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.