Patent ID: 12261108

Reference signs:1-Plating layer2-Heat sink3-First metal layer4-Second metal layer5-Bottom plate6-Dissipating fin7-Connecting portion8-Wafer9-Solder layer10-Plastic encapsulating structure11-Substrate12-Solder ball13-Circuit board

DESCRIPTION OF EMBODIMENTS

Embodiments of the present application are applied to a chip. It should be noted that when a solution of an embodiment of the present application is applied to a current chip or a chip that may appear in the future, names of various structures may change, but it is not affect the implementation of the solutions in embodiments of the present application.

It should be pointed out that terms or wordings involved in embodiments of the present application may be referenced between each other, and will not be repeated.

In prior art, an exposed die package of a wafer refers to exposing the wafer to achieve a goal of better heat dissipation. Among them, a silicon wafer may be referred to as a wafer for short. While the exposed die package is performed, a traditional thermally conductive glue is used to attach a heat sink on the top of the chip, but the thermal conductivity of the traditional thermally conductive glue is generally lower than 2 W/(m·C), which leads to poor heat dissipation of the chip and becomes a heat dissipation bottleneck of a system. In order to achieve a better heat dissipation, a solder with a higher thermal property has become an ideal substitute for thermally conductive glue. The thermal conductivity of the solder is higher than 60 W/(m·C), which can greatly improve the heat dissipation efficiency of the chip. However, the solder cannot be well soldered onto the plastic encapsulating structure of the wafer and the chip.

A chip heat dissipating structure, a chip structure, a circuit board and a supercomputing device provided in the present application aim to solve the above technical problems in the prior art.

In order to a better understanding of features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below with reference to the drawings. The attached drawings are for reference and explanation purposes only and are not used to limit the embodiments of the present application. In the following technical description, for a convenience of explanation, a number of details are used to provide a sufficient understanding of the disclosed embodiments. However, without these details, one or more embodiments can still be implemented. In other cases, in order to simplify the drawings, well-known structures and devices may be simplified for display.

FIG.1is a structural schematic diagram I of a chip heat dissipating structure provided by an embodiment of the present application:FIG.2is a structural schematic diagram II of a chip heat dissipating structure provided by an embodiment of the present application:FIG.3is a structural schematic diagram III of a chip heat dissipating structure provided by an embodiment of the present application: as shown inFIG.1toFIG.3, the chip heat dissipating structure is arranged on the chip, and the chip heat dissipating structure includes: a plating layer1covered on the chip, where the plating layer1includes a first metal layer3and a second metal layer4arranged in sequence. Exemplarily, the chip heat dissipating structure provided in the present application may be arranged on the chip. Among them, the chip includes a wafer8, a plastic encapsulating structure10and a substrate11: a groove is arranged on the plastic encapsulating structure10, and the wafer8may be arranged in the groove, and then the plastic encapsulating structure10is used to encapsulate the wafer8and an upper surface of the wafer8is exposed, which is an exposed die structure: the plastic encapsulating structure10is fixedly arranged on one side of the substrate11: furthermore, at least one solder ball12may be arranged on the other side of the substrate11, and the solder ball12is used to connect with a circuit board, so as to fix the chip on the circuit board.

As mentioned above, since the solder cannot be well soldered onto the wafer8and the plastic encapsulating structure10of the chip, in this application, a plating layer1is covered on the wafer8and the plastic encapsulating structure10at the same time to realize a connection of the chip and an external heat sink2by soldering.

A shape of the wafer8may be a circle, or a rectangle, or a square, or a trapezoid, or other regular shapes, or other irregular shapes: the shape of the wafer8is not limited in the present application. A material of the wafer8is not limited in the present application either.

A shape of the plastic encapsulating structure10is not limited in the present application, as long as the plastic encapsulating structure10can realize plastic encapsulation of the wafer8. A material of the plastic encapsulating structure10is not limited in the present application either.

The plating layer1includes a first metal layer3and a second metal layer4arranged in sequence: materials used for the first metal layer3and the second metal layer4are different. Among them, thicknesses of the first metal layer3and the second metal layer4may be the same or not: areas of the first metal layer3and the second metal layer4may be the same or not.

Optionally, the plating layer1may be grid-shaped, that is, the first metal layer3and the second metal layer4are both grid-shaped, so that a cost of the plating layer1can be saved.

In another implementation, the chip heat dissipating structure further includes a heat sink2, where the plating layer1is covered on the chip, that is, the plating layer1is covered on the wafer8and the plastic encapsulating structure10: the heat sink2and the plating layer1are connected, where the heat sink2and the plating layer1are connected by soldering.

A shape and a size of the heat sink2are not limited in the present application.

For example,FIG.4is a structural schematic diagram I of a heat sink provided by an embodiment of the present application. As shown inFIG.4, the heat sink2is composed of a bottom plate5and at least one dissipating fin6, and each dissipating fin6is fixedly connected to the bottom plate5, and the bottom plate5is soldered to a surface of the plating layer1.

For another example,FIG.5is a structural schematic diagram II of a heat sink provided by an embodiment of the present application. As shown inFIG.5, a connecting portion7may also be arranged on the heat sink2, the connecting portion7is composed of a first plate and a second plate, and there is a preset angle between the first plate and the second plate, the preset angle may be in a range of 180 degrees to 90 degrees: furthermore, each dissipating fin6is fixedly arranged on an upper surface of the connecting portion7, the bottom plate5is fixedly arranged on a lower surface of the connecting portion7: moreover, a gripper may be arranged on one of the dissipating fins6of the heat sink.

In this embodiment, by providing a chip heat dissipating structure composed of a plating layer1, the chip heat dissipating structure is used to be arranged on the chip, and the plating layer1is covered on a wafer8and a plastic encapsulating structure10of the chip, where the plating layer1includes a first metal layer3and a second metal layer4arranged in sequence: furthermore, a heat sink2may be connected to the plating layer1. Since two metal layers are added on the top of the chip by physical sputtering, the heat sink may be soldered onto the metal layer through a solder layer, so that the heat sink is fixed to the top of the chip: the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip, thus improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip.

FIG.6is a structural schematic diagram I of another chip heat dissipating structure provided by an embodiment of the present application:FIG.7is a structural schematic diagram II of another chip heat dissipating structure provided by an embodiment of the present application: on the basis of the embodiments shown inFIG.1, as shown inFIG.6andFIG.7, the first metal layer3is covered on the chip, and the second metal layer4is covered on the first metal layer3.

Optionally, an area of the plating layer1is the same as an area of an upper surface of the chip.

Optionally, the first metal layer3is an alloy metal layer. A thickness of the first metal layer is 0.1-0.5 microns.

Optionally, the second metal layer4is a copper metal layer. A thickness of the second metal layer is 2-6 microns.

Optionally, an area of the first metal layer3is the same as an area of the second metal layer4.

Optionally, the heat sink2is soldered onto the plating layer1through a solder layer9.

Optionally, a solder in the solder layer9is tin. A thickness of the solder layer9is 0.1-0.15 millimeters.

Optionally, an area of the solder layer9is the same as an area of the plating layer1, or an area of the solder layer9is the same as an area of a lower surface of the heat sink2.

Optionally, if an upper surface of the wafer8is flush with an upper surface of the plastic encapsulating structure10, the plating layer1is a plating layer1with a uniform thickness: if the upper surface of the wafer8is lower than the upper surface of the plastic encapsulating structure10, the plating layer1is embedded in the plastic encapsulating structure10; and if the upper surface of the wafer8is higher than the upper surface of the plastic encapsulating structure10, the wafer8is embedded in the plating layer1.

Exemplarily, on the basis of the embodiments shown inFIG.1, the first metal layer3is covered on the upper surfaces of the wafer8and the plastic encapsulating structure10, and the second layer4is covered on an upper surface of the first metal layer3.

In this embodiment, a material of the first metal layer3is an alloy, that is, the first metal layer3is an alloy metal layer, for example, the alloy is a stainless steel (SUS); and a material of the second metal layer4is a copper, that is, the second metal layer4is an alloy metal layer, in this way, the alloy metal layer is covered on the upper surfaces of the wafer8and the plastic encapsulating structure10, and the copper metal layer is covered on an upper surface of the alloy metal layer.

In order to facilitate the connection of the two metal layers to the chip and the heat sink2, and to facilitate a heat conduction of the two metal layers and the heat dissipation of the chip, thicknesses of the above two metal layers may be set to the following parameters: a thickness of the first metal layer3is 0.1-0.5 microns, preferably, the thickness of the first metal layer3is 0.15 microns; and a thickness of the second metal layer4is 2-6 microns, preferably, the thickness of the second metal layer4is 3 microns.

In this embodiment, a solder layer is provided on the plating layer1, that is, a solder layer9is provided on the second metal layer4; and the heat sink2and the solder layer9are soldered together. A material of the solder layer9is tin. Optionally, a thickness of the solder layer9is 0.1-0.15 millimeters: preferably, the thickness of the solder layer9is 0.13 millimeters. A thermal conductivity of the solder layer9is higher than 60 W/(m·C), which can improve the heat dissipation effect of the chip.

In this embodiment, the area of the plating layer1is the same as the area of the upper surface of the chip, that is, the area of the plating layer1is equal to a sum of the area of the upper surface of the wafer8and the area of the upper surface of the plastic encapsulating structure10; at this time, the area of the first metal layer3is the same as the area of the upper surface of the chip. As shown inFIG.7, the area of the first metal layer3is the same as the area of the upper surface of the chip, and the area of the first metal layer3is the same as the area of the second metal layer4: alternatively,FIG.8is a structural schematic diagram III of another chip heat dissipating structure provided by an embodiment of the present application, as shown inFIG.8, the area of the first metal layer3is the same as the area of the upper surface of the chip, while the area of the first metal layer3is different from the area of the second metal layer4.

In this embodiment, regarding the area of the solder layer9, the following implementations are provided.

An implementation I of the area of the solder layer9: as shown inFIG.7, the area of the first metal layer3is the same as the area of the second metal layer4, and the area of the solder layer9is the same as the area of the plating layer1.

An implementation II of the area of the solder layer9:FIG.9is a structural schematic diagram IV of another chip heat dissipating structure provided by an embodiment of the present application, as shown inFIG.9, the area of the first metal layer3is the same as the area of the second metal layer4, while the area of the solder layer9is different from the area of the plating layer1.

An implementation III of the area of the solder layer9:FIG.10is a structural schematic diagram V of another chip heat dissipating structure provided by an embodiment of the present application, as shown inFIG.10, the area of the first metal layer3is the same as the area of the second metal layer4, and the area of the solder layer9is the same as the area of the lower surface of the heat sink2: where the area of the solder layer9is different from the area of the plating layer1. The area of the solder layer9is the same as the area of a bottom surface of the heat sink2, thus facilitating a good connection between the heat sink2and the solder layer9.

An implementation IV of the area of the solder layer9:FIG.11is a structural schematic diagram VI of another chip heat dissipating structure provided by an embodiment of the present application, as shown inFIG.11, the area of the first metal layer3is the same as the area of the second metal layer4, and the area of the solder layer9is the same as the area of the lower surface of the heat sink2: where the area of the solder layer9is the same as the area of the plating layer1.

Regarding a positional relationship between the plating layer1and the chip, the following implementations are provided.

An implementation I of the positional relationship between the plating layer1and the chip:FIG.12is a structural schematic diagram VII of another chip heat dissipating structure provided by an embodiment of the present application, as shown inFIG.12, if an upper surface of the wafer8is flush with an upper surface of the plastic encapsulating structure10, the plating layer1is a plating layer1with a uniform thickness.

An implementation II of the positional relationship between the plating layer1and the chip:FIG.13is a structural schematic diagram VIII of another chip heat dissipating structure provided by an embodiment of the present application, as shown inFIG.13, if an upper surface of the wafer8is lower than an upper surface of the plastic encapsulating structure10, a thickness of the plating layer1is not uniform, and the first metal layer3of the plating layer1is embedded in a groove of the plastic encapsulating structure10.

An implementation III of the positional relationship between the plating layer1and the chip:FIG.14is a structural schematic diagram IX of another chip heat dissipating structure provided by an embodiment of the present application, as shown inFIG.14, if an upper surface of the wafer8is higher than an upper surface of the plastic encapsulating structure10, a thickness of the plating layer1is not uniform, the wafer8is embedded in the first metal layer3of the plating layer1.

In this embodiment, a process of obtaining the chip heat dissipating structure is the following process.

Step I, Dicing the Wafer.

FIG.15is a structure schematic diagram of a diced wafer provided by an embodiment of the present application. As shown inFIG.15, the wafer8is firstly diced to obtain the diced wafer8as shown inFIG.15.

Step II, Mounting the Wafer.

FIG.16is a process flow schematic diagram I of a chip provided by an embodiment of the present application. As shown inFIG.16, the diced wafer8is respectively mounted on the substrate11of each chip.

Step III, Plastic-Encapsulating the Chip.

FIG.17is a process flow schematic diagram II of a chip provided by an embodiment of the present application. As shown inFIG.17, the wafer8on each substrate11is plastic-encapsulated, that is, the wafer8is plastic-encapsulated by the plastic encapsulating structure10.

Step IV, Mounting a Tape.

FIG.18is a process flow schematic diagram III of a chip provided by an embodiment of the present application. As shown inFIG.18, each chip shown inFIG.17is provided with a tape mount, and strip loading is performed.

Step V, Setting Metal Layers.

FIG.19is a process flow schematic diagram IV of a chip provided by the embodiment of the present application. As shown inFIG.19, the first metal layer3and the second metal layer4are sequentially arranged on the upper surface of the chip by physical sputtering or electroplating.

Step VI, Peeling and Unloading.

FIG.20is a process flow schematic diagram V of a chip provided by an embodiment of the present application. As shown inFIG.20, the strip under the chip is removed.

Step VII, Separation Processing.

FIG.21is a process flow schematic diagram VI of a chip provided by the embodiment of the present application. As shown inFIG.21, strip singulation processing is performed on a respective chip to obtain the chip.

Step VIII, Soldering a Solder.

A solder layer9may be arranged on the second metal layer4of the plating layer1, so that the heat sink2and the solder layer9may be soldered together.

In this embodiment, by providing a chip heat dissipating structure composed of a plating layer1, the chip heat dissipating structure is used to be arranged on the chip, the plating layer1is covered on a wafer8and a plastic encapsulating structure10of the chip, and a heat sink2is connected to the plating layer1via a solder layer9: where the plating layer1includes a first metal layer3and a second metal layer4arranged in sequence: the first metal layer3is covered on the wafer8and the plastic encapsulating structure10, and the second metal layer4is covered on the first metal layer3. By adding two metal layers on the top of the chip by physical sputtering, the heat sink2may be soldered onto the metal layer through the solder layer, so that the heat sink2is fixed to the top of the chip: the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip: the metal layer and the solder layer9further accelerate the heat dissipation of the chip, hence improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip.

FIG.22is a structural schematic diagram I of a chip structure provided by an embodiment of the present application:FIG.23is a structural schematic diagram II of a chip structure provided by an embodiment of the present application: as shown inFIG.22andFIG.23, the chip structure includes a chip body and a chip heat dissipating structure arranged on the chip body, where the chip heat dissipating structure adopts the chip heat dissipating structure provided in the above-mentioned embodiments.

Exemplarily, the chip body includes a wafer8, a plastic encapsulating structure10and a substrate11: a groove is arranged on the plastic encapsulating structure10, and the wafer8may be arranged in the groove, and then the plastic encapsulating structure10is used to encapsulate the wafer8and an upper surface of the wafer8is exposed: the plastic encapsulating structure10is fixedly arranged on one side of the substrate11: furthermore, at least one solder ball12may be arranged on the other side of the substrate11, and the solder ball12is used to connect with a circuit board, so as to fix the chip on the circuit board.

Then, the chip heat dissipating structure provided in the above-mentioned embodiments is arranged on the chip body, and the plating layer1of the chip heat dissipating structure is arranged on the wafer8and the plastic encapsulating structure10of the chip body. The structure and principle of the chip heat dissipating structure may be referred to the above-mentioned embodiments, which will not be repeated.

In this embodiment, at least one hole may be opened on the plastic encapsulating structure10: one or more of the at least one hole is provided with a thermally conductive structure. Optionally, the thermally conductive structure is a metal thermally conductive structure or a non-metal thermally conductive structure. Thus, by opening a hole on the plastic encapsulating structure10and providing a thermally conductive structure in the hole, the chip structure can be further dissipated.

For example, a material of the metal thermally conductive structure includes at least one or more of copper, aluminum, silver, tin, gold, iron, and aluminum alloy. A material of the non-metal thermally conductive structure includes at least one or more of resin, ceramic, graphite, graphene, and water.

In this embodiment, the chip heat dissipating structure provided in the above-mentioned embodiments is arranged on the chip body. A chip heat dissipating structure composed of a plating layer1is provided, the chip heat dissipating structure is used to be arranged on the chip, and the plating layer1is covered on a wafer8and a plastic encapsulating structure10of the chip, where the plating layer1includes a first metal layer3and a second metal layer4arranged in sequence: furthermore, a heat sink2may be connected to the plating layer1. By adding two metal layers on the top of the chip by physical sputtering, the heat sink may be soldered onto the metal layer through a solder layer, so that the heat sink is fixed to the top of the chip: the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip, hence improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip.

FIG.24is a structure schematic diagram of a circuit board provided by an embodiment of the present application, as shown inFIG.24, the circuit board13of the embodiment of the present application is provided with at least one chip structure of the above-mentioned embodiments.

Exemplarily, the circuit board13is provided with at least one chip structure of the above-mentioned embodiments, and the chip structure and a solder ball are fixedly connected to the circuit board13.

A position and the number of chip structures on the circuit board13are not limited. For example, at least one chip structure may be arranged on an upper surface of the circuit board13: alternatively, at least one chip structure may be arranged on an upper surface of the circuit board13, and at least one chip structure may be arranged on a lower surface of the circuit board13.

The specific structure of the chip structure on the circuit board13may be the same or not. For example, the upper surface of the wafer in one chip structure on the circuit board13is flush with the upper surface of the plastic encapsulating structure, and the upper surface of the wafer in another chip structure on the circuit board13is lower than the upper surface of the plastic encapsulating structure.

Among them, the structure and principle of the chip structure may be referred to the above-mentioned embodiments, which will not be repeated.

In this embodiment, by providing at least one chip structure of the above-mentioned embodiments on a circuit board13, and the chip structure is provided with the chip heat dissipating structure provided by the above-mentioned embodiments. By adding two metal layers on the top of the chip by physical sputtering, the heat sink may be soldered onto the metal layer through a solder layer, so that the heat sink is fixed to the top of the chip: the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip, hence improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip. Furthermore, the circuit board13is dissipated to prevent heat from damaging the circuit board13and components on the circuit board13.

FIG.25is a structural schematic diagram of a supercomputing device provided by an embodiment of this application, as shown inFIG.25, the supercomputing device provided in an embodiment of the present application is provided with at least one circuit board13provided in the above-mentioned embodiments.

Optionally, circuit boards13in the supercomputing device are connected in parallel with each other.

Optionally, a sliding groove may be provided on a case of the supercomputing device, the sliding groove is used for slidable connection with each circuit board13in the supercomputing device.

Optionally, fans may also be arranged on both sides of the case of the supercomputing device, and a heat dissipation air duct of the fan may be consistent with a heat dissipating chamber of a heat sink on the circuit board13, so as to quickly dissipate the heat generated by the circuit board13in the case to the outside of the case, thereby providing a performance of supercomputing device.

Exemplarily, one or more circuit boards13are arranged in the supercomputing device, and the circuit board13adopts the circuit boards13provided in the above-mentioned embodiments. The structure and function of the circuit board13may be referred to the introduction of the above-mentioned embodiments, which will not be repeated.

In this embodiment, multiple circuit boards13may be connected in parallel, and then the parallel circuit boards13may be arranged in the supercomputing device. In one implementation, the supercomputing device may be a supercomputing server.

A connection between the circuit board13and the supercomputing device may be a fixed connection or slidable connection. Exemplarily, one or more sliding grooves may be arranged on the case of the supercomputing device, and then the circuit board13is arranged in the sliding groove, so that the circuit board13may slide on the sliding groove.

Among them, when multiple circuit boards13are arranged in the supercomputing device, the structure of each circuit board13of the multiple circuit boards13may be the same or not.

Each circuit board13is provided with at least one chip structure of the above-mentioned embodiments, and the chip structure and a solder ball are fixedly connected to the circuit board13.

Among them, the structure and principle of the chip structure may be referred to the above-mentioned embodiments, which will not be repeated.

In this embodiment, by providing one or more circuit boards13of the above embodiments in a supercomputer device, at least one chip structure of the above embodiments is arranged on each circuit board13, and the chip heat dissipating structure provided by the above embodiment is arranged on the chip structure. By adding two metal layers on the top of the chip by physical sputtering, the heat sink may be soldered onto the metal layer through a solder layer, so that the heat sink is fixed to the top of the chip: the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip, hence improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip. Furthermore, the circuit board13is dissipated to prevent heat from damaging the circuit board13and components on the circuit board13.

In the present application, although the terms “first”, “second”, etc. may be used in the present application to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without changing the meaning of the description, a first element may be called a second element, and likewise, a second element may be called a first element, as long as all occurrences of the “first element” are renamed consistently and all occurrences of the “second component” are renamed consistently. The first element and the second element are both elements, but they may not be the same element.

The terms used in the present application are only used to describe the embodiment but not used to limit the claim. For example, the singular forms “a”, “an” and “the” used in the description of the embodiment and claim are intended to include plural forms unless limitation to the singular is explicitly stated. Similarly, the term “and/or” used in the present application refers to any and all possible combinations that include one or more of the associated lists. Furthermore, when used in this application, the term “comprise” and its variants “comprises” and/or “comprising” and the like refer to an existence of a stated feature, a whole, a step, an operation, an element, and/or a component, but does not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components, and/or groups of these.

The various aspects, implementations, realizations or features in the described embodiments can be used alone or in any combination.

The above technical description may refer to the drawings, which form a part of the present application, and the drawings show implementations in accordance with the described embodiments. Although these embodiments are described in sufficient detail to enable persons of ordinary skill in the art to implement these embodiments, these embodiments are non-limitative: so that other embodiments and changes may be used without departing from the scope of the described embodiments. For example, an order of operations described in the flowchart is non-limitative, so that the order of two or more operations illustrated in the flowchart and described according to the flowchart can be changed according to several embodiments. For another example, in several embodiments, one or more operations illustrated in the flowchart and described according to the flowchart are optional or can be deleted. Furthermore, certain steps or functions may be added to the disclosed embodiments, or the order of two or more steps may be replaced. All these changes are considered to be included in the disclosed embodiment and claim.

Furthermore, terms are used in the above technical description to provide a thorough understanding of the described embodiments. However, particular details are not required to implement the described embodiments. Therefore, the above description of the embodiments is presented for explanation and description. The embodiments presented in the above description and the examples disclosed according to these embodiments are provided separately, so that context may be added for facilitating understanding of the described embodiments. The above description is not intended to be exhaustive or to limit the described embodiments to the precise form of the present application. Based on the above teachings, several modifications, options and changes are feasible. In some cases, well-known processing steps are not described in detail to avoid unnecessarily affecting the described embodiments.