Patent ID: 12237299

The drawings have not necessarily been drawn to scale. Similarly, some components and/or operations can be separated into different blocks or combined into a single block for the purpose of discussion of some of the implementations of the present technology. Moreover, while the technology is amenable to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the technology to the particular implementations described. On the contrary, the technology is intended to cover all modifications, equivalents, and alternatives falling within the scope of the technology as defined by the appended claims.

DETAILED DESCRIPTION

Overview

Stacked semiconductor assemblies, and systems and methods for their manufacture, are disclosed herein. In some embodiments, the stacked semiconductor assembly includes a first semiconductor die having a semiconductor substrate with a first bonding surface and one or more first conductive features positioned on the first bonding surface (e.g., bond pads, exposed interconnects, thermal transfer units, and/or various other conductive features). A second semiconductor die is stacked on the first die. The second die includes a semiconductor substrate with a second bonding surface contacting the first bonding surface of the first semiconductor substrate and one or more second conductive features positioned on the second bonding surface. In some embodiments, the second bonding surface directly contacts the first bonding surface of the first semiconductor substrate. Further, each of the one or more second conductive features can be electrically coupled to a corresponding first conductive feature at an interface between the bonding surfaces. The stacked semiconductor assembly also includes a void at the bonding interface for the first and second bonding surfaces and laterally between pairs of first and second conductive features. Further, the void can include a layer of diffused and oxidized metal extending from at least one of the first conductive features. As a result of the manufacturing process, the diffused and oxidized metal is electrically non-conductive.

In some embodiments, a method for bonding layers in the stacked semiconductor includes aligning a first array of conductive features on the first bonding surface of the first semiconductor substrate with a second array of conductive features on the second bonding surface of the second semiconductor substrate. Once aligned, the method includes annealing the stacked semiconductor dies to directly bond the first bonding surface to the second bonding surface. The alignment and/or annealing process can result in at least one void forming between the upper surface and the lower surface, and the void can include a layer of metal material. The layer of metal material can be the result of, for example, metallic drift when forming the first array of conductive features, aligning the first and second arrays, and/or annealing the stacked semiconductor dies. In some embodiments, the layer of metal material extends from a first individual conductive feature in the first array towards a second individual conductive feature in the first array. In some embodiments, the layer of metal material extends entirely from the first individual conductive feature to the second individual conductive feature, thereby forming an electrical and/or thermal short between the conductive features.

Once the first and second semiconductor substrates are bonded, the method includes exposing the stacked semiconductor device to microwave radiation to excite a chemical constituent present in the void. The excited chemical constituent reacts with the layer of metal material in the void to reduce the electrical and/or thermal conductivity of the metal. In some embodiments, for example, the chemical constituent is a hydroxy group molecule (e.g., doped into the first and/or second bonding surface, in gaseous form in the void, etc.). In these embodiments, the microwave radiation excites the hydroxy group molecule, which then reacts with the layer of metal material to oxidize the metal.

For ease of reference, a stacked semiconductor assembly is sometimes described herein with reference to top and bottom, upper and lower, upwards and downwards, and/or horizontal plane, x-y plane, vertical, or z-direction relative to the spatial orientation of the embodiments shown in the figures. It is to be understood, however, that the stacked semiconductor assembly, and the surfaces bonded therein, can be moved to, and used in, different spatial orientations without changing the structure and/or function of the disclosed embodiments of the present technology.

Further, although primarily discussed herein in the context of bonding two semiconductor dies together, one of skill in the art will understand that the scope of the invention is not so limited. For example, the method can be used in bonding any two surfaces in a semiconductor assembly, bonding two semiconductor assemblies together, bonding surfaces within an individual semiconductor die, and/or bonding surfaces with similar materials. Accordingly, the scope of the invention is not confined to any subset of embodiments and is confined only by the limitations set out in the appended claims.

DESCRIPTION OF THE FIGURES

FIGS.1A and1Billustrate a hybrid bonding process between two semiconductor dies in a stacked semiconductor assembly100(“stacked assembly100”) in accordance with some embodiments of the present technology. As illustrated with reference toFIG.1A, in some embodiments, the hybrid bonding process can occur between a first semiconductor die110(“first die110”) and a second semiconductor die140(“second die140”).

The first die110includes a semiconductor substrate112that has a first surface114(e.g., an upper surface) and a second surface116(e.g., a lower surface) opposite the first surface114. A material120is deposited on the first surface114with a bonding surface122facing outwardly (e.g., upwardly) from the substrate112. The material120insulates the first die110and facilitates bonding the first die110to the second die140. The material120can be a dielectric material, a polymer material, and/or various other suitable materials. Examples of dielectrics that can be used include silicon dioxide, silicon nitride, silicon oxynitride, silicon carbon nitride, polysilicon, silicon carbonate, and/or any other suitable dielectric. Examples of polymers include polypyrrole, polyaniline, polydopamine, and/or various suitable epoxy resins.

As further illustrated inFIG.1A, the first die includes interconnect structures130extending from the bonding surface122of the material120towards the second surface116of the substrate112. In some embodiments, the interconnect structures130extend fully from the bonding surface122to the second surface116. In other embodiments, the interconnect structures130extend from the bonding surface122to the first surface114of the substrate112and/or to some intermediate depth between the bonding surface122and the second surface116(e.g., to the first surface114, to a depth in the substrate112, etc.). Further, each individual interconnect structure130includes a bond site132at the bonding surface122. As illustrated, each bond site132is generally flush with the bonding surface122of the material120, thereby providing a generally flat surface for bonding with the second die140.

In the illustrated embodiment, each bond site132is illustrated with a bond pad shape, having a wider diameter than the remainder of the corresponding interconnect structure130. The larger diameter of the bond site132can help facilitate bonding to a corresponding electrical feature in the second die140(e.g., as discussed below, a corresponding interconnect structure160). In some embodiments, each bond site132can have a different size and/or shape. For example, in various embodiments, the bond sites132can have a diameter generally corresponding to the diameter of the interconnect structure130, varying diameters (e.g., based on the location on the first die110), and/or can have varying shapes when viewed from above. In some embodiments, each bond site132can be an exposed portion of the interconnect structure130at the bonding surface122.

In some embodiments, the interconnect structures130can be made from copper, nickel, tungsten, cobalt, indium, tin, ruthenium, molybdenum, bismuth, aluminum, polysilicon and/or polycide (e.g., tungsten silicon, molybdenum silicon, nickel silicon, etc.), conductor-filled epoxy, and/or other suitable electrically conductive materials. In some embodiments, the interconnect structures130can be surrounded by an insulator to electrically isolate the interconnect structures130from the substrate112. In some embodiments, the bond sites132can also be made from copper, nickel, tungsten, cobalt, indium, tin, ruthenium, molybdenum, bismuth, aluminum, polysilicon and/or polycide (e.g., tungsten silicon, molybdenum silicon, nickel silicon, etc.), conductor-filled epoxy, and/or other suitable electrically conductive materials. In some embodiments, the interconnect structures130and the bond sites132can be made from the same material (e.g., when a bond site is a continuation of the interconnect structure). For example, the interconnect structures130and the bond sites132can both be made from copper. In some such embodiments, the interconnect structures130and the bond sites132can be formed in a single step. In other embodiments, they can be formed in separate steps. In some embodiments, the interconnect structures130and the bond sites132can be made from differing materials. For example, the interconnect structures130can be made from nickel while the bond sites132can be made from copper.

Similar to above, the second die140includes a semiconductor substrate142that has a first surface144(e.g., a lower surface) and a second surface146(e.g., an upper surface) opposite the first surface144. A material150is deposited on the first surface144with a bonding surface152facing outwardly from the substrate142. The material150insulates the second die140and facilitates bonding the second die140to the first die110. The material150can correspond to the material120, such as a corresponding dielectric, a corresponding polymer, and/or various other suitable materials.

The second die also includes interconnect structures160extending from the bonding surface152of the material150towards the second surface146of the substrate142. In some embodiments, the interconnect structures160extend fully from the bonding surface152to the second surface146. In other embodiments, the interconnect structures160extend from the bonding surface152to some intermediate depth (e.g., to the first surface144, to a depth in the material150, to a depth in the substrate142, etc.). Further, each individual interconnect structure160includes a bond site162at the bonding surface152. As illustrated, each bond site162is generally flush with the bonding surface152of the material150, thereby providing a generally flat surface for bonding with the first die110. In various embodiments, each bond site162can have a diameter generally corresponding to the diameter of the interconnect structure160, varying diameters (e.g., based on the location on the second die140), can be an exposed portion of the interconnect structure160at the bonding surface152, and/or can have varying shapes when viewed from above.

Further, in various embodiments, the interconnect structures160and/or bond sites162can be made from copper, nickel, conductor-filled epoxy, and/or other electrically conductive materials. In some embodiments, the interconnect structures160can be surrounded by an insulator to electrically isolate the interconnect structures160from the substrate142. In some embodiments, the interconnect structures160and the bond sites162can be made from the same material (e.g., when a bond site is a continuation of the interconnect structure). In some embodiments, the interconnect structures160and the bond sites162can be made from differing materials.

As illustrated by arrows inFIG.1B, the hybrid bonding process includes stacking the second die140on the first die110to form the stacked assembly100. Within the stacked assembly100, as illustrated inFIG.1B, the material120of the first die110is in direct contact with the material150from the second die140at a bonding interface170. In a typical hybrid bonding process, the stacked assembly100is then heated and put under pressure to join the material120to the material150at the bonding interface170. However, each of the bonding surfaces122,152can include various impurities (e.g., particles, organic contamination, ionic contamination, etc.) resulting from previous manufacturing steps and/or movement during manufacturing. The impurities can result in voids forming at the bonding interface170. The voids can reduce the strength of the bond between the first and second dies110,140. Further, as discussed in more detail below with respect toFIGS.2A and2B, metal adjacent the voids can drift into the void, which can result in an electrical or thermal short between corresponding bond pads adjacent the void. Accordingly, in a typical hybrid bonding process, each of the bonding surfaces122,152is meticulously cleaned prior to stacking to reduce the impurities present at the bonding interface170. However, even with extensive cleaning, one or more voids can still form at the bonding interface170, thereby creating a risk of shorts between bond pads.

FIG.2Ais a cross-sectional view of a stacked assembly100with a void270in accordance with some embodiments of the present technology. In the illustrated embodiment, the second die140is stacked on the first die110and the material150is bonded with the material120at the bonding interface170. Further, individual interconnect structures160a,160bare generally aligned with corresponding individual interconnect structures130a,130b, thereby forming electrical and/or thermal connections between the first and second dies110,140. In some embodiments, the hybrid bonding process applied to the bonding surfaces122,152(FIG.1A) can anneal corresponding individual interconnect structures130a,160aand130b,160bat the bonding interface170, thereby forming an integral bond between the corresponding individual interconnect structures130a,160aand130b,160b. In some embodiments, the stacked assembly100can be further annealed after the bonding surfaces122,152are bonded.

As further illustrated inFIG.2A, however, a particle202was leftover at the bonding interface170after cleaning and alignment. When the first and second dies110,140were bonded together, the particle202caused the void270to form at the bonding surface. In turn, as illustrated in more detail inFIG.2B, the void270can allow metal from the bond sites132,162and/or the interconnect structures130,160to drift in the void270.

FIG.2Bis an enlarged cross-sectional view of the void270from region A ofFIG.2Ain accordance with some embodiments of the present technology. As discussed above, the void270results from a particle202between the materials120,150during the bonding process. As further illustrated inFIG.2B, a layer of metal material272is present in the void270. In some embodiments, the metal material272is the result of surface diffusion from one or more of the bond sites132,162during the hybrid bonding process. For example, as the stacked assembly100is pressurized and heated, the metal material272can drift into the open surface area in the void270. In embodiments having an additional annealing process for the bond sites132,162, the metal material272can additionally, or alternatively, diffuse into the void270during the addition annealing process.

In the illustrated embodiment, the metal material272extends from an individual bond site162ato an individual bond site162b. As a result, the metal material272forms an electrical and/or thermal short between the individual bond site162aand the individual bond site162b. As a result, the metal material272forms an electrical and/or thermal short between the corresponding individual interconnect structures130a,160aand the corresponding individual interconnect structures130b,160b, thereby reducing the electrical and/or thermal performance of the stacked assembly100. If enough similar voids form elsewhere at the bonding interface170with similar layers of metal material drifting through them, the voids can reduce the electrical and/or thermal performance of the stacked assembly100beyond an acceptable threshold. That is, some embodiments, completed stacked assemblies is tested after bonding to measure the electrical and/or thermal performance of the stacked assemblies. A stacked assembly with too many shorts between interconnect structures will fail to meet performance standards due to the electrical and/or thermal shorts. In some embodiments, for example, the shorts can cause the stacked assembly to have too few functional electrical paths. In some embodiments, the shorts can cause heat to be too mobile through the stacked assembly. In a typical manufacturing process, stacked assemblies that fail to meet performance standards are thrown out, thereby reducing the throughput of the process.

Although discussed primarily herein as causing shorts between interconnect structures, the voids can cause shorts between other conductive structures at the bonding interface. For example, in some embodiments, the materials120,150can include one or more conductive structures that facilitate bonding between the first and second dies110,140, provide designated thermal pathways at the bonding interface170, and/or provide various other suitable functions. A similar void at the bonding interface can also disrupt these functions. For example, a metal material can form a short between conductive structures providing a designated thermal pathway, thereby shorting the pathway; and/or a metal material can form a short between a conductive structure in the thermal pathway and the interconnect structure, thereby introducing an unintended thermal pathway. These shorts can also cause a completed stacked assembly to fail to meet performance standards and, in a typical hybrid bonding process, be thrown out.

As discussed above, the hybrid bonding process can include one or more cleaning steps before the first and second dies110,140are stacked. By cleaning the surfaces, the process can reduce the number of particles that can form voids at the bonding interface, thereby reducing the number of shorts caused by a metal material that drifts into in the voids. However, the cleaning process can be expensive and often cannot fully clean the bonding surfaces to fully remove the chance of shorts forming. In some embodiments, the hybrid bonding process can alternatively, or additionally, include exposing the stacked assembly100to radiation (e.g., microwave radiation) after bonding the bonding surfaces. The electromagnetic radiation (“radiation”) can be used to corrode the metal material in any voids to reduce the number of shorts on the backend of the hybrid bonding process. Additional details on such embodiments are described with respect toFIGS.3-5below.

FIG.3is a cross-sectional view of the stacked assembly100ofFIG.2Aexposed to electromagnetic radiation304(“radiation304”) in accordance with some embodiments of the present technology. The radiation304excites a chemical constituent302present in the void270. The excited chemical constituent302then reacts with the metal material272in the void270to degrade (e.g., oxidize, corrode, consume, and/or deteriorate) the metal material272. As a result of the reaction, the electrical and/or thermal conductivity of the metal material272can be reduced (or destroyed), thereby reducing and/or removing the shorts caused by the metal material272. For example, in some embodiments, the chemical constituent302can be a hydroxy group molecule. The radiation304excites the hydroxy group molecule, which the reacts with the metal material272in the void270to oxidize the metal material272. In some embodiments, the chemical constituent302is a gas present in the void270. For example, the chemical constituent302can be atmospheric air containing dihydrogen oxide molecules. In some embodiments, the radiation304is microwave radiation having a frequency between about 100 megahertz (MHz) and about 3000 MHz, between 500 MHz and about 2750 MHz, or between about 900 MHz and about 2450 MHz.

In some embodiments, the chemical constituent302is more quickly excited by the radiation304than the other materials in the stacked assembly100. Accordingly, the radiation304can cause the reaction between the excited chemical constituent302and the metal material272before any of the other components of the stacked assembly100are detrimentally affected by the radiation304. Accordingly, in some embodiments, the hybrid bonding process can target the entire stacked assembly100with the radiation304to address the shorts in multiple voids (not shown) at once. For example, the stacked assembly can include three or more stacked semiconductor dies (not shown) directly bonded to each other, with one or more voids formed at each interface. The hybrid bonding process can include exposing the entire stacked assembly to the radiation304at once. In other embodiments, the hybrid bonding process can target the radiation304at one or more specific voids in the stacked assembly100. For example, in some embodiments, the hybrid bonding process can include testing the stacked assembly100after bonding to identify one or more shorts, then targeting the shorts with the radiation304. In some embodiments, the hybrid bonding process can include multiple iterations of stacking a semiconductor die on another, bonding the dies, exposing the bonded dies to the radiation304, then stacking another die on the bonded stack and repeating. By exposing the stack to radiation304at each iteration of stacking, the hybrid bonding process can help ensure the radiation304reaches any newly formed voids.

Further, in some embodiments, the hybrid bonding process can include iterations of the radiation exposure depicted inFIG.3. For example, the hybrid bonding process can include testing the stacked assembly100after the radiation304and/or any resulting reactions. If the stacked assembly100contains more shorts than acceptable, the hybrid bonding process can include re-exposing the stacked assembly100to the radiation304. Similar to above, the re-exposure to the radiation304re-excites the chemical constituent302, which then further reacts with the metal material272to further degrade the metal material272. In some embodiments, the iterations of radiation exposure can continue until the stacked assembly100contains an acceptable number of shorts. In some embodiments, the iterations of radiation exposure can continue until all of the shorts are removed from the stacked assembly100. In some embodiments, iterations of radiation exposure can continue for a predetermined maximum number of iterations. If the stacked assembly100still contains more shorts than acceptable after the maximum iterations, the hybrid bonding process can include disposing the stacked assembly100.

FIGS.4A and4Bare a cross-sectional view of the stacked assembly100after being exposed to electromagnetic radiation in accordance with some embodiments of the present technology. As illustrated with respect toFIG.4A, the components of the stacked assembly100were generally unaffected by the radiation and subsequent reaction. For example, the first and second dies110,140remain bonded by the materials120,150, and the interconnect structures130in the first die110remain bonded to corresponding interconnect structures160in the second die140. However, as further illustrated inFIG.4A, the materials in the void270have been affected by the reaction between the chemical constituent302and the metal material472.FIG.4Bis an enlarged cross-sectional view of the region B ofFIG.4A.

As illustrated with respect toFIG.4B, the components of the stacked assembly100are only affected where exposed to the chemical constituent302in the void270. For example, the metal material472is now fully degraded (e.g., oxidized, corroded, consumed, and/or deteriorated) because the metal material272(FIG.3) was fully exposed to the chemical constituent302in the void270. Further, in the illustrated embodiment, an edge portion434of one of the bond sites132adjacent the void270was degraded because the edge portion434was exposed to the chemical constituent302, while a central portion436was generally unaffected because the central portion436was not exposed. Similarly, an edge portion464of one of the bond sites162adjacent the void270was degraded while a central portion466was generally unaffected. In some embodiments, the edge portions434,464of the bond pads132,162exposed to the chemical constituent302in the void270can be sufficiently small to not react with the chemical constituent302to degrade. In some embodiments, the metal extending away from an edge portion and into the void shelters the edge portion from the chemical constituent302. Accordingly, in these embodiments, the bond pads132,162are generally unaffected by the exposure to the radiation.

The degraded metal material472(as well as the degraded edge portions434,464) are less conductive after the reaction. In some embodiments, the degraded metal material472does not conduct electricity at all and/or has a very low thermal conduction. That is, the degraded metal material472is generally unable to provide an electrical and/or thermal short between the corresponding individual interconnect structures130a,160aand the corresponding individual interconnect structures130b,160b. As a result, the stacked assembly100can have an improved electrical and/or thermal performance after the exposure to the radiation compared to the stacked assembly's performance before. The improvement in performance can move some stacked assemblies from below a predefined standard for performance to at or above the predefined standard, thereby reducing the number of stacked assemblies that are thrown out at the end of the hybrid bonding process.

FIG.5is a flow diagram of a generalized process500(“process500”) for bonding semiconductor materials in accordance with some embodiments of the present technology. As described above, the process500can bond two or more semiconductor dies in a stacked assembly. Further, in various embodiments, the process500can bond any two surfaces in a semiconductor assembly and/or using semiconductor materials (e.g., two or more semiconductor assemblies, two or more bonding surfaces within an individual semiconductor die, and/or two or more bonding surfaces with similar materials).

At block505the process500includes stacking at least two semiconductor materials with bonding surfaces of the semiconductor materials in contact with each other. For example, in some embodiments, the process500includes stacking a first semiconductor die onto a second semiconductor die with bonding surfaces of the semiconductor dies in direct contact with each other. In some embodiments, the process500includes stacking multiple semiconductor materials with bonding surfaces of the semiconductor materials in direct contact with each other. For example, the process500can include stacking three or more semiconductor dies directly on top of each other at block505.

In some embodiments, the process500includes a cleaning phase at block505to reduce the number of impurities present at a bonding interface between the semiconductor materials. As discussed above, the cleaning phase can reduce the number of voids that are formed during the process500. In some embodiments, the process500includes a doping phase at block505to introduce a desired chemical constituent between the semiconductor materials to react with materials in any voids that do form during the process500. In some embodiments, the doping phase at block505introduces the chemical constituent into the ambient air around the semiconductor materials. In some embodiments, the doping phase includes doping the bonding surface of the semiconductor materials with the chemical constituent.

Further, in some embodiments, the process500includes an alignment phase at block505to ensure proper alignment of components in the semiconductor materials. For example, the alignment phase can include aligning a first plurality of conductive features (e.g., metallic bond sites) on the bonding surface of a first semiconductor die with a second plurality of conductive features on the bonding surface of a second semiconductor die.

At block510the process500includes bonding the stacked semiconductor surfaces through a hybrid bonding process. As discussed above, the hybrid bonding process of block510can include heating and/or pressurizing the stacked semiconductor materials. As a result, the bonding surfaces directly bond together while the aligned conductive features bond together to form electrical and/or thermal connections between the semiconductor materials.

During the bonding process at block510, impurities at the bonding surfaces can cause one or more voids to form between the semiconductor materials. In embodiments that included a doping phase at block505, the voids will include the chemical constituent. In some embodiments, the presence of the chemical constituent in the ambient air around the stacked semiconductor results in the voids including the chemical constituent. In some embodiments, the bonding process at block510can include introducing, or maintaining, the chemical constituent in the ambient air. As a result, if any voids form between the stacked semiconductor surfaces, they will include the chemical constituent.

At block515the process500includes exposing the stacked structure to electromagnetic radiation. The electromagnetic radiation excites the chemical constituent in any voids between the stacked semiconductor surfaces. The excited chemical constituent can react metals to thereby degrade the metals present in the void. For example, the chemical constituent can react with metals present in the void to oxidize, corrode, and/or otherwise deteriorate the metal. As a result, metal layers that may have otherwise created an electrical and/or thermal short between conductive features can be degraded beyond being able to create the short.

In some embodiments, the electromagnetic radiation can be microwave radiation with a frequency of between about 900 MHz and about 2450 MHz. In some embodiments, the chemical constituent can be specifically selected based on the chemical constituent's ability to be quickly excited by the microwave radiation. For example, the chemical constituent can be a hydroxy group molecule, which are easily excited by microwave radiation to release a reactive molecule with oxygen. The reactive molecule can then oxidize the metal present in the void. Because the hydroxy group molecule is excited and reacts with the metal with relatively low levels of exposure to the microwave radiation, the process500is able to degrade the metal in the void without negatively effecting other components in the stacked structure. Further, because the chemical constituent is only present within the void, the metallic structures adjacent the void have only edge portions degraded by a reaction with the excited chemical constituent.

In some embodiments, the radiation process at block515exposes the entire stacked structure to the microwave radiation. The broad exposure can address multiple voids between the stacked semiconductor surfaces at once, thereby significantly reducing the number of shorts in a completed device. In some embodiments, the radiation process at block515selectively exposes portions of the stacked structure to the microwave radiation. The selective exposures can target known and/or suspected shorts while reducing the risk of damage to any other components in the stacked structure. In some embodiments, for example, the process500can include a step before the radiation exposure to check for shorts in the stacked structure, then expose only the known shorts to the microwave radiation. In some embodiments, the location of shorts in the stacked structure can be a recurring phenomenon (e.g., resulting from a step in the bonding process), such that the radiation process can target the recurring location.

At optional block520the process500includes checking the stacked structure for electrical and/or thermal short circuits. In some embodiments, the testing process can include an overall performance test of the stacked structure. Performance at, or above, a predetermined threshold can indicate that a sufficiently small number of shorts exist in the stacked structure. Performance below the predetermined threshold can indicate that an excessive number of shorts may still exist. In some embodiments, the testing process can include more individualized tests to locate and/or tally the number of shorts. Stacked structures with a total number of shorts beneath a predefined number can be expected to perform at or above the predetermined threshold, while stacked structures with a total number of shorts above the predefined number can be expected to perform below the predetermined threshold.

In some embodiments, stacked structures performing (or expected to perform) above the predetermined threshold continue in the manufacturing process while stacked structures performing (or expected to perform) below the predetermined threshold are thrown out. In some embodiments, the process can return to block515for stacked structures performing (or expected to perform) below the predetermined threshold to re-expose the stacked structures to the electromagnetic radiation. The second exposure can continue a reaction between the chemical constituent and the metal present in a void to further degrade the metal. As a result, one or more shorts that previously survived the previous exposure can be removed, such that when the process returns to block520, the stacked assembly performs (or is expected to perform) above the predetermined threshold.

In some embodiments, the iteration between blocks515and520can be repeated until all the shorts in the stacked structure are removed. In some embodiments, the iteration between blocks515and520can be repeated until an acceptable number of shorts are detected. In some embodiments, the iteration between blocks515and520can include a predetermined maximum iterations. If the shorts are not removed (or not reduced to an acceptable level) before the predetermined maximum iterations, the process500can dispose of the stacked structure and end.

In some embodiments, the process500can be repeated for each layer of a stacked assembly. For example, in some embodiments, the process includes stacking first and second semiconductor dies at block505in a stacked assembly, bonding the surfaces of the dies at510, exposing the stacked assembly to electromagnetic radiation at block515, testing the stacked assembly at block520, then returning to block505to add another semiconductor die to the stacked assembly. In some embodiments, the process500can be repeated while adding multiple layers of semiconductor materials (e.g., stacking two, three, five, ten, or any suitable number of materials) on each pass.

FIG.6is a schematic view of a system that includes a semiconductor die assembly configured in accordance with embodiments of the present technology. Any one of the semiconductor devices having the features described above with reference toFIGS.1A-5can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system900shown schematically inFIG.6. The system900can include a memory990substantially as described above (e.g., SRAM, DRAM, flash, and/or other memory devices), a power supply992, a drive994, a processor996, and/or other subsystems or components998. The semiconductor devices described above with reference toFIGS.1A-5can be included in any of the elements shown inFIG.6. For example, the memory990can be include a stack of semiconductor dies bonded in accordance with the process described above with respect toFIG.5. The resulting system900can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system900include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system900include lights, cameras, vehicles, etc. With regard to these and other example, the system900can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system900can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the technology. To the extent any material incorporated herein by reference conflicts with the present disclosure, the present disclosure controls. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Furthermore, as used herein, the phrase “and/or” as in “A and/or B” refers to A alone, B alone, and both A and B. Additionally, the terms “comprising,” “including,” “having,” and “with” are used throughout to mean including at least the recited feature(s) such that any greater number of the same features and/or additional types of other features are not precluded.

From the foregoing, it will also be appreciated that various modifications may be made without deviating from the disclosure or the technology. For example, one of ordinary skill in the art will understand that various components of the technology can be further divided into subcomponents, or that various components and functions of the technology may be combined and integrated. In addition, certain aspects of the technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Furthermore, although advantages associated with certain embodiments of the technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.