Patent ID: 12237154

In the drawings, reference numbers may be reused to identify similar and/or identical elements.

DETAILED DESCRIPTION

A substrate support in a substrate processing system may include an edge ring. An upper surface of the edge ring may extend above an upper surface of the substrate support, causing the upper surface of the substrate support (and, in some examples, an upper surface of a substrate arranged on the substrate support) to be recessed relative to the edge ring. This recess may be referred to as a pocket. A distance between the upper surface of the edge ring and the upper surface of the substrate may be referred to as a “pocket depth.” Generally, the pocket depth is fixed according to a height of the edge ring relative to the upper surface of the substrate.

Some aspects of etch processing may vary due to characteristics of the substrate processing system, the substrate, gas mixtures, etc. For example, flow patterns, and therefore an etch rate and etch uniformity, may vary according to the pocket depth of the edge ring, edge ring geometry (i.e., shape), as well as other variables including, but not limited to, gas flow rates, gas species, injection angle, injection position, etc. Accordingly, varying the configuration of the edge ring (e.g., including edge ring height and/or geometry) may modify the gas velocity profile across the surface of the substrate.

Some substrate processing systems may implement moveable (e.g., tunable) edge rings and/or replaceable edge rings. In one example, a height of a moveable edge may be adjusted during processing to control etch uniformity. The edge ring may be coupled to an actuator configured to raise and lower the edge ring in response to a controller, user interface, etc. In one example, a controller of the substrate processing system controls the height of the edge ring during a process, between process steps, etc. according to a particular recipe being performed and associated gas injection parameters. Further, edge rings and other components may comprise consumable materials that wear/erode over time. Accordingly, the height of the edge ring may be adjusted to compensate for erosion. In other examples, edge rings may be removable and replaceable (e.g., to replace eroded or damaged edge rings, to replace an edge ring with an edge ring having different geometry, etc.). Examples of substrate processing systems implementing moveable and replaceable edge rings can be found in U.S. patent application Ser. No. 14/705,430, filed on May 6, 2015, the entire contents of which are incorporated herein by reference.

Substrate processing systems and methods according to the principles of the present disclosure include middle edge rings and bottom edge rings configured to support movable top edge rings.

Referring now toFIG.1, an example substrate processing system100is shown. For example only, the substrate processing system100may be used for performing etching using RF plasma and/or other suitable substrate processing. The substrate processing system100includes a processing chamber102that encloses other components of the substrate processing system100and contains the RF plasma. The substrate processing chamber102includes an upper electrode104and a substrate support106, such as an electrostatic chuck (ESC). During operation, a substrate108is arranged on the substrate support106. While a specific substrate processing system100and chamber102are shown as an example, the principles of the present disclosure may be applied to other types of substrate processing systems and chambers, such as a substrate processing system that generates plasma in-situ, that implements remote plasma generation and delivery (e.g., using a plasma tube, a microwave tube), etc.

For example only, the upper electrode104may include a gas distribution device such as a showerhead109that introduces and distributes process gases (e.g., etch process gases). The showerhead109may include a stem portion including one end connected to a top surface of the processing chamber. A base portion is generally cylindrical and extends radially outwardly from an opposite end of the stem portion at a location that is spaced from the top surface of the processing chamber. A substrate-facing surface or faceplate of the base portion of the showerhead includes a plurality of holes through which process gas or purge gas flows. Alternately, the upper electrode104may include a conducting plate and the process gases may be introduced in another manner.

The substrate support106includes a conductive baseplate110that acts as a lower electrode. The baseplate110supports a ceramic layer112. In some examples, the ceramic layer112may comprise a heating layer, such as a ceramic multi-zone heating plate. A thermal resistance layer114(e.g., a bond layer) may be arranged between the ceramic layer112and the baseplate110. The baseplate110may include one or more coolant channels116for flowing coolant through the baseplate110.

An RF generating system120generates and outputs an RF voltage to one of the upper electrode104and the lower electrode (e.g., the baseplate110of the substrate support106). The other one of the upper electrode104and the baseplate110may be DC grounded, AC grounded or floating. For example only, the RF generating system120may include an RF voltage generator122that generates the RF voltage that is fed by a matching and distribution network124to the upper electrode104or the baseplate110. In other examples, the plasma may be generated inductively or remotely. Although, as shown for example purposes, the RF generating system120corresponds to a capacitively coupled plasma (CCP) system, the principles of the present disclosure may also be implemented in other suitable systems, such as, for example only transformer coupled plasma (TCP) systems, CCP cathode systems, remote microwave plasma generation and delivery systems, etc.

A gas delivery system130includes one or more gas sources132-1,132-2, . . . , and132-N (collectively gas sources132), where N is an integer greater than zero. The gas sources supply one or more gases (e.g., etch gas, carrier gases, purge gases, etc.) and mixtures thereof. The gas sources may also supply purge gas. The gas sources132are connected by valves134-1,134-2, . . . , and134-N (collectively valves134) and mass flow controllers136-1,136-2, . . . , and136-N (collectively mass flow controllers136) to a manifold140. An output of the manifold140is fed to the processing chamber102. For example only, the output of the manifold140is fed to the showerhead109.

A temperature controller142may be connected to a plurality of heating elements, such as thermal control elements (TCEs)144arranged in the ceramic layer112. For example, the heating elements144may include, but are not limited to, macro heating elements corresponding to respective zones in a multi-zone heating plate and/or an array of micro heating elements disposed across multiple zones of a multi-zone heating plate. The temperature controller142may be used to control the plurality of heating elements144to control a temperature of the substrate support106and the substrate108.

The temperature controller142may communicate with a coolant assembly146to control coolant flow through the channels116. For example, the coolant assembly146may include a coolant pump and reservoir. The temperature controller142operates the coolant assembly146to selectively flow the coolant through the channels116to cool the substrate support106.

A valve150and pump152may be used to evacuate reactants from the processing chamber102. A system controller160may be used to control components of the substrate processing system100. A robot170may be used to deliver substrates onto, and remove substrates from, the substrate support106. For example, the robot170may transfer substrates between the substrate support106and a load lock172. Although shown as separate controllers, the temperature controller142may be implemented within the system controller160. In some examples, a protective seal176may be provided around a perimeter of the bond layer114between the ceramic layer112and the baseplate110.

The substrate support106includes an edge ring180. The edge ring180may correspond to a top ring, which may be supported by a bottom ring184. In some examples, the edge ring180may be further supported by one or more of a middle ring (not shown inFIG.1), a stepped portion of the ceramic layer112, etc. as described below in more detail. The edge ring180is moveable (e.g., moveable upward and downward in a vertical direction) relative to the substrate108. For example, the edge ring180may be controlled via an actuator responsive to the controller160. In some examples, the edge ring180may be adjusted during substrate processing (i.e., the edge ring180may be a tunable edge ring). In other examples, the edge ring180may be removable (e.g., using the robot170, via an airlock, while the processing chamber102is under vacuum). In still other examples, the edge ring180may be both tunable and removable.

Referring now toFIGS.2A and2B, an example substrate support200having a substrate204arranged thereon is shown. The substrate support200may include a base or pedestal having an inner portion (e.g., corresponding to an ESC)208and an outer portion212. In examples, the outer portion212may be independent from, and moveable in relation to, the inner portion208. For example, the outer portion212may include a bottom ring216and a top edge ring220. The substrate204is arranged on the inner portion208(e.g., on a ceramic layer224) for processing. A controller228communicates with one or more actuators232to selectively raise and lower the edge ring220. For example, the edge ring220may be raised and/or lowered to adjust a pocket depth of the support200during processing. In another example, the edge ring220may be raised to facilitate removal and replacement of the edge ring220.

For example only, the edge ring220is shown in a fully lowered position inFIG.2Aand in a fully raised position inFIG.2B. As shown, the actuators232correspond to pin actuators configured to selectively extend and retract pins236in a vertical direction. Other suitable types of actuators may be used in other examples. For example only, the edge ring220corresponds to a ceramic or quartz edge ring, although other suitable materials may be used (e.g., silicon carbide, yttria, etc.). InFIG.2A, the controller228communicates with the actuators232to directly raise and lower the edge ring220via the pins236. In some examples, the inner portion208is moveable relative to the outer portion212.

Features of an example substrate support300are shown in more detail inFIGS.3A and3B. The substrate support300includes an insulator ring or plate304and a baseplate (e.g., of an ESC)308arranged on the insulator plate304. The baseplate308supports a ceramic layer312configured to support a substrate316arranged thereon for processing. InFIG.3A, the ceramic layer312has a non-stepped configuration. InFIG.3B, the ceramic layer312has a stepped configuration. The substrate support300includes a bottom ring320that supports an upper (“top”) edge ring324. One or more vias or guide channels328may be formed through the insulator plate304, the bottom ring320, and/or the baseplate308to accommodate respective lift pins332arranged to selectively raise and lower the edge ring324. For example, the guide channels328function as pin alignment holes for respective ones of the lift pins332. As shown inFIG.3B, the substrate support300may further include a middle ring336arranged between the bottom ring320and the edge ring324. In the stepped configuration, the middle ring336overlaps the ceramic layer312and is arranged to support an outer edge of the substrate316.

The lift pins332may comprise an erosion-resistant material (e.g., sapphire). An outer surface of the lift pins332may be polished smooth to reduce friction between the lift pins332and structural features of the bottom ring320to facilitate movement. In some examples, one or more ceramic sleeves340may be arranged in the channels328around the lift pins332. Each of the lift pins332may include a rounded upper end344to minimize contact area between the upper end344and the edge ring324. The smooth outer surface, rounded upper end344, guide channel328, and/or ceramic sleeves340facilitate raising and lowering of the edge ring324and while preventing binding of the lift pins332during movement.

As shown inFIG.3A, the bottom ring320includes a guide feature348. InFIG.3B, the middle ring336includes the guide feature348. For example, the guide feature348corresponds to a raised annular rim352that extends upward from the bottom ring320/the middle ring336. InFIG.3A, the guide channels328and the lift pins332extend through the guide feature348to engage the edge ring324. Conversely, inFIG.3B, the guide channels328and the lift pins332extend through the bottom ring320to engage the edge ring324without passing through the middle ring336.

The edge ring324includes an annular bottom groove356arranged to receive the guide feature348. For example, a profile (i.e., cross-section) shape of the edge ring324may generally correspond to a “U” shape configured to receive the guide feature348, although other suitable shapes may be used. Further, although the upper surface of the edge ring324is shown as generally horizontal (i.e., parallel to an upper surface of the substrate support300), the upper surface of the edge ring324may have a different profile in other examples. For example, the upper surface of the edge ring324may be tilted or slanted, rounded, etc. In some examples, the upper surface of the edge ring324is tilted such that a thickness at an inner diameter of the edge ring324is greater than a thickness at an outer diameter of the edge ring324to compensate for erosion at the inner diameter.

Accordingly, a bottom surface of the edge ring324is configured to be complementary to an upper surface of the bottom ring320inFIG.3A, or respective surfaces of the bottom ring320and the middle ring336inFIG.3B. Further, an interface360between the edge ring324and the bottom ring320/middle ring336is labyrinthine. In other words, the lower surface of the edge ring324and, correspondingly, the interface360, includes multiple changes of direction (e.g., 90 degree changes of direction, upward and downward steps, alternating horizontal and vertical orthogonal paths, etc.) rather than providing a direct (e.g., line of sight) path between the edge ring324and the bottom ring320/middle ring336to interior structures of the substrate support300. Typically, likelihood of plasma and process material leakage may be increased in substrate supports including multiple interfacing rings (e.g., both the top edge ring324and one or more of the middle ring336and the bottom ring320). This likelihood may be further increased when the moveable edge ring324is raised during processing. Accordingly, the interface360(and, in particular, the profile of the edge ring324) is configured to prevent process materials, plasma, etc. from reaching interior structures of the substrate support300.

For example, as shown inFIG.3A, the interface360includes five changes of direction to restrict access to the guide channels328and pins332, the ceramic layer312, a backside and edge of the substrate316, etc. Conversely, as shown inFIG.3B, the interface360includes seven changes of direction in a first path364and five changes of direction in a second path368to restrict access to the guide channels328and pins332, the ceramic layer312, a backside and edge of the substrate316, a bond layer372, a seal376, etc. Accordingly, the interface360reduces the likelihood of plasma leakage and light-up, erosion, etc. affecting the interior structures of the substrate support300.

The profile (i.e., cross-section) shape of the edge ring324(as well as the interfacing surfaces of the bottom ring320, middle ring336, etc.) is designed to facilitate manufacturing and reduce manufacturing costs. For example, walls380,384of the groove356and the guide feature340may be substantially vertical (e.g., in contrast to being parabolic, trapezoidal, triangular, etc.) to facilitate manufacturing while preventing plasma and process material leakage. For example only, substantially vertical may be defined as being perpendicular to upper and/or lower surfaces of the edge ring324, within 1° of a normal line of an upper and/or lower surface of the edge ring324, parallel to a direction of movement of the edge ring324, etc. Further, the vertical walls380,384maintain alignment of the edge ring324relative to the guide feature340during movement of the edge ring324. In contrast, when respective profiles of the groove356and the guide feature340are parabolic, trapezoidal, triangular, etc., upward movement of the edge ring324causes significant separation between the walls380and the walls384.

Surfaces of the edge ring324, the bottom ring320, and the middle ring336within the interface360(and, in particular, within the groove356) are relatively smooth and continuous to minimize friction between the edge ring324and the guide feature340during movement of the edge ring324. For example, respective surfaces of the edge ring324, the bottom ring320, and the middle ring336within the interface360may undergo additional polishing to achieve a desired surface smoothness. In other examples, surfaces of the edge ring324, the bottom ring320, and the middle ring336within the interface360may be coated with a material that further reduces friction. In still other examples, the surfaces of the edge ring324, the bottom ring320, and the middle ring336within the interface360(and, in particular, the edge ring324) may be free of screw holes and/or similar assembly features. In this manner, creation of particles due to contact between surfaces (e.g., during movement of the edge ring324) may be minimized.

When the edge ring324is raised for tuning during processing as described above, the controller228as described inFIGS.2A and2Bis configured to limit a tunable range of the edge ring324according to a height H of the guide feature348. For example, the tunable range may be limited to less than the height H of the guide feature348. For example, if the guide feature348has a height H of approximately 0.24″ (e.g., 0.22″-0.26″), the tunable range of the edge ring324may be 0.25″. In other words, the edge ring324may be raised from a fully lowered position (e.g., 0.0″) to a fully raised position (e.g., 0.25″) without entirely removing the guide feature348from the groove356in the edge ring324. Accordingly, even in the fully raised position, the edge ring324still overlaps at least a portion of the guide feature348. Limiting the range of the edge ring324in this manner retains the labyrinthine interface360as described above and prevents lateral misalignment of the edge ring324. A depth of the groove356may be approximately equal to (e.g., within 5%) of the height H of the guide feature348. The depth of the groove356may be at least 50% of the thickness of the edge ring. For example only, the tunable range of the edge ring324ofFIG.3Ais 0.15″ to 0.25″ and the tunable range of the edge ring324ofFIG.3Bis 0.05″ to 0.15″. For example, a thickness (i.e., height) of the edge ring324may be between approximately 0.50″ (e.g., 0.45″ to 0.55″) and approximately 0.6″ (e.g., 0.58″ to 0.620″), and a depth of the groove356may be approximately 0.30″ (e.g., 0.29″ to 0.31″).

For example, the “thickness” of the edge ring324, as used herein, may refer to a thickness of the edge ring324at an inner diameter of the edge ring324(e.g., a thickness/height of the edge ring324at an inner wall388). In some examples, a thickness of the edge ring324may not be uniform across an upper surface of the edge ring324(e.g., the upper surface of the edge ring324may be tilted as described above such that a thickness at the inner wall388is greater than a thickness at an outer diameter of the edge ring324). However, since erosion due to exposure to plasma may be increased at the inner wall388relative to an outer diameter of the edge ring324, the edge ring324may be formed such that the inner wall388has at least a predetermined thickness to compensate for the increased erosion at the inner wall388. For example only, the inner wall388is substantially vertical to avoid contact with the substrate316during movement of the edge ring324.

Referring now toFIGS.4A,4B, and4C, another example substrate support400is shown in more detail. The substrate support400includes an insulator ring or plate404and a baseplate408arranged on the insulator plate404. The baseplate408supports a ceramic layer412configured to support a substrate416arranged thereon for processing. InFIG.4A, the ceramic layer412has a non-stepped configuration. InFIGS.4B and4C, the ceramic layer412has a stepped configuration. The substrate support400includes a bottom ring420that supports an upper edge ring424. In the stepped configuration, the edge ring424overlaps the ceramic layer412. One or more vias or guide channels428may be formed through the insulator plate404, the bottom ring420, and/or the baseplate408to accommodate respective lift pins432arranged to selectively raise and lower the edge ring424. For example, the guide channels428function as pin alignment holes for respective ones of the lift pins432.

In the examples ofFIGS.4A,4B, and4C, the edge rings424are configured to support an outer edge of the substrate416arranged on the ceramic layer412. For example, inner diameters of the edge rings424include a step434arranged to support the outer edge of the substrate416. Accordingly, the edge ring424may be raised and lowered to facilitate removal and replacement of the edge ring424buy may not be raised and lowered during processing (i.e., the edge ring424is not tunable). For example, the edge ring424may be raised using the lift pins432for removal and replacement (e.g., using the robot170).

In an example, a lower, inside corner436of the edge ring424may be chamfered to facilitate alignment (i.e., centering) of the edge ring424on the substrate support400. Conversely, an upper, outside corner444and/or a lower, inside corner448of the ceramic layer412may be chamfered complementarily to the corner436. Accordingly, as the edge ring424is lowered onto the substrate support400, the chamfered corner436interacts with the chamfered corner(s)444/448to cause the edge ring424to self-center on the substrate support400.

An upper, outer corner456of the edge ring424may be chamfered to facilitate removal of the edge ring424from the processing chamber102. For example, since the substrate support400is configured for in situ removal of the edge ring424(i.e., without fully opening and venting the processing chamber102), the edge ring424is configured to be removed via an airlock. Typically, airlocks are sized to accommodate substrates of a predetermined size (e.g., 300 mm). However, the edge ring424has a diameter that is significantly larger than the substrate416and a typical edge ring424may not fit through the airlock. Accordingly, a diameter of the edge ring424is reduced (e.g., as compared to the edge rings324as shown inFIGS.3A and3B). For example, an outer diameter of the edge ring324is similar to an outer diameter of the bottom ring320. Conversely, an outer diameter of the edge ring424is significantly less than an outer diameter of the bottom ring420. For example only, an outer diameter of the edge ring424is less than or equal to approximately 13″ (e.g., 12.5″ to 13″). Chamfering the outer corner456further facilitates transfer of the edge ring424through the airlock.

For example only, the chamfer of the outer corner may have a height of 0.050″ to 0.070″, a width of 0.030″ to 0.050″, and an angle of 25-35°. In some examples, the chamfer of the lower corner436may have a height of approximately 0.025″ (e.g., 0.015″ to 0.040″), a width of approximately 0.015″ (e.g., 0.005″ to 0.030″), and an angle of approximately 60° (50-70°). For example only, a thickness (i.e., height) of the edge ring424is approximately, but not greater than, 0.275″ (e.g., 0.25″ to 0.30″). For example, the thickness of the edge ring424may not exceed a height of an airlock of the processing chamber102to allow removal of the edge ring424. For example only, the “thickness” of the edge ring424, as used herein, may refer to a thickness of the edge ring424at an inner diameter of the edge ring424(e.g., a thickness/height of the edge ring424at an inner wall458) as described above with respect toFIGS.3A and3B.

As shown inFIG.4C, the bottom ring420includes a guide feature460. For example, the guide feature460corresponds to a raised annular rim464that extends upward from the bottom ring420. The guide channels428and the lift pins432extend through the bottom ring420to engage the edge ring424. The edge ring424includes an annular bottom groove468arranged to receive the guide feature460. For example, a profile of the edge ring424may generally correspond to a “U” shape configured to receive the guide feature460.

Accordingly, similar to the examples ofFIGS.3A and3B, a bottom surface of the edge ring424inFIG.4Cis configured to be complementary to respective upper surfaces of the bottom ring420and the ceramic layer412to form a labyrinthine interface472. In other words, the interface472includes multiple changes of direction (e.g., 90 degree changes of direction) rather than providing a direct path between the edge ring424and the bottom ring420to interior structures of the substrate support400. In some examples, portions of the guide feature460, the edge ring424, the bottom ring420, and/or the ceramic layer412within the interface360may be chamfered to facilitate alignment (i.e., centering) of the edge ring424on the substrate support400. For example, a lower, inside corner476of an inner diameter of the edge ring424and a corresponding lower, inside corner480and/or upper, outside corner484of the ceramic layer412are chamfered. In other examples, mechanical alignment of the guide feature460within the groove468centers the edge ring324. In some examples, the chamfer of the lower corner476may have a height of approximately 0.025″ (e.g., 0.015″ to 0.040″), a width of approximately 0.015″ (e.g., 0.005″ to 0.030″), and an angle of approximately 60° (e.g., 50-60°).

Referring now toFIGS.5A and5B, another example substrate support500is shown in more detail. The substrate support500includes an insulator ring or plate504and a baseplate508arranged on the insulator plate504. The baseplate508supports a ceramic layer512configured to support a substrate516arranged thereon for processing. InFIG.5A, the ceramic layer512has a non-stepped configuration. InFIG.5B, the ceramic layer512has a stepped configuration. The substrate support500includes a bottom ring520that supports an upper edge ring524(as shown inFIG.5A) or an upper edge ring526(as shown inFIG.5B). One or more vias or guide channels528may be formed through the insulator plate504, the bottom ring520, and/or the baseplate508to accommodate respective lift pins532arranged to selectively raise and lower the edge ring524/526. For example, the guide channels528function as pin alignment holes for respective ones of the lift pins532. As shown inFIG.5B, the substrate support500may further include a middle ring536arranged between the bottom ring520and the edge ring526. In the stepped configuration, the middle ring536overlaps the ceramic layer512and is arranged to support an outer edge of the substrate516.

The examples ofFIGS.5A and5Bcombine features of both the tunable edge rings324ofFIGS.3A and3Band the removable/replaceable edge rings ofFIGS.4A,4B, and4C. For example, even in the stepped configuration ofFIG.5B, the edge ring526does not extend beneath and support the substrate516. Accordingly, the edge ring524/526may be raised and lowered during processing. For example only, a tunable range of the edge ring524ofFIG.5Ais 0.05″ to 0.15″ and a tunable range of the edge ring526ofFIG.5Bis 0.02″ to 0.05″. Further, an outer diameter of the edge ring524/526is reduced as described with respect toFIGS.4A,4B, and4Cto facilitate transfer of the edge ring524/526through an airlock. Accordingly, the edge ring524/526may be removed and replaced in situ as described above.

As shown inFIG.5A, the bottom ring520includes a guide feature540. InFIG.5B, the middle ring536includes the guide feature540. For example, the guide feature540corresponds to a raised annular rim544that extends upward from the bottom ring520/the middle ring536. In each ofFIGS.5A and5B, the guide channels528and the lift pins532extend through the bottom ring520to engage the edge ring524/526. For example, the edge ring524/526includes an annular bottom groove548arranged to receive the guide feature540. For example, a profile of the edge ring524/526may generally correspond to a “U” shape configured to receive the guide feature540.

Accordingly, similar to the examples ofFIGS.3A,3B, and4C, a bottom surface of the edge ring524/526is configured to be complementary to respective upper surfaces of the bottom ring520and the middle ring536to form a labyrinthine interface552. In other words, the interface552includes multiple changes of direction (e.g., 90 degree changes of direction) rather than providing a direct path between the edge ring524/526and the bottom ring520to interior structures of the substrate support500. In some examples, portions of the guide feature540, the edge ring524/526, the bottom ring520, and/or the middle ring536within the interface552may be chamfered to facilitate alignment (i.e., centering) of the edge ring524/526on the substrate support500. For example, inFIG.5A, corners556and558of the edge ring524and complementary corners560of the guide feature540and562of the bottom ring520are chamfered. Conversely, inFIG.5B, only the corner556of the edge ring526and the corner560of the bottom ring520are chamfered. An upper, outer corner564of the edge ring524may be chamfered to facilitate removal of the edge ring524from the processing chamber102as described above with respect toFIGS.4A,4B, and4C.

For example only, the chamfers of the lower corners556and558may have a height and width of approximately 0.005″ to 0.030″ and an angle of approximately 25 to 35°. For example, a thickness (i.e., height) of the edge ring524/526may be approximately, but not greater than, 0.25″ (e.g., 0.25″ to 0.26″) and a depth of the groove548may be 0.200″ to 0.220″. A difference between the thickness of the edge ring524/526and the depth of the groove548may be not less than 0.075″. For example, the thickness of the edge ring524/526may not exceed a height of an airlock of the processing chamber102to allow removal of the edge ring524/526. However, the thickness of the edge ring524/526may also be maximized, without exceeding the height of the airlock, to optimize tunability of the edge ring524/526. In other words, as the edge ring524/526erodes over time, the amount the edge ring524/526may be raised without needing to be replaced increases proportionately to the thickness of the edge ring524/526. For example only, the “thickness” of the edge ring524/526as used herein, may refer to a thickness of the edge ring524/526at an inner diameter of the edge ring524/526(e.g., a thickness/height of the edge ring524/526at an inner wall568) as described above with respect toFIGS.3A,3B,4A,4B, and4C.

Referring now toFIGS.6A and6B, an example bottom ring600(e.g., corresponding to any of the bottom rings320,420, or520) may implement a clocking feature to facilitate alignment of the bottom ring600with an insulator ring604. The bottom ring600includes a plurality of guide channels608arranged to receive respective lift pins612extending through the insulator ring604. The bottom ring600further includes one or more clocking features, such as a notch616. The notch616is configured to receive a complementary structure, such as a projection620, extending upward from the insulator ring604. Accordingly, the bottom ring600may be installed such that the notch616is aligned with and receives the projection620to ensure that the guide channels608are aligned with respective ones of the lift pins612.

Referring now toFIGS.7A,7B, and7C, a substrate support700includes example bottom rings704,708, and712configured to support top moveable edge rings in a non-stepped configuration according to the principles of the present disclosure. For example, as shown inFIG.7A, the bottom ring704is configured to support the edge ring324ofFIG.3A. As shown inFIG.7B, the bottom ring708is configured to support the edge ring424ofFIG.4A. As shown inFIG.7C, the bottom ring712is configured to support the edge ring524ofFIG.5A. Respective upper surfaces of each of the bottom rings704,708, and712is stepped. In other words, each of the respective upper surfaces has at least two different heights.

The substrate support700includes an insulator ring or plate716and a baseplate (e.g., of an ESC)720arranged on the insulator plate716. The baseplate720supports a ceramic layer724configured to support a substrate thereon for processing. One or more vias or guide channels728may be formed through the insulator plate716and the bottom rings704,708,712to accommodate lift pins732arranged to selectively raise and lower the respective edge rings. For example, the guide channels728function as pin alignment holes for respective ones of the lift pins732. A gap between the lift pins732and inner surfaces of the guide channels728is minimized to decrease plasma leakage. In other words, a diameter of the guide channels728is only slightly greater (e.g., 0.005″-0.010″ greater) than a diameter of the lift pins732. For example, the lift pins732may have a diameter of 0.057″-0.061″ while the guide channels728have a diameter of 0.063″-0.067″. In some examples, the guide channels728include narrow regions734that have a diameter that is less than other portions of the guide channels728to further restrict plasma leakage. For example, the narrow regions734may have a diameter that is 0.002-0.004″ less than the diameter of the guide channels728. Similarly, in some examples, the lift pins732may include narrow regions located within the narrow regions734of the guide channels728.

As shown inFIG.7A, the bottom ring704includes a guide feature736. For example, the guide feature736corresponds to a raised annular rim740that extends upward from the bottom ring704. The rim740and an inner annular rim742define a groove744. The guide channels728and the lift pins732extend through the guide feature736. An upper surface of the bottom ring704is configured to be complementary to a bottom surface of the edge ring324to form a labyrinthine interface including multiple changes of direction as described above. Respective widths of the groove744and the rim740are selected to minimize gaps between respective vertical surfaces of the groove744and the rim740and complementary vertical surfaces on the bottom of the edge ring324. For example, the gaps may be less than 0.02″.

Similarly, as shown inFIG.7C, the bottom ring712includes a guide feature746. For example, the guide feature746corresponds to a raised annular rim748that extends upward from the bottom ring712. The rim748and an inner annular rim750define a first groove752while the rim748and an outer annular rim754define a second groove756. The guide channels728and the lift pins732extend through the bottom ring712. An upper surface of the bottom ring712is configured to be complementary to a bottom surface of the edge ring524to form a labyrinthine interface including multiple changes of direction as described above. A height of the rim748is greater than a height of the inner annular rim750to facilitate engagement of the rim748with the edge ring524prior to contact between the inner annular rim750and the edge ring524.

In some examples, portions of the guide feature746and/or the bottom ring712may be chamfered to facilitate alignment (i.e., centering) of the edge ring524on the substrate support700. For example, corners760and764of the guide feature746and corner768of the bottom ring712are chamfered. In some examples, the chamfer of the corner760may have a height and width of at least approximately 0.008″ (e.g., 0.007″ to 0.011″) and an angle of 15-25°. The chamfer of the corner764may have a height and width of at least approximately 0.01″ (e.g., 0.01″ to 0.02″) and an angle of 20-35°. The chamfer of the corner768may have a height and width of at least approximately 0.010″ (e.g., 0.010″ to 0.030″) and an angle of 20-35°.

Inner diameters of the bottom rings704,708, and712may be at least 11.5″ (e.g., between 11.5″ and 11.7″). Outer diameters of the bottom rings704,708, and712may be no greater than 14″ (e.g., between 13.8″ and 14.1″). Step inner diameters of the bottom rings708and712at772are selected to accommodate the outer diameter of the edge ring424or524. For example, the outer diameter of the edge ring424or524may be approximately 12.8″ (e.g., +/−0.10″). Accordingly, the inner diameter of the bottom rings708and712at772may be at least 13.0″.

Referring now toFIGS.8A,8B, and8C, a substrate support800includes example bottom rings804,808, and812configured to support top moveable edge rings in a stepped configuration according to the principles of the present disclosure. For example, as shown inFIG.8A, the bottom ring804is configured to support the edge ring324ofFIG.3B. As shown inFIG.8B, the bottom ring808is configured to support the edge ring424ofFIG.4C. As shown inFIG.8C, the bottom ring812is configured to support the edge ring526ofFIG.5B. The bottom rings804and812may be further configured to support the middle ring336ofFIG.3Band the middle ring536ofFIG.5B, respectively. Respective upper surfaces of each of the bottom rings804,808, and812is stepped. In other words, each of the respective upper surfaces has at least two different heights.

The substrate support800includes an insulator ring or plate816and a baseplate (e.g., of an ESC)820arranged on the insulator plate816. The baseplate820supports a ceramic layer824configured to support a substrate thereon for processing. A bond layer828may be arranged between the baseplate820and the ceramic layer824and a seal832surrounds the bond layer828. One or more vias or guide channels836may be formed through the insulator plate816and the bottom rings804,808, and812to accommodate lift pins840arranged to selectively raise and lower the respective edge rings. For example, the guide channels836function as pin alignment holes for respective ones of the lift pins840. A gap between the lift pins840and inner surfaces of the guide channels836is minimized to decrease plasma leakage. In other words, a diameter of the guide channels836is only slightly greater (e.g., 0.005″-0.010″ greater) than a diameter of the lift pins840. For example, the lift pins840may have a diameter of 0.1″ while the guide channels836have a diameter of 0.105″. In some examples, the guide channels836include narrow regions842that have a diameter that is less than other portions of the guide channels836to further restrict plasma leakage. For example, the narrow regions842may have a diameter that is 0.002-0.004″ less than the diameter of the guide channels836. In some examples, one or more ceramic sleeves844may be arranged in the channels836around the lift pins840.

As shown inFIG.8B, the bottom ring808includes a guide feature846. For example, the guide feature846corresponds to a raised annular rim848that extends upward from the bottom ring808. The rim848and an outer annular rim850define a groove852. An upper surface of the bottom ring808is configured to be complementary to a bottom surface of the edge ring424to form a labyrinthine interface including multiple changes of direction as described above. Respective widths of the groove852and the rim848are selected to minimize gaps between respective vertical surfaces of the groove852and the rim848and complementary vertical surfaces on the bottom of the edge ring424. For example, the gaps may be less than 0.010″. Conversely, inFIG.8A and8C, the bottom rings804and812are configured to support the middle rings336and536having respective guide features348and540. Accordingly, upper surfaces of the bottom rings804and812are configured to be, in combination with upper surfaces of the middle rings336and536, complementary to bottom surfaces of the edge rings324and526to form a labyrinthine interface including multiple changes of direction as described above.

In examples where the guide channels836include the ceramic sleeves844(e.g., examples where the guide channels836are routed through the baseplate820), the bottom rings804,808, and812may be configured to accommodate the ceramic sleeves844. For example, the bottom rings804,808, and812may include a clearance feature such as cavity or cutout856having a greater diameter than the guide channels836to accommodate upper ends of the ceramic sleeves844. In some examples, the bottom rings804,808, and812may be installed subsequent to the lift pins840. Accordingly, respective openings in the bottom rings804,808, and812may include a chamfered edge860to facilitate installation of the bottom rings804,808, and812over the lift pins840. For example, the chamfer of the edge860may have a height and width of 0.020″ to 0.035″ and an angle of 40-50°.

As shown inFIGS.8B and8C, step inner diameters of the bottom rings808and812at862are selected to accommodate the outer diameter of the edge rings424ofFIG.4C and526ofFIG.5B. For example, the outer diameter of the edge rings424and526may be approximately 12.8″ (e.g., +/−0.10″). Accordingly, the inner diameters of the bottom rings808and812at862may be at least 13.0″. Accordingly, a gap between the bottom rings808and812and the outer diameter of the edge rings424and526can be minimized while still preventing contact between vertical surfaces of the bottom rings808and812and the edge rings424and526.

In some examples, such as shown inFIG.8B, the bottom ring808may include a first outer diameter at864and a second outer diameter at868. The second outer diameter868is greater than the first outer diameter at864. For example, the substrate support800may include a liner872that protects outer portions of the insulator plate816, the baseplate820, the bottom ring808, etc. However, the liner872may not protect upper portions of the bottom ring808that are exposed to plasma, and increased erosion of the bottom ring808in a region adjacent to an upper edge876of the baseplate820(as indicated by dashed arrow880) may occur. Accordingly, the bottom ring808includes additional material at the second outer diameter868to compensate for the increased erosion.

Referring now toFIG.9, an example middle ring900is shown. The middle ring900may be provided in configurations where the top edge ring would otherwise be supported by upper surfaces of two different components of a substrate support. For example, as shown inFIGS.3B and5B(corresponding toFIGS.8A and8C, respectively), the top edge rings overlap both a respective ceramic layer and a respective bottom ring. Accordingly, the middle ring900is arranged to support a portion of the top edge ring that would otherwise by supported by the ceramic layer. As shown, the middle ring900is “U”-shaped.

The middle ring900includes an inner annular rim904and an outer annular rim908defining a groove912. The groove912is configured to receive a respective top edge ring (e.g., the edge ring324or526). Conversely, the outer annular rim908functions as a guide feature to center the top edge ring324or526during replacement as described above inFIGS.3B and5B. In some examples, corners916and920are chamfered to facilitate engagement with the top edge ring. For example, the chamfer of the corner916may have a height and width of at least approximately 0.010″ (e.g., 0.005″ to 0.015″) and an angle of approximately 20° (e.g., 15-25°). The chamfer of the corner920may have a height and width of at least approximately 0.015″ (e.g., 0.010″ to 0.020″) and an angle of approximately 30° (e.g., 25-35°). A width of the outer annular rim908is selected to minimize gaps between respective vertical surfaces of the rim908and complementary vertical surfaces on the bottom of the edge ring324or526. For example, the gaps may be less than 0.010″ to restrict plasma leakage.

Referring now toFIGS.10A and10B, two cross-sectional views of a substrate support1000illustrate a bottom ring1004configured to support top moveable edge rings in a stepped configuration according to the principles of the present disclosure. For example, the bottom ring1004is configured to support an edge ring (e.g.,526) in a configuration similar to that shown inFIGS.5B and8C. The bottom ring1004may be further configured to support a middle ring in a configuration similar to that shown inFIG.5B.

The substrate support1000includes an insulator ring or plate1008and a baseplate (e.g., of an ESC)1012arranged on the insulator plate1008. The baseplate1012supports a ceramic layer1016configured to support a substrate thereon for processing. A bond layer1020may be arranged between the baseplate1012and the ceramic layer1016and a seal1024surrounds the bond layer1020. As shown inFIG.10A, one or more vias or guide channels1028may be formed through the insulator plate1008, the baseplate1012, and the bottom ring1004to accommodate lift pins1032arranged to selectively raise and lower the edge ring. For example, the guide channels1028function as pin alignment holes for respective ones of the lift pins1032. A gap between the lift pins1032and inner surfaces of the guide channels1028is minimized to decrease plasma leakage. In other words, a diameter of the guide channels1028is only slightly greater (e.g., 0.005″-0.010″ greater) than a diameter of the lift pins1032. For example, the lift pins1032may have a diameter of 0.1″ while the guide channels1028have a diameter of 0.105″. In some examples, the guide channels1028include narrow regions1036that have a diameter that is less than other portions of the guide channels1028to further restrict plasma leakage. For example, the narrow regions1036may have a diameter that is 0.002-0.004″ less than the diameter of the guide channels1028. In some examples, one or more ceramic sleeves1040may be arranged in the channels1028around the lift pins1032.

The substrate support1000may include a liner1044arranged to enclose and protect components of the substrate support1000such as the insulator plate1008, the baseplate1012, and the bottom ring1004. The bottom ring1004as shown inFIGS.10A and10Bincludes an annular lip1048extending radially outward from the bottom ring1004above the liner1044. The lip1048facilitates installation and removal of the bottom ring1004when the liner1044is present.

As shown inFIG.10B, the baseplate1012may be coupled to the insulator plate1008using bolts1052inserted through respective bolt mounting holes1056. Ceramic plugs1060are arranged above the bolts1052to prevent plasma leakage in the bolt mounting holes1056and between the bottom ring1004and the baseplate1012. The bottom ring1004as shown inFIG.10Bincludes clearance features such as cavities or cutouts1064to accommodate the ceramic plugs1060.

The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and/or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.

Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”

In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.

Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

The controller, in some implementations, may be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.

As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and/or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another remain within the scope of this disclosure.

Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”

In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.

Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

The controller, in some implementations, may be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.

As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.