Patent ID: 12260129

DETAILED DESCRIPTION

To provide an overall understanding of the devices described herein, certain illustrative embodiments will be described. Although the embodiments and features described herein are specifically described for use in connection with a solid-state drive (SSD) having a controller, it will be understood that all the components and other features outlined below may be implemented in a variety of fashions in either hardware or firmware of an SSD in any suitable manner, and may be adapted and applied to other types of SSD architectures having a similar need to avoid burdensome read retry flows caused by executing read commands based on a default threshold. Further, all of the components and other features outlined below may be implemented in other types of nonvolatile memory devices, including universal flash storage (UFS) devices or secure digital (SD) card devices.

The present disclosure provides a method for tracking a threshold voltage used to read data from a NAND device by a controller of an SSD, and for updating the threshold voltage in the event that the data read from the NAND device has a corresponding bit error rate (BER) that exceeds some threshold. By tracking and updating the threshold voltage, burdensome read retry flows are avoided, system degradation is prevented, and system performance overall is improved.

As explained herein, the threshold tracking mechanism exploits the relationship between MLC NAND flash characteristics and different stress conditions. In particular, the failed bit count (FBC) results of ECC in the upper and lower pages of MLC NAND flash and stress type and magnitude are correlated. The tracking mechanism uses this correlation, as well as ECC decoding statistics of pages that have already been read and decoded in a standard, functional read flow, to estimate new read-thresholds. Such thresholds can be estimated, optimized, and adjusted to yield a BER that can be corrected by ECC, so that retry flows are not invoked. The read threshold tracking/adaptation mechanism and BER estimation method are simple and effective, and can be implemented both in hardware or firmware.

Implementation of such tracking mechanisms can be done with zero overhead: no additional buffer or NAND reads are required, as the statistics on which the estimations are based are gathered contemporaneously with the issued functional read commands. The tracking mechanisms described herein improve system performance and enable working with a higher endurance, as occurrences read-retry events followed by reading pages with default read-thresholds are reduced). The result is optimized quality of service (QOS) and continuous, successful hard-decoding due to the matching of stresses and thresholds.

FIG.1is a block diagram of a memory system comprising an SSD100in communication with a host105. The host105may be a computing system that comprises processors, memories, and other components as generally known in the art. Such components of the host105are not illustrated inFIG.1for the sake of brevity. SSD100may communicate with host105via a host interface120. SSD100may further comprise a controller110, which itself may comprise a codebook112, a processor114, and an ECC module116. Codebook112is, in some embodiments, a data structure in which information regarding read voltage thresholds is accessed, stored, and updated as described herein. Codebook112may be embodied as a storage component on controller110, or may be implemented as a component of processor114. ECC module116is, in some embodiments, a component of controller110configured to implement ECC on the codewords read from NAND devices140of SSD100. ECC module116provides statistics on the BERs of the blocks of the NAND devices140, as ascertained from the results of the ECC applied to the codewords read therefrom. ECC module116may be implemented as hardware, software, or as a combination of both hardware and software. Controller110is configured to track the threshold voltages used to execute read commands received from host105, and, in some embodiments, is further configured to update the threshold voltages based on the block BER statistics determined by ECC module116.

Controller110communicates via NAND interface130with a plurality of nonvolatile memory devices140. WhileFIG.1shows that SSD100comprises NAND devices140, other nonvolatile memory devices could be implemented in SSD100without loss of generality.

Controller110, host interface120, and NAND interface130may be implemented as a system-on-a-chip (SoC). SoCs are advantageous as they provide a single integrated circuit that contains all of the circuitry and components of the electronic system for SSD100to function.

FIGS.2A-2Crepresent illustrative voltage threshold distributions used to read data from multi-level cell (MLC) NAND devices with four programmable states. As described above, NAND devices subject to stress, including data retention (“DR”) stress and read disturb (“RD”) stress are subject to failure. In particular, and as shown in the illustrative distributions ofFIGS.2A-2C, the voltage thresholds used to read data from particular pages of MLC blocks may shift in response to stress. This shifting in voltage threshold leads errors.

FIG.2Ademonstrates an exemplary voltage threshold distribution used to read data from an MLC NAND device in the absence of stress.FIG.2Ahas four voltage threshold lobes:201,202,203, and204.FIG.2Afurther shows three voltage thresholds: T0, T1, and T2. To read data from the lower page, the device may use threshold T0. Thresholds T1and T2are used to read data from the upper page of the device. The lowermost lobe201represents an “erase” state.

FIG.2Bdemonstrates the effect of data retention stresses on the exemplary voltage threshold distribution ofFIG.2A. Electron detrapping caused by large elapsed times between programming operations and read operations may cause lobes202′ and203′ to shift leftwards, towards lower voltages. As a consequence, when a read operation is performed on an MLC NAND device subject to data retention stresses using default threshold T1, the result might erroneously read the state of the upper page of the cell to be a ‘1’ when, in actuality, the upper page was programmed to state ‘0’. Similarly, if the read operation is performed using default threshold T0, the state of the lower page may be erroneously read as a ‘1’ when, in actuality, the lower page was programmed to state ‘0’.

FIG.2Cdemonstrates the effect of read disturb stresses on the exemplary voltage threshold distribution ofFIG.2A. Pass-through voltages applied to cells sharing a common bit line with a cell subject to a read operation cause lobes201″ and202″ to shift rightwards, towards higher voltages. As a consequence, when a read operation is performed on an MLC NAND device subject to data retention stresses using default threshold T1, the result might erroneously read the state of the upper page of the cell to be a ‘0’ when, in actuality, the upper page was programmed to state ‘1’. Similarly, if the read operation is performed using default threshold T0, the state of the lower page may be erroneously read as a ‘0’ when, in actuality, the lower page was programmed to state ‘1’.

In order to track and update the read voltage threshold used to read codewords from MLC NAND devices that have been subject to read disturb or data retention stresses, controller110of SSD100ofFIG.1comprises a codebook112, a processor114, and ECC module116. Exemplary tracking and updating operations of controller110by codebook112, processor114, and ECC module116are described below with respect toFIGS.3-9.

FIGS.3A and3Billustrate in detail an exemplary codebook112for use in such a tracking mechanism. The codebook112ofFIGS.3A and3Bmay be, in some embodiments, configured for use as the codebook112ofFIG.1. As described above, codebook112may be stored in controller110.FIG.3Arepresents a history table302, andFIG.3Brepresents a codebook table304. History table302keeps, for each combination block and die of an MLC NAND device, an entry pointing a specific entry in codebook table304. Codebook table304contains up-to-date read thresholds associated with a particular stress for each block. Thus, using codebook112, the up-to-date read threshold can be selected, from codebook table304, based on the particular combination of block and die of interest in history table302. Both of history table302and codebook table304may be implemented in codebook112as look-up tables.

The exemplary codebook112ofFIGS.3A and3Bassumes that the MLC NAND system has four NAND dies, each die having 8 blocks. However, the codebook ofFIGS.3A and3Bcould be implemented in any configuration of MLC NAND without loss of generality. For the exemplary codebook ofFIGS.3A and3B, history table302is of size 32×4: there are 32 blocks in the exemplary system of the embodiment, and each corresponding entry to the history table has 4 bits. Codebook table304has size 16×39: there are 16 entries in the table, each entry corresponding to 3 read thresholds (as described above with respect toFIGS.2A-2C), and each read threshold corresponds to 13 bits that represents a threshold voltage level ranging from, for example, 0 to 8,192 mV. While the entries of codebook table304ofFIG.3Bare arranged in ascending order between and within each threshold, any suitable ordering of codebook table entries can be implemented. For a particular entry in codebook304, {TQ, T1j, T2k}, for 0≤i,j,k,≤3, the content of codebook table304is set using a for loop as described by exemplary code:

For i=0:3For j=0:3For k=0:3Row(i*4+j*4+k*4) = {T0i,T1j,T2k} (1)End for-loop ‘k’End for-loop ‘j’End for-loop ‘i’

Implementing the codebook ofFIGS.3A and3Bin controller110of SSD100allows read thresholds to be tracked and adjusted in response to particular stresses with a low memory footprint. Further, the codebook entries can be updated with a very low complexity.

The entries in codebook table304are updated over time in response to ECC statistics of codewords from pages that are read and decoded in standard, functional read flows. The updated entries to codebook table304are voltages that, when applied to read commands, return codewords having BERs that are correctable by ECC, as described herein. When a read threshold update trigger indication is asserted by ECC statistics, a new codebook index can be found. The new codebook index may point to an entry in codebook table304that provides threshold more appropriate for the actual stress. By updating the entries in codebook table304as such, the described embodiments avoid decoding failure events and prevent QoS degradation.

In order for the read voltage thresholds stored in the codebook ofFIGS.3A and3Bto be updated, the stress on each MLC NAND device can be analyzed, and a subsequent adjustment, or offset, to the stored read voltage threshold can be calculated. In particular, the BER corresponding to a codeword read from each block of a particular NAND device in response to a read command can be calculated, and a new threshold voltage can be calculated so as to lower the BER of subsequent codewords read by subsequent read commands executed on the block.

The updated read voltage threshold VTUpdatedmay be calculated based on the stored read voltage threshold VTStoredas described above with respect toFIG.3B, and the offset ΔVT in accordance with exemplary formula 2:

VTupdate=VTstored+Δ⁢VT.(2)

The offset ΔVT may be further calculated in accordance with exemplary formula 3:

Δ⁢VT=16⁢Δ⁢T0+4⁢Δ⁢T1+Δ⁢T2,(3)
where ΔT0, ΔT1, and ΔT2, represent offset values that are equal to 0, 1, or −1, depending on the type and magnitude of the stress to which the MLC NAND device is subject. As explained herein, positive offset values may be implemented when a system is subject to read disturb stress (as read disturb stress has the tendency to increase the voltage of all memory cells), and negative offset values may be implemented when a system is subject to data retention stress (as data retention stress has the tendency to reduce the voltage of all memory cells). For typical magnitudes of read disturb and data retention stress, the offset values used may be of magnitude 1. However, in instances in which the magnitude of the stress on the system is particular large, ΔT0, ΔT1, and ΔT2, may in general be any integer values in proportion to |P0-P1|, as this value indicates the magnitude of the read threshold shift due to stress on the MLC NAND.

FIGS.4A-4Jdemonstrate various different cases of RD and DR stresses, andFIG.5describes, for the cases ofFIGS.4B-4G, the impact of the stress on the states of each page, statistical observations for ECC applied to each such page, and the offset values that are used in the calculation of ΔVT.

FIG.4Aagain reproduces the exemplary voltage threshold distribution used to read data from an MLC NAND device in the absence of stress.

FIG.4Bdemonstrates the effect of RD stress on the system ofFIG.4A. InFIG.4B, it can be seen that lobe405has shifted to the right, relative to unstressed lobe401inFIG.4A. Row509of the table inFIG.5describes the stress impact, ECC statistical observations, and offset values for calculation of ΔVT forFIG.4B. In particular, in the case ofFIG.4B, the lower page of the read block is unaffected (column506), but data may be erroneously read from the upper page using threshold T1. In particular, a read command executed on an MLC device under the stress ofFIG.4Bmay return a ‘0’ from the upper page of the block, when in actuality the state was programmed to a ‘1’ (column508). Reads from the upper page using threshold T2are unaffected (column510). For the lower page, the BER is low (“L”, column512) and, as such, there is a small probability that, for the lower page, any data will be erroneously read (column514). However, there is a high probability (“H”, column516) that data will be erroneously read from the upper page. In particular, ECC will detect more ‘1’s erroneously read as ‘0’s (“P0”) than it will ‘0’s erroneously read as ‘1’s (“P1”). Accordingly, for the upper page in the case ofFIG.4B, P0>P1(column518). Finally, for the case ofFIG.4B, because the erroneous reads arise from the voltage threshold increasing beyond threshold T1, the updated read voltage threshold should be increased to prevent such errors. Accordingly, the offset ΔVT is computed using a value of 1 for ΔT1.

FIG.4Cdemonstrates another effect of RD stress on the system ofFIG.4A. InFIG.4C, it can be seen that both lobes409and410have shifted to the right, relative to unstressed lobes401and402inFIG.4A. Row511of the table inFIG.5describes the stress impact, ECC statistical observations, and offset values for calculation of ΔVT forFIG.4C. In particular, in the case ofFIG.4C, data may be erroneously read from the lower page using threshold T0. A read command executed on an MLC device under the stress ofFIG.4Cmay return a ‘0’ from the lower page of the block when the page was programmed to a ‘1’ (column506). Further, a read command executed using threshold T1may also return a ‘0’ from the upper page of the block when the page was programmed to a ‘1’ (column508). Reads from the upper page using threshold T2are unaffected (column510). For the lower page, the BER is high (“H”, column512) and, ECC will detect more ‘1’s erroneously read as ‘0’s (“P0”) than it will ‘0’s erroneously read as ‘1’s (“P1”). Accordingly, for the lower page in the case ofFIG.4C, P0>P1(column514). Further, there is a high probability (“H”, column516) that data will be erroneously read from the upper page. In particular, ECC will detect more ‘1’s erroneously read as ‘0’s (“P0”) than it will ‘0’s erroneously read as ‘1’s (“P1”). Accordingly, for the upper page in the case ofFIG.4C, P0>P1(column518). Finally, for the case ofFIG.4C, because the erroneous reads arise from voltage thresholds increasing beyond thresholds T0and T1, both such thresholds need to be positively shifted, and the offset ΔVT is computed using a value of 1 for both ΔT0and ΔT1.

FIG.4Ddemonstrates a third case of RD stress on the system ofFIG.4A. InFIG.4D, lobes413,414, and415have shifted to the right, relative to unstressed lobes401,402, and403inFIG.4A. Row513of the table inFIG.5describes the stress impact, ECC statistical observations, and offset values for calculation of ΔVT forFIG.4D. In particular, in the case ofFIG.4C, data may be erroneously read from the lower page using threshold T0. A read command executed on an MLC device under the stress ofFIG.4Cmay return a ‘0’ from the lower page of the block when the page was programmed to a ‘1’ (column506). Further, a read command executed using threshold T1may also return a ‘0’ from the upper page of the block when the page was programmed to a ‘1’ (column508). Finally, for large enough RD stress, a read command executed using threshold T2may return a ‘1’ from the upper page of the block when the page was programmed to a ‘0’ (column510). For both pages, BER is high (“H”, columns512and516). For the lower page, ECC will detect more ‘1’s erroneously read as ‘0’s (“P0”) than it will ‘0’s erroneously read as ‘1’s (“P1”). Accordingly, for the lower page in the case ofFIG.4D, P0>P1(column514). In the upper page, because both read thresholds T1and T2are affected by the RD stress ofFIG.4D, ‘1’s and ‘O’s will be erroneously read with a roughly similar frequency. Thus, P0≈P1(column518). Finally, for the case ofFIG.4D, because the erroneous reads arise from voltage thresholds increasing beyond all thresholds, all thresholds need to be positively shifted, and the offset ΔVT is computed using a value of 1 for each of ΔT0, ΔT1, and ΔT2.

FIG.4Edemonstrates an effect of DR stress on the system ofFIG.4A. InFIG.4E, it can be seen that both lobes418and419have shifted to the left, relative to unstressed lobes402and403inFIG.4A. Row515of the table inFIG.5describes the stress impact, ECC statistical observations, and offset values for calculation of ΔVT forFIG.4E. In particular, in the case ofFIG.4E, data may be erroneously read from the lower page using threshold T0. A read command executed on an MLC device under the stress ofFIG.4Emay return a ‘1’ from the lower page of the block when the page was programmed to a ‘0’ (column506). Further, a read command executed using threshold T1may also return a ‘1’ from the upper page of the block when the page was programmed to a ‘0’ (column508). Reads from the upper page using threshold T2are unaffected (column510). For the lower page, the BER is high (“H”, column512) and, ECC will detect more ‘0’s erroneously read as ‘1’s (“P1”) than it will ‘1’s erroneously read as ‘O’s (“P0”). Accordingly, for the lower page in the case ofFIG.4E, P0<P1(column514). Further, there is a high probability (“H”, column516) that data will be erroneously read from the upper page. In particular, ECC will detect more ‘0’s erroneously read as ‘1’s (“P1”) than it will ‘1’s erroneously read as ‘0’s (“P0”). Accordingly, for the upper page in the case ofFIG.4E, P0<P1(column518). Finally, for the case ofFIG.4E, because the erroneous reads arise from voltage thresholds decreasing beyond thresholds T0and T1, both such thresholds need to be negatively shifted, and the offset ΔVT is computed using a value of −1 for both ΔT0and ΔT1.

FIG.4Fdemonstrates another effect of DR stress on the system ofFIG.4A. InFIG.4F, it can be seen that lobes422,423, and424have shifted to the left, relative to unstressed lobes402,403, and404inFIG.4A. Row517of the table inFIG.5describes the stress impact, ECC statistical observations, and offset values for calculation of ΔVT forFIG.4F. In particular, in the case ofFIG.4F, data may be erroneously read from the lower page using threshold T0. A read command executed on an MLC device under the stress ofFIG.4Fmay return a ‘1’ from the lower page of the block when the page was programmed to a ‘0’ (column506). Further, a read command executed using threshold T1may also return a ‘1’ from the upper page of the block when the page was programmed to a ‘0’ (column508). A read command executed using threshold T2may return a ‘0’ from the upper page of the block when the page was programmed to a ‘1’ (column510). For the lower page, the BER is high (“H”, column512) and, ECC will detect more ‘0’s erroneously read as ‘1’s (“P1”) than it will ‘I’s erroneously read as ‘0’s (“P0”). Accordingly, for the lower page in the case ofFIG.4F, P0<P1(column514). Further, there is a high probability (“H”, column516) that data will be erroneously read from the upper page. In the upper page, because both read thresholds T1and T2are affected by the DR stress ofFIG.4F, ‘1’s and ‘0’s will be erroneously read with a roughly similar frequency. Thus, P0≈P1(column518). Finally, for the case ofFIG.4F, because the erroneous reads arise from each voltage threshold decreasing beyond the default thresholds, each threshold needs to be negatively shifted, and the offset ΔVT is computed using a value of −1 for ΔT0, ΔT1, and ΔT2.

FIG.4Gdemonstrates another effect of DR stress on the system ofFIG.4A. InFIG.4G, it can be seen that lobe426has shifted to the left, relative to unstressed lobe402inFIG.4A. Row519of the table inFIG.5describes the stress impact, ECC statistical observations, and offset values for calculation of ΔVT forFIG.4G. In particular, in the case ofFIG.4G, reads from the lower page of the MLC NAND device are unaffected (column506). However, a read command executed using threshold T1may return a ‘1’ from the upper page of the block when the page was programmed to a ‘0’ (column508). A read command executed on the upper page of the MLC NAND device using threshold T2will also be unaffected (column510). For the lower page, the BER is low (“L”, column512) and, there is a small probability that ECC will erroneous bits (column514). However, there is a high probability (“H”, column516) that data will be erroneously read from the upper page. For the upper page, because ECC will detect more ‘0’s erroneously read as ‘1’s (“P1”) than it will ‘1’s erroneously read as ‘0’s (“P0”), P0<P1(column518). Finally, for the case ofFIG.4G, because the erroneous reads arise from the voltage threshold decreasing beyond threshold T1, the offset ΔVT is computed using a value of −1 for ΔT1.

FIG.4Hdemonstrates data taken of a voltage threshold distribution from a SSD subject to one year of data retention stress and one program/erase cycle. It can be observed that reading this page with default read voltage thresholds provides no errors, as none of lobes429,430, or431shift past the delineated thresholds marked by vertical lines.FIG.4Idemonstrates data taken of a voltage threshold distribution from a SSD subject to 1 year of data retention and 6,000 program/erase cycles. It can be observed that reading this page with default read voltage thresholds provides several errors both in the lower and upper pages, as lobes432and433shift past the delineated thresholds. This scenario is similar to that described inFIG.4E, with a moderate magnitude of | P0-P1|. The errors demonstrated inFIG.4Imay result an offset of magnitude ‘1’.FIG.4Jdemonstrates data taken of a voltage threshold distribution from a SSD subject to 10 years of data retention stress and subject to 6,000 program/erase cycles. Reading this page with default read voltage thresholds provides several errors both in the lower and upper pages, as lobes435and436shift past the delineated thresholds. This scenario is again similar to that described inFIG.4E, with a high magnitude of | P0-P1|. The errors demonstrated inFIG.4Jmay result in offset values of magnitude ‘2’.

FIG.6illustrates an embodiment of a SSD100in which the codewords based on which ECC statistics are computed arrive sequentially to the ECC module116from NAND devices140from different blocks and dies, rather than sequentially from the same block, page-by-page in order. This may occur in cases in which the controller110is processing many read commands issued from a host (not illustrated) in parallel.

In the embodiment ofFIG.6, controller110in which ECC module116is stored, is, via NAND interface130, in communication with three NAND devices140: NAND device0, NAND device1, and NAND device2. The controller110may process read commands to each NAND device in parallel. As a consequence, as shown along the time axis at the bottom ofFIG.6, the first codeword631to arrive at ECC module116is based on data read from the upper page of block A of NAND device0. Codeword631is followed by codeword632(upper page of block B of NAND device0),633(lower page of block C of NAND device1), and634(upper page of block E of NAND device2). It is not until codeword635(lower page of block A of NAND device0) arrives at ECC module116that ECC module can compute statistics for a complete block of any of NAND devices640. For this reason, it is desirable to allow the ECC module to track statistics of several MLC NAND blocks at once. This allows for the thresholds of any relevant block to be continually tracked and updated in accordance with any of the embodiments described herein.

FIG.7describes an embodiment of an SSD100in which ECC module116tracks statistics for each of NAND device0, NAND device1, and NAND device2. In particular, statistics718-0reflect the erroneous reads for both the upper and lower pages of blocks in NAND device0. Statistics718-1reflect the erroneous reads for both the upper and lower pages of blocks in NAND device1. Statistics718-2reflect the erroneous reads for both the upper and lower pages of blocks in NAND device2. By maintaining statistics for several NAND devices as shown inFIG.7, the read thresholds for the blocks of each device can be tracked and updated with time in order to prevent burdensome read retry flows from being invoked and to improve system efficiency.

FIG.8illustrates a graph of BER versus time for cases in which a controller of an SSD reads data using default read thresholds (top line) and in which a controller of an SSD reads data using read thresholds that are tracked and adjusted over time in accordance with the embodiments described herein (bottom lines).FIG.8illustrates a case in which the SSDs are subject to data retention stress. Each circle inFIG.8represents an issued read command. Horizontal line802represents a value of the BER which, if calculated for a codeword read from a NAND device in response to a read command, results in a hard decode failure event. Horizontal line804represents a threshold BER which, if encountered, triggers a readjustment of the read voltage threshold in accordance with any one of the embodiments described herein. The threshold804may be selected in certain embodiments based on the configuration of the SSD system and the stress to which it is expected to be subject. Subsequent read commands issued with the updated threshold have lower BERs and, consequently, avoid hard decode failure events.

Prior to time t1inFIG.8, read commands are issued and corresponding BERs are calculated according to any of the embodiments described herein. At time t1inFIG.8, the read command returns codeword having a corresponding BER, as determined by ECC, that lies on the threshold defined by line804. A system programmed with default read voltage thresholds makes no adjustment to its read voltage thresholds in response to encountering the threshold BER of line804. Such a system issues a subsequent read command after time t1that returns an even larger BER, as shown by the top line inFIG.8. On the other hand, a system configured to implement the tracking and updating mechanisms as described by the embodiments herein adjusts its read voltage threshold in response to encountering the BER of threshold804(bottom line). The next read commands issued by such a system uses this adjusted voltage threshold and, consequently, return codewords with corresponding BERs that lie below threshold804.

At time t2, another read command is issued. The BER of the default read voltage threshold system (top line) continues to increase and approaches line802, corresponding to the BER that yields a hard decode failure event. The BER of the system using updated read voltage thresholds (bottom line) again exceeds the BER threshold defined by line804. The system using updated thresholds once more adjusts the read voltage threshold in response to having encountered the BER defined by threshold804, and uses this threshold for subsequent reads until the threshold804is again encountered.

At time t3, another read command is issued. The resultant BER is, for the system using default read voltage thresholds (top line), sufficiently large so as to trigger a hard decode failure event. Subsequently, the system using the default read voltage thresholds issues a read retry flow, resulting in a QoS penalty. On the other hand, the system using updated read voltage thresholds (bottom line), has adjusted its read voltage threshold so that the read command issued at time t3returns a codeword having a corresponding BER, as determined by ECC, that lies below the threshold804. It is thus seen that by adjusting the read threshold voltage in accordance with the embodiments described herein, the system ofFIG.8using updated read voltage thresholds continues to be able to issue read commands without encountering a BER corresponding to a hard decode failure event.

FIG.9illustrates a flowchart describing a method implemented by a controller of an SSD in accordance with the embodiments described herein. In certain embodiments, the controller of the SSD is in communication with a plurality of nonvolatile memory devices, each comprising a multi-level memory cell, each such memory cell comprising a plurality of blocks.

InFIG.9, at step902, a controller reads, from a first block of a plurality of blocks, data corresponding to a read command received from a host. In step904, the controller subsequently determines a bit error rate for the first block based on the data read in response to the read command. In step906, the controller updates the read voltage threshold for the first block when the bit error rate for the first block exceeds a first error threshold. The controller may update the read voltage threshold by calculating an offset to add to a currently stored read voltage threshold, in accordance with exemplary equation 3 and a corresponding description provided above. The updated read voltage threshold is stored within the codebook in the controller in place of the currently stored read voltage threshold, and is used for subsequent read operations from the block in order to reduce the BER of subsequent reads.

In the foregoing, it should be noted that the term “roughly” indicates a set of values within +20% of each other. Other objects, advantages and embodiments of the various aspects of the present invention will be apparent to those who are skilled in the field of the invention and are within the scope of the description and the accompanying drawings. For example, but without limitation, structural or functional elements might be rearranged consistent with the present invention. Similarly, principles according to the present invention could be applied to other examples, which, even if not specifically described here in detail, would nevertheless be within the scope of the present invention.