Patent ID: 12206044

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form part of the disclosure, and in which specific exemplary aspects are illustrated for purposes of illustration. In this context, directional terminology such as “top”, “bottom”, “front”, “back”, “over”, “on”, “in front of”, “behind”, “leading”, “trailing”, etc. refers to the orientation of the figures just described. Since the components of the exemplary aspects may be positioned in different orientations, the directional terminology is only used for explanation and is not restrictive in any way.

The description of the exemplary aspects is not restrictive, since also other exemplary aspects exist and structural or logical changes may be made without deviating from the scope defined by the claims. In particular, elements of exemplary aspects described in the following text may be combined with elements of other exemplary aspects described, unless the context indicates otherwise.

The terms “wafer” and “semiconductor substrate” used in the following description may include any semiconductor-based structure that includes a semiconductor surface. The wafer and structure are to be understood to include doped and undoped semiconductors, epitaxial semiconductor layers, possibly supported by a base, and further semiconductor structures. For example, a layer made of a first semiconductor material may be grown on a growth substrate made of a second semiconductor material or of an insulating material, for example, sapphire. Depending on the intended use, the semiconductor may be based on a direct or an indirect semiconductor material. Examples of semiconductor materials particularly suited for generating electromagnetic radiation may include, in particular, nitride semiconductor compounds which may, for example, generate ultraviolet, blue or longer-wave light such as GaN, InGaN, AlN, AlGaN, AlGaInN, phosphide semiconductor compounds, which may, for example, generate green or longer-wave light such as GaAsP, AlGaInP, GaP, AlGaP, as well as other semiconductor materials such as AlGaAs, SiC, ZnSe, GaAs, ZnO, Ga2O3, diamond, hexagonal BN, and combinations of the materials mentioned. The stoichiometric ratio of the ternary compounds may vary. Further examples of semiconductor materials may include silicon, silicon germanium, and germanium. In the context of the present description, the term “semiconductor” also includes organic semiconductor materials.

The term “substrate” generally includes insulating, conductive or semiconductor substrates.

The terms “lateral” and “horizontal”, as used in this description, are intended to describe an orientation or alignment which runs essentially parallel to a first surface of a substrate or semiconductor body. This may, for example, be the surface of a wafer or a die or a chip.

The horizontal direction may, for example, lie in a plane perpendicular to a direction of growth when layers are grown on.

The term “vertical”, as used in this description, is intended to describe an orientation which is essentially perpendicular to the first surface of the substrate or semiconductor body.

The vertical direction may, for example, correspond to a direction of growth when layers are grown on.

To the extent that the terms “have”, “contain”, “comprise”, “include” and the like are used herein, they are open-ended terms that indicate the presence of said elements or features, but do not rule out the presence of other elements or features. The indefinite articles and the definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

In the context of this description, the term “electrically connected” means a low-ohmic electrical connection between the connected elements. The electrically connected elements need not necessarily be directly connected to one another. Additional elements may be arranged between electrically connected elements. The term “electrically connected” also includes tunnel contacts between the connected elements.

In the context of the present description, layers are, in particular, described which include a stress, for example, a tensile or compressive stress. In general, stress may be positive or negative, i.e. a tensile or compressive stress. Within the scope of the present description, stress denotes a stress that leads to a deformation of a suitable substrate material, for example, a test wafer, if a corresponding layer is applied to the substrate material. In the case of a tensile stress, the substrate material with the applied layer may take on a bowl-like or concave shape. In the case of a compressive stress, the substrate material with the applied layer may take on a convex shape.

In the context of the present description, the term “defined stress” denotes a stress that is intentionally introduced and the absolute value of which is greater than a predetermined limit value. For example, a defined stress may be purposefully set by setting deposition parameters.

For example, the stress may be measured by measuring the wafer deflection on a test wafer. At a pressure in a range from −25 MPa to +25 MPa, the wafer may be free of stress. If the stress is greater than 25 MPa, one speaks of a tensile stress, and if the stress is less than −25 MPa, one speaks of a compressive stress. Correspondingly, a stress compensation layer with a tensile stress on a test wafer may lead to a stress of more than 25 MPa. A stress compensation layer with a compressive stress may lead to a stress of less than −25 MPa on a test wafer. A stress-relieving layer may lead to a stress between −25 MPa and +25 MPa on a test wafer.

The present invention may be based on the object of providing an improved semiconductor device, as well as an improved method for manufacturing a semiconductor device.

According to the present invention, the object may be achieved by the subject matter or the method of the independent claims.

FIG.1Aillustrates a cross-sectional view through portions of a semiconductor device10. A conductive layer130may be arranged over a semiconductor body100. The conductive layer may, for example, be a metallic layer, for example, a layer that may include Ni, Zn, Al, Ti, W or other metals that are typically used for metallizations in semiconductor devices. The semiconductor body100,125may, for example, be any semiconductor body, for example, a semiconductor substrate with semiconductor layers deposited or applied thereon. The layers do not necessarily include monocrystalline, they may also be amorphous or polycrystalline. The semiconductor body100,125may also include semiconductor layers without a semiconductor substrate or another substrate. Further non-semiconductor layers may be included in the semiconductor body, for example, insulating or conductive layers.

The semiconductor body100may, in particular, be a semiconductor chip125, in which special functional components such as active or passive components, electronic or optoelectronic devices may be included. Examples include, amongst others, switching devices, power semiconductor devices, light-receiving devices, for example, sensors or solar cells, and light-emitting devices such as LEDs or lasers.

The conductive layer may be formed over a second main surface120of the semiconductor body100,125and, for example, be in direct contact with the second main surface. In accordance with further aspects, further intermediate layers may also be arranged between the second main surface of the semiconductor body and the conductive layer. An insulating layer150adjoins the conductive layer130. The insulating layer may, in particular, form part of a passivation layer or of a passivation layer stack. In addition to its insulating property, such a passivation layer serves as a diffusion barrier against gases, for example, corrosive gases such as water vapor. Examples of the insulating layer include silicon nitride, aluminum oxide, niobium oxide and silicon oxynitride. For example, the insulating layer may be chemically inert and may cause the passivation layer to adhere to the conductive layer. For example, the insulating layer may include a tensile stress. This may, for example, be the result of the manufacturing process of the insulating layer over the conductive layer.

A first stress compensation layer170may be arranged directly adjacent to a first main surface160of the insulating layer150. The first stress compensation layer170may include a defined first stress. For example, the first stress compensation layer170may be a silicon oxide layer. For example, the silicon oxide layer may be TEOS-based, i.e. grown on by a deposition process, for example, a PECVD process (“plasma enhanced chemical vapor deposition”) using TEOS (tetraethyl orthosilicate).

The first stress may, for example, include a compressive stress. For example, a compressive stress in the first stress compensation layer170may compensate for a tensile stress that prevails in an uncontrolled manner in the insulating layer150as a result of the manufacture.

In some aspects, the designation “over” may refer, in connection with applied layers, to a distance from a reference layer. If, for example, a stress compensation layer stack is described, then the feature that a first layer is arranged “over” a second layer may mean that the first layer is at a greater distance from the conductive layer130of the semiconductor device than the second layer. Accordingly, the term “over” may not be appropriate to describe a deposition sequence.

For example, according to aspects, the insulating layer150and the first stress compensation layer170may be arranged between the semiconductor body100,125and the conductive layer130.

FIG.1Billustrates a cross section through a portion of a semiconductor device according to further aspects. In this figure, deviating from the semiconductor device inFIG.1A, the first stress in the first stress compensation layer170may include a tensile stress. Furthermore, the semiconductor device10or the stress compensation layer stack165may additionally include a second stress compensation layer175, which may be arranged over the first stress compensation layer170.

According to aspects, the second stress compensation layer175may be pressure-stressed. The stress in the second stress compensation layer175may thus be opposite to the stress in the first stress compensation layer170. The second stress compensation layer175may directly adjoin the first stress compensation layer170. According to further aspects, a first stress-relieving layer180may be arranged between the first and the second stress compensation layers170,175. The stress-relieving layer may be a layer in which an absolute value of stress is less than a predetermined limit value. For example, this limit value may be 25 MPa. The compensation layer stack may further include a second stress-relieving layer185, which may be arranged over the second stress compensation layer175. The presence of the stress-relieving layer180between the first and the second stress compensation layers170,175may enable the stability of the compensation layer stack165to be increased further. Due to the fact that the first stress compensation layer170may include the same type of stress as the insulating layer150, mechanical and thermal stresses that occur may be compensated for particularly gently, so that the combination of compensation layer stack and insulating layer may be stable and the semiconductor device may therefore be particularly reliable.

According to the aspects, the stress compensation layer and, if applicable, the stress-relieving layers may each include silicon oxide or include silicon oxide, for example, silicon oxide which is TEOS-based. Further examples of materials may include silicon nitride, aluminum oxide or zirconium oxide. For example, aluminum oxide or zirconium oxide may be applied using ALD processes. The stress compensation layers may include a defined stress. The stress compensation layers and stress-relieving layers may form a stress compensation layer stack165. The combination of stress compensation layer stack165and insulating layer150together may form a passivation layer stack155which may be suitable for mechanically, electrically and chemically protecting the underlying semiconductor device or the adjacent conductive layer. For example, the passivation layer stack155may form a diffusion barrier against corrosive gases such as water vapor.

FIG.1Cillustrates a cross-sectional view of a portion of a semiconductor device according to further aspects. In addition to the layers illustrated inFIG.1B, the stress compensation layer stack165may further include a third stress compensation layer177, which may be arranged over the second stress-relieving layer185. The third stress compensation layer177may include, for example, a stress with the same sign as the second stress compensation layer175. The third stress compensation layer may be pressure-stressed. Furthermore, the stress compensation layer stack165may additionally include a stress-relieving layer187, which may be arranged over the third stress compensation layer177.

FIG.1Dillustrates a portion of a semiconductor device according to further aspects. In this figure, deviating from the semiconductor device inFIG.1C, the stress in the second stress compensation layer175may include a tensile stress.

FIG.1Eillustrates a portion of a semiconductor device according to further aspects. In this figure, deviating from the aspects illustrated inFIG.1A, the insulating layer150may be omitted, and the first stress compensation layer170may directly adjoin the conductive layer130. The other components of the device may be as described with reference toFIG.1A. For example, the first stress compensation layer170may include the same type of stress as the adjacent conductive layer. If the conductive layer130is pressure-stressed, then also the first stress compensation layer170may be pressure-stressed. If the conductive layer130is tension-stressed, then also the first stress compensation layer170may be tension-stressed. According to further aspects, further stress compensation layers and, if applicable, stress-relieving layers, as described with reference toFIGS.1B to1D, may be arranged over the first stress compensation layer170.

In the described aspects, a total layer thickness of the stress compensation layer may be slightly more than 500 nm, for example, 500 to 1000 nm. A layer thickness of the individual layers may be approximately 120 to 200 nm, for example, 150 to 180 nm. The insulating layer150may, for example, include a layer thickness of more than 200 nm, for example, more than 300 nm, for example, 300 to 400 nm. For example, a layer thickness of the insulating layer may be less than 1000 nm.

Overall, it may be favorable to arrange a likewise tension-stressed first stress compensation layer170adjacent to a tension-stressed insulating layer150. In this way, the pressure within the stress compensation layer stack165may adapt to the tensile stress in the adjacent insulating layer150. Furthermore, when the stress-relieving layers180,185,187are used, a greater stability of the applied layer stack may be achieved and thus the reliability of the semiconductor device may be increased.

As a result of the differently stressed layers of the stress compensation layer stack165, the passivation layer stack155may compensate for thermal and mechanical stresses with different signs (expansion, contraction). Such thermal and mechanical stresses may, in particular, occur if, for example, soldering processes are carried out on the semiconductor device. More precisely, the increase in temperature that coincides with a soldering process may lead to the creation of stresses within the semiconductor device. Due to the fact that the stress compensation layer stack is structured in the manner described, the stress on the chip may be reduced, as a result of which the reliability of the semiconductor device may be improved. The robustness against mechanical stresses may be increased in a similar way.

For example, a semiconductor device10with the stress compensation layer stack165described, as it is, for example, illustrated inFIGS.1A to1D, may further include a carrier element205. The carrier element may be applied to one side of an insulating layer stack221,226of the semiconductor chip. The insulating layer stack221,226may include the stress compensation layer stack165.

FIG.2Aillustrates a schematic cross-sectional view of a semiconductor chip125with a carrier element205applied. The semiconductor device illustrated inFIG.2Amay include a semiconductor chip, for example, with a semiconductor substrate230. Various components of the semiconductor device, for example, conductive lines, doped areas, active, passive components, resistance elements, transistors, etc., may be formed within the semiconductor chip125. The semiconductor chip125may include, for example, a first contact pad220, which may be connected to a first component232of the semiconductor chip125via a contact material228. The first contact pad220may be connected to a first contact area206of the carrier element205. In addition, the semiconductor chip125may include a second contact pad225which, for example, may be connected to a second contact area207of a carrier element205via a contact material229. The second contact pad225may be, for example, connected to a second component of the semiconductor chip125.

For example, a first insulating layer stack221may be arranged between the semiconductor substrate230and the first contact pad220. The first insulating layer stack221may include an insulating layer150, as discussed above, as well as the stress compensation layer stack165. For example, the first insulating layer stack221may cause passivation of the semiconductor substrate with the components arranged therein.

Furthermore, a second insulating layer stack226may be arranged between the second contact pad225and the carrier element205. The described compensation layer stack165, which are described with reference toFIGS.1A to1Dand forms part of the insulating layer stack221, may therefore be arranged both between the semiconductor substrate and the metallic layer. According to further aspects, the described compensation layer stack165may also be arranged between the metallic layer and an adjacent carrier element.

The carrier element205may, for example, likewise be a semiconductor substrate, for example, with semiconductor devices arranged therein. According to further aspects, however, it may also include a printed circuit board onto which the semiconductor substrate230with the components included therein may be soldered. If the semiconductor substrate230with the components formed therein is brought into contact with the carrier element205and subsequently heated, a strong thermal and associated mechanical stress may occur within the semiconductor device. Due to the fact that the semiconductor device10may include stress compensation layers as described, these stresses may be compensated for.

The semiconductor device10illustrated inFIG.2Amay include any semiconductor device which, for example, represents a switching device, for example, for logic applications or an optoelectronic device, for example, a solar cell. For example, the semiconductor device10may not include an outer housing, but rather it may be designed in such a manner that it is soldered directly onto the carrier element205.

FIG.2Billustrates a schematic cross-sectional view of a further aspect of a semiconductor device which may be designed as an optoelectronic semiconductor device15. The optoelectronic semiconductor device15may include, for example, a transparent insulating substrate200which may be optional and may be omitted depending on the design. The substrate200may, for example, include a sapphire substrate. A first semiconductor layer212, for example, of a first conductivity type, for example, n-type, may be arranged over the substrate200. A second semiconductor layer213, for example, of a second conductivity type, for example, p-type, may be arranged over the first semiconductor layer212. For example, an active area214may be arranged between the first and second semiconductor layers212,213. The active area214may, for example, include a pn junction, a double heterostructure, a single quantum well (SQW) structure or a multi quantum well (MQW) structure for generating radiation. In this process, the term “quantum well structure” may include no meaning with regard to the dimensionality of the quantization. Thus, it may include, among other things, quantum wells, quantum wires and quantum dots, as well as any combination of these layers.

Electromagnetic radiation20emitted by the semiconductor device15may be output, for example, via a first main surface210of the substrate200or of the first semiconductor layer212. The optoelectronic semiconductor device20may thus represents a flip-chip device within which contacts for contacting the semiconductor layers may be arranged on a side of the semiconductor stack that faces away from the light emission surface210. Part of a metallic layer may be arranged adjacent to the second semiconductor layer213and may form a second contact pad225. Part of a further metallic layer may be arranged over an insulating layer stack221and may be electro-conductively connected to the first semiconductor layer212via an electrical contact material218. For example, the first contact pad220may be connected to the first semiconductor layer212via a contact element218. The first contact element218may be arranged within a contact opening219and may be isolated from the second semiconductor layer213via a side wall insulation217and the first insulating layer stack221.

The optoelectronic semiconductor device15may further include a carrier element205, for example, a printed circuit board or a semiconductor chip with contact areas207,206arranged therein.

A second insulating layer stack226may be arranged over an exposed surface of the second contact pad225. The first and the second insulating layer stacks221,226may each include an insulating layer150, as discussed above, and the stress compensation layer stack165described above. The second insulating layer stack may also be omitted. When applying the semiconductor chip125to the carrier element205and subsequently heating it to carry out a connecting or soldering process, high temperatures may occur, which may lead to a thermal and mechanical stress on the optoelectronic semiconductor device15. Due to the fact that the optoelectronic semiconductor device may include an insulating layer stack221,226with the stress compensation layer stack165described, the thermal and mechanical stresses that occur may be efficiently compensated for. For example, the insulating layer150may be formed within the insulating layer stack221adjacent to the first contact pad220. In a corresponding manner, the insulating layer150, which may be in contact with the second contact pad225, may be formed within the second insulating layer stack226.

FIGS.2C to2Eillustrate cross-sectional views through further examples of optoelectronic semiconductor devices15, within each of which the substrate200may be arranged on a side of the optoelectronic semiconductor devices15that faces away from a light emission surface or light incidence surface. The light emission surface or light incidence surface may correspond to a first main surface105of the optoelectronic semiconductor device15.

The optoelectronic semiconductor device illustrated inFIG.2Cmay include a first semiconductor layer212of a first conductivity type, for example, n- or p-type, a second semiconductor layer213of a second conductivity type, for example, p- or n-type, and, if applicable, an active area214as described above. The active area214may be arranged between the first semiconductor layer212and the second semiconductor layer213. A converter215may, for example, be arranged over the second semiconductor layer213. A second contact pad225formed of electrically conductive material may be electro-conductively connected to the second semiconductor layer213. For example, the second contact pad225may be arranged on a side of the second semiconductor layer213that faces away from the first semiconductor layer212. The second contact pad may be arranged in the area of the first main surface105of the optoelectronic semiconductor device. A first contact pad220made of electrically conductive material may be electrically connected to the first semiconductor layer212and may be arranged on a side of the first semiconductor layer212that faces away from the second semiconductor layer213. The layer stack of the first and second semiconductor layers may, for example, be arranged over a substrate200, which, for example, may be constructed from an insulating material, a conductive material or a semiconductor material. The substrate200may, for example, be mounted on a carrier element205. For example, one or more conductive lines208may be arranged within or over the carrier element205. The conductive lines208may be made of an electrically conductive material.

According to aspects, a first insulating layer stack221may be arranged adjacent to the first contact pad220. For example, it may be arranged between the first contact pad220and the substrate200. For example, the first insulating layer stack221may approximately include a similar size to the first contact pad220and may not extend over the entire lateral extension of the substrate. According to further aspects, it may extend over the entire lateral extension of the substrate200.

Furthermore, a second insulating layer stack226may be arranged between the substrate200and the carrier element205. For example, the second insulating layer stack226may adjoin, at least in sections, the conductive line226.

The first and the second insulating layer stacks221,226may each include an insulating layer150, as discussed above, and the stress compensation layer stack165described above.

FIG.2Dillustrates a schematic cross-sectional view of an optoelectronic semiconductor device15according to further aspects. Many components of the optoelectronic semiconductor device15illustrated inFIG.2Dmay correspond to those illustrated inFIG.2C. Deviating fromFIG.2C, the substrate200may be insulating. The conductive line208may be connected to the first semiconductor layer212via a contact element218. A first insulation layer stack221, as described above, may be arranged between the conductive line208and the substrate200. A second insulating layer stack226may be arranged between the substrate200and the first semiconductor layer212. The first and the second insulating layer stacks221,226may each include an insulating layer150, as discussed above, and the stress compensation layer stack165described above.

FIG.2Eillustrates a schematic cross-sectional view of an optoelectronic semiconductor device15according to further aspects. Many components of the optoelectronic semiconductor device15illustrated inFIG.2Emay correspond to those illustrated inFIGS.2C and2D. Deviating fromFIG.2C, the substrate200may be insulating. Furthermore, the second contact pad225may be arranged on one side of the first semiconductor layer212. The contact pad225may be, for example, connected to the second semiconductor layer213by a contact element224, which may extend through the first semiconductor layer212and the active area214. The contact element224may be isolated from the first semiconductor layer212and the active area214by a sidewall insulation217. The sidewall insulation217may, for example, be implemented by an insulating layer stack. For example, the first contact pad may be arranged on a side of the substrate200that faces away from the first semiconductor layer212. Furthermore, a second insulating layer stack226may be arranged between the second contact pad225and the substrate200. The first contact pad220may be connected to the first semiconductor layer212via a contact element218. The contact element218may extend through the substrate200. For example, the first contact pad220may adjoin the conductive line208. According to aspects, a first insulating layer stack221may be arranged on a side of the substrate200which may be adjacent to the carrier element205.

The first and the second insulating layer stacks221,226and, if applicable, the insulating layer stack representing the sidewall insulation217may each include an insulating layer150as discussed above, as well as the stress compensation layer stack165described above.

FIG.3Aillustrates a schematic cross-sectional view of an optoelectronic device15, which represents a flip-chip LED chip. A second main surface302of a transparent substrate300may be, for example, roughened in order to increase the light extraction efficiency of the optoelectronic semiconductor device. A first main surface301of the transparent substrate300may serve as a light emission surface of the optoelectronic semiconductor device. A second semiconductor layer307, for example, of the second conductivity type, for example, n-type, may be arranged over the second main surface302of the substrate300. A first semiconductor layer305of a first conductivity type, for example, p-type, may be arranged over the second semiconductor layer307. An active area308may be arranged between the first and second semiconductor layers305,307. The first semiconductor layer305may be electrically connected to a first contact pad312via the mirror layer310and a first metal layer311. The mirror layer310may, for example, include silver. The first metal layer311may be formed from a common metal for contacting the first semiconductor layer305; examples may include Au, Ti, Pt or Ni. A material of the first contact pad312may, for example, include Ti, Cr, Al, Mo, Ni, W, AuSn, Sn, Cu and Pt.

The second semiconductor layer307may be connected to a second contact pad321via a second metal layer320. The second metal layer320may be arranged within a contact opening319formed within the first semiconductor layer305. An electrically insulating material may be arranged between the second metal layer320and the mirror layer310, as well as the first metal layer311. For example, the insulating material may include an insulating layer316and a stress compensation layer stack318. For example, the insulating layer316may be structured analogously to the insulating layer150. The insulating layer316may adjoin both the first and the second main surfaces of the second metal layer320. According to aspects, however, the insulating layer316may also be arranged on only one side of the second metal layer320. In addition, the stress compensation layer stack318may adjoin the insulating layer316. The stress compensation layer stack318may be formed similarly to that discussed with reference toFIGS.1A to1D.

According to further aspects, a further insulating layer314may be arranged between the first metal layer and the stress compensation layer stack318. For example, the further insulating layer314may be constructed from Al2O3. Parts of the insulating layer314may also be formed adjacent to the first metal layer311at further sites.

Due to the fact that the insulating material, which may isolate the p-contact from the n-contact, may include the stress compensation layer stack318, a thermal and mechanical stress that, for example, may occur if the optoelectronic semiconductor device15is applied to a suitable carrier element, and may be effectively compensated for. As a result, the metal layer may be reliably isolated and protected, and the reliability of the optoelectronic semiconductor device may be increased.

FIG.3Billustrates an optoelectronic semiconductor device15according to further aspects. The optoelectronic semiconductor device15may be implemented, for example, as a semiconductor laser. The semiconductor laser may include, for example, a first semiconductor layer305of a first conductivity type, for example, p-type, and a second semiconductor layer307of a second conductivity type, for example, n-type. An active area308may be arranged between the first and second semiconductor layers305,307. The first and the second semiconductor layers305,307may each act as waveguide layers. In addition, a suitable first cladding layer327of the first conductivity type may be arranged adjacent to the first semiconductor layer305. Furthermore, a second cladding layer329of a second conductivity type may be arranged adjacent to the second semiconductor layer307. The second cladding layer329may be arranged over a substrate325. The substrate325may, for example, include a semiconductor substrate, for example, made of GaN. Furthermore, a conductive layer321, which may form a second contact pad, may be arranged adjacent to one side of the substrate325. Furthermore, a suitable first metal layer311may be arranged as a contact layer to the cladding layer327. A first contact pad312may be arranged adjacent to the first metal layer.

The semiconductor layer sequence may include, for example, a conventional pn junction, a double heterostructure, a single quantum well structure (SQW structures) or a multi quantum well structure (MQW structures) as the active area. In addition to the active area, the semiconductor layer sequence may include further functional layers and functional areas such as p- or n-doped charge carrier transport layers, p- or n-doped confinement, cladding or waveguide layers, barrier layers, planarization layers, buffer layers, protective layers and/or electrodes and combinations thereof. The electrodes may each include one or more metal layers with Ag, Au, Sn, Ti, Pt, Pd, Rh and/or Ni. Such structures, relating to the active area or the further functional layers and areas, may be known to a person skilled in the art, in particular, with regard to the composition, function and structure and are therefore not explained in more detail at this point.

In addition, additional layers such as buffer layers, barrier layers and/or protective layers may also be arranged perpendicular to the direction of growth of the semiconductor layer sequence, for example, around the semiconductor layer sequence, that is to say on the side faces of the semiconductor layer sequence.

The stack of the first semiconductor layer305, the first cladding layer327and the first metal layer311may be structured to form a ridge30. More precisely, the ridge30may be formed along a direction of propagation of the generated laser radiation in the horizontal direction. In particular, such a configuration of the semiconductor layer sequence, also referred to as a “ridge structure”, may be suitable, depending on its width and height and due to the ridge-shaped structure and an associated jump in the refractive index, a so-called indexing, for enabling the generation of a transverse fundamental mode in the active area. The ridge may, in particular, extend from the radiation outcoupling surface to the side face of the semiconductor layer sequence opposite the radiation outcoupling surface. The radiation outcoupling surface may run parallel to the cross section illustrated.

According to aspects, an insulating material may be arranged between the first contact pad312and the semiconductor layers of the semiconductor laser. For example, the insulating material may include an insulating layer316and a stress compensation layer stack318, which may be formed as discussed with reference toFIGS.1A to1D. The presence of the stress compensation layer stack318between the first contact pad312and the semiconductor material may effectively compensate for thermal and mechanical stress, such as occurs, for example, when the first contact pad312is soldered onto a suitable carrier element.

In the semiconductor device illustrated, an effect may additionally occur that the effective refractive index of the adjacent semiconductor material may be modified by the stress compensation layer stack due to the photoelastic effect. For example, an anti-guiding effect caused by stress may be compensated for. As a result, the indexing of the laser mode in the semiconductor laser may be improved.

FIG.4Aillustrates a flowchart of a method according to aspects

A method for manufacturing a semiconductor device may include forming (S100) a conductive layer over a semiconductor body, forming (S110) an insulating layer adjacent to the conductive layer, and forming (S120) a first stress compensation layer, which may include a defined first stress, adjacent to the insulating layer.

According to further aspects, the method may further include forming (S130) a first stress-relieving layer adjacent to the first stress compensation layer. The method may, in addition, include forming (S140) a second stress compensation layer with a defined second stress adjacent to the first stress-relieving layer. The method may further include forming (S150) a second stress-relief layer adjacent to the second stress compensation layer. For example, the defined first stress may include a tensile stress. The defined second stress may include a compressive stress. An absolute value of the stress in the first and second stress-relieving layers may, in each case, be less than a predetermined limit value.

FIG.4Billustrates a flowchart of a method according to aspects.

A method for manufacturing a semiconductor device may include forming (S100) a conductive layer over a semiconductor body and forming (S120) a first stress compensation layer, which may include a defined first stress, adjacent to the conductive layer.

According to further aspects, the method may further include forming (S130) a first stress-relieving layer adjacent to the first stress compensation layer. The method may, in addition, include forming (S140) a second stress compensation layer with a defined second stress adjacent to the first stress-relieving layer. The method may further include forming (S150) a second stress-relief layer adjacent to the second stress compensation layer. For example, the defined first stress may include a tensile stress. The defined second stress may include a compressive stress. An absolute value of the stress in the first and second stress-relieving layers may, in each case, be less than a predetermined limit value.

In the described method, the sequence for forming the conductive layer, the insulating layer and the first stress compensation layer may, according to aspects, vary depending on the structure of the layer as long as the layers formed adjoin the corresponding layers. For example, the first stress compensation layer may initially be formed over a semiconductor body. Subsequently, the insulating layer may be formed adjacent to the first stress compensation layer, and the conductive layer may be formed adjacent to the insulating layer. The effect described may be, for example, not tied to a specific sequence of the deposition processes but to adjacent layers within the layer stack produced.

In a corresponding manner, the sequence of the further process may be given as an example and may be arbitrary.

For example, the stress compensation layers and stress-relieving layers may be constructed from silicon oxide. According to aspects, they may be formed with a PECVD method using TEOS as the starting material.

According to aspects, the type of stress in the first stress compensation layer, i.e. whether compressive stress or tensile stress, may be selected depending on the type of stress in the adjacent conductive or insulating layer. For example, it may be selected in such a manner that the type of stress corresponds to the type of stress in the adjacent conductive or insulating layer.

For example, the stress in the stress compensation layers and the stress-relieving layers may be set by setting the deposition parameters. For example, a compressive stress may be created by increasing the RF power and the pressure during the deposition. A tensile stress may be created by decreasing the pressure during the deposition and decreasing the RF power. In particular, when using a PECVD process for deposition, a stable stress may be achieved due to the high temperature that is present in this process (approx. 300° C.)

Although specific aspects are been illustrated and described herein, persons skilled in the art will recognize that the specific aspects illustrated and described may be replaced by a multitude of alternative and/or equivalent aspects without departing from the scope of the invention. Aspects may cover any adaptations or variations of the specific aspects discussed herein. Therefore, the aspects may be limited only by the claims and their equivalents.

LIST OF REFERENCES

10Semiconductor device15Optoelectronic semiconductor device20Electromagnetic radiation100Semiconductor body105First main surface of the optoelectronic semiconductor device110First main surface of the semiconductor body120Second main surface of the semiconductor body125Semiconductor chip130Conductive layer140First main surface of the conductive layer150Insulating layer155Passivation layer stack160First main surface of the insulating layer165Stress compensation layer stack170First stress compensation layer175Second stress compensation layer177Third stress compensation layer180First stress-relieving layer185Second stress-relieving layer187Third stress-relieving layer200Substrate205Carrier element206First contact area207Second contact area208Conductive line210First main surface of the optoelectronic semiconductor device212First semiconductor layer213Second semiconductor layer214Active area215Converter217Sidewall insulation218Contact element219Contact opening220First contact pad221First insulating layer stack224Contact element225Second contact pad226Second insulating layer stack228Contact material229Contact material230Semiconductor substrate232First component of the semiconductor device234Second component of the semiconductor device300Substrate301First main surface of the substrate302Second main surface of the substrate305First semiconductor layer307Second semiconductor layer308Active area310Mirror layer311First metal layer312First contact pad314Insulating layer316Insulating layer318Stress compensation layer stack319Contact opening320Second metal layer321Second contact pad325Laser substrate327First cladding layer329Second cladding layer330Ridge