Patent ID: 12204355

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings. It is noted that, the identical or same constituent elements will be assigned the identical reference characters.

Findings of Inventor

In the series regulator disclosed in Patent Document 1, it has been found that, when the switching of the operation mode occurs, the noise of the differential amplifier is superimposed on the output voltage from the reference voltage source having a high output resistance via the parasitic capacitance of the MOS transistor, and thus, a malfunction of a circuit called switching oscillation in which switching is performed between two operation modes occurs. The following embodiment is intended to prevent this malfunction.

EMBODIMENTS

FIG.1is a block diagram illustrating a configuration example of a constant voltage generator circuit2and peripheral circuits thereof according to an embodiment.

Referring toFIG.1, an input voltage Vin is inputted from a DC voltage source1to the constant voltage generator circuit2. The constant voltage generator circuit2is, for example, an LDO, generates a predetermined constant voltage Vout based on the input voltage Vin, and outputs the constant voltage to a load4via an output capacitor3.

The constant voltage generator circuit2includes a reference voltage generator circuit11, a monitoring target node12, a protection execution circuit13, a P-channel MOS transistor Q1, a current source14, three differential amplifier circuits21,22, and23, and a control circuit10that controls operations of the differential amplifier circuits21and22.

The reference voltage generator circuit11converts the input voltage Vin into a predetermined reference voltage Vref, and outputs the reference voltage. The differential amplifier circuits21and22are, for example, “differential amplifier circuits with a voltage fluctuation suppression function” having the same circuit configuration, operate at an operation frequency of, for example, 10 MHz to several 100 MHz based on enable signals EN1and EN2from the control circuit10, and operate at a higher speed and higher power consumption than those of the differential amplifier circuit23. In this case, the differential amplifier circuits21and22operate in response to the enable signals EN1and EN2each having an H level from the control circuit10, respectively, but do not operate in response to the enable signal EN1having an L level. In this case, the differential amplifier circuit21is a main differential amplifier of the constant voltage generator circuit2, generates a predetermined constant voltage, and supplies the predetermined constant voltage to the load4. In addition, the differential amplifier circuit23is a sub-differential amplifier of the constant voltage generator circuit2, generates a predetermined constant voltage, and supplies the predetermined constant voltage to the load4.

In this case, the differential amplifier circuit21configures a main differential amplifier circuit that is dominant in control during a heavy load, and the differential amplifier circuit22configures a sub-differential amplifier circuit that is not dominant in control during the heavy load. That is, the two differential amplifier circuits21and22are operating during the heavy load, the differential amplifier circuit21having a large current consumption at this time is the main differential amplifier circuit, and the differential amplifier circuit22having a current consumption smaller than that the differential amplifier circuit21configures the sub-differential amplifier circuit.

Further, the differential amplifier circuit22detects, for example, a voltage of the monitoring target node12that changes in voltage in proportion to Vout, and configures a protection circuit that executes protection processing such as limitation of an output current Iout by using, for example, a known brick wall current limitation method or a fold-back current limitation method together with the protection execution circuit13including a differential amplifier.

The output terminals of the differential amplifier circuits21and23and the protection execution circuit13are connected to a gate of the MOS transistor Q1that controls the output current Iout according to a gate voltage, and thus, the differential amplifier circuits21and23and the protection execution circuit13drive the MOS transistor Q1to control the output current Iout flowing through the MOS transistor Q1. In addition, a positive electrode of the input voltage Vin is grounded via a source and a drain of the MOS transistor Q1and the current source14.

FIG.7Ais a diagram for describing setting values of threshold currents Ith1and Ith2used in the differential amplifier circuit21ofFIG.1. In addition,FIG.7Bis a diagram for describing setting values of threshold currents Ith3and Ith4used in the differential amplifier circuit22ofFIG.1. The control circuit10operates as follows by converting the gate voltage of the MOS transistor Q1into the output current Iout or based on a current signal indicating the output current Iout from a current sensor that detects the output current Iout flowing through an output voltage terminal.

(1) As illustrated inFIG.7A, the control circuit10outputs the enable signal EN1having the L level to the differential amplifier circuit21until the output current Iout increases from current0or a current during a light load and reaches the threshold current Ith2, and outputs the enable signal EN1having the H level to the differential amplifier circuit21when Iout≥Ith2. On the other hand, the control circuit10outputs the enable signal EN1having the H level to the differential amplifier circuit21until the output current Iout decreases from a current during the heavy load and reaches the threshold current Ith1(<Ith2), and outputs the enable signal EN1having the L level to the differential amplifier circuit21when Iout≤Ith1. That is, the control circuit10controls the differential amplifier circuit21by a hysteresis operation as illustrated inFIG.7A.

(2) As illustrated inFIG.7B, the control circuit10outputs the enable signal EN2having the L level to the differential amplifier circuit22until the output current Iout increases from current0or the current during the light load and reaches the threshold current Ith4, and outputs the enable signal EN2having the H level to the differential amplifier circuit22when Iout≥Ith4. On the other hand, the control circuit outputs the enable signal EN2having the H level to the differential amplifier circuit22until the output current Iout decreases from a current during the heavy load and reaches the threshold current Ith3(<Ith4), and outputs the enable signal EN2having the L level to the differential amplifier circuit22when Iout≤Ith3. That is, the control circuit10controls the differential amplifier circuit22by a hysteresis operation as illustrated inFIG.7B.

It is noted that, a relationship among the threshold currents Ith1to Ith4is set as follows:

Ith⁢1≤Ith⁢3<Ith⁢2(1)Ith⁢2≤Ith⁢4(2)

In this case, as a “simple setting example of the threshold current”, the threshold currents may be set such that Ith1=Ith3and Ith2=Ith4.

FIG.2is a circuit diagram illustrating a detailed configuration of each of the differential amplifier circuits21and22ofFIG.1. Referring toFIG.2, each of the differential amplifier circuits21and22has the following five terminals T1to T5.(1) Inverting input terminal (INN) T1;(2) Non-inverting input terminal (INP) T2;(3) Output terminal T3;(4) Enable signal terminal T4; and(5) Reference voltage terminal T5.

Referring toFIG.2, each of the differential amplifier circuits21and22is configured to include an inverter33, a bias voltage generator circuit31, switches SW11and SW12, and a differential amplifier32. It is noted that, inFIG.2, among a plurality of MOS transistors Q11to Q34, the MOS transistors Q12, Q22, and Q32are configured of depression type, but may be configured of enhancement type, and the same applies hereinafter.

The bias voltage generator circuit31includes a P-channel MOS transistor Q11, an N-channel MOS transistor Q12, and an N-channel MOS transistor Q13, and these MOS transistors Q11, Q12and Q13are connected in series. The power source voltage Vin is applied to a source of the MOS transistor Q11, and a gate of the MOS transistor Q11is connected to a drain thereof. Gates of the MOS transistors Q12and Q13are connected to each other and connected to the terminal T5. A connection point P1between a source of the MOS transistor Q12and a drain of the MOS transistor Q13is connected to a connection point P6between a source of the MOS transistor Q22and a drain of the MOS transistor Q23in the differential amplifier32via the switch SW11. Further, a source of the MOS transistor Q13is grounded via the current source41via a connection point P2. The connection point P2is connected to a connection point P7in the differential amplifier32via the switch SW12.

The bias voltage generator circuit31having the above-described configuration converts the reference voltage Vref to be applied to the terminal T5into a predetermined bias voltage, and applies the predetermined bias voltage to the connection point P6in the differential amplifier32via the switch SW11.

The differential amplifier32ofFIG.2includes MOS transistors Q21, Q22, Q23, Q31, Q32, Q33, and Q34, switches SW1, SW2, SW3, SW13, and SW14, and current sources42and43. The MOS transistor Q21, a connection point P4, the MOS transistor Q22, the connection point P6, and the MOS transistor Q23are connected in series with each other, a source of the MOS transistor Q21is connected to the power source voltage Vin, and a source of the MOS transistor Q23is grounded via the switch SW2and the current source42. In addition, the MOS transistor Q31, a connection point P5, and the MOS transistors Q32and33are connected in series with each other, a source of the MOS transistor Q31is connected to the power source voltage Vin, and a source of the MOS transistor Q33is grounded via the switch SW2and the current source42. Further, the connection point P3at which the gates of the MOS transistors Q21and Q31are connected to each other is connected to the power source voltage Vin via the switch SW13, and is connected to the connection point P4via the switch SW1.

The gates of the MOS transistors Q32and Q33are connected to each other and are then connected to the terminal T2. The connection point P5is connected to the gate of the MOS transistor Q34, and the gate of the MOS transistor Q34is connected to the power source voltage Vin and the source of the MOS transistor Q34via the switch SW14. A drain of the MOS transistor Q34is grounded via a connection point connected to the terminal T3, the switch SW3, and the current source43.

The enable signals EN1and EN2to be inputted to the terminal T4are inputted to control terminals of the switches SW1to SW3, and inverted enable signals/EN1and/EN2to be inputted to the inverter33and to be outputted from the inverter33are inputted to control terminals of the switches SW11to SW14. When the enable signals EN1and EN2having the H level are inputted to the control terminals of the switches SW1to SW3, the switches SW1to SW3are turned on, and when the enable signals EN1and EN2each having the L level are inputted, the switches SW1to SW3are turned off. In addition, when the inverted enable signals /EN1and/EN2having the H level are inputted to the control terminals of the switches SW11to SW14, the switches SW11to SW14are turned on, and when the inverted enable signals/EN1and/EN2each having the L level are inputted, the switches SW11to SW14are turned off.

In each of the differential amplifier circuits21and22having the above-described configuration, when the enable signals EN1and EN2having the H level are inputted, the switches SW1to SW3are turned on and the switches SW11to SW14are turned off. At this time, the differential amplifier32enters an operation state in a state where the predetermined bias voltage from the bias voltage generator circuit31is not applied to the differential amplifier32. Accordingly, the differential amplifier32subtracts the inverting input voltage INN to be inputted to the inverting input terminal T1from the non-inverting input voltage INP to be inputted to the non-inverting input terminal T2, and outputs the output voltage obtained by amplifying the voltage of the subtraction result from the terminal T3. It is noted that, the terminal T3of the differential amplifier circuit21is connected to the gate of the MOS transistor Q1ofFIG.1, and the terminal T3of the differential amplifier circuit22is connected to the gate of the MOS transistor Q1via the protection execution circuit13ofFIG.1.

In addition, when the enable signals EN1and EN2each having the L level are inputted, the switches SW1to SW3are turned off and the switches SW11to SW14are turned on. At this time, the differential amplifier32enters such a non-operation state that the predetermined bias voltage from the bias voltage generator circuit31is applied to the differential amplifier32. Accordingly, the differential amplifier32does not perform the differential amplification and is in a stop state without an output from the terminal T3. However, since the predetermined bias voltage is applied, the voltage fluctuations of the connection points P6and P7are suppressed, and thus, fluctuations in the gate voltages of the MOS transistors Q22and Q23via parasitic capacitances of the MOS transistors Q22and Q23are suppressed.

That is, each of the differential amplifier circuits21and22performs the differential amplification operation during the operation, and does not perform the differential amplification operation during the non-operation. However, at this time, since the predetermined bias voltage is applied to the internal nodes (connection point P6or P7), it is possible to suppress a fluctuation in the reference voltage.

FIG.3is a timing chart illustrating stop operations of the differential amplifier circuit22and the differential amplifier circuit21for the protection execution circuit13of the constant voltage generator circuit2ofFIG.1. It is noted that,FIG.3illustrates a case of a simple setting example of the threshold current when the threshold currents are set such that Ith1=Ith3and Ith2=Ith4.

In a time interval T11ofFIG.3, since the enable signals EN1and EN2have the H level, the differential amplifier circuit21is in the operation state, the differential amplifier circuit22for the protection execution circuit13is in the operation state, and the protection circuit is operating. Subsequently, at time t1, the output current Iout decreases by changing from the heavy load to the light load, the output current Iout≤Ith3. Thus, since the enable signal EN2becomes the L level, the control circuit10stops the operation of the differential amplifier circuit22for the protection execution circuit13. In addition, the enable signal EN1has the L level, and in the differential amplifier circuit21, the differential amplifier32is in the non-operation state in a state where the bias voltage is applied to the differential amplifier32. Accordingly, the differential amplifier circuit21is in a state of not performing the differential amplification described above. However, since the predetermined bias voltage is applied, the fluctuation in the reference voltage via the parasitic capacitances of the MOS transistors Q22and Q23is suppressed. The above effect is similarly exhibited in the differential amplifier circuit22. At this time, since a change in an output voltage of a reference voltage source is small due to the effect of the bias voltage, a fluctuation in the output current Iout is also small, the differential amplifier circuit22and the differential amplifier circuit21for the protection execution circuit13do not malfunction, and the output voltage Vout does not oscillate.

As described above, each of the differential amplifier circuits21and22is configured of the “differential amplifier circuit with the voltage fluctuation suppression function” as illustrated inFIG.2. When each of the differential amplifier circuits21and22is in the stop state, since the predetermined bias voltage is applied to the differential amplifier32of each of the differential amplifier circuits21and23, the fluctuation in the reference voltage via the parasitic capacitances of the MOS transistors Q22and Q23is suppressed. At this time, since the voltage fluctuation of the output voltage Vout is small due to the effect of the bias voltage, the fluctuation in the output current Iout is also small, the differential amplifier circuits21and22and the protection execution circuit13do not malfunction, and the output voltage Vout does not oscillate. That is, the offset voltage of the differential amplifier can be set to be small by suppressing the change in the output voltage of the reference voltage source, and it is possible to prevent the malfunction in which the power source circuit continues to transition a plurality of modes while suppressing degradation of the accuracy of the output voltage Vout between the modes.

Modified Embodiments of Embodiments

In the above embodiment, a stop control circuit that stops the operation of the differential amplifier circuit22used for the protection execution circuit13when the differential amplifier circuit22for the protection execution circuit13is in the stopped state, or the bias voltage generator circuit31that fixes the bias voltage of the differential amplifier circuit22is provided. The present invention is not limited thereto, and these functional circuits may be provided only in the differential amplifier circuit21and may not be provided in the differential amplifier circuit22, or may not have a function of stopping the operation according to the output current by the enable signal EN2from the control circuit10.

In the above embodiment, the differential amplifier circuit23is configured of a normal differential amplifier circuit without any voltage fluctuation suppression function. The present invention is not limited thereto, and the differential amplifier circuit23may be configured of a differential amplifier circuit with the voltage fluctuation suppression function in a manner similar to that of each of the differential amplifier circuits21and22.

In the above embodiment, the MOS transistors Q12and Q13, the MOS transistors Q22and Q23, and the MOS transistors Q32and Q33are cascode-connected. The present invention is not limited thereto, and may be configured to include only one MOS transistor Q13, one MOS transistor Q23, and one MOS transistor Q33without any cascode connection.

Other Modified Embodiments

In the above embodiment, although the differential amplifier circuits21and22used in the constant voltage generator circuit2have been described, first, second, and third modified embodiments of the differential amplifier circuits21and22will be described below. It is noted that, although differential amplifier circuits21A,21B, and21C will be described below, these configurations may be similarly applied to the differential amplifier circuits21and22.

First Modified Embodiment

FIG.4is a block diagram illustrating a configuration example of the differential amplifier circuit21A according to the first modified embodiment. Referring toFIG.4, the same constituent elements as those ofFIG.2are denoted by the same reference characters. The differential amplifier circuit21A ofFIG.4is different from the differential amplifier circuits21and22ofFIG.2in the following points:(1) a bias voltage generator circuit31A is provided instead of the bias voltage generator circuit31; and(2) a differential amplifier32A is provided instead of the differential amplifier32.

Hereinafter, the differences will be described.

Referring toFIG.4, the bias voltage generator circuit31A is configured to include MOS transistors Q11and Q13, current sources41and44, and MOS transistors Q41and Q42. The bias voltage generator circuit31A is different from the bias voltage generator circuit31in the following points:(1) the MOS transistor Q12is removed; and(2) the current mirror circuit CM1is configured to include the MOS transistors Q41and Q42, and thus, the bias voltage corresponding to the source voltage potential of the MOS transistor Q13is generated by the current mirror circuit CM1, and the bias voltage is outputted to a connection point P7via a switch SW15.

The enable signal EN1to be inputted to the terminal T4is inputted to each of the control terminals of switches SW1to SW3, and is inputted to each of the control terminals of switches SW13to SW15via an inverter33.

In accordance with the differential amplifier circuit21A having the above-described configuration, the change in the output voltage of the reference voltage source can be suppressed, by generating the bias voltage corresponding to the source voltage potential of the MOS transistor Q13by the current mirror circuit CM1during the non-operation, and outputting the bias voltage to the connection point P7of the differential amplifier32A.

Second Modified Embodiment

FIG.5is a block diagram illustrating a configuration example of a differential amplifier circuit21B according to the second modified embodiment. Referring toFIG.5, the same constituent elements as those ofFIGS.2and4are denoted by the same reference characters. The differential amplifier circuit21B ofFIG.5is different from the differential amplifier circuit21A ofFIG.4in the following points:(1) a bias voltage generator circuit including an internal reference voltage generator circuit50and a voltage generator circuit60is provided instead of the bias voltage generator circuit31A; and(2) a differential amplifier32AA is provided instead of the differential amplifier32A, and it is noted that, the differential amplifier32AA includes a switch SW11that connects a connection point P22of the voltage generator circuit60to a connection point P6of the differential amplifier32AA, instead of the switch SW15, as compared with the differential amplifier32A.

Accordingly, the differential amplifier circuit21B is configured to include the internal reference voltage generator circuit50, the voltage generator circuit60, and the differential amplifier32AA. Hereinafter, the differences will be described.

Referring toFIG.5, the internal reference voltage generator circuit50includes a differential amplifier51, a P-channel MOS transistor Q51, and voltage-dividing resistors R1and R2, and is configured by a known reference voltage generator circuit. Accordingly, the internal reference voltage generator circuit50generates a predetermined internal reference voltage based on the reference voltage Vref to be inputted to the terminal T5, and outputs the predetermined internal reference voltage to a source of a MOS transistor Q61of the voltage generator circuit60via a connection point P21. In this case, the voltage at the connection point P21may be used as the reference voltage by being outputted to the outside of the block.

The voltage generator circuit60includes P-channel MOS transistors Q60to Q62and N-channel MOS transistors Q63and Q64. In this case, the MOS transistors Q51and Q60configures a current mirror circuit CM2. In addition, the MOS transistors Q61to Q64configures a current mirror circuit. Accordingly, the voltage generator circuit60adjusts an output impedance of a constant voltage from the internal reference voltage generator circuit50by the current mirror circuit CM2, and outputs the constant voltage to the differential amplifier32AA.

The enable signal EN1to be inputted to a terminal T4is inputted to each of the control terminals of the switches SW1to SW3, and is inputted to each of the control terminals of the switches SW11, SW13, and SW14via an inverter33.

In accordance with the differential amplifier circuit21B having the above-described configuration, the change in the output voltage of the reference voltage source can be suppressed by generating the bias voltage corresponding to the drain voltage potential of the MOS transistor Q51by the current mirror circuit CM2during the non-operation and outputting the bias voltage to the connection point P6of the differential amplifier32AA.

Third Modified Embodiment

FIG.6is a block diagram illustrating a configuration example of a differential amplifier circuit21C according to the third modified embodiment. The differential amplifier circuit21C ofFIG.6is different from the differential amplifier circuit21ofFIG.2in the following points:(1) a current generator circuit including two parallel transistor circuits70and80and a current source circuit90is provided instead of the bias voltage generator circuit31; and(2) a differential amplifier32B is provided instead of the differential amplifier32.

Hereinafter, the differences will be described.

The differential amplifier32B includes switches SW3, SW13, SW14, and SW20, MOS transistors Q21, Q31, Q32, Q33, and Q34, and a current source43. In this case, the MOS transistor Q34and the current source43configures an output amplifier circuit.

The two parallel transistor circuits70and80are connected in series between the MOS transistor Q21and the current source circuit90. In this case, the parallel transistor circuit70includes two MOS transistors Q71and Q72and a switch SW21. In addition, the parallel transistor circuit80includes two MOS transistors Q81and Q82and a switch SW23. Further, the current source circuit90includes two current sources91and92and a switch SW25. Accordingly, when the switches SW21to SW25are turned off (during the non-operation of the differential amplifier32B), a flowing current is smaller than that when the switches SW21to SW25are turned on (during the operation of the differential amplifier32B). In particular, when the differential amplifier32B is not operated, the small current is caused to flow from the current generator circuit to the internal nodes (the connection points P4, P6, and P7) of the differential amplifier32B to fix an operation voltage potential. Thus, the change in the output voltage of the reference voltage source is suppressed.

It is noted that, the number of each of the MOS transistors connected to the switches in the parallel transistor circuits70and80is not limited to one, and may be a plurality of MOS transistors.

In the above-described embodiment and first and second modified embodiments, the predetermined bias voltages are applied from the bias voltage generator circuits31and31A and the voltage generator circuit60to the internal nodes of the differential amplifiers32,32A, and32AA, respectively, during the non-operations of the differential amplifiers32,32A, and32AA. Thus, the voltage potential fluctuation of the reference voltage is suppressed by fixing operation voltage potentials of the differential amplifiers32,32A, and32AA (configuring the operation voltage potential fixing circuit). On the other hand, in the third modified embodiment, when the differential amplifier32B is not operated, a predetermined small current is caused to flow to the internal nodes (the connection points P4, P6, and P7) of the differential amplifier32B (the current generator circuit) to fix the operation voltage potential (the operation voltage potential fixing circuit is configured), and thus, the voltage potential fluctuation of the reference voltage is suppressed.

Further Modified Embodiments

In the above embodiment and modified embodiments, the switches SW1to SW25are provided. In this case, the switches SW1to SW25are configured of semiconductor switch elements made of MOS transistors, for example.

Although the differential amplifiers32,32A, and32B are used in the above embodiment and modified embodiments, the present invention is not limited thereto, and an amplifier that amplifies an input voltage may be used.

INDUSTRIAL APPLICABILITY

As mentioned above in detail, in accordance with the constant voltage generator circuit according to the present invention, it is possible to suppress the change in the output voltage of the reference voltage source caused by the noise superimposition via the coupling capacitance. As a result, the offset voltage of the differential amplifier can be set to be small, and it is possible to prevent the malfunction in which the power source circuit continues to transition between the plurality of modes while suppressing the deterioration in the accuracy of the output voltage generated as the difference in the output voltage between the modes.