Patent ID: 12262132

DETAILED DESCRIPTION

Hereinafter, some example embodiments according to the technical idea of the present inventive concepts will be explained referring to the accompanying drawings.

FIG.1is a block diagram of an image sensing device according to some example embodiments.

Referring toFIG.1, the image sensing device1may include an image sensor100and an image signal processor900.

The image sensor100may generate an image signal IMS, by sensing an image to be sensed using light. In some example embodiments, although the generated image signal IMS may be, for example, a digital signal, some example embodiments according to the technical ideas of the present inventive concepts are not limited thereto.

The image signal IMS may be provided to the image signal processor900and processed. The image signal processor900receives the image signal IMS that is output from a buffer170of the image sensor100, and may process or treat the received image signal IMS to be easily displayed.

In some example embodiments, the image signal processor900may perform digital binning on the image signal IMS that is output from the image sensor100. At this time, the image signal IMS that is output from the image sensor100may be a raw image signal from the pixel array140without analog binning, and may also be an image signal IMS on which analog binning has already been performed.

In some example embodiments, the image sensor100and the image signal processor900may be placed separately from each other as shown. For example, the image sensor100may be mounted on the first chip, the image signal processor900may be mounted on the second chip, and they may communicate with each other through a predetermined interface. However, some example embodiments are not limited thereto, and the image sensor100and the image signal processor900may be implemented as a single package, for example, an MCP (multi-chip package).

The image sensor100may include a control register block110, a timing generator120, a row driver130, a pixel array140, a readout circuit150, a ramp signal generator160, and a buffer170. The row driver130may be referred to herein interchangeably as a first row driver.

The control register block110may generally control the operation of the image sensor100. In particular, the control register block110may transmit an operating signal directly to the timing generator120, the ramp signal generator160, and the buffer170.

The timing generator120may generate a signal that serves as a reference for the operation timing of various components of the image sensor100. The operation timing reference signal generated by the timing generator120may be transferred to the row driver130, the readout circuit150, the ramp signal generator160, and the like.

The ramp signal generator160may generate and transmit the ramp signal used in the readout circuit150. For example, the readout circuit150may include a correlated double sampler (CDS), a comparator, and the like. The ramp signal generator160may generate and transmit the ramp signal used in the correlated double sampler, the comparator, and the like.

The buffer170may include, for example, a latch. The buffer170may temporarily store the image signal IMS to be provided to the outside, and may transmit the image signal IMS to an external memory or an external device.

The pixel array140may sense external images. The pixel array140may include a plurality of pixels (or unit pixels). The row driver130may selectively activate the row of the pixel array140.

The readout circuit150may sample the pixel signal provided from the pixel array140, compare it to the ramp signal, and convert the analog image signal (data) into a digital image signal (data) on the basis of the comparison results.

FIG.2is a diagram showing a conceptual layout of the image sensor ofFIG.1.

Referring toFIG.2, the image sensor100may include first and second regions S1and S2stacked in a third direction Z. The first and second regions S1and S2may extend in a first direction X and a second direction Y as shown, and blocks shown inFIG.1may be placed in the first and second regions S1and S2.

Although not shown in the drawing, a third region in which the memory is placed may be placed below the second region S2. At this time, the memory placed in the third region receives the image data from the first and second regions S1and S2, and stores or processes the image data, and transmit the image data to the first and second regions S1and S2again. At this time, the memory may include a memory element such as a DRAM (dynamic random access memory) element, a SRAM (static random access memory) element, a STT-MRAM (spin transfer torque magnetic random access memory) element, and a flash memory element. When the memory includes, for example, a DRAM element, the memory may receive and process the image data at a relatively high speed. Also, in some example embodiments, the memory may also be placed in the second region S2.

The first region S1may include a pixel array region PA and a first peripheral region PH1, and the second region S2may include a logic circuit region LC and a second peripheral region PH2. The first and second regions S1and S2may be placed to be sequentially stacked one above the other.

In the first region S1, the pixel array region PA may be a region in which the pixel array (140ofFIG.1) explained referring toFIG.1is placed. The pixel array region PA may include a plurality of unit pixels arranged in a matrix form. Each pixel may include a photo diode and a transistor. A more specific description thereof will be provided below.

The first peripheral region PH1may include a plurality of pads, and may be placed around the pixel array region PA. The plurality of pads may transmit and receive electrical signals to and from an external device or the like.

In the second region S2, the logic circuit region LC may include electronic elements including a plurality of transistors. The electronic elements included in the logic circuit region LC may be electrically connected to the pixel array region PA to provide a constant signal to each unit pixel PX of the pixel array region PA or control the output signal.

For example, the control register block110, the timing generator120, the row driver130, the readout circuit150, the ramp signal generator160, the buffer170, and the like explained referring toFIG.1may be placed in the logic circuit region LC. For example, blocks other than the pixel array140among the blocks ofFIG.1may be placed in the logic circuit region LC.

In the second region S2, the second peripheral region PH2may also be placed in the region corresponding to the first peripheral region PH1of the first region S1. However, some example embodiments are not limited thereto.

FIG.3is a diagram for explaining an image sensor according to some example embodiments.FIG.4is a diagram for explaining the pixels ofFIG.3.

Referring toFIGS.3and4, the image sensor100may include a row driver130(e.g., “first row driver”), row lines ROW1to ROWn, column lines COL1to COLn, a pixel array140, a first boosting driver200, a second boosting driver210, a plurality of boosting circuits PB, a ramp signal generator160, an analog-to-digital converter151, a buffer170and the like.

As shown, the row lines ROW1to ROWn may be connected to the row driver130and may extend in the first direction X. The row driver130may drive the pixel array140row by row. The row driver130may generate a transfer control signal TS, a reset control signal RS, a selection control signal SEL, and the like and provide them to the pixel PX of the pixel array140.

The pixel array140may include a plurality of pixels PX. Here, the pixels PX may be arranged in a lattice form along a large number of rows and columns. The pixel array140may detect light, using the plurality of pixels PX, and convert light into an electrical signal to generate an image signal.

A plurality of row lines ROW1to ROWn may extend in the first direction X. The plurality of row lines ROW1to ROWn may be sequentially arranged in the third direction Z. For example, the first row line ROW1may be spaced apart from (e.g., isolated from direct contact with) the second row line ROW2in the third direction Z. A plurality of column lines COL1to COLn may extend in the third direction Z. The plurality of column lines COL1to COLn may be sequentially arranged in the first direction X. For example, the second column line COL2may be spaced apart from (e.g., isolated from direct contact with) the first column line COL1in the first direction X. However, some example embodiments of the present inventive concepts are not limited thereto. As used in at leastFIG.3, “n” may be any positive integer. In some example embodiments, “n” may be equal to or greater than 4.

The plurality of pixels PX may be connected to the row lines ROW1to ROWn and the column lines COL1to COLn. For example, a single pixel PX may be connected to both the first row line ROW1and the first column line COL1. Further, the pixel PX may be located at an intersection part between the first row line ROW1and the first column line COL1. The plurality of pixels PX may be arranged in a lattice form accordingly. As shown inFIG.3, when “n” is equal to or greater than 4, a first pixel PX1, a second pixel PX2, a third pixel PX(n−1), and a fourth pixel PXn are connected to the first row line ROW1and are sequentially arranged in the first direction X, a first column line COL1may be connected to the first pixel PX1and may be configured to receive a first output signal from the first pixel PX1, a second column line COL2may be connected to the second pixel PX2and may be configured to receive a second output signal from the second pixel PX2, a third column line COL(n−1) may be connected to the third pixel PX(n−1) and may be configured to receive a third output signal from the third pixel PX(n−1), and a fourth column line COLn may be connected to the fourth pixel PXn and may be configured to receive a fourth output signal from the fourth pixel PXn.

Referring toFIG.4, the pixel PX may include a photoelectric conversion element (e.g., photo diode PD) that is configured to receive (e.g., absorb and/or photoelectrically convert) incident light, a transfer transistor TX, a reset transistor RX, a source follower SF, and a selection transistor SX. Here, the pixel PX may be a unit that constitutes the pixel array140or the pixel array region PA.

One end of the transfer transistor TX may be connected to the photo diode PD, and the other end may be connected to the floating diffusion region FD. The control electrode of the transfer transistor TX may receive the transfer control signal TS. Here, light incident on the image sensor100may be converted into an electric signal through a photo diode PD. The converted electrical signal may be transferred to the floating diffusion region FD through the transfer transistor TX.

One end of the reset transistor RX receives the power supply voltage VDD, and the other end may be connected to the floating diffusion region FD. The control electrode of the reset transistor RX may receive the reset control signal RS. One end of the source follower SF may receive the power supply voltage VDD, and the other end may be connected to one end of the selection transistor SX. The control electrode of the source follower SF may be connected to the floating diffusion region FD. The other end of the selection transistor SX is connected to the column lines COL1to COLn, and the control electrode may receive the selection control signal SEL.

Each of the control signals TS, RS, and SEL which control each of the transistors TX, RX, and SX may be output from the row driver130. An output signal Vout of the selection transistor SX may be supplied to the column lines COL1to COLn. The output signal Vout may correspond to an analog signal. That is, the output signal Vout that is output from the pixel PX may be converted into a digital signal through the readout circuit150, and may be transferred to the image signal processor900as an image signal IMS. Accordingly, a given pixel (e.g., first pixel PX1) may include a photoelectric conversion element (e.g., photodiode PD) that is configured to receive incident light and a transfer transistor TX that connects the photoelectric conversion element to a corresponding connected column line (e.g., first column line COL1for the first pixel PX1), where the transfer transistor TX of the pixel PX is configured to operate in response to a transfer control signal TS received from the row driver130. As shown inFIG.4, the given pixel PX may include a reset transistor RX which connects the voltage source VDD and the corresponding connected column line (e.g., first column line COL1for the first pixel PX1) and is configured to operate in response to the reset control signal RS received from the row driver130.

Here, the row lines ROW1to ROWn ofFIG.3may be signal lines that transfer the transfer control signal TS, the reset control signal RS, and the selection control signal SEL from the row driver130to the pixel PX. Further, the column lines COL1to COLn ofFIG.3may be signal lines that transfer the output signal Vout of the selection transistor SX.

Referring toFIG.3again, the plurality of column lines COL1to COLn may be connected to the analog-to-digital converter151. Here, the analog-to-digital converter151may also be connected to the ramp signal generator160. That is, the analog-to-digital converter151may receive the ramp signal from the ramp signal generator160, and may receive the output signal Vout from the plurality of column lines COL1to COLn. The analog-to-digital converter151may perform a CDS (correlation double sampling) operation, a counting operation, and the like to convert the output signal Vout, which is an analog signal, into a digital signal. Here, the analog-to-digital converter151may be included in the readout circuit150ofFIG.1. As shown inFIG.3, the boosting circuits PB, or a single boosting circuit PB that is connected to the column lines COL1to COLn, may be between the analog-to-digital converter151and the pixels PX (e.g., pixels PX1to PXn that are connected to the first row line ROW1). The readout circuit150including the analog-to-digital converter151may be spaced apart from (e.g., isolated from direct contact with) the pixel array140in a direction opposite to the third direction Z. WhileFIG.3illustrates multiple “ADC” analog-to-digital converters151connected to separate, respective column lines, it will be understood that the multiple “ADC” analog-to-digital converters151shown inFIG.3may collectively represent a single analog-to-digital converter151that is connected to the column lines COL1to COLn. For example, when “n” is equal to or greater than 4, the analog-to-digital converter151may be connected to the first to fourth column lines COL1to COLn, and the analog-to-digital converter151may be configured to receive first to fourth output signals from the first to fourth pixels PX1to PXn via the first to fourth column lines COL1to COLn and convert the received first to fourth output signals into digital signals. Further, a plurality of analog-to-digital converters151may be sequentially arranged along the first direction X. That is, the analog-to-digital converter151may be placed to correspond to each pixel PX.

The buffer170may be connected to a plurality of analog-to-digital converters151and/or to a single analog-to-digital converter151that is connected to the column lines COL1to COLn, and may provide a converted digital signal from the analog-to-digital converter151. The buffer170may be placed in the direction opposite to the third direction Z from the analog-to-digital converter151.

The row line RL may be placed between the pixel array140and the analog-to-digital converter151. The row line RL may extend in the first direction X. For example, the row line RL may be formed to be parallel to a plurality of row lines ROW1to ROWn. The row line RL may include a first terminal in the direction opposite to the first direction X, and a second terminal in the first direction X. That is, the row line RL may extend along the first direction X from the first terminal to the second terminal.

A plurality of boosting circuits PB may be connected to a plurality of column lines COL1to COLn. That is, the boosting circuits PB may be sequentially arranged in the first direction X. For example, the boosting circuit PB may be placed one by one to correspond to each of the column lines COL1to COLn. The boosting circuits PB may be connected to the row line RL. That is, the boosting circuit PB may be connected to both the row line RL and the column lines COL1to COLn. Further, the boosting circuit PB may be located at the intersection part between the row line RL and the column lines COL1to COLn. The boosting circuits PB may be referred to herein as a single boosting circuit PB. For example, where n≥4, boosting circuits PB may be referred to as a boosting circuit PB that is connected to the first to fourth column lines COL1to COLn, and a row line RL (also referred to herein as a second row line) may be connected to the boosting circuit PB and may extend in the first direction X. The multiple boosting circuits PB shown inFIG.3may represent multiple sub-boosting circuits of a single boosting circuit that is connected to the column lines COL1to COLn. For example, as shown inFIG.3, a single boosting circuit PB that is connected to the column lines COL1to COLn, where n≥4, may include a first sub-boosting circuit connected between the first column line and the second row line (e.g., PB1as shown inFIG.5), a second sub-boosting circuit connected between the second column line and the second row line e.g., PB2as shown inFIG.5), a third sub-boosting circuit connected between the third column line and the second row line (e.g., PB3as shown inFIG.6), and a fourth sub-boosting circuit connected between the fourth column line and the second row line (e.g., PB4as shown inFIG.6).

The first boosting driver200may be connected to the row line RL. Specifically, the first boosting driver200may be connected to the first terminal of the row line RL in the direction opposite to the first direction X. Further, the first boosting driver200may be placed apart from the plurality of boosting circuits PB in the direction opposite to the first direction X. In addition, the first boosting driver200may be connected to a plurality of boosting circuits PB through the row line RL.

The second boosting driver210may be connected to the row line RL. Specifically, the second boosting driver210may be connected to the second terminal of the row line RL (which is opposite to the first terminal of the row line RL) in the first direction X. As shown inFIG.3, the first and second boosting drivers200and210are connected to opposite ends of the row line RL. Further, the second boosting driver210may be placed to be spaced apart from (e.g., isolated from direct contact with) the plurality of boosting circuits PB in the first direction X. The second boosting driver210may be connected to the plurality of boosting circuits PB through the row line RL.

The row line RL and the plurality of boosting circuits PB may be placed between the first boosting driver200and the second boosting driver210. That is, the row driver130is placed to be spaced apart from (e.g., isolated from direct contact with) the pixel array140in the direction opposite to the first direction X, whereas the first and second boosting drivers200and210may be located on both sides of the row line RL and the plurality of boosting circuits PB. Also, the first and second boosting drivers200and210may be placed symmetrically.

The first switch SWC1may connect the row line RL and the first boosting driver200. The first switch SWC1may be placed between the row line RL and the first boosting driver200. In some example embodiments, the first switch SWC1may be in a closed state. That is, the first boosting driver200, the row line RL, and the boosting circuit PB may be connected by the closed first switch SWC1. However, some example embodiments of the present inventive concepts are not limited thereto.

The second switch SWC2may connect the row line RL and the second boosting driver210. That is, the second switch SWC2may be placed between the row line RL and the second boosting driver210. In some example embodiments, the second switch SWC2may be in the closed state. That is, the second boosting driver210, the row line RL, and the boosting circuit PB may be connected by the closed second switch SWC2. However, some example embodiments of the present inventive concepts are not limited thereto.

The first boosting driver200may control the boosting circuit PB to be turned on or off, and the boosting circuit PB may adjust the voltage of the output signal Vout that is output from the column lines COL1to COLn in response to the control of the first boosting driver200. For example, where n≥4, the boosting circuits PB may be referred to collectively as a boosting circuit PB that is configured to adjust a voltage of the first and second output signals (received from the first and second pixels PX1and PX2via the first and second column lines COL1and COL2) based on a first boosting enable signal received from the first boosting driver200. Also, the second boosting driver210may control the boosting circuits PB to be turned on or off, and the boosting circuits PB may adjust the voltage of the output signal Vout that is output from the column lines COL1to COLn in response to the control of the second boosting driver210. For example, where n≥4, the boosting circuits PB may be referred to collectively as a boosting circuit PB that is configured to adjust a voltage of the third and fourth output signals (received from the third and fourth pixels PX(n−1) and PXn via the column lines COL(n−1) and COLn) based on a first boosting enable signal received from the second boosting driver210. In some example embodiments, the boosting circuits PB may be referred to as separate boosting circuits PB that are connected to separate, respective column lines and are each configured to adjust a voltage of a separate output signal received from a separate pixel PX via the separate column line to which the separate boosting circuit PB is connected.

FIG.5is an enlarged view of a region R1ofFIG.3.FIG.6is an enlarged view of a region R2ofFIG.3.

Referring toFIG.5, in the region R1, the first boosting driver200may be connected to the first boosting circuit PB1and the second boosting circuit PB2through the row line RL. In some example embodiments, the first and second boosting circuits PB1and PB2may be considered to be part of a single booster circuit PB that is connected to column lines COL1to COLn. In some example embodiments, the first boosting circuit PB1may be referred to as a first sub-boosting circuit, of a single boosting circuit PB, that is connected between a first column line COL1and the row line RL. In some example embodiments, the second boosting circuit PB2may be referred to as a second sub-boosting circuit, of a single boosting circuit PB, that is connected between a second column line COL2and the row line RL. Here, the row line RL may include parasitic resistors R1and R2, and parasitic capacitors C1and C2. The parasitic resistors R1and R2and the parasitic capacitors C1and C2may be due to the natural characteristics of the row line RL. The parasitic resistor R1and the parasitic capacitor C1may exist between a first node N1, to which the first boosting circuit PB1and the row line RL are connected, and a third node N3to which the second boosting circuit PB2and the row line RL are connected. Further, the parasitic resistor R2and the parasitic capacitor C2may be connected to the third node N3.

A boosting enable signal VBST_ENa that is output from the first boosting driver200may be transferred by being delayed with the parasitic resistors R1and R2and the parasitic capacitors C1and C2. That is, the boosting enable signal VBST_ENa may be delayed by the RC delay. For example, a first boosting enable signal VBST_ENa1transferred to the first boosting circuit PB1may reach before a second boosting enable signal VBST_ENa2transferred to the second boosting circuit PB2. That is, the first boosting circuit PB1may operate earlier than the second boosting circuit PB2.

The first boosting driver200may output the boosting enable signal VBST_ENa that operates a plurality of boosting circuits PB to the row line RL. The boosting enable signal VBST_ENa is transferred along the row line RL and may be delayed. Although the boosting enable signal VBST_ENa may be transferred in the first direction X, some example embodiments of the present inventive concepts are not limited thereto.

The first boosting circuit PB1may include a first current source I1, a second current source I2, and a first switch SW1. The first current source I1may be connected to a second node N2of the first column line COL1and thus connected to the first column line COL1, and the first switch SW1may be connected to the second node N2of the first column line COL1and thus connected to the first column line COL1. Further, the second current source I2may be connected to the first switch SW1. That is, the first switch SW1may connect the second current source I2and the second node N2. The first switch SW1may operate in response to the first boosting enable signal VBST_ENa1transferred from the row line RL (e.g., transferred through the row line RL). That is, when the first boosting enable signal VBST_ENa1is applied, the first switch SW1may be closed. However, if the first boosting enable signal VBST_ENa1is not applied, the first switch SW1may be opened.

The first current source I1may generate a constant current, and the second current source I2may also generate a constant current. That is, when the first boosting enable signal VBST_ENa1is not applied, only the current generated from the first current source I1may flow through the second node N2. However, when the first boosting enable signal VBST_ENa1is applied, the overall currents generated from the first current source I1and the second current source I2may flow through the second node N2. Because the overall currents generated from the first current source I1and the second current source I2flow, the voltage of the first output signal Vout1may be adjusted. That is, the first boosting circuit PB1may be operated by the first boosting enable signal VBST_ENa1that is output from the first boosting driver200, and the voltage of the first output signal Vout1may be adjusted. At this time, the first column line COL1has a capacitor Ca. When a transfer control signal TS or a reset control signal RS is applied to the pixel PX, the voltage of the first output signal Vout1may increase temporarily. The first boosting circuit PB1may reduce the voltage of the increased first output signal Vout1, after the transfer control signal TS or the reset control signal RS is applied. Specifically, the first boosting circuit PB1may be boosted so that the voltage of the first output signal Vout1decreases faster.

A second boosting circuit PB2may also include a first current source I1, a second switch SW2and a second current source I2connected to the fourth node N4of the second column line COL2. The second switch SW2may be turned on or off by the second boosting enable signal VBST_ENa2. That is, the second boosting circuit PB2may be boosted so that the voltage of the second output signal Vout2decreases faster. At this time, the second boosting enable signal VBST_ENa2may reach the second boosting circuit PB2after the first boosting enable signal VBST_ENa1. Accordingly, the second boosting circuit PB2may operate after the first boosting circuit PB1. A boosting enable signal VBST_ENa may then be transferred in the first direction X along the row line RL. At this time, the second column line COL2has a capacitor Cb.

Referring toFIG.6, in the region R2, the second boosting driver210may be connected to a third boosting circuit PB3and a fourth boosting circuit PB4through the row line RL. In some example embodiments, the third and fourth boosting circuits PB3and PB4may be considered to be part of a single booster circuit PB that is connected to column lines COL1to COLn. In some example embodiments, the third boosting circuit PB3may be referred to as a third sub-boosting circuit, of a single boosting circuit PB, that is connected between a third column line COL(n−1) and the row line RL. In some example embodiments, the fourth boosting circuit PB4may be referred to as a fourth sub-boosting circuit, of a single boosting circuit PB, that is connected between a fourth column line COLn and the row line RL. Here, the row line RL may include parasitic resistors R3and R4and parasitic capacitors C3and C4. The parasitic resistor R4and the parasitic capacitor C4may exist between a fifth node N5, to which the third boosting circuit PB3and the row line RL are connected, and a seventh nodes N7to which the fourth boosting circuit PB4and the row line RL are connected. Further, the parasitic resistor R3and the parasitic capacitor C3may be connected to the fifth node N5.

A boosting enable signal VBST_ENb which is output from the second boosting driver210may be transferred by being delayed with the parasitic resistors R3and R4and the parasitic capacitors C3and C4. That is, the boosting enable signal VBST_ENb may be delayed by the RC delay. For example, a first boosting enable signal VBST_ENb1transferred to the fourth boosting circuit PB4may reach before a second boosting enable signal VBST_ENb2transferred to the third boosting circuit PB3. That is, the third boosting circuit PB3may operate earlier than the fourth boosting circuit PB4. Here, the first to fourth boosting circuits PB1to PB4may be sequentially arranged along the first direction X.

The second boosting driver210may output the boosting enable signal VBST_ENb that operates a plurality of boosting circuits PB to the row line RL. The boosting enable signal VBST_ENb is transferred along the row line RL and may be delayed. Although the boosting enable signal VBST_ENb may be transferred in the direction opposite to the first direction X, some example embodiments of the present inventive concepts are not limited thereto.

Referring toFIGS.5and6, in some example embodiments the image sensor100may be configured to delay the boosting enable signal VBST_ENa in relation to the boosting enable signal VBST_ENb such that the image sensor100is configured to cause the boosting enable signal VBST_ENb to be applied, as boosting enable signal VBST_ENb2, to the sub-boosting circuit connected to the column line COL(N−1) (e.g., boosting circuit PB3) before the boosting enable signal VBST_ENa is applied, as boosting enable signal VBST_ENa1, to the sub-boosting circuit connected to the column line COL1(e.g., boosting circuit PB1) and before the boosting enable signal VBST_ENb is applied to the sub-boosting circuit connected to the column line COL1(e.g., boosting circuit PB1).

The fourth boosting circuit PB4may include a first current source I1, a fourth switch SW4and a second current source I2connected to an eighth node N8of the fourth column line COLn. The fourth switch SW4may be turned on or off by the first boosting enable signal VBST_ENb1. That is, the fourth boosting circuit PB4may be boosted so that the voltage of the fourth output signal Vout4decreases faster. At this time, the fourth column line COLn has a capacitor Cd.

The third boosting circuit PB3may also include a first current source I1, a third switch SW3and a second current source I2connected to a sixth node N6of the third column line COL(n−1). The third switch SW3may be turned on or off by the second boosting enable signal VBST_ENb2. That is, the third boosting circuit PB3may be boosted so that the voltage of the third output signal Vout3decreases faster. At this time, the second boosting enable signal VBST_ENb2may reach the third boosting circuit PB3after the first boosting enable signal VBST_ENb1. Accordingly, the third boosting circuit PB3may operate after the fourth boosting circuit PB4. The boosting enable signal VBST_ENb may then be transferred along the row line RL in the direction opposite to the first direction X. At this time, the third column line COL(n−1) has a capacitor Cc.

A decrease in voltage of the first to fourth output signals Vout1to Vout4applied to the plurality of column lines COL1to COLn may be boosted by the boosting enable signal VBST_ENa that is output from the first boosting driver200and the boosting enable signal VBST_ENb that is output from the second boosting driver210. Here, the boosting enable signal VBST_ENa is transferred from the first boosting driver200in the first direction X along the row line RL, and the boosting enable signal VBST_ENb is transferred from the second boosting driver210along the row line RL in the direction opposite to the first direction X. Accordingly, the symmetry of the boosting circuit PB may be improved, and the settling time may be improved. A more detailed explanation thereof will be provided later.

FIG.7is a flowchart for explaining the operation of the image sensor according to some example embodiments.FIG.8is a timing diagram for explaining the operation of the image sensor according to some example embodiments.

Referring toFIGS.3to8, the row driver130may provide a transfer control signal TS to the transfer transistor TX of the pixel PX (S300). For example, the row driver130may provide the transfer control signal TS to the transfer transistor TX of the pixel PX, and charges generated from the photo diode PD may be transferred to the floating diffusion region FD. That is, the floating diffusion voltage VFD of the floating diffusion region FD may increase. Further, the voltage of the output signal Vout of the column lines COL1to COLn that receive the floating diffusion voltage VFD from the pixel PX may increase. However, the voltage of the output signal Vout may gradually increase, and a constant voltage may be maintained after a certain period of time.

The row driver130may interrupt the provision of the transfer control signals TS (S301). For example, the transfer control signal TS may not be applied to the transfer transistor TX at a first time t1. The floating diffusion voltage VFD may decrease accordingly. Also, the voltage of the output signal Vout may decrease, but it does not sharply decrease and may gradually decrease.

The first boosting driver200and the second boosting driver210may provide the row line RL with the boosting enable signals VBST_ENa and VBST_ENb (S302). As shown inFIG.8, the boosting enable signals VBST_ENa and VBST_ENb may be outputted by the first boosting driver200and the second boosting driver210at S302after the transfer control signal TS is applied (e.g., after the transfer control signal is provided at S300and stopped at S301).

For example, the first boosting driver200may output the boosting enable signal VBST_ENa, the first boosting enable signal VBST_ENa1may be transferred to the first boosting circuit PB1, and the second boosting enable signal VBST_ENa2may be transferred to the second boosting circuit PB2. Here, the first boosting enable signal VBST_ENa1may be applied from the first time t1to the third time t3, and the second boosting enable signal VBST_ENa2may be applied from the second time t2to the fourth time t4. Here, the first boosting enable signal VBST_ENa1may be transferred before the second boosting enable signal VBST_ENa2. That is, the first boosting circuit PB1may operate earlier than the second boosting circuit PB2.

For example, the second boosting driver210may output the boosting enable signal VBST_ENb, the first boosting enable signal VBST_ENb1may be transferred to the fourth boosting circuit PB4, and the second boosting enable signal VBST_ENb2may be transferred to the third boosting circuit PB3. Here, the first boosting enable signal VBST_ENb1may be applied from the first time t1to the third time t3, and the second boosting enable signal VBST_ENb2may be applied from the second time t2to the fourth time t4. Here, the first boosting enable signal VBST_ENb1may be transferred before the second boosting enable signal VBST_ENb2. That is, the fourth boosting circuit PB4may operate earlier than the third boosting circuit PB3. In some example embodiments, the first and fourth boosting circuits PB1and PB4may operate earlier than either the second or third boosting circuits PB2or PB3. In some example embodiments, the first and fourth boosting circuits PB1and PB4may operate during a same time (e.g., at least partially or exactly simultaneously or substantially simultaneously).

The first boosting enable signal VBST_ENa1and the first boosting enable signal VBST_ENb1may be transferred to the boosting circuit PB during the same time, and the second boosting enable signal VBST_ENa2and the second boosting enable signal VBST_ENb2may be transferred to the boosting circuit PB during the same time. That is, the second boosting enable signal VBST_ENa2and the second boosting enable signal VBST_ENb2may be transferred after the first boosting enable signal VBST_ENa1and the first boosting enable signal VBST_ENb1. For example, the image sensor100may be configured to cause the first boosting enable signal VBST_ENa to be applied, as boosting enable signal VBST_ENa1, to the sub-boosting circuit connected between the column line COL1and the row line RL (e.g., boosting circuit PB1) at a first time and to cause the second boosting enable signal VBST_ENb to be applied, as boosting enable signal VBST_ENb1, to the sub-boosting circuit connected between the column line COLn and the row line RL (e.g., boosting circuit PB4) at the same first time, such that the first and second boosting enable signals VBST_ENa and VBST_ENb are applied to the first and fourth sub-boosting circuits, respectively, at a same first time (e.g., simultaneously or substantially simultaneously). In another example, the image sensor100may be configured to cause the first boosting enable signal VBST_ENa to be applied, as boosting enable signal VBST_ENa2, to the sub-boosting circuit connected between the column line COL2and the row line RL (e.g., boosting circuit PB2) at a second time and to cause the second boosting enable signal VBST_ENb to be applied, as boosting enable signal VBST_ENb2, to the sub-boosting circuit connected between the column line COL(n−1) and the row line RL (e.g., boosting circuit PB3) at the same second time, such that the first and second boosting enable signals VBST_ENa and VBST_ENb are applied to the second and third sub-boosting circuits, respectively, at a same second time (e.g., simultaneously or substantially simultaneously). However, some example embodiments of the present inventive concepts are not limited thereto.

As shown in at leastFIG.8, the image sensor100may be configured to cause the respective switches SW1and SW4of the first and fourth boosting circuits PB1and PB4to close (based on the respective boosting enable signals VBST_ENa1and VBST_ENb1) earlier than the respective switches SW2and SW3of the second and third boosting circuits PB2and PB3are closed (based on the respective boosting enable signals VBST_ENa2and VBST_ENb2).

As further shown in at leastFIG.8, the image sensor is configured to, after the respective switches SW1to SW4of the first to fourth boosting circuits PB1and PB4are closed, cause the respective switches SW1and SW4of the first and fourth boosting circuits PB1and PB4to open (e.g., based on the stopping of the respective boosting enable signals VBST_ENa1and VBST_ENb1) earlier than the respective switches SW2and SW3of the second and third boosting circuits PB2and PB3are opened (based on the stopping of the respective boosting enable signals VBST_ENa2and VBST_ENb2).

The boosting circuits PB may operate on the basis of the boosting enable signal VBST_ENa and the boosting enable signal VBST_ENb (S303). Accordingly, the voltage of the output signal Vout applied to the column lines COL1to COLn may be settled.

Referring toFIG.8, the voltage of the first output signal Vout1and the voltage of the fourth output signal Vout4may be reduced by the first boosting enable signal VBST_ENa1and the first boosting enable signal VBST_ENb1. That is, the voltage of the first output signal Vout1and the voltage of the fourth output signal Vout4may be reduced more rapidly. Accordingly, the voltage of the first output signal Vout1and the voltage of the fourth output signal Vout4may be settled after a first settling time interval ST1.

The voltage of the second output signal Vout2and the voltage of the third output signal Vout3may be reduced by the second boosting enable signal VBST_ENa2and the second boosting enable signal VBST_ENb2. That is, the voltage of the second output signal Vout2and the voltage of the third output signal Vout3may be reduced more rapidly. Accordingly, the voltage of the second output signal Vout2and the voltage of the third output signal Vout3may be settled after a second settling time interval ST2. Here, the second settling time interval ST2may be greater than the first settling time interval ST1. That is, the settling time interval of the voltage of the output signal Vout applied to the column lines COL1to COLn may increase, as it goes away from the first and second boosting drivers200and210.

In this case, when the boosting enable signal VBST_ENa and the boosting enable signal VBST_ENb are transferred in both directions from the first boosting driver200and the second boosting driver210located on both sides of the row line RL, the settling time interval of voltage of the output signal Vout applied to the column lines COL1to COLn may be reduced generally. Accordingly, the asymmetry of the image sensor100may be improved, and the image quality of the image sensor100may be improved.

Also, boosting of the voltage of the output signal Vout may be further required when no light is incident on the photo diode PD. At this time, when the settling time interval of voltage of the output signal Vout decreases, the dark shading or dark offset of the image sensor100may be reduced. Further, when the settling time interval of voltage of the output signal Vout decreases, the image sensor100may operate at high speed.

Hereinafter, the operation of the image sensor100will be explained referring toFIG.9.

FIG.9is a timing diagram for explaining the operation of the image sensor according to some example embodiments. For convenience of explanation, repeated parts of contents explained usingFIGS.1to8will be briefly explained or omitted.

Referring toFIG.9, the row driver130may provide a reset control signal RS to the reset transistor RX. For example, the row driver130may provide a reset control signal RS to the reset transistor RX of the pixel PX. Accordingly, the floating diffusion voltage VFD of the floating diffusion region FD may increase. Further, the voltage of the output signal Vout of the column lines COL1to COLn that receive the floating diffusion voltage VFD from the pixel PX may increase. However, the voltage of the output signal Vout may gradually increase, and a constant voltage may be maintained after a certain period of time.

The row driver130may interrupt the provision of the reset control signal RS. For example, the reset control signal RS may not be applied to the reset transistor RX at the first time t1. The floating diffusion voltage VFD may decrease accordingly. Also, the voltage of the output signal Vout may decrease, but it does not sharply decrease and may gradually decrease.

The first boosting driver200and the second boosting driver210may provide the row line RL with the boosting enable signals VBST_ENa and VBST_ENb. Accordingly, the voltages of the first output signal Vout1and the fourth output signal Vout4may be settled during a first settling time interval ST1′, and the voltage of the second output signal Vout2and the third output signal Vout3may be settled during a second settling time interval ST2′. That is, even when the reset control signal RS is applied to the pixel PX, the boosting circuit PB boosts the decrease in voltage of the output signal Vout of the column lines COL1to COLn. As shown inFIG.9, the boosting enable signals VBST_ENa and VBST_ENb may be outputted by the first boosting driver200and the second boosting driver210at S302after the reset control signal RS is applied (e.g., after the reset control signal is provided and stopped as shown inFIG.9).

Hereinafter, the operation of the image sensor100will be explained referring toFIGS.10to12.

FIG.10is a flowchart for explaining the operation of the image sensor according to some example embodiments.FIG.11is a diagram of a region R2for explaining the image sensor according to some example embodiments.FIG.12is a timing diagram for explaining the operation of the image sensor according to some example embodiments. For convenience of explanation, repeated parts of contents explained usingFIGS.1to9will be briefly explained or omitted.

Referring toFIG.10, the row driver130may provide the reset control signal RS to the reset transistor RX or provide the transfer control signal TS to the transfer transistor TX (S310). After that, the row driver130may interrupt the provision of the reset control signal RS or the transfer control signal TS to the pixel PX. Here, although it is assumed that the transfer control signal TS is provided to the pixel PX, some example embodiments of the present inventive concepts are not limited thereto. The voltage of the output signal Vout of the color lines COL1to COLn may increase and become constant, while the transfer control signal TS is being provided.

The image sensor100may determine whether the incident light is greater than a threshold value (e.g., whether the intensity, illuminance, amount, etc. of the incident light is greater than an incident value) (S311). For example, the image sensor100may determine whether the incident light is greater than the threshold value, using another illuminance sensor or the like. However, some example embodiments of the present inventive concepts are not limited thereto, and the image sensor100may determine this by other methods.

If the incident light is not greater than (e.g., equal to or less than) the threshold value (S311-N), the image sensor100may operate the first boosting driver200and the second boosting driver210(S312). That is, both the first boosting driver200and the second boosting driver210may operate as explained referring toFIGS.1to9. At this time, the first switch SWC1and the second switch SWC2may be closed. That is, the boosting circuit PB may be connected to the first boosting driver200through the first switch SWC1, and the boosting circuit PB may be connected to the second boosting driver210through the second switch SWC2.

If the incident light is greater than the threshold value (S311-Y), the image sensor100may operate the first boosting driver200(S313). That is, the second boosting driver210may not operate, and only the first boosting driver200may operate. If the incident light is greater than the threshold value, settling of voltage of the output signal Vout may be less important. Accordingly, only the first boosting driver200may be used, and dark shading and dark offset may not occur. As described herein, operating only the first boosting driver200at S313may be referred to as the image sensor100operating in a first operating mode, and operating both the first and second boosting drivers200and210at S312may be referred to as the image sensor operating in a second operating mode that is different from the first operating mode. As described herein, when the image sensor100is operating in the first operating mode, the boosting circuits PB may each be understood to operate in the first operating mode, and when the image sensor100is operating in the second operating mode, the boosting circuits PB may each be understood to operate in the second operating mode.

Referring toFIG.11, the second switch SWC2may have an open state. That is, the second boosting driver210may not be connected to the row line RL. Although not shown in the drawing, the first switch SWC1may have a closed state. That is, all the boosting circuits PB may be connected to the first boosting driver200through the first switch SWC1and the row line RL. Such connection as shown inFIG.11may occur when the image sensor100is operating in the first operating mode at S313inFIG.10. That is, the boosting circuits PB may be operated by the boosting enable signal VBST_ENa that is output from the first boosting driver200. At this time, the boosting enable signal VBST_ENa may be transferred only in the first direction X along the row line RL. Accordingly, the image sensor100may be configured to open the second switch SWC2based on the image sensor100operating in the first operating mode at S312and to close the second switch SWC2based on the image sensor100operating in the second operating mode at S312. Although it is assumed that only the first boosting driver200is connected to the row line RL in the description, some example embodiments of the present inventive concepts are not limited thereto. For example, only the second boosting driver210may be connected to the row line RL. In this case, the second switch SWC2may have a closed state, and the first switch SWC1may have an open state.

The third boosting circuit PB3and the fourth boosting circuit PB4may be placed adjacent to the second boosting driver210. However, the third boosting circuit PB3and the fourth boosting circuit PB4are not connected to the second boosting driver210, but may be connected to the first boosting driver200. A distance from the first boosting driver200to the third and fourth boosting circuits PB3and PB4may be greater than a distance from the second boosting driver210to the third and fourth boosting circuits PB3and PB4.

Referring toFIGS.11and12, the third boosting circuit PB3may receive the boosting enable signal VBST_ENa. The boosting enable signal VBST_ENa may be delayed by a parasitic resistor R3and a parasitic capacitor C3. Accordingly, the third boosting circuit PB3may receive a third boosting enable signal VBST_ENa3. At this time, the third boosting enable signal VBST_ENa3may be transferred after the first boosting enable signal VBST_ENa1and the second boosting enable signal VBST_ENa2. Accordingly, the third settling time interval ST3of voltage of the third output signal Vout3may be greater than the first settling time interval ST1and the second settling time interval ST2.

The fourth boosting circuit PB4may receive the boosting enable signal VBST_ENa. The boosting enable signal VBST_ENa may be delayed by the parasitic resistor R4and the parasitic capacitor C4. Accordingly, the fourth boosting circuit PB4may receive the fourth boosting enable signal VBST_ENa4. At this time, the fourth boosting enable signal VBST_ENa4may be transferred after the first boosting enable signal VBST_ENa1, the second boosting enable signal VBST_ENa2, and the third boosting enable signal VBST_ENa3. Accordingly, the fourth settling time interval ST4of voltage of the fourth output signal Vout4may be greater than the first settling time interval ST1, the second settling time interval ST2, and the third settling time interval ST3.

As a result, the third and fourth boosting circuits PB3and PB4may be configured to adjust a voltage of respective third and fourth output signals Vout3and Vout4based on the boosting enable signal VBST_ENa3and VBST_ENa4received from the first boosting driver200based on the image sensor100operating in a first operating mode (e.g., at S312inFIG.10), for example operating such that switch SWC1is closed and switch SWC2is opened. Additionally, the third and fourth boosting circuits PB3and PB4may be configured to adjust a voltage of respective third and fourth output signals Vout3and Vout4based on the boosting enable signal VBST_ENb1and VBST_ENb2received from the second boosting driver210based on the image sensor100operating in a second operating mode (e.g., at S313inFIG.10), for example operating such that switch SWC1and SWC2are both closed.

Still referring toFIGS.10and11, because the first boosting circuit PB1may be operated in either the first operating mode (S312) or the second operating mode (S313), the first boosting circuit PB1may be configured to adjust a voltage of the first output signal Vout1based on the first boosting enable signal VBST_ENa1received from the first boosting driver200based on the image sensor100operating in either of the first operating mode or the second operating mode, for example due to the adjacency of the first boosting circuit PB1to the first boosting driver200as shown in at leastFIGS.3and5.

Hereinafter, the operation of the image sensor100will be explained referring toFIG.13.

FIG.13is a flowchart for explaining the operation of the image sensor according to some example embodiments. For convenience of explanation, repeated parts of contents explained usingFIGS.1to12will be briefly explained or omitted.

Referring toFIG.13, the row driver130may provide the reset control signal RS to the reset transistor RX or may provide the transfer control signal TS to the transfer transistor TX (S320). After that, the row driver130may interrupt the provision of the reset control signal RS or the transfer control signal TS to the pixel PX. The voltage of the output signal Vout of the color lines COL1to COLn may increase and become constant, while the transfer control signal TS or the reset control signal RS is being provided.

The image sensor100may determine whether the number of pixels PX is greater than the threshold value (S321). For example, the image sensor100may determine whether the pixel array140includes pixels PX of the threshold value or more.

If the number of pixels PX is greater than the threshold value (S321-Y), the image sensor100may determine whether the operating speed is greater than the threshold value (S322). For example, the image sensor100may determine whether the speed of the signal output from the row driver130is high.

If the operating speed of the image sensor100is greater than the threshold value (S322-Y), the image sensor100may operate the first boosting driver200and the second boosting driver210(S323). That is, both the first boosting driver200and the second boosting driver210may operate as explained referring toFIGS.1to9. That is to say, when the number of pixels PX of the image sensor100is large and the operating speed is high, the image sensor100may boost the decrease in voltage of the output signal Vout of the column lines COL1to COLn, using both the first boosting driver200and the second boosting driver210.

If the number of pixels PX is not greater than the threshold value (S321-N), or if the operating speed of the image sensor100is not greater than the threshold value (S322-N), the image sensor100may operate the first boosting driver200(S324). That is, the second boosting driver210may not operate, and only the first boosting driver200may operate.

Hereinafter, the image sensor100will be explained referring toFIG.14.

FIG.14is a diagram for explaining an image sensor according to some example embodiments. For convenience of explanation, repeated parts of contents explained usingFIGS.1to13will be briefly explained or omitted.

Referring toFIG.14, the image sensor100may include a row driver132(also referred to herein as a second row driver). Here the row driver132may be different from the row driver130(which is also referred to herein as a first row driver). The row driver132may be spaced apart from (e.g., isolated from direct contact with) the pixel array140in the first direction X. The row driver132may be connected to a plurality of row lines ROW1to ROWn. That is, one ends of the plurality of row lines ROW1to ROWn may be connected to the row driver130, and the other ends of the plurality of row lines ROW1to ROWn may be connected to the row driver132. For example, the first row line ROW1and the pixels PX connected thereto may be between the row drivers130and132. The row driver132may output control signals to the plurality of row lines ROW1to ROWn, and may drive the image sensor100. Also, the row driver132may be located on the same side as the second boosting driver210.

Hereinafter, an electronic device2000according to some example embodiments will be explained referring toFIGS.15and16.

As described herein, any image sensing devices, image sensors, and/or portions thereof according to any of the example embodiments, including the image sensing device1, the image sensor100, and/or any portions thereof (including, without limitation, the control register block110, the timing generator120, the row driver130, the pixel array140, the readout circuit150, the ramp signal generator160, the buffer170, the image signal processor900, etc.) may include, may be included in, and/or may be implemented by one or more instances of processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), and programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an Electronic Control Unit (ECU), an Image Signal Processor (ISP), and the like. In some example embodiments, the processing circuitry may include a non-transitory computer readable storage device (e.g., a memory), for example a solid state drive (SSD), storing a program of instructions, and a processor (e.g., CPU) configured to execute the program of instructions to implement the functionality and/or methods performed by some or all of the image sensor, including the functionality and/or methods performed by some or all of the image sensor.

FIG.15is a block diagram for explaining an electronic device including a multi-camera module according to some example embodiments.FIG.16is a detailed block diagram of the camera module ofFIG.15. For convenience of explanation, repeated parts of contents explained usingFIGS.1to14will be briefly explained or omitted.

Referring toFIG.15, the electronic device2000may include a camera module group2100, an application processor2200, a PMIC2300, an external memory2400, and a display2500.

The camera module group2100may include a plurality of camera modules2100a,2100band2100c, also referred to herein as simply “cameras.” Even if the drawing shows some example embodiments in which three camera modules2100a,2100band2100care placed, some example embodiments are not limited thereto. In some example embodiments, the camera module group2100may be modified to include only two camera modules. Also, in some example embodiments, the camera module group2100may be modified to include n (n is a natural number equal to or greater than 4) camera modules.

Here, one of the three camera modules2100a,2100b, and2100cmay include the image sensor100explained referring toFIGS.1to14. That is, the image sensor100of the camera module2100a,2100band2100cmay include both the first boosting driver200and the second boosting driver210.

Hereinafter, although the detailed configuration of the camera module2100bwill be explained in more detail referring toFIG.16, the following explanation may also be equally applied to other camera modules2100aand2100cdepending on the example embodiments.

Referring toFIG.16, the camera module2100bmay include a prism2105, an optical path folding element hereinafter (hereinafter, “OPFE”)2110, an actuator2130, an image sensing device2140, and a storage device2150(e.g., a storage device or memory, such as a non-transitory computer-readable storage device.

The prism2105may include a reflecting surface2107of a light-reflecting material to modify the path of light L that is incident from the outside.

In some example embodiments, the prism2105may change the path of light L incident in the first direction X to a second direction Y perpendicular to the first direction X. Further, the prism2105may rotate the reflecting surface2107of the light-reflecting material in a direction A around a central axis2106, or may rotate the central axis2106in a direction B to change the path of the light L incident in the first direction X into the vertical second direction Y. At this time, the OPFE2110may also move in the third direction Z that is perpendicular to the first direction X and the second direction Y.

In some example embodiments, as shown, although a maximum rotation angle of the prism2105in the direction A is equal to or less than 15 degrees in a positive (+) direction A, and may be greater than 15 degrees in a negative (−) direction A, some example embodiments are not limited thereto.

In some example embodiments, the prism2105may move about 20 degrees, or between 10 and 20 degrees, or between 15 and 20 degrees in the positive (+) or negative (−) direction B. Here, the moving angle may move at the same angle in the positive (+) or negative (−) direction B, or may move to almost the same angle within the range of about 1 degree.

In some example embodiments, the prism2105may move the reflecting surface2107of the light-reflecting material in the third direction (e.g., a direction Z) parallel to the extension direction of the central axis2106.

The OPFE2110may include, for example, an optical lens including m (here, m is a natural number) groups. The m lenses may move in the second direction Y to change an optical zoom ratio of the camera module2100b. For example, when a basic optical zoom ratio of the camera module2100bis set as Z, if the m optical lenses included in the OPFE2110are moved, the optical zoom ratio of the camera module2100bmay be changed to the optical zoom ratio of 3Z or 5Z or higher.

The actuator2130may move the OPFE2110or an optical lens (hereinafter, referred to as an optical lens) to a specific position. For example, the actuator2130may adjust the position of the optical lens so that the image sensor2142is located at a focal length of the optical lens for accurate sensing.

The image sensing device2140may include an image sensor2142, control logic2144and a memory2146. The image sensor2142may sense the image to be sensed, using light L provided through the optical lens. In some example embodiments, the image sensor2142may include the image sensor100described above.

The control logic2144may control the overall operation of the camera module2100b. For example, the control logic2144may control the operation of the camera module2100baccording to the control signal provided through the control signal line CSLb.

The memory2146may store information necessary for the operation of the camera module2100bsuch as calibration data2147. The calibration data2147may include information necessary for the camera module2100bto generate image data, using the light L provided from the outside. The calibration data2147may include, for example, information on the degree of rotation, information on the focal length, information on the optical axis explained above, and the like. If the camera module2100bis implemented in the form of a multi-state camera whose focal length changes depending on the position of the optical lens, the calibration data2147may include information about the focal length values and auto focusing for each position (or for each state) of the optical lens.

The storage device2150may store the image data sensed through the image sensor2142. The storage device2150may be placed outside the image sensing device2140, and may be implemented in the form of being stacked with a sensor chips constituting the image sensing device2140. In some example embodiments, although the storage device2150may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), some example embodiments are not limited thereto.

Referring toFIGS.15and16together, in some example embodiments, each of the plurality of camera modules2100a,2100b, and2100cmay include an actuator2130. Accordingly, each of the plurality of camera modules2100a,2100b, and2100cmay include calibration data2147that is the same as or different from each other depending on the operation of the actuator2130included therein.

In some example embodiments, one camera module (e.g.,2100b) among the plurality of camera modules2100a,2100b, and2100cis a folded lens (e.g.,2100b) type camera module including the prism2105and the OPFE2110described above, and the remaining camera modules (e.g.,2100aand2100c) may be vertical camera modules which do not include the prism2105and the OPFE2110. However, some example embodiments are not limited thereto.

In some example embodiments, one camera module (e.g.,2100c) among the plurality of camera modules2100a,2100b, and2100cmay be a vertical depth camera which extracts depth information, for example, using an IR (Infrared Ray). In this case, the application processor2200may merge the image data provided from such a depth camera with the image data provided from another camera module (e.g.,2100aor2100b) to generate a three-dimensional (3D) depth image.

In some example embodiments, at least two camera modules (e.g.,2100aand2100c) among the plurality of camera modules2100a,2100b, and2100cmay have fields of view different from each other. In this case, for example, although the optical lenses of at least two camera modules (e.g.,2100aand2100c) among the plurality of camera modules2100a,2100b, and2100cmay be different from each other, some example embodiments are not limited thereto.

Also, in some example embodiments, viewing angles of each of the plurality of camera modules2100a,2100b, and2100cmay be different from each other. In this case, although the optical lenses included in each of the plurality of camera modules2100a,2100b, and2100cmay also be different from each other, some example embodiments are not limited thereto.

In some example embodiments, each of the plurality of camera modules2100a,2100b, and2100cmay be placed physically separated from each other. That is, the sensing region of one image sensor2142is not used separately by a plurality of camera modules2100a,2100b, and2100c, but an independent image sensor2142may be placed inside each of the plurality of camera modules2100a,2100b, and2100c.

Referring toFIG.15again, the application processor2200may include an image processing device2210, a memory controller2220, and an internal memory2230. The application processor2200may be implemented separately from the plurality of camera modules2100a,2100b, and2100c. For example, the application processor2200and the plurality of camera modules2100a,2100b, and2100cmay be implemented separately as separate semiconductor chips.

The image processing device2210may include a plurality of sub-image processors2212a,2212b, and2212c, an image generator2214, and a camera module controller2216.

The image processing device2210may include a plurality of sub-image processors2212a,2212b,2212ccorresponding to the number of the plurality of camera modules2100a,2100b, and2100c.

Image data generated from each of the camera modules2100a,2100b, and2100cmay be provided to the corresponding sub-image processors2212a,2212b, and2212cthrough image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated from the camera module2100ais provided to the sub-image processor2212athrough the image signal line ISLa, the image data generated from the camera module2100bis provided to the sub-image processor2212bthrough the image signal line ISLb, and the image data generated from the camera module2100cmay be provided to the sub-image processor2212cthrough the image signal line ISLc. Although such an image data transmission may be performed using, for example, a camera serial interface (CSI) based on a mobile industry processor interface (MIPI), some example embodiments are not limited thereto.

On the other hand, in some example embodiments, one sub-image processor may be placed to correspond to a plurality of camera modules. For example, the sub-image processor2212aand the sub-image processor2212care not implemented separately from each other as shown, but are integrated and implemented as a single sub-image processor. The image data provided from the camera module2100aand the camera module2100cmay be selected through a selection element (e.g., a multiplexer) or the like and then provided to an integrated sub-image processor.

The image data provided to the respective sub-image processors2212a,2212b, and2212cmay be provided to the image generator2214. The image generator2214may generate the output image, using the image data provided from the respective sub-image processors2212a,2212b, and2212caccording to the image generating information or the mode signal.

Specifically, the image generator2214merges at least a part of the image data generated from the camera modules2100a,2100b, and2100chaving different viewing angles to generate the output image, according to the image generating information or the mode signals. Further, the image generator2214may select any one of the image data generated from the camera modules2100a,2100b, and2100chaving different viewing angles and output the output image, according to the image generating information or the mode signal.

In some example embodiments, the image generating information may include a zoom signal (or a zoom factor). Also, in some example embodiments, the mode signal may be, for example, a signal based on the mode selected from a user.

When the image generating information is a zoom signal (a zoom factor) and each of the camera modules2100a,2100b, and2100chas different fields of view (viewing angles), the image generator2214may perform different operations depending on the type of zoom signal. For example, when the zoom signal is a first signal, the image data output from the camera module2100aand the image data output from the camera module2100care merged, and then an output image may be generated, using the merged image signal, and the image data which is not used for merging and output from the camera module2100b. If the zoom signal is a second signal that is different from the first signal, the image generator2214does not merge the image data, and may select one of the image data output from each of the camera modules2100a,2100b, and2100cand generate the output image. However, some example embodiments are not limited thereto, and the method of processing the image data may be modified as much as necessary.

In some example embodiments, the image generator2214may receive a plurality of image data with different exposure times from at least one of the plurality of sub-image processors2212a,2212b, and2212c, and perform high dynamic range (HDR) processing on the plurality of image data to generate merged image data with an increased dynamic range.

The camera module controller2216may provide the control signal to each of the camera modules2100a,2100b, and2100c. The control signals generated from the camera module controller2216may be provided to the corresponding camera modules2100a,2100b, and2100cthrough the control signal lines CSLa, CSLb and CSLc separated from each other.

One of the plurality of camera modules2100a,2100b, and2100cis designated as a master camera (e.g.,2100a) depending on the image generating information including the zoom signal or the mode signal, and the remaining camera modules (e.g.,2100band2100c) may be designated as a slave camera. This information is included in the control signal, and may be provided to the corresponding camera modules2100a,2100b, and2100cthrough the control signal lines CSLa, CSLb and CSLc separated from each other.

Depending on the zoom factor or the operation mode signal, the camera modules that operate as master and slave may be modified. For example, if the viewing angle of the camera module2100ais wider than that of the camera module2100cand the zoom factor exhibits a low zoom ratio, the camera module2100coperates as the master, and the camera module2100amay operate as the slave. In contrast, when the zoom factor exhibits a high zoom ratio, the camera module2100amay operate as the master and the camera module2100cmay operate as the slave.

In some example embodiments, the control signal provided from the camera module controller2216to the respective camera modules2100a,2100b, and2100cmay include a sync enable signal. For example, if the camera module2100bis the master camera and the camera modules2100aand2100care slave cameras, the camera module controller2216may transmit sync enable signal to the camera module2100b. The camera module2100b, which receives the sync enable signal, generates a sync signal on the basis of the received sync enable signal, and may provide the generated sync signal to the camera modules2100aand2100cthrough the sync signal line SSL. The camera modules2100band the camera modules2100aand2100cmay transfer the image data to the application processor2200in synchronization with such a sync signal.

In some example embodiments, the control signal provided from the camera module controller2216to the plurality of camera modules2100a,2100b, and2100cmay include mode information according to the mode signal. On the basis of the mode information, the plurality of camera modules2100a,2100b, and2100cmay operate in the first and second operating modes in connection with the sensing speed.

The plurality of camera modules2100a,2100b, and2100cmay generate an image signal at the first speed (for example, generate an image signal of a first frame rate) in the first operation mode, encode the image signal at a second speed higher than the first speed (for example, encode an image signal of a second frame rate higher than the first frame rate), and transmit the encoded image signal to the application processor2200. At this time, the second speed may be 30 times or less of the first speed.

The application processor2200may store the received image signal, that is to say, the encoded image signal, in the internal memory2230or an external memory2400of the application processor2200, and then read and decode the encoded image signal from the internal memory2230or the external memory2400, and display image data generated on the basis of the decoded image signal. For example, the corresponding sub-image processors among the plurality of sub-image processors2212a,2212b, and2212cof the image processing device2210may perform decoding, and may also perform image processing on the decoded image signal. For example, the image data generated on the basis of the decoded image signal may be displayed on the display2500.

A plurality of camera modules2100a,2100b, and2100cmay generate image signals at a third speed lower than the first speed in the second operating mode (for example, generate an image signal of a third frame rate lower than the first frame rate), and transmit the image signal to the application processor2200. The image signal provided to the application processor2200may be a non-encoded signal. The application processor2200may perform image processing on the received image signal or store the image signal in the internal memory2230or the external memory2400.

The PMIC2300may supply the power, e.g., the power supply voltage, to each of the plurality of camera modules2100a,2100b, and2100c. For example, the PMIC2300may supply the first power to the camera module2100athrough a power signal line PSLa, supply the second power to the camera module2100bthrough a power signal line PSLb, and supply the third power to the camera module2100cthrough a power signal line PSLc, under the control of the application processor2200.

The PMIC2300may generate power corresponding to each of the plurality of camera modules2100a,2100b, and2100cand adjust the level of power, in response to a power control signal PCON from the application processor2200. The power control signal PCON may include power adjustment signals for each operating mode of the plurality of camera modules2100a,2100b, and2100c. For example, the operating mode may include a low power mode, and at this time, the power control signal PCON may include information about the camera module operating in the low power mode and the set power level. The levels of powers provided to each of the plurality of camera modules2100a,2100b, and2100cmay be the same as or different from each other. Also, the levels of powers may be changed dynamically.

As described herein, any of the electronic devices, including the electronic device2000, and/or any portions thereof (including, without limitation, the application processor2200, the image processing device2210, the memory controller2220, the internal memory2230, any of the sub-image processors2212ato2212c, image generator2214, camera module controller2216, the PMIC2300, the external memory2400, and/or any of the camera modules2100a-2100cof the camera module group2100, including image sensing device2140, image sensor2142, control logic2144, memory2146, storage device2150, OPFE2110, etc.) may include, may be included in, and/or may be implemented by one or more instances of processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), and programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an Electronic Control Unit (ECU), an Image Signal Processor (ISP), and the like. In some example embodiments, the processing circuitry may include a non-transitory computer readable storage device (e.g., internal memory2230, external memory2400, memory2146, and/or storage device2150), for example a solid state drive (SSD), storing a program of instructions, and a processor (e.g., image processing device2210or any portion thereof, memory controller2220, camera module controller2216, etc.) configured to execute the program of instructions to implement the functionality and/or methods performed by some or all of the electronic device, including the functionality and/or methods performed by some or all of the image processing device2210, the image generator2214, the camera module controller2216, any of the sub-image processors2212ato2212c, the memory controller2220, the internal memory2230, the PMIC2300, the external memory2400, the application processor2200, the image sensing device2140, any combination thereof, or the like.

Any of the memories described herein, including, without limitation, internal memory2230, external memory2400, memory2146, and/or storage device2150may be a non-transitory computer readable medium and may store a program of instructions. Any of the memories described herein may be a nonvolatile memory, such as a flash memory, a phase-change random access memory (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), or a ferro-electric RAM (FRAM), or a volatile memory, such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM).

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the described example embodiments described without substantially departing from the principles of the present inventive concepts. Therefore, the described example embodiments of the inventive concepts are used in a generic and descriptive sense only and not for purposes of limitation.