Patent ID: 12255177

DETAILED DESCRIPTION

Various embodiments of the present teachings will be described in greater detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, possible embodiments should not be construed as being limited to the particular configurations and shapes illustrated herein but may include deviations in configurations and shapes which do not depart from the spirit and scope of the present teachings as defined in the appended claims.

The present teachings are described herein with reference to cross-section and/or plan illustrations of idealized embodiments. However, embodiments of the present teachings should not be construed as limiting the inventive concept. Although a few embodiments of the present teachings will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made in these embodiments without departing from the principles and spirit of the present teachings.

FIG.1is a cross-sectional view illustrating a stacked semiconductor device in accordance with an example embodiment, andFIG.2is a plan view illustrating a stacked semiconductor device in accordance with an example embodiment.

Referring toFIG.1, a semiconductor device10-1may include a plurality of semiconductor dies100which are vertically stacked. Further, the semiconductor device10-1includes a plurality of through silicon vias (TSV)301,303,305,307, and a plurality of conductive bumps400, to electrically couple the stacked semiconductor dies100. The semiconductor device10-1further includes a first power line210, a second power line230, and an external connection line500.

In example embodiments, a first semiconductor die101may be arranged on an upper surface of a substrate (not shown). A second semiconductor die103may be stacked on the first semiconductor die101. A third semiconductor die105, a fourth semiconductor die107, a fifth semiconductor die (not shown), etc., may be sequentially stacked on the second semiconductor die103. The number of stacked semiconductor dies100may be changed based on need.

For example, the first semiconductor die101may correspond to a lowermost semiconductor die among the stacked semiconductor dies100. A circuit (not shown) for interfacing a memory controller with other semiconductor dies including the second semiconductor die103, the third semiconductor die105, and the fourth semiconductor die107may be formed in/on the first semiconductor die101. The first semiconductor die101may include power management, memory management, etc., between the semiconductor dies100, but is not limited thereto.

A TSV301(hereinafter, a first TSV) may be formed in the first semiconductor die101to penetrate the first semiconductor die101. The first power line210may be arranged under the first semiconductor die101. The first power line210may be connected to the first semiconductor die101. The first semiconductor die101may receive power from the first power line210by a connection member C. For example, the first TSV301may be connected to the first power line210by the connection member C. The first semiconductor die101may share the power from the first power line210with the stacked semiconductor dies103,105, and107.

The second semiconductor die103may be stacked on the first semiconductor die101. The second semiconductor die103may include a TSV303(hereinafter, a second TSV). The second TSV303may correspond to the first TSV301. The first TSV301may be electrically connected with the second TSV303via a conductive bump400.

The third semiconductor die105and the fourth semiconductor die107may be electrically connected with the second semiconductor die103by the second TSV303, a TSV305(hereinafter, third TSV) formed in the third semiconductor die105, a TSV307(hereinafter, fourth TSV) formed in the fourth semiconductor die107and conductive bumps400between the TSVs. That is, the first to fourth TSVs301,303,305, and307may be arranged to correspond to each other.

For example, an uppermost position of the stacked semiconductor device10-1may correspond to the fourth semiconductor die107. The second power line230is arranged on an upper surface of the fourth semiconductor die107. The second power line230may be configured to contact with the fourth TSV307. The second power line230may have a shape configured to wholly cover the upper surface of the fourth semiconductor die107, but is not limited thereto.

The first power line210and the second power line230may be electrically connected by the external connection line500. For example, the external connection line500may include a wire.

The power may be directly supplied to the uppermost semiconductor die and the lowermost semiconductor die through the external connection line500so that the power may be relatively rapidly supplied to the semiconductor device10-1compared to when the power must be supplied to the uppermost semiconductor die through the lowermost and intermediate semiconductor dies.

Referring toFIG.2, the fourth semiconductor die107corresponding to the uppermost semiconductor die may include the second power line230. The second power line230may make contact with the fourth TSV307. The external connection line500may be configured to connect the first power line210connected to the first semiconductor die101with the second power line230on the fourth semiconductor die107.

FIG.3is a cross-sectional view illustrating a stacked semiconductor device in accordance with an example embodiment.

Referring toFIG.3, a stacked semiconductor device10-2may include a plurality of vertically stacked semiconductor dies100and TSVs310and320. The TSVs310may be configured to connect the semiconductor dies100with signals. The TSVs320may be configured to connect the semiconductor dies100with power. The stacked semiconductor device10-2may include first interconnection layers M1and second interconnection layers M2. The number of interconnection layers is not restricted to be equal to or less than any specific value. Connecting portions such as the first interconnection layer M1and the second interconnection layer M2may be located on at least one position in the TSVs310and320. The connection portions may be electrically connected with each other via the TSV.

In order to transmit signals between the stacked semiconductor dies100, each semiconductor die100may include a first interconnection layer M1, a second interconnection layer M2, a logic circuit L, and a TSV310. The semiconductor dies100may be connected with each other via conductive bumps400.

The first interconnection layers M1and the second interconnection layers M2may function as electrical connections. The first interconnection layers M1in the semiconductor dies100may be positioned on a plane lower than a plane where the second interconnection layers M2may be positioned. The first interconnection layers M1and the second interconnection layers M2may be distinguished from each other for description in accordance with their positions, a first interconnection layer being lower than a second interconnection layer within the same semiconductor die. This, however, need not always be the case. A first interconnection layer M1may be connected with a lower semiconductor die through a conductive bump400. The first interconnection layer M1may be directly or indirectly connected to a second interconnection layer M2, The second interconnection layer M2may make contact with one end of a TSV310so that the second interconnection layer M2may be connected with an upper semiconductor die. The other end of the TSV310may be connected with the upper semiconductor die via a conductive bump400. The semiconductor dies100having the above-indicated structure may be vertically stacked.

The logic circuit L may be arranged between the first interconnection layer M1and the second interconnection layer M2. The logic circuit L may transmit and receive signals between the upper semiconductor die and the lower semiconductor die. The signal from the lower semiconductor die may be transmitted to the logic circuit L through the conductive bump400and the first interconnection layer M1. The logic circuit L may transmit the signal to the upper semiconductor die through the second interconnection layer M2, the TSV310and the conductive bump400. The logic circuit L may receive a signal in a reverse order.

The first semiconductor die101corresponding to the lowermost semiconductor die in the stacked semiconductor dies100may be connected with a signal block S configured to transmit and receive signals. The fourth semiconductor die107corresponding to the uppermost semiconductor die in the stacked semiconductor dies100might not include the TSV310connected to the second interconnection layer M2.

In order to transmit power between the stacked semiconductor dies100, the semiconductor dies100may include first interconnection layers M1, second interconnection layers M2, and the TSVs320.

The first interconnection layer M1in a semiconductor die100may be positioned on a plane lower than a plane where the second interconnection layer M2may be positioned. The first interconnection layer M1may be connected with a lower semiconductor die through the conductive bump400. The first interconnection layer M1may be connected with the second interconnection layer M2of the lower semiconductor die through a TSV320of the lower semiconductor die. The second interconnection layer M2may contact the conductive bump400so that the second interconnection layer M2may be connected with an upper semiconductor die through the TSV320.

The first semiconductor die101corresponding to the lowermost semiconductor die in the stacked semiconductor dies100may be electrically connected with the first power line210. The first power line210may provide the power to the first semiconductor die101. The fourth semiconductor die107corresponding to the uppermost semiconductor die in the stacked semiconductor dies100may include the second power line230arranged on the upper surface of the fourth semiconductor die107. The second power line230may be formed in most regions of the upper portion of the fourth semiconductor die107. The second power line230may be formed to contact the TSV320of the fourth semiconductor die107. A shape and a size of the second power line320is not limited.

The external connection line500may be directly connected between the first power line210, which may be connected to the first semiconductor die101corresponding to the lowermost semiconductor die, and the second power line230arranged on the upper surface of the fourth semiconductor die107corresponding to the uppermost semiconductor die. For example, the external connection line500may include a wire.

The power may be supplied from the lower semiconductor die to the upper semiconductor die through the conductive bumps400, the first interconnection layers M1, the second interconnection layers M2and the TSVs320formed on and/or under the second interconnection layers M2. Alternatively, the power may be transmitted through the TSVs320, the second interconnection layers M2, the TSVs320, and the first interconnection layers M1.

According to an example embodiment, the power may be directly supplied from the first semiconductor die101corresponding to the lowermost semiconductor die to the fourth semiconductor die107corresponding to the uppermost semiconductor die through the external connection line500.

As the number of stacked semiconductor dies100increases, a delay in getting power to the upper semiconductor die may also increase. However, according to the example embodiment, the first power line210and the second power line230may be directly connected with each other through the external connection line500so that the power may be directly supplied to the uppermost semiconductor die. Thus, the power may be effectively and rapidly supplied to the uppermost semiconductor die in the stacked semiconductor device10-2.

FIG.4is a cross-sectional view illustrating a connection of a stacked semiconductor device10-3along a direction of a semiconductor die in accordance with an example embodiment.

The stacked semiconductor device10-3may include a plurality of vertically stacked semiconductor dies100. In detail, the stacked semiconductor device10-3includes a pair of flip chip bonding dies by connecting a conductive bump400. An upper surface of a first semiconductor die101may be bonded to an upper surface of a semiconductor die103to contact the first interconnection line M1of the first semiconductor die101and the first interconnection line M1of the second semiconductor die103, thereby forming a first pair of flip chip bonding dies101and103. Likewise, an upper surface of a third semiconductor die105may be bonded to an upper surface of a semiconductor die107to contact the first interconnection line M1of the third semiconductor die105and the first interconnection line M1of the fourth semiconductor die107, thereby forming a second pair of flip chip bonding dies105and107.

The upper surface of the first semiconductor die101may be upwardly oriented. In contrast, the lower surface of the first semiconductor die101may be downwardly oriented. The second semiconductor die103may be vertically stacked on the first semiconductor die101. The upper surface of the second semiconductor die103may be downwardly oriented. In contrast, the lower surface of the second semiconductor die103may be upwardly oriented. The first semiconductor die101may connect the second interconnection layer M2through the first power line210and the TSV320. The first interconnection layer M1of the first semiconductor die101may make contact with the first interconnection layer M1of the second semiconductor die103vertically stacked on the first semiconductor die101. The first semiconductor die101and the second semiconductor die103may be bonded to each other by a direct bonding process without a conductive bump. Such a method may be referred to as the flip-chip bonding method. The first interconnection layer M1of the first semiconductor die101may contact the first interconnection layer M1of the second semiconductor die103so that the first semiconductor die101and the second semiconductor die103may electrically connect with each other.

The third semiconductor die105may be vertically stacked on the second semiconductor die103. The lower surface of the third semiconductor die105may be downwardly oriented. In contrast, the upper surface of the third semiconductor die105may be upwardly oriented. Thus, the lower surface of the second semiconductor die103may face the lower surface of the third semiconductor die105. The second semiconductor die103and the third semiconductor die105may be connected with each other through the conductive bump400. The third semiconductor die105may be connected with the second semiconductor die103through the second interconnection layer M2, the TSV320and the conductive bump400. The TSV320and the second interconnection layer M2of the third semiconductor die105may be sequentially located.

The fourth semiconductor die107may be vertically stacked on the third semiconductor die105. The upper surface of the fourth semiconductor die107may be downwardly oriented. In contrast, the lower surface of the fourth semiconductor die107may be upwardly oriented. The third semiconductor die105and the fourth semiconductor die107may be bonded to each other by a direct bonding process without a conductive bump.

The second power line230may be arranged on the upper surface of the fourth semiconductor die107corresponding to the uppermost semiconductor die in the stacked semiconductor device10-3. The external connection line500may be connected between the second power line230on the upper surface of the fourth semiconductor die107and the first power line210on the lower surface of the first semiconductor die101. Thus, the first power line210may be directly connected with the second power line230to rapidly supply the power to the upper semiconductor die in the stacked semiconductor device10-3.

Connection structures between the semiconductor dies may be changed in accordance with directions of the upper surface and the lower surface in the semiconductor dies100. When the semiconductor dies100may be directly bonded to each other without the conductive bump400, a power supply length may be reduced by the conductive bump400to more rapidly supply the power to the semiconductor dies100. Further, by directly bonding the semiconductor dies to each other, the number of conductive bumps400between the semiconductor dies100may be decreased to reduce a size of the stacked semiconductor device10-3.

The directions in which the upper surfaces and the lower surfaces of the semiconductor dies100face is not limited to the arrangement shown inFIG.4. The semiconductor dies100may be connected with each other by corresponding connection structures in accordance with the orientation of the semiconductor dies100. When the upper surfaces of the adjacent semiconductor dies100may face to each other, the adjacent semiconductor dies100may be directly bonded to each other without the conductive bump400. In contrast, the lower surfaces of the adjacent semiconductor dies100and the lower surface and the upper surface of the adjacent semiconductor dies100may face to each other, the adjacent semiconductor dies100may be connected with each other using the conductive bump400. The arrangement of the stacked semiconductor device10-3is not be restricted to the above-described structure ofFIG.4.

FIGS.5to7are cross-sectional views illustrating stacked semiconductor devices having different sizes in accordance with example embodiments.

Stacked semiconductor devices10-4,10-5, and10-6of example embodiments may include stacked semiconductor dies having different sizes.

Referring toFIG.5, the first semiconductor die101corresponding to the lowermost semiconductor die in the stacked semiconductor device10-4may have a size larger than a size of other semiconductor dies103,105, and107stacked on the first semiconductor die101.

The first semiconductor die101corresponding to the lowermost semiconductor die may be connected to the first power line210. The fourth semiconductor die107corresponding to the uppermost semiconductor die may include the second power line230. A pad600may be arranged on the upper surface of the first semiconductor die101. The second to fourth semiconductor dies103,105, and107may be stacked on the first semiconductor die101so as to leave the pad600of the first semiconductor die101exposed. The pad600may be connected to the first power line210. The pad600may be connected to the second power line230of the fourth semiconductor die107, which may correspond to the uppermost semiconductor die in the stacked semiconductor device10-4, through the external connection line500.

The external connection line500may be located a range of the width of the first semiconductor die101. The external connection line500may be connected between the pad600on the first semiconductor die101and the second power line230.

Through this, the external connection line500connecting the first power line210and the second power line230is not located outside the width range of the first semiconductor die101. Accordingly, the size of the stacked semiconductor device10-4including the semiconductor dies100having different sizes may be reduced.

Referring toFIG.6, the fourth semiconductor die107corresponding to the uppermost semiconductor die in the stacked semiconductor device10-5may have a size larger than a size of other semiconductor dies101,103, and105stacked under the fourth semiconductor die107.

The fourth semiconductor die107corresponding to the uppermost semiconductor die may include the second power line230. The first semiconductor die101corresponding to the lowermost semiconductor die may be connected to the first power line210. A pad600may be arranged on the lower surface of the fourth semiconductor die107. The pad600may be positioned in a region of the fourth semiconductor die107so as not to overlap the third semiconductor die105. The pad600may be connected to the second power line230. The pad600may be connected to the first power line210, which may be connected to the first semiconductor die101corresponding to the lowermost semiconductor die in the stacked semiconductor device10-5, through the external connection line500.

The external connection line500may be located a range of the width of the fourth semiconductor die107. The external connection line500may be connected between the pad600under the fourth semiconductor die107and the first power line210.

Through this, the external connection line500connecting the first power line210and the second power line230is not located outside the width range of the fourth semiconductor die107. Accordingly, the size of the stacked semiconductor device10-5including the semiconductor dies100having different sizes may be reduced.

Referring toFIG.7, the first semiconductor die101corresponding to the lowermost semiconductor die and the fourth semiconductor die107corresponding to the uppermost semiconductor die in the stacked semiconductor device10-6may have a size larger than a size of the second and third semiconductor dies103and105.

The first semiconductor die101corresponding to the lowermost semiconductor die may be connected to the first power line210. A first pad601may be arranged on the upper surface of the first semiconductor die101.

The second semiconductor die103and the third semiconductor die105are stacked on the first semiconductor die101in such a way to leave the first pad601exposed. Although not shown in theFIG.7, the first pad601may be electrically connected to the first power line210through a conductive interconnecting member, such as the TSVs310and/or320, the first and second interconnection lines M1and/or M2, which are formed in the first semiconductor die101.

The fourth semiconductor die107corresponding to the uppermost semiconductor die may include a first surface and a second surface.

A second pad603may be formed on the first surface of the fourth semiconductor die107. The second power line230may be formed on the second surface of the fourth semiconductor die107. Although not shown in theFIG.7, the second pad603may be electrically connected to the second power line230through a conductive interconnecting member, such as the TSVs310and/or320, the first and second interconnection lines M1and/or M2, which are formed in the fourth semiconductor die107.

The fourth semiconductor die107may be stacked on the third semiconductor die105. The fourth semiconductor die107may be stacked so that the second pad603of the fourth semiconductor die107and the first pad601of the first semiconductor die101face each other.

The first pad601of the first semiconductor die101and the second pad603of the fourth semiconductor die107may be connected with each other through the external connection line500. The external connection line500is not located outside the width range of the first semiconductor die101or the fourth semiconductor die107. The external connection line500may be located within the width range of the first semiconductor die101or the fourth semiconductor107. Accordingly, the size of the stacked semiconductor device10-6including the semiconductor dies100having different sizes may be reduced.

Although not shown in theFIG.7, the first power line210and the second power line230may be further connected by the external connection line500(refer toFIG.1)

In example embodiments, the semiconductor dies100in the stacked semiconductor devices10-4,10-5, and10-6inFIGS.5to7may have uniform directions, but are not limited thereto. As indicated above with reference toFIG.4, the directions of the semiconductor dies100may be differently arranged. The semiconductor dies100may be directly bonded to each other, or connected to each other using the conductive bump400in accordance with the directions of the semiconductor dies100.

In example embodiments, each of the semiconductor dies100may include a power generator. The power generator may integrate the power supplied from the first power line210and the power supplied from the second power line230with each other to supply stable power to the semiconductor die. The power generator may supply the stable power supplied from the first power line210and the second power line230to the logic circuit L to transmit the signal.

Although not shown in the drawings, the plurality of stacked semiconductor dies100may be encapsulated by a mold structure to form a package.

According to example embodiments, the stacked semiconductor devices10-1,10-2,10-3,10-4,10-5, and10-6may improve the problems of supplied power generated by numerous numbers of the semiconductor dies100in the stacked semiconductor devices10-1,10-2,10-3,10-4,10-5and10-6.

Stacked semiconductor devices may further include the second power line230. The second power line230may be directly connected between the external connection line and the uppermost semiconductor die having the weakness of the power supply to rapidly supply the power to the semiconductor dies. Further, when the semiconductor dies have different sizes, the pad may be formed at the upper surface or the lower surface of the semiconductor the having the large size. Thus, the first power line and the second power line may be directly connected with each other to prevent the size of the stacked semiconductor device from being enlarged.

The above described embodiments of the present teachings are intended to illustrate and not to limit the present teachings. Various alternatives and equivalents are possible. The present teachings are not limited by the embodiments described herein. Nor are the present teachings limited to any specific type of semiconductor device. Additions, subtractions, or modifications are possible in view of the present disclosure and are intended to fall within the scope of the appended claims.