Patent ID: 12211460

DETAILED DESCRIPTION OF THE EMBODIMENTS

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts should fall within the protection scope of the present disclosure.

Terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. Unless otherwise specified in the context, words, such as “a”, “the”, and “this”, in a singular form in the embodiments of the present disclosure and the appended claims include plural forms.

Electronic paper products have certain requirements for a storage capacitor of a pixel. If the storage capacitor is too small, its retention ability within one frame is insufficient, leading to insufficient driving of electrophoretic particles and causing uneven display. One of the main factors affecting the capacitance value of the storage capacitor in electronic paper products is the overlapping area of two plates of the storage capacitor. The overlapping area of the two plates directly affects the pixel size. In addition, electronic paper products require high voltages to drive the electrophoretic particles, so the transistor in the driver circuit needs to have a certain width-to-length ratio. This is one of the limits on the reduction in pixel sizes in electronic paper products.

Embodiments of the present disclosure provide a driver board. Pixel electrodes in a driver circuit share one storage capacitor, which allows for the reduction of the size of the pixel electrode while maintaining a sufficiently large capacitance value for the storage capacitor. This ensures efficient driving of electrophoretic particles and prevents uneven display when applied in electronic paper products. In addition, since the pixel electrodes share the same storage capacitor, each pixel electrode has sufficient space for arranging the pixel switch, therefore meeting the size requirement of the pixel switch. The pixel switch can withstand a high voltage, so the off-state leakage current of the pixel switch is reduced and the voltage on the pixel electrode is stabilized. According to the present disclosure, the pixel size can be miniaturized, meeting the requirements of color electronic paper products on Pixels Per Inch (PPI).

FIG.1is a partial schematic diagram of a driver board according to an embodiment of the present disclosure, andFIG.2is a schematic circuit diagram of a driver circuit in the driver board according to an embodiment of the present disclosure.

As shown inFIG.1, the driver board includes a plurality of driver circuits10. One or more of the driver circuits10each include N pixel electrodes11and one storage capacitor12. N is a positive integer and N≥2. The N pixel electrodes11in the driver circuit10share one storage capacitor12. The storage capacitor12includes a reference electrode121and a counter electrode122that are overlapped with each other. InFIG.1, N=3 is used for illustration.

Referring toFIG.2, each driver circuit10further includes a data switch14and N pixel switches13, and a control terminal of each pixel switch13receives a gating signal. The gating signal is provided by a gating signal line40. Control terminals of the three pixel switches13shown inFIG.2are respectively connected to a first gating signal line40-1, a second gating signal line40-2, and a third gating signal line40-3. A first terminal of each pixel switch13is connected to the counter electrode122of the storage capacitor12, and a second terminal of each pixel switch13is connected to one of the pixel electrodes11. The reference electrode121of the storage capacitor12may be grounded. That is, the N pixel electrodes11are connected to the storage capacitor12via the pixel switches13respectively, and the N pixel electrodes11in the driver circuit10share one storage capacitor12.

The driver board includes data lines20and data control lines30. The data lines20are connected to the counter electrodes122via the data switches14. Control terminals of the data switches14are connected to the data control lines30.

InFIG.1, both the pixel switch13and the data switch14are illustrated as single-gate transistors. In some embodiments, at least one of the pixel switch13and the data switch14is a double-gate transistor. This can reduce the off-state leakage current of the transistor. For example, the pixel switch13is a double-gate transistor, which reduces the off-state leakage current of the pixel switch13and improves the voltage stability on the pixel electrode. In addition, the transistor types of the pixel switch13and the data switch14are not limited by the illustrated embodiments of the present disclosure, and the pixel switch13and the data switch14each may be an N-type transistor or a P-type transistor.

In the driver board provided in embodiments of the present disclosure, the driver circuit10includes N pixel electrodes11, and the N pixel electrodes11in the driver circuit10share one storage capacitor12, such that the quantity of storage capacitors12in the driver board is reduced when the quantity of pixel electrodes11is kept unchanged. Even when the size of the pixel electrode11is reduced, there is sufficient space to arrange a large-sized storage capacitor12, ensuring that the capacitance value of the storage capacitor12is sufficiently large. This allows meeting the requirements on the capacitance value of the storage capacitor12when applied in electronic paper products. The pixel electrodes11can be fully charged using the storage capacitor, thereby avoiding voltage drops of the pixel electrodes11caused by leakage or gate-source capacitive coupling of the transistor switch. This ensures efficient driving of electrophoretic particles and prevents uneven display. In addition, since the N pixel electrodes11share the same storage capacitor12, each pixel electrode11has sufficient space to accommodate the pixel switch13. This ensures that the pixel switch13can meet the size requirements. Therefore, the pixel switch can withstand a high voltage, the off-state leakage current of the pixel switch is reduced, and the voltage on the pixel electrode is stabilized. When the driver board provided in the embodiments of the present disclosure is applied to electronic paper products, the pixel size can be miniaturized, especially meeting the requirements of color electronic paper products on PPI.

In some embodiments, the driver board may be used as the driver backplane of the electronic paper product. The pixel electrode11on the driver board and a common electrode on a counter substrate form an electric field to drive electrophoretic particles to move. Each pixel in the electronic paper product includes one pixel electrode11.

In some embodiments, the display panel adopts the microcapsule electrophoretic display technology.FIG.3is a schematic diagram of a display panel according to an embodiment of the present disclosure. As shown inFIG.3, the display panel includes a driver board01, an electrophoretic film02, and a counter substrate03. The electrophoretic film02includes microcapsules021, in each of which electrophoretic particles022and electrophoretic liquid are provided. The electrophoretic film02is a display medium between the driver board01and the counter substrate03. The counter substrate03further includes a common electrode031, and the common electrode031overlaps the pixel electrode11in a thickness direction e of the display panel. The structure of the driver board01inFIG.3is shown in merely a simplified manner. The driver board01, the electrophoretic film02, and the counter substrate03are separately fabricated. Then, the driver board01and the electrophoretic film02are bonded using an adhesive layer, and the electrophoretic film02and the counter substrate03are also bonded using an adhesive layer. Alternatively, the electrophoretic film02may be fabricated on the counter substrate03, and then the electrophoretic film02and the counter substrate03as a whole are bonded with the driver board01. The common electrode031on the counter substrate03may be electrically connected to the driver board01, such that the driver board01can supply a driving voltage to the common electrode031.

In other embodiments, the display panel adopts the microcup electrophoretic display technology.FIG.4is a schematic diagram of another display panel according to an embodiment of the present disclosure. As shown inFIG.4, the display panel includes a driver board01, an electrophoretic film02, and a counter substrate03. The electrophoretic film02includes a plurality of microcups023, each including electrophoretic particles022and electrophoretic liquid. The electrophoretic film02is a display medium between the driver board01and the counter substrate03.FIG.4schematically shows a common electrode031on the counter substrate03and pixel electrodes11on the driver board01. In this embodiment, the electrophoretic film02may be separately fabricated, and then bonded to the driver board01and the counter substrate03separately using adhesive layers. Alternatively, the electrophoretic film02may be fabricated on the counter substrate03, and then the electrophoretic film02and the counter substrate03as a whole are bonded with the driver board01. The common electrode031on the counter substrate03may be electrically connected to the driver board01, such that the driver board01can supply a driving voltage to the common electrode031.

In other embodiments, the display panel adopts the cofferdam electrophoretic display technology.FIG.5is a schematic diagram of another display panel according to an embodiment of the present disclosure. As shown inFIG.5, the display panel includes a driver board01and a counter substrate03. After the driver circuits are fabricated on the driver board01, a plurality of cofferdam structures024are fabricated on the driver circuits. The cofferdam structures024surround the pixel regions respectively. The cofferdam structures024define micro cavities. Electrophoretic particles022and electrophoretic liquid are arranged in the cofferdam structures024, and then encapsulated. The cofferdam structures024, the electrophoretic particles022, and the electrophoretic liquid constitute a display medium layer04between the driver board01and the counter substrate03.FIG.5schematically shows a substrate00, a pixel switch13, and a pixel electrode11. The pixel switch13includes a gate g, an active layer W, a source s, and a drain d, and the pixel electrode11is electrically connected to the drain d.FIG.5shows the pixel switch13as a bottom-gate transistor, and the pixel switch13may alternatively be a top-gate transistor. In a thickness direction e of the display panel, the common electrode031on the counter substrate03overlaps with the pixel electrode11on the driver board01.

In some embodiments, the microcapsule electrophoretic display technology is used as an example.FIG.6is a schematic diagram of another display panel according to an embodiment of the present disclosure. As shown inFIG.6, the counter substrate03further includes a color filter layer including at least three color filter units032with different colors. In the thickness direction e of the display panel, the color filter unit032overlaps with the pixel electrode11. With the color filter layer, color display is achieved. Optionally, the N pixel electrodes11overlap with N color filter units in the driver circuit, and the N color filter units have different colors.

The driver board provided in embodiments of the present disclosure is used for driving the display panel to display. Displaying of an image includes N refresh cycles, and data voltages are written into the N pixel electrodes11in the N refresh cycles respectively. In each refresh cycle, the data switch14is turned on to connect the data line20to the counter electrode122, the pixel switch13corresponding to the refresh cycle is turned on to connect the pixel electrode11corresponding to the refresh cycle to the counter electrode122. The data line20writes the data voltage corresponding to the refresh cycle into the pixel electrode11corresponding to the refresh cycle and stores the data voltage in the storage capacitor12. During the period when the pixel switch13is turned on, the storage capacitor12can be used to maintain the voltage on the pixel electrode11. Because the capacitance value of the storage capacitor12is large enough, the pixel electrode11can be fully charged, thereby avoiding voltage drop of the pixel electrode11caused by current leakage and gate-source capacitive coupling. This ensures efficient driving of electrophoretic particles. For each driver circuit10, during each refresh cycle, the data voltage is written into to the corresponding pixel electrode11by turning on the data switch14and the corresponding pixel switch13. In the N refresh cycles, data voltages are respectively written into the N pixel electrodes11in the driver circuit10. All the N pixel electrodes11participate in the display process, and the driver board performs driving of display of a complete image through N refresh cycles.

In some embodiments, the data voltage ranges between −15V and 15V.

In an embodiment, for example, N=3. Referring toFIG.6, the driver board is applied to a display panel, each driver circuit10includes three pixel electrodes11, and each pixel electrode11overlaps with one color filter unit032. The colors of the three color filter units032overlapping with the three pixel electrodes11in the driver circuit are different, for example, the three pixel electrodes11respectively overlap with red, green, and blue color filter units032. Each pixel in the display panel includes the color filter unit032, the pixel electrode11, and the pixel switch13. In this case, the red pixel in the display panel includes the red color filter unit and the pixel electrode11overlapping with the red color filter unit, the green pixel includes the green color filter unit and the pixel electrode11overlapping with the green color filter unit, and the blue pixel includes the blue color filter unit and the pixel electrode11overlapping with the blue color filter unit. The display panel may display an image in the following ways.

The display panel displays an image through the driving of three refresh cycles, and the red, green, and blue pixels are respectively driven in the three refresh cycles.

FIG.7is a drive timing diagram according to an embodiment of the present disclosure. Description is made with reference to the circuit diagram of the driver circuit shown inFIG.2. InFIG.7, the timing30represents the signal timing of a data control line30in the driver board. In an embodiment, the pixel switch13connected to the first gating signal line40-1is included the red pixel, the pixel switch13connected to the second gating signal line40-2is included the green pixel, and the pixel switch13connected to the third gating signal line40-3is included the blue pixel. The data control line30controls the data switch14, and the data control line30provides an enable signal to turn on the data switch14. As shown inFIG.7, the three refresh cycles include a first refresh cycle T1, a second refresh cycle T2, and a third refresh cycle T3.

In the first refresh cycle T1, the pixel switch13in the red pixel is turned on to connect the pixel electrode11in the red pixel to the counter electrode122, and the data switch14is turned on to connect the data line20to the counter electrode122. The data line20writes a data voltage corresponding to the red pixel into the pixel electrode11. During the period when the pixel switch13is turned on, the storage capacitor12makes the voltage on the pixel electrode11stable, avoiding voltage drop on the pixel electrode11. In the red pixel, an electric field is formed between the pixel electrode11and the common electrode031to control the electrophoretic particles in the red pixel to move to the desired position, so as to realize grayscale display of the red pixel. Due to the bi-stable characteristics of the electrophoretic particles, after the pixel switch13is turned off, the electrophoretic particles remain at the current position and do not move, such that the red pixel maintains its display state. In this refresh cycle, all the driver circuits10work and charge the pixel electrodes11of all the red pixels, such that all the red pixels display their desired grayscales. And the red pixels maintain the display state after the first refresh cycle.

In the second refresh cycle T2, the pixel switch13in the green pixel is turned on to connect the pixel electrode11in the green pixel to the counter electrode122, and the data switch14is turned on to connect the data line20to the counter electrode122. The data line20writes a data voltage corresponding to the green pixel into the pixel electrode11in the green pixel. During the period when the pixel switch13is turned on, the storage capacitor12makes the voltage on the pixel electrode11stable. In the green pixel, an electric field is formed between the pixel electrode11and the common electrode031to control the electrophoretic particles in the green pixel to move to the desired position, so as to realize grayscale display of the green pixel. After the pixel switch13is turned off, the green pixel maintains its display state. In this refresh cycle, all the driver circuits10work and charge the pixel electrodes11of all the green pixels, such that all the green pixels display their desired grayscales. The green pixel maintains the display state after the second refresh cycle, and the red pixel maintains the display state during and after the second refresh cycle.

In the third refresh cycle T3, the pixel switch13in the blue pixel is turned on to connect the pixel electrode11in the blue pixel to the counter electrode122, and the data switch14is turned on to connect the data line20to the counter electrode122. The data line20writes a data voltage corresponding to the blue pixel into the pixel electrode11in the blue pixel. During the period when the pixel switch13is turned on, the storage capacitor12makes the voltage on the pixel electrode11stable. In the blue pixel, an electric field is formed between the pixel electrode11and the common electrode031to control the electrophoretic particles in the blue pixel to move to the desired position, so as to realize grayscale display of the blue pixel. After the pixel switch13is turned off, the blue pixel maintains its display state. In this refresh cycle, all the driver circuits10work and charge the pixel electrodes11of all the blue pixels, such that all the blue pixels display their desired grayscales. In the third refresh cycle, both the green pixel and the red pixel maintain the display state. After the third refresh cycle, the red, green, and blue pixels in the display panel all maintain the display state, and the three color pixels cooperate to display the image.

FIG.7illustrates an example embodiment that the first refresh cycle is for the red pixel, the second refresh cycle is for the green pixel, and the third refresh cycle is for the blue pixel. The embodiments of the present disclosure do not impose any limitations on the driving and display sequence of the red, green, and blue pixels within the three refresh cycles.

In the embodiments of the present disclosure, the N pixel electrodes11in the driver circuit10share one storage capacitor12. With reference to the timing diagram ofFIG.7, it can be understood that in each refresh cycle, the data switch14is turned on once and the corresponding pixel switch13is turned on once, such that the data line20writes the data voltage to the corresponding pixel electrode11, and the storage capacitor12is used to improve the voltage stability on the pixel electrode11and ensure full charging of the pixel electrode11. When the driver board is applied to a display panel, after the pixel electrode11is charged, the pixel electrode11and the common electrode form an electric field to drive the electrophoretic particles to move, and the electrophoretic particles move to the desired position for displaying the pixel grayscale. When the pixel switch13connected to the pixel, electrode11is turned off, the electrophoretic particles still maintain their desired positions, and the grayscale displayed by the corresponding pixel remains unchanged. However, in some instances, there may be residual charges on the pixel electrode11even after the pixel switch13is turned off. These residual charges on the pixel electrode11may form an electric field with the common electrode (because the pixels in the display panel share the common electrode, and there is a continuous voltage signal on the common electrode during the display process). Consequently, this causes some electrophoretic particles in the pixel to be out of their desired positions, leading to disordered movement of some electrophoretic particles and resulting in abnormal pixel display.

In the embodiments of the present disclosure, to avoid the disordered movement of the electrophoretic particles within the pixel during image display, a reset phase is added in the refresh cycle, and the drive timing is further improved.FIG.8is a schematic diagram of another drive timing diagram according to an embodiment of the present disclosure. Description is made with reference to the circuit diagram of the driver circuit shown inFIG.2, for example, N=3. As shown inFIG.8, in some embodiments, each refresh cycle includes a data writing phase t-1 and a reset phase t-2. In the data writing phase t-1, the data control line30provides an enable signal to turn on the data switch14, and the data line20writes the data voltage into the pixel electrode11. In the reset phase t-2, the data control line30provides the enable signal again to turn on the data switch14, and the data line20writes a reset voltage into the pixel electrode11. In each refresh cycle, the reset phase t-2 is subsequent to the data writing phase t-1. In this embodiment, the reset phase t-2 is added in the refresh cycle, and the pixel electrode11is reset by the reset voltage, to ensure that there is no voltage difference between the pixel electrode11and the common electrode after the refresh cycle ends and the pixel switch13is turned off, such that the electrophoretic particles within the pixel maintain at the position where they arrive when the pixel electrode11is charged. This ensures the target grayscale display and prevents disordered movement of the electrophoretic particles, thereby avoiding abnormal pixel display.

In some embodiments, the reset voltage is equal to the common voltage set in the display panel, for example, the reset voltage is 0 V.

In some embodiments, as shown inFIG.1, the driver board further includes data control lines30, the control terminal of the data switch14is connected to the corresponding data control line30, the first terminal of the data switch14is connected to the corresponding data line20, and the second terminal of the data switch14is connected to the counter electrode122. The plurality of driver circuits10are arranged in an array including circuit rows10H and circuit columns10L. The circuit rows10H extend along a first direction x and are arranged along a second direction y. The driver circuits10in the same circuit row10H are arranged along the first direction x. The circuit columns10L extend along the second direction y and are arranged along the first direction x. The driver circuits10in the same circuit column10L are arranged along the second direction y. The first direction x crosses the second direction y. For example, the first direction x is perpendicular to the second direction y. Each data control line30is connected to the data switches14in one circuit row10H, and each data line20is connected to the data switches14in one circuit column10L. In this embodiment, the data switches14in one circuit row10H are controlled by one data control line30, the data control line30is equivalent to a row selecting line, and one data line20supplies data voltages to the driver circuits10in one circuit column10L. The cooperation of the data control lines30and the data lines20can realize row-by-row drive of the plurality of circuit rows10H to complete a refresh cycle.

FIG.9is a schematic circuit diagram of another driver board according to an embodiment of the present disclosure. As shown inFIG.9, in some embodiments, the driver board further includes gating line groups40Z, each gating line group40Z includes N gating signal lines40, and control terminals of N pixel switches13in the driver circuit are respectively connected to the N gating signal lines40. For example, N=3. As shown inFIG.9, the plurality of driver circuits10are arranged in circuit rows10H along the first direction x. The driver circuits10in each circuit row10H share one gating line group40Z. The gating line group40Z includes a first gating signal line40-1, a second gating signal line40-2, and a third gating signal line40-3. In the example embodiment, N=3, the driver circuit10includes three pixel switches13, and control terminals of the three pixel switches13are respectively connected to the three gating signal lines40in the gating line group40Z corresponding to the circuit row where the driver circuit10is located. One gating line group40Z drives one circuit row10H, which can simplify the driving method of the circuit row10H and simplify the layout in the driver board.

As shown inFIG.9, the driver board includes a plurality of circuit rows10H and a plurality of data control lines30, and the data control lines30are arranged along the second direction y.FIG.9illustrates an example embodiment in which three circuit rows10H, and a first data control line30-1, a second data control line30-2, and a third data control line30-3corresponding to the three circuit rows10H, respectively. The data control lines30are connected to a row driving circuit60, and the row driving circuit60provides enable signals to the data control lines30row by row in a refresh cycle. The row driving circuit60may be, for example, a shift driver circuit fabricated on the driver board or a driver chip bonded on the driver board. The data line20is electrically connected to a data driving circuit50, which may be a driver chip or a flexible printed circuit board bonded on the driver board.

In each refresh cycle, the data control lines30sequentially output enable signals, and the data switches14connected to one data control line30are simultaneously turned on by the enable signal on the one data control line30. The process of driving the circuit rows10H row by row using the data control lines30is completed in one refresh cycle. With reference toFIG.2andFIG.7, it can be understood that for one driver circuit10in one refresh cycle, the data switch14of the driver circuit10is turned on once to write the data voltage to one pixel electrode11of the driver circuit10. The process of writing data voltages to the N pixel electrodes11in the driver circuit10is completed by N refresh cycles.

In some embodiments, the N gating signal lines40in the gating line group40Z are a first gating signal line40-1, a second gating signal line40-2, . . . , and an Nthgating signal line40-N. The driver board includes a plurality of gating line groups40Z, and a plurality of ithgating signal lines40-iin the plurality of gating line groups40Z are electrically connected with each other, where i is a positive integer, and 1≤i≤N.

FIG.10is a schematic circuit diagram of another driver board according to an embodiment of the present disclosure. As shown inFIG.10, N=3, and the gating line group40Z includes a first gating signal line40-1, a second gating signal line40-2, and a third gating signal line40-3. In these gating line groups40Z, a plurality of first gating signal lines40-1are electrically connected with each other, a plurality of second gating signal lines40-2are electrically connected with each other, and a plurality of third gating signal lines40-3are electrically connected with each other. The gating line groups40Z can share the gating signal in one refresh cycle, which can reduce the quantity of gating signal required for the driver board, thereby reducing the quantity of pins of the driver chip. This is beneficial to reducing the cost.

In some embodiments, the N gating signal lines40provide enable signals in the N refresh cycles respectively. A duration of each refresh cycle is t, and the duration of the enable signal on each gating signal line40is t. In each refresh cycle, the data control lines30provide enable signals row by row, and the turn-on duration of the data switch14is far shorter than the refresh cycle t. The gating signal line40controls the turn-on duration of the pixel switch13to be equal to the duration t of the refresh cycle. In the refresh cycle, the pixel electrode11is still electrically connected to the storage capacitor12after the data switch14is turned off, and the storage capacitor12can maintain the voltage on the pixel electrode11to ensure that the pixel electrode11is fully charged. When the driver board is applied to electronic paper products, the electrophoretic particles can be fully driven by the fully charged pixel electrode11, thereby avoiding uneven display.

FIG.11is another drive timing diagram according to an embodiment of the present disclosure. For example, N=3, a display period of an image includes three refresh cycles: T1, T2, and T3. The driving method of the driver board in the refresh cycles is described with reference toFIG.10. The duration of one enable signal provided by the gating signal line40is the same as the duration of refresh cycle. Take the first refresh cycle T1as an example. In the first refresh cycle T1, the first gating signal line40-1provides the enable signal to turn on the pixel switch13connected to the first gating signal line40-1, and the duration of the enable signal provided by the first gating signal line40-1is the same as the duration of the first refresh cycle T1. The data control lines30provide enable signals row by row, and one data control line30controls the data switches14in one circuit row10H to be turned on simultaneously. Since the gating line groups40Z share the gating signal, the pixel switches13connected to the first gating signal lines40-1in all circuit rows10H are all in the turned-on state. The data voltage is written to the pixel electrode11by the data line20when the data switch14is turned on, and the voltage on the pixel electrode11is maintained by the storage capacitor12after the data switch14is turned off. During the period when the first gating signal lines40-1provide the gating signal once, the data control lines30provide the enable signals row by row, and data voltages are written row by row through the data line20to the pixel electrodes11in the circuit rows10H. For one driver circuit10, only one pixel switch13is turned on in one refresh cycle. Then after the data switch14is turned off, the storage capacitor12is still electrically connected to the pixel electrode11, and the voltage on the pixel electrode11is maintained by the storage capacitor12to ensure that the pixel electrode11is fully charged.

In this embodiment of the present disclosure, the refresh cycle includes a data writing phase. In the data writing phase, the data switch14is turned on, and the data voltage is written to the pixel electrode11through the data line20. The period during which the gating signal line40provides the enable signal covers the data writing phase. The data writing phase is a phase, in which data control lines30provide enable signals row by row, in the refresh cycle. The duration of one enable signal provided by the gating signal line40is the same as the duration of the refresh cycle.FIG.11illustrates an example embodiment in which three gating signal lines sequentially providing the enable signal in one refresh cycle. As shown inFIG.11, in one refresh cycle, the period in which the gating signal line40provides the enable signal covers the data writing phase, such that a plurality of circuit rows10H can share the gating signal, and the data writing process for the plurality of circuit rows10H is completed in the period when the gating signal lines40provide the enable signal in each refresh cycle.

FIG.12is a schematic diagram of another drive timing diagram according to an embodiment of the present disclosure. For example, N=3. The driver board provided inFIG.10may be driven with the timing shown inFIG.12. As shown inFIG.12, display of a frame of image includes three refresh cycles, namely, a first refresh cycle T1, a second refresh cycle T2, and a third refresh cycle T3. Each refresh cycle includes a data writing phase t-1 and a reset phase t-2. In the data writing phase t-1, a plurality of data control lines30sequentially output enable signals, and data lines20write data voltages into corresponding pixel electrodes11. In the reset phase t-2, the data control lines30simultaneously output the enable signals, data switches14are turned on, and the data lines20write a reset voltage into the corresponding pixel electrodes11. As shown inFIG.12, the first data control line30-1, the second data control line30-2, and the third data control line30-3sequentially output the enable signal in the data writing phase t-1, whereas the first data control line30-1, the second data control line30-2, and the third data control line30-3simultaneously output the enable signal in the reset phase t-2. In this embodiment, the reset phase t-2 is added in the refresh cycle. After the data writing phase t-1, the pixel electrode11is reset by the reset voltage, so as to ensure that there is no voltage difference between the pixel electrode11and the common electrode after the refresh cycle ends and the pixel switch13is turned off. The electrophoretic particles in the pixel can maintain the position where the electrophoretic particles arrive when the pixel electrode11is charged, thereby keeping the target display grayscale of the pixel and avoiding abnormal pixel display caused by the chaotic movement of the electrophoretic particles. In addition, in the reset phase t-2, the plurality of data control lines30simultaneously output the enable signal, that is, the pixel electrodes11in the circuit rows10H are reset at the same time in the refresh cycle, such that the duration of the reset phase t-2 in the refresh cycle is relatively short, and the added reset phase t-2 has little impact on the refresh cycle, thereby reducing the impact on the display refresh rate.

In addition, in the refresh cycle, the duration of the enable signal provided by the gating signal line40covers the data writing phase t-1 and the reset phase t-2. For example, as shown inFIG.12, in the first refresh cycle T1, the first gating signal line40-1provides the enable signal, and the duration of the enable signal provided by the first gating signal line40-1covers the data writing phase t-1 and the reset phase t-2. Therefore, the plurality of circuit rows10H can share the gating signal. In one refresh cycle, the data writing process for the plurality of circuit rows10H and the resetting process for the pixel electrodes11are completed in the period in which the gating signal lines40provide the enable signal. During application, after the data voltage is written into the pixel electrode11, an electric field is formed between the pixel electrode11and the common electrode to control the electrophoretic particles in the pixel to move to the target position, and then the pixel electrode11is reset by the reset voltage. When the reset voltage is equal to the voltage of the common electrode, the position of the electrophoretic particles in the pixel does not change, to prevent abnormal pixel display caused by chaotic movement of the electrophoretic particles after the refresh cycle.

In some embodiments, takingFIG.1as an example,FIG.1is a top view of a driver board. It can be understood that the top view direction is parallel to the thickness direction of the driver board.FIG.1shows the driver circuit10including three pixel electrodes11and one storage capacitor12. In the thickness direction of the driver board, the pixel electrode11overlaps with the pixel switch13connected to the pixel electrode11, and the storage capacitor12partially overlaps with the three pixel electrodes11. When applied to electronic paper products, the pixel electrode11need to be opposed to the common electrode to form an electric field. Therefore, the pixel electrodes11of the driver board are arranged in a plane. The storage capacitor12partially overlaps with the N pixel electrodes11respectively, that is, the storage capacitor12is disposed in the space in which the N pixel electrodes11are arranged, such that the space for arranging the storage capacitor12is larger, thereby meeting the capacitance requirements of electronic paper products on the storage capacitor12. In addition, the pixel switch13overlaps with the pixel electrode11. This ensures that the pixel switch13can meet the size requirements in electronic paper products, the pixel switch13can withstand a high voltage, and the off-state leakage current is reduced. This can stabilize the voltage on the pixel electrode11.

In some embodiments, the N pixel electrodes11in the driver circuit10are arranged along the first direction x, and electrodes of the storage capacitor12extend along the first direction x. For example, N=3. As shown inFIG.1, three pixel electrodes11in the driver circuit10are arranged along the first direction x, and both the reference electrode121and the counter electrode122of the storage capacitor12extend along the first direction x, such that the electrodes of the storage capacitor12can have a longer length in the first direction x. This can increase the electrode area and capacitance value of the storage capacitor12and meet the requirements on the capacitance value of the storage capacitor12.

As shown inFIG.1, gating signal lines40, data control lines30, and data lines20are provided in the driver board. The gating signal line40and the data control line30extend along the first direction x, and the data line20extends along the second direction y. The data line20and the data control line30cross each other to define the region of the driver circuit10. A part of the gating signal line40is reused as the gate of the pixel switch13, and the pixel switch13overlaps with the pixel electrode11, such that the gating signal line40partially overlaps with the pixel electrode11.FIG.1further shows a first conductive via V1through which the pixel switch13is connected to the pixel electrode11.

FIG.13is a schematic diagram of another driver board according to an embodiment of the present disclosure.FIG.14is a schematic circuit diagram of a driver circuit inFIG.13.FIG.13schematically shows four driver circuits10in the driver board. As shown inFIG.13, N=4, and four pixel electrodes11in the driver circuit10are arranged in two rows and two columns. Gating signal lines40and data control lines30extending in the first direction x, and data lines20extending in the second direction y are arranged in the driver board. Four pixel electrodes11in the driver circuit10are connected to the storage capacitor12through the pixel switches13respectively, the data line20is connected to the storage capacitor12through the data switch14, and the pixel switches13are controlled by the gating signal lines40respectively. In the driver board, the plurality of driver circuits10are arranged in circuit rows10H along the first direction x and in circuit columns10L along the second direction y.

When N=4, one circuit row10H is driven by four gating signal lines40, and four gating signal lines40form a gating line group40Z. With reference toFIG.14, control terminals of four pixel switches13in the driver circuit10are respectively connected to a first gating signal line40-1, a second gating signal line40-2, a third gating signal line40-3, and a fourth gating signal line40-4in the gating line group40Z.

In this embodiment, displaying of an image includes four refresh cycles, and data voltages are written to the four pixel electrodes11in the four refresh cycles respectively. In each refresh cycle, the data switch14is turned on to connect the data line20to the counter electrode122, one of the pixel switches13is turned on to connect the corresponding pixel electrode11to the counter electrode122, and the data line20writes the data voltage into the corresponding pixel electrode11. During the period in which the pixel switch13is turned on, the storage capacitor12maintains the voltage on the pixel electrode11. In the four refresh cycles, data voltages are written to the four pixel electrodes11in the driver circuit10respectively. All the four pixel electrodes11participate in the display process, and the driver board performs driving of display of a complete image through the four refresh cycles.

In the embodiment ofFIG.13, the plurality of gating line groups40Z share the gating signal, that is, a plurality of ithgating signal lines40-iin the plurality of gating line groups40Z are electrically connected with each other, where i is a positive integer, and 1≤i≤N. The driving mode in the timing diagram ofFIG.11can be applied to the driver board provided in the embodiment ofFIG.13. Displaying of an image includes four refresh cycles. For example, in the first refresh cycle, the first gating signal line40-1provides an enable signal to turn on the connected pixel switch13. The duration of the enable signal of the first gating signal line40-1is the same as the duration of the first refresh cycle. Since the gating line groups40Z share the gating signal, the pixel switches13connected to the first gating signal lines40-1in all circuit rows10H are all in the turned-on state. When the first gating signal lines40-1provide the enable signal, the data control lines30provide the enable signals one by one. One data control line30controls the data switches14in one circuit row10H to be simultaneously turned on. When the data switches14are turned on, the data voltages are written to the pixel electrodes11by the data lines20, and the storage capacitors12maintains the voltages on the pixel electrodes11after the data switches14are turned off. During the period when the first gating signal lines40-1provide the enable signal once, the data control lines30provide the enable signals one by one, and data voltages are written row by row through the data line20to the pixel electrodes11in the circuit rows10H. After four refresh cycles, data voltages are written to the four pixel electrodes11in all driver circuits10in the driver board.

During the period when the gating signal lines provide the enable signal once, the process in which the data control lines30provide the enable signals to write the data voltages to the circuit rows10H row by row is the data writing phase.

The driving mode in the timing diagram ofFIG.12can also be applied to the driver board provided in the embodiment ofFIG.13, that is, a refresh cycle includes a data writing phase and a reset phase. In the reset phase, the plurality of data control lines30simultaneously output enable signals to reset the pixel electrodes11. It can be understood with reference to the embodiments ofFIG.1andFIG.12above, and details are not repeated herein.

In an embodiment, the display panel includes the driver board provided in the embodiment ofFIG.13. The pixels of the display panel include red pixels, green pixels, blue pixels, and white pixels, and each pixel includes electrophoretic particles. One red pixel, one green pixel, one blue pixel, and one white pixel constitute a display unit, and one display unit corresponds to one driver circuit10in the driver board. That is, one pixel electrode11cooperates with the common electrode to drive the electrophoretic particles in the pixel to move, thus realizing pixel display. In this embodiment, the process of displaying an image by the display panel includes four refresh cycles. For example, the data voltage is written to the pixel electrode11corresponding to the red pixel in the first refresh cycle to drive the red pixel to display, the data voltage is written to the pixel electrode11corresponding to the green pixel in the second refresh cycle to drive the green pixel to display, the data voltage is written to the pixel electrode11corresponding to the blue pixel in the third refresh cycle to drive the blue pixel to display, and the data voltage is written to the pixel electrode11corresponding to the white pixel in the fourth refresh cycle to drive the white pixel to display. The image is displayed after four refresh cycles. This embodiment of the present disclosure does not limit the refresh order of pixels with different colors in the four refresh cycles.

In some embodiments, pixels of the display panel include red pixels, green pixels, blue pixels, and white pixels, and each pixel includes electrophoretic particles. The driver board in the display panel includes a plurality of driver circuits10. Each driver circuit10includes four pixel electrodes11and one storage capacitor. The four pixel electrodes11in the driver circuit10are arranged in the same direction. One red pixel, one green pixel, one blue pixel, and one white pixel constitute a display unit, and one display unit corresponds to one driver circuit10in the driver board. In this embodiment, the process of displaying an image by the display panel includes four refresh cycles.

FIG.15is an enlarged view of a driver circuit inFIG.13. As shown inFIG.15, in a driver circuit10, four pixel electrodes11are arranged in a first electrode row11H-1and a second electrode row11H-2along a first direction x. Edge portions of the two pixel electrodes11in the first electrode row11H-1adjacent to the second electrode row11H-2are first edge portions (not labeled with reference sign inFIG.15), and edge portions of the two pixel electrodes11in the second electrode row11H-2adjacent to the first electrode row11H-1are second edge portions (not labeled with reference sign inFIG.15). The storage capacitor12overlaps with the first edge portions of the two pixel electrodes11and the second edge portions of the two pixel electrodes11, that is, the storage capacitor12overlaps with the middle region of the array formed by the four pixel electrodes11. The driver board further includes gating signal lines40extending in the first direction x, a control terminal of the pixel switch13is connected to a corresponding gating signal line40, and the driver circuit10is correspondingly connected to four gating signal lines40. In the second direction y, two of the four gating signal lines40are located at one side of the storage capacitor12and the other two are located at the other side of the storage capacitor12, and the second direction y crosses the first direction x. The control terminal of the data switch14is connected to the data control line30, and the data control line30extends along the first direction x. In the second direction y, the data control line30is located at a side of the storage capacitor12.

The embodiment ofFIG.15shows that when N=4, the four pixel electrodes11in the driver circuit10are arranged in two rows and two columns, and the storage capacitor12is arranged in the middle region of the arrangement region of the four pixel electrodes11, such that the storage capacitor12partially overlaps with each of the four pixel electrodes11. Arranging one storage capacitor12within the arrangement region of the four pixel electrodes11can ensure that the capacitance value of the storage capacitor12is sufficiently large. This allows for meeting the requirements on the capacitance value of the storage capacitor12when applied in electronic paper products, thereby fully charging the pixel electrodes11. This ensures efficient driving of electrophoretic particles and prevents uneven display. In addition, the four gating signal lines40are arranged in pairs that are located on two sides of the storage capacitor12respectively, which can facilitate the electrical connection between the gating signal line40and the pixel switch13. Setting the data control line30at a side of the storage capacitor12facilitates the electrical connection between the data control line30and the data switch14.

FIG.16is a schematic cross-sectional view taken along a line A-A′ shown inFIG.1. As shown inFIG.16, the driver board includes a substrate00, and a first metal layer001, a second metal layer002, and a transparent conductive layer003arranged sequentially away from the substrate00. At least one of the gating signal lines40, at least one of the data control lines30, and the reference electrode121are located in the first metal layer001, the data line20and the counter electrode122are located in the second metal layer002, and the pixel electrode11is located in the transparent conductive layer003. Optionally, the material of the first metal layer001includes molybdenum, the material of the second metal layer002includes titanium and aluminum, and the material of the transparent conductive layer003includes indium tin oxide. As shown inFIG.16, the driver board further includes a semiconductor layer004, and the material of the semiconductor layer004includes silicon. The semiconductor layer004is used to form active layers of switch transistors.FIG.16shows that active layers of the pixel switch13and the data switch14are located in the semiconductor layer004. InFIG.16, the pixel switch13and the data switch14are bottom-gate transistors. In other embodiments, the pixel switch13and the data switch14are top-gate transistors.

The active layers of the transistors of the present disclosure may include at least one of amorphous silicon, low-temperature polysilicon, and oxide semiconductor, and the transistors here may include the pixel switch13and the data switch14.FIG.16illustrates the structure of a transistor prepared by an amorphous silicon process.

FIG.16also shows a first conductive via V1through which the pixel electrode11is electrically connected to the second terminal of the pixel switch13.

In addition, a planarization layer005is arranged between the transparent conductive layer003and the second metal layer002. The planarization layer005has a planarization function, and can provide a flat base for the transparent conductive layer003, thereby ensuring the flatness of the pixel electrode11.

In some embodiments, at least one gating signal line40each includes a part located in the second metal layer002.FIG.17is a schematic diagram illustrating another driver board according to an embodiment of the present disclosure.FIG.17merely shows one driver circuit10on the driver board and N=3 is used as an example. As shown inFIG.17, three pixel electrodes11in the driver circuit10are arranged along a first direction x. The driver board includes a first-type gating signal line40aextending along the first direction x and a second-type gating signal line40bextending along the second direction y. The first-type gating signal line40ais located in the first metal layer01. The second-type gating signal line40bincludes a first line segment40b-1and a second line segment40b-2. The first line segment40b-1is located in the first metal layer001and the second line segment40b-2is located in the second metal layer002, and the second line segment40b-2is electrically connected to the first line segment40b-1via a second contact via V2. Part of the first line segment40b-1is reused as a gate of the pixel switch13. The data line20is located in the second metal layer002, the data control line30is located in the first metal layer001, and the pixel electrode11is located in the transparent conductive layer003. The sheet resistance of the second metal layer002is smaller than that of the first metal layer001. Setting the second line segment40b-2of the second-type gating signal line40bin the second metal layer002can reduce the overall resistance of the second-type gating signal line40b, thus reducing the voltage drop of the signal transmitted on the second-type gating signal line40b, which improves the in-plane signal uniformity.

In other embodiments, at least one data control line30each includes a third line segment and a fourth line segment, the third line segment is located in the first metal layer001, and the fourth line segment is located in the second metal layer002. The third line segment is electrically connected to the fourth line segment through a contact via penetrating through the insulating layer, and part of the third line segment is reused as a gate of the data switch14. This arrangement can reduce the overall resistance of the data control line30, thereby reducing the voltage drop of the signal transmitted on the data control line30, which improves the in-plane signal uniformity.

FIG.18is a schematic diagram of another driver board according to an embodiment of the present disclosure, andFIG.19is a schematic cross-sectional view taken along a line B-B′ inFIG.18.FIG.18schematically shows one driver circuit10on the driver board and N=3 is used as an example. With reference toFIG.18andFIG.19, the driver board includes a gating signal line40and a data control line30, a control terminal of a pixel switch13is connected to the gating signal line40, and a control terminal of a data switch14is coupled to the data control line30. The driver board includes a substrate00, and a first metal layer001, a second metal layer002, a third metal layer006, and a transparent conductive layer003arranged sequentially away from the substrate00. Optionally, the material of the first metal layer001includes molybdenum, the material of the second metal layer002and the third metal layer006includes titanium and aluminum, and the material of the transparent conductive layer003includes indium tin oxide.

A storage capacitor12includes a reference electrode121, a counter electrode122, and a third electrode123. The reference electrode121is opposite to the counter electrode122, the third electrode123is opposite to the reference electrode121, and the third electrode123is electrically connected to the counter electrode122.

At least one gating signal line40, at least one data control line30, and the counter electrode122are located in the first metal layer001, the data line20and the reference electrode121are located in the second metal layer002, the third electrode123is located in the third metal layer006, and the pixel electrode11is located in the transparent conductive layer003.

As can be seen fromFIG.19, the third electrode123is connected to a second terminal of the data switch14through a third conductive via V3penetrating through the insulating layer, and the second terminal of the data switch14is connected to the counter electrode122through a fourth conductive via V4penetrating through the insulating layer. Thus, the electrical connection between the third electrode123and the counter electrode122is realized.

The driver board provided in this embodiment includes three metal layers, and the three electrodes of the storage capacitor12are respectively located in the three metal layers, such that the storage capacitor12forms a sandwich structure. This can increase the capacitance value of the storage capacitor12.

In this embodiment of the present disclosure, the capacitance value of the storage capacitor12in the driver board is C0, and 0.5 pf≤C0≤3 fp. The capacitance value of the storage capacitor12is not less than 0.5 pf, which can ensure that the pixel electrode11is fully charged in the refresh cycle, and ensure that electrophoretic particles are fully driven when applied in electronic paper products. The capacitance value of the storage capacitor12is not larger than 3 fp, which can avoid the excessive size of the storage capacitor12affecting the PPI of the electronic paper products.

In the above related embodiments, N=3 or N=4 is used as an example to illustrate the structure of the driver board, and the driving mode of the driver board in the process of displaying an image.

In other embodiments, N=2, that is, one driver circuit10includes two pixel electrodes11and one storage capacitor12. In this embodiment, displaying of an image includes two refresh cycles. The driver board is applied to a display panel, the display panel includes red pixels, green pixels, and blue pixels, and each pixel includes a pixel electrode11. Some driver circuits10each correspond to one red pixel and one green pixel, some driver circuits10each correspond to one red pixel and one blue pixel, and some driver circuits10each correspond to one green pixel and one blue pixel.

In another embodiment, the display panel includes red pixels, green pixels, blue pixels, and white pixels, and a driver circuit10in the driver board includes two pixel electrodes11and one storage capacitor12.

In another embodiment, the display panel includes red pixels, green pixels, blue pixels, and white pixels, and a driver circuit10in the driver board includes three pixel electrodes11and one storage capacitor12.

FIG.20is a schematic diagram of another driver board according to an embodiment of the present disclosure, andFIG.21is a schematic circuit diagram at a region Q inFIG.20. As shown inFIG.20, the driver board includes a plurality of driver circuits10. The driver circuit10includes two pixel electrodes11and one storage capacitor12. The pixel electrode11is connected to a counter electrode122of the storage capacitor12through a pixel switch13, and a reference electrode121of the storage capacitor12is grounded. A control terminal of the pixel switch13is connected to a gating signal line40. With reference toFIG.21, two pixel switches13in the driver circuit10are respectively connected to a first gating signal line40-1and a second gating signal line40-2. A first data line20-1is arranged in the driver board, and the first data line20-1is connected to the storage capacitor12in the driver circuit10through the data switch14.

The driver board further includes a supplementary driving circuit70including one pixel electrode11and one storage capacitor12. In the driving circuit70, the pixel electrode11is electrically connected to the storage capacitor12.FIG.20shows that the pixel electrode11is connected to the counter electrode122of the storage capacitor12through a fifth conductive via V5. A second data line20-2is arranged in the driver board, and the second data line20-2is connected to the storage capacitor12in the driving circuit70through the data switch14.

In addition, as can be seen fromFIG.20, a control terminal of the data switch14in the driver circuit10and a control terminal of the data switch14in the driving circuit70are both connected to the data control line30.

An embodiment of the present disclosure further provides a display apparatus.FIG.22is a schematic diagram of a display apparatus according to an embodiment of the present disclosure. As shown inFIG.22, the display apparatus includes the display panel100provided in any embodiment of the present disclosure. The structure of the display panel100has been described in the foregoing embodiments, and details are not repeated. The display apparatus provided by the embodiment of the present disclosure may be an electronic product such as a smart tag, a reader, an advertising billboard.

The above descriptions are merely exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, and the like made within the spirit and principle of the present disclosure shall fall within the protection scope of the present disclosure.

Finally, it should be noted that the foregoing embodiments are merely intended to describe and not to limit the technical solutions of the present disclosure. Although the present disclosure has been described in detail with reference to the foregoing embodiments, persons skilled in the art should understand that they can still make modifications to the technical solutions described in the foregoing embodiments or make equivalent replacements to some or all of the technical features thereof. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.