Patent ID: 12253775

DESCRIPTION OF EMBODIMENTS

For the sake of a better understanding of the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

It should be noted that the embodiments in the following descriptions are merely some rather than all of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art on the basis of the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

Terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. Unless otherwise specified in the context, words, such as “a”, “the”, and “this”, in a singular form in the embodiments of the present disclosure and the appended claims include plural forms.

It should be understood that the term “and/or” in this specification merely describes associations between associated objects, and it indicates three types of relationships. For example, A and/or B may indicate that A exists alone, A and B coexist, or B exists alone. In addition, the character “/” in this specification generally indicates that the associated objects are in an “or” relationship.

It is to be understood that terms such as first, second and third in the embodiments of the present disclosure are merely used to distinguish similar objects, rather than describe a particular sequence.

In an aspect, the present disclosure provides a display panel.FIG.1andFIG.2are respectively schematic cross-sectional views of two display panels according to the embodiment of the present disclosure. As shown inFIG.1andFIG.2, the display panel includes an array substrate1. The array substrate1is provided with a display region AA and a non-display region NA. Specifically, the array substrate1includes a substrate10. The substrate10includes a display region AA and a non-display region NA. The non-display region NA at least partially surrounds the display region AA. The display region AA includes a color filter11, a pixel electrode12, and a first transistor13that are located on a same side of the substrate10. The first transistor13is electrically connected to the pixel electrode12. Specifically, as shown inFIG.1, the first transistor13includes a first gate130and a first semiconductor layer133. The first semiconductor layer133includes a channel region1330, a first doped region1331, and a second doped region1332. The first doped region1331is electrically connected to a data line. The second doped region1332is electrically connected to the pixel electrode12. As shown inFIG.1, orthographic projection of the first gate130on a plane of the substrate10overlaps with orthographic projection of the channel region1330on the plane of the substrate10.

In an embodiment of the present disclosure, as shown inFIG.1, along a direction h1perpendicular to the plane of the substrate10, the color filter11may be provided between the first semiconductor layer133and the pixel electrode12. The first semiconductor layer133is electrically connected to the pixel electrode12through a first connecting portion141. As shown inFIG.1, the first connecting portion141includes a first connecting sub-portion1411in a first connecting hole K1. Orthographic projection of the first connecting sub-portion1411on the plane of the substrate10does not overlap with orthographic projection of the color filter11on the plane of the substrate10. In an embodiment of the present disclosure, the first connecting sub-portion1411in the first connecting hole K1and the pixel electrode12may be made of a same material and formed in a same process. Along a direction parallel to the plane of the substrate10, the first connecting sub-portion1411at least partially overlaps with the color filter11. InFIG.1, the first connecting sub-portion1411is thicker than the color filter11, and along the direction parallel to the plane of the substrate10, the first connecting sub-portion1411includes one part overlapping with the color filter11, and the other part not overlapping with the color filter11.

Or, as shown inFIG.2, along the direction h1perpendicular to the plane of the substrate10, the first semiconductor layer133and the pixel electrode12are located on a same side of the color filter11.

Exemplarily, the display panel may be a liquid crystal display (LCD) panel. The display panel may be cooperatively provided with a backlight module (not shown). The color filter11is located at a light exit side of the backlight module. As shown inFIG.1andFIG.2, the display panel further includes a common electrode51and a liquid crystal layer81. The liquid crystal layer81is located at a side of the pixel electrode12away from the substrate10. In response to display of the display panel, the first transistor13is turned on under the control of the first gate130. The pixel electrode12receives a data voltage of the data line through the first transistor13. The common electrode51receives a common voltage. Under an action of an electric field between the pixel electrode12and the common electrode51, liquid crystal molecules in the liquid crystal layer81deflect at a particular angle, to adjust a transmittance of light rays from the backlight module. Moreover, after passing through the color filter11, the light rays from the backlight module can be emitted at a particular color, such that corresponding sub-pixels are turned on according to required colors.

According to the display panel provided by the embodiment of the present disclosure, the array substrate1includes the color filter11. In response to manufacturing of the display panel, the color filter11and the first transistor13are successively provided at a same side of the substrate10. That is, both the color filter11and the first transistor13can be integrated into the array substrate1. Compared with a solution in which the color filter11and the first transistor13are respectively provided on different substrates to form a color filter base including the color filter11and a driver base including the first transistor13, and then the color filter base and the driver base are aligned to form the display panel, the technical solutions In an embodiment of the present disclosure can achieve a higher alignment accuracy, can reduce problems such as light leakage caused by an alignment deviation, and improves a product yield.

Moreover, the smaller the size of the sub-pixel, the higher the requirement on the alignment accuracy. According to the solutions provided by the embodiment of the present disclosure, the color filter11is provided in the array substrate1. While ensuring the yield of the display panel, this can make the sub-pixel smaller, increases a number of pixels per inch (PPI) in the display panel, and realizes the high-resolution display panel. For example, the display panel provided by the embodiment of the present disclosure can be used in a VR display product.

In addition, as shown inFIG.1, along the direction h1perpendicular to the plane of the substrate10, the orthographic projection of the first connecting sub-portion1411on the plane of the substrate10does not overlap with the orthographic projection of the color filter11on the plane of the substrate10. Or, as shown inFIG.2, along the direction perpendicular to the plane of the substrate10, the first semiconductor layer133and the pixel electrode12are located on a same side of the color filter11. While ensuring that the first semiconductor layer133and the pixel electrode12are electrically connected, this does not form a via hole in the color filter11to connect the pixel electrode12and the first semiconductor layer133. The thicker the color filter11, the more difficult the formation of the via hole, and the larger the area required by the via hole. Therefore, the technical solutions provided by the embodiment of the present disclosure can reduce a process difficulty of electrical connection between the first semiconductor layer133and the pixel electrode12. Furthermore, if the via hole is formed in the color filter11, the via hole cannot be too small due to process limitations. Accordingly, the area of the color filter11also cannot be too small, and this is far from satisfactory to the requirement of the high-resolution display panel. While the first semiconductor layer133and the pixel electrode12are electrically connected, the technical solutions provided by the embodiment of the present disclosure can make the color filter11small enough, thereby further meeting the design requirement of the high-resolution display panel.

Exemplarily, as shown inFIG.1andFIG.2, the array substrate1further includes a first conductive layer M1and a second conductive layer M2. The first conductive layer M1includes the first gate130of the first transistor13. The second conductive layer M2includes a first terminal131of the first transistor13. The first terminal131is electrically connected to the data line. The first terminal131includes a source or a drain. Exemplarily, the first transistor includes a P-type transistor or an N-type transistor.

Optionally, the first conductive layer M1or the second conductive layer M2includes a metal layer.

InFIG.1andFIG.2, the first conductive layer M1is located at a side of the first semiconductor layer133away from the substrate10, and the second conductive layer M2is located at a side of the first conductive layer M1away from the first semiconductor layer133. Optionally, as shown inFIG.1andFIG.2, the array substrate1further includes a first gate insulating layer221and a first interlayer dielectric layer231. The first gate insulating layer221is located between the first semiconductor layer133and the first conductive layer M1. The first interlayer dielectric layer231is located between the first conductive layer M1and the second conductive layer M2.

Exemplarily, as shown inFIG.1andFIG.2, the array substrate1further includes a first electrode insulating layer31and a second electrode insulating layer32. The first electrode insulating layer31is located between the common electrode51and the pixel electrode12. The second electrode insulating layer32is located between the pixel electrode12and the second conductive layer M2.

Optionally, as shown inFIG.1, the color filter11may be provided at a side of the second conductive layer M2away from the first conductive layer M1. Exemplarily, as shown inFIG.1, the second electrode insulating layer32includes a first electrode insulating sub-layer321and a second electrode insulating sub-layer322that are stacked. The first electrode insulating sub-layer321is located between the color filter11and the pixel electrode12. The second electrode insulating sub-layer322is located between the color filter11and the second conductive layer M2. Optionally, the first electrode insulating sub-layer321includes a planarization layer, to improve a flatness on a surface of the first electrode insulating sub-layer321, thereby improving a manufacturing yield of the pixel electrode12on the surface of the first electrode insulating sub-layer321.

Exemplarily, the first connecting hole K1may penetrate through all insulating layers between the first semiconductor layer133and the pixel electrode12. As shown inFIG.1, the first connecting hole K1penetrates through the first electrode insulating sub-layer321, the second electrode insulating sub-layer322, the first interlayer dielectric layer231and the first gate insulating layer221.

In an embodiment, the first connecting hole K1may be relatively shallow In an embodiment of the present disclosure. The first connecting hole K1only penetrates through at least one of the insulating layers between the first semiconductor layer133and the pixel electrode12.FIG.3is a schematic cross-sectional view of still another display panel according to an embodiment of the present disclosure. Exemplarily, as shown inFIG.3, the first connecting portion141may further include a first connecting electrode1410between the pixel electrode12and the first semiconductor layer133. Orthographic projection of the first connecting electrode1410on the plane of the substrate10at least partially overlaps with orthographic projection of the first semiconductor layer133on the plane of the substrate10. The orthographic projection of the first connecting electrode1410on the plane of the substrate10at least partially overlaps with orthographic projection of the pixel electrode12on the plane of the substrate10. In an embodiment of the present disclosure, the first connecting hole K1may only penetrate through the insulating layer between the pixel electrode12and the first connecting electrode1410. The first connecting sub-portion1411in the first connecting hole K1is electrically connected to the first connecting electrode1410and the pixel electrode12. InFIG.3, the first connecting electrode1410is located between the first electrode insulating sub-layer321and the second electrode insulating sub-layer322. The first electrode insulating sub-layer321is provided between the pixel electrode12and the first connecting electrode1410. The first connecting hole K1only penetrates through the first electrode insulating sub-layer321.

Optionally, as shown inFIG.3, the first connecting portion141further includes a second connecting sub-portion1412in a second connecting hole K2. Along the direction h1perpendicular to the plane of the substrate10, the second connecting hole K2is located between the first connecting electrode1410and the first semiconductor layer133. The second connecting sub-portion1412is electrically connected to the first connecting electrode1410and the first semiconductor layer133. In an embodiment of the present disclosure, the second connecting hole K2only penetrates through the insulating layer between the first connecting electrode1410and the first semiconductor layer133. As shown inFIG.3, the second connecting hole K2penetrates through the second electrode insulating sub-layer322, the first interlayer dielectric layer231and the first gate insulating layer221.

In an embodiment of the present disclosure, the first connecting sub-portion1411, the first connecting electrode1410and the second connecting sub-portion1412are collectively connected to the pixel electrode12and the first semiconductor layer133. There is no need to provide a deep via hole between the first semiconductor layer133and the pixel electrode12. This can lower a connection difficulty between the pixel electrode12and the first semiconductor layer133, and reduce an area of the first connecting hole K1. As such, while orthographic projection of the first connecting hole K1on the plane of the substrate10does not overlap with the color filter11, the area of the color filter11can be made as large as possible improve an aperture ratio of the sub-pixel.

Exemplarily, as shown inFIG.3, the array substrate1further includes a third conductive layer M3. Both the third conductive layer M3and the color filter11are located between the second electrode insulating sub-layer322and the first electrode insulating sub-layer321. The third conductive layer M3includes the first connecting electrode1410. Exemplarily, the third conductive layer M3includes metal.

Exemplarily, as shown inFIG.1andFIG.3, the first electrode insulating sub-layer321includes a first sub-portion3211and a second sub-portion3212that are located in the display region AA. Orthographic projection of the first sub-portion3211on the plane of the substrate10overlaps with the orthographic projection of the color filter11on the plane of the substrate10. Orthographic projection of the second sub-portion3212on the plane of the substrate10does not overlap with the orthographic projection of the color filter11on the plane of the substrate10. As shown inFIG.3, the orthographic projection of the second sub-portion3212on the plane of the substrate10partially overlaps with the orthographic projection of the first connecting electrode1410on the plane of the substrate10.

Optionally, as shown inFIG.1andFIG.3, the first connecting hole K1may penetrate through the second sub-portion3212In an embodiment of the present disclosure, such that the orthographic projection of the first connecting hole K1on the plane of the substrate10does not overlap with the orthographic projection of the color filter11on the plane of the substrate10.

In an embodiment of the present disclosure, it is to be noted that the first buffer layer211, the first gate insulating layer221, the first interlayer dielectric layer231, the second electrode insulating sub-layer322and the first electrode insulating sub-layer321each may include one or more insulating layers. Different insulating layers may be made of a same material or different materials. For example, in case of a plurality of insulating layers, at least one of the insulating layers may be made of silicon oxide, and a remaining insulating layer may be made of silicon nitride. InFIG.1andFIG.3, the first gate insulating layer221includes a first gate insulating sub-layer2211and a second gate insulating sub-layer2212, and the first interlayer dielectric layer231includes a first interlayer dielectric sub-layer2311, a second interlayer dielectric sub-layer2312, and a third interlayer dielectric sub-layer2313. InFIG.2, the first gate insulating layer221, the first interlayer dielectric layer231and the second electrode insulating layer32are a single-layer structure.

In some embodiments of the present disclosure, the array substrate1includes a plurality of color filters11with different colors.FIG.4is a schematic top view of a display region of a display panel according to an embodiment of the present disclosure. As shown inFIG.4, the plurality of color filters11are arranged in an array in a first direction h21and a second direction h22. The first direction h21intersects with the second direction h22. Both the first direction and the second direction are parallel to the plane of the substrate10. InFIG.4, the color filter11includes a color filter111of a first color and a color filter112of a second color. Exemplarily, the first color includes any one of a red, a green and a blue, and the second color includes another one of the red, the green and the blue except the first color.

FIG.5is a schematic cross-sectional view along line BB′ shown inFIG.4. Referring toFIG.4andFIG.5, the array substrate1further includes a first light-blocking portion41in the display region AA. In an embodiment of the present disclosure, the first light-blocking portion41may include a first light-blocking sub-portion411extending along the first direction h21and a second light-blocking sub-portion412extending along the second direction h22. The first light-blocking sub-portion411is at least partially located between two adjacent color filters11in the second direction h22. The second light-blocking sub-portion412is at least partially located between two adjacent color filters11in the first direction h21. The first light-blocking sub-portion411and the second light-blocking sub-portion412can shield an opaque structure in the display region AA, so as to prevent light leakage due to a disordered electric field near the opaque structure. Exemplarily, the opaque structure includes the first transistor13and an opaque wiring portion such as the gate line and the data line. On the other hand, the first light-blocking sub-portion411and the second light-blocking sub-portion412can further prevent color mixing between different sub-pixels, thereby improving a display contrast and a display effect.

In an embodiment of the present disclosure, the first light-blocking portion41is provided in the array substrate1. Compared with a solution in which the first light-blocking portion41is provided in a base opposite to the array substrate1, this prevents the light leakage, can make a width of the first light-blocking portion41as small as possible, improves the aperture ratio of the sub-pixel, and can also improve the light transmittance of the display panel.

Optionally, In an embodiment of the present disclosure, at least one of the first light-blocking sub-portion411and the second light-blocking sub-portion412includes metal. The metal has a better light resistance than a resin material. In an embodiment of the present disclosure, at least one of the first light-blocking sub-portion411and the second light-blocking sub-portion412includes the metal. While ensuring the light resistance of the first light-blocking sub-portion411and/or the second light-blocking sub-portion412, this can reduce a thickness of the first light-blocking sub-portion411or the second light-blocking sub-portion412, and a width of the first light-blocking sub-portion411or the second light-blocking sub-portion412, thereby further improving the aperture ratio of the sub-pixel. Exemplarily, the metal includes a metal material with a relatively low reflectivity, to reduce a reflected visibility. Optionally, the metal includes at least one of molybdenum, chromium, aluminum, titanium and copper or at least one of corresponding metal oxide and metal nitride of molybdenum, chromium, aluminum, titanium and copper.

In addition, the metal is used to manufacture the first light-blocking portion41and/or the second light-blocking portion42In an embodiment of the present disclosure. While ensuring the light resistance, this can reduce the thickness of the first light-blocking portion41and/or the second light-blocking portion42as much as possible.FIG.6is a schematic cross-sectional view along line CC′ shown inFIG.4. As shown inFIG.6, the color filter11is located at a side of the first light-blocking portion41away from the substrate10, and the orthographic projection of the color filter11on the plane of the substrate10at least partially overlaps with orthographic projection of the first light-blocking portion41on the plane of the substrate10. This can prevent an overlarge included angle β between a bottom S1and a side S2of the color filter11, can make the first electrode insulating sub-layer321behind the color filter11better form a film and cover the color filter11, and improves the yield of the display panel.

Optionally, the array substrate1may include a first film layer In an embodiment of the present disclosure. The first film layer includes a first portion and a second portion that are insulated from each other. The first portion includes the first light-blocking sub-portion411. The second portion includes the first connecting electrode1410. That is, the first light-blocking sub-portion411and the first connecting electrode1410may be provided in the same first film layer. The first light-blocking sub-portion and the first connecting electrode are provided in the same layer, which refers to that both the first light-blocking sub-portion and the first connecting electrode are made of a same material, and formed in a same patterning process.

Exemplarily, the first film layer may be a metal film layer nearest to the color filter11in the array substrate1, to reduce a distance between the first light-blocking sub-portion411and the color filter11, and not to project wide-angle light rays of one sub-pixel to another sub-pixel through a region between the first light-blocking sub-portion411and the color filter11, thereby preventing the color mixing between different sub-pixels. InFIG.5, the array substrate1includes the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. The first film layer includes the third conductive layer M3.

Optionally, as shown inFIG.4, along the direction h1perpendicular to the plane of the substrate10, the first connecting electrode1410may not be overlap with the first light-blocking sub-portion411. This ensures that the first connecting electrode1410and the first light-blocking sub-portion411are insulated from each other when provided in the same first film layer.

Optionally, as shown inFIG.4, the first connecting electrode1410may at least partially overlap with the second light-blocking sub-portion412. When the first connecting electrode1410and the first light-blocking sub-portion411are provided in the same first film layer, this prevents the first connecting electrode1410from additionally occupying a space of an aperture region for transmitting the light rays in the sub-pixel, and ensures the aperture ratio of the sub-pixel.

Exemplarily, as shown inFIG.4, the second light-blocking sub-portion412may be electrically connected to the first transistor13. Referring toFIG.5, the second light-blocking sub-portion412may be electrically connected to the first terminal131of the first transistor13. The first terminal131includes the source or the drain. The first terminal131is electrically connected to the first doped region1331of the first semiconductor layer133. In response to display of the display panel, the second light-blocking sub-portion412provides a data signal for the first transistor13. As such, the data line is reused as the second light-blocking sub-portion412. This can further improve the aperture ratio of the sub-pixel, and can further simplify manufacture of the display panel.

Optionally, as shown inFIG.5, along the direction perpendicular to the plane of the substrate10, the second light-blocking sub-portion412may be located between the first connecting electrode1410and the first semiconductor layer133.FIG.7is a schematic top view of a second conductive layer shown inFIG.4. Referring toFIG.4,FIG.5, andFIG.7, the second light-blocking sub-portion412includes a first sub-hole K21. The orthographic projection of the first connecting electrode1410on the plane of the substrate10at least partially overlaps with the first sub-hole K21. With the first sub-hole K21, the first connecting electrode1410is electrically connected to the first semiconductor layer133through a connecting portion in the first sub-hole K21. This ensures the aperture ratio of the sub-pixel, without affecting electrical connection between the first connecting electrode1410and the first semiconductor layer133.

Exemplarily, as shown inFIG.4andFIG.5, the array substrate1further includes a second sub-hole K22. The first terminal131of the first transistor13is electrically connected to the first doped region1331of the first semiconductor layer133through a connecting portion in the second sub-hole K22. As shown inFIG.5, the second sub-hole K22penetrates through the first gate insulating layer221and the first interlayer dielectric layer231.

Optionally, beside the first portion and the second portion, a third portion may further be provided in the first film layer In an embodiment of the present disclosure. The third portion is insulated from the first portion and the second portion. The third portion includes the second light-blocking sub-portion412.FIG.8is a schematic top view of a display region of another display panel according to an embodiment of the present disclosure.FIG.9is a schematic cross-sectional view along line DD′ shown inFIG.8. Referring toFIG.8andFIG.9, the array substrate1includes the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. The first film layer includes the third conductive layer M3. The first light-blocking sub-portion411, the second light-blocking sub-portion412and the first connecting electrode1410may be provided in the same first film layer. This can simplify a manufacturing process of the display panel and reduce a thickness of the display panel. On the other hand, a distance between the second light-blocking sub-portion412and the color filter11can also be reduced, so as to prevent color mixing between two adjacent sub-pixels, and ensure a display effect. Exemplarily, the first light-blocking sub-portion411and the second light-blocking sub-portion412come in contact with the color filter11In an embodiment of the present disclosure.

Exemplarily, as shown inFIG.8, along the direction h1perpendicular to the plane of the substrate10, the orthographic projection of the first connecting electrode1410on the plane of the substrate10does not overlap with orthographic projection of the first light-blocking sub-portion411on the plane of the substrate10, and the orthographic projection of the first connecting electrode1410on the plane of the substrate10does not overlap with orthographic projection of the second light-blocking sub-portion412on the plane of the substrate10. While reducing the thickness of the display panel, and simplifying the manufacture of the display panel, this ensures that the first connecting electrode1410is insulated from the first light-blocking sub-portion411and the second light-blocking sub-portion412.

It is to be noted that the shape of the orthographic projection of the pixel electrode12on the plane of the substrate10is only schematic inFIG.4andFIG.8. In an embodiment of the present disclosure, the shape of the orthographic projection of the pixel electrode12on the plane of the substrate10can be adjusted according to different design requirements.

Referring also toFIG.1andFIG.3, the array substrate1further includes a non-display region NA. The non-display region NA includes a second light-blocking portion42. In response to display of the display panel, the second light-blocking portion42can prevent leakage of the light rays of the backlight module from the non-display region NA.

Optionally, as shown inFIG.1andFIG.3, the second light-blocking portion42may be provided between the second electrode insulating sub-layer322and the first electrode insulating sub-layer321. Exemplarily, the second light-blocking portion42may include a third light-blocking sub-portion421In an embodiment of the present disclosure. The third light-blocking sub-portion421includes a light-absorbing material. With the light-absorbing material, the third light-blocking sub-portion421cannot be coupled to a conductive structure in the non-display region NA. Exemplarily, the light-absorbing material includes resin.

Exemplarily, as shown inFIG.1andFIG.3, the array substrate1further includes a common connecting line52in the non-display region NA. The common electrode51is electrically connected to the common connecting line52through a second connecting portion142. Exemplarily, the common connecting line52receives a common voltage signal from a driver chip (not shown), and transmits the common voltage signal to the common electrode51through the second connecting portion142. As shown inFIG.1andFIG.3, the second connecting portion142includes a third connecting sub-portion1421in a third connecting hole K3. The third connecting hole K3penetrates through at least one of film layers between the common electrode51and the common connecting line52. Along the direction parallel to the substrate10, the third connecting sub-portion1421at least partially overlaps with the third light-blocking sub-portion421.

Exemplarily, as shown inFIG.1andFIG.3, orthographic projection of the third connecting sub-portion1421on the plane of the substrate10does not overlap with orthographic projection of the third light-blocking sub-portion421on the plane of the substrate10. While preventing the third connecting hole K3in the third light-blocking sub-portion421, ensuring that the common electrode51and the common connecting line52are connected smoothly, and lowering a manufacturing difficulty of the third connecting hole K3, this can increase a thickness of the third light-blocking sub-portion421to ensure a light absorption property of the third light-blocking sub-portion421.

Referring also toFIG.1andFIG.3, the first electrode insulating sub-layer321further includes a third sub-portion3213and a fourth sub-portion3214that are located in the non-display region NA. Orthographic projection of the third sub-portion3213on the plane of the substrate10does not overlap with the orthographic projection of the third light-blocking sub-portion421on the plane of the substrate10, and orthographic projection of the fourth sub-portion3214on the plane of the substrate10overlaps with the orthographic projection of the third light-blocking sub-portion421on the plane of the substrate10. In an embodiment of the present disclosure, the third connecting hole K3may penetrate through the third sub-portion3213. This prevents the third connecting hole K3from passing through the third light-blocking sub-portion421, and lowers the process difficulty of the third connecting hole K3.

Exemplarily, as shown inFIG.1andFIG.3, the common connecting line52may include a first common connecting sub-line521in the first conductive layer M1and a second common connecting sub-line522in the second conductive layer M2. The first common connecting sub-line521is electrically connected to the second common connecting sub-line522, to reduce a resistance of the common connecting line52.

Exemplarily, when the third connecting hole K3is formed, the third connecting hole K3may penetrate through all of the insulating layers between the common electrode51and the common connecting line52. InFIG.1, the first electrode insulating layer31, the first electrode insulating sub-layer321and the second electrode insulating sub-layer322are provided between the common electrode51and the common connecting line52. The third connecting hole K3penetrates through the first electrode insulating layer31, the first electrode insulating sub-layer321and the second electrode insulating sub-layer322.

Or, as shown inFIG.3, the third connecting hole K3may be relatively shallow In an embodiment of the present disclosure. A second connecting electrode1420is provided between the third connecting hole K3and the common connecting line52. The third connecting hole K3penetrates through the first electrode insulating layer31and the first electrode insulating sub-layer321. As shown inFIG.3, the second connecting electrode1420is electrically connected to the common connecting line52and the third connecting sub-portion1421. This can reduce a depth of the third connecting hole K3, and lower the manufacturing difficulty of the third connecting hole K3.

Exemplarily, beside the first portion and the second portion, the first film layer may further include a fourth portion In an embodiment of the present disclosure. The fourth portion includes the second connecting electrode1420. That is, as shown inFIG.3, the second connecting electrode1420and the first connecting electrode1410may be provided in the same first film layer, to simplify the manufacturing process of the display panel. InFIG.3, the first film layer includes the third conductive layer M3.

Optionally, as shown inFIG.3, the second light-blocking portion42further includes a fourth light-blocking sub-portion422. The fourth light-blocking sub-portion422includes the second connecting electrode1420. As such, the second connecting electrode1420is reused as the fourth light-blocking sub-portion422. While making the third connecting hole K3keep away from the third light-blocking sub-portion421to reduce the manufacturing difficulty of the third connecting hole K3, this can prevent light leakage of the display panel at a position without the third light-blocking sub-portion421.

Exemplarily, as shown inFIG.3, the orthographic projection of the second connecting electrode1420on the plane of the substrate10at least partially overlaps with the orthographic projection of the third light-blocking sub-portion421on the plane of the substrate10, so as to prevent a gap between the second connecting electrode and the third light-blocking sub-portion, and prevent light leakage at the gap.

Optionally, as shown inFIG.2, along the direction h1perpendicular to the plane of the substrate10, the first semiconductor layer133and the pixel electrode12may be located on a same side of the color filter11. InFIG.2, both the first semiconductor layer133and the pixel electrode12are located at a side of the color filter11away from the substrate10. In an embodiment of the present disclosure, the first semiconductor layer133may be electrically connected to the pixel electrode12through a third connecting portion143in a fourth connecting hole K4. The fourth connecting hole K4is located at a side of the color filter11adjacent to the pixel electrode12. Along the direction parallel to the plane of the substrate10, the fourth connecting hole K4does not overlap with the color filter11. When the third connecting portion143in the fourth connecting hole K4is provided to electrically connect the first semiconductor layer133and the pixel electrode12, this can prevent the fourth connecting hole K4from passing through the color filter11, and can lower a manufacturing difficulty of the fourth connecting hole K4.

Optionally, as shown inFIG.2, the fourth connecting hole K4penetrates through the first gate insulating layer221, the first interlayer dielectric layer231and the second electrode insulating layer32. Different fromFIG.1andFIG.3, the first gate insulating layer221, the first interlayer dielectric layer231and the second electrode insulating layer32are located on a same side of the color filter11inFIG.2.

Exemplarily, the first semiconductor layer133may include metal oxide In an embodiment of the present disclosure. This can improve a carrier mobility of the first semiconductor layer133. When the display panel is designed according to the film layer structure inFIG.2, this can improve a light transmittance of the first semiconductor layer133, thereby reducing the visibility of the first semiconductor layer133and improving the display effect. Optionally, the first semiconductor layer133includes indium gallium zinc oxide (IGZO).

FIG.10is a schematic cross-sectional view of still another display panel according to an embodiment of the present disclosure. Optionally, as shown inFIG.10, along the direction h1perpendicular to the plane of the substrate10, the first semiconductor layer133and the pixel electrode12are located on a same side of the color filter11. In an embodiment of the present disclosure, no insulating layer is provided between the first semiconductor layer133and the pixel electrode12. The first semiconductor layer133comes in contact with and is electrically connected to the pixel electrode12. There is no need to form a hole for electrically connecting the pixel electrode12and the first semiconductor layer133. This can simplify the manufacture of the display panel.

Exemplarily, as shown inFIG.10, the pixel electrode12may be located at a side of the first semiconductor layer133adjacent to the substrate10. That is, the first transistor13forms a bottom gate-bottom contact (BGBC) structure. The bottom contact refers to that a surface of the first semiconductor layer133adjacent to the substrate10comes in contact with the pixel electrode12and the first terminal131. Based on the structure, in response to display of the display panel, carriers can be directly injected into the channel region1330of the first transistor13from an edge of the pixel electrode12or the first terminal131, thereby improving an injection efficiency of the carriers. Certainly, the first terminal131and the pixel electrode12may also be provided at a side of the first semiconductor layer133away from the substrate10In an embodiment of the present disclosure. The first terminal131and the pixel electrode12come in contact with a surface of the first semiconductor layer133away from the substrate10. That is, the first transistor13forms a bottom gate-top contact (BGTC) structure.

Optionally, as shown inFIG.10, the first gate insulating layer221is located between the first conductive layer M1and the first semiconductor layer133. The first terminal131of the first transistor13and the pixel electrode12are located between the first gate insulating layer221and the first semiconductor layer133. The first doped region1331of the first semiconductor layer133is located at a side of the first terminal131away from the substrate10. The first doped region1331comes in contact with and is electrically connected to the first terminal131. The second doped region1332of the first semiconductor layer133is located at a side of the pixel electrode12away from the substrate10. The second doped region1332comes in contact with and is electrically connected to the pixel electrode12. Exemplarily, as shown inFIG.10, the array substrate1further includes an electrode insulating layer30between the common electrode51and the pixel electrode12.

Exemplarily, the pixel electrode12and the first terminal131of the first transistor13may be made of a same material and formed in a same patterning process In an embodiment of the present disclosure. For example, the pixel electrode12and the first terminal131include transparent metal oxide, so as not to affect normal light emission of the sub-pixel. Or, the pixel electrode12and the first terminal131of the first transistor13may be made of different materials in different patterning processes In an embodiment of the present disclosure. For example, the pixel electrode12may include transparent conductive oxide such as indium tin oxide (ITO) and indium zinc oxide (IZO), and the first terminal131may include metal In an embodiment of the present disclosure.

Exemplarily, In an embodiment of the present disclosure, the non-display region NA includes a gate driving circuit. The gate driving circuit includes a cascaded shift register unit. The shift register unit is electrically connected to a gate line. As shown inFIG.1,FIG.2,FIG.3andFIG.10, the cascaded shift register unit includes a second transistor14. The second transistor14includes a second gate140, a first terminal141, a second terminal142, and a second semiconductor layer143. One of the first terminal141and the second terminal142serves as a source, while the other servers as a drain.

In an implementation, as shown inFIG.1andFIG.3, the first semiconductor layer133and the second semiconductor layer143may be made of a same material and formed in a same patterning process, and the first gate130and the second gate140may be made of a same material and formed in a same patterning process. Optionally, the first semiconductor layer133and the second semiconductor layer143include low-temperature polysilicon or metal oxide.

Or, at least one of structures in the first transistor13and the second transistor14may also be provided on a different layer. In an embodiment of the present disclosure. As shown inFIG.2andFIG.10, the first transistor13and the second transistor14may be respectively located at two sides of the color filter11. In an embodiment of the present disclosure, along the direction h1perpendicular to the plane of the substrate10, the first semiconductor layer133and the second semiconductor layer143may be respectively located at the two sides of the color filter11, and the first gate130and the second gate140may be respectively located at the two sides of the color filter11. Optionally, the first semiconductor layer133and the second semiconductor layer143may be made of a same material, and may also be made of different materials. The first gate130and the second gate140may be made of a same material, and may also be made of different materials. The first transistor13and the second transistor14are provided independently. In response to manufacturing of the display panel, the first transistor13and the second transistor14can be adjusted according to different requirements, thereby improving the process flexibility of the first transistor and the second transistor.

Optionally, as shown inFIG.2andFIG.10, the array substrate1further includes a fourth conductive layer M4and a fifth conductive layer M5. The fourth conductive layer M4includes the second gate140of the second transistor14. The fifth conductive layer M5includes the first terminal141and the second terminal142of the second transistor14. Exemplarily, as shown inFIG.2andFIG.10, the fourth conductive layer M4and the fifth conductive layer M5are located at a side of the color filter11adjacent to the substrate10. Optionally, the fourth conductive layer M4and the fifth conductive layer M5include metal.

Exemplarily, as shown inFIG.2andFIG.10, the array substrate1further includes a second gate insulating layer222and a second interlayer dielectric layer232. The second gate insulating layer222is located between the second semiconductor layer143and the fourth conductive layer M4. The second interlayer dielectric layer232is located between the fifth conductive layer M5and the fourth conductive layer M4. InFIG.2andFIG.10, the second interlayer dielectric layer232includes a fourth interlayer dielectric sub-layer2321and a fifth interlayer dielectric sub-layer2322that are stacked.

Or, as shown inFIG.11andFIG.12, the first transistor13and the second transistor14are located at a side of the color filter11adjacent to the substrate10. The first semiconductor layer133and the second semiconductor layer143are provided on different layers. The first gate130and the second gate140are provided on different layers.FIG.11andFIG.12are respectively schematic cross-sectional views of still another two display panels according to an embodiment of the present disclosure.

Different fromFIG.2andFIG.10, beside the first terminal131of the first transistor13, the second conductive layer M2further includes the first terminal141and the second terminal142of the second transistor14inFIG.11andFIG.12.

As shown inFIG.11andFIG.12, the array substrate1further includes a fourth conductive layer M4. The fourth conductive layer M4includes the second gate140of the second transistor14. Along a direction away from the substrate10, the second semiconductor layer143, the fourth conductive layer M4, the first semiconductor layer133, the first conductive layer M1and the second conductive layer M2are sequentially stacked.

Exemplarily, as shown inFIG.2,FIG.10andFIG.11, the display region AA further includes a first insulating layer61, a third light-blocking portion43in the display region AA, and a fourth light-blocking portion44in the non-display region NA. The first insulating layer61includes a first aperture610. The color filter11is at least partially located in the first aperture610. Both the third light-blocking portion43and the fourth light-blocking portion44are located at a side of the first insulating layer61away from the substrate10. Optionally, in response to manufacturing of the display panel having the structure shown inFIG.2,FIG.10andFIG.11, the first insulating layer61is first provided. The first aperture610is formed in the first insulating layer61. The color filter11is provided in the first aperture610. The third light-blocking portion43and the fourth light-blocking portion44are provided at a side of the color filter11away from the substrate10. Exemplarily, the third light-blocking portion43and the fourth light-blocking portion44may be made of a same material, and formed in a same patterning process. The first aperture610may serve as an accommodating space of the color filter11. This makes the position of the color filter11more accurate.

As shown inFIG.2,FIG.9andFIG.10, the array substrate1further includes a second insulating layer62. The second insulating layer62is located at a side of each of the third light-blocking portion43and the fourth light-blocking portion44away from the substrate10. The second insulating layer62covers the third light-blocking portion43and the fourth light-blocking portion44. Exemplarily, both the first insulating layer61and the second insulating layer62include a transparent organic material. Optionally, both the first insulating layer61and the second insulating layer62include a planarization layer. In an embodiment of the present disclosure, the second insulating layer62includes the planarization layer. This can improve a flatness on a surface of the second insulating layer62. As shown inFIG.2, the first semiconductor layer133may be provided at a side of the second insulating layer62away from the substrate10, so as to ensure a yield of the first semiconductor layer133. Or, as shown inFIG.10, the first gate130may be provided at the side of the second insulating layer62away from the substrate10, so as to ensure a yield of the first gate130and a yield of the gate line in the same layer as the first gate130. Or, as shown inFIG.11, the pixel electrode12may be provided at the side of the second insulating layer62away from the substrate10, so as to ensure a yield of the pixel electrode12.

Moreover, while the flatness on the surface of the second insulating layer62is ensured, when the first insulating layer61and the second insulating layer62are provided with the planarization layer, a single planarization layer with a large thickness can be prevented, and the yield of the first insulating layer61and the second insulating layer62is improved.

In addition, the third light-blocking portion43and the fourth light-blocking portion44are located between the first insulating layer61and the second insulating layer62In an embodiment of the present disclosure. While preventing the light leakage, this can prevent the third light-blocking portion43and the fourth light-blocking portion44from affecting a flatness at corresponding positions.

Optionally, the third light-blocking portion43and/or the fourth light-blocking portion44may include metal In an embodiment of the present disclosure. The metal has a better light resistance than a resin material. In an embodiment of the present disclosure, at least one of the third light-blocking portion43and/or the fourth light-blocking portion44includes the metal. While ensuring the light resistance of the third light-blocking portion43and/or the fourth light-blocking portion44, this can reduce the thickness of the third light-blocking portion43and/or the fourth light-blocking portion44and the width of the third light-blocking portion43and/or the fourth light-blocking portion44. Exemplarily, the metal includes a metal material with a relatively low reflectivity, so as to reduce a reflected visibility. Optionally, the metal includes at least one of molybdenum, chromium, aluminum, titanium and copper or at least one of corresponding metal oxide and metal nitride of the molybdenum, the chromium, the aluminum, the titanium and the copper.

Exemplarily, as shown inFIG.2andFIG.10, the orthographic projection of the channel region1330of the first semiconductor layer133on the plane of the substrate10may overlap with orthographic projection of the third light-blocking portion43on the plane of the substrate. The third light-blocking portion43can prevent the light rays of the backlight module from irradiating the channel region1330. This can ensure that the first transistor13is turned on accurately.

Exemplarily, the fourth light-blocking portion44may include the metal, and the fourth light-blocking portion44may be grounded In an embodiment of the present disclosure. Exemplarily, as shown inFIG.2,FIG.10andFIG.11, the array substrate1includes a grounding portion9. The fourth light-blocking portion44is electrically connected to the grounding portion9. The fourth light-blocking portion44is grounded In an embodiment of the present disclosure. While reducing a thickness of the fourth light-blocking portion44, this can weaken coupling interference between the fourth light-blocking portion44and other conductive structures in the non-display region NA.

Optionally, as shown inFIG.2,FIG.10andFIG.11, a second aperture440in the non-display region NA may further be formed in the fourth light-blocking portion44In an embodiment of the present disclosure. The second aperture440can reduce an overlapping area between the fourth light-blocking portion44and other conductive structures in the non-display region NA, thereby weakening the coupling interference between the fourth light-blocking portion44and the other conductive structures in the non-display region NA.

Exemplarily, as shown inFIG.2,FIG.10andFIG.11, the non-display region NA further includes a fifth light-blocking portion45. Along the direction perpendicular to the plane of the substrate10, the fifth light-blocking portion45at least partially overlaps with the second aperture440. The fifth light-blocking portion45can prevent the light leakage of the non-display region NA at the second aperture440.

Optionally, the fifth light-blocking portion45may be provided at a side of the second aperture440adjacent to the substrate10In an embodiment of the present disclosure. For example, as shown inFIG.2andFIG.10, the fifth light-blocking portion45may be provided in the fifth conductive layer M5. Or, as shown inFIG.11, the fifth light-blocking portion45may be provided in the second conductive layer M2.

Or, the fifth light-blocking portion45may also be provided at a side of the second aperture440away from the substrate10In an embodiment of the present disclosure.

Exemplarily, as shown inFIG.2,FIG.10andFIG.11, the non-display region NA includes a peripheral circuit region NA1and a common wiring region NA2. The peripheral circuit region NA1includes the shift register unit. The shift register unit includes the second transistor14. The common wiring region NA2includes the common connecting line52. The second aperture440may be located in the common wiring region NA2In an embodiment of the present disclosure. Compared with the peripheral circuit region NA1, there are less conductive structures in the common wiring region NA2. By forming the second aperture440in the common wiring region NA2In an embodiment of the present disclosure, while weakening the coupling interference between the fourth light-blocking portion44and other conductive structures, this is more convenient to provide the fifth light-blocking portion45not interfering with the conductive structure in the common wiring region NA2.

Exemplarily, as shown inFIG.2andFIG.10, the common connecting line52may be provided in the second conductive layer M2, and the fifth light-blocking portion45may be provided in the fifth conductive layer M5.

Or, as shown inFIG.11, the common connecting line52may be provided in the fourth conductive layer M4, and the fifth light-blocking portion45may be provided in the second conductive layer M2.

Optionally, as shown inFIG.11, the fifth light-blocking portion45may be located between the common electrode51and the common connecting line52, and the fifth light-blocking portion45is electrically connected to the common electrode51and the common connecting line52. The fifth light-blocking portion45not only can block emission of the light rays to prevent the light leakage in the non-display region NA, but also can be electrically connected to the common electrode51and the common connecting line52. Neither a component for preventing the light leakage in the non-display region NA nor a component electrically connected to the common electrode51and the common connecting line52is provided. This simplifies the structure of the display panel and the manufacturing process of the display panel.

Exemplarily, as shown inFIG.11andFIG.12, the color filter11may be located between the pixel electrode12and the first semiconductor layer133, and the pixel electrode12may be electrically connected to the first semiconductor layer133through a fifth connecting portion15. The fifth connecting portion15is at least partially located in a fifth connecting hole K5. The fifth connecting hole K5penetrates through the color filter11.

Exemplarily, as shown inFIG.12, the array substrate1further includes a sixth light-blocking portion46and a seventh light-blocking portion47. The sixth light-blocking portion46is located in the display region AA. The sixth light-blocking portion46includes a third aperture460. The color filter11is at least partially located in the third aperture460. The seventh light-blocking portion47is located in the non-display region NA. Exemplarily, the sixth light-blocking portion46and the seventh light-blocking portion47include a light-absorbing material. Optionally, the light-absorbing material includes shading resin.

In an embodiment of the present disclosure, the sixth light-blocking portion46and the seventh light-blocking portion47may be reused as the planarization layer. Optionally, the planarization layer may be the first insulating layer61inFIG.2,FIG.10andFIG.11. This simplifies the film layer structure in the display panel, reduces the thickness of the display panel, and simplifies the manufacturing process of the display panel.

Optionally, the sixth light-blocking portion46and the seventh light-blocking portion47may be made of a same material, and formed in a same patterning process.

Exemplarily, as shown inFIG.1,FIG.2,FIG.3,FIG.10,FIG.11andFIG.12, the display panel further includes a cover plate6, a sealant7, and a support portion8. In response to assembly of the array substrate1and the cover plate6, the cover plate6and the color filter11are separated In an embodiment of the present disclosure. This reduces the requirement on an alignment accuracy between the array substrate1and the cover plate6.

Optionally, as shown inFIG.1,FIG.2,FIG.3andFIG.10, the support portion8is located between the cover plate6and the array substrate1. Orthographic projection of the support portion8on the plane of the substrate10at least partially overlaps with orthographic projection of the first transistor13on the plane of the substrate10. After the array substrate1is aligned at the cover plate6, the support portion8is configured to maintain a thickness between the array substrate1and the cover plate6. In an embodiment of the present disclosure, the orthographic projection of the support portion8on the plane of the substrate10at least partially overlaps with the orthographic projection of the first transistor13on the plane of the substrate10. This can prevent the support portion8from affecting deflection of liquid crystals in a sub-pixel aperture region, and ensure the display effect of the display panel.

Exemplarily, the pixel electrode12and the common electrode51include transparent conductive oxide. The transparent conductive oxide includes ITO or IZO.

It is to be noted thatFIG.1,FIG.2,FIG.3,FIG.8,FIG.9andFIG.10only schematically shows that the pixel electrode12is located at a side of the common electrode51adjacent to the substrate10. In an embodiment of the present disclosure, there are no limits made on a relative positional relationship between the pixel electrode12and the common electrode51and shapes of the pixel electrode and the common electrode. For example, In an embodiment of the present disclosure, according to different requirements, the pixel electrode12and the common electrode51can be designed as structures corresponding to different display modes. Exemplarily, the display modes include any one of an advanced super dimension switch (ADS) mode, a high advanced super dimension switch (HADS) display mode, a VA twisted nematic (TN) display mode, an in-plane switching (IPS) display mode, and a fringe field switching (FFS) display mode.

Optionally, as shown inFIG.1,FIG.3,FIG.5,FIG.9,FIG.11andFIG.12, the array substrate1further includes a first protective layer LS1. Orthographic projection of the first protective layer LS1on the plane of the substrate10overlaps with orthographic projection of the channel region1330of the first semiconductor layer133on the plane of the substrate10. The first protective layer LS1is located at a side of the first semiconductor layer133adjacent to the substrate10. The first protective layer LS1can absorb or reflect light coming from a backside of the display panel and emitted to the first semiconductor layer133, such that the light from the backside does not irradiate the channel region1330of the first semiconductor layer133, and the first transistor13is turned on or off accurately.

Exemplarily, as shown inFIG.11andFIG.12, the first protective layer LS1and the second gate140may be provided in the same fourth conductive layer M4In an embodiment of the present disclosure.

Optionally, as shown inFIG.1,FIG.2,FIG.3,FIG.10,FIG.11andFIG.12, the array substrate1further includes a second protective layer LS2. Orthographic projection of the second protective layer LS2on the plane of the substrate10overlaps with orthographic projection of a channel region of the second semiconductor layer143on the plane of the substrate10. The second protective layer LS2is located at a side of the second semiconductor layer143adjacent to the substrate10. The second protective layer LS2can absorb or reflect light coming from the backside of the display panel and emitted to the second semiconductor layer143, such that the light from the backside does not irradiate the channel region of the second semiconductor layer143, and the second transistor14is turned on or off accurately.

Optionally, as shown inFIG.1andFIG.3, the first protective layer LS1and the second protective layer LS2may be provided in a same layer In an embodiment of the present disclosure.

An embodiment of the present disclosure further provides a display apparatus.FIG.13is a schematic diagram of a display apparatus according to an embodiment of the present disclosure. As shown inFIG.13, the display apparatus includes the foregoing display panel100. A specific structure of the display panel100has been described in detail in the foregoing embodiments, and is not repeated herein. Certainly, the display apparatus shown inFIG.13is for schematic description only. The display apparatus may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an ebook, or a television.

The above descriptions are merely preferred embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, and the like made within the spirit and principle of the present disclosure shall fall within the protection scope of the present disclosure.