Patent ID: 12204468

DETAILED DESCRIPTION

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes at least one memory die of a first memory type. Memory control circuitry is coupled to the at least one memory die. An interface circuit is for coupling to a host IC chiplet. The interface circuit includes data input/output (I/O) circuitry for coupling to multiple data lanes. Link directional control circuitry selects, for a first memory transaction, a first subset of the multiple data lanes to transfer data between the memory chiplet and the host IC chiplet. By providing link directional control capability, such that multiple groups of links can change directions independently, arbitration efficiencies may be improved as compared to fixed link mapping.

Throughout the disclosure provided herein, the term multi-chip module (MCM) is used to represent a semiconductor device that incorporates multiple semiconductor die or sub-packages in a single unitary package. An MCM may also be referred to as a system in a package (SiP). The die or sub-packages are referred to herein as chiplets. The die or sub-packages that are interconnected in an MCM or SiP are referred to herein as chiplets. Packaged die that are disposed external to an MCM or SiP, such as being mounted on a printed circuit board (PCB), are referred to herein as chips.

FIG.1illustrates one embodiment of an MCM, generally designated100, that employs a package substrate102for mounting a host integrated circuit (IC) chiplet104and a memory chiplet106. An interface circuit108provides a low-latency and arbitration-efficient communications protocol between the host IC chiplet104and the memory chiplet106. For one embodiment, the interface circuit108is packet-based and operates via a packet protocol. As explained in further detail below, embodiments of the communications protocol described herein enhances memory transaction efficiency while reducing power consumption.

Further referring toFIG.1, the package substrate102may take a variety of forms, depending on the application. For some embodiments, the package substrate102may be realized as a “standard” package substrate, formed with an organic non-silicon material and incorporating a relatively sparse trace density appropriate for standard ball grid array (BGA) contact arrays (such as on the order of approximately one hundred to one hundred fifty microns). In other embodiments, the package substrate102may take the form of an “advanced” package substrate, such as a silicon interposer or silicon bridge-based substrate that provides a trace density on the order of approximately twenty-five to fifty-five microns.

With continued reference toFIG.1, the host IC chiplet104generally includes processor circuitry110or other logic that performs operations on data, with the need to periodically carry out read and write data transfers with the memory chiplet106. The processor circuitry110may take the form of one or more processors such as a computer processing unit (CPU), graphics processing unit (GPU), tensor processing unit (TPU), artificial intelligence (AI) processing circuitry, field-programmable gate array (FPGA) circuitry or other form of host chiplet with a need to access memory.

Further referring toFIG.1, the first IC chiplet104includes a communications fabric112for controlling communications on-chip, but for also controlling how the first IC chiplet104communicates off-chip with other chiplets, such as the memory chiplet106. For one embodiment, the communications fabric112includes network-on-chip (NoC) circuitry, such as that disclosed in U.S. patent Ser. No. 18/528,702, filed Dec. 4, 2023, titled: “UNIVERSAL NETWORK-ATTACHED MEMORY ARCHITECTURE”, owned by the assignee of the instant application and expressly incorporated herein by reference.

With continued reference toFIG.1, the IC chiplet104includes a “primary” interface sub-circuit114that forms a portion of the overall interface108. For one embodiment, the primary interface sub-circuit114includes minion link directional control circuitry116to control a selection of lanes for data transmission between the IC chiplet104and the memory chiplet106. As explained more fully below, lane selection may be based on a variety of factors, including data prioritization, relative flow control between read and write pipelines, and other criteria. Clock generation and cycle count circuitry118provides a system clock signal SCLK to serve as a forwarded clock to synchronize overall timing throughout the interface108, as well as providing a cycle count for dynamic bidirectional switching synchronization. Flow control circuitry120provides traffic regulation at the host IC chiplet104end to maximize data pipeline efficiencies. Further details pertaining to each of the above features of the primary interface sub-circuit114are more fully described below.

Further referring toFIG.1, for one embodiment, the memory IC chiplet106includes memory control circuitry122for controlling the scheduling of memory transactions between the host IC chiplet104and memory of a specific standard or type, such as high-bandwidth memory (HBM), double-data rate (DDR) memory, low-power double data rate (LPDDR), graphics double data rate (GDDR), to name but a few. Positioning the memory control circuitry122on the memory chiplet106removes the need for the host IC chiplet104(often a costly application-specific integrated circuit) to know the type of memory being accessed. The memory-agnostic feature of the primary interface sub-circuit114allows the host IC chiplet104to be paired with a variety of memory types, hence taking the form of a universally applicable memory interface (UMI).

For one embodiment, the memory chiplet106includes a second portion of the interface108, referred to herein as a “secondary” interface sub-circuit124. For one embodiment, the secondary interface subcircuit124includes master link directional control circuitry126, lane allocation circuitry128, cycle count circuitry130and I/O circuitry132. In some embodiments, register storage134may be provided on the memory chiplet106to store configurable parameters, such as turnaround time, relating to bidirectional link control, among other things. A memory chiplet-side flow control circuit136cooperates with the host IC chiplet-side flow control circuit120and provides traffic regulation at the memory IC chiplet104end to maximize data pipeline efficiencies.

For some embodiments, the memory chiplet106may take the form of a single-die chiplet that includes the memory control circuitry122and the features of the secondary interface sub-circuit124. The single-die chiplet may then be employed as a base die upon which are stacked memory die135for a stacked memory implementation, such as for HBM. Other embodiments may employ the single die as a buffer or intermediary between the IC chiplet104and memory die disposed proximate the single die on the package substrate102or off-MCM (not shown).

For one embodiment, the I/O circuitry108of the host IC chiplet104connects to the I/O circuitry132of the memory chiplet106via multiple lanes136. For one embodiment, the multiple lanes136are configured (from the perspective of the IC chiplet104) with memory transactions in mind to employ and utilize memory-centric features and functionality, thereby reducing latency and power consumption that might otherwise result from use of a generic D2D interface designed for a wide range of applications. For one embodiment, the multiple lanes136are configured or partitioned (from the perspective of the primary interface sub-circuit114) into an egress link138, an ingress link140, a data link142and a forwarding clock link144. For one specific embodiment, the data link142may be partitioned into multiple data links DATA1and DATA2. For some embodiments, a bidirectional sideband link146may be employed for out-of-band communications. Further details regarding specific embodiments of the multiple lanes136are disclosed in copending U.S. patent application Ser. No. 18/652,675, filed May 1, 2024, titled “UNIVERSAL MEMORY INTERFACE”, owned by the assignee of the instant application and expressly incorporated herein by reference.

Further referring toFIG.1, and as noted above, for one specific embodiment, the partitioned data link142takes the form of two subsets of bidirectional data lanes DATA1and DATA2. Each subset of bidirectional data lanes includes a number of lanes sufficient to transfer a sixty-four byte cacheline of data within an acceptable turnaround time constraint. One implementation utilizes thirty-seven lanes for each subset of bidirectional data lines for transferring the sixty-four byte cacheline of data. The time interval required to transfer the cacheline of data is referred to herein as a slot in the data link. Rather than assigning the subsets of bidirectional data lanes DATA1and DATA2to a fixed lane mapping (such as having one set operate only in a write direction, and the other set operate only in a read direction), the two subsets of lanes are individually dynamically configurable by the master link direction control circuitry126during operation to, as an example only, transfer a first cacheline of data (such as read data) in one direction, and subsequently transfer a second cacheline of data (such as write data) in the opposite direction. Dynamically configuring the subsets of bidirectional data lanes DATA1and DATA2in a memory-centric manner allows for arbitration efficiencies that typically exceed those of fixed lane mapping.

In an effort to maximize the arbitration efficiency involved in communications between the IC chiplet104and the memory chiplet106, the minion link directional control circuitry116of the “primary” interface sub-circuit114and the master link directional control circuitry126of the “secondary” interface sub-circuit124are configured to cooperate in selecting between the subset of lanes DATA1and DATA2for a given memory operation based on a variety of factors. For one embodiment, the secondary interface sub-circuit124is configured as the default owner of the bidirectional data links DATA1and DATA2. Being positioned on the memory chiplet106, the secondary interface sub-circuit124is closer to the memory135and the memory control circuitry122than any circuitry of the host IC chiplet104. This allows fast access to link availability information involving, for example, a read data pipeline in the memory chiplet104, and specifically information regarding when read operations have been scheduled by the memory control circuitry122, and thus when read data is available to traverse one or more of the data links DATA1and DATA2. The proximity also drastically lowers the area and power needed to add dedicated control signals between the Memory Control Circuitry122and the Master Link Direction Control Circuitry126. This proximity to the read pipeline information reduces any latency and area penalty that may be involved in obtaining the read operation information.

As explained above, with the read pipeline information readily available and in close proximity, for one embodiment, the master link directional control circuitry126on the memory chiplet106uses the link availability information as at least one factor in selecting from which of the two subsets of bidirectional data lanes DATA1or DATA2to use for a given write operation or read operation. In addition to read pipeline information, the master link directional control circuitry126may track the difference between write requests received and write data received to determine the number of outstanding write data transfers. It can then use this information to optimize how aggressively it allocates slots for write data transfers.

For some embodiments, selecting between the two subsets of bidirectional data lanes DATA1or DATA2to use for a given write operation or read operation may be achieved in a variety of ways. For one specific embodiment, the link direction is controlled by “link availability” information generated by the master link direction control circuitry126and specified in a field of a response packet, which is issued from the memory chiplet106by the “secondary” interface sub-circuit124for transfer along the ingress link140to the host IC chiplet104. Regardless of the implementation employed, an optimization between link bandwidth utilization versus read latency should be observed. For instance, based upon memory scheduling alone there may not be open timing intervals in the read pipeline that are large enough to allow for write data transfers, or the open timing intervals might not be large enough to minimize bandwidth lost to turnaround cycles. In these cases, the master link directional control circuitry126may need to temporarily delay some read data returns to allow for better link utilization and to prevent a large number of write data transactions from being queued in chiplet104. The queing of write data transactions should be limited to avoid two possible negative performance effects: (a) if the write data queues are ever filled, processing in chiplet104must be stopped to prevent overflow, and (b) read after write conflict logic often requires writes to be flushed to the DRAM so a conflicting read may need to wait for a long time if the offending write data hasn't already been transferred to chiplet106.

In addition to specifying link availability information, for one embodiment, response packets that control link direction also specify a clock synchronization parameter referred to herein as a cycle count. The cycle count represents a count of the system clock cycles at a given timing instant and at a given location in the system. For one specific embodiment, and described more fully below, the cycle count is generated by the cycle count circuitry130of the memory chiplet104, thus providing a common timing reference point for both chiplets. Distributing the cycle count so that it is known by both the primary interface sub-circuit114and the secondary interface sub-circuit124allows for performing synchronized operations across the link, particularly those involving bidirectional bus direction switchovers.

FIG.2illustrates one embodiment of a pipeline architecture, generally designated200, that includes a cycle counter202which may be employed by both the primary interface sub-circuit114and the secondary interface sub-circuit124to generate the clock cycle count to support synchronized transfers between the two interface sub-circuits114and124while employing dynamic bidirectional capability for the data links DATA1and DATA2. For one embodiment, the pipeline architecture200includes a receive pipeline204that includes sampling circuitry206to sample signals received from the link partner interface. The sampled signals are then fed to deserialization circuitry208to deserialize the signals from a serialized stream to parallel signals. The parallel signals are then forwarded to a receive buffer210which is coupled to common clock logic212which includes the cycle counter202. Running in a direction opposite to that of the receive pipeline204, a transmit pipeline214includes a transmit buffer216coupled to the common clock logic212. The transmit buffer feeds serialization circuitry218to serialize parallel signals from the transmit buffer216for transmission to the chiplet link partner by driver circuitry220.

FIG.3illustrates an overall data path and associated logic for one specific embodiment of the common clock logic212. The common clock logic212includes majority function logic302that performs a majority function on received pattern information (during a training procedure described more fully below). A first count register304stores a received reflected count that is received by the majority function logic302. A second count register306stores a received partner count that is also received by the majority function logic302. A third count register308stores a snapshot count value from the cycle counter202. An invariant cycle counter310couples to the cycle counter202. Histogram tracking logic312is coupled to the invariant cycle counter310and provides histogram information to controller logic314.

Prior to operation, the multiple lanes136undergo a lane initialization or calibration sequence to deskew relative signal propagation times between the various lanes. The deskew process may take the form of one from a variety of methods, with the underlying goal to have all signals for a given clock cycle or unit interval (UI) of a given packet arrive at the intended receiver circuitry in a predetermined alignment.

Further referring toFIG.3andFIG.4, following the lane training and word byte/alignment training, the cycle count value may be generated by carrying out a cycle count training process. The cycle count training process may be performed as a one-time procedure during an initialization mode of operation, or periodically during a run-time mode of operation. For one embodiment, the training process involves an initial coarse training sequence to generate a coarse calibrated value followed by a fine training sequence that further refines the coarse calibrated value into a finely tuned calibrated value.

To support the cycle count training process, the entire interface108is configured in a training mode of operation with sets of lanes associated with the ingress and egress lanes140and138designated for transferring specific patterns that include information regarding certain cycle counts. For example, in one embodiment, two specific training patterns are employed by each interface sub-circuit114and124for concurrent transmission along a certain number of lanes. One pattern may include a repeating 8-bit (byte) cycle count value, while the other pattern may include a repeating 8-bit received partner count value. Each pattern is sent across three lanes, for a total of six lanes in each direction. Comma values may be spaced every thirty-two repetitions of the count values.

Referring now toFIG.4, for one embodiment, the coarse training sequence starts with the primary interface sub-circuit114sending a start event, at402, to the secondary interface sub-circuit124via a write transaction executed by the sideband link146. The write transaction essentially serves as a command for the secondary interface sub-circuit124to begin its cycle count training sequence. The primary interface sub-circuit116then starts its own cycle count training sequence, at404. At the start of the cycle count training sequence, each interface sub-circuit, or “PHY”, at406, sets its own cycle counter to zero, and begins transmitting the first pattern (which includes that PHY's cycle count value) along a first set of three lanes, and the second pattern (which includes the other PHY's cycle count value) along a second set of three lanes. During the initial clock cycles of the training sequence, the received partner count value will be zero for several clock cycles until a count is received from the other PHY. As the training sequence progresses, real-time count value updates are made to the patterns.

With the patterns running, on the receive path of each PHY, two values will be available for the common clock logic212, the received partner count value from the remote PHY, stored in the second register306of the common clock logic212, and the local PHY's forwarded cycle count value, known as the received reflected count value, from the first register304of the common clock logic212, after undergoing a full round trip of delay. Once a valid received reflected count value is received on the forwarded channel, at408, the common clock logic212for that chiplet immediately creates a snapshot copy of its own cycle count value, known as a cycle count snapshot, and loads the value into the third register308of the common clock logic212, AT410. The cycle count snapshot thus represents the number of clock cycles that it took for the forwarded cycle count value to propagate to the partner chiplet and back, representing a round-trip propagation delay. At the secondary interface sub-circuit124, the common clock logic212periodically compares, at412, whether half the difference between the received reflected count value and the cycle count snapshot matches the difference between the received partner count and the cycle count snapshot. If the comparison results in a non-match, then the common clock signal fed to the common clock logic should be incrementally delayed or advanced by a delay circuit, at414, to reduce the cycle count by at least one clock cycle for a subsequent comparison. The comparison and adjustment steps are iterated until the comparison results in a match, at412.

Once the comparison operation results in a consistent matching condition, the cycle count training sequence ends the coarse training sequence, and begins the fine training sequence with a series of steps shown inFIG.5. The fine training sequence begins, at502, by setting a fine tune counter to 20479 (in terms of system clock cycles), such that it counts down to zero, defining a fine count interval. At the start of the fine tune count interval, the invariant cycle count counter will be loaded from the cycle count counter, at504. The invariant cycle count will free-run from this point on and will not be subject to any incrementing or decrementing adjustments. Based on the timing difference between the cycle count and the invariant cycle count, a histogram is created, at506, that counts the number of cycles where the timing difference is equal to 0, +1, −1, +2, −2, and Other.

Further referring toFIG.5, once the fine tune count interval ends, a delay will be applied to the system clock such that the cycle count for the secondary interface sub-circuit is adjusted, at508, to coincide with the median of the histogram. No further adjustments are made. If any samples of the histogram corresponded to the “Other” category, at510, then the fine tune sequence has failed, and a new sequence initiated, at502. If the sequence consistently fails, then an error condition is generated and sent to the primary interface sub-circuit114. If the sequence succeeds, then the training sequence ends, at512, and the interface108placed into a runtime mode of operation.

During runtime operation, the data links may be selectively switched to transfer data in either direction to allow for optimized traffic conditions. For some embodiments, the data traffic conditions may be additionally optimized through use of a flow control process that regulates packet transfers to prevent buffer circuits at each end of the links from overflowing or starving while at the same time optimizing the filling of the buffer circuits to reduce latency. For one embodiment, a credit-based flow control system is employed that employs credit counters in each chiplet. The use of such counters provides a predictive indication of the buffer usage at the other end of the link, without the need to wait for an actual acknowledgment that a given packet was received. As one example, where the memory chiplet106has a maximum buffer space, during the initialization mode, the buffer space may be advertised to the host IC chiplet104. In response, the host IC chiplet may configure a credit counter with a number of “credits” that correspond to the available buffer space of the memory chiplet104. Having a positive count of credits in the credit counter provides an indication to a transmitter in the host IC chiplet104that the destination receiver has room for additional data. As packets are sent to the destination receiver, the credit counter may decrement to account for the reduced buffer availability. A value of “0” generally corresponds to no availability in the buffer. When the packets are received and validated at the destination, the memory chiplet106may send a response packet confirming receipt of the packets. The credit counter at the host IC chiplet104may then increment the count back up once receiving the response packet.

While the dynamic bidirectional switching, cycle count, and flow control circuitry and techniques described above cooperate to maximize arbitration efficiency with minimal latency, further improvements may be realized by including the ability to dispatch partial transfers between the host IC chiplet104and the memory chiplet106, and reassembling the partial transfers into a whole transfer at the receiving end. For one embodiment, this may be accomplished by using the lane allocation circuitry128to tap into the read and write pipeline information and identify potential intervals or “holes” along a given link where a full or partial cacheline of data may be inserted for transfer. This allows for maximizing the transfer efficiency of the link by fully packing the pipeline of interest with data. Partial transfers may be tracked through use of tag information that may be included in packet fields. For one embodiment, the tag information for multiple partial packet payloads is unique, allowing for reassembly of the partial payloads into a full payload, such as an entire cacheline of data, at the receiving end of the link. The lane allocation circuitry128may also include logic to allocate lane availability based on one or more prioritization schemes.

When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘<signal name>’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement.

While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.