Patent ID: 12205891

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments include fusible structures and corresponding methods of manufacturing the same. In some embodiments, a fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages, relative to previously known technology, whereas thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity to protect against metal sputtering when the metal line is destructively altered.

FIG.1Ais a top view of a fusible structure100, in accordance with some embodiments.

In some embodiments, fusible structure100is as an electrical fuse (eFuse). Fusible structure100includes a metal line102, which in some embodiments is a narrow stripe (also called a “link”) of conductive material (metal, polysilicon, or the like). To program a fusible structure100, a programming current is applied to metal line102that destructively alters (i.e., fuses) metal line102, thus increasing the resistance of fusible structure100. In some embodiments, programming fusible structure100is referred to as burning fusible structure100. In some embodiments, fusible structure100is used as a one-time programmable memory (OTP). In some embodiments, to determine the bit state stored by fusible structure100, a sense current is propagated through metal line102. A sense amplifier (not shown), which is electrically coupled to metal line102, compares the current on metal line102with a reference current. The sense current is lower in magnitude than the programming current and thus does not destructively alter metal line102. The programming current is higher in magnitude than the sense current. As such, a programming voltage that corresponds to the programming current is higher in magnitude than the sense voltage that corresponds to the sense current.

The programming voltage is configured to generate sufficient programming current so as to destructively alter metal line102with a result being the destructive alteration of metal line102. The destructive alteration of metal line102breaks metal line102which creates an electrical discontinuity (or open circuit) in metal line102. When metal line102is destructively altered and broken, metal line102is configured in a high resistance state. Prior to the destructive alteration of metal line102, as shown inFIG.1A, metal line102is in a low resistive state. As explained in further detail below, the configuration of fusible structure100shown inFIG.1Afacilitates using lower programming voltages, and thus lower programming currents, to destructively alter metal line102with (again) the result that metal line102is put into the high resistance state. In other words, the programming voltage is expanded into lower voltages thereby decreasing the probability that metal line102does not break. Increasing the range of the programming voltage range to include lower voltages is beneficial, e.g., because the voltages used by modern semiconductor devices are decreasing.

In some embodiments, the high resistance state or the low resistance state of fuse structure100are used to represent bit values, and thus data is stored in a non-volatile manner. Sense amplifiers (not shown) in a memory circuit (not shown) are configured to generate a read current of sufficiently small magnitude that does not alter metal line102, and the corresponding resistance state (either the high resistance state or the low resistance state) of corresponding fusible structure100is determined by the sense amplifier (not shown). In a write operation (also referred to as a “programming operation”), a source line driver (not shown) is configured to supply a write voltage (also referred to as “programming voltage”) to metal line102to destructively alter metal line102. Other types of functionality other than as non-volatile memory are within the scopes of various embodiments.

Fusible structure100is provided in a semiconductor structure104. Semiconductor structure104includes a semiconductor substrate106and one or more metal layers108formed above or below semiconductor substrate104. In this embodiment, all of the components of fusible structure100are formed in a single metal layer108. In other embodiments, one or more of the components of fusible structure100are formed in one metal layer and another one or more of the components of fusible structure100are formed in another metal layer.

Metal line102has a long axis that extends in a first direction, which is parallel to the X-axis inFIG.1A. Metal line102has a short axis that extends in a second direction, which is perpendicular to the X-axis. In this embodiment, the short axis is parallel with the Y-axis. Metal line102includes a first portion110, a second portion112, and a third portion114. Relative to the X-axis, first portion110is between second portion112and third portion114. Relative to a third direction perpendicular to each of the X-axis and Y-axis, e.g., parallel to the Z-axis (not shown inFIG.1A), first portion110and third portion114have approximately a first thickness and second portion112has approximately a second thickness. Second portion112is between first portion110and third portion114relative to the X-axis (i.e., parallel to the X-axis). The second thickness is less than the first thickness. Relative to the X-axis, first portion110has a length (L_110) demarcated by demarcations fp1, fp2; in some embodiments, the length of first portion110is about L_110≈0.12 μm. Relative to the X-axis, second portion112has a length (L_112) demarcated by demarcations sp1, fp1; in some embodiments, the length of second portion112is about L_112≈0.666 μm. Relative to the X-axis, third portion114has a length (L_114) demarcated by demarcations fp2, sp2; in some embodiments, the length of third portion114is L_112≈0.666 μm. In some embodiments, L_112≈L_114. In some embodiments, L_110≈0.18*L_112. In some embodiments, L_112≈L_114. In some embodiments, L_110≈0.18*L_114. In some embodiments, a length between demarcations tv1and fp1is L_tv1_fp1≈0.14 μm. In some embodiments, a length between demarcations tv2and fp2is L_tv2_fp2≈0.14 μm. In some embodiments, L_tv1_fp1≈L_tv2_fp2. In some embodiments, L_110≈0.86*L_tv1_fp1. In some embodiments, L_110≈0.86*L_tv2_fp2.

Because first portion110is thinner than second portion112and third portion114, first portion110breaks at lower current amplitudes and thus at lower voltage amplitudes than each of first portion110and third portion114. Because first portion110is thinner and breaks at lower current amplitudes and thus at lower voltage amplitudes, the lower end of the voltage range for the programming voltage is increased beneficially.

Fusible structure100includes dummy structure116and dummy structure118. Dummy structure116and dummy structure118are on opposite sides of metal line102with respect to the X-axis. Dummy structure116and dummy structure118are aligned with one another with respect to the X-axis. Dummy structure116is separated from metal line102by a distance D1with respect to the Y-axis. Dummy structure118is separated from metal line102by a distance D2with respect to the Y-axis. In this embodiment, distance D1and distance D2are equal. In other embodiments, distance D1and distance D2are different.

Dummy structure116and dummy structure118are designed to prevent the destruction of first portion110of metal line102from affecting nearby non-dummy structures or devices. In some circumstances, programming/burning/destroying the first portion110results in sputtering, which can damage nearby non-dummy structures and/or devices. Dummy structures116and118are located so as to absorb material sputtered from first portion110, which reduces (if not prevents) damage to the nearby structures and/or devices.

Reducing distances D1, D2facilitates the first thickness of first portion110being thinner in comparison with the remainder of metal line102(i.e., second portion112, third portion114). In some embodiments, distances D1, D2are equal. In some embodiments, D1=D2=22 nanometers. In some embodiments, D1=D2=32 nanometers. In some embodiments, D1=D2=42 nanometers. In some embodiments, D1=D2=60 nanometers. In some embodiments, D1=D2=90 nanometers. In some embodiments, D1=D2=120 nanometers.

Dummy structure116and dummy structure118are of any shape. InFIG.1A, dummy structure116and dummy structure118are rectangles and have the same proportions. A long axis of dummy structure116and a long axis of dummy structure118are each provided in the X-axis to define a length a. A short axis of dummy structure116and a short axis of the dummy structure118are each provided in the Y-axis to define a width b. In some embodiments, a ratio of the length a divided by width b is between approximately 0.01 and 100. In some embodiments, the ratio of the length a divided by distance D1is between approximately 0.01 and 100. In some embodiments, the ratio of the length a divided by distance D2is between approximately 0.01 and 100.

As shown inFIG.1A, fusible structure100also includes conductive pads120,122,124,126. In some embodiments, conductive pads120,122,124,126are connected to metal line102through conductors and vias in other conductive layers and via layers (not shown). In this manner, the programming voltage and the sense voltage are applied to metal line102. A leftmost edge of conductive pad120and a leftmost edge of conductive pad122are aligned with a first end of metal line102. The first end of metal line102and leftmost edge of conductive pads120,122are demarcated by demarcation sp1. Conductive pads120,122each have a long axis that extends in the X-axis until demarcation tv1. A rightmost edge of conductive pads124and a rightmost edge of conductive pad126are aligned with a second end of metal line102. Second end of metal line102and rightmost edge of conductive pads124,126are demarcated by demarcation sp2. Conductive pads124,126each have a long axis that extends in the X-axis until demarcation tv2.

A length L of metal line102is defined between rightmost edge of conductive pads120,122(demarcated by demarcation tv1) and leftmost edge of conductive pads124,126(demarcated by demarcation tv2relative to the X-axis. Thus, inFIG.1A, length L is the length of metal line102from demarcation tv1to demarcation tv2. In some embodiments, L≈0.4 μm.

Metal line102defines a short axis in the Y-axis which provides a width w of metal line102. In some embodiments, the ratio of distance D1divided by length L is between approximately 0.01 and 100. In some embodiments, the ratio of the length a divided by distance D2is between approximately 0.01 and 100. In some embodiments, the ratio of the length L a divided by the width w is between approximately 4 and 100. In some embodiments, the ratios mentioned above provide adequate spacing so that the metal line102is thinner in the first portion110.

InFIG.1A, dummy structure116and dummy structure118are aligned with the first portion110with respect to the X-axis. However, relative to the X-axis, first portion110extends slightly past dummy structures116and118, both to the left and to the right of dummy structures116and118. Thus, inFIG.1A, there is a distance relationship in which distance fp1-fp2is greater than length a. In some of the embodiments, the distance relationship is facilitated using optical proximity correction (OPC).

FIG.1Bis a component diagram that illustrates a cross-sectional view of metal line102taken along a midline IB of metal line102in the X-axis, in accordance with some embodiments.

The thicknesses of metal line102is shown inFIG.1Bwith respect to the Z-axis. The Y-axis is not shown inFIG.1Bbecause the Y-axis goes into and out of the page. As shown inFIG.1B, metal line102has first portion110that is between second portion112and third portion114with respect to the X-axis. In this embodiment, second portion112and third portion114have a thickness t2while first portion110has a thickness t1, where t2>t1. Second portion112and third portion114are thus thicker than first portion110. Accordingly, first portion110is destructively altered at a lower programming voltage than second portion112and third portion114because first portion110is thinner than second portion112and third portion114. More specifically, first portion110has less material and therefore is more susceptible to destruction from resistive heating than second portion112and third portion114. In one embodiment, first portion110is destructively altered by an applied programming voltage of 1.53 Volts.

Dummy structure116(SeeFIG.1A) and dummy structure118(SeeFIG.1A) are placed near first portion110. Because first portion110is designed to be destructively altered and dummy structures116,118protect against metal sputtering, first portion110is thinner than second portion112and third portion114. As shown inFIG.1A, each of dummy structure116and dummy structure118is centered at first portion110. However, length a of each of dummy structure116and dummy structure118is shorter than the length of first portion110.

FIG.2is a top view of a fusible structure200, in accordance with some embodiments.

Fusible structure200is similar to fusible structure100inFIG.1A. Accordingly, discussion of fusible structure200concentrates on the differences between fusible structure200and fusible structure100. Like components include similar labels.

Dummy structure216and dummy structure218are sized in a similar manner as dummy structure116and dummy structure118inFIG.1A. Additionally, dummy structure216and dummy structure218are positioned in the same manner as dummy structure116and dummy structure118with respect to the X-axis and the Y-axis. However, in this embodiment, dummy structure216and dummy structure218are in a different metal layer than metal line112and contact pads120,122,124,126. In this embodiment, dummy structure216and dummy structure218are in a second metal layer of metal layers108of semiconductor structure104while metal line112and contact pads120,122,124,126are in a first metal layer of metal layers108, the first metal layer being beneath the second metal layer.

In some embodiments, the memory circuit further includes programming devices. In some embodiments, multiple fuse elements are connected to each programming device. Thus, the multiple fuse elements share a same programming device which significantly reduces the area occupied by the memory circuit compared to other approaches. In some embodiments, the programming device includes at least one transistor that is sized to provide the programming voltage (and thereby the programming current) to the fusible structure100during a write operation. In some embodiments, the programming device is or is part of the source line driver.

FIG.3Ais a top view of a fusible structure300, in accordance with some embodiments.

Fusible structure300is similar to fusible structure100inFIG.1A. Accordingly, discussion of fusible structure200concentrates on the differences between fusible structure200and fusible structure100. Like components include similar labels.

In this embodiment, fusible structure300includes a metal line302and dummy structures316,318,320, and322. Metal line302includes a first portion310, a second portion311, a third portion312, a fourth portion314, and a fifth portion315. With respect to the X-axis, first portion310is between third portion312and fifth portion315. First portion310is demarcated by demarcations tv1, m1. With respect to the X-axis, second portion311is between fifth portion315and fourth portion314. Second portion310is demarcated by demarcations m2, tv2. With respect to the X-axis, third portion312is demarcated by demarcations sp1, tv1. Demarcation sp1demarcates the left end of metal line302with respect to the X-axis. With respect to the X-axis, fourth portion312is demarcated by demarcations tv2, sp2. Demarcation sp2demarcates the right end of metal line302with respect to the X-axis. With respect to the X-axis, fifth portion315is between first portion310and second portion311. Fifth portion315is demarcated by demarcations m1, m2.

As explained in further detail below (SeeFIG.3B), first portion310and second portion311are thinner than third portion312, fourth portion314, and fifth portion315. More specifically, first portion310has less material and therefore is more susceptible to destruction from resistive heating than third portion312, fourth portion314, and fifth portion315. Accordingly, first portion310and second portion311are destructively altered at lower programming voltages than third portion312, fourth portion314, and fifth portion315. By destructively altering first portion310and/or second portion311, fusible structure300goes from the low resistance state to the high resistance state.

Fusible structure300includes dummy structures316,318,320, and322. Dummy structure316and dummy structure320are on one side of metal line302with respect to the X-axis while dummy structure318and dummy structure322are on an opposite side of metal line302with respect to the X-axis. Dummy structure316and dummy structure318are aligned with first portion310with respect to X-axis. Dummy structure316and dummy structure318are placed close enough to first portion310to allow first portion310to be thinner than third portion312and fifth portion315. As shown inFIG.3A, there is a length relationship in which dummy structure316and dummy structure318each have a length that is shorter than a length with respect to the X-axis of first portion310. In some embodiments, the length relationship is facilitated by optical proximity correction (OPC).

Dummy structure318and dummy structure322are aligned with second portion311with respect to X-axis. Dummy structure318and dummy structure322are placed close enough to second portion311to allow second portion311to be thinner than fifth portion315and fourth portion314. More specifically, second portion311has less material and therefore is more susceptible to destruction from resistive heating than third portion312, fourth portion314, and fifth portion315. As shown inFIG.3A, there is a length relationship in which dummy structure316and dummy structure318each have a length that is shorter than a length with respect to the X-axis of first portion310. In some embodiments, the length relationship is facilitated by OPC.

Dummy structure316is separated from dummy structure320with respect to the X-axis and dummy structure318is separated from dummy structure322with respect to the X-axis. As a result, fifth portion315is located between first portion310and second portion311where fifth portion315is thicker than first portion310and second portion311.

FIG.3Bis a component diagram that illustrates a cross-sectional view of metal line302taken along a midline IIIB of metal line302in the X-axis.

The thicknesses of metal line302is shown inFIG.3Bwith respect to the Z-axis. The Y-axis is not shown inFIG.3Bbecause the Y-axis goes into and out of the page. As shown inFIG.3B, metal line302has first portion310that is between third portion312and fifth portion315with respect to the X-axis. Metal line302also has second portion311between fifth portion315and fourth portion314with respect to the X-axis. In this embodiment, third portion312, fourth portion314and fifth portion315have a thickness t2while first portion310and second portion311have a thickness t1, where t2>t1. Third portion312, fourth portion314and fifth portion315are thus thicker than first portion310and second portion311. Accordingly, first portion310and second portion311are destructively altered at a lower programming voltage than third portion312, fourth portion314and fifth portion315. In one embodiment, first portion310and second portion311are destructively altered by an applied programming voltage of 1.53 Volts.

FIG.4Ais a top view of a fusible structure400, in accordance with some embodiments.

Fusible structure400is similar to fusible structure100inFIG.1A. Accordingly, discussion of fusible structure400concentrates on the differences between fusible structure400and fusible structure100. Like components include similar labels.

Metal line402includes a first portion410, a second portion412, and a third portion414. Relative to a Z-axis, first portion410and third portion414have approximately a first thickness and second portion412has approximately a second thickness. Second portion412is between first portion410and third portion414relative to the X-axis (i.e., parallel to the X-axis). The second thickness is less than the first thickness. First portion410is demarcated by demarcations fp1′, fp2′. Second portion412is demarcated by demarcations sp1, fp1′. Third portion114is demarcated by demarcations fp2′, sp2. Because first portion410is thinner than second portion412and third portion414, first portion410breaks at lower current amplitudes and thus at lower voltage amplitudes.

In comparison to first portion110shown inFIG.1A, first portion410inFIG.4Ais larger in length with respect to the X-axis because fusible structure400includes dummy structures416,418, and420. Dummy structure416and dummy structure420are on one side of metal line402and dummy structure418is on an opposite side of metal line402with respect to X-axis. Dummy structure418is aligned with first portion418with respect to the X-axis and is partially between and partially overlapping dummy structure416and dummy structure420with respect to the X-axis. Dummy structure416and dummy structure420are partially aligned with first portion410with respect to X-axis. However, dummy structure416extends to the left past demarcation fp1′ and dummy structure420extends to the right past demarcation420. Dummy structure416and dummy structure420thus allow first portion410to be longer than first portion110inFIG.1Abut does not extend the entirety of length of the leftmost edge of dummy structure416and rightmost edge of dummy structure420because fusible structure400is asymmetric with respect to dummy structures416,418, and420.

FIG.4Bis a component diagram that illustrates a cross-sectional view of metal line402taken along a midline IVB of metal line402in the X-axis, in accordance with some embodiments.

The thicknesses of metal line402is shown inFIG.4Bwith respect to the Z-axis. The Y-axis is not shown inFIG.4Bbecause the Y-axis goes into and out of the page. As shown inFIG.4B, metal line402has first portion410that is between second portion412and third portion414with respect to the X-axis. In this embodiment, second portion412and third portion414have a thickness t2while first portion410has a thickness t1, where t2>t1. Second portion412and third portion414are thus thicker than first portion410. Accordingly, first portion410is destructively altered at a lower programming voltage than second portion412and third portion414. In one embodiment, first portion410is destructively altered by an applied programming voltage of 1.53 Volts.

FIG.5is a top view of a fusible structure500, in accordance with some embodiments.

Fusible structure500is similar to fusible structure100inFIG.1A. Accordingly, discussion of fusible structure500concentrates on the differences between fusible structure500and fusible structure100. Like components include similar labels.

Fusible structure500is the same as fusible structure100except that fusible structure500does not include dummy structure116. It should be noted that different embodiments of the fusible structure like fusible structures100,200,300,400,500include different numbers of dummy structures to provide different numbers of portions of different thicknesses, whether asymmetric or symmetric.

FIG.6is a flowchart of a method600of generating a layout diagram, in accordance with some embodiments.

Method600is implementable, for example, using EDA system2(FIG.10, discussed above) and an integrated circuit (IC) manufacturing system1100(FIG.11, discussed below), in accordance with some embodiments. Regarding method600, examples of the layout diagram include layout diagrams having shapes that represent fusible structures100,200,300,400,500,800and900in corresponding FIGS.1A2,3A,4A,5,8A and9A.

InFIG.6, method600includes blocks602-604. At block602, a layout diagram is generated which, among other things, include shapes representing fusible structures100,200,300,400,500,800and900in correspondingFIGS.1A,2,3A,4A,5,8A and9A. From block602, flow proceeds to block604.

At block604, based on the layout diagram, at least one of (A) one or more photolithographic exposures are made or (b) one or more semiconductor masks are fabricated or (C) one or more components in a layer of a semiconductor device are fabricated. See discussion below of IC manufacturing system1100inFIG.11below.

FIG.7is a flowchart700of a method of forming a metal line that extends in a X-axis, in accordance with some embodiments.

Examples of metal lines formed by flowchart700include metal line102, metal line302, and metal line402, in correspondingFIGS.1A,3A and4A. In some embodiments, the method is included in procedures performed during block602in order to fabricate a fusible structure, e.g., fusible structure100,200,300,400,500,800and900in correspondingFIGS.1A,3A,4A,5,8A and9A. The method includes blocks702-706.

At block702, a mask is configured such that the metal line has a first portion that is between a second portion and a third portion. Examples of metal line are the metal line102,302,402in correspondingFIGS.1A,3A and4A. Examples of masks are discussed below inFIG.8BandFIG.9B. From block702, flow proceeds to block704.

At block704, an optical proximity correction (OPC) technique is used with the mask so that the first portion is thinner than each of the second portion and the third portion. Examples of first portion include first portion110, first portion310, second portion311, and first portion410inFIGS.1B,3B and4B. From block704, flow proceeds to block706.

At block706, a first dummy structure is formed proximal to the metal line and aligned with the first portion relative to the X-axis. Examples of dummy structures include dummy structures116,118inFIG.1AandFIG.5, dummy structures216,218inFIG.2A, dummy blocks structures316,318,320,322inFIG.3A, and dummy structures416,418,420inFIG.4A.

FIGS.8A and8Bcorrespondingly a component diagram and a cross-sectional view, in accordance with some embodiments.

FIG.8Ais a top view whileFIG.8Bis a cross sectional view along midline VIIIB of metal line810. A corresponding mask802has a segment804over portion806. Portion806is demarcated by demarcations C1, C2. An OPC technique is used with mask802so that portion806is thinner than each of portion818and third portion820.

FIGS.9A and9Bare correspondingly a component diagrams and a cross-sectional view, in accordance with some embodiments.

FIG.9Ais a top view whileFIG.9Bis a cross sectional view along midline IXB of metal line910. A corresponding mask902has a segment904under portion906. Portion906is demarcated by demarcations C1, C2. An OPC technique is used with mask902so that portion906is thinner than each of portion918and third portion920.

FIG.10is a block diagram of an electronic design automation (EDA) system1000, in accordance with some embodiments.

In some embodiments, EDA system1000includes an APR system. Methods described herein of designing layout diagrams, in accordance with one or more embodiments, are implementable, for example, using EDA system1000, in accordance with some embodiments.

In some embodiments, EDA system1000is a general purpose computing device including a hardware processor1002and a non-transitory, computer-readable storage medium1004. Storage medium1004, amongst other things, is encoded with, i.e., stores, computer program code1006, i.e., a set of executable instructions. Execution of instructions1006by hardware processor1002represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods).

Processor1002is electrically coupled to computer-readable storage medium1004via a bus1008. Processor1002is also electrically coupled to an I/O interface1010by bus1008. A network interface1012is also electrically connected to processor1002via bus1008. Network interface1012is connected to a network1014, so that processor1002and computer-readable storage medium1004are capable of connecting to external elements via network1014. Processor1002is configured to execute computer program code1006encoded in computer-readable storage medium1004in order to cause system1000to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor1002is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium1004is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium1004includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium1004includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).

In one or more embodiments, storage medium1004stores computer program code1006configured to cause system1000(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1004also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1004stores library1007of standard cells including such standard cells as disclosed herein. In one or more embodiments, storage medium1004stores one or more layout diagrams1009corresponding to one or more layouts disclosed herein.

EDA system1000includes I/O interface1010. I/O interface1010is coupled to external circuitry. In one or more embodiments, I/O interface1010includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor1002.

EDA system1000also includes network interface1012coupled to processor1002. Network interface1012allows system1000to communicate with network1014, to which one or more other computer systems are connected. Network interface1012includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems1000.

System1000is configured to receive information through I/O interface1010. The information received through I/O interface1010includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor1002. The information is transferred to processor1002via bus1008. EDA system1000is configured to receive information related to a UI through I/O interface1010. The information is stored in computer-readable medium1004as user interface (UI)1042.

In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system1000. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.

In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.

FIG.11is a block diagram of an integrated circuit (IC) manufacturing system1100, and an IC manufacturing flow associated therewith, in accordance with some embodiments.

The manufacturing system1100is configured to manufacture fusible structures100,200,300,400,500,800,900disclosed in correspondingFIGS.1A-1B,2,3A-3B,4A-4B,5,8A,8B,9A and9B.

In some embodiments, based on a layout diagram, e.g., at least one of (A) one or more semiconductor masks or (b) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system1100.

InFIG.11, IC manufacturing system1100includes entities, such as a design house1120, a mask house1130, and an IC manufacturer/fabricator (“fab”)1150, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1160. The entities in system1100are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1120, mask house1130, and IC fab1150is owned by a single larger company. In some embodiments, two or more of design house1120, mask house1130, and IC fab1150coexist in a common facility and use common resources.

Design house (or design team)1120generates an IC design layout diagram1122. IC design layout diagram1122includes various geometrical patterns designed for an IC device1160. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1160to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1122includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1120implements a proper design procedure to form IC design layout diagram1122. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1122is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1122is expressed in a GDSII file format or DFII file format.

Mask house1130includes data preparation1132and mask fabrication1144. Mask house1130uses IC design layout diagram1122to manufacture one or more masks1145to be used for fabricating the various layers of IC device1160according to IC design layout diagram1122. Mask house1130performs mask data preparation1132, where IC design layout diagram1122is translated into a representative data file (“RDF”). Mask data preparation1132provides the RDF to mask fabrication1144. Mask fabrication1144includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1145or a semiconductor wafer1153. The design layout diagram1122is manipulated by mask data preparation1132to comply with particular characteristics of the mask writer and/or requirements of IC fab1150. InFIG.11, mask data preparation1132and mask fabrication1144are illustrated as separate elements. In some embodiments, mask data preparation1132and mask fabrication1144is collectively referred to as mask data preparation.

In some embodiments, mask data preparation1132includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram1122. In some embodiments, mask data preparation1132includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation1132includes a mask rule checker (MRC) that checks the IC design layout diagram1122that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1122to compensate for limitations during mask fabrication1144, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation1132includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1150to fabricate IC device1160. LPC simulates this processing based on IC design layout diagram1122to create a simulated manufactured device, such as IC device1160. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are repeated to further refine IC design layout diagram1122.

It should be understood that the above description of mask data preparation1132has been simplified for the purposes of clarity. In some embodiments, data preparation1132includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1122according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1122during data preparation1132may be executed in a variety of different orders.

After mask data preparation1132and during mask fabrication1144, a mask1145or a group of masks1145are fabricated based on the modified IC design layout diagram1122. In some embodiments, mask fabrication1144includes performing one or more lithographic exposures based on IC design layout diagram1122. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1145based on the modified IC design layout diagram1122. Mask1145is formed in various technologies. In some embodiments, mask1145is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1145includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask1145is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1145, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask is attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1144is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1153, in an etching process to form various etching regions in semiconductor wafer1153, and/or in other suitable processes.

IC fab1150is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1150is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

IC fab1150includes fabrication tools1152configured to execute various manufacturing operations on semiconductor wafer1153such that IC device1160is fabricated in accordance with the mask(s), e.g., mask1145. In various embodiments, fabrication tools1152include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

IC fab1150uses mask(s)1145fabricated by mask house1130to fabricate IC device1160. Thus, IC fab1150at least indirectly uses IC design layout diagram1122to fabricate IC device1160. In some embodiments, semiconductor wafer1153is fabricated by IC fab1150using mask(s)1145to form IC device1160. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram1122. Semiconductor wafer1153includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer1153further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g., system1100ofFIG.11), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference.

In some embodiments, a method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.

In some embodiments, the forming a metal line further includes: the configuring the mask such that the first portion of the metal line and the first dummy structure have substantially the same width.

In some embodiments, the forming a first dummy structure includes: locating the first dummy structure so that a size of a gap between the first dummy structure and the metal line is proportional to the second thickness of the metal line.

In some embodiments, the forming a first dummy structure includes: aligning the first dummy structure substantially with the second portion of the metal line relative to the first direction.

In some embodiments, the method further includes forming a second dummy structure, and wherein the forming a first dummy structure includes: locating the second dummy structure and the first dummy structure on opposite sides of the metal line relative to the first direction; locating the second dummy structure to be proximal to the metal line relative to the second direction; and aligning the second dummy structure substantially with the second portion relative to the first direction.

In some embodiments, the method further includes forming a third dummy structure and a fourth dummy structure including: locating the third dummy structure and the fourth dummy structure on opposite sides of the metal line relative to the second direction; locating the third dummy structure and the fourth dummy structure to be proximal to the metal line relative to the second direction; aligning the third dummy structure and the fourth dummy structure substantially with the second portion relative to the first direction; and wherein the forming a metal line further includes: configuring the mask such that the metal line also has a fourth portion and a fifth portion, the fourth portion being between the third portion and the fifth portion; and the method further includes: using the optical proximity correction technique with the mask so that the fourth portion has approximately the first thickness and the fifth portion has approximately the second thickness relative to the third direction.

In some embodiments, the method further includes forming a second dummy structure and a third dummy structure including: locating the first dummy structure to be on a side of the metal line opposite to each of the second dummy structure and the third dummy structure relative to the second direction; locating the second dummy structure and the third dummy structure to be proximal to the metal line relative to the second direction; locating the first dummy structure at least partially between the second dummy structure and third dummy structure relative to the second direction; and aligning the first dummy structure, the second dummy structure, and the third dummy structure to be at least partially aligned with the second portion of the metal line relative to the first direction.

In some embodiments, the forming a metal line further includes forming the metal line is in a first metal layer; and the forming a first dummy structure includes forming the first dummy structure in a second metal layer that is different than the first metal layer.

In some embodiments, the method further includes forming a first contact pad; and a second contact pad including locating the first contact pad; and the second contact pad so that the first portion is between the first contact pad and the second contact pad relative to the first direction; and wherein: a length is defined relative to the first direction from the first contact pad to the second contact pad; a width of the metal line is defined relative to the second direction; a ratio is defined as the length divided by the width; and the method further includes locating the first contact pad; and the second contact pad so that the ratio is in a range between approximately 4 and approximately 100.

In some embodiments, a width of the metal line is defined relative to the second direction; a distance is defined between the metal line and the first dummy structure relative to the second direction; and the forming a first dummy structure includes locating the first dummy structure so that a ratio is defined as the distance divided by the width, the ratio being in a range between approximately 0.1 and approximately 100.

In some embodiments, the method further includes forming a first contact pad and a second contact pad including locating the first contact pad; and the second contact pad so that the first portion is between the first contact pad and the second contact pad relative to the first direction, and wherein: a first length is defined relative to the first direction from the first contact pad to the second contact pad; a second length of the first dummy structure is defined relative to the first direction; a width of the metal line is defined relative to the second direction; and the forming a metal line further includes sizing the metal line so that a ratio is defined as the second length divided by the first length, wherein the ratio is in a range between approximately 0.01 and approximately 0.99.

In some embodiments, a first length of the first dummy structure is defined relative to the first direction; a second length of the first dummy structure is defined relative to the second direction; a ratio is defined as the second length divided by the first length; and the forming a first dummy structure includes locating the first dummy structure so that the ratio is in a range between approximately 0.01 and approximately 100.

In some embodiments, a length of the first dummy structure is defined relative to the second direction; a distance is defined relative to the second direction between the metal line and the first dummy structure; a ratio is defined as the length divided by the distance; and the forming a first dummy structure includes locating the first dummy structure so that the ratio is in a range between approximately 0.01 and approximately 100.

In some embodiments, a method (of fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion, and configuring the mask such that the first portion of the metal line and the first dummy structure have substantially the same width; using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.

In some embodiments, the forming a first dummy structure includes locating the first dummy structure so that a size of a gap between the first dummy structure and the metal line is proportional to the second thickness of the metal line.

In some embodiments, the forming a first dummy structure includes aligning the first dummy structure substantially with the second portion of the metal line relative to the first direction.

In some embodiments, the method further includes forming a second dummy structure, and wherein: the forming a first dummy structure includes: locating the second dummy structure and the first dummy structure on opposite sides of the metal line relative to the first direction; locating the second dummy structure to be proximal to the metal line relative to the second direction; and aligning the second dummy structure substantially with the second portion relative to the first direction.

In some embodiments, the method further includes forming a third dummy structure and a fourth dummy structure including: locating the third dummy structure and the fourth dummy structure on opposite sides of the metal line relative to the second direction; locating the third dummy structure and the fourth dummy structure to be proximal to the metal line relative to the second direction; and aligning the third dummy structure and the fourth dummy structure substantially with the second portion relative to the first direction; and wherein the forming a metal line further includes configuring the mask such that the metal line also has a fourth portion and a fifth portion, the fourth portion being between the third portion and the fifth portion; and the method further includes using the optical proximity correction technique with the mask so that the fourth portion has approximately the first thickness and the fifth portion has approximately the second thickness relative to the third direction.

In some embodiments, the method further includes forming a second dummy structure and a third dummy structure including: locating the first dummy structure to be on a side of the metal line opposite to each of the second dummy structure and the third dummy structure relative to the second direction; locating the second dummy structure and the third dummy structure to be proximal to the metal line relative to the second direction; locating the first dummy structure at least partially between the second dummy structure and third dummy structure relative to the second direction; and aligning the first dummy structure, the second dummy structure, and the third dummy structure to be at least partially aligned with the second portion of the metal line relative to the first direction.

In some embodiments, a method (of fabricating a fusible structure) includes: forming a metal line that extends in a first direction, the forming a metal line including configuring the mask such that the metal line has a first portion that is between a second portion and a third portion, and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction, the forming a first dummy structure including locating the first dummy structure so that a size of a gap between the first dummy structure and the metal line is proportional to the second thickness of the metal line.

In some embodiments, the forming a metal line further includes the configuring the mask such that the first portion of the metal line and the first dummy structure have substantially the same width.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.