Patent ID: 12249966

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

A mmW intermediate frequency integrated circuit (IFIC) typically supports a single mmW radio frequency integrated circuit (RFIC) in a user equipment (UE) mode but generally supports more than one mmW RFIC in customer premises equipment (CPE) and small cell (cell site modem (CSM) and femtocell (FSM)) modes. In previous solutions, a mmW IFIC may have a total of eight (8) driving amplifiers (DAs) to support eight (8) communication ports. However, a newer generation mmW IFIC may implement 16 DAs for supporting multiple communication bands, such as, for example, a low band (LB) and high band (HB) operating mode. Unfortunately, a DA occupies considerable silicon area, thus making integrating such a large number of DAs on a die challenging. Moreover, multiple DAs lead to DA-dependent behavior. In previous IFICs, the residual sideband (RSB) and LO leakage performance exhibit significant discrepancy among the different communication ports due to the DA mismatch and different spatial electromagnetic (EM)/package coupling over the multiple DAs. Because the RSB and local oscillator (LO) leakage are calibrated based on a single baseband filter, the calibration is not able to account for the RSB discrepancy over multiple communication ports that results from the DA-dependent behavior.

In a communication system that uses a phased array antenna system, a communication device may be reconfigurable to operate in more than one mode. For example, a communication device may be configurable to operate in a user equipment (UE) mode and also in a customer premises equipment (CPE) mode. Operating in different modes often employs different circuitry on the communication device. For example, in a UE mode, intermediate frequency (IF) circuitry may support one type or amount of RF circuitry, and in CPE mode, the IF circuitry may support another type or amount of RF circuitry. Further, there may be multiple UE and/or CPE modes which each support a different number of antennas. One element in IF circuitry that consumes a high amount of power and area on the circuit is referred to as a driver amplifier. A driver amplifier may be part of a transceiver interface whereby the driver amplifier may operate at a first frequency (for example, an intermediate frequency (IF)), and provide an IF signal to another circuit, for example, a radio frequency (RF) circuit. Therefore, it would be desirable to reduce or minimize the number of driver amplifiers on an IF circuit that support multiple configurations of a communication device. As that one DA may support be used to support different circuitry in different modes of communications, it is beneficial to ensure proper operation of the DA in each of the different modes (e.g., by ensuring an appropriate or substantially constant load line impedance is presented to the DA).

In an exemplary embodiment, a transceiver interface as described herein may be used in a millimeter wave (mmW) communication system in an intermediate circuit located between baseband signal processing elements and radio frequency (RF) signal processing elements. For example, the intermediate circuit may be included in an IC or chip which converts between IF signals and baseband signals, and which is separate from an IC or chip which processes analog baseband signals and also separate from an IC or chip which converts between IF and a mmW frequency. In another example, the intermediate circuit and the circuitry which process analog baseband signals are included on the same chip or IC. In yet another example, signals output from the transceiver interface (or received by the transceiver interface) have the same frequency as signals which are wirelessly transmitted from the communication device. In such examples, the transceiver interface may not be coupled to a mmW subsystem, or a certain port of the transceiver interface may be coupled to a mmW subsystem while one or more other ports are coupled to one or more antennas such that signals communicated between the one or more other ports and the one or more antennas are not converted in frequency. For example, the one or more antennas may be configured to operate in an FR3 frequency.

FIG.1is a diagram showing a wireless device110communicating with a wireless communication system120. The wireless communication system120may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a wireless local area network (WLAN) system, a 5G NR (new radio) system, or some other wireless system. A CDMA system may implement Wideband CDMA (WCDMA), CDMA 1×, Evolution-Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity,FIG.1shows wireless communication system120including two base stations130and132and one system controller140. In general, a wireless communication system may include any number of base stations and any set of network entities.

The wireless device110may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device110may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet, a cordless phone, a medical device, a device configured to connect to one or more other devices (for example through the internet of things), a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device110may communicate with wireless communication system120. Wireless device110may also receive signals from broadcast stations (e.g., a broadcast station134) and/or signals from satellites (e.g., a satellite150in one or more global navigation satellite systems (GNSS), etc). Wireless device110may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA 1×, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

The wireless communication system120may also include a wireless device160. In an exemplary embodiment, the wireless device160may be a wireless access point, or another wireless communication device that comprises, or comprises part of a wireless local area network (WLAN). In an exemplary embodiment, the wireless device160may be referred to as a customer premises equipment (CPE), which may be in communication with a base station130and a wireless device110, or other devices in the wireless communication system120. In some embodiments, the CPE may be configured to communicate with the wireless device110using WAN signaling and to interface with the base station130based on such communication instead of the wireless device110directly communicating with the base station130. In exemplary embodiments where the wireless device160is configured to communicate using WLAN signaling, a WLAN signal may include WiFi, or other communication signals. In some embodiments, a single wireless device, such as the wireless device110or the wireless device160, may be configured to operate in multiple modes. For example, a single wireless device may be configured to operate in a first mode as a UE and in a second mode as a CPE.

Wireless device110may support carrier aggregation, for example as described in one or more LTE or 5G standards. In some embodiments, a single stream of data is transmitted over multiple carriers using carrier aggregation, for example as opposed to separate carriers being used for respective data streams. Wireless device110may be able to operate in a variety of communication bands including, for example, those communication bands used by LTE, WiFi, 5G or other communication bands, over a wide range of frequencies. Wireless device110may also be capable of communicating directly with other wireless devices without communicating through a network.

In general, carrier aggregation (CA) may be categorized into two types—intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same band. Inter-band CA refers to operation on multiple carriers in different bands.

FIG.2Ais a block diagram showing a wireless device200in which the exemplary techniques of the present disclosure may be implemented. The wireless device200may, for example, be an embodiment of the wireless device110and/or the wireless device160illustrated inFIG.1.

FIG.2Ashows an example of a transceiver220having a transmitter230and a receiver250. In general, the conditioning of the signals in the transmitter230and the receiver250may be performed by one or more stages of amplifier, filter, upconverter, downconverter, etc. These circuit blocks may be arranged differently from the configuration shown inFIG.2A. Furthermore, other circuit blocks not shown inFIG.2Amay also be used to condition the signals in the transmitter230and receiver250. Unless otherwise noted, any signal inFIG.2A, or any other figure in the drawings, may be either single-ended or differential. Some circuit blocks inFIG.2Amay also be omitted.

In the example shown inFIG.2A, wireless device200generally comprises the transceiver220and a data processor210. The data processor210may include a processor296operatively coupled to a memory298. The memory298may be configured to store data and program codes shown generally using reference numeral299, and may generally comprise analog and/or digital processing components. The transceiver220includes a transmitter230and a receiver250that support bi-directional communication. In general, wireless device200may include any number of transmitters and/or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver220may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

A transmitter or a receiver may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between radio frequency (RF) and baseband in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for a receiver. In the direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the example shown inFIG.2A, transmitter230and receiver250are implemented with the direct-conversion architecture.

In the transmit path, the data processor210processes data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to the transmitter230. In an exemplary embodiment, the data processor210includes digital-to-analog-converters (DAC's)214aand214bfor converting digital signals generated by the data processor210into the I and Q analog output signals, e.g., I and Q output currents, for further processing. In other embodiments, the DACs214aand214bare included in the transceiver220and the data processor210provides data (e.g., for I and Q) to the transceiver220digitally.

Within the transmitter230, baseband (e.g., lowpass) filters232aand232bfilter the I and Q analog transmit signals, respectively, to remove undesired images caused by the prior digital-to-analog conversion. Amplifiers (Amp)234aand234bamplify the signals from baseband filters232aand232b, respectively, and provide I and Q baseband signals. An upconverter240having upconversion mixers241aand241bupconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator290and provides an upconverted signal. A filter242filters the upconverted signal to remove undesired images caused by the frequency upconversion as well as noise in a receive frequency band. A power amplifier (PA)244amplifies the signal from filter242to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch246and transmitted via an antenna248. While examples discussed herein utilize I and Q signals, those of skill in the art will understand that components of the transceiver may be configured to utilize polar modulation.

In the receive path, antenna248receives communication signals and provides a received RF signal, which is routed through duplexer or switch246and provided to a low noise amplifier (LNA)252. The duplexer246is designed to operate with a specific RX-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by LNA252and filtered by a filter254to obtain a desired RF input signal. Downconversion mixers261aand261bin a downconverter260mix the output of filter254with I and Q receive (RX) LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator280to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers262aand262band further filtered by baseband (e.g., lowpass) filters264aand264bto obtain I and Q analog input signals, which are provided to data processor210. In the exemplary embodiment shown, the data processor210includes analog-to-digital-converters (ADC's)216aand216bfor converting the analog input signals into digital signals to be further processed by the data processor210. In some embodiments, the ADCs216aand216bare included in the transceiver220and provide data to the data processor210digitally.

InFIG.2A, TX LO signal generator290generates the I and Q TX LO signals used for frequency upconversion, while RX LO signal generator280generates the I and Q RX LO signals used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A phase locked loop (PLL)292receives timing information from data processor210and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator290. Similarly, a PLL282receives timing information from data processor210and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from LO signal generator280.

In an exemplary embodiment, the RX PLL282, the TX PLL292, the RX LO signal generator280, and the TX LO signal generator290may alternatively be combined into a single LO generator circuit295, which may include common or shared LO signal generator circuitry to provide the TX LO signals and the RX LO signals. Alternatively, separate LO generator circuits may be used to generate the TX LO signals and the RX LO signals.

Wireless device200may support CA and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies and/or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. Those of skill in the art will understand, however, that aspects described herein may be implemented in systems, devices, and/or architectures that do not support carrier aggregation.

Certain components of the transceiver220are functionally illustrated inFIG.2A, and the configuration illustrated therein may or may not be representative of a physical device configuration in certain implementations. For example, as described above, transceiver220may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver220is implemented on a substrate or board such as a printed circuit board (PCB) having various modules, chips, and/or components. For example, the power amplifier244, the filter242, and the duplexer246may be implemented in separate modules or as discrete components, while the remaining components illustrated in the transceiver220may be implemented in a single transceiver chip.

The power amplifier244may comprise one or more stages comprising, for example, driver stages, power amplifier stages, or other components, that can be configured to amplify a communication signal on one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier244can be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and can be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

In an exemplary embodiment in a super-heterodyne architecture, the filter242, PA244, LNA252and filter254may be implemented separately from other components in the transmitter230and receiver250, and may be implemented on a millimeter wave integrated circuit. An example super-heterodyne architecture is illustrated inFIG.2B.

FIG.2Bis a block diagram showing a wireless device in which the exemplary techniques of the present disclosure may be implemented. Certain components, for example which may be indicated by identical reference numerals, of the wireless device200ainFIG.2Bmay be configured similarly to those in the wireless device200shown inFIG.2Aand the description of identically numbered items inFIG.2Bwill not be repeated.

The wireless device200ais an example of a heterodyne (or superheterodyne) architecture in which the upconverter240and the downconverter260are configured to process a communication signal between baseband and an intermediate frequency (IF). For example, the upconverter240may be configured to provide an IF signal to an upconverter275. In an exemplary embodiment, the upconverter275may comprise summing function278and upconversion mixer276. The summing function278combines the I and the Q outputs of the upconverter240and provides a non-quadrature signal to the mixer276. The non-quadrature signal may be single ended or differential. The mixer276is configured to receive the IF signal from the upconverter240and TX RF LO signals from a TX RF LO signal generator277, and provide an upconverted RF signal to phase shift circuitry281. While PLL292is illustrated inFIG.2Bas being shared by the signal generators290,277, a respective PLL for each signal generator may be implemented.

In an exemplary embodiment, components in the phase shift circuitry281may comprise one or more adjustable or variable phased array elements, and may receive one or more control signals from the data processor210over connection294and operate the adjustable or variable phased array elements based on the received control signals.

In an exemplary embodiment, the phase shift circuitry281comprises phase shifters283and phased array elements287. Although three phase shifters283and three phased array elements287are shown for ease of illustration, the phase shift circuitry281may comprise more or fewer phase shifters283and phased array elements287.

Each phase shifter283may be configured to receive the RF transmit signal from the upconverter275, alter the phase by an amount, and provide the RF signal to a respective phased array element287. Each phased array element287may comprise transmit and receive circuitry including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifters283may be incorporated within respective phased array elements287.

The output of the phase shift circuitry281is provided to an antenna array248. In an exemplary embodiment, the antenna array248comprises a number of antennas that typically correspond to the number of phase shifters283and phased array elements287, for example such that each antenna element is coupled to a respective phased array element287. In an exemplary embodiment, the phase shift circuitry281and the antenna array248may be referred to as a phased array. Although shown inFIG.2Bas having a particular architecture, the phase shift circuitry281may comprise other architectures depending on application.

In a receive direction, an output of the phase shift circuitry281is provided to a downconverter285. In an exemplary embodiment, the downconverter285may comprise an I/Q generation function291and a downconversion mixer286. In an exemplary embodiment, the mixer286downconverts the receive RF signal provided by the phase shift circuitry281to an IF signal according to RX RF LO signals provided by an RX RF LO signal generator279. The I/Q generation function291receives the IF signal from the mixer286and generates I and Q signals for the downconverter260, which downconverts the IF signals to baseband, as described above. While PLL282is illustrated inFIG.2Bas being shared by the signal generators280,279, a respective PLL for each signal generator may be implemented.

In some embodiments, the upconverter275, downconverter285, and the phase shift circuitry281are implemented on a common IC. In some embodiments, the summing function278and the I/Q generation function291are implemented separate from the mixers276and286such that the mixers276,286and the phase shift circuitry281are implemented on the common IC, but the summing function278and I/Q generation function291are not (e.g., the summing function278and I/Q generation function291are implemented in another IC coupled to the IC having the mixers276,286). In some embodiments, the LO signal generators277,279are included in the common IC. In some embodiments in which phase shift circuitry is implemented on a common IC with276,286,277,278,279, and/or291, the common IC and the antenna array248are included in a module, which may be coupled to other components of the transceiver220via a connector. In some embodiments, the phase shift circuitry281, for example, a chip on which the phase shift circuitry281is implemented, is coupled to the antenna array248by an interconnect. For example, components of the antenna array248may be implemented on a substrate and coupled to an integrated circuit implementing the phase shift circuitry281via a flexible printed circuit.

In some embodiments, both the architecture illustrated inFIG.2Aand the architecture illustrated inFIG.2Bare implemented in the same device. For example, a wireless device110or200may be configured to communicate with signals having a frequency below about 10 GHz using the architecture illustrated inFIG.2Aand to communicate with signals having a frequency above about 10 GHz using the architecture illustrated inFIG.2B. In devices in which both architectures are implemented, one or more components ofFIGS.2A and2Bthat are identically numbered may be shared between the two architectures. For example, both signals that have been downconverted directly to baseband from RF and signals that have been downconverted from RF to baseband via an IF stage may be filtered by the same baseband filter264. In other embodiments, a first version of the filter264is included in the portion of the device which implements the architecture ofFIG.2Aand a second version of the filter264is included in the portion of the device which implements the architecture ofFIG.2B.

FIG.3shows two exemplary embodiments of a multi-mode, multi-port driver interface. A first exemplary embodiment of a multi-mode, multi-port driver interface300shows a driver amplifier (DA)310, a load line impedance modulation circuit320and communication ports330. The communication ports330may comprise communication port 1341, communication port 2343, communication port 3345, and communication port 4347. In an exemplary embodiment, the communication ports330may also be referred to as output ports. The load line impedance modulation circuit320comprises an adjustable resistance322, an adjustable capacitance324, a magnetic circuit326, an adjustable capacitance313, adjustable resistances328, and diplexers329. The adjustable resistances328may be implemented in a number of ways and inFIG.3, are shown as comprising a resistor and two switches. For example, the adjustable resistance333may comprise a resistor334and switches335and337. The adjustable resistances331,336and338are similar to the adjustable resistance333. The DA310may be configured to receive an intermediate frequency (IF) signal and provide an amplified IF signal to the communication ports330. However, although IF signals are used in this example, the frequencies processed by the DA310and load line impedance modulation circuit320might be the actual transmission frequencies. Further, the communication ports330may comprise or be coupled to respective IC or chip inputs/outputs. A receive signal(s) may be provided to one or more of the communication ports330from a component external to the IC or chip, and the diplexer(s)329may route the receive signal to a receive chain (not illustrated). The adjustable resistance322, the adjustable capacitance324, the adjustable capacitance313, and the adjustable resistances328may be controlled by a control signal from the data processor210or another control circuit.

A second exemplary embodiment of a multi-mode, multi-port driver interface301shows a driver amplifier (DA)350, a load line impedance modulation circuit370and communication ports380. The communication ports380may comprise communication port 1391, communication port 2393, communication port 3395, and communication port 4397. In an exemplary embodiment, the communication ports380may also be referred to as output ports. The load line impedance modulation circuit370comprises an adjustable resistance372, an adjustable capacitance374, a magnetic circuit376, an adjustable capacitance373, adjustable resistances378, and diplexers379. The adjustable resistances378may be implemented in a number of ways and inFIG.3, are shown as comprising a resistor and two switches. For example, the adjustable resistance381may comprise a resistor382and switches361and362; the adjustable resistance383may comprise a resistor384and switches363and364; the adjustable resistance385may comprise a resistor386and switches365and366; and the adjustable resistance387may comprise a resistor388and switches367and368. The DA350may be configured to receive an IF signal and provide an amplified IF signal to the communication ports380. However, although IF signals are used in this example, the frequencies processed by the DA350and load line impedance modulation circuit370might be the actual transmission frequencies. Further, the communication ports380may comprise or be coupled to respective IC or chip inputs/outputs. A receive signal(s) may be provided to one or more of the communication ports380(in this example, all of the communication ports380) from a component external to the IC or chip, and the diplexer(s)379may route the receive signal to a receive chain (not illustrated). The adjustable resistance372, the adjustable capacitance374, the adjustable capacitance373, and the adjustable resistances378may be controlled by a control signal from the data processor210or another control circuit.

In an exemplary embodiment, the multi-mode, multi-port driver interface300may be configured to support a single communication port, in this example, communication port 2343, whereby the switch337is conductive and the switch335is non-conductive, thereby coupling the communication port 2343to the magnetic circuit326. Further, the switches in the adjustable resistances331,336and338are all non-conductive, such that communication port 1341, communication port 3345, and communication port 4347are not connected to the magnetic circuit326or to the DA310. In the exemplary embodiment where the switch337is conductive, thereby coupling the communication port 2343to the magnetic circuit326, the switch335is non-conductive, such that the resistor334does not contribute to excess loss. In this exemplary embodiment, the loss is minimized and the DA310provides higher gain and/or improved power efficiency. Although in this example a UE mode is used to support a single communication port, in other embodiments of a UE mode two or more outputs may be sent to two or more communication ports. In an exemplary embodiment, the multi-mode, multi-port driver interface300may be configured to support a user equipment (UE) in a low power mode (e.g., lower in power relative to a high power mode).

In an exemplary embodiment, the multi-mode, multi-port driver interface301may be configured to support multiple communication ports, such as, for example, two or four communication ports, such as to support a CPE in CPE mode or in CSM/FSM mode. In this example, all communication ports380are supported by the DA350, whereby the adjustable resistances378all provide a relatively low resistance, thereby coupling all communication ports380to the magnetic circuit376through respective adjustable resistances381,383,385and387. In this example, the switches361,363,365and367are all non-conductive and the switches362,364,366and368are all conductive, such that respective resistances382,384,386and388provide a relatively low resistance between the magnetic circuit376and the communication ports380, where all of the communication ports380are enabled. In an exemplary embodiment, the respective resistances382,384,386and388may be configured to provide a relatively low resistance, on the order of 30 ohm to 40 ohm. In an exemplary embodiment, the multi-mode, multi-port driver interface301may be configured to support a customer premises equipment (CPE) in a high power mode (e.g., higher in power relative to the low power mode). In an exemplary embodiment, the multi-mode, multi-port driver interface301may be configured to support between one (1) and four (4) communication ports at the same frequency. In an exemplary embodiment, the multi-mode, multi-port driver interface300or301may be configured to support more or fewer communication ports, with four (4) communication ports being illustrated as an example only. In some embodiments, a single DA and a single magnetic circuit may support up to eight (8) or more communication ports.

In an exemplary embodiment, using a single DA (such as the DA310or the DA350) to support multiple communication ports reduces circuit area, reduces local oscillator (LO) signal leakage, and helps to minimize or eliminate the DA-dependent RSB discrepancy among output ports mentioned above because a common DA is used to drive communication ports 1 through 4 instead of using a respective individual DA for each communication port.

Although in this example a CPE mode is used to support all four communication ports, in other embodiments fewer than all available communication ports may be used for a CPE mode.

The load line impedance modulation circuit320can be selectively configured to provide a higher load line impedance in UE (low power) mode, while the load line impedance modulation circuit370can be selectively configured to provide a lower load line impedance in CPE (high power) mode. As used herein, the term “load line” impedance refers to the impedance presented to the output of a driver amplifier, such as DA310and DA350, and the term “load line impedance modulation” refers to adjusting the load line impedance based on a number of factors including the number of communication ports coupled to a single driver amplifier (DA). For example, selectively adjusting the load line impedance may be desirable to strike a balance between power consumption and linearity of the DA310and the DA350.

In an example, the multi-port driver interface300or301may be coupled between the upconverter240and the upconverter275. In another example, the multi-port driver interface300or301may be coupled between the summing function278and the upconversion mixer276.

In an example, each communication port may be coupled to and may drive a separate mmwIC. For example, in a UE implementation, the communication port 2343may be coupled to a single mmwIC352over an interconnection344. However, in a CPE implementation, the communication port 1391and the communication port 2393may be coupled to a mmwIC354over interconnections392and394; and the communication port 3395and the communication port 4397may be coupled to a mmwIC356over interconnections396and398. In another example, each of the communication ports391,393,395,397are coupled to a respective mmwIC over a respective interconnection. The mmwICs352,354,356may include elements of the phase shift circuitry281, upconverter,275, and/or downconverter285, and may be coupled to the antenna array248. One or more of the mmwICs may be packaged together with the antenna array248in a module or the mmwIC may be implemented separate from the antenna array248and coupled thereto. In an example, the mmwIC354and the mmwIC356(and/or any other mmwICs coupled to the multi-port driver interface301) may collectively implement some or all of a phased array system. In another example, one or more mmwICs coupled to the communication ports391,393,395,397implement a phased array separate from the other mmwICs. Other numbers of mmwICs may be coupled to one or more communication ports than illustrated, with the configuration shown inFIG.3as an example only. In an exemplary embodiment, the mmwIC352, mmwIC354and mmwIC356may be configured to convert an IF signal to a mmw signal. In an exemplary embodiment, the load line impedance modulation circuits320and370may be located on one IC and the mmwIC352, mmwIC354and mmwIC356may be separate ICs coupled thereto by respective interconnects. In an exemplary embodiment, the interconnects344,392,394,396and398may comprise circuit traces, coaxial cable, or other connections. In some UE configurations, there may be a single IC supporting a phased array/module. In a CPE, the ICs may be tiled, or layered, to support phased arrays having a larger number of elements. In an exemplary embodiment, a single DA and magnetic circuit, such as DA350and magnetic circuit376, may be coupled to multiple communication ports to process a signal at a single frequency.

In some examples, one or more of the communication ports341,343,345,347,391,393,395,397are coupled to an antenna without passing through a mmwIC. For example, one of the communication ports may be coupled to directly to an antenna or coupled to an antenna through a power amplifier module that does not include frequency conversion components. Such configuration may be advantageous when the output frequency of the multi-port driver interface300or301is the same as a frequency at which the antenna is configured to communicate.

FIG.4shows an exemplary embodiment of a multi-mode, multi-port driver interface implemented in a portion of a multiple-band communication system400. In an exemplary embodiment, the communication system400includes a high band (HB) mixer402and a low band (LB) mixer404. The high band mixer402comprises a high band in-phase (I) mixer403aand a high band quadrature (Q) mixer405a. The low band mixer404comprises a low band in-phase (I) mixer403band a low band quadrature (Q) mixer405b. Each of the mixers402and404may be an example of the upconversion mixers241aand241bofFIG.2B. Each of the mixers402and404may receive in-phase (I) and quadrature (Q) local oscillator (LO) signals from, for example, TX LO signal generator290ofFIG.2B, and may receive in-phase (I) and quadrature (Q) baseband signals from amplifiers234aand234bofFIG.2B, and may provide in-phase (I) and quadrature (Q) communication signals at an intermediate frequency (IF). The IF signals may be provided to adjustable resistances411aand411b, adjustable capacitances415aand415b, and magnetic circuits417aand417b. The adjustable resistances411aand411b, and the adjustable capacitances415aand415b, may be controlled by a control signal from the data processor210or another control circuit. A low drop out voltage regulator (LDO)416may be coupled to the magnetic circuits417aand417b.

The communication system400includes an HB DA406configured to receive the I and Q outputs of the magnetic circuit417avia capacitances407and409; and an LB DA408configured to receive the output of the magnetic circuit417bvia capacitances423and425. The HB DA406and the LB DA408are coupled to a load line impedance modulation circuit420. In an exemplary embodiment, the load line impedance modulation circuit420may be similar to the load line impedance modulation circuits320and370ofFIG.3.

The load line impedance modulation circuit420may comprise adjustable resistances422aand422b, adjustable capacitances424aand424b, magnetic circuits426aand426b, a switch circuit411coupled to the output of the DA406via the magnetic circuit426a, and a switch circuit471coupled to the output of the DA408via magnetic circuit426b. In an exemplary embodiment, the switch circuit411may comprise a switch427and an adjustable capacitance413. The switch427may be an output select switch and the adjustable capacitance413may be similar to the adjustable capacitance313ofFIG.3. In an exemplary embodiment, the switch circuit471may comprise a switch477and an adjustable capacitance473. The switch477may be an output select switch and the adjustable capacitance473may be similar to the adjustable capacitance373ofFIG.3. The adjustable capacitance413and the adjustable capacitance473contribute to the selectable load line impedance modulation provided by the load line impedance modulation circuit420.

The load line impedance modulation circuit420may also comprise adjustable resistances428. Diplexers429and communication ports430may be coupled to the adjustable resistances428. The adjustable resistances428may be similar to the adjustable resistances328and378ofFIG.3, the diplexers429may be similar to the diplexers329and379ofFIG.3, and the communication ports430may be similar to the communication ports330and380ofFIG.3. The communication ports430may comprise communication port 1441, port 2443, port 3445, and port 4447. The adjustable resistances428may comprise adjustable resistances451,453,455and457. The adjustable resistances451,453,455and457may be adjusted by a control signal from the data processor210or another control circuit. The resistance provided by each adjustable resistance451,453,455and457may be selectively controlled to provide resistance between zero (0) ohms (a short circuit), and a resistance value that is dependent upon application. In an exemplary embodiment, each adjustable resistance451,453,455and457may be selectively controlled to provide a resistance that ranges between 20 ohms and 70 ohms. However, each adjustable resistance451,453,455and457may be selectively controlled to provide a resistance lower than 20 ohms and greater than 70 ohms.

The adjustable resistance422aand422b, the adjustable capacitance424aand424b, the adjustable capacitance413, the adjustable capacitance473, the switch427, the switch477and the adjustable resistances428may be controlled by a control signal from the data processor210or another control circuit.

In an exemplary embodiment, the load line impedance modulation circuit420provides a selectable load line impedance, and the adjustable resistances428create a resistive splitter for output impedance matching.

As described previously, each of the communication ports may be individually and/or independently selected/enabled for use as an output. Switches may be used to implement this selectability. For example, switches may be integrated in the adjustable resistances451,453,455,457as described with respect toFIG.3. In other examples, the adjustable resistances451,453,455,457may be configured to provide a high impedance (e.g., to act as an “open” circuit) using means other than a switch. In yet other examples, a switch may be included in series with each of the adjustable resistances451,453,455,457(e.g., between the switches427,477, and a respective one of the adjustable resistances).

FIG.5shows an exemplary embodiment500of the load line impedance modulation circuit320ofFIG.3. The load line impedance modulation circuit320receives the output of the DA310and includes the magnetic circuit326located in a balun model circuit510, the adjustable resistances328, an inductance511, the diplexer329and a communication port330. The adjustable resistance328may also comprise a resistance333, a capacitance503and a resistance504. The exemplary embodiment of the load line impedance modulation circuit320may be implemented when the DA310is in a low power mode, for example, in UE mode, such as shown using the multi-mode, multi-port driver interface300ofFIG.3. In an exemplary embodiment, a relatively higher DA load line impedance (˜80 ohm) may be provided by the load line impedance modulation circuit320in UE mode. The balun model circuit510includes an adjustable capacitance513and an inductive element507, which can be used to provide the load line impedance modulation as described herein. The adjustable capacitance513may be an example of the adjustable capacitance413ofFIG.4. The resistance333illustrates the on-resistance of the adjustable resistance333when a single communication port330is coupled to the DA310. For example, the resistance333will exhibit a relatively low on-resistance (on the order of 1-3 ohms) to minimize loss in a mode where one communication port, such as the communication port 2343ofFIG.3, is coupled to the DA310. The adjustable resistances328provide output matching and power splitting functionality. The size of each resistance in the adjustable resistances328may be dependent on a number of factors, including, for example, a tradeoff between resistor size (resistance value) and insertion loss. For example, the size of each resistance in the adjustable resistances328may be chosen to meet an output impedance matching requirement by having the ability to provide a selectable resistance, such as, for example, a high resistance in a first mode and a low resistance in a second mode. There is a design tradeoff between the loss and output matching when choosing the size of the resistor and the resistance provided by the adjustable resistances328.

FIG.6shows an exemplary embodiment600of the load line impedance modulation circuit370ofFIG.3. The load line impedance modulation circuit370receives the output of the DA350and comprises the magnetic circuit376located in a balun model circuit610, the adjustable resistances378, an inductance611, the diplexer379and a communication port380. The exemplary embodiment of the load line impedance modulation circuit370may be implemented when the DA350is in a high power mode, for example, in CPE mode, where more than one communication port may be coupled to a DA. In an exemplary embodiment, a relatively lower DA load line impedance (˜40 ohm) may be provided by the load line impedance modulation circuit370in CPE mode. The magnetic circuit376includes an adjustable capacitance673and an inductive element607, which can be used to provide the load line impedance modulation described herein. The adjustable capacitance373may be an example of the adjustable capacitance473ofFIG.4. The adjustable resistance378illustrates the on-resistance of the adjustable resistances378when multiple communication ports380are coupled to the DA350. For example, the resistances381,383,385and387will exhibit a relatively high on-resistance (on the order of 70 ohms) to maximize power in a mode where more than one communication port, such as the communication port 1391, the communication port 2393, the communication port 3395and the communication port 4397ofFIG.3, are coupled to the DA350. In an exemplary embodiment, the adjustable resistances378may comprise resistors382,384,386and388.

FIG.7is a diagram700showing an effect of driver amplifier load line impedance modulation for UE modes and for CPE modes. The vertical axis represents impedance (in ohms) and the horizontal axis represents frequency (in GHz). The traces702,704and706show load line impedance over frequency in UE mode. The traces752,754and756show load line impedance over frequency in CPE mode. In an exemplary embodiment, the adjustable components in the load line impedance modulation circuit320, the load line impedance modulation circuit370, or the load line impedance modulation circuit420may be adjusted to obtain a desired impedance at a desired frequency. In an exemplary embodiment, the desired load line impedance may be dependent upon the number of communication ports being coupled to a DA. In an exemplary embodiment, the desired load line impedance may be dependent upon the operating mode of a communication device.

In an exemplary embodiment, a lower DA load line impedance is desirable for implementations in which multiple communication ports are coupled to a single DA to improve DA linearity and satisfy the relatively higher power output (Pout).

In an exemplary embodiment, a higher DA load line impedance is desirable for implementations in which a single communication port is coupled to a single DA to improve efficiency at lower output power.

In an exemplary embodiment, a load line impedance modulation circuit allows a single DA to be optimized for linearity and efficiency.

In an exemplary embodiment, a load line impedance modulation circuit reduces the need for an increase in DA supply voltage for a higher power (CPE) mode.

FIG.8shows two alternative exemplary embodiments of a multi-mode, multi-port driver interface. A first exemplary embodiment of a multi-mode, multi-port driver interface800is similar to the multi-mode, multi-port driver interface300ofFIG.3, and identical elements are numbered according to the convention8XX, where an element inFIG.8labeled8XX is similar to an element inFIG.3labeled3XX, and will not be described again. A second exemplary embodiment of a multi-mode, multi-port driver interface801is similar to the multi-mode, multi-port driver interface301ofFIG.3, and identical elements are identically numbered and will not be described again.

In an exemplary embodiment, the multi-mode, multi-port driver interface800includes a transmission line805located between the magnetic circuit326and the adjustable resistances378. In an exemplary embodiment, an approximate 50 ohm impedance at the output of the magnetic circuit326corresponds to an approximate 50 ohm impedance at the input to the adjustable resistances328(adjustable resistance333in this example).

In an exemplary embodiment, the multi-mode, multi-port driver interface801includes a transmission line855located between the magnetic circuit376and the switches377. In an exemplary embodiment, an approximate 50 ohm impedance at the output of the magnetic circuit376corresponds to an approximate (R+50)/4 ohm impedance at the input to the adjustable resistances378(all of the adjustable resistances378in this example).

FIG.9shows a table900illustrating RSB variation over four (4) ports in an exemplary high band (HB) CPE communication device in the 12.1 GHz band. The RSB variation for ports V1, V2, V3and V4, shown by reference numeral910fall within 3.1 dBc of each other, while the RSB variation for ports H1, H2, H3and H4, shown by reference numeral920fall within 1.4 dBc of each other. This illustrates a behavior that is not port dependent.

FIG.10is a flow chart1000describing an example of the operation of a method for signal processing. The blocks in the method1000can be performed in or out of the order shown, and in some embodiments, can be performed at least in part in parallel.

In block1002, output ports are selectively coupled to an amplifier through a load line impedance modulation circuit. For example, one or more communication ports330or380may be selectively coupled to a driver amplifier310or350through load line impedance modulation circuit320or370. For example, a number (e.g., one through four in examples described above) of output ports may be selectively coupled to the amplifier.

In block1004, the load line impedance of the interface circuit is selectively adjusted based on the selectively coupled ports. For example, the load line impedance of the multi-mode, multi-port driver interface300ofFIG.3may be selectively adjusted depending on the number of selectively coupled communication ports330or380.

In block1006, a communication signal is amplified. For example, the driver amplifier310or350may amplify the communication signal.

In block1008, the amplified communication signal may be output via the load line impedance modulation circuit through the selectively coupled output ports. For example, the amplified communication signal may be output via a load line impedance modulation circuit320or370through the selectively coupled output ports330or380.

FIG.11is a functional block diagram of an apparatus for signal processing. The apparatus1100comprises means1102for selectively coupling (a number of) output ports to an amplifier through a load line impedance modulation circuit. In certain embodiments, the means1102for selectively coupling output ports to an amplifier through a load line impedance modulation circuit can be configured to perform one or more of the functions described in operation block1002of method1000(FIG.10). In an exemplary embodiment, the means1102for selectively coupling output ports to an amplifier through a load line impedance modulation circuit may comprise one or more switches and/or adjustable resistances configured to selectively couple communication ports330or380to a driver amplifier310or350through load line impedance modulation circuit320or370.

The apparatus1100may also comprise means1104for selectively adjusting the load line impedance of the interface circuit based on the (number of) selectively coupled ports. In certain embodiments, the means1104for selectively adjusting the load line impedance of the interface circuit based on the selectively coupled ports can be configured to perform one or more of the functions described in operation block1004of method1000(FIG.10). In an exemplary embodiment, the means1104for selectively adjusting the load line impedance of the interface circuit based on the selectively coupled ports may comprise elements (e.g., a resistor, capacitor, switch, balun or transformer, etc.) of load line impedance modulation circuit320or370, or a controller or process coupled thereto and configured to selectively adjusting the load line impedance of the multi-mode, multi-port driver interface300ofFIG.3depending on a number of selectively coupled output ports.

The apparatus1100may also comprise means1106for amplifying a communication signal. In certain embodiments, the means1106for amplifying a communication signal can be configured to perform one or more of the functions described in operation block1006of method1000(FIG.10). In an exemplary embodiment, the means1106for amplifying a communication signal may comprise the driver amplifier310or350.

The apparatus1100may also comprise means1108for outputting an amplified communication signal via a load line impedance modulation circuit through the selectively coupled output ports. In certain embodiments, the means1108for outputting an amplified communication signal via a load line impedance modulation circuit through the selectively coupled output ports can be configured to perform one or more of the functions described in operation block1008of method1000(FIG.10). In an exemplary embodiment, the means1108for outputting an amplified communication signal via a load line impedance modulation circuit through the selectively coupled output ports may comprise any elements of the multi-port driver interface300or301configured to convey the amplified communication signal through the load line impedance modulation circuit320or370and to the selectively coupled output ports330or380.

Implementation examples are described in the following numbered clauses:1. A transceiver interface circuit, comprising a driver amplifier (DA); a load line impedance modulation circuit coupled to the DA; and multiple selectable output ports coupled to the load line impedance modulation circuit, an impedance presented by the load line impedance modulation circuit being adjustable dependent on at least a number of output ports coupled to the load line impedance modulation circuit.2. The transceiver interface circuit of clause 1, wherein an impedance presented by the load line impedance modulation circuit corresponds to a high impedance when the transceiver interface circuit is configured for one output port in a user equipment (UE) in a low power mode.3. The transceiver interface circuit of any of clauses 1 or 2, wherein an impedance presented by the load line impedance modulation circuit corresponds to a low impedance when the transceiver interface circuit is configured for at least two output ports in a customer premises equipment (CPE) in a high power mode.4. The transceiver interface circuit of any of clauses 1 through 3, wherein the load line impedance modulation circuit is implemented at an intermediate frequency (IF) in a multiple-band millimeter-wave (mmW) communication system.5. The transceiver interface circuit of any of clauses 1 through 4, wherein the load line impedance modulation circuit comprises a resistive splitter configured to provide power splitting among the output ports.6. The transceiver interface circuit of any of clauses 1 through 5, wherein the DA comprises a first DA configured for a first band, and wherein the interface circuit further comprises a second DA configured for a second band, the second DA coupled to the multiple selective output ports through at least a portion of the load line impedance modulation circuit.7. The transceiver interface circuit of any of clauses 1 through 6, wherein the DA is configured to provide a transmit signal to the multiple selective output ports, and wherein the multiple selective output ports are configured to receive a receive signal from components external to the transceiver in which the transceiver interface circuit is disposed.8. The transceiver interface circuit of any of clauses 1 through 7, wherein the transceiver interface circuit is coupled to a plurality of millimeter wave integrated circuits forming a phased array system.9. The transceiver interface circuit of any of clauses 1 through 7, wherein the transceiver interface circuit is located on a first integrated circuit (IC) and is coupled to a second integrated circuit (IC) by an interconnect, the second IC configured to convert an intermediate frequency (IF) signal to a millimeter wave signal.10. A method for communication, comprising selectively coupling a number of output ports to an amplifier through a load line impedance modulation circuit; selectively adjusting a load line impedance of the communication device based on the number of selectively coupled selected mode output ports; amplifying a communication signal; and outputting the amplified communication signal via the load line impedance modulation circuit through the selectively coupled output ports.11. The method of clause 10, further comprising selectively coupling one output port to the amplifier in a user equipment (UE) mode.12. The method of clause 10, further comprising selectively coupling two or four output ports to the amplifier in a customer premises equipment (CPE) mode.13. The method clause 11, selectively adjusting the load line impedance to a relatively high impedance when one output port is selected in the UE mode in a low power mode.14. The method of clause 12, further comprising selectively adjusting the load line impedance to a relatively low impedance when more than one output port is selected in the CPE mode in a high power mode.15. The method of any of clauses 10 through 14, further comprising configuring the amplifier as a first driver amplifier (DA) for a first band; configuring a second amplifier as a second DA for a second band; and selectively coupling the second DA to the one or more output ports through at least a portion of the load line impedance modulation circuit.16. The method of any of clauses 10 through 15, further comprising configuring the amplifier to provide a transmit signal to the one or more selectively coupled output ports, and wherein the one or more selectively coupled output ports are configured to receive a receive signal from components external to a transceiver of the communication device.17. A device, comprising means for selectively coupling a number of output ports to an amplifier through a load line impedance modulation circuit; means for selectively adjusting a load line impedance based on the number of selectively coupled output ports; means for amplifying a communication signal; and means for outputting the amplified communication signal via the load line impedance modulation circuit through the selectively coupled output ports.18. The device of clause 17, further comprising means for selectively coupling one output port to the amplifier in a user equipment (UE) mode.19. The device of clause 17, further comprising means for selectively coupling two or four output ports to the amplifier in a customer premises equipment (CPE) mode.20. The device of clause 18, further comprising means for selectively adjusting the load line impedance to a relatively high impedance when one output port is selected in the UE mode in a low power mode.21. The device of clause 19, further comprising means for selectively adjusting the load line impedance to a relatively low impedance when more than one output port is selected in the CPE mode in a high power mode.22. The device of any of clauses 17 through 21, wherein the amplifier is configured as an amplifier for a first band; wherein the device further comprises: means for amplifying signals for a second band; and means for selectively coupling the means for amplifying to the one or more output ports through at least a portion of the load line impedance modulation circuit.23. The device of any of clauses 17 through 22, further comprising means for configuring the amplifier to provide a transmit signal to the one or more selectively coupled output ports, and wherein the one or more selectively coupled output ports are configured to receive a receive signal from components external to an integrated circuit including the means for amplifying.24. A load line impedance modulation circuit, comprising a magnetic circuit; an adjustable capacitance coupled to an output of the magnetic circuit; and a plurality of adjustable resistances coupled to an output of the magnetic circuit, wherein the plurality of adjustable resistances are configured to select from available output ports, an impedance presented by the load line impedance modulation circuit being adjustable dependent on at least a number of selected output ports.25. The load line impedance modulation circuit of clause 24, wherein an impedance presented by the load line impedance modulation circuit corresponds to a high impedance when configured for one selected output port in a user equipment (UE) in a low power mode.26. The load line impedance modulation circuit of clause 24, wherein an impedance presented by the load line impedance modulation circuit corresponds to a low impedance when configured for more than one selected output port in a customer premises equipment (CPE) in a high power mode.27. The load line impedance modulation circuit of any of clauses 24 through 26, wherein the load line impedance modulation circuit is implemented at an intermediate frequency (IF) in a multiple-band millimeter-wave (mmW) communication system.28. The load line impedance modulation circuit of any of clauses 24 through 26, wherein the plurality of adjustable resistances comprises a resistive splitter configured to provide power splitting among the output ports.29. The load line impedance modulation circuit of any of clauses 24 through 28, wherein the plurality of adjustable resistances are configured to select two output ports or four output ports.30. The load line impedance modulation circuit of any of clauses 24 through 29, wherein each of the plurality of adjustable resistances comprises a first switch in parallel with a resistor and a second switch.

The circuit architecture described herein described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

An apparatus implementing the circuit described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.

Although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.