Patent ID: 12218119

DETAILED DESCRIPTION

One example of a proposed microelectronic device assembly to address the issues mentioned above, would comprise a host device, for example, a GPU, and a memory device comprising multiple stacked memory die, for example, high bandwidth memory devices, all mounted to an interposer comprising a semiconductor material (e.g., silicon), which may be characterized as a “core.” The interposer would be, in turn, mounted and operably coupled to a laminate (e.g., organic) substrate for connecting the microelectronic device assembly to higher-level packaging by, for example, discrete conductive elements in the form of balls, bumps or studs of a metal material. The GPU would have integrated SRAM cache memory, which as noted above presents fabrication problems and necessitates the use of TSVs in the GPU. The microelectronic device assembly would locate the memory device over and operably coupled to an interface die being operably coupled to circuitry carried by the interposer, by which circuitry memory die of the memory device would communicate with the host device. TSVs extending through the interposer would, in turn, communicate with a laminate substrate, which might comprise multiple levels of circuitry separated by dielectric material, and which circuitry would be operably coupled to discrete conductive elements on side thereof opposite the interposer for connection to external circuitry.

Another example of a proposed microelectronic device assembly to address the issues mentioned above would employ an interposer comprising a core of semiconductor material (e.g., silicon) with RDLs on opposing sides thereof, each RDL having multiple (e.g., four or more) layers of conductive traces to accommodate the high-speed, high-capacity signal requirements of HBM designs and, specifically HBMx (also termed HBM2, HBM2e, HBM3 and HBM4) designs, incorporating a stack of memory (i.e., DRAM dice) and a host in the form of a graphics processor unit (GPU) or central processor unit (CPU). Applications for such proposed designs would include graphics, client, server, network and high-performance computing. However, fabrication of a silicon interposer bearing back-to-back RDLs presents issues in terms of process cost and complexity and quality control.

Semiconductor (e.g., silicon) interposer structures comprising multiple stacked interposers are disclosed, as well as microelectronic device assemblies including such interposer structures, and methods of fabricating such assemblies.

The following description provides specific details, such as sizes, shapes, material compositions, and orientations in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without necessarily employing these specific details. Embodiments of the disclosure may be practiced in conjunction with conventional fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing an HBM device, a silicon interposer structure, a GPU, CPU or other processor, or a microelectronic device assembly including HBM devices, a GPU, CPU or other processor and a silicon interposer structure. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete HBM device, silicon interposer structure, GPU, CPU or other processor, or a microelectronic device assembly including the foregoing may be performed by conventional fabrication processes known to those of ordinary skill in the art in the semiconductor and electronics industry.

Drawings presented herein are for illustrative purposes only, and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles between surfaces that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale.

As used herein, the terms “comprising,” “including,” “containing,” “characterized by,” and grammatical equivalents thereof are inclusive or open-ended terms that do not exclude additional, unrecited elements or method acts, but also include the more restrictive terms “consisting of” and “consisting essentially of” and grammatical equivalents thereof. As used herein, the term “may” with respect to a material, structure, feature or method act indicates that such is contemplated for use in implementation of an embodiment of the disclosure and such term is used in preference to the more restrictive term “is” so as to avoid any implication that other, compatible materials, structures, features and methods usable in combination therewith should or must be, excluded.

As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are in reference to a major plane of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by earth's gravitational field. A “lateral” or “horizontal” direction is a direction that is substantially parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction that is substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “over,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “over” or “above” or “on” or “on top of” other elements or features would then be oriented “below” or “beneath” or “under” or “on bottom of” the other elements or features. Thus, the term “over” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, the terms “configured” and “configuration” refer to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a predetermined way.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, or even at least 99.9% met.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein the terms “layer” and “film” mean and include a level, sheet or coating of material residing on a structure, which level or coating may be continuous or discontinuous between portions of the material, and which may be conformal or non-conformal, unless otherwise indicated.

As used herein, the term “substrate” means and includes a base material or construction upon which additional materials are formed. The substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. The materials on the semiconductor substrate may include, but are not limited to, semiconductive materials, insulating materials, conductive materials, etc. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

As used herein, the terms “comprising,” “including,” “containing,” “characterized by,” and grammatical equivalents thereof are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps, but also include the more restrictive terms “consisting of” and “consisting essentially of” and grammatical equivalents thereof.

As used herein, the term “may” with respect to a material, structure, feature or method act indicates that such is contemplated for use in implementation of an embodiment of the disclosure and such term is used in preference to the more restrictive term “is” so as to avoid any implication that other, compatible materials, structures, features and methods usable in combination therewith should or must be excluded.

The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.

As described in more detail below, the specification describes various embodiments of a stacked interposer structure comprising multiple, vertically stacked interposers. Embodiments include various configurations of stacked interposers, each interposer of a stack including a semiconductor core, such as a silicon core and bearing a redistribution structure on one side thereof. In embodiments, the redistribution structures include multiple individual redistribution layers. The multiple individual redistribution layers may be implemented, in some embodiments, to provide high bandwidth communication capability between microelectronic devices connected through the interposers.

Additionally, the specification describes incorporation of circuit elements, including active and passive circuit elements that may be formed in an interposer. In some embodiments, the active and passive circuit elements will be formed at least in part in the semiconductor core. In some examples, circuit elements may have one or more bodies formed within the semiconductor core and one or more bodies formed in material structures formed over the semiconductor core.

Referring now to the drawings in more detail, and particularly toFIGS.1A-1E,FIG.1Adepicts a simplified representation of an embodiment of a microelectronic device assembly100including a processor102and multiple memory devices104A,104B,104C,104D, connected to an assembly of stacked interposers106A and106B, each interposer106A and106B comprising semiconductor material (e.g., silicon) in accordance with one or more of the configurations described herein.

As will be apparent to persons skilled in the art, processor102may be any of multiple configurations of a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a controller), a system on a chip (SoC)), or some other form of host device. Memory devices104A,104B,104C,104D may be of the same or different forms; and any of the memory devices may be either a single die or a stack of interconnected memory die, as discussed in more detail in reference toFIG.1E. The representation ofFIG.1Adepicts each memory device104A,104B,104C,104D as a stack of multiple memory die108A-108H. In some embodiments, the memory devices104A-104D coupled to stacked interposers106A and106B may all be of comparable heights. Non-limiting examples of existing memory devices104A-104D include JEDEC-standard HBM memory devices and Hybrid Memory Cube (HMC) memory devices, both HBM and HMC assemblies comprising multiple, vertically stacked. DRAM die. However, HMC memory devices employ a TSV-equipped logic die, whereas HBM memory devices do not.

The processor102may exchange information with one or more of memory devices104A,104B,104C,104D using signals communicated over signal paths formed at least in part within and between interposers106A and106B. Such signal paths include a path that a message or transmission may take in communicating from a transmitting component to a receiving component. In some cases, a signal path may be a conductor coupled with at least two components, where the conductor allows electrons to flow between the at least two components. In some cases, the signal path may be formed at least in part in a wireless medium as in the case for wireless communications (e.g., radio frequency (RF) or optical). In some examples, stacked interposers106A and106B will be coupled to an external structure, such as a package substrate, a motherboard, etc., to form part of a larger system.

In some applications, microelectronic device assembly100may benefit from a high-speed connection between the processor102and one or more of memory devices104A,104B,104C,104D. As a result, in some examples, one or more of memory devices104A,104B,104C,104D will support applications, processes, or processors that have multiple terabytes per second (TB/s) bandwidth needs. Such applications may include a serializer/deserializer (“SerDes”) between the memory and a processor or other logic devices requiring high bandwidth. Satisfying such a bandwidth constraint within an acceptable energy budget may pose challenges in certain contexts.

The memory devices104A,104B,104C,104D and interposers106A and106B may be configured such that the signal path between memory cells in the memory devices104A,104B,104C,104D and the processor102are as short as the material properties, operating environment, component layout, and application allow. For example, the memory devices104A,104B,104C,104D may be bufferless memory devices with a point-to-point connection between the host device and the memory array. In other examples, the data channels coupling a memory device104A,104B,104C,104D with the processor102may comprise a point-to-many configuration, with one pin of the processor102coupled with corresponding pins of at least two memory arrays (which may be located in the same or different memory die108A-108H, and/or memory devices104A-104D).

Many interposers may be formed to have multiple arrays of contacts configured to interconnect with each of multiple devices (such as, in the example ofFIG.1A, processor102and memory devices104A-104D). For purposes of the present description, each of the depicted devices is coupled to interposer106A at a respective mounting site; and at each mounting site interposer106A includes one or more arrays of contacts arranged and configured to engage complementary arrays of contacts on each of processor102and memory devices104A-104D). A second interposer106B is stacked under interposer106A, and functions in cooperation with interposer106A as a unit for signal communication between processor102, memory devices104A-104D, and higher-level packaging.

FIG.1Bdepicts a top elevation of one implementation of the microelectronic device assembly100ofFIG.1A, andFIG.1Cdepicts a schematic side elevation. As shown, memory devices104A-104D are located at peripheral sites on interposer106A on laterally opposing sides of processor102, in this instance comprising, for example, a GPU. Optionally, and as shown in broken lines inFIG.1Bwithin the boundaries of processor102, cache memory in the form of SRAM140has been fabricated over an active surface of the silicon of interposer106A to reside under processor102and operably couple processor102to memory devices104A-104D through circuit traces of a Back End of Line (BEOL) structure B (FIG.1C) carried by interposer106A over the active surface of the silicon to memory devices104A-104D and to circuitry external to microelectronic device assembly100through cooperatively configured and operably coupled interposer106B. However, such a memory configuration is not essential to implementation of embodiments of the present disclosure, and cache memory may, as noted, above, be incorporated in the GPU or reside under the GPU. BEOL structure B comprises multiple layers, each comprising a dielectric material and a level of conductive traces, the various conductive levels being vertically interconnected, as known to those of ordinary skill in the art, and may function as a redistribution structure as further described below. Also as shown inFIG.1Bin broken lines adjacent the boundaries of each memory device104A-104D, interface circuitry segments120A-120D have been fabricated over the active surface of the silicon of interposer106A to reside, respectively, immediately below locations of each of memory devices104A-104D and operably couple memory devices104A-104D to processor102through conductive traces of BEOL structure B. Circuitry of interposer106A is operably coupled to circuitry of interposer106B which, in turn, may, optionally, be coupled to circuitry of laminate substrate106L through TSVs extending through interposers106A and106B, circuitry of laminate substrate106L being operably coupled to discrete conductive elements110for connection to higher-level packaging. Interposer106B includes a redistribution structure fabricated by BEOL processing and comprising multiple redistribution layers (RDLs), each RDL comprising a dielectric material and a level of conductive traces, the conductive traces being operably coupled to conductive paths of BEOL structure B through TSVs.

FIG.1Ddepicts a side elevation of another implementation of the microelectronic device assembly100ofFIG.1A. As depicted inFIG.1D, a laminate substrate is omitted from the assembly, in lieu of which, interposer106B is operably coupled to discrete conductive elements110for connection to higher-level packaging. Each interposer106A,106B includes a redistribution structure RS comprising multiple redistribution layers (RDLs), each RDL, comprising a dielectric material and a level of conductive traces. In one embodiment (not indicated inFIG.1D), the redistribution structure RS of interposer106B faces away from interposer106A, and carries discrete conductive elements110on under-bump metallization (UBM) as is known to those of ordinary skill in the art. In another embodiment and as shown inFIG.1D, the redistribution structure RS of interposer106B faces interposer106A, and discrete conductive elements110for connection to higher-level packaging are operably coupled to TSVs extending from the redistribution structure RS through the core of semiconductor material of interposer106B for connection to higher-level packaging.

In the embodiment ofFIGS.1A through1D, it will be apparent to those of ordinary skill in the art that optional placement of cache memory in the form of SRAM in close proximity to, and immediately below the GPU reduces signal length and latency while relieving the GPU of SRAM which would otherwise consume valuable real estate and simplifying the processor design.

FIG.1Edepicts an example memory device118suitable for use in microelectronic device assembly100ofFIG.1Aas memory devices104A-104D. Memory device118includes, as an example, eight individual memory die108A-108H that are vertically stacked and interconnected. As noted previously, memory device118may include only a single memory die, or any other number of stacked memory die, for example, two memory die, four memory die, and/or more than eight memory die, for example, twelve, sixteen, thirty-two or sixty-four memory die.

One example structure for forming the vertical interconnections includes multiple through silicon vias (“TSVs”). Though the term “through silicon vias” (“TSVs”) taken literally suggests vias that extend through a silicon body, the term is conventionally used in the art to refer to vertical interconnects extending through not only silicon, and not only semiconductors, but to vertical interconnects extending through other materials as well. The term is used herein in this broader meaning, and as used herein does not imply that the described vias may extend only through a silicon body.

Each memory die108A-108H includes multiple memory cells that are programmable to store different logic states. For example, each memory cell may be programmed to store one or more logic states (e.g., a logic ‘0,’ a logic ‘1,’ a logic ‘00’ a logic ‘01,’ a logic ‘10,’ a logic ‘11’). The memory die may use one or more of different storage technologies to store data including DRAM, SRAM, ferroelectric RAM (FeRAM), Resistive RAM (RRam or ReRAM), phase change memory (PCM), 3D XPoint™ memory, NAND flash memory, NORflash memory, or other memory technologies known to persons skilled in the art, and/or a combination thereof.

In a memory device such as118, all of the stacked memory die may implement a first memory technology (e.g., DRAM); or alternatively one or more of the stacked memory die may include memory cells of a different storage technology different from the first memory technology. Alternatively, any of the above types of memory devices may be stacked in combination within memory device118.

Additionally, memory device118depicts a configuration in which the stacked memory die are stacked above an interface circuitry segment120A-120D of interposer106A. Interface circuitry segment120can be any of many different configurations, and when present, may implement logic functions relating to operation or management of the memory die of a memory device104A-104D stacked on an associated interface circuitry segment120A-102D. The interface circuitry segment120A-120D interfaces with other circuitry of interposer106A and interposer106B, and with processor102through BEOL structure B (FIG.1C). In some embodiments, the lowermost memory die108A will include contacts126which may, for example, comprise conductive pillars or micro-bumps, for interfacing with an associated interface circuitry segment120A-120D. In many examples, the contacts126will be arranged in one or more arrays configured to engage a respective device mounting site comprising contacts128of an interface circuitry segment120A-120D of interposer106A.

In some examples, the vertically interconnected memory die108A-108H may be interconnected through an array of TSVs extending essentially linearly and vertically through the stacked memory die108-108H (though not necessarily through the uppermost stacked memory die108H), as depicted at122A,122B,122C,122D,122E. In one of many alternate configurations some TSVs through individual die may be cross-connected to interleave vertical connections through the stacked memory die. For example, in one such embodiment, as depicted, the conductive paths may alternate between TSV paths in alternate die within the stack, as schematically depicted at124, in conductive paths122F-122G. Other, more complex, interleaved conductive paths may also be implemented. In some examples, one or more of the conductive paths will connect to each of the stacked memory die; while in other examples, a vertical conductive path may only electrically connect to communicate with other circuitry in a subset of the stacked memory die. For example, in the context of memory device118some TSVs might extend directly through the lowermost memory die108A-108D without connecting with other circuitry; and form electrical interconnections with circuitry only in the upper half of the stacked memory die108E-108H. In other examples, TSVs might form electrical connections only with alternating die within a stack of memory die.

Additionally, individual memory die108A-108H, or some portion thereof, may each contain multiple partitions (as indicated at130A-130H on memory die108H). Some or all of memory die108A-108H may be partitioned similarly. These partitions (or some subset thereof), may be vertically interconnected with corresponding partitions of other memory devices in the stack through the above discussed vertical connections, forming an independently operable memory unit. In some examples, the memory unit can include two or more vertically aligned partitions; and, in some examples, may include vertically aligned partitions from all memory die in the stack. As indicated in partition130A, each partition may be further subdivided into multiple banks or other subdivisions, such as individual memory channels. As one example, four banks (as indicated at132A-132D, defining four banks) are formed within partition130A, with each bank including further subdivided units, for example, representing individual memory channels (indicated typically at134). In some examples, these further subdivisions will be vertically interconnected in the same manner as described for the partitions to include portions of memory in multiple, or all, memory die in the stack, which may then be operated as a group.

Referring now toFIG.2, the figure depicts a simplified cross-sectional representation of an embodiment of interposer200suitable for use in implementation of embodiments of the disclosure comprising assemblies of memory and a host device, for example, a processor. Interposer200includes a semiconductor core, which, for purposes of the present example, will be described as a silicon core202having multiple TSVs204extending through silicon core202. As is known to persons skilled in the art, TSVs204each include a conductive structure, commonly a metal, extending within an insulator isolating the conductive structure from the surrounding silicon. By utilizing a silicon core202, TSVs can be arranged in a more compact spacing than would be feasible with current organic interposer technology. In some examples, for example, TSVs may be arranged at a pitch of 40 μm or less, for example, a pitch of approximately 20 μm. In many examples, the pitch of at least some portion of the TSVs will be sized to match a contact pitch of the semiconductor die or other devices coupled to interposer200. In such examples, the contact pitch of TSVs can correspond to the contact pitch(s) of the die or other device coupled to interposer200. In the depicted example, a conductive level (designated M1) extends “over” a side of core202, conductive level M1electrically insulated from the core202by a respective dielectric level208A (which may include one or more dielectric materials). The term “over” is used in the present description for clarity, and refers to the material or level being relatively outward from the core202. As will be recognized by persons of skill in the art, the materials and structures to one side of the core will typically be formed at different times, during which the respective side of the core over which a material is being formed will face directionally upward. Similarly, the term “under” is used herein to denote a structure closer to the core.

Conductive level M1will, in many examples, be patterned to define conductive traces210, at least some of which will interconnect with respective TSVs204, as depicted. Some conductive traces210may not connect with respective TSVs, and may just provide interconnection for conductive traces formed above conductive level M1. The term “redistribution layer” or “RDL” is used in the industry in multiple contexts sometimes to refer to a single level of a multi-level structure, and sometimes to refer to the multi-level structure itself. Herein, for clarity, the term “redistribution layer” or “RDL” is used to refer to a respective dielectric level supporting a respective metal level (as discussed below); and the term “redistribution structure” will be used to refer to multiple overlying individual RDLs as a group. Redistribution structures as described herein may be fabricated using BEOL techniques known to those of ordinary skill in the art and may correspond in structure and function to BEOL structures B as previously described herein with respect toFIGS.1B through1D.

A first redistribution structure214may be formed over a first side of core202. Redistribution structure214includes multiple respective redistribution layers (RDLs). Each of the multiple RDLs, in the example, redistribution structure214includes four RDLs, although the number of RDLs is not so limited, and it is contemplated that a greater number of RDLs, for example, six RDLS, may be employed in a redistribution structure to accommodate power and bias (e.g., ground) as well as signal transmission. In redistribution structure214, RDLs218,220,222,224, extend over a first side of core202and metal level M1formed thereon. Each RDL includes a respective dielectric level226,228,232, each dielectric level226,228,232supporting a respective metal (or other conductive material) level M2, M3, M4, M5. Each metal level M1-M5will preferably be patterned to collectively form conductive traces to redistribute contacts of a semiconductor die or other microelectronic device or structure mounted to interposer200to desired locations within interposer200. Of course, as noted above, a redistribution structure in the form of four RDLs is by way of example only, and a different number of RDLs may be employed.

In some examples, all metal levels M1-M5may be formed of the same metal. In other examples, however, outermost metal level M5will typically form surfaces for connecting (directly or through an interconnection structure) with complementary contact structures of another device. In the case of outermost metal level M5, the level will form surfaces suitable connecting with contacts of a semiconductor die, or other microelectronic device. As a result of the different functions of these metal levels, and the likely exposure of the metal to potentially oxidizing environments after formation, in some examples, one or both of the outermost metal levels may be formed of another conductive material that oxidizes more slowly than the metal used for used for other levels. For example, for examples in which metal levels M1-M4are formed of copper, outermost metal level M5may be formed of aluminum. As will be apparent to persons skilled in the art having the benefit of this disclosure, other conductive materials and/or other metals may be used for any one or more of conductive levels corresponding to metal levels M1-M5.

In many examples, the dielectric levels of the RDLs will comprise primarily, or in significant part, a polyimide compound. In general, a polyimide compound will be more elastic, and less prone to cracking, than other dielectric materials used in other locations in semiconductor manufacturing (such as silicon oxide (in various forms), silicon nitride, etc.). Additionally, the polyimide material may be formed at lower temperatures than other materials used in build-up applications, thereby minimizing stress on core202during manufacture of interposer200.

Interposer200may further include circuitry280formed within the dimensions of core202. In some embodiments, circuitry280may include passive components (such as resistors, inductors, capacitors) that may be formed, at least in part, in the bulk semiconductor (silicon) of core202. In other examples, the components may be formed, at least in part, of materials deposited in recesses formed in core202. In some examples, the passive components may be formed entirely within the dimensions of the core. In such examples, individual circuit elements may connect outside of the core through interconnection to one or more TSVs204extending through core202, or through one or more micro-vias282formed as a portion of M1formed over the upper surface of core202, and extending through dielectric level208A over the first surface of core202. In some cases, multiple passive components may be connected to one another. For example, resistors and capacitors may be coupled together to form a resistor/capacitor circuit. As one example, such a resistor/capacitor circuit, or an inductor, may be coupled and adapted to condition signals on conductive traces extending through one or more of the RDL layers of redistribution structure214.

In embodiments of the disclosure, active circuit components may be located within the dimensions of core202. Many forms of circuitry including active components will beneficially be formed with one or more bodies within the bulk silicon of core202, with one or more additional bodies formed in materials extending over core202. In many forms of such devices, regions of silicon core202may be isolated from one another by shallow trench isolation in silicon core202; and isolated regions of silicon core202may be doped relative to the remaining silicon of silicon core202. Specifically, and as noted above, interface circuitry segments120A-120D may be formed within or over core202. In addition, as described with respect toFIGS.1A-1D, cache memory in the form of SRAM may be formed within and over core202at least partially under the footprint of processor102.

With continued reference toFIG.2, TSVs204extend from metal level M1through core202of interposer200, for connecting individual circuit elements outside of core202, but also for connecting metal levels M2-M5and, therefore, data, power and bias (e.g., ground) signals to and from microelectronic devices, such as memory and processor, mounted to interposer200and connected by contacts126(FIG.1E) to metal level M5. TSVs204extend through core202from metal level M1and through dielectric level208B to another metal level M6opposite M1, metal level M6comprising conductive pads216.

By way of example only, the semiconductor material core202of interposer200may be of a thickness of about 50 μm or less, for example, about 30 μm. TSVs204may be of a diameter of about 5 μm. Fabrication of active and passive circuitry280may be effected by techniques known to those of ordinary skill in the art of semiconductor device fabrication, for example, memory device fabrication. Redistribution structure214, comprising multiple RDLs218,220,222and22may be fabricated by BEOL techniques known to those of ordinary skill in the art of semiconductor device fabrication. Similarly, TSVs204may be initially fabricated in the form of blind holes, for example, of about 65 μm depth in semiconductor core of a greater thickness, for example, a partially thinned wafer of about 100 μm thickness, the blind ends revealed by thinning of the core, and back side pads (i.e., conductive pads216) formed on the revealed ends by blanket conductive material deposition and patterning, all as known to those of ordinary skill in the art of semiconductor device fabrication. Such dimensions and processing techniques are equally applicable to all of the interpose embodiments of the present disclosure.

Notably, another interposer200may be fabricated for stacking with and connection to the interposer200described above for connection to that interposer200in a same or in an “inverted” orientations with different patterns of metal levels M1-M5and conductive pads216for stacking with the other interposer200to provide a redistribution structure comprising eight (8) metal levels, as well as additional passive and active circuitry as described above, which passive and active circuitry may be the same as, or different from, the circuitry employed in the first interposer, the stacked interposers200being connected through conductive elements extending between conductive pads216. If a second interposer200is fabricated for connection to a first interposer200in a similar orientation (i.e., redistribution structures facing in the same direction), conductive pads216of the second interposer200may be employed for connection of the assembly to higher-level packaging, such as a motherboard. When an interposer is configured for use in an inverted orientation, unlike an interposer200configured for direct connection of microelectronic devices, the metal level M5of the redistribution structure of the inverted interposer may be configured with conductive pads for connection to higher-level packaging, for example, a motherboard, while metal level M6is employed for connections to the first interposer200. In either implementation, the patterns of TSVs through the cores202of respective first and second interposers200may also be the same or different if, for example, conductive pads216may be employed with circuit traces to reroute signals between a first interposer and a second interposer having mutually offset TSVs.

By way of further elaboration, and with reference toFIGS.3A-3C, a first embodiment of stacked interposers200with redistribution structures214facing in the same direction, and a microelectronic device assembly300incorporating same, will be described. Elements previously described withFIG.2are identified with the same or similar reference numerals for convenience.

Referring toFIG.3A, a first interposer200D1of a first redistribution structure configuration comprising four RDLs218,220,222,224and, optionally, a first passive and active circuitry configuration, is depicted above a second interposer200D2with a second redistribution structure comprising four RDLs218,220,222,224and, optionally, second passive and active circuitry configuration. In both interposers as illustrated, first metal level M1(seeFIG.2) has been omitted for clarity. Upper interposer200D1comprises a semiconductor (e.g., silicon) core202, over which a redistribution structure214comprising four RDLs218,220,222,224has been fabricated. Circuitry280, comprising passive circuitry, active circuitry, or both may, optionally, be located within core202under redistribution structure214. TSVs204extend from redistribution structure214through core202and through dielectric level208B to conductive pads216.

Still referring toFIG.3A, lower interposer200D1comprises a semiconductor (e.g., silicon) core202, over which a redistribution structure214comprising four RDLs218,220,222,224has been fabricated on an upper side thereof, the redistribution structures214of both upper interposer200D1and lower interposer200D2are facing in the same direction. The conductive paths of RDLs218,220,222,224of redistribution structure214of lower interposer200D2are different from that of redistribution structure214of upper interposer200D1, and cooperatively configured for signal and, optionally, power and ground transmission. Circuitry280, comprising passive circuitry, active circuitry, or both may, optionally be located within core202under redistribution structure214. TSVs204extend from redistribution structure214through core202and through dielectric level208B to conductive pads216.

Referring toFIG.3B, interposer200D1is stacked over interposer200D2, and physically and electrically connected thereto by conductive elements230bonded to conductive pads216of interposer200D1and conductive pads of metal level M5of interposer200D2to form stacked interposer structure200S. Conductive elements230may, for example, comprise solder-capped copper pillars bonded to conductive pads in a reflow process, copper pillars bonded to copper pads in a diffusion bonding process, solder balls reflowed, gold stud bumps, oxide bonding (also termed oxide bonding, involving Cu—Cu diffusion bonds), and covalent bonding of oxide passivation materials in the bond line, or other suitable direct chip attach technique. It is contemplated that conductive elements230may be employed with a non-conductive film (NCF)240interposed between interposer200D1and interposer200D2or, alternatively, a wafer level underfill (WLUF).

FIG.3Cdepicts a microelectronic device assembly300of stacked and interconnected interposers200D1and200D2comprising stacked interposer structure200S and having mounted thereto microelectronic devices and configured for connection to higher level packaging. Microelectronic devices include, by way of example only, a memory stack302of high bandwidth-configured DRAM die mounted on and operably coupled to interposer200D1of microelectronic device assembly300. As noted previously, any suitable number of DRAM die may be incorporated in memory stack302, for example, four, eight, twelve, sixteen, thirty-two or sixty-four DRAM die. As depicted inFIGS.1A-1D, more than one stack of memory die, and of more than one type, may be mounted to microelectronic device assembly300. A processor304may also be mounted on and connected to interposer200D1of microelectronic device assembly300. Processor304may comprise, for example, a graphics processing unit (GPU), a central processing until (CPU), a controller, or a system on a Chip (SoC). Memory stack302and processor304may each be physically and electrically connected to conductive pads250of metal level M5of interposer200D1by, for example, solder-capped copper pillars, diffusion-bonded conductive pillars, solder bumps, micro bumps, or any other suitable conductive elements306. Conductive elements260in the form of, for example, solder balls residing on conductive pads216of interposer200D2may be employed for connection of microelectronic device assembly300to higher-level packaging. Prior to application or formation of conductive elements260, microelectronic device assembly300may be encapsulated with a dielectric molding compound, as known to those of ordinary skill in the art.

By way of further elaboration, and with reference toFIGS.3D-3F, a second embodiment of stacked interposers200with redistribution structures facing in opposing directions, and a microelectronic device assembly incorporating same, will be described. Elements previously described withFIG.2are identified with the same or similar reference numerals for convenience.

Referring toFIG.3D, a first interposer200D1′ of a first redistribution structure configuration comprising four RDLs218,220,222,224and, optionally, a first passive and active circuitry configuration, is depicted above a second interposer200D2′ with a second redistribution structure comprising four RDLs218,220,222,224and, optionally, second passive and active circuitry configuration. Upper interposer200D1′ comprises a semiconductor (e.g., silicon) core202, over which a redistribution structure214comprising four RDLs218,220,222,224has been fabricated. Circuitry280, comprising passive circuitry, active circuitry, or both may, optionally be located within core202under redistribution structure214. TSVs204extend from redistribution structure214through core202and through dielectric level208B to conductive pads216.

Still referring toFIG.3D, lower interposer200D2′ comprises a semiconductor (e.g., silicon) core202, over which a redistribution structure214comprising four RDLs218,220,222,224has been fabricated on a lower side thereof, so that redistribution structures214of interposer200D1′ and200D2′ are facing in opposing directions. The conductive paths of RDLs218,220,222,224of redistribution structure214of lower interposer200D2′ are different from that of redistribution structure214of upper interposer200D1, and cooperatively configured for signal and, optionally, power and ground transmission. Circuitry280, comprising passive circuitry, active circuitry, or both may, optionally be located within core202over redistribution structure214. TSVs204extend from redistribution structure214through core202and through dielectric level208B to conductive pads216.

Referring toFIG.3E, interposer200D1′ is stacked over interposer200D2′, and physically and electrically connected thereto by conductive elements230bonded to conductive pads216of interposer200D1′ and conductive pads216of interposer200D2′ to form stacked interposer structure200S′. Conductive elements230may, for example, comprise solder-capped copper pillars bonded to conductive pads in a reflow process, copper pillars bonded to copper pads in a diffusion bonding process, reflowed solder balls, gold stud bumps, hybrid bonding (also termed oxide bonding, involving Cu—Cu diffusion bonds and covalent bonding of oxide passivation materials in the bond line), or other suitable direct chip attach technique. It is contemplated that conductive elements230may be employed with a non-conductive film (NCF)240interposed between interposer200D1′ and interposer200D2′ or, alternatively, a wafer level underfill (WLUF). Notably, the conductive paths in redistribution structures214of interposers200D1′ and200D2′ (and thus of stacked interposer structure200S′) may be different from those in redistribution structures214of interposers200D1and200D2(and thus of stacked interposer structure200S), as will one or more of the number, spacing and pattern of TSVs204interconnecting the stacked interposers200. Similarly, the type, number and locations of passive and active circuitry may differ between stacked interposer structures200S and200S′.

FIG.3Fdepicts a microelectronic device assembly300′ of stacked and interconnected interposers200D1′ and200D2′ having mounted thereto microelectronic devices and configured for connection to higher level packaging. Microelectronic devices include, by way of example only, a memory stack302of high bandwidth-configured. DRAM die mounted on and operably coupled to interposer200D1′ of assembly300′. As noted previously, any suitable number of DRAM die may be incorporated in memory stack302, for example, four, eight, twelve, sixteen, thirty-two or sixty-four DRAM die. As depicted inFIGS.1A-1D, more than one stack of memory die, and of more than one type, may be mounted to microelectronic device assembly300. A processor304may also be mounted on and connected to interposer200D1′ of microelectronic device assembly300. Processor304may comprise, for example, a graphics processing unit (GPU), a central processing until (CPU), a controller, or a system on a Chip (SoC). Memory stack302and processor304may each be physically and electrically connected to conductive pads250of metal level M5of interposer200D1′ by, for example, solder-capped copper pillars, diffusion-bonded conductive pillars, solder bumps, or any other suitable conductive elements306. Conductive elements260in the form of, for example, solder balls residing on conductive pads270of metal level M5of interposer200D2′ may be employed for connection of microelectronic device assembly300′ to higher-level packaging. Prior to application or formation of conductive elements260, microelectronic device assembly300′ may be encapsulated with a dielectric molding compound, as known to those of ordinary skill in the art.

In embodiments depicted and described with respect to each ofFIGS.3A-3CandFIGS.3D-3F, respectively, the circuitry, including traces, vias, active circuitry (if present) and passive circuitry (if present) in each cooperative combination of two stacked interposers comprising stacked interposer structures200S and200S′ is designed to function as a single interposer, for example, a single interposer having a core with redistribution structures on opposing sides thereof and operably coupled by conductive vias extending through the core and between the redistribution structures. However, embodiments of the stacked interposer designs of the present disclosure are far easier and less costly to fabricate, employing techniques already in use to fabricate active and passive circuitry in and on a semiconductor wafer and redistribution structures in the form of multiple RDLs on the wafer active surface. In addition, utilization of embodiments of the present disclosure may enhance throughput while increasing yield. For some examples, it will be desirable to form stacked interposers200with the same number of multiple RDLs in redistribution structures214. As discussed later herein, in some examples, the symmetrical structure may also be beneficial to conveying signals in multiple conductive channels (e.g., in some examples, with a first conductive channel implemented at least in part through metal levels M2-M5in first redistribution structure214, and a second conductive channel implemented at least in part through metal levels M2-M5of second redistribution structure214). Also, there may be an unequal number of RDLs on each interposer200, and individual RDLs may have vertical dimensions different than other RDLs. Further, it is contemplated that more than two interposers200may be stacked in various cooperative configurations and orientations in instances where height limitations of an assembly incorporating stacked interposers are not an issue. In addition, it is contemplated that RDLs of respective interposers may be engineered to minimize warpage of the interposers, and that the embodiment ofFIGS.3A-3Cmay enable mirroring of any warpage (i.e., warping in the same direction) of the stacked interposers to minimize stress within the interposer cores.

Referring now toFIG.4, the figure depicts a block diagram representation of an example configuration for a stacked interposer structure400, including example optional circuit componentry may be formed in accordance with the description herein. Stacked interposer structure400is analogous to interposers106A and106B ofFIG.1A, in that the upper surface of the upper interposer of the stack defines metallization configured to form processor interfaces402A,402B,402C,402D for four memory devices, as part of a processor interface operably coupled to SRAM410located under the footprint of processor404and additionally configured for external communication to other devices. Each processor interface402A,402B,402C,402D may communicate data, command, and control signals between the memory devices and the processor through cache memory in the form of SRAM410to and through a respective communication channel406A,406B,406C,406D extending to four memory interfaces408A,408B,408C,408D corresponding to interface circuitry segments120A,120B,120C,120D as described with respect toFIGS.1A-1E. The particular configuration of metallization for each processor interface402A,402B,402C,402D, and also the contact array of each memory interface408A,408B,408C,408D can be adapted to a desired configuration, such as may be dictated by a standardized interface.

The ability to configure an interposer to include active and/or passive circuit components facilitates the forming of logic structures such as interface circuitry segments120A-120D and/or additional structures, for example, cache memory in the form of SRAM410, within the interposer to simplify incorporating such circuit components into the microelectronic device assembly to be formed with interposers of the stacked interposer structure400. In addition to cache memory, such as SRAM410, another form of memory412may be formed within or over core202, such as, by way of example only, any of DRAM, ferroelectric random-access memory (FeRAM), phase change memory (PCM), 3D XPoint™ memory, NAND flash memory, NOR flash memory, resistive random-access memory (ReRAM or RRAM), or other memory types known to persons skilled in the art, and/or a combination thereof.

Additionally, logic structures in addition to those of interface circuitry segments120A-120D may be formed in interposers of the stacked interposer structure400. Such logic structures may be in the form of Field-Programmable Gate Arrays (FPGAs)414, or other types of logic416. Additionally, configuration circuitry, as may be used to tune or trim circuits or to enable or disable circuit components, such as fuses or anti-fuses, can be formed in interposers of stacked interposer structure400. And, as discussed previously passive circuit components420, such as, for example, components to condition signals traversing interposers of stacked interposer structure400may also be formed.

For clarity of the block diagram representation, the different circuit components are depicted surrounding, but offset from, processor404. However, the ability to incorporate such circuit components into interposers of stacked interposer structure400facilitates placing the circuit components in a desired location within stacked interposer structure400, such as placement of cache memory in the form of410under the footprint of processor404and interface circuitry segments120A-120D, as better illustrated inFIGS.1B,1C and1D. Any of the above memory, logic, or configuration circuitry may communicate through connected TSVs to the opposite side of an upper interpose of stacked interposer structure400and, as applicable to a lower interposer thereof.

Accordingly, stacked interposer structure400depicts, in schematic form, the various features that may be incorporated into a combination of stacked interposers, for example, stacked interposers200D1and D2and stacked interposers200D1′ and200D2′, respectively. In each instance, the various circuit components shown on a single level inFIG.4may be distributed among the two cooperative redistribution structures214of each two-interposer stacked interposer structure200S,200S′, and active and passive circuitry may be fabricated on one or both cores202of stacked interposer structure200S,200S′, to operate in combination with the circuitry of the redistribution structures214and with TSVs204extending through the respective cores202.

The incorporation of logic gates and memory into the structure of described interposers was previously identified. As was described, for many such structures, particularly those including active components, forming one or more bodies of the components in the silicon of the interposer core may be desirable, with one or more bodies of the components formed in materials formed over the core. An example manner of a structure incorporating such active components and related structures into the interposer core will be discussed in reference toFIG.5.

FIG.5depicts a portion of an example interposer500including circuit elements, including logic gates as previously discussed in reference to interposer200ofFIG.2.FIG.5depicts a logic structure502formed above silicon core522. The levels of a redistribution structure comprising metal levels M2-M5of RDL layers532,534,536and538have been enlarged for clarity, as has logic structure502and components thereof. In the depicted example, logic structure502includes coupled transistors504,506. Each transistor504,506includes source/drain regions508,510,512formed by doping selected regions of silicon core522. In some examples, in which such transistor gates are to be formed, it may be desirable to remove at least a portion of dielectric level520formed over silicon core522, in order to form another dielectric material, indicated at514, optimized to form a gate oxide for the transistors. In regions outside the logic gates, dielectric level520may remain intact. In some examples, it may be advantageous to isolate portions of silicon core522adjacent one or more circuit components, such as by forming shallow trench isolation, as indicated at516within silicon core522. Forming of transistors504,506can include forming one or more conductive gate materials524,526(such as, for example, doped polysilicon) over the gate oxide514; and isolating the sidewalls of the gates with spacers, as depicted. Also, as discussed previously, electrical connection between circuitry can be made with one or more conductive levels, such as one or more logic metal (LM) materials within the logic region. In order to provide a planar surface on which to form the previously-described RDLs, where, as in the example, the circuit components extend above the surface of silicon core522, an insulating material530, for example, such as TEOS, may be formed above the logic circuitry and planarized. On the opposing side of silicon core522, conductive pads542are connected to the above-described circuitry through TSVs540.

The microelectronic device assemblies300,300′ incorporating stacked interposer structures according to embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG.6is a block diagram of an illustrative electronic system600according to embodiments of disclosure. The electronic system600includes at least one electronic device fabricated in accordance with embodiments of the disclosure. The electronic device may comprise, for example, a memory device602comprising an embodiment of one or more of the microelectronic device assemblies300,300′ previously described herein, such as an HBM assembly comprising a stack of DRAM dice. The electronic system600may further include a host device in the form of a processor device604such as, for example, a GPU, a CPU, a controller, an FPGA or a SoC incorporated in the microelectronic device assembly300,300′. The electronic system600may further include one or more input devices606for inputting information into the electronic system600by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system600may further include one or more output devices608for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device606and the output device608may comprise a single touchscreen device that can be used both to input information to the electronic system600and to output visual information to a user. The input device606and the output device608may communicate electrically with one or both of the processor device604and the memory device602in microelectronic device assembly300,300′.

Electronic system600may be a computer, a server, a laptop computer, a notebook computer, a Wi-Fi or cellular-enabled tablet computer such as an iPad® or SURFACE® tablet, a mobile phone, a wearable electronic device, a personal electronic device, a digital camera, a portable media (e.g., music, video) player, a navigation device, or the like. Similarly, electronic system600may be a portion or subcomponent of such a device. In some examples, electronic system600is an aspect of a computer with high reliability, mission critical, or low latency constraints or parameters, such as a vehicle (e.g., an autonomous automobile, airplane, a spacecraft, or the like), Electronic system600may be or include logic for artificial intelligence (AI), augmented reality (AR), or virtual reality (VR) applications.

In embodiments, a stacked interposer structure comprises a first interposer comprising a first core comprising a semiconductor material a first redistribution structure comprising multiple redistribution layers (RDLs) over a side of the first core and a first set of through silicon vias (TSVs) extending from the first redistribution structure through the first core to an opposite side of the first core and a second interposer comprising a second core comprising a semiconductor material a second redistribution structure comprising multiple redistribution layers (RDLs) over a side of the second core a second set of through silicon vias (TSVs) extending from the second redistribution structure through the second core to an opposite side of the second core. The first and second redistribution structures are operably coupled through at least one of the first set of TSVs and the second set of TSVs.

In embodiments, a microelectronic device assembly comprises a stacked interposer structure comprising multiple interconnected interposers, each interposer having a semiconductor core and a redistribution structure on one side thereof, at least one host device and at least one memory device mounted on, and operably coupled to, a redistribution structure of one of the multiple interconnected interposers, and circuitry of the stacked interposer structure operably coupling the at least one host device and the at least one memory device and extending to a side of the stacked interposer structure opposite the at least one host device and the at least one memory device for connection to higher level packaging.

In embodiments, an interposer comprises a silicon core comprising at least one of active circuitry and passive circuitry over a single active surface of the silicon core, a redistribution structure comprising at least four redistribution layers (RDLs) located over the active circuitry and the passive circuitry, and through silicon vias (TSVs) operably coupled to at least the redistribution structure and extending through the silicon core to a side thereof opposite the redistributions structure.

In embodiments, a stacked interposer structure comprises two interposers, one stacked above another and each having a redistribution structure comprising multiple redistribution layers (RDLs), the redistribution structures operably coupled through TSVs extending through a semiconductor core of at least one of the two interposers, the redistribution structure of one of the two interposers configured for operably coupling to a host device and a memory device and the redistribution structure of each of the two interposers comprising different conductive paths configured as operably coupled, in combination, to cooperatively function as a single redistribution structure comprising the combined number of multiple redistribution layers of the two interposers.

In embodiments, an electronic system comprises an input device, an output device, the electronic system further comprising a processor device and at least one memory device operably coupled to a redistribution structure of an interposer comprising a semiconductor core, the redistribution structure of the interposer operably coupled to another redistribution structure of another interposer at least by through silicon vias (TSVs) extending from the redistribution structure of the interposer through the semiconductor core to a side thereof opposite the redistribution structure, the input device and the output device operably coupled to the processor through conductive paths of the another interposer.

In embodiments, a method comprises providing two interposers each having a redistribution structure comprising multiple redistribution layers (RDLs) over a semiconductor core, conductive paths of the multiple redistribution layers (RDLs) of the redistribution structures cooperatively configured to function as a single redistribution structure consisting of a total number of redistribution layers (RDLs) of the two interposers, and electrically connecting the conductive paths of the redistribution layers (RDLs) of the two interposers through TSVs extending through at least one of the semiconductor cores.

While certain illustrative embodiments have been described in connection with the figures, those of ordinary skill in the art will recognize and appreciate that embodiments encompassed by the disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of embodiments encompassed by the disclosure, such as those hereinafter claimed, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the disclosure.