Patent ID: 12224296

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter an image sensor and a method of fabricating the same according to an exemplary embodiment of the present inventive concept will be described more fully with reference to the accompanying drawings.

It will be understood that spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, in the example, terms “below” and “beneath” may encompass both an orientation of above, below and beneath. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

FIG.1illustrates a plan view showing an image sensor according to an exemplary embodiment of the present inventive concept.

Referring toFIG.1, an image sensor may include a pixel array region R1and a pad region R2.

The pixel array region R1may include a plurality of unit pixels P that are two-dimensionally arranged along a first direction D1and a second direction D2. Each of the unit pixels P may include a photoelectric conversion element and readout elements. Each unit pixel P of the pixel array region R1may output electrical signals converted from incident light.

The pixel array region R1may include a light-receiving region AR and a light-shielding region OB. From a plan view, the light-shielding region OB may at least partially surround the light-receiving region AR. For example, when viewed from a plan view, the light-shielding region OB may be disposed on all of the sides of the light-receiving region AR. The light-shielding region OB may include reference pixels on which no or little light is incident, and an amount of charges sensed in the unit pixels P of the light-receiving region AR may be compared with a reference amount of charges occurring at reference pixels, which may result in obtaining magnitudes of electrical signals sensed in the unit pixels P.

The pad region R2may include a plurality of conductive pads CP used for input and output of control signals and photoelectric conversion signals. For easy connection with external devices, when viewed in a plan view, the pad region R2may at least partially surround the pixel array region R1. The conductive pads CP may allow an external device to receive electrical signals generated from the unit pixels P.

The image sensor according to an exemplary embodiment of the present inventive concept may use an infrared ray to detect light reflected from an object and may output optical depth information of the object. As such, like operations of infrared cameras, the optical depth information obtained from the image sensor may be utilized to achieve a three-dimensional image. In addition, a three-dimensional color image may be accomplished by using an image sensor including infrared-light pixels and visible-light pixels.

FIGS.2A and2Billustrate plan views partially showing an image sensor according to an exemplary embodiment of the present inventive concept.FIGS.3A,3B, and3C illustrate cross-sectional views taken along lines A-A′, B-B′, and C-C′ ofFIG.2A, showing an image sensor according to an exemplary embodiment of the present inventive concept.FIG.3Dillustrates a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.2B.FIGS.4A to4Fillustrate enlarged views showing section P ofFIG.3A.

Referring toFIGS.2A and3A, an image sensor according to an exemplary embodiment of the present inventive concept may include a photoelectric conversion layer10, a readout circuit layer20, and an optical transmission layer30. When viewed in cross-section, the photoelectric conversion layer10may be disposed between the readout circuit layer20and the optical transmission layer30.

For example, a semiconductor substrate100may have a first surface (or, e.g., a front surface)100aand a second surface (or, e.g., a rear surface)100bthat are opposite to each other. For example, the semiconductor substrate100may be an epitaxial layer formed on a bulk silicon substrate that has the same first conductivity type (e.g., p-type) as that of the epitaxial layer, or a p-type epitaxial layer from which a bulk silicon substrate is removed in fabrication of the image sensor. In addition, the semiconductor substrate100may be a bulk semiconductor substrate that includes a well of the first conductivity type.

On each of pixel regions PR, a device isolation layer101may be disposed adjacent to the first surface100aof the semiconductor substrate100. The device isolation layer101may form an active section on the semiconductor substrate100.

The semiconductor substrate100may be provided therein with a first pixel separation structure PIS1adjacent to the first surface100aof the semiconductor substrate100. The first pixel separation structure PIS1may have a bottom surface between the first and second surfaces100aand100bof the semiconductor substrate100. The first pixel separation structure PISA may be spaced apart from the second surface100bof the semiconductor substrate100. The first pixel separation structure PIS1may have a first width at the first surface100aof the semiconductor substrate100and a second width at the bottom surface of the first pixel separation structure PIS1. For example, the second width may be closer to the second surface100bof the semiconductor substrate100than the first width. For example, the first width may be an upper width, and the second width may be a lower width. The second width may be substantially the same as or less than the first width. The first pixel separation structure PIS1may have a width that gradually decreases from the first surface100atoward the second surface100bof the semiconductor substrate100. For example, the first pixel separation structure PIS1may have a tapered shape.

The first pixel separation structure PIS1may have a first length L1in a direction perpendicular to a surface of the semiconductor substrate100. The first length L1of the first pixel separation structure PIS1may range from about 4 μm to about 8 μm.

The first pixel separation structure PIS1may provide the pixel regions PR. The first pixel separation structure PIS1may include first parts that are parallel to each other and extend along a first direction D1, second parts that are parallel to each other and run in a second direction D2across the first parts, and intersection parts where the first and second parts intersect each other.

When viewed in a plan view, the first pixel separation structure PIS1may surround each of the pixel regions PR. The first pixel separation structure PIS1may separate the pixel regions PR from each other in the first and second directions D1and D2, and this may also be applied to a second pixel separation structure PIS2which will be discussed below. For example, the pixel regions PR may be two-dimensionally arranged along the first and second directions D1and D2.

The first pixel separation structure PIS1may include a liner dielectric pattern103, a semiconductor pattern105, and a capping pattern107. The semiconductor pattern105may vertically penetrate a portion of the semiconductor substrate100, and the liner dielectric pattern103may be provided between the semiconductor pattern105and the semiconductor substrate100. The capping pattern107may be disposed on the semiconductor pattern105, and may be, for example, a top surface at a level substantially the same as that of a top surface of the device isolation layer101. The capping pattern107may have a bottom surface at a level the same as or lower than that of a bottom surface of the device isolation layer101. However, the present inventive concept is not limited thereto, and for example, the bottom surface of the capping pattern107may be higher than the bottom surface of the device isolation layer101. For example, the capping pattern107may have a round shape at the bottom surface thereof. The liner dielectric pattern103and the capping pattern107may include at least one of a silicon oxide layer, a silicon oxynitride layer, and/or a silicon nitride layer. The semiconductor pattern105may include an undoped polysilicon layer or an impurity-doped polysilicon layer. For example, the semiconductor pattern105may include an air gap or a void.

The semiconductor substrate100may be provided therein with a second pixel separation structure PIS2adjacent to the second surface100bof the semiconductor substrate100. The second pixel separation structure PIS2may have a bottom surface between the first and second surfaces100aand100bof the semiconductor substrate100. For example, the second pixel separation structure PIS2may be spaced apart from the first surface100aof the semiconductor substrate100. For example, the second pixel separation structure PIS2may be disposed on the first pixel separation structure PIS1. For example, the second pixel separation structure PIS2may be in contact with the first pixel separation structure PIS1.

The second pixel separation structure PIS2may have a third width at the second surface100bof the semiconductor substrate100and a fourth width at the bottom surface of the second pixel separation structure PIS2. For example, the third width may be an upper width, and the fourth width may be a lower width. The fourth width may be substantially the same as or less than the third width. The second pixel separation structure PIS2may have a width that gradually decreases from the second surface100btoward the first surface100aof the semiconductor substrate100.

The second pixel separation structure PIS2may have a planar structure substantially the same as that of the first pixel separation structure PIS1. When viewed from a plan view, the second pixel separation structure PIS2may overlap the first pixel separation structure PIS1. The second pixel separation structure PIS2may include first parts P1that are parallel to each other and extend along the first direction D1, second parts P2that extend along the second direction D2intersecting the first direction D1, and intersection parts P3connected to the first and second parts P1and P2. For example, the second pixel separation structure PIS2may have a vertical length that is substantially the same at the first, second, and intersection parts P1, P2, and P3. For example, the second pixel separation structure PIS2may have a height that is substantially consistent for the first, second, and intersection parts P1, P2, and P3.

The second pixel separation structure PIS2may have a second length L2in a vertical direction, and the second length L2may be different from the first length L1of the first pixel separation structure PIS1. However, the present inventive concept is not limited thereto. For example, the second length. L2of the second pixel separation structure PIS2may be substantially the same as the first length L1of the first pixel separation structure PIS1. For example, the second length L2of the second pixel separation structure PIS2may range from about 2 μm to about 5 μm.

In an exemplary embodiment of the present inventive concept, a value of about 8 μm to about 13 μm may be given as a vertical thickness of the semiconductor substrate100, or a sum of the first and second lengths L1and L2of the first and second pixel separation structures PIS1and PIS2.

The second pixel separation structure PIS2may be formed of at least one high-k dielectric layer whose dielectric constant is greater than that of a silicon oxide layer. For example, the second pixel separation structure PIS2may include a surface dielectric layer121and a gap-fill dielectric layer123.

In an exemplary embodiment of the present inventive concept, the semiconductor substrate100may have a first trench overlapping the first pixel separation structure PIS1and disposed on the second surface100b, and may also have a second trench that overlaps a photoelectric conversion region110. The surface dielectric layer121may conformally cover inner walls of the first and second trenches and the second surface100bof the semiconductor substrate100. The gap-fill dielectric layer123may fill the first and second trenches in which the surface dielectric layer121is formed, and may have a top surface that is substantially flat. The surface and gap-fill dielectric layers121and123may include one of metal oxide and metal fluoride each of which includes at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and/or lanthanoid (Ln). For example, the surface dielectric layer121may include an aluminum oxide layer, and the gap-fill dielectric layer123may include a hafnium oxide layer.

In an exemplary embodiment of the present inventive concept, the gap-fill dielectric layer123of the second pixel separation structure PIS2may have a width less than that of the first pixel separation structure PIS1.

Referring toFIG.4A, the surface dielectric layer121of the second pixel separation structure PIS2may be in contact with the liner dielectric pattern103of the first pixel separation structure PIS1.

Referring toFIG.4B, the surface dielectric layer121of the second pixel separation structure PIS2may be in contact with the semiconductor pattern105of the first pixel separation structure PIS1. In an exemplary embodiment of the present inventive concept, the gap-fill dielectric layer123of the second pixel separation structure PIS2may be in contact with the semiconductor pattern105of the first pixel separation structure PIS1.

Referring toFIG.4C, the second pixel separation structure PIS2may be disposed to deviate from the first pixel separation structure PIS1. In this case, the second pixel separation structure PIS2may be in partial contact with a sidewall of the first pixel separation structure PIS1. For example, the second pixel separation structure PIS2may, be misaligned with the first pixel separation structure PIS1.

Referring toFIG.4D, the second pixel separation structure PIS2may be vertically spaced apart from the first pixel separation structure PIS1, while overlapping the first pixel separation structure PIS1. For example, a portion of the semiconductor substrate100may be present between the first pixel separation structure PIS1and the second pixel separation structure PIS2.

Referring toFIG.4E, the first pixel separation structure PIS1may have a flat bottom surface. For example, the liner dielectric pattern103of the first pixel separation structure PIS1may include a flat bottom part and sidewall parts that vertically extend from the bottom part. The second pixel separation structure PIS2may be in contact with the flat bottom surface of the first pixel separation structure PIS1.

Referring toFIG.4F, the second pixel separation structure PIS2may partially penetrate the first pixel separation structure PIS1. The second pixel separation structure PIS2may include a first portion (e.g., an upper portion) that penetrates the semiconductor substrate100and a second portion (e.g., a lower portion) that penetrates the first pixel separation structure PIS1. For example, the lower portion may have a width less than that of the upper portion.

Referring back toFIGS.2A and3A, a plurality of photoelectric conversion regions110may be provided in the semiconductor substrate100of their corresponding pixel regions PR. The photoelectric conversion regions110may generate photo-charges in proportion to a magnitude of incident light. The photoelectric conversion regions110may be formed in the semiconductor substrate100by implanting the semiconductor substrate100with impurities having a second conductivity type opposite to that of the semiconductor substrate100. A photodiode may be formed at a junction between the semiconductor substrate100having the first conductivity type and the photoelectric conversion region110having the second conductivity type.

According to an exemplary embodiment of the present inventive concept, the photoelectric conversion regions110may each have a difference in impurity concentration between a location thereof adjacent to the first surface100aand a location thereof adjacent to the second surface100b, and thus a potential gradient may be provided between the first and second surfaces100aand100bof the semiconductor substrate100. For example, each of the photoelectric conversion regions110may include a plurality of vertically stacked impurity regions.

According to an exemplary embodiment of the present inventive concept, on each of the pixel regions PR, scattering patterns SP may be provided on the second surface100bof the semiconductor substrate100. The scattering patterns SP may be disposed in a plurality of second trenches formed on the second surface100bof the semiconductor substrate100. The scattering patterns SP may have substantially uniform widths and may be spaced apart from each other at a regular interval. However, the present inventive concept is not limited thereto. For example, the scattering patterns SP may not be spaced apart from each other at a regular interval.

The scattering patterns SP may have their top surfaces at a level substantially the same as that of a top surface of the second pixel separation structure PIS2. For example, the top surfaces of the scattering patterns SP may be substantially coplanar with the top surface of the second separation structure PIS2.

The scattering patterns SP may be formed of the same material as that of the second pixel separation structure PIS2, and may have the same stacking structure as that of the second pixel separation structure PIS2. For example, the scattering patterns SP may be formed of a high-k dielectric layer whose dielectric constant is greater than that of a silicon oxide layer. The scattering patterns SP may include a surface dielectric layer121and a gap-fill dielectric layer123.

Portions of the surface and gap-fill dielectric layers121and123, included in the second pixel separation structure PIS2and the scattering patterns SP, may be disposed on the second surface100bof the semiconductor substrate100. For example, the surface dielectric layer121may directly contact the semiconductor substrate100, and the gap-fill dielectric layer123may have a flat top surface.

As shown inFIG.2A, the scattering patterns SP may be shaped like circles, tetragons, or polygons, from a plan view. The scattering patterns SP may be spaced apart from each other in the first and second directions D1and D2. For example, the scattering patterns SP may be arranged in a matrix shape, a checkerboard shape, or any other suitable shape.

The scattering patterns SP may each have a third length L3in a vertical direction, and the third length L3of the scattering patterns SP may be different from the second length L2of the second pixel separation structure PIS2. For example, as illustrated inFIG.3A, the third length L3of the scattering patterns SP may be less than the second length L2of the second pixel separation structure PIS2. As another example, referring toFIG.3B, the third length L3of the scattering patterns SP may be substantially the same as the second length L2of the second pixel separation structure PIS2. In another example, referring toFIG.3C, the third length L3of the scattering patterns SP may be greater than the second length L2of the second pixel separation structure PIS2. In another example, referring toFIG.3D, the scattering patterns SP may have varying lengths, and each of the lengths may be less than the second length L2.

The scattering patterns SP may scatter incident light having a relatively long wavelength and may allow the incident light to have an increased optical path. Therefore, the photoelectric conversion regions110may have an increase in optical absorption efficiency of incident light.

The readout circuit layer20may be disposed on the first surface100aof the semiconductor substrate100. The readout circuit layer20may include readout circuits connected to the photoelectric conversion layer10. The readout circuit layer20may signally process an electrical signal converted in the photoelectric conversion layer10.

For example, the readout circuits may include MOS transistors (e.g., a reset transistor, a source follower transistor, and a selection transistor). On the pixel regions PR, transfer gate electrodes TG may be disposed on the first surface100aof the semiconductor substrate100. When viewed from a plan view, the transfer gate electrode TG may be positioned in each pixel region PR. For example, the transfer gate electrode TF may be positioned on a central portion of each pixel region PR. A portion of the transfer gate electrode TG may be disposed in the semiconductor substrate100, and a gate dielectric layer may be interposed between the transfer gate electrode TG and the semiconductor substrate100. A floating diffusion region FD may be provided in the semiconductor substrate100on one side of the transfer gate electrode1G. The floating diffusion region FD may be formed by implanting the semiconductor substrate100with impurities whose conductivity type is opposite to that of semiconductor substrate100. For example, the floating diffusion region FD may be an n-type impurity region.

Interlayer dielectric layers210may be stacked on the first surface100aof the semiconductor substrate100, and may cover the transfer gate electrode TG and the MOS transistors included in the readout circuits. The interlayer dielectric layers210may include, for example, one or more of silicon oxide, silicon nitride, and/or silicon oxynitride.

The interlayer dielectric layers210may have therein wiring structures221and222connected to the readout circuits. The wiring structures221and222may include metal lines222and contact plugs221that connect the metal lines222to each other.

The optical transmission layer30may be disposed on the second surface100bof the semiconductor substrate100. The optical transmission layer30may include a planarized dielectric layer310, a grid structure320, a protection layer330, a microlens array340, and a passivation layer350.

For example, the planarized dielectric layer310may be disposed on the gap-fill dielectric layer123of the scattering patterns SP and the second pixel separation structure PIS2. The planarized dielectric layer310may include a first planarized layer311, a second planarized layer313, and a third planarized layer315that are sequentially stacked on the gap-fill dielectric layer123. The first, second, and third planarized layers311,313, and315may be formed of a transparent dielectric material. The first, second, and third planarized layers311,313, and315may have refractive indices that are different from each other. The first, second, and third planarized layers311,313, and315may be combined to have a predetermined thickness and to have a relatively high refractive index. For example, the second planarized layer313may be thicker than the first planarized layer311and/or the third planarized layer315.

The first and the third planarized layers311and315may have the same refractive index as each other, and the second planarized layer313may have a different refractive index from that of the first and third planarized layers311and315. For example, the first and third planarized layers311and315may include metal oxide, and the second planarized layer313may include silicon oxide.

The grid structure320may be disposed on the planarized dielectric layer310. Similar to that of the first and second pixel separation structures PIS1and PIS2, the grid structure320may have a grid shape when viewed from a plan view. When viewed from a plan view, the grid structure320may overlap the first and second pixel separation structures PIS1and PIS2. For example, the grid structure320may include first parts that extend in the first direction D1, and may also include second parts that extend in the second direction D2while running across the first parts. The grid structure320may have a width substantially the same as or less than minimum widths of the first and second pixel separation structures PIS1and PIS2.

The grid structure320may include one or more of a light-shielding pattern and a low-refractive pattern. The light-shielding pattern may include a metallic material, such as titanium, tantalum, or tungsten. The low-refractive pattern may be formed of a material whose refractive index is less than that of the light-shielding pattern. The low-refractive pattern may be formed of an organic material and may have a refractive index of about 1.1 to about 1.3. For example, the grid structure320may be a polymer layer including silica nano-particles.

The planarized dielectric layer310may be provided on second surface100bof the semiconductor substrate with the protection layer330having a substantially uniform thickness that covers a surface of the grid structure320. The protection layer330may be a single layer or multiple layers including one or more of, for example, aluminum oxide and silicon carbon oxide.

The microlens array340may be disposed on the protection layer330. The microlens array340may include a planarized part that fills a space provided by the grid structure320, and may also include microlenses that are provided on the planarized part and correspond to the pixel regions PR.

The passivation layer350may conformally cover a top surface of the microlens array340. The passivation layer350may be formed of, for example, inorganic oxide.

The following will discuss an image sensor according to an exemplary embodiment of the present inventive concept, and explanations of the same features as those of the image sensor discussed above may be omitted for brevity of description.

Referring toFIGS.2A and3B, as discussed above, the first pixel separation structure PIS1may overlap the second pixel separation structure PIS2. Each of the first and second pixel separation structures PIS1and PIS2may include first parts P1that extend in the first direction D1, second parts P2that extend in the second direction D2intersecting the first direction D1, and interconnection parts P3connected to the first and second parts P1and P2.

The first pixel separation structure PIS1may have a first length L1ain a vertical direction at the first and second parts P1and P2, and may also have at the intersection parts P3a second length L1b, in the vertical direction, greater than the first length L1a. In an exemplary embodiment of the present inventive concept, the first pixel separation structure PIS1may have a round profile on a surface (e.g., a bottom surface) thereof. The first pixel separation structure PIS1may have a minimum vertical length at centers of the first and second parts P1and P2, and may also have a maximum vertical length at the intersection parts P3. For example, the first and second parts P1and P2of the first pixel separation structure PIS1may have vertical lengths that increase as approaching the intersection parts P3from the centers thereof.

The second pixel separation structure PIS2may be in contact with the first pixel separation structure PIS1. For example, the second pixel separation structure PIS2may be in contact with an entirety of the first pixel separation structure PIS1. The second pixel separation structure PIS2may have a third length L2ain a vertical direction at the first and second parts P1and P2, and may also have at the intersection parts P3a fourth length L2bin the vertical direction less than the third length L2a. The second pixel separation structure PIS2may have undulation on a surface adjacent to the first pixel separation structure PIS1.

Referring toFIGS.2A and3C, as discussed above, the first pixel separation structure PIS1may be vertically spaced apart from the second pixel separation structure PIS2, while overlapping the second pixel separation structure PIS2.

For example, the first and second parts P1and P2of the first pixel separation structure PIS1may be vertically spaced apart from the first and second parts P1and P2of the second pixel separation structure PIS2. Because, as discussed above, the intersection parts P3of the first pixel separation structure PIS1have lengths greater than those of the first and second parts P1and P2of the first pixel separation structure PIS1, the intersection parts P3of the first pixel separation structure PIS1may be in contact with the second pixel separation structure PIS2.

Referring toFIGS.2B and3D, the scattering patterns SP may include bar-shaped or polygonally shaped (e.g., rectangular) patterns, and the bar-shaped or polygonally shaped patterns may be disposed in all directions when viewed from a plan view. Some of the bar-shaped or polygonally shaped patterns may intersect each other, and may have at an intersection part vertical lengths greater than those of other parts,

FIG.5illustrates a plan view partially showing an image sensor according to an exemplary embodiment of the present inventive concept.FIG.6illustrates a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.5, showing an image sensor according to an exemplary embodiment of the present inventive concept.

Referring toFIGS.5and6, the scattering patterns SP may be omitted from each pixel region PR. For example, on each pixel region PR, the semiconductor substrate100may have a substantially flat surface on the second surface100b.

In an exemplary embodiment of the present inventive concept, because the first and second pixel separation structures PIS1and PIS2are formed in the semiconductor substrate100, the semiconductor substrate100may have an increased thickness. Therefore, even though the scattering patterns SP are omitted from each pixel region PR, it may be possible to secure optical absorption efficiency of incident light having a long wavelength.

FIG.7illustrates a plan view partially showing an image sensor according to an exemplary embodiment of the present inventive concept.FIG.8illustrates a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.7, showing an image sensor according to an exemplary embodiment of the present inventive concept.

Referring toFIGS.7and8, as discussed above, the first pixel separation structure PIS1may include first parts that extend in the first direction D1, second parts that extend in the second direction D2, and intersection parts connected to the first and second parts.

The second pixel separation structure PIS2may include first parts P1that extend in the first direction D1and second parts P2that extend in the second direction D2, and the first parts P1may be spaced apart from the second parts P2.

For example, the first and second parts of the first pixel separation structure PIS1may overlap and contact the first and second parts P1and P2, respectively, of the second pixel separation structure PIS2. The intersection parts of the first pixel separation structure PIS1may be spaced apart from the second pixel separation structure PIS2, and may be in contact with the semiconductor substrate100.

FIG.9illustrates a plan view partially showing an image sensor according to an exemplary embodiment of the present inventive concept.FIG.10illustrates a cross-sectional view taken along lines A-A′ and B-B′ ofFIG.9, showing an image sensor according to an exemplary embodiment of the present inventive concept.

Referring toFIGS.9and10, as discussed above, each of the first and second pixel separation structures PIS1and PIS2may include first parts P1that extend in the first direction D1, second parts P2that extend in the second direction D2intersecting the first direction D1, and intersection parts P3connected to the first and second parts P1and P2.

The first and second parts of the first pixel separation structure PIS1may have substantially the same width as each other. However, the present inventive concept is not limited thereto.

Each of the first parts P1of the second pixel separation structure PIS2may have a first width W1, which is at a first portion adjacent to the second parts P2, and a second width W2, which is greater than the first width W1, at a second portion spaced apart from the second parts P2. This may be applicable to the second parts of the second pixel separation structure PIS2. For example, each of the second parts P2of the second pixel separation structure PIS2may have a first width W1, which is at a first portion adjacent to the first parts P1, and a second width W2, which is greater than the first width W1, at a second portion spaced apart from the first parts P1. For example, the second pixel separation structure PIS2may have a minimum width at the intersection parts P3and a maximum width at the first and second parts P1and P2, for example, at a central portion of the first and second parts P1and P2. In addition, the widths of the first and second parts P1and P2may progressively increase as approaching a maximum-width position from a minim m-width position. In addition, the second pixel separation structure PIS2may have at the first and second parts P1and P2lengths greater than those at the intersection parts P3. For example, the second width W2at the second portion of the first and second parts P1and P2of the second pixel separation structure PIS2may be greater than that of the first and second parts of the first pixel separation structure PIS1. As such, because the second pixel separation structure PIS2has different widths at the first and second portions, the second pixel separation structure PIS2may contact an entirety of the first pixel separation structure PIS1.

FIG.11Aillustrates a cross-sectional view taken along line A-A′ ofFIG.1, showing an image sensor according to an exemplary embodiment of the present inventive concept.

Referring toFIGS.1and11A, an image sensor may include a sensor chip1and a logic chip2.

The sensor chip1, as discussed above, may include a photoelectric conversion layer10, a readout circuit layer20, and an optical transmission layer30.

As mentioned above, the photoelectric conversion layer10of the sensor chip1may include a semiconductor substrate100, first and second pixel separation structures PIS1and PIS2that provide pixel regions PR, and photoelectric conversion regions110provided in the pixel regions PR.

The semiconductor substrate100may include a light-receiving region AR, a light-shielding region OB, and a pad region R2. On the light-receiving region AR, the sensor chip1may have technical characteristics the same as those of the image sensor discussed above.

The first and second pixel separation structures PIS1and PIS2may be disposed in the semiconductor substrate100on the light-shielding region OB. A portion of the first pixel separation structure PIS1may be connected to a contact plug540on the light-shielding region OB. A contact pad CT may be disposed on the contact plug540, and the contact pad CT may be provided on a second surface100bof the semiconductor substrate100on the light-shielding region OB. The contact pad CT may include aluminum. The contact plug540may penetrate a portion of the semiconductor substrate100. As shown inFIG.11A, the contact plug540may have a stepwise sidewall profile. For example, the contact plug540may have a first surface and a second surface lower than the first surface. In addition, as shown inFIG.11B, the contact plug540may have a vertical or inclined sidewall.

A planarized dielectric layer310may extend from the light-receiving region AR toward the light-shielding region OB and the pad region R2. On the light-shielding region OB, a light-shielding pattern530may be disposed on the planarized dielectric layer310. The light-shielding pattern530may block incidence of light on the photoelectric conversion regions110provided on the light-shielding region OB.

On the light-shielding region OB, a first through conductive pattern510may penetrate the semiconductor substrate100and may have electrical connection with a metal line222of the readout circuit layer20and with a wiring structure1111of the logic chip2. The first through conductive pattern510may have a first bottom surface and a second bottom surface that are positioned at different levels. A first buried pattern511may be provided in the first through conductive pattern510. The first buried pattern511may include a material whose refractive index is relatively low and may have dielectric characteristics.

On the pad region R2, conductive pads CP may be provided on the second surface100bof the semiconductor substrate100. The conductive pads CP may include metal, such as aluminum, copper, tungsten, titanium, tantalum, or any alloy thereof. A plurality of bonding wires may be bonded to the conductive pads CP in an image sensor mounting process. The conductive pads CP may be electrically connected through the bonding wires to an external device.

According to an exemplary embodiment of the present inventive concept, the first and second pixel separation structures PIS1and PIS2may be provided on the pad region R2and may be disposed around the conductive pads CP.

On the pad region R2, a second through conductive pattern520may penetrate the semiconductor substrate100and may have electrical connection with the wiring structure1111of the logic chip2. The second through conductive pattern520may extend on the second surface100bof the semiconductor substrate100and may have electrical connection with the conductive pads CP. The second through conductive pattern520may have a portion550that covers, for example, bottom surfaces and sidewalls of the conductive pads CP. A second buried pattern521may be provided in the second through conductive pattern520. The second buried pattern521may include a material whose refractive index is relatively low and may have dielectric characteristics.

The logic chip2may include a logic semiconductor substrate1000, logic circuits TR, wiring structures1111connected to the logic circuits TR, and logic interlayer dielectric layers1100. An uppermost one of the logic interlayer dielectric layers1100may be coupled to the readout circuit layer20of the sensor chip1. The logic chip2may be electrically connected to the sensor chip1through the first through conductive pattern510and the second through conductive pattern520.

FIG.11Billustrates a cross-sectional view taken along line A-A′ ofFIG.1, showing an image sensor according to an exemplary embodiment of the present inventive concept. The technical features the same as those of the image sensor discussed with reference toFIG.11Awill be omitted in the interest of brevity, and a difference thereof will be described below.

According to the embodiment illustrated inFIG.11B, an image sensor may be configured such that the sensor chip1may include first bonding pads BP1provided on an uppermost metal layer of the readout circuit layer20, and that the logic chip2may include second bonding pads BP2provided on an uppermost metal layer of the readout circuit layer20and on the wiring structure1111. The first and second bonding pads BP1and BP2may include, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and/or titanium nitride (TiN).

A hybrid bonding may be used to directly and electrically connect the first bonding pads BP1of the sensor chip1to the second bonding pads BP2of the logic chip2. In this description, the term “hybrid bonding” may denote a bonding method in which two components of the same kind are merged at an interface therebetween. For example, when the first and second bonding pads BP1and BP2are formed of copper, a copper-to-copper bonding may be employed to physically and electrically connect the first and second bonding pads BP1and BP2to each other. In addition, a dielectric-to-dielectric bonding may be adopted to couple a surface of a dielectric layer included in the sensor chip1to a surface of a dielectric layer included in the logic chip2.

FIGS.12to17illustrate cross-sectional views taken along line A-A′ ofFIG.1, showing a method of fabricating an image sensor according to an exemplary embodiment of the present inventive concept.

Referring toFIGS.1and12, a semiconductor substrate100may be provided with a first conductivity type (e.g., p-type). For example, the semiconductor substrate100may include an epitaxial layer. The semiconductor substrate100may have a first surface100aand a second surface100bthat are opposite to each other. The semiconductor substrate100may include a pad region R2and a pixel array region R1that includes a light-receiving region AR and a light-shielding region OB. The light-receiving region AR and the light-shielding region OB may each include a plurality of pixel regions PR.

On each pixel region PR, a device isolation layer101may be formed to adjoin the first surface100aof the semiconductor substrate100and to provide active sections of the semiconductor substrate100. The device isolation layer101may be formed by forming a shallow trench by patterning the first surface100aof the semiconductor substrate100and then depositing a dielectric material in the shallow trench. The device isolation layer101may be formed before or after photoelectric conversion regions110are formed.

A first pixel separation structure PIS1may be formed on the semiconductor substrate100, providing the pixel regions PR.

The formation of the first pixel separation structure PIS1may include forming a deep trench by patterning the first surface100aof the semiconductor substrate100, and forming a liner dielectric layer to conformally cover an inner wall of the deep trench. The formation of the first pixel separation structure PIS1may further include depositing a semiconductor layer to fill the deep trench in which the liner dielectric layer is formed, and forming in the deep trench a liner dielectric pattern103and a semiconductor pattern105by planarizing the liner dielectric layer and the semiconductor pattern105to expose the first surface100aof the semiconductor substrate100. The liner dielectric pattern103may include, for example, one or more of silicon oxide, silicon nitride, and/or silicon oxynitride. The semiconductor pattern105may include one or more of an impurity-doped polysilicon layer and an undoped polysilicon layer.

Photoelectric conversion regions110may be formed in the semiconductor substrate100. The semiconductor substrate100may be doped with impurities having a second conductivity type (e.g., n-type) different from the first conductivity type, and thus the photoelectric conversion regions110may be formed on corresponding pixel regions PR.

MOS transistors may be formed on the first surface100aof the semiconductor substrate100, constituting readout circuits. For example, transfer gate electrodes TG may be formed on the first surface100aof the semiconductor substrate100with a gate dielectric layer between the semiconductor substrate100and each of the transfer gate electrodes TG. Gate electrodes of readout transistors may also be formed together with the transfer gate electrodes TG.

After the formation of the transfer gate electrodes TG, floating diffusion regions FD may be formed in the semiconductor substrate100on sides of the transfer gate electrodes TG. The floating diffusion regions FD may be formed by implanting impurities having the second conductivity type. In addition, source/drain impurity regions of the readout transistors may also be formed together with floating diffusion regions FD.

Interlayer dielectric layers210and wiring structures221and222may be formed on the first surface100aof the semiconductor substrate100. The interlayer dielectric layers210may cover transfer transistors and logic transistors. The interlayer dielectric layers210may be formed of a material having superior gap-fill properties and may have their planarized upper portions.

Contact plugs221may be formed to lie in the interlayer dielectric layers210and to have connection with the floating diffusion regions FD or the readout transistors. Metal lines222may be formed in the interlayer dielectric layers210. The contact plugs221and the metal lines222may be formed of, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), or any alloy thereof.

Referring toFIGS.1and13, a logic chip2may be coupled to the first surface100aof the semiconductor substrate100.

The logic chip2may include a logic semiconductor substrate1000, logic circuits TR, wiring structures1111connected to the logic circuits TR, and logic interlayer dielectric layers1100. An interlayer dielectric layer1100of the logic chip2may be coupled to an interlayer dielectric layer210on the first surface100aof the semiconductor substrate100. For example, on the first surface100aof the semiconductor substrate100, an uppermost interlayer dielectric layer1100of the logic chip2may be coupled to a lowermost interlayer dielectric layer210.

After the bonding of the logic chip2, a thinning process may be performed to cause the semiconductor substrate100to have a reduced thickness. The thinning process may include a grinding or polishing process being executed on the second surface100bof the semiconductor substrate100. The semiconductor substrate100may be turned upside down to perform the thinning process thereon. The thinning process may remove a portion of the semiconductor substrate100, and then an isotropic or anisotropic etching process may be performed to remove surface defects remaining on the semiconductor substrate100.

For example, the semiconductor substrate100may include an epitaxial layer on a bulk silicon substrate, and may undergo the thinning process to remove the bulk silicon substrate and to leave a p-type epitaxial layer. In an exemplary embodiment of the present inventive concept, a value of about 8 μm to about 15 μm may be given a thickness of the semiconductor substrate100that remains after the thinning process.

After the thinning process, on the pad region R2, the second surface100bof the semiconductor substrate100may be patterned to form a pad trench PT.

Referring toFIGS.1and14, on the pixel array region. R1, the second surface100bof the semiconductor substrate100may be patterned to form first and second trenches T1and T2at substantially the same time.

The formation of the first and second trenches T1and T2may include forming a mask pattern on the second surface100bof the semiconductor substrate100and using the mask pattern as an etching mask to anisotropically etch the semiconductor substrate100. When the first and second trenches T1and T2are foraged, the first trench T1may expose the first pixel separation structure PIS1. The first trench T1and the second trench12may have different widths from each, and different depths from each other. For example, the first trench T1may have a width greater than that of the second trench T2, and the first trench T1may have a depth greater than that of the second trench T2.

According to an exemplary embodiment of the present inventive concept, the first trench T1may be formed on the pixel array region R1and the pad region R2, and when the first trench T1is formed, the semiconductor pattern105of the first pixel separation structure PIS1may be exposed.

According to an exemplary embodiment of the present inventive concept, when the first trench T1is formed, the linear dielectric pattern103, disposed on the semiconductor pattern105, of the first pixel separation structure PIS1may be exposed.

On the light-shielding region OB, the first trench T1may partially expose the first pixel separation structure PIS1. For example, on the light-shielding region OB, the first trench T1may not be formed on a portion of the first pixel separation strut re PIS1.

Referring toFIGS.1and15, a surface dielectric layer121and a gap-fill dielectric layer123may be sequentially formed in the first and second trenches T1and T2.

The surface dielectric layer121may be conformally deposited on surfaces of the first and second trenches T1and T2and on the second surface100bof the semiconductor substrate100. An atomic layer deposition (ALD) process may be performed to form the surface and gap-fill dielectric layers121and123. The gap-fill dielectric layer123may fill the first and second trenches T1and T2in which the surface dielectric layer121is formed, and may have a substantially flat top surface. The surface and gap-fill dielectric layers121and123may include metal oxide, such as one or more of aluminum oxide and/or hafnium oxide. In addition, on the pad region R2, the surface and gap-fill dielectric layers121and123may conformally cover an inner wall of the pad trench PT.

A planarized dielectric layer310may be formed on a top surface of the gap-fill dielectric layer123. The formation of the planarized dielectric layer310may include sequentially depositing a first planarized layer311, a second planarized layer313, and a third planarized layer315. The first, second, and third planarized layers311,313, and315may be formed of a transparent dielectric material and may have different thicknesses from each other. The first, second, and third planarized layers311,313, and315may include, for example, metal oxide and/or silicon oxide.

Referring toFIGS.1and16, on the light-shielding region OB, a contact hole may be formed to penetrate a portion of the semiconductor substrate100and to expose a portion of the semiconductor pattern105included in the first pixel separation structure PIS1.

On the light-shielding region OB, a first through hole501may be formed to penetrate the semiconductor substrate100and to expose the wiring structure1111of the logic chip2. On the pad region R2, a second through hole502may be formed to penetrate the semiconductor substrate100and to expose the wiring structure1111of the logic chip2.

The first through hole501may have a first bottom surface and a second bottom surface at different levels from each other. The first bottom surface of the first through hole501may expose the metal line222of the readout circuit layer20, and the second bottom surface of the first through hole501may expose the wiring structure1111of the logic chip2.

Afterwards, a conductive layer may be deposited on the planarized dielectric layer310. The conductive layer may conformally cover a surface of the planarized dielectric layer310, an inner wall of the contact hole, an inner wall of the first through hole501, and an inner wall of the second through hole502. After the conductive layer is deposited, the conductive layer may undergo a patterning process to remove the conductive layer from the light-receiving region AR. The conductive layer may include metal, such as copper, tungsten, aluminum, titanium, tantalum, or any alloy thereof.

As the patterning process is performed on the conductive layer, a contact plug540may be formed in the contact hole, and on the light-shielding region OB, a light-shielding pattern530may be formed on the planarized dielectric layer310. In addition, first and second through conductive patterns510and520may be formed in the first and second through holes501and502, respectively.

The first through conductive pattern510may be electrically connected to the metal line222of the readout circuit layer20and to the wiring structure1111of the logic chip2. As shown, the second through conductive pattern520may be electrically connected to a conductive pad CP. The second through conductive pattern520may extend into the second through hole502and may cover the second through hole502. For example, the second through conductive pattern520may conformally cover a sidewall and a bottom surface of the second through hole502. The second through conductive pattern520may be electrically connected to the wiring structure1111of the logic chip2.

A contact plug540may be provided on the second surface100bof the semiconductor substrate100on the light-shielding region OB. A contact trench may be formed on the second surface100bof the semiconductor substrate100, and the contact plug540may be provided in the contact trench.

The contact pad CT may be connected to the contact plug540. The contact pad CT may include a conductive material different from that of the contact plug540. For example, the contact pad CT may include aluminum. The contact pad CT may be electrically connected to the semiconductor pattern105of the first pixel separation structure PIS1. A negative bias may be applied thorough the contact pad CT to the semiconductor pattern105of the first pixel separation structure PIS1, and a predetermined bias may be transmitted to the pixel array region R1.

On the pad region R2, the conductive pad CP may be buried in the pad trench of the semiconductor substrate100. The conductive pad. CP may include metal, such as aluminum, copper, tungsten, titanium, tantalum, or any alloy thereof. For example, a bonding wire may be formed on and coupled to the conductive pad CP in an image sensor mounting process. The conductive pad CP may be electrically connected to an external device via the bonding wire.

Referring toFIGS.1and17, on the light-receiving region AR, a grid structure320may be formed on the planarized dielectric layer310.

When viewed from a plan view, as discussed above, the grid structure320may overlap the first and second pixel separation structures PIS1and PIS2in the semiconductor substrate100.

The formation of the grid structure320may include sequentially forming a light-shielding layer and a low-refractive layer on the planarized dielectric layer310, forming a mask pattern on the low-refractive layer, and using the mask pattern as an etching mask to sequentially etch the low-refractive layer and the light-shielding layer to expose the planarized dielectric layer310.

In an exemplary embodiment of the present inventive concept, the grid structure320on the light-receiving region AR may be formed simultaneously with the light-shielding pattern530on the light-shielding region OB. In an exemplary embodiment of the present inventive concept, the grid structure320may also be formed on the light shielding region OB after the light-shielding pattern530is formed on the light-shielding region. OB.

When the grid structure320is formed, buried dielectric patterns may fill the first through hole501in which the first through conductive pattern510is formed and the second through hole502in which the second through conductive pattern520is formed. The buried dielectric patterns may include the same material of the grid structure320. For example, the buried dielectric patterns may include a relatively low-refractive material and may have dielectric characteristics.

A protection layer330may be formed to conformally cover a surface of the grid structure320and a top surface of the planarized dielectric layer310exposed by the grid structure320. The protection layer330may be formed by, for example, performing a chemical vapor deposition process or an atomic layer deposition process. The protection layer330may be formed of a single layer or multiple layers. The protection layer330may include one or more of an aluminum oxide layer and/or a silicon carbon oxide layer.

Referring toFIGS.11A and11B, a microlens array340including microlenses that correspond to the pixel regions PR may be formed.

The microlens array340may be formed by forming an optical transmissive photoresist layer, partially patterning the photoresist layer to form photoresist patterns that correspond to the pixel regions PR, and reflowing the photoresist patterns. Thus, the microlenses may be formed with upwardly convex shapes having a substantially constant curvature. For example, after the microlenses are formed, a uniformly thick planarized member may be formed below the microlenses.

An organic layer345may be formed on the light-shielding region OB and the pad region R2. The organic layer345may be connected to the microlens array340. The organic layer345may include the same material as that of the microlens array340. The organic layer345may expose the conductive pad CP on the pad region R2.

After the formation of microlens array340, a passivation layer350may be formed to conformally cover surfaces of the microlens array340. The passivation layer350may be formed of, for example, inorganic oxide.

According to an exemplary embodiment of the present inventive concept, a first pixel separation structure may be provided adjacent to a first surface of a semiconductor substrate, and a second pixel separation structure may be provided adjacent to a second surface of the semiconductor substrate. It may thus be possible to increase a thickness of the semiconductor substrate in which photoelectric conversion regions are provided, and unit pixels may have increased quantum efficiency, or optical absorption efficiency of incident light (e.g., infrared light).

Furthermore, the first and second pixel separation structures may divide adjacent unit pixels from each other, and therefore crosstalk issues may be reduced between neighboring unit pixels.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the present inventive concept.