Patent ID: 12223328

DETAILED DESCRIPTION

Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

As used herein, a control flow refers to an order in which instructions (e.g., statements and/or function calls of a program) are executed. The order in which a number of instructions are executed can vary according to jumps, unconditional branches, conditional branches, loops, returns, and/or halts, among other instruction types associated with a program. In a number of examples, the number of instructions can also be function calls. An if-then statement is an example of a conditional branch. The condition evaluated in association with the if-then statement can be evaluated by a first device (e.g., a host processor) to generate a control flow. For example, a first set of instructions or a second set of instructions can be executed by a second device given the evaluation of a condition by the first device. The first device can further evaluate loops (e.g., for loops, while loops, etc.), for instance, to generate a number of instructions that are executed by a second device and an order associated with the number of instructions.

In various previous approaches, the control flow is generated and the instructions associated with the control flow are executed by a same device (e.g., a host processor). For example, the same device that generates a number of instructions and an order of execution associated with the instructions also executes the number of instructions according to the generated order. Generating the control flow and executing the instructions associated with the control flow in a same device can include generating the control flow before executing the instructions. For example, the control flow cannot be generated and the instructions executed at the same time if a single device is generating the control flow and executing the associated instructions.

In a number of examples according to the present disclosure, a first device can generate the control flow and a second device can execute the instructions corresponding to the control flow. For example, the control flow can be generated concurrently with the execution of the control flow. As used herein, instructions corresponding to a control flow, which may be referred to as “control flow instructions,” are meant to refer to instructions that involve manipulating data. For instance, instructions that involve manipulating data include instructions involving performing computations on data, which can include mathematical operations (e.g., addition, subtraction, multiplication, and/or division), which can include performing various Boolean logic operations such as AND, OR, invert, etc. Examples of instructions that do not involve manipulating data include memory commands such as data read, data write, and data refresh operations.

As an example, the first device can be a host. A host can include one of a central processing unit (CPU), a system on a chip (SoC), and an application specific integrated circuitry (ASIC), for instance. As an example, a SoC can comprise one or more processors and one or more controllers (e.g., channel controllers) coupled to a number of memory devices. A second device can be a memory device including a memory array, an execution unit, which can comprise sensing circuitry that includes a number of compute components, and a controller that controls of the execution unit to execute the instructions. The controller of the memory device can operate the compute components of the execution unit to coordinate the execution of the instructions associated with the control flow.

As an example, the instructions generated by a host can be executed by performing a number of operations. For example, an “add” instruction includes performing various logical operations. As used herein, instructions and operations are used interchangeably. Operations can be compare operations, swap operations, and/or logical operations (e.g., AND operations, OR operations, SHIFT operations, INVERT operations etc.). However, embodiments are not limited to these examples. As used herein, executing Single Instruction Multiple Data (SIMD) operations is defined as performing a same operation on multiple elements in parallel (e.g., simultaneously). As used herein, an element is a numerical value that can be stored (e.g., as a bit-vector) in a memory array.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “J,” “N,” “R,” “S,” “U,” “V,” “W,” and ‘X’ particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays).

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example,110may reference element “10” inFIG.1, and a similar element may be referenced as210inFIG.2. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

FIG.1is a block diagram of an apparatus in the form of a computing system100in accordance with a number of embodiments of the present disclosure. As used herein, a host110, a memory device120, a memory array130, and/or sensing circuitry150might also be separately considered an “apparatus” and/or a device.

System100includes a host110coupled to memory device120, which includes a memory array130. Host110can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host110can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) such as a CPU, SoC, ASIC, and/or memory buffer (e.g., registered dual in-line memory module (DIMN)). The system100can include separate integrated circuits or both the host110and the memory device120can be on the same integrated circuit. The system100can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown inFIG.1illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-von Neumann architectures (e.g., a Turing machine), which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

For clarity, the system100has been simplified to focus on features with particular relevance to the present disclosure. The memory array130can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array130can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single array130is shown inFIG.1, embodiments are not so limited. For instance, memory device120may include a number of arrays130(e.g., a number of banks of DRAM cells). An example DRAM array is described in association withFIG.6.

The memory device120includes address circuitry142to latch address signals provided over an I/O bus156(e.g., a data bus) through I/O circuitry144. Address signals are received and decoded by a row decoder146and a column decoder152to access the memory array130. Data can be read from memory array130by sensing voltage and/or current changes on the sense lines using sensing circuitry150. The sensing circuitry150can read and latch a page (e.g., row) of data from the memory array130. The I/O circuitry144can be used for bi-directional data communication with host110over the I/O bus156. The write circuitry148is used to write data to the memory array130.

Controller140decodes signals provided by control bus154from the host110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array130, including data read, data write, and data erase operations. In various embodiments, the controller140is responsible for executing instructions from the host110. The controller140can be a state machine, a sequencer, or some other type of controller.

As described further below, the controller140can comprise of multiple controllers (e.g., separate controller units). In a number of embodiments, the sensing circuitry150can comprise a number of sense amplifiers and a number of compute components, which may comprise an accumulator and can be used to perform logical operations (e.g., on data associated with complementary sense lines). In a number of embodiments, the sensing circuitry (e.g.,150) can be used to perform (e.g., execute) operations on data stored in array130and to store the results of the sort operation back to the array130without transferring data via a sense line address access (e.g., without firing a column decode signal) and/or without enabling a local I/O line coupled to the sensing circuitry. As such, operations can be performed using sensing circuitry150rather than and/or in addition to being performed by processing resources external to the sensing circuitry150(e.g., by a processor associated with host110and/or other processing circuitry, such as ALU circuitry, located on device120(e.g., on controller140or elsewhere)). In a number of embodiments the sensing circuitry150can be referred to as an execution unit. The execution unit may be coupled to the memory array130and/or may be decoupled from the memory array130.

As such, in a number of embodiments, registers and/or an ALU external to array130and sensing circuitry150may not be needed to perform various operations as the sensing circuitry150can be controlled to perform the appropriate computations involved in performing operations using the address space of memory array130. Additionally, operations can be performed without the use of an external processing resource. For instance, an external processing resource such as host110may generate a control flow, but the host110(e.g., an ALU of the host) may not be used to perform computations associated with executing the instructions corresponding to the control flow.

FIG.2is a block diagram of an apparatus in the form of a computing system200in accordance with the prior art. The system200includes a host210, a memory device220-1, and a memory device220-2. The host210includes an ALU260and cache262. Memory device220-1includes memory array230.

As used herein, the host210is a first device and the memory device220-1is a second device. Memory device220-1and/or memory device220-2can be volatile memory and/or non-volatile memory. For example, memory device220-1can be a volatile memory (e.g., DRAM) and memory device220-2can be non-volatile memory (e.g., a hard drive, solid state drive (SSD), etc.).

In a number of previous approaches, the host210can request data from memory device220-1. The memory device220-1can transfer the data stored in memory array230to the host210. The memory device220-1can retrieve the data from memory device220-2(e.g., via a suitable interface represented by arrow272) if memory device220-1does not have the requested data. The memory device220-1can store the data retrieved from memory device220-2in memory array230. The data can be stored in cache262by the host210. The data can be, for example, a set of executable instructions associated with performing a particular task (e.g., a program).

The ALU260can be used by the host210to identify the location of a number of instructions that need to be executed from the data stored in the cache262. After each instruction is identified, by the ALU260, the host210can execute the identified instruction (as indicated by arrow268). For example, the host210can generate a control flow and can further execute the instructions associated with the control flow.

FIG.3is a block diagram of an apparatus in the form of a computing system300in accordance with a number of embodiments of the present disclosure. The system300includes a host310, a memory device320-1, and a memory device320-2. In this example, the host310includes an ALU360and cache362, and the memory device320-1includes a controller340, memory array330, and sensing circuitry350.

The host310can be referred to as a first device and can comprise a CPU, SoC which may include a number of processors and a number of channel controllers (not shown), for example, and/or an ASIC, among other types of devices. The host310can be used to generate a control flow, which includes instructions and an execution order associated with the instructions. In a number of examples, the host310can utilize the ALU360to generate the control flow. Generating a control flow is further described inFIG.5.

The host310can request data associated with a program from memory device320-1. The memory device can retrieve the requested data from memory array330. The memory device can return the data to host310. The host can store the data in cache362and utilize the ALU360to generate a control flow. In a number of examples, the data can be data associated with a set of executable instructions (e.g., a program). The program can be represented in various formats. For example, the program can be represented as a source file, an assembly file, an object file, and/or an executable file. In a number of examples, the program can be generated dynamically. For example, the program can be provided via assembly file and/or a buffer.

The data retrieved from memory array330can be used by host310to generate a control flow. For example, the ALU360can be used to retrieve a number of instructions that represent operations.FIG.5further describes the process of generating instructions.

In contrast to the example ofFIG.2, in which the control flow instructions generated by host210are executed on the host210(e.g., as indicated by arrow268), in the example shown inFIG.3, the host310can provide the control flow instructions and an order of execution associated with the instructions to the memory device320-1for execution on the device320-1(e.g., via an execution unit local to device320-1). For example, although host310includes an ALU360, which may be configured to execute control flow instructions generated by host310, in a number of embodiments, the execution of the control flow instructions generated by host310occurs on a separate device (e.g., memory device320-1). As an example, the memory device320-1can receive the control flow instructions from the host310at controller340. The controller340can receive the instructions via a buffer, a memory array, and/or shift circuitry of memory device320-1, for instance.

The controller340can control execution of the control flow instructions on data stored in memory cells in the memory array330. For example, the controller340can control the execution of the instructions by controlling the sensing circuitry350, which may serve as an execution unit, to perform a number of operations associated with the control flow instructions. In contrast, the memory device220-1shown inFIG.2may have a controller (not shown); however, such a controller would control execution of instructions other than command flow instructions. For example, a controller on device220-1might control execution of memory command operations such as data read, data write, and data refresh operations, which do not involve manipulation of data associated with computations, but would not control execution of command flow instructions.

Control flow instructions can include a number of operations including AND operations, OR operations, INVERT operations, and/or SHIFT operations. The number of operations can include other operations. For example the operations can be any number of binary operations and non-binary operations such as an addition operation, a multiplication operation, and/or a comparison operation. In a number of examples, the number of operations can be performed without transferring data via an input/output (I/O) line634inFIG.6.

The controller340can control a plurality of compute components (e.g., compute components631-0,631-1,631-2,631-3,631-4,631-5,631-6,631-7, . . . ,631-X inFIG.6, referred to generally as compute components631) coupled to a plurality of sense lines (e.g., sense lines605-0,605-1,605-2,605-3,605-4,605-5,605-6,605-7, . . . ,605-S inFIG.6, referred to generally as sense lines605) and formed on pitch with the plurality of memory cells (e.g., memory cells603-0,603-1,603-2,603-3,603-4,603-5,603-6, . . . ,603-J inFIG.6, referred to generally as memory cells603) in array330. The controller can also control a plurality of sense amplifiers (e.g., sense amplifiers606-0,606-1,606-2,606-3,606-4,606-5,606-6,606-7, . . . ,606-U inFIG.6, referred to generally as sense amplifiers606) coupled to the plurality of compute components631. The controller340can control the compute components631and the sense amplifiers606to execute the instructions.

For example, the controller340can activate a number of sense lines605and access lines (e.g., access lines604-0,606-1,606-2,606-3,606-4,606-5,606-6, . . . ,606-R inFIG.6, referred to generally as access lines604) in array330to read the data in the array330. The data can be stored in the sense amplifiers606and/or the compute components631. The controller340can further activate the sense lines605, access lines604, and/or latches associated with the compute components631and/or sense amplifiers606to execute a number of operations on the data stored in the sense lines605and/or the compute components631.

The controller340can also activate the sense lines605and/or the access lines604to store the results of the operations (e.g., the results of the execution of the number of instructions) back to the array330. In a number of examples, the controller340can further transfer the results of the operations and/or an indication that the operations have been executed back to host310.

In a number of examples, the controller340can comprise a number of controllers. For example, the controller340can comprise a first controller and a number of second controllers. The first controller can receive the number of instructions from the host310. The instructions can include instructions to perform, for example, an addition operation. The first controller can translate the number of instructions into a number of AND operations, OR operations, INVERT operations, and/or SHIFT operations, for example. The first controller can provide the AND operations, OR operations, INVERT operations, and/or SHIFT operations to the number of second controllers. The number of second controllers can control the compute components631and the sense amplifiers606to execute the AND operations, OR operations, INVERT operations, and/or SHIFT operations. For example, the number of second controllers can activate the sense lines605, access lines604, and/or latches associated with the compute components631and/or sense amplifiers606to execute the AND operations, OR operations, INVERT operations, and/or SHIFT operations. In a number of examples, each of the number of second controllers can control the compute components631and/or the sense amplifiers606to execute at least one of the AND operations, OR operations, INVERT operations, and/or SHIFT operations.

In accordance with a number of embodiments, a device on which a control flow is generated (e.g., host310) can be independent from a device on which the corresponding control flow instructions are executed (memory device320-1). As an example, a control flow can be generated in a number of portions. For instance, the host310can generate a control flow that includes a first portion and a second portion, with the first portion comprising a first number of control flow instructions and the second portion comprising a second number of control flow instructions. As an example, the host310can generate a first number of instructions that are associated with the first portion of the control flow and provide them to the memory device320-1. The host310can generate the second number of instructions that are associated with the second portion of the control flow while the execution of the first number of instructions is occurring on the memory device320-1(e.g., the generation of the second portion of the control flow can occur concurrently with execution of the first portion of the control flow). The memory device320-1can return a result of the execution of the first number of instructions to the host310and the host310can provide the second number of instructions to the memory device320-1. The memory device320-1can provide the result of the execution of the second number of instructions and/or an indication that the second number of instructions have been executed to the host310.

Separating the creation of the control flow from the execution of the control flow provides the ability to execute the control flow concurrently with the creation of the control flow. Furthermore, separating the creation of the control flow from the execution of the control flow eliminates the need to move data to be operated on in association with the execution of the control flow to a host310, since the control flow instructions are executed via an execution unit on a device (e.g.,320-1) separate from the host310.

FIG.4is a block diagram of an apparatus in the form of a computing system in accordance with a number of embodiments of the present disclosure. System400includes a host410that can be analogous to host310inFIG.3.FIG.4also includes memory devices420-1,420-2, . . . ,420-N (e.g., referred to generally as memory devices420), which can be analogous to memory device320.

In this example, each of the memory devices420includes a controller, a memory array, and sense circuitry. For example, memory device420-1includes controller440-1, memory array430-1, and sense circuitry450-1, memory device420-2includes controller440-2, memory array430-2, and sense circuitry450-2, and memory device420-N includes controller440-N, memory array430-N, and sense circuitry450-N. The controller440-1, the controller440-2, . . . , and the controller440-N are referred to generally as controllers440. The array430-1, the array430-2, . . . , and the array430-N are referred to generally as arrays430. The sense circuitry450-1, the sense circuitry450-2, . . . , and the sense circuitry450-N are referred to generally as sense circuitry450. As described further below, in a number of embodiments, the sense circuitry450can be operated (e.g., by a corresponding controller440) to serve as an execution unit.

Host410can generate a number of different control flows. Each of the control flows can be associated with a particular memory device420. For example, a first control flow can be associated with memory device420-1, a second control flow can be associated with memory device420-2, . . . , and an Nth control flow can be associated with memory device420-N. Arrows from host410to devices420-1to420-N represent an interface (e.g., bus) over which data, addresses, and/or commands can be transferred. However, the devices420may be coupled to the host410via a common bus, for instance.

As an example, each of the different control flows can be associated with a single (e.g., same) program and/or the different control flows can be associated with a different programs. For example, the first and second control flow can be associated with a first program and the Nth control flow can be associated with a second (e.g., different) program. The first control flow can be associated with a first portion of the first program that is independent from a second portion of the first program. The second control flow can be associated with a second portion of the first program that is independent from the first portion of the first program. A first portion of a program can be considered as being independent from a second portion of a program if executing a number of instructions associated with the first portion does not have an impact on the execution of a second number of instructions associated with the second portion of the program.

Each of the memory devices420can execute different instructions from a plurality of instructions associated with the plurality of control flows. For example, the memory device420-1can execute a first number of instructions associated with the first control flow, the memory device420-2can execute a second number of instructions associated with the second control flow, . . . , and the memory device420-N can execute an Nth number of instructions associated with the Nth control flow.

In contrast to the example ofFIG.2, in which the creation of a control flow and execution of the corresponding control flow instructions occur on the same device, embodiments of the present disclosure can involve separating the creation of the control flows and the execution of the control flows, which can allow a number of processes to be executed concurrently. As used herein, a process refers to an instance of a program that is being executed. For example, a process can be executed concurrently with the execution of a second program.

Concurrent execution of a number of processes can include a host410generating control flows while the memory devices420are executing the control flows. For example, host410can generate a first control flow. The host410can provide the first control flow to memory device420-1. The host410can generate a second control flow while the memory device420-1is executing a first number of instructions associated with the first control flow via the controller440-1, the memory array430-1, and the sense circuitry450-1. The host410can provide the second control flow to memory device420-2while the memory device420-1is executing the first number of instructions associated with the first control flow. The host410can generate and provide an Nth control flow to the memory device420-N while the memory device420-1and the memory device420-2are executing the first number of instructions associated with the first control flow and the second number of instructions associated with the second control flow, respectively. The memory device420-2can execute the second number of instructions via the controller440-2, the memory array430-2, and the sense circuitry450-2. Each of the memory devices420can execute a different plurality of instructions associated with different control flows concurrently. For example, the memory device410-2can execute the first number of instructions, the memory device410-2can execute the second number of instructions, and the memory device410-N can execute the Nth number of instructions concurrently. The memory device410-N can execute the Nth number of instructions via the controller440-N, the memory array430-N, and the sense circuitry450-N.

Each of the memory devices420can return a result of the execution of the different plurality of instructions and/or an indication that the different plurality of instructions have been executed. For example, the memory device420-1can inform the host410that the first number of instructions have been executed while the second number of instructions and the Nth number of instructions are being executed (e.g., on devices420-2and420-N, respectively). The host410can generate a different control flow that is associated with the first control flow based on the result of the first number of instructions that are associated with the first control flow. The host410can provide the different control flow to the memory device420-1while the memory device420-2and the memory device420-N are executing the second number of instructions and the Nth number of instructions, respectively. Each of the different control flows can be generated serially. For example, the second control flow can be generated after the first control flow is generated and the Nth control flow can be generated after the first control flow and the second control flow are generated. Each of a different number of instructions associated with the different control flows can be executed concurrently (e.g., at a same time). Each of the different number of instructions associated with the control flow can be executed concurrently with the creation of the different control flows.

The example ofFIG.4provides the ability to generate a number of control flows and execute a number of control flows concurrently by separating the creation of the control flow from the execution of the control flow. Executing a number of control flows concurrently can increase productivity and can utilize a greater number of computational resources concurrently as opposed to executing a single control flow at a time as provided in the example ofFIG.2. As an example, the ALU460of host410can be configured to determine the manner in which control flows are generated and/or distributed among the devices420for execution.

FIG.5is a block diagram of a control flow and the execution of the control flow in accordance with a number of embodiments of the present disclosure.FIG.5illustrates a system500that includes a device510and a device520. Generating a control flow can include fetching, decoding, and generating control flow instructions, which can include memory operable instructions. Executing the memory operable instructions includes receiving the memory operable instructions586, operating an execution unit (e.g., by activating access lines, sense lines, and latches), and returning the result of the execution of the memory operable instructions.

In the example shown inFIG.5, device510can be a host (e.g., host410) configured to generate control flows, and device520can be a memory device (e.g., device420) configured to execute at least some control flow instructions generated by the device510. Fetching, decoding, and/or generating memory operable instructions can be classified as host operable instructions. Host operable instructions are instructions that a host (e.g., device510) uses to create memory operable instructions. For example, the host operable instructions are instructions that the host uses to create a number of operations that are executed by device520. Memory operable instructions are further described below.

As described above the device510can be a host and the device520can be a memory device. Host510can be associated with a program counter. The program counter holds the memory address of the next instruction to be executed. The program counter can be incremented to get the address of the next instructions.

At580, the device510fetches an instruction from memory using the program counter. At the end of the fetch operation the program counter can point to the next instruction that will be read at the next cycle. The device510can store the fetched instruction in a cache. Cache can be, for example, an instruction register and/or another form of memory.

At582, the device510decodes the fetched instruction. Decoding the fetched instruction can include determining an operation to be performed based on op-code associated with the fetched instruction. For example, the device510can decode an instruction (e.g., fetched instruction) to determine that an addition operation is to be performed.

At584, the device510generates memory operable instructions. Generating memory operable instructions can include dynamically generating memory operable instructions. Dynamically generating memory operable instructions can be synonymous with dynamically generating a control flow because the memory operable instructions can be control flow instructions that are associated with a control flow. The memory operable instructions can be dynamically generated when the device510evaluates the decoded instructions to generate the memory operable instructions. The device510can dynamically generate memory operable instructions by evaluating a decoded instruction to generate the memory operable instructions. For example, a decoded instruction can be an if-then statement. The if-then statement can be dynamically evaluated by the device510. The device510can dynamically select a first memory operable instruction instead of a second memory operable instruction based on the evaluation of the if-then statement. In a number of examples, the memory operable instructions can be dynamically generated after a program has been compiled.

As used herein, memory operable instructions refers to instructions that are to be executed by the device520. Memory operable instructions can include logical operations (e.g., AND operation, OR operations, etc.), addition operations, subtraction operations, multiplication operations, division operations, and/or comparison operations among other types of operations that can be associated with control flow instructions. Furthermore, memory operable instructions can include read operations and/or write operations (e.g., memory commands that do not involve manipulating data).

A plurality of memory operable instructions can be generated or a single memory operable instruction can be generated by device510. At586, the device520can receive the memory operable instructions. The memory operable instructions can be received at a controller (e.g., controller340). At588, the device520can activate access lines, sense lines, and/or latches to execute the memory operable instructions. For example, the controller can activate a number of access lines, sense lines, and/or latches associated with a memory array and/or sense circuitry in device520. Activating the number of access lines, sense lines, and/or latches can move data from array in to the sensing circuitry.

The controller can further activate access lines, sense lines, and/or latches in sense circuitry to execute the memory operable instructions on the data stored in the sensing circuitry. In a number of examples, the result of the execution of the memory operable instructions can be stored back to the array. At590, the result of the memory operable instructions can be returned to device510.

In a number of examples, the device510and the device520at least partially decode the instructions. For example, the device510can partially decode an instruction to generate a memory operable instruction. The device510can provide the partially decoded memory operable instruction to the controller in device520. The decoder can further decode the memory operable instruction and execute the fully decoded memory operable instruction.

In a number of examples, the device510can retain partial control over the memory operable instructions while the memory operable instructions are executed on device520. The device510can retain partial control over the memory operable instructions by partially decoding the memory operable instructions. For example, the device510can partially decode memory operable instructions by translating a virtual address into a physical memory address and device520can retrieve an instruction from the translated physical memory address. The device510can retain partial control over the memory operable instructions by translating the virtual address into the physical memory address.

FIG.6illustrates a schematic diagram of a portion of a memory array630in accordance with a number of embodiments of the present disclosure. The array630includes memory cells603-0,603-1,603-3,603-4,603-5,603-6,603-7,603-8, . . . ,603-J (e.g., referred to generally as memory cells603), coupled to rows of access lines604-0,604-1,604-2,604-3,604-4,604-5,604-6, . . . ,604-R and columns of sense lines605-0,605-1,605-2,605-3,605-4,605-5,605-6,605-7, . . . ,605-S, which may be referred to generally as access lines604and sense lines605. Memory array630is not limited to a particular number of access lines and/or sense lines, and use of the terms “rows” and “columns” does not intend a particular physical structure and/or orientation of the access lines and/or sense lines. Although not pictured, each column of memory cells can be associated with a corresponding pair of complementary sense. The array630can be an array such as array330inFIG.3or array430inFIG.4, for example.

Each column of memory cells can be coupled to sensing circuitry (e.g., sensing circuitry150shown inFIG.1). In this example, the sensing circuitry comprises a number of sense amplifiers606-0,606-1,606-2,606-3,606-4,606-5,606-6,606-7, . . . ,606-U (e.g., referred to generally as sense amplifiers606) coupled to the respective sense lines605-0,605-1,605-2,605-3,605-4,605-5,605-6,605-7, . . . ,605-S. The sense amplifiers606are coupled to input/output (I/O) line634(e.g., a local I/O line) via access devices (e.g., transistors)608-0,608-2,608-3,608-4,608-5,608-6,608-7, . . . ,608-V. In this example, the sensing circuitry also comprises a number of compute components631-0,631-2,631-3,631-4,631-5,631-6,631-7, . . . ,631-X (e.g., referred to generally as compute components631) coupled to the respective sense lines. Column decode lines610-0to610-W are coupled to the gates of transistors608-0to608-V, respectively, and can be selectively activated to transfer data sensed by respective sense amplifiers606-0to606-U and/or stored in respective compute components631-0to631-X to a secondary sense amplifier612and/or to processing resources external to array630(e.g., via I/O line634). In a number of embodiments, the compute components631can be formed on pitch with the memory cells of their corresponding columns and/or with the corresponding sense amplifiers606.

The sensing circuitry (e.g., compute components631and sense amplifiers606) can be controlled by the controller (e.g.,140,340, and440) to execute control flow operations in accordance with a number of embodiments described herein. The example described in association withFIGS.3to5, demonstrate how operations can be performed on data (e.g., elements) stored in an array such as array630.

FIG.7is a schematic diagram illustrating sensing circuitry having selectable logical operation selection logic in accordance with a number of embodiments of the present disclosure.FIG.7shows a number of sense amplifiers706coupled to respective pairs of complementary sense lines705-1and705-2, and a corresponding number of compute components731coupled to the sense amplifiers706via pass gates707-1and707-2. The gates of the pass gates707-1and707-2can be controlled by a logical operation selection logic signal, PASS. For example, an output of the logical operation selection logic713-6can be coupled to the gates of the pass gates707-1and707-2.

According to the embodiment illustrated inFIG.7, the compute components731can comprise respective stages (e.g., shift cells) of a loadable shift register configured to shift data values left and right For example, as illustrated inFIG.7, each compute component731(e.g., stage) of the shift register comprises a pair of right-shift transistors781and786, a pair of left-shift transistors789and790, and a pair of inverters787and788. The signals PHASE 1R, PHASE 2R, PHASE 1L, and PHASE 2L can be applied to respective control lines782,783,791and792to enable/disable feedback on the latches of the corresponding compute components831in association with performing logical operations and/or shifting data in accordance with embodiments described herein. Examples of shifting data (e.g., from a particular compute component731to an adjacent compute component731) is described further below with respect toFIG.9.

The logical operation selection logic713-6includes the swap gates742, as well as logic to control the pass gates707-1and707-2and the swap gates742. The logical operation selection logic713-6includes four logic selection transistors: logic selection transistor762coupled between the gates of the swap transistors742and a TF signal control line, logic selection transistor752coupled between the gates of the pass gates707-1and707-2and a TT signal control line, logic selection transistor754coupled between the gates of the pass gates707-1and707-2and a FT signal control line, and logic selection transistor764coupled between the gates of the swap transistors742and a FF signal control line. Gates of logic selection transistors762and752are coupled to the true sense line through isolation transistor750-1(having a gate coupled to an ISO signal control line). Gates of logic selection transistors764and754are coupled to the complementary sense line through isolation transistor750-2(also having a gate coupled to an ISO signal control line).FIG.9illustrate timing diagrams associated with performing logical operations and shifting operations using the sensing circuitry shown inFIG.7.

FIG.8is a logic table illustrating selectable logic operation results implemented by a sensing circuitry (e.g., sensing circuitry shown inFIG.7) in accordance with a number of embodiments of the present disclosure. The four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the complementary sense lines, can be used to select one of a plurality of logical operations to implement involving the starting data values stored in the sense amplifier706and compute component731. The four control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the complementary sense lines (e.g., on nodes S and S*), controls the pass gates707-1and707-2and swap transistors742, which in turn affects the data value in the compute component731and/or sense amplifier706before/after firing. The capability to selectably control the swap transistors742facilitates implementing logical operations involving inverse data values (e.g., inverse operands and/or inverse result), among others.

Logic Table8-1illustrated inFIG.8shows the starting data value stored in the compute component731shown in column A at844, and the starting data value stored in the sense amplifier706shown in column B at845. The other 3 column headings in Logic Table8-1refer to the state of the pass gates707-1and707-2and the swap transistors742, which can respectively be controlled to be OPEN or CLOSED depending on the state of the four logic selection control signals (e.g., TF, TT, FT, and FF), in conjunction with a particular data value present on the pair of complementary sense lines705-1and705-2when the ISO control signal is asserted. The “NOT OPEN” column corresponds to the pass gates707-1and707-2and the swap transistors742both being in a non-conducting condition, the “OPEN TRUE” column corresponds to the pass gates707-1and707-2being in a conducting condition, and the “OPEN INVERT” column corresponds to the swap transistors742being in a conducting condition. The configuration corresponding to the pass gates707-1and707-2and the swap transistors742both being in a conducting condition is not reflected in Logic Table8-1since this results in the sense lines being shorted together.

Via selective control of the pass gates707-1and707-2and the swap transistors742, each of the three columns of the upper portion of Logic Table8-1can be combined with each of the three columns of the lower portion of Logic Table8-1to provide nine (e.g., 3×3) different result combinations, corresponding to nine different logical operations, as indicated by the various connecting paths shown at875. The nine different selectable logical operations that can be implemented by the sensing circuitry750are summarized in Logic Table8-2.

The columns of Logic Table8-2show a heading880that includes the states of logic selection control signals (e.g., FF, FT, TF, TT). For example, the state of a first logic selection control signal (e.g., FF) is provided in row876, the state of a second logic selection control signal (e.g., FT) is provided in row877, the state of a third logic selection control signal (e.g., TF) is provided in row878, and the state of a fourth logic selection control signal (e.g., TT) is provided in row879. The particular logical operation corresponding to the results is summarized in row847.

FIG.9illustrates a timing diagram associated with performing a logical AND operation and a shifting operation using the sensing circuitry in accordance with a number of embodiments of the present disclosure.FIG.9includes waveforms corresponding to signals EQ, ROW X, ROW Y, SENSE AMP, TF, TT, FT, FF, PHASE 1R, PHASE 2R, PHASE 1L, PHASE 2L, ISO, Pass, Pass*, DIGIT, and DIGIT_. The EQ signal corresponds to an equilibrate signal (not shown) associated with a sense amplifier (e.g., sense amplifier706). The ROW X and ROW Y signals correspond to signals applied to respective access line (e.g., access lines ROW 1 and ROW 2 shown inFIG.6) to access a selected cell (or row of cells). The SENSE AMP signal corresponds to a signal used to enable/disable a sense amplifier (e.g., sense amplifier706). The TF, TT, FT, and FF signals correspond to logic selection control signals such as those shown inFIG.7(e.g., signals coupled to logic selection transistors762,752,754, and764). The PHASE 1R, PHASE 2R, PHASE 1L, and PHASE 2L signals correspond to the control signals (e.g., clock signals) provided to respective control lines782,783,791and792shown inFIG.7. The ISO signal corresponds to the signal coupled to the gates of the isolation transistors750-1and750-2shown inFIG.7. The PASS signal corresponds to the signal coupled to the gates of pass transistors707-1and707-2shown inFIG.7, and the PASS* signal corresponds to the signal coupled to the gates of the swap transistors742. The DIGIT and DIGIT_signals correspond to the signals present on the respective sense lines705-1(e.g., DIGIT (n)) and705-2(e.g., DIGIT (n)_).

The timing diagram shown inFIG.9is associated with performing a logical AND operation on a data value stored in a first memory cell and a data value stored in a second memory cell of an array. The memory cells can correspond to a particular column of an array (e.g., a column comprising a complementary pair of sense lines) and can be coupled to respective access lines (e.g., ROW X and ROW Y). In describing the logical AND operation shown inFIG.9, reference will be made to the sensing circuitry described inFIG.7. For example, the logical operation described inFIG.9can include storing the data value of the ROW X memory cell (e.g., the “ROW X” data value) in the latch of the corresponding compute component731(e.g., the “A” data value), which can be referred to as the accumulator731, storing the data value of the ROW Y memory cell (e.g., the “ROW Y” data value) in the latch of the corresponding sense amplifier706(e.g., the “B” data value), and performing a selected logical operation (e.g., a logical AND operation in this example) on the ROW X data value and the ROW Y data value, with the result of the selected logical operation being stored in the latch of the compute component731.

As shown inFIG.9, at time T1, equilibration of the sense amplifier706is disabled (e.g., EQ goes low). At time T2, ROW X goes high to access (e.g., select) the ROW X memory cell. At time T3, the sense amplifier706is enabled (e.g., SENSE AMP goes high), which drives the complementary sense lines705-1and705-2to the appropriate rail voltages (e.g., VDDand GND) responsive to the ROW X data value (e.g., as shown by the DIGIT and DIGIT_signals), and the ROW X data value is latched in the sense amplifier706. At time T4, the PHASE 2R and PHASE 2L signals go low, which disables feedback on the latch of the compute component731(e.g., by turning off transistors786and790, respectively) such that the value stored in the compute component may be overwritten during the logical operation. Also, at time T4, ISO goes low, which disables isolation transistors750-1and750-2. At time T5, TT and FT are enabled (e.g., go high), which results in PASS going high (e.g., since either transistor752or754will conduct depending on which of node ST2 or node SF2 was high when ISO was disabled at time T4(recall that when ISO is disabled, the voltages of the nodes ST2 and SF2 reside dynamically on the gates of the respective enable transistors752and754). PASS going high enables the pass transistors707-1and707-2such that the DIGIT and DIGIT_signals, which correspond to the ROW X data value, are provided to the respective compute component nodes ST2 and SF2. At time T6, TT and FT are disabled, which results in PASS going low, which disables the pass transistors707-1and707-2. It is noted that PASS* remains low between time T5and T6since the TF and FF signals remain low. At time T7, ROW X is disabled, and PHASE 2R, PHASE 2L, and ISO are enabled. Enabling PHASE 2R and PHASE 2L at time T7enables feedback on the latch of the compute component731such that the ROW X data value is latched therein. Enabling ISO at time T7again couples nodes ST2 and SF2 to the gates of the enable transistors752,754,762, and764. At time T8, equilibration is enabled (e.g., EQ goes high such that DIGIT and DIGIT_are driven to an equilibrate voltage such as VDD/2) and the sense amplifier706is disabled (e.g., SENSE AMP goes low).

With the ROW X data value latched in the compute component731, equilibration is disabled (e.g., EQ goes low at time T9). At time T10, ROW Y goes high to access (e.g., select) the ROW Y memory cell. At time T11, the sense amplifier706is enabled (e.g., SENSE AMP goes high), which drives the complementary sense lines705-1and705-2to the appropriate rail voltages (e.g., VDDand GND) responsive to the ROW Y data value (e.g., as shown by the DIGIT and DIGIT_signals), and the ROW Y data value is latched in the sense amplifier706. At time T12, the PHASE 2R and PHASE 2L signals go low, which disables feedback on the latch of the compute component731(e.g., by turning off transistors786and790, respectively) such that the value stored in the compute component may be overwritten during the logical operation. Also, at time T12, ISO goes low, which disables isolation transistors750-1and750-2. Since the desired logical operation in this example is an AND operation, at time T13, TT is enabled while TF, FT and FF remain disabled (as shown in TABLE 8-2, FF=0, FT=0, TF=0, and TT=1 corresponds to a logical AND operation). Whether enabling TT results in PASS going high depends on the value stored in the compute component731when ISO is disabled at time T12. For example, enable transistor752will conduct if node ST2 was high when ISO is disabled, and enable transistor will not conduct if node ST2 was low when ISO was disabled at time T12.

In this example, if PASS goes high at time T13, the pass transistors707-1and707-2are enabled such that the DIGIT and DIGIT_signals, which correspond to the ROW Y data value, are provided to the respective compute component nodes ST2 and SF2. As such, the value stored in the compute component731(e.g., the “ROW X” data value) may be flipped, depending on the value of DIGIT and DIGIT_(e.g., the ‘ROW Y” data value). In this example, if PASS stays low at time T13, the pass transistors707-1and707-2are not enabled such that the DIGIT and DIGIT_signals, which correspond to the ROW Y data value, remain isolated from the nodes ST2 and SF2 of the compute component731. As such, the data value in the compute component (e.g., the ROW X data value) would remain the same.

At time T14, TT is disabled, which results in PASS going (or remaining) low, such that the pass transistors707-1and707-2are disabled. It is noted that PASS* remains low between time T13and T14since the TF and FF signals remain low. At time T15, ROW Y is disabled, and PHASE 2R, PHASE 2L, and ISO are enabled. Enabling PHASE 2R and PHASE 2L at time T15enables feedback on the latch of the compute component731such that the result of the AND operation (e.g., “A” AND “B”) is latched therein. Enabling ISO at time T15again couples nodes ST2 and SF2 to the gates of the enable transistors752,754,762, and764. At time T16, equilibration is enabled (e.g., EQ goes high such that DIGIT and DIGIT_are driven to an equilibrate voltage) and the sense amplifier706is disabled (e.g., SENSE AMP goes low).

The result of the AND operation, which is initially stored in the compute component731in this example, can be transferred back to the memory array (e.g., to a memory cell coupled to ROW X, ROW Y, and/or a different row via the complementary sense lines) and/or to an external location (e.g., an external processing component) via I/O lines.

FIG.9also includes (e.g., at901) signaling associated with shifting data (e.g., from a compute component731to an adjacent compute component731). The example shown inFIG.9illustrates two left shifts such that a data value stored in a compute component corresponding to column “N” is shifted left to a compute component corresponding to column “N-2”. As shown at time T16, PHASE 2R and PHASE 2L are disabled, which disables feedback on the compute component latches, as described above. To perform a first left shift, PHASE 1L is enabled at time T17and disabled at time Tis. Enabling PHASE 1L causes transistor789to conduct, which causes the data value at node SF1 to move left to node SF2 of a left-adjacent compute component731. PHASE 2L is subsequently enabled at time T19and disabled at time T20. Enabling PHASE 2L causes transistor790to conduct, which causes the data value from node ST1 to move left to node ST2 completing a left shift.

The above sequence (e.g., enabling/disabling PHASE 1L and subsequently enabling/disabling PHASE 2L) can be repeated to achieve a desired number of left shifts. For instance, in this example, a second left shift is performed by enabling PHASE 1L at time T21and disabling PHASE 1L at time T22. PHASE 2L is subsequently enabled at time T23to complete the second left shift. Subsequent to the second left shift, PHASE 2L remains enabled and PHASE 2R is enabled (e.g., at time T24) such that feedback is enabled to latch the data values in the compute component latches.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.