Patent ID: 12217802

DETAILED DESCRIPTION

In the following, the contents of the present disclosure will be described in detail with reference to the drawings to the extent that those of ordinary skill in the pertinent technical field may readily implement the teachings described herein.

A non-volatile memory device, a storage device including the same, and an operating method thereof, according to an embodiment of the present disclosure, may selectively use information data according to a user's intended purpose of use, such as to optimize performance or to optimize reliability.

FIG.1illustrates a storage device10according to an embodiment of the present disclosure. Referring toFIG.1, a storage device10may include at least one non-volatile memory device NVM(s)100and a controller CNTL200.

The at least one non-volatile memory device100may be implemented to store data. The non-volatile memory device100may be a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase-change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), or the like. Also, the non-volatile memory device100may be implemented to have a three-dimensional array structure. The present disclosure may be applicable not only to a flash memory device in which a charge storage layer is formed of a conductive floating gate, but also to a charge trap flash (CTF) in which a charge storage layer is formed of an insulating film. Hereinafter, for convenience of description, the non-volatile memory device100may be referred to as a vertical NAND flash memory device (VNAND), without limitation thereto.

The non-volatile memory device100may include a meta area111storing meta data, and a user area112storing user data. Each of the meta area111and the user area122may be implemented to include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of pages. Each of the plurality of pages may include a plurality of memory cells. Each of the plurality of memory cells may store at least one bit. In an embodiment, the memory cell of the meta area111may be implemented as a single level cell (SLC). In an embodiment, the memory cell of the user area112may be implemented as one of a multi-level cell (MLC), a triple level cell (TLC), a quad level cell (QLC), a penta-level cell (PLC), or a hexa-level cell (HLC). It should be understood that a memory cell of the present disclosure is not limited to SLC, MLC, TLC, QLC, PLC, and HLC.

The meta area111may store initial data. In this case, the initial data may include information indicating a product specification of the non-volatile memory device100. For example, the initial data may include information related to operation options, functions, characteristics, and operating modes of the non-volatile memory device100. In an embodiment, the initial data may be stored in a page, a memory block, or a mat (MAT).

The initial data may include first initial data IDR_FST and second initial data IDR_SCD (e.g., IDR_SCD1, . . . IDR_SCDk, where k is an integer of 2 or more).

The first initial data IDR_FST may include first initial data that may be provided in common, regardless of a user. The first initial data may include information indicating a performance-related parameter of an operation of the non-volatile memory device100.

The second initial data (e.g., IDR_SCD1, . . . IDR_SCDk) may include second initial data selectable by a user. The second initial data may include information indicating reliability-related parameters of an operation of the non-volatile memory device100.

An initialization register101may store the first initial data IDR_FST. All or part of the initialization register101may store the second initial data IDR_SCD. In this case, the second initial data IDR_SCD may be second initial data selected in an initialization operation.

A control logic150may receive a command and an address from the controller CNTL200, and may be implemented to perform an operation (a program operation, a reading operation, an erase operation, or the like) corresponding to the received command in memory cells corresponding to the address. In this case, the operation may be performed with reference to data stored in the registers101and102.

The controller CNTL200may be connected to the at least one non-volatile memory device100through a plurality of control pins transmitting control signals (e.g., a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and the like). Also, the controller CNTL200may be implemented to use the control signals (CLE, ALE, CE(s), WE, RE, or the like) to control the non-volatile memory device100. For example, the non-volatile memory device100may latch a command (CMD) or an address (ADD) at an edge of the WE signal according to the CLE signal and the ALE signal, to perform program operation/read operation/erase operation. For example, during a read operation, the chip enable signal CE is activated, CLE is activated during a command transmission interval, ALE is activated during an address transmission interval, and RE indicates that data is transmitted through the data signal line DQ. It can be toggled in the transmission section. The data strobe signal DQS may be toggled with a frequency corresponding to the data input/output speed. The read data may be sequentially transmitted in synchronization with the data strobe signal DQS.

In addition, the controller200may include at least one processor (e.g., a central processing unit (CPU))210, a buffer memory220, and an error correction circuit230.

The processor210may be implemented to control an overall operation of the storage device10. The processor210may perform various management operations such as a cache/buffer management, a firmware management, a garbage collection management, a wear leveling management, a data duplication removal management, a read refresh/reclaim management, a bad block management, a multi-stream management, managements of data of a host and mapping of a non-volatile memory, a quality of service (QoS) management, a system resource allocation management, a non-volatile memory queue management, a read level management, an erase/program management, a hot/cold data management, a power loss protection management, a dynamic thermal management, an initialization management, a redundant array of inexpensive disk (RAID) management, or the like.

In particular, the processor210may be implemented to drive an initialization unit211. In an embodiment, the initialization unit211may be implemented in firmware/software.

The initialization unit211may control the initialization operation of the non-volatile memory device100. In an embodiment, the initialization unit211may generate an initial data read command IDR CMD for the initialization operation, when power is turned on. Addresses indicating the first initial data IDR_FST and the second initial data IDR_SCD may be transmitted, together with the initial data read command IDR CMD. For example, a first address for reading the first initial data IDR_FST and a second address for reading the second initial data IDR_SCD may be transmitted.

The buffer memory220may be implemented as a volatile memory (e.g., a static random access memory (SRAM), a dynamic RAM (DRAM), a synchronous RAM (SDRAM), and the like) or a non-volatile memory (e.g., a flash memory, a phase-change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and the like).

The ECC circuit230may be implemented to generate an error correction code during a program operation, and use the error correction code during a reading operation to recover data. For example, the ECC circuit230may generate an error correction code (ECC) for correcting a failure bit or an error bit of data received from the non-volatile memory device100. The ECC circuit230may perform error correction encoding of data provided to the non-volatile memory device100, to form data to which a parity bit is added. The parity bit may be stored in the non-volatile memory device100.

In addition, the ECC circuit230may perform error correction decoding on the data output from the non-volatile memory device100. The ECC circuit230may correct an error using the parity bit. The ECC circuit230may correct an error using a coded modulation such as a low density parity check (LDPC) code, a BCH code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a block coded modulation (BCM), or the like. When error correction is impossible or impractical in the error correction circuit230, a read retry operation may be performed.

In general, it is desirable to change a setting condition of a non-volatile memory device in order to match operation and reliability characteristics according to a request of a client. In a general storage device, after reading initial data, an initialization condition required for operation of a non-volatile memory device may be set by adding an e-fuse by a user, if desired. The additional setting method may require additional time for initial setting. In addition, since the additional setting may be performed on a wafer level, management of the non-volatile memory device may be complicated.

In a non-volatile memory device100according to an embodiment of the present disclosure, by selecting a second initial data IDR_SCD according to a user's purpose or an application usage in an initialization operation, additional time may not be required for additional setting, and the additional setting may be also made on a SET level.

A storage device10according to an embodiment of the present disclosure may provide a customized non-volatile memory device100by enabling a combination of initial data (e.g., IDR_FST and IDR_SCD) to be selected during an initialization operation.

FIG.2illustrates the non-volatile memory device100illustrated inFIG.1. Referring toFIG.2, the non-volatile memory device100may include an initialization register101, a memory cell array110, a row decoder120, a page buffer circuit130, an input/output buffer circuit140, control logic150, a voltage generator160, and a cell counter170.

The initialization register101may store first initial data IDR_FST in an initialization operation. In addition, all or part of the initialization register101may store second initial data IDR_SCD in the initialization operation.

The memory cell array110may be connected to the row decoder120through word-lines WLs, or select lines SSL and GSL. The memory cell array110may be connected to the page buffer circuit130through bit-lines BLs. The memory cell array110may include a plurality of cell strings. Each channel of the cell strings may be formed in a vertical direction or a horizontal direction. Each of the cell strings may include a plurality of memory cells. In this case, the plurality of memory cells may be programmed, erased, or read by a voltage provided to the bit-lines BLs or the word-lines WLs. In general, a program operation may be performed on a page basis, and an erase operation may be performed on a block basis. Details of the memory cells will be described in U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 9,536,970. In an embodiment, the memory cell array110may include a2D memory cell array, and the2D memory cell array may include a plurality of NAND strings arranged in row and column directions.

The row decoder120may be implemented to select any one of memory blocks BLK1to BLKz (where, z is an integer equal to or greater than 2) of the memory cell array110in response to an address ADD. The row decoder120may select any one of word-lines of a selected memory block in response to the address ADD. The row decoder120may transfer a word-line voltage VWL corresponding to an operating mode to the word-lines of the selected memory block. During a program operation, the row decoder120may apply a program voltage and a verify voltage to a selected word-line, and may apply a pass voltage to an unselected word-line. During a reading operation, the row decoder120may apply a read voltage to a selected word-line, and may apply a read pass voltage to an unselected word-line.

The page buffer circuit130may be implemented to operate as a write driver or a sense amplifier according to an operating mode. For example, during a program operation, the page buffer circuit130may apply a bit-line voltage corresponding to data to be programmed to the selected bit-line. During a read operation or a verify read operation, the page buffer circuit130may sense data stored in a memory cell through the bit-line BL. A plurality of page buffers PB1to PBn (where n is an integer equal to or greater than 2) included in the page buffer circuit130may be connected to at least one bit-line, respectively.

Each of the plurality of page buffers PB1to PBn may be implemented to perform sensing and latching for an OVS sensing operation. For example, each of the plurality of page buffers PB1to PBn may perform a plurality of sensing operations to identify any one state stored in the selected memory cells under control of the control logic150. In addition, after each of the plurality of page buffers PB1to PBn stores data sensed by the plurality of sensing operations, any one data may be selected under the control of the control logic150. For example, each of the plurality of page buffers PB1to PBn may perform the plurality of sensing operations to identify the any one state. In addition, each of the plurality of page buffers PB1to PBn may select or output optimal data, among a plurality of pieces of data, sensed according to the control of the control logic150.

The input/output buffer circuit140may provide, data externally provided, to the page buffer circuit130. The input/output buffer circuit140may provide, a command CMD externally provided, to the control logic150. The input/output buffer circuit140may provide, an address ADD externally provided, to the control logic150or the row decoder120. In addition, the input/output buffer circuit140may externally output data sensed and latched by the page buffer circuit130.

The control logic150may be implemented to control the row decoder120and the page buffer circuit130in response to a command CMD transmitted from an external source (e.g., the controller200, seeFIG.1).

In addition, the control logic150may perform a first background operation151or a second background operation152according to control of a controller200, and may be implemented to output health information according to the first background operation151and the second background operation152to the controller200.

The voltage generator160may be implemented to generate various types of word-line voltages to be respectively applied to word-lines under control of the control logic150and a well voltage to be supplied to a bulk (e.g., well region) in which memory cells are formed. The word-line voltages respectively applied to the word-lines may include a program voltage, a pass voltage, a read voltage, read pass voltages, or the like.

The cell counter170may be implemented to count the number of memory cells corresponding to a specific threshold voltage range from data sensed by the page buffer circuit130. For example, the cell counter170may process data respectively sensed in the plurality of page buffers PB1to PBn, to count the number of memory cells having a threshold voltage in a specific threshold voltage range.

FIG.3illustrates a circuit diagram of a memory block (BLKi, where i is an integer equal to or greater than 2) according to an embodiment of the present disclosure. A plurality of memory NAND strings included in the memory block BLKi may be formed in a direction, perpendicular to a substrate.

Referring toFIG.3, the memory block BLKi may include a plurality of memory NAND strings NS11to NS33connected between bit-lines BL1, BL2, and BL3and a common source line CSL. Each of the plurality of memory NAND strings NS11to NS33may include a string select transistor SST, a plurality of memory cells MC1, MC2, . . . , and MC8, and a ground select transistor GST. InFIG.3, each of the plurality of memory NAND strings NS11to NS33is illustrated as including eight memory cells MC1, MC2, . . . , and MC8, but is not limited thereto.

The string select transistor SST may be connected to string select lines SSL1, SSL2, and SSL3corresponding thereto. The plurality of memory cells MC1, MC2, . . . , and MC8may be respectively connected to gate lines GTL1, GTL2, . . . , and GTL8corresponding thereto. The gate lines GTL1, GTL2, . . . , and GTL8may correspond to word-lines, and a portion of the gate lines GTL1, GTL2, . . . , and GTL8may correspond to dummy word-lines. The ground select transistor GST may be connected to ground select lines GSL1, GSL2, and GSL3corresponding thereto. The string select transistor SST may be connected to the bit-lines BL1, BL2, and BL3corresponding thereto, and the ground select transistor GST may be connected to the common source line CSL.

Word-lines (e.g., WL1) having the same height may be connected in common, and the ground select lines GSL1, GSL2, and GSL3and the string select lines SSL1, SSL2, and SSL3may be separated from each other.FIG.3illustrates that the memory block BLKi is connected to eight gate lines GTL1, GTL2, . . . , and GTL8and three bit-lines BL1, BL2, and BL3, but is not necessarily limited thereto.

FIG.4illustrates a controller200according to an embodiment of the present disclosure. Referring toFIG.4, a controller200may include a host interface201, a memory interface202, at least one CPU210, a buffer memory220, an error correction circuit230, a flash translation layer manager240, a packet manager250, and an encryption device260.

The host interface201may be implemented to transmit and receive a packet to and from a host. A packet transmitted from the host to the host interface201may include a command or data to be written to a non-volatile memory100. A packet transmitted from the host interface201to the host may include a response to a command or data read from the non-volatile memory100. The memory interface202may transmit data to be written in the non-volatile memory100to the non-volatile memory100or receive data read from the non-volatile memory100. This memory interface202may be implemented to comply with a standard protocol such as JDEC Toggle or ONFI.

The flash translation layer manager240may perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation may be an operation of converting a logical address, received from the host, into a physical address, used to actually store data in the non-volatile memory100. The wear-leveling may be technology for using blocks in the non-volatile memory100uniformly to prevent excessive deterioration of a specific block therein, and may be implemented, for example, by a firmware technique balancing erase counts of physical blocks. The garbage collection may be technology for copying valid data of an existing block to a new block and then erasing the existing block, to secure capacity, usable in the non-volatile memory100.

The packet manager250may generate a packet according to a protocol of an interface negotiated with the host, or may parse various pieces of information from a packet received from the host. Also, the buffer memory220may temporarily store data to be written in the non-volatile memory100or data read from the non-volatile memory100. In an embodiment, the buffer memory220may be a component provided in the controller200. In another embodiment, the buffer memory220may be disposed outside the controller200.

The encryption device260may perform at least one of an encryption operation and a decryption operation on data input to a storage controller210, using a symmetric-key algorithm. The encryption device260may perform encryption and decryption of data using an advanced encryption standard (AES) algorithm. The encryption device260may include an encryption module and a decryption module.

The first initial data IDR_FST may include a core condition for performing an operation of the non-volatile memory device100, and the second initial data IDR_SCD may include an additional condition corresponding to the core condition.

FIGS.5A and5Billustrate meta blocks storing initial data according to an embodiment of the present disclosure.

Referring toFIG.5A, four operation sets A, B, C, and D are illustrated for a non-volatile memory device100. First and second operation sets A and B may be stored in a first meta block111-1, and third and fourth operation sets C and D may be stored in a second meta block111-2. However, it should be understood that storage relation between an operation set and a meta block of the present disclosure is not limited thereto.

The first meta block111-1may include a page111-1-1storing a core condition of the first operation set A and a page111-1-3storing an additional condition of the first operation set A. In addition, the first meta block111-1may include a page111-1-2storing a core condition of the second operation set B and a page111-1-4storing an additional condition of the second operation set B.

The second meta block111-2may include a page111-2-1storing a core condition of the third operation set C and a page111-2-3storing an additional condition of the third operation set C. In addition, the second meta block111-2may include a page111-2-2storing a core condition of the fourth operation set D and a page111-2-4storing an additional condition of the fourth operation set D.

Referring toFIG.5B, two operation sets A and B are illustrated for a non-volatile memory device100. First and second operation sets A and B may be equally stored in meta blocks111-1aand111-2a. However, it should be understood that storage relation between an operation set and a meta block of the present disclosure is not limited thereto.

The first meta block111-1amay include a page111-1-1storing a core condition of the first operation set A, a page111-1-3storing an additional condition of the first operation set A, a page111-1-2storing a core condition of the second operation set B and a page111-1-4storing an additional condition of the second operation set B.

The meta block111-2amay include a page111-1-1astoring a core condition of the first operation set A, a page111-1-3astoring an additional condition of the first operation set A, a page111-1-2astoring a core condition of the second operation set B, and a page111-1-4astoring an additional condition of the second operation set B.

The core condition and the additional condition illustrated inFIGS.5A and5Bmay be stored in pages, different from each other, respectively, but the present disclosure is not limited thereto. In the present disclosure, a core condition and an additional condition corresponding to the core condition may be stored in the same page.

Although the core condition/additional condition may be stored in a respective page inFIGS.5A and5B, the present disclosure is not necessarily limited thereto. It should be understood that the core condition/additional condition of the present disclosure are stored in types of regions, different from each other, accessible by addresses, different from each other.

FIGS.6A and6Billustrate embodiments of a scanning method for initial data in an initialization operation.

Referring toFIG.6A, in an initialization operation, an entire area of a first initial data area111amay be scanned, and a partial area of a second initial data area111bmay be scanned. In this case, the second initial data area111bmay be a region selected by a user.

In an embodiment, a non-volatile memory device100may receive read commands and addresses, different from each other, for reading the first initial data area111aand the second initial data area111b.

As illustrated inFIG.6B, an entire area of a second initial data area111bmay be scanned in an initialization operation. In this case, a non-volatile memory device may select a partial area among the entire scanned region as second initial data IDR_SCD.

In general, an initialization operation may include an initial read operation of reading initial data stored in a meta area, a dump-down operation of verifying validity of initial data stored in a page buffer circuit according to the initial read operation and storing the initial data in the page buffer circuit, and a subsequent process of setting conditions for operation of a non-volatile memory device in a register, based on the initial data stored in the page buffer circuit. For example, the subsequent processes may include setting levels of operating voltages, “WORscan” for excluding a buffer of a bad column from a pass/fail operation, and the like. In an embodiment, the read level may be adjusted in an initial read operation differently from a general read operation. Details related to a read level change in the initial read operation may be found in US 2021-0097010, which is incorporated by reference in this application.

It should be understood that a scanning method of initial data in an initialization operation is not limited toFIGS.6A and6B.

FIG.7illustrates initial data according to an embodiment of the present disclosure. Referring toFIG.7, first initial data IDR_FST may include performance parameters related to a non-volatile memory device100, and second initial data IDR_SCD may include reliability parameters related to the non-volatile memory device100.

In an embodiment, the performance parameters may include a read time tR, a program time tPROG, an erase time tERS, and the like. In an embodiment, the reliability parameters may include a retention-related parameter, an endurance-related parameter, a width and level of a step pulse of an incremental step pulse program (ISPP), a recovery voltage, a verification method, the number of verification target states, and the like. It should be understood that the performance parameters and the reliability parameters of the present disclosure are not limited thereto.

FIG.8illustrates an initialization operation of storage according to an embodiment of the present disclosure. Referring toFIGS.1to8, an initialization operation of a storage device10according to an embodiment of the present disclosure may be performed as follows.

As power is supplied, a power-up operation may be performed (S110). In this case, an application usage may be selected in a controller200(S120). An initialization command IDR CMD and an address according to the selected application usage may be transmitted to a non-volatile memory device100. The non-volatile memory device100may perform a read operation on initial data according to the application usage (S130). In this case, the initial data may include first initial data IDR_FST and second initial data IDR_SCD. The first initial data IDR_FST and the second initial data IDR_SCD may be stored in registers101and102, corresponding thereto. Therefore, the initial data of the non-volatile memory device100may be set (S140).

FIG.9illustrates a method of operating a storage device according to an embodiment of the present disclosure. Referring toFIGS.1to9, an operation method of a storage device10may proceed as follows.

A host may transmit a power-up request to a controller CNTL of the storage device10(S10). In this case, the power-up request may be directly performed according to power supply or may be performed according to a separate command from the host. The controller CNTL may select an application usage of a non-volatile memory device NVM according to the power-up request (S11). Thereafter, the controller CNTL may transmit a read request (i.e., an initial read request) for initial data IDR according to the selected application usage (S13). The initial read request may include a read command and an address corresponding thereto. In this case, the address may include a first address for reading first initial data IDR_FST corresponding to the selected application usage, and a second address for reading second initial data IDR_SCD corresponding to the selected application usage. In an embodiment, the initial read request may be arbitrarily transmitted to the non-volatile memory device NVM according to a power-up operation or an operation for optimizing performance or reliability.

The non-volatile memory device NVM may perform an initial read operation in response to the read request for initial data (S14). In this case, the initial read operation may include a first read operation of reading the first initial data and a second read operation of reading the second initial data. In an embodiment, the first read operation and the second read operation may be performed in response to one initial read command. In an embodiment, the first read operation and the second read operation may be performed in response to initial read commands, different from each other. In an embodiment, the first initial data and the second initial data may be stored in regions accessed by addresses, different from each other.

The first initial data IDR_FST and the second initial data IDR_SCD may be read from a meta block, based on the initial read operation. Thereafter, the non-volatile memory device NVM may store the initial data IDR_FST and IDR_SCD in the registers101and102(refer toFIG.1).

Thereafter, the host may transmit an operation request (e.g., a read/write/delete request) to the storage device10(S16). The controller CNTL may transmit a read/program/erase command, corresponding to the operation request, to the non-volatile memory device NVM (S17). The non-volatile memory device NVM may use the initial data stored in the registers101and102for initialization to perform an operation corresponding to the received command by (S18).

A storage device according to an embodiment of the present disclosure may include an artificial processor dedicated to initialization setting.

FIG.10illustrates a storage device20according to another embodiment of the present disclosure. Referring toFIG.10, a controller200aof a storage device20may include a processor215for artificial intelligence, controlling an initialization operation, as compared to that illustrated inFIG.1. The processor215may be implemented to manage the initialization operation described inFIGS.1to9. A non-volatile memory device100amay set initial data (e.g., IDR_FST and IDR_SCD) according to control of the processor215.

A non-volatile memory device according to an embodiment of the present disclosure may be implemented in a chip to chip (C2C) structure.

FIG.11illustrates a non-volatile memory device1000implemented in a C2C structure according to an embodiment of the present disclosure. In this case, a C2C structure may refer that an upper chip including a cell region CELL is prepared on a first wafer, a lower chip including a peripheral circuit region PERI is prepared on a second wafer, different from the first wafer, and the upper chip and the lower chip are connected to each other by a bonding method. For example, the bonding method may be a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. In an embodiment, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu—Cu bonding method. In another embodiment, the bonding metal may be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit region PERI and the cell region CELL of the non-volatile memory device1000may include an external pad bonding area PA, a word-line bonding area WLBA, and a bit-line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate1210, an interlayer insulating layer1215, a plurality of circuit elements1220a,1220b, and1220cformed on the first substrate1210, first metal layers1230a,1230b, and1230crespectively connected to the plurality of circuit elements1220a,1220b, and1220c, and second metal layers1240a,1240b, and1240crespectively formed on the first metal layers1230a,1230b, and1230c. In an embodiment, the first metal layers1230a,1230b, and1230cmay be formed of tungsten having relatively high resistivity. In an embodiment, the second metal layers1240a,1240b, and1240cmay be formed of copper having a relatively low resistivity.

As illustrated inFIG.11, the first metal layers1230a,1230b, and1230cand the second metal layers1240a,1240b, and1240care illustrated, but the present disclosure will not be limited thereto. At least one metal layer may be further formed on the second metal layers1240a,1240b, and1240c. At least a portion of the one or more metal layers formed on the second metal layers1240a,1240b, and1240cmay be formed of aluminum having a resistivity, different from that of copper forming the second metal layers1240a,1240b, and1240c.

In an embodiment, the interlayer insulating layer1215may be disposed on the first substrate1210to cover the plurality of circuit elements1220a,1220b, and1220c, the first metal layers1230a,1230b, and1230c, and the second metal layers1240a,1240b, and1240c. In an embodiment, the interlayer insulating layer1215may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals1271band1272bmay be formed on the second metal layer1240bof the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metals1271band1272bof the peripheral circuit region PERI may be electrically connected to upper bonding metals1371band1372bof the cell region CELL by a bonding method. In an embodiment, the lower bonding metals1271band1272band the upper bonding metals1371band1372bmay be formed of aluminum, copper, tungsten, or the like. Additionally, the upper bonding metals1371band1372bof the cell region CELL may be referred to as first metal pads, and the lower bonding metals1271band1272bmay be referred to as second metal pads.

The cell region CELL may include at least one memory block. In an embodiment, the cell region CELL may include a second substrate1310and a common source line1320. On the second substrate1310, a plurality of word-lines1331to1338(i.e.,1330) may be stacked in a direction (a Z-axis direction), perpendicular to an upper surface of the second substrate1310. In an embodiment, string select lines and ground select line may be respectively disposed on and below the word-lines1330. In an embodiment, the plurality of word-lines1330may be disposed between the string select lines and the ground select line.

In the bit-line bonding area BLBA, a channel structure CH may extend in a direction (the Z-axis direction), perpendicular to the upper surface of the second substrate1310, to pass through the word-lines1330, the string select lines, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer1350cand a second metal layer1360c. For example, the first metal layer1350cmay be a bit-line contact, and the second metal layer1360cmay be a bit-line. In an embodiment, the bit-line1360cmay extend in a first direction (a Y-axis direction), parallel to the upper surface of the second substrate1310.

As illustrated inFIG.11, a region in which the channel structure CH, the bit-line1360c, and the like are arranged may be defined as the bit-line bonding area BLBA. In an embodiment, the bit-line1360cmay be electrically connected to the circuit elements1220cproviding a page buffer1393in the peripheral circuit region PERI, in the bit-line bonding area BLBA. For example, the bit-line1360cmay be connected to upper bonding metals1371cand1372cin the peripheral circuit region PERI. In this case, the upper bonding metals1371cand1372cmay be connected to lower bonding metals1271cand1272cconnected to the circuit elements1220cof the page buffer1393. In the word-line bonding area WLBA, the word-lines1330may extend in a second direction (the X-axis direction), parallel to the upper surface of the second substrate1310. In an embodiment, the word-line bonding area WLBA may be connected to a plurality of cell contact plugs1341to1347(i.e.,1340). For example, the word-lines1330and the cell contact plugs1340may be connected to each other by pads provided with at least a portion of the word-lines1330extending in the second direction and having different lengths. In an embodiment, the first metal layer1350band the second metal layer1360bmay be sequentially connected to the cell contact plugs1340connected to the word-lines1330. In an embodiment, the cell contact plugs1340may be connected to the peripheral circuit region PERI by the upper bonding metals1371band1372bof the cell region CELL and the lower bonding metals1271band1272bof the peripheral circuit region PERI in the word-line bonding area WLBA.

In an embodiment, the cell contact plugs1340may be electrically connected to the circuit elements1220bproviding the row decoder1394in the peripheral circuit region PERI. In an embodiment, operating voltages of the circuit elements1220bproviding the row decoder1394may be different from operating voltages of the circuit elements1220cproviding a page buffer1393. For example, the operating voltages of the circuit elements1220cproviding the page buffer1393may be greater than the operating voltages of the circuit elements1220bproviding the row decoder1394.

A common source line contact plug1380may be disposed in the external pad bonding area PA. In an embodiment, the common source line contact plug1380may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like. The common source line contact plug1380may be electrically connected to the common source line1320. A first metal layer1350aand a second metal layer1360amay be sequentially stacked on the common source line contact plug1380. For example, an area in which the common source line contact plug1380, the first metal layer1350a, and the second metal layer1360aare arranged may be defined as the external pad bonding area PA. The second metal layer1360amay be electrically connected to an upper metal via1371a. The upper metal via1371amay be electrically connected to an upper metal pattern1372a.

Input/output pads1205and1305may be arranged in the external pad bonding area PA. Referring toFIG.11, a lower insulating layer1201covering a lower surface of the first substrate1210may be formed below the first substrate1210. Also, a first input/output pad1205may be formed on the lower insulating layer1201. In an embodiment, the first input/output pad1205may be connected to at least one of a plurality of circuit elements1220a,1220b, and1220c, arranged in the peripheral circuit region PERI, by a first input/output contact plug1203. In an embodiment, the first input/output pad1205may be separated from the first substrate1210by the lower insulating layer1201. In addition, since a lateral insulating layer may be disposed between the first input/output contact plug1203and the first substrate1210, the first input/output contact plug1203and the first substrate1210may be electrically separated.

Referring toFIG.11, an upper insulating layer1301may be formed on the second substrate1310to cover the upper surface of the second substrate1310. Also, a second input/output pad1305may be disposed on the upper insulating layer1301. In an embodiment, the second input/output pad1305may be connected to at least one of a plurality of circuit elements1220a,1220b, and1220c, arranged in the peripheral circuit region PERI, by a second input/output contact plug1303, a lower metal pattern1272a, and a lower metal via1271a.

In an embodiment, the second substrate1310, the common source line1320, and the like may not be disposed in an area where the second input/output contact plug1303is disposed. Also, the second input/output pad1305may not overlap the word-lines1380in a third direction (the Z-axis direction). Referring toFIG.11, the second input/output contact plug1303may be separated from the second substrate1310in a direction, parallel to the upper surface of the second substrate1310. Also, the second input/output contact plug1303may pass through an interlayer insulating layer1315of the cell region CELL, and may be connected to the second input/output pad1305. In an embodiment, the second input/output pad1305may be electrically connected to the circuit element1220a.

In an embodiment, the first input/output pad1205and the second input/output pad1305may be selectively formed. For example, the non-volatile memory device1000may include the first input/output pad1205disposed on the first substrate1201, or alternatively it may include the second input/output pad1305disposed on the second substrate1301. In another embodiment, the non-volatile memory device1000may include both of the first input/output pad1205and the second input/output pad1305.

A metal pattern of an uppermost metal layer in each of the external pad bonding area PA and the bit-line bonding area BLBA included in each of the cell region CELL and the peripheral circuit region PERI may be present as a dummy pattern, or the uppermost metal layer may be empty.

A non-volatile memory device according to an embodiment of the present disclosure may selectively use information data suitable for a user's intended application or area of use. In an embodiment, one or more pieces of information data may be written in a predetermined Page/Block/MAT of the non-volatile memory device. After selecting such information data according to a situation, the selected information data may be read, and the read information data may be used to drive the non-volatile memory device.

In an embodiment, in setting an initialization condition for operating a non-volatile memory device, a condition suitable for a characteristic (e.g., performance or reliability) desired by a user may be used selectively by information data without setting additional conditions or replacing the non-volatile memory device. In addition, a time period required to change the suitable conditions may be eliminated.

In an embodiment, in order to selectively use the information data, various types of initial data may be stored on-chip, and the user may select a condition suitable for an intended application or area of use from the stored initial data.

A non-volatile memory device, a storage device including the same, and an operating method thereof, according to an embodiment of the present disclosure, may readily optimize operating conditions of a memory according to an intended application or area of use by selecting additional operation-related information according to a user selection and an application usage.

While illustrative embodiments have been shown and described, it will be apparent to those of ordinary skill in the pertinent art that modifications and variations may be made to these and other embodiments without departing from the scope of the present disclosure as defined by the appended claims.