Patent ID: 12237219

DETAILED DESCRIPTION

In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.

FIG.1shows a microelectronic device100that includes electronic components101(e.g., metal oxide semiconductor (MOS) transistors) disposed on or in a semiconductor substrate102. Although the example microelectronic device100is an integrated circuit with multiple components101, other microelectronic device implementations can include a single electronic component. The semiconductor substrate102in one example is a silicon wafer, a silicon-on-insulator (SOI) substrate or other semiconductor structure. One or more isolation structures103are formed on select portions of the upper surface of the substrate102. The isolation structures103can be shallow trench isolation (STI) features or field oxide (FOX) structures in some examples.

A multi-layer metallization structure104,106is disposed above the substrate102. The metallization structure includes a first dielectric structure layer104formed above the substrate102, and a multi-level upper metallization structure106. In one example, the first dielectric104structure layer is a pre-metal dielectric (PMD) layer disposed above the components101and the upper surface of the substrate102. In one example, the first dielectric structure layer104includes silicon dioxide (SiO2) deposited over the components101, the substrate102and the isolation structures103. In one example, the upper metallization structure106is a multi-layer structure. In one example, the multi-layer structure is formed as a multi-layer metallization structure using integrated circuit fabrication processing.FIG.1shows an example 6 layer upper metallization structure106, including a first layer108, referred to herein as an interlayer or interlevel dielectric (ILD) layer. Different numbers of layers can be used in different implementations. In one example, the first ILD layer108, and the other ILD layers of the upper metallization structure106are formed of silicon dioxide (SiO2) or other suitable dielectric material. In certain implementations, the individual layers of the multi-layer upper metallization structure106are formed in two stages, including an intra-metal dielectric (IMD, not shown) sub layer and an ILD sublayer overlying the IMD sub layer. The individual IMD and ILD sublayers can be formed of any suitable dielectric material or materials, such as SiO2-based dielectric materials.

Tungsten or other conductive contacts110extend through selective portions of the first dielectric structure layer104. The first ILD layer108, and the subsequent ILD layers in the upper metallization structure106include conductive metallization interconnect structures112, such as aluminum formed on the top surface of the underlying layer. In this example, the first layer108and the subsequent ILD layers also include conductive vias113, such as tungsten, providing electrical connection from the metallization features112of an individual layer to an overlying metallization layer. The example ofFIG.1includes a second layer114disposed over the first layer108. The second ILD layer114includes conductive interconnect structures112and vias113. The illustrated structure includes further metallization levels with corresponding dielectric layers115,116and117, as well as an uppermost or top metallization layer118. The substrate102, the electronic components101, the first dielectric structure layer104and the upper metallization structure106constitute a wafer or die120with an upper side or surface121. The individual layers115-118in this example include conductive interconnect structures112and associated vias113.

The top metallization layer118includes two example conductive features119, such as upper most aluminum vias. The conductive features119include a side or surface at the upper side121of the wafer or die120at the top of the uppermost metallization layer118. Any number of conductive features119may be provided. One or more of the conductive features119can be electrically coupled with an electronic component101. The upper ILD dielectric layer118in one example is covered by one or more protection layers (e.g., protective overcoat (PO) and/or passivation layers, not shown), for example, silicon nitride (SiN), silicon oxynitride (SiOxNy), or silicon dioxide (SiO2). In one example, the protection layer or layers include one or more openings that expose a portion of the conductive features119to allow electrical connection of the features119to corresponding contact structures.

The microelectronic device100ofFIG.1also includes two example contact structures132. Each contact structure132is electrically coupled with corresponding one of the conductive features119. The individual contact structures132include a barrier layer122disposed at least partially on the corresponding conductive feature119, along with a copper structure126that extends at least partially outward (e.g., upward inFIG.1) from the upper side121of the wafer or die120. The individual contact structures132also include a bronze material124disposed between the barrier layer122and the copper structure126. In one example, the bronze material layer124has a thickness of 300 μm or more and 800 μm or less (e.g., along the vertical or Y-axis direction inFIG.1). In one example, the barrier layer122includes titanium (Ti) or titanium tungsten (TiW). In one example, the barrier layer122has a thickness that is less than the thickness of the bronze material layer124.

In one example, the copper structure126provides a copper pillar or post for subsequent soldering to a flip-chip substrate or chip carrier, or for soldering to a bond wire during packaging. The bronze material124in one example provides electrically conductive coupling between the copper structure126and the barrier layer122. In one example, the lateral dimensions of the barrier layer122, the bronze material124and the copper structure126(e.g., along the X-axis direction inFIG.1) are approximately equal to one another. In particular, the lateral dimensions of the bronze material124and the copper structure126are substantially equal in one implementation due to a reduction or elimination of undercutting of the bronze material124beneath the copper structure126during fabrication. This facilitates low impedance coupling of the copper structure126with the conductive features119of the wafer or die120.

In one example, the contact structure132further includes solder130, such as tin silver (SnAg) on or above the copper structure126, although not required for all possible implementations. In one example, the contact structure132further includes a diffusion barrier layer128, such as a nitride material disposed between the copper structure126and the solder130, although other implementations are possible in which the diffusion barrier layer128and/or the solder130are omitted. In another example, the copper structure126is directly soldered to a chip carrier substrate or to a bond wire using solder supplied during a packaging process.

FIG.2shows a method200of fabricating a microelectronic device, such as the device100ofFIG.1. The example method200includes a process or method to fabricate a contact structure of an electronic apparatus, such as the contact structures132inFIG.1.FIGS.3-13illustrate processing at various intermediate stages of fabrication to produce the device100ofFIG.1according to the method200. The method200begins with fabricating one or more electronic components on and/or in a substrate at202. Any suitable semiconductor processing steps can be used at202in order to fabricate one or more electronic components on and/or in a semiconductor substrate102. For example, the processing at202can include fabricating one or more transistors101on and/or in the semiconductor substrate102as shown inFIG.3. In one example, the fabrication at202includes fabrication of additional structural features, such as isolation structures103shown inFIG.3. The method200ofFIG.2further includes fabricating a metallization structure above the substrate at204(e.g., first dielectric structure layer104and an upper metallization structure106above the substrate102inFIG.3). In certain examples, construction of the metallization structure at204can further include fabrication of one or more additional electronic components (e.g., resistors, inductors, capacitors, transformers, not shown) at least partially in the metallization structure. The processing at202and204in one example provides a wafer120as shown inFIG.3.

Further processing at206-226inFIG.2provides an included method for fabricating a contact structure, such as the contact structure132inFIG.1. In this example, the method200includes forming a barrier layer at least partially on a conductive feature of the wafer120at204.FIG.4shows one example, including performing a sputtering or electroplating deposition process400that deposits the barrier layer122on the upper side121of the wafer120. In one example, the deposition process400forms a titanium or titanium tungsten material barrier layer122on the wafer side121, which extends at least partially on the conductive features119of the wafer120.

The method200further includes forming a seed layer on the barrier layer at208.FIG.5shows one example, including performing a deposition process500that forms a tin (Sn) seed layer123on the barrier layer122. In one example, the deposition process500forms the tin seed layer123to a thickness of 300 μm or more and 800 μm or less. In one example, the process500is a sputtering process that deposits tin directly on a TiW or Ti barrier layer122. In another example, an electroplating deposition process500can be used to form the tin seed layer123on the barrier layer122. The seed layer123in one example provides a conductive material to facilitate subsequent electroplating to form a copper structure (e.g., copper structure126inFIG.1). Moreover, the use of tin for the seed layer123facilitates subsequent formation of bronze above the barrier layer122(e.g., bronze124inFIG.1), and further facilitates removal of portions of the bronze124without significant undercutting. In this regard, using sputtered copper for a seed layer can lead to undesirable undercutting during subsequent etching, in which the etch process preferentially removes sputtered copper seed layer material at a higher etch rate than overlying electroplated copper. The use of deposited tin and subsequently formed bronze for the seed layer material according to the process200advantageously reduces or mitigates undercutting, and facilitates construction of low impedance contact structures to allow soldering during subsequent packaging operations with low impedance electrical coupling to the conductive features119of the wafer120.

The method200continues inFIG.2with formation of a copper post or pillar structure above the deposited seed layer at210,212and214. One example implementation includes forming a photoresist layer at210, and patterning the photoresist layer at212to form openings for pillars.FIG.6shows an example deposition process600that deposits and patterns a photoresist material layer602on the tin seed layer123. The photoresist layer602in one example is patterned at212using a photolithography process that selectively removes portions of the photoresist material602to expose portions of the tin seed layer123above the conductive features119of the wafer120. The lateral (X-axis) width of the openings in the photoresist layer602in one example is generally coextensive with the lateral width of the conductive features119of the wafer120, although not a requirement of all possible implementations. The copper structure formation in this example includes depositing copper material at214on the exposed portion of the tin seed layer123above the conductive feature.FIG.7shows one example, including performing an electroplating deposition process700that forms the copper structures126in the openings of the photoresist602. The process700forms the copper structures126on the exposed portions of the seed layer123above the conductive features119of the wafer120. As previously mentioned, the use of the initially tin barrier layer123directly under the deposited copper structures126, and the subsequent reaction to form bronze124below the electroplated copper structures126advantageously mitigates or avoids undercutting during subsequent etching steps during fabrication of the microelectronic device100. In addition, the use of a thin tin barrier layer123(e.g., 300 to 800 μm) advantageously mitigates or avoids formation of Kirkendall voids at the interface of the copper post structures126and the tin seed layer123.

In one example, the contact structures132also include a diffusion barrier layer (e.g.,128inFIG.1), and solder (e.g.,130) above the deposited copper structures126. In this example, the method200further includes forming a diffusion barrier layer at216inFIG.2.FIG.8shows an example process800that forms a diffusion barrier layer128on the portions of the copper structures126exposed through the photoresist602. In one example, the process800forms a nickel material (Ni) diffusion barrier layer128on the exposed portions of the copper structures126. In another example, the diffusion barrier formation at216is omitted.

In the example ofFIG.2, the method200further includes forming solder at218on the diffusion barrier layer (if included), or forming solder at218directly on the exposed portions of the copper structures126.FIG.9shows an example process900that forms solder (e.g., tin silver or SnAg)130on the diffusion barrier layer128above the copper structure126. In one example, the solder130is formed by an electroplating process900at218. In another example, the solder deposition at218and the diffusion barrier formation at216are omitted.

The method200continues at220inFIG.2with removal of the remaining resist layer.FIG.10shows a photoresist removal process1000(e.g., selective etch) that removes the photoresist material602from the wafer120. Although the example method200is illustrated and described above using a damascene type process to form the copper structures126using a pattern photoresist602, other processing steps can be used to form a conductive copper structure on the seed layer above the conductive feature119of the wafer120. Moreover, although the illustrated example wafer120includes multiple conductive features119and corresponding contact structures132, other implementations are possible in which only a single contact structure132is formed, and further examples are possible in which more than two contact structures132are formed.

Continuing at222inFIG.2, the method200also includes heating the seed layer123and the copper structure126to form a bronze material124between the barrier layer122and the copper structure126.FIG.11shows an example in which an annealing process1100is performed at a temperature sufficient to react the deposited tin seed layer123with the overlying electroplated copper126to form the bronze material124between the underlying barrier layer122and the overlying electroplated copper structures126above the corresponding conductive features119of the wafer120. In one example, the annealing process1100causes diffusion of tin and copper at the interface of the copper post structure126resulting on formation of bronze material124as shown inFIG.11.

The method200further includes removing the exposed portion(s) of the remaining tin seed layer123to expose a portion of the barrier layer122at224inFIG.2.FIG.12shows an example in which an etch process1200is performed that etches the exposed tin seed layer123. The process1200selectively removes an exposed portion of the tin seed layer123to expose a portion of the barrier layer122as shown inFIG.12. In one example, the etch process1200uses an acidic stripping solution (e.g., Enstrip TL-105 from Enthone by immersing the wafer120into the solution, where no current is required). The etch process1200selectively removes the exposed portion of the tin seed layer123from an underlying portion of the barrier layer122. In another example, the tin seed layer123is selectively removed at224substantially without removing copper126either by immersion into hot solution of potassium hydroxide or sodium hydroxide. Alternatively, Enstrip TL-105 (from Enthone) can be used by immersing the work specimen into this solution and no current is required. Other selective etch processes1200can be used, for example, using a solution designed for removing of tin from copper and copper alloys. The use of the process1200to selectively remove the remaining (e.g., unreacted) seed layer material123, and the previously diffused bronze material124between the copper126and the Ti/TiW barrier layer122mitigates or avoids the undercut issue found in alternate processes that use a sputtered copper seed layer (not shown).

The process200continues at226inFIG.2with removal of the exposed barrier layer122.FIG.13shows one example using a selective etch process1300that removes the exposed portions of the barrier layer122between the contact structures132. The microelectronic device fabrication process200concludes at228with die singulation and (e.g., separation of the wafer120into two or more dies), and packaging of individual microelectronic device dies.FIG.14shows one example packaged microelectronic device100undergoing a packaging process1400that solders the bond wires1402to the constructed contact structures132using solder1404.FIG.15shows another example in which the microelectronic device100undergoes a flip-chip soldering process1500that solders the constructed contact structures132to conductive pads or features1504of a flip-chip substrate1502.

A finished microelectronic device100can include other features, such as molded or ceramic packaging material, lead frames, solder bumps, etc.FIG.16shows an example integrated circuit (IC)1600that includes the microelectronic device100. This example includes bond wires1402(e.g.,FIG.14above) soldered between the contact structures132and electrical conductors1602(e.g., leads, pins or pads) of a leadframe. The example IC1600also includes a molded package material1604(e.g., plastic) that encloses the die120, the contact structures132, the bondwires1402and portions of the electrical conductors1602. The example electrical conductors1602are IC pins or pads that can be soldered to a host printed circuit board (PCB, not shown).

The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.