Patent ID: 12212340

DESCRIPTION OF EMBODIMENTS

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation.

References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to implement such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. “Coupled” is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other. “Connected” is used to indicate the establishment of communication between two or more elements that are coupled with each other.

The embodiments set forth below represent information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure.

Radio Node: As used herein, a “radio node” is either a radio access node or a wireless device.

Radio Access Node: As used herein, a “radio access node” is any node in a radio access network of a cellular communications network that operates to wirelessly transmit and/or receive signals. Some examples of a radio access node include, but are not limited to, a base station (e.g., an enhanced or evolved Node B (eNB) in a Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) network), a high-power or macro base station, a low-power base station (e.g., a micro base station, a pico base station, a home eNB, or the like), and a relay node.

Core Network Node: As used herein, a “core network node” is any type of node in a core network. Some examples of a core network node include, e.g., a Mobility Management Entity (MME), a Packet Data Network (PDN) Gateway (P-GW), a Service Capability Exposure Function (SCEF), or the like.

Wireless Device: As used herein, a “wireless device” is any type of device that has access to (i.e., is served by) a cellular communications network by wirelessly transmitting and/or receiving signals to a radio access node(s). Some examples of a wireless device include, but are not limited to, a User Equipment device (UE) in a 3GPP network and a Machine Type Communication (MTC) device.

Network Node: As used herein, a “network node” is any node that is either part of the radio access network or the core network of a cellular communications network/system.

Note that the description given herein focuses on a 3GPP cellular communications system and, as such, 3GPP LTE terminology or terminology similar to 3GPP LTE terminology is oftentimes used. However, the concepts disclosed herein are not limited to LTE or a 3GPP system.

FIG.2illustrates one example of a cellular communications network10according to some embodiments of the present disclosure. In the embodiments described herein, the cellular communications network10is an LTE network in which some or all of the radio access nodes operate on a carrier(s) in an unlicensed spectrum. In a particular embodiment, for example, cellular communications network10may operate on the 5 gigahertz (GHz) spectrum. However, the present disclosure is not limited thereto. Accordingly, in another example, the cellular communications network10may implement LAA, LTE-U, MulteFire, or some other technology in which radio access nodes operate on an unlicensed carriers(s).

As depicted, the cellular communications network10includes base stations12-1and12-2, which in LTE are referred to as eNBs, controlling corresponding macro cells14-1and14-2. The base stations12-1and12-2are generally referred to herein collectively as base stations12and individually as base station12. Likewise, the macro cells14-1and14-2are generally referred to herein collectively as macro cells14and individually as macro cell14. The cellular communications network10also includes a number of low power nodes16-1through16-4controlling corresponding small cells18-1through18-4. In LTE, the low power nodes16-1through16-4can be small base stations (such as pico or femto base stations) or Remote Radio Heads (RRHs), or the like. Notably, while not illustrated, one or more of the small cells18-1through18-4may alternatively be provided by the base stations12. The low power nodes16-1through16-4are generally referred to herein collectively as low power nodes16and individually as low power node16. Likewise, the small cells18-1through18-4are generally referred to herein collectively as small cells18and individually as small cell18. The base stations12(and optionally the low power nodes16) are connected to a core network20.

The base stations12and the low power nodes16provide service to wireless devices22-1through22-5in the corresponding cells14and18. The wireless devices22-1through22-5are generally referred to herein collectively as wireless devices22and individually as wireless device22. In LTE, the wireless devices22are referred to as UEs.

According to certain embodiments, the macro cells14may be provided in a licensed frequency spectrum (i.e., in the frequency spectrum dedicated for the cellular communications network10) such as, for example, for LAA operation. In other embodiments, the macro cells14may be provided in an unlicensed frequency spectrum such as, for example, for LAA in the unlicensed spectrum (LAA-U) or MulteFire operation. According to certain embodiments, one or more (and possibly all) of the small cells18may be provided in an unlicensed frequency spectrum such as, for example, the 5 GHz frequency spectrum.

In a particular embodiment, base stations12,14that operate on a carrier(s) in an unlicensed spectrum may operate to perform LBT and transmit Multimedia. Broadcast Multicast. Services (MBMS) data according to any of the embodiments described herein.

FIG.3is a schematic block diagram of radio access node24, according to certain embodiments. The radio access node24may be, for example, a base station12,16. As illustrated, the radio access node24includes a control system26that includes one or more processors28(e.g., Central Processing Units (CPUs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and/or the like), memory30, and a network interface32. In addition, the radio access node24includes one or more radio units34that each includes one or more transmitters36and one or more receivers38coupled to one or more antennas40. In some embodiments, the radio unit(s)34is external to the control system26and connected to the control system26via, for example, a wired connection such as, for example, an optical cable. However, in some other embodiments, the radio unit(s)34and potentially the antenna(s)40may be integrated together with the control system26. The one or more processors28may operate to provide one or more functions of a radio access node24as described herein. In some embodiments, the function(s) may be implemented in software that is stored such as, for example, in the memory30and executed by the one or more processors28.

FIG.4is a schematic block diagram that illustrates a virtualized embodiment of the radio access node24, according to certain embodiments. However, the description thereof may be equally applicable to other types of network nodes. Further, any of the types of network nodes may have similar virtualized architectures.

As used herein, a “virtualized” radio access node is an implementation of the radio access node24in which at least a portion of the functionality of the radio access node24is implemented as a virtual component(s). For example, the functionality of the radio access node may be implemented via a virtual machine(s) executing on a physical processing node(s) in a network(s), in a particular embodiment. In the illustrated example embodiment, the radio access node24includes the control system26that includes the one or more processors28(e.g., CPUs, ASICs, FPGAs, and/or the like), the memory30, and the network interface32and the one or more radio units34that each includes the one or more transmitters36and the one or more receivers38coupled to the one or more antennas40, as described above. The control system26is connected to the radio unit(s)34via, for example, an optical cable or the like. The control system26is connected to one or more processing nodes42coupled to or included as part of a network(s)44via the network interface32. Each processing node42includes one or more processors46(e.g., CPUs, ASICs, FPGAs, and/or the like), memory48, and a network interface50.

According to certain embodiments, functions52of the radio access node24described herein may be implemented at the one or more processing nodes42or distributed across the control system26and the one or more processing nodes42in any desired manner. In some particular embodiments, some or all of the functions52of the radio access node24described herein are implemented as virtual components executed by one or more virtual machines implemented in a virtual environment(s) hosted by the processing node(s)42. As may be appreciated by one of ordinary skill in the art, additional signaling or communication between the processing node(s)42and the control system26may be used in order to carry out at least some of the desired functions52. Notably, in some embodiments, the control system26may not be included, in which case the radio unit(s)34communicate directly with the processing node(s)42via an appropriate network interface(s).

According to certain embodiments, a computer program including instructions which, when executed by at least one processor, causes the at least one processor to carry out the functionality of radio access node24or a node (e.g., a processing node42) implementing one or more of the functions52of the radio access node24in a virtual environment according to any of the embodiments described herein is provided. In some embodiments, a carrier comprising the aforementioned computer program product is provided. The carrier is one of an electronic signal, an optical signal, a radio signal, or a computer readable storage medium (e.g., a non-transitory computer readable medium such as memory).

FIG.5is a schematic block diagram illustrating another example radio access node24, according to certain other embodiments. The radio access node24includes one or more modules54, each of which is implemented in software. The module(s)54provide the functionality of the radio access node24described herein. This discussion is equally applicable to the processing node42ofFIG.7(described below) where the modules54may be implemented at one of the processing nodes42or distributed across multiple processing nodes42and/or distributed across the processing node(s)42and the control system26.

FIG.6is a schematic block diagram of a UE56, according to certain embodiments. As illustrated, the UE56includes one or more processors58(e.g., CPUs, ASICs, FPGAs, and/or the like), memory60, and one or more transceivers62each including one or more transmitters64and one or more receivers66coupled to one or more antennas68. In some embodiments, the functionality of the UE56described above may be fully or partially implemented in software that is, e.g., stored in the memory60and executed by the processor(s)58.

In some embodiments, a computer program including instructions which, when executed by at least one processor, causes the at least one processor to carry out the functionality of the UE56according to any of the embodiments described herein is provided. In some embodiments, a carrier comprising the aforementioned computer program product is provided. The carrier is one of an electronic signal, an optical signal, a radio signal, or a computer readable storage medium (e.g., a non-transitory computer readable medium such as memory).

FIG.7is a schematic block diagram of the UE56according to some other embodiments of the present disclosure. The UE56includes one or more modules70, each of which is implemented in software. The module(s)70provide the functionality of the UE56described herein.

Various network nodes can perform the functionality described below. For example, an access node (e.g., an eNB) could perform the various interleaving steps provided herein. One of ordinary skill in the art would realize that a receiver (e.g., a UE) would be able to perform the corresponding decoding, according to one example. Of course, it would be readily understood by one of ordinary skill in the art that various combinations of radio nodes could be implemented to perform the functionality described herein.

It should be noted that while the discussion herein uses the downlink control information (DCI) and uplink control information (UCI) as an example, the methods disclosed below can be used for any type of information packet transmission that require both the function of error detection and the function of error correction. Hence, for example, the same methods can be applied to physical uplink channel data packets, physical downlink data channel packets, higher layer control packets, etc.

Note that while two types of precoders, CRC and PC, are used as example in discussion below, the same principle can be applied to other types of precoders, e.g., other types of linear block codes.

According to certain embodiments, when designing concatenated Polar codes for error correction control of DCI and UCI of NR, CRC bits are attached as a precoder of Polar codes for two purposes:A sequence of Ld,0CRC bits, where Ld,0is the minimum number of CRC bits necessary to ensure minimum level of error detection capability. Using 3GPP LTE as a reference, Ld,0=16 for DCI, Ld,0=8 for UCI of larger information block size K.An additional Lc,0CRC bits attached. The additional Lc,0CRC bits can be used for error detection and/or error correction purposes.
Hence a total of Ltotal=+Lc,0) CRC bits are attached in the precoder of Polar codes. In a particular embodiment, the LtotalCRC bits are generated using one CRC generator polynomial of length Ltotal. In another embodiment, the Ld,0CRC bits are generated using a first CRC generator polynomial of length Ld,0, while the Lc,0CRC bits are generated using a second CRC generator polynomial of length Lc,0.

According to certain embodiments, adaptive allocation of CRC bits between error correction and error detection is provided. The set of LtotalCRC bits may be used in an adaptive manner to achieve the best combination of error detection performance and error correction performance. The adaptation may be performed such that at least two of the following three options of allocating the CRC bits for different purposes are supported, according to a particular embodiment:OPTION A: Lower error detection capability, higher error correction capability. In this option, Ld,1CRC bits are used for error detection, Lc,1CRC bits are used to assist with SCL decoding (i.e., error correction).OPTION B: Medium error detection capability, medium error correction capability. In this option, Ld,2CRC bits are used for error detection, Lc,2CRC bits are used to assist with SCL decoding (i.e., error correction).OPTION C: Higher error detection capability, lower error correction capability. In this option, Ld,3CRC bits are used for error detection, Lc,3CRC bits are used to assist with SCL decoding (i.e., error correction).
In the above scenarios, Ltotal=(Ld,1+Lc,1)=(Ld,2+Lc,2)=(Ld,3+Lc,3), with: Ld,0<=Ld,1<Ld,2<Ld,3, Lc,0>=Lc,1>Lc,2>Lc,3. It may be taken into account that larger number of CRC bits used for SCL decoding generally requires a more complex decoder implementation, which is then able to achieve better BLER performance of the same information block size K and codeword size M. Note that in each of the scenarios mentioned above, a predetermined subset of Lc,iCRC bits is used for error correction, for any i=1,2,3, but the bits chosen for error correction need not be consecutive or contiguous and can be, for example, spaced evenly across the available CRC bits, in a particular embodiment. While three different ways to balance the error detection and error correction capabilities are described in Options A-C, it may be understood that more ways to balance are possible using the same or similar principles.

According to certain particular embodiments, the adaption can be performed as a function of various configuration parameters, including:According to various particular embodiments, the adaptation may be performed according to different target levels of reliability of the service. For example, for high reliability applications (e.g. URLLC), Option A may be used, in a particular embodiment. On the other hand, for low reliability applications (e.g., mMTC), Option C may be used, in a particular embodiment.According to various particular embodiments, the adaptation may be performed according to the latency target of the associated data packet. The target latency can also be reflected by the maximum number retransmissions possible for the associated data packet. For example, for data packets with a low-latency requirement, Option A may be used, in a particular embodiment. Examples of low-latency scenarios include: video packet, voice packet, and instantaneous channel feedback. More CRC bits are used for error correction, since detecting an error may not help the applications as retransmission is not worth the delay. On the other hand, for data packets that can tolerate high latency, Option C may be used, in a particular embodiment.According to various particular embodiments, the adaptation may be performed according to different receiver categories (or receiver types). Typically, the receiver is the UE on the downlink. For example, for lower-cost UEs, lower-complexity SCL decoder implementation is desired, hence Option C may be used, in a particular embodiment. For higher-cost UEs, higher-complexity SCL decoder implementation can be afforded, hence Option A may be used in a particular embodiment. For a medium-cost UE, Option B may be used in an exemplary compromise.

According to certain embodiments, the total number of CRC bits (Ltotal) may be adaptively chosen according to different configuration parameters. Examples include:According to various particular embodiments, the choice of the total number of CRC bits may be selected according to different target levels of reliability of the service. For example, for high reliability applications (e.g. URLLC), a larger total number of CRC bits may be used. On the other hand, for low reliability applications (e.g., mMTC), a smaller number of total CRC bits is used.According to various particular embodiments, the choice of the total number of CRC bits is chosen according to the information block length K, the code block length N, and/or the code rate R=K/N. For a fixed code length N more CRC bits may be used for small number of information bits K, or equivalently, for lower rate R, and vice versa.
Note that the adaptation of total number of CRC bits Ltotalcan be done along with its corresponding allocation between error correction purpose (Lc,ibits) and error detection purpose (Ld,ibits) as described above.

According to certain embodiments, the placement of CRC bits may be adaptively chosen.FIG.8illustrates an encoder structure of concatenated Polar code without interleaving, according to certain embodiments. As shown, the CRC bits are attached as a contiguous block and not interleaved with the information bits. Typically, the sequence of CRC bits are attached to the end of information bit sequence, as shown inFIG.8.

When the sequence of LtotalCRC bits are attached as a contiguous block to the end of info bit sequence, the CRC bits must be used as a block to perform CRC check. The CRC bits cannot be used individually to perform CRC check. Thus, the CRC bits are treated the same as the information bits in the SCL decoding process until the very end of the trellis. At the end of the trellis, the CRC bits are used to perform CRC check and select the best codeword candidate as decoder output.

Even though the CRC bits are attached at the end of the block, some of the CRC bits may still be integrated into a list decoder for the Polar inner code to limit the decoding to within a subspace that is consistent with those CRC bits integrated into the list decoding process. This would improve the error correction capability of the resulting integrated list decoding process. However, since the CRC bits are clustered together in the end, the performance benefit is limited. If further performance benefit is desired, one may consider using an “Interleaved CRC bits” construction as described below.

FIG.9illustrates an encoder structure using interleaved CRC bits, according to certain embodiments. Specifically, the sequence of LtotalCRC bits may be interleaved with information bits before Polar encoding. In a particular embodiment, the CRC bits may be coupled with such an interleaver that the CRC bits can be used individually to perform a CRC check. One example of the encoder structure using interleaved CRC bits is illustrated inFIG.9.

According to certain embodiments, and as depicted, an interleaver may be added between the CRC outer code and the Polar inner code. Thus, the CRC bits are interleaved with the information bits, before being sent to the input of inner Polar encoder. The interleaver is built to facilitate list decoding of the inner Polar code, where the Polar SCL decoder can take into account the dependency structure of the parity bits and the data bits from the outer code. In some applications, only some (Lc,i) CRC bits are used to account for the dependency structure of the parity bits to improve error correction capability of the code, while the other (Ld,i) CRC bits are treated like other information bits where the decoder would hypothesize their values during the decoding process. In this alternative embodiment, some of the distributed CRC bits are not treated the same as information bits. The error-correcting CRC bits are used in the process of tree expansion to select the better decoding paths in such a way that each surviving decoding path selected must be consistent with the dependency structure of the parity bits. The CRC check does not have to wait till the end of trellis expansion.

According to certain embodiments, instead of CRC bits, parity checksum (PC) bits can be generated in the precoder instead. It is generally recognized that any of the above methods and techniques described above as being applicable to CRC bits are equally applicable to PC bits.

FIG.10illustrates a PC-Polar code, according to certain embodiments. Each of the PC bits, which may also be referred to as PC-frozen bits, is derived as the parity checksum of a selected subset of information bits. The PC bits are similar to the interleaved CRC bits, where each of the PC bits can be used individually to select the better decoding paths.

Similar to the adaptive allocation of CRC bits between error correction and error detection, the PC bits can be used for both functions, according to certain embodiments. The exact split of PC bits between these two functions can be done adaptively, as discussed below. Specifically, according to certain embodiments, the set of LtotalPC bits can be used in an adaptive manner to achieve the best combination of error detection performance and error correction performance. The adaptation is performed such that at least two of the following three options of allocating the PC bits for different purposes are supported, according to an embodiment:OPTION A: Lower error detection capability, higher error correction capability. In this option, Ld,1PC bits are used for error detection, Lc,1PC bits are used to assist with SCL decoding (i.e., error correction).OPTION B: Medium error detection capability, medium error correction capability. In this option, Ld,2PC bits are used for error detection, Lc,2PC bits are used to assist with SCL decoding (i.e., error correction).OPTION C: Higher error detection capability, lower error correction capability. In this option, Ld,3PC bits are used for error detection, Lc,3PC bits are used to assist with SCL decoding (i.e., error correction).
In the above scenarios, Ltotal=(Ld,1+Lc,1)=(Ld,2+Lc,2)=(Ld,3+Lc,3), with: 0<=Ld,1<Ld,2<Ld,3, Ltotal>=Lc,1>Lc,2>Lc,3.

Similar to the CRC bits, the total number of PC bits, Ltotal, can be fixed for a size combination (K,M), or vary with the size combination. Here K is the number of information bits, and M the number of coded bits to send over the air.

In contrast to CRC bits, there is no non-zero minimum number of PC bits that have to be allocated to error detection purpose; that is, all PC bits can be used for error correction purpose.

According to certain embodiments, once an option from Option A-C is selected, the Polar decoder is run accordingly.The Lc,i, i=1,2,3, PC bits are used in the middle of SCL decoding to select the best decoding path during path expansion.The Ld,i, i=1,2,3, PC bits are not used in the middle of SCL decoding. Instead, the Ld,i, PC bits are treated as information bits during path expansion. Hard decisions for the Ld,i, PC bits are made. Then the Ld,i, PC bits are used as checksum at the end of SCL decoding to detect if the SCL output is a valid codeword or not.
Similar to CRC-assisted Polar, the adaption can be performed as a function of various configuration parameters such as data service type, latency requirement, block error rate target, and UE category. Additionally, both the value Ltotal, and the split of Ltotalbetween Lc,iand Ld,i, can be adapted.

FIG.11is a flow diagram illustrating an example method for adaptively selecting a total number of CRC or PC bits, according to certain embodiments. As shown inFIG.11, at step1100, a network node adaptively selects the total number of, for example, CRC bits. At step1110, a different amount of the available CRC bits can be allocated between error detection and error correction for Polar codes. At step1120, the CRC bits can be placed within a code block. As described above, the precoder bits can be CRC bits or parity-checksum (PC) bits, according to various embodiments.

In certain embodiments, the method for adaptively selecting a total number of CRC or PC bits as described above may be performed by a computer networking virtual apparatus.FIG.12illustrates an example virtual computing device1200for adaptively selecting a total number of CRC or PC bits, according to certain embodiments. In certain embodiments, virtual computing device1200may include modules for performing steps similar to those described above with regard to the method illustrated and described inFIG.11. For example, virtual computing device1200may include a selecting module1210, an allocating module1220, a placing module1230, and any other suitable modules for adaptively selecting a total number of CRC or PC bits. In some embodiments, one or more of the modules may be implemented using one or more processor(s)28ofFIG.3or one or more processor(s)58ofFIG.6. In certain embodiments, the functions of two or more of the various modules may be combined into a single module.

The selecting module1210may perform the selecting functions of virtual computing device1200. For example, in a particular embodiment, selecting module1210may adaptively select the total number of CRC or PC bits.

The allocating module1220may perform the allocation functions of virtual computing device1200. For example, in a particular embodiment, allocating module1220may allocate a different amount of the available CRC bits, for example, between error detection and error correction for Polar codes.

The placing module1230may perform the placing functions of virtual computing device1200. For example, in a particular embodiment, placing module1230may place the CRC bits, for example, within a code block.

Other embodiments of virtual computing device1200may include additional components beyond those shown inFIG.12that may be responsible for providing certain aspects of the functionality, including any of the functionality described above and/or any additional functionality (including any functionality necessary to support the solutions described above). The various different types of devices and radio nodes may include components having the same physical hardware but configured (e.g., via programming) to support different radio access technologies, or may represent partly or entirely different physical components.

FIG.13illustrates an example method1300by a transmitter for adaptively generating precoder bits for a Polar code, according to certain embodiments. According to certain embodiments, the transmitter may be a wireless device such as wireless device56, described above. According to certain other embodiments, the transmitter may be a network node such as radio access node24or another network node. In various embodiments, the precoder bits may include CRC bits or PC bits.

The method begins at step1310when the transmitter acquires at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter may include at least one of an information block length K, a code block length N, and/or a code rate R=K/N.

At step1320, the transmitter determines the total number of precoder bits. In a particular embodiment, for example, the transmitter may allocate a first number of the available precoder bits (Ld) to error detection and a second number of the available precoder bits (Lc) to error correction. According to a particular embodiment, the first number of the available precoder bits (Ld) may be a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection for a number of info bits and the second number of the available precoder bits (Lc) may be determined by subtracting the first number of available precoder bits (Ld) from a total number of available precoder bits (Ltotal). In another particular embodiment, the first number of the available precoder bits (Ld) allocated to error detection may be greater than a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability.

In still another particular embodiment, the transmitter may determine the total number of precoder bits by performing one of:allocating a first number of the available precoder bits (Ld,1) to error detection and a second number of the available precoder bits (Lc,1) to error correction for lower error detection capability and higher error correction capability;allocating a third number of the available precoder bits (Ld,2) to error detection and a fourth number of the available precoder bits (Lc,2) to error correction for medium error detection capability and medium error correction capability;allocating a fifth number of the available precoder bits (Ld,3) to error detection and a sixth number of the available precoder bits (Lc,3) to error correction for higher error detection capability and lower error correction capability, and
In any of the above scenarios, for a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability, the following may be true:
Ld,0<=Ld,1<Ld,2<Ld,3, and
Lc,1>Lc,2>Lc,3

At step1330, the transmitter generates the precoder bits for a code block according to the determined total number of precoder bits. According to various particular embodiments, the precoder bits may be generated based on at least one of latency requirements, reliability requirements, wireless channel conditions as indicated by a target code rate, and available radio resources as indicated by a code length. Where the precoder bits are CRC bits, for example, the CRC bits may be generated using a single CRC generated polynomial, in a particular embodiment. In another particular embodiment, the CRC bits may be generated using two or more CRC generated polynomials.

At step1340, the transmitter places the precoder bits within the code block. In a particular embodiment the transmitter may place the precoder bits in the code block as a contiguous block. In another embodiment, the transmitter may use an interleaver to place the precoder bits at interleaved positions within the code block.

In certain embodiments, the method for adaptively generating precoder bits for a Polar code as described above may be performed by a virtual computing device.FIG.14illustrates an example virtual computing device1400for adaptively generating precoder bits for a Polar code, according to certain embodiments. In certain embodiments, virtual computing device1400may include modules for performing steps similar to those described above with regard to the method1300illustrated and described inFIG.13. For example, virtual computing device1400may include at least one acquiring module1410, a determining module1420, a generating module1430, a placing module1440, and any other suitable modules for adaptively generating precoder bits for a Polar code. In some embodiments, one or more of the modules may be implemented using one or more processors28ofFIG.3or one or more processors58ofFIG.6. In certain embodiments, the functions of two or more of the various modules may be combined into a single module.

The acquiring module1410may perform the acquiring functions of virtual computing device1400. For example, in a particular embodiment, acquiring module1410may acquire at least one configuration parameter upon which a total number of precoder bits depends.

The determining module1420may perform the determining functions of virtual computing device1400. For example, in a particular embodiment, determining module1420may determine the total number of precoder bits.

The generating module1430may perform the generating functions of virtual computing device1400. For example, in a particular embodiment, generating module1430may generate the precoder bits for a code block according to the determined total number of precoder bits.

The placing module1440may perform the placing functions of virtual computing device1400. For example, in a particular embodiment, placing module1440may place the precoder bits within the code block.

Other embodiments of virtual computing device1400may include additional components beyond those shown inFIG.14that may be responsible for providing certain aspects of the transmitter's functionality, including any of the functionality described above and/or any additional functionality (including any functionality necessary to support the solutions described above). The various different types of transmitters may include components having the same physical hardware but configured (e.g., via programming) to support different radio access technologies, or may represent partly or entirely different physical components.

FIG.15illustrates another example method1500by a transmitter for adaptively generating precoder bits for a Polar code, according to certain embodiments. According to certain embodiments, the transmitter may be a wireless device such as wireless device56, described above. According to certain other embodiments, the transmitter may be a network node such as radio access node24or another network node. In various embodiments, the precoder bits may include CRC bits or PC bits.

The method begins at step1510when the transmitter allocates a different amount of available precoder bits between error detection and error correction for the Polar code. According to various particular embodiments, the precoder bits may be allocated based on at least one of latency requirements, reliability requirements, wireless channel conditions as indicated by a target code rate, and available radio resources as indicated by a code length.

In a particular embodiment, the transmitter may allocate a first number of the available precoder bits (Ld) to error detection and a second number of the available precoder bits (Lc) to error correction. 24. For example, the first number of the available precoder bits (Ld) may be a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection for a number of info bits and the second number of the available precoder bits (Lc) is determined by subtracting the first number of available precoder bits (Ld) from a total number of available precoder bits (Ltotal), in a particular embodiment. In another embodiment, the first number of the available precoder bits (Ld) allocated to error detection may be greater than a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability.

In still another particular embodiment, the transmitter may determine the total number of precoder bits by performing one of:allocating a first number of the available precoder bits (Ld,1) to error detection and a second number of the available precoder bits (Lc,1) to error correction for lower error detection capability and higher error correction capability;allocating a third number of the available precoder bits (Ld,2) to error detection and a fourth number of the available precoder bits (Lc,2) to error correction for medium error detection capability and medium error correction capability;allocating a fifth number of the available precoder bits (Ld,3) to error detection and a sixth number of the available precoder bits (Lc,3) to error correction for higher error detection capability and lower error correction capability, and
In any of the above scenarios, for a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability, the following may be true:
Ld,0<=Ld,1<Ld,2<Ld,3, and
Lc,1>Lc,2>Lc,3.

At step1520, the transmitter generates the precoder bits for a code block according to the allocation and a total number of CRC bits. In a particular embodiment, for example, the CRC bits may be generated using a single CRC generated polynomial. In another particular embodiment, the CRC bits may be generated using two or more CRC generated polynomials.

At step1530, the transmitter places the precoder bits within the code block. In a particular embodiment the transmitter may place the precoder bits in the code block as a contiguous block. In another embodiment, the transmitter may use an interleaver to place the precoder bits at interleaved positions within the code block.

In certain embodiments, the method for adaptively generating precoder bits for a Polar code as described above may be performed by a virtual computing device.FIG.16illustrates an example virtual computing device1600for adaptively generating precoder bits for a Polar code, according to certain embodiments. In certain embodiments, virtual computing device1600may include modules for performing steps similar to those described above with regard to the method1500illustrated and described inFIG.15. For example, virtual computing device1600may include at least one allocating module1610, a generating module1620, a placing module1630, and any other suitable modules for adaptively generating precoder bits for a Polar code. In some embodiments, one or more of the modules may be implemented using one or more processors28ofFIG.3or one or more processors58ofFIG.6. In certain embodiments, the functions of two or more of the various modules may be combined into a single module.

The allocating module1610may perform the allocating functions of virtual computing device1600. For example, in a particular embodiment, allocating module1610may allocate a different amount of available precoder bits between error detection and error correction for the Polar code.

The generating module1620may perform the generating functions of virtual computing device1600. For example, in a particular embodiment, generating module1620may generate the precoder bits for a code block according to the allocation and a total number of CRC bits.

The placing module1630may perform the placing functions of virtual computing device1600. For example, in a particular embodiment, placing module1630may place the precoder bits within the code block.

Other embodiments of virtual computing device1600may include additional components beyond those shown inFIG.16that may be responsible for providing certain aspects of the transmitter's functionality, including any of the functionality described above and/or any additional functionality (including any functionality necessary to support the solutions described above). The various different types of transmitters may include components having the same physical hardware but configured (e.g., via programming) to support different radio access technologies, or may represent partly or entirely different physical components.

FIG.17illustrates an example method1700by a receiver for adaptively using precoder bits to assist decoding of a Polar code, according to certain embodiments. According to certain embodiments, the receiver may be a wireless device such as wireless device56, described above. According to certain other embodiments, the receiver may be a network node such as radio access node24or another network node. In various embodiments, the precoder bits may include CRC bits or PC bits.

The method begins at step1710when the receiver allocates a different amount of available precoder bits between error detection and error correction for a Polar code. According to various particular embodiments, the precoder bits may be allocated based on at least one of latency requirements, reliability requirements, wireless channel conditions as indicated by a target code rate, and available radio resources as indicated by a code length.

In a particular embodiment, the receiver may allocate a first number of the available precoder bits (Ld) to error detection and a second number of the available precoder bits (Lc) to error correction. 24. For example, the first number of the available precoder bits (Ld) may be a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection for a number of info bits and the second number of the available precoder bits (Lc) may be determined by subtracting the first number of available precoder bits (Ld) from a total number of available precoder bits (Ltotal), in a particular embodiment. In another embodiment, the first number of the available precoder bits (Ld) allocated to error detection may be greater than a minimum number of precoder bits (Ld,0) associated with a minimum level of error detection to provide increased error detection capability.

According to certain other embodiments, when allocating the precoder bits, the receiver may perform one of the following steps:allocating a first number of the available precoder bits (Ld,1) to error detection and a second number of the available precoder bits (Lc,1) to error correction for lower error detection capability and higher error correction capability;allocating a third number of the available precoder bits (Ld,2) to error detection and a fourth number of the available precoder bits (Lc,2) to error correction for medium error detection capability and medium error correction capability; orallocating a fifth number of the available precoder bits (Ld,3) to error detection and a sixth number of the available precoder bits (Lc,3) to error correction for higher error detection capability and lower error correction capability;
In the above scenarios, the minimum number of precoder bits (Ld,0) may be associated with a minimum level of error detection to provide increased error detection capability, and the following may be true:
Ld,0<=Ld,1<Ld,2<Ld,3, and
Lc,1>Lc,2>Lc,3

At step1720, the receiver uses the precoder bits allocated for error correction to assist decoding of a code block. After decoding the code block, the receiver uses the precoder bits allocated for error detection to perform error detection on the decoded bits, at step1730.

According to certain embodiments, the method may further include the receiver receiving, from a transmitter, an indication of the different amount of available precoder bits for allocation between error detection and error correction for the Polar codes. The receiver may perform the allocation step1710based on the indication.

In certain embodiments, the method for adaptively using precoder bits to assist decoding of a Polar code as described above may be performed by a virtual computing device.FIG.18illustrates an example virtual computing device1800for adaptively using precoder bits to assist decoding of a Polar code, according to certain embodiments. In certain embodiments, virtual computing device1800may include modules for performing steps similar to those described above with regard to the method1700illustrated and described inFIG.17. For example, virtual computing device1800may include at least one allocating module1810, a first using module1820, a second using module1830, and any other suitable modules for adaptively using precoder bits to assist decoding of a Polar code. In some embodiments, one or more of the modules may be implemented using one or more processors28ofFIG.3or one or more processors58ofFIG.6. In certain embodiments, the functions of two or more of the various modules may be combined into a single module.

The allocating module1810may perform the allocating functions of virtual computing device1800. For example, in a particular embodiment, allocating module1810may allocate a different amount of available precoder bits between error detection and error correction for a Polar code.

The first using module1820may perform certain of the using functions of virtual computing device1800. For example, in a particular embodiment, first using module1820may use the precoder bits allocated for error correction to assist decoding of a code block.

The second using module1830may perform certain other of the using functions of virtual computing device1800. For example, in a particular embodiment, second using module1830may use the precoder bits allocated for error detection to perform error detection on the decoded bits.

Other embodiments of virtual computing device1800may include additional components beyond those shown inFIG.18that may be responsible for providing certain aspects of the receiver's functionality, including any of the functionality described above and/or any additional functionality (including any functionality necessary to support the solutions described above). The various different types of receivers may include components having the same physical hardware but configured (e.g., via programming) to support different radio access technologies, or may represent partly or entirely different physical components.

As disclosed herein, methods, systems and apparatus are disclosed for adaptively selecting the total number of CRC or PC bits, allocating a different amount of the available CRC bits between error detection and error correction for Polar codes, and placing the CRC bits within a code block. As a result, various balances of error correction and error detection capabilities can be achieved in the SCL decoder. The features described allow the concatenation of CRC and PC code to be customized for different amounts of payloads, different coding parameters needed for the varying communication channel conditions, and different types of applications with different requirements in terms of, for example, latency and reliability. Stated differently, according to various embodiments, the foregoing features may be based on the requirements (e.g. latency or reliability) of the underlying application, the wireless channel conditions as indicated by the target code rate, and/or the available radio resources as indicated by the code length.

In one embodiment, the precoder bits can be CRC bits. According to an alternative embodiment, the precoder bits are parity-checksum (PC) bits.

According to various embodiments, an advantage of features herein is to allow the concatenation of CRC code to be customized for different amounts of payloads, different coding parameters needed for the varying communication channel conditions, and different types of applications with different requirements in terms of, for example, latency and reliability. Since wireless communications need to cover a wide range of circumstances and applications, embodiments of this disclosure allow the system to judiciously allocate radio resources based on cost-benefit tradeoffs.

While processes in the figures may show a particular order of operations performed by certain embodiments of the invention, it should be understood that such order is exemplary (e.g., alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, etc.).

While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.