Patent ID: 12218080

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. Where applicable, the term “substantially” may also relate to 90% or higher of what is specified, such as 95% or higher, especially 99% or higher, including 100%. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” are to be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10 degrees. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y.

Terms such as “about” in conjunction with a specific distance or size are to be interpreted so as not to exclude insignificant deviation from the specified distance or size and may include for example deviations of up to 10%. The term “about” in relation to a numerical value x may mean x±5 or 10%.

Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure and/or the package structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

Embodiments of the disclosure may relate to three-dimensional (3D) packaging or 3D-IC devices. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3D-IC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3D-IC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIGS.1A-1Jare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. As shown inFIG.1A, a carrier substrate100is provided or received. The carrier substrate100is used as a support substrate during the fabrication process. The carrier substrate100also functions as a reinforced plate that enhances the strength of the package structure, so as to prevent and/or reduce warpage of the package structure. The reliability and performance of the package structure are improved. In some embodiments, the carrier substrate100has a high strength and a low coefficient of thermal expansion (CTE). For example, the carrier substrate100has a coefficient of thermal expansion that is smaller than about 4 ppm, and the carrier substrate100has a modulus that is greater than about 75 MPa.

The carrier substrate100may be made of or include a semiconductor material, a dielectric material, one or more other suitable materials, or a combination thereof. The semiconductor material may be made of or include silicon, germanium, silicon germanium, one or more other suitable semiconductor materials, or a combination thereof. In some embodiments, the carrier substrate100is a semiconductor substrate, such as a silicon wafer. In some embodiments, the carrier substrate100is a dielectric substrate, such as a glass wafer. In some embodiments, the main body of the carrier substrate100is a single layer structure. The single material layer may be made of a semiconductor material (such as silicon), a dielectric material (such as a glass material), one or more other suitable materials, or a combination thereof.

In some embodiments, multiple conductive structures104are formed in the carrier substrate100, as shown inFIG.1A. The conductive structures104may function as conductive vias. In some embodiments, the carrier substrate100is partially removed to form multiple openings. The openings may be formed using one or more photolithography processes and one or more etching processes.

Afterwards, a dielectric layer102is deposited over the carrier substrate100, as shown inFIG.1Ain accordance with some embodiments. The dielectric layer102extends along the sidewalls and bottoms of the openings. The dielectric layer102may be used to electrically isolate the carrier substrate100and the conductive structures104that will be formed later. The dielectric layer102may be made of or include silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, silicon carbide, one or more other suitable materials, or a combination thereof. The dielectric layer102may be deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, one or more other applicable processes, or a combination thereof.

A conductive material is then deposited over the carrier substrate100to partially or completely fill the openings of the carrier substrate100, as shown inFIG.1Ain accordance with some embodiments. The conductive material may be made of or include copper, aluminum, cobalt, tungsten, gold, titanium, platinum, one or more other suitable materials, or a combination thereof. The conductive material may be deposited using a physical vapor deposition (PVD) process, a CVD process, an ALD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

Afterwards, the conductive material is partially removed. As a result, the remaining portions of the conductive material form the conductive structures104, as shown inFIG.1A. A planarization process may be used to remove the portions of the conductive material outside of the openings. The remaining portions of the conductive material in the openings form the conductive structure104. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1A, an interconnection structure is formed over the carrier substrate100and the conductive structures104, in accordance with some embodiments. The interconnection structure includes multiple dielectric layers108and multiple conductive features106. The conductive features106may include conductive lines, conductive vias, and/or other suitable conductive structures. The conductive features106may be used to form electrical connection to the conductive structures104.

The dielectric layers108may be made of or include silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, silicon carbide, one or more other suitable materials, or a combination thereof. The conductive features106may be made of or include copper, aluminum, cobalt, tungsten, gold, titanium, platinum, one or more other suitable materials, or a combination thereof. The formation of the interconnection structure may involve multiple deposition processes, multiple patterning processes, and multiple planarization processes.

As shown inFIG.1A, the interconnection structure may further include a passivation layer110, conductive layers112, and conductive pads114. Each of the conductive pads114may be electrically connected to the respective conductive structures104through the respective conductive layer112and the respective conductive features106.

As shown inFIG.1B, an insulating layer116ais formed over the passivation layer110and the conductive pads114, in accordance with some embodiments. In some embodiments, the insulating layer116ais a polymer-containing layer. The insulating layer116amay be made of or include one or more polymer materials. The polymer material(s) may include polybenzoxazole (PBO), polyimide (PI), epoxy-based resin, one or more other suitable polymer materials, or a combination thereof. In some embodiments, the polymer material is photosensitive. A photolithography process may therefore be used to form openings118with desired patterns in the insulating layer116a. The openings118expose the conductive pads114, as shown inFIG.1B.

As shown inFIG.1C, conductive features120aare formed over the insulating layer116a, in accordance with some embodiments. The conductive features120aextend into the openings118to form electrical connection to the conductive pads114. The conductive features120amay be made of or include copper, cobalt, tin, titanium, gold, platinum, aluminum, tungsten, one or more other suitable materials, or a combination thereof. The conductive features120amay be formed using an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1D, multiple insulating layers116b-116eand multiple conductive features120b-120eare formed over the insulating layer116aand the conductive features120a, in accordance with some embodiments. The material and formation method of the insulating layers116b-116emay be the same as or similar to those of the insulating layer116a. The material and formation method of the conductive features120b-120emay be the same as or similar to those of the conductive features120a.

As shown inFIG.1E, an insulating layer116fand conductive features120fare formed over the insulating layer116eand the conductive features120e, in accordance with some embodiments. The insulating layers116a-116fand the conductive features120a-120ftogether form a redistribution structure121. As shown inFIG.1E, some conductive features in the redistribution structure121are conductive vias. In some embodiments, the upper portion of the conductive via is wider than the lower portion of the conductive via, as shown inFIG.1E.

The insulating layer116fmay function as a topmost insulating layer of the redistribution structure121. The conductive features120fmay function as conductive pads and/or conductive pillars of the redistribution structure121. For example, the conductive features120fare used as under bump metallization (UBM) pads. The material and formation method of the insulating layer116fmay be the same as or similar to those of the insulating layer116a. The material and formation method of the conductive features120fmay be the same as or similar to those of the conductive features120a.

As shown inFIG.1E, conductive connectors122are formed over the conductive features120f, in accordance with some embodiments. In some embodiments, the conductive connectors122are made of or include a solder material. The solder material may be tin-containing material. The tin-containing material may further include copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination thereof. In some other embodiments, the solder material is lead-free. A thermal reflow operation may be performed to the conductive connectors122. As a result, the reflowed conductive connectors122may have rounded profiles.

As shown inFIG.1F, multiple chip structures (or chip-containing structures)124A,124B,124C, and124D are disposed over the redistribution structure121formed over the carrier substrate100, in accordance with some embodiments.FIG.2is a top view of a portion of a package structure, in accordance with some embodiments.FIG.2shows the distribution of the chip structures124disposed over the carrier substrate100. In some embodiments, some of the chip structures124have different sizes and/or profiles, as shown inFIG.2.

In some embodiments, the chip structures124A-124D are bonded onto the conductive features120fof the redistribution structure121through conductive connectors128. In some embodiments, each of the chip structures124A-124D includes conductive pillars126with solder elements formed thereon. The chip structures124A-124D are picked and placed onto the redistribution structure121. In some embodiments, the solder elements of the chip structures124A-124D and the conductive connectors122are reflowed together. As a result, the conductive connectors128are formed. The chip structures124A-124D and the redistribution structure121are bonded together through the conductive connectors128.

The chip structures124A-124D may be semiconductor dies and/or packages including one or more semiconductor dies that are encapsulated or protected. In some embodiments, some of the semiconductor dies are system-on-chip (SoC) chips that include multiple functions. In some embodiments, the back sides of the semiconductor dies face upwards with the front sides of the semiconductor dies facing the redistribution structure121. In some embodiments, some of the semiconductor dies include memory devices such as high bandwidth memory (HBM) devices.

Each of the chip structures124A-124D may include a semiconductor substrate, an interconnection structure125, and the conductive pillars126. In some embodiments, various device elements are formed in and/or on the semiconductor substrate of the chip structures124A-124D. Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high-frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, or other suitable elements.

The device elements are interconnected to form integrated circuit devices through conductive features formed in the interconnection structure125. The interconnection structure125may include multiple dielectric layers and multiple conductive features. The conductive features may include multiple conductive lines, conductive contacts, and conductive vias. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, other applicable types of devices, or a combination thereof.

As shown inFIG.1F, an underfill material130is formed to surround and protect the conductive connectors128, in accordance with some embodiments. A portion of the underfill material130may extend into a space between the nearby chip structures124A-124D. The underfill material130may be made of or include a polymer material, such as an epoxy-based resin with fillers dispersed therein. The fillers may include fibers (such as silica fibers and/or carbon-containing fibers), particles (such as silica particles and/or carbon-containing particles), or a combination thereof.

As shown inFIG.1F, a protective layer132is formed over the redistribution structure121to surround and protect the chip structures124A-124D, in accordance with some embodiments. In some embodiments, the protective layer132is in physical contact with the redistribution structure121. In some embodiments, the protective layer132is separated from the conductive connectors128below the chip structures124A-124D by the underfill material130.

However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the underfill material130is not formed. In these cases, the protective layer132may be in direct contact with the conductive connectors128below the chip structures124A-124D.

In some embodiments, the protective layer132is made of or includes an insulating material such as a molding material. The molding material may include a polymer material, such as an epoxy-based resin with fillers dispersed therein. The fillers may include fibers (such as silica fibers and/or carbon-containing fibers), particles (such as silica particles and/or carbon-containing particles), or a combination thereof. In some embodiments, the distribution density of the fillers in the protective layer132is greater than the distribution density of the fillers in the underfill material130. The profiles, sizes, and/or materials of the fillers in the protective layer132and the underfill material130may be different from each other.

In some embodiments, a molding material (such as a liquid molding material) is introduced or injected to cover the redistribution structure121and the chip structures124A-124D. In some embodiments, a thermal process is then used to cure the liquid molding material and to transform it into the protective layer132. In some embodiments, a planarization process is performed to the protective layer132to improve the flatness of the protective layer132. For example, the planarization process may include a grinding process, a CMP process, a dry polishing process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1G, a temporary support substrate134is attached to the protective layer132, in accordance with some embodiments. The temporary support substrate134may be made of a dielectric material, a semiconductor material, a metal material, one or more other suitable materials, or a combination thereof. For example, the temporary support substrate134is a silicon wafer or a glass wafer. In some embodiments, an adhesive tape or adhesive glue may be used to attach the temporary support substrate134to the protective layer132.

As shown inFIG.1G, the carrier substrate100is partially removed to expose the conductive structures104, in accordance with some embodiments. The conductive structures104may penetrate through the carrier substrate100after the carrier substrate100is partially removed. The conductive structures104may completely penetrate through opposite surfaces of the carrier substrate100. The conductive structures104may thus function as through substrate vias (TSVs) that form electrical connections between elements disposed over opposite surfaces of the carrier substrate100. In some embodiments, a thinning process is used to partially remove the carrier substrate100. The thinned carrier substrate100may function as a reinforced plate that enhances the strength of the package structure, so as to prevent and/or reduce warpage of the package structure. The reliability and performance of the package structure are improved. The thinning process may include a CMP process, a grinding process, an etching process, a dry polishing process, one or more other applicable processes, or a combination thereof.

The structure may be turned upside down with the bottom surface of the carrier substrate100facing upwards. Afterwards, the thinning process is applied on the surface to thin down the carrier substrate100. As a result, the conductive structures104are exposed. In some embodiments, the conductive structures104slightly protrude from the surface of the carrier substrate100after the thinning of the carrier substrate100. In some other embodiments, the ends of the conductive structures104are substantially level with the surface of the carrier substrate100after the thinning of the carrier substrate100.

As shown inFIG.1H, a protective layer136is formed over the surface of the carrier substrate100, in accordance with some embodiments. The material and formation method of the protective layer136may be the same as or similar to those of the insulating layer116f. Afterwards, the protective layer136is patterned to form openings that expose the conductive structures104.

Afterwards, conductive pads138are formed in the openings to form electrical connection to the conductive structures104, as shown inFIG.1Hin accordance with some embodiments. The material and formation method of the conductive pads138may be the same as or similar to those of the conductive features120f. For example, the conductive pads138are used as UBM pads.

As shown inFIG.1H, conductive connectors140are formed on the conductive pads138, in accordance with some embodiments. The material and formation method of the conductive connectors140may be the same as or similar to those of the conductive connectors122. In some embodiments, each of the conductive connectors140is wider and larger than each of the conductive connectors122.

As shown inFIG.1I, the structure inFIG.1His attached onto a carrier tape142, in accordance with some embodiments. Afterwards, the temporary support substrate134is removed, and the protective layer132is further thinned to expose one or more of the chip structures124A-124D, as shown inFIG.1Iin accordance with some embodiments. In some embodiments, each of the chip structures124A-124D is exposed after the thinning of the protective layer132. The heat dissipation of the chip structures124A-124D may thus become better. The performance and reliability of the chip structures124A-124D are improved. The thinning process may include a grinding process, an etching process, one or more other applicable processes, or a combination thereof.

In some embodiments, a sawing process is used to cut through the structure shown inFIG.1Iinto multiple separate package structures. These package structures may then be integrated into other larger package structures.

However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the sawing process is not performed to separate the structure inFIG.1Iinto multiple smaller package structures. The entirety of the wafer-level package structure may then be integrated into a large package structure.

As shown inFIG.1J, the package structure shown inFIG.1Iis picked from the carrier tape142and placed over a package substrate144, in accordance with some embodiments. In some embodiments, the package structure shown inFIG.1Iis bonded to the package substrate144through conductive connectors148. In some embodiments, the package substrate144includes multiple conductive pads146with solder elements formed thereon and multiple conductive bumps150formed on the opposite surface of the package substrate144. The package substrate144may include one or more polymer layers and multiple conductive features. These conductive features form electrical connection between the conductive pads146and the conductive bumps150. The package substrate144may include a core portion. The core portion may include organic materials such as materials that can be easily laminated. In some embodiments, the core portion may include a single-sided or double-sided copper clad laminate, epoxy, resin, glass fiber, molding compound, plastic (such as polyvinylchloride (PVC), acrylonitril, butadiene and styrene (ABS), polypropylene (PP), polyethylene (PE), polystyrene (PS), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonates (PC), polyphenylene sulfide (PPS)), one or more other suitable elements, or a combination thereof. Conductive vias may extend through the core portion to provide electrical connections between elements disposed on either side of the core portion.

Afterwards, the package structure shown inFIG.1Iis disposed over the package substrate144such that the conductive connectors140are in physical contact with the solder elements formed on the conductive pads146. Afterwards, a thermal reflow process is used. As a result, the conductive connectors140and the solder elements are reflowed together to form the conductive connectors148.

In some embodiments, an underfill material152is formed to surround and protect the conductive connectors148, in accordance with some embodiments. The material and formation method of the underfill material152may be the same as or similar to those of the underfill material130inFIG.1F.

The redistribution structure121and the package substrate144may have a greater thermal expansion difference. As more and more chip structures are designed to be placed over the redistribution structure121, the redistribution structure121is correspondingly formed to have a large area to receive these chip structures. As a result, the risk of warpage is further increased after bonding with the package substrate144, which may negatively affect the reliability and performance of the package structure.

In some embodiments, the carrier substrate100(that functions as a reinforced plate) is substantially as wide as the redistribution structure121. Due to the carrier substrate100having high strength and a low coefficient of thermal expansion, the thermal expansion difference between the package substrate144and the elements above the carrier substrate100may be limited. The risk of warpage is significantly reduced or prevented. Therefore, the reliability and performance of the package structure are greatly improved.

As shown inFIG.1J, the carrier substrate100has a thickness T1, and the redistribution structure121has a thickness T2. In some embodiments, the thickness T2is greater than the thickness T1. In some other embodiments, the thickness T2is substantially equal to the thickness T1. The thickness T1of the carrier substrate100may be in a range from about 10 μm to about 100 μm. In some embodiments, the thickness ratio (T1/T2) of the thickness T1to the thickness T2is in a range from about 0.5 to about 1.

In some cases, if the thickness ratio (T1/T2) is smaller than about 0.5, the carrier substrate100might not be thickness enough to serve as a reinforced plate. As a result, there might be a high degree of warpage of the package structure, which would negatively affect the reliability and performance of the package structure. In some other cases, if the thickness ratio (T1/T2) is greater than about 1, the carrier substrate100might be too thick. If the carrier substrate100is too thick, high stress might be generated. As a result, the conductive connectors148might be damaged or negatively affected.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.3is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. In some embodiments, a package structure similar to the structure shown inFIG.1Jis formed. A thermal conductive structure154is formed over the chip structures124A-124D, as shown inFIG.3in accordance with some embodiments. The thermal conductive structure154may be made of or include copper, aluminum, gold, one or more other suitable materials, or a combination thereof. In some embodiments, the thermal conductive structure154is in physical contact with the chip structures124A-124D. In some other embodiments, a thermal conductive glue may be used to attach the thermal conductive structure154to the chip structures124A-124D. Due to the thermal conductive structure154, the heat dissipation of the chip structures124A-124D may be improved, which results in better performance and reliability of the chip structures124A-124D.

Many variations and/or modifications can be made to embodiments of the disclosure. For example, in some embodiments, the redistribution structure is formed directly on the carrier substrate. There is no interconnection structure formed between the redistribution structure and the carrier substrate.

FIGS.4A-4Jare cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. As shown inFIG.4A, a carrier substrate100is received or provided. The material of the carrier substrate100inFIG.4Amay be the same as or similar to that of the carrier substrate100inFIG.1A. Similar to the embodiments inFIG.1A, conductive structures104and a dielectric layer102are formed, as shown inFIG.4Ain accordance with some embodiments. The materials and formation methods of the conductive structures104and the dielectric layer102inFIG.4Aare the same as or similar to those of the conductive structures104and the dielectric layer102inFIG.1A.

As shown inFIG.4B, conductive pads114and an insulating layer116aare formed directly on the carrier substrate100, in accordance with some embodiments. The material and formation method of the conductive pads114inFIG.4Bmay be the same as or similar to those of the conductive pads114inFIG.1A. The material and formation method of the insulating layer116ainFIG.4Bmay be the same as or similar to those of the insulating layer116ainFIG.1B. Unlike the embodiments illustrated inFIG.1A, the elements106,108,110, and112are not formed in the embodiments illustrated inFIG.4B. In some embodiments, each of the conductive pads114is in physical contact with the respective conductive structure104. Afterwards, the insulating layer116awith multiple openings118are formed over the carrier substrate100and the conductive pads114. The openings118expose the conductive pads114. In some embodiments, the insulating layer116ais in physical contact with the dielectric layer102formed on the carrier substrate100and the conductive pads114. In some other embodiments, the portion of the dielectric layer102on the top surface of the carrier substrate100is removed during the formation of the conductive structures104. In these cases, the insulating layer116amay be in physical contact with the carrier substrate100.

As shown inFIG.4C, conductive features120aare formed over the insulating layer116a, in accordance with some embodiments. Each of the conductive features120amay extend into the respective opening118to form electrical connection to the respective conductive structure104through the respective conductive pad114. The material and formation method of the conductive features120ainFIG.4Cmay be the same as or similar to those of the conductive features120ainFIG.1C.

As shown inFIG.4D, multiple insulating layers116b-116eand multiple conductive features120b-120eare formed over the insulating layer116aand the conductive features120a, in accordance with some embodiments. The material and formation method of the insulating layers116b-116emay be the same as or similar to those of the insulating layer116a. The material and formation method of the conductive features120b-120emay be the same as or similar to those of the conductive features120a.

As shown inFIG.4E, an insulating layer116fand conductive features120fare formed over the insulating layer116eand the conductive features120e, in accordance with some embodiments. The insulating layers116a-116fand the conductive features120a-120ftogether form a redistribution structure121. The insulating layer116fmay function as a topmost insulating layer of the redistribution structure121. The conductive features120fmay function as conductive pads and/or conductive pillars of the redistribution structure121. For example, the conductive features120fare used as under bump metallization (UBM) pads. The material and formation method of the insulating layer116fmay be the same as or similar to those of the insulating layer116a. The material and formation method of the conductive features120fmay be the same as or similar to those of the conductive features120a.

As shown inFIG.4E, conductive connectors122are formed over the conductive features120f, in accordance with some embodiments. The material and formation method of the conductive connectors122inFIG.4Emay be the same as or similar to those of the conductive connectors122inFIG.1E.

As shown inFIG.4F, similar to the embodiments shown inFIG.1F, multiple chip structures including chip structures124A,124B,124C, and124D are disposed over the redistribution structure121formed over the carrier substrate100, in accordance with some embodiments. Similar to the chip structures124A-124D inFIG.1F, the chip structures124A-124D inFIG.4Fmay be semiconductor dies and/or packages including one or more semiconductor dies that are encapsulated or protected.

In some embodiments, the chip structures124A-124D are bonded onto the conductive features120fof the redistribution structure121through conductive connectors128. The material and formation method of the conductive connectors128inFIG.4Fmay be the same as or similar to those of the conductive connectors128inFIG.1F.

As shown inFIG.4F, an underfill material130is formed to surround and protect the conductive connectors128, in accordance with some embodiments. The material and formation method of the underfill material130inFIG.4Fmay be the same as or similar to those of the underfill material130inFIG.1F.

As shown inFIG.4F, a protective layer132is formed over the redistribution structure121to surround and protect the chip structures124A-124D, in accordance with some embodiments. The material and formation method of the protective layer132inFIG.4Fmay be the same as or similar to those of the protective layer132inFIG.1F.

As shown inFIG.4G, similar to the embodiments illustrated inFIG.1G, a temporary support substrate134is attached to the protective layer132, in accordance with some embodiments. The material of the temporary support substrate134inFIG.4Gmay be the same as or similar to that of the temporary support substrate134inFIG.1G.

As shown inFIG.4G, similar to the embodiments illustrated inFIG.1G, the carrier substrate100is partially removed to expose the conductive structures104, in accordance with some embodiments. The conductive structures104may penetrate through the carrier substrate100after the carrier substrate100is partially removed. In some embodiments, a thinning process is used to partially remove the carrier substrate100. The thinned carrier substrate100may function as a reinforced plate that enhances the strength of the package structure, so as to prevent and/or reduce warpage of the package structure. The reliability and performance of the package structure are improved.

As shown inFIG.4H, a protective layer136, conductive pads138, and conductive connectors140are formed, in accordance with some embodiments. The material and formation method of the protective layer136, the conductive pads138, and the conductive connectors140inFIG.4Hmay be the same as or similar to those of the protective layer136, conductive pads138, and conductive connectors140inFIG.1H.

As shown inFIG.4I, the structure inFIG.4His attached onto a carrier tape142, in accordance with some embodiments. Afterwards, the temporary support substrate134is removed, and the protective layer132is further thinned to expose one or more of the chip structures124A-124D, as shown inFIG.4Iin accordance with some embodiments. In some embodiments, each of the chip structures124A-124D is exposed after the thinning of the protective layer132.

In some embodiments, a sawing process is used to cut through the structure shown inFIG.4Iinto multiple separate package structures. These package structures may then be integrated into other larger package structures.

However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the sawing process is not performed to separate the structure inFIG.4Iinto multiple smaller package structures. The entirety of the wafer-level package structure may then be integrated into a large package structure.

As shown inFIG.4J, the package structure shown inFIG.4Iis picked from the carrier tape142and placed over a package substrate144, in accordance with some embodiments. The package substrate144inFIG.4Jmay be the same as or similar to the package substrate144inFIG.1J. In some embodiments, the package structure shown inFIG.4Iis bonded to the package substrate144through conductive connectors148. The material and formation method of the conductive connectors148inFIG.4Jmay be the same as or similar to those of the conductive connectors148inFIG.1J.

In some embodiments, an underfill material152is formed to surround and protect the conductive connectors148, in accordance with some embodiments. The material and formation method of the underfill material152inFIG.4Jmay be the same as or similar to those of the underfill material130inFIG.1F.

The redistribution structure121and the package substrate144may have a greater thermal expansion difference. As more and more chip structures are designed to be placed over the redistribution structure121, the redistribution structure121is correspondingly formed to have a large area to receive these chip structures. As a result, the risk of warpage is further increased after bonding with the package substrate144, which may negatively affect the reliability and performance of the package structure. Due to the carrier substrate100having high strength and a low coefficient of thermal expansion, the thermal expansion difference between the package substrate144and the elements above the carrier substrate100may be limited. The risk of warpage is significantly reduced or prevented. Therefore, the reliability and performance of the package structure are greatly improved.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.5is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. In some embodiments, a package structure similar to the structure shown inFIG.4Jis formed. Similar to the embodiments shown inFIG.3, a thermal conductive structure154is formed over the chip structures124A-124D, as shown inFIG.5in accordance with some embodiments. The thermal conductive structure154may be made of or include copper, aluminum, gold, one or more other suitable materials, or a combination thereof. In some embodiments, the thermal conductive structure154is in physical contact with the chip structures124A-124D. In some other embodiments, a thermal conductive glue may be used to attach the thermal conductive structure154to the chip structures124A-124D. Due to the thermal conductive structure154, the heat dissipation of the chip structures124A-124D may be improved, which would improve the performance and reliability of the package structure.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, two or more redistribution structures are formed over opposite surfaces of the carrier substrate.

FIGS.6A-6Eare cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. As shown inFIG.6A, a structure the same as or similar to that shown inFIG.1G or4Gis formed, in accordance with some embodiments.

As shown inFIG.6B, a second redistribution structure621is formed over the carrier substrate100, in accordance with some embodiments. As a result, the carrier substrate100is between the redistribution structure121and the second redistribution structure621. Similar to the redistribution structure121, the second redistribution structure621includes multiple insulating layers602and multiple conductive features604. The material and formation method of the second redistribution structure621may be the same as or similar to those of the redistribution structure121.

As shown inFIG.6B, some conductive features in the redistribution structure121are conductive vias. In some embodiments, the upper portion of the conductive via is wider than the lower portion of the conductive via, as shown inFIG.6B. As shown inFIG.6B, some conductive features in the second redistribution structure621are conductive vias. In some embodiments, in the second redistribution structure621, the lower portion of the conductive via is wider than the upper portion of the conductive via, as shown inFIG.6B.

As shown inFIG.6C, a protective layer136, conductive pads138, and conductive connectors140are formed, in accordance with some embodiments. The material and formation method of the protective layer136, the conductive pads138, and the conductive connectors140inFIG.6Cmay be the same as or similar to those of the protective layer136, conductive pads138, and conductive connectors140inFIG.1H.

As shown inFIG.6D, the structure inFIG.6Cis attached onto a carrier tape142, in accordance with some embodiments. Afterwards, the temporary support substrate134is removed, and the protective layer132is further thinned to expose one or more of the chip structures124A-124D, as shown inFIG.6Din accordance with some embodiments. In some embodiments, each of the chip structures124A-124D is exposed after the thinning of the protective layer132.

In some embodiments, a sawing process is used to cut through the structure shown inFIG.6Dinto multiple separate package structures. These package structures may then be integrated into other larger package structures.

However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the sawing process is not performed to separate the structure inFIG.6Dinto multiple smaller package structures. The entirety of the wafer-level package structure may then be integrated into a large package structure.

As shown inFIG.6E, the package structure shown inFIG.6Dis picked from the carrier tape142and placed over a package substrate144, in accordance with some embodiments. The package substrate144inFIG.6Emay be the same as or similar to the package substrate144inFIG.1J. In some embodiments, the package structure shown inFIG.6Dis bonded to the package substrate144through conductive connectors148. The material and formation method of the conductive connectors148inFIG.6Emay be the same as or similar to those of the conductive connectors148inFIG.1J.

In some embodiments, an underfill material152is formed to surround and protect the conductive connectors148, in accordance with some embodiments. The material and formation method of the underfill material152may be the same as or similar to those of the underfill material130inFIG.1F.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.7is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. In some embodiments, a package structure similar to the structure shown inFIG.6Eis formed. Similar to the embodiments shown inFIG.3, a thermal conductive structure154is formed over the chip structures124A-124D, as shown inFIG.7in accordance with some embodiments. The thermal conductive structure154may be made of or include copper, aluminum, gold, one or more other suitable materials, or a combination thereof. In some embodiments, the thermal conductive structure154is in physical contact with the chip structures124A-124D. In some other embodiments, a thermal conductive glue may be used to attach the thermal conductive structure154to the chip structures124A-124D. Due to the thermal conductive structure154, the heat dissipation of the chip structures124A-124D may be improved, which facilitates the performance and reliability of the package structure.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.8is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. In some embodiments, a package structure similar to the structure shown inFIG.7is formed. Unlike the embodiments illustrated inFIG.7, the elements106,108,110, and112are not formed in the embodiments illustrated inFIG.8.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the carrier substrate is made of an insulating material such as glass. The dielectric layer102may not need to be formed along the sidewalls and bottoms of the conductive structures104.

FIGS.9A-9Kare cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. As shown inFIG.9A, a carrier substrate900is received or provided. In some embodiments, the carrier substrate900is a dielectric substrate, such as a glass wafer. The carrier substrate900may be made of or include silicon oxide, aluminum oxide, titanium oxide, one or more other suitable materials, or a combination thereof. In some embodiments, the main body of the carrier substrate900is a single layer structure.

As shown inFIG.9A, the carrier substrate900is partially removed to form openings902, in accordance with some embodiments. The openings902may be formed using an energy beam drilling process, a mechanical drilling process, photolithography and etching processes, one or more other applicable processes, or a combination thereof. The energy beam drilling process may include a laser beam drilling process, an electron beam drilling process, an ion beam drilling process, a plasma beam drilling process, the like, or a combination thereof.

As shown inFIG.9B, similar to the embodiments illustrated inFIG.1A, conductive structures904are formed, in accordance with some embodiments. In some embodiments, since the dielectric layer102is not formed, the conductive structures904fill the openings902and are in physical contact with the carrier substrate900. The material and formation method of the conductive structures904may be the same as or similar to the conductive structures104inFIG.1A. In some embodiments, the conductive structures904slightly protrude from the top surface of the carrier substrate900. In some other embodiments, the top ends of the conductive structures904are substantially level with the top surface of the carrier substrate900.

As shown inFIG.9C, an insulating layer906awith multiple openings908is formed over the carrier substrate900, in accordance with some embodiments. The openings908expose the conductive structures904. In some embodiments, the insulating layer906ais in physical contact with the carrier substrate900. The material and formation method of the insulating layer906amay be the same as or similar to those of the insulating layer116ainFIG.1B.

As shown inFIG.9D, conductive features910aand910band an insulating layer906bare formed, in accordance with some embodiments. The conductive features910amay function as conductive pads that form electrical connection to the conductive structures904in the carrier substrate900. The material and formation method of the conductive features910aand910binFIG.9Dmay be the same as or similar to those of the conductive features120ainFIG.1C. The material and formation method of the insulating layer906bmay be the same as or similar to those of the insulating layer906a.

As shown inFIG.9E, multiple insulating layers906c-906fand multiple conductive features910c-910fare formed, in accordance with some embodiments. The material and formation method of the insulating layers906c-906fmay be the same as or similar to those of the insulating layer116ainFIG.1B. The material and formation method of the conductive features910c-910fmay be the same as or similar to those of the conductive features120ainFIG.1C.

As shown inFIG.9F, an insulating layer906gand conductive features910gare formed, in accordance with some embodiments. The insulating layers906a-906gand the conductive features910a-910gtogether form a redistribution structure914. The insulating layer906gmay function as a topmost insulating layer of the redistribution structure914. The conductive features910gmay function as conductive pads and/or conductive pillars of the redistribution structure914. For example, the conductive features910gare used as under bump metallization (UBM) pads. The material and formation method of the insulating layer906gmay be the same as or similar to those of the insulating layer116ainFIG.1B. The material and formation method of the conductive features910gmay be the same as or similar to those of the conductive features120ainFIG.1C.

As shown inFIG.9F, conductive connectors912are formed over the conductive features910g, in accordance with some embodiments. The material and formation method of the conductive connectors912inFIG.9Fmay be the same as or similar to those of the conductive connectors122inFIG.1E.

As shown inFIG.9G, similar to the embodiments shown inFIG.1F, multiple chip structures including chip structures916A,916B,916C, and916D are disposed over the redistribution structure914formed over the carrier substrate900, in accordance with some embodiments. Similar to the chip structures124A-124D inFIG.1F, the chip structures916A-916D inFIG.9Gmay be semiconductor dies and/or packages including one or more semiconductor dies that are encapsulated or protected.

In some embodiments, the chip structures916A-916D are bonded onto the conductive features910gof the redistribution structure914through conductive connectors920. In some embodiments, each of the chip structures916A-916D includes conductive pillars918with solder elements formed thereon. The chip structures916A-916D are picked and placed onto the redistribution structure914. In some embodiments, the solder elements of the chip structures916A-916D and the conductive connectors912are reflowed together. As a result, the conductive connectors920are formed. The chip structures916A-916D and the redistribution structure914are bonded together through the conductive connectors920.

As shown inFIG.9G, an underfill material922is formed to surround and protect the conductive connectors920, in accordance with some embodiments. The material and formation method of the underfill material922may be the same as or similar to those of the underfill material130inFIG.1F.

As shown inFIG.9G, a protective layer924is formed over the redistribution structure914to surround and protect the chip structures916A-916D, in accordance with some embodiments. The material and formation method of the protective layer924may be the same as or similar to those of the protective layer132inFIG.1F.

As shown inFIG.9H, similar to the embodiments illustrated inFIG.1G, a temporary support substrate926is attached to the protective layer924, in accordance with some embodiments. The material of the temporary support substrate926may be the same as or similar to that of the temporary support substrate134inFIG.1G.

As shown inFIG.9H, similar to the embodiments illustrated inFIG.1G, the carrier substrate900is partially removed to expose the conductive structures904, in accordance with some embodiments. The conductive structures904may penetrate through the carrier substrate900after the carrier substrate900is partially removed. In some embodiments, the conductive structures904slightly protrude below the bottom surface of the carrier substrate900. In some other embodiments, the bottom ends of the conductive structures904are substantially level with the bottom surface of the carrier substrate900. In some embodiments, a thinning process is used to partially remove the carrier substrate900. The thinned carrier substrate900may function as a reinforced plate that enhances the strength of the package structure, so as to prevent and/or reduce warpage of the package structure. The reliability and performance of the package structure are improved.

As shown inFIG.9I, a protective layer928, conductive pads930, and conductive connectors932are formed, in accordance with some embodiments. The material and formation method of the protective layer928, the conductive pads930, and the conductive connectors932may be the same as or similar to those of the protective layer136, conductive pads138, and conductive connectors140inFIG.1H.

As shown inFIG.9J, the structure inFIG.9Iis attached onto a carrier tape934, in accordance with some embodiments. Afterwards, the temporary support substrate926is removed, and the protective layer924is further thinned to expose one or more of the chip structures916A-916D, as shown inFIG.9Jin accordance with some embodiments. In some embodiments, each of the chip structures916A-916D is exposed after the thinning of the protective layer924.

In some embodiments, a sawing process is used to cut through the structure shown inFIG.9Jinto multiple separate package structures. These package structures may then be integrated into other larger package structures.

However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the sawing process is not performed to separate the structure in FIG.9J into multiple smaller package structures. The entirety of the wafer-level package structure may then be integrated into a large package structure.

As shown inFIG.9K, the package structure shown inFIG.9Jis picked from the carrier tape934and placed over a package substrate936, in accordance with some embodiments. The package substrate936may be the same as or similar to the package substrate144inFIG.1J. The package substrate936further includes multiple conductive bumps940. The conductive bumps940may be used to connect another element such as a circuit board. In some embodiments, the package structure shown inFIG.9Jis bonded to the package substrate936through conductive connectors938. The material and formation method of the conductive connectors938may be the same as or similar to those of the conductive connectors148inFIG.1J.

In some embodiments, an underfill material942is formed to surround and protect the conductive connectors938, in accordance with some embodiments. The material and formation method of the underfill material942may be the same as or similar to those of the underfill material130inFIG.1F.

The redistribution structure914and the package substrate936may have a greater thermal expansion difference. As more and more chip structures are designed to be placed over the redistribution structure914, the redistribution structure914is correspondingly formed to have a large area to receive these chip structures. As a result, the risk of warpage is further increased after bonding with the package substrate936, which may negatively affect the reliability and performance of the package structure. Due to the carrier substrate900having high strength and a low coefficient of thermal expansion, the thermal expansion difference between the package substrate936and the elements above the carrier substrate900may be limited. The risk of warpage is significantly reduced or prevented. Therefore, the reliability and performance of the package structure are greatly improved.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.10is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. In some embodiments, a package structure similar to the structure shown inFIG.9Kis formed. Similar to the embodiments shown inFIG.3, a thermal conductive structure154is formed over the chip structures916A-916D, as shown inFIG.10in accordance with some embodiments. The thermal conductive structure154may be made of or include copper, aluminum, gold, one or more other suitable materials, or a combination thereof. In some embodiments, the thermal conductive structure154is in physical contact with the chip structures916A-916D. In some other embodiments, a thermal conductive glue may be used to attach the thermal conductive structure154to the chip structures916A-916D. Due to the thermal conductive structure154, the heat dissipation of the chip structures916A-916D may be improved, which would improve the performance and reliability of the package structure.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, two or more redistribution structures are formed over opposite surfaces of the carrier substrate.

FIGS.11A-11Eare cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. As shown inFIG.11A, a structure the same as or similar to that shown inFIG.9His formed, in accordance with some embodiments.

As shown inFIG.11B, a second redistribution structure951is formed over the carrier substrate900, in accordance with some embodiments. As a result, the carrier substrate900is between the redistribution structure914and the second redistribution structure951. Similar to the redistribution structure914, the second redistribution structure951includes multiple insulating layers952and multiple conductive features954. The material and formation method of the second redistribution structure951may be the same as or similar to those of the redistribution structure914.

As shown inFIG.11B, some conductive features in the redistribution structure914are conductive vias. In some embodiments, the upper portion of the conductive via is wider than the lower portion of the conductive via, as shown inFIG.11B. As shown inFIG.11B, some conductive features in the second redistribution structure951are conductive vias. In some embodiments, in the second redistribution structure951, the lower portion of the conductive via is wider than the upper portion of the conductive via, as shown inFIG.11B.

As shown inFIG.11C, a protective layer956, conductive pads958, and conductive connectors960are formed, in accordance with some embodiments. The material and formation method of the protective layer956, the conductive pads958, and the conductive connectors960inFIG.11Cmay be the same as or similar to those of the protective layer136, conductive pads138, and conductive connectors140inFIG.1H.

As shown inFIG.11D, the structure inFIG.11Cis attached onto a carrier tape962, in accordance with some embodiments. Afterwards, the temporary support substrate926is removed, and the protective layer924is further thinned to expose one or more of the chip structures916A-916D, as shown inFIG.11Din accordance with some embodiments. In some embodiments, each of the chip structures916A-916D is exposed after the thinning of the protective layer924.

In some embodiments, a sawing process is used to cut through the structure shown inFIG.11Dinto multiple separate package structures. These package structures may then be integrated into other larger package structures.

However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the sawing process is not performed to separate the structure inFIG.11Dinto multiple smaller package structures. The entirety of the wafer-level package structure may then be integrated into a large package structure.

As shown inFIG.11E, the package structure shown inFIG.11Dis picked from the carrier tape962and placed over a package substrate964, in accordance with some embodiments. The package substrate964inFIG.11Emay be the same as or similar to the package substrate144inFIG.1J. The package substrate964further includes multiple conductive bumps968. The conductive bumps968may be used to connect another element such as a circuit board. In some embodiments, the package structure shown inFIG.11Dis bonded to the package substrate964through conductive connectors966. The material and formation method of the conductive connectors966inFIG.11Emay be the same as or similar to those of the conductive connectors148inFIG.1J.

In some embodiments, an underfill material970is formed to surround and protect the conductive connectors966, in accordance with some embodiments. The material and formation method of the underfill material970may be the same as or similar to those of the underfill material130inFIG.1F.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.12is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. In some embodiments, a package structure similar to the structure shown inFIG.11Eis formed. Similar to the embodiments shown inFIG.3, a thermal conductive structure154is formed over the chip structures916A-916D, as shown inFIG.12in accordance with some embodiments. Due to the thermal conductive structure154, the heat dissipation of the chip structures916A-916D may be improved, which facilitates the performance and reliability of the package structure.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the conductive structures formed in the carrier substrate have slanted sidewalls. In some embodiments, a first portion of the conductive structure closer to the chip structures is wider than a second portion of the conductive structure closer to the package substrate.

FIGS.13A-13Bare cross-sectional views of various stages of a process for forming a portion of a package structure, in accordance with some embodiments. As shown inFIG.13A, a structure similar to the structure shown inFIG.1Ais formed. In some embodiments, the openings used for containing the conductive structures104and the dielectric layer102are formed to have slanted sidewalls. Therefore, the conductive structures104also have slanted sidewalls.

Afterwards, the processes similar to those illustrated inFIGS.1B-1Jare performed. As a result, the package structure shown inFIG.13Bis formed, in accordance with some embodiments. In some embodiments, each top end of the conductive structures104is wider than the respective bottom end of the respective conductive structure104.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, one or more device elements are formed in the carrier substrate100and/or900. In some embodiments, the device elements are passive device elements. In some embodiments, the device elements are capacitors such as deep trench capacitors.

FIG.14is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. In some embodiments, a structure similar to that shown inFIG.1Jis formed. In some embodiments, multiple capacitors C are formed in the carrier substrate100. In some embodiments, the capacitors C are formed before the formation of the conductive structures104. In some other embodiments, the capacitors C are formed after the formation of the conductive structures. In some embodiments, the capacitors C are formed before the formation of the redistribution structure121.

FIG.15is a cross-sectional view of a portion of a package structure, in accordance with some embodiments. In some embodiments,FIG.15is an enlarged cross-sectional view showing a portion of the carrier substrate100. In some embodiments, multiple capacitors C are formed in the carrier substrate100. The capacitors C may be deep trench capacitors.

In some embodiments, after the formation of the conductive structures104and before the formation of the redistribution structure121, the carrier substrate100is partially removed to form multiple trenches. Afterwards, a dielectric layer182, a first electrode layer184, a capacitor dielectric layer186, a second electrode layer188, and a dielectric filling layer190are sequentially deposited over the carrier substrate100to fill the trenches. Afterwards, a planarization process is used to remove the portions of these layers outside of the trenches. As a result, the remaining portions of these layers form the capacitors C. The capacitors may also be formed in the carrier substrate100or900of the structure shown inFIGS.3,4J,5,6E,7,8,9K,10,11E,12, and/or13B.

Embodiments of the disclosure form a package structure including multiple chip structures, a polymer-containing redistribution structure, and a reinforced plate. Multiple conductive structures that penetrate through the reinforced plate are formed to form electrical connection between devices elements formed on opposite surfaces of the reinforced plate. Due to the reinforced plate having high strength and a low coefficient of thermal expansion, the thermal expansion difference between the elements above and below the carrier substrate may be limited. The risk of warpage is significantly reduced or prevented. Therefore, the reliability and performance of the package structure are greatly improved.

In accordance with some embodiments, a method for forming a package structure is provided. The method includes forming a plurality of conductive structures in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has a plurality of polymer-containing layers and a plurality of conductive features. The method also includes bonding a plurality of chip structures over the redistribution structure and forming a protective layer over the redistribution structure to surround the chip structures. The method further includes forming a plurality of conductive connectors over a surface of the carrier substrate. The carrier substrate is between the redistribution structure and the conductive connectors.

In accordance with some embodiments, a method for forming a package structure is provided. The method includes forming a plurality of conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has a plurality of polymer-containing layers and a plurality of conductive features. The method also includes disposing a plurality of chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure.

In accordance with some embodiments, a package structure is provided. The package structure includes a reinforced plate and a plurality of conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure comprises a plurality of polymer-containing layers and a plurality of conductive features. The package structure further includes a plurality of chip structures over the redistribution structure and a protective layer surrounding the chip structures. In addition, the package structure includes a plurality of conductive connectors below a bottom surface of the reinforced plate. The reinforced plate is between the redistribution structure and the conductive connectors.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.