Patent ID: 12255242

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to three-dimensional memory devices including hammerhead-shaped word lines and methods of making thereof, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various structures including a multilevel memory structure, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices comprising a plurality of NAND memory strings.

The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.

Generally, a semiconductor die, or a semiconductor package, can include a memory chip. Each semiconductor package contains one or more dies (for example one, two, or four). The die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (typically one or two). Identical, concurrent operations can take place on each plane, although with some restrictions. Each plane contains a number of blocks, which are the smallest unit that can be erased by in a single erase operation. Each block contains a number of pages, which are the smallest unit that can be programmed, i.e., a smallest unit on which a read operation can be performed.

Referring toFIG.1, a first exemplary structure according to a first embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The first exemplary structure includes a substrate (9,10), which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer9and an optional semiconductor material layer10. The substrate semiconductor layer9maybe a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105S/cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105S/cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−6S/cm. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to have electrical conductivity greater than 1.0×105S/cm. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.

At least one semiconductor device700for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer9. The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure720can be formed by etching portions of the substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (750,752,754,758), each of which can include a gate dielectric750, a gate electrode (752,754), and a gate cap dielectric758. The gate electrode (752,754) may include a stack of a first gate electrode portion752and a second gate electrode portion754. At least one gate spacer756can be formed around the at least one gate structure (750,752,754,758) by depositing and anisotropically etching a dielectric liner. Active regions730can be formed in upper portions of the substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (750,752,754,758) as masking structures. Additional masks may be employed as needed. The active region730can include source regions and drain regions of field effect transistors. A first dielectric liner761and a second dielectric liner762can be optionally formed. Each of the first and second dielectric liners (761,762) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner761can be a silicon oxide layer, and the second dielectric liner762can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer770. In one embodiment the planarized top surface of the planarization dielectric layer770can be coplanar with a top surface of the dielectric liners (761,762). Subsequently, the planarization dielectric layer770and the dielectric liners (761,762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer9. As used herein, a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air).

The optional semiconductor material layer10, if present, can be formed on the top surface of the substrate semiconductor layer9prior to, or after, formation of the at least one semiconductor device700by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the substrate semiconductor layer9. The deposited semiconductor material can be any material that can be employed for the substrate semiconductor layer9as described above. The single crystalline semiconductor material of the semiconductor material layer10can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer170can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer770.

The region (i.e., area) of the at least one semiconductor device700is herein referred to as a peripheral device region200. The region in which a memory array is subsequently formed is herein referred to as a memory array region100. A contact region300for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region100and the peripheral device region200.

In one alternative embodiment, the peripheral device region200containing the at least one semiconductor device700for a peripheral circuitry may be located under the memory array region100in a CMOS under array configuration. In another alternative embodiment, the peripheral device region200may be located on a separate substrate which is subsequently bonded to the memory array region100.

Referring toFIG.2, a stack of an alternating plurality of first material layers (which can be insulating layers32) and second material layers (which can be sacrificial material layer42) is formed over the top surface of the substrate (9,10). As used herein, a “material layer” refers to a layer including a material throughout the entirety thereof. As used herein, an alternating plurality of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the first elements on both ends. The first elements may have the same thickness thereamongst, or may have different thicknesses. The second elements may have the same thickness thereamongst, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of the first material layers or with an instance of the second material layers, and may end with an instance of the first material layers or with an instance of the second material layers. In one embodiment, an instance of the first elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality.

Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulating layer32, and each second material layer can be a sacrificial material layer. In this case, the stack can include an alternating plurality of insulating layers32and sacrificial material layers42, and constitutes a prototype stack of alternating layers comprising insulating layers32and sacrificial material layers42.

The stack of the alternating plurality is herein referred to as an alternating stack (32,42). In one embodiment, the alternating stack (32,42) can include insulating layers32composed of the first material, and sacrificial material layers42composed of a second material different from that of insulating layers32. The first material of the insulating layers32can be at least one insulating material. As such, each insulating layer32can be an insulating material layer. Insulating materials that can be employed for the insulating layers32include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layers32can be silicon oxide.

The second material of the sacrificial material layers42is a sacrificial material that can be removed selective to the first material of the insulating layers32. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material.

The sacrificial material layers42may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layers42can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers42can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.

In one embodiment, the insulating layers32can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the insulating layers32can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulating layers32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the sacrificial material layers42can be formed, for example, CVD or atomic layer deposition (ALD).

The sacrificial material layers42can be suitably patterned so that conductive material portions to be subsequently formed by replacement of the sacrificial material layers42can function as electrically conductive electrodes, such as the control gate electrodes of the monolithic three-dimensional NAND string memory devices to be subsequently formed. The sacrificial material layers42may comprise a portion having a strip shape extending substantially parallel to the major surface7of the substrate.

The thicknesses of the insulating layers32and the sacrificial material layers42can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer32and for each sacrificial material layer42. The number of repetitions of the pairs of an insulating layer32and a sacrificial material layer42can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The sacrificial material layers42are replaced with electrically conductive layers that function as gate electrodes. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer42in the alternating stack (32,42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer42.

While the present disclosure is described employing an embodiment in which the spacer material layers are sacrificial material layers42that are subsequently replaced with electrically conductive layers, embodiments are expressly contemplated herein in which the sacrificial material layers are formed as electrically conductive layers. In this case, steps for replacing the spacer material layers with electrically conductive layers can be omitted.

Optionally, an insulating cap layer70can be formed over the alternating stack (32,42). The insulating cap layer70includes a dielectric material that is different from the material of the sacrificial material layers42. In one embodiment, the insulating cap layer70can include a dielectric material that can be employed for the insulating layers32as described above. In this case, the insulating cap layer70may be an additional insulating layer having a same material composition as the insulating layers32. The insulating cap layer70can have a greater thickness than each of the insulating layers32. The insulating cap layer70can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer70can be a silicon oxide layer.

Referring toFIG.3, stepped surfaces are formed at a peripheral region of the alternating stack (32,42), which is herein referred to as a terrace region. As used herein, “stepped surfaces” refer to a set of surfaces that include at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume from which portions of the alternating stack (32,42) are removed through formation of the stepped surfaces. A “stepped cavity” refers to a cavity having stepped surfaces.

The terrace region is formed in the contact region300, which is located between the memory array region100and the peripheral device region200containing the at least one semiconductor device for the peripheral circuitry. The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the substrate (9,10). In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

Each sacrificial material layer42other than a topmost sacrificial material layer42within the alternating stack (32,42) laterally extends farther than any overlying sacrificial material layer42within the alternating stack (32,42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32,42) that continuously extend from a bottommost layer within the alternating stack (32,42) to a topmost layer within the alternating stack (32,42).

Each vertical step of the stepped surfaces can have the height of one or more pairs of an insulating layer32and a sacrificial material layer. In one embodiment, each vertical step can have the height of a single pair of an insulating layer32and a sacrificial material layer42. In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd1such that each vertical step has the height of a plurality of pairs of an insulating layer32and a sacrificial material layer42, and the number of columns can be at least the number of the plurality of pairs. Each column of staircase can be vertically offset among one another such that each of the sacrificial material layers42has a physically exposed top surface in a respective column of staircases. In the illustrative example, two columns of staircases are formed for each block of memory stack structures to be subsequently formed such that one column of staircases provide physically exposed top surfaces for odd-numbered sacrificial material layers42(as counted from the bottom) and another column of staircases provide physically exposed top surfaces for even-numbered sacrificial material layers (as counted from the bottom). Configurations employing three, four, or more columns of staircases with a respective set of vertical offsets among the physically exposed surfaces of the sacrificial material layers42may also be employed. Each sacrificial material layer42has a greater lateral extent, at least along one direction, than any overlying sacrificial material layers42such that each physically exposed surface of any sacrificial material layer42does not have an overhang. In one embodiment, the vertical steps within each column of staircases may be arranged along the first horizontal direction hd1, and the columns of staircases may be arranged along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1may be perpendicular to the boundary between the memory array region100and the contact region300.

A retro-stepped dielectric material portion65(i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the retro-stepped dielectric material portion65. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the retro-stepped dielectric material portion65, the silicon oxide of the retro-stepped dielectric material portion65may, or may not, be doped with dopants such as B, P, and/or F.

Optionally, drain-select-level isolation structures72can be formed through the insulating cap layer70and a subset of the sacrificial material layers42located at drain select levels. The drain-select-level isolation structures72can be formed, for example, by forming drain-select-level isolation trenches and filling the drain-select-level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the insulating cap layer70.

Referring toFIGS.4A and4B, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70and the retro-stepped dielectric material portion65, and can be lithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region100and a second set of openings formed over the contact region300. The pattern in the lithographic material stack can be transferred through the insulating cap layer70or the retro-stepped dielectric material portion65, and through the alternating stack (32,42) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the alternating stack (32,42) underlying the openings in the patterned lithographic material stack are etched to form memory openings49and support openings19. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, is subsequently formed. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings49are formed through the insulating cap layer70and the entirety of the alternating stack (32,42) in the memory array region100. The support openings19are formed through the retro-stepped dielectric material portion65and the portion of the alternating stack (32,42) that underlie the stepped surfaces in the contact region300.

The memory openings49extend through the entirety of the alternating stack (32,42). The support openings19extend through a subset of layers within the alternating stack (32,42). The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack (32,42) can alternate to optimize etching of the first and second materials in the alternating stack (32,42). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings49and the support openings19can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.

The memory openings49and the support openings19can extend from the top surface of the alternating stack (32,42) to at least the horizontal plane including the topmost surface of the semiconductor material layer10. In one embodiment, an overetch into the semiconductor material layer10may be optionally performed after the top surface of the semiconductor material layer10is physically exposed at a bottom of each memory opening49and each support opening19. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the semiconductor material layer10may be vertically offset from the un-recessed top surfaces of the semiconductor material layer10by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings49and the support openings19can be coplanar with the topmost surface of the semiconductor material layer10.

Each of the memory openings49and the support openings19may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings49can be formed in the memory array region100. A two-dimensional array of support openings19can be formed in the contact region300. The substrate semiconductor layer9and the semiconductor material layer10collectively constitutes a substrate (9,10), which can be a semiconductor substrate. Alternatively, the semiconductor material layer10may be omitted, and the memory openings49and the support openings19can be extend to a top surface of the substrate semiconductor layer9.

FIGS.5A-5Hillustrate structural changes in a memory opening49, which is one of the memory openings49in the first exemplary structure ofFIGS.4A and4B. The same structural change occurs simultaneously in each of the other memory openings49and in each support opening19.

Referring toFIG.5A, a memory opening49in the first exemplary device structure ofFIGS.4A and4Bis illustrated. The memory opening49extends through the insulating cap layer70, the alternating stack (32,42), and optionally into an upper portion of the semiconductor material layer10. At this processing step, each support opening19can extend through the retro-stepped dielectric material portion65, a subset of layers in the alternating stack (32,42), and optionally through the upper portion of the semiconductor material layer10. The recess depth of the bottom surface of each memory opening with respect to the top surface of the semiconductor material layer10can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the sacrificial material layers42can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

Referring toFIG.5B, a graded silicon oxynitride layer51G is deposited over the physically exposed surfaces of the memory opening49and over the top surface of the insulating cap layer70by a conformal deposition process. The graded silicon oxynitride layer51G is a composite dielectric spacer layer51in which a dielectric material composition is not homogeneous. The graded silicon oxynitride layer51G may have a material composition of SiO2-2αN4α/3, in which the parameter α monotonically or strictly increases during deposition of the graded silicon oxynitride layer51G. The range of the value of the parameter α may be in a range from 0 to 1. In one embodiment, the value of the parameter α may be between 0 and 0.1 in the beginning of the deposition process, and the value of the parameter α may be between 0.9 and 1 at the end of the deposition process. Thus, the value of the parameter α may be 0 or greater than 0 in the beginning of the deposition process, and/or the value of the parameter α may be 1 or less than 1 at the end of the deposition process.

The graded silicon oxynitride layer51G may be forming by providing a silicon oxide layer by a conformal deposition process such as a low pressure chemical vapor deposition process. For example, tetraethylorthosilicate (TEOS) may be flowed into a deposition chamber under vacuum at a deposition temperature in a range from 600 degrees Celsius to 750 degrees Celsius at the beginning of a deposition process. Subsequently, a nitridation process such as a thermal nitridation process may be performed such that surface portions of the deposited silicon oxide layer is converted into a silicon oxynitride material such that the nitrogen content in the silicon oxynitride material decreases with a distance from the physically exposed surface of the silicon oxynitride material. A thermal nitridation process employing ammonia may be employed to convert the silicon oxide layer into the graded silicon oxynitride layer51G. Alternatively, both an oxygen containing source gas (e.g., TEOS) and a nitrogen containing source gas (e.g., ammonia) may be provided into the deposition chamber at the same time, and the ratio of the oxygen containing source gas to the nitrogen containing source gas is decreased continuously or stepwise during the deposition of the graded silicon oxynitride layer51G. Other suitable methods may be used to deposit the graded silicon oxynitride layer51G.

The thickness of the graded silicon oxynitride layer51G may be in a range from 1 nm to 20 nm, such as from 2 nm to 10 nm, although lesser and greater thicknesses may also be employed. Generally, the graded silicon oxynitride layer51G has a composition gradient such that an atomic concentration of nitrogen increases with a lateral distance from a sidewall of each memory opening49.

Referring toFIG.5C, a stack of layers including a dielectric metal oxide blocking dielectric layer52A, a silicon oxide blocking dielectric layer52S, a memory material layer54, a dielectric material liner56, and an optional sacrificial cover material layer (not illustrated) can be sequentially deposited over the graded silicon oxynitride layer51G in the memory openings49by a respective conformal deposition process.

The dielectric metal oxide blocking dielectric layer52A can consist essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the dielectric metal oxide blocking dielectric layer52A can have a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide blocking dielectric layer52A can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric metal oxide blocking dielectric layer52A can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the dielectric metal oxide blocking dielectric layer52A includes, and/or consists essentially of, aluminum oxide.

The silicon oxide blocking dielectric layer52S can include, and/or consist essentially of, silicon oxide. In this case, the silicon oxide blocking dielectric layer52S can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the silicon oxide blocking dielectric layer52S can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed.

Subsequently, the memory material layer54can be deposited as a continuous material layer by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. The memory material layer54includes a memory material, i.e., a material that can store data by selecting a state of the material. For example, the memory material layer54may include a charge storage material such as silicon nitride, polysilicon, or a metallic material (e.g., floating gate material), a ferroelectric material that can store information in the form of a ferroelectric polarization direction, or any other memory material that can store date by altering electrical resistivity.

The memory material layer54can be formed as a single memory material layer of homogeneous composition, or can include a stack of multiple memory material layers. In one embodiment, the memory material layer54may comprise an insulating charge trapping material, such as one or more silicon nitride segments or a continuous silicon nitride layer. In one embodiment, each memory material layer54can include a vertical stack of charge storage regions (e.g., regions of a continuous layer or vertically separated regions) that store electrical charges upon programming. In one embodiment, the memory material layer54can be a memory material layer in which each portion adjacent to the sacrificial material layers42constitutes a charge storage region.

The memory material layer54can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. In one embodiment, the memory material layer54comprises a continuous silicon nitride charge storage layer. The thickness of the memory material layer54can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The dielectric material liner56includes a dielectric material. The dielectric material liner56can be formed on the memory material layer54employing a conformal deposition process. In one embodiment, the dielectric material liner56comprises a tunneling dielectric layer through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The dielectric material liner56can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the dielectric material liner56can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the dielectric material liner56can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the dielectric material liner56can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

Optionally, a sacrificial cover material layer (not shown) may be deposited over the dielectric material liner56. In one embodiment, the sacrificial cover layer includes a sacrificial material that can be subsequently removed selective to the material of the dielectric material liner56. In one embodiment, the sacrificial cover material layer can include a semiconductor material such as amorphous silicon, or may include a carbon-based material such as amorphous carbon or diamond-like carbon (DLC). The sacrificial cover material layer can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the sacrificial cover material layer can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity49′ is formed in the volume of each memory opening49that is not filled with the deposited material layers.

Referring toFIG.5D, the optional sacrificial cover material layer (if present), the dielectric material liner56, the memory material layer54, the silicon oxide blocking dielectric layer52S, the dielectric metal oxide blocking dielectric layer52A and the graded silicon oxynitride layer51G can be sequentially anisotropically etched employing at least one anisotropic etch process. Horizontally-extending portions of the sacrificial cover material layer (if present), the dielectric material liner56, the memory material layer54, the silicon oxide blocking dielectric layer52S, the dielectric metal oxide blocking dielectric layer52A and the graded silicon oxynitride layer51G located above the top surface of the insulating cap layer70can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the sacrificial cover material layer (if present), the dielectric material liner56, the memory material layer54, the silicon oxide blocking dielectric layer52S, the dielectric metal oxide blocking dielectric layer52A and the graded silicon oxynitride layer51G located at a bottom of each memory cavity49′ can be removed to form openings through remaining portions thereof. Each of the sacrificial cover material layer (if present), the dielectric material liner56, the memory material layer54, the silicon oxide blocking dielectric layer52S, the dielectric metal oxide blocking dielectric layer52A and the graded silicon oxynitride layer51G can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may, or may not, be the same for the various material layers.

Subsequently, remaining portions of the sacrificial cover material layer (if employed) can optionally be removed selective to the dielectric material liner56employing an isotropic etch process or an ashing process. A surface of the semiconductor material layer10can be physically exposed underneath each opening through the layer stack (52A,52S,54,56) at the bottom of a respective memory opening49. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the semiconductor material layer10by a recess distance.

A set of a dielectric metal oxide blocking dielectric layer52A, a silicon oxide blocking dielectric layer52S, a memory material layer54, and a dielectric material liner56in a memory opening49constitutes a memory film50. In one embodiment, the memory film50may include a plurality of charge storage regions (comprising portions of the memory material layer54) that are insulated from surrounding materials by the stack of the dielectric metal oxide blocking dielectric layer52A and the silicon oxide blocking dielectric layer52S or by the dielectric material liner56. In one embodiment, the dielectric material liner56, the memory material layer54, the silicon oxide blocking dielectric layer52S, the dielectric metal oxide blocking dielectric layer52A, and the graded silicon oxynitride layer51G can have vertically coincident sidewalls around an opening through the memory film50at the bottom of each memory opening49.

Referring toFIG.5E, a semiconductor channel layer60L can be deposited directly on the semiconductor surface of the semiconductor material layer10, and directly on the dielectric material liner56. The semiconductor channel layer60L includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer60L includes amorphous silicon or polysilicon. The semiconductor channel layer60L can have a doping of a first conductivity type, which is the same as the conductivity type of the semiconductor material layer10. The semiconductor channel layer60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer60L can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The semiconductor channel layer60L may partially fill the memory cavity49′ in each memory opening, or may fully fill the cavity in each memory opening.

Referring toFIG.5F, in case the memory cavity49′ in each memory opening is not completely filled by the semiconductor channel layer60L, a dielectric core layer62L can be deposited in the memory cavity49′ to fill any remaining portion of the memory cavity49′ within each memory opening. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG.5G, the horizontal portion of the dielectric core layer62L can be removed, for example, by a recess etch process such that each remaining portions of the dielectric core layer62L is located within a respective memory opening49and has a respective top surface below the horizontal plane including the top surface of the insulating cap layer70. Each remaining portion of the dielectric core layer62L constitutes a dielectric core62.

Referring toFIG.5H, a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores62. The deposited semiconductor material can have a doping of a second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

Excess portions of the deposited semiconductor material having a doping of the second conductivity type and a horizontal portion of the semiconductor channel layer60L can be removed from above the horizontal plane including the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the semiconductor channel layer60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel60.

A dielectric material liner56is surrounded by a memory material layer54, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a dielectric metal oxide blocking dielectric layer52A, a silicon oxide blocking dielectric layer52S, a memory material layer54, and a dielectric material liner56collectively constitute a memory film50, which can store electrical charges or ferroelectric polarization with a macroscopic retention time. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours. According to an embodiment of the present disclosure, the memory film50comprises a dielectric metal oxide blocking dielectric layer52A that is formed directly on the inner cylindrical sidewall of the graded silicon oxynitride layer51G.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a vertical semiconductor channel60, a dielectric material liner56, a plurality of memory elements comprising portions of the memory material layer54, a silicon oxide blocking dielectric layer52S, and a dielectric metal oxide blocking dielectric layer52A.

An entire set of material portions that fills a memory opening49is herein referred to as a memory opening fill structure58. An entire set of material portions that fills a support opening19constitutes a support pillar structure. In one embodiment, the memory opening fill structure58comprises a graded silicon oxynitride layer51G, a dielectric metal oxide blocking dielectric layer52A, a silicon oxide blocking dielectric layer52S, a memory material layer54, an optional dielectric material liner56, a vertical semiconductor channel60, a dielectric core62, and a drain region63. A vertical NAND string can be formed through each memory opening upon subsequent replacement of the sacrificial material layers42with electrically conductive layers.

Referring toFIG.6, the first exemplary structure is illustrated after formation of memory opening fill structures58and support pillar structure20within the memory openings49and the support openings19, respectively. An instance of a memory opening fill structure58can be formed within each memory opening49of the structure ofFIGS.4Aand4B. An instance of the support pillar structure20can be formed within each support opening19of the structure ofFIGS.4A and4B.

Each memory stack structure55includes a vertical semiconductor channel60and a memory film50. The memory film50may comprise a dielectric material liner56laterally surrounding the vertical semiconductor channel60, a vertical stack of charge storage regions (as embodied as memory material layer54) laterally surrounding the dielectric material liner56, a dielectric metal oxide blocking dielectric layer52A, and a silicon oxide blocking dielectric layer52S.

Referring toFIGS.7A-7C, a contact-level dielectric layer73can be formed over the alternating stack (32,42) of insulating layer32and sacrificial material layers42, and over the memory opening fill structures58and the support pillar structures20. The contact-level dielectric layer73includes a dielectric material that is different from the dielectric material of the sacrificial material layers42. For example, the contact-level dielectric layer73can include silicon oxide. The contact-level dielectric layer73can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the contact-level dielectric layer73, and is lithographically patterned to form openings in areas between clusters of memory opening fill structures58. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer73, the alternating stack (32,42) and/or the retro-stepped dielectric material portion65employing an anisotropic etch to form backside trenches79, which vertically extend from the top surface of the contact-level dielectric layer73at least to the top surface of the substrate (9,10), and laterally extend through the memory array region100and the contact region300.

In one embodiment, the backside trenches79can laterally extend along a first horizontal direction hd1and can be laterally spaced apart among one another along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. The memory stack structures55can be arranged in rows that extend along the first horizontal direction hd1. The drain-select-level isolation structures72can laterally extend along the first horizontal direction hd1. Each backside trench79can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain-select-level isolation structure72can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory stack structures55can be located between a neighboring pair of a backside trench79and a drain-select-level isolation structure72, or between a neighboring pair of drain-select-level isolation structures72. In one embodiment, the backside trenches79can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing.

A source region61can be formed at a surface portion of the semiconductor material layer10under each backside trench79by implantation of electrical dopants into physically exposed surface portions of the semiconductor material layer10. An upper portion of the semiconductor material layer10that extends between the source region61and the memory opening fill structures58constitutes a horizontal semiconductor channel59for a plurality of field effect transistors. The horizontal semiconductor channel59is connected to multiple vertical semiconductor channels60.

Referring toFIGS.8and9A, an etchant that selectively etches the second material of the sacrificial material layers42with respect to the first material of the insulating layers32and the oxygen rich material at the outer sidewalls of the graded silicon oxynitride layer51G can be introduced into the backside trenches79.FIG.9Aillustrates a region of the first exemplary structure ofFIG.8. Backside recesses43are formed in volumes from which the sacrificial material layers42are removed. The removal of the second material of the sacrificial material layers42can be selective to the first material of the insulating layers32, the material of the retro-stepped dielectric material portion65, the semiconductor material of the semiconductor material layer10, and the oxygen rich material of the outer sidewalls of the graded silicon oxynitride layer51G. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32and the retro-stepped dielectric material portion65can be selected from silicon oxide and dielectric metal oxides. Generally, the backside recesses43can be formed by removing the sacrificial material layers42selective to the insulating layers32and the graded silicon oxynitride layers51G.

The etch process that removes the second material selective to the first material and the outermost layer of the memory films50can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches79. For example, if the sacrificial material layers42include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, oxygen rich silicon oxynitride, and various other materials employed in the art. The support pillar structure20, the retro-stepped dielectric material portion65, and the memory opening fill structures58provide structural support while the backside recesses43are present within volumes previously occupied by the sacrificial material layers42.

Each backside recess43can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess43can be greater than the height of the backside recess43. A plurality of backside recesses43can be formed in the volumes from which the second material of the sacrificial material layers42is removed. The memory openings in which the memory stack structures55are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses43. In one embodiment, the memory array region100comprises an array of three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9,10). In this case, each backside recess43can define a space for receiving a respective word line of the array of three-dimensional NAND strings.

Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate (9,10). A backside recess43can be vertically bounded by a top surface of an underlying insulating layer32and a bottom surface of an overlying insulating layer32. In one embodiment, each backside recess43can have a uniform height throughout.

Referring toFIG.9B, a first isotropic etch process can be performed to etch physically exposed surface portions of the graded silicon oxynitride layer51G around the backside recesses43. The first isotropic etch process etches silicon oxide at a higher etch rate than silicon nitride. The duration of the first isotropic etch process can be selected such that the lateral expansion of the backside recesses43into the graded silicon oxynitride layers51G stops before the backside recesses43reach the interfaces between the nitrogen rich inner sidewalls of the graded silicon oxynitride layers51G and the memory films50. In an illustrative example, the first isotropic etch process may comprise a wet etch process employing dilute hydrofluoric acid.

Surface portions of the insulating layers32, the insulating cap layer70, and the contact-level dielectric layer73may be collaterally recessed during the first isotropic etch process. The recess distance of the first isotropic etch process into the graded silicon oxynitride layer MG may be in a range from 30% to 95%, such as from 50% to 90%, of the thickness of the graded silicon oxynitride layer51G.

Referring toFIG.9C, a second isotropic etch process can be performed to etch the nitrogen rich inner portions of the graded silicon oxynitride layer51G containing nitrogen atoms at a higher atomic concentration (such as greater than 40% in atomic percentage) than the outer portions. Optionally, the second isotropic etch process may also etch adjacent portions of the dielectric metal oxide blocking dielectric layers52A around the backside recesses43. The second isotropic etch process etches silicon nitride and the dielectric metal oxide material of the dielectric metal oxide blocking dielectric layers52A at a higher etch rate than silicon oxide. The duration of the second isotropic etch process can be selected such that the lateral expansion of the backside recesses43into the dielectric metal oxide blocking dielectric layers52A stops before the backside recesses43reach the interfaces between a respective adjoining pair of a dielectric metal oxide blocking dielectric layer52A and a silicon oxide blocking dielectric layer52S (i.e., before the backside recesses43cut through the entire thickness of layer52A). In an illustrative example, the second isotropic etch process may comprise a wet etch process employing hot phosphoric acid which etches through part of the thickness of the dielectric metal oxide blocking dielectric layer52A. The nitrogen-rich portions of the graded silicon oxynitride layers51G and the dielectric metal oxide blocking dielectric layers52A can be isotropically recessed such that the vertical extent of each backside recess43is at a maximum within volumes laterally bounded by recessed surface segments of the dielectric metal oxide blocking dielectric layers52A that are formed by the second isotropic etch process. The recess distance of the second isotropic etch process, as measured from a vertical plane including an outer cylindrical sidewall of a dielectric metal oxide blocking dielectric layer52A toward an inner cylindrical sidewall of the dielectric metal oxide blocking dielectric layer52A, may be in a range from 30% to 95%, such as from 50% to 90%, of the thickness of the dielectric metal oxide blocking dielectric layer52A.

Generally, the second isotropic etch process etches silicon nitride at a higher etch rate than silicon oxide, and the backside recesses43are expanded through the composite dielectric spacer layer51around the memory film50within each memory opening fill structure58. The second isotropic etch process etches surface portions of the dielectric metal oxide blocking dielectric layer52A concurrently with recessing of the nitrogen rich surface portions of the graded silicon oxynitride layer51G. The combination of the first isotropic etch and the second isotropic etch divides each graded silicon oxynitride layer51G into a vertical stack of tubular graded silicon oxynitride portions53G laterally surrounding a respective memory film50. The tubular graded silicon oxynitride portions53G comprise composite dielectric spacers53that are located between the dielectric metal oxide blocking dielectric layer52A of a respective memory opening fill structure58and the insulating layers32.

In one embodiment, each tubular graded silicon oxynitride portion53G within each vertical stack of tubular graded silicon oxynitride portions53G comprises a contoured top surface including an inner concave top surface segment and an outer concave top surface segment that are adjoined to each other at a cusp, and a contoured bottom surface including an inner concave bottom surface segment and an outer concave bottom surface segment that are adjoined to each other at a cusp.

Referring toFIG.9D, a backside blocking dielectric layer44can be optionally formed. The backside blocking dielectric layer44, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses43. The backside blocking dielectric layer44can be formed in the backside recesses43and on a sidewall of the backside trench79. The backside blocking dielectric layer44can be formed directly on horizontal surfaces of the insulating layers32and directly on physically exposed surface segments of the dielectric metal oxide blocking dielectric layer52A around the backside recesses43. In one embodiment, the backside blocking dielectric layer44can be formed by a conformal deposition process such as atomic layer deposition (ALD). The thickness of the backside blocking dielectric layer44can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.

The dielectric material of the backside blocking dielectric layer44can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. In one embodiment, the backside blocking dielectric layer44can consist essentially of aluminum oxide. The backside blocking dielectric layer44can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer44is formed on the sidewalls of the backside trenches79, horizontal surfaces and sidewalls of the insulating layers32, physically exposed contoured surfaces of the tubular graded silicon oxynitride portions53G, and physically exposed surface segments of the memory stack structures55that are physically exposed to the backside recesses43. A backside cavity79′ is present within the portion of each backside trench79that is not filled with the backside blocking dielectric layer44.

Referring toFIG.9E, an optional metallic barrier layer46A can be deposited in the backside recesses43. The metallic barrier layer46A includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer46A can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer46A can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer46A can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer46A can consist essentially of a conductive metal nitride such as TiN.

A metal fill material is deposited in the plurality of backside recesses43, on the sidewalls of the at least one the backside trench79, and over the top surface of the contact-level dielectric layer73to form a metallic fill material layer46B. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer46B can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer46B can be selected, for example, from tungsten, molybdenum, cobalt, ruthenium, titanium, or tantalum. In one embodiment, the metallic fill material layer46B can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer46B can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer46B can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer46B is spaced from the insulating layers32and the memory stack structures55by the metallic barrier layer46A, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough. Alternatively, the metallic barrier layer46A may be omitted if the metallic fill material layer46B comprises molybdenum or another metal which may be used without a diffusion barrier.

A plurality of electrically conductive layers46can be formed in the plurality of backside recesses43, and a continuous metallic material layer46L can be formed on the sidewalls of each backside trench79and over the contact-level dielectric layer73. Each electrically conductive layer46includes a portion of the metallic barrier layer46A and a portion of the metallic fill material layer46B that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers32. The continuous metallic material layer46L includes a continuous portion of the metallic barrier layer46A and a continuous portion of the metallic fill material layer46B that are located in the backside trenches79or above the contact-level dielectric layer73. Each sacrificial material layer42can be replaced with an electrically conductive layer46. A backside cavity79′ is present in the portion of each backside trench79that is not filled with the backside blocking dielectric layer44and the continuous metallic material layer46L.

Referring toFIGS.9F and9G, the deposited metallic material of the continuous electrically conductive material layer46L is etched back from the sidewalls of each backside trench79and from above the contact-level dielectric layer73, for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.

In one embodiment, the removal of the continuous electrically conductive material layer46L can be selective to the material of the backside blocking dielectric layer44. In this case, a horizontal portion of the backside blocking dielectric layer44can be present at the bottom of each backside trench79. In another embodiment, the removal of the continuous electrically conductive material layer46L may not be selective to the material of the backside blocking dielectric layer44, and sidewalls of the insulating layers32may be physically exposed. A backside cavity79′ is present within each backside trench79.

In one embodiment, each of the electrically conductive layers46may be formed with a hammerhead-shaped vertical cross-sectional profile. As used herein, a “hammerhead-shaped vertical cross-sectional profile” refers to a vertical cross-sectional profile including a vertically-extending portion that is adjoined to a horizontally-extending portion such that the vertical extent of the vertically-extending portion is greater than the vertical extent of the joint between the vertically-extending portion and the horizontally-extending portion.

In one embodiment, the vertical extent of each of the electrically conductive layers46may have a local minimum LM (i.e., a pinch point or a narrow height plane) within a cylindrical volume laterally bounded by a sidewall of a respective memory opening49(as formed at the processing steps ofFIGS.4A,4B, and5A). In one embodiment, the local minimum LM may be located between a first cylindrical plane CP1including outer sidewalls of a vertical stack of tubular graded silicon oxynitride portions53G within a memory opening fill structure58and a second cylindrical plane CP2including inner sidewalls of the vertical stack of tubular graded silicon oxynitride portions53G. In one embodiment, the local minimum LM may be located along a continuous closed shape (such as a circle or an ellipse) that is equidistant from the first cylindrical plane CP1in a plan view along a vertical direction, for example, as illustrated inFIG.9G. In one embodiment, a maximum vertical extent of at least one, a plurality, or each, of the electrically conductive layers46within the cylindrical volume is greater than a vertical extent of a horizontally-extending portion of the one, the plurality, or each, of the electrically conductive layers46located outside the cylindrical volume, and the horizontally-extending portion having a uniform thickness along a vertical direction.

In one embodiment, the memory material layer54may comprise a charge storage layer, and the dielectric material liner56may comprise a tunneling dielectric layer. In this case, the memory film50comprises a layer stack including a tunneling dielectric layer and a charge storage layer in contact with the tunneling dielectric layer. In one embodiment, the memory film50comprises a dielectric metal oxide blocking dielectric layer52A in contact with the vertical stack of tubular graded silicon oxynitride portions53G.

In one embodiment, each of the electrically conductive layers46is spaced from the dielectric metal oxide blocking dielectric layer52A by a respective backside blocking dielectric layer44. In one embodiment, the respective backside blocking dielectric layer44is in contact with a respective pair of tubular graded silicon oxynitride portions53G and the dielectric metal oxide blocking dielectric layer52A.

In one embodiment, the dielectric metal oxide blocking dielectric layer52A comprises a straight inner sidewall that vertically extends straight through each of the electrically conductive layers46from a top periphery of the straight inner sidewall to a bottom periphery of the straight inner sidewall, and a laterally undulating outer sidewall having a first lateral thickness at levels of the insulating layers32and having a second lateral thickness at levels of the electrically conductive layers46that is less than the first lateral thickness. As used herein, lateral undulation refers to a variation of a lateral extent with respective to a vertical plane or with respect to a vertical line.

In one embodiment, the memory film50comprises a silicon oxide blocking dielectric layer52S in contact with an inner sidewall of the dielectric metal oxide blocking dielectric layer52A.

Referring toFIG.10, an insulating material layer can be formed in the backside trenches79and over the contact-level dielectric layer73by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed.

An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer73and at the bottom of each backside trench79. Each remaining portion of the insulating material layer constitutes an insulating spacer74. A backside cavity79′ is present within a volume surrounded by each insulating spacer74. A top surface of the semiconductor material layer10can be physically exposed at the bottom of each backside trench79.

A backside contact via structure76can be formed within each backside cavity79′. Each contact via structure76can fill a respective cavity79′. The contact via structures76can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity79′) of the backside trench79. For example, the at least one conductive material can include a conductive liner76A and a conductive fill material portion76B. The conductive liner76A can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion76B can include a metal or a metallic alloy. For example, the conductive fill material portion76B can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

The at least one conductive material can be planarized employing the contact-level dielectric layer73overlying the alternating stack (32,46) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer73can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches79constitutes a backside contact via structure76.

The backside contact via structure76extends through the alternating stack (32,46), and contacts a top surface of the source region61. If a backside blocking dielectric layer44is employed, the backside contact via structure76can contact a sidewall of the backside blocking dielectric layer44.

Alternatively, the above described insulating material layer can be formed in the backside trenches79to completely fill the entire volume of a backside trench79and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region61and the backside trench via structure76may be omitted, and a horizontal source line (e.g., direct strap contact) may contact an side of the lower portion of the semiconductor channel60.

Referring toFIGS.11A-11C, additional contact via structures (88,86,8P) can be formed through the contact-level dielectric layer73, and optionally through the retro-stepped dielectric material portion65. For example, drain contact via structures88can be formed through the contact-level dielectric layer73on each drain region63. Word line contact via structures86can be formed on the electrically conductive layers46through the contact-level dielectric layer73, and through the retro-stepped dielectric material portion65. Peripheral device contact via structures8P can be formed through the retro-stepped dielectric material portion65directly on respective nodes of the peripheral devices. Bit lines (not shown for clarity) are then formed in electrical contact with the drain contact via structures88

FIGS.12A and12Bare sequential vertical cross-sectional views of a region of a first alternative embodiment of the first exemplary structure during formation of electrically conductive layers46according to the first embodiment of the present disclosure.

Referring toFIG.12A, the first alternative configuration of the first exemplary structure may be derived from the first exemplary structure illustrated at the processing steps ofFIG.9Cby performing an oxidation process, such as a thermal or plasma oxidation process. The oxidation process converts exposed surface portions of the tubular graded silicon oxynitride portions53G into silicon oxide portions57. The distance between a physically exposed sidewall and an interface with a respective tubular graded silicon oxynitride portion53G for each silicon oxide portion57may be in a range from 1 nm to 10 nm, although lesser and greater distances may also be employed.

Referring toFIG.12B, the processing steps ofFIGS.9D-9G,10, and11A-11Ccan be performed. In one embodiment, each of the electrically conductive layers46is spaced from the dielectric metal oxide blocking dielectric layer52A by a respective backside blocking dielectric layer44. In one embodiment, the memory opening fill structure58comprises a vertical stack of silicon oxide portions57located between neighboring pairs of an electrically conductive layer46of the electrically conductive layers46and a tubular graded silicon oxynitride portion53G of the vertical stack of tubular graded silicon oxynitride portions53G. In one embodiment, the respective backside blocking dielectric layer44may be in contact with a respective pair of silicon oxide portions57within the vertical stack of silicon oxide portions57.

FIGS.13A and13Bare sequential vertical cross-sectional views of a region of a second alternative embodiment of the first exemplary structure during formation of electrically conductive layers according to the first embodiment of the present disclosure.

Referring toFIG.13A, the second alternative embodiment of the first exemplary structure may be derived from the first exemplary structure ofFIG.9Bby performing a second isotropic etch process described with reference toFIG.9Cwith a modification to the etch chemistry and/or to the duration of the second isotropic etch process such that the etch process stops on the outer sidewall of the material of the dielectric metal oxide blocking dielectric layer52A. In this embodiment, the etch chemistry of the second isotropic etch process may be modified such that the second isotropic etch process etches the nitrogen-rich portions of the tubular graded silicon oxynitride portions53G selective to the material of the dielectric metal oxide blocking dielectric layer52A. Alternatively and/or additionally, the duration of the second anisotropic etch process can be selected such that portions of the outer cylindrical sidewall of the dielectric metal oxide blocking dielectric layer52A are physically exposed without etching the dielectric metal oxide blocking dielectric layer52A. Thus, the backside recesses43do not extend into the dielectric metal oxide blocking dielectric layer52A.

Referring toFIG.13B, the processing steps ofFIGS.9D-9G,10, and11A-11Ccan be subsequently performed. In one embodiment, the dielectric metal oxide blocking dielectric layer52A may have a uniform lateral thickness throughout. In one embodiment, the dielectric metal oxide blocking dielectric layer52A may comprise a straight inner sidewall that vertically extends straight through each of the electrically conductive layers from a top periphery of the straight inner sidewall to a bottom periphery of the straight inner sidewall, and may comprise a straight outer sidewall that vertically extends straight through each of the electrically conductive layers from a top periphery of the straight outer sidewall to a bottom periphery of the straight outer sidewall. The electrically conductive layers46or the backside blocking dielectric layers44(if present) contact the outer sidewall of the dielectric metal oxide blocking dielectric layer52A.

Referring toFIG.14, a region of a third alternative embodiment of the first exemplary structure according to the first embodiment of the present disclosure is illustrated. The third alternative embodiment of the first exemplary structure may be derived from the first exemplary structure or the previously described alternative embodiments thereof by omitting formation of the backside blocking dielectric layer44. In one embodiment, each of the electrically conductive layers46may be in direct contact with a respective pair of insulating layers32within the insulating layers32of the alternating stack (32,46), and is in direct contact with a respective pair of tubular graded silicon oxynitride portions53G within the vertical stack of tubular graded silicon oxynitride portions53G (or in direct contact with the silicon oxide portions57, if present).

Referring toFIGS.1-14and according to various embodiments of the first exemplary structure, a semiconductor structure comprises an alternating stack of insulating layers32and electrically conductive layers46; a memory opening49vertically extending through the alternating stack (32,46), and a memory opening fill structure58located in the memory opening49and comprising a vertical semiconductor channel60, a memory film50in contact with the vertical semiconductor channel60, and a vertical stack of tubular graded silicon oxynitride portions53G laterally surrounding the memory film50and having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film50. In one embodiment, the memory film comprises a dielectric metal oxide blocking dielectric layer. In one embodiment, each of the electrically conductive layers46has a hammerhead-shaped vertical cross-sectional profile such that a vertical extent of each of the electrically conductive layers46has a local minimum LM within a cylindrical volume laterally bounded by outer sidewall segments of the memory opening fill structure58. In one embodiment, the vertical extent of each of the electrically conductive layers46may have the local minimum LM within a cylindrical volume laterally bounded by a sidewall of a respective memory opening49(as formed at the processing steps ofFIGS.4A,4B, and5A). In one embodiment, the local minimum LM may be located between a first cylindrical plane CP1including outer sidewalls of a vertical stack of tubular graded silicon oxynitride portions53G within a memory opening fill structure58and a second cylindrical plane CP2including inner sidewalls of the vertical stack of tubular graded silicon oxynitride portions53G. In one embodiment, the local minimum LM may be located along a continuous closed shape (such as a circle or an ellipse) that is equidistant from the first cylindrical plane in a plan view along a vertical direction, for example, as illustrated inFIG.9G.

According to an aspect of the present disclosure, a second exemplary structure according to a second embodiment of the present disclosure may be derived from the first exemplary structure ofFIGS.4A,4B, and5Aby alternating components of each memory opening fill structure58.FIGS.15A-15Hare sequential schematic vertical cross-sectional views of a memory opening49within a second exemplary structure during formation of a memory opening fill structure58therein according to the second embodiment of the present disclosure.

Referring toFIG.15A, each memory opening49within the second exemplary structure may be the same as the memory opening49illustrated inFIG.5Aat a processing step that corresponds to the processing steps ofFIGS.4A,4B, and5A.

Referring toFIG.15B, a composite dielectric spacer layer51is formed on the physically exposed surfaces of each memory opening49and each support opening19and over the top surface of the insulating cap layer70. In one embodiment, the composite dielectric spacer layer51comprises a layer stack that includes a first silicon oxide spacer layer511(which is also referred to as an outer silicon oxide spacer layer), a dielectric metal oxide spacer layer512, and a second silicon oxide spacer layer513. The first silicon oxide spacer layer511, the dielectric metal oxide spacer layer512, and the second silicon oxide spacer layer513may be sequentially deposited by a respective conformal deposition process. The conformal deposition processes employed to deposit the first silicon oxide spacer layer511, the dielectric metal oxide spacer layer512, and the second silicon oxide spacer layer513may comprise at least one low pressure chemical vapor deposition process and/or at least one atomic layer deposition process.

The first silicon oxide spacer layer511and the second silicon oxide spacer layer513comprise, and/or consist essentially of, silicon oxide. The dielectric metal oxide spacer layer512comprises, and/or consists essentially of, a dielectric metal oxide material, such as aluminum oxide. The thickness of the first silicon oxide spacer layer511may be in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses may also be employed. The thickness of the dielectric metal oxide spacer layer512may be in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses may also be employed. The thickness of the third silicon oxide spacer layer513may be in a range from 2 nm to 20 nm, such as from 4 nm to 10 nm, although lesser and greater thicknesses may also be employed.

Referring toFIG.15C, a stack of layers including the dielectric metal oxide blocking dielectric layer52A, a memory material layer54, a dielectric material liner56, and an optional sacrificial cover material layer (not illustrated) can be sequentially deposited in the memory openings49by a respective conformal deposition process, as described in the first embodiment above. Each of the dielectric metal oxide blocking dielectric layer52A, the memory material layer54, the dielectric material liner56, and the optional sacrificial cover material layer may have the same material composition and the same thickness range as in the first exemplary structure illustrated inFIG.5C. The dielectric metal oxide blocking dielectric layer52A may be deposited directly on the composite dielectric spacer layer51, and the memory material layer54may be deposited directly on the dielectric metal oxide blocking dielectric layer52A.

Referring toFIG.15D, at least one anisotropic etch process may be performed to sequentially etch horizontally-extending portions of the optional sacrificial cover material layer (if present), the dielectric material liner56, the memory material layer54, the dielectric metal oxide blocking dielectric layer52A, and the composite dielectric spacer layer51. A surface of the semiconductor material layer10can be physically exposed underneath each opening through the layer stack (51,52A,54,56) at the bottom of a respective memory opening49. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the semiconductor material layer10by a recess distance.

A set of a dielectric metal oxide blocking dielectric layer52A, a memory material layer54, and a dielectric material liner56in a memory opening49constitutes a memory film50. In one embodiment, the memory film50may include a plurality of charge storage regions (comprising portions of the memory material layer54) that are insulated from surrounding materials by the dielectric metal oxide blocking dielectric layer52A or by the dielectric material liner56. In one embodiment, the dielectric material liner56, the memory material layer54, the dielectric metal oxide blocking dielectric layer52A, and the composite dielectric spacer layer51can have vertically coincident sidewalls around an opening through the memory film50at the bottom of each memory opening49.

Referring toFIG.15E, the semiconductor channel layer60L can be deposited directly on the semiconductor surface of the semiconductor material layer10, and directly on the dielectric material liner56. The material composition and the thickness range of the semiconductor channel layer60L may be the same as in the first exemplary structure.

Referring toFIG.15F, in case the memory cavity49′ in each memory opening is not completely filled by the semiconductor channel layer60L, a dielectric core layer62L can be deposited in the memory cavity49′ to fill any remaining portion of the memory cavity49′ within each memory opening. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG.15G, the horizontal portion of the dielectric core layer62L can be removed, for example, by a recess etch process such that each remaining portions of the dielectric core layer62L is located within a respective memory opening49and has a respective top surface below the horizontal plane including the top surface of the insulating cap layer70. Each remaining portion of the dielectric core layer62L constitutes a dielectric core62.

Referring toFIG.15H, the processing steps ofFIG.5Hmay be performed to form a vertical semiconductor channel60and a drain region63within each memory opening49. According to an embodiment of the present disclosure, the memory film50comprises a dielectric metal oxide blocking dielectric layer52A that is formed directly on the inner cylindrical sidewall of the composite dielectric spacer layer51.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a vertical semiconductor channel60, a dielectric material liner56, a plurality of memory elements comprising portions of the memory material layer54, and a dielectric metal oxide blocking dielectric layer52A. An entire set of material portions that fills a memory opening49is herein referred to as a memory opening fill structure58. An entire set of material portions that fills a support opening19constitutes a support pillar structure.

Generally, a memory opening fill structure58can be formed in each memory opening49. In one embodiment, the memory opening fill structure58comprises a composite dielectric spacer layer51, a dielectric metal oxide blocking dielectric layer52A, a memory material layer54, an optional dielectric material liner56, a vertical semiconductor channel60, a dielectric core62, and a drain region63.

Generally, an instance of a memory opening fill structure58illustrated inFIG.15Hcan be formed within each memory opening49of the structure ofFIGS.4A and4B. An instance of the support pillar structure can be formed within each support opening19of the structure ofFIGS.4A and4B. Generally, the composite dielectric spacer layer51comprises a stack of a first silicon oxide spacer layer511, a dielectric metal oxide spacer layer512, and a second silicon oxide spacer layer513. The memory film50may be formed by sequentially depositing a dielectric metal oxide blocking dielectric layer52A, a memory material layer54(which may comprise a charge storage layer), and dielectric material liner56(such as a tunneling dielectric layer) over the second silicon oxide spacer layer513.

Subsequently, the processing steps ofFIGS.7A-7Cand the processing steps ofFIGS.8and9Acan be performed to provide the second exemplary structure illustrated inFIG.16A.

Referring toFIG.16A, an etchant that selectively etches the second material of the sacrificial material layers42with respect to the first material of the insulating layers32and the silicon oxide material of the first silicon oxide spacer layer511can be introduced into the backside trenches79, for example, employing an etch process. Backside recesses43are formed in volumes from which the sacrificial material layers42are removed. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32and the retro-stepped dielectric material portion65can be silicon oxide and/or dielectric metal oxide. Generally, the backside recesses43can be formed by removing the sacrificial material layers42selective to the insulating layers32and the first silicon oxide spacer layer511. In one embodiment, the etch process that removes the second material selective to the first material and the first silicon oxide spacer layer511may be the same as the etch process described above with reference toFIGS.8and9A.

Referring toFIG.16B, a first isotropic etch process can be performed to isotropically etch the silicon oxide material of the portions of the first silicon oxide spacer layer511located around the backside recesses43. The first isotropic etch process etches silicon oxide selective to the material of the dielectric metal oxide spacer layer512. The duration of the first isotropic etch process can be selected such that cylindrical segments of the outer sidewall of the dielectric metal oxide spacer512are physically exposed around the backside recesses43. The recess distance of the first isotropic etch process into the first silicon oxide spacer layer511may be in a range from 100% to 130% of the thickness of the first silicon oxide spacer layer511. Surface portions of the insulating layers32, the insulating cap layer70, and the contact-level dielectric layer73may be collaterally recessed during the first isotropic etch process. In an illustrative example, the first isotropic etch process may comprise a wet isotropic etch process employing dilute hydrofluoric acid.

The backside recesses43are expanded into the composite dielectric spacer layer51around the memory film50. The first silicon oxide spacer layer511can be divided into a vertical stack of first tubular silicon oxide spacers511′ having a uniform thickness and having at least one tapered concave annular surface. A subset of the first tubular silicon oxide spacers511′ may comprise a respective tapered concave top annular surface511T and a respective tapered concave bottom annular surface511B.

Referring toFIG.16C, a second isotropic etch process can be performed to isotropically etch the dielectric metal oxide material of the portions of the dielectric metal oxide spacer layer512located around the backside recesses43. The second isotropic etch process etches the dielectric metal oxide material of the dielectric metal oxide spacer layer512selective to the silicon oxide material of the first tubular silicon oxide spacers511′ and selective to the materials of the insulating layers32, the insulating cap layer70, and the contact-level dielectric layer73. The duration of the second isotropic etch process can be selected such that cylindrical segments of the outer sidewall of the second silicon oxide spacer513are physically exposed around the backside recesses43. The recess distance of the second isotropic etch process into the dielectric metal oxide spacer layer512may be in a range from 100% to 200% of the thickness of the dielectric metal oxide spacer layer512. In an illustrative example, the second isotropic etch process may comprise a wet isotropic etch process employing hot phosphoric acid. The respective tapered concave top annular surface511T and the respective tapered concave bottom annular surface511B define respective protruding portions511P of the first tubular silicon oxide spacers511′.

The backside recesses43are expanded into the composite dielectric spacer layer51around the memory film50. The dielectric metal oxide spacer layer512can be divided into a vertical stack of tubular dielectric metal oxide spacers512′ having a uniform thickness and having at least one tapered concave annular surface. A subset of the tubular dielectric metal oxide spacers512′ may comprise a respective tapered concave top annular surface512T and a respective tapered concave bottom annular surface512B. In one embodiment, the vertical extent of each backside recess43between a vertically neighboring pair of tubular dielectric metal oxide spacers512′ may be greater than the vertical extent of the horizontally-extending portion of the respective backside recess43between a vertically neighboring pair of insulating layers32.

Referring toFIG.16D, a third isotropic etch process can be performed to isotropically etch the silicon oxide material of the portions of the second silicon oxide spacer layer513located around the backside recesses43. The third isotropic etch process etches the silicon oxide material of the second silicon oxide spacer layer513selective to the material of the memory material layer54, and selective to the dielectric metal oxide material of the tubular dielectric metal oxide spacers512′. The first tubular silicon oxide spacers511′, the insulating layers32, the insulating cap layer70, and the contact-level dielectric layer73may be collaterally recessed during the third isotropic etch process. The duration of the third isotropic etch process can be selected such that cylindrical segments of the outer sidewall of the second silicon oxide spacer513are physically exposed around the backside recesses43. The recess distance of the third isotropic etch process into the second silicon oxide spacer layer513may be in a range from 100% to 200% of the thickness of the second silicon oxide spacer layer513. In an illustrative example, the third isotropic etch process may comprise a wet etch process employing dilute hydrofluoric acid.

The backside recesses43are expanded through the composite dielectric spacer layer51around the memory film50. The second silicon oxide spacer layer513can be divided into a vertical stack of second tubular silicon oxide spacers513′ having a uniform thickness and having at least one tapered concave annular surface. A subset of the second tubular silicon oxide spacers513′ may comprise a respective tapered concave top annular surface513T and a respective tapered concave bottom annular surface513B. In one embodiment, the vertical extent of each backside recess43between a vertically neighboring pair of second tubular silicon oxide spacers513′ may be greater than the vertical extent of the horizontally-extending portion of the respective backside recess43between a vertically neighboring pair of insulating layers32. In one embodiment, the vertical extent of each backside recess43between a vertically neighboring pair of tubular dielectric metal oxide spacers512′ may also be greater than the vertical extent of the horizontally-extending portion of the respective backside recess43between a vertically neighboring pair of insulating layers32.

Each contiguous set of a first tubular silicon oxide spacer511′, a tubular dielectric metal oxide spacer512′, and a second tubular silicon oxide spacer513′ constitutes a tubular composite dielectric spacer51′. Generally, the composite dielectric spacer layer51can be divided into a vertical stack of tubular composite dielectric spacers51′ by a combination of isotropic etch processes, such as the combination of the first isotropic etch process, the second isotropic etch process, and the third isotropic etch process. The vertical stack of tubular composite dielectric spacers51′ laterally surrounds the memory film50, which may comprise a layer stack of a dielectric metal oxide blocking dielectric layer52A, a memory material layer54(which may comprise a charge storage layer), and a dielectric material liner56(which may comprise a tunneling dielectric layer).

The cylindrical plane including the outer sidewalls of the vertical stack of tubular composite dielectric spacers51′ is herein referred to as a first cylindrical plane CP1. According to an aspect of the present disclosure, each first tubular silicon oxide spacer511′ within the vertical stack of tubular composite dielectric spacers51′ may have a variable vertical extent that increases with a lateral distance from the first cylindrical plane CP1. In one embodiment, each tubular dielectric metal oxide spacer512′ within the vertical stack of tubular composite dielectric spacers512′ has a variable vertical extent that increases with a lateral distance from the first cylindrical plane CP1. In one embodiment, each second tubular silicon oxide spacer513′ within the vertical stack of tubular composite dielectric spacers513′ may have a variable vertical extent that increases with a lateral distance from the first cylindrical plane CP1.

In one embodiment, each of the tubular composite dielectric spacers51′ comprises a respective second tubular silicon oxide spacer513′ in contact with an outer sidewall of the memory film50. In one embodiment, the memory film50may comprise a layer stack including a tunneling dielectric layer (comprising a dielectric material liner56) in contact with the vertical semiconductor channel60, a charge storage layer (comprising a memory material layer54) in contact with the tunneling dielectric layer, and a dielectric metal oxide blocking dielectric layer52A in contact with the charge storage layer54and with the vertical stack of tubular composite dielectric spacers51′.

In one embodiment, a vertical cross-sectional profile of a tubular composite dielectric spacer51′ within the vertical stack of tubular composite dielectric spacers51′ comprises a serrated top surface including a concave top surface segment511T of a first tubular silicon oxide spacer511′ of the first tubular silicon oxide spacers511′, a concave top surface segment512T of a tubular dielectric metal oxide spacer512′ of the tubular dielectric metal oxide spacers512′, and a concave top surface segment513T of a second tubular silicon oxide spacer513′ of the second tubular silicon oxide spacers513′. In one embodiment, the serrated top surface comprises a first vertical surface segment (which is a first cylindrical surface segment) of the first tubular silicon oxide spacer511′ connecting the concave top surface segment of the first tubular silicon oxide spacer511′ and the concave top surface segment of the tubular dielectric metal oxide spacer512′, and an additional vertical surface segment (which is an additional cylindrical surface segment) of the tubular dielectric meal oxide spacer512′ connecting the concave top surface segment of the tubular dielectric metal oxide spacer512′ and the concave top surface segment of the second tubular silicon oxide spacer513′.

In one embodiment, the vertical cross-sectional profile of a tubular composite dielectric spacer51′ within the vertical stack of tubular composite dielectric spacers51′ comprises a serrated bottom surface including a concave bottom surface segment511B of a first tubular silicon oxide spacer511′ of the first tubular silicon oxide spacers511′, a concave bottom surface segment512B of a tubular dielectric metal oxide spacer512′ of the tubular dielectric metal oxide spacers512′, and a concave bottom surface segment513B of a second tubular silicon oxide spacer513′ of the second tubular silicon oxide spacers513′. In one embodiment, the serrated bottom surface comprises a second vertical surface segment (which is a second cylindrical surface segment) of the first tubular silicon oxide spacer511′ connecting the concave bottom surface segment of the first tubular silicon oxide spacer511′ and the concave bottom surface segment of the tubular dielectric metal oxide spacer512′, and an additional vertical surface segment (which is an additional cylindrical surface segment) of the tubular dielectric meal oxide spacer512′ connecting the concave bottom surface segment of the tubular dielectric metal oxide spacer512′ and the concave bottom surface segment of the second tubular silicon oxide spacer513′.

Referring toFIG.16E, a backside blocking dielectric layer44can be optionally formed. The backside blocking dielectric layer44, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses43. The backside blocking dielectric layer44can be formed in the backside recesses43and on a sidewall of the backside trench79. The backside blocking dielectric layer44can be formed directly on horizontal surfaces of the insulating layers32and directly on physically exposed surface segments of the dielectric metal oxide blocking dielectric layer52A around the backside recesses43. In one embodiment, the backside blocking dielectric layer44can be formed by a conformal deposition process such as atomic layer deposition (ALD). The material composition and the thickness range of the backside blocking dielectric layer44may be the same as in the first exemplary structure.

Referring toFIG.16F, the processing steps ofFIGS.9E,9F, and9Gcan be performed to sequentially deposit a metallic barrier layer46A and a metallic fill material layer46B, and to remove a continuous metallic material layer46L from inside the backside trenches79and from above the insulating cap layer70. Each remaining portion of the metallic barrier layer46A and the metallic fill material layer46B in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46. Alternatively, the metallic barrier layer46A may be omitted.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.

In one embodiment, the removal of the continuous electrically conductive material layer46L can be selective to the material of the backside blocking dielectric layer44. In this case, a horizontal portion of the backside blocking dielectric layer44can be present at the bottom of each backside trench79. In another embodiment, the removal of the continuous electrically conductive material layer46L may not be selective to the material of the backside blocking dielectric layer44, and sidewalls of the insulating layers32may be physically exposed. A backside cavity79′ is present within each backside trench79.

In one embodiment, each of the electrically conductive layers46may be formed with a hammerhead-shaped vertical cross-sectional profile. In one embodiment, the vertical extent of each of the electrically conductive layers46may have a local minimum LM within a cylindrical volume laterally bounded by outer sidewall segments of the memory opening fill structure58that contact the insulating layers32.

In one embodiment, the local minimum LM may be located between a first cylindrical plane CP1including outer sidewalls of a vertical stack of tubular composite dielectric spacers51′ within a memory opening fill structure58and a second cylindrical plane CP2including inner sidewalls of the vertical stack of tubular composite dielectric spacers51′. In one embodiment, the local minimum LM may be located along a continuous closed shape (such as a circle or an ellipse) that is equidistant from the first cylindrical plane CP1in a plan view along a vertical direction.

In one embodiment, each of the electrically conductive layers46is spaced from the dielectric metal oxide blocking dielectric layer52A by a respective backside blocking dielectric layer44. In one embodiment, each of the backside blocking dielectric layers44contacts a respective pair of tubular composite dielectric spacers51′ within the vertical stack of tubular composite dielectric spacers41′. Alternatively, the backside blocking dielectric44may be omitted. In one embodiment, the maximum vertical extent of one, a plurality, or each, of the electrically conductive layers46within the cylindrical volume is greater than the vertical extent of a horizontally-extending portion of the one, the plurality, or each, of the electrically conductive layers46located outside the cylindrical volume and having a uniform thickness along a vertical direction.

Referring toFIG.16G, the processing steps ofFIG.10can be performed to form an insulating spacer74and a backside contact via structure76in each of the backside trenches79. The processing steps ofFIGS.11A and11Bcan be performed to form various additional contact via structures (88,86,8P). For example, drain contact via structures88can be formed through the contact-level dielectric layer73on each drain region63. Word line contact via structures86can be formed on the electrically conductive layers46through the contact-level dielectric layer73, and through the retro-stepped dielectric material portion65. Peripheral device contact via structures8P can be formed through the retro-stepped dielectric material portion65directly on respective nodes of the peripheral devices.

According to an aspect of the present disclosure, a third exemplary structure according to a third embodiment of the present disclosure may be derived from the first exemplary structure ofFIGS.4A,4B, and5Aby alternating components of each memory opening fill structure58.FIGS.17A-17Hare sequential schematic vertical cross-sectional views of a memory opening49within the third exemplary structure during formation of a memory opening fill structure58therein according to the third embodiment of the present disclosure.

Referring toFIG.17A, each memory opening49within the second exemplary structure may be the same as the memory opening49illustrated inFIG.5Aat a processing step that corresponds to the processing steps ofFIGS.4A,4B, and5A.

Referring toFIG.17B, a composite dielectric spacer layer51is formed on the physically exposed surfaces of each memory opening49and each support opening19and over the top surface of the insulating cap layer70. In one embodiment, the composite dielectric spacer layer51comprises a layer stack that includes a silicon oxide spacer layer511(which is also referred to as an outer silicon oxide spacer layer) and a dielectric metal oxide spacer layer512. The silicon oxide spacer layer511and the dielectric metal oxide spacer layer512may be sequentially deposited by a respective conformal deposition process. The conformal deposition processes employed to deposit the silicon oxide spacer layer511and the dielectric metal oxide spacer layer512may comprise at least one low pressure chemical vapor deposition process and/or at least one atomic layer deposition process.

The silicon oxide spacer layer511may have the same material composition and the same thickness range as the first silicon oxide spacer layer511of the second exemplary structure. The dielectric metal oxide spacer layer512may have the same material composition and the same thickness range as in the second exemplary structure.

Referring toFIG.17C, a stack of layers including a silicon oxide blocking dielectric layer52S, a memory material layer54, a dielectric material liner56, and an optional sacrificial cover material layer (not illustrated) can be sequentially deposited in the memory openings49by a respective conformal deposition process. Each of the silicon oxide blocking dielectric layer52S, the memory material layer54, the dielectric material liner56, and the optional sacrificial cover material layer may have the same material composition and the same thickness range as in the first exemplary structure illustrated inFIG.5C. The silicon oxide blocking dielectric layer52S may be deposited directly on the composite dielectric spacer layer51, and the memory material layer54may be deposited directly on the silicon oxide blocking dielectric layer52S.

Referring toFIG.17D, at least one anisotropic etch process may be performed to sequentially etch horizontally-extending portions of the optional sacrificial cover material layer (if present), the dielectric material liner56, the memory material layer54, the silicon oxide blocking dielectric layer52S, and the composite dielectric spacer layer51. A surface of the semiconductor material layer10can be physically exposed underneath each opening through the layer stack (51,52S,54,56) at the bottom of a respective memory opening49. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the semiconductor material layer10by a recess distance.

A set of a silicon oxide blocking dielectric layer52S, a memory material layer54, and a dielectric material liner56in a memory opening49constitutes a memory film50. In one embodiment, the memory film50may include a plurality of charge storage regions (comprising portions of the memory material layer54) that are insulated from surrounding materials by the silicon oxide blocking dielectric layer52S or by the dielectric material liner56. In one embodiment, the dielectric material liner56, the memory material layer54, the silicon oxide blocking dielectric layer52S, and the composite dielectric spacer layer51can have vertically coincident sidewalls around an opening through the memory film50at the bottom of each memory opening49.

Referring toFIG.17E, a semiconductor channel layer60L can be deposited directly on the semiconductor surface of the semiconductor material layer10, and directly on the dielectric material liner56. The material composition and the thickness range of the semiconductor channel layer60L may be the same as in the first exemplary structure.

Referring toFIG.17F, in case the memory cavity49′ in each memory opening is not completely filled by the semiconductor channel layer60L, a dielectric core layer62L can be deposited in the memory cavity49′ to fill any remaining portion of the memory cavity49′ within each memory opening. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG.17G, the horizontal portion of the dielectric core layer62L can be removed, for example, by a recess etch process such that each remaining portions of the dielectric core layer62L is located within a respective memory opening49and has a respective top surface below the horizontal plane including the top surface of the insulating cap layer70. Each remaining portion of the dielectric core layer62L constitutes a dielectric core62.

Referring toFIG.17H, the processing steps ofFIG.5Hmay be performed to form a vertical semiconductor channel60and a drain region63within each memory opening49.

A dielectric material liner56is surrounded by a memory material layer54, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a silicon oxide blocking dielectric layer52S, a memory material layer54, and a dielectric material liner56collectively constitute a memory film50, which can store electrical charges or ferroelectric polarization with a macroscopic retention time. According to an embodiment of the present disclosure, the memory film50comprises a silicon oxide blocking dielectric layer52S that is formed directly on the inner cylindrical sidewall of the composite dielectric spacer layer51.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a vertical semiconductor channel60, a dielectric material liner56, a plurality of memory elements as embodied as portions of the memory material layer54, and a silicon oxide blocking dielectric layer52S. An entire set of material portions that fills a memory opening49is herein referred to as a memory opening fill structure58. An entire set of material portions that fills a support opening19constitutes a support pillar structure.

Generally, a memory opening fill structure58can be formed in each memory opening49. In one embodiment, the memory opening fill structure58comprises a composite dielectric spacer layer51, a silicon oxide blocking dielectric layer52S, a memory material layer54, an optional dielectric material liner56, a vertical semiconductor channel60, a dielectric core62, and a drain region63.

Generally, an instance of a memory opening fill structure58illustrated inFIG.17Hcan be formed within each memory opening49of the structure ofFIGS.4A and4B. An instance of the support pillar structure can be formed within each support opening19of the structure ofFIGS.4A and4B. Generally, the composite dielectric spacer layer51comprises a stack of a silicon oxide spacer layer511and a dielectric metal oxide spacer layer512. The memory film50may be formed by sequentially depositing a silicon oxide blocking dielectric layer52S, a memory material layer54(which may comprise a charge storage layer), and dielectric material liner56(such as a tunneling dielectric layer) over the dielectric metal oxide spacer layer512.

Subsequently, the processing steps ofFIGS.7A-7Cand the processing steps ofFIGS.8and9Acan be performed to provide the third exemplary structure illustrated inFIG.18A. Generally, the backside recesses43can be formed by removing the sacrificial material layers42selective to the insulating layers32and the silicon oxide spacer layer511. In one embodiment, the etch process that removes the second material selective to the first material and the silicon oxide spacer layer511may be the same as the etch process described above with reference toFIGS.8and9A.

Referring toFIG.18B, a first isotropic etch process can be performed to isotropically etch the silicon oxide material of the portions of the silicon oxide spacer layer511located around the backside recesses43. The first isotropic etch process etches silicon oxide selective to the material of the dielectric metal oxide spacer layer512. The duration of the first isotropic etch process can be selected such that cylindrical segments of the outer sidewall of the dielectric metal oxide spacer512are physically exposed around the backside recesses43. The recess distance of the first isotropic etch process into the silicon oxide spacer layer511may be in a range from 100% to 130% of the thickness of the silicon oxide spacer layer511. Surface portions of the insulating layers32, the insulating cap layer70, and the contact-level dielectric layer73may be collaterally recessed during the first isotropic etch process. In an illustrative example, the first isotropic etch process may comprise a wet isotropic etch process employing dilute hydrofluoric acid.

The backside recesses43are expanded into the composite dielectric spacer layer51around the memory film50. The silicon oxide spacer layer511can be divided into a vertical stack of tubular silicon oxide spacers511′ having a uniform thickness and having at least one tapered concave annular surface. A subset of the tubular silicon oxide spacers511′ may comprise a respective tapered concave top annular surface and a respective tapered concave bottom annular surface.

Referring toFIG.18C, a second isotropic etch process can be performed to isotropically etch the dielectric metal oxide material of the portions of the dielectric metal oxide spacer layer512located around the backside recesses43. The second isotropic etch process etches the dielectric metal oxide material of the dielectric metal oxide spacer layer512selective to the silicon oxide material of the tubular silicon oxide spacers511′ and selective to the materials of the insulating layers32, the insulating cap layer70, and the contact-level dielectric layer73. The duration of the second isotropic etch process can be selected such that cylindrical segments of the outer sidewall of the memory film50are physically exposed around the backside recesses43. The recess distance of the second isotropic etch process into the dielectric metal oxide spacer layer512may be in a range from 100% to 200% of the thickness of the dielectric metal oxide spacer layer512. In an illustrative example, the second isotropic etch process may comprise a wet isotropic etch process employing hot phosphoric acid.

The backside recesses43are expanded through the composite dielectric spacer layer51around the memory film50. The dielectric metal oxide spacer layer512can be divided into a vertical stack of tubular dielectric metal oxide spacers512′ having a uniform thickness and having at least one tapered concave annular surface. A subset of the tubular dielectric metal oxide spacers512′ may comprise a respective tapered concave top annular surface and a respective tapered concave bottom annular surface. In one embodiment, the vertical extent of each backside recess43between a vertically neighboring pair of tubular dielectric metal oxide spacers512′ may be greater than the vertical extent of the horizontally-extending portion of the respective backside recess43between a vertically neighboring pair of insulating layers32.

Each contiguous set of a tubular silicon oxide spacer511′ and a tubular dielectric metal oxide spacer512′ constitutes a tubular composite dielectric spacer51′. Generally, the composite dielectric spacer layer51can be divided into a vertical stack of tubular composite dielectric spacers51′ by a combination of isotropic etch processes, such as the combination of the first isotropic etch process and the second isotropic etch process. The vertical stack of tubular composite dielectric spacers51′ laterally surrounds the memory film50, which may comprise a layer stack of a silicon oxide blocking dielectric layer52S, a memory material layer54(which may comprise a charge storage layer), and a dielectric material liner56(which may comprise a tunneling dielectric layer).

The cylindrical plane including the outer sidewalls of the vertical stack of tubular composite dielectric spacers51′ is herein referred to as a first cylindrical plane CP1. The cylindrical plane including the inner sidewalls of the vertical stack of tubular composite dielectric spacers51′ is herein referred to as a second cylindrical plane CP2. According to an aspect of the present disclosure, each tubular silicon oxide spacer511′ within the vertical stack of tubular composite dielectric spacers51′ may have a variable vertical extent that increases with a lateral distance from the first cylindrical plane CP1. In one embodiment, each tubular dielectric metal oxide spacer512′ within the vertical stack of tubular composite dielectric spacers512′ has a variable vertical extent that increases with a lateral distance from the first cylindrical plane CP1.

In one embodiment, the memory film50may comprise a layer stack including a tunneling dielectric layer (comprising the dielectric material liner56) in contact with the vertical semiconductor channel60, a charge storage layer (comprising the memory material layer54) in contact with the tunneling dielectric layer, and a silicon oxide blocking dielectric layer52S in contact with the charge storage layer54and with the vertical stack of tubular composite dielectric spacers51′.

In one embodiment, a vertical cross-sectional profile of a tubular composite dielectric spacer51′ within the vertical stack of tubular composite dielectric spacers51′ comprises a serrated top surface including a concave top surface segment of a tubular silicon oxide spacer511′ of the tubular silicon oxide spacers511′, and a concave top surface segment of a tubular dielectric metal oxide spacer512′ of the tubular dielectric metal oxide spacers512′. In one embodiment, the serrated top surface comprises a first vertical surface segment (which is a first cylindrical surface segment) of the tubular silicon oxide spacer511′ connecting the concave top surface segment of the tubular silicon oxide spacer511′ and the concave top surface segment of the tubular dielectric metal oxide spacer512′.

In one embodiment, the vertical cross-sectional profile of a tubular composite dielectric spacer51′ within the vertical stack of tubular composite dielectric spacers51′ comprises a serrated bottom surface including a concave bottom surface segment of a tubular silicon oxide spacer511′ of the tubular silicon oxide spacers511′, and a concave bottom surface segment of a tubular dielectric metal oxide spacer512′ of the tubular dielectric metal oxide spacers512′. In one embodiment, the serrated bottom surface comprises a second vertical surface segment (which is a second cylindrical surface segment) of the tubular silicon oxide spacer511′ connecting the concave bottom surface segment of the tubular silicon oxide spacer511′ and the concave bottom surface segment of the tubular dielectric metal oxide spacer512′.

Optionally, the second isotropic etching step may be performed in two sub-steps. In a first sub-step, the dielectric metal oxide spacer layer512is partially etched (i.e., part of the thickness of the dielectric metal oxide spacer layer512is etched) using hot phosphoric acid. Then an additional isotropic rounding etch process may be performed to round out or decrease the height of the protruding portions511P of the tubular silicon oxide spacers511′. The additional isotropic rounding etch may comprise a dilute hydrofluoric acid etch. Then the second sub-step of the second isotropic etching step is performed to etch through the entire thickness of the dielectric metal oxide spacer layer512to form the tubular dielectric metal oxide spacers512′.

Referring toFIG.18D, a backside blocking dielectric layer44can be optionally formed. The material composition and the thickness range of the backside blocking dielectric layer44may be the same as in the first exemplary structure.

Subsequently, the processing steps ofFIGS.9E,9F, and9Gcan be performed to sequentially deposit a metallic barrier layer46A and a metallic fill material layer46B, and to remove a continuous metallic material layer46L from inside the backside trenches79and from above the insulating cap layer70. Each remaining portion of the metallic barrier layer46A and the metallic fill material layer46B in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46.

In one embodiment, each of the electrically conductive layers46may be formed with a hammerhead-shaped vertical cross-sectional profile. In one embodiment, the vertical extent of each of the electrically conductive layers46may have a local minimum LM within a cylindrical volume laterally bounded by outer sidewall segments of the memory opening fill structure58that contact the insulating layers32. In one embodiment, the local minimum LM may be located between a first cylindrical plane CP1including outer sidewalls of a vertical stack of tubular composite dielectric spacers51′ within a memory opening fill structure58and a second cylindrical plane CP2including inner sidewalls of the vertical stack of tubular composite dielectric spacers51′. In one embodiment, the local minimum LM may be located along a continuous closed shape (such as a circle or an ellipse) that is equidistant from the first cylindrical plane CP1in a plan view along a vertical direction.

In one embodiment, each of the electrically conductive layers46is spaced from the silicon oxide blocking dielectric layer52S by a respective backside blocking dielectric layer44. In one embodiment, each of the backside blocking dielectric layers44contacts a respective pair of tubular composite dielectric spacers51′ within the vertical stack of tubular composite dielectric spacers41′. Alternatively, the backside blocking dielectric layer44may be omitted. In one embodiment, the maximum vertical extent of one, a plurality, or each, of the electrically conductive layers46within the cylindrical volume is greater than the vertical extent of a horizontally-extending portion of the one, the plurality, or each, of the electrically conductive layers46located outside the cylindrical volume and having a uniform thickness along a vertical direction.

Referring toFIG.18E, the processing steps ofFIG.10can be performed to form an insulating spacer74and a backside contact via structure76in each of the backside trenches79. The processing steps ofFIGS.11A and11Bcan be performed to form various additional contact via structures (88,86,8P). For example, drain contact via structures88can be formed through the contact-level dielectric layer73on each drain region63. Word line contact via structures86can be formed on the electrically conductive layers46through the contact-level dielectric layer73, and through the retro-stepped dielectric material portion65. Peripheral device contact via structures8P can be formed through the retro-stepped dielectric material portion65directly on respective nodes of the peripheral devices.

Referring collectively toFIGS.1-18Eand according to various embodiments of the present disclosure, a semiconductor structure is provided, which comprises: an alternating stack of insulating layers32and electrically conductive layers46; a memory opening49vertically extending through the alternating stack (32,46); and a memory opening fill structure58located in the memory opening49and comprising a vertical semiconductor channel60, a memory film50in contact with the vertical semiconductor channel60, and a vertical stack of tubular composite dielectric spacers51′ laterally surrounding the memory film50, wherein: each of the tubular composite dielectric spacers51′ comprises a respective tubular silicon oxide spacer511′ and a respective tubular dielectric metal oxide spacer512′; and each of the electrically conductive layers46has a hammerhead-shaped vertical cross-sectional profile such that a vertical extent of each of the electrically conductive layers46has a local minimum LM within a cylindrical volume laterally bounded by outer sidewall segments of the memory opening fill structure58.

The various embodiments of the present disclosure may be employed to provide control gate electrodes (i.e., portions of the electrically conductive layers46) having decreased gate tip rounding and improved gate contact width. The memory cell diameter may be reduced and the memory cell shape may be controlled by the methods of the embodiments of the present disclosure. Furthermore, the bit density and effective gate length may be increased to improve device performance. Finally, the device yield and reliability may be improved by allowing a greater space between adjacent memory openings, which reduces defects caused by fluorine degassing during deposition of tungsten electrically conductive layers.

Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.