Patent ID: 12237382

Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, a first feature is formed on a second feature in the description that follows may include embodiments in which the first feature and second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and second feature, so that the first feature and second feature may not be in direct contact.

It should be understood that additional steps may be implemented before, during, or after the illustrated methods, and some steps might be replaced or omitted in other embodiments of the illustrated methods.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “on,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In the present disclosure, the terms “about,” “approximately” and “substantially” typically mean±20% of the stated value, more typically ±10% of the stated value, more typically ±5% of the stated value, more typically ±3% of the stated value, more typically ±2% of the stated value, more typically ±1% of the stated value, and even more typically ±0.5% of the stated value. The stated value of the present disclosure is an approximate value. That is, when there is no specific description of the terms “about,” “approximately” and “substantially”, the stated value includes the meaning of “about,” “approximately” or “substantially”.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the embodiments of the present disclosure.

The present disclosure may repeat reference numerals and/or letters in following embodiments. This repetition is for the purpose of simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In a high-power semiconductor device or a power amplifier having the semiconductor device, such as a high electron mobility transistor (HEMT), an ohmic contact may be formed between the source/drain electrode and the epitaxial structure underneath. The source electrode and the drain electrode are often made of conductive materials (such as metals), while the epitaxial structure may be made of semiconductor materials. The ohmic contact may be referred to as an interface between the metal materials and the semiconductor materials. Through a thermal treatment (for example, an annealing process), one or more metal layers within the source electrode and the drain electrode may be alloyed and extended into the epitaxial structure below. As the extension continues further into the epitaxial structure, the alloyed metal materials may gradually form into one or more spike structures, which may be known as a spike region. The spike region may extend from at least one of the source electrode and the drain electrode. Therefore, a larger contact area between the metal materials and the semiconductor materials may be obtained. The larger contact area allows for a lower contact resistance (Re) of the semiconductor device, which in turn exhibits a more superior performance during operation.

Nevertheless, the larger contact area between the metal materials and the semiconductor materials may also imply a higher probability of current leakage. With a significant amount of current leakage, the operation performance of the semiconductor device may be undermined. In particular, the device breakdown performance may be compromised. For this reason, an inserting structure may be introduced to the semiconductor device of the present application. The inserting structure may be inserted into the epitaxial structure, which can compensate for breakdown loss resulting from the spike structures. As a result, the semiconductor device of the present application is able to demonstrate a sufficiently high breakdown voltage and a relatively low contact resistance simultaneously.

FIG.1is a cross-sectional view of one design of a semiconductor device10, according to some embodiments of the present disclosure. According to some embodiments of the present disclosure, the semiconductor device10may include a high electron mobility transistor (for example, a GaN-based high electron mobility transistor).

Referring toFIG.1, the semiconductor device10may include a substrate100, a buffer layer110, a channel layer120, a barrier layer130, a two-dimensional electron gas (2DEG)140, a cap layer150, an inserting structure200, a passivation layer300, a source electrode310, a first spike region320, a drain electrode330, a second spike region340, and a gate electrode350. The inserting structure200may include a first inserting layer210and a second inserting layer220. The buffer layer110, the channel layer120, the barrier layer130, and the cap layer150may be formed on the substrate100by an epitaxial process and thus may be known as an epitaxial structure. As previously mentioned, the inserting structure200may be inserted within the epitaxial structure, for example, between the channel layer120and the barrier layer130.

In some embodiments, the substrate100may also be, for example, a wafer or a chip, but the present disclosure is not limited thereto. In some embodiments, the substrate100may be a semiconductor substrate, for example, silicon (Si) substrate. Furthermore, in some embodiments, the semiconductor substrate may also be an elemental semiconductor including germanium (Ge), a compound semiconductor including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb), an alloy semiconductor including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and/or gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

In some embodiments, the substrate100may be an n-type or a p-type conductive type. In some embodiments, the substrate100may be a silicon carbide substrate doped with vanadium (V).

In some embodiments, the substrate100may include isolation structures (not shown) to define active regions and to electrically isolate active region elements within or above the substrate100.

Referring toFIG.1, the buffer layer110, the channel layer120, the barrier layer130, and the cap layer150may be sequentially formed on the substrate100. Conventionally, the two-dimensional electron gas140may be formed in the channel layer120near an interface between the channel layer120and the barrier layer130. However, since the inserting structure200are inserted between the channel layer120and the barrier layer130, the two-dimensional electron gas140may be located near the interface between the channel layer120and the inserting structure200.

According to some embodiments, the buffer layer110may alleviate the strain of the overlying channel layer120to be formed subsequently to prevent the generation of defects within the channel layer120. The strain may be caused by a mismatch between the channel layer120and the underlying film. In some embodiments, a nucleation layer may be additionally disposed between the substrate100and the buffer layer110to further alleviate the lattice difference between the substrate100and the overlying film, thereby elevating the crystalline quality. In a specific embodiment of the present disclosure, the buffer layer110may be made of AlwGa1-wN, and w satisfies the condition 0≤w≤0.2, for example, w may be between 0 and 0.1. It should be noted that, when w equals 0, the buffer layer110may be made of pure or substantially pure GaN. The thickness of the buffer layer110may be approximately between 200 Å and 1800 Å.

According to some embodiments, the channel layer120may provide an electron transmission path between the source electrode310and the drain electrode330(described in detail below) of the transistor structure (such as the high electron mobility transistor). In some embodiments, the channel layer120may be doped (for example, with n-type dopants or p-type dopants) or undoped. In a specific embodiment of the present disclosure, the channel layer120may be made of pure or substantially pure GaN. The thickness of the channel layer120may be approximately between 50 Å and 200 Å.

According to some embodiments, the barrier layer130may be made of AlzGa1-zN, and z satisfies the condition 0.18≤z≤0.50, for example, z may be between 0.2 and 0.3, or between 0.3 and 0.5. The thickness of the barrier layer130may be approximately between 80 Å and 260 Å.

According to some embodiments, the ohmic contacts of the source electrode310and the drain electrode330, and the Schottky contact of the gate electrode350are both located on the cap layer150. In a specific embodiment of the present disclosure, the cap layer150may be made of pure or substantially pure GaN. The thickness of the cap layer150may be approximately between 10 Å and 30 Å.

Still referring toFIG.1, the inserting structure200is inserted between the channel layer120and the barrier layer130. The first inserting layer210of the inserting structure200is disposed on the channel layer120. According to some embodiments of the present disclosure, the two-dimensional electron gas140may be generated in the channel layer120near an interface between the channel layer120and the first inserting layer210. In a specific embodiment of the present disclosure, the first inserting layer210may be made of AlxGa1-xN, and x satisfies the condition 0.15≤x≤0.50, for example, x may be between 0.15 and 0.18, or between 0.2 and 0.5. In some embodiments, the aluminum composition (such as x of AlxGa1-xN) is substantially uniform across the entire thickness of the first inserting layer210. The thickness of the first inserting layer210may be approximately between 5 Å and 20 Å.

As shown inFIG.1, the second inserting layer220of the inserting structure200is disposed between the first inserting layer210and the barrier layer130. According to some embodiments of the present disclosure, the aluminum composition of the second inserting layer220is adjusted to be higher than the aluminum composition of the first inserting layer210.

In some embodiments, the combination of the first inserting layer210and the second inserting layer220improves the breakdown voltage of the semiconductor device10.

In a specific embodiment of the present disclosure, the second inserting layer220may be made of AlyGa1-yN, and y satisfies the condition 0.5<y≤1. It should be noted that, when y equals 1, the second inserting layer220may be made of pure or substantially pure aluminum nitride (AlN). The thickness of the second inserting layer220may be approximately between 5 Å and 15 Å.

In some embodiments, the second inserting layer220is made of AlN, and the first inserting layer210is made of AlxGa1-xN (0.2≤x≤0.3). By adjusting the aluminum composition of the first inserting layer210and the aluminum composition of the second inserting layer220, the semiconductor device10may have a higher transconductance peak value compared to the semiconductor device with only the second inserting layer220and without the first inserting layer210.

In some embodiments, the ratio of the thickness of the second inserting layer220to the thickness of the first inserting layer210may be between 0.25 and 3. The thickness of the second inserting layer220and the thickness of the first inserting layer210may be adjusted to improve the cut-off frequency of the semiconductor device10.

Still referring toFIG.1, the ratio of the aluminum composition (such as x of AlxGa1-xN) of the first inserting layer210to the aluminum composition (such as z of AlzGa1-zN) of the barrier layer130may be between 0.5 and 1.5, for example, between 0.8 and 1.2, or for example, 1. In some embodiments, by adjusting the aluminum compositions of the first inserting layer210and the barrier layer130, the Shottky turn-on voltage and the saturation output power of the semiconductor device10may both be improved. Moreover, when the ratio equals 1, or when the aluminum compositions of the first inserting layer210and the barrier layer130are identical, the same material may be used to epitaxially grow the barrier layer130and the first inserting layer210, in which the manufacture of the semiconductor device10may be more simplified with lower cost.

Referring toFIG.1, the source electrode310and the drain electrode330may be formed on the cap layer150. According to some embodiments of the present disclosure, the source electrode310and the drain electrode330are positioned respectively on opposing sides of the subsequently formed gate electrode350. The source electrodes310and the drain electrode330may function respectively as a source terminal and a drain terminal of the transistor structure (such as the high electron mobility transistor) of the semiconductor device10. In a specific embodiment of the present disclosure, the source electrode310and the drain electrode330are made of titanium (Ti), nickel (Ni), aluminum (Al), gold (Au), molybdenum (Mo), platinum (Pt), or a combination thereof.

Still referring toFIG.1, the first spike region320and the second spike region340may be formed under the source electrode310and the drain electrode330, respectively. As shown inFIG.1, the first spike region320and the second spike region340may extend downward into the underlying semiconductor films (such as the buffer layer110, the channel layer120, the barrier layer130, the cap layer150, and the inserting structure200). The ohmic contacts may be defined by the interface between the source electrode310and the cap layer150, and the interface between the drain electrode330and the cap layer150. The first spike region320and the second spike region340may reduce the contact resistance of the transistor structure (such as the high electron mobility transistor) of the semiconductor device10. Materials of the first spike region320and the second spike region340may be similar to those of the source electrode310and the drain electrode330. In a specific embodiment of the present disclosure, the first spike region320and the second spike region340may be made of titanium, titanium nitride (TiN), or a combination thereof.

After the source electrode310and the drain electrode330are formed, a thermal treatment may be performed. The thermal treatment may be carried out in-situ or ex-situ, and may be any types of annealing process, such as rapid thermal anneal (RTA), spike anneal, soak anneal, laser anneal, furnace anneal, or the like. The processing temperature of the thermal treatment may be approximately between 800° C. and 1000° C. The processing temperature may need to be high enough for the metal materials (of the source electrode310and the drain electrode330) to react with the underlying semiconductor materials to form the first spike region320and the second spike region340. Except for the processing temperature, the extension of the first spike region320and the second spike region340may also be determined by the process duration. Moreover, the thermal treatment may be performed in the environment of selected process gas, and the illustrative process gas may include, but are not limited to, nitrogen (N2), ammonia (NH3), oxygen (O2), dinitrogen monoxide (N2O), argon (Ar), helium (He), hydrogen (H2), or the like. As shown inFIG.1, the first spike region320and the second spike region340may be designed to reach into the channel layer120.

Still referring toFIG.1, a passivation layer300may be conformally formed on the surface of the cap layer150, the source electrode310, and the drain electrode330. The passivation layer300may provide protection and insulation of the underlying epitaxial structure, the source electrode310, and the drain electrode330from the subsequently formed elements and the fabrication processes thereof. Even though the passivation layer300of the present application is illustrated to be a single layer, but the present disclosure is not limited thereto. For example, the passivation layer300may include any number of dielectric layers, depending on application and design requirements.

In a specific embodiment of the present disclosure, the passivation layer300may be made of silicon nitride, aluminum nitride, silicon oxide, aluminum oxide, or a combination thereof. The passivation layer300may be formed by chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), the like, or a combination thereof.

Referring toFIG.1, the gate electrode350may be formed on the passivation layer300. In some embodiments, the gate electrode350is located laterally between the source electrode310and the drain electrode330. The gate electrode350may function as a gate terminal of the transistor structure (such as the high electron mobility transistor) of the semiconductor device10. As shown inFIG.1, a portion of the gate electrode350penetrates through the passivation layer300and sits on the cap layer150. The contact area of the portion of the gate electrode350and the cap layer150may be defined as the Schottky contact. In a specific embodiment of the present disclosure, the gate electrode350may be made of nickel, palladium (Pd), platinum, chromium (Cr), gold, titanium, or a combination thereof.

FIG.2is a cross-sectional view of another design of a semiconductor device20, according to some embodiments of the present disclosure. In comparison withFIG.1,FIG.2illustrates a deeper extension of the first spike region320and the second spike region340. For simplicity, the features of the elements having the same reference numerals are similar to those illustrated inFIG.1, and the details are not described again herein to avoid repetition.

Referring toFIG.2, the first spike region320and the second spike region340may extend further into the buffer layer110. The extension of the first spike region320and the second spike region340may be controlled by adjusting the process conditions of the thermal treatment, such as the annealing temperature and/or the annealing time. The deeper extension of the first spike region320and the second spike region340allows for more contact area that may lead to an even lower contact resistance. However, the increased contact area may imply higher current leakage, which causes breakdown degradation. Therefore, the presence of the inserting structure200may be more critical to improve the device performance.

FIG.3is a cross-sectional view of one design of a semiconductor device30, according to other embodiments of the present disclosure. In comparison withFIG.1,FIG.3illustrates different profiles of the first spike region320and the second spike region340. For simplicity, the features of the elements having the same reference numerals are similar to those illustrated inFIG.1, and the details are not described again herein to avoid repetition.

Referring toFIG.3, the first spike region320and the second spike region340may each include a single spike structure. It should be appreciated that, the spike structures are generated from the two-dimensional interface (the ohmic contact) between the source electrode310/the drain electrode330and the cap layer150. Due to the annealing conditions and the different material characteristics at different locations, the generated spike structures may have irregular shapes and patterns across the two-dimensional interface. While the cross-sectional view of the semiconductor device30may illustrate a single spike structure, the first spike region320and the second spike region340may display an entirely different profile from another cross-sectional view. In response to the impact of the spike structures of various profiles, it is imperative to include the inserting structure200to improve the reliability of the device.

FIG.4is a cross-sectional view of another design of a semiconductor device40, according to other embodiments of the present disclosure. In comparison withFIG.3,FIG.4illustrates a deeper extension of the first spike region320and the second spike region340. For simplicity, the features of the elements having the same reference numerals are similar to those illustrated inFIG.1, and the details are not described again herein to avoid repetition.

Referring toFIG.4, the first spike region320and the second spike region340may extend further into the buffer layer110. The extension of the first spike region320and the second spike region340may be controlled by adjusting the process conditions of the thermal treatment, such as the annealing temperature and/or the annealing time. The deeper extension of the first spike region320and the second spike region340allows for more contact area that may lead to an even lower contact resistance. However, the increased contact area may imply higher current leakage, which causes breakdown degradation. Therefore, the presence of the inserting structure200may be more critical to improve the device performance.

FIG.5is a cross-sectional view of one design of a semiconductor device50, according to yet other embodiments of the present disclosure. In comparison withFIG.1,FIG.5illustrates different profiles of the first spike region320and the second spike region340. For simplicity, the features of the elements having the same reference numerals are similar to those illustrated inFIG.1, and the details are not described again herein to avoid repetition.

Referring toFIG.5, only some of the spike structures may extend further into the buffer layer110, while other spike structures may remain in the channel layer120. As stated earlier, due to the annealing conditions and the different material characteristics at different locations, the generated spike structures may have irregular shapes and patterns across the two-dimensional interface. Therefore, it may be understandable that the profiles of the first spike region320and the second spike region340may extend into different films of the epitaxial structure. In response to the impact of the spike structures of various profiles, it is imperative to include the inserting structure200to improve the reliability of the device.

The present disclosure introduces the innovative inserting structure within the epitaxial structure to compensate for the breakdown loss caused by the spike regions under the source electrode and the drain electrode. As a result, the semiconductor device of the present application is able to demonstrate a sufficiently high breakdown voltage and a relatively low contact resistance simultaneously.

The foregoing outlines features of several embodiments so that those skilled in the art will better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection should be determined through the claims. In addition, although some embodiments of the present disclosure are disclosed above, they are not intended to limit the scope of the present disclosure.

Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single embodiment of the disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. One skilled in the prior art will recognize, in light of the description herein, that the disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the disclosure.