Patent ID: 12224711

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the disclosure relate to target voltage generation in an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to generate a time-variant ET voltage based a time-variant target voltage for amplifying a radio frequency (RF) signal modulated for communication in multiple time intervals. In embodiments disclosed herein, the ETIC is self-contained to generate the time-variant target voltage based on a sensed signal having a time-variant sensed envelope that tracks a time-variant power envelope of the RF signal. Since the time-variant target voltage is generated to track the time-variant sensed envelope, which further tracks the time-variant power envelope, the time-variant ET voltage can better track the time-variant power envelope of the RF signal when the time-variant ET voltage is provided to a power amplifier(s) that amplifies the RF signal.

Before discussing target voltage generation in an ETIC according to the present disclosure, starting atFIG.3, an overview of target voltage generation in an existing ETIC is first provided with reference toFIGS.1and2.

FIG.1is a schematic diagram of an exemplary existing ETIC10provided in a power amplifier apparatus12and configured to generate a time-variant variant ET voltage VCCfor amplifying an RF signal14modulated for transmission in multiple time intervals16(1)-16(N). The power amplifier apparatus12includes a transceiver circuit18that is configured to generate and modulate the RF signal14in the time intervals16(1)-16(N) in any modulation bandwidth as shown in Table 1 above. Accordingly, each of the time intervals16(1)-16(N) can have a duration of an orthogonal frequency division multiplexing (OFDM) symbol, which is inversely related to the modulation bandwidth of the RF signal14according to Table 1.

The transceiver circuit18is configured to provide the RF signal14to the existing ETIC10and a signal processing circuit20. In a non-limiting example, the transceiver circuit18can provide the RF signal14to the existing ETIC10and the signal processing circuit20in an intermediate frequency (IF). The signal processing circuit20may be configured to upconvert the RF signal14from the IF to an appropriate carrier frequency and provides the RF signal14to a power amplifier circuit22.

The existing ETIC10is configured to provide the time-variant ET voltage VCCto the power amplifier circuit22for amplifying the RF signal14in each of the time intervals16(1)-16(N). The existing ETIC10is configured to generate the time-variant ET voltage VCCto closely track a time-variant power envelope24associated with the RF signal14. Notably, the time-variant power envelope24can vary (rise or fall) rapidly during each of the time intervals16(1)-16(N). Notably, the power amplifier circuit22is operating as a current source to the existing ETIC10. As a result, any misalignment between the time-variant ET voltage VCCand the time-variant power envelope24will not only reduce operation efficiency and/or linearity of the power amplifier circuit22, but also cause some degree of distortion (e.g., amplitude clipping) to the RF signal14. As such, it is desirable to make sure the existing ETIC10can adapt the time-variant ET voltage VCCin accordance with the time-variant power envelope24in each of the time intervals16(1)-16(N).

In this regard,FIG.2is a schematic diagram of the existing ETIC10inFIG.1configured to generate the time-variant ET voltage VCCto track the time-variant power envelope24. Common elements betweenFIGS.1and2are shown therein with common element numbers and will not be re-described herein.

The existing ETIC10includes a target voltage generation circuit26and an ET voltage circuit28. The target voltage generation circuit26is configured to generate a time-variant target voltage VTGTbased on the time-variant power envelope24associated with the RF signal14. The ET voltage circuit28is configured to generate the time-variant ET voltage VCCbased on the time-variant target voltage VTGT.

The target voltage generation circuit26includes an amplitude detector circuit30and an analog lookup table (LUT) circuit32. The amplitude detector circuit30is configured to determine a time-variant amplitude34based on the time-variant power envelope24of the RF signal14. The analog LUT circuit32is configured to generate the time-variant target voltage VTGTbased on the time-variant amplitude34. In a non-limiting example, the analog LUT circuit32can include an analog LUT (not shown) that correlates the time-variant amplitude34with the time-variant target voltage VTGT. Accordingly, the analog LUT circuit32is configured to generate the time-variant target voltage VTGTbased on the correlation established in the analog LUT.

The ET voltage circuit28includes a voltage amplifier36and an offset capacitor COFF. The voltage amplifier36is configured to generate an initial ET voltage VAMPbased on the time-variant voltage VTGT. The offset capacitor COFFis configured to raise the initial ET voltage VAMPby an offset voltage VOFFto thereby generate the time-variant ET voltage VCC(VCC=VAMP+VOFF). Notably, by providing the offset capacitor COFFto raise the initial ET voltage VAMP, the voltage amplifier36can generate the initial ET voltage VAMPat a lower level than the time-variant ET voltage VCC, thus helping to improve headroom and efficiency of the voltage amplifier36.

The existing ETIC10also includes a switcher circuit38configured to modulate the offset voltage VOFFbased on a battery voltage VBAT. The switcher circuit38can further include a multi-level charge pump (MCP)40and a power inductor42. The MCP40is configured to generate a low-frequency voltage VDCas a function of the battery voltage VBATand in accordance with a duty cycle. The power inductor42is configured to induce a low-frequency current IDCto charge the offset capacitor COFFto thereby modulate the offset voltage VOFF.

As mentioned earlier, the power amplifier circuit22acts as a current source to the existing ETIC10. As such, the time-variant ET voltage VCCwill cause a time-variant load current ILOADto flow through the power amplifier circuit22. Understandably, the time-variant load current ILOADcan go up and down as the time-variant power envelope24increases and decreases. As a result, since the low-frequency current IDCmay be constant, the voltage amplifier36may need to source or sink a high-frequency current IAC(e.g., alternating current) such that the time-variant load current ILOADcan closely track the time-variant power envelope24. In other words, the high-frequency current IACis correlated (e.g., lock stepped) with the time-variant power envelope24.

As such, the high-frequency current IACcan be used as an indicator of the time-variant power envelope24. In embodiments disclosed herein, an ETIC can be configured to generate a time-variant ET voltage in accordance with a time-variant envelope associated with the high-frequency current IAC. Given that the high-frequency current IACis generated internally to the ETIC, the ETIC no longer needs to receive the time-variant power envelope24from the transceiver circuit18. Further, it is also not necessary to employ the amplitude detector circuit30to detect the time-variant amplitude34. As a result, the ETIC can be more self-contained and simplified to help reduce cost and footprint.

In this regard,FIG.3is a schematic diagram of an exemplary ETIC44configured according to an embodiment of the present disclosure to generate a time-variant target voltage VTGTbased on a time-variant sensed envelope46that tracks a time-variant power envelope48of an RF signal50. In an embodiment, the ETIC44includes an ET voltage circuit52and a target voltage generation circuit54. The ET voltage circuit52is configured to generate a time-variant ET voltage VCCbased on the time-variant target voltage VTGTfor amplifying the RF signal50in multiple time intervals56(1)-56(N). In examples discussed herein, each of the time intervals56(1)-56(N) has a duration of an OFDM symbol.

The ET voltage circuit52is further configured to generate a sensed signal58having the time-variant sensed envelope46that tracks the time-variant power envelope48of the RF signal50. The target voltage generation circuit54is configured to generate the time-variant target voltage VTGTbased on the time-variant sensed envelope46to thereby cause the time-variant ET voltage VCCto track the time-variant power envelope48of the RF signal50. Since the sensed signal58is generated internally in the ETIC44, the ETIC44can become more self-contained to generate the time-variant target voltage VTGTand the time-variant ET voltage VCCwithout requiring the amplitude detector circuit30as required in the existing ETIC10ofFIG.2and relying on the transceiver circuit18in the power amplifier apparatus12ofFIG.1to provide the time-variant power envelope24. As a result, the ETIC44can be built with lower cost, smaller footprint, and reduced complexity.

The ET voltage circuit52includes a voltage amplifier60and an offset capacitor COFF. The voltage amplifier60is configured to generate an initial ET voltage VAMPbased on the time-variant voltage VTGT. The offset capacitor COFFis configured to raise the initial ET voltage VAMPby an offset voltage VOFFto thereby generate the time-variant ET voltage VCC(VCC=VAMP+VOFF). Notably, by providing the offset capacitor COFFto raise the initial ET voltage VAMP, the voltage amplifier60can generate the initial ET voltage VAMPat a lower level than the time-variant ET voltage VCC, thus helping to improve headroom and efficiency of the voltage amplifier60.

The ETIC44also includes a switcher circuit62configured to modulate the offset voltage VOFFbased on a battery voltage VBAT. The switcher circuit62can further include an MCP64and a power inductor66. The MCP64is configured to generate a low-frequency voltage VDCas a function of the battery voltage VBATand in accordance with a duty cycle. In a non-limiting example, the MCP64can generate the low-frequency voltage VDCat 0×VBAT(0 V), 1×VBAT, or 2×VBATbased on the duty cycle. For example, if the battery voltage VBATis 5 V and the duty cycle is 30% at 0×VBAT(0 V), 30% at 1×VBAT, and 40% at 2×VBAT, the MCP64will then generate the low-frequency voltage VDCat 5.5 V (0×30%+5×30%+10×40%). The power inductor66is configured to induce a low-frequency current IDCto charge the offset capacitor COFFto thereby modulate the offset voltage VOFF.

The ETIC44is configured to provide the time-variant ET voltage VCCto a power amplifier circuit68, which acts as a current source to the ETIC44. In this regard, like the voltage amplifier36in the existing ETIC10, the voltage amplifier60also needs to source or sink a high-frequency current IAC(e.g., alternating current) such that the time-variant load current ILOADcan closely track the time-variant power envelope48.

In an embodiment, the voltage amplifier60is configured to generate the sensed signal58to reflect an amount of the high-frequency current IACthat is sourced or sunk by the voltage amplifier60in accordance with the time-variant power envelope48. In one embodiment, the sensed signal58can be a sensed current ISENSE. Accordingly, the time-variant sensed envelope46can represent a time-variant current envelope of the high-frequency current IACthat tracks the time-variant power envelope48of the RF signal50. In another embodiment, the sensed signal58can be a sensed voltage VSENSE(e.g., converted from the sensed current ISENSE). Accordingly, the time-variant sensed envelope46can represent a time-variant voltage envelope (e.g., derived from the time-variant current envelope of the high-frequency current IAC) that tracks the time-variant power envelope48of the RF signal50.

FIG.4is a graphic diagram providing an exemplary illustration of the time-variant sensed envelope46that closely tracks the time-variant power envelope48of the RF signal50inFIG.3.FIG.4illustrates three consecutive symbols SN−1, SN, and SN+1, which can represent any three consecutive time intervals among the time intervals56(1)-56(N). As shown, the time-variant sensed envelope46is in lock step with the time-variant power envelope48in each of the symbols SN−1, SN, and SN+1. As such, the time-variant sensed envelope46can be treated as a replica of the time-variant power envelope48.

With reference back toFIG.3, the target voltage generation circuit54includes a detection circuit70and a voltage selection circuit72. The detection circuit70is configured to detect one or more peaks74(shown inFIGS.5and6) of the time-variant sensed envelope46in a respective one of the time intervals56(1)-56(N). As discussed inFIGS.5and6, next, the voltage selection circuit72is configured to cause the time-variant target voltage VTGTto increase in response to the detection circuit70detecting the peaks in the respective one of the time intervals56(1)-56(N).

FIGS.5and6are graphic diagrams providing exemplary illustrations as to how the voltage selection circuit72can be configured according to embodiments of the present disclosure to generate the time-variant target voltage VTGTbased on the detected peaks74in the time-variant sensed envelope46. Similar toFIG.4,FIGS.5and6each illustrate three consecutive symbols SN−1, SN, and SN+1, which can represent any three consecutive time intervals among the time intervals56(1)-56(N). Common elements betweenFIGS.5and6are shown therein with common element numbers and will not be re-described herein.

With reference toFIG.5, the detection circuit70may be configured to detect each of the peaks74in the time-variant sensed envelope46in response to the time-variant sensed envelope46being higher than a peak detection threshold PTH, which can be a function of an average (e.g., root-mean-square (RMS) average) of the time-variant ET voltage VCCacross the symbols SN−1, SN, and SN+1. In a non-limiting example, if the time-variant sensed envelope46represents the time-variant current envelope associated with the sensed current ISENSE, then the peak detection threshold PTHcan be determined based on a programmed RMS level of the time-variant ET voltage VCCand an expected range of load-line impedance value.

At a start of each of the symbols SN−1, SN, and SN+1, the voltage selection circuit72is configured to set the time-variant target voltage VTGTat a starting level VTGT-START. In the embodiment illustrated inFIG.5, the starting level VTGT-STARTis set by decaying the time-variant target voltage VTGTfrom a level set at an end of a previous (e.g., immediately preceding) symbol until a first of the peaks74(e.g., at time T1, T3, T5) of the time-variant sensed envelope46is detected in the symbol. For example, at the start of the symbol SN(e.g., time T2), the voltage selection circuit72is configured to cause the time-variant target voltage VTGTto decay from a previous level VTGT(N−1) set at the end of the preceding symbol SN−1until a first one of the peaks74is detected (e.g., at time T3) during the symbol SN. Similarly, at the start of the symbol SN+1(e.g., time T4), the voltage selection circuit72is configured to cause the time-variant target voltage VTGTto decay from a previous level VTGT(N) set at the end of the preceding symbol SNuntil a first one of the peaks74is detected (e.g., at time T5) during the symbol SN+1.

Alternatively, as shown inFIG.6, the voltage selection circuit72can set the starting level at the start of the symbols SN−1, SN, and SN+1by decaying the time-variant target voltage VTGTfrom a level set at the end of a previous (e.g., immediately preceding) symbol to a predefined minimum target voltage VTGT-MIN.

With reference back toFIG.5, in response to detecting the first one of the peaks74in a respective one of the symbols SN−1, SN, and SN+1, the voltage selection circuit72is configured to cause the time-variant target voltage VTGTto increase from the starting level VTGT-STARTto a respective one of levels VTGT(N−1), VTGT(N), and VTGT(N+1). Each of the levels VTGT(N−1), VTGT(N), and VTGT(N+1) may be determined as a function of an expected peak-to-average ratio (PAR) in the respective one of the symbols SN−1, SN, and SN+1. For example, each of the levels VTGT(N−1), VTGT(N), and VTGT(N+1) can be expressed by equation (Eq. 1) below:
VCC-RMS*10(PAR/20)(Eq. 1)

In the equation (Eq. 1) above, VCC-RMSrepresents an RMS average of the time-variant ET voltage VCCacross the symbols SN−1, SN, and SN+1and PAR represents an expected PAR in a respective one of the symbols SN−1, SN, and SN+1. In a non-limiting example, the time-variant target voltage VTGTcan be increased only once in each of the symbols SN−1, SN, and SN+1.

With reference back toFIG.3, in an embodiment, the detection circuit70can be configured to provide a digital indication signal76to the voltage selection circuit72in response to detecting the peaks74of the time-variant sensed envelope46in each of the symbols SN−1, SN, and SN+1. In a non-limiting example, the digital indication signal76can include a coded digital word DWordthat indicates the detected peaks74of the time-variant sensed envelope46. In one embodiment, the coded digital word DWordcan be a single-bit binary word encoded as one (“1”) to indicate that the peaks74are detected or zero (“0”) to indicate that the peaks74are not detected. Understandably, the single-bit binary word is used if the peak detection threshold PTHis the sole threshold used for detecting the peaks74.

In another embodiment, the coded digital word DWordcan be a multi-bit binary word if multiple thresholds are used for detecting the peaks74. For example, if two peak detection thresholds PTHLand PTHH(PTHH>PTHL) are employed for detecting the peaks74, then the coded digital word DWordcan be a 2-bit binary word. The 2-bit binary word may be encoded as “00,” “01,” “10,” or “11” to indicate respectively that the peaks74above both PTHHand PTHLare not detected, the peaks74above both PTHHand PTHLare detected, the peaks74below PTHHbut above PTHLare not detected, or the peaks74below PTHHbut above PTHLare detected. It should be appreciated that the multi-bit binary word can help improve granularities in peak detection and target voltage generation.

The voltage selection circuit72be configured to generate a time-variant digital target voltage DVTGTbased on the coded digital word DWordreceived in the digital indication signal76. In a non-limiting example, the voltage selection circuit72can convert the coded digital word DWordinto the time-variant digital target voltage DVTGTbased on a digital LUT. Specifically, the voltage selection circuit72can be configured to increase the time-variant digital target voltage DVTGTin response to receiving the coded digital word DWordthat indicates the detected peaks74of the time-variant sensed envelope46.

The target voltage generation circuit54can further include a digital-to-analog converter (DAC)78. The DAC78is configured to convert the time-variant digital target voltage DVTGTinto the time-variant target voltage VTGT. In this regard, the voltage selection circuit72can cause the time-variant target voltage VTGTto increase by increasing the time-variant digital target voltage DVTGT.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.