Patent ID: 12199797

DETAILED DESCRIPTION

Preferred embodiments and their advantages are best understood by reference toFIGS.1through3, wherein like numbers are used to indicate like and corresponding parts.

For the purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, an information handling system may be a personal computer, a personal digital assistant (PDA), a consumer electronic device, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include memory, one or more processing resources such as a central processing unit (“CPU”) or hardware or software control logic. Additional components of the information handling system may include one or more storage devices, one or more communications ports for communicating with external devices as well as various input/output (“I/O”) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communication between the various hardware components.

For the purposes of this disclosure, computer-readable media may include any instrumentality or aggregation of instrumentalities that may retain data and/or instructions for a period of time. Computer-readable media may include, without limitation, storage media such as a direct access storage device (e.g., a hard disk drive or floppy disk), a sequential access storage device (e.g., a tape disk drive), compact disk, CD-ROM, DVD, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and/or flash memory; as well as communications media such as wires, optical fibers, microwaves, radio waves, and other electromagnetic and/or optical carriers; and/or any combination of the foregoing.

For the purposes of this disclosure, information handling resources may broadly refer to any component system, device or apparatus of an information handling system, including without limitation processors, service processors, basic input/output systems, buses, memories, I/O devices and/or interfaces, storage resources, network interfaces, motherboards, and/or any other components and/or elements of an information handling system.

For the purposes of this disclosure, circuit boards may broadly refer to printed circuit boards (PCBs), printed wiring boards (PWBs), printed wiring assemblies (PWAs), etched wiring boards, and/or any other board or similar physical structure operable to mechanically support and electrically couple electronic components (e.g., packaged integrated circuits, slot connectors, etc.). A circuit board may comprise a substrate of a plurality of conductive layers separated and supported by layers of insulating material laminated together, with conductive traces disposed on and/or in any of such conductive layers, with vias for coupling conductive traces of different layers together, and with pads for coupling electronic components (e.g., packaged integrated circuits, slot connectors, etc.) to conductive traces of the circuit board.

FIG.1illustrates a system100comprising a plurality of chassis101, each chassis101comprising at least one information handling system102, in accordance with embodiments of the present disclosure. Each chassis101may be an enclosure that serves as a container for various information handling systems102and information handling resources104, and may be constructed from steel, aluminum, plastic, and/or any other suitable material. Although the term “chassis” is used, a chassis101may also be referred to as a case, cabinet, tower, box, enclosure, and/or housing. In certain embodiments, a chassis101may be configured to hold and/or provide power to one or more information handling systems102and/or information handling resources104.

In some embodiments, one or more of information handling systems102may comprise servers. For example, in some embodiments, information handling systems102may comprise rack servers and each chassis101may comprise a rack configured to house such rack servers. As shown inFIG.1, each information handling system102may include one or more information handling resources104. An information handling resource104may include any component system, device or apparatus of an information handling system102, including without limitation processors, service processors, basic input/output systems, buses, memories, I/O devices and/or interfaces, storage resources, network interfaces, motherboards, air movers, sensors, power supplies, and/or any other components and/or elements of an information handling system. For example, in some embodiments, an information handling resource104of an information handling system102may comprise a processor. Such processor may include any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include, without limitation, a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, a processor may interpret and/or execute program instructions and/or process data stored in a memory and/or another information handling resource of an information handling system102.

In these and other embodiments, an information handling resource104of an information handling system102may comprise a memory. Such a memory may be communicatively coupled to an associated processor and may include any system, device, or apparatus configured to retain program instructions and/or data for a period of time (e.g., computer-readable media). A memory may include RAM, EEPROM, a PCMCIA card, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and/or array of volatile or non-volatile memory that retains data after power to an associated information handling system102is turned off.

In addition to a processor and/or a memory, an information handling system102may include one or more other information handling resources.

As shown inFIG.1, information handling resources104may be communicatively coupled to each other via a cable106, whether such information handling resources104are within different information handling systems102in the same chassis101, or are in different chassis101. A cable106may include any suitable assembly of two or more electrically-conductive wires running side by side to carry one or more signals between information handling resources. In some embodiments, cable106may comprise a smart cable, as described in greater detail below.

FIG.2illustrates a block diagram of an example subsystem comprising a transmitter202, smart cable106, and a receiver204, in accordance with embodiments of the present disclosure. Smart cable106as shown inFIG.2may be used to implement one or more cables106depicted inFIG.1.

Transmitter202may comprise any suitable system, device, or apparatus configured to communicate a differential signal IN to receiver204via a smart cable106. In addition, as shown inFIG.2, transmitter202may provide a voltage rail VDD to smart cable106to provide electrical energy for powering functionality of circuit board212integral to cable106. Further, as described in greater detail below, transmitter202may also be configured for bidirectional communication with circuit board212of smart cable106for communication of system information SYS INTERFACE, which may include telemetry, debug, and/or training information between transmitter202and circuit board212.

Further, receiver204may comprise any suitable system, device, or apparatus configured to receive a differential signal OUT from transmitter202via smart cable106, wherein such differential signal OUT is a function of differential signal IN as processed by smart cable106.

For purposes of clarity and exposition,FIG.2contemplates only single-direction communication from transmitter202and receiver204. However, in some embodiments, transceivers may be present in lieu of both of transmitter202and receiver204, thus enabling bidirectional communication of bidirectional signals.

Smart cable106may have a plurality of wires, including communication wires201and203, power wire206, and system interface wire208. Other wires integral to smart cable106may not be shown inFIG.2in order to aid in clarity and exposition ofFIG.2. As shown inFIG.2, smart cable106may include a small printed circuit board212communicatively coupled to communication wires201and203, power wire206, and system interface wire208. For example, in some embodiments, printed circuit board212may be approximately the size of a postage stamp. Printed circuit board212may be integrated within smart cable106in any suitable manner, including without limitation in one or more paddle boards at the ends of smart cable106, a circuit board in the middle of the cable, or on one or more system boards to which smart cable106electrically couples.

AlthoughFIG.2shows voltage rail VDD provided by transmitter202via power wire206for purposes of clarity and exposition, in some embodiments, such voltage rail VDD may be provided by another component of an information handling system102or chassis101in which smart cable106resides. In addition, althoughFIG.2shows system information SYS INTERFACE interfaced between transmitter202and circuit board212via system interface wire208for purposes of clarity and exposition, in some embodiments, system information SYS INTERFACE may be interfaced between circuit board212and a host system of an information handling system102(e.g., via a sideband Inter-Integrated Circuit (I2C) interface).

FIG.3illustrates selected components of an example circuit board212that may be used within smart cable106, in accordance with embodiments of the present disclosure. As shown inFIG.3, circuit board212may include a first band-pass filter322a, a second band-pass filter322b, a first peak detector324a, a second peak detector324b, logic308, a first deskewer310a, a second deskewer310b, a crosstalk filter312, a common-mode filter314, a first attenuator316a, a second attenuator316b, and a differential redriver318. Circuit board212may also include first input trace302a, second input trace302b, system interface trace304, first output trace306a, and second output trace306b.

First band-pass filter322amay receive first polarity input signal IN+ via first input trace302aand may be configured to select a particular frequency (e.g., the Nyquist frequency) of first polarity input signal IN+. In other words, first band-pass filter322amay filter first polarity input signal IN+ to include only a frequency band near the particular frequency. Similarly, second band-pass filter322bmay be configured to select the particular frequency of second polarity input signal IN−. In other words, second band-pass filter322bmay filter second input signal IN− to include only a frequency band near the particular frequency.

First peak detector324amay be configured to receive the output of first band-pass filter322aand measure a first amplitude of first polarity input signal IN+ at the particular frequency. Similarly, second peak detector324bmay be configured to receive the output of second band-pass filter322band measure a second amplitude of second polarity input signal IN− at the particular frequency.

Logic308may comprise any suitable system, device, or apparatus configured to perform functionality of logic308described below. Thus, logic308may include a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or another digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, logic308may include a program of executable instructions embodied on computer-readable media and configured to execute on a processing device to carry out the functionality of logic308.

Logic308may be configured to receive the measurements of the first amplitude of first polarity input signal IN+ at the particular frequency and the second amplitude of second polarity input signal IN− at the particular frequency and perform processing to generate control signals for first deskewer310a, second deskewer310b, first attenuator316a, second attenuator316b, and differential redriver318, as described below.

For example, a difference in the amplitudes of first polarity input signal IN+ at the particular frequency and second polarity input signal IN− at the particular frequency may be indicative of a signal skew of the differential pair of signals. In particular, the difference between amplitudes of first polarity input signal IN+ and second polarity input signal IN− may be proportional to the signal skew of the differential pair of signals. Accordingly, based on the difference, logic308may be configured to generate control signals, in particular first bias signal BIAS+ and second bias signal BIAS−, based on the difference of the first amplitude and the second amplitude to adjust speed and/or timing of one or both of first polarity input signal IN+ and second polarity input signal IN−. In some embodiments, such generation of first bias signal BIAS+ and second bias signal BIAS− may be in accordance with the systems and methods disclosed in either or both of U.S. patent application Ser. No. 18/314,216 filed May 9, 2023 (the “216 Application”) and U.S. patent application Ser. No. 18/448,380 filed Aug. 11, 2023 (the “'380 Application”), both of which are incorporated by reference herein in their entireties.

First deskewer310amay modify a propagation delay of the signal path of first polarity input signal IN+ as a function of first bias signal BIAS+. For example, as a delay of first polarity input signal IN+ relative to second polarity input signal IN− increases, first bias signal BIAS+ may increase, decreasing a propagation delay of the signal path of first polarity input signal IN+. As another example, as the delay of first polarity input signal IN+ relative to second polarity input signal IN− decreases, first bias signal BIAS+ may decrease, increasing a propagation delay of first polarity input signal IN+.

Similarly, second deskewer310bmay modify a propagation delay of the signal path of second polarity input signal IN− as a function of second bias signal BIAS−. For example, as a delay of second polarity input signal IN− relative to first polarity input signal IN+ increases, second bias signal BIAS− may increase, decreasing a propagation delay of the signal path of second polarity input signal IN−. As another example, as the delay of second polarity input signal IN− relative to first polarity input signal IN+ decreases, second bias signal BIAS− may decrease, increasing a propagation delay of second polarity input signal IN−.

In some embodiments, such modification of the propagation delay of the signal path of first polarity input signal IN+ as a function of first bias signal BIAS+ and modification of the propagation delay of the signal path of second polarity input signal IN− as a function of first bias signal BIAS− may be in accordance with those systems and methods disclosed in either or both of the '216 Application or the '380 Application.

As a result, increases and decreases to the propagation delays of the signal path of first polarity signal IN+ and the signal path of second polarity input signal IN− responsive to the presence of skew may compensate for such skew.

Crosstalk filter312may comprise any suitable electromagnetic coupler device configured to mitigate or eliminate capacitive crosstalk between the signal path of first polarity signal IN+ and the signal path of second polarity input signal IN−. In some embodiments, crosstalk filter312may be in accordance with the systems and methods disclosed in U.S. patent application Ser. No. 17/451,969 filed Oct. 22, 2021 (the “'969 Application”), which is incorporated by reference herein in its entirety. Accordingly, in operation, crosstalk filter312may receive the differential signal output from first deskewer310aand second deskewer310band generate a resulting differential signal in which any crosstalk present between the positive and negative polarity components of the differential signal may be mitigated or eliminated.

Common-mode filter314may comprise any suitable system, device, or apparatus configured to mitigate or eliminate the presence of common mode noise on the signal paths of first polarity signal IN+ and second polarity input signal IN−. For example, in some embodiments, common-mode filter314may be implemented using a common-mode choke. As another example, in other embodiments, common-mode filter314may be implemented using a ground trace between traces of the differential signal paths of first polarity signal IN+ and second polarity input signal IN−, as set forth in the systems and methods described in U.S. patent application Ser. No. 17/726,189 filed Apr. 21, 2021 (the “189 Application”), which is incorporated by reference herein in its entirety. Accordingly, in operation, common-mode filter314may receive the differential signal output from crosstalk filter312and generate a resulting differential signal in which any common-mode noise present in the differential signal may be mitigated or eliminated.

There may be instances when a channel has very low loss (e.g., due to a short cable). In such cases, first polarity input signal IN+ and second polarity input signal IN− may be very strong and may potentially create excessive crosstalk, may overdrive a receiver input, and/or may cause other undesirable issues. Thus, logic308may be configured to generate a control signal, in particular attenuation signal ATTEN, based on the first amplitude and the second amplitude (e.g., based on an average of the first amplitude and the second amplitude). First attenuator316amay modify an attenuation of the signal path of first polarity input signal IN+ as a function of attenuation signal ATTEN. Similarly, second attenuator316bmay modify an attenuation of the signal path of second polarity input signal IN− as a function of attenuation signal ATTEN. For example, as the first amplitude and/or the second amplitude increase, attenuation signal ATTEN may increase, increasing attenuation of the signal paths of first polarity input signal IN+ and second polarity input signal IN−. As another example, as the first amplitude and/or the second amplitude decrease, attenuation signal ATTEN may decrease, decreasing attenuation of the signal paths of first polarity input signal IN+ and second polarity input signal IN−.

In some embodiments, such modification of the variable attenuation of the signal path of first polarity input signal IN+ as a function of first attenuation signal ATTEN and modification of the variable attenuation of the signal path of second polarity input signal IN− as a function of first attenuation signal ATTEN may be in accordance with those systems and methods disclosed in the '643 Application.

Differential redriver318may comprise an amplifier with a variable gain GAIN, controlled by logic308. In some embodiments, logic308may set variable gain GAIN based on cable properties pre-stored in logic308or memory accessible by logic308. In other embodiments, logic308may set variable gain GAIN based on measurements from first peak detector324aand/or second peak detector324b, to ensure that the differential output signal generated from smart cable106(and thus received by receiver204) is properly conditioned for processing by receiver204.

As mentioned above, logic308may be configured to receive information (e.g., training information for logic308, etc.) from and/or transmit information (e.g., telemetry information, debug information, etc. from logic308) to transmitter202, a host system of an information handling system102, and/or another component.

As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

Although exemplary embodiments are illustrated in the figures and described above, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the figures and described above.

Unless otherwise specifically noted, articles depicted in the figures are not necessarily drawn to scale.

All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.

Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description.

To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.