Patent ID: 12218218

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

The nanostructure transistor (e.g. nanosheet transistor, nanowire transistor, multi-bridge channel, nano-ribbon FET, gate all around (GAA) transistor structures) described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure may include nanostructures formed over a substrate and a gate structure wraps around the nanostructures. The fin structure is formed over the substrate, and the fin structure includes a number of first semiconductor layers and a number of second semiconductor layers. The hard mask layer is formed over the fin structure and is patterned to form the trench. The gate spacer layer is formed in the trench and the dummy gate electrode layer (e.g. polysilicon) is formed on the gate spacer layer and in the trench. Note that the formation of the dummy gate electrode layer is after the gate spacer layer without using the photoresist layer. Therefore, the dummy gate structure has a low aspect ratio to reduce the risk of the dummy gate electrode layer (e.g. polysilicon) collapse. Therefore, the yield of the semiconductor device structure is improved.

FIG.1shows a top view of a semiconductor structure100, in accordance with some embodiments.FIG.1has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features may be added in the semiconductor structure100, and some of the features described below may be replaced, modified, or eliminated.

The semiconductor structure100may include multi-gate devices and may be included in a microprocessor, a memory, or other IC devices. For example, the semiconductor structure100may be a portion of an IC chip that include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other applicable components, or combinations thereof.

FIGS.2A to2Willustrate perspective views of intermediate stages of manufacturing a semiconductor structure100ain accordance with some embodiments. More specifically,FIGS.2A to2Willustrate diagrammatic perspective views of intermediate stages of manufacturing the semiconductor structure100ashown inFIG.1.

As shown inFIG.2A, a substrate102is provided. The substrate102may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate102may include other elementary semiconductor materials such as germanium. In some embodiments, the substrate102is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the substrate102is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate102includes an epitaxial layer. For example, the substrate102has an epitaxial layer overlying a bulk semiconductor.

A number of first semiconductor layers106and a number of second semiconductor layers108are sequentially alternately formed over the substrate102. The first semiconductor layers106and the second semiconductor layers108are vertically stacked to form a stacked nanostructures structure (or a stacked nanosheet or a stacked nanowire).

In some embodiments, the first semiconductor layers106and the second semiconductor layers108independently include silicon (Si), germanium (Ge), silicon germanium (Si1-xGex, 0.1<x<0.7, the value x is the atomic percentage of germanium (Ge) in the silicon germanium), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), or another applicable material. In some embodiments, the first semiconductor layer106and the second semiconductor layer108are made of different materials.

The first semiconductor layers106and the second semiconductor layers108are made of different materials having different lattice constant. In some embodiments, the first semiconductor layer106is made of silicon germanium (Si1-xGex, 0.1<x<0.7), and the second semiconductor layer108is made of silicon (Si). In some other embodiments, the first semiconductor layer106is made of silicon (Si), and the second semiconductor layer108is made of silicon germanium (Si1-xGex, 0.1<x<0.7).

In some embodiments, the first semiconductor layers106and the second semiconductor layers108are formed by a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process (e.g. low-pressure CVD (LPCVD), plasma enhanced CVD (PECVD)), a molecular epitaxy process, or another applicable process. In some embodiments, the first semiconductor layers106and the second semiconductor layers108are formed in-situ in the same chamber.

In some embodiments, the thickness of each of the first semiconductor layers106is in a range from about 5 nanometers (nm) to about 10 nm. Terms such as “about” in conjunction with a specific distance or size are to be interpreted as not to exclude insignificant deviation from the specified distance or size and may include for example deviations of up to 20%. In some embodiments, the first semiconductor layers106are substantially uniform in thickness. In some embodiments, the thickness of each of the second semiconductor layers108is in a range from about 5 nm to about 10 nm. In some embodiments, the second semiconductor layers108are substantially uniform in thickness.

Then, as shown inFIG.2B, the first semiconductor layers106and the second semiconductor layers108are patterned to form fin structures104-1,104-2,104-3,104-4,104-5, in accordance with some embodiments of the disclosure. In some embodiments, the fin structures104-1,104-2,104-3,104-4,104-5, include base fin structures105and the semiconductor material stacks, including the first semiconductor layers106and the second semiconductor layers108, formed over the base fin structure105. In some embodiments, each of the fin structures104-1,104-2,104-3,104-4,104-5has different widths along the horizontal direction.

In some embodiments, the patterning process includes forming mask structures110over the semiconductor material stack, and etching the semiconductor material stack and the underlying substrate102through the mask structure110. In some embodiments, the mask structures110are a multilayer structure including a pad oxide layer112and a nitride layer114formed over the pad oxide layer112. The pad oxide layer112may be made of silicon oxide, which may be formed by thermal oxidation or CVD, and the nitride layer114may be made of silicon nitride, which may be formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).

Afterwards, as shown inFIG.2C, a liner (not shown) is formed to cover the fin structures104-1,104-2,104-3,104-4,104-5, and an insulating layer (not shown) is formed around the fin structures104-1,104-2,104-3,104-4,104-5over the liner, in accordance with some embodiments of the disclosure. In some embodiments, the liner is made of an oxide and a nitride. In some embodiments, the liner is omitted. In some embodiments, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof.

Afterwards, the insulating layer and the liner are recessed to form an isolation structure116, in accordance with some embodiments. The isolation structure116is configured to electrically isolate active regions (e.g. the fin structures104-1and104-2) of the semiconductor structure and is also referred to as shallow trench isolation (STI) feature in accordance with some embodiments.

Afterwards, as shown inFIG.2D, the isolation structure116is formed, cladding layers118are formed over the top surfaces and the sidewalls of the fin structures104-1and104-2over the isolation structure116, in accordance with some embodiments. In some embodiments, the cladding layers118are made of semiconductor materials. In some embodiments, the cladding layers118are made of silicon germanium (SiGe). In some embodiments, the cladding layers118and the first semiconductor layers106are made of the same semiconductor material.

The cladding layer118may be formed by performing an epitaxy process, such as VPE and/or UHV CVD, molecular beam epitaxy, other applicable epitaxial growth processes, or combinations thereof. After the cladding layers118are deposited, an etching process may be performed to remove the portion of the cladding layer118not formed on the sidewalls of the fin structures104-1,104-2,104-3,104-4,104-5, for example, using a plasma dry etching process. In some embodiments, the portions of the cladding layers118formed on the top surface of the fin structures104-1,104-2,104-3,104-4,104-5are partially or completely removed by the etching process, such that the thickness of the cladding layer118over the top surface of the fin structures104-1,104-2,104-3,104-4,104-5is thinner than the thickness of the cladding layer118on the sidewalls of the fin structures104-1,104-2,104-3,104-4,104-5.

Before the cladding layers118are formed, a semiconductor liner (not shown) may be formed over the fin structures104-1,104-2,104-3,104-4,104-5. The semiconductor liner may be a Si layer and may be incorporated into the cladding layers118during the epitaxial growth process for forming the cladding layers118.

Next, as shown inFIG.2E, a liner layer120and a filling layer122are sequentially formed over the cladding layers118and the isolation structure116, in accordance with some embodiments. In some embodiments, the liner layer120is made of a low k dielectric material having a k value lower than 7. In some embodiments, the liner layer120is made of SiN, SiCN, SiOCN, SiON, or the like. The liner layer120may be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other applicable methods, or combinations thereof. In some embodiments, the liner layer120has a thickness in a range from about 2 nm to about 8 nm.

After the liner layer120is formed, the filling layer122is formed over the liner layer120to completely fill the spaces between the adjacent fin structures104-1and104-2, and a polishing process is performed until the top surfaces of the cladding layers118are exposed, in accordance with some embodiments.

In some embodiments, the filling layer122and the liner layer120are both made of oxide but are formed by different methods. In some embodiments, the filling layer122is made of SiN, SiCN, SiOCN, SiON, or the like. The filling layer122may be deposited using a flowable CVD (FCVD) process that includes, for example, depositing a flowable material (such as a liquid compound) and converting the flowable material to a solid material by a suitable technique, such as thermal annealing and/or ultraviolet radiation treating.

Next, as shown inFIG.2F, recesses124are formed between the fin structures104-1and104-2, in accordance with some embodiments. In some embodiments, the filling layer122and the liner layer120are recessed by performing an etching process. In some embodiments, the filling layer122are formed using a flowable CVD process, so that the resulting filling layer122can have a relatively flat top surface after the etching process is performed.

Afterwards, as shown inFIG.2G, a cap layer126is formed in the recesses124, thereby forming dielectric features134, in accordance with some embodiments. In some embodiments, the dielectric features134include dielectric features134-1,134-2,134-3,134-4at opposite sides of the fin structures104-1and104-2. In some embodiments, each of the dielectric features134-1,134-2,134-3,134-4has different width along the horizontal direction.

In some embodiments, the cap layer126is made of a high k dielectric material, such as HfO2, ZrO2, HfAlOx, HfSiOx, Al2O3, or the like. The dielectric materials for forming the cap layer126may be formed by performing ALD, CVD, PVD, oxidation-based deposition process, other suitable process, or combinations thereof. After the cap layers126are formed, a CMP process is performed until the mask structures110are exposed in accordance with some embodiments. The cap layers126should be thick enough to protect the dielectric features134during the subsequent etching processes, so that the dielectric features134may be used to separate the adjacent source/drain structures formed afterwards.

Next, as shown inFIG.2H, the mask structures110over the fin structures104-1,104-2,104-3,104-4,104-5and the top portions of the cladding layers118are removed to expose the top surfaces of the topmost second semiconductor material layers108, in accordance with some embodiments. In some embodiments, the top surfaces of the cladding layers118are substantially level with the top surfaces of the topmost second semiconductor layers108.

The mask structures110and the cladding layers118may be recessed by performing one or more etching processes that have higher etching rate to the mask structures110and the cladding layers118than the dielectric features134, such that the dielectric features134are only slightly etched during the etching processes. The selective etching processes can be dry etching, wet drying, reactive ion etching, or other applicable etching methods.

Afterwards, as shown inFIG.2I, a first oxide layer136is formed over the cap layer126, and the topmost second semiconductor layer108and the cladding layer118, in accordance with some embodiments. The first oxide layer136is conformally formed on the cap layer126, and therefore the spaces between two adjacent cap layers126that are not filled with the first oxide layer136.

In some embodiments, the first oxide layer136is made of silicon oxide or another applicable material. In some embodiments, the first oxide layer136is formed by a deposition process, such as CVD process, ALD process, another applicable process, or a combination thereof.

Afterwards, as shown inFIG.2J, a first hard mask layer138is formed over the first oxide layer136, and a second oxide layer140is formed over the first hard mask layer138, in accordance with some embodiments. In addition, the first hard mask layer138is filled into the spaces between two adjacent cap layers126are not filled with the first oxide layer136. The first hard mask layer138has a number of protruding portions, and therefore the first hard mask layer138has a non-planar top surface. In order to reduce the height difference, the second oxide layer140is formed over the first hard mask layer138. As a result, the second oxide layer140has a substantially planar top surface.

The first oxide layer136and the first hard mask layer138are made of different materials. The first oxide layer136has a high etching selectivity with respect to the first hard mask layer138. In some embodiments, the first hard mask layer138is removed while the first oxide layer136is remaining due to the etching selectivity between them. In some embodiments, the first hard mask layer138is made of silicon nitride, silicon oxynitride, or another applicable material. In some embodiments, the first hard mask layer138is formed by a deposition process, such as CVD process, ALD process, another applicable process, or a combination thereof.

Afterwards, as shown inFIG.2K, a portion of the second oxide layer140is removed to expose the top surface of the first hard mask layer138, in accordance with some embodiments. In some embodiments, the portion of the second oxide layer140is removed by a planarizing process, such as a chemical mechanical polishing (CMP) process.

The second oxide layer140and the first oxide layer136are made of the same or different material. In some embodiments, the second oxide layer140is made of silicon oxide or another applicable material. In some embodiments, the second oxide layer140is formed by a deposition process, such as CVD process, ALD process, another applicable process, or a combination thereof.

Afterwards, as shown inFIG.2L, the remaining second oxide layer140is removed, and then the protruding portions of the first hard mask layer138are removed, in accordance with some embodiments. As a result, the first hard mask layer138has a planar top surface. In some embodiments, the remaining second oxide layer140is removed, and then the protruding portions of the first hard mask layer138are removed by a planarizing process, such a chemical mechanical polishing (CMP) process. The height of the dummy gate electrode layer148(formed later, inFIG.2Q) is determined by controlling the height of the remaining first hard mask layer138.

Afterwards, as shown inFIG.2M, a portion of the first hard mask layer138is removed to form a first trench141, in accordance with some embodiments. In addition, the first oxide layer136is exposed by the first trench141. Since the first oxide layer136has a high etching selectivity with respect to the first hard mask layer138, the first oxide layer136is not removed while the first hard mask layer138is removed. The first oxide layer136is used as an etching stop layer at the step ofFIG.2M.

The portion of the first hard mask layer138is removed by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

Afterwards, as shown inFIG.2N, the exposed first oxide layer136is removed to expose the cap layer126and the topmost second semiconductor layer108, in accordance with some embodiments. In some embodiments, the exposed first oxide layer136is removed by an etching process, such as a dry etching process or a wet etching process. Note that another portion of the first oxide layer136which is covered by the first hard mask layer138is not removed.

Afterwards, as shown inFIG.2O, a gate spacer layer142is formed in the first trench141, in accordance with some embodiments. The gate spacer layer142is conformally formed on the first hard mask layer138, in the first trench141, and on the cap layer126. However, the trench141is not completely filled with the gate spacer layer142.

In some embodiments, the gate spacer layer142is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof. In some embodiments, the gate spacer layer142is formed by a deposition process, such as CVD process, ALD process, another applicable process, or a combination thereof.

Afterwards, as shown inFIG.2P, a portion of the gate spacer layer142is removed to form a second trench143, and a portion of the topmost second semiconductor layer108is removed to form a recess145, in accordance with some embodiments. The portion of the gate spacer layer142and the portion of the topmost second semiconductor layer108are removed simultaneously. It should be noted that the top portion of the cladding layer118exposed by the second trench143and the portion of the topmost second semiconductor layer108are also removed simultaneously. More specifically, the horizontal portions of the gate spacer layer142are removed. The horizontal portions of the gate spacer layer142includes a first portion above the first hard mask layer138and a second portion at the bottom of the trench141. In some embodiments, the width of the second trench143is greater than the width of the first trench141since a portion of the gate spacer layer142is removed.

In some embodiments, the portion of the gate spacer layer142and the portion of the topmost second semiconductor layer108are removed by an etching process, such as dry etching process. In some embodiments, the dry etching process is performed by using a gas including fluorocarbon (CxHyFz) gas.

Afterwards, as shown inFIG.2Q, a dummy gate dielectric layer146is formed in the recess145, and a dummy gate electrode layer148is formed in the second trench143and on the dummy gate dielectric layer146, in accordance with some embodiments. In addition, the dummy gate electrode layer148is formed on the gate spacer layer142and the first hard mask layer138.

The top surface of the dummy gate dielectric layer146is lower than the top surface of the topmost second semiconductor108and the top surface of the first oxide layer136.

In some embodiments, the dummy gate dielectric layer146is made of silicon oxide. In some embodiments, an oxidation process is performed on the exposed second semiconductor layers108to form the dummy gate dielectric layer146. In some embodiments, the exposed second semiconductor layers108is exposed in an oxidation process (e.g., a dry oxidation process, or a wet oxidation process). In some embodiments, the exposed second semiconductor layers108is exposed in the wet process including water, hydrogen peroxide or ozone to perform the oxidation process.

In some embodiments, the dummy gate electrode layer148is made of polysilicon. In some embodiments, the dummy gate electrode layer148is formed by a deposition process, such as CVD process, ALD process, another applicable process, or a combination thereof.

Afterwards, as shown inFIG.2R, the top portion of the dummy gate electrode layer148is removed, in accordance with some embodiments. As a result, the top surface of the gate spacer layer142and the top surface of the first hard mask layer138are exposed. In some embodiments, the portion of the dummy gate electrode layer148is removed by a planarizing process, such as a chemical mechanical polishing (CMP) process.

Afterwards, as shown inFIG.2S, another portion of the dummy gate electrode layer148is removed to form an opening151, in accordance with some embodiments. In some embodiments, another portion of the dummy gate electrode layer148is removed by an etching process.

Afterwards, as shown inFIG.2T, a second hard mask layer152is formed in the opening151and over the first hard mask layer138, in accordance with some embodiments. Afterwards, the portion of the second hard mask layer152outside of the opening151is removed to expose the top surface of the first hard mask layer138.

It should be noted that the first hard mask layer138and the second hard mask layer152are made of different materials. The first hard mask layer138has a high etching selectivity with respect to the second hard mask layer152, and therefore the second hard mask layer152is removed but the first hard mask layer138is remaining. In some embodiments, the second hard mask layer152is made of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or another applicable material. In some embodiments, the second hard mask layer152is formed by a deposition process, such as CVD process, ALD process, another applicable process, or a combination thereof.

Afterwards, as shown inFIG.2U, the first hard mask layer138is removed, and then the first oxide layer136directly below the first hard mask layer138is removed, in accordance with some embodiments. As a result, the cap layer126not covered by the dummy gate electrode layer148is exposed. A dummy gate structure147is constructed by the dummy gate dielectric layer146and the dummy gate electrode layer148.

It should be noted that the second hard mask layer152and the first hard mask layer138are made of different materials, and the second hard mask layer152has a high etching selectivity with respect to the first hard mask layer138. Therefore, the first hard mask layer138is removed, but the second hard mask layer152is left.

In the compared embodiment, an compared dummy gate electrode layer is formed by forming a dummy gate electrode layer over the fin structure104-1,104-2, and then performing a patterning process by using the hard mask layer over the dummy gate electrode layer. Since the hard mask layer has a certain thickness, the aspect ratio (height/width) of the compared dummy gate electrode layer is sum of the height of the hard mask layer and the height of the compared dummy gate electrode layer with respect to the width of the dummy gate electrode layer. Therefore, the aspect ratio of the compared dummy gate electrode layer is too high to make the compared dummy gate electrode layer collapse. Therefore, the pitch or distance between two adjacent compared dummy gate electrode layers is difficult to reduce due to the collapse issue.

In order to prevent the dummy gate electrode layers148collapse, in this disclosure, the dummy gate electrode layer148is formed without using any photoresist layer over the dummy gate electrode layer148. In addition, the gate spacer layer142has already been formed before the dummy gate electrode layer148is formed. In contrast to compared embodiment, the aspect ratio (HT/WT) of the dummy gate electrode layer148of this disclosure is the sum HTof height of the second hard mask layer152and height of the dummy gate electrode layer148with respect to the sum WTof the width of the gate spacer layer142and the width of the dummy gate electrode layer148. Therefore, the aspect ratio (HT/WT) of the dummy gate electrode layer148is calculated by greater width and smaller height (than the compared dummy gate electrode layer), and the risk of dummy gate electrode layer148collapse is reduced. Furthermore, the pitch or distance between two adjacent dummy gate electrode layers148can be reduced to about 2 nm to about 10 nm.

Afterwards, as shown inFIG.2V, a portion of the first semiconductor layers106and a portion of the second semiconductor layers108are removed to form a source/drain (S/D) recess153, in accordance with some embodiments. The portion of the first semiconductor layers106and the portion of the second semiconductor layers108are removed by an etching process, such as a dry etching process or wet etching process. In addition, a top portion of the cap layer126is also removed by the etching process.

Next, as shown inFIG.2W, a portion of the first semiconductor layers106is removed to form a number of notches, and inner spacers156are formed in the notches, in accordance with some embodiments of the disclosure. More specifically, the portion of the first semiconductor layers106is exposed by the S/D recess153is removed to form the notches. In some embodiments, the portion of the first semiconductor layers106is exposed by the S/D recess153is removed by an etching process, such as a dry etching process or wet etching process. The inner spacers156can reduce the parasitic capacitance between the S/D structure158and the gate structure186(formed later).

The inner spacers156are directly below the gate spacer layer142. The inner sidewall of each of the inner spacers156is aligned with the inner sidewall of the gate spacer layer142. In addition, the outer sidewall of the dummy gate dielectric layer146is aligned with the inner sidewall of each of the inner spacers156.

Afterwards, the S/D structure158is formed in the S/D recess153. The S/D structure158may include silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAIP), indium phosphide (I P), or a combination thereof. The S/D structure158may dope with one or more dopants. In some embodiments, the S/D structure158is silicon (Si) doped with phosphorus (P), arsenic (As), antimony (Sb), or another applicable dopant. Alternatively, the S/D structure154is silicon germanium (SiGe) doped with boron (B) or another applicable dopant.

In some embodiments, the S/D structure158is formed by an epitaxy or epitaxial (epi) process. The epi process may include a selective epitaxial growth (SEG) process, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epi processes.

In some embodiments, when an N-type FET (NFET) device is desired, the S/D structure158includes an epitaxially growing silicon (epi Si). Alternatively, when a P-type FET (PFET) device is desired, the S/D structure158includes an epitaxially growing silicon germanium (SiGe).

Note that the topmost second semiconductor layer108has a U-shaped structure with a first portion directly below the gate spacer layer142and a second portion directly below the dummy gate electrode layer148. The height of the first portion is greater than the height of the second portion. The top surface of the first portion is higher than the top surface of the second portion of the topmost second semiconductor layer108. The bottommost second semiconductor layer108has a rectangular structure, rather than U-shaped structure.

FIGS.3A-3Ishow cross-sectional representations of various stages of forming the semiconductor device structure100aalong line X-X′ shown inFIG.2W, in accordance with some embodiments of the disclosure.

As shown inFIG.3A, the dummy gate dielectric layer146is formed over the topmost second semiconductor layer108, and a top oxide layer150is formed over the cladding layer118. Since the top portion of the cladding layer118is also oxidized by the oxidation process and the cladding layer118is made of silicon germanium (SiGe), the top oxide layer150is made of silicon germanium oxide (SiGeOx). The top oxide layer150is in direct contact with the liner layer120. The top surface of the dummy gate dielectric layer146is substantially level with the top surface of the top oxide layer15. Furthermore, the top surface of the top oxide layer150is lower than the top surface of the liner layer120and the top surface of the filling layer122. The interface between the dummy gate dielectric layer146and the top oxide layer150is aligned with the outer sidewall of the cladding layer118.

Note that since the top portion of the topmost second semiconductor layer108is oxidized by the oxidation process, the thickness of the topmost second semiconductor layer108is reduced. The topmost second semiconductor layer108has a first height H1along the vertical direction, and the bottommost second semiconductor layer108has a second height H2along the vertical direction. The second height H2is greater than the first height H1. In some embodiments, the first height H1is in a range from about 2 nm to about 9 nm. In some embodiments, the second height H2is in a range from about 5 nm to about 10 nm.

The dummy gate electrode layer148is formed over the dummy gate dielectric layer146and top oxide layer150, and the second hard mask layer152is formed over the dummy gate electrode layer148. Furthermore, the dummy gate electrode layer148is formed over the cap layer126.

Next, as shown inFIG.3B, the second hard mask layer152is removed, and then the dummy gate electrode layer148is removed to from a third trench165, in accordance with some embodiments of the disclosure. As a result, the cap layer126is exposed, and the top surface of the dummy gate dielectric layer146and the top surface of the top oxide layer150are exposed. In addition, a portion of the sidewall of the liner layer120is exposed.

Next, as shown inFIG.3C, a portion of the cap layer126is removed, in accordance with some embodiments of the disclosure. More specifically, the cap layer126has four portions and one portion of the cap layer126is removed by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

Next, as shown inFIG.3D, the dummy gate dielectric layer146and the top oxide layer150are removed to expose the topmost second semiconductor layer108and the top surface of the cladding layer118, in accordance with some embodiments of the disclosure. The dummy gate dielectric layer146and the top oxide layer150are removed by an etching process, such as a dry etching process or wet etching process.

Next, as shown inFIG.3E, the first semiconductor layers106and the cladding layer118are removed to expose a number of gaps167, in accordance with some embodiments of the disclosure. The gaps167are between two adjacent second semiconductor layers108. The suspending second semiconductor layers108are used as the channel region of the semiconductor layer structure100a.

Next, as shown inFIG.3F, a gate structure186is formed in the third trench165and the gaps167, in accordance with some embodiments of the disclosure. As a result, the number of nanostructures (e.g. the second semiconductor layers108) are surrounded by the gate structure186. The portion of the second semiconductor layers108covered by the gate structure186can be referred to as a channel region.

The gate structure186includes a gate dielectric layer182and a gate electrode layer184. The gate dielectric layer182is conformally formed along the main surfaces of the second semiconductor layers108to surround the second semiconductor layers108. The inner spacers156are between the gate structure186and the S/D structures158.

In some embodiments, the gate dielectric layer182includes a high-k dielectric layer. In some embodiments, the high-k gate dielectric layer is made of one or more layers of a dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HMO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, another suitable high-k dielectric material, or a combination thereof. In some embodiments, the high-k gate dielectric layer is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof.

In some embodiments, the gate electrode layer184includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof.

In addition, the gate electrode layer184includes one or more layers of n-work function layer or p-work function layer. In some embodiments, the n-work function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or a combination thereof. In some embodiments, the p-work function layer includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), molybdenum nitride, tungsten nitride (WN), ruthenium (Ru) or a combination thereof. In some embodiments, the gate electrode layer184is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof.

Next, as shown inFIG.3G, a portion of the gate electrode layer184is removed to expose the top surface of the cap layer126, in accordance with some embodiments of the disclosure. In some embodiments, the portion of the gate electrode layer184is removed by a planarizing process and an etching process. In some embodiments, the planarizing process is a chemical mechanical polishing (CMP) process. The etching process may be a dry etching process or a wet etching process.

Next, as shown inFIG.3H, a dielectric layer188is formed over the cap layer126and the gate structure186, in accordance with some embodiments of the disclosure. In some embodiments, the dielectric layer188includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, or a suitable dielectric material. The dielectric layer188may be deposited using CVD, ALD, PEALD, or a suitable method. After the deposition of the dielectric layer188, a chemical mechanical polishing (CMP) may be performed to remove excess dielectric layer188.

Afterwards, the dielectric layer188is patterned to form an opening189. The dielectric layer188is patterned by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

Next, as shown inFIG.3I, a gate contact structure190is formed in the opening189, in accordance with some embodiments of the disclosure. The gate contact structure190is electrically connected to the gate electrode layer184of the gate structure186.

In some embodiments, the gate contact structure190is made of aluminum (Al), copper (Cu), ruthenium (Ru), nickel (Ni), molybdenum (Mo), or tungsten (W). In some embodiments, the gate contact structure190is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or a combination thereof.

FIG.4illustrates a perspective view of the semiconductor structure100a, in accordance with some embodiments.FIG.3Ishows a cross-sectional representation of the semiconductor device structure100aalong line BB′ shown inFIG.4, in accordance with some embodiments of the disclosure.

As shown inFIG.4, the nanostructures (the second semiconductor layers108) are surrounded by the first gate structure186a. The first gate structure186aextends across two adjacent staked nanostructures. Therefore, the dielectric feature143including the liner layer120and the filling layer122is covered by the first gate structure186a. The second gate structure186bis adjacent to the first gate structure186a. The second gate structure186bincludes a second gate dielectric layer182band the second gate electrode layer184b. The second gate structure186bis isolated from the first gate structure186aby cap layer126. In other words, the top surface of the cap layer126is higher than the top surface of the first gate structure186aand the top surface of the second gate structure186b.

The topmost nanostructures (e.g. the second semiconductor layer108) surrounded by the first gate structure186ahas a U-shaped structure, and the topmost nanostructures (e.g. the second semiconductor layer108) surrounded by the second gate structure186balso has a U-shaped structure. The bottommost second semiconductor layer108(or called nanostructures) surrounded by the first gate structure186ahas a rectangular structure with the second height H2. The topmost second semiconductor layer108includes a first portion directly below the gate spacer layer142and a second portion directly below the first gate structure186a. Since the first portion of the topmost second semiconductor layer108is covered by the gate spacer layer142, the first portion of the topmost second semiconductor layer108is not removed by the etching process inFIG.2P. Therefore, the first portion of the topmost second semiconductor layer108has a third height H3, and the second portion has the first height H1(shown inFIG.3AandFIG.4). The third height H3is greater than the first height H1. The second height H2is greater than the first height H1. In some embodiments, the second height H2is substantially equal to the third height H3.

Furthermore, the inner spacer156is directly below the first portion of the topmost second semiconductor layer108. The bottommost second semiconductor layer108has a rectangular structure.

As shown inFIG.4, the topmost surface of the first gate dielectric layer182ais lower than the topmost surface of the nanostructure (e.g. the second semiconductor layer108). In addition, the top surface of the S/D structure158is lower than the top surface of the topmost second semiconductor layer108. The isolation structure116has a width along a horizontal direction which is greater than the width of the dielectric feature134including the liner layer120and filling layer122.

FIG.5illustrates a perspective view of the semiconductor structure100a, in accordance with some embodiments.

An S/D contact structure194is formed through the ILD layer162, the CESL160and the S/D structure158, and the S/D contact structure194is embedded in the S/D structure158. The S/D contact structure194is electrically connected to the S/D structure158. The topmost nanostructure (e.g. the second semiconductor layer108) has the U-shaped structure and has two protruding sidewall portions and a recessed middle portion. The gate dielectric layer182is formed in the recessed middle portion, and therefore the topmost surface of the gate dielectric layer182is lower than the top surface of the protruding portions of the topmost nanostructure. The topmost surface of the gate dielectric layer182is lower than the bottommost surface of the first gate spacer layer142. In addition, the inner spacer156is directly below the protruding sidewall portions of the topmost nanostructure (e.g. the second semiconductor layer108).

FIG.6illustrates a perspective view of a semiconductor structure100b, in accordance with some embodiments. The semiconductor structure100bofFIG.6is similar to, or the same as, the semiconductor structure100aofFIG.5, the difference between theFIG.6andFIG.5is the position of the S/D structure158.

As shown inFIG.6, the bottom surface of the S/D structure158is higher than the top surface of the isolation structure116. The bottom surface of the S/D structure158is substantially leveled with the bottom surface of the inner spacer156. The top surface of the S/D structure158is higher than the topmost nanostructure (e.g. the second semiconductor layer108). In addition, the top surface of the S/D structure158is higher than the bottom surface of the gate spacer layer142.

FIG.7is an enlarged view of region A ofFIG.6, in accordance with some embodiments. The topmost nanostructure (e.g. the second semiconductor layer108) has a U-shaped structure with the first portion and the second portion. The first portion is directly below the gate spacer layer142and has the third height H3along the vertical direction. The second portion is directly below the gate structure186and has the first height H1. The third height H3is greater than the first height H1. In addition, the topmost gate dielectric layer182is lower than the topmost surface of the topmost nanostructure (e.g. the second semiconductor layer108).

It should be noted that since the dummy gate structure147formation sequence is changed, the dummy gate electrode layer148is formed after the gate spacer layer142is formed. The dummy gate electrode layer148is formed without using additional photoresist layer, and it is formed on the gate spacer layer142. Therefore, the aspect ratio of the dummy gate structure147is reduced, and the risk of dummy gate structure147collapse is reduced. The pitch or distance between two adjacent dummy gate structures147can be reduced to about 2 nm to about 10 nm.

Embodiments for forming a semiconductor device structure and method for formation the same are provided. A fin structure is formed over a substrate, and the fin structure includes a number of first semiconductor layers and a number of second semiconductor layers stacked in the vertical direction. The first hard mask layer is formed over the fin structure and patterned to form a trench. A dummy gate electrode layer is formed in the trench to finish the dummy gate structure loop (or called as a poly loop). Since the dummy gate electrode layer is formed after the gate spacer layer is formed, the aspect ratio is reduced by changing the process sequence. Therefore, the risk of dummy gate electrode layer collapse is reduced, and the yield of semiconductor device structure is improved.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first fin structure formed over a substrate, and the first fin structure includes a plurality of first nanostructures stacked in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion directly below the gate spacer layer and a second portion directly below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first fin structure formed over a substrate, and the first fin structure includes a plurality of first nanostructures stacked in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures, and the first gate structure includes a first gate dielectric layer and a first gate electrode. The semiconductor device structure includes a first S/D structure formed adjacent to the first gate structure, and a topmost surface of the first gate dielectric layer is lower than a topmost surface of the first nanostructures.

In some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate, and the first fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction, and the second fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked in a vertical direction. The method includes forming a hard mask layer over the first fin structure and the second fin structure, and patterning the hard mask layer to form a trench. The method includes forming a gate spacer layer in the trench, and forming a dummy gate electrode layer in the trench and on the gate spacer layer. The method also includes removing the hard mask layer, and removing a portion of the first fin structure and a portion of the second fin structure to form a first S/D recess and a second S/D recess. The method includes forming a first source/drain (S/D) structure in the first S/D recess and a second S/D structure in the second S/D recess.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.