Patent ID: 12211582

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is now made toFIG.1which shows a schematic diagram of an in-memory computation circuit10. The circuit10utilizes a memory array12formed by a plurality of memory cells14arranged in a matrix format having m columns and n rows. Each memory cell14is programmed to store data gmnrelating to the computational weights for an in-memory compute operation.

Each memory cell14includes a word line WL and a bit line BL. The memory cells14in a common row of the matrix are connected to each other through a common word line WL<n>. The memory cells14in a common column of the matrix are connected to each other through a common bit line BL<m>.

The word lines WL<1>, . . . , WL<n> are driven by a word line driver circuit18which generates word line signals16in response to a received address signal (Address). The word line driver circuit18decodes the Address and applies the pulse of the word line signal16to one word line WL at a time (illustrated here, as an example, as being applied to word line WL<1>). The pulse width of each word line signal16is fixed and defined by an on time TON.

It is important to note here that the activation of one word line WL at a time performs a single multiply and accumulate (MAC) operation. In order to perform matrix-vector multiplication (MVM), where k MAC operations are implemented (k being less than or equal to n), a sequence of k word line WL activations are required. Consequently, k word line WL on time (Ton) cycles are necessary for the performance of one full MVM operation.

Biasing circuitry20applies a bias (time, voltage and/or current) to each of the bit lines BL in response to feature (or coefficient) data x input to the in-memory computation circuit10. This feature data may, for example, comprise a plurality of multi-bit digital signals x1, . . . , xmthat are processed by the biasing circuits201, . . . ,20mto generate the bias applied to the corresponding word lines WL<1>, . . . , WL<n>. The analog signal ymat a column output on a given bit line BL<m> (i.e., the bit line charge) is then dependent on a product between the bias applied to the bit line and the transconductance gmn(which corresponds to the programmed resistivity) of the memory cell14mnselected by the word line WL to which the word line signal16is applied. In other words, the memory cell14contributes a bit line current for the analog signal ymthat is proportional to xm×gmin. So, in the example shown inFIG.1where the word line signal16is applied to word line WL<1>, the analog signal y1charge on bit line BL<1> is proportional to x1×g11, the analog signal y2charge on bit line BL<2> is proportional to x2×g21, and the analog signal ymcharge on bit line BL<m> is proportional to xm×gm1.

A combining circuit22combines, for example through an integration operation, the analog signal y1, . . . , ymcharges to generate a corresponding decision znresult for the MAC decision operation, where zn=g1n×x1+g2n×x2+ . . . +gmn×xm. Further processing of the decision znresult may, for example, be made by converting the analog decision signal znto a digital value using an analog-to-digital converter (ADC) which is then processed in a digital signal processing (DSP) circuit.

In a preferred embodiment, each memory cell14is a phase change memory (PCM) cell comprising a select circuit (MOSFET transistor, BJT transistor, diode device, etc.)14toperating as a switching element and a variable resistive element14rproviding the transconductance gmn.

In case of a MOSFET transistor for the select circuit14t(as shown inFIG.1), the control node (gate) of the MOSFET transistor is connected to the word line WL. The source-drain path of the MOSFET transistor is connected in series with the variable resistive element14rbetween the bit line BL and a reference node (for example, a source line or ground). More specifically, a drain of the MOSFET transistor is connected to a first terminal of the variable resistive element14r, the source of the MOSFET transistor is connected to the reference node, and the second terminal of the variable resistive element14ris connected to the bit line BL.

In case of a BJT transistor for the select circuit14t, the control node (base) of the BJT transistor is connected to the word line WL. The conduction path of the BJT transistor is connected in series with the variable resistive element14rbetween the bit line BL and a reference node (for example, ground). More specifically, the emitter of the BJT transistor is connected to a first terminal of the variable resistive element14r, the collector of the BJT transistor is connected to the reference node (for example, ground), and the second terminal of the variable resistive element14ris connected to the bit line BL. In this case the WL driver has the opposite polarity respect to the MOS select transistor case.

In case of a diode device for the select circuit14t, the control node of the select device14tis connected to the word line WL. The diode path of the select circuit14tis connected in series with the variable resistive element14rbetween the bit line BL and the word line. More specifically, one terminal of the diode device is connected to a first terminal of the variable resistive element14r, the other is connected to the word line, and the second terminal of the variable resistive element14ris connected to the bit line BL.

As is well known to those skilled in the art, a PCM-type memory cell14is configured to store data using phase change materials (such as chalcogenide) that are capable of stably transitioning between amorphous and crystalline phases according to an amount of heat transferred thereto. The amorphous and crystalline phases exhibit two or more distinct resistances (corresponding to the variable resistive element14r), in other words two or more distinct transconductances, which are used to distinguish two or more distinct logic states programmable into the memory cell. The amorphous phase exhibits a relatively higher resistance (i.e., a lower transconductance) and thus the current sunk from the bit line BL by the memory cell programmed in this state when selected by assertion of the word line signal at the gate of the select circuit14tis relatively smaller. Conversely, the crystalline phase exhibits a relatively lower resistance (i.e., a higher transconductance) and thus the current sunk from the bit line BL by the memory cell programmed in this state when selected by assertion of the word line signal at the gate of the select circuit14tis relatively larger.

In an embodiment for a specific, but non-limiting, example for two distinct logic states: the amorphous phase may represent programming of the memory cell to logic “0” (or reset state) for the associated coefficient weight and the crystalline phase may represent programming of the memory cell to logic “1” (or set state) for the associated coefficient weight. In an embodiment for a three or more distinct logic states: varying degrees of the amorphous phase (with different resistances) plus the crystalline phase may be used to represent programming of the memory cell into three or more corresponding levels.

It will be understood that other memory cell types could instead be used for the array12. For example, magnetoresistive random access memory (MRAM) cells or resistive random access memory (RRAM) cells could be used. The memory cell may alternatively comprise a static random access memory (SRAM) cell.

Reference is now made toFIG.2Awhich shows an embodiment for the biasing circuits201, . . . ,20m. A metal oxide semiconductor field effect transistor (MOSFET) device30has its source-drain path coupled, preferably connected, in series with the bit line BL<m>. More specifically, the source terminal of the transistor30is connected to the bit line and the drain terminal that outputs the analog signal ymand is connected at a column output to the combining circuit22. A differential amplifier circuit32has an inverting input terminal coupled, preferably directly connected, to the source terminal of transistor30. An output of the amplifier circuit32is coupled, preferably directly connected, to the gate terminal of the transistor30. The non-inverting input terminal of the amplifier32receives a voltage vmgenerated by a digital-to-analog converter (DAC) from a conversion of the feature (or coefficient) data xm. The negative feedback with the transistor30and amplifier32forces the drain voltage (i.e., the bit line BL<m> voltage) to equal the voltage vmcorresponding to the feature (or coefficient) data xm. The bit line current for the analog signal ymis accordingly dependent on the product of bias voltage vmand the transconductance gmn(programmed resistivity) of the selected memory cell14mn.

Those skilled in the art will understand that memory cells based on devices like phase change memory cells do not act as ideal resistances. The actual value of transconductance depends on the bit line BL voltage VBL, and thus the transconductance gmnis a function of voltage VBL. This relationship is referred to as a “non-linearity effect.” For this reason, the circuit ofFIG.2Ais not fully suitable for use in an in-memory computing application. The reason for this is that input is directly coupled to the bit line BL voltage, and thus the readout current would equal gmn(vm)·vm. Circuits to both keep the bit line voltage constant and to perform the multiplication necessary for in-memory computing are needed. The problem is solved with the circuits shown inFIGS.2B,2C and2D. In this context, the biasing circuit ofFIG.2Bprovides an approximate solution, and the biasing circuits ofFIGS.2C and2Dprovide more accurate solutions. The circuits ofFIGS.2C and2Dsupport reading of the memory cells at a fixed reference voltage level Vref, and this obviates concerns with the non-linearity effect.

FIG.2Bshows an alternative embodiment for the biasing circuits201, . . . ,20m. A MOSFET device40has its source-drain path coupled, preferably connected, in series with the bit line BL<m>. More specifically, the source terminal of the transistor40is connected to the bit line and the drain terminal is connected to an intermediate node42. The gate terminal of the transistor40is biased by a reference voltage Vref (generated, for example, using a band gap or voltage regulator circuit). Transistor40functions as a voltage regulator to bias the bit line BL<m> with a voltage that is a function of on the reference voltage Vref and a term that is dependent on the bit line bias current (which can be made negligible with proper sizing of transistor40in a manner understood by those skilled in the art). A further MOSFET device44has its source-drain path coupled, preferably connected, in series with the transistor40. More specifically, the source terminal of the transistor44is connected to the intermediate node42and the drain terminal that outputs the analog signal ymand is connected at a column output to the combining circuit22. Transistor44functions as a switching element. A comparator circuit46has an inverting input terminal coupled, preferably directly connected, to receive a ramp signal Vramp. An output of the comparator circuit46is coupled, preferably directly connected, to the gate terminal of the transistor44to control the switching function. The non-inverting input terminal of the comparator46receives a voltage vmgenerated by a digital-to-analog converter (DAC) from a conversion of the feature (or coefficient) data xm. The comparator46functions to compare the voltage vmto the ramp signal Vramp. When the voltage vmis less than the voltage of the ramp signal Vramp, the output of comparator46causes transistor44to turn on and the bit line biasing current is applied to the selected memory cell14mn. When the voltage of the ramp signal Vramp exceeds the voltage vm, comparator46turns off transistor44. The duration of time for bit line current flow for the analog signal ymis accordingly dependent on the bias voltage vmwhile the BL current is proportional to the transconductance gmn(programmed resistivity) of the selected memory cell14mn. The analog signal ymis accordingly dependent on the product of bias voltage vmand the transconductance gmn(programmed resistivity) of the selected memory cell14mn. It will be noted here that the analog signal ymis a charge.

FIG.2Cshows a further embodiment for the biasing circuits201, . . . ,20m. A metal oxide semiconductor field effect transistor (MOSFET) device50has its source-drain path coupled, preferably connected, in series with the bit line BL<m>. More specifically, the source terminal of the transistor50is connected to the bit line and the drain terminal is connected to intermediate node52. A differential amplifier circuit54has an inverting input terminal coupled, preferably directly connected, to the source terminal of transistor50. An output of the amplifier circuit54is coupled, preferably directly connected, to the gate terminal of the transistor50. The non-inverting input terminal of the amplifier54receives a reference voltage Vref (generated, for example, using a voltage regulator circuit). The negative feedback with the transistor50and amplifier54provides a voltage regulator circuit function that forces the drain voltage (i.e., the bit line BL<m> voltage) to equal the reference voltage Vref. In other words, a fixed reference voltage level is applied to the bit line. A further MOSFET device56has its source-drain path coupled, preferably connected, in series with the transistor50. More specifically, the source terminal of the transistor56is connected to the intermediate node52and the drain terminal that outputs the analog signal ymand is connected at a column output to the combining circuit22. Transistor56functions as a switching element. A comparator circuit58has an inverting input terminal coupled, preferably directly connected, to receive a ramp signal Vramp. An output of the comparator circuit58is coupled, preferably directly connected, to the gate terminal of the transistor56to control the switching function. The non-inverting input terminal of the comparator58receives a voltage vmgenerated by a digital-to-analog converter (DAC) from a conversion of the feature (or coefficient) data xm. The comparator58functions to compare the voltage vmto the ramp signal Vramp. When the voltage vmis less than the voltage of the ramp signal Vramp, the output of comparator58causes transistor56to turn on and connect the bit line current from the selected memory cell14mnto the combining circuit22. When the voltage of the ramp signal Vramp exceeds the voltage vm, comparator58turns off transistor56. The duration of time for bit line current flow for the analog signal ymis accordingly dependent on the bias voltage vmwhile the BL charge is proportional to the transconductance gmn(programmed resistivity) of the selected memory cell14mn. The analog signal ymis accordingly dependent on the product of bias voltage vmand the transconductance gmn(programmed resistivity) of the selected memory cell14mn. It will be noted here that the analog signal ymis a charge.

FIG.2Dshows a further embodiment for the biasing circuits201, . . . ,20m. A metal oxide semiconductor field effect transistor (MOSFET) device60has its source-drain path coupled, preferably connected, in series with the bit line BL<m>. More specifically, the source terminal of the transistor60is connected to the bit line and the drain terminal is connected to intermediate node62. A further MOSFET device64has its source-drain path coupled, preferably connected, in series with the transistor60. More specifically, the source terminal of the transistor64is connected to the intermediate node62and the drain terminal is connected to intermediate node66. Transistor64functions as a switching element. A comparator circuit68has an inverting input terminal that receives a ramp signal Vramp. An output of the comparator circuit68is coupled, preferably directly connected, to the gate terminal of the transistor64to control the switching function. The non-inverting input terminal of the comparator68receives a voltage vmgenerated by a digital-to-analog converter (DAC) from a conversion of the feature (or coefficient) data xm. A MOSFET device70has its source-drain path coupled, preferably connected, in series with the transistor64. More specifically, the drain terminal of the transistor70is connected to the intermediate node66and the source terminal is connected to a positive supply node. A MOSFET device72is connected to transistor60to form a current mirror circuit. The source terminal of transistor72is coupled to receive a reference voltage Vref. The gate and drain terminals of transistor72are coupled, preferably directly connected, together at intermediate node74and further coupled, preferably directly connected, to the gate terminal of transistor60. A MOSFET device76has its source-drain path coupled, preferably connected, in series with the transistor72. More specifically, the drain terminal of the transistor76is connected to the intermediate node74and the source terminal is connected to intermediate node78. Transistor76functions as a switching element. The gate terminal of transistor76is coupled to the output of comparator64which controls its switching function. A MOSFET device80is connected to transistor70to form a current mirror circuit. The source terminal of transistor80is coupled, preferably directly connected, to the positive supply node and a drain terminal is coupled, preferably directly connected, to intermediate node78. The gate and drain terminals of transistor70are coupled, preferably directly connected, together at intermediate node66and further coupled, preferably directly connected, to the gate terminal of transistor80. This current mirror circuit further includes MOSFET device82whose gate terminal is coupled, preferably directly connected, to the gate terminals of transistors70and80, whose source terminal is coupled, preferably directly connected, to the positive supply node and whose drain terminal outputs the analog signal ymand is connected at a column output to the combining circuit22.

This circuit configuration with the two current mirrors provides a voltage feedback that functions to force the gate-to-source voltages of transistors60and72to be equal. Thus, with the reference voltage Vref applied to the source of transistor72, that reference voltage Vref will also be applied to the bit line BL<m>. In other words, a fixed reference voltage level is applied to the bit line. In an embodiment, the current mirroring ratio between transistors70and80may, for example, be on the order of 10:1 in order to reduce current and limit total current consumption. A similar current mirroring ratio may be used between transistors70and82.

The comparator68functions to compare the voltage vmto the ramp signal Vramp. When the voltage vmis less than the voltage of the ramp signal Vramp, the output of comparator68causes transistors64and76to turn on and activate the current mirror circuits. The bit line current from the selected memory cell14mnis mirrored through transistor82to the combining circuit22. When the voltage of the ramp signal Vramp exceeds the voltage vm, comparator68turns off transistors64and76. The duration of time for bit line current for the analog signal ymis accordingly dependent on the bias voltage vmwhile the BL current is proportional to the transconductance gmn(programmed resistivity) of the selected memory cell14mn. The analog signal ymis accordingly dependent on the product of bias voltage vmand the transconductance gmn(programmed resistivity) of the selected memory cell14mn. It will be noted here that the analog signal ymis a charge.

The reference voltage Vref applied to the source terminal of transistor72may be generated using a voltage regulator circuit. For example, a low-drop out (LDO) type voltage regulator92formed by an amplifier94and MOSFET device96, where the MOSFET device is coupled in series with transistor72and gate driven by the output of the amplifier. Feedback from the source of transistor72(drain of transistor96) is provided to the non-inverting input of the amplifier, and the inverting input receives the reference voltage Vref which may be generated using a band-gap circuit. The voltage at the source of transistor72(drain of transistor96) is regulated to equal the reference voltage Vref. The LDO type regulator92may be used as well for generating the reference voltage Vref for the circuit ofFIG.2B. It will also be understood that the LDO type regulator may be shared in parallel by multiple ones of the circuits20m.

Reference is now made toFIG.3Awhich shows an embodiment for a ramp generator circuit100used to generate the ramp signal Vramp used in the biasing circuit20mshown inFIGS.2B,2C and2D. The voltage for the ramp signal Vramp is generated across a capacitor102in response to a ramp current Tramp output by a current mirror circuit formed by MOSFET devices104and106. The source terminals of transistors104and106are coupled, preferably directly connected, to the positive supply node. The drain terminal of transistor106is coupled, preferably directly connected, to a first terminal of the capacitor102. A second terminal of the capacitor102is coupled, preferably directly connected, to ground. The drain terminal of transistor104is coupled, preferably directly connected, to the gate terminals of transistors104and108and also to intermediate node108. A MOSFET device110has its source-drain path coupled, preferably directly connected, between intermediate node108and a reference bit line BL<ref>. A reference memory cell14refis coupled, preferably directly connected, to the reference bit line BL<ref> and programmed with a reference transconductance gref. The reference memory cell14refis selected by a word line signal concurrently with the word line actuation in the memory array. In a preferred implementation, the reference bit line BL<ref> with reference memory cell14refis part of the memory array12. It will also be noted that plural reference memory cells14refmay be coupled to the reference bit line BL<ref>.

A differential amplifier circuit112has an inverting input terminal coupled, preferably directly connected, to the source terminal of transistor110. An output of the amplifier circuit112is coupled, preferably directly connected, to the gate terminal of the transistor110. The non-inverting input terminal of the amplifier112receives a reference voltage Vref. The negative feedback with the transistor110and amplifier112forces the drain voltage (i.e., the bit line BL<ref> voltage) to equal the reference voltage Vref. Note here that this is analogous to circuits ofFIGS.2C and2Dfor the bit line BL<m>. The bit line current flow from the reference memory cell14refis mirrored by the current mirror circuit (transistors104and106) to generate a current Iramp to charge the capacitor102and produce the ramp signal Vramp. A MOSFET device114connected in parallel with the capacitor102is selectively activated by reset signal (Reset) to discharge the capacitor102at the start of each cycle of the ramp signal Vramp. The advantage provided by use of the bit line current from the reference memory cell14refis that the generation of the ramp signal Vramp will match any drift experienced with respect to the memory cells14mnof the memory12.

Reference is now made toFIG.3Bwhich shows an embodiment for a ramp generator circuit100used to generate the ramp signal Vramp used in the biasing circuit20mshown inFIGS.2B,2C and2D. The voltage for the ramp signal Vramp is generated by an integrator circuit120across an integration capacitor102in response to a ramp current Tramp output by a current mirror circuit formed by MOSFET devices104and106. The integrator circuit120includes a differential amplifier122having an inverting input terminal configured to receive a ramp reference voltage Vref,ramp. The integration capacitor102is coupled, preferably directly connected, in feedback between the output terminal of the amplifier122and the non-inverting input terminal. A MOSFET device114connected in parallel with the capacitor102is selectively activated by reset signal (Reset) to discharge the capacitor102at the start of each cycle of the ramp signal Vramp. The source terminals of transistors104and106for the current mirror circuit are coupled, preferably directly connected, to the positive supply node. The drain terminal of transistor106is coupled, preferably directly connected, to the non-inverting input terminal and the first terminal of the capacitor102. The drain terminal of transistor104is coupled, preferably directly connected, to the gate terminals of transistors104and108and also to intermediate node108. A MOSFET device110has its source-drain path coupled, preferably directly connected, between intermediate node108and a reference bit line BL<ref>. A reference memory cell14refis coupled, preferably directly connected, to the reference bit line BL<ref> and programmed with a reference transconductance gref. The reference memory cell14refis selected by a word line signal concurrently with the word line actuation in the memory array. In a preferred implementation, the reference bit line BL<ref> with reference memory cell14refis part of the memory array12. It will also be noted that plural reference memory cells14refmay be coupled to the reference bit line BL<ref>.

A differential amplifier circuit112has an inverting input terminal coupled, preferably directly connected, to the source terminal of transistor110. An output of the amplifier circuit112is coupled, preferably directly connected, to the gate terminal of the transistor110. The non-inverting input terminal of the amplifier112receives a reference voltage Vref. The negative feedback with the transistor110and amplifier112forces the drain voltage (i.e., the bit line BL<ref voltage) to equal the reference voltage Vref. Note here that this is analogous to circuits ofFIGS.2C and2Dfor the bit line BL<m>. The bit line current from the reference memory cell14refis mirrored by the current mirror circuit (transistors104and106) to generate a current Iramp that is integrated by the integration circuit120across the capacitor102to produce the ramp signal Vramp. The advantage provided by use of the bit line current from the reference memory cell14refis that the generation of the ramp signal Vramp will match any drift experienced with respect to the memory cells14mnof the memory12.

Reference is now made toFIGS.4A-1and4A-2which each show an embodiment for the combining circuit22. The analog signal ym(ymAB, ymAC, ymAD) is dependent on the bit line current from the memory cell14mnat the column output which is mirrored by a current mirror circuit22m(22mAB,22mAC,22mAD) and sourced as current iBLm(iBLmAB, iBLmAC, iBLmAD) to charge an output capacitor Cout across which is generated an output voltage for the decision znresult of the MAC decision operation. It is the sum of the currents iBL1, . . . , iBLm(iBL1AB, . . . , iBLmAD) generated by the current mirror circuits221, . . . ,22m(221AB, . . . ,22mAD) that is integrated on the output capacitor Cout. A switch circuit, formed for example by a MOSFET device, is controlled the reset signal (Reset) to discharge the output capacitor Cout at the beginning of each MAC decision operation.

It is important to again note here that the activation of one word line WL at a time performs a single multiply and accumulate (MAC) operation. Each MAC operation needed for the in-memory computation, for examine in connection with performing matrix-vector multiplication (MVM), requires a different word line selection.

The MAC operation performed may be mathematically described as follows:

VO⁢U⁢T,n=∑i=1mQOUT,iCO⁢U⁢T=IBL,i⁢TON,iCOUT=∑i=1mgi,n(V⁢r⁢ef,t)⁢VrefCO⁢U⁢T⁢vi⁢CR⁢A⁢M⁢PIR⁢A⁢M⁢P=∑i=1mgi,n(V⁢r⁢ef,t)⁢VrefCO⁢U⁢T⁢vi⁢CR⁢A⁢M⁢Pgref(V⁢r⁢e⁢f,t)⁢V⁢r⁢e⁢f=CR⁢A⁢M⁢PCO⁢U⁢T⁢∑i=1mgi,n(V⁢r⁢ef,t)⁢vigref(V⁢r⁢e⁢f,t)

Where: VOUT,n, i.e., zn, is the output voltage across the output capacitor Cout in response to the bit line currents from the memory cell transconductances g1nto gmn, QOUT,iis the corresponding charge contribution of BL<i>, where i=1, . . . , m, COUT is the capacitance of the output capacitor Cout, iBL,iis the mirrored bit line current from the memory cell14in, TON,iis the duration of time for bit line BL<i> current flow for the analog signal yi, gi,nis the transconductance of the memory cell14i,ncorresponding to its programmed weight, Vref is the reference voltage, viis the input voltage corresponding to the feature (or coefficient) data xi, CRAMP is the capacitance of the ramp generator circuit capacitor102, grefis the transconductance of the reference memory cell14ref.

The foregoing mathematical representation is applicable to the use of the circuits shown inFIGS.2B,2C and2Dalong with either of the circuits shown inFIGS.4A-1,4A-2,4B-1and4B-2.

The use of the reference memory cell14refin connection with the generation of the ramp signal further supports removal of the weight time (drift) dependence. It is known in the art that the conductance of the memory cells14tends to decrease due to amorphization and relaxation of the crystal lattice for the phase change material. In particular, this conductance drift can be modeled and shaped by empirical law:

G⁡(t)=G0(tt0)-α

Where: t is time, t0is an arbitrary time instant, α is the drift coefficient, and G0is the conductance at time t0.

Considering the contribution of a single bit line BL current only, then the output voltage is given by:

VO⁢U⁢T,m=(CR⁢A⁢M⁢PCO⁢U⁢T⁢gmn(t)gr⁢e⁢f(t))⁢vm=(CR⁢A⁢M⁢PCOUT⁢gmn(tt0)-αmngref(tt0)-αref)⁢vm=(CR⁢A⁢M⁢PCO⁢U⁢T⁢gm⁢ngr⁢e⁢f⁢(tt0)-(αm⁢n-αr⁢e⁢f))⁢vm

Considering now the whole MAC operation, where all BL currents are summed and integrated on the COUT capacitance:

VO⁢U⁢T,m=∑i=1m(CR⁢A⁢M⁢PCO⁢U⁢T⁢gi,n(t)gref(t))⁢vi=∑i=1m(CR⁢A⁢M⁢PCO⁢U⁢T⁢gi,n(tt0)-αi,ngref(tt0)-αr⁢e⁢f)⁢vi=(CR⁢A⁢M⁢PCO⁢U⁢T⁢∑i=1mgi,n⁢vigref⁢(tt0)-(αi,n-αr⁢e⁢f))

If αmn˜αref, meaning that the memory cells14mnand the reference memory cell14refsuffer from substantially the same drift, the drift coefficient is zero and drift is compensated for using the circuit.

Reference is now made toFIGS.4B-1and4B-2which each show another embodiment for the combining circuit22. The analog signal ymis dependent on the bit line current from the memory cell14mnat the column output which is mirrored by a current mirror circuit22m(22mAB,22mAC,22mAD) and sourced as current iBLm(iBLmAB, iBLmAC, iBLmAD) to an integrator circuit220. The output voltage for the decision znresult of the MAC decision operation is generated by the integrator circuit220across an integration capacitor Cout. The integrator circuit220includes a differential amplifier222having an inverting input terminal configured to receive a output reference voltage Vref,out. The integration capacitor Cout is connected in feedback between the output terminal of the amplifier222and the non-inverting input terminal. It is the sum of the currents iBL1, . . . , iBLm(iBL1AB, . . . , iBLmAD) generated by the current mirror circuits221, . . . ,22m(221AB, . . . ,22mAD) that is integrated on the output capacitor Cout. A switch formed, for example, by a MOSFET device connected in parallel with the capacitor Cout is selectively activated by reset signal (Reset) to discharge the capacitor Cout at the beginning of each MAC decision operation.

Again, it will be noted that the activation of one word line WL at a time performs a single multiply and accumulate (MAC) operation. Each MAC operation needed for the in-memory computation, for examine in connection with performing matrix-vector multiplication (MVM), requires a different word line selection.

Operation is this case provides for:

VO⁢U⁢T,n=∑i=1mQOUT,iCO⁢U⁢T=IBL,i⁢TON,iCOUT=∑i=1mgi,n(V⁢r⁢ef,t)⁢VrefCO⁢U⁢T⁢vi⁢CR⁢A⁢M⁢PIR⁢A⁢M⁢P=∑i=1mgi,n(V⁢r⁢ef,t)⁢VrefCO⁢U⁢T⁢vi⁢CR⁢A⁢M⁢Pgref(V⁢r⁢e⁢f,t)⁢V⁢r⁢e⁢f=CR⁢A⁢M⁢PCO⁢U⁢T⁢∑i=1mgi,n(V⁢r⁢ef,t)⁢vigref(V⁢r⁢e⁢f,t)

Where: VOUT,n, i.e., zn, is the output voltage across the output capacitor Cout in response to the bit line currents from the memory cell transconductances g1nto gmn, QOUT,iis the corresponding charge contribution of BL<i>, where i=1, . . . , m, COUT is the capacitance of the output capacitor Cout, iBL,iis the mirrored bit line current from the memory cell14in, TON,iis the duration of time for bit line BL<i> current flow for the analog signal yi, gi,nis the transconductance of the memory cell14i,ncorresponding to its programmed weight, Vref is the reference voltage, viis the input voltage corresponding to the feature (or coefficient) data xi, CRAMP is the capacitance of the ramp generator circuit capacitor102, grefis the transconductance of the reference memory cell14ref.

The foregoing mathematical representation is applicable to the use of the circuits shown inFIGS.2B,2C and2Dalong with either of the circuits shown inFIGS.4A-1,4A-2,4B-1and4B-2.

The current mirror circuits221,222, . . . ,22minFIGS.4A-1,4A-2,4B-1and4B-2are shown to have current mirroring ratios of A:B, A:C and A:D, respectively. In an embodiment, B, C and D may all be equal. In this case, each of the currents iBL1, iBL2, . . . , iBLmgenerated by the current mirror circuits221,222, . . . ,22mare given equal weight for the integration process. For this implementation, the biasing circuits201,202, . . . ,20mconnected to the current mirror circuits221,222, . . . ,22mwill be driven in response to inputs v1, v2, . . . , vm, respectively, as shown inFIGS.4A-1and4B-1.

In an alternative embodiment, however, B, C and D are not equal. In this case, each of the currents iBL1, iBL2, . . . , iBLmgenerated by the current mirror circuits221,222, . . . ,22mare given different weights for the integration process. For example only, in an embodiment supporting binary weighting: B=4, C=2 and D=1. The currents iBL1, iBL2, . . . , iBLmfor the integration in this case will be binary weighted. For this implementation, the biasing circuits201,202, . . . ,20mconnected to the current mirror circuits221,222, . . . ,22mwill be driven in response to a common input vmas shown inFIGS.4A-2and4B-2.

It will be noted that with the use of the biasing circuit20membodiment as shown inFIG.2D, the current mirror circuit22minFIGS.4A-1,4A-2,4B-1and4B-2may be provided by the current mirror formed by transistors70,80and82. In other words, transistor82would correspond to the output transistor for the current mirror22m. In this implementation, in the event that binary weighting is desired, the current mirroring ratio (A:B, A:C or A:D) would be implemented between transistors70and82and, as discussed above in connection withFIGS.4B-1and4B-2, the biasing circuits201,202, . . . ,20mwill be driven in response to a common input vm.

Reference is now made toFIG.5which shows a schematic diagram of another embodiment for an in-memory computation circuit10. Like references inFIGS.1and5refer to like or similar components. The circuit10utilizes a memory array12formed by a plurality of memory cells14arranged in a matrix format having m columns and n rows. Each memory cell14mncomprises a pair of bit-cells14mnPand14mnN. In this context, the index mn indicates the column (m) and row (n) location of the cell14, while the suffix of P indicates that the bit-cell is for storing a positive (+) weight and the suffix of N indicates that the bit-cell is for storing a negative (−) weight. Thus, P suffix bit-cells are programmed to store data gmnPrelating to the positive computational weights for an in-memory compute operation, while N suffix bit-cells are programmed to store data gmnNrelating to the negative computational weights for an in-memory compute operation. Only one of the bit-cells in the pair for each memory cell14stores a weight value. In other words, the memory cell14mnstores either a positive weight in the positive bit-cell14mnPor stores a negative weight in the negative bit-cell14mnN.

In this configuration, all of the bit-cells14mnPtogether may be considered to form a first bank of the memory array and all of the bit-cells14mnNtogether may be considered to form a second bank of the memory array.

Each memory cell14mnincludes a word line WL and a pair of bit lines BL. The pair of bit-cells14mnPand14mnNin the memory cells14in a common row of the matrix are connected to each other through a common word line WL<n>. The positive bit-cells14mnPof the memory cells14in a common column of the matrix are connected to each other through a common positive bit line BL<m>P, while the negative bit-cells14mnNof the memory cells14in a common column of the matrix are connected to each other through a common negative bit line BL<m>N.

The word lines WL<1>, . . . , WL<n> are driven by a word line driver circuit18which generates word line signals16in response to a received address signal (Address). The word line driver circuit18decodes the Address and applies the pulse of the word line signal16to one word line WL at a time (illustrated here, as an example, as being applied to word line WL<1>). The pulse width of each word line signal16is fixed and defined by an on time TON.

It is important to note here that the activation of one word line WL at a time performs a single multiply and accumulate (MAC) operation. In order to perform matrix-vector multiplication (MVM), where k MAC operations are implemented (k being less than or equal to n), a sequence of k word line WL activations are required. Consequently, k word line WL on time (Ton) cycles are necessary for the performance of one full MVM operation.

Biasing circuitry20applies a bias (time, voltage and/or current) to the positive and negative bit lines BL in response to feature (or coefficient) data x input to the in-memory computation circuit10. This feature data may, for example, comprise a plurality of multi-bit digital signals x1, . . . , xmthat are processed by the biasing circuits201P,201N, . . . ,20mP,20mNto generate the bias applied to the corresponding word lines WL<1>P, WL<1>N, . . . , WL<n>P, WL<n>N. The biasing circuit20mPis coupled to the positive bit line BL<m>P and the biasing circuit20mNis coupled to the negative bit line BL<m>N, with those biasing circuits both receiving the digital signal xm. The positive or negative analog signal ymP, ymNon the positive or negative bit line BL<m>P, BL<m>N (i.e., the bit line charge) at the column output is then dependent on a product between the bias applied to the bit line and the transconductance gmnPor gmnN(which corresponds to the programmed resistivity) of the bit-cell of the memory cell14mnselected by the word line WL to which the word line signal16is applied. In other words, the memory cell14contributes either a (positive) bit line current for the positive analog signal ymPthat is proportional to xm×gmnP, or a (negative) bit line current for the negative analog signal ymNthat is proportional to xm×gmnN. So, for an example where the word line signal16is applied to word line WL<1>, and the positive bit-cell1411Pof the memory cell1411is programmed with the in-memory computation weight, the positive analog signal y1Pcurrent on the positive bit line BL<1>P is proportional to x1×g11P, and the negative analog signal y1Ncurrent on the negative bit line BL<1>N is zero. Conversely, if instead the negative bit-cell1411Nof the memory cell1411is programmed with the in-memory computation weight, the positive analog signal y1Pcurrent on the positive bit line BL<1>P is zero, and the negative analog signal y1Ncurrent on the negative bit line BL<1>N is proportional to x1×g11N. A similar operation is performed for each column.

The biasing circuits201P,201N, . . . ,20mP,20mNof the biasing circuitry20may have any one of the circuit configurations as shown inFIGS.2B-2D.

A combining circuit22combines, for example through an integration operation, the analog signal y1P, y1N, . . . ymP, ymNcurrents at the column outputs to generate a corresponding decision znresult for the MAC decision operation, where zn=(±g1n×x1)+(±g2n×x2)+ . . . +(±gmn×xm), and where the ± symbol indicates a taking into account of whether the weight gmnis positive or negative. Further processing of the decision znresult may, for example, be made by converting the analog decision signal znto a digital value using an analog-to-digital converter (ADC) which is then processed in a digital signal processing (DSP) circuit.

Reference is now made toFIGS.6-1and6-2which each show an embodiment for the combining circuit22for use with the implementation ofFIG.5. The positive analog signal ymPis dependent on the bit line current from the positive bit-cell14mnPat the column output which is mirrored by a current mirror circuit22mPand sourced as positive current iBLmPto an integrator circuit220. The negative analog signal ymNis dependent on the bit line current from the negative bit-cell14mnPat the column output which is mirrored by a current mirror circuit22mNand sunk as negative current iBLmNfrom the integrator circuit220. The output voltage for the decision znresult of the MAC decision operation is generated by the integrator circuit220across an integration capacitor Cout. The integrator circuit220includes a differential amplifier222having an inverting input terminal configured to receive a output reference voltage Vref,out. The integration capacitor Cout is connected in feedback between the output terminal of the amplifier222and the non-inverting input terminal. It is the sum of the currents iBL1P, iBL1N, . . . , iBLmP, iBLmNgenerated by the current mirror circuits221P,221N,22mP,22mNthat is integrated on the output capacitor Cout. A switch formed, for example, by a MOSFET device connected in parallel with the capacitor Cout is selectively activated by reset signal (Reset) to discharge the capacitor Cout at the beginning of each MAC decision operation.

The current mirror circuits221P,221N, . . . ,22mP,22mNinFIGS.6-1and6-2are shown to have current mirroring ratios of A:B, and A:C, respectively. In an embodiment, B and C may all be equal. In this case, the currents iBL1P, iBL1Ngenerated by the current mirror circuits221P,221Nand the currents iBLmP, iBLmNgenerated by the current mirror circuits22mP,22mNare given equal weight for the integration process. For this implementation, the biasing circuits201P,201N,20mP,20mNconnected to the current mirror circuits221P,221N, . . . ,22mP,22mNwill be driven in response to inputs v1, v2, . . . , vm, respectively, as shown inFIG.6-1.

In an alternative embodiment, however, B and C are not equal. In this case, the currents iBL1P, iBL1Ngenerated by the current mirror circuits221P,221Nand the currents iBLmP, iBLmNgenerated by the current mirror circuits22mP,22mNare given different weights for the integration process. For example only, in an embodiment supporting binary weighting: B=2, C=1. The currents for the integration in this case will be binary weighted. For this implementation, the biasing circuits201P,201N, . . . ,20mP,20mNconnected to the current mirror circuits221P,221N, . . . ,22mP,22mNwill be driven in response to input vm, as shown inFIG.6-2.

It will be noted that with the use of the biasing circuit20membodiment as shown inFIG.2D, the current mirror circuit22mPor22mNinFIG.6may be provided by the current mirror formed by transistors70,80and82. In other words, transistor82would correspond to the output transistor for the current mirror22mPor22mN. In this implementation, in the event that binary weighting is desired, the current mirroring ratio (A:B, A:C) would be implemented between transistors70and82and, as discussed above in connection withFIG.6-2, the biasing circuits201P,201N, . . . ,20mP,20mNwill be driven in response to a common input vm.

Reference is now made toFIG.7which shows a schematic diagram of a further embodiment for an in-memory computation circuit10. Like references inFIGS.1,5and7refer to like or similar components. The circuit10utilizes a memory array12formed by a plurality of memory cells14arranged in a matrix format having m columns and n rows. Each memory cell14mncomprises a pair of bit-cells14mnWand14mnS. In this context, the index mn indicates the column (m) and row (n) location of the cell14, while the suffix of W indicates that the bit-cell is for storing a weight and the suffix of S indicates that the bit-cell is for storing a sign (positive or negative) for that weight.

Each memory cell14includes a word line WL and a pair of bit lines BL. The pair of bit-cells14mnWand14mnSin the memory cells14in a common row of the matrix are connected to each other through a common word line WL<n>. The weight bit-cells14mnWof the memory cells14in a common column of the matrix are connected to each other through a common weight bit line BL<m>W, while the sign bit-cells14mnSof the memory cells14in a common column of the matrix are connected to each other through a common sign bit line BL<m>S.

The word lines WL<1>, . . . , WL<n> are driven by a word line driver circuit18which generates word line signals16in response to a received address signal (Address). The word line driver circuit18decodes the Address and applies the pulse of the word line signal16to one word line WL at a time (illustrated here, as an example, as being applied to word line WL<1>). The pulse width of each word line signal16is fixed and defined by an on time TON. It is important to note here that the activation of one word line WL at a time performs a single multiply and accumulate (MAC) operation. In order to perform matrix-vector multiplication (MVM), where k MAC operations are implemented (k being less than or equal to n), a sequence of k word line WL activations are required. Consequently, k word line WL on time (Ton) cycles are necessary for the performance of one full MVM operation.

Biasing circuitry20applies a bias (time, voltage and/or current) to the weight bit lines BL in response to feature (or coefficient) data x input to the in-memory computation circuit10. This feature data may, for example, comprise a plurality of multi-bit digital signals x1, . . . , xmthat are processed by the biasing circuits201W, . . . ,20mWto generate the bias applied to the corresponding word lines WL<1>W, . . . , WL<n>W. The analog signal ymWon the weight bit line BL<m>W, (i.e., the weight bit line charge) at the column output is then dependent on a product between the bias applied to the bit line and the transconductance gmnW(which corresponds to the programmed resistivity) of the weight bit-cell of the memory cell14mnselected by the word line WL to which the word line signal16is applied. In other words, the weight bit-cell contributes a bit line current for the analog signal ymWthat is proportional to xm×gmnW. So, for an example where the word line signal16is applied to word line WL<1>, and the weight bit-cell1411Wof the memory cell1411is programmed with the in-memory computation weight, the analog signal y1Wcurrent on the weight bit line BL<1>W is proportional to x1×g11W. A similar operation is performed for each column.

The biasing circuits201W, . . . ,20mWof the biasing circuit20may have any one of the circuit configurations as shown inFIGS.2B-2D.

Sign bit lines BL<m>S can optionally have biasing circuitry20, but the applied bias is not dependent on the feature (or coefficient) data x input to the in-memory computation circuit10. Circuit embodiments for the biasing circuits20mSon the sign bit lines BL<m>S are shown inFIGS.2B-S,2C-S and2D-S and have a similar circuit configuration as the biasing circuit20mWused for the weight bit lines BL<m>W as shown inFIGS.2B,2C and2D. These circuits apply the bias voltage Vref to each of the sign bit lines BL<m>S.

The analog signal ymSon the sign bit line BL<m>S, (i.e., the sign bit line charge) is dependent on the transconductance gums (which corresponds to the programmed resistivity) of the sign bit-cell of the memory cell14mnselected by the word line WL to which the word line signal16is applied. So, for an example where the word line signal16is applied to word line WL<1>, and the sign bit-cell1411Sof the memory cell1411is programmed with a positive sign, there is a zero analog signal y1Scurrent on the sign bit line BL<1>S. Conversely, if the sign bit-cell1411Sof the memory cell1411is programmed with a negative sign, there is a non-zero analog signal y1Scurrent on the sign bit line BL<1>S. A similar operation is performed for each column.

A combining circuit22combines, for example through an integration operation, the analog signal y1W, . . . , ymWcurrents, as a function of the analog signal y1S, . . . , ymScurrents (which indicate whether the weight gmnWis positive or negative), to generate a corresponding decision znresult for the MAC decision operation, where zn=(±g1n×x1)+(±g2n×x2)+ . . . +(±gmn×xm), and where the ± symbol indicates the taking into account of whether the weight is positive or negative. Further processing of the decision znresult may, for example, be made by converting the analog decision signal znto a digital value using an analog-to-digital converter (ADC) which is then processed in a digital signal processing (DSP) circuit.

Reference is now made toFIGS.8-1and8-2which shows an embodiment for the combining circuit22for use with the implementation ofFIG.7. The analog signal ymWwhich is the bit line current from the weight bit-cell14mnWat the column output is mirrored by a current mirror circuit22mand sourced as current iBLmto a current switching circuit formed by a pair of MOSFET devices160,162. When device160is turned on, the current iBLmis inverted by a current mirror circuit164and sunk as negative current iBLmNfrom node166. Conversely, when device162is turned on, the current iBLmis sourced as positive current iBLmPto node166. The analog signal ymSwhich is the bit line current from the sign bit-cell14mnSis compared to a reference current irefusing a comparison circuit formed by pair of current mirrors170,172. The result of the current comparison is a logic signal output at node174and applied to drive the operation of the transistors160,162of the current switching circuit. The logic signal output at node174is applied to the gate of transistor160and further applied to the gate of transistor164through a logic inverter. When the bit line current from the sign bit-cell14mnSis less than the reference current iref, this being indicative of the sign bit-cell14mnSis storing a value for a positive sign, the logic signal at node174is logic low causing the transistor162to turn on (and the transistor160to turn off). The positive current iBLmPis then sourced to node166. On the other hand, when the bit line current from the sign bit-cell14mnSis more than the reference current iref, this being indicative of the sign bit-cell14mnSis storing a value for a negative sign, the logic signal at node174is logic high causing the transistor160to turn on (and the transistor162to turn off). The negative current iBLmNis then sunk from node166.

The currents sourced to/sunk from the node166are applied to an integrator circuit220. The output voltage for the decision znresult of the MAC decision operation is generated by the integrator circuit220across an integration capacitor Cout. The integrator circuit220includes a differential amplifier222having an inverting input terminal configured to receive a output reference voltage Vref,out. The integration capacitor Cout is connected in feedback between the output terminal of the amplifier222and the non-inverting input terminal. It is the sum of the currents iBL1P(or iBL1N), . . . , iBLmP(or iBLmN) applied to node166that is integrated on the output capacitor Cout. A switch formed, for example, by a MOSFET device connected in parallel with the capacitor Cout is selectively activated by reset signal (Reset) to discharge the capacitor Cout at the beginning of each MAC decision operation.

The current mirror circuits221, . . . ,22minFIGS.8-1and8-2are shown to have current mirroring ratios of A:B, and A:C, respectively. In an embodiment, B and C may all be equal. In this case, each of the currents iBL1, . . . , iBLmgenerated by the current mirror circuits221, . . . ,22mare given equal weight for the integration process. For this implementation, the biasing circuits201W, . . . ,20mWconnected to the current mirror circuits221, . . . ,22mwill be driven in response to inputs v1, . . . , vm, respectively, as shown inFIG.8-1.

In an alternative embodiment, however, B and C are not equal. In this case, the currents iBL1, iBLmgenerated by the current mirror circuits221,22mare given different weights for the integration process. For example only, in an embodiment supporting binary weighting: B=2, C=1. The currents iBL1, iBLmfor the integration in this case will be binary weighted. For this implementation, the biasing circuits201W, . . . ,20mWconnected to the current mirror circuits221, . . . ,22mwill be driven in response to input vmas shown inFIG.8-2.

It will be noted that with the use of the biasing circuit20membodiment as shown inFIG.2D, the current mirror circuit22minFIG.8may be provided by the current mirror formed by transistors70,80and82. In other words, transistor82would correspond to the output transistor for the current mirror22m. In this implementation, in the event that binary weighting is desired, the current mirroring ratio (A:B, or A:C) would be implemented between transistors70and82and, as discussed above in connection withFIG.8-2, the biasing circuits201W, . . . ,20mWwill be driven in response to a common input vm.

Reference is now made toFIG.9which shows a schematic diagram of a further embodiment for an in-memory computation circuit10. Like references inFIGS.7and9refer to like or similar components. The circuit10utilizes a memory array12formed by a plurality of memory cells14mnarranged in a matrix format having m columns and n rows. Each memory cell14comprises a pair of bit-cells14mnWand14mnS. In this context, the index mn indicates the column (m) and row (n) location of the cell14, while the suffix of W indicates that the bit-cell is for storing a weight and the suffix of S indicates that the bit-cell is for storing a sign (positive or negative) for that weight.

Each memory cell14includes a word line WL and a pair of bit lines BL. The pair of bit-cells14mnWand14mnSin the memory cells14in a common row of the matrix are connected to each other through a common word line WL<n>. The weight bit-cells14mnWof the memory cells14in a common column of the matrix are connected to each other through a common weight bit line BL<m>W, while the sign bit-cells14mnSof the memory cells14in a common column of the matrix are connected to each other through a common sign bit line BL<m>S.

The word lines WL<1>, . . . , WL<n> are driven by a word line driver circuit18which generates word line signals16in response to a received address signal (Address). The word line driver circuit18decodes the Address and applies the pulse of the word line signal16to one word line WL at a time (illustrated here, as an example, as being applied to word line WL<1>). The pulse width of each word line signal16is fixed and defined by an on time TON.

It is important to note here that the activation of one word line WL at a time performs a single multiply and accumulate (MAC) operation. In order to perform matrix-vector multiplication (MVM), where k MAC operations are implemented (k being less than or equal to n), a sequence of k word line WL activations are required. Consequently, k word line WL on time (Ton) cycles are necessary for the performance of one full MVM operation.

The circuit ofFIG.9differs from the circuit ofFIG.7in that it can also take into account the sign of the plurality of multi-bit digital signals x1, . . . , xmthat form the feature data. In this case, consider that one bit xmSof each multi-bit digital signal xmis reserved for indicating the sign (positive or negative) of the feature data value. This bit xmSis input to the combining circuit22. The remaining bits xmVof each multi-bit digital signal xmindicate the value of the feature data and are applied to biasing circuitry20through the voltage vm.

The biasing circuitry20applies a bias (time, voltage and/or current) to the weight bit lines BL in response to the remaining bits xmVof the feature (or coefficient) data. The bits x1V, . . . , xmVare processed by the biasing circuits201W, . . . ,20mWto generate the bias applied to the corresponding word lines WL<1>W, WL<n>W. The analog signal ymWon the weight bit line BL<m>W, (i.e., the weight bit line charge) at the column output is then dependent on a product between the bias applied to the bit line and the transconductance gmnW(which corresponds to the programmed resistivity) of the weight bit-cell of the memory cell14mnselected by the word line WL to which the word line signal16is applied. In other words, the weight bit-cell contributes a bit line current for the analog signal ymWthat is proportional to xmV×gmnW. So, for an example where the word line signal16is applied to word line WL<1>, and the weight bit-cell1411Wof the memory cell1411is programmed with the in-memory computation weight, the analog signal y1Wcurrent on the weight bit line BL<1>W is proportional to x1V×g11W. A similar operation is performed for each column.

The biasing circuits201W, . . . ,20mWof the biasing circuitry20may have any one of the circuit configurations as shown inFIGS.2B-2D.

There is also biasing circuitry20for the sign bit lines BL<m>S, but the applied bias is not dependent on the feature (or coefficient) data x input to the in-memory computation circuit10. Circuit embodiments for the biasing circuits20mSon the sign bit lines BL<m>S are shown inFIGS.2B-S,2C-S and2D-S and have a similar circuit configuration as the biasing circuit20mWused for the weight bit lines BL<m>W as shown inFIGS.2B,2C and2D. These circuits apply the bias voltage Vref to each of the sign bit lines BL<m>S.

The analog signal ymSon the sign bit line BL<m>S, (i.e., the sign bit line charge) is dependent on the transconductance (which corresponds to the programmed resistivity) of the sign bit-cell of the memory cell14mnselected by the word line WL to which the word line signal16is applied. So, for an example where the word line signal16is applied to word line WL<1>, and the sign bit-cell1411Sof the memory cell14iiis programmed with a positive sign, there is a zero analog signal y1Scurrent on the sign bit line BL<1>S. Conversely, if the sign bit-cell1411Sof the memory cell1411is programmed with a negative sign, there is a non-zero analog signal y1Scurrent on the sign bit line BL<1>S. A similar operation is performed for each column.

The combining circuit22combines, for example through an integration operation, the analog signal y1W, . . . , ymWcurrents, as a function of the analog signal y1S, . . . ymScurrents (which indicate whether the weight gmnis positive or negative) and the sign bit xmS(which indicate whether the multi-bit digital signal xmis a positive or negative feature data value), to generate a corresponding decision znresult for the MAC decision operation, where zn=(±g1n×±x1V)+(±g2n×±x2V)+ . . . +(±gmn×±xmV), and where the ± symbols indicate the taking into account of whether the weight and/or feature data value is positive or negative. Further processing of the decision znresult may, for example, be made by converting the analog decision signal znto a digital value using an analog-to-digital converter (ADC) which is then processed in a digital signal processing (DSP) circuit.

Reference is now made toFIGS.10-1and10-2which show an embodiment for the combining circuit22for use with the implementation ofFIG.9. The analog signal ymWwhich is the bit line current from the weight bit-cell14mnWat the column output is mirrored by a current mirror circuit22mand sourced as current iBLmto a current switching circuit formed by a pair of MOSFET devices160,162. When device160is turned on, the current iBLmis inverted by a current mirror circuit164and sunk as negative current iBLmNfrom node166. Conversely, when device162is turned on, the current iBLmis sourced as positive current iBLmPto node166. The analog signal ymSwhich is the bit line current from the sign bit-cell14mnSis compared to a reference current irefusing a comparison circuit formed by pair of current mirrors170,172. The result of the current comparison is a logic signal output at node174. The logic signal at node174is then logically combined with the sign bit xmSto produce a control signal that is applied to drive the operation of the transistors160,162of the current switching circuit. The logic circuit for logically combining the logic signal at node174with the sign bit xmSmay, for example, comprise an exclusive-OR (XOR) gate whose output is applied to the gate of transistor164and whose output is further applied to the gate of transistor160through a logic inverter.

When the bit line current from the sign bit-cell14mnSis less than the reference current iref, this being indicative of the sign bit-cell14mnSis storing a value for a positive sign, the logic signal at node174is logic low, and when the sign bit xmSis also logic low, this being indicative of the remaining bits xmVof the feature (or coefficient) data having a positive sign, the control signal for the current switching circuit output by the XOR gate will be logic low causing the transistor162to turn on (and the transistor160to turn off). The positive current iBLmPis then sourced to node166.

When the bit line current from the sign bit-cell14mnSis less than the reference current iref, this being indicative of the sign bit-cell14mnSis storing a value for a positive sign, the logic signal at node174is logic low, and when the sign bit xmSis logic high, this being indicative of the remaining bits xmVof the feature (or coefficient) data having a negative sign, the control signal for the current switching circuit output by the XOR gate will be logic high causing the transistor160to turn on (and the transistor162to turn off). The negative current iBLmNis then sunk from node166.

When the bit line current from the sign bit-cell14mnSis more than the reference current iref, this being indicative of the sign bit-cell14mnSis storing a value for a negative sign, the logic signal at node174is logic high, and when the sign bit xmSis logic low, this being indicative of the remaining bits xmVof the feature (or coefficient) data having a positive sign, the control signal for the current switching circuit output by the XOR gate will be logic high causing the transistor160to turn on (and the transistor162to turn off). The negative current iBLmNis then sunk from node166.

When the bit line current from the sign bit-cell14mnSis more than the reference current iref, this being indicative of the sign bit-cell14mnSis storing a value for a negative sign, the logic signal at node174is logic high, and when the sign bit xmSis logic high, this being indicative of the remaining bits xmVof the feature (or coefficient) data having a negative sign, the control signal for the current switching circuit output by the XOR gate will be logic low causing the transistor162to turn on (and the transistor160to turn off). The positive current iBLmPis then sourced to node166.

The currents sourced to/sunk from the node166are applied to an integrator circuit220. The output voltage for the decision znresult of the MAC decision operation is generated by the integrator circuit220across an integration capacitor Cout. The integrator circuit220includes a differential amplifier222having an inverting input terminal configured to receive a output reference voltage Vref,out. The integration capacitor Cout is connected in feedback between the output terminal of the amplifier222and the non-inverting input terminal. It is the sum of the currents iBL1P(or iBL1N), . . . , iBLmP(or iBLmN) applied to node166that is integrated on the output capacitor Cout. A switch formed, for example, by a MOSFET device connected in parallel with the capacitor Cout is selectively activated by reset signal (Reset) to discharge the capacitor Cout at the beginning of each MAC decision operation.

The current mirror circuits221, . . . ,22minFIGS.10-1and10-2are shown to have current mirroring ratios of A:B, and A:C, respectively. In an embodiment, B and C may all be equal. In this case, each of the currents iBL1, . . . , iBLmgenerated by the current mirror circuits221, . . . ,22mare given equal weight for the integration process. For this implementation, the biasing circuits201W, . . . ,20mWconnected to the current mirror circuits221, . . . ,22mwill be driven in response to inputs v1, . . . , vm, respectively, as shown inFIG.10-1.

In an alternative embodiment, however, B and C are not equal. In this case, the currents iBL1, iBLmgenerated by the current mirror circuits221,22mare given different weights for the integration process. For example only, in an embodiment supporting binary weighting: B=2, C=1. The currents iBL1, iBLmfor the integration in this case will be binary weighted. For this implementation, the biasing circuits201W, . . . ,20mWconnected to the current mirror circuits221, . . . ,22mwill be driven in response to input vmas shown inFIG.10-1.

It will be noted that with the use of the biasing circuit20membodiment as shown inFIG.2D, the current mirror circuit22minFIG.10may be provided by the current mirror formed by transistors70,80and82. In other words, transistor82would correspond to the output transistor for the current mirror22m. In this implementation, in the event that binary weighting is desired, the current mirroring ratio (A:B, or A:C) would be implemented between transistors70and82and, as discussed above in connection withFIG.10-2, the biasing circuits201W, . . . ,20mWwill be driven in response to a common input vm.

Reference is now made toFIG.11which shows a schematic diagram of a further embodiment for an in-memory computation circuit10. Like references inFIGS.1and11refer to like or similar components. The circuit10utilizes a memory array12formed by a plurality of memory cells14arranged in a matrix format having m columns and n rows. Each memory cell14is programmed to store data gmnrelating to the computational weights for an in-memory compute operation.

Each memory cell14includes a word line WL and a bit line BL. The memory cells14in a common row of the matrix are connected to each other through a common word line WL. The memory cells14in a common column of the matrix are connected to each other through a common bit line BL. The word lines WL<1>, WL<n> are driven by a word line driver circuit18which generates word line signals16in response to a received address signal (Address). The word line driver circuit18decodes the Address and applies the pulse of the word line signal16to one word line WL at a time (illustrated here, as an example, as being applied to word line WL<1>). The pulse width of each word line signal16is fixed and defined by an on time TON.

It is important to note here that the activation of one word line WL at a time performs a single multiply and accumulate (MAC) operation. In order to perform matrix-vector multiplication (MVM), where k MAC operations are implemented (k being less than or equal to n), a sequence of k word line WL activations are required. Consequently, k word line WL on time (Ton) cycles are necessary for the performance of one full MVM operation.

The circuit ofFIG.11differs from the circuit ofFIG.1in that it can also take into account the sign of the plurality of multi-bit digital signals x1, . . . , xmthat form the feature data. In this case, consider that one bit xmSof each multi-bit digital signal xmis reserved for indicating the sign (positive or negative) of the feature data value. This bit xmSis input to the combining circuit22. The remaining bits xmVof each multi-bit digital signal xmindicate the value of the feature data and are applied to biasing circuitry20as the voltage vm.

The biasing circuitry20applies a bias (time, voltage and/or current) to the bit lines BL in response to the remaining bits xmVof the feature (or coefficient) data. The bits xiv, xmVare processed by the biasing circuits201, . . . ,20mto generate the bias applied to the corresponding word lines WL<1>, . . . , WL<n>. The analog signal ymon the bit line BL<m>, (i.e., the weight bit line charge) at the column output is then dependent on a product between the bias applied to the bit line and the transconductance (which corresponds to the programmed resistivity) of the memory cell14mnselected by the word line WL to which the word line signal16is applied. In other words, the memory cell contributes a bit line current for the analog signal ymthat is proportional to xmV×gmn. So, for an example where the word line signal16is applied to word line WL<1>, and the memory cell1411is programmed with the in-memory computation weight, the analog signal y1current on the bit line BL<1> is proportional to x1V×g11.

The biasing circuits201W, . . . ,20mWof the biasing circuitry20may have any one of the circuit configurations as shown inFIGS.2B-2D.

A combining circuit22combines, for example through an integration operation, the analog signal y1, . . . , ymcurrents as a function of the sign bit xmS(which indicates whether the multi-bit digital signal xmis a positive or negative feature data value), to generate a corresponding decision znresult for the MAC decision operation, where zn=(g1n×±x1V)+(g2n×±x2V)+ . . . +(gmn×±xmV), and where the ± symbol indicates the taking into account of whether the feature data is positive or negative. Further processing of the decision znresult may, for example, be made by converting the analog decision signal znto a digital value using an analog-to-digital converter (ADC) which is then processed in a digital signal processing (DSP) circuit.

Reference is now made toFIGS.12-1and12-2which show an embodiment for the combining circuit22for use with the implementation ofFIG.11. The analog signal ymwhich is the bit line current from the memory cell14mnat the column output is mirrored by a current mirror circuit22mand sourced as current iBLmto a current switching circuit formed by a pair of MOSFET devices160,162. When device160is turned on, the current iBLmis inverted by a current mirror circuit164and sunk as negative current iBLmNfrom node166. Conversely, when device162is turned on, the current iBLmis sourced as positive current iBLmPto node166. The sign bit xmSprovides a control signal that is applied to drive the operation of the transistors160,162of the current switching circuit.

When the sign bit xmSis logic low, this being indicative of the remaining bits xmVof the feature (or coefficient) data having a positive sign, the control signal for the current switching circuit will be logic low causing the transistor162to turn on (and the transistor160to turn off). The positive current iBLmPis then sourced to node166.

When the sign bit xmSis logic high, this being indicative of the remaining bits xmVof the feature (or coefficient) data having a negative sign, the control signal for the current switching circuit will be logic high causing the transistor160to turn on (and the transistor162to turn off). The negative current iBLmNis then sunk from node166.

The currents sourced to/sunk from the node166are applied to an integrator circuit220. The output voltage for the decision znresult of the MAC decision operation is generated by the integrator circuit220across an integration capacitor Cout. The integrator circuit220includes a differential amplifier222having an inverting input terminal configured to receive a output reference voltage Vref,out. The integration capacitor Cout is connected in feedback between the output terminal of the amplifier222and the non-inverting input terminal. It is the sum of the currents iBL1P(or iBL1N), . . . , iBLmP(or iBLmN) applied to node166that is integrated on the output capacitor Cout. A switch formed, for example, by a MOSFET device connected in parallel with the capacitor Cout is selectively activated by reset signal (Reset) to discharge the capacitor Cout at the beginning of each MAC decision operation.

The current mirror circuits221, . . . ,22minFIGS.12-1and12-2are shown to have current mirroring ratios of A:B, A:C and A:D, respectively. In an embodiment, B, C and D may all be equal. In an embodiment, B, C and D may all be equal. In this case, each of the currents iBL1, iBL2, . . . , iBLmgenerated by the current mirror circuits221,222, . . . ,22mare given equal weight for the integration process. For this implementation, the biasing circuits201, . . . ,20mconnected to the current mirror circuits221, . . . ,22mwill be driven in response to inputs v1, . . . , vm, respectively, as shown inFIG.12-1.

In an alternative embodiment, however, B, C and D are not equal. In this case, each of the currents iBL1, iBL2, . . . , iBLmgenerated by the current mirror circuits221,222, . . . ,22mare given different weights for the integration process. For example only, in an embodiment supporting binary weighting: B=4, C=2 and D=1. The currents iBL1, iBL2, . . . , iBLmfor the integration in this case will be binary weighted. For this implementation, the biasing circuits201, . . . ,20mconnected to the current mirror circuits221, . . . ,22mwill be driven in response to input vmas shown inFIG.12-2.

It will be noted that with the use of the biasing circuit20membodiment as shown inFIG.2D, the current mirror circuit22minFIG.12may be provided by the current mirror formed by transistors70,80and82. In other words, transistor82would correspond to the output transistor for the current mirror22m. In this implementation, in the event that binary weighting is desired, the current mirroring ratio (A:B, A:C or A:D) would be implemented between transistors70and82and, as discussed above in connection withFIG.12-2, the biasing circuits201, . . . ,20mwill be driven in response to a common input vm.

Reference is now made toFIG.13which shows a further embodiment for the combining circuit. In this implementation, the array12is divided into a positive bank including columns300of memory cells14storing positive weight data and a negative bank including columns302of memory cells14storing negative weight data. Although not shown inFIG.13, it will be understood that each bank may be arranged in the manner of a memory array12as shown inFIG.1which is accessed through word lines. The configuration of the combining circuit is similar to that shown inFIGS.12-1and12-2except that there are distinct combining circuits for the bit lines BL<m>P of the positive bank and the bit lines BL<m>N of the positive bank. The currents from the positive bank and the currents from the negative bank are summed and then integrated at the integrator circuit220to support signed MAC operations dependent on the sign of the weight data. The inclusion of the current steering circuits in the combining circuits with the positive/negative current steering operation driven by the sign bit xmSsupports signed MAC operations dependent on the sign of the feature data. It will be noted that the bias circuits are all driven here in response to the common input vmin connection with implementation of binary weighting for A:B and A:C.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.