Patent ID: 12255146

DETAILED DESCRIPTION

Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

It shall be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limited to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be further understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

FIG.1is a cross-sectional view of a semiconductor device100a, in accordance with some embodiments of the present disclosure.

In some embodiments, the semiconductor device100amay include a substrate110. The substrate110may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate110can include an elementary semiconductor including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may a SiGe alloy with a gradient Ge feature in which the Si and Ge composition changes from one ratio at one location to another ratio at another location of the gradient SiGe feature. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, a SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate110may have a multilayer structure, or the substrate110may include a multilayer compound semiconductor structure.

In some embodiments, the semiconductor device100amay include a dielectric layer112. The dielectric layer112may be disposed on or over the substrate110. The dielectric layer112may include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material (k<4), a high-k dielectric material (k<4), or other suitable materials.

In some embodiments, the semiconductor device100amay include a dielectric layer114. The dielectric layer114may be disposed on or over the dielectric layer112. The dielectric layer114may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, a low-k dielectric material, a high-k dielectric material, or other suitable materials. In some embodiments, the material of the dielectric layer114may be different from the dielectric layer112.

Although not shown inFIG.1, some features, such as transistors, diodes, and/or capacitors, may be formed within the substrate110, dielectric layer112, and/or dielectric layer114. For example, gate structures, doped regions, and/or other conductive features may be formed within the substrate110, dielectric layer112, and/or dielectric layer114.

In some embodiments, the gate structure may include a gate dielectric, which may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer can include dielectric material(s), such as high-k dielectric material. The high-k dielectric material may have a dielectric constant (k value) greater than 4. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2) or another applicable material. The gate structure may include a gate electrode. The gate electrode may include polysilicon, tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), the like, and/or a combination thereof.

Doped regions may be doped with p type and/or n type dopants. In some embodiments, n type dopants may include arsenic (As), phosphorus (P), other group V elements, or any combination thereof. In some embodiments, p type dopants may include boron (B), other group III elements, or any combination thereof.

In some embodiments, the semiconductor device100amay include a dielectric layer116. The dielectric layer116may be disposed on or over the dielectric layer114. The dielectric layer116may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, a low-k dielectric material, a high-k dielectric material, or other suitable materials. In some embodiments, the material of the dielectric layer116may be different from that of the dielectric layer114. In some embodiments, the material of the dielectric layer116may be the same as that of the dielectric layer112. The dielectric layer116may also be referred to as an isolation feature. The dielectric layer116may have a surface116s1(or a lateral surface).

In some embodiments, the semiconductor device100amay include a dielectric layer118. The dielectric layer118may be disposed on or over the dielectric layer116. The dielectric layer118may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, a low-k dielectric material, a high-k dielectric material, or other suitable materials. In some embodiments, the material of the dielectric layer118may be different from that of the dielectric layer116. In some embodiments, the material of the dielectric layer118may be the same as that of the dielectric layer114. The dielectric layer118may have a surface118s1(or a lateral surface), a surface118s2(or a lower surface), and a surface118s3(or an upper surface). In some embodiments, the surface118s1of the dielectric layer118may be non-coplanar with the surface116s1of the dielectric layer116. In some embodiments, the surface116s1of the dielectric layer116may be recessed from the surface118s1of the dielectric layer118.

In some embodiments, the semiconductor device100amay include interconnection structures125-1and125-2. The interconnection structure125-2may be disposed adjacent to the interconnection structure125-1. In some embodiments, each of the interconnection structures125-1and125-2may be disposed on the surface116s1of the dielectric layer116. In some embodiments, each of the interconnection structures125-1and the interconnection structure125-2may be covered by the dielectric layer118. Each of the interconnection structures125-1and the interconnection structure125-2may be configured to serve as a part of a conductive path or a channel transmitting carriers, such as holes and/or electrons. In some embodiments, the interconnection structure125-1may include layers126-1and128-1. In some embodiments, the interconnection structure125-2may include layers126-2and128-2.

The layer126-1may be disposed on the surface116s1of the dielectric layer116. In some embodiments, the layer126-1may be in contact with the surface116s1of the dielectric layer116. In some embodiments, the layer126-1may extend between the dielectric layer114and the dielectric layer118. In some embodiments, the layer126-1may include a semiconductor material, such as silicon (Si), silicon-germanium (SiGe), or other suitable materials. In some embodiments, the layer126-1may include a conductive material, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

The layer126-2may be disposed on the surface116s1of the dielectric layer116. In some embodiments, the layer126-2may be in contact with the surface116s1of the dielectric layer116. In some embodiments, the layer126-2may extend between the dielectric layer114and the dielectric layer118. In some embodiments, the material of the layer126-2may be the same as that of the layer126-1. Each of the layer126-1and the layer126-2may have a surface126s1and a surface126s2opposite to the surface126s1. Each of the surface126s1and the surface126s2may also be referred to as a lateral surface. In some embodiments, the dielectric layer116may be disposed on the surface126s2of the layer126-1.

The layer128-1may be disposed on the surface126s1of the layer126-1. In some embodiments, the layer128-1may be in contact with the surface126s1of the layer126-1. In some embodiments, the layer128-1may extend between the dielectric layer114and the dielectric layer118. In some embodiments, the layer128-1may include a semiconductor material, germanium (Ge) or other suitable materials. In some embodiments, the layer128-1may include a conductive material, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof. In some embodiments, the material of the layer128-1may be different from that of the layer126-1.

The layer128-2may be disposed on the surface126s1of the layer126-2. In some embodiments, the layer128-2may be in contact with the surface126s1of the layer126-2. In some embodiments, the layer128-2may extend between the dielectric layer114and the dielectric layer118. In some embodiments, the material of the layer128-2may be the same as that of the layer128-1. In some embodiments, the layer128-1may face the layer128-2. Each of the layers128-1and128-2may have a surface128s1(or a lateral surface). In some embodiments, the surface128s1of the layer128may be substantially coplanar with the surface118s1of the dielectric layer118. In some embodiments, a roughness of the surface118s1of the dielectric layer118may be different from that of the surface128s1of the layer128.

Each of the layer126-1and the layer126-2may have a horizontal dimension H1(e.g., length, thickness, and/or width). Each of the layer128-1and the layer128-2may have a horizontal dimension H2(e.g., length, thickness, and/or width). Each of the layer126-1and the layer126-2may have a vertical dimension V1(e.g., length, thickness, and/or width). Each of the layer128-1and the layer128-2may have a vertical dimension V2(e.g., length, thickness, and/or width). In some embodiments, the horizontal dimension H1of the layer126-1may be substantially the same as the horizontal dimension H2of the layer128-1. In some embodiments, the vertical dimension V1of the layer126-1may be substantially the same as the vertical dimension V2of the layer128-1.

In some embodiments, the semiconductor device100amay include a dielectric layer130. The dielectric layer130may be disposed on or over the dielectric layer118. The dielectric layer130may cover the surface118s3of the dielectric layer118. The dielectric layer130may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, a low-k dielectric material, a high-k dielectric material, or other suitable materials. In some embodiments, the material of the dielectric layer130may be different from that of the dielectric layer118. In some embodiments, the material of the dielectric layer130may be the same as that of the dielectric layer116. The dielectric layer130may have a surface130s1(or a lower surface). In some embodiments, the surface130s1of the dielectric layer130may protrude toward the substrate110. In some embodiments, the surface130s1may be a curved surface. In some embodiments, the dielectric layer130may have a protruding portion1301. In some embodiments, the protruding portion1301may protrude toward the substrate110. In some embodiments, the protruding portion1301of the dielectric layer130may be in contact with the surface118s1of the dielectric layer118.

In some embodiments, the semiconductor device100amay include air gaps132. In some embodiments, the dielectric constant of the air gap132may be different from that of the dielectric layer116. In some embodiments, the dielectric constant of the air gap132may be less than that of the dielectric layer116. The air gap132may also be referred to as an isolation feature. In some embodiments, the air gap132may be defined by the interconnection structures (e.g.,125-1or125-2), the dielectric layer130, and the dielectric layer114. In some embodiments, each of the layer128-1and the layer128-2may be exposed to the air gap132. In some embodiments, the surface128s1of the layer128-1(or128-2) may be exposed to the air gap132. In some embodiments, the interconnection structure125-1may be spaced apart from the interconnection structure125-2by the air gap132. In some embodiments, the layer128-1may be spaced apart from the layer128-2by the air gap132.

In some embodiments, a horizontal dimension (not annotated in the figures) of the air gap132may be greater than the horizontal dimension H1of the layer126-1. In some embodiments, a horizontal dimension (not annotated in the figures) of the dielectric layer116may be greater than the horizontal dimension H1of the layer126-1. In some embodiments, the horizontal dimension of the dielectric layer116may be the same as the horizontal dimension of the air gap132. In some embodiments, the horizontal dimension of the dielectric layer116may be twice as big as the horizontal dimension H1of the layer126-1. In some embodiments, the horizontal dimension of the air gap132may be twice as big as the horizontal dimension H1of the layer126-1.

In this embodiment, the interconnection structure125-1(or125-2) is made of at least two different materials. The interconnection structure125-1(or125-2) may be proximal to two isolation features (e.g., dielectric layer116and air gap132) with different dielectric constants. Such an asymmetry structure may be applied in semiconductor devices, such as a memory device, to control electrical properties.

FIG.2is a cross-sectional view of a semiconductor device100b, in accordance with some embodiments of the present disclosure. The semiconductor device100bshown inFIG.2can be similar to the semiconductor device100ashown inFIG.1, differing in that the dielectric layer114of the semiconductor device100bmay have a recessed surface.

In some embodiments, the dielectric layer114may have a surface114s1and a surface114s2. The surface114s1may also be referred to as an upper surface. The surface114s2may also be referred to as a lateral surface. The layer126-1may have a surface126s3(or a lower surface). The layer128-1may have a128s2(or a lower surface). In some embodiments, the surface114s1of the dielectric layer114may be non-coplanar with the surface126s3of the layer126-1. In some embodiments, the surface114s1of the dielectric layer114may be lower than the surface126s3of the layer126-1. In some embodiments, the surface114s1of the dielectric layer114may be non-coplanar with the surface128s2of the layer128-1. In some embodiments, the surface114s1of the dielectric layer114may be lower than the surface128s2of the layer128-1. In some embodiments, the surface114s2of the dielectric layer114may be substantially coplanar with the surface128s1of the layer128. In some embodiments, the surface114s2of the dielectric layer114may be exposed to the air gap132. In other words, a portion of a top surface of the dielectric layer114is exposed to the air gap132.

FIG.3is a cross-sectional view of a semiconductor device100c, in accordance with some embodiments of the present disclosure. The semiconductor device100cshown inFIG.3can be similar to the semiconductor device100ashown inFIG.1, differing in that the layer126-1(or126-2) may have uneven horizontal dimensions.

In some embodiments, each of the layers126-1and126-2may have extending portions1261and1262. In some embodiments, the extending portion1261may extend toward the air gap132. In some embodiments, the extending portion1262may extend toward the air gap132. In some embodiments, the extending portion1261may be disposed over the surface114s1of the dielectric layer114. In some embodiments, the extending portion1261of the layer126-1may be disposed between the layer128-1and the dielectric layer114. In some embodiments, the extending portion1262of the layer126-1may be disposed between the layer128-1and the dielectric layer118. In some embodiments, the surface128s1of the layer128-1may be non-coplanar with the surface118s1of the layer118. In some embodiments, the surface128s1of the layer128-1may exceed the surface118s1of the layer118.

In some embodiments, the air gap132may have uneven horizontal dimensions. The air gap132may have a horizontal dimension H3at a horizontal level L1. The air gap132may have a horizontal dimension H4at a horizontal level L2. The air gap132may have a horizontal dimension H5at a horizontal level L3. The horizontal level H2may be higher than the horizontal level H1. The horizontal level H3may be higher than the horizontal level H2. In some embodiments, the horizontal dimension H3may be less than the horizontal dimension H4. In some embodiments, the horizontal dimension H5may be less than the horizontal dimension H4. In some embodiments, the horizontal dimension H3may be substantially the same as the horizontal dimension H5.

FIG.4is a flowchart illustrating a method200of manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.

The method200begins with operation202in which a substrate is provided. A first dielectric layer may be formed on or over the substrate. A second dielectric layer may be formed on or over the first dielectric layer. In some embodiments, the material of the first dielectric layer may be different from that of the second dielectric layer.

The method200continues with operation204in which a first isolation feature may be formed on or over the second dielectric layer. A third dielectric layer may be formed on or over the first isolation feature. In some embodiments, the material of the first isolation feature may be different from that of the third dielectric layer.

The method200continues with operation206in which a mask may be formed on or over the third dielectric layer. In some embodiments, the mask may include a photoresist. In some embodiments, the mask may define a plurality of openings. A first portion of the third dielectric layer may be exposed by the mask. A first portion of the first isolation feature may be exposed by the mask.

The method200continues with operation208in which a first etching process may be performed. In some embodiments, the first portion of the third dielectric layer may be removed. In some embodiments, the first portion of the first isolation feature may be removed. In some embodiments, a plurality of first openings may be formed. The upper surface of the second dielectric layer may be exposed to the first openings. In some embodiments, a second portion of the first isolation feature may be exposed to the first openings.

The method200continues with operation210in which a second etching process may be performed. The second etching process may have a selectivity with respect to the first isolation feature and the third dielectric layer. The second portion of the first isolation feature may be removed. A plurality of second openings may be formed. The second opening may be connected to the first opening. In some embodiments, a lateral surface of the first isolation feature may be recessed from the lateral surface of the third dielectric layer. In some embodiments, a lower surface of the third dielectric layer may be exposed to the second opening. An upper surface of the third dielectric layer may be exposed.

The method200continues with operation212in which a material layer may be formed. The material layer may include a semiconductor material or a conductive material. In some embodiments, the material layer may be formed on the lateral surface of the third dielectric layer. In some embodiments, the material layer may be formed on the lower surface of the third dielectric layer. In some embodiments, the material layer may be formed on the upper surface of the third dielectric layer. In some embodiments, the material layer may be formed on the lateral surface of the first isolation feature. In some embodiments, the material layer may be formed on the upper surface of the second dielectric layer.

The method200continues with operation214in which a portion of the material layer may be removed to form a first layer. In some embodiments, the material layer on the upper surface of the third dielectric layer may be removed. In some embodiments, the material layer on the lower surface of the third dielectric layer may be removed. In some embodiments, the material layer on the lateral surface of the third dielectric layer may be removed. In some embodiments, the material layer on the upper surface of the second dielectric layer may be removed. In some embodiments, the first layer may remain on the lateral surface of the first isolation feature.

The method200continues with operation216in which a second layer may be formed on the first layer. In some embodiments, the second layer may be selectively formed on the lateral surface of the first layer. As a result, an interconnection structure, including the first layer and the second layer, may be produced.

The method200continues with operation218in which a fourth dielectric layer may be formed on the third dielectric layer. In some embodiments, an air gap may be formed. The air gap may be surrounded by the fourth dielectric layer, the second layer, and the second dielectric layer. As a result, a semiconductor device may be produced.

The method200is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, or after each operation of the method200, and some operations described can be replaced, eliminated, or reordered for additional embodiments of the method. In some embodiments, the method200can include further operations not depicted inFIG.4. In some embodiments, the method200can include one or more operations depicted inFIG.4.

FIG.5A-5Iillustrates one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

Referring toFIG.5A, a substrate110may be provided. A dielectric layer112may be formed on or over the substrate110. A dielectric layer114may be formed on or over the dielectric layer112. Each of the dielectric layer112and the dielectric layer114may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), or other suitable processes. In some embodiments, the material of the dielectric layer112may be different from that of the dielectric layer114.

Referring toFIG.5B, a dielectric layer116may be formed on or over the dielectric layer114. A dielectric layer118may be formed on or over the dielectric layer116. Each of the dielectric layer116and the dielectric layer118may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, low-pressure chemical vapor deposition, or other suitable processes. In some embodiments, the material of the dielectric layer116may be different from that of the dielectric layer118.

Referring toFIG.5C, a mask120may be formed on or over the dielectric layer118. In some embodiments, the mask120may include a photoresist. The mask120may be formed by, for example, a photolithography process. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). In some embodiments, the mask120may define a plurality of openings. A portion1181of the dielectric layer118may be exposed by the mask120. A portion1161of the dielectric layer116may be exposed by the mask120.

Referring toFIG.5D, an etching process P1may be performed. The etching process P1may include dry etching, wet etching, or other suitable techniques. In some embodiments, the portion1181of the dielectric layer118may be removed. In some embodiments, the portion1161of the dielectric layer116may be removed. In some embodiments, a plurality of openings122may be formed. The upper surface of the dielectric layer114may be exposed to the openings122. In some embodiments, a portion1162of the dielectric layer116may be exposed to the openings122.

Referring toFIG.5E, an etching process P2may be performed. The etching process P2may have a selectivity with respect to the dielectric layer116and the dielectric layer118. The portion1162of the dielectric layer116may be removed. A plurality of openings124may be formed. The opening124may be connected to the opening122. In some embodiments, a surface116s1of the dielectric layer116may be recessed from the surface118s1of the dielectric layer118. In some embodiments, a surface118s2of the dielectric layer118may be exposed to the opening124. A surface118s3of the dielectric layer118may be exposed.

Referring toFIG.5F, a material layer126′ may be formed. The material layer126′ may include a semiconductor material or a conductive material. In some embodiments, the material layer126′ may be formed on the surface118s1of the dielectric layer118. In some embodiments, the material layer126′ may be formed on the surface118s2of the dielectric layer118. In some embodiments, the material layer126′ may be formed on the surface118s3of the dielectric layer118. In some embodiments, the material layer126′ may be formed on the surface116s1of the dielectric layer116. In some embodiments, the material layer126′ may be formed on the upper surface of the dielectric layer114. In some embodiments, the material layer126′ may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or other suitable processes.

Referring toFIG.5G, a portion of the material layer126′ may be removed to form a layer126. In some embodiments, the material layer126′ on the surface118s3of the dielectric layer118may be removed. In some embodiments, the material layer126′ on the surface118s2of the dielectric layer118may be removed. In some embodiments, the material layer126′ on the surface118s1of the dielectric layer118may be removed. In some embodiments, the material layer126′ on the upper surface of the dielectric layer114may be removed. In some embodiments, the layer126may remain on the surface116s1of the dielectric layer116. The material layer126′ may be removed by an etching process.

Referring toFIG.5H, a layer128may be formed on the layer126. In some embodiments, the layer128may be selectively formed on the surface126s1of the layer126. As a result, an interconnection structure125, including the layer126and the layer128, may be produced.

Referring toFIG.5I, a dielectric layer130may be formed on the dielectric layer118. In some embodiments, an air gap132may be formed. The dielectric layer130may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, flowable chemical vapor deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or other suitable processes. An air gap132may be formed. The air gap132may be surrounded by the dielectric layer130, the layer128, and the dielectric layer114. As a result, a semiconductor device, such as the semiconductor device as shown inFIG.1, may be produced.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an interconnection structure, a first isolation feature, and a second isolation feature. The interconnection structure has a first lateral surface and a second lateral surface. The first isolation feature is disposed on the first lateral surface of the interconnection structure. The second isolation feature is disposed on the second lateral surface of the interconnection structure. The first isolation feature is different from the second isolation feature.

Another aspect of the present disclosure provides another a first dielectric layer, a first interconnection structure, and a second interconnection structure. The first dielectric layer is disposed over the substrate. The first interconnection structure is disposed over the first dielectric layer. The second interconnection structure is disposed over the first dielectric layer. The first interconnection structure is spaced apart from the second interconnection structure by an air gap.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The method includes: providing a substrate; forming a first dielectric layer over the substrate; forming a second dielectric layer over the first dielectric layer; patterning the first dielectric layer and the second dielectric layer to form an opening; forming an interconnection structure within the opening; and forming a third dielectric layer to form an air gap surrounded by the interconnection structure and the third dielectric layer.

The embodiments of the present disclosure a semiconductor device with a composite isolation feature around an interconnection structure. In this embodiment, the interconnection structure is made of at least two different materials. The interconnection structure may be proximal to two mediums with different dielectric constants. Such an asymmetry structure may be applied in semiconductor devices, such as a memory device, to control electrical properties.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.