Patent ID: 12250019

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Use of the term “approximately,” “near,” “about”, and/or “substantially” should be understood to mean including close to a target (e.g., design, value, amount), such as within a margin of any suitable or contemplatable error (e.g., within 0.1% of a target, within 1% of a target, within 5% of a target, within 10% of a target, within 25% of a target, and so on).

This disclosure is directed to isolation circuitry and phase shifting in a transceiver within a phased array system of a wireless communication device (e.g., user equipment). The transceiver may include a transmitter and a receiver. In certain embodiments, the transmitter and the receiver may share the same antennas, which may reduce the size of the phased array system. The smaller phased array system may result in less space consumed on a printed circuit board (PCB) or integrated circuit (IC), as well as reduced design complexity and greater reciprocity of the phased array system. Reciprocity, as used herein, is defined as the conservation of voltage between the input and output of a node or port in the phased array system.

The transmitter and the receiver may also share the same phase shifters. Phase shifters may be passive or active microwave devices used to change the phase angle of a radio frequency (RF) signal. Phase shifters may be used for applications such as phase modulators, frequency up-converters, testing instruments, or phased array antennas within a phased array system. In order to use one set of antennas and one set of phase shifters for both the transmitter and the receiver, transmit/receive (T/R) switches may be implemented. The T/R switches may connect a common antenna or set of antennas to either the transmitter or receiver. In a transmit (TX) mode, the T/R switches may enable a TX path, allowing a transmission signal to be sent from a processor (e.g., a baseband processor) to the transmitter, while in a receive (RX) mode the T/R switches may enable an RX path, allowing a received signal to be sent from the receiver to the processor. While the T/R switches may enable the receiver and transmitter to share the antennas and phase shifters, they may also increase the overall insertion loss of the system, which may result in a lower signal quality (e.g., by increasing the noise figure (NF) of the system) and may negatively impact the linearity of the system.

As previously stated, phase shifters may be passive (e.g., consume no or negligible power) or active (e.g., consume power). Passive phase shifters may be advantageous due to their power saving attributes. In particular, a switch-based phase shifter (e.g., a phase shifter consisting of multiple phase shifting stages) may be advantageous due to its ability to provide large bandwidths and relatively low insertion loss. However, while insertion loss in the switch-based phase shifter is relatively low, the insertion loss may increase as additional stages are added to the phase shifter. For example, if a system requires a phase shift of 45 degrees, a phase shift of 90 degrees, and a phase shift of 180 degrees, each phase shifting stage may compound the amount of insertion loss. The increase in insertion loss due to the additional T/R switches and the increase in insertion loss experienced in each stage of the switch-based phase shifter may be reduced or minimized by implementing a circuit that combines the functionality of the phase shifter with the functionality of the T/R switch, thus reducing the number of T/R switches and phase shifter stages responsible for the increased insertion loss in the phased array transceiver circuitry.

Embodiments herein provide various apparatuses and techniques to reduce insertion loss while decreasing or minimizing the space consumed on an integrated circuit, PCB, and/or the device overall by integrating one or more phase shifters with one or more T/R switches in a phased array transceiver circuit. To do so, the embodiments disclosed herein include a transmitter and a receiver, each including one or more differential amplifiers (e.g., differential operational amplifiers) coupled to a first inductor, and a switching network coupled to a second inductor and one or more phase shifting circuitries. The differential amplifiers may be used in a multistage receiver, such as a multistage low-noise amplifier (LNA) and/or a multistage transmitter, such as a multistage power amplifier (PA) in an RF/millimeter wave (mmWave) circuit. A differential interface of the differential amplifier may enable the integration of a stage of the switch-based phase shifter (e.g., the 180 degree stage) with the differential ports of the LNA and PA, such that a single circuit may operate as the phase shifter and as the T/R switch. The T/R switch/phase shifter circuitry may include multiple sets of switches (e.g., a switching network). In a TX mode, the LNA may be deactivated or effectively removed from the circuit (e.g., all switches coupled to the LNA are open), while at least one set of switches coupled to the PA may be closed. One set of switches in the T/R switch/phase shifter circuitry coupled to the PA may be closed in order to produce a 0 degree phase shift in the signal transmitted by the PA, while another set of switches may be closed in order to produce a 180 degree phase shift in the signal transmitted by the PA. Likewise, in an RX mode, the PA may be deactivated or effectively removed from the circuit (e.g., all switches coupled to the PA are open), while at least one set of switches coupled to the LNA may be closed. One set of switches in the T/R switch/phase shifter circuitry coupled to the LNA may be closed in order to produce a 0 degree phase shift in the signal received by the LNA, while another set of switches may be closed in order to produce a 180 degree phase shift in the signal received by the LNA. This implementation may reduce the number of T/R switches and phase shifter stages in the phased array system, reducing the overall insertion loss experienced by the phased array system.

With the foregoing in mind,FIG.1is a block diagram of an electronic device10, according to embodiments of the present disclosure. The electronic device10may include, among other things, one or more processors12(collectively referred to herein as a single processor for convenience, which may be implemented in any suitable form of processing circuitry), memory14, nonvolatile storage16, a display18, input structures22, an input/output (I/O) interface24, a network interface26, and a power source29. The various functional blocks shown inFIG.1may include hardware elements (including circuitry), software elements (including machine-executable instructions) or a combination of both hardware and software elements (which may be referred to as logic). The processor12, memory14, the nonvolatile storage16, the display18, the input structures22, the input/output (I/O) interface24, the network interface26, and/or the power source29may each be communicatively coupled directly or indirectly (e.g., through or via another component, a communication bus, a network) to one another to transmit and/or receive data between one another. It should be noted thatFIG.1is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device10.

By way of example, the electronic device10may include any suitable computing device, including a desktop or notebook computer (e.g., in the form of a MacBook®, MacBook® Pro, MacBook Air®, iMac®, Mac® mini, or Mac Pro® available from Apple Inc. of Cupertino, California), a portable electronic or handheld electronic device such as a wireless electronic device or smartphone (e.g., in the form of a model of an iPhone® available from Apple Inc. of Cupertino, California), a tablet (e.g., in the form of a model of an iPad® available from Apple Inc. of Cupertino, California), a wearable electronic device (e.g., in the form of an Apple Watch® by Apple Inc. of Cupertino, California), and other similar devices. It should be noted that the processor12and other related items inFIG.1may be generally referred to herein as “data processing circuitry.” Such data processing circuitry may be embodied wholly or in part as software, hardware, or both. Furthermore, the processor12and other related items inFIG.1may be a single contained processing module or may be incorporated wholly or partially within any of the other elements within the electronic device10. The processor12may be implemented with any combination of general-purpose microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, dedicated hardware finite state machines, or any other suitable entities that may perform calculations or other manipulations of information. The processors12may include one or more application processors, one or more baseband processors, or both, and perform the various functions described herein.

In the electronic device10ofFIG.1, the processor12may be operably coupled with a memory14and a nonvolatile storage16to perform various algorithms. Such programs or instructions executed by the processor12may be stored in any suitable article of manufacture that includes one or more tangible, computer-readable media. The tangible, computer-readable media may include the memory14and/or the nonvolatile storage16, individually or collectively, to store the instructions or routines. The memory14and the nonvolatile storage16may include any suitable articles of manufacture for storing data and executable instructions, such as random-access memory, read-only memory, rewritable flash memory, hard drives, and optical discs. In addition, programs (e.g., an operating system) encoded on such a computer program product may also include instructions that may be executed by the processor12to enable the electronic device10to provide various functionalities.

In certain embodiments, the display18may facilitate users to view images generated on the electronic device10. In some embodiments, the display18may include a touch screen, which may facilitate user interaction with a user interface of the electronic device10. Furthermore, it should be appreciated that, in some embodiments, the display18may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and/or other display technologies.

The input structures22of the electronic device10may enable a user to interact with the electronic device10(e.g., pressing a button to increase or decrease a volume level). The I/O interface24may enable electronic device10to interface with various other electronic devices, as may the network interface26. In some embodiments, the I/O interface24may include an I/O port for a hardwired connection for charging and/or content manipulation using a standard connector and protocol, such as the Lightning connector provided by Apple Inc. of Cupertino, California, a universal serial bus (USB), or other similar connector and protocol. The network interface26may include, for example, one or more interfaces for a personal area network (PAN), such as an ultra-wideband (UWB) or a BLUETOOTH® network, for a local area network (LAN) or wireless local area network (WLAN), such as a network employing one of the IEEE 802.11x family of protocols (e.g., WI-FTC)), and/or for a wide area network (WAN), such as any standards related to the Third Generation Partnership Project (3GPP), including, for example, a 3rdgeneration (3G) cellular network, universal mobile telecommunication system (UMTS), 4thgeneration (4G) cellular network, long term evolution (LTE®) cellular network, long term evolution license assisted access (LTE-LAA) cellular network, 5thgeneration (5G) cellular network, and/or New Radio (NR) cellular network, a satellite network, and so on. In particular, the network interface26may include, for example, one or more interfaces for using a Release-15 cellular communication standard of the 5G specifications that include the millimeter wave (mmWave) frequency range (e.g., 24.25-300 gigahertz (GHz)) and/or any other cellular communication standard release (e.g., Release-16, Release-17, any future releases) that define and/or enable frequency ranges used for wireless communication. The network interface26of the electronic device10may allow communication over the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, and so forth).

The network interface26may also include one or more interfaces for, for example, broadband fixed wireless access networks (e.g., WIMAX®), mobile broadband Wireless networks (mobile WIMAX®), asynchronous digital subscriber lines (e.g., ADSL, VDSL), digital video broadcasting-terrestrial (DVB-T®) network and its extension DVB Handheld (DVB-H®) network, ultra-wideband (UWB) network, alternating current (AC) power lines, and so forth.

As illustrated, the network interface26may include a transceiver30. In some embodiments, all or portions of the transceiver30may be disposed within the processor12. The transceiver30may support transmission and receipt of various wireless signals via one or more antennas, and thus may include a transmitter and a receiver. The power source29of the electronic device10may include any suitable source of power, such as a rechargeable lithium polymer (Li-poly) battery and/or an alternating current (AC) power converter.

FIG.2is a functional diagram of the electronic device10ofFIG.1, according to embodiments of the present disclosure. As illustrated, the processor12, the memory14, the transceiver30, a transmitter52, a receiver54, and/or antennas55(illustrated as55A-55N, collectively referred to as an antenna55) may be communicatively coupled directly or indirectly (e.g., through or via another component, a communication bus, a network) to one another to transmit and/or receive data between one another.

The electronic device10may include the transmitter52and/or the receiver54that respectively enable transmission and reception of data between the electronic device10and an external device via, for example, a network (e.g., including base stations) or a direct connection. As illustrated, the transmitter52and the receiver54may be combined into the transceiver30. The electronic device10may also have one or more antennas55A-55N electrically coupled to the transceiver30. The antennas55A-55N may be configured in an omnidirectional or directional configuration, in a single-beam, dual-beam, or multi-beam arrangement, and so on. Each antenna55may be associated with a one or more beams and various configurations. In some embodiments, multiple antennas of the antennas55A-55N of an antenna group or module may be communicatively coupled a respective transceiver30and each emit radio frequency signals that may constructively and/or destructively combine to form a beam. The electronic device10may include multiple transmitters, multiple receivers, multiple transceivers, and/or multiple antennas as suitable for various communication standards. In some embodiments, the transmitter52and the receiver54may transmit and receive information via other wired or wireline systems or means.

As illustrated, the various components of the electronic device10may be coupled together by a bus system56. The bus system56may include a data bus, for example, as well as a power bus, a control signal bus, and a status signal bus, in addition to the data bus. The components of the electronic device10may be coupled together or accept or provide inputs to each other using some other mechanism.

FIG.3is a block diagram of the transceiver30(e.g., transceiver circuitry) of the electronic device10, according to embodiments of the present disclosure. As illustrated, the transceiver circuitry30includes isolation/phase-shifting circuitry58disposed between a transmitter (e.g., a transmit circuit52) and a receiver (e.g., a receive circuit54). The isolation/phase-shifting circuitry58is communicatively coupled to the transmitter52and the receiver54, and the transmitter52and the receiver54are coupled to one or more antennas55. The isolation/phase-shifting circuitry58blocks the signals from passing from the transmitter52through to the receiver54, and blocks the received signals from passing from the receiver54through to the transmitter52. The isolation/phase-shifting circuitry58may also shift phases of the signals, as will be described in further detail below.

FIG.4is a schematic diagram of the transmitter52(e.g., transmit circuitry), according to embodiments of the present disclosure. As illustrated, the transmitter52may receive outgoing data60in the form of a digital signal to be transmitted via the one or more antennas55. A digital-to-analog converter (DAC)62of the transmitter52may convert the digital signal to an analog signal, and a modulator64may combine the converted analog signal with a carrier signal to generate a radio wave. A power amplifier (PA)66receives the modulated signal from the modulator64. The power amplifier66may amplify the modulated signal to a suitable level to drive transmission of the signal via the one or more antennas55. A filter68(e.g., filter circuitry and/or software) of the transmitter52may then remove undesirable noise from the amplified signal to generate transmitted data70to be transmitted via the one or more antennas55. The filter68may include any suitable filter or filters to remove the undesirable noise from the amplified signal, such as a bandpass filter, a bandstop filter, a low pass filter, a high pass filter, and/or a decimation filter. Additionally, the transmitter52may include any suitable additional components not shown, or may not include certain of the illustrated components, such that the transmitter52may transmit the outgoing data60via the one or more antennas55. For example, the transmitter52may include a mixer and/or a digital up converter. As another example, the transmitter52may not include the filter68if the power amplifier66outputs the amplified signal in or approximately in a desired frequency range (such that filtering of the amplified signal may be unnecessary).

FIG.5is a schematic diagram of the receiver54(e.g., receive circuitry), according to embodiments of the present disclosure. As illustrated, the receiver54may receive received data80from the one or more antennas55in the form of an analog signal. A low noise amplifier (LNA)82may amplify the received analog signal to a suitable level for the receiver54to process. A filter84(e.g., filter circuitry and/or software) may remove undesired noise from the received signal, such as cross-channel interference. The filter84may also remove additional signals received by the one or more antennas55that are at frequencies other than the desired signal. The filter84may include any suitable filter or filters to remove the undesired noise or signals from the received signal, such as a bandpass filter, a bandstop filter, a low pass filter, a high pass filter, and/or a decimation filter. A demodulator86may remove a radio frequency envelope and/or extract a demodulated signal from the filtered signal for processing. An analog-to-digital converter (ADC)88may receive the demodulated analog signal and convert the signal to a digital signal of incoming data90to be further processed by the electronic device10. Additionally, the receiver54may include any suitable additional components not shown, or may not include certain of the illustrated components, such that the receiver54may receive the received data80via the one or more antennas55. For example, the receiver54may include a mixer and/or a digital down converter.

FIG.6is a schematic diagram of an example phased array system600wherein the receiver54and the transmitter52share antennas. In order to use one set of antennas and one set of phase shifters for both the transmitter and the receiver, T/R switches606may be implemented. The phased array system600may include transmit/receive (T/R) circuitry602, which may send signals to and receive signals from the antennas55. For example, in a receive mode, the T/R switch606A may receive a received signal from the antennas and pass the received signal to the LNA82(which may be representative of the receiver54as a whole). The received signal may pass, via the T/R switch606B, to a phase shifter612, which may adjust the phase of the received signal by a predetermined phase angle (e.g., 45 degrees, 90 degrees, 180 degrees, and so on). The received signal may then pass to a combiner/splitter614. The T/R switch606C may then enable the received data80to pass to an intermediate frequency (IF) port616. As may be appreciated, the T/R switches606A,606B, and606C, when flipped to a transmit mode, may enable a transmit signal to propagate from the IF port616through the PA66and to the antennas55. While two T/R circuitries602are shown, it should be noted that the phased array system600may have any suitable number of T/R circuitries602(e.g., one, two, ten, one hundred, or several hundred).

As illustrated inFIG.6, for the LNA82and the PA66to share the same antennas55, the example phased array system600may implement three T/R switches606A,606B, and606C. The T/R switches606may each contribute to an increase in the overall insertion loss of the phased array system600. Increased insertion loss may result in a lower signal quality (e.g., by increasing the noise figure (NF) of the system) and may negatively impact the linearity of the system. By reducing the number of T/R switches606, the insertion loss may be decreased.

FIG.7is a schematic diagram of a switch-based phase shifter700, according to an embodiment of the present disclosure. Phase shifters (e.g.,612) may be passive (e.g., consume no or negligible power) or active (consume power). Passive phase shifters such as the switch-based phase shifter700may be advantageous due to their power saving attributes. In particular, the switch-based phase shifter700having multiple phase shift stages (e.g.,702,704, and706) may be advantageous due to its ability to provide large bandwidths and relatively low insertion loss. However, while insertion loss in any one stage of the switch-based phase shifter700is relatively low, the insertion loss may increase as additional stages are added. For example, if the switch-based phase shifter700includes a 45 degree phase shift stage702, a 90 degree phase shift stage704, and a 180 degree phase shift stage706, each stage may cause some amount of insertion loss, and the overall insertion loss of the switch-based phase shifter700may be compounded. For example, the insertion loss due to a phase shift of 135 degrees (e.g., provided by activating the 45 degree phase shift stage702and the 90 degree phase shift stage704) may have a smaller corresponding insertion loss than a phase shift of315(e.g., provided by activating the 45 degree phase shift stage702, the 90 degree phase shift stage704, and the 180 degree phase shift stage180). The increase in insertion loss due to the additional T/R switches606and the increase in insertion loss experienced in each stage of the switch-based phase shifter may be reduced or minimized by implementing a circuit that integrates one or more stages of the switch-based phase shifter700with the functionality of the T/R switch606, thus reducing the number of T/R switches606and removing one or more stages of the switch-based phase shifter700that may be responsible for the increased insertion loss in the phased array system600.

FIG.8Ais a schematic diagram of transmit circuitry800(e.g., of the transmitter52) having a multistage PA801and a switching network802arranged to shift the phase of a transmit signal by 0 degrees, according to an embodiment of the present disclosure. The multistage PA801may be a differential power amplifier (e.g., a differential operational amplifier) including multiple PAs66and an transformer810; the transformer810including an inductor812A and an inductor812B. The switching network802includes switches804A and804B and shunt switches806A and806B. The switch804A and the shunt switch806A may together make a set808A, while the switch804B and the shunt switch806B may together make a set808B. When the set808A is activated (e.g., the switch804A and the shunt switch806A are closed) and the set808B is deactivated (e.g., the switch804B and the shunt switch806B are open), the activated switching network802may carry a transmit signal from the processor12to a differential port814A of the multistage PA801by coupling the processor12to a first end816A of the inductor812B of the transformer810, which inductively transfers the transmit signal from the inductor812B to the inductor812A coupled to the differential port814A of the multistage PA801. The activated shunt switch806A may short the second end816B of the inductor812B (e.g., transforming the differential signal to a single-ended signal as the second end816B may be grounded). By enabling the processor12to couple to the differential port814A of the multistage PA801, the switching network802may maintain a phase of a transmit signal going to the multistage PA801, or shift the phase of the transmit signal going to the multistage PA801by 0 degrees.

FIG.8Bis a schematic diagram of the transmit circuitry800having a multistage PA801and a switching network802arranged to produce a 180 degree phase shift, according to an embodiment of the present disclosure. When the set808B of the switching network802is activated (e.g., the switch804B and the shunt switch806B are closed) and the set808A is deactivated (e.g., the switch804A and the shunt switch806A are open) the processor12may couple to a differential port814B of the multistage PA801by coupling to the second end816B of the inductor812B. Coupling the processor12to the differential port814B of the multistage PA801may cause the transmit signal to swap polarity, inverting the transmit signal sent from the multistage PA801causing the phase of the transmit signal to be offset by 180 degrees (e.g., resulting in a 180 degree phase shift inFIG.8A) in the signal going to the multistage PA801. The activated shunt switch806B may short the first end816A of the inductor812B (e.g., transforming the differential signal to a single-ended signal as the first end816A may be grounded).

By using the switching network802to shift the phase of the transmit signal, a phase shifter (e.g., the 180 degree phase shift stage706ofFIG.7) may be removed from the switch-based phase shifter700(as evidenced in the switching network802), thus reducing the insertion loss in a phased array system (e.g.,600). In the following embodiments, it will be discussed how switching networks similar to the switching network802may be used to integrate a stage (e.g., the 180 degree phase shift stage706) of the switch-based phase shifter700and a T/R switch606. Additionally, whileFIGS.8A and8Billustrate the switching network802producing different phase shifts for the multistage PA801, it should be noted that a switching network similar to the switching network802may be implemented to produce one or more phase shifts in a signal coming from the LNA82(e.g., a multistage LNA).

FIG.9is a flowchart of a method900for applying a phase shift using the transmit circuitry800, according to an embodiment of the present disclosure. Any suitable device (e.g., a controller) that may control components of the electronic device10, such as the processor12, may perform the method900. In some embodiments, the method900may be implemented by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as the memory14or storage16, using the processor12. For example, the method900may be performed at least in part by one or more software components, such as an operating system of the electronic device10, one or more software applications of the electronic device10, and the like. While the method900is described using steps in a specific sequence, it should be understood that the present disclosure contemplates that the described steps may be performed in different sequences than the sequence illustrated, and certain described steps may be skipped or not performed altogether.

In process block902the processor12determines that a signal is being sent from the processor12to transmit circuitry (e.g., including the PA66) of the transceiver30or determines that a signal is being sent from receive circuitry (e.g., including the LNA82) of the transceiver30to the processor12. In decision block904, the processor12may determine whether a phase shift of greater than 180 degrees is desired. If the processor12determines that a phase shift of greater than 180 degrees is desired, then, in process block906, the processor12activates a first set of switches (e.g., the set808B) that causes the transceiver30to apply a 180 degree phase shift to a transmitted or received signal. For example, if the processor12determines that a 225 degree phase shift is desired for a transmit signal, then the processor12may activate a 45 degree phase shifter and the set808B (e.g., that couples the processor12to the first end816A of the inductor812B), combining the 45 degree phase shift with the 180 degree phase shift to shift the phase of the transmit signal by 225 degrees.

However, if the processor12determines that a phase shift greater than 180 degrees is not desired, then, in process block908, the processor12activates a second set of switches (e.g., the set808B) that cause the transceiver to apply a 0 degree phase shift to a transmitted or received signal. For example, if the processor12determines that a 135 degree phase shift is desired, then the processor12may activate the 45 degree phase shifter, a 90 degree phase shifter, and the set808A, producing a 135 degree phase shift. In this manner, the method900enables the processor12to apply a phase shift to an input (e.g., transmission) signal. While the method900ofFIG.9describes shifting the phase of the transmit signal going to the multi-stage PA801as illustrated inFIG.8AandFIG.8B, the method900may also apply to a received signal coming from an LNA (e.g.,82), as will be discussed in greater detail below.

FIG.10Ais a schematic diagram of transceiver circuitry1000having switches of the isolation/phase-shifting circuitry58configured so as to shift the phase of a transmit signal, according to an embodiment of the present disclosure. The transceiver circuitry1000includes the PA66(which is representative of the transmitter52), the LNA82(which is representative of the receiver54), and the isolation/phase-shifting circuitry58, which further includes the switching network802and a switching network1002. The switching network802may, as illustrated inFIG.8AandFIG.8B, shift the phase of a signal going to the PA66by 0 degrees (e.g., by activating the switch804A and the shunt switch806A and deactivating the switch804B and the shunt switch806B) or 180 degrees (e.g., by activating the switch804B and the shunt switch806B and deactivating the switch804A and the shunt switch806A). The switching network1002may shift the phase of a signal coming from the LNA82by 180 degrees or 0 degrees. The switching network1002includes switches1004A and1004B and shunt switches1006A and1006B. As illustrated, the switching network802is activated and the switching network1002is deactivated (e.g., the switches1004A and1004B and the shunt switches1006A and1006B are open), thus the transceiver circuitry1000is in a transmit (TX) mode. As the switch804A and the shunt switch806A are activated and the switch804B and the shunt switch806B are deactivated, the isolation/phase-shifting circuitry58may couple the processor12to the first end816A of the inductor812B, which may inductively transfer the transmit signal from the inductor812B to the inductor812A coupled to the differential port814A of the PA66, maintaining the phase of the transmit signal or shifting the phase of the transmit signal by 0 degrees.

The isolation/phase-shifting circuitry58and the switching network1002may enable the processor12to couple to a differential port1014A or a differential port1014B of the LNA82by coupling the processor to a first end1016A or a second end1016B an inductor1012A of the transformer1010. When the switch1004A and the shunt switch1006A are activated (e.g., closed) and the switch1004B and the shunt switch1006B are deactivated (e.g., open) the processor12may couple to the differential port1014A of the LNA82, causing a phase shift (e.g., a 0 degree phase shift) in the signal coming from the LNA82Similarly, when the switch1004B and the shunt switch1006B are activated (e.g., closed) and the switch1004A and the shunt switch1006A are deactivated (e.g., open) the processor12may couple to a differential port1014B of the LNA82and decouple from the differential port1014A causing a phase shift (e.g., a 180 degree phase shift) in the signal coming from the LNA82. The transceiver circuitry1000also includes a 45 degree phase shifter1020and a 90 degree phase shifter1018. While only the 45 degree phase shifter1020and the 90 degree phase shifter1018are shown in the transceiver circuitry1000, it should be noted that the transceiver circuitry1000may include fewer or more phase shifters that may apply any appropriate phase shift (e.g., a 30 degree phase shift, a 15 degree phase shift, and so on).

As discussed, the transceiver circuitry1000inFIG.10Ais in a TX mode.FIG.10Bis a schematic diagram of the transceiver circuitry1000having the switches of the isolation/phase-shifting circuitry58configured so as to apply a phase shift to a received signal, according to an embodiment of the present disclosure. As may be observed, as the transceiver circuitry1000is in an RX mode. The switching network802is deactivated (e.g., all switches804and shunt switches806in the switching network802are open) and the switching network1002is activated (e.g., the switch1004B and the shunt switch1006B are closed). Activating the switch1004B and the shunt switch1006B and deactivating the switch1004A and the shunt switch1006A may cause the switching network1002to couple the processor12to a second end1016B of the inductor1012B, which may inductively transfer the received signal from the inductor1012B to the inductor1012A coupled to the differential port1014B of the LNA82, shifting the phase of the received signal by 180 degrees. In other embodiments, the switch1004A and the shunt switch1006A may be activated and the switch1004B and the shunt switch1006B may be deactivated to couple the processor12to the first end1016A of the inductor1012B. The inductor1012B may inductively transfer the received signal from the inductor102B to the inductor1012A coupled to the differential port1014A of the LNA82, which may maintain the phase shift of the received signal or shift the phase of the received signal by 0 degrees.

FIG.11is a schematic diagram of transceiver circuitry1100utilizing single-ended transmission lines, according to an embodiment of the present disclosure. The single-ended transmission line1102couples the switching network802to the phase shifters1018and1020. The single-ended transmission line1104connects the switching network1002to the phase shifters1018and1020. However, at certain frequencies (e.g., 30 gigahertz and higher), the single-ended transmission lines1102and1104may cause reactive energy (e.g., capacitive reactance) to accumulate at the deactivated switching network (e.g., the switching network802in the receive mode and the switching network1002in the transmit mode). For example, inFIG.11, the transceiver circuitry1100is in an RX mode, thus the switching network1002is activated (e.g., one or more switches1004and one or more shunt switches1006are closed) and the switching network802is deactivated (e.g., the switches804and the shunt switches806are open). If the signal coming from the LNA82has a frequency of 50 gigahertz, excess reactive energy (e.g., in particular, excess capacitive reactance) may build up at the switching network802; and the switching network1002may not be able to absorb the excess capacitive reactance. Embodiments that resolve or compensate for the excess capacitive reactance will be discussed below.

FIG.12is a Smith chart1200illustrating total impedance of the transceiver circuitry1100, according to an embodiment of the present disclosure. The Smith chart1200illustrates impedance1202present at a deactivated switching network (e.g.,802inFIG.11) due to various components in the transceiver circuitry1100(e.g., the activated switching network1002, the single-ended transmission lines1102and1104, and so on). The top hemisphere1204of the Smith chart1200represents the inductive reactance of one or more component (e.g., the single-ended transmission lines1102and1104) in the transceiver circuitry1100. The bottom hemisphere1206represents the capacitive reactance of the one or more components in the transceiver circuitry1100. The impedance1202indicates a significant buildup of capacitive reactance at the switching network802that may not be absorbed or dissipated by the rest of the transceiver circuitry1100.

FIG.13is a schematic diagram of transceiver circuitry1300utilizing differential transmission lines and an additional inductor, according to an embodiment of the present disclosure. To resolve the excess capacitive reactance issue for signals at the certain frequencies discussed above, the switching network802may be moved from an input port1308or near the input port1308of the PA66and repositioned between a differential transmission line1302and an inductor1306. Similarly, the switching network1002may be moved from an input port1310or near the input port1310of the LNA82and repositioned between a differential transmission line1304and the inductor1306. The shunt switches806A and806B may be 100 micrometers to 250 micrometers from an input port1308and/or the inductor812B of the PA66and the shunt switches1006A and1006B may be 100 micrometers to 250 micrometers from an input port1310and/or the inductor1012B of the LNA82. By removing the single-ended transmission lines1102and implementing the differential transmission lines1302and1304in the transceiver circuitry1300and taking advantage of the differential nature of the differential transmission lines1302and1304, the capacitive reactance at the deactivated switching network (e.g.,802inFIG.13) may be reduced rather that combined. Additionally, the inductor1306may dissipate all or a portion of the remaining capacitive reactance. To sufficiently dissipate the remaining capacitive reactance, the inductor1306may have a range of 100 picohenries to 150 picohenries.

FIG.14is a Smith chart1400illustrating total impedance of the transceiver circuitry1300, according to an embodiment of the present disclosure. The Smith chart1400illustrates an impedance1402within the transceiver circuitry1300due to components such as the differential transmission lines1302and1304, the switching networks802and1002, and the inductor1306. As may be observed, the capacitive reactance of the impedance of the transceiver circuitry1300(e.g., the capacitive reactance at the differential port of the PA66) has been reduced (e.g., is closer to a system impedance1404).

FIG.15is a schematic diagram of transceiver circuitry1500, wherein the transceiver circuitry1500is an alternative embodiment of the transceiver circuitry1300, according to an embodiment of the present disclosure. The transceiver circuitry1500may be realized by moving the shunt switches806A and806B from the positions seen inFIG.13(e.g., 100 to 250 micrometers from the input port1308and/or the inductor812B of the PA66) and repositioning them at the input port1308or near the input port1308of the PA66, such that the differential transmission lines1302are disposed between the shunt switches806A and806B and the switches804A and804B Similarly, the shunt switches1006A and1006B may be moved from the positions seen inFIG.13(e.g., 100 to 250 micrometers from the input port1310and/or the inductor1012B of the LNA82) and repositioned at the input port1310or near the input port1310of the LNA82, such that the differential transmission lines1304are disposed between the shunt switches1006A and1006B and the switches1004A and1004B. By repositioning the shunt switches806A,806B,1006A, and1006B, the transceiver circuitry1500may further reduce the excess capacitive reactance accumulated at the deactivated switching network for signals at the certain frequencies (e.g., as seen inFIG.11). Due to the decreased capacitive reactance, the transceiver circuitry1500may include an inductor1502that may be smaller than the inductor1306. For example, while the inductor1306may have a range of 100 picohenries to 150 picohenries, the inductor1502may have a range of 20 picohenries to 30 picohenries. In one or more other embodiments, the inductor1502may be removed altogether. The arrangement of the transceiver circuitry1500may also further reduce the insertion loss experienced by the phased array system (e.g., by one-half dB).

FIG.16is a Smith chart1600illustrating the total impedance of the transceiver circuitry1500, according to an embodiment of the present disclosure. As may be observed, the impedance1602of the transceiver circuitry1500is less than that of the impedance1402of the transceiver circuitry1300. Particularly, it may be observed that the capacitive reactance of the impedance1602is less than the capacitive reactance component of the impedance1402. As previously stated, this smaller capacitive reactance component of the impedance1602may enable the transceiver circuitry1500to absorb the capacitive reactance at the deactivated switching network (e.g., the switching network802inFIG.15) with the smaller inductor1502or with no inductor.

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The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . ” or “step for [perform]ing [a function] . . . ,” it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).