Patent ID: 12236879

DETAILED DESCRIPTION

The attached drawings for illustrating exemplary embodiments of the inventive concept are referred to in order to gain a sufficient understanding of the inventive concept, the merits thereof, and the objectives accomplished by the implementation of the inventive concept. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein; rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

Hereinafter, the present invention will be described in detail by explaining exemplary embodiments of the inventive concept with reference to the attached drawings. Like reference numerals in the drawings denote like elements, and their descriptions may not be provided. Sizes of components in the drawings may be exaggerated for convenience of explanation. In other words, because sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following exemplary embodiments are not limited thereto.

FIG.1is a block diagram illustrating a display device10according to some embodiments of the present inventive concept.

Referring toFIG.1, a display device10may include a display panel100and a display panel driver. The display panel driver may include a driving controller200, a gate driver300, a gamma reference voltage generator400, and a data driver500.

For example, the driving controller200and the data driver500may be integrally formed. For example, the driving controller200, the gamma reference voltage generator400, and the data driver500may be integrally formed. For example, the driving controller200, the gate driver300, the gamma reference voltage generator400, and the data driver500may be integrally formed. A driving module including at least the driving controller200and the data driver500which are integrally formed may be referred to as a timing controller embedded data driver (TED).

The display panel100may include a display region displaying an image and a peripheral region disposed adjacent to the display region.

For example, the display panel100may be an organic light emitting diode display panel including organic light emitting diodes. For example, the display panel100may be a quantum-dot organic light emitting diode display panel including organic light emitting diodes and quantum-dot color filters. For example, the display panel100may be a quantum-dot nano light emitting diode display panel including nano light emitting diodes and quantum-dot color filters.

The display panel100may include gate lines GL, data lines DL, and active pixels AP and dummy pixels DP electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2crossing the first direction D1.

The driving controller200may receive input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may further include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

The driving controller200may generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

The driving controller200may generate the first control signal CONT1for controlling an operation of the gate driver300based on the input control signal CONT, and output the first control signal CONT1to the gate driver300. The first control signal CONT1may include a vertical start signal and a gate clock signal.

The driving controller200may generate the second control signal CONT2for controlling an operation of the data driver500based on the input control signal CONT, and output the second control signal CONT2to the data driver500. The second control signal CONT2may include a horizontal start signal and a load signal.

The driving controller200may generate the data signal DATA based on the input image data IMG. The driving controller200may output the data signal DATA to the data driver500.

The driving controller200may generate the third control signal CONT3for controlling an operation of the gamma reference voltage generator400based on the input control signal CONT, and output the third control signal CONT3to the gamma reference voltage generator400.

The gate driver300may generate gate signals for driving the gate lines GL in response to the first control signal CONT1received from the driving controller200. The gate driver300may output the gate signals to the gate lines GL.

In some embodiments, the gate driver300is integrated on the peripheral region of the display panel100.

The gamma reference voltage generator400may generate a gamma reference voltage VGREF in response to the third control signal CONT3received from the driving controller200. The gamma reference voltage generator400may provide the gamma reference voltage VGREF to the data driver500. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

In some embodiments, the gamma reference voltage generator400is disposed in the drive controller200or the data driver500.

The data driver500may receive the second control signal CONT2and the data signal DATA from the driving controller200and receive the gamma reference voltage VGREF from the gamma reference voltage generator400. The data driver500may convert the data signal DATA into a data voltage in analog form. The data driver500may output the data voltage to the data line DL.

FIG.2Ais a block diagram illustrating an example of a pixel column included in a display device10of the related art, which does not include a dummy pixel, andFIG.2Bis a block diagram illustrating an example of a pixel column included in a display device10of the related art, which does include a dummy pixel.

Referring toFIGS.1and2, the display device10of the related art may include a display panel100. The display panel100may include active pixels AP in first to N-th pixel rows. The display panel100may include dummy pixels DP[N+1] and DP[N+2] arranged in pixel rows from the N+1-th pixel row (i.e., lower side of the active pixels AP). The dummy pixels DP[N+1] and DP[N+2] may improve (e.g., increase) a luminance difference between the active pixels AP adjacent to the dummy pixels DP[N+1] and DP[N+2].

For example, as illustrated inFIG.2A, a pixel column of the display device10of the related art may not include dummy pixels. The pixel column of the display device10of the related art may include an N−3-th active pixel AP[N−3], an N−2-th active pixel AP[N−2], an N−1-th active pixel AP[N−1], and an N-th active pixel AP[N]. A data voltage VDATA may be concurrently (e.g., simultaneously) applied to one active pixel AP through a data line DL, and in some cases, may be concurrently (e.g., simultaneously) applied to two or more active pixels AP. In addition, when the data voltage VDATA is concurrently (e.g., simultaneously) applied to two or more active pixels AP, the data voltage VDATA may be applied to one active pixel AP, or may be applied to a next second active pixel AP while skipping a next first active pixel AP. For example, the data voltage VDATA may be applied to the N−3-th active pixel AP[N−3] and the N−1-th active pixel AP[N−1]. Then, the data voltage VDATA may be applied to the N−2-th active pixel AP[N−2] and the N-th active pixel AP[N]. Unlike the previous case, the data voltage VDATA may be applied only to the N−1-th active pixel AP[N−1]. Next, the data voltage VDATA may be applied only to the N-th active pixel AP[N]. Therefore, when the data voltage VDATA is applied only to the N−1-th active pixel AP[N−1] or the N-th active pixel AP[N], a luminance difference may occur between the N−1-th active pixel AP[N−1] and the N-th active pixel AP[N].

To solve this problem, as illustrated inFIG.2B, the pixel column of the display device10of the related art may include the active pixels AP in the first to N-th pixel rows, and may include the dummy pixels DP[N+1] and DP[N+2] arranged in a plurality of pixel rows from the N+1-th pixel row (i.e., the lower side of the active pixels AP). For example, the data voltage VDATA may be concurrently (e.g., simultaneously) applied to two or more active pixels AP, and the dummy pixels DP may include an N+1-th dummy pixel DP[N+2] and an N+2-th dummy pixel DP[N+1]. Therefore, after the data voltage VDATA is applied to the N−2-th active pixel AP[N−2] and the N-th active pixel AP[N], the data voltage VDATA may be applied to the N−1-th active pixel AP[N−1] and the N+1-th dummy pixel DP[N+1]. Next, the data voltage VDATA may be applied to the N-th active pixel AP[N] and the N+2-th dummy pixel DP[N+2]. As described above, the pixel column of the display device10of the related art includes the dummy pixels DP[N+1] and DP[N+2], so that the luminance difference between the active pixels AP[N−1] and AP[N] arranged adjacent to the dummy pixels DP[N+1] and DP[N+2] may be improved.

However, as the number of the active pixels AP to which the data voltage VDATA is concurrently (e.g., simultaneously) applied in the pixel column increases, the number of the dummy pixels DP utilized to improve the luminance difference between the active pixels AP may increase. Thus, in the related art, a dead space in which the dummy pixels DP are arranged may increase, and power consumption of the display panel100may increase.

FIG.3Ais a block diagram illustrating an example of a pixel column included in the display device10ofFIG.1, according to some embodiments of the present inventive concept.FIG.3Bis a circuit diagram illustrating an example of the dummy pixel DP[N+1] included in the pixel column ofFIG.3A, according to some embodiments of the present inventive concept.FIG.3Cis a timing diagram illustrating an operation of the dummy pixel DP[N+1] ofFIG.3B, according to some embodiments of the present inventive concept.FIGS.3D and3Eare circuit diagrams illustrating an operation of the dummy pixel DP[N+1] ofFIG.3C, according to some embodiments of the present inventive concept.FIG.3Fis a circuit diagram illustrating an example of the dummy pixel DP[N+1] ofFIG.3A, according to some embodiments of the present inventive concept.

Referring toFIGS.1to3F, as illustrated inFIG.3A, the display panel100according to some embodiments of the present inventive concept includes the active pixels AP in the first to N-th pixel rows. The display panel100may include the dummy pixels DP[N+1] in the N+1-th pixel row. That is, in one pixel column, the display panel100may include the first to N-th active pixels AP[1]-AP[N] and one dummy pixel DP[N+1] (where N is a natural number of 4 or more).

As illustrated inFIG.3B, the dummy pixel DP[N+1] may include a dummy driving transistor T1, a plurality of dummy compensation transistors T3-1and T3-2, a dummy initialization transistor T4, and a dummy storage capacitor CST. The dummy compensation transistors may include a dummy first compensation transistor T3-1and a dummy second compensation transistor T3-2. In some embodiments, as illustrated inFIG.3F, the dummy pixel DP[N+1] further includes a dummy write transistor T2configured to connect the data line DL to the dummy driving transistor T1, and the dummy driving transistor T1may be turned on at all times.

The dummy driving transistor T1may include a gate electrode connected to a first node N1, a first electrode connected to the data line DL which transmits the data voltage VDATA, and a second electrode connected to a second node N2.

The dummy compensation transistors may be connected in parallel to each other between the first node N1and the second node N2. The dummy first compensation transistor T3-1may include a gate electrode configured to receive an N+1-th write gate signal GW[N+1] (e.g., a write gate signal), a first electrode connected to the second node N2, and a second electrode connected to the first node N1. The dummy second compensation transistor T3-2may include a gate electrode configured to receive an N+2-th write gate signal GW[N+2] (e.g., a first later write gate signal) applied after the N+1-th write gate signal GW[N+1], a first electrode connected to the second node N2, and a second electrode connected to the first node N1. As illustrated inFIG.3C, the N+1-th write gate signal GW[N+1] and the N+2-th write gate signal GW[N+2] may have two active pulses. The active pulses of the N+1-th write gate signal GW[N+1] may not overlap the active pulses of the N+2-th write gate signal GW[N+2]. When each of the dummy first compensation transistor T3-1and the dummy second compensation transistor T3-2is turned on, the data voltage VDATA may be applied to the first node N1through each of the dummy first compensation transistor T3-1and the dummy second compensation transistor T3-2.

The dummy initialization transistor T4may include a gate electrode configured to receive an initialization gate signal CLA[N+1], a first electrode configured to receive an initialization voltage VINT, and a second electrode connected to the first node N1. When the dummy initialization transistor T4is turned on, the initialization voltage VINT may be applied to the first node N1. Therefore, the voltage of the first node N1may be initialized to the initialization voltage VINT.

The dummy write transistor T2may include a gate electrode configured to receive a low gate voltage VGL, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the dummy driving transistor T1. Therefore, the dummy write transistor T2may be turned on at all times, and may transmit the data voltage VDATA to the first electrode of the dummy driving transistor T1.

In some embodiments, each of the dummy driving transistor T1, the dummy write transistor T2, the dummy first compensation transistor T3-1, the dummy second compensation transistor T3-2, and the dummy initialization transistor T4is a P-type transistor (e.g., a PMOS transistor). In some other embodiments, each of the dummy driving transistor T1, the dummy write transistor T2, the dummy first compensation transistor T3-1, the dummy second compensation transistor T3-2, and the dummy initialization transistor T4is an N-type transistor (e.g., an NMOS transistor).

In some embodiments, the dummy first compensation transistor T3-1has a dual gate structure including two gate electrodes. In some embodiments, the dummy second compensation transistor T3-2has a dual gate structure including two gate electrodes. In some embodiments, the dummy initialization transistor T4has a dual gate structure including two gate electrodes.

The dummy storage capacitor CST may include a first electrode configured to receive a first supply voltage ELVDD and a second electrode connected to the first node N1. The dummy storage capacitor CST may store a voltage of the first node N1.

To improve (e.g., increase) the luminance difference between the active pixels AP (i.e., the N−1-th active pixel AP[N−1] and the N-th active pixel AP[N]) arranged adjacent to the dummy pixel DP[N+1], the dummy pixel DP[N+1] may include the dummy compensation transistors T3-1and T3-2.

To improve (e.g., increase) the luminance difference between the active pixels AP (i.e., the N−1-th active pixel AP[N−1] and the N-th active pixel AP[N]) arranged adjacent to the dummy pixel DP[N+1], the dummy compensation transistors T3-1and T3-2may be alternately turned on.

In a first period P1, the N−1-th write gate signal GW[N−1] and the N+1-th write gate signal GW[N+1] may have the active pulses. In the first period P1, when the dummy pixel DP[N+1] receives the data voltage VDATA, the dummy first compensation transistor T3-1is turned on, and the dummy second compensation transistor T3-2is turned off, the N−1-th active pixel AP[N−1] may receive the data voltage VDATA. The data voltage VDATA may be applied to the first node N1through the dummy first compensation transistor T3-1. Therefore, the dummy storage capacitor CST may store the voltage of the first node N1.

In a second period P2, the N-th write gate signal GW[N] and the N+2-th write gate signal GW[N+2] may have the active pulses. In the second period P2, when the dummy pixel DP[N+1] receives the data voltage VDATA, the dummy second compensation transistor T3-2is turned on, and the dummy first compensation transistor T3-1is turned off, the N-th active pixel AP[N] may receive the data voltage VDATA. The data voltage VDATA may be applied to the first node N1through the dummy second compensation transistor T3-2. Therefore, the dummy storage capacitor CST may store the voltage of the first node N1.

Active pulses of the initialization gate signal CLA[N+1] may not overlap (e.g., overlap in time) the active pulses of the write gate signal. Therefore, an operation of initializing the voltage of the first node N1to the initialization voltage VINT may not overlap an operation of applying the data voltage VDATA to the first node N1in time.

As described above, the dummy pixel DP[N+1] may include the dummy compensation transistors T3-1and T3-2based on the number of the active pulses of the write gate signal. The dummy compensation transistors T3-1and T3-2may be alternately turned on, the data voltage VDATA may be applied to the first node N1through the dummy compensation transistors T3-1and T3-2, and the dummy storage capacitor CST may store the voltage of the first node N1.

In summary, the display panel100and the display device10, according to some embodiments, includes the active pixels AP and the dummy pixel DP[N+1] arranged adjacent to the active pixels AP in the same pixel column. The dummy pixel DP[N+1] may include the dummy compensation transistors T3-1and T3-2. Accordingly, although the display panel100, according to some embodiment, includes only one dummy pixel row, the luminance difference between the active pixels AP may be improved, the dead space in which the dummy pixel row is arranged may be reduced, and the power consumption of the display panel100may be reduced.

FIG.4Ais a block diagram illustrating an example of a pixel column included in the display device10ofFIG.1, according to some embodiments of the present inventive concept.FIG.4Bis a circuit diagram illustrating an example of the dummy pixel DP[N+1] included in the pixel column ofFIG.4A, according to some embodiments of the present inventive concept.FIG.4Cis a timing diagram illustrating an operation of the dummy pixel DP[N+1] ofFIG.4B, according to some embodiments of the present inventive concept.FIGS.4D to4Gare circuit diagrams illustrating an operation of the dummy pixel DP[N+1] ofFIG.4C, according to some embodiments of the present inventive concept.FIG.4His a circuit diagram illustrating an example of the dummy pixel DP[N+1] ofFIG.4A, according to some embodiments of the present inventive concept.

Referring toFIGS.1to4H, the dummy pixel DP[N+1] ofFIG.4Ais substantially the same as the dummy pixel DP[N+1] ofFIG.3A, except that the dummy pixel DP[N+1] ofFIG.4Afurther includes a dummy third compensation transistor T3-3and a dummy fourth compensation transistor T3-4, and the write gate signal has three active pulses. Therefore, overlapping descriptions of the same or corresponding components may be omitted.

As illustrated inFIG.4B, the dummy pixel DP[N+1] may include a dummy driving transistor T1, a plurality of dummy compensation transistors, a dummy initialization transistor T4, and a dummy storage capacitor CST. The dummy compensation transistors may include a dummy first compensation transistor T3-1, a dummy second compensation transistor T3-2, and a dummy third compensation transistor T3-3. In some embodiments, as illustrated inFIG.4H, the dummy pixel DP[N+1] further includes a dummy write transistor T2configured to connect the data line DL to the dummy driving transistor T1, and the dummy driving transistor T1may be turned on at all times.

The dummy compensation transistors may be connected in parallel between a first node N1and a second node N2. The dummy third compensation transistor T3-3may include a gate electrode configured to receive an N+3-th write gate signal GW[N+3] (e.g., a third later write gate signal) applied after the N+2-th write gate signal GW[N+2], a first electrode connected to the second node N2, and a second electrode connected to the first node N1. The dummy fourth compensation transistor T3-4may include a gate electrode configured to receive an N+4-th write gate signal GW[N+4] (e.g., a fourth later write gate signal) applied after the N+3-th write gate signal GW[N+3], a first electrode connected to the second node N2, and a second electrode connected to the first node N1. The N+2-th write gate signal GW[N+2], the N+3-th write gate signal GW[N+3], and the N+4-th write gate signal GW[N+4] may have three active pulses.

In some embodiments, each of the dummy third compensation transistor T3-3and the dummy fourth compensation transistor T3-4is a P-type transistor (e.g., a PMOS transistor). In some other embodiments, each of the dummy third compensation transistor T3-3and the dummy fourth compensation transistor T3-4is an N-type transistor (e.g., an NMOS transistor).

In some embodiments, the dummy third compensation transistor T3-3may have a dual gate structure including two gate electrodes. In some embodiments, the dummy fourth compensation transistor T3-4has a dual gate structure including two gate electrodes.

To improve a luminance difference between the active pixels AP (i.e., the N−3-th active pixel AP[N−3], the N−2-th active pixel AP[N−2], the N−1-th active pixel AP[N−1], and the N-th active pixel AP[N]) arranged adjacent to the dummy pixel DP[N+1], the dummy pixel DP[N+1] may include the dummy compensation transistors T3-1, T3-2, T3-3, and T3-4.

To improve (e.g., increase) the luminance difference between the active pixels AP (e.g., the N−3-th active pixel AP[N−3], the N−2-th active pixel AP[N−2], the N−1-th active pixel AP[N−1], and the N-th active pixel AP[N]) arranged adjacent to the dummy pixel DP[N+1], the dummy compensation transistors T3-1, T3-2, T3-3, and T3-4may be alternately turned on (e.g., in one period, odds ones of the dummy compensation transistors T3-1, T3-2, T3-3, and T3-4may be turned on while even ones of the same are turned off, and in a subsequent period, the opposite may occur).

In a first period P1, the N−3-th write gate signal GW[N−3], the N−1-th write gate signal GW[N−1], and the N+1-th write gate signal GW[N+1] may have active pulses. In the first period P1, when the dummy pixel DP[N+1] receives the data voltage VDATA, the dummy first compensation transistor T3-1is turned on, and the dummy second compensation transistor T3-2, the dummy third compensation transistor T3-3, and the dummy fourth compensation transistor T3-4are turned off, the N−1-th active pixel AP[N−1] and the N−3-th active pixel AP[N−3] may receive the data voltage VDATA. The data voltage VDATA may be applied to the first node N1through the dummy first compensation transistor T3-1. Therefore, the dummy storage capacitor CST may store the voltage of the first node N1.

In a second period P2, the N−2-th write gate signal GW[N−2], the N-th write gate signal GW[N], and the N+2-th write gate signal GW[N+2] may have active pulses. In the second period P2, when the dummy pixel DP[N+1] receives the data voltage VDATA, the dummy second compensation transistor T3-2is turned on, and the dummy first compensation transistor T3-1, the dummy third compensation transistor T3-3, and the dummy fourth compensation transistor T3-4are turned off, the N-th active pixel AP[N] and the N−2-th active pixel AP[N−2] may receive the data voltage VDATA. The data voltage VDATA may be applied to the first node N1through the dummy second compensation transistor T3-2. Therefore, the dummy storage capacitor CST may store the voltage of the first node N1.

In a third period P3, the N−1-th write gate signal GW[N−1], the N+1-th write gate signal GW[N+1], and the N+3-th write gate signal GW[N+3] may have active pulses. In the third period P3, when the dummy pixel DP[N+1] receives the data voltage VDATA, the dummy first compensation transistor T3-1and the dummy third compensation transistor T3-3are turned on, and the dummy second compensation transistor T3-2and the dummy fourth compensation transistor T3-4are turned off, the N−1-th active pixel AP[N−1] may receive the data voltage VDATA. The data voltage VDATA may be applied to the first node N1through the dummy first compensation transistor T3-1and the dummy third compensation transistor T3-3. Therefore, the dummy storage capacitor CST may store the voltage of the first node N1.

FIG.5is a block diagram illustrating an electronic device1000.FIG.6is a diagram illustrating some embodiments in which the electronic device1000ofFIG.5is implemented as a smart phone.

Referring toFIGS.5and6, the electronic device1000may include a processor1010, a memory device1020, a storage device1030, an input/output (I/O) device1040, a power supply1050, and a display device1060. The display device1060may be the display device10ofFIG.1. In addition, the electronic device1000may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic device, and the like.

In some embodiments, as illustrated inFIG.6, the electronic device1000is implemented as a smart phone. However, the electronic device1000is not limited thereto. For example, the electronic device1000may be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop, a head mounted display (HMD) device, and the like.

The processor1010may perform various computing functions. The processor1010may be a microprocessor, a central processing unit (CPU), an application processor (AP), and the like. The processor1010may be coupled to other components via an address bus, a control bus, a data bus, and the like. Further, the processor1010may be coupled to an extended bus such as a peripheral component interconnection (PCI) bus.

The memory device1020may store data for operations of the electronic device1000. For example, the memory device1020may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and the like and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, and the like.

The storage device1030may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, and the like.

The I/O device1040may include an input device such as a keyboard, a keypad, a mouse device, a touch-pad, a touch-screen, and the like, and an output device such as a printer, a speaker, and the like. In some embodiments, the I/O device1040includes the display device1060.

The power supply1050may provide power for operations of the electronic device1000.

The display device1060may be connected to other components through buses or other communication links.

The inventive concepts may be applied to any display device and any electronic device including the touch panel. For example, the inventive concepts may be applied to a mobile phone, a smart phone, a tablet computer, a digital television (TV), a 3D TV, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

It will be understood that, although the terms “first”, “second”, “third”, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the inventive concept.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “include,” “including,” “comprises,” “comprising,” “has,” “have,” and “having,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and/or B” denotes A, B, or A and B. Expressions such as “one or more of” and “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression “one or more of A, B, and C,” “at least one of A, B, or C,” “at least one of A, B, and C,” and “at least one selected from the group consisting of A, B, and C” indicates only A, only B, only C, both A and B, both A and C, both B and C, or all of A, B, and C.

Further, the use of “may” when describing embodiments of the inventive concept refers to “one or more embodiments of the inventive concept.” Also, the term “exemplary” is intended to refer to an example or illustration.

It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent” another element or layer, it can be directly on, connected to, coupled to, or adjacent the other element or layer, or one or more intervening elements or layers may be present. When an element or layer is referred to as being “directly on,” “directly connected to”, “directly coupled to”, “in contact with”, “in direct contact with”, or “immediately adjacent” another element or layer, there are no intervening elements or layers present.

As used herein, the term “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by those of ordinary skill in the art.

As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

The display device and/or any other relevant devices or components according to embodiments of the present invention described herein may be implemented utilizing any suitable hardware, firmware (e.g., an application-specific integrated circuit), software, or a suitable combination of software, firmware, and hardware. For example, the various components of the display device may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of the display device may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a same substrate. Further, the various components of the display device may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the scope of the exemplary embodiments of the present invention.

The foregoing is illustrative of the inventive concept and is not to be construed as limiting thereof. Although a few embodiments of the inventive concept have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and features of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined by the claims and equivalents thereof. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.