Patent ID: 12230477

DETAILED DESCRIPTION

Some embodiments include a high voltage nanosecond pulser system with an control system. In some embodiments, the control system can monitor and/or measure and/or record waveforms produce by the high voltage nanosecond pulser. In some embodiments, the control system may monitor the output waveforms produced by the high voltage nanosecond pulser system. In some embodiments, the control system may perform waveform digitization and/or waveform processing.

In some embodiments, a high voltage nanosecond pulser system may pulse voltages with amplitudes of about 2 kV to about 40 kV. In some embodiments, a high voltage nanosecond pulser system may switch with frequencies up to about 500 kHz. In some embodiments, a high voltage nanosecond pulser system may provide single pulses of varying pulse widths from about 50 seconds to about 1 nanosecond. In some embodiments, a high voltage nanosecond pulser system may switch at pulse repetition frequencies greater than about 10 kHz. In some embodiments, a high voltage nanosecond pulser system may operate with rise times less than about 20 ns.

FIG.1is a circuit diagram of a nanosecond pulser system100according to some embodiments. The nanosecond pulser system100can be implemented within a high voltage nanosecond pulser system. The nanosecond pulser system100can be generalized into five stages (these stages could be broken down into other stages or generalized into fewer stages and/or may or may not include the components shown in the figure). The nanosecond pulser system100includes a pulser and transformer stage101, a resistive output stage102, a lead stage103, a DC bias compensation circuit104, and a load stage106.

In some embodiments, the nanosecond pulser system100can produce pulses from the power supply with voltages greater than 2 kV, with rise times less than about 20 ns, and frequencies greater than about 10 kHz.

In some embodiments, the pulser and transformer stage101can produce a plurality of high voltage pulses with a high frequency and fast rise times and fall times. In all of the circuits shown, the high voltage pulser may comprise a nanosecond pulser.

In some embodiments, the pulser and transformer stage101can include one or more solid state switches S1(e.g., solid state switches such as, for example, IGBTs, a MOSFETs, a SiC MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, etc.), one or more snubber resistors R3, one or more snubber diodes D4, one or more snubber capacitors C5, and/or one or more freewheeling diodes D2. One or more switches and or circuits can be arranged in parallel or series.

In some embodiments, the load stage106may represent an effective circuit for a plasma deposition system, plasma etch system, or plasma sputtering system. The capacitance C2may represent the capacitance of the dielectric material upon which a wafer may sit or capacitance C2may represent the capacitance between an electrode and a wafer which are separated by a dielectric material. The capacitor C3may represent the sheath capacitance of the plasma to the wafer. The capacitor C9may represent capacitance within the plasma between a chamber wall and the top surface of the wafer. The current source12and the current source I1may represent the ion current through the plasma sheaths.

In some embodiments, the resistive output stage102may include one or more inductive elements represented by inductor L1and/or inductor L5. The inductor L5, for example, may represent the stray inductance of the leads in the resistive output stage102. Inductor L1may be set to minimize the power that flows directly from the pulser and transformer stage101into resistor R1.

In some embodiments, the resistor R1may dissipate charge from the load stage106, for example, on fast time scales (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc. time scales). The resistance of resistor R1may be low to ensure the pulse across the load stage106has a fast fall time tf.

In some embodiments, the resistor R1may include a plurality of resistors arranged in series and/or parallel. The capacitor C11may represent the stray capacitance of the resistor R1including the capacitance of the arrangement series and/or parallel resistors. The capacitance of stray capacitance C11, for example, may be less than 5 nF, 2 nF, 1 nF, 500 pF, 250 pF, 100 pF, 50 pF, 10 pF, 1 pF, etc. The capacitance of stray capacitance C11, for example, may be less than the load capacitance such as, for example, less than the capacitance of C2, C3, and/or C9.

In some embodiments, a plurality of pulser and transformer stages101can be arranged in parallel and coupled with the resistive output stage102across the inductor L1and/or the resistor R1. Each of the plurality of pulser and transformer stages101may each also include diode D1and/or diode D6.

In some embodiments, the capacitor C8may represent the stray capacitance of the blocking diode D1. In some embodiments, the capacitor C4may represent the stray capacitance of the diode D6.

In some embodiments, the DC bias compensation circuit104may include a DC voltage source V1that can be used to bias the output voltage either positively or negatively. In some embodiments, the capacitor C12isolates/separates the DC bias voltage from the resistive output stage and other circuit elements. It allows for a potential shift from one portion of the circuit to another. In some applications the potential shift it establishes is used to hold a wafer in place. Resistance R2may protect/isolate the DC bias supply from the high voltage pulsed output from the pulser and transformer stage101.

In this example, the DC bias compensation circuit104is a passive bias compensation circuit and can include a bias compensation diode D1and a bias compensation capacitor C15. The bias compensation diode C15can be arranged in series with offset supply voltage V1. The bias compensation capacitor C15can be arranged across either or both the offset supply voltage V1and the resistor R2. The bias compensation capacitor C15can have a capacitance less than 100 nH to 100 μF such as, for example, about 100 μF, 50 μF, 25 μF, 10 μF, 2μ, 500 nH, 200 nH, etc.

In some embodiments, the bias capacitor C12may allow for a voltage offset between the output of the pulser and transformer stage101(e.g., at the position labeled125) and the voltage on the electrode (e.g., at the position labeled124). In operation, the electrode may, for example, be at a DC voltage of −2 kV during a burst, while the output of the nanosecond pulser alternates between +6 kV during pulses and 0 kV between pulses.

In some embodiments, the bias compensation capacitor C15and the bias compensation diode D1may allow for the voltage offset between the output of the pulser and transformer stage101(e.g., at the position labeled125) and the voltage on the electrode (e.g., at the position labeled124) to be established at the beginning of each burst, reaching the needed equilibrium state. For example, charge is transferred from bias capacitor C12into bias compensation capacitor C15at the beginning of each burst, over the course of a plurality of pulses (e.g., about 5-100 pulses), establishing the correct voltages in the circuit.

In some embodiments, the DC bias compensation circuit104may include one or more high voltage switches placed across the bias compensation diode D1and coupled with the power supply V1. In some embodiments, a high voltage switch may include a plurality of switches arranged in series to collectively open and close high voltages.

A high voltage switch may be coupled in series with either or both an inductor and a resistor. The inductor may limit peak current through high voltage switch. The inductor, for example, may have an inductance less than about 100 μH such as, for example, about 250 μH, 100 μH, 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, etc. The resistor, for example, may shift power dissipation to the resistive output stage102. The resistance of resistor may have a resistance of less than about 1,000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 10 ohms, etc.

In some embodiments, a high voltage switch may include a snubber circuit.

In some embodiments, the high voltage switch may include a plurality of switches arranged in series to collectively open and close high voltages. For example, the high voltage switch may, for example, include any switch described in U.S. patent application Ser. No. 16/178,565, filed Nov. 1, 2018, titled “High Voltage Switch with Isolated Power,” which is incorporated into this disclosure in its entirety for all purposes.

In some embodiments, a high voltage switch may be open while the pulser and transformer stage101is pulsing and closed when the pulser and transformer stage101is not pulsing. When the high voltage switch is closed, for example, current can short across the bias compensation diode C15. Shorting this current may allow the bias between the wafer and the chuck to be less than 2 kV, which may be within acceptable tolerances.

In some embodiments, the pulser and transformer stage101can produce pulses having a high pulse voltage (e.g., voltages greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), high pulse repetition frequencies (e.g., frequencies greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), fast rise times (e.g., rise times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), fast fall times (e.g., fall times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.) and/or short pulse widths (e.g., pulse widths less than about 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

In some embodiments, the various stages or components shown inFIG.1are optional. For example, the resistive output stage102may be removed or replaced.

FIG.2shows example waveforms produced by the nanosecond pulser system100. In these example waveforms, the pulse waveform205may represent the voltage provided by the pulser and transformer stage101. As shown, the pulse waveform205produces a pulse with the following qualities: high voltage (e.g., greater than about 4 kV as shown in the waveform), a fast rise time (e.g., less than about 200 ns as shown in the waveform), a fast fall time (e.g., less than about 200 ns as shown in the waveform), and short pulse width (e.g., less than about 300 ns as shown in the waveform). The waveform210may represent the voltage at the surface of a wafer represented in the circuit shown inFIG.1by the point between capacitor C2and capacitor C3or the voltage across capacitor C3. The pulse waveform215represent the current flowing from the pulser and transformer stage101to the plasma. The nanosecond pulser system100may or may not include either or both diodes D1or D2.

During the transient state (e.g., during an initial number of pulses not shown in the figure), the high voltage pulses from the pulser and transformer stage101charge the capacitor C2. Because the capacitance of capacitor C2is large compared to the capacitance of capacitor C3and/or capacitor C1, and and/or because of the short pulse widths of the pulses, the capacitor C2may take a number of pulses from the high voltage pulser to fully charge. Once the capacitor C2is charged the circuit reaches a steady state, as shown by the waveforms inFIG.2.

In steady state and when the switch S1is open, the capacitor C2is charged and slowly dissipates through the resistive output stage102, as shown by the slightly rising slope of waveform210. Once the capacitor C2is charged and while the switch S1is open, the voltage at the surface of the wafer (the point between capacitor C2and capacitor C3) is negative. This negative voltage may be the negative value of the voltage of the pulses provided by the pulser and transformer stage101. For the example waveform shown inFIG.2, the voltage of each pulse is about 4 kV; and the steady state voltage at the wafer is about −4 kV. This results in a negative potential across the plasma (e.g., across capacitor C3) that accelerates positive ions from the plasma to the surface of the wafer. While the switch S1is open, the charge on capacitor C2slowly dissipates through the resistive output stage.

When the switch S1is closed, the voltage across the capacitor C2may flip (the pulse from the pulser is high as shown in the pulse waveform205) as the capacitor C2is charged. In addition, the voltage at the point between capacitor C2and capacitor C3(e.g., at the surface of the wafer) changes to about zero as the capacitor C2charges, as shown in waveform210. Thus, the pulses from the high voltage pulser produce a plasma potential (e.g., a potential in a plasma) that rise from a negative high voltage to zero and returns to the negative high voltage at high frequencies, with fast rise times, fast fall times, and/or short pulse widths.

In some embodiments, the action of the resistive output stage, elements represented by the resistive output stage102, that may rapidly discharge the stray capacitance C1, and may allow the voltage at the point between capacitor C2and capacitor C3to rapidly return to its steady negative value of about −4 kV as shown by waveform210. The resistive output stage may allow the voltage at the point between capacitor C2and capacitor C3to exists for about % of the time, and thus maximizes the time which ions are accelerated into the wafer. In some embodiments, the components contained within the resistive output stage may be specifically selected to optimize the time during which the ions are accelerated into the wafer, and to hold the voltage during this time approximately constant. Thus, for example, a short pulse with fast rise time and a fast fall time may be useful, so there can be a long period of fairly uniform negative potential.

Various other waveforms may be produced by the nanosecond pulser system100.

FIG.3is a circuit diagram of a nanosecond pulser system300with the pulser and transformer stage101and an energy recovery circuit305according to some embodiments. The energy recovery circuit, for example, may replace the resistive output stage102shown inFIG.1. In this example, the energy recovery circuit305may be positioned on or electrically coupled with the secondary side of the transformer T1. The energy recovery circuit305, for example, may include a diode330(e.g., a crowbar diode) across the secondary side of the transformer T1. The energy recovery circuit305, for example, may include diode310and inductor315(arranged in series), which can allow current to flow from the secondary side of the transformer T1to charge the power supply C7. The diode310and the inductor315may be electrically connected with the secondary side of the transformer T1and the power supply C7. In some embodiments, the energy recovery circuit305may include diode335and/or inductor340electrically coupled with the secondary of the transformer T1. The inductor340may represent the stray inductance and/or may include the stray inductance of the transformer T1.

When the nanosecond pulser is turned on, current may charge the load stage106(e.g., charge the capacitor C3, capacitor C2, or capacitor C9). Some current, for example, may flow through inductor315when the voltage on the secondary side of the transformer T1rises above the charge voltage on the power supply C7. When the nanosecond pulser is turned off, current may flow from the capacitors within the load stage106through the inductor315to charge the power supply C7until the voltage across the inductor315is zero. The diode330may prevent the capacitors within the load stage106from ringing with the inductance in the load stage106or the bias compensation circuit104.

The diode310may, for example, prevent charge from flowing from the power supply C7to the capacitors within the load stage106.

The value of inductor315can be selected to control the current fall time. In some embodiments, the inductor315can have an inductance value between 1 μH-500 μH.

In some embodiments, the energy recovery circuit305may include an energy recovery switch that can be used to control the flow of current through the inductor315. The energy recovery switch, for example, may be placed in series with the inductor315. In some embodiments, the energy recovery switch may be closed when the switch S1is open and/or no longer pulsing to allow current to flow from the load stage106back to the high voltage load C7.

In some embodiments, the energy recovery switch may include a plurality of switches arranged in series to collectively open and close high voltages. For example, the energy recovery switch may, for example, include any switch described in U.S. patent application Ser. No. 16/178,565, filed Nov. 1, 2018, titled “High Voltage Switch with Isolated Power,” which is incorporated into this disclosure in its entirety for all purposes.

In some embodiments, the nanosecond pulser system300may produce similar waveforms as those shown inFIG.2.

FIG.4is a block diagram of an control system400for a nanosecond pulser system100(or nanosecond pulser system300) according to some embodiments. In some embodiments, the control system400may be electrically coupled with the nanosecond pulser system100at one or more locations. For example, a first HV signal405A (or a second HV signal405B) may include the voltage signal at point120of the nanosecond pulser system100, which is between the pulser and transformer stage101and the bias compensation circuit104. As another example, a first HV signal405A (or a second HV signal405B) may include the voltage signal at point124of the nanosecond pulser system100, which is between the load stage106and the bias compensation circuit104. As another example, a first HV signal405A (or a second HV signal405B) may include the voltage signal at point125of the nanosecond pulser system100, which is prior to the resistive output stage102. As another example, a first HV signal405A (or a second HV signal405B) may include the voltage on the wafer, chuck, or electrode. While two signals are shown, any number of signals may be received. As another example, a first HV signal405A (or a second HV signal405B) may include the voltage across the resistor R1in resistive output stage102, which may be representative of the ion current in the chamber. As another example, a first HV signal405A (or a second HV signal405B) may include the voltage in the energy recovery stage, such as, for example, the voltage across inductor315, which may be representative of the ion current in the chamber.

In some embodiments, the first HV signal405A and the second HV signal405B may include the voltage signals on each side of the capacitor C12of the bias compensation circuit104. Any number of other signals may be received.

In some embodiments, the first HV signal405A or the second HV signal405B may include the voltage signals provided to the load stage106. In some embodiments, the first HV signal405A or the second HV signal405B may include the voltage signals provided to the bias compensation circuit104. In some embodiments, the first HV signal405A or the second HV signal405B may include the voltage signals provided to the lead stage103. In some embodiments, the first HV signal405A or the second HV signal405B may include the voltage signals provided to the pulser and transformer stage101may be measured. In some embodiments, the first HV signal405A or the second HV signal405B may include the voltage signals provided to the resistive output stage102.

The first HV signal405A and the second HV signal405B collectively or individually may be referred to as the HV input signal405.

In some embodiments, the HV input signal405may divided at voltage divider410. The voltage divider410, for example, may include high value resistors or low value capacitors to divide the high voltage HV input signal (e.g., greater than 1 KV) to a low voltage signal (e.g., less than 50 V). The voltage divider410, for example, may divide the voltage with a 500:1 ratio, 1,000:1 ratio, a 10,000:1 ratio, a 100,000:1 ratio, etc. The voltage divider410, for example, may divide the HV input signal405voltage of 0-10 kV to a voltage of 0-20 V. The voltage divider410, for example, may divide the voltage with minimal power loss such as, for example, less than about 5 W of power loss.

In some embodiments, the voltage divider410may include a low value capacitor, a large value capacitor, a low value resistor, and a large value resistor. The low value capacitor, for example, may comprise a capacitor that has a capacitance value of about 0.1 pF, 0.5 pF, 1.0 pF, 2.5 pF, 5.0 pF, 10.0 pF, 100 pF, 1 nF, 10 nF, etc. The large value capacitor, for example, may comprise a capacitor that has a capacitance value of about 500 pf. In some embodiments, the large value capacitor may have a capacitance value that is about 50, 100, 250, 500, 1,000, 2,500, 5,000 pF, etc. greater than the capacitance value of the low value capacitor.

The low value resistor may have a resistance value of about 1.0 kΩ, 2.5 kΩ, 5.0 kΩ, 10 kΩ, 25 kΩ, 50 kΩ, 100 kΩ, etc. The large value resistor may have a resistance value of about 0.5 MΩ, 1.0 MΩ, 2.5 MΩ, 5.0 MΩ, 10 MΩ, 25 MΩ, 50 MΩ, 100 MΩ, etc. In some embodiments, the large value resistor may have a resistance value that is about 50Ω, 100Ω, 250 Ω, 500Ω, 1,000Ω, 2,500Ω, 5,000Ω, etc. greater than the resistance value of the low value resistor. In some embodiments, the ratio of the low value capacitor to the large value capacitor may be substantially the same as the ratio of the low value resistor to the large value resistor.

In some embodiments, the voltage divider410may receive the HV input signal and output a divided voltage signal. The divided voltage signal, for example, may be 100, 250, 500, 750, 1,000, etc. times smaller than the HV input signal.

In some embodiments, a filter415may be included such as, for example, to filter out any noise from the divided voltage signal. The filter, for example, may include any type of low pass filter, a band pass filter, a band stop filter, or a high pass filter.

In some embodiments, the divided voltage signal may be digitized by the first ADC420. Any type of analog to digital converter may be used. The first ADC420may produce a digitized waveform signal. In some embodiments, the first ADC420may capture data at 100, 250, 500, 1,000, 2,000, 5,000 MSPS (megasamples per second or millions of samples per second). In some embodiments, the digitized waveform signal may be communicated to the controller425using any type of communication protocol such as, for example, SPI, UART, RS-232, USB, I2C, etc.

In some embodiments, any of the voltage divider410, the filter415, or the first ADC420may be isolated from the nanosecond pulser system100via galvanic isolation or via fiber optic link.

In some embodiments, the controller425may comprise any type of controller such as, for example, an FPGA, ASIC, complex programmable logic device, microcontroller, system on a chip (SoC), or any combination thereof. In some embodiments, the controller425may include any or all the components of the computational system600. In some embodiments, the controller425may include a standard microcontroller such as, for example, Broadcom Arm Cortex, Intel ARM Cortex, PIC32, etc.

In some embodiments, the controller425may receive a trigger signal from trigger430. In other embodiments, the first ADC420may receive the trigger signal from trigger430. The trigger signal may provide the timing of data acquisition at the first ADC420. The trigger signal, for example, may be a 5V TTL trigger. The trigger signal, for example, may, have a 50 ohm termination.

The digitized signal may then be output from the controller425via one or more output ports such as, for example, a first output435A or a second output435B (individually or collectively output435). These outputs may be coupled with a nanosecond pulser controller. Either or both the output435may include an electrical connecter such as, for example, an LVDS, TTL, LVTTL connector. Either or both the output435may provide data to the nanosecond pulser controller using any type of communication protocol such as, for example, SPI, UART, RS-232, USB, I2C, EtherCat, Ethernet, Profibus, PROFINET.

In some embodiments, the control system400may couple with the nanosecond pulser system100via a 4 mm Multilam receptacles on the control system400.

In some embodiments, the control system400may include a second ADC445, which may receive inputs from a first sensor450A and a second sensor450B (individually or collectively sensor450) (or any number of sensors). In some embodiments, the second ADC445may digitize analog signals from the sensors450. The sensors450may include, for example, a sensor that senses inlet water temperature, dielectric fluid temperature, dielectric fluid pressure, chassis air temperature, voltage, fluid flow, fluid leak sensor, etc. In some embodiments, the second ADC445may include ARM, PIC32, AVR, PSOC, or PIC32.

In some embodiments, the second ADC445and the first ADC420may comprise a single ADC device. In some embodiments, either or both the second ADC445or the first ADC420may be part of the controller425. In some embodiments, the first ADC420may operate at a higher acquisition rate than the second ADC.

In some embodiments, the control system may measure the full-width half-max, peak voltage, DC bias, rise time, fall time, etc. of pulses in the nanosecond pulser system100.

In some embodiments, the control system400may monitor the voltage, frequency, pulse width, etc. of pulses and, in response, may adjust the voltage, pulse repetition frequency, pulse width, burst repetition frequency (where a burst includes a plurality of pulses), etc. provided to the input of the nanosecond pulser system100. For example, the first ADC420may monitor the voltage amplitude of a waveform. This voltage data may be provided to the nanosecond pulser controller. The nanosecond pulser controller may adjust the amplitude or frequency of the signal provided to the nanosecond pulser system100.

In some embodiments, the control system400may output arbitrary pulse signals via output435to one or more nanosecond pulser systems100. The output435, for example, may include either fiber or electric connections. In some embodiments, control system400can include a plurality of output pulse channels (e.g., 1, 2, 5, 8, 20, 50, 100, etc.) that may, for example, be independent from each other. The plurality of output pulse channels may, for example, output pulses with sub-nanosecond resolution.

For example, if the pulse voltage is less than a predetermined voltage, the controller425may send a signal to the nanosecond pulser system100to produce pulses with a higher voltage. If the pulse voltage is greater than a predetermined voltage, the first ADC420may send a signal to the nanosecond pulser system100to produce pulses with a lower voltage. In some embodiments, the signal to the nanosecond pulser to increase the pulse voltage may comprise a low voltage pulse that has a longer pulse width than the previously sent signal, and the signal to the nanosecond pulser to decrease the pulse voltage may comprise a low voltage pulse that has a shorter pulse width than the previously sent signal.

As another example, if the pulse repetition frequency is greater than an desired pulse repetition frequency, the controller425may send a signal to the nanosecond pulser system100to produce pulses with a lower frequency. If the burst repetition frequency is less than an desired burst repetition frequency, the controller425may send a signal to the nanosecond pulser system100to produce pulses with a higher pulse repetition frequency. If the full width half max of the measured pulse is different than an desired burst repetition frequency, the controller425may send a signal to the nanosecond pulser system100to produce a pulses with an adjusted pulse width or pulse repetition frequency.

As another example, if the waveform pulse width is longer than an desired pulse width, the first ADC420may send a signal to the nanosecond pulser system100to produce a waveform with a shorter or longer pulse width. If the waveform duty cycle is shorter or longer than an desired duty cycle, the first ADC420may send a signal to the nanosecond pulser system100to produce a pulses with the appropriate duty cycle.

The control system400may monitor other waveform characteristics and/or adjust these other characteristics.

In some embodiments, the control system400may output arbitrary pulse signals via output435to one or more nanosecond pulser systems100. For example, the control system may comprise an arbitrary pulse generator. The output435, for example, may include either fiber or electric connections. In some embodiments, control system400can include a plurality of output pulse channels (e.g., 1, 2, 5, 8, 20, 50, 100, etc.) that may, for example, be independent from each other. The plurality of output pulse channels may, for example, output pulses with sub-nanosecond resolution. In some embodiments, the control system400may output pulses with resolution less than about 0.1 ns. In some embodiments, the control system400may output pulses with jitter less than about 100 ps.

In some embodiments, each output pulse channel of the control system400may output pulses to a nanosecond pulser system100that triggers the nanosecond pulser system100. The control system400may, for example, adjust parameters of the output pulses in real-time or between pulses. These parameters may include pulse width, pulse repetition frequency, duty cycle, burst repetition frequency, voltage, number of pulses in a burst, the number of burst, etc. In some embodiments, one or more parameters may be adjusted or changed based on input to the control system400or based on a recipe or a program.

For example, a recipe may include alternating high bursts and low bursts. A high burst, for example, may include a plurality of high voltage pulses. A low burst, for example, may include a plurality of lower voltage pulses. The high burst and the low burst may, for example, include the same number of pulses or a different number of pulses within each burst. A low burst, for example, may have a voltage that is 10%, 20%, 30%, 40%, 50%, etc. lower than the voltage of the high burst voltage.

The alternating high bursts and low bursts may include 5%, 20%, 50%, 100%, 125%, 150%, etc. ratio of low bursts to high bursts (low-high ratio). For example, a 20% low-high ratio may include a train of 10 bursts, where each burst includes about 500 pulses (or any number of pulses from 1 to 10,000 pulses. In a train of 10 bursts with a 10% low-high ratio, 2 bursts may be low voltage bursts and 8 bursts may be high voltage bursts.

In some embodiments, the controller425may communicate pulses with longer low voltage pulses to produce the high bursts and communicate pulses with shorter low voltage pulses to produce the low bursts to the nanosecond pulser to produce alternating high bursts and low bursts as described in U.S. patent application Ser. No. 16/114,195, titled “ARBITRARY WAVEFORM GENERATION USING NANOSECOND PULSES,” which is incorporated herein for all purposes.

In some embodiments, the control system400comprises an electrical shield. An electrical shield, for example, can separate the high voltage components from the low voltage components. An electrical shield, for example, may be disposed physically between the divider410and the controller425or the first ADC420. As another example, the electric shield may be disposed physically between the nanosecond pulser system100and the controller425or the first ADC420.

In some embodiments, the electric shield may be disposed physically between resistors in the divider410. In some embodiments, the electric shield may be disposed physically between capacitors in the divider410.

In some embodiments, the electrical shield may comprise any type of electrically conductive material or metal such as, for example, copper, nickel, aluminum, bronze, steel, brass, etc. In some embodiments, the electrical shield may comprise sheet metal, metal screen, or metal foam.

In some embodiments, the control system400may monitor the sensors150and take action. A number of examples are provided below.

In some embodiments, the nanosecond pulser system100may include a cooling subsystem. In some embodiments, the cooling subsystem may include a fluid, such as, for example, either water or a dielectric fluid, that flows through the cooling subsystem to remove heat from the nanosecond pulser system100. For example, one of the sensors450may include a flow rate sensor for fluid in the cooling system. If the controller425determines the flow rate is below a flow rate threshold, the control system400will not allow the nanosecond pulser system100to turn on. If the controller425determines the flow rate is below a flow rate threshold, the controller425may turn off the nanosecond pulser system100. In some embodiments, the flow rate sensor (in some cases with the controller425) may be a flow rate interlock. A flow rate interlock, for example, may prevent the nanosecond pulser system100from turning on or may turn off the nanosecond pulser system100, if it is already on, if the flow rate is below the flow rate threshold.

For example, one of the sensors450may include a thermometer coupled with the cooling subsystem. If the controller425determines the temperature of the cooling subsystem (e.g., the temperature of the fluid) is above a water temperature threshold, the control system400will not allow the nanosecond pulser system100to turn on. If the controller425determines the temperature of the water is above the water temperature threshold, the controller425may turn off the nanosecond pulser system100. A temperature interlock, which is distinct from the controller425, for example, may prevent the nanosecond pulser system100from turning on or may turn off the nanosecond pulser system100, if it is already on, if the temperature is above the water temperature threshold.

For example, one of the sensors450may include a liquid level sensor for a fluid reservoir in a cooling system. If the controller425determines the reservoir liquid level is above a liquid level threshold, the control system400will not turn on. If the controller425determines the reservoir liquid level is above the liquid level threshold, the controller425may turn off the nanosecond pulser system100. A liquid level interlock, which is distinct from the controller425, for example, may prevent the nanosecond pulser system100from turning on or may turn off the nanosecond pulser system100, if it is already on, if the liquid level is below the liquid level threshold.

In some embodiments, the nanosecond pulser system100may include a nitrogen purge subsystem that pumps nitrogen into the nanosecond pulser system. The nitrogen purge system, for example, may introduce dry nitrogen into an enclosure within which the high voltage nanosecond pulser system is disposed. For example, one of the sensors450may include a nitrogen pressure sensor. If the controller425determines the nitrogen pressure level is below a pressure threshold the control system400will not turn on. If the controller425determines the nitrogen pressure level is below the pressure threshold the controller425may turn off the nanosecond pulser system100. A pressure interlock, which is distinct from the controller425, for example, may prevent the nanosecond pulser system100from turning on or may turn off the nanosecond pulser system100, if it is already on, if the pressure is below the pressure threshold.

In some embodiments, one of the sensors450may include a DC voltage sensor that may be coupled with a DC power supply in the nanosecond pulser system100. For example, if multiple DC power supply systems are used in nanosecond pulser system100and during operation the voltage varies by more than a set percentage (e.g., 1%, 5%, 10%, 20%, etc.) or more than an absolute voltage (e.g., 5V, 10V, 50V, 100V, etc.) then the controller425may turn off the nanosecond pulser system100. As another example, if power supply systems are used and during operation the voltage output differs by more than a percentage from a set voltage (e.g., 1%, 5%, 10%, 20%, etc.) or more than an absolute voltage from the set voltage (e.g., 5V, 10V, 50V, 100V, etc.) then the controller425may turn off pulsing.

In some embodiments, output435may include an EtherCat module that may communicate with a third party system (e.g., an external system). In some embodiments, the EtherCat module may comprise any type of communication module. In some embodiments, the EtherCat may include one or more components of the computational system600.

In some embodiments, the control system400may include one or more interlocks coupled with one or more sensors450. An interlock may, for example, automatically interrupt operation of the nanosecond pulser system100without interaction with the controller425if the one of the sensor detects a parameter out of tolerance. An interlock signal, for example, may be coupled with a nanosecond pulser system100control signal using an AND gate that only allows the control signal to operate the nanosecond pulser if the interlock provides a positive signal.

In some embodiments, a sensor450may be coupled with both the controller425and an interlock. For example, the interlock may operate at a first threshold level and the controller425may operate at a second, different threshold level. The interlock, for example, may operate at a first threshold that protects the nanosecond pulser system from immediate or near-term damage. The controller, for example, may operate at a second threshold that is out of tolerance and the controller may adjust various parameters to bring the system into tolerance, or monitor the system for a period of time before turning off the nanosecond pulser, or may turn off the nanosecond pulser.

For example, a 24V DC interlock may be included may be coupled with a voltage sensor that measures input voltage from a 24V DC power supplier. If the voltage from the 24 V DC power supply exceeds 24V by a predetermined threshold or percentage, then the interlock will send a negative signal to the nanosecond pulser system100and the nanosecond pulser system100will not operate.

As another example, a high voltage DC interlock may be included may be coupled with a voltage sensor that measures input voltage from a high voltage DC power supplier. If the voltage from the high voltage DC power supply exceeds the expected voltage by a predetermined threshold or percentage, then the interlock will send a negative signal to the nanosecond pulser system100and the nanosecond pulser system100will not operate.

As another example, a dry N2 pressure interlock may be coupled with a pressure sensor coupled with a nitrogen purge subsystem. If the pressure from the nitrogen purge subsystem exceeds a predetermined threshold or percentage, then the interlock will send a negative signal to the nanosecond pulser system100and the nanosecond pulser system100will not operate.

As another example, a water flow interlock may be coupled with a water line in the thermal management system. If the flow rate of the water exceeds a predetermined threshold or percentage, then the interlock will send a negative signal to the nanosecond pulser system100and the nanosecond pulser system100will not operate.

As another example, a dielectric fluid flow interlock may be coupled with a dielectric fluid line in the thermal management system. If the flow rate of the dielectric fluid exceeds a predetermined threshold or percentage, then the interlock will send a negative signal to the nanosecond pulser system100and the nanosecond pulser system100will not operate.

As another example, a reservoir level interlock may be coupled with a water or dielectric fluid reservoir in the thermal management system. If the reservoir level exceeds a predetermined threshold or percentage, then the interlock will send a negative signal to the nanosecond pulser system100and the nanosecond pulser system100will not operate.

As another example, a water temperature interlock may be coupled with a thermometer in the thermal management system. If the temperature of the water exceeds a predetermined threshold or percentage, then the interlock will send a negative signal to the nanosecond pulser system100and the nanosecond pulser system100will not operate.

As another example, a dielectric fluid temperature interlock may be coupled with a thermometer in the thermal management system. If the temperature of the dielectric fluid exceeds a predetermined threshold or percentage, then the interlock will send a negative signal to the nanosecond pulser system100and the nanosecond pulser system100will not operate.

In some embodiments, the control system may control the operation of a pulsing system such as, for example, pulse width, duty cycle, high voltage set point, on/off, returns current output voltage, high voltage current set point, returns current output current, enable high voltage output, returns high voltage enable state, emergency shutdown, etc.

In some embodiments, a user may interface with the control system through an EtherCat module. A user, for example, may issue a PW command to set the output pulse width. As another example, user may issue DUTY command to set the duty cycle. As another example, a user may issue a PWR command to turn the power on and begin operation of unit or off to end operation of the unit. As another example, the unit may continue to operate as set until issued another command to change duty cycle, pulse width, or issued another PWR command to shut off.

In some embodiments, the control system400may receive commands from an external source in any type of communication protocols such as, for example, EtherCat, LXI, Ethernet, Profibus, PROFINET, RS-232, ModBus, USB, UART, SPI, CC-Lin, etc.

FIG.5is a block diagram of a flowchart of process500according to some embodiments. Process500includes a number of blocks. Any additional blocks may be added or any blocks may be removed. The process500may, for example, be executed by one or more components of computational system600. The process500may, for example be executed by the control system400.

At block505, the process500can send a plurality of low voltage pulses to a high voltage pulser system (e.g., nanosecond pulser100or nanosecond pulser300) based on a recipe. The low voltage pulses, for example, may have a peak voltage of less than 20 V such as, for example, 5V. The low voltage pulses may have a pulse repetition frequency and each pulse may have a pulse width.

In some embodiments, the recipe may include alternating high bursts and low bursts as described above. In some embodiments, the recipe may be adjusted or changed in real time. In some embodiments, the recipe may be dependent on various parameters or characteristics of the plasma chamber.

At block510, high voltage pulses can be measured at the high voltage pulser. The high voltage pulsers, for example, may have a peak voltage greater than 2 kV. In some embodiments, the high voltage pulses may have a peak voltage that is more then 100 times the peak voltage of the low voltage pulses. In some embodiments, the high voltage pulses may be measured at the electrode within a plasma chamber. In some embodiments, the high voltage pulses may be measured across a resistor within a resistive output stage or an energy recover stage of the high voltage pulser. In some embodiments, the high voltage pulses may be measured at a bias capacitor within the high voltage pulser.

In some embodiments, the full-width half-max, peak voltage, DC bias, rise time, fall time, etc. of the high voltage pulses can be measured.

At block515, the measure pulses can be compared with the desired (or anticipated) pulses. If the measured pulses are consistent with the desired pulses (e.g., within some tolerance), the process500proceeds to block505and the process repeats.

If the measured pulses are not consistent with the desired pulses, then process500proceeds to block520. At block520the pulse width or the pulse repetition frequency of the low voltage pulses are adjusted. For example, if the voltage of the high voltage pulses is lower than desired, then the pulse width of the low voltage pulses may be increased. As another example, if the voltage of the high voltage pulses is higher than desired, then the pulse width of the low voltage pulses may be decreased.

For example, if the pulse repetition frequency (or the pulse repetition period) of the high voltage pulses is lower than desired, then the pulse repetition frequency of the low voltage pulses may be increased. As another example, if the pulse repetition frequency (or the pulse repetition period) of the high voltage pulses is higher than desired, then the pulse repetition frequency of the low voltage pulses may be decreased.

In some embodiments, the process500may be executed in real time. For example, the process500may repeat in less than about 20 μs, 10 μs, 5 μs, 1 μs, etc. As another example, the process500may control the accuracy of the period between pulses (e.g., the pulse repetition period) with an accuracy less than about 50 μs, 20 μs, 10 μs, 5 μs, 1 μs, etc.

In some embodiments, the control system400may include a computational system that includes some or all of the components of computational system600, shown inFIG.6. As another example, computational system600can be used perform any calculation, identification and/or determination described in this document. The computational system600may include hardware elements that can be electrically coupled via a bus605(or may otherwise be in communication, as appropriate). The hardware elements can include one or more processors610, including without limitation one or more general-purpose processors and/or one or more special-purpose processors (such as digital signal processing chips, graphics acceleration chips, and/or the like); one or more input devices615, which can include without limitation a mouse, a keyboard and/or the like; and one or more output devices620, which can include without limitation a display device, a printer and/or the like.

The computational system600may further include (and/or be in communication with) one or more storage devices625, which can include, without limitation, local and/or network accessible storage and/or can include, without limitation, a disk drive, a drive array, an optical storage device, a solid-state storage device, such as a random access memory (“RAM”) and/or a read-only memory (“ROM”), which can be programmable, flash-updateable and/or the like. The computational system600might also include a communications subsystem630, which can include without limitation a modem, a network card (wireless or wired), an infrared communication device, a wireless communication device and/or chipset (such as a Bluetooth device, an 802.6 device, a Wi-Fi device, a WiMax device, cellular communication facilities, etc.), and/or the like. The communications subsystem630may permit data to be exchanged with a network (such as the network described below, to name one example), and/or any other devices described herein. In many embodiments, the computational system600will further include a working memory635, which can include a RAM or ROM device, as described above.

The computational system600also can include software elements, shown as being currently located within the working memory635, including an operating system640and/or other code, such as one or more application programs645, which may include computer programs of the invention, and/or may be designed to implement methods of the invention and/or configure systems of the invention, as described herein. For example, one or more procedures described with respect to the method(s) discussed above might be implemented as code and/or instructions executable by a computer (and/or a processor within a computer). A set of these instructions and/or codes might be stored on a computer-readable storage medium, such as the storage device(s)625described above.

In some cases, the storage medium might be incorporated within the computational system600or in communication with the computational system600. In other embodiments, the storage medium might be separate from a computational system600(e.g., a removable medium, such as a compact disc, etc.), and/or provided in an installation package, such that the storage medium can be used to program a general-purpose computer with the instructions/code stored thereon. These instructions might take the form of executable code, which is executable by the computational system600and/or might take the form of source and/or installable code, which, upon compilation and/or installation on the computational system600(e.g., using any of a variety of generally available compilers, installation programs, compression/decompression utilities, etc.) then takes the form of executable code.

Unless otherwise specified, the term “substantially” means within 5% or 10% of the value referred to or within manufacturing tolerances. Unless otherwise specified, the term “about” means within 5% or 10% of the value referred to or within manufacturing tolerances.

Numerous specific details are set forth herein to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter may be practiced without these specific details. In other instances, methods, apparatuses or systems that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter.

Some portions are presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory, such as a computer memory. These algorithmic descriptions or representations are examples of techniques used by those of ordinary skill in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm is a self-consistent sequence of operations or similar processing leading to a desired result. In this context, operations or processing involves physical manipulation of physical quantities. Typically, although not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared or otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals or the like. It should be understood, however, that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, it is appreciated that throughout this specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” and “identifying” or the like refer to actions or processes of a computing device, such as one or more computers or a similar electronic computing device or devices, that manipulate or transform data represented as physical electronic or magnetic quantities within memories, registers, or other information storage devices, transmission devices, or display devices of the computing platform.

The system or systems discussed herein are not limited to any particular hardware architecture or configuration. A computing device can include any suitable arrangement of components that provides a result conditioned on one or more inputs. Suitable computing devices include multipurpose microprocessor-based computer systems accessing stored software that programs or configures the computing system from a general-purpose computing apparatus to a specialized computing apparatus implementing one or more embodiments of the present subject matter. Any suitable programming, scripting, or other type of language or combinations of languages may be used to implement the teachings contained herein in software to be used in programming or configuring a computing device.

Embodiments of the methods disclosed herein may be performed in the operation of such computing devices. The order of the blocks presented in the examples above can be varied—for example, blocks can be re-ordered, combined, and/or broken into sub-blocks. Certain blocks or processes can be performed in parallel.

The use of “adapted to” or “configured to” herein is meant as open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps. Additionally, the use of “based on” is meant to be open and inclusive, in that a process, step, calculation, or other action “based on” one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited. Headings, lists, and numbering included herein are for ease of explanation only and are not meant to be limiting.

While the present subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily produce alterations to, variations of, and equivalents to such embodiments. Accordingly, it should be understood that the present disclosure has been presented for purposes of example rather than limitation, and does not preclude inclusion of such modifications, variations and/or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art.