Patent ID: 12248420

DETAILED DESCRIPTION

The multiplicity of I/O data ports mentioned above may not be technically connected directly to actually controlling and processing module1(e.g., an FPGA). An indirect control via a further FPGA therefore takes place, which is then used as a port expander. It is connected with far fewer signal lines between the FPGAs than between the peripheral pins. As already mentioned above, this requires an efficient approach for the high-performance, indirect control of connection module3to control module1, i.e., with a high update rate, low latency, and low jitter.

An arrangement of a control module1and a connection module3which is connected thereto via a first data link2is schematically illustrated inFIG.1. InFIG.1, multiple peripheral devices5are connected to connection module3via a second data link4in the form of digital I/Os. Control module1includes an FPGA or a CPU and is mounted on an FMC carrier6(FMC: FPGA mezzanine card). Connection module3includes an FPGA as a central unit. Connection module3is mounted on an FMC module7, which rests on FMC carrier6based on a plug connection. A first data link2is set up between control module1and connection module3by the plug connection. Peripheral devices5are also mounted on FMC module7.

FIG.2shows a previous approach for indirectly controlling peripheral device5via connection module3by means of control module1. Up to now, this has usually been done only by transparently sending the control bit for activating the output driver for the output state for control module1to/from the expander or connection module FPGA for each I/O pin to be connected (if applicable in each case).

Unlike what is proposed in the present case, all driver control bits and output states were always transmitted in a serialized manner in one direction (if necessary, via multiple channels or so-called “lanes,” cf.FIG.2), and the same procedure was carried out in the other direction for the input states. In the example inFIG.2, 7 bits each for output enable (OE) and the output state (O) of pins were transmitted via 4 data lines. “S” stands for a start bit for synchronization, which is not discussed in greater detail here. The diagram may be scaled accordingly for an arbitrary number of bits and lanes. This results in a periodic transmission of all bits for each pin. Since the bits generally change only rarely, redundant information is transmitted for the most part.

Instead of periodically transmitting all bits for all pins, it is proposed in the present case to transmit only changes to the states (input, driver activation, and output value) in both directions.FIG.3shows a corresponding schematic illustration for this purpose. Only the index and not the state of a modified bit may also be transmitted and, on the receiver side, the selected bit would be reversed, for which purpose the initial state must be fixed or transmitted at the beginning. Although proposed in the following sections, an update within one period is mot absolutely necessary, depending on the available number of channels or lanes. Updates which may occur and possibly accumulate may be buffered, e.g. in a FIFO. Alternatively, certain bits may be given preference in case of a conflict, if stricter time requirements apply to them (priority).

FIG.3shows an example of the transmission of configuration data in an example to the invention. The uppermost channel transmits clock signal8, and the channel thereunder transmits the indexes of pins. In parallel to the indexes, setpoint states (in the flow direction toward connection module3) or actual states (in the direction of data flow toward control module1) of the pins indexed in each case are transmitted on two further channels. “Out enable”12is a value which indicates whether the pin is currently able to be changed by connection module3. If the value is 0, the pin is set to “read only,” i.e., its state may be influenced only by connected peripheral device5but not by connection module3or the device driver. “Out value”13is the instantaneous value of the pin and may be zero or one or low or high. Pin index 0 is a placeholder, which indicates that no pin is being presently addressed because no changes currently exist to be communicated. The values of out enable12and out value13(control signals14) are not relevant in this state, which is illustrated by the crosshatched area. The (setpoint) value of out value13is also irrelevant if the value of out enable12is zero.

A pin having index “a” is first set to 0 driving (“out enable” high, “out value” low); at pin “b,” the driver is deactivated with some delay (“out enable” low), and, at pin “c”, the driver is activated in the following cycle and set to 1 driving. The changes for pins b and c may have been generated in the same cycle, but they must be transmitted sequentially in this diagram. A physical bit does not have to be behind each index, e.g., with index 0 as a placeholder here.

By way of example, it is assumed with reference to the table inFIG.4that serializer devices, each having a12C bus and 5 additional I/Os, are to be connected on an FMC module8, i.e., a total of 56 pins. These pins would each be connected bidirectionally, i.e., 56 bits are to be transmitted from connection module3to control module1for the input states, and 112 bits are to be transmitted in the other direction for the driver activation and output states. The bridge connection would have a total of 21 channels available, which could be used according to the table inFIG.4. This makes it possible to transmit the setpoint and actual states of a pin within one data cycle in each case, while many more reserve indexes would be present for future pins or also internal bits to be transmitted. Assuming a realistic clock rate of 100 MHz, this means that an update would be transmittable every 10 ns.

The aforementioned approaches according to the invention offer a great advantage over the existing approach: Individual changes may be communicated at a rate of 100 MHz; in the existing concept, approximately 10 cycles would be needed for the same number of lanes, i.e., one would obtain an update rate of only 10 MHz. In the typical case, the latency drops to 10 ns (instead of 50 ns otherwise), and while the jitter in the previous approach would be 10 ns to 100 ns, it would be typically 10 ns in this case. In the atypical case that multiple pins (are to) change simultaneously, the proposed system would initially have a slight disadvantage compared to the existing approach only if there are more than 10 simultaneously or accumulated changes.

It should be noted that filters may generally be implemented in both directions, from control module1to connection module3and vice versa, to prevent redundant messages and to reduce the data traffic to the absolute minimum. The main device may thus drive each request from a device driver, a certain pin, to a certain value, check it for redundancy, and generate a control message only if the particular pin is not already in the requested state. A logging via the instantaneous pin states of connection module3is necessary for this purpose. Conversely, the connection module may transmit only those pins changes to the control module which were initiated by a peripheral device and not by the connection module itself.

However, filters of this type increase the implementation complexity. In an example, the control module can generate a control message for each pin change requested by a driver, and the connection module will generate a status message for each pin change. A complete feedback of this type is advantageous, in particular on the part of connection module3, e.g., with regard to debugging or error monitoring.

The invention makes it possible to achieve a significant reduction in the latency and jitter of the state mirroring in typical applications, in particular if no frequent, (nearly) simultaneous switching of many pins takes place, while changes to individual or only a few pins may be transmitted simultaneously at a much higher frequency. The potential performance increase permits, for example, higher frequencies in buses tunneled hereby, such as12C or SPI.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.