Patent ID: 12243809

DETAILED DESCRIPTION

In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the terms “coupled, “couple”, and/or or “couples” is/are intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is electrically coupled with a second device that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and/or connections.

FIG.1shows a partial side section view of a packaged electronic device100. The packaged electronic device100includes a first subassembly101, having a first conductive plate102(e.g., copper or aluminum) with a first recess103(e.g., a slot). In one example, apart from the recess103, the first conductive plate102is a generally flat metallic structure. The first subassembly101also includes a first conductive pad104(e.g., copper or aluminum) with a top side generally coplanar with a first side105of the first conductive plate102, as well as a second conductive pad106(e.g., copper or aluminum). The bottom of the example packaged electronic device100is a planar structure to be soldered to a planar host PCB (not shown). The recess103extends into the first side105of the first conductive plate102(e.g., along the negative Z direction inFIG.1) and includes a first bottom107. The bottom of the example packaged electronic device100includes exposed portions of the first conductive plate102, the first conductive pad104, and the second conductive pad106, separated by an electrically insulating packaging material108(e.g., molded plastic). The first conductive plate102includes the first side105(e.g., the top side along the Z axis inFIG.1) as well as an opposite second side109(e.g., the bottom side inFIG.1). In one example, the first conductive plate102is a copper or aluminum die attach pad of a starting leadframe structure held in place during fabrication on an adhesive carrier (not shown) in a controlled spatial relationship to the conductive pads104and106.

A first semiconductor die110is positioned at least partially in the first recess103. The first semiconductor die110includes a first side111(e.g., the bottom side inFIG.1) that is electrically coupled to the first bottom107of the first recess103. A first conductive epoxy112is located in the first recess103between the first side111of the first semiconductor die110and the first bottom107of the first recess103. In one example, the first conductive epoxy112is a lead-free epoxy. The first conductive epoxy112electrically couples at least a portion of the first side111of the first semiconductor die110to the first bottom107of the first recess103. In one example, the first semiconductor die110includes one or more conductive features (e.g., die pads) on the first side111that is or are electrically coupled to the first bottom107of the first recess103via at least a portion of the first conductive epoxy112in the recess103. The first semiconductor die110also includes an opposite second side113(e.g., the top side inFIG.1). A first electrically insulating film114is located at least partially in the first recess103, and extends at least partially along a sidewall and a portion of the second side113of the first semiconductor die110. Some examples of materials for the first electrically insulating film114and other electrically insulating films of various implementations include dry films or liquid photo-imageable films, solder mask photo resist, polyimide materials (e.g., also photo-imageable and can remove unpolymerized material after application, for example, to make a pattern for isolation), and ABF films. A first intermediate conductive epoxy116is located on the second side113of the first semiconductor die110. In one example, the first intermediate conductive epoxy116is a lead-free epoxy. The first intermediate conductive epoxy116electrically couples the second side128of the second conductive plate122to the second side113of the first semiconductor die110.

The packaged electronic device100includes a second subassembly120located on the and above the first subassembly101. The second subassembly120includes a second conductive plate122(e.g., copper or aluminum) with a second recess123, as well as a conductive structure124that is electrically isolated from the second conductive plate122. In one example, apart from the second recess123, the second conductive plate122is a generally flat metallic structure. The second recess123is formed in a first side125(e.g., the top side inFIG.1) of the second conductive plate122. The second subassembly120also includes an electrically insulating packaging material126(e.g., molded plastic) that separates and electrically isolates the second conductive plate122from the conductive structure124. The second recess123includes a second bottom127that extends downward into the first side125toward an opposite second side128of the second conductive plate122.

A third conductive plate129electrically couples a second semiconductor die130to the conductive structure124. In one example, the third conductive plate129is a generally flat metallic structure (e.g., copper or aluminum). The second semiconductor die130includes a first side131(e.g., the bottom side inFIG.1). The first side131of the second semiconductor die130is electrically connected to the second bottom127of the second conductive plate122via a second conductive epoxy132. In one example, the second conductive epoxy132is a lead-free epoxy. The second conductive epoxy132is located in the second recess123between the first side131of the second semiconductor die130and the second bottom127of the second conductive plate122. The second semiconductor die130includes the first side131and an opposite (e.g., top) second side133electrically coupled to the third conductive plate129. A second electrically insulating film134is located at least partially in the second recess123along a sidewall of the second semiconductor die130. The third conductive plate129includes a bottom side135electrically coupled to the second side133of the second semiconductor die130. A second intermediate conductive epoxy136is located on the second side133of the second semiconductor die130to electrically couple the bottom side135of the third conductive plate129to the second side133of the second semiconductor die130. In one example, the second intermediate conductive epoxy136is a lead-free epoxy. The third conductive plate129includes a second (e.g., top) side137covered by the packaging material126.

The package structure108,126in one example is a molded plastic material that encloses the first semiconductor die110, and the second semiconductor die130. The package structure108,126includes a first side140(e.g., a bottom side inFIG.1) that exposes a portion of the second side109of the first conductive plate102, and an opposite (e.g., top) side142. The molded package structure108,126in one example is a really rectangular structure, although not a requirement of all possible implementations. Other electrically insulating materials can be used, preferably having high thermal conductivity to facilitate cooling of the first and second semiconductor dies110and130, respectively. The first conductive pad104is electrically coupled to the third conductive plate129through the first intermediate conductive epoxy116, the conductive structure124, and the second intermediate conductive epoxy136. The third conductive plate129, in turn, is electrically coupled to the second side133of the second semiconductor die130through the associated portion of the second intermediate conductive epoxy136. The structure forms an electrical connection between the second side133of the second semiconductor die and the first conductive pad104. In one example, this electrical connection provides an input voltage connection for a buck converter implementation as described further below.

In the example packaged electronic device100, the second conductive pad106is electrically coupled to the second conductive plate122through the associated portion of the first intermediate conductive epoxy116. The second conductive plate122is electrically coupled to the first side131of the second semiconductor die130through the second conductive epoxy132, and also to the second side113of the first semiconductor die110through the first intermediate conductive epoxy116. This structure forms an electrical connection between the first side131of the second semiconductor die130and the second side113of the first semiconductor die110, and the second conductive pad106. In one example, this electrical connection provides a switching node connection for the example buck converter described further below. The example packaged electronic device100also provides an electrical connection of the first bottom107of the first recess103of the first conductive plate102to the first side111of the first semiconductor die110through the first conductive epoxy112. This electrical connection provides a ground or reference voltage node connection for the example buck converter described below. In the illustrated example, the package structure108,126exposes a portion of the lower side of the first conductive pad104, and the package structure108,126exposes a portion of the lower side of the second conductive pad106. In this manner, the packaged electronic device100provides a packaged switching circuit (e.g., a stacked power module) that can be soldered to a host PCB (not shown) together with external components to form a switching DC-DC converter, such as a buck converter, a boost converter, a cuk converter, a buck-boost converter, etc.

FIG.1also shows a schematic representation of one example interconnection of the conductive features of the first conductive plate102, the first conductive pad104and the second conductive pad106to form a buck DC-DC converter150. In this example, the packaged electronic device100provides a packaged switching circuit100with a stacked configuration of NMOS high and low side switching transistors Q1and Q2, respectively. In this example, the transistors Q1and Q2are respectively located in the corresponding first and second semiconductor dies110and130and the device100connects the transistors Q1and Q2in a half bridge circuit.

The first semiconductor die110includes the first transistor Q1, with a first source terminal S1connected to a ground reference node GND of the buck converter150, a first drain terminal D1connected to a switching node SW, and a first gate terminal G1connected to a first gate control terminal151. In the packaged electronic device100ofFIG.1, the first side111(e.g., bottom) of the first semiconductor die110is electrically coupled to the first source terminal S1and to the first bottom107of the first recess103of the first conductive plate102. The lower second side109of the first conductive plate102in this example can be soldered to a circuit board ground connection of a host PCB (not shown) as schematically shown in dashed line inFIG.1. The upper second side113of the first semiconductor die110is electrically coupled to the first drain terminal D1and to the second conductive plate122through the first intermediate conductive epoxy116. The second conductive plate122forms the buck converter switching node SW and connects the first drain terminal D1to the second conductive pad106through the associated portion of the first intermediate conductive epoxy116. In one example, the second side113of the first semiconductor die110includes a second die pad or other conductive feature (not shown) that connects the first gate terminal G1to the first gate control terminal151exposed along the bottom side140of the device100, as shown inFIG.15below, to allow connection to a gate driver circuit of a host PCB (not shown).

The second semiconductor die130includes the second transistor Q2, with a second source terminal S2, a second drain terminal D2, and a second gate terminal G2. The first side131of the second semiconductor die130includes a conductive feature connected to the second source terminal S2, which is electrically coupled to the second bottom127of the second recess123of the second conductive plate122at the switching node SW through the second conductive epoxy132. The second side133of the second semiconductor die130includes a die pad or other conductive feature that is electrically coupled to the second drain terminal D2, and is connected to the first side135of the third conductive plate129through the second intermediate conductive epoxy136. In one example, the upper second side133of the second semiconductor die130also includes a second die pad or other conductive feature (not shown), that connects the second gate terminal G2through another conductive plate (not shown) to the second gate control terminal152exposed along the bottom side140of the device100, as shown inFIG.15below, to allow connection to a second gate driver circuit of a host PCB (not shown).

The packaged electronic device100provides a packaged switching circuit that includes bottom side pads and features which can be soldered to a host PCB along with the inductor L and the capacitor C to form the buck converter circuit150inFIG.1. The packaged electronic device100in this example includes the bottom side109of the first conductive plate electrically coupled to the first source S1, the first conductive pad104electrically coupled to the third conductive plate129for the input voltage node VIN connection, the second conductive pad106electrically coupled to the second conductive plate122for the switching node SW connection, as well as the third conductive pad151(FIG.15below) electrically coupled to the first gate terminal G1, and the fourth conductive pad152(FIG.15below) electrically coupled to the second gate terminal G2. The package structure108,126in this example encloses the first semiconductor die110, and the second semiconductor die130.

The first (e.g., bottom) side140of the package structure108,126exposes respective portions of the first conductive pad104, the second conductive pad106, the third conductive pad151(FIG.15below), the fourth conductive pad152(FIG.15below), and the second side109of the first conductive plate102for soldering to a host PCB (not shown). A connected host PCB in one example includes an inductor L with a first terminal connected to the switching node SW (i.e., connected to the second conductive pad106), and a second terminal connected to the output voltage node VOUT. The PCB also includes an output capacitor C with a first terminal connected to the output voltage node VOUT and a second terminal connected to an output common or reference node as schematically shown inFIG.1to create a buck DC-DC converter. A PWM controller and gate driver circuitry (not shown) provides a pulse width modulated switching control signals to the third and fourth conductive pads to operate the respective first and second transistors Q1and Q2in order to convert an input voltage VIN to a DC output voltage VOUT. In other implementations, the input voltage node, switching node and the ground reference node connections can be coupled in other circuit configurations to implement different types of DC-DC converter circuits (not shown). In another possible implementation, the package electronic device can include gate driver circuitry. In another example, the packaged electronic device includes gate driver circuits as well as a PWM circuit to generate the switching control signals according to a connected reference voltage and a feedback connection (not shown).

The various features of the example packaged electronic device100can be used to facilitate lead-free manufacturing processing for a variety of different circuit implementations. Stacked power switching circuits can be constructed with high current carrying capability (e.g., 80 A) through the use of conductive plates for interconnecting multiple semiconductor dies. Solder screen printing can be performed in fabricating the disclosed structures to facilitate manufacturability and processability. In one example, a film mask can be formed over the die110and/or130, and the associated recess103,123can be etched to provide a platform for printing or deposition of solder, epoxy, and/or an electrically insulating film solder. Various implementations can use either dry film or liquid film or combinations thereof. Dam and film encapsulants can be used in other examples.

The example packaged electronic device100ofFIG.1advantageously includes the slots or recesses103and123which provide a protected cavity for lead-free die attach to prevent the possible leakage from lead-free epoxy resin overflow or bleed out. The recesses103and123can be used in combination with lead-free conductive epoxy and/or other conductive epoxies in different implementations. The example packaged electronic device100also includes electrically insulating films114and134in combination with the recesses103and123. The recesses103and123facilitate the use of screen printing on the clip for better volume control of the conductive epoxies. In one example, the electrically insulating films114and134are formed as a thin layer of film mask to protect the die edges of the semiconductor dies110and130and prevent or mitigate epoxy overflow and associated short circuits. The electrically insulating films114and134also provide stress relief to the corner of die attach material in certain examples.

In addition, disclosed example packaged electronic device100includes unbent or flat conductive plates or clips, and thus reduce tooling and production costs associated with formed or bent clips. In addition, flat conductive plates facilitate reliability of the packaged electronic device100, with reduced clip tilting to facilitate improved manufacturing yield. The flat conductive plates also facilitate planar assembly with uniform BLT and less tilting compared with power stack fabrication using clips. The example packaged electronic device100ofFIG.1includes three flat conductive plates102,122and129, which reduces manufacturing cost and complexity. In another example, the second conductive plate122can be a formed structure that extends downward on the right inFIG.1, with a lower surface generally coplanar with the bottom140of the packaged electronic device100, and the second conductive pad106is omitted. In another example, the third conductive plate129can be a formed structure that extends downward on the left inFIG.1, with a lower surface generally coplanar with the bottom140of the packaged electronic device100, and the first conductive pad104is omitted.

FIGS.2-14illustrate an example fabrication process for manufacturing a packaged electronic device.FIG.2shows an example method200, andFIGS.3-14illustrate the example packaged electronic device100ofFIG.1undergoing fabrication according to the method200. In the example method200, the first subassembly101ofFIG.1is fabricated at202-214, and the second subassembly120is separately fabricated at216-224, where the first and second subassembly processing can be performed independently, including concurrently. In other possible implementations, the fabrication of the second subassembly120is performed following fabrication of the first subassembly101in a continuous process (not shown).

The example method200begins with a starting leadframe structure.FIG.3shows one suitable example of a starting lead frame104made through stamping or other suitable fabrication processes using a suitable conductive material, such as copper. The example leadframe structure includes separated conductive structures102(lead frame die attach pad, referred to herein as the first conductive plate),104(first conductive pad) and106(second conductive pad). The conductive structures102,104and106in one example are located in a predetermined spatial relationship to one another, for example, on an adhesive carrier tape (not shown). The method200includes pre-molding the lead frame structure at202.FIG.4shows one suitable example, in which a molding process400is performed that forms the electrically insulating (e.g., nonconductive) packaging material108(e.g., molded plastic) that extends between the first conductive pad104and a first end of the first conductive plate102, as well as between a second opposite end of the first conductive plate102and the second conductive pad106. With the lead frame pre-molded as shown inFIG.4, any previously used adhesive carrier tape can be removed for further processing.

The method200continues at204inFIG.2with plating the lead frame structure and forming a first recess in the first conductive plate. Any suitable plating process can be used to form a desired plated surface on the pre-molded lead frame structure at204. In another example, the plating process is omitted, and the first recess is formed at204.FIG.5shows one suitable example, in which a first etching process500is performed that etches the first recess103in the first side105of the first conductive plate102using a first mask502. Any suitable etch process500and etching mask502can be used to form the first recess103. In the illustrated example, the first bottom107of the first recess103is generally planar and the side walls of the recess103are generally vertical (e.g., along the Z axis inFIG.5), although these characteristics are not strict requirements of all possible implementations. A generally flat bottom107facilitates subsequent processing to form (e.g., dispense, print, silkscreen, etc.) a conductive epoxy within the recess103and die attach processing to locate a semiconductor die at least partially within the recess103on the previously dispensed conductive epoxy.

The method200continues at206with forming a conductive epoxy on the first bottom of the first recess in the first conductive plate, followed by a die attach step at208to attach the first semiconductor die to the first conductive epoxy in the bottom of the first recess.FIG.6shows one suitable example, in which a printing and die attach process600is performed that prints the first conductive epoxy112on the first bottom107of the first recess103. Any suitable printing equipment and techniques can be used. In another example, a dispensing process is used to form the conductive epoxy112on the first bottom107of the first recess103. In another example, a screening process is used to form the conductive epoxy112on the first bottom107of the first recess103. The example process600inFIG.6also includes attaching the first side111of the first semiconductor die110to the first conductive epoxy112(at208inFIG.2). In one example, the processing600inFIG.6also includes a first thermal process that reflows the first conductive epoxy112(e.g., at210inFIG.2) after attaching the first side111of the first semiconductor die110to the first conductive epoxy112at208. In one example, the first conductive epoxy112is formed in a semi-solid state through dispensing, printing, silk screening, etc. Subsequent thermal processing at210in one example initially reflows the formed first conductive epoxy material112and the heating and/or subsequent cooling of the material112cures the first conductive epoxy112to a solid state that mechanically and electrically connects at least a portion of the lower first side111of the first semiconductor die110to the first conductive plate102.

As previously discussed, the first side111of the first semiconductor die110can include a first conductive feature electrically connected to the first transistor source S1(FIG.1), as well as a second conductive feature electrically connected to the first gate terminal G1. In this example, the die attach processing can include contemporaneous dispensing, printing, etc. of the first conductive epoxy112in separate areas to accommodate electrically separated connections for the first source terminal S1and the first gate terminal G1, such as forming a first portion of the first conductive epoxy112on a corresponding conductive pad151(e.g.,FIGS.1and15) for the first gate terminal connection, and forming a second portion of the first conductive epoxy112on at least a portion of the first bottom107of the first recess103of the first conductive plate102for the first source terminal connection as shown inFIGS.3-14. In one example, the thermal process cures the first conductive epoxy112. The die attach processing at208and210electrically couples at least a portion of the first side111of the first semiconductor die110to the first bottom107of the first recess103of the first conductive plate102.

The method200continues at212with forming a first insulating film on portions of the first conductive plate and the first semiconductor die. Any suitable material formation processing can be used at212, for example, printing, dispensing, silk screening, etc.FIG.7shows one example, in which a first deposition process, such as a printing process700, is performed. The printing process700deposits the first electrically insulating film114at least partially in the first recess103along the sidewalls of the first semiconductor die110and along a laterally peripheral portion of the upper second side113of the first semiconductor die110. In another example, the printing process700does not deposit the first electrically insulating film114on the upper second side113of the first semiconductor die110. The illustrated example advantageously coats the peripheral edge of the upper second side113of the first semiconductor die110, and helps to protect the die edges and prevent or mitigate epoxy overflow and associated short circuits in subsequent processing. In the example ofFIG.7, moreover, the process700forms the first electrically insulating film114on the peripheral edges of the second side113, and leaves one or more upper conductive features of the first semiconductor die110exposed for subsequent electrical connection (e.g., the first drain terminal D1inFIG.1).

At214inFIG.2, the method200further includes forming a first intermediate conductive epoxy on the upper second side of the first semiconductor die. Any suitable material formation processing can be used at214, for example, printing, dispensing, silk screening, etc.FIG.8shows one example, in which a dispensing process800is performed that dispenses the first intermediate conductive epoxy116on select portions of the second side113of the first semiconductor die110. In particular, the top second side113in one example includes a conductive feature electrically connected to the first drain terminal D1, and may include a separate conductive feature electrically connected to the first gate terminal G1of the first transistor Q1of the first semiconductor die110. Where separate conductive terminals are formed on the second side113, the dispensing process800forms corresponding separate portions of the first intermediate conductive epoxy116thereon. In the example ofFIG.8, the dispensing process800also dispenses separate portions of the first intermediate conductive epoxy116on the respective first and second conductive pads104and106for subsequent electrical connection.

The example method200continues at216-224with separate processing to form the second subassembly120shown inFIG.1. In this example, the second subassembly fabrication processing begins at216with plating and etching a second recess in a second conductive plate. Any suitable plating process can be used to form a desired plated surface on the pre-molded lead frame structure at216. In another example, the plating process is omitted, and the second recess is formed at216.FIG.9shows one suitable example, starting with a second conductive plate122and the conductive structure124spaced from one another in a predetermined spatial relationship, for example, on an adhesive carrier tape (not shown).

In the example ofFIG.9, a second etching process900is performed that etches the second recess123in the upper first side125of the second conductive plate122using a second etch mask902. Any suitable etch process900and etching mask902can be used to form the second recess123at216. In the illustrated example, the second bottom127of the second recess123is generally planar and the side walls of the second recess123are generally vertical (e.g., along the Z axis inFIG.9), although these characteristics are not strict requirements of all possible implementations. A generally flat bottom127facilitates subsequent processing to form (e.g., dispense, print, silkscreen, etc.) a second conductive epoxy within the second recess123and die attach processing to locate a second semiconductor die at least partially within the recess123on the previously dispensed conductive epoxy.

At218inFIG.2, the method200continues with forming a second conductive epoxy on the second bottom of the second recess. After the second conductive epoxy is formed, the method200includes attaching the first side of the second semiconductor die to the second conductive epoxy at220.FIG.10shows one example, in which a printing and die attach process1000is performed that prints the second conductive epoxy132on at least a portion of the second bottom127of the second recess123. Any suitable printing equipment and techniques can be used at218. In another example, a dispensing process is used to form the second conductive epoxy132on the second bottom127of the second recess123. In another example, a screening process is used to form the second conductive epoxy132on the second bottom127of the second recess123. The example process1000inFIG.10also includes attaching the first side131of the second semiconductor die130to the second conductive epoxy132(at220inFIG.2). In one example, the processing1000inFIG.10also includes a second thermal process that reflows the second conductive epoxy132(e.g., at222inFIG.2) after attaching the first side131of the second semiconductor die130to the second conductive epoxy132at220. In one example, the second conductive epoxy132is formed in a semi-solid state through dispensing, printing, silk screening, etc. Subsequent thermal processing at222in one example initially reflows the formed second conductive epoxy132and the heating and/or subsequent cooling of the material132cures the second conductive epoxy132to a solid state that mechanically and electrically connects at least a portion of the lower first side131of the second semiconductor die130to the second conductive plate122.

In one example, the first side131of the second semiconductor die130includes a conductive feature electrically connected to the second transistor source terminal S2(FIG.1), as well as another conductive feature electrically connected to the second gate terminal G2. In this example, the die attach processing can include contemporaneous dispensing, printing, etc. of the second conductive epoxy132in separate areas to accommodate electrically separated connections for the second source terminal S2and the second gate terminal G2, such as forming a first portion of the second conductive epoxy132on a corresponding conductive pad152(e.g.,FIGS.1and15) for the second gate terminal connection, and forming a second portion of the second conductive epoxy132on at least a portion of the second bottom127of the second recess123of the second conductive plate122for the second source terminal connection as shown inFIGS.3-14. In one example, the thermal process at222cures the second conductive epoxy132. The die attach processing at220and222electrically couples at least a portion of the first side131of the second semiconductor die130to the second bottom127of the second recess123of the second conductive plate122.

The method200continues at224with forming a second insulating film on portions of the second conductive plate and the second semiconductor die. Any suitable material formation processing can be used at224, for example, printing, dispensing, silk screening, etc.FIG.11shows one example, in which a second deposition process, such as a printing process1100, is performed. The printing process1100deposits the second electrically insulating film134at least partially in the second recess123along the sidewalls of the second semiconductor die130and along a laterally peripheral portion of the upper second side133of the second semiconductor die130. In another example, the printing process1100does not deposit the second electrically insulating film134on the upper second side133of the second semiconductor die130. The illustrated example advantageously coats the peripheral edge of the upper second side133of the second semiconductor die130, and helps to protect the die edges and prevent or mitigate epoxy overflow and associated short circuits in subsequent processing. In the example ofFIG.11, moreover, the process1100forms the second electrically insulating film134on the peripheral edges of the second side133, and leaves one or more upper conductive features of the second semiconductor die130exposed for subsequent electrical connection (e.g., the second drain terminal D2inFIG.1).

After the first and second subassemblies101and120are completed, the second subassembly120is assembled onto the first subassembly101at226inFIG.2.FIG.12shows one example, in which an attachment process1200is performed (e.g., mechanical robotic pick and place) that attaches the second side128of the second conductive plate122to the first intermediate conductive epoxy116. At228, one example further includes performing a third thermal process that reflows and cures the first intermediate conductive epoxy116to complete the electrical coupling of the second side128of the second conductive plate122to the second side113of the first semiconductor die110at the switching node SW.

The method200at230further includes forming the second intermediate conductive epoxy136on the upper second side133of the second semiconductor die130.FIG.13shows an example, in which a dispensing process1300is performed that dispenses the second intermediate conductive epoxy136on the upper second side133of the second semiconductor die130. At232, the method200further includes attaching the lower first side135of the third conductive plate129to the second intermediate conductive epoxy136to electrically couple the lower first side135of the third conductive plate129to the upper second side133of the second semiconductor die130, as shown inFIG.13. The method200continues at234with performing a fourth thermal process that reflows the second intermediate conductive epoxy136. Wire bonding (not shown) can optionally be performed at236, and a molding process is performed at238.FIG.14shows one example, in which a molding process1400is performed that forms the package structure126. The final molded package material126and the pre-molded material108form a molded package structure that encloses the first semiconductor die110, and the second semiconductor die130, and includes the lower side140that exposes a portion of the second side109of the first conductive plate102and the conductive pads104and106as shown inFIG.14.

FIG.15shows a bottom view of the finished packaged electronic device100, following package singulation at240inFIG.2. The finished device100includes solderable conductive pads or features102,104,106,151and152separated from one another by the pre-molded insulating material108. As schematically shown inFIG.1, the example device provides a stacked power circuit in a single package to facilitate construction of a buck converter or other switching circuit with two transistors connected in a half-bridge configuration.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.