Patent ID: 12222390

DETAILED DESCRIPTION

Certain terms have been used throughout this description and claims to refer to particular system components. As one skilled in the art will appreciate, different parties may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In this disclosure and claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” is intended to mean “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.

Synchronizer circuits employ flip-flops to synchronize an asynchronous input signal to a system clock. As device geometry shrinks, flip-flops become more susceptible to soft errors caused by cosmic radiation, power supply noise, or other external events. Smaller device geometries also allow for an increase in device density with a corresponding increase in asynchronous clocking. Soft errors in asynchronous clocking circuitry can produce a variety of faults in a system. In the past, the limited nature of asynchronous clocking allowed soft errors in synchronization flip-flops to be ignored, but as device geometries shrink, the errors in synchronization become more significant, especially in safety critical applications that require protection from soft errors.

The synchronization circuit disclosed herein detects soft errors in synchronization flip-flops and allows a synchronizer output to change state only after any soft errors are resolved. Implementations of the synchronization circuit compare the outputs of two parallel synchronizers. If the two outputs are the same logic level, then the output of one of the synchronizers is provided to be the current output of the synchronization circuit. If the two outputs are different logic levels, then a previously captured output of the synchronization circuit is provided to be the current output of the synchronization circuit. Thus, implementations of the synchronizer circuit reduce or eliminate the errors in the output of the synchronizer circuit caused by soft errors in the synchronizer flip-flops.

FIG.1shows a block diagram for an example synchronization circuit100in accordance with the present disclosure. The synchronization circuit100includes a synchronizer102, a synchronizer104, and selection circuitry105. Some implementations of the100also include soft error detection circuitry112, and soft error testing circuitry114. The synchronization circuit100includes an input terminal124for receiving an asynchronous input signal, a clock terminal128for receiving a synchronization clock signal; and an output terminal126for providing a synchronized output signal to circuitry external to the synchronization circuit100. The input terminal124is coupled to the synchronizer102and the synchronizer104.

The synchronizer102and the synchronizer104are connected in parallel, such that each of the synchronizer102and the synchronizer104independently synchronizes the asynchronous input signal received at the input terminal124to the clock signal received at the clock terminal128. The synchronizer102includes one or more flip-flops116to synchronize the asynchronous input signal received at the input terminal124to the clock signal received at the clock terminal128. The flip-flop116includes an input terminal116A, a clock terminal116B, and an output terminal116C. The input terminal116A is coupled to the input terminal124, and the clock terminal116B is coupled to the clock terminal128. Similarly, the synchronizer104includes one or more flip-flops117to synchronize the asynchronous input signal received at the input terminal124to the clock signal received at the clock terminal128. The flip-flop117includes an input terminal117A, a clock terminal117B, and an output terminal117C. The input terminal117A is coupled to the input terminal124, and the clock terminal117B is coupled to the clock terminal128.

The selection circuitry105is coupled to the synchronizer102and the synchronizer104. The selection circuitry105includes comparison circuitry106, a multiplexer108, and storage circuitry110. The comparison circuitry106compares the output signals generated by synchronizer102and the synchronizer104, and provides a result of the comparison to the multiplexer108. In some implementations, the selection circuitry105may include an exclusive-OR circuit118(or other comparison circuitry, e.g., exclusive-NOR, etc.) that compares the output signals generated by synchronizer102and the synchronizer104. Some implementations of the comparison circuitry106include other circuitry (e.g., exclusive-NOR circuitry) to compare the output signals generated by synchronizer102and the synchronizer104. The exclusive-OR circuit118includes an input terminal118A, an input terminal input terminal118B, and an output terminal118C. The input terminal118A is coupled to the output terminal116C, and the input terminal118B is coupled to the output terminal117C.

The multiplexer108includes an input terminal108A, an input terminal108B, a control terminal108C, and an output terminal108D. The control terminal108C is coupled to the output terminal118C, the input terminal108A is coupled to an output of the synchronizer102or the synchronizer104. The input terminal108B is coupled to the storage circuitry110, and the output terminal108D is coupled to the storage circuitry110. The multiplexer108routes the signal at the input terminal108A to the output terminal108D if the signal at the control terminal108C indicates that the outputs of the synchronizer102and the synchronizer104are the same, and routes the signal at the input terminal108B to the output terminal108D if the signal at the control terminal108C indicates that the outputs of the synchronizer102and the synchronizer104are not the same.

The storage circuitry110stores the synchronized output signal produced by the multiplexer108. The storage circuitry110includes a flip-flop122or other storage circuit, and soft-error protection circuitry120coupled to the flip-flop122. The flip-flop122includes an input terminal122A and an output terminal122B. The input terminal122A is coupled to the output terminal108D, and the output terminal122B is coupled to the input terminal108B. The soft-error protection circuitry120protects the flip-flop122from soft errors. For example, the soft-error protection circuitry120may include error correction code (ECC) circuitry that corrects the output of the flip-flop122if a soft error occurs in the flip-flop122.

The synchronization circuit100mitigates the effects of soft errors in the synchronizer102and the synchronizer104by producing, at the output terminal126, the output of the synchronizer104if the output of the synchronizer102is the same as the output of the synchronizer104, and producing, at the output terminal126, a stored prior output of the multiplexer108if the output of the synchronizer102is not the same as the output of the synchronizer104. If a soft error changes the output of the one of the synchronizer102or the synchronizer104, the selection circuitry105provides the stored prior output of the multiplexer108at the output terminal126.

The soft error detection circuitry112is coupled to the synchronizer102and the synchronizer104. The soft error detection circuitry112monitors the output of the synchronizer102and the synchronizer104to identify the presence of a soft error in the synchronizer102or the synchronizer104. If the soft error detection circuitry112identifies a soft error in the output of the synchronizer102or the output of the synchronizer104, the soft error detection circuitry112asserts an output to notify circuitry external to the synchronization circuit100of the soft error.

The soft error testing circuitry114is coupled to the soft error detection circuitry112. The soft error testing circuitry114generates signals to test soft error detection in the soft error detection circuitry112. The soft error testing circuitry114generates signal sequences that replicate the outputs of the synchronizer102and the synchronizer104when a soft error occurs in the synchronizer102or the synchronizer104. The soft error detection circuitry112processes the signals generated by the soft error testing circuitry114to test soft error detection.

FIG.2shows a block diagram for an example soft error detection circuit200in accordance with the present disclosure. The soft error detection circuit200is an implementation of the soft error detection circuitry112. The soft error detection circuit200includes an input multiplexer202, comparison circuitry204, and sequence storage206.

The input multiplexer202selects either the outputs of the synchronizer102and synchronizer104, or the output signals produced by the soft error testing circuitry114to process for detection of soft errors. For example, to test the soft error detection circuit200, the input multiplexer202selects the output signals produced by the soft error testing circuitry114, and in normal operating conditions the input multiplexer202selects the outputs of the synchronizer102and the synchronizer104.

In some implementations of the soft error detection circuit200, the sequence storage206stores signal sequences produced by the synchronizer102and synchronizer104when no soft error has occurred. For example, if the asynchronous input data changes from logic “0” (0) to logic “1” (1), then the signals at the output terminal116C and the output terminal117C will change as shown in one of Tables 1-3 below if no soft error occurs:

TABLE 1outputoutputterminalterminal116C117C1stclock002ndclock11

TABLE 2outputoutputterminalterminal116C117C1stclock002ndclock013rdclock11

TABLE 3outputoutputterminalterminal116C117C1stclock002ndclock103rdclock11

If the asynchronous input data changes from 1 to 0, then the signals at the output terminal116C and the output terminal117C will change as shown in one of Tables 4-6 below if no soft error occurs:

TABLE 4outputoutputterminalterminal116C117C1stclock112ndclock00

TABLE 5outputoutputterminalterminal116C117C1stclock112ndclock103rdclock00

TABLE 6outputoutputterminalterminal116C117C1stclock112ndclock013rdclock00

The comparison circuitry204may compare the data sequence received from the input multiplexer202to the data sequences stored in the sequence storage206, and if the data sequence received from the input multiplexer202does not match one of the data sequences stored in the sequence storage206, then the comparison circuitry204may indicate that a soft error has been detected.

In some implementations of the soft error detection circuit200, the sequence storage206stores signal sequences produced by the synchronizer102and synchronizer104when a soft error occurs. If a soft error occurs in the synchronizer102or the synchronizer104, then the signals at the output terminal116C and the output terminal117C may change as shown in one of Tables 7-10.

TABLE 7outputoutputterminalterminal116C117C1stclock002ndclock013rdclock00

TABLE 8outputoutputterminalterminal116C117C1stclock002ndclock103rdclock00

TABLE 9outputoutputterminalterminal116C117C1stclock112ndclock013rdclock11

TABLE 10outputoutputterminalterminal116C117C1stclock112ndclock103rdclock11

The comparison circuitry204may compare the data sequence received from the input multiplexer202to the data sequences stored in the sequence storage206, and if the data sequence received from the input multiplexer202matches one of the data sequences stored in the sequence storage206, then the comparison circuitry204may indicate that a soft error has been detected.

In some implementations of the soft error detection circuit200, the comparison circuitry204and the sequence storage206may implemented in a state machine that monitors the signals received from the input multiplexer202for sequences that indicate the presence of a soft error.

FIG.3shows a block diagram for an example toggle occupancy circuit300that uses synchronization circuits in accordance with the present disclosure. The toggle occupancy circuit300includes synchronization circuit302and synchronization circuit304. The synchronization circuit302and the synchronization circuit304are implementations of the synchronization circuit100. In the toggle occupancy circuit300, the source circuitry issues a S_PUSH event that causes the flip-flop306to toggle. The flip-flop306may include parity or ECC circuitry that protects against soft errors. The synchronization circuit302synchronizes the output of the flip-flop306to DCLK and the destination circuitry can use data associated with the occupancy cell. When the destination circuitry issues a D PUSH event, the flip-flop308toggles. The flip-flop308may include parity or ECC circuitry that protects against soft errors. The synchronization circuit304synchronizes the output of the flip-flop308to SCLK and the source circuitry regains ownership of the occupancy cell. Use of the synchronization circuit302and the synchronization circuit304reduces or eliminates faults caused by soft errors in signal synchronization between the source and destination circuitry.

FIG.4shows a flow diagram for a method400for synchronizing a signal in accordance with the present disclosure. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some implementations may perform only some of the actions shown.

In block402, the soft error detection circuitry112is tested to ensure that the presence of soft errors in the output of the synchronizer102and the synchronizer104can be identified. Details of the testing are provided in the method600.

In block404, the synchronized signal value provided at the output terminal108D of the multiplexer108is stored in the storage circuitry110.

In block406, the synchronizer102synchronizes the asynchronous signal received at the input terminal124to the clock signal received at the clock terminal128.

In block408, operating in parallel with the synchronizer102, the synchronizer104synchronizes the asynchronous signal received at the input terminal124to the clock signal received at the clock terminal128.

In block410, the soft error testing circuitry114analyzes the output of the synchronizer102and the synchronizer104to determine whether a soft error has occurred in the synchronizer102or the synchronizer104. Details of the soft error detection are provided in the method500.

In block412, the comparison circuitry106compares the outputs of the synchronizer102and synchronizer104.

If, in block414, the output of the synchronizer102is the same as the output of the synchronizer104, then the output of one of the synchronizer102or the synchronizer104is provided as the synchronized output value at the output terminal126in block418.

If, in block414, the output of the synchronizer102is not the same as the output of the synchronizer104, then the value stored in the storage circuitry110(i.e., a prior synchronized output value present at the output terminal126) is provided as the synchronized output value at the output terminal126in block416.

FIG.5shows a flow diagram for a method500for detecting a soft error in a synchronizer in accordance with the present disclosure. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some implementations may perform only some of the actions shown.

In block502, the sequence storage206generates data sequences that correspond to operation of the synchronizer102and the synchronizer104when no soft error has occurred (see Tables 1-6).

In block504, the input multiplexer202is set to provide the outputs of the synchronizer102and the synchronizer104to the comparison circuitry204. The comparison circuitry204compares the data sequences generated by the sequence storage206to the data sequences received from the synchronizer102and the synchronizer104.

In block506, if the data sequence received from the synchronizer102and the synchronizer104is same as one of the data sequences provided by the sequence storage206, then the comparison circuitry204indicates that no soft error is present in block508.

In block506, if the data sequence received from the synchronizer102and the synchronizer104is not same as one of the data sequences provided by the sequence storage206, then the comparison circuitry204indicates that a soft error is present in block510.

FIG.6shows a flow diagram for a method600for testing a soft error detection circuit in accordance with the present disclosure. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some implementations may perform only some of the actions shown.

In block602, the input multiplexer202is set to provide the outputs of the soft error testing circuitry114to the comparison circuitry204. The soft error testing circuitry114generates a data sequence indicative of a soft error in the synchronizer102or the synchronizer104(see Tables 7-10). The data sequence generated by the soft error testing circuitry114is provided to the soft error detection circuitry112and the comparison circuitry204compares the data sequence received from the soft error testing circuitry114to the data sequences provided by the sequence storage206.

In block604, if the comparison circuitry204indicates that a soft error is present in the data received from the soft error testing circuitry114, then in block606, the soft error detection circuitry112is operating properly.

In block604, if the comparison circuitry204indicates that no soft error is present in the data received from the soft error testing circuitry114, then in block608, the soft error detection circuitry112is not operating properly.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.