Patent ID: 12232425

DETAILED DESCRIPTION

Referring toFIGS.1-5,FIGS.1-5illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. As shown inFIG.1, a substrate12made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs). A MRAM region14and a logic region16are defined on the substrate12, in which the MRAM region14further includes a plurality of array regions including an array region102and an array region104.

Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and interlayer dielectric (ILD) layer18could also be formed on top of the substrate12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain region, spacer, epitaxial layer, and contact etch stop layer (CESL). The ILD layer18could be formed on the substrate12to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer18to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Next, metal interconnect structures20,22are sequentially formed on the ILD layer18on the MRAM region14and the logic region16to electrically connect the aforementioned contact plugs, in which the metal interconnect structure20includes an inter-metal dielectric (IMD) layer24and metal interconnections26embedded in the IMD layer24, and the metal interconnect structure22includes a stop layer28, an IMD layer30, and metal interconnections32embedded in the stop layer28and the IMD layer30.

In this embodiment, each of the metal interconnections26from the metal interconnect structure20preferably includes a trench conductor and the metal interconnection32from the metal interconnect structure22on the MRAM region14includes a via conductor. Preferably, each of the metal interconnections26,32from the metal interconnect structures20,22could be embedded within the IMD layers24,30and/or stop layer28according to a single damascene process or dual damascene process. For instance, each of the metal interconnections26,32could further include a barrier layer34and a metal layer36, in which the barrier layer34could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer36could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the metal layers36in the metal interconnections26are preferably made of copper, the metal layer36in the metal interconnections32are made of tungsten, the IMD layers24,30are preferably made of silicon oxide such as tetraethyl orthosilicate (TEOS), and the stop layer28is preferably made of nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof.

Next, a bottom electrode42, a MTJ stack38or stack structure, a top electrode50, and a patterned mask (not shown) are formed on the metal interconnect structure22. In this embodiment, the formation of the MTJ stack38could be accomplished by sequentially depositing a pinned layer44, a barrier layer46, and a free layer48on the bottom electrode42. In this embodiment, the bottom electrode layer42and the top electrode layer50are preferably made of conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or combination thereof. The pinned layer44could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB) or cobalt-iron (CoFe). Alternatively, the pinned layer44could also be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer44is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer46could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer48could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer48could be altered freely depending on the influence of outside magnetic field.

Next, as shown inFIG.2, one or more etching process is conducted by using the patterned mask as mask to remove part of the top electrode50, part of the MTJ stack38, part of the bottom electrode42, and part of the IMD layer30to form MTJs52on the MRAM region14. It should be noted that a reactive ion etching (RIE) and/or an ion beam etching (IBE) process is conducted to remove the top electrode50, MTJ stack38, bottom electrode42, and the IMD layer30in this embodiment for forming the MTJs52. Due to the characteristics of the IBE process, the top surface of the remaining IMD layer30is slightly lower than the top surface of the metal interconnections32after the IBE process and the top surface of the IMD layer30also reveals a curve or an arc. Moreover, as the IBE process is conducted to remove part of the IMD layer30, part of the metal interconnection32is removed at the same time to form inclined sidewalls on the surface of the metal interconnection32immediately adjacent to the MTJs52.

It should also be noted that the top electrodes50disposed on the array regions102,104are preferably made of TiN and it would be desirable to adjust the nitrogen to titanium (N/Ti) ratio in the top electrodes50before or after the aforementioned patterning process so that the top electrode50on the array region102and the top electrode50on the array region104would have different nitrogen to titanium (N/Ti) ratios. For instance, it would be desirable to form a patterned mask (not show) on the array region104before or after patterning the MTJ stack38for forming the MTJs52, conduct an ion implantation process to implant nitrogen ions into the array region102or inject a nitrogen-containing gas into the array region102, and then remove the patterned mask on the array region104so that the N/Ti ratio of the top electrode50on the array region102would be substantially higher than the N/Ti ratio of the top electrode50on the array region104. In this embodiment, the N/Ti ratio of the top electrode50on the array region102is between 0.3 to 1.5 and most preferably at 1.09 while the N/Ti ratio of the top electrode50on the array region104is between 0.3 to 1.5 and most preferably at 0.99.

According to a first embodiment of the present invention, the top electrode50having higher nitrogen to titanium (N/Ti) ratio on the array region102could generate lower tunnel magnetoresistance (TMR) and such combination would be more suitable for memory blocks requiring higher operating speed in a MRAM unit. On the other hand, the top electrode50having lower N/Ti ratio on the array region104would generate higher TMR which would be more suitable for memory blocks requiring higher retention in a MRAM unit.

Next, a cap layer56is formed on the MTJs52while covering the surface of the IMD layer30. In this embodiment, the cap layer56preferably includes silicon nitride, but could also include other dielectric material including but not limited to for example silicon oxide, silicon oxynitride (SiON), or silicon carbon nitride (SiCN).

Next, as shown inFIG.3, an etching back process is conducted to remove part of the cap layer56for forming spacers58,60on sidewalls of each of the MTJs52and an inter-metal dielectric (IMD) layer62is formed on the MTJs52and the IMD layer30on the logic region16. In this embodiment, the IMD layer62preferably include an ultra low-k (ULK) dielectric layer including but not limited to for example porous material or silicon oxycarbide (SiOC) or carbon doped silicon oxide (SiOCH). Since the top surface of the IMD layer62on the MRAM region14could be slightly higher than the top surface of the IMD layer62on the logic region16at this stage, a selective planarizing process such as chemical mechanical polishing (CMP) is conducted to remove part of the IMD layer62on the MRAM region14and logic region16without exposing the top surfaces of the top electrodes50so that the top surface of the IMD layer62on the MRAM region14is even with the top surface of the IMD layer62on the logic region16.

Next, as shown inFIG.4, a pattern transfer process is conducted by using a patterned mask (not shown) to remove part of the IMD layer62, part of the IMD layer30, and part of the stop layer28on the logic region16to form a contact hole (not shown) exposing the metal interconnection26underneath and conductive materials are deposited into the contact hole afterwards. For instance, a barrier layer selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and metal layer selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP) could be deposited into the contact hole, and a planarizing process such as CMP could be conducted to remove part of the conductive materials including the aforementioned barrier layer and metal layer to form a contact plug or metal interconnection70in the contact hole electrically connecting the metal interconnection26.

Next, as shown inFIG.5, a stop layer72is formed on the MRAM region14and logic region16to cover the IMD layer62and metal interconnection70, an IMD layer74is formed on the stop layer72, and one or more photo-etching process is conducted to remove part of the 1 MB layer74, part of the stop layer72, and part of the IMD layer62on the MRAM region14and logic region16to form contact holes (not shown). Next, conductive materials are deposited into each of the contact holes and a planarizing process such as CMP is conducted to form metal interconnections76connecting the MTJs52and metal interconnection70underneath, in which the metal interconnections76on the array regions102and104directly contact the top electrodes50underneath while the metal interconnection76on the logic region16directly contacts the metal interconnection70on the lower level. Next, another stop layer78is formed on the 1 MB layer74to cover the metal interconnections76.

In this embodiment, the stop layers72and78could be made of same or different materials, in which the two layers72,78could all include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof. Similar to the metal interconnections formed previously, each of the metal interconnections76could be formed in the IMD layer74through a single damascene or dual damascene process. For instance, each of the metal interconnections76could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

Referring toFIG.6,FIG.6illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG.6, in contrast to the spacers58,60on the array region102and the spacers58,60on the array region104having same thickness in the aforementioned embodiment, it would also be desirable to adjust the thickness of the spacers58,60on each of the array regions102,104during the formation of the spacers58,60inFIG.3so that the spacers58,60on the array region102and the spacers58,60on the array region104would have different thicknesses. For instance, it would be desirable to first form a patterned mask (not shown) on the array region102after the spacers58,60are formed and then conduct an etching process to remove part of the spacers58,60on the array region104so that the thickness of each of the spacers58,60on the array region104becomes slightly less than the thickness of each of the spacers58,60on the array region102. Next, the patterned mask is removed and the IMD layer62is formed on the spacers58,60and metal interconnections are formed thereafter.

It should be noted that the thickness of the spacers58,60on the array regions102,104specifically refers to the width of each of the spacers58,60extending along the direction of the top surface of the substrate12or top surface of the top electrodes50, in which the thickness or width of each of the spacers58,60on the array region104is less than the thickness or width of each of the spacers58,60on the array region102. Preferably, the thickness or width of each of the spacers58,60on the array region102is twice or even three times thicker than the thickness or width of each of the spacers58,60on the array region104. Specifically, the thickness of each of the spacers58,60on the regions102,104is between 50-400 Angstroms, in which the thickness or width of each of the spacers58,60on the array region102is between 330-400 Angstroms or most preferably 365 Angstroms while the thickness or width of each of the spacers58,60on the array region104is between 60-120 Angstroms or most preferably 90 Angstroms.

Preferably, the top surfaces of the spacers58,60and the top electrode50on the array region102are coplanar, the top surfaces of the spacers58,60and the top electrode50on the array region104are coplanar, and the top surfaces of the spacers58,60on the array regions102and104are coplanar. According to a second embodiment of the present invention, the top electrode50having thicker spacers58,60on the array region102could generate lower tunnel magnetoresistance (TMR) and such combination would be more suitable for memory blocks requiring higher operating speed in a MRAM unit. On the other hand, the top electrode50having thinner spacers58,60on the array region104would generate higher TMR which would be more suitable for memory blocks requiring higher retention in a MRAM unit.

Referring toFIG.7,FIG.7illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG.7, in contrast to only having top electrode50on the array region102and the top electrode50on the array region104with different N/Ti ratios as shown inFIG.5or only having the spacers58,60on the array regions102,104with different thicknesses as shown inFIG.6, it would also be desirable to combine the embodiments shown inFIGS.5-6so that not only the top electrodes50on the array regions102,104having different N/Ti ratios but also the spacers58,60on the array regions102,104having different thicknesses or widths, which is also within the scope of the present invention.

Typically, critical dimension (CD) or perpendicular magnetic anisotropy (PMA) on different array regions of current MRAM devices could be changed to adjust the coercivity of free layer so that different array regions or memory blocks could be used for higher speed or higher retention applications as well as achieving fusions chips having hybrid memory functions. According to a first embodiment of the present invention, it would be desirable to adjust nitrogen to titanium (N/Ti) ratio of top electrodes on different array regions so that the MTJ with top electrode having higher N/Ti ratio could generate lower tunnel magnetoresistance (TMR) for memory blocks requiring higher operating speed while the MTJ with top electrode having lower N/Ti ratio could generate higher TMR for memory blocks requiring higher retention.

Moreover, according to a second embodiment of the present invention, it would be desirable to adjust the thickness or widths of the spacers on different array regions so that the array region or MTJ with thicker spacers on adjacent two sides could generate lower TMR for memory blocks requiring higher operating speed while the array region or MTJ with thinner spacers on adjacent two sides could generate higher TMR for memory blocks requiring higher retention.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.