Patent ID: 12199131

DETAILED DESCRIPTION

The same elements have been designated with the same reference numerals in the different drawings. In particular, the structural and/or functional elements common to the different embodiments may be designated with the same reference numerals and may have identical structural, dimensional, and material properties.

For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the forming of the photodetection areas and of the transistors for controlling the pixels of the described sensors has not been detailed, the described embodiments being compatible with usual structures of pixels of back-side illuminated sensors.

Throughout the present disclosure, the term “connected” is used to designate a direct electrical connection between circuit elements with no intermediate elements other than conductors, whereas the term “coupled” is used to designate an electrical connection between elements that may be direct, or may be via one or more intermediate elements.

In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, “lateral”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., unless otherwise specified, it is referred to the orientation of the drawings, it being understood that, in practice, the described devices may be oriented differently.

The terms “about”, “substantially”, “approximately”, and “in the order of” are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question.

FIG.1is a partial simplified cross-section view of an example of a back-side illuminated image sensor. The sensor ofFIG.1comprises a semiconductor layer101, for example, made of single-crystal silicon. The sensor ofFIG.1further comprises an interconnection structure103coating the upper surface or front side of semiconductor layer101. The sensor ofFIG.1comprises a plurality of pixels Px formed inside and on top of semiconductor layer101. Each pixel Px comprises at least one photosensitive area (not detailed) formed in semiconductor layer101, and one or a plurality of control transistors (not detailed) formed inside and on top of conductive layer101. Pixels101are interconnected by conductive tracks (not detailed) formed in interconnection structure103. In operation, the sensor is illuminated on its lower surface or back side, that is, on its side opposite to interconnection structure103, as illustrated by arrows104ofFIG.1.

Sensors of the type illustrated inFIG.1, comprising capacitive insulation walls105vertically extending through semiconductor layer101, from the front side and to the back side of layer101, are here more particularly considered. As an example, in each pixel, the photosensitive area of the pixel is totally surrounded, in top view, by a ring-shaped capacitive insulation wall105. Each capacitive insulation wall105comprises two vertical insulating walls105aand105b, separated by a vertical conductor or semiconductor region105c, for example, made of polysilicon or of amorphous silicon. Regions105a,105b, and105cfor example each extend across the entire thickness of semiconductor layer101, from the front side to the back side of layer101. Each of insulating walls105aand105bhas an outer lateral surface in contact with semiconductor layer101and an inner lateral surface in contact with region105c. As an example, insulating walls105aand105bare made of silicon oxide. In the shown example, each capacitive insulation wall105further comprises a central insulating wall105d, for example, made of silicon oxide, extending along the entire height of the wall and separating conductor or semiconductor region105cin two separate walls105c1and105c2.

As an example, the thickness of semiconductor layer101, and thus the height of walls105, is in the range from 1 to 20 μm, for example, from 2 to 10 μm. Conductor or semiconductor regions105c1and105c2for example each have a width in the range from 10 to 100 nm, for example, in the order of 50 nm. Central insulating region105dfor example has a width in the range from 10 to 200 nm, for example, in the order of 50 nm. Outer insulating regions105aand105bfor example each have a width in the range from 5 to 40 nm, for example, in the order of 15 nm.

In each capacitive insulation wall105, the conductor or semiconductor wall105c1and/or105c2of the wall may be electrically connected, by its front side, to a terminal of application of a bias potential (not detailed in the drawing) formed in interconnection structure103, which enables to bias the capacitance formed between semiconductor layer101and wall105c1and/or the capacitance formed between semiconductor layer101and wall105c2during the sensor operation.

On the back side of the sensor, a passivation layer107made of a dielectric material, continuously extending over substantially the entire rear surface of the sensor, that is, on the back side of semiconductor layer101and on the back side of capacitive insulation walls105, is provided. Layer107is for example made of a material different from the material of insulating walls105aand105b. As an example, layer107is made of a material having a high dielectric constant, that is, having a dielectric constant greater than that of silicon oxide, for example, hafnium oxide (HfO2) or aluminum oxide (Al2O3).

In the example ofFIG.1, the sensor further comprises an antireflection layer109, for example, made of tantalum oxide (Ta2O5), coating the back side of passivation layer107.

According to the needs of the application, other layers, not shown, may be provided on the back side of the sensor, for example, a silicon oxide protection layer, a filtering layer made of colored resin, a layer of microlenses, etc.

To form the sensor ofFIG.1, it may be started form a relatively thick initial substrate, for example, made of silicon, having its upper portion formed by semiconductor layer101of the sensor.

Pixels Px, capacitive insulation walls105, and interconnection structure103are then formed inside and on top of semiconductor layer101, from the front side of the substrate.

A support handle is then affixed onto the upper surface of interconnection structure103, after which the substrate is thinned from its lower surface or back side, for example by grinding and/or by chemical thinning, possibly followed by a step of planarization or chemical-mechanical polishing (CMP), until the back side of semiconductor layer101and of capacitive insulation walls105is reached.

Passivation layer107, as well as the possible additional back side layers of the sensor (antireflection layer109in the example ofFIG.1) are then deposited on the back side of semiconductor layer101and of capacitive insulation walls105.

The support handle attached to the front side of interconnection structure103may then be removed. As a variation, the support handle may be kept as a mechanical support until the end of the method (and possibly in the final product). As a variation, the support handle may comprise an integrated circuit comprising transistors for controlling the sensor pixels.

In practice, it can be observed that the capacitance formed between conductor or semiconductor wall105c1and semiconductor layer101(separated by insulating wall105a), and the capacitance formed between conductor or semiconductor wall105c2and semiconductor layer101(separated by insulating wall105b) have relatively low breakdown voltages. As an example, when the thickness of insulating walls105aand105bis selected to obtain a theoretical breakdown voltage of 20 V between region105c1and region101and between region105c2and region101, it can be observed, in practice, that the real breakdown voltage of the capacitances is approximately 10 V. Beyond this voltage, breakdowns are capable of occurring in the vicinity of the lower surface of walls105aand105b.

To solve this problem, after the step of thinning substrate101from its back side, and before the step of depositing dielectric passivation layer107, a step of partial etching, from the back side, of semiconductor layer101and of conductor or semiconductor regions105c1and105c2, selectively over insulating regions105a,105b, and105d, may be provided.

At the end of this etch step, insulating layers105a,105b, and105dof walls105have portions protruding from the back side of semiconductor layer101and from the back side of conductor or semiconductor regions105c1and105c2.

Passivation layer107is then deposited on the back side of semiconductor layer101and on the back side of conductor or semiconductor regions105c1and105c2, as well as on the back side and on the sides of the protruding portions of insulating regions105a,105b, and105d.

The possible additional back side layers of the sensor may then be deposited on the back side of layer107.

FIG.2is a partial simplified cross-section view illustrating an example of a back-side illuminated image sensor obtained by this method.FIG.2shows an enlargement of a portion of the sensor, centered on a vertical capacitive insulation wall105of the sensor. InFIG.2, the orientation of the sensor is inverted with respect toFIG.1. In other words, inFIG.2, the back side (or illumination surface) of the sensor corresponds to its upper surface, and the front side of the sensor corresponds to its lower surface.

An advantage of the manufacturing method described in relation withFIG.2and of the sensor obtained by this method is a significant improvement of the breakdown voltage of capacitive insulation walls105. Such an improvement can in particular be explained by the increase of the electric path between semiconductor layer101and conductor or semiconductor region105c1or105c2, via the interface between insulating walls105aor105band passivation layer107.

As an example, for identical dimensions, and particularly for a same thickness of insulating walls105aand105bof walls105, an improvement by a factor two of the breakdown voltage of the capacitances formed between region105c1and layer101on the one hand, and between region105c2and layer101on the other hand, can be observed.

It would however be desirable to at least partly improve certain aspects of back-side illuminated image sensors of the type described in relation withFIG.2.

FIGS.3,4,5,6,7,8,9, and10are partial simplified cross-section views illustrating steps of an example of a method of manufacturing a back-side illuminated image sensor according to an embodiment. While the steps of the manufacturing method are described sequentially with respect toFIGS.3through10, it will be readily appreciated that in various embodiments, the steps may be performed in any suitable sequence.

The sensor ofFIGS.3to10comprises elements common with the sensors ofFIGS.1and2. These elements will not be detailed again hereafter. Hereafter, only the differences with the sensors ofFIGS.1and2will be highlighted. It should be noted that the cross-section views ofFIGS.3to10have the same orientation as the cross-section view ofFIG.2and show an enlargement of an upper portion of the sensor, centered on a vertical capacitive insulation wall105of the sensor.

FIG.3illustrates an initial step of forming a structure comprising semiconductor layer101and capacitive insulation walls105extending vertically from the front side (lower surface in the orientation ofFIGS.3to10, not shown inFIGS.3to10) to the back side (upper surface in the orientation ofFIGS.3to10) of semiconductor layer101. To form this structure, one may, as in the previously-described examples, start from a relatively thick initial substrate, for example, made of silicon, having its front portion formed by semiconductor layer101. Pixels Px, capacitive insulation walls105, and interconnection structure103(not shown inFIGS.3to10) are then formed inside and on top of semiconductor layer101, from the front side of the substrate. A support handle (not shown) is then affixed to the front side of interconnection structure103(that is, the surface of interconnection structure103opposite to the substrate), after which the substrate is thinned from its back side, for example, by grinding, to reach the back side of semiconductor layer101and of capacitive insulation walls105. The substrate thinning step may in particular comprise a step of chemical-mechanical planarization or polishing (CMP) aiming at obtaining, after thinning, a substantially planar rear surface. In other words, at the end of this step, capacitive insulation walls105of the sensor are flush with the level of the back side of semiconductor101to form a substantially planar rear surface.

FIG.4illustrates a step of partial removal or recess of semiconductor layer101and of conductor or semiconductor regions105c1and105c2, from the back side of the structure obtained at end of the steps ofFIG.3. During this step, the insulating regions105a,105b, and105dof capacitive insulation walls105are kept. To achieve this, a partial etching of semiconductor layer101and of conductive or semiconductor regions105c1and105c2, selectively over insulating regions105a,105b, and105d, is performed from the back side of the structure obtained at the end of the steps ofFIG.3. Selective etching means that the speed at which the material(s) forming layer101and regions105c1and105c2(for example, silicon) are etched is greater, for example ten times greater, and preferably at least one hundred times greater, than the speed at which the material(s) forming regions105a,105b, and105d(for example, silicon oxide) are etched. As an example, the etching implemented at the step ofFIG.4is a plasma or dry etch step. As a variation, a wet etching may be used. The thickness of layer101and of regions105c1and105c2removed at the step ofFIG.4is for example in the range from 5 to 200 nm, and preferably from 10 to 50 nm. As an example, the etching implemented at the step ofFIG.4is a non-local etching, that is, semiconductor layer101and regions105c1and105c2are thinned across substantially the entire surface of the sensor

Thus, at the end of the step ofFIG.4, on the back side of the structure, the conductor or semiconductor regions105c1of105c2of capacitive insulation walls105substantially stop at the same level as the back side of semiconductor layer101. However, insulating layers105a,105b, and105dof walls105have portions protruding from the back side of semiconductor layer101and from the back side of conductor or semiconductor regions105c1and105c2.

At the end of the step of selective partial etching of layer101and of regions105c1and105c2, a step of chemical cleaning of the back side of the sensor may be provided. During this step, a thin oxide layer (not shown), of native oxide or of chemical oxide, having a thickness in the order of 1 nm or less, may form on the back side of semiconductor layer101and on the back side of conductor and semiconductor regions105c1and105c2. As a variation, a specific step of oxidizing the back side of semiconductor layer101may be provided to obtain a slightly ticker oxide layer, for example, having a thickness in the range from 1 to 5 nm.

FIG.5illustrates a step of deposition of passivation layer107of the sensor, on top of and in contact with the back side of the structure obtained at the end of the steps ofFIGS.3and4. Layer107is for example deposited by atomic layer deposition (ALD). More generally, any other conformal deposition method may be used, so that layer107follows the shape of the relief formed by the protruding portions of insulating walls105a,105b, and105dof walls105. Passivation layer107is for example continuously deposited all over the rear surface of the sensor. The thickness of passivation layer107is for example smaller than the height of the protruding portions of insulating walls105a,105b, and105d. As an example, the thickness of passivation layer107is in the range from 2 to 100 nm, for example, in the order of 13 nm.

FIG.6illustrates a step of deposition of a sacrificial layer201on the upper surface of the structure obtained at the end of the steps ofFIGS.3,4, and5. Layer201is made of a material selectively etchable over the material of layer107(for example, hafnium oxide or aluminum oxide) and over the material of insulating walls105a,105b, and105d(for example, silicon oxide). As an example, sacrificial layer201is made of silicon nitride, or resin, or of metal, for example, a metal from the group comprising copper, tungsten, and aluminum. As a variation, sacrificial layer201is made of silicon oxide deposited at low temperature to have a density lower than that of the silicon oxide of insulating walls105a,105b, and105dand thus be selectively etchable over insulating walls105a,105b, and105d. Sacrificial layer201is for example continuously deposited all over the rear surface of the sensor. The thickness of sacrificial layer201is for example selected to be greater than the height of the protruding portions of insulating walls105a,105b, and105d. As an example, the thickness of sacrificial layer201is in the range from 10 to 200 nm, for example, in the order of 50 nm.

FIG.7illustrates a step of thinning, from the back side, the structure obtained at the end of the steps ofFIGS.3,4,5, and6, for example, by chemical-mechanical planarization or polishing (CMP), to reach the back side of the insulating walls105a,105b, and105d. The thinning is interrupted when the back side of the protruding portions of insulating walls105a,105b, and105dis reached. Thus, at the end of this step, passivation layer107is interrupted opposite the back side of insulating walls105a,105b, and105d. Passivation layer107is however kept opposite the back side of semiconductor layer101and of conductor or semiconductor regions105c1and105c2, and on the sides of the protruding portions of insulating walls105a,105b, and105d. At the end of this step, the back sides of insulating walls105a,105b, and105dand of the portions of layer107coating the sides of insulating walls105a,105b, and105dare flush with the back side of sacrificial layer201, to form a substantially planar rear surface of the sensor.

FIG.8illustrates a step of removing the portions of sacrificial layer201remaining opposite the back side of semiconductor layer101and conductor or semiconductor regions105c1and105c2. During this step, sacrificial layer201is selectively removed over passivation layer107and over insulating walls105a,105b, and105d. Sacrificial layer201may be removed by dry etching or by wet etching.

FIG.9illustrates a step of deposition of antireflection layer109, for example, made of tantalum oxide, on the back side of the structure obtained at the end of the steps ofFIGS.3,4,5,6,7, and8. More particularly, in this example, layer109is deposited on top of and in contact with the back side of passivation layer107opposite semiconductor layer101and conductor or semiconductor regions105c1and105c2, and on top of and in contact with the back side of insulating walls105a,105b, and105d. Antireflection layer109is for example continuously deposited all over the rear surface of the sensor. As an example, layer109is deposited by atomic layer deposition (ALD). More generally, any other conformal deposition method may be used. As an example, the thickness of antireflection layer109is in the range from 2 to 200 nm, for example, in the order of 47 nm.

FIG.10illustrates a step of deposition of a protection insulating layer111, for example, made of silicon oxide, on top of and in contact with the back side of antireflection layer109. Protection layer111is for example continuously deposited over the entire rear surface of the sensor. As an example, the thickness of protection layer111is in the range from 15 to 400 nm.

As previously indicated, according to the needs of the application, other layers, not shown, may be provided on the back side of the sensor, for example, a filtering layer made of colored resin, a layer of microlenses, etc.

An advantage of the manufacturing method described in relation withFIGS.3to10and of the sensor obtained by this method is a significant decrease in the dark current detected by the sensor pixels.

A possible explanation of this advantage is that dielectric passivation layer107is not perfectly electrically insulating and may, in a structure of the type described in relation withFIG.2, conduct parasitic electric charges from conductor or semiconductor regions105c1and105c2to the photodetection areas of the pixels formed in semiconductor layer101. In a sensor of the type obtained by the method ofFIGS.3to10, the interruption of passivation layer107opposite the back side of the protruding portions of insulating walls105a,105b, and105denables to interrupt the conduction of parasitic charges via layer107.

FIG.11is a partial simplified cross-section view illustrating an alternative embodiment of the method illustrated inFIGS.3to10.FIG.11is a view in the same cross-section plane asFIGS.3to10, showing the sensor obtained at the end of the method.

The method ofFIG.11differs from the method ofFIGS.3to10mainly in that, in the example ofFIG.11, antireflection layer109is deposited on the back side of passivation layer107before the deposition of sacrificial layer201(not shown inFIG.11). Thus, during the step of planarization of the back side of the sensor (FIG.7), passivation layer107and antireflection layer109are both interrupted opposite the back side of insulating walls105a,105b, and105d. After the removal of sacrificial layer201, protection layer111may be deposited on top of and in contact with the back side of antireflection layer109and on top of and in contact with the exposed portion of passivation layer107opposite semiconductor layer101and conductor or semiconductor regions105c1and105c2, and on top of and in contact with the back side of insulating walls105a,105b, and105d. In this variation, the material of sacrificial layer201is selected to be selectively etchable not only over the material of layer107and over the material of insulating walls105a,105b, and105d, but also over the material of layer109.

An advantage of the manufacturing method ofFIG.11and of the sensor obtained by this method is that it enables to still further decrease the dark current by avoiding the conduction of parasitic charges from conductor or semiconductor regions105c1and105c2to semiconductor layer101, via layer109.

FIGS.12A and12Billustrate another variation of the method illustrated inFIGS.3to10. Each ofFIGS.12A and12Bshow an enlargement of a portion of the sensor, close to the back side of the sensor, at the level of an insulating wall105aof the vertical capacitive insulation wall105of the sensor (corresponding to the portion delimited by a frame12inFIG.4).

FIG.12Ashows the back side of the sensor at the end of the step of selective partial etching of layer101and of regions105c1and105c2, described in relation withFIG.4. As shown inFIG.12A, it can be observed that in practice, the etching of layer101and of regions105c1and105c2is not perfectly uniform. More particularly, according to the type of method used for perform the etching, there may remain residues of the material of layer101and of regions105c1and105c2in the immediate vicinity of insulating walls105a,105b, and105d, for example, due to a shadowing effect, to a selectivity effect, etc. This results in the forming, in layer101and/or in regions105c1and105c2, of point-shaped or bird's beak structures301, bearing on insulating walls105a,105b, and105c.

FIG.12Billustrates a step of oxidizing the back side of the structure obtained at the end of the steps ofFIGS.3and4, to form a relatively thick oxide layer303, for example, in the range from 1 to 10 nm, for example, in the order of 5 nm, on the back side of semiconductor layer101and on the back side of regions105c1and105c2of capacitive insulation walls105. As illustrated inFIG.12B, this oxidation step results in significantly rounding, or even in suppressing, the points of bird's beak structures301at the interface with insulating walls105a,105b, and105d. As an example, the oxidation step is carried out by submitting the back side of the sensor to an oxygen plasma, preferably at a temperature smaller than 400° C. to avoid damaging interconnection structure103of the sensor. As a variation, a chemical oxidation may be provided.

The rest of the method is for example identical or similar to what has been previously described in relation withFIGS.5to10.

An advantage of the alternative embodiment ofFIGS.12A and12Bis that it enables to further improve the voltage behavior of the capacitive insulation walls of the sensor.

Of course, the alternative embodiments ofFIGS.11and12A and12Bmay be combined.

FIG.13is a partial simplified cross-section view illustrating another example of a back-side illuminated image sensor according to an embodiment.

FIG.13is a view in the same cross-section plane asFIG.10. The sensor ofFIG.13shows elements common with the sensor ofFIG.10, and is formed by a manufacturing method similar to the method described in relation withFIGS.3to10. In the following, only the differences with respect to the sensor ofFIG.10will be detailed.

The sensor ofFIG.13differs from the sensor ofFIG.10mainly in that, in the example ofFIG.13, capacitive insulation walls105comprise no central insulating wall105d. Thus, in the example ofFIG.13, regions105c1and105c2are combined in a single central conductive or semiconductor region105c. In other words, each capacitive insulation wall105comprises two insulating walls105aand105bhaving their outer lateral surfaces in contact with semiconductor layer101, and a conductor or semiconductor region105cforming a single central wall having its lateral surfaces respectively in contact with the inner lateral surface of insulating wall105aand with the inner lateral surface of insulating wall105b.

Of course, the variation ofFIG.13may be combined with the variation ofFIG.11and/or with the variation ofFIGS.12A and12B.

Various embodiments and variations have been described. It will be understood by those skilled in the art that certain features of these various embodiments and variations may be combined, and other variations will occur to those skilled in the art. In particular, the above-described embodiments are not limited to the examples of numerical dimensions or to the examples of materials mentioned in the present disclosure.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present disclosure. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present disclosure is limited only as defined in the following claims and the equivalents thereto.

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.