Patent ID: 12237037

DETAILED DESCRIPTION

Below, some example embodiments of the inventive concepts will be described in detail and clearly to such an extent that one skilled in the art easily carries out the inventive concepts.

FIG.1is a block diagram illustrating a reference voltage generation device according to an example embodiment of the inventive concepts.

Referring toFIG.1, a reference voltage generation device400may be used in an electronic system10. The electronic system10may include a first electronic device100and a second electronic device300that perform data communication using the multi-level signaling scheme, and the reference voltage generation device400may generate a reference voltage VREF that is used in the second electronic device300among the first and second electronic devices100and300.

In an example embodiment, the first electronic device100may be a memory controller, and the second electronic device300may be a memory device; however, the example embodiments are not limited thereto. In another example embodiment, the first electronic device100may be a host device, and the second electronic device300may be a memory system including the memory controller and the memory device. The memory device may include at least one of a nonvolatile memory device and a volatile memory device. An example embodiment in which the memory device is implemented with the volatile memory device will be described with reference toFIG.6, and an example embodiment in which the memory device is implemented with the nonvolatile memory device will be described with reference toFIG.18.

The first electronic device100and the second electronic device300may perform data communication using the multi-level signaling scheme. The data communication may allow the first electronic device100and the second electronic device300to transmit multi-level signals having signal levels of different magnitudes and respectively indicating multi-bit symbols; in some example embodiments, the throughput may be increased with the bandwidth of the data communication maintained. For example, a type of the data communication may correspond to pulse amplitude modulation (PAM) signaling. In some example embodiments, each symbol may be expressed by one of signal levels having different magnitudes. For example, in the case of the PAM4 signaling scheme, each symbol may be expressed by one of four signal levels having different magnitudes, and each signal level may indicate a 2-bit symbol.

In an example embodiment, when the first electronic device100and the second electronic device300perform the data communication, power noises that come from a first power PS1and a second power PS2supplied to the first electronic device100may be propagated to the second electronic device300through a communication line. The power noises may be added to the multi-level signals according to the data communication; when the signals are decoded, a decoding error may be caused by the power noises.

The reference voltage generation device400includes a noise information generation circuit200and a reference voltage generation circuit310. The noise information generation circuit200includes a power noise transmitter210, a communication line230, and a power noise receiver250.

The noise information generation circuit200generates power noise information PNINFO based on a first power noise pns1and a second power noise pns2that are generated based on the first power PS1and the second power PS2and are propagated from the first electronic device100to the second electronic device300.

In an example embodiment, the power noise information PNINFO may be generated without the addition of separate pins/pads.

In an example embodiment, the noise information generation circuit200may generate the power noise information PNINFO based on both the first power PS1and the second power PS2, not one of the first power PS1and the second power PS2.

In an example embodiment, the first power PS1and the second power PS2may be supplied to the first electronic device100and may correspond to each other, and the first power PS1may be greater than the second power PS2. For example, the first power PS1and the second power PS2may include powers VDD and VSS and may further include powers VDDQ and VSSQ. For example, one of the first power PS1and the second power PS2may include a ground voltage.

In an example embodiment, the first power noise pns1may be a power noise that is generated based on the first power PS1and is propagated to the second electronic device300through the communication line230, and the second power noise pns2may be a power noise that is generated based on the second power PS2and is propagated to the second electronic device300through the communication line230. The first power noise pns1and the second power noise pns2may be provided to the communication line230by the power noise transmitter210included in the first electronic device100and may be received from the communication line230by the power noise receiver250included in the second electronic device300.

In an example embodiment, the communication line230may not be an electronic line that is additionally provided to implement (or carry out) the inventive concepts, but it may be one of electrical lines that are used to perform general operations of the first electronic device100and the second electronic device300. For example, the communication line230may include at least one of a data line and a power line between the first electronic device100and the second electronic device300.

In an example embodiment, the power noise transmitter210and the power noise receiver250may include a plurality of resistors. For example, the plurality of resistors may include variable resistors. Resistance values of the variable resistors may be adjusted based on a control signal NCTL that is generated by a control circuit (not illustrated) included in the second electronic device300. In another example embodiment, the plurality of resistors may be set to have resistance values that are determined in advance.

The reference voltage generation circuit310generates three or more reference voltages VREF for the multi-level signaling based on the power noise information PNINFO.

In an example embodiment, the power noise information PNINFO may include one or more noise signals. The one or more noise signals may correspond to one or more of signal levels according to the data communication, and a noise signal corresponding to a specific signal level of the signal levels may be generated by adjusting the resistance values of the variable resistors. The noise signal will be described with reference toFIG.8.

One or more of the reference voltages VREF may be generated by adding the noise signal to one or more of separate analog voltage signals that the reference voltage generation circuit310generates. The second electronic device300may include a plurality of memory devices, and the reference voltage generation circuit310may supply the reference voltages VREF for the plurality of memory devices. In some example embodiments, the first electronic device100may be referred to as an “external electronic device”.

In an example embodiment, the reference voltage generation circuit310may supply the same reference voltages VREF to all the plurality of memory devices. In some example embodiments, the reference voltage generation circuit310may be referred to as a “global reference voltage generation circuit”. In another example embodiment, the reference voltage generation circuit310may supply the reference voltages VREF to some of the plurality of memory devices. In some example embodiments, the reference voltage generation circuit310may be referred to as a “local reference voltage generation circuit”, and the number of local reference voltage generation circuits may be 2 or more. The power noise information PNINFO will be described with reference toFIGS.7and8.

In an example embodiment, in the case where the first electronic device100and the second electronic device300perform the data communication using the PAM4 signaling scheme, the reference voltages VREF may include a first reference voltage, a second reference voltage, and a third reference voltage, magnitudes of which increase sequentially. In some example embodiments, the reference voltages VREF may be used to decode multi-level signals that are transmitted from the first electronic device100to the second electronic device300in the process of performing the data communication. The reference voltages VREF will be described with reference toFIGS.4and5. The reference voltage generation circuit310will be described with reference toFIGS.9A,9B, and9C.

Through the above configuration, a reference voltage generation device according to an example embodiment of the inventive concepts may generate power noise information based on power noises that are generated based on both a first power and a second power supplied to the external electronic device and are propagated through a communication line. In the case of decoding multi-level signals, reference voltages may be generated based on the power noise information, and all the power noises that are based on both the first power and the second power may be removed based on the reference voltages. This may mean that the decoding error is inhibited or prevented.

FIGS.2and3are block diagrams illustrating an example embodiment of a memory system using a reference voltage generation device ofFIG.1.

Referring toFIGS.1and2, a memory system10aincludes a memory controller100aand a memory device300a.

The memory controller100amay overall control an operation of the memory device300a. For example, the memory system10amay include a plurality of signal lines, and may control the operation of the memory device300aby providing the memory device300awith commands CMD, addressees ADDR, and data MDAT through the plurality of signal lines.

The memory controller100amay correspond to the first electronic device100ofFIG.1, the memory device300amay correspond to the second electronic device300ofFIG.1, and the memory controller100aand the memory device300amay exchange the data MDAT in the multi-level signaling scheme described with reference toFIG.1. For example, the memory device300amay receive multi-level data MDAT from the memory controller100aand may transmit the multi-level data MDAT to the memory controller100a.

The memory system10amay further include a reference voltage generation device200aincluding a power noise transmitter210aand a power noise receiver250a. The power noise transmitter210amay be included in the memory controller100a, and the power noise receiver250amay be included in the memory device300a.

The reference voltage generation device200amay generate power noise information based on power noises that are propagated to the memory device300aand may generate reference voltages used to decode the multi-level data MDAT. The power noises may be generated based on both the first power PS1and the second power PS2supplied to the memory controller100a. The power noise transmitter210aand the power noise receiver250amay include a plurality of resistors, and the plurality of resistors may be variable resistors whose resistance values are adjusted based on the control signal NCTL. The control signal NCTL may be generated by a control circuit (not illustrated) included in the memory device300a.

Referring toFIGS.1,2, and3, a memory system10bincludes a memory controller100band a memory device300b.

The memory controller100bmay include a plurality of transmission drivers15a,15b, and15c, a plurality of reception drivers17a,17b, and17c, and a plurality of input/output pads19a,19b, . . . ,19m, and the memory device300bmay include a plurality of transmission drivers35b, and35c, a plurality of reception drivers37a,37b, and37c, and a plurality of input/output pads39a,39b, . . . ,39m.

Each of the plurality of transmission drivers15a,15b, and15cmay generate a multi-level signal, and each of the plurality of reception drivers17a,17b, and17cmay receive the multi-level signal. The memory controller100band the memory device300bmay be connected with each other through plurality of input/output pads19a,19b, . . . ,19mand39a,39b, . . . ,39m, and may exchange multi-level data MDAT1, MDAT2, . . . , MDATm. For example, the memory controller100bmay encode input data IDAT1, IDAT2, . . . , IDATm by using the plurality of transmission drivers15a,15b, and15cand may transmit the multi-level data MDAT1, MDAT2, . . . , MDATm to the memory device300bas an encoding result; the memory device300bmay decode the multi-level data MDAT1, MDAT2, . . . , MDATm by using the plurality of reception drivers37a,37b, and37cand may receive output data ODAT1, ODAT2, . . . , ODATm as a decoding result.

In an example embodiment, when the memory controller100btransmits the multi-level data MDAT1, MDAT2, MDATm to the memory device300b, the plurality of reception drivers37a,37b, and37cmay receive the multi-level data MDAT1, MDAT2, . . . , MDATm, may receive the reference voltages, and may decode the multi-level data MDAT1, MDAT2, . . . , MDATm based on a result of comparing the multi-level data MDAT1, MDAT2, . . . , MDATm and the reference voltages.

FIG.4is a block diagram illustrating an example embodiment of a reception driver ofFIG.3.FIG.5is a diagram illustrating an eye diagram associated with signals used in multi-level signaling.

Referring toFIGS.3and4, the reception driver37amay include reception buffers311,313, and315and an output decoder330. Configurations of the remaining reception drivers17ato17c,37b, and37cillustrated inFIG.3may be similar to the configuration of the reception driver37a.

The reception buffers311,313, and315may receive the multi-level data MDAT1and a clock signal CLK. The reception buffer311may further receive a reference voltage VREF3, the reception buffer313may further receive a reference voltage VREF2, and the reception buffer315may further receive a reference voltage VREF1.

The reception buffers311,313, and315may compare a voltage level of the multi-level data MDAT1with voltage levels of corresponding reference voltages based on the clock signal CLK toggling every unit time period and may output comparison results to the output decoder330, and the output decoder330may output a symbol, which is obtained by decoding the multi-level data MDAT1based on the comparison results, as output data ODAT1.

Signal levels VL1, VL2, VL3, and VL4and the reference voltages VREF1, VREF2, and VREF3are illustrated inFIG.5. Referring toFIG.5, the signal levels VL1, VL2, VL3, and VL4may indicate signal levels that the multi-level data MDAT1is capable of having in the PAM4 signaling-based data communication, and the reference voltages VREF1, VREF2, and VREF3that have preset voltage levels may be used in the process of decoding the multi-level data MDAT1. For example, the reference voltage VREF1may have a voltage level between the signal levels VL2and VL1, the reference voltage VREF2may have a voltage level between the signal levels VL3and VL2, and the reference voltage VREF3may have a voltage level between the signal levels VL4and VL3. As illustrated inFIG.5, in the case of performing the data communication using the PAM4 signaling scheme, eye heights (or intervals) EH1, EH2, and EH3between adjacent signal levels of the signal levels VL1to VL4may be reduced by “⅓” or less of an NRZ eye height and may be vulnerable to the power noise.

FIG.6is a block diagram illustrating an example embodiment of a memory device ofFIG.2or3.

Referring toFIGS.2,3, and6, a memory device500may include a control logic circuit510, a row decoder520, a bank array530, a sense amplifier unit531, an input/output gating circuit540, a column decoder550, an ECC engine560, a data input/output buffer570, and an on-die termination (ODT) circuit580. The control logic circuit510may include a command decoder511, a mode register513, a refresh counter515, an address register517, and bank control logic519. For example, the memory device500may be a volatile memory device. In detail, the memory device500may be a DRAM.

The bank array530may include a plurality of bank arrays. The row decoder520may include a plurality of bank row decoders respectively connected with the plurality of bank arrays, the column decoder550may include a plurality of bank column decoders respectively connected with the plurality of bank arrays, and the sense amplifier unit531may include a plurality of bank sense amplifiers respectively connected with the plurality of bank arrays. The plurality of bank arrays, the plurality of bank row decoders, the plurality of bank column decoders, and the plurality of bank sense amplifiers may constitute a plurality of banks. Each of the plurality of bank arrays may include a plurality of memory cells MC that are formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

The address register517may receive the address ADDR including a bank address, a row address, and a column address from the memory controller. The address register517may provide the bank address to the bank control logic519, may provide the row address to the row decoder520, and may provide the column address to the column decoder550.

The bank control logic519may generate a bank control signal in response to the bank address. A bank row decoder and a bank column decoder that correspond to the bank address may be activated based on the bank control signal.

The refresh counter515may generate a refresh row address that sequentially increases or decreases under control of the control logic circuit510. The bank column decoder activated from the plurality of bank column decoders may activate sense amplifiers, which correspond to the bank address, the row address, and the column address and are included in the sense amplifier unit531, by using the input/output gating circuit540.

A codeword CW read from one of the plurality of bank arrays may be sensed by sense amplifiers corresponding to the one bank array, the ECC engine560may perform ECC decoding on the sensed codeword CW, and a DQ signal may be provided to the memory controller through the data input/output buffer570as an ECC decoding result. Data DAT that are transmitted from an input/output pad590to the data input/output buffer570may be the multi-level data described with reference toFIGS.1and4. The data input/output buffer570may include reception drivers for encoding the multi-level data and may receive the reference voltages VREF1, VREF2, and VREF3for the encoding.

The data DAT to be written in one of the plurality of bank arrays may be provided to the ECC engine560, the ECC engine560may generate parity bits based on the data DAT and may provide a codeword including the data DAT and the parity bits to the input/output gating circuit540, and the input/output gating circuit540may write the codeword in the one bank array.

The control logic circuit510may control the operation of the memory device500. For example, the control logic circuit510may generate control signals such that the memory device500performs a write operation or a read operation. The control logic circuit510may include the command decoder511that decodes the command CMD received from the memory controller and the mode register513for setting an operation mode of the memory device500. For example, the command decoder511may decode a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc., and may generate the control signals corresponding to the command CMD.

The ODT circuit580may be connected with the data input/output pad590and the data input/output buffer570and may perform impedance matching.

FIG.7is a circuit diagram illustrating an example embodiment of a noise information generation circuit ofFIG.1.

Referring toFIGS.1and7, a noise information generation circuit200bmay include a power noise transmitter210b, a communication line230b, and a power noise receiver250b.

The power noise transmitter210bmay be included in the first electronic device100, and the power noise receiver250bmay be included in the second electronic device300.

The power noise transmitter210bmay output, to a first terminal270, the first power noise pns1and the second power noise pns2that are generated based on the first power PS1and the second power PS2supplied to the first electronic device100and are propagated from the first electronic device100to the second electronic device300through the communication line230b. The power noise receiver250bmay receive the first and second power noises pns1and pns2through a second terminal290connected with the first terminal270through the communication line230b.

In an example embodiment, the power noise transmitter210bmay be electrically connected with the first power PS1, the second power PS2, and the first terminal270, and the power noise receiver250bmay be electrically connected with the first power PS1and the second terminal290.

The power noise transmitter210bmay include a resistor RPU and a resistor RPD connected in series between the first power PS1and the second power PS2, and the power noise receiver250bmay include a resistor RT electrically connected between the first power PS1and the second terminal290.

In an example embodiment, the first terminal270may be connected with a first node N1, and the first node N1may be a node between the resistor RPU and the resistor RPD.

In an example embodiment, resistance values of the resistor RPU and the resistor RPD may be adjusted based on the control signal NCTL or may be determined in advance. The power noise information PNINFO may be generated based on the resistor RPU, the resistor RPD, and the resistor RT. The power noise information PNINFO may include a noise signal corresponding to one or more of signal levels according to the data communication between the first electronic device100and the second electronic device300.

FIG.8is a diagram for describing power noise information ofFIG.7. Various trials for adjusting resistance values of the resistor RPU and the resistor RPD necessary to generate the power noise information PNINFO are illustrated inFIG.8.

Referring toFIGS.7and8, when the resistor RPU has a resistance value of 40 ohm and the resistor RPD has a resistance value of “Inf” (e.g., refer to TRIAL1), the power noise receiver250bmay output the power noise information PNINFO including a noise signal. For example, the power noise information PNINFO may be generated based on a result of measuring a voltage across the resistor RT. In some example embodiments, the power noise information PNINFO may include the noise signal in which a ratio of the first power noise pns1propagated based on the first power PS1and the second power noise pns2propagated based on the second power PS2is 0.5:0 (e.g., in which only a component of the first power noise pns1is included).

When the resistor RPU has a resistance value of 48 ohm and the resistor RPD has a resistance value of 240 ohm (e.g., refer to TRIAL2), the power noise receiver250bmay output the power noise information PNINFO. In some example embodiments, the power noise information PNINFO may include the noise signal in which a ratio of the first power noise pns1and the second power noise pns2is 0.417:0.083 (e.g., the noise signal including both the first power noise component and the second power noise component at a given ratio).

When the resistor RPU has a resistance value of 60 ohm and the resistor RPD has a resistance value of 120 ohm (e.g., refer to TRIAL3), the power noise receiver250bmay output the power noise information PNINFO. In some example embodiments, the power noise information PNINFO may include the noise signal in which a ratio of the first power noise pns1and the second power noise pns2is 0.333:0.167.

As in the above description, the remaining trials TRIAL4, TRIAL5, TRIAL6, and TRIAL7may be performed by adjusting resistance values of the resistor RPU and the resistor RPD, and thus, the power noise information PNINFO including a noise signal corresponding to each trial may be generated.

In an example embodiment, the power noise information PNINFO may be generated by performing the trials TRIAL2, TRIAL4, and TRIAL6. In some example embodiments, the power noise information PNINFO may include noise signals nds1, nds2, and nds3.

In an example embodiment, the first noise signal nds1may correspond to the second signal level VL2of the signal levels VL1, VL2, VL3, and VL4described with reference toFIG.5. The second noise signal nds2may correspond to the third signal level VL3of the signal levels VL1, VL2, VL3, and VL4. The third noise signal nds3may correspond to the fourth signal level VL4of the signal levels VL1, VL2, VL3, and VL4.

FIGS.9A,9B, and9Care block diagrams illustrating example embodiments of a reference voltage generation circuit ofFIG.1.

Referring toFIGS.8and9A, a reference voltage generation circuit310amay generate three or more reference voltages VREF for multi-level signaling based on the power noise information PNINFO. For example, the reference voltage generation circuit310amay generate three reference voltages VREF1, VREF2, and VREF3for PAM4 signaling. The reference voltage generation circuit310amay include a voltage generator311aand adders313-1,313-2, and313-3. The power noise information PNINFO may include the first to third noise signals nds1to nds3.

The voltage generator311amay output a first voltage signal V1, a second voltage signal V2, and a third voltage signal V3. The first adder313-1may receive the first voltage signal V1and the first noise signal nds1and may output a value obtained by adding the first voltage signal V1and the first noise signal nds1as the first reference voltage VREF1. The second adder313-2may receive the second voltage signal V2and the second noise signal nds2and may output a value obtained by adding the second voltage signal V2and the second noise signal nds2as the second reference voltage VREF2. The third adder313-3may receive the third voltage signal V3and the third noise signal nds3and may output a value obtained by adding the third voltage signal V3and the third noise signal nds3as the third reference voltage VREF3.

Referring toFIGS.8and9B, a reference voltage generation circuit310bmay generate the three reference voltages VREF1, VREF2, and VREF3for PAM4 signaling based on the power noise information PNINFO. The reference voltage generation circuit310bmay include a voltage generator311b, adders313-4,313-5,313-6, and313-7, and a first multiplier315-1. The power noise information PNINFO may include the first noise signal nds1and the third noise signal nds3.

The voltage generator311bmay output the first voltage signal V1, the second voltage signal V2, and the third voltage signal V3. The fourth adder313-4may receive the first voltage signal V1and the first noise signal nds1and may output a value obtained by adding the first voltage signal V1and the first noise signal nds1as the first reference voltage VREF1. The fifth adder313-5may receive the first noise signal nds1and the third noise signal nds3and may output a value obtained by adding the first noise signal nds1and the third noise signal nds3. The first multiplier315-1may output a value obtained by multiplying a given ratio (e.g., “½”) and a value output from the fifth adder313-5together. The sixth adder313-6may output a value obtained by adding the second voltage signal V2and a value output from the first multiplier315-1as the second reference voltage VREF2. The seventh adder313-7may receive the third voltage signal V3and the third noise signal nds3and may output a value obtained by adding the third voltage signal V3and the third noise signal nds3as the third reference voltage VREF3.

Referring toFIGS.8and9C, a reference voltage generation circuit310cmay generate the three reference voltages VREF1, VREF2, and VREF3for PAM4 signaling based on the power noise information PNINFO. The reference voltage generation circuit310cmay include a voltage generator311c, adders313-8,313-9, and313-10, and a second multiplier315-3. The power noise information PNINFO may include the first noise signal nds1and the third noise signal nds3.

The voltage generator311cmay output the first voltage signal V1and the third voltage signal V3. The eighth adder313-8may receive the first voltage signal V1and the first noise signal nds1and may output a value obtained by adding the first voltage signal V1and the first noise signal nds1as the first reference voltage VREF1. The tenth adder313-10may receive the third voltage signal V3and the third noise signal nds3and may output a value obtained by adding the third voltage signal V3and the third noise signal nds3as the third reference voltage VREF3. The ninth adder313-9may receive the first reference voltage VREF1and the third reference voltage VREF3and may output a value obtained by adding the first reference voltage VREF1and the third reference voltage VREF3, and the second multiplier315-3may output a value obtained by multiplying a given ratio (e.g., “½”) and a value output from the ninth adder313-9as the second reference voltage VREF2.

FIG.10is a block diagram illustrating a memory system including a reference voltage generation device according to an example embodiment of the inventive concepts.

Referring toFIG.10, a memory system10-1may include a memory controller100-1and a memory device300-1. The memory controller100-1may overall control an operation of the memory device300-1, and the memory device300-1may include a plurality of sub-memory devices MD11, MD12, . . . , MD1n, MD21, MD22, . . . , MD2n, and MDz1, MDz2, . . . , MDzn (n and z being an integer of 3 or more).

The plurality of sub-memory devices MD11, MD12, . . . , MD1n, MD21, MD22, . . . , MD2n, and MDz1, MDz2, . . . , MDzn may constitute the plurality of banks described with reference toFIG.6. For example, the sub-memory devices MD11to MD1nmay constitute a first bank, the sub-memory devices MD21to MD2nmay constitute a second bank, and the sub-memory devices MDz1to MDzn may constitute a z-th bank. The first bank, the second bank, and the z-th bank may respectively correspond to a plurality of channels CH1, CH2, . . . , CHz.

In an example embodiment, the memory device300-1may be connected with the memory controller100-1through the plurality of channels CH1, CH2, . . . , CHz.

The memory device300-1may further include local reference voltage generation circuits310-11,310-21, . . . ,310-z1respectively corresponding to the plurality of channels CH1, CH2, . . . , CHz. Each of the local reference voltage generation circuits310-11,310-21, . . . ,310-z1may generate the power noise information PRINFO based on a first power noise and a second power noise that are generated based on a first power and a second power supplied to the memory controller100-1and are propagated from the memory controller100-1to the memory device300-1through a communication line, and may generate three or more reference voltages for multi-level signaling, for example, the three reference voltages VREF1, VREF2, and VREF3based on the power noise information PRINFO.

In an example embodiment, the reference voltage generation device, e.g.,400inFIGS.1and200ainFIG.2, described with reference toFIGS.1and2may be implemented in the memory controller100-1and the memory device300-1for each of the channels CH1, CH2, . . . , CHz. For example, a first noise information generation circuit200-11that includes a power noise transmitter210-11and a power noise receiver250-11may be implemented to correspond to the first channel CH1; a second noise information generation circuit200-21that includes a power noise transmitter210-21and a power noise receiver250-21may be implemented to correspond to the second channel CH2; a z-th noise information generation circuit200-z1that includes a power noise transmitter210-z1and a power noise receiver250-z1may be implemented to correspond to the z-th channel CHz.

In an example embodiment, the first local reference voltage generation circuit310-11may supply the reference voltages VREF1, VREF2, and VREF3to the sub-memory devices MD11, MD12, . . . , MD1ncorresponding to the first channel CH1; the second local reference voltage generation circuit310-21may supply the reference voltages VREF1, VREF2, and VREF3to the sub-memory devices MD21, MD22, . . . , MD2ncorresponding to the second channel CH2; the z-th local reference voltage generation circuit310-z1may supply the reference voltages VREF1, VREF2, and VREF3to the sub-memory devices MDz1, MDz2, . . . , MDzn corresponding to the z-th channel CHz.

In an example embodiment, the first to z-th noise information generation circuits200-11,200-21, . . . ,200-z1may operate based on control signals NCTL1, NCTL2, . . . , NCTLz respectively corresponding thereto.

FIG.11Ais a block diagram illustrating an example embodiment of a memory system ofFIG.10.FIG.11Bis a diagram for describing a power noise transmitter included in a reference voltage generation device ofFIG.11A.

Referring toFIGS.10and11A, a memory system700amay correspond to the memory system10-1ofFIG.10. The memory system700amay include a memory controller710aand a memory device730a, the memory controller710amay correspond to the memory controller100-1ofFIG.10, and the memory device730amay correspond to the memory device300-1ofFIG.10.

The memory system700amay include a plurality of channels and local reference voltage generation circuits corresponding to the plurality of channels. For example, the plurality of channels may include the first channel CH1and the second channel CH2, and the local reference voltage generation circuits may include a first local reference voltage generation circuit790-11and a second local reference voltage generation circuit790-21.

The first local reference voltage generation circuit790-11may receive (1-1)-th power noise information that corresponds to the first channel CH1and includes the first noise signal nds1from a (1-1)-th noise information generation circuit including a power noise transmitter710-11and a power noise receiver750-11. The first local reference voltage generation circuit790-11may correspond to the first channel CH1and may receive (1-2)-th power noise information including the third noise signal nds3from a (1-2)-th noise information generation circuit including a power noise transmitter710-12and a power noise receiver750-12.

The second local reference voltage generation circuit790-21may correspond to the second channel CH2and may receive (2-1)-th power noise information including the first noise signal nds1from a (2-1)-th noise information generation circuit including a power noise transmitter710-21and a power noise receiver750-21. The second local reference voltage generation circuit790-21may correspond to the second channel CH2and may receive (2-2)-th power noise information including the third noise signal nds3from a (2-2)-th noise information generation circuit including a power noise transmitter710-22and a power noise receiver750-22.

In an example embodiment, the (1-1)-th power noise information and the (2-1)-th power noise information may be identical or substantially identical to each other, and the (1-2)-th power noise information and the (2-2)-th power noise information may be identical or substantially identical to each other.

In an example embodiment, the (1-1)-th power noise information and the (2-1)-th power noise information may correspond to a first signal level of multi-level signaling that is performed between the memory controller710aand the memory device730a. The (1-2)-th power noise information and the (2-2)-th power noise information may correspond to a second signal level of the multi-level signaling.

Referring toFIGS.10,11A, and11B, the (1-1)-th noise information generation circuit may include the power noise transmitter710-11, and the power noise transmitter710-11may include a first resistor and a second resistor that are sequentially connected between a first power and a second power supplied to the memory controller710a. The (1-2)-th noise information generation circuit may include the power noise transmitter710-12, and the power noise transmitter710-12may include a third resistor and a fourth resistor that are sequentially connected between the first power and the second power. The (2-1)-th noise information generation circuit may include the power noise transmitter710-21, and the power noise transmitter710-21may include a fifth resistor and a sixth resistor that are sequentially connected between the first power and the second power. The (2-2)-th noise information generation circuit may include the power noise transmitter710-22, and the power noise transmitter710-22may include a seventh resistor and an eighth resistor that are sequentially connected between the first power and the second power.

In an example embodiment, first resistance values of the first resistor, the fourth resistor, the fifth resistor, and the eighth resistor may be identical or substantially identical to each other, and second resistance values of the second resistor, the third resistor, the sixth resistor, and the seventh resistor may be identical or substantially identical to each other. For example, as illustrated inFIG.11B, a magnitude of each of the first resistance values may be “R1”, and a magnitude of each of the second resistance values may be “R2”.

In an example embodiment, as illustrated inFIG.11B, each of the power noise transmitters710-11,710-12,710-13, and710-14may adjust resistance values of resistors included therein, based on one of the control signals NCTL1and NCTL2.

FIG.12Ais a block diagram illustrating an example embodiment of a memory system ofFIG.10.FIG.12Bis a diagram for describing a power noise transmitter included in a reference voltage generation device ofFIG.12A.

Referring toFIGS.10and12A, a memory system700bmay correspond to the memory system10-1ofFIG.10. The memory system700bmay include a memory controller710band a memory device730b, the memory controller710bmay correspond to the memory controller100-1ofFIG.10, and the memory device730bmay correspond to the memory device300-1ofFIG.10.

The memory system700bmay include a plurality of channels and local reference voltage generation circuits corresponding to the plurality of channels. For example, the plurality of channels may include the first channel CH1and the second channel CH2, and the local reference voltage generation circuits may include a third local reference voltage generation circuit790-13and a fourth local reference voltage generation circuit790-23.

The third local reference voltage generation circuit790-13may receive third power noise information that corresponds to the first channel CH1and includes the first noise signal nds1from a third noise information generation circuit including a power noise transmitter710-13and a power noise receiver750-13.

The fourth local reference voltage generation circuit790-23may receive fourth power noise information that corresponds to the second channel CH2and includes the third noise signal nds3from a fourth noise information generation circuit including a power noise transmitter710-23and a power noise receiver750-23.

In an example embodiment, each of the third and fourth local reference voltage generation circuits may further receive power noise information from a noise information generation circuit corresponding to the other channel, not the corresponding channel. For example, the third local reference voltage generation circuit790-13may further receive the third power noise information including the third noise signal nds3from the fourth noise information generation circuit, and the fourth local reference voltage generation circuit790-23may further receive the fourth power noise information including the first noise signal nds1from the third noise information generation circuit.

In an example embodiment, the third power noise information and the fourth power noise information may be different from each other.

In an example embodiment, the third power noise information may correspond to a first signal level of multi-level signaling that is performed between the memory controller710band the memory device730b. The fourth power noise information may correspond to a second signal level of the multi-level signaling.

Referring toFIGS.10,12A, and12B, the third noise information generation circuit may include the power noise transmitter710-13, and the power noise transmitter710-13may include a ninth resistor and a tenth resistor that are sequentially connected between a first power and a second power supplied to the memory controller710b. The fourth noise information generation circuit may include the power noise transmitter710-23, and the power noise transmitter710-23may include an eleventh resistor and a twelfth resistor that are sequentially connected between the first power and the second power.

In an example embodiment, resistance values of the ninth and twelfth resistors may be identical or substantially identical to each other, and resistance values of the tenth and eleventh resistors may be identical or substantially identical to each other. For example, as illustrated inFIG.12B, a magnitude of each of the resistance values of the ninth resistor and the twelfth resistor may be “R1”, and a magnitude of each of the resistance values of the tenth resistor and the eleventh resistor may be “R2”.

In an example embodiment, as illustrated inFIG.12B, each of the power noise transmitters710-13and710-23may adjust resistance values of resistors included therein, based on one of the control signals NCTL1and NCTL2.

In an example embodiment, the third local reference voltage generation circuit790-13and the fourth local reference voltage generation circuit790-23may share the third power noise information and the fourth power noise information.

FIG.13Ais a block diagram illustrating an example embodiment of a memory system ofFIG.10.FIG.13Bis a diagram for describing a power noise transmitter included in a reference voltage generation device ofFIG.13A.

Referring toFIGS.10and13A, a memory system700cmay correspond to the memory system10-1ofFIG.10. The memory system700cmay include a memory controller710cand a memory device730c, the memory controller710cmay correspond to the memory controller100-1ofFIG.10, and the memory device730cmay correspond to the memory device300-1ofFIG.10.

The memory system700cmay include a plurality of channels and local reference voltage generation circuits corresponding to the plurality of channels. For example, the plurality of channels may include the first channel CH1, the second channel CH2, and the third channel CH3, and the local reference voltage generation circuits may include a fifth local reference voltage generation circuit790-15, a sixth local reference voltage generation circuit790-26, and a seventh local reference voltage generation circuit790-37.

The fifth local reference voltage generation circuit790-15may receive fifth power noise information that corresponds to the first channel CH1and includes the first noise signal nds1from a fifth noise information generation circuit including a power noise transmitter710-15and a power noise receiver750-15.

The sixth local reference voltage generation circuit790-26may receive sixth power noise information that corresponds to the second channel CH2and includes the second noise signal nds2from a sixth noise information generation circuit including a power noise transmitter710-26and a power noise receiver750-26.

The seventh local reference voltage generation circuit790-37may receive seventh power noise information that corresponds to the third channel CH3and includes the third noise signal nds3from a seventh noise information generation circuit including a power noise transmitter710-37and a power noise receiver750-37.

In an example embodiment, each of the fifth to seventh local reference voltage generation circuits may further receive power noise information from a noise information generation circuit corresponding to any other channel, not the corresponding channel. For example, the fifth local reference voltage generation circuit790-15may further receive the sixth power noise information including the second noise signal nds2from the sixth noise information generation circuit and may further receive the seventh power noise information including the third noise signal nds3from the seventh noise information generation circuit. The sixth local reference voltage generation circuit790-26may further receive the fifth power noise information including the first noise signal nds1from the fifth noise information generation circuit and may further receive the seventh power noise information including the third noise signal nds3from the seventh noise information generation circuit. The seventh local reference voltage generation circuit790-37may further receive the fifth power noise information including the first noise signal nds1from the fifth noise information generation circuit and may further receive the sixth power noise information including the second noise signal nds2from the sixth noise information generation circuit.

In an example embodiment, the fifth power noise information, the sixth power noise information, and the seventh power noise information may be different from each other.

In an example embodiment, the fifth power noise information may correspond to a first signal level of multi-level signaling that is performed between the memory controller710cand the memory device730c. The sixth power noise information may correspond to a second signal level of the multi-level signaling. The seventh power noise information may correspond to a third signal level of the multi-level signaling.

Referring toFIGS.10,13A, and13B, the fifth noise information generation circuit may include the power noise transmitter710-15, and the power noise transmitter710-15may include a 13rd resistor and a 14th resistor that are sequentially connected between a first power and a second power supplied to the memory controller710c. The sixth noise information generation circuit may include the power noise transmitter710-26, and the power noise transmitter710-26may include a 15th resistor and a 16th resistor that are sequentially connected between the first power and the second power. The seventh noise information generation circuit may include the power noise transmitter710-37, and the power noise transmitter710-37may include a 17th resistor and a 18th resistor that are sequentially connected between the first power and the second power.

In an example embodiment, resistance values of the 13rd resistor and the 18th resistor may be identical or substantially identical to each other, resistance values of the 14th resistor and the 17th resistor may be identical or substantially identical to each other, and resistance values of the 15th resistor and the 16th resistor may be identical or substantially identical to each other. For example, as illustrated inFIG.13B, a magnitude of each of the resistance values of the 13rd resistor and the 18th resistor may be “R1”, a magnitude of each of the resistance values of the 14th resistor and the 17th resistor may be “R2”, and a magnitude of each of the resistance values of the 15th resistor and the 16th resistor may be “R3”.

In an example embodiment, as illustrated inFIG.13B, each of the power noise transmitters710-15,710-26, and710-37may adjust resistance values of resistors included therein, based on one of the control signals NCTL1, NCTL2, and NCTL3.

In an example embodiment, the fifth local reference voltage generation circuit790-15, the sixth local reference voltage generation circuit790-26, and the seventh local reference voltage generation circuit790-37may share the fifth power noise information, the sixth power noise information, and the seventh power noise information.

In the example embodiments described with reference toFIGS.11A,11B,12A,12B,13A, and13B, local reference voltage generation circuits may respectively correspond to a plurality of channels, and each of the local reference voltage generation circuits may provide reference voltages to sub-memory devices associated with the corresponding one of the plurality of channels. However, the example embodiments are not limited thereto. In an example embodiment, the local reference voltage generation circuits may respectively correspond to a plurality of dies; in another example embodiment, the local reference voltage generation circuits may respectively correspond to a plurality of packages.

FIGS.14,15, and16are graphs illustrating results of performing simulation on a reference voltage generation device ofFIG.1.

InFIGS.14,15, and16, Case1refers to a case of not generating both the first power noise pns1and the second power noise pns2described with reference toFIGS.1,7, and8, Case2refers to a case of generating only the first power noise pns1, and Case3refers to a case of generating only the second power noise pns2. Case4refers to a case of generating all the first and second power noises pns1and pns2, with the first power noise pns1and the second power noise pns2being in phase, and Case5refers to a case of generating all the first and second power noises pns1and pns2, with the first power noise pns1and the second power noise pns2being out of phase.

InFIGS.14,15, and16, there are illustrated results of measuring the eye heights EH3, EH2, EH1through the simulation performed for each of the following cases: the case w/o_VREF_H where the power noise transmitter (e.g.,210b) described with reference toFIG.7does not include all the resistors RPU and RPD, the case w_SVREF_H where the power noise transmitter includes the resistor RPU and does not include the resistor RPD, the case w_DVREF_H where the power noise transmitter includes all the resistors RPU and RPD and is configured as illustrated inFIG.11A, and the case w/p DVREF_H where the power noise transmitter includes all the resistors RPU and RPD and is configured as illustrated inFIG.12A.FIG.14illustrates a result of measuring the eye height EH3,FIG.15illustrates a result of measuring the eye height EH2, andFIG.16illustrates a result of measuring the eye height EH1. That is, the “w/o_VREF_H” case corresponds to the case where all the first and second power noises are not removed from a signal transmitted to a memory device through a communication line after encoded by the PAM4 signaling scheme, and the “w_SVREF_H” case corresponds to the case where only the first power noise is removed from a signal transmitted to the memory device. The “w_DVREF_H” and “w/p DVREF_H” cases correspond to the case where the first and second power noises are removed from a signal transmitted to the memory device in different schemes.

It is confirmed fromFIG.14that the eye heights EH3corresponding to the “w_SVREF_H” case where only the first power noise is removed and the “w_DVREF_H” and “w/p DVREF_H” cases where all the first and second power noises are removed appear to be larger than that corresponding to the “w/o_VREF_H” case where all the first and second power noises are not removed.

It is confirmed fromFIG.15that the eye height EH2corresponding to the “w_SVREF_H” case where only the first power noise is removed appears to be larger than that corresponding to the “w/o_VREF_H” case where all the first and second power noises are not removed and that the eye heights EH2corresponding to the “w_DVREF_H” and “w/p DVREF_H” cases where all the first and second power noises are removed appear to be larger than that corresponding to the “w_SVREF_H” case where only the first power noise is removed.

It is confirmed fromFIG.16that the eye height EH1corresponding to the c′w_SVREF_H″ case where only the first power noise is removed appears to be larger than that corresponding to the “w/o_VREF_H” case where all the first and second power noises are not removed and the eye height EH1corresponding to the “w_DVREF_H” and “w/p DVREF_H” cases where all the first and second power noises are removed appear to be larger than that corresponding to the “w_SVREF_H” case where only the first power noise is removed.

The eye height EH3among the eye heights EH1, EH2, and EH3may be more susceptible to the first power noise among the first power noise and the second power noise, and the eye height EH1may be more susceptible to the second power noise. In the simulation of measuring the eye height EH3(refer toFIG.14), the “w_DVREF_H” and “w/p DVREF_H” cases where all the first and second power noises are removed may show a small performance difference, compared to the “w_SVREF_H” case where only the first power noise is removed; in the simulations of measuring the eye heights EH1and EH2(refer toFIGS.15and16), the “w_DVREF_H” and “w/p DVREF_H” cases where all the first and second power noises are removed may show a significant performance difference, compared to the “w_SVREF_H” case where only the first power noise is removed.

FIG.17is a flowchart illustrating a reference voltage generation method according to an example embodiment of the present disclosure.

Referring toFIG.17, in the reference voltage generation method according to an example embodiment of the inventive concepts, a first power noise and a second power noise are received (S100).

In an example embodiment, the first power noise and the second power noise may be received from an external electronic device.

Power noise information is generated based on the first power noise and the second power noise (S300).

In an example embodiment, the first power noise may refer to a power noise that is generated based on a first power and is propagated through a communication line, and the second power noise may refer to a power noise that is generated based on a second power and is propagated through the communication line.

In an example embodiment, the first power and the second power may be powers that are supplied to the external electronic device.

In an example embodiment, operation S100and operation S300may be performed by a noise information generation device (e.g.,400ofFIG.1).

Reference voltages for multi-level signaling are generated based on the power noise information (S500).

In an example embodiment, operation S500may be performed by a reference voltage generation circuit (e.g.,310ofFIG.1).

FIG.18is a block diagram illustrating a memory system according to an example embodiment of the inventive concepts.

Referring toFIG.18, a memory system1000may include a memory device1300and a memory controller1400. The memory device1300may correspond to one of memory devices, which communicates with the memory controller1400based on one of the plurality of channels CH1to CHz described with reference toFIG.10. The memory controller1400may correspond to one of the first electronic devices100and100aofFIGS.1and2or may correspond to one of the memory controllers100b,100-1,710a,710b, and710cofFIGS.3,10,11A,12A, and13A.

The memory device1300may include first to eighth pins P11to P18, a memory interface circuitry1310, a control logic circuitry1320, and a memory cell array1330.

The memory interface circuitry1310may receive a chip enable signal nCE from the memory controller1400through the first pin P11. The memory interface circuitry1310may transmit and receive signals to and from the memory controller1400through the second to eighth pins P12to P18in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enable state (e.g., a low level), the memory interface circuitry1310may transmit and receive signals to and from the memory controller1400through the second to eighth pins P12to P18.

The memory interface circuitry1310may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller1400through the second to fourth pins P12to P14. The memory interface circuitry1310may receive a data signal DQ from the memory controller1400through the seventh pin P17or transmit the data signal DQ to the memory controller1400. A command CMD, an address ADDR, and data may be transmitted via the data signal DQ. For example, the data signal DQ may be transmitted through a plurality of data signal lines. In some example embodiments, the seventh pin P17may include a plurality of pins respectively corresponding to a plurality of data signals DQ(s).

In an example embodiment, the data signal DQ may be a signal encoded by the multi-level signaling scheme described above with reference toFIG.1. For example, the multi-level signaling scheme may be a PAM4 signaling scheme.

The memory interface circuitry1310may obtain the command CMD from the data signal DQ, which is received in an enable section (e.g., a high-level state) of the command latch enable signal CLE based on toggle time points of the write enable signal nWE. The memory interface circuitry1310may obtain the address ADDR from the data signal DQ, which is received in an enable section (e.g., a high-level state) of the address latch enable signal ALE based on the toggle time points of the write enable signal nWE.

In an example embodiment, the write enable signal nWE may be maintained at a static state (e.g., a high level or a low level) and toggle between the high level and the low level. For example, the write enable signal nWE may toggle in a section in which the command CMD or the address ADDR is transmitted. Thus, the memory interface circuitry1310may obtain the command CMD or the address ADDR based on toggle time points of the write enable signal nWE.

The memory interface circuitry1310may receive a read enable signal nRE from the memory controller1400through the fifth pin P15. The memory interface circuitry1310may receive a data strobe signal DQS from the memory controller1400through the sixth pin P16or transmit the data strobe signal DQS to the memory controller1400.

In a data (DATA) output operation of the memory device1300, the memory interface circuitry1310may receive the read enable signal nRE, which toggles through the fifth pin P15, before outputting the data DATA. The memory interface circuitry1310may generate the data strobe signal DQS, which toggles based on the toggling of the read enable signal nRE. For example, the memory interface circuitry1310may generate a data strobe signal DQS, which starts toggling after a predetermined delay (e.g., tDQSRE), based on a toggling start time of the read enable signal nRE. The memory interface circuitry1310may transmit the data signal DQ including the data DATA based on a toggle time point of the data strobe signal DQS. Thus, the data DATA may be aligned with the toggle time point of the data strobe signal DQS and transmitted to the memory controller1400.

In a data (DATA) input operation of the memory device1300, when the data signal DQ including the data DATA is received from the memory controller1400, the memory interface circuitry1310may receive the data strobe signal DQS, which toggles, along with the data DATA from the memory controller1400. The memory interface circuitry1310may obtain the data DATA from the data signal DQ based on toggle time points of the data strobe signal DQS. For example, the memory interface circuitry1310may sample the data signal DQ at rising and falling edges of the data strobe signal DQS and obtain the data DATA.

The memory interface circuitry1310may transmit a ready/busy output signal nR/B to the memory controller1400through the eighth pin P18. The memory interface circuitry1310may transmit state information of the memory device1300through the ready/busy output signal nR/B to the memory controller1400. When the memory device1300is in a busy state (e.g., when operations are being performed in the memory device1300), the memory interface circuitry1310may transmit a ready/busy output signal nR/B indicating the busy state to the memory controller1400. When the memory device1300is in a ready state (e.g., when operations are not performed or completed in the memory device1300), the memory interface circuitry1310may transmit a ready/busy output signal nR/B indicating the ready state to the memory controller1400. For example, while the memory device1300is reading data DATA from the memory cell array1330in response to a page read command, the memory interface circuitry1310may transmit a ready/busy output signal nR/B indicating a busy state (e.g., a low level) to the memory controller1400. For example, while the memory device1300is programming data DATA to the memory cell array1330in response to a program command, the memory interface circuitry1310may transmit a ready/busy output signal nR/B indicating the busy state to the memory controller1400.

The control logic circuitry1320may control all operations of the memory device1300. The control logic circuitry1320may receive the command/address CMD/ADDR obtained from the memory interface circuitry1310. The control logic circuitry1320may generate control signals for controlling other components of the memory device1300in response to the received command/address CMD/ADDR. For example, the control logic circuitry1320may generate various control signals for programming data DATA to the memory cell array1330or reading the data DATA from the memory cell array1330. For example, the control logic circuitry1320may further generate the control signal NCTL described above with reference toFIG.1.

The memory cell array1330may store the data DATA obtained from the memory interface circuitry1310, via the control of the control logic circuitry1320. The memory cell array1330may output the stored data DATA to the memory interface circuitry1310via the control of the control logic circuitry1320.

The memory cell array1330may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the example embodiments are not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, an example embodiment in which the memory cells are NAND flash memory cells will mainly be described.

The memory controller1400may include first to eighth pins P21to P28and a controller interface circuitry1410. The first to eighth pins P21to P28may respectively correspond to the first to eighth pins P11to P18of the memory device1300.

The controller interface circuitry1410may transmit a chip enable signal nCE to the memory device300through the first pin P21. The controller interface circuitry1410may transmit and receive signals to and from the memory device1300, which is selected by the chip enable signal nCE, through the second to eighth pins P22to P28.

The controller interface circuitry1410may transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device1300through the second to fourth pins P22to P24. The controller interface circuitry1410may transmit or receive the data signal DQ to and from the memory device1300through the seventh pin P27.

The controller interface circuitry1410may transmit the data signal DQ including the command CMD or the address ADDR to the memory device1300along with the write enable signal nWE, which toggles. The controller interface circuitry1410may transmit the data signal DQ including the command CMD to the memory device1300by transmitting a command latch enable signal CLE having an enable state. Also, the controller interface circuitry1410may transmit the data signal DQ including the address ADDR to the memory device1300by transmitting an address latch enable signal ALE having an enable state.

The controller interface circuitry1410may transmit the read enable signal nRE to the memory device1300through the fifth pin P25. The controller interface circuitry1410may receive or transmit the data strobe signal DQS from or to the memory device1300through the sixth pin P26.

In a data (DATA) output operation of the memory device1300, the controller interface circuitry410may generate a read enable signal nRE, which toggles, and transmit the read enable signal nRE to the memory device1300. For example, before outputting data DATA, the controller interface circuitry1410may generate a read enable signal nRE, which is changed from a static state (e.g., a high level or a low level) to a toggling state. Thus, the memory device1300may generate a data strobe signal DQS, which toggles, based on the read enable signal nRE. The controller interface circuitry1410may receive the data signal DQ including the data DATA along with the data strobe signal DQS, which toggles, from the memory device1300. The controller interface circuitry1410may obtain the data DATA from the data signal DQ based on a toggle time point of the data strobe signal DQS.

In a data (DATA) input operation of the memory device1300, the controller interface circuitry1410may generate a data strobe signal DQS, which toggles. For example, before transmitting data DATA, the controller interface circuitry1410may generate a data strobe signal DQS, which is changed from a static state (e.g., a high level or a low level) to a toggling state. The controller interface circuitry1410may transmit the data signal DQ including the data DATA to the memory device1300based on toggle time points of the data strobe signal DQS.

The controller interface circuitry1410may receive a ready/busy output signal nR/B from the memory device1300through the eighth pin P28. The controller interface circuitry1410may determine state information of the memory device1300based on the ready/busy output signal nR/B.

As described above, a reference voltage generation device and a memory system according to some example embodiments of the inventive concepts may generate power noise information based on power noises that are generated based on both a first power and a second power supplied to an external electronic device and are propagated through a communication line. In the case of decoding multi-level signals, reference voltages may be generated based on the power noise information, and all the power noises that are based on both the first power and the second power may be removed based on the reference voltages. This may mean that the decoding error is inhibited or prevented.

The reference voltage generation device and the memory system according to some example embodiments of the inventive concepts may generate the power noise information without the addition of separate pins/pads.

It will be understood that elements and/or properties thereof described herein as being “substantially” the same and/or identical encompasses elements and/or properties thereof that have a relative difference in magnitude that is equal to or less than 10%. Further, regardless of whether elements and/or properties thereof are modified as “substantially,” it will be understood that these elements and/or properties thereof should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated elements and/or properties thereof.

One or more of the elements disclosed above may include or be implemented in one or more processing circuitries such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitries more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FGPA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

While the inventive concepts have been described with reference to example embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the scope of the example embodiments.