Patent ID: 12218084

DETAILED DESCRIPTION

Embodiments of an overvoltage protection device that comprises a voltage blocking device and a trenched connector formed within a semiconductor body are described herein. The voltage blocking device may be configured as an ESD protection device that allows an applied potential between the first and second contact pads to deviate within a defined voltage range while clamping the applied potential if it falls outside the allowable voltage range. According to an embodiment, the voltage blocking device is a vertical voltage blocking device that is connected between the first contact pad and a substrate region of the semiconductor body, and the trenched connector provides an electrical connection between the substrate region and the second contact pad. This arrangement facilitates a vertical diode structure and the performance benefits flowing therefrom in a chip-scale package at low cost and with low area consumption.

Separately or in combination, a semiconductor device that comprises a trenched connector formed within a semiconductor body is described herein. The trenched connector may comprise a metal electrode disposed within a trench and a doped sidewall region lining sidewalls of the trench. The metal electrode may form a conductive connection between a subjacent semiconductor region and a contact pad disposed on a surface of the semiconductor body. According to an embodiment, the doped sidewall region forms part of an active device region, e.g., anode, cathode, emitter, collector, etc., of an active semiconductor device. This arrangement allows for an operational current of the active semiconductor device to flow in multiple directions, i.e., in a lateral direction and in a vertical direction. As a result, important device parameters such as capacitance, resistance, and area consumption can be improved.

Referring toFIG.1, an overvoltage protection device100is shown, according to an embodiment. The overvoltage protection device100is formed in a semiconductor body102. The semiconductor body102may generally comprise standard semiconductor materials. According to an embodiment, the semiconductor body102is a silicon-based semiconductor body.

The semiconductor body102comprises a substrate region104disposed beneath an upper surface106of the semiconductor body102. The substrate region104can correspond to a bulk substrate, such as a silicon wafer, that is used to form epitaxial material thereon. The substrate region104can have a first conductivity type (e.g., n-type), and can be highly doped, e.g., having a net dopant concentration of between 1018dopant atoms/cm3and 1020dopant atoms/cm3. As shown, the substrate region104may extend to a rear surface108of the semiconductor body102that is opposite from the upper surface106. Alternatively, the substrate region104may be provided over another part of the semiconductor body102(not shown).

The semiconductor body102comprises a buried layer110and a low-doped region112. The buried layer110is arranged between the substrate region104and the low-doped region112. The low-doped region112is arranged between the buried layer110and the upper surface106of the semiconductor body102. The buried layer110may have the same first conductivity type as the substrate region104(e.g., n-type). The buried layer110may have a net dopant concentration that is lower than the substrate region104. For example, the buried layer110may have a net dopant concentration of between 1015dopant atoms/cm3and 1018dopant atoms/cm3. The low-doped region112may have a net dopant concentration that is lower than the buried layer110and the substrate region104. For example, the low-doped region112may have a dopant concentration of no greater than 1015dopant atoms/cm3and more typically in the range of 1011dopant atoms/cm3to 1013dopant atoms/cm3, which may correspond to the intrinsic dopant concentration of semiconductor material that is not intentionally doped. The low-doped region112may have either a first conductivity type (e.g., n-type) or a second conductivity type (e.g., p-type) opposite from the first conductivity type. The low-doped region112may be an epitaxial region of semiconductor material, e.g., silicon, that is formed on top of the substrate region104by an epitaxy process. The buried layer110may correspond to a portion of the epitaxial material which forms the low-doped region112and is more heavily doped by a specific doping process. Alternatively, buried layer110may correspond to a part of the substrate region104that is created by a doping process.

The overvoltage protection device100comprises an interlayer dielectric114disposed on the upper surface106of the semiconductor body102. The interlayer dielectric114can comprise passivation materials and/or electric isolation materials. For example, the interlayer dielectric114can comprise SiO2(silicon dioxide), Si3N4(silicon nitride), SiOXNy (silicon oxynitride), etc. The interlayer dielectric114can comprise multiple layers of the same or different material.

The overvoltage protection device100comprises first and second contact pads116,118disposed over the upper surface106of the semiconductor body102. As shown, the first and second contact pads116,118are formed on the interlayer dielectric114and are therefore separated from the semiconductor body102by the interlayer dielectric114. The first and second contact pads116,118may each be formed from an electrically conductive material, e.g., copper, aluminum, nickel, and alloys thereof. The first and second contact pads116,118may be configured as externally accessible points of electrical contact that can be contacted by an interconnect structure such as a bond wire, clip, ribbon, solder etc.

The overvoltage protection device100comprises a conductive interconnect layer120and conductive vias122disposed within the interlayer dielectric114. The conductive interconnect layer120may be formed on the upper surface106of the semiconductor body102and comprises an electrically conducive material such as copper, aluminum or highly doped polysilicon. The conductive interconnect layer120is structured into pad regions that are used to form lower-level electrical interconnect and/or to effectuate a vertical connection through the interlayer dielectric114. The conductive vias122may be trenched contact structures in the interlayer dielectric114that are filled with a conductive material, e.g., tungsten, aluminum, copper, polysilicon, etc. As shown, the conductive interconnect layer120and conductive vias122are used in combination to provide a vertical electrical connection between the upper surface106of the semiconductor body102and the first and second contact pads116,118.

The overvoltage protection device100comprises a vertical voltage blocking device124formed in the semiconductor body102. The vertical voltage blocking device124comprises a first voltage blocking device126and a second voltage blocking device128. The first voltage blocking device126comprises a first doped region130that extends from the upper surface106of the semiconductor body102into the low-doped region112and a first buried doped region132that is arranged between the low-doped region112and the buried layer110. The first doped region130may be a first conductivity type region (e.g., n-type) with a net dopant concentration of between 1017dopant atoms/cm3to 1020dopant atoms/cm3, for example. The first buried doped region132may be a second conductivity type region (e.g., p-type) with a net dopant concentration of at least 1015dopant atoms/cm3and more typically in the range of 1017dopant atoms/cm3to 1019dopant atoms/cm3, for example. The second voltage blocking device128comprises a second doped region134that extends from the upper surface106of the semiconductor body102into the low-doped region112and a second buried doped region136that is arranged between the low-doped region112and the buried layer110. The second doped region134may be a second conductivity type region (e.g., p-type) with a net dopant concentration of between 1017dopant atoms/cm3to 1020dopant atoms/cm3, for example. The second buried doped region136may be a first conductivity type region (e.g., n-type) with a net dopant concentration of at least 1015dopant atoms/cm3and more typically in the range of 1017dopant atoms/cm3to 1019dopant atoms/cm3, for example.

The first and second voltage blocking devices126,128are each connected between the second contact pad118and the substrate region104in an antiparallel configuration, meaning that the first voltage blocking device126is forward biased while the second voltage blocking device128is reverse biased, and vice-versa. The first voltage blocking device126is arranged to conduct a vertical current138flowing from the substrate region104to the second contact pad118. The second voltage blocking device128is arranged to conduct a vertical current140flowing from the second contact pad118to the substrate region104.

The overvoltage protection device100comprises trenched connectors142formed in the semiconductor body102. The trenched connectors142each comprise a trench144that is formed in the upper surface106of the semiconductor body102and extends to the substrate region104, and a metal electrode146disposed within the trench144. The metal electrode146may be formed from or comprise tungsten, aluminum, copper, nickel, etc., and other highly conductive metals, for example. The metal electrode146forms an electrically conductive connection between the first contact pad116and the substrate region104. That is, the metal electrode146provides a low resistance ohmic connection for current flow between the first contact pad116and the substrate region104. As can be seen, the metal electrode146may contact a structured part of the interconnect layer120, which in turn is electrically connected to the first contact pad116.

According to an embodiment, the trenched connectors142comprise a doped sidewall region148lining sidewalls of the trench144. The doped sidewall region148may be a first conductivity type region (e.g., n-type) with a relatively high dopant concentration, e.g., a net dopant concentration of between 1018dopant atoms/cm3and 1021dopant atoms/cm3. This facilitates a low-ohmic connection between the metal electrode146and the substrate region104. Generally speaking, the trench144can be formed by a variety of techniques including wet or dry etching techniques. The doped sidewall region148may be created by implanting dopant atoms into a sidewall and bottom of the trench144after formation of the trench144, for example.

The overvoltage protection device100comprises electrical isolation structures150that extend from the upper surface106of the semiconductor body102into the substrate region104. The electrical isolation structures150surround and laterally electrically isolate the first voltage blocking device126and the second voltage blocking device128such that the vertical current138of the first voltage blocking device126flows through a first laterally isolated region of the semiconductor body102and such that the vertical current140of the second voltage blocking device128flows through a second laterally isolated region of the semiconductor body102. That is, the electrical isolation structures150form an enclosure around the active regions of the first voltage blocking device126and the second voltage blocking device128. As a result, the vertical current138and the vertical current140are laterally isolated from potentially interfering fields and/or currents within laterally adjacent regions of the semiconductor body102

In the depicted embodiment, the electrical isolation structures150are provided by a plurality of isolation trenches152that extend from the upper surface106of the semiconductor body102into the substrate region104. The isolation trenches152are at least partially filled by or lined with an electrically insulating material. For example, the isolation trenches152can comprise silicon-based insulators such as SiO2(silicon dioxide), Si3N4(silicon nitride), SiOXNy (silicon oxynitride), etc. The isolation trenches152can be completely filled by the electrically insulating material. Alternatively, the isolation trenches152can comprise a conductive structure such as a metal or highly doped polysilicon that is separated from the adjacent semiconductor body102by dielectric material. These conductive structures can be configured as an electrical shielding element, for example.

Referring toFIG.2, an equivalent circuit schematic of the overvoltage protection device100is shown. The substrate region104forms a node of the circuit that is connected to the vertical voltage blocking device124and the trenched connector142. The first voltage blocking device126comprises a blocking diode154and a forward diode156arranged in an anti-serial configuration. These devices result from an open base bipolar transistor (i.e., an NPN structure or a PNP structure) that is realized by the combination of the buried layer110, the first buried doped region132, the portion of the low-doped region112arranged between the first buried doped region132and the first doped region130. The blocking diode154may correspond to a p-n junction between the buried layer110and the first buried doped region132. The forward diode156may correspond to the combination of the first doped region130, the first buried doped region132, and an intervening part of the low-doped region112, which collectively can be regarded as a PIN diode. A PIN diode refers to a type of diode that comprises an intrinsic semiconductor region, e.g., a region of relatively low doped or undoped doped semiconductor material, interposed between a p-type anode region and an n-type cathode region. Meanwhile, the second voltage blocking device128results from a PIN diode that corresponds to the combination of the second buried doped region136, the portion of the low-doped region112arranged between the second buried doped region136and the second doped region134, and the second doped region134. In the case of the second voltage blocking device128.

The working principle of the overvoltage protection device100is as follows. The vertical voltage blocking device124and the trenched connector142collectively form a unidirectional voltage clamping device between the first and second contact pads116,118. A unidirectional voltage clamping device refers to a device wherein the clamping voltage is different in a forward bias direction than in a reverse bias direction. In this device, the negative clamping voltage of the device at a negative bias between the first and second contact pads116,118is defined by the second voltage blocking device128. When the negative bias between the first and second contact pads116,118exceeds the forward conduction voltage of the second voltage blocking device128, the second voltage blocking device128conducts the vertical current140flowing from the second contact pad118to the substrate region104, and the trenched connector142forms a conduction path for this current to flow from the substrate region104to the first contact pad116. The positive clamping voltage of the unidirectional voltage clamping device at a positive bias between the first and second contact pads116,118is defined by the first voltage blocking device126. When the positive bias between the first and second contact pads116,118exceeds the reverse conduction voltage of the first voltage blocking device126and the forward conduction voltage of the forward diode156, the first voltage blocking device126becomes conductive. In this state, the first voltage blocking device126conducts the vertical current138flowing from the substrate region104to the second contact pad118, and the trenched connector142forms a conduction path for this current to flow from the first contact pad116to the substrate region104.

Referring toFIG.3, a plan-view layout of the overvoltage protection device100is shown, according to an embodiment. In this arrangement, the first and second voltage blocking devices126,128are configured such that the active regions of these devices form an enclosed area that is underneath the second contact pad118. These active regions are enclosed by circular shaped electrical isolation structures150, thus forming circular isolated portions of the semiconductor body102for the first and second vertical currents138,150to flow between the second contact pad118and the substrate region104. The trenched connectors142are formed to enclose the circular shaped electrical isolation structures150with a similar circular geometry. As can be seen, the trenched connectors142can be formed in very close proximity to the active areas of the first and second voltage blocking devices126,128. For example, a separation distance between the electrical isolation structures150and the trenched connector142may correspond to a minimum dimension of the processing techniques (e.g., trench formation) used to form the trenched connector142and the electrical isolation structures150. The electrical connection between the metal electrodes146of the trenched connector142and the first contact pad116may be effectuated using a structured span of the conductive interconnect layer120that forms a ring over the metal electrodes146and extends from underneath the second contact pad118from underneath the first contact pad116. The layout shown inFIG.3advantageously minimizes the lateral portion of the substrate region104that current must flow between the first and second voltage blocking devices126,128and the trenched connector142, thereby lowering the electrical resistance and capacitance of the device.

Referring toFIG.4, an overvoltage protection device100is shown, according to another embodiment. The overvoltage protection device100may have the following differences from the embodiment described with reference toFIG.1. In this embodiment, the electrical isolation structures150are replaced by the trenched connectors142. That is, the trenched connectors142serve a dual role. First, the trenched connectors142serve their previously described function of providing the electrical connection between the substrate region104and the first contact pad116. The trenched connectors142provide electrical isolation for the first and second voltage blocking devices126,128akin to the electrical isolation structures150as previously described. The electrodes146of the trenched connectors142may serve as shielding structures to provide this electrical isolation.

In the embodiment ofFIG.4, the first voltage blocking device126can operate in the same way as the embodiment ofFIG.1, i.e., as an open base bipolar transistor connected between the second contact pad118and the substrate region104. As can be seen, a separation distance is provided between the first buried doped region132and the doped sidewall region148of the trenched connectors142. This ensures that the p-n junction between the first buried doped region132and the buried layer110effectively operates as the blocking diode154.

In the embodiment ofFIG.4, the second voltage blocking device128can operate in the same way as the embodiment ofFIG.1, i.e., as a PIN diode, with the following exception. Instead of having a vertical current140that flows exclusively in a vertical direction, the second voltage blocking device128is configured to conduct a multi-directional current158in a forward conduction mode of the device. This multi-directional current158comprises a vertical component that flows into the second buried doped region136in a similar manner as described above. Additionally, this multi-directional current158comprises a lateral component that flows laterally across the across sidewalls of the connection trench144and into the metal electrode146. This multi-directional current158results from the fact that the doped sidewall regions148of the trenched connectors142adjoining the second voltage blocking device128have the same conductivity type as the second buried doped region136and thus form an extension of the second buried doped region136. Thus, the effective area from which carriers can flow into an active region of the device (in this example the cathode of the PIN diode) is increased.

A semiconductor device that comprises the trenched connector142with the doped sidewall regions148as an active region of the device that conducts an operational current of the device may have a variety of different configurations in addition to the specific overvoltage protection device embodiments described herein. Examples of devices that may comprise the trenched connector142include without being limited to: a Zener diode, an open base bipolar transistor (i.e., an NPN or PNP structure), an open base thyristor (i.e., an NPNP or PNPN structure), a vertical MOSFET device, a vertical DMOS device, PIN diode, a PN diode, etc. In each case, a favorable increase to the effective area of the device can be realized by using the doped sidewall regions148as a substitute for or in combination with an active device region that conducts an operational current. Separately or in combination, the doped sidewall regions148may have multiple different regions of different conductivity type, e.g., alternating regions of p-type and n-type, so as to realize multiple active device regions as part of the trenched connector142.

Referring toFIG.5, an overvoltage protection device100is depicted, according to an embodiment. The overvoltage protection device100may have the following differences from the embodiments described with references toFIGS.1and4. The overvoltage protection device100in the embodiment ofFIG.5comprises a semiconductor body102that comprises a base region160and a plurality of semiconductor mesas162disposed on an upper surface161of the base region160. The base region160may comprise semiconductor materials such as, silicon (Si) and germanium (Ge), silicon carbide (SiC), etc. The base region160may comprise a bulk wafer, such as a silicon wafer, for example, with one or more semiconductor layers and/or dielectric layers disposed thereon. Separately or in combination, the base region160may comprise other electrical insulators, e.g., glass materials, molded epoxy material, resins, etc. As shown, the base region160comprises a dielectric layer164that extends to the upper surface161of the base region160. The dielectric layer164may comprise an insulator such as SiO2, Si3N4, SiOXNy, etc. The semiconductor mesas162are regions of semiconductor material that are formed on the base region160and are laterally isolated from one another by open regions. For example, the semiconductor mesas162may be formed by bonding one or more active semiconductor wafers onto a carrier. The active semiconductor wafers may be etched and/or multiple active semiconductor wafers may be bonded.

The overvoltage protection device100comprises first and second contact pads116,118that are disposed on upper surfaces163of two separate ones of the semiconductor mesas162. In the depicted embodiment, the first contact pad116is disposed on the upper surface of a first one of the mesas162and the second contact pad118is disposed on the upper surface162of a second mesa162that is laterally spaced apart from the first mesa162.

The overvoltage protection device100comprises a plurality of doped regions166that are formed in lower regions of the semiconductor mesas162. The doped regions166are formed at lower surfaces of the semiconductor mesas162that face the base region160. In the cross-sectional perspective ofFIG.5, the first one of the mesas162that comprises the first contact pad116disposed thereon comprises one of the doped regions166and a third one of the mesas162that is laterally between the first and second mesas162comprises one of the doped regions166. The doped regions166have a higher net dopant concentration than the adjacent semiconductor material within the semiconductor mesas162. For example, the semiconductor mesas162may have an underlying dopant concentration of no greater than 1015dopant atoms/cm3and more typically in the range of 1011dopant atoms/cm3to 1013dopant atoms/cm3, which may correspond to the intrinsic dopant concentration of semiconductor material that does not receive active or intentional doping processes. By contrast, the doped regions166may have a dopant concentration of between 1018dopant atoms/cm3to 1021dopant atoms/cm3, for example.

The overvoltage protection device100comprises a plurality of the trenched connectors142formed in the semiconductor mesas162. In a similar manner as described in the previous embodiments, the trenched connectors142comprise a trench144that is formed in an upper surface of the semiconductor mesas162and extends to the base region160, a metal electrode146disposed within the trench144, and a doped sidewall region148lining sidewalls of the trench144.

Some of the trenched connectors142of the overvoltage protection device100form voltage blocking devices168with the doped regions166. In the cross-sectional perspective ofFIG.5, the trenched connectors142in the first one of the mesas162that comprises the first contact pad116disposed thereon form a voltage blocking device168and the trenched connectors142in the third one of the mesas162that is laterally between the first and ones of the second mesas162form a voltage blocking device168. In these voltage blocking devices168, the doped regions166and the doped sidewall regions148may form the anode and cathode regions of the voltage blocking devices168(or vice-versa). To this end, the doped regions166may have a net first conductivity type (e.g., p-type), and the doped sidewall regions148may have a net second conductivity type opposite from the first conductivity type (e.g., n-type). The regions of the semiconductor mesas162between the doped regions166and the doped sidewall regions148may be relatively low-doped regions of the first or second conductivity type that form an intrinsic region of a PIN diode. The voltage blocking devices168configured as PIN diodes in this arrangement are configured to conduct a multi-directional current170. In a forward conduction state of the voltage blocking device168, the multi-directional current170flows laterally between the doped regions166and the doped sidewall regions148and spreads vertically from the lower region of the mesas162to higher parts of the trenched connectors142along the sidewalls of the trenches144. This arrangement favorably increases to the effective area of the device in a similar manner as described above. The above-described of the doped regions166and the trenched connectors142may form a unit cell such that any number of PIN diodes, e.g., two, three, four, etc. may be connected between the first and second contact pads116,118.

Some of the trenched connectors142of the overvoltage protection device100are used as connection elements for electrically connecting the voltage blocking devices168to the first and second contact pads116,118. As shown, the first semiconductor mesa162that comprises the second contact pad118disposed thereon comprises trenched connectors142that are used to electrically connect the second contact pad118to the base region160. The metal electrode146of the trenched connectors142forms a low-ohmic contact with a buried metallization layer172that is disposed within the dielectric layer164. The buried metallization layer172is structured into interconnect lines that facilitate electrical connection between the different semiconductor mesas162.

Referring toFIG.6, an equivalent electrical schematic of the overvoltage protection device100fromFIG.5is shown. The first contact pad116forms a first node of the circuit and the second contact pad118forms a second node of the circuit. The circuit comprises a first voltage blocking device126and a second voltage blocking device128connected between the first and second contact pads116,118in an antiparallel configuration. The first and second voltage blocking devices126,128each comprise a pair of the voltage blocking devices168formed by the trenched connectors142as shown inFIG.5. A forward clamping voltage of the overvoltage protection device100at a positive bias between the first and second contact pads116,118is determined by a forward conduction voltage of the first voltage blocking device126. A negative clamping voltage of the overvoltage protection device100at a negative bias between the first and second contact pads116,118is determined by a conduction voltage of the second voltage blocking device128. According to an embodiment, the overvoltage protection device100is a bidirectional device such that the positive and negative clamping voltages are the same.

Referring toFIG.7, a plan-view layout of the overvoltage protection device100is shown, according to an embodiment. The overvoltage protection device100comprises third and fourth ones of the semiconductor mesas162that are laterally between the first and second ones of the semiconductor mesas162which comprise the first and second contact pads116,118disposed thereon142. Each of the third and fourth ones of the semiconductor mesas162comprise one of the voltage blocking devices168formed by the trenched connectors142as shown inFIG.6. Additionally, one of the voltage blocking devices168formed by the trenched connectors142as shown inFIG.6is formed in each one of the first and second ones of the semiconductor mesas162which comprise the first and second contact pads disposed thereon142. Structured regions of the buried metallization layer172are used to provide the electrical connection between separate mesas162. As a result, the first and second voltage blocking devices126,128are realized by two sets of series connected voltage blocking devices168connected between the first and second contact pads116,118.

As can be seen, the voltage blocking devices168are realized by a layout comprising a plurality of the doped regions166, wherein each of these doped regions166have an elongated geometry and run parallel to one another. The trenched connectors142are arranged to have fingers with an elongated geometry that are interleaved between immediately adjacent ones of the doped regions166. As a result, when the diodes are in a forward conduction mode, a multi-directional current170, i.e., a current that flows in more than one direction, spreads laterally away from the doped regions166in multiple directions, thereby increasing the effective area of the device.

Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.

Example 1. An overvoltage protection device, comprising: a semiconductor body comprising a substrate region disposed beneath an upper surface of the semiconductor body; first and second contact pads disposed over the upper surface of the semiconductor body; a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector comprises a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.

Example 2. The overvoltage protection device of example 1, wherein the trenched connector further comprises a doped sidewall region lining sidewalls of the trench, and wherein the metal electrode directly adjoins the doped sidewall region and is in low-ohmic contact with the substrate region via the doped sidewall region.

Example 3. The overvoltage protection device of example 2, wherein the vertical voltage blocking device comprises a first voltage blocking device and a second voltage blocking device, wherein the first and second voltage blocking devices are connected between the second contact pad and the substrate region in an antiparallel configuration, wherein the first voltage blocking device is arranged to conduct a vertical current flowing from the substrate region to the second contact pad, wherein the second voltage blocking device is arranged to conduct a vertical current flowing from the second contact pad to the substrate.

Example 4. The overvoltage protection device of example 3, wherein the semiconductor body comprises a low-doped region and a buried layer, wherein the buried layer is arranged between the substrate region and the low-doped region, wherein the low-doped region is arranged between the buried layer and the upper surface of the semiconductor body, and wherein buried layer has the same conductivity type as the substrate region and has a lower net dopant concentration than the substrate region.

Example 5. The overvoltage protection device of example 4, wherein the first voltage blocking device comprises a first doped region that extends from the upper surface of the semiconductor body into the low-doped region and a first buried doped region that is arranged between the low-doped region and the buried layer, wherein the second voltage blocking device comprises a second doped region that extends from the upper surface of the semiconductor body into the low-doped region and a second buried doped region that is arranged between the low-doped region and the buried layer.

Example 6. The overvoltage protection device of example 3, wherein the overvoltage protection device comprises electrical isolation structures that extend from the upper surface of the semiconductor body into the substrate region, wherein the electrical isolation structures surround and laterally electrically isolate the first voltage blocking device and the second voltage blocking device such that the current of the first voltage blocking device flows through a first laterally isolated region of the semiconductor body and such that the current of the second voltage blocking device flows through a second laterally isolated region of the semiconductor body.

Example 7. The overvoltage protection device of example 6, wherein the electrical isolation structures are separate from the trenched connector.

Example 8. The overvoltage protection device of example 6, wherein the electrical isolation structures comprise the trenched connector.

Example 9. The overvoltage protection device of example 8, wherein the trenched connector that surrounds and laterally electrically isolates the second voltage blocking device is arranged such that the second vertical current flows across sidewalls of the connection trench.

Example 10. An overvoltage protection device, comprising a semiconductor body comprising a substrate region disposed beneath an upper surface of the semiconductor body; first and second contact pads disposed over the upper surface of the semiconductor body; a trenched connector electrically connected between the first contact pad and the substrate region; and a unidirectional voltage clamping device formed in the semiconductor body and connected between the second contact pad and the substrate region.

Example 11. The overvoltage protection device of example 10, wherein the trenched connector comprises a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, a metal electrode disposed within the trench, and a doped sidewall region lining sidewalls of the trench, and wherein the metal electrode directly adjoins the doped sidewall region and is in low-ohmic contact with the substrate region via the doped sidewall region.

Example 12. The overvoltage protection device of example 11, wherein the unidirectional voltage clamping device comprises a first voltage blocking device and a second voltage blocking device, wherein the first and second voltage blocking devices are connected between the second contact pad and the substrate region in an antiparallel configuration, wherein a negative clamping voltage of the unidirectional device at a negative bias between the first and second contact pads is defined by the second voltage blocking device, and wherein a positive clamping voltage of the unidirectional device at a positive bias between the first and second contact pads is defined by the first voltage blocking device.

Example 13. The overvoltage protection device of example 12, wherein the first voltage blocking device is an open base bipolar transistor, and wherein the second voltage blocking device is a PIN diode.

Example 14. The overvoltage protection device of example 13, wherein the trenched connector is arranged immediately adjacent to an intrinsic region of the PIN diode such that a forward current of the PIN diode flows across sidewalls of the trench.

Example 15. An overvoltage protection device, comprising: a semiconductor body comprising a base region and a plurality of semiconductor mesas disposed on an upper surface of the base region; first and second contact pads disposed on upper surfaces of separate ones of the semiconductor mesas; a plurality of doped regions formed at lower surfaces of the semiconductor mesas, the lower surfaces of the semiconductor mesas facing the base region; and a plurality of trenched connectors formed in the semiconductor mesas, wherein each of the trenched connectors comprise a trench that is formed in an upper surface of the semiconductor mesas and extends to the base region, a metal electrode disposed within the trench, and a doped sidewall region lining sidewalls of the trench, wherein the doped regions and the trenched connectors collectively form a first voltage blocking device between the first and second contact pads.

Example 16. The overvoltage protection device of example 15, wherein the plurality of doped regions each have an elongated geometry and run parallel to one another, wherein the trenched connectors are interleaved between immediately adjacent ones of the doped regions.

Example 17. The overvoltage protection device of example 16, wherein the plurality of doped regions and the trenched connectors form a PIN diode connected between the first and second contact pads, and wherein regions of the semiconductor mesas between the doped regions and the doped sidewall regions form the intrinsic region of the PIN diode.

Example 18. The overvoltage protection device of example 16, wherein in a forward conduction state of the first voltage blocking device current flows in multiple directions in the semiconductor mesas across sidewalls of the trench from the trenched connectors.

Example 19. The overvoltage protection device of example 15, wherein the first contact pad is disposed on a first one of the mesas, wherein the second contact pad is disposed on a second one of the mesas, wherein at least some of the trenched connectors and the doped regions are disposed in a third one of the mesas that is between the first and second ones of the mesas.

Example 20. The overvoltage protection device of example 15, wherein the doped regions and the doped sidewall regions are collectively arranged to form a second voltage blocking device between the first and second contact pads, wherein the first and second voltage blocking devices are arranged in an antiparallel configuration.

A “lateral” device as used herein refers to semiconductor device which conducts an operational current exclusively in a lateral direction that is parallel to a main or upper surface of a semiconductor substrate. By contrast, a “vertical” device as used herein refers to semiconductor device which conducts an operational current that flows at least partially in a vertical direction that is parallel to a main or upper surface of a semiconductor substrate. Vertical devices include devices that conduct operational current that flows with a lateral component and with a vertical component simultaneously.

The term “low-ohmic contact” or “low-ohmic connection” intends to describe a non-rectifying electrical contact or connection between two elements, e.g., a contact or connection wherein electrical current may flow with low electrical resistance in both directions. By contrast, a non-ohmic contact or non-ohmic connection intends to describe a contact or connection with non-linear I-V characteristics.

The semiconductor body disclosed herein may include or consist of a semiconductor material from group IV elemental semiconductors, IV-IV compound semiconductor material, III-V compound semiconductor material, Examples of semiconductor materials from the group IV elemental semiconductors include, inter alia, silicon (Si) and germanium (Ge). Examples of IV-IV compound semiconductor materials include, inter alia, silicon carbide (SiC) and silicon germanium (SiGe). Examples of III-V compound semiconductor material include, inter alia, gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN) and indium gallium arsenide (InGaAs).

The present specification refers to a “first” and a “second” conductivity type of dopants. These terms refer to the majority carrier type of doped semiconductor regions. The present specification also refers to n-type semiconductor regions, i.e., semiconductor regions with a net n-type majority carrier concentration, and p-type semiconductor regions, i.e., semiconductor regions with a net p-type majority carrier concentration. In any of the embodiments described herein, the doping types may be reversed to obtain a device that operates on a similar working principle. For example, an n-type device may be converted to a p-type device by changing the n-type regions to p-type regions, and vice-versa. The polarity of any diode structure may be reversed by changing the n-type regions to p-type regions, and vice-versa. The present specification encompasses all such embodiments.

Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second,” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.