Patent ID: 12191279

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below for the purposes of conveying the present disclosure in a simplified manner. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the same reference numerals and/or letters may be used to refer to the same or similar parts in the various examples the present disclosure. The repeated use of the reference numerals is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “over”, “overlying”, “above”, “upper” and the like, may be used herein to facilitate the description of one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1AtoFIG.1Fare cross-sectional views of a method of forming an integrated circuit package in accordance with some embodiments.

Referring toFIG.1A, a package structure100is provided onto a carrier substrate C. In some embodiments, the package structure100is placed onto the carrier substrate C. The carrier substrate C may be a glass carrier. In some embodiments, a de-bonding layer DB is formed between the carrier substrate C and the package structure100. The de-bonding layer DB is a light-to heat-conversion (LTHC) release layer, for example. The materials of the carrier substrate C and the de-bonding layer DB are not limited in this disclosure.

In some embodiments, the package structure100includes a plurality of integrated circuits110,120, an encapsulant130, a redistribution layer structure140, a substrate layer150and a plurality of conductive pillars160. In some embodiments, the integrated circuit110is disposed between the integrated circuits120, and the integrated circuit110is surrounded by the integrated circuits120. In some embodiments, each of the integrated circuits110includes a logic die such as an application processor (AP) die, a central processing unit (CPU) die, a general processing unit (GPU) die, a field programmable gate arrays (FPGA) die, application-specific integrated circuit (ASIC) die, an I/O die, a network processing unit (NPU) die, a time processing unit (TPU) die, an artificial intelligence (AI) engine die, and a system on integrated chips (SoIC). In some embodiments, each of the integrated circuits120includes a memory die such as a high bandwidth memory (HBM) die, a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a wide I/O memory die, a NAND memory die, a resistive random access memory (RRAM) die, a phase change random access memory (PRAM) die and a magnetic random access memory (MRAM) die, a SoC die, a SoIC die, a die stack or the like. In some embodiments, upon the process requirements, the dimension of the integrated circuit120is similar to or different from the dimension of the integrated circuit110. The dimension may be a height, a width, a size, a top-view area or a combination thereof. In some embodiments, three integrated circuits are shown to represent plural integrated circuits, and the disclosure is not limited thereto. For example, there may be two integrated circuits or more than three integrated circuits.

In some embodiments, the integrated circuit110is different from the integrated circuit120. In some embodiments, the integrated circuit110is a logic die, and the integrated circuits120is respectively memory die stacks or three-dimensional (3D) memory cubes. In some embodiments, the integrated circuit120has a plurality of dies122. The dies122are stacked vertically and connected by micro-bumps122aand/or through vias122bof the dies122, for example. In some embodiments, the integrated circuits110and120are connected to the redistribution layer140through the connector112,124by flip chip bonding, hybrid bonding, fan-out RDL, and/or the like. In some embodiments, each of the integrated circuits110,120has a plurality of connectors112,124thereon and a dielectric layer114,126aside the connectors112,124. In some embodiments, the connectors112,124are copper pillars or other suitable metal pillars. In some embodiments, the dielectric layer114,126is a polybenzoxazole (PBO) layer, a polyimide (PI) layer or other suitable underfilling epoxy polymers. In some alternative embodiments, the dielectric layer114,126is made of inorganic materials. In some alternative embodiments, the integrated circuits120further include a controller. However, the structure of the integrated circuits110,120are merely for illustration, and the disclosure is not limited thereto. For example, in some alternative embodiments, the connectors112,124have solder layers (not shown) thereon, or the dielectric layer114,126is omitted.

In some embodiments, the encapsulant130encapsulates the integrated circuits110,120. The encapsulant130is formed around the integrated circuits110,120. Specifically, the encapsulant130fills the gap between any two of the integrated circuits110,120. In some embodiments, the encapsulant130includes a molding compound, a resin or the like. In some embodiments, the encapsulant130includes a polymer material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or the like. In alternative embodiments, the encapsulant130includes silicon oxide, silicon nitride or a combination thereof.

In some embodiments, the redistribution layer structure140is connected to surfaces of the integrated circuits110,120. The redistribution layer structure140includes a dielectric layer142and conductive features144embedded by the dielectric layer142. The conductive features144are electrically connected to the connectors112,124of the integrated circuits110,120. In some embodiments, the dielectric layer142includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), silicon oxide, and other inorganic dielectrics, a combination thereof or the like. In some embodiments, the dielectric layer142includes other dielectric material. In some embodiments, the conductive features144include metal lines144aand/or metal vias144bconfigured to electrically connect to different components. In some embodiments, the conductive features144include Cu, Ti, Ta, W, Ru, Co, Ni, a combination thereof or the like. In some embodiments, a seed layer and/or a barrier layer is disposed between each metal feature144and the dielectric layer142. The seed layer may include Ti/Cu. The barrier layer may include Ta, TaN, Ti, TiN, CoW or a combination thereof. In some alternative embodiments, the metal features144are formed to form a redistribution layer structure such as serializer/deserializer (SerDes) redistribution layer structure.

In some embodiments, the substrate layer150is formed over the redistribution layer structure140. In some embodiments, a material of the substrate layer150includes a semiconductor layer such as a silicon layer. In some embodiments, a lateral sidewall of the substrate layer150is substantially flush with lateral sidewalls of the encapsulant130and the redistribution layer structure140. A thickness of the substrate layer150may range from 50 to 100 μm. In some alternative embodiments, the substrate layer150may be omitted.

Then, the conductive pillars160are formed in an on the substrate layer150to electrically connect the redistribution layer structure140. In some embodiments, the conductive pillars160are copper pillars. In some embodiments, a plurality of openings in the substrate layer150to expose the conductive features144, and then the conductive pillars160are formed in the openings and on the substrate layer150respectively. The conductive pillars160may be formed by a deposition process, a sputtering process, a plating process or the like and a sequential patterning process. In some embodiments, a shape of a top surface of the conductive pillars160is circle, square, rectangular, ellipse or the like. In some embodiments, the conductive pillars160penetrate the substrate layer150and protrude from the substrate layer150. Specifically, the conductive pillars160have first portions160aand second portions160bconnecting to the first portions160a, the first portions160a(for example, upper portions) are disposed on the substrate layer150, and the second portions160b(for example, lower portions) are embedded in the substrate layer150. In some embodiments, the first portion160ahas a width larger than the second portion160b. In some embodiments, the characteristic width of the first portion160aof the conductive pillars160ranges from about 20 μm to 50 μm, and the width of the second portion160bof the conductive pillars160ranges from about 5 μm to 15 μm. The height of the first portion160aof the conductive pillar160may range from 30 μm to 300 μm. The thickness of the second portion is substantially equal to the thickness of the substrate layer150. In some embodiments, a gap G is formed between the first portions160aof the conductive pillars160. In some embodiments, a width of the gap G is substantially the same, in other words, the conductive pillars160is arranged regularly. However, the invention is not limited thereto. In some alternative embodiments, the conductive pillars160is arranged irregularly. In some embodiments, depending on design needs, the width of the gap G ranges largely from 50 μm to 8000 μm.

Referring toFIG.1B, a plurality of dies170are formed over the package structure100. In some embodiments, after the package structure100is disposed on the carrier substrate C, the dies170may be picked and placed onto the substrate layer150. In some embodiments, the dies170are disposed in the gaps G between the conductive pillars160on the substrate layer150. In some embodiments, the dies170are integrated passive device (IPD) dies, integrated voltage regulator (IVR) dies, memory dies, SerDes PHY dies, or the like. In some embodiments, depending on design needs, the dies170include dies of one function or multiple different functions, dies of same size or different sizes aforementioned. In some embodiments, the die170includes connectors172disposed thereon and extending away from the substrate layer150. In some alternative embodiments, the die170is mounted onto the substrate layer150through an adhesive layer (not shown) such as a die attach film (DAF). In some alternative embodiments, the die170is mounted onto the substrate layer150through a metal bonding (not shown) such as flip chip bonding. In such embodiments, the connectors172of the die170may extend toward the substrate layer150and be electrically connected to the redistribution layer structure140via the conductive pillar160. In some embodiments, a total height of the die170and the connector172thereon is in a range of 30 μm to 300 μm, and a width of the die170is in a range of 500 μm to 7500 μm. In some embodiments, top surfaces of the connectors172of the dies170are substantially coplanar with top surfaces of the conductive pillars160. However, in some alternative embodiments, the top surfaces of the connectors172of the dies170are lower or higher than the top surfaces of the conductive pillars160.

Referring toFIGS.1C and1D, an encapsulant180is formed over carrier substrate C to encapsulate the package structure100and the dies170. In some embodiments, as shown inFIG.1C, an insulating material180′ is formed over the carrier substrate C to cover the package structure100and the dies170. In some embodiments, the insulating material180′ includes a molding compound such as an epoxy molding compound formed by a molding process. In some alternative embodiments, the insulating material180′ includes an epoxy, a resin or the like.

Then, as shown inFIG.1D, the insulating material180′ is grinded until the conductive pillars160and the connectors172of the dies170are exposed, so as to form the encapsulant180. In some embodiments, the insulating material180′ is grinded by a planarization process such as a chemical mechanical polish process. In some embodiments, after grinded, the top surfaces of the conductive pillars160and the connectors172are substantially coplanar with the top surface of the encapsulant180. In some embodiments, the encapsulant180encapsulates the lateral sidewalls of the encapsulant130, the redistribution layer structure140, the substrate layer150, the conductive pillars160, the dies170and the connectors172. The top surfaces of the conductive pillars160and the connectors172of the dies170are exposed by the encapsulant180. In other words, the conductive pillars160and the dies170are embedded in the encapsulant180with the exposed top surfaces. In some embodiments, the conductive pillars160and the dies170are encapsulated and in contact with the encapsulant180. The conductive pillars160and the connectors172may be disposed in and penetrate the encapsulant180. In some alternative embodiments, the encapsulant180is formed by a lamination process.

Referring toFIG.1E, after forming the encapsulant180, a redistribution layer structure190is formed over the encapsulant180and electrically connected to the conductive pillars160and the dies170. In some embodiments, the redistribution layer structure190includes a plurality of dielectric layers192and a plurality of conductive features194embedded in the dielectric layers192. It is noted that numbers of layers of the conductive features194are shown for illustration purpose, and the scope of the disclosure is not limited thereto. In some embodiments, the dielectric layer192is a multi-layer structure. In some embodiments, the dielectric layer192includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. In some embodiments, the dielectric layer192includes other dielectric material. In some embodiments, the conductive features194include metal lines194aand/or metal vias194bconfigured to electrically connect to different components. In some embodiments, the conductive features194include Cu, Ti, Ta, W, Ru, Co, Ni, a combination thereof or the like. In some embodiments, a seed layer and/or a barrier layer is disposed between each conductive feature194and the dielectric layer192. The seed layer may include Ti/Cu. The barrier layer may include Ta, TaN, Ti, TiN, CoW or a combination thereof.

In some embodiments, a thickness of the dielectric layer192is in a range of 10 μm to 30 μm. In some embodiments, the conductive features194have a linewidth ranging from 2 μm to 10 μm. In some alternative embodiments, the linewidth of the conductive features194is increased as the conductive features194becomes closer to the redistribution layer structure200(shown inFIG.1F). In some alternative embodiments, the linewidth of the conductive features194is substantially the same or larger than the linewidth of the underlying conductive features194. In some embodiments, the linewidth is referred to as a critical dimension or a pitch.

Referring toFIG.1F, a redistribution layer structure200is formed over the redistribution layer structure190and electrically connected to the conductive pillars160and the dies170. In some embodiments, the redistribution layer structure200includes a plurality of dielectric layers202and a plurality of conductive features204embedded in the dielectric layers202. In some embodiments, the conductive features204include metal lines204aand/or metal vias204bconfigured to electrically connect to different components. It is noted that numbers of layers of the conductive features204are shown for illustration purpose, and the scope of the disclosure is not limited thereto.

In some embodiments, the main function of the redistribution layer structure200is to provide electrical connection to the conductive terminals and structure rigidity of an integrated circuit package10. Thus, the machine, the method and the material for fabricating the redistribution layer structure200may be different from those for fabricating the redistribution layer structure190. In some embodiments, a photoresist layer is formed on the redistribution layer structure190by lamination and/or coating process. After image patterning, the metal lines204aand the metal via204bare formed by electrical plating process. Then, the photoresist layer is removed and undesired seed layer is removed by a dry and/or wet etch process. To strengthen the structure rigidity, an enhanced encapsulant material is applied to fill up the metal lines and metal vias by an encapsulation process. In some embodiments, the enhanced encapsulant materials is an epoxy based polymers with fine grain of inorganic fillers (0.5 μm˜2 μm) and volume fraction of 30%-80%. In some embodiments, the encapsulation process includes wafer molding, wafer dispensing, wafer lamination, and the like. After encapsulation, a planarization process is applied to remove the excess encapsulant to expose the metal lines. The same steps are repeated to form multiple layers of the redistribution layer structure200. In some embodiments, a thick dielectric layer is formed on the structure190, then metal via and metal lines are formed at one time by laser imaging process (LDI). In some embodiments, the thick dielectric layer includes Ajinomoto Buildup Film (ABF), polyimide, and the like. For metal formation, a conformal seed layer is formed first by an electroless process, then metal vias and the metal lines are formed by electroplating. Finally, a metal planarization is needed to remove the metal overburden. In some embodiments, the metal layer includes Cu, Ti, Ta, W, Ru, Co, Ni, a combination thereof or the like. In some embodiments, the metal planarization includes method of CMP, wheel grinding, diamond blade fly cut, and the like. In such way, a dual damascene like redistribution layer is formed. The same steps are repeated to form multiple layer s of the redistribution layer structure200.

In some embodiments, a linewidth of the conductive features204is larger than a linewidth of the conductive features194. In some embodiments, the linewidth of the conductive features204is at least 1.5, 2, 3, 4, 5, 6, 7, 8, 9 or 10 times of the linewidth of the conductive features194. In some embodiments, the linewidth of the conductive features204is in a range of 20 μm to 50 μm. In some alternative embodiments, the linewidth of the conductive features204is increased as the conductive features204becomes closer to conductive terminals210. In some alternative embodiments, the linewidth of the conductive features204is substantially the same or larger than the linewidth of the underlying conductive features204. For example, the linewidth of the conductive features204is substantially the same or larger than the linewidth of the conductive features204btherebeneath. In some embodiments, a thickness of the dielectric layer202is larger than a thickness of the dielectric layer192. The thickness of the dielectric layer202may be in a range of 50 μm to 150 μm. In some embodiments, the redistribution layer structure200provides a high modulus for support such as in a range of 1 GPa to 10 GPa.

In some embodiments, the redistribution layer structure200is formed by the process such as LDI which is generally used to manufacture the PCB, and thus the redistribution layer structure200has good rigidity. In addition, the cost and the time of the manufacture for the redistribution layer structure200are reduced. Furthermore, compared with the printed circuited board having a core layer, the redistribution layer structure200is directly formed over and integrated onto the package structure100and the encapsulant180, and thus a support substrate similar to the core layer is not needed. Accordingly, a total thickness of the integrated circuit package10is smaller than the integrated circuit package having the package structure bonded to the printed circuited board. Moreover, the connectors such as controlled collapse chip connection (C4) bumps between the package structure and the printed circuit board are not required.

After forming the redistribution layer structure200, a plurality of conductive terminals210are formed on the redistribution layer structure200. In some embodiments, the conductive terminals210are ball grid array (BGA) connectors, solder balls, metal pillars, and/or the like. In some embodiments, the conductive terminals210are formed by a mounting process and a reflow process. In some embodiments, a plurality of under-ball metallurgy (UBM) patterns208are formed under the conductive terminals210for ball mount.

In some embodiments, a plurality of dies220are mounted on the redistribution layer structure200between the conductive terminals210. At this point, the integrated circuit package10is fabricated. In some embodiments, the dies220are IPD dies, IVR dies, memory dies or the like. In some embodiments, the die220includes connectors222thereon. In some embodiments, the dies220are mounted onto the redistribution layer structure200through the connectors222and solders224. In some embodiments, an underfill226is provided between the die220and the redistribution layer structure200to seal the region therebetween. However, in some alternative embodiments, the die220is a bare (unpackaged) die.

In some embodiments, the integrated circuit package10is separated from the carrier substrate C. That is, the carrier substrate C is removed. In some embodiments, the de-bonding layer DB is irradiated by an UV laser such that the integrated circuit package10is peeled from the carrier substrate C. In some alternative embodiments, after the conductive terminals210and the dies220are formed, a singulation process is performed to form a single integrated circuit package. In some embodiments, the integrated circuit package10is provided in a high-performance computing system, to provide high data transmission rate. In some embodiments, a dimension of the integrated circuit package10is larger than 40 mm×40 mm. In some embodiments, the integrated circuit package10is an integrated fan-out package.

In some embodiments, the package structure100is connected to the conductive terminals210through the conductive pillars160and the redistribution layer structures190,200therebetween. Since the conductive pillars160and the redistribution layer structures190,200are directly formed over the package structure100, the bonding of the package structure100to an additional circuit board and the formation of additional bumps (such as C4 bumps) between the additional circuit board and the package structure are not required. In addition, the dies170such as IPD dies, memory dies, SerDes dies, and/or IVR dies are disposed between the conductive pillars160and embedded in the encapsulant180, and thus the integration of the integrated circuit package10is improved. Furthermore, in some embodiments, the logic die and the memory dies (such as 3D memory cube) is integrated to realize near in-memory computing (IMC) technology with high computing efficiency, high bandwidth and low latency.

FIG.2AtoFIG.2Iare cross-sectional views of integrated circuit packages in accordance with some embodiments.FIG.3is a top view of an integrated circuit package ofFIG.2DtoFIG.2F.FIG.4is a top view of an integrated circuit package ofFIG.2GtoFIG.2I.FIG.5is a top view of an integrated circuit package in accordance with some embodiments. The semiconductor packages10A-10I illustrated inFIGS.2A to2Iare similar to the semiconductor package10illustrated inFIG.1F, hence the same reference numerals are used to refer to the same and liked parts, and its detailed description will be omitted herein. The difference between the semiconductor package10A-10I and the semiconductor package10is the structure of the integrated circuit110. In the embodiment shown inFIGS.2A to2I, the integrated circuit110is a system on integrated chips (SoIC).

In detail, in the embodiments shown inFIGS.2A to2C, the integrated circuit110includes a first die116a, a plurality of second dies116b, a plurality of conductive pillars116c, and an encapsulant116d. In some embodiments, the second dies116bare sequentially stacked on the first die116ato form a die stack. In some embodiments, the second dies116bare stacked on the first die116avertically and connected to each other by micro-bumps (not shown) and/or through vias (not shown) of the second dies116b. In some embodiments, the first die116ais a logic die such as a SoC die, and the second dies116bare memory dies such as SRAM dies. In some embodiments, the die stack of second dies116bis different from the die stack of the integrated circuit120, in other words, the package structure100includes at least two different memory cubes. In some embodiments, the conductive pillars116care disposed on the first die116aaside the second dies116b. The encapsulant116dis formed on the first die116ato encapsulate the second dies116band the conductive pillars116c. In some embodiments, the conductive pillars116care disposed in and penetrate the encapsulant116d. The conductive pillars116care thermal pillars for heat spreading, vertical interconnect for I/O communication, and the like.

In the embodiments shown inFIGS.2B and2C, the integrated circuit110further includes a third die116e. In some embodiments, the third die116eis a logic die such as a SoC die. In some embodiments, the third die116eis a memory controller logic, an I/O logic, a digital signal processing (DSP), an IPD die, and a logic core or the like. In some embodiments, the third die116eis itself a stacked die of multiple logic cores and I/O die or the like. In some embodiments, the third die116eis itself a SoIC of multiple stacked logic cores and I/O die or the like. In some embodiments, the third die116ehas the same size as the dies116b. In some embodiments, the third die116ehas a different size from the dies116b. In detail, in the embodiment shown inFIG.2B, the third die116eis disposed between the first die116aand the second dies116b, that is, the third die116eis disposed adjacent to the first die116a. However, the invention is not limited thereto. In the embodiment shown inFIG.2C, the third die116eis disposed on the second dies116bover the first die116a, in other words, the third die116eis disposed opposite to the first die116awith respect to the second dies116b.

In the embodiments shown inFIGS.2D to2I, the integrated circuit110includes a first die116a, a plurality of second dies116b, an additional die116f, and an encapsulant116d. The additional die116fmay be an IPD die, an IVR die or the like. The additional die116fmay be a bare (unpackaged) die mounted on the periphery surface of the first die116a. In some embodiments, the additional die116fis bonded to the first die116awith a face-to-face direct bonding. In some alternative embodiments, an underfill (not shown) is provided between the additional die116fand the first die116ato seal the region therebetween. In the embodiments shown inFIGS.2D to2F and3, the additional die116fis disposed on the first die116aaside the second dies116b. The encapsulant116dis formed on the first die116ato encapsulate the second dies116band the additional die116f. In some embodiments, as shown inFIGS.2G to2IandFIG.4, the additional dies116fis disposed aside and separated from the first die116a. In some embodiments, the additional die116fis deposited in a face-up manner with a die attach film and use vertical connectors (not shown) to connect to the redistribution layer structure140. The encapsulant116dis formed to encapsulate the first die116a, the second dies116band the additional die116f. In addition, in the embodiments shown inFIGS.2E,2F,2H and2I, a third die116eis disposed between the first die116aand the second dies116bor on the second dies116bover the first die116a.

In above embodiments, one integrated circuit110is shown. However, the invention is not limited thereto. For example, in the embodiment shown inFIG.5, a plurality of integrated circuits110is disposed between the integrated circuits120. In addition, each of the integrated circuits110may include a first die116a, a plurality of second dies116band a plurality of additional dies116f, and the second dies116band the additional dies116fare disposed on the first die116a. The integrated circuits120may respectively include a plurality of dies122(i.e., a die stack). Therefore, as shown inFIG.5, the first dies116aare surrounded by the dies122(i.e., a die stack), and the second dies116bis surrounded by the additional dies116e. In the embodiment, the first dies116aare logic dies, the dies116b,122are memory dies, and the additional dies116fare IPD dies and/or IVR dies. Accordingly, the logic dies may be surrounded by the memory dies, and IPD die and/or IVR die may be disposed between the memory dies.

FIG.6is a cross-sectional view of an integrated circuit packages in accordance with some embodiments. The semiconductor package10J illustrated inFIG.6is similar to the semiconductor package10illustrated inFIG.1F, hence the same reference numerals are used to refer to the same and liked parts, and its detailed description will be omitted herein. The difference between the semiconductor package10J and the semiconductor package10is the substrate layer150. For example, in the embodiment shown inFIG.1F, the semiconductor package10includes the substrate layer150. However, in the embodiment shown inFIG.6, the conductive pillars160of semiconductor package10J are directly formed on the redistribution layer structure140without a substrate layer150therebetween. In some embodiments, the integrated circuits110and120are connected to the redistribution layer140through the connector112,124by flip chip bonding, hybrid bonding, fan-out RDL and/or the like. In detail, as shown inFIG.6, the conductive pillar160has a top width substantially the same as a bottom width. In the embodiment, a lateral sidewall of the conductive pillar160is entirely encapsulated by the encapsulant180. In some embodiments, if required, the redistribution layer structure190is a serializer/deserializer (SerDes) redistribution layer structure. In addition, in some alternative embodiments, the package structure100is any one of the package structures ofFIGS.1,2A-2Ior the like.

FIG.7is a cross-sectional view of an integrated circuit packages in accordance with some embodiments. The semiconductor package10K illustrated inFIG.7is similar to the semiconductor package10J illustrated inFIG.6, hence the same reference numerals are used to refer to the same and liked parts, and its detailed description will be omitted herein. The difference between the semiconductor package10K and the semiconductor package10J is the structure of the integrated circuit110. In detail, in the embodiment shown inFIG.7, the integrated circuit110includes a first die116aand a plurality of second dies116b1,116b2. In some embodiments, the second dies116b1,116b2are bonded on opposite surfaces of the first die116aand electrically connected to the first die116athrough a through silicon via (TSV) in the die116a(not shown). In some embodiments, the second dies116b1,116b2are bonded to the first die116athrough a plurality of connectors117and a dielectric layer118aside the connectors117. The dimension of the first die116amay be larger than the dimension of each of the second dies116b1,116b2. In some embodiments, the first die116ais a logic die, and the second dies116b1,116b2are memory dies. In some embodiments, the die circuits110is itself a SoIC die as described in theFIGS.2A to2I. In some embodiments, the first die116ais itself a SoIC die as described in theFIG.2A to2I. In addition, the integrated circuit120may be memory die stacks, and includes a plurality of dies122. Therefore, the second dies116b1,116b2are disposed at opposite surfaces of the first die116ain a first direction, and the dies122are disposed at opposite lateral sidewalls of the first die116ain a second direction substantially perpendicular to the first direction. Accordingly, the die116asuch as a compute logic die is-immersed in the dies116b1,116b2,122such as memory dies. In above embodiments, one integrated circuit110is shown. However, the invention is not limited thereto. In some embodiments, there are multiple integrated circuits110as shown inFIG.5.

In some embodiments, the integrated circuit110further includes a plurality of conductive pillars116c1,116c2and a plurality of encapsulants116d1,116d2. In some embodiments, the conductive pillars116c1aside the second die116b1are thermal pillars for heat spreading, and the conductive pillars116c2aside the second die116b2are through vias for electrical connection. In some embodiments, the conductive pillars116c1are disposed on electrically connected to the first die116athrough a plurality of conductive layers116gtherebetween. In some embodiments, the conductive pillars116c2is electrically connected to the first die116aand the redistribution layer structure140. The encapsulant116d1encapsulates the first die116a, the second die116b2and the conductive pillars116c1. The encapsulant116d2encapsulates the second die116b2and the conductive pillars116c2.

FIG.8AtoFIG.8Dare cross-sectional views of a method of forming an integrated circuit package in accordance with some embodiments.

Referring toFIG.8A, a package structure100is provided. The package structure100may be any one of the package structures100ofFIGS.1,2A-2I and7or the like. Then, a carrier substrate C with redistribution layer structures190,200thereon is provided. In some embodiments, a de-bonding layer DB is formed over the carrier substrate C. Then, the redistribution layer structure200and the redistribution layer structure190are sequentially formed over the de-bonding layer DB. The configuration, material and forming method of the redistribution layer structures190,200are similar to those of the redistribution layer structures190,200inFIGS.1E and1F. In some embodiments, if required, the redistribution layer structure190is serializer/deserializer (SerDes) redistribution layer structure.

In some embodiments, after the redistribution layer structures190,200are formed, a plurality of dies170are bonded onto the redistribution layer structure190. The dies170are disposed corresponding to gaps G between adjacent conductive pillars160, and thus after the dies170may be disposed between the adjacent conductive pillars160after the package structure100is bonded to the redistribution layer structure190over the carrier substrate C. In some embodiments, the dies170are mounted onto the redistribution layer structure190through connectors172of the dies170and solders174on the connectors172. In some embodiments, an underfill176is provided between the die170and the redistribution layer structure190to seal the region therebetween. However, in some alternative embodiments, the die170is a bare (unpackaged) die.

Referring toFIG.8B, the package structure100is bonded to the redistribution layer structure190over the carrier substrate C. In some embodiments, the package structure100is flip-chip bonded to the redistribution layer structure190through the conductive pillars160. In some embodiments, solder regions230are formed between the conductive pillars160and conductive features194of the redistribution layer structure190. In some embodiments, as shown inFIG.8A, the solders regions230are formed on the conductive pillars160. However, in some alternative embodiments, the solders regions230are formed on the redistribution layer structure190. After bonding, an underfill232(also referred to as an encapsulant) may be formed between the package structure100and the redistribution layer structure190to seal the region therebetween. In some embodiments, the dies170are embedded in the underfill232between the conductive pillars160. In some embodiments, the dies170are physically separated from the redistribution layer structure190. In some embodiments, the underfill232are disposed between the dies170and the redistribution layer structure190.

Referring toFIG.8C, a heat sink240is formed over the package structure100. In some embodiments, the heat sink240is a cover. In some embodiments, the heat sink240is disposed on a portion of the redistribution layer structure190exposed by the underfill232, to cover the package structure100entirely. In some embodiments, the heat sink240is in contact with the portion of the redistribution layer structure190. In some embodiments, the heat sink240is directly in contact with exposed surfaces of the package structure100such as surfaces of the integrated circuits110,120and the encapsulant130. In some alternative embodiments, the heat sink240is physically separated from and not in contact with the package structure100.

Referring toFIG.8D, a structure ofFIG.8Cis separated from the carrier substrate C. That is, the carrier substrate C and the de-bonding layer DB are removed. Then, the structure may be turned upside, and a plurality of conductive terminals210and a plurality of dies220may be formed over the redistribution layer structure200, so as to electrically connect the redistribution layer structure200. In some embodiments, the dies220are IPD dies, IVR dies, memory dies or the like. In some embodiments, a plurality of under-ball metallurgy (UBM) patterns208are formed under the conductive terminals210for ball mount. At this point, an integrated circuit package10L is fabricated. In some embodiments, the die circuits110is itself a SoIC die as described in theFIGS.2A to2I.

In some embodiments, the package structure100is bonded to the redistribution layer structures190,200through the conductive pillars160. Thus, the die170may be disposed in the space formed between the conductive pillars160. Accordingly, the additional space is not needed. In addition, since the carrier substrate C is directly used as a base layer for forming the redistribution layer structures190,200, a support substrate similar to a core layer may be omitted. In addition, since the carrier substrate C will be then removed, a total thickness of the integrated circuit package10L is smaller than the integrated circuit package having the package structure bonded to the printed circuited board.

FIG.9is a cross-sectional view of an integrated circuit packages in accordance with some embodiments. The semiconductor package10M illustrated inFIG.9is similar to the semiconductor package10L illustrated inFIG.8D, hence the same reference numerals are used to refer to the same and liked parts, and its detailed description will be omitted herein. The difference between the semiconductor package10L and the semiconductor package10M is the structure of the integrated circuit110and removal of the heat sink240. In the embodiment shown inFIG.9, the integrated circuit110has a structure similar to the integrated circuit110shown inFIG.7. In some embodiments, the integrated circuits110is itself a SoIC die as described in theFIGS.2A to2I. In some embodiments, the first die116ais itself a SoIC die as described in theFIGS.2A to2I. In some embodiments, the package structures100may include the substrate layer150interposed between the dies170and the integrated circuits110as illustrated inFIGS.1A to2I. In some embodiments, the package structure100and the dies170are bonded to the redistribution layer structure190through flip-chip bonding. In some alternative embodiments, a heat sink (not shown) is also disposed aside the package structure100.

In some embodiments, the package structure is connected to the conductive terminals through the conductive pillars and the redistribution layer structures therebetween. The redistribution layer structures are directly formed over the package structure or the carrier substrate which is then removed, and thus the bonding of the package structure to an additional circuit board and the formation of additional bumps (such as C4 bumps) between the additional circuit board and the package structure are not required. In addition, the technique for manufacturing the PBC is applied in the fabrication of the redistribution layer structure having a large linewidth. Therefore, the strength of the redistribution layer structure is improved, and the cost and the time for manufacturing the redistribution layer structure may be reduced. Furthermore, the dies such as IPD and/or IVR may be disposed between the conductive pillars and embedded in the encapsulant, and thus the integration of the integrated circuit package is improved. Accordingly, the logic die and the memory dies (such as 3D memory cube) may be integrated side by side to realize in-memory computing (IMC) technology with high computing efficiency, high bandwidth and low latency.

Many variations of the above examples are contemplated by the present disclosure. It is understood that different embodiments may have different advantages, and that no particular advantage is necessarily required of all embodiments.

In accordance with some embodiments of the present disclosure, an integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure. The third redistribution structure is disposed over and electrically connected to the second redistribution structure, wherein a linewidth of the third redistribution structure is larger than a linewidth of the second redistribution structure.

In accordance with alternative embodiments of the present disclosure, an integrated circuit package includes a package structure, a second redistribution structure, at least one second die and a second encapsulant. The package structure includes a plurality of first dies, a first encapsulant encapsulating the first dies, a first redistribution structure over the first encapsulant and a plurality of conductive pillars over the first redistribution structure. The second redistribution structure is disposed over the package structure, and electrically connected to the package structure through the conductive pillars. The second die is disposed between the conductive pillars and electrically connected to the second redistribution structure. The second encapsulant encapsulates the conductive pillars and the at least one second die.

In accordance with yet alternative embodiments of the present disclosure, a method of manufacturing an integrated circuit package includes the following steps. A package structure is provided, and the package structure includes a plurality of first dies, a first encapsulant encapsulating the first dies, a first redistribution structure over the first encapsulant and a plurality of conductive pillars over the first redistribution structure. At least one second die is formed between the conductive pillars. A second encapsulant is formed to encapsulate the conductive pillars and the at least one second die. A second redistribution structure is formed over the second encapsulant. A third redistribution structure is formed, wherein a linewidth of the third redistribution structure is larger than a linewidth of the second redistribution structure. The package structure and the second redistribution structure are electrically connected, wherein the second redistribution structure is disposed between the package structure and the third redistribution structure.

In accordance with alternative embodiments of the present disclosure, an integrated circuit package includes a package structure including a plurality of first dies, a second redistribution structure, a second die and a second encapsulant. The package structure includes the first dies, a first encapsulant encapsulating the first dies, a first redistribution structure over the first encapsulant and a plurality of conductive pillars over the first redistribution structure. The second redistribution structure is disposed over the package structure, and electrically connected to the package structure through the conductive pillars. The second die is disposed between the conductive pillars and electrically connected to the second redistribution structure, wherein a first surface of the second die is substantially flush with a surface of the first redistribution structure and a second surface opposite to the first surface of the second die is substantially flush with a surface of the second redistribution structure. The second encapsulant encapsulates the conductive pillars and the second die.

In accordance with alternative embodiments of the present disclosure, an integrated circuit package includes a first redistribution structure, a second redistribution structure, a semiconductor layer, a plurality of conductive pillars and a first die. The semiconductor layer is disposed between the first redistribution structure and the second redistribution structure. The conductive pillars are disposed on the semiconductor layer and penetrate through the semiconductor layer, wherein the conductive pillars are disposed between and electrically connected to the first redistribution structure and the second redistribution structure. The first die is disposed on the semiconductor layer between the first redistribution structure and the second redistribution structure.

In accordance with alternative embodiments of the present disclosure, a method of manufacturing an integrated circuit package includes the following steps. A semiconductor layer is formed on a first redistribution structure. A plurality of conductive pillars are formed in the semiconductor layer to electrically connect to the first redistribution structure. A first die is formed on the semiconductor layer between the conductive pillars. A second redistribution structure is formed on the semiconductor layer to electrically connect to the first die and the conductive pillars.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.