Patent ID: 12250811

DETAILED DESCRIPTION

The specific structural or functional description disclosed herein is merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms, and cannot be construed as limited to the embodiments set forth herein.

Embodiments provide a semiconductor device with a stable structure and improved characteristics, and a manufacturing method of the semiconductor device.

FIGS.1A and1Bare views illustrating a structure of a semiconductor device in accordance with an embodiment of the present disclosure.

Referring toFIG.1A, the semiconductor device may include a gate structure GST, a channel layer16, memory patterns14, and a blocking layer13. The semiconductor device may further include a tunnel insulating layer15, a core17, or a combination thereof.

The gate structure GST may include conductive layers11and insulating layers12, which are alternately stacked. The conductive layers11may be gate electrodes of a memory cell, a select transistor, and the like. In an embodiment, the conductive layers11may be control gates. Each of the conductive layers11may include a conductive pattern11A and a barrier pattern11B. The barrier patterns11B may be respectively located between the blocking layer13and the conductive patterns11A. Each of the barrier patterns11B may have a C-shaped section. The barrier patterns11B may include metal nitride. The conductive pattern11A may include a conductive material, such as poly-silicon, tungsten, molybdenum, or other metal. The insulating layer12may be used to insulate the stacked conductive layers11from each other. The insulating layers12may include an insulating material, such as oxide, nitride or an air gap.

The channel layer16may penetrate the gate structure GST. The channel layer16may extend in a stacking direction of the conductive layers11and the insulating layers12. The channel layer16may be a region in which a channel of a memory cell, a select transistor, or the like is formed. The channel layer16may include a semiconductor material. In an embodiment, the channel layer16may include silicon, germanium, a nano structure, etc.

The tunnel insulating layer15may be formed to surround a sideman of the channel layer16. In an embodiment, the tunnel insulating layer15may include pure oxide. The core17may be formed in the channel layer16. The core17may have a single- or multi-layered structure. The core17may include an insulating material, such as oxide, nitride or an air gap. Alternatively, the core17may include a conductive material and may be an electrode layer, a vertical bit line, or the like.

The semiconductor device may have a form in which the core17is omitted, or the channel layer16is filled even in the center thereof.

The memory patterns14may be respectively located between the conductive layers11and the channel layer16, The memory patterns14may include a floating gate, a charge trap material, poly-silicon, nitride, a variable resistance material, a phase change material, and the like, or may include a combination thereof. The memory patterns14may be located between the insulating layers12. Each of the memory patterns14may be in contact with an upper insulating layer12and a lower insulating layer12, Each of the memory patterns14may have a first height H1, and each of the conductive layers11may have a second height H2, The first height H1may be substantially equal to or different from the second height H2. In an embodiment, the first height H1may be higher than the second height H2.

The blocking layer13may include first blocking patterns13A, a second blocking pattern13B, or third blocking patterns13C, or include any combination thereof.

The first blocking patterns13A may be respectively located between the conductive layers11and the memory pattern14, The first blocking patterns13A may include oxide. Each of the first blocking patterns13A may have substantially the same height H1as each of the memory patterns14, Each of the first blocking patterns13A may have a first thickness T1, and the first thickness T1may be 1 to 10 nm.

The second blocking pattern13B may be located between the first blocking patterns13A and the conductive layers11and between the conductive layers11and the insulating layers12. The second blocking pattern13B may extend to sidewalls of the insulating layers12. The second blocking pattern13B may surround the conductive layers11, and the barrier patterns11B may be respectively located between the second blocking pattern13B and the conductive patterns11A. The second blocking pattern13B may have a second thickness T2, and the second thickness T2may be 1 to 10 nm.

The second blocking pattern13B may include a material with a dielectric constant that is higher than that of the first blocking patterns13A. The second blocking pattern13B may include a high dielectric constant (high-k) material. In an embodiment, the second blocking pattern13B may include silicon nitride (Si3N4), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4), or hafnium silicate (HfSiO4), or include any combination thereof. In an embodiment, the second blocking pattern13B may include hafnium silicate (HfSiOx), and may adjust a dielectric constant of the second blocking pattern13B by adjusting a silicon concentration of the hafnium silicate (HfSiOx). The second blocking pattern13B with a relatively high silicon content may have a dielectric constant that is lower than that of the second blocking pattern13B with a relatively low silicon content, Thus, the dielectric constant of the second blocking pattern13B may be adjusted with the silicon content so that a gate coupling ratio can be tuned.

The third blocking patterns13C may be respectively located between the first blocking patterns13A and the memory patterns14. Each of the third blocking patterns13C may have substantially the same height H1as each of the memory patterns14. Each of the third blocking patterns13C may have substantially the same height H1as each of the first blocking patterns13A, Each of the third blocking patterns13C may have a third thickness T3, and the third thickness T3may be 1 to 10 nm.

The third blocking patterns13C may include a material with a dielectric constant that is higher than that of the first blocking patterns13A. The third blocking patterns13C may include a high dielectric constant (high-k) material. In an embodiment, the third blocking patterns13C may include silicon nitride (Si3N4), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4), or hafnium silicate (HfSiO4), or include any combination thereof. In an embodiment, the third blocking patterns13C may include hafnium silicate (HfSiOx), and may adjust a dielectric constant of the third blocking patterns13C by adjusting a silicon concentration of the hafnium silicate (HfSiOx). Accordingly, the gate coupling ratio can be tuned.

The third blocking patterns13C may substantially include the same material as the second blocking pattern13B, or include a material different from that of the second blocking pattern13B. In an embodiment, the second blocking pattern13B and the third blocking patterns13C may include hafnium silicate (HfSiOx), and a concentration of silicon included in the second blocking pattern13B and a concentration of silicon included in the third blocking patterns13C may be substantially equal to or different from each other.

Referring toFIG.1B, the semiconductor device may further include metal patterns18. The metal patterns18may be respectively located between the blocking layer13and the memory patterns14. In an embodiment, the metal patterns18may be respectively located between the first blocking patterns13A and the memory patterns14or may be respectively located between the third blocking patterns13C and the memory patterns14. The metal patterns18may have substantially the same height H1as the first blocking patterns13A, the third blocking patterns13C, or the memory patterns14. In an embodiment, each of the metal patterns18may have a fourth thickness T4, and the fourth thickness T4may be 1 to 100 Å.

The metal patterns18may include a metal with a relatively high work function. The metal with the high work function may have a high Fermi energy and may increase an inelastic scattering rate of electrons. Therefore, electrons that are tunneling toward the blocking layer13from the memory patterns14may be trapped in the metal pattern18. Although the blocking layer13includes a high dielectric constant (high-k) material, an increase in leakage current can be prevented or minimized. In an embodiment, the metal patterns18may include pure metal, metal nitride, or metal silicide. The metal patterns18may include titanium (Ti), platinum (Pt), tin (Sn), ruthenium (Ru), or titanium nitride (TiN), or include any combination thereof. The metal patterns18may include a nano structure such as a nano dot, a nano cluster, or a nano thin film.

According to the structure described above, since the blocking layer13includes a high dielectric constant (high-k) material, the gate coupling ratio can be increased. Further, the concentration of silicon included in the hafnium silicate (HfSiOx) may be adjusted, thereby tuning the gate coupling ratio. Since the blocking layer13is not interposed between the memory patterns14and the insulating layers12, the height of the gate structure GST can be decreased, and the degree of integration of the semiconductor device can be improved. Since the metal patterns18are located between the blocking layer13and the memory patterns14, the leakage current can be reduced.

FIGS.2A to2Care views illustrating a structure of a semiconductor device in accordance with an embodiment of the present disclosure. Hereinafter, descriptions of portions overlapping with those described above will be omitted.

Referring toFIG.2A, the semiconductor device may include a gate structure GST, a channel layer26, memory patterns24, and a blocking layer23. The semiconductor device may further include a tunnel insulating layer25, a core27, or a combination thereof.

The gate stack structure GST may include conductive layers21and insulating layers22, which are alternately stacked. The conductive layers21may be control gates. Each of the conductive layers21may include a conductive pattern21A and a barrier pattern21B. The barrier patterns21B may be located between the conductive patterns21A and third blocking patterns23C and between the conductive patterns21A and the insulating layers22. The channel layer26may penetrate the gate structure GST. The tunnel insulating layer25may be formed to surround a sidewall of the channel layer26. The core27may be formed in the channel layer26.

The memory patterns24may be respectively located between the conductive layers21and the channel layer26. In an embodiment, the memory patterns24may include a floating gate, a charge trap material, poly-silicon, nitride, a variable resistance material, a phase change material, and the like, or may include a combination thereof. The memory patterns24may be located between the insulating layers22. Each of the memory patterns24may be surrounded by the blocking layer23. Each of the memory patterns24may have a first height H1, and each of the conductive layers21may have a second height H2. The first height H1may be substantially equal to or different from the second height H2, In an embodiment, the second height H2may be higher than the first height H1.

The blocking layer23may include first blocking patterns23A, a second blocking pattern23B, the third blocking patterns23C, or a combination thereof. The first blocking patterns23A may be respectively located between the conductive layers21and the memory patterns24. Each of the first blocking patterns23A may have substantially the same height H2as each of the conductive layers21. The first blocking patterns23A may include hafnium silicate (HfSiOx). When the first blocking patterns23A includes the hafnium silicate (HfSiOx), a dielectric constant of the first blocking patterns23A may be adjusted by adjusting a silicon concentration of the hafnium silicate (HfSiOx). Accordingly, a gate coupling ratio can be tuned.

The second blocking pattern23B may be located between the first blocking patterns23A and the memory patterns24and between the memory patterns24and the insulating layers22, The second blocking pattern23B may extend to sidewalls of the insulating layers22. The second blocking pattern23B may surround the memory patterns24, The second blocking pattern23B may include a material with a dielectric constant that is lower than that of the first blocking patterns23A. In an embodiment, the second blocking pattern23B may include oxide.

The third blocking patterns23C may be respectively located between the first blocking patterns23A and the conductive layers21. Each of the third blocking patterns23C may have substantially the same height H2as each of the conductive layers21. Each of the third blocking patterns23C may have substantially the same height H2as each of the first blocking patterns23A. The third blocking patterns23C may include a material with a dielectric constant that is lower than that of the first blocking patterns23A. In an embodiment, the third blocking patterns23C may include oxide.

Referring toFIG.2B, each of the conductive layers21may include a conductive pattern21A and might not include the barrier pattern. Each of the conductive patterns21A may have a second height H2, and each of the memory patterns24may have a first height H1. The first height H1and the second height H2may be substantially equal to or different from each other. The second height H2may be higher than the first height H1.

Referring toFIG.2C, the semiconductor device may further include metal patterns28, The metal patterns28may be respectively located between the blocking layer23and the memory patterns24. In an embodiment, the metal patterns28may be respectively located between the first blocking patterns23A and the memory patterns24, or be respectively located between the third blocking patterns23C and the memory patterns24. The metal patterns28may have a height that is lower than that of the first blocking patterns23A or the third blocking patterns23C. The metal patterns28may have substantially the same height as the memory patterns24, Since the metal patterns28are located between the blocking layer23and the memory patterns24, leakage current can be decreased.

According to the structure described above, since the blocking layer23includes a high dielectric constant (high-k) material, the gate coupling ratio can be increased. Further, the concentration of silicon included in the hafnium silicate (HfSiOx) is adjusted, thereby tuning the gate coupling ratio. The blocking layer23might not be interposed between the conductive layers21and the insulating layers22. Thus, the height of the gate stack structure GST can be decreased, and the degree of integration of the semiconductor device can be improved. Since the metal patterns28are located between the blocking layer23and the memory patterns24, the leakage current can be reduced.

FIGS.3A to3Kare views illustrating a manufacturing method of a semiconductor device in accordance with an embodiment of the present disclosure. Hereinafter, descriptions of portions overlapping with those described above will be omitted.

Referring toFIG.3A, a stack structure ST is formed. The stack structure ST may include first material layers31and second material layers32, which are alternately stacked. The first material layers31may include a material with a high etch selectivity with respect to the second material layers32. In an embodiment, the first material layers31may include a sacrificial material, such as nitride, and the second material layers32may include an insulating material, such as oxide.

Subsequently, a first opening OP1may be formed, which penetrates the stack structure ST. The first opening OP1may have a plane with a circular shape, an elliptical shape, a polygonal shape, or the like. In an embodiment, a plurality of first openings OP1may be formed, which are arranged in a first direction and a second direction that intersects the first direction.

Referring toFIG.3B, second openings OP2are formed between the second material layers32. The second openings OP2may be used to secure spaces for forming memory cells. The second openings OP2may be formed by selectively etching the first material layers31. The second openings OP2may be connected to the first opening OP1.

Referring toFIG.3C, first blocking patterns33A are formed on the first material layers31exposed through the second openings OP2. The first blocking patterns33A may be formed by oxidizing the first material layers31exposed through the second openings OP2, The first blocking patterns33A may be respectively located in the second openings OP2, and be isolated from each other. The first blocking patterns33A may include oxide. A thickness33A_T of each of the first blocking patterns33A may be 1 to 10 nm.

Referring toFIG.3D, a third blocking layer33C is formed. The third blocking layer33C may be formed in the first opening OP1and the second opening OP2. The third blocking layer33C may be formed along surfaces of the second material layers32, which are exposed through the first opening OP1and the second openings OP2, and surfaces of the first blocking patterns33A. The third blocking layer33may include a material with a dielectric constant that is higher than that of the first blocking patterns33A. In an embodiment, the third blocking layer33C may include hafnium silicate (HfSiOx). A thickness33C_T of the third blocking layer33C may be 1 to 10 nm.

Referring toFIG.3E, sacrificial layers62are respectively formed in the second openings OP2. In an embodiment, the sacrificial layers62may be formed by forming a sacrificial material layer in the first opening OP1and the second openings OP2, and then etching a portion of the sacrificial material layer, which is formed in the first opening OP1. The third blocking layer33C may be partially exposed by the sacrificial layers62. Portions of the third blocking layer33C, which are formed in the second openings OP2, may be covered by the sacrificial layers62, and a portion of the third blocking layer33C, which is formed in the first opening OP1, may be exposed. The sacrificial layers62may include a material with a high etch selectivity with respect to the second material layers32and the third blocking layer33C. In an embodiment, the sacrificial layers62may include poly-silicon, tungsten, etc.

Referring toFIG.3F, third blocking patterns33CA are formed. The third blocking patterns33CA may be formed by selectively etching the third blocking layer33C, Portions of the third blocking layer33C, which are exposed by the sacrificial layers62, may be etched, and portions located between the first blocking patterns33A and the sacrificial layers62may remain. Accordingly, grooves G may be formed between the sacrificial layers62and the second material layers32.

Referring toFIG.3G, the sacrificial layers62are removed. The second openings OP2may be again opened by selectively etching the sacrificial layers62. The second material layers32and the third blocking patterns33CA may be exposed by the second openings OP2.

Referring toFIG.3H, memory patterns34are respectively formed in the second openings OP2. The memory patterns34may be isolated from each other by the second material layers32. In an embodiment, the memory patterns34may be formed by forming a memory layer in the first opening OP1and the second openings OP2, and then etching a portion of the memory layer, which is formed in the first opening OP1. Each of the memory patterns34may have a surface exposed through the first opening OP1, and include a groove G1at the surface thereof. The groove G1may be caused in a process of depositing the memory layer along inner surfaces of the first opening OP1and the second openings OP2.

The memory patterns34may include a floating gate, a charge trap material, poly-silicon, nitride, a variable resistance material, a phase change material, and the like, or may include a combination thereof. In an embodiment, the memory patterns34may be floating gates. The memory patterns34may be formed by forming a floating gate layer in the first opening OP1and the second openings OP2, and then etching the floating gate layer. The shape of the floating gates may be controlled by performing wet etching and oxidation on the floating gate layer.

Referring toFIG.3I, a tunnel insulating layer35is formed in the first opening OP1, When each of the memory patterns34includes the groove G1at the surface thereof, the tunnel insulating layer35may be filled in the groove G1, Subsequently, a channel layer36is formed in the tunnel insulating layer35. The channel layer36may completely fill the first opening OP1or partially fill the first opening OP1, Subsequently, a core37may be formed in the channel layer36.

Referring toFIG.3J, third openings OP3may be formed by removing the first materials31, In an embodiment, the third openings OP3may be formed by forming a slit (not shown) penetrating the stack structure ST and then selectively etching the first material layers31. The first blocking patterns33A may be respectively exposed through the third openings OP3.

Referring toFIG.3K, a second blocking pattern33B is formed. In an embodiment, the second blocking pattern33B may be formed along inner surfaces of the first opening OP1and the third openings OP3. The second blocking pattern33B may be formed on the surfaces of the second material layers32and the surfaces of the first blocking patterns33A. The second blocking pattern33B may include a material with a dielectric constant that is higher than that of the first blocking patterns33A. In an embodiment, the second blocking pattern33B may include hafnium silicate (HfSiOx). Accordingly, a blocking layer may be formed, which includes the first blocking patterns33A, the second blocking pattern33B, and the third blocking patterns33CA.

Subsequently, third material layers61may be respectively formed in the third openings OP3. In an embodiment, the third material layers61may be formed by forming a third material layer in the first opening OP1and the third openings OP3, and then etching a portion of the third material layer, which is formed in the first opening OP1. The third material layers61may be isolated from each other. In an embodiment, the third material layers61may be control gates. The third material layers61may be surrounded by the second blocking pattern33B. Each of the third material layers61may have a height that is lower than that of each of the memory patterns34. Accordingly, a gate structure GST may be formed, in which the third material layers61and the second material layers32are alternately stacked.

Each of the third material layers61may include a conductive pattern61A and a barrier pattern61B. In an embodiment, after a barrier layer and a conductive layer are formed in the first opening OP1and the third openings OP3, a portion of the barrier layer, which is formed in the first opening OP1, and a portion of the conductive layer, which is formed in the first opening OP1, may be etched. Accordingly, the conductive patterns61A and the barrier patterns61B respectively surrounding the conductive patterns61A may be formed.

According to the manufacturing method described above, the blocking layer33including a high dielectric constant (high-k) material is formed. Thus, a gate coupling ratio can be increased. Also, the blocking layer33is formed not to be interposed between the memory patterns34and the second material layers32. Thus, the length of the floating gate can be increased, and a program/erase window can be increased. Further, the height of the gate structure GST can be decreased, and the degree of integration of the semiconductor device can be improved.

FIGS.4A to4Fare views illustrating a manufacturing method of a semiconductor device in accordance with an embodiment of the present disclosure. Hereinafter, descriptions of portions overlapping with those described above will be omitted.

Referring toFIG.4A, a stack structure ST is formed. The stack structure ST may include first material layers41and second material layers42, which are alternately stacked. The first material layers41may include a material with a high etch selectivity with respect to the second material layers42. Subsequently, a first opening OP1may be formed, which penetrates the stack structure ST. Subsequently, second openings OP2may be formed by etching the first material layers41. Subsequently, first blocking patterns43may be formed by oxidizing the first material layers41exposed through the second openings OP2. Subsequently, third blocking patterns43C may be respectively formed in the second openings OP2. In an embodiment, the third blocking patterns43C may be formed by forming a third blocking layer in the first opening OP1and the second openings OP2, and then etching the third blocking layer, using a sacrificial layer. The third blocking patterns43C may include a material with a dielectric constant that is higher than that of the first blocking patterns43A, In an embodiment, the third blocking patterns43C may include hafnium silicate (HfSiOx).

Referring toFIGS.4B to4E, metal patterns48A are respectively formed in the second openings OP2, In an embodiment, the metal patterns48A may be formed by selectively depositing a metal on surfaces of the third blocking patterns43C, which are exposed through the second openings OP2. In an embodiment, the metal patterns48A may be formed through an etching process using sacrificial layers72. Hereinafter, a process using the sacrificial layers72will be described.

First, referring toFIG.4B, a metal layer48is formed. The metal layer48may be formed in the first opening OP1and the second openings OP2. The metal layer48may be formed along surfaces of the second material layers42and the surfaces of the third blocking patterns43C, which are exposed through the first opening OP1and the second openings OP2, The metal layer48may include pure metal or include metal nitride. The metal layer48may include titanium nitride (TiN), titanium (Ti), platinum (Pt) or ruthenium (Ru), or include any combination thereof. The metal layer48may include a nano structure such as a nano dot, a nano duster, or a nano thin film.

Referring toFIG.4C, the sacrificial layers72are respectively formed in the second openings OP2. The sacrificial layers72may include a material with a high etch selectivity with respect to the second material layers42and the metal layer48. In an embodiment, the sacrificial layers72may include poly-silicon, silicon oxide (SiO2), silicon nitride (SixNy), etc.

Referring toFIG.4D, the metal patterns48A are formed. The metal patterns48A may be formed by selectively etching the metal layer48. Portions of the metal layer48, which are exposed by the sacrificial layers72, may be etched, and portions that are located between the third blocking patterns43C and the sacrificial layers72may remain. Accordingly, grooves G may be formed between the sacrificial layers72and the second material layers42.

Referring toFIG.4E, the sacrificial layers72are removed. The second openings OP2may be again opened by selectively etching the sacrificial layers72. The second material layers42and the metal patterns48A may be exposed by the second openings OP2.

Referring toFIG.4F, memory patterns44may be respectively formed in the second openings OP2, Subsequently, a tunnel insulating layer45, a channel layer46, and a core47may be formed in the first opening OP1, or some of the tunnel insulating layer45, the channel layer46, and the core47may be formed.

Subsequently, the first material layers41may be removed, and a second blocking pattern43B may be formed. The second blocking pattern43B may include a material with a dielectric constant that is higher than that of the first blocking patterns43A. In an embodiment, the second blocking pattern430B may include hafnium silicate (HfSiOx). Accordingly, a blocking layer43may be formed, which includes the first blocking patterns43A, the second blocking pattern43B, and the third blocking patterns43C. Subsequently, third material layers71may be respectively formed in third openings OP3(seeFIG.3J). Each of the third material layers71may include a conductive pattern71A and a barrier pattern71B.

According to the manufacturing method described above, the metal patterns48A are formed between the memory patterns44and the blocking layer43, Thus, a leakage current can be reduced.

FIGS.5A to5Gare views illustrating a manufacturing method of a semiconductor device in accordance with an embodiment of the present disclosure. Hereinafter, descriptions of portions overlapping with those described above will be omitted.

Referring toFIG.5A, a stack structure ST is formed. The stack structure ST may include first material layers51and second material layers52, which are alternately stacked. The first material layers51may include a material with a high etch selectivity with respect to the second material layers52. In an example, the first material layers51may include a sacrificial material such as nitride, and the second material layers52may include an insulating material such as oxide. In another example, the first material layers51may include a conductive material such as poly-silicon, tungsten or molybdenum, and the second material layers52may include an insulating material such as oxide.

Subsequently, a first opening OP1may be formed, which penetrates the stack structure ST. Subsequently, second openings OP2may be formed by etching the first material layers51, Subsequently, third blocking patterns53C may be respectively formed in the second openings OP2, In an embodiment, the third blocking patterns53C may be formed by oxidizing the first material layers51exposed through the second openings OP2. The third blocking patterns53C may include oxide.

Referring toFIGS.5B to5E, first blocking patterns53AB may be respectively formed in the second openings OP2. In an embodiment, the first blocking patterns53AB may be respectively formed on surfaces of the third blocking patterns53C, which are exposed through the second openings OP2.

First, referring toFIG.5B, a first blocking layer53A is formed in the first opening OP1and the second openings OP2. The first blocking layer53A may be formed along surfaces of the second the second material layers52and the surfaces of the third blocking patterns53C, which are exposed through the first opening OP1and the second openings OP2. The first blocking layer53A may include a material with a dielectric constant that is higher than that of the third blocking patterns53C, In an embodiment, the first blocking layer53A may include hafnium silicate (HfSiOx).

Referring toFIG.5C, sacrificial layers82are respectively formed in the second openings OP2. The sacrificial layers82may include a material with a high etch selectivity with respect to the second materials layer52and the first blocking layer53A. In an embodiment, the sacrificial layers82may include poly-silicon, tungsten, etc.

Referring toFIG.5D, the first blocking patterns53AB are formed. The first blocking patterns53AB may be formed by selectively etching the first blocking layer53A, Portions of the first blocking layer53A, which are exposed by the sacrificial layers82, may be etched, and portions located between the third blocking patterns53C and the sacrificial layer82may remain. Accordingly, grooves G may be formed between the sacrificial layers82and the second material layers52.

Referring toFIG.5E, the sacrificial layers82are removed. The second openings OP2may be again opened by selectively etching the sacrificial layers82, The second material layers52and the first blocking patterns53A may be exposed by the second openings OP2.

Referring toFIG.5F, a second blocking pattern53B is formed. The second blocking pattern53B may be formed along inner surfaces of the first opening OP1and the second openings OP2. The second blocking insulating layer53B may include a material with a dielectric constant that is lower than that of the first blocking patterns53AB. In an embodiment, the second blocking pattern53B may include oxide. Accordingly, a blocking layer53may be formed, which includes the first blocking patterns53AB, the second blocking pattern53B, and the third blocking patterns53C.

Subsequently, memory patterns54may be respectively formed in the second openings OP2. The memory patterns54may be surrounded by the second blocking pattern53B. The memory patterns54may include a floating gate, a charge trap material, poly-silicon, nitride, a variable resistance material, a phase change material, and the like, or include a combination thereof. Subsequently, a tunnel insulating layer55, a channel layer56, and a core57may be formed in the first opening OP1, or some of the tunnel insulating layer55, the channel layer56, and the core57may be formed in the first opening OP1.

Metal patterns may be formed before the memory patterns54are formed. In an embodiment, the metal patterns may be formed through a selective deposition process or an etching process using sacrificial layers.

Referring toFIG.5G, the first material layers51may be replaced with third material layers81. In an example, when the first material layers51include a sacrificial material and the second material layers52include an insulating material, the first material layers51may be replaced with conductive layers. Each of the third material layers81may include a conductive pattern81A and a barrier pattern81B. In another example, when the first material layers51include a conductive material and the second material layers52include an insulating material, the first materials layer51may be silicided.

According to the manufacturing method described above, the blocking layer53including a high dielectric constant (high-k) material is formed. Thus, a gate coupling ratio can be increased. Also, the blocking layer53is formed not to be interposed between the third material layers81and the second material layers52, Thus, the height of a gate structure GST can be decreased, and the degree of integration of the semiconductor device can be improved.

FIG.6is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure.

Referring toFIG.6, the memory system1000may include a memory device1200configured to store data and a controller1100configured to communicate between the memory device1200and a host2000.

The host2000may be a device or system which stores data in the memory system1000or retrieves data from the memory system1000. The host2000may generate requests for various operations, and output the generated requests to the memory system1000. The requests may include a program request for a program operation, a read request for a read operation, an erase request for an erase operation, and the like. The host2000may communicate with the memory system1000through various interfaces such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (DATA), Serial Attached SCSI (SAS), or Non-Volatile Memory Express (NVMe), a Universal Serial Bus (USB), a Multi-Media Card (MMC), an Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

The host2000may include at least one of a computer, a portable digital device, a tablet, a digital camera, a digital audio player, a television, a wireless communication device, and a cellular phone, but embodiments of the present disclosure are not limited thereto.

The controller1100may control overall operations of the memory system1000, The controller1100may control the memory device1200according to a request of the host2000. The controller1100may control the memory device1200to perform a program operation, a read operation, an erase operation, and the like according to a request of the host2000. Alternatively, the controller1100may perform a background operation, etc. for improving the performance of the memory system1000without any request of the host2000.

The controller1100may transmit a control signal and a data signal to the memory device1200so as to control an operation of the memory device1200. The control signal and the data signal may be transmitted to the memory device1200through different input/output lines. The data signal may include a command, an address or data. The control signal may be used to distinguish a period in which the data signal is input.

The memory device1200may perform a program operation, a read operation, an erase operation, and the like under the control of the controller1100. The memory device1200may be implemented with a volatile memory device in which stored data disappears when the supply of power is interrupted or a nonvolatile memory device in which stored data is retained even when the supply of power is interrupted. The memory device1200may be a semiconductor device with the structures described above with reference toFIGS.1A to2C, The memory device1200may be a semiconductor device manufactured by the manufacturing method described above with reference toFIGS.3A to3K,4A to4F, or5A to5G. In an embodiment, the semiconductor device may include: a gate structure including insulating layers and control gates, which are alternately stacked; a channel layer penetrating the gate structure; floating gates respectively located between the control gates and the channel layer; first blocking patterns respectively located between the control gates and the floating gates; and a second blocking pattern located between the first blocking patterns and the control gates and between the control gates and the insulating layers, the second blocking pattern including a material with a dielectric constant that is higher than that of the first blocking patterns.

FIG.7is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure.

Referring toFIG.7, the memory system30000may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. The memory system30000may include a memory device2200and a controller2100capable of controlling an operation of the memory device2200.

The controller2100may control a data access operation of the memory device2200, e.g., a program operation, an erase operation, a read operation, or the like under the control of a processor3100.

Data programmed in the memory device2200may be output through a display3200under the control of the controller2100.

A radio transceiver3300may transmit/receive radio signals through an antenna ANT. For example, the radio transceiver3300may change a radio signal received through the antenna ANT into a signal that can be processed by the processor3100. Therefore, the processor3100may process a signal output from the radio transceiver3300and transmit the processed signal to the controller2100or the display3200. The controller2100may transmit the signal processed by the processor3100to the memory device2200. Also, the radio transceiver3300may change a signal output from the processor3100into a radio signal, and output the changed radio signal to an external device through the antenna ANT. An input device3400is a device capable of inputting a control signal for controlling an operation of the processor3100or data to be processed by the processor3100, and may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The processor3100may control an operation of the display3200such that data output from the controller2100, data output from the radio transceiver3300, or data output from the input device3400can be output through the display3200.

In some embodiments, the controller2100capable of controlling an operation of the memory device2200may be implemented as a part of the processor3100, or be implemented as a chip separate from the processor3100.

FIG.8is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure.

Referring toFIG.8, the memory system40000may be implemented as a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA), a portable multi-media player (PMP), an MP3 player, or an MP4 player.

The memory system40000may include a memory device2200and a controller2100capable of controlling a data processing operation of the memory device2200.

A processor4100may output data stored in the memory device2200through a display4300according to data input through an input device4200. For example, the input device4200may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor4100may control overall operations of the memory system40000, and control an operation of the controller2100. In some embodiments, the controller2100capable of controlling an operation of the memory device2200may be implemented as a part of the processor4100, or be implemented as a chip separate from the processor4100.

FIG.9is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure.

Referring toFIG.9, the memory system50000may be implemented as an image processing device, e.g., a digital camera, a mobile terminal with a digital camera attached thereto, a smart phone with a digital camera attached thereto, or a tablet PC with a digital camera attached thereto.

The memory system50000may include a memory device2200and a controller2100capable of controlling a data processing operation of the memory device2200, e.g., a program operation, an erase operation, or a read operation.

An image sensor5200of the memory system50000may convert an optical image into digital signals, and the converted digital signals may be transmitted to a processor5100or the controller2100. Under the control of the processor5100, the converted digital signals may be output through a display5300, or be stored in the memory device2200through the controller2100. In addition, data stored in the memory device2200may be output through the display5300under the control of the processor5100or the controller2100.

In some embodiments, the controller2100capable of controlling an operation of the memory device2200may be implemented as a part of the processor5100, or be implemented as a chip separate from the processor5100.

FIG.10is a diagram illustrating a memory system in accordance with an embodiment of the present disclosure.

Referring toFIG.10, the memory system70000may be implemented as a memory card or a smart card. The memory system70000may include a memory device2200, a controller2100, and a card interface7100.

The controller2100may control data exchange between the memory device2200and the card interface7100. In some embodiments, the card interface7100may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but the present disclosure is not limited thereto.

The card interface7100may interface data exchange between a host60000and the controller2100according to a protocol of the host60000. In some embodiments, the card interface7100may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. The card interface7100may mean hardware capable of supporting a protocol used by the host60000, software embedded in the hardware, or a signal transmission scheme.

When the memory system70000is connected to a host interface6200of the host60000such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, console video game hardware, or a digital set-top box, the host interface6200may perform data communication with the memory device2200through the card interface7100and the controller2100under the control of a microprocessor6100.

In accordance with the present disclosure, memory cells are three-dimensionally stacked, so that the degree of integration of the semiconductor device can be improved. Further, the semiconductor device can have a stable structure and improved reliability.

The exemplary embodiments of the present disclosure have been described in the drawings and specification. Although specific terminologies are used here, those are only to explain the embodiments of the present disclosure, Therefore, the present disclosure is not restricted to the above-described embodiments and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that various modifications can be made on the basis of the technological scope of the present disclosure in addition to the embodiments disclosed herein.

So far as not being differently defined, all terms used herein including technical or scientific terminologies have meanings that they are commonly understood by those skilled in the art to which the present disclosure pertains. The terms with the definitions as defined in the dictionary should be understood such that they have meanings consistent with the context of the related technique, So far as not being clearly defined in this application, terms should not be understood in an ideally or excessively formal way.