Patent ID: 12230938

DESCRIPTION OF EMBODIMENTS

An optical semiconductor device according to the embodiments of the present disclosure will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.

First Embodiment

FIG.1is a circuit diagram of an optical semiconductor device according to a first embodiment. An optical semiconductor device1, which is a transmitter optical sub-assembly (TOSA), includes a light emitting device2, a capacitor3, and a terminating resistor4. An anode of the light emitting device2is connected to a drive circuit5, and a cathode is connected to a GND. The capacitor3and the terminating resistor4are connected in parallel with the light emitting device2. The light emitting device2is, for example, an electro-absorption modulator laser diode (EML-LD). The light emitting device2emits light in accordance with a high-frequency modulated electric signal supplied from the drive circuit5. Note that while the capacitor3and the terminating resistor4are connected in this order from the drive circuit5toward the GND inFIG.1, connection order is not limited to this, and they may be connected in the order of the terminating resistor4and the capacitor3from the drive circuit5side.

FIG.2is a perspective view illustrating the optical semiconductor device according to the first embodiment.FIG.3is a plan view illustrating the optical semiconductor device according to the first embodiment.FIG.4is a side view illustrating the optical semiconductor device according to the first embodiment.

A submount7is provided on a carrier substrate6. The carrier substrate6and the submount7are formed with, for example, AlN. A conductive pattern8is provided on a lower surface of the carrier substrate6. A conductive pattern9which is a GND pattern is provided on an upper surface of the carrier substrate6. In the present embodiment, the conductive patterns8and9on the upper and lower surfaces of the carrier substrate6are made conductive with each other through a through-hole via, or the like. A conductive pattern10is provided on a lower surface of the submount7. The conductive pattern9of the carrier substrate6is bonded to the conductive pattern10of the submount7with solder, or the like. Conductive patterns11to13which are separate from each other are provided on an upper surface of the submount7. Note that surfaces of the conductive patterns9to13are gold-plated.

The conductive pattern11is connected to a modulated electric signal line15with a wire14. The conductive pattern12is connected to a GND line17with a wire16. Note that the GND line17is provided on both sides of the modulated electric signal line15and the conductive pattern12is provided on both sides of the conductive pattern11, thereby coplanar waveguides are respectively formed. The modulated electric signal line15and the conductive pattern11transmit a modulated electric signal from the drive circuit5.

The light emitting device2is provided on the conductive pattern12. A lower surface electrode18of the light emitting device2is bonded to the conductive pattern12with solder, or the like. An upper surface electrode19of the light emitting device2is connected to the conductive pattern11with a wire20.

The capacitor3is provided on the conductive pattern13. A lower surface electrode21of the capacitor3is bonded to the conductive pattern13with solder22. An upper surface electrode23of the capacitor3is connected to the upper surface electrode19of the light emitting device2with a wire24. Note that the lower surface electrode21is provided on the whole surface of the lower surface of a dielectric body of the capacitor3, and the upper surface electrode23is provided on the whole surface of the upper surface.

The terminating resistor4is provided on the upper surface of the submount7and is connected between the conductive pattern12and the conductive pattern13. A resistance value of the terminating resistor4is set at 50Ω to achieve impedance matching. However, the resistance value of the terminating resistor4may be set at a value other than 50Ω. Note that while the wires14,16,20, and24are, for example, gold wires, the wires may be ribbon-shaped gold wires.

The conductive pattern13has a rectangular planar shape, and the capacitor3has a quadrangular planar shape. The conductive pattern13has a long side of 550 μm, which is longer than sides of the capacitor3. Thus, the conductive pattern13has a protruding portion25which protrudes outside from a region below the capacitor3in planar view viewed in a vertical direction with respect to the upper surface of the submount7. This enables appearance inspection of the solder22by observing the solder22protruding from the capacitor3on the protruding portion25from above.

Meanwhile, the conductive pattern13has a short side of 290 μm, which is shorter than sides of the capacitor3. Thus, a width of the protruding portion25of the conductive pattern13is narrower than a width of the capacitor3at a boundary of the protruding portion25and the capacitor3.

Subsequently, effects of the present embodiment will be described in comparison with a comparative example.FIG.5is a plan view illustrating an optical semiconductor device according to the comparative example. In the comparative example, the conductive pattern13has a short side of 430 μm, and the conductive pattern13is larger than the width of the capacitor3. Thus, the conductive pattern13protrudes from all four sides at an outer periphery of the capacitor3. It is therefore possible to perform appearance inspection of the solder22. However, in the comparative example, the conductive pattern13is large, and thus, parasitic capacity between the conductive pattern9which is a GND pattern on the lower surface side of the submount7and the conductive pattern13on the upper surface side is large.

On the other hand, in the present embodiment, the width of the protruding portion25of the conductive pattern13is narrower than the width of the capacitor3. This reduces parasitic capacity between the conductive pattern9and the conductive pattern13, which increases amplitude responses at a frequency used at the optical semiconductor device. Thus, noise is reduced, and sensitivity of signals is improved, so that it is possible to improve high frequency performance.

FIG.6is a simulation result indicating relationship between signal attenuation and a frequency. In simulation, the resistance value of the terminating resistor4is set at 50Ω, and capacity of the capacitor3is set at 10 nF.FIG.6indicates a frequency of a signal input to the optical semiconductor device on a horizontal axis and indicates attenuation when the optical semiconductor device transmits a signal on a vertical axis. For example, in a case where a value on the vertical axis is −3 dB, signal intensity becomes half. In the comparative example, roll-off appears around 10 to 20 GHz which is a frequency used at the optical semiconductor device. On the other hand, in the present embodiment, it was confirmed that attenuation is close to 0 dB even around 10 to 20 GHz, and high frequency performance is achieved.

Further, the conductive pattern13has a rectangular planar shape, and the protruding portion25of the conductive pattern13protrudes from two facing sides of the capacitor3. In this manner, the protruding portion25preferably protrudes from two or more portions at an outer periphery of the capacitor3. This enables appearance inspection of the solder22at two or more portions, which leads to high reliability of the inspection.

Further, in a case where a device includes a plurality of sets each including the submount7, the conductive pattern13, the light emitting device2, the capacitor3, and the terminating resistor4, further miniaturization of the device is needed. Concerning this, in the present embodiment, the conductive pattern13has a rectangular shape, and the protruding portion25does not protrude from sides of the capacitor3which are orthogonal in a short side direction of the conductive pattern13. Thus, a width of the submount7of each set can be made smaller in a direction along the short side of the conductive pattern13. Therefore, further miniaturization can be achieved by arranging the plurality of sets side-by-side in a direction along the short side of the conductive pattern13.

Second Embodiment

FIG.7is a plan view illustrating an optical semiconductor device according to a second embodiment. The conductive pattern13has an L planar shape, and the protruding portion25of the conductive pattern13protrudes from two adjacent sides of the capacitor3. In a similar manner to the first embodiment, the width of the protruding portion25of the conductive pattern13is narrower than the width of the capacitor3at a boundary of the protruding portion25and the capacitor3. This reduces parasitic capacity between the conductive pattern9and the conductive pattern13, so that it is possible to improve high frequency performance.

Further, the protruding portion25protrudes from two portions at an outer periphery of the capacitor3, so that it is possible to perform appearance inspection of the solder22at two portions. Further, as a result of the conductive pattern13having an L shape, a length of the submount7in a vertical direction in the drawing can be made shorter. It is therefore possible to increase a resonant frequency of the submount7and improve high frequency performance. Other configurations and effects are similar to those in the first embodiment.

Third Embodiment

FIG.8is a plan view illustrating an optical semiconductor device according to a third embodiment. The protruding portion25of the conductive pattern13has a comb tooth shape. This reduces an area of the protruding portion25and reduces parasitic capacity between the GND pattern8and the conductive pattern13, so that it is possible to improve high frequency performance. Note that it is necessary to set a width of each comb tooth at equal to or greater than 100 μm to enable appearance inspection of the solder22. Other configurations and effects are similar to those in the first embodiment.

Fourth Embodiment

FIG.9is a side view illustrating an optical semiconductor device according to a fourth embodiment.FIG.10is a plan view illustrating a conductive pattern provided between a carrier substrate and a submount of the optical semiconductor device according to the fourth embodiment. The submount7and components above the submount7are omitted in this plan view.

The conductive patterns9and10provided between the carrier substrate6and the submount7exist below the light emitting device2, but do not exist below the capacitor3. The conductive patterns9and10are bonded to each other below the light emitting device2, so that heat generated by the light emitting device2can be dissipated on the carrier substrate6side.

In the first embodiment, the conductive patterns9and10which are GND patterns exist below the capacitor3, and thus, parasitic capacity exists between the conductive pattern13and the conductive patterns9and10. In contrast, the conductive patterns9and10do not exist below the capacitor3in the present embodiment, an interval between the conductive patterns can be expanded, so that parasitic capacity can be reduced. It is therefore possible to improve high frequency performance compared to the first embodiment. Other configurations and effects are similar to those in the first embodiment.

REFERENCE SIGNS LIST

1optical semiconductor device;2light emitting device;3capacitor;4terminating resistor;6carrier substrate;7submount;8conductive pattern (GND pattern);9conductive pattern (GND pattern, second conductive pattern);10conductive pattern (third conductive pattern);13conductive pattern (first conductive pattern);22solder;21lower surface electrode;23upper surface electrode;25protruding portion