Patent ID: 12237391

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the present inventive concept will now be described more fully with reference to the accompanying drawings.

FIG.1Aillustrates a plan view illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept.FIGS.1B and1Cillustrate cross-sectional views respectively taken along lines I-I′ and II-II′ ofFIG.1A, illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept.

Referring toFIGS.1A,1B, and1C, a substrate100may be provided and may include a first cell region PR and a second cell region NR. The substrate100may be a compound semiconductor substrate or a semiconductor substrate including one of, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, the substrate100may be a silicon substrate. The substrate100may have a top surface that is parallel to a first direction D1and a second direction D2, and a third direction D3is substantially perpendicular to the top surface of the substrate100. The first, second, and third directions D1, D2, and D3may be orthogonal to one another.

The first cell region PR and the second cell region NR may be defined by a second trench TR2that is formed on an upper portion of the substrate100. The second trench TR2may be positioned between the first cell region PR and the second cell region NR. The first cell region PR and the second cell region NR may be spaced apart from each other in the second direction D2with the second trench TR2therebetween. For example, the second trench TR2may extend in the first direction D1.

The first cell region PR and the second cell region NR may each be an area in which a standard cell, which constitutes a logic circuit, is provided. For example, the first cell region PR may be an area in which PMOS field effect transistors are provided, and the second cell region NR may be an area in which NMOS field effect transistors are provided.

Active patterns AP may be defined by a first trench TR1formed on the upper portion of the substrate100. The active patterns AP may be provided on the first cell region PR and the second cell region NR. The first trench TR1may be shallower than the second trench TR2. For example, the first trench TR1may have a bottom surface TR1blocated at a higher level than that of a bottom surface TR2bof the second trench TR2. For example, the first trench TR1may overlap the second trench TR2. The active patterns AP may extend in the first direction D1and may be spaced apart from each other in the second direction D2. The active patterns AP may be portions protruding from the substrate100in the third direction D3. The active patterns AP may each have widths in the first direction D1and the second direction D2, and the widths may decrease in the third direction D3away from the bottom surface TR1bthereof.

A first device isolation layers ST1may fill the first and second trenches TR1and TR2. The first device isolation layer ST1may include, for example, silicon oxide. Each of the active patterns AP may have an upper portion that protrudes upwardly from the first device isolation layer ST1. The first device isolation layer ST1might not cover the upper portion of each of the active patterns AP. The first device isolation layer ST1may partially cover a sidewall of each of the active patterns AP.

The active patterns AP in the first cell region PR may be spaced apart from each other in the first direction D1by a third trench TR3. The active patterns AP in the second cell region NR may also be spaced apart from each other in the first direction D1by the third trench TR3. The third trench TR3may be shallower than the first trench TR1. For example, the third trench TR3may have a bottom surface TR3blocated at a higher level than that of the bottom surface TR2bof the second trench TR2. For example, the bottom surface TR3bof the third trench TR3may be located at substantially the same height as that of the bottom surface TR1bof the first trench TR1.

A second device isolation layer ST2may fill the third trench TR3. The second device isolation layer ST2may include, for example, silicon oxide. The second device isolation layer ST2may extend along sidewalls of channel layers CH and along a sidewall of a bottom electrode GEb of one of gate electrodes GE which will be discussed below. At least a portion of the second device isolation layer ST2may protrude upwardly from a top surface of an uppermost one of channel layers CH which will be discussed below, and may overlap in the first direction D1with a portion of a top electrode GEt of one of gate electrodes GE which will be discussed below.

Each of the active patterns AP may include a plurality of channel layers CH. The channel layers CH may be provided on the upper portion of each of the active patterns AP. The channel layers CH may be spaced apart from each other in the third direction D3. The channel layers CH may include, for example, one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, the channel layers CH may include silicon (Si).

Each of the active patterns AP may have source/drain patterns SD on the upper portion thereof. For example, the source/drain patterns SD may be impurity regions having a first conductivity type (e.g., p-type) or a second conductivity type (e.g., n-type). The channel layers CH may be provided between a pair of source/drain patterns SD. The source/drain patterns SD may be epitaxial patterns formed by a selective epitaxial growth process.

The source/drain patterns SD may include a semiconductor material (e.g., SiGe) whose lattice constant is greater than that of a semiconductor material included in the substrate100, or the source/drain patterns SD may include a semiconductor material (e.g., Si) whose lattice constant is the same as that of a semiconductor material included in the substrate100. The second source/drain patterns SD2may provide the channel layers CH with compressive stress.

A plurality of gate electrodes GE may be provided to run across the active patterns AP and extend in the second direction D2. The gate electrodes GE may be spaced apart from each other in the first direction D1. Each of the gate electrodes GE may overlap in the third direction D3with the channel layers CH. Each of the gate electrodes GE may include a top electrode GEt and a bottom electrode GEb. The top electrode GEt may be provided on an uppermost one of the channel layers CH, and the bottom electrode GEb may be provided between the channel layers CH. Each of the top and bottom electrodes GEt and GEb may be a portion of a single unitary electrode. The bottom electrode GEb of each of the gate electrodes GE may extend between the channel layers CH and in the second direction D2parallel to a bottom surface of the top electrode GEt. For example, the bottom electrode GEb may extend below the lowermost channel layer CH. Each of the gate electrodes GE may cover top surfaces, bottom surfaces, and sidewalls of the channel layers CH. Each of transistors on the first and second cell regions PR and NR may be a three-dimensional field effect transistor (or gate-all-around type transistor) in which each of the gate electrodes GE three-dimensionally at least partially surrounds the channel layers CH.

The gate electrodes GE may include one or more of doped semiconductor materials, conductive metal nitrides, and metals. For example, each of the gate electrodes GE may include a plurality of different metal patterns. The plurality of metal patterns may have different resistances from each other. A composition and/or thickness of each of the plurality of metal patterns may be adjusted to achieve desired threshold voltages for transistors.

Each of the active patterns AP may have a first sidewall E1and a second sidewall E2that faces in the first direction D1toward the first sidewall E1. The gate electrodes GE may include a first gate electrode GE1, a second gate electrode GE2and a third gate electrode GE3. The first gate electrode GE1may be adjacent to the first sidewall E1. The second gate electrode GE2may be adjacent to the second sidewall E2, and the third gate electrode GE3may be between the first gate electrode GE1and the second gate electrode GE2. For example, the third gate electrode GE3may be provided in plural.

The first sidewall E1might not be aligned with a sidewall of the top electrode GEt that is included in the first gate electrode GE. The second sidewall E2might not be aligned with a sidewall of the top electrode Get that is included in the second gate electrode GE2. For example, each of the first and second sidewalls E1and E2may have a portion that has a curved shape or concave shape that is rounded or protruding toward the source/drain pattern SD adjacent thereto. For example, the first sidewall E1may have a curvature different from that of the sidewall E2. The second device isolation layer ST2may extend along the first sidewall E1or the second sidewall E2.

A first distance L1may be a maximum distance between the first sidewall E1and an outer sidewall of the top electrode GEt included in the first electrode GE1(e.g., the outer sidewall is a sidewall that is remote or furthest, among the sidewalls of the top electrode GEt, from the source/drain pattern SD or the active contact AC). A second distance L2may be a maximum distance between the second sidewall E2and an outer sidewall of the top electrode GEt included in the second gate electrode GE2. The first distance L1and the second distance L2may be measured in the first direction D1. However, the present inventive concept is not limited thereto. For example, the first distance L1may be the same as the second distance L2.

The first distance L1may be different from the second distance L2. It is illustrated by way of example that the second distance L2is greater than the first distance L1, but this is merely an example and the present inventive concept is not limited thereto. Each of the first and second distances L1and L2may be less than a width WG in the first direction D1of each of the gate electrodes GE. For example, each of the first and second distances L1and L2may be less than half of the width WG in the first direction D1of each of the gate electrodes GE.

First gate spacers GS1and second gate spacers GS2may be provided on sidewalls of the gate electrodes GE. The first gate spacers GS1may extend in the second direction D2along the sidewalls of the gate electrodes GE. Each of the first gate spacers GS1may extend in the third direction D3from a top surface of an uppermost one of the channel layers CH. The first gate spacers GS1may have their top surfaces located at a higher level than that of top surfaces of the gate electrodes GE (or that of a top surface of the top electrode GEt included in each of the gate electrodes GE). For example, the top surface of each of the first gate spacers GS1may be substantially coplanar with that of the gate capping patterns GP. For example, the first gate spacers GS1may include a nitride-based dielectric material. The first gate spacers GS1may include, for example, at least one of SiCN, SiCON, and/or SiN. In addition, the first gate spacers GS1may include a multi-layer formed of at least two of SiCN, SiCON, and/or SiN.

The first gate spacer GS1, which covers the outer sidewall of each of the first and second gate electrodes GE1and GE2(e.g., the outer sidewall is a sidewall that is remote or furthest, among the sidewalls of the first and second gate electrodes GE1and GE2, from the source/drain pattern SD or the active contact AC), may extend downwardly from a bottom surface of the top electrode GEt of each of the first and second gate electrodes GE1and GE2(or, from the top surface of the uppermost channel layer CH of the channel layers CH). In addition, the first gate spacer GS1may extend along a top surface of the second device isolation layer ST2. The first gate spacer GS1, which extends along the top surface of the second device isolation layer ST2, may have a bottom surface located at a level lower than that of a top surface of the active pattern AP adjacent thereto. However, the present inventive concept is not limited thereto. For example, the bottom surface of the first gate spacer GS1may be located above or at substantially the same level as that of the top surface of the active pattern AP.

The second gate spacers GS2may be horizontally provided between the source/drain patterns SD and the bottom electrode GEb of each of the gate electrodes GE. The second gate spacers GS2may be vertically provided between the channel layers CH, and may overlap in the third direction D3with the first gate spacers GS1. Each of the gate electrodes GE may be spaced apart in the first direction D1from the source/drain patterns SD with the second gate spacers GS2disposed therebetween.

A gate capping pattern GP may be provided on each of the gate electrodes GE. The gate capping pattern GP may extend in the second direction D2along the gate electrode GE. The gate capping pattern GP may include a material having an etch selectivity with respect to first and second interlayer dielectric layers110and120which will be discussed below. The gate capping pattern GP may include, for example, at least one of SiON, SiCN, SiCON, and/or SiN.

A gate dielectric pattern GI may be interposed between the gate electrode GE and the channel layers CH. The gate dielectric pattern GI may extend between the gate electrode GE and the first gate spacers GS1and between the gate electrode GE and the second gate spacers GS2. The gate dielectric pattern GI may extend between the bottom electrode GEb of the gate electrode GE and a sidewall of the second device isolation layer ST2adjacent to the bottom electrode GEb. The gate dielectric pattern GI may have an uppermost surface substantially coplanar with that of the gate electrode GE. The gate electrode GE may be spaced apart from the first and second gate spacers GS1and GS2with the gate dielectric pattern GI disposed therebetween. The bottom electrode GEb of the gate electrode GE may be spaced apart from the second device isolation layer ST2with the gate dielectric pattern GI disposed therebetween.

The gate dielectric pattern GI may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and/or high-k dielectric. The high-k dielectric may include a material, such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO), whose dielectric constant is greater than that of silicon oxide and that of silicon nitride.

A first interlayer dielectric layer110may be provided on the substrate100. The first interlayer dielectric layer110may cover top surfaces of the first and second device isolation layers ST1and ST2, sidewalls of the first gate spacers GS1, sidewalls of the active contacts AC, and top surfaces and sidewalls of the source/drain patterns SD. The first interlayer dielectric layer110may have a top surface located at substantially the same level as that of the top surface of the gate capping pattern GP and that of the top surfaces of the first gate spacers GS1. The first interlayer dielectric layer110may be provided on the substrate100, and a second interlayer dielectric layer120may cover the top surface of the gate capping pattern GP and the top surfaces of the first gate spacers GS1. The first and second interlayer dielectric layers110and120may include, for example, silicon oxide.

Active contacts AC may penetrate the first and second interlayer dielectric layers110and120and electrically connect to corresponding source/drain patterns SD. A pair of active contacts AC may be provided on opposite sides of each of the gate electrodes GE. When viewed in plan, each of the active contacts AC may have a linear or rectangular shape that extends in the second direction D2.

Each of the active contacts AC may include a conductive pattern FM and a barrier pattern BM that at least partially surrounds the conductive pattern FM. For example, the conductive pattern FM may include at least one of aluminum, copper, tungsten, molybdenum, and/or cobalt. The barrier pattern BM may cover a sidewall and a bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include at least one of, for example, titanium, tantalum, tungsten, nickel, cobalt, and/or platinum. The metal nitride layer may include at least one of, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and/or platinum nitride (PtN).

The active contacts AC may be self-aligned contacts. For example, the gate capping pattern GP and the first gate spacers GS1may be used to form the active contacts AC in a self-alignment manner. For example, the active contacts AC may cover at least portions of the sidewalls of the first gate spacers GS1. According to an exemplary embodiment of the present inventive concept, the active contacts AC may cover portions of the top surfaces of the gate capping patterns GP.

A silicide pattern may be provided between each of the active contacts AC and each of the source/drain patterns SD. Each of the active contacts AC may be electrically connected through the silicide pattern to one of the source/drain patterns SD. The silicide pattern may include metal silicide. The silicide pattern may include, for example, at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and/or cobalt silicide.

A gate contact GC may be provided to penetrate the second interlayer dielectric layer120and the gate capping pattern GP and to electrically connect to at least one of the gate electrodes GE. According to an exemplary embodiment of the present inventive concept, the gate contact GC may be provided on the first device isolation layer ST1between the first cell region PR and the second cell region NR. When viewed in plan, the gate contact GC may have a linear or rectangular shape that extends in the first direction D1. Similar to the active contact AC, the gate contact GC may include a conductive pattern FM and a barrier pattern BM that at least partially surrounds the conductive pattern FM.

A third interlayer dielectric layer130may be provided on the second interlayer dielectric layer120. The third interlayer dielectric layer130may be provided on the second interlayer dielectric layer120with first lines M1, the first via V1, and a second via V2disposed in the second interlayer dielectric layer120. The first and second vias V1and V2may be provided below the first lines M1. The first lines M1may extend in the first direction D1. The first lines M1may be arranged along the first direction D1or the second direction D2. The first via V1may lie between and electrically connect one of the first lines M1and one of the active contacts AC to each other. The second via V2may lie between and electrically connect the gate contact GC and one of the first lines M1to each other.

The first lines M1and one of the first and second vias V1and V2may be integrally connected into a single conductive structure. For example, the first lines M1may be formed simultaneously with one of the first or second vias V1or V2. A dual damascene process may be performed such that the first lines M1and one of the first or second vias V1or V2may be formed into a single conductive structure. According to an exemplary embodiment of the present inventive concept, metal layers (e.g., M2, M3, M4, etc.) may be additionally stacked on the third interlayer dielectric layer130.

FIG.2illustrates an enlarged cross-sectional view of sections A and B ofFIG.1B, partially illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept.

FIG.2partially depicts the first gate electrode GE1, which is adjacent to the first sidewall E1, and the second gate electrode GE2, which is adjacent to the second sidewall E2. In the following description, a width may be a maximum or average width in the first direction D1.

Referring to section A ofFIG.2, the first gate electrode GE1may include a bottom electrode GEb and a top electrode GEt. The bottom electrode GEb of the first gate electrode GE1may include a first part GEb1, a second part GEb2, and a third part GEb3that are sequentially stacked with the channel layers CH therebetween. The first part GEb1, the second part GEb2, and the third part GEb3of the bottom electrode GEb may be spaced apart, in the third direction D3, from each with the channel layers CH therebetween. The first part GEb1, the second part GEb2, and the third part GEb3may have different widths from each other. For example, the width of the first part GEb1may be greater than that of the second part GEb2, and the width of the second part GEb2may be greater than that of the third part GEb3.

Each of the first, second, and third parts GEb1, GEb2, and GEb3of the bottom electrode GEb included in the first gate electrode GE1may have a sidewall with a curved shape that is rounded along a profile of the first sidewall E1.

The top electrode GEt of the first gate electrode GE1may include a first part GEt1and a second part Get2. The first part Get1may be adjacent to the bottom electrode GEb, and the second part GEt2may be disposed on the first part GEt1. The first part GEt1of the top electrode GEt may overlap in the first direction D1with the second device isolation layer ST2. The second part GEt2of the top electrode GEt may have a width greater than that of the first part GEt1of the top electrode GEt.

Referring to section B ofFIG.2, the second gate electrode GE2may include a bottom electrode GEb and a top electrode GEt. The second gate electrode GE2may include a fourth part GEb4, a fifth part GEb5, and a sixth part GEb6that are sequentially stacked with the channel layers CH therebetween. The fourth part GEb4, the fifth part GEb5, and the sixth part GEb6of the bottom electrode GEb may be spaced apart from each other in the third direction D3with the channel layers CH therebetween. The fourth part GEb4, the fifth part GEb5, and the sixth part GEb6may have different widths from each other. For example, the width of the fourth part GEb4may be greater than that of the fifth part GEb5, and the width of the fifth part GEb5may be greater than that of the sixth part GEb6.

Each of the fourth, fifth, and sixth parts GEb4, GEb5, and GEb6of the bottom electrode GEb included in the second gate electrode GE2may have a sidewall with a curved shape that is rounded along a profile of the second sidewall E2.

In comparison with sections A and B ofFIG.2, the first part GEb1of the bottom electrode GEb included in the first gate electrode GE1may be located at substantially the same height as that of the fourth part GEb4of the bottom electrode GEb included in the second gate electrode GE2. In the following description, the phrase “components having their thickness in the third direction D3are located at the same level” may mean that top surfaces of the components are located at the same level, and that bottom surfaces of the components are also located at the same level. The first part GEb1of the bottom electrode GEb included in the first gate electrode GE1may have a width different from that of the fourth part GEb4of the bottom electrode GEb included in the second gate electrode GE2. For example, the width of the first part GEb1of the bottom electrode GEb included in the first gate electrode GE1may be greater than that of the fourth part GEb4of the bottom electrode GEb included in the second gate electrode GE2.

In addition, the second part GEb2of the bottom electrode GEb included in the first gate electrode GE1may be located at substantially the same level as that of the fifth part GEb5of the bottom electrode GEb included in the second gate electrode GE2. The width of the second part GEb2of the bottom electrode GEb included in the first gate electrode GE1may be different from that of the fifth part GEb5of the bottom electrode GEb included in the second gate electrode GE2For example, the width of the second part GEb2of the bottom electrode GEb included in the first gate electrode GE1may be greater than that of the fifth part GEb5of the bottom electrode GEb included in the second gate electrode GE2.

In addition, the third part GEb3of the bottom electrode GEb included in the first gate electrode GE1may be located at substantially the same level as that of the sixth part GEb6of the bottom electrode GEb included in the second gate electrode GE2. The third part GEb3of the bottom electrode GEb included in the first gate electrode GE1may have a width different from that of the sixth part GEb6of the bottom electrode GEb included in the second gate electrode GE2. For example, the width of the third part GEb3of the bottom electrode GEb included in the first gate electrode GE1may be greater than that of the sixth part GEb6of the bottom electrode GEb included in the second gate electrode GE2.

The top electrode GEt of the second gate electrode GE2may have a structure substantially the same as that of the top electrode GEt of the first gate electrode GE1. For example, at least a portion of the top electrode GEt of the second gate electrode GE2may overlap in the first direction D1with the second device isolation layer ST2adjacent thereto.

FIG.3illustrates a cross-sectional views taken along line I-I′ ofFIG.1A, illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenience of explanation, the same technical features as those discussed above will not be repeated herein, and the following description will focus on differences between previous and present embodiments.

Referring toFIGS.1C and3, the third trench TR3may be deeper than the first trench TR1. In this case, the bottom surface TR3bof the third trench TR3may be located at a level lower than that of the bottom surface TR1bof the first trench TR1. For example, the bottom surface TR3bof the third trench TR3may be located at substantially the same level as that of the bottom surface TR2bof the second trench TR2.

FIG.4illustrates a cross-sectional views taken along line I-I′ ofFIG.1A, illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept. For the sake of convenience of explanation, the same technical features as those discussed above will not be repeated herein, and the following description will focus on differences between previous and present embodiments.

Referring toFIG.4, the first sidewall E1may have first recessed portions E1R. For example, the first recessed portions E1R may be more recessed than the sidewalls of adjacent channel layers CH in a direction toward the source/drain pattern SD. For example, the side surfaces of the bottom electrode GEb may be recessed toward the source/drain pattern SD.

Similar to the first sidewall E1, the second sidewall E2may have second recessed portions E2R. The second recessed portions E2R may be more recessed than the sidewalls of adjacent channel layers CH in a direction toward the source/drain pattern SD.

For example, each of the first and second sidewalls E1and E2may have an embossed curved shape. The bottom electrode GEb of each of the first and second gate electrodes GE1and GE2may have a sidewall with a curved shape that is rounded along the first recessed portions E1R or the second recessed portions E2R.

FIGS.5A,6A,7A, and8Aillustrate plan views illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept.FIGS.5B,6B,7B, and8Billustrate cross-sectional views taken along line I-I′ ofFIGS.5A,6A,7A, and8A, respectively, illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept.FIGS.5C and8Cillustrate cross-sectional views taken along line II-II′ ofFIGS.5A and8A, respectively, illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept.

With reference toFIGS.5A to8C, the following will describe in detail a method of fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept.

Referring toFIGS.5A,5B, and5C, a substrate100may be provided and may include a semiconductor material. In addition, the substrate100may have a polygonal shape (e.g., a square shape or rectangular shape) extending in a first direction D1and a second direction D2. For example, first semiconductor layers and second semiconductor layers may be alternately and repeatedly stacked on the substrate100. The first semiconductor layers may include one of, for example, silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or the second semiconductor layers may include another of, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, the first semiconductor layers may include silicon (Si), and the second semiconductor layers may include silicon-germanium (SiGe).

A first etching process may be performed to form a first trench TR1that provides active patterns AP. During the first etching process, the first and second semiconductor layers may be patterned to respectively form first semiconductor patterns SP1and second semiconductor patterns SP2. The first and second semiconductor patterns SP1and SP2may be alternately and repeatedly stacked on each of the active patterns AP.

A second etching process may be patterned to form a second trench TR2that provides a first cell region PR and a second cell region NR. The second trench TR2may be formed deeper than the first trench TR1. For example, the second trench TR2may have a bottom surface TR2blocated at a level lower than that of a bottom surface TR1bof the first trench TR1. Active pattern AP may be correspondingly formed on the first cell region PR and the second cell region NR.

A first device isolation layer ST1may be formed to fill the first and second trenches TR1and TR2. The first device isolation layer ST1may include a dielectric material, such as silicon oxide. The first device isolation layer ST1may be recessed until upper portions of the active patterns AP are exposed. The upper portions of the active patterns AP may protrude upwardly in a third direction D3from the first device isolation layer ST1.

A plurality of sacrificial patterns PP may be formed to extend across the active patterns AP. The sacrificial patterns PP may be spaced apart from each other in a first direction D1. Each of the sacrificial patterns PP may be formed to have a linear or rectangular shape that extends in a second direction D2.

The formation of the sacrificial patterns PP may include forming a sacrificial layer on the substrate100, forming a hardmask pattern MP on the sacrificial layer, and using the hardmask pattern MP as an etching mask to pattern the sacrificial layer. The sacrificial layer may include, for example, polysilicon. The hardmask pattern MP may include, for example, silicon nitride.

Referring toFIGS.6A and6B, a third etching process may be performed to form a third trench TR3that divides the active patterns AP into separate pieces in the first direction D1. The third etching process may include, for example, at least one wet etching process and at least one dry etching process. According to an exemplary embodiment of the present inventive concept, during the third etching process, the second semiconductor pattern SP2may be recessed more than the first semiconductor patterns SP1.

The third trench TR3may form a plurality of active patterns AP that are spaced apart from each other in the first direction D1in each of the first cell region PR and the second cell region NR. The third trench TR3may be formed shallower than the second trench TR2, but this is merely an example and the present inventive concept is not limited thereto.

A second device isolation layer ST2may be formed on the substrate100and may fill the third trench TR3. The second device isolation layer ST2may include a dielectric material the same as that of the first device isolation layer ST1. The formation of the second device isolation layer ST2may include filling the third trench TR3with a dielectric material and recessing the second device isolation layer ST2until a top surface of the second device isolation layer ST2is located at the same level as that of a top surface of the first device isolation layer ST1. Afterwards, at least a portion of the second device isolation layer ST2may remain while covering sidewalls of the first and second semiconductor patterns SP1and SP2.

The sacrificial patterns PP may be partially etched during the formation of the third trench TR3. For example, the sacrificial pattern PP adjacent to the third trench TR3may be partially etched on a lower portion thereof, and the second device isolation layer ST2may fill an etched spaced.

Afterwards, first gate spacers GS1may be formed to cover opposite sidewalls of each of the sacrificial patterns PP. A portion of the first gate spacer GS1may extend downwardly from bottom surfaces of the sacrificial pattern PP to extend onto the top surface of the second device isolation layer ST2.

The formation of the first gate spacers GS1may include forming a first gate spacer layer that covers a top surface of an uppermost one of the first semiconductor patterns SP1, a top surface of the hardmask pattern MP, sidewalls of the hardmask pattern MP and the sacrificial pattern PP, and the top surface of the second device isolation layer ST2, and then removing the first gate spacer layer from the top surface of the uppermost one of the first semiconductor patterns SP1and the top surface of the hardmask pattern MP. The first gate spacers GS1may include, for example, silicon nitride.

Referring toFIGS.7A and7Btogether withFIG.6B, the active patterns AP may be partially recessed to form first recessions RC1. The first recessions RC1may be formed on opposite sides of the sacrificial pattern PP. The first recessions RC1may be formed by using the hardmask pattern MP and the first gate spacers GS1as an etching mask to etch an upper portion of each of the active patterns AP.

The second semiconductor patterns SP2may have parts exposed to the first recessions RC1, and the exposed parts may be recessed in the first direction D1to form second recessions RC2. The first semiconductor patterns SP1exposed to the first recessions RC1might not be removed during the formation of the second recessions RC2. Second gate spacers GS2may be formed in the second recessions RC2. The formation of the second gate spacers GS2may include forming a second gate spacer layer that covers inner sidewalls of the first and second recessions RC2, and removing a portion of the second gate spacer layer formed in the first recessions RC1. The second gate spacers GS2may include, for example, silicon nitride. However, according to an exemplary embodiment of the present inventive concept, neither the second recessions RC2nor the second gate spacers GS2may be formed.

Source/drain patterns SD may be formed to fill the first recessions RC1on upper portions of the active patterns AP. A pair of source/drain patterns SD may be formed on opposite sides of the sacrificial pattern PP.

A selective epitaxial growth process may be performed in which the first semiconductor patterns SP1and top surfaces of the active patterns AP exposed to the first recessions RC1are used as seeds to form the source/drain patterns SD. For example, impurities may be in-situ implanted during the selective epitaxial growth process for forming the source/drain patterns SD. For another example, impurities may be implanted after the formation of the source/drain patterns SD. According to an exemplary embodiment of the present inventive concept, the source/drain patterns SD may have their top surfaces located at a level higher than that of the top surface of the first device isolation layer ST1and that of the top surfaces of the active patterns AP, and the top surfaces of the source/drain patterns SD may be externally exposed.

A first interlayer dielectric layer110may be formed to cover sidewalls and top surfaces of the source/drain patterns SD and also to cover sidewalls and top surfaces of the first gate spacers GS1.

Thereafter, a planarization process may be performed until the top surfaces of the sacrificial patterns PP are exposed. The planarization process may remove the hardmask pattern MP and a portion of the first interlayer dielectric layer110positioned at a level higher than that the top surfaces of the sacrificial patterns PP. The planarization process may be, for example, an etch-back process or a chemical mechanical polishing (CMP) process. After the planarization process, the first interlayer dielectric layer110may have a top surface substantially coplanar with those of the sacrificial patterns PP.

Referring toFIGS.8A,8B, and8Ctogether withFIG.7B, the sacrificial pattern PP may be selectively removed. The removal of the sacrificial pattern PP may form a first empty space ES1that exposes a portion of each of the active patterns AP, an uppermost one of the first semiconductor patterns SP1, and inner sidewalls of the first gate spacers GS1. For example, the first empty space ES1may expose the second semiconductor patterns SP2.

After that, the second semiconductor patterns SP2may be selectively removed. The second semiconductor patterns SP2may be selectively removed by an etching process in which the second semiconductor patterns SP2have their high etch selectivity with respect to the first semiconductor patterns SP1. After the etching process is performed on the second semiconductor patterns SP2, the first semiconductor patterns SP1may remain without being removed. After the etching process is performed on the second semiconductor patterns SP2, the first and second gate spacers GS1and GS2may also remain without being removed. The removal of the second semiconductor patterns SP2may form second empty spaces ES2. Each of the second empty spaces ES2may a gap between the first semiconductor patterns SP1that are adjacent to each other in the third direction D3.

Referring back toFIGS.1A,1B,1C, and2together withFIGS.8B and8C, a gate electrode GE may be formed to fill the first and second empty spaces ES1and ES2. A top electrode GEt of the gate electrode GE may at least partially fill the first empty space ES1, and a bottom electrode GEb of the gate electrode GE may at least partially fill the second empty spaces ES2. Before the gate electrode GE is formed, a gate dielectric pattern GI may be formed to conformally cover sidewalls, top surfaces, and bottom surfaces of the first and second empty spaces ES1and ES2. The first semiconductor patterns SP1may be called channel layers CH.

Thereafter, a gate capping pattern GP may be formed on the gate electrode GE. The formation of the gate capping pattern GP may include partially recessing the gate electrode GE that fills the first empty space ES1, forming a capping layer that fills a hollow area where the gate electrode GE is recessed, and performing a planarization process to remove a portion of the capping layer. For example, the gate capping layer may be planarized such that a top surface of the gate capping pattern GP is substantially coplanar with top surfaces of the first gate spacers GS1. The gate capping pattern GP may include, for example, silicon nitride. The gate capping pattern GP may have a top surface substantially coplanar with those of the first gate spacers GS1.

Afterwards, active contacts AC may be formed on opposite sides of the gate electrode GE. A second interlayer dielectric layer120may be formed to cover the top surface of the first interlayer dielectric layer110and the top surface of the gate capping pattern GP. A gate contact GC may be formed to penetrate the second interlayer dielectric layer120and the gate capping pattern GP, and may be electrically connected to the gate electrode GE.

A third interlayer dielectric layer130may be formed on a top surface of the second interlayer dielectric layer120, top surfaces of the active contacts AC, and a top surface of the gate contact GC. A first metal layer may be formed in the third interlayer dielectric layer130, and the first metal layer may include first lines M1, a first via V1, and a second via V2. The first via V1may be connected to the top surface of the active contact AC. The second via V2may be connected to the top surface of the gate contact GC. Additional metal layers (e.g., M2, M3, M4, etc.) may be provided on the third interlayer dielectric layer130.

A semiconductor device according to an exemplary embodiment of the present inventive concept may have an asymmetric structure on first and second sidewalls of an active pattern, and thus it may be possible to minimize or prevent possible manufacturing defects (e.g., electrical short of the source/drain patterns SD or parasitic epitaxial growth of patterns). Accordingly, the semiconductor device according to an exemplary embodiment of the present inventive concept may increase in yield, electrical properties, and reliability.

While the present inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the present inventive concept.