Patent ID: 12243833

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIGS.1A-1Cillustrate the formation of some embodiments of a first semiconductor device101having an Electromagnetic Interference (EMI) film121(shown inFIG.1C).FIGS.2A-2Cillustrate the formation of some embodiments of a second semiconductor device201having an Electromagnetic Interference (EMI) film121. In some embodiments, the first semiconductor device101or the second semiconductor device201may be incorporated into an Integrated Fan-Out (InFO) structure, an Integrated Fan-Out Package-on-Package (InFO-PoP) structure, or another type of package structure.

Referring toFIGS.1A-1C,FIG.1Aillustrates first semiconductor devices101prior to singulation. Prior to singulation, each first semiconductor device101is separated by a scribe region105.FIG.1Ashows two first semiconductor devices101as an illustrative example, and in other embodiments more than two first semiconductor devices101may be formed together, each separated by scribe regions105. The first semiconductor devices101may be semiconductor devices designed for an intended purpose such as a memory die (e.g., a DRAM die), a logic die, an integrated circuit, a central processing unit (CPU) die, combinations of these, or the like.

In some embodiments, the first semiconductor devices101include a first substrate103, first contact pads107, first passivation layer109, first via layer111, and second passivation layer113. The first substrate103may be a wafer or other substrate, and may be a semiconductor material such as silicon, germanium, or gallium arsenide, may be doped or undoped, or may be silicon-on-insulator (SOI), silicon dioxide (SiO2) or other insulating material, or another material. Generally, an SOI substrate is a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The first substrate103may also be a multi-layered substrate, gradient substrate, hybrid orientation substrate, or another type of substrate or wafer.

In some embodiments, the first substrate103may include active devices (not shown) and an optional metallization layer (not shown). The active devices of the first semiconductor devices101may include a wide variety of active devices and passive devices such as transistors, capacitors, resistors, inductors and the like that may be used to generate the desired structural and functional features of the design for the first semiconductor devices101. The active devices on or within the first substrate103may be formed using any suitable methods. The optional metallization layers (not shown) may be formed over the active devices, and are designed to connect the various active devices to form functional circuitry. In some embodiments, the metallization layers are formed of alternating layers of dielectric and conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, etc.). In some cases, the metallization layers include one or more redistribution layers (RDL).

FIG.1Aalso shows first semiconductor devices101mounted to a frame115by a first adhesive layer117. The frame115may be, for example, a silicon-based material, such as glass or silicon oxide, or another material, such as aluminum oxide, metal, ceramic, polymer, combinations of any of these materials, or the like. The first adhesive layer117may be a die attach film (DAF) such as an epoxy resin, a phenol resin, acrylic rubber, silica filler, or a combination thereof, and may be applied using a lamination technique. However, any other suitable alternative materials and formation techniques may alternatively be used. In some embodiments, the first substrate103has been thinned prior to mounting on the frame115. The thinning may be performed, e.g., using a mechanical grinding or chemical mechanical polishing (CMP) process whereby chemical etchants and abrasives are utilized to react and grind away the first substrate103.

The first contact pads107may be formed over and in electrical contact with metallization layers or active devices of first semiconductor devices101. As an illustrative example,FIGS.1A-1Cshow first contact pad107aand first contact pad107b, collectively referred to as first contact pads107. Other embodiments may include more or fewer first contact pads107. In some embodiments, the first contact pads107are aluminum, but other conductive materials may be used such as copper, AlCu, or other materials. In some embodiments, the first contact pads107are formed using a deposition process, such as sputtering, to form a layer of conductive material. Portions of the layer of conductive material are then removed through a suitable process (such as photolithographic masking and etching) to form the first contact pads107. In some embodiments, the first contact pads107are underbump metallization (UBMs).

The first passivation layer109may be formed on the first substrate103over any metallization layers and the first contact pads107. The first passivation layer109may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, combinations of these, or the like. In some embodiments, the first passivation layer109may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, may be utilized. The first passivation layer109may be placed using, e.g., a spin-coating process. In other embodiments, the first passivation layer109may be formed through a process such as chemical vapor deposition (CVD). Openings in the first passivation layer109may be formed over the first contact pads107using a suitable photolithography and etching process.

The first via layer111is formed over the first contact pads107and is electrically connected to the first contact pads107. As an illustrative example,FIGS.1A-1Cshow a first via111aformed over first contact pad107aand a first via111bformed over first contact pad107b. Other embodiments of the first via layer111may include more or fewer first vias. The first via layer111may be formed to provide conductive regions for electrical contact between the first contact pads107and external features. For example, regions of the first via layer111may be connected to an RDL subsequently formed over a first semiconductor device101. (See, for example, RDL601a-cshown inFIGS.6-9). The first via layer111may be formed from a conductive material such as copper, although other conductive materials such as nickel, gold, solder, metal alloy, combinations of these, or the like may also be used. The first via layer111may be formed through any suitable process (such as deposition, damascene, dual damascene, etc.). In some embodiments, the first via layer111may be formed using a process such as electroplating. In some embodiments, a portion of the first via layer111extends into the scribe region105, as shown for first via111binFIG.1A.

The second passivation layer113may be formed on the first passivation layer109and the first via layer111. The second passivation layer113may formed from a material or from a process described above with respect to first passivation layer109. The second passivation layer113may be the same material as or a different material than first passivation layer109. In some embodiments, the first semiconductor device101may have more passivation layers and/or metallization layers, and in some embodiments, the first semiconductor device101may have fewer passivation layers and/or metallization layers.

FIG.1Billustrates first semiconductor devices101after a singulation process. The singulation process removes the scribe region105and separates the first semiconductor devices101. In some embodiments, the singulation process may be performed by using a saw blade to slice through the substrate103, the first passivation layer109, and the second passivation layer113. The singulation process may also slice through some or all of the first adhesive layer117. As shown inFIGS.1A-1B, the singulation process also slices through the portion of the first via layer111that extends into the scribe region105, exposing a sidewall of the first via layer111. An example exposed sidewall119of first via111bis indicated inFIG.1B, though other embodiments may include more than one exposed sidewall. After singulation, the exposed sidewall of the first via layer111may be substantially coplanar with a sidewall of the substrate103. As one of ordinary skill in the art will recognize, utilizing a saw blade for the singulation process is merely one illustrative embodiment and is not intended to be limiting. Any suitable technique may be used for performing the first singulation process, such as utilizing one or more etches. These and any other suitable techniques may be used to singulate the first semiconductor devices101.

FIG.1Cillustrates an EMI film121formed over the singulated first semiconductor devices101. In some embodiments, EMI film121is formed from a single conformal layer of material, and in some embodiments, EMI film121is formed from multiple conformal layers of materials. EMI film121is formed over the first semiconductor devices101to shield the first semiconductor devices101from electromagnetic interference.

In some embodiments, EMI film121is formed from an adhesion layer123aand a conduction layer123b. The adhesion layer123ais formed conformally over the exposed surfaces of the first semiconductor devices101. The adhesion layer123amay improve adhesion of the conduction layer123bto the first semiconductor devices101. In some embodiments the adhesion layer1203may be a conductive metal such as stainless steel (SUS), titanium, or another conductive metal. The adhesion layer123amay be formed using a suitable technique, for example a deposition process such as sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), spray coating, electroless plating, or the like. In some embodiments, the adhesion layer123ais formed having a thickness of between about 0.05 μm and about 1 μm, such as about 0.1 μm.

The conduction layer123bis formed conformally over the adhesion layer123a. In some embodiments, conduction layer123bmay be a material such as copper, silver, a palladium/copper alloy, or the like. The conduction layer123bmay be formed using a process such as sputtering, PVD, CVD, ALD, plating, or spraying. In some embodiments, the conduction layer123bis formed having a thickness of between about 1 μm and about 100 μm, such as about 10 μm.

In some embodiments, the EMI film121includes an additional protection layer (e.g., an SUS layer) formed over the conduction layer123bto protect the conduction layer123b. In some embodiments, the EMI film121does not include an additional protection layer formed over the conduction layer123b. For example, in some embodiments, a molding compound, encapsulant, or underfill is formed directly over the conduction layer123band protects the conduction layer123b. In embodiments such as these, an additional protection layer over the conduction layer123bmay not be needed. See, for example,FIGS.5-9in which a molding compound is formed directly over the EMI film121, discussed in greater detail below.

As the first via111bof first via layer111has an exposed sidewall119, the EMI film121may make physical contact and electrical contact to the first via111bthrough the exposed sidewall119. In this manner, the EMI film121may be electrically connected to a voltage of a first semiconductor device101at first via111b. For example, the EMI film121may be electrically connected to a reference voltage or a ground of a first semiconductor device101through first via111b. In other embodiments, the EMI film121may be connected to a first semiconductor device101through exposed sidewalls of multiple first vias or other conductive features. By electrically connecting the EMI film121to the device, the electromagnetic shielding from the EMI film121may be improved.

After deposition of the EMI film121, each first semiconductor device101may be removed from the frame115and incorporated into a package such as an Integrated Fan-Out (InFO) structure, an Integrated Fan-Out Package-on-Package (InFO-PoP) structure, or another type of package structure. The first semiconductor device101may be removed from the frame115by a suitable process such as a pick-and-place process. In some cases, the pick-and-place process may sever the portions of the EMI film121attached to the first semiconductor device101from portions of the EMI film121attached to the frame115.

However, as one of ordinary skill in the art will recognize, the above described process to form semiconductor device101is merely one such description, and is not meant to limit the embodiments to this exact process. Rather, the described process is intended to be merely illustrative, as any suitable process for forming semiconductor device101may alternatively be utilized. All suitable processes are fully intended to be included within the scope of the present embodiments.

Turning now toFIGS.2A-2C, the second semiconductor devices201are similar to the first semiconductor devices101. The second semiconductor devices201may be semiconductor devices designed for an intended purpose such as a memory die (e.g., a DRAM die), a logic die, an integrated circuit, a central processing unit (CPU) die, combinations of these, or the like. However, the first via layer211of the second semiconductor devices201does not extend into scribe region205. Additionally, first contact pads207are formed such that a first contact pad207extends into scribe region215, as shown for first contact pad207binFIG.2A. Thus, the first contact pad207bwill have an exposed sidewall219after singulation, as shown inFIG.2B. After singulation, the exposed sidewall of the first contact pad207bmay be substantially coplanar with a sidewall of the substrate103.FIG.2Cillustrates the second semiconductor devices201after a conformal EMI film221has been formed over the surfaces of the second semiconductor devices201. The EMI film221may be similar to the EMI film221described above with respect toFIG.1C. For example, the EMI film221may be formed from an adhesion layer123aand a conduction layer123b.

As the first contact pad207bhas an exposed sidewall219, the EMI film221may make physical contact and electrical contact to the first contact pad207bthrough the exposed sidewall219. In this manner, the EMI film221may be electrically connected to a voltage of a second semiconductor device201at first contact pad207b. In other embodiments, the EMI film221may be connected to a second semiconductor device201through exposed sidewalls of multiple first contact pads207. In other embodiments, the EMI film221may be connected to a second semiconductor device201through exposed sidewalls of one or more first contact pads207and through exposed sidewalls of one or more first vias (as described above with respect toFIG.1C). By electrically connecting the EMI film221to the device, the electromagnetic shielding from the EMI film221may be improved.

FIGS.3-9show the formation of some embodiments of an InFO-PoP structure350. The InFO-PoP structure350may include one or more semiconductor devices like those described above with respect toFIGS.1A-1C and2A-2C. With reference now toFIG.3, there is shown a first carrier substrate301with a second adhesive layer303, a first polymer layer305, and a first seed layer307over the first carrier substrate301. Regions350have been indicated where individual InFO-PoP structures350will be formed. The first carrier substrate301may be a silicon-based material such as glass or silicon oxide, another material such as aluminum oxide, combinations of these materials, or the like. The first carrier substrate301is planar within process variations in order to accommodate an attachment of semiconductor devices such as the first semiconductor device101, the second semiconductor device201, or one or more other semiconductor devices (not illustrated inFIG.3but illustrated and discussed below with respect toFIGS.4-9).

The second adhesive layer303is formed on the first carrier substrate301in order to assist in the adherence of overlying structures (e.g., the first polymer layer305). In some embodiments, the second adhesive layer303may comprise an ultraviolet glue, which loses its adhesive properties when exposed to ultraviolet light. However, other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, or the like, may also be used. The second adhesive layer303may be formed onto the first carrier substrate301in a semi-liquid or gel form which is readily deformable under pressure.

The first polymer layer305is placed over the second adhesive layer303and may provide protection to attached semiconductor devices. In some embodiments, the first polymer layer305may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, Solder Resistance (SR), or Ajinomoto build-up film (ABF) may alternatively be utilized. The first polymer layer305may be placed using, e.g., a spin-coating process to a thickness of between about 2 μm and about 15 μm, such as about 5 μm, although any suitable method and thickness may alternatively be used.

The first seed layer307is formed over the first polymer layer305. In some embodiments, the first seed layer307is a thin layer of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. In some embodiments, the first seed layer307is a layer of titanium about 1,000 Å thick covered by a layer of copper about 5,000 Å thick. The first seed layer307may be formed using a process such as sputtering, evaporation, a PECVD process, or another process. In some embodiments, the first seed layer307may have a thickness of between about 0.3 μm and about 1 μm, such as about 0.5 μm.

FIG.3also illustrates the formation and patterning of a photoresist309over the first seed layer307. In some embodiments, the photoresist309may be formed on the first seed layer307using a spin coating technique or another technique. In some embodiments, the photoresist309is formed to a thickness between about 50 μm and about 250 μm, such as about 120 μm. The photoresist309may be patterned by one or more suitable photolithography techniques.

In some embodiments, the pattern formed into the photoresist309is a pattern for forming vias311. The vias311may be located on different sides of subsequently attached semiconductor devices as shown inFIGS.4-9, though in other embodiments the vias311may be located in any suitable arrangement. In some embodiments, the vias311are formed within the photoresist309from one or more conductive materials, such as copper, tungsten, other conductive metals, or the like. The vias311may be formed, for example, by electroplating, electroless plating, or the like.

After the vias311have been formed, the photoresist309may be removed using a suitable removal process (not illustrated inFIG.3but seen inFIG.4below). The photoresist may be removed using a suitable removal process such as plasma ashing, wet strip or any other suitable process. The removal of the photoresist309may expose the underlying portions of the first seed layer307.

The exposed portions of the first seed layer307may be removed (not illustrated inFIG.3but seen inFIG.4below). In some embodiments, the exposed portions of the first seed layer307(e.g., those portions that are not covered by the vias311) may be removed by a wet or dry etching process, or another suitable process. After the exposed portion of the first seed layer307has been removed, a portion of the first polymer layer305is exposed between the vias311.

FIG.4illustrates a third semiconductor device401and a fourth semiconductor device403placed onto the polymer layer305. The third semiconductor device401or the fourth semiconductor device403may be a semiconductor device designed for an intended purpose such as a memory die (e.g., a DRAM die), a logic die, an integrated circuit, a central processing unit (CPU) die, combinations of these, or the like. In some embodiments, the third semiconductor device401and the fourth semiconductor device403are similar to the first semiconductor device101and/or second semiconductor device201described previously. For example, the third semiconductor device401may be covered by an EMI film405that is connected to a first via407, and the fourth semiconductor device403may be covered by an EMI film409that is connected to a first via411. The EMI film405or the EMI film409may be similar to or different from EMI film121described above. In some embodiments, one semiconductor device or more than two semiconductor devices are placed within each InFO-PoP structure. In some embodiments, one or more of the semiconductor devices may not be covered in an EMI film or may not have a first via or a contact pad connected to an EMI film. The third semiconductor device401or the fourth semiconductor device403may be attached to the polymer layer305by an adhesive layer (not shown). The adhesive layer may be formed on the third semiconductor device401and/or the fourth semiconductor device403, and the adhesive layer may be similar to the first adhesive layer117shown inFIGS.1A-2C. In some embodiments, the semiconductor devices may be placed onto the first polymer layer305using a pick-and-place process. However, any other suitable method of placing semiconductor devices may be used.

FIG.5illustrates an encapsulation and planarization of the vias311, the third semiconductor device401and the fourth semiconductor device403. A first encapsulant501may be formed over the vias311, the third semiconductor device401and the fourth semiconductor device403using any suitable method. The first encapsulant501may be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like. In some embodiments, the first encapsulant501is cured after formation.

FIG.5also illustrates a planarization of the first encapsulant501. The planarization may be performed using a mechanical grinding process, a chemical mechanical polishing (CMP) process, or another process. In some embodiments, the planarization may grind away the first encapsulant501, portions of the vias311, the top surface of EMI film405of the third semiconductor device401and portions of the third semiconductor device401, and the top surface of EMI film409of the fourth semiconductor device403and portions of the fourth semiconductor device403. The planarization exposes top surfaces of the vias311, first vias407of the third semiconductor device401, and first vias411of the fourth semiconductor device403for further processing. As such, the vias311, the third semiconductor device401, and the fourth semiconductor device403may have a planar surface that is also planar with the first encapsulant501, as shown inFIG.5. As shown inFIGS.5-9, in some embodiments the first encapsulant501covers and protects the EMI films covering the semiconductor devices.

FIG.6illustrates a formation of redistribution layers (RDL)601a-cover the vias311, the third semiconductor device401, and the fourth semiconductor device403in order to connect the vias311, the third semiconductor device401, the fourth semiconductor device403, and external connections621. For example, the RDL601a-cmay connect the vias311to the external connections621, the vias311to the third semiconductor device401and/or the fourth semiconductor device403, the external connections621to the third semiconductor device401and/or the fourth semiconductor device403, and/or the third semiconductor device401to the fourth semiconductor device403.FIG.6is an illustrative cross-sectional view of the RDL601a-c, and thus may not show all features of the RDL601a-c, as some features may not be present in the example cross-section. For example, the cross-section shown inFIG.601may not show all conductive features of the RDL601a-cand may not show all interconnections between conductive features. The RDL601a-cshown inFIGS.6-9include 3 RDL layers601a,601band601c, but in other embodiments, the RDL601a-cmay include more or fewer RDL layers. In some embodiments, the RDL601a-care formed of alternating layers of insulating material and conductive material and may be formed through any suitable process. An example insulating layer605and an example conductive material layer603are indicated inFIG.6.

A passivation layer607may be formed over the topmost RDL layer601cof RDL601a-c. In some embodiments, the passivation layer607may be a polymer such as PBO, a polyimide, a polyimide derivative, or another dielectric material. Openings may be made through the passivation layer607to expose portions of the topmost RDL layer601c. The openings in the passivation layer607allow for contact between the topmost RDL layer601cand Underbump Metallizations (UBMs)619. The openings may be formed using a suitable photolithographic mask and etching process, although any suitable process may be used.

The UBMs619may be created by forming one or more conductive layers over the passivation layer607and along the interior of the opening through the passivation layer607. The forming of each conductive layer may be performed using a plating process, such as electrochemical plating, although other processes of formation, such as sputtering, evaporation, or PECVD process. Once the desired layers have been formed, portions of the layers may then be removed through a suitable photolithographic masking and etching process to remove excess material. The external connections621are formed on the UBMs619and may provide external electrical connection points to topmost RDL layer601c. The external connections621may be, for example, contact bumps, solder bumps, or another type of connection feature.

FIG.7illustrates a debonding of the first carrier substrate301from the vias311, the third semiconductor devices401, and the fourth semiconductor devices403. In some embodiments, the external connections621may be attached to a ring structure701. The ring structure701may be a metal ring intended to provide support and stability for the structure during and after the debonding process. In some embodiments, the external connections621are attached to the ring structure701using an ultraviolet tape703, although any other suitable adhesive, tape, frame, or attachment may be used. Once the external connections621are attached to the ring structure701, the first carrier substrate301may be debonded from the first polymer layer305.FIG.7also illustrates a patterning of the first polymer layer305to form openings705and expose the first seed layers307of the vias311. In some embodiments, the first polymer layer305may be patterned using laser drilling, photolithographic techniques, or another technique.

FIG.8illustrates backside ball pads801placed within the openings705in order to protect the exposed vias311. In some embodiments, the backside ball pads801may comprise a conductive material such as solder on paste or an oxygen solder protection (OSP), although any suitable material may be used. In some embodiments, the backside ball pads801may be applied using a stencil or another technique, and then the backside ball pads801may be reflowed to form a bump shape.

FIG.8also illustrates the formation and patterning of a backside protection layer803over the backside ball pads801, effectively sealing the joint between the backside ball pads801and the vias311from moisture. In some embodiments, the backside protection layer803may be a protective material such as a PBO, Solder Resistance (SR), Lamination Compound (LC) tape, Ajinomoto build-up film (ABF), non-conductive paste (NCP), non-conductive film (NCF), patterned underfill (PUF), warpage improvement adhesive (WIA), liquid molding compound V9, combinations of these, or the like. However, any suitable material may also be used. The backside protection layer803may be applied using a process such as screen printing, lamination, spin coating, or the like. After formation, the backside protection layer803may be patterned to expose the backside ball pads801. The backside protection layer803may be patterned using laser drilling, photolithographic techniques, or other suitable techniques.

FIG.8also illustrates the backside ball pads801bonded to a first package850. In some embodiments the first package850may comprise a second substrate805, a fifth semiconductor device807, a sixth semiconductor device809(bonded to the fifth semiconductor device807), second contact pads811, second encapsulant813, and second external connections815. In some embodiments, the second substrate805may be a packaging substrate including through substrate vias817to connect the fifth semiconductor device807and the sixth semiconductor device809to the backside ball pads801. In some embodiments, the second substrate805may be an interposer, a silicon substrate, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. The second substrate805may also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide a suitable protection and/or interconnection functionality.

The a fifth semiconductor device807may be a semiconductor device designed for an intended purpose such as a memory die (e.g., a DRAM die), a logic die, a central processing unit (CPU) die, combinations of these, or the like. In some embodiments, the fifth semiconductor device807includes integrated circuit devices, such as transistors, capacitors, inductors, resistors, first metallization layers (not shown), and the like. In some embodiments, the fifth semiconductor device807is designed and manufactured to work in conjunction with or concurrently with the third semiconductor device401or the fourth semiconductor device403.

The sixth semiconductor device809may be similar to the fifth semiconductor device807. For example, the sixth semiconductor device809may be a semiconductor device designed for an intended purpose (e.g., a DRAM die) and comprising integrated circuit devices for a desired functionality. In some embodiments the sixth semiconductor device809is designed to work in conjunction with or concurrently with the third semiconductor device401or the fourth semiconductor device403.

The sixth semiconductor device809may be bonded to the fifth semiconductor device807. In some embodiments the sixth semiconductor device809is only physically bonded with the fifth semiconductor device807, such as by using an adhesive. In this embodiment the sixth semiconductor device809and the fifth semiconductor device807may be electrically connected to the second substrate805using wire bonds819, although any suitable electrical bonding may be alternatively be utilized.

Alternatively, the sixth semiconductor device809may be bonded to the fifth semiconductor device807both physically and electrically. In this embodiment the sixth semiconductor device809may comprise sixth external connections (not separately illustrated inFIG.8) that connect with seventh external connections (also not separately illustrated inFIG.8) on the fifth semiconductor device807in order to interconnect the sixth semiconductor device809with the fifth semiconductor device807.

The second contact pads811may be formed on the second substrate805to form electrical connections between the fifth semiconductor device807and the second external connections815. In some embodiments, the second contact pads811may be formed over and in electrical contact with electrical routing (such as through substrate vias817) within second substrate805.

The second encapsulant813may be used to encapsulate and protect the fifth semiconductor device807, the sixth semiconductor device809, and the second substrate805. In some embodiments, the second encapsulant813may be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like. In some embodiments, the second encapsulant813may be cured after formation.

In some embodiments, the second external connections815may be formed to provide an external connection between the second substrate805and the backside ball pads801. The second external connections815may be contact bumps such as microbumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, silver, copper, or another suitable material. After the second external connections815have been formed, the second external connections815are aligned with and placed into physical contact with the backside ball pads801, and a bonding process is performed. For example, in some embodiments in which the second external connections815are solder bumps, the bonding process may comprise a reflow process.

FIG.9illustrates InFO-PoP structure350after debonding from the ring structure701and singulation. Prior to debonding and singulation, an underfill material901may be injected or otherwise formed in the space between adjacent first packages850and in the space between first packages850and the backside protection layer803. In some embodiments, the underfill material901may be a liquid epoxy that is dispensed between first packages850and the backside protection layer803, and then cured to harden. In some embodiments, a second EMI film (not shown) may be formed over the InFO-PoP structure350.

However, as one of ordinary skill in the art will recognize, the above described process to form the InFO-PoP structure350is merely one such description, and is not meant to limit the embodiments to this exact process. Rather, the described process is intended to be merely illustrative, as any suitable process for forming and packaging semiconductor devices with EMI films such as first semiconductor device101, second semiconductor device201, third semiconductor device401, or fourth semiconductor device403may alternatively be utilized. In some embodiments, semiconductor devices with EMI films such as first semiconductor device101, second semiconductor device201, third semiconductor device401, or fourth semiconductor device403may be incorporated into an InFO structure without vias311. All suitable processes, packages, and structures are fully intended to be included within the scope of the present embodiments.

FIGS.10-14show the formation of some embodiments of an InFO structure1050. The InFO structure1050can include one or more semiconductor devices, such as example seventh semiconductor device1007and example eighth semiconductor device1009shown inFIGS.10-14. In some embodiments, one semiconductor device or more than two semiconductor devices are placed within each InFO structure1050. In some embodiments, the one or more semiconductor devices may have a first via or a contact pad with an exposed sidewall, similar to first semiconductor device101shown inFIG.1Band/or second semiconductor device201shown inFIG.2B. For example, seventh semiconductor device1007includes a first via1011having an exposed sidewall, and eighth semiconductor device1009includes a first via1013having an exposed sidewall. In some embodiments, one or more of the semiconductor devices is not covered by an EMI film prior to placement within the InFO structure1050. For example, the seventh semiconductor device1007and the eighth semiconductor device1009shown inFIG.10are not covered by an EMI film.

With reference now toFIG.10, there is shown a second carrier substrate1001with a third adhesive layer1003and a second polymer layer1005. Regions1050have been indicated where InFO structures1050will be formed. In some embodiments, the second carrier substrate1001may be similar to first carrier substrate301shown inFIGS.3-6. For example, the second carrier substrate1001may be a material such as those described for first carrier substrate301.

The third adhesive layer1003is formed on the second carrier substrate1001. In some embodiments, the third adhesive layer1003may be similar to the second adhesive layer303described previously. The second polymer layer1005is placed over the third adhesive layer1003. In some embodiments, the second polymer layer1005may be similar to the first polymer layer305described previously. In some embodiments, the seventh semiconductor device1007and the eighth semiconductor device1009may be placed onto the second polymer layer1005using a pick-and-place process. However, any other suitable method of placing semiconductor devices may be used.

FIG.11illustrates a conformal EMI film1101formed over the surfaces of the seventh semiconductor device1007, the eighth semiconductor device1009, and the second polymer layer1005. The EMI film1101may be similar to EMI film121or EMI film221described previously. For example, the EMI film1101may be formed from a conduction layer formed over an adhesion layer. In some embodiments, the EMI film1101is formed from a copper conduction layer formed over a SUS adhesion layer.

As the first via1011of the seventh semiconductor device1007and the first via1013of the eighth semiconductor device1009have exposed sidewalls, the EMI film1101may make physical contact and electrical contact to the seventh semiconductor device1007and the eighth semiconductor device1009. By electrically connecting the EMI film1101to the seventh semiconductor device1007and the eighth semiconductor device1009, the electromagnetic shielding from the EMI film1101may be improved.

FIG.12illustrates an encapsulation and planarization of the seventh semiconductor device1007and the eighth semiconductor device1009. A second encapsulant1201may be formed over the seventh semiconductor device1007and the eighth semiconductor device1009using any suitable method. The second encapsulant1201may be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like. In some embodiments, the second encapsulant1201is cured after formation.

FIG.12also illustrates a planarization of the first encapsulant501. The planarization may be performed using a mechanical grinding process, a chemical mechanical polishing (CMP) process, or another process. In some embodiments, the planarization may grind away the second encapsulant1201, the top surface of EMI film1101over the seventh semiconductor device1007and the eighth semiconductor device1009, and portions of the seventh semiconductor device1007and the eighth semiconductor device1009. The planarization exposes top surfaces of the first via1011of the seventh semiconductor device1007and the first via1013of the eighth semiconductor device1009for further processing. As such, the first via1011of the seventh semiconductor device1007and the first via1013of the eighth semiconductor device1009may have a planar surface that is also planar with the second encapsulant1201, as shown inFIG.12. As shown inFIGS.12-14, in some embodiments the second encapsulant1201covers and protects the EMI film1101.

FIG.13illustrates a formation of redistribution layers (RDL)1301a-cover the seventh semiconductor device1007and the eighth semiconductor device1009. The RDL1301a-cshown inFIGS.13-14include 3 RDL layers1301a,1301band1301c, but in other embodiments, the RDLs1301a-cmay include more or fewer RDL layers. In some embodiments, the RDL1301a-care formed of alternating layers of dielectric and conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, etc.). An example dielectric layer1305and an example conductive material layer1303are indicated inFIG.13.

A passivation layer1307may be formed over the topmost RDL layer1301cof RDL1301a-c. In some embodiments, the passivation layer1307may be a polymer such as PBO, a polyimide, a polyimide derivative, or another dielectric material. Openings may be made through the passivation layer1307to expose portions of the topmost RDL layer1301c. The openings in the passivation layer1307allow for contact between the topmost RDL layer1301cand Underbump Metallizations (UBMs)1319. The openings may be formed using a suitable photolithographic mask and etching process, although any suitable process may be used. The UBMs1319may be created by forming one or more conductive layers over the passivation layer607and along the interior of the opening through the passivation layer1307. The external connections1321are formed on the UBMs1319and may provide external electrical connection points to topmost RDL layer1301c. The external connections1321may be, for example, contact bumps, solder bumps, or another type of connection feature.

FIG.14illustrates InFO structure1050after singulation. In some embodiments, prior to singulation, the second carrier substrate1001may be debonded from the second polymer layer1005, and the external connections1321may be attached to a ring structure, similar to the embodiment shown inFIG.7. In some embodiments, the second polymer layer1005may also be removed (not shown). In some embodiments, a molding compound, encapsulant, dielectric film, semiconductor device, or package may be disposed on the InFO structure1050(not shown). In some embodiments, additional electrical connections may be made to portions of the EMI film1101.

However, as one of ordinary skill in the art will recognize, the above described process to form the InFO structure1050is merely one such description, and is not meant to limit the embodiments to this exact process. Rather, the described process is intended to be merely illustrative, as any suitable process for forming and packaging semiconductor devices such as the seventh semiconductor device1007and the eighth semiconductor device1009may alternatively be utilized. All suitable processes, packages, and structures are fully intended to be included within the scope of the present embodiments.

FIGS.15-16show the formation of an embodiment of an InFO-PoP structure1500. In some embodiments, the InFO-PoP structure1500may be similar to InFO-PoP structure350shown inFIG.9and formed by similar processes. For example, the InFO-PoP structure1500can include one or more semiconductor devices placed within InFO-PoP structure1500. The one or more semiconductor devices may be similar to the first semiconductor device101shown inFIGS.1A-1C, the second semiconductor device201shown inFIGS.2A-2C, the seventh semiconductor device1007shown inFIG.10-14, or the eighth semiconductor device1009shown inFIGS.10-14, though other semiconductor devices may be used in other embodiments. The semiconductor devices may or may not be covered by an EMI film.FIGS.15-16show an example ninth semiconductor device1503and an example tenth semiconductor device1505placed within InFO-PoP structure1500. In some embodiments, one semiconductor device or more than two semiconductor devices are placed within InFO-PoP structure1500.

The InFO-PoP structure1500includes RDL1507. In some embodiments, one or more conductive material layers of the RDL1507may be exposed at a sidewall of the InFO-PoP structure1500. An example exposed sidewall1509of a conductive material layer of the RDL1507is indicated inFIGS.15-16. The exposed surface1511of the InFO-PoP structure1500that includes exposed sidewall1509is also indicated inFIGS.15-16. The exposed surface1511may include exposed surfaces of molding compound, encapsulant, dielectric layers, conductive layers, or other materials or layers.

FIG.15also illustrates a surface preparation process1513applied to the exposed surface1511of the InFO-PoP structure1500. The surface preparation process1513includes one or more processes that may improve adhesion of a conductive layer that is subsequently formed over portions of the exposed surface1511. The conductive layer may be part of an EMI film, and an embodiment is described in greater detail below with respect toFIG.16.

In some embodiments, the surface preparation process1513includes an oxygen enrichment treatment and/or a surface roughness treatment. In some embodiments, the oxygen enrichment treatment may include exposing the exposed surface1511to an oxygen plasma process. In some embodiments, the oxygen enrichment treatment may include exposing the exposed surface1511to a solution containing hydrogen peroxide (H2O2). In some embodiments, the surface roughness treatment may include exposing the exposed surface1511to an argon plasma process. In some embodiments, the surface roughness treatment may include exposing the exposed surface1511to an etchant. The surface preparation process1513may include one or more of these or other treatments, a combination of treatments, or the like.

FIG.16illustrates an EMI film1601formed over the exposed surface1511of the InFO-PoP structure1500. In some embodiments, EMI film1601is formed from a single conformal layer of material, and in some embodiments, EMI film1601is formed from multiple conformal layers of materials. EMI film1601is formed over the InFO-PoP structure1500to shield the InFO-PoP structure1500from electromagnetic interference.

In some embodiments, EMI film1601is formed from a conductive layer1603aand a protection layer1603b. The conductive layer1603ais formed conformally over the exposed surface1511of the InFO-PoP structure1500. The conductive layer1603amay be formed using a suitable technique, for example a deposition process such as sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), spray coating, electroless plating, or the like. In some embodiments, the conductive layer1603ais a material such as copper, silver, a palladium/copper alloy, or the like. In some cases, the use of surface preparation process1513can allow the conductive layer1603ato adhere to the exposed surface1511without a need for an adhesive layer (e.g., an SUS layer or another type of adhesive layer) between the exposed surface1511and the conductive layer1603. In some embodiments, the conductive layer1603ais formed having a thickness of between about 1 μm and about 10 μm, such as about 1 μm.

The protection layer1603bis formed conformally over the conductive layer1603a. The protection layer1603bmay be a protective material such as stainless steel (SUS), although any other suitable material, such as nickel, may be used. The protection layer1603bmay be deposited by a process such as sputtering, PVD, CVD, ALD, plating, or the like, to a thickness of between about 0.1 μm and about 100 μm, such as about 10 μm.

As the RDL1507has an exposed sidewall1509, the EMI film1601may make physical contact and electrical contact to InFO-PoP structure1500through the exposed sidewall1509. In this manner, the EMI film1601may be electrically connected to a voltage within the InFO-PoP structure1500, such as a reference voltage or a ground voltage. In other embodiments, the EMI film1601may be connected to the InFO-PoP structure1500through multiple exposed sidewalls of the RDL1507. By electrically connecting the EMI film1601to the InFO-PoP structure1500, the electromagnetic shielding from the EMI film1601may be improved. Moreover, by forming the conductive layer1603adirectly over the exposed sidewall1509, the electrical connection between the InFO-PoP structure1500and the EMI film1601can have a reduced contact resistance. For example, the exposed sidewall1509connection to the conductive layer1603aas shown inFIG.16may have reduced contact resistance compared with a connection between the exposed sidewall1509and an adhesive SUS layer under a conductive layer of an EMI film.

However, as one of ordinary skill in the art will recognize, the above described process to form the EMI film1601over the InFO-PoP structure1500is merely one such description, and is not meant to limit the embodiments to this exact process. Rather, the described process is intended to be merely illustrative, as any suitable process for forming and packaging semiconductor devices such as the InFO-PoP structure1500may alternatively be utilized. All suitable processes, packages, and structures are fully intended to be included within the scope of the present embodiments.

Embodiments of the present disclosure include a semiconductor device covered by an Electromagnetic Interference (EMI) film that shields the device from electromagnetic interference. The semiconductor device may have an internal conductive layer that connects directly to the EMI film. In this manner, the EMI film may be electrically coupled to the semiconductor device, improving the shielding effect of the EMI film. Moreover, the semiconductor device may be incorporated into a package structure such as an InFO structure, an InFO-PoP structure, or another structure. In some cases, covering the semiconductor device with the EMI film eliminates the need to cover the entire package structure with an EMI film, which may reduce the amount of EMI material required, reduce cost, and simplify processing. Additionally, a semiconductor device may be covered by a molding compound or encapsulant within the package structure, in which case the EMI film covering the semiconductor device may not need a protective layer. In this manner, forming an EMI film without a protective layer may also reduce the amount of EMI material required, reduce cost, and simplify processing.

In some embodiments, an EMI film may be formed over a package structure. By performing a surface preparation structure prior to forming the EMI film, an adhesive layer of the EMI film may not be needed. Forming an EMI film without an adhesive layer may also reduce the amount of EMI material required, reduce cost, and simplify processing. Moreover, without the adhesive layer of the EMI film, the package structure may be electrically connected to the conductive layer of the EMI film, which may reduce contact resistance between the package structure and the EMI film.

According to some embodiments, a method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

According to some embodiments, a method includes forming a package, wherein forming the package includes forming an encapsulant laterally surrounding a first semiconductor device and forming a Redistribution Layer (RDL) over and electrically connected to the first semiconductor device. The method also includes performing a surface preparation process on exposed surfaces of the encapsulant and a portion of the exposed surfaces of the RDL. The method also includes forming an Electromagnetic Interference (EMI) film on an outer surface of the package, wherein the surface preparation process increases adhesion of the EMI film to the package.

According to some embodiments, a structure includes a semiconductor device including a metal layer disposed over a semiconductor substrate, wherein a sidewall of the metal layer is substantially coplanar with a sidewall of the semiconductor substrate. The structure also includes a conductive film disposed over the semiconductor device, wherein the conductive film physically contacts the sidewall of the metal layer and physically contacts the sidewall of the semiconductor substrate, and wherein the conductive film comprises an inner adhesive layer and an outer conduction layer. The structure also includes an encapsulant disposed over and physically contacting the conductive film. The structure also includes a Redistribution Layer (RDL) disposed over and physically contacting the semiconductor device and the encapsulant, wherein the RDL is electrically connected to the metal layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.