Patent ID: 12241932

DETAILED DESCRIPTION OF THE DRAWINGS

The disclosure herein is described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the subject innovation. It may be evident, however, that various disclosed aspects can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the subject innovation.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “implementation” does not require that all implementations include the discussed feature, advantage, or mode of operation.

The terminology used herein describes particular implementations only and should not be construed to limit any implementations disclosed herein. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Those skilled in the art will further understand that the terms “comprises,” “comprising,” “includes,” and/or “including,” as used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Various components as described herein may be implemented as application specific integrated circuits (ASICs), programmable gate arrays (e.g., FPGAs), firmware, hardware, software, or a combination thereof. Further, various aspects and/or embodiments may be described in terms of sequences of actions to be performed by, for example, elements of a computing device. Those skilled in the art will recognize that various actions described herein can be performed by specific circuits (e.g., an application specific integrated circuit (ASIC)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequences of actions described herein can be considered to be embodied entirely within any form of non-transitory computer-readable medium having stored thereon a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects described herein may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the aspects described herein, the corresponding form of any such aspects may be described herein as, for example, “logic configured to”, “instructions that when executed perform”, “computer instructions to” and/or other structural components configured to perform the described action.

Those of skill in the art will further appreciate that the various illustrative logical blocks, components, agents, IPs, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, processors, controllers, components, agents, IPs, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

InFIG.1, a central processing unit (CPU)100is illustrated with a set of processor cores101and a system controller processor (SCP)120that handles many of the utility and management functions of the CPU100. The CPU100may include more than the illustrated four processor cores (e.g., 50 cores, 80 cores, or 120+ cores). The processors cores101are connected to SCP120via a mesh interconnect111that forms a high-speed bus connecting each of various circuits of the CPU100to each other and connecting to other on chip resources including memory (e.g., L3 cache), PCIe interfaces, I2C bus connections off chip, other chiplets, and other resources. Specifically, the mesh interconnect111may individually connect to the security processor124, the management processor123, input/output (I/O) ports122and memory121of the SCP120. The mesh interconnect111, an I2C interface, or other connections may connect the SCP120to the JTAG ports170.

The CPU100may be configured to connect to other chiplets, such as chiplet142, chiplet144, chiplet146, and chiplet148inFIG.1, when combined on a semiconductor package10. When in operation, the CPU100, chiplet142, and chiplet144, (as well as optional chiplet146optional chiplet148, in some aspects) may connect to the mesh interconnect111and perform operating system (OS) processes as an integrated system. These connections to chiplets and ports may be via PCIe interfaces, I2C interfaces, the mesh interconnect111, various connections with the SCP120(e.g., I/O122), and other connections. The management processor123may manage power ON and power OFF processes for CPU100and may manage voltages and power distribution for the CPU100. Accordingly, even if the CPU100is not connected to a package, the CPU100may include power inputs to the management processor123to enable operation and boot of the CPU100. Likewise, at power ON, the I/O122, security processor124, and JTAG170may provide interfaces as illustrated to enable debugging, controlled boot, and other tests as will be described.

InFIG.2, the SCP120is illustrated in more detail. The input and output (I/O) connections122may be configured to connect to external systems (e.g., a baseboard management controller (BMC)), system memory, and on-board memory121. The SCP120may use the I/O connections122to interface with the base board management controller (BMC). The SCP120may perform scaling, balancing, throttling, and other control processes to manage the CPU100. In a test scenario, where the CPU100is bare silicon (i.e., not yet integrated into a multi-chip package), the SCP120may connect to a test bed220or other apparatus for testing and/or validating the SCP120, such that power inputs260are driven by the test bed220. Likewise, I/O122and JTAG170may connect to the test bed220. The bootstrap controller290may include hardware switches210which may be embodied as logic gates (e.g. OR, XOR, NOR, AND, NAND), semiconductor switches, checksum functions, and other control logic in silicon. These hardware switches210may be the first components on the CPU100to be powered-on apart from (or after) the management processor123. The hardware switches210may read efuses211which may operate as immutable ROM and/or hardware coded values. The hardware switches210may determine whether access to the JTAG ports170should be granted or denied.

The test bed220may include a mount or socket to connect the semiconductor die of the CPU100and the SCP120to a test environment and various stimuli. The semiconductor die may be attached as in a hardware-in-the-loop arrangement and each pin of the semiconductor die may be driven or monitored by the test bed220. One or more pins may correspond to power inputs260and one or more pins (e.g., four or eight) may correspond to the JTAG ports170. Likewise, the SCP120may connect directly to one or more pins that may be driven to select one or more boot modes. That is, if a first pin is driven, then patching and RMA procedures may be implemented via JTAG170and the bootstrap controller290. If a second pin is driven, the semiconductor die may enter an automatic test equipment (ATE) mode for boot processes. The ATE boot mode may be authenticated by signals transmitted at the second pin or via one or more certificates transmitted over the JTAG ports170at power ON.

Various checks, flags, or logic switches may determine early in a boot process, after power ON, which boot mode is to be implemented. These checks may be performed by flags in efuses211(e.g., one-time programmable flags) and hardware switches210. The hardware switches210may connect to JTAG ports170and receive one or more certificates on boot and the hardware switches210may read one or more pins to determine and authorize an appropriate boot mode for the bootstrap controller290. The bootstrap controller290may include firmware that includes instructions for various boot modes. For example, when in an ATE boot mode, the bootstrap controller290may execute firmware to generate additional logs, skip various hardware checks (e.g., external hardware checks), or idle to await commands from JTAG170before proceeding. This versatile firmware may be hardcoded onto ROM230or may be loaded into onboard RAM240via JTAG170to override hardcoded firmware.

The shared memory121may be on-board RAM or secured RAM which can be trusted by the bootstrap controller290after an integrity check or certificate check. Indeed, the components of the CPU100may be divided into trusted components and non-trusted components, where the trusted components may be verified by certificates, in the case of software components, or are pure hardware components. The RAM240may be loaded with executable computer instructions via the JTAG ports170which may be read from the RAM240to permit the bootstrap controller290to perform a different boot process or a reconfigurable boot process. For example, the RAM240may be loaded, after initial boot of the bootstrap controller290, with an Unified Extensible Firmware Interface (UEFI) Basic Input/Output System (BIOS) or a full operating system (e.g., embedded Linux, other small distribution OS, etc.). The initial boot of the bootstrap controller290may make the onboard RAM of the CPU100or shared memory121of the SCP120available for loading of instructions via JTAG170. This onboard RAM or shared memory121may then host the BIOS or operating system to be used for functional tests and benchmarks of the CPU100.

InFIG.3, a series of information flows are illustrated between various points in the system and device under test. A test bed310(e.g., test bed220) may be connected to a CPU350or other processor and may initiate a power ON of the CPU350. The power ON may begin with the SCP120as in power ON311. The test bed310may assert one or more pins of the SCP120or transmit one or more certificates over JTAG I/O320to have ATE asserted313as the boot mode. The ATE assertion313may be simultaneous or substantially simultaneous in time with power ON311. As shown, the JTAG I/O320may provide signals and certificates for JTAG-controlled boot315to the SCP120(e.g., based on hardware switches210). The SCP120may then enter ATE boot mode.

The firmware on the SCP120or bootstrap controller290may execute initial computer instructions in accordance with the selected ATE boot mode. That is, the SCP120or bootstrap controller290may include firmware (e.g., hardcoded ROM) that includes instructions to establish a test boot mode controlled by JTAG170. Once in an ATE boot mode, the test bed310may deliver executable code321through the JTAG I/O320and SCP120into RAM340of the SCP120. In other words, the ATE boot mode will control the SCP120to enable the loading of computer instructions into RAM340via JTAG I/O320. The RAM340may be onboard RAM located on the SCP120or CPU100or CPU350. Since the ATE test is performed on the bare silicon chip, the external components such as the base board management controller (BMC), external memory, and memory controllers may not be connected to the CPU100/350. In a disaggregated configuration, the CPU100may have processor cores and sub-processors and may have few supporting components on-chip.

The executable code321may be delivered to RAM340by the JTAG170interface and once stored may be executed by the SCP120or CPU350, as the case may be. RAM340may include SRAM, cache, and other memory onboard various circuits of the CPU100. The JTAG I/O320and related JTAG debug access ports (DAP) may provide computer instructions (e.g., binary or machine language) to perform boot functions not included in the installed firmware (e.g., a UEFI BIOS). The executed boot functions323may involve start up or power ON of components of the CPU350via the SCP120or CPU350. For example, the executable code321may operate to bring the CPU350out of reset at operation331. The executable code321may be executed in between steps of the installed firmware. To accomplish this, the ATE boot mode may enable the SCP120to halt or fork the boot process based on commands delivered from the JTAG I/O320. The test bed310may monitor the boot process via JTAG I/O320and issue halt commands and insert computer instructions into the boot process to branch functionality of the boot process. For example, the SCP120may be instructed to skip boot process steps that correspond to power ON of a BMC or memory controller or may be instructed to branch execution to a different set of instructions in RAM340.

The SCP120may also log events in the boot process through operations325such that the progression of the boot process and any errors may be monitored by the JTAG I/O320. These logged events may include circuits brought out of reset, components authenticated, transmission checks, sensor readings, and other functions of the CPU350or SCP120that have been enabled by the installed firmware or executable code321. The events may be logged in a buffer of RAM340and dumped periodically via the JTAG I/O320or via a universal asynchronous receiver/transmitter (UART) interface of the CPU350. The events may be logged in a cyclical buffer of the JTAG I/O320and read out by the test bed310periodically or in real time. These events may include errors that are not serious enough to stop function of the boot process but which may nevertheless result in undesirable behavior during normal operations. For example, the JTAG or UART interface may enable the test bed310to monitor a normal boot process of installed firmware and identify unexpected events (e.g., buffer overflows, incorrect boot flags, etc.). As noted previously, the hardware-coded boot process may be modified by the executable code321to skip steps or instructions that are not possible or could cause unpredictable behavior when executed with the CPU350operating as bare silicon without connections to other chiplets or a computing platform. The boot firmware may be configured to automatically skip steps requiring external components (outside the processor under test) and await instructions via JTAG170at various points of execution.

After the CPU350is brought out of reset and booted to enable execution of instructions, the test bed310may deliver executable code333to RAM340. The executable code333may be a BIOS or an operating system which may enable further code to be loaded to RAM340and executed. As a result, the CPU350may be provided with many normal functional execution capabilities despite being in a bare metal silicon form. For example, various functional benchmark tests may be delivered to the RAM340as executable code333for evaluation of the CPU350such as overclocking tests, thermal tests, stress tests, randomized testing, data consistency tests, boundary tests, and other quality control evaluations for the semiconductor circuits. Telemetry data (e.g., power, thermal, and error data) that is normally monitored by external platform entities (e.g., BMC) may be monitored via JTAG access to on-chip sensors.

This execution of processing functions at operation335may be monitored to log events in CPU processing at operation337. Various stimulus tests (e.g., directed and randomized signal tests)327can be executed by CPU350and the test result(s) can be written to CPU I/O360(e.g., CPU pins) or receive inputs from the CPU I/O360. The test bed310may connect to each pin of the bare metal CPU and read the signal tests to verify connectivity on the semiconductor. Likewise, voltage or current margins may be tested via stimulus and recorded by the test bed310. The logged events in CPU processing at operation337may be captured by the test bed310via JTAG, UART, a debug communication channel (DCC) or debug access port (DAP), or similar interface with the CPU350. The processing by the SCP120and the CPU350may be staged so that executable code333is sequentially delivered via JTAG I/O320and sequentially executed by the respective processor. In this manner, the functionality of the chiplet or semiconductor circuit may be driven based solely on the JTAG inputs even though the chiplet or semiconductor circuit is not integrated into a package or computing platform.

InFIG.4, a sequential execution of executable code, firmware, executable code, skip instructions, halt instructions, and similar functions are illustrated for SCP120and CPU350. The JTAG boot315is enabled and executable code421is delivered to RAM340(e.g., RAM240or memory121). The executable code421may be configured to perform a boot process, create a firmware test environment, enable overrides of processing and instruction execution on the SCP120, or a combination thereof. The SCP120may execute this boot code at execute code422which may generate logs442of events that are sent to JTAG I/O320. Executable code421may include boot code which may replace code used to bring a platform (or other chiplets) out of reset. The executable code421may extract firmware at423and execute firmware as operations424. For example, the executable code421may establish various processes running on the SCP120as a wrapper (e.g., buffered execution) or execution environment. Then, in this example, the SCP120may execute the installed firmware as operations424in such a way that the firmware can be halted/skipped via operations432from the JTAG I/O320(e.g., staged or staggered execution). Any events or errors from these executed firmware instructions during operations424may then be logged via logs444. These logs444may be stored in a buffer, as described above, and/or may be transmitted over JTAG, UART, or another interface to a receiver. After execution of executable code421, the SCP120may operate a test environment or wrapper to log events as logs444that are occurring in firmware that are not logged during normal execution of such firmware.

Additional executable code425may be transmitted via JTAG I/O320and SCP120to RAM340. This executable code425in RAM340may be accessed by the SCP120to execute code434which may perform various signal tests435on the CPU350. For example, to test various functionality of the CPU and perform ATE tests, the tests' processes may be hosted and executed on the SCP120such that the CPU is not brought out of reset. This may simplify initial boot processes. If the CPU350is brought out of reset and connected to the SCP120, then executable code437may be transmitted to RAM340and such executable code437may be accessed by CPU350to perform functional tests450. It is contemplated that further firmware may be extracted as at operation423(e.g., from ROM) and further executable code may be transmitted to RAM340from JTAG I/O320throughout an ongoing ATE testing operation. Logs442,444, and446may be received from JTAG I/O320to identify functional errors, runtime errors, system faults, and other hardware or software errors that may indicate a quality control problem with the chiplet under test.

InFIG.5, a chiplet (semiconductor die) that does not include a general processor is illustrated as ASIC500. The ASIC500may include various circuits for processing specific inputs and outputs. The ASIC500may include I/O interface510and I/O interface515with the ASIC500forming an intermediary processing circuit. For example, the ASIC500may be a memory controller or a PCIe root complex. I/O interface510may be a mesh interconnect to another chiplet and I/O interface515may be a PCIe interface to an external device. The chiplet of ASIC500may be tested with functional tests as contemplated herein even if it cannot boot as a bare metal device. The ASIC500may include a JTAG interface530which may connect to onboard addressable memory, RAM520.

The ASIC500may be connected to a test bed310via I/O interface510, I/O interface515, and JTAG interface530. The test bed310may power ON the ASIC500and trigger a built-in-test framework of the ASIC500. The test bed310may power ON the ASIC500and may stimulate the I/O interface510and I/O interface515while monitoring the RAM520for functional errors or real time errors. The JTAG interface530may load computer instructions into RAM520where the instructions may be executed by the ASIC500. For example, errors may be introduced to RAM520via JTAG interface530to monitor error recovery methods of the ASIC500. The JTAG interface530may have logging capability and a buffer as described previously. The JTAG interface530may include a JTAG DAP interface for input and output from RAM520. The tests of the ASIC500may include overclocking tests, thermal tests, stress tests, randomized testing, data consistency tests, boundary tests, and other quality control evaluations for its semiconductor circuits.

InFIG.6, a process600is illustrated for performing an ATE test on a bare silicon, non-packaged semiconductor device. At610, the non-packaged semiconductor circuit (e.g., die or chiplet) is attached to a test bed. At620, first computer instructions are loaded into a memory of the non-packaged semiconductor circuit. The computer instructions may be loaded via JTAG ports of the circuit. At630, the non-packaged semiconductor circuit may operate in a test boot mode such that the operating includes executing the first computer instructions. The JTAG ports may monitor execution of the first computer instructions and may control the non-packaged semiconductor circuit to return and load more computer instructions (at620) and execute those instructions in the test boot mode (at630). In this manner, a variety of tests or complex software may be executed in test boot mode on bare silicon circuits. In some aspects, the computer instructions may include instructions that replace or suppress portions of the test boot mode that require connections to hardware other than the non-packaged semiconductor circuit.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.