Patent ID: 12219824

DETAILED DESCRIPTION OF EMBODIMENTS

The description of the following embodiments refers to the attached drawings to illustrate specific embodiments in which the present disclosure can be implemented. The directional terms mentioned in the present disclosure, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only the direction of the attached drawings. Therefore, the directional terms used are used to describe and understand the present disclosure, rather than to limit the present disclosure. In the drawings, units with similar structures are indicated by the same reference numerals.

In the description of the present disclosure, it should be understood that the term “first”, “second” are for illustrative purposes only and are not to be construed as indicating or imposing a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature that limited by “first”, “second” may expressly or implicitly comprise at least one of the features. In the description of the present disclosure, the meaning of “plural” is two or more, unless otherwise specifically defined.

In the description of the present disclosure, it should be noted that the terms “installation”, “connection” and “coupling” should be understood in a broad sense, unless otherwise clearly specified and defined. For example, it can be a fixed connection, a detachable connection, or integrated connection; it can be a mechanical connection, an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediary, it can also be the connection between two elements or the interaction between two elements. Those ordinary skilled in the art can understand the specific meanings of the above terms in the present disclosure according to specific situations.

Technical solutions of the present disclosure will now be described in conjunction with specific embodiments.

Referring toFIG.1toFIG.2, an embodiment of the present disclosure provides a display panel, comprising:a base10; anda pixel driving circuit layer20disposed on the base10, wherein the pixel driving circuit layer20comprises a plurality of pixel driving circuits;

The pixel driving circuit layer20comprises: a first semiconductor layer100, a first insulating layer200, and a second semiconductor layer300stacked on the base10;

Wherein, the pixel driving circuit layer20comprises first grooves21located between the pixel driving circuits and opened in the first insulating layer200, and an organic spacer layer22disposed in the first grooves21.

It is understandable that, as flexible and foldable displays gradually become a main development direction in the display field, during a dynamic bending process of a display panel, threshold voltages of thin film transistors are likely to drift due to influence of a bending stress, which leads to a relative large brightness difference before and after bending the display panel. In addition, for example, in a display panel using LTPO technology, a thickness of an array substrate is large due to presence of different layers of LTPS TFT and LTPO TFT, and the LTPS TFT and/or LTPO TFT are further affected by the bending stress. In this embodiment, the first insulating layer200is provided with the first grooves21located between the pixel driving circuits, and the first organic spacer layer22is disposed in the first grooves21, so that stress generated when the display panel is bent can be concentrated and released at the first grooves21, which reduces influence of the bending stress on performance of thin film transistor devices in the pixel driving circuits, prevents threshold values of the thin film transistors from drifting, and stabilizes display brightness during the bending process of the display panel.

It should be noted that, the first grooves21are opened in the first insulating layer200. In this embodiment, a depth of the first grooves21may be less than a thickness of the first insulating layer200. That is, the first grooves21may be opened on any side of the first insulating layer200without penetrating the first insulating layer200. Apparently, the first grooves21may also penetrate the first insulating layer200to form through grooves, which is not limited herein.

In one embodiment, referring toFIGS.1to3, the display panel comprises a display area1, and the first grooves21comprise a plurality of first sub-grooves211located in the display area1and a plurality of second sub-grooves212intersected by the first sub-grooves211, the plurality of first sub-grooves211and the plurality of second sub-grooves212divide the display area1into a plurality of sub-areas11, and each of the sub-areas11is provided with at least one pixel driving circuit.

It is understandable that, the first sub-grooves211and the second sub-grooves212are arranged in different directions, and the display area is divided by the plurality of first sub-grooves211and the plurality of second sub-grooves212into the plurality of sub-areas11, and each of the sub-areas11is provided with at least one pixel driving circuit, and thus a structure that completely surrounds the pixel driving circuits on all sides is formed. When the display panel is bent along any axis, the first sub-grooves211and the second sub-grooves212can both play a good stress relief effect, thereby improving adaptability to different bending conditions of the display panel, guaranteeing stability of the performance of the thin film transistor devices in the pixel driving circuit to the greatest extend, and stabilizing the display brightness during the bending process of the display panel. It should be noted that, in the sub-areas11divided by the plurality of first sub-grooves211and the plurality of second sub-grooves212, a number of the pixel driving circuits provided in each sub-area11is not limited. In the embodiments of the present disclosure, unless otherwise specified, description is made by taking an arrangement of one pixel driving circuit in each sub-area11as an example.

In this embodiment, referring toFIGS.1to3, the display panel comprises at least one bending centerline located in the display area1, and the first sub-grooves211or the second sub-grooves212are disposed along a direction perpendicular to the bending centerline.

It is understandable that, the display panel comprises at least one bending centerline located in the display area1, that is, the display panel can be bent around the bending centerline, and during the display panel is bent, the first sub-grooves211and/or the second sub-grooves212need to play a role of stress relief. Apparently, when the first sub-grooves211or the second sub-grooves212are disposed along the direction perpendicular to the bending centerline, the first sub-grooves211or the second sub-grooves212can achieve the best stress relief effect, and an influence of the bending of the display panel on the thin film transistors in the pixel driving circuits is minimized.

Continuing, it should be noted that the display panel comprises the at least one bending centerline located in the display area1, that is, the display panel may also comprise a first bending centerline and a second bending centerline located in the display area1. When the first sub-grooves211are arranged perpendicular to the first bending centerline, the second sub-grooves212may also be arranged perpendicular to the second bending centerline, which is not limited here.

In one embodiment, referring toFIGS.1to3, the display panel further comprises a bending wire area2located on a side of the display area1, and a second insulating layer400is disposed on the second semiconductor layer300, and a first metal layer500is disposed on the second insulating layer400;

The pixel driving circuit layer20comprises second grooves23located in the bending wire area2and penetrating at least the first insulating layer200and the second insulating layer400, and a second organic spacer layer24disposed in the second grooves23.

It is understandable that, pad bending technology, as a main technical means to realize a narrow frame of the display panel, is mainly achieved by bending a part of the display panel in the bending wire area2to achieve the narrow frame. At present, large bending stress is prone to be generated in the pad bending process, which causes film structures in the bending wire area2to be easily broken or peeled; in this embodiment, the second grooves23are disposed in the bending wire area2, and the second organic spacer layer24is filled in the second grooves23, so that the bending stress generated in the pad bending process can be released at the second grooves23, which prevents the bending stress causing the film layers located in the bending wire area2to break or peel off.

In this embodiment, referring toFIGS.1to3, the display area1and the bending wire area2are arranged side by side along a first direction X, and the second organic spacer layer24is provided with a plurality of third grooves25;

In the first direction X, two adjacent third grooves25are arranged in a wave shape, and the third grooves25are filled with an inorganic spacer layer26.

It can be understood that, by opening the plurality of third grooves25in the second organic spacer layer24located in the second grooves23, and filling the inorganic spacer layer26in the third grooves25, that is, the first insulating layer200, the second insulating layer400, the second organic spacer layer24, and the inorganic spacer layer26are formed with inorganic materials and organic materials alternately stacked in a concavo-convex structure, and in the first direction X, two adjacent third grooves25may be arranged in a wave shape, which increases contact areas between film layers, and can also make the display panel better release the bending stress generated by the pad bending at the second grooves23, and prevents the bending stress causing the film layers in the bending wire area2to crack or peel off.

In this embodiment, referring toFIGS.1to3, the first metal layer500comprises a plurality of signal wires5001extending along the first direction X and located in the bending wire area2, the plurality of third grooves25are correspondingly provided under each signal wire5001, and a part of each of the signal wires5001corresponding to the third grooves25is arranged in a W shape along inner walls of each third groove25, and is located between the second organic spacer layer24and the inorganic spacer layer26.

It can be understood that, the plurality of signal wires5001extend along the first direction X and are arranged side by side along a second direction Y, and the second direction Y and the first direction X are arranged at a predetermined angle. Specifically, the first direction X is perpendicular to the second direction Y. Apparently, the plurality of third grooves25are correspondingly provided under each signal wire5001, that is, each signal wire5001is arranged above the plurality of third grooves25arranged in a wave shape, and the part of each of the signal wires5001corresponding to the third grooves25is disposed along the inner walls of each third groove25in a W shape and located between the second organic spacer layer24and the inorganic spacer layer26. By arranging the signal wires5001in a W shape, a bending resistance of the signal wires5001is improved, and contact areas between the signal wires5001and the second organic spacer layer24and the inorganic spacer layer26are increased, so that cracking or peeling of the signal wires5001can be prevented.

It should be noted that, in the second direction Y, a width of the third grooves25is greater than or equal to a width of the signal wires5001, so that each of the signal wires5001runs along the inner walls of each third groove25in a W shape and located between the second organic spacer layer24and the inorganic spacer layer26. Specifically, in the second direction Y, two groove groups are arranged side by side, each groove group comprises at least two third grooves25arranged along the first direction X, and the third grooves25in two adjacent groove groups may be arranged in a one-to-one correspondence. It can also be arranged in a staggered manner, but it is not limited here.

In one embodiment, referring toFIGS.1to3, the pixel driving circuit layer20further comprises a first planarization layer27disposed on the first metal layer500, and the first planarization layer27and the inorganic spacer layer26is an integrally formed structure.

It is understandable that, both the first planarization layer27and the inorganic spacer layer26may be inorganic insulating materials, and the first planarization layer27and the inorganic spacer layer26are formed into an integral structure, that is, the first planarization layer27and the inorganic spacer layer26can be made by a same manufacturing process. On the basis of realizing release of the bending stress caused by the pad bending, additional process is omitted and manufacturing costs is saved.

In one embodiment, referring toFIGS.1to3, each of the first grooves21penetrates the first insulating layer200and the second insulating layer400, and the first organic spacer layer22and the second organic spacer layer24is an integrally formed structure.

It is understandable that, both the first organic spacer layer22and the second organic spacer layer24may be organic insulating materials, and the first organic spacer layer22and the second organic spacer layer24are arranged to form an integrally formed structure, that is, the first organic spacer layer22and the second organic spacer layer24can be made by a same manufacturing process, and when the first groove21penetrates the first insulating layer200and the second insulating layer400, the first grooves21and the second grooves23can also be formed by a same manufacturing process, so that on the basis of ensuring that the bending stress generated by display bending and the pad bending is released, the additional process is omitted, and the manufacturing costs of the display panel is greatly reduced.

In this embodiment, referring toFIGS.1to3, an organic insulating layer28is disposed between the second insulating layer400and the first metal layer500. The organic insulating layer28, the first organic spacer layer22, and the second organic spacer layer24are integrally formed. It is understandable that the organic insulating layer28, the first organic spacer layer22, and the second organic spacer layer24can all be made of organic insulating materials, and the organic insulating layer28, the first organic spacer layer22, and the second organic spacer layer24are arranged in an integrally formed structure, that is, the organic insulating layer28, the first organic spacer layer22, and the second organic spacer layer24can be manufactured by a same process, so that on the basis of ensuring that the bending stress generated by the display bending and the pad bending is released, the additional process is omitted, and the manufacturing costs of the display panel is greatly reduced.

In one embodiment, referring toFIGS.1to3, the base10comprises a substrate12and an inorganic insulating layer13disposed on the substrate12, and the first grooves21sequentially penetrate the inorganic insulating layer13, the first insulating layer200, and the second insulating layer400, and the first organic spacer layer22is filled in the first grooves21.

It is understandable that, the first grooves21penetrate the inorganic insulating layer13, the first insulating layer200, and the second insulating layer400in sequence, that is, the first grooves21are not only disposed in the pixel driving circuit layer20, but is further extended to the inorganic insulating layer13of the substrate12, and the first organic spacer layer22is filled in the first grooves21, so that the first grooves21and the first organic spacer layer22penetrate a plurality of film layer structures to achieve a better release effect on the bending stress generated when the display panel is bent for display.

In one embodiment, referring toFIGS.1to3, the base10further comprises a buffer layer14located between the substrate12and the inorganic insulating layer13, and the second grooves23penetrate the buffer layer14, the inorganic insulating layer13, the first insulating layer200, and the second insulating layer400in sequence, and the second organic spacer layer24is filled in the second grooves23.

It can be understood that, the second grooves23sequentially penetrate the buffer layer14, the inorganic insulating layer13, the first insulating layer200, and the second insulating layer400, that is, the second grooves23are not only disposed in the pixel driving circuit layer20, but also extend to the inorganic insulating layer13and the buffer layer14on the substrate12, and the second organic spacer layer24is filled in the second grooves23, so that the second grooves23and the second organic spacer layer24penetrate a plurality of film layer structures, so as to achieve a better release effect on the bending stress generated by the display panel during the pad bending.

In one embodiment, referring toFIGS.1to3, the first metal layer500comprises scan bridge wires located on the second insulating layer400and the first organic spacer layer22, and two adjacent pixel driving circuits located in different sub-areas11are bridged by the scan bridge wires.

It can be understood that, the first metal layer500is located on a side of the first organic spacer layer22away from the substrate12, and two adjacent pixel driving circuits located in different sub-areas11are separated by the first grooves21and the first organic spacer layer22located in the first grooves21. The first metal layer500comprises the scan bridge wires located on the second insulating layer400and the first organic spacer layer22, and two adjacent pixel driving circuits located in different sub-areas11are bridged by the scan bridge wires to realize connection between the pixel driving circuits. In addition, by bridging two adjacent pixel driving circuits located in different sub-areas11, an overall bending resistance of the pixel driving circuits and the scan bridge wires is also improved.

In an embodiment, referring toFIGS.4to5, the display panel further comprises a plurality of light-emitting devices D1 arranged in an array, the pixel driving circuits are configured to drive the light-emitting devices D1 to emit light, and each of the pixel driving circuits comprises:A first initialization transistor T4 configured to input an initialization signal VI to a first node Q under control of a first scan signal Scant;A switching transistor T2 configured to input a data signal Vdata to a second node A under control of a second scan signal Scan2;A driving transistor T1 configured to drive the light-emitting device D1 to emit light under control of potentials of the first node Q and the second node A;A compensation transistor T3 connected to the driving transistor T1 through the first node Q and a third node B, and configured to compensate a threshold voltage of the driving transistor T1 under control of a third scan signal Scan3;A second initialization transistor T7 configured to input the initialization signal VI to an anode of the light-emitting device under the control of the third scan signal Scan3;A first light-emitting control transistor T5 connected to the driving transistor T1 through the second node A, and configured to turn on a current flowing from a power high potential signal line to the driving transistor T1 under control of a light-emitting control signal EM;A second light-emitting control transistor T6 connected to the driving transistor T1 through the third node B, and configured to turn on a current flowing from the driving transistor T1 to the anode C of the light-emitting device D1 under the control of the light-emitting control signal EM;A storage capacitor C1 connected to the driving transistor T1 through the first node Q, and connected to the power high potential signal line through a fourth node D, and configured to store the data signal Vdata;Wherein, the scan bridge wires are respectively bridged with the first initialization transistor T4, the switching transistor T2, the compensation transistor T3, the second initialization transistor T7, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 through vias.

It should be noted that, as shown inFIG.5, which is a timing diagram of the pixel driving circuit of the present disclosure in a display phase, in this embodiment, the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 are N-type transistors; the switching transistor T2, the driving transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are P-type transistors.

In a reset phase t1, the second scan signal Scan2 is at a high potential, the switching transistor T2 is turned off; the third scan signal Scan3 is at a low potential, the compensation transistor T3 and the second initialization transistor T7 are turned off; the light-emitting control signal EM is at a high potential, the light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off; and the first scan signal Scant is at a high potential, and the first initialization transistor T4 is turned on, and an initialization signal is input to the first node Q to pull down a potential of the first node Q.

In a data writing phase t2, the first scan signal Scant is at a low potential, the first initialization transistor T4 is turned off; the second scan signal Scan2 is at a low potential, the switching transistor T2 is turned on; and the third scan signal Scan3 is at a high potential, the compensation transistor T3 and the second initialization transistor T7 are turned on. Since the potential of the first node Q is low, a gate and a second electrode of the driving transistor T1 are short circuit after the compensation transistor T3 is turned on. A voltage difference is generated between the gate and a first electrode of the driving transistor T1 through a threshold voltage of the driving transistor T1. At this time, the driving transistor T1 is turned on, and the switching transistor T2 inputs the data signal Vdata to the second node A. The data signal Vdata comprises a compensated threshold voltage and is input to the gate of the driving transistor T1, and thus threshold voltage deviation of the driving transistor T1 is compensated. The written data signal Vdata charges the first node Q through the driving transistor T1 until the voltage of the first node Q becomes Vdata-Vth, and the driving transistor T1 is turned off. In addition, since the second initialization transistor T7 is turned on, the anode of the light-emitting device D1 receives the initialization signal and is reset.

In a light-emitting phase t3, the light-emitting control signal EM is at a low level, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the currents flowing from the power high potential signal line VDD to the driving transistor T1 and flowing from the driving transistor T1 to the anode C of the light-emitting device D1 are turned on, and a driving current flowing through the light-emitting device D1 at this time satisfies the formula I=1/2K[Vdd−(Vdata−Vth)−Vth]2=1/2K[Vdd−Vdata]2. The light-emitting device D1 operates and emits light under action of the driving current I.

It can be understood that, in each of the pixel driving circuits, the driving transistor T1 is configured to drive the light-emitting device D1 to emit light under the control of the potentials of the first node Q and the second node A. The first initialization transistor T4, the switching transistor T2, the compensation transistor T3, the second initialization transistor T7, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are bridged by the vias, so as to achieve a circuit connection between two adjacent pixel driving circuits located in different sub-areas11.

In an embodiment, please referring toFIG.1. The first insulating layer200comprises a first insulating sub-layer210disposed on the first semiconductor layer100, a second insulating sub-layer220disposed on the first insulating sub-layer210, and a third insulating sub-layer230disposed on the second insulating sub-layer220. The second insulating layer400comprises a fourth insulating sub-layer410disposed on the second semiconductor layer300and a fifth insulating sub-layer420disposed on the fourth insulating sub-layer410;

The pixel driving circuit comprises a second metal layer600disposed between the first insulating sub-layer210and the second insulating sub-layer220, a third metal layer700disposed between the second insulating sub-layer220and the third insulating sub-layer230, and a fourth metal layer800disposed between the fourth insulating sub-layer410and the fifth insulating sub-layer420.

It should be noted that, please referring toFIG.1, which is a schematic diagram of a cross-sectional structure of each film layer in the display panel provided by the embodiment of the present disclosure, the display panel comprises the substrate12, the first semiconductor layer100, the second metal layer600, the third metal layer700, the second semiconductor layer300, the fourth metal layer800, and the first metal layer500stacked from bottom to top; wherein, the first semiconductor layer100forms a polysilicon active layer of each low-temperature polysilicon transistor, and the second semiconductor layer300forms an oxide active layer of each oxide transistor. In addition, the display panel also comprises a fifth metal layer900, a second planarization layer1000, an anode layer1100, a pixel definition layer1200, an organic light emitting layer1300, and a spacer layer1400stacked from bottom to top on the first planarization layer27.

InFIG.1, a transistor on a left side is a film layer structure of a low-temperature polysilicon transistor, and a transistor on a right side is a film layer structure of an oxide transistor. In each of the pixel driving circuits, structures of the switching transistor T2, the driving transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are same as a structure of the transistor on the left side ofFIG.1. Structures of the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 are same with a structure of the transistor on the right side ofFIG.1.FIG.6is a schematic diagram of a planar superimposed structure of each film layer in the display panel provided by the embodiment of the present disclosure, andFIG.7toFIG.12are schematic planar diagrams of each film layer, respectively.

It can be understood that, when the first insulating layer200comprises the first insulating sub-layer210disposed on the first semiconductor layer100, the second insulating sub-layer220disposed on the first insulating sub-layer210, and the third insulating sub-layer230disposed on the second insulating sub-layer220, and the first grooves21are opened in the first insulating layer200, that is, the first grooves21may be arranged to penetrate at least one of the first insulating sub-layer210, the second insulating sub-layer220, and the third insulating sub-layer230. In addition, the second insulating layer400comprises the fourth insulating sub-layer410disposed on the second semiconductor layer and the fifth insulating sub-layer420disposed on the fourth insulating sub-layer410. In this embodiment, in order to achieve a better release effect on the bending stress generated when the display panel is bent for display, the first grooves21are arranged to penetrate at least the first insulating sub-layer210, the second insulating sub-layer220, the third insulating sub-layer230, the fourth insulating sub-layer410, and the fifth insulating sub-layer420in order, so as to separate the pixel driving circuits in different sub-areas11, and the two adjacent pixel drive circuits located in different sub-areas11need to be bridged by the scan bridge wires. The film layer structure of each transistor in the pixel driving circuit and how to bridge the structure will be specifically described below in conjunction with specific embodiments.

Referring toFIG.1, the substrate12may comprise a rigid substrate or a flexible substrate. When the substrate12is a rigid substrate, materials may be metal or glass. When the substrate12is a flexible substrate, the materials may comprise at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy-based resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, or polyamide-based resin. In this embodiment, the substrate12is the flexible substrate.

Referring toFIGS.6-7, the first semiconductor layer100is patterned to form the polysilicon active layers of the switching transistor T2, the driving transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6, and the polysilicon active layers of the transistors are connected to each other. The polysilicon active layer can be formed by crystallizing amorphous silicon. The crystallization method may comprise rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC) and sequential lateral solidification (SLS), etc.

In one embodiment, referring toFIGS.6,8,13,14, and15, the second metal layer600is patterned to form a gate of the switching transistor T2, a gate of the first light-emitting control transistor T5, a gate of the second light-emitting control transistor T6, the gate of the driving transistor T1, a first scan signal line601connected to the gate of the switching transistor T2, a second scan signal line602connected to the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6, and a first plate603of the storage capacitor C1, and the gate of the driving transistor T1 is connected to the first plate603of the storage capacitor C1;

The scan bridge wires comprise a first bridge wire501and a second bridge wire502, and the pixel driving circuit layer20comprises a first via001and a second via002penetrating the second insulating sub-layer220, the third insulating sub-layer230, the fourth insulating sub-layer410, and the fifth insulating sub-layer420, and the first bridge wire501is connected to the first scan signal line601through the first via001, and the second bridge wire502is connected to the second scan signal line602through the second via002.

It can be understood that, the second metal layer600is formed on the first insulating sub-layer210, and the second metal layer600is formed with the first scan signal line601connecting the gate of the switching transistor T2, and the second scan signal line602connecting the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6. The first bridge wire501is connected to the first scan signal line601through the first via001, and the second bridge wire502is connected to the second scan signal line602through the second via002to realize layer change connection of the first scan signal line601and the second scan signal line602, wherein the first scan signal lines601in the two adjacent pixel driving circuits located in different sub-areas11are connected by the first bridge wire501, that is, each end of the first bridge wire501is connected to the first scan signal line601in one of the pixel driving circuits. Similarly, each end of the second bridge wire502is connected to the second scan signal line602in one of the pixel driving circuits, which will not be repeated here. In this embodiment, materials of the second metal layer600may comprise at least one metal of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), or tungsten (W).

It should be noted that, referring toFIGS.6to12, projections of the first scan signal line601and the polysilicon active layer on the substrate12have an intersection area, and a portion of the first scan signal line601located in the intersection area forms the gate of the switching transistor T2, and a portion of the polysilicon active layer in the intersection area forms a channel region of the switching transistor T2. The second scan signal line602is a light-emitting control signal line, projections of the second scan signal line602and the polysilicon active layer on the substrate12have an intersection area, a portion of the second scan signal line602located in the intersection area respectively forms the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6, and portions of the polysilicon active layer located in the intersecting area respectively form a channel region of the first light-emitting control transistor T5 and a channel region of the second light-emitting control transistor T6. Projections of the first plate603of the storage capacitor and the polysilicon active layer on the substrate12also have an intersection area, a portion of the first plate603of the storage capacitor located in the intersection area forms the gate of the driving transistor T1, and a portion of the polysilicon active layer located in the intersection area forms a channel region of the driving transistor T1. Wherein, parts of the polysilicon active layer except for the above-mentioned channel regions is ion-doped to form a source region and a drain region of each low-temperature polysilicon transistor. Through the ion doping and intersecting arrangement of the first scan signal line, a second electrode of the switching transistor T2, a second electrode of the first light-emitting control transistor T5, and the first electrode of the driving transistor T1 are connected, and the second electrode of the driving transistor T1 and a first electrode of the second light-emitting control transistor T6 are connected.

It is should be noted that, referring toFIG.13, the first via001and the second via002may be disposed in the sub-area11and located on peripheral side of the sub-area11, so as to prevent positions of the first via001and the second via002from overlapping positions of the pixel driving circuits to increase wiring complexity. In addition, along an extension direction of the first scan signal line601, when at least two pixel driving circuits are disposed in one of the sub-areas11, the first scan signal line601in each pixel driving circuit can be connected in a same layer. Similarly, a connection principle of a connection structure of the second scan signal lines602is the same as that of the first scan signal lines601, and will not be repeated here.

In one embodiment, referring toFIG.6,FIG.9,FIG.16,FIG.17,FIG.18, andFIG.19, the third metal layer700is patterned to form a bottom gate of the first initialization transistor T4, a bottom gate of the compensation transistor T3, a bottom gate of the second initialization transistor T7, a sixth scan signal line701connected to the bottom gate of the first initialization transistor T4, a seventh scan signal line702connected to the bottom gate of the compensation transistor T3, an eighth scan signal line703connected to the bottom gate of the second initialization transistor T7, and a second plate704of the storage capacitor C1. In addition, the third metal layer700is also patterned and formed with an eleventh scan signal line705, and the eleventh scan signal line705is the initialization signal line VI. It should be noted that an upmost eleventh scan signal line705inFIG.9is a scan signal line of the pixel driving circuit corresponding to a previous light-emitting device, a bottom eleventh scan signal line705is a scan signal line in the pixel driving circuit corresponding to a next light-emitting device.

The scan bridge wires comprise a sixth bridge wire506, a seventh bridge wire507, and an eighth bridge wire508. The pixel driving circuit layer20comprises a sixth via006, a seventh via007, and an eighth via008penetrating the third insulating sub-layer230, the fourth insulating sub-layer410, and the fifth insulating sub-layer420, the sixth bridge wire506is connected to the sixth scan signal line701through the sixth via006, the seventh bridge wire507is connected to the seventh scan signal line702through the seventh via007, and the eighth bridge wire508is connected to the eighth scan signal line703through the eighth via008.

It can be understood that the third metal layer700is disposed on the second insulating sub-layer220, and the third metal layer700is patterned to form the bottom gate of the first initialization transistor T4, the bottom gate of the compensation transistor T3, the bottom gate of the second initialization transistor T7, the sixth scan signal line701connected to the bottom gate of the first initialization transistor T4, the seventh scan signal line702connected to the bottom gate of the compensation transistor T3, and the eighth scan signal line703connected to the bottom gate of the second initialization transistor T7. The sixth bridge wire506is connected to the sixth scan signal line701through the sixth via006, the seventh bridge wire507is connected to the seventh scan signal line702through the seventh via007, and the eighth bridge wire508is connected to the eighth scan signal line703through the eighth via008to realize layer change connection of the sixth scan signal line701, the seventh scan signal line702, and the eighth scan signal line703. Wherein, the sixth scan signal lines701in the two adjacent pixel driving circuits located in different sub-areas11are connected by the sixth bridge wire506, that is, each end of the sixth bridge wire506are connected to the sixth scan signal line701in one of the pixel driving circuits. Similarly, each end of the seventh bridge wire507is connected to the seventh scan signal line702in one of the pixel driving circuits, and each end of the eighth bridge wire508is connected to the eighth scan signal line703in one of the pixel driving circuits, which will not be repeated here. In this embodiment, materials of the fourth metal layer800may comprise at least one metal of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (T1), tantalum (Ta), or tungsten (W).

It is should be noted that, referring toFIG.16, the sixth via006, the seventh via007, and the eighth via008may be disposed in the sub-area11and located on the peripheral side of the sub-area11, which prevents positions of the sixth via006, the seventh via007, and the eighth via008from overlapping with the positions of the pixel driving_circuits to increase the wire complexity. In addition, along an extension direction of the sixth scan signal line701, when at least two pixel driving circuits are disposed in one of the sub-areas11, the sixth scan signal lines701in each of the pixel driving circuits can be connected in a same layer. Similarly, a connection principle of connection structures of the seventh scan signal line702and the eighth scan signal line703is the same as the connection principle of the sixth scan signal line701, which will not be repeated here.

In this embodiment, referring toFIGS.6,10,20,21, and22, the second semiconductor layer300forms an active layer of the first initialization transistor T4 and an active layer of the second initialization transistor T7;

The scan bridge wires comprise a ninth bridge wire509and a tenth bridge wire510, and the pixel driving circuit layer20comprises a ninth via009and a tenth via010penetrating the fourth insulating sub-layer410and the fifth insulating sub-layer420. The ninth bridge wire509is connected to the active layer of the first initialization transistor T4 through the ninth via009, and the tenth bridge wire510is connected to the active layer of the second initialization transistor T7 through The tenth via010.

It is understandable that, the second semiconductor layer300is disposed on the third insulating sub-layer230, and is patterned to form the active layer of the first initialization transistor T4 and the active layer of the second initialization transistor T7. The ninth bridge wire509is connected to the active layer of the first initialization transistor T4 through the ninth via009, and the tenth bridge wire510is connected to the active layer of the first initialization transistor T4 through the tenth via010. Wherein, a portion of the active layer of the first initialization transistor T4 connected to the ninth bridge wire509undergoes a conductive process, and a portion of the active layer of the second initialization transistor T7 connected to the tenth bridge wire510undergoes the conductive process to ensure that there is a better connection and conduction effect between the active layer of the first initialization transistor T4 and the ninth bridge wire509, and between the active layer of the second initialization transistor T7 and the tenth bridge wire510.

It should be noted that, the second semiconductor layer300is formed on the third insulating sub-layer230, and the active layers of the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 formed by patterning are oxide active layers. Wherein, the oxide active layers of the compensation transistor T3 and the first initialization transistor T4 are connected to each other, and the oxide active layer of the second initialization transistor T7 is independent of other transistors. Materials of the oxide active layers may comprise at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), or indium oxide zinc tin (IZTO).

In one embodiment, referring toFIG.6,FIG.11,FIG.23,FIG.24,FIG.25, andFIG.26, the fourth metal layer800is patterned to form a top gate of the first initialization transistor T4, and a top gate of the compensation transistor T3, a top gate of the second initialization transistor T7, a third scan signal line801connected to the top gate of the first initialization transistor T4, a fourth scan signal line802connected to the top gate of the compensation transistor T3, and a fifth scan signal line803connected to the top gate of the second initialization transistor T7;

The scan bridge wires comprise a third bridge wire503, a fourth bridge wire504, and a fifth bridge wire505. The pixel driving circuit layer20comprises a third via003, a fourth via004, and a fifth via005penetrating the fourth insulating sub-layer410and the fifth insulating sub-layer420. The third bridge wire503is connected to the third scan signal line801through the third via003, the fourth bridge wire504is connected to the fourth scan signal line802through the fourth via004, and the fifth bridge wire505is connected to the fifth scan signal line803through the fifth via005.

It can be understood that, the fourth metal layer800is formed on the fourth insulating sub-layer410, and the fourth metal layer800is patterned to form the third scan signal line801connected to the top gate of the first initialization transistor T4, the fourth scan signal line802connected to the top gate of the compensation transistor T3, and the fifth scan signal line803connected to the top gate of the second initialization transistor T7. The third bridge wire503is connected to the third scan signal line801through the third via003, the fourth bridge wire504is connected to the fourth scan signal line802through the fourth via004, and the fifth bridge wire505is connected to the fifth scan signal line803through the fifth via005to realize layer change connection of the third scan signal line801, the fourth scan signal line802, and the fifth scan signal line803. Wherein, the third scan signal lines801in the two adjacent pixel driving circuits located in different sub-areas11are connected by the third bridge wire503, that is, each end of the third bridge wire503is connected to the third scan signal line801in one of the pixel driving circuits. Similarly, each end of the fourth bridge wire504is connected to the fourth scan signal line802in one of the pixel driving circuits, and each end of the fifth bridge wire505is connected to the fifth scan signal line803in one of the pixel driving circuits, which will not be repeated here. In this embodiment, materials of the fourth metal layer800may comprise at least one metal of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), or tungsten (W).

It should be noted that, referring toFIGS.6and11, projections of the third scan signal line801and the oxide active layer on the substrate12have an intersection area, and a portion of the third scan signal line801in the intersection area forms the top gate of the first initialization transistor T4, and a portion of the oxide active layer in the intersecting area forms a channel region of the first initialization transistor T4. Projections of the fourth scan signal line802and the oxide active layer on the substrate12have is an intersection area, a portion of the fourth scan signal line802located in the intersection area forms the top gate of the compensation transistor T3, and a portion of the oxide active layer located in the intersection area forms a channel region of the compensation transistor T3. Projections of the fifth scan signal line803and the oxide active layer on the substrate12also have an intersection area, a portion of the fifth scan signal line803located in the intersection area forms the top gate of the second initialization transistor T7, and a portion of the oxide active layer located at the intersection area forms a channel region of the second initialization transistor T7.

Parts of the oxide active layer excluding the above-mentioned channel regions forms source and drain regions of each oxide transistor. Through an arrangement of the third bridge wire503, the fourth bridge wire504, the fifth bridge wire505, the third scan signal line801, the fourth scan signal line802, and the fifth scan signal line803, connections between the second electrode of the compensation transistor T3 and the second electrode of the first initialization transistor T4, and between the first electrode of the first initialization transistor T4 and the first electrode of the second initialization transistor T7 are achieved.

It should be noted that, the third via003, the fourth via004, and the fifth via005may be arranged in the sub-area11and located on the peripheral side of the sub-area11, so as to prevent positions of the third via003, the fourth via004, and the fifth via005from overlapping the positions of the pixel driving circuits to increase the wire complexity. In addition, along an extension direction of the third scan signal line801, when at least two pixel driving circuits are disposed in one of the sub-areas11, the third scan signal line801in each of the pixel driving circuits may be connected in a same layer. Similarly, a connection principle of connection structures of the fourth scan signal line802and the fifth scan signal line803is the same as a connection principle of the third scan signal lines801, which will not be repeated here.

In one embodiment, referring toFIG.6toFIG.12, the first metal layer500is further patterned to form a data signal line520, a power high-potential signal line530, a first connection line540, a second connection line550, a third connection line560, a fourth connection line570, and a fifth connection line580. Materials of a first source-drain layer800comprises at least one element or alloy of Mo, Al, Cu, T1, or the like.

The data signal line520is connected to the polysilicon active layer of the switching transistor T2 through an eleventh via011; the power high-potential signal line530is connected to the polysilicon active layer of the first light-emitting control signal line T5 through an twelfth via012, and is connected to the first plate603of the storage capacitor C1 through an thirteenth via013which needs to penetrate a capacitor via7041formed in the second plate704of the storage capacitor; the first connection line540is connected to the oxide active layer of the first initialization transistor T4 through a fourteenth via014to form the first electrode of the first initialization transistor T4, and is then connected to the initialization signal line VI through a fifteenth via015; the second connection line550is connected to the gate of the driving transistor T1 and the second plate704of the storage capacitor C1 through a sixteenth via016, and is connected to the oxide active layer of the first initialization transistor T4 through a seventeenth via017to form the second electrode of the first initialization transistor T4; the third connection line560is connected to the polysilicon active layer of the driving transistor T1 and the second light-emitting control transistor T6 through an eighteenth via018to form the second electrode of the driving transistor T1 and the first electrode of the second light-emitting control transistor, and is connected to the oxide active layer of the compensation transistor T3 through a nineteenth via019to form the second electrode of the compensation transistor T3; the fourth connection line570is connected to the polysilicon active layer of the second light emitting control transistor T6 through a twentieth via020to form the second electrode of the second light-emitting control transistor T6, and is connected to the oxide active layer of the second initialization transistor T7 through a twenty-first via021to form the second electrode of the second initialization transistor T7; and the fifth connection line580is connected to the oxide active layer of the second initialization transistor T7 through a twenty-second via022to form the first electrode of the second initialization transistor T7, and then is connected to the initialization signal line VI through a twenty-third via023. In addition, the power high-potential signal line530is connected to the fifth metal layer900through a twenty-fourth via024. The fifth metal layer900is also patterned to form a blocking member (not shown in the figure). The blocking member forms a second drain of the second light-emitting control transistor T6, is connected to the second electrode of the second light-emitting control transistor T6 through a twenty-fifth via025, and is connected to the anode of the light-emitting device D1 through a twenty-sixth via026.

It should be noted that, on the basis of the above structure, the ninth bridge wire509can be connected to the first electrode of the first initialization transistor T4 to achieve a connection with the oxide active layer of the first initialization transistor T4. The tenth bridge wire510can be connected to the first electrode of the second initialization transistor T7 to realize connection with the active layer of the second initialization transistor T7.

In summary, in the display panel provided by the present disclosure, the first insulating layer200is provided with the first grooves21located between the pixel driving circuits, and the first organic spacer layer22is disposed in the first grooves21. Therefore, the stress generated when the display panel is bent can be concentrated and released at the first grooves21, which reduces the influence of the bending stress on the performance of the thin film transistor devices, prevents the threshold voltage drift of the thin film transistors, and stabilizes the display brightness of the display panel during the bending process.

In summary, although preferred embodiments have been described above in the present disclosure, the above-mentioned preferred embodiments are not intended to limit the present disclosure. Those of ordinary skilled in the art can make various modifications and changes without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure is subject to the scope defined by the claims.