Patent ID: 12232248

EXAMPLE EMBODIMENT

Example embodiments of the sample holder and the superconducting quantum computer according to the present disclosure will be described below in detail with reference to the drawings. However, the drawings schematically show the configuration in the example embodiments of the present disclosure. The example embodiments of the present disclosure described below are examples, and can be appropriately changed within the scope of the same essence. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. In the following drawings, elements and the like that are not used for description are appropriately omitted. In the following description, the ground may be referred to as GND. For example, the front-surface ground is referred to as front-surface GND. For example, the back-surface ground is referred to as back-surface GND.

In order to make the effect of the sample holder according to each example embodiment clearer, a result of modeling and simulating of the sample holder in which a cavity is formed in the base immediately below the chip is compared with a result of modeling and simulating of the sample holder according to each example embodiment. Therefore, before the detailed description of the example embodiments, first, the problem of chip mode in the superconducting quantum circuit will be described in more detail. Then, the result of modeling and simulating of the sample holder to be compared with the sample holder according to each example embodiment will be described. In the sample holder to be compared, a PCB is placed on a metal base. This sample holder is provided with a through hole near the center of the PCB. In this sample holder, a part of a metal base immediately below the chip is hollowed out to form a cavity immediately below the chip.

In the drawings, in order to make the orientation clear, description will be made using an x axis, a y axis, and a z axis as a three-dimensional coordinate system.

FIG.1Ais an explanatory diagram showing an example of a sample holder that holds a chip on which a superconducting quantum circuit is formed.FIG.1Bis a side view of a sample holder101shown inFIG.1A. As shown inFIG.1A, the sample holder101has the configuration in which a PCB103is placed on a metal base102. InFIG.1A, the shape of the base102is a rectangular parallelepiped or a cube. A through hole104penetrating the PCB103is provided near the center of the PCB103.

An example of the PCB103is shown inFIGS.2A to2E.FIG.2Ais a top view of the PCB103.FIG.2Bis a bottom view of the PCB103.FIG.2Cis a side view of the PCB103.FIG.2Dis a perspective view of the PCB103.FIG.2Eis an enlarged view of the PCB103near the through hole104.

As shown inFIGS.2A to2E, the PCB103has a structure in which, for example, a front-surface GND109and a core wire110of a coplanar waveguide are formed on one surface of a plate-like dielectric108extending in parallel to the xy plane, and a back-surface GND111is formed on the other surface of the dielectric108. The core wire110, the front-surface GND109, and the back-surface GND111are conductors, for example, metals. Here, the coplanar waveguide is a waveguide that includes a central conductor and two GND planes arranged on both side surfaces of the central conductor with a gap interposed between the central conductor and the two GND planes on the xy plane, and has a structure where the central conductor and the two GND planes are arranged on substantially the same plane. The two GND planes of the coplanar waveguide shown inFIGS.2A and2Eare formed by the front-surface GND109. In the PCB103shown inFIGS.2A to2E, the core wire110corresponds to the central conductor. In the PCB103shown inFIGS.2A to2E, the coplanar waveguide is formed by forming the front-surface GND109on both side surfaces of the core wire110with a gap on the xy plane. In the example shown inFIGS.2A to2E, eight coplanar waveguides are formed on the PCB103. As shown inFIG.2D, the PCB103is provided with a plurality of through holes112. These through holes112penetrate the dielectric108and electrically connect the front-surface GND109and the back-surface GND111. For example, the through hole112is produced by forming a hole that penetrates the dielectric108, the front-surface GND109, and the back-surface GND111and then plating the inside of the hole with metal. InFIGS.1A and1B, the back-surface GND111of the PCB103is in contact with the base102. Therefore, the metal base102, the back-surface GND111of the PCB103, the through hole112of the PCB103, and the front-surface GND109of the PCB103are electrically connected. The through hole104provided near the center of the PCB103has, for example, the same shape as the that of the chip of the superconducting quantum circuit mounted on the sample holder101, that is, a rectangular or square shape. In order to allow the chip to enter the inside of the through hole104, the area of the through hole104is larger than the area of the chip.

Next,FIGS.3A and3Bshow the configuration in a case where a chip107of the superconducting quantum circuit is mounted on the sample holder101shown inFIGS.1A and1B.FIG.3Ais a perspective view showing the configuration in a case where the chip107of a superconducting quantum circuit is mounted on the sample holder101shown inFIGS.1A and1B.FIG.3Bis an end view in which the configuration in a case where the chip107of a superconducting quantum circuit is mounted on the sample holder101shown inFIGS.1A and1Bis cut with a plane parallel to the xz plane including the cutting line A-AA shown inFIG.3A. InFIGS.3A and3B, the PCB103shown inFIGS.2A to2Eis used. As shown inFIGS.3A and3B, the chip107is placed inside the through hole104of the PCB103, the chip107is placed on the base102, the pad of the chip107and the core wire110of the PCB103are electrically connected by a bonding wire113such as aluminum (Al), and the GND plane of the chip107and the front-surface GND109of the PCB are electrically connected by the bonding wire113such as Al. Here, the pad of the chip107is a signal input/output terminal formed on the chip107. In the example shown inFIGS.3A and3B, the back surface of the chip107is in contact with the metal base102. InFIG.3B, the back surface of the chip107is lower surface of the chip107.

In a case where the chip107is mounted on the sample holder101shown inFIGS.1A and1B, resonance occurs when a signal of a specific frequency is input to the chip107. In order to identify the cause of the resonance in the chip mode, simulation is performed using electromagnetic field analysis software. Here, simulation is performed using ANSYS® HFSS developed by Ansys Japan Inc. Simulation is performed using the same tool in the simulation hereinafter.

The chip is shown inFIGS.4A and4B.FIG.4Ais a top view of the chip107used in simulation.FIG.4Bis an enlarged view of a first coplanar waveguide71near the tip end. As shown inFIG.4A, the chip107has a rectangular or square shape, and the lengths of the sides of the chip107are v and w. In the following description, the simulation assumes that the shape of the chip107is square, and the length of each side of the chip107is v=w=5 [mm] (millimeters). In the chip107used in the simulation, a metal film having a thickness of 200 [nm] (nanometers) is laminated on a silicon substrate having a thickness of 380 [μm] (micrometers), and a predetermined part of the metal film is removed, whereby a circuit pattern is formed. In the chip107shown inFIGS.4A and4B, the first coplanar waveguide71and a second coplanar waveguide72are formed. The first coplanar waveguide71and the second coplanar waveguide72have the same shape. The characteristic impedance of the first coplanar waveguide71and the second coplanar waveguide72is designed to 50[Ω] (ohms) and the length is 1 [mm].FIG.4Bshows the enlarged view of the first coplanar waveguide71near the tip end. As shown inFIG.4B, the tip end of the first coplanar waveguide71is not in contact with a GND plane73. As shown inFIG.4A, the first coplanar waveguide71and the second coplanar waveguide72are not connected. Similarly, the tip end of the second coplanar waveguide72is also not in contact with the GND plane73. One end of a first core wire74is connected to a first pad76, and one end of a second core wire75is connected to a second pad77.

FIGS.5A and5Bshow an example in which the chip107shown inFIGS.4A and4Bis mounted on the sample holder101shown inFIGS.1A and1B.FIG.5Ais a perspective view showing an example in which the chip107shown inFIGS.4A and4Bis mounted on the sample holder101shown inFIGS.1A and1B.FIG.5Bis an enlarged view near the chip107. As shown inFIGS.5A and5B, the first pad76of the chip107is electrically connected to a first core wire110aof the PCB103by the bonding wire113of Al. The second pad77of the chip107is electrically connected to a second core wire110bof the PCB103by the bonding wire113of Al, and the GND plane73of the chip107is electrically connected to the front-surface GND109of the PCB103by the bonding wire113of Al. As shown inFIG.5A, the other end of the first core wire110aof the PCB103than the end connected to the first pad76of the chip107is defined as Port 1. On the other hand, the other end of the second core wire110bof the PCB103than the end connected to the second pad77of the chip107is defined as Port 2. In the simulation, reflection to Port 1 and transmission to Port 2 when a high-frequency signal is input from Port 1, for example, are calculated. Here, reflection to Port 1 is denoted by S11, and transmission to Port 2 is denoted by S21.

FIGS.6A and6Bshow simulation results when a high-frequency signal is input from Port 1 shown inFIG.5A.FIG.6Ais an explanatory diagram showing reflection (S11) to Port 1 when a high-frequency signal is input from Port 1 shown inFIG.5A.FIG.6Bis an explanatory diagram showing transmission (S21) to Port 1 when a high-frequency signal is input from Port 1 shown inFIG.5A. InFIGS.6A and6B, the horizontal axis represents the frequency (unit: [GHz] (gigahertz)). S11and S21on the vertical axis are indicated in decibels ([dB]). That is, S11and S21on the vertical axis are indicated in logarithm. In the following description of the simulation results, the horizontal axis represents the frequency (unit: [GHz]), and S11or S21on the vertical axis are indicated in decibels ([dB]).

As shown inFIG.6AandFIG.6B, when signals of several specific frequencies are input, S21becomes very large, and S11becomes very small. As shown inFIGS.4A and4B, the first coplanar waveguide71and the second coplanar waveguide72of the chip107are not connected. Therefore, even if a signal is input to Port 1, it is expected that the signal will not be transmitted to Port 2. However, as shown by the simulation result ofFIG.6B, when signals of several specific frequencies are input from Port 1, S21becomes very large. For example, according to the simulation result ofFIG.6B, S21is about −1.9 [dB] when a signal of 8.9 [GHz] is input from Port 1. That is, the amount of about 65% of the energy of the signal input from Port 1 is transmitted to Port 2. The simulation result shown inFIG.6Aindicates that S11becomes very small at such specific frequency at which S21becomes very large.

From the above, the simulation results shown inFIGS.6A and6Bindicate the following. That is, in the system in which the chip107of the superconducting quantum circuit is mounted on the sample holder101as shown inFIGS.5A and5B, the space sandwiched between the GND plane73on the front surface of the chip107and the metal base102, that is, the silicon substrate forms a cavity resonator. The first coplanar waveguide71and the second coplanar waveguide72of the chip107are coupled with this cavity resonator. Therefore, when a signal having a frequency equal to the resonance frequency of this cavity resonator is input to the chip from Port 1, for example, resonance of the cavity resonator is excited. Then, a standing wave rises in the silicon substrate, and energy of the electromagnetic field is accumulated. Since the second coplanar waveguide72of the chip107is also coupled with this cavity resonator, a part of the energy of the electromagnetic field accumulated in the silicon substrate is transmitted to Port 2 through the second coplanar waveguide72of the chip107.

Such a phenomenon can occur in the system shown inFIGS.3A and3Bregardless of the type of the circuit formed in the chip107. Such a phenomenon can occur not only in a case where the coplanar waveguides71and72as shown inFIGS.4A and4Bare formed in the chip107, but also in a case where an arbitrary superconducting quantum circuit is formed in the chip107. In the mounting system as shown inFIG.3, the resonance caused by the space sandwiched between the GND plane73and the metal base102on the surface of the chip107, that is, the silicon substrate that forms the cavity resonator is referred to as resonance of the chip mode in the present description.

In the simulation results ofFIG.6AandFIG.6B, several specific frequencies at which S21becomes very large and S11becomes very small are hereinafter referred to as resonance frequencies of the chip mode. When a signal having a frequency equal to or close to the resonance frequency of the chip mode is input to the chip107, resonance of the chip mode occurs. According to the simulation results ofFIGS.6A and6B, the lowest resonance frequency of the chip mode is 8.9 [GHz] in the system shown inFIGS.5A and5B. In the system shown inFIGS.3A and3B, where the chip107having the superconducting quantum circuit is mounted on the sample holder101shown inFIGS.1A and1B, when the chip mode is coupled with the superconducting quantum circuit formed on the chip107, it causes decoherence of the superconducting quantum circuit. It is known that the resonance frequency of the chip mode needs to be as high as possible in order to reduce the influence of decoherence.

For this reason, a technology for increasing the resonance frequency of the chip mode is required. For example, in the sample holder101to be compared, the influence of the chip mode can be reduced by hollowing out a part of a section of the base102immediately below the chip107to form a cavity immediately below the chip107.

FIGS.7A to7Cshow enlarged views of the sample holder101having a cavity formed in the base102, near the through hole104of the PCB103.FIG.7Ais a perspective view of the sample holder101in which the cavity is formed in the base.FIG.7Bis a top view of the sample holder101in which the cavity is formed in the base;FIG.7Cis an end view in which the sample holder101in which the cavity is formed in the base is cut with a plane parallel to the xz plane including the cutting line B-BB shown inFIG.7B. As shown inFIGS.7A to7C, a cavity105is formed in a section of the base102immediately below the through hole104of the PCB103. In other words, as shown inFIGS.7A to7C, in the base102, the cavity105is formed in a section immediately below the chip107when the chip107is mounted on the sample holder101. InFIGS.7A to7C, the cavity105has a quadrangular prism shape having a bottom surface having the same area as the area of the chip107. The base102has a structure in which columns106are left at four corners of the cavity105. The column106is made of metal, for example. InFIG.7C, the chip107is mounted on the sample holder101with the bonding wire113.

InFIGS.7A,7B, and7C, in order to clearly show the columns106, the columns106are indicated in a pattern different from that of the base102. The metal columns106at the four corners are integrated with the base102and constitute a part of the base102. Of the two bottom surfaces of the metal columns106at the four corners shown inFIGS.7A to7C, the upper bottom surface is in contact with the back surface of the chip107. InFIGS.7A and7B, the bottom surface of the metal column106is an isosceles right triangle. As shown inFIG.7C, simulation is performed for a case where the chip107ofFIGS.4A and4Bis mounted on the sample holder101ofFIG.7with the lengths of the two equal sides of the bottom surface of the column106being 1 [mm] and the height of the cavity105being 3 [mm].

FIG.8is an explanatory diagram showing a simulation result of reflection (S11) to Port 1 when a high-frequency signal is input from Port 1 shown inFIG.5Ain a case where the chip107shown inFIGS.4A and4Bis mounted with the bonding wire113on the sample holder101shown inFIGS.7A,7B, and7C. The simulation result ofFIG.8indicates that when the chip107shown inFIGS.4A and4Bis mounted with the bonding wire113on the sample holder101in which the cavity105ofFIG.7is formed on the base102, the lowest resonance frequency of the chip mode can be increased to 19.9 [GHz]. In the simulation results shown inFIGS.6A and6Bin a case where the cavity105is not formed in the base102, the lowest resonance frequency of the chip mode is 8.9 [GHz]. This indicates that the resonance frequency of the chip mode can be significantly increased by using the sample holder101in which the cavity105ofFIGS.7A,7B, and7Cis formed in the base102.

The reason why the resonance frequency of the chip mode can be increased by forming the cavity105in the base102is inferred that, when the cavity105is formed immediately below the chip107, the inside of the cavity resonator formed by the space sandwiched between the GND plane73on the front surface of the chip107and the base102is silicon and vacuum. In this case, the base102is the bottom of the cavity105. A thickness of the silicon is 380 [μm] in the simulation. A thickness of vacuum is 3 [mm] in the simulation. Due to this, it is inferred to be because the effective permittivity inside the cavity resonator decreases as compared with the case where the cavity105is not formed in the base102. The case where the cavity105is not formed in the base102is, in other words, the case where the inside of the cavity resonator is substantially only silicon. While the relative permittivity of vacuum is 1, the relative permittivity of silicon is 11.9, which is very high. The resonance frequency of the cavity resonator generally has a property that the lower the permittivity of the medium filling the inside of the cavity resonator is, the higher the resonance frequency becomes.

Thus, the resonance frequency of the chip mode can be increased by using the sample holder101in which the cavity105is formed in the base102. However, in order to reduce the influence of the chip mode on the superconducting quantum circuit, it is required to make the resonance frequency of the chip mode as high as possible. It is predicted that the chip107having an area larger than 5 [mm]×5 [mm] will be required when the number of bits of quantum bits integrated on the chip107increases toward practical use of a quantum computer. The more the area of the chip107increases, the more the resonance frequency of the chip mode decreases. This is because the more the area of the chip107increases, the more the dimensions of the bottom surface of the cavity resonator formed by the space sandwiched between the GND plane73on the front surface of the chip107and the base102increases. Therefore, even if the sample holder101in which the cavity105is formed in the base102as shown inFIGS.7A to7Cis used, it is predicted that the more the area of the chip107increases, the more the resonance frequency of the chip mode decreases and the more the influence on the quantum circuit increases. From the above, it is required to develop a technology capable of further making the resonance frequency of the chip mode as high as possible as compared with the case of using the sample holder101in which the cavity105is formed on the base102.

The example embodiments capable of further increasing the resonance frequency of the chip mode will be described.

First Example Embodiment

In the first example embodiment, the sample holder includes a base and a PCB in contact with the base. In the first example embodiment, an example in which a PCB includes a dielectric, a front-surface GND that is formed on a front surface of the dielectric, a back-surface GND that is formed on a back surface of the dielectric, and a through hole that penetrates from the front-surface GND to the back-surface GND, the through hole in which a chip is disposed will be described. In the first example embodiment, at least a part of the base below the through hole has a cavity, and the cavity has a support structure that supports a surface of the chip and is conducted to the base. Here, the first example embodiment is characterized in that at least a part of the section that supports the chip in the support structure is not parallel to the back surface of the chip. In particular, in the first example embodiment, an example in which a column is used as the support structure will be described.

FIG.9is an explanatory diagram showing the sample holder according to the first example embodiment. A sample holder1of the first example embodiment has a configuration in which a PCB3is placed on a metal base2as shown inFIG.9. A through hole4penetrating the PCB3is provided near the center of the PCB3. The shape of the base2is not particularly limited. Examples of the shape of the base2include a rectangular parallelepiped and a cube. The sample holder1has a cavity5in a section of the base2immediately below the through hole4of the PCB3.

By aligning the height of the circuit surface of the chip and the height of the surface of the PCB3as much as possible, it is possible to facilitate wire bonding, and it is possible to shorten the bonding wire. The shorter the bonding wire is, the better the electrical characteristics become. By forming the through hole4in the PCB3, it is possible to increase the resonance frequency of the chip mode. If a dielectric or a conductor exists on the back surface of the chip, the resonance frequency of the chip mode decreases. The back surface of the chip is the surface opposite to the circuit surface. Therefore, in order to increase the resonance frequency of the chip mode, the back surface of the chip is brought into contact with vacuum as much as possible. If the chip is disposed on the PCB3without forming the through hole4in the PCB3, the dielectric or the conductor of the PCB3comes into contact with the back surface of the chip, and therefore the resonance frequency of the chip mode cannot be increased. Therefore, the first example embodiment has a structure in which the largest possible area of the back surface of the chip is in contact with the vacuum by forming the through hole4in the PCB3, disposing the chip in the through hole4, and forming the cavity5in the base2immediately below the chip.

FIGS.10A to10Cshow enlarged views of the sample holder1of the first example embodiment near the through hole4of the PCB3.FIG.10Ais a perspective view showing the sample holder1of the first example embodiment.FIG.10Bis a top view of the sample holder1of the first example embodiment.FIG.10Cis an end view in which the sample holder1of the first example embodiment is cut with a plane parallel to the xz plane including the cutting line C-CC shown inFIG.10B. InFIG.10C, a chip7is mounted with a bonding wire13on the sample holder1of the first example embodiment.

The sample holder1has the cavity5in at least a part of the base2below the through hole4. InFIGS.10A to10C, the sample holder1has the cavity5in a section of the base2immediately below the through hole4of the PCB3. In other words, inFIGS.10A to10C, the sample holder1has the cavity5in a section of the base2immediately below the chip7when the chip7is mounted on the sample holder1with the bonding wire13. The shape of the cavity5is not particularly limited. For example, the bottom surface of the cavity5may be a flat surface or may be a surface other than a flat surface. The side surface of the cavity5may be a flat surface or may be a surface other than a flat surface. For example, there may be a recess or the like on the side surface of the cavity5or the bottom surface of the cavity5. InFIGS.10A to10C, the cavity5has the shape of a quadrangular prism. More specifically, inFIGS.10A to10C, the cavity5has a quadrangular bottom surface where the lengths of the sides are a and b, and the cavity5has a quadrangular prism shape where the height is d. The cavity5has a support structure that supports the surface of the chip7and is conducted to the base. The material of the support structure is, for example, metal. Specifically, the material of the support structure may be, for example, a mixture containing metal such as a resin mixed with metal particles or a filler.

The shape of the support structure is not particularly limited. For example, inFIGS.10A to10C, the support structure may be a column6. Although not illustrated, the support structure may be, for example, a protrusion extending from the side surface of the cavity5. Alternatively, although not illustrated, the support structure may be three support points that are not linear, for example. Alternatively, although not illustrated, the support structure may be a structure extending from the bottom surface of the cavity5like a spiky frog.

Here, the column6shown inFIGS.10A to10Cwill be described as an example of the support structure. The number of the columns6and the shape of the columns6are not particularly limited. The same is true for the following example embodiments. InFIGS.10A to10C, a plurality of the columns6are provided in the cavity5. More specifically, the columns6that are conductors are arranged at the four corners of the cavity5.

InFIGS.10A to10C, in order to clearly show the columns6, the columns6are indicated in a pattern different from that of the base2. The cavity5inFIGS.10A to10Chas the same structure as that of the cavity105inFIGS.7A to7C. That is, the lower bottom surfaces of the columns6at the four corners have a shape of an isosceles right triangle. The length of equal two sides (equal sides) of the lower bottom surface of the column6is s. The height of the column6is d. The columns6of the conductors at the four corners are in electrical contact with the base2. The four conductor columns6shown inFIGS.10A to10Cmay be separate from the base2. Alternatively, the columns6shown inFIGS.10A to10Cmay be made of the same material as that of the base2. That is, the base2and the columns6may be integrated.

Here, effects of use of the column6will be described. If there is no column6, there is a concern that the chip7falls in the cavity5. The chip7and the PCB3are connected by the bonding wire. Therefore, there is a possibility that the chip7does not fall in the cavity5even without the column6, but there is a concern that the chip7falls in the cavity5due to vibration or the like, or the chip7falls in the cavity5due to detachment of some of the bonding wires. Therefore, by providing the metal column6, it is possible to prevent the chip7from falling in the cavity5and prevent the bonding wire from being detached. The metal column6can strengthen the thermal path between the chip7and the base2. The chip7of the superconducting quantum circuit is cooled to about 10 [mK] (milli-Kelvin) by a cryocooler and operated. In general, the base2is in thermal contact with a cold stage of the cryocooler. The cold stage of the cryocooler is the coldest place of the cryocooler. That is, the base2has a very low temperature. The stronger the thermal path between the base2and the chip7is, in other words, the smaller the thermal resistance between the base2and the chip7is, the more the chip7is cooled. If the chip7is not cooled well, good performance of the quantum circuit formed in the chip7cannot be obtained, and thus it is desirable to cool the chip7to a temperature as low as possible. Therefore, the thermal resistance between the base2and the chip7is preferably as small as possible. The metal column6can reduce the thermal resistance between the base2and the chip7.

The difference from the structure of the cavity105shown inFIGS.7A to7Cis that, in the present example embodiment, at least a part of the upper surfaces of the columns6at the four corners, that is, the surface opposing the back surface of the chip7when the chip7is mounted on the sample holder1, is not parallel to the back surface of the chip7. In other words, in the present example embodiment, at least a part of the upper surfaces of the columns6at the four corners is not parallel to the upper surface of the base2.

InFIG.10C, the column6used in the sample holder1of the present example embodiment has a structure in which an upper section61and a lower section62are connected. The lower section62has a column shape. The lower section62has a prismatic shape. InFIGS.10A to10C, the lower section62has a triangular prism shape, and the bottom surface of the lower section62has a shape of an isosceles right triangle. The length of the equal two sides of this bottom surface is s, and the height of the lower section62is d1. The upper section61has a frustum shape. The bottom surface of the frustum having the smaller area is the through hole4side. InFIGS.10A to10C, the upper section61has a triangular pyramid shape, the bottom surface of the upper section61has a shape of an isosceles right triangle, and the height of the upper section61is d2. Here, d1+d2=d. For example, the bottom surface of the upper section61and the bottom surface of the lower section62have the same shapes and dimensions. In this structure, when the chip7is mounted on the sample holder1, at least a part of the columns6at the four corners comes into contact with the back surface of the chip7. This structure makes it possible to reduce the contact area between the back surface of the chip7and the column6of the conductor as compared with the sample holder101shown inFIGS.7A to7C.

FIG.11Ais a top view of the PCB3used in the sample holder1of the first example embodiment.FIG.11Bis a bottom view of the PCB3used in the sample holder1of the first example embodiment.FIG.11Cis a side view of the PCB3used in the sample holder1of the first example embodiment.FIG.11Dis a perspective view of the PCB3used in the sample holder1of the first example embodiment.FIG.11Eis an enlarged view of the PCB3used in the sample holder1of the first example embodiment near the through hole4.

As shown inFIGS.11A and11E, the PCB3has a plate-shaped dielectric8extending parallel to the xy plane, for example. The PCB3has a structure in which a front-surface GND9and a core wire10of the coplanar waveguide are formed on one surface (front surface) of the dielectric8. The PCB3has a structure in which a back-surface GND11is formed on the other surface (back surface) of the dielectric8. The core wire10, the front-surface GND9, and the back-surface GND11are conductors that is, for example, metals. Examples of the metal include copper (Cu) and Cu plated with gold plating (Au plating). InFIG.11A, eight coplanar waveguides are formed on the PCB3. The coplanar waveguide is as described inFIG.2A. However, the number of the coplanar waveguides formed on the PCB3is not particularly limited, and may be any number. As shown inFIG.11D, the PCB3is provided with a plurality of through holes12. These through holes12penetrate the dielectric8and electrically connect the front-surface GND9and the back-surface GND11. The through hole12is produced, for example, by forming a hole that penetrates the dielectric8, the front-surface GND9, and the back-surface GND11and then plating the inside of the hole with metal.

InFIG.9, the back-surface GND11of the PCB3is in contact with the base2. Therefore, the metal base2, the back-surface GND11of the PCB3, the through hole12of the PCB3, and the front-surface GND9of the PCB3are electrically connected. The through hole4is provided near the center of the PCB3. This through hole4may have, for example, the same shape as that of the chip7of the superconducting quantum circuit mounted on the sample holder1, that is, a rectangular shape or a square shape. In order to allow the chip7to enter the inside of the through hole4, the area of the through hole4is larger than the area of the chip7.

FIG.12shows a simulation result of S11of the system in which the chip7is mounted with the bonding wire13on the sample holder1of the first example embodiment shown inFIG.9. Here, as described above, S11is reflection to Port 1 in a case where a high-frequency signal is input from Port 1 shown inFIG.11A.FIG.12is an explanatory diagram showing a simulation result of S11in a case where the chip7is mounted with the bonding wire13on the sample holder1according to the first example embodiment. In the simulation inFIG.12, a=5 [mm], b=5 [mm], d=3 [mm], d1=2 [mm], d2=1 [mm], and s=1 [mm].

As shown inFIG.12, the lowest resonance frequency of the chip mode is 21.5 [GHz]. Therefore, as inFIG.12, the lowest resonance frequency of the chip mode can be made higher than that in the simulation result shown inFIG.8where the simulation is performed using the sample holder101shown inFIGS.7A to7C.

The reason why the resonance frequency of the chip mode can be further increased by using the sample holder1of the first example embodiment is considered to be as follows. In the example of the sample holder101shown inFIGS.7A to7C, the electric field of the standing wave generated when resonance of the chip mode occurs spreads mainly in the silicon substrate and in the cavity105(vacuum) provided in the base102. In the part immediately above the columns106at the four corners, the space sandwiched between the GND plane73on the front surface of the chip107and the columns106is only silicon, and the electric field cannot spread in vacuum. Therefore, the effective permittivity is high in the section immediately above the columns106at the four corners. On the other hand, in the case of the sample holder1of the first example embodiment, at least a part of the upper surfaces of the columns6at the four corners is not parallel to the back surface of the chip7. Due to this, in the section immediately above the columns6at the four corners, the space sandwiched between the GND plane73on the front surface of the chip7and the columns6becomes silicon and vacuum, and therefore the electric field can also spread in vacuum in this section. Therefore, it is considered that the effective permittivity in the section immediately above the columns6at the four corners becomes lower than that of the sample holder101shown inFIGS.7A to7C. As another example of the first example embodiment,FIGS.13A to13Cshow a case where the thickness s of the columns6at the four corners is made larger than that inFIGS.10A to10C.FIG.13Ais a perspective view of a sample holder1according to another example of the first example embodiment.FIG.13Bis a top view of the sample holder1according to the another example of the first example embodiment.FIG.13Cis an end view in which the sample holder1according to the another example of the first example embodiment is cut with a plane parallel to the xz plane including the cutting line D-DD shown inFIG.13B. InFIG.13C, the chip7is mounted on the sample holder1according to another example of the first example embodiment.

FIG.14shows a simulation result of S11where the chip7is mounted with the bonding wire13on the sample holder1using the base2in which the cavity5ofFIGS.13A to13Cis formed.

FIG.14is an explanatory diagram showing a simulation result of S11according to the another example of the first example embodiment. In the simulation, a=5 [mm], b=5 [mm], d=3 [mm], d1=0.5 [mm], d2=2.5 [mm], and s=2.5 [mm]. As shown inFIG.14, the lowest resonance frequency of the chip mode is 21.5 [GHz]. Therefore, as inFIG.14, the lowest resonance frequency of the chip mode can be made higher than that in the simulation result shown inFIG.8where the simulation is performed using the sample holder101shown inFIGS.7A to7C.

Modification of First Example Embodiment

In the modification of the first example embodiment, the upper surfaces of the upper section61of the columns6at the four corners of the cavity5, that is, a part of the front surface opposing the back surface of the chip7when the chip7is mounted with the bonding wire13on the sample holder1, is not parallel to the back surface of the chip7, but a part is parallel to the back surface of the chip7.

FIG.15Ais a perspective view of the sample holder1according to a modification of the first example embodiment.FIG.15Bis a top view of the sample holder1according to the modification of the first example embodiment.FIG.15Cis an end view in which the sample holder1according to the modification of the first example embodiment is cut with a plane parallel to the xz plane including the cutting line E-EE shown inFIG.15B. InFIGS.15A to15C, the upper surface of the upper section61of the columns6at the four corners of the cavity5, that is, a part of the front surface opposing the back surface of the chip7of the surface of the base2forming the cavity5when the chip7is mounted with the bonding wire13on the sample holder1, is not parallel to the back surface of the chip7, but a part is parallel to the back surface of the chip7. In other words, at least a part of the upper surface of the upper section61of the columns6at the four corners is not parallel to the upper surface of the base2, but a part is parallel to the upper surface of the base2. Similarly to the case of10A to10C and13A to13C, the lower section62of the column6has a triangular prism shape, the bottom surface of the lower section62is an isosceles right triangle, and the length of the equal two sides is s1.

On the other hand, the upper section61of the column6has a triangular frustum shape, the lower bottom surface of the upper section61is an isosceles right triangle, and the length of the equal two sides is s1, but the upper bottom surface of the upper section61is an isosceles right triangle, and the length of the equal two sides is s2. Here, s1>s2. The height of the lower section62of the column6is d1, and the height of the upper section61is d2. In this structure, when the chip7is mounted on the sample holder1, at least a part of the columns6at the four corners comes into contact with the back surface of the chip7. This structure makes it possible to reduce the contact area between the back surface of the chip7and the column6of the conductor as compared with the sample holder101shown inFIGS.7A to7C. However, in the sample holder1shown inFIGS.15A to15C, the contact area between the back surface of the chip7and the column6of the conductor becomes larger than that in the case ofFIGS.10Ato10C andFIGS.13A to13C.

FIG.16is an explanatory diagram showing a simulation result of S11in a case where the chip7is mounted on the sample holder1using the base2in which the cavity5is formed, ofFIGS.15A to15C. In the simulation, a=5 [mm], b=5 [mm], d=3 [mm], d1=2 [mm], d2=1 [mm], s1=1 [mm], and s2=0.5 [mm]. As shown inFIG.16, the lowest resonance frequency of the chip mode is 21.2 [GHz]. As shown inFIG.16, according to the modification of the first example embodiment, the lowest resonance frequency of the chip mode can be made higher than that in the simulation result shown inFIG.8where the simulation is performed using the sample holder101shown inFIGS.7A to7C. Thus, the first example embodiment achieves the effect that the simulation result can be made higher than the simulation result shown inFIG.8where simulation is performed using the sample holder101shown inFIGS.7A to7Ceven if a part of the upper surface of the upper section61of the columns6at the four corners is made parallel to the back surface of the chip7.

In the first example embodiment and the modification of the first example embodiment, for example, the chip7mounted on the sample holder1has a rectangular shape, and the length of the short side of the chip7is v, and the length of the long side of the chip7is w. In such a case, in the cavity5shown inFIGS.10A to10C, the cavity5shown inFIGS.13A to13C, and the cavity5shown inFIGS.15A to15C, it is preferable that a<b, a is v or more, and b is w or more. In a case otherwise, there is a concern that the contact area between the back surface of the chip7and the base2increases, and the resonance frequency of the chip mode decreases. In this case, the through hole4of the PCB3used in the first example embodiment and the modification of the first example embodiment is preferably rectangular, and when the length of the short side of the through hole4of the PCB3is x1and the length of the long side of the through hole4is y1, it is necessary that v<x1and w<y1because the chip7needs to enter the inside of the through hole4. Since the shorter x1and y1are, the higher the resonance frequency of the chip mode can be made, x1is preferably 1.2 v or less, and more preferably 1.1 v or less. For the same reason, b is preferably 1.2 w or less, and more preferably 1.1 w or less.

On the other hand, when the chip7mounted on the sample holder1has a square shape and the length of one side of the chip7is v, a=b is preferable in the cavity5ofFIGS.10A to10C,FIGS.13A to13C, andFIGS.15A to15C, and a is preferably v or more. In this case, the through hole4of the PCB3used in the first example embodiment and the modification of the first example embodiment is preferably square. In a case where the length of one side of the through hole4of the PCB3is x1, the chip7needs to enter the inside of the through hole4, and therefore v<x1is required. Since the shorter x1is, the higher the resonance frequency of the chip mode can be made, x1is preferably 1.2 v or less, and more preferably 1.1 v or less.

According to the simulation, the larger the height d of the cavity5is made, the higher the resonance frequency of the chip mode becomes, but when d is increased to some extent, the resonance frequency of the chip mode hardly changes even if d is further increased. Therefore, in the first example embodiment, in a case where the thickness of the chip7mounted on the sample holder1is t, the height d of the cavity5shown inFIGS.10A to10Cis preferably 2 t or more, more preferably 3 t or more, and still more preferably 5 t or more. In the first example embodiment and the modification of the first example embodiment, there is an effect of increasing the resonance frequency of the chip mode when d2is larger than 0. Therefore, d2is preferably larger than 0 and less than or equal to d. When d2=d, d1=0, and in this case, the column6includes only the upper section61. In the first example embodiment, in a case where the chip7mounted on the sample holder1is a rectangle and the length of the short side of the chip7is v, s is preferably 0.1 v or more and 0.5 v or less. When the chip7mounted on the sample holder1is a square and the length of one side of the chip7is v, s is preferably 0.1 v or more and 0.5 v or less. Similarly, in the modification of the first example embodiment, in a case where the chip7mounted on the sample holder1is a rectangle and the length of the short side of the chip7is v, s1is preferably 0.1 v or more and 0.5 v or less. When the chip7mounted on the sample holder1is a square and the length of one side of the chip7is v, s1is preferably 0.1 v or more and 0.5 v or less. In the modification of the first exemplary example embodiment, s2is only required to satisfy s2<s1. In the first example embodiment and the modification of the first example embodiment, there is an effect of increasing the resonance frequency of the chip mode when d2is larger than 0. Therefore, d2is preferably larger than 0 and less than or equal to d. When d2=d, d1=0, and in this case, the column6includes only the upper section61.

In the first example embodiment and the modification of the first example embodiment, the shape of the lower section62of the column6is a triangular prism having a bottom surface of an isosceles right triangle, and the shape of the upper section61is a triangular pyramid, but the shapes of the lower section62and the upper section61of the column6are not particularly limited. Unless at least a part of the upper surface of the upper section61, that is, the surface of the upper section61opposing the back surface of the chip7, is parallel to the back surface of the chip7or the upper surface of the base2, the effects described in the first example embodiment and the modification of the first example embodiment are obtained.

Second Example Embodiment

The second example embodiment will be described in detail with reference to the drawings. Hereinafter, description of the content overlapping with the above description will be omitted to the extent that the description of the second example embodiment does not become unclear.

The sample holder1of the second example embodiment has a configuration in which the PCB3is placed on the metal base2as shown inFIG.9. In the second example embodiment, similarly to the first example embodiment, the PCB3shown inFIGS.11A to11Eis used. In the second example embodiment, the sample holder1has the cavity5in a section of the base2immediately below the through hole4of the PCB3. In other words, the sample holder1has the cavity5in a section of the base2immediately below the chip7when the chip7is mounted on the sample holder1. In the second example embodiment, the cavity5has a shape in which the column and the frustum are combined, and the bottom surface having the narrower area of the frustum and the upper bottom surface of the column have the same shape. For example, the bottom surface of the frustum having the larger area is the through hole4side. As an example of the frustum of the cavity5, a prismoid will be described as an example. As an example of the column of the cavity5, a prism will be described as an example.

The sample holder1according to the second example embodiment is shown inFIGS.17A to17C.FIG.17Ais a perspective view of the sample holder1according to the second example embodiment.FIG.17Bis a top view of the sample holder1according to the second example embodiment.FIG.17Cis an end view in which the sample holder1according to the second example embodiment is cut with a plane parallel to the xz plane including the cutting line F-FF shown inFIG.17B. InFIG.17C, the chip7is mounted with the bonding wire13on the sample holder1according to the second example embodiment.

As shown inFIGS.17B and17C, the cavity5formed in the base2in the second example embodiment has a structure in which a prismatic section51, which is a prism, and a prismoid section52, which is a prismoid, are connected. InFIGS.17B and17C, the bottom surface of the prismatic section51and the bottom surface of the prismoid section52having the smaller area are connected. Therefore, the bottom surface of the prismatic section51and the bottom surface of the prismoid section52having the smaller area have the same shape and the same area. The bottom surface of the prismoid section52having the larger area is the through hole4side.

InFIGS.17A to17C, the prismatic section51has a quadrangular bottom surface whose sides have the lengths a1and b1and a quadrangular prism shape having the height d1. InFIGS.17A to17C, the prismoid section52is a quadrangular prismoid.

Here, for example, lengths of sides of the chip7and the prismatic section51in a case where the chip7mounted on the sample holder1has a rectangular shape will be described. In a case where the length of the short side of the chip7is v and the length of the long side of the chip7is w, it is preferable that a1<b1in the prismatic section51, and a1is smaller than v and b1is smaller than w.

On the other hand, when the chip7mounted on the sample holder1has a square shape and the length of one side of the chip7is v, a1=b1is preferable in the prismatic section51, and a1is preferably smaller than v.

InFIGS.17A to17C, in the prismoid section52, the bottom surface of the two bottom surfaces that has the smaller area has a quadrangular shape in which the lengths of the sides are a1and b1. InFIGS.17A to17C, the bottom surface having the larger area of the prismoid section52has a quadrangular shape in which the lengths of the sides are a2and b2.

Here, assume that the chip7mounted on the sample holder1, for example, has a rectangular shape, and the length of the short side of the chip7is v and the length of the long side of the chip7is w. In such a case, it is preferable that a2<b2in the prismoid section52, a2is v or more and 1.5 v or less, and b2is w or more and 1.5 w or less.

On the other hand, when the chip7mounted on the sample holder1has a square shape and the length of one side of the chip7is v, a2=b2is preferable in the prismoid section52, and a2is preferably v or more and 1.5 v or less. The height of the prismoid section52is d2. The cavity5formed in the base2of the sample holder1of the present example embodiment has a structure in which the prismoid section52is connected above the prismatic section51, and the upper bottom surface of the prismatic section51and the lower bottom surface of the prismoid section52are the same plane. Here, the lower bottom surface of the prismoid section52is a bottom surface having the smaller area of the two bottom surfaces of the prismoid section52.

A feature of the sample holder1of the second example embodiment is that the prismoid section52is provided on the upper side of the cavity5, so that at least a part of the surface of the base2opposing the back surface of the chip7when the chip7is mounted on the sample holder1is not parallel to the back surface of the chip7. InFIGS.17A to17C, this part refers to the side surface of the prismoid section52. As shown inFIG.17C, the angle formed by a part not parallel to the back surface of the chip7in the side surface of the prismoid section52, that is, the surface opposing the back surface of the chip7when the chip7is mounted on the sample holder1and the back surface of the chip7is θ. In other words, the angle formed by the side surface of the prismoid section52and the upper surface of the base2is defined as θ. For example, θ is a range in which a part not parallel to the back surface of the chip7is formed on the side surface of the prismoid section52. For example, θ is less than 90 degrees. In the structure of the sample holder1of the second example embodiment, when the chip7is mounted on the sample holder1, at least a part of the base2comes into contact with the back surface of the chip7. This structure makes it possible to reduce the contact area between the back surface of the chip7and the base2as compared with the sample holder101shown inFIGS.7A to7C.

FIG.18is an explanatory diagram showing a simulation result of S11in a case where the chip7is mounted with the bonding wire13on the sample holder1according to the second example embodiment. In the simulation inFIG.18, a1=4 [mm], b1=4 [mm], d1=2.5 [mm], a2=5 [mm], b2=5 [mm], and d2=0.5 [mm]. In this case, θ is 45 degrees. As shown inFIG.18, the lowest resonance frequency of the chip mode can be increased to 20.8 [GHz].

Thus, the sample holder1of the second example embodiment has the effect that the simulation result can be made higher than the simulation result shown inFIG.8where simulation is performed using the sample holder101shown inFIGS.7A to7C. The reason why in the second example embodiment, the resonance frequency of the chip mode can be made higher than that in the simulation result shown inFIG.8where the simulation is performed using the sample holder101shown inFIGS.7A to7Cwill be described. In the case of the sample holder101shown inFIGS.7A to7C, the electric field of the standing wave generated when resonance of the chip mode occurs spreads mainly in the silicon substrate and in the cavity105(vacuum) provided in the base102, but in the section immediately above the columns106at the four corners, in other words, the section of the four corners of the chip107, the space sandwiched between the GND plane73on the front surface of the chip107and the columns106is only silicon, and the electric field cannot spread in vacuum. Therefore, the effective permittivity is high at the four corners of the chip107. On the other hand, in the case of the present example embodiment, since the prismoid section52is provided in the cavity5, also in the section of the four corners of the chip7, the space sandwiched between the GND plane73on the front surface of the chip7and the base2becomes silicon and vacuum. Therefore, it is considered that since the electric field can also spread in vacuum in this section, the effective permittivity in the section at the four corners of the chip7becomes lower than that of the sample holder101shown inFIGS.7A to7C.

Modification of Second Example Embodiment

As a modification of the second example embodiment,FIGS.19A to19Cshow the sample holder1in a case where the prismatic section51of the cavity5is eliminated and only the prismoid section52is provided.FIG.19Ais a perspective view of the sample holder1according to the modification of the second example embodiment.FIG.19Bis a top view of the sample holder1according to the modification of the second example embodiment.FIG.19Cis an end view in which the sample holder1according to the modification of the second example embodiment is cut with a plane parallel to the xz plane including the cutting line G-GG shown inFIG.19B. InFIG.19C, the chip7according to the modification of the second example embodiment is mounted with the bonding wire13. As shown inFIGS.19A to19C, the cavity5does not have the prismatic section51but has the prismoid section52. InFIGS.19A to19C, the prismoid section52is a quadrangular prismoid. For example, θ is a range in which the side surface of the prismoid section52becomes not parallel to the back surface of the chip7. For example, in the case of a quadrangular prismoid, θ is less than 90 degrees.

FIG.20is an explanatory diagram showing a simulation result of S11in a case where the chip7is mounted with the bonding wire13on the sample holder1using the base2in which the cavity5is formed, shown inFIGS.19A to19C. InFIG.20, in the simulation, a1=2 [mm], b1=2 [mm], a2=5 [mm], b2=5 [mm], d1=0 [mm], and d2=5 [mm]. In this case, θ is about 73.3 degrees. As shown inFIG.20, the lowest resonance frequency of the chip mode is 21.4 [GHz]. AsFIG.20, the lowest resonance frequency of the chip mode can be made higher than the simulation result ofFIG.8by the sample holder101shown inFIGS.7A to7C.

In the second example embodiment and the modification of the second example embodiment, in a case where the thickness of the chip7mounted on the sample holder1is t, the height d1+d2of the cavity5inFIGS.17A to17CandFIGS.19A to19Cis preferably 2 t or more, more preferably 3 t or more, and still more preferably 5 t or more.

In the second example embodiment and the modification of the second example embodiment, there is an effect of increasing the resonance frequency of the chip mode when d2is larger than 0. Therefore, d2is preferably greater than 0. On the other hand, d1may be 0, and thus d2is preferably 0 or more. When d1=0, the cavity5includes only the prismoid section52.

In the second example embodiment and the modification of the second example embodiment, the cavity5has a structure in which the prismatic section51and the prismoid section52are connected or a structure including only the prismoid section52, but the prismoid section52need not have a prismoid shape. For example, the side surface of the prismoid section52may be a curved surface instead of a plane. That is, unless at least a part of the front surface of the base2forming the cavity5opposing the back surface of the chip7is parallel to the back surface of the chip7or the upper surface of the base2, the effects described in the second example embodiment and the modification of the second example embodiment are obtained. Instead of the prismoid shape of the prismoid section52, a pyramid shape may be used. Therefore, the cavity5may have a structure in which the prismatic section51and a pyramid section are connected or a structure including only the pyramid section.

Third Example Embodiment

The third example embodiment will be described in detail with reference to the drawings. Hereinafter, description of the content overlapping with the above description will be omitted to the extent that the description of the third example embodiment does not become unclear.

The sample holder1of the third example embodiment has a configuration in which the PCB3is placed on the metal base2as shown inFIG.9. The third example embodiment uses the PCB3having the structure shown inFIGS.11A to11Esimilarly to that of the first example embodiment. In the third example embodiment, the sample holder1has the cavity5in a section of the base2immediately below the through hole4of the PCB3, in other words, in a section immediately below the chip7when the chip7is mounted on the sample holder1. Similarly to the second example embodiment, the cavity5has a shape in which the prism and the prismoid are combined, and has a shape in which the bottom surface having the narrower area of the prismoid and the upper bottom surface of the prism are connected. In the third example embodiment, unlike the second example embodiment, a prismoid may be deformed. Due to this, in the third example embodiment, when the chip7is mounted on the sample holder1, at least a part of the front surface opposing the back surface of the chip7of the surface of the base2forming the cavity5is not parallel to the back surface of the chip7.

FIG.21Ais a perspective view of the sample holder of the third example embodiment.FIG.21Bis a top view of the sample holder of the third example embodiment.FIG.21Cis a cross-sectional view in which the sample holder1of the third example embodiment is cut with a plane parallel to the xz plane including the cutting line H-HH shown inFIG.21B. InFIG.21C, the chip7is mounted with the bonding wire13on the sample holder1according to the third example embodiment. As shown inFIGS.21A to21C, the cavity5formed in the base2in the third example embodiment has a structure in which the prismatic section51and the prismoid deformation section53are connected.

The prismatic section51has a quadrangular bottom surface whose sides have the lengths a1and b1and a quadrangular prism shape having the height d1.

Here, assume that the chip7mounted on the sample holder1, for example, has a rectangular shape, and the length of the short side of the chip7is v and the length of the long side of the chip7is w. In such a case, it is preferable that a1<b1in the prismatic section51, and a1is smaller than v and b1is smaller than w.

On the other hand, when the chip7mounted on the sample holder1has a square shape and the length of one side of the chip7is v, a1=b1is preferable in the prismatic section51, and a1is preferably smaller than v.

In the prismoid deformation section53, the bottom surface of the two bottom surfaces that has the smaller area has a quadrangular shape in which the lengths of the sides are a1and b1, and the bottom surface having the larger area has an octagonal shape in which the four corners of the quadrangle in which the lengths of the sides are a2and b2are obliquely cut.

Here, assume that the chip7mounted on the sample holder1, for example, has a rectangular shape, and the length of the short side of the chip7is v and the length of the long side of the chip7is w. In such a case, it is preferable that a2<b2in the prismoid deformation section53, a2is v or more and 1.5 v or less, and b2is w or more and 1.5 w or less.

On the other hand, when the chip7mounted on the sample holder1has a square shape and the length of one side of the chip7is v, a2=b2is preferable in the prismoid deformation section53, and a2is preferably v or more and 1.5 v or less.

The height of the prismoid deformation section53is d2. The cavity5formed in the base2of the sample holder1of the present example embodiment has a structure in which the prismoid deformation section53is connected above the prismatic section51, and the upper bottom surface of the prismatic section51and the lower bottom surface of the prismoid deformation section53are the same plane. Here, the lower bottom surface of the prismoid deformation section53is a bottom surface having the smaller area of the two bottom surfaces of the prismoid deformation section53. The shape of the cavity5inFIGS.21A to21Cof the present example embodiment will be described with reference toFIGS.22A to22CandFIGS.23A to23Cfor more accurate description.

FIG.22Ais a perspective view showing the shape example 1 of the cavity5of the sample holder1of the third example embodiment.FIG.22Bis a top view showing the shape example 1 of the cavity5of the sample holder1of the third example embodiment.FIG.22Cis an end view in which in the example shape 1 of the cavity5of the sample holder1of the third example embodiment, the sample holder1is cut near the cavity5with a plane parallel to the xz plane including the cutting line I-II shown inFIG.22B. InFIG.22C, the chip7is mounted with the bonding wire13on the sample holder1according to the second example embodiment.

FIG.23Ais a perspective view showing the shape example 2 of the cavity5of the sample holder1of the third example embodiment.FIG.23Bis a top view showing the shape example 2 of the cavity5of the sample holder1of the third example embodiment.FIG.23Cis a cross-sectional view in which the sample holder1is cut with a plane parallel to the xz plane including the cutting line J-JJ shown inFIG.23Bin the example shape 2 of the cavity5of the sample holder1of the third example embodiment. InFIG.23C, the chip7is mounted with the bonding wire13on the sample holder1according to the third example embodiment.

The cavity5shown inFIGS.22A to22Chas the same structure as that of the cavity5shown inFIGS.17A to17Cof the second example embodiment. That is, the cavity5shown inFIGS.22A to22Chas a configuration in which the prismatic section51and the prismoid section52are connected. In the third example embodiment, four conductor columns6shown inFIGS.23A to23Care further added to the four corners of the cavity5shown inFIGS.22A to22Csimilar to the second example embodiment. Due to this, the cavity5having the structure shown inFIGS.21A to21Ccan be formed in the base2. As shown inFIGS.23A to23C, in the present example embodiment, the conductor columns6at the four corners are triangular prisms, the bottom surface of the triangular prism has a shape of an isosceles right triangle, the length of the equal two sides of this bottom surface is s, and the height of the triangular prism is d1+d2. The columns6of the conductors at the four corners are in electrical contact with the base2. The four conductor columns6shown inFIGS.23A to23Cmay be separate from the base2, but may be made of the same material as that of the base2, that is, the base2and the four columns6may be integrated.

A feature of the sample holder1of the third example embodiment is that the prismoid deformation section53is provided on the upper side of the cavity5, so that at least a part of the front surface opposing the back surface of the chip7when the chip7is mounted with the bonding wire13on the sample holder1is not parallel to the back surface of the chip7. As shown inFIG.21C, the angle formed by a part not parallel to the back surface of the chip7in the side surface of the prismoid deformation section53, that is, the surface opposing the back surface of the chip7when the chip7is mounted on the sample holder1and the back surface of the chip7is θ. In other words, the angle formed by the side surface of the prismoid deformation section53and the upper surface of the base2is defined as θ. For example, θ is a range in which the side surface of the prismoid deformation section53becomes not parallel to the back surface of the chip7. For example, when the prismoid deformation section53is created based on the prismoid section52, which is a quadrangular prismoid, θ is less than 90 degrees. In the structure of the sample holder1of the third example embodiment, when the chip7is mounted on the sample holder1, at least a part of the base2comes into contact with the back surface of the chip7.

FIG.24shows a simulation result of S11in a case where the chip7is mounted with the bonding wire13on the sample holder1using the base2in which the cavity5ofFIGS.21A to21Cis formed.FIG.24is an explanatory diagram showing a simulation result of S11of the system in which the chip7is mounted with the bonding wire13on the sample holder1of the third example embodiment. In the simulation inFIG.24, a1=3 [mm], b1=3 [mm], a2=5 [mm], b2=5 [mm], d1=1 [mm], d2=2 [mm], and s=0.5 [mm]. In this case, θ is about 63.4 degrees. As shown inFIG.24, the lowest resonance frequency of the chip mode is 21.0 [GHz]. Therefore, as inFIG.24, the lowest resonance frequency of the chip mode can be made higher than that in the simulation result shown inFIG.8where the simulation is performed using the sample holder101shown inFIGS.7A to7C.

Thus, the sample holder1of the third example embodiment has an effect that the resonance frequency of the chip mode can be made higher than that of the sample holder101shown inFIGS.7A to7C.

Modification of Third Example Embodiment

As a modification of the third example embodiment,FIGS.25A to25Cshow a sample holder in a case where the prismatic section51of the cavity5is eliminated and only the prismoid deformation section53is provided.FIG.25Ais a perspective view of the sample holder1of the modification of the third example embodiment.FIG.25Bis a top view of the sample holder1of the modification of the third example embodiment.FIG.25Cis a cross-sectional view in which the sample holder1of the modification of the third example embodiment is cut with a plane parallel to an xz plane including the cutting line K-KK shown inFIG.25B. InFIG.25C, the chip7is mounted with the bonding wire13on the sample holder1according to the third example embodiment. In order to describe the shape of the cavity5shown inFIGS.25A,25B, and25Cof the modification of the third example embodiment in more detail, a description will be given with reference toFIGS.26A to26CandFIGS.27A to27C.

FIG.26Ais a perspective view showing the shape example 1 of the cavity5of the sample holder1of the modification of the third example embodiment.FIG.26Bis a top view showing the shape example 1 of the cavity5of the sample holder1of the modification of the third example embodiment.FIG.26Cis an end view in which in the example shape 1 of the cavity5of the sample holder1of the modification of the third example embodiment, the sample holder1is cut near the cavity5with a plane parallel to the xz plane including the cutting line L-LL shown inFIG.26B. InFIG.26C, the chip7is mounted with the bonding wire13on the sample holder1according to the modification of the third example embodiment.

FIG.27Ais a perspective view showing the shape example 2 of the cavity5of the sample holder1of the modification of the third example embodiment.FIG.27Bis a top view showing the shape example 2 of the cavity5of the sample holder1of the modification of the third example embodiment.FIG.27Cis a cross-sectional view in which the sample holder1is cut with a plane parallel to the xz plane including the cutting line M-MM shown inFIG.27Bin the shape example 2 of the cavity5of the sample holder1of the modification of the third example embodiment. InFIG.27C, the chip7is mounted with the bonding wire13on the sample holder1according to the modification of the third example embodiment.

The cavity5shown inFIGS.26A to26Chas the same structure as that of the cavity5inFIGS.19A to19Cof the modification of the second example embodiment. That is, the cavity5shown inFIGS.26A to26Bincludes only the prismoid section52. In the modification of the third example embodiment, four conductor columns6shown inFIG.27are further added to the four corners of the cavity5shown inFIG.26similarly to the modification of the second example embodiment. Due to this, the cavity5shown inFIGS.25A to25Ccan be formed in the base2. For example, θ is a range in which a part not parallel to the back surface of the chip7is formed on the side surface of the cavity5(prismoid section52) shown inFIGS.26A to26C. For example, when the cavity5shown inFIGS.26A to26Cis a quadrangular prismoid, θ is less than 90 degrees.

FIG.28shows a simulation result of S11in a case where the chip7is mounted with the bonding wire13on the sample holder1using the base2in which the cavity5shown inFIGS.25A to25Cis formed.FIG.28is an explanatory diagram showing a simulation result of S11of the system in which the chip7is mounted with the bonding wire13on the sample holder1of the modification of the third example embodiment. InFIG.28, in the simulation, a1=2 [mm], b1=2 [mm], a2=5 [mm], b2=5 [mm], d2=5 [mm], and s=0.5 [mm]. In this case, θ is about 73.3 degrees. As shown inFIG.28, the lowest resonance frequency of the chip mode is 21.1 [GHz]. Therefore, as inFIG.28, the lowest resonance frequency of the chip mode can be made higher than that in the simulation result shown inFIG.8where the simulation is performed using the sample holder101shown inFIGS.7A to7C.

In the third example embodiment and the modification of the third example embodiment, in a case where the thickness of the chip7mounted on the sample holder1is t, the sum d1+d2of the height d1of the prismatic section51of the cavity5and the height d2of the prismoid deformation section53inFIGS.21A to21CandFIGS.25A to25Cis preferably 2 t or more, more preferably 3 t or more, and still more preferably 5 t or more.

In the third example embodiment and the modification of the third example embodiment, there is an effect of increasing the resonance frequency of the chip mode when d2is larger than 0. Therefore, d2is preferably greater than 0. On the other hand, d1may be 0, and thus d2is preferably 0 or more. When d1=0, the cavity5includes only the prismoid deformation section53.

In the third example embodiment and the modification of the third example embodiment, the smaller the bottom area of the columns6at the four corners inFIGS.23A to23CandFIGS.27A to27Cis, the more the contact area between the back surface of the chip7and the base2can be reduced, and therefore the resonance frequency of the chip mode can be increased. Therefore, in a case where the chip7mounted on the sample holder1is a rectangle and the length of the short side of the chip7is v, s needs to be 0.5 v or less, preferably 0.3 v or less, and more preferably 0.2 v or less. On the other hand, when the chip7mounted on the sample holder1is a square and the length of one side of the chip7is v, s needs to be 0.5 v or less, preferably 0.3 v or less, and more preferably 0.2 v or less.

In the third example embodiment and the modification of the third example embodiment, the cavity5has a structure in which the prismatic section and the prismoid deformation section are connected or a structure including only the prismoid deformation section, but the cavity5may have another shape. For example, the side surface of the prismoid deformation section may be a curved surface instead of a plane. That is, unless at least a part of the front surface of the base2forming the cavity5opposing the back surface of the chip7is parallel to the back surface of the chip7or the upper surface of the base2, the effects described in the third example embodiment and the modification of the third example embodiment are obtained.

Other Example Embodiments

In the first to third example embodiments and the modifications of the first to third example embodiments, the PCB3inFIGS.11A to11Dis used as the PCB3. The PCB3ofFIGS.11A to11Dhas two metal layers. Specifically, it has a total of two metal layers of a metal layer in which the front-surface GND9and the core wire10are formed and a metal layer in which the back-surface GND11is formed. However, in the first to third example embodiments and the modifications of the first to third example embodiments, the effects described in the first to third example embodiments and the modifications of the first to third example embodiments can be obtained even if the PCB3having three or more metal layers is used instead of the PCB3having two metal layers as inFIGS.11A to11D. As an example of the PCB3having three or more metal layers, a configuration example of the PCB3having three metal layers is shown inFIGS.29A to29F.

FIG.29Ais a top view showing the structure of the PCB3according to another example embodiment.FIG.29Bis a cross-sectional view in which the PCB3according to the another example embodiment is cut with a plane parallel to an xy plane so that a core wire formed in a region sandwiched between the front-surface GND9and the back-surface GND11is visible.FIG.29Cis an enlarged view of a cross section, near the core wire10, of the PCB3according to the another example embodiment that is cut with a plane parallel to the xz plane including the cutting line N-NN shown inFIG.29A. The cross-sectional view shown inFIG.29Bis a view in which the PCB3is cut along a plane parallel to the xy plane including a cutting line O-OO shown inFIG.29C.FIG.29Dis a bottom view showing the structure of the PCB3according to the another example embodiment.FIG.29Eis a perspective view of the PCB3according to the another example embodiment.FIG.29Fis an enlarged view of the PCB3according to a modification of the another example embodiment near the through hole4.

As shown inFIG.29C, the PCB3has a structure in which the front-surface GND9is formed on one surface of the plate-shaped dielectric8extending parallel to the xy plane, for example. The PCB3has a structure in which the back-surface GND11is formed on the other surface of the dielectric8. The PCB3has a structure in which the core wire10is formed inside the dielectric8, that is, in a region sandwiched between the front-surface GND9and the back-surface GND11. A line having such a structure is generally called a stripline. As shown inFIG.29A, the upper surface of the PCB3is provided with the front-surface GND9, an input/output pad15, and a bonding pad16. The input/output pad15is a pad that connects the core wire10of the PCB3to an external measuring instrument or the like and is used for signal input/output. The bonding pad16is a pad for connecting the core wire10of the PCB3and the pad of the chip7with the bonding wire13or the like. The input/output pad15and the bonding pad16formed on the upper surface of the PCB3are electrically connected to the core wire10formed in the region sandwiched between the front-surface GND9and the back-surface GND11. In the top view ofFIG.29A, the core wire10is invisible because it is hidden by the front-surface GND9.FIG.29Bshows a cross-sectional view cut with a plane parallel to the xy plane near the core wire10. InFIGS.29A to29F, four striplines are formed on the PCB3. However, the number of striplines formed on the PCB3is not particularly limited, and may be any number. As shown inFIGS.29B,29C, and29E, the PCB3is provided with a plurality of the through holes12. These through holes12penetrate the dielectric8and electrically connect the front-surface GND9and the back-surface GND11. The through hole4is provided near the center of the PCB3.

In the first to third example embodiments and the modifications of the first to third example embodiments, the same effects as those of the first to third example embodiments and the modifications of the first to third example embodiments can be achieved even if the PCB3having three or more metal layers as shown inFIGS.29A to29Fis used.

In the first to third example embodiments and the modifications of the first to third example embodiments, as a mounting method of the chip7of the superconducting quantum circuit, the configuration in which the chip7is directly placed on the metal base2has been described, but the mounting method is not limited to this. For example, also in a case of a mounting form in which a resin material such as varnish is applied onto the metal base2and then the chip7is placed on the resin material such as varnish, it is possible to achieve the effect of the example embodiments, that is, the effect that the resonance frequency of the chip mode can be increased.

In the first to third example embodiments and the modifications of the first to fifth example embodiments, the configuration in which the PCB3is directly placed on the metal base2has been described as the configuration of the sample holder1. The effect of the example embodiments can also be achieved by the sample holder1having a configuration in which a sheet of metal such as indium (In) is placed on the metal base2and the PCB3is placed on the sheet of metal such as In. By sandwiching a sheet of soft metal such as In between the base2and the PCB3, it is possible to make a gap less likely to occur between the back-surface GND11of the PCB3and the base2. This sometimes improves high-frequency characteristics of the sample holder1. Specifically, if there is a gap between the PCB3and the base2, the gap can form a new cavity resonator and cause resonance when a signal of a specific frequency is input to the chip7. Therefore, it is preferable that no gap is generated between the back-surface GND11of the PCB3and the base2.

In the first to third example embodiments and the modifications of the first to third example embodiments, the configuration in which the PCB3is placed on the metal base2has been described as the configuration of the sample holder1. A metal lid may be placed on the PCB3. The effect of the example embodiments can also be achieved even if the lid is placed. In such the sample holder1, the metal lid is in electrical contact with the front-surface GND9of the PCB3. However, the lid does not come into contact with the core wire10of the PCB3and the chip7. This is to prevent the core wire10of the PCB3and the circuit and wiring of the chip7from coming into contact with the GND. For the same reason as described above, it is preferable that no gap is generated between the lid and the front-surface GND9of the PCB3, and therefore a sheet such as In may be sandwiched between the lid and the front-surface GND9of the PCB3.

In the first to third example embodiments and the modifications of the first to third example embodiments, the case where the base2is a rectangular parallelepiped or a cube has been described as the shape of the sample holder1, but the effect of the present disclosure can also be achieved if the base2has another shape such as a cylinder. Similarly, the effect of the example embodiments can also be achieved even if the shape of the PCB3is also a rectangular shape and a square shape but other shapes such as a circular shape.

Fourth Example Embodiment

In the fourth example embodiment, the basic configuration of the content described in the first to third example embodiments will be described. Here, the fourth example embodiment will be described with reference toFIG.10Aused in the first example embodiment.

As shown inFIG.10A, the sample holder1includes the base2and the PCB3in contact with the base2. The PCB3has the through hole4. In the PCB3, the base2has the cavity5in at least a part below the through hole4. The shape of the cavity5is not particularly limited. For example, the bottom surface of the cavity5may be a flat surface or may be a surface other than a flat surface. The side surface of the cavity5may be a flat surface or may be a surface other than a flat surface.

The cavity5has a support structure that supports the surface of the chip7and is conducted to the base2. At least a part of the section supporting the chip7in the support structure is not parallel to the surface of the chip. The surface of the chip here is the back surface of the chip opposite to the circuit surface of the chip. The support structure is not particularly limited. InFIG.10A, the support structure is the conductor columns6arranged at the four corners of the cavity5. At least a part of the upper surface of the column6is not parallel to the upper surface of the base2. When the support structure is the column6, the shape is not limited to the shape inFIG.10A. As inFIGS.13A and13Cused in the description of another example of the first example embodiment, since the upper section61of the column6has a triangular pyramid shape, the upper section61need not be parallel to the back surface of the chip7. For example, as inFIG.15Aused in the description of the modification of the first example embodiment, at least a part of the upper surface of the column6need not be parallel to the back surface of the chip7, and at least a part of the upper surface of the column6may be parallel to the back surface of the chip7.

The support structure may be achieved by the shape of the cavity5. Specifically, as described in the second example embodiment and the third example embodiment, the shape of the cavity5may be a shape partially including a frustum. Due to this, when the chip7is mounted on the sample holder1, at least a part of the front surface opposing the back surface of the chip7of the surface of the base2forming the cavity5is not parallel to the back surface of the chip7.

In the fourth example embodiment, the sample holder1has the cavity5in the base2, has the support structure that supports the back surface of the chip in the cavity5, and at least a part of the section that supports the chip7in the support structure is not parallel to the surface of the chip. This makes it possible to further increase the resonance frequency of the chip mode.

It has been required to cause the resonance frequency of resonance that occurs by supplying a signal of a specific frequency to a chip in a case where the chip is mounted on the sample holder, higher than a technique described in B. Lienhard, et al., “Microwave Packaging for Superconducting Qubits,” arXiv: 1906.05425v1 [quant-ph] 12 Jun. 2019.

As above, in a case where a chip is mounted on the sample holder1according to the example embodiments, the resonance frequency of resonance that occurs when a signal of a specific frequency is input to the chip is further increased.

The description of the sample holder1according to the example embodiments is finished. The superconducting quantum computer according to the example embodiments includes the sample holder1according to the example embodiments and the chip on which the superconducting quantum circuit is formed is disposed in the sample holder1.

The previous description of embodiments is provided to enable a person skilled in the art to make and use the present disclosure. Moreover, various modifications to these example embodiments will be readily apparent to those skilled in the art, and the generic principles and specific examples defined herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present disclosure is not intended to be limited to the example embodiments described herein but is to be accorded the widest scope as defined by the limitations of the claims and equivalents.

Further, it is noted that the inventor's intent is to retain all equivalents of the claimed disclosure even if the claims are amended during prosecution.

Supplementary Note

Some or all of the above example embodiments can also be described as the following supplementary notes. However, some or all of the above example embodiments are not limited to the following.

(Supplementary Note 1)

A sample holder including:a base including a support structure; andPCB in contact with the base; the PCB including a through hole; whereinat least a part of the base below the through hole has a cavity,a support structure that supports a surface of a chip and is electrically connected to the base,the support structure is disposed in the cavity, andat least a part of a section of the support structure that supports the chip is not parallel to the surface of the chip.
(Supplementary Note 2)

The sample holder according to Supplementary Note 1, in whichthe support structure is a conductor column.
(Supplementary Note 3)

The sample holder according to Supplementary Note 2, in whichthe column has a shape in which a frustum and a prism are combined,a bottom surface of the frustum having a smaller area is a side of the through hole, anda bottom surface of the frustum having a larger area and an upper bottom surface of the prism have a same shape and are connected.
(Supplementary Note 4)

The sample holder according to Supplementary Note 2 or 3, in whichthe support structure is a plurality of columns provided in the cavity.
(Supplementary Note 5)

The sample holder according to Supplementary Note 4, in whichthe plurality of columns are provided at four corners of the cavity.
(Supplementary Note 6)

The sample holder according to Supplementary Note 1, in whichthe cavity has a frustum shape, anda bottom surface of the frustum having a larger area is the through hole side.
(Supplementary Note 7)

The sample holder according to Supplementary Note 6, in whichthe cavity has a shape in which the frustum and a column are combined, anda bottom surface of the frustum having a smaller area and an upper bottom surface of the column have a same shape and are connected.
(Supplementary Note 8)

The sample holder according to Note 7, whereinthe prism is a quadrangular prism, andthe frustum is a quadrangular prismoid.
(Supplementary Note 9)

The sample holder according to any of Supplementary Notes 6 to 8, in whichthe cavity is further provided with a conductor prism, andan upper bottom surface of the conductor prism is parallel to an upper surface of the base.
(Supplementary Note 10)

The sample holder according to Supplementary Note 8, in whichthe prism is provided at four corners of the cavity.
(Supplementary Note 11)

The sample holder according to Supplementary Note 1, in whichthe cavity has a pyramid shape, anda bottom surface of the pyramid is on the through hole side.
(Supplementary Note 12)

The sample holder according to any of Supplementary Notes 1 to 11, in whichthe support structure is made of metal or a mixture containing metal.
(Supplementary Note 13)

The sample holder according to Supplementary Notes 1 to 12, in whichthe base is made of metal.
(Supplementary Note 14)

The sample holder according to any of Supplementary Notes 1 to 13, in whichthe chip is disposed in the through hole.
(Supplementary Note 15)

The sample holder according to any of Supplementary Notes 1 to 14, in whichthe PCB includes a dielectric, a front-surface ground formed on a front surface of the dielectric, and a back-surface ground formed on a back surface of the dielectric.
(Supplementary Note 16)

The sample holder according to any of Supplementary Notes 1 to 15, in whichthe PCB has a core wire of a coplanar waveguide on the front surface of the dielectric.
(Supplementary Note 17)

The sample holder according to any of Supplementary Notes 1 to 15, in whichthe PCB further includes a core wire in the dielectric in a region sandwiched between the front-surface ground and the back-surface ground.
(Supplementary Note 18)

A superconducting quantum computer including:a sample holder; anda chip on which a superconducting quantum circuit is formed, the chip being disposed in the sample holder, whereinthe sample holder including:a base including a support structure; anda PCB in contact with the base, the PCB including a through hole; whereinat least a part of the base below the through hole has a cavity,the support structure that supports a surface of a chip and is electrically connected to the base,the support structure is disposed in the cavity andat least a part of a section of the support structure that supports the chip is not parallel to the surface of the chip.