Patent ID: 12244282

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, parameter values in the description that follows may vary depending on a given technology node. As another example, parameter values for a given technology node may vary depending on a given application or operating scenario. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

In order to compensate for impedance changes caused by PVT variations, a calibration circuit may perform ZQ calibration upon an impedance of an output driver with the use of an external resistor connected to a ZQ pad. The calibration circuit usually utilizes a closed loop calibration mechanism, in which an output of the output driver is fed back for determining an impedance control code. However, the calibration circuit with closed loop control has a complicated structure and exhibits a slower response.

The present disclosure describes exemplary impedance calibration circuits, each of which can adjust an impedance at an output terminal to fall within a tolerance range of a predetermined impedance value based on the detection of PVT variations. The exemplary impedance calibration circuit can utilize a detection path to track impedance characteristics of one or more conduction paths connected to the output terminal. The impedance characteristics of the one or more conduction paths are affected by PVT variations. For example, the detection path used for tracking the impedance characteristics can be connected to an impedance element that is not be subjected to PVT variations. By applying a supply voltage to the impedance element through the detection path, the exemplary impedance calibration circuit can generate a voltage that is indicative of the effect of PVT variations on the impedance characteristics of the one or more conduction paths. In addition, the exemplary impedance calibration circuit can compare the voltage with a plurality of reference voltages to determine the amount of impedance adjustment, which is used to compensate for impedance changes caused by PVT variations. The proposed impedance compensation scheme can be applied to an impedance calibration circuit employing open loop control or closed loop control. Further description is provided below.

FIG.1is a block diagram illustrating an exemplary impedance calibration circuit in accordance with some embodiments of the present disclosure. The impedance calibration circuit100can be employed in memory interfaces for realizing impedance matching between a memory controller and a memory device. The memory interfaces may include, but are not limited to, high speed memory interfaces such as an Open NAND Flash Interface (ONFI). In the present embodiment, the impedance calibration circuit100can utilize open loop control to perform high resolution ZQ calibration.

The impedance calibration circuit100includes, but is not limited to, a plurality of input/output (I/O) cells110[0]-110[p] and a calibration cell120, where p is a positive integer. Each I/O cell may be regarded as a variable impedance circuit, which is configured to adjust an impedance thereof according to a calibration code CC. For example, when the I/O cells110[0]-110[p] operate at a transmitter side, each I/O cell can be configured to adjust an output impedance thereof according to the calibration code CC. As another example, when the I/O cells110[0]-110[p] operate at a receiver side, each I/O cell can be configured to adjust an input impedance thereof according to the calibration code CC. In the present embodiment, the calibration code CC can be implemented using an (m+1)-bit digital code including trim bits TM[0]-TM[m], where m is a positive integer. One or more conduction paths within each I/O cell can be enabled/disabled according to the trim bits TM[0]-TM[m].

The calibration cell120, also referred to as a ZQ cell, is configured to provide the calibration code CC by detecting the effect of PVT variations on impedance characteristics of the I/O cells110[0]-110[p]. In the present embodiment, the calibration cell120is coupled to a reference terminal (or a reference pad) PDREF, which can be connected to an impedance element RZQsuch as an external impedance element. The impedance element RZQis coupled to a node NR which may have a reference potential. The impedance element RZQcan be a high precision resistor, or a resistor located outside the impedance calibration circuit100. For example, the impedance elements of the I/O cells110[0]-110[p] can be on-chip resistors, while the impedance element RZQcan be an off-chip resistor. With the use of the impedance element RZQ, the calibration cell120can generate an input voltage VINat the reference terminal PDREFin response to the detection of PVT variations. The input voltage VINcan be indicative of the effect of PVT variations on the impedance characteristics of the I/O cells110[0]-110[p]. The calibration cell120can generate the calibration code CC according to the input voltage VIN.

In operation, the calibration cell120can be clocked by a clock signal CLK_C to perform ZQ calibration. The calibration cell120can enter a calibration mode in response to a mode selection signal MS. In the calibration mode, the calibration cell120can be reset when a reset signal ZQ_R is asserted. For example, a code value of the calibration code CC can be reset in response to the reset signal ZQ_R. Next, when an enable signal ZQ_E is asserted, the calibration cell120can detect the effect of PVT variations on impedance characteristics of the I/O cells110[0]-110[p], thereby generating the input voltage VIN. The calibration cell120can update the code value of the calibration code CC according to the input voltage VIN. After a period of time, the calibration cell120can issue an output signal ZQ_D to indicate that the ZQ calibration is done. Each of the I/O cells110[0]-110[p] can adjust an impedance thereof according to the calibration code CC outputted from the calibration cell120.

For illustrative purposes, the proposed impedance calibration scheme is described below with reference to a single I/O cell. Those skilled in the art should appreciate that the proposed impedance calibration scheme described below can be applied to an impedance calibration circuit having multiple I/O cells without departing from the scope of the present disclosure.

FIG.2Aillustrates an implementation of the impedance calibration circuit100shown inFIG.1in accordance with some embodiments of the present disclosure. The impedance calibration circuit200A includes, but is not limited to, a variable impedance circuit210and a calibration cell220. The variable impedance circuit210can serve as an embodiment of one of the I/O cells110[0]-110[p] shown inFIG.1. The calibration cell220can serve as an embodiment of the calibration cell120shown inFIG.1.

The variable impedance circuit210includes, but is not limited to, a plurality of conduction paths CP[0]-CP[x] connected in parallel between a supply terminal TSP and an output terminal PDOUT, where x is a positive integer. The supply terminal TSP is coupled to a supply voltage VSPX. The variable impedance circuit210can be configured to enable at least one of the conduction paths CP[0]-CP[x] to provide an impedance ZIOat the output terminal PDOUT. In addition, the variable impedance circuit210can be configured to adjust the impedance ZIOby enabling/disabling one or more of the conduction paths CP[0]-CP[x] according to the calibration code CC. For example, the impedance ZIOmay be the equivalent impedance presented between the supply terminal TSP and the output terminal PDOUT. The impedance ZIOwill decrease when the number of enabled conduction paths increases. The impedance ZIOwill increase when the number of disabled conduction paths increases.

In the present embodiment, respective impedances of two or more of the conduction paths CP[0]-CP[x] may be different from each other. An impedance of a conduction path as used herein refers to an impedance presented by the conduction path in a conductive state. The amount of impedance adjustment may vary with the impedance of each conduction path that is enabled/disabled according to the calibration code CC. For example, the conduction paths CP[1] and CP[2] may have different impedances. In some cases where the conduction path CP[0] is enabled and the remaining conduction paths are disabled, the variable impedance circuit210may provide the impedance ZIOof a certain value. When the conduction path CP[1] is enabled and the conduction path CP[2] is disabled, the variable impedance circuit210may adjust the impedance ZIOby a first calibration amount. The impedance ZIOcan be contributed by the conduction paths CP[0] and CP[1]. When the conduction path CP[1] is disabled and the conduction path CP[2] is enabled, the variable impedance circuit210may adjust the impedance ZIOby a second calibration amount. The impedance ZIOcan be contributed by the conduction paths CP[0] and CP[2]. Note that the second calibration amount is different from the first calibration amount since the conduction path CP[2] has an impedance different from that of the conduction path CP[1].

The calibration cell220includes, but is not limited to, a detection circuit230and a control circuit240. The detection circuit230is configured to detect a change in impedance of the conduction paths CP[0]-CP[x] by applying a supply voltage VSPYto the reference terminal PDREFthrough a detection path CPD, and accordingly generate the input voltage VINat the reference terminal PDREF. An electric potential of the supply voltage VSPYis equal to, or substantially equal to, an electric potential of the supply voltage VSPXcoupled to the supply terminal TSP. The detection path CPDcan be arranged for tracking an impedance characteristic of at least one of the conduction paths CP[0]-CP[x]. By way of example but not limitation, the detection path CPDmay have an impedance ZDindicative of an impedance of at least one conduction path of the variable impedance circuit210. The impedance ZDcan represent an impedance presented by the detection path CPDin a conductive state. The impedance ZDcan change with variations in impedance of the at least one conduction path.

In some examples, the impedance ZDcan be indicative of an equivalent impedance of multiple conduction paths in parallel included in the variable impedance circuit210. The detection path CPDmay be, but is not limited to, a replica of an equivalent circuit of the multiple conduction paths in parallel. In some other examples, the impedance ZDcan be indicative of an impedance of a single conduction path included in the variable impedance circuit210. The detection path CPDmay be, but is not limited to, a replica of the single conduction path.

Note that the impedance ZREFof the impedance element RZQcan be unaffected by variations in impedance of the at least one conduction path. A change in the input voltage VINmay mainly result from a change in impedance of the detection path CPD, and therefore can reflect variations in impedance of the at least one conduction path.

The control circuit240, coupled to the variable impedance circuit210and the detection circuit230, is configured to compare the input voltage VINwith a plurality of reference voltages {VR} to generate the calibration code CC. For example, respective voltage levels of the reference voltages {VR} may correspond to different amounts of change in the impedance of the at least one conduction path. Different code values of the calibration code CC may correspond to different calibration amounts by which the impedance ZIOwould be adjusted.

In the embodiment shown inFIG.2A, the supply voltage VSPXsupplied to the supply terminal TSP may have a reference potential which can be a positive electric potential, a negative electric potential or a ground potential. By coupling the supply voltage VSPY(having an electric potential equal to that of a supply voltage coupled to the supply terminal TSP) to the reference terminal PDREF, the calibration cell220can be configured to detect the effect of PVT variations on an impedance characteristic of one or more conduction paths which are coupled to a positive electric potential, a negative electric potential or a ground potential.

For example, referring toFIG.2B, the impedance calibration circuit200B can be configured to perform ZQ calibration by detecting the effect of PVT variations on the conduction paths CP[0]-CP[x] coupled to a supply voltage VDDIO. The detection circuit230can be configured to apply the supply voltage VDDIO (i.e. a supply voltage coupled to the supply terminal TSP) to the reference terminal PDREFto thereby detect a change in impedance of the conduction paths CP[0]-CP[x]. Each of the supply voltages VSPXand VSPYshown inFIG.2Acan be implemented using the supply voltage VDDIO, which can be a positive power supply voltage. In addition, the impedance element RZQis coupled to a supply voltage VSS through the node NR. The supply voltage VSS can have a voltage potential lower than that of the supply voltage VDDIO. In the present embodiment, the supply voltage VSS may be, but is not limited to, a ground voltage or a negative power supply voltage.

As another example, referring toFIG.2C, the impedance calibration circuit200C can be configured to perform ZQ calibration by detecting the effect of PVT variations on the conduction paths CP[0]-CP[x] coupled to a supply voltage VSSIO, which may be a ground voltage or a negative power supply voltage. The detection circuit230can be configured to apply the supply voltage VSS (having an electric potential equal to that of the supply voltage VSSIO) to the reference terminal PDREFto thereby detect a change in impedance of the conduction paths CP[0]-CP[x]. The supply voltages VSSIO and VSS can serve as embodiments of the supply voltages VSPXand VSPYshown inFIG.2A, respectively. The supply voltages VSSIO and VSS can have substantially the same electric potential, but may be electrically isolated from each other. In addition, the impedance element RZQis coupled to the supply voltage VDDIO through the node NR. The supply voltage VDDIO can have a voltage potential higher than that of the supply voltage VSS. In the present embodiment, the supply voltage VDDIO may be, but is not limited to, a positive power supply voltage.

Note that in some embodiments, the detection circuit230can be configured to apply the supply voltage VSSIO (i.e. a supply voltage coupled to the supply terminal TSP) to the reference terminal PDREFto thereby detect a change in impedance of the conduction paths CP[0]-CP[x] without departing from the scope of the present disclosure.

To facilitate understanding of the present disclosure, some embodiments are given as follows for further description of the proposed impedance calibration scheme. Those skilled in the art should appreciate that other embodiments employing the calibration architecture shown inFIG.2A/2B/2C are also within the contemplated scope of the present disclosure.

FIG.3illustrates an implementation of the variable impedance circuit210shown inFIG.2Bin accordance with some embodiments of the present disclosure.FIG.4illustrates an implementation of the calibration cell220shown inFIG.2Bin accordance with some embodiments of the present disclosure. The calibration cell320shown inFIG.4is operable with the variable impedance circuit310shown inFIG.3to realize an open loop calibration mechanism.

Referring firstly toFIG.3, the variable impedance circuit310includes, but is not limited to, a driver circuit312and a plurality of controllers316P and316N. The driver circuit312is controlled by the drive signals DP[0]-DP[2] and DN[0]-DN[2] to adjust the equivalent impedance at the output terminal PDOUT. The driver circuit312may include a plurality of conduction paths PP[0]-PP[2] connected in parallel between the supply terminal TD and the output terminal PDOUT. The conduction paths PP[0]-PP[2] may represent an embodiment of the conduction paths CP[0]-CP[x] shown inFIG.2B. The conduction paths PP[0]-PP[2] are controlled by the drive signals DP[0]-DP[2], respectively. By enabling one or more of the conduction paths PP[0]-PP[2] according to the drive signals DP[0]-DP[2], the driver circuit312can adjust the equivalent impedance presented between the supply terminal TD and the output terminal PDOUT, i.e. the impedance ZIO.

The driver circuit312may further include a plurality of conduction paths PN[0]-PN[2] connected in parallel between the supply terminal TS and the output terminal PDOUT. The supply terminal TS can be coupled to a supply voltage VSSIO having a voltage potential lower than that of the supply voltage VDDIO. The supply voltage VSSIO may be, but is not limited to, a ground voltage. The conduction paths PN[0]-PN[2] are controlled by the drive signals DN[0]-DN[2], respectively. The driver circuit312can enable one or more of the conduction paths PN[0]-PN[2] according to the drive signals DN[0]-DN[2], thereby adjusting the equivalent impedance presented between the supply terminal TS and the output terminal PDOUT.

In the present embodiment, the impedance of the conduction path PP[i] can be equal to or substantially equal to the impedance of the conduction path PN[i], where i=0, 1, 2. The conduction path PP[i] may include a switch MP[i] and an impedance element RP[i] connected in series. The switch MP[i], controlled by the drive signals DP[i], can be implemented using a p-channel transistor. When the switch MP[i] is turned on, the conduction path PP[i] is enabled, and the impedance of the impedance element RP[i] can serve as the impedance of the conduction path PP[i]. Similarly, the conduction path PN[i] may include a switch MN[i] and an impedance element RN[i] connected in series. The switch MN[i], controlled by the drive signals DN[i], can be implemented using an n-channel transistor. When the switch MN[i] is turned on, the conduction path PN[i] is enabled, and the impedance of the impedance element RN[i] can serve as the impedance of the conduction path PN[i].

The controller316P is configured to generate the drive signals DP[1] and DP[2] according to the trim bit TM[0], the trim bit TM[1] and the drive signal DP[0]. The controller316N is configured to generate the drive signals DN[1] and DN[2] according to the trim bit TM[0], the trim bit TM[1] and the drive signal DP[0]. The trim bits TM[0] and TM[1] can serve as an embodiment of the calibration code CC shown inFIG.2B. In the present embodiment, the driver signals DP[0] and DN[0] can be provided from a pre-driver of the variable impedance circuit310(not shown inFIG.3). In addition, the controller316P/316N is coupled to the supply voltage VSS. The supply voltages VSS and VSSIO can have substantially the same electric potential, but may be electrically isolated from each other.

Referring toFIG.4and also toFIG.3, the calibration cell320operable with the variable impedance circuit310may include a detection circuit330and a control circuit340, which can represent implementations of the detection circuit230and the control circuit240shown inFIG.2Brespectively. The detection circuit330may utilize the detection path CPDto detect a change in impedance of the conduction paths PP[0]-PP[2]. In the present embodiment, the impedance ZDcan be indicative of an equivalent impedance ZC1of the conduction paths PP[0] and PP[1] in parallel. The detection path CPDmay include a switch MR and an impedance element RREFconnected in series, which can be used to track impedance characteristics of the conduction paths PP[0] and PP[1] in parallel. For example, the switch MR can be implemented using a p-channel transistor, which can be formed based on the size of the p-channel transistor used for implementing the switch MP[0]/MP[1]. The impedance element RREFcan be formed based on the dimensions of the impedance elements RP[0] and RP[1].

The switch MR can be controlled by the enable signal ZQ_E. When the switch MR is turned on, the detection circuit330can apply the supply voltage VDDIO to the impedance element RREF. The impedance element RREFand the impedance element RZQcan serve as a voltage divider for generate the input voltage VINat the reference terminal PDREF. As the impedance ZREFof the impedance element RZQis substantially unaffected by PVT variations, the input voltage VINcan vary with variations in impedance of the impedance element RREF. In addition, as the impedance of the impedance element RREFcan vary with impedance variations in the parallel combination of the conduction paths PP[0] and PP[1], the input voltage VINcan reflect a change in the equivalent impedance ZC1.

For example, when no or negligible PVT variation occurs, the equivalent impedance ZC1may be equal to a nominal impedance, which is equal to the impedance ZREF. The impedance element RREFcan have an impedance equal to the nominal impedance. When PVT variations cause the equivalent impedance ZC1to be less than the nominal impedance, the impedance element RREFwould have an impedance less the nominal impedance, which results in an increase in the input voltage VIN. When PVT variations cause the equivalent impedance ZC1to be greater than the nominal impedance, the impedance element RREFwould have an impedance greater the nominal impedance, which results in a decrease in the input voltage VIN.

In the example ofFIG.4, the detection circuit330may further include a resistor-capacitor (RC) filter332for noise reduction. In other words, the RC filter332can reduce or eliminate the noise component of the input voltage VINto thereby generate a filtered version of the input voltage VIN, i.e. the input voltage VINF.

The control circuit340may include a comparison circuit370, a processing circuit380and a frequency divider390. The comparison circuit370is configured to compare a filtered version of the input voltage VIN(i.e. the input voltage VINF) with a plurality of reference voltages VH0and VL0to determine a voltage range in which the input voltage VIN/VINFfalls. The reference voltage VH0can be greater than the reference voltage VL0. For example, the comparison circuit370may include a plurality of comparators376H and376L. The comparator376H is configured to compare the input voltage VINFwith the reference voltage VH0to generate a comparison result CRH, which can indicate whether the input voltage VIN/VINFis greater than the reference voltage VH0. The comparator376L is configured to compare the input voltage VINFwith the reference voltage VL0to generate a comparison result CRL, which can indicate whether the input voltage VIN/VINFis greater than the reference voltage VL0.

The processing circuit380is configured to process the comparison results CRH and CRL to generate the calibration code CC, i.e. the trim bits TM[0] and TM[1]. For example, the processing circuit380may include a plurality of registers384[0]-384[2] and a plurality of buffers386[0]-386[2]. Each of the registers384[0]-384[2] can be triggered by a clock signal CLK_D. The register384[0] is configured to store and output the comparison result CRH. The buffer386[0] is configured to output the trim bit TM[0] according to an output of the register384[0]. Similarly, the register384[1] is configured to store and output the comparison result CRL. The buffer386[1] is configured to output the trim bit TM[1] according to an output of the register384[1]. In addition, the register384[2] is configured to receive the supply voltage VDD, and assert an output signal ZQ_D0in response to the clock signal CLK_D. The buffer386[2] is configured to buffer the output signal ZQ_D0to generate the output signal ZQ_D. In the present embodiment, each of the buffers386[0]-386[2] can be implemented using two inverters connected in series.

The frequency divider390is configured to divide the frequency of the clock signal CLK_C by a division factor of FDIVto generate the clock signal CLK_D, where FDIVis a real number. As a result, each of the registers384[0]-384[2] can be triggered once every FDIVclock cycles of the clock signal CLK_C. By way of example but not limitation, FDIVmay be equal to 210. The register384[2] can assert the output signal ZQ_D0after 210clock cycles of the clock signal CLK_C has elapsed since assertion of the enable signal ZQ_E. Additionally, the output signal ZQ_D can be asserted to indicate that the ZQ calibration is done.

FIG.5illustrates an implementation of the reference voltages VH0and VL0shown inFIG.4in accordance with some embodiments of the present disclosure. In the present embodiment, the input voltage VINis substantially equal to a reference voltage VREFwhen the equivalent impedance ZC1shown inFIG.3is equal to a nominal impedance. The input voltage VINwould reach the reference voltage VH0when the equivalent impedance ZC1shown inFIG.3falls below the nominal impedance by P % of the nominal impedance. The input voltage VINwould reach the reference voltage VL0when the equivalent impedance ZC1shown inFIG.3exceeds the nominal impedance by Q % of the nominal impedance. In other words, the reference voltage VREFmay correspond to the nominal impedance. The reference voltage VH0may correspond to a P % reduction in impedance compared to the nominal impedance. The reference voltage VL0may correspond to a Q % increase in impedance compared to the nominal impedance. In the example ofFIG.5, the reference voltages VH0and VL0can be set to appropriate levels such that both P and Q can be 12. However, those skilled in the art can appreciate that the reference voltage VH0/VL can be set to any appropriate level without departing from the scope of the present disclosure. In other words, P and/or Q may vary depending on design requirements.

Referring toFIG.3,FIG.4andFIG.5, in operation, the switch MR is turned on in response to assertion of the enable signal ZQ_E. The supply voltage VDDIO is applied to the impedance element RREFto create the input voltage VINat the reference terminal PDREF. The comparator376H can compare a filtered version of the input voltage VIN(the input voltage VINF) with the reference voltage VH0to determine whether the input voltage VINis greater than the reference voltage VH0. The comparator376L can compare a filtered version of the input voltage VIN(the input voltage VINF) with the reference voltage VL0to determine whether the input voltage VINis greater than the reference voltage VL0. The processing circuit380can generate the calibration code CC according to the comparison results CRH and CRL. With the use of the calibration code CC, the variable impedance circuit310can provide the impedance ZIOthat falls within a predetermined impedance range.

When the input voltage VINis greater than the reference voltage VL0and less than the reference voltage VH0, the equivalent impedance ZC1may lie within a tolerance range of a nominal impedance, e.g. a range of plus or minus 12% of the impedance ZREF. The variable impedance circuit310can enable the conduction paths PP[0] and PP[1] and disable the conduction path PP[2]. In other words, the switches MP[0] and MP[1] are turned on, and the switch MP[2] is turned off. As a result, the equivalent impedance ZC1of the conduction paths PP[0] and PP[1] in parallel can serve as the impedance ZIO, which lies within a range of plus or minus 12% of the impedance ZREF.

When the input voltage VINis less than the reference voltage VL0, the equivalent impedance ZC1may exceed the impedance ZREFby more than 12% of the impedance ZREF. To compensate for the increase in impedance caused by PVT variations, the variable impedance circuit310can enable the conduction path PP[2] to adjust an impedance presented between the supply terminal TD and the output terminal PDOUT. For example, the switches MP[0]-MP[2] are turned on to enable the conduction paths PP[0]-PP[2], respectively. The resulting impedance ZIOcan exhibit a decrease, such as 18% of the impedance ZREF, compared to an impedance contributed by the conduction paths PP[0] and PP[1] in parallel. In other words, the variable impedance circuit310can enable the conduction path PP[2] to compensate for an increase in impedance, such as 18% of the impedance ZREF.

When the input voltage VINis greater than the reference voltage VH0, the equivalent impedance ZC1may fall below the impedance ZREFby more than 12% of the impedance ZREF. To compensate for the reduction in impedance caused by PVT variations, the variable impedance circuit310can disable the conduction path PP[1] to adjust an impedance presented between the supply terminal TD and the output terminal PDOUT. For example, the switches MP[1] and MP[2] are turned off to disable the conduction paths PP[1] and PP[2]. The switch MP[0] is turned on to enable the conduction path PP[0]. The resulting impedance ZIOcan exhibit an increase, such as 18% of the impedance ZREF, compared to an impedance contributed by the conduction paths PP[0] and PP[1] in parallel. In other words, the variable impedance circuit310can disable the conduction path PP[1] to compensate for a reduction in impedance, such as 18% of the impedance ZREF.

In the present embodiment, the impedance of the conduction path PP[i] can be equal to or substantially equal to the impedance of the conduction path PN[i], where i=0, 1, 2. For example, the impedance of the impedance element RP[i] can be substantially equal to the impedance of the impedance element RN[i]. The variable impedance circuit310can enable the conduction path PN[0], and disable the conduction paths PN[1] and PN[2] to provide an impedance presented between the supply terminal TS and the output terminal PDOUT, which may exhibit an 18% increase of the impedance ZREFcompared to an impedance contributed by the conduction paths PN[0] and PN[1] in parallel. Alternatively, the variable impedance circuit310can enable each of the conduction paths PN[0]-PN[2] to provide an impedance presented between the supply terminal TS and the output terminal PDOUT, which may exhibit a 18% decrease of the impedance ZREFcompared to an impedance contributed by the conduction paths PN[0] and PN[1] in parallel. As those skilled in the art can appreciate the calibration operation associated with the conduction paths PN[0]-PN[2] after reading the above paragraphs directed toFIG.1toFIG.5, similar description is omitted here for brevity.

FIG.6illustrates another implementation of the variable impedance circuit210shown inFIG.2Bin accordance with some embodiments of the present disclosure.FIG.7illustrates another implementation of the calibration cell220shown inFIG.2Bin accordance with some embodiments of the present disclosure. The calibration cell620shown inFIG.7can be operable with the variable impedance circuit410shown inFIG.3to realize an open loop calibration mechanism.

Referring firstly toFIG.6, the variable impedance circuit610includes, but is not limited to, a driver circuit612, a decoder614, and a plurality of controllers616P and616N. The driver circuit612is controlled by the drive signals DP[0]-DP[4] and DN[0]-DN [4] to adjust the equivalent impedance at the output terminal PDOUT. The driver circuit612may include a plurality of conduction paths PP[0]-PP[4] connected in parallel between the supply terminal TD and the output terminal PDOUT. The conduction paths PP[0]-PP[4] may represent an embodiment of the conduction paths CP[0]-CP[x] shown inFIG.2B. The conduction paths PP[0]-PP[4] are controlled by the drive signals DP[0]-DP [4], respectively. By enabling one or more of the conduction paths PP[0]-PP[4] according to the drive signals DP[0]-DP[4], the driver circuit612can adjust the equivalent impedance presented between the supply terminal TD and the output terminal PDOUT, i.e. the impedance ZIO.

The driver circuit612may further include a plurality of conduction paths PN[0]-PN[4] connected in parallel between the supply terminal TS and the output terminal PDOUT. The conduction paths PN[0]-PN[4] are controlled by the drive signals DN[0]-DN[4], respectively. The driver circuit612can enable one or more of the conduction paths PN[0]-PN[4] according to the drive signals DN[0]-DN[4], thereby adjusting the equivalent impedance presented between the supply terminal TS and the output terminal PDOUT.

In the present embodiment, the impedance of the conduction path PP[i] can be equal to or substantially equal to the impedance of the conduction path PN[i], where i=0 to 4. The conduction path PP[i] may include a switch MP[i] and an impedance element RP[i] connected in series. The switch MP[i], controlled by the drive signals DP[i], can be implemented using a p-channel transistor. When the switch MP[i] is turned on, the conduction path PP[i] is enabled, and the impedance of the impedance element RP[i] can serve as the impedance of the conduction path PP[i]. Similarly, the conduction path PN[i] may include a switch MN[i] and an impedance element RN[i] connected in series. The switch MN[i], controlled by the drive signals DN[i], can be implemented using an n-channel transistor. When the switch MN[i] is turned on, the conduction path PN[i] is enabled, and the impedance of the impedance element RN[i] can serve as the impedance of the conduction path PN[i]. The impedance of the impedance element RP[i] can be substantially equal to that of the impedance of the impedance element RN[i].

The controller616P can be configured to generate the drive signals DP[1]-DP[4] according to a control code CT and the drive signal DP[0] used for controlling the conduction path PP[0]. By way of example but not limitation, the control code CT includes four control bits CT[1]-CT[4]. The controller616P may determine a logic state of the drive signal DP[j] according to the control bit CT[j], where j=1 to 4. In addition, the controller616P may determine a voltage level of the drive signal DP[j] in the logic state according to a voltage level of the drive signal DP[0]. Similarly, the controller616N can be configured to generate the drive signals DN[1]-DN[4] according to the control code CT and the drive signal DN[0] used for controlling the conduction path PN[0]. By way of example but not limitation, the controller616N may determine a logic state of the drive signal DN[j] according to the control bit CT[j], where j=1 to 4. In addition, the controller616N may determine a voltage level of the drive signal DN[j] in the logic state according to a voltage level of the drive signal DN[0].

The decoder614, coupled to the controllers616P and616N, is configured to decode the calibration code CC to generate the control code CT. In the present embodiment, the calibration code CC can be implemented as the trim bits TM[0]-TM[2], which will be described later.

Referring toFIG.7and also toFIG.6, the calibration cell620operable with the variable impedance circuit610may include the detection circuit330shown inFIG.3and the control circuit640, which can represent implementations of the control circuit240shown inFIG.2Brespectively. In the present embodiment, the conduction paths PP[0]-PP[4] can be divided into the conduction path PP[0], a group of conduction paths GP1and a group of impedances GP2. The group of conduction paths GP1includes the conduction paths PP[1] and PP[2]. The group of conduction paths GP2includes the conduction paths PP[3] and PP[4]. The impedance ZDof the detection path CPDcan be indicative of an equivalent impedance ZC2of the conduction path PP[0] and the group of conduction paths GP1in parallel. The detection circuit330may utilize the detection path CPDto track impedance characteristics of the conduction paths PP[0]-PP[2] in parallel. For example, the switch MR can be implemented using a p-channel transistor, which can be formed based on the size of the p-channel transistor used for implementing the switch MP[0]/MP[1]/MP[2]. The impedance element RREFcan be formed based on the dimensions of the impedance elements RP[0]-RP[2]. The input voltage VINat the reference terminal PDREFcan reflect a change in the equivalent impedance ZC2.

The control circuit640is configured to compare the input voltage VINwith the plurality of reference voltages {VR} to generate the trim bits TM[0]-TM[2]. In the present embodiment, the plurality of reference voltages {VR} may include a predetermined reference voltage VPDT, a set of reference voltages {VH} and a set of reference voltages {VL}. The control circuit640may include a comparator650and a signal generator circuit660.

The comparator650is configured to compare a filtered version of the input voltage VIN(i.e. the input voltage VINF) with the predetermined reference voltage VPDTto generate a comparison result CR1. The signal generator circuit660, coupled to the comparator650, can be configured to generate a second portion of the calibration code CC by comparing a filtered version of the input voltage VIN(i.e. the input voltage VINF) with one set of reference voltages selected from among the set of reference voltages {VH} and the set of reference voltages {VL} according to the comparison result CR1. The set of reference voltages {VH} is different from the set of reference voltages {VL}. For example, each reference voltage in the set of reference voltages {VH} is different from each reference voltage in the set of reference voltages {VL}. As another example, each reference voltage in the set of reference voltages {VH} is greater than the predetermined reference voltage VPDT, and each reference voltage in the set of reference voltages {VL} is less than the predetermined reference voltage VPDT.

In the present embodiment, the set of reference voltages {VH} may include different reference voltages VH1-VH3, each of which is greater than the predetermined reference voltage VPDT. The set of reference voltages {VL} may include different reference voltages VL1-VL3, each of which is less than the predetermined reference voltage VPDT. When the comparison result CR1indicates that the input voltage VINis greater the predetermined reference voltage VPDT, the signal generator circuit660is configured to compare the input voltage VINwith the set of reference voltages {VH} to generate the second portion of the calibration code CC. When the comparison result CR1indicates that the input voltage VINis less the predetermined reference voltage VPDT, the signal generator circuit660is configured to compare the input voltage VINwith the set of reference voltages {VL} to generate the second portion of the calibration code CC. The comparison result CR1can serve as the first portion of the calibration code CC. For example, the signal generator circuit660can store the comparison result CR1, and output the comparison result CR1as the trim bit TM[2], which can indicate a relationship between the input voltage VINand the predetermined reference voltage VPDT. In addition, the second portion of the calibration code CC can be implemented as the trim bits TM[0] and TM[1] to indicate a relationship between the input voltage VINand each reference voltage in the selected one set of reference voltages.

The signal generator circuit660includes, but is not limited to, N comparison circuits670_1-670_N, a processing circuit680, and the frequency divider390shown inFIG.3, where N is an integer greater than one. In the example ofFIG.7, N is equal to 3, i.e. the number of reference voltages in the set of reference voltages {VH}/{VL}. The comparison circuits670_1-670_3are coupled to the reference voltages VH1-VH3respectively, and coupled to the reference voltages VL1-VL3respectively. The average of the two reference voltages coupled to a comparison circuit can be substantially equal to the predetermined reference voltage VPDT. For example, the predetermined reference voltage VPDTcan be half the supply voltage VDDIO. The average of the reference voltages VH1and VL1can be substantially equal to the supply voltage VDDIO. Each comparison circuit is configured to compare the input voltage VINwith a corresponding reference voltage in the selected set of reference voltages, and accordingly generate a comparison result (i.e. one of the comparison results CR21-CR23).

In the present embodiment, the comparison circuit670_iincludes a multiplexer672_i, a multiplexer674_iand a comparator676_i, where i=0, 1, 2. The multiplexer672_iis configured to selectively output the input voltage VINor a reference voltage in the set of reference voltages {VH}. The multiplexer674_iis configured to selectively output the input voltage VINor a reference voltage in the set of reference voltages {VL}. The comparator676_iis configured to generate compare the input voltage VINwith a reference voltage outputted from one of the multiplexer672_iand the multiplexer674_i.

For example, the multiplexer672_1is configured to output one of the input voltage VINand the reference voltage VH1as a voltage V11according to the comparison result CR1. The multiplexer674_1is configured to output one of the input voltage VINand the reference voltage VL1as a voltage V21according to the comparison result CR1. When the multiplexer672_1is configured to output the reference voltage VH1as the voltage V11, the multiplexer674_1is configured to output the input voltage VINas the voltage V21. When the multiplexer672_1is configured to output the input voltage VINas the voltage V11, the multiplexer674_1is configured to the reference voltage VL1as the voltage V21. The comparator676_1, coupled to the multiplexers672_1and674_1, is configured to compare the voltage V11with the voltage V21to generate the comparison result CR21.

Similarly, the multiplexer672_2is configured to output one of the input voltage VINand the reference voltage VH2as a voltage V12according to the comparison result CR1. The multiplexer674_2is configured to output one of the input voltage VINand the reference voltage VL2as a voltage V22according to the comparison result CR1. The comparator676_2is configured to compare the voltage V12with the voltage V22to generate the comparison result CR22. The multiplexer672_3is configured to output one of the input voltage VINand the reference voltage VH3as a voltage V13according to the comparison result CR1. The multiplexer674_3is configured to output one of the input voltage VINand the reference voltage VL3as a voltage V23according to the comparison result CR1. The comparator676_3is configured to compare the voltage V13with the voltage V23to generate the comparison result CR23.

The processing circuit680, coupled to the comparison circuits670_1-670_3, is configured to process the comparison results CR21-CR23to generate the trim bits TM[0] and TM[1]. The processing circuit680may include, but is not limited to, an encoder682, a plurality of registers684[0]-684[2], and a plurality of buffers686[0]-686[2]. The encoder682is configured to encode the comparison results CR21-CR23to generate the output codes ZQ0and ZQ1. The registers684[0]-684[2] can be implemented using the registers384[0]-384[2] shown inFIG.3. The registers684[0]-684[2] can be configured to store the output code ZQ0, the output code ZQ1and the comparison result CR1, respectively. The buffers686[0]-686[2] can be implemented using the buffers386[0]-386[2] shown inFIG.3. The buffers686[0]-686[2] can be configured to output the trim bits TM[0]-TM[2], respectively. In some embodiments, the processing circuit680may further include a register coupled in series with a buffer (e.g. the register384[2] and the buffer386[2] shown inFIG.4) to output the output signal ZQ_D shown inFIG.1.

FIG.8illustrates an implementation of the reference voltages VH1-VH3and VL1-VL3shown inFIG.7in accordance with some embodiments of the present disclosure. In the present embodiment, the input voltage VINis substantially equal to the reference voltage VPDTwhen the equivalent impedance ZC2shown inFIG.6is equal to a nominal impedance. The input voltage VINwould reach the reference voltages VH1, VH2and VH3when the equivalent impedance ZC2shown inFIG.6falls below the nominal impedance by A %, B % and C % of the nominal impedance, respectively. The reference voltages VH1-VH3may correspond to A %, B % and C % reductions in impedance compared to the nominal impedance, respectively. The input voltage VINwould reach the reference voltages VL1, VL2and VL3when the equivalent impedance ZC2shown inFIG.6exceeds the nominal impedance by A %, B % and C % of the nominal impedance, respectively. The reference voltages VL1-VL3may correspond to A %, B % and C % increases in impedance compared to the nominal impedance, respectively.

In the example ofFIG.8, the reference voltages VH1-VH3and VL1-VL3can be set to appropriate levels such that A, B and C can be equal to 3, 9 and 15. However, those skilled in the art can appreciate that each reference voltage can be set to any appropriate level depending on design requirements without departing from the scope of the present disclosure.

Referring toFIG.6,FIG.7andFIG.8, in operation, the switch MR is turned on in response to assertion of the enable signal ZQ_E. The supply voltage VDDIO is applied to the impedance element RREFto generate the input voltage VINwhich can reflect a change in the equivalent impedance ZC2. The comparator650can generate the comparison result CR1that is indicative of whether the input voltage VINis greater than the predetermined reference voltage VPDT. When comparison result CR1indicates that the input voltage VINis less than the predetermined reference voltage VPDT, the variable impedance circuit610can enable each conduction path in the group of conduction paths GP1, and selectively enable at least one conduction path in the group of conduction paths GP2according to the calibration code CC. Enabling one or more conduction paths in the group of conduction paths GP2can compensate for the increase in impedance caused by PVT variations. When comparison result CR1indicates that the input voltage VINis greater than the predetermined reference voltage VPDT, the variable impedance circuit610can disable each conduction path in the group of conduction paths GP2, and selectively disable at least one conduction path in the group of conduction paths GP1according to the calibration code CC. Disabling one or more conduction paths in the group of conduction paths GP1can compensate for the reduction in impedance caused by PVT variations.

In the present embodiment, when comparison result CR1indicates that the input voltage VINis less than the predetermined reference voltage VPDT, each of the multiplexers672_1-672_3can output the input voltage VIN, and the multiplexers674_1-674_3can output the reference voltages VL1-VL3, respectively. The comparators676_1-676_3can compare the input voltage VINwith the reference voltages VL1-VL3, respectively, to determine a deviation of the equivalent impedance ZC2from the nominal impedance (e.g. the impedance ZREFof the impedance element RZQ). The processing circuit680can generate the calibration code CC according to the comparison results CR21-CR23outputted from the comparators676_1-676_3. With the use of the calibration code CC indicative of a voltage range in which the input voltage VIN/VINFfalls, the variable impedance circuit610can enable/disable one or more conduction paths having different impedances to adaptively compensate for impedance changes caused by PVT variations.

For example, when the input voltage VINis greater than the reference voltage VL1and less than the predetermined reference voltage VPDT, the equivalent impedance ZC2may exceed by the impedance ZREFby less than 3% of the impedance ZREF. The variable impedance circuit610can enable the conduction paths PP[0]-PP[2], and disable the conduction paths PP[3] and PP[4]. In other words, the switches MP[0]-MP[2] are turned on, and the switches MP[3] and MP[4] are turned off. As a result, the equivalent impedance ZC2of the conduction paths PP[0]-PP[2] in parallel can serve as the impedance ZIO, which lies within a tolerance range of a nominal impedance, e.g. a range of plus or minus 3% of the impedance ZREF.

When the input voltage VINis greater than the reference voltage VL2and less than the reference voltage VL1, the equivalent impedance ZC2may exceed the impedance ZREFby 3% to 9% of the impedance ZREF. To compensate for the increase in impedance caused by PVT variations, the variable impedance circuit610can enable the conduction path PP[3] to adjust an impedance presented between the supply terminal TD and the output terminal PDOUT. For example, the switches MP[0]-MP[3] are turned on to enable the conduction paths PP[0]-PP[3], respectively. The switch MP[4] is turned off to disable the conduction path PP[4]. The resulting impedance ZIOcan exhibit a decrease, such as 6% of the impedance ZREF, compared to an impedance contributed by the conduction paths PP[0]-PP[2] in parallel. In other words, the variable impedance circuit610can enable the conduction path PP[3] to compensate for an increase in impedance, such as 6% of the impedance ZREF.

When the input voltage VINis greater than the reference voltage VL3and less than the reference voltage VL2, the equivalent impedance ZC2may exceed the impedance ZREFby 9% to 15% of the impedance ZREF. The variable impedance circuit610can enable the conduction path PP[4] to adjust an impedance presented between the supply terminal TD and the output terminal PDOUT. The conduction path PP[4] can have an impedance different that of the conduction path PP[3]. For example, the switches MP[0]-MP[2] and MP[4] are turned on to enable the conduction paths PP[0]-PP[2] and PP[4], respectively. The switch MP[3] is turned off to disable the conduction path PP[3]. The resulting impedance ZIOcan exhibit a decrease, such as 12% of the impedance ZREF, compared to an impedance contributed by the conduction paths PP[0]-PP[2] in parallel. In other words, the variable impedance circuit610can enable the conduction path PP[4] to compensate for an increase in impedance, such as 12% of the impedance ZREF.

When the input voltage VINis less than the reference voltage VL3, the equivalent impedance ZC2may exceed the impedance ZREFby more than 15% of the impedance ZREF. The variable impedance circuit610can enable both the conduction paths PP[3] and PP[4] to adjust an impedance presented between the supply terminal TD and the output terminal PDOUT. For example, the switches MP[0]-MP[4] are turned on to enable the conduction paths PP[0]-PP[4], respectively. The resulting impedance ZIOcan exhibit a decrease, such as 18% of the impedance ZREF, compared to an impedance contributed by the conduction paths PP[0]-PP[2] in parallel. In other words, the variable impedance circuit610can enable both the conduction paths PP[3] and PP[4] to compensate for an increase in impedance, such as 18% of the impedance ZREF.

Moreover, in the present embodiment, when comparison result CR1indicates that the input voltage VINis greater than the predetermined reference voltage VPDT, the multiplexers672_1-672_3can output the reference voltages VH1-VH3, respectively, and each of the multiplexers674_1-674_3can output the input voltage VIN. The comparators676_1-676_3can compare the input voltage VINwith the reference voltages VH1-VH3, respectively, to determine a deviation of the equivalent impedance ZC2from the nominal impedance (e.g. the impedance ZREFof the impedance element RZQ). The processing circuit680can generate the calibration code CC according to the comparison results CR21-CR23outputted from the comparators676_1-676_3. With the use of the calibration code CC, the variable impedance circuit610can provide the impedance ZIOthat falls within a predetermined impedance range.

For example, when the input voltage VINis greater than the predetermined reference voltage VPDTand less than the reference voltage VH1, the equivalent impedance ZC2may fall below the impedance ZREFby less than 3% of the impedance ZREF. The variable impedance circuit610can enable the conduction paths PP[0]-PP[2], and disable the conduction paths PP[3] and PP[4]. In other words, the switches MP[0]-MP[2] are turned on, and the switches MP[3] and MP[4] are turned off. As a result, the equivalent impedance ZC2of the conduction paths PP[0]-PP[2] in parallel can serve as the impedance ZIO, which lies within a tolerance range of a nominal impedance, e.g. a range of plus or minus 3% of the impedance ZREF.

When the input voltage VINis greater than the reference voltage VH1and less than the reference voltage VH2, the equivalent impedance ZC2may fall below the impedance ZREFby 3% to 9% of the impedance ZREF. To compensate for the reduction in impedance caused by PVT variations, the variable impedance circuit610can disable the conduction path PP[1] to adjust an impedance presented between the supply terminal TD and the output terminal PDOUT. For example, the switches MP[0] and MP[2] are turned on to enable the conduction paths PP[0] and PP[2], respectively. The switches MP[1], MP[3] and MP[4] are turned off to disable the conduction paths PP[1], PP[3] and PP[4]. The resulting impedance ZIOcan exhibit an increase, such as 6% of the impedance ZREF, compared to an impedance contributed by the conduction paths PP[0]-PP[2] in parallel. In other words, the variable impedance circuit610can disable the conduction path PP[1] to compensate for a decrease in impedance, such as 6% of the impedance ZREF.

When the input voltage VINis greater than the reference voltage VH2and less than the reference voltage VH3, the equivalent impedance ZC2may fall below the impedance ZREFby 9% to 15% of the impedance ZREF. The variable impedance circuit610can disable the conduction path PP[2] to adjust an impedance presented between the supply terminal TD and the output terminal PDOUT. The conduction path PP[2] can have an impedance different that of the conduction path PP[1]. For example, the switches MP[0] and MP[1] are turned on to enable the conduction paths PP[0] and PP[1], respectively. The switches MP[2]-MP[4] are turned off to disable the conduction paths PP[2]-PP[4]. The resulting impedance ZIOcan exhibit an increase, such as 12% of the impedance ZREF, compared to an impedance contributed by the conduction paths PP[0]-PP[2] in parallel. In other words, the variable impedance circuit610can disable the conduction path PP[2] to compensate for a decrease in impedance, such as 12% of the impedance ZREF.

When the input voltage VINis greater than the reference voltage VH3, the equivalent impedance ZC2may fall below the impedance ZREFby more than 15% of the impedance ZREF. The variable impedance circuit610can disable both the conduction paths PP[1] and PP[2] to adjust an impedance presented between the supply terminal TD and the output terminal PDOUT. For example, the switch MP[0] is turned on to enable the conduction path PP[0], and the switches MP[1]-MP[4] are turned off to disable the conduction paths PP[1]-PP[4]. The resulting impedance ZIOcan exhibit an increase, such as 18% of the impedance ZREF, compared to an impedance contributed by the conduction paths PP[0]-PP[2] in parallel. In other words, the variable impedance circuit610can disable both the conduction paths PP[1] and PP[2] to compensate for a decrease in impedance, such as 18% of the impedance ZREF.

In the embodiment shown inFIG.6, the impedance of the conduction path PP[i] can be equal to or substantially equal to the impedance of the conduction path PN[i], where i=0 to 4. For example, the impedance of the impedance element RP[i] can be substantially equal to the impedance of the impedance element RN[i]. The variable impedance circuit610can enable/disable one or more conduction paths PN[0]-PN[4] to adaptively compensate for impedance changes caused by PVT variations, thereby maintain an impedance presented between the supply terminal TS and the output terminal PDOUTto lie within a tolerance range of a nominal impedance, e.g. a range of plus or minus 3% of the impedance ZREF. As those skilled in the art can appreciate the calibration operation associated with the conduction paths PN[0]-PN[4] after reading the above paragraphs directed toFIG.1toFIG.8, similar description is omitted here for brevity.

The circuit structures described above are provided for illustrative purposes, and are not intended to limit the scope of the present disclosure. In some embodiments, the RC filter332shown inFIG.4orFIG.7may be optional. In some embodiments, the detection circuit330shown inFIG.4orFIG.7may be implemented using other circuit topologies as long as the generated input voltage VINcan reflect a change in impedance of the conduction paths included in the variable impedance circuit310/610. In some embodiments, the frequency divider390shown inFIG.4orFIG.7may be optional.

In some embodiments, the detection path CPDshown inFIG.4orFIG.7may be implemented using other circuit structures, each of which is capable of tracking the effect of PVT variations on the output impedance characteristics. In some embodiments, the detection path CPDshown inFIG.4orFIG.7may have an impedance indicative of an impedance of one or more than three conduction paths as long as the impedance ZDcan reflect a change in impedance caused by PVT variations. For example, the impedance ZDcan be indicative of an impedance of the conduction path PP[0]. The impedance ZREFof the impedance element RZQcan be equal to a nominal impedance of the detection path PP[0].

In some embodiments, the comparison circuits670_1-670_3shown inFIG.7may be regarded as a selection stage662and a comparison stage664. The selection stage662can be configured to select the one set of reference voltages from among the set of reference voltages {VH} and the set of reference voltages {VL} according to the comparison result CR1, and output the selected set of reference voltages. The comparison stage664, coupled to the selection stage662, can be configured to compare the input voltage VINwith each reference voltage in the selected one set of reference voltages to generate a set of comparison results, such as the comparison results CR21-CR23. Note that the selection stage662and/or the comparison stage664can be implemented using other circuit structures different from the circuit topology shown inFIG.6. By way of example but not limitation, the selection stage662can be implemented using a 6-to-3 multiplexer circuit, and the comparison stage664can receive the input voltage VINF/VIN, and compare the received input voltage VINF/VINwith an output of the 6-to-3 multiplexer circuit to generate the set of comparison results.

In some embodiments, the calibration code CC outputted from the control circuit340shown inFIG.4can be generated based on the detection scheme shown inFIG.2C.FIG.9illustrates an implementation of the calibration cell220shown inFIG.2Cin accordance with some embodiments of the present disclosure. The structure of the calibration cell920can be identical/similar to that of the calibration cell320shown inFIG.4except for the detection circuit930. The detection circuit930can serve as an embodiment of the detection circuit230shown inFIG.2C. The calibration cell920is operable with the variable impedance circuit310shown inFIG.3to realize an open loop calibration mechanism.

Referring toFIG.9and also toFIG.3, the detection circuit930is arranged to apply the supply voltage VSS (having an electric potential equal to that of the supply voltage VSSIO coupled to the supply terminal TS) to the reference terminal PDREFthrough the detection path CPD, thereby detecting a change in impedance of the conduction paths PN[0]-PN[2]. In the present embodiment, the impedance ZDcan be indicative of an equivalent impedance of the conduction paths PN[0] and PN[1] in parallel. The detection path CPDmay include a switch MS and an impedance element RRSconnected in series, and can be used to track impedance characteristics of the conduction paths PN[0] and PN[1] in parallel. For example, the switch MS can be implemented using an n-channel transistor, which can be formed based on the size of the n-channel transistor used for implementing the switch MN[0]/MN[1]. The impedance element RRScan be formed based on the dimensions of the impedance elements RN[0] and RN[1].

With the use of the calibration code CC generated in response to the input voltage VIN/VINF, the variable impedance circuit310can adjust an equivalent impedance presented between the supply terminal TS and the output terminal PDOUTto fall within a predetermined impedance range. Additionally or alternatively, the variable impedance circuit310can be operable with the calibration cell920to adjust an equivalent impedance presented between the supply terminal TD and the output terminal PDOUTto fall within a predetermined impedance range. As those skilled in the art can understand the impedance calibration mechanism performed by the calibration cell920and the variable impedance circuit310after reading the above paragraphs directed toFIG.1toFIG.8, similar description is omitted here for brevity.

In some embodiments, the calibration code CC outputted from the control circuit640shown inFIG.7can be generated based on the detection scheme shown inFIG.2C.FIG.10illustrates an implementation of the calibration cell220shown inFIG.2Cin accordance with some embodiments of the present disclosure. The structure of the calibration cell1020can be identical/similar to that of the calibration cell620shown inFIG.7except for the detection circuit930. The calibration cell1020is operable with the variable impedance circuit610shown inFIG.6to realize an open loop calibration mechanism.

Referring toFIG.10and also toFIG.6, the detection circuit930is arranged to apply the supply voltage VSS (having an electric potential equal to that of the supply voltage VSSIO coupled to the supply terminal TS) to the reference terminal PDREFthrough the detection path CPD, thereby detecting a change in impedance of the conduction paths PN[0]-PN[4]. In the present embodiment, the impedance ZDcan be indicative of an equivalent impedance of the conduction paths PN[0]-PN[2] in parallel. The detection path CPDcan be used to track impedance characteristics of the conduction paths PN[0]-PN[2] in parallel. For example, the switch MS can be implemented using an n-channel transistor, which can be formed based on the size of the n-channel transistor used for implementing the switch MN[0]/MN[1]/MN[2]. The impedance element RRScan be formed based on the dimensions of the impedance elements RN[0]-RN[2].

With the use of the calibration code CC generated in response to the input voltage VIN/VINF, the variable impedance circuit610can adjust an equivalent impedance presented between the supply terminal TS and the output terminal PDOUTto fall within a predetermined impedance range. Additionally or alternatively, the variable impedance circuit610can be operable with the calibration cell1020to adjust an equivalent impedance presented between the supply terminal TD and the output terminal PDOUTto fall within a predetermined impedance range. As those skilled in the art can understand the impedance calibration mechanism performed by the calibration cell1020and the variable impedance circuit610after reading the above paragraphs directed toFIG.1toFIG.9, similar description is omitted here for brevity.

With the use of a detection circuit capable of tracking impedance characteristics affected by PVT variations, the proposed impedance calibration circuit can realize an open loop calibration mechanism, and achieve a simplified structure and faster response. In addition, the proposed impedance calibration circuit can compare a voltage indicative of impedance variations with a selected set of reference voltages and accordingly enable/disable or more conduction paths having different impedances, thereby realizing adaptive impedance compensation with high precision. For example, the impedance calibration circuit shown inFIG.6may maintain the impedance ZIOto lie within a range of plus or minus 3% of a nominal impedance.

In some embodiments, the proposed adaptive impedance compensation with high precision can be applied to an impedance calibration circuit utilizing closed loop control.FIG.11illustrates an implementation of the impedance calibration circuit shown inFIG.1in accordance with some embodiments of the present disclosure. In the present embodiment, the impedance calibration circuit1100may include the variable impedance circuit210shown inFIG.2Aand the control circuit640shown inFIG.6. The input voltage VINFinputted to the control circuit640may come from the variable impedance circuit210.

By way of example but not limitation, in operation, the control circuit640can compare a voltage occurring at the output terminal PDOUT, i.e. the input voltage VINF, with the plurality of reference voltages {VR} to generate/update the trim bits TM[0]-TM[2]. The generated/updated trim bits TM[0]-TM[2], i.e. the generated/updated calibration code CC, can be fed back to the variable impedance circuit210for impedance compensation. As those skilled in the art can understand the operation of the impedance calibration circuit1100after reading the above paragraphs directed toFIG.1toFIG.10, further description is omitted here for brevity. In addition, those skilled in the art can appreciate that the control circuit340shown inFIG.4, the control circuit340shown inFIG.9and the control circuit640shown inFIG.10can be applied to an impedance calibration circuit utilizing closed loop control without departing from the scope of the present disclosure.

FIG.12is a flow chart of an exemplary impedance calibration method in accordance with some embodiments of the present disclosure. The impedance calibration method1200is described with reference to the variable impedance circuit610shown inFIG.6and the calibration cell620shown inFIG.7for illustrative purposes. Those skilled in the art should appreciate that the impedance calibration method1200can be employed in the impedance calibration circuit100shown inFIG.1, the impedance calibration circuit200A shown inFIG.2A, the impedance calibration circuit200B shown inFIG.2B, the impedance calibration circuit200C shown inFIG.2C, an impedance calibration circuit including the variable impedance circuit310shown inFIG.3and the calibration cell320shown inFIG.4(orFIG.9), and an impedance calibration circuit including the variable impedance circuit610shown inFIG.6and the calibration cell1020shown inFIG.10without departing from the scope of the present disclosure. Additionally, in some embodiments, other operations in the impedance calibration method1200can be performed. In some embodiments, operations of the impedance calibration method1200can vary.

At operation1202, a first supply voltage is applied to a reference terminal through a detection path to detect a change in impedance of a plurality of conduction paths connected in parallel. An input voltage at the reference terminal is generated accordingly. The conduction paths are connected in parallel between a supply terminal and an output terminal of the variable impedance circuit. The supply terminal is coupled to a second supply voltage, and an electric potential of the first supply voltage is equal to an electric potential of the second supply voltage. For example, the detection circuit330can detect a change in impedance of the conduction paths PP[0]-PP[4] connected in parallel by applying the supply voltage VDDIO to the reference terminal PDREFthrough the detection path CPD, and accordingly generate the input voltage VINat the reference terminal PDREF.

At operation1204, the input voltage is compared with a plurality of reference voltages to generate a calibration code. For example, the control circuit640can compare the input voltage VINwith a plurality of reference voltages, which include the predetermined reference voltage VPDT, the set of reference voltages {VH} and the set of reference voltages {VL}, and accordingly generate a calibration code including the trim bits TM[0]-TM[2].

At operation1206, an impedance at the output terminal is adjusted by enabling one or more of the conduction paths according to the calibration code. For example, the variable impedance circuit610can adjust the impedance ZIOby enabling one or more of the conduction paths PP[0]-PP[4] according to the trim bits TM[0]-TM[2].

In some embodiments, the conduction paths connected in parallel may include a conduction path, a first group of conduction paths and a second group of conduction paths. The impedance of the detection path can be indicative of an equivalent impedance of the conduction path and the first group of conduction paths. When the input voltage is less than a minimum voltage of the reference voltages, each conduction path in the first group of conduction paths is enabled, and each conduction path in the second group of conduction paths is enabled. When the input voltage is greater a maximum voltage of the reference voltages, each conduction path in the first group of conduction paths is disabled, and each conduction path in the second group of conduction paths is disabled.

For example, the conduction paths PP[0]-PP[4] may be divided into the conduction path PP[0], a group of conduction paths GP1and a group of conduction paths GP2. The group of conduction paths GP1includes the conduction paths PP[1] and PP[2]. The group of conduction paths GP2includes the conduction paths PP[3] and PP[4]. When the input voltage VINis less than the reference voltage VL3, the variable impedance circuit610can enable each of the conduction paths PP[1]-PP[4] to compensate for an increase in impedance. When the input voltage VINis greater than the reference voltage VH3, the variable impedance circuit610can disable each of the conduction paths PP[1]-PP[4] to compensate for a reduction in impedance.

As those skilled in the art can appreciate operation of the impedance calibration method1200after reading the above paragraphs directed toFIG.1throughFIG.11, further description is omitted here for brevity.

As used herein, the terms “substantially” are used to describe and account for small variations. When used in conduction with an event or circumstance, the terms can refer to instances in which the event of circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to ta given value or range, the term “substantially” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. In addition, when referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.