Patent ID: 12211439

DETAILED DESCRIPTION

For clearer descriptions of the objectives, technical solutions, and advantages of the inventive concept of embodiments of the present disclosure, the inventive concept claimed by the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings and some embodiments.

Transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices having the same feature. Based on their functions in a circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. The source electrode and the drain electrode of the switching transistor used herein are symmetrical, such that the source electrode and the drain electrode can be exchanged. In this embodiment of the present disclosure, the source electrode is referred to as a first electrode; and the drain electrode is referred to as a second electrode. Alternatively, the drain electrode is referred to as a first electrode; and the source electrode is referred to as a second electrode. According to their shapes in the accompanying drawings, a middle end, a signal input end, and a signal output end of the transistor are defined as a gate electrode, a source electrode, and a drain electrode, respectively. In addition, the switching transistor used in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor. The P-type switching transistor is conducted when the gate electrode is at a low level, and is cut off when the gate electrode is at a high level. The N-type switching transistor is conducted when the gate electrode is at a high level, and is cut off when the gate electrode is at a low level. In addition, a plurality of signals in the embodiments of the present disclosure correspondingly have first electric potentials and second electric potentials. A first electric potential and a second electric potential of a signal only represent two status parameters of the electric potential of the signal, and do not indicate that the first electric potential or the second electric potential in this description has a specific numerical value.

In the related art, an OLED display panel generally includes a base substrate, as well as a plurality of pixel circuits, a plurality of light-emitting elements, and a plurality of signal lines (such as reset signal lines and initial power lines) which are disposed on the base substrate. Each pixel circuit is coupled with a light-emitting element and a plurality of signal lines providing different signals, and is configured to drive the light-emitting element to emit light in response to a signal provided by each signal line.

However, a quantity of signal lines which need to be disposed on the base substrate increases with the resolution of the display panel. Accordingly, an area which needs to be occupied by the signal lines and is of the base substrate becomes larger.

With the development of display technologies, people have increasingly higher requirements on visual experience. An embodiment of the present disclosure provides a display panel. The resolution and the refresh rate of the display panel are both high, such that people's requirements on visual experience can be met. A quantity of pixels per inch (PPI) of the display panel may be used to represent the resolution. In other words, the display panel is a high-PPI display panel.

FIG.1is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown inFIG.1, the display panel may include a base substrate00; a plurality of light-emitting elements01disposed on a side of the base substrate00; a plurality of first initial power lines Vinit1and a plurality of first reset signal lines RST1which are disposed on a side of the base substrate00; and a plurality of pixel circuits02disposed on a side of the base substrate00and arranged in an array. Each of the plurality of pixel circuits02may include a first reset circuit021and a drive circuit022.

The first reset circuit021may be respectively coupled with (namely, electrically coupled with) a first reset signal line RST1, a first initial power line Vinit1, and a driving node P0. The first reset circuit021may be configured to transmit a first initial power signal provided by the first initial power line Vinit1to the driving node P0in response to a first reset signal provided by the first reset signal line RST1.

For example, when the electric potential of the first reset signal provided by the first reset signal line RST1is a first electric potential, the first reset circuit021may transmit the first initial power signal provided by the first initial power line Vinit1to the driving node P0, thereby resetting the driving node P0. The electric potential of the first initial power signal may be a second electric potential. The first electric potential may be a valid electric potential, and the second electric potential may be an invalid electric potential. The valid electric potential may be lower than the invalid electric potential.

The drive circuit022may be respectively coupled with the driving node P0and a light-emitting element01. The drive circuit022may be configured to transmit a drive signal to the light-emitting element01based on an electric potential of the driving node P0.

For example, the first reset circuit021transmits the first initial power signal to the driving node P0, such that the driving node P0may be reset in the reset phase. The drive circuit022may include a data-writing sub-circuit and a drive sub-circuit. In a data-writing phase after the reset phase, the data-writing sub-circuit may charge the driving node P0under the control of each signal line coupled with the data-writing sub-circuit. In a light-emitting phase after the data-writing phase, the drive sub-circuit in the drive circuit022may transmit the drive signal (for example, a drive current) to the light-emitting element01based on the electric potential of the driving node P0, thereby driving the light-emitting element01to emit light.

In this embodiment of the present disclosure, among a plurality of pixel circuits02in a same column, first reset circuits021included in at least two pixel circuits02may share a same first initial power line Vinit1. In other words, first initial power lines Vinit1coupled with at least two first reset circuits021in a same column may be the same.

For example, in the display panel shown inFIG.1, among a plurality of pixel circuits02in a same column, first reset circuits021included in every two adjacent pixel circuits02are coupled with a same first initial power line Vinit1. The following uses the first column as an example. Referring toFIG.1, it can be seen that a first reset circuit021included in a first pixel circuit02in the first row and a first reset circuit021included in a second pixel circuit02in the second row share a same first initial power line Vinit1, that a first reset circuit021included in a third pixel circuit02in the third row and a first reset circuit021included in a fourth pixel circuit02in the fourth row share a same first initial power line Vinit1, and by analogy. In this way, compared with the related art in which all first reset circuits021in pixel circuits02are coupled with different first initial power lines Vinit1, a quantity of first initial power lines Vinit1which need to be disposed on the base substrate00can be reduced by half. Therefore, an area which needs to be occupied by the first initial power lines Vinit1and is of the base substrate is reduced. On the premise that the area of the base substrate is fixed, compared with the related art, a greater quantity of pixel circuits02may be disposed on the base substrate00) described in this embodiment of the present disclosure, that is, the resolution of the display panel described in this embodiment of the present disclosure is higher.

In summary, a display panel is provided in the embodiment of the present disclosure. The display panel includes a base substrate and a plurality of pixel circuits disposed on the base substrate. At least two pixel circuits in a same column are coupled with a same first initial power line, such that only a small quantity of signal lines need to be disposed on the base substrate. Accordingly, an area which needs to be occupied by the signal lines and is of the base substrate becomes smaller, thereby facilitating high-resolution design of the display panel.

FIG.2is a schematic structural diagram of another display panel according to an embodiment of the present disclosure. As shown inFIG.2, the display panel may further include a plurality of second reset signal lines RST2and a plurality of second initial power lines Vinit2which are disposed on a side of the base substrate00. The pixel circuit02may further include a second reset circuit023.

The second reset circuit023may be respectively coupled with a second reset signal line RST2, a second initial power line Vinit2, and a light-emitting element01. The second reset circuit023may be configured to transmit a second initial power signal provided by the second initial power line Vinit2to the light-emitting element01in response to a second reset signal provided by the second reset signal line RST2.

For example, referring toFIG.2, the second reset circuit023shown in this figure is coupled with the anode of the light-emitting element01, and the cathode of the light-emitting element01is coupled with a pull-down power end VSS. When the electric potential of the second reset signal provided by the second reset signal line RST2is a first electric potential, the second reset circuit023may transmit the second initial power signal provided by the second initial power line Vinit2to the light-emitting element01, thereby resetting the light-emitting element01. The electric potential of the second initial power signal may be a second electric potential.

Still referring toFIG.2, it can be seen that the display panel may further include a plurality of data signal lines DATA, a plurality of gate drive lines GATE, a plurality of drive power lines VDD, and a plurality of light-emitting control lines EM.

The drive circuit022may be respectively coupled with a data signal line DATA, a gate drive line GATE, a drive power line VDD, and a light-emitting control line EM. The drive circuit02may be configured to transmit a drive signal to the light-emitting element01based on a gate drive signal provided by the gate drive line GATE, a data signal provided by the data signal line DATA, a drive power signal provided by the drive power line VDD, and the electric potential of the driving node P0.

In some embodiments, referring to the structure of a pixel circuit02shown inFIG.3, it can be seen that the drive circuit022may include a data-writing sub-circuit0221, a light-emitting control sub-circuit0222, a storage sub-circuit0223, and a drive sub-circuit0224.

The data-writing sub-circuit0221may be respectively coupled with a driving node P0, a gate drive line GATE, a data signal line DATA, a first node P1, and a second node P2. The data-writing sub-circuit0221may be configured to transmit a data signal provided by the data signal line DATA to the first node P1in response to a gate drive signal which is of the first electric potential and is provided by the gate drive line GATE, and adjust the electric potential of the driving node P0based on the electric potential of the second node P2.

The light-emitting control sub-circuit0222may be respectively coupled with a light-emitting control line EM, a drive power line VDD, the first node P1, the second node P2, and an anode of the light-emitting element01. The light-emitting control sub-circuit0222may be configured to transmit a drive power signal provided by the drive power line VDD to the first node P1in response to a light-emitting control signal which is of the first electric potential and is provided by the light-emitting control line EM, and control the second node P2to be conducted with the light-emitting element01.

The storage sub-circuit0223may be respectively coupled with the drive power line VDD and the driving node P0. The storage sub-circuit0223may adjust the electric potential of the driving node P0based on a drive power signal provided by the drive power line VDD.

The drive sub-circuit0224may be respectively coupled with the first node P1, the second node P2, and the driving node P0. The drive sub-circuit0224may transmit a drive signal to the second node P2based on the electric potential of the first node P1and the electric potential of the driving node P0. After the light-emitting control sub-circuit0222conducts the second node P2with the light-emitting element01, the drive signal transmitted by the drive sub-circuit0224to the second node P2can be further transmitted to the light-emitting element01, such that the light-emitting element01emits light based on the drive signal.

As an optional embodiment, in this embodiment of the present disclosure, among all first reset circuits021sharing a same first initial power line Vinit1, a target first reset circuit021may be directly coupled with the first initial power line Vinit1, and the other first reset circuits021may be coupled with the target first reset circuit021, that is, the other first reset circuits021may be indirectly coupled with the first initial power line Vinit1through the target first reset circuit021.

For example, two first reset circuits021of two adjacent pixel circuits02in a same column share a same first initial power line Vinit1.FIG.4is a schematic structural diagram of still another display panel. As shown inFIG.4, a first reset circuit021of a pixel circuit02in the first row is directly coupled with a first initial power line Vinit1; and a first reset circuit021of a pixel circuit02in the second row is directly coupled with the first reset circuit021of the pixel circuit02in the first row. Thus, it can be determined that the first reset circuit021of the pixel circuit02in the first row is the target first reset circuit. In addition, structures of the drive circuits022and the light-emitting elements01are not shown inFIG.4.

Using the structure shown inFIG.4as an example,FIG.5shows a schematic circuit diagram of two pixel circuits02in a same column. As shown inFIG.5, each first reset circuit021may include a reset transistor T1.

The gate electrode of the reset transistor T1may be coupled with the first reset signal line RST1. The second electrode of the reset transistor T1may be coupled with a driving node P0of the pixel circuit02to which the reset transistor T1belongs. Between two reset transistors T1coupled with a same first initial power line Vinit1, the first electrode of one reset transistor T1may be coupled with the first initial power line Vinit1, and the first electrode of the other reset transistor T1is coupled with the second electrode of the one reset transistor T1.

As another optional embodiment, in this embodiment of the present disclosure, all first reset circuits021sharing a same first initial power line Vinit1may be coupled with the first initial power line Vinit1.

For example, referring to the display panel shown inFIG.1, both a first reset circuit021of a pixel circuit02in the first row and a first reset circuit021of a pixel circuit02in the second row are directly coupled with a same first initial power line Vinit1.

Using the structure shown inFIG.1as an example,FIG.6shows another schematic circuit diagram of two pixel circuits in a same column. As shown inFIG.6, each first reset circuit021may include a reset transistor T1.

Between two reset transistors T1coupled with a same first initial power line Vinit1, the gate electrode of each reset transistor T1may be coupled with the first reset signal line RST1, the second electrode of each reset transistor T1may be coupled with a driving node P0of the pixel circuit02to which the reset transistor T1belongs, and the first electrode of each reset transistor T1may be coupled with the first initial power line Vinit1.

In some embodiments, the reset transistor T1included in the first reset circuit021may be a single-gate transistor. The active layer material of the single-gate transistor may include an oxide material. For example, the single-gate transistor may be manufactured according to a low-temperature poly-crystalline oxide (LTPO) technology. In this way, compared with a reset transistor T1using a double-gate transistor, the reset transistor T1using the single-gate transistor has the following advantages: The electric leakage degree of the reset transistor T1is reduced; and an area which is occupied by the reset transistor T1and is of the base substrate00is reduced. Accordingly, the PPI of the display panel may be further improved.

In addition, with reference toFIG.5andFIG.6, it can be seen that in each pixel circuit02, the second reset circuit023may include a reset transistor T2; in the drive circuit022, the data-writing sub-circuit0221may include a data-writing transistor T3and a compensation transistor T4; the light-emitting control sub-circuit0222may include a first light-emitting control transistor T5and a second light-emitting control transistor T6; the storage sub-circuit0223may include a storage capacitor C0; and the drive sub-circuit0224may include a drive transistor T7.

The gate electrode of the reset transistor T2may be coupled with the second reset signal line RST2. The first electrode of the reset transistor T2may be coupled with the second initial power line Vinit2. The second electrode of the reset transistor T2may be coupled with the anode of the light-emitting element01.

The gate electrode of the data-writing transistor T3and the gate electrode of the compensation transistor T4may be both coupled with the gate drive line GATE. The first electrode of the data-writing transistor T3may be coupled with the data signal line DATA. The second electrode of the data-writing transistor T3may be coupled with the first node P1. The first electrode of the compensation transistor T4may be coupled with the second node P2. The second electrode of the compensation transistor T4may be coupled with the driving node P0.

The gate electrode of the first light-emitting control transistor T5and the gate electrode of the second light-emitting control transistor T6may be both coupled with the light-emitting control line EM. The first electrode of the first light-emitting control transistor T5may be coupled with the drive power line VDD. The second electrode of the first light-emitting control transistor T5may be coupled with the first node P1. The first electrode of the second light-emitting control transistor T6may be coupled with the second node P2. The second electrode of the second light-emitting control transistor T6may be coupled with the anode of the light-emitting element01.

One end of the storage capacitor C0may be coupled with the driving node P0, and the other end of the storage capacitor C0may be coupled with the drive power line VDD.

The gate electrode of the drive transistor T7may be coupled with the driving node P0. The first electrode of the drive transistor T7may be coupled with the drive power line VDD. The second electrode of the drive transistor T7may be coupled with the second node P2.

In some embodiments, on the premise that first reset circuits021of at least two pixel circuits02share one first initial power line Vinit1in the manner shown inFIG.1, among a plurality of pixel circuits02in a same column, second reset circuits023included in at least two pixel circuits02may be coupled with a same second initial power line Vinit2. The same first initial power line Vinit1coupled with the first reset circuits021and the same second initial power line Vinit2coupled with the second reset circuits023may share a same line. In other words, among at least two pixel circuits02in a same column, the second reset circuits023of the pixel circuits02share one second initial power line Vinit2; and the shared second initial power line Vinit2and the first initial power line Vinit1shared by the first reset circuits021of the at least two pixel circuit02are the same initial power line. In this way, an area which needs to be occupied by signal lines and is of the base substrate00can be further reduced, and the design of the display panel with high-PPI is further facilitated.

For example, referring to yet another display panel shown inFIG.7, it can be seen that in two adjacent pixel circuits02in a same column, two first reset circuits021are coupled with a same first initial power line Vinit1; two second reset circuits023are coupled with a same second initial power line Vinit2; and the first initial power line Vinit1and the second initial power line Vinit2are a same signal line.

Still referring to the display panel shown inFIG.7, it can be seen that in every two adjacent pixel circuits02, a first reset signal line RST1coupled with a first reset circuit021included in one pixel circuit02and a second reset signal line RST2coupled with a second reset circuit023included in the other pixel circuit02may share a same line. In other words, two first reset circuits021and two second reset circuits023included in every two adjacent pixel circuits02only need to be coupled with two reset signal lines in total. Compared with the related art in which all first reset circuits021in pixel circuits02are coupled with different first reset signal lines RST1and all second reset circuits023in the pixel circuits02are coupled with different second reset signal lines RST2, a quantity of first reset signal lines RST1and a quantity of second reset signal lines RST2which need to be disposed on the base substrate00can be both reduced by half. In this way, an area which needs to be occupied by signal lines and is of the base substrate00can be further reduced, and the design of the display panel with high-PPI is further facilitated.

Based on the structure shown inFIG.7,FIG.8shows a schematic structural diagram of yet another display panel. Referring toFIG.8, it can be seen that in every two adjacent pixel circuits02, a first reset signal line RST1coupled with a first reset circuit021included in one pixel circuit02and a first reset signal line RST1coupled with a first reset circuit021included in the other pixel circuit02share a same line. In addition, a second reset signal line RST2coupled with a second reset circuit023included in one pixel circuit02and a second reset signal line RST2coupled with a second reset circuit023included in the other pixel circuit02share a same line. In other words, referring toFIG.8, it can be seen that two first reset circuits021and two second reset circuits023included in every two adjacent pixel circuits02only need to be coupled with one reset signal line. Compared with the related art described above, the total quantity of first reset signal lines RST1and second reset signal lines RST2which need to be disposed on the base substrate00can be reduced to ¼. In this way, an area which needs to be occupied by signal lines and is of the base substrate00can be further reduced, and the design of the display panel with high-PPI is further facilitated.

In addition, based on the structures shown inFIG.7andFIG.8, drive circuits022included in at least two pixel circuits02sharing a same first initial power line Vinit1may be coupled with different drive power lines VDD. For example, it can be seen that in the two adjacent pixel circuits02shown inFIG.7andFIG.8, a drive circuit022included in one pixel circuit02is coupled with a drive power line VDD; and a drive circuit022included in the other pixel circuit02is coupled with another drive power line VDD.

Based on the structure shown inFIG.4,FIG.9shows a schematic structural diagram of yet another display panel. Referring toFIG.9, it can be seen that on the premise that first reset circuits021of at least two pixel circuits02share one first initial power line Vinit1in the manner shown inFIG.4, in each pixel circuit02, a first reset signal line RST1coupled with the first reset circuit021and a second reset signal line RST2coupled with the second reset circuit023may share a same line. In other words, the first reset circuit021and the second reset circuit023of each pixel circuit02may be coupled with a same reset signal line. In this way, an area which needs to be occupied by signal lines and is of the base substrate00can be further reduced, and the design of the display panel with high-PPI is further facilitated.

Moreover, referring toFIG.9, it can be further seen that based on the structure shown inFIG.4, a first initial power line Vinit1coupled with a first reset circuit021of a pixel circuit02in the first row and a second initial power line Vinit2coupled with a second reset circuit023of the pixel circuit02share a same line. A second reset circuit023of a pixel circuit02in the second row is independently coupled with a second initial power line Vinit2.

In addition, based on the structure shown inFIG.9, drive circuits022included in at least two pixel circuits02sharing a same first initial power line Vinit1are coupled with a same drive power line VDD. For example, it can be seen that two drive circuits022included in two adjacent pixel circuits02shown inFIG.9are coupled with a same drive power line VDD.

In addition, in this embodiment of the present disclosure, drive circuits022included in at least two pixel circuits02sharing a same first initial power line Vinit1are coupled with different data signal lines DATA. For example, it can be further seen that in the two adjacent pixel circuits02shown inFIG.7toFIG.9, a drive circuit022included in one pixel circuit02is coupled with a data signal line DATA1; and a drive circuit022included in the other pixel circuit02is coupled with another data signal line DATA2.

It should be noted that, neither a specific structure of the drive circuit022nor a light-emitting control line EM and a data signal line DATA which are coupled with the drive circuit022are shown in the display panels shown inFIG.7toFIG.9. In addition,FIG.7toFIG.9only show structures of two adjacent pixel circuits02in a same column.

In some embodiments, each pixel circuit02may generally include: (1) a semiconductor layer disposed on a side of the base substrate00, wherein the semiconductor layer may be configured to form an active layer of each transistor in the pixel circuit; (2) a first gate metal layer disposed on a side of the base substrate00, wherein the first gate metal layer may be configured to form the gate electrode of each transistor and a capacitor plate of the storage capacitor C0; with reference toFIG.5andFIG.6, the gate electrode of each transistor may be coupled with a corresponding signal line; and the gate electrode of each transistor may be overlapped with a channel region of the transistor; (3) a second gate metal layer disposed on a side of the base substrate00, wherein the second gate metal layer may be configured to form another capacitor plate of the storage capacitor C0, as well as some signal lines (such as the first initial power line Vinit1) with which the pixel circuit02needs to be coupled; (4) a first source-drain metal layer and a second source-drain metal layer which are disposed on a side of the base substrate00, wherein the first source-drain metal layer and the second source-drain metal layer may be configured to form some signal lines (such as the data signal line DATA) with which the pixel circuit02needs to be coupled, and connect two layers which need to be connected; and (5) an insulation layer disposed between every two adjacent metal layers. In some embodiments, the semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer may be generally stacked in a direction distal from the base substrate00in sequence.

The active layer may include a channel region, as well as a source region and a drain region disposed on two sides of the channel region. The channel region may be undoped; or a doped type of the channel region is different from that of the source region and the drain region, such that the channel region has the feature of a semiconductor. Both the source region and the drain region may be doped, thereby having electrical conductivity. An impurity used for doping may vary with the type of a transistor (namely, N-type or P-type). Moreover, the source electrode of each transistor may be coupled with the source region; and the drain electrode of the transistor may be coupled with the drain region.

With reference to the above description of the pixel circuit and using the structure shown inFIG.7as an example,FIG.10shows a semiconductor layer02A included in two adjacent pixel circuits02. Based onFIG.10,FIG.11further shows a first gate metal layer02B included in the two adjacent pixel circuits02. Based onFIG.11,FIG.12further shows a second gate metal layer02C included in the two adjacent pixel circuits02. Based onFIG.12,FIG.13further shows a first source-drain metal layer02D and a second source-drain metal layer02E included in the two adjacent pixel circuits02. In addition, with reference toFIG.6,FIG.13further shows an optional location of each transistor on the layout.

Referring toFIG.10, it can be seen that the semiconductor layer configured to form two adjacent pixel circuits02includes three independent parts.

Referring toFIG.11andFIG.13, it can be seen that the first gate metal layer02B can be configured to form a gate electrode coupled with a gate drive line GATE (namely, a data-writing transistor T3and a compensation transistor T4), a capacitor plate C01, a gate electrode coupled with a light-emitting control line EM (namely, light-emitting control transistors T5and T6), a gate electrode coupled with a first reset signal line RST1(namely, a reset transistor T1), and a gate electrode coupled with a second reset signal line RST2(namely, a reset transistor T2). Among the three independent parts included in the semiconductor layer, a vertical bar-shaped part is overlapped with the first reset signal line RST1and the second reset signal line RST2. Moreover, a reset transistor T1included in a first reset circuit021of one pixel circuit02and a reset transistor T2included in a second reset circuit023of the other pixel circuit02share a same reset signal line.

Referring toFIG.12andFIG.13, it can be seen that the second gate metal layer02C may be configured to form another capacitor plate C02, a first initial power line Vinit1, and a second initial power line Vinit2. Moreover, a first initial power line Vinit1coupled with two reset transistors T1and a second initial power line Vinit2coupled with two reset transistors T2share a same line. The shared initial power line includes two independent parts which are connected by the first source-drain metal layer02D, thereby effectively transmitting a signal.

Referring toFIG.13, it can be seen that the first source-drain metal layer02D and the second source-drain metal layer02E may form data signal lines DATA1and DATA2, a drive power line VDD, and a component used for connecting. In addition, it can be further seen that different parts which need to be coupled and are disposed on different layers can be connected through connecting holes K0. Moreover, it can be further seen that two data-writing transistors T3are respectively coupled with different data signal lines DATA1and DATA2; and two light-emitting control transistors T5are respectively coupled with two drive power lines VDD.

Using the structure shown inFIG.8as an example,FIG.14shows a semiconductor layer02A, a first gate metal layer02B, a second gate metal layer02C, a first source-drain metal layer02D, and a second source-drain metal layer02E which are included in two adjacent pixel circuits02. Moreover, with reference toFIG.6,FIG.14further shows an optional location of each transistor on the layout. Compared with the structure shown inFIG.13, referring toFIG.14, it can be seen that two reset transistors T1and two reset transistors T2which are included in two adjacent pixel circuits02share a same reset signal line (including a first reset signal line RST1and a second reset signal line RST2). It should be noted that a reference numeral of each layer is not shown inFIG.14; and only each structure formed by each layer is marked.

With reference to the above description of the pixel circuit and using the structure shown inFIG.9as an example,FIG.15shows a semiconductor layer02A included in two adjacent pixel circuits02. Based onFIG.15,FIG.16further shows a first gate metal layer02B included in the two adjacent pixel circuits02. Based onFIG.16,FIG.17further shows a second gate metal layer02C included in the two adjacent pixel circuits02. Based onFIG.17,FIG.18further shows a first source-drain metal layer02D and a second source-drain metal layer02E included in the two adjacent pixel circuits02. In addition, with reference toFIG.5,FIG.18further shows an optional location of each transistor on the layout.

Referring toFIG.15, it can be seen that the semiconductor layer configured to form two adjacent pixel circuits02includes two independent parts.

Referring toFIG.16andFIG.18, it can be seen that the first gate metal layer02B can be configured to form a gate electrode coupled with a gate drive line GATE (namely, a data-writing transistor T3and a compensation transistor T4), a capacitor plate C01, a gate electrode coupled with a light-emitting control line EM (namely, light-emitting control transistors T5and T6), a gate electrode coupled with a first reset signal line RST1(namely, a reset transistor T1), and a gate electrode coupled with a second reset signal line RST2(namely, a reset transistor T2). In each pixel circuit02, a reset transistor T1and a reset transistor T2share a same reset signal line.

Referring toFIG.17andFIG.18, it can be seen that the second gate metal layer02C may be configured to form another capacitor plate C02, a first initial power line Vinit1, and a second initial power line Vinit2. Moreover, a first initial power line Vinit1coupled with a reset transistor T1of a first pixel circuit02and a second initial power line Vinit2coupled with a reset transistor T2of the first pixel circuit02share a same line. A reset transistor T1of a second pixel circuit02is coupled with the reset transistor T1of the first pixel circuit02through a first source-drain metal layer02D. A reset transistor T2of the second pixel circuit02is coupled with a second initial power line Vinit2. In addition, referring toFIG.17, it can be further seen that the second gate metal layer02C can further form a metal overlapping part BI which is overlapped with a reset transistor T1, such that an impact of electric leakage of the reset transistor T1on the driving node P0can be reduced.

Referring toFIG.18, it can be seen that the first source-drain metal layer02D and the second source-drain metal layer02E may form data signal lines DATA1and DATA2, a drive power line VDD, and a component used for connecting. In addition, it can be further seen that different parts which need to be coupled and are disposed on different layers can be connected through connecting holes K0. Moreover, it can be further seen that two data-writing transistors T3are respectively coupled with different data signal lines DATA1and DATA2; and two light-emitting control transistors T5are coupled with a same drive power line VDD.

In some embodiments, with reference to the structures shown inFIG.13,FIG.14, andFIG.18and using an example in which each transistor is a P-type transistor,FIG.19shows a working sequence diagram of a pixel circuit02. As shown inFIG.19, a phase in which a pixel circuit02drives a light-emitting element01to emit light may include: a reset phase t1, a data-writing phase t2, and a light-emitting phase t3.

In the reset phase t1, an electric potential of a first reset signal provided by a first reset signal line RST1and the electric potential of a second reset signal provided by a second reset signal line RST2are both first electric potentials. In this case, reset transistors T1and T2of two pixel circuits02are both enabled. A first initial power signal provided by a first initial power line Vinit1is transmitted to corresponding driving nodes P0respectively through the reset transistors T1of the two pixel circuits02, thereby reliably resetting the driving nodes P0. A second initial power signal provided by a second initial power line Vinit2is transmitted to the anodes of corresponding light-emitting elements01respectively through reset transistors T2of the two pixel circuits02, thereby reliably resetting the anodes of the light-emitting elements01.

In some embodiments,FIG.20further shows an equivalent diagram of a signal transmission direction in the reset phase t1based on the structure shown inFIG.13; andFIG.21further shows an equivalent diagram of a signal transmission direction in the reset phase t1based on the structure shown inFIG.18.

In the data-writing phase12, an electric potential of a gate drive signal provided by each gate drive line GATE is the first electric potential. In this case, data-writing transistors T3and compensation transistors T4of two pixel circuits02are both enabled. Data signals provided by data signal lines DATA1and DATA2are respectively transmitted to corresponding first nodes P1through the data-writing transistors T3coupled with the data signal lines, thereby charging the first nodes P1. In this case, drive transistors T7are enabled and transmit the electric potentials of the first nodes P1to second nodes P2. Then, the compensation transistors T4adjust the electric potentials of the driving nodes P0based on the electric potentials of the second nodes P2, thereby charging the driving nodes P0.

In some embodiments,FIG.22shows an equivalent diagram of a signal transmission direction in the data-writing phase t2based on the structure shown inFIG.13; andFIG.23further shows an equivalent diagram of a signal transmission direction in the data-writing phase t2based on the structure shown inFIG.18.

In the light-emitting phase t3, an electric potential of a light-emitting control signal provided by each light-emitting control line EM is a first electric potential; and light-emitting control transistors T5and T6included in two pixel circuits02are both enabled. A drive power signal which is of a first electric potential and provided by a drive power line VDD can be transmitted to the first nodes P1through the light-emitting control transistors T5. In this case, the drive transistors T7may transmit a drive current to the second nodes P2based on electric potentials written to the driving nodes P0in the data-writing phase t2and the current electric potentials of the first nodes P1. The drive current may be further transmitted to the anodes of light-emitting elements01through the light-emitting control transistors T6, such that the light-emitting elements01can emit light.

In some embodiments,FIG.24shows an equivalent diagram of a signal transmission direction in the light-emitting phase t3based on the structure shown inFIG.13; andFIG.25further shows an equivalent diagram of a signal transmission direction in the light-emitting phase t3based on the structure shown inFIG.18.

It should be noted that, inFIG.19, a time sequence of a reset signal represents time sequences of a first reset signal and a second reset signal; and a time sequence of a data signal represents time sequences of a first data signal and a second data signal. Moreover, the first electric potential, the second electric potential, and the electric potential of the data signal which are shown inFIG.19are −6 V (volt), 6 V, and about 2 V to 4.5 V, respectively. With reference to the working sequence diagram shown inFIG.19, it can be seen that in this embodiment of the present disclosure, two adjacent pixel circuits in a same column can emit light simultaneously; and the brightness of the light can vary with data signals provided by data signal lines respectively coupled with the pixel circuits. Therefore, it can be determined that the refresh rate of the display panel described in this embodiment of the present disclosure is higher.

In addition, with reference to the above description, it can be seen that the structures of the two pixel circuits02in this embodiment of the present disclosure are 14T2C (that is, 14 transistors and 2 capacitors) structures. In some embodiments, the structures of the two pixel circuits02may also be other structures (for example, 12T2C structures). Two adjacent pixel circuits02respectively drive two light-emitting elements02to emit light independently, and can share a signal in the reset phase t1. In this way, the refresh rate of the display panel is improved while a high PPI of the display panel is ensured.

It should be noted that, the above embodiments are all described by using an example in which all the transistors are P-type transistors and the first electric potential is lower than the second electric potential. All the transistors may alternatively be N-type transistors. When all the transistors are the N-type transistors, the first electric potential is higher than the second electric potential.

In summary, a display panel is provided in this embodiment of the present disclosure. The display panel includes a base substrate and a plurality of pixel circuits disposed on the base substrate. At least two pixel circuits in a same column are coupled with a same first initial power line, such that only a small quantity of signal lines need to be disposed on the base substrate. Accordingly, an area which needs to be occupied by the signal lines and is of the base substrate becomes smaller, thereby facilitating high-resolution design of the display panel.

FIG.26is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown inFIG.26, the display device may include a power supply assembly J1and the display panel000shown in the above accompanying drawings. The power supply assembly J1may be coupled with the display panel000and configured to supply power to the display panel000.

In some embodiments, the display device may be any product or component with a display function, such as a liquid crystal display device, electronic paper, an OLED device, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, or a navigator.

It should be understood that the terms “first,” “second,” and the like in the description and claims, as well as the above-mentioned drawings, of the present disclosure are used to distinguish similar objects, and not necessarily used to describe a specific order or precedence order. It should be understood that data used in this way can be interchanged where appropriate. For example, the present disclosure can be implemented in a sequence other than the sequence illustrated or described in the embodiments of the present disclosure.

The above descriptions are merely exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, or improvements and the like made within the spirit and principles of the present disclosure should be included within the protection scope of the present disclosure.