Patent ID: 12244947

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present disclosure will be described in detail on the basis of the drawings. Description will be given in the following order. Note that in each of the following embodiments, the same parts are denoted by the same symbols, and redundant description will be omitted.1. First Embodiment2. Second Embodiment3. Third Embodiment4. Fourth Embodiment5. Fifth Embodiment6. Application Examples to Imaging Device

1. First Embodiment

Configuration of Imaging Element

FIG.1is a diagram illustrating a configuration example of an imaging element according to an embodiment of the present disclosure. The drawing is a block diagram illustrating a configuration example of an imaging element1. The imaging element1is a semiconductor element that generates image data of a subject. The imaging element1includes a pixel array unit a vertical drive unit20, a column signal processing unit and a control unit40.

The pixel array unit10includes a plurality of pixels100arranged therein. The pixel array unit10in the drawing is an example in which the plurality of pixels100is arrayed in a shape of a two-dimensional matrix. Incidentally, a pixel100includes a photoelectric conversion unit that performs photoelectric conversion of incident light and generates an image signal of a subject on the basis of emitted incident light. For example, a photodiode can be used as the photoelectric conversion unit. Signal lines11and12are wired to each of the pixels100. A pixel100is controlled by a control signal transmitted by a signal line11to generate an image signal and outputs the generated image signal via a signal line12. Note that a signal line11is disposed for each of the rows shaping the two-dimensional matrix and is wired in a shared manner to a plurality of pixels100arranged in one row. A signal line12is disposed for each of the columns shaping the two-dimensional matrix and is wired in a shared manner to a plurality of pixels100arranged in one column.

The vertical drive unit20generates control signals for the pixels100described above. The vertical drive unit20in the drawing generates a control signal for each of the rows of the two-dimensional matrix of the pixel array unit10and sequentially outputs the control signals via a signal line11.

The column signal processing unit30processes an image signal generated by a pixel100. The column signal processing unit30in the drawing simultaneously processes image signals from a plurality of pixels100arranged in one row of the pixel array unit10transmitted via a signal line12. As this processing, for example, analog-digital conversion for converting an analog image signal generated by a pixel100into a digital image signal or correlated double sampling (CDS) for removing an offset error of the image signal can be performed. The processed image signal is output to a circuit or the like outside the imaging element1.

The control unit40controls the vertical drive unit20and the column signal processing unit30. The control unit40in the drawing outputs control signals via each of signal lines41and42to control the vertical drive unit20and the column signal processing unit30.

The imaging element1in the drawing includes three stacked semiconductor substrates (semiconductor substrates120,220and320). The pixel array unit10can be disposed on the semiconductor substrates120and220. The vertical drive unit20, the column signal processing unit30, and the control unit40can be arranged on the semiconductor substrate320. Details of the structure of the semiconductor substrate120and others will be described later. Note that the imaging element1in the drawing is an example of the imaging device described in the claims. Note that the pixel array unit10in the drawing is an example of the imaging element described in the claims. Furthermore, the vertical drive unit20in the drawing is an example of the control signal generating circuit described in the claims. In an, the column signal processing unit30in the drawing is an example of the processing circuit described in the claims.

Configuration of Pixel

FIG.2is a diagram illustrating a configuration example of a pixel according to a first embodiment of the disclosure. The drawing is a circuit diagram illustrating a structure example of the pixels100. A pixel100in the drawing includes photoelectric conversion units101a,101b,101c, and101d, charge transfer units102a,102b,102c, and102d, and an image signal generating circuit110.

Furthermore, the image signal generating circuit110includes MOS transistors111to113. The MOS transistors111to113, the charge transfer units102a,102b,102c, and102dcan include an n-channel MOS transistor.

As described above, signal lines11and12are wired to the pixel100. The signal lines11in the drawing include a signal line TG1, a signal line TG2, a signal line TG3, a signal line TG4, a signal line RST, and a signal line SEL. In addition, a power supply line Vdd is wired to the pixel100. The power supply line Vdd is wiring that supplies power to the pixel100.

An anode of the photoelectric conversion unit101ais grounded, and a cathode is connected to a source of the charge transfer unit102a. An anode of the photoelectric conversion unit101bis grounded, and a cathode is connected to a source of the charge transfer unit102b. An anode of the photoelectric conversion unit101cis grounded, and a cathode is connected to a source of the charge transfer unit102c. An anode of the photoelectric conversion unit101dis grounded, and a cathode is connected to a source of the charge transfer unit102d. A drain of the charge transfer unit102a, a drain of the charge transfer unit102b, a drain of the charge transfer unit102c, and a drain of the charge transfer unit102dare connected to a gate of the MOS transistor112in a shared manner. The gate of the MOS transistor112is further connected with a source of the MOS transistor111and a first end of the charge holding unit103. A second end of the charge holding unit103is grounded. A drain of the MOS transistor111and a drain of the MOS transistor112are connected to the power supply line Vdd in a shared manner. A source of the MOS transistor112is connected to a drain of the MOS transistor113, and a source of the MOS transistor113is connected to the signal line12.

The signal line TG1, the signal line TG2, the signal line TG3, and the signal line TG4are connected to a gate of the charge transfer unit102a, a gate of the charge transfer unit102b, a gate of the charge transfer unit102c, and a gate of the charge transfer unit102d, respectively. The signal line RST and the signal line SEL are connected to a gate of the MOS transistor111and a gate of the MOS transistor113, respectively.

The photoelectric conversion units101a,101b,101c, and101dperform photoelectric conversion of incident light. The photoelectric conversion units101a,101b,101c, and101dcan include a photodiode formed in the semiconductor substrate120described later.

The charge holding unit103holds a charge. The charge holding unit103holds charges generated by photoelectric conversion by the photoelectric conversion units101a,101b,101c, and101d. The charge holding unit103can include a floating diffusion (FD) region which is a semiconductor region formed in the semiconductor substrate120.

The charge transfer units102a,102b,102c, and102dtransfer the charges generated by photoelectric conversion by the photoelectric conversion units101a,101b,101c, and101dto the charge holding unit103. The charge transfer units102a,102b,102c, and102dtransfer the charges of the photoelectric conversion units101a,101b,101c, and101d, respectively. Control signals of the charge transfer units102a,102b,102c, and102dare transmitted by signal lines TG1, TG2, TG3, and TG4, respectively. Applicable as this control signal is a pulse signal (hereinafter referred to as an ON signal) having a voltage exceeding a threshold value of a gate-source voltage Vgs of a MOS transistor included in the charge transfer unit102aand others. By applying this ON signal to the gate of the charge transfer unit102aand others, the charge transfer unit102aand others can be made conductive.

The image signal generating circuit110generates an image signal on the basis of a charge held by the charge holding unit103. As described above, the image signal generating circuit110includes the MOS transistors111to113. As described later, the image signal generating circuit110is disposed in the semiconductor substrate220.

The MOS transistor111resets the charge holding unit103. This reset can be performed by discharging the charge of the charge holding unit103by electrically connecting the charge holding unit103and the power supply line Vdd. A control signal for the MOS transistor111is transmitted by the signal line RST. In addition, the gate of the MOS transistor112is connected to the charge holding unit103. Therefore, an image signal having a voltage corresponding to the charge held in the charge holding unit103is generated at the source of the MOS transistor112. Furthermore, the image signal can be output to the signal line12by making the MOS transistor113conductive. A control signal for the MOS transistor113is transmitted by the signal line SEL. The above ON signal can also be applied to the control signals of the MOS transistors111and113.

Generation of image signals in the pixel100in the drawing can be performed as follows. First, the MOS transistor111is made conductive to reset the charge holding unit103. At this point, the charge transfer units102a,102b,102c, and102dare further made conductive. As a result, charges of the photoelectric conversion units101a,101b,101c, and101dare discharged, and the photoelectric conversion units101a,101b,101c, and101dare reset. After completion of this reset, application of an ON signal to the MOS transistor111and the charge transfer units102a,102b,102c, and102dis stopped to bring the MOS transistor111and the charge transfer units102a,102b,102c, and102dinto a non-conductive state. As a result, exposure is started.

After a predetermined exposure period elapses, the charge holding unit103is reset again by the MOS transistor111. After completion of the reset, the charge transfer unit102ais made conductive, and the charge of the photoelectric conversion unit101ais transferred to the charge holding unit103and held therein. An image signal corresponding to the held charge is generated by the MOS transistor112. Next, by making the MOS transistor113conductive, the image signal based on the photoelectric conversion by the photoelectric conversion unit101acan be output to the signal line12.

Next, the procedure from the resetting of the charge holding unit103to the output of the image signal is sequentially performed on the charge transfer units102b,102c, and102d. As a result, image signals based on the photoelectric conversion by the photoelectric conversion units101b,101c, and101dcan be sequentially output to the signal line12.

When the charge transfer units102aand others transfer the charges of the photoelectric conversion units101aand others to the charge holding unit103, an ON signal is applied to the charge transfer units102a,102b,102c, and102dvia the signal lines TG1, TG2, TG3, and TG4. By application of these ON signals, the charge transfer units102a,102b,102c, and102denter a conduction state, and the charges are transferred. In a case where there is a difference in the conduction states of the charge transfer units102a,102b,102c, and102d, variations occur in the charge transfer from the photoelectric conversion units101aand others. For example, the time required for charge transfer varies, and the sensitivity varies for each of the photoelectric conversion units101a,101b,101c, and101d. As a result, an error occurs in the image signals.

The variation in the conduction state in each of the charge transfer units102a,102b,102c, and102dis caused by, for example, a variation in the ON signal, that is, the control signal. This variation in the control signal is caused by, for example, a variation in wiring capacitances of the signal lines TG1, TG2, TG3, and TG4that transmit the control signals. This is because variations in the wiring capacitances cause variations in the waveform of control signals, which changes the conduction states of the charge transfer units102aand others. Furthermore, for example, also in a case where the capacitance between the signal line TG1and others and drains of MOS transistors included in the charge transfer unit102aand others to which the respective signal lines are connected varies, the conduction states of the charge transfer unit102aand others change. This is because the potential immediately below the gate of the charge transfer unit102aand others changes as described later.

As described above, in order to reduce variations in charge transfer by the charge transfer units102a,102b,102c, and102d, it is necessary to make the wiring capacitances and others of the signal lines TG1, TG2, TG3, and TG4uniform. Therefore, it is necessary to completely match the arrangement of the signal lines TG1, TG2, TG3, and TG4with respect to the semiconductor substrate. However, it is difficult to completely match the arrangement of the signal lines TG1, TG2, TG3, and TG4. This is because there are constraints in the layout in the semiconductor substrate120. Therefore, in the pixels100of the present disclosure, variations are reduced by adjusting the wiring capacitances of the signal lines TG1, TG2, TG3, and TG4. By disposing a capacitance adjustment unit130described later, the wiring capacitances of the signal lines TG1, TG2, TG3, and TG4can be adjusted.

Planar Structure of Pixel

FIG.3is a plan view illustrating a structure example of a pixel according to the first embodiment of the disclosure. The drawing is a plan view illustrating the configuration example of the pixel100. As described above, the pixel array unit10includes the semiconductor substrates120and220. In the drawing, the semiconductor substrates120and220are illustrated. The semiconductor substrate120is disposed in a first layer, in which the photoelectric conversion units101a,101b,101c, and101d, the charge transfer units102a,102b,102c, and102d, and the charge holding unit103of the pixel100are formed. The semiconductor substrate220is disposed in a second layer, in which the image signal generating circuit110is formed.

Hatched regions in the drawing represent the semiconductor substrates (semiconductor substrates120and220). A white rectangle represents a semiconductor region formed in the semiconductor substrate. A polygon of a two-dot chain line represents a gate electrode of a MOS transistor. Rectangles hatched with dots represent capacitance adjustment units130a,130b,130c, and130d. A region of a dotted line represents wiring disposed in the semiconductor substrate120. A region of a broken line represents wiring disposed in the semiconductor substrate220. A dotted circle represents a via plugs and a contact plug. Details of the above will be described later.

In the semiconductor substrate120, the photoelectric conversion units101a,101b,101c, and101dare arranged in two rows and two columns. The charge holding unit103is disposed at the center among the photoelectric conversion units101a,101b,101c, and101d. The charge transfer units102a,102b,102c, and102dare arranged between the photoelectric conversion units101a,101b,101c, and101dand the charge holding unit103, respectively.

The image signal generating circuit110of the semiconductor substrate220is disposed at a position where a part thereof overlaps the photoelectric conversion units101aand101d. As illustrated in the drawing, in the image signal generating circuit110, the MOS transistors111to113are arranged side by side.

Wiring244of the semiconductor substrate220corresponds to the signal line TG1described inFIG.2and is connected to a gate electrode of the charge transfer unit102avia a contact plug and wiring of the semiconductor substrate120. Similarly, wiring246corresponds to the signal line TG2and is connected to a gate electrode of the charge transfer unit102b. Wiring247corresponds to the signal line TG3and is connected to a gate electrode of the charge transfer unit102c. Wiring245corresponds to the signal line TG4and is connected to a gate electrode of the charge transfer unit102d. Meanwhile, wiring242of the semiconductor substrate220is connected to the charge holding unit103, a gate electrode of the MOS transistor112, and a source region of the MOS transistor111via contact plugs. For convenience, description of other pieces of wiring and the like is omitted.

The wiring244connected to the charge transfer unit102aand the wiring245connected to the charge transfer unit102din the drawing have larger wiring capacitance than the wiring246connected to the charge transfer unit102band the wiring247connected to the charge transfer unit102c. This is due to the proximity to the wiring242. Therefore, the capacitance adjustment units130a,130b,130c, and130dare arranged to correct the wiring capacitances. Specifically, the capacitance adjustment units130band130cadjust and increase the wiring capacitances of the wiring246and247.

[Structure of Cross-Section of Pixel]

FIG.4is a cross-sectional view illustrating a structure example of a pixel according to the first embodiment of the disclosure. The drawing illustrates a simplified structure of a cross section of the pixel100and is a cross-sectional view taken along line a-a′ inFIG.3. As illustrated in the drawing, the imaging element1includes the semiconductor substrates120,220, and320sequentially stacked. Among them, the pixel100is disposed in the semiconductor substrates120and220. The pixel100includes the semiconductor substrates120and220, insulating films128,129, and229, wiring regions140and240, the capacitance adjustment unit130, a color filter171, and an on-chip lens172.

The semiconductor substrate120is a semiconductor substrate in which diffusion regions of a photoelectric conversion unit101(photoelectric conversion units101a,101b,101c, and101d), the charge holding unit103, and a charge transfer unit102(charge transfer units102a,102b,102c, and102d) of the pixel100are formed. The semiconductor substrate120can be made of silicon (Si). In the drawing, the photoelectric conversion units101aand101b, the charge holding unit103, and the charge transfer units102aand102bare illustrated. The diffusion regions of these elements are formed in a well region formed in the semiconductor substrate120. For convenience, it is based on the premise that the semiconductor substrate120in the drawing includes a p-type well region. An element can be disposed by forming an n-type or p-type semiconductor region in the p-type well region. A white rectangle illustrated in the semiconductor substrate120represents an n-type semiconductor region. In the drawing, n-type semiconductor regions121a,121b, and122are illustrated.

The photoelectric conversion unit101aincludes the n-type semiconductor region121a. Specifically, a photodiode including a p-n junction at an interface between the n-type semiconductor region121aand the surrounding p-type well region corresponds to the photoelectric conversion unit101a. In the photoelectric conversion unit101a, electrons of charges generated by photoelectric conversion are accumulated in the n-type semiconductor region121aand transferred by the charge transfer unit102a. Similarly, the photoelectric conversion unit101bincludes the n-type semiconductor region121b.

The charge holding unit103includes the n-type semiconductor region122. The n-type semiconductor region122is a semiconductor region having a relatively high impurity concentration and corresponds to the above-described FD.

The charge transfer unit102aincludes the n-type semiconductor region121a, the n-type semiconductor region122, and a gate electrode125a. In this case, the n-type semiconductor region121aand the n-type semiconductor region122correspond to a source region and a drain region, respectively. Similarly, the charge transfer unit102bincludes the n-type semiconductor region121b, the n-type semiconductor region122, and a gate electrode125b.

The insulating film129is disposed on a front surface of the semiconductor substrate120to insulate and protect the semiconductor substrate120. The insulating film129can be made of, for example, silicon oxide (SiO2). Note that the insulating film129immediately below the gate electrodes125aand125bcorresponds to a gate insulating film.

The wiring region140is disposed on the front surface side of the semiconductor substrate120and is a region in which wiring is disposed. In the wiring region140, an insulating layer141and contact plugs251,252a, and252bdescribed later are arranged. The insulating layer141insulates wiring such as the contact plug251. The insulating layer141can be made of, for example, an insulating material such as SiO2.

The capacitance adjustment units130aand130bare arranged in the vicinity of wiring for transmitting a control signal for the charge transfer unit102and wiring connected to the charge holding unit103and adjust electrostatic capacitance between these pieces of wiring. The capacitance adjustment unit130ais formed into a shape that is connected to the contact plug252aand approaches the contact plug251. Likewise, the capacitance adjustment unit130bis formed into a shape that is connected to the contact plug252band approaches the contact plug251. Details of the configurations of the capacitance adjustment units130aand130bwill be described later.

Note that a barrier layer139(not illustrated) can be disposed on a surface of the capacitance adjustment unit130. The barrier layer139is a film that prevents diffusion of tungsten (W) contained in a contact plug252disposed in a later step into the capacitance adjustment unit130. The barrier layer139can be made of, for example, a laminated film of titanium (Ti) and molybdenum (Mo) or titanium nitride (TiN).

The semiconductor substrate220is a substrate made of a semiconductor on which the image signal generating circuit110is disposed. The semiconductor substrate220is stacked on the semiconductor substrate120. A back surface of the semiconductor substrate220is bonded to a front surface of the wiring region140of the semiconductor substrate120, thereby making the semiconductor substrates120and220to be stacked. Similarly to the semiconductor substrate120, the semiconductor substrate220can be made of Si. As described inFIG.3, the MOS transistors111to113included in the image signal generating circuit110are arranged on the semiconductor substrate220. In the drawing, the MOS transistor112is illustrated. A gate electrode225of the MOS transistor112is disposed on the semiconductor substrate220in the drawing. In addition, the insulating film229is disposed on a front surface of the semiconductor substrate220. The insulating film229immediately below the gate electrode225corresponds to a gate insulating film.

Note that the semiconductor substrate220in the drawing illustrates an example in which a region of the image signal generating circuit110is disposed in an island shape. A region other than the region of the image signal generating circuit110of the semiconductor substrate220is removed by etching. An insulating layer241to be described later is disposed in the region removed by the etching.

The wiring region240is disposed on a front surface side of the semiconductor substrate220. The wiring region240includes wiring (wiring242,243a,243b, and244to248), contact plugs (contact plugs251,252a,252b, and254), via plugs (via plugs253a,253b, and255), and the insulating layer241. The wiring region240further includes a pad249.

Similarly to the insulating layer141, the insulating layer241insulates wiring and others. The insulating layer241can be made of, for example, SiO2.

The wiring242,243a,243b, and244to248transmit signals and the like to the elements of the pixel100. The wiring242,243a,243b, and244to248can be made of metal such as copper (Cu) or W. In addition, the wiring242and others and the insulating layer241can be multiple layers. This drawing illustrates a case where the insulating layer241and the wiring are formed in three layers. The wiring242,243a, and243bis included in a first wiring layer, the wiring244to247is included in a second wiring layer, and the wiring248is included in a third wiring layer. Note that the wiring242illustrated in a divided state in the drawing is included in a single piece of wiring as described inFIG.3.

The contact plugs251,252a,252b, and254electrically connect wiring and a semiconductor substrate. The contact plug251connects the wiring242and the semiconductor region122of the semiconductor substrate120. The contact plug252aconnects the wiring243aand the gate electrode125a, and the contact plug252bconnects the wiring243band the gate electrode125b. The contact plugs252aand252bin the drawing connect the wiring243aand243band the gate electrodes125aand125bvia the capacitance adjustment units130aand130b, respectively. The contact plug254connects the wiring242and the gate electrode225of the semiconductor substrate220. The contact plugs251,252a,252b, and254can be made of, for example, W or the like in a columnar shape.

The via plugs253a,253b, and255electrically connect pieces of wiring arranged in different layers. The via plug253aconnects the wiring243aand the wiring244, and the via plug253bconnects the wiring243band the wiring246. Incidentally, the via plug255connects the wiring248and the pad249.

The pad249is a conductor that transmits a signal to another semiconductor substrate to be bonded. The pad249in the drawing is bonded to a pad249disposed in a wiring region340of the semiconductor substrate320and transmits a signal between the semiconductor substrates220and320. The pad249can be made of Cu, for example.

The semiconductor substrate320is a semiconductor substrate in which circuits other than the pixel array unit10of the imaging element1are arranged. The semiconductor substrate320is stacked on the semiconductor substrate220. A surface of the wiring region340of the semiconductor substrate320is bonded to a surface of the wiring region240of the semiconductor substrate220, thereby making the semiconductor substrates220and320to be stacked. Similarly to the semiconductor substrate120, the semiconductor substrate320can be made of Si.

The wiring region340includes wiring342, a via plug351, a pad349, and an insulating layer341.

The insulating film128is a film that is disposed on a back surface of the semiconductor substrate120to insulate and protect the semiconductor substrate120. The insulating film129can be made of, for example, SiO2.

The color filter171is an optical filter that transmits incident light having a predetermined wavelength among incident light. As the color filter171, color filters171that transmit red light, green light, or blue light can be used.

The on-chip lens172condenses incident light. The on-chip lens172condenses incident light on the photoelectric conversion unit101aor others.

As described above, in the pixel100, the photoelectric conversion unit101aand others are irradiated with incident light from the back surface side of the semiconductor substrate120, and an image signal is generated. Such an imaging element is referred to as a back-illuminated imaging element.

Stacking the semiconductor substrates120and220can be performed by the following steps. First, the wiring region140is formed in the semiconductor substrate120. Next, the front surface of the wiring region140and the back surface of the semiconductor substrate220are activated, overlaid, heated, and pressure-bonded. Thus, the semiconductor substrates120and220are bonded and stacked.

Then, the semiconductor substrate220is ground by chemical mechanical polishing (CMP) to be thinned. Next, a region other than the region of the image signal generating circuit110is removed by etching. Next, the region removed by etching is filled with the insulating layer241. Next, a well region and a semiconductor region are formed in the semiconductor substrate220, and the insulating film229and the gate electrode225are formed. Next, the insulating layer241is disposed on the front surface side of the semiconductor substrate220. Next, an opening is formed in the insulating layer241in a region where the contact plug252aand others are to be formed and filled with W, thereby arranging the contact plug252aand others. Then, the wiring242of the first layer and the insulating layer241are stacked. Next, an opening is formed in the insulating layer241in a region where the via plug253aand others are to be arranged and filled with Cu and others, thereby arranging the wiring244and others of the second layer. Arranging wiring and the insulating layer241is repeated as many layers as necessary, and the pad249is disposed on the surface.

Then, the semiconductor substrate320, in which the wiring region340on which the pad349is disposed on the surface is formed, and the semiconductor substrate220are stacked. For this stacking, the surfaces of the wiring regions240and340are activated, overlaid, heated, and pressure-bonded. At this point, the pads249and349are aligned. As a result, the pad249and the pad349are electrically connected, and the semiconductor substrate220and the semiconductor substrate320are stacked.

Note that the semiconductor substrate120is an example of the first semiconductor substrate described in the claims. The wiring region140is an example of the first wiring region described in the claims. The semiconductor substrate220is an example of the second semiconductor substrate described in the claims. The wiring region240is an example of the second wiring region described in the claims.

[Structure of Capacitance Adjustment Unit]

FIG.5Ais a cross-sectional view illustrating a structure example of a capacitance adjustment unit according to a first embodiment of the disclosure. The drawing is a diagram illustrating a configuration example of the capacitance adjustment unit130b. The capacitance adjustment unit of the present disclosure will be described by taking the capacitance adjustment unit130b(for convenience, it is referred to as a capacitance adjustment unit130) as an example. Note that, in the drawing, the photoelectric conversion unit101, the charge transfer unit102b, the charge holding unit103, and the image signal generating circuit110are illustrated in a simplified manner.

As described above, a capacitance adjustment units130is disposed in the vicinity of wiring for transmitting a control signal for a charge transfer unit102and the wiring connected to the charge holding unit103and adjusts electrostatic capacitance between these pieces of wiring. Hereinafter, wiring that transmits a control signal of the charge transfer unit and the wiring connected to the charge holding unit are referred to as a charge transfer unit signal line and a charge holding unit signal line, respectively.

A charge transfer unit signal line161in the drawing includes the wiring246, the via plug253(via plug253b), a wiring243(wiring243b), and the contact plug252(contact plug252b). The charge transfer unit signal line161transmits a control signal generated by the vertical drive unit20to the charge transfer unit102(charge transfer unit102b). The charge transfer unit signal line161in the drawing is connected to the gate electrode of the charge transfer unit102via the capacitance adjustment unit130.

A charge holding unit signal line162in the drawing includes the wiring242, the contact plug254, and the contact plug251. The charge holding unit signal line162transmits a voltage corresponding to the charge held in the charge holding unit103to the image signal generating circuit110. The charge holding unit signal line162in the drawing is connected to the gate electrode225of the MOS transistor112of the image signal generating circuit110.

The capacitance adjustment unit130in the drawing can be made of a conductor. Specifically, the capacitance adjustment unit130in the drawing can be made of polycrystalline silicon doped with an impurity. Furthermore, the capacitance adjustment unit130in the drawing can be disposed in connection with a gate electrode125(gate electrode125b) of the charge transfer unit102and can have a shape having a region close to the contact plug251. An electrostatic capacitance401between this region and the contact plug251is added in parallel to a wiring capacitance between the charge transfer unit signal line161and the charge holding unit signal line162. With this configuration, the wiring capacitance can be adjusted.

In addition,FIG.5Bis a plan view illustrating the structure example of the capacitance adjustment unit according to the first embodiment of the disclosure. As illustrated in the drawing, the capacitance adjustment unit130can be formed in a rectangular shape in top view. L1in the drawing represents a distance between the capacitance adjustment unit130and the contact plug251. In addition, L2in the drawing represents the width of the capacitance adjustment unit130. Moreover, L3inFIG.5Arepresents the thickness of the capacitance adjustment unit130. The electrostatic capacitance401can be adjusted by adjusting L1, L2, and L3. In the capacitance adjustment units130a,130b,130c, and130d, L1and others are adjusted, and wiring capacitances between respective charge holding unit signal lines162of the charge transfer units102a,102b,102c, and102dand the charge holding unit signal line162are adjusted to equivalent values. As a result, it is possible to reduce variations in the wiring capacitances in the charge transfer units102a,102b,102c, and102dand to reduce variations in the charge transfer.

Note that the capacitance adjustment unit130can be disposed only in a charge transfer unit signal line161of a charge transfer unit102for which adjustment of the wiring capacitance is required. That is, the capacitance adjustment unit130can be arranged in at least one of the charge transfer units102arranged in the pixel100.

Transfer of Charge

FIG.6is a diagram illustrating an example of charge transfer by a charge transfer unit according to an embodiment of the disclosure. The drawing is a diagram illustrating an example of charge transfer in a charge transfer unit102. The upper diagram in the drawing is a cross-sectional view of the charge transfer unit102, and the lower diagram illustrates the potential of the charge transfer unit102. In the lower diagram in the drawing, a black dot represents a charge (electron).

During an exposure period, the charge transfer unit102is in a non-conductive state. At this point, since the potential immediately below a gate electrode of the charge transfer unit102is shallow, a charge generated in a photoelectric conversion unit101is accumulated in a semiconductor region121. When an ON signal is applied to the charge transfer unit102after the lapse of the exposure period, the charge transfer unit102transitions to a conduction state. The potential immediately below the gate electrode125of the charge transfer unit102becomes deeper than the potential of the semiconductor region121of the photoelectric conversion unit101. A dotted line in the lower diagram in the drawing represents the potential in a case where the ON signal is applied. As a result, the charge passes through the charge transfer unit102and is transferred to the semiconductor region122of the charge holding unit103. A dotted arrow in the lower diagram in the drawing represents a state of charge transfer.

When the electrostatic capacitance401between the charge transfer unit signal line161and the charge holding unit signal line162changes, the waveform of the ON signal changes. This also results in a change in the charge transfer of the charge transfer unit102. However, it may seem that a slight change in the electrostatic capacitance401does not significantly affect the charge transfer of the charge transfer unit102.

However, in a case where charge transfer is performed at high speed, such as a case where the imaging element1is driven at a high frame frequency, a change in the electrostatic capacitance401significantly affects the charge transfer. In a relatively short period of time immediately after the charge transfer unit102transitions to the conduction state, the potential of the charge holding unit103also becomes deep. ΔV in the lower diagram in the drawing represents this change in the potential. The change in the potential of the charge holding unit103promotes the charge transfer. As a result, the time required for transferring the charge can be shortened.

However, when the electrostatic capacitance401between the charge transfer unit signal line161and the charge holding unit signal line162changes and the waveform of the ON signal changes, ΔV fluctuates. For example, in a case where the rise time of the ON signal is longer than a period in which the fluctuation of ΔV appears, ΔV becomes substantially 0. In this case, the above-described effect of promoting the charge transfer disappears. Furthermore, in a case where electrostatic capacitances401are different among the plurality of charge transfer units102, the amount of change in the potential also has a different value for each of the charge transfer units102. For this reason, variations in charge transfer of the plurality of charge transfer units102increase. By arranging the capacitance adjustment units130and reducing variations in the electrostatic capacitances401, changes in the potential can be made uniform, and variations in the charge transfer can be reduced.

Manufacturing Method of Capacitance Adjustment Unit

FIGS.7A,7B,7C,7D,7E, and7Fare diagrams illustrating an example of a manufacturing method of the capacitance adjustment unit according to the first embodiment of the present disclosure.FIGS.7A,7B,7C,7D,7E, and7Fare diagrams illustrating an example of manufacturing steps of the capacitance adjustment unit130. First, a well region is formed in the semiconductor substrate120, and the semiconductor regions121and122and others are formed. Next, the insulating film129is disposed on the semiconductor substrate120, and the gate electrode125of the charge transfer unit102is disposed (FIG.7A). Note that sidewalls126are described on the gate electrode125in the drawing.

Next, the insulating layer141is disposed on the front surface side of the semiconductor substrate120(FIG.7B). This can be performed by forming a SiO2film by chemical vapor deposition (CVD) or the like. Note that the insulating layer141may be ground by CMP to have a desired thickness.

Next, an opening501is formed in the insulating layer141adjacent to the gate electrode125(FIG.7C). This can be performed by disposing a resist having an opening in a region where the opening501is formed on a surface of the insulating layer141and etching the insulating layer141. Dry etching can be applied to this etching.

Next, a polycrystalline silicon film502is disposed on the surface of the insulating layer141including the opening501(FIG.7D). This can be performed by forming a film of polycrystalline silicon by CVD. Next, the polycrystalline silicon film502is etched to form the capacitance adjustment unit130(FIG.7E).

Next, the barrier layer139is disposed on the surface of the capacitance adjustment unit130(FIG.7F). This can be performed by forming a material film of the barrier layer139by sputtering or CVD and etching. Note that the barrier layer139can also be disposed in such a manner as to spread over a surface portion138of the gate electrode125. By disposing the barrier layer139on the surface portion138, the connection resistance between the capacitance adjustment unit130and the gate electrode125can be reduced.

Structure of Barrier Layer

FIGS.8A and8Bare diagrams illustrating a structure example of a barrier layer according to the first embodiment of the disclosure.FIGS.8A and8Bare plan views illustrating a structure example of the barrier layer139.FIG.8Ais a diagram illustrating an example of a barrier layer139having substantially the same shape as that of the capacitance adjustment unit130.

FIG.8Bis a diagram illustrating an example of a case where the region where the barrier layer139is disposed on the surface of the gate electrode125is widened. The connection resistance between the capacitance adjustment unit130and the gate electrode125can be reduced as compared with the example ofFIG.8A.

First Modification

FIG.9Ais a cross-sectional view illustrating a first modification of the capacitance adjustment unit according to the first embodiment of the present disclosure.FIG.9Bis a plan view illustrating the first modification of the capacitance adjustment unit according to the first embodiment of the disclosure. A capacitance adjustment unit130inFIGS.9A and9Billustrate an example in which a region in contact with a gate electrode125is reduced as compared with the capacitance adjustment unit130inFIGS.5A and5B. A contact plug252is directly connected to the gate electrode125.

Second Modification

FIG.10Ais a cross-sectional view illustrating a second modification of the capacitance adjustment unit according to the first embodiment of the present disclosure.FIG.10Bis a plan view illustrating the second modification of the capacitance adjustment unit according to the first embodiment of the disclosure. A capacitance adjustment unit130inFIGS.10A and10Billustrate an example in which a step of the capacitance adjustment unit130inFIGS.5A and5Bare reduced. Since the capacitance adjustment unit130is disposed close to a semiconductor region122of a charge holding unit103, an electrostatic capacitance401can be increased as compared with the capacitance adjustment unit130inFIGS.5A and5B. The adjustment range of the electrostatic capacitance401by the capacitance adjustment unit130can be expanded.

Third Modification

FIGS.11A and11Bare cross-sectional views illustrating a third modification of the capacitance adjustment unit according to the first embodiment of the present disclosure. A capacitance adjustment unit130inFIGS.11A and11Billustrate an example of the capacitance adjustment unit130arranged at a position separated from a gate electrode125.FIG.11Ais a diagram illustrating an example in which a contact plug252is formed in a shape that penetrates the capacitance adjustment unit130and is connected to the gate electrode125. Moreover,FIG.11Bis a diagram illustrating an example in which the capacitance adjustment unit130and the gate electrode125are connected by a columnar connection portion137formed at the bottom of the capacitance adjustment unit130. The contact plug252is connected to the capacitance adjustment unit130. In these examples, the capacitance adjustment unit130is disposed at a position separated from a semiconductor region122included in a charge holding unit103, and the influence of a distance between the capacitance adjustment unit130and the semiconductor region122on the electrostatic capacitance401can be reduced. Note that the planar structure of the plane of the capacitance adjustment unit130inFIGS.11A and11Bcan adopt the same structure as that inFIG.10B.

Fourth Modification

FIG.12is a plan view illustrating a fourth modification of the capacitance adjustment unit according to the first embodiment of the disclosure. The drawing a diagram illustrating a planar structure of the capacitance adjustment unit130similarly toFIG.10B. This differs from the capacitance adjustment unit130inFIG.10Bin that a face facing the contact plug251is expanded. The capacitance adjustment unit130in the drawing can improve the electrostatic capacitance401. Note that the cross-sectional structure of the capacitance adjustment unit130can adopt a structure similar to that of the capacitance adjustment unit130inFIG.11B.

Note that the configuration of the imaging element1according to the first embodiment of the disclosure is not limited to this example. For example, two sets of a photoelectric conversion unit101and a charge transfer unit102may be arranged in a pixel100.

As described above, in the imaging element1according to the first embodiment of the present disclosure, the capacitance adjustment unit130is disposed to adjust the electrostatic capacitance401between the charge holding unit signal lines162connected to the respective charge transfer units102of the pixel100and the charge holding unit signal line162connected to the charge holding unit103. As a result, it is possible to reduce variations in the electrostatic capacitances401between the plurality of charge transfer unit signal lines161and the charge holding unit signal line162. It is possible to reduce variations in charge transfer in the plurality of charge transfer units arranged in the pixel100.

2. Second Embodiment

In the imaging element1of the first embodiment described above, the capacitance adjustment unit130is disposed in the charge transfer unit signal line161of the pixel100. On the other hand, an imaging element1according to a second embodiment of the present disclosure is different from the first embodiment in that a capacitance adjustment unit connected to a charge holding unit signal line162is further disposed.

Structure of Capacitance Adjustment Unit

FIG.13Ais a cross-sectional view illustrating a structure example of a capacitance adjustment unit according to the second embodiment of the disclosure.FIG.13Bis a plan view illustrating the structure example of the capacitance adjustment unit according to the second embodiment of the disclosure. A pixel100inFIGS.13A and13Bare different from the pixel100inFIGS.5A and5Bin further including a capacitance adjustment unit150.

The capacitance adjustment unit150is connected to a charge holding unit signal line162and adjusts the electrostatic capacitance with respect to a charge transfer unit signal line161. A contact plug251in the drawing is formed in a shape penetrating the capacitance adjustment unit150, and the capacitance adjustment unit150is connected to the contact plug251. The capacitance adjustment unit150has an effect of increasing the area of a portion in the contact plug251facing a capacitance adjustment unit130. The capacitance adjustment unit150can be made of a member similar to that of the capacitance adjustment unit130.

First Modification

FIG.14is a cross-sectional view illustrating a first modification of the capacitance adjustment unit according to the second embodiment of the disclosure. The drawing illustrates an example in which a capacitance adjustment unit130is disposed separated from a gate electrode125, similarly to the capacitance adjustment unit130inFIG.10A. A capacitance adjustment unit150is disposed at the same level as the capacitance adjustment unit130.

Second Modification

FIG.15Ais a cross-sectional view illustrating a second modification of the capacitance adjustment unit according to the second embodiment of the present disclosure. A capacitance adjustment unit150in the drawing includes a connection portion137similarly to the capacitance adjustment unit150inFIG.11B. In addition, the capacitance adjustment unit150in the drawing includes a connection portion157connected to a semiconductor region122of a charge holding unit103and is at the same level as that of a capacitance adjustment unit130.

FIG.15Bis a plan view illustrating the second modification of the capacitance adjustment unit according to the second embodiment of the disclosure. The capacitance adjustment unit130in the drawing illustrates an example in which a region facing the charge holding unit signal line162is formed in a U-shape surrounding the capacitance adjustment unit150. In the capacitance adjustment unit130in the drawing, a region facing the capacitance adjustment unit150can be widened, and the electrostatic capacitances401can be increased.

The configuration of the imaging element1other than the above is similar to the configuration of the imaging element1in the first embodiment of the present disclosure, and thus description thereof is omitted.

As described above, in the imaging element1according to the second embodiment of the present disclosure, the capacitance adjustment unit130and the capacitance adjustment unit150are arranged in the charge transfer unit signal line161and the charge holding unit signal line162of the pixel100, respectively, and the electrostatic capacitances401are adjusted.

3. Third Embodiment

In the imaging element1of the first embodiment described above, the capacitance adjustment unit130is disposed in the charge transfer unit signal line161of the pixel100. On the other hand, an imaging element1according to a third embodiment of the present disclosure is different from the first embodiment in that a capacitance adjustment unit is disposed in a charge holding unit signal line162.

Structure of Capacitance Adjustment Unit

FIG.16Ais a cross-sectional view illustrating a structure example of a capacitance adjustment unit according to the third embodiment of the disclosure.FIG.16Bis a plan view illustrating the structure example of the capacitance adjustment unit according to the third embodiment of the disclosure. A pixel100inFIGS.16A and16Bare different from the pixel100inFIGS.5A and5Bin including a capacitance adjustment unit150instead of the capacitance adjustment unit130.

The capacitance adjustment unit150in the drawing includes a connection portion157similarly to the capacitance adjustment unit150inFIG.15A. In addition, the capacitance adjustment unit150in the drawing has an end portion extended to a position overlapping a gate electrode125.

First Modification

FIG.17Ais a cross-sectional view illustrating a first modification of the capacitance adjustment unit according to the third embodiment of the disclosure.FIG.17Bis a plan view illustrating the first modification of the capacitance adjustment unit according to the third embodiment of the disclosure. As illustrated inFIG.17B, it is a diagram illustrating an example in which a capacitance adjustment unit150in the drawing has a shape in which a region facing a contact plug252is expanded.

Second Modification

FIG.18is a plan view illustrating a second modification of the capacitance adjustment unit according to the third embodiment of the disclosure. The capacitance adjustment unit150in the drawing illustrates an example in which a region facing a contact plug252is further expanded as compared with that in the capacitance adjustment unit150inFIG.17B.

The configuration of the imaging element1other than the above is similar to the configuration of the imaging element1in the first embodiment of the present disclosure, and thus description thereof is omitted.

As described above, in the imaging element1according to the third embodiment of the present disclosure, the capacitance adjustment unit150is disposed in a charge holding unit signal line162of the pixel100to adjust an electrostatic capacitance401.

4. Fourth Embodiment

In the imaging element1of the first embodiment described above, the capacitance adjustment unit130is disposed in the charge transfer unit signal line161of the pixel100. On the other hand, an imaging element1according to a fourth embodiment of the present disclosure is different from the above-described first embodiment in that a capacitance adjustment unit is disposed between a charge transfer unit signal line161and a charge holding unit signal line162.

Structure of Capacitance Adjustment Unit

FIG.19Ais a cross-sectional view illustrating a structure example of a capacitance adjustment unit according to the fourth embodiment of the disclosure.FIG.19Bis a plan view illustrating the structure example of the capacitance adjustment unit according to the fourth embodiment of the disclosure. The pixel100inFIGS.19A and19Bare different from the pixel100inFIGS.5A and5Bin including a capacitance adjustment unit160instead of the capacitance adjustment unit130.

The capacitance adjustment unit160is disposed between a charge transfer unit signal line161and a charge holding unit signal line162and adjusts an electrostatic capacitance401between the charge transfer unit signal line161and the charge holding unit signal line162. As illustrated inFIGS.19A and19B, since the capacitance adjustment unit160is not connected to either the charge transfer unit signal line161or the charge holding unit signal line162, a capacitance component is formed between the charge transfer unit signal line161and the charge holding unit signal line162. Let an electrostatic capacitance between the capacitance adjustment unit160and a contact plug252and an electrostatic capacitance between the capacitance adjustment unit160and a contact plug251be electrostatic capacitances402and403, respectively, and the electrostatic capacitance401between the contact plugs251and252can be expressed by the following equation.
C401=C402×C403/(C402+C403)

Incidentally, C401represents the value of the electrostatic capacitance401. C402represents the value of the electrostatic capacitance402. C403represents the value of the electrostatic capacitance403. As the above, the electrostatic capacitance401has an electrostatic capacitance value in a case where the electrostatic capacitances402and403are connected in series.

The capacitance adjustment unit160can be made of a conductor, for example, polycrystalline silicon doped with an impurity. In this case, an effect is achieved that the distance between the contact plugs251and252is shortened by the length of the capacitance adjustment unit160in the vicinity of the capacitance adjustment unit160. That is, by disposing the capacitance adjustment unit160, the electrostatic capacitance401between the contact plugs251and252increases. By adjusting the size of the capacitance adjustment unit160, the electrostatic capacitance401between the contact plugs251and252can be adjusted.

Note that a contact plug259is disposed in the capacitance adjustment unit160in the drawing, and a signal different from signals transmitted by the contact plugs251and252can be applied to the capacitance adjustment unit160. Alternatively, the contact plug259can be omitted to make the capacitance adjustment unit160to be in a floating state.

Further alternatively, the capacitance adjustment unit160may be made of an insulating material (dielectric). At this point, by making the capacitance adjustment unit160to have a dielectric constant different from that of an insulating layer141, the electrostatic capacitance401between the contact plugs251and252can be adjusted. This is because the electrostatic capacitance401is configured by connecting capacitors including dielectrics having different dielectric constants in series. The capacitance adjustment unit160can be made of, for example, polycrystalline silicon. This is because polycrystalline silicon that is not doped with an impurity behaves as a dielectric. In addition, characteristics of polycrystalline silicon can change from those of an insulating material to those of a conductor by adjusting the doping amount of an impurity. That is, it is possible to obtain a dielectric constant corresponding to the doping amount of the impurity. Therefore, the electrostatic capacitance401can be adjusted by disposing the capacitance adjustment unit160made of polycrystalline silicon and adjusting the doping amount of the impurity.

The configuration of the imaging element1other than the above is similar to the configuration of the imaging element1in the first embodiment of the present disclosure, and thus description thereof is omitted.

As described above, in the imaging element1according to the fourth embodiment of the present disclosure, the electrostatic capacitance401can be adjusted by the capacitance adjustment unit160disposed between the charge transfer unit signal line161and the charge holding unit signal line162of the pixel100.

5. Fifth Embodiment

In the imaging element1of the first embodiment described above, one charge holding unit103is shared by four pairs of a photoelectric conversion unit101and a charge transfer unit102. On the other hand, an imaging element1according to a fifth embodiment of the present disclosure is different from the first embodiment in that a charge holding unit103is disposed for each pair of a photoelectric conversion unit101and a charge transfer unit102.

Configuration of Pixel

FIG.20is a diagram illustrating a configuration example of a pixel according to the fifth embodiment of the disclosure. The drawing is a circuit diagram illustrating a configuration example of a pixel100similarly toFIG.2. The pixel100in the drawing is different from the pixel100inFIG.2in including four charge holding units.

The pixel100in the drawing includes charge holding units103a,103b,103c, and103d. The charge holding units103a,103b,103c, and103dhold charges transferred by charge transfer units102a,102b,102c, and102d, respectively. Note that the charge holding units103a,103b,103c, and103dare connected in parallel and connected to the same node.

Structure of Cross-Section of Pixel

FIG.21is a cross-sectional view illustrating a structure example of a pixel according to the fifth embodiment of the disclosure. The drawing is a cross-sectional view illustrating a structure example of a pixel100similarly toFIG.4. The pixel100in the drawing is different from the pixel100inFIG.4in that charge holding units103aand103bare arranged instead of the charge holding unit103.

In a semiconductor substrate120in the drawing, semiconductor regions122aand122bincluded in the charge holding units103aand103bare formed. These semiconductor regions are formed by dividing a single semiconductor region122into four by a separation unit180. In this example, the separation unit180is obtained by embedding an insulating material in a groove portion penetrating the semiconductor substrate120formed from a back surface side of the semiconductor substrate120and separates the semiconductor region. Contact plugs251aand251bare connected to the semiconductor regions122aand122b, respectively. The contact plugs251aand251bare connected to wiring242in a shared manner. Capacitance adjustment units130aand130bin the drawing are arranged close to the contact plugs251aand251b, respectively, and adjust variations in the electrostatic capacitances401.

The configuration of the imaging element1other than the above is similar to the configuration of the imaging element1in the first embodiment of the present disclosure, and thus description thereof is omitted.

As described above, in the imaging element1according to the fifth embodiment of the present disclosure, in a case where a plurality of charge holding units103is disposed in a pixel100, it is possible to reduce variations in the charge transfer in a plurality of charge transfer units arranged in the pixel100.

6. Application Examples to Imaging Device

The technology according to the present disclosure can be applied to various products. For example, the technology according to the disclosure can be applied to imaging devices such as cameras.

FIG.22is a diagram illustrating an exemplary configuration of an imaging device to which the technology according to the disclosure can be applied. An imaging device1000in the drawing includes an imaging element1001, a control unit1002, an image processing unit1003, a display unit1004, a recording unit1005, and an imaging lens1006.

The imaging lens1006is a lens that collects light from a subject. The subject is imaged on a light receiving plane of the imaging element1001by the imaging lens1006.

The imaging element1001captures an image of a subject. A plurality of pixels including a photoelectric conversion unit that performs photoelectric conversion of light from a subject is arranged on the light receiving plane of the imaging element1001. Each of the plurality of pixels generates an image signal based on a charge generated by photoelectric conversion. The imaging element1001converts image signals generated by the pixels into digital image signals and outputs the digital image signals to the image processing unit1003. Note that image signals for one screen are referred to as a frame. The imaging element1001can also output image signals frame by frame.

The control unit1002controls the imaging element1001and the image processing unit1003. The control unit1002can include, for example, an electronic circuit using a microcomputer or the like.

The image processing unit1003processes an image signal from the imaging element1001. The processing of an image signal in the image processing unit1003corresponds to, for example, demosaic processing of generating an image signal of a color that is insufficient when a color image is generated or noise reduction processing of removing noise of the image signal. The image processing unit1003can include, for example, an electronic circuit using a microcomputer or the like.

The display unit1004displays an image on the basis of the image signals processed by the image processing unit1003. The display unit1004can include, for example, a liquid crystal monitor.

The recording unit1005records an image (frame) based on the image signals processed by the image processing unit1003. The recording unit1005can include, for example, a hard disk or a semiconductor memory.

The imaging device to which the present disclosure can be applied has been described above. The present technology can be applied to the imaging element1001among the above-described components. Specifically, the imaging element1described inFIG.1can be applied to the imaging element1001. Note that the imaging element1001is an example of the imaging element described in the claims. Moreover, that the image processing unit1003is an example of the processing circuit described in the claims. Furthermore, the imaging device1000is an example of the imaging device described in the claims.

Note that the configuration of the fifth embodiment of the present disclosure can be applied to other embodiments. Specifically, the configuration of the pixel100including the charge holding units103a,103b,103c, and103dinFIG.20can be applied to the second to fourth embodiments of the present disclosure.

Effects

An imaging element1includes a plurality of photoelectric conversion units101, a plurality of charge transfer units102, an image signal generating circuit110, charge transfer unit signal lines161, a charge holding unit signal line162, and a capacitance adjustment unit130. A photoelectric conversion unit101is disposed in a semiconductor substrate120in which a wiring region140is formed on a front surface side and performs photoelectric conversion of incident light to generate a charge. A charge holding unit103is disposed on the semiconductor substrate120and holds the generated charge. A charge transfer unit102is disposed for each of the photoelectric conversion units101and transfers the generated charge to the charge holding unit103. The image signal generating circuit110is disposed in the semiconductor substrate220stacked on the semiconductor substrate120on a back surface side with a wiring region240formed on the front surface side and generates an image signal on the basis of the held charge. A charge transfer unit signal line161includes wiring disposed in the wiring region240and wiring disposed in the wiring region140and is disposed for each of the plurality of charge transfer units102to transmit a control signal. The charge holding unit signal line162includes wiring arranged in the wiring region240and wiring arranged in the wiring region140and transmits a voltage corresponding to the charge held in the charge holding unit103to the image signal generating circuit110. The capacitance adjustment unit130is disposed in the vicinity of at least one of the plurality of charge transfer unit signal lines161and the charge holding unit signal line162in the wiring region140and adjusts an electrostatic capacitance between the charge transfer unit signal line161and the charge holding unit signal line162. As a result, the wiring capacitance of a control signal disposed in a pixel100can be adjusted.

Furthermore, the charge holding unit103may be arranged for each of the plurality of photoelectric conversion units101, and the plurality of charge transfer units102may transfer the generated charges to the respective charge holding units103. As a result, it is possible to adjust the electrostatic capacitance between a charge transfer unit signal line161and a charge holding unit signal line162of a charge holding unit103disposed for each of the photoelectric conversion units101.

Furthermore, the capacitance adjustment unit130may be connected to a charge transfer unit signal line161. As a result, the electrostatic capacitance with the charge holding unit signal line162can be adjusted by the capacitance adjustment unit130connected to the charge transfer unit signal line161.

Furthermore, the capacitance adjustment unit130may be disposed adjacent to a gate electrode of a MOS transistor included in a charge transfer unit102.

Furthermore, the capacitance adjustment unit130may be connected to the charge holding unit signal line162.

Alternatively, the capacitance adjustment unit130may be disposed in such a manner as to be insulated from the charge transfer unit signal lines161and the charge holding unit signal line162. Accordingly, connection with the capacitance adjustment unit130can be omitted.

In addition, the capacitance adjustment unit130may be made of a conductor. As a result, the electrostatic capacitance between the charge holding unit signal line162and the charge transfer unit signal line161can be adjusted by adjusting the shape of the capacitance adjustment unit130.

In addition, the capacitance adjustment unit may have a dielectric constant different from that of an insulating layer disposed in the first wiring region. As a result, the electrostatic capacitance between the charge holding unit signal line162and the charge transfer unit signal line161can be adjusted by adjusting the dielectric constant of the capacitance adjustment unit130.

Incidentally, the capacitance adjustment unit may be made of silicon. This makes it possible to apply a high-temperature process in the manufacturing steps.

An imaging element1includes a plurality of photoelectric conversion units101, a plurality of charge transfer units102, an image signal generating circuit110, charge transfer unit signal lines161, a charge holding unit signal line162, a capacitance adjustment unit130, and a control signal generating circuit (vertical drive unit20). A photoelectric conversion unit101is disposed in a semiconductor substrate120in which a wiring region140is formed on a front surface side and performs photoelectric conversion of incident light to generate a charge. A charge holding unit103is disposed on the semiconductor substrate120and holds the generated charge. A charge transfer unit102is disposed for each of the photoelectric conversion units101and transfers the generated charge to the charge holding unit103. The image signal generating circuit110is disposed in the semiconductor substrate220stacked on the semiconductor substrate120on a back surface side with a wiring region240formed on the front surface side and generates an image signal on the basis of the held charge. A charge transfer unit signal line161includes wiring disposed in the wiring region240and wiring disposed in the wiring region140and is disposed for each of the plurality of charge transfer units102to transmit a control signal. The charge holding unit signal line162includes wiring arranged in the wiring region240and wiring arranged in the wiring region140and transmits a voltage corresponding to the charge held in the charge holding unit103to the image signal generating circuit110. The capacitance adjustment unit130is disposed in the vicinity of at least one of the plurality of charge transfer unit signal lines161and the charge holding unit signal line162in the wiring region140and adjusts an electrostatic capacitance between the charge transfer unit signal line161and the charge holding unit signal line162. The control signal generating circuit (vertical drive unit20) generates the control signal and outputs the control signal to the charge transfer unit signal line. As a result, the wiring capacitance of a control signal disposed in a pixel100can be adjusted.

Note that the effects described herein are merely examples and are not limited, and other effects may also be achieved.

Note that the present technology can also have the following configurations.

(1)

An imaging element comprising:a plurality of photoelectric conversion units that performs photoelectric conversion of incident light and generates a charge, the plurality of photoelectric conversion units arranged in a first semiconductor substrate having a first wiring region formed on a front surface side;a charge holding unit that holds the generated charges, the charge holding unit disposed in the first semiconductor substrate;a plurality of charge transfer units that transfers the generated charges to the charge holding unit, the plurality of charge transfer units each disposed for one of the photoelectric conversion units;an image signal generating circuit that generates an image signal on a basis of the held charge, the image signal generating circuit disposed in a second semiconductor substrate stacked on the first semiconductor substrate on a back surface side with a second wiring region formed on a front surface side;a plurality of charge transfer unit signal lines that each transmits a control signal, the plurality of charge transfer unit signal lines comprising wiring disposed in the second wiring region and wiring disposed in the first wiring region, the plurality of charge transfer unit signal lines each disposed for one of the plurality of charge transfer units;a charge holding unit signal line that transmits a voltage corresponding to a charge held in the charge holding unit to the image signal generating circuit, the charge holding unit signal line comprising wiring disposed in the second wiring region and wiring disposed in the first wiring region; anda capacitance adjustment unit that is disposed in a vicinity of at least one of the plurality of charge transfer unit signal lines and the charge holding unit signal line in the first wiring region and adjusts an electrostatic capacitance between the charge transfer unit signal line and the charge holding unit signal line.
(2)

The imaging element according to the above (1),wherein the charge holding unit is disposed for each of the plurality of photoelectric conversion units, andthe plurality of charge transfer units transfers the generated respective charges to the respective charge holding units.
(3)

The imaging element according to the above (1) or (2), wherein the capacitance adjustment unit is connected to a charge transfer unit signal line.

(4)

The imaging element according to the above (3), wherein the capacitance adjustment unit is disposed adjacent to a gate electrode of a MOS transistor comprised in the charge transfer unit.

(5)

The imaging element according to the above (1) or (2), wherein the capacitance adjustment unit is connected to the charge holding unit signal line.

(6)

The imaging element according to the above (1) or (2), wherein the capacitance adjustment unit is disposed in such a manner as to be insulated from the charge transfer unit signal lines and the charge holding unit signal line.

(7)

The imaging element according to the above (6), wherein the capacitance adjustment unit is made of a conductor.

(8)

The imaging element according to the above (6), wherein the capacitance adjustment unit has a dielectric constant different from a dielectric constant of an insulating layer disposed in the first wiring region.

(9)

The imaging element according to any one of the above (1) to (8), wherein the capacitance adjustment unit is made of silicon.

(10)

An imaging device comprising:a plurality of photoelectric conversion units that performs photoelectric conversion of incident light and generates a charge, the plurality of photoelectric conversion units arranged in a first semiconductor substrate having a first wiring region formed on a front surface side;a charge holding unit that holds the generated charges, the charge holding unit disposed in the first semiconductor substrate;a plurality of charge transfer units that transfers the generated charges to the charge holding unit, the plurality of charge transfer units each disposed for one of the photoelectric conversion units;an image signal generating circuit that generates an image signal on a basis of the held charge, the image signal generating circuit disposed in a second semiconductor substrate stacked on the first semiconductor substrate on a back surface side with a second wiring region formed on a front surface side;a plurality of charge transfer unit signal lines that each transmits a control signal, the plurality of charge transfer unit signal lines comprising wiring disposed in the second wiring region and wiring disposed in the first wiring region, the plurality of charge transfer unit signal lines each disposed for one of the plurality of charge transfer units;a charge holding unit signal line that transmits a voltage corresponding to a charge held in the charge holding unit to the image signal generating circuit, the charge holding unit signal line comprising wiring disposed in the second wiring region and wiring disposed in the first wiring region;a capacitance adjustment unit that is disposed in a vicinity of at least one of the plurality of charge transfer unit signal lines and the charge holding unit signal line in the first wiring region and adjusts an electrostatic capacitance between the charge transfer unit signal line and the charge holding unit signal line; anda control signal generating circuit that generates the control signals and outputs the control signals to the charge transfer unit signal lines.
(11)

The imaging device according to the above (10), further comprising a processing circuit that processes the image signal.

REFERENCE SIGNS LIST

1,1001IMAGING ELEMENT10PIXEL ARRAY UNIT20VERTICAL DRIVE UNIT30COLUMN SIGNAL PROCESSING UNIT100PIXEL101,101a,101b,101c,101dPHOTOELECTRIC CONVERSION UNIT102,102a,102b,102c,102dCHARGE TRANSFER UNIT103,103a,103b,103c,103dCHARGE HOLDING UNIT110IMAGE SIGNAL GENERATING CIRCUIT120,220,320SEMICONDUCTOR SUBSTRATE130,130a,130b,130c,130dCAPACITANCE ADJUSTMENT UNIT140,240,340WIRING REGION141,241,341INSULATING LAYER150,160CAPACITANCE ADJUSTMENT UNIT161CHARGE TRANSFER UNIT SIGNAL LINE162CHARGE HOLDING UNIT SIGNAL LINE180SEPARATION UNIT242,243a,243b,244to248,342WIRING251,251a,251b,252,252a,252b,254,259CONTACT PLUG253,253a,253b,255,351VIA PLUG1000IMAGING DEVICE1003IMAGE PROCESSING UNIT