Patent ID: 12191127

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

PVD is an appropriate and widely-used process to form a thin film on a substrate (i.e., a wafer). Typically, the apparatus for performing a PVD operation includes a chamber and a process kit. The chamber may include a chamber wall and a pedestal, and the process kit may be placed within the chamber to prevent undesirable material deposition on the chamber components, such as the chamber wall and the pedestal.

Usually, the process kit includes a deposition ring. The deposition ring is disposed on the pedestal. A wafer may be disposed on the pedestal and an edge of the wafer may be above at least a portion of the deposition ring. During a PVD process for forming, for example but not limited to, a layer on the wafer, a problem recognized as arcing may occur. Arcing can be caused by factors such as contamination or residue over a surface of the wafer. It is found that the contamination or residues may cause local charge accumulation and thus serve as a potential arcing source. When a path is established from the wafer (i.e., where the residue exists) to the target through electrons or ions in the plasma, the arcing is caused. Arcing during PVD can cause a local thicker deposition of target material on the wafer. For example, an unwanted local thicker layer may be formed over a wafer edge.

In some comparative embodiments, extra cleaning operations may be performed to remove the residue, which serves as the potential arcing source, before the PVD operation. This approach may mitigate the arcing problem, but an overall throughput is reduced and process cost is increased. In other comparative embodiments, degassing time during the PVD operation is extended or a degassing temperature during the PVD operation is increased in order to mitigate the arcing problem, but the PVD operation throughput is reduced and energy consumption is increased. In still other comparative embodiments, discharge power is reduced in order to reduce charge accumulation, but this approach suffers from reduced PVD throughput. In summary, although apparatus designers have attempted to prevent arcing problem during PVD operation by making the above-mentioned modifications, none of these approaches can effectively reduce the arcing without increasing process time, energy consumption and cost, or without reducing the overall throughput.

The present disclosure therefore provides an apparatus for PVD to mitigate the arcing issue without reducing PVD throughput, increasing process cost, or increasing energy consumption. In some embodiments, a deposition ring including a barrier structure is provided. The barrier structure of the deposition ring is able to alter electron density distribution such that the path from the wafer (e.g., where the residue exists or the wafer edge) to the target through electrons or ions in the plasma may not be formed. Accordingly, arcing can be mitigated even though there is residue over the wafer.

FIG.1is a schematic drawing illustrating an apparatus for PVD100according to aspects of one or more embodiments of the present disclosure. It will be appreciated that although an apparatus is illustrated as having components specific for a PVD process, the aspects of the disclosed apparatus may be applied to any type of processing operation that utilizes plasma. For example, the disclosed aspects may be applied to a plasma-enhanced chemical vapor deposition (PECVD) operation or plasma etching operation.

Referring toFIG.1, the apparatus for PVD100includes a chamber wall102, a plasma source104, a pedestal110, a target130and a process kit140disposed within the chamber wall102. The chamber wall102can be a stainless steel chamber body that is vacuum-tight, and a chamber106is enclosed within the chamber wall102. The plasma source104is configured to provide plasma to the chamber106. In some embodiments, the plasma source104may include an upstream source located external to the chamber106, as shown inFIG.1. In some alternative embodiments, the plasma source104can be located within the chamber106. The pedestal110, also referred to as wafer stage or a substrate support, is disposed within the chamber wall102for supporting and accommodating a workpiece, such as a wafer, to be processed. In some embodiments, the pedestal110may include an electrostatic chuck (ESC)112and/or a heater (not shown). In some embodiments, an RF bias power source114may be coupled to the pedestal110in order to induce a negative DC bias on the workpiece. In other embodiments, the pedestal110may be grounded or left electrically floating. In some embodiments, the apparatus for PVD100further includes a communication interface (not shown), for example, a monitor, showing the required operation parameters of the current deposition operation.

Referring toFIG.1, the target130may have a sputtering surface. A power supply132can be electrically connected to the target130. In various embodiments of the present disclosure, the power supply132is a DC supply, an RF power supply, or a DC-RF power supply. The target130is posed of metal or metal alloys which are predetermined to be deposited onto the wafer120. The target130may be composed of any suitable and appropriate source material including, for example but not limited thereto, nickel (Ni), nickel platinum (Ni Pt) alloys, nickel titanium (Ni Ti) alloys, cobalt (Co), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), indium tin oxide (ITO), zinc sulfide-silicon dioxide (ZnS—SiO2), gold (Au), silver (Ag) and other noble metals.

Still referring toFIG.1, the process kit140may be placed within the chamber wall102to prevent material from being deposited on the chamber components, such as the chamber wall102and the pedestal110. Specifically, the process kit140includes a first ring150or151, a second ring160and a wall shield170. In some embodiments, the first ring150or151can be a deposition ring150/151and may include an annular band surrounding the pedestal110. The second ring160, such as a cover ring160, also referred to as a clamp ring, may at least partially cover the deposition ring150. In some embodiments, the cover ring160holds the wafer120in place on the pedestal110when a positive gas pressure is applied between the heater and the pedestal110such that heat can be efficiently conducted from the heater to the wafer120. Another function served by the cover ring160is to allow a predetermined flow of argon to leak from under the wafer120into the chamber106. The cover ring160is constructed with an annular shape with an oriented cut-out to match a wafer's flat side. As shown inFIG.1, the wall shield170forms a seal between the cover ring160and the chamber wall102to reduce the contamination of the chamber wall102resulting from the particles sputtered from the target130.

The wall shield170helps to prevent or minimize depositing of target material films on the interior surfaces of the chamber wall102. The wall shield170may include an annular attachment portion which is mounted to the chamber wall102, an annular vertical portion which extends downwardly from the attachment portion; and an annular horizontal portion which extends inwardly from the vertical portion.

As shown inFIG.1, the deposition ring150or151can be disposed on the pedestal110and may be at least partially covered by the cover ring160.

Please refer toFIGS.2to5, which are schematic drawings illustrating a deposition ring according to aspects of one or more embodiments of the present disclosure. As shown inFIGS.2and3, the deposition ring150includes a ring body152having a first top surface154aand a second top surface154b, and a barrier structure156disposed between the first top surface154aand the second top surface154b. In some embodiments, an innermost surface153of the ring body152, which is an annular surface, may be in contact with electrostatic chuck (ESC)112or pedestal110, but the disclosure is not limited thereto. In some embodiments, the first top surface154ais an annular surface coupled to the innermost surface153, the barrier structure156is an annular structure surrounding the first top surface154a, and the second top surface154bis an annular surface surrounding the first top surface154aand the barrier structure156. In some embodiments, the ring body152and the barrier structure156are monolithic. In some embodiments, the ring body152and the barrier structure156include a same material, such as a conductive material. For example but not limited thereto, the ring body152and the barrier structure156may include stainless steel, but the disclosure is not limited thereto. In some embodiments, an insulating film158is disposed over the barrier structure156, as shown inFIG.3. In some embodiments, the insulating film158includes aluminum oxide (AlXOY) or aluminum nitride (AlXNY), but the disclosure is not limited thereto. Additionally, a bottom of the ring body152may have a step height, as shown inFIG.2, in order to help to secure the ring body152over the pedestal110, but the disclosure is not limited thereto. In other embodiments, the bottom of the ring body152can have a flat surface, though not shown.

The barrier structure156is separated from the first top surface154aby a horizontal distance DH, which is defined between a vertical sidewall of the barrier structure156that faces the first top surface154aand a vertical wall of the ring body152that is coupled to the first top surface154aand faces the barrier structure156, as shown inFIG.2. In other embodiments, when the barrier structure156includes the insulating film158, the horizontal distance DHis defined between a vertical surface of the insulating film158that faces the first top surface154aand the vertical wall of the ring body152that is coupled to the first top surface154aand faces the barrier structure156, as shown inFIGS.3to5. In some embodiments, the horizontal distance DHis greater than 0.

As shown inFIGS.2to5, in some embodiments, a first vertical distance DV1is defined between a top surface of the barrier structure156and the first top surface154aof the ring body152, and a second vertical distance DV2is defined between the top surface of the barrier structure156and the second top surface154bof the ring body152, as shown inFIG.2. In some embodiments, when the barrier structure156includes the insulating film158, the top surface is a surface of the insulating film158. Accordingly, the first vertical distance DV1is defined between the top surface of the insulating film158of the barrier structure156and the first top surface154aof the ring body152, and the second vertical distance DV2is defined between the top surface of the insulating film158of the barrier structure156and the second top surface154bof the ring body152, as shown inFIGS.3to5.

In some embodiments, the first top surface154aand the second top surface154bof the ring body152are not coplanar with each other. For example, the first top surface154ais higher than the second top surface154b, as shown inFIGS.2and3. In some embodiments, the first vertical distance DV1and the second vertical distance DV2are different from each other, as shown inFIGS.2and3. In some embodiments, both of the first and second vertical distances DV1and DV2are greater than 0, and the second vertical distance DV2is greater than the first vertical distance DV1, as shown inFIGS.2and3. In addition, a groove159may be disposed between the barrier structure156and the first top surface154a. Shapes of the barrier structure156or the groove159can be modified. The modified shapes are also included in the scope of the present disclosure.

In some embodiments, the first top surface154aand the second top surface154bof the ring body152are coplanar with each other, as shown inFIG.4. In some embodiments, the first vertical distance DV1and the second vertical distance DV2are the same, as shown inFIG.4. In such embodiments, both of the first and second vertical distances DV1and DV2are greater than 0. In addition, a groove159may be disposed between the barrier structure156and the first top surface154a. Shapes of the barrier structure156or the groove159can be modified. The modified shapes are also included in the scope of the present disclosure.

Referring toFIG.5, in some embodiments, the first top surface154aand the second top surface154bof the ring body152are not coplanar with each other. For example, the first top surface154ais higher than the second top surface154b, as shown inFIG.5. In some embodiments, the top surface of the barrier structure156or the top surface of the insulating film158is coplanar with the first top surface154aof the ring body152. Therefore the first vertical distance Dv1is equal to 0. In such embodiments, the first vertical distance Dv1and the second vertical distance Dv2are different from each other. As shown inFIG.5, the second vertical distance Dv2is greater than the first vertical distance Dv1.

Referring toFIGS.6to10, in some embodiments, the process kit140can include a deposition ring151. As shown inFIGS.6to10, the deposition ring151includes a ring body152having a first top surface154aand a second top surface154b, and a barrier structure156a,156bdisposed between the first top surface154aand the second top surface154b. In some embodiments, the barrier structure includes at least a first portion156aand a second portion156b. In other embodiments, the barrier structure156a,156bcan include more than two portions. In some embodiments, the first top surface154ais an annular surface, the first portion156aof the barrier structure is an annular portion surrounding the first top surface154a, the second portion156bof the barrier structure is an annular portion surrounding the first portion156a, and the second top surface154bis an annular surface surrounding the first top surface154aand the barrier structure156a,156b. In some embodiments, the ring body152and the barrier structure156a,156bare monolithic. In some embodiments, the ring body152and the barrier structure156a,156binclude a same material, such as a conductive material. For example but not limited thereto, the ring body152and the barrier structure156a,156bmay include stainless steel, as shown inFIGS.6to10, but the disclosure is not limited thereto. In some embodiments, an insulating film158is disposed on the first portion156aand the second portion156bof the barrier structure, as shown inFIGS.7to10. In some embodiments, the insulating film158includes AlXOYor AlXNY, but the disclosure is not limited thereto. It should be noted that in some embodiments, the insulating film158is disposed or coated on both of the first portion156aand the second portion156b, as shown inFIGS.7to10. In other embodiments, the insulating film158can be disposed on the first portion156aonly. In still other embodiments, the insulating film158can be disposed on the second portion156b, only.

In some embodiments, the first portion156aand the second portion156bare separated from each other by a first horizontal distance DHa, which is defined by a vertical sidewall of the first portion156athat faces the second portion156band a vertical sidewall of the second portion156bthat faces the first portion156a, as shown inFIG.6. Further, the first top surface154aof the ring body152and the first portion156aof the barrier structure are separated by a second horizontal distance DHb, which is defined between the vertical sidewall of the first portion156athat faces the first top surface154aand a vertical wall of the ring body152that is coupled to the first top surface154aand faces the first portion156a, shown inFIG.6. In some embodiments, when the first portion156aand the second portion156binclude the insulating film158, the first horizontal distance DHais defined between a vertical surface of the insulating film158on the first portion156athat faces the second portion156band a vertical surface of the insulating film158on the second portion156bthat faces the first portion156a, as shown inFIGS.7to10. Further, the second horizontal distance DHb, is defined between the vertical surface of the insulating film158on the first portion156a(and facing the first top surface154a) and the vertical wall of the ring body152that is coupled to the first top surface154a(and faces the first portion156a), as shown inFIGS.7to10. Both of the first horizontal distance DHaand the second horizontal distance DHbare greater than 0. In some embodiments, the first horizontal distance DHaand the second horizontal distance DHbare the same.

As shown inFIG.6, in some embodiments, a first vertical distance DVais defined between a top surface of the first portion156aand a top surface of the second portion156b, a second vertical distance DVbis defined between the first top surface154aof the ring body152and the top surface of the first portion156aof the barrier structure, and a third vertical distance DVcis defined between the first top surface154aof the ring body152and the top surface of the second portion156bof the barrier structure. The third vertical distance DVccan be a sum of the first vertical distance DVaand the second vertical distance DVb. In some embodiments, when the first portion156aand the second portion156bof the barrier structure156include the insulating film158, the top surface is a surface of the insulating film158, as shown inFIGS.7to10. Accordingly, the first vertical distance DVais defined between the top surface of the insulating film158on the first portion156aand the top surface of the insulating film158on the second portion156b, the second vertical distance DVbis defined between the top surface of the insulating film158on the first portion156aand the first top surface154aof the ring body152, and the third vertical distance DVcis defined between the insulating film158on the second portion156bof the barrier structure and the first top surface154aof the ring body152, as shown inFIGS.7to10.

In some embodiments, the first top surface154aand the second top surface154bare not coplanar with each other. For example, the first top surface154ais higher than the second top surface154b, as shown inFIGS.6to8. In some embodiments, the first vertical distance DVaand the second vertical distance DVbare the same, as shown inFIGS.6and7. In other embodiments, the first vertical distance DVaand the second vertical distance DVbare different from each other. For example, the second vertical distance DVbis greater than the first vertical distance DVa, as shown inFIG.8. In still other embodiments, the second vertical distance DVbcan be less than the first vertical distance DVa, though such arrangement is not shown. In some embodiments, both of the first and second vertical distances DVaand DVbare greater than 0, as shown inFIGS.6to8. In addition, a groove159amay be disposed between the first portion156aand the second portion156b, and a groove159bmay be disposed between the first portion156aand the first top surface154a. Shapes of the first portion156aand the second portion156bof the barrier structure or the grooves159aand159bcan be modified. The modified shapes are also included in a scope of the present disclosure.

In some embodiments, the first top surface154aand the second top surface154bare flush with each other, as shown inFIGS.9and10. In some embodiments, the first vertical distance DVaand the second vertical distance DVbare the same, as shown inFIG.9. In other embodiments, the first vertical distance DVais greater than the second vertical distance DVb, as shown inFIG.10. In still other embodiments, the second vertical distance DVbcan be greater than the first vertical distance DVa, though such arrangement is not shown.

Please refer toFIGS.11to13, whereinFIG.11is a flow diagram of a method for forming a layer in accordance with some embodiments of the present disclosure,FIGS.12A and12Bare schematic views of different stages in a method for forming a layer in accordance with some embodiments of the present disclosure, andFIG.13is an enlarged partial view ofFIG.12B. In some embodiments, a method for forming a layer20is provided. The method20can include operations202,204and206.

Referring toFIG.12A, in some embodiments, in operation202, a workpiece such as a wafer120is received in an apparatus for deposition, such as the abovementioned apparatus for PVD100. The wafer120can be positioned in the chamber106through a wafer port (not shown). In some embodiments, the wafer120, being placed on the pedestal110is raised to an operation position with the heater touching the cover ring160of the process kit140as shown inFIG.12B. In some embodiments, a bottom surface of the wafer120may be in contact with the first top surface154aof the ring body152of the deposition ring150, as shown inFIG.13. It should be noted that although the deposition ring150is illustrated inFIGS.12A,12B and13, those skilled in that art would easily realize that the deposition ring151can be used in some embodiments, though not shown.

Referring toFIGS.12B and13, in operation204, the target130is sputtered. As mentioned above, the target130is posed of metal or metal alloys which are predetermined to be deposited onto the wafer120. In some embodiments, a plasma may be introduced to impact the surface of the target130, which may be electrically biased by the power supply132. Atoms, molecules and/or ions may be generated from the target130. In some embodiments, a pressure within the chamber106is adjusted to a desirable pressure. A reactant gas such as argon (Ar) or nitrogen (Ni) is introduced into the chamber106until an optimum condition for igniting plasma is reached and the plasma source104can be turned on to ignite the plasma. Ions, such as Ar or N ions in the plasma, are accelerated and the target130is struck by the ions. Consequently, the target130is sputtered and the sputtered material is deposited onto a top surface of the wafer120to form a layer in operation206. In operations204and206, the barrier structure156may alter electron density distribution during the depositing the sputter material, which will be described inFIGS.14-16.

Still referring toFIG.13, in some embodiments, a horizontal distance DHWdefined by an edge of the wafer120and the barrier structure156, is between approximately 0.01 mm and approximately 10 mm. In some comparative embodiments, when the horizontal distance DHWis less than 0.01 mm, the barrier structure156may be too close to the edge of the wafer120to alter electron density distribution. In some comparative embodiments, when the horizontal distance DHWis greater than 10 mm, the alteration provided by the barrier structure156may be too far from the wafer120to make sufficient difference. In some embodiments, a vertical distance DVW, defined by a top surface of the barrier structure156and a top surface of the wafer120is between approximately 0 mm and approximately 50 mm. In some embodiments, the top surface of the barrier structure156can be higher than the top surface of the wafer120. In other embodiments, the top surface of the barrier structure156can be lower than the top surface of the wafer120. Therefore, the vertical distance DVWbetween the top surface of the barrier structure156and the top surface of the wafer120can be between approximately 0 mm and approximately 50 mm. In some comparative embodiments, when the vertical distance between the top surface of the barrier structure156and the top surface of the wafer120is greater than 50 mm, the barrier structure156may fail to alter electron density distribution. In some comparative embodiments, when the vertical distance between the top surface of the barrier structure156and the top surface of the wafer120is greater than 50 mm, the barrier structure156may obstruct material deposition. In some embodiments, when the insulating film158is coated on the barrier structure156(including the first portion156aand/or the second portion156b), the vertical distance DVWcan be defined by a top surface of the insulating film158and the top surface of the wafer120, and the distance between the top surface of the insulating film158and the top surface of the wafer120can be between approximately-50 mm and approximately 50 mm, but the disclosure is not limited thereto.

FIG.14is a chart illustrating an electron density distribution during a PVD operation in the apparatus100according to aspects of one or more embodiments of the present disclosure. It should be noted that the insulating film158is omitted fromFIG.14for the purpose of clarity. In some comparative embodiments, in which no barrier structure156is adopted, the electron density around the wafer edge may be greater than 0.5×1015m−3. In some embodiments, in which the barrier structure156having the top surface coplanar with the first top surface154aof the ring body152is adopted, the electron density distribution in the plasma is altered. Additionally, the top surface of the barrier structure156is lower than the top surface of the wafer120. For example, the electron density around the wafer edge may be reduced from 0.5×1015m−3to less than 0.3×1015m−3, but the disclosure is not limited thereto. In some embodiments, the electron density around the wafer edge is reduced by more than 20%, but the disclosure is not limited thereto. Significantly, because the electron density is reduced, an incidence rate of arcing is reduced.

FIG.15is a chart illustrating an electron density distribution during a PVD operation in the apparatus100according to aspects of one or more embodiments of the present disclosure. It should be noted that the insulating film158is omitted fromFIG.15for the purpose of clarity. In some comparative embodiments, in which no barrier structure156is adopted, the electron density around the wafer edge may be greater than 0.5×1015m−3. In some embodiments, in which the barrier structure156having the top surface higher than the first top surface154ais adopted, the electron density distribution in the plasma is altered. Additionally, the top surface of the barrier structure156is higher than the top surface of the wafer120. For example, the electron density around the wafer edge may be reduced from 0.5×1015m−3to less than 0.3×1015m−3, but the disclosure is not limited thereto. It can be found that a portion of the plasma with greater electron density (e.g., electron density greater than 0.3×1015m−3) is pushed away from the wafer edge. In some embodiments, the electron density around the wafer edge is reduced by more than 30%, but the disclosure is not limited thereto. Significantly, because the electron density is reduced, an incidence rate of arcing is reduced.

FIG.16is a chart illustrating an electron density distribution during a PVD operation in the apparatus100according to aspects of one or more embodiments of the present disclosure. It should be noted that the insulating film158is omitted fromFIG.16for the purpose of clarity. As mentioned above, in some comparative embodiment in which no barrier structure is adopted, the electron density around the wafer edge may be greater than 0.5×1015m−3. In some embodiments, when the barrier structure including the first portion156aand the second portion156bis adopted, the electron density distribution in the plasma is altered. For example, the electron density around the wafer edge may be reduced from 0.5×1015m−3to less than 0.3×1015m−3, but the disclosure is not limited thereto. It can be found that a portion of the plasma with greater electron density (e.g., electron density greater than 0.3×1015m−3) is pushed away from the wafer edge by the first portion156aand the second portion156b. In some embodiments, the electron density around the wafer edge is reduced by more than 30%, but the disclosure is not limited thereto. Significantly, because the electron density is reduced, an incidence rate of arcing is reduced.

As shown inFIGS.14to16, because the electron density distribution of the plasma is altered by the barrier structure156of the deposition ring150or the barrier structure (i.e., the first portion156aand the second portion156b) of the deposition ring151, the electron density around the wafer edge is reduced and thus the incidence rate of arcing is reduced. Consequently, the arcing issue is mitigated.

Accordingly, there is no need to adjust the PVD operation or parameters in order to avoid the arcing issue. In other words, the operation is simplified. Further, the arcing issue can be mitigated without reducing PVD throughput or increasing energy consumption. In some embodiments, because the deposition rings150and151effectively mitigate the arcing issue, additional cleaning processes for removing the residue over the wafer120can be omitted, and thus the overall throughput can be increased and process cost can be reduced.

The present disclosure provides an apparatus for PVD to mitigate the arcing issue without reducing PVD throughput, increasing process cost, or increasing energy consumption. In some embodiments, a deposition ring including a barrier structure is provided. The barrier structure of the deposition ring is able to alter the electron density distribution and thus electron density of the plasma around the wafer edge is reduced. Accordingly, incidence rate of arcing can be reduced. In other words, the arcing issue is mitigated although there still is residue over the wafer edge.

In some embodiments, a ring is provided. The ring includes a ring body having a first top surface and a second top surface, and a barrier structure disposed between the first top surface and the second top surface. In some embodiments, the barrier structure is separated from the first top surface by a horizontal distance. A first vertical distance is defined between the barrier structure and the first top surface, and a second vertical distance is defined between the barrier structure and the second top surface. In some embodiments, the second vertical distance is equal to or greater than the first vertical distance.

In some embodiments, an apparatus for PVD is provided. The apparatus includes a chamber, a pedestal disposed in the chamber to accommodate a wafer, and a ring. The ring includes a ring body having a first top surface and a second top surface, and a barrier structure disposed between the first top surface and the second top surface.

In some embodiments, a method for forming a layer is provided. The method includes following operations. A workpiece is received in an apparatus for deposition. In some embodiments, the apparatus for deposition includes a chamber, a pedestal disposed in the chamber to accommodate the workpiece, and a ring disposed on the pedestal. The ring includes a ring body having a first top surface and a second top surface and a barrier structure disposed between the first top surface and the second top surface. A vertical distance is defined by a top surface of the barrier structure and a top surface of the workpiece. In some embodiments, the vertical distance is between approximately 0 mm and approximately 50 mm. A target disposed in the apparatus for deposition is sputtered. A sputtered material is deposited onto a top surface of the workpiece to form a layer. In some embodiments, the barrier structure alters an electrical density distribution during the depositing the sputter material.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.