Patent ID: 12237367

Reference numerals:

A-A1: first direction;100: semiconductor substrate;110: active area;120: shallow trench isolation area;101: sacrificial layer;210: first recesses;220: second recesses;300: contact holes; H2: depth;230: adhesive layer;240: metal layer.

DETAILED DESCRIPTION

In order to explain technical solutions of embodiments of the present application more clearly, the accompanying drawings to be used for describing the embodiments of the present application will be introduced simply. Apparently, the accompanying drawings to be described below are merely some embodiments of the present application. A person of ordinary skill in the art may obtain other drawings according to these drawings without paying any creative effort.

FIG.1is a schematic structure diagram of the method for forming a semiconductor structure in this embodiment.FIG.2is a top plan view of the method for forming a semiconductor structure in this embodiment.

A semiconductor substrate100is provided. The surface of the semiconductor substrate has a plurality of active areas110and shallow trench isolation areas120, defined as a plurality of shallow trench isolation areas120arranged in the first direction A-A1and a plurality of active areas110extending in the first direction A-A1.

The semiconductor substrate100may comprise, but is not limited to, a monocrystalline silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, when the semiconductor substrate100is a monocrystalline substrate or a polycrystalline substrate, it may be an intrinsic silicon substrate or a doped silicon substrate, and further, it may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

A sacrificial layer101is deposited on the surface of the semiconductor substrate100. The sacrificial layer101is made of at least one of silicon dioxide, silicon nitride, silicon oxynitride, polycrystalline silicon, monocrystalline silicon, and carbon. In this embodiment, a silicon nitride layer is deposited on the surface of the semiconductor substrate100to cover the active areas110and the shallow trench isolation areas120. The deposition of a silicon nitride layer is to prepare a mask layer for subsequent etching. The mask layer (not shown) comprises: a silicon nitride layer with a thickness of 45 nanometers; a carbon layer with a thickness of 150 nanometers; and a DARC layer with a thickness of 30 nanometers (silicon oxynitride).

The active areas110and the shallow trench isolation areas120are etched in a direction perpendicular to the first direction A-A1to form first recesses210and second recesses220. The surfaces of the first recesses210and the second recesses220are covered with an adhesive layer230and a metal layer240. The adhesive layer230is made of titanium nitride and the metal layer240is made of tungsten.

An adhesive layer230and a metal layer240are sequentially deposited on the surfaces of the first recesses210and the second recesses220by a deposition process. In the thin film deposition process, there are two main deposition methods: chemical vapor deposition, in which gases of one or more substances are activated somehow to have chemical reactions on the surface of the substrate and then deposited into a desired solid thin film. Physical vapor deposition may be used, in which the transfer of substances is realized by a certain physical process, that is, atoms or molecules are transferred to the surface of the silicon substrate and deposited into a thin film. The thin film deposition process further includes pin coating, electroplating and the like. For example, in this embodiment, there may be many specific deposition methods for the adhesive layer230. For example, chemical vapor deposition may be used to deposit an adhesive layer230with a preset thickness distribution in the first recesses210. Further, controlling the flow rate of the introduced airflow, controlling the flow of the introduced airflow, controlling the deposition time, or controlling the deposition temperature may be used separately. By improving the accuracy in controlling the airflow and temperature, all atoms can be deposited neatly to form a single crystalline layer. Finally, an adhesive layer230with a uniform thickness is obtained in the first recesses210and the second recesses220. Further, the metal layer240is filled to cover the first recesses210and the second recesses220.

It may be understood by those skilled in the art that, in the technical field of semiconductors, due to the design layout of the structure, the buried word lines (WL) will go through both the active areas (AA) and the shallow trench isolation areas (STI). The buried word lines in the shallow trench isolation areas will, when they are working, be coupled with the buried word lines in the parallel active areas. As a result, there is an extra strong electric field between the gate in the active area and the semiconductor substrate, which is affected by the gate induced drain leakage (GIDL). Therefore, there is a need for a buried gate preparation method that improves the gate induced drain leakage effect.

FIG.3is a schematic structure diagram of the method for forming a semiconductor structure in this embodiment.FIG.4is a top plan view of the method for forming a semiconductor structure in this embodiment.

The metal layer240deposited on the surface of the recesses is removed by a chemical mechanical polishing process to form a recess from which the adhesive layer230is exposed.

In this embodiment, due to the deposition in the active areas110and the shallow trench isolation areas120in the above steps, the outermost layer is the metal layer240. It is required to remove the excess metal layer240by a chemical mechanical polishing process to expose the adhesive layer230, in order to facilitate the subsequent etching process.

FIG.5is a schematic structure diagram of the method for forming a semiconductor structure in this embodiment.FIG.6is a top plan view of the method for forming a semiconductor structure in this embodiment.

The adhesive layer230exposed from the second recesses220in the shallow trench isolation area120is etched in the direction perpendicular to the first direction A-A1, the depth of etching the adhesive layer230is defined as H0, and the range of the H0is from 10 nanometers to 20 nanometers. Meanwhile, the H0is less than the H2. The H2is the depth of the contact holes300in the second recesses220finally formed in this embodiment, and the range of the H2is from 71nanometers to 80 nanometers.

By an etching process, the adhesive layer230exposed from the second recesses220in the shallow trench isolation area120is etched downward by using the depth of H0as the standard. In this embodiment, the adhesive layer230may be etched by dry etching. The semiconductor structure is conveyed to the reaction chamber, and the pressure in the reaction chamber is decreased by a vacuum system. When the reaction chamber is in vacuum, a reaction gas is introduced into the reaction chamber. For the etching of a titanium nitride material, a mixture of nitrogen fluoride and oxygen is usually used as the reaction gas. Alternatively, other fluorine-containing gases may be used as the etching gas, for example carbon tetrafluoride, sulfur hexafluoride, nitrogen trifluoride, silicon tetrachloride, chlorine, and the like. The power supply creates a radio frequency electric field through the electrodes in the reaction chamber. The energy field excites the mixed gas into the plasma state. In the excited state, the etching is performed with the reactive fluorine and the reactive fluorine is converted into volatile components to be discharged by the vacuum system. In this embodiment, the main component of the reaction gas used is nitrogen fluoride. By controlling the ratio of nitrogen ions to fluoride ions, at the same time, controlling the reaction time, temperature and other factors of the process, the etching rate is adjusted.

In this embodiment, in the first step, only the adhesive layer230exposed from the second recesses220in the shallow trench isolation area120is selectively etched, in order to distinguish the depth of the adhesive layer230exposed from the first recesses210in the active area110during the secondary etching in the subsequent process.

FIG.7is a schematic structure diagram of the method for forming a semiconductor structure in this embodiment.FIG.8is a top plan view of the method for forming a semiconductor structure in this embodiment.

The active area110and the shallow trench isolation area120are continuously etched in the direction perpendicular to the first direction, to expose the adhesive layer and the metal layer to form contact holes. The depth of etching the adhesive layer and the metal layer is defined as H1, and the H1is less than the H2. Further, the range of the H0is from 10 nanometers to 20 nanometers; the range of the H1is from 60 nanometers to 70 nanometers; the range of the H2is from 71 nanometers to 80 nanometers; and the H2=the H1+the H0.

In this embodiment, the adhesive layer230and the metal layer240are continuously etched downward to a certain depth by plasma dry etching. Dry etching is a process that uses plasma to etch the thin film. When the gas exists in the form of plasma, it has two characteristics: on one hand, the chemical activities of the gas in the form of plasma are much stronger than in the normal state. Depending upon different materials to be etched, the selection of an appropriate gas may facilitate the reaction with the materials to achieve the purpose of etching and removal; and on the other hand, the plasma may be guided and accelerated by the electric field to have certain energy, and when the surface of the material to be etched is bombarded by the plasma, the plasma will knock out atoms of the material to be etched, thus to realize physical energy transfer to achieve the purpose of etching. Therefore, dry etching is the result of balancing physical and chemical processes on the surface of the wafer. In this embodiment, the use of plasma dry etching realizes more precise processing, and the resistance of the buried word lines will not increase due to the too large etching depth. Meanwhile, the masking and etching process used in the technical solution are less technically difficult and easier to obtain the desired design shape.

Further, the range of the H0is from 10 nanometers to 20 nanometers; the range of the H1is from 60 nanometers to 70 nanometers; the range of the H2is from 71 nanometers to 80 nanometers. For example, the H2may be equal to the sum of the H1and the H0. In this way, the height of the adhesive layer230in the shallow trench isolation area220is much lower than the height of the adhesive layer230in the active area210.

Compared with some semiconductor manufacturing technologies, in the present application, by pre-etching, the adhesive layer of the buried word lines is formed in the shallow trench isolation area to a certain depth, which can improve the coupling path of the buried word lines in the adjacent active areas to the shallow trench isolation areas. It may be found from the arrow inFIG.7that, substituted solid arrows for dash arrows the path becomes longer, so the gate-side effective distance between the buried word lines adjacent to the active areas becomes larger. Therefore, the additional electric fields between the adjacent buried word lines in the shallow trench isolation areas and the adjacent buried word lines in the active areas are weakened. Thus, the gate induced drain leakage effect is improved. Meanwhile, in the present application, compared with the technical solution in which a gap is introduced between the gate and the drain and high-resistance substance is filled between the gate and the drain, the masking and etching process used in this technical solution are less technically difficult and easier for implementation.

Further, the metal layer240is higher than the adhesive layer230. Therefore, in the present application, the resistance of the buried word lines is still maintained low. Therefore, the present application can improve the gate induced drain leakage effect and further improve the refresh performance.

An embodiment of the present application further provides a semiconductor structure.

FIG.7is a schematic cross-sectional view of a semiconductor structure in an embodiment of the present application.

The semiconductor structure comprises: a semiconductor substrate100, active areas110, shallow trench isolation areas120, first recesses210, second recesses220, an adhesive layer230, a metal layer240, contact holes300, and a sacrificial layer101.

The surface of the semiconductor substrate has a plurality of active areas110and shallow trench isolation areas120, defined as a plurality of shallow trench isolation areas120arranged in the first direction A-A1and a plurality of active areas110extending in the first direction A-A1.

The semiconductor substrate100may comprise, but is not limited to, a monocrystalline silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, when the semiconductor substrate100is a monocrystalline substrate or a polycrystalline substrate, it may be an intrinsic silicon substrate or a doped silicon substrate, and further, it may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

Further, the sacrificial layer101covers the surface of the semiconductor substrate100. The sacrificial layer101is made of at least one of silicon dioxide, silicon nitride, silicon oxynitride, polycrystalline silicon, monocrystalline silicon, and carbon. In this embodiment, a silicon nitride layer is deposited on the surface of the semiconductor substrate100to cover the active areas110and the shallow trench isolation areas120. The deposition of a silicon nitride layer is to prepare a mask layer for subsequent etching.

The active areas110and the shallow trench isolation areas120are etched in a direction perpendicular to the first direction A-A1to form first recesses210and second recesses220. The surfaces of the first recesses210and the second recesses220are covered with an adhesive layer230and a metal layer240. The adhesive layer230is made of titanium nitride and the metal layer240is made of tungsten.

The contact holes300are formed based on the method for forming a semiconductor structure. Further, the depth of the adhesive layer230in the contact holes300in the second recesses220are defined as H2; wherein the H2is formed by secondary etching and the range of the H2is from 71 nanometers to 80nanometers.

Compared with some semiconductor manufacturing technologies, in the present application, by pre-etching, the adhesive layer of the buried word lines is formed in the shallow trench isolation area to a certain depth, which can improve the coupling path of the buried word lines in the adjacent active areas to the shallow trench isolation areas. It may be found from the arrow inFIG.7that, the path becomes longer, so the gate-side effective distance between the buried word lines adjacent to the active areas becomes larger. Therefore, the additional electric fields between the adjacent buried word lines in the shallow trench isolation areas and the adjacent buried word lines in the active areas are weakened. Thus, the gate induced drain leakage effect is improved. Meanwhile, in the present application, compared with the technical solution in which a gap is introduced between the gate and the drain and high-resistance substance is filled between the gate and the drain, the masking and etching process used in this technical solution is less technically difficult and is easier for implementation.

The foregoing descriptions are merely preferred embodiments of the present application. It should be noted that, for a person of ordinary skill in the art, various improvements and modifications may be made without departing from the principle of the present application, and these improvements and modifications shall be deemed as falling into the protection scope of the present application.