Patent ID: 12230330

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments will be clearly described in detail hereinafter so as to be easily implemented by one of ordinary skill in the art of the inventive concept.

FIG.1is a block diagram of a memory system according to an embodiment. Referring toFIG.1, a memory system10may include a memory controller100and a memory device200. The memory system10may be included in or mounted on electronic devices such as a personal computer (PC), a server, a data center, a smartphone, a tablet PC, an autonomous vehicle, a handheld game console, and a wearable device. For example, the memory system10may include a storage device such as a solid state drive (SSD).

The memory controller100may generally control operations of the memory device200. In detail, the memory controller100may provide a control signal CTRL, a command CMD, and/or an address ADDR to the memory device200to control the memory device200. In an example embodiment, the memory controller100may control the memory device200to store data DATA or output the data DATA in response to a request from an external host.

The memory device200may operate under the control of the memory controller100. In an example embodiment, the memory device200may output the data DATA stored therein or store the data DATA provided from the memory controller100, under the control of the memory controller100.

The memory device200may include a memory cell array210, a page buffer circuit220, and a page buffer controller230. The memory cell array210may include a plurality of memory cells connected to word lines and bit lines. A row address in the address ADDR may indicate at least one word line, and a column address in the address ADDR may indicate at least one bit line.

For example, the memory cells may include flash memory cells. However, embodiments are not limited thereto, and the memory cells may include a resistive random access memory (RRAM) cell, a ferroelectric RAM (FRAM) cell, a phase-change RAM (PRAM) cell, a thyristor RAM (TRAM) cell, a magnetic RAM (MRAM) cell, and a dynamic RAM (DRAM) cell. Hereinafter, descriptions will be focused on embodiments in which the memory cells include NAND flash memory cells.

The page buffer circuit220may include a plurality of page buffers. Each of the page buffers may be connected to memory cells of the memory cell array through a corresponding bit line. Each of the page buffers may operate as a write driver or a sense amplifier. For example, in a program operation, a page buffer may apply a voltage, which corresponds to the data DATA to be programmed, to a bit line such that the data DATA may be stored in a memory cell. In a program verify operation or a read operation, a page buffer may detect the data DATA that has been programmed by sensing a current or a voltage through a bit line.

The page buffer controller230may control operations of the page buffer circuit220. The page buffer controller230may control a page buffer using various control signals. For example, the page buffer circuit220may detect the data DATA stored in memory cells based on the control signals of the page buffer controller230.

In an example embodiment, the page buffer controller230may control page buffers based on different control timings. For example, the page buffer controller230may control page buffers such that a precharge timing of a first sensing node of a first page buffer is different from a precharge timing of a second sensing node of a second page buffer. The page buffer controller230may control the page buffers such that a develop timing of the first sensing node is different from a develop timing of the second sensing node. When adjacent page buffers are controlled based on different control timings in a read operation or a program verify operation, the influence of the voltage change of a sensing node of an adjacent page buffer may be reduced. Accordingly, the reliability of data detected through a page buffer may be increased.

FIG.2is a block diagram of an example of a memory device inFIG.1. Referring toFIG.2, the memory device200may include the memory cell array210, the page buffer circuit220, a data input/output (I/O) circuit240, a control logic circuit250, a voltage generator260, and a row decoder270. In this specification, the page buffer circuit220, the data I/O circuit240, the control logic circuit250, the voltage generator260, and the row decoder270may be referred to as peripheral circuits PECT.

The memory cell array210may include a plurality of memory blocks BLK1through BLKz (where “z” is a positive integer). Each of the memory blocks BLK1through BLKz may include a plurality of memory cells. The memory cell array210may be connected to the page buffer circuit220through bit lines BLs and connected to the row decoder270through word lines WLs, string selection lines SSLs, and ground selection lines GSLs.

In an example embodiment, the memory cell array210may include a three-dimensional (3D) memory cell array, which may include a plurality of NAND strings. Each of the NAND strings may include memory cells respectively connected to word lines vertically stacked on a substrate. The disclosures of U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application No. 2011/0233648 are incorporated herein by reference in their entirety. Any incorporation by reference of documents above is limited such that no subject matter is incorporated that is contrary to the explicit disclosure herein. In an example embodiment, the memory cell array210may include a two-dimensional (2D) memory cell array, which may include a plurality of NAND strings in row and column directions.

The page buffer circuit220may include a plurality of page buffers, e.g., first through n-th page buffers PB1through PBn, which may be connected to memory cells through the bit lines BLs, respectively. The page buffer circuit220may select at least one of the bit lines BLs under the control of the control logic circuit250. For example, during a program operation, the page buffer circuit220may apply a program bit line voltage, which corresponds to the data DATA to be programmed, to a selected bit line. In a read operation, the page buffer circuit220may detect the data DATA stored in a memory cell by sensing a current or a voltage of a selected bit line. The page buffer circuit220may be configured to temporarily store the data DATA to be programmed or the data DATA that has been read from a memory cell.

The data I/O circuit240may provide the data DATA from the memory controller100to the page buffer circuit220through data lines DLs or provide the data DATA from the page buffer circuit220to the memory controller100through the data lines DLs.

The control logic circuit250may generally control operations of the memory device200. For example, the control logic circuit250may control each element of the memory device200based on the command CMD, the address ADDR, and/or the control signal CTRL such that the memory device200performs various operations (e.g., a program operation, a read operation, and erase operation).

The control logic circuit250may include the page buffer controller230. The page buffer controller230may generate control signals for controlling each of the first through n-th page buffers PB1through PBn. In an example embodiment, the page buffer controller230may generate control signals such that adjacent page buffers are controlled based on different control timings. For example, respective sensing nodes of page buffers may have different precharge timings or different develop timings based on the control signals. Control signals generated based on different control timings will be described in detail with reference toFIGS.8A through14B.

The voltage generator260may generate various voltages for performing program, read, and erase operations based on a control signal from the control logic circuit250. For example, the voltage generator260may generate a program voltage, a read voltage, and a program verify voltage as word line voltages VWL.

The row decoder270may select one of the word lines WLs and one of the string selection lines SSLs in response to a control signal (e.g., a row address). For example, the row decoder270may apply a program voltage and a program verify voltage to a selected word line during a program operation and may apply a read voltage to a selected word line during a read operation.

FIG.3is a circuit diagram of a memory block according to an embodiment. Referring toFIG.3, a memory block BLK may correspond to one of the memory blocks BLK1through BLKz inFIG.2. The memory block BLK may include NAND strings NS11through NS33, of which each (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MCs, and a ground selection transistor GST, which are connected in series to one another. The transistors, e.g., the string selection transistor SST and the ground selection transistor GST, and the memory cells MCs included in each NAND string may form a stack structure on a substrate in a third direction D3(i.e., a vertical direction).

First through eighth word lines WL1through WL8may extend in a first direction D1perpendicular to the third direction D3, and first through third bit lines BL1through BL3may extend in a second direction D2perpendicular to the first direction D1and the third direction D3. The NAND strings NS11, NS21, and NS31may be between the first bit line BL1and a common source line CSL; the NAND strings NS12, NS22, and NS32may be between the second bit line BL2and the common source line CSL; and the NAND strings NS13, NS23, and NS33may be between the third bit line BL3and the common source line CSL. The string selection transistor SST may be connected to a corresponding one of string selection lines SSL1through SSL3. Each of the memory cells MCs may be connected to a corresponding one of the first through eighth word lines WL through WL8. The ground selection transistor GST may be connected to a corresponding one of ground selection lines GSL1through GSL3. The string selection transistor SST may be connected to a corresponding one of the first through third bit lines BL1through BL3, and the ground selection transistor GST may be connected to the common source line CSL. Here, the numbers of NAND strings, word lines, bit lines, ground selection lines, and string selection lines may vary with embodiments.

FIG.4is a block diagram of an example of the memory device inFIG.1. Referring toFIG.4, a memory device300may include a memory cell array310, a page buffer circuit320including a first page buffer321and a second page buffer322, and a page buffer controller330. The memory cell array310, the page buffer circuit320, and the page buffer controller330may respectively correspond to the memory cell array210, the page buffer circuit220, and the page buffer controller230inFIG.1.

The memory cell array310may include a plurality of memory cells including a first memory cell MC1and a second memory cell MC2. The first memory cell MC1and the second memory cell MC2may be connected to a selected (e.g., “a first”) word line SWL among a plurality of word lines. The memory cell array310may be in a memory cell area MA.

The first page buffer321may be connected to the first memory cell MC1through the first bit line BL1. For example, an end of the first bit line BL1may be connected to a NAND string including the first memory cell MC1, and the other end of the first bit line BL1may be connected to a transistor of the first page buffer321. The second page buffer322may be connected to the second memory cell MC2through the second bit line BL2. For example, an end of the second bit line BL2may be connected to a NAND string including the second memory cell MC2, and the other end of the second bit line BL2may be connected to a transistor of the second page buffer322.

The first page buffer321may detect data of the first memory cell MC1through the first bit line BL1. For example, the first page buffer321may perform a precharge operation. In this case, a first sensing node SO1may be precharged. The first page buffer321may perform a develop operation after performing the precharge operation. In this case, a voltage of the first sensing node SO1that has been precharged may be changed based on data stored in the first memory cell MC1. For example, during the develop operation, a voltage level of the first sensing node SO1may maintain, decrease, or increase based on a threshold voltage of the first memory cell MC1. Accordingly, the first page buffer321may detect data stored in the first memory cell MC1.

The second page buffer322may detect data of the second memory cell MC2through the second bit line BL2. For example, the second page buffer322may perform a precharge operation. In this case, a second sensing node SO2may be precharged. The second page buffer322may perform a develop operation after performing the precharge operation. In this case, a voltage of the second sensing node SO2that has been precharged may be changed based on data stored in the second memory cell MC2. For example, during the develop operation, a voltage level of the second sensing node SO2may maintain, decrease, or increase based on a threshold voltage of the second memory cell MC2. Accordingly, the second page buffer322may detect data stored in the second memory cell MC2.

The first page buffer321and the second page buffer322may be arranged in a line in a direction (i.e., the second direction D2), in which the first and second bit lines BL1and BL2extend. For example, each of the first page buffer321and the second page buffer322may include a plurality of transistors, which may be arranged in a line in the second direction D2. For example, the second page buffer322may be below the first page buffer321in the second direction D2. Accordingly, the first page buffer321may be more adjacent to the memory cell area MA than the second page buffer322. In other words, a distance from the first page buffer321to the memory cell area MA may be less than a distance from the second page buffer322to the memory cell area MA.

When the first page buffer321and the second page buffer322are arranged as shown inFIG.4, the second bit line BL2may be adjacent to the first sensing node SO1of the first page buffer321. In this case, coupling may occur due to capacitance f between the first sensing node SO1and the second bit line BL2. In an example embodiment, the voltage of the second bit line BL2may be changed by coupling resulting from the voltage change of the first sensing node SO1. For example, when the voltage of the first sensing node SO1is changed according to the develop operation of the first page buffer321, the voltage of the second bit line BL2may also be changed. The voltage of the second sensing node SO2may be changed according to the voltage change of the second bit line BL2. Because a value of data may be determined based on the voltage of the second sensing node SO2, the reliability of data detected based on the voltage of the second sensing node SO2may be degraded.

The page buffer controller330may control the first page buffer321based on first control signals CS1. For example, the page buffer controller330may provide the first control signals CS1to the first page buffer321such that the first page buffer321detects data stored in the first memory cell MC1. The page buffer controller330may control the second page buffer322based on second control signals CS2. For example, the page buffer controller330may provide the second control signals CS2to the second page buffer322such that the second page buffer322detects data stored in the second memory cell MC2.

In an example embodiment, the page buffer controller330may control the first page buffer321and the second page buffer322based on different control timings. For example, the page buffer controller330may generate the first control signals CS1and the second control signals CS2such that precharge timings and develop timings of the first and second sensing nodes SO1and SO2are different from one another. The page buffer controller330may adjust the control timings of the first page buffer321and the second page buffer322to reduce the degradation of data reliability caused by coupling between the first sensing node SO1and the second bit line BL2. Accordingly, even when the voltage of the second bit line BL2is changed by coupling between the first sensing node SO1and the second bit line BL2, the reliability of data detected from the second page buffer322may be maintained.

Although it is illustrated inFIG.4that two page buffers, i.e., the first and second page buffers321and322, are arranged in a line, embodiments are not limited thereto. For example, at least three page buffers may be arranged in a line in the second direction D2, and the page buffer controller330may control the page buffers based on different control timings. Hereinafter, for convenience of description, embodiments will be described based on two page buffers.

FIG.5illustrates an example structure of the memory device ofFIG.1. Referring toFIG.5, a memory device400may include a first semiconductor layer L1and a second semiconductor layer L2. The first semiconductor layer L1may be stacked on the second semiconductor layer L2in the vertical direction (i.e., the third direction D3). In detail, the second semiconductor layer L2may be below the first semiconductor layer L1in the third direction D3.

In an example embodiment, the memory cell array210inFIG.2may be formed in the first semiconductor layer L1, and the peripheral circuits PECT inFIG.2may be formed in the second semiconductor layer L2. Accordingly, the memory device400may have a cell over periphery (COP) structure, in which the memory cell array210is above the peripheral circuits PECT. According to the COP structure, an area in a horizontal direction (i.e., in the first and second directions D1and D2) may be effectively reduced, and the integration density of the memory device400may be increased.

In an example embodiment, the second semiconductor layer L2may include a substrate. The peripheral circuits PECT may be formed in the second semiconductor layer L2by forming transistors (e.g., transistors TR inFIG.6) and metal patterns (e.g., first through third lower conductive lines PM1, PM2, and PM3inFIG.6) for the wiring of the transistors on the substrate. After the peripheral circuits PECT are formed in the second semiconductor layer L2, the first semiconductor layer L1including the memory cell array210may be formed. Metal patterns, which electrically connect word lines WL and bit lines BL of the memory cell array210to the peripheral circuits PECT in the second semiconductor layer L2, may be formed. For example, the word lines WL may extend in the first direction D1, and the bit lines BL may extend in the second direction D2.

The memory device400may have the COP structure as described above, but embodiments are not limited thereto. For example, the memory device400may have a chip-to-chip (C2C) structure. In this case, the first semiconductor layer L1may correspond to an upper chip, and the second semiconductor layer L2may correspond to a lower chip. In the C2C structure, the first semiconductor layer L1may include the memory cell array210inFIG.2on a first wafer, and the second semiconductor layer L2may include the peripheral circuits PECT inFIG.2on a second wafer. The first semiconductor layer L1may be connected to the second semiconductor layer L2using a bonding method. For example, a bonding metal (e.g., an upper bonding metal572cinFIG.15) formed in a top metal layer of the first semiconductor layer L1may be electrically connected to a bonding metal (e.g., a lower bonding metal672cinFIG.15) formed in a top metal layer of the second semiconductor layer L2. For example, when a bonding metal includes copper (Cu), the bonding method may include a Cu—Cu bonding method. For example, the first semiconductor layer L1and the second semiconductor layer L2may be stacked in a wafer level. For example, the first semiconductor layer L1and the second semiconductor layer L2may be stacked in a chip level.

FIG.6is an example cross-sectional view of the memory device ofFIG.5. In detail,FIG.6shows a cross-sectional view of the memory device400having a COP structure. Referring toFIG.6, the second semiconductor layer L2may include a lower substrate L_SUB and circuits CT formed in the lower substrate L_SUB. The circuits CT may include at least one transistor TR. The circuits CT may include the page buffer circuit220and the page buffer controller230, which have been described above.

The second semiconductor layer L2may further include lower contacts LMC1, LMC2, and LMC3, which are electrically connected to the circuits CT, and the first through third lower conductive lines PM1, PM2, and PM3, which are electrically connected to the lower contacts LMC1, LMC2, and LMC3. The circuits CT, the lower contacts LMC1, LMC2, and LMC3, and the first through third lower conductive lines PM1, PM2, and PM3may be covered with a lower insulating layer L_IL.

The first semiconductor layer L1may include an upper substrate U_SUB and a plurality of channel structures CS on the upper substrate U_SUB. The channel structures CS may extend through gate conductive layers GS in the vertical direction (i.e., the third direction D3). The channel structures CS may be separated from one another at a certain distance in the first and second directions D1and D2. Each of the channel structures CS may include a gate dielectric film GD, a channel region CR, a buried insulating film BI, and a drain region DR. The gate dielectric film GD may include a tunneling dielectric film, a charge storage film, and a blocking dielectric film, which are sequentially formed on the channel region CR. The channel region CR may include doped polysilicon or undoped polysilicon. The channel region CR may have a cylindrical shape. The inner space of the channel region CR may be filled with the buried insulating film BI. The buried insulating film BI may include an insulating material. In some embodiments, the buried insulating film BI may be omitted. In this case, the channel region CR may have a pillar shape without an inner space. The drain region DR may include a doped polysilicon film. The drain region DR may be electrically connected to a bit line BL through a first upper contact UMC1. A plurality of drain regions DR of the channel structures CS may be insulated from each other by a first insulating film IL1.

The first semiconductor layer L1may further include first upper contacts UMC1electrically connected to the channel structures CS, a second upper contact UMC2electrically connected to a through electrode or through-hole-via THV, and the bit line BL. The channel structures CS and the bit line BL may be covered with an upper insulating layer U_IL.

The through electrode THV may extend through the gate conductive layers GS in the vertical direction (i.e., the third direction D3). The through electrode THV may pass through the upper substrate U_SUB through a through hole HL. The through electrode THV may extend to a portion of the second semiconductor layer L2in the vertical direction (i.e., the third direction D3). The through electrode THV may be surrounded by the first insulating film IL1and an insulating structure ILS and surrounded by a buried insulating film H_IL in the through hole HL. The through electrode THV may include an end connected to the bit line BL through the second upper contact UMC2and an opposite end connected to the third lower conductive line PM3. Accordingly, the bit line BL of the first semiconductor layer L1may be electrically connected to the circuits CT of the second semiconductor layer L2through the through electrode THV. For example, each page buffer of the page buffer circuit220in the second semiconductor layer L2may be connected to the bit line BL through the through electrode THV.

The channel structures CS may be in a block region BLK_R, and the through electrode THV may be in a through electrode region THV_R. The block region BLK_R may be separated from the through electrode region THV_R by a plurality of word line cut regions WLC, which extend on the upper substrate U_SUB in the first and second directions D1and D2. The word line cut regions WLC may be filled with an insulating film W_IL.

The gate conductive layers GS may include a plurality of gate lines GL extending in the second direction D2to be parallel with each other. For example, the gate lines GL may form a ground selection line, word lines, and a string selection line. For example, the ground selection line, the word lines, and the string selection line may be sequentially formed on the upper substrate U_SUB, as described above with reference toFIG.3. A second insulating film IL2may be formed between gate lines GL. For example, the ground selection line and a portion of a channel structure CS adjacent to the ground selection line may form the ground selection transistor GST inFIG.3. The word lines and a portion of the channel structure CS adjacent to the words lines may form the memory cells MCs inFIG.3. The string selection line and a portion of the channel structure CS adjacent to the string selection line may form the string selection transistor SST inFIG.3.

In an example embodiment, the channel structures CS in the block region BLK_R may form the memory cell array210described above. In this case, the circuits CT in a region (i.e., a region below the block region BLK_R in the third direction D3) of the second semiconductor layer L2corresponding to the block region BLK_R of the first semiconductor layer L1may form the page buffer circuit220. Page buffers of the page buffer circuit220may be arranged in a line in the second direction D2.

As described above, in the memory device400having the COP structure, the bit line BL may be connected to a page buffer through the through electrode THV, which is formed in the through electrode region THV_R of the first and second semiconductor layers L1and L2.

FIG.7is a diagram of an example of the memory device ofFIG.5. Referring toFIG.7, the memory device400may include a memory cell array410, a page buffer circuit420including a first page buffer421and a second page buffer422, and a page buffer controller430. The memory cell array410may be formed in the first semiconductor layer L1, and the page buffer circuit420and the page buffer controller430may be formed in the second semiconductor layer L2. The memory cell array410, the page buffer circuit420, and the page buffer controller430may respectively correspond to the memory cell array210, the page buffer circuit220, and the page buffer controller230inFIG.1.

The memory cell array410may include a plurality of memory cells including the first memory cell MC1and the second memory cell MC2. The first memory cell MC1and the second memory cell MC2may be connected to the selected word line SWL among a plurality of word lines. The first memory cell MC1and the second memory cell MC2may be respectively connected to the first bit line BL1and the second bit line BL2, which are formed in the first semiconductor layer L1.

The first page buffer421and the second page buffer422may be respectively connected to a first lower bit line LVBL1and a second lower bit line LVBL2, which are formed in the second semiconductor layer L2. The first bit line BL1may be electrically connected to the first lower bit line LVBL1through a first through electrode THV1, and the second bit line BL2may be electrically connected to the second lower bit line LVBL2through a second through electrode THV2. An end of the first through electrode THV1and an end of the second through electrode THV2may be in a through electrode region THV_RH of the first semiconductor layer L1, and the other end of the first through electrode THV1and the other end of the second through electrode THV2may be in a through electrode region THV_RL of the second semiconductor layer L2.

The first page buffer421may detect data, which is stored in the first memory cell MC1, through the first bit line BL1and the first lower bit line LVBL1, which are electrically connected by the first through electrode THV1. For example, the first page buffer421may detect the data of the first memory cell MC1by performing a precharge operation and a develop operation. The second page buffer422may detect data, which is stored in the second memory cell MC2, through the second bit line BL2and the second lower bit line LVBL2, which are electrically connected by the second through electrode THV2. For example, the second page buffer422may detect the data of the second memory cell MC2by performing a precharge operation and a develop operation.

The first page buffer421and the second page buffer422may be arranged in a line in a direction (i.e., the second direction D2), in which the first and second lower bit lines LVBL1and LVBL2extend. For example, as described above with reference toFIG.6, each of the first page buffer421and the second page buffer422may include a plurality of transistors TR, which may be arranged in a line in the second direction D2. Accordingly, the first page buffer421may be more adjacent (i.e., closer in proximity) to the through electrode region THV_RL than the second page buffer422.

When the first page buffer421and the second page buffer422are arranged as shown inFIG.7, the second lower bit line LVBL2may be adjacent to the first sensing node SO1of the first page buffer421. Due to the proximity of the second lower bit line LVBL2to the first sensing node SO1, as described above with reference toFIG.4, the voltage of the second lower bit line LVBL2may be changed by coupling resulting from the voltage change of the first sensing node SO1, and the voltage of the second sensing node SO2may also be changed according to the voltage change of the second lower bit line LVBL2. As a result, the reliability of data detected based on the voltage of the second sensing node SO2may be degraded.

The page buffer controller430may control the first page buffer421based on the first control signals CS1. The page buffer controller430may control the second page buffer422based on the second control signals CS2. The page buffer controller430may control the first page buffer421and the second page buffer422based on different control timings. For example, the page buffer controller430may adjust the control timings of the first page buffer421and the second page buffer422to reduce the degradation of data reliability caused by coupling between the first sensing node SO1and the second lower bit line LVBL2. Accordingly, the reliability of data detected from the second page buffer422may be maintained.

FIGS.8A through8Dillustrate data detection operations according to embodiments. In detail,FIGS.8A through8Dshow examples of controlling the first sensing node SO1and the second sensing node SO2based on different control timings, as described above with reference toFIGS.4through7. In this case, the first sensing node SO1may be included in a page buffer (e.g., the first page buffer321or421) at a first distance from the memory cell area MA or the through electrode region THV_RL, and the second sensing node SO2may be included in a page buffer (e.g., the second page buffer322or422) at a second distance (the second distance being greater than the first distance) from the memory cell area MA or the through electrode region THV_RL. Referring toFIGS.8A through8D, a data detection operation may be performed through a precharge operation, a develop operation, and a sensing operation.

Referring toFIG.8A, a precharge operation of the second sensing node SO2may be started earlier than a precharge operation of the first sensing node SO1. A develop operation of the second sensing node SO2may be started earlier than a develop operation of the first sensing node SO1. The develop operation of the second sensing node SO2may be started during the precharge operation of the first sensing node SO1. The develop operation of the first sensing node SO1may be started after the develop operation of the second sensing node SO2is terminated. In this case, a develop time (hereinafter, referred to as a first develop time DT1) of the first sensing node SO1may not overlap with a develop time (hereinafter, referred to as a second develop time DT2) of the second sensing node SO2. After the end of the develop operation of the first sensing node SO1, a sensing operation of the first sensing node SO1and a sensing operation of the second sensing node SO2may be started. For example, the sensing operations of the first and second sensing nodes SO1and SO2may be started at the same timing, but embodiments are not limited thereto.

Referring toFIG.8B, the precharge operation of the second sensing node SO2may be started earlier than the precharge operation of the first sensing node SO1. The develop operation of the second sensing node SO2may be started earlier than the develop operation of the first sensing node SO1. The develop operation of the second sensing node SO2may be started during the precharge operation of the first sensing node SO1. The develop operation of the first sensing node SO1may be started before the develop operation of the second sensing node SO2is terminated. In this case, the first develop time DT1and the second develop time DT2may partially overlap with each other. After the end of the develop operation of the first sensing node SO1, the sensing operation of the first sensing node SO1and the sensing operation of the second sensing node SO2may be started.

In an example embodiment, when the first develop time DT1and the second develop time DT2partially overlap with each other as shown inFIG.8B, a time of a data detection operation (e.g., a read operation or a program verify operation) may be reduced. Accordingly, a data detection time DST2in the embodiment ofFIG.8Bmay be less than a data detection time DST1in the embodiment ofFIG.8A.

Referring toFIG.8C, the precharge operation of the first sensing node SO1may be started earlier than the precharge operation of the second sensing node SO2. The develop operation of the first sensing node SO1may be started earlier than the develop operation of the second sensing node SO2. The develop operation of the first sensing node SO1may be started during the precharge operation of the second sensing node SO2. The develop operation of the second sensing node SO2may be started after the develop operation of the first sensing node SO1is terminated. In this case, the first develop time DT1and the second develop time DT2may not overlap with each other. After the end of the develop operation of the second sensing node SO2, the sensing operation of the first sensing node SO1and the sensing operation of the second sensing node SO2may be started.

Referring toFIG.8D, the precharge operation of the first sensing node SO1may be started earlier than the precharge operation of the second sensing node SO2. The develop operation of the first sensing node SO1may be started earlier than the develop operation of the second sensing node SO2. The develop operation of the first sensing node SO1may be started during the precharge operation of the second sensing node SO2. The develop operation of the second sensing node SO2may be started before the develop operation of the first sensing node SO1is terminated. In this case, the first develop time DT1and the second develop time DT2may partially overlap with each other. After the end of the develop operation of the second sensing node SO2, the sensing operation of the first sensing node SO1and the sensing operation of the second sensing node SO2may be started.

In an example embodiment, when the first develop time DT1and the second develop time DT2partially overlap with each other as shown inFIG.8D, a time of a data detection operation may be reduced. Accordingly, a data detection time DST4in the embodiment ofFIG.8Dmay be less than a data detection time DST3in the embodiment ofFIG.8C.

As described above, in the data detection operations according to embodiments, adjacent page buffers may be controlled such that precharge and develop timings of sensing nodes are different from one another. When a develop start time of the first sensing node SO1is different from a develop start time of the second sensing node SO2as shown inFIGS.8A through8D, the influence of coupling by the develop operation of the first page buffer PB1may be reduced. For example, when the first develop time DT1does not overlap with the second develop time DT2, the develop operation of the second page buffer PB2may be performed, without the voltage change of second sensing node SO2by coupling. Accordingly, in the develop operation of the second page buffer PB2, the degradation of data reliability by coupling may not occur.

In an example embodiment, when the first develop time DT1partially overlaps with the second develop time DT2, the voltage of the second sensing node SO2may be changed by coupling during the develop operation of the second page buffer PB2. When the second page buffer PB2is controlled to decrease the second develop time DT2, the influence of coupling on the develop operation of the second page buffer PB2may be reduced. For example, in the embodiments ofFIGS.8B and8D, the second page buffer PB2may be controlled such that the second develop time DT2is less than the first develop time DT1. For example, the second page buffer PB2may be controlled such that the second develop time DT2in the embodiments ofFIGS.8B and8Dis less than the second develop time DT2in the embodiments ofFIGS.8A and8C.

FIG.9is a circuit diagram showing page buffers according to an embodiment. Referring toFIG.9, the first page buffer PB1may be connected to a first NAND string SS1through the first bit line BL1, and the second page buffer PB2may be connected to a second NAND string SS2through the second bit line BL2. Although it is illustrated inFIG.9for convenience of description that the first page buffer PB1and the second page buffer PB2are directly connected to the first bit line BL1and the second bit line BL2, respectively, the first page buffer PB1and the second page buffer PB2, which will be described below, may also be applied to the first page buffer421and the second page buffer422, which are respectively connected to bit lines via through electrodes.

The first NAND string SS1may include a ground selection transistor GST1, memory cells including the first memory cell MC1, and a string selection transistor SST1. The second NAND string SS2may include a ground selection transistor GST2, memory cells including the second memory cell MC2, and a string selection transistor SST2. The ground selection transistors GST1and GST2may be connected to a common source line CSL and a ground selection line GSL, and the memory cells may be connected to zeroth to m-th word lines WL0through WLm. For example, the first memory cell MC1of the first NAND string SS1and the second memory cell MC2of the second NAND string SS2may be connected to the first word line WL1corresponding to the selected word line SWL. The string selection transistors SST1and SST2may be connected in common to a string selection line SSL and respectively connected to the first and second bit lines BL1and BL2. Accordingly, the first memory cell MC1may be connected to the first page buffer PB1through the first bit line BL1, and the second memory cell MC2may be connected to the second page buffer PB2through the second bit line BL2. It will be understood that when an element is referred to as being “connected” or “on” another element, it can be directly connected or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” to or “directly on” another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

The first page buffer PB1may include a first transistor TR1, which is driven by a first bit line shut-off signal BLSHF1, and a second transistor TR2, which is driven by a first bit line connection control signal CLBLK1. For example, the first transistor TR1may be turned on according to the first bit line shut-off signal BLSHF1at a high level and turned off according to the first bit line shut-off signal BLSHF1at a low level. For example, the second transistor TR2may be turned on according to the first bit line connection control signal CLBLK1at a high level and turned off according to the first bit line connection control signal CLBLK1at a low level.

The first transistor TR1and the second transistor TR2may be between the first bit line BL1and the first sensing node SO1. Although it is illustrated inFIG.9that the first transistor TR1is directly connected to the first bit line BL1, embodiments are not limited thereto. For example, a separate transistor (e.g., a bit line selection transistor) for selecting a bit line may be further provided between the first bit line BL1and the first transistor TR1.

The first page buffer PB1may further include a third transistor TR3driven by a first precharge control signal PSO1. For example, the third transistor TR3may be turned on according to the first precharge control signal PSO1at a low level and turned off according to the first precharge control signal PSO1at a high level. When the third transistor TR3is turned on, the precharge operation of the first page buffer PB1may be started based on a precharge voltage Vpre. For example, the voltage of the first sensing node SO1may be increased, and the first sensing node SO1may be precharged to a voltage level corresponding to the precharge voltage Vpre. When the third transistor TR3is turned off, the precharge operation of the first page buffer PB1may be terminated.

When the first and second transistors TR1and TR2are in a turned-on state and the third transistor TR3is turned off after the precharge operation is performed, the develop operation of the first page buffer PB1may be started. For example, the develop operation of the first page buffer PB1may be started by electrically connecting the precharged first sensing node SO1to the first bit line BL1. During the develop operation, the voltage of the first sensing node SO1may be changed according to data stored in the first memory cell MC1. For example, when the first memory cell MC1is an on-cell, the voltage of the first sensing node SO1may be decreased to or below a reference voltage. When the first memory cell MC1is an off-cell, the voltage of the first sensing node SO1may be maintained at the reference voltage or higher. The reference voltage may be used to determine whether the first memory cell MC1is an on-cell or an off-cell. In other words, the reference voltage may be used to identify whether a data value stored in the first memory cell MC1is 0 or 1. When the second transistor TR2is turned off, the develop operation of the first page buffer PB1may be terminated.

The first page buffer PB1may further include a fourth transistor TR4, which is driven by a first sensing monitoring signal MON1, and a first sensing latch SL1. The fourth transistor TR4may be between the first sensing node SO1and the first sensing latch SL1. For example, the fourth transistor TR4may be turned on according to the first sensing monitoring signal MON1at a high level and turned off according to the first sensing monitoring signal MON1at a low level. When the fourth transistor TR4is turned on after the develop operation, data sensed from the first memory cell MC1may be stored in the first sensing latch SL1. The sensing operation of the first page buffer PB1may be performed by storing the data of the first memory cell MC1in the first sensing latch SL1. For example, although not shown inFIG.9, the first page buffer PB1may further include data latches and a cache latch as well as the first sensing latch SL1.

The second page buffer PB2may include a fifth transistor TR5, which is driven by a second bit line shut-off signal BLSHF2, and a sixth transistor TR6, which is driven by a second bit line connection control signal CLBLK2. The second page buffer PB2may further include a seventh transistor TR7driven by a second precharge control signal PSO2, an eighth transistor TR8driven by a second sensing monitoring signal MON2, and a second sensing latch SL2. As shown inFIG.9, the configuration of the second page buffer PB2may be the same as that of the first page buffer PB1, and accordingly, the operations of the second page buffer PB2may be substantially the same as those of the first page buffer PB1. Therefore, redundant descriptions thereof are omitted.

As described above, each page buffer may detect data, which is stored in a memory cell, by performing a precharge operation, a develop operation, and a sensing operation based on transistors. The transistors of each page buffer may be driven based on control signals. The page buffer controllers230,330, and430described above may control page buffers using control signals.

Hereinafter, control signals generated to control the first page buffer PB1and the second page buffer PB2will be described in detail with reference toFIGS.10A through14B. In detail, an example of performing a data detection operation using the first and second page buffers PB1and PB2based on the same control timings will be described with reference toFIGS.10A and10B; and examples of performing a data detection operation using the first and second page buffers PB1and PB2based on different control timings will be described with reference toFIGS.11A through14B. For convenience of description, it is assumed that the first memory cell MC1is an on-cell and the second memory cell MC2is an off-cell, but embodiments are not limited thereto. For example, when the first memory cell MC1is an off-cell and the second memory cell MC2is an on-cell or both the first and second memory cells MC1and MC2are on-cells, a data detection operation may be performed using the first and second page buffers PB1and PB2based on different control timings.

FIG.10Ais a timing diagram of control signals for performing a data detection operation based on the same control timings.FIG.10Bis a timing diagram showing the voltage changes of sensing nodes with respect to the control signals ofFIG.10A.

Referring toFIGS.9,10A, and10B, the first and second bit line shut-off signals BLSHF1and BLSHF2may be controlled to be at the high level. The first and second precharge control signals PSO1and PSO2may be controlled to be at the low level from a first time point t11to a third time point t13. Accordingly, the precharge operation of each of the first and second page buffers PB1and PB2may be performed from the first time point t11to the third time point t13. During a precharge time PT, the voltage of each of the first and second sensing nodes SO1and SO2may be increased to a voltage level corresponding to the precharge voltage Vpre.

The first and second bit line connection control signals CLBLK1and CLBLK2may be controlled to be at the high level from a second time point t12to a fourth time point t14. The first and second precharge control signals PSO1and PSO2may be controlled to be at the high level from the third time point t13to the fourth time point t14. While the first and second precharge control signals PSO1and PSO2and the first and second bit line connection control signals CLBLK1and CLBLK2are being controlled to be at the high level (i.e., during a period from the third time point t13to the fourth time point t14), the develop operation of each of the first and second page buffers PB1and PB2may be performed. For example, the develop operation of each of the first and second page buffers PB1and PB2by electrically connecting the first and second sensing nodes SO1and SO2to the first and second bit lines BL1and BL2, respectively.

During a develop time DT, the voltage of the first sensing node SO1may be developed according to data stored in the first memory cell MC1, and the voltage of the second sensing node SO2may be developed according to data stored in the second memory cell MC2. For example, the voltage of the first sensing node SO1may decrease below a reference voltage Vref. In this case, the second bit line BL2adjacent to the first sensing node SO1may undergo down-coupling according to the voltage change of the first sensing node SO1. When the voltage of the second bit line BL2is changed by down-coupling, the voltage of the second sensing node SO2may be decreased more than when there is no down-coupling influence. For example, when there is no down-coupling influence, the voltage of the second sensing node SO2may be developed to a first voltage V1that is higher than the reference voltage Vref. When there is a down-coupling influence, the voltage of the second sensing node SO2may be developed to a second voltage V2that is lower than the reference voltage Vref. In other words, when the develop time DT of the first page buffer PB1is the same as the develop time DT of the second page buffer PB2, the voltage of the second sensing node SO2may be further decreased due to down-coupling during the develop time DT.

The first and second sensing monitoring signals MON1and MON2may be controlled to be at the high level from the fourth time point t14to a fifth time point t15. Accordingly, data sensed by the first sensing node SO1and data sensed by the second sensing node SO2may be respectively stored in the first and second sensing latches SL1and SL2. A data value stored in each of the first and second sensing latches SL1and SL2may correspond to a voltage developed during the develop time DT. Because the voltage of the second sensing node SO2may be developed to the second voltage V2that is lower than the reference voltage Vref during the develop time DT due to the down-coupling influence, a data value stored in the second sensing latch SL2during a sensing time ST may be changed. In other words, data having a value different from a data value stored in the second memory cell MC2may be stored in the second sensing latch SL2.

As described above, when the first and second page buffers PB1and PB2are controlled based on the same control timings, a data value detected by the second page buffer PB2may be changed because of the down-coupling influence. Accordingly, the reliability of data detected through page buffers may be degraded.

FIG.11Ais a timing diagram of control signals for performing a data detection operation based on different control timings.FIG.11Bis a timing diagram showing the voltage changes of sensing nodes with respect to the control signals ofFIG.11A. In detail, the embodiment ofFIGS.11A and11Bmay correspond to the embodiment ofFIG.8A.

Referring toFIGS.9,11A, and11B, the first and second bit line shut-off signals BLSHF1and BLSHF2may be controlled to be at the high level. The second precharge control signal PSO2may be controlled to be at the low level from a first time point t21to a third time point t23. Accordingly, the precharge operation of the second page buffer PB2may be performed from the first time point t21to the third time point t23. During a precharge time (hereinafter, referred to as a second precharge time PT2) of the second page buffer PB2, the voltage of the second sensing node SO2may be increased to a voltage level corresponding to the precharge voltage Vpre.

The first precharge control signal PSO1may be controlled to be at the low level from a second time point t22to a fifth time point t25. Accordingly, the precharge operation of the first page buffer PB1may be performed from the second time point t22to the fifth time point t25. During a precharge time (hereinafter, referred to as a first precharge time PT1) of the first page buffer PB1, the voltage of the first sensing node SO1may be increased to a voltage level corresponding to the precharge voltage Vpre.

While the second precharge control signal PSO2and the second bit line connection control signal CLBLK2are being controlled to be at the high level (i.e., during a time period from the third time point t23to a fourth time point t24), the develop operation of the second page buffer PB2may be performed (i.e., second develop time DT2). During the second develop time DT2of the second page buffer PB2, the voltage of the second sensing node SO2may be developed according to data stored in the second memory cell MC2. When the second memory cell MC2is an off-cell, the voltage of the second sensing node SO2may be developed to a voltage Vs higher than the reference voltage Vref.

While the first precharge control signal PSO1and the first bit line connection control signal CLBLK1are being controlled to be at the high level (i.e., during a time period from the fifth time point t25to a sixth time point t26), the develop operation of the first page buffer PB1may be performed (i.e., first develop time DT1). During the first develop time DT1of the first page buffer PB1, the voltage of the first sensing node SO1may be developed according to data stored in the first memory cell MC1. When the first memory cell MC1is an on-cell, the voltage of the first sensing node SO1may decrease below the reference voltage Vref. In this case, the second bit line BL2may be down-coupled according to the voltage change of the first sensing node SO1. Because the second bit line connection control signal CLBLK2is controlled to be at the low level during the first develop time DT1, the voltage of the second sensing node SO2may be maintained regardless of the voltage change of the second bit line BL2.

The first and second sensing monitoring signals MON1and MON2may be controlled to be at the high level from the sixth time point t26to a seventh time point t27. Accordingly, data sensed by the first sensing node SO1and data sensed by the second sensing node SO2may be respectively stored in the first and second sensing latches SL1and SL2. Because the voltage of the second sensing node SO2is not changed even if down-coupling of the second bit line BL2occurs during the first develop time DT1, a data value stored in the second sensing latch SL2during a sensing time ST may not be changed. Accordingly, the reliability of data detected by the second page buffer PB2may be maintained.

FIG.12Ais a timing diagram of control signals for performing a data detection operation based on different control timings.FIG.12Bis a timing diagram showing the voltage changes of sensing nodes with respect to the control signals ofFIG.12A. In detail, the embodiment ofFIGS.12A and12Bmay correspond to the embodiment ofFIG.8B. The control signals ofFIG.12Amay be generated in a similar manner to the control signals ofFIG.11A, and thus, redundant descriptions thereof will be omitted.

Referring toFIGS.9,12A, and12B, the develop operation of the first page buffer PB1may be started before the develop operation of the second page buffer PB2is terminated. For example, before the second bit line connection control signal CLBLK2transits from the high level to the low level at a second time point t32, the first precharge control signal PSO1may transit from the low level to the high level. Accordingly, the first develop time DT1may partially overlap with the second develop time DT2. In other words, an overlap time OT may occur.

During the overlap time OT, the voltage of the second bit line BL2may be decreased due to down-coupling. Because the second bit line connection control signal CLBLK2is maintained at the high level during the overlap time OT, the voltage of the second sensing node SO2may be changed according to the voltage change of the second bit line BL2. For example, during the second develop time DT2, the voltage of the second sensing node SO2may be developed to a voltage Vs' due to down-coupling. The voltage Vs' involved in down-coupling may be lower than the voltage Vs in the example ofFIGS.11A and11B(for example, when there is no down-coupling influence).

Even when the voltage of the second sensing node SO2is decreased due to down-coupling in the develop operation of the second page buffer PB2, the voltage Vs' of the second sensing node SO2may be higher than the reference voltage Vref due to the short duration of the overlap time OT. Accordingly, the reliability of data detected by the second page buffer PB2may be maintained.

In an example embodiment, the second page buffer PB2may be controlled to decrease the second develop time DT2such that the down-coupling influence during the overlap time OT is reduced. In other words, the second page buffer PB2may be controlled such that the overlap time OT is reduced. Accordingly, even when the voltage of the second sensing node SO2is decreased due to down-coupling during the overlap time OT, the voltage Vs' of the second sensing node SO2may be maintained to be higher than the reference voltage Vref.

FIG.13Ais a timing diagram of control signals for performing a data detection operation based on different control timings.FIG.13Bis a timing diagram showing the voltage changes of sensing nodes with respect to the control signals ofFIG.13A. In detail, the embodiment ofFIGS.13A and13Bmay correspond to the embodiment ofFIG.8C.

Referring toFIGS.9,13A, and13B, the first and second bit line shut-off signals BLSHF1and BLSHF2may be controlled to be at the high level. The first precharge control signal PSO1may be controlled to be at the low level from a first time point t41to a third time point t43. Accordingly, the precharge operation of the first page buffer PB1may be performed from the first time point t41to the third time point t43. During the first precharge time PT1of the first page buffer PB1, the voltage of the first sensing node SO1may be increased to a voltage level corresponding to the precharge voltage Vpre.

The second precharge control signal PSO2may be controlled to be at the low level from a second time point t42to a fifth time point t45. Accordingly, the precharge operation of the second page buffer PB2may be performed from the second time point t42to the fifth time point t45. During the second precharge time PT2of the second page buffer PB2, the voltage of the second sensing node SO2may be increased to a voltage level corresponding to the precharge voltage Vpre.

While the first precharge control signal PSO1and the first bit line connection control signal CLBLK1are being controlled to be at the high level (i.e., during a time period from the third time point t43to a fourth time point t44), the develop operation of the first page buffer PB1may be performed. During the first develop time DT1of the first page buffer PB1, the voltage of the first sensing node SO1may be developed according to data stored in the first memory cell MC1. When the first memory cell MC1is an on-cell, the voltage of the first sensing node SO1may be decreased below the reference voltage Vref. In this case, the second bit line BL2may be down-coupled according to the voltage change of the first sensing node SO1. Even when the second bit line BL2is down-coupled, the precharge operation of the second sensing node SO2may be normally performed. For example, when the second precharge time PT2is maintained until the down-coupling influence disappears or when the second bit line connection control signal CLBLK2is controlled to be at the high level after the down-coupling influence disappears, the precharge operation of the second sensing node SO2may be normally performed. Accordingly, the second sensing node SO2may have a voltage corresponding to the precharge voltage Vpre during the second precharge time PT2.

While the second precharge control signal PSO2and the second bit line connection control signal CLBLK2are being controlled to be at the high level (i.e., during a time period from the fifth time point t45to a sixth time point t46), the develop operation of the second page buffer PB2may be performed. During the second develop time DT2of the second page buffer PB2, the voltage of the second sensing node SO2may be developed according to data stored in the second memory cell MC2. When the second memory cell MC2is an off-cell, the voltage of the second sensing node SO2may be developed to the voltage Vs higher than the reference voltage Vref. Because the second sensing node SO2has a voltage corresponding to the precharge voltage Vpre during the second precharge time PT2, the voltage of the second sensing node SO2may be developed regardless of down-coupling occurring during the first develop time DT1.

The first and second sensing monitoring signals MON1and MON2may be controlled to be at the high level from the sixth time point t46to a seventh time point t47. Accordingly, data sensed by the first sensing node SO1and data sensed by the second sensing node SO2may be respectively stored in the first and second sensing latches SL1and SL2. As described above, because the developed voltage of the second sensing node SO2is not changed even if down-coupling occurs during the first develop time DT1, a data value stored in the second sensing latch SL2during a sensing time ST may not be changed. Accordingly, the reliability of data detected by the second page buffer PB2may be maintained.

FIG.14Ais a timing diagram of control signals for performing a data detection operation based on different control timings.FIG.14Bis a timing diagram showing the voltage changes of sensing nodes with respect to the control signals ofFIG.14A. In detail, the embodiment ofFIGS.14A and14Bmay correspond to the embodiment ofFIG.8D. The control signals ofFIG.14Amay be generated in a similar manner to the control signals ofFIG.13A, and thus, redundant descriptions thereof will be omitted.

Referring toFIGS.9,14A, and14B, the develop operation of the second page buffer PB2may be started before the develop operation of the first page buffer PB1is terminated. For example, before the first bit line connection control signal CLBLK1transits from the high level to the low level at a second time point t52, the second precharge control signal PSO2may transit from the low level to the high level. Accordingly, the first develop time DT1may partially overlap with the second develop time DT2. In other words, the overlap time OT may occur.

During the overlap time OT, the voltage of the second bit line BL2may be decreased due to down-coupling. Because the second bit line connection control signal CLBLK2is maintained at the high level during the overlap time OT, the voltage of the second sensing node SO2may be changed according to the voltage change of the second bit line BL2. For example, during the second develop time DT2, the voltage of the second sensing node SO2may be developed to the voltage Vs' due to down-coupling. The voltage Vs' involved in down-coupling may be lower than the voltage Vs in the example ofFIGS.13A and13B(for example, when there is no down-coupling influence).

Even when the voltage of the second sensing node SO2is decreased due to down-coupling in the develop operation of the second page buffer PB2, the voltage Vs' of the second sensing node SO2may be higher than the reference voltage Vref due to the duration of the second develop time DT2. Accordingly, the reliability of data detected by the second page buffer PB2may be maintained.

In an example embodiment, the second page buffer PB2may be controlled to decrease the second develop time DT2such that the down-coupling influence during the overlap time OT is reduced. Accordingly, even when the voltage of the second sensing node SO2is decreased due to down-coupling, the voltage of the second sensing node SO2may be developed to the voltage Vs' higher than the reference voltage Vref during the second develop time DT2.

As described above, when the first page buffer PB1and the second page buffer PB2are controlled such that the first develop time DT1partially overlaps with the second develop time DT2, a total time of a data detection operation may be reduced even if a sensing margin is reduced with the decrease in the voltage of the second sensing node SO2.

As described above with reference toFIGS.11A through14B, the first page buffer PB1and the second page buffer PB2may be controlled based on different control timings. For example, a precharge time of the first page buffer PB1may be different from a precharge time of the second page buffer PB2, and a develop time of the first page buffer PB1may be different from a develop time of the second page buffer PB2. In this case, the reliability of data detected by a page buffer may be maintained regardless of the precharge or develop operation of an adjacent page buffer.

FIG.15is an example cross-sectional view of the memory device ofFIG.5. In detail,FIG.15shows a cross-sectional view of a memory device500having the C2C structure. Referring toFIG.15, a cell region CELL of the memory device500may correspond to the first semiconductor layer L1, and a peripheral circuit region PERI of the memory device500may correspond to the second semiconductor layer L2. Each of the cell region CELL and the peripheral circuit region PERI of the memory device500may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate610, an interlayer insulating layer615, a plurality of circuit elements620a,620b, and620cformed on the first substrate610, first metal layers630a,630b, and630crespectively connected to the plurality of circuit elements620a,620b, and620c, and second metal layers640a,640b, and640cformed on the first metal layers630a,630b, and630c. In an example embodiment, the first metal layers630a,630b, and630cmay be formed of tungsten having relatively high resistivity, and the second metal layers640a,640b, and640cmay be formed of copper having relatively low resistivity.

In an example embodiment, although only the first metal layers630a,630b, and630cand the second metal layers640a,640b, and640care shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers640a,640b, and640c. At least a portion of the one or more additional metal layers formed on the second metal layers640a,640b, and640cmay be formed of aluminum or the like having a lower resistivity than those of copper forming the second metal layers640a,640b, and640c.

The interlayer insulating layer615may be disposed on the first substrate610and cover the plurality of circuit elements620a,620b, and620c, the first metal layers630a,630b, and630c, and the second metal layers640a,640b, and640c. The interlayer insulating layer615may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals671band672bmay be formed on the second metal layer640bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals671band672bin the peripheral circuit region PERI may be electrically bonded to upper bonding metals571band572bof the cell region CELL. The lower bonding metals671band672band the upper bonding metals571band572bmay be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals571band572bin the cell region CELL may be referred to as first metal pads and the lower bonding metals5271band5272bin the peripheral circuit region PERI may be referred to as second metal pads.

The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate510and a common source line520. On the second substrate510, a plurality of word lines531to538(i.e.,530) may be stacked in a direction (a third direction D3), perpendicular to an upper surface of the second substrate510. At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines530, respectively, and the plurality of word lines530may be disposed between the at least one string select line and the at least one ground select line.

In the bit line bonding area BLBA, a channel structure CH may extend in a direction (a third direction D3), perpendicular to the upper surface of the second substrate510, and pass through the plurality of word lines530, the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer550cand a second metal layer560c. For example, the first metal layer550cmay be a bit line contact, and the second metal layer560cmay be a bit line. In an example embodiment, the bit line560cmay extend in a second direction D2, parallel to the upper surface of the second substrate510.

In an example embodiment, an area in which the channel structure CH, the bit line560c, and the like are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line560cmay be electrically connected to the circuit elements620cproviding a page buffer593in the peripheral circuit region PERI. The bit line560cmay be connected to upper bonding metals571cand572cin the cell region CELL, and the upper bonding metals571cand572cmay be connected to lower bonding metals671cand672cconnected to the circuit elements620cof the page buffer593. Accordingly, the page buffer593may be connected to the bit line560cthrough the upper bonding metals571cand572cand the lower bonding metals671cand672c. In an example embodiment, the page buffer593may correspond to a page buffer described with reference toFIGS.1through14B. Although not shown inFIG.15, a page buffer controller described with reference toFIGS.1through14Bmay be further provided in the bit line bonding area BLBA. For example, the page buffer controller may control page buffers based on different control timings.

In the word line bonding area WLBA, the plurality of word lines530may extend in a first direction D1, parallel to the upper surface of the second substrate510, and may be connected to a plurality of cell contact plugs541to547(i.e.,540). The plurality of word lines530and the plurality of cell contact plugs540may be connected to each other via pads provided by at least a portion of the plurality of word lines530extending in different lengths in the second direction. A first metal layer550band a second metal layer560bmay be sequentially connected to an upper portion of the plurality of cell contact plugs540connected to the plurality of word lines530. The plurality of cell contact plugs540may be connected to the peripheral circuit region PERI by the upper bonding metals571band572bof the cell region CELL and the lower bonding metals671band672bof the peripheral circuit region PERI in the word line bonding area WLBA.

The plurality of cell contact plugs540may be electrically connected to the circuit elements620bproviding a row decoder594in the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elements620bof the row decoder594may be different than operating voltages of the circuit elements620cproviding the page buffer593. For example, operating voltages of the circuit elements620cproviding the page buffer593may be greater than operating voltages of the circuit elements620bproviding the row decoder594.

A common source line contact plug580may be disposed in the external pad bonding area PA. The common source line contact plug580may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line520. A first metal layer550aand a second metal layer560amay be sequentially stacked on an upper portion of the common source line contact plug580. For example, an area in which the common source line contact plug580, the first metal layer550a, and the second metal layer560aare disposed may be defined as the external pad bonding area PA.

Input-output pads605and505may be disposed in the external pad bonding area PA. A lower insulating film601covering a lower surface of the first substrate610may be formed below the first substrate610, and a first input-output pad605may be formed on the lower insulating film601. The first input-output pad605may be connected to at least one of the plurality of circuit elements620a,620b, and620cdisposed in the peripheral circuit region PERI through a first input-output contact plug603, and may be separated from the first substrate610by the lower insulating film601. In addition, a side insulating film may be disposed between the first input-output contact plug603and the first substrate610to electrically separate the first input-output contact plug603and the first substrate610.

An upper insulating film501covering the upper surface of the second substrate510may be formed on the second substrate510, and a second input-output pad505may be disposed on the upper insulating layer501. The second input-output pad505may be connected to at least one of the plurality of circuit elements620a,620b, and620cdisposed in the peripheral circuit region PERI through a second input-output contact plug503.

According to embodiments, the second substrate510and the common source line520may not be disposed in an area in which the second input-output contact plug503is disposed. Also, the second input-output pad505may not overlap the word lines530in the third direction (the third direction D3). The second input-output contact plug503may be separated from the second substrate510in a direction, parallel to the upper surface of the second substrate510, and may pass through an interlayer insulating layer of the cell region CELL to be connected to the second input-output pad505.

According to embodiments, the first input-output pad605and the second input-output pad505may be selectively formed. For example, the memory device400may include only the first input-output pad605disposed on the first substrate610or the second input-output pad505disposed on the second substrate510. Alternatively, the memory device400may include both the first input-output pad605and the second input-output pad505.

A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

In the external pad bonding area PA, the memory device500may include a lower metal pattern673a, corresponding to an upper metal pattern572aformed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern572aof the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern673aformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern, corresponding to the lower metal pattern formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL.

The lower bonding metals671band672bmay be formed on the second metal layer640bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals671band672bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals571band572bof the cell region CELL by a Cu-to-Cu bonding.

Further, in the bit line bonding area BLBA, an upper metal pattern592, corresponding to a lower metal pattern652formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern652, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern592formed in the uppermost metal layer of the cell region CELL.

In an example embodiment, the memory cell array210inFIG.2may be arranged in the cell region CELL, and the peripheral circuits PECT inFIG.2may be arranged in the peripheral circuit region PERI. For example, the page buffer circuit220and the page buffer controller230, which have been described with reference toFIGS.1through14B, may be arranged in the peripheral circuit region PERI. Accordingly, the memory device500may control page buffers, which are adjacent to each other, based on different control timings.

FIG.16is a block diagram of an SSD system using a memory device according to an embodiment. Referring toFIG.16, an SSD system1000may include a host1100and an SSD1200.

The SSD1200may exchange signals SIG with the host1100through a signal connector1201and may receive power PWR through a power connector1202. The SSD1200may include an SSD controller1210, a plurality of flash memories1221through122n, an auxiliary power supply1230, and a buffer memory1240. The flash memories1221through122nmay be connected to the SSD controller1210through a plurality of channels, respectively.

The SSD controller1210may control the flash memories1221through122nin response to a signal SIG received from the host1100. The SSD controller1210may store an internally generated signal or an externally received signal (e.g., the signal SIG received from the host1100) in the buffer memory1240. The SSD controller1210may correspond to the memory controller100described above with reference toFIG.1.

The flash memories1221through122nmay operate under the control of the SSD controller1210. The auxiliary power supply1230is connected to the host1100through the power connector1202. Each of the flash memories1221through122nmay correspond to any one of the memory devices200,300,400, and500described above with reference toFIGS.1through15. For example, each of the flash memories1221through122nmay control page buffers, which are adjacent to each other, based on different control timings.

The auxiliary power supply1230may be connected to the host1100through the power connector1202. The auxiliary power supply1230may receive the power PWR from the host1100and may be charged. The auxiliary power supply1220may supply power to the SSD1200when power is not smoothly supplied from the host1100.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.