Patent ID: 12232335

DETAILED DESCRIPTION

In the following description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments. Although various embodiments described herein are described with respect to RRAM cells, in other embodiments, these technologies can be used in other filamentary RAM technologies, including, for example, CBRAM cells, interfacial RRAM cells, MRAM cells, PCM cells, or other programmable metallization cells.

Resistive random-access memory (RRAM) is a type of non-volatile random-access memory. An RRAM structure includes a bottom electrode that is formed of a conductive material. The RRAM structure further includes a switchable layer disposed above the bottom electrode. When a voltage is applied to the switchable layer, one or more oxygen vacancies (e.g., switchable filaments) may be formed in the switchable layer. The oxygen vacancies may provide a conductive path across the switchable layer. Therefore, the switchable layer may be in a low resistance state when oxygen vacancies are formed. Conversely, the switchable layer may be in a high resistance state when the oxygen vacancies are broken (e.g., reset). A resistive layer may be disposed above the switchable layer.

Memory cells of the RRAM structure (also referred to as “RRAM cells” hereafter) may be formed at an intersection of a bit line and a word line or above vias of a semiconductor device. The RRAM cells may be formed using an etching or plasma process. A masking material may be applied to a portion of the upper surface of the resistive layer that resists an etching chemical or plasma. The switching layer and resistive layer may be exposed to the etching chemical or plasma to form the RRAM cells. Following the etching or plasma process, a top electrode layer may be disposed above the resistive layer and a masking material may be applied to a portion of the upper surface of the top electrode layer. Then a second etching or plasma process may be performed on the top electrode layer to form top electrodes (e.g., bit lines) of the RRAM structure. In order to form the individual RRAM cells of the RRAM structure, multiple masking operations may be performed, increasing the cost to produce and manufacture the RRAM structure as well as the complexity of the manufacturing process. Furthermore, the etching or plasma process may leave extra material around the RRAM cells, causing cell edge effects that decrease RRAM cell performance and uniformity.

Embodiments of the present disclosure can address the above-mentioned and other deficiencies by extending the resistive layer laterally across multiple memory cells of a bit line, reducing the number of masking and etching operations required to produce an RRAM structure to a single masking and etching operation. The top electrode layer may be disposed above the resistive layer without performing a masking and etching operation on the resistive layer. Then, a single masking and etching operation may be performed on the top electrode layer and the resistive layer, reducing the cost to produce and manufacture the RRAM structure. Furthermore, by reducing the amount of material that may be removed by the etching or plasma process, the amount of extra material present around the RRAM cells after the etching operation may decrease, reducing cell edge effects and improving cell performance and uniformity. Embodiments of the present disclosure may provide other benefits in addition to those previously discussed.

FIG.1illustrates an RRAM structure100having a switching layer that is a planar sheet in accordance with an embodiment. The RRAM structure100may include a semiconductor structure110. The semiconductor structure may include vias150that serve as vertically conductive paths between a switching layer120and underlying components of the semiconductor device110. In one embodiment, the vias150may be made of a conductive material. Examples of conductive materials include, but are not limited to, copper, gold, silver, tungsten or similar materials. Forming the vias150from tungsten may improve the performance of the RRAM structure100because the tungsten is easily oxidized (e.g., oxygen is trapped by the tungsten to form tungsten oxide) when the switching layer120is switching between a high resistance state and a low resistance state and vice versa, as will be discussed in more detail below. In some embodiments, the tungsten oxidation may be controlled using optimized algorithms to improve the endurance of the RRAM structure100.

A switching layer120may be disposed above the semiconductor device and the vias150. The switching layer120may be disposed using chemical vapor deposition (CVD), atomic layer deposition (ALD) or any suitable method. In one embodiment, the switching layer120may be made of a dielectric material, such as a transition metal oxide (TMO). Examples of TMO's include, but are not limited to, stoichiometric Hafnium Oxide (HfOx), stoichiometric Tantalum Oxide (TaOx), or other similar materials. The switching layer120may include one or more oxygen vacancies160that may serve as a conductive path through the switching layer120. In one embodiment, the oxygen vacancies160may serve as a conductive path between vias150and a resistive layer130. In some embodiments, rather than forming an oxygen vacancy160when a voltage is applied to the switching layer120, a metallic conductive filament may be formed. The oxygen vacancies160may be formed by applying a voltage to the switching layer120. The switching layer120may have a resistance value, where the resistance value may change upon application of a voltage. For example, the switching layer120may switch between a high resistance state and a low resistance state when a voltage is applied. In one embodiment, the high resistance state may be between 100-500 kiloohms and the low resistance state may be between 10-30 kiloohms, inclusively. In some embodiments, a ratio of the high resolution state to the low resistance state may be greater than1. For example, if the resistance of the high resolution state is 100 kiloohms and the resistance in the low resolution state is 10 kiloohms, the ratio may be 10 (e.g., 100 kiloohms/10 kiloohms). In some embodiments, the ratio of the high resistance state to the low resistance state may be greater than10. In one embodiment, the switching layer120may be a planar sheet disposed above the semiconductor device110and vias150.

A resistive layer130may be disposed above the switching layer120. The resistive layer130may be disposed using CVD, ALD or any suitable method. In one embodiment, the resistive layer130may be a conductive material. In another embodiment, the resistive layer130may be a conductive metal oxide (CMO). The resistive layer130may extend laterally to connect to two or more vias150through the switching layer120. In some embodiments, each via150may correspond to a memory cell and the resistive layer130may extend laterally to connect two or more memory cells along the top electrode140. In one embodiment, the vias150may connect to the drains of N-type metal-oxide semiconductor (NMOS) transistors. A top electrode140may be disposed above the resistive layer130. The top electrode140may be a conductive material. Examples of conductive materials include, but are not limited to, aluminum, copper or any similar materials. The top electrode140may be disposed above the resistive layer130using CVD, ALD or any suitable method to form memory cells170,180at the intersection of vias150and top electrodes140. The top electrode140may extend laterally along the resistive layer130. In some embodiments, the top electrode140may be a bit line and the resistive layer130may connect two or more memory cells along the bit line. For example, the resistive layer130and top electrode140may extend laterally to connect memory cell170to memory cell180. In some embodiments the top electrode140corresponds to a standard metallization layer used for other connections on the semiconductor device. Although embodiments of the present disclosure illustrate the switching layer120and resistive layer130between a via150and a top electrode140, in other embodiments the switching layer120and resistive layer130may be located between any via and any metal layer of a semiconductor structure.

FIG.2illustrates an RRAM structure200having a switching layer that extends laterally in accordance with an embodiment. The RRAM structure200may include a semiconductor structure210. The semiconductor structure may include vias250that serve as vertically conductive paths between a switching layer220and underlying components of the semiconductor device210. In one embodiment, the vias250may be made of a conductive material, such as tungsten. A switching layer220may be disposed above the semiconductor device and the vias250. The switching layer220may be disposed using CVD, ALD or any suitable method. In one embodiment, the switching layer220may be a dielectric material. In another embodiment, the switching layer220may be a TMO. In further embodiments, the switching layer220may be HfOx, TaOx, TiOx or other similar materials. The switching layer220may include one or more oxygen vacancies260that may serve as a conductive path through the switching layer120. The oxygen vacancies260may be formed by applying a voltage to the switching layer220. The switching layer220may have a resistance value that changes upon application of a voltage. For example, the switching layer220may switch between a high resistance state and a low resistance state when a voltage is applied. In one embodiment, the switching layer220may extend laterally above two or more vias250.

A resistive layer230may be disposed above the switching layer220. The resistive layer230may be disposed using CVD, ALD or other method. In one embodiment, the resistive layer230may be a conductive material. In another embodiment, the resistive layer230may be a CMO. The resistive layer230may extend laterally to connect to two or more vias250through switching layer220. In some embodiments, each via250may correspond to a memory cell and the resistive layer230may extend laterally to connect two or more memory cells along the top electrode240. In one embodiment, the vias250may connect to a drain of an N-type metal-oxide semiconductor (NMOS) transistor. A top electrode240may be disposed above the resistive layer230. The top electrode240may be a conductive material. Examples of conductive materials include, but are not limited to, aluminum, copper, or any similar materials. The top electrode240may be disposed above the resistive layer230using CVD, ALD or any suitable method to form memory cells270,280at the intersection of vias250and top electrodes240. The top electrode240may extend laterally along the resistive layer230. In some embodiments, the top electrode240may be a bit line and the resistive layer230may connect two or more memory cells along the bit line. For example, the resistive layer230and top electrode240may extend laterally to connect memory cell270to memory cell280. In some embodiments the top electrode240corresponds to a standard metallization layer used for other connections on the semiconductor device. Although embodiments of the present disclosure illustrate the switching layer220and resistive layer230between a via250and a top electrode240, in other embodiments the switching layer220and resistive layer230may be located between any via and any metal layer of a semiconductor structure.

FIG.3illustrates an RRAM structure300having a non-linear device layer in accordance with an embodiment. The RRAM structure300may include word lines310. The word lines310may be made of a conductive material and may connect the gates of transistors for an array segment. Examples of conductive materials include, but are not limited to, copper, tungsten or any similar material. The word lines310may be orthogonal to bit lines340, which will be discussed in more detail below. A switching layer320may be disposed above the bottom electrodes310. The switching layer320may be disposed using CVD, ALD or any suitable method. In one embodiment, the switching layer320may be a dielectric material. In another embodiment, the switching layer320may be a TMO. In further embodiments, the switching layer320may be HfOx, TaOx, TiOx or other similar materials. The switching layer320may include one or more oxygen vacancies360that may serve as a conductive path through the switching layer320. The oxygen vacancies360may be formed by applying a voltage to the switching layer320. The switching layer320may have a resistance value that changes upon application of a voltage. For example, the switching layer320may switch between a high resistance state and a low resistance state when a voltage is applied. Although the switching layer320may be illustrated as a planar sheet, in some embodiments the switching layer320may extend laterally along bit lines340as shown inFIG.2. A resistive layer330may be disposed above the switching layer320. The resistive layer330may be disposed using CVD, ALD or any suitable method. In one embodiment, the resistive layer330may be a conductive material. In another embodiment, the resistive layer330may be a CMO. The resistive layer330may extend laterally to connect to two or more memory cells along bit lines340. For example, the resistive layer330and bit line340may extend laterally to connect memory cell370to memory cell380.

A non-linear device layer350may be disposed above the resistive layer330. The non-linear device layer350may exhibit a high resistance for a particular range of voltages and a low resistance range for voltages above and below the particular range of voltages. In one embodiment, the range of voltage may be less than three volts. The non-linear device layer350may cause the RRAM structure300to exhibit a non-linear resistive characteristic. In some embodiments, the non-linear device layer350may be disposed below the switching layer320and the word line310. In one embodiment, the non-linear device layer350may be two oppositely oriented diodes connected in series. When the diodes are oppositely oriented, one diode's forward current may be blocked by the other diode at voltages in the particular range of voltages. The particular range of voltages may correspond to a breakdown voltage of the diodes, where the breakdown voltage may be the minimum voltage that causes a portion of the diodes to become electrically conductive. In another embodiment, the non-linear device layer350may be a metal-insulator-metal (MIM) tunneling device. A bit line340may be disposed above the resistive layer330. The bit line340may be a conductive material. The bit line340may be disposed above the resistive layer330using CVD, ALD or any suitable method to form memory cells370,380at the intersection of word lines310and bit lines340. The bit line340may extend laterally along the resistive layer330.

FIG.4is a flow diagram of a fabrication process for the manufacture of an RRAM structure in accordance with an embodiment. It may be noted that elements ofFIGS.1-3may be described below to help illustrate method400. Method400may be performed as one or more operations. It may be noted that method400may be performed in any order and may include the same, more or fewer operations. It may be noted that method400may be performed by one or more pieces of semiconductor fabrication equipment or fabrication tools.

Method400begins at block410by disposing a switching layer above a substrate. In one embodiment, the substrate may be a semiconductor device including vias. In another embodiment, the switching layer may be disposed above word lines of a memory structure. The switching layer may be disposed by CVD, ALD or any suitable process. In one embodiment, the switching layer may be a dielectric material. In another embodiment, the switching layer may be a TMO. In further embodiments, the switching layer may be HfOx. At block420, a resistive layer may be disposed above the switching layer. The resistive layer may be disposed by CVD, ALD or any suitable process. In one embodiment, the resistive layer may be a conductive material. In another embodiment, the resistive layer may be a CMO. At block430, a top electrode layer may be disposed above the resistive layer. The top electrode layer may be disposed by CVD, ALD or any suitable process. In one embodiment, the top electrode layer may be a conductive material. Examples of conductive materials include, but are not limited to, gold, silver, copper, tungsten, or any other suitable material.

At block440a masking material may be disposed on the upper surface of the top electrode layer that resists an etching chemical or plasma. In one embodiment, the masking material may be disposed on portions of the upper surface of the top electrode layer to form a top electrode (e.g., bit lines) of a RRAM structure when exposed to the etching chemical or plasma. At block450, the RRAM structure may be exposed to an etching chemical or plasma which may remove areas of the RRAM structure exposed by the masking material. In one embodiment, the etching or plasma process may only remove portions of the top electrode layer and the resistive layer, while the switching layer may remain a planar sheet. The top electrode and the resistive layer may extend laterally to connect multiple memory cells along a bit line. In another embodiment, the etching or plasma process may remove portions of the top electrode layer, the resistive layer and the switching layer. The top electrode, the resistive layer and the switching layer may extend laterally to connect multiple memory cells along a bit line. At block460, the masking material may be removed from the upper surface of the top electrode.

The above description of illustrated embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. Other embodiments may have layers in different orders, additional layers or fewer layers than the illustrated embodiments.

Various operations are described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

The terms “over,” “above” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer deposited above or over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer deposited between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature deposited between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims may generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an embodiment” or “one embodiment” or “an embodiment” or “one embodiment” throughout is not intended to mean the same embodiment or embodiment unless described as such. The terms “first,” “second,” “third,” “fourth,” etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation.