Patent ID: 12189241

DETAILED DESCRIPTION

The electronic device of the present disclosure is described in detail in the following description. It should be understood that in the following detailed description, for purposes of explanation, numerous specific details and embodiments are set forth in order to provide a thorough understanding of the present disclosure. The elements and configurations described in the following detailed description are set forth in order to clearly describe the present disclosure. The embodiments are used merely for the purpose of illustration. In addition, the drawings of different embodiments may use like and/or corresponding numerals to denote like and/or corresponding elements in order to clearly describe the present disclosure. However, the use of like and/or corresponding numerals in the drawings of different embodiments does not suggest any correlation between different embodiments.

The present disclosure can be understood by referring to the following detailed description in connection with the accompanying drawings. It should be noted that, in order to allow the reader to easily understand the drawings, several drawings in the present disclosure only depict a portion of the electronic device, and the specific elements in the drawings are not drawn to scale. In addition, the number and size of each element in the drawings are only for illustration, and are not limited the scope of the present disclosure.

Throughout the present disclosure and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that electronic device manufacturers may refer to the same element with different names. The present disclosure does not intend to distinguish between elements that have the same function but different names. In the specification and claims, the terms “comprising”, “including”, “having” and the like are open-ended phrases, so they should be interpreted as “including but is not limited to . . . ”. Therefore, when the terms “comprising”, “including” and/or “having” are used in the description of the present disclosure, they specify the corresponding features, regions, steps, operations and/or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and/or components.

Directional terms mentioned in the present disclosure, such as “upper”, “lower”, “front”, “rear”, “left”, “right”, etc., are only the directions referring to the drawings. Therefore, the directional terms are used for illustration, not for limiting the present disclosure. In the drawings, each drawing depicts general features of methods, structures, and/or materials used in particular embodiments. However, these drawings should not be interpreted as defining or limiting the scope or property encompassed by these embodiments. For example, for clarity, the relative sizes, thicknesses, and positions of the various layers, regions, and/or structures may be reduced or enlarged.

When a corresponding component (such as a layer or region) is referred to as “(disposed or located) on another component”, it may be directly (disposed or located) on another component, or there may be other components between them. On the other hand, when a component is referred to as “directly (disposed or located) on another component”, there is no component existing between them. In addition, when a component is referred to as “(disposed or located) on another component”, the two have an upper-lower relationship in a top-view direction, and this component may be above or below another component, and the upper-lower relationship depends on the orientation of the device.

The terms “about”, “equal to”, “the same as”, “identical to”, “substantially” or “approximately” are generally interpreted as being within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1% or 0.5% of the given value or range.

The ordinal numbers used in the specification and claims, such as the terms “first”, “second”, etc., are used to modify an element, which itself does not mean and represent that the element (or elements) has any previous ordinal number, and does not mean the order of a certain element and another element, or the order in the manufacturing method. The use of these ordinal numbers is used to make a component with a certain name can be clearly distinguished from another component with the same name. The same words may not be used in the claims and the specification. Accordingly, the first component in the specification may be the second component in the claims.

It should be noted that the following embodiments can replace, recombine, and mix features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features between the various embodiments can be mixed and used arbitrarily as long as they do not violate or conflict the spirit of the present disclosure.

In the present disclosure, the length and the width of the component can be measured from an optical microscope image, and the thickness of the component can be measured from a cross-sectional image in an electron microscope, but it is not limited thereto. In addition, certain errors may exist between any two values or directions used for comparison. If the first value is equal to the second value, it implies that there may be an 10% error between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should be appreciated that, in each case, the term, which is defined in a commonly used dictionary, should be interpreted as having a meaning that conforms to the relative skills of the present disclosure and the background or the context of the present disclosure, and should not be interpreted in an idealized or overly formal manner unless so defined.

In accordance with some embodiments of the present disclosure, the provided electronic device includes spacers with a large buffer space for displacement. In detail, for example, spacers (such as the first spacer and the second spacer as follows) are disposed on the two substrates respectively, and these spacers may contact or intersect each other, and these spacers respectively have part that overlaps with the opposite spacer and other parts that do not overlap with the opposite spacers. In addition, the area (or length) of the non-overlapping part (or portion) may be greater than or equal to the area (or length) of the overlapping part (or portion). When the panel is subjected to external force, the above design can reduce the slippage of the spacers due to displacement, which affecting other layers (for example, alignment layer, but it is not limited thereto) on the opposite substrate. For example, when the spacer shifts and slips, and scratches the alignment layer disposed on the opposite substrate, or uneven alignment may occur.

In accordance with some embodiments of the present disclosure, the electronic device may include a display device, a light-emitting device, a touch device, a sensing device, an antenna device or a tiled device (a tiled device having any of the above functions or a hybrid function), but it is not limited thereto. The electronic device may include a bendable electronic device or a flexible electronic device, but it is not limited thereto. For example, the electronic device may include, liquid-crystal, light-emitting diode (LED), quantum dot (QD), fluorescence, phosphor, other suitable materials or a combination thereof. For example, the light-emitting diode may include organic light-emitting diode (OLED), micro-LED, micro-LED, mini-LED or quantum dot light-emitting diode (QLED, QDLED), but it is not limited thereto. In some embodiments, the electronic device may include a panel and/or a backlight module. The panel includes a liquid-crystal panel, but it is not limited thereto. It should be understood that the liquid-crystal display device will be taken as an example to illustrate the disclosed electronic device, but it is not limited thereto.

Refer toFIG.1,FIG.2andFIG.3,FIG.1is a schematic partial top-view diagram of an electronic device10in accordance with some embodiments of the present disclosure.FIG.2is a schematic partial top-view diagram of the electronic device10in accordance with some embodiments of the present disclosure.FIG.3is a schematic cross-sectional diagram of the electronic device10taken along segment line C-C′ in the embodiment ofFIG.1. It should be understood that, some elements in the electronic device10are omitted inFIG.1,FIG.2, andFIG.3, and only some elements formed or disposed on the first substrate100or the second substrate200are schematically shown for clarity. In accordance with some embodiments, additional features or elements may be added to the electronic device10. In some embodiments, some features of the electronic device10described below may be optionally replaced or omitted.

Referring toFIG.1,FIG.2, andFIG.3, the electronic device10includes a first substrate100, a second substrate200, a first spacer102and a second spacer202. In some embodiments (also refer toFIG.6), the second substrate200is disposed opposite to the first substrate100, the first spacer102is disposed on the first substrate100, and the second spacer202is disposed on the second substrate200and between the first spacer102and the second substrate200. In some embodiments, the materials of the first substrate100and/or the second substrate200may include, but is not limited to, glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), photosensitive polyimide (PSPI), polyethylene terephthalate (PET), other suitable materials or a combination thereof.

Referring toFIG.1, in some embodiments, the first substrate100can be used as a driving substrate (or an array substrate), but it is not limited thereto. In some embodiments, the electronic device10may include a driving circuit (not illustrated) disposed on the first substrate100. The driving circuit may include an active driving circuit or a passive driving circuit. In some embodiments, the electronic device10includes a plurality of data lines DL and a plurality of scan lines SL (e.g., indicated by bold dotted lines) disposed on the first substrate100. The data lines DL and the scan lines SL are intersected to define a plurality of pixel units (e.g., sub-pixels, not illustrated), these pixel units have transistors100T, which respectively includes, but is not limited to, switching transistors or driving transistors. Refer toFIG.1, in some embodiments, the transistor100T includes a semiconductor layer104(thin dotted line), a source electrode SE (e.g., a part of the data line DL, and the source electrode SE may at least overlap with the semiconductor layer104), a drain electrode106and a gate electrode GE (e.g. a part of the scan line SL). The gate electrode GE is connected to the scan line SL, and the gate electrode GE may extend along the Y direction and protrude from the scan line SL, the source electrode SE, the drain electrode106and the gate electrode GE all may at least partially overlap with the semiconductor layer104.

As shown inFIG.3, in some embodiments, the scan line SL and/or the gate electrode GE are disposed on the first substrate100, and a first dielectric layer120is disposed (or covered) on the scan line SL and/or the gate electrode GE. The semiconductor layer104is disposed on the first dielectric layer120, the drain electrode106, the source electrode SE, and/or the data line DL are disposed on the first dielectric layer120. In addition, in a normal direction (e.g., the Z direction) of the first substrate100, the drain electrode106and the source electrode SE partially overlap with the semiconductor layer104and the scanning line SL (e.g., the gate electrode GE). In some embodiments, a second dielectric layer122is disposed on the first dielectric layer120, and is disposed or covered on the semiconductor layer104, the drain electrode106, the source electrode SE, and/or the data line DL. In some embodiments, a planarization layer110is disposed on the second dielectric layer122, and the planarization layer110may be disposed on the scan line SL, the data line DL, the semiconductor layer104, and/or the drain electrode106. In other words, the planarization layer110may cover the transistor100T. In some embodiments, the first dielectric layer120and/or the second dielectric layer122may serve as an inter-layer dielectric (ILD). In some embodiments, the material of the first dielectric layer120and/or the second dielectric layer122may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials or a combination thereof. In some embodiments, the planarization layer110may include, but is not limited to, organic materials, inorganic materials, other suitable materials, or a combination thereof. For example, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials or a combination thereof, but it is not limited thereto. For example, the organic material may include epoxy resins, silicone resins, acrylic resins (such as polymethylmetacrylate (PMMA)), polyimide, perfluoroalkoxy alkane (PFA), other suitable materials or a combination thereof, but it is not limited thereto.

Referring toFIG.1andFIG.3at the same time, in some embodiments, the second dielectric layer122has a plurality of first through holes V1, and in a normal direction of the first substrate100, these first through holes V1overlap with at least a portion of the drain electrodes106. For example, the first through hole V1may penetrate the second dielectric layer122and expose a portion of the drain electrode106. In some embodiments, the pixel unit of the electronic device10may include a pixel electrode108. For example, the pixel electrode108may be disposed on a portion of the second dielectric layer122and/or a portion of the planarization layer110. The planarization layer110has a plurality of second through holes V2. In the Z direction, these second through holes V2overlap with the first through holes V1, and the pixel electrode108may be electrically connected to the transistor100T (e.g., the drain electrode106) through the second through holes V2and/or the first through holes V1, but it is not limited thereto. In some embodiments, the material of the pixel electrode108may include a metal conductive material, a transparent conductive material, other suitable materials or a combination thereof, but it is not limited thereto.

Referring toFIG.3, in some embodiments, the first spacer102may be disposed on the planarization layer110. In some embodiments, a thickness T1of the first spacer102may be less than or equal to a thickness T2of the planarization layer110. The thickness T1may be defined by a maximum thickness of the first spacer102in the Z direction in a cross-sectional image, and the thickness T2may be defined by a maximum thickness of the planarization layer110in the Z direction in a cross-sectional image. In some embodiments, the first spacer102is disposed on the planarization layer110, and the first spacer102is not disposed in the first through hole V1and/or the second through hole V2, the first spacer102has a more planar structure to reduce the slippage of the second spacer202when an external force is applied thereto.

Referring toFIG.1andFIG.3, in some embodiments, the first spacer102may be located between two adjacent first through holes V1. In some embodiments, in a normal direction (e.g., the Z direction) of the first substrate100, the first through hole V1does not overlap with the first spacer102. In some embodiments, the first spacer102may be located between two adjacent second through holes V2. In some embodiments, in the normal direction of the first substrate100, the second via hole V2does not overlap with the first spacer102. In some embodiments, a distance G1between the first spacer102and the first through hole V1may be greater than or equal to 5 micrometers (μm) (distance G1≥5 micrometers), but it is not limited thereto. The distance G1may be defined by a minimum distance between the first spacer102and the first through hole V1in the X direction. In some embodiments, the distance G1may be greater than or equal to 6 micrometers (μm) (distance G1≥6 micrometers), and the distance G1may be greater than or equal to 6.5 micrometers, 7 micrometers, or 7.5 micrometers. In some embodiments, the distance G1may be greater than or equal to 0.5 times a width W1of the first spacer102(distance G1≥0.5*width W1), but it is not limited thereto. In some embodiments, the distance G1may be greater than or equal to 0.55 times the width W1of the first spacer102(distance G10.55*width W1). In some embodiments, the distance G1may be, for example, greater than or equal to 0.6 times, 0.7 times, or 0.8 times the width W1of the first spacer102. In some embodiments, the distance G1may be less than 2.5 times the width W1of the first spacer102(distance G1<2.5*width W1). The width W1may be defined by a maximum width of the first spacer102in a direction (for example, X direction) perpendicular to an extending direction E102of the first spacer102. It should be understood that, the “extending direction” of an object refers to a direction along or substantially parallel to the long axis of the object. For example, the object can be encircled by a minimum rectangle, and the extending direction of the long side of the minimum rectangle is the direction of the long axis. In addition, the distance G1and the width W1can be measured in an image (for example an optical microscope image). For example, the width W1is obtained from measuring a maximum width between outer edges of the first spacer102in the direction perpendicular to the extending direction E102. For example, the distance G1is obtained from measuring a minimum distance between the outer edge of the first spacer102and the inner edge of the first through hole V1in the direction perpendicular to the extending direction E102.

It should be understood that although both the minimum distances between the first spacer102and the two adjacent first through holes V1in the drawing are denoted as G1, in accordance with some other embodiments, the distances G1between the first spacer102and the two adjacent first through holes V1may be the same or different. As described above, as shown inFIG.1toFIG.3, the first spacer102and/or the second spacer202is disposed between the first substrate100and the second substrate200, and the first spacer102and/or the second spacer202can serve as spacing elements. In some embodiments, the extending direction E102of the first spacer102is substantially the same as an extending direction E1of the data line DL, but it is not limited thereto. In some embodiments (not illustrated), an included angle θ1between the extending direction E102of the first spacer102and the extending direction E1of the data line DL may be between about 5 degrees and about 40 degrees (5 degrees≤included angle θ1≤40 degrees), but it is not limited thereto. In some embodiments, in the normal direction of the first substrate100, the first spacer102may overlap with the data line DL, and the above-mentioned “overlap with” means that the two at least partially overlap. Under the above design, the length of the first spacer102can be appropriately extended to increase the buffer space, and the first spacer102does not significantly occupy the aperture area of the pixel unit. Similarly, in some embodiments, the second spacer202may extend along an extending direction E202. In some embodiments (as shown inFIG.4), the extending direction E102of the first spacer102is different from the extending direction E202of the second spacer202. In some embodiments (as shown inFIG.4), the included angle θ between the extending direction E102of the first spacer102and the extending direction E202of the second spacer202may be between about 45 degrees and about 90 degrees (45 degrees≤included angle θ≤90 degrees), but it is not limited thereto. In some embodiments, the included angle θ between the extending direction E102of the first spacer102and the extending direction E202of the second spacer202may be between about 60 degrees and about 90 degrees (60 degrees≤included angle θ≤90 degrees). In some embodiments, the included angle θ between the extending direction E102of the first spacer102and the extending direction E202of the second spacer202may be between about 80 degrees and about 90 degrees (80 degrees≤included angle θ≤90 degrees).

In some embodiments, the material of the first spacer102and/or the second spacer202may include, but is not limited to, organic materials, inorganic materials, or a combination thereof. For example, the organic material may include epoxy resin, acrylic resin such as polymethylmetacrylate (PMMA), benzocyclobutene (BCB), polyethylene terephthalate (PET), polyethylene (PE), polyethersulfone (PES), polycarbonate (PC), other suitable materials or a combination thereof. In some embodiments, the material of the second spacer202may be the same as or different from the material of the first spacer102. As shown inFIG.2, in some embodiments, the second substrate200can be used as a color filter substrate, but it is not limited thereto. In some embodiments, the electronic device10may include a light-shielding layer204and/or a color filter layer206disposed on the second substrate200, and the second spacer202may be disposed on the light-shielding layer204. In addition, in the normal direction of the first substrate100, the light-shielding layer204may overlap with or cover the second spacer202. In some embodiments, the light-shielding layer204may include a black matrix, and the light-shielding layer204may have a plurality of openings OP. In addition, in the normal direction of the first substrate100, the color filter layer206may overlap with the openings OP of the light-shielding layer204. In some embodiments, the material of the light-shielding layer204may include, but is not limited to, black photoresist, black printing ink, black resin, metal, carbon black material, resin material, photosensitive material, other suitable materials or a combination thereof. In some embodiments, the color filter layer206may include a plurality of color filter units FU. For example, the color filter units FU may include red filter units, green filter units and/or blue filter units, but they are not limited thereto. In accordance with different embodiments, the color filter layer206may have a suitable number or color filter units FU of a suitable color.

Next, refer toFIG.4, which is a schematic top-view diagram of the electronic device10in accordance with some embodiments of the present disclosure. In detail,FIG.4includes the first substrate100and the second substrate200, andFIG.4may be an overlay diagram of the first substrate100shown inFIG.1(including elements disposed on the first substrate100) and the second substrate200shown inFIG.2(including elements disposed on the second substrate200). It should be understood that, in order to clearly describe the characteristics of specific elements, some elements of the electronic device10are omitted in the drawing, and the dashed line and solid line illustrated in the drawing may not represent the up-down relationship of the elements. In addition, the same or similar components (or elements) in the following paragraph will be denoted by the same or similar reference numbers, and their materials, manufacturing methods and functions are the same or similar to those described above, and thus they will not be repeated in the following context.

As shown inFIG.1toFIG.4, in some embodiments, the first spacer102and/or the second spacer202have an elongated structure, and the first spacer102and the second spacer202intersect (cross) with each other to form a cross-shaped or an X-shaped, but it is not limited thereto. In some embodiments, part of the first spacer102does not overlap with the second spacer202. Specifically, the first spacer102includes a first portion102a, a second portion102b, and a third portion102c. The first portion102aoverlaps with the second spacer202in the normal direction (e.g., the Z direction) of the first substrate100. The second portion102band the third portion102care respectively adjacent to the first portion102a, and the first portion102aconnects between the second portion102band the third portion102c. Furthermore, in some embodiments, the first portion102ahas a first length B1, the second portion102bhas a second length Da, the third portion102chas a third length Db. In addition, the second length Dais greater than or equal to the first length B1(the second length Da≥the first length B1), and the third length Dbis greater than or equal to the first length B1(the third length Db>the first length B1).

It should be noted that, the second portion102band/or the third portion102ccan serve as a shifting buffer region for the second spacer202. The second portion102band/or the third portion102ccan reduce the probability of the second spacer202shifting to an area outside the first spacer102when an external force is applied to the panel, or reduce the probability of the layer (e.g., alignment layer, not illustrated) disposed on the first substrate100being scratched by the second spacer202.

In some embodiments, the second length Dais greater than or equal to 10 micrometers (second length Da>10 micrometers), or greater than or equal to 12 micrometers, 14 micrometers, 16 micrometers, or 18 micrometers, but it is not limited thereto. In some embodiments, the third length Dbis greater than or equal to 10 micrometers (third length Db≥10 micrometers), or greater than or equal to 11 micrometers, 13 micrometers, 15 micrometers, or 17 micrometers, but it is not limited thereto.

In some embodiments, the ratio of the second length Daof the second portion102bto the first length B1of the first portion102ais greater than or equal to 1.4 (second length Da/first length B1≥1.4), or greater than or equal to 1.6, 1.8 or 2, but it is not limited thereto. In some embodiments, the ratio of the third length Dbof the third portion102cto the first length B1of the first portion102ais greater than or equal to 1.4 (third length Db/ first length B1≥1.4), or greater than or equal to 1.5, 1.7 or 1.9, but it is not limited thereto.

In some embodiments, the ratio of the third length Dbto the second length Dais between 0.6 and 1.7 (0.6≤third length Db/second length Da≤1.7), or between 0.8 and 1.5 (0.8≤third length Db/second length Da≤1.5), for example, may be 0.9, 1, 1.1, 1.2, 1.3 or 1.4, but it is not limited thereto.

It should be noted that, the aforementioned first length B1, second length Da, and third length Dbare measured along a reference line on the same image (e.g., OM image). The reference line may be a line extending in any direction paralleled to the surface of the first substrate100(for example, the XY plane in the drawing), as long as the first length B1, the second length Daand the third length Dbmeet the above-mentioned relationships that the second length Dais greater than or equal to the first length B1, and the third length Dbis greater than or equal to the first length B1. In accordance with some embodiments, the extending direction E102of the first spacer102can be used as a reference line. In other words, the aforementioned first length B1, second length Daand third length Dbcan be measured along the extending direction E102of the first spacer102, but it is not limited thereto.

In some embodiments, the first spacer102has a length L1in the extending direction E102, and the length L1is the sum of the first length B1, the second length Da, and the third length Dbin the extending direction E102. In some embodiments, the ratio of the length L1of the first spacer102to the width W1of the first spacer102is greater than or equal to 3 (length L1/width W1≥3), or greater than or equal to 3.5, 4, or 4.5, but it is not limited thereto. In some embodiments, the ratio of the length L1of the first spacer102to the first length B1of the first portion102ais between 3 and 8 (3≤length L1/first length B1≤8), or between 4 and 7 and 4 (4≤length L1/first length B1≤7). For example, 5 or 6, but it is not limited thereto.

According to the foregoing, in accordance with some embodiments, the first spacer102is designed to have a specific size, which can enhance the buffering effect for shifting or reduce the probability of the layer (e.g., alignment layer, not illustrated) on the second substrate200being scratched by the first spacer102.

As shown inFIG.4, in some embodiments, in the normal direction (e.g., the Z direction) of the first substrate100, the light-shielding layer204overlaps with the first spacer102, and the color filter layer206does not overlap with the first spacer102. In some embodiments, the light-shielding layer204may cover the first spacer102, the second spacer202, the data line DL and/or the scan line SL. The above-mentioned “cover” means that the first spacer102, the second spacer202, the data line DL and/or the scan line SL can be covered by the light-shielding layer204when they are viewed in the normal direction of the first substrate100. However, the first spacer102, the second spacer202, the data line DL and/or the scan line SL may be formed on the same or different substrates as the light-shielding layer204. In some embodiments, in the normal direction of the first substrate100, the first spacer102may overlap with the data line DL and/or the scan line SL. In some embodiments, the position where the first spacer102overlaps with the second spacer202(i.e. the first portion102a) may overlap with an intersecting region of the data line DL and the scan line SL, but it is not limited thereto.

Refer toFIG.5, which is a schematic top-view diagram of the electronic device10in accordance with some embodiments of the present disclosure. Specifically,FIG.5is similar toFIG.4, but the features are different. It should be understood that, in order to clearly describe the characteristics of specific elements, some elements of the electronic device10are omitted in the drawing, and the dashed line and solid line illustrated in the drawing may not represent the up-down relationship of the elements. As shown inFIG.5, in some embodiments, part of the second spacer202does not overlap with the first spacer102. In detail, the second spacer202may include a fourth portion202a, a fifth portion202b, and a sixth portion202c. The fourth portion202aoverlaps with the first spacer102in the normal direction (e.g., the Z direction) of the first substrate100, the fifth portion202band the sixth portion202care adjacent to the fourth portion202a, and the fourth portion202aconnects between the fifth portion202band the sixth portion202c. In some embodiments, the fourth portion202ahas a fourth length B2, the fifth portion202bhas a fifth length Dc, and the sixth portion202chas a sixth length Dd. In addition, the fifth length Dcis greater than or equal to the fourth length B2(fifth length Dc≥fourth length B2), and the sixth length Ddis greater than or equal to the fourth length B2(sixth length Dd≥fourth length B2).

It should be noted that, the fifth portion202band the sixth portion202cof the second spacer202can serve as a shifting buffer region for the first spacer102. The fifth portion202band the sixth portion202ccan reduce the probability of the first spacer102shifting to an area outside the second spacer202when an external force is applied to the panel, or reduce the probability of the layer (e.g., alignment layer, not illustrated) disposed on the second spacer202being scratched by the first spacer102.

In some embodiments, the fifth portion202bhas a fifth length Dcgreater than or equal to 10 micrometers (fifth length Dc≥10 micrometers), or greater than or equal to 12 micrometers, 14 micrometers, 16 micrometers or 18 micrometers, but it is not limited thereto. In some embodiments, a sixth length Ddof the sixth portion202cis greater than or equal to 10 micrometers (sixth length Dd≥10 micrometers), or greater than or equal to 11 micrometers, 13 micrometers, 15 micrometers, or 17 micrometers, but it is not limited thereto.

In some embodiments, the ratio of the fifth length Dcto the fourth length B2is greater than or equal to 1.4 (fifth length Dc/fourth length B2≥1.4), or greater than or equal to 1.5, 1.6, 1.7 or 1.8, but it is not limited thereto. In some embodiments, the ratio of the sixth length Ddto the fourth length B2is greater than or equal to 1.4 (sixth length Dd/fourth length B2≥1.4), or greater than or equal to 1.5, 1.6, 1.7 or 1.8, but it is not limited thereto.

In some embodiments, the ratio of the fifth length Dcof the fifth portion202bto the sixth length Ddof the sixth portion202cis between 0.6 and 1.7 (0.6 ≤fifth length Dc/sixth length Dd≤1.7) or between 0.8 and 1.5 (0.8≤fifth length Dc/sixth length Dd≤1.5), for example, 0.9, 1, 1.1, 1.2, 1.3 or 1.4, but it is not limited thereto. It should be noted that, the aforementioned fourth length B2, fifth length Dc, and sixth length Ddare measured along a reference line on the same image (e.g., OM image). The reference line may be a line extending in any direction paralleled to the surface of the first substrate100(for example, the XY plane in the drawing) as long as the fourth length B2, fifth length Dcand sixth length Ddmeet the above-mentioned relationships that the fifth length Dcis greater than or equal to the fourth length B2, and the sixth length Ddis greater than or equal to the fourth length B2. In accordance with some embodiments, the extending direction E202of the second spacer202can be used as the reference line. In other words, the aforementioned fourth length B2, fifth length Dc, and sixth length Ddcan be measured along the extending direction E202of the second spacer202, but it is not limited thereto.

In some embodiments, the second spacer202has a length L2in the extending direction E202, and the length L2is the sum of the fourth length B2, the fifth length Dc, and the sixth length Ddin the extending direction E202. In some embodiments, the ratio of the length L2of the second spacer202to a width W2of the second spacer202is greater than or equal to 3 (length L2/width W2≥3), or greater than or equal to 3.5, 4, or 4.5, but it is not limited thereto. In some embodiments, the ratio of the length L2of the second spacer202to the fourth length B2of the fourth portion202ais between 3 and 8 (3<length L2/fourth length B2<8) or between 4 and 7 (4<length L2/fourth length B2<7), for example, 5 or 6, but it is not limited thereto.

According to the foregoing, in accordance with some embodiments, the second spacer202is designed to have a specific size, which can enhance the buffering effect for shifting or reduce the probability of the layer (e.g., alignment layer, not illustrated) disposed on the first substrate100being scratched by the second spacer202.

As shown inFIG.5, in some embodiments, the extending direction E202of the second spacer202is different from the extending direction E102of the first spacer102. In some embodiments, the included angle between the extending direction E102of the first spacer102and the extending direction E202of the second spacer202may be between about 45 degrees and about 90 degrees (45 degrees≤included angle≤90 degrees), but it is not limited thereto. In some embodiments, the included angle between the extending direction E102of the first spacer102and the extending direction E202of the second spacer202may be between about 60 degrees and about 90 degrees (60 degrees≤included angle≤90 degrees), but it is not limited thereto. In some embodiments, the included angle between the extending direction E102of the first spacer102and the extending direction E202of the second spacer202may be between about 80 degrees and about 90 degrees (80 degrees≤included angle≤90 degrees). In some embodiments, the extending direction E202of the second spacer202is substantially the same as an extending direction E2of the scan line SL. In some embodiments, in the normal direction of the first substrate100, the second spacer202may overlap with the data line DL and/or the scan line SL, and the above-mentioned “overlap with” means that the two at least partially overlap. In this way, the length of the second spacer202can be appropriately extended to increase the buffer space, and the second spacer202does not significantly occupy the aperture area of the pixel unit. In some embodiments, the position where the second spacer202overlaps with the first spacer102(i.e. the fourth portion202a) may overlap with an intersecting region of the data line DL and the scan line SL, but it is not limited thereto.

Refer toFIG.6, which is a schematic cross-sectional diagram of the electronic device10in accordance with some embodiments of the present disclosure. The cross-sectional structure shown inFIG.6may correspond to the section line A-A′ inFIG.4. It should be understood that, some elements of the electronic device10are omitted in the drawing for clarity. As shown inFIG.6, the first spacer102and the second spacer202are disposed between the first substrate100and the second substrate200, the first spacer102and the second spacer202interlace with each other. In some embodiments, the planarization layer110is disposed between the first spacer102and the first substrate100. In some embodiments, a planarization layer210is disposed between the second spacer202and the second substrate200. In some embodiments, the planarization layer110may provide a planar surface for disposing the first spacer102, or improving the structural flatness of the first spacer102. In some embodiments, the planarization layer210may provide a planar surface for disposing the second spacer202, or improving the structural flatness of the second spacer202. In some embodiments, the planarization layer210may be disposed between the second spacer202and the light-shielding layer204. It should be noted that, if the structure of the first spacer102is not flat (or planar), the opposite spacer (for example, the second spacer202) may be easily shifted (or displaced) due to an external force, affecting other layers (for example, a first alignment layer AL1, but it is not limited thereto) disposed on the first substrate100. It should be noted that, if the structure of the second spacer202is not flat, the opposite spacer (for example, the first spacer102) may be easily displaced due to an external force, affecting other layers disposed on the second substrate200(for example, a second alignment layer AL2, but it is not limited thereto). Furthermore, the material of the planarization layer210may be similar to the material of the planarization layer110, and will not be repeated herein. Furthermore, the material of the planarization layer210may be the same as or different from the material of the planarization layer110. In some other embodiments (not illustrated), the planarization layer110or the planarization layer210can be removed.

In some embodiments, the first alignment layer AL1may be disposed on the first spacer102and a portion of the planarization layer110, and the second alignment layer AL2may be disposed on the second spacer202and a portion of the planarization layer210. In some embodiments, a dielectric layer (such as a liquid-crystal layer or other dielectric layers, not illustrated) may be disposed between the first alignment layer AL1and the second alignment layer AL2. In some embodiments (not illustrated), the thickness of the first alignment layer AL1corresponding to (or disposing on) the first spacer102is smaller than the thickness of the first alignment layer AL1corresponding to (or disposing on) the planarization layer110. In some embodiments (not illustrated), the thickness of the second alignment layer AL2corresponding to (or disposing on) the second spacer202is smaller than the thickness of the second alignment layer AL2corresponding to (or disposing on) the planarization layer210. In some embodiments, in the cross section, the first spacer102and/or the second spacer202may have curved edges, but it is not limited thereto.

Refer toFIG.7andFIG.8, which are schematic top-view diagrams of the first spacer102and the second spacer202of the electronic device in accordance with some embodiments of the present disclosure. As shown inFIG.7, in some embodiments, the first spacer102may have an elongated structure, and the second spacer202may have a circle shape structure (such as cylindrical structure), but it is not limited thereto. As shown inFIG.8, in some embodiments, the first spacer102may have a circle shape structure (such as cylindrical structure), and the second spacer202may have an elongated structure, but it is not limited thereto. In the embodiments shown inFIG.7andFIG.8, the first spacer102has part that does not overlap with the second spacer202, and the second spacer202also has part that does not overlap with the first spacer102. As described above, these parts (or portions) can serve as shifting buffer regions for the first spacer102and/or the second spacer202.

It should be understood that, in accordance with the embodiments of the present disclosure, the shapes of the first spacer102and the second spacer202are not limited to those depicted inFIG.7andFIG.8. In accordance with some embodiments, the first spacer102and the second spacer202can have any other suitable shapes (such as rectangular, polygonal, or arc-shaped, but it is not limited thereto) according to needs, as long as the shape of the first spacer102can meet the aforementioned relationships that the second length Dais greater than or equal to the first length B1, and the third length Dbis greater than or equal to the first length B1or the shape of the second spacer202can meet the aforementioned relationships that the fifth length Dcis greater than or equal to the fourth length B2, and the sixth length Ddis greater than or equal to the fourth length B2.

Refer toFIG.9, which is a schematic top-view diagram of the first spacer102, the second spacer202, the data line DL, and the first through holes V1of the electronic device in accordance with some embodiments of the present disclosure. As shown inFIG.9, in some embodiments, the included angle between the extending direction E102of the first spacer102and the extending direction E202of the second spacer202is between 45 degrees and 90 degrees (45 degrees≤included angle θ≤90 degrees), or between 60 degrees to 90 degrees (60 degrees≤included angle θ≤90 degrees), or between 80 degrees to 90 degrees (80 degrees≤included angle θ≤90 degrees), but it is not limited thereto. In some embodiments, the included angle θ1between the extending direction E102of the first spacer102and the extending direction E1of the data line DL is between 0 degree and 45 degrees (0 degree≤included angle θ1≤45 degrees), or between 10 degrees and 45 degrees (10 degrees≤included angle θ1≤45 degrees), or between 10 degrees and 30 degrees (10 degrees≤included angle θ1≤30 degrees), but it is not limited thereto. In some embodiments, the overlapping area of the first spacer102and the second spacer202is substantially between two adjacent first through holes V1, and the overlapping area of the first spacer102and second spacer202is substantially located on a connecting line of two adjacent first through holes V1, and the connecting line may be substantially parallel to the X direction, but it is not limited thereto.

In accordance with the embodiments of the present disclosure, an optical microscopy (OM), a scanning electron microscope (SEM), a film thickness profiler (a-step), an ellipsometer or another suitable methods may be used to measure the width, length, thickness of each element or the distance between elements. Specifically, in some embodiments, a scanning electron microscope can be used to obtain any cross-sectional image including the elements to be measured, and the width, length, thickness or distance between the elements in the image can be measured.

Although some embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. The features of the various embodiments can be used in any combination as long as they do not depart from the spirit and scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods or steps. In addition, each claim constitutes an individual embodiment, and the claimed scope of the present disclosure includes the combinations of the claims and embodiments. The scope of protection of present disclosure is subject to the definition of the scope of the appended claims. Any embodiment or claim of the present disclosure does not need to meet all the purposes, advantages, and features disclosed in the present disclosure.