Patent ID: 12204155

The use of the same or similar reference numerals in different figures indicates similar, related, or identical items.

The use of cross-hatching or shading in the accompanying figures is generally provided to clarify the boundaries between adjacent elements and also to facilitate legibility of the figures. Accordingly, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, element proportions, element dimensions, commonalities of similarly illustrated elements, or any other characteristic, attribute, or property for any element illustrated in the accompanying figures.

Additionally, it should be understood that the proportions and dimensions (either relative or absolute) of the various features and elements (and collections and groupings thereof) and the boundaries, separations, and positional relationships presented therebetween, are provided in the accompanying figures merely to facilitate an understanding of the various embodiments described herein and, accordingly, may not necessarily be presented or illustrated to scale, and are not intended to indicate any preference or requirement for an illustrated embodiment to the exclusion of embodiments described with reference thereto.

DETAILED DESCRIPTION

Embodiments described herein are directed to systems and methods for defining photonic integrated circuits. A photonic integrated circuit, as described herein, can be architected for any suitable computational, imaging, information transfer, or other purpose. As known to a person of skill in the art, a photonic integrated circuit can include a number of elements, including, but not limited to, lasers, photodiodes, interferometers, waveguides, lenses, polarization filters, polarizers, couplers, and so on.

In many cases, a photonic circuit element may be manufactured using a process specific to that photonic circuit element. For example, manufacturing processes necessary to define a light source (such as a laser) are necessarily different from manufacturing processes necessary to define a silicon or silicon nitride waveguide. Continuing the example, metallic and/or conductive layers of the laser may be incompatible with temperatures necessary to anneal the silicon waveguide. Manufacturing temperature is merely one example incompatibility; it may be appreciated that many different photonic circuit element manufacturing processes may include one or more operations that are incompatible with one another.

To account for manufacturing incompatibilities, among other reasons, it is often the case that a photonic integrated circuit includes components that are separately manufactured on different chips and, thereafter, assembled together. In many cases, such manufacturing/assembly techniques are referred to as “flip-chip” designs in which one chip is positioned over as second chip and coupled thereto to define a single circuit.

However, conventional flip-chip techniques require mechanical relative alignment between chips, which may be particularly challenging for small-scale chips, such as those that may include a limited number of photonic integrated circuit elements. As a result, conventional flip-chip manufacturing requires high alignment tolerance. For photonic integrated circuits, high alignment tolerances may not be suitable for reliably, repeatably, and precisely optically coupling together two or more singulated chips, each including one or more phonic integrated circuits.

For example, among other issues, flip-chip bonding of two chips can introduce lateral and/or vertical misalignment of certain circuit elements. As one non-limiting example, standoffs or posts that attach and/or offset flip-chip bonded chips set Z-axis (e.g., vertical) alignment but do not assist in X-Y (e.g., lateral) alignment. Further, the vertical alignment guiding as provided by standoffs or posts of conventional methods may only provide vertical alignment accuracy or precision within manufacturing tolerances of the standoffs or posts.

For photonic circuits, relative misalignment of chips may be particularly problematic. For example, in conventional flip-chip implementations in which a first chip includes a first waveguide and a second chip includes a second waveguide, relative three dimensional alignment between the first and second waveguides cannot be ensured. In particular, lateral misalignment may lead to loss of light transmitted from the first waveguide to the second waveguide, and thus to power loss for the overall photonic integrated circuit. The same is true, although often to a lesser extent, for vertical misalignment between chips and their component waveguides.

To account for these and other drawbacks of conventional flip-chip manufacturing techniques, embodiments described herein reference systems and methods for leveraging photolithography (and similar high-precision manufacturing techniques) to define complementary geometry on different chips to be coupled via a flip-chip methodology. The complementary geometry can be used as an alignment guide for two or three dimensions of relative alignment. As a result of systems and methods described herein, two or more chips including complementary geometry can be relatively aligned with the same accuracy and precision as the photolithography process that was leveraged to define the complementary geometry on each chip. As used herein the phrase “complementary geometry” refers generally to tongue-in-groove mating structures; one structure typically extends proud of a surface and another structure typically defines a cavity extending into a different surface. Complementary structures can have the same cross-sectional profile or different cross-sectional profiles.

For example, a first substrate can be used as a base substrate to form a light source that provides optical power to a photonic integrated circuit, collectively defining a first chip. The photonic integrated circuit and/or the light source can be optically coupled to other photonic circuit elements disposed on the base substrate. For example, the light source may be optically coupled to a waveguide that defines an input/output facet.

A second substrate can be used as a base substrate to form a waveguide configured to direct light emitted from the light source (e.g., via the first waveguide) to another circuit element of the same photonic integrated circuit, collectively defining a second chip. As noted above, process steps required to manufacture a light source may be thermally incompatible with process steps required to manufacture an annealed waveguide on the second substrate. As a result, the light source, the first waveguide, and the first substrate (the first chip) may be manufactured separately from the second waveguide and the second substrate (the second chip). In this example embodiment, during manufacturing of the light source, one or more surface features can be formed on, formed into, and/or defined from the first substrate during a photolithography process also used to define one or more features of the light source itself. As a result, a single photolithographic process defines positioning of both the light source and each individual surface feature.

Similarly, the waveguide of this example can be manufactured on the second substrate. A photolithography process leveraged to define geometry of the waveguide can be also used to define two or more surface features on the second substrate that complement the surface features of the first substrate. In a more general phrasing, a single manufacturing step can be used to define multiple functional elements on a chip, including channels or protrusion that may, in later manufacturing steps (following singulation, in some examples) be used for alignment guiding purposes as described herein. These operations may be selected in certain embodiments so that size and shape of different structures formed onto and/or into different substrates can be defined with the precision of a single photolithography step.

As a result of this construction, the surface features of each chip can be used as interlocking/intercoupling/mating alignment guides that, when engaged, provide precise threedimensional alignment of the light source and an input facet of the optical waveguide.

Surface features as described herein can be formed in a number of suitable ways. For example, in some embodiments, an anisotropic etch process may be used to define a linear channel and/or a linear protrusion, each having a cross-sectional profile having a rectangular shape. In other cases, a directional etch process may be used to define a channel with a triangular cross-sectional profile and, correspondingly, a protrusion having a triangular cross-sectional profile each extending for a distance in a linear manner. In other cases, a protrusion may have a rectangular cross-section, whereas a channel corresponding to the protrusion may have a triangular profile; each can extend along a linear path. In other cases, a linear path may not be required; curved paths may be possible in some examples. In these examples, protruding surface features can be configured to interlock with a corresponding, and complementary channel surface feature. In another phrasing, an embossed surface feature can be configured to engage with a debossed surface feature.

In many embodiments, multiple surface features are formed onto (or into, or disposed on, or formed from) a single chip so as to constrain motion and/or position of that chip in multiple dimensions when the chip is positioned relative to another chip having complementary geometry. For example, a first channel defined into a substrate surface can be oriented along a first axis and a second channel defined into the same substrate surface can be oriented along a second axis perpendicular to the first axis. In other cases, two or more channels can overlap, so as to define a cross-shape, an L-shape, or an X-shape. Many configurations are possible.

In some embodiments, debossed surface features may have a different cross-sectional profile geometry than complementary embossed surface features. For example, a channel with a triangular cross-sectional profile (e.g., formed with a directional etch process) may be wider than a complementary protrusion that also has a triangular cross-sectional profile. In other cases, a protrusion may have a rectangular cross-sectional profile, and may be configured to align within a channel having a triangular cross-sectional profile.

In some cases, multiple channels can be aligned in parallel, with different depth, length, or cross-sectional profile geometry. Rectilinear channels may not be required; channels can bow, arch, or otherwise curve or have multiple differently-oriented discrete portions. In some examples, channels of different size can be used to progressively align two chips together. In other cases, a channel may not have a single width and may instead be constructed with a tapered width that can be used to guide alignment of a second substrate toward a narrow end of the channel.

These foregoing and other embodiments are discussed below with reference toFIGS.1A-8. However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanation only and should not be construed as limiting.

FIGS.1A-1Bdepict a simplified cross-section diagram of an operation of aligning two photonic circuit chips by leveraging complementary geometry, such as described herein.

In particular,FIG.1Adepicts a diagram of a portion of a photonic integrated circuit100that is defined at least in part by two chips that can be assembled and intercoupled by leveraging a flip-chip technique, as described herein. In particular, a first chip102can serve as a base substrate over which a second chip104can be positioned.

The first chip102and the second chip104can each include different photonic circuit elements that may require precise multi-axis alignment. More specifically, the photonic circuit elements of each chip may require precise alignment along an X axis (e.g., from right to left ofFIG.1A), along a Y axis (e.g., into or out ofFIG.1A), and along a Z axis (e.g., from top to bottom ofFIG.1A). In this example, the X and Y axes can define a surface plane of the first chip102and the Z axis can extend through a thickness of the first chip102. Misalignment of the two photonic circuit elements may result in substantial optical power loss and/or low coupling efficiency which, in turn, can affect and degrade performance of the photonic integrated circuit100.

As with other embodiments described herein, the first chip102and the second chip104each are formed with complementary geometry that, when mutually engaged, precisely aligns the first chip102with the second chip104.

For example, in some embodiments, the second chip104can include a light source intended to be optically coupled to a waveguide defined on or through the first chip102. This is merely one example; it may be appreciated that either chip can include one or more passive or active optical elements or photonic elements or semiconductor circuit elements that, in turn may be configured to align with a corresponding optical coupling or conductive coupling of the other chip. For simplicity of description, the embodiments that follow reference intercoupled chips that include a single photonic circuit element coupling to a single photonic circuit element, but it may be appreciated that this is merely one example, and that other architectures and implementations can leverage embodiments described herein.

In this example, the second chip104includes a base substrate106over which at least a portion of a photonic integrated circuit element108may be formed (e.g., a light source). In some cases, the base substrate106is formed form silicon (e.g., bulk silicon) although this may not be required of all embodiments.

The second chip104can also define at least two protrusions, identified as the protrusions110and112. In this example, the protrusions110and112are show as extending from a surface of the photonic integrated element108, but this may not be required of all embodiments. For example, in some cases, the protrusions110,112can be formed from a surface of the base substrate106. In further cases, one or more protrusions and/or one or more channels may be formed on, disposed on, or otherwise formed from the same base substrate of the same chip. More specifically, a single chip can include both protrusions and channels configured to mate with corresponding protrusions and channels of another chip.

The protrusions110,112are shown with identical cross-sectional profiles, but this may not be required of all embodiments. For example, in some cases, the protrusion110may be shorter along the Z-axis than the protrusion112, the protrusion110may be deeper along the Z-axis than the protrusion112. In other cases, the protrusion110may have a circular cross section/profile, whereas the protrusion112may have a triangular or otherwise polygonal cross section. A person of skill in the art may readily appreciate that any suitable arrangement and geometry of the protrusions110,112may be used.

The first chip102, similar to the second chip104, can include a base substrate114. The base substrate114may be formed from silicon, although this is not required of all embodiments.

The base substrate114can have formed (or disposed, placed, and so on) thereon at least a portion of a photonic circuit element116(e.g., a waveguide). As noted above, the photonic circuit element116may be configured to precisely align with the photonic circuit element108when the second chip104is positioned over and aligned with the first chip102. More specifically, an optical axis (light emitting axis, input facet, output facet, and so on) of the photonic circuit element116may be configured to precisely align with the photonic circuit element108. In one example construction, the photonic circuit element116may be a first waveguide and the second photonic circuit element108may be a second waveguide.

To effect such alignment, the base substrate114includes at least two channels, identified as the channels118and120. In this example, the channels118and120are show as extending from a surface of the base substrate114, but this may not be required of all embodiments. For example, in some cases, the protrusions110,112can be formed from a surface of the photonic integrated circuit element116.

As may be appreciated by a person of skill in the art, the channels118,120and the protrusions110,112can be formed with complementary geometry such that when the second chip104is positioned over the first chip102, and the second chip104is advanced in the XY plane, the protrusions110,112can become engaged with the channels118,120and the triangular geometry of the channels118,120can guide the protrusion110,112to a specific Z position, thereby precisely aligning the photonic circuit element116and the photonic circuit element108. More broadly, the dual alignment channel geometry illustrated inFIGS.1A and1Bprovides for alignment along all three primary axes, namely the X-axis, the Y-axis and the Z-axis.

These foregoing embodiments depicted inFIGS.1A-1Band the various alternatives thereof and variations thereto are presented, generally, for purposes of explanation, and to facilitate an understanding of various configurations and constructions of a method of aligning two chips to form a photonic integrated circuit, such as described herein. However, it will be apparent to one skilled in the art that some of the specific details presented herein may not be required in order to practice a particular described embodiment, or an equivalent thereof.

Thus, it is understood that the foregoing and following descriptions of specific embodiments are presented for the limited purposes of illustration and description. These descriptions are not targeted to be exhaustive or to limit the disclosure to the precise forms recited herein. To the contrary, it will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.

For example,FIGS.2A-2Ddepict example views of a chip as described herein that can be formed with a set of surface features that may be leveraged with complementary geometry of corresponding surface features of a second chip to precisely align with that chip, such as described herein.

For example,FIG.2Adepicts a view of a chip200that includes a base layer202onto which one or more features can be formed that, in turn, can define at least a portion of a photonic integrated circuit, such as described herein. For example, the chip can include an elevated portion204that supports a waveguide206that can define an input/output edge facet configured to optically and/or mechanically couple to an input/output edge facet of another waveguide formed/defined on a separate substrate.

Adjacent to or otherwise separated from the elevated portion204, can be defined two or more surface features, identified as the surface feature208and the surface feature210. The surface feature208and/or the surface feature210can be formed into or out of an upper surface of the base layer202. More generally, the surface feature208and/or the surface feature210may be embossed features or debossed features; the surface feature208and/or the surface feature210may define one or more channels or may define one or more protrusions.

The surface feature208and/or the surface feature210can exhibit any suitable cross-sectional profile or geometry. In the illustrated example, the surface feature208and/or the surface feature210each have a triangular cross-sectional profile that may be formed via photolithographically-masked directional etch or anisotropic etch processes. This is merely one example cross-sectional profile; in other examples, a surface feature as described herein can be formed to have any suitable shape.

In the illustrated example, the surface feature208and the surface feature210have a generally rectilinear shape, and are arranged in parallel to one another. This is not required of all embodiments, for example inFIG.2B, the surface feature210may be oriented at an angle perpendicular to the surface feature210.

In the examples illustrated inFIGS.2A-2B, the surface feature208and the surface feature210are shown as the only two surface features defined onto the chip200; this is not required of all embodiments. For example, as shown inFIG.2C, more than two surface features can be defined. More particularly, in this example, a third surface feature212is defined between the surface feature208and the surface feature210.

In the examples illustrated inFIGS.2A-2C, each surface feature—whether embossed or debossed from a surface or layer of the chip200is shown as having the same size and cross-sectional profile. This is not required of all embodiments. For example, as shown inFIG.2D, the surface feature208and the surface feature210may have different sizes and/or may be arranged at an oblique angle relative to one another. In this example, the surface feature210is depicted has larger than the surface feature208, which in turn is oriented at a non-parallel, non-perpendicular, oblique angle relative to the surface feature210.

Each of the example embodiments depicted inFIGS.2A-2Dillustrate example possible geometries of surface features that may be formed into a chip, such as the first chip102or the second chip104ofFIGS.1A-1B. More generally, for these embodiments show inFIGS.2A-2D, it may be appreciated that a similar pattern to that which is shown can be formed into a second chip or chip in order that the chip200can be coupled to and precisely aligned with the other chip.

These foregoing embodiments depicted inFIGS.2A-2Dand the various alternatives thereof and variations thereto are presented, generally, for purposes of explanation, and to facilitate an understanding of various configurations and constructions of a method of defining and/or positioning surface features onto a chip for aligning that chip with another chip having complementary geometry to form a photonic integrated circuit, such as described herein. However, it will be apparent to one skilled in the art that some of the specific details presented herein may not be required in order to practice a particular described embodiment, or an equivalent thereof.

Thus, it is understood that the foregoing and following descriptions of specific embodiments are presented for the limited purposes of illustration and description. These descriptions are not targeted to be exhaustive or to limit the disclosure to the precise forms recited herein. To the contrary, it will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.

For example, in many embodiments, a surface feature extending proud of a surface configured to mate with and/or interface with a surface feature defining a channel may have different cross-sectional profiles. For example,FIG.3depicts a simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein.

In this embodiment, a photonic integrated circuit300can be formed by mating a first chip302with a second chip304. The first chip includes a first circuit element306(e.g., waveguide, light source, splitter, delay line, Bragg reflector, other reflectors, mode field converters, and so on) may be aligned with a second circuit element308of the second chip304when surface features of the first and second chips are engaged.

More particularly, in the illustrated embodiment, the first chip302includes a surface feature310and a surface feature312, each having a rectangular cross-section. Correspondingly, the second chip304includes a surface feature314and a surface feature316, each having a triangular cross-section. In this example, the surface feature310may be configured to mate with and/or engage with the surface feature314and the surface feature312may be configured to mate with and/or engage with the surface feature316.

In other cases, protrusions can have a triangular cross-sectional profile and channels, as described herein, can have a different cross-sectional profile. For example,FIG.4depicts another simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein.

In this embodiment, a photonic integrated circuit400can be formed by mating a first chip402with a second chip404. The first chip includes a first circuit element406that may be aligned with a second circuit element408of the second chip404when surface features of the first and second chips are engaged.

More particularly, in the illustrated embodiment, the first chip402includes a surface feature410and a surface feature412, each having a triangular cross-section. Correspondingly, the second chip404includes a surface feature414and a surface feature416, each having a rectangular cross-section. In this example, the surface feature410may be configured to mate with and/or engage with the surface feature414and the surface feature412may be configured to mate with and/or engage with the surface feature416.

In yet further examples, mating of surface features as described herein can serve a functional purpose, in addition to a mechanical and/or alignment purpose. For example,FIG.5depicts a simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein.

In this embodiment, a photonic integrated circuit500can be formed by mating and conductively coupling a first chip502with a second chip504. More particularly, in the illustrated embodiment, the first chip502includes a surface feature506which may be a solder ball or other conductive surface. The first chip may also include a surface feature508, which may also be a solder ball or other conductive surface. Each of the surface features506,508can have a circular or curved cross-section, but this is not required of all embodiments.

As with other embodiments described herein, the second chip504includes a surface feature512and a surface feature514, each having a triangular cross-section. In this example, the surface feature508may be configured to mate with and/or engage with the surface feature512and the surface feature506may be configured to mate with and/or engage with the surface feature514. In this embodiment, the conductive surface features of each chip (which can extend into the surface features512,514) can form a conductive coupling between the chips, electrically coupling semiconductor circuitry defined thereon or therein. In addition, as with other embodiments described herein, the surface features may provide for precise alignment of photonic integrated circuit elements, such as an element516of the first chip and an element518of the second chip.

These foregoing embodiments depicted inFIGS.2A-5and the various alternatives thereof and variations thereto are presented, generally, for purposes of explanation, and to facilitate an understanding of various configurations and constructions of a method of defining and/or positioning surface features onto a chip for aligning that chip with another chip having complementary geometry to form a photonic integrated circuit, such as described herein. However, it will be apparent to one skilled in the art that some of the specific details presented herein may not be required in order to practice a particular described embodiment, or an equivalent thereof.

Thus, it is understood that the foregoing and following descriptions of specific embodiments are presented for the limited purposes of illustration and description. These descriptions are not targeted to be exhaustive or to limit the disclosure to the precise forms recited herein. To the contrary, it will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.

Accordingly, more generally and broadly, it may be appreciated that photonic circuit elements formed on different chips can be aligned and/or mechanically, optically, and/or electrically coupled to one another.

It may be appreciated that complementary geometry defined in part by photonic circuit element manufacturing operations can be defined in any number of suitable ways. In some examples, different channels and corresponding protrusions can intersect. In some cases, channels and protrusions can be disposed parallel to one another and perpendicular to an optical axis of a photonic component of one phonic integrated circuit defined on a chip. In other cases, a single chip can include at least one channel feature and at least one protruding feature.

In some cases, a channel can have a tapering geometry to encourage particular alignment by sliding a protruding feature into the tapering channel. In this manner, optical components formed onto, into, or otherwise disposed on each respective chip can be aligned so as to share a common optical axis. In other cases, channels may have keyed depth so that optical alignment will only be achieved if particular protrusions are aligned with particular channels.

In yet further examples, an alignment structure as described herein can be used to align both a semiconductor circuit and a photonic circuit, each formed onto and/or defined onto respective chips. For example,FIG.6depicts another simplified cross-section diagram of a pair of photonic circuit chips aligned by leveraging complementary geometry, such as described herein. In this example, a photonic integrated circuit600includes a first chip602disposed over a second chip604. The first chip602and the second chip604are aligned in part by complementary geometry, as described herein. More specifically, a photonic circuit element606aof the first chip602can be aligned with a second photonic circuit element606bof the second chip604.

As with other embodiments described herein, the alignment can be effected by mating and/or engagement of surface features of the first chip602and the second chip604. In particular, the first chip602can include a protrusion608that mates with a channel610of the second chip604. In addition, the first chip602can include a second protrusion614that mates with a channel612of the second chip604.

In addition to optical coupling between the photonic circuit element606aand the photonic circuit element606b, the first chip602and the second chip604can be conductively coupled in one or more suitable locations to conductively intercouple silicon circuitry, either digital or analog, of the respective chips. For example, solder balls616can conductively couple conductive pads or traces of the first chip602with a circuit or circuit element618of the second chip604. More specifically the solder balls616can facilitate one or more electrical connections between the first chip602and the second chip604; in some cases, the solder balls may be reflowed or otherwise melted in a manufacturing step in order to conductively and mechanically couple the first and second chips to one another.

It may be appreciated, more generally and broadly, that other constructions of a multi-chip architecture as described herein can emit light and/or receive light in any suitable position or location; in some cases, the circuit element618can be configured to emit light or receive light, for example.

These foregoing embodiments depicted inFIGS.2A-6and the various alternatives thereof and variations thereto are presented, generally, for purposes of explanation, and to facilitate an understanding of various configurations and constructions of a method of defining and/or positioning surface features onto a chip for aligning that chip with another chip having complementary geometry to form a photonic integrated circuit, such as described herein. However, it will be apparent to one skilled in the art that some of the specific details presented herein may not be required in order to practice a particular described embodiment, or an equivalent thereof.

Thus, it is understood that the foregoing and following descriptions of specific embodiments are presented for the limited purposes of illustration and description. These descriptions are not targeted to be exhaustive or to limit the disclosure to the precise forms recited herein. To the contrary, it will be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.

For example, generally and broadly, it may be appreciated that any structure as shown in these figures and/or described herein can be formed onto any suitable base substrate. After complementary features are defined on separate chips, at least one of the chips may be flipped and/or otherwise positioned onto a second chip, after which an alignment between the two chips may be guided through three dimensions.

In other cases, a channel as described herein may be both embossed and debossed. For example, regions around a channel can be etched away such that the channel is defined at least in part by sidewalls that extend proud of a substrate surface.

FIG.7Adepicts a first stage of defining a bonded flip-chip structure, as described herein. In particular, a set of separately manufactured chips700may include a first chip702and a second chip704. The first chip, as with other embodiments described herein can include a first surface feature706and a second surface feature708, each of which extend from a surface of the first chip702. In a complementary manner, the second chip704can include a first surface feature710and a second surface feature712that are respectively configured to mate with and engage with the first surface feature706and the second surface feature708. As a result of this set of complementary geometries, the first chip702can be flipped/inverted onto the second chip704so as to effect precise alignment (lateral and vertical) between a first photonic circuit element716defined on the first chip702and a second photonic circuit element718defined on the second chip704, such as shown inFIG.7B. After inversion of the first chip702onto the second chip704, the first chip704may be mechanically guided (e.g., via pick and place machine, manually, by vibration, and so on) such that the respective surface feature of each chip are engaged, such as shown inFIG.7C.

FIG.8is a flowchart depicting example operations of a method of aligning chips, such as described herein. In this embodiment, the method800includes operation802at which a chip is selected. Thereafter, at operation804, two or more alignment features can be formed into or onto the chip. Finally, at operation806, the chip can be aligned with corresponding features of another chip, and the two chips can be affixed to one another in a suitable manner.

As used herein, the phrase “at least one of” preceding a series of items, with the term “and” or “or” to separate any of the items, modifies the list as a whole, rather than each member of the list. The phrase “at least one of” does not require selection of at least one of each item listed; rather, the phrase allows a meaning that includes at a minimum one of any of the items, and/or at a minimum one of any combination of the items, and/or at a minimum one of each of the items. By way of example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; any combination of A, B, and C; and/or one or more of each of A, B, and C. Similarly, it may be appreciated that an order of elements presented for a conjunctive or disjunctive list provided herein should not be construed as limiting the disclosure to only that order provided.

One may appreciate that although many embodiments are disclosed above, that the operations and steps presented with respect to methods and techniques described herein are meant as exemplary and accordingly are not exhaustive. One may further appreciate that alternate step order or fewer or additional operations may be required or desired for particular embodiments.

Although the disclosure above is described in terms of various exemplary embodiments and implementations, it should be understood that the various features, aspects and functionality described in one or more of the individual embodiments are not limited in their applicability to the particular embodiment with which they are described, but instead can be applied, alone or in various combinations, to one or more of the some embodiments of the invention, whether or not such embodiments are described and whether or not such features are presented as being a part of a described embodiment. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments but is instead defined by the claims herein presented.