Patent ID: 12249590

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Prepositions, such as “on” and “side” (as in “sidewall”) are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The term “horizontal” is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above, i.e., perpendicular to the surface of a substrate. The terms “first,” “second,” “third,” and “fourth” may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

There are many packaging technologies to house the semiconductors such as the 2D fan-out (chip-first) IC integration, 2D flip chip IC integration, PoP (package-on-package), SiP (system-in-package) or heterogeneous integration, 2D fan-out (chip-last) IC integration, 2.1D flip chip IC integration, 2.1D flip chip IC integration with bridges, 2.1D fan-out IC integration with bridges, 2.3D fan-out (chip-first) IC integration, 2.3D flip chip IC integration, 2.3D fan-out (chip-last) IC integration, 2.5D (solder bump) IC integration, 2.5D (μbump) IC integration, μthump 3D IC integration, μbump chiplets 3D IC integration, bumpless 3D IC integration, bumpless chiplets 3D IC integration, SoIC and/or any other packaging technologies. It should be understood that various embodiments disclosed herein, although described and illustrated in a context of a specific semiconductor packaging technology, are not intended to limit the present disclosure only to that packaging technology. One skilled in the art would understand those embodiments may be applied in other semiconductor technologies in accordance with principles, concepts, motivations, and/or insights provided by the present disclosure.

System on integrated chip (SoIC) is a recent development in advanced packaging technologies. SoIC technology integrates both homogeneous and heterogeneous chiplets into a single System-on-Chip (SoC)-like chip with a smaller footprint and thinner profile, which can be holistically integrated into advanced WLSI (aka CoWoS® service and InFO). From external appearance, the newly integrated chip is just like a general SoC chip yet embedded with desired and heterogeneously integrated functionalities. SoIC realizes 3D chiplets integration with additional advantages in performance, power and form factor. Among many other features, the SoIC features ultra-high-density-vertical stacking for high performance, low power, and reduced RLC (resistance-inductance-capacitance). SoIC integrates active and passive chips into a new integrated-SoC system to achieve better form factor and performance. US Patent Publication #20200168527, entitled “SoIC chip architecture,” provides some descriptions of some example SoIC structures. US Patent Publication #20200168527 is incorporated by reference in its entirety. Another example of SoICTM can be found at https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm, which is also incorporated by reference in the present disclosure in its entirety.

Various embodiments relate to multi-chip devices having stacked chips disposed on a base structure. As used herein, chips and dies are used interchangeably and refer to pieces of a semiconductor wafer, to which a semiconductor manufacturing process has been performed, formed by separating the semiconductor wafer into individual dies. A chip or die can include a processed semiconductor circuit having a same hardware layout or different hardware layouts, same functions or different functions. In general, a chip or dies has a substrate, a plurality of metal lines, a plurality of dielectric layers interposed between the metal lines, a plurality of vias electrically connecting the metal lines, and active and/or passive devices. The dies can be assembled together to be a multi-chip device or a die group. As used herein, a chip or die can also refer to an integrated circuit including a circuit configured to process and/or store data. Examples of a chip, die, or integrated circuit include a field programmable gate array (e.g., FPGA), a processing unit, e.g., a graphics processing unit (GPU) or a central processing unit (CPU), an application specific integrated circuit (ASIC), memory devices (e.g., memory controller, memory), and the like.

In accordance with the present disclosure, a die-group package having an embedded deep trench capacitor (DTC) is provided. In various embodiments, the die-group package includes a carrier substrate disposed on a first die group, a second die group, a base die group having the first die group and the second die group disposed thereon, and any other components (if any). In those embodiments, the first die group and the second die group have a height difference, and a carrier substrate is disposed on the first die group to more or less compensate that height difference. In those embodiments, the DTC is embedded in the carrier substrate and is connected to the first die group through one or more interconnects in the first group. In this way, a form factor of the die-group package is improved because the DTC and carrier substrate occupy a same space rather than two different spaces in the die-group package.

In accordance with the present disclosure, a method for fabricating a die-group package having an embedded DTC is provided. In various embodiments, the method includes etching a DTC space within a carrier substrate, growing a liner in the space, fusion bonding a DTC die in the DTC space, filling one or more gaps within the DTC space, planarizing the DTC space, hybrid bonding the carrier substrate onto a first die group of the die group structure, planarizing the carrier substrate to make a combined height of the first die group and the carrier substrate more or less the same as a second die group of the die-group structure.

Dies and Die Groups in Accordance with the Present Disclosure

In this section, an example individual die structure, an example stacked die structure in a die group, and an example wafer-on-wafer configuration having the example stacked die structure are provided to illustrate some embodiments where the present disclosure may be applied. It should be understood that the examples shown in this section are merely illustrative for understanding how the present disclosure may be applied in those examples. Thus, these examples should not be construed as being intended to limit the present disclosure. One skilled in the art will understand the present disclosure may be applied in other semiconductor packaging technologies wherever appropriate.

An Example Individual Die Structure in Accordance with the Present Disclosure

FIG.1is a structure of a semiconductor device10according to some exemplary embodiments. One or more of such a semiconductor device may be arranged on an individual die in a die group in various embodiments. Referring toFIG.1, the semiconductor device10includes a substrate101, an active region102formed on a surface of the substrate101, a plurality of dielectric layers103, a plurality of metal lines and a plurality of vias105and108formed in the dielectric layers104, and a metal structure106in a top intermetal layer107. In the example ofFIG.1, the semiconductor device10also includes trans-substrate via (TSV) (110), and back side contacts109formed in a backside dielectric layer111on the back side of substrate101. In an embodiment, the semiconductor device10can also include passive devices, such as resistors, capacitors, inductors, and the like (not shown). The substrate101can be a semiconductor substrate or a non-semiconductor substrate. For example, the substrate101may include a bulk silicon substrate. In some embodiments, the substrate101may include an elementary semiconductor, such as silicon or germanium in a crystalline structure, a compound semiconductor, e.g., silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, or combinations thereof. Possible substrate101may also include a semiconductor-on-insulator (SOI) substrate. In an embodiment, the substrate101is a silicon layer of an SOI substrate. The substrate101can include various doped regions depending on design requirements, e.g., n-type wells or p-type wells. The doped regions are doped with p-type dopants, e.g., boron, n-type dopants, e.g., phosphorous or arsenic, or combination thereof. The active region102may include transistors. The dielectric layers103may include interlayer dielectric (ILD) and intermetal dielectric (IMD) layers. The ILD and IMD layers may be low-k dielectric layers which have dielectric constants (k values) smaller than a predetermined value, e.g., about 3.9, smaller than about 3.0, smaller than about 2.5 in some embodiments. In some other embodiments, the dielectric layers103may include non-low-k dielectric materials having dielectric constants equal to or greater than 3.9. The metal lines and vias may include copper, aluminum, nickel, tungsten, or alloys thereof.

An Example Stacked Die Structure in Accordance with the Present Disclosure

FIG.2is a cross-sectional view of a die group20having a plurality of dies stacked on top of each other horizontally according to some embodiments. Referring toFIG.2, the die group20includes a stacked die structure210including a plurality of dies211,212, and213stacked on top of each other in a substantially horizontal arrangement. As shown, in this example, each of the dies211-213in the die group includes a semiconductor device similar to the semiconductor device10described and illustrated in connection withFIG.1. It should be understood although 3 dies are shown to be in the stacked die structure210, this is not intended to be limiting. One skilled in the art will understand that a stacked die structure in accordance with the present disclosure can include a greater or fewer number of dies than those shown inFIG.2.

As can be seen, in this example, the stacked dies in the stacked die structure210are bonded to each other through bonding members214. In some implementations, the bonding members214include hybrid bonding films. However, this is not intended to be limiting. It is understood that the bonding members214, in accordance with the present disclosure, are not limited to hybrid bonding films. For example, it is contemplated that the bonding members214may include micro bumps, solder balls, metal pads, and/or any other suitable bonding structures.

As also can be seen, each of the stacked dies211,212, and213includes a substrate201, an active region202formed on a surface of the substrate201, a plurality of dielectric layers203, a plurality of metal lines and a plurality of vias204formed in the dielectric layers203, and a passivation layer207on a top inter-metal layer206. In an embodiment, a stacked die can also include passive devices, such as resistors, capacitors, inductors, and the like. The substrate201can be a semiconductor substrate or a non-semiconductor substrate. For example, the substrate201may include a bulk silicon substrate. In some embodiments, the substrate201may include an elementary semiconductor, such as silicon or germanium in a crystalline structure, a compound semiconductor, e.g., silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or combinations thereof. Possible substrate201may also include a semiconductor-on-insulator (SOI) substrate. In an embodiment, the substrate201is a silicon layer of an SOI substrate. The substrate201can include various doped regions depending on design requirements, e.g., n-type wells or p-type wells. The doped regions are doped with p-type dopants, e.g., boron, n-type dopants, e.g., phosphorous or arsenic, or combinations thereof. The active region102may include transistors. The dielectric layers203may include interlayer dielectric (ILD) and intermetal dielectric (TMD) layers. The ILD and IMD layers may be low-k dielectric layers which have dielectric constants (k values) smaller than a predetermined value, e.g., about 3.9, smaller than about 3.0, smaller than 2.5 in some embodiments. In some other embodiments, the dielectric layers203may include non-low-k dielectric materials having dielectric constants equal to or greater than 3.9. The metal lines and vias may include copper, aluminum, nickel, tungsten, or alloys thereof.

In this example, the die group20includes through silicon vias (TSVs) or through oxide vias (TOVs)208configured to electrically connect the metal lines in the stacked dies211,212, and213with each other. In an implementation, an individual TSV/TOV208may include copper, aluminum, tungsten, alloys thereof, and/or any other suitable materials. TSV/TOVs208are arranged in this example to facilitate electronic communication between and among stacked dies211,212and213. However, it is understood that in some other semiconductor packaging technologies where the present disclosure applies, TSV/TOVs may not be present and thus the TSV/TOVs208shown in this example shall not be construed as being intended to limit the present disclosure.

In this example, each of the stacked dies211,212, and213also includes a side metal interconnect structure209on a sidewall of the stack dies. The side metal interconnect structure209may include one or more metal wirings extending through an exposed surface of the plurality of dielectric layers203. The side metal interconnect structure209may be formed at the same time as the metal layers and exposed to the side surface of the die group20after the different dies211,212, and213have been bonded together and the side surface is polished by a chemical mechanical polishing (CMP) process.

In some embodiments, the die group20can be formed by bonding a plurality of wafers together using fusion bonding, eutectic bonding, metal-to-metal bonding, hybrid bonding processes, and the like. A fusion bonding includes bonding an oxide layer of a wafer to an oxide layer of another wafer. In an embodiment, the oxide layer can include silicon oxide. In an eutectic bonding process, two eutectic materials are placed together, and are applied with a specific pressure and temperature to melt the eutectic materials. In the metal-to-metal bonding process, two metal pads are placed together, and a pressure and high temperature are provided to the metal pads to bond them together. In the hybrid bonding process, the metal pads of the two wafers are bonded together under high pressure and temperature, and the oxide surfaces of the two wafers are bonded at the same time.

In some embodiments, each wafer may include a plurality of dies, such as semiconductor devices ofFIG.1. The bonded wafers contain a plurality of die groups having a plurality of stacked dies. The bonded wafers are singulated by mechanical sawing, laser cutting, plasma etching, and the like to separate into individual die groups that can be the die group as shown inFIG.2.

An Example Wafer-On-Wafer Configuration

FIG.3Ais a simplified perspective view illustrating a plurality of wafers stacked on top of each other in a three-dimensional (3D) configuration according to some embodiments. Referring toFIG.3A, a first wafer “wafer1” is a base wafer on which a plurality of dies can be formed. A second wafer “wafer2” is an intermediate wafer on which a plurality of dies can be formed, and a third wafer “wafer3” is a top wafer on which a plurality of dies can be formed. The wafers may have through substrate vias and/or through oxide vias and a backside bonding layer (e.g., metallization layer and/or dielectric layer) and are bonded together to form a 3D stacked wafer configuration using any known bonding techniques, e.g., fusion bonding, eutectic bonding, metal bonding, hybrid bonding, and the like. The three wafers are electrically connected to each other through substrate vias, through oxide vias, and/or backside metallization layer and dielectric layer. The wafers each can have different dies. For example, wafer1may include dies of central processing units, graphics processing units, and logic; wafer2may include dies of memory devices and memory controllers; and wafer3may include dies of bus interfaces, input/output ports, and communication and networking devices. In the example shown inFIG.3A, three wafers are used, but it is understood that the number is illustrative only and is chosen for describing the example embodiment and should not be limiting. In some embodiments, a passivation layer is formed on the upper surface of each of the wafers and includes a thickness to provide separation between the substrate and the metallization layer. The passivation layer includes an oxide material.

FIG.3Bis a simplified perspective view illustrating the stacked wafer configuration ofFIG.3Athat has been cut and separated into individual bars according to an exemplary embodiment. For example, the stacked wafers can be cut into individual bars and individual die groups by mechanical sawing, plasma etching, laser cutting, and the like. Referring toFIG.3B, each of the wafers include a substrate, a plurality of dielectric layers including interlayer dielectric layers (ILDs) and intermetal dielectric layers (IMDs), and a plurality of metal lines and a plurality of vias104formed in the dielectric layers. The dies of the stacked wafers are electrically coupled to each other through substrate vias and through oxide vias. In some embodiments, the individual bars are placed on a polishing board, and the surfaces of the bars are polished prior to being diced or singulated into dies.

FIG.3Cis a simplified perspective view of an individual die group30including a plurality of stacked dies according to an exemplary embodiment. Referring toFIG.3C, the die group30includes a first die301a, a second die301b, and a third die301cstacked on top of each other. Each of the first, second, and third dies may include a substrate, an active region including a plurality of active devices (not shown), an interconnect structure303formed on the substrate and configured to electrically connect the active region of each die with each other. The interconnect structure303may include a plurality of dielectric layers303a, metal lines303bformed in the dielectric layers303a, and vias303cconnecting metal lines303bin different layers. In some embodiments, the dielectric layers303ainclude silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and/or combinations thereof. In some embodiments, the dielectric layers303amay include one or more low-k dielectric layers having low k values. In some embodiments, the k values of the low-k dielectric materials may be lower than about 3.0.

In some embodiments, the dies are electrically coupled to each other by through substrate vias (TSVs) and through oxide vias (TOVs)308. In some embodiments, the die group30also includes a bonding layer317including an oxide material, e.g., silicon oxide. In some embodiments, the bonding layer317may include a plurality of bonding films and electrical connectors309having a plurality of solder regions. In some embodiments, the electrical connectors309include copper posts, solder caps, and/or electrically conductive bumps310configured to electrically coupled to other electronic circuits on a printed circuit board or other substrates. In some embodiments, the die group30includes a plurality of semiconductor dies or chips similar to those ofFIG.2. In an embodiment, the stacked dies of the die group30include logic devices, input/output (IO) devices, processing units, e.g., data processing units, graphics processing unit, application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), other applicable types of devices. In some embodiment, the die group30is a system-on-integrated circuits (SoIC) device that includes multiple functions. In the example shown inFIG.3A, three dies are shown, but it is understood that the number is illustrative only and is chosen for describing the example embodiment and should not be limiting. For example, the die group30can include a single die, two dies, or more than three dies. In some embodiments, the die group30may be bonded to a package substrate (e.g., an interposer, a printed circuit board) through flip-chip bonding using the electrical connectors309.

In some embodiments, the dies are bonded to each other by a hybrid bonding process. In an embodiment, the first die301ahas a first bonding surface formed on its upper surface including a first bonding dielectric layer315aand a first conductive contact structure316a. The second die301bhas a second bonding surface formed on a bottom of its substrate, the second bonding surface includes a second bonding dielectric layer315band a conductive contact structure316b. In an embodiment, the first and second conductive contact structures316a,316bmay be electrically coupled to the interconnect structure303. In another embodiment, the first and second conductive contact structures316a,316bmay not be electrically coupled to the interconnect structure303. In an embodiment, the first die301aand the second die301bare directly hybrid bonded together, such that the first and second conductive contact structures316a,316bare bonded together, and the first and second bonding dielectric layers315a,315bare bonded together. In an embodiment, the first and second bonding dielectric layers315a,315beach include silicon oxide, and the first and second conductive contact structures316a,316beach include copper.

In an embodiment, the dies also include a seal ring320configured to stop cracks generated by stress during the bonding processes and/or the singulation. The seal ring320is also configured to prevent water, moisture, and other pollutant from entering the dies. In an embodiment, the seal ring320includes copper configured to suppress electromagnetic noise. In an embodiment, the first die301amay include a bonding dielectric layer330configured to be bonded to a carrier substrate by fusion bonding.

Uneven Stacking of Die Groups

In various embodiments, due to a design choice, a functional requirement, and/or any other consideration, two die groups stacked on a base die group in a die group structure have different heights. The difference of their heights, in some embodiments, may exceed a threshold and cause potential warpage or crack in the base die group.FIGS.4-5are illustrated and described herein to show such an uneven stacking of die groups.

FIG.4is a simplified cross-sectional view of a die group40including a plurality of stacked dies according to an exemplary embodiment. The die group40can be included in a die-group structure in accordance with the present disclosure. Referring toFIG.4, the die group40includes a plurality of dies that are stacked on top of each other. In an exemplary embodiment, the die group40includes dies401a,401b,401c,401d, and401e. In an exemplary embodiment, each die includes a substrate4011, a front-end-of-line (FEOL) structure4012, and a back-end-of-line structure4013. The FEOL structure generally includes a first portion of a fabrication of an integrated circuit, such as forming trench isolation structures, performing implants for forming wells, forming active regions, e.g., source/drain regions, gate structures, and interlayer dielectric layers. The BEOL structure generally includes forming electrically conductive lines, and vias in intermetal dielectric layers to electrically couple electronic circuits formed on the substrate. In some embodiments, the dies401a,401b,401c,401d, and401eare memory dies. The memory dies may include memory devices, such as static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, other suitable devices, or a combination thereof. In some embodiments, the die401ais a memory controller die that is electrically connected to the memory dies401b,401c,401d, and401edisposed thereon. In some embodiments, the die group40may function as a high bandwidth memory (HBM). In the example shown inFIG.4, five dies are shown, but it is understood that the number is illustrative only and is chosen for describing the example embodiment and should not be limiting. For example, the die group40can include fewer or more than five dies in some embodiments.

In some embodiments, the die group40also includes a plurality of conductive features402extending through the dies401ato401eand electrically coupled to a plurality of conductive bonding structures403disposed between the dies401a,401b,401c,401d, and401eto electrically bond them together. The conductive features402are configured as through-substrate vias (TSVs) to electrically connect the dies with each other. In an embodiment, the conductive bonding structures403include tiny solder bumps, such as controlled collapse chip connection (C4) bumps or ball grid array (BGA) bumps and pillars formed on an upper surface of a die using various process steps. In some embodiments, the die group40also includes a bonding structure405formed on a surface of the BEOL structure of the die401aand configured to bond the die group40to a substrate410. The die group40is flipped over and mounted on the substrate410. In some embodiments, the die group40also includes a molding compound layer411that encapsulates the dies401a,401b,401c,401d, and401e. The molding compound layer411includes an epoxy-based resin or other suitable material. In some embodiments, the molding compound layer411fills the air gaps between the dies401a,401b,401c,401d, and401eand surrounds the conductive bonding structures403and405.

FIG.5Ais a simplified cross-sectional view of a package device50according to an embodiment. Referring toFIG.5A, the package device50includes a package substrate500, a first die group501, and a second die group502. As can be seen, inFIG.5A, the first die group501and the second die group502are bonded onto the package substrate500. In an implementation, a bonding process used to bond die groups501and/or502can include through fusion bonding, eutectic bonding, metal-to-metal bonding, hybrid bonding processes, and the like. A fusion bonding includes bonding an oxide layer of a wafer to an oxide layer of another wafer. In an embodiment, the oxide layer can include silicon oxide. In an eutectic bonding process, two eutectic materials are placed together, and are applied with a specific pressure and temperature to melt the eutectic materials. In the metal-to-metal bonding process, two metal pads are placed together; a pressure and high temperature are provided to the metal pads to bond them together. In the hybrid bonding process, the metal pads of the two wafers are bonded together under high pressure and temperature, and the oxide surfaces of the two wafers are bonded at the same time.

In some embodiments, the first die group501includes a plurality of dies stacked with other through hybrid bonding. In those embodiments, the second die group502includes a plurality of dies stacked onto each other through metal-to-metal bonding. In one implementation, the first die group501is the die group30shown and described with reference toFIG.3C. In another implementation, the second die group502is the die group40shown and described with reference toFIG.4. The first die group501and the second die group502each has a planar upper surface. Referring toFIG.5A, the package substrate includes a plurality of bond pads500a,500b, the first die group501is flip-chip mounted over the package substrate500by attaching conductive bumps511to the bond pads500a, and the second die group502is mounted over the package substrate500by attaching conductive bumps521to the bond pads500b. The package substrate includes a plurality of electrically conductive wires configured to electrically connect the first and second die groups.

FIG.5Bis a cross-sectional view of first die group501shown inFIG.5Aaccording to an embodiment. Referring toFIG.5B, the first die group501includes a first die501ahaving a substrate501s, a FEOL structure501fformed on the substrate501s, a BEOL structure501bformed on the FEOL structure501f, a passivation layer501pon the BEOL structure501b, and a dielectric layer501don the passivation layer501p. In an embodiment, the first die511also includes a contact pad511cand a solder ball511sformed on the contact pad511c. In an embodiment, the FEOL structure511fmay include one or more dielectric layers having a suitable material, such as silicon oxide, silicon nitride, low-k dielectrics, e.g., carbon doped oxides, extremely low-k dielectrics, such as porous carbon doped silicon dioxide, the like, or a combination thereof. The BEOL structure may include one or more intermetal dielectric layers, patterned metal lines, and vias.

In an embodiment, the first die group501also includes a second die501bhaving a substrate511s, a FEOL structure511fformed on the substrate511s, a BEOL structure511bformed on the FEOL structure511f, a dielectric layer512dformed on a surface of the BEOL structure512b, and a bonding structure512bin the dielectric layer512d. In an embodiment, second die501bis bonded to the first die501aby hybrid bonding, i.e., a metal surface of the bonding structure512bof the second die501bis bonded to a metal surface of a bonding structure511bin a dielectric layer511ddisposed on a lower surface of the first die501a, and the surfaces of the dielectric layers512dand511dare bonded together.

FIG.5Cis a cross-sectional view of second die group502shown inFIG.5Aaccording to an embodiment. Referring toFIG.5C, the second die group502includes a plurality of dies502a,502b,502c,502d,502estacked on top of each other. The dies502a,502b,502c,502d,502eare electrically connected to each other through a plurality of conductive bonding structures503. In an embodiment, the die401also includes a conductive bump521formed on a surface of the die401aand configured to bond the die group502to the substrate500. The second die group502also includes a molding compound layer511that encapsulates the dies501a,501b,501c,501d, and501e.

In some embodiments, the first die group501and the second die group502are bump bonded to the substrate500. The substrate500, the first die group501, and the second die group502may have different coefficients of thermal expansion (CTEs). The different CTEs will induce thermal stress when the temperature in the package device50changes.

Referring back toFIG.5A, package device50is subjected to a molding operation. In an exemplary molding operation, a mold compound530is formed over the first die group510, the second die group520, and the substrate500. In a compression molding process, a liquid thermoset epoxy resin mold compound may be used in a compress molding machine, and the mold compound may be heated to an elevated temperature where it becomes a lower viscous liquid, and surrounds the first die group510, the second die group520, and the substrate500. The mold compound530solidifies when cooled and is then released from the compress molding machine. After the mold compound530is cured, a grinding operation may be performed to remove a top portion of the mold compound530. Because the CTE of epoxy does not match the CTE of silicon, when the epoxy resin mold compound is adhered to the die groups501and502, the CTE mismatch introduces thermal stress on the die groups501and502. In an embodiment, the mold compound530includes a material similar or substantially the same to the material of the molding compound layer411. In an embodiment, the mold compound530is a high thermal conductivity mold compound for good heat dissipation.

As also can be seen inFIG.5A, a height501T (or thickness) of die group501is lower than a height (or thickness)502T of die group502. It has been observed, when the height difference between die group501and die group502exceeds a threshold, stress can build up at package substrate500. For addressing stress buildup on the package substrate500, in one embodiment, a stress relief feature is configured in the package50to compensate for the height difference between the first and second die groups501and502by attaching a dummy wafer540(e.g., a carrier wafer or substrate) to an upper surface of the first die group. In some embodiments, dummy wafer540is formed from a silicon (Si) wafer, a germanium (Ge) wafer, and/or a silicon-germanium (SiGe) wafer, etc. In one embodiment, the dummy wafer540having a height540T is attached to the upper surface of the first die group through fusion bonding.

In some embodiments, for disposing the dummy wafer540, a height difference between the first die group501and the second die group502is determined, and the dummy wafer540is provided on first die group501according to the determined height difference. This may include thinning the dummy wafer540based on the height difference to obtain a thinned dummy wafer540, and mounting the thinned dummy wafer540to the first die group501to form a height-adjusted first die group501having a combined height (501T+540T) within a height range of the second die group. In an embodiment, the combined height (501T+540T) is within 10% (plus or minus) of the height502T of the second die group.

Embedded DTC in a Carrier Substrate in a Die-Group Package

In some embodiments, for saving space in a die-group package, a deep-trench capacitor (DTC) device, such as a capacitor device used in a voltage stabilizer, is embedded in a carrier substrate disposed on a die group of the die-group package.FIG.6Aillustrates a simplified view of an example die-group package60having a DTC device embedded in a carrier substrate of the die-group package. The package device60is similar to the package device50with the difference that a stress relief feature is adhered to the first die group for compensating for a height difference between the first and second die groups. Referring toFIG.6A, the package device60includes a carrier substrate604mounted on an upper surface of the first die group501. The carrier substrate604has a thickness604T, where a sum of the thickness604T and the first thickness501T of the first die group501is at least equal to or greater than the second thickness502T. Furthermore, the carrier substrate604includes at least a trench containing a dielectric material607. In some embodiments, the carrier substrate604can have material characteristics that are similar to the material characteristics of the first die group501. In some embodiments, the material of the carrier substrate604is different from the material of the mold compound so that the mold compound does not transfer or extend stress to the first die group during the molding operation. In an embodiment, the carrier substrate604has a material substantially the same as the material of the substrate of the first die group501. In an embodiment, the dielectric material607includes a dielectric constant value similar to those of the dielectric layers in the FEOL or BEOL processes.

In some embodiments, the carrier substrate604is a blank carrier substrate without any electronic components formed thereon. The carrier substrate may include glass, ceramic, silicon, silicon oxide, and the like; the air gap is completely encapsulated in the dielectric material to prevent residual moisture and pollutants from entering or remaining in the air gap during and after the forming process. The dielectric material can include a low-k dielectric material.

In an embodiment, the lower surface of the carrier substrate is planarized to adjust the thickness604T prior to being bonded to the upper surface of the first die group. In an embodiment, the bonding of the carrier substrate to the first die group includes fusion bonding. In an exemplary embodiment, the fusion bonding includes pressing the carrier substrate and the first die group against each other and performing an annealing process to cause the carrier substrate and the first die group to be bonded together due to atomic attraction forces. In an embodiment, the annealing process is performed at a temperature in a range from 500° C. to 1200° C.

As can be seen, in this example, the DTC device605is embedded in a carrier substrate604. As also can be seen, a height604T of dummy wafer604is combined with a height of first die group501to be more or less the same as a height502T of the second die group502. That is, the combined height604T+501T is more or less than the height of502T. In some embodiments, the combined height604T+501T is within 10% of the height502T, plus or minus. It is also illustrated inFIG.6Athat a DTC device605would otherwise be disposed on the substrate500of die-group package60—shown by the dotted line. This is to illustrate that by moving the DTC device605into the carrier substrate604, a space of the die-group package60is improved such that form factor of die-group package60can be reduced by reducing or eliminating the space DTC device605(shown as the dotted line) occupies. In some embodiments, the space of dotted line DTC device605shown in this example may be used to dispose other die-group structure(s).

FIG.6Bis a simplified cross-sectional view of a deep trench capacitor (DTC) device according to an embodiment. As shown inFIG.6B, deep trench capacitor (DTC) device62includes deep trench capacitors621aand621b. Deep trench capacitor621aincludes deep trenches622formed in a substrate620and a liner623disposed at the surface of deep trenches622. Deep trenches622can be formed using a patterned etch process. Liner623can be a dielectric layer, for example, SiO2, Si3N4, etc. Alternating electrode metal layers624and high K dielectric layer625are formed in the trench and can extend over the edges of the trench. The electrode material can be TiN, Ti, polysilicon, or other suitable electrode materials. The high K dielectric layer625can be formed using ZrO2, Al2O3-ZrO2, etc., or other suitable High K dielectric materials. In the example ofFIG.6B, deep trench capacitor621includes four layers of high K dielectric layer625sandwiched between five layers of electrode metal layer624. The five layers of electrode metal layer624are connected by interconnect structures626to form two electrodes627and628of the capacitor. Deep trench capacitor621bis similar to deep trench capacitor621a, and is not described in detail. The deep trench capacitor can provide higher capacitance per unit area over other capacitor structures, such as metal-insulator-metal (MIM) capacitors.

The deep trench capacitor (DTC) device62is often fabricated as a stand-alone die and packaged with a circuit that requires capacitors, such as illustrated inFIG.6A. An example of a circuit that requires a capacitor is the voltage stabilizer. A voltage stabilizer, also referred to as a voltage regulator or voltage converter, is a circuit for maintaining the voltage supply to an integrated circuit. Switched mode power converters provide higher efficiency than linear regulators. For example, switched capacitor (SC) converters have been used to provide programmable voltages to integrated circuits, but have mostly been implemented using off-chip capacitors. The switched capacitor converter has several advantages. Integrated capacitors can achieve significantly high capacitance density and low series resistance, enabling SC converters to support high output power. They can be used to implement DC-DC converters in current CMOS processes.

FIG.6Cis a simplified schematic diagram for a voltage stabilizer according to some embodiments. InFIG.6C, a voltage stabilizer67implemented as a switched capacitor regulator is illustrated. Voltage stabilizer67includes four switches S1, S2, S3and S4, a pump capacitor C1, and a load capacitor CL. A current source I1provides the charging and discharging current of capacitor C1. A voltage divider formed by resistors R1and R2provides a feedback path to amplifier A1, which controls the current source to regulate the output voltage according to a reference signal Vref. In voltage stabilizer67, capacitors C1and CL can be implemented with DTC devices described in connection toFIG.6B. As illustrated inFIG.6A, DTC device605can be embedded in a carrier substrate604. Carrier substrate604is bonded to die group501, which can include a voltage stabilizer circuit that is coupled to the DTC device605in carrier substrate604. A method of forming such a device is described below with reference toFIG.7andFIGS.8A-8E.

In some embodiments, the device embedded in the carrier wafer is not limited to DTC. Another semiconductor die can be bonded in the trench of the carrier substrate. For example, the semiconductor die can be silicon logic die, processor die, or memory die. The semiconductor die can also be an optical light source or sensor, or a mechanical sensor in a micro-electro-mechanical system (MEMS) die, or the like. In some embodiments, the semiconductor die is bonded in the trench in the carrier substrate using silicon fusion bonding between a substrate of the semiconductor die and the carrier substrate without using of intermediate adhesives.

FIG.7is a simplified flowchart illustrating a method70of fabricating a carrier substrate having an embedded DTC device for a die-group structure according to some embodiments.FIGS.8A to8Eare cross-sectional views illustrating intermediate stages of a method of fabricating a carrier substrate according to an embodiment. Method70is described below with reference to the cross-sectional views illustrated inFIGS.8A-8E.

Referring toFIGS.7and8A, the method70includes providing a carrier substrate840having a first surface801and a second surface802opposite the first surface (step701). In an embodiment, the carrier substrate can include silicon. In some embodiments, the carrier substrate provided at701is the same or substantially similar to the dummy wafer540and604shown and described in connection withFIGS.5-6. As mentioned, in some embodiments, carrier substrate provided at701is to compensate for a height difference between two die groups disposed in the die group structure.

At702, a patterned etch process is carried out to form a trench810in the carrier substrate840, as shown inFIG.8B. Here, a patterned mask is formed on the first surface and has an opening. The patterned mask may be formed of a photoresist layer. An etch process is performed onto the carrier substrate using the patterned mask as an etch mask to form a trench. The etch process can be a wet process, a dry process, or a combination thereof.

At step703, a DTC die820is bonded to the carrier substrate840in the trench810, as shown inFIG.8C. The DTC device or DTC die820may be similar to the DTC die62shown and described in connection withFIG.6B. In some embodiments, the bonding process is a fusion bonding between the substrate of the DTC die820and the carrier substrate840at the bottom of the trench810. In some embodiments, the back side of the substrate for the DTC die820may be thinned before bonding to the trench in the carrier substrate840.

At step704, a gap fill and planarization process is carried out to form a gap fill material in the gaps between the DTC die and the carrier substrate840.FIG.8Cshows gaps812between the DTC die820and the carrier substrate840. As shown inFIG.8D, a gap fill material814is formed in the gaps812between the DTC die820and the carrier substrate840. The top of gap fill material814is planarized such that the top surface822of the DTC die and the top surface of the gap fill material814are co-planar to the first surface801of carrier substrate840. The gap fill material814can be a dielectric material such as TEOS, SiO2, or the like. The gap fill material814can be formed by a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), etc.

At step705, the thickness of carrier substrate840is reduced by a polishing or etching process at the backside or second surface802of the carrier substrate. As described below with reference to the flowchart inFIG.10. The thickness of the thinned carrier substrate is determined to compensate for the height differences between die groups in a multiple die group device. Alternatively, step705is postponed until after the carrier substrate840is bonded to die group850. In other words, in this alternative embodiments, steps705is executed after step706described below.

At step706, the thinned carrier substrate840including the embedded DTC820is bonded to a die group850.FIG.8Eis a cross-sectional view illustrating a package device according to some embodiments. Referring toFIG.8E, the package device80includes a first die group850. In an embodiment, the first die group850includes bumps configured to be bonded to a base substrate (not shown), which can be an interposer or another die group. The bumps may be solder balls, conductive bumps, ball grid arrays, or the like.

The first die group850may be similar to the die group30ofFIG.3Cor die group501ofFIG.5B, and the second die group920may be similar to the die group40ofFIG.4, or die group502ofFIG.5C. In an embodiment, the first die group850includes a first die850adisposed in a first plane level, a second die850b, and a third die850cdisposed in a second plane level, where the second and third dies are hybrid bonded to the first die850aby a metal-to-metal bonding through the through-substrate vias857and oxide-to-oxide (dielectric) layer854bonding at a temperature from about 100° C. to 200° C. and a pressure in a range from about 0.7 bar to about 10 bar. In some embodiments, a dummy layer855is disposed in the second plane level and configured to provide mechanical stability to the second plane level when the second plane level does not have sufficient die density. The first die group850also includes an around-die dielectric layer (e.g., TEOS, SiO2)858surrounding the first die850ain the first plane level and the second and third dies850b,850cin the second plane level. The first die group850also includes a seal ring859surrounding each of the first, second, and third dies850a,850b, and850cand configured to prevent moisture from entering the dies.

Referring toFIG.8E, the carrier substrate840is similar to carrier substrate840ofFIG.8D. The carrier substrate840includes a silicon substrate having a trench and a DTC device820embedded in the trench. In this example, DTC device820includes deep trench capacitors821aand821b. Further, dies850band850cin the first die group850include voltage stabilizer circuits, similar to voltage stabilizer67described above in connection toFIG.6C. In some embodiments, DTC820is coupled to the voltage stabilizer circuits in dies850band850cin the first die group by through-substrate vias (TSVs)851band851c.

FIG.9is a cross-sectional view illustrating a package device according to some embodiments. The package device90is similar to the package device60ofFIG.6A. Referring toFIG.9, the package device90includes a first die group910and a second die group920flip-chip bonded to a substrate900. In an embodiment, the first die group910and the second die group920each include bumps configured to be bonded to the substrate900. The bumps may be solder balls, conductive bumps, ball grid arrays, or the like.

The first die group910may be similar to the die group30ofFIG.3Cor die group501ofFIG.5B, and the second die group920may be similar to the die group40ofFIG.4, or die group502ofFIG.5C, or die group850ofFIG.8E. In an embodiment, the first die group910includes a first die910adisposed in a first plane level, a second die910b, and a third die910cdisposed in a second plane level, where the second and third dies are hybrid bonded to the first die910aby a metal-to-metal bonding through the through-substrate vias907and oxide-to-oxide (dielectric) layer904bonding at a temperature from about 100° C. to 200° C. and a pressure in a range from about 0.7 bar to about 10 bar. In some embodiments, a dummy layer905is disposed in the second plane level and configured to provide mechanical stability to the second plane level when the second plane level does not have sufficient die density. The first die group910also includes an around die dielectric layer (e.g., TEOS, SiO2)908surrounding the first die910ain the first plane level and the second and third dies910b,910cin the second plane level. The first die group910also includes a seal ring909surrounding each of the first, second, and third dies910a,910b, and910cand configured to prevent moisture from entering the dies.

In an embodiment, the second die group920includes a first die920a, a second die920b, a third die920c, and a fourth die920dbonded to each other through conductive bonding structures913. In an embodiment, the first, second, third, and fourth dies are electrically and mechanically connected to a plurality of conductive bonding structures913. The second die group920also includes a molding compound layer915that encapsulates the dies920athrough920dand fills air gaps between the dies.

The first die group910and the second die group920may have different heights (thickness) and CTEs. When the first die group and the second die group are encapsulated in a molding compound, the height difference between the first and second die groups may induce uneven top stress to the die group that has a smaller height. The inventor has discovered that molding stress can cause warpage and delamination of the first die group when the height difference is greater than a certain percentage height range of the second die group. The inventor provided herein a solution by mounting a carrier substrate930on an upper surface of the first die group910to compensate for the height difference, thereby reducing the uneven top stress of the first die group.

Referring toFIG.9, the carrier substrate930is similar to carrier substrate840ofFIG.8E. The carrier substrate930includes a silicon substrate having a trench and a DTC device931embedded in the trench. In this example, DTC device931includes deep trench capacitors931aand931b. Further, dies910band910cin the first die group910include voltage stabilizer circuits, similar to voltage stabilizer67described above in connection toFIG.6C. In some embodiments, DTC931is coupled to the voltage stabilizer circuits in dies910band910cin the first die group by through-substrate vias (TSVs)911band911c.

In an embodiment, the carrier substrate930has a height or thickness that is characterized by a height or thickness difference between the first and second die groups. In an embodiment, the first die group has a first thickness, the second die group has a second thickness, and the sum of the thickness of the carrier substrate and the first thickness of the first die group is equal to or greater than the second thickness of the second die group. The carrier substrate930and the first die group910are hybrid bonded together. In some embodiments, the carrier substrate930may include a glass substrate, quartz, resin, or silicon substrate. In some embodiments, the carrier substrate930may be attached to a top surface of the first passivation layer using an adhesion layer. The carrier substrate can relieve mechanical and thermal stress applied to the first die group. The carrier substrate can support the die package from being warped. A fabrication process of the carrier substrate including the encapsulated air gap and the thickness adjustment has been described with reference toFIGS.7through8E, so that a detailed description is omitted herein for the sake of brevity.

Referring still toFIG.9, the package device90also includes an encapsulating layer940on the substrate900and covering the first die group910and the second die group920. In an embodiment, the encapsulating layer940may include a molding material similar to the mold compound530. As described with reference toFIG.5A, in an embodiment, the encapsulating layer940may include organic polymers, ceramics, glasses, or plastics that have a viscosity higher than the viscosity of deionized water.

FIG.10is a simplified flowchart illustrating a method100of adjusting a thickness of a device according to an embodiment. Referring toFIG.10, the method100includes, at step1001, providing a first die group and a second die group, the first die group having a first height or thickness, and the second die group having a second height or thickness, the second height or thickness being greater than the first height or thickness. At step1002, the method100includes determining a height or thickness difference between the first and second die groups. In an embodiment, when the height difference is greater than a certain percentage of the second height of the second die group, the method100will take corrective action to reduce the height difference. In an exemplary embodiment, the method100will take corrective action when the height difference is greater than 30 percent of the second height of the second die group. At step1003, in response to the determined height or thickness difference, the method100further includes providing a carrier substrate that is substantially free of electronic devices. In an embodiment, the carrier substrate is a blank silicon substrate. The carrier substrate can be formed using a fabrication process as shown inFIG.7throughFIG.8E. At step1004, the method100includes thinning the carrier substrate to obtain a thinned carrier substrate having a third height or thickness based on the determined height difference. At step1005, the method100includes mounting the thinned carrier substrate to an upper surface of the first die group in order to adjust the height or thickness of the first die group with a height range of the second die group. In an embodiment, the method100includes removing a surface portion of the carrier substrate, such that the sum of the first height of the first die group and the third height of the thinned carrier substrate is equal to or greater than the second height of the second die group. Alternatively, step1004is postponed until after the carrier substrate is bonded to first die group. In other words, in this alternative embodiments, step1004is executed after step1005. In this case, the carrier substrate is bonded to the first die group before the carrier substrate is thinned based on the determined height difference.

Referring back toFIG.6, in some embodiments, the mold compound530has a thermal expansion coefficient that is different from the material properties of the package substrate500, the first die group501, and the second die group502. Furthermore, the package die50can operate with a wide range of operational temperature, e.g., from −40 degrees C. to +150 degrees C. The wide range of temperature can cause thermal stress to the package die50. The material properties of the package substrate, the dielectric layers, electrically conductive layers, the carrier substrate, and the mold compound have coefficients of thermal expansion (CTE) that vary substantially with temperatures. For example, the CTE of silicon is about 2.5 10−6/K (2.5 ppm/° C.) at 20 degrees C., the CTE of copper is about 14 to 19 ppm/° C. at 20 degrees C., the CTE of dielectric is about 0.5 to 8 ppm/° C. at 20 degrees C. The overall CTE of the die groups can be about 2 to about 10 ppm/° C. at 20 degrees C. The CTE of the mold compound can vary more than two orders of magnitude over the temperature −40 degrees C. to +150 degrees C. The large difference in CTEs between the carry substrate and the mold compound can cause warpage to the die groups. As a result, embodiments further provide a stress relief feature that can reduce or eliminate this thermal stress. In an embodiment, the mold compound530includes at least one cavity or void disposed between the first and second die groups.

In some embodiments, a package device comprising a base substrate. A first die group includes a first set of one or more dies. The first die group is bonded to the base substrate, and the first die group includes a voltage stabilizer circuit. A second die group, including a second set of one or more dies, is bonded to the base substrate. The height of the second die group is greater than the height of the first die group. A carrier substrate is bonded to the first die group and includes a trench and a deep trench capacitor (DTC) die bonded within the trench. The DTC die is coupled to the voltage stabilizer circuit in the first die group. A combined height of the first die group and the carrier substrate is within 30% of the height of the second die group.

In some embodiments, a semiconductor device includes a package substrate. A first die group and a second die group are bonded onto the package substrate. The first die group is characterized by a first thickness, and the second die group is characterized by a second thickness. The semiconductor device also includes a carrier substrate bonded on the first die group. The carrier substrate includes a trench with a semiconductor die bonded therein. The carrier substrate is characterized by a third thickness that is determined based a difference between the first thickness and the second thickness.

In some embodiments, a method of forming a package device includes providing a carrier substrate, forming a trench in a front side of the carrier substrate, and bonding a semiconductor die in the trench. The method also includes thinning a back side of the carrier substrate based on a target thickness to obtain a thinned carrier substrate. The method further includes providing a first die group and bonding the thinned carrier substrate to the first die group to form a height-adjusted first die group.

The foregoing merely outlines features of embodiments of the disclosure. Various modifications and alternatives to the described embodiments will be apparent to those skilled in the art in view of the teachings herein. Those skilled in the art will appreciate that equivalent constructions do not depart from the scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.