Patent ID: 12224753

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the term “about” generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term “about” means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

Flip-flops are commonly used in a semiconductor device as data storage elements. A flip-flop is a device which stores a single bit of data; one of its two states represents a logical ‘1’ and the other represents a logical ‘0’. Such data storage can be used for storage of state, and such a circuit is described as sequential logic in electronics. Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous), wherein the simple ones are commonly described as latches, while the clocked ones are described as flip-flops.

Flip-flops can be divided into common types such as SR (set-reset), D (delay), T (toggle) and JK, wherein each type can be implemented by couples of logic gates, and each logic gate can be implemented by couples of transistors. With such configurations, when a huge amount of flip-flops are used in a semiconductor device, a large area is consumed, which is not desired for designers. The present disclosure proposes an input circuit of a flip-flop and an associated manufacturing method to solve the aforementioned problem.

FIG.1is a diagram illustrating a flip-flop10in accordance with an embodiment of the present disclosure. In this embodiment, the flip-flop10includes an input circuit20as a first stage, and further includes a second stage30coupled to the input circuit20. The input circuit20includes P-type Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), or so called PMOSs211to215, and N-type MOSFETs, or so called NMOSs221to225.

The PMOS211is coupled between a voltage source VDD and a terminal A. Specifically, the voltage source VDD is coupled to a source terminal of the PMOS211, and the terminal A is coupled to a drain terminal of the PMOS211. Moreover, a signal S1is directed to a gate terminal of the PMOS211. The PMOS212is coupled between the terminal A and a terminal Y. Specifically, the terminal A is coupled to a drain terminal of the PMOS212, and the terminal Y is coupled to a source terminal of the PMOS212. Moreover, a signal S2is directed to a gate terminal of the PMOS212. Because the terminal A is coupled to the drain terminals of the PMOSs211and212, the terminal A is configured to be a co-drain terminal of the PMOSs211and212.

The PMOS213is coupled between the voltage source VDD and a terminal B. Specifically, the voltage source VDD is coupled to a source terminal of the PMOS213, and the terminal B is coupled to a drain terminal of the PMOS213. Moreover, a signal S3is directed to a gate terminal of the PMOS213. The PMOS214is coupled between the terminal B and a terminal Y. Specifically, the terminal B is coupled to a drain terminal of the PMOS214, and the terminal Y is coupled to a source terminal of the PMOS214. Moreover, a signal S4is directed to a gate terminal of the PMOS214. Because the terminal B is coupled to the drain terminals of the PMOSs213and214, the terminal B is configured to be a co-drain terminal of the PMOSs213and214. In addition, because the terminal Y is coupled to the source terminals of the PMOSs212and214, the terminal Y is configured to be a co-source terminal of the PMOSs212and214.

The PMOS215is coupled between the terminal Y and the NMOS225. Specifically, the terminal Y is coupled to a source terminal of the PMOS215, and a drain terminal of the NMOS225is coupled to the drain terminal of the PMOS215. Moreover, a clock signal CLK2is directed to a gate terminal of the PMOS215. The NMOS225is coupled between the PMOS21and the terminal X. Specifically, the terminal X is coupled to a source terminal of the NMOS225. Moreover, a clock signal CLK1is directed to a gate terminal of the NMOS225.

The NMOS221is coupled between a voltage source VSS and a terminal C. Specifically, the voltage source VSS is coupled to a source terminal of the NMOS221, and the terminal C is coupled to a drain terminal of the NMOS221. Moreover, the signal S1is directed to a gate terminal of the NMOS221. The NMOS223is coupled between the terminal C and a terminal X. Specifically, the terminal C is coupled to a drain terminal of the NMOS223, and the terminal X is coupled to a source terminal of the NMOS223. Moreover, the signal S3is directed to a gate terminal of the NMOS223. Because the terminal C is coupled to the drain terminals of the NMOSs221and223, the terminal C is configured to be a co-drain terminal of the NMOSs221and223.

The NMOS222is coupled between the voltage source VSS and a terminal D. Specifically, the voltage source VSS is coupled to a source terminal of the NMOS222, and the terminal D is coupled to a drain terminal of the NMOS222. Moreover, the signal S2is directed to a gate terminal of the NMOS222. The NMOS224is coupled between the terminal4and the terminal X. Specifically, the terminal D is coupled to a drain terminal of the NMOS224, and the terminal X is coupled to a source terminal of the NMOS224. Moreover, the signal S4is directed to a gate terminal of the NMOS224. Because the terminal D is coupled to the drain terminals of the NMOSs222and224, the terminal D is configured to be a co-drain terminal of the NMOSs221and223. In addition, because the terminal X is coupled to the source terminals of the NMOSs223and224, the terminal X is configured to be a co-source terminal of the NMOSs223and224.

Those skilled in the art should understand that the source terminal and the drain terminal of a PMOS or an NMOS can be swapped. In addition, those skilled in the art should understand that the PMOSs211to214constitute a multiplexer which is denoted as MUX1inFIG.1, and the NMOSs221to224constitute a multiplexer which is denoted as MUX2inFIG.1. In practice, the multiplexers MUX1and MUX2are usually designed in the same cell, and the layout of the cell plays an important role for saving the area of input circuit10.

Refer toFIG.2, which is a diagram illustrating a layout of a cell40in accordance with an embodiment of the present disclosure. The cell40represents a part of the input circuit20. Particularly, the cell40includes the layout of the multiplexers MUX1and MUX2of the input circuit20. The cell40includes gate strips411,412,413,414and415configured to be gate terminals of transistors.

Specifically, the gate strip412extending in y direction is configured to be a co-gate terminal of the PMOS212and the NMOS222, and the signal S2is directed to the gate strip412. Moreover, the gate strip413extending in y direction is configured to be a co-gate terminal of the PMOS214and the NMOS224, and the signal S4is directed to the gate strip413. Furthermore, the gate strip414extending in y direction is configured to be a co-gate terminal of the PMOS213and the NMOS223, and the signal S3is directed to the gate strip414. Besides, the gate strips411and415extending in y direction are configured to be a gate terminal of the PMOS211and a gate terminal of the NMOS221, respectively, and the signal S1is directed to the gate strips411and415.

The cell40further includes doping regions421to430. In this embodiment, the doping regions421to425are doped with p-type material while the doping regions426to430are doped with n-type material. With such configurations, the doping regions421to425are configured to be the source/drain terminals of PMOS, and the doping regions426to430are configured to be the source/drain terminals of NMOS.

Refer toFIG.2in conjunction withFIG.1, the doping region422is configured to be the co-drain terminal A of the PMOSs211and212, the doping region423is configured to be the co-source terminal Y of the PMOSs212and214, and the doping region424is configured to be the co-drain terminal B of the PMOSs213and214. The doping region421is configured to be the source terminal of the PMOS211, and the doping region425is configured to be the source terminal of the PMOS213.

In addition, the doping region427is configured to be the co-drain terminal D of the NMOSs222and224, the doping region428is configured to be the co-source terminal X of the NMOSs223and224, and the doping region429is configured to be the co-drain terminal C of the NMOSs221and223. The doping region426is configured to be the source terminal of the NMOS222, and the doping region430is configured to be the source terminal of the NMOS221. In this embodiment, the voltage source VDD is directed to the doping regions421and425, and the voltage source VSS is directed to the doping regions426and430.

As shown inFIG.2, the transistors in the multiplexers MUX1and MUX2share the gate strips412,413and414. Those skilled in the art should understand that the distance between two immediately adjacent gate strips are defined as a pitch, and the width of the cell40is only 6 pitches long, which save more area for the input circuit20.

Refer toFIG.3, which is a diagram illustrating a layout of a cell50in accordance with an embodiment of the present disclosure. The cell50represents a part of the input circuit20. Particularly, the cell50includes the layout of the multiplexers MUX1and MUX2of the input circuit20. The cell50includes gate strips511,512,513,514and515configured to be gate terminals of transistors.

Specifically, the gate strip512extending in y direction is configured to be a co-gate terminal of the PMOS214and the NMOS224, and the signal S4is directed to the gate strip512. Moreover, the gate strip513extending in y direction is configured to be a co-gate terminal of the PMOS212and the NMOS222, and the signal S2is directed to the gate strip513. Furthermore, the gate strip514extending in y direction is configured to be a co-gate terminal of the PMOS211and the NMOS221, and the signal S1is directed to the gate strip514. Besides, the gate strips511and515extending in y direction are configured to be a gate terminal of the PMOS213and a gate terminal of the NMOS223, respectively, and the signal S3is directed to the gate strips511and515.

The cell50further includes doping regions521to530. In this embodiment, the doping regions521to525are doped with p-type material while the doping regions526to530are doped with n-type material. With such configurations, the doping regions521to525are configured to be the source/drain terminals of PMOS, and the doping regions526to530are configured to be the source/drain terminals of NMOS.

Refer toFIG.3in conjunction withFIG.1, the doping region522is configured to be the co-drain terminal B of the PMOSs213and214; the doping region523is configured to be the co-source terminal Y of the PMOSs212and214; and the doping region524is configured to be the co-drain terminal A of the PMOSs211and212. The doping region521is configured to be the source terminal of the PMOS213, and the doping region525is configured to be the source terminal of the PMOS211.

In addition, the doping region527is configured to be the co-drain terminal D of the NMOSs222and224; the doping region528is configured to be the source terminal of the NMOS221and in the meantime, to be the source terminal of the NMOS222; and the doping region529is configured to be the co-drain terminal C of the NMOSs221and223. The doping region526and the doping region530are the source terminals of the NMOSs223and224, respectively. As mentioned inFIG.1, the source terminal of the NMOSs223and224are connected to the terminal X. Therefore, the doping regions526and530are connected via a conductive line531. The connected doping regions526and530are considered as the co-source terminal X. It should be noted that, the material or the location of the conductive line531are not limited by the present disclosure.

In this embodiment, the voltage source VDD is directed to the doping regions521and525, and the voltage source VSS is directed to the doping region528. As shown inFIG.3, the transistors in the multiplexers MUX1and MUX2share the gate strips512,513and514. Therefore, the width of the cell50is only 6 pitches long, which save more area for the input circuit20.

Refer toFIG.4, which is a diagram illustrating a layout of a cell60in accordance with an embodiment of the present disclosure. The cell60represents a part of the input circuit20. Particularly, the cell60includes the layout of the multiplexers MUX1and MUX2of the input circuit20. The cell60includes gate strips611,612,613,614and615configured to be gate terminals of transistors.

Specifically, the gate strip612extending in y direction is configured to be a co-gate terminal of the PMOS213and the NMOS223, and the signal S3is directed to the gate strip612. Moreover, the gate strip613extending in y direction is configured to be a co-gate terminal of the PMOS211and the NMOS221, and the signal S1is directed to the gate strip613. Furthermore, the gate strip614extending in y direction is configured to be a co-gate terminal of the PMOS212and the NMOS222, and the signal S2is directed to the gate strip614. Besides, the gate strips611and615extending in y direction are configured to be a gate terminal of the PMOS214and a gate terminal of the NMOS224, respectively, and the signal S4is directed to the gate strips611and615.

The cell60further includes doping regions621to630. In this embodiment, the doping regions621to625are doped with p-type material while the doping regions626to630are doped with n-type material. With such configurations, the doping regions621to625are configured to be the source/drain terminals of PMOS, and the doping regions626to630are configured to be the source/drain terminals of NMOS.

Refer toFIG.4in conjunction withFIG.1, the doping region622is configured to be the co-drain terminal B of the PMOSs213and214; the doping region623is configured to be the source terminal of the PMOS211and in the meantime, to be the source terminal of the PMOS213; and the doping region624is configured to be the co-drain terminal A of the PMOSs211and212. The doping region621and the doping region625are configured to be the source terminals of the PMOSs212and214, respectively. As mentioned inFIG.1, the source terminal of the PMOSs212and214are connected to the terminal Y. Therefore, the doping regions621and625are connected via a conductive line631. The connected doping regions621and625are considered as the co-source terminal Y. It should be noted that, the material or the location of the conductive line631are not limited by the present disclosure.

In addition, the doping region627is configured to be the co-drain terminal C of the NMOSs221and223; the doping region628is configured to be the source terminal of the NMOS221, and in the meantime, to be the source terminal of the NMOS222; and the doping region629is configured to be the co-drain terminal D of the NMOSs222and224. The doping region626and the doping region630are configured to be the source terminals of the NMOSs223and224, respectively. As mentioned inFIG.1, the source terminal of the NMOSs223and224are connected to the terminal X. Therefore, the doping regions626and630are connected via a conductive line632. The connected doping regions626and630are considered as the co-source terminal X. It should be noted that, the material or the location of the conductive line632are not limited by the present disclosure.

In this embodiment, the voltage source VDD is directed to the doping region623, and the voltage source VSS is directed to the doping region628. As shown inFIG.4, the transistors in the multiplexers MUX1and MUX2share the gate strips612,613and614. Therefore, the width of the cell60is only 6 pitches long, which save more area for the input circuit20.

Refer toFIG.5, which is a diagram illustrating a layout of a cell70in accordance with an embodiment of the present disclosure. The cell70represents a part of the input circuit20. Particularly, the cell70includes the layout of the multiplexers MUX1and MUX2of the input circuit20. The cell70includes gate strips711,712,713,714and715configured to be gate terminals of transistors.

Specifically, the gate strip712extending in y direction is configured to be a co-gate terminal of the PMOS211and the NMOS221, and the signal S1is directed to the gate strip712. Moreover, the gate strip713extending in y direction is configured to be a co-gate terminal of the PMOS213and the NMOS223, and the signal S3is directed to the gate strip713. Furthermore, the gate strip714extending in y direction is configured to be a co-gate terminal of the PMOS214and the NMOS224, and the signal S4is directed to the gate strip714. Besides, the gate strips711and715extending in y direction are configured to be a gate terminal of the PMOS212and a gate terminal of the NMOS222, respectively, and the signal S2is directed to the gate strips711and715.

The cell70further includes doping regions721to730. In this embodiment, the doping regions721to725are doped with p-type material while the doping regions726to730are doped with n-type material. With such configurations, the doping regions721to725are configured to be the source/drain terminals of PMOS, and the doping regions726to730are configured to be the source/drain terminals of NMOS.

Refer toFIG.5in conjunction withFIG.1, the doping region722is configured to be the co-drain terminal A of the PMOSs211and212; the doping region723is configured to be the source terminal of the PMOS211and in the meantime, to be the source terminal of the PMOS213; and the doping region724is configured to be the co-drain terminal B of the PMOSs213and214. The doping region721and the doping region725are configured to be the source terminals of the PMOSs212and214, respectively. As mentioned inFIG.1, the source terminal of the PMOSs212and214are connected to the terminal Y. Therefore, the doping regions721and725are connected via a conductive line731. The connected doping regions721and725are considered as the co-source terminal Y. It should be noted that, the material or the location of the conductive line731are not limited by the present disclosure.

In addition, the doping region727is configured to be the co-drain terminal C of the NMOSs221and223; the doping region728is configured to be the co-source terminal X of the NMOSs223and224; and the doping region729is configured to be the co-drain terminal D of the NMOSs222and224. The doping region726is configured to be the source terminal of the NMOS221, and the doping region730is configured to be the source terminal of the NMOS222. In this embodiment, the voltage source VDD is directed to the doping region723, and the voltage source VSS is directed to the doping regions726and730.

As shown inFIG.5, the transistors in the multiplexers MUX1and MUX2share the gate strips712,713and714. Therefore, the width of the cell70is only 6 pitches long, which save more area for the input circuit20.

Refer toFIG.6, which is a diagram illustrating a layout of a cell80in accordance with an embodiment of the present disclosure. The cell80represents a part of the input circuit20. Particularly, the cell80includes the layout of the multiplexers MUX1and MUX2of the input circuit20. The cell80includes gate strips811,812,813, and814configured to be gate terminals of transistors.

Specifically, the gate strip811extending in y direction is configured to be a co-gate terminal of the PMOS211and the NMOS221, and the signal S1is directed to the gate strip811. Moreover, the gate strip812extending in y direction is configured to be a co-gate terminal of the PMOS212and the NMOS222, and the signal S2is directed to the gate strip812. Furthermore, the gate strip813extending in y direction is configured to be a co-gate terminal of the PMOS214and the NMOS224, and the signal S4is directed to the gate strip813. In addition, the gate strip814extending in y direction is configured to be a co-gate terminal of the PMOS213and the NMOS223, and the signal S3is directed to the gate strip814.

The cell80further includes doping regions821to830. In this embodiment, the doping regions821to825are doped with p-type material while the doping regions826to830are doped with n-type material. With such configurations, the doping regions821to825are configured to be the source/drain terminals of PMOS, and the doping regions826to830are configured to be the source/drain terminals of NMOS.

Refer toFIG.6in conjunction withFIG.1, the doping region822is configured to be the co-drain terminal A of the PMOSs211and212; the doping region823is configured to be the co-source terminal Y of the PMOSs212and214; and the doping region824is configured to be the co-drain terminal B of the PMOSs213and214. The doping region821is configured to be the source terminal of the PMOS211, and the doping region825is configured to be the source terminals of the PMOS213.

In addition, the doping region827is configured to be the source terminal of the NMOS221, and in the meantime, to be the source terminal of the NMOS222; the doping region828is configured to be the co-drain terminal D of the NMOSs222and224; and the doping region829is configured to be the co-source terminal X of the NMOSs223and224. The doping region826and the doping region8305are configured to be the drain terminals of the NMOSs221and223, respectively. As mentioned inFIG.1, the drain terminal of the NMOSs221and223are connected to the terminal C. Therefore, the doping regions826and830are connected via a conductive line831. The connected doping regions826and830are considered as the co-source terminal C. It should be noted that, the material or the location of the conductive line831are not limited by the present disclosure.

In this embodiment, the voltage source VDD is directed to the doping regions821and825, and the voltage source VSS is directed to the doping region827. As shown inFIG.6, the transistors in the multiplexers MUX1and MUX2share the gate strips811,812,813and814. Therefore, the width of the cell80is only 5 pitches long, which save more area for the input circuit20.

Refer toFIG.7, which is a diagram illustrating a layout of a cell90in accordance with an embodiment of the present disclosure. The cell90represents a part of the input circuit20. Particularly, the cell90includes the layout of the multiplexers MUX1and MUX2of the input circuit20. The cell90includes gate strips911_1,911_2,912,913_1,913_2and914configured to be gate terminals of transistors. The gate strips9111and911_2extending and arranged in y direction can be formed by executing a cut-off operation upon a gate strip to generate two halves of gate strip. Likewise, the gate strips913_1and913_2extending and arranged in y direction can be formed by executing a cut-off operation upon a gate strip to generate two halves of gate strip.

Specifically, the gate strip9111extending in y direction is configured to be a gate terminal of the PMOS212, and the signal S2is directed to the gate strip911_1. Moreover, the gate strip912extending in y direction is configured to be a co-gate terminal of the PMOS211and the NMOS221, and the signal S1is directed to the gate strip912. Furthermore, the gate strip913_1extending in y direction is configured to be a gate terminal of the PMOS213, and the signal S3is directed to the gate strip913_1. In addition, the gate strip914extending in y direction is configured to be a co-gate terminal of the PMOS214and the NMOS224, and the signal S4is directed to the gate strip914.

On the other hand, the gate strip911_2is configured to be the gate terminal of the NMOS223, and the signal S3is directed to the gate strip911_2. Moreover, the gate strip9132is configured to be the gate terminal of the NMOS222, and the signal S2is directed to the gate strip913_2.

The cell90further includes doping regions921to930. In this embodiment, the doping regions921to925are doped with p-type material while the doping regions926to930are doped with n-type material. With such configurations, the doping regions921to925are configured to be the source/drain terminals of PMOS, and the doping regions926to930are configured to be the source/drain terminals of NMOS.

Refer toFIG.7in conjunction withFIG.1, the doping region922is configured to be the co-drain terminal A of the PMOSs211and212; the doping region923is configured to be the source terminal of the PMOS211, and in the meantime, to be the source terminal of the PMOS213; and the doping region924is configured to be the co-drain terminal B of the PMOSs213and214. The doping region921and the doping region925are configured to be the source terminals of the PMOS212and214, respectively. As mentioned inFIG.1, the source terminals of the PMOSs212and214are connected to the terminal Y. Therefore, the doping regions921and925are connected via a conductive line931. The connected doping regions921and925are considered as the co-source terminal Y. It should be noted that, the material or the location of the conductive line931are not limited by the present disclosure.

In addition, the doping region927is configured to be the co-drain terminal C of the NMOSs221and223; the doping region928is configured to be the source terminal of the NMOS221, and in the meantime, to be the source terminal of the NMOS222; and the doping region929is configured to be the co-drain terminal D of the NMOSs222and224. The doping region926and the doping region930are configured to be the source terminals of the NMOSs223and224, respectively. As mentioned inFIG.1, the source terminals of the NMOSs223and224are connected to the terminal X. Therefore, the doping regions926and930are connected via a conductive line932. The connected doping regions926and930are considered as the co-source terminal X. It should be noted that, the material or the location of the conductive line932are not limited by the present disclosure.

Those skilled in the art should readily understand that there can be another conductive line connected between the gate strip9111and the gate strip913_2, to which the signal S2is directed. Likewise, there can be another conductive line connected between the gate strip911_2and the gate strip9131, to which the signal S3is directed.

In this embodiment, the voltage source VDD is directed to the doping region923, and the voltage source VSS is directed to the doping region928. As shown inFIG.7, the transistors in the multiplexers MUX1and MUX2share the gate strips912and914. In addition, the cut-off operation is executed to generate the gate strip911_1and911_2which carry different signals, and the gate strip9131and913_2which carry different signals. Therefore, the width of the cell90is only 5 pitches long, which save more area for the input circuit20.

Refer toFIG.8, which is a diagram illustrating a layout of a cell100in accordance with an embodiment of the present disclosure. The cell100represents a part of the input circuit20. Particularly, the cell100includes the layout of the multiplexers MUX1and MUX2of the input circuit20. The cell100includes gate strips1011_1,1011_2,1012,1013_1,1013_2and1014configured to be gate terminals of transistors. The gate strips1011_1and1011_2extending and arranged in y direction can be formed by executing a cut-off operation upon a gate strip to generate two halves of gate strip. Likewise, the gate strips1013_1and1013_2extending and arranged in y direction can be formed by executing a cut-off operation upon a gate strip to generate two halves of gate strip.

Specifically, the gate strip10111extending in y direction is configured to be a gate terminal of the PMOS213, and the signal S3is directed to the gate strip1011_1. Moreover, the gate strip1012extending in y direction is configured to be a co-gate terminal of the PMOS214and the NMOS224, and the signal S4is directed to the gate strip1012. Furthermore, the gate strip1013_1extending in y direction is configured to be a gate terminal of the PMOS212, and the signal S2is directed to the gate strip1013_1. In addition, the gate strip1014extending in y direction is configured to be a co-gate terminal of the PMOS211and the NMOS221, and the signal S1is directed to the gate strip1014.

On the other hand, the gate strip1011_2is configured to be the gate terminal of the NMOS222, and the signal S2is directed to the gate strip1011_2. Moreover, the gate strip1013_2is configured to be the gate terminal of the NMOS223, and the signal S3is directed to the gate strip1013_2.

The cell100further includes doping regions1021to1030. In this embodiment, the doping regions1021to1025are doped with p-type material while the doping regions1026to1030are doped with n-type material. With such configurations, the doping regions1021to1025are configured to be the source/drain terminals of PMOS, and the doping regions1026to1030are configured to be the source/drain terminals of NMOS.

Refer toFIG.8in conjunction withFIG.1, the doping region1022is configured to be the co-drain terminal B of the PMOSs213and214; the doping region1023is configured to be the co-source terminal Y of the PMOSs212and214; and the doping region1024is configured to be the co-drain terminal A of the PMOSs211and212. The doping region1021and the doping region1025are configured to be the source terminals of the PMOS213and211, respectively.

In addition, the doping region1027is configured to be the co-drain terminal D of the NMOSs222and224; the doping region1028is configured to be the co-source terminal X of the NMOSs223and224; and the doping region1029is configured to be the co-drain terminal C of the NMOSs221and223. The doping region1026and the doping region1030are configured to be the source terminals of the NMOSs221and222, respectively.

Those skilled in the art should readily understand that there can be another conductive line connected between the gate strip10111and the gate strip1013_2, to which the signal S2is directed. Likewise, there can be another conductive line connected between the gate strip1011_2and the gate strip1013_1, to which the signal S3is directed.

In this embodiment, the voltage source VDD is directed to the doping regions1021and1025, and the voltage source VSS is directed to the doping regions1026and1030. As shown inFIG.8, the transistors in the multiplexers MUX1and MUX2share the gate strips1012and1014. In addition, the cut-off operation is executed to generate the gate strip1011_1and1011_2which carry different signals, and the gate strip1013_1and1013_2which carry different signals. Therefore, the width of the cell100is only 5 pitches long, which save more area for the input circuit20.

FIG.9is a flowchart illustrating the manufacturing method1100of the multiplexers MUX1and MUX2in accordance with an embodiment of the present disclosure. In this embodiment, the manufacturing method1100can be used to manufacture the cell90or100in the aforementioned embodiments. Provided that the results are substantially the same, the operations shown inFIG.9are not required to be executed in the exact order. The method1100is summarized as follows.

Operation1101: a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip are deposited.

In this operation, a distance between the first gate strip and the second gate strip, a distance between the second gate strip and the third gate strip, and a distance between the third gate strip and the fourth gate strip equal.

Operation1102: a cut-off operation is executed upon the first gate strip to generate a first first gate strip and a second first gate strip. In this operation, the first first gate strip is a gate terminal of a first PMOS, and the second first gate strip is a gate terminal of a first NMOS;

Operation1103: a cut-off operation is executed upon the third gate strip to generate a first third gate strip and a second third gate strip. In this operation, the first third gate strip is a gate terminal of a second PMOS and the second third gate strip is a gate terminal of a second NMOS.

Operation1104: a first signal is directed to the first first gate strip and the second third gate strip, and a second signal is directed to the second first gate strip and the first third gate strip.

Those skilled in the art should readily understand the manufacturing method1100after reading the embodiments ofFIGS.7and8, the detailed description is omitted here for brevity.

In some embodiments, a manufacturing method of an input circuit of a flip-flop is disclose. The method includes depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip, wherein the first first gate strip is a gate terminal of a first PMOS, and the second first gate strip is a gate terminal of a first NMOS; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip, wherein the first third gate strip is a gate terminal of a second PMOS and the second third gate strip is a gate terminal of a second NMOS; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip; forming a first conductive strip connected between the first first gate strip and the second third gate; and forming a second conductive strip connected between the second first gate strip and the first third gate.

In some embodiments, a manufacturing method of an input circuit of a flip-flop is disclosed. The method includes: forming a first gate strip configured to be a co-gate terminal of a first PMOS and a first NMOS; forming a second gate strip configured to be a co-gate terminal of a second PMOS and a second NMOS, wherein the first PMOS and the second PMOS share a doping region, and the first NMOs and the second NMOS share a doping region; and forming a third gate strip configured to be a co-gate terminal of a third PMOS and a third NMOS, wherein the second PMOS and the third PMOS share a doping region, and the second NMOS and the third NMOS share a doping region.

In some embodiments, a manufacturing method of an input circuit of a flip flop is disclosed. The method includes: forming a first first gate strip, wherein the first first gate strip is configured to be a gate terminal of a first PMOS; forming a second first gate strip, wherein the second first gate strip is configured to be a gate terminal of a first NMOS; forming a second gate strip, wherein the second gate strip is configured to be a co-gate terminal of a second PMOS and a second NMOS, the first PMOS and the second PMOS share a doping region, and the first NMOS and the second NMOS share a doping region; forming a first third gate strip, wherein the first third gate strip is configured to be a gate terminal of a third PMOS, and the second PMOS and the third PMOS share a doping region; forming a second third gate strip, wherein the second third gate strip is configured to be a gate terminal of the third NMOS, and the second NMOS and the third NMOS share a doping region; and forming a fourth gate strip, wherein the fourth gate strip is configured to be a co-gate terminal of the fourth PMOS and a fourth NMOS, the third PMOS and the fourth PMOS share a doping region, and the third NMOS and the fourth NMOs share a doping region.