Patent ID: 12249970

Any reference signs in the claims shall not be construed as limiting the scope.

In the different drawings, the same reference signs refer to the same or analogous elements.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

In a first aspect embodiments of the present invention relate to a filter200comprising a number of cascaded building blocks100for filtering an incoming signal. Each building block100, also referred as unit cell, has a topology which is especially suited for building the filter200. It may for example be used for implementing an analog (mixed-mode) FIR filter.

The basic elements and topology of such a building block will therefore be explained with the aid of the signal flow graph of a filter200in accordance with embodiments of the present invention and illustrated inFIG.4.

Each building block100a,100bcan be used for filtering an incoming signal. Each building block comprises a first delay element110a,110bhaving a first delay τ1, and a second delay element120a,120bhaving a second delay τ2.

Scaling devices, this may be amplifiers or attenuators, are present between the inputs and outputs of the delay elements. A first scaling device130a,130bis present between an input node of the first delay element110a,110band an output node of the second delay element120a,120b. A second scaling device140a,140bis present between an output node of the first delay element110a,110band an input node of the second delay element120a,120b.

Each building block100a,100bmoreover comprises a first cross scaling device150a,150bconnected between the output node of the first delay element110a,110band the output node of the second delay element120a,120b, and/or a second cross scaling device160a,160bbetween the input node of the first delay element110a,110band the input node of the second delay element120a,120b.

When an incoming signal is applied to the input node of the first delay element110a,110ba filtered signal can be obtained at the output node of the second delay element120a,120b. Each building bock100a,100bis configured such that incoming signals at the input node and output node of the second delay element120a,120bare summed together.

Using such a building block with 2 delay elements a 4 taps transversal filter can be made. This is illustrated inFIG.5. In this example, 4 filter taps with different delays are schematically illustrated. In embodiments of the present invention the tap delay value Tdmay be equal to the symbol period TS(in the example ofFIG.5τ1is equal to 2Tsand τ2is equal to Ts). In that case symbol spaced FIR equalizers are discussed (i.e. the same new topology can also be used to realize fractionally spaced FIR filters). For example, for a 100 Gbd signal, τ1may be selected 20 ps, and τ2may be selected 10 ps to realize a symbol spaced filter.

In the exemplary embodiment, illustrated inFIG.4, the filter is obtained by cascading the first building block100aand the second building block100b. The output of the first delay element110aof the first building block100ais connected with the input of the first delay element110bof the second building block100b, and the output of the second delay element120bof the second building block100bis connected with the input of the second delay element120aof the first building block100a. The configuration is such that when an incoming signal is applied to the input of the first delay element110aof the first building block an output signal can be obtained at the output of the second delay element120aof the first building block.

In the example ofFIG.4the second scaling device140aof the first building block is the same as the first scaling device130bof the second building block.

In the example ofFIG.4, 2 building blocks are cascaded. The invention is, however, not limited thereto. Thus, a higher order filter can be obtained by cascading the building blocks. This is illustrated inFIG.6. This architecture is called the full cross filter hereafter. In this example all rectangle blocks represent delay elements with their corresponding delay marked to obtain a uniformly symbol spaced FIR filter (τ1is equal to 2Tsand τ2is equal to Ts). All triangles represent scaling devices which are used to tune each degree of freedom in the FIR filter (e.g. variable gain amplifiers (VGA)). Nodes connected to the output of the scaling devices are summation nodes for the signals.

The most essential element in the different embodiments of the present invention are the cross connected scaling devices. These make it possible to implement distributed summation with a reduced amount of delay elements per order.

In this example the number of separate delay elements is ceil(2*(n)/3) with n+1 the number of amplifiers in the filter.

The summation is performed in a distributed way, limiting bandwidth limitation in the summation but loads are higher than in the distributed variant. In case the signal x(t) is a binary logical signal, the delay elements of the input delay line can be digital flip-flops. This makes this architecture viable for a mixed-mode equalizer structure. This structure is implementable in unit cells as for each increase of 3 orders, 2 delay cells and 3 scaling devices can be cascaded without affecting the performance in the first taps of the equalizer. A transposed architecture is possible when the location of the Tsand 2Tsblocks are interchanged (τ1is equal to Tsand τ2is equal to 2Ts). This is illustrated inFIG.7.

In the exemplary embodiments illustrated inFIGS.4to7, 2 cross scaling devices are used per building block. This is not strictly necessary for the present invention. A building block may as well only comprise the first cross scaling device or the second cross scaling device. Both topologies are shown inFIG.8andFIG.9.

These architectures are further addressed as the half cross filters. To correct for the missing scaling devices, new delay values must be introduced. In this example the separate delay values are all equal to the symbol period Ts. In total, n of them are present. The summation is performed in a distributed way limiting bandwidth limitation in the summation, but loads are higher than in the distributed variant. In case the incoming signal x(t) is a binary logical signal, the delay elements of the input delay line can be digital flip-flops. This makes this architecture viable for a mixed-mode equalizer structure. This structure is implementable in unit cells as for each increase of 2 orders, 2 delay cells and 2 scaling devices can be cascaded without affecting the performance in the first taps of the equalizer.

The complete architectures can be both implemented in the analog and digital domain.

The architectures itself are independent of the symbol rate and delay values with respect to the symbol rate. For this purpose, the values can be scaled to the user's needs. However, when one wants to obtain a uniform distribution of the taps, the ratios between forward and backward delays must be kept.

The implementation of the delay elements and scaling devices itself are variable and can be freely chosen by the designer. Both active and passive delay solutions could be used in direct implementations of the delay cells. Using digital flip-flops is also possible (e.g. at the input of the forward delay lines), which omits the physical implementation of the delays but still the same architecture is used. These clocked solutions lead to an efficient mixed-mode filter (e.g. equalizer) structure.

Depending on the situation and application, the scaling devices (e.g. VGAs) can be linear/nonlinear, have a fixed gain/attenuation or a limited gain/attenuation range.

The summation nodes (i.e. the input and output nodes at the second delay elements) can be implemented by analog additions or can be implemented by digital summations in digital designs.

The order of the filter is variable as well. The unit cells can be freely cascaded to reach higher order filters. Not all scaling devices should be physically present if one desires to lower the order of the filter.

All blocks can be implemented as complex scaling devices and delay elements. This means that each delay line is doubled and each scaling device is implemented 4 times and connected properly between the delay line nodes.

The previous discussions of FIR filter topologies can be summarized in following table. For each architecture, the performance with respect to several relevant properties are reported. Again, a symbol spaced FIR filter of the nth order is assumed without loss of generality. The filter order is defined as n. The property “maximum load”, is defined as the maximum total sum of incoming and outgoing signals on a node. From the table, it can be concluded that both the full cross and half cross-FIR architecture provide a unique set of properties which address both the problems of node complexity and number delay elements simultaneously.

#LinearMax.Mixed modeFIR# DelayDelayDelaylinear#SummationMaxCascadablewithouttopologyelementselementsvaluesdelaynodesload(order/cascade)oversamplingDirectn0TsNA1n + 1NoYesTransposednnTsTsnn + 1NoNA2directDistributed2nnaTs,(1-a)Tsn3YesNo(1-a)TsFull cross FIRCeil(2*n/3)Ceil⁡(n3)Ts, 2 TsTs1+Floor⁡(n3)5YesYesTransposed full crossCeil(2*n/3)Ceil⁡(n3)Ts, 2 Ts2Ts1+Floor⁡(n3)5YesYesFIRHalf cross FIR 1nceil⁡(n-12)TsTsceil⁢(n+12)4YesYesHalf crossFIR 2nceil⁡(n2)TsTsceil⁡(n+22)4YesYes

In the full and half cross-filters illustrated inFIG.6toFIG.9and for which the parameters are summarized in the table above, the delay values are equal to or a multiple of Ts(similar as the direct implementation). The relation to the symbol period can be advantageous over the distributed implementation as these values can easily be generated in clocked input signals or S/H systems where only 1 phase clock can be used (without oversampling).

The number of delay elements used in the filter should be limited to reduce the introduced distortions. It is therefore advantageous to have as low as possible physical delay elements in e.g. active delay solutions. The full cross filter has the lowest number of delay elements. The half cross filters have n elements, which is still advantageous over the distributed architecture and equal in performance to most other solutions.

Besides the total number of delay elements, the amount of possible delay cells that can be implemented as digital flip-flops is important. In case of binary logical input data, the input delay lines can be replaced by shifted clocked versions of the input data which omits the implementation of these physical delays. Both in the full cross architecture and half cross, half of the delay cells could be omitted in this way. This makes the full cross solution (and half cross) ideally suited for high order mixed-mode equalizer structures.

As, in the full and half cross-filters illustrated inFIG.6toFIG.9, the summation is distributed and an input delay line is used, the maximum load on a node does not increase for higher order implementations (similar as the distributed architecture). This is an advantage in high order filters with stringent bandwidth limitations. Compared to the distributed architecture, the maximum load is higher but still limited.

Both the half cross and full cross solution are implementable in unit cells. This means that in analog implementations, one can increase the order by cascading equal blocks. This has a clear advantage in design as only one unit cell must be designed, independent of the order. The largest benefit, however, can be found in the fact that increasing the order does not affect the performance of filter taps that are generating lower order terms. For example, in the direct implementation, the bandwidth of all taps drops with increasing filter order.

In embodiments of the present invention the first delay element110of a building block may be implemented by delaying demultiplexed versions of the incoming signals and by multiplexing again these signals.

An example of a delay element which is adapted for delaying demultiplexed versions (xhalf,1(t), xhalf,2(t)) at half of the clock rate at which the output signal is sampled, and for multiplexing again these signals is illustrated inFIG.10. In this example the delay elements are implemented using one or more latches. For example flip flops (FF) comprising 2 latches may be used to generate symbol spaced delays at the half rate. Three multiplexers (1:2) are used for multiplexing the signals. A non-delayed version of the incoming signal xfull(t) and two delayed versions xfull(t−τ1) and xfull(t−2τ1) are obtained.

An example of a delay element which is adapted for delaying demultiplexed versions (xquart,1(t), xquart,2(t), xquart,3(t), xquart,4(t)) at a quarter of the clock rate, and for multiplexing again these signals is illustrated inFIG.11. In this example the delay elements are implemented using latches (latch). Three multiplexers (1:4) are used for multiplexing the signals. A non-delayed version of the incoming signal xfull(t) and two delayed versions xfull(t−τ1) and xfull(t−2τ1) are obtained.

One of the main disadvantages in the full cross architecture is the presence of delay values of 2Ts. In simple analog active delay solutions (first order solutions), it is difficult to implement these large values without too much group delay distortion. If sub-symbol spaced analog equalizers with active delays are intended, the group delay distortion with respect to the symbol period will be much lower and the disadvantage of the high delay value can be dropped.

On the other hand, if one intends to keep the group delay distortion low in symbol spaced equalizers, higher order delay cells are necessary increasing the apparent number of delay cells per filter order.

When clocked implementations are used, the problems arising from the 2Tsdelay values can be easily overcome by using a divided clock.

In a second aspect, embodiments of the present invention relate to a multilevel signal generator300comprising a predefined number of filters200in accordance with embodiments of the present invention. In such a multilevel signal generator the filters have the same number of building blocks and are connected in parallel. A first filter is connected in parallel with a second filter by connecting the input of the second delay element of a building block of the first filter with the input of the second delay element of the corresponding building block of the second filter and by connecting the output of the second delay element of a building block of the first filter with the output of the second delay element of the corresponding building block of the second filter. The connection is done such that when an incoming signal is applied to the input of the first delay element110of the first building block of the first filter, and when an incoming signal is applied to the input of the first delay element110of the first building block of the second filter, an output signal can be obtained at the output of the second delay element120of the first building block of the first and the second filter. The incoming signals at the input node of the second delay element are summed together and the incoming signals at the output node of the second delay element are summed together. The second delay element of the first building block may be the same as the second delay element of the second building block.

The input delay line and scaling devices can be implemented M times in parallel to simultaneous generate and equalize multilevel (2M-PAM) signaling from 2 level input data.

An example for PAM4 modulation is illustrated inFIG.12. In this example two filters200are put in parallel and the second delay elements120are shared between the filters.

InFIG.13this is extended to PAM-2Msignal generation. In this example M filters (200,1;200,2; . . . ;200, M) are put in parallel and the second delay elements are shared between the filters. When applying input signals x1(t) to xm(t) to the respective input nodes an output signal yPAM 2M(t) is obtained at the output node of the multilevel signal generator.

In a third aspect embodiments of the present invention relate to a complex multilevel signal generator400. Such a complex multilevel signal generator comprises two multilevel signal generators300A,300B each comprising the same even number of filters (half for the real or inphase signals, half for the imaginary/quadrature signals) connected one by one with each other wherein the first delay elements of corresponding filters are connected in parallel.

FIG.14shows a 4-QAM complex signal generator in accordance with embodiments of the present invention. This figure shows a first multilevel signal generator300A and a second multilevel signal generator300B. The first multilevel signal generator300A comprises a first filter200A,1and a second filter200A,2. The second multilevel signal generator300B comprises a first filter200B,1and a second filter (hidden behind200B,1). The first delay elements (with delay τ1) of the first filters of both multilevel signal generators are connected in parallel. Also, the first delay elements of the second filters of both multilevel signal generators are connected in parallel. The first delay elements are shared between the coupled filters.

The in-phase data Iin(t) is applied to the input of the first delay element of the first building block of the first filters and the quadrature-phase Qin(t) is applied to the input of the first delay element of the first building block of the second filters.

The quadrature-phase output signal Qout(t) can be retrieved from the output of the delay element of the first building block of the first multilevel signal generator300A. The in-phase output signal Iout(t) can be retrieved from the output of the delay element of the first building block of the second multilevel signal generator300B.

FIG.15shows a 22M-QAM complex multilevel signal generator in accordance with embodiments of the present invention. Pairs of filters are formed by connecting the first delay elements of corresponding filters of the two multilevel signal generators in parallel. The in-phase and quadrature input signals Iin,0(t), Qin,0(t), Iin,1(t), Qin,1(t), . . . Iin,M(t), Qin,M(t) are connected to the filter inputs and the in-phase and quadrature output signals Iout(t), Qout(t) are obtained from the filter outputs.

From the embodiments explained above it can be concluded that it is an advantage of embodiments of the present invention that the maximum number of components connected to a single node can be limited, independent of the filter order. Hence the filter order can be increased without reducing the bandwidth of the filter.

It is an advantage of embodiments of the present invention that the amount of delay cells required for a given order is reduced compared to existing filter implementations, thus reducing power and/or circuit area compared to existing implementations. In addition, when using clocked active delay cells, a filter topology according to embodiments of the present invention allows lower clock frequencies compared to several existing high-speed filter structures.

Building blocks according to embodiments of the present invention may be used as area efficient mixed-mode equalizer structures for multi-level modulation formats.

They can be implemented as FIR filters to overcome bandwidth limitations in communication links. They can be integrated at either the transmitter or at the receiver side. Transmit side equalization has the advantage that the error-free data to be transmitted is readily available, but poses challenges while adjusting the tap coefficients (as the link information required for setting the tap values is in principle only known at the receiver). Receiver side equalization does not have this problem, however needs to handle signals that may have undergone significant attenuation by the link. Therefore, it is interesting to pre-compensate the frequency dependent loss of the overall link at the transmit side.

As mentioned above, the delay cells required to realize a FIR filter can be implemented as digital flipflops, provided the input to these delay cells is a binary logic signal. This is the normal case for transmit side equalizers. Compared to passive delay line structures using transmission lines, digital flip-flops require significantly less area (several orders of magnitude), which is advantageous not only from a cost perspective but also because it allows scaling the equalizer more readily to higher orders. It is therefore an advantage of embodiments of the present invention that transmit side equalizers can be realized with a topology of the FIR filter with a large fraction of the delay cells having binary logic signals as their inputs.

An important extension occurs when transmitting multilevel modulation formats (e.g. M-ary pulse amplitude modulation). In one possible implementation, a transmitter receives a number of binary logic bitstreams and converts these to an 2M-PAM output signal. A problem then is how to combine these different bitstreams into this 2M-PAM output signal, while simultaneously performing equalization preferably with a significant amount of delay cells implemented as digital flip-flops. It is an advantage of embodiments of the present invention that both the node complexity problem and the number of delay elements problem are tackled, especially when increasing the modulation order M. In contrast to conventional equalizer solutions, which are optimized to address either the node complexity problem or the number of delay elements problem, in embodiments of the present invention both problems are tackled simultaneously, which makes it ideally suited for multilevel modulation mixed mode equalizers.

The concept of the cascadable building blocks can be implemented as filtering architecture for high speed data communications. It can for example extent current NRZ transmitters with equalizing and multi-level signal generation.

Embodiments of the present invention may for example be implemented using CMOS or BiCMOS process technology.