Patent ID: 12224122

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the features of the present invention will be specifically described by describing preferred embodiments of the present invention. In the following, a multilayer ceramic capacitor is described as an example of an electronic component of the present invention. However, the electronic component is not limited to the multilayer ceramic capacitor, and may be another electronic component such as, for example, an inductor or an LC filter.

FIG.1is a perspective view of an example of a multilayer ceramic capacitor10according to a preferred embodiment of the present invention.FIG.2is a cross-sectional view of the multilayer ceramic capacitor10illustrated inFIG.1along the line II-II.FIG.3is a cross-sectional view of the multilayer ceramic capacitor10illustrated inFIG.1taken along the line III-III.

As illustrated inFIGS.1to3, the multilayer ceramic capacitor10preferably has a rectangular parallelepiped shape or a substantially rectangular parallelepiped shape as a whole, and includes a laminate11and a pair of external electrodes14(14aand14b). The pair of external electrodes14(14aand14b) face each other as illustrated inFIG.1.

Here, the direction in which the pair of external electrodes14face each other is defined as a length direction L of the multilayer ceramic capacitor10, the lamination direction of internal electrodes13(13a,13b) described later is defined as a lamination direction T, and the direction orthogonal or substantially orthogonal to either of the length direction L and the lamination direction T is defined as a width direction W.

The size of the multilayer ceramic capacitor10is preferably, for example, about 0.2 mm to about 3.2 mm (inclusive) in dimension in the length direction L, about 0.1 mm to about 1.6 mm (inclusive) in dimension in the width direction W, and about 0.1 mm to about 1.6 mm (inclusive) in dimension in the lamination direction T.

The laminate11includes a first end surface15aand a second end surface15bopposite to each other in the length direction L, a first main surface16aand a second main surface16bopposite to each other in the lamination direction T, and a first side surface17aand second side surface17bopposite to each other in the width direction W.

The first end surface15aand the second end surface15bextend along the width direction W and the lamination direction T. The first main surface16aand the second main surface16bextend along the length direction L and the width direction W. The first side surface17aand the second side surface17bextend along the length direction L and the lamination direction T.

The laminate11preferably has rounded corner portions and ridge line portions. Here, the corner portion is a portion at which the three surfaces of the laminate11intersect, and the ridge line portion is a portion at which the two surfaces of the laminate11intersect.

As illustrated inFIGS.2and3, the laminate11includes an inner layer portion21, outer layer portions22, and side margin portions23.

The inner layer portion21includes dielectric layers12, first internal electrodes13a, and second internal electrodes13b. The dielectric layer12is sandwiched between the first internal electrode13aand the second internal electrode13b. The inner layer portion21is provided by alternately laminating the plurality of first internal electrodes13aand the plurality of second internal electrodes13bwith the dielectric layers12interposed therebetween.

The dielectric layer12preferably includes a dielectric material including Ba and Ti as main components, and for example, includes about 90 mol % or more of Ba and Ti in combination. More specifically, the dielectric layer12preferably includes a perovskite compound with Ba and Ti as main components, and includes dielectric ceramic particles having a perovskite structure. At least one of Si, Mg, and Ba, for example, may be included in these main components as an additive. The dielectric layers12may also include rare earth elements, for example, Dy, Y and Ho. However, the dielectric layer12does not include Ca and Zr. The thickness of the dielectric layers12is preferably, for example, about 0.3 μm or more and about 0.8 μm or less.

The first internal electrode13aand the second internal electrode13bface each other in the lamination direction T with the dielectric layer12interposed therebetween. Capacitance is generated in a portion where the first internal electrode13aand the second internal electrode13bface each other with the dielectric layer12interposed therebetween.

The dielectric layer12extends in the width direction W and the length direction L. The first internal electrode13aextends flatly along the dielectric layer12and is drawn to the first end surface15aof the laminate11. The second internal electrode13bextends flatly along the dielectric layer12and is drawn to the second end surface15bof the laminate11.

The first internal electrode13aand the second internal electrode13bpreferably include, for example, Cu. The first internal electrode13aand the second internal electrode13bmay include, in addition to Cu, other metal(s), for example, Ni, Ag, Pd, an Ag—Pd alloy, or Au. The first internal electrode13aand the second internal electrode13bmay include the same dielectric particles or similar dielectric particles as the dielectric layer12.

The number of laminated internal electrodes13including the first internal electrodes13aand the second internal electrodes13bis preferably, for example, about 10 or more and about 500 or less. The thickness of the first internal electrode13aand the second internal electrode13bis preferably, for example, about 0.3 μm or more and about 0.8 μm or less.

When the cross section including the width direction W and the lamination direction T of the multilayer ceramic capacitor10is viewed from the length direction L, the positions of the end portions of the internal electrodes13are aligned in the lamination direction T, or may have such a positional relationship that the central portion in the lamination direction bulges outward compared to the outer sides in the lamination direction. In other words, the dimensions in the width direction W of the internal electrodes13located at the central portion in the lamination direction T are equal to or larger than the dimensions in the width direction W of the internal electrodes13located on the outer side in the lamination direction T.

The outer layer portions22are provided on both outer sides in the lamination direction T of the inner layer portion21. That is, the inner layer portion21is sandwiched between the two outer layer portions22provided on both the outer sides in the lamination direction T. The outer layer portions22each correspond to a region in which none of the first internal electrode13aand the second internal electrode13bexist except for the side margin portions23described later when a freely-selected cross section including the lamination direction T and the width direction W of the laminate11is viewed from the length direction L. The outer layer portions22are each preferably a dielectric including the same material or a similar material as the dielectric layer12.

The dimensions in the lamination direction T of the outer layer portions22, that is, a distance between the internal electrode at a position closest to the first main surface16aamong the first internal electrodes13aand the second internal electrodes13b, and the first main surface16aand a distance between the internal electrode at a position closest to the second main surface16bamong the first internal electrodes13aand the second internal electrodes13band the second main surface16bare each preferably, for example, about 5 μm or more and about 30 μm or less.

The side margin portions23each correspond to a region in which none of the first internal electrode13aand the second internal electrode13bexists when a freely-selected cross section including the length direction L and the width direction W of the laminate11is viewed from the lamination direction T. As illustrated inFIG.3, the side margin portions23are located on both outer sides in the width direction W. That is, the two side margin portions23are provided to sandwich the inner layer portion21and the outer layer portions22in the width direction W.

In the present preferred embodiment, the side margin portion23includes a plurality of side margin layers laminated in the width direction W. Specifically, the side margin portion23includes an outer side margin layer23aand an inner side margin layer23b. The outer side margin layers23aare located on the first side surface17aside and the second side surface17bside of the laminate11. Further, the inner side margin layers23bare located on the inner layer portion21side.

It should be noted that the side margin portion23includes the plurality of side margin layers23aand23b, and the boundary is able to be easily confirmed by observation with an optical microscope due to the difference in the sinterability between the outer side margin layer23aand the inner side margin layer23b. That is, the boundary exists between the outer side margin layer23aand the inner side margin layer23b.

The dimension in the width direction W of the side margin portion23is preferably, for example, about 5 μm or more and about 30 μm or less. In the present preferred embodiment, the dimension in the width direction W of the outer side margin layer23ais larger than the dimension in the width direction W of the inner side margin layer23b.

The dimension in the width direction W of the side margin portion23is an average dimension obtained by measuring dimensions of the side margin portion23at a plurality of locations along the lamination direction T and calculating an average based on the measurement results. The measuring method of the dimension in the width direction W of the side margin portion23is as follows.

First, a surface including the width direction W and the lamination direction T of the multilayer ceramic capacitor10is exposed. This surface is hereinafter referred to as a “WT cross section”. Next, an image is taken with an optical microscope so that the end portions in the width direction W of the first internal electrodes13aand the second internal electrodes13bin the WT cross section and any one of the two side margin portions23located on both the outer sides in the width direction W are captured within the same field of view or substantially the same field of view. There are three imaging locations of an upper portion, a central portion, and a lower portion in the lamination direction T. Then, in the upper portion, the central portion, and the lower portion, a plurality of line segments parallel or substantially parallel to the width direction W are drawn from the end portions in the width direction W of the first internal electrodes13aand the second internal electrodes13btoward the first side surface17aor the second side surface17b, and the lengths of the line segments are measured. The average value of the lengths of the line segments measured, as described above, at each of the upper portion, the central portion, and the lower portion is calculated. Further, the average values are further averaged to obtain a dimension in the width direction W of the side margin portion23.

The side margin portion23preferably includes a dielectric with Ca, Zr, and Ti, for example. That is, the side margin portion23includes a dielectric ceramic material with Ca, Zr, and Ti as main components. The side margin portion23preferably further includes Si, for example, as an additive. Each component is able to be observed by WDX or TEM.

The outer side margin layer23aincludes a larger content of Si than the inner side margin layer23b. That is, the molar ratio of Si/Ti of the outer side margin layer23ais higher than the molar ratio of Si/Ti of the inner side margin layer23b. Since Si functions as a sintering aid, the outer side margin layer23aprovided by firing in manufacturing the multilayer ceramic capacitor10includes a denser structure than the inner side margin layer23b. With this, the strength of the side margin portion23is able to be significantly improved, so that the side margin portion23is unlikely to be cracked or chipped, thus being able to significantly reduce or prevent the entry of moisture into the inside. Each component can be observed by WDX or TEM.

A first external electrode14ais provided on the entire or substantially the entire first end surface15aof the laminate11, and wraps around the first main surface16a, the second main surface16b, the first side surface17a, and the second side surface17b, from the first end surface15a. The first external electrode14ais electrically connected to the first internal electrodes13a.

A second external electrode14bis provided on the entire or substantially the entire second end surface15bof the laminate11, and wraps around the first main surface16a, the second main surface16b, the first side surface17a, and the second side surface17b, from the second end surface15b. The second external electrode14bis electrically connected to the second internal electrodes13b.

In the present preferred embodiment, as illustrated inFIG.2, the first external electrode14aincludes a three-layer structure including a first base electrode layer141a, a first lower plating layer141bprovided on the surface of the first base electrode layer141a, and a first upper plating layer141cprovided on the surface of the first lower plating layer141b.

The first base electrode layer141acovers the entire or substantially the entire first end surface15aof the laminate11, and covers a portion of each of the first side surface17aand the second side surface17band a portion of each of the first main surface16aand the second main surface16b, from the portion covering the first end surface15a.

Further, in the present preferred embodiment, as illustrated inFIG.2, the second external electrode14bincludes a three-layer structure including a second base electrode layer142a, a second lower plating layer142bprovided on the surface of the second base electrode layer142a, and a second upper plating layer142cprovided on the surface of the second lower plating layer142b.

The second base electrode layer142acovers the entire or substantially the entire second end surface15bof the laminate11, and covers a portion of each of the first side surface17aand the second side surface17band a portion of each of the first main surface16aand the second main surface16b, from the portion covering the second end surface15b.

The first base electrode layer141aand the second base electrode layer142apreferably include, for example, metal(s) such as Ni, Cu, Ag, Pd, an Ag—Pd alloy, or Au. The first base electrode layer141aand the second base electrode layer142amay be a plurality of layers.

The first base electrode layer141aand the second base electrode layer142amay be formed by co-firing in which the first base electrode layer141aand the second base electrode layer142aare fired with the first internal electrodes13aand the second internal electrodes13bat the same time, or may be formed by post-fire in which conductive paste is applied on the laminate11and the first base electrode layer141aand the second base electrode layer142aare fired. In the case of formation by co-firing, for example, the first internal electrode13aand the second internal electrode13bmay include Ni, and the first base electrode layer141aand the second base electrode layer142amay also include Ni. In the case of formation by the co-firing, the first base electrode layer141aand the second base electrode layer142ainclude a common material made of a dielectric material shared with the dielectric layer (note that the common material is a dielectric material which is commonly used (i.e. shared) in the electrode layer and the dielectric layer). The first base electrode layer141aand the second base electrode layer142apreferably include three or more times by weight of the common material as compared with the common material included in the internal electrode. The first base electrode layer141aand the second base electrode layer142amay be formed by direct plating, or may be formed by curing a resin layer including conductive particles and thermosetting resin.

It is preferable that the first lower plating layer141band the second lower plating layer142binclude Ni, for example, in order to prevent solder breakage. However, the first lower plating layer141band the second lower plating layer142bmay include, for example, metal(s) such as Cu, Ag, Pd, an Ag—Pd alloy, or Au in addition to Ni.

It is preferable that the first upper plating layer141cand the second upper plating layer142cinclude Sn, for example, in order to significantly improve the mountability. However, the first upper plating layer141cand the second upper plating layer142cmay include, for example, metal(s) such as Cu, Ag, Pd, an Ag—Pd alloy, or Au, in addition to Sn.

The configurations of the first external electrode14aand the second external electrode14bare not limited to the configurations described above. For example, by directly plating the laminate11, the first external electrode14aand the second external electrode14bmay be formed by plating.

(Circuit Board on which Multilayer Ceramic Capacitor is Mounted)

The multilayer ceramic capacitor10described above is able to be mounted on a circuit board so that the side margin portion23faces the mounting surface of the circuit board.

FIG.4is a view of a state in which the multilayer ceramic capacitor10is mounted on a circuit board40. The multilayer ceramic capacitor10is mounted so that the side margin portion23faces a mounting surface40aof the circuit board40. More specifically, the first external electrode14aand the second external electrode14bof the multilayer ceramic capacitor10are mounted by each being joined to a land electrode provided on the mounting surface40aof the circuit board40by solder45.

In the example illustrated inFIG.4, the side margin portion23located on the first side surface17aside is mounted to face the mounting surface40aof the circuit board40, but the side margin portion23located on the second side surface17bside may be mounted to face the mounting surface40aof the circuit board40.

In the mounted state illustrated inFIG.4, the lamination direction of the first internal electrodes13aand the second internal electrodes13bare parallel or substantially parallel to the extending direction of the mounting surface40aof the circuit board40.

A distance L1between the end portion of the multilayer ceramic capacitor10on the circuit board40side and the mounting surface40aof the circuit board40is preferably, for example, about 20 μm or more and about 50 μm or less.

In a high frequency band, a skin effect concentrates current on the surface of a conductor. Therefore, the current flowing in the multilayer ceramic capacitor10mounted on the circuit board40flows in the vicinity of the surface of the internal electrode13closest to the mounting surface40aof the circuit board40as indicated by the arrow inFIG.4. In this case, the configuration of the side margin portion23on the side close to the mounting surface40aof the substrate40greatly affects a current loss, but in the present preferred embodiment, the side margin portion23preferably includes Ca, Zr, and Ti, for example, as main components. That is, since the side margin portion23includes Ca, Zr and Ti as main components included in a dielectric of a temperature compensating capacitor which is able to provide good high frequency characteristics, the current loss is able to be reduced, and the high frequency characteristics are able to be significantly improved.

In addition, since the multilayer ceramic capacitor10in the present preferred embodiment is manufactured by bonding, later, ceramic green sheets defining the side margin portions23as described later, the dimension in the width direction W of the side margin portions23is able to be shortened. With this, the distance between the circuit board40and the position where the current flows in the multilayer ceramic capacitor10is able to be shortened, so that a current path is able to be shortened, and an equivalent series inductance (ESL) is able to be reduced.

Furthermore, the dielectric layers12of the inner layer portion21each include Ba and Ti but do not include Ca and Zr, so that the capacitance per volume of the multilayer ceramic capacitor10is able to be increased.

The advantageous effects described above are advantageous effects of the circuit board40on which the multilayer ceramic capacitor10is mounted, and also advantageous effects of the multilayer ceramic capacitor10itself.

(Method of Manufacturing Multilayer Ceramic Capacitor)

Hereinafter, an example of the method of manufacturing the multilayer ceramic capacitor10which includes the structure described above is described.FIGS.5A and5Bare views of an example of the method of manufacturing the multilayer ceramic capacitor10according to a preferred embodiment of the present invention, in whichFIG.5Ais a schematic view of a ceramic green sheet on which conductive films are provided, andFIG.5Bis a schematic view of a state in which the ceramic green sheets on which conductive films are provided are being laminated.FIG.6is a perspective view of an example of the appearance of a laminate chip prepared in the middle of the manufacture of the multilayer ceramic capacitor10.

First, a perovskite compound including Ba and Ti is prepared as a dielectric material. A ceramic slurry is prepared by mixing, as additives, at least one of Si, Mg, and Ba, an organic binder, an organic solvent, a plasticizer, and a dispersant in a predetermined ratio with dielectric powder obtained from the dielectric material.

Then, ceramic green sheets50aand50bare prepared by applying the prepared ceramic slurry on the surfaces of a plurality of resin films (not shown). The ceramic green sheets50bare alternately laminated with the ceramic green sheets50a. The ceramic green sheets50aand50bmay preferably be prepared, for example, by a die coater, a gravure coater, a microgravure coater, or the like.

Next, as illustrated inFIG.5A, conductive paste that defines internal electrodes is printed in stripes on the surfaces of the ceramic green sheets50aand50b, and dried. The conductive paste that defines the internal electrodes includes Cu. Here, the direction in which the conductive paste that defines the internal electrodes extends in stripes is defined as an X direction, and the direction orthogonal or substantially orthogonal to the X direction on the ceramic green sheet is defined as a Y direction. Thus, conductive films52a(52b) to be the first internal electrodes13a(second internal electrodes13b) are formed. As the printing method, various methods, including screen printing, ink jet printing, gravure printing, and the like, may preferably be used.

Next, the prepared ceramic green sheets are laminated. Specifically, after a predetermined number of ceramic green sheets on which conductive films are not formed to be the outer layer portion22are laminated, the plurality of ceramic green sheets50aand50bon which the conductive films52aand52bare formed are laminated while being mutually shifted in the Y direction, as illustrated inFIG.5B. Then, a predetermined number of ceramic green sheets on which conductive films are not formed to be the outer layer portion22are laminated thereon to obtain a mother laminate.

Subsequently, the mother laminate is pressed by, for example, a method such as rigid press or isostatic press. Then, the pressed mother laminate is cut into a chip shape, so that a laminate chip60illustrated inFIG.6is provided.

As illustrated inFIG.6, only the conductive films52aof the ceramic green sheets50aare exposed at one end surface of the laminate chip60, and only the conductive films52bof the ceramic green sheets50bare exposed at the other end surface. Further, on both side surfaces of the laminate chip60, the conductive films52aof the ceramic green sheets50aand the conductive films52bof the ceramic green sheets50bare exposed.

Subsequently, ceramic green sheets that define side margin portions to be the side margin portions23are prepared. A compound including Ca, Zr, and Ti is prepared as a dielectric material for preparing a ceramic green sheet that defines a side margin portion. A ceramic slurry is prepared by mixing an additive including at least Si, an organic binder, an organic solvent, a plasticizer, and a dispersant in a predetermined ratio with dielectric powder obtained from the dielectric material. Subsequently, the ceramic green sheets that define the side margin portions are prepared with the prepared ceramic slurry.

Here, when the ceramic slurry is to be prepared, the content of Si included in the ceramic slurry that defines the outer side margin layer23ais adjusted to be larger than the content of Si included in the ceramic slurry that defines the inner side margin layer23b. Further, the ceramic slurry is applied so that the thickness of the ceramic green sheet that defines the outer side margin layer23ais larger than the thickness of the ceramic green sheet that defines the inner side margin layer23b.

Subsequently, the ceramic green sheet that defines an inner side margin layer is laminated and bonded onto the ceramic green sheet that defines an outer side margin layer to provide a ceramic green sheet that defines a side margin portion with a two-layer structure.

Subsequently, of the ceramic green sheets that defines a side margin portion, the ceramic green sheet that defines an inner side margin layer, and the side surface of the laminate chip60to which the conductive films52aand52bare exposed face each other, and pressing and punching are preformed, to thus form a layer to be the side margin portion23. A layer to be the side margin portion23is formed on the side surface on the opposite side by the same method or a similar method.

Subsequently, barrel polishing of the laminate chip on which the layer to be the side margin portion23is provided is performed. Then, the laminate chip is subjected to degreasing treatment under a predetermined condition in a nitrogen atmosphere, and then firing treatment is performed at a predetermined temperature in a nitrogen-hydrogen-steam mixed atmosphere. With this, a sintered laminate is provided.

Next, external electrode paste including Cu as a main component is applied and baked on each end surface of the sintered laminate to form the first base electrode layer141aconnected to the first internal electrodes13aand the second base electrode layer142aconnected to the second internal electrodes13b. Subsequently, the first lower plating layer141bis formed by Ni plating on the surface of the first base electrode layer141a, and the first upper plating layer141cis formed by Sn plating on the surface of the first lower plating layer141b. Accordingly, the first external electrode14ais formed. The second external electrode14bis formed by the same method or a similar method.

However, the laminate chip and the external electrode paste may be fired at the same time.

The multilayer ceramic capacitor10is prepared by the method described above. However, the manufacturing method described above is an example, and the method of manufacturing multilayer ceramic capacitor10is not limited to the manufacturing method described above.

The present invention is not limited to the preferred embodiment described above, and various applications and modifications may be applied within the scope of the present invention.

For example, although the side margin portion23is described as including the two side margin layers23aand23blaminated in the width direction W in the preferred embodiment described above, the side margin portion23may include one side margin layer or may include three or more side margin layers.

While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.