Patent ID: 12237310

The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not drawn to scale since the variation in size of various elements in the Figures is too great to permit depiction to scale.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

Embodiments of the present disclosure provide, among other things, a disaggregated multi-component transistor structure comprising one or more stacks of components electrically connected in parallel with component connections. Stacks of parallel-connected components can have a performance superior to a single larger component providing the same function and having the same structure and size. In some embodiments, the components are integrated circuits comprising transistors. In some embodiments, the components are micro-assemblies comprising a component substrate, bare die (e.g., unpackaged integrated circuits comprising one or more transistors), and electrical connections. Each transistor can comprise a gate controlling current flow through an interface (shown as a gate in the figures) between a source and drain. The interfaces of all of the transistors, taken together, can have an aggregated area or length equivalent to an interface area or length of a single, larger transistor, thus providing the same function and having substantially the same total structure and size. The disaggregated multiple components and component connections can have reduced resistive heating and improved conductivity and therefore can be more efficient and can operate at higher power levels and switching speeds than the single, larger transistor. The multiple components can each be a power transistor. To enable shorter component connections and reduced resistance in the parallel electrical connection connecting the components, the components can be provided in a stacked configuration of bare die with at least one component disposed on another component in a component stack, for example disposed on a support substrate.

According to embodiments of the present disclosure and as shown inFIGS.1A-1CandFIGS.2A-2D, a multi-component transistor structure99comprises separate and discrete components20each comprising a component transistor21comprising a transistor element40and a component connection30disposed external to transistor element40of each of components20on a support substrate10. Component connection30is not a part of component transistor21and is not a transistor element40. In some embodiments, at least some of component connection30is not physically in and is external to components20. In some embodiments, component connection30can be at least partially disposed within component20and can connect to transistor element40. In some embodiments, component connection30passes through components20. Each component20comprises a component transistor21comprising a transistor element40having a transistor element resistance and an individual, discrete, and separate component substrate56. Component transistor21can be native to component substrate56. Component substrate56can be a semiconductor substrate, for example a compound semiconductor substrate. Component connection30has a connection resistance and electrically connects transistor elements40in each of components20in parallel. The connection resistance can be less than the transistor element resistance of the corresponding transistor element40of at least one component transistor21of at least one of components20, the component transistors21are functionally similar, and at least one of components20is disposed on another different one of components20in a component stack28. Components20can comprise a dielectric or passivation layer disposed on a side of components20opposite component substrate56to provide electrical insulation and enable component stacking without electrical shorting. The components20are separate and distinct from each other. Functionally similar component transistors21have the same transistor40elements and perform the same function in an electronic circuit but may differ in size or shape or materials.

In some embodiments, the connection resistance is less than a sum of the transistor element resistances of components20. In some embodiments, the connection resistance is less than an average of the transistor element resistances of components20. In some embodiments, the connection resistance is less than at least one of the transistor element resistances (e.g., all of the transistor element resistances) of components20. In some embodiments, a resistivity (e.g., resistance per length or ohms per square) of connection resistance is less than a resistivity of the transistor element resistances of components20. In some embodiments, a length of component connection30(component connection length LCas shown inFIGS.3A,4A, and4B) is less than a length of at least one transistor element40(transistor element length LEas shown inFIGS.3A and5C). In some embodiments, a length LCof component connection30is less than an average or a sum of the lengths LEof transistor elements40of components20. In some embodiments, component connection length LCis longer than transistor element length LE) but has a lower resistance because component connection30comprises anyone or more of different materials, wider wires, or thicker wires. In general, for each process resolution there is an optimal transistor element length LEthat minimizes the drain-source resistance (RDSON), e.g., the lateral scaling limit. However, switching frequency requirements can also affect the desired transistor element length LE, so that the actual choice of transistor element length LE) and component connection length LCis a matter of design for a specific implementation.

In some embodiments and as shown inFIGS.1B and2B, each component transistor21can have multiple transistor elements40, for example a source22(e.g., an n- or p-doped semiconductor portion of component substrate56), a drain26(e.g., a p- or n-doped semiconductor portion of component substrate56), and a gate24(e.g., that can be an interface (illustrated as a rectangle for clarity) between source22and drain26) (each referred to as a transistor element40and collectively transistor elements40). Each transistor element40can be electrically connected with and comprise a transistor electrode41, for example a source electrode42, a gate electrode44, or a drain electrode46(collectively transistor electrodes41) that is in contact with the semiconductor portion of component substrate56and that can each comprise a portion of transistor element40. Thus, the transistor element resistance of transistor element40can include the resistance of transistor electrode41and the resistance of a corresponding semiconductor portion in contact with transistor electrode41. Transistor electrodes41can each be connected to a separate, discrete, and individual component connection30, for example so that sources22of component transistors21of components20are electrically connected in parallel and in common with a component source connection32, the gates24of component transistors21of components20are electrically connected in parallel and in common with a component gate connection34, and the drains26of component transistors21of components20are electrically connected in parallel and in common with a component drain connection36. Component source, gate, and drain connections32,34,36are generically referred to as component connections30.

Each component20can have a separate, discrete, and individual component substrate56, for example micro-transfer printed from a component source wafer onto support substrate10or onto other components20or layers (e.g., encapsulation or planarization layers70such as dielectric structures58) disposed on and insulating components20from electrical conductors such as component connections30or stacked component substrates56. As a consequence of micro-transfer printing, each component20can comprise a fractured component tether52. Each component20can be a singular, separate, distinct, and different unpackaged die98. The dies98can have a small thickness, for example from 2 to 20 microns, thereby enabling a dense configuration, efficient components20stacking, and short, low-resistance component connections30between components20in component stack28. Component transistor21can be a power transistor.

As shown inFIG.1A, according to some embodiments of the present disclosure, components20can have different sizes and are disposed in component stack28on support substrate10according to size with the largest component20disposed directly on or over support substrate10and successively smaller components20stacked in size order on or over the largest component20(e.g., in a direction orthogonal to a surface of support substrate10on which components20are disposed), so that the smallest component20is disposed farthest from support substrate10. Component stack28can be two components20high, three components20high, or four (or more) components20high. As shown inFIG.1B, some layers of component stack28comprise more than one component20. Each layer of component stack28can comprise the same number of components20(e.g., as shown inFIG.2Bfor an aligned component stack28, though some embodiments are unaligned) or have different numbers of components20(e.g., as shown inFIG.1B). In some embodiments, each successive layer of component stack28has a smaller number of components20forming an offset component stack28with a tiered structure so that the lowest layer has the largest number of components20and the top layer has the smallest number of components20, as shown inFIG.1B. The top layer can be a side of component stack28opposite support substrate10. Component stacks28of components20can enable a greater density of components20with shorter component connections30.

Components20in component stack28can be spatially offset with respect to one component edge, two component edges, three component edges, or four component edges (e.g., as shown inFIG.1Ain a wedding cake configuration) and hence can be aligned on three component edges, two component edges, one component edge, or no component edges, respectively. In some embodiments, as shown inFIG.1A, first component20A is disposed on support substrate10, second component20B smaller than first component20A is disposed on first component20A, and third component20C smaller than second component20B is disposed on second component20B.FIG.1Aillustrates a single first component20A, a single second component20B, and a single third component20C, wherein the first, second, and third components20A,20B,20C have different sizes. In some embodiments, as shown inFIG.1B, component stack28comprises multiple first components20A disposed in a first layer (a first row) on support substrate10, multiple second components20B disposed in a second layer (a second row) on the first layer of first components20A, and a third component20C disposed in a third layer on the second layer of second components20B. The first, second, and third layers of components20are spatially offset and thus components20are likewise offset. The first, second, and third components20A,20B,20C can have the same size, as shown inFIG.1B, or can be different sizes, as inFIG.1A.FIG.1Cshows an edge of spatially offset component stack28of transistor elements40and transistor electrodes41electrically connected with component connection30and insulated with dielectric structures58. Offset component stack28can expose at least a portion of transistor element40on an edge of each of components20and component connection30can be disposed at least partly along and in electrical contact with the exposed portion of transistor element40.

In some embodiments, as shown inFIGS.1A-1D, all of components20are disposed in component stack28, component stack28is an offset component stack28, and component connection30is disposed at least partly on an edge or exposed portion of components20. An offset component stack28can comprise one or more components20disposed in at least a first lower row of components20and a second upper row of one or more components20disposed on or over the first lower row of components20. In some embodiments, in an offset component stack28, either the second upper row comprises fewer components20than the first lower row or at least some components20in the second upper row are smaller than components20in the first lower row, for example exposing an edge of components20in the first row, or there are fewer components20that are also smaller. In some embodiments, one or more larger components20in one layer are disposed on multiple smaller components20in another layer, as shown inFIG.1D.

According to some embodiments, and as shown inFIGS.2A-2D, all of components20are not offset and are aligned with vertical edges, e.g., orthogonally with respect to a surface of support substrate10on which components20are disposed. In some embodiments, not shown in the Figures, components20are aligned on some edges and offset on other edges. As shown inFIGS.2A-2C, first, second, and third components20A,20B, and20C are disposed in an aligned component stack28. In some embodiments, multi-component transistor structure99comprises multiple aligned and adjacent component stacks28that share a common component connection30, for example as shown inFIG.2B.

In some embodiments, as shown inFIG.2C, components20are electrically connected with component connection30through component vias54. Since photolithographically constructed component transistors21are largely planar and components20according to embodiments of the present disclosure can have a relatively small component substrate56thickness, component connections30for a component stack28of components20that pass through or on the edge of component substrates56can be relatively short (and therefore a lower resistance and greater efficiency) compared to electrical connections disposed on support substrate10for components20that are not in a component stack28.

Component vias54can have a cross section aspect ratio taken in a plane parallel to a surface of support substrate10that is 1:1 (length to width). In some embodiments, and as shown inFIG.2D, the cross section aspect ratio of component vias54can be greater than one, for example two, four, eight, ten, or even more so that component connection30forms a wall through component20(through a portion of component substrate56). In some embodiments, for example, component vias54can have a size of about (e.g., within 10% of) or no more than 10 microns by 50, 100, 200, or 500 microns and a corresponding aspect ratio of about (e.g., within 10% of) or no more than 5, 10, 20, or 50. Such a high-aspect ratio component connection30can provide increased electrical conductivity and thermal conductivity and can also serve as an electromagnetic radiation shield that reduces electromagnetic interference between components20. Component vias54can be disposed in a center of components20or closer to a center of components20than to an edge of components20to facilitate routing of electrical connections between components20. In some embodiments, multiple component vias54are connected in parallel between components20.

Thus, according to some embodiments of the present disclosure, a semiconductor structure comprises a semiconductor substrate (e.g., component substrate56) having a first side and a second side, the second side on an opposite side of the semiconductor substrate from the first side, and a high-aspect-ratio via (e.g., component via54) formed in the semiconductor substrate that extends from the first side to the second side through the semiconductor substrate. The high-aspect-ratio via can have a high aspect ratio in a cross section of the high-aspect-ratio via parallel to the first side. The high-aspect-ratio via can comprise a dielectric surrounding a via conductor that can be a component connection30. Some embodiments comprise a circuit (e.g., component transistor21) formed in or on the first side of the semiconductor substrate and the via conductor can be electrically connected to the circuit. The high-aspect-ratio via can extend at least along a side of the circuit, for example no less than one half, one quarter, one eighth, or one sixteenth of the way along a side of the circuit, no less than one half, one quarter, one eighth, or one sixteenth of the way along two sides of the circuit, no less than one half, one quarter, one eighth, or one sixteenth of the way along three sides of the circuit, or no less than one half, one quarter, one eighth, or one sixteenth of the way along four sides of the circuit. In some embodiments, the high-aspect ratio via can extend three quarters or all of the way along a side of the circuit. Some embodiments comprise a plurality of separate high-aspect-ratio vias in one semiconductor substrate that can be disposed along one or more sides of the circuit, that are not in contact with each other, and can extend completely along each side of the circuit. Some embodiments comprise a plurality of separate semiconductor substrates disposed in a component stack28, each of the semiconductor substrates comprising a via conductor, and the via conductors of the separate semiconductor substrates are electrically connected. The via conductors can be vertically aligned in a direction orthogonal to the first side. The via conductors can extend between at least two semiconductor substrates beyond the high-aspect-ratio via and can provide additional shielding.

Each component20can comprise a transistor element40having a transistor element resistance, for example, but not necessarily, an ohmic resistance to the conduction of electrical current. Transistor element40can be a conductor, for example a wire or conductive area, for example comprising patterned metal, metal particles, or conductive polymers or conductive oxides, such as transparent conductive oxides, including ITO. Transistor element40can be a semiconductor, for example a doped semiconductor, such as a p-doped semiconductor or an n-doped semiconductor. Transistor element40can be a semiconductor in combination with a conductor disposed in electrical contact with the semiconductor. Transistor element40has a transistor element resistance, that is an electrical resistance to a flow of current (e.g., electrons or holes) along the extent of transistor element40.

Components20can comprise a bulk layer of a semiconductor (for example a compound semiconductor such as GaAs, GaN, InP or various binary, trinary, or quaternary compound semiconductors) comprising component substrate56and a doped or implanted portion of the bulk layer forming component transistor21and transistor elements40. (For clarity, in the Figures the bulk semiconductor comprising component substrate56is shown as thinner or smaller than transistor elements40, but in practice can be much thicker or larger than transistor elements40.) Transistor electrodes41can be metal or semiconductor materials (e.g., doped semiconductor materials) or combinations thereof in transistor element40for conducting electrical current to source, gate, or drain22,24,26. Gate24can be a gate electrode44(e.g., a transistor electrode41). Components20, component transistors21, transistor elements40, transistor electrodes41, and component connection30can be constructed using photolithographic methods and materials.

In some embodiments, a thickness or width of component connection30is greater than a thickness or width of transistor elements40or transistor electrodes41of component transistor21of components20. Component connection30can comprise different materials than transistor elements40or transistor electrodes41of component transistor21of components20. In some embodiments, component connection30has a lower resolution than a resolution of transistor element40and can be made in a different process or with different process limitations, for example transistor element40can have a finer resolution with smaller features or feature separation than component connection30.

Component connections30are electrically connected to respective transistor elements40of each component20in parallel. Thus, if component20comprises first, second, and third transistor elements40(e.g., source, gate, and drain22,24,26), a first component connection30is electrically connected in parallel to first transistor element40of all of components20in multi-component transistor structure99so that first component connection30is electrically connected in parallel to every first transistor element40in multi-component transistor structure99, a second component connection30is electrically connected in parallel to second transistor element40of all of components20in multi-component transistor structure99so that second component connection30is electrically connected in parallel to every second transistor element40in multi-component transistor structure99, and a third component connection30is electrically connected in parallel to third transistor element40of all of components20in multi-component transistor structure99so that third component connection30is electrically connected in parallel to every third transistor element40in multi-component transistor structure99. First, second, and third component connections30are separate and distinct electrical conductors.

In some embodiments, a respective connection resistance of each component connection30(e.g., the resistance of component connection30) is less than the corresponding transistor element resistance of at least one component transistor21, less than an average of the corresponding transistor element resistances of component transistor21of components20, or less than a sum of the corresponding transistor element resistances of component transistor21of each of components20. A resistivity of the component connection30can be less than a resistivity of the transistor element40of components20. Resistivity can be a resistance per length or ohms per square of connection resistance and transistor element resistance. Thus, using the example above, the connection resistance of first component connection30can be less than, less than an average of, or less than a sum of the transistor element resistances of first transistor elements40of all of components20connected by first component connection30, the connection resistance of second component connection30can be less than, less than an average of, or less than of a sum of the transistor element resistances of second transistor elements40of all of the components20connected by second component connection30, and the connection resistance of third component connection30can be less than, less than an average of, or less than a sum of the transistor element resistances of third transistor elements40of all of the components20connected by third component connection30.

A material, material thickness, or material width of component connection30can be different from a material or material thickness of transistor element40. In some embodiments, the material of component connection30is more conductive (e.g., has a greater conductivity) than a material of respective transistor element40to which component connection30is electrically connected. In some embodiments, a material thickness of component connection30is greater than a material thickness of transistor element40to which component connection30is electrically connected. In some embodiments, a material width of component connection30is greater than a material width of transistor element40to which component connection30is electrically connected. Thus, in some embodiments, component connections30are more conductive than transistor elements40, e.g., have a lower resistivity per length or ohms per square.

Component connection30has a connection resistance, for example but not necessarily, an ohmic resistance that is an electrical resistance to a flow of current (e.g., electrons or holes). Component connection30includes only those portions of a conductor that electrically connect transistor elements40of components20in common (e.g., see conductor80inFIG.16for portions of a conductor that are not included in component connection30) and the connection resistance is the resistance to current flow through all of the necessary portions. For example, component connection30can be electrically connected to an external controller or external circuit (not shown), but those portions of conductor80electrically connected to the external controller are not necessary to electrically connect transistor elements40of components20in common and are therefore not portions of component connection30. Similarly, the transistor element resistance is the resistance to current flow through the entire transistor element40. According to some embodiments of the present disclosure, the connection resistance of component connection30is less than, less than the average, or less than the sum of the transistor element resistances of elements40of each of the components20. Where one or both of the element or common transistor element resistances vary as a function of operation, the element or common resistances are measured under the same operating conditions.

In some embodiments of the present disclosure, a length of component connection30is less than a length of the transistor element40in a component20, is less than an average of the lengths of the respective corresponding transistor elements40in the components20, or is less than a sum of the lengths of the respective corresponding transistor elements40in the components20, e.g., the corresponding transistor elements40in the components20to which the component connection30is connected.

FIGS.3A-3Eillustrate embodiments of a multi-component transistor structure99comprising components20in a row or layer on support substrate10and electrically connected in parallel with component connections30, e.g., corresponding to a layer or row inFIG.1B. Each component20comprises one or more transistor elements40each having a respective transistor element resistance. Thus, each transistor element40of a component20has a transistor element resistance. The transistor element resistance is the resistance of the entire transistor element40, for example the sum of the resistances of all of any portions of transistor element40. A substantially linear transistor element40can have a transistor element resistance per length (e.g., ohms per square) that, when multiplied by the linear transistor element40length, can substantially equal the transistor element resistance.

FIG.3Ais a plan view of a multi-component transistor structure99comprising multiple component connections30electrically connecting transistor elements40of component transistors21in components20comprising component transistors21disposed in a row or layer. (FIGS.3A-3Eshow only one row or layer of components20but some embodiments of the present disclosure include multiple rows or layers in a component stack28, for example as shown inFIGS.1A-2C.) As shown inFIGS.3B and3C, each component20has or comprises a separate, discrete, distinct, different, and individual component substrate56(e.g., has or comprises a separate, discrete, distinct, different, and individual die98) and some components20can be formed in or disposed on (e.g., directly on and in contact with) or over a support substrate10or layers disposed on support substrate10.

As shown inFIGS.3D and3E, in some embodiments components20share a common component substrate57and components20can be disposed directly on and in contact with common component substrate57or can be constructed on or in (e.g., native to) common component substrate57. According to some embodiments of the present disclosure, components20that share a common component substrate57are or comprise a single, unpackaged bare die98, chiplet, or micro-chiplet, and can be a micro-transfer-printable or -printed unit, structure, or device, for example micro-transfer printed with a single post of a transfer-print stamp and are therefore not native to common component substrate57. Thus, a single unpackaged bare die98, chiplet, unit, or device can comprise a single component20(as shown inFIGS.3A-3C) or can comprise a group of components20(as shown inFIGS.3D-3E). Each die98, if micro-transfer printed, can comprise a broken (e.g., fractured) or separated component tether52or, if disposed on a component source wafer60(a component source substrate), can comprise a component tether62(seeFIGS.10A,10Bdiscussed below) that is not broken (e.g., fractured) or separated.

A multi-component structure99can comprise a plurality of component20groups sharing a common component substrate57and interconnected with component connections30(e.g., as shown inFIGS.3D and3E). Some such embodiments can provide improved component20packing density. Portions or all of component connection30disposed on common component substrate57can be constructed with relatively fine (high-resolution) processes (e.g., made using front-end-of-line processes), improving packing density, and portions of component connections30providing electrical connections between groups of components20sharing a common component substrate57can be made at relatively coarse (low-resolution) processes (e.g., back-end-of-line processes) with wider, thicker or wider and thicker lines to improve electrical conductivity and reduce thermal resistance. In some designs it can be preferable to make the high-resolution portions of component connections30relatively shorter and the low-resolution portions relatively longer to reduce the overall resistance and parasitic capacitance and parasitic inductance of the component connections30. If desired, component substrates57can be spaced farther apart than components20sharing common component substrate57. In some designs, using unpackaged die micro-assembled using micro-transfer printing provides twice the component source wafer60utilization (reducing costs by one half) and using multiple common component substrates57can reduce costs by a factor of22. Furthermore, component20groups sharing a common component substrate57can be tested before micro-assembly to ensure known good die thereby increasing yields.

FIGS.3A-3Eillustrate a multi-component transistor structure99according to embodiments of the present disclosure in which each component20comprises multiple transistor elements40each with its own transistor element resistance. Each transistor element40in a component20can have a different transistor element resistance, or some or all of the transistor element resistances can be the same. As illustrated inFIGS.3A-3E, in some embodiments, component20is a component transistor21, and each component transistor21has multiple transistor elements40, for example a component transistor21can comprise a transistor element40that is a source22having a source resistance, a transistor element40that is a gate24having a gate resistance, and a transistor element40that is a drain26having a drain resistance. The sources22of each component20in multi-component transistor structure99are electrically connected with a component connection30that is a component source connection32, the gates24of each component20in multi-component transistor structure99are electrically connected with a component connection30that is a component gate connection34(shown with a dashed connection inFIG.3Aand not shown inFIG.3B), and the drains26of each component20in multi-component transistor structure99are electrically connected with a component connection30that is a component drain connection36(not shown inFIG.3B). All of component connections30(e.g., component source connection32, component gate connection34, and component drain connection36) are shown inFIG.3A, only the component source connection32is shown inFIGS.3B and3D, and the component connections30are all omitted for clarity inFIGS.3C and3E.

FIG.3Ais a plan view that illustrates a multi-component transistor structure99that has four components20, each a component transistor21with three transistor elements40(source22, gate24, and drain26) of each component transistor21electrically connected in common with a component connection30(where component connection30refers generically to each of component source connection32, component gate connection34, and component drain connection36). Each of source22, gate24, and drain26(transistor elements40) (for a given component20) have a length LE. Components20(e.g., component transistors21) are disposed on a support substrate10, have a width W, and adjacent components20are separated on support substrate10by a separation S distance that can be less than width W, providing a dense arrangement of components20on support substrate10enabled by bare die98components20. Component connections30can be likewise disposed on support substrate10and each have a component connection length LC(as discussed further below with respect toFIGS.4A and4B).FIGS.3B and3Dare perspectives illustrating components20(e.g., component transistors21) disposed on support substrate10and component source connection32.FIGS.3C and3Eare cross sections taken along cross-section line A ofFIGS.3A,3B, and3Dand shows each of the four individual components20(e.g., component transistors21) disposed on support substrate10. InFIGS.3A-3E, stacked components20are omitted for clarity.

According to some embodiments of the present disclosure, a connection resistance of component connection30is less than, less than the average of, or less than the sum of the transistor element resistances of the same transistor elements40of components20(e.g., taken from connection points R1to R2inFIG.3A). Where components20have multiple transistor elements40, the combined transistor element resistances are of corresponding transistor elements40. As shown inFIG.4A, in some embodiments, component connection30(e.g., corresponding to any of the component source, gate, or drain connections32,34,36) comprises five portions, P1, P2, P3, P4, and P5. As shown inFIG.4B, the connection resistance is the resistance of all five portions P1, P2, P3, P4, and P5serially connected together, that is from connection points R1to R2inFIG.4B(different from connection points R1and R2inFIG.3A). The combined length of the five portions, P1, P2, P3, P4, and P5is LC, the length of component connection30. Similarly, the length LEof transistor element40is the sum of all portions of transistor element40and the transistor element resistance is the resistance of all transistor element40portions electrically connected in serial. In embodiments in accordance withFIG.3A, transistor element40is linear between connection points R1and R2but in some embodiments, for example as shown inFIG.5A, transistor element40can be serpentine, comprise multiple segments, or comprise curves. Thus, according to some embodiments of the present disclosure and as illustrated inFIGS.3A-3E,4A, and4B, the connection resistance is less than, less than the average of, or less than the sum of the transistor element resistances of corresponding transistor elements40. In theFIGS.3A-4Bexample, the sum of the transistor element resistances of corresponding transistor elements40is equal to four times the transistor element resistance of the length LEfrom connection points R1to R2(inFIG.3A) of transistor element40. (In this illustration, component connection30can be any one of component source connection32, component gate connection34, or component drain connection36and transistor element40can be the corresponding source22, gate24, or drain26.)

According to some embodiments of the present disclosure, component connection30comprises a different material or has a different material thickness than transistor element40. For example, transistor element40can be or include a doped semiconductor or an aluminum conductor. As an example, component connection30can be copper. For example, transistor element40can have a thickness less than two microns and component connection30can have a thickness greater than two microns.

As shown inFIG.5A, a transistor can be serpentine, for example a source, gate, or drain22,24,26of a serpentine transistor90each with a connected source, gate, or drain electrode42,44,46, respectively, provided, for example, in a die98. As shown inFIG.5B, an interdigitated transistor92can comprise interdigitated sub-transistors electrically connected in parallel, each having a source, gate, or drain22,24,26each with a connected source, gate, or drain electrode42,44,46, respectively, provided, for example, in a die98. (Drain electrode46is not shown inFIG.5Bbut electrically connects each of the drains26, for example through vias or in a different interconnect or metal layer).FIG.5Cillustrates an electrically equivalent linear transistor for serpentine transistor90inFIG.5Aor each interdigitated sub-transistor of interdigitated transistor92inFIG.5B. The transistor element resistance is the resistance of the transistor element40along the length of transistor element40(transistor length LT) forming at least a portion of component20, for example from connection points R1to R2, and, in these examples, at least a portion of component transistor21. For illustration as shown inFIG.5Cand corresponding to the illustration ofFIGS.3A-4B, transistor element40of component transistor21is divided into four (arbitrarily selected) serially connected portions P1-P4comprising transistor length LT. In some embodiments of the present disclosure, each of the four portions P1-P4is provided as a component20having a transistor element40(any one of source22, gate24, or drain26) as shown inFIGS.3A-3Cand electrically connected with a component connection30. As shown inFIG.5C, current provided by the source and drain electrodes42,46and controlled by a voltage provided through the gate electrode44passed through the interface between the source22and drain26of portion P1does not experience any additional resistance from portions P2-P4. However, the current passing through the source/drain interface of portion P2must pass through P1. The current passing through the source/drain interface of portion P3must pass through P1and P2and current passing through the source/drain interface of portion P4must pass through portions P1, P2, and P3, so that the current passing through the portions P2, P3, and P4experiences resistive losses and heat generation.

Comparing the electrical current flow and resistance ofFIGS.5A and5B, with the disaggregated component transistor21ofFIGS.3A-2C, there is no current resistive loss or heat generation in each of the transistor elements40of components20specifically due to other transistor element40portions (e.g., where each disaggregated component transistor21transistor element40corresponds to a portion). However, there is current loss and resistive heating within the component connection30ofFIGS.3A-2Cdue to the connection resistance, but this current loss and resistive heating can be less than the current loss and resistive heating due to portions P2-P4in a conventional transistor. Therefore, according to some embodiments of the present disclosure, as long as the connection resistance is less than, less than an average of, or less than the sum of the transistor element resistances of the corresponding transistor elements40within the components20, the multi-component transistor structure99ofFIGS.3A-4Bwill provide a performance advantage of reduced resistive heating, providing improved efficiency, switching rates, and reduced resistive, capacitive, or inductive parasitic losses, for example switching losses. In turn, such improvements provide an increased power density, peak voltage, and current in multi-component transistor structure99.

Since component connection30can be constructed externally to component20or transistor element40, it can be made, in various embodiments, with more conductive materials, wider materials, or thicker materials, or have a shorter length, as illustrated, all of which provide reduced resistance, reduced heating, improved switching rates, and reduced parasitics (e.g., resistive, capacitive or inductive parasitics) in multi-component transistor structure99. Component connection30can also be constructed at a lower resolution than component20, saving manufacturing costs. A device resolution is the smallest dimension parallel to a substrate surface (e.g., x and y dimensions but not z dimension) of the device or the smallest separation between devices, whichever is smaller. The resolution of component20is the resolution of a transistor element40in component20. Component connection30can also be constructed separately from component20, in a different process, with different materials, at a separate time, and disposed externally to component20.

For ease of understanding, the examples ofFIGS.4A,4B, and5Carbitrarily use an illustration with four portions, but in an actual implementation, the increase in resistance along a length LEof transistor element40is continuous. Mathematically, the transistor element resistance for linear structures connected at one end can be computed as the integral of the element length LEor ½ kx2(where x is the element length LEand k is the resistance in ohms per square of transistor element40) and the connection resistance y is similar. This is equivalent to the area under a line with a slope k that extends from zero to the transistor element length LEof transistor element40or component connection length LCcomponent connection30. For a multi-component transistor structure99with four components20as inFIGS.3A-4Bwhere the resistance of transistor element40is arbitrarily chosen to be twice the resistance of component connection30and four portions of the equivalent structure inFIGS.5A,5B), the structure ofFIGS.5A-5Chas a transistor element resistance of sixteen (one half of four squared times2) and the multi-component transistor structure99ofFIGS.3A-4Bhas a transistor element resistance of two (four times one half of one squared) times one.

FIGS.6A-6Cgraphically illustrate the calculation. Assuming that the length of component connection30is the same as the length of transistor element40(transistor element length LEand arbitrarily selected as one) and that the resistance of transistor element40is twice that of component connection30, the shaded area under the line inFIG.6Aillustrates the connection resistance equal to ½ or (½×12)×1 (where the x axis represents the element length LEequal to one, k is the resistance in ohms per square of transistor element40equal to 2, and the y axis equals f(x)=½kx2). As shown inFIG.6B, the transistor element resistance equals 1 or (½×12)×2. In comparison, a corresponding non-disaggregated device, illustrated inFIG.6C, has a resistance of sixteen or (½×42)×2.FIG.6Dillustrates the difference in area between four transistor elements40(as shown inFIG.6B) and one non-disaggregated device as shown inFIG.6C.

The multi-component transistor structure99ofFIGS.3A-4Balso has component connection30losses from the connection resistance, calculated as ½ above. The net resistance of multi-component transistor structure99for a given component connection30and transistor element40is thus (number of transistor elements40times transistor element resistance) plus connection resistance, or (four times one) plus ½, equal to 4.5, compared to sixteen as noted above. Thus, a performance improvement factor can be 16/4.5 or about 3.56.

Following this illustrative example, the performance of multi-component transistor structure99can be modeled as:LT=length of transistor (e.g.,FIG.5C);N=number of transistor elements40(e.g.,4,FIGS.3A-3E);LE=length of transistor element40equal to LT/N (e.g.,FIG.3A);LC=length of component connection30(e.g.,FIGS.3A-3D,4B);Transistor element resistance E=½(LE2)R=½R(LT/N)2;Relative resistance R=transistor element resistance per/connection resistance per;Transistor resistance T=½(LT2)×R;Connection resistance C=½(LC2);Multi-component resistance M=(N×E)+C; andPerformance factor P=T/M=(½(LT2)R)/((N×½(LT/N)2×R)+½(LC)2).

For the example above, LT=4, N=4, LC=LE=1, R=2, so that:
P=(½(42)2)/((4×½×2)+½(1)2=16/(4+½)=16/4.5=3.56.

In general, the performance factor P is improved by increasing N (the number of components20and thereby decreasing the length LEof each transistor element40in components20), by decreasing LC(the length of component connection30length), and by decreasing R (the resistance of component connection30). However, as N is increased, it is likely that LCwill also increase, so that an actual performance factor P will be a matter of design choice. It is helpful to pack components20as closely together as is possible to meet design goals since a dense arrangement of components20can also reduce LC, for example by reducing component separation distance S with respect to component width W. R can be reduced by improving the conductivity of component connection30, for example by using thick and conductive materials such as copper or gold. In embodiments in which component20comprises multiple transistor elements40, a performance factor P can be obtained for each transistor element40in component20, further improving the overall performance of multi-component transistor structure99.

Thus, according to some embodiments of the present disclosure, a multi-component transistor structure99comprises stacked components20having component transistors21electrically connected in parallel, each of component transistors21comprising at least a transistor element40having a transistor element resistance, and a component connection30electrically connected to transistor element40of each component20. A material, material width, or material thickness of component connection30can be different from a material, material width, or material thickness of transistor element40. Component connection30has a connection resistance and transistor element40has a transistor element resistance. An integral of a connection resistance function taken over a length of component connection30is less than an integral of a transistor element resistance function taken over a sum of the lengths of transistor elements40, the connection resistance function is f(x)=CRXwhere CR=(the connection resistance divided by a length of component connection30), and the transistor element resistance function is f(x)=ERXwhere ER=(the transistor element resistance divided by a transistor length LT).

In some embodiments, components20can be disposed closely together, for example separated by a separation distance S that is less than a width W of components20(as shown inFIGS.3A-3Eand made possible by using bare die98components20). This enables a short component connection30so that according to some embodiments of the present disclosure, a multi-component transistor structure99comprises components20electrically connected in parallel, each of components20comprising at least a transistor element40and a component connection30electrically connected to transistor element40of each component20. A material, material width, or material thickness of component connection30can be different from a material, material width, or material thickness of transistor element40.

The length of component connection30can be less than transistor length LTtimes the number of components20. Thus, in some embodiments of a multi-component transistor structure99, a length of component connection30is less than a sum of the lengths of transistor elements40of components20, is less than an average of the lengths of transistor elements40of components20, is less than the longest length of any transistor element40of components20, or is less than the shortest length of any transistor element40of components20. A shorter component connection30has reduced resistive and parasitic losses in multi-component transistor structure99providing improved efficiency.

Groups of multi-component transistor structures99can be provided and electrically connected together. In some embodiments, the group itself is a multi-component transistor structure99, for example where a group component connection30comprises a combination of each of component connections30of each multi-component transistor structure99together and the connection resistance is the resistance of the group component connection30and the sum of the transistor element resistances is the sum of all of transistor elements40of components20in each of the multi-component transistor structures99. In other embodiments, the group of multi-component transistor structures99is not itself a multi-component transistor structure99.

As discussed above, each of components20can include one or more component transistors21, for example field-effect transistors (FETs), power transistors, or radio frequency (RF) transistors, or any one or combination thereof, and can be applied, for example, in power amplifiers in mobile devices or in automotive applications. Component transistors21can have multiple transistor elements40, e.g., a source22, gate24, and drain26, each with an electrically separate component connection30, e.g., a component source connection32electrically connected to source22of components20, a component gate connection34electrically connected to gate24of components20, and a component drain connection36electrically connected to drain26of components20. In some embodiments, component gate connection34is more conductive than a conductivity of gate24of any of component transistors21, component source connection32is more conductive than a conductivity of source22of any of component transistors21, or component drain connection36is more conductive than a conductivity of drain26of any of component transistors21, or any combination thereof. In some embodiments, component gate connection34is shorter than a gate24length of any of component transistors21, component source connection32is shorter than a source22length of any of component transistors21, or component drain connection36is shorter than a drain26length of any of component transistors21, or any combination thereof. In some embodiments, component gate connection34is shorter than a sum of gate24lengths of component transistors21, component source connection32is shorter than a sum of source22lengths of component transistors21, or component drain connection36is shorter than a sum of drain26length of component transistors21, or any combination thereof.

In some embodiments, source22of each component transistor21comprises a source material and component source connection32comprises an electrical conductor material that is different from the source material, drain26of each component transistor21comprises a drain material and component drain connection36comprises an electrical conductor material that is different from the drain material, or both. In some embodiments, component source, gate, and drain connections32,34,36are first component source, gate, and drain connections32,34,36and components20comprise second component source, gate, and drain connections32,34,36, for example as shown inFIG.20, connected at both ends of linear source22, gate24, and drain26of component transistor21. InFIG.20, component connections30at each end of each transistor element40(e.g., source, gate, and drain electrodes42,44,46) are electrically connected in common (not shown) and are at least a portion of the corresponding component source, gate, and drain connections32,34,36. Because the source, gate, and drain22,24,26are electrically connected at both ends, their effective length is one half that of a source, gate, and drain22,24,26connected at only one end.

Thus, according to embodiments of the present disclosure, a multi-transistor structure99comprises a plurality of stacked component transistors21electrically connected in parallel, each component transistor21comprising at least a gate24having a gate resistance, a source22having a source resistance, and a drain26having a drain resistance. A component gate connection34is electrically connected to gates24of each component transistor21at two or more locations, a component source connection32is electrically connected to source22of each component transistor21at two or more locations, and a component drain connection36is electrically connected to drain26of each component transistor21at two or more locations. Any one or combination of a material, material width, or material thickness of component source connection32can be different from a material, material width, or material thickness of source22or source electrode42, a material, material width, or material thickness of component gate connection34can be different from a material or material thickness of gate electrode44, and a material, material width, or material thickness of component drain connection36can be different from a material or material thickness of drain26or drain electrode46.

In some embodiments, the resistance of component source connection32is less than, less than the average of, or less than the sum of the source resistances of the component transistors21, the resistance of the component drain connection36is less than, less than the average of, or less than the sum of the drain resistances of component transistors21, the resistance of component gate connection34is less than, less than the average of, or less than the sum of the gate resistances of component transistors21, or any combination thereof. In some embodiments, an integral of the connection resistance of component source connection32, taken over the length of component source connection32is less than an integral of the source resistance taken over a length of source22, an integral of the connection resistance of component gate connection34taken over the length of component gate connection34is less than an integral of the gate resistance taken over a length of gate24, or an integral of the connection resistance of component drain connection36taken over the length of component drain connection36is less than an integral of the drain resistance taken over a length of drain26, or any combination thereof. For example, an integral of a source connection resistance function taken over a length of component source connection32can be less than an integral of a source resistance function taken over a sum of the lengths of sources22; the source connection resistance function can be f(x)=CRXwhere CR=(a resistance of component source connection32divided by a length of component source connection32), and the source resistance function is f(x)=ERXwhere ER=(source resistance divided by a length of source22). An integral of a gate connection resistance function taken over a length of component gate connection34can be less than an integral of a gate resistance function taken over a sum of the lengths of gates24; the gate connection resistance function can be f(x)=CRXwhere CR=(a resistance of component gate connection34divided by a length of component gate connection34), and the gate resistance function is f(x)=ERXwhere ER=(gate resistance divided by a length of gate24). An integral of a drain connection resistance function taken over a length of component drain connection36can be less than an integral of a drain resistance function taken over a sum of the lengths of drains26; the drain connection resistance function can be f(x)=CRXwhere CR=(a resistance of component drain connection36divided by a length of component drain connection36), and the drain resistance function is f(x)=ERXwhere ER=(drain resistance divided by a length of drain26).

As illustrated inFIGS.7A-8Cand also with reference toFIGS.1A,1B,2A, and2B, components20can be disposed individually or in a row or layer on support substrate10. Rows of components20can be disposed on each other in layers, as shown, to form a stacked configuration with excellent density and short component connections30. As shown inFIGS.7A,1B,2A, and2B, each component20is substantially (within manufacturing tolerances) the same size and the layers of components20have the same number of components20. As shown inFIGS.7B and1A, components20can have different sizes. First component20A is the largest and is disposed on support substrate10, second component20B is slightly smaller than first component20A and is disposed on first component20A, and third component20C is the smallest and is disposed on second component20B. Components20in a component stack28can be successively smaller in length, in width (as shown inFIG.7B), or in both length and width, as shown in the perspective ofFIG.1A. By using increasingly smaller components20in component stack28, connections to components20in component stack28can be facilitated, as discussed further with respect toFIGS.18A-18Cbelow. Component stacks28illustrated inFIGS.2A,2B, and7Aare aligned component stacks28. Component stacks28illustrated inFIGS.7B,1A, and1Bare offset component stacks28.

As illustrated inFIGS.8A-8C, components20can be the same size (e.g., as inFIG.7A) and component stack28can be offset, with each successive layer comprising a successively smaller number of components20, forming a step pyramid of components20. Such an offset component stack28can have simpler component connections30(as illustrated and discussed further below with respect toFIG.15).FIG.8Aillustrates a two-layer offset component stack28with the upper layer having a single component20,FIG.8Billustrates component stack28with a center location in a second layer devoid of a component20, andFIG.8Cillustrates a three-level or three-layer structure offset component stack28of components20. Component20stacks illustrated inFIGS.8A,8B, and8C are offset component stacks28.

Components20can each be individually disposed on support substrate10by micro-transfer printing, for example as individual die98or units. In some embodiments, multiple components20are disposed on support substrate10as a single die98and transfer printed as a single die98to form each row (or a portion of a row) within a stacked structure on support substrate10. Where a multi-component transistor structure99comprises stacked components20or rows of components20, either components20comprising individual dies98or multiple components20comprising a single die98can be micro-transfer printed on top of pre-disposed components20to form component stack28(or a portion thereof).

As shown inFIGS.9A and9B, a heat conductor14can be disposed on support substrate10and extend beneath one or more of components20to transfer heat from components20and improve cooling of the structure. For clarity,FIGS.9A and9Bomits component connections30.

As is also shown inFIGS.9A and9B, support substrate10can comprise an electronic circuit12connected to components20with vias formed through heat conductor14(not shown inFIGS.9A-9B). Electronic circuit12can be disposed in or on support substrate10. Components20can be disposed on (e.g., directly on or over) electronic circuit12and can be electrically connected to electronic circuit12. Electronic circuit12can control or respond to components20or provide signals or power and ground to components20. For example, electronic circuit12can be a power FET control circuit. Support substrate10can be a semiconductor substrate such as silicon and electronic circuit12can be a digital, analog, or mixed signal circuit, for example comprising CMOS transistors. Thus, some embodiments of a multi-component transistor structure99comprise a silicon support substrate10comprising an electronic circuit12that is electrically connected to any combination of component source connection32, component gate connection34, and component drain connection36.

Although component substrates56can have a common origin and materials (e.g., component source wafer60), when transferred to support substrate10(e.g., by micro-transfer printing from component source wafer60and forming fractured or separated tethers52), component substrates56are completely separated, discrete, distinct, and individual and are separated on support substrate10by separation distance S (shown inFIGS.3A-3C). Once components20are disposed on support substrate10, component connections30can be disposed and patterned on components20and the common semiconductor substrate, for example using any one or combination of different materials, different material thicknesses, and different processes (e.g., as illustrated inFIGS.3A-3E). In some embodiments, component connections30are constructed at a different resolution from structures in components20or transistor elements40, for example using different process methods or materials, or both. Support substrate10can be diced or, if part of a support substrate source wafer, micro-transfer printed with multi-component transistor structure99into an external structure, such as a desired product or system.

Components20can be made in or comprise a substrate such as a semiconductor substrate or compound semiconductor substrate, for example a III/V compound semiconductor such as GaN or GaAs or a II/VI compound semiconductor. Thus, each of components20can comprise a component substrate56comprising a component material (e.g., GaN or GaAs) that is different from a support substrate10material (e.g., silicon or glass). Components20can be substantially identical in function, size, and shape, or have different sizes or shapes. By substantially identical is meant designed to be and operate the same within the constraints of a manufacturing process. Components20can be chiplets or micro-chiplets and can comprise bare die98that are not provided in a package with additional electrical connections to transistor elements40in components20(e.g., bond wires connected to pins). Such bare die98components20reduce costs and improve performance, as well as component density. Bare die98can be processed on support substrate10, for example using photolithographic materials and methods, to provide, for example insulating dielectric structures58, conductors such as component connections30, or other useful circuit structures.

In some embodiments and as shown inFIG.10A, components20can be formed in a component source wafer60that includes a wafer of source substrate material having a patterned sacrificial layer68that is formed on or in the source substrate material or that is a designated portion of the source substrate material (e.g., an anisotropically etchable portion). Component transistors21can comprise semiconductor materials as well as dielectric structures58, conductors, vias, and other structures useful in integrated circuits that can be formed using photolithographic methods and materials. Patterned sacrificial layer68defines separate anchors64between sacrificial portions66of the patterned sacrificial layer68. Each component20can be disposed over a separate sacrificial portion66and attached to anchors64by one or more component tethers62over sacrificial portion66. Such components20can be micro-transfer printed to support substrate10, as shown inFIGS.3B and3C, and can comprise fractured or separated tethers52(e.g., as shown inFIG.3C) when micro-transfer printed.

As shown inFIG.10B, a group of components20(for example forming a multi-component transistor structure99) sharing a common component substrate57can be formed or disposed over each sacrificial portion66of sacrificial layer68and attached to anchors64by one or more component tethers62over sacrificial portion66. Such multi-component transistor structures99can be micro-transfer printed as a component to support substrate10, as shown inFIGS.3D and3E, and can comprise broken (e.g., fractured) or separated tethers52(FIG.3D).

As shown in the detail ofFIG.11Aand system ofFIG.11B, component transistors21can be electrically connected to connection posts50with component connections (e.g., component source, gate, and drain connections32,34,36) and can be micro-transfer printed from component source wafer60using a stamp to adhere components20and remove components20from component source wafer60, fracturing component tethers62to form fractured tethers52, and printed onto support substrate10to contact connection posts50to contact pads16on support substrate10. In some embodiments, component connections30are electrically connected to contact pads16using photolithographic methods and materials. Contact pads16can be electrically connected to electronic circuit12, so that electronic circuit12is electrically connected to components20.

As shown inFIG.12, components20with connection posts50can be constructed on a component source wafer60by etching forms into sacrificial layer68, patterning the forms with a conductor such as metal, disposing a component substrate56over the patterned conductor, forming component vias54through component substrate56and electrically connecting connection posts50through component via54to respective component source, gate, and drain connections32,34,36. Dielectric structures58can insulate semiconductor materials from electrodes and component20can be protected by encapsulation layer70(or a planarization layer70). Once formed, sacrificial portion66can be etched to form a gap between component20and component source wafer60to release component20from component source wafer60so that component20is held in position and suspended over component source wafer60by component tether62and anchor64, breaking (e.g., fracturing) or separating component tether62. Component20can then be micro-transfer printed with connection posts50using a stamp. Micro-assembly and photolithographic processes performed on support substrate10at a lower resolution can be less expensive than photolithographic processes performed at a higher resolution in an integrated circuit, for example panel processing is less expensive than wafer processing.

In some methods of the present disclosure illustrated inFIGS.21-24, a multi-component transistor structure99is constructed by providing a component source wafer60in step100and constructing components20in step110, for example using integrated circuit process methods and materials, such as photolithography in a semiconductor foundry. Each component20can comprise or be disposed on an individual, discrete, distinct, and different component substrate56and die98(e.g., as shown inFIG.10A) or components20can comprise or be disposed on or in a common die57such as a common semiconductor substrate (e.g., common component substrate57shown inFIG.10B), such as a compound semiconductor substrate. In step120, component connections30are disposed and patterned on components20and semiconductor substrate56or common semiconductor substrate57, for example using any one or combination of different materials, different material thicknesses, and different processes. In step130, components20connected with component connections30on common semiconductor substrate57are integrated into a desired system.

In some embodiments, and as shown inFIGS.22-24, support substrate10is provided in step140and each component20is removed from the common semiconductor substrate (e.g., component source wafer60) in step150, for example by micro-transfer printing, and transferred to a support substrate10. In some embodiments, each component20can comprise or be formed in or on and native to a separate and component substrate56, for example an individual and discrete die98and can be transfer printed with a single stamp post. In step120, component connections30are constructed and, in step130, components20connected with component connections30can be integrated into a desired system.

FIGS.23and24illustrate successive transfer steps useful for constructing a stacked arrangement of components20. As shown inFIG.23, after a first set of components20(e.g., a first row of components20) are disposed onto support substrate10(step150) and electrically connected in parallel with component connection30(step120), a second set of components20(e.g., a second stacked row of components20) are disposed onto the first set of components20(step152) and electrically connected in parallel with component connection30(repeated step120). As shown inFIG.24, a first set of components20are printed (step150) followed by a second set on top of the first set (step152). Both sets of components20are then electrically connected in parallel at the same time in a common step with component connection(s)30. Disposing step152can be repeated, either interspersed with forming component connection step150, as inFIG.23, or followed by step150, as inFIG.24to form an interconnected component stack28of components20. According to embodiments of the present disclosure, after an offset component stack28of components20is formed, component connection(s)30can be made in a common step, reducing the number of photolithographic deposition and patterning steps, e.g., as shown inFIG.1C.

In some embodiments, component connections30are constructed at a different (e.g., lower) resolution from structures in components20or transistor elements40, for example using different process methods or materials, or both, (e.g., at a lower cost). In optional step130, multi-component transistor structure99can be removed from the common semiconductor wafer, for example by dicing, or by micro-transfer printing into an external structure, such as a desired product or system, thereby forming fractured tethers52for support substrate10. In such multi-component transistor structures99, component substrate56can comprise at least a portion of and common materials with component source wafer60and can support one component (e.g., as shown inFIGS.3A-3C) or multiple components20(e.g., as illustrated inFIGS.3D and3E). In some embodiments, support substrate10with multi-component transistor structure99can be micro-transfer printed or diced and transferred to a system, e.g., having a system substrate.

For a discussion of micro-transfer printing techniques see U.S. Pat. Nos. 8,722,458, 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in their entirety. Micro-transfer printing using compound micro-assembly structures and methods can also be used with the present disclosure, for example as described in U.S. patent application Ser. No. 14/822,868, filed Aug. 10, 2015, entitledCompound Micro Assembly Strategies and Devices, which is hereby incorporated by reference in its entirety. U.S. Pat. No. 9,520,537, filed Jun. 18, 2015, entitledMicro Assembled LED Displays and Lighting Elements, incorporated herein by reference describes micro-transfer printing structures and processes useful with the present disclosure.

FIG.13is a detail and plan view of a component20design (an 8.5-micron thick power FET) and layout disposed on support substrate10and electrically connected in parallel with 3-micron thick component connections30. Each component20has an area of 165 by 330 microns. This design comprises an 18 by 9 array of 162 components20covering approximately 3.2 mm by 3.2 mm. Components20can be arranged, for example, in three layers so that multi-component transistor structure99comprises 486 components20.FIG.14is a detail of component20comprising a bare die98embedded in component substrate56(e.g., an FR4 core) together with dielectric structures58, component vias54, and portions of component connection30having a 100-micron thickness in component vias54, reducing resistance in the vertical direction.

FIG.15illustrates a design and partial layout of an offset stacked configuration (e.g., corresponding toFIG.8B) of first, second, third, and fourth components20A-20D with component connections30disposed on a silicon support substrate10having an electronic circuit12to control components20.FIG.16illustrates the structure ofFIG.15with conductors80electrically connected to component connection30providing thick (e.g., 12-20 microns) multi-layer copper metal interconnects for conducting current to and removing heat from the multi-component transistor structure99. The metal conductors80are 12, 18 and 20 microns thick and component vias54are 25 microns thick. In some embodiments, the metal is copper; such thick metal conductors (e.g., up to 100 microns thick) can be constructed using some embodiments of the present disclosure but are difficult or impossible to deposit on or with such small bare die98using conventional methods.FIG.17illustrates a stacked arrangement (corresponding toFIG.7A) of aligned components20and component connections30disposed on a silicon support substrate10having an electronic circuit12to control components20. Component stacks28illustrated inFIGS.15and16are offset component stacks28andFIG.17is an aligned component stack28as shown inFIGS.2A-2C.

FIGS.18A-18Cillustrate three components20comprising component transistors21that are interdigitated (e.g., interdigitated transistors92as shown inFIG.5B) having different sizes that are suitable for a stacked multi-component transistor structure99configuration as shown inFIGS.7B,1A, and1C).FIG.18Aillustrates the largest component20,FIG.18Billustrates a component20that is slightly smaller than the component20ofFIG.18A, andFIG.18Cillustrates a component20that is smaller than the component20ofFIG.18B, so that the three components20can be stacked directly on top of each other and the edges of the components20at each level (or layer) are exposed (as shown inFIGS.7B,1A,1C, and15) to form an offset component stack28. By locating electrical contacts on the exposed edges (e.g., as shown inFIG.15), components20can be electrically connected with a component connection30on the exposed edges, while maintaining a very dense configuration. Furthermore, connections along a length of a transistor element40can be made by disposing connections linearly along the exposed edge, for example along at least 50%, 60%, 70%, 80% or 90% of the exposed edge. As shown inFIG.18A, component source and drain connections32,36indicated by the dark rectangles are provided along the length of the exposed transistor elements40(e.g., drain26and source22), optionally connected with component connections30through component vias54(not shown inFIGS.18A-18C). For a transistor comprising a source22, gate24, and drain26, by making components20successively smaller (e.g., as illustrated inFIG.1Cin perspective andFIG.15in cross section) in both length and width, transistor elements40electrically connected to a contact along a short side (the width) of component20can also be electrically connected with a component connection30.

Thus, according to some embodiments of the present disclosure, a multi-component transistor structure99comprises components20electrically connected in parallel. Each component20comprises one or more transistor elements40. Each transistor element40has a respective transistor element resistance. One or more component connections30each have a respective connection resistance, and each electrically connects to respective transistor elements40of components20. The connection resistance is less than, less than an average of, or less than a sum of the transistor element resistances of the respective transistor elements40of each component20. At least one component20is disposed on another component20, for example in an aligned component stack28or an offset component stack28. In some embodiments, all of components20are the same size. In some embodiments, components20in component stack28are successively smaller and the largest component20is disposed on support substrate10forming an offset component stack28. In some embodiments, components20have a length and a width smaller than a length and electrical connections to transistor elements40that experience the greatest current (e.g., source22or drain26) are disposed along an edge of component20in the length direction. Successive components20can be smaller in length, smaller in width, or smaller in both length and width. Relatively smaller components20can be disposed entirely over relatively larger components20so that no portion of the smaller component20extends beyond the larger component20or extends over an edge of the larger component20. Components20can be, but are not necessarily, rectangular and can have other shapes, for example any polygon, and including curved shapes. Thus, one, two, three, four, or more edges of the larger components20in component stack28can be exposed.

In some embodiments, electrical connections to one or more transistor elements40are disposed on an exposed edge of a component20. The electrical connection can be a component connection30that electrically connects transistor elements40in components20in a component stack28such as an offset component stack28, for example as shown inFIG.15. For example, an electrical connection to gate24can be located at one end of a bare die98comprising an interdigitated component transistor21(e.g., as shown inFIG.5B) and electrically connected to a component gate connection34(e.g., as shown inFIG.3A) and electrical connections to high-current source22and drain26can be made along the exposed edges along the length of the bare die98to respective component source connections32and component drain connections36. Thus, a multi-component transistor structure99comprising stacked components20ofFIGS.18A-18Cin a configuration such as that ofFIG.7Band electrically connected with component connections30as indicated inFIGS.15and16provides a more integrated, compact, and dense structure with improved performance, such as decreased resistance and heating and increased power and switching speed.

FIG.19illustrates the relative reduction in source/drain resistance (Rds) modeled as a function of component20count and the relative area required for components20in a multi-component transistor structure99of the present disclosure for the component design ofFIGS.12and15using 40-volt field-effect component transistors21(FETs). The upper line corresponds to a two-dimensional array of transistors and the lower line corresponds to a three-dimensional array of components20in a component stack28according to embodiments of the present disclosure and as shown inFIGS.7B,1A,15, and18A-18C. Further modeling, not illustrated, shows that as voltage increases (e.g., greater than 40V), relative performance of a stacked component array of multi-component transistor structure99with respect to a conventional component arrangement increases exponentially.

As shown inFIGS.3A-3E,11A, and11B, components20or multi-component transistor structures99can be mounted upon, micro-transfer printed upon, or adhered to support substrate10. As intended herein, to be mounted upon means that separate substrates are separately produced and then brought into proximity and adhered together in some fashion, for example by micro-transfer printing. The components20can be, for example, unpackaged bare die98so that each component20is in direct contact with the support substrate10or with an adhesive layer disposed on support substrate10(not shown). To be mounted upon, micro-transfer printed to, or adhered to electronic circuit12or support substrate10means that component transistor21is mounted upon, micro-transfer printed upon, or adhered to any of the circuits of electronic circuit12or support substrate10, for example upon a semiconductor layer, a patterned or doped semiconductor layer or structure, a conductor layer or patterned conductor, a dielectric layer, a patterned dielectric layer, a protective layer, or any other portion of the electronic circuit12, layers on support substrate10, or support substrate10.

Electronic circuit12can be a circuit that includes active or passive (or both) components or elements. For example, an active electronic circuit12can include a transistor, an amplifier, or a switch and, in some embodiments, can provide control functions to components20. Electronic circuit12can be a silicon circuit in a silicon support substrate10for compound semiconductor components20, such as GaN, GaAs, or InP, for example useful for power or radio frequency applications. Passive components such as conductors, resistors, capacitors, and inductors can also be included in electronic circuit12. Portions of electronic circuit12can be electrically connected to circuit contact pads16. Circuit contact pads16can be portions of electronic circuit12that are available to make electrical connections with electrical devices external to electronic circuit12, for example such as controllers, power supplies, ground, or signal connections. Circuit contact pads16can be, for example, rectangular areas of electrically conductive materials accessible or exposed to external elements such as wires or conductors or component transistor21or any one or all of the component source, gate, and drain connections32,34,36and component connections30. Electrical connections to the circuit contact pads16can be made using solder and solder methods, photolithographic processes, or by contacting and possibly penetrating the contact pads16with electrically conductive protrusions or spikes (e.g., connection posts50) formed in or on a device with another substrate separate, distinct, and independent from support substrate10and connected to component transistors21, for example as described in U.S. Pat. No. 10,468,363 entitled Chiplets with Connection Posts, whose contents are incorporated by reference in their entirety. Alternatively, the component transistor21can include connection posts50that are printed onto contact pads16of a support substrate10.

Support substrate10and component transistors21can take a variety of forms, shapes, sizes, and materials. In some embodiments, component transistor21is thinner than support substrate10. In some embodiments, support substrate10can have a thickness no greater than 500 microns (e.g., no greater than 100 microns, no greater than 50 microns, or no greater than 20 microns). In some embodiments, components20are chiplets, small integrated structures, for example bare die98, that are micro-transfer printed to support substrate10and electrically connected using photolithographic materials and methods, or with connection posts50and contact pads16. In various embodiments, component20has at least one of a width, a length, and a height from 2 to 50 μm (e.g., 2 to 5 μm, 5 to 10 μm, 10 to 20 μm, or 20 to 50 μm). In some embodiments, components20can have a thickness no greater than 20 microns (e.g., no greater than 10 microns, no greater than 5 microns, no greater than 2 microns, no greater than 1 micron, or no greater than 0.5 micron). Such a variety of sizes and small component substrates56can enable highly integrated and small structures useful in a corresponding variety of electronic systems and can provide a high degree of integration and material utilization and consequently reduced manufacturing costs and improved performance. Assemblies of integrated components20(e.g., multi-component transistor structure99) can be subsequently packaged. Broken (e.g., fractured) or separated tethers52can have a thickness of several nm (e.g., no more than 50, 100, 200, 500, 700, or 800 nm) to a few μm (e.g., no more than 1-5 μm), for example from 600 nm to 1.5 μm. The integrated assembly (e.g., multi-component transistor structure99) can be a surface-mount device.

As is understood by those skilled in the art, the terms “over”, “under”, “above”, “below”, “beneath”, and “on” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present disclosure. For example, a first layer on a second layer, in some embodiments means a first layer directly on and in contact with a second layer. In other embodiments, a first layer on a second layer can include another layer there between. Additionally, “on” can mean “on” or “in.” As additional non-limiting examples, a patterned sacrificial layer68or sacrificial portion66is considered “on” a substrate when a layer of sacrificial material or sacrificial portion66is on top of the substrate, when a portion of the substrate itself is the patterned sacrificial layer68, or when the patterned sacrificial layer68or sacrificial portion66comprises material on top of the substrate or a portion of the substrate itself.

Having described certain embodiments, it will now become apparent to one of skill in the art that other embodiments incorporating the concepts of the disclosure may be used. Therefore, the disclosure should not be limited to the described embodiments, but rather should be limited only by the spirit and scope of the following claims.

Throughout the description, where apparatus and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus, and systems of the disclosed technology that consist essentially of, or consist of, the recited components, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.

It should be understood that the order of steps or order for performing certain action is immaterial so long as the disclosed technology remains operable. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously. The disclosure has been described in detail with particular reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the disclosure.

PARTS LIST

A cross-section lineLCcomponent connection lengthLEelement lengthLTtransistor lengthP1, P2, P3, P4, P5portionsR1, R2connection pointsS separation distanceW width10support substrate12electronic circuit14heat conductor16contact pad20component20A first component20B second component20C third component20D fourth component21component transistor22source24gate/interface26drain28component stack30component connection32component source connection34component gate connection36component drain connection40transistor element41transistor electrode42source electrode44gate electrode46drain electrode50connection post52fractured component tether54component via56component substrate57common component substrate/common die58dielectric structure60component source wafer62component tether64anchor66sacrificial portion68sacrificial layer70encapsulation layer/planarization layer80conductor90serpentine transistor92interdigitated transistor98die99multi-component transistor structure100provide component source substrate110form components step120form component connections step130optional integrate into system step140provide support substrate step150transfer components to support substrate step152transfer components to transferred components step