Patent ID: 12255157

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms “approximate,” “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

The present disclosure provides a semiconductor package device integrated with an on-chip inductor and its associated manufacturing operations, according to various embodiments. The inductor is an indispensable component in many aspects of modern semiconductor electronics, such as sensors, transformers, power management circuits, charging circuits and radio-frequency circuits. However, as the size of the packaged semiconductor device continues to shrink, the miniaturization of the inductor has drawn attention as a key step necessary to successfully reduce the dimensions of the packaged device. To address such need, a miniaturized on-chip inductor is proposed that is produced using techniques common to fabrication of semiconductor devices, such as lithography, etching, and deposition. Compared to the conventional inductor comprised of enameled wires, the proposed on-chip inductor has a smaller size. Moreover, the configuration and properties of the semiconductor-based inductor are improved due to design of the semiconductor manufacturing operations. As a result, the resultant inductor-embedded package device renders better inductor performance and integration efficiency with a reduced device size.

FIGS.1through8andFIGS.10through14are cross-sectional views of intermediate structures for a method of manufacturing a semiconductor package device100, in accordance with some embodiments. The semiconductor package device100may be an electronic device, such as a sensor, a transformer, a power management integrated circuit (IC), a wireless charger device, or a radio-frequency transmitter/receiver. Referring toFIG.1, a substrate110is received or provided. The substrate110includes a semiconductor material, such as silicon. In an embodiment, the substrate110may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. The substrate110may be a p-type semiconductive substrate (acceptor type) or an n-type semiconductive substrate (donor type). Alternatively, in various applications the substrate110may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or combinations thereof. In the present embodiment, the substrate110is an interposer substrate formed of bulky silicon. Conductive vias may be formed in the substrate to electrically couple components on opposite sides of the substrate110. In some embodiments, the substrate110may be substantially free of active devices, such as transistors, or passive devices, such as resistors, capacitors or inductors, in addition to the conductive vias.

Referring toFIG.1, several recesses102are formed through a surface110A of the substrate110. An etching operation is performed on the substrate110to form the recesses102. In some embodiments, the etching operation may be a dry etch, a wet etch, or a combination thereof. In the depicted embodiment, a dry etch or a reactive ion etching (RIE) operation is adopted. Although not shown, a photoresist layer may be formed over the substrate110to define the geometry of the recesses102. Furthermore, after the recesses102are formed, the photoresist layer may be cleaned or stripped.

FIG.2shows the forming of conductive vias104in the recesses102. In some embodiments, a protection layer106is initially formed on the substrate110before the conductive vias104are formed. The protection layer106may line sidewalls and the bottoms of the recesses102. The protection layer106may be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like. The protection layer106may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, or the like.

The conductive vias104are formed over the protection layer106and in the recesses102. In some embodiments, the conductive vias104act as through-interposer vias of the semiconductor package device100. The conductive vias104are made of a conductive material such as copper, tungsten, titanium, aluminum, silver, combinations thereof, or the like. The conductive vias104may be formed by CVD, PVD, ALD, electroplating, or other suitable methods. The conductive vias104may be formed by forming a conductive material over the substrate110and into the recesses102. Afterwards, excess conductive materials may be removed by a planarization operation, such as grinding or chemical mechanical polishing (CMP). Accordingly, the conductive vias104are level with horizontal portions of the protection layer106.

FIG.3throughFIG.8illustrate cross-sectional views of intermediate structures of the process of forming an interconnect structure120, in accordance with various embodiments. The interconnect structure120, also known as a redistribution layer (RDL), is widely applied in semiconductor circuits in order to provide rerouted interconnections between components on one side of an interconnect structure, such as the interconnect structure120. In some embodiments, the interconnect structure120is configured to electrically couple components on different sides of the interconnect structure120. The interconnect structure120generally includes stacked metallization layers comprised of conductive features connected with each other to establish the interconnection routes, e.g., metallization layers212,213,214,215and216shown inFIG.3throughFIG.8. Each of the metallization layers may include conductive lines or vias in which the conductive lines are electrically coupled to an adjacent overlaying or underlying conductive line through intervening conductive vias. The metal lines and metal vias are electrically insulated by insulating materials, usually referred to as an inter-metal dielectric (IMD). Moreover, an inductor200(seeFIG.9A) is formed and embedded in the interconnect structure120. Components of the inductor200, e.g., a magnetic core and a coil, are simultaneously formed during forming of the conductive lines and vias of the interconnect structure120. Accordingly, the semiconductor device comprised of the substrate110and the interconnect structure120may also be referred to as an inductor device. However, in some embodiments, the configurations and materials of the interconnection conductive lines and vias foreign to the inductor200may be different from those of the inductor200, as described in subsequent paragraphs.

Initially, as illustrated inFIG.3, a first metallization layer212is formed over the substrate110. In some embodiments, a first dielectric layer116and a second dielectric layer118, collectively referred to as the IMD of the first metallization layer212, are sequentially formed with dielectric materials in a blanket manner over the substrate110. In some embodiments, the first dielectric layer116is eliminated and is not present in the formation of the first metallization layer212. In some embodiments, the first dielectric layer116comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or the like. In some embodiments, the second dielectric layer118comprises oxide, such as un-doped silicate glass (USG), fluorinated silicate glass (FSG), borophosphosilicate glass (BPSG), tetraethosiloxane (TEOS), spin-on glass (SOG), high-density plasma (HDP) oxide, plasma-enhanced TEOS (PETEOS), or the like. The first dielectric layer116and the second dielectric layer118may include different dielectric materials. The first dielectric layer116and the second dielectric layer118may be formed by CVD, PVD, ALD, spin-on coating, or other suitable operations.

Once deposited, the first dielectric layer116and the second dielectric layer118are patterned. Several recesses111are formed through the first dielectric layer116and the second dielectric layer118using a patterning operation. In some embodiments, the patterning operation involves a lithography operation and an etching operation in a manner similar to that used during the forming of the vias104. Some of the recesses111may be aligned with the underlying conductive vias104to expose the conductive vias104and portions of the protection layer106. The etching operation may be dry etch, wet etch, or a combination thereof. Although not shown in the figure, each of the recesses111may have a strip shape extending in a horizontal direction substantially parallel to the surface110A of the substrate110.

Referring toFIG.4, metal lines112are formed in the recesses111. The metal lines112may be formed of conductive materials, such as titanium, copper, silver, aluminum, gold, tungsten, combinations thereof, or the like. The metal lines112may be formed by depositing the conductive material using CVD, PVD, ALD or other suitable methods. In some embodiments, a planarization operation, such as grinding or CMP, may be utilized to level upper surfaces of the metal lines112and the second dielectric layer118. Thus, the first metallization layer212is completed. As shown inFIG.4, an inductor zone201is defined for the inductor200where the metal lines112within the inductor zone201are used as components of the inductor200. The conductive lines or vias within the inductor zone201that are configured to perform the function of the inductor200may be electrically isolated from other conductive components, such as the metal lines112outside of the inductor zone201. The metal lines112outside the inductor zone201may serve as an interconnection route and may be configured for interconnecting devices or components of the semiconductor package device100on both sides of the interconnect structure120.

Next, a second metallization layer213and a third metallization layer214are successively formed over the first metallization layer212inFIG.5. The configurations and manufacturing methods of the second metallization layer213and the third metallization layer214are similar to those of the first metallization layer212. The first dielectric layer116of the first metallization layer212is omitted from the current and subsequent figures for simplicity. In some embodiments, the second metallization layer213includes a first dielectric layer126and a second dielectric layer128that are sequentially formed in a blanket manner over the first metallization layer212. Similarly, the third metallization layer214includes a first dielectric layer131and a second dielectric layer135that are sequentially formed in a blanket manner over the second metallization layer213.

In some embodiments, the first dielectric layer126of the second metallization layer213comprises a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or the like. In some embodiments, the second dielectric layer128of the second metallization layer213comprises oxide, such as USG, FSG, BPSG, TEOS, SOG, HDP oxide, PETEOS, or the like. In some embodiments, the first dielectric layer126and the second dielectric layer128may include different dielectric materials. The first dielectric layer126and the second dielectric layer128may be formed by CVD, PVD, ALD, spin-on coating, or other suitable operations.

In some embodiments, the first dielectric layer136of the third metallization layer214comprises a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or the like. In some embodiments, the second dielectric layer135of the third metallization layer214comprises oxide, such as USG, FSG, BPSG, TEOS, SOG, HDP oxide, PETEOS, or the like. In some embodiments, the first dielectric layer136and the second dielectric layer135of the third metallization layer214may include different dielectric materials. In some embodiments, the first dielectric layer116of the first metallization layer212, the first dielectric layer126of the second metallization layer213and the first dielectric layer136of the third metallization layer214may be formed of different dielectric materials, e.g. the dielectric layers126and136are formed of silicon carbide and silicon nitride, respectively. The first dielectric layer136and the second dielectric layer135may be formed by CVD, PVD, ALD, spin-on coating, or other suitable operations.

Still referring toFIG.5, after the second dielectric layer135is formed, several recesses211and217are formed in the second metallization layer213and the third metallization layer214. Some recesses, e.g., the recesses217, may be aligned with and expose their underlying metal lines112. The recesses211and217may be formed using an etching operation, such as dry etch, wet etch, or a combination thereof. The recesses211and217may have an upper portion in the third metallization layer214and a lower portion in the second metallization layer213. In some embodiments, the upper portion of the recess211or217has a width larger than a width of the lower portion of the corresponding recess211or217. In some embodiments, the lower portion of each recess211or217includes more than one vias exposing the corresponding metal line112. Each of the vias in the lower portion of the recess211or217has a width smaller than the width of the upper portion of the corresponding recess211or217. In some embodiments, the upper portion of the recess211within the inductor zone201has a polygonal or circular shape. In some embodiments, the upper portion of the recess217outside the inductor zone201has a strip-like shape extending in a horizontal direction substantially parallel to the surface110A of the substrate110.

Referring toFIG.6, metal lines123are formed in the upper portions of the recesses111. Additionally, metal vias114,115and122are formed in the lower portions of the recesses111during a same formation operation of the metal lines123. The materials and forming methods of the metal lines123and the metal vias114,115and122may be similar to those of the metal lines112. In some embodiments, metal vias114and122within the inductor zone201that are configured to perform the function of the inductor200may be electrically isolated from other conductive components, such as the metal lines123or metal vias115outside the inductor zone201. The metal lines123and the metal vias115outside the inductor zone201may be configured for interconnecting devices or components of the semiconductor package device100on both sides of the interconnect structure120. In some embodiments, the metal vias122within the inductor zone201may have a circular or polygonal shape serving as a node of conduction electrically coupling the metal vias114and overlying metal vias (e.g., metal vias314inFIG.8). In some embodiments, the metal vias122have a first width greater than a second width of the metal vias114from a cross-sectional view of top-view perspective for ensuring robust electrical connection between them. In some embodiments, the metal vias122have a first area from a top-view perspective greater than a second area of the metal vias114from a top-view perspective.

FIG.7illustrates the formation of a magnetic core124as a magnetic region in the third metallization layer214. The methods of forming the magnetic core124are similar to those of the forming of the metal lines112and123or the forming of the metal vias114,115and122. For example, a recess may be initially formed in the second metallization layer213. In some embodiments, a photoresist, different from that used for forming the metal lines123or the metal vias122, may be patterned to specifically define the geometry of the recess. Next, an etching operation is performed to form the recess. A magnetic material is subsequently deposited to fill the recess. The chosen magnetic material of the magnetic core124possesses a high permeability coefficient. The magnetic material may have a low hysteresis coefficient. Further, the magnetic material may possess a low conductivity in order to mitigate the induced Eddy current. In contrast, the metal line112and the metal vias114and122are made of highly conductive materials, such as copper, in order to reduce conduction resistance.

In some embodiments, a first magnetic material of the magnetic core124comprises nickel, zinc and copper with percentages of 40%, 20% and 20%, respectively, plus ferric oxide (e.g., Fe2O4) with a relatively lower percentage. In some embodiments, the magnetic core124has a second magnetic material comprised of yttrium and bismuth with percentages of 80% and 20%, respectively, plus ferric oxide (e.g., Fe5O12) with a relatively lower percentage. The first magnetic material or the second magnetic material may be formed by spin-coating.

In some embodiments, the magnetic core124has a third magnetic material comprised of nickel and iron with percentages of 80% and 20%, respectively. The third magnetic material may be formed by electroplating or PVD (e.g., sputtering). In some embodiments, the magnetic core124has a fourth magnetic material comprised of cobalt, zirconium and tantalum (also referred to as CZT) with percentages of 91.5%, 4% and 4.5%, respectively. The fourth magnetic material may be formed by the sputtering operation.

In some embodiments, the magnetic core124is disposed above the second metallization layer213. In some embodiments, the magnetic core124is disposed at the tier of the third metallization layer214. In some embodiments, the magnetic core124has a top surface substantially level with the metal vias122and the metal lines123. In some embodiments, the magnetic core124has a top surface substantially level with the third metallization layer214. In some embodiments, the magnetic core124extends between two adjacent metal vias122. In some embodiments, magnetic core124is not present between one metal via122and a metal line123adjacent to the metal via122.

Referring toFIG.8, a fourth metallization layer215and a fifth metallization layer216are successively formed over the third metallization layer214and the magnetic core124. The fourth metallization layer215includes metal vias314and315surrounded by an IMD, in which the IMD is formed of a first dielectric layer146and a second dielectric layer148. The metal vias314are configured as part of the inductor200while the metal vias315are configured as part of an interconnection path. In some embodiments, the configuration, materials and methods of formation of the fourth metallization layer215are similar to those of the second metallization layer213. Similarly, the fifth metallization layer216includes metal lines132and133surrounded by an IMD in which the IMD is formed of a first dielectric layer156and a second dielectric layer158. The metal line132is configured as part of the inductor200and the metal lines133are configured as part of an interconnection path. In some embodiments, the configuration, materials and methods of formation of the fifth metallization layer216are similar to those of the third metallization layer214. In the depicted example, the metal line132electrically connects two adjacent metal vias122at two sides of the magnetic core124and extends over the magnetic core124.

FIG.9Ais a schematic perspective view of the inductor200in the semiconductor package device100, in accordance with some embodiments. Referring toFIG.8andFIG.9A, the cross-sectional view of the inductor zone201inFIG.8is taken from a sectional line AA inFIG.9A. InFIG.9A, the inductor200includes a conductive coil910and a magnetic core920. The conductive coil910is comprised of a bottom metal layer902, a middle metal layer904and a top metal layer906interconnected to each other. The metals in the bottom metal layer902and top metal layer906correspond to the metal lines112and132, respectively, of the interconnect structure120inFIG.8. Further, the illustration of an exemplary middle metal layer904on the left side ofFIG.9Ashows the details of its structure including the metal vias114,122and314corresponding to those of the interconnect structure120inFIG.8. Moreover, the magnetic core920ofFIG.9Acorresponds to the magnetic core124inFIG.8. It can be seen inFIG.9Athat the conductive coil910has a helical shape, which surrounds and winds around the magnetic core920. In the depicted embodiment, the magnetic core920is wound by the conductive coil910by nine turns, where one turn is made up of one bottom metal layer902, two middle metal layers904and one top metal layer906. In some embodiments, the metal lines of the top metal layer906are staggered with those in the bottom metal layer902in order to form the helical structure of the conductive core910. Although the conductive coil910and the magnetic core920may be closely disposed, they are electrically insulated by the IMD, as shown inFIG.8. In some embodiments, the magnetic core902is fully encapsulated by the IMD. In some embodiments, the magnetic core920is electrically isolated from other conductive features of the interconnect structure120.

Still referring toFIG.9A, an input port912and an output port914are configured to electrically couple the conductive coil910with external conductive features. In some embodiments, the inductor200conductively couples to other features through only the input port912and the output port914. In some embodiments, the input port912and the output port914are disposed at the tier of the bottom metal layer902and are formed from the metal lines112of the first metallization layer212. However, depending on design needs, the input port912or the output port914can be alternatively formed at the tier of the top metal layer906and can be formed of the metal lines132of the fifth metallization layer216.

In some embodiments, the magnetic core920has a circular shape or a ring shape. In some embodiments, the magnetic core920has a polygonal ring shape. In some embodiments, the cross section of the magnetic core920has a quadrilateral shape (e.g., square, rectangle or trapezoid), as illustrated by the region of the magnetic core124inFIG.7. Such shape occurs because the recess for forming the magnetic core124is formed through a semiconductor etching process. In some embodiments, referring toFIG.8orFIG.9A, a diameter D1of the magnetic core124or920is between about 10 μm and about 30 μm. In some embodiments, the diameter D1is between about 10 μm and about 20 μm. In some embodiments, a diameter D2of the metal via122or the conductive coil910is between about 10 μm and about 30 μm. In some embodiments, the diameter D2is between about 10 μm and about 20 μm. In some embodiments, the diameter D1is substantially equal to the diameter D2. In some embodiments, a distance D3between the conductive coil910and the magnetic core920is between about 10 μm and about 30 μm. In some embodiments, the distance D3is between about 10 μm and about 30 μm. In some embodiments, a distance between the first metallization layer212and the fifth metallization layer216is between about 80 μm and 200 μm, for example 100 μm.

FIG.9Bis a schematic perspective view of an inductor230in the semiconductor package device100, in accordance with some embodiments. The inductor230has a conductive coil930and a magnetic core940, around which the conductive coil930is wound. Referring toFIG.9AandFIG.9B, the inductor230is similar to the inductor200except that the configuration of the magnetic core940has a bar or strip shape. In some embodiments, the magnetic core940has two ends extending in substantially opposite directions. In some embodiments, the conductive coil930has an input port932and an output port934at the two ends of the magnetic core940.

FIG.10shows the formation of an insulating film134of the interconnect structure120. The insulating film134may be formed of a dielectric material, such as oxide, nitride, oxynitride, carbide, or the like. In some embodiments, the insulating film134is formed of the same material as the IMD in the interconnect structure120. The insulating film134may be formed using CVD, PVD, spin-coating, or the like. Subsequently, several conductive vias136are formed through the insulating film134. The material and method of the manufacture of the conductive vias136may be similar to those of the metal lines and metal vias in the metallization layers212to216of the interconnect structure120. Some of the conductive vias136are electrically coupled to the metal lines133while some other conductive vias136are electrically coupled to the metal lines132of the conductive coil.

Several conductive pads138are formed on the surface of the insulating film134to electrically couple to the conductive vias136. The conductive pads138may be formed of copper, aluminum, tungsten, titanium, combinations thereof, or the like. Next, a passivation layer152is formed over the insulating film134and the conductive pads138. The passivation layer152may be formed in a blanket manner using CVD, PVD, spin-coating, or the like. The passivation layer152may comprise a dielectric material such as oxide, nitride, or oxynitride. Moreover, the passivation152is patterned to expose the conductive pads138. The resultant semiconductor structure inFIG.10may be referred to as an interposer die150.

Referring toFIG.11, a first semiconductor die162and a second semiconductor die172are provided or received. In some embodiments, the first semiconductor die162or the second semiconductor die172is a memory device, a processor device, a communication receiver or transmitter, a power management die, a transformer die, or the like. The first semiconductor die162and the second semiconductor die172comprise a first substrate (also called a die substrate)164and a second substrate174, respectively. The substrate164or174includes a semiconductor material, such as silicon. In one embodiment, the substrate164may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. The substrate164or174may be a p-type semiconductive substrate (acceptor type) or an n-type semiconductive substrate (donor type).

Various components may be formed on a front surface (front side)164A of the first substrate164and a front surface174A of the second substrate174. Examples of the components include active devices, such as transistors and diodes, and passive devices, such as capacitors, inductors, and resistors. The components may also include conductive elements, such as conductive traces or vias, and insulating materials. In addition, the semiconductor die162or172comprises one or more connection terminals (not illustrated) electrically coupled to external circuits or devices through the connection terminals.

A first passivation layer166and a second passivation176are formed on the first substrate164and the second substrate174, respectively. The connection terminals of the semiconductor die162or172are exposed through the first passivation layer166or the second passivation layer172. The first passivation layer166or the second passivation layer176may be formed of dielectric materials, such as oxide, nitride, or the like. Conductive connectors154are formed to bond the interposer die150with the semiconductor dies162and172, wherein the connection terminals of the first semiconductor die162and the second semiconductor die172are electrically coupled to the conductive pads138of the interposer die150. In some embodiments, the conductive connectors154may be contact bumps such as controlled collapse chip connection (C4) bumps, ball grid array bumps or microbumps.

FIG.12shows the forming of an encapsulating material182. The encapsulating material182encapsulates or surrounds the conductive connectors154, the semiconductor dies162and172, and the passivation layer152of the interposer die150. The encapsulating material182may include a molded underfill material. In some embodiments, the encapsulating material182is formed of epoxy, deformable gel, silicon rubber, thermal plastic polymer, combinations thereof, or the like. In other embodiments, the encapsulating material182includes a filler material. The encapsulating material182may be formed by dispensing, injecting, or spraying techniques.

Subsequently, an encapsulating material184is applied to fill the gap of the encapsulating material182between the semiconductor dies162and172. In some embodiments, the encapsulating material184fills the gaps between the interposer die150and the semiconductor dies162and172. In some embodiments, the encapsulating material184includes a molding compound such as polyimide, PPS, PEEK, PES, a molding underfill, an epoxy, a resin, or a combination thereof. The encapsulating material184may be formed by dispensing, injecting, or spraying techniques.

Once the molding material182or184has been formed, a thinning or planarization process may be performed for removing excess encapsulating material182or184. The thinning and planarization operation may be performed using a mechanical grinding or CMP method. In some embodiments, the upper surfaces of the encapsulating materials182/184and the semiconductor dies162and172are substantially level with one another.

The semiconductor package device100is flipped as shown inFIG.13. A depth of the substrate110is removed or thinned so as to expose the bottoms of the conductive vias104. The thinning and planarization operation may be performed using a mechanical grinding or CMP method. Subsequently,FIG.14illustrates a formation of external connectors232. Initially, a conductive pad222and an under bump metallization (UBM)224are sequentially formed over the conductive via104. In some embodiments, the conductive pad222may comprise a single layer or a multilayer structure. For example, the conductive pad222comprises copper, cooper alloy, tin, nickel, nickel alloy, combinations, or the like. In an embodiment, the UBM224may comprise a diffusion barrier layer, a seed layer, or a seed layer over a diffusion barrier layer. In some embodiments, the diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some embodiments, the seed layer may comprise copper or copper alloys. The conductive pad222and the UBM224may be formed by CVD, PVD, sputtering or other suitable methods.

Next, a solder material232is formed over the UBM224. In some embodiments, the solder material232comprises lead-based materials, such as Sn, Pb, Ni, Au, Ag, Cu, Bi, combinations thereof, or mixtures of other electrically conductive material. In an embodiment, the solder material232is a lead-free material. A thermal process may be performed on the solder material232, forming an external connector232. In some embodiments, the external connector232comprises a spherical shape. However, other shapes of the external connector232may be also possible. In some embodiments, the external connector156may be C4 bumps, ball grid array bumps, or microbumps.

The present disclosure provides advantages. The proposed μm-level on-chip inductor is advantageous due to its reduced size and 10-times higher permeability coefficient compared to conventional millimeter-level inductors. In addition, compared to an existing on-chip inductor configuration in which an inductor core made of conductive material is wrapped by a magnetic coil, the proposed inductor adopts a conductive coil winding around a magnetic core. When working in conjunction with an on-chip capacitor in power management applications, the proposed inductor configuration provides a better charging performance than the existing conductive-core configuration.

The present disclosure provides a method, which includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure; and a connecting metal line adjacent to and on an outside of the inductor zone, the connecting metal line being electrical isolated from the inductor zone. The vertically-extending conductive vias include first conductive vias in contact with a first one of the horizontally-extending conductive lines, second conductive vias overlapping the first conductive vias and in contact with a second one of the horizontally-extending conductive lines opposite to the first one of the horizontally-extending conductive lines, and a third conductive via between the first conductive vias and the second conductive vias. The connecting metal line is between, and non-overlapped with, the first conductive via and the second conductive vias vertically from a cross-sectional view.

The present disclosure provides a method, including forming an interconnect structure over a substrate, the interconnect structure including a plurality of metallization layers forming an interconnection path and an inductor electrically isolated from the interconnection path. The plurality of metallization layers includes: first metal features in an inductor zone to form a coil of the inductor and include a magnetic region extending within the coil of the inductor, wherein the coil includes a first conductive via in a first metallization layer, a second conductive via in a second metallization layer, and a third conductive via in a third metallization layer; and second metal features arranged outside the inductor zone, the second metal features including a first connecting metal via in the first metallization layer, and a second connecting metal via in the second metallization layer, wherein the first conductive via has an upper surface and a bottom surface coplanar with an upper surface and a bottom surface, respectively, of the first connecting metal via, and the second conductive via has an upper surface and a bottom surface coplanar with an upper surface and a bottom surface of the second connecting metal via.

The present disclosure provides a method, including forming an interconnect structure over a semiconductor substrate, the forming including forming an inductor in an inductor zone, the inductor including a coil and a magnetic core wrapped around by the coil. The forming of the inductor includes: depositing the magnetic core in an intermediate layer of the interconnect structure; and depositing metal lines and metal vias laterally spaced apart from the magnetic core, wherein the metal vias comprises first metal vias arranged in a first metallization layer of the interconnect structure and second metal vias arranged in a second metallization layer of the interconnect structure over the first metallization layer. The forming of the interconnect structure further includes: depositing a connecting metal line adjacent to and on an outside of the inductor zone, the connecting metal line being electrical isolated from the inductor zone and leveled with the magnetic core; and depositing a connecting metal via electrically coupled to the connecting metal line, wherein the connecting metal via is electrically isolated from the inductor zone and has an upper surface and a bottom surface aligned with an upper surface and a bottom surface, respectively, of the first metal vias or the second metal vias.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.