Patent ID: 12223867

DESCRIPTION OF EMBODIMENTS

In order to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

It should be made clear that the described embodiments are merely some of rather than all of the embodiments of the present disclosure. All other embodiments acquired by those of ordinary skill in the art without creative efforts based on the embodiments in the present disclosure fall within the protection scope of the present disclosure.

The terms used in the embodiments of the present disclosure are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used in the embodiments of the present disclosure and the appended claims, the singular forms of “a/an”, “the”, and “said” are intended to include plural forms, unless otherwise clearly specified in the context.

It should be understood that the term “and/or” used herein is merely an association relationship describing associated objects, indicating that three relationships may exist. For example, A and/or B indicates that there are three cases of A alone, A and B together, and B alone. In addition, the character “/” herein generally means that associated objects before and after it are in an “or” relationship.

A process of manufacturing a display panel100is described first in the present disclosure for providing a clearer understanding of structures such as a panel edge1and first electrostatic discharge protection wires5in the display panel100.

Generally, the display panel is obtained by cutting a motherboard. Referring toFIG.19, a motherboard200according to some embodiments of the present disclosure includes a plurality of panel regions300. Each panel region300corresponds to a to-be-tested display panel600. The panel region300includes structures such as test pads4.

Referring toFIGS.37A-37D and38A-38C, in a process of cutting the motherboard200into the display panels100, firstly, the motherboard200is cut along cutting lines500to form a plurality of independent to-be-tested display panels600. The cutting lines500include a first cutting line501. Edges of the to-be-tested display panels600formed by cutting the motherboard200along the first cutting line501are first edges400. Then, each of the to-be-tested display panels600is tested. During the testing, test voltages are applied to the test pads4in the to-be-tested display panel600, the test voltages are transferred to various signal lines to control the to-be-tested display panel600to display a test pattern, and then it is determined according to the displayed test pattern whether display performance of the to-be-tested display panel600is normal. For preventing material waste, the defective display panel600that cannot display normally will not be bonded to a driver chip or a printed circuit board. After the testing of the to-be-tested display panels600, the to-be-tested display panels600are utilized to form the display panel.

It is to be noted that, when the display panel is a mini LED display panel, after the motherboard200is cut to form the plurality of independent to-be-tested display panels600, a transfer process (such as surface mounting) is further required to place mini LEDs on the to-be-tested display panels600, and then the to-be-tested display panels600are tested.

For the process of forming the display panel by the to-be-tested display panel600, some embodiments of the present disclosure provide two feasible methods.

In the first feasible method, referring toFIG.37A-37D, the to-be-tested display panel600is not cut, connections between the test pads4and various signal lines in the to-be-tested display panel600are directly cut off (fractures are formed in connection lines11between the test pads4and pins9). That means, by this method, a structure where the test pads4are located is kept in the final display panel100, and thus the display panel100includes the test pads4.

In the second feasible method, referring toFIGS.38A-38C, the to-be-tested display panel600is further cut along a second cutting line502. In the method, the structure where the test pads4are located is cut away, so the final display panel100includes no test pads4.

In addition, referring toFIG.19, each of the panel regions300of the motherboard200is further provided with a plurality of first electrostatic discharge protection wires5. At least one first electrostatic discharge protection wire5of the first electrostatic discharge protection wires5extends between two adjacent test pads4. The first electrostatic discharge protection wires5in each panel region300further extend to the outside of the panel region300and are connected together, and then are connected to an outer edge of the motherboard200through a lead wire, thereby discharging static electricity generated in the manufacturing process of the motherboard200to the outside of the motherboard200and providing electrostatic discharge protection for the motherboard200. When the motherboard200is cut to form the to-be-tested display panels600, the first electrostatic discharge protection wires5are cut off at the first edges400of the to-be-tested display panels600. During the testing of the to-be-tested display panels600, the first electrostatic discharge protection wires5may still discharge the static electricity to the outside of the to-be-tested display panels600to prevent breakdown of circuits in the to-be-tested display panels600by the static electricity, thereby also providing electrostatic discharge protection for the to-be-tested display panels600.

Based on this, some embodiments of the present disclosure provide a display panel100. The display panel100may be formed with the above first feasible method. That means, the structure where the test pads4are located is kept in the display panel100.

FIG.1is a schematic structural diagram of a display panel100according to some embodiments of the present disclosure, andFIG.2is a schematic diagram of arrangement of test pads4and first electrostatic discharge protection wires5according to some embodiments of the present disclosure. As shown inFIG.1andFIG.2, the display panel100includes a panel edge1extending along a first direction x, and a display region2and a test region3arranged along a second direction y. The test region3is located between the display region2and the panel edge1. The first direction x intersects the second direction y. The panel edge1coincides with the first edge400of the to-be-tested display panel600. The panel edge1is formed by cutting the motherboard200along a first cutting line501.

The test region3includes a plurality of test pads4, at least part of the test pads4are arranged along the first direction x, and at least two of the test pads4adjacent in the first direction x are spaced apart by first electrostatic discharge protection wires5. The first electrostatic discharge protection wires5extend from one side of the display region2close to the test region3to the panel edge1. With reference to the above description of the manufacturing process of the display panel100, it can be seen that when the motherboard200is cut along the first cutting line501to form the to-be-tested display panels600, the first electrostatic discharge protection wires5are cut off at the first cutting line501(i.e. the panel edge1). Therefore, when the to-be-tested display panel600is further processed to form the display panel100by using the first feasible method, the first electrostatic discharge protection wires5extend from the side of the display region2close to the test region3to the panel edge1in the display panel100.

Referring toFIG.2, the first electrostatic discharge protection wire5includes a first line segment6and a second line segment7, the first line segment6is located between two adjacent test pads4, and the second line segment7is adjacent to the panel edge1. Moreover, adjacent first line segments6between two adjacent test pads4are spaced by a distance d1in the first direction x, adjacent second line segments7are spaced by a distance d2in the first direction x, and the distance d1is less than the distance d2.

In some embodiments of the present disclosure, in the design of the first electrostatic discharge protection wires5, the distance between the second line segments7that are close to the panel edge1is set to a larger value. Accordingly, when the motherboard200is cut along the first cutting line501to form the to-be-tested display panels600, even if the metal particle generated by cutting falls between the adjacent second line segments7, it is difficult for the metal particle to contact the two second line segments7at the same time, thereby preventing short circuit of the adjacent second line segments7. In this way, the second line segments7are independent of each other in the to-be-tested display panels600formed by cutting the motherboard200. In some embodiments, when the first electrostatic discharge protection wires5are connected to the pins, short circuit between the pins caused by the short circuit of the second line segments7can be prevented, and then false detection caused by a signal transmission error can be prevented during the testing of the to-be-tested display panels600.

At the same time, the distance d1between adjacent first line segments6is designed to be smaller, that is, the first line segments6are densely arranged, which can reduce a total width required for arranging the first line segments6in the first direction x. When the distance between two adjacent test pads4is fixed, the distance d3between the first line segments6and the test pad4is increased to space the first line segments6farther from the test pads4. In this way, during the testing of the to-be-tested display panels600, when the test voltage is applied to the test pad4by using a probe, the probe is prevented from being in contact with or near the first line segments6, thereby preventing short circuit between the test pads4and the first line segments6and between two adjacent first line segments6. In some embodiments, when the first electrostatic discharge protection wires5are connected to the pins, short circuit between the pins caused by the short circuit between the test pads4and the first line segments6and the short circuit between two adjacent first line segments6can be prevented, and then false detection caused by a signal transmission error can be further prevented during the testing of the to-be-tested display panels600.

In addition, when a large number of test pads4are arranged in the display panel100and the first line segments6are densely arranged, two adjacent test pads4can also be arranged closer with ensuring a sufficient spacing distance between the first line segments6and the test pads4, thereby reducing a total width required for arranging the test pads4in the first direction x and optimizing the arrangement of the test pads4on a lower bezel. In other words, a total space occupied by the test pads4on the lower bezel can be reduced, helping to optimize the design of a narrow bezel of the display panel100.

In some embodiments, referring toFIG.2again, the distance d3between the test pad4and the first line segment6adjacent thereto in the first direction x is greater than the distance d1between adjacent first line segments6that are arranged between two adjacent test pads4in the first direction x, to ensure a sufficient distance between the test pad4and the first line segment6closest thereto, thereby preventing scratches of the probe on the first line segments6during the testing.

It is to be noted that, in practical applications, the value of the distance d1between the adjacent first line segments6in the first direction x, the value of the distance d2between the adjacent second line segments7in the first direction x, and the value of the distance d3between the test pad4and the first line segment6adjacent thereto in the first direction x can be adjusted according to design parameters such as a designed distance between two adjacent test pads4in the display panel, a designed number of the first electrostatic discharge protection wires5between two adjacent test pads4, and a designed line width of the first electrostatic discharge protection wires5.

For example, when the designed distance between two adjacent test pads4is larger and the number of first electrostatic discharge protection wires5between two adjacent test pads4is smaller, the values of d1, d2, and d3may be designed to be larger. However, if the designed distance between two adjacent test pads4is smaller and the number of first electrostatic discharge protection wires5between two adjacent test pads4is larger, the values of d1, d2, and d3may be designed to be smaller with preventing the foregoing short circuit. That is, the specific values of d1, d2, and d3may be adaptively adjusted according to different display panel structures. The values of d1, d2, and d3are not limited in the embodiments of the present disclosure.

In one or more feasible embodiments, as shown inFIG.3which is another schematic structural diagram of the display panel100andFIG.4which is a schematic diagram of connections of pins9, the display panel100further includes a bonding region8between the display region2and the test region3, and the bonding region8includes a plurality of pins9. The display panel100is bonded to a driver chip or a printed circuit board through the pins9. At least part of the pins9each include a first end connected to a driving signal line10and a second end connected to a first end12of a connection line11, and a second end13of the connection line11is connected to the test pad4. The connection line11includes a fracture14between the first end12and the second end13and is disconnected at the fracture14.

It is to be noted that, referring toFIG.19andFIGS.37A-37D, the fracture14does not exist in the connection lines11in the motherboard200and the connection lines11in the to-be-tested display panels600formed by cutting the motherboard200. In the to-be-tested display panel600, a connection relationship exists among the driving signal lines10, the pins9, the connection lines11, and the test pads4. In this way, when a test voltage is applied to the test pad4, the test voltage can be transferred to the driving signal line10through the connection line11and the pin9, and then drive the display panel100to display a test pattern.

However, after the testing of the to-be-tested display panel600, the fractures14can be formed in the connection lines11by cutting to make the test pads4and the pins9disconnected when forming the display panel100by the to-be-tested display panel600. In this way, the display panel100is formed, the test pads4and the driving signal lines10are disconnected, which can improve reliability of display. In some embodiments of the present disclosure, the connection lines11may be cut by using a laser trimmer process, which reduces a risk of static electricity, is not prone to generate metal particles, and prevents short circuit between adjacent wires.

In addition, it is to be noted that, in some embodiments of the present disclosure, referring toFIG.4, during the laser trimmer process, only the connection lines11are cut off, but the first electrostatic discharge protection wires5are not subjected to the laser. In this way, in the display panel100finally formed, the first electrostatic discharge protection wires5are still continuous, so the first electrostatic discharge protection wires5can still be utilized to discharge static electricity to the first edge1. In some embodiments, as shown inFIG.5which is another schematic diagram of connections of the pins9according to some embodiments of the present disclosure, during the laser trimmer process, the first electrostatic discharge protection wires5are also cut off at the same time, which leads to a lower requirement on process accuracy and reduces process difficulty.

In one or more feasible embodiments, referring toFIG.4andFIG.5again, the second ends of the at least part of the pins9are further connected to the first electrostatic discharge protection wires5. In this way, the first electrostatic discharge protection wires5are connected to the pins9. In this way, static electricity in the to-be-tested display panel600is more easily conducted away via the first electrostatic discharge protection wires5during the testing of the to-be-tested display panel600. Moreover, referring toFIG.5, the first electrostatic discharge protection wires5are not disconnected by cutting of the laser, and when the display panel100is use, the static electricity in the display panel100is also more easily conducted away via the first electrostatic discharge protection wires5.

In one or more feasible embodiments, as shown inFIG.6which is yet another schematic structural diagram of the display panel100andFIG.7which is a schematic diagram of connections between data lines Data and first pads17, the pins9include first pins15, the driving signal lines10include data lines Data located in the display region2, and the connection lines11include a plurality of first connection lines16. First ends of the first pins15are connected to the data lines Data, and second ends of the first pins15are connected to first ends12of the first connection lines16. It is to be noted that the first ends of the first pins15may be connected to the data lines Data in the display region2through fan-out lines located on the lower bezel.

The test pads4include at least two first pads17. Each first pad17is connected to second ends13of multiple ones of the plurality of first connection lines16. The first connection line16has a fracture14between the first end12and the second end13of the first connection line16. That means, the first end12and the second end13of the first connection line16are disconnected. Moreover, the data lines Data corresponding to the first connection lines16connected to different first pads17are different. At least part of the first pads17are arranged along the first direction x, and at least two first pads17adjacent in the first direction x are spaced apart by one another by multiple first electrostatic discharge protection wires5.

In one related design, all the data lines Data in the display region2are connected to only one test pad4. When a test data voltage is applied to the one test pad4, all sub-pixels in the display region2emit light at the same time, and only a single test pattern is displayed. However, due to a huge number, a high pixel density, and a dense arrangement of the sub-pixels in the display region2, there is a high probability of false detection and missing detection during the testing, and thus some sub-pixels that cannot emit light normally are found out.

In some embodiments of the present disclosure, the data lines Data are classified into at least two groups, and each group corresponds to one first pad17, so that the test data voltage can be applied to the at least two first pads17sequentially during the testing of the to-be-tested display panel600. In this way, the to-be-tested display panel600displays multiple test patterns sequentially. When one of the at least first pads17receives the test data voltage, only the sub-pixels corresponding to the data lines Data connected to the one first pad17display the test pattern. The number of sub-pixels emitting light in the test pattern is smaller, so the probability of false detection and missing detection can be greatly reduced during the testing.

In addition, in some embodiments of the present disclosure, the first electrostatic discharge protection wires5are included between the at least two first pads17adjacent in the first direction x, so that the distance between adjacent first pads17can be reduced by reducing the spacing of the first line segments6of the first electrostatic discharge protection wires5, thereby reducing an overall space required by all the first pads17in the first direction x and optimizing the arrangement of the first pads17on the lower bezel.

When one first pad17corresponds to multiple data lines Data, in one or more feasible embodiments, referring toFIG.7, the display panel100further includes a plurality of pixel columns19arranged along the first direction x in the display region2. The pixel column19includes multiple sub-pixels18arranged along the second direction y. The data lines Data include first data lines Data1connected to a 2n-1thpixel column19and second data lines Data2connected to a 2nthpixel column19, where n is a positive integer. For clarity, an ithpixel column inFIG.7is denoted by a reference sign19_i.

The first connection lines16include first-A connection lines16_1and first-B connection lines16_2, first ends of the first-A connection lines16_1are connected to the first data lines Data1respectively, and first ends of the first-B connection lines16_2are connected to the second data lines Data2respectively.

The first pads17include at least one first-A pad17_1and at least one first-B pad17_2, one of the first-A pads17_1is connected to multiple ones of the first-A connection lines16_1, and one of the first-B pads17_2is connected to multiple ones of the first-B connection lines16_2.

Taking the first-A pad17_1as an example, in the to-be-tested display panel600, when the test data voltage is applied to the first-A pad17_1, only the sub-pixels18in the odd-numbered pixel columns19emit light to form a test pattern. Any two adjacent odd-numbered pixel columns19that emit light are at least spaced by one even-numbered pixel column19that does not emit light. Therefore, in each test pattern, each two adjacent pixel columns19that emit light may be spaced by a certain distance. The sub-pixels18that should emit light but fail to emit light can be easily identified.

In some embodiments, as shown inFIG.8, which is another schematic diagram of connections between the data lines Data and the first pads17, the display region2includes at least two sub regions20arranged along the first direction x. At least two first-A pads17_1are provided, and the pixel columns19corresponding to the first-A connection lines16_1connected to the at least two first-A pads17_1are located in at least two different sub regions20respectively. Additionally or alternatively, at least two first-B pads17_2are provided, and the pixel columns19corresponding to the first-B connection lines16_2connected to the at least two first-B pads17_2are located in the at least two sub regions20respectively.

Still taking the first-A pads17_1as an example, in the above arrangement, the odd-numbered pixel columns19are further classified into at least two groups, and each group is located in one sub region20. In this way, during the testing of the to-be-tested display panel600, when the test data voltage is applied to one first-A pad17_1, only the odd-numbered pixel columns19in a certain sub region20emit light and display a test pattern. As a result, any two pixel columns19that emit light are spaced apart, and the pixel columns19that emit light are not arranged too dispersedly in the entire display area2, facilitating identification.

In the example shown inFIG.8, the display region2is divided into two sub regions20, the data lines Data in each sub region20are classified into two groups, and one group corresponds to one first-A pad17_1and the other group corresponds to one first-B pad17_2. However, in other embodiments of the present disclosure, the sub regions2and the data lines Data may also be classified in other manners. For example, the display region2may be divided into three sub regions20, and the data lines Data in each sub region20are classified into two groups that respectively correspond to one first-A pad17_1and one first-B pad17_2. Alternatively, for a same sub region20, the data lines Data corresponding to the odd-numbered pixel columns19in the sub region20may be classified into two groups that respectively correspond to two first-A pads17_1, while the data lines Data corresponding to the even-numbered pixel columns19in the sub region20may be classified into only one group that corresponds to one first-B pad17_2. Examples are not listed one by one in the embodiments of the present disclosure.

When one first pad17corresponds to multiple data lines Data, in some other embodiments, as shown inFIG.9which is yet another schematic diagram of connections between the data lines Data and the first pads17, the display region100further includes a plurality of pixel columns19arranged along the first direction x in the display region2.

The display region2includes at least two sub regions20arranged along the first direction x. The pixel columns19corresponding to the first connection lines16connected to the at least two first pads17are located in the at least two sub regions20respectively.

In the above arrangement, the data lines Data in each sub region20are classified into one group and connected to one first pad17. During the testing of the to-be-tested display panel600, the test data voltage may be applied to the at least two first pads17sequentially, and the sub-pixels18in the at least two sub regions20are controlled to present a test pattern sequentially. As a result, the number of sub-pixels18tested by each test pattern is smaller, and risks of false detection and missing detection are reduced. Moreover, in the arrangement, a smaller number of first pads17are required, which can reduce manufacturing difficulty of a test device.

In one or more feasible embodiments, as shown inFIG.10which is still another schematic diagram of connections between the data lines Data and the first pads17, the pins9include first pins15, the driving signal lines10include data lines Data located in the display region2, and the connection lines11include first connection lines16. First ends of the first pins15are connected to the data lines Data, and second ends of the first pins15are connected to first ends12of the first connection lines16.

The test pads4include first pads17. The first pads17are connected to the second ends13of the first connection lines16in a one-to-one correspondence manner. At least part of the first pads17are arranged along the first direction x, and at least two first pads17adjacent in the first direction x are spaced apart by the first electrostatic discharge protection wires5.

In the above arrangement, during the testing of the to-be-tested display panel600, the test data voltage may be applied to the first pads17sequentially, so that only the pixel column19corresponding to one data line Data, that is connected to the first pad17to which the test data voltage is applied, emits light to present a test pattern at a time. In some embodiments, the test data voltage may be simultaneously applied to some of the first pads17, so that the pixel columns19corresponding to the data lines Data, that are connected to the some first pads17to which the test data voltage is applied, emit light to present a test pattern at a time. In this way, the number of the sub-pixels18tested in each test pattern is small, and the sub-pixels18that cannot emit light normally can be easily identified, greatly reducing the probability of false detection or missing detection.

In addition, in some embodiments of the present disclosure, at least two first pads17adjacent in the first direction x are spaced apart be multiple first electrostatic discharge protection wires5, so that the distance between adjacent first pads17can be reduced by the dense arrangement of the first line segments6of the first electrostatic discharge protection wires5, thereby reducing an overall space required by all the first pads17in the first direction x and optimizing the arrangement of the first pads17on the lower bezel.

In addition, in some embodiments, all the first pads17corresponding to the data lines Data are densely arranged in a middle region of the lower bezel, such that there is more space for arranging the test pads4connected to other signal lines.

In one or more feasible embodiments, as shown inFIG.11which is still another schematic structural diagram of the display panel100, the pins9further include second pins21, the driving signal lines10further include power signal lines22located in the display region2, and the connection lines11further include second connection lines23. A first end of one of the second pins21is connected to one of the power signal lines22, and a second end of one of the second pins21is connected to a first end12of one of the second connection lines23. The pads include second pads24, and the second pads24are connected to second ends13of all the second connection lines23. The second connection line23includes a fracture14between the first end12and the second end13of the second connection line23.

Different from the manner in which the data lines Data are connected to the first pads17, in some embodiments of the present disclosure, in the design of the connection between the power signal lines22and the second pads24, the power signal lines22are not divided into groups, but all the power signal lines22are connected to the second pads24. During the testing, when a test power voltage is applied to the second pads24, no matter which pixel columns19are being driven to display a test pattern, the sub-pixels18in the pixel columns19can receive the test power voltage.

Since the driving signal lines10in the display panel100include multiple kinds of signal lines, if the multiple kinds of signal lines adopt a same grouping and testing method, it may be difficult to balance test accuracy and space saving. However, in the arrangement, the number of second pads24required by the power signal lines22can be reduced, thereby reducing a total number of the test pads4required to be arranged in the display panel100.

In addition, in one related design, a power bus is arranged in a bezel region, the power signal lines22in the display region2are connected to the power bus, and then the power bus is connected to the pins9. However, in order to prevent breakdown of the power bus by static electricity, the power bus may generally have a large width and be required to occupy a larger bezel space in the lower bezel, thereby leading to a larger width of the lower bezel in the second direction y. In the arrangement according to the embodiments of the present disclosure, each power signal line22is extended to the bonding region8and connected to the second pins21, and there is no need to arrange the power bus, so a design size of the lower bezel in the second direction y can also be reduced.

In some embodiments, referring toFIG.11again, the pads include at least two second pads24. In this way, during the testing, the test power voltage may be simultaneously applied to the at least two second pads24, so that the test power voltage is transferred from the at least two second pads24to the power signal lines22in the display region2at the same time, thereby reducing voltage drop of the test power voltage during the transfer.

In one or more feasible embodiments, as shown inFIG.12which is another schematic diagram of connections between power signal lines22and second pads24, the second pins21include second-A pins21_1, the power signal lines22include positive power signal lines PVDD, and the second connection lines23include second-A connection lines23_1. A first end of one of the first-A pins21_1is electrically connected to one of the positive power signal lines PVDD, and a second end of one of the first-A pins21_1is connected to a first end12of one of the second-A connection lines23_1. The second pads24include second-A pads24_1, and the second-A pads24_1are connected to second ends13of all the second-A connection lines23_1.

Additionally or alternatively, the second pins21include second-B pins21_2, the power signal lines22include negative power signal lines PVEE, and the second connection lines23include second-B connection lines23_2. A first end of one of the second-B pins21_2is electrically connected to one of the negative power signal lines PVEE, and a second end of one of the second-B pins21_2is connected to a first end12of one of the second-B connection lines23_2. The second pads24include second-B pads24_2, and the second-B pads24_2are connected to second ends13of all the second-B connection lines23_2.

For example, the sub-pixel18may include a pixel circuit and a light-emitting element. The light-emitting element may be a mini LED. The positive power signal line PVDD is electrically connected to the pixel circuit and configured to transfer a positive power supply voltage to the pixel circuit. The pixel circuit is driven to supply a driving voltage to an anode of the light-emitting element. The negative power signal line PVEE is electrically connected to the light-emitting element and configured to transfer a negative power supply voltage to the light-emitting element. When the anode of the light-emitting element is connected to the driving voltage, the light-emitting element emits light under the action of the driving voltage and the negative power supply voltage.

In one or more feasible embodiments, as shown inFIG.13which is a further schematic structural diagram of the display panel100, the pins9include third pins25, the driving signal lines10include fixed potential signal lines26surrounding the display region2, and the connection lines11include third connection lines27. First ends of the third pins25are connected to the fixed potential signal lines26, and second ends of the third pins25are connected to first ends12of the third connection lines27. The test pads4include third pads28, and the third pads28are connected to second ends13of the third connection lines27.

During the testing of the to-be-tested display panel600, generally, all kinds of signal lines in the to-be-tested display panel600are required to be tested. With reference to the foregoing content, both the data lines Data and the power signal lines22may be extended to the pins9and connected to the pins9, and then connected to the test pads4. In some embodiments of the present disclosure, the fixed potential signal lines26are not extended to the lower bezel but extended in a periphery region around the display region2to the third pins25and connected to the third pins25. In this way, intersections between other connection lines11and the third connection lines27corresponding to the fixed potential signal lines26can be reduced, so that the third connection lines27corresponding to the fixed potential signal lines26can be arranged on a same layer as other connection lines11, without the need to arrange an additional metal wire layer.

In some embodiments, referring toFIG.13again, two ends of each fixed potential signal line26are electrically connected to two third pins25respectively, and each of the two third pins25is connected to one of the third pads28through one of the third connection lines27. During the testing of the to-be-tested display panel600, the test power voltage can be applied to two third pads28at the same time, so that a test fixed voltage on the two third pads28is transferred from the two ends of the fixed potential signal line26to the middle of the fixed potential signal line26at the same time, which reduces voltage drop of the test fixed voltage during the transfer.

In some embodiments, referring toFIG.13again, in the second direction y, the third pins25do not overlap with the display region2. In this way, the fixed potential signal line26connected to the third pins25does not intersect the connection wire (fan-out line) connected between the data line Data and the first pin15and the connection wire connected between the power signal line22and the second pin21. The fixed potential signal line26may be arranged in a same layer as the connection wire (fan-out line) connected between the data line Data and the first pin15and the connection wire connected between the power signal line22and the second pin21.

In one or more feasible embodiments, referring toFIG.13again, the display panel100further includes a protection circuit29, and the fixed potential signal lines26include constant-voltage signal lines30. The constant-voltage signal lines30surround the display region2and are connected to the protection circuit29. In one arrangement, the constant-voltage signal lines30include a first constant-voltage signal line VGH and a second constant-voltage signal line VGL. The protection circuit29may be electrically connected to the data lines Data and configured to protect the data lines Data to prevent the data line Data from being broken down by static electricity.

Additionally or alternatively, referring toFIG.13again, the display panel100further includes first reset signal lines Vref1extending along the second direction y in the display region2. The first reset signal lines Vref1are electrically connected to the pixel circuit and configured to transfer a reset voltage to the pixel circuit to cause the pixel circuit to perform a reset operation. The fixed potential signal lines26include a second reset signal line Vref2. The second reset signal line Vref2surrounds the display region2and are connected to end portions of the first reset signal lines Vref1away from the third pads28. That is, the second reset signal line Vref2and the first reset signal lines Vref1are connected at an upper bezel. When a test reset voltage is transferred on the second reset signal line Vref2, the test reset voltage is quickly transferred to each first reset signal line, so as to be quickly inputted into the sub-pixels18of each pixel column19.

In addition, it is also to be noted that, in some embodiments of the present disclosure, as shown inFIG.14which is a further schematic structural diagram of the display panel100, the bonding region8may include a first bonding region31and two second bonding regions32located on two sides of the first bonding region31in the first direction x. The first pins15are located in the first bonding region31. The first bonding region31is configured for binding the display panel with the driver chip. The second pins21and the third pins25are located in the second bonding regions32. The second bonding regions32are configured for binding the display panel with the printed circuit board. Correspondingly, in order to optimize the routing and layout of the connection lines11, the first pads17are densely arranged on the side of the first bonding region31away from the display region2, the second pads24are located on outer sides of the first pads17in the first direction x, and the third pads28are located on outer sides of the second pads24in the first direction x.

In some embodiments of the present disclosure, the test pads4include the first pads17, the second pads24, and the third pads28, the first electrostatic discharge protection wires5may be arranged between two adjacent first pads17, the first electrostatic discharge protection wires5may be arranged between two adjacent second pads24, and the first electrostatic discharge protection wires5may be arranged between two adjacent third pads28. In some embodiments, the first electrostatic discharge protection wires5may be arranged between adjacent first and second pads17and24, or between two adjacent second and third pads24and28. This is not limited in the embodiments of the present disclosure.

In one or more feasible arrangement, as shown inFIG.15which is a further schematic structural diagram of the display panel100, the test pads4are further connected to second electrostatic discharge protection wires33, and the second electrostatic discharge protection wires33at least extend to the panel edge1.

The connection of the test pads4to the second electrostatic discharge protection wires33can increase electrostatic discharge paths. During the testing of the to-be-tested display panel600, electrostatic charges on the test pads4can be discharged through the second electrostatic discharge protection wires33, so as to improve electrostatic discharge protection capability of the to-be-tested display panel600during the testing.

In one or more feasible embodiments, as shown inFIG.16which is a schematic diagram of arrangement of the test pads4and the first electrostatic discharge protection wires5, the test region3includes at least two pad groups34arranged along the second direction y, and each pad group34includes test pads4arranged along the first direction x. For the first line segments6between adjacent test pads4in each of the pad groups34, the distance between any adjacent first line segments6is less than the distance between adjacent second line segments7.

In the above arrangement, in the case of a large number of test pads4, the test pads4may be arranged in at least two rows with the length of the lower bezel in the first direction x being fixed, which can increase a distance between two adjacent test pads4in the first direction x, thereby further increasing the distance between the test pad4and the first line segment6adjacent thereto and more greatly reducing a risk of short circuit between the first line segments6caused by scratches of the probe on the first line segments6.

It is to be noted that the test pads4in the at least two pad groups34may be aligned or misaligned in the second direction y.

In one or more feasible embodiments, as shown inFIG.17which is a schematic diagram of arrangement of the test pads4and the first electrostatic discharge protection wires5, the test region3includes a pad group34, the pad group34includes at least two pad units35arranged along the first direction x, and each pad unit35includes at least two test pads4arranged along the first direction x. The first electrostatic discharge protection wires5are not arranged between two adjacent test pads4in the pad unit35. The first electrostatic discharge protection wires5are arranged between two adjacent pad units35. For the first line segments6between any adjacent pad units35, the distance between any adjacent first line segments6is less than the distance between adjacent second line segments7.

In the above arrangement, one or two sides of one or more test pads4is not arranged with the first electrostatic discharge protection wire5, so a risk of contact between the probe and the first line segment6can be reduced when the test voltage is applied to the test pads4by using the probe.

In addition, it is also to be noted that, in some embodiments of the present disclosure, the number of the first electrostatic discharge protection wires5may be greater than or equal to the number of the test pads4, and two adjacent test pads4may be spaced apart by a same number of first electrostatic discharge protection wires5or a different number of first electrostatic discharge protection wires5, which is not limited in the embodiments of the present disclosure.

In one or more feasible embodiments, as shown inFIG.18which is a further schematic structural diagram of the display panel100, the driving signal lines10may further include scanning signal lines Scan extending along the first direction x in the display region2. The scanning signal lines Scan are electrically connected to the pixel circuit in the sub-pixels18and configured to transmit a scanning signal to the pixel circuit to control the pixel circuit to perform a reset operation and a charging operation. The pins9further include fourth pins36, the connection lines11further include fourth connection lines38, and the test pads4further include fourth pads40. One end of each scanning signal line Scan is connected to a first end of one of the fourth pins36, or two ends of each scanning signal line Scan are connected to first ends of two of the fourth pins36. Second ends of the fourth pins36are connected to first ends12of the fourth connection lines38, and second ends13of the fourth connection lines38are connected to the fourth pads40.

Additionally or alternatively, the driving signal lines10further include light emission control signal lines Emit extending along the first direction x in the display region2. The light emission control signal lines Emit are electrically connected to the pixel circuits in the sub-pixels18and configured to transmit a light emission control signal to the pixel circuits to control the pixel circuits to perform a light emission control operation. The pins9further include fifth pins37, the connection lines11further include fifth connection lines39, and the test pads4further include fifth pads41. One end of each light emission control signal line Emit is connected to a first end of one of the fifth pins37, or two ends of each light emission control signal line Emit are connected to first ends of two of the fifth pins37. Second ends of the fifth pins37are connected to first ends12of the fifth connection lines39, and second ends13of the fifth connection lines39are connected to the fifth pads41.

During the testing of the to-be-tested display panel600, each fourth pad40applies a test scanning voltage to one corresponding scanning signal line Scan, and each fifth pad41applies a test light emission control voltage to one corresponding light emission control signal line Emit.

It is to be noted that the above design is generally applied to a mini LED display panel. In a liquid crystal display panel and an organic light-emitting diode display panel, the scanning signal lines Scan and the light emission control signal lines Emit are generally electrically connected to a shift register. Driven by signal lines such as clock signal lines and frame start signal lines, the shift register sequentially outputs the scanning signal to the scanning signal lines Scan or sequentially outputs the light emission control signal to the light emission control signal lines Emit. Based on the structure, it just needs to arrange some test pads4for providing test voltages to the signal lines such as the clock signal lines and the frame start signal lines, and the shift register can be normally driven to output signals during the testing. However, in the mini LED display panel, referring toFIG.18, each scanning signal line Scan corresponds to one or two fourth pads40, and each light emission control signal line Emit corresponds to one or two fifth pads41. As a result, a large number of test pads4are required in such display panels, and the number of the test pads4in the mini LED display panel may generally be much greater than the number of the test pads4in the liquid crystal display panel or the organic light-emitting diode display panel. Therefore, the design of the first electrostatic discharge protection wires5according to the embodiments of the present disclosure can bring an improved effect to the mini LED display panel.

Based on a similar inventive concept, some embodiments of the present disclosure further provide a motherboard200.FIG.19is a schematic structural diagram of a motherboard200according to some embodiments of the present disclosure. Referring toFIG.1,FIG.2andFIG.19, the motherboard200includes a plurality of panel regions300. Each panel region300corresponds to a to-be-tested display panel600.

The panel region300includes a first edge400extending along a first direction x, and a display region2and a test region3arranged along a second direction y. The first direction x intersects the second direction y. The test region3is located between the display region2and the first edge400. The test region3includes a plurality of test pads4, at least part of the test pads4are arranged along the first direction x, and at least two of the test pads4adjacent in the first direction x are spaced apart by first electrostatic discharge protection wires5. The first electrostatic discharge protection wires5extend from one side of the display region2adjacent to the test region3to the first edge400.

Referring toFIG.2, each first electrostatic discharge protection wire5includes a first line segment6and a second line segment7, the first line segment6is located between two adjacent test pads4, and the second line segment7is connected to the first line segment6. The distance between adjacent first line segments6between two adjacent test pads4in the first direction x is less than the distance between adjacent second line segments7in the first direction x.

In one manufacturing process of the above display panel100, referring toFIG.19andFIGS.37A-37D, the motherboard200is cut to form a plurality of independent to-be-tested display panels600and then the to-be-tested display panels600are tested, so as to prevent material waste caused by bonding the defective display panel with a driver chip or a printed circuit board. During the testing, test voltages are applied to the test pads4in the to-be-tested display panel600, the test voltages are transferred to various signal lines to control the to-be-tested display panel600to display a test pattern, and then it is determined according to the displayed test pattern whether the to-be-tested display panel600can emit light normally. After being tested, the to-be-tested display panel600is further processed to form the display panel.

In some embodiments of the present disclosure, the distance d1between adjacent first line segments6is reduced, that is, the first line segments6are closer to one another (that is, densely arranged), which can reduce a total arrangement width of the first line segments6in the first direction x. Accordingly, when the distance between two adjacent test pads4is fixed, the distance d3between the first line segment6and the test pad4can be increased, and thus the first line segment6is spaced apart from the test pad4by a reliable distance. In this way, during the testing of the to-be-tested display panel600, the test voltage is applied to the test pad4by a probe, the probe is prevented form scratching the first line segment6, thereby preventing short circuit between the test pad4and the first line segment6and short circuit between two adjacent first line segments6. In some embodiments, the first electrostatic discharge protection wires5are connected to the pins, the short circuit between the test pad4and the first line segment6and short circuit between two adjacent first line segments6may cause short circuit between the pins, and the above configuration can prevent such short circuit between the pins, thereby preventing false detection during the testing of the to-be-tested display panels600.

In addition, when a larger number of test pads4are arranged in the panel region300, with the first line segments6are densely arranged, the distance between two adjacent test pads4can also be reduced on the premise of ensuring a sufficient distances between the first line segment6and the test pad4, thereby reducing a total width required arranging the test pads4in the first direction x and optimizing the arrangement of the test pads4on the lower bezel.

In addition, it is also to be noted that, referring toFIG.19, in the motherboard200, the first electrostatic discharge protection wires5of each panel region300are further extended to the outside of the panel region300and then connected together, and then are led to an outer edge of the motherboard200through a wire. In this way, static electricity generated in the manufacturing process of the motherboard200is discharged to the outside of the motherboard200, and thus electrostatic discharge protection is provided for the motherboard200.

In some embodiments, referring toFIG.2, the distance between the test pad4and the first line segment6adjacent thereto in the first direction x is greater than the distance between adjacent first line segments6that are disposed between two adjacent test pads4in the first direction x. In this way, a sufficient distance between the test pad4and its nearest first line segment6is ensured, thereby preventing the probe from scratching the first line segments6during the testing.

In one or more feasible embodiments, as shown inFIG.20which is a schematic structural diagram of the motherboard200andFIG.21which is a schematic structural diagram of a single to-be-tested display panel600inFIG.20, the panel region300further includes a bonding region8between the display region2and the test region3, and the bonding region8includes a plurality of pins9. At least one of the plurality of pins9each includes a first end electrically connected to one of the driving signal lines10, and a second end electrically connected to one of the test pads4through one of the connection lines11.

Based on the above structure, during the testing of each to-be-tested display panel600, a test voltage is applied to the test pad4, and the test voltage is transferred to the driving signal line10via the connection line11and the pin9and then drives the to-be-tested display panel600to display a test pattern.

In some embodiments, referring toFIG.20andFIG.21again, the second ends of at least part of the pins9are further connected to the first electrostatic discharge protection wires5. In this way, the first electrostatic discharge protection wires5are connected to the pins9, so that static electricity in the to-be-tested display panel600is more easily conducted away via the first electrostatic discharge protection wires5during the testing of the to-be-tested display panel600.

In one or more feasible embodiments, referring toFIG.22toFIG.26, each second line segment7includes a first-type second line segment40. The first-type second line segment40is located on the side of the first line segment6close to the first edge400. The distance between adjacent first-type second line segments40in the first direction x is greater than the distance between adjacent first line segments6located between two adjacent test pads4in the first direction x.

With reference to the foregoing content, in some embodiments of the present disclosure, the motherboard200may form the display panels100in two manners.

FIG.22is a schematic diagram of a partial structure of the motherboard200according to some embodiments of the present disclosure, andFIG.23is a schematic partial enlarged view ofFIG.22. In a first manufacturing process of the display panel100, referring toFIG.1toFIG.5,FIG.22,FIG.23, andFIGS.37A-37D, after the formation of the motherboard200, the motherboard200is cut along cutting lines500to form the plurality of to-be-tested display panels600. The cutting lines500include a first cutting line501. The first cutting line501coincides with the first edge400. Then, the to-be-tested display panels600are tested. After the testing, referring toFIG.3toFIG.5, the connection lines11in the to-be-tested display panel600are cut off by laser, and fractures14are formed on the connection lines11, so as to form the display panel100shown inFIG.3.

That is, the structure where the test pads4are located are kept in the display panel100formed according to the above method. After the testing of the to-be-tested display panel600, reliability of display can be improved by disconnecting the connection lines11between the test pads4and the pins9.

In the above structure, the first-type second line segments40are adjacent to the first edge400, i.e., adjacent to the first cutting line501. In some embodiments of the present disclosure, the distance between adjacent first-type second line segments40is designed to be larger, so that, when the motherboard200is cut along the first cutting line501. In this way, even if a metal particle generated by cutting falls between the adjacent first-type second line segments40, it is difficult for the metal particle to contact both the two first-type second line segments40at the same time, thereby preventing short circuit of the adjacent first-type second line segments40and then preventing adverse effects on the testing.

FIG.24is another schematic structural diagram of the motherboard200according to some embodiments of the present disclosure,FIG.25is a schematic partial enlarged view corresponding toFIG.24, andFIG.26which is a further schematic structural diagram of the display panel100according to some embodiments of the present disclosure. In a second manufacturing process of the display panel100, as shown inFIGS.38A-38CandFIG.24toFIG.26, after the formation of the motherboard200, the motherboard200is cut along cutting lines500to form a plurality of to-be-tested display panels600. The cutting lines500include a first cutting line501. The first cutting line501coincides with the first edge400. Then, the to-be-tested display panels600are tested. After the testing, the to-be-tested display panel600is cut along a second cutting line502to form the display panel100. The second cutting line is located between the pins9and the test pads4.

That is, the structure where the test pads4are located are not kept in the display panel100obtained according to the above method. After the testing of the to-be-tested display panel600, the structure where the test pads4are located is removed by directly cutting along the second cutting line502.

In the above structure, the first-type second line segments40are adjacent to the first edge400, i.e., adjacent to the first cutting line501. In some embodiments of the present disclosure, the distance between adjacent first-type second line segments40is designed to be larger. In this way, when the motherboard200is cut along the first cutting line501, short circuit of the adjacent first-type second line segments40caused by the metal particle generated by cutting can be prevented, thereby preventing adverse effects on the testing.

FIG.27is another schematic partial enlarged view corresponding toFIG.24. In one or more feasible embodiments, referring toFIG.24toFIG.27, each second line segment7includes a second-type second line segment41. The second-type second line segment41is located on a side of the first line segment6away from the first edge400. The distance between adjacent second-type second line segments41is greater than the distance between adjacent first line segments6.

With reference to the above description of the second manufacturing process of the display panel100, after the testing of the to-be-tested display panel600, on the side of the first line segments6away from the first edge400, the to-be-tested display panel600is cut along the second cutting line502. The distance between adjacent second-type second line segments41is designed to be larger. In this way, when the to-be-tested display panel600is cut along the second cutting line502, short circuit of two adjacent first-type second line segments40caused by the metal particle generated by cutting can also be prevented.

FIG.28is yet another schematic structural diagram of the motherboard200according to some embodiments of the present disclosure. In one or more feasible embodiments, as shown inFIG.28, the pins9include first pins15, the driving signal lines10include data lines Data located in the display region2, and the connection lines11include first connection lines16. First ends of the first pins15are electrically connected to the data lines Data, and second ends of the first pins15are electrically connected to the first connection lines16. The test pads4include first pads17, one of the first pads17is electrically connected to multiple ones of the first connection lines16, and different data lines Data are connected to different first pads17.

At least two first pads17of the first pads17are arranged along the first direction x, and the at least two first pads17adjacent in the first direction x are spaced apart by multiple first electrostatic discharge protection wires5.

In some embodiments of the present disclosure, the data lines Data are classified into at least two groups, and each group corresponds to one first pad17. A test data voltage is sequentially applied to the first pads17during the testing of the to-be-tested display panel600, and accordingly the to-be-tested display panel600displays multiple test patterns sequentially. When one of the first pads17receives the test data voltage, only the sub-pixels corresponding to the data lines Data connected to the one first pad17display a test pattern. A smaller number of sub-pixels emit light in each of the multiple test patterns, so the probability of false detection and missing detection can be greatly reduced during the testing.

In addition, in some embodiments of the present disclosure, at least two first pads17adjacent in the first direction x are spaced apart by multiple first electrostatic discharge protection wires5, so that the distance between adjacent first pads17can be reduced by reducing the arrangement width of the first line segments6of the first electrostatic discharge protection wires5in some embodiments of the present disclosure, thereby reducing an overall space required by all the first pads17in the first direction x and optimizing the arrangement of the first pads17on the lower bezel.

FIG.29is a schematic structural diagram of a panel region300according to some embodiments of the present disclosure. As shown inFIG.29, one first pad17corresponds to multiple data lines Data, and the panel region300further includes a plurality of pixel columns19arranged along the first direction x in the display region2. The data lines Data include a first data line Data1electrically connected to a 2n-1thpixel column19and a second data line Data2electrically connected to a 2nthpixel column19, where n is a positive integer. The first connection lines16include a first-A connection line16_1connected to the first data line Data1and a first-B connection line16_2connected to the second data line Data2. The first pads17include at least one first-A pad17_1and at least one first-B pad17_2, one first-A pad17_1is electrically connected to multiple first-A connection lines16_1, and one first-B pad17_2is electrically connected to multiple first-B connection lines16_2.

Taking the first-A pad17_1as an example, when the test data voltage is applied to the first-A pad17_1, only the sub-pixels18in the odd-numbered pixel columns19emit light to form a test pattern. Any two adjacent odd-numbered pixel columns19that are emitting light may be spaced by at least one even-numbered pixel column19that are not emitting light. Therefore, in each test pattern, each two adjacent pixel columns19that are emitting light may be spaced by a certain distance. The sub-pixels18that should but fails to emit light can be easily identified.

In some embodiments, as shown inFIG.30which is another schematic structural diagram of the panel region300, the display region2includes at least two sub regions20arranged along the first direction x. At least two first-A pads17_1are provided, and the at least two first-A pads17_1are connected to pixel columns19located in at least two different sub regions20respectively. In some embodiments, at least two first-B pads17_2are provided, and the at least two first-B pads17_2are connected to pixel columns19located in at least two sub regions20respectively.

Still taking the first-A pad17_1as an example, in the above arrangement, the odd-numbered pixel columns19are further classified into at least two groups, and each group is located in one sub region20. In this way, during the testing of the to-be-tested display panel600, when the test data voltage is applied to one of the first-A pads17_1, only the group of odd-numbered pixel columns19in a certain sub region20displays a test pattern. As a result, any two pixel columns19that are emitting light are spaced by a distance, and the pixel columns19that are emitting light are not too sparsely arranged in the entire display area2, facilitating identification.

FIG.31is yet another schematic structural diagram of the panel region300according to some embodiments of the present disclosure. As shown inFIG.31, one first pad17corresponds to multiple data lines Data, and the display region300further includes a plurality of pixel columns19arranged along the first direction x in the display region2. The display region2includes at least two sub regions20arranged along the first direction x. The pixel columns19connected to different ones of the at least two first pads17are located in different ones of the at least two sub regions20respectively.

In the above arrangement, the data lines Data in each sub region20are classified into one group and correspond to one first pad17. During the testing of the to-be-tested display panel600, the test data voltage may be sequentially applied to the at least two first pads17, and the sub-pixels18in the at least two sub regions20are controlled to sequentially present a test pattern, so that the number of sub-pixels18tested in each test pattern is reduced, thereby reducing risks of false detection and missing detection. Moreover, in the arrangement, a smaller number of first pads17are required, which can reduce manufacturing difficulty of a test device.

FIG.32is still another schematic structural diagram of the motherboard200according to some embodiments of the present disclosure. In one or more feasible embodiments, as shown inFIG.32, the pins9include first pins15, the driving signal lines10include data lines Data located in the display region2, and the connection lines11include first connection lines16. First ends of the first pins15are electrically connected to the data lines Data, and second ends of the first pins15are electrically connected to the first connection lines16.

The test pads4include a plurality of first pads17. The plurality of first pads17are electrically connected to a plurality of first connection lines16in a one-to-one correspondence manner. At least part of the plurality of first pads17are arranged along the first direction x, and at least two first pads17adjacent in the first direction x are spaced apart by multiple of the plurality of first electrostatic discharge protection wires5.

In the above arrangement, during the testing of the to-be-tested display panel600, the test data voltage may be sequentially applied to the plurality of first pads17, so that only the pixel column19corresponding to one data line Data emits light to present a test pattern at a time. In some embodiments, the test data voltage may be simultaneously applied to several of the plurality of first pads17, so that the pixel columns19corresponding to several data lines Data emit light to present a test pattern at a time. In this way, a very small number of sub-pixels18are tested in each test pattern, and the sub-pixels18that cannot emit light normally can be easily identified, greatly reducing the probability of false detection or missing detection

In addition, in some embodiments of the present disclosure, at least two first pads17adjacent in the first direction x are spaced apart by multiple first electrostatic discharge protection wires5, so that the distance between adjacent first pads17can be reduced by reducing the width of the arrangement of the first line segments6of the first electrostatic discharge protection wires5, thereby reducing an overall space required by the first pads17in the first direction x and optimizing the arrangement of the first pads17on the lower bezel.

FIG.33is a further schematic structural diagram of the motherboard200according to some embodiments of the present disclosure. In one or more feasible embodiments, as shown inFIG.33, the pins9include second pins21, the driving signal lines10include power signal lines22located in the display region2, and the connection lines11include second connection lines23. Each second pin21includes a first end electrically connected to one of the power signal lines22, and a second end electrically connected to one of the second connection lines23. The pads include second pads24, and each second pads24is electrically connected to all the second connection lines23.

The manner the power signal lines22being connected to the second pads24is different from the manner the data lines Data being connected to the first pads17. The power signal lines22are not grouped. All the power signal lines22are connected to the second pads24. During the testing, when a test power voltage is applied to the second pads24, no matter which part of the pixel columns19are driven to display a test pattern at a current moment, the sub-pixels18in the pixel columns19can receive the test power voltage.

Since there are many kinds of driving signal lines10in the display panel100, if these kinds of driving signal lines10adopt a same grouping and testing method, it may be difficult to balance test accuracy and space saving. However, in the arrangement, the number of second pads24required by the power signal lines22can be reduced, thereby reducing an overall number of the test pads4required to be arranged on the lower bezel.

In addition, in one related design, a power bus is arranged in a bezel region, the power signal lines22in the display region2are extended to the bezel region and connected to the power bus, and then the power bus is connected to the pins9. However, in order to prevent breakdown of the power bus by static electricity, the power bus may have a large width and occupy a larger bezel space in the lower bezel, thereby leading to a larger width of the lower bezel in the second direction y. In embodiments of the present disclosure, each power signal line22is directly extended to the pin9and connected to the pin9, so there is no need to arrange the power bus, reducing the width of the lower bezel in the second direction y.

In some embodiments, referring toFIG.33again, the pads include at least two second pads24. In this way, during the testing, the test power voltage may be simultaneously applied to at least two second pads24, so that the test power voltage on the at least two second pads24is transferred to the power signal lines22in the display region2at the same time, thereby reducing voltage drop in the test power voltage during the transfer.

FIG.34is a further schematic structural diagram of the motherboard200according to some embodiments of the present disclosure. In some embodiments, as shown inFIG.34, the pins9include third pins25, the driving signal lines10include fixed potential signal lines26surrounding the display region2, and the connection lines11include third connection lines27. First ends of the third pins25are electrically connected to constant-voltage signal lines30, and second ends of the third pins25are electrically connected to the third connection lines27. The test pads4include third pads28, and the third pads28are electrically connected to the third connection lines27.

During the testing of the to-be-tested display panel600, all kinds of signal lines in the to-be-tested display panel600are tested. With reference to the foregoing content, both the data lines Data and the power signal lines22may be extended to the pins9and connected to the pins9, and then connected to the test pads4. In some embodiments of the present disclosure, the fixed potential signal lines26are not directly extended down, but extended around the display region2. The fixed potential signal lines26are extended, through a periphery of the display region2, to the third pins25and connected to the third pins25. In this way, intersections between other connection lines11and the third connection lines27corresponding to the fixed potential signal lines26can be reduced. In this way, the third connection lines27corresponding to the fixed potential signal lines26can be arranged on a same layer as other connection lines11, without the need to arrange an additional metal wire layer.

In some embodiments, referring toFIG.34again, two ends of the fixed potential signal line26are electrically connected to two third pins25respectively, and one of the third pins25is connected to one of the third pads28through one of the third connection lines27. During the testing of the to-be-tested display panel600, the test power voltage can be applied to two third pads28at the same time, so that a test fixed voltage on the two third pads28is transferred from the two ends of the fixed potential signal line26to the middle of the fixed potential signal line at the same time, which reduces voltage drop in the test fixed voltage during the transfer.

In some embodiments, referring toFIG.34again, in the second direction y, the third pins25do not overlap with the display region2. In this way, the fixed potential signal lines26that are connected to the third pins25do not intersect connection wires (fan-out lines) connected between the data lines Data and the first pins15and connection wires connected between the power signal lines22and the second pins21. These wires may be arranged in a same layer.

In one or more feasible embodiments, referring toFIG.34again, the panel region300further includes a protection circuit29, and the fixed potential signal lines26include constant-voltage signal lines30. The constant-voltage signal lines30surround the display region2and are electrically connected to the protection circuit29. In one arrangement, the constant-voltage signal lines30include a first constant-voltage signal line VGH and a second constant-voltage signal line VGL. The protection circuit29may be electrically connected to the data lines Data and configured to protect the data lines Data to prevent the data line Data from static electricity breakdown.

Additionally or alternatively, the panel region300further includes first reset signal lines Vref1extending along the second direction y in the display region2, and the fixed potential signal lines26include a second reset signal line Vref2. The second reset signal line Vref2surrounds the display region2and is connected to ends of the first reset signal lines Vref1away from the third pads28. That is, the second reset signal line Vref2and the first reset signal lines Vref1are connected at an upper bezel. When a test reset voltage is transferred on the second reset signal line Vref2, the test reset voltage may be quickly transferred to each reset signal line and quickly inputted into the sub-pixels18of each pixel column19.

FIG.35is a further schematic structural diagram of the motherboard200according to some embodiments of the present disclosure. In one or more feasible embodiments, as shown inFIG.35, the driving signal lines10may further include scanning signal lines Scan extending along the first direction x in the display region2. Each scanning signal line Scan is electrically connected to the pixel circuit in the sub-pixel18and configured to transmit a scanning signal to the pixel circuit to control the pixel circuit to perform a reset operation and a charging operation. The pins9further include fourth pins36, the connection lines11further include fourth connection lines38, and the test pads4further include fourth pads40. One end of each scanning signal line Scan is connected to a first end of one of the fourth pins36, or two ends of each scanning signal line Scan are connected to first ends of two of the fourth pins36. Second ends of the fourth pins36are connected to the fourth pads40through the fourth connection lines38.

Additionally or alternatively, the driving signal lines10further include light emission control signal lines Emit extending along the first direction x in the display region2. Each light emission control signal line Emit is electrically connected to the pixel circuit in the sub-pixel18and configured to transmit a light emission control signal to the pixel circuit to control the pixel circuit to perform a light emission control operation. The pins9further include fifth pins37, the connection lines11further include fifth connection lines39, and the test pads4further include fifth pads41. One end of each light emission control signal line Emit is connected to a first end of one of the fifth pins37, or two ends of each light emission control signal line Emit are connected to first ends of two of the fifth pins37. Second ends of the fifth pins37are connected to the fifth pads41through the fifth connection lines39.

During the testing of the to-be-tested display panel600, each fourth pad40applies a test scanning voltage to its corresponding scanning signal line Scan separately, and each fifth pad41applies a test light emission control voltage to its corresponding light emission control signal line Emit separately.

As described above, the above design is generally applied to a motherboard200for forming a mini LED display panel. Since each panel region300in the motherboard200is provided with a larger number of test pads4, the configuration of the first electrostatic discharge protection wires5according to the embodiments of the present disclosure can bring a better effect.

Based on a same inventive concept, some embodiments of the present disclosure further provide a method for manufacturing a display panel100.FIG.36is a flowchart of a method for manufacturing a display panel100according to some embodiments of the present disclosure. As shown inFIG.36, the manufacturing method includes the following steps.

In step S1, the motherboard200is formed.

In step S2, the motherboard200is cut to form a plurality of independent to-be-tested display panels600.

In step S3, a test voltage is applied to the test pads4in each to-be-tested display panel600to test the to-be-tested display panel600.

In step S4, the display panel100is formed using the to-be-tested display panel600.

Based on the above analysis of the display panel100and the motherboard200, when the test voltages are applied by a probe to the test pads4in the display panel100formed with the above manufacturing method, a risk of scratching the first line segments6by the probe can be reduced, and short circuit between the test pads4and the first line segments6and short circuit between two adjacent first line segments6can be prevented, thereby preventing false detection during the testing of the to-be-tested display panels600. In addition, when each panel region300is provided with a larger number of test pads4, the arrangement of these test pads4on the lower bezel can also be optimized based on the narrowing design of the arrangement of the first line segments6.

It is to be noted that, when the display panel is a mini LED display panel, after the motherboard200is cut to form the plurality of independent to-be-tested display panels600, a transfer process (such as surface mounting) is further performed to place mini LEDs on the to-be-tested display panels600, and then the to-be-tested display panels600are tested.

In one or more feasible embodiments, referring toFIG.28andFIG.29, the panel region300further includes a bonding region8between the display region2and the test region3, and the bonding region8includes a plurality of pins9. At least one of the plurality of pins9each includes a first end electrically connected to the driving signal line10, and a second end electrically connected to the test pad4through the connection line11.

The pins9include first pins15, the driving signal lines10include data lines Data located in the display region2, and the connection lines11include first connection lines16. First ends of the first pins15are electrically connected to the data lines Data, and second ends of the first pins15are electrically connected to the first connection lines16. The test pads4include at least two first pads17, each one of which is electrically connected to multiple first connection lines16. Different first pads17are connected to different data lines Data. At least part of the at least two first pads17are arranged along the first direction x. At least two first pads17adjacent in the first direction x are spaced apart by multiple first electrostatic discharge protection wires5.

Based on the above structure, the process of applying a test voltage to the test pads4in each to-be-tested display panel600includes: applying the test voltage to at least two first pads17sequentially in each to-be-tested display panel600, to cause the to-be-tested display panel600to sequentially display a plurality of test patterns. When one of the at least two first pads17receives the test data voltage, only the sub-pixels18corresponding to the data lines Data connected to the one first pad17display a test pattern. The number of sub-pixels18emit light in the test pattern is reduced, so the probability of false detection and missing detection can be greatly reduced during the testing.

In one or more feasible embodiments, referring toFIG.3toFIG.5,FIG.22, andFIG.23, the panel region300further includes a bonding region8between the display region2and the test region3, the bonding region8includes a plurality of pins9, first ends of the plurality of pins9are electrically connected to driving signal lines10, and second ends of at least part of the plurality of pins9are electrically connected to the test pads4through connection lines11.

FIGS.37A-37Dare structural flowcharts of the method for manufacturing a display panel according to some embodiments of the present disclosure. As shown inFIGS.37A-37D, step S2may include: cutting the motherboard200along cutting lines500to form the plurality of to-be-tested display panels600, where the cutting lines500include a first cutting line501, and the first cutting line501coincides with the first edge400.

For example, step S4may include cutting off, by laser, the connection lines11in each to-be-tested display panel600to form a fracture14in each of the connection lines11, so as to form the display panel.

That is, the step the test pads4are kept in the display panel100is obtained with the above manufacturing method. After the testing of the to-be-tested display panel600, the connection lines11between the test pads4and the pins9are cut by laser, which can disconnect the test pads4from the pins9. After the display panel100is put into use, reliability of display can be improved. Moreover, since the connection lines11are cut off by laser, a risk of static electricity is reduced, less or no metal particle is generated by cutting, and short circuit between adjacent wires caused by the metal particle generated by cutting is prevented.

In step S3inFIGS.37A-37DandFIGS.38A-38C, the probe is denoted by a reference sign700.

In one or more feasible embodiments, referring toFIG.24toFIG.26, the panel region300further includes a bonding region8between the display region2and the test region3, the bonding region8includes a plurality of pins9, first ends of the plurality of pins9are electrically connected to driving signal lines10, and second ends of at least part of the plurality of pins9are electrically connected to the test pads4through connection lines11.

FIGS.38A-38Care structural flowcharts of the method for manufacturing a display panel according to some embodiments of the present disclosure. As shown inFIGS.38A-38C, step S2may include: cutting the motherboard200along cutting lines500to form the plurality of to-be-tested display panels600, where the cutting lines500include a first cutting line501, and the first cutting line501coincides with the first edge400.

For example, S4may include cutting the to-be-tested display panel600along a second cutting line502to form the display panel100, where the second cutting line502is located between the pins9and the test pads4.

That is, the step where the test pads4are located is not kept in the display panel100obtained with the above manufacturing method. After the testing of the to-be-tested display panel600, the step where the test pads4are located is removed by cutting directly along the second cutting line502. In this way, the display panel100finally formed may have a narrow lower bezel, which optimizes the design of the narrow bezel of the display panel100.

Based on a similar inventive concept, some embodiments of the present disclosure provide a display panel100. The display panel100is manufactured with the above method for manufacturing a display panel100. The display panel100formed by the above manufacturing method may be either the panel structure with the test pads4shown inFIG.3or the panel structure without the test pads4shown inFIG.26.

Based on a same invention concept, some embodiments of the present disclosure further provide a mini LED display device.FIG.39is a schematic structural diagram of a mini LED display device according to some embodiments of the present disclosure. As shown inFIG.39, the display device includes the above display panel100. The specific structure of the display panel100has been described in detail in the above embodiments. Details are not described herein again. It is to be noted that the display panel100may be either the panel structure with the test pads4shown inFIG.3or the panel structure without the test pads4shown inFIG.26.

Certainly, the display device shown inFIG.39is only a schematic illustration, and the display device may be any electronic device with a display function such as a mobile phone, a tablet computer, a notebook computer, an e-book, or a television.

It is to be noted that the number of test pads4in the display panel in the mini LED display device may generally be much greater than the number of test pads4in a display panel of a liquid crystal display device or an organic light-emitting diode display device. In the display panels of the liquid crystal display device and the organic light-emitting diode display device, the scanning signal lines Scan and the light emission control signal lines Emit are generally electrically connected to a shift register and driven by signal lines such as clock signal lines and frame start signal lines. The shift register sequentially outputs a scanning signal to the scanning signal lines Scan or sequentially outputs a light emission control signal to the light emission control signal lines Emit. For the display panels of the liquid crystal display device and the organic light-emitting diode display device, it just needs to arrange test pads4for providing test voltages to the signal lines such as the clock signal lines and the frame start signal lines. Accordingly, the shift register can be driven to output signals during the testing. However, in the display panel of the mini LED display device, referring toFIG.18andFIG.35, each scanning signal line Scan corresponds to one or two fourth pads40, and each light emission control signal line Emit also corresponds to one or two fifth pads41. As a result, a large number of test pads4are required in such display panels. For the mini LED display device with a larger number of test pads4, the application of the design of the first electrostatic discharge protection wires5according to the embodiments of the present disclosure can bring a more significant effect.

The above are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, and the like made within the spirit and the principle of the present disclosure are intended to be included within the protection scope of the present disclosure.

Finally, it should be noted that the above embodiments are merely intended to describe the technical solutions of the present disclosure instead of limiting the present disclosure. Although the present disclosure is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that they can still make modifications to the technical solutions described in the above embodiments, or make equivalent replacements to some or all of the technical features in the technical solutions; and these modifications or replacements do not make the essence of corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present disclosure.