Patent ID: 12230178

DESCRIPTION OF EMBODIMENTS

Embodiments of the disclosure will be described below. Note that, for convenience of description, members having the same functions as the members described earlier may be denoted by the same reference numerals and signs, and the description thereof will not be repeated.

FIG.1is a schematic diagram of a display device100according to the embodiments of the disclosure. The display device100is a specific example of an active matrix type OLED display device. The display device100includes a display control circuit110, a display portion120, a source driver130, a gate driver4, a monitor driver23, and an emission driver5.

Typically, the gate driver4, the monitor driver23, and the emission driver5are formed to be monolithic, but may be configured so as not to be monolithic.

The display device100is further provided with power supply lines ELVDD and ELVSS common to a large number of pixels2. Regarding driving of each light-emitting element, which will be described later, the potential of the power supply line ELVDD is at a high level, and the potential of the power supply line ELVSS is at a low level.

The display control circuit110includes a compensation processing unit112and a temperature detection unit113. The compensation processing unit112compensates for deterioration of a drive transistor and a light-emitting element, which will be described later. The temperature detection unit113detects the temperatures of the pixels2.

The display portion120includes a large number of data lines S and a large number of gate lines G orthogonal to the large number of data lines S. A large number of monitor lines M are provided in the display portion120in one-to-one correspondence with the large number of gate lines G. In the display portion120, a plurality of emission lines E are provided in one-to-one correspondence with the large number of gate lines G. The gate lines G, the monitor lines M, and the emission lines E are typically parallel to each other in the display portion120.

In the display portion120, the pixel2is formed at each of intersections of the data lines S and the gate lines G. The large number of pixels2are disposed in a matrix shape. One pixel2corresponds to one pixel in the display device100and emits, for example, light of any one of red, green, and blue. Further, a unit including one pixel2or a plurality of pixels2adjacent to each other along a certain row is referred to as a pixel unit1. For example, one pixel unit1may emit light of any one of red, green, and blue, or may emit light of a color obtained by combining two or more of these colors.

The display control circuit110receives an input image signal DIN and a group of timing signals (for example, a horizontal synchronization signal, and a vertical synchronization signal) TG sent from the outside of the display control circuit110. The display control circuit110outputs a data signal DA, a source control signal SCTL, a gate control signal GCTL, a monitor driver control signal MCTL, and an emission driver control signal ECTL. The source control signal SCTL is a signal for controlling an operation of the source driver130. The gate control signal GCTL is a signal for controlling an operation of the gate driver4. The monitor driver control signal MCTL is a signal for controlling an operation of the monitor driver23. The emission driver control signal ECTL is a signal for controlling an operation of the emission driver5. The data signal DA is a signal for image display, and is generated by the compensation processing unit112and the temperature detection unit113performing compensation calculation processing on the input image signal DIN in response to monitor data MO supplied from the source driver130. The monitor data MO includes data necessary for obtaining characteristics of the drive transistor, characteristics of the light-emitting element, and a temperature of the pixel2.

The gate driver4is connected to the large number of gate lines G and supplies a scanning signal to each gate line G based on the gate control signal GCTL. The monitor driver23is connected to the large number of monitor lines M and supplies a monitor control signal to each monitor line M based on the monitor driver control signal MCTL. The emission driver5is connected to the large number of emission lines E and supplies an emission control signal to each emission line E based on the emission driver control signal ECTL.

The source driver130includes an output unit133. The output unit133includes a large number of output circuits3301connected to the large number of data lines S in one-to-one correspondence with the large number of data lines S. The output circuit3301supplies a luminance signal to the data line S connected thereto based on the data signal DA. The output circuit3301operates based on the source control signal SCTL and measures a current flowing through the data line S connected thereto.

A large number of initialization lines N are provided in the display portion120. The pixel unit1is formed at each of intersections of the initialization lines N and the gate lines G. The data lines S and the initialization lines N are typically parallel to each other in the display portion120.

The output unit133includes a large number of output circuits3302connected to the large number of initialization lines N in one-to-one correspondence with the large number of initialization lines N. The output circuit3302operates based on the source control signal SCTL, and has a function as an initialization line driver that controls a potential of the initialization line N connected to the output circuit3302itself. The output circuit3302operates based on the source control signal SCTL, and has a function as a monitor circuit that measures a current flowing through the initialization line N connected to the output circuit3302itself.

The display portion120includes a temperature detection circuit3. One temperature detection circuit3is provided for two corresponding pixel units1among the large number of pixel units1. The temperature detection circuit3is required to detect a temperature of one of the pixels2included in the two pixel units1.

In the display device100, the output circuit3301is provided for each of the large number of data lines S, but may be provided in common to two or more data lines S. In the display device100, the output circuit3302is provided for each of the large number of initialization lines N, but may be provided in common to two or more initialization lines N.

First Embodiment

FIG.2is a circuit diagram illustrating a schematic configuration of a main portion101of the display device100according to a first embodiment of the disclosure. The main portion101is illustrated with a first pixel unit1a, a second pixel unit1b, a first temperature detection circuit3a, and the periphery thereof. Each of the first pixel unit1aand the second pixel unit1bis one of the large number of pixel units1. The first temperature detection circuit3ais one temperature detection circuit3.

The first pixel unit1aincludes at least one (here, one) first pixel2a. It is assumed that the first pixel unit1ais disposed at an i-th row and a j-th column in the large number of pixel units1disposed in a matrix. The first pixel2aincludes a first write transistor T1a, a first drive transistor T2a, a first monitor transistor T3a, a first emission transistor T4a, a first initialization transistor T5a, a first capacitor Ca, and a first light-emitting element ELa. Each of the transistors included in the first pixel2ais, for example, an n-channel type MOSFET.

A gate of the first write transistor T1aand a gate of the first initialization transistor T5aare connected to the gate line G(i) in the i-th row corresponding to the first pixel unit1a. The first write transistor T1ais connected between the data line S(j) in the j-th column corresponding to the first pixel unit1aand a gate of the first drive transistor T2a. The first initialization transistor T5ais connected between the first drive transistor T2aand the first initialization line N(j) corresponding to the first pixel unit1a. The first initialization line N(j) is also the initialization line N in the j-th column. When the first initialization transistor T5ais turned on, the first initialization transistor T5aconnects a source of the first drive transistor T2ato the first initialization line N(j), so that a source potential of the first drive transistor T2ais made to be a potential of the first initialization line N(j) (the first drive transistor is initialized).

A gate of the first drive transistor T2ais connected to the data line S(j) via the first write transistor T1a. The first drive transistor T2ais connected between the power supply line ELVDD and the first emission transistor T4a.

A gate of the first monitor transistor T3ais connected to the monitor line M(i) in the i-th row corresponding to the first pixel unit1a. The first monitor transistor T3ais connected between the data line S(j) and the first drive transistor T2a.

A gate of the first emission transistor T4ais connected to the emission line E(i) in the i-th row corresponding to the first pixel unit1a. The first emission transistor T4ais connected between the first drive transistor T2aand an anode of the first light-emitting element ELa.

The anode of the first light-emitting element ELa is connected to the first emission transistor T4a. A cathode of the first light-emitting element ELa is connected to the power supply line ELVSS. One end of the first capacitor Ca is connected between the first write transistor T1aand the gate of the first drive transistor T2a. The other end of the first capacitor Ca is connected between the first drive transistor T2aand the first monitor transistor T3a.

The second pixel unit1bincludes at least one (here, one) second pixel2b. It is assumed that the second pixel unit1bis the pixel unit1disposed at the i-th row and a (j+1)-th column among the large number of pixel units1disposed in the matrix. The second pixel2bincludes a second write transistor T1b, a second drive transistor T2b, a second monitor transistor T3b, a second emission transistor T4b, a second initialization transistor T5b, a second capacitor Cb, and a second light-emitting element ELb. Each of the transistors included in the second pixel2bis, for example, an n-channel type MOSFET.

A gate of the second write transistor T1band a gate of the second initialization transistor T5bare connected to the gate line G(i) corresponding to the second pixel unit1b. The second write transistor T1bis connected between the data line S(j+1) in the (j+1)-th column corresponding to the second pixel unit1band a gate of the second drive transistor T2b. The second initialization transistor T5bis connected between the second drive transistor T2band the second initialization line N(j+1) corresponding to the second pixel unit1b. The second initialization line N(j+1) may be the initialization line N in the (j+1)-th column. When the second initialization transistor T5bitself is turned on, the second initialization transistor T5bconnects a source of the second drive transistor T2bto the second initialization line N(j+1), so that a source potential of the second drive transistor T2bis made to be a potential of the second initialization line N(j+1) (the second drive transistor is initialized).

The gate of the second drive transistor T2bis connected to the data line S(+1) via the second write transistor T1b. The second drive transistor T2bis connected between the power supply line ELVDD and the second emission transistor T4b.

A gate of the second monitor transistor T3bis connected to the monitor line M(i) corresponding to the second pixel unit1b. The second monitor transistor T3bis connected between the data line S(j+1) and the second drive transistor T2b.

A gate of the second emission transistor T4bis connected to the emission line E(i) corresponding to the second pixel unit1b. The second emission transistor T4bis connected between the second drive transistor T2band an anode of the second light-emitting element ELb.

The anode of the second light-emitting element ELb is connected to the second emission transistor T4b. A cathode of the second light-emitting element ELb is connected to the power supply line ELVSS. One end of the second capacitor Cb is connected between the second write transistor T1band the gate of the second drive transistor T2b. The other end of the second capacitor Cb is connected between the second drive transistor T2band the second monitor transistor T3b.

The first temperature detection circuit3aincludes a first temperature detection transistor T6aand a first switch transistor T7a. A gate of the first temperature detection transistor T6ais connected to the first initialization line N(j). The first temperature detection transistor T6ais connected between the power supply line ELVDD and the second initialization line N(j+1). A gate of the first switch transistor T7ais connected to the monitor line M(i) corresponding to the first pixel unit1a. The first switch transistor T7ais connected between the first temperature detection transistor T6aand the second initialization line N(j+1). In other words, the first temperature detection transistor T6ais connected to the second initialization line N(j+1) via the first switch transistor T7a.

The main portion101includes the output circuit3301and the output circuit3302. The output circuit3301is connected to each of the data lines S(j) and S(j+1), and the output circuit3302is connected to each of the first initialization line N(j) and the second initialization line N(j+1).

FIG.3is a circuit diagram illustrating an example of an output circuit330. The output circuit330can be used as any one of the output circuit3301and the output circuit3302. The output circuit330includes an operational amplifier7, a capacitor8, switches9to11, and a signal converter12. An inverting input terminal of the operational amplifier7is connected to a connection target wiring line (any one of the first initialization line N(j), the second initialization line N(j+1), and the data lines S(j) and S(j+1)) to which the output circuit330is connected. An analog voltage Vs is applied to a non-inverting input terminal of the operational amplifier7. The capacitor8and the switch9are connected between an output terminal of the operational amplifier7and the connection target wiring line. The switches9to11are switched on and off by a control clock signal So2, a signal So1, and a signal So0, respectively. The output circuit330is constituted by an integration circuit.

In the output circuit330, when the switch9is turned on by the control clock signal So2, the output terminal and the inverting input terminal of the operational amplifier7are short-circuited. As a result, a potential of the output terminal of the operational amplifier7and a potential of the connection target wiring line become equal to a potential of the analog voltage Vs. By changing the potential of the analog voltage Vs when the switch9is in an on state, the output circuit330can function as an initialization line driver that controls the potential of the connection target wiring line in response to the potential of the analog voltage Vs. In the main portion101, the output circuits3302connected to the first initialization line N(j) and the second initialization line N(j+1) function as initialization line drivers that control a potential of the first initialization line N(j) and a potential of the second initialization line N(j+1), respectively.

In the output circuit330, when the switch9is turned off by the control clock signal So2, the potential of the output terminal of the operational amplifier7changes according to the magnitude of a current flowing through the connection target wiring line due to the presence of the capacitor8. An output signal from the operational amplifier7serves as output data to the signal converter12. The signal converter12performs AD conversion on an output signal from the operational amplifier7and outputs the converted signal as monitor data MO. In this manner, the output circuit330can function as a monitor circuit that performs an output that changes according to the magnitude of a current flowing through the connection target wiring line. In the main portion101, the output circuit3302connected to the second initialization line N(j+1) functions as a monitor circuit that performs an output that changes according to the magnitude of a current flowing through the second initialization line N(j+1). In the main portion101, the output circuits3301connected to the data lines S(j) and S(j+1) also function as monitor circuits that perform outputs that change according to the magnitudes of currents flowing through the data lines S(j) and S(j+1), respectively.

The switch10is connected between the connection target wiring line and the inverting input terminal of the operational amplifier7. The switch10is provided in order to prevent a current from flowing from the connection target wiring line to the output circuit330when the output data of the output circuit330is determined. One end of the switch11is connected between the connection target wiring line and the switch10, and the other end thereof is connected to a voltage source (not illustrated). When a bus line of a panel is disconnected from the source driver side during the AD conversion of the output data from the output circuit330, the switch11switches which of a voltage for black display (V0) or floating (Hi-Z) is to be fixed with the bus line. Since noise is likely to occur in the bus line in the floating state, the bus line can be fixed to the voltage for black display if, by any chance, the noise affects display. It is not essential that the switch11is provided in the output circuit330.

The output data of the output circuit330is the monitor data MO and is sent to the display control circuit110.

When the connection target wiring line is the second initialization line N(j+1), the temperature detection unit113detects characteristics of the first temperature detection transistor T6aassociated with a current value of the output data. Then, the temperature detection unit113detects, as a temperature of the first pixel2a, a temperature at which the first temperature detection transistor T6aexhibits the characteristics detected by the temperature detection unit113.

When the connection target wiring line is the data line S(j), the compensation processing unit112can detect characteristics of the first drive transistor T2afrom a current value of the output data. When the connection target wiring line is the data line S(j+1), the compensation processing unit112can detect characteristics of the second drive transistor T2bfrom a current value of the output data.

FIG.4is a timing chart illustrating an example of potentials of the gate line G(i), the monitor line M(i), the emission line E(i), the data line S, the first initialization line N(j), and the second initialization line N(j+1).

A display period t0is a period of display performed immediately before display in the first pixel unit1a. In the display period to, a potential of the emission line E(i) is switched from a high level to a low level, and each of a potential of the gate line G(i) and a potential of the monitor line M(i) is at a low level. In other words, in the display period t0, the first emission transistor T4ais switched from an on state to an off state, and each of the first write transistor T1a, the first monitor transistor T3a, the first initialization transistor T5a, and the first switch transistor T7ais in an off state. In the display period t0, a potential of the data line S is at a potential Vdata(n−1). The potential Vdata(n−1) is a potential corresponding to the fact that a data signal for display is supplied to the data line S corresponding to a pixel or a pixel unit where display is performed in the display period t0. In the display period to, each of a potential of the first initialization line N(j) and a potential of the second initialization line N(j+1) is set to a potential Vinit, which is an initialization potential, by the corresponding output circuits330, and at this time, a gate potential of the first temperature detection transistor T6ais set to an inactive potential. An active potential and the inactive potential of the gate potential of the first temperature detection transistor T6aare respectively a potential in a state in which the gate potential of the first temperature detection transistor T6ais a high potential for temperature detection, and a potential in a state in which the gate potential of the first temperature detection transistor T6ais not the high potential, and are slightly different from a simple concept of an on/off operation in a switching element.

Subsequently, in a reset period t1, the potential of the gate line G(i) becomes a high level. In other words, in the reset period t1, the first write transistor T1aand the first initialization transistor T5aare turned on. In the reset period t1, the potential of the data line S is an initialization potential Vpc. In the reset period t1, the voltage of the initialization potential Vpc is written to the gate and the source of the first drive transistor T2awhile charges accumulated in the source of the first drive transistor T2aare being initialized by turning on the first initialization transistor T5a.

Subsequently, in a reference voltage write period t2, the potential of the data line S rises from the initialization potential Vpc up to a potential Vref_TFT. The reference voltage write period t2is a period in which a monitor voltage is written to the gate of the transistor to be monitored by the first monitor transistor T3a, that is, the gate of the first drive transistor T2a.

Subsequently, at the end of the reference voltage write period t2, the potential of the gate line G(i) becomes the low level. In other words, at the end of the reference voltage write period t2, the first write transistor T1aand the first initialization transistor T5aare turned off.

Subsequently, the potential of the monitor line M(i) becomes a high level during a line charging current stabilization period t3and a measurement period t4. In other words, the first monitor transistor T3aand the first switch transistor T7aare turned on during the line charging current stabilization period t3and the measurement period t4. In the line charging current stabilization period t3, the potential of the data line S is lowered from the potential Vref_TFT to a potential Vm_TFT. During the line charging current stabilization period t3and the measurement period t4, the output circuit3302connected to the first initialization line N(j) raises the potential of the first initialization line N(j) up to the potential Vref_temp. Similarly, the potential of the second initialization line N(j+1) is changed from the potential Vinit up to a potential Vm_temp. When the potential of the first initialization line N(j) rises to the potential Vref_temp and the potential of the second initialization line N(j+1) changes to the potential Vm_temp, the gate potential of the first temperature detection transistor T6abecomes the potential Vref_temp and a source potential of the first temperature detection transistor T6abecomes the potential Vm_temp, via the first switch transistor T7a, and a current corresponding to the potentials flows. That is, a gate-source voltage of the first temperature detection transistor T6abecomes the potential Vref_temp−the potential Vm_temp, and a current corresponding to the potential Vref_temp−the potential Vm_temp flows. In the line charging current stabilization period t3, the source driver130itself also outputs a voltage corresponding to the potential Vm_temp to the second initialization line N(j+1). In this state, by opening the switch9in the measurement period t4, a current set by the first temperature detection transistor T6aflows through a path of the power supply line ELVDD→the first temperature detection transistor T6a→the first switch transistor T7a, and the current is monitored.

In the line charging current stabilization period t3, the first monitor transistor T3ais turned on by applying the monitor voltage to the data line S. Thus, in the line charging current stabilization period t3, a current flows through the first drive transistor T2a, the first monitor transistor T3a, the data line S(j), and the output circuit3301connected to the data line S(j) in this order.

In the line charging current stabilization period t3, the second initialization line N(j+1) is set to the monitor voltage, the gate potential of the first temperature detection transistor T6ais set to the active potential, and the first switch transistor T7ais turned on. Accordingly, in the line charging current stabilization period t3, a current flows through the first temperature detection transistor T6a, the first switch transistor T7a, the second initialization line N(j+1), and the output circuit3302connected to the second initialization line N(j+1) in this order.

Subsequently, at the end of the measurement period t4, the potential of the monitor line M(i) becomes the low level. In other words, at the end of the measurement period t4, the first monitor transistor T3aand the first switch transistor T7aare turned off.

Next, in an AD conversion period t5, the output circuit3302connected to the first initialization line N(j) decreases the potential of the first initialization line N(j) from the potential Vref_temp to the potential Vinit. Thus, no current flows through the first temperature detection transistor T6a. The potential of the second initialization line N(j+1) is also changed from the potential Vm_temp to the potential Vinit.

The measurement period t4and the AD conversion period t5are periods in which when the current flowing from the data line S to the output circuit3301is stabilized, the output circuit3301measures the current and performs AD conversion so that the current can be read out. Referring toFIG.3and the description thereof, characteristics of the first drive transistor T2acan be detected from output data from the output circuit3301connected to the data line S(j).

The measurement period t4and the AD conversion period t5are periods in which when the current flowing from the second initialization line N(j+1) to the output circuit3302is stabilized, the output circuit3302measures the current and performs AD conversion so that the current can be read out. Referring toFIG.3and the description thereof, characteristics of the first temperature detection transistor T6acan be detected from output data of the output circuit3302connected to the second initialization line N(j+1).

Subsequently, in a data write period t6, the potential of the gate line G(i) becomes the high level, and then, the potential of the emission line E(i) becomes the high level. In other words, in the data write period t6, the first write transistor T1aand the first initialization transistor T5aare turned on, and then, the first emission transistor T4ais turned on. In the data write period t6, the potential of the data line S is the potential Vdata(n). The potential Vdata(n) is a potential corresponding to the fact that a data signal for display is supplied to the data line S(j).

As described above, in the main portion101, the characteristics of the first temperature detection transistor T6acan be detected together with the characteristics of the first drive transistor T2a.

FIG.5is a timing chart illustrating an example of on/off states of the switches9to11of the output circuit330. The on/off states of the switches9to11correspond to high levels and low levels of the control clock signal So2, the signal So1, and the signal So0, respectively.

In the output circuit3302connected to the first initialization line N(j), each of the switches9and10is always in the on state and the switch11is always in the off state (see3302(N(j)) inFIG.5).

In the output circuit3302connected to the second initialization line N(j+1), the switches9to11are turned on and off as follows. The switch9is in the off state during a period from the start of the measurement period t4to the end of the AD conversion period t5, and is in the on state during the other periods. The switch10is in the off state during the AD conversion period t5, and is in the on state during the other periods. The switch11is in the on state during the AD conversion period t5, and is in the off state during the other periods (see3302(N(j+1)) inFIG.5).

In the output circuit3301connected to the data line S, the switches9to11are turned on and off as follows. The switch9is in the off state during a period from the start of the measurement period t4to the end of the AD conversion period t5, and is in the on state during the other periods. The switch10is in the off state during the AD conversion period t5, and is in the on state during the other periods. The switch11is in the on state during the AD conversion period t5, and is in the off state during the other periods (see3301(S) inFIG.5).

FIG.6is a graph for describing an example of a method for detecting a temperature of the first pixel2a. InFIG.6, the horizontal axis represents a gate-source voltage of the first temperature detection transistor T6a, and the vertical axis represents a current flowing through the first temperature detection transistor T6a. According toFIG.6, candidates18to22for characteristics of the first temperature detection transistor T6aare present. Differences among the candidates18to22correspond to differences in temperature of the first pixel2a. The main portion101detects the magnitude of a current flowing through the first temperature detection transistor T6awhen the gate-source voltage of the first temperature detection transistor T6ais equal to the potential Vref_temp−the potential Vm_temp. For this detection, the second initialization line N(j+1) and the output circuit3302connected to the second initialization line N(j+1) are used. Then, the temperature of the first pixel2acan be detected by applying, to any one of the candidates18to22, the magnitude of the current flowing through the first temperature detection transistor T6awhen the gate-source voltage of the first temperature detection transistor T6ais the potential Vref_temp−the potential Vm_temp. For example, in a case where the magnitude of the current flowing through the first temperature detection transistor T6ais a current Ic when the gate-source voltage of the first temperature detection transistor T6ais the potential Vref_temp−the potential Vm_temp, a temperature of the first pixel2acorresponding to the candidate22can be detected as the temperature of the first pixel2a. Note that when the number of candidates for the characteristics of the first temperature detection transistor T6ais small, a new candidate may be created from the existing candidates by linear interpolation.

FIG.7is a graph for describing an example of compensation for a voltage-current characteristic shift of the first drive transistor T2a. InFIG.7, the horizontal axis represents a voltage, and the vertical axis represents a current.

With respect to the first pixel2a, as a mechanism of external compensation, characteristics of the first drive transistor T2aare monitored, and a data voltage (the gate potential of the first drive transistor T2a) at which a target current flows is determined according to the result obtained by the monitoring. Referring toFIG.7, current-voltage characteristics, among the characteristic candidates13to17, corresponding to present deterioration in the first drive transistor T2aare determined from current values measured when the monitoring is performed at several monitor voltages. When the current-voltage characteristics of the first drive transistor T2aare determined, a current to flow through the first light-emitting element20ais determined according to data necessary for display, and thus, the gate potential of the first drive transistor T2ais determined according to the current. Since the above is taken into consideration at a reference temperature, it is necessary to consider temperature characteristics of the first drive transistor T2a. In this case, a plurality of sets of current-voltage characteristic curves of the deterioration characteristics illustrated inFIG.7are considered to be present according to the temperatures. Thus, a set of current-voltage characteristic curves to be used is determined based on temperature information from an external temperature sensor or the like. As a result, the present deterioration characteristics of the first drive transistor T2acan be known, so that it is possible to determine a data voltage for causing a necessary current to flow into the first drive transistor T2a. Since current characteristics of the first light-emitting element20aalso have temperature characteristics, in reality, when the current to be caused to flow into the first light-emitting element20ais determined from the data necessary for display, the current is also determined by using the temperature information. The same applies to each pixel2other than the first pixel2a.

According to the main portion101, the second initialization line N(j+1), which is necessary even in a display device that does not detect a temperature of the first pixel2a, is used as a reading line connected to an output end of the temperature detection circuit3a. Accordingly, it is not necessary to provide an unnecessary bus line in the display device in which the temperature of the first pixel2ais not detected, and thus, the display device100with the high degree of freedom in design can be achieved.

The first switch transistor T7ais connected between the first temperature detection transistor T6aand the second initialization line N(j+1), and the gate thereof is connected to the monitor line M(i). By providing the first switch transistor T7a, conduction and non-conduction between the first temperature detection transistor T6aand the second initialization line N(j+1) can be controlled separately from the active potential and the inactive potential of the gate potential of the first temperature detection transistor T6aitself. This is suitable for selecting the pixel2that is a target for temperature detection from the pixel units1in one column. The first initialization line N(j) is generally common to all the pixel units1included in the same column as that of the first pixel unit1a. Thus, when the first initialization line N(j) sets the gate potential of the first temperature detection transistor T6ato the active potential, the gate potentials of the temperature detection transistors corresponding to all the pixel units1included in the same column as that of the first pixel unit1aare unintentionally set to the active potential. In this case, turning on the first switch transistor T7aand turning off the other switch transistors allow only the first temperature detection transistor T6ato be selectively brought into conduction with the second initialization line N(j+1). However, the conduction and the non-conduction between the first temperature detection transistor T6aand the second initialization line N(j+1) can be minimally controlled by the active potential and the inactive potential of the gate potential of the first temperature detection transistor T6aitself. Due to this, it is not essential that the first switch transistor T7ais provided in the main portion101.

The first switch transistor T7afunctions as a switch that switches between the conduction and the non-conduction between the first temperature detection transistor T6aand the second initialization line N(j+1). Because of this, the first switch transistor T7amay be switched on and off at a gate potential sufficiently higher than that of the first temperature detection transistor T6a. That is, the gate potential of the first temperature detection transistor T6awhen the gate potential of the first temperature detection transistor T6ais switched from the inactive potential to the active potential may be lower than the gate potential of the first switch transistor T7awhen the first switch transistor T7ais switched from the off state to the on state. This corresponds to the fact that the potential Vref_temp is lower than the potential at the high level of the potential of the monitor line M(i) in the timing chart illustrated inFIG.4.

The period in which the gate potential of the first temperature detection transistor T6ais set to the active potential substantially coincides with (at least partially coincides with) the period in which the first switch transistor T7ais set to the on state. This corresponds to most of the line charging current stabilization period t3and the measurement period t4in which the potential of the monitor line M(i) is set to the high level and the potential of the first initialization line N(j) is set to the potential Vref_temp in the timing chart illustrated inFIG.4.

The output circuit3302connected to the second initialization line N(j+1) has a function of a monitor circuit that performs an output that changes according to the magnitude of a current flowing through the second initialization line N(j+1).

On the other hand, the output circuit3302connected to the first initialization line N(j) has a function of an initialization line driver that switches between a first state and a second state. The first state is a state in which the potential of the first initialization line N(j) is the potential Vinit (a first potential) that sets the gate potential of the first temperature detection transistor T6ato the inactive potential. The second state is a state in which the potential of the first initialization line N(j) is the potential Vref_temp (a second potential) that sets the gate potential of the first temperature detection transistor T6ato the active potential.

Since the first temperature detection transistor T6aitself has known temperature characteristics and a flowing current thereinto changes depending on the temperature even at the same gate-source voltage, the value of the monitored current can be converted into a temperature. Since no current flows through the first temperature detection transistor T6aduring displaying by the display device100, deterioration of the first temperature detection transistor T6acan be ignored. Accordingly, the temperature of the first pixel2aaffected by heat generation of the display device100itself can be sensed, and the correction of characteristics of the first drive transistor T2aand the correction of various current values for display corresponding to the sensed temperature can be performed.

Second Embodiment

FIG.8is a circuit diagram illustrating a schematic configuration of a main portion102of the display device100according to a second embodiment of the disclosure. The main portion102is illustrated with the first pixel unit1a, the second pixel unit1b, the first temperature detection circuit3a, and the periphery thereof.

In the main portion102, the first pixel unit1aincludes three first pixels2a. The gate line G(i), the monitor line M(i), the emission line E(i), and the first initialization line N(j) are shared as the common wiring lines by the three first pixels2a, and the data line S(j) is provided for each first pixel2a. The three first pixels2acorrespond to, for example, a pixel that emits red light, a pixel that emits green light, and a pixel that emits blue light.

In the main portion102, the second pixel unit1bincludes three second pixels2b. The gate line G(i), the monitor line M(i), the emission line E(i), and the second initialization line N(j+1) are shared as the common wiring lines by the three second pixels2b, and the data line S(j+1) is provided for each second pixel2b. The three second pixels2bcorrespond to, for example, a pixel that emits red light, a pixel that emits green light, and a pixel that emits blue light.

As described above, each of the numbers of the first pixels2aand the second pixels2bis not limited to one, and may be two or more.

Third Embodiment

FIG.9is a circuit diagram illustrating a schematic configuration of a main portion103of the display device100according to a third embodiment of the disclosure. The main portion103is illustrated with the first pixel unit1a, the second pixel unit1b, a third pixel unit1c, the first temperature detection circuit3a, a second temperature detection circuit3b, and the periphery thereof. The third pixel unit1cis one of the large number of pixel units1. The second temperature detection circuit3bis one temperature detection circuit3.

The main portion103includes the third pixel unit1cand the second temperature detection circuit3bin addition to the configuration of the main portion102.

The third pixel unit1cincludes at least one (here, three) third pixels2c. It is assumed that the third pixel unit1cis the pixel unit1disposed at the i-th row and the (j+2)-th column among the large number of pixel units1disposed in a matrix. The third pixel2cincludes a third write transistor T1c, a third drive transistor T2c, a third monitor transistor T3c, a third emission transistor T4c, a third initialization transistor T5c, a third capacitor Cc, and a third light-emitting element ELc. Each of the transistors included in the third pixel2cis, for example, an n-channel type MOSFET.

A gate of the third write transistor T1cand a gate of the third initialization transistor T5care connected to the gate line G(i) corresponding to the third pixel unit1c. The third write transistor T1cis connected between the data line S(j+2) in the (j+2)-th column corresponding to the third pixel unit1cand a gate of the third drive transistor T2c. The third initialization transistor T5cis connected between the third drive transistor T2cand a third initialization line N(j+2) corresponding to the third pixel unit1c. The third initialization line N(j+2) is also the initialization line N in the (j+2)-th column. When the third initialization transistor T5citself is turned on, the third initialization transistor T5cconnects a source of the third drive transistor T2cto the third initialization line N(j+2), so that a source potential of the third drive transistor T2cbecomes a potential of the third initialization line N(j+2) (the third drive transistor is initialized).

A gate of the third drive transistor T2cis connected to the data line S(j+2) via the third write transistor T1c. The third drive transistor T2cis connected between the power supply line ELVDD and the third emission transistor T4c.

A gate of the third monitor transistor T3cis connected to the monitor line M(i) corresponding to the third pixel unit1c. The third monitor transistor T3cis connected between the data line S(j+2) and the third drive transistor T2c.

A gate of the third emission transistor T4cis connected to the emission line E(i) corresponding to the third pixel unit1c. The third emission transistor T4cis connected between the third drive transistor T2cand an anode of the third light-emitting element ELc.

The anode of the third light-emitting element ELc is connected to the third emission transistor T4c. A cathode of the third light-emitting element ELc is connected to the power supply line ELVSS. One end of the third capacitor Cc is connected between the third write transistor T1cand the gate of the third drive transistor T2c. The other end of the third capacitor Cc is connected between the third drive transistor T2cand the third monitor transistor T3c.

The second temperature detection circuit3bincludes a second temperature detection transistor T6band a second switch transistor T7b. A gate of the second temperature detection transistor T6bis connected to the second initialization line N(j+1). The second temperature detection transistor T6bis connected between the power supply line ELVDD and the third initialization line N(j+2). A gate of the second switch transistor T7bis connected to the monitor line M(i) corresponding to the second pixel unit1b. The second switch transistor T7bis connected between the second temperature detection transistor T6band the third initialization line N(j+2). In other words, the second temperature detection transistor T6bis connected to the third initialization line N(j+2) via the second switch transistor T7b.

The output circuit3301is connected to the data line S(j+2), and the output circuit3302is connected to the third initialization line N(j+2).

In the main portion103, relationships among the first pixel unit1a, the second pixel unit1b, the first temperature detection circuit3a, and the periphery thereof are similar to relationships among the second pixel unit1b, the third pixel unit1c, the second temperature detection circuit3b, and the periphery thereof. Thus, in the main portion103, a temperature of the second pixel2bcan be detected by using the second temperature detection circuit3bin a manner similar to that of detecting a temperature of the first pixel2aby using the first temperature detection circuit3a.

That is, the display device100may include at least one third pixel2cincluding the third drive transistor T2cand the third initialization transistor T5cthat initializes the third drive transistor T2c, the third initialization line N(j+2) connected to the third drive transistor T2cvia the third initialization transistor T5c, and the second temperature detection transistor T6bconnected to the third initialization line N(j+2), the second temperature detection transistor T6bincluding a gate connected to the second initialization line N(j+1). Thus, although measurement is required twice, there is an advantage that a temperature distribution can be seen in detail.

Supplement

A display device according to a first aspect of the disclosure includes at least one first pixel including a first drive transistor and a first initialization transistor configured to initialize the first drive transistor, at least one second pixel including a second drive transistor and a second initialization transistor configured to initialize the second drive transistor, a first initialization line connected to the first drive transistor via the first initialization transistor, a second initialization line connected to the second drive transistor via the second initialization transistor, and a first temperature detection transistor connected to the second initialization line, the first temperature detection transistor including a gate connected to the first initialization line.

In a display device according to a second aspect of the disclosure, in the first aspect, the first pixel includes a monitor transistor connected to the first drive transistor, and the display device includes a monitor line connected to a gate of the monitor transistor, and a switch transistor connected between the first temperature detection transistor and the second initialization line, the switch transistor including a gate connected to the monitor line.

In a display device according to a third aspect of the disclosure, in the second aspect, a gate potential of the first temperature detection transistor at which the gate potential of the first temperature detection transistor is switched from an inactive potential to an active potential is lower than a gate potential of the switch transistor at which the switch transistor is switched from an off state to an on state.

In a display device according to a fourth aspect of the disclosure, in the second or third aspect, at least a part of a period in which a gate potential of the first temperature detection transistor is an active potential coincides with at least a part of a period in which the switch transistor is in an on state.

A display device according to a fifth aspect of the disclosure further includes, in any one of the first to fourth aspects, a monitor circuit connected to the second initialization line, the monitor circuit being configured to perform an output that changes according to a magnitude of a current flowing through the second initialization line.

In a display device according to a sixth aspect of the disclosure, in the fifth aspect, the monitor circuit performs the output when a write transistor included in the first pixel is in an off state.

A display device according to a seventh aspect of the disclosure further includes, in any one of the first to sixth aspects, an initialization line driver configured to switch between a first state in which a potential of the first initialization line is a first potential at which a gate potential of the first temperature detection transistor is set to an inactive potential and a second state in which the potential of the first initialization line is a second potential at which the gate potential of the first temperature detection transistor is set to an active potential.

In a display device according to an eighth aspect of the disclosure, in the seventh aspect, the initialization line driver is connected to the first initialization transistor and the gate of the first temperature detection transistor.

In a display device according to a ninth aspect of the disclosure, in the seventh or eighth aspect, the first potential is a potential configured to initialize the first drive transistor.

In a display device according to a tenth aspect of the disclosure, in any one of the seventh to ninth aspects, the initialization line driver does not perform an output that changes according to a magnitude of a current flowing through the first initialization line.

A display device according to an eleventh aspect of the disclosure further includes, in any one of the first to tenth aspects, at least one third pixel including a third drive transistor and a third initialization transistor configured to initialize the third drive transistor, a third initialization line connected to the third drive transistor via the third initialization transistor, and a second temperature detection transistor connected to the third initialization line, the second temperature detection transistor including a gate connected to the second initialization line.

The disclosure is not limited to each of the embodiments described above, and various modifications may be made within the scope of the claims. Embodiments obtained by appropriately combining technical approaches disclosed in each of the different embodiments also fall within the technical scope of the disclosure. Furthermore, novel technical features can be formed by combining the technical approaches disclosed in each of the embodiments.