Patent ID: 12225706

DETAILED DESCRIPTION

Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be understood as limited to the embodiments set forth herein. Conversely, these embodiments are provided to make the disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. In the drawings, the same reference numerals represent the same or similar structures, and thus the detailed description will be omitted.

Although relative terms, such as “upper” and “lower”, are used in the specification to describe the relative relationship of one component to another component, these terms are used herein for convenience only, for example, according to the direction of the examples as shown in the drawings. It can be understood that if the device in the drawings is turned upside down, the components described as “upper” will become the “lower” components. When one structure is “on” the other structure, it is possible to indicate that the structure is integrally formed on the other structure, or the structure is “directly” disposed on the other structure, or the structure is “indirectly” disposed on the other structure by means of another structure.

The terms “a”, “an”, “the”, and “said” are used to express the presence of one or more elements/parts/or the like. The terms “include” and “have” are used to be inclusive, and mean there may be additional elements/parts/or the like in addition to the listed elements/parts/or the like. The terms “first” and “second” are only used as markers, not as a restriction on the number of objects.

A capacitor mainly includes a conductive contact plug and a storage capacitor connected to the surface of the conductive contact plug. After the conductive contact plug is formed, the DRAM conducts an electrical test thereon to verify the electrical performance of the conductive contact plug. During this process, an oxide layer is easily formed on the surface of the conductive contact plug, resulting in poor contact between the conductive contact plug and the storage capacitor.

In some implementations, as shown inFIG.1andFIG.2, a semiconductor structure mainly includes a substrate100as well as an insulating layer200and conductive contact plugs300formed on the substrate100. In order to ensure the electrical performance of a Dynamic Random-Access Memory (DRAM), an electrical test needs to be conducted thereon during a manufacturing process. During this process, the conductive contact plugs300are exposed to the external environment, and surfaces thereof are likely to be oxidized to generate oxide crystal nuclei400. Under high temperature conditions of the electrical test, the oxide crystal nuclei400further grow into an oxide crystal. The oxide crystal is not easy to be washed away by acid, resulting in poor contact between the conductive contact plugs300and a capacitor. Under high temperature conditions, thermal migration is likely to occur between two adjacent conductive contact plugs300, such that the two adjacent conductive contact plugs300communicate with each other, and a short circuit is likely to occur between the two adjacent conductive contact plugs300(region A as shown inFIG.2).

Embodiments of the disclosure provide a method for manufacturing a semiconductor structure. As shown inFIG.3, the manufacturing method can include:step S110: providing a substrate;step S120: forming a first insulating layer covering the substrate, and patterning the first insulating layer to form a plurality of vias and a plurality of isolation grooves that are alternatingly distributed;step S130: forming conductive contact plugs in the vias respectively, where the conductive contact plugs cover bottoms of the vias and each includes a first region and a second region adjacent to each other, and the conductive contact plugs located in the first regions cover outer walls of the isolation structures and extend along the outer walls to surfaces of the isolation structures distal from the substrate; andstep S140: forming a passivation layer covering side walls and surfaces of the conductive contact plugs.

According to the method for manufacturing a semiconductor structure of the disclosure, charges in a storage capacitor can be stored through the conductive contact plugs. During this process, on the one hand, the conductive contact plugs can be supported by the top surfaces of the isolation structures to avoid the collapse of capacitor holes. On the other hand, the surfaces of the conductive contact plugs can be protected by the passivation layer to prevent the surfaces of the conductive contact plugs from being oxidized during an electrical test, and ensure that the conductive contact plugs maintain good contact with the storage capacitor, thereby improving the electrical performance of the semiconductor device. In addition, the passivation layer can form a barrier between two adjacent contact plugs, which can reduce the thermal migration effect of tungsten plugs in the subsequent heat treatment process, and reduce the risk of device failure. Furthermore, since the second regions of the conductive contact plugs are located in the bottoms of the vias, two adjacent vias are separated by an isolation structure, such that two adjacent conductive contact plugs are separated by the isolation structure, thus the communication between the two adjacent conductive contact plugs can be avoided, and the risk of a short circuit between the two adjacent conductive contact plugs can be reduced.

The following describes in detail the steps of the manufacturing method according to the embodiments of the disclosure.

In step S110, the substrate is provided.

The substrate can be of a flat structure, which can be a rectangle, a circle, an ellipse, a polygon or an irregular figure, and the material thereof can be silicon or other semiconductor materials. The shape and material of the substrate are not specifically limited here. It should be noted that the substrate of the disclosure can include semiconductor structures such as word lines and bit lines, which are not shown in the drawings because they do not involve the technical features of the disclosure.

In step S120, the first insulating layer covering the substrate is formed, and the first insulating layer is patterned to form the plurality of vias and the plurality of isolation structures that are alternatingly distributed.

As shown inFIG.4, the first insulating layer2can be formed on the substrate1. The first insulating layer2can be a thin film formed on a surface of the substrate1. The first insulating layer2can be formed on the substrate1by means of chemical vapor deposition, atomic layer deposition or the like. Certainly, the first insulating layer2can also be formed by means of other methods, which will not be listed here. The first insulating layer2can have the same shape as the substrate1, the material thereof can be silicon nitride, silicon oxide, etc., and the material is not specifically limited here.

The first insulating layer2can be patterned to form the plurality of vias21and the plurality of isolation structures22that are alternatingly distributed. As shown inFIG.5, the isolation structure22can be groove-like structures. The vias21can be circular, rectangular, or in other shapes. The shapes of the vias21and the isolation structures22are not specifically limited here. Each via21and the isolation structure22adjacent thereto can form a group, and thus multiple groups of structures can be formed. The via21and the isolation structure22in each group can be arranged adjacent to each other, and a side wall of the via21proximal to the isolation structure22can be adjacent to the bottom of the isolation structure22. Moreover, the bottom surface of the via21can be lower than the bottom surface of the isolation structure22, such that the vias21are separated by the isolation structures22and the first insulating layer2located in the bottoms of the isolation structures22. The isolation structures22and the vias21in two adjacent groups of structures can be separated by the top surfaces of the isolation structures22, and the top surfaces of the isolation structures22can be configured to support the conductive contact plugs3to prevent the conductive contact plugs3from collapse.

The vias21and the isolation structures22can be formed on the first insulating layer2by means of a photolithography process. It is possible to form the vias21and the isolation structures22by photo-etching multiple times, that is, it is possible to form the vias21by first etching and then form the isolation structures22by second etching. Certainly, it is also possible to form the vias21and the isolation structures22simultaneously by one etching process. The formation process for the vias21and the isolation structures22is not specifically limited here.

In step S130, the conductive contact plugs are formed in the vias respectively. The conductive contact plugs cover bottoms of the vias and each includes a first region and a second region adjacent to each other, and the conductive contact plugs located in the first regions cover the outer walls of the isolation structures and extend along the outer walls to the surfaces of the isolation structures distal from the substrate.

As shown inFIG.6, the conductive contact plugs3can be formed in the vias21respectively, such that the conductive contact plugs3are distributed at intervals. The conductive contact plug3can be in contact with the storage capacitor, and can store the charges in the storage capacitor. The conductive contact plugs3can cover the bottoms of the vias21and can be electrically connected to the substrate1through the vias21for signal transmission with the word lines and the bit lines in the substrate1. As shown inFIG.6andFIG.7, the conductive contact plugs3each can include a first region31and a second region32(region B as shown in the drawings) adjacent to each other. The conductive contact plugs3located in the first regions31can cover the outer walls of the isolation structures22and can extend along the outer walls to the surfaces of the isolation structures22distal from the substrate. The surfaces of the conductive contact plugs3located in the second regions32distal from the substrate1can be lower than the surface of the first insulating layer2distal from the substrate1. That is, one end of the conductive contact plugs3can extend along the side walls of the vias21proximal to the top surfaces of the isolation structures22to the top surfaces of the isolation structures22, and the surface of the other end distal from the substrate1can be lower than the surface of the first insulating layer2distal from the substrate1. The contact area between the conductive contact plugs3and the insulating layer can be increased, and two adjacent conductive contact plugs3can also be separated by an isolation structure22, thus the communication between the two adjacent conductive contact plugs3can be avoided, and the risk of a short circuit between two adjacent conductive contact plugs3can be reduced.

The conductive contact plugs3can be made of a conductive material, for example, the material can be tungsten, copper or polysilicon, etc., and certainly, can also be other conductive materials, which are not listed here. The conductive contact plugs3can be formed in the vias21by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Certainly, the conductive contact plugs3can also be formed by means of other method. The formation process for the conductive contact plugs3is not specifically limited here.

In an embodiment of the disclosure, forming the isolation structures22and the conductive contact plugs3can include step S210to step S250, as shown inFIG.8.

At step S210, the first insulating layer is formed on the substrate by using a chemical vapor deposition process.

The first insulating layer2can be made of an insulating material to isolate the conductive contact plugs3, the material thereof can be silicon nitride, silicon oxide, etc., and the material is not specifically limited here. The first insulating layer2can be a thin film formed on the substrate1, and can completely cover the surface of the substrate1. In an embodiment, the first insulating layer2can be formed on the substrate1by using a chemical vapor deposition process. Certainly, the first insulating layer2can also be formed by means of other methods, which are not specifically limited here.

At step S220, the first insulating layer is patterned to form the plurality of vias that are distributed at intervals.

The plurality of vias21that are distributed at intervals can be formed on the first insulating layer2by using a photolithography process. The vias21can respectively expose the substrate1, such that other structures are connected to the substrate1through the vias21.

For example, a mask material layer can be formed on the surface of the first insulating layer2distal from the substrate1by means of chemical vapor deposition, vacuum evaporation, atomic layer deposition or other methods, and a photoresist layer can be formed on the surface of the mask material layer distal from the substrate1by means of spin coating or other methods. The material of the photoresist layer can be positive photoresist or negative photoresist, which is not specifically limited here.

The photoresist layer can be exposed by using a mask, and the pattern of the mask can match the pattern required by the first insulating layer2. Subsequently, the exposed photoresist layer can be developed to form a plurality of development regions. Each development region can expose the mask material layer, and the pattern of the development region can be the same as the pattern required by the first insulating layer2. The width of the development region can be the same as the size required by the vias21.

The mask material layer can be etched in the development region by means of a plasma etching process, and the first insulating layer2can be exposed in the etched region, so as to form a required mask pattern on the mask material layer. Moreover, the first insulating layer2is patterned according to the mask pattern to obtain each via21. It should be noted that after the above-mentioned etching process is completed, the photoresist layer and the mask material layer can be removed to expose the formed vias21.

At step S230, a conductive layer covering the first insulating layer is formed. The conductive layer is capable of filling the vias.

As shown inFIG.9, the conductive layer301can be formed on the surface of the first insulating layer2distal from the substrate1by means of vacuum evaporation or chemical vapor deposition. During this process, the conductive layer301can fill the vias21in the first insulating layer2. Moreover, the conductive layer can be in contact with the substrate1through the vias21. The conductive layer301can be made of a conductive material, for example, the material thereof can be tungsten, copper or polysilicon, etc., and certainly, can also be other conductive materials, which are not specifically limited here.

At step S240, the conductive layer and the first insulating layer are etched by using a dry etching process to form the plurality of isolation structures. The isolation structures and the vias are alternatingly distributed. The conductive layer has openings respectively exposing the isolation structures, and the openings all partially overlap the vias, respectively.

As shown inFIG.10, the conductive layer301and the first insulating layer2can be etched by using a dry etching process to form the openings302in the conductive layer301, and also to form the plurality of isolation structures22in the first insulating layer2. In an embodiment, the isolation structures22are all groove-shaped, and the isolation structures22can be alternatingly distributed with the vias21in the first insulating layer2. The openings302can respectively expose the isolation structures22. It should be noted that the number of the openings302can be equal to that of the vias21in the first insulating layer2. The openings302can be arranged in a one-to-one correspondence with the vias21. Moreover, partial regions of the openings302can respectively overlap partial regions of the corresponding vias21, and the orthographic projections of the remaining partial regions on the isolation structures22adjacent to the vias21can overlap the boundaries of the isolation structures22.

For example, a mask layer7can be formed on the side of the conductive layer301distal from the first insulating layer2by means of chemical vapor deposition or other methods. The material of the mask material layer can be at least one of silicon nitride, polysilicon, or carbon, and certainly, can also be other materials, which are not listed here. The mask material layer can be a single-layer structure or a multi-layer structure, which is not specifically limited here.

In an embodiment, as shown inFIG.9, the mask layer7can be a multi-layer structure, which can include a carbon layer71, a silicon nitride layer72, and a polysilicon layer73stacked in sequence. The carbon layer71can formed on the surface of the conductive layer301distal from the first insulating layer2. The silicon nitride layer72can be located between the carbon layer71and the polysilicon layer73. The carbon layer71can be formed on the surface of the conductive layer301distal from the first insulating layer2by means of a chemical vapor deposition process. The silicon nitride layer72can be formed on the surface of the carbon layer71distal from the conductive layer301by means of an atomic layer deposition process. The polysilicon layer73can be formed on the surface of the silicon nitride layer72distal from the carbon layer71by means of a chemical vapor deposition process.

A photoresist layer can be formed on the surface of the mask layer7distal from the conductive layer301by means of spin coating or other methods. The material of the photoresist layer can be positive photoresist or negative photoresist, which is not specifically limited here.

The photoresist layer can be exposed by using a mask, and the pattern of the mask can match the pattern required by the openings302of the conductive layer301. Subsequently, the exposed photoresist layer can be developed to form a plurality of development regions. Each development region can expose the mask layer7, and the pattern of the development region can be the same as the pattern required by the conductive layer301. The width of the development region can be the same as the size required by the openings302.

The mask layer7can be etched in the development region by means of a plasma etching process, and the conductive layer301can be exposed in the etched region, so as to form a required mask pattern on the mask layer7. It should be noted that when the mask layer7is a single-layer structure, the mask pattern can be formed by one etching process. When the mask layer7is a multi-layer structure, film layers can be etched in layers, that is, one layer can be etched by one etching process, and the mask layer7can be thoroughly etched by multiple etching processes to form the mask pattern.

It should be noted that after the above-mentioned etching process is completed, the photoresist layer can be removed by processes such as cleaning with a cleaning liquid or ashing, such that the mask layer7is no longer covered by the photoresist layer, and the formed mask layer7is exposed to obtain a hard mask structure, as shown inFIG.10. The conductive layer301and the first insulating layer2can be plasma-etched according to the mask pattern to form the plurality of isolation structures22in the first insulating layer2.

It should be noted that the conductive layer301and the first insulating layer2can be etched in stages, that is, the conductive layer301can be etched first to form the plurality of openings302. The openings302can partially overlap the vias21in the first insulating layer2respectively and can expose the first insulating layer2. Then, the first insulating layer2and the conductive layer301filling the vias21are synchronously etched at the openings302to form the isolation structures22.

In step S250, the conductive layer in portions of the vias overlapping the openings is etched to form the conductive contact plugs having the first regions and the second regions. The conductive contact plugs located in the first regions cover the outer walls of the isolation structures and extend along the outer walls to the surfaces of the isolation structures distal from the substrate, and surfaces of the conductive contact plugs located in the second regions distal from the substrate are lower than a surface of the first insulating layer distal from the substrate.

The conductive layer301in the vias21overlapping the openings302can be selectively etched by using a first gas and a second gas by means of a plasma process, so as to form the conductive contact plugs3having the first regions31and the second regions32. In an embodiment, the conductive contact plugs3located in the first regions31cover the outer walls of the isolation structures22and extend along the outer walls to the surfaces of the isolation structures22distal from the substrate1, and the surfaces of the conductive contact plugs3located in the second regions32distal from the substrate1are lower than the surface of the first insulating layer2distal from the substrate1. Thus, the communication between the conductive contact plugs3can be reduced. For example, the conductive contact plugs3can be in a deep Z shape.

In an embodiment, the first gas can be chlorine, and the second gas can be nitrogen trifluoride (NF3) or hydrogen bromide (HBR). The etching ratio of the conductive contact plugs3to the first insulating layer2during the etching process can be controlled by separately controlling the flow of the first gas and the second gas. For example, the etching ratio of the conductive contact plugs3to the first insulating layer2is not less than 100:1.

It should be noted that the first gas and the second gas can also be other gases, as long as the conductive contact plugs3can be etched thereby without damaging other film layers. The gases are not specifically limited here.

In step S140, a passivation layer covering side walls and surfaces of the conductive contact plugs is formed.

As shown inFIG.11, the passivation layer4can be formed on the side walls and the surface of the conductive contact plugs3. The passivation layer4can block oxygen. The surfaces of the conductive contact plugs3can be protected by the passivation layer4to prevent the surfaces of the conductive contact plugs3from being oxidized due to excessive temperature during the electrical test, which affects the performance of the device.

The passivation layer4can be made of a conductive material, and the storage capacitor can be electrically connected to the conductive contact plugs3through the passivation layer4. In an embodiment, the material of the passivation layer can be tungsten nitride. That is, the conductive contact plugs3can be tungsten plugs. The surfaces of the tungsten plugs can be treated by means of a hydrogen or nitrogen plasma treatment process to form the passivation layer4on the surfaces of the tungsten plugs. For example, by means of the hydrogen and nitrogen plasma treatment on the surfaces of the tungsten plugs, not only the tungsten oxide formed by oxidation on the surfaces of the tungsten plugs can be removed, but also tungsten nitride can be formed on the surfaces of the tungsten plugs while removing the tungsten oxide. The tungsten nitride can be used as the passivation layer4to protect the surfaces of the tungsten plugs and prevent the surfaces of the tungsten plugs from being further oxidized. In addition, the thermal migration effect of the tungsten plugs in the subsequent heat treatment process can be reduced, thereby reducing the risk of device failure. Furthermore, since tungsten nitride is a conductive material, the storage capacitor and the tungsten plugs can be electrically connected through the tungsten nitride to ensure the performance of the semiconductor device.

Certainly, the passivation layer4can also be formed on the side walls and surfaces of the conductive contact plugs3by means of vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. The formation process for the passivation layer4is not specifically limited here.

The passivation layer4should not be too thick, so as not to affect the conductivity of the conductive contact plugs and thus affect the performance of the semiconductor structure, and the thickness thereof can range from 3 nm to 8 nm. For example, the thickness can be 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, or 8 nm. Certainly, the passivation layer4can also have other thicknesses, which are not listed there.

In an embodiment of the disclosure, the manufacturing method of the disclosure can further include the following step.

At step S150, a protective layer is formed on a surface of the passivation layer. The protective layer covers the side walls of the conductive contact plugs, and extends to the side walls of the isolation structures for supporting the conductive contact plugs.

As shown inFIG.12, the protective layer5can be formed on the surface of the passivation layer4by means of chemical vapor deposition or atomic layer deposition. The protective layer5can cover the side walls of the passivation layer4and can extend to the side walls of the isolation structures22for supporting the conductive contact plugs3. In a subsequent pickling process, the protective layer5can protect the conductive contact plugs3and the surfaces of the isolation structures22for supporting the conductive contact plugs3, to prevent the isolation structures22for supporting the conductive contact plugs3from being etched by acid, and avoid the collapse of the conductive contact plugs3, thereby preventing the storage capacitor on the conductive contact plugs3from a short circuit due to collapse.

For example, in order to facilitate the process, as shown inFIG.12andFIG.13, the protective layer5can be formed on the passivation layer4and the surfaces of the isolation structures22for supporting the conductive contact plugs3by means of an atomic layer deposition process or chemical vapor deposition. The protective layer5on the tops of the conductive contact plugs3and on the surface of the first insulating layer2can be removed by means of a plasma dry etching process, and only the protective layer5located on the side walls of the conductive contact plugs3and the side walls of the isolation structures22for supporting the conductive contact plugs3is retained. This can ensure that subsequent electrical tests can be carried out smoothly, and can prevent the side walls of the isolation structures22from being etched by acid during the pickling process, which can cause the capacitor hole to collapse.

The protective layer5can be made of an insulating material, for example, the insulating material can be silicon dioxide, and the thickness thereof can range from 8 nm to 12 nm. For example, the thickness can be 8 nm, 9 nm, 10 nm, 11 nm, or 12 nm. Certainly, the protective layer5can also have other thicknesses, which are not listed there.

It should be noted that after the passivation layer4and the protective layer5are formed, an electrical performance test can be conducted on the conductive contact plugs3to test the electrical performance of the DRAM. During this process, the passivation layer4covers the outsides of the conductive contact plugs3, and can prevent the surfaces of the conductive contact plugs3from being oxidized, thereby ensuring that the conductive contact plugs3maintain good contact with the storage capacitor, such that the electrical performance of the semiconductor device can be improved.

In an embodiment of the disclosure, the manufacturing method of the disclosure can further include the following step.

At step S160, a second insulating layer is formed on a surface of a structure constituted by the passivation layer and the first insulating layer jointly. The second insulating layer fills gaps between the conductive contact plugs.

After the electrical test is finished, as shown inFIG.4, an insulating material can be deposited on the surface of the structure constituted by the passivation layer4and the first insulating layer2jointly by means of a chemical vapor deposition process to form the second insulating layer6. The second insulating layer6can fill the gaps between the conductive contact plugs3. That is, the second insulating layer6can fill the gap between two adjacent conductive contact plugs3and can be in contact with the first insulating layer2. Furthermore, the second insulating layer6can also cover the surfaces of the conductive contact plugs3. Two adjacent conductive contact plugs3can be separated by the first insulating layer2and the second insulating layer6, so as to insulate the two adjacent conductive contact plugs3. Since the passivation layer4and the protective layer5are provided on the surfaces of the conductive contact plugs3, the both form a barrier between two adjacent conductive contact plugs3, thereby reducing the thermal migration effect between the conductive contact plugs3. Even if layer separation occurs between the first insulating layer2and the second insulating layer6, the two conductive contact plugs3do not communicate with each other.

The manufacturing method according to the embodiments of the disclosure can further include forming an insulating dielectric layer8. As shown inFIG.4, the insulating dielectric layer8can be formed on the side of the second insulating layer6distal from the substrate1. The storage capacitor can be formed in the insulating dielectric layer8, and can pass through the second insulating layer6to communicate with the passivation layer4on the surfaces of the conductive contact plugs3. The passivation layer4is made of a conductive material, and thus can electrically connect the storage capacitor to the conductive contact plugs3, and then the charges collected in the storage capacitor can be stored through the conductive contact plugs3.

The insulating dielectric layer8can be formed on the side of the second insulating layer6distal from the substrate1by means of atomic layer deposition or chemical vapor deposition. The insulating dielectric layer8can be a one-layer structure or a multi-layer structure, which is not specifically limited here. In an embodiment, the insulating dielectric layer8can include a film layer, which can be boron phosphorous silicate glass.

The embodiments of the disclosure also provide a semiconductor structure. As shown inFIG.4, the semiconductor structure can include a substrate1, a first insulating layer2, a plurality of conductive contact plugs3, and a passivation layer4.

The first insulating layer2can cover the substrate1, and can include a plurality of vias21and a plurality of isolation structures22that are alternatingly distributed.

The plurality of conductive contact plugs3can respectively cover the bottoms of the vias21. The conductive contact plugs3each includes a first region31and a second region32adjacent to each other. The conductive contact plugs3located in the first regions31cover outer walls of the isolation structures22and extend along the outer walls to surfaces of the isolation structures22distal from the substrate1.

The passivation layer4can cover side walls and surfaces of the conductive contact plugs3.

According to the semiconductor structure of the disclosure, charges in a storage capacitor can be stored through the conductive contact plugs3. During this process, on the one hand, the conductive contact plugs3can be supported by the top surfaces of the isolation structures22to avoid the collapse of capacitor holes. On the other hand, the surfaces of the conductive contact plugs3can be protected by the passivation layer4to prevent the surfaces of the conductive contact plugs3from being oxidized during an electrical test, and ensure that the conductive contact plugs3maintain good contact with the storage capacitor, thereby improving the electrical performance of the semiconductor device. In addition, the passivation layer4can form a barrier between two adjacent contact plugs, which can reduce the thermal migration effect of tungsten plugs in the subsequent heat treatment process, and reduce the risk of device failure. Furthermore, since the second regions32of the conductive contact plugs3are located in the bottoms of the vias21, and two adjacent vias21are separated by an isolation structure22, such that two adjacent conductive contact plugs3are separated by the isolation structure22, thus the communication between two the adjacent conductive contact plugs3can be avoided, and the risk of a short circuit between the two adjacent conductive contact plugs3can be reduced.

Subsequently, the above-mentioned semiconductor structure can be etched by means of a plasma etching process to expose the conductive contact plugs3, so as to facilitate the contact between the conductive contact plugs3and the storage capacitor. Since no inventive point is involved, no repeated description is provided here.

The specific details and manufacturing processes of all parts of the above-mentioned semiconductor structure have been described in detail in the corresponding method for manufacturing a semiconductor structure, and therefore, no repeated description is provided here.

The embodiments of the disclosure also provide a semiconductor device, including the semiconductor structure according to any one of the foregoing embodiments and a capacitor array. The capacitor array can include a plurality of columnar capacitors arranged at intervals. The columnar capacitors are respectively formed on the conductive contact plugs3, and lower electrode layers of the columnar capacitors are in contact with the conductive contact plugs3. When in use, the plurality of columnar capacitors can be charged and discharged simultaneously, thereby increasing the capacitance.

For example, the semiconductor device can be a storage chip, for example, a DRAM, and certainly, can also be other semiconductor devices, which are not listed here. The beneficial effects of the semiconductor device can be referred to the beneficial effects of the above-mentioned semiconductor structure, which are not repeated here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed here. This application is intended to cover any variations, uses, or adaptive changes of the disclosure following the general principles thereof and including such departures from the disclosure as come within known or customary practice in the art. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the appended claims.