Patent ID: 12249920

With reference toFIG.3a, according to one embodiment of the invention, a charger, not shown in its entirety, comprises a single-phase or multiphase power-factor correction rectifying input stage, referred to as PFC and not shown, and a DC-to-DC conversion device1comprising a bidirectional full-bridge LLC resonant converter20. It should be noted that the elements of the charger are described with reference to the charging mode. Thus, the input of the DC-to-DC converter corresponds to the connections of the converter opposite the connections of the battery Batt. Likewise, the secondary of the transformer of the converter belongs to the output stage comprising the battery Batt.

The full-bridge LLC resonant converter20comprises a full switching bridge21generating a squarewave voltage or signal exciting an LLC circuit22that is composed of a capacitor and two inductors. The LLC circuit22then produces a resonant sinusoidal current that is transmitted by a transformer23and rectified by a bridge rectifier24. The rectified and amplified current/signal is collected by the battery26, the battery25also being shown as a voltage source25.

The assembly that is formed by the full switching bridge21and the LLC circuit22is referred to as the primary circuit or primary portion of the converter, and the assembly that is formed by the rectifier24is referred to as the secondary circuit or secondary portion of the converter.

In inverted mode, the impedance of the power-factor correction stage, the network or the loads that are connected at the input of the charger is lumped together as a load resistor Rload.

In bidirectional operation of the charger, when current is sent from the primary to the secondary of the converter20, this is referred to as the forward operating direction of the converter20, which allows the battery26to be recharged from an external electricity network that is connected to the primary. The charger is further configured to operate in the reverse direction, in which the power that is stored by the battery26passes from the secondary to the primary of the converter20in order to supply power to an external electricity network by operating as a current source, or to replace a network by operating as a voltage source.

The switching bridge21comprises 4 switching arms, each being formed from a parallel structure210,210′,210″,210′″, in the sense that the structure comprises electronic components that are connected in parallel with one other.

Each parallel structure210,210′,210″,210′″ comprises a diode and a transistor.

The parallel structures210,210′,210″,210′″ are connected as a full bridge, in a configuration that is well known to a person skilled in the art.

The LLC circuit22and the transformer23are in accordance with those from the prior art that was cited previously with reference toFIG.1.

The rectifier24of the secondary circuit comprises a full bridge that is formed from 4 switching arms.

Each switching arm is formed from a parallel structure240,240′,240″,240′″, in the sense that the structure comprises electronic components that are connected in parallel with one another.

Each parallel structure240,240′,240″,240′″ comprises, with reference toFIG.3a, a diode302and a transistor301, in a full-bridge rectifier circuit.

A parallel branch28connected in parallel with the LLC circuit22is added between the full switching bridge21and said LLC circuit22. This branch28is connected to the two outputs of the switching bridge21upstream of the LLC circuit22(the term “upstream” referring here to the forward charging direction).

In other words, this parallel branch28extends to a first junction between an output of the switching bridge21and the capacitor Cr of the LLC circuit, while the other junction is connected between the second output of the switching bridge21and the second inductor Lm of the two inductors Lr and Im of the LLC circuit.

The parallel branch28comprises an inductor that is referred to as the switched inductor Lm_switched that is connected to the LLC circuit22in discharging mode, and disconnected in charging mode.

Thus, the DC-to-DC converter in discharging operating mode is equivalent to an LLC circuit.

The DC-to-DC conversion device1comprises a control means (not shown), for example a microprocessor and/or an FPGA, in order to control the switch k of the parallel branch28so as to open and close.

The control method4according to the invention aims to control the frequency of the voltage Vdc of the input capacitor.

The objective of this method is to implement a regulating mode for the DC bus, which is known by the name “burst” mode, by hysteresis on the frequency and DC bus is envisaged. This burst mode consists in applying the maximum frequency in packets and in shifting the frequency between 200 kHz and 0 Hz in order to be able to regulate the DC bus at the limit points.

This implies stopping chopping at intervals in order to let the DC bus (with a voltage Vdc inFIG.3a) return to the setpoint.

Chopping then resumes in order to maintain it as far as possible. As soon as the DC bus exceeds a certain maximum threshold, which is defined by calibration, and as soon as the frequency is saturated, the control frequency is shifted to zero and chopping stops. These steps are implemented repeatedly.

Thus, with reference toFIG.2, the burst mode is explained for discharging, but operates on the same principle in charging operation, for operating points that are given as examples, here Vbat=400 V or Vbat=430 V with a setpoint of the voltage Vdc at Vdcregthat is equal to 450 V.

InFIG.2, as soon as the frequency F_nomreaches50a value that is greater than or equal to 190 kHz or, according to an alternative, any value approaching 200 kHz, and the DC bus departs51from the setpoint, the burst mode is activated52, returning the DC bus to its setpoint, substantially 450 V.

When the power goes back up, leading the frequency F_nomto no longer saturate53naturally, and the DC bus converges54once again toward the setpoint value, the burst mode is stopped55and the nominal regulation56applies the control frequency continuously.

To this end, the method according to the invention comprises calculating a chopping frequency of the DC-to-DC converter.

It is known, with reference toFIG.3b, that the transfer function of an LLC DC-to-DC converter in discharging mode according to the invention is of the form:

G=VDCη⁢Vbat=VoutVin(1)

With G being the gain of the transfer function of the DC-to-DC converter (or at the very least of the inverter portion of the DC-to-DC converter up to the primary of the transformer);η being the turns ratio of the transformer of the DC-to-DC converter;Vbatbeing the voltage across the terminals of the battery, or the voltage at the output of the DC-to-DC converter;Vdcbeing the DC voltage at the input of the DC-to-DC converter;And, in accordance with generic terminology, in discharging operating mode: Voutbeing the voltage at the output of the DC-to-DC converter in discharging mode, and Vinbeing the voltage at the input of the DC-to-DC converter in discharging mode.

With reference toFIG.3b, which is a simplified view of the DC-to-DC converter, the resistor Rloadcorresponds to the impedance of the PFC and of the various loads or networks that are connected to the charger in reversible (discharging) mode. Thus, Rloadis calculated according to the following equation:

Rload=8π2⁢VDC2p(2)

With P being the power at the primary of the transformer.

Thus, in order to calculate the gain of the transfer function of the DC-to-DC converter,

G⁡(s)=❘"\[LeftBracketingBar]"VoutVin❘"\[RightBracketingBar]"=❘"\[LeftBracketingBar]"VDCη⁢Vbat❘"\[RightBracketingBar]"=❘"\[LeftBracketingBar]"Rload⁢Lm⁢switched⁢Cr⁢s2(Lm⁢switched⁢Lr⁢Cr⁢s3+RloadLmswitched⁢s+Rload❘"\[RightBracketingBar]"(3)
is calculated.

This equation (3) is rewritten as a function of angular frequency (ω=2πfsw), setting s=jω.

The gain equation may consequently be written according to the following equations:

G⁡(s)=❘"\[LeftBracketingBar]"VoutVin❘"\[RightBracketingBar]"=❘"\[LeftBracketingBar]"VDCη⁢Vbat❘"\[RightBracketingBar]"=❘"\[LeftBracketingBar]"Rload⁢Lm-switched⁢Cr(jw)2(Lm⁢switched⁢Lr⁢Cr(jw)3+RloadLmswitched(j⁢w)+Rload❘"\[RightBracketingBar]"⁢Or⁢G⁡(s)=❘"\[LeftBracketingBar]"VoutVin❘"\[RightBracketingBar]"=❘"\[LeftBracketingBar]"VDCη⁢Vbat❘"\[RightBracketingBar]"=❘"\[LeftBracketingBar]"Rload⁢Lm⁢switched⁢Cr(j⁢2⁢π⁢fsw)2(Lm⁢switched⁢Lr⁢Cr(j⁢2⁢π⁢fsw)3+RloadloadLmswitched(j⁢2⁢π⁢fsw)+Rload)❘"\[RightBracketingBar]"

Calculating the gain G of the transfer, in order to obtain an expression for the control frequency fswaccording to the equation:

fSW(ω)=f⁢c⁢t⁡(Vbat,Preq,Vdc⁡(setpoint))(5)

With Vbatbeing the battery voltage, Vdcthe voltage at the input of the DC-to-DC converter and preqa power setpoint at the input of the DC-to-DC converter.

Specifically, by replacing Vdcin the expression for G(s) with a setpoint Vdcvalue, the frequency for which the DC bus converges with a given voltage, for example 450 V, may be calculated.

The gain G is calculated as being the ratio of Vdc/ηVbat, or in this embodiment G=450 V/ηVbat.

It will be noted that the general expression for the gain G is the same for discharging, but the gain values are different, since the parameters are themselves different.

A 3rd-order equation that is dependent on (ω=2πfsw) is deduced therefrom,

ω3+A⁢ω2+B⁢ω+C=0(6)

With the parameters A, B and C being functions of Vbatand PREQ, Lm_switchedand Lrthe inductance values of the inductors of the equivalent circuit of the DC-to-DC converter inFIG.3b, and Cr the capacitance value of the equivalent circuit of the DC-to-DC converter inFIG.3b. In other words, Cr and Lr correspond to the series capacitor and to the series inductor of the LLC circuit22ofFIG.3a.

Solving the equation (6) for ω allows the control frequency fsw(ω) for the DC-to-DC converter to be calculated by feedforward control.

Because of parameter dispersions, calculation precision levels and simplifying assumptions that are made for writing the transfer function of the DC-to-DC converter, the application of this equation is not sufficient to eliminate the steady-state error between the measured DC voltage and the setpoint. However, the error remains insignificant and has a maximum of 30 V.

In order to overcome this problem, with reference toFIG.4, a controller has been added to the previous feedforward. It operates by incrementing or decrementing the frequency until the steady-state error is eliminated, and thus adjusts the initial frequency that is generated by the previous calculation a little more, for better precision.

The controller according to the first embodiment is a discrete controller in which:eps1 is a threshold value from which the frequency incrementation/decrementation begins.eps2 is a threshold value for which the control frequency is fixed.

Thus, according to an example embodiment with reference toFIG.4, in a first step the control frequency fzw(ω), also called the switching frequency fsw(ω), is calculated40, as described previously, according to a setpoint voltage VDCreq, the battery voltage and the power.

The control frequency value fsw(k) is initialized41at the previously calculated initial frequency value fsw_feedforward.

Then, an error value & between the setpoint voltage VDCreqand the measured voltage Vdcmeasuredat the input of the DC-to-DC converter is calculated44.

This error value & is compared to two error threshold values eps1 and eps2, that are positive real numbers such that eps1>eps2.

If42the error & is between the adjustable limits of eps1 and −eps1, for example between 200 V and −200 V, and if, in addition, the error ε is greater than eps2 or less than −eps2, these thresholds being, for example, 5 V and −5 V, the initial frequency value fsw_feedforwardis incremented or decremented according to the position of the DC bus with respect to the setpoint43, by incrementing by a frequency increment step ΔF, or:

fsw(k)=fsw_feedforward+/-Δ⁢F(7)
k being a time integer.

After this step43, the method loops back to the step44.

If47after the step44the error & is between the limits of eps2 and −eps2, the value of the frequency fsw(k) is fixed and maintained 45 which ensures a DC bus at 5 V that is close to the setpoint at the previous value, or:

fS⁢W(k)=fS⁢W(k-1)

The value fsw(k−1) being equal to fsw_feedforwardif the condition1has not been verified previously, or to fsw_feedforward+k*ΔF if the step45takes place after k previous steps43.

Lastly, if48the error & is greater than eps1 or less than −eps1, the frequency value fsw(k) that is calculated by feedforward in the step40is used 46.

This value is updated periodically. The control will continue to apply the frequency that is calculated by feedforward as long as no condition on the error is satisfied, the steps43,45and46looping back to the step44.

The invention is not limited to the values of the given example error threshold values eps1 and eps2. In particular, eps2 may be adjusted to 1 or 0 V, according to the feasibility of the operating point.

This method ensures convergence at a stable frequency, which is ensured by the feedforward action and is effective by virtue of the action of the controller, which finishes eliminating the steady-state error and makes the DC bus converge with the setpoint value with precision.

The invention is not limited to the type of controller described in the first example embodiment. A controller of the proportional-integral or proportional-integral-derivative type may also be provided, which a person skilled in the art knows how to implement, although adjusting them is more complex than the controller of the first embodiment of the invention.