Patent ID: 12261180

DESCRIPTION OF THE EMBODIMENTS

Example embodiments will now be described in detail in accordance with the accompanying drawings. Throughout the drawings, the same elements or corresponding elements are labeled with common references, and the description thereof may be omitted or simplified.

First Embodiment

FIG.1is a block diagram illustrating a general configuration of a photoelectric conversion device according to the present embodiment. The photoelectric conversion device includes a pixel array10, a vertical scanning circuit16, a column amplifier circuit18, a horizontal scanning circuit20, an output circuit24, and a control circuit22. These circuits may be formed on a semiconductor substrate, such as a silicon substrate. Note that, although it is assumed that the photoelectric conversion device of the present embodiment is an imaging device configured to acquire an image, the photoelectric conversion device is not limited thereto. For example, the photoelectric conversion device may be a focus-detection device, a ranging device, a time-of-flight (TOF) camera, or the like.

The pixel array10includes a plurality of pixels100arranged so as to form a plurality of rows and a plurality of columns. Note that, as described later, the pixel100may be any of an effective pixel, a charge discharging pixel, and an optical black (OB) pixel.

The vertical scanning circuit16is a scanning circuit that supplies control signals via control signal lines14provided on respective rows of the pixels100, and the control signals are for controlling transistors included in the pixels100to be switched on (conductive state) or off (nonconductive state). The vertical scanning circuit16may be formed of logic circuits, such as a shift register, an address decoder, or the like. Herein, since the control signals supplied to each pixel100may include multiple types of control signals, the control signal lines14on each row may be formed of a set of a plurality of drive wirings. An output line12is provided on each column of the pixels100, and signals from the pixels100are read to the output line12on a column basis.

The column amplifier circuit18amplifies signals output to the output lines12. Further, the column amplifier circuit18may perform a correlated double sampling process using an N-signal based on a reset state of the pixel100and an S-signal generated by photoelectric conversion at the pixel100. The horizontal scanning circuit20supplies control signals used for controlling a switch connected to an amplifier of the column amplifier circuit18to be switched on or off. The horizontal scanning circuit20may be formed of logic circuits, such as a shift register, an address decoder, or the like. The output circuit24is formed of a buffer amplifier, a differential amplifier, or the like, and outputs a signal from the column amplifier circuit18to a signal processing unit outside the photoelectric conversion device. Note that the photoelectric conversion device may be configured to further have an AD conversion unit and thereby output a digital image signal. The control circuit22controls operation timings or the like of the vertical scanning circuit16, the column amplifier circuit18, and the horizontal scanning circuit20.

FIG.2Ais a circuit diagram of an effective pixel100aaccording to the present embodiment, andFIG.2Bis a circuit diagram of a charge discharging pixel100baccording to the present embodiment. The effective pixel100aand the charge discharging pixel100bare examples of the pixels100illustrated inFIG.1. The effective pixel100a(first pixel) is a pixel that photoelectrically converts an incident light and outputs a signal in accordance with the incident light. The charge discharging pixel100b(second pixel) is a pixel that includes a semiconductor region supplied with a power source potential and discharges noise charges to a power source wiring. In the pixel array10, the effective pixels100aand the charge discharging pixels100bare arranged.FIG.2AandFIG.2Billustrate a single effective pixel100aand a single charge discharging pixel100barranged in the pixel array10as an example. Note that, in the following description, it is assumed that signal charges are electrons. However, signal charges may be holes, and in such a case, the conductivity type of each semiconductor region will be opposite.

First, the configuration of the effective pixel100awill be described with reference toFIG.2A. The effective pixel100aincludes a photoelectric conversion unit PD, a floating diffusion FD, a transfer transistor M1, a reset transistor M2, an amplifier transistor M3, and a selection transistor M4. These transistors are each formed of a MOS transistor having a gate as a control electrode. Control signals PTX(n), PRES(n), and PSEL(n) used for controlling the transfer transistor M1, the reset transistor M2, and the selection transistor M4are input to the gates of these transistors from the vertical scanning circuit16via the control signal lines14. Note that “n” in parenthesis represents a row number of the effective pixel100ato which these signals are input.

The photoelectric conversion unit PD is a photoelectric conversion element that performs photoelectric conversion to generate charges in accordance with incident light and accumulates these charges. The photoelectric conversion unit PD may be formed of a photodiode formed inside a semiconductor substrate. The anode of the photodiode forming the photoelectric conversion unit PD is connected to a ground wiring supplied with a ground potential, and the cathode is connected to the source of the transfer transistor M1.

The drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplifier transistor M3are connected to the floating diffusion FD. When switched on, the transfer transistor M1transfers charges of the photoelectric conversion unit PD to the floating diffusion FD. Because of the capacity of the floating diffusion FD, the potential of the floating diffusion FD varies in accordance with charges transferred from the photoelectric conversion unit PD.

The drain of the reset transistor M2and the drain of the amplifier transistor M3are connected to the power source wiring having a power source potential. The source of the amplifier transistor M3is connected to the drain of the selection transistor M4. The source of the selection transistor M4is connected to the output line12at a node N1. The amplifier transistor M3forms a source follower circuit together with a constant current source (not illustrated) connected to the output line12. This source follower circuit outputs a signal based on the potential of the floating diffusion FD to the output line12via the selection transistor M4. When switched on, the reset transistor M2resets the potential of the floating diffusion FD.

The effective pixel100ahas a micro-lens and a color filter arranged on an optical path up to where incident light is guided to the photoelectric conversion unit PD. The micro-lens converges incident light into the photoelectric conversion unit PD. The color filter selectively transmits light of a predetermined color.

Next, the configuration of the charge discharging pixel100bwill be described with reference toFIG.2B. As illustrated inFIG.2B, the charge discharging pixel100bhas a circuit configuration of the effective pixel100awith the transfer transistor M1, the reset transistor M2, and the amplifier transistor M3being eliminated. The anode of a photodiode forming the photoelectric conversion unit PD is connected to the ground wiring supplied with the ground potential, and the cathode is connected to the power source wiring having the power source potential and the drain of the selection transistor M4. The source of the selection transistor M4is connected to the output line12at the node N1. Therefore, when the selection transistor M4is switched on in accordance with the control signal PSEL(n), a potential based on the power source potential is output to the output line12.

FIG.3Ais a schematic plan view of the effective pixel100aaccording to the present embodiment.FIG.3Aillustrates a plan layout of the effective pixel100ain plan view with respect to the semiconductor substrate on which the photoelectric conversion device is formed.FIG.3B,FIG.3C, andFIG.3Dare schematic sectional views of the effective pixel100aaccording to the present embodiment.FIG.3B,FIG.3C, andFIG.3Dschematically illustrate sectional views taken along line A-A′, line B-B′, and line C-C′ inFIG.3A, respectively. The structure of the effective pixel100awill be described with reference to these drawings with each other.

The effective pixel100ahas semiconductor regions101,102,103,104,105, and121and an element isolation region106that are arranged in a semiconductor substrate120. Further, the effective pixel100ahas gates107,108,109, and110, contacts111,112,113,114,115,116, and117, a wiring118, and an insulating layer122that are arranged on or above the semiconductor substrate120. These contacts are each formed of a conductive member arranged so as to pass through a hole penetrating the insulating layer122.

The semiconductor region101(first semiconductor region) is an n-type (first conductivity type) semiconductor region. The semiconductor region121arranged on the front face side of the semiconductor substrate120from the semiconductor region101is a p-type semiconductor region. The semiconductor region101and the semiconductor region121form a p-n junction, which forms an embedded photodiode corresponding to the photoelectric conversion unit PD inFIG.2A. The semiconductor region101functions as a charge accumulation layer. Further, the semiconductor region121functions as a surface protection layer of the embedded photodiode. Employing such an embedded photodiode may reduce noise that may occur at an interface of the substrate surface or the like. Note that, inFIG.3A, depiction of the semiconductor region121is omitted.

The gates107,108,109, and110correspond to the gates of the transfer transistor M1, the reset transistor M2, the amplifier transistor M3, and the selection transistor M4, respectively. The contacts111,113, and116are connected to the gates107,108, and110, respectively, and control signals are input thereto via these contacts. The semiconductor region102is an n-type semiconductor region forming the floating diffusion FD. The semiconductor region102further forms the drain of the transfer transistor M1and the source of the reset transistor M2. The contact112is connected to the semiconductor region102, and the contact115is connected to the gate109. The contact112and the contact115are connected to each other via the wiring118arranged in a wiring layer layered on the insulating layer122.

The semiconductor region103is an n-type semiconductor region forming the drain of the reset transistor M2and the drain of the amplifier transistor M3. The contact114is connected to the semiconductor region103, and the contact114is connected to the power source wiring provided in a layer on the insulating layer122.

The semiconductor region104is an n-type semiconductor region forming the source of the amplifier transistor M3and the drain of the selection transistor M4. The semiconductor region105is an n-type semiconductor region forming the source of the selection transistor M4. The contact117is connected to the semiconductor region105and connected to the output line12. That is, the contact117corresponds to the node N1inFIG.2A.

Note that the semiconductor regions102,103,104, and105each are an n-type semiconductor region having a higher impurity concentration than the semiconductor region101. This can reduce the resistance. The element isolation region106may be Shallow Trench Isolation (STI), Local Oxidation of Silicon (LOCOS), or the like.

FIG.4Ais a schematic plan view of the charge discharging pixel100baccording to the present embodiment.FIG.4Aillustrates a plan layout of the charge discharging pixel100bin plan view with respect to the semiconductor substrate on which the photoelectric conversion device is formed.FIG.4B,FIG.4C, andFIG.4Dare schematic sectional views of the charge discharging pixel100baccording to the present embodiment.FIG.4B,FIG.4C, andFIG.4Dschematically illustrate sectional views taken along line D-D′, line E-E′, and line F-F′ inFIG.4A, respectively. The structure of the charge discharging pixel100bwill be described with reference to these drawings with each other. Note that description for features common to the effective pixel100amay be omitted.

The charge discharging pixel100bhas semiconductor regions131,132,133, and105and the element isolation region106that are arranged in the semiconductor substrate120. Further, the charge discharging pixel100bhas the gate110, the contacts114,116, and117, and the insulating layer122that are arranged on or above the semiconductor substrate120. These contacts are each formed of a conductive member arranged so as to pass through a hole penetrating the insulating layer122. As described with reference toFIG.2B, no transfer transistor M1, no reset transistor M2, or no amplifier transistor M3is arranged in the charge discharging pixel100b, and nor is the gate corresponding thereto arranged.

The semiconductor region131(second semiconductor region) is an n-type semiconductor region. The semiconductor region133arranged on the front face side of the semiconductor substrate120from the semiconductor region131is a p-type semiconductor region. Note that, inFIG.4A, depiction of the semiconductor region133is omitted. The semiconductor region132(third semiconductor region) is an n-type semiconductor region and is connected to the semiconductor region131. Note that the dashed line between the semiconductor region131and the semiconductor region132illustrated inFIG.4Arepresents the end of the semiconductor region131.

The gate110corresponds to the gate of the selection transistor M4. The contact116is connected to the gate110, and a control signal is input thereto via the contact116. The semiconductor region132extends from the gate of the selection transistor M4to the semiconductor region131and forms the drain (first main electrode) of the selection transistor M4. Further, the contact114(second contact) is connected to the semiconductor region132and connected to the power source wiring provided in a layer above the insulating layer122.

The semiconductor region105(fourth semiconductor region) is an n-type semiconductor region forming the source (second main electrode) of the selection transistor M4. The contact117(first contact) is connected to the semiconductor region105and connected to the output line12. That is, the contact117corresponds to the node N1inFIG.2B.

Note that the semiconductor region132is an n-type semiconductor region having a higher impurity concentration than the semiconductor region131. Accordingly, the contact114supplied with the power source potential and the semiconductor region132can be connected to each other at a low resistance, and this may improve the charge discharging effect. Further, the semiconductor region105is also an n-type semiconductor region having a higher impurity concentration than the semiconductor region101. This can reduce the resistance.

Unlike the effective pixel100a, the semiconductor region133is arranged only near the element isolation region106in the charge discharging pixel100b. This reduces the influence of junction leak that may occur when there is a p-n junction between the high-concentration n-type semiconductor region132and the high-concentration p-type semiconductor region133. Note that the p-type semiconductor region133may not be arranged in the charge discharging pixel100b, and in such a case, the same effect is obtained.

As described above, the photoelectric conversion device of the present embodiment has the charge discharging pixel100bhaving a circuit configuration of the effective pixel100awith the transfer transistor M1, the reset transistor M2, and the amplifier transistor M3being eliminated. The charge discharging pixel100bcan discharge noise charges, which are present nearby, from the semiconductor region131to the power source wiring via the semiconductor region132and the contact114. Thus, according to the present embodiment, a photoelectric conversion device that can more suitably discharge noise charges can be provided.

Note that, although the example in which the contact114of the charge discharging pixel100bis arranged at the same position as that of the effective pixel100ais illustrated inFIG.4A,FIG.4C, andFIG.4D, the embodiment is not limited thereto. For example, a contact connected to the power source wiring may be directly connected to the semiconductor region131. Further, a plurality of contacts connected to the power source wiring may be arranged.

Further, the selection transistor M4is arranged in the charge discharging pixel100bof the present embodiment in the same manner as the effective pixel100a. This enables the charge discharging pixel100bto output a signal whose level corresponds to the power source potential in response to the control signal PSEL(n). The signal whose level corresponds to the power source potential may be used for correction of a signal, for example.

It is desirable that the semiconductor region101of the effective pixel100aand the semiconductor region131of the charge discharging pixel100bhave the same shape in plan view. Such the same shape reduces characteristic variation between pixels that would otherwise be caused when the manufacturing process is uneven due to a difference in the layout of nearby elements between a case where another effective pixel100ais arranged near one effective pixel100aand a case where the charge discharging pixel100bis arranged near the one effective pixel100a.

Second Embodiment

In the present embodiment, an example of the layout when OB pixels are arranged inside the pixel array10will be described. Since the configuration of a circuit block of a photoelectric conversion device, the structure of the effective pixel100aand the charge discharging pixel100b, and the like are the same as those of the first embodiment, the description thereof will be omitted.

FIG.5is a schematic diagram illustrating a layout of the photoelectric conversion device according to the present embodiment. As illustrated inFIG.5, the pixel array10, the vertical scanning circuit16, the column amplifier circuit18, the horizontal scanning circuit20, and the control circuit22are arranged on a semiconductor substrate. The vertical scanning circuit16, the column amplifier circuit18, the horizontal scanning circuit20, and the control circuit22represent an example of a peripheral circuit arranged around the pixel array10, and the arrangement of these circuits are not limited to what is illustrated. Further, a circuit other than these circuits may be arranged around the pixel array10.

The pixel array10has an effective pixel region RE a charge discharging pixel region R2, and an OB pixel region R3. The effective pixel region R1(first pixel region) is a region in which the effective pixels100adescribed in the first embodiment are arranged to form a plurality of rows and a plurality of columns.

The OB pixel region R3(third pixel region) is a region in which OB pixels are arranged so as to form a plurality of rows and a plurality of columns. The OB pixel has the same circuit configuration as the effective pixel100adescribed in the first embodiment and is a pixel in which the photoelectric conversion unit PD is covered with a light shielding film, such as a metal thin film. Accordingly, since light does not enter the photoelectric conversion unit PD of the OB pixel, the OB pixel can output a black level signal. This black level signal may be used for correction of a signal, for example. The OB pixel region R3is arranged on the outer circumference of the effective pixel region R1. For example, the OB pixel region R3may be arranged so as to be along two sides of the effective pixel region R1as illustrated inFIG.5or may be arranged so as to be along three or four sides of the effective pixel region R1.

The charge discharging pixel region R2(second pixel region) is a region in which the charge discharging pixels100bdescribed in the first embodiment are arranged so as to form a plurality of rows and a plurality of columns. The charge discharging pixel region R2is arranged in the outer circumference of the effective pixel region R1and the OB pixel region R3so as to surround these regions.

In the present embodiment, the charge discharging pixel region R2is arranged in the outer circumference of the OB pixel region R3. The charge discharging pixels100binside the charge discharging pixel region R2discharge noise charges, and thereby, in particular, inflow of noise charges to the OB pixels from the outer circumferential side of the OB pixel region R3is reduced. Accordingly, in the present embodiment, in addition to the advantageous effect described in the first embodiment, it is possible to more accurately achieve generation of a black level signal from the OB pixel.

Third Embodiment

In the present embodiment, a modified example of the circuit configuration and the structure of the charge discharging pixel100bin the first embodiment will be described. Since the configuration of a circuit block of a photoelectric conversion device, the structure of the effective pixel100a, and the like are the same as those of the first embodiment, the description thereof will be omitted.

FIG.6is a circuit diagram of a charge discharging pixel100caccording to the present embodiment. The charge discharging pixel100c(second pixel) is the same as the charge discharging pixel100bof the first embodiment in that both the pixels are to discharge noise charges from a semiconductor region supplied with the power source potential but differs from the charge discharging pixel100bin the circuit configuration and the structure.

As illustrated inFIG.6, the charge discharging pixel100chas a circuit configuration of the effective pixel100awith the transfer transistor M1and the reset transistor M2being eliminated. In other words, the charge discharging pixel100chas a circuit configuration of the charge discharging pixel100bwith the amplifier transistor M3being added.

The anode of the photodiode forming the photoelectric conversion unit PD is connected to the ground wiring supplied with the ground potential. The cathode of the photodiode, the gate of the amplifier transistor M3, and the drain of the amplifier transistor M3are connected to the power source wiring having the power source potential. The source of the amplifier transistor M3is connected to the drain of the selection transistor M4. The source of the selection transistor M4is connected to the output line12at the node N1. The amplifier transistor M3forms a source follower circuit together with a constant current source (not illustrated) connected to the output line12. Therefore, when the selection transistor M4is switched on in response to the control signal PSEL(n), the potential based on the power source potential is output to the output line12.

FIG.7Ais a schematic plan view of the charge discharging pixel100caccording to the present embodiment.FIG.7Aillustrates a plan layout of the charge discharging pixel100cin plan view with respect to the semiconductor substrate on which the photoelectric conversion device is formed.FIG.7B,FIG.7C, andFIG.7Dare schematic sectional views of the charge discharging pixel100caccording to the present embodiment.FIG.7B,FIG.7C, andFIG.7Dschematically illustrate sectional views taken along line G-G′, line H-H′, and line I-I′ inFIG.7A, respectively. The structure of the charge discharging pixel100cwill be described with reference to these drawings with each other. Note that description for features common to the effective pixel100aor the charge discharging pixel100bmay be omitted.

The charge discharging pixel100chas the semiconductor regions131,133,142,104, and105and the element isolation region106that are arranged in the semiconductor substrate120. Further, the charge discharging pixel100chas the gates109and110, the contacts112,143,115,116, and117, and the insulating layer122that are arranged on or above the semiconductor substrate120. These contacts are each formed of a conductive member arranged so as to pass through a hole penetrating the insulating layer122. As described with reference toFIG.6, neither the transfer transistor M1nor the reset transistor M2is arranged in the charge discharging pixel100c, and nor is the gate corresponding thereto arranged.

The semiconductor region131(second semiconductor region) is an n-type semiconductor region. The semiconductor region133arranged on the front face side of the semiconductor substrate120from the semiconductor region131is a p-type semiconductor region. Note that, inFIG.7A, depiction of the semiconductor region133is omitted. The semiconductor region142(third semiconductor region) is an n-type semiconductor region and is connected to the semiconductor region131. Note that the dashed line between the semiconductor region131and the semiconductor region142illustrated inFIG.7Arepresents the end of the semiconductor region131.

The gates109and110correspond to the gates of the amplifier transistor M3and the selection transistor M4, respectively. The contact116is connected to the gate110, and a control signal is input via the contact116. The semiconductor region142extends to the semiconductor region131from the gate109of the amplifier transistor M3and forms the drain (first main electrode) of the amplifier transistor M3. Further, the contacts112and143(first conductive member passing through the first hole) are connected to the semiconductor region142, the contact115(second conductive member passing through the second hole) is connected to the gate109. The contact112, the contact143, and the contact115are connected to each other via a wiring118arranged in the wiring layer layered on the insulating layer122. The power source potential is provided to the wiring118(power source wiring).

The semiconductor region104is an n-type semiconductor region forming the source of the amplifier transistor M3and the drain of the selection transistor M4. The semiconductor region105is an n-type semiconductor region forming the source of the selection transistor M4. The contact117is connected to the semiconductor region105and connected to the output line12. That is, the contact117corresponds to the node N1inFIG.6.

Note that the semiconductor region142is an n-type semiconductor region having a higher impurity concentration than the semiconductor region132. Accordingly, the contact112or the contact143provided with the power source potential and the semiconductor region142can be connected to each other at a low resistance, and this may improve the charge discharging effect. Further, the semiconductor regions104and105are also n-type semiconductor regions having a higher impurity concentration than the semiconductor region101. This can reduce the resistance.

As described above, the photoelectric conversion device of the present embodiment has the charge discharging pixel100chaving a circuit configuration of the effective pixel100awith the transfer transistor M1and the reset transistor M2being eliminated. The charge discharging pixel100ccan discharge noise charges, which are present nearby, from the semiconductor region131to the wiring118via the semiconductor region142and the contacts112and143in the same manner as in the first embodiment. Thus, according to the present embodiment, a photoelectric conversion device that can more preferably discharge noise charges can be provided.

In the charge discharging pixel100cof the present embodiment, the amplifier transistor M3and the selection transistor M4are arranged in the same manner as in the effective pixel100a. Accordingly, in response to the control signal PSEL(n), the charge discharging pixel100ccan output substantially the same potential as the N-signal having a level based on a reset state of a pixel. This output signal may be used in correction of a signal, for example. In the present embodiment, because the N-signal output by the effective pixel100aand a signal output by the charge discharging pixel100care at substantially the same level, this reduces influence of potential variation or the like between a case where the effective pixel100ais connected to an output line12and a case where the charge discharging pixel100cis connected to the same output line12.

Note that it is desirable that the semiconductor region101of the effective pixel100aand the semiconductor region131of the charge discharging pixel100chave the same shape in plan view also in the present embodiment for the same reason as described in the first embodiment. Further, the charge discharging pixel100cof the present embodiment may be arranged in the charge discharging pixel region R2of the second embodiment, and the same advantageous effect as described in the second embodiment is obtained.

Fourth Embodiment

In the present embodiment, a modified example of a layout of the pixel array10in the second embodiment will be described. Since other features are the same as those of the second embodiment, the description thereof will be omitted.

FIG.8is a schematic diagram illustrating a layout of the photoelectric conversion device according to the present embodiment. InFIG.8, a difference from the pixel array10illustrated inFIG.5of the second embodiment is the arrangement of the effective pixel region R1, the charge discharging pixel region R2, and the OB pixel region R3. As illustrated inFIG.8, in the present embodiment, the charge discharging pixel region R2(second pixel region) is also arranged between the effective pixel region R1(first pixel region) and the OB pixel region R3(third pixel region). Accordingly, in the present embodiment, in addition to the advantageous effect of the second embodiment, noise charges flowing in the OB pixel from the effective pixel region R1are also reduced. Accordingly, in the present embodiment, it is possible to more accurately achieve generation of a black level signal from the OB pixel than in the second embodiment.

Note that, in the present embodiment, the charge discharging pixel100bof the first embodiment may be arranged in the charge discharging pixel region R2, or the charge discharging pixel100cof the third embodiment may be arranged in the charge discharging pixel region R2.

Fifth Embodiment

In the present embodiment, a modified example of the circuit configuration and the structure of the effective pixel100aand the charge discharging pixels100band100cin the first embodiment and the third embodiment will be described. Since the configuration of a circuit block of a photoelectric conversion device and the like are the same as those of the first embodiment, the description thereof will be omitted.

FIG.9Ais a circuit diagram of an effective pixel100daccording to the present embodiment, andFIG.9Bis a circuit diagram of a charge discharging pixel100eaccording to the present embodiment. First, in the configuration of the effective pixel100d, features different from the effective pixel100aof the first embodiment will be described with reference toFIG.9A.

The effective pixel100d(first pixel) of the present embodiment differs from the effective pixel100aof the first embodiment in that two photoelectric conversion units PDa and PDb and two transfer transistors M1aand M1bare arranged in a single effective pixel100d. The anodes of the photoelectric conversion units PDa and PDb are connected to the ground wiring supplied with the ground potential. The cathode of the photoelectric conversion unit PDa is connected to the source of the transfer transistor M1a, and the cathode of the photoelectric conversion unit PDb is connected to the source of the transfer transistor M1b. The control signals PTXa(n) and PTXb(n) are input to the gates of the transfer transistors M1aand M1bvia the control signal lines14from the vertical scanning circuit16, respectively. The drain of the transfer transistor M1a, the drain of the transfer transistor M1b, the source of the reset transistor M2, and the gate of the amplifier transistor M3are connected to the floating diffusion FD.

The effective pixel100dhas a micro-lens and a color filter arranged on the optical path up to where incident light is guided to the photoelectric conversion unit PD. The micro-lens converges incident light into the photoelectric conversion units PDa and PDb. The color filter selectively transmits light of a predetermined color. In the present embodiment, the two PDa and PDb have a configuration to share a single micro-lens. Accordingly, since light passing through pupil regions of the same micro-lens, which are different from each other, enters the two PDa and PDb, signals generated by the photoelectric conversion units PDa and PDb, respectively, may be used as ranging signals.

Next, in the configuration of the charge discharging pixel100e, features different from the charge discharging pixel100cof the third embodiment will be described with reference toFIG.9B. As illustrated inFIG.9B, the charge discharging pixel100e(second pixel) has a circuit configuration of the effective pixel100dwith the transfer transistors M1aand M1band the reset transistor M2being eliminated. The anodes of the two photodiodes forming the photoelectric conversion units PDa and PDb are connected to the ground wiring supplied with the ground potential. The cathodes of the two photodiodes, the gate of the amplifier transistor M3, and the drain of the amplifier transistor M3are connected to the power source wiring having the power source potential.

FIG.10Ais a schematic plan view of the effective pixel100daccording to the present embodiment and illustrates a plan layout of the effective pixel100din plan view with respect to the semiconductor substrate on which the photoelectric conversion device is formed.FIG.10Bis a schematic plan view of the charge discharging pixel100eaccording to the present embodiment and illustrates a plan layout of the charge discharging pixel100ein plan view with respect to the semiconductor substrate on which the photoelectric conversion device is formed. First, the structure of the effective pixel100dwill be described with reference toFIG.10A. Note that description of features common to the effective pixel100amay be omitted.

The effective pixel100dhas semiconductor regions201a,201b,202,203a,203b,204a,204b, and205and an element isolation region206that are arranged in the semiconductor substrate. Further, the effective pixel100dhas gates207a,207b,208,209, and210, contacts211a,211b,212,213,214a,214b,215,216,217,250a, and250b, and a wiring218that are arranged on or above the semiconductor substrate. These contacts are each formed of a conductive member arranged so as to pass through a hole penetrating the insulating layer.

The semiconductor regions201aand201b(first semiconductor region) are n-type semiconductor regions. In the same manner as in the first embodiment, a p-type semiconductor region (not illustrated) may be arranged on the front face side of the semiconductor substrate from the semiconductor regions201aand201b, and the photodiode of the present embodiment may also be an embedded photodiode.

The gates207a,207b,208,209, and210correspond to the gates of the transfer transistor M1a, the transfer transistor M1b, the reset transistor M2, the amplifier transistor M3, and the selection transistor M4, respectively. The contacts211a,211b,213, and216are connected to the gates207a,207b,208, and210, respectively, and control signals are input via these contacts. The semiconductor region202is an n-type semiconductor region forming the floating diffusion FD. Further, the semiconductor region202further forms the drains of the transfer transistor M1aand M1band the source of the reset transistor M2. The contact212is connected to the semiconductor region202, and the contact215is connected to the gate209. The contact212and the contact215are connected to each other via a wiring arranged in the wiring layer layered on the insulating layer.

The semiconductor region203ais an n-type semiconductor region forming the drain of the reset transistor M2, and the semiconductor region203bis an n-type semiconductor region forming the drain of the amplifier transistor M3. The contact214ais connected to the semiconductor region203a, and the contact214bis connected to the semiconductor region203b. The contact214aand the contact214bare connected to the wiring218that is the power source wiring provided in a layer on the insulating layer.

The semiconductor region204ais an n-type semiconductor region forming the source of the amplifier transistor M3, and the semiconductor region204bis an n-type semiconductor region forming the drain of the selection transistor M4. The contact250ais connected to the semiconductor region204a, and the contact250bis connected to the semiconductor region204b. The contact250aand the contact250bare connected to each other by a wiring provided in a layer on the insulating layer.

The semiconductor region205is an n-type semiconductor region forming the source of the selection transistor M4. The contact217is connected to the semiconductor region205, and the contact217is connected to the output line12. That is, the contact217corresponds to the node N1inFIG.9A.

Note that the semiconductor regions202,203a,203b,204a,204b, and205are n-type semiconductor regions having a higher impurity concentration than the semiconductor regions201aand201b. This can reduce the resistance. The element isolation region106may be STI, LOCOS, or the like.

Next, the structure of the charge discharging pixel100ewill be described with reference toFIG.10B. Note that description of features common to the charge discharging pixel100cor the effective pixel100dmay be omitted.

The charge discharging pixel100ehas the semiconductor regions201a,201b,202,203b,204a,204b, and205and the element isolation region206arranged in a semiconductor substrate. Further, the charge discharging pixel100ehas the gates209and210and the contacts214a,214b,215,216,217,250a, and250barranged on or above the semiconductor substrate. These contacts are each formed of a conductive member arranged so as to pass through a hole penetrating the insulating layer. As illustrated with reference toFIG.9B, no transfer transistor M1aor M1bor no reset transistor M2is arranged in the charge discharging pixel100e, and nor is the gate corresponding thereto arranged.

The semiconductor regions201aand201b(second semiconductor region) are n-type semiconductor regions. The semiconductor region202is an n-type semiconductor region and is connected to the semiconductor regions201aand201b. The contact214ais connected to the semiconductor region202. The contact215(the second conductive member passing through the second hole) is connected to the gate209corresponding to the gate of the amplifier transistor M3. The semiconductor region203b(third semiconductor region) is an n-type semiconductor region forming the drain (first main electrode) of the amplifier transistor M3. The contact214b(the first conductive member passing through the first hole) is connected to the semiconductor region203b. The contact214a, the contact214b, and the contact215are connected to each other via the wiring218arranged in the wiring layer layered on the insulating layer. The power source potential is provided to the wiring218(power source wiring). Since the features other than the above are the same as those of the effective pixel100d, the description thereof will be omitted.

Note that the semiconductor region202is an n-type semiconductor region having a higher impurity concentration than the semiconductor regions201aand201b. Accordingly, the contact214aprovided with the power source potential and the semiconductor regions201aand201bcan be connected to each other at a low resistance, and this may improve the charge discharging effect. Further, the semiconductor regions203b,204a,204b, and205are also n-type semiconductor regions having a higher impurity concentration than the semiconductor region201aand201b. This can reduce the resistance.

As described above, the photoelectric conversion device of the present embodiment has the charge discharging pixel100ehaving a circuit configuration of the effective pixel100dwith the transfer transistors M1aand M1band the reset transistor M2being eliminated. The charge discharging pixel100ecan discharge noise charges present nearby to the wiring118in the same manner as in the first embodiment or the third embodiment. Thus, according to the present embodiment, a photoelectric conversion device that can more preferably discharge noise charges can be provided.

In the charge discharging pixel100eof the present embodiment, the amplifier transistor M3and the selection transistor M4are arranged in the same manner as in the effective pixel100d. Accordingly, influence of potential variation or the like between a case where the effective pixel100dis connected to an output line12and a case where the charge discharging pixel100eis connected to the same output line12is reduced for the same reason as described in the third embodiment.

Note that it is desirable that the semiconductor region201aof the effective pixel100dand the semiconductor region201aof the charge discharging pixel100ehave the same shape in plan view also in the present embodiment for the same reason as described in the first embodiment. Further, it is also desirable that the semiconductor region201bof the effective pixel100dand the semiconductor region201bof the charge discharging pixel100ehave the same shape in plan view. The charge discharging pixel100eof the present embodiment may be arranged in the charge discharging pixel region R2of the second embodiment or the fourth embodiment, and the same advantageous effect as described in the second embodiment or the fourth embodiment is obtained.

Sixth Embodiment

In the present embodiment, three types of modified examples of the circuit configuration and the structure of the effective pixel100ain the first embodiment will be described. Since the configuration of the circuit block of the photoelectric conversion device, the structure of the charge discharging pixel100b, and the like are the same as those of the first embodiment, the description thereof will be omitted.

FIG.11is a circuit diagram of the effective pixel100faccording to the present embodiment. In the configuration of the effective pixel100f, features different from the effective pixel100aof the first embodiment will be described with reference toFIG.11.

The effective pixel100fof the present embodiment differs from the effective pixel100aof the first embodiment in that a first capacitance addition transistor M5(first transistor) is further arranged. The source of the first capacitance addition transistor M5is connected to the floating diffusion FD. The drain of the first capacitance addition transistor M5is connected to the source of the reset transistor M2. A control signal PFDINC1(n) is input to the gate of the first capacitance addition transistor M5from the vertical scanning circuit16via the control signal line14. Note that the reference “n1” inFIG.11represents the first node corresponding to the node of the floating diffusion FD. The reference “n2” represents the second node corresponding to a connecting point of the drain of the first capacitance addition transistor M5and the source of the reset transistor M2.

The first capacitance addition transistor M5has a function of adding a capacitance to the capacitance of the floating diffusion FD. When the control signal PFDINC1(n) is at a high level, the first capacitance addition transistor M5is switched on. When the first capacitance addition transistor M5is switched on, a channel is formed in the first capacitance addition transistor M5, and the capacitance (MOS capacitance) due to this channel is added to the capacitance of the floating diffusion FD. Further, the capacitance parasitic on another electrode (drain) of the first capacitance addition transistor M5is also added to the capacitance of the floating diffusion FD. An example of such a parasitic capacitance may be a capacitance between the gate electrode and another electrode (drain), a p-n junction capacitance of a semiconductor region forming another electrode, a capacitance with respect to a surrounding wiring, or the like. In such a way, the capacitance of the first capacitance addition transistor M5is added to the floating diffusion FD resulting in an increased overall capacitance, thereby charges that can be held are increased, and the dynamic range is expanded. Further, when the control signal PFDINC1(n) is at a low level and the first capacitance addition transistor M5is thus in an off-state, the capacitance of the first capacitance addition transistor M5is not added to the floating diffusion FD. In such a case, the sensitivity of the effective pixel100f(for example, an amount of voltage change per a single charge (charge-voltage conversion efficiency)) can be increased. In such a way, the effective pixel100fof the present embodiment can change the sensitivity by control of the first capacitance addition transistor M5.

Note that the first capacitance addition transistor M5may be arranged in parallel to the reset transistor M2. In such a case, since the capacitance parasitic on the floating diffusion FD increases when the first capacitance addition transistor M5is in the off-state, the charge-voltage conversion efficiency when no capacitance is added decreases. It is therefore desirable that the first capacitance addition transistor M5and the reset transistor M2be connected in series to the floating diffusion FD.

Next, another modified example of the circuit configuration and the structure of the effective pixel100ain the first embodiment will be described.FIG.12is a circuit diagram of the effective pixels100gand100haccording to the present embodiment. In the configuration of the effective pixels100gand100h, features different from the effective pixel100aof the first embodiment will be described with reference toFIG.12.

The effective pixels100gand100hof the present embodiment differ from the effective pixel100aof the first embodiment in that the first capacitance addition transistor M5and a second capacitance addition transistor M6(second transistor) are further arranged. The source of the first capacitance addition transistor M5is connected to the floating diffusion FD. The drain of the first capacitance addition transistor M5is connected to the source of the second capacitance addition transistor M6. The drain of the second capacitance addition transistor M6is connected to the source of the reset transistor M2. The control signal PFDINC1(n) is input to the gate of the first capacitance addition transistor M5from the vertical scanning circuit16via the control signal line14. A control signal PFDINC2(n) is input to the gate of the second capacitance addition transistor M6from the vertical scanning circuit16via the control signal line14. Note that the reference “n1” inFIG.11represents the first node corresponding to the node of the floating diffusion FD. The reference “n2” represents the second node corresponding to the connecting point of the drain of the first capacitance addition transistor M5and the source of the second capacitance addition transistor M6. The reference “n3” represents the third node corresponding to the connecting point of the drain of the second capacitance addition transistor M6and the source of the reset transistor M2.

When the control signal PFDINC1(n) is at the high level and the control signal PFDINC2(n) is at the low level, the first capacitance addition transistor M5is in an on-state, and the second capacitance addition transistor M6is in an off-state. Accordingly, the capacitance of the first capacitance addition transistor M5is added to the floating diffusion FD. When the control signal PFDINC1(n) and the control signal PFDINC2(n) are at the high level, the first capacitance addition transistor M5and the second capacitance addition transistor M6are in the on-state. Accordingly, the capacitances of the first capacitance addition transistor M5and the second capacitance addition transistor M6are added to the floating diffusion FD. When the control signal PFDINC1(n) and the control signal PFDINC2(n) are at the high low level, the first capacitance addition transistor M5and the second capacitance addition transistor M6are in the off-state. At this time, neither the capacitance of the first capacitance addition transistor M5nor the second capacitance addition transistor M6is added to the floating diffusion FD. In such a way, the effective pixel100gof the present modified example can change the sensitivity in three levels by controlling the first capacitance addition transistor M5and the second capacitance addition transistor M6to change the capacitance in three levels.

Note that, since the difference between the effective pixel100gand the effective pixel100his in a level relationship of the capacitances of the first capacitance addition transistor M5and the second capacitance addition transistor M6, the circuit diagrams of the effective pixel100gand the effective pixel100hare common to each other as illustrated inFIG.12.

FIG.13Ais a schematic plan view of the effective pixel100faccording to the present embodiment.FIG.13Bis a schematic plan view of the effective pixel100gaccording to the present embodiment.FIG.13Cis a schematic plan view of the effective pixel100haccording to the present embodiment. The configuration of the first capacitance addition transistor M5and the second capacitance addition transistor M6will be mainly described with reference to these schematic plan views. Since elements other than the first capacitance addition transistor M5and the second capacitance addition transistor M6are generally the same as those described in the first embodiment, the description thereof will be omitted or simplified.

The effective pixel100ghas the semiconductor region101arranged in the semiconductor substrate120. Further, the effective pixel100ghas the gates107,108,109,110, and160and the contacts112and114arranged on or above the semiconductor substrate120. Further, the effective pixel100gand the effective pixel100hhave a gate161in addition to the configuration of the effective pixel100g. The gates107,108,109, and110correspond to the gates of the transfer transistor M1, the reset transistor M2, the amplifier transistor M3, and the selection transistor M4, respectively. Further, the gates160and161correspond to the gates of the first capacitance addition transistor M5and the second capacitance addition transistor M6, respectively. The contact112is connected to the semiconductor region forming the floating diffusion FD. The contact114is connected to the power source wiring.

The difference between the effective pixel100gand the effective pixel100his in a level relationship of the capacitances of the first capacitance addition transistor M5and the second capacitance addition transistor M6. In the effective pixel100g, the capacitance of the first capacitance addition transistor M5is larger than the capacitance of the second capacitance addition transistor M6. In contrast, in the effective pixel100h, the capacitance of the second capacitance addition transistor M6is larger than the capacitance of the first capacitance addition transistor M5. Herein, the capacitances of the first capacitance addition transistor M5and the second capacitance addition transistor M6may be proportional to their gate lengths. As illustrated inFIG.13B, in the effective pixel100g, the gate length of the first capacitance addition transistor M5(gate160) is larger than the gate length of the second capacitance addition transistor M6(gate161). In contrast, as illustrated inFIG.13C, in the effective pixel100h, the gate length of the second capacitance addition transistor M6(gate161) is larger than the gate length of the first capacitance addition transistor M5(gate160). InFIG.13BandFIG.13C, the gate widths of the first capacitance addition transistor M5and the second capacitance addition transistor M6are the same but may be different from each other.

FIG.14is a table listing capacitances of respective portions of the effective pixels100f,100g, and100haccording to the sixth embodiment.FIG.14lists capacitances of the floating diffusion FD, the first capacitance addition transistor M5, and the second capacitance addition transistor M6in the effective pixels100f,100g, and100h. Note that the value of capacitances listed inFIG.14is represented in arbitrary unit and normalized so that the total value resulted when all the capacitances of respective portions are summed is 1. In the example ofFIG.14, in the effective pixel100f, the capacitance of the floating diffusion FD is 0.25, and the capacitance of the first capacitance addition transistor M5is 0.75. In the effective pixel100g, the capacitance of the floating diffusion FD is 0.25, the capacitance of the first capacitance addition transistor M5is 0.50, and the capacitance of the second capacitance addition transistor M6is 0.25. In the effective pixel100h, the capacitance of the floating diffusion FD is 0.25, the capacitance of the first capacitance addition transistor M5is 0.25, and the capacitance of the second capacitance addition transistor M6is 0.50. In such a way,FIG.14illustrates the example of the effective pixel100gin which the capacitance of the first capacitance addition transistor M5is larger than the capacitance of the second capacitance addition transistor M6and the example of the effective pixel100hin which the capacitance of the second capacitance addition transistor M6is larger than the capacitance of the first capacitance addition transistor M5.

In the effective pixel100g, the total capacitance may vary in three ways, 0.25, 0.75, and 1 in accordance with the control signals PFDINC1(n) and PFDINC2(n). Further, in the effective pixel100h, the total capacitance may vary in three ways, 0.25, 0.50, and 1, in accordance with the control signals PFDINC1(n) and PFDINC2(n). For example, it is assumed that such switching of the capacitance is used for application in which the gain of the photoelectric conversion device (the gain outside the pixels, such as the column amplifier circuit18) is set in three ways, fourfold, twofold, and onefold, and these three ways of capacitances are used to change the sensitivity of the pixel, respectively. In such application, it is possible to output a signal at an appropriate level while avoiding signal saturation. Herein, noise included in the output signal is proportional to both the gain and the capacitance, that is, proportional to the product of the gain and the capacitance. When the configuration as with the effective pixel100hin which the capacitance of the second capacitance addition transistor M6is larger than the capacitance of the first capacitance addition transistor M5is used, the relationship between the gain and the total capacitance is closer to inverse proportional. Accordingly, since it is possible to make the product of the gain and the total capacitance closer to constant, this can achieve even noise in various gains to improve the S/N ratio. However, this is an example, and the suitable level relationship and ratio between the first capacitance addition transistor M5and the second capacitance addition transistor M6may vary in accordance with design.

According to the present embodiment, a photoelectric conversion device that can change charge-voltage conversion efficiency can be provided. Further, according to the modified example of the effective pixels100gand100h, a photoelectric conversion device that can change the charge-voltage conversion efficiency in three levels can be provided.

Seventh Embodiment

Each photoelectric conversion device in the embodiments described above is applicable to various apparatuses. Such an apparatus may be a digital still camera, a digital camcorder, a camera head, a copy machine, a fax machine, a mobile phone, an on-vehicle camera, an observation satellite, a surveillance camera, or the like.FIG.15illustrates a block diagram of a digital still camera as an example of an apparatus.

An apparatus7illustrated inFIG.15includes a barrier706, a lens702, an aperture704, and an imaging device70(an example of the photoelectric conversion device). The apparatus7further includes a signal processing unit (processing device)708, a timing generation unit720, a general control/operation unit718(control device), a memory unit710(storage device), a storage medium control IN unit716, a storage medium714, and an external IN unit712. At least one of the barrier706, the lens702, and the aperture704is an optical device adapted for the apparatus. The barrier706protects the lens702, and the lens702captures an optical image of an object onto the imaging device70. The aperture704changes the amount of light that has passed through the lens702. The imaging device70is configured as with the embodiments described above and converts an optical image captured by the lens702into image data (image signal). Herein, an analog-to-digital (AD) conversion unit is formed on a semiconductor substrate of the imaging device70. The signal processing unit708performs various correction, data compression, or the like on imaging data output from the imaging device70. The timing generation unit720outputs various timing signals to the imaging device70and the signal processing unit708. The general control/operation unit718controls the overall digital still camera, and the memory unit710temporarily stores image data. The storage medium control IN unit716is an interface used for storage or reading of image data on the storage medium714, and the storage medium714is a removable storage medium, such as a semiconductor memory used for storage or reading of imaging data. The external IN unit712is an interface used for communicating with an external computer or the like. A timing signal or the like may be input from the outside of the apparatus. Further, the apparatus7may include a display device (a monitor, an electronic view finder, or the like) that displays information obtained by the photoelectric conversion device. The apparatus includes at least the photoelectric conversion device. The apparatus7further includes at least any one of the optical device, the control device, the processing device, the display device, the storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable unit (for example, a robot arm) that operates in response to a signal from the photoelectric conversion device.

While the imaging device70and the AD conversion unit are provided on the separate semiconductor substrates in the present embodiment, the imaging device70and the AD conversion unit may be formed on the same semiconductor substrate. Further, the imaging device70and the signal processing unit708may be formed on the same semiconductor substrate.

Further, each pixel may include a plurality of photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit) as with the fifth embodiment, for example. The signal processing unit708may be configured to process a pixel signal based on charges generated by the first photoelectric conversion unit and a pixel signal based on charges generated by the second photoelectric conversion unit and acquire distance information on the distance from the imaging device70to an object.

Eighth Embodiment

FIG.16AandFIG.16Bare block diagrams of an apparatus related to an on-vehicle camera in the present embodiment. An apparatus8has an imaging device80(an example of the photoelectric conversion device) of any of the embodiments described above and a signal processing device (processing device) that processes signals from the imaging device80. The apparatus8has an image processing unit801that performs image processing on a plurality of image data acquired by the imaging device80and a parallax calculation unit802that calculates a parallax (a phase difference of parallax images) from the plurality of image data acquired by the apparatus8. Further, the apparatus8has a distance measurement unit803that calculates a distance to the object based on the calculated parallax and a collision determination unit804that determines whether or not there is a collision possibility based on the calculated distance. Here, the parallax calculation unit802and the distance measurement unit803represent an example of a distance information acquisition unit that acquires distance information on the distance to an object. That is, the distance information is information on a parallax, a defocus amount, a distance to an object, or the like. The collision determination unit804may use any of the distance information to determine the collision possibility. The distance information acquisition unit may be implemented by dedicatedly designed hardware or may be implemented by a software module. Further, the distance information acquisition unit may be implemented by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) or may be implemented by a combination thereof.

The apparatus8is connected to the vehicle information acquisition device810and can acquire vehicle information, such as a vehicle speed, a yaw rate, a steering angle, or the like. Further, the apparatus8is connected to a control ECU820, which is a control device that outputs a control signal for causing a vehicle to generate braking force based on a determination result from the collision determination unit804. Further, the apparatus8is also connected to an alert device830that issues an alert to the driver based on a determination result from the collision determination unit804. For example, when the determination result from the collision determination unit804indicates a high collision probability, the control ECU820performs vehicle control to avoid a collision or reduce damage by applying a brake, pushing back an accelerator, suppressing engine power, or the like. The alert device830alerts a user by sounding an alert, such as a sound, displaying alert information on a display of a car navigation system or the like, providing vibration to a seat belt or a steering wheel, or the like. The apparatus8functions as a control unit that controls the operation of controlling a vehicle as described above.

In the present embodiment, an area around a vehicle, for example, an image of the front area or the rear area is captured by using the apparatus8.FIG.16Billustrates the apparatus when an image of the front area of a vehicle (a capturing area850) is captured. The vehicle information acquisition device810as an imaging control unit instructs the apparatus8or the imaging device80to perform an imaging operation. Such a configuration can further improve the ranging accuracy.

Although the example of control for avoiding a collision to another vehicle has been described above, the embodiment is applicable to automatic driving control for following another vehicle, automatic driving control for not going out of a traffic lane, or the like. Furthermore, the apparatus is not limited to a vehicle, such as an automobile and can be applied to a movable body (movable apparatus), such as a ship, an airplane, a satellite, an industrial robot and a consumer use robot, or the like, for example. In addition, the apparatus can be widely applied to an apparatus which utilizes object recognition or biometric authentication, such as an intelligent transportation system (ITS), a surveillance system, or the like without being limited to movable bodies.

Modified Embodiments

The present disclosure can be modified in various ways and is not limited to the embodiments described above. For example, an example in which a configuration of a part of any of the embodiments is added to another embodiment or an example in which a configuration of a part of any of the embodiments is replaced with a configuration of a part of another embodiment is also one of the embodiments of the present disclosure.

Some embodiments can also be realized by a computer of a system or apparatus that reads out and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be referred to more fully as a ‘non-transitory computer-readable storage medium’) to perform the functions of one or more of the above-described embodiments and/or that includes one or more circuits (e.g., application specific integrated circuit (ASIC)) for performing the functions of one or more of the above-described embodiments, and by a method performed by the computer of the system or apparatus by, for example, reading out and executing the computer-executable instructions from the storage medium to perform the functions of one or more of the above-described embodiments and/or controlling the one or more circuits to perform the functions of one or more of the above-described embodiments. The computer may comprise one or more processors (e.g., central processing unit (CPU), micro processing unit (MPU)) and may include a network of separate computers or separate processors to read out and execute the computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or the storage medium. The storage medium may include, for example, one or more of a hard disk, a random-access memory (RAM), a read only memory (ROM), a storage of distributed computing systems, an optical disk (such as a compact disc (CD), digital versatile disc (DVD), or Blu-ray Disc (BD)™), a flash memory device, a memory card, and the like.

While the present disclosure has described exemplary embodiments, it is to be understood that some embodiments are not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

This application claims priority to Japanese Patent Application No. 2021-060266, which was filed on Mar. 31, 2021 and which is hereby incorporated by reference herein in its entirety.