Patent ID: 12204357

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are as follows to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments, or examples, illustrated in the drawings are disclosed below using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations and modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art.

Further, it is understood that several processing steps and/or features of a device may be only briefly described. Also, additional processing steps and/or features can be added, and certain of the following processing steps and/or features can be removed or changed while still implementing the claims. Thus, the following description should be understood to represent examples only, and are not intended to suggest that one or more steps or features is required.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG.1is a schematic diagram of an electronic device1in accordance with some embodiments of the present disclosure. The electronic device1may be referred to as a low dropout (LDO) circuit. The electronic device1includes a current mirror10, an amplifier15, a power stage30, a compensation circuit40, and a feedback circuit50. The electronic device1may include an input terminal IN and an output terminal OUT. The electronic device1may be configured to receive a first voltage V1(or an input voltage) at the input terminal IN. The electronic device1may be configured to provide a second voltage V2(or an output voltage) at the output terminal OUT. The amplifier15is electrically connected to the input terminal IN. The power stage30is electrically connected to the input terminal IN. The power stage30is electrically connected to the output terminal OUT. In some embodiments, the electronic device1may include a load capacitor CL. The power stage30is electrically connected to a load capacitor CL. The compensation circuit40is electrically connected to the amplifier15. The compensation circuit40is electrically connected to the power stage30. The compensation circuit40is electrically connected to the feedback circuit50. The feedback circuit50is electrically connected to the amplifier15. The feedback circuit50is electrically connected to the power stage30.

The current mirror10includes a transistor M11and a transistor M12. The transistor M11or M12may include a MOS field-effect transistor (FET). The transistor M11or M12may include a p-type MOSFET or an n-type MOSFET. The exemplary transistor as shown inFIG.1for the transistor M11or M12will be an n-type MOSFET. The transistor M11has a source electrically connected to the ground VSS, a drain electrically connected to an independent bias current source IBIAS, and a gate electrically connected to the drain of the transistor M11. The transistor M12has a source electrically connected to the ground VSS, a drain electrically connected to the amplifier15, and a gate electrically connected to the gate of the transistor M11.

The transistor M11or M12may include a short-channel transistor. The transistor M11or M12may include a transistor with a minimum-available channel length. The transistor M11or M12may include a FIN-FET. The transistor M11or M12may include a core transistor. The core transistor may be defined as a transistor manufactured in a core region of a semiconductor device. The core transistor may be defined as a transistor manufactured at a minimum-available dimension. For example, the gate length of the core transistor may be significantly smaller than an I/O transistor or a high-voltage transistor. The gate length of the core transistor may be, for example, less than or equal to, but is not limited to, around 65 nm, 45 nm, 28 nm, 20 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 1 nm or less.

The current mirror10is configured to receive a first constant current from the independent bias current source IBIASand, in response to the first constant current, provide a second constant current to the amplifier15. The first constant current may be the same as the second constant current. The independent bias current source IBIASis electrically connected to the input terminal IN of the electronic device1.

The amplifier15has a first input node151and a second input node152, and an output node153. The amplifier15may be an operational amplifier (OPA). The amplifier15is configured to amplify the difference between the voltages received by the first input node151and the second input node152and provide a voltage at the output node153proportional thereto.

The amplifier15may include transistors M21, M22, M23, M24, MS1, and MS4. The transistors M21, M22, M23, M24, MS1, and MS4may each include a MOS field-effect transistor (FET). The transistors M21, M22, M23, M24, MS1, and MS4may each include a p-type MOSFET or an n-type MOSFET. The exemplary transistor as shown inFIG.1for the transistor M21or M22will be an n-type MOSFET. The exemplary transistor as shown inFIG.1for the transistor M23, M24, MS1, or MS4will be a p-type MOSFET.

The transistor M21has a source electrically connected to the drain of the transistor M12of the current mirror10, a gate electrically connected to the first input node151of the amplifier15, and a drain electrically connected to a drain of the transistor M23. The gate of the transistor M21(or the first input node152) is configured to receive a feedback voltage VFBfrom the feedback circuit50.

The transistor M22has a source electrically connected to the drain of the transistor M12of the current mirror10, a gate electrically connected to the second input node152of the amplifier15, and a drain electrically connected to the output node153of the amplifier15. The source of the transistor M21and the source of the transistor M22are electrically connected with each other. The gate of the transistor M22(or the second input node152) is configured to receive a reference voltage VBG. The reference voltage VBGmay be provided by a voltage reference circuit (or a bandgap circuit). The reference voltage VBGmay be maintained within a predetermined range. The reference voltage VBGmay be a desirable constant voltage.

In some embodiments, the transistors M21and M22may consist of a differential pair.

The transistor M23has a source electrically connected to the input terminal IN of the electronic device1, the drain electrically connected to the drain of the transistor M21, and a gate electrically connected to a gate of the transistor M24. The transistor M24has a source electrically connected to the output terminal OUT of the electronic device1, the drain electrically connected to the drain of the transistor M22, and the gate electrically connected to the gate of the transistor M24. In some embodiments, the input terminal IN may act as a power supply (e.g., AVDD) for the amplifier15.

The transistor MS1may be referred to as a switch transistor. The switch transistor MS1has a source electrically connected to the gate of the transistor M23, a drain electrically connected to the drain of the transistor M23, and a gate configured to receive a bias voltage VB1(or a first bias voltage). The first bias voltage VB1may be smaller than the first voltage V1at the input terminal IN. The first bias voltage VB1may be proportional to the first voltage V1at the input terminal IN. The switch transistor MS1is turned off when the absolute value of the bias voltage VB1is less than the absolute value of the threshold voltage of the switch transistor MS1. The switch transistor MS1is turned on when the absolute value of the bias voltage VB1is greater than the absolute value of the threshold voltage of the switch transistor MS1. For example, in the event that the switch transistor MS1is a p-type MOSFET, the switch transistor MS1is turned off when the bias voltage VB1is higher than the threshold voltage of the switch transistor MS1. The switch transistor MS1is turned on when the bias voltage VB1is lower than the threshold voltage of the switch transistor MS1.

The transistor MS4may be referred to as a switch transistor. The switch transistor MS4has a source electrically connected to the drain of the transistor M24and the drain of the transistor M22, a drain electrically connected to the output node153of the amplifier15, and a gate configured to receive a power control signal Pd2. The amplifier15may be configured to generate an output voltage VAMP1at the output node153(or at the drain of the switch transistor MS4). The output voltage VAMP1is proportional to a difference between the voltage VFBreceived by the first input node151and the voltage VBGreceived by the second input node152.

The switch transistor MS4is turned off when the absolute value of the power control signal Pd2is less than the absolute value of the threshold voltage of the switch transistor MS4. The switch transistor MS4is turned on when the absolute value of the power control signal Pd2is greater than the absolute value of the threshold voltage of the switch transistor MS4. For example, in the event that the switch transistor MS4is a p-type MOSFET, the switch transistor MS4is turned off when the power control signal Pd2is higher than the threshold voltage of the switch transistor MS1. The switch transistor MS4is turned on when the power control signal Pd2is lower than the threshold voltage of the switch transistor MS4.

The transistors M21, M22, M23, M24, MS1, and MS4may each include a short-channel transistor. The transistors M21, M22, M23, M24, MS1, and MS4may each include a transistor with a minimum-available channel length. The transistors M21, M22, M23, M24, MS1, and MS4may each include a FIN-FET. The transistors M21, M22, M23, M24, MS1, and MS4may each include a core transistor. The core transistor may be defined as a transistor manufactured in a core region of a semiconductor device. The core transistor may be defined as a transistor manufactured at a minimum-available dimension. For example, the gate length of the core transistor may be significantly smaller than an I/O transistor or a high-voltage transistor. The gate length of the core transistor may be, for example, less than or equal to, but is not limited to, around 65 nm, 45 nm, 28 nm, 20 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 1 nm or less.

The power stage30has a first terminal301electrically connected to the input terminal IN of the electronic device1, a second terminal302electrically connected to the output node153of the amplifier15, and a third terminal303electrically connected to the output terminal OUT of the electronic device1. The third terminal303may be electrically connected to the load capacitor CL. The third terminal303of the power stage30may be electrically connected to an external system.

The power stage30includes a transistor M31and a transistor M32. The transistor M31or M32may include a MOS field-effect transistor (FET). The transistor M31or M32may include a p-type MOSFET or an n-type MOSFET. The exemplary transistor as shown inFIG.1for the transistor M31or M32will be a p-type MOSFET.

The transistor M31has a source electrically connected to the input terminal IN of the electronic device1, a gate electrically connected to the output node153of the amplifier15, a drain electrically connected to a source of the transistor M32. The gate of the transistor M31may be configured to receive the output voltage VAMP1from the amplifier15. The transistor M31may be configured to generate a current ISDfrom the source to the drain of the transistor M31based on the magnitude of the voltage at the gate, e.g., the output voltage VAMP1. If the absolute value of the voltage at the gate of the p-type transistor M31is lower, the current ISDwill be greater, and vice versa.

The transistor M32has the source electrically connected to the drain of the transistor M31, a gate configured to receive an adaptive bias voltage VBA, and a drain electrically connected to the output terminal OUT of the electronic device1.

The transistor M31or M32may include a short-channel transistor. The transistor M31or M32may include a transistor with a minimum-available channel length. The transistor M31or M32may include a FIN-FET. The transistor M31or M32may include a core transistor. The core transistor may be defined as a transistor manufactured in a core region of a semiconductor device. The core transistor may be defined as a transistor manufactured at a minimum-available dimension. For example, the gate length of the core transistor may be significantly smaller than an I/O transistor or a high-voltage transistor. The gate length of the core transistor may be, for example, less than or equal to, but is not limited to, around 65 nm, 45 nm, 28 nm, 20 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 1 nm or less.

The compensation circuit40includes a resistor RCand a capacitor CCconnected in series. The compensation circuit40is electrically connected between the gate of the transistor M31of the power stage30and the drain of the transistor32of the power stage M31. In some embodiments, the output node153of the amplifier15may generate a first pole in the frequency response for the electronic device1. The output terminal OUT may generate a second pole in the frequency response for the electronic device1. The value of the second pole may exceed that of the first pole. The compensation circuit40may generate a zero for the frequency response of the electronic device1. The first pole generated at the output node153of the amplifier15may be cancelled out by the zero generated by the compensation circuit40. As such, the electronic device1is more stable. Output noise (e.g., the thermal noise) at the output terminal OUT can be minimized.

The feedback circuit50includes a first resistor RFB1and a second resistor RFB2connected in series. The feedback circuit50has a first terminal501electrically connected to the output terminal OUT or the third terminal303of the power stage30, a second terminal502between the first resistor RFB1and the second resistor RFB2, and a third terminal503connected to the ground VSS. The second terminal502of the feedback circuit50is configured to provide the feedback voltage VFBto the amplifier15, e.g., the first input node151of the amplifier15. The ratio of the feedback voltage VFBand the voltage V2at the output terminal OUT may be equal to the ratio of RFB2/(RFB1+RFB2). The feedback voltage VFBmay be smaller than the voltage V2at the output terminal OUT.

The feedback circuit50may build a negative feedback loop for the electronic device1. The electronic device1is configured to maintain the voltage V2at the output terminal OUT. For example, when the voltage V2at the first terminal151of the feedback circuit50(or at the output terminal OUT) increases, the feedback voltage VFBincreases, which in turn raises the difference between the feedback voltage VFBat the first input terminal151and the reference voltage VBGat the second input terminal152of the amplifier15. Therefore, the amplifier15generates a greater output voltage VAMP1, which is in turn introduced to the gate of the transistor M31. Subsequently, the drain current ISDis lower, as is the voltage V2at the output terminal OUT accordingly.

The electronic device1is configured to receive the first voltage V1at the input terminal IN and, in response to the first voltage V1, provide the second voltage V2at the output terminal OUT, which may connect to a next stage or an external system. The second voltage V2is relatively more stable than the first voltage V1. The second voltage V2may be lower than the first voltage V1. For example, the first voltage V1may be around 2.0V and the second voltage V2around 1.0V. The transistor M31or M32may include a core transistor, which can be applied with a core-specific maximum voltage between the gate and the drain, the gate and the source, or the drain and the source. In some embodiments, the core-specific maximum voltage is around 1.0V, 0.75V, or less. The voltage applied between the drain and source of the transistor M31, between the drain and gate of the transistor M31, or between the gate and source of the transistor M31of the power stage30should be lower than the core-specific maximum voltage to ensure reliability.

The adaptive bias voltage VBAmay be varied in response to the voltage at the input terminal IN of the electronic device1. In response to the adaptive bias voltage VBA, a voltage applied between the drain and source of the transistor M31, between the drain and gate of the transistor M31, or between the gate and source of the transistor M31of the power stage can be controlled to be less than or equal to the core-specific maximum voltage. The transistor M32is configured to, in response to the adaptive bias voltage VBA, constrain the voltage drop on the junction within the transistor M31, and protect the transistor M31from being stressed in a high-voltage condition (e.g., the transistor M31operates at a voltage exceeding the core-specific maximum voltage). As such, the transistor M31will not experience the high-voltage-induced damage. In some embodiments, the transistor M32is configured to constrain the current ISDin response to the adaptive bias voltage VBA, and protect the transistor M31from being stressed in a high-voltage condition. Furthermore, in response to the adaptive bias voltage VBA, a voltage applied between the drain and source of the transistor M32, between the drain and gate of the transistor M32, or between the gate and source of the transistor M32may be lower or equal to the core-specific maximum voltage. As such, the transistor M32will not experience any high-voltage-induced damage.

In some embodiments, the power stage30may include more transistors for the protection of the transistor M31from being stressed in a high-voltage condition.

In an LDO circuit, a power transistor responsible for generating an output voltage would have to sustain a relatively high voltage drop. Generally, the power transistor would be an I/O transistor with a high threshold voltage and a high voltage endurance. However, the drawbacks of the I/O transistor, such as limited input range and incompatible manufacturing process, are no longer suitable for some wide operation voltage range circuits, such as, system-on-chip (SOC) digital circuits with dynamic voltage and frequency scaling, and high-performance circuits such as a computer processing unit (CPU), graphic processing unit (GPU), or super computer applications.

In the present disclosure, the core transistor M31of the power stage has a relatively strong driving capability which means that it can achieve the same driving current as an I/O transistor, but with a smaller size. The relatively small size of the core transistor M31can reduce the size of the electronic device1. The relatively small threshold voltage of the core transistor M31promises a wider input range. The core transistor M32protects the core transistor31from being stressed in a high-voltage condition. Therefore, the power stage30with core transistors has a relative strong driving capacity and a relatively small size in comparison with an I/O power transistor. Furthermore, the electronic device1, which consists of core transistors, is compatible with the manufacturing of the advanced node. For example, the electronic device1(e.g., the LDO circuit) and other high-performance circuits can be manufactured under the same process flow. The integration of the electronic device (e.g., the LDO circuit) and the other high-performance circuits can be improved.

The electronic device is configured to operate in a first mode when the gate of the transistor M31receives the output voltage VAMP1from the amplifier15. The electronic device1is configured to operate in a second mode when the gate of the transistor M24and the gate of the transistor M31are pulled up to a power supply. In some embodiments, the gate of the transistor M24may be electrically connected to a reset transistor, and such reset transistor may be configured to pull the voltage at the gate of the transistor M24to the power supply. The amplifier15is thereby disabled. In some embodiments, the gate of the transistor M31may be electrically connected to a reset transistor, and such reset transistor may be configured to pull the voltage at the gate of the transistor M31to the power supply. The power stage30is thereby disabled.

The first mode indicates that the electronic device1is enabled. In some embodiments, the first mode may be referred to as a normal mode. The second mode indicates that the electronic device1is disabled. In some embodiments, the second mode may be referred to as a power down mode.

In the first mode, the switch transistor MS4is turned on in response to the power control signal Pd2. For example, the power control signal Pd2may be logic low and the p-type switch transistor MS4may be turned on. In some embodiments, electronic device1is configured to operate in the first mode, when the switch transistor MS4is turned on.

In the second mode, the switch transistor MS4is turned off in response to the power control signal Pd2. For example, the power control signal Pd2may be logic high and the p-type switch transistor MS4may be turned off. The switch transistor MS4is configured to isolate the amplifier15from the power stage30(e.g., the gate of the transistor M31of the power stage30) during the pull-up of the gate of the transistor M31. In some embodiments, the electronic device1is configured to operate in the second mode when the switch transistor MS4is turned off.

FIG.2is a schematic diagram of an electronic device2in accordance with some embodiments of the present disclosure. The electronic device2may be referred to as an LDO circuit. The electronic device2ofFIG.2is similar to the electronic device1ofFIG.1, and some of the differences therebetween are as follows.

The electronic device2includes an amplifier20. The amplifier20has a first input node201and a second input node202, and an output node203. The amplifier20may be an OPA. The amplifier20is configured to amplify the difference between the feedback voltage VFBreceived by the first input node201and the reference voltage VBGreceived by the second input node202, and to provide a voltage VAMP2at the output node203proportional thereto.

The amplifier20of the electronic device2is similar to the amplifier15of the electronic device1, except that the amplifier20further includes transistors M25, M26, M27, M28, MS2, and MS3. The amplifier20may be a cascode operation amplifier. The transistors M25, M26, M27, M28, MS2, and MS3may each include a MOS field-effect transistor (FET). The transistors M25, M26, M27, M28, MS2, and MS3may each include a p-type MOSFET or an n-type MOSFET. The exemplary transistor as shown inFIG.2for the transistors M27, M28, and MS3will be an n-type MOSFET. The exemplary transistor as shown inFIG.2for the transistor M25, M26, or MS3will be a p-type MOSFET.

The transistor M25has a source electrically connected to the drain of the transistor M23, a gate electrically connected to a gate of the transistor M26, and a drain electrically connected to the drain of the transistor M27. The transistor M26has a source electrically connected to the drain of the transistor M24, a gate electrically connected to the gate of the transistor M25, and a drain electrically connected to the drain of the transistor M28. The drain of the transistor M26is electrically connected to the source of the switch transistor MS4. The gate of the transistor M25and the gate of the transistor M26are configured to receive a bias voltage VB2(or a second bias voltage). The second bias voltage VB2is smaller than the bias voltage VB1applied on the gate of the switch transistor MS1. The first bias voltage VB2may be proportional to the first voltage V1at the input terminal IN.

The transistor M27has a source electrically connected to the drain of the transistor M21, a gate electrically connected to a gate of the transistor M28, and a drain electrically connected to the drain of the transistor M25. The transistor M28has a source electrically connected to the drain of the transistor M22, the gate electrically connected to the gate of the transistor M27, and a drain electrically connected to the drain of the transistor M28. The drain of the transistor M28is electrically connected to the source of the switch transistor MS4. The gate of the transistor M27and the gate of the transistor M28are configured to receive a bias voltage VB3(or a third bias voltage). The third bias voltage VB3is smaller than the second bias voltage VB2The third bias voltage VB3may be proportional to the first voltage V1at the input terminal IN.

The switch transistor MS2has a source electrically connected to the gate of the transistor M26, a gate configured to receive a bias voltage VB4(or a fourth bias voltage), and a drain electrically connected to the drain of the transistor M26. The switch transistor MS3has a source electrically connected to the drain of the transistor M27, a gate configured to receive a power control signal Pd1, and a drain electrically connected to the gate of the transistor M27. The fourth bias voltage VB4is smaller than the first voltage V1at the input terminal. The fourth bias voltage VB4may be proportional to the first voltage V1at the input terminal IN. The fourth bias voltage VB4is greater than the first bias voltage VB1.

The transistors M25, M26, M27, M28, MS2, and MS3may each include a short-channel transistor. The transistors M25, M26, M27, M28, MS2, and MS3may each include a transistor with a minimum-available channel length. The transistors M25, M26, M27, M28, MS2, and MS3may each include a FIN-FET. The transistors M25, M26, M27, M28, MS2, and MS3may each include a core transistor. The core transistor may be defined as a transistor manufactured in a core region of a semiconductor device. The core transistor may be defined as a transistor manufactured at a minimum-available dimension. For example, the gate length of the core transistor may be significantly smaller than an I/O transistor or a high-voltage transistor. The gate length of the core transistor may be, for example, less than or equal to, but is not limited to, around 65 nm, 45 nm, 28 nm, 20 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 1 nm or less.

Table I as provided here illustrates the exemplary voltages at different nodes in the electronic device1in the first mode (normal mode) and the second mode (power down mode):

TABLE INodeNormal ModePower Down ModeV1Logic HighLogic HighVB1Logic LowLogic HighVB2Logic HighLogic HighVB3Logic HighLogic HighVB4Logic HighLogic LowPd1Logic LowLogic HighPd2Logic LowLogic High

FIG.3Ashows an equivalent circuit3A of the electronic device2in the first mode as shown inFIG.2, in accordance with some embodiments of the present disclosure. The switch transistor MS1connects the gate and the source of the transistor M23in response to the first bias voltage VB1, and the transistor M23operates in a diode-connected mode. The diode-connected transistor M23acts as an active load and mirrors the current from the transistor M23to the transistor M24. For example, the first bias voltage VB1may be logic low and the p-type switch transistor MS1may be turned on. The first bias voltage VB1is adapted with the voltage V1at the input terminal IN. In some embodiments, when the voltage V1is low, the first bias voltage VB1is low and vice versa. The first bias voltage VB1is a division of the voltage V1at the input terminal IN.

The switch transistor MS2is turned off in response to the fourth bias voltage VB4. For example, the fourth bias voltage VB4may be logic high and the p-type switch transistor MS2may be turned off. The fourth bias voltage VB4is adapted with the voltage V1at the input terminal IN. In some embodiments, when the voltage V1is low, the fourth bias voltage VB4is low and vice versa. The bias voltage VB4is a division of the voltage V1at the input terminal IN.

The switch transistor MS3is turned off in response to the power control signal Pd1. For example, the power control signal Pd1may be logic low and the n-type switch transistor MS3may be turned off. The switch transistor MS4is turned on in response to the power control signal Pd2. For example, the power control signal Pd2may be logic low and the p-type switch transistor MS4may be turned on.

In some embodiments, the electronic device1is configured to operate in the first mode when the switch transistor MS1is turned on and the switch transistor MS2and switch transistor MS3are turned off.

As shown inFIG.3A, an equivalent circuit20A of the cascode operational amplifier20ofFIG.2is configured to receive the feedback voltage VFBat the first input node201and the reference voltage VBGat the second input node202, and provide the output voltage VAMP2at the output node203. The power stage30is configured to receive the output voltage VAMP2at the gate and, in response to the VAMP2and the voltage V1from the input terminal IN, generate the current ISD. The power stage30is then configured to provide the voltage V2at the output terminal OUT based on the current ISDand the equivalent impedance at the output terminal OUT.

The second bias voltage VB2is adapted with the voltage V1at the input terminal IN. In some embodiments, when the voltage V1is low, the second bias voltage VB2is low and vice versa. The second bias voltage VB2is a division of the voltage V1at the input terminal IN. The third bias voltage VB3is adapted with the voltage V1at the input terminal IN. In some embodiments, when the voltage V1is low, the third bias voltage VB3is low and vice versa. The third bias voltage VB3is a division of the voltage V1at the input terminal IN. Since the second bias voltage VB2and the third bias voltage VB3are adapted with the voltage V1at the input terminal IN, the input voltage range of the electronic device1will increase.

FIG.3Bshows an equivalent circuit3B of the electronic device2in the second mode as shown inFIG.2, in accordance with some embodiments of the present disclosure. The switch transistor MS1disconnects the gate and the source of the transistor M23in response to the first bias voltage VB1. For example, the first bias voltage VB1may be logic high and the p-type switch transistor MS1may be turned off. The switch transistor MS2is turned on in response to the fourth bias voltage VB4. For example, the fourth bias voltage VB4may be logic low and the p-type switch transistor MS2may be turned on. The switch transistor MS3is turned on in response to the power control signal Pd1. For example, the power control signal Pd1may be logic high and the n-type switch transistor MS3may be turned on. The switch transistor MS4is turned off in response to the power control signal Pd2. For example, the power control signal Pd2may be logic high and the p-type switch transistor MS4may be turned off.

In some embodiments, the electronic device1is configured to operate in the second mode when the switch transistor MS1is turned off and the switch transistor MS2and switch transistor MS3are turned on.

As shown inFIG.3B, an equivalent circuit20B of the amplifier20is electrically isolated from the power stage30when the switch transistor MS4is turned off. The gate of the transistor M31can be pulled up to the power supply without any interference from the amplifier20. Therefore, no high voltage will be applied between the gate and the drain, the drain and the source, or the gate and the source of the transistor M31. Furthermore, the core transistors M25, M26, M27, and M28may form a self-biased loop and a voltage at the node between the drain of the core transistor M26and the drain of the transistor core M28may be stable at a certain level, instead of floating. Due to being self-biased, and as a result of the isolation by the switch transistor MS4, the core transistors M26and M28will be insulated from any noise disturbance. Therefore, no relatively high voltage will be applied between the gate and the drain, the drain and the source, or the gate and the source of the core transistor M26. Similarly, no relatively high voltage will be applied between the gate and the drain, the drain and the source, or the gate and the source of the core transistor M28. The core transistors M26and M28are free from being stressed in a high-voltage condition (e.g., any voltage which exceeds the core-specific maximum voltage).

FIG.4is a top view of the electronic device2inFIG.2in accordance with some embodiments of the present disclosure. The power stage30is disposed adjacent to the amplifier20and the feedback circuit50. The compensation circuit40is disposed between the amplifier20and the load capacitor CL. The feedback circuit50is disposed between the amplifier20and the load capacitor CL. The feedback circuit50and the compensation circuit40may be integrated. The feedback circuit50and the compensation circuit40may consist of one or more capacitor array and one or more resistor to improve the resistor-capacitor (RC) network matching. The feedback circuit50is disposed between the power stage30and the load capacitor CL. The output terminal may be disposed adjacent the load capacitor CL. The power stage30may have a substantially rectangular area on a substrate SUB in which the electronic device2is disposed. The rectangular power stage30enlarges the total width of the conductive lines through the power stage30from the input terminal IN to the output terminal OUT.

The load capacitor CLmay have a substantially rectangular area on the substrate SUB. The amplifier20may have a substantially rectangular area on the substrate SUB. The feedback circuit50may have a substantially rectangular area on the substrate SUB. Furthermore, the electronic device2includes another output terminal OUT′ adjacent to the other side of the load capacitor CL.

FIG.5is a cross-sectional view of the electronic device1inFIG.1in accordance with some embodiments of the present disclosure. As shown inFIG.5, the electronic device1further includes a first via stacking structure VS1disposed on the source of the transistor M31, a second via stacking structure VS2disposed on the drain of the transistor M32, a first conductive via TV1, a second conductive via TV2, a first conductive layer TM1, and a second conductive layer TM2.

The first via stacking structure VS1includes a plurality of conductive vias VIA10, VIA11, VIA12. . . , VIA1nand a plurality of conductive layers M10, M11. . . , M1n. The reference “n” is a positive integer. The first via stacking structure VS1is electrically connected to the source of the transistor M31. The first via stacking structure VS1extends from the source of the transistor M31vertically. The first conductive via TV1connects the first conductive layer TM1and the first via stacking structure VS1. The first conductive layer TM1is configured to receive the voltage V1from the input terminal IN. The first conductive layer TM1may have a smaller resistivity than any of the conductive layers M10, M11. . . , M1nof the first stacking via structure VS1.

The second via stacking structure VS2includes a plurality of conductive vias VIA20, VIA21, VIA22. . . , VIA2nand a plurality of conductive layers M20, M21. . . , M2n. The second via stacking structure VS2is electrically connected to the drain of the transistor M32. The second via stacking structure VS2extends from the drain of the transistor M32vertically. The second conductive via TV2connects the second conductive layer TM2and the second via stacking structure VS2. The second conductive layer TM2is configured to provide the voltage V2to the output terminal OUT. The second conductive layer TM2may have a smaller resistivity than any of the conductive layers M20, M21. . . , M2nof the second stacking via structure VS2.

The input terminal IN has a first projecting area A1on the substrate and the source of the transistor M31has a second projecting area A2on the substrate. The first projecting area A1is free from overlapping the second projecting area A2. In other words, the first projecting area A1does not overlap the second projecting area A2. The first via stacking structure VS1extends between and electrically connects the input terminal IN and the source of the transistor M31. The first conductive layer TM1may extend in a direction perpendicular to the extending direction of the first via stacking structure VS1. Therefore, the current path between the input terminal IN and the source of the transistor M31is mainly within the first conductive layer TM1having a smaller resistivity. As such, the IR drop between the input terminal IN and the source of the transistor M31is less and the electron migration (EM) effect can be improved.

The terminal OUT has a third projecting area A3on the substrate and the drain of the transistor M32has a fourth projecting area A4on the substrate. The third projecting area A3is free from overlapping the fourth projecting area A4. In other words, the third projecting area A3does not overlap the fourth projecting area A4. The second via stacking structure VS2extends between and electrically connects the output terminal OUT with the drain of the transistor M32. The second conductive layer TM2may extend in a direction perpendicular to the extending direction of the second via stacking structure VS2. Therefore, the current path between the output terminal OUT and the drain of the transistor M31is mainly within the second conductive layer TM2having a smaller resistivity. As such, the IR drop the output terminal OUT and the drain of the transistor M31is less and the EM effect can improved.

The first via stacking structure VS1may include metal materials, such as Cu, Ti, Ta, Au, Al, or the like. The second via stacking structure VS2may include metal materials, such as Cu, Ti, Ta, Au, Al, or the like. The first conductive via TV1, a second conductive via TV2, a first conductive layer TM1, and a second conductive layer TM2may each include metal materials, such as Cu, Ti, Ta, Au, Al, or the like.

FIG.6is a flow chart of a method200of manufacturing an LDO circuit (e.g., the electronic device1inFIG.1) in accordance with some embodiments of the present disclosure. The method200includes steps S201, S203, S205, S207, S209, and S211.

In step S201, a substrate is provided. The substrate may include a doped wafer.

In step S203, a first transistor (e.g., the transistor M31) and a second transistor (e.g., the transistor M32) of a power stage (e.g., the power stage30) are formed in a series connection in the substrate. The first transistor has a source electrically connected to an input terminal of the LDO circuit. The second transistor has a source electrically connected to a drain of the first transistor, a gate configured to receive an adaptive bias voltage (e.g., the adaptive bias voltage VBA), a drain electrically connected to an output terminal of the LDO circuit.

In step S205, a first via stacking structure (e.g., the first via stacking structure VS1) is formed to be electrically connected to the first transistor of the power stage.

In step S207, a second via stacking structure (e.g., the second via stacking structure VS2) is formed to be electrically connected to the second transistor of the power stage.

In step S209, a first conductive layer (e.g., the first conductive layer TM1) is formed to electrically connect the first via stacking structure and the input terminal of the LDO circuit. The first via stacking structure extends between and electrically connects the input terminal and the source of the transistor. The first conductive layer may extend in a direction perpendicular to the extending direction of the first via stacking structure. Therefore, the current path between the input terminal and the source of the first transistor is mainly within the first conductive layer having a smaller resistivity. As such, the IR drop between the input terminal and the source of the first transistor is less and the EM effect can be improved.

In step S211, a second conductive layer (e.g., the second conductive layer TV2) is formed to electrically connect the second via stacking structure and the output terminal of the LDO circuit. The second via stacking structure extends between and electrically connects the output terminal with the drain of the second transistor. The second conductive layer may extend in a direction perpendicular to the extending direction of the second via stacking structure. Therefore, the current path between the output terminal and the drain of the transistor is mainly within the second conductive layer having a smaller resistivity. As such, the IR drop between the output terminal and the drain of the transistor is less and the EM effect can be improved.

The present disclosure provides a low dropout (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, a cascode operational amplifier, and a power stage. The cascode operational amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the cascode operational amplifier, and a third terminal electrically connected to the output terminal.

The present disclosure provides a low dropout (LDO) circuit. The LDO circuit includes an input terminal, an output terminal, an amplifier, and a power stage. The amplifier is electrically connected to the input terminal. The power stage has a first terminal electrically connected to the input terminal, a second terminal electrically connected to an output node of the amplifier, and a third terminal electrically connected to the output terminal. The amplifier includes a fourth switch transistor electrically connected to the output node of the amplifier.

The present disclosure provides a method of manufacturing an LDO circuit, including providing a substrate; forming a first transistor and a second transistor of a power stage in a series connection in the substrate, wherein the first transistor has a source electrically connected to an input terminal of the LDO circuit, and wherein the second transistor has a source electrically connected to a drain of the first transistor, a gate configured to receive an adaptive bias voltage, and a drain electrically connected to an output terminal of the LDO circuit.

The methods and features of the present disclosure have been sufficiently described by examples and descriptions. It should be understood that any modifications or changes without departing from the spirit of the present disclosure are intended to be covered in the protection scope of the present disclosure.

Moreover, the scope of the present application in not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As those skilled in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, composition of matter, means, methods or steps presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure.

Accordingly, the appended claims are intended to include within their scope such as processes, machines, manufacture, compositions of matter, means, methods or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the present disclosure.