Patent ID: 12206411

The use of the same reference label in different drawings indicates the same or like components.

DETAILED DESCRIPTION

In the present invention, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of embodiments of the invention. Persons of ordinary skill in the art would recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

FIG.1shows a power chip100in accordance with an embodiment of the present invention. The power chip100comprises a power pin PPIN, an indicating signal generating circuit11, a communicating circuit12, a power-on detecting circuit13, a pin control circuit14and a multi-function pin MUL. The power pin PPIN receives an input voltage VIN via a voltage divider comprising a first resistor R11and a second resistor R12as shown inFIG.1. The input voltage VIN is provided by a switching converter, and is provided to the power chip100as a power-on signal FBP. The switching converter may comprise any suitable voltage converters, like a boost converter, a buck converter or a flyback converter. The power-on detecting circuit13receives the power-on signal FBP and a power-on voltage threshold REF1, and generates a power-on enabling signal PEN based on a comparison result of the power-on voltage threshold REF1and the power-on enabling signal PEN. The indicating signal generating circuit11generates an indicating signal PGS based on working states of the switching converter. In one embodiment, when the switching converter is in a normal working condition, the indicating signal PGS is logic high; when the switching converter is in an abnormal working condition, the indicating signal PGS is logic low. The abnormal working condition includes but is not limited to conditions of over-power, over-current, over-temperature, short circuit, open circuit and other circuit faults. On the contrary, the normal working condition refers to the state that the switching converter works without the aforementioned fault. The communicating circuit12receives/transmits communication data DEXT and DINT through the multi-function pin MUL via the pin control circuit14. Specifically, the communicating circuit12receives an external data DEXT from the multi-function pin MUL via the pin control circuit14, transmits an internal data DINT to the multi-function pin MUL via the pin control circuit14, and meanwhile generates an indicator enabling signal PGEN and a communication enabling signal UEN to enable/disable the data communication. The pin control circuit14receives the power-on enabling signal PEN, the indicator enabling signal PGEN, and the communication enabling signal UEN, the indicating signal PGS, the external data DEXT and the internal data DINT, and provides the indicating signal PGS and the internal data DINT to the multi-function pin MUL or receives the external data DEXT from the multi-function pin MUL based on the power-on enabling signal PEN, the indicator enabling signal PGEN, and the communication enabling signal UEN.

In one embodiment, when the power-on signal FBP is lower than the power-on voltage threshold REF1, the power-on enabling signal PEN is logic high, the multi-function pin MUL receives/transmits the communication data (the internal data DINT and the external data DEXT) through the multi-function pin; when the power-on signal FEP is higher than the power-on voltage threshold REF1, the power-on enabling signal PEN is logic low, based on the indicator enabling signal PGEN and the communication enabling signal UEN, the pin control circuit14controls the functions of multi-function pin MUL, which are: (1) providing the indicating signal PGS; (2) receiving/transmitting the communication data; (3) providing the indicating signal PGS, and receiving/transmitting the communication data. Table 1 below shows the functions of the multi-function pin MUL under the different combinations of the power-on enabling signal PEN, the indicator enabling signal PGEN and the communication enabling signal UEN in accordance with an embodiment of the present invention.

TABLE 1PENPGENUENThe function of MUL1——Receiving/transmitting the communication data010Idle000Providing indicating signal011Receiving/transmitting the communication data001Providing indicating signal and receiving/transmitting the communication data

In the embodiment shown inFIG.1, the multi-function pin MUL is coupled to a host controller19. The host controller19has a transmitting terminal TX for transmitting the external data DEXT to the multi-function pin MUL and a receiving terminal RX for receiving the internal data DINT from the multi-function pin MUL. The indicator enabling signal PGEN and the communication enabling signal UEN are set by users through the host controller19. More specifically, the external data DEXT from the host controller19sets the indicator enabling signal PGEN and the communication enabling signal UEN. In one embodiment, the power-on voltage threshold REF1is also set by users through the host controller19, which means the information of the power-on voltage threshold REF1is included in the external data DEXT transmitted to the communicating circuit12. In the embodiment ofFIG.1, the communicating circuit12further comprises a storage unit121for storing necessary information, like the communication data.

FIG.2Aschematically shows waveforms of the multi-function pin MUL of the power chip100inFIG.1, when the multi-function pin MUL provides the indicating signal PGS and transmits the internal data DINT, in accordance with an embodiment of the present invention. The signal at the multi-function pin MUL is marked as a multi-function pin signal PMUL. In the embodiment shown inFIG.2A, when the indicating signal PGS is logic high, the switching converter is in the normal working condition. Otherwise, the switching converter is in the abnormal working condition. During time t0˜t1, the indicating signal PGS is logic high and the host controller19is idle, the multi-function pin signal PMUL follows the indicating signal PGS. During time t1˜t2, the communicating circuit12transmits the internal data DINT to the host controller19through the multi-function pin MUL, and the multi-function pin signal PMUL follows the internal data DINT. During time t2˜t3, the transmission of the internal data DINT is completed, and the multi-function pin MUL provides the indicating signal PGS again. After time t3, the indicating signal PGS becomes logic low, the multi-function pin signal PMUL changes accordingly, indicating the abnormal condition of the switching converter. In the embodiment shown inFIG.2A, the internal data DINT comprises an 8-bit word, a start bit and a stop bit. It should be known that the internal data DINT may comprise other data forms.

FIG.2Bschematically shows waveforms of the multi-function pin MUL of the power chip100inFIG.1, when the multi-function pin MUL provides the indicating signal PGS and receives the external data DEXT, in accordance with an embodiment of the present invention. In the embodiment shown inFIG.2B, when the indicating signal PGS is logic high, the switching converter is in a normal working condition. Otherwise, the switching converter is in the abnormal working condition. During time t4˜t5, the indicating signal PGS is logic high and the host controller19is idle, the multi-function pin MUL follows the indicating signal PGS. During time t5˜t6, the communicating circuit12receives the external data DEXT from the host controller19through the multi-function pin MUL, and the multi-function pin signal PMUL follows the external data DEXT. During time t6˜t7, the transmission of external data DEXT is completed, and the multi-function pin MUL provides the indicating signal PGS. After time t7, the indicating signal PGS becomes logic low, the multi-function pin signal PMUL changes accordingly, indicating the abnormal condition of the switching converter. In the embodiment shown inFIG.2B, the external data DEXT comprises an 8-bit word, a start bit and a stop bit. In other embodiments, the external data DEXT may comprise other data forms.

FIG.3schematically shows a power chip300in accordance with an embodiment of the present invention. The power chip300comprises a pin control circuit34which includes a digital control circuit34a, a first switch S1, a pull-up resistor RUP, a second switch S2and a receiving data control circuit34bconnected as shown inFIG.3. The digital control circuit34areceives the indicating signal PGS, the power-on enabling signal PEN, the indicator enabling signal PGEN, the communication enabling signal UEN and the internal data DINT. Based on the indicating signal PGS, the power-on enabling signal PEN, the indicator enabling signal PGEN, the communication enabling signal UEN and the internal data DINT, the digital control circuit34agenerates a first control signal CTRL1to control the first switch S1, a second control signal CTRL2to control the second switch S2, and a third control signal CTRL3to control the receiving data control circuit34b.

FIG.4schematically shows a connection of the multi-function pin MUL of the power chip300to a post-stage circuit42with an isolation circuit41in-between, in accordance with an embodiment of the present invention. When the power-on enabling signal PEN is logic low, by additionally setting the indicator enabling signal PGEN and the communication enabling signal UEN to logic low, the multi-function pin MUL performs the function (1) providing the indicating signal PGS. In this case, as mentioned before, the first switch S1is turned on/off by the first control signal CTRL1to restore the indicating signal PGS at the multi-function pin MUL, the second switch S2keeps off by the second control signal CTRL2, and the communicating circuit32disconnects the communication circuit32from the multi-function pin MUL by the third control signal CTRL3, that is, the receiving data control circuit34bis coupled to a power chip reference ground GND1.

In the embodiment shown inFIG.4, the indicating signal PGS is provided to the post-stage circuit42through an isolation circuit41. The post-stage may be a fault indicating signal, that receives the indicating signal PGS to instruct a fault condition to be further processed by a fault processing circuit. The isolation circuit41comprises a first isolation resistor RA1, an isolation optocoupler OC1and a second isolation resistor RA2. The first isolation resistor RA1has a first terminal and a second terminal, wherein the first terminal is coupled to the multi-function pin MUL. The isolation optocoupler OC1comprises a light-emitting diode (LED) and a photosensitive triode, wherein the LED is coupled between the second terminal of the first isolation resistor RA1and the power chip reference ground GND1. The photosensitive triode has a collector, an emitter and a base, wherein the collector of the photosensitive triode is coupled to a power supply VDDA, and the emitter of the photosensitive triode provides an amplified signal PGI to the post-stage circuit42. The second isolation resistor RA2is coupled between the emitter of photosensitive triode and a post stage reference ground GND2.

FIGS.5A and5Bshow a connection of the multi-function pin MUL of the power chip300to the host controller19in accordance with an embodiment of the present invention. In the embodiments shown inFIG.5AandFIG.5B, by setting the indicator enabling signal PGEN and the communication enabling signal UEN to particular logic states, i.e., logic high as shown in Table 1, the multi-function pin MUL performs the function (2) receiving/transmitting the communication data. In this case, the first switch S1keeps on by the control of the first control signal CTRL1, the second switch S2is turned on/off by the second control signal CTRL2to restore the internal data DINT at the multi-function pin MUL, and the receiving data control circuit34bconnects the receiving terminal R of the communicating circuit32to the multi-function pin MUL to receive the external data DEXT, i.e., the signal at the multi-function pin MUL is passing through the data control circuit34b. Specifically,FIG.5Ashows the state when the internal data DINT is transmitted to the host controller19from the communicating circuit32via the second switch S2, andFIG.5Bshows the state when the external data DEXT is transmitted from the host controller19to the communicating circuit32via the data control circuit34b.

FIGS.6A and6Bshow a connection of the multi-function pin MUL of the power chip300to the host controller19in accordance with an embodiment of the present invention. Compared with the embodiments inFIGS.5A and5B, a regulating resistor REX is coupled between a power supply VEX and the multi-function pin MUL. The regulating resistor REX is configured by the users to replace the pull-up resistor RUP inside the power chip300, which means that the first switch S1is turned off to disconnect the pull-up resistor RUP in the embodiments ofFIGS.6A and6B. The working principle of the examples inFIGS.6A and6Bis similar with that inFIGS.5A and5B, and is not described here for brevity.

FIG.7schematically shows a connection of the multi-function pin MUL of the power chip300to the post-stage circuit42with a transmitting circuit71in-between, and a connection between the multi-function pin MUL of the power chip300to the host controller19with a receiving circuit72in-between, in accordance with an embodiment of the present invention. When the power-on enabling signal PEN is logic low, by setting the indicator enabling signal PGEN and the communication enabling signal UEN to particular logic states, e.g., PGEN=0 and UEN=1 as indicated by the Table 1, the multi-function pin MUL performs the function (3): providing the indicating signal PGS, and receiving/transmitting the communication data. Through the transmitting circuit71, the indicating signal PGS is provided to the post-stage circuit42, and the internal data DINT is provided to the host controller19. Through the receiving circuit72, the external data DEXT is transmitted from the transmitting terminal TX of the host controller19to the power chip300. The transmitting circuit71comprises a transmitting switch MR, a transmitting optocoupler OC2and a transmitting resistor RR1. The transmitting switch MR has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the multi-function pin MUL, and the second terminal is coupled to the power chip reference ground GND1. The transmitting optocoupler OC2comprises an LED and a photosensitive triode. The anode of the LED is coupled to a transmitting side power supply VDDP, and the cathode of the LED is coupled to the first terminal of the transmitting switch MR. The photosensitive triode has a collector, an emitter and a base, wherein the collector is coupled to a receiving side power supply VDDS and the emitter provides the indicating signal PGS or transmits the internal data DINT. The transmitting resistor RR1comprises a first terminal and a second terminal, wherein the first terminal is coupled to the emitter of the photosensitive triode, the receiving terminal RX of the host controller19and the indicating terminal PG of the post-stage circuit, and the second terminal is coupled to the post stage reference ground GND2. The receiving circuit72comprises a receiving switch MT, a receiving resistor RT1and a receiving optocoupler OC3. The receiving switch MT has a control terminal, a first terminal and a second terminal, wherein the control terminal is coupled to the transmitting terminal TX of the host controller19, and the second terminal is coupled to the post stage reference ground GND2. The first resistor RT1is coupled between the first terminal of the receiving switch MT and the receiving side power supply VDDS. The receiving optocoupler OC3comprises an LED and a photosensitive triode, wherein the LED is coupled between the first and second terminal of the switch MT. The photosensitive triode has a collector, an emitter and a gate wherein the emitter is coupled to the power chip reference ground GND1and the collector is coupled to the multi-function pin MUL.

In the embodiment ofFIG.7, the first switch S1keeps on by the control of the first control signal CTRL1, the second switch S2is turned on/off by the second control signal CTRL2to restore the internal data DINT at the multi-function pin MUL, and the receiving data control circuit34bconnects the receiving terminal R of the communicating circuit32to the multi-function pin MUL to receive the external data DEXT, i.e., the signal at the multi-function pin MUL is passing through the data control circuit34b. The internal data DINT is provided by turning on/off the second switch S2, and the external data DEXT is received through the data control circuit34b. When the indicating signal PGS indicates the abnormal working condition, the second switch S2is turned on to pull down the multi-function pin MUL, so as to provide a logic low signal to the post stage circuit42with the first priority, which means if data communication is going on, it is interrupted. The signal at the multi-function pin MUL is determined to be the internal data DINT or the indicating signal PGS by frequency.

FIG.8shows a power chip800in accordance with an embodiment of the present invention. In the embodiment ofFIG.8, the switching converters, i.e., a PFC (Power Factor Correction) circuit85and the resonance conversion circuit86provides the input voltage VIN and a load voltage VLLC respectively. Specifically, the PFC circuit85receives an AC voltage Vac and generates the input voltage VIN based on the AC voltage Vac. The resonance conversion circuit86receives the input voltage VIN and generates the load voltage VLLC based on the input voltage VIN. The power chip800receives a rectified voltage of the AC voltage Vac through an AC voltage pin ACIN and receives the input voltage VIN through the power pin PPIN. InFIG.8, the power chip800comprises the indicating signal generating circuit81, which includes an under-voltage detecting circuit81a, an over-power detecting circuit81b, and a logic circuit81c. The under-voltage detecting circuit81areceives a correction feedback signal FB1indicative of the rectified voltage of the AC voltage Vac and an under-voltage threshold REF2, and generates an under-voltage signal UVP based on a comparison result of the correction feedback signal FB1and the under-voltage threshold REF2. The over-power detecting circuit81breceives an input feedback signal FB2indicative of the input voltage VIN and an over-voltage threshold REF3, and generates an over-power signal OPP based on a comparison result of the input feedback signal FB2and the over-voltage threshold REF3. The logic circuit81creceives the under-voltage signal UVP and the over-power signal OPP, and generates the indicating signal PGS based thereon. In the embodiment ofFIG.8, when the correction feedback signal FB1is lower than the under-voltage threshold REF2, the indicating signal PGS is logic high, indicating an under-voltage condition. When the resonant feedback signal FB2is higher than the over-voltage threshold REF3, the indicating signal PGS is logic high, indicating an over-power condition. In one embodiment, the under-voltage threshold REF2and the over-voltage threshold REF3are set by the host controller19. More specifically, the information of the under-voltage threshold REF2and the over-voltage threshold REF3is included in the external data DEXT transmitted to the communicating circuit82. Persons of ordinary skill in the art should know that the under-voltage detecting circuit81aand the over-power detecting circuit81bare just for illustrating, and may be realized by any known circuit performing the similar function. It should be understood that, the indicating signal PGS is for indicating the abnormal condition of the switching converters85and86in the embodiment ofFIG.8, thus may be generated based on other fault indicating signals of the switching converters.

As shown inFIG.8, the PFC circuit85and the resonance conversion circuit86are independent from the power chip800. It should be understood that the switching converter, like the PFC circuit85and the resonance conversion circuit86may be integrated into the power chip800in other embodiments.

Continuing the illustration ofFIG.8, the power chip800comprises a pin control circuit84. The pin control circuit84is coupled to the power-on detecting circuit83, the indicating signal generating circuit81, the communicating circuit82and the multi-function pin MUL. The pin control circuit84further comprises a digital control circuit84a. The digital control circuit84acomprises a first inverter INV1, a second inverter INV2, a third inverter INV3, an NAND gate NAND1, a selector MUX, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a first OR gate OR1and a third OR gate OR3. The NAND gate NAND1has a first input terminal configured to receive the indicator enabling signal PGEN, a second input terminal configured to receive an inverted signal of the power-on enabling signal PEN, and an output terminal configured to provide a first logic signal PGF. The selector MUX1has a first input terminal configured to receive the logic power supply VCC, a second input terminal configured to receive the communication enabling signal UEN, a control terminal configured to receive an inverted signal of the power-on enabling signal PEN, and an output terminal configured to provide the third control signal CTRL3. The third control signal CTRL3is either logic high or equal to the communication enabling signal UEN under the control the power-on enabling signal PEN. The first AND gate AND1has a first input terminal configured to receive the first logic signal PGF, a second input terminal configured to receive the indicating signal PGS, and an output terminal configured to provide a third logic signal S3. The second AND gate AND2has a first input terminal configured to receive an off-chip resistor indicating signal PUP, a second input terminal configured to receive the third control signal CTRL3, and an output terminal configured to provide a fourth logic signal S4. The first OR gate OR1has a first input terminal configured to receive the third logic signal S3, a second input terminal configured to receive the fourth logic signal S4, and an output terminal configured to provide the first control signal CTRL1. The third AND gate AND3has a first input terminal configured to receive the third control signal CTRL3, a second input terminal configured to receive the first logic signal PGF, and an output terminal configured to provide a fifth logic signal S5. The fourth AND gate AND4has a first input terminal configured to receive the fifth logic signal S5and a second input terminal configured to receive the indicating signal PGS, and an output terminal configured to provide a sixth logic signal S6. The third OR gate OR3has a first input terminal configured to receive the sixth logic signal S6, a second input terminal configured to receive an inverted signal of the internal data DINT, and a transmitting terminal configured to provide the second control signal CTRL2.

In the embodiment ofFIG.8, when there is an off-chip resistor coupled to the multi-function pin MUL, like the regulating resistor REX inFIGS.6A and6B, the off-chip resistor indicating signal PUP is logic low to turn off the first switch S1.

Persons of ordinary skill in the art should know that the digital circuit83ais an example for illustration. Any digital control circuits which could achieve the above control functions are applicable to the present invention.

In the present invention, the multi-function pin MUL of the power chip is configured as the data communication pin and meanwhile provides the indicating signal PGS, which minimizes the size and cost of the power chip.

While specific embodiments of the present invention have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Since the invention can be practiced in various forms without distracting the spirit or the substance of the invention, it should be understood that the above embodiments are not confined to any aforementioned specific detail, but should be explanatory broadly within the spirit and scope limited by the appended claims. Thus, all the variations and modification falling into the scope of the claims and their equivalents should be covered by the appended claims.