Patent ID: 12218683

DETAILED DESCRIPTION

Various types of error correcting codes can be used for detecting and correcting errors that may be introduced into data that is being transmitted through a noisy medium (a noisy wireless communication link, for example) and/or is being stored into a memory device (such as, for example, a hard disk drive or a solid-state drive). One example of an error correcting code is referred to as a low-density parity-check code (LDPC). An LDPC decoder can be configured to perform error detection and correction by using log likelihood ratio (LLR) values. Each LLR value provides a statistical indication of a level of certainty or confidence that a detection of a data bit is either a logic 1 or a logic 0.

In the description provided herein, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. Hence, the figures and description are not intended to be restrictive. Certain words and phrases are used herein based on convenience and such words and phrases should be interpreted in various forms and equivalencies by persons of ordinary skill in the art. For example, the word “bit” as used herein represents a binary value (either a “1” or a “0”) that can be stored in a memory. Furthermore, it should be understood that each of words such as “implementation,” “scenario,” “approach,” “application,” “case” and “configuration” as used herein is an abbreviated version of the phrase “In an example (“implementation,” “scenario,” “approach,” “application,” “case,” “configuration” etc.) in accordance with disclosure.” It must also be understood that the word “example” as used herein is intended to be non-exclusionary and non-limiting in nature.

FIG.1illustrates a block diagram of an example error correction system100that includes a bit error tracker155in accordance with an embodiment of the disclosure. The example error correction system100includes an LDPC encoder105that encodes input data in an encoded format (e.g., by adding parity bits) that is suitable for storing in a storage system115. Encoding the input data enables the use of error correction procedures for correcting bit errors that may occur during operations such as, for example, writing the data into the storage system115, or reading the stored data from the storage system115. Storage system115can be, for example, solid-state drives (SSDs), storage cards, and Universal Standard Bus (USB) drives, and can be implemented using non-volatile memory such as flash memory (e.g., NAND flash).

In an example implementation, the data and parity bits produced by the LDPC encoder105can be stored in memory cells of a multi-level flash memory that can be a part of the storage system115. The contents of any individual cell can be read out by applying a gate voltage having various voltage amplitudes that enable the contents of the cell to be read out. An array of multi-level flash memories can be configured to include multiple memory blocks. Each memory block may include multiple pages. For example, a set of memory cells having a word line that is coupled in common to each of the set of memory cells can be configured as a page that can be read and written (or programmed) concurrently.

More specifically, a multi-level flash memory can be a type of NAND flash memory containing an array of cells each of which can be used to store multiple bits of data. For example, a tri-level cell (TLC) flash memory can store three bits of data per cell. Each of the three bits of data can be either in a programmed state (logic 0) or in an erased stated (logic 1), thereby allowing for storage of any of eight possible logic bit combinations in each cell. Each cell can be configured to store three bits of data by placing one of eight charge levels in a charge trap layer of a cell. Thus, for example, a cell may be configured to store a 000 logic bit combination by placing a first amount of charge in the cell, a cell may be configured to store a 110 logic bit combination by placing a second amount of charge in the cell, and so on. More generally, a N-bit multi-level cell can have 2 N states or charge levels representing the different possible combinations of N bits.

Data bit errors may be introduced during storage of the data bits in the multi-level flash memory and/or when writing/reading the data bits in/out of the multi-level flash memory. The data bit errors may be introduced because of various factors such as, for example, hardware defects in the flash memory, aging of the flash memory, interference by adjacent pages, software bugs, and/or read/write timing issues, etc.

The detector125is configured to read the data bits stored in the storage system115. In an example implementation, the detector125includes a hard output detector and a soft output detector. The hard output detector carries out detection based on voltage thresholds that provide an indication whether a detected bit is either a one or a zero. The input data bits provided to detector125from the storage system115can have bit errors. Consequently, the output produced by the hard detector can contain hard errors where one or more bits have been detected inaccurately (a “1” read as a “0” or vice-versa). The soft detector operates upon the input data and produces an output that is based on statistical probabilities indicating a confidence level whether a detected bit is a one or a zero. The statistical probabilities may be characterized, for example, based on log likelihood ratio (LLR) values.

The output of the detector125is coupled into the LDPC decoder130. In an example implementation, the LDPC decoder130uses a decoder parity-check matrix150during decoding of the data bits. The decoder parity-check matrix150corresponds to the encoder parity-check matrix110, and vice-versa.

In the illustrated example, the hard detector bits provided by the detector125may be decoded by a hard decoder135. The soft detector bits and the statistical probability information provided by the detector125may be decoded by the soft decoder140by use of LLR values145. In an example implementation, the LLR values145may be stored in the form of a table.

Hard errors can adversely affect the overall performance of the error correction system100. It is desirable to detect and correct these hard error bits. Data errors may be quantified in various ways such as, for example, in the form of a bit error rate (BER). The overall performance of the error correction system100can be characterized by metrics such as, for example, a maximum bit error rate (MBER), a maximum acceptable bit error rate, and/or a residual bit error rate (RBER).

The maximum acceptable BER may be used, for example, to calculate an acceptable signal-to-noise ratio (SNR) of the error correction system100. The residual bit error rate (RBER) provides an indication of a likelihood that a particular bit is erroneous and the error is undetected. In general, the performance of the LDPC decoder130not only depends upon the RBER but also upon the number of hard errors. The number of hard errors, which may be characterized in the form of a hard error percentage, degrades the error correcting capabilities of the LDPC decoder130. More particularly, the performance of the soft decoder140is dependent in large part upon the LLR values145that are used to decode the signals provided to the LDPC decoder130by the detector125. Thus, in accordance with disclosure, a bit error tracker155is used to evaluate the performance of the soft decoder140and adjust the LLR values145to optimize the performance of the soft decoder140. Further details pertaining to the bit error tracker155is provided below.

FIG.2illustrates an example graph200showing degradation of the error correction capability of a soft decoder (such as, for example, the soft decoder140) in the presence of various levels of hard errors. More particularly, graph line220indicates RBER values when no hard errors are present. Graph line215indicates RBER in the presence of 10% hard errors. Graph line210indicates RBER in the presence of 20% hard errors. Graph line205indicates RBER in the presence of 40% hard errors. The bit error tracker155determines adjustment of LLR values145in accordance with the disclosure, based at least in part, on the percentage of hard errors present in data provided to the bit error tracker155by the hard decoder135. This aspect is described below in more detail.

FIG.3illustrates an example distribution diagram300of cell voltages in a TLC flash memory that may be a part of the storage system115. It should be understood that various aspects of the disclosure that are described herein with respect to tri-level cell operations and TLC flash memories are equally applicable to various other types of multi-level cell operations and devices such as, for example, quad-level cell (QLC) memories, penta-level cell (PLC) memories, etc. The example embodiments described herein should therefore be interpreted accordingly for other multi-level operations, flash memories, devices, and applications.

Each cell of the TLC flash memory stores three data bits, thereby allowing storage of any of eight logic combinations. The three data bits in each cell are labeled as most significant bit (MSB), center significant bit (CSB), and least significant bit (LSB). The label PV indicates a programmed state in each cell. PV0corresponds to an erased state and each of the PV1through PV7programmed states corresponds to one of eight logic combinations. The erased state corresponds to111due to the NAND configuration of the TLC flash memory. In this example, the seven programmed states of the TLC flash memory are labeled A, B, C, D, E, F, and G. The seven programmed states can be read by applying a voltage corresponding to the seven read threshold voltages (Vr1through Vr7). Each of the seven read threshold voltages corresponds to a valley between any two adjacent logic transitions. The probability distribution of read voltages for each individual cell is represented as a bell-shaped curve. The seven bell-shaped curves corresponding to the seven programmed states are labeled A, B, C, D, E, F, and G.

In this example, the MSB includes two logic state transitions as the threshold voltage is increased—a first logic state transition (1 to 0 transition) from state B to state C, and a second logic state transition (0 to 1 transition) from state F to state G. The CSB includes three logic state transitions—a first logic state transition (1 to 0 transition) from state A to state B, a second logic state transition (0 to 1 transition) from state C to state D, and a third logic state transition (1 to 0 transition) from state E to state F. The LSB includes two logic state transitions—a first logic state transition (1 to 0 transition) from state Er to state A, and a second logic state transition (0 to 1 transition) from state D to state E.

FIG.4illustrates some features of an example probability distribution diagram400of cell voltages applicable to a soft decoding procedure in accordance with the disclosure. The example probability distribution diagram400illustrates the logic states of the CSB shown inFIG.3(11001100) when the threshold voltage is varied. In this scenario, the CSB is read as a 0 when the threshold voltage of the cell is above the read threshold voltage Vr2and below the read threshold voltage Vr4, and is further read as a 0 when the threshold voltage of the cell is above the read threshold voltage Vr6. The CSB is read as a 1 when the threshold voltage of the cell is below the read threshold voltage Vr2, and when the threshold voltage of the cell is between the read threshold voltage Vr4and the read threshold voltage Vr6.

As described above, the CSB includes three logic state transitions—a first logic state transition (1 to 0 transition) from state A to state B, a second logic state transition (0 to 1 transition) from state C to state D, and a third logic state transition (1 to 0 transition) from state E to state F.

Read threshold voltage Vr2corresponds to the first logic state transition from a 1 state to a 0 state. An idealized read operation would have a step function response at the read threshold voltage Vr2. In practice, there exists an area of uncertainty on either side of the threshold voltage Vr2. The level of uncertainty can be quantified by use of a first bell-shaped curve that represents logic state A, a second bell-shaped curve that represents logic state B, and a set of LLR values that are located on either side of the read threshold voltage (Vr2) corresponding to the valley between the first bell-shaped curve and the second bell-shaped curve.

Read threshold voltage Vr4corresponds to the second logic state transition from a 0 state to a 1 state. In this case, the level of uncertainty can be quantified by use of a third bell-shaped curve that represents logic state C, a fourth bell-shaped curve that represents logic state D, and a set of LLR values that are located on either side of the read threshold voltage Vr4corresponding to the valley between the third bell-shaped curve and the fourth bell-shaped curve.

Read threshold voltage Vr6corresponds to the third logic state transition from a 1 state to a 0 state. In this case, the level of uncertainty can be quantified by use of a fifth bell-shaped curve that represents logic state E, a sixth bell-shaped curve that represents logic state F, and a set of LLR values that are located on either side of the read threshold voltage Vr6corresponding to the valley between the fifth bell-shaped curve and the sixth bell-shaped curve.

In an example implementation in accordance with the disclosure, the read threshold voltage Vr3is designated as a first assist read voltage and the read threshold voltage Vr5is designated as a second assist read voltage, thereby designating three assist read (AR) zones that are referred to herein as AR zone0, AR zone1, and AR zone2. Each AR zone encompasses a region of the threshold voltage containing a logic transition. For example, AR zone0encompasses adjacent threshold voltage distributions indicated by the bell-shaped curves A and B representing the first logic transition from 1 to 0, AR zone1encompasses adjacent threshold voltage distributions indicated by the bell-shaped curves C and D representing the second logic transition from 0 to 1, and AR zone2encompasses adjacent threshold voltage distributions indicated by the bell-shaped curves E and F representing the third logic transition from 1 to 0. The description below with respect to AR zone0is equally applicable to AR zone1and AR zone2and should be understood as such.

The read threshold voltage Vr2in AR zone0can be used for executing hard decisions (determining whether the CSB in a cell is either a 0 or a 1). In some scenarios, when data received by a decoder contains errors, hard decisions carried out by use of the read threshold voltage Vr2can lead to errors (a 1 written into memory that is erroneously read as a 0, or vice-versa). In such scenarios, it is desirable to use a soft decision operation that utilizes multiple reads to read a programmed state of a cell. In the illustrated example, seven read operations (R0through R6) in AR zone0corresponding to various read threshold voltages for reading the contents of the cell can be used. The read operation R0can be referred to as a hard read operation and the remaining six read operations can be referred to as soft read operations. The seven read operations define eight regions in the transition or overlapping area of the bell-shaped curve1and the bell-shaped curve0. Each of these eight regions may be referred to by a bin label.

Bin0corresponds to a first defined region below R5and can be assigned an LLR value of −4. Bin1corresponds to a second defined region between R5and R3and can be assigned an LLR value of −3. Bin2corresponds to a third defined region between R3and R1and can be assigned an LLR value of −2. Bin3corresponds to a fourth defined region between R1and R0(at the read threshold voltage Vr2) and can be assigned an LLR value of −1. Bin4corresponds to a fifth defined region between R0(at the read threshold voltage Vr2) and R2and can be assigned an LLR value of +1. Bin5corresponds to a sixth defined region between R2and R4and can be assigned an LLR value of +2. Bin6corresponds to a seventh defined region between R4and R6and can be assigned an LLR value of +3. Bin7corresponds to an eighth defined region above R6and can be assigned an LLR value of +4.

A negative LLR value indicates the read bit is likely a logic 1, and a positive LLR value indicates the read bit is likely a logic 0. The absolute magnitude of the LLR value indicates the likelihood that a read bit is a logic 1 or a logic 0. The higher the absolute magnitude, the higher the likelihood that a read bit is a logic 1 or a logic 0. Thus, in the case of the TLC flash memory, an LLR value of +4 provides an indication that the likelihood of a read bit being a logic 0 is higher than for an LLR value of +3, for example. Correspondingly, a read bit that is in bin0has a higher likelihood of being a logic 0 than a read bit that is located in bin1. Similarly, an LLR value of −4 provides an indication that the likelihood of a read bit being a logic 1 is higher than when the read bit corresponds to an LLR value of −3, for example. Here, a read bit that is in bin7has a higher likelihood of being a logic 1 than a read bit that is in bin6. Read bits located in bins3and4(LLR values −1 and +1) have the lowest likelihood, and the level of uncertainty whether the bit is a logic 1 or a logic 0 is highest in this area.

In some cases, each of the LLR values can be theoretically determined based on the following equations, and used in the form of preset LLR values, where Pr(r=x|w=0) is the probability of writing a logic 0 to the cell and reading a threshold voltage falling in bin x, and Pr(r=x|w=1) is the probability of writing a logic 1 to the cell and reading a threshold voltage falling in bin x.

LLR⁢(bin⁢0)=log⁢P⁢r⁡(r=0⁢❘"\[LeftBracketingBar]"w=0)P⁢r⁡(r=0⁢❘"\[LeftBracketingBar]"w=1)LLR⁢(bin⁢1)=log⁢P⁢r⁡(r=1⁢❘"\[LeftBracketingBar]"w=0)P⁢r⁡(r=1⁢❘"\[LeftBracketingBar]"w=1)…LLR⁢(bin⁢7)=log⁢P⁢r⁡(r=7⁢❘"\[LeftBracketingBar]"w=0)P⁢r⁡(r=7⁢❘"\[LeftBracketingBar]"w=1)

However, using preset LLR values may lead to an inflexible operating structure for a decoder. The inflexible operating structure may fail to take into consideration various factors causing erroneous reads in a flash memory. An example factor that may lead to a read error may be attributed to changes over time (e.g., aging) in cell characteristics in the flash memory. Another example factor that may lead to a read error may be attributed to shifts in the threshold voltages as a result of various changes in operating conditions, interference from other cells, and/or in circuitry, associated with the flash memory.

Accordingly, it is desirable to provide for a solution in accordance with the disclosure that allows for flexible reconfiguration of a soft decoder (such as, for example, the soft decoder140shown inFIG.1). The flexible reconfiguration can include modifying one or more of the LLR values such as, for example, one or more of the LLR values145that can be stored in a table in the LDPC decoder130.

FIG.5illustrates an enlarged view of some features of an example probability distribution diagram500of cell voltages applicable to a soft decoding procedure in accordance with the disclosure. The example probability distribution diagram500illustrates adjacent logic states corresponding to a 1 and a 0. The seven read operations described above (hard read operation R0and soft read operations R1through R6) are illustrated along with the respective bins. A hard error can be defined as an event that may occur during a soft read as a result of a cell voltage falling outside a soft read range515that is centered around an optimal read threshold. In the case of a flash memory having a single level cell (SLC) structure, an example soft read range can span ±400 mV around R0. An example soft read range for an MLC cell can span ±400 mV around R0. An example soft read range for a TLC cell can span ±250 mV around R0.

The example probability distribution diagram500illustrates a first region505and a second region510, each having an overlap between the two bell-shaped curves of the two logic states. In an example scenario, a hard error can occur in the first region505and/or in the second region510. For example, a cell threshold voltage falling in bin0with a LLR value of −4 should have a high likelihood of being a logic 1. However, a hard error may occur in region505if the read data is decoded to be a logic 0 instead of a logic 1. Similarly, a cell threshold voltage falling in bin7with a LLR value of +4 should have a high likelihood of being a logic 0. However, a hard error may occur in region510if the read data is decoded to be a logic 1 instead of a logic 0.

FIG.6illustrates an example implementation of counters600that can be a part of the bit error tracker155in accordance with the disclosure. In an example operation, the LDPC decoder130performs read operations on the multibit memory cells of a TLC flash memory in the manner described above. The read operations include assist read operations to determine an AR zone for each bit of data stored in the TLC flash memory. The read operations can further include soft reads to determine a bin within each AR zone for each bit of data.

Errors may be present at the input of the LDPC decoder130for various reasons including due to changes in the characteristics of the flash over time, interference from neighboring cells, etc. The bit error tracker may be configured in accordance with the disclosure, to track and identify such errors, identify the LLRs associated with the errors, collect statistics based on the identified LLRs, and adjust one or more LLR values based on evaluating the statistics. Evaluating the statistics can include, for example, computing a hard error percentage for each AR zone and adjusting the LLR values based on the hard error percentage. In an example embodiment, the bit error tracker performs such operations by using a set of counters for each AR zone.

FIG.6illustrates the counters arranged in three groups corresponding to the three AR zones—AR zone0, AR zone1, and AR zone2(described above and illustrated inFIG.4). A first set of counters in each group is configured to monitor bit values decoded to a logic 0 from each bin ranging from bin0to bin7, and a second set of counters is configured to monitor bit values decoded to a logic 1 from each bin (ranging from bin0to bin7). More particularly, a first group605corresponding to AR zone0has a first set of counters620and a second set of counters625. A second group610corresponding to AR zone1has a first set of counters630and a second set of counters635. A third group615corresponding to AR zone2has a first set of counters640and a second set of counters645.

Some of the description below is directed primarily to the first group605. However, it should be understood that the description, such as, for example, structural and functional aspects of each of the set of counters, is equally applicable to the other two groups and should be understood in context.

Each set of counters includes eight counters, each of which is labeled in a C(B→Y, AR) format where “C” is an abbreviation for counter, “B” is a bin label (ranging from bin0to bin7), “Y” is the decoded logic state (1 or 0) of the bit being read, and “AR” indicates the associated AR zone. The output of each counter provides a count of the number of read bits belonging to each bin B in each AR zone that have decoded to the Y logic state.

For example, the label C(0→0,0) represents a first counter that counts reads in bin0of AR zone0that decoded to a logic 0, the label C(1→0,0) represents a second counter that counts reads in bin1of AR zone0that decoded to a logic 0, the label C(2→0,0) represents a third counter that counts reads in bin2of AR zone0that decoded to a logic 0, and so on. The label C(0→1,0) represents a first counter that counts reads in bin0of AR zone0that decoded to a logic 1, the label C(1→1,0) represents a second counter that counts reads in bin1of AR zone0that decoded to a logic 1, the label C(2→1,0) represents a third counter that counts reads in bin2of AR zone0that decoded to a logic 1, and so on.

A similar format is used for each of the counters in each of AR zone1and AR zone2. Thus, for example, the label C(0→0,1) represents a first counter that counts reads in bin0of AR zone1that decoded to a logic 0, the label C(1→0,1) represents a second counter that counts reads in bin1of AR zone1that decoded to a logic 1, the label C(2→0,1) represents a third counter that counts reads in bin2of AR zone1that decoded to a logic 0, and so on. The label C(0→1,1) represents a first counter that counts reads in bin0of AR zone1that decoded to a logic 1, the label C(1→1,1) represents a second counter that counts reads in bin1of AR zone1that decoded to a logic 1, the label C(2→1,1) represents a third counter that counts reads in bin2of AR zone1that decoded to a logic 1, and so on.

An example set of data bits being read can include, for example, seven CSB bits read from seven cells of a word line in the TLC flash memory. The result of the soft reads may be (0,0), (6,1), (7,1), (2,1), (5,1), (2,2), (3,0), in which the two tuple values represent the bin and AR zone (bin, AR) corresponding to each CSB bit being read. Referring back toFIG.4, the soft read (0,0) corresponds to bin0of AR zone0, and thus has a LLR value of −4 indicating the bit has a very high likelihood of being a logic 1; the soft read (6,1) corresponds to bin6of AR zone1, and thus has a LLR value of +3 indicating the bit has a high likelihood of being a logic 0; the soft read (7,1) corresponds to bin7of AR zone1, and thus has a LLR value of +4 indicating the bit has a very high likelihood of being a logic 0; the soft read (2,1) corresponds to bin2of AR zone1, and thus has a LLR value of −2 indicating the bit has a medium likelihood of being a logic 1; the soft read (5,1) corresponds to bin5of AR zone1, and thus has a LLR value of +2 indicating the bit has a medium likelihood of being a logic 0; the soft read (2,2) corresponds to bin2of AR zone2, and thus has a LLR value of −2 indicating the bit has a medium likelihood of being a logic 1; and the soft read (3,0) corresponds to bin3of AR zone0, and thus has a LLR value of −1 indicating the bit has a slight likelihood of being a logic 1. By way of example, the LDPC decoder130may perform error correction decoding on the seven read bits, which may yield the decoded bit values of (1, 0, 0, 0, 0, 1, 1) corresponding to the soft reads (0,0), (6,1), (7,1), (2,1), (5,1), (2,2), (3,0). It should be noted that in this example, soft read (2,1) decoded to a logic 0 even though the LLR indicates a medium likelihood of being a logic 1. This may indicate that a bit error may have occurred for this cell.

Consequently, counters600of the bit error tracker can be incremented as follows. For soft read (0,0) that decoded to a bit value of 1, the counter value of C(0→1,0) is incremented, as indicated by reference number601. For soft read (6,1) that decoded to a bit value of 0, the counter value of C(6→0,1) is incremented, as indicated by reference number606. For soft read (7,1) that decoded to a bit value of 0, the counter value of C(7→0,1) is incremented, as indicated by reference number607. For soft read (2, 1) that decoded to a bit value of 0, the counter value of C(2→0,1) is incremented, as indicated by reference number603. For soft read (5,1) that decoded to a bit value of 0, the counter value of C(5→0,1) is incremented, as indicated by reference number604. For soft read (2,2) that decoded to a bit value of 1, the counter value of C(2→1,2) is incremented, as indicated by reference number608. For soft read (3,0) that decoded to a bit value of 1, the counter value of C(3→1,0) is incremented, as indicated by reference number602.

Each bit of the multi-level cell (e.g., MSB, CSB, LSB) can have its own set of counters. Furthermore, each word line or page in the memory can maintain separate counters to count decoded bit values for each bin of each AR zone. In some implementations, instead of maintaining a set of counters for each word line, adjacent word lines can be grouped together into word line groups, and one set of counters can be used for all the word lines in each word line group. The counters can be allowed to increment for a predetermined amount of time, predetermine number of program/erase cycles, and/or for a predetermined number of reads. Thereafter, count values can be evaluated to determine if the LLR values should be adjusted to reflect the characteristics of each word line or word line group. Hence, each word line or word line group can have its own LLR table. The count values can be evaluated periodically or at certain points in time (intermittently, randomly, or on an as-need basis) during the lifetime of the memory to update the LLR values.

In some implementations, the counter values can be evaluated by the bit error tracker155. The bit error tracker155can be implemented, for example, using firmware and/or software executable by a processor of a memory controller. The evaluation is directed at obtaining statistical information associated with performance characteristics of the LLR values145used by the soft decoder140in the LDPC decoder130. The evaluation may be used to identify various conditions of the word lines or word line groups of the memory. For examples, the statistics collected by the counters can determine the number of errors that have been corrected as well as hard errors that have occurred. The number of read errors of logic 1 that have been corrected to logic 0 can be determined, for example, by the count values in counters C(0→0, AR), C(1→0, AR), C(2→0, AR), and C(3→0, AR). The number of read errors of logic 0 that have been corrected to logic 1 can be determined, for example, by the count values in counters C(4→1, AR), C(5→1, AR), C(6→1, AR), and C(7→1, AR). Of these read errors, the number of hard errors can be determined, for example, by the count values in counters C(0→0, AR) and C(7→1, AR).

The errors can be indicative of conditions that can adversely affect the performance of the memory, such as, for example, resulting in a degradation of data retention, a corruption of data stored in one or more cells, a hardware failure of one or more cells, a change or shift in the threshold voltage distributions, etc. The evaluation can identify one or more LLR values that can be modified to improve the error decoding. Modification of the LLR values may be carried out by modifying the LLR values for one or more of the threshold voltage distribution bins described above. In an example implementation, that is described below in more detail, the count values can be used to remap one or more bin labels to different LLR values.

In an example process, evaluation of the counters illustrated inFIG.6may be carried out by executing the example steps shown below:Hard_err_cnt=0//total hard error countHard_err_cnt_per_ar_0 to 1=[0, . . . 0]//hard error count per AR pattern. Hard_err_cnt_per_ar_1 to 0=[0, . . . 0]//hard error count per AR patternHard_err_cnt_per_ar=[0, . . . 0]//hard error count per AR patternTotal_err_cnt=0.Total_err_cnt_per_ar_0 to 1=[0, . . . 0]Total_err_cnt_per_ar_1 to 1=[0, . . . 0]Total_err_cnt_per_ar=[0, . . . 0]Hard_err_percent=0Hard_err_percent_per_ar_0 to 1=[0, . . . 0]Hard_err_percent_per_ar_1 to 0=[0, . . . 0]Hard_err_percent_per_ar=[0, . . . 0]For ar in AR:Hard_err_cnt_per_ar_0 to 1[ar]=C(7→1, ar)Hard_err_cnt_per_ar_1 to 0[ar]=C(0→0, ar)Hard_err_cnt_per_ar[ar]=Hard_err_cnt_per_ar_0 to 1[ar]+Hard_err_cnt_per_ar_1 to 0[ar]Hard_err_cnt=Hard_err_cnt+Hard_err_cnt_per_ar[ar]For bin_label in [0,1,2,3]Total_err_cnt_per_ar_1 to 0 [ar]=Total_err_cnt_per_ar_1 to 0[ar]+C(bin_label→0, ar)For bin label in [4,5,6,7]Total_err_cnt_per_ar_0 to 1[ar]=Total_err_cnt_per_ar_0 to 1[ar]+C(bin_label→1, ar)Total_err_cnt_per_ar[ar]=Total_err_cnt_per_ar_1 to 0[ar]+Total_err_cnt_per_ar_0 to 1[ar]Total_err_cnt=Total_err_cnt+Total_err_cnt_per_ar[ar]For ar in AR:Hard_err_percent_per_ar[ar]=hard_err_cnt_per_ar[ar]/total_err_cnt_per_ar[ar]Hard_err_percent_per_ar_0 to 1[ar]=hard_err_cnt_per_ar_0 to 1[ar]/total_err_cnt_per_ar_0 to 1[ar]Hard_err_percent_per_ar_1 to 0[ar]=hard_err_cnt_per_ar_1 to 0[ar]/total_err_cnt_per_ar_1 to 0[ar]Hard_err_percent=hard_err_cnt/total_err_cnt

Based on executing the example steps shown above, a hard error percentage for each AR zone can be determined by evaluating the various counter output values of the various counters. The hard error percentage per AR zone can then be used to modify a mapping of LLR values to bin values such as, for example, modifying one or more of the LLR values145illustrated inFIG.1. In an example scenario, evaluating the various counter output values of the counters in AR zone0involves identifying whether a hard error percentage of decoding errors where a read of logic 0 was decoded to a logic 1 exceeds a threshold value α0→1. The threshold value α0→1may be identified in various ways such as, for example, based on a priori data analysis and/or a system performance requirement (low MBER and/or low RBER, for example), or other heuristics. If the hard error percentage exceeds the threshold value, LLR values used in future reads may be remapped in a lookup table of LLR values145. For example, bin7that is currently mapped to +4 LLR value may be remapped to a lower LLR value such as, for example, +3 or +2.

In another example scenario, where the hard error percentage of decoding errors where a read of logic 1 was decoded to a logic 0 exceeds a threshold value α1→0, LLR values used in future reads may be remapped in a lookup table of LLR values145. For example, bin0that is currently mapped to −4 LLR value may be remapped to a higher LLR value such as, for example, −3 or −2.

In another example embodiment, the LLR values145for future use may be determined for each AR zone by use of the example formulae shown below for AR zone0. Similar formulae can be used for other AR zones.

LLR⁢(bin⁢0,AR=0)=log⁢C⁡(0->0,0)C⁡(0->1,0)LLR⁢(bin⁢1,AR=0)=log⁢C⁡(1->0,0)C⁡(1->1,0)…LLR⁢(bin⁢7,AR=0)=log⁢C⁡(7->0,0)C⁡(7->1,0)

It should be noted that adjacent word lines in a TLC flash memory having a NAND architecture usually have similar characteristics and can share a LLR table. Consequently, in an example implementation, computation complexity may be reduced by performing one set of calculations for a group of word lines (e.g., adjacent word lines) instead of performing a set of calculations for each individual word line in the group. The word lines in each block of memory cells can be grouped into word line groups. Bit error statistics may then be collected on a word line basis in a format such as C(B→Y, AR, WL), where the label WL indicates a word line. In this case, the format C(B→Y, AR, WL) is a variation of the C(B→Y, AR) format described above. The collected bit errors from all counters associated with the word lines in a group may be combined C(B→Y, AR)=ΣWLC(B→Y, AR, WL) and evaluated in the manner described above with reference to the counters illustrated inFIG.6. The evaluation can be used to identify LLR values to modify, and the modified LLR values (e.g., in a LLR table) can be applied to all the word lines in the word line group.

FIG.7illustrates a simplified flow chart700of an example process for LLR adjustment in accordance with the disclosure. The process can include, at step705, performing assist reads (AR) of multibit memory cells of a memory to determine an AR zone for each bit of data stored in the multibit memory cells. In an example embodiment, the memory can be a NAND flash memory that can be a component of a storage system, such as the storage system115described above. At step710, soft reads of the multibit memory cells may be performed to determine a bin within the AR zone for each bit of the data stored in the memory cells. Each bin is associated with a log likelihood ratio (LLR) value.

At step715, error correction decoding can be performed on the data stored in the multibit memory cells. At step720, statistics on the decoded data for each bin in each AR zone may be collected. In an example implementation, collecting statistics can include maintaining a counter for each bin in each AR zone that decoded to a bit value of 0, and maintaining a counter for each bin in each AR zone that decoded to a bit value of 1. This aspect is described above with reference toFIG.6.

At step725, a hard error percentage may be computed for each AR zone based on the collected statistics. The hard error percentage can be, for example, a hard error percentage of reading a bit value of 0 that decoded to a bit value of 1 (denoted as “0 to 1”), which can be computed as the ratio of the hard error count of 0 to 1 for a particular AR zone to the total number of errors of 0 to 1 for the AR zone. The hard error count of 0 to 1 is the count value of counter C(7→1, ar), and the total number of errors of 0 to 1 is the sum of the count values of counters C(4→1, ar), counter C(5→1, ar), counter C(6→1, ar), and counter C(7→1, ar). As another example, the hard error percentage can be a hard error percentage of reading a bit value of 1 that decoded to a bit value of 0 (denoted as “1 to 0”), which can be computed as the ratio of the hard error count of 1 to 0 for a particular AR zone to the total number of errors of 1 to 0 for the AR zone. The hard error count of 1 to 0 is the count value of counter C(0→0, ar), and the total number of errors of 1 to 0 is the sum of the count values of counters C(0→0, ar), counter C(1→0, ar), counter C(2→0, ar), and counter C(3→0, ar).

At step730, one or more LLR values for the AR zone can be adjusted based on the hard error percentage. In an example implementation, adjusting the one or more LLR values can include comparing the hard error percentage of 0 to 1 with a threshold, determining that the hard error percentage of 0 to 1 is above the threshold, and decreasing the LLR value associated with the bin having a largest likelihood of being a bit value of 0 (e.g., decrease the LLR value of bin7such as decrease LLR=4 to LLR=3). As another example, adjusting the one or more LLR values can include comparing the hard error percentage of 1 to 0 with a threshold, determining that the hard error percentage of 1 to 0 is above the threshold, and increasing the LLR value associated with the bin having a largest likelihood of being a bit value of 1 (e.g., increase the LLR value of bin0such as increase LLR=−4 to LLR=−3). The adjusted LLR values can be updated in the LLR table for the word line or word line group, and subsequent soft decoding for the word line or word line group can use the adjusted LLR values.

FIG.8shows a simplified block diagram illustrating a solid-state storage system800, which can be an example of an electronic device utilizing the LLR adjustment techniques described herein. As shown, solid-state storage system800can include a solid-state storage device850(e.g., implemented using flash memory) and a storage controller860. Storage controller860, also referred to as a memory controller, is one example of a system that can perform the processes and techniques described herein. In some embodiments, storage controller860can be implemented on a semiconductor device, such as an application-specific integrated circuit (ASIC) or field programmable gate array (FPGA). Some of the functions can also be implemented in firmware or software. Solid-state storage system800is an example of a solid-state drive (SSD).

Controller804can include one or more processors806and memories808(non-transitory computer readable medium) for performing the control functions described herein. Storage controller860can also include lookup tables810, which can include, for example, LLR tables, etc. Registers814can be used to store data for control functions and configurations for storage controller860.

Controller804can be coupled to solid-state storage850through a storage interface802. Error-correction decoder812(e.g., an LDPC decoder) can perform error-correction decoding on the read data and send the corrected data to controller804. Controller804can update the bit error tracker counters, evaluate the count values, and update the LLR tables according to the techniques disclosed herein.

FIG.9illustrates a computer system900usable for implementing one or more embodiments of the present disclosure.FIG.9is merely an example and does not limit the scope of the disclosure as recited in the claims. As shown inFIG.9, the computer system900may include a display monitor910, a computer905, a user output device945, a user input device940, a communications interface935, and may further include other computer hardware or accessories. In an example implementation, the computer system900, or select components of the computer system900, can be used to implement the LLR99adjustment techniques disclosed herein. For example, non-volatile memory925may include a flash memory whose LLR values are adjusted according to the techniques disclosed herein.

The computer905may include one or more processors such as, for example, the processor915that is configured to communicate with a number of peripheral devices via a bus subsystem930. Some example peripheral devices may include the user output device945, the user input device940, and the communications interface935. The computer905may further include a storage subsystem that includes a random-access memory (RAM)920and a disk drive925or other forms of non-volatile memory.

The user input device940can be any of various types of devices and mechanisms for inputting information to the computer905such as, for example, a keyboard, a keypad, a touch screen incorporated into the display, and audio input devices (such as voice recognition systems, microphones, and other types of audio input devices). In various embodiments, the user input device940is typically embodied as a computer mouse, a trackball, a track pad, a joystick, a wireless remote, a drawing tablet, a voice command system, an eye tracking system, and the like. The user input device940typically allows a user to select objects, icons, text and the like that appear on the monitor910via a command such as a click of a button or the like.

The user output device945can be any of various types of devices and mechanisms for outputting information from the computer905such as, for example, a display (e.g., the display monitor910), non-visual displays such as audio output devices, etc.

The communications interface935provides an interface to a communication network. The communications interface935may serve as an interface for receiving data from and transmitting data to other systems. Embodiments of the communications interface935typically include an Ethernet card, a modem (telephone, satellite, cable, ISDN), (asynchronous) digital subscriber line (DSL) unit, FireWire interface, USB interface, and the like. In an example implementation, the communications interface935may be coupled to a computer network, to a FireWire bus, or the like. In other example implementations, the communications interfaces935may be physically integrated on the motherboard of the computer905, and may include a software program, such as soft DSL, or the like.

In various embodiments, the computer system900may also include software that enables communications over a network such as the HTTP, TCP/IP, RTP/RTSP protocols, and the like. In alternative embodiments of the present disclosure, other communications software and transfer protocols may also be used, for example IPX, UDP or the like.

The RAM920and the disk drive925are examples of non-transitory computer-readable media configured to store computer-executable instructions for performing operations associated with various embodiments of the present disclosure, including executable computer code, human readable code, or the like. Other types of computer-readable storage media include floppy disks, removable hard disks, optical storage media such as CD-ROMS, DVDs and bar codes, semiconductor memories such as flash memories, non-transitory read-only-memories (ROMS), battery-backed volatile memories, networked storage devices, and the like. The RAM920and the disk drive925may be configured to store the basic programming and data constructs that provide the functionality of the present disclosure.

Software code modules and instructions that provide the functionality of the present disclosure may be stored in the RAM920and the disk drive925. These software modules may be executed by the processor915. The RAM920and the disk drive925may also provide a repository for storing data used in accordance with the present disclosure.

The RAM920and the disk drive925may include a number of memories such as a main random-access memory (RAM) for storage of instructions and data during program execution and a read-only memory (ROM) in which fixed non-transitory instructions are stored. The RAM920and the disk drive925may include a file storage subsystem providing persistent (non-volatile) storage for program and data files. The RAM920and the disk drive925may also include removable storage systems, such as removable flash memory.

The bus subsystem930provides a mechanism for letting the various components and subsystems of the computer905communicate with each other as intended. Although the bus subsystem930is shown schematically as a single bus, alternative embodiments of the bus subsystem may utilize multiple busses.

It will be readily apparent to one of ordinary skill in the art that many other hardware and software configurations are suitable for use with the present disclosure. For example, the computer905may be a desktop, portable, rack-mounted, or tablet configuration. Additionally, the computer905may be a series of networked computers. In still other embodiments, the techniques described above may be implemented upon a chip or an auxiliary processing board.

Various embodiments of the present disclosure can be implemented in the form of logic in software or hardware or a combination of both. The logic may be stored in a computer-readable or machine-readable non-transitory storage medium as a set of instructions adapted to direct a processor of a computer system to perform a set of steps disclosed in embodiments of the present disclosure. The logic may form part of a computer program product adapted to direct an information-processing device to perform a set of steps disclosed in embodiments of the present disclosure. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate other ways and/or methods to implement the present disclosure.

The data structures and code described herein may be partially or fully stored on a computer-readable storage medium and/or a hardware module and/or hardware apparatus. A computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, and magnetic and optical storage devices, such as disk drives, magnetic tape, CDs, DVDs, or other media, now known or later developed, that are capable of storing code and/or data. Hardware modules or apparatuses described herein include, but are not limited to, ASICs, FPGAs, dedicated or shared processors, and/or other hardware modules or apparatuses now known or later developed.

The methods and processes described herein may be partially or fully embodied as code and/or data stored in a computer-readable storage medium or device, so that when a computer system reads and executes the code and/or data, the computer system performs the associated methods and processes. The methods and processes may also be partially or fully embodied in hardware modules or apparatuses, so that when the hardware modules or apparatuses are activated, they perform the associated methods and processes. The methods and processes disclosed herein may be embodied using a combination of code, data, and hardware modules or apparatuses.

The embodiments disclosed herein are not to be limited in scope by the specific embodiments described herein. Various modifications of the embodiments of the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Further, although some of the embodiments of the present disclosure have been described in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that the disclosure's usefulness is not limited thereto and that the embodiments of the present disclosure can be beneficially implemented in any number of environments for any number of purposes.