Patent ID: 12242320

DETAILED DESCRIPTION

The following illustrative embodiments are provided to illustrate the disclosure of the present disclosure, these and other advantages and effects can be apparent to those in the art after reading this specification.

The present disclosure provides a power management circuit and system thereof applicable to power management and supply for a 2D accelerator chip (comprising a plurality of computing units) so as to effectively supply power to the 2D computing units and greatly reduce the number of connection interfaces coupled to the 2D computing units, thereby improving the power and data transmission performance.

FIG.1is a schematic diagram of a power management circuit and system thereof according to an embodiment of the present disclosure. Referring toFIG.1, the power management circuit and system thereof at least have, but not limited to, M×N computing units10, a main power supply unit12(also referred to as a first power supply unit), an I/O power supply unit14(also referred to as a second power supply unit), N−1 connection interfaces16and a processor18.

Referring toFIG.1, in an embodiment, the M×N computing units10have M columns and N rows of computing units (the present disclosure is not limited to as such). M and N are natural numbers greater than 1. The main power supply unit12is coupled to and supplies power to the computing units of the Nth row of the M×N computing units10(i.e., (1, N) to (M, N) computing units). The computing units of the Nth row are coupled to and supply power to the computing units of the (N−1)th row (i.e., (1, N−1) to (M, N−1) computing units), respectively, and so on correspondingly to computing units of subsequent rows until the computing units of the 2nd row (i.e., (1, 2) to (M, 2) computing units) are coupled to and supply power to the computing units of the 1st row (i.e., (1, 1) to (M, 1) computing units), respectively. The I/O power supply unit14is coupled to and supplies current to the M×N computing units10, and the N−1 connection interfaces16are coupled to corresponding computing units of the 1st column of the M×N computing units, respectively. In addition, the processor18is coupled to the N−1 connection interfaces16. Therein, the corresponding computing units are computing units of the Nth to 2nd rows of the 1st column (i.e., (1, N) to (1, 2) computing units).

Referring toFIG.1, in an embodiment, the processor18is coupled to the N−1 connection interfaces16through N−1 I/O terminals of a plurality of I/O terminals (i.e., the N−1 I/O terminals of the plurality of I/O terminals are coupled to the N−1 connection interfaces16, respectively), and another I/O terminal of the plurality of I/O terminals of the processor18is directly coupled to the computing unit of the 1st column and the 1st row (i.e., (1, 1) computing unit).

Further, in an embodiment, when any computing unit of the M×N computing units10needs I/O transmission, the I/O power supply unit14only supplies current (about 50 mA or less) to said any computing unit of the M×N computing units.

Furthermore, in another embodiment, one end of each of the computing units of the 1st row (i.e., (1, 1) to (M, 1) computing units) is coupled to ground.

FIG.2is a schematic diagram of a power management circuit and system thereof according to another embodiment of the present disclosure. Referring toFIG.2, the power management circuit and system thereof at least have, but not limited to, M×N computing units20, a main power supply unit22(also referred to as a first power supply unit), an I/O power supply unit24(also referred to as a second power supply unit), N−1 connection interfaces26and a processor28.

Referring toFIG.2, in an embodiment, the M×N computing units20have M columns and N rows of computing units (the present disclosure is not limited to as such). M and N are natural numbers greater than 1. The main power supply unit22is coupled to and supplies power to the computing units of the Nth row of the M×N computing units20(i.e., (1, N) to (M, N) computing units). The computing units of the Nth row are coupled to and supply power to the computing units of the (N−1)th row (i.e., (1, N−1) to (M, N−1) computing units), respectively, and so on correspondingly to computing units of subsequent rows until the computing units of the 2nd row (i.e., (1, 2) to (M, 2) computing units) are coupled to and supply power to the computing units of the 1st row (i.e., (1, 1) to (M, 1) computing units), respectively. The I/O power supply unit24is coupled to and supplies power to the M×N computing units20, and the N−1 connection interfaces26are coupled to corresponding computing units of the 1st column of the M×N computing units, respectively. In addition, the processor28is coupled to the N−1 connection interfaces26. Therein, the corresponding computing units are computing units of the Nth to 2nd rows of the 1st column (i.e., (1, N) to (1, 2) computing units).

Referring toFIG.2, different from the embodiment ofFIG.1, the processor28is coupled to the N−1 connection interfaces26and the computing unit of the 1st column and the 1st row (i.e., (1, 1) computing unit) through a single I/O terminal.

Further, in an embodiment, when any computing unit of the M×N computing units20needs I/O transmission, the I/O power supply unit24only supplies current (about 50 mA or less) to said any computing unit of the M×N computing units.

Furthermore, in an embodiment, one end of each of the computing units of the 1st row (i.e., (1, 1) to (M, 1) computing units) is coupled to ground.

FIG.3is a schematic circuit diagram of each of the connection interfaces of the power management circuit and system thereof according to an embodiment of the present disclosure. Each of the connection interfaces16,26has a unidirectional circuit162,262for transmission from the processor to the corresponding computing unit and a unidirectional circuit164,264for transmission from the corresponding computing unit to the processor. In an embodiment, reference input voltage Vref ofFIG.3is an intermediate value of an input voltage range. In another embodiment, Vx and Vy ofFIG.3have different voltage levels in different rows. In yet another embodiment, GND ofFIG.3refers to system ground.

FIG.4is a schematic circuit diagram of each of the connection interfaces according to another embodiment of the present disclosure. Each of the connection interfaces16,26has a bidirectional circuit166,266for transmission between the processor and the corresponding computing unit. In an embodiment, reference input voltage Vref ofFIG.4is an intermediate value of an input voltage range. In another embodiment, Vx, Vy and Vz ofFIG.4have different voltage levels in different rows. In yet another embodiment, GND ofFIG.4refers to system ground, while GNDy ofFIG.4refers to row ground. That is, different rows have different ground levels.

Referring toFIG.5A, in an embodiment, the main power supply unit12,22has a single power source coupled to and supplying power to the computing units of the 1st to Mth columns of the Nth row (i.e., (1, N) to (M, N) computing units).

Referring toFIG.5B, in another embodiment, the main power supply unit12,22has M power sources coupled to and supplying power to the computing units of the 1st to Mth columns of the Nth row (i.e., (1, N) to (M, N) computing units), respectively.

FIG.6is a schematic diagram of the I/O power supply unit14,24(also referred as the second power supply unit) of the power management circuit and system thereof according to the present disclosure. The I/O power supply unit14,24includes N direct current-direct current (DC-DC) converters142,242or N low dropout voltage regulators142,242that are coupled to and supply power to the computing units of the Nth to 1st rows, respectively. Further, the I/O power supply unit can have a power source144,244coupled to the N DC-DC converters or N low dropout voltage regulators142,242.

According to the above-described embodiments of the present disclosure, the power management circuit and system thereof of the present disclosure can effectively solve the following problems: 1. the conventional high-power power supply units cannot provide current required by a large number of accelerator chips; 2. the conventional accelerator chips have a 1D structure, power transmission and data transmission between the computing units are in the same direction, when one of the computing units is burned or does not function, power and data transmission of the overall structure will fail; and 3. the conventional overall structure requires a large number of connection interfaces, thus leading to complicated design and high cost.

Therefore, the power management circuit and system thereof of the present disclosure have the following advantages: 1. the sum of current required by the computing units of M columns is less than the output current of the I/O power supply unit; 2. the sum of voltage required by the computing units of N rows is less than the output voltage of the main power supply unit; 3. data transmission can be performed between the computing units in each row without any connection interface; 4. power transmission can be performed between the computing units of different rows without any connection interface; 5. the power management system only needs N−1 connection interfaces (i.e., the computing units of each row only need one connection interface); and 6. since power transmission is in a vertical direction and data transmission is in a horizontal direction, when any one of the computing units is burned or does not function, the transmission performance of the whole chip will not be affected.

Further, the power management circuit and system thereof of the present disclosure is applicable to accelerator chips using 10 nm or less semiconductor technologies.

The above-described descriptions of the detailed embodiments are to illustrate the preferred implementation according to the present disclosure, and it is not to limit the scope of the present disclosure. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present disclosure defined by the appended claims.