Patent ID: 12237314

DETAILED DESCRIPTION OF THE EMBODIMENTS

While the disclosure is open to various modifications and alternative embodiments, specific embodiments thereof will be described and illustrated by way of example in the accompanying drawings. However, it should be understood that there is no intention to limit the disclosure to the particular embodiments disclosed, and, on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.

Like numbers refer to like elements throughout the drawings. In the accompanying drawings, the sizes of structures may be exaggerated for clarity. Although the terms “first,” “second,” etc. are used herein to describe various elements, these elements should not be limited by these terms. The terms are used only for the purpose of distinguishing one element from another. For example, without departing from the scope of the disclosure, a first element could be termed a second element, and similarly a second element could be also termed a first element. A single form of expression is meant to include multiple elements unless otherwise stated.

It will be understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof. In addition, when a layer, a film, an area, or a plate is referred to as being “on” or “under” another layer, another film, another area, or another plate, it can be “directly” or “indirectly” on the other layer, film, area, plate, or one or more intervening layers may also be present. Further, in the disclosure, when a part of a layer, a film, an area, a plate, and the like is formed on another part, a direction, in which the part is formed, is not limited only to an up direction, and includes a lateral direction or a down direction. On the contrary, it will be understood that when an element such as a layer, film, area, or plate is referred to as being “beneath” another element, it can be directly beneath the other element or intervening elements may also be present.

In the application, when it is described that an element (such as a first element) is “operatively or communicatively coupled with/to,” “electrically connected,” or “connected” to another element (such as a second element), the element can be directly connected to the other element or can be connected to the other element through another element (e.g., a third element). On the contrary, when it is described that an element (e.g., a first element) is “directly connected” or “directly coupled” to another element (e.g., a second element), it means that there is no intermediate element (e.g., a third element) between the element and the other element.

In the specification and the claims, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.” In the specifications and the claims, the “gradually” means that a change will occur at a moderate rate, opposed to an abrupt or sudden change, as understood by one of ordinary skill in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, embodiments and other subject matters necessary for those skilled in the art to easily understand the contents of the disclosure will be described in detail with reference to the accompanying drawings. In the following description, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

FIG.1is a schematic perspective view illustrating a light-emitting element according to an embodiment, andFIGS.2to4Bare cross-sectional views illustrating the light-emitting element ofFIG.1according to the embodiments.

In an embodiment, the type and/or shape of the light-emitting element are not limited to the embodiments illustrated inFIGS.1to4B.

Referring toFIGS.1to4B, a light-emitting element LD may include a first semiconductor layer11, a second semiconductor layer13, and an active layer12interposed between the first semiconductor layer11and the second semiconductor layer13. The light-emitting element LD may include a first electrode16and a second electrode15.

In an embodiment, the light-emitting element LD may be implemented with a light-emitting stack pattern10in which the second electrode15, the second semiconductor layer13, the active layer12, the first semiconductor layer11, and the first electrode16are stacked.

The light-emitting element LD may be provided in a shape that extends in one direction. When it is assumed that an extending direction of the light-emitting element LD is a direction of a length thereof, the light-emitting element LD may include a first end portion EP1(or lower end portion) and a second end portion EP2(or upper end portion) in the extending direction. One semiconductor layer of the first and second semiconductor layers11and13may be disposed at the first end portion EP1(or lower end portion) of the light-emitting element LD, and the other semiconductor layer of the first and second semiconductor layers11and13may13may be disposed at the second end portion EP2(or upper end portion) of the light-emitting element LD. In an embodiment, the second semiconductor layer13may be disposed at the first end portion EP1(or lower end portion) of the light-emitting element LD, and the first semiconductor layer11may be disposed at the second end portion EP2(or upper end portion) of the light-emitting element LD.

The light-emitting element LD may be provided in various shapes. As an example, the light-emitting element LD may have a rod-like shape, a bar-like shape, or a column shape which is long in a direction of a length L thereof (i.e., has an aspect ratio greater than one). In an embodiment, the length L of the light-emitting element LD in the direction of the length thereof may be greater than a diameter D (or width of a cross section) thereof. The light-emitting element LD may include, for example, a light-emitting diode (LED) manufactured in a very small size to such an extent as to have the diameter D and/or the length L ranging from a nanoscale to a microscale.

The diameter D of the light-emitting element LD may be in a range of about 0.5 μm to about 500 μm, and the length L thereof may be in a range of about 1 μm to about 10 μm. However, the diameter D and the length L of the light-emitting element LD are not limited thereto, and the size of the light-emitting element LD may be changed such that the light-emitting element LD meets requirements (or design conditions) of a lighting device or a self-luminous display device to which the light-emitting element LD is applied.

The second semiconductor layer13may include, for example, at least one p-type semiconductor layer. As an example, the second semiconductor layer13may include a p-type semiconductor layer which includes at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and is doped with a second conductive type dopant (or p-type dopant) such as magnesium (Mg). However, the material constituting the second semiconductor layer13is not limited thereto, and the second semiconductor layer13may be made of various materials. In an embodiment, the second semiconductor layer13may13may include a gallium nitride (GaN) semiconductor material doped with the second conductive dopant (or p-type dopant). The second semiconductor layer13may include an upper surface13bin contact with the active layer12and a lower surface13ain contact with the second electrode15in the direction of the length of the light-emitting element LD.

The active layer12may be disposed on the second semiconductor layer13and may be formed to have a single or multi-quantum well structure. As an example, when the active layer12is formed to have a multi-quantum well structure, in the active layer12, a barrier layer (not illustrated), a strain reinforcing layer, and a well layer may be repeatedly and periodically stacked as one unit. The strain reinforcing layer may have a smaller lattice constant than the barrier layer to further reinforce strain, for example, compression stress applied to the well layer. However, the structure of the active layer12is not limited to the above-described embodiment.

The active layer12may emit light having a wavelength of about 400 nm to about 900 nm and may have a double hetero structure. In an embodiment, a clad layer (not illustrated) doped with a conductive dopant may be formed on an upper portion and/or a lower portion of the active layer12in the direction of the length L of the light-emitting element LD. As an example, the clad layer may be formed as an AlGaN layer or an InAlGaN layer. According to embodiments, a material such as AlGaN or InAlGaN may be used to form the active layer12, and in addition, various materials may constitute the active layer12. The active layer12may include a first surface12ain contact with the second semiconductor layer13and a second surface12bin contact with the first semiconductor layer11.

When an electric field having a certain or predetermined voltage or more is applied to both end portions of the light-emitting element LD, electron-hole pairs combine, and thus, the light-emitting elements LD emits light. By controlling the light emission of the light-emitting element LD using such a principle, the light-emitting element LD may be used as a light source (or light-emitting source) of various light-emitting devices including pixels of a display device.

The first semiconductor layer11may be disposed on the second surface12bof the active layer12and may include a semiconductor layer which is a different type from the second semiconductor layer13. As an example, the first semiconductor layer11may include at least one n-type semiconductor layer. For example, the first semiconductor layer11may be an n-type semiconductor layer which includes any one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and is doped with a first conductive type dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer11is not limited thereto, and the first semiconductor layer11may be made of various materials. In an embodiment, the first semiconductor layer11may11may include a gallium nitride (GaN) semiconductor material doped with the first conductive dopant (or n-type dopant). The first semiconductor layer11may include a lower surface11ain contact with the second surface12bof the active layer12and an upper surface11bin contact with the first electrode16in the direction of the length L of the light-emitting element LD.

In an embodiment, the second semiconductor layer13and the first semiconductor layer11may11may have different thicknesses in the direction of the length L of the light-emitting element LD. As an example, the first semiconductor layer11may have a thickness that is relatively greater than that of the second semiconductor layer13in the direction of the length L of the light-emitting element LD. Accordingly, the active layer12of the light-emitting element LD may be disposed closer to the lower surface13aof the second semiconductor layer13than the upper surface11bof the first semiconductor layer11.

Each of the first semiconductor layer11and the second semiconductor layer13are illustrated as being formed as one layer, but the embodiments are not limited thereto. In an embodiment, each of the first semiconductor layer11and the second semiconductor layer13may further include at least one layer, for example, a clad layer and/or a tensile strain barrier reducing (TSBR) layer according to a material of the active layer12. The TSBR layer may be a strain reducing layer disposed between semiconductor layers having different lattice structures to serve as a buffer for reducing a lattice constant difference. The TSBR layer may be formed as a p-type semiconductor layer including p-GaInP, p-AlInP, or p-AlGaInP, but the embodiments are not limited thereto.

The second electrode15may be in contact with the lower surface13aof the second semiconductor layer13. The second electrode15may be an ohmic contact electrode electrically connected to the second semiconductor layer13. The second electrode15may include a conductive material having a transmittance (or light transmittance) of a certain or predetermined level or more. As an example, the second electrode15may be made of from chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), an oxide or alloy of these materials or a mixture of these materials. The second electrode15may be substantially transparent. Accordingly, light generated in the active layer12of the light-emitting element LD may pass through the second electrode15to be externally emitted from the light-emitting element LD. The second electrode15may include an upper surface15bin contact with the second semiconductor layer13and a lower surface15aexternally exposed in the direction of the length L of the light-emitting element LD. In an embodiment, the lower surface15aof the second electrode15may be the first end portion EP1(or lower end portion) of the light-emitting element LD.

The first electrode16may be provided on the first semiconductor layer11and may be in contact with the upper surface11bof the first semiconductor layer11. In an embodiment, the first electrode16may include a first layer16aand a second layer16b. As an example, the first electrode16may include the second layer16band the first layer16awhich are disposed in the direction of the length L of the light-emitting element LD.

The second layer16bmay be an ohmic contact electrode which is in direct contact with the upper surface11bof the first semiconductor layer11. The second layer16bmay include a conductive material having a transmittance (or light transmittance) of a certain or predetermined level or more. As an example, the second layer16bmay include a transparent conductive oxide selected from the materials described as structure materials of the second electrode15. According to embodiments, the second layer16bmay be made of indium (In), titanium (Ti), chromium (Cr), nickel (Ni), or the like in the form of a thin film. The second layer16bmay include a lower surface16b1in contact with the first semiconductor layer11and an upper surface16b2in contact with the first layer16ain the direction of the length L of the light-emitting element LD.

The first layer16amay be in direct contact with the upper surface16b2of the second layer16b. The first layer16amay be made of a transparent conductive material having a transmittance (or light transmittance) of a certain or predetermined level or more. As an example, the first layer16amay include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), fluorine doped tin oxide (FTO), fluorine doped zinc oxide, or the like. According to embodiments, the first layer16amay include a metal in the form of a thin film. The metal may include gold (Au) or the like. The first layer16amay include a lower surface16a_1in contact with the second layer16band an upper surface16a_2externally exposed in the direction of the length L of the light-emitting element LD. In an embodiment, the upper surface16a_2of the first layer16amay be the second end portion EP2(or upper end portion) of the light-emitting element LD.

The upper surface16a_2of the first layer16amay have an overall uniform (or substantially uniform) surface, for example, a smooth surface. However, the embodiments are not limited thereto, and according to embodiments, as illustrated inFIG.4A, the upper surface16a_2of the first layer16amay have surface roughness so as to include an uneven pattern having overall or substantially uniform (or substantially regular) periodicity. In addition, according to another embodiment, as illustrated inFIG.4B, the upper surface16a_2of the first layer16amay have surface roughness so as to include an uneven pattern having an overall or substantially non-uniform (or substantially irregular) shape. As described above, when the upper surface16a_2of the first layer16aincludes the uneven pattern having the uniform (or regular) periodicity or the uneven pattern having the non-uniform (or irregular) shape, light emitted from the active layer12may be diffusely reflected so that extraction efficiency of light may be further improved.

FIGS.1to4B, for convenience, the first layer16aand the second layer16bare illustrated as having the same thickness in the direction of the length L of the light-emitting element LD, but the embodiments are not limited thereto. According to embodiments, the second layer16bmay be thicker than the first layer16ain the direction of the length L of the light-emitting element LD. As described above, since the second layer16bcorresponds to the ohmic contact electrode in direct contact with the first semiconductor layer11, the second layer16bmay be deposited in the form of a thin film for smooth ohmic contact with the first semiconductor layer11. The second layer16bmay be designed to be thinner than the first layer16ain the direction of the length L of the light-emitting element LD, but the embodiments are not limited thereto.

In an embodiment, the light-emitting stack pattern10may be provided and/or formed to have a shape corresponding to a shape of the light-emitting element LD. For example, when the light-emitting element LD is provided and/or formed to have a cylindrical shape, the light-emitting stack pattern10may also be provided and/or formed to have a cylindrical shape. When the light-emitting stack pattern10has a cylindrical shape, each of the second electrode15, the second semiconductor layer13, the active layer12, the first semiconductor layer11, and the first electrode16may have a cylindrical shape.

In the direction of the length L of the light-emitting element LD, the second electrode15electrically connected to the second semiconductor layer13may be disposed at the first end portion EP1(or lower end portion) of the light-emitting element LD, and the first electrode16electrically connected to the first semiconductor layer11may be disposed at the second end portion EP2(or upper end portion) of the light-emitting element LD. The light-emitting element LD may include the lower surface15aof the second electrode15and the upper surface16a_2of the first layer16aof the first electrode16, which are disposed at both end portions EP1and EP2of the light-emitting element LD and are externally exposed. The lower surface15aof the second electrode15and the upper surface16a_2of the first layer16amay be surfaces (for example, outer surfaces) which are externally exposed to be in contact with external conductive materials, for example, contact electrodes and to be electrically connected to the contact electrodes.

When the light-emitting stack pattern10is provided and/or formed to have the shape corresponding to the shape of the light-emitting element LD, the light-emitting stack pattern10may have a length that is substantially similar to or the same as the length L of the light-emitting element LD.

In an embodiment, the light-emitting element LD may further include an insulating film14. However, according to embodiments, the insulating film14may also be omitted and may also be provided to cover only a portion of the light-emitting stack pattern10.

The insulating film14may prevent an electrical short circuit that may occur when the active layer12comes into contact with conductive materials other than the first and second semiconductor layers11and13. In addition, the insulating film14may minimize surface defects of the light-emitting element LD, thereby improving a lifespan and luminous efficiency of the light-emitting element LD. Furthermore, when a plurality of light-emitting elements LD are closely disposed, the insulating film14may prevent an undesired short circuit that may occur between the light-emitting elements LD. When the active layer12may be prevented from being short-circuited with an external conductive material, whether the insulating film14is provided is not limited.

The insulating film14may include a transparent insulating material. For example, the insulating film14may include at least one insulating material selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), titanium oxide (TiOx), hafnium oxide (HfOx), titanium strontium oxide (SrTiOx), cobalt oxide (CoxOy), magnesium oxide (MgO), zinc oxide (ZnO), ruthenium oxide (RuOx), nickel oxide (NiO), tungsten oxide (WOx), tantalum oxide (TaOx), gadolinium oxide (GdOx), zirconium oxide (ZrOx), gallium oxide (GaOx), vanadium oxide (VxOy), ZnO:Al, ZnO:B, InxOy:H, niobium oxide (NbxOy), magnesium fluoride (MgFx), aluminum fluoride (AlFx), an alucone polymer film, titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlNx), gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN), and vanadium nitride (VN). However, the embodiments are not limited thereto, and various materials having insulating properties may be used as the material of the insulating film14.

The insulating film14may be provided in the form of a single-film or in the form of a multi-film including at least two films.

The insulating film14may be formed and/or provided on an outer circumferential surface (or surface) of the light-emitting stack pattern10so as to surround the outer circumferential surface of the active layer12. The insulating film14may further surround an outer circumferential surface of each of the second electrode15, the second semiconductor layer13, the first semiconductor layer11, and the first electrode16. For convenience,FIG.1illustrates a portion of the insulating film14removed, actually, the second electrode15, the second semiconductor layer13, the active layer12, the first semiconductor layer11, and the first electrode16included in the light-emitting element LD may all be surrounded by the insulating film14. In an embodiment, the insulating film14may completely surround each of the outer circumferential surface of the second electrode15and the outer circumferential surface of the first electrode16, but the embodiments are not limited thereto. The insulating film14may surround only a portion of the outer circumferential surface of the second electrode15and/or only a portion of the circumferential surface of the first electrode16.

The insulating film14may include a lower surface14aparallel to the lower surface15aof the second electrode15in a direction intersecting the direction of the length L of the light-emitting element LD, an upper surface14bopposite to the lower surface14ain the direction of the length L, and a side surface14csurrounding the outer circumferential surface of the light-emitting stack pattern10. The lower surface14aof the insulating film14, the upper surface14bof the insulating film14, and the side surface14cof the insulating film14may be consecutively connected to each other. Here, the upper surface14bof the insulating film14may be defined as a virtual surface including an upper circumference of the insulating film14, and the lower surface14aof the insulating film14may be defined as a virtual surface including a lower circumference of the insulating film14.

The lower surface14aof the insulating film14may be disposed on the same surface (or the same line) as the lower surface15aof the second electrode15, and the upper surface14bof the insulating film14may be disposed on the same surface (or the same line) as the upper surface16a_2of the first layer16aof the first electrode16. The lower surface14aof the insulating film14and the lower surface15aof the second electrode15do not necessarily have to be disposed on the same surface (or the same line) and may be disposed on different surfaces (or different lines) according to embodiments. The upper surface14bof the insulating film14and the upper surface16a_2of the first layer16ado not necessarily have to be disposed on the same surface (or the same line) and may also be disposed on different surfaces (or different lines) according to embodiments. As an example, as illustrated inFIG.3, the upper surface14bof the insulating film14may be disposed on a different surface (or different line) from the upper surface16a_2of the first layer16ato externally expose a portion of the first layer16a, for example, a side surface thereof. The insulating film14may surround a portion of the outer circumferential surface of the first electrode16to expose a portion of the first electrode16. When a portion of the first layer16ais not covered by the insulating film14and is externally exposed, a contact area between a conductive material, for example, a contact electrode (not illustrated) and the first layer16amay be increased. Accordingly, the contact electrode and the first layer16amay be electrically and/or physically connected more stably.

The insulating film14may be formed by forming an insulating material layer (not illustrated) on the outer circumferential surface (or surface) of the light-emitting stack pattern10and then removing a portion of the insulating material layer through an etching process. The above-described etching process may be a dry etching method which is an anisotropic etching method. Due to such an etching process, a portion of the side surface14cof the insulating film14, which is in contact with the upper surface14b, may be provided in a shape having a certain or predetermined radius of curvature or a shape having a certain or predetermined gradient. In this region of the insulating film corresponding to the second end portion EP2(upper end portion), the thickness d of the side surface14cof the insulating film14may14may gradually decrease upward in the direction of the length L of the light-emitting element LD. The region of the insulating film14corresponding to the second end portion EP2may have a different shape from the region corresponding to the first end portion (lower end portion) which is not provided to have a curvature or gradient.

The second electrode15, the second semiconductor layer13, the active layer12, the first semiconductor layer11, and the first electrode16, which are stacked in the direction of the length L of the light-emitting element LD, may have different thicknesses, but the embodiments are not limited thereto.

The light-emitting element LD may be grown and manufactured on a substrate (not illustrated) for epitaxial growth.

A light-emitting element grown on a substrate may be separated from the substrate using a physical method. The separation surface of the light-emitting element may not be constant and may have different surface roughness depending on the regions.

Here, the term “constant” may mean that the size, shape, range, and time of something are uniform or substantially uniform. The term “constant” may also mean that a surface of an object is constantly even, uniform, smooth, or flat. The term “constant” may also mean that a surface of an object is approximately or averagely even, uniform, smooth, or flat. However, the definition of term “constant” is not limited thereto in this disclosure.

In case that a substrate and a light-emitting element grown on the substrate are separated using a physical method, a surface of the light-emitting element separated from the substrate may not have approximately or averagely constant surface roughness and may have a different surface roughness for each region. As an example, in the case of a physical separation method of separating the light-emitting element from the substrate by applying a physical force or impact to the light-emitting element and the substrate, stresses on the substrate and the light-emitting elements may be different according to the intensity (or magnitude) of the applied force at each position, and thus, at least one region of the surface of the light-emitting element separated from the substrate may form uneven steps. Due to the uneven steps, unlike the remaining region of the surface, at least one region of the surface of the light-emitting element may not be constant, for example, may have a rough or uneven shape or non-constant (or non-uniform) surface roughness. The surface roughness of at least one region of the surface of the light-emitting element may be different from that of the remaining region of the surface of the light-emitting element such that the surface of the light-emitting element may have various shapes (or surfaces) without uniformity. The surface of the light-emitting element separated from the substrate and the other surface of the light-emitting element opposite to the surface may have different surface roughness. When one surface of the light-emitting element has a different surface roughness from the other surface, contact defects may occur when the light-emitting element comes into contact with a contact electrode.

In the light-emitting element LD according to the embodiments of this disclosure, in order to mitigate or avoid such uneven and nonuniform surfaces, the light-emitting element LD may be separated using a laser lift-off (LLO) method and/or a chemical lift-off (CLO) method, thereby allowing the first end portion EP1(or lower end portion) and the second end portion EP2(or the upper end portion) of the light-emitting element LD to have an approximately (or averagely) constant surface roughness. This will be described below with reference toFIGS.5to20.

The light-emitting element LD may be used as a light-emitting source (or light source) of various display devices. The light-emitting element LD may be manufactured through a surface treatment process. For example, when the plurality of light-emitting elements LD are mixed in a flowable solution (or solvent) and supplied to each pixel area (for example, an emission area of each pixel or an emission area of each subpixel), the light-emitting elements LD may be surface-treated so as to be uniformly sprayed without being non-uniformly aggregated in the solution.

A light-emitting unit (or light-emitting device) including the light-emitting element LD may be used in various types of electronic devices, such as display devices, which require a light source. For example, when the light-emitting elements LD are disposed in a pixel area of each pixel of a display panel, the light-emitting elements LD may be used as light sources for each pixel. However, the application field of the light-emitting element LD is not limited to these examples. For example, the light-emitting element LD may be used in other types of electronic devices, such as lighting devices, which require a light source.

FIGS.5to20are cross-sectional views sequentially illustrating a method of manufacturing the light-emitting element ofFIGS.1and2.

Referring toFIGS.1,2, and5, a first substrate1configured to support a light-emitting element LD is prepared.

The first substrate1may be a GaAs, GaP, or InP substrate. The first substrate1may be a wafer (or growth substrate) for epitaxial growth. The first substrate1may include a ZnO substrate including a GaAs layer on a surface thereof. Furthermore, a Ge substrate including a GaAs layer on a surface thereof and a Si substrate including a GaAs layer on a Si wafer with a buffer layer interposed therebetween may also be applied.

As for the first substrate1, as an example, a commercially available single crystal substrate may be used. As long as the selectivity for manufacturing the light-emitting element LD is satisfied and epitaxial growth may be smoothly performed, the material for the first substrate1is not limited thereto.

A surface of the first substrate1, upon which epitaxial growth is to be performed, may be flat. The size and diameter of the first substrate1may vary according to the product to which the first substrate1is applied, and the first substrate1may be manufactured in a form capable of reducing a warpage caused by a stacked structure due to epitaxial growth. The shape of the first substrate1is not limited to a circular shape but may be a polygonal shape such as a rectangular shape.

A sacrificial layer3is formed on a first surface SF1(or upper surface) of the first substrate1. In a process of manufacturing the light-emitting element LD, the sacrificial layer3may3may be disposed between the light-emitting element LD and the first substrate1to physically separate the light-emitting element LD and the first substrate1. As illustrated inFIG.5, a second surface SF2(or rear surface) opposite to the first surface SF1of the first substrate1may face downward in a thickness direction DR3of the first substrate1(hereinafter, referred to as a “third direction”).

The sacrificial layer3may include various types of structures and may Include a single-layered structure or a multi-layered structure. The sacrificial layer3may be a layer that is removed in a final manufacturing process of the light-emitting element LD. By removing the sacrificial layer3, layers disposed on and below the sacrificial layer3may be separated.

The sacrificial layer3may be made of GaAs, AlAs, or AlGaAs.

Referring toFIGS.1,2,5, and6, a first electrode16is formed on the sacrificial layer3.

Specifically, a first layer16ais formed on the sacrificial layer3, and a second layer16bis formed on the first layer16a.

The first layer16amay include at least one material selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), fluorine doped tin oxide (FTO), and fluorine doped zinc oxide. According to embodiments, the first layer16amay include a metal in the form of a thin film. The first layer16amay improve contact reliability between a first semiconductor layer11formed through a process to be described below, and a contact electrode (not illustrated). The first layer16amay prevent the second layer16bfrom being externally exposed by a laser irradiated when the first substrate1is removed. Since the first layer16ais made of a transparent conductive oxide and is in ohmic contact with the first semiconductor layer11, electrical characteristics and luminous efficiency of the light-emitting element LD can be further improved. The above-described first layer16amay be a light-transmitting conductive layer.

The second layer16bmay be made of a conductive material having a transmittance of a certain or predetermined level or more, such as indium (In), titanium (Ti), chromium (Cr), or nickel (Ni). According to embodiments, the second layer16bmay be made of a transparent conductive oxide. The second layer16bmay be an ohmic contact layer which is disposed between the first semiconductor layer11and the first layer16aand is in direct ohmic contact with the first semiconductor layer11.

In an embodiment, the first layer16aand the second layer16bmay include different materials.

The first electrode16including the above-described first layer16aand second layer16bmay be an ohmic contact electrode. As an example, the first electrode16may be in ohmic contact with the first semiconductor layer11. However, the embodiments are not limited thereto, and according to embodiments, the first electrode16may be a Schottky contact electrode.

The first electrode16may be deposited on the sacrificial layer3through a sputtering method or the like. The embodiments of the method for forming the first layer16aand the second layer16bon the sacrificial layer3are not limited thereto, and other typical deposition method or the like may be applied.

Referring toFIGS.1,2, and5to7, the first semiconductor layer11is formed on the first electrode16.

The first semiconductor layer11may be formed through epitaxial growth and formed through a metal-organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, a vapor phase epitaxy (VPE) method, a liquid phase epitaxy (LPE) method, or the like. According to embodiments, a buffer layer or an additional semiconductor layer such as an undoped semiconductor layer for improving crystallinity may be further formed between the first semiconductor layer11and the first electrode16.

The first semiconductor layer11may include a group III (Ga, Al, or In)—V (P or As) semiconductor material and may include a semiconductor layer doped with a first conductive type dopant (n-type dopant) such as Si, Ge, or Sn. For example, the first semiconductor layer11may11may include at least one semiconductor material selected from GaP, GaAs, GaInP, and AlGaInP doped with Si. The first semiconductor layer11may include at least one n-type semiconductor layer.

In an embodiment, the first semiconductor layer11may include a gallium nitride (GaN) semiconductor material doped with the first conductive type dopant (or n-type dopant). In case that the first semiconductor layer11includes the gallium nitride semiconductor material, the first semiconductor layer11may include an N-face polarity region and a Ga-face polarity region. According to embodiments, the first semiconductor layer11may have an N-face polarity in which N atoms are arranged on a top layer (exposed surface) or a Ga-face polarity in which Ga atoms are arranged on a top layer (exposed surface).

Referring toFIGS.1,2, and5to8, an active layer12is formed on the first semiconductor layer11. The active layer12is a region in which electrons and holes are recombined. As electrons and holes are recombined to transition to a low energy state, the active layer12may emit light having a corresponding wavelength. The active layer12may12may be formed on the first semiconductor layer11and may be formed in a single or multi-quantum well structure. The position of the active layer12may be changed according to the position of the light-emitting element LD.

The active layer12may include at least one material selected from GaInP, AlGaInP, GaAs, AlGaAs, InGaAs, InGaAsP, InP, and InAs. The active layer12may emit light having a wavelength of about 400 nm to about 900 nm. The active layer12may have a double hetero structure. According to embodiments, a cladding layer (not illustrated) doped with a conductive dopant may be further formed on a first surface12aand/or a second surface12bof the active layer12. According to another embodiment, a TSBR layer may be further formed on the first surface12aof the active layer12.

Referring toFIGS.1,2, and5to9, a second semiconductor layer13is formed on the active layer12. The second semiconductor layer13may include a semiconductor layer which is a different type from the first semiconductor layer11. The second semiconductor layer13may include a group III (Ga, Al, or In)—V (P or As) semiconductor material and may include a semiconductor layer doped with a second conductive type dopant (or p-type dopant) such as Mg. For example, the second semiconductor layer13may include at least one semiconductor material selected from GaP, GaAs, GaInP, and AlGaInP doped with Mg. That is, the second semiconductor layer13may include a p-type semiconductor layer.

Referring toFIGS.1,2, and5to10, a second electrode15is formed on the second semiconductor layer13. The second electrode15may be made from chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), an oxide or alloy of these materials, or a mixture of these materials. In an embodiment, in order to minimize a loss of light generated in the active layer12and externally emitted from the light-emitting element LD and improve current spreading to the second semiconductor layer13, the second electrode15may be made of a transparent conductive oxide such as indium tin oxide (ITO).

The second electrode15may be an ohmic contact electrode. As an example, the second electrode15may be in ohmic contact with the second semiconductor layer13. However, the embodiments are not limited thereto, and according to embodiments, the second electrode15may be a Schottky contact electrode.

The second electrode15may be deposited on the second semiconductor layer13through a sputtering method. However, since nitrogen vacancies may be formed by plasma in the light-emitting element LD including a nitride-based semiconductor, the ohmic contact characteristics of the second electrode15may be degraded when it is deposited through the sputtering method. Accordingly, in consideration of oxygen amounts and deposition temperatures, the second electrode15may be deposited directly on the second semiconductor layer13through an E-beam evaporation method, thereby improving the transmittance of the second electrode15. However, the methods of forming the second electrode15on the second semiconductor layer13are not limited thereto, and other typical deposition methods or the like may be applied.

The second electrode15may have the same thickness as the first electrode16in a direction of a length L of the light-emitting element LD, but the embodiments are not limited thereto. According to embodiments, the second electrode15may have a thickness different from that of the first electrode16in the third direction DR3. In consideration of the oxygen amounts, deposition temperatures, and/or deposition times in the chamber in which a deposition process is performed when the corresponding electrode is formed, the thickness of each of the first and second electrodes16and15may be determined within a range in which the loss of light emitted from the active layer12is minimized.

The first electrode16, the first semiconductor layer11, the active layer12, the second semiconductor layer13, and the second electrode15, which are stacked on the first substrate1, may constitute a light-emitting stack10′.

Referring toFIGS.1,2, and5to11, a buffer layer19is formed on the second electrode15. The buffer layer19may be an inorganic insulating film including an inorganic material. As an example, the buffer layer19may be an inorganic insulating film made of silicon oxide (SiOx).

Referring toFIGS.1,2, and5to12, an adhesive layer20(or bonding metal) for bonding to a second substrate2is formed on the buffer layer19, the second substrate2is disposed on the adhesive layer20, and then, the first substrate1and the second substrate2are bonded to each other.

The second substrate2may be a support substrate which supports the light-emitting stack10′ while a series of processes are performed. The second substrate2may include a rigid substrate such as a glass substrate.

The second substrate2may include a first surface SF1and a second surface SF2opposite to each other. The first surface SF1of the second substrate2may be in contact with the adhesive layer20(or bonding metal), and the second surface SF2of the second substrate2may be exposed.

Referring toFIGS.1,2, and5to13, in order to remove the first substrate1, the first substrate1is turned over such that the first surface SF1of the first substrate1faces downward and the second surface SF2of the first substrate1faces upward. Accordingly, the second surface SF2of the second substrate2may face downward in the third direction DR3. The light-emitting stack10′ may include the second electrode15, the second semiconductor layer13, the active layer12, the first semiconductor layer11, and the first electrode16which are stacked on the first surface SF1of the second substrate2.

Subsequently, the first substrate1is separated from the light-emitting stack10′ through a laser lift-off (LLO) method using a laser. In case that a laser is irradiated onto the first substrate1, the sacrificial layer3and the light-emitting stack10′ may be physically separated. For example, the sacrificial layer3may lose an adhesive function when the laser is irradiated. As the first substrate1is removed, the first layer16aof the first electrode16may be externally exposed.

After the first substrate1is removed through the LLO method, the externally exposed first layer16aof the first electrode16may have constant surface roughness. For example, an entire region of the first layer16aof the first electrode16, which is externally exposed, may approximately (or averagely) have constant surface roughness. Since the first substrate1and the first electrode16are separated by removing the sacrificial layer3through the LLO method without applying a physical force or impact between the first substrate1and the first electrode16, an upper surface16a_1of the first layer16amay have may approximately (or averagely) have constant surface roughness.

Referring toFIGS.1,2, and5to14, a mask layer30is formed on the first electrode16. The mask layer30may include an insulating layer (not illustrated) and a metal layer (not illustrated). The insulating layer may be formed on the first layer16aof the first electrode16. The insulating layer may serve as a mask for continuously etching the light-emitting stack10′. The insulating layer may be made of an oxide or a nitride and may include, for example, silicon oxide (SiOx), silicon nitride (SiNx), or the like. The metal layer may include a metal such as chromium (Cr), but the embodiments are not limited thereto.

Referring toFIGS.1,2, and5to15, one or more fine patterns FP may be formed on the mask layer30. The fine patterns FP may be formed through a polymer layer. The fine patterns FP may be formed by forming the polymer layer on the mask layer30and forming patterns on the polymer layer at nanoscale to microscale intervals. The polymer layer on the mask layer30may be patterned through a method such as photo-lithography, electron beam lithography, or nanoimprint lithography (NIL), thereby forming the fine patterns FP at nanoscale to microscale intervals.

Referring toFIGS.1,2, and5to16, the mask layer30is patterned using the fine patterns FP as a mask to form mask patterns30′. The mask pattern30′ may be formed to have a shape corresponding to the fine pattern FP. The above-described mask pattern30′ may be used as an etching mask for forming light-emitting stack patterns10by etching the light-emitting stack10′. The fine pattern FP may be removed through a typical wet etching method or dry etching method, but the embodiments are not limited thereto. The fine pattern FP may be removed through a typical removal method.

Referring toFIGS.1,2, and5to17, an etching process using the mask patterns30′ as an etching mask is performed to etch the light-emitting stack10′ in a vertical direction, for example, in the third direction DR3at nanoscale to microscale intervals, thereby forming the light-emitting stack patterns10.

In the above-described etching process, a region of the light-emitting stack10′, which does not correspond to the mask pattern30′, may be etched to form a groove HM exposing a region A of the buffer layer19. A region of the light-emitting stack10′, which corresponds to the mask pattern30′, may not be etched.

The groove HM is recessed from an upper surface16a_2of the first layer16aof each light-emitting stack pattern10to region A of the buffer layer19in the third direction DR3.

A dry etching method such as a reactive ion etching (RIE) method, a reactive ion beam etching (RIBE) method, or an inductively coupled plasma reactive ion etching (ICP-RIE) method may be used as an etching method of forming the light-emitting stack patterns10. Unlike wet etching methods, the dry etching methods may allow unidirectional etching and thus may be suitable for forming the light-emitting stack patterns10. In wet etching methods, isotropic etching may be performed, and thus, etching may be performed in all directions. Unlike wet etching methods, in dry etching methods, etching may be mainly performed in a depth direction to form a groove HM that may have a desired size, depth, or the like. According to embodiments, the etching for the light-emitting stack patterns10may be performed through a combination of dry etching and wet etching. For example, after etching is performed in a depth direction through dry etching, the sidewalls may be further etched to be perpendicular to the surface through an isotropic wet etching.

In an embodiment, each of the light-emitting stack patterns10may have a size ranging from a nanoscale to a microscale.

After the above-described etching process is performed, residues remaining on the light-emitting stack patterns10, for example, the mask patterns30′, may be removed through a typical wet etching or dry etching method, but the embodiments are not limited thereto. As an example, the mask pattern30′ may be removed through a typical removal method.

Referring toFIGS.1,2, and5to18, an insulating material layer14′ is formed on the light-emitting stack patterns10and region A of the buffer layer19. The insulating material layer14′ may include an upper insulating material layer, a side insulating material layer, and a lower insulating material layer. The upper insulating material layer may completely cover an upper surface of each of the light-emitting stack patterns10. Here, the upper surface of each of the light-emitting stack patterns10may be the upper surface16a_2of the first layer16a. That is, the upper insulating material layer may completely cover the upper surface16a_2of the first layer16aof each of the light-emitting stack patterns10. The side insulating material layer may completely cover a side surface of each of the light-emitting stack patterns10. The lower insulating material layer may completely cover region A of the buffer layer19exposed by the groove HM.

The upper insulating material layer, the side insulating material layer, and the lower insulating material layer may be consecutively connected to each other on the light-emitting stack patterns10.

As a method of forming the insulating material layer14′, a method of applying an insulating material on the light-emitting stack patterns10disposed on the second substrate2may be used, but the embodiments are not limited thereto. The insulating material layer14′ may include a transparent insulating material. For example, the insulating material layer14′ may include at least one insulating material selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), titanium oxide (TiOx), hafnium oxide (HfOx), titanium strontium oxide (SrTiOx), cobalt oxide (CoxOy), magnesium oxide (MgO), zinc oxide (ZnO), ruthenium oxide (RuOx), nickel oxide (NiO), tungsten oxide (WOx), tantalum oxide (TaOx), gadolinium oxide (GdOx), zirconium oxide (ZrOx), gallium oxide (GaOx), vanadium oxide (VxOy), ZnO:Al, ZnO:B, InxOy:H, niobium oxide (NbxOy), magnesium fluoride (MgFx), aluminum fluoride (AlFx), an alucone polymer film, titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlNx), gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN), and vanadium nitride (VN).

As an example, if the insulating material layer14′ includes aluminum oxide (AlOx), the insulating material layer14′ may be formed through an atomic layer deposition (ALD) method. The insulating material layer14′ may have a thickness of about 30 nm to about 150 nm, but the embodiments are not limited thereto.

Referring toFIGS.1,2, and5to19, an etching process may be performed to remove a portion of the insulating material layer14′, thereby forming an insulating film14. The above-described etching process may be a dry etching method.

Through the above-described etching process, the upper insulating material layer and the lower insulating material layer may be removed, and thus, the insulating film14including only the side insulating material layer covering the side surface of each of the light-emitting stack patterns10may be finally formed. An edge of the upper insulating material layer of the insulating material layer14′ may be over-etched compared with other regions of the insulating material layer14′. By over-etching, the portion of a side surface14cof the insulating film14, which is in contact with an upper surface14b, may be shaped to have a certain or predetermined radius of curvature or to have a certain or predetermined slope. A region of the side surface14cof the insulating film14in contact with the upper surface14band corresponding to the outer circumferential surface of the first electrode, may be shaped such that the thickness d gradually decreases upward in the third direction DR3. Other regions such as the region in contact with a lower surface14aat the lower side of each of the light-emitting stack patterns10may not be over-etched in the above-described etching process. Thus, the other regions may not be shaped to have a radius of curvature and may be shaped to have a uniform thickness d. Accordingly, the region of the insulating film14in contact with the upper surface14b(and corresponding to the second end portion EP2) and the region in contact with the lower surface14a(corresponding to the first end portion EP1) may be provided in different shapes.

Through the above-described etching process, the upper insulating material layer may be removed to expose the upper surface16a_2of the first layer16a. The upper surface14bof the insulating film14may be provided and/or formed on the same surface (or the same line) as the upper surface16a_2of the first layer16a. In addition, through the above-described etching process, the lower insulating material layer may be removed to expose a region of the buffer layer19.

Through the above-described etching process, light-emitting elements LD including the light-emitting stack patterns10and the insulating film14surrounding an outer circumferential surface of each of the light-emitting stack patterns10may be finally formed. The exposed upper surface16a_2of the first layer16amay become a second end portion EP2(or upper surface) of each of the light-emitting elements LD.

Referring toFIGS.1to20, the buffer layer19is removed to separate the light-emitting elements LD from the second substrate2. The buffer layer19may be dissolved by an etching solution such as a hydrofluoric acid (HF). As illustrated inFIG.20, the light-emitting elements LD may be separated from the second substrate2through a CLO method. As the light-emitting elements LD are separated from the second substrate2, the lower surface15aof the second electrode15of each of the light-emitting elements LD may be exposed. The exposed lower surface15aof the second electrode15may become the first end portion EP1(or lower surface) the light-emitting elements LD.

The lower surface15aof the second electrode15, which is separated from the second substrate2and exposed through the CLO method, may approximately (or averagely) have constant surface roughness. The entire region of the lower surface15aof the second electrode15, which is exposed, may approximately (or averagely) have constant surface roughness. Since the second substrate2and the second electrode15are separated by dissolving the buffer layer19through a CLO method without applying physical force or impact to the second substrate2and the second electrode15, the lower surface15aof the second electrode15may have may approximately (or averagely) have constant surface roughness.

In each of the light-emitting elements LD finally manufactured through the above-described manufacturing process, each of the first and second end portions EP1and EP2may approximately (or averagely) have constant surface roughness in the direction of the length L of each light-emitting element LD. As an example, the lower surface15aof the second electrode15corresponding to the first end portion EP1of each light-emitting element LD and the upper surface16a_2of the first layer16acorresponding to the second end portion EP2of the corresponding light-emitting element LD may have a flat surface and the lower surface15aand the upper surface16a_2is parallel to each other.

Since a growth substrate, i.e., the first substrate1and the upper surface16a_2of the first layer16aare separated through the LLO method, and a support substrate, i.e., the second substrate2and the lower surface15aof the second electrode15are separated through the CLO method, in each light-emitting element LD, surfaces (the lower surface15aof the second electrode15and the upper surface16a_2of the first layer16a) separated from the corresponding substrates may have a flat surface. Thus, in each light-emitting element LD, an effective contact area between the lower surface15aof the second electrode15and a contact electrode (not illustrated) in contact with the lower surface15amay be the same or substantially similar to an effective contact area between the upper surface16a_2of the first layer16aand the other contact electrode (not illustrated) in contact with the upper surface16a_2. Accordingly, contact resistance of the first end portion EP1of the light-emitting elements LD may be the same or similar to the contact resistance of the second end portion EP2. The intensity (or amount) of light emitted from each light-emitting element LD may be uniform. Accordingly, the light-emitting elements LD may have uniform luminous efficiency.

FIG.21illustrates a display device according to an embodiment, in particular, is a schematic plan view of a display device using the light-emitting element illustrated inFIGS.1and2as a light source.

InFIG.21, for convenience, the structure of the display device is schematically illustrated based on a display area DA in which an image is displayed.

Referring toFIGS.1,2, and21, the display device according to an embodiment may include a substrate SUB, a plurality of pixels PXL which are provided on the substrate SUB and each include at least one light-emitting element LD, a driver which is provided on the substrate SUB and drives the pixels PXL, and a line portion which connects the pixels PXL and the driver.

When the display device is an electronic device, in which a display surface is applied to at least one surface thereof, such as a smartphone, a television, a tablet personal computer (PC), a mobile phone, an image phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a medical device, a camera, or a wearable device, the embodiments may be applied.

The display device may be classified into a passive matrix type display device or an active matrix type display device according to the method of driving the light-emitting element LD. As an example, when the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor which controls an amount of a current supplied to the light-emitting element LD, a switching transistor which transmits a data signal to the driving transistor, and the like.

The display device may be provided in various shapes, for example, a flat rectangular plate shape having two pairs of sides parallel to each other, but the embodiments are not limited thereto. When the display device is provided in the rectangular plate shape, among the two pairs of sides, one pair of sides may be longer than the other pair of sides. For convenience,FIG.21illustrates a display device with a rectangular shape having a pair of long sides and a pair of short sides. The direction parallel to the long sides may be the second direction DR2, the direction parallel to the short sides may be the first direction DR1, and a direction perpendicular to the long sides and the short sides may be the third direction DR3. In the flat rectangular display device, a corner, at which a long side is in contact with (or meets) a short side, may have a round shape, but the embodiments are not limited thereto.

The substrate SUB may include a display area DA and a non-display area NDA.

The display area DA may be an area in which the pixels PXL displaying an image are provided. The non-display area NDA may be an area in which the driver for driving the pixels PXL and a portion of the line portion for connecting the pixels PXL and the driver are provided. For convenience, only one pixel PXL is illustrated inFIG.21, but multiple pixels PXL may be substantially disposed in the display area DA of the substrate SUB.

The non-display area NDA may be provided on at least one side of the display area DA. The non-display area NDA may surround a periphery (or edge) of the display area DA. The line portion connected to the pixels PXL and the driver connected to the line portion and configured to drive the pixels PXL may be provided in the non-display area NDA.

The line portion may electrically connect the driver and the pixels PXL. The line portion may provide a signal to each pixel PXL and may be a fan-out line portion connected to signal lines, for example, a scan line, a data line, and an emission control line. The line portion also may be a fan-out line portion connected to signal lines connected to each pixel PXL, for example, a control line and a sensing line in order to compensate for changes in electrical characteristics of each pixel PXL in real time.

The substrate SUB may include a transparent insulating material to transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

One area of the substrate SUB may be the display area DA where the pixels PXL may be disposed. The remaining area of the substrate SUB may be the non-display area NDA. As an example, the substrate SUB may include the display area DA including pixel areas in which the pixels PXL are disposed and include the non-display area NDA disposed around (or adjacent to) the display area DA.

The pixels PXL may each be provided in the display area DA of the substrate SUB. In an embodiment, the pixels PXL may be arranged in the display area DA in a stripe arrangement structure or a pentile arrangement structure, but the embodiments are not limited thereto.

Each pixel PXL may include at least one light-emitting element LD driven by a corresponding scan signal and data signal. The light-emitting element LD may have a small size ranging from a nanoscale to a microscale and may be connected in parallel with adjacent light-emitting elements, but the embodiments are not limited thereto. The light-emitting element LD may constitute the light source of each pixel PXL.

Each pixel PXL may include at least one light source, for example, the light-emitting element LD illustrated inFIG.1driven by certain or predetermined signals (for example, a scan signal and a data signal) and/or certain or predetermined power sources (for example, first driving power and second driving power). However, the embodiments are not limited by the type of the light-emitting element LD used as the light source of each pixel PXL.

The driver may provide a certain or predetermined signal and certain or predetermined power to each pixel PXL through the line portion, thereby controlling the driving of the pixel PXL. The driver may include a scan driver, an emission driver, a data driver, and a timing controller.

FIG.22is a circuit diagram illustrating the electrical connections between components included in the pixel PXL illustrated inFIG.21according to an embodiment.

FIG.22illustrates the electrical connections between components included in a pixel PXL applicable to an active type display device according to an embodiment. However, the types of the components included in the pixel PXL to which the embodiments are applicable are not limited thereto.

InFIG.22, not only the components included in each of the pixels illustrated inFIG.21but also the area in which the components are located may be collectively referred to as the pixel PXL.

Referring toFIGS.1,2,21, and22, a pixel PXL may include a light-emitting unit EMU which generates light having luminance corresponding to a data signal. The pixel PXL may further include a pixel circuit PXC for driving the light-emitting unit EMU.

According to embodiments, the light-emitting unit EMU may include a plurality of light-emitting elements LD connected in parallel with each other between a first power line PL1to which a voltage of a first driving power source VDD is applied and a second power line PL2to which a voltage of a second driving power source VSS is applied. For example, the light-emitting unit EMU may include a first pixel electrode EL1(or “first alignment electrode”) connected to the first driving power source VDD through the pixel circuit PXC and the first power line PL1, a second pixel electrode EL2(or “second alignment electrode”) connected to the second driving power source VSS through the second power line PL2, and the plurality of light-emitting elements LD connected in parallel with each other in the same direction between the first pixel electrode EL1and the second pixel electrode EL2. In an embodiment, the first pixel electrode EL1may be an anode, and the second pixel electrode EL2may be a cathode.

Each of the light-emitting elements LD included in the light-emitting unit EMU may include one end portion connected to the first driving power source VDD through the first pixel electrode EL1and the other end portion connected to the second driving power source VSS through the second pixel electrode EL2. The first driving power source VDD and the second driving power source VSS may have different potentials. As an example, the first driving power source VDD may be set as a high potential power source, and the second driving power source VSS may be set as a low potential power source. The potential difference between the first driving power source VDD and the second driving power source VSS may be set to be greater than or equal to the threshold voltage of the light-emitting elements LD during an emission period of the pixel PXL.

As described above, each of the light-emitting elements LD connected in parallel with each other in the same direction (for example, the forward direction) between the first pixel electrode EL1and the second pixel electrode EL2, to which voltages having different potentials are supplied, may each constitute an effective light source. The effective light sources may be clustered to constitute the light-emitting unit EMU of the pixel PXL.

The light-emitting elements LD of the light-emitting unit EMU may emit light having luminance corresponding to the driving current supplied through the corresponding pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to the gradation value of the corresponding frame data to the light-emitting unit EMU. The driving current supplied to the light-emitting unit EMU may be divided to flow in each of the light-emitting elements LD. Accordingly, while each light-emitting element LD emits light at a luminance corresponding to the current flowing therein, the light-emitting unit EMU may emit light at a luminance corresponding to the driving current.

An embodiment is illustrated in which both end portions of the light-emitting elements LD are connected in the same direction between the first driving power source VDD and the second driving power source VSS, but the embodiments are not limited thereto. According to embodiments, the light-emitting unit EMU may further include at least one ineffective light source, for example, a reverse light-emitting element LDr, in addition to the light-emitting-elements LD constituting the effective light sources. The reverse light-emitting element LDr may be connected parallel with the light-emitting elements LD constituting the effective light sources between the first pixel electrode EL1and the second pixel electrode EL2and may be connected between the first pixel electrode EL1and the second pixel electrode EL2in an opposite direction as the light-emitting elements LD. The reverse light-emitting element LDr maintains an inactive state even when a driving voltage (for example, a driving voltage in a forward direction) is applied between the first pixel electrode EL1and the second pixel electrode EL2, and thus, a current does not substantially flow in the reverse light-emitting element LDr.

The pixel circuit PXC may be connected to a scan line Si and a data line Dj of the corresponding pixel PXL. As an example, when the pixel PXL is disposed in an ithrow and a jthcolumn of a display area DA (wherein i is a natural number and j is a natural number), the pixel circuit PXC of the pixel PXL may be connected to an ithscan line Si and a jthdata line Dj of the display area DA. In addition, the pixel circuit PXC may be connected to an ithcontrol line CLi and a jthsensing line SENj of the display area DA.

The above-described pixel circuit PXC may include first to third transistors T1to T3and a storage capacitor Cst.

A first terminal of the first transistor T1(driving transistor) may be connected to the first driving power source VDD, and a second terminal thereof may be electrically connected to the first pixel electrode EL1of each of the light-emitting elements LD. A gate electrode of the first transistor T1may be connected to a first node N1. The first transistor T1may control the amount of a driving current supplied to the light-emitting elements LD in response to a voltage of the first node N1.

A first terminal of the second transistor T2(switching transistor) may be connected to the jthdata line Dj, and a second terminal thereof may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2may be different terminals, and for example, when the first terminal is a source electrode, the second terminal may be a drain electrode. A gate electrode of the second transistor T2may be connected to the ithscan line Si.

The second transistor T2is turned on when a scan signal having a voltage, at which the second transistor T2may be turned on, is supplied from the ithscan line Si, thereby electrically connecting the jthdata line Dj and the first node N1. A data signal of a corresponding frame is supplied to the jthdata line Dj, and thus, the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1is charged in the storage capacitor Cst.

The third transistor T3may be connected between the first transistor T1and the jthsensing line SENj. For example, a first terminal of the third transistor T3may be connected to the first terminal (for example, a source electrode) of the first transistor T1connected to the first pixel electrode EL1, and a second terminal of the third transistor T3may be connected to the jthsensing line SENj. A gate electrode of the third transistor T3may be connected to the ithcontrol line CLi. The third transistor T3is turned on by a control signal having a gate-on voltage supplied to the ithcontrol line CLi during a sensing period, thereby electrically connecting the jthsensing line SENj and the first transistor T1.

The sensing period may be a period for extracting characteristic information (for example, the threshold voltage or the like of the first transistor T1) of each of the pixels PXL disposed in the display area DA.

One electrode of the storage capacitor Cst may be connected to the first driving power source VDD, and the other electrode may be connected to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to a data signal supplied to the first node N1and may maintain the charged voltage until a data signal of a next frame is supplied.

FIG.22illustrates an embodiment in which all of the first to third transistors T1to T3are n-type transistors, but the embodiments are not limited thereto. For example, at least one of the above-described first to third transistors T1to T3may be changed to a p-type transistor. In addition,FIG.22illustrates an embodiment in which the light-emitting unit EMU is connected between the pixel circuit PXC and the second driving power source VSS, but the light-emitting unit EMU may be connected between the first driving power source VDD and the pixel circuit PXC.

The structure of the pixel circuit PXC may be changed and implemented in many ways. As an example, the pixel circuit PXC may further additionally include other circuit elements such as at least one transistor element for initializing the first node N1and/or a transistor element for controlling emission times of the light-emitting elements LD, and a boosting capacitor for boosting the voltage of the first node N1.

FIG.22illustrates an embodiment in which the light-emitting elements LD constituting the light-emitting unit EMU are all connected in parallel, but the embodiments are not limited thereto. The light-emitting unit EMU may include at least one series stage including multiple light-emitting elements LD connected in parallel with each other. The light-emitting unit EMU may also have a series-and-parallel mixed structure.

The structure of the pixel PXL applicable to the embodiments are not limited to the embodiment illustrated inFIG.22, and the pixel PXL may have various structures. For example, each pixel PXL may be provided inside a passive light-emitting display device. The pixel circuit PXC may be omitted, and both end portions of the light-emitting elements LD included in the light-emitting unit EMU may be connected directly to the ithscan line Si, the jthdata line Dj, the first power line PL1to which the first driving power source VDD is connected, the second power line PL2to which the second driving power source VSS is connected, and/or a control line.

FIG.23is a schematic plan view illustrating one of the pixels illustrated inFIG.21.

InFIG.23, for convenience, the transistors and signal lines electrically connected to the transistors T are omitted.

In an embodiment, for convenience of description, a lateral direction (or horizontal direction) may be the first direction DR1, a longitudinal direction (or vertical direction) may be the second direction DR2, and a thickness direction of a substrate SUB in a cross section may be the third direction DR3. The first to third directions DR1, DR2, and DR3may each refer to their respective directions.

Referring toFIG.23, each pixel PXL may be formed in a pixel area PXA provided in the substrate SUB. The pixel area PXA may include an emission area EMA and a peripheral area. In an embodiment, the peripheral area may include a non-emission area from which light is not emitted.

According to embodiments, each pixel PXL may include a bank BNK disposed in the peripheral area.

The bank BNK may be a structure defining (or partitioning) the pixel area PXA or the emission area of each of the corresponding pixel PXL and adjacent pixels PXL and may be, for example, a pixel definition film. In an embodiment, in a process of supplying the light-emitting elements LD to each pixel PXL, the bank BNK may be a pixel definition film or a dam structure defining each emission area EMA to which the light-emitting elements LD should be supplied. As an example, the emission area EMA of each pixel PXL may be partitioned by the bank BNK, and thus, a mixed solution (for example, ink) including the desired amount and/or type of the light-emitting element LD may be supplied (or introduced) to the emission area EMA.

The bank BNK may include at least one light blocking material and/or reflective material to prevent light leakage defects in which light (or light rays) leaks between a pixel PXL and its adjacent pixels. According to embodiments, the bank BNK may include a transparent substance (or material). The transparent material may include, for example, a polyamide-based resin, a polyimide-based rein, or the like, but the embodiments are not limited thereto. According to another embodiment, a reflective material layer may be separately provided and/or formed on the bank BNK in order to further improve efficiency of light emitted from each pixel PXL.

The bank BNK may include one or more openings exposing components disposed under the bank BNK in the pixel area PXA of the corresponding pixel PXL. As an example, the bank BNK may include a first opening OP1and a second opening OP2exposing the components disposed under the bank BNK in the pixel area PXA of the corresponding pixel PXL. According to an embodiment, the emission area EMA of each pixel PXL and the second opening OP2of the bank BNK may correspond to each other.

In the pixel area PXA, the first opening OP1of the bank BNK may be disposed to be spaced apart from the second opening OP2and may be disposed adjacent to one side (for example, an upper or lower side) of the pixel area PXA. As example, the first opening OP1of the bank BNK may be disposed adjacent to the upper side of the pixel area PXA.

Each pixel PXL may include a first pixel electrode EL1and a second pixel electrode EL2spaced apart from each other in the first direction DR1. The first pixel electrode EL1may correspond to the first pixel electrode EL1inFIG.22, and the second pixel electrode EL2may correspond to the second pixel electrode EL2inFIG.22.

After the light-emitting elements LD are supplied and aligned in the pixel area PXA in a process of manufacturing a display device, the first pixel electrode EL1of each pixel PXL may be separated (or cut) from another electrode that originally extends across multiple pixels PXL adjacent in the second direction DR2. The first opening OP1of the bank BNK may be provided for the process of separating (or cutting) the original electrode into the first pixel electrode EL1of each pixel PXL.

The first pixel electrode EL1may be electrically connected to the first transistor T1described with reference toFIG.22through a first contact hole CH1, and the second pixel electrode EL2may be electrically connected to the second driving power source VSS (or second power line PL2) described with reference toFIG.22through a second contact hole CH2.

The first pixel electrode EL1and the second pixel electrode EL2may have a multi-layered structure including a reflective electrode and a conductive capping layer. In addition, the reflective electrode may have a single-layered or multi-layered structure. As an example, the reflective electrode may include at least one opaque metal layer and may optionally further include at least one transparent conductive layer disposed on and/or below the opaque metal layer.

Each pixel PXL may include multiple light-emitting elements LD. According to embodiments, each pixel PXL may further include the reverse light-emitting element LDr inFIG.22.

The light-emitting elements LD may be disposed between the first pixel electrode EL1and the second pixel electrode EL2. Each of the light-emitting elements LD may include a first end portion EP1and a second end portion EP2disposed at the end portions in a direction of its length L. In an embodiment, a second electrode15in ohmic contact with a p-type semiconductor layer may be disposed at the first end portion EP1, and a first electrode16in ohmic contact with an n-type semiconductor layer may be disposed at the second end portion EP2. Here, the p-type semiconductor layer may be the second semiconductor layer13described with reference toFIG.1, and the n-type semiconductor layer may be the first semiconductor layer11described with reference toFIG.1. The light-emitting elements LD may be connected in parallel with each other between the first pixel electrode EL1and the second pixel electrode EL2. Each of the light-emitting elements LD may include the same components as the light-emitting element LD described inFIGS.1and2.

In an embodiment, the first end portion EP1of each of the light-emitting elements LD may be not provided directly on the first pixel electrode EL1but may be electrically connected to the first pixel electrode EL1through at least one contact electrode, for example, a first contact electrode CNE1. The second end portion EP2of each of the light-emitting elements LD may also not be provided directly on the second pixel electrode EL2but may be electrically connected to the second pixel electrode EL2through at least another contact electrode, for example, a second contact electrode CNE2.

Each of the light-emitting elements LD may be a light-emitting diode having a micro size, for example, a small size ranging from a nanoscale to a microscale using a material having an inorganic crystal structure.

At least two to tens of the light-emitting elements LD may be aligned and/or provided in the emission area EMA of each pixel PXL, but the number of the light-emitting elements LD is not limited thereto. According to embodiments, the number of the light-emitting elements LD arranged and/or provided in the emission area EMA may be varied.

Each of the light-emitting elements LD may emit a color light and/or a white light. Each of the light-emitting elements LD may be aligned between the first pixel electrode EL1and the second pixel electrode EL2such that the direction of the length L is parallel to the first direction DR1. The light-emitting elements LD may be introduced (or supplied) to the emission area EMA of each pixel PXL by being sprayed in a solution.

The light-emitting elements LD may be introduced (or supplied) to the emission area EMA of each pixel PXL through an inkjet printing method, a slit coating method, or various other methods. As an example, the light-emitting elements LD may be mixed into a volatile solvent and introduced (or supplied) to the emission area EMA through the inkjet printing method or the slit coating method. When a corresponding alignment signal is applied to the first pixel electrode EL1and the second pixel electrode EL2, an electric field may be formed between the first pixel electrode EL1and the second pixel electrode EL2. As a result, the light-emitting elements LD may be aligned between the first pixel electrode EL1and the second pixel electrode EL2. By volatilizing the solvent or removing the solvent through other methods after the light-emitting elements LD are aligned, the light-emitting elements LD may be stably aligned between the first pixel electrode EL1and the second pixel electrode EL2.

According to embodiments, each pixel PXL may include the first contact electrode CNE1and the second contact electrode CNE2.

The first contact electrode CNE1may be provided and/or formed at the first end portion EP1of each of the light-emitting elements LD and in a corresponding region of the first pixel electrode EL1, physically and/or electrically connecting the first end portion EP1of each of the light-emitting elements LD to the first pixel electrode EL1. The first contact electrode CNE1may be provided and/or formed on the first pixel electrode EL1to overlap the first pixel electrode EL1. The first contact electrode CNE1may have a bar-like shape extending in the second direction DR2in a plan view, but the embodiments are not limited thereto. According to embodiments, the shape of the first contact electrode CNE1may be varied as long as the first contact electrode CNE1is electrically and stably connected to each of the light-emitting elements LD. In addition, the shape of the first contact electrode CNE1may be varied in consideration of the connection with the first pixel electrode EL1disposed under the first contact electrode CNE1.

The second contact electrode CNE2may be provided and/or formed on the second end portion EP2of each of the light-emitting elements LD and on a corresponding region of the second pixel electrode EL2, physically and/or electrically connecting the second end portion EP2of each of the light-emitting elements LD to the second pixel electrode EL2. The second contact electrode CNE2may be provided and/or formed on the second pixel electrode EL2to overlap the second pixel electrode EL2. The second contact electrode CNE2may have a bar-like shape extending in the second direction DR2in a plan view, but the embodiments are not limited thereto. According to embodiments, the shape of the second contact electrode CNE2may be varied as long as the second contact electrode CNE2is electrically and stably connected to each of the light-emitting elements LD. In addition, the shape of the second contact electrode CNE2may be varied in consideration of the connection with the second pixel electrode EL2disposed under the second contact electrode CNE2.

Hereinafter, the stacked structure of each pixel PXL according to the above-described embodiment will be described with reference toFIGS.24to29.

FIG.24is a cross-sectional view taken along line I-I′ ofFIG.23.FIG.25is a schematic enlarged cross-sectional view of portion EA1ofFIG.24.FIG.26is a schematic enlarged cross-sectional view of portion EA2ofFIG.25.FIG.27is a schematic enlarged cross-sectional view of portion EA3ofFIG.25.FIG.28is a cross-sectional view taken along line II-II′ ofFIG.23.FIG.29is a cross-sectional view taken along line III-III′ ofFIG.23.

InFIGS.24to29, a pixel PXL is simplified and illustrated in such a manner that each electrode is illustrated as a single-film electrode and each insulating layer is illustrated only as a single-film insulating layer, but the embodiments are not limited thereto.

Referring toFIGS.23to29, the pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

The substrate SUB may include a transparent insulating material to transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

The rigid substrate may be, for example, one of an organic substrate, a quartz substrate, a glass ceramic substrate, or a crystalline glass substrate.

The flexible substrate may be one of a film substrate and a plastic substrate which may include a polymer organic material. For example, the flexible substrate may include at least one material selected from polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

The pixel circuit layer PCL may include a buffer layer BFL, at least one transistor T, at least one storage capacitor Cst, and a passivation layer PSV.

The buffer layer BFL may prevent impurities from being diffused into the transistor T included in the pixel circuit (refer to “PXC” inFIG.22). The buffer layer BFL may be an inorganic insulating film including an inorganic material. The buffer layer BFL may include at least one material selected from metal oxides such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The buffer layer BFL may be provided as a single-film but may also be provided as a multi-film including at least two films. When the buffer layer BFL is provided as the multi-film, respective layers may be made of the same material or may be made of different materials. The buffer layer BFL may be omitted according to the material and process conditions of the substrate SUB.

The transistor T may include a driving transistor Tdr for controlling a driving current of the light-emitting elements LD and a switching transistor Tsw electrically connected to the driving transistor Tdr. However, the embodiments are not limited thereto, and the pixel circuit PXC may further include circuit elements that perform other functions in addition to the driving transistor Tdr and the switching transistor Tsw. The driving transistor Tdr may be the first transistor T1inFIG.22, and the switching transistor Tsw may be the second transistor T2inFIG.22. In the following embodiments, the driving transistor Tdr and the switching transistor Tsw will be collectively referred to as a transistor T or transistors T.

The driving transistor Tdr and the switching transistor Tsw may each include a semiconductor pattern SCL, a gate electrode GE, a first terminal ET1, and a second terminal ET2. The first terminal ET1may be either a source electrode or a drain electrode, and the second terminal ET2may be the other electrode.

The semiconductor pattern SCL may be provided and/or formed on the buffer layer BFL. The semiconductor pattern SCL may include a first contact region in contact with the first terminal ET1and a second contact region in contact with the second terminal ET2. A region between the first contact region and the second contact region may be a channel region. The channel region may overlap the gate electrode GE of the corresponding transistor T. The semiconductor pattern SCL may be a semiconductor pattern made of poly silicon, amorphous silicon, an oxide semiconductor, or the like. The channel region may be, for example, a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities.

The gate electrode GE may be provided and/or formed on a gate insulating layer GI and correspond to the channel region of the semiconductor pattern SCL. The gate electrode GE may be provided on the gate insulating layer GI to overlap the channel region of the semiconductor pattern SCL. The gate electrode GE may have a single-film structure made of a material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and an alloy of these materials, or a mixture of these materials. The gate electrode may also have a double-film or multi-film structure including a low resistance material, such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) in order to reduce line resistance.

The gate insulating layer GI may be an inorganic insulating film including an inorganic material. As an example, the gate insulating layer GI may include at least one material selected from metal oxides such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the gate insulating layer GI is not limited thereto. According to embodiments, the gate insulating layer GI may be formed as an organic insulating film including an organic material. The gate insulating layer GI may be provided as a single-film, but may also be provided as a multi-film including at least two films.

The first terminal ET1and the second terminal ET2may each be provided and/or formed on a second interlayer insulating layer ILD2and may be in contact with the first contact region and the second contact region of the semiconductor pattern SCL through contact holes passing through the gate insulating layer GI and first and second interlayer insulating layers ILD1and ILD2. As an example, the first terminal ET1may be in contact with the first contact region of the semiconductor pattern SCL, and the second terminal ET2may be in contact with the second contact region of the semiconductor pattern SCL. Each of the first and second terminals ET1and ET2may include the same materials as the gate electrode GE or may include at least one material selected from the materials described as structure materials of the gate electrode GE.

The first interlayer insulating layer ILD1may include the same material as the gate insulating layer GI or may include at least one material selected from the materials described as structural materials of the gate insulating layer GI.

The second interlayer insulating layer ILD2may be provided and/or formed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. According to embodiments, the second interlayer insulating layer ILD2may include the same material as the first interlayer insulating layer ILD1, but the embodiments are not limited thereto. The second interlayer insulating layer ILD2may be provided as a single-film but may also be provided as a multi-film including at least two films.

In the embodiments, the first and second terminals ET1and ET2of the transistor T may be separate electrodes electrically connected to the semiconductor pattern SCL through the contact holes passing through the gate insulating layer GI and the first and second interlayer insulating layers ILD1and ILD2, but the embodiments are not limited thereto. The first terminal ET1may be a first contact region adjacent to the channel region of the corresponding semiconductor pattern SCL, and the second terminal ET2may be a second contact region adjacent to the channel region of the corresponding semiconductor pattern SCL. The second terminal ET2of the transistor T may be electrically connected to the light-emitting elements LD of the corresponding pixel PXL through a separate connection means such as a bridge electrode or the like.

In an embodiment, the transistors T may be formed as low temperature polysilicon thin film transistors, but the embodiments are not limited thereto. The transistors T may be formed as oxide semiconductor thin film transistors. Furthermore, the transistors T are described as thin film transistors having a top gate structure, but the embodiments are not limited thereto. The structure of the transistors T may be varied.

The storage capacitor Cst may include a lower electrode LE provided on the gate insulating layer GI and an upper electrode UE provided on the first interlayer insulating layer ILD1to overlap the lower electrode LE.

The lower electrode LE may be provided on the same layer as the gate electrode GE of the driving transistor Tdr and may include the same material as the gate electrode GE. The lower electrode LE may be integrally provided with the gate electrode GE of the driving transistor Tdr. The lower electrode LE may be regarded as a region of the gate electrode GE of the driving transistor Tdr. According to embodiments, the lower electrode LE may be provided as a component that is separate from (or non-integral with) the gate electrode GE of the driving transistor Tdr. The lower electrode LE and the gate electrode GE of the driving transistor Tdr may be electrically connected through a separate connection means.

The upper electrode UE may overlap the lower electrode LE and may cover the lower electrode LE. A capacitance of the storage capacitor Cst may be increased by increasing the overlapping area of the upper electrode UE and the lower electrode LE. The upper electrode UE may be electrically connected to the first power line (refer to “PL1” ofFIG.22). The storage capacitor Cst may be covered by the second interlayer insulating layer ILD2.

The pixel circuit layer PCL may include a driving voltage line DVL provided and/or formed on the second interlayer insulating layer ILD2. The driving voltage line DVL may be the same component as the second power line PL2described inFIG.22. Accordingly, a voltage of a second driving power source VSS may be applied to the driving voltage line DVL. The pixel circuit layer PCL may further include the first power line PL1connected to a first driving power source VDD. Although not illustrated directly in the drawings, the first power line PL1may be provided on the same layer as the driving voltage line DVL or on a different layer from the driving voltage line DVL. In the embodiments, the driving voltage line DVL may be provided on the same layer as the first and second terminals ET1and ET2of the transistors T, but the embodiments are not limited thereto. According to embodiments, the driving voltage line DVL may be provided on the same layer as any of the conductive layers provided in the pixel circuit layer PCL. The position of the driving voltage line DVL in the pixel circuit layer PCL may be varied.

Each of the first power line PL1and the driving voltage line DVL may include a conductive material (substance). As an example; each of the first power line PL1and the driving voltage line DVL may have a single-film structure made of a material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), an alloy of these materials, or a mixture of these materials. The first power line PL1and the driving voltage line DVL may also have a double-film or multi-film structure including a low resistance material, such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) in order to reduce line resistance. As an example, the first power line PL1and the driving voltage line DVL may be formed as a double-film in which titanium (Ti) and copper (Cu) are stacked.

The first power supply line PL1may be electrically connected to some components of the display element layer DPL, for example, the first pixel electrode EL1, and the driving voltage line DVL may be electrically connected to other components of the display element layer DPL, for example, the second pixel electrode EL2.

The passivation layer PSV may be provided and/or formed on the transistors T and the driving voltage line DVL.

The passivation layer PSV may be provided in the form of an organic insulating film, an inorganic insulating film, or an organic insulating film disposed on an inorganic insulating film. The inorganic insulating film may include, for example, at least one selected from metal oxides such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating film may include, for example, at least one selected from an acrylic-based resin (polyacrylate-based resin), an epoxy-based resin, a phenolic-based resin, a polyamide-based resin, a polyimide-based resin, an unsaturated polyester-based resin, a polyphenylene ether-based resin, a polyphenylene sulfide-based resin, and a benzocyclobutene resin.

The passivation layer PSV may include the first contact hole CH1exposing the second terminal ET2of the driving transistor Tdr and the second contact hole CH2exposing the driving voltage line DVL.

The display element layer DPL may be provided on the passivation layer PSV.

The display element layer DPL may include the bank BNK, the first and second pixel electrodes EL1and EL2, the light-emitting elements LD, the first and second contact electrodes CNE1and CNE2, and first to third insulating layers INS1to INS3.

The bank BNK may be provided and/or formed on the first insulating layer INS1and may define (or partition) the emission area EMA of the corresponding pixel PXL. The bank BNK may include the first opening OP1and the second opening OP2spaced apart from the first opening OP1. The second opening OP2of the bank BNK may correspond to the emission area EMA of each of the pixels PXL.

The first pixel electrode EL1and the second pixel electrode EL2may be disposed to be spaced apart from each other in the first direction DR1. An end portion of the first pixel electrode EL1may be disposed in the first opening OP1of the bank BNK. After the light-emitting elements LD are supplied and aligned in the pixel area PXA of the corresponding pixel PXL in a process of manufacturing a display device, the first pixel electrode EL1may be separated from another electrode (for example, the first electrode (not illustrated) provided to each of the adjacent pixels PXL adjacent in the second direction DR2in a plan view) in the first opening OP1. The first opening OP1of the bank BNK may be provided for a process of separating the first pixel electrode EL1.

In the embodiments, it was described that only the first pixel electrode EL1is separated (or cut) from another electrode in the first opening OP1of the bank BNK, but the embodiments are not limited thereto. According to embodiments, the second pixel electrode EL2may be separated from another electrode that originally extends across multiple pixels PXL adjacent in the second direction DR2. The first opening OP1of the bank BNK may be provided for the process of separating (or cutting) both the first pixel electrode EL1and the second pixel electrode EL2.

Each of the first pixel electrode EL1and the second pixel electrode EL2may be made of a material having certain or predetermined reflectance to allow light emitted from each of the light-emitting elements LD to travel in an image display direction (for example, a front direction) of a display device. As an example, each of the first and second pixel electrodes EL1and EL2may be made of a conductive substance (or material) having certain or predetermined reflectance. The conductive substance (or material) may include an opaque metal that is advantageous in reflecting light emitted from the light-emitting elements LD in an image display direction of a display device. The opaque metal may include, for example, a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy thereof. According to embodiments, each of the first and second pixel electrodes EL1and EL2may include a transparent conductive substance (or material). The transparent conductive substance (or material) may include a conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO), or a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT). When the first and second pixel electrodes EL1and EL2include the transparent conductive substance (or material), a separate conductive layer made of an opaque metal may be added to reflect light emitted from the light-emitting elements LD in an image display direction of a display device. However, the material of the first and second pixel electrodes EL1and EL2is not limited to the above-described materials.

Furthermore, each of the first and second pixel electrodes EL1and EL2may be provided and/or formed as a single-film, but the embodiments are not limited thereto. According to embodiments, each of the first and second pixel electrodes EL1and EL2may be provided and/or formed as a multi-film in which at least two materials selected from metals, alloys, conductive oxides, and conductive polymers are stacked. In order to minimize distortion due to signal delay when a signal (or voltage) is transmitted to both end portions EP1and EP2of each of the light-emitting elements LD, each of the first and second pixel electrodes EL1and EL2may be formed as a multi-film including at least two films. As an example, each of the first and second pixel electrodes EL1and EL2may be formed as a multi-film in which indium tin oxide (ITO), silver (Ag), and ITO are stacked.

The first pixel electrode EL1may be electrically connected to the driving transistor Tdr of the pixel circuit layer PCL through the first contact hole CH1of the passivation layer PSV, and the second pixel electrode EL2may be electrically connected to the driving voltage line DVL of the pixel circuit layer PCL through the second contact hole CH2of the passivation layer PSV. The first and second pixel electrodes EL1and EL2may be used as alignment electrodes for aligning the light-emitting elements LD in each pixel PXL. Furthermore, the first and second pixel electrodes EL1and EL2may be used as driving electrodes for driving the light-emitting elements LD after the light-emitting elements LD are aligned.

The first insulating layer INS1may be provided and/or formed on the first pixel electrode EL1and the second pixel electrode EL2.

The first insulating layer INS1may include an inorganic insulating film made of an inorganic material or an organic insulating film made of an organic material. The first insulating layer INS1may be formed as the inorganic insulating film that is advantageous in protecting the light-emitting elements LD from the pixel circuit layer PCL. As an example, the first insulating layer INS1may include at least one material selected from metal oxides such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx), but the embodiments are not limited thereto. According to embodiments, the first insulating layer INS1may be formed as the organic insulating film that is advantageous in planarizing support surfaces of the light-emitting elements LD.

The first insulating layer INS1may be provided and/or formed on the passivation layer PSV to entirely cover the first pixel electrode EL1and the second pixel electrode EL2. After the light-emitting elements LD are supplied and aligned on the first insulating layer INS1, as illustrated inFIGS.24,25, and28, the first insulating layer INS1may be partially opened to expose one region of each of the first and second pixel electrodes EL1and EL2. After the light-emitting elements LD are supplied and aligned, the first insulating layer INS1may be patterned in the form of an individual pattern that is locally disposed only below the light-emitting elements LD. The first insulating layer INS1may cover the remaining regions excluding one region of each of the first and second pixel electrodes EL1and EL2. The first insulating layer INS1may be omitted according to embodiments.

The bank BNK may be provided and/or formed on the first insulating layer INS1. The bank BNK is formed between other pixels PXL so as to surround the emission area EMA of each pixel PXL and may constitute a pixel definition layer that partitions the emission area EMA of the pixel PXL. In a process of supplying the light-emitting elements LD to the emission area EMA, the bank BNK may be a dam structure that performs control to prevent a solution, in which the light-emitting elements LD are mixed, from flowing into the emission area EMA of the adjacent pixel PXL or to supply a certain or predetermined amount of the solution to each emission area EMA.

The light-emitting elements LD may be supplied and aligned in the emission area EMA of each pixel PXL in which the first insulating layer INS1is formed. As an example, the light-emitting elements LD may be supplied (or introduced) to the emission area EMA through an inkjet method or the like. The light-emitting elements LD may be aligned between the first pixel electrode EL1and the second pixel electrode EL2by a certain or predetermined alignment signal (or alignment voltage) applied to each of the first and second pixel electrodes EL1and EL2.

Each of the light-emitting elements LD may include the first end portion EP1and the second end portion EP2in the direction of the length L parallel to the first direction DR1. Each of the light-emitting elements LD may include a light-emitting stack pattern10and an insulating film14surrounding an outer circumferential surface (or surface) thereof. The light-emitting stack pattern10may include the second electrode15, the second semiconductor layer13, an active layer12, the first semiconductor layer11, and the first electrode16which are stacked in the direction of the length L of each light-emitting element LD parallel to the first direction DR1. In an embodiment, the first semiconductor layer11may include an n-type semiconductor layer doped with an n-type dopant, and the second semiconductor layer13may13may include a p-type semiconductor layer doped with a p-type dopant.

The second electrode15in ohmic contact with the second semiconductor layer13may13may be disposed at the first end portion EP1of each light-emitting element LD, and the first electrode16in ohmic contact with the first semiconductor layer11may be disposed at the second end portion EP2of each light-emitting element LD.

The second insulating layer INS2may be provided and/or formed on the light-emitting elements LD. The second insulating layer INS2may be provided and/or formed on the light-emitting elements LD aligned between the first pixel electrode EL1and the second pixel electrode EL2, thereby partially covering an outer circumferential surface (or surface) of each of the light-emitting elements LD and exposing the first end portion EP1and the second end portion EP2of each of the light-emitting elements LD.

The second insulating layer INS2may be formed as a single-film or a multi-film and may include an inorganic insulating film including at least one inorganic material or an organic insulating film including at least one organic material. The second insulating layer INS2may include the inorganic insulating film that is advantageous in protecting the active layer12of each of the light-emitting elements LD from external oxygen, moisture, or the like. However, the embodiments are not limited thereto. The second insulating layer INS2may be formed as an organic insulating film including an organic material according to design conditions of a display device to which the light-emitting elements LD are applied. After the alignment of the light-emitting elements LD is completed in the pixel area PXA of each of the pixels PXL, the second insulating layer INS2may be formed on the light-emitting elements LD to prevent the light-emitting elements LD from deviating from positions at which the light-emitting elements LD are aligned.

When an empty gap (or space) is between the first insulating layer INS1and the light-emitting elements LD before the second insulating layer INS2is formed, the empty gap may be filled with the second insulating layer INS2in a process of forming the second insulating layer INS2. The second insulating layer INS2may be formed as an organic insulating film that is advantageous in filling the empty gap between the first insulating layer INS1and the light-emitting elements LD.

The first contact electrode CNE1may be provided and/or formed on the first pixel electrode EL1to electrically and/or physically stably connect the first pixel electrode EL1and one end portion of the first and second end portions EP1and EP2of the light-emitting elements LD, for example, the first end portion EP1.

The first contact electrode CNE1may be provided and/or formed on the first pixel electrode EL1and the first end portion EP1of each of the light-emitting elements LD. The first contact electrode CNE1may be disposed to be in contact with the first pixel electrode EL1on a region of the first pixel electrode EL1which is not covered by the first insulating layer INS1. According to embodiments, when a conductive capping layer (not illustrated) is disposed on the first pixel electrode EL1, the first contact electrode CNE1may be disposed on the conductive capping layer to be connected to the first pixel electrode EL1through the conductive capping layer. The conductive capping layer may protect the first pixel electrode EL1from defects or the like generated in a process of manufacturing a display device and may also further intensify adhesion between the first pixel electrode EL1and the pixel circuit layer PCL. The conductive capping layer may include a transparent conductive substance (or material) such as indium zinc oxide (IZO).

The first contact electrode CNE1may be disposed at the first end portion EP1of each of the light-emitting elements LD so as to be in contact with the first end portion EP1of each of the light-emitting elements LD adjacent to the first pixel electrode EL1. The first contact electrode CNE1may be disposed to cover the first end portion EP1of each of the light-emitting elements LD and at least one region of the first pixel electrode EL1corresponding thereto.

The second contact electrode CNE2may be provided and/or formed on the second pixel electrode EL2to electrically and/or physically stably connect the second pixel electrode EL2and one end portion of the first and second end portions EP1and EP2of the light-emitting elements LD, for example, the second end portion EP2.

The second contact electrode CNE2may be provided and/or formed on the second pixel electrode EL2and the second end portion EP2of each of the light-emitting elements LD. The second contact electrode CNE2may be disposed to be in contact with the second pixel electrode EL2on a region of the second pixel electrode EL2which is not covered by the first insulating layer INS1. According to embodiments, when a conductive capping layer is disposed on the second pixel electrode EL2, the second contact electrode CNE2may be disposed on the conductive capping layer to be connected to the second pixel electrode EL2through the conductive capping layer.

The second contact electrode CNE2may be disposed at the second end portion EP2of each of the light-emitting elements LD so as to be in contact with the second end portion EP2of each of the light-emitting elements LD adjacent to the second pixel electrode EL2. The second contact electrode CNE2may be disposed to cover the second end portion EP2of each of the light-emitting elements LD and at least one region of the second pixel electrode EL2corresponding thereto.

The first and second contact electrodes CNE1and CNE2may be made of various transparent conductive materials to allow light, which is emitted from each of the light-emitting elements LD and is reflected by the first and second pixel electrodes EL1and EL2, to travel in an image display direction of a display device without loss. As an example, the first and second contact electrodes CNE1and CNE2may include at least one material selected from various transparent conductive substances (materials) such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO) and may be substantially transparent or semitransparent to satisfy desired transmittance (or transmittancy). However, the material of the first and second contact electrodes CNE1and CNE2is not limited to the above-described embodiment. According to embodiments, the first and second contact electrodes CNE1and CNE2may be made of various opaque conductive substances (or materials). The first and second contact electrodes CNE1and CNE2may be formed as a single-film or a multi-film.

The first contact electrode CNE1and the second contact electrode CNE2may be disposed to be spaced apart from each other in the first direction DR1. As an example, the first contact electrode CNE1and the second contact electrode CNE2may be disposed to be spaced apart from each other by a certain or predetermined distance on the second insulating layer INS2on the light-emitting elements LD.

The first contact electrode CNE1and the second contact electrode CNE2may be provided on the same layer. The first contact electrode CNE1and the second contact electrode CNE2may be formed using the same conductive material through the same process, but the embodiments are not limited thereto. According to embodiments, the first contact electrode CNE1and the second contact electrode CNE2may be formed through different processes and provided on different layers. This will be described below with reference toFIG.33.

The third insulating layer INS3may be provided and/or formed on the first and second contact electrodes CNE1and CNE2. The third insulating layer INS3may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. As an example, the third insulating layer INS3may have a structure in which at least one inorganic insulating film and at least one organic insulating film are alternately stacked. The third insulating layer INS3may entirely cover the display element layer DPL to prevent external water or moisture from being introduced into the display element layer DPL including the light-emitting elements LD.

According to embodiments, the display element layer DPL may optionally further include an optical layer in addition to the third insulating layer INS3. As an example, the display element layer DPL may further include a color conversion layer including color conversion particles that convert light emitted from the light-emitting elements LD into specific color light.

According to another embodiment, at least one overcoat layer (for example, a layer that planarizes an upper surface of the display element layer DPL) may be further disposed on the third insulating layer INS3.

The light-emitting stack pattern10of each light-emitting element LD may include the second electrode15, the second semiconductor layer13, the active layer12, the first semiconductor layer11, and the first electrode16which are stacked in the direction of the length L of the corresponding light-emitting element LD. In an embodiment, the first electrode16may include a second layer16bdisposed on the first semiconductor layer11and a first layer16adisposed on the second layer16b. The first layer16aand the second layer16bmay be made of a transparent conductive material having certain or predetermined transmittance.

The first layer16amay be a component in direct contact with the second contact electrode CNE2and may be a light-transmitting conductive layer. The second layer16bmay be a component in direct contact with the first semiconductor layer11and may be an ohmic contact layer. The first layer16aand the second layer16bmay be made of the same ohmic material or different ohmic materials according to embodiments. In an embodiment, the first layer16aand the second layer16bmay be made of different ohmic materials.

The second electrode15disposed at the first end portion EP1of each light-emitting element LD may be in direct contact with the first contact electrode CNE1. A contact surface CNF1(hereinafter, referred to as a “first contact surface”) between the second electrode15and the first contact electrode CNE1may be the first end portion EP1of each light-emitting element LD. The first layer16aof the first electrode16disposed at the second end portion EP2of each light-emitting element LD may be in direct contact with the second contact electrode CNE2. A contact surface CNF2(hereinafter, referred to as a “second contact surface”) between the first layer16aand the second contact electrode CNE2may be the second end portion EP2of each light-emitting element LD.

The first contact surface CNF1and the second contact surface CNF2may have substantially the same or similar area (or size). In an embodiment, the first contact surface CNF1may be the same as a lower surface15aof the second electrode15, and the second contact surface CNF2may be the same as an upper surface16a_2of the first layer16.

In the embodiments, when each light-emitting element LD is manufactured, the upper surface16a_2of the first layer16amay be separated from a growth substrate, i.e., a first substrate (refer to “1” ofFIG.5) through an LLO method, and the lower surface15aof the second electrode15may be separated from a support substrate, i.e., a second substrate (refer to “2” ofFIG.13) through a CLO method.

Since the upper surface16a_2and the lower surface15aare separated from the corresponding substrates through the LLO method and the CLO method rather than a physical separation method, each of the upper surface16a_2of the first layer16aand the lower surface15aof the second electrode15may have approximately (or averagely) have constant surface roughness. As illustrated inFIGS.26and27, the upper surface16a_2of the first layer16aand the lower surface15aof the second electrode15may have a flat surface. An area of the second contact surface CNF2between the upper surface16a_2of the first layer16aand the second contact electrode CNE2may be the same or similar to an area of the first contact surface CNF1between the lower surface15aof the second electrode15and the first contact electrode CNE1. When the area of the first contact surface CNF1and the area of the second contact surface CNF2are the same or similar, contact resistance of the first contact surface CNF1and contact resistance of the second contact surface CNF2may be the same or similar. When the area of the first contact surface CNF1and the area of the second contact surface CNF2are different, the contact resistance of the first contact surface CNF1and the contact resistance of the second contact surface CNF2may be different. A spreading direction of a current may be non-uniform at the first end portion EP1and the second end portion EP2of each light-emitting element LD. When the spreading direction of the current is non-uniform, a flow of a current in the active layer12of each light-emitting element LD may be non-uniform, and efficiency of current spreading may also be reduced. Thus, overall luminance and driving voltage characteristics may be degraded in each pixel PXL of the display device using the light-emitting element LD as a light source.

In the embodiments, the upper surface16a_2of the first layer16adisposed at the second end portion EP2of each light-emitting element device LD and the lower surface15aof the second electrode15disposed at the first end portion EP1of the corresponding light-emitting element LD may have a flat surface by using an LLO method or a CLO method rather than a physical separation method, and thus, the area of the first contact surface CNF1and the area of the second contact surface CNF2may be the same or similar. As a result, the first end portion EP1and the second end portion EP2of the corresponding light-emitting element LD may have the same or similar contact resistance.

According to the embodiments, the second electrode15in ohmic contact with the second semiconductor layer13may be disposed at the first end portion EP1of each light-emitting element LD, and the first electrode16in ohmic contact with the first semiconductor layer11may be disposed at the second end portion EP2of each light-emitting element LD. Thus, the characteristics of the first end portion EP1and the second end portion EP2of the corresponding light-emitting element LD may be uniform. Since the characteristics of both end portions EP1and EP2of each light-emitting element LD are uniform, the light-emitting elements LD may have uniform luminous efficiency. Accordingly, luminance of each pixel PXL in which the light-emitting elements LD are aligned and luminance of the adjacent pixels PXL adjacent to the corresponding pixel PXL may be uniform. As a result, the display device including the pixels PXL may have uniform luminance over an entire area.

FIG.30is a schematic plan view illustrating a pixel according to another embodiment.FIG.31is a cross-sectional view taken along line IV-IV′ ofFIG.30.FIG.32is a cross-sectional view corresponding to line IV-IV′ ofFIG.30which illustrates a bank pattern ofFIG.31that is implemented according to another embodiment.FIG.33is a cross-sectional view corresponding to line IV-IV′ ofFIG.30which illustrates first and second contact electrodes ofFIG.31that are implemented according to another embodiment.

A pixel PXL illustrated inFIGS.30to33may have a configuration that is substantially the same or similar to that of the pixel illustrated inFIGS.23to29except that a bank pattern BNKP is disposed between a passivation layer PSV and each of first and second pixel electrodes EL1and EL2.

Accordingly, in relation to the pixel ofFIGS.30to33, differences from the above-described an embodiment will be mainly described in order to avoid redundant descriptions.

Referring toFIGS.30to33, a support member (or pattern) may be disposed between each of the first and second pixel electrodes EL1and EL2and the passivation layer PSV. As an example, as illustrated inFIGS.31to33, the bank pattern BNKP may be disposed between each of the first and second pixel electrodes EL1and EL2and the passivation layer PSV.

The bank pattern BNKP may be disposed in an emission area EMA of a pixel area PXA in each pixel PXL, from which light is emitted. In order to guide light emitted from light-emitting elements LD in an image display direction of a display device, the bank pattern BNKP may be a support member which supports each of the first and second pixel electrodes EL1and EL2to change a surface profile (or shape) of each of the first and second pixel electrodes EL1and EL2.

The bank pattern BNKP may be provided between the passivation layer PSV and the first and second pixel electrodes EL1and EL2in the emission area EMA of the corresponding pixel PXL.

The bank pattern BNKP may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. According to embodiments, the bank pattern BNKP may include a single organic insulating film and/or a single inorganic insulating film, but the embodiments are not limited thereto. According to embodiments, the bank pattern BNKP may be provided in the form of a multi-film in which at least one organic insulating film and at least one inorganic insulating film are stacked. However, the material of the bank pattern BNKP is not limited thereto, and according to the embodiments, the bank pattern BNKP may include a conductive material.

The bank pattern BNKP may have a cross section having a trapezoidal shape of which a width is gradually decreased upward from a surface (for example, an upper surface) of the passivation layer PSV in a third direction DR3, but the embodiments are not limited thereto. According to embodiments, as illustrated inFIG.32, the bank pattern BNKP may have a curved surface including a cross section with a semi-elliptical shape or a semicircular shape (or hemisphere shape) of which a width is gradually decreased upward from a surface of the passivation layer PSV in the third direction DR3. When viewed in a cross section, the shape of the bank pattern BNKP is not limited to the above-described embodiments and may be varied as long as the efficiency of the light emitted from each of the light-emitting elements LD is improved.

Each of the first and second pixel electrodes EL1and EL2may be provided and/or formed on the corresponding bank pattern BNKP. Each of the first and second pixel electrodes EL1and EL2may have a surface profile corresponding to the shape of the bank pattern BNKP disposed thereunder when viewed in a cross section. Accordingly, light emitted from the light-emitting elements LD may be reflected by each of the first and second pixel electrodes EL1and EL2to further travel in an image display direction of a display device. Each of the bank pattern BNKP and the first and second pixel electrodes EL1and EL2may be used as a reflective member to improve light efficiency of a display device by guiding light emitted from the light-emitting elements LD in a desired direction. Accordingly, luminous efficiency of the light-emitting elements LD may be further improved.

A first contact electrode CNE1and a second contact electrode CNE2may be disposed to be spaced apart from each other in a first direction DR1in a plan view. As an example, the first contact electrode CNE1and the second contact electrode CNE2may be disposed to be spaced apart from each other by a certain or predetermined interval on a second insulating layer INS2on the light-emitting elements LD. The first contact electrode CNE1and the second contact electrode CNE2may be provided on the same layer and may be formed through the same process. However, the embodiments are not limited thereto, and the first and second contact electrodes CNE1and CNE2may be provided on different layers and may be formed through different processes. As illustrated inFIG.33, an additional insulating layer AUINS may be provided and/or formed between the first contact electrode CNE1and the second contact electrode CNE2. The additional insulating layer AUINS may be provided on the first contact electrode CNE1to prevent the first contact electrode CNE1from being externally exposed, thereby preventing corrosion of the first contact electrode CNE1. The additional insulating layer AUINS may include an inorganic insulating film made of an inorganic material or an organic insulating film made of an organic material. As an example, the additional insulating layer AUINS may include at least one material selected from metal oxides such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx), but the embodiments are not limited thereto. In addition, the additional insulating layer AUINS may be formed as a single-film or a multi-film.

A third insulating layer INS3may be provided and/or formed on the first and second contact electrodes CNE1and CNE2. The third insulating layer INS3may be an inorganic insulating film including an inorganic material or an organic insulating film including an organic material. As an example, the third insulating layer INS3may have a structure in which at least one inorganic insulating layer and at least one organic insulating layer are alternately stacked. The third insulating layer INS3may entirely cover a display element layer DPL to prevent external water or moisture from being introduced into the display element layer DPL including the light-emitting elements LD. According to embodiments, at least one overcoat layer (for example, a layer that planarizes an upper surface of the display element layer DPL) may be further disposed on the third insulating layer INS3.

In a light-emitting element, a method of manufacturing the light-emitting element, and a display device including the light-emitting element, since a first electrode in ohmic contact with an n-type semiconductor layer is separated from a growth substrate (first substrate) using a laser lift-off method, and a second electrode in ohmic contact with a p-type semiconductor layer is separated from a support substrate (second substrate) using a chemical lift-off method, a separation surface of the first electrode and a separation surface of the second electrode may have constant surface roughness. Accordingly, it is possible to manufacture a light-emitting element of which both end portions have uniform characteristics.

In addition, a contact area of a first contact electrode in contact with the first electrode of each light-emitting element may be substantially the same or similar to a contact area of a second contact electrode in contact with the second electrode of the corresponding light-emitting element. Accordingly, it is possible to minimize defects due to non-uniform contact areas at both end portions of each light-emitting element, thereby improving the reliability of the corresponding light-emitting element.

The effects according to an embodiment are not limited by the above-described contents, and other effects are included in the specification.

Although embodiments have been described, it is understood that the disclosure should not be limited to these embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the disclosure as hereinafter claimed.

Therefore, the technical scope of the disclosure is not limited to the embodiments described herein, but should be determined by claims.