Patent ID: 12244686

DETAILED DESCRIPTION

Hereinafter, example embodiments will be described clearly and in detail to the extent that a person of ordinary skill in the art may easily implement the same using the drawings.

An image sensor, an image processing system having the same, and an operating method of the same, according to some embodiments, may include a differential power analysis (DPA) countermeasure module using a private key stored in a non-volatile memory (NVM) of a CMOS image sensor (CIS), to prevent or incapacitate a DPA attack against the private key (or a secret key). In addition, an image sensor, an image processing system having the same, and an operating method of the same, according to some embodiments, may store a encoded private key in a non-volatile memory (e.g., NVM), may load the encoded private key from the non-volatile memory during a decryption operation, and may restore a private key from the encoded private key, to fundamentally block a DPA attack at the time of loading the private key. Therefore, an image sensor, an image processing system having the same, and an operating method of the same, according to some embodiments, may eliminate the possibility of leakage of a private key due to a DPA attack and may improve reliability of a cyber security system.

FIG.1is a view illustrating an image processing system10according to some embodiments. Referring toFIG.1, an image processing system10may include an image sensor100and a controller200. In some embodiments, the image sensor100may be, for example, a CMOS image sensor (CIS). In some embodiments, the controller200may be an electronic control unit (ECU). For example, the image sensor100may be a camera device that performs an imaging operation using a camera lens. The image processing system10may be applied to various types of systems. For example, the image processing system10may be applied to an autonomous driving system.

Although a device for controlling the image sensor100is illustrated inFIG.1as the controller200, with an example of the electronic control unit (ECU), it should be understood that the controller of various embodiments is not limited thereto. In addition to an ECU, the controller200of some embodiments may be an image signal processor (ISP), an application processor (AP), and/or a host.

The image sensor100may be implemented to acquire an image from around a vehicle. The image sensor100may be implemented to convert the acquired image into a security image guaranteeing reliability and to transmit the converted security image to the controller200. In an embodiment, the security image may include original image data IMG and a tag for verifying reliability of the original image data IMG. In some embodiments, the tag may be a cipher-based message authentication code (CMAC). In another embodiment, the security image may include an image encrypted based on an encryption algorithm.

The image sensor100may include an image sensing circuit110, a signal processor120, a security circuit130, an NVM160, and an interface circuit170(MIPI). In an embodiment, the image sensor100may be implemented as a vehicle image sensor, for example, ISOCELL Auto 4AC.

The image sensing circuit110may be implemented to obtain an image using a plurality of pixels. The image sensing circuit110may include a pixel array implemented as one of an N-type metal-oxide-semiconductor (NMOS) image sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, or a charge coupled device (CCD) image sensor.

The signal processor120may be implemented to output the image data IMG by processing an image signal that is acquired from the image sensing circuit110according to at least one processing method.

The security circuit130may be implemented to perform a series of security functions (e.g., an authentication operation, a key exchange operation, an encryption/decryption operation, etc.) to convert the acquired image data IMG into a security image. In this case, the security circuit130may be implemented in software, hardware, and/or firmware. For example, the security circuit130may include one or more microprocessors that execute the security functions described herein or control logic configured to implement the security functions described herein.

The security circuit130may be implemented to perform an authentication operation with the controller200. In this case, the authentication operation may be performed based on various algorithms. In an embodiment, an authentication procedure may be performed based on an asymmetric-key algorithm such as Rivest Shamir Adleman (RSA), elliptic curve cryptography (ECC), Diffie-Hellman, or the like. In another embodiment, the authentication procedure may be performed based on a symmetric-key algorithm such as advanced encryption standard (AES), data encryption standard (DES), or the like. In an embodiment, the authentication operation may be initiated after an operation of setting up the image sensor100. While the authentication operation is performed, the image data IMG and the tag, acquired from the image sensor100, may be transmitted separately to the controller200. In other words, the image transmitted simultaneously with the authentication operation may not include the tag for reliability verification. By contrast, once the authentication operation has been completed, the image data IMG and the tag may be transmitted simultaneously to the controller200.

The security circuit130may be implemented to perform a security processing operation on the image data IMG to identify whether the image transmitted from the controller200has been forged or tampered with. In this case, the security processing operation may generate the tag for the acquired image data IMG.

In an embodiment, the security circuit130may generate the tag using the image data IMG and key information (e.g., shared key information). In this case, the tag may be, for example, a message authentication code (MAC) for all or a portion of the image data IMG. In some embodiments, the MAC may be, for example, a cipher-based message authentication code (CMAC)).

The security circuit130may include a crypto module131, a DPA countermeasure module132, and a private key generator133. The crypto module131may be implemented to perform an encryption operation or a decryption operation, based on an encryption algorithm. For example, in some embodiments, the crypto module131may be executed by the one or more microprocessors of the security circuit130to perform the operations of the module described herein, or may be implemented as a crypto circuit or logic that is part of the security circuit130. In an embodiment, the crypto module131may receive a cipher text CT from the controller200, and may decrypt the cipher text CT using a private key PrivK of the image sensor100and an encryption algorithm (a public key-based algorithm, for example, an RSA encryption algorithm). In this case, the cipher text CT may be encrypted in the controller200by a public key PubK of the image sensor100and the encryption algorithm.

The DPA countermeasure module132may be implemented to prevent a DPA attack against the image sensor100. For example, in some embodiments, the DPA countermeasure module132may be executed by the one or more microprocessors of the security circuit130to perform the operations of the module described herein, or may be implemented as a DPA countermeasure circuit or logic that is part of the security circuit130.0. In general, a DPA attack may acquire a private key (e.g., a secret key) by analyzing power consumption when an encryption algorithm is executed. A countermeasure on the DPA attack may have a method of modifying an encryption algorithm itself using a random number, and a method of eliminating correlation between information of power consumption to be leaked and an intermediate value, during an encryption operation, using a dual-rail logic. In this case, the dual-rail logic method may insert a random time or use a random clock. All of these countermeasures may require a random number. The DPA countermeasure module132may defend against a differential power attack using a random number.

In an embodiment, the random number may be generated from a true random number generator. In another embodiment, the random number may be generated from a pseudo-random number generator. For example, the random number may be generated using the cipher text CT transmitted from the controller200to generate a random number required for a DPA defense operation. In this case, the cipher text CT may have the randomness (or entropy) of an encryption algorithm used. This randomness may be because, for example, in an RSA encryption algorithm, the cipher text CT may be generated using a random padding technique.

In general, an RSA encryption algorithm requires two keys. One key may be a public key, and the other key may be a private key. A message (m) may be encrypted using the public key, and a cipher text may be decrypted using the private key. Generation of the keys through the RSA encryption algorithm may be as follows. First, two large prime numbers p and q may be randomly chosen. In this case, a value of n may be determined by n=pq. Also, ϕ(n)=(p−1)(q−1), which is the number of numbers that may be less than or equal to n and may be prime to n, may be calculated. Here, 1<e<φ(n), and e may be chosen such that e and φ(n) are coprime. Thereafter, d in which de≡1(mod ϕ(n)) is satisfied may be calculated. That is, for any integer k, de=1+kφ(n) will be satisfied. In this case, (n, e) may be the public key and d may be the private key. In this case, a sender may transmit c=memod n to a receiver. The receiver may receive c from the sender, and may execute decryption using a private key (d) from c, to calculate m=cdmod n. This may be because it is med≡0ed=0≡m (mod p). An RSA encryption algorithm uses a principle that it is easy to make a composite number using a prime number, but it is difficult to make a prime number by factoring a composite number into a prime number. In this case, the RSA encryption algorithm may basically have randomness. Therefore, messages (m), which are identical, may be output as cipher text having different values, when the messages are encrypted using an encryption algorithm.

In summary, the DPA countermeasure module132may be implemented to reduce direct exposure of the private key using a random number, when a security processing operation (an authentication operation, a decryption operation, a key generation operation, a MAC operation, etc.) is performed.

The private key generator133may be implemented to read an encoded private key from the NVM160, and to restore a private key of the image sensor100. For example, in some embodiments, the private key generator133may be executed by the one or more microprocessors of the security circuit130to perform the operations of the generator described herein, or may be implemented as a private key generator circuit or logic that is part of the security circuit130. In an embodiment, the private key generator133may read the encoded private key from the NVM160for message decryption, every time the image sensor100is booted, and may decode the read encoded private key according to a predetermined method, to generate the private key.

The NVM160may be implemented to store a public key and an encoded (or a changed) private key. In an embodiment, the public key and the encoded private key may be stored in the NVM160in manufacturing the image sensor100. In an embodiment, the NVM160may be implemented as an one-time programmable (OTP) memory. In another embodiment, the NVM160may be implemented as a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase-change memory (PRAM), a magneto-resistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), or the like.

The interface circuit170may transmit acquired image data IMG and a security image to which the tag is attached, to the controller200, according to a predetermined interface standard. In an embodiment, the interface standard may be a mobile industry processor interface (MIPI) standard, an MIPI automotive SerDes solution (MASS) standard, a DisplayPort standard, or the like.

The controller200may be implemented to perform an authentication operation with the image sensor100. The controller200may transmit a cipher text CT encrypted with the public key of the image sensor100to the image sensor100. In this case, the cipher text CT may be transmitted through an interface standard such as an inter-integrated circuit (I2C), a serial peripheral interface (SPI), a universal asynchronous receiver/transmitter (UART), or the like.

In addition, the controller200may be implemented to receive security image data (e.g., IMG and tag) transmitted from the image sensor100, check integrity of image data thereto, and perform a processing operation on the image data. For example, the controller200may be implemented as a semiconductor chip implemented separately from the image sensor100. In an embodiment, the semiconductor chip may be a system-on-chip (SoC) in which at least one processor and an image processing module are integrated. For example, the controller200may be an advanced driver assistance system (ADAS) SOC. In an embodiment, the controller200may calculate a MAC value using the received image data IMG and information of a session key shared with the image sensor100, and may compare the calculated MAC value with a MAC value (e.g., a CMAC) transmitted from the image sensor100, to verify integrity of the image data IMG transmitted from the image sensor100.

In addition, the controller200may communicate with an external controller in various communication methods, such as controller area network (CAN), media oriented system transport (MOST), local interconnected network (LIN), FlexRay, Ethernet, or the like.

As illustrated inFIG.1, in the image processing system10, one controller200and one image sensor100are illustrated. However, embodiments are not limited thereto, and according to various embodiments, the image processing system10may be implemented to have various other forms. An image processing system according to other embodiments may include a plurality of controllers200and/or a plurality of image sensors100and may be implemented by variously combining the number of controllers or the number of image sensors.

The controller200may analyze a large amount of images received from each camera sensor, may interpret current traffic conditions and obstacles based thereon, and may then execute device control for subsequent operations in real time. At the same time, the controller200may perform a security processing operation to confirm whether an image is transmitted from a correct camera device and whether forgery or tampering has occurred in a process of transmitting the image.

The controller200may include a security module201that performs the above-described security function. In various embodiments, the security module201may be implemented in software, hardware, and/or firmware. In general, the security module201may refer to a cryptographic processor specially designed for protecting a lifecycle of an encryption key. The security module201may perform cryptographic processing, key protection, and key management within an enhanced anti-counterfeiting device.

In some embodiments, the security module201may be a hardware security module (HSM). In general, an HSM used in a vehicle controller domain may include a secure memory for safely storing a key. For example, the secure memory may include an HSM dedicated random access memory (RAM) or a read only memory (ROM) with high security, separate from a host system. The HSM may perform a series of operations through a dedicated central processing unit (CPU) to perform functions relatively safely from attacks by potential attackers.

A related art vehicle image processing system may include a hardware block in which a security function is mounted on an image sensor. Such a hardware block may receive an encrypted message from a host, and may decrypt the encrypted message. During this decryption operation, it may be necessary to load a private key stored in a non-volatile memory in the image sensor into a decryption module. In this case, a DPA attack may be performed by an attacker. When the private key is stored in the non-volatile memory as a raw value, the private key may be leaked externally by the DPA attack.

By contrast, in the image processing system10according to some embodiments, an encoded (or changed/converted) private key with immunity to the DPA attack from the NVM160may be loaded into the security circuit130of the image sensor100, to incapacitate the DPA attack on the private key, even when receiving the DPA attack. For example, the image sensor100inFIG.1may store the encoded private key to be efficiently restored, to block the DPA attack at the time of loading the private key and perform a relatively fast security processing operation, at the same time.

FIG.2Ais a view illustrating an image sensing circuit110according to some embodiments. Referring toFIG.2A, the image sensing circuit110may include a pixel array111, a row driver112, an analog-to-digital converter (ADC)113, a ramp voltage generator (Ramp GNRT)116, a timing controller (CTRL)117, and an output buffer118.

The pixel array111may include a plurality of pixels arranged in a matrix form, each of which is connected to a plurality of row lines and a plurality of column lines. Each of the plurality of pixels may include a photosensing device. For example, the photosensing device may include a photodiode, a phototransistor, a port gate, or a pinned photodiode.

Each of the plurality of pixels may include at least one photosensing device. In an embodiment, each of the plurality of pixels may include a plurality of photosensing devices. The plurality of photosensing devices may be stacked on each other. Each of the plurality of pixels may sense light using the photosensing device, and may convert the light into a pixel signal which may be an electrical signal. Each of the plurality of pixels may sense light within a specific spectral region. For example, the plurality of pixels may include a red pixel for converting light in a red spectral region into an electrical signal, a green pixel for converting light in a green spectral region into an electrical signal, and a blue pixel for converting light in a blue spectral region into an electrical signal. A color filter for transmitting light of a specific spectral region may be disposed on each of the plurality of pixels.

In an embodiment, each of the plurality of pixels may include a pixel group having various color patterns on which the row lines and the column lines intersect. In this case, the pixel group may be implemented to have a 2×2 Bayer pattern, a 4×4 Tetra pattern, or an 8×8 Q-cell pattern, or may be implemented to have an infrared sub-pixel. In an embodiment, the pixel array111may be implemented with pixels suitable for a dynamic vision sensor.

The row driver112may be implemented to drive the pixel array111in a row unit. The row driver112may decode a row control signal (e.g., an address signal) generated by the timing controller170, and may select at least one of the row lines included in the pixel array111in response to the decoded row control signal. For example, the row driver112may generate a row selection signal. The pixel array111may also output a pixel signal from a row selected by the row selection signal provided by the row driver112. The pixel signal may include a reset signal and an image signal.

The analog-to-digital converter (ADC)113may be implemented to convert an analog pixel signal input from the pixel array111into digital data. The analog-to-digital converter113may include a comparison circuit and a counter circuit. The comparison circuit may be configured to compare a pixel signal output by a unit pixel connected to one of column lines included in the pixel array111, with a ramp voltage. The comparison circuit may include a plurality of comparators provided to correspond to each column. Each of the comparators may be connected to the pixel array111and the ramp voltage generator116. The comparator may be configured to compare the pixel signal with the received ramp voltage RAMP generated by the ramp voltage generator (Ramp GNRT)116, and to output a comparison result signal to an output terminal.

The counter circuit of the analog-to-digital converter (ADC) may include a plurality of counters. Each of the plurality of counters may be connected to the output terminal of the comparators, and may be configured to count based on the output of each comparator. A counter control signal may include a counter activation signal, a counter clock signal, a counter reset signal for controlling a reset operation of the plurality of counters, an inverting signal for inverting internal bits of each of the plurality of counters, or the like. The counter circuit may count a comparison result signal according to the counter clock signal, to output the signal as digital data. The counter may include an up/down counter or a bit-wise counter. In this case, the bit-wise counter may perform an operation similar to that of the up/down counter. For example, the bit-wise counter may perform a function of only up-counting, and may perform a function of inverting entire bits in the counter into 1's complements, when a specific signal comes in. The bit-wise counter may perform a reset count, and may invert the count into 1's complements, that is, a negative value.

The ramp voltage generator (Ramp GNRT)116may be implemented to generate a ramp voltage RAMP. The ramp voltage generator116may operate based on a ramp control signal provided by a timing controller117. The ramp control signal may include a ramp enable signal, a mode signal, and the like. When the ramp enable signal is activated, the ramp voltage generator116may generate a ramp voltage RAMP having a slope determined based on the mode signal.

The timing controller (CTRL)117may be implemented to control operations or timings of the row driver112, the analog-to-digital converter113, and the ramp voltage generator116by outputting a control signal or a clock signal to each of the row driver112, the analog-to-digital converter113, and the ramp voltage generator116. The timing controller117may also generate switching control signals provided to the comparison circuit to differentiate decision speeds, depending on a column line group.

The output buffer118may be implemented to temporarily store, amplify and output digital data output by the analog-to-digital converter113. The output buffer118may include a column memory block and a sense amplifier circuit. The column memory block may include a plurality of memories. Each of the plurality of memories may temporarily store digital data output by each of the plurality of counters and may output the digital data to the sense amplifier circuit. The sense amplifier circuit may be implemented to sense and amplify digital data output by the plurality of memories. The sense amplifier circuit may output the amplified digital data IDATA to the signal processor120(refer toFIG.1) as image data.

FIG.2Bis a view illustrating a signal processor120according to some embodiments. Referring toFIG.2B, a signal processor120may include a first image processor121and a second image processor122.

The signal processor120may be implemented to receive an image signal IDATA acquired from the image sensing circuit110, perform at least one image processing operation on the image signal IDATA, and output the processed image data IDATA to an external entity.

Processing performed by at least one of the first image processor121and the second image processor122may include generating a depth map, 3D modeling, generating a panorama, extracting feature points, synthesizing an image, or compensating an image (e.g., reducing noise, adjusting resolution, adjusting brightness, bluffing, sharpening, softening). The signal processor120may also perform exposure time control, readout timing control, or the like.

In addition, the image data IMG output from the signal processor120may be transmitted to the security circuit130and the interface circuit170. The security circuit130may receive the image data IMG, and may generate a tag for integrity of the image data IMG for all or a portion of the image data IMG. The tag may be, for example, a MAC value, e.g., a CMAC. The interface circuit170may receive the image data IMG from the signal processor120, may receive the tag from the security circuit130, may generate a security image conforming to the interface standard, and the generated security image may be transmitted to an external device (e.g., the controller200).

FIGS.3A and3Bare views illustrating a crypto module according to some embodiments.

Referring toFIG.3A, a security circuit130may include a key generator131-1and a tag generator131-2. The key generator131-1may be implemented to receive an encrypted key and generate a session key. The session key may be an n-bit session key. The encrypted key may be transmitted from the controller200. In an embodiment, the encrypted key may be included in a cipher text CT as described with respect toFIG.1. The encrypted key may be decrypted by a private key of an image sensor100. In this case, the private key may be loaded from the NVM160in the image sensor100during the decryption operation. In addition, the key generator131-1may include a DPA processor132-1that prevents exposure of the private key or the session key therein using a random number RN.

The tag generator131-2may be implemented to receive image data IMG and the session key, and to generate a tag corresponding to the image data IMG. In this case, the image data IMG may be received from a signal processor120(refer toFIG.1). The session key may be received from the key generator131-1. Also, the tag generator131-2may include a DPA processor132-2that prevents exposure of the session key therein using a random number RN during a tag generation operation.

A security circuit according to some embodiments may load a encoded private key to prevent a DPA attack from the NVM, and may restore the loaded encoded private key to use the restored private key for the decryption operation of the cipher text CT.

Referring toFIG.3B, a security circuit130amay include the key generator131-1, the tag generator131-2, and a private key generator133. The private key generator133may be implemented to load a encoded private key from a NVM160during a decryption operation, and restore the loaded encoded private key to generate a private key. The remaining elements of the security circuit130aare similar in structure and function to like elements of the security circuit130ofFIG.3A, and thus a repeated description thereof is omitted for conciseness.

FIGS.4A,4B, and4Care views illustrating a method for generating a random number for performing a DPA countermeasures operation in a security circuit according to some embodiments.

Referring toFIG.4A, during a decryption operation of a cipher text CT, a random number generator140may be implemented to generate a random number RN for protecting a private key from a DPA attack, and provide the random number RN to a secure circuit130. In an embodiment, the random number generator140may be implemented as a true random number generator. The true random number generator may generate a random number, which may not have periodicity and regularity. In another embodiment, the random number generator140may be implemented as a pseudo-random number generator.

In general, a cipher text may be data acquired by applying various security algorithms to a plain text in a controller. Therefore, the cipher text itself may be guaranteed to have randomness. In particular, in specific security algorithms such as RAS encryption scheme (RSAES)-optimal asymmetric encryption padding (OAEP) or elliptic curve cryptography (ECC), an SHA function may be used during an encryption operation. In this case, even when plain texts, which are identical to each other, are encrypted, cipher texts to be generated are different from each other. For example, randomness may be already included at the time the cipher texts are generated.

In general, a cipher text may be generated by encrypting a plain text (original data) in a host through a security algorithm (e.g., RSA, ECC) or the like. During an encryption operation, unless a key is leaked, a third party cannot extract the plain text from the cipher text. During the encryption operation, randomness may be given to the cipher text in the host. In particular, even when the encryption operation is performed by repeating the same plain text, randomness may be provided at each execution time of the encryption operation. Therefore, cipher texts generated every time from the same plain text may have different values. For example, when a plain text of “0x01234567” is encrypted at a first time point with a key (A), a cipher text of “0x373a8897” may be generated. When a plain text of “0x01234567”, which is identical to the above, is encrypted at a second time point with the key (A), a cipher text of “0x0a7c674d” may be generated.

The security circuit130may include an entropy spreader that generates an index for extracting randomness of the cipher text CT.

Referring toFIG.4B, a pseudo-random number generator140amay be implemented to generate a random number RN using randomness of a cipher text CT.

Referring toFIG.4C, a pseudo-random number generator140bmay be implemented to select a portion of a cipher text CT, according to a value of an index IND, to generate a random number RN. In this case, the index IND may be generated by an entropy spreader150. In this case, the entropy spreader150may include a circuit for generating an index IND for extracting a random number from a cipher text in a system. The entropy spreader150may be implemented to receive the cipher text CT and generate the index IND for extracting randomness of the cipher text CT.

FIGS.5A and5Bare views illustrating a process for generating a random number from a cipher text CT using an entropy spreader according to some embodiments. As illustrated inFIG.5A, a cipher text CT may include a plurality of divided data (CT_1, CT_2, CT_3, CT_4, . . . , CT_n, where n is an integer of 2 or more). In some embodiments, sizes of the divided data CT_1, . . . , CT_n may be equal to each other. In other embodiments, sizes of the divided data CT_1, . . . , CT_n may be different from each other. In some embodiments, at least two of the divided data CT_1, . . . , CT_n may share some bits. As illustrated inFIG.5B, an entropy spreader150may be implemented to generate an index IND. A pseudo-random number generator140bmay include a multiplexer141that selects one of divided data CT_1, . . . , CT_n as a random number RN according to the index IND.

An entropy spreader according to some embodiments may be implemented in various manners.

FIGS.6A,6B, and6Care views illustrating examples of an entropy spreader according to some embodiments.

Referring toFIG.6A, an entropy spreader150may be implemented using a temperature sensor151. The temperature sensor151may output an index IND having a plurality of bits. In an embodiment, the temperature sensor151may be disposed inside an image sensing circuit110(refer toFIG.1) or outside the image sensing circuit110. The entropy spreader150may directly use temperature information sensed from the temperature sensor151as the index IND.

As illustrated inFIG.6A, the entropy spreader150uses the temperature information as it is, as the index IND. It should be understood that embodiments are not limited thereto. An entropy spreader may change detected temperature information and use the changed temperature information as the index IND.

Referring toFIG.6B, an entropy spreader150amay include a temperature sensor151and an index encoder152. The index encoder152may be implemented to receive temperature information of the temperature sensor151, and output an index IND having a plurality of bits corresponding to the temperature information.

An entropy spreader according to various embodiments may be implemented using a pseudo-random number generator PRNG. In this case, the pseudo-random number generator PRNG may be implemented in various manners.

Referring toFIG.6C, an entropy spreader150bmay be implemented using a block cipher-based pseudo-random number generator BPRNG. The entropy spreader150bmay output an index IND by using an initial vector IV and keys ki and ki* of an image sensor100(seeFIG.1) to perform block encryption operations E1and E2a predetermined number of times. In this case, the initial vector IV may be a cipher text CT.

In an embodiment, the block cipher-based pseudo-random number generator may be implemented using an internal block encryption algorithm of a security circuit130(refer toFIG.1). For example, the block cipher-based pseudo-random number generator may be implemented in software and/or firmware. In another embodiment, the entropy spreader may generate an index using a hash algorithm. An entropy spreader according to some embodiments may generate an index using a cipher text and an encryption algorithm.

FIGS.7A,7B, and7Care views illustrating a process for selecting a random number from a cipher text using an entropy spreader according to some embodiments.

Referring toFIG.7A, the entropy spreader150amay be implemented using the temperature sensor151. The entropy spreader150amay perform an XOR operation on internal bits of an output value (e.g., “00000010”) of the temperature sensor151, according to a predetermined order, to generate an index IND. According to the index IND, a portion (e.g., BC . . . BAE8) of a cipher text may be selected as a random number RN. A method of outputting the index IND using the temperature sensor151may generate a limited random number due to temperature characteristics.

Referring toFIG.7B, the entropy spreader150bmay be implemented using a block cipher-based pseudo-random number generator153(BPRNG). The block cipher-based pseudo-random number generator153may generate a static random number using the block pseudo-random number.

The entropy spreaders illustrated inFIGS.7A and7Bmay use a value output from a specific block in a system as it is, and as a seed (or an index) of a random number. However, embodiments are not be limited thereto. An entropy spreader according to various embodiments may extract a random number using a cipher text.

Referring toFIG.7C, an entropy spreader150cmay extract an index IND from a cipher text received from a controller200(refer toFIG.1). In this case, the extracted index IND may be a pure random number due to usage of the cipher text.

FIGS.8A and8Bare views illustrating a process for transferring a private key used in a DPA countermeasure module according to some embodiments.

Referring toFIG.8A, an NVM160may store a public key and an encoded private key of an image sensor100. According to an authentication request of the controller200, the public key of the image sensor100may be transmitted from the NVM160to the controller200. In addition, for decryption of a cipher text CT, the encoded private key of the image sensor100may be loaded into a security circuit130from the NVM160. The security circuit130may include the DPA countermeasure module132and the private key generator133. The private key generator133may read the encoded private key from the NVM160every time the image sensor100boots, and may decode the read encoded private key, according to a predetermined method, to generate a private key. The security circuit130may perform a decryption operation of the cipher text CT using the private key restored by the private key generator133.

In addition, the security circuit130may prevent a DPA attack on the private key using the DPA countermeasure module132during the decryption operation using the private key. For example, the DPA countermeasure module132may protect the private key by a masking technique using a random number. In general, a masking technique may perform a masking operation before an encryption operation to randomize an input to be used in the encryption operation, and may further perform an unmasking operation after the encryption operation to derive an equivalent operation result as a result.

An NVM according to some embodiments may store a private key, instead of an encoded private key. Referring toFIG.8B, an NVM160amay store a public key and a private key. A security circuit130amay read the private key stored in the NVM160aevery time an image sensor100boots, and may perform a DPA security module132using the private key.

FIGS.9A and9Bare views illustrating a process for using a private key used in DPA countermeasures according to some embodiments.

Referring toFIG.9A, a factory hardware security module (HSM) may generate a private key corresponding to an image sensor100. A self-recursive encoder300may be implemented to divide data of a predetermined unit of the private key generated in the factory HSM, and store one of the divided data (e.g., first data of “10010010”) as a seed value in an NVM160. In this case, the predetermined unit may be a byte or a word unit. In addition, after the seed value, the self-recursive encoder300may be implemented to perform an XOR operation on the data of a predetermined unit and an output value of a random number generator, and store the operated value in the NVM160. In this case, the random number generator may be a block cipher-based pseudo-random number generator BPRNG.

As illustrated inFIG.9A, a secure circuit130may include the crypto module131and a self-recursive decoder133a. In this case, the self-recursive decoder133amay be included in the private key generator133illustrated inFIG.1. The self-recursive decoder133amay read the seed value (e.g., “1001010”) of the private key from the NVM160, and may transmit the same to the crypto module131. In addition, the self-recursive decoder133amay sequentially read values operated in the NVM160, may perform an XOR operation on the read values and the output value of the random number generator, and transmit the operated values to the crypto module131. Therefore, the private key may be changed in manufacturing the image sensor100, may be stored in the NVM160, may be restored in booting the image sensor100, and may transmitted to the crypto module131. A private key according to some embodiments may be changed and restored in various manners.

A private key may not be changed and stored in the NVM. Referring toFIG.9B, a security circuit130amay sequentially load a private key of a predetermined unit from an NVM160aduring a security operation. The security circuit130amay read the private key stored in the NVM160a, and may perform the security operation. In this case, the security operation may be a decryption operation for a cipher text.

FIG.10Ais a view illustrating a self-recursive encoder according to some embodiments, andFIG.10Bis a view illustrating a self-recursive decoder according to some embodiments.

FIG.10Ais a view illustrating a self-recursive encoder133aaccording to some embodiments. Referring toFIG.10A, a self-recursive encoder300may include a block cipher-based pseudo-random number generator (BPRNG)310and an XOR operator320.

The block cipher-based pseudo-random number generator (BPRNG)310may receive first data (e.g., “10011010”) of a private key as a seed value. First random numbers may be generated by the block cipher-based pseudo-random number generator310using lower bit values (“1010”) among the first byte data as an index. The number of driving times of the block cipher-based pseudo-random number generator310for generating a Pt first random number among the first random numbers may be determined according to the index. For example, when the index is “1010,” the block cipher-based pseudo-random number generator310may be repeatedly driven ten (10) times to output a tenth pseudo-random number “11110100.” Subsequently, the block cipher-based pseudo-random number generator310may be repeatedly driven eleven (11) times to output an eleventh pseudo-random number “10011010.”

The index may be determined using a higher bit value of the seed value, instead of using a lower bit value (an m-bit value) of the seed value. According to an embodiment, an index may be a value corresponding to at least one bit of the seed value.

The XOR operator320may perform an XOR operation on a private key, excluding the seed value, and an XOR operation on an output value of the block cipher-based pseudo-random number generator310by in units of bytes. For example, a value of “00111100” may be output by performing an XOR operation on data of “11011000” following the seed value of the private key and an XOR operation on the tenth pseudo-random number “11110100” of the block cipher-based pseudo-random number generator310. Then, a value of “00111001” may be output by performing an XOR operation on data of “10100011” and the eleventh pseudo-random number “10011010.” As described above, an XOR operation on the divided data of the private key and an XOR operation on the first random number may be sequentially performed. In an embodiment, output values of the XOR operator320and the seed value of the private key may be stored in the NVM160.

FIG.10Bis a view illustrating a self-recursive decoder133aaccording to some embodiments. Referring toFIG.10B, a self-recursive decoder133amay include a block cipher-based pseudo-random number generator (BPRNG)133-1and an XOR operator133-2.

The block cipher-based pseudo-random number generator (BPRNG)133-1may read a seed value (e.g., “10010010”) of a private key from an NVM160, and second random numbers may be generated by the block cipher-based pseudo-random number generator133-1using the seed value as an index. The number of driving times of the block cipher-based pseudo-random number generator133-1for generating a 1stsecond random number among the second random numbers may be determined according to the index. For example, when the index is “1010,” the block cipher-based pseudo-random number generator133-1may be repeatedly driven ten (10) times to output a tenth pseudo-random number “11110100.” Subsequently, the block cipher-based pseudo-random number generator133-1may be repeatedly driven eleven (11) times to output an eleventh pseudo-random number “10011010.” As described above, the second random numbers may be output from the block cipher-based pseudo-random number generator133-1.

The XOR operator133-2may perform an XOR operation on data corresponding to a encoded private key, excluding the seed value, and an XOR operation on an output value of the block cipher-based pseudo-random number generator133-1. For example, a value “11011000” may be output by performing an XOR operation on data of the encoded private key “00101100” and an XOR operation on the tenth pseudo-random number “11100100” of the block cipher-based pseudo-random number generator133-1. A value of “10100011” may be output by performing an XOR operation on next data “00111001” of the encoded private key and an XOR operation on the eleventh pseudo-random number “10011010.” As described above, an XOR operation on the divided data of the encoded private key and an XOR operation on the second random number may be sequentially performed. In an embodiment, a private key may be restored using the seed value of the private key and the output values of the XOR operator133-2. The restored private key may be transmitted to a crypto module131.

It should be understood that a private key may be variously changed. For example, a private key according to some embodiments may be changed by performing an XOR operation without using a random number generator.

FIG.11is a view illustrating a process for transferring a private key used in DPA countermeasures according to another embodiment. Referring toFIG.11, a private key of an image sensor100bmay be generated in a factory HSM. The generated private key may be divided into a plurality of block data, and an XOR operation on each of the block data may be performed by an XOR operator410with a predetermined key value. The XOR operated block data and the key value may be stored in an NVM160bin manufacturing the image sensor100b. In a booting operation of the image sensor100b, an operation on the key value stored in the NVM160band an operation on the operated block data may be sequentially performed by the XOR operator410, to restore a private key required for an encryption operation. Therefore, the private key of the image sensor100bmay be restored. A security circuit131bmay perform a decryption operation using the restored private key.

FIG.12Ais a view illustrating a channel between an image sensor100aand a controller200asuch as ISP/AP/ECU/Host according to some embodiments. Referring toFIG.12A, image data acquired from an image sensor100amay be transmitted to a controller200athrough a camera serial interface (CSI) channel (a first channel). In an embodiment, the CSI channel may be a MIPI CSI-2 channel. In addition, a security circuit130aof the image sensor100aand a security module201a(HSM) of the controller200amay communicate data for a security operation through a side channel (a second channel). In this case, the side channel may be implemented as an I2C interface, an SPI interface, or the like.

FIG.12Bis a view illustrating a channel between an image sensor100band a controller200baccording to another embodiment. Referring toFIG.12B, an image sensor100band a controller200bmay communicate through a low voltage differential signal (LVDS) channel. A physical layer module PHY of the image sensor100bmay receive image data from an image sensing circuit110bin a CSI scheme, or may receive security-related data from a security circuit130bin a side channel manner, and the received data may be converted into serial data suitable for an LVDS scheme. In addition, the physical layer module PHY may receive data from the controller200bin the LVDS scheme, and may convert the received data in a CSI scheme or a side channel scheme. The controller200bmay include a security module201b(HSM) that performs an authentication operation with the image sensor100bin an LVDS scheme or performs an encryption/decryption operation.

FIG.13is a timing diagram illustrating a booting operation of an image sensor CIS according to some embodiments. Hereinafter, for convenience of explanation, a controller will be referred to as an ECU.

Referring toFIG.13, a booting operation may be performed when a CIS reset signal is on a high level. Through an I2C channel, an ECU may write information related to initialization operation for transmitting image to the ECU to a CIS. In this case, a security circuit in the CIS may be in an uninitialized state, and may be in standby mode. By setting image transmission, a CIS setting operation may be performed. Thereafter, as the image is transmitted to the ECU, the ECU may read a public key from the CIS for device authentication through an I2C channel, data required for device authentication (PubK, CERT_camera), and the like. Then, the ECU may write an RSA encryption code (e.g., the cipher text CT ofFIG.1) to the CIS through the I2C channel.

The CIS may be in a hardware standby state or in an idle state (IDLE), before performing the CIS setting operation. In a section of the CIS setting operation, the CIS may perform register setting for performing an image sensing operation. CIS information according to such register setting may be transmitted to the ECU. When the register setting is completed, the CIS may sense an image. The CIS may directly output an acquired first image stream to the ECU. As illustrated inFIG.10A, as the first image stream transmits, a device authentication operation may be performed. The CIS may perform a read operation for an NVM to obtain a private key PrivK. Thereafter, the CIS may transmit the private key PrivK to a key buffer of a security circuit. After that, the ECU may restore the private key PrivK processed in a DPA countermeasure module, and may send the restored private key to the key buffer of the secure circuit, and a message may be decrypted using the restored private key. Thereafter, the ECU may transmit a cipher text to the CIS. In this case, the cipher text may include a key value encrypted with a public key (PubK, CERT_camera) of the CIS. The CIS may decrypt an encryption code using the private key PrivK. Therefore, the CIS may share the key value with the ECU through an authentication operation. For performing this message decryption, the CIS may receive an encrypted cipher text encrypted with a security algorithm (e.g. RSA, ECC, . . . ) or the like from the ECU, through a command channel such as I2C, SPI, or the like. After receiving the cipher text, the CIS may restore an original message through decryption process. This restored data may include key data for CMAC, addition information for CMAC processing, or the like.

Thereafter, a tag (or a MAC value) for an image is acquired by using a CMAC key value included in a decrypted value. As illustrated inFIG.13, after the register setting of the CIS, as the image streaming is performed in the CIS, a device authentication operation (ECU: Dev. Auth) of the ECU may be performed at the same time. Therefore, a CIS booting time may be shortened.

FIG.14is a view illustrating a process for receiving data from an image sensor CIS according to some embodiments. Referring toFIG.14, a crypto module of an image sensor CIS (100inFIG.1) may load a public key and a private key according to an RSA encryption algorithm for key exchange (PKE), when a reset signal is on a high level. The crypto module of the image sensor CIS may transmit its public key to a controller ECU (200inFIG.1), and the controller ECU may transmit a cipher text through an I2C channel. In this case, the cipher text may be encrypted using the public key of the image sensor CIS. The crypto module of the image sensor CIS may decrypt a command set. In this case, the image sensor CIS may generate a random number (or random data) using the cipher text. In this case, the random number may be generated using some data of the cipher text by an entropy spreader for the cipher text. The crypto module of the image sensor CIS may decrypt the cipher text using the private key. In this case, it will be used for a random number operation for preventing a DPA attack on the private key during the decryption process. The image sensor CIS may use a decoded plain text.

FIG.15is a flowchart illustrating an operating method of an image sensor according to some embodiments. Referring toFIG.15, an image sensor may operate as follows. The image sensor100may receive a cipher text from a controller200(S110). In some embodiments, the image sensor100may receive the cipher text from an ECU. The image sensor100may generate a random number using the cipher text (S120). The image sensor100may execute DPA countermeasures using the random number (S130).

FIG.16is a flowchart illustrating an operating method of an image sensor according to some embodiments. Referring toFIG.16, an image sensor may operate as follows. The image sensor100may receive a cipher text from a controller200(S210). In some embodiments, the image sensor100may receive the cipher text from an ECU. A security circuit130of the image sensor100may read an encoded private key from an NVM, to decrypt the cipher text (S220). The security circuit130may decode the encoded private key (S230). For example, the security circuit130may decode a read private key, to restore a private key using random numbers. Then, the security circuit130may decrypt the cipher text using the decoded private key (S240).

In an embodiment, random numbers may be block cipher-based pseudo-random numbers. In an embodiment, a block cipher-based pseudo-random number generator may generate random numbers using partial information of a private key. In an embodiment, a private key may be divided into data of a predetermined unit, an index corresponding to first data, among the divided data, may be set, and a first random number among the random numbers may be generated by repeatedly driving a block cipher-based pseudo-random number generator as much as the index using the first data as a seed value. In an embodiment, an XOR operation on remaining data, except for first data, among the divided data, respectively, and an XOR operation on random numbers may be sequentially performed. In an embodiment, an NVM may store first data among data acquired by dividing a private key into data of a predetermined unit, and data, other than the first data, encoded by random numbers. In an embodiment, an XOR operation on encoded data, respectively, and an XOR operation on random numbers may be sequentially performed.

FIG.17is a flowchart illustrating an operating method of a controller according to some embodiments. Referring toFIG.17, a controller may operate as follows. The controller200may receive a public key from an image sensor100(S310). In some embodiments, the image sensor100may be a CMOS image sensor (CIS). The controller200may encrypt a session key using the public key (S320). The controller200may transmit the encrypted session key to the image sensor100(S330).

FIG.18is a ladder diagram illustrating an operation of an image processing system according to some embodiments. Referring toFIGS.1to18, an operation of an image processing system10may proceed as follows.

An image sensor CIS may transmit a public key to an ECU (S10). The ECU may encrypt a plain text using the received public key (511). The ECU may transmit a cipher text to the image sensor CIS (S12). The image sensor CIS may generate a random number using the cipher text (S13). The image sensor CIS may decrypt the cipher text using the random number and a private key (S14).

FIG.19is a ladder diagram illustrating a process for transmitting image data of an image processing system10according to some embodiments. Referring toFIGS.1to19, an image processing system10may transmit image data as follows.

An image sensor CIS may receive a power-on command from an ECU (S20). The image sensor CIS may perform a reset operation in response to the power-on command (S21). Thereafter, the image sensor CIS may transmit a public key thereof to the ECU (S22). The ECU may encrypt a code using the received public key of the image sensor CIS and an RSA algorithm (S23). It should be understood that the present inventive concept is not limited to the RSA algorithm. The present inventive concept may use an asymmetric-key encryption algorithm. The ECU may transmit an RAS encryption code (or, the cipher text CT ofFIG.1) to the image sensor CIS (S24).

The image sensor CIS may generate a random number using the RSA encryption code (S26). The image sensor CIS may extract the random number from the RAS encryption code, and input the random number into a DPA block (S27). In this case, a decrypted code may be key information used to verify integrity of an image.

The image sensor CIS may acquire a plain text from an encryption code for a tag (S28). The image sensor CIS may acquire an image IDATA from an image sensing circuit110(S28-1). The image sensor CIS may calculate a CMAC tag and a tag key using the decrypted code, e.g., key information and the acquired image IDATA (S29). The image sensor CIS may transmit the acquired image data IDATA and the CMAC tag to the controller ECU.

A DPA countermeasure module may be activated.

FIG.20is a view illustrating an image processing system20according to another embodiment. Referring toFIG.20, an image processing system20may include an image sensor100cand a controller200c. The image sensor100cfurther may include a DPA mode register139, as compared to the image sensor100ofFIG.1. The DPA mode register139may be implemented to store a DPA mode. The DPA mode may be generated, when activation of the DPA countermeasure module139in a security module201cof the controller200cis to be used.

FIGS.21A,21B, and21Care views illustrating an image sensor according to some embodiments.

Referring toFIG.21A, an image sensor1000according to some embodiments may include a first layer1100and a second layer1200provided below the first layer1100. In an embodiment, the first layer1100and the second layer1200may be stacked in a direction, perpendicular to each other. In an embodiment, the first layer1100and the second layer1200may be stacked on each other on a wafer level.

The first layer1100may include a sensing region SA provided with a plurality of pixels PX, and a first pad region PA1provided around the sensing region SA. The first pad region PA1may include a plurality of upper pads PAD, and the plurality of upper pads PAD may be connected to pads provided in a second pad region PA2and a control logic LC in the second layer1200through a via or the like. Each of the plurality of pixels PX may include a photodiode that receives light to generate an electric charge, a pixel circuit that processes the electric charge generated by the photodiode, or the like. The pixel circuit may include a plurality of transistors for outputting a voltage corresponding to the electric charge generated by the photodiode.

The second layer1200may include a plurality of elements that provide the control logic LC. The plurality of elements included in the control logic LC may provide circuits for driving the pixel circuit provided in the first layer1100, for example, a row driver, a column driver, a timing controller, and the like. The plurality of elements included in the control logic LC may be connected to the pixel circuit through the first and second pad regions PA1and PA2. The control logic LC may generate a pixel signal by obtaining a reset voltage and a pixel voltage, from the plurality of pixels PX. The control logic LC may include a security circuit CS that performs the security function described with reference toFIGS.1to18.

In an embodiment, at least one of the plurality of pixels PX may include a plurality of photodiodes disposed on the same level. Pixel signals generated from electric charges of each of the photodiodes may have a phase difference from each other, and the control logic LC may include a plurality of photodiodes included in one pixel PX. An autofocus function may be provided based on the phase difference between the pixel signals generated from the photodiodes.

Referring toFIG.21B, an image sensor1000amay further include a third layer1300provided below a second layer1200, compared to the image sensor1000illustrated inFIG.21A. In an embodiment, a first layer1100, a second layer1200, and a third layer1300may be stacked in a direction, perpendicular to each other. In an embodiment, the first layer1100and the second layer1200may be stacked on each other on a wafer level, and the third layer1300may be attached to a lower portion of the second layer1200on a chip level. In an embodiment, the first to third layers1100to1300may be provided as one semiconductor package.

The third layer1300provided below the second layer1200may include a memory chip MC, a dummy chip DC, and a protective layer EN sealing the memory chip MC and the dummy chip DC. The memory chip MC may be a dynamic random access memory (DRAM) or a static random access memory (SRAM), and the dummy chip DC may not have a function of actually storing data. The memory chip MC may be electrically connected to at least some of an element included in a control logic LC of the second layer1200by a bump, and may store information necessary to provide an autofocus function. In an embodiment, the bump may be a micro bump.

Referring toFIG.21C, an image sensor2000may include a first layer2100and a second layer2200. The first layer2100may include a sensing region SA in which a plurality of pixels PX are provided, a control logic LC in which elements for driving the plurality of pixels PX are provided, and a first pad region PA1provided around the sensing region SA and the control logic LC. The control logic LC may include a security circuit SC having a DPA countermeasure module that prevents a DPA attack on the private key, as described inFIGS.1to18.

The first pad region PA1may include a plurality of upper pads PAD. In an embodiment, the plurality of upper pads PAD may be connected to a memory chip MC provided in the second layer2200through a via or the like. The second layer2200may include a memory chip MC and a dummy chip DC, and a protective layer EN sealing the memory chip MC and the dummy chip DC.

FIG.22is a view illustrating an autonomous driving vehicle3000according to some embodiments. Referring toFIG.22, a front view camera3100, a rear view camera3200, and surround view cameras3300and3400may be implemented as the image sensors described inFIGS.1to21B. In addition, at least one of a side sensing camera, a driver monitoring camera, and an electronic mirror may be implemented as the image sensor described inFIGS.1to21C.

Various embodiments described herein may be used for autonomous driving.

FIG.23is a view illustrating an autonomous driving system4000according to some embodiments. Referring toFIG.23, an autonomous driving system4000may include an ECU4100, at least one camera4200, RIDAR/LADAR4300, at least one sensor4400, a storage device4500, and a display device4600.

The ECU4100may be connected to the at least one camera4200and the RIDAR/LADAR4300through a CSI-2 interface. In this case, the camera4200and the RIDAR/LADAR4300may be implemented to perform secure communication with the ECU4100and incapacitate a DPA attack on a private key, as described inFIGS.1to21C.

The ECU4100may be connected to the at least one sensor4400through an I2C interface. The ECU4100may be connected to the storage device4500through a universal flash storage (UFS) interface. The ECU4100may be connected to the display device4600through a display interface, such as a high definition multimedia interface (HDMI), a display serial interface (DSI), an embedded display port (eDP), or the like. The ECU4100may be connected to another ECU through a mobile industry processor interface (MIPI) A-PHY interface. It should be understood that the present inventive concept is not limited to the MIPI A-PHY interface. The ECU4100may be connected to another ECU through a MIPI C-PHY/D-PHY/M-PHY interface. The ECU4100may be connected to another domain in a vehicle through an Ethernet interface. It should be understood that the present inventive concept is not limited to the Ethernet interface. The ECU4100may be connected to other domains through various interfaces for vehicle communication (CAN, CAN-FD, LIN, FlexRay, etc.).

In general, an image sensor may perform a reset operation, may receive a cipher text encrypted from a host, and may perform a decryption operation. Random data may be required for a function of a countermeasure against an external DPA attack during such a decryption operation. An image sensor according to some embodiments may efficiently acquire such random data.

To obtain random data, a related art system may use a specific IP such as a true random number generator (TRNG) or the like. By contrast, the image sensor of various embodiments may acquire random data, used as DPA countermeasures, from encrypted data received from the host. Since a vehicle image sensor of various embodiments does not use a true random number generator (TRNG) IP, a reduction in system area may be expected by that much. In addition, it is possible to reduce possibility of leakage of a random number generator. An image sensor of various embodiments may efficiently acquire random data without using a true random number generator. It should be understood that embodiments are not limited to the image sensor. The various embodiments may be applicable to any type of electronic device that connects to a host and uses a random number to perform secure communication. For example, an electronic device according to some embodiments may be implemented to generate a random number using randomness of a cipher text of the host.

In addition, a related art system has a structure vulnerable to a DPA attack by storing the private key in the form of raw data into an NVM in a CIS. An image processing system according to some embodiments may be implemented to make an image sensor strong against the DPA attack, to prevent possibility of leaking the private key externally. An image sensor according to some embodiments may incapacitate the DPA attack on the private key. Therefore, various embodiments may improve reliability of a cyber security system of an autonomous vehicle.

The contents of the present disclosure described above may be only specific examples for carrying out the various embodiments. The embodiments include not only concrete and practically usable means, but also technical ideas, which may be abstract and conceptual ideas that may be utilized as future technologies.

An image sensor, an image processing system having the same, and an operating method of the same, according to some embodiments, may incapacitate or prevent a DPA attack against a private key.

While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.