Patent ID: 12191393

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The method and device described below uses a multi-step process for forming the epitaxial source/drain regions of a nano-FET. Generally, ends of nanostructures acting as channels for the nano-FETs are exposed and a multi-step process is performed to epitaxially grow source/drain regions from the ends of the nanostructures. The multi-step process is performed such that a first epitaxial layer grown on the ends of the nanostructures is less likely to merge between some or all of nanostructures. Subsequently, a second bottom-up growth process is used to form a second semiconductor material layer in the epitaxial source/drain region that reduces the creation of stacking fault defects in the epitaxial source/drain regions. By using the methods described below, a nano-FET can be realized that has higher current carrying capabilities, lower internal resistances, and enhanced electrical performance.

FIG.1illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) in a three-dimensional view, in accordance with some embodiments. The nano-FETs comprise nanostructures55(e.g., nanosheets, nanowire, or the like) over fins66on a substrate50(e.g., a semiconductor substrate), wherein the nanostructures55act as channel regions for the nano-FETs. The nanostructure55may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions68are disposed between adjacent fins66, which may protrude above and from between neighboring isolation regions68. Although the isolation regions68are described/illustrated as being separate from the substrate50, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fins66are illustrated as being single, continuous materials with the substrate50, the bottom portion of the fins66and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fins66refer to the portion extending between the neighboring isolation regions68.

Gate dielectric layers100are over top surfaces of the fins66and along top surfaces, sidewalls, and bottom surfaces of the nanostructures55. Gate electrodes102are over the gate dielectric layers100. Epitaxial source/drain regions92are disposed on the fins66on opposing sides of the gate dielectric layers100and the gate electrodes102.

FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A′ is along a longitudinal axis of a gate electrode102and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions92of a nano-FET. Cross-section B-B′ is perpendicular to cross-section A-A′ and is parallel to a longitudinal axis of a fin66of the nano-FET and in a direction of, for example, a current flow between the epitaxial source/drain regions92of the nano-FET. Cross-section C-C′ is parallel to cross-section A-A′ and extends through epitaxial source/drain regions of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs).

FIGS.2through20Care cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.FIGS.2through5,6A,13A,14A,15A,16A,17A,18A,19A, and20Aillustrate reference cross-section A-A′ illustrated inFIG.1.FIGS.6B,7B,8B,9B,10B,11B,11C,12B,12D,12F,12H,12I,12J,13B,14B,15B,16B,17B,18B,19B, and20Billustrate reference cross-section B-B′ illustrated inFIG.1.FIGS.7A,8A,9A,10A,11A,12A,12C,12E,12G,13C,18C,19C, and20Cillustrate reference cross-section C-C′ illustrated inFIG.1.

InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.

The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region50N may be physically separated from the p-type region50P (as illustrated by divider20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P. Although one n-type region50N and one p-type region50P are illustrated, any number of n-type regions50N and p-type regions50P may be provided.

Further inFIG.2, a multi-layer stack64is formed over the substrate50. The multi-layer stack64includes alternating layers of first semiconductor layers51A-C (collectively referred to as first semiconductor layers51) and second semiconductor layers53A-C (collectively referred to as second semiconductor layers53). For purposes of illustration and as discussed in greater detail below, the second semiconductor layers53will be removed and the first semiconductor layers51will be patterned to form channel regions of nano-FETs in the p-type region50P. Also, the first semiconductor layers51will be removed and the second semiconductor layers53will be patterned to form channel regions of nano-FETs in the n-type regions50N. Nevertheless, in some embodiments the first semiconductor layers51may be removed and the second semiconductor layers53may be patterned to form channel regions of nano-FETs in the n-type region50N, and the second semiconductor layers53may be removed and the first semiconductor layers51may be patterned to form channel regions of nano-FETs in the p-type regions50P.

The multi-layer stack64is illustrated as including three layers of each of the first semiconductor layers51and the second semiconductor layers53for illustrative purposes. In some embodiments, the multi-layer stack64may include any number of the first semiconductor layers51and the second semiconductor layers53. Each of the layers of the multi-layer stack64may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layers51may be formed of a first semiconductor material suitable for p-type nano-FETs, such as silicon germanium, germanium tin, or the like, and the second semiconductor layers53may be formed of a second semiconductor material suitable for n-type nano-FETs, such as silicon, silicon carbon, or the like. The multi-layer stack64is illustrated as having a bottommost semiconductor layer suitable for p-type nano-FETs for illustrative purposes. In some embodiments, multi-layer stack64may be formed such that the bottommost layer is a semiconductor layer suitable for n-type nano-FETs.

The first semiconductor materials and the second semiconductor materials may be materials having a high-etch selectivity to one another. As such, the first semiconductor layers51of the first semiconductor material may be removed without significantly removing the second semiconductor layers53of the second semiconductor material in the n-type region50N, thereby allowing the second semiconductor layers53to be patterned to form channel regions of n-type NSFETS. Similarly, the second semiconductor layers53of the second semiconductor material may be removed without significantly removing the first semiconductor layers51of the first semiconductor material in the p-type region50P, thereby allowing the first semiconductor layers51to be patterned to form channel regions of p-type NSFETS.

Referring now toFIG.3, fins66are formed in the substrate50and nanostructures55are formed in the multi-layer stack64, in accordance with some embodiments. In some embodiments, the nanostructures55and the fins66may be formed in the multi-layer stack64and the substrate50, respectively, by etching trenches in the multi-layer stack64and the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures55by etching the multi-layer stack64may further define first nanostructures52A-C (collectively referred to as the first nanostructures52) from the first semiconductor layers51and define second nanostructures54A-C (collectively referred to as the second nanostructures54) from the second semiconductor layers53. The first nanostructures52and the second nanostructures54may further be collectively referred to as nanostructures55.

The fins66and the nanostructures55may be patterned by any suitable method. For example, the fins66and the nanostructures55may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins66.

FIG.3illustrates the fins66in the n-type region50N and the p-type region50P as having substantially equal widths for illustrative purposes. In some embodiments, widths of the fins66in the n-type region50N may be greater or thinner than the fins66in the p-type region50P. Further, while each of the fins66and the nanostructures55are illustrated as having a consistent width throughout, in other embodiments, the fins66and/or the nanostructures55may have tapered sidewalls such that a width of each of the fins66and/or the nanostructures55continuously increases in a direction towards the substrate50. In such embodiments, each of the nanostructures55may have a different width and be trapezoidal in shape.

InFIG.4, isolation regions68are formed adjacent the fins66. The isolation regions68may be formed by depositing an insulation material over the substrate50, the fins66, and nanostructures55, and between adjacent fins66. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures55. Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along a surface of the substrate50, the fins66, and the nanostructures55. Thereafter, a fill material, such as those discussed above may be formed over the liner.

A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures55. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures55such that top surfaces of the nanostructures55and the insulation material are level after the planarization process is complete.

The insulation material is then recessed to form the isolation regions68. The insulation material is recessed such that upper portions of fins66in the n-type region50N and the p-type region50P protrude from between neighboring isolation regions68. Further, the top surfaces of the isolation regions68may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the isolation regions68may be formed flat, convex, and/or concave by an appropriate etch. The isolation regions68may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the material of the fins66and the nanostructures55). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.

The process described above with respect toFIGS.2through4is just one example of how the fins66and the nanostructures55may be formed. In some embodiments, the fins66and/or the nanostructures55may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins66and/or the nanostructures55. The epitaxial structures may comprise the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together.

Additionally, the first semiconductor layers51(and resulting first nanostructures52) and the second semiconductor layers53(and resulting second nanostructures54) are illustrated and discussed herein as comprising the same materials in the p-type region50P and the n-type region50N for illustrative purposes only. As such, in some embodiments one or both of the first semiconductor layers51and the second semiconductor layers53may be different materials or formed in a different order in the p-type region50P and the n-type region50N.

Further inFIG.4, appropriate wells (not separately illustrated) may be formed in the fins66, the nanostructures55, and/or the isolation regions68. In embodiments with different well types, different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist or other masks (not separately illustrated). For example, a photoresist may be formed over the fins66and the isolation regions68in the n-type region50N and the p-type region50P. The photoresist is patterned to expose the p-type region50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in a range from about 1016atoms/cm3to about 1018atoms/cm3. After the implant, the photoresist is removed, such as by an acceptable ashing process.

Following or prior to the implanting of the p-type region50P, a photoresist or other masks (not separately illustrated) is formed over the fins66, the nanostructures55, and the isolation regions68in the p-type region50P and the n-type region50N. The photoresist is patterned to expose the n-type region50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in a range from about 1016atoms/cm3to about 1018atoms/cm3. After the implant, the photoresist may be removed, such as by an acceptable ashing process.

After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

InFIG.5, a dummy dielectric layer70is formed on the fins66and/or the nanostructures55. The dummy dielectric layer70may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer72is formed over the dummy dielectric layer70, and a mask layer74is formed over the dummy gate layer72. The dummy gate layer72may be deposited over the dummy dielectric layer70and then planarized, such as by a CMP. The mask layer74may be deposited over the dummy gate layer72. The dummy gate layer72may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer72may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer72may be made of other materials that have a high etching selectivity from the etching of isolation regions. The mask layer74may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer72and a single mask layer74are formed across the n-type region50N and the p-type region50P. It is noted that the dummy dielectric layer70is shown covering only the fins66and the nanostructures55for illustrative purposes only. In some embodiments, the dummy dielectric layer70may be deposited such that the dummy dielectric layer70covers the isolation regions68, such that the dummy dielectric layer70extends between the dummy gate layer72and the isolation regions68.

FIGS.6A through18Cillustrate various additional steps in the manufacturing of embodiment devices.FIGS.7A,8A,9A,10A,11A,12A,12C,12E,12G,13A,13C,14A,15A,18C,19C, and20Cillustrate features in either the n-type region50N or the p-type region50P. InFIGS.6A and6B, the mask layer74(seeFIG.5) may be patterned using acceptable photolithography and etching techniques to form masks78. The pattern of the masks78then may be transferred to the dummy gate layer72and to the dummy dielectric layer70to form dummy gates76and dummy gate dielectrics71, respectively. The dummy gates76cover respective channel regions of the fins66. The pattern of the masks78may be used to physically separate each of the dummy gates76from adjacent dummy gates76. The dummy gates76may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins66.

InFIGS.7A and7B, a first spacer layer80and a second spacer layer82are formed over the structures illustrated inFIGS.6A and6B, respectively. The first spacer layer80and the second spacer layer82will be subsequently patterned to act as spacers for forming self-aligned source/drain regions. InFIGS.7A and7B, the first spacer layer80is formed on top surfaces of the isolation regions68; top surfaces and sidewalls of the fins66, the nanostructures55, and the masks78; and sidewalls of the dummy gates76and the dummy gate dielectric71. The second spacer layer82is deposited over the first spacer layer80. The first spacer layer80may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer82may be formed of a material having a different etch rate than the material of the first spacer layer80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

After the first spacer layer80is formed and prior to forming the second spacer layer82, implants for lightly doped source/drain (LDD) regions (not separately illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above inFIG.4, a mask, such as a photoresist, may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins66and nanostructures55in the p-type region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins66and nanostructures55in the n-type region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in a range from about 1×1015atoms/cm3to about 1×1019atoms/cm3. An anneal may be used to repair implant damage and to activate the implanted impurities.

InFIGS.8A and8B, the first spacer layer80and the second spacer layer82are etched to form first spacers81and second spacers83. As will be discussed in greater detail below, the first spacers81and the second spacers83act to self-aligned subsequently formed source drain regions, as well as to protect sidewalls of the fins66and/or nanostructure55during subsequent processing. The first spacer layer80and the second spacer layer82may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer layer82has a different etch rate than the material of the first spacer layer80, such that the first spacer layer80may act as an etch stop layer when patterning the second spacer layer82and such that the second spacer layer82may act as a mask when patterning the first spacer layer80. For example, the second spacer layer82may be etched using an anisotropic etch process wherein the first spacer layer80acts as an etch stop layer, wherein remaining portions of the second spacer layer82form second spacers83as illustrated inFIG.8A. Thereafter, the second spacers83acts as a mask while etching exposed portions of the first spacer layer80, thereby forming first spacers81as illustrated inFIG.8A.

As illustrated inFIG.8A, the first spacers81and the second spacers83are disposed on sidewalls of the fins66and/or nanostructures55. As illustrated inFIG.8B, in some embodiments, the second spacer layer82may be removed from over the first spacer layer80adjacent the masks78, the dummy gates76, and the dummy gate dielectrics71, and the first spacers81are disposed on sidewalls of the masks78, the dummy gates76, and the dummy dielectric layers60. In other embodiments, a portion of the second spacer layer82may remain over the first spacer layer80adjacent the masks78, the dummy gates76, and the dummy gate dielectrics71.

It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the first spacers81may be patterned prior to depositing the second spacer layer82), additional spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps.

InFIGS.9A and9B, first recesses86are formed in the fins66, the nanostructures55, and the substrate50, in accordance with some embodiments. Epitaxial source/drain regions will be subsequently formed in the first recesses86. The first recesses86may extend through the first nanostructures52and the second nanostructures54, and into the substrate50. As illustrated inFIG.9A, top surfaces of the isolation regions68may be level with bottom surfaces of the first recesses86. In various embodiments, the fins66may be etched such that bottom surfaces of the first recesses86are disposed below the top surfaces of the isolation regions68; or the like. The first recesses86may be formed by etching the fins66, the nanostructures55, and the substrate50using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers81, the second spacers83, and the masks78mask portions of the fins66, the nanostructures55, and the substrate50during the etching processes used to form the first recesses86. A single etch process or multiple etch processes may be used to etch each layer of the nanostructures55and/or the fins66. Timed etch processes may be used to stop the etching of the first recesses86after the first recesses86reach a desired depth.

InFIGS.10A and10B, portions of sidewalls of the layers of nanostructures55formed of the first semiconductor materials (e.g., the first nanostructures52) exposed by the first recesses86are etched to form sidewall recesses88in the n-type region50N, and portions of sidewalls of the layers of the nano structures55formed of the second semiconductor materials (e.g., the second nanostructures54) exposed by the first recesses86are etched to form sidewall recesses88in the p-type region50P. Although sidewalls of the first nanostructures52and the second nanostructures54in sidewall recesses88are illustrated as being straight inFIG.10B, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. The p-type region50P may be protected using a mask (not shown) while etchants selective to the first semiconductor materials are used to etch the first nanostructures52such that the second nanostructures54and the substrate50remain relatively unetched as compared to the first nanostructures52in the n-type region50N. Similarly, the n-type region50N may be protected using a mask (not shown) while etchants selective to the second semiconductor materials are used to etch the second nanostructures54such that the first nanostructures52and the substrate50remain relatively unetched as compared to the second nanostructures54in the p-type region50P. In embodiments in which the first nanostructures52include, e.g., SiGe, and the second nanostructures54include, e.g., Si or SiC, a dry etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch sidewalls of the first nanostructures52in the n-type region50N, and a dry etch process with hydrogen fluoride, another fluorine-based gas, or the like may be used to etch sidewalls of the second nanostructures54in the p-type region50P.

InFIGS.11A-11C, first inner spacers90are formed in the sidewall recess88. The first inner spacers90may be formed by depositing an inner spacer layer (not separately illustrated) over the structures illustrated inFIGS.10A and10B. The first inner spacers90act as isolation features between subsequently formed source/drain regions and a gate structure. As will be discussed in greater detail below, source/drain regions will be formed in the first recesses86, while the first nanostructures52in the n-type region50N and the second nanostructures54in the p-type region50P will be replaced with corresponding gate structures.

The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the first inner spacers90. Although outer sidewalls of the first inner spacers90are illustrated as being flush with sidewalls of the second nanostructures54in the n-type region50N and flush with the sidewalls of the first nanostructures52in the p-type region50P, the outer sidewalls of the first inner spacers90may extend beyond or be recessed from sidewalls of the second nanostructures54and/or the first nanostructures52, respectively.

Moreover, although the outer sidewalls of the first inner spacers90are illustrated as being straight inFIG.11B, the outer sidewalls of the first inner spacers90may be concave or convex. As an example,FIG.11Cillustrates an embodiment in which sidewalls of the first nanostructures52are concave, outer sidewalls of the first inner spacers90are concave, and the first inner spacers are recessed from sidewalls of the second nanostructures54in the n-type region50N. Also illustrated are embodiments in which sidewalls of the second nanostructures54are concave, outer sidewalls of the first inner spacers90are concave, and the first inner spacers are recessed from sidewalls of the first nanostructures52in the p-type region50P. The inner spacer layer may be etched by an anisotropic etching process, such as RIE, NBE, or the like. The first inner spacers90may be used to prevent damage to subsequently formed source/drain regions (such as the epitaxial source/drain regions92, discussed below with respect toFIGS.12A-12H) by subsequent etching processes, such as etching processes used to form gate structures.

InFIGS.12A-12H, epitaxial source/drain regions92(collectively referring to a first semiconductor material layer92A, a second semiconductor material layer92B, and a third semiconductor material layer92C) are formed in the first recesses86. In some embodiments, the epitaxial source/drain regions92may exert stress on the second nanostructures54in the n-type region50N and on the first nanostructures52in the p-type region50P, thereby improving performance. As illustrated inFIGS.12B,12D,12F, and12Hthe epitaxial source/drain regions92are formed in the first recesses86such that each dummy gate76is disposed between respective neighboring pairs of the epitaxial source/drain regions92. In some embodiments, the first spacers81are used to separate the epitaxial source/drain regions92from the dummy gates76and the first inner spacers90are used to separate the epitaxial source/drain regions92from the nanostructures55by an appropriate lateral distance so that the epitaxial source/drain regions92do not short out with subsequently formed gates of the resulting nano-FETs.

The epitaxial source/drain regions92in the p-type region50P, e.g., the PMOS region, may be formed by masking the n-type region50N, e.g., the NMOS region. Then, the epitaxial source/drain regions92are epitaxially grown in the first recesses86in the p-type region50P. The epitaxial source/drain regions92may include any acceptable material appropriate for p-type nano-FETs. For example, if the first nanostructures52are silicon germanium, the epitaxial source/drain regions92may comprise materials exerting a compressive strain on the first nanostructures52, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions92may also have surfaces raised from respective surfaces of the nanostructures55and may have facets.

The epitaxial source/drain regions92and the first nanostructures52, and/or the substrate50may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The p-type dopants for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions92may be in situ doped during growth.

In the embodiment shown inFIGS.12A and12B, with respect to the p-type region50P, a first semiconductor material layer92A of epitaxial source/drain regions92is grown from the substrate and exposed portions of the first nanostructures52to a thickness T1 in a range of about 2 nanometers (nm) to about 6 nm. In this embodiment, the first semiconductor material layer92A is formed from Si1-X_L1Gex_L1, wherein x_L1 is between 0.1 and 0.4, such as 0.4, and doped with an impurity suitable for p-type source/drain regions, such as boron, with a doping concentration between 1×1020atoms/cm3and 5×1020atoms/cm3, such as 5×1020atoms/cm3.

In some embodiments a CVD process is used to epitaxially grow first semiconductor material layer92A where nitrogen is used to purge an epitaxial reactor of air. The reactor is then heated to between 550° C. and 650° C. In some embodiments, after temperatures have stabilized in the range, a germanium-containing precursor gas such as germane (GeH4), and a silicon-containing precursors such as silane (SiH4), disilane (Si2H6), or dichlorosilane (DCS), are introduced into the reactor at a flow rate between 100 and 300 standard cubic centimeters per minute (sccm) for GeH4, and at a flow rate between 20 and 150 sccm for DCS, SiH4, or Si2H6, for between 2 and 5 minutes, to form a first semiconductor material layer92A between about 2 nm and about 6 mn thick. In some embodiments, a carrier gas such as hydrogen, argon, or the like, is also added. In some embodiments, a boron-containing gas such as diborane (B2H6) is further injected into the reactor at a flow rate between 20 and 150 sccm. In some embodiments, the boron-containing gas is injected to achieve in-situ boron doping of the first semiconductor material layer92A with a doping concentration between 1×1020atoms/cm3and 5×1020atoms/cm3, such as 5×1020atoms/cm3. In some embodiments, and etching gas such as hydrochloric acid (HCl) or chlorine (Cl2) may be injected into the reactor with the process gases at a flow rate between 50 and 200 sccm to remove amorphous SiGe grown on dielectrics without significantly etching epitaxial SiGe as the etching rate will not exceed the deposition growth rate for the flow rates indicated.

In the embodiment shown inFIGS.12C and12D, a second semiconductor material layer92B of epitaxial source/drain region92is grown up from the substrate50, to cover the first semiconductor material layer92A and substantially fill first recesses86in the p-type region50P. In some embodiments, the second semiconductor material layer92B is also formed from boron doped silicon-germanium, but with a doping concentration between 5×1020atoms/cm3and 10×1020atoms/cm3, and greater than the doping concentration of the first semiconductor material layer92A. In some embodiments the second semiconductor material layer92B of epitaxial source/drain region92is grown through a CVD process controlling the concentration of germanium in the CVD process for a bottom-up growing pattern. Using such a bottom-up growing mechanism for the second semiconductor material layer92B of epitaxial source/drain region92has been noted to achieve fewer stacking fault defects in epitaxial source/drain region92. In some embodiments, the second semiconductor material layer92B is Si1-x_L2Gex_L2, wherein 0.2≤x_L2≤0.9, and with a germanium atomic percentage greater than that of the first semiconductor material layer92A.

In some embodiments a CVD process is used to epitaxially grow the second semiconductor material layer92B as a continuation of the epitaxial process for growing the first semiconductor material layer92A, where the temperatures and flow rates of the component gases are controlled to achieve a bottom-up growth of the second semiconductor material layer92B. In some embodiments, the reactor temperature is changed to between 550° C. and 650° C., the precursor gas GeH4flow rate is set between 100 and 500 sccm, and precursor gases DCS, SiH4or Si2H6are sequentially pulsed into the chamber at a flow rate between 20 and 50 sccm for between 3 and 5 minutes to grow the second semiconductor material layer92B in a bottom-up manner. In some embodiments, a boron-containing gas such as B2H6is further injected into the reactor at a flow rate between 150 and 300 sccm. In some embodiments, the boron-containing gas is injected to achieve in-situ boron doping of the second semiconductor material layer92B with a doping concentration between 5×1020atoms/cm3and 10×1020atoms/cm3, and greater than the doping concentration of the first semiconductor material layer92A In some embodiments, and etching gas such as HCl or Cl2may be injected into the reactor at a flow rate between 150 and 250 sccm to remove amorphous SiGe grown on dielectrics without etching epitaxial SiGe as the etching rate will not exceed the deposition rate for the flow rates indicated.

In some embodiments, as shown inFIGS.12E and12F, further layers of semiconductor material, for example, a third semiconductor material layer92C is grown over the second semiconductor material layer92B to complete the formation of epitaxial source/drain regions92in the p-type region50P. These further layers of semiconductor material may be formed from Si1-x_L3Gex_L3, wherein 0.1≤x_L3≤0.25, and lower than that of the first semiconductor material layer92A. In some embodiments the further layers of semiconductor material may be formed of other materials than that used to grow the first semiconductor material layer92A and second semiconductor material layer92B. In some embodiments the third semiconductor material layer92C is 2 to 4 nm thick and acts as a protective barrier for the second semiconductor material layer92B during subsequent wet etches.

In some embodiments a CVD process is used to epitaxially grow the subsequent third semiconductor material layer92C as a continuation of the epitaxial process for growing the second semiconductor material layer92B and first semiconductor material layer92A. In some embodiments, the reactor temperature is changed to between 580° C. and 650° C., the precursor gas GeH4flow rate is set between 150 and 300 sccm, and precursor gas DCS flow rate is set between 30 and 50 sccm for between 2 and 4 minutes to grow the subsequent third semiconductor material layer92C, and finish growing epitaxial source/drain region92. In some embodiments, a boron-containing gas such as B2H6is further injected into the reactor at a flow rate between 20 and 80 sccm. In some embodiments, the boron-containing gas is injected to achieve in-situ boron doping of the third semiconductor material layer92C with a doping concentration of between 6×1019atoms/cm3and 2×1020atoms/cm3, and lower than that of the first semiconductor material layer92A. In some embodiments, and etching gas such as HCl or Cl2may be injected into the reactor at a flow rate between 50 and 100 sccm to remove amorphous SiGe grown on dielectrics without etching epitaxial SiGe as the etching rate will not exceed the deposition rate for the flow rates indicated.

As discussed in greater detail below, the epitaxial source/drain regions92in the n-type region50N, e.g., the NMOS region, may be formed by masking the p-type region50P, e.g., the PMOS region. Then, the epitaxial source/drain regions92are epitaxially grown in the first recesses86in the n-type region50N. The epitaxial source/drain regions92may include any acceptable material appropriate for n-type nano-FETs. For example, if the second nanostructures54are silicon, the epitaxial source/drain regions92may include materials exerting a tensile strain on the second nanostructures54, such as silicon, carbon-doped silicon (SiC), phosphorous and carbon doped silicon (SiCP), silicon phosphide (SiP), or the like. The epitaxial source/drain regions92may have surfaces raised from respective upper surfaces of the nanostructures55and may have facets.

In some embodiments a CVD process is used to epitaxially grow first semiconductor material layer92A in the n-type region50N, where nitrogen is used to purge an epitaxial reactor of air. The reactor is then heated to between 580° C. and 700° C. In some embodiments, after temperatures have stabilized in the range, a carbon-containing precursor gas such as propane (C3H8) and ethylene (C2H4), and a silicon-containing precursor such as DCS, SiH4, or Si2H6, are introduced into the reactor. In an embodiment where C3H8or C2H4and DCS, SiH4, or Si2H6, are the precursor gasses used, C3H8or C2H4is injected into the reactor at a flow rate between 20 and 250 sccm, and DCS, SiH4, or Si2H6, is injected at a flow rate between 100 and 900 sccm, for between 1 and 10 minutes, to form a first semiconductor material layer92A between 2 nm and 6 mn thick. In some embodiments, a carrier gas such as hydrogen, argon, or the like is also added. In some embodiments, a phosphorous-containing gas such as phosphine (PH3) is further injected into the reactor at a flow rate between 50 and 300 sccm. In some embodiments, the phosphorous-containing gas is injected to achieve in-situ phosphorous doping of the first semiconductor material layer92A with a doping concentration between 1×1020atoms/cm3and 4×1020atoms/cm3, such as 4×1020atoms/cm3In some embodiments, and etching gas such as HCl or Cl2may be injected into the reactor at a flow rate between 20 and 150 sccm to remove amorphous SiC grown on dielectrics without significantly etching epitaxial SiC as the etching rate will not exceed the deposition growth rate for the flow rates indicated.

A second semiconductor material layer92B of epitaxial source/drain region92is grown up from the substrate50, to cover the first semiconductor material layer92A and substantially fill first recesses86in the n-type region50N. In some embodiments, the second semiconductor material layer92B is also formed from phosphorous and carbon doped silicon, but with a phosphorous doping concentration greater than 7×1020atoms/cm3, and greater than the phosphorous doping concentration of the first semiconductor material layer92A. In some embodiments the second semiconductor material layer92B of epitaxial source/drain region92is grown through a CVD process controlling the concentration of carbon in the CVD process for a bottom-up growing pattern. Using such a bottom-up growing mechanism for the second semiconductor material layer92B of epitaxial source/drain region92has been noted to achieve fewer stacking fault defects in epitaxial source/drain region92of the n-type region50N. In some embodiments, the second semiconductor material layer92B is Si1-x_L2Cx_L2, wherein 0.2≤x_L2≤0.9, and with a carbon atomic percentage greater than that of the first semiconductor material layer92A.

In some embodiments a CVD process is used to epitaxially grow the second semiconductor material layer92B as a continuation of the epitaxial process for growing the first semiconductor material layer92A, where the temperatures and flow rates of the component gases are controlled to ensure a bottom-up growth of the second semiconductor material layer92B. In some embodiments, the reactor temperature is changed to between 580° C. and 700° C., the precursor gas C3H8or C2H4flow rate is set between 100 and 250 sccm, and precursor gas DCS, SiH4, or Si2H6, flow rate is set between 100 and 900 sccm for between 5 and 15 minutes to grow the second semiconductor material layer92B in a bottom-up manner. In some embodiments, a phosphorous-containing gas such as PH3is further injected into the reactor at a flow rate between 50 and 500 sccm. In some embodiments, the phosphorous—containing gas is injected to achieve in-situ phosphorous doping of the second semiconductor material layer92B with a phosphorous doping concentration greater than 7×1020atoms/cm3, and greater than the phosphorous doping concentration of the first semiconductor material layer92A In some embodiments, and etching gas such as HCl or Cl2may be injected into the reactor at a flow rate between 20 and 200 sccm to remove amorphous SiC grown on dielectrics without etching epitaxial SiC as the etching rate will not exceed the deposition rate for the flow rates indicated.

In some embodiments, further layers of semiconductor material, for example, a third semiconductor material layer92C is grown over the second semiconductor material layer92B to complete the formation of epitaxial source/drain regions92in the n-type region50N. These further layers of semiconductor material may be formed from Si1-x_L3Cx_L3, wherein 0≤x_L3≤10. In some embodiments the further layers of semiconductor material may be formed of other materials than that used to grow the first semiconductor material layer92A and second semiconductor material layer92B.

In some embodiments a CVD process is used to epitaxially grow the subsequent third semiconductor material layer92C as a continuation of the epitaxial process for growing the second semiconductor material layer92B and first semiconductor material layer92A. In some embodiments, the reactor temperature is changed to between 580° C. and 900° C., the precursor gas C3H8or C2H4flow rate is set between 20 and 100 sccm, and precursor gas DCS, SiH4, or Si2H6, flow rate is set between 50 and 500 sccm, for between 10 and 20 minutes to grow the subsequent third semiconductor material layer92C, and finish growing epitaxial source/drain region92. In some embodiments, a phosphorous-containing gas such as PH3is further injected into the reactor at a flow rate between 20 and 100 sccm. In some embodiments, the phosphorous-containing gas is injected to achieve in-situ phosphorous doping of the third semiconductor material layer92C with a phosphorous doping concentration of between 1×1020atoms/cm3and 4×1020atoms/cm3In some embodiments, and etching gas such as HCl or Cl2may be injected into the reactor at a flow rate between 50 and 200 sccm to remove amorphous SiC grown on dielectrics without etching epitaxial SiC as the etching rate will not exceed the deposition rate for the flow rates indicated.

The end-wall shape of the first nanostructures52in the p-type region50P or the second nanostructures54in the n-type region50N are shown as being rectangular for illustrative purposes. In some embodiments, the end-wall shapes of the first nanostructures52in the p-type region50P and/or the second nanostructures54in the n-type region50N may be other shapes, such as convex (FIG.12I) or concave (FIG.12J), or any other shape.

Using the above outlined process, it has been noted that the first semiconductor material layer92A is less likely to merge over the first inner spacers90between adjacent first nanostructures52, such that the first semiconductor layer92A comprises a plurality of segments as illustrated inFIG.12B. For example, partial non-merger may be achieved, as shown on the right pillar of the p-type region50P inFIG.12Bwhere the first semiconductor material layer92A has only merged across first inner spacer90on the left side of52C and52B. Alternatively, full non-merger may be achieved, such as is shown on the left pillar of the p-type region50P inFIG.12Bwhere no merger of the first semiconductor material layer92A is shown across any first inner spacer90. By reducing or preventing the merger of the first semiconductor material layer92A, the second semiconductor material layer92B will have a larger volume for the same semiconductor design, thus reducing the resistivity of the epitaxial source/drain region92overall. Further, the process has been shown to result in fewer defect stacking fault creations in epitaxial source/drain region92than if a bottom-up growth process was not used. By minimizing or reducing defect stacking faults and reducing mergers of the first semiconductor material layer92A across first inner spacers90to increase the volume of the second semiconductor material layer92B, the nano-FETs exhibit lower resistivity, and higher current carrying capacity, from the epitaxial source/drain region92, to the channel formed by the first nanostructures52(in the p-type region50P) and second nanostructures54(in the n-type region50N). Thus, the nano-FET capacity and electrical performance is improved.

As a result of the epitaxy processes used to form the epitaxial source/drain regions92in the n-type region50N and the p-type region50P, upper surfaces of the epitaxial source/drain regions92have facets which expand laterally outward beyond sidewalls of the nanostructures55. In some embodiments, these facets cause adjacent epitaxial source/drain regions92of a same NSFET to merge as illustrated byFIGS.12C and12E. In other embodiments, adjacent epitaxial source/drain regions92remain separated after the epitaxy process is completed as illustrated byFIG.12G. In the embodiments illustrated inFIGS.12A,12C,12E, and12G, the first spacers81may be formed to a top surface of the isolation regions68thereby blocking the epitaxial growth. In some other embodiments, the first spacers81may cover portions of the sidewalls of the nanostructures55further blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers81may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the isolation region68.

FIG.12Hillustrates an embodiment in which sidewalls of the first nanostructures52in the n-type region50N and sidewalls of the second nanostructures54in the p-type region50P are concave, outer sidewalls of the first inner spacers90are concave, and the first inner spacers90are recessed from sidewalls of the second nanostructures54and the first nanostructures52, respectively. As illustrated inFIG.12H, the epitaxial source/drain regions92may be formed in contact with the first inner spacers90and may extend past sidewalls of the second nanostructures54in the n-type region50N and past sidewalls of the first nanostructures52in the p-type region50P.

InFIGS.13A-13C, a first interlayer dielectric (ILD)96is deposited over the structure illustrated inFIGS.6A,12H, and12G(the processes ofFIGS.7A-12Hdo not alter the cross-section illustrated inFIGS.6A), respectively. The first ILD96may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)94is disposed between the first ILD96and the epitaxial source/drain regions92, the mask78, and the first spacers81. The CESL94may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD96.

InFIGS.14A-14C, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD96with the top surfaces of the dummy gates76or the masks78. The planarization process may also remove the masks78on the dummy gates76, and portions of the first spacers81along sidewalls of the masks78. After the planarization process, top surfaces of the dummy gates76, the first spacers81, and the first ILD96are level within process variations. Accordingly, the top surfaces of the dummy gate76are exposed through the first ILD96. In some embodiments, the masks78may remain, in which case the planarization process levels the top surface of the first ILD96with top surface of the masks78and the first spacers81.

InFIGS.15A and15B, the dummy gate76, and the mask78if present, are removed in one or more etching steps, so that second recesses98are formed. Portions of the dummy gate dielectrics71in the second recesses98are also be removed. In some embodiments, the dummy gate76and the dummy dielectrics layers60are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gate76at a faster rate than the first ILD96or the first spacers81. Each second recess98exposes and/or overlies portions of nanostructures55, which act as channel regions in subsequently completed nano-FETs. Portions of the nanostructures55which act as the channel regions are disposed between neighboring pairs of the epitaxial source/drain regions92. During the removal, the dummy dielectric layers60may be used as etch stop layers when the dummy gate76is etched. The dummy dielectric layers60may then be removed after the removal of the dummy gate76.

InFIGS.16A and16B, the first nanostructures52in the n-type region50N and the second nanostructures54in the p-type region50P are removed extending the second recesses98. The first nanostructures52may be removed by forming a mask (not shown) over the p-type region50P and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the first nanostructures52, while the second nanostructures54, the substrate50, the isolation regions68remain relatively unetched as compared to the first nanostructures52. In embodiments in which the first nanostructures52include, e.g., SiGe, and the second nanostructures54A-54C include, e.g., Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructures52in the n-type region50N.

The second nanostructures54in the p-type region50P may be removed by forming a mask (not shown) over the n-type region50N and performing an isotropic etching process such as wet etching or the like using etchants which are selective to the materials of the second nanostructures54, while the first nanostructures52, the substrate50, the isolation regions68remain relatively unetched as compared to the second nanostructures54. In embodiments in which the second nanostructures54include, e.g., SiGe, and the first nanostructures52include, e.g., Si or SiC, hydrogen fluoride, another fluorine-based gas, or the like may be used to remove the second nanostructures54in the p-type region50P.

InFIGS.17A and17B, gate dielectric layers100and gate electrodes102are formed for replacement gates. The gate dielectric layers100are deposited conformally in the second recesses98. In the n-type region50N, the gate dielectric layers100may be formed on top surfaces and sidewalls of the substrate50and on top surfaces, sidewalls, and bottom surfaces of the second nanostructures54, and in the p-type region50P, the gate dielectric layers100may be formed on top surfaces and sidewalls of the substrate50and on top surfaces, sidewalls, and bottom surfaces of the first nanostructures52. The gate dielectric layers100may also be deposited on top surfaces of the first ILD96, the CESL94, the first spacers81, and the isolation regions68.

In accordance with some embodiments, the gate dielectric layers100comprise one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. For example, in some embodiments, the gate dielectrics may comprise a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers100include a high-k dielectric material, and in these embodiments, the gate dielectric layers100may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers100may be the same or different in the n-type region50N and the p-type region50P. The formation methods of the gate dielectric layers100may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

The gate electrodes102are deposited over the gate dielectric layers100, respectively, and fill the remaining portions of the second recesses98. The gate electrodes102may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although single layer gate electrodes102are illustrated inFIGS.17A and17B, the gate electrodes102may comprise any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers which make up the gate electrodes102may be deposited in the n-type region50N between adjacent ones of the second nanostructures54and between the second nanostructure54A and the substrate50, and may be deposited in the p-type region50P between adjacent ones of the first nanostructures52.

The formation of the gate dielectric layers100in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectric layers100in each region are formed from the same materials, and the formation of the gate electrodes102may occur simultaneously such that the gate electrodes102in each region are formed from the same materials. In some embodiments, the gate dielectric layers100in each region may be formed by distinct processes, such that the gate dielectric layers100may be different materials and/or have a different number of layers, and/or the gate electrodes102in each region may be formed by distinct processes, such that the gate electrodes102may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

After the filling of the second recesses98, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers100and the material of the gate electrodes102, which excess portions are over the top surface of the first ILD96. The remaining portions of material of the gate electrodes102and the gate dielectric layers100thus form replacement gate structures of the resulting nano-FETs. The gate electrodes102and the gate dielectric layers100may be collectively referred to as “gate structures.”

InFIGS.18A-18C, the gate structure (including the gate dielectric layers100and the corresponding overlying gate electrodes102) is recessed, so that a recess is formed directly over the gate structure and between opposing portions of first spacers81. A gate mask104comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD96. Subsequently formed gate contacts (such as the gate contacts114, discussed below with respect toFIGS.23A and23B) penetrate through the gate mask104to contact the top surface of the recessed gate electrodes102.

As further illustrated byFIGS.18A-18C, a second ILD106is deposited over the first ILD96and over the gate mask104. In some embodiments, the second ILD106is a flowable film formed by FCVD. In some embodiments, the second ILD106is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like.

InFIGS.19A-19C, the second ILD106, the first ILD96, the CESL94, and the gate masks104are etched to form third recesses108exposing surfaces of the epitaxial source/drain regions92and/or the gate structure. The third recesses108may be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the third recesses108may be etched through the second ILD106and the first ILD96using a first etching process; may be etched through the gate masks104using a second etching process; and may then be etched through the CESL94using a third etching process. A mask, such as a photoresist, may be formed and patterned over the second ILD106to mask portions of the second ILD106from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the third recesses108extend into the epitaxial source/drain regions92and/or the gate structure, and a bottom of the third recesses108may be level with (e.g., at a same level, or having a same distance from the substrate), or lower than (e.g., closer to the substrate) the epitaxial source/drain regions92and/or the gate structure. AlthoughFIG.19Billustrate the third recesses108as exposing the epitaxial source/drain regions92and the gate structure in a same cross section, in various embodiments, the epitaxial source/drain regions92and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts. After the third recesses108are formed, silicide regions110are formed over the epitaxial source/drain regions92. In some embodiments, the silicide regions110are formed by first depositing a metal (not shown) capable of reacting with the semiconductor materials of the underlying epitaxial source/drain regions92(e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys, over the exposed portions of the epitaxial source/drain regions92, then performing a thermal anneal process to form the silicide regions110. The un-reacted portions of the deposited metal are then removed, e.g., by an etching process. Although silicide regions110are referred to as silicide regions, silicide regions110may also be germanide regions, or silicon germanide regions (e.g., regions comprising silicide and germanide). In an embodiment, the silicide region110comprises TiSi, and has a thickness in a range between about 2 nm and about 10 nm.

Next, inFIGS.20A-C, contacts112and114(may also be referred to as contact plugs) are formed in the third recesses108. The contacts112and114may each comprise one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, the contacts112and114each include a barrier layer and a conductive material, and are electrically coupled to the underlying conductive feature (e.g., gate electrodes102and/or silicide region110in the illustrated embodiment). The contacts114are electrically coupled to the gate electrodes102and may be referred to as gate contacts, and the contacts112are electrically coupled to the silicide regions110and may be referred to as source/drain contacts. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material118may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD106.

Embodiments may achieve advantages. For example, using the above outlined process, it has been noted that the first semiconductor material layer92A is less likely to merge over the first inner spacers90between adjacent first nanostructures52, such that the first semiconductor layer92A comprises a plurality of segments as illustrated inFIG.12B. The process has been shown to result in fewer defect stacking fault creations in epitaxial source/drain region92than if a bottom-up growth process was not used. By minimizing defect stacking faults and reducing mergers of the first semiconductor material layer92A across first inner spacers90, the nano-FETs exhibit lower resistivity, and higher current carrying capacity, from the epitaxial source/drain region92, to the channel formed by the first nanostructures52(in the p-type region50P) and second nanostructures54(in the n-type region50N). Thus, the nano-FET capacity and electrical performance is improved.

In an embodiment, a nano-FET device is provided including a substrate, the substrate including a fin, isolation regions over the substrate and along opposing sides of the fin, a plurality of nanostructures over the fin, an epitaxial source/drain region adjacent the plurality of nano structures, the epitaxial source/drain region includes first semiconductor material segments, each of the first semiconductor material segments contacting an end of at least one of the plurality of nanostructures, each of the first semiconductor material segments being separated from others of the first semiconductor material segments, the first semiconductor material segments having a first dopant concentration of dopants of a first conductivity type, and a second semiconductor material layer having a second dopant concentration of dopants of the first conductivity type, the second dopant concentration being greater than the first dopant concentration, the second semiconductor material layer including a single layer covering each of the first semiconductor material segments; and a gate electrode over the plurality of nanostructures. In some embodiments, the first dopant concentration is between 1×1020atoms/cm3and 5×1020atoms/cm3. In some embodiments, the second dopant concentration is between 5×1020atoms/cm3and 10×1020atoms/cm3. In some embodiments, the first semiconductor material segments include Si1-x_L1Gex_L1, where x_L1 is between 0.1 and 0.4. In some embodiments, the second semiconductor material layer includes Si1-x_L2Gex_L2, where x_L2 is greater than or equal to 0.2 and less than or equal to 0.9, where x_L2 is greater than x_L1. In some embodiments, the epitaxial source/drain region further includes a third semiconductor material layer formed over the second semiconductor material layer, the third semiconductor material layer including a different material than the second semiconductor material layer. In some embodiments, each of the first semiconductor material segments contacts a single nanostructure of the plurality of nano structures.

In an embodiment, a nano-FET is provided including a substrate, a first nanostructure and a second nanostructure over the substrate, an epitaxial source/drain region contacting ends of the first nanostructure and the second nanostructure, the epitaxial source/drain region including a first semiconductor material layer including a first semiconductor material, the first semiconductor material layer including a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, where the first segment is separated from the second segment; and a second semiconductor material layer over the first segment and the second segment, the second semiconductor material layer including a second semiconductor material, where the second semiconductor material layer has a higher concentration of dopants of a first conductivity type than the first semiconductor material layer, where the second semiconductor material layer and the first semiconductor material layer are silicon-based materials, where the second semiconductor material layer has a lower concentration percentage of silicon than the first semiconductor material layer; and a gate electrode over the first nanostructure and the second nanostructure. In some embodiments, the nano-FET further includes a third nanostructure over the second nanostructure, where the second segment extends continuously from the second nanostructure to the third nanostructure, where the gate electrode extends over the third nanostructure. In some embodiments, the first semiconductor material includes Si1-x_L1Gex_L1, x_L1 being is between 0.1 and 0.4, where the second semiconductor material includes Si1-x_L2Gex_L2, x_L2 being greater than or equal to 0.2 and less than or equal to 0.9, x_L2 being greater than x_L1. In some embodiments, the first semiconductor material has a first dopant concentration of boron between 1×1020atoms/cm3and 5×1020atoms/cm3, where the second semiconductor material has a second dopant concentration of boron between 5×1020atoms/cm3and 10×1020atoms/cm3. In some embodiments, the first semiconductor material layer has a thickness between 2 nanometers and 6 nanometers.

In an embodiment, a method for forming a nano-FET is provided including forming a plurality of nanostructures including alternating layers of a first semiconductor material and a second semiconductor material, forming a first recess in the plurality of nanostructures, ends of the plurality of nanostructures being exposed in the first recess, recessing ends of the plurality of nanostructures of the second semiconductor material to form a second recess, forming inner spacers in the second recess on the ends of the plurality of nanostructures of the second semiconductor material, forming source/drain regions in the first recess, forming the source/drain regions including, epitaxially growing a first semiconductor material layer on each end of the plurality of nanostructures of the first semiconductor material, where the first semiconductor material layer is discontinuous, and epitaxially growing a second semiconductor material layer over each of the first semiconductor material layers, where the first semiconductor material layer has a lower concentration of dopants of a first conductivity type than the second semiconductor material layer. In some embodiments, a dopant concentration of dopants of the first conductivity type in the first semiconductor material layer is between 1×1020atoms/cm3and 5×1020atoms/cm3, where a dopant concentration of dopants of the first conductivity type in the second semiconductor material is between 5×1020atoms/cm3and 10×1020atoms/cm3. In some embodiments, the first semiconductor material layer and the second semiconductor material layer include silicon germanium, where the second semiconductor material layer has a higher concentration of germanium than the first semiconductor material layer. In some embodiments, the first semiconductor material layer includes Si1-x_L1Gex_L1, where x_L1 is between 0.1 and 0.4. In some embodiments, the second semiconductor material layer includes Si1-x_L2Gex_L2, where x_L2 is greater than or equal to 0.2 and less than or equal to 0.9, where X_L2 is greater than x_L1. In some embodiments, the source/drain region includes a third semiconductor material layer formed over the second semiconductor material layer. In some embodiments, the first semiconductor material layer is discontinuous across each inner spacer between adjacent nanostructures. In some embodiments, the first semiconductor material layer is grown to a thickness between 2 nanometers and 6 nanometers.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.