Patent ID: 12213313

DETAILED DESCRIPTION

Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which some example embodiments are shown.

FIG.1is a diagram schematically illustrating an electronic system including a semiconductor device according to an example embodiment of the inventive concepts.

Referring toFIG.1, an electronic system1000according to an example embodiment of the inventive concepts may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The electronic system1000may be a storage device, which includes one or more semiconductor devices1100, or an electronic device including the storage device. For example, the electronic system1000may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical system, or a communication system, in which at least one semiconductor device1100is provided.

The semiconductor device1100may be a nonvolatile memory device (e.g., a NAND FLASH memory device). The semiconductor device1100may include a first structure1100F and a second structure1100S on the first structure1100F. As an example, the first structure1100F may be disposed beside the second structure1100S. The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S may be a memory cell structure including a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be variously changed, according to example embodiments.

In an example embodiment, at least one of the upper transistors UT1and UT2may include the string selection transistor, and at least one of the lower transistors LT1and LT2may include a ground selection transistor. The gate lower lines LL1and LL2may be used as gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be used as gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1and UL2may be used as gate electrodes of the upper transistors UT1and UT2, respectively.

In an example embodiment, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground selection transistor LT2, which are connected in series. The upper transistors UT1and UT2may include a string selection transistor UT1and an upper erase control transistor UT2, which are connected in series. At least one of the lower and upper erase control transistors LT1and UT2may be used for an erase operation of erasing data, which are stored in the memory cell transistors MCT, using a gate-induced drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection lines1115, which are extended from a region in the first structure1100F to a region in the second structure1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection lines1125, which are extended from a region in the first structure1100F to a region in the second structure1100S.

In the first structure1100F, the decoder circuit1110and the page buffer1120may be configured to perform a control operation on at least selected one of the memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through an input/output pad1101, which is electrically connected to the logic circuit1130. The input/output pad1101may be electrically connected to the logic circuit1130through an input/output connection line1135, which is provided in the first structure1100F and is extended into the second structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In an example embodiment, the electronic system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the semiconductor devices1100.

The processor1210may control overall operations the electronic system1000including the controller1200. The processor1210may be operated depending on a specific firmware and may control the NAND controller1220to access the semiconductor device1100. The NAND controller1220may include a NAND interface1221, which is used for communication with the semiconductor device1100. The NAND interface1221may be used to transmit and receive control commands, which are used to control the semiconductor device1100, data, which will be written in or read from the memory cell transistors MCT of the semiconductor device1100, and so forth. The host interface1230may be configured to allow for communication between the electronic system1000and an external host. When a control command is received from the external host through the host interface1230, the processor1211may control the semiconductor device1100in response to the control command.

FIG.2is a perspective view schematically illustrating an electronic system including a semiconductor device, according to an example embodiment of the inventive concepts.

Referring toFIG.2, an electronic system2000according to an example embodiment of the inventive concepts may include a main substrate2001and a controller2002, at least one semiconductor package2003, and a DRAM2004, which are mounted on the main substrate2001. The semiconductor package2003and the DRAM2004may be connected to the controller2002through interconnection patterns2005, which are formed in the main substrate2001.

The main substrate2001may include a connector2006, which includes a plurality of pins to be coupled to an external host. In the connector2006, the number and arrangement of the pins may depend on a communication interface between the electronic system2000and the external host. In an example embodiment, the electronic system2000may communicate with the external host, in accordance with one of interfaces, such as universal serial bus (USB), peripheral component interconnect express (PCI-Express), serial advanced technology attachment (SATA), universal flash storage (UFS) M-PHY, or the like. In an example embodiment, the electronic system2000may be driven by an electric power, which is supplied from the external host through the connector2006. The electronic system2000may further include a power management integrated circuit (PMIC) that is configured to separately supply an electric power, which is provided from the external host, to the controller2002and the semiconductor package2003.

The controller2002may be configured to control a writing or reading operation on the semiconductor package2003and to improve an operation speed of the electronic system2000.

The DRAM2004may be a buffer memory, which relieves technical difficulties caused by a difference in speed between the semiconductor package2003, which serves as a data storage device, and an external host. In an example embodiment, the DRAM2004in the electronic system2000may serve as a cache memory and may provide a storage space to temporarily store data during a control operation on the semiconductor package2003. In the case where the electronic system2000includes the DRAM2004, the controller2002may further include a DRAM controller to control the DRAM2004, in addition to a NAND controller to control the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003b, which are spaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, the semiconductor chips2200on the package substrate2100, adhesive layers2300respectively disposed on bottom surfaces of the semiconductor chips2200, a connection structure2400electrically connecting the semiconductor chips2200to the package substrate2100, and a molding layer2500disposed on the package substrate2100to cover the semiconductor chips2200and the connection structure2400.

The package substrate2100may be a printed circuit board including package upper pad portions2130. Each of the semiconductor chips2200may include an input/output pad portion2210. The input/output pad portion2210may correspond to the input/output pad1101ofFIG.1. Each of the semiconductor chips2200may include gate stacks3210and vertical structures3220. Each of the semiconductor chips2200may include a semiconductor device, which will be described below, according to an example embodiment of the inventive concepts.

In an example embodiment, the connection structure2400may be a bonding wire electrically connecting the input/output pad portion2210to the package upper pad portions2130. In each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other in a bonding wire manner and may be electrically connected to the package upper pad portions2130of the package substrate2100. In some example embodiments, the semiconductor chips2200in each of the first and second semiconductor packages2003aand2003bmay be electrically connected to each other by a connection structure including through silicon vias (TSVs), not by the connection structure2400provided in the form of bonding wires.

In an example embodiment, the controller2002and the semiconductor chips2200may be included in a single package. In an example embodiment, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate, which is prepared independent of the main substrate2001, and may be connected to each other through interconnection lines, which are provided in the interposer substrate.

FIGS.3and4are sectional views, each of which schematically illustrates a semiconductor package according to an example embodiment of the inventive concepts.FIGS.3and4conceptually illustrate two different examples of the semiconductor package ofFIG.2and are, for example, sectional views taken along a line I-I′ ofFIG.2.

Referring toFIG.3, in the semiconductor package2003, the package substrate2100may be a printed circuit board. The package substrate2100may include a package substrate body portion2120, the package upper pad portions2130(e.g., ofFIG.2) disposed on a top surface of the package substrate body portion2120, lower pad portions2125, which are disposed on or exposed through a bottom surface of the package substrate body portion2120, and internal lines2135, which are provided in the package substrate body portion2120to electrically connect the package upper pad portions2130to the lower pad portions2125. The lower pad portions2125may be connected to the interconnection patterns2005of the main substrate2001of the electronic system2000through conductive connecting portions2800, as shown inFIG.2.

Each of the semiconductor chips2200may include a semiconductor substrate3010and first and second structures3100and3200, which are sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region, in which peripheral lines3110are provided. The second structure3200may include a source structure3205, the gate stack3210on the source structure3205, the vertical structures3220penetrating the gate stack3210, bit lines3240electrically connected to the vertical structures3220, and cell contact plugs3235electrically connected to the word lines WL (e.g., seeFIG.1) of the gate stack3210. The second structure3200may further include separation structures3230(e.g., seeFIG.2), which will be described in more detail below.

Each of the semiconductor chips2200may include penetration lines3245, which are electrically connected to the peripheral lines3110of the first structure3100and are extended into the second structure3200. The penetration line3245may be disposed outside the gate stack3210or may be disposed to penetrate the gate stack3210. Each of the semiconductor chips2200may further include the input/output pad portions2210(e.g., ofFIG.2), which are electrically connected to the peripheral lines3110of the first structure3100.

Referring toFIG.4, in the semiconductor package2003A, each of the semiconductor chips2200amay include a semiconductor substrate4010, a first structure4100on the semiconductor substrate4010, and a second structure4200, which is provided on the first structure4100and is bonded with the first structure4100in a wafer bonding manner.

The first structure4100may include a peripheral circuit region, in which a peripheral line4110and first junction structures4150are provided. The second structure4200may include a source structure4205, a gate stack4210between the source structure4205and the first structure4100, vertical structures4220penetrating the gate stack4210, and second junction structures4240electrically connected to the vertical structures4220and the word lines WL (e.g., seeFIG.1) of the gate stack4210. For example, the second junction structures4240may be electrically connected to the vertical structures4220and the word lines WL (e.g., seeFIG.1) respectively through bit lines4250, which are electrically connected to the vertical structures4220, and cell contact plugs4235, which are electrically connected to the word lines WL (e.g., seeFIG.1), respectively. The first junction structures4150of the first structure4100and the second junction structures4240of the second structure4200may be in contact with each other and may be bonded to each other. Portions of the first and second junction structures4150and4240, which are bonded to each other, may be formed of, for example, copper (Cu). Each of the semiconductor chips2200amay further include the input/output pad portions2210(e.g., seeFIG.2), which are electrically connected to the peripheral lines4110of the first structure4100.

The semiconductor chips2200ofFIG.3and the semiconductor chips2200aofFIG.4may be connected to each other by the connection structures2400(e.g., seeFIG.2), which are provided in the form of bonding wires. However, in some example embodiments, the semiconductor chips (e.g.,2200or2200a), which are provided in each semiconductor package, may be electrically connected to each other by a connection structure including through silicon vias (TSVs).

The first structure3100ofFIG.3and the first structure4100ofFIG.4may correspond to a peripheral circuit structure in the example embodiments to be described below, and the second structure3200ofFIG.3and the second structure4200ofFIG.4may correspond to a cell array structure in the example embodiments to be described below.

FIG.5is a plan view schematically illustrating a semiconductor device according to an example embodiment of the inventive concepts.

Referring toFIG.5, the semiconductor device may include a substrate10, a horizontal layer100on the substrate10, and a plurality of mat regions MTR on the horizontal layer100. Each of the mat regions MTR may include a plurality of memory blocks. Each of the memory blocks may be a unit size of data to be erased during an erase operation. Each of the memory blocks may include a plurality of pages. The pages may include the second structure1100S described with reference toFIG.1. The page may be a unit size of data to be read or written during a reading or writing operation and may include a plurality of unit memory cells.

Each of the mat regions MTR may be controlled through a peripheral circuit structure formed between the substrate10and the horizontal layer100. The peripheral circuit structure may include the first structure1100F described with reference toFIG.1. The horizontal layer100may be formed on the peripheral circuit structure and may have a flat top surface, on which the mat regions MTR are formed. The mat regions MTR may be arranged in a first direction D1and a second direction D2, which are parallel to the top surface of the horizontal layer100.

A buried insulating pattern102may be formed between the mat regions MTR. The buried insulating pattern102may be extended in the first and second directions D1and D2to cross at least a portion of the horizontal layer100. In an example embodiment, the buried insulating pattern102may be provided to fully cross the horizontal layer100or to divide the horizontal layer100into a plurality of electrically-separated regions. The mat regions MTR and the peripheral circuit structure may be connected to each other through penetration vias, which are formed to penetrate the buried insulating pattern102. The penetration vias may include the first connection lines1115described with reference toFIG.1.

FIG.6is a plan view illustrating a portion (e.g., a portion ‘A’ ofFIG.5) of a semiconductor device according to an example embodiment of the inventive concepts.FIGS.7and8are sectional views taken along lines I-I′ and II-II′ ofFIG.6.FIGS.9and10are enlarged sectional views illustrating portions ‘AA’ and ‘BB’ ofFIG.7, respectively.

Referring toFIGS.6to8, a peripheral circuit structure PS may include peripheral logic circuits PTR integrated on a top surface of the substrate10, a lower insulating gapfill layer50covering the peripheral logic circuits PTR, and peripheral circuit interconnection lines33in the lower insulating gapfill layer50. The substrate10may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystalline epitaxial layer grown on a single-crystalline silicon substrate. The substrate10may include active regions defined by a device isolation layer11. The substrate10may include mat regions MTR, a penetration interconnection region THR between the mat regions MTR, and gap regions GR between the mat regions MTR and the penetration interconnection region THR.

The peripheral logic circuits PTR may include the row and column decoders, the page buffer, and the control circuit described with reference toFIG.1. The peripheral logic circuits PTR may include NMOS and PMOS transistors, low- and high-voltage transistors, and resistors, which are integrated on the substrate10. The peripheral circuit interconnection lines33and landing pads LP may be electrically connected to the peripheral logic circuits PTR through peripheral contact plugs31.

The lower insulating gapfill layer50may be provided on the top surface of the substrate10. The lower insulating gapfill layer50may cover the peripheral logic circuits PTR, the peripheral contact plugs31, the peripheral circuit interconnection lines33, and the landing pads LP. The lower insulating gapfill layer50may include a first lower layer51, a second lower layer52, and a third lower layer53, which are sequentially stacked. The second lower layer52may have a thickness that is smaller than the first lower layer51and the third lower layer53. Each of the first lower layer51, the second lower layer52, and the third lower layer53may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a low-k dielectric layer. The second lower layer52may be formed of or include at least one of materials having an etch selectivity with respect to the first lower layer51and the third lower layer53. In an example embodiment, the second lower layer52may serve as an etch stop layer.

The peripheral contact plugs31, the peripheral circuit interconnection lines33, and the landing pads LP may be provided between the second lower layer52and the top surface of the substrate10. The landing pads LP may be electrically connected to the peripheral circuit interconnection lines33through the peripheral contact plugs31. The peripheral circuit interconnection lines33may be electrically connected to the peripheral logic circuits PTR through the peripheral contact plugs31. The landing pads LP may have top surfaces which are located at a level adjacent to a top surface of the first lower layer51. In an example embodiment, the landing pads LP may have a thickness that is larger than the peripheral circuit interconnection lines33.

A cell array structure CS may be disposed on the lower insulating gapfill layer50. The cell array structure CS may include memory structures, which are provided on the mat regions MTR, and vertical conductive structures VCS1, VCS2, and VCS3, which are provided in an insulating layer covering the memory structures.

For example, the horizontal layer100may be disposed on the lower insulating gapfill layer50. The horizontal layer100may be disposed between an electrode structure ST and the peripheral circuit structure PS and may have a flat top surface, on which the electrode structure ST is formed. The horizontal layer100may be formed of or include at least one of semiconductor materials. The horizontal layer100may be formed of or include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenic (GaAs), indium gallium arsenic (InGaAs), or aluminum gallium arsenic (AlGaAs). The horizontal layer100may include a polysilicon layer doped with n-type impurities. The horizontal layer100may be formed to have one of single-crystalline, poly-crystalline, and amorphous structures.

A source structure SC may be disposed between the electrode structure ST and the horizontal layer100. The source structure SC may be extended parallel to the electrode structure ST or in the first and second directions D1and D2. The source structure SC may include a first horizontal pattern SCP1and a second horizontal pattern SCP2on the first horizontal pattern SCP1. Each of the first and second horizontal patterns SCP1and SCP2may be formed of or include at least one of doped semiconductor materials. In each of the first and second horizontal patterns SCP1and SCP2, the dopants may include, for example, phosphorus (P) or arsenic (As). In an example embodiment, the first horizontal pattern SCP1may have a doping concentration that is higher than the second horizontal pattern SCP2.

The electrode structures ST may be disposed on the source structure SC. The electrode structures ST may be extended from a cell array region CAR to a connection region CNR. Each of the electrode structures ST may include insulating layers ILD and electrodes EL, which are alternately stacked in a third direction D3perpendicular to the top surface of the substrate10. The electrodes EL may be stacked to have a stepwise structure on the connection region CNR, which is located at an edge portion of each mat region MTR. In each electrode structure ST, lengths of the electrodes EL in the first direction D1may decrease with increasing distance from the horizontal layer100. Each of the electrode structures ST may have pads PAD, which are arranged in a stepwise shape on the connection region CNR. The pads PAD may be portions of the electrodes EL and may be exposed by another of the electrodes EL directly disposed thereon. Adjacent ones of the pads PAD may be placed at horizontal and vertical positions different from each other. The electrodes EL may be formed of or include at least one of conductive materials. The electrodes EL may be formed of or include at least one of, for example, semiconductor materials, metal silicides, metallic materials, or metal nitrides. The insulating layers ILD may be formed of or include silicon oxide.

Vertical channel structures VS may be provided on the cell array region CAR to penetrate the electrode structure ST. The vertical channel structures VS may penetrate the source structure SC and may be connected to the horizontal layer100. The vertical channel structures VS may be arranged in a specific direction or in a zigzag shape, when viewed in a plan view. The vertical channel structures VS may be formed of or include at least one of semiconductor materials (e.g., silicon (Si) and germanium (Ge)). Further, the vertical channel structures VS may be formed of or include at least one of doped semiconductor materials and/or undoped or intrinsic semiconductor materials.

For example, referring toFIG.9, the vertical channel structures VS may include a buried insulating pattern VI, a vertical semiconductor pattern VP, and a data storing layer SP. The data storing layer SP may include a tunnel insulating layer TL, a charge storing layer CIL, and a blocking insulating layer BIL. The data storing layer SP may be used as a data storing layer of a NAND FLASH memory device. The data storing layer SP may include two portions, which are vertically separated from each other by an undercut region UC. The undercut region UC may be filled with the first horizontal pattern SCP1.

Referring back toFIGS.6to8, a planarization insulating layer150may be provided on the horizontal layer100. The planarization insulating layer150may cover end portions (i.e., the pads PAD) of the electrodes EL forming a stepwise structure. The planarization insulating layer150may have a flat top surface. In an example embodiment, the top surface of the planarization insulating layer150may be coplanar with the top surface of the uppermost one of the insulating layers ILD of the electrode structure ST. The planarization insulating layer150may be formed of or include at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride. A first interlayer insulating layer112may be provided on the top surface of the planarization insulating layer150. The first interlayer insulating layer112may cover top surfaces of the vertical channel structures VS.

Supporting structures DS may be formed on the connection region CNR. The supporting structures DS may be provided to penetrate the electrode structure ST (e.g., seeFIG.14). In an example embodiment, the supporting structures DS and the vertical channel structures VS may be formed through the same process. The supporting structures DS may have a structure similar to the vertical channel structures VS but may not be connected to the bit lines BL to be described below.

Separation structures SS1and SS2may be provided on each of the mat regions MTR. The separation structures SS1and SS2may be extended in the first direction D1. The separation structures SS1and SS2may be provided to cross the electrode structure ST in the first direction D1. The separation structures SS1and SS2may be extended in the third direction D3to penetrate the first interlayer insulating layer112, the planarization insulating layer150, and the electrode structure ST. The electrodes EL may be spaced apart from each other in the second direction D2by the separation structures SS1and SS2. Top surfaces of the separation structures SS1and SS2may be located at the same level as a top surface of the first interlayer insulating layer112. Bottom surfaces of the separation structures SS1and SS2may be located at a level lower than a bottom surface of the lowermost one of the electrodes EL. In an example embodiment, the bottom surfaces of the separation structures SS1and SS2may be in contact with the source structure SC. The separation structures SS1and SS2may be formed of or include at least one of insulating materials. For example, the separation structures SS1and SS2may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

The separation structures SS1and SS2may include first separation structures SS1, which are provided to fully cross the electrode structure ST, and second separation structures SS2, which are provided to partially cross the electrode structure ST. In an example embodiment, the first separation structures SS1and the second separation structures SS2may be alternately disposed in the second direction D2.

An insulating separation pattern115may be formed in an upper portion of the electrode structure ST. The insulating separation pattern115may be provided on the cell array region CAR to extend in the first direction D1. The insulating separation pattern115may be aligned to the second separation structure SS2on the connection region CNR in the first direction D1. The insulating separation pattern115may be provided to penetrate some of the electrodes EL provided at an upper level of the electrode structure ST. In other words, due to the insulating separation pattern115, some of the electrodes EL provided at an upper level of the electrode structure ST may be separated from each other in the second direction D2. The insulating separation pattern115may overlap some of the vertical channel structures VS.

A second interlayer insulating layer114and a third interlayer insulating layer116may be sequentially stacked on the first interlayer insulating layer112. The second interlayer insulating layer114and the third interlayer insulating layer116may be formed of or include, for example, silicon oxide. The second interlayer insulating layer114may cover the top surfaces of the separation structures SS1and SS2.

The bit lines BL may be provided on the cell array region CAR. The bit lines BL may be disposed on the third interlayer insulating layer116. The bit lines BL may be extended in the second direction D2to cross the electrode structures ST. Each of the bit lines BL may be electrically connected to the vertical channel structures VS through bit line plugs BP. The bit line plugs BP may be provided to penetrate the first interlayer insulating layer112, the second interlayer insulating layer114, and the third interlayer insulating layer116and to connect the bit lines BL to the vertical channel structures VS.

Contact plugs CP may be provided on the connection region CNR. The contact plugs CP may be provided to penetrate the first interlayer insulating layer112, the second interlayer insulating layer114, and the planarization insulating layer150and may be coupled to the end portions (e.g., the pads PAD) of the electrodes EL. Lengths of the contact plugs CP may depend on heights of the pads PAD coupled thereto. The larger the distance from the cell array region CAR, the larger the lengths of the contact plugs CP. That is, vertical levels of bottom ends of the contact plugs CP may depend on the heights of the pads PAD coupled thereto.

Penetration vias TV may be provided on the penetration interconnection region THR. The penetration vias TV may be provided to penetrate the first interlayer insulating layer112, the second interlayer insulating layer114, the planarization insulating layer150, the buried insulating pattern102, and the lower insulating gapfill layer50and may be coupled to the landing pads LP. The penetration vias TV may have vertical lengths which are larger than the contact plugs CP. The penetration vias TV may be connected to the contact plugs CP, respectively, through upper interconnection lines CL, which are formed on the third interlayer insulating layer116. In other words, the penetration vias TV may electrically connect the electrodes EL of the electrode structures ST to the peripheral logic circuits PTR.

The vertical conductive structures VCS1, VCS2, and VCS3may be provided on the connection region CNR, the gap region GR, and the penetration interconnection region THR. At least some of the vertical conductive structures VCS1, VCS2, and VCS3may be located between the contact plugs CP and the penetration vias TV. The vertical conductive structures VCS1, VCS2, and VCS3may be surrounded by at least one insulating material and may be in an electrically-floated state. For example, the vertical conductive structures VCS1, VCS2, and VCS3may include a plurality of conductive pillars, which are horizontally spaced apart from each other, and each of which is in an electrically-floated state. The conductive pillars may not be grounded. A voltage from an external power may not be applied to the conductive pillars. The conductive pillars may be electrically disconnected from each other.

The vertical conductive structures VCS1, VCS2, and VCS3may have top surfaces which are located at a level that is higher than top surfaces of the separation structures SS1and SS2and is lower than bottom surfaces of the upper interconnection lines CL. The top surfaces of the vertical conductive structures VCS1, VCS2, and VCS3may be located at the same level as a top surface of the second interlayer insulating layer114. The top surfaces of the vertical conductive structures VCS1, VCS2, and VCS3may be covered with the third interlayer insulating layer116. The vertical conductive structures VCS1, VCS2, and VCS3may be provided to penetrate the first interlayer insulating layer112and the second interlayer insulating layer114and may be extended into the planarization insulating layer150. Some of the vertical conductive structures VCS1, VCS2, and VCS3may have lower portions which are inserted in the planarization insulating layer150. Others of the vertical conductive structures VCS1, VCS2, and VCS3may penetrate the planarization insulating layer150and may be inserted in the lower insulating gapfill layer50. Each of the vertical conductive structures VCS1, VCS2, and VCS3may have a width decreasing with decreasing distance from the substrate10.

The vertical conductive structures VCS1, VCS2, and VCS3may include first vertical conductive structures VCS1on the gap region GR, second vertical conductive structures VCS2on the penetration interconnection region THR, and third vertical conductive structures VCS3on the connection region CNR. The first vertical conductive structures VCS1may have a length which is smaller than the second vertical conductive structures VCS2and is larger than the third vertical conductive structures VCS3. Each of the first, second, and third vertical conductive structures VCS1, VCS2, and VCS3may be referred to as a conductive pillar. The conductive pillars may be arranged to have a specific density on each region of the substrate10, and in this case, it may be possible to more easily exhaust an impurity gas, which is formed in the planarization insulating layer150during a process of fabricating a semiconductor device. In an example embodiment, the impurity gas may include hydrogen gas. The numbers of the conductive pillars per unit area on the gap region GR, the penetration interconnection region THR, and the connection region CNR may be different from each other.

The vertical conductive structures VCS1, VCS2, and VCS3will be described in more detail with reference toFIGS.6to8and10. The first vertical conductive structures VCS1may be positioned between the electrode structure ST and the penetration vias TV. The first vertical conductive structures VCS1may be arranged on the gap region GR in the first and second directions D1and D2. Some of the first vertical conductive structures VCS1may be located between the separation structures SS1and SS2, which are adjacent to each other in the first direction D1. Others of the first vertical conductive structures VCS1may be located between the separation structures SS1and SS2and the penetration vias TV. The first vertical conductive structures VCS1may be located on a top surface100tof the horizontal layer100.

At least some of the first vertical conductive structures VCS1may vertically overlap the upper interconnection line CL connecting the contact plug CP to the penetration via TV, as shown inFIGS.7and10. The first vertical conductive structures VCS1may be electrically disconnected from the upper interconnection lines CL. The first vertical conductive structures VCS1may have top surfaces VCS1t, which are located at a level lower than the bottom surfaces of the upper interconnection lines CL, and the bottom surfaces of the upper interconnection lines CL and the top surfaces VCS1tof the first vertical conductive structures VCS1may be spaced apart from each other in the third direction D3with the third interlayer insulating layer116interposed therebetween. The top surfaces VCSlt of the first vertical conductive structures VCS1may be located at the same level as top surfaces CPt of the contact plugs CP and top surfaces TVt of the penetration vias TV.

Lengths of the first vertical conductive structures VCS1in the third direction D3may be shorter than the penetration vias TV. The first vertical conductive structures VCS1may have a length, which is longer than the longest one of the contact plugs CP, when measured in the third direction D3. For example, the first vertical conductive structures VCS1may have a length, which is longer than the contact plug CP that is connected to the lowermost one of the electrodes EL or is closest to the penetration vias TV, when measured in the third direction D3.

The first vertical conductive structures VCS1may have bottom surfaces VCS1b, which are located at a level higher than the top surface100tof the horizontal layer100. The bottom surfaces VCS1bof the first vertical conductive structures VCS1may be located at a level lower than bottom ends CPb of the contact plugs CP. A region between the bottom surfaces VCS1bof the first vertical conductive structures VCS1and the top surface100tof the horizontal layer100may be filled with the planarization insulating layer150. The bottom surfaces VCS1bof the first vertical conductive structures VCS1may be covered with the planarization insulating layer150. In other words, lower portions of the first vertical conductive structures VCS1may be buried or inserted in the planarization insulating layer150. The bottom surfaces VCS1bof the first vertical conductive structures VCS1may be adjacent to the top surface100tof the horizontal layer100. For example, a distance between the bottom surfaces VCS1bof the first vertical conductive structures VCS1and the top surface100tof the horizontal layer100may be smaller than a thickness of the horizontal layer100. The bottom surfaces VCS1bof the first vertical conductive structures VCS1may be located at a level lower than the bottom surface of the lowermost one of the electrodes EL. The bottom surfaces VCS1bof the first vertical conductive structures VCS1may be positioned at a level between top and bottom surfaces of the source structure SC. Widths of the bottom surfaces VCS1bof the first vertical conductive structures VCS1may be smaller than widths of the top surfaces VCS It of the first vertical conductive structures VCS1.

The second vertical conductive structures VCS2may be positioned between the penetration vias TV. The second vertical conductive structures VCS2may be arranged on the penetration interconnection region THR and in the first and second directions D1and D2. The second vertical conductive structures VCS2may be positioned between a pair of the penetration vias TV, which are adjacent to each other in the first direction D1. For example, a pair of the second vertical conductive structures VCS2may be disposed between the pair of the penetration vias TV, which are adjacent to each other in the first direction D1. The second vertical conductive structures VCS2may vertically overlap the buried insulating pattern102.

The second vertical conductive structures VCS2may have bottom surfaces VCS2bwhich are located at a level lower than a bottom surface100bof the horizontal layer100. The second vertical conductive structures VCS2may be provided to penetrate the buried insulating pattern102, and the bottom surfaces VCS2bof the second vertical conductive structures VCS2may be spaced apart from a bottom surface of the buried insulating pattern102. The second vertical conductive structures VCS2may be lower portions which are buried or inserted in the lower insulating gapfill layer50. The bottom surface VCS2bof the second vertical conductive structures VCS2may be covered with the third lower layer53. Some of the second vertical conductive structures VCS2may vertically overlap the landing pads LP. The bottom surface VCS2bof the second vertical conductive structure VCS2, which overlaps the landing pad LP, may be adjacent to a top surface LPt of the landing pad LP. For example, the bottom surface VCS2bof the second vertical conductive structure VCS2overlapping the landing pad LP may be located at a vertical level, which is closer to the top surface LPt of the landing pad LP than to a bottom surface100bof the horizontal layer100. The bottom surface VCS2bof the second vertical conductive structures VCS2may be located at a level which is higher than a top surface of the second lower layer52.

At least one of the second vertical conductive structures VCS2may vertically overlap the upper interconnection line CL on the penetration interconnection region THR, as shown inFIGS.7and10. The second vertical conductive structures VCS2may be electrically disconnected from the upper interconnection lines CL. The second vertical conductive structures VCS2may have top surfaces VCS2t, which are located at a level lower than the bottom surfaces of the upper interconnection lines CL, and the bottom surface of the upper interconnection lines CL and the top surfaces VCS2tof the second vertical conductive structures VCS2may be spaced apart from each other in the third direction D3with the third interlayer insulating layer116interposed therebetween. The top surfaces VCS2tof the second vertical conductive structures VCS2may be located at the same level as the top surfaces CPt of the contact plugs CP and the top surfaces TVt of the penetration vias TV. Widths of the top surfaces VCS2tof the second vertical conductive structures VCS2may be larger than widths of the bottom surfaces VCS2bof the second vertical conductive structures VCS2.

The second vertical conductive structures VCS2may have a length, which is longer than the first vertical conductive structures VCS1and is shorter than the penetration vias TV, when measured in the third direction D3. The second vertical conductive structures VCS2may have a length, which is longer than the longest one of the contact plugs CP, when measured in the third direction D3. For example, the second vertical conductive structures VCS2may have a length, which is longer than the contact plug CP that is connected to the lowermost one of the electrodes EL or is closest to the penetration vias TV, when measured in the third direction D3.

The third vertical conductive structures VCS3may be arranged on the connection region CNR in the first and second directions D1and D2. The third vertical conductive structures VCS3may vertically overlap the pads PAD. At least one of the third vertical conductive structures VCS3may vertically overlap two adjacent ones of the pads PAD. For example, one of the third vertical conductive structures VCS3may vertically overlap a pair of the pads PAD, which are adjacent to each other in the first direction D1. One of the third vertical conductive structures VCS3may vertically overlap a side surface ELs of the electrode EL oriented in the first direction D1. For example, one of the third vertical conductive structures VCS3may vertically overlap the side surfaces ELs of the electrodes EL oriented in the first direction D1. The third vertical conductive structures VCS3may be located between the contact plugs CP. The third vertical conductive structures VCS3may be located between a pair of the contact plugs CP, which are adjacent to each other in the first direction D1. For example, one of the third vertical conductive structures VCS3may be disposed between the contact plugs CP, which are adjacent to each other in the first direction D1. The third vertical conductive structures VCS3may have a length which is shorter than the pair of the contact plugs CP adjacent to each other in the first direction D1.

The third vertical conductive structures VCS3may have bottom surfaces VCS3b, which are located at a level higher than the top surface of each of the pads PAD vertically overlapping the third vertical conductive structures VCS3. In the case where the third vertical conductive structure VCS3vertically overlaps a pair of the pads PAD, the bottom surface VCS3bof the third vertical conductive structure VCS3may be located at a level higher than a top surface of a higher one of the pair of the pads PAD. In other words, the third vertical conductive structures VCS3may be spaced apart from the pads PAD in the third direction D3and may be electrically disconnected from the pads PAD. Regions between the third vertical conductive structures VCS3and the pads PAD may be filled with the planarization insulating layer150. The bottom surfaces VCS3bof the third vertical conductive structures VCS3may be covered with the planarization insulating layer150. In other words, lower portions of the third vertical conductive structures VCS3may be buried or inserted in the planarization insulating layer150. At least one of the third vertical conductive structures VCS3may have the bottom surface VCS3blocated at a level lower than the bottom ends CPb of some contact plugs CP. For example, the bottom surface VCS3bof the third vertical conductive structure VCS3, which is closest to the penetration interconnection region THR, may be located at a level that is lower than the bottom end CPb of the contact plug CP coupled to the highest one of the pads PAD.

The third vertical conductive structures VCS3may be electrically disconnected from the upper interconnection lines CL. The third vertical conductive structures VCS3may have top surfaces VCS3twhich are located at a level lower than the bottom surface of the upper interconnection lines CL. The top surfaces VCS3tof the third vertical conductive structures VCS3may be located at the same level as the top surfaces CPt of the contact plugs CP and the top surfaces TVt of the penetration vias TV. Widths of the top surfaces VCS3tof the third vertical conductive structures VCS3may be larger than widths of the bottom surfaces VCS3bof the third vertical conductive structures VCS3.

FIGS.11A,11B, and11Care enlarged sectional views, each of which illustrate a semiconductor device according to an example embodiment of the inventive concepts and corresponds to the portion ‘BB’ ofFIG.7.

Referring toFIG.11A, the first vertical conductive structures VCS1may include a first conductive pillar VC1, a second conductive pillar VC2, and a third conductive pillar VC3which have different lengths in the third direction D3. Because the first vertical conductive structures VCS1have different lengths from each other, it may be possible to improve reliability in an electric separation property between the first vertical conductive structures VCS1and elements provided therebelow.

In an example embodiment, the first conductive pillar VC1, the second conductive pillar VC2, and the third conductive pillar VC3may have top surfaces which are located at the same level. A bottom surface VC2bof the second conductive pillar VC2may be located at a level that is lower than a bottom surface VC1bof the first conductive pillar VC1and is higher than a bottom surface VC3bof the third conductive pillar VC3. The bottom surface VC1bof the first conductive pillar VC1may be located at a level higher than the top surface of the lowermost one of the electrodes EL. The bottom surface VC2bof the second conductive pillar VC2may be located at a vertical level between the top and bottom surfaces of the source structure SC. The bottom surface VC3bof the third conductive pillar VC3may be located at a level lower than the top surface100tof the horizontal layer100. For example, the bottom surface VC3bof the third conductive pillar VC3may be located at a vertical level between the top surface100tof the horizontal layer100and the bottom surface100bof the horizontal layer100. A lower portion of the third conductive pillar VC3may be buried in the buried insulating pattern102. The bottom surface VC3bof the third conductive pillar VC3may be covered with the buried insulating pattern102. In an example embodiment, the first vertical conductive structures VCS1may have lengths increasing with decreasing distance from the penetration vias TV.

Referring toFIG.11B, the second vertical conductive structure VCS2may have the bottom surface VCS2blocated at a level higher than the bottom surface100bof the horizontal layer100. Because the second vertical conductive structure VCS2has a reduced length, it may be possible to mitigate or prevent the second vertical conductive structures VCS2from leaning. Further, it may be possible to improve reliability in an electric separation property between the second vertical conductive structures VCS2and the landing pads LP. In an example embodiment, the bottom surface VCS2bof the second vertical conductive structure VCS2may be located at a vertical level between the top surface100tof the horizontal layer100and the bottom surface100bof the horizontal layer100. The bottom surface VCS2bof the second vertical conductive structure VCS2may be covered with the buried insulating pattern102. That is, a lower portion of the second vertical conductive structure VCS2may be buried or inserted in the buried insulating pattern102.

Referring toFIG.11C, the top surfaces VCS1t, VCS2t, and VCS3tof the vertical conductive structures VCS1, VCS2, and VCS3may be located at a level lower than the top surfaces CPt of the contact plugs CP. The top surfaces VCS1t, VCS2t, and VCS3tof the vertical conductive structures VCS1, VCS2, and VCS3may be covered with the second interlayer insulating layer114. The top surfaces VCS1t, VCS2t, and VCS3tof the vertical conductive structures VCS1, VCS2, and VCS3may be located at the same level as the top surface of the first interlayer insulating layer112. A length of an upper plug UP connecting the contact plug CP to the upper interconnection line CL may be shorter than a length of the upper plug UP connecting the penetration via TV to the upper interconnection line CL.

FIGS.12A and12Bare enlarged plan views, each of which illustrates a semiconductor device according to an example embodiment of the inventive concepts and corresponds to a portion ‘CC’ ofFIG.6.

Referring toFIGS.6and12A, a distance d1between adjacent ones of the first vertical conductive structures VCS1in the first direction D1may be smaller than a distance d2between adjacent ones of the second vertical conductive structures VCS2in the first direction D1. The first vertical conductive structures VCS1may be arranged to have a density that is higher than that of the second vertical conductive structures VCS2, when viewed in a plan view. For example, the number of the first vertical conductive structures VCS1per unit area on the gap region GR may be greater than the number of the second vertical conductive structures VCS2per unit area on the penetration interconnection region THR.

In an example embodiment, diameters r1of the vertical conductive structures VCS1, VCS2, and VCS3may be smaller than diameters r2of the penetration vias TV and diameters r3of the contact plugs CP. The diameters r1of the vertical conductive structures VCS1, VCS2, and VCS3may be larger than diameters r4of the supporting structures DS.

Referring toFIG.12B, the second vertical conductive structures VCS2may be disposed between the penetration vias TV, which are adjacent to each other in the second direction D2. In an example embodiment, the second vertical conductive structures VCS2may be arranged to surround the penetration vias TV when viewed in a plan view. In an example embodiment, the penetration vias TV and the second vertical conductive structures VCS2may be alternately arranged in the first and second directions D1and D2.

FIG.13is an enlarged plan view illustrating a semiconductor device according to an example embodiment of the inventive concepts and corresponding to a portion ‘DD’ ofFIG.6.FIGS.14and15are sectional views taken along lines and IV-IV′ ofFIG.13.

Referring toFIGS.13to15, the second vertical conductive structures VCS2may be disposed between the supporting structures DS, which are adjacent to each other in the first direction D1. Further, the second vertical conductive structures VCS2may be disposed between the contact plugs CP, which are adjacent to each other in the second direction D2.

For example, the second vertical conductive structures VCS2may be disposed between the supporting structures DS, which are provided to penetrate one of the pads PAD and are spaced apart from each other in the first direction D1. The second vertical conductive structures VCS2may have bottom surfaces located at a level higher than the top surface of the one of the pads PAD.

A pair of the second vertical conductive structures VCS2, which are spaced apart from each other in the second direction D2, may be disposed on one of the pads PAD. The contact plug CP coupled to the one of the pads PAD may be disposed between a pair of the second vertical conductive structures VCS2, which are spaced apart from each other in the second direction D2.

FIG.16is an enlarged plan view illustrating a semiconductor device according to an example embodiment of the inventive concepts and corresponding to the portion ‘DD’ ofFIG.6.FIGS.17and18are sectional views taken along lines and IV-IV′ ofFIG.13.

Referring toFIGS.16to18, at least some of the second vertical conductive structures VCS2may vertically overlap the separation structures SS1and SS2. The second vertical conductive structures VCS2may be partially or fully overlapped with the separation structures SS1and SS2, when viewed in a plan view.

At least some of the second vertical conductive structures VCS2may be located between the second separation structures SS2. For example, the second separation structures SS2may be spaced apart from each other in the first direction D1, and the second vertical conductive structures VCS2may be located on the electrodes EL between the second separation structures SS2. The second vertical conductive structures VCS2may have bottom surfaces VCS2b, which are spaced apart from the top surfaces of the electrodes EL between the second separation structures SS2in the third direction D3.

FIG.19is a sectional view illustrating a semiconductor device according to an example embodiment of the inventive concepts, taken along the line I-I′ ofFIG.6. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.

Referring toFIG.19, the electrode structure ST may include a lower electrode structure ST1and an upper electrode structure ST2on the lower electrode structure ST1. The lower electrode structure ST1may include first insulating layers ILD1and first electrodes EL1, which are alternately stacked in the third direction D3. The upper electrode structure ST2may include second insulating layers ILD2and second electrodes EL2, which are alternately stacked in the third direction D3. The uppermost one of the second insulating layers ILD2of the upper electrode structure ST2may be thicker than the first insulating layers ILD1and the others of the second insulating layers ILD2placed therebelow. One of the first insulating layers ILD1, which is located between the uppermost electrode EL1of the lower electrode structure ST1and the lowermost electrode EL2of the upper electrode structure ST2, may be thicker than others of the first insulating layers ILD1placed therebelow.

The vertical channel structures VS may be provided on the cell array region CAR to penetrate the upper electrode structure ST2and the lower electrode structure ST1. The vertical channel structures VS may have a diameter decreasing from the top surface of the upper electrode structure ST2to the bottom surface of the upper electrode structure ST2. The vertical channel structures VS may have a diameter decreasing from the top surface of the lower electrode structure ST1(i.e., the top surface of the uppermost first insulating layer ILD1) to the bottom surface of the lower electrode structure ST1. Each of the vertical channel structures VS may have a height-difference portion stp whose diameter is discontinuously changed near a boundary between the lower and upper electrode structures ST1and ST2. The bottom surfaces VCS1bof the first vertical conductive structures VCS1and the bottom surfaces VCS2bof the second vertical conductive structures VCS2may be located at a level that is lower than the top surface of the lower electrode structure ST1and the height-difference portions stp of the vertical channel structures VS.

Hereinafter, a method of fabricating a semiconductor device according to an example embodiment of the inventive concepts will be described in more detail with reference to the accompanying drawings.

FIGS.20,21,22,23,26, and27are sectional views illustrating a method of fabricating a semiconductor device according to an example embodiment of the inventive concepts, taken along the line I-I′ ofFIG.6.FIG.24is a diagram illustrating a method of fabricating a semiconductor device according to an example embodiment of the inventive concepts and corresponding to a portion ‘EE’ ofFIG.23.FIG.25is a plan view illustrating a portion of an optical mask according to an example embodiment of the inventive concepts.

Referring toFIG.20, the peripheral circuit structure PS including the peripheral logic circuits PTR on the substrate10may be formed. In an example embodiment, the peripheral logic circuits PTR may include row and column decoders, page buffers, and control circuits, which are formed on the substrate10. For example, the formation of the peripheral logic circuits PTR may include forming the device isolation layer11in the substrate10to define active regions, sequentially forming a peripheral gate insulating layer and a peripheral gate electrode on the substrate10, and injecting impurities into portions of the substrate10at both sides of the peripheral gate electrode to form source/drain regions. Peripheral gate spacers may be formed on side surfaces of the peripheral gate electrode.

The peripheral contact plugs31, the peripheral circuit interconnection lines33, and the landing pads LP may be formed in the lower insulating gapfill layer50. In an example embodiment, the landing pads LP may be electrically connected to the peripheral logic circuits PTR constituting the row decoder of the peripheral logic circuits PTR.

Referring toFIG.21, the horizontal layer100and the buried insulating pattern102may be formed on the peripheral circuit structure PS. The horizontal layer100may be formed using a deposition process. For example, the formation of the horizontal layer100may include depositing a poly-silicon layer to cover the entire top surface of the substrate10. Thereafter, a patterning process and a deposition process may be performed to form the buried insulating pattern102partially penetrating the horizontal layer100.

A first preliminary source layer SCL1and a second preliminary source layer SCL2may be deposited on the horizontal layer100and the buried insulating pattern102. In an example embodiment, during the process of depositing the first and second preliminary source layers SCL1and SCL2, the first and second preliminary source layers SCL1and SCL2may be doped to have a first conductivity type. Thereafter, a plurality of sacrificial layers SL and the insulating layers ILD may be alternately stacked on the second preliminary source layer SCL2.

Referring toFIG.22, a mold structure MS may be formed by performing a trimming process on the sacrificial layers SL and the insulating layers ILD. Here, the trimming process may include steps of forming a mask pattern (not shown) on a layered structure including the sacrificial layers SL and the insulating layers ILD, etching a portion of the layered structure, reducing a planar area of the mask pattern, and removing the mask pattern, and here, the steps of etching a portion of the layered structure and reducing the planar area of the mask pattern may be repeated several times, before the step of removing the mask pattern. As a result of the trimming process, the mold structure MS may be formed to have a stepwise structure on the connection region CNR of the substrate10. The buried insulating pattern102may define the penetration interconnection region THR of the substrate10. The gap region GR may be defined between the connection region CNR and the penetration interconnection region THR, and the mold structure MS may not be formed on the gap region GR. The uppermost sacrificial layers SL of the mold structure MS may define the cell array region CAR of the substrate10.

The vertical channel structures VS may be formed to penetrate the mold structure MS. The formation of the vertical channel structures VS may include forming channel holes to penetrate the mold structure MS and forming a semiconductor material in the channel holes using a deposition process. Thereafter, the source structure SC including the first and second horizontal patterns SCP1and SCP2may be formed.

The planarization insulating layer150may be formed to cover the stepwise region of the mold structure MS. The formation of the planarization insulating layer150may include forming a thick insulating layer to cover the mold structure MS and performing a planarization process on the insulating layer. The planarization insulating layer150may be formed of or include at least one of insulating materials having an etch selectivity with respect to the sacrificial layers SL.

Referring toFIGS.22and23, a process of replacing the sacrificial layers SL with the electrodes EL may be performed. Trenches may be formed to cross the mold structure MS in the first direction D1, and then, the sacrificial layers SL may be removed using an etch recipe, which has an etch selectivity with respect to the insulating layers ILD, the vertical channel structures VS, and the horizontal layer100. Next, the electrodes EL may be formed by a deposition process of filling empty spaces, which are formed by removing the sacrificial layers SL, with a conductive material. The electrodes EL, along with the insulating layers ILD, may constitute the electrode structure ST.

Referring back toFIG.23, the first interlayer insulating layer112and the second interlayer insulating layer114may be formed on the planarization insulating layer150. Next, a mask pattern MK may be formed on the second interlayer insulating layer114. The mask pattern MK may include patterning holes H having at least two different depths. The depths of the patterning holes H in the mask pattern MK may vary depending on depths of vertical holes VH to be formed in a subsequent process. The formation of the mask pattern MK may include forming a preliminary mask layer on the second interlayer insulating layer114and patterning the preliminary mask layer through a photolithography process using an optical mask OM as a photomask.

For example, referring toFIGS.23,24, and25, the preliminary mask layer may be thickly formed on the top surface of the second interlayer insulating layer114. The preliminary mask layer may be formed of or include, for example, a photoresist material. In an example embodiment, the preliminary mask layer may be formed using a spin coating process. Next, the preliminary mask layer may be irradiated with a transmission light Ltr passing through the optical mask OM. The optical mask OM may be formed to have openings OP exposing the preliminary mask layer. A portion of an input light Lin, which is incident into a surface of the optical mask OM, may form the transmission light Ltr that passes through the openings OP and is incident into the preliminary mask layer. Thereafter, the mask pattern MK may be formed by developing the preliminary mask layer irradiated with the transmission light Ltr.

A light amount of the transmission light Ltr may be controlled by light-amount control patterns LCP. For example, the openings OP may include a first opening OP1, a second opening OP2, and a third opening OP3that are used to form patterning holes H1, H2, and H3, which have different depths from each other, in the mask pattern MK. Each of the first, second, and third openings OP1, OP2, and OP3may have a circular shape, when viewed in a plan view. The light-amount control patterns LCP may be formed in the second and third openings OP2and OP3. In an example embodiment, each of the light-amount control patterns LCP may be a ring-shaped pattern, when viewed in a plan view. For example, the light-amount control patterns LCP may include a plurality of concentric ring-shaped patterns which have diameters different from each other. A light amount of the transmission light Ltr may vary depending on a planar area of the light-amount control patterns LCP occupying the opening OP2or OP3. The planar area of the light-amount control patterns LCP in the third opening OP3may be smaller than the planar area of the light-amount control pattern LCP in the second opening OP2, and a light amount per unit area of the transmission light Ltr passing through the third opening OP3may be smaller than a light amount per unit area of the transmission light Ltr passing through the second opening OP2. In an example embodiment, the light amount of the transmission light Ltr may vary depending on the number of the light-amount control patterns LCP in each of the openings OP1, OP2, and OP3. For example, the number of the light-amount control pattern LCP in the third opening OP3may be greater than the number of the light-amount control pattern LCP in the second opening OP2, and the light amount per unit area of the transmission light Ltr passing through the third opening OP3may be smaller than the light amount per unit area of the transmission light Ltr passing through the second opening OP2.

In an example embodiment, the light-amount control patterns LCP may have a stripe shape and may be provided to cross the second and third openings OP2and OP3in a specific direction.

Due to the afore-described difference in the light amount per unit area of the transmission light Ltr, the patterning holes H1, H2, and H3may be formed in the mask pattern MK to have different depths from each other. A depth of a second patterning hole H2corresponding to the second opening OP2may be smaller than a depth of a first patterning hole H1corresponding to the first opening OP1and may be larger than a depth of a third patterning hole H3corresponding to the third opening OP3. In an example embodiment, the light-amount control patterns LCP may not be provided in the first opening OP1, and the first patterning hole H1may be formed to vertically penetrate the mask pattern MK and to expose the top surface of the second interlayer insulating layer114.

In an example embodiment, the optical mask OM may be placed on a top surface of the preliminary mask layer such that it vertically overlaps the preliminary mask layer. However, in an example embodiment, the optical mask OM may be placed on a propagation path of the input light Lin, which is incident into the mask pattern MK, not on the top surface of the preliminary mask layer.

In an example embodiment, an exposure process for forming the mask pattern MK may be performed using a reflection-type optical mask, not using a transmission-type optical mask. In an example embodiment, the mask pattern MK may be formed by a lithography process using extreme ultraviolet (EUV) light. The lithography process using the EUV light may include performing an exposing process of irradiating the EUV light onto a photoresist layer and performing a developing process. As an example, the photoresist layer may be an organic photoresist layer containing an organic polymer (e.g., polyhydroxystyrene). The organic photoresist layer may further include a photosensitive compound, which can react with the EUV light. The organic photoresist layer may further contain a material having high EUV absorptivity (e.g., organometallic materials, iodine-containing materials, or fluorine-containing materials). As another example, the photoresist layer may be an inorganic photoresist layer containing an inorganic material (e.g., tin oxide).

Referring toFIGS.23and26, the vertical holes VH having at least two different depths may be formed by performing an etching process using the mask pattern MK as an etch mask. The depths of the vertical holes VH may depend on the depths of the patterning holes H. The vertical holes VH may be formed to penetrate the first interlayer insulating layer112and the second interlayer insulating layer114and may have bottom surfaces that are located at a level lower than the top surface of the planarization insulating layer150. For example, the bottom surfaces of the vertical holes VH on the top surface of the horizontal layer100may be located at a level higher than the top surface of the horizontal layer100.

Referring toFIG.27, the contact plug CP, the vertical conductive structures VCS1, VCS2, and VCS3, and the penetration vias TV may be formed. The formation of the contact plug CP, the vertical conductive structures VCS1, VCS2, and VCS3, and the penetration vias TV may include filling the vertical holes VH with a conductive material. For example, the conductive material may include tungsten. In an example embodiment, a planarization process may be performed on the conductive material, after the filling of the vertical holes VH. Accordingly, the contact plug CP, the vertical conductive structures VCS1, VCS2, and VCS3, and the penetration vias TV may have top surfaces that are substantially coplanar with each other.

Referring back toFIG.7, the third interlayer insulating layer116may be formed on the second interlayer insulating layer114, and the bit line plugs BP and the upper plug UP may be formed to penetrate at least a portion of the interlayer insulating layers112,114, and116. Thereafter, the bit lines BL and the upper interconnection lines CL may be formed on the third interlayer insulating layer116. The formation of the bit lines BL and the upper interconnection lines CL may include forming a conductive layer on the third interlayer insulating layer116and patterning the conductive layer. The upper interconnection lines CL may be patterned to connect the contact plugs CP to the penetration vias TV. In an example embodiment, the upper interconnection lines CL may be patterned to connect the contact plugs CP to the penetration vias TV in a one-to-one manner.

According to an example embodiment of the inventive concepts, vertical conductive structures may be formed in a planarization insulating layer covering a memory structure. The vertical conductive structures may mitigate or prevent a semiconductor device from being deformed, and thus, it may be possible to improve durability of the semiconductor device and to mitigate or prevent a crack from occurring in regions adjacent to a penetration interconnection region.

Further, the vertical conductive structures may be configured to exhaust impurity gases in the semiconductor device, and thus, it may be possible to reduce a failure rate in a process of fabricating the semiconductor device and to improve reliability of the semiconductor device.

While some example embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.