Patent ID: 12200761

DETAILED DESCRIPTION

FIG.1shows a network device that may be include the transceiver described herein. The network device10has a processing unit20and an associated memory device25. The processing unit20may be any suitable component, such as a microprocessor, embedded processor, an application specific circuit, a programmable circuit, a microcontroller, or another similar device. The memory device25contains the instructions, which, when executed by the processing unit20, enable the network device10to perform the functions described herein. This memory device25may be a non-volatile memory, such as a FLASH ROM, an electrically erasable ROM or other suitable devices. In other embodiments, the memory device25may be a volatile memory, such as a RAM or DRAM. The instructions contained within the memory device25may be referred to as a software program, which is disposed on a non-transitory storage media.

The network device10also includes a network interface30, which may be a wireless network interface that includes an antenna37. The network interface30may support any wireless network protocol that supports range detection, such as Bluetooth. The network interface30is used to allow the network device10to communicate with other devices disposed on the network39.

The network interface30includes a transceiver31. This transceiver31is used to process the incoming signal and convert the wireless signals to digital signals. The transceiver31is also used to transmit outgoing signals. The components within the transceiver31are described in more detail below.

The transceiver31includes a receive circuit36. The receive circuit36is used to receive, synchronize and decode the digital signals received from the antenna37. Specifically, the receive circuit36has a preamble detector that is used to identify the start of an incoming packet. The receive circuit36also has a sync detector, which is used to identify a particular sequence of bits that are referred to as a sync character. Additionally, the receive circuit36has a decoder which is used to convert the digital signals into properly aligned bytes of data.

The network interface30also includes a transmit circuit38. The transmit circuit38may include a power amplifier that is used to supply a signal to be transmitted to the antenna37.

The network device10may include a second memory device40. Data that is received from the network interface30or is to be sent via the network interface30may also be stored in the second memory device40. This second memory device40is traditionally a volatile memory.

While a memory device25is disclosed, any computer readable medium may be employed to store these instructions. For example, read only memory (ROM), a random access memory (RAM), a magnetic storage device, such as a hard disk drive, or an optical storage device, such as a CD or DVD, may be employed. Furthermore, these instructions may be downloaded into the memory device25, such as for example, over a network connection (not shown), via CD ROM, or by another mechanism. These instructions may be written in any programming language, which is not limited by this disclosure. Thus, in some embodiments, there may be multiple computer readable non-transitory media that contain the instructions described herein. The first computer readable non-transitory media may be in communication with the processing unit20, as shown inFIG.1. The second computer readable non-transitory media may be a CDROM, or a different memory device, which is located remote from the network device10. The instructions contained on this second computer readable non-transitory media may be downloaded onto the memory device25to allow execution of the instructions by the network device10.

While the processing unit20, the memory device25, the network interface30and the second memory device40are shown inFIG.1as separate components, it is understood that some or all of these components may be integrated into a single electronic component. Rather,FIG.1is used to illustrate the functionality of the network device10, not its physical configuration.

Although not shown, the network device10also has a power supply, which may be a battery or a connection to a permanent power source, such as a wall outlet.

FIG.2shows a block diagram of the receive circuit36. The wireless signals first enter the transceiver31through the antenna37. This antenna37is in electrical communication with a low noise amplifier (LNA)51. The LNA51receives a very weak signal from the antenna37and amplifies that signal while maintaining the signal-to-noise ratio (SNR) of the incoming signal. The amplified signal is then passed to a mixer52. The mixer52is also in communication with a local oscillator53, which provides two phases to the mixer52. The cosine of the frequency may be referred to as Io, while the sine of the frequency may be referred to as Qo, together called the complex Io/Qosignal. Using the mixer52, the complex Io/Qosignal is then multiplied by the incoming signal to create the complex Im/Qmsignal. The inphase signal, Im, and the quadrature signal, Qm, from the mixer52are then fed into programmable gain amplifier (PGA)54. The PGA54amplifies the Imand Qmsignals by a programmable amount. These amplified signals are referred to as Igand Qg. The amplified signals, Igand Qg, are then fed from the PGA54into an analog to digital converter (ADC)55. The ADC55converts these analog signals to digital signals, Idand Qd. These digital signals may pass through channel filter56then exit the transceiver31as I and Q. The channel filter56is programmable for a particular frequency and bandwidth. For example, the channel filter56may have an input that provides the channel settings57, such as center frequency and bandwidth, to be used. In certain embodiments, the channel filter56may comprise a complex digital mixer, a complex digital oscillator and two digital lowpass filters. The complex digital mixer provides complex multiplication by multiplying the complex Idand Qd signals with the complex signals from the complex digital oscillator. The complex output of the digital mixer is fed to the input of a digital lowpass filters, where one digital lowpass filter is used for the inphase channel and the other is used for the quadrature channel. The outputs of the digital filters may provide the I and Q outputs of the channel filter56. This allows for configuring the center frequency by setting the frequency of the complex digital oscillator and the bandwidth by configuring the digital lowpass filters. Decimation filters, DC cancelation circuits, IQ calibration circuits, and other circuits may all be part of the channel filter56, as those of ordinary skill in the art will recognize. Alternatively, the center frequency may be changed by configuring the Local Oscillator53to tune the receiver to the desired channel.

The I and Q signals then enter a Radio Signal Strength Indicator (RSSI) detector58, which is used to measure the energy in the received signal. In certain embodiments, the RSSI detector58comprises a magnitude detector, which determines the magnitude of the incoming signals as √{square root over (I2+Q2)}. In certain embodiments, this magnitude detector may be incorporated in a CORDIC, which may be dedicated to the RSSI detector58. Alternatively, the CORDIC may be used for other functions as well, such as determining phase which may be used by other components in the transceiver31.

This magnitude may then be the input to a log converter, which converts the magnitude from the linear domain to a logarithmic domain. The output of the log converter may then serve as an input to a filter, which may be used to average the information. Alternatively, the filter may be placed before the log converter to filter the magnitude signal in the linear domain. The output from the RSSI detector58is then provided to a threshold comparator59. If the energy detected by the RSSI detector58is less than a predetermined threshold, the threshold comparator59outputs a signal that indicates that the channel is clear, referred to as channel below threshold or CBT. If the energy detected by the RSSI detector58is greater than a predetermined threshold, the threshold comparator59outputs a signal that indicates that the channel is busy, referred to as channel above threshold or CAT. Note that the described RSSI detection is also known as energy detection or “energy above threshold”.

The channel filter56, the RSSI detector58and the threshold comparator59may together be considered to be the CCA block60. Based on the inputs supplied to the channel filter56, the CCA block60provides a channel clear signal for a specific frequency band. In other words, the term “channel” refers to a specific range of frequencies. Note that multiple CCA blocks may be incorporated in the receive circuit36so that multiple frequency bands may be monitored simultaneously.

Instead of using RSSI for CCA, those skilled in the art would recognize that other characteristics may be used as well. For example, Carrier Sense may be used, as is published in the IEEE 802.15.4-2020 standard. Using Carrier Sense, CCA shall report a busy medium upon detection of a signal with the same modulation and spreading characteristics of the PHY that is intended for that channel. Alternatively, Carrier Sense could be combined with RSSI detection, such as by applying OR or AND functions to the outputs of the RSSI detector and the Carrier Sense detector.

Having described the architecture of the network device10, its operation when used in a multi-PHY network will be described. In certain network protocols, such as the WiSUN Field Area Network (FAN) protocol, the transmitting node sends a receiving node a first packet, referred to as a MODE SWITCH packet, informing the receiving node that the next packet will be sent using a different PHY mode. The transmitting node then sends a second packet, referred to as the NEW PHY MODE packet.

A PHY mode is a set of parameters that define the characteristics of a packet. These parameters may include modulation type, encoding scheme, bit rate, data rate, baud rate and other parameters.

The processing of the CCA completes when it produces either a clear channel indication, also referred to as CCA succeed, or a busy channel indication, also referred to as CCA fail. Using a conventional CCA scheme, the following steps are typically performed when mode switching is used, such as per WiSUN FAN 1.1. First, a network device10, which is referred to the transmitting node, must set the channel settings57so as to correspond to the frequency and bandwidth associated with the first PHY mode that is intended for transmission on that channel. This may be the PHY mode used for the MODE SWITCH packet. Once the channel filter is configured, the receiver will be enabled. A backoff time may be included before the start of CCA but typically the backoff time is zero before the first CCA attempt and gradually increases when CCA retries accumulate. Once CCA commences, the receiver on-time is long enough to settle the RSSI value. After some time, the CCA completes by checking the output of the threshold comparator59in CCA block60. The CCA block60may return a channel clear indication (CBT), at which time, the transmitting node may transmit the MODE SWITCH packet.

Once this MODE SWITCH packet has been transmitted, a similar CCA process as described for the MODE SWITCH packet is then performed prior to transmitting the NEW PHY MODE packet. The transmitting node must then set the channel settings57so as to correspond to the frequency and bandwidth associated with the second PHY mode, which corresponds to the NEW PHY MODE packet. After the CCA completes, the CCA block60may return a channel clear indication, at which time, the transmitting node may transmit the NEW PHY MODE packet.

As explained above, there are various issues associated with this approach. For example, after sending the MODE SWITCH packet, the transmitting node may not receive an indication of a clear channel for the second PHY mode within the predetermined time duration. Thus, the transmitting node will not send the NEW PHY MODE packet and will return to the first PHY mode. However, the receiving node may still be configured for the second PHY mode, and therefore cannot receive packets from the transmitting node until the receiving node returns to the MODE SWITCH PHY MODE, also known as the base PHY mode.

The present disclosure described several embodiments to overcome this shortcoming.

FIG.3shows a portion of a network device10that utilizes the receive circuit36ofFIG.2to enable the transmit circuit38. In this embodiment, the receive circuit36comprises only one CCA block60. The network device10also includes a Channel Access Controller100. In some embodiments, the Channel Access Controller100may be implemented in hardware. In other embodiments, the Channel Access Controller100may be implemented in software executing on processing unit20.

The network device10also includes a protocol processor110. In some embodiments, the protocol processor110may be implemented in hardware. In other embodiments, the protocol processor110may be implemented in software executing on processing unit20.

The protocol processor110operates in conjunction with the Channel Access Controller100to configure the receive circuit36and enable the transmit circuit38. In some embodiments, the Channel Access Controller100and the protocol processor110may share hardware or may be combined into a single hardware or software component. In other embodiments, the Channel Access Controller may be implemented as part of a receiver/transmitter controller, also referred to as the Radio Controller. A Radio controller is commonly used in many Wireless SoC products where it controls PHY settings, activates the receiver or transmitter and to support radio functions.

FIG.4shows a sequence of operations, using the receive circuit36ofFIG.3according to one embodiment. First, as shown in Box400, a clear channel test for channel2is performed. In these figures, a clear channel test comprises the following steps. First, the receive circuit36waits a predetermined backoff delay time. Note that typically the backoff time is zero before the first CCA attempt and gradually increases when CCA retries accumulate. After this backoff delay time, the receive circuit36is enabled, with the channel settings configured for the desired PHY mode, and time is allowed for RSSI settling. Then the Channel Access Controller100checks the CAT and CBT outputs of receive circuit36. If the energy is above a predetermined threshold, as indicated by CAT, an indication that the channel is busy is provided. This indication must be referred to as CCAx Failure. If the energy is below the predetermined threshold, as indicated by CBT, an indication that the channel is clear, referred to as CCAx Success, is provided. The sequence shown inFIG.4may be controlled by the Channel Access Controller100or the Protocol Processor110or a combination thereof.

To perform a clear channel test for channel2, the Channel Access Controller100may provide channel settings57to the receive circuit36associated with the second PHY mode, which operates on the second channel.

The clear channel test for channel2either returns CCA2Failure or CCA2Success. If the clear channel test fails, the Channel Access Controller100adjusts the backoff delay time, as shown in Box410. If the delay is less than a threshold value, the Channel Access Controller100performs another clear channel test for channel2. If the number of retries has been exhausted, the Channel Access Controller100indicates that the operation has failed, as shown in Box460.

If the clear channel test for channel2succeeds, the Channel Access Controller100performs a clear channel test for channel1, as shown in Box420. To perform a clear channel test for channel1, the Channel Access Controller100may provide channel settings57to the receive circuit36associated with the first PHY mode, which operates on the first channel.

The clear channel test for channel1either returns CCA1Failure or CCA1Success. If the clear channel test fails, the Channel Access Controller100adjusts the backoff delay time, as shown in Box430. If the delay is less than a threshold value, the Channel Access Controller100performs another clear channel test for channel1. If the number of retries has been exhausted, the Channel Access Controller100indicates that the operation has failed, as shown in Box460.

If the clear channel test for channel1succeeds, the protocol processor110indicates that the transmit circuit38may transmit the MODE SWITCH packet, as shown in Box440. The protocol processor110may provide an enable signal to the transmit circuit38, along with the PHY mode to be used, which is the first PHY mode.

Once the MODE SWITCH packet has been transmitted, the protocol processor110may provide an enable signal to the transmit circuit38, along with the PHY mode to be used, which is the second PHY mode. The NEW PHY MODE packet may now be transmitted, as shown in Box450.

By performing the two CCA tests during a first time period, and the transmissions during a second time period, where the second time period commences after the first period time, this embodiment ensures that both channels are clear prior to transmitting either packet. This may reduce the possibility that the MODE SWITCH packet is delivered, but the NEW PHY MODE packet is not delivered, thereby saving bandwidth and power.

Further, in certain embodiments, the sequence may be switched such that the clear channel test is performed for channel1first.

FIG.5Ashows a sequence of operations using the receive circuit36ofFIG.3according to a second embodiment. In this embodiment, the channel filter56is designed such that its bandwidth may encompass both the first channel and the second channel.FIG.5Bshows the first frequency range550used by the first channel, and the second frequency range551used by the second channel. In this embodiment, the channel settings57are such that the bandwidth of the channel filter56creates a frequency range552that encompasses both the first channel and the second channel. In this way, if the clear channel test fails, it cannot be determined which channel was busy. However, if the clear channel test succeeds, both channels are assumed to be clear.

As shown inFIG.5A, to perform a clear channel test for the combined channel, the Channel Access Controller100may provide channel settings57to the receive circuit36that encompass both the first channel and the second channel.

As shown in Box500, the clear channel test for combined channel either returns COMB CCA Failure or COMB CCA Success. If the clear channel test fails, the Channel Access Controller100adjusts the backoff delay time, as shown in Box510. If the delay is less than a threshold value, the Channel Access Controller100performs another clear channel test for the combined channel. If the number of retries has been exhausted, the Channel Access Controller100indicates that the operation has failed, as shown in Box540.

If the clear channel test for the combined channel succeeds, the protocol processor110indicates that the transmit circuit38may transmit the MODE SWITCH packet, as shown in Box520. The protocol processor110may provide an enable signal to the transmit circuit38, along with the PHY mode to be used, which is the first PHY mode.

Once the MODE SWITCH packet has been transmitted, the protocol processor110may provide an enable signal to the transmit circuit38, along with the PHY mode to be used, which is the second PHY mode. The NEW PHY MODE packet may now be transmitted, as shown in Box530. The sequence shown inFIG.5Amay be controlled by the Channel Access Controller100or the Protocol Processor110or a combination thereof.

FIG.6shows a portion of a network device10that utilizes the receive circuit36ofFIG.2to enable the transmit circuit38. In this embodiment, the receive circuit36comprises two CCA blocks60, where each CCA block60comprises a channel filter56, RSSI detector58and threshold comparator59. Each CCA block60may be independently configured using its own set of channel settings57, and provides its own CAT and CBT outputs.

Thus, in one embodiment, the sequence shown inFIG.4may be performed using a receive circuit36with two CCA blocks60. In other words, the Channel Access Controller100may choose to check each channel sequentially, as shown inFIG.4.

However, the sequence shown inFIG.4may be optimized by performing the two clear channel tests simultaneously. The receiver on-time, and hence the power consumption, can be reduced by processing two clear channel tests simultaneously. An additional benefit is a reduced latency between the clear channel tests and the subsequent transmission. This embodiment is shown inFIG.7. First, the Channel Access Controller100may configure the first and second CCA blocks with the channel setting57for the first channel and second channel, respectively.

As shown in Box700, the clear channel test for channel1may commence. This may be at the same time as the clear channel test for channel2, as shown in Box710. As described above, the clear channel test for channel1either returns CCA1Failure or CCA1Success. If the clear channel test for channel1fails, the Channel Access Controller100adjusts the backoff delay time, as shown in Box720. If the delay is less than a threshold value, the Channel Access Controller100performs another clear channel test for channel1. If the number of retries has been exhausted, the Channel Access Controller100indicates that the operation has failed, as shown in Box760.

Simultaneously, the clear channel test for channel2either returns CCA2Failure or CCA2Success. If the clear channel test for channel2fails, the Channel Access Controller100adjusts the backoff delay time, as shown in Box730. If the delay is less than a threshold value, the Channel Access Controller100performs another clear channel test for channel2. If the number of retries has been exhausted, the Channel Access Controller100indicates that the operation has failed, as shown in Box760.

If the clear channel tests for both channel1and channel2succeed, the protocol processor110indicates that the transmit circuit38may transmit the MODE SWITCH packet, as shown in Box740. The protocol processor110may provide an enable signal to the transmit circuit38, along with the PHY mode to be used, which is the first PHY mode.

Once the MODE SWITCH packet has been transmitted, the protocol processor110may provide an enable signal to the transmit circuit38, along with the PHY mode to be used, which is the second PHY mode. The NEW PHY MODE packet may now be transmitted, as shown in Box750. The sequence shown inFIG.7may be controlled by the Channel Access Controller100or the Protocol Processor110or a combination thereof.

Thus, each of the embodiments shown inFIGS.4,5A and7illustrate a sequence wherein, during a first time period, the network device ensures that both the first channel and the second channel are clear. During the second time period, which follows the first time period, the network device transmits two packets, using different PHY modes. These two packets may be a MODE SWITCH packet, which informs the receiving node that the next packet will be transmitted using a different PHY mode; and a NEW PHY packet, which is transmitted using the second PHY mode.

FIG.8shows a different sequence that can be performed using the network device10shown inFIG.6. In this configuration, it is assumed that the receiving node is able to receive packets transmitted using different channels without prior notification of which channel is to be used. An example of such receiver was disclosed in U.S. Patent Application Publication US20210135692A1. Without needing prior notification of which channel is used, this embodiment eliminates the need for a MODE SWITCH packet. This greatly improves the security of the network as all packets can be encrypted. Also, all packets can contain specific destination address supporting more efficient network traffic.

First, the Channel Access Controller100may configure the first and second CCA blocks with the channel setting57for the first channel and second channel, respectively.

As shown in Box800, the clear channel test for channel1may commence. This may be at the same time as the clear channel test for channel2, as shown in Box810. As described above, the clear channel test for channel1either returns CCA1Failure or CCA1Success. Simultaneously, the clear channel test for channel2either returns CCA2Failure or CCA2Success.

One of the two channels may be the preferred channel. For example, channel2may utilize a different PHY mode having a higher bit rate. Note that the preferred PHY mode may be selected based on other criteria, such as transmission range, Signal to Noise Ratio (SNR), link budget, or other criteria. In this scenario, channel2is a higher rate (HR) and may be preferred. Channel1may be considered the base PHY. In this example, it is assumed that Channel2is a higher rate channel and is therefore the preferred PHY mode.

Therefore, if the clear channel test for channel2succeeds, the protocol processor110may provide an enable signal to the transmit circuit38, along with the PHY mode to be used, which is the higher rate (HR) PHY mode, as shown in Box820. If, however, the clear channel test for channel2fails, but the clear channel test for channel1succeeds, the protocol processor110may provide an enable signal to the transmit circuit38, along with the PHY mode to be used, which is the base PHY mode, as shown in Box830. In this way the packet transmission does not have to be delayed until a subsequent retry.

If both clear channel tests fail, the operation may be considered failed. Although not shown, retries may be introduced into the sequence shown inFIG.8. For example, if the clear channel test for both channels fails, the sequence may include steps to adjust the delays for both channels and retry the clear channel test until the delays exceed a threshold. The sequence shown inFIG.8may be controlled by the Channel Access Controller100or the Protocol Processor110or a combination thereof.

FIG.8shows a sequence using concurrent performance of the clear channel tests. Those of ordinary skill in the art would recognize that the clear channel tests may also be performed sequentially using a single CCA block. For example, the clear channel test for the preferred PHY mode may be performed first. This is done by configuring the channel filter center frequency and bandwidth to the channel dedicated to the preferred PHY mode, enable the receiver and wait for the result. If the first clear channel test succeeds, the packet may be transmitted using the preferred PHY mode. If the first clear channel test fails, a second clear channel test may be performed by configuring the channel filter center frequency and bandwidth to the channel dedicated for the base PHY mode, enable the receiver and wait for the clear channel test result. If the second clear channel test succeeds, the packet may be transmitted using the base PHY. If the second clear channel test also fails, the Channel Access Controller100may either terminate or retry, with or without adjusted back-off delay. Other variants of this sequence may be used as well.

Note that the above description suggests that the different channels are associated with different PHY modes. However, other embodiments are also possible. For example, a wireless network protocol may utilize a single PHY mode with a plurality of frequency ranges. For example, the receive circuit ofFIG.6, which includes multiple CCA blocks60, may be utilized to simultaneously check multiple frequency channels. The network device10may then select a channel that returned a channel clear indication.

In another embodiment, the Channel Access Controller100may have access to the output of the RSSI detector58in each CCA block60. In this embodiment, the Channel Access Controller100may select the channel with the lowest energy and use this channel to transmit the outgoing packet.

The present system and method has many advantages. As described above, in current systems where different PHY modes are used, traditional network devices check the first channel. When it is clear, the network device transmits the MODE SWITCH packet. The network device then checks the second channel. When the second channel is clear, the second packet using the new PHY mode is transmitted. However, there are issues wherein the second channel may remain busy such that the network device cannot send the second packet. This causes the network device to abort to sequence, but the receiving node may still be awaiting a packet using the second PHY mode. By checking both channels before transmitting the MODE SWITCH packet, the probability that the second packet is not transmitted is greatly reduced. This improves throughput and reduces wanted power consumption.

The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.