Patent ID: 12242181

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A hard mask layer may be used as a pattern by which a pellicle frame of a photomask assembly is etched. A hard mask layer may be deposited onto a capping layer of the photomask assembly during manufacturing of the photomask assembly. A buffer layer may be formed between material of the pellicle frame and material of the capping layer to promote adhesion between the pellicle frame material and the capping layer material.

Due to the high extreme ultraviolet (EUV) light absorption of the buffer layer, a first portion of the buffer layer may be removed after the pellicle frame is etched based on the pattern of the hard mask layer. However, a second portion of the buffer layer remains between the pellicle frame of the photomask and the capping layer on which the hard mask layer was formed. A wet etch may be performed to remove the first portion of the buffer layer, which can cause the second portion of the buffer layer to be undercut. This undercutting of the second portion of the buffer layer between the pellicle frame of the photomask and the capping layer on which the hard mask layer was formed may cause the hard mask layer to become unstable and delaminate or peel away from the pellicle frame, resulting in damage to the pellicle layer and/or other components of the photomask assembly.

Some implementations described herein provide a photomask assembly, techniques and apparatuses for forming the photomask assembly, and a system in which the photomask assembly may be used. During manufacturing of the photomask assembly, a buffer layer may be deposited onto a substrate. A portion of the buffer layer on a backside of the substrate may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. A hard mask layer may be formed on the capping layer(s) on the backside of the substrate. The hard mask layer may be patterned, and the pattern may be used to etch the capping layer(s), the substrate, and one or more other layers to define the pellicle frame of the photomask assembly.

In this way, the capping layer(s) and the hard mask of a photomask assembly may be formed on the substrate without an intervening buffer layer. This may reduce the likelihood that the hard mask becomes unstable and delaminate or peel away from the frame of the photomask assembly. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.

FIG.1is a diagram of an example environment100in which systems and/or methods described herein may be implemented. As shown inFIG.1, environment100may include a plurality of semiconductor processing tools102-110and a transport device112. The plurality of semiconductor processing tools102-110may include a deposition tool102, an exposure tool104, an etch tool106, a developer tool108, a photoresist removal tool110, and/or other the like. The tools included in example environment100may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing and/or manufacturing facility, and/or the like.

The deposition tool102is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool102includes a chemical vapor deposition (CVD) tool, such as an atomic layer deposition (ALD) tool, an epitaxy tool, a metal organic CVD (MOCVD) tool, a plasma-enhanced CVD (PECVD) tool, or another type of CVD tool. In some implementations, the deposition tool102includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the example environment100includes a plurality of types of deposition tools102.

The exposure tool104is a semiconductor processing tool that is capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light source, and/or the like), an x-ray source, an electron beam (e-beam) source, and/or the like. The exposure tool104may expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include a pattern for forming one or more structures of a semiconductor device, may include a pattern for etching various portions of a semiconductor device, and/or the like. In some implementations, the exposure tool104includes a scanner, a stepper, or a similar type of exposure tool.

The etch tool106is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool106may include a wet etch tool, a dry etch tool, and/or the like. In some implementations, the etch tool106includes a chamber that is filled with an etchant, and the substrate is placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. In some implementations, the etch tool106may etch one or more portions of a the substrate using a plasma etch or a plasma-assisted etch, which may involve using an ionized gas to isotopically or directionally etch the one or more portions.

The developer tool108is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool104. In some implementations, the developer tool108develops a pattern by removing unexposed portions of a photoresist layer. In some implementations, the developer tool108develops a pattern by removing exposed portions of a photoresist layer. In some implementations, the developer tool108develops a pattern by dissolving exposed or unexposed portions of a photoresist layer through the use of a chemical developer.

The photoresist removal tool110is a semiconductor processing tool that is capable of removing remaining portions of a photoresist layer from a substrate after the etch tool106removes portions of the substrate. For example, the photoresist removal tool110may use a chemical stripper and/or another technique to remove a photoresist layer from a substrate.

Transport device112includes a mobile robot, a robot arm, a tram or rail car, an overhead hoist transfer (OHT) vehicle, and/or another type of device that are used to transport photomask assemblies (or components thereof), wafers, and/or dies between semiconductor processing tools102-110and/or to and from other locations such as a wafer rack, a storage room, and/or the like. In some implementations, transport device112may be a programmed device to travel a particular path and/or may operate semi-autonomously or autonomously.

The number and arrangement of devices shown inFIG.1are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or differently arranged devices than those shown inFIG.1. Furthermore, two or more devices shown inFIG.1may be implemented within a single device, or a single device shown inFIG.1may be implemented as multiple, distributed devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of environment100may perform one or more functions described as being performed by another set of devices of environment100.

FIG.2is a diagram of a cross-sectional view of an example photomask assembly200described herein. The photomask assembly200may be an apparatus that is used to transfer a pattern (e.g., a die layer pattern, an integrated circuit pattern, and/or the like) to a wafer or a substrate. In some implementations, the photomask assembly200may be used in an exposure tool (e.g., the exposure tool104, exposure tool500ofFIG.5, and/or another exposure tool). As shown inFIG.2, the photomask assembly200may include various components and/or subsystems, such as a cooling layer202, a pellicle210, a pellicle frame220, a photomask frame230, and a photomask240, among other examples.

The cooling layer202includes a layer of material that dissipates heat generated during a lithography patterning process. The heat dissipation properties of the cooling layer202may reduce warpage, deformation, and/or other heat-related degradations. In some implementations, the cooling layer202includes ruthenium (Ru), a carbon-based material (e.g., graphite, grapheme, diamond, carbon nanotube, and/or the like), or another thermally conductive material. The cooling layer202may have a thickness ranging from approximately 3 nanometers (nm) to approximately 10 nm.

The pellicle210may include a plurality of layers that perform different functions, such as a capping layer212on a function layer214, and another capping layer216on which the function layer214is formed. The pellicle210protects the photomask240from particles and other debris, and keeps the particles and other debris out of focus in the exposure tool so that the particles and other debris do not produce a patterned image, which may cause defects to be transferred to the wafer.

The capping layers212and216may protect the function layer214from chemicals and/or particles. For example, the function layer214may be formed of silicon, which may be susceptible to environmental chemicals and/or particles. The capping layers212and216may be thin without degrading the transparency of the pellicle210. In some examples, the thickness of the capping layers212and216range from approximately 3 nm to approximately 10 nm. In some examples, the thickness of each of the capping layers212and216is approximately 5 nm with a variation of approximately 10% or less.

The function layer214may include one or more materials including silicon, such as polycrystalline silicon (poly-Si), amorphous silicon (a-Si), doped silicon (such as phosphorous doped silicon (SiP)), or a silicon-based compound. Alternatively, the function layer214includes a polymer, grapheme, or other suitable material. The function layer214may be formed to a thickness such that the function layer214has sufficient mechanical strength while not degrading the transparency of the function layer214. In some examples, the function layer214may have a thickness ranging from approximately 30 nm to approximately 50 nm.

The pellicle210may be attached, bonded, glued, or otherwise secured to the pellicle frame220by a buffer layer218. The buffer layer218may be formed of an adhesive material such as a thermal plastic elastomer or other macromolecular adhesive material cured by heat or drying. In some implementations, the buffer layer218includes Styrene Ethylene/Butylene Styrene rubber (SEBS), Thermoplastic Polyester Elastomer (TPE), polyether urethane (TPU), Thermoplastic Olefinic elastomer (TPO), Thermoplastic Vulcanisate (TPV), or another adhesive material. The buffer layer218may also function as an etch-stop layer during manufacturing of the photomask assembly200due to the etching selectivity of the buffer layer218relative to the material of the pellicle frame220.

The pellicle frame220may be a mounting structure on which the pellicle210is mounted via the buffer layer218. The pellicle frame220may be formed of silicon, a silicon oxide (SiOx), or another material having sufficient rigidity to support the pellicle210(e.g., during lithography patterning process). As shown inFIG.2, the pellicle frame220may have a plurality of sides222, such as an inner side222a(e.g., which may be angled, straight, curved, or formed of a different geometry), an outer side222b, a top side222cfacing the pellicle210, and a bottom side222dfacing the photomask frame230and the photomask240. The pellicle210may be bonded to the top side222cof the pellicle frame220. In particular, the capping layer216of the pellicle210may be bonded to an outer portion of the top side222c(e.g., a portion of the top side222ctoward or located near the outer side222b) via the buffer layer218.

A lower capping layer224may be located on the bottom side222dof the pellicle frame220. The lower capping layer224may be formed during formation of the capping layers212and216, and may be formed from a combination of the capping layers212and216. Unlike the capping layers212and216, the lower capping layer224may be formed directly on the pellicle frame220(e.g., without an intervening buffer layer between the bottom side222dof the pellicle frame220and the lower capping layer224).

The lower capping layer224may be formed during formation of the capping layer212and the capping layer216. In some implementations, the lower capping layer224is a single continuous capping layer directly on the bottom side222dof the pellicle frame220. In some implementations, the lower capping layer224includes two or more layers formed as a part of two or more deposition procedures. For example, a first layer of the lower capping layer224may be formed directly on the pellicle frame220during deposition of the capping layer216and a second layer of the lower capping layer224may be formed directly on the first layer during deposition of the capping layer212. In these examples, a thin layer of native oxide material may be present between the two or more capping layers of the lower capping layer224.

In some implementations, the capping layer212, the capping layer216, and the lower capping layer224are formed of a low-stress material (e.g., a low tensile strength material) to promote adhesion between the pellicle frame220and the capping layer212, the capping layer216, and the lower capping layer224. As indicated above, the lower capping layer224is formed directly on the pellicle frame, which may result in a lattice mismatch between the material of the lower capping layer and a material of the pellicle frame. The lattice mismatch may cause warping, peeling, and/or delamination of the lower capping layer224if the lower capping layer224is formed of a material that is too stiff (e.g., a high tensile strength material). Accordingly, the capping layer212, the capping layer216, and the lower capping layer224may be formed of the low-stress material to reduce warping of the pellicle frame220, to reduce peeling and/or delamination of the lower capping layer224that might otherwise occur due to the lattice mismatch.

The low-stress material may be a material having a tensile strength that is lower than the material of the pellicle frame220. In some implementations, the low-stress material is a material having a tensile strength of less than approximately 600 megapascals. Examples of low-stress materials that may be used to form the capping layer212, the capping layer216, and the lower capping layer224include (but are not limited to) a silicon oxide (SiOx), a silicon nitride (SixNy), or a boron nitride (BN).

A hard mask layer226may be located on the lower capping layer224over the bottom side222dof the pellicle frame220. The hard mask layer226may be used during etching of the pellicle frame220. In particular, a pattern may be formed in the hard mask layer226, and the pellicle frame220may be etched based on the pattern in the hard mask layer226. The hard mask layer226may be formed of a material having an etch selectivity that permits the pellicle frame220to be etched based without (or with minimal) etching of the hard mask layer226. In some implementations, the material of the hard mask layer226includes ruthenium (Ru), ruthenium silicon (RuSi), a combination thereof, or another hard mask material.

The pellicle frame220may be attached, bonded, glued, or otherwise secured to the photomask frame230. In particular, the pellicle frame220may attach to the photomask frame230at the hard mask layer226. In some implementations, the photomask frame230may attach to the hard mask layer226via a buffer layer228. The buffer layer228may be formed of an adhesive material such as a thermal plastic elastomer or other macromolecular adhesive material cured by heat or drying. In some implementations, the buffer layer228includes SEBS, TPE, TPU, TPO, TPV, or another adhesive material.

The photomask frame230may hold and/or support the pellicle frame220and the pellicle210. The photomask frame230may be used to mount the pellicle frame220and the pellicle210to the photomask240. The height of the pellicle frame220and the photomask frame230may be configured such that particles and/or other debris that lands on the surface of the pellicle210are out of focus during a lithography exposure process and are not transferred to the wafer.

The photomask frame230may include one or more components to reduce the transfer of force between the pellicle frame220and the photomask240, to allow for ventilation of an internal cavity of the photomask assembly200between the pellicle210and the photomask240, and/or the like. For example, the photomask frame230may include a bracket232that is mounted to a sidewall234. A filter236may be placed between the bracket232and the sidewall234to allow for ventilation and pressure balance in the internal cavity during pressurization of the exposure tool. Moreover, the photomask frame230may include a gasket238to provide structural isolation between the photomask frame230and the photomask240. The gasket238may reduce or prevent vibration and/or other mechanical stresses from being transferred from the photomask frame230to the photomask240.

The photomask frame230may be attached, bonded, glued, or otherwise secured to the photomask240via a buffer layer242. The buffer layer242may be formed of an adhesive material such as a thermal plastic elastomer or other macromolecular adhesive material cured by heat or drying. In some implementations, the buffer layer242includes SEBS, TPE, TPU, TPO, TPV, or another adhesive material.

The photomask240may include a pattern that is to be transferred to a resist layer on the wafer during a lithography patterning process. The photomask240may be formed by one or more photomask fabrication processes, such as a mask blank fabrication process, a mask patterning process, and/or the like. During a mask blank fabrication process, a mask blank is formed by depositing suitable layers (e.g., a plurality of reflective layers, a plurality of refractive layers, and/or the like) on a suitable substrate. In some implementations, the surface roughness of the mask blank is less than approximately 50 nm.

A capping layer (e.g., ruthenium) may be formed over the multilayer coated substrate followed by deposition of an absorber layer. The mask blank may then be patterned (e.g., the absorber layer is patterned) to form a desired pattern on the photomask240. In some implementations, an anti-reflective coating (ARC) layer may be deposited over the absorber layer prior to patterning the mask blank. The patterned photomask240may then be used to transfer circuit and/or device patterns onto the wafer.

In some implementations, the photomask240may be fabricated to include different structure types such as, for example, a binary intensity mask (BIM) or a phase-shifting mask (PSM). An example BIM includes opaque absorbing regions and reflective regions, where the BIM includes a pattern (e.g., an integrated circuit pattern) to be transferred to the wafer. The opaque absorbing regions include an absorber that is configured to absorb incident light (e.g., incident EUV light). In the reflective regions, the absorber may be removed (e.g., during the mask patterning process described above) and the incident light is reflected by the multilayer. Additionally, in some implementations, the photomask240may be a PSM which utilizes interference produced by phase differences of light reflected therefrom. Examples of PSMs include an alternating PSM (AltPSM), an attenuated PSM (AttPSM), or a chromeless PSM (cPSM), among other examples. An AltPSM may include phase shifters (of opposing phases) disposed on either side of each patterned mask feature. In some examples, an AttPSM may include an absorber layer having a transmittance greater than zero (e.g., approximately a 6% intensity transmittance). In some cases, a cPSM may be described as a 100% transmission AltPSM, for example, because the cPSM does not include phase shifter material or chrome on the mask. In some implementations, the patterned layer of a PSM is a reflective layer with a material stack similar to that of a multi-layer structure.

In some implementations, the photomask assembly200includes other components, different components, and/or differently arranged components depending on the type of exposure tool in which the photomask assembly200is to be used. For example, if the photomask assembly200is to be used in a refractive-based exposure tool (e.g., a tool in which radiation energy is to travel through the photomask assembly200), the photomask assembly200may include a transparent substrate and an absorption layer that is patterned to have one or more openings through which the radiation energy may travel without being absorbed by the absorption layer. As another example, if the photomask assembly200is to be used in a reflective-based exposure tool (e.g., an exposure tool in which radiation energy is to be reflected off of the photomask assembly200), the photomask assembly200may include a substrate coated with a plurality of films to provide a reflective mechanism. In these cases, the photomask assembly200may include a plurality of alternating layers of silicon and molybdenum deposited on a substrate to act as a Bragg reflector that maximizes the reflection of the radiation energy.

The number and arrangement of components, structures, and/or layers shown inFIG.2are provided as one or more examples. In practice, there may be additional components, structures, and/or layers; fewer components, structures, and/or layers; different components, structures, and/or layers; and/or differently arranged components, structures, and/or layers than those shown inFIG.2.

FIGS.3A-3Mare diagrams illustrating one or more example implementations300described herein. In some implementations, example implementation(s)300may be example implementation(s) of forming a photomask assembly, such as the photomask assembly200ofFIG.2and/or other photomask assemblies having stress relief trenches formed therein.

FIG.3Aillustrates a top-down view and a cross-sectional view along line AA of a substrate302. The substrate302may include a wafer (e.g., a 200 mm wafer, a 300 mm wafer, and/or the like) formed of silicon, crystal silicon, polycrystalline silicon, amorphous silicon, or another material.

FIG.3Billustrates another top-down view and another cross-sectional view along the line AA of the substrate302. As shown inFIG.3B, one or more semiconductor processing tools may form a buffer layer218. For example, the deposition tool102may form the buffer layer218by a deposition process, such as a spin-coating process, a PVD process, a CVD process, an ALD process, or another type of deposition process. In some implementations, the deposition tool102forms the buffer layer218on a top side of the substrate302. In some implementations, the deposition tool102forms the buffer layer218around the substrate302such that the buffer layer218is formed on the top side, on a bottom side (or back side), on a left side, and on a right side of the substrate302.

FIG.3Cillustrates a bottom-up view and another cross-sectional view along line AA of the substrate302. As shown inFIG.3C, one or more semiconductor processing tools may remove a portion of the buffer layer218from the substrate302. In particular, one or more semiconductor processing tools may remove a portion of the buffer layer218from the bottom side (or the back side) of the substrate302. In some implementations, the one or more semiconductor processing tools may remove a portion of the buffer layer218from the left side and/or from the right side of the substrate302(or from a portion thereof). In some implementations, the deposition tool102may form a photoresist layer on the buffer layer218, the exposure tool104may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool108may develop and remove portions of the photoresist layer to expose the pattern, the etch tool106may etch the portion of the buffer layer218on the bottom side of the substrate302, and the photoresist removal tool110may remove the remaining portions of the photoresist layer (e.g., using a chemical stripper and/or another technique) after the etch tool106etches the portion of the buffer layer218.

FIGS.3D-3Fillustrate respective top-down views and respective cross-sectional views along the line AA of the substrate302. As shown inFIGS.3D-3F, one or more semiconductor processing tools may form a plurality of layers to form a pellicle210and to form a lower capping layer224. For example, the deposition tool102may form the plurality of layers by a deposition process, such as a spin-coating process, a PVD process, a CVD process, an ALD process, or another type of deposition process. The deposition tool102may form one or more of the plurality of layers on the buffer layer218over the top side of the substrate302, and may form one or more of the plurality of layers over and/or on the back side or the bottom side of the substrate302. In some implementations, the deposition tool102forms one or more of the plurality of layers around the substrate302(e.g., over the top side, over the bottom side, over the left side, and over the right side).

As shown inFIG.3D, the deposition tool102may deposit the capping layer216of the pellicle210on the buffer layer218, and may deposit a first portion of the lower capping layer224directly on the bottom side or the back side of the substrate302(e.g., without an intervening buffer layer between the first portion of the lower capping layer224and the substrate302). The capping layer216and the first portion of the lower capping layer224may be formed as part of the same deposition procedure. The capping layer216and the first portion of the lower capping layer224may be formed of a low-stress material having a tensile strength of less than approximately 600 megapascals (e.g., a silicon oxide (SiOx), a silicon nitride (SixNy), a boron nitride (BN), or another material having a tensile strength of less than approximately 600 megapascals) to promote adhesion between the lower capping layer224and the substrate302, and to reduce peeling, delamination, and/or warpage between the lower capping layer224and the substrate302.

As shown inFIG.3E, the deposition tool102may deposit the function layer214over the top side of the substrate302and on the capping layer216. As shown inFIG.3F, the deposition tool102may deposit the capping layer212over the top side of the substrate302and on the function layer214. Moreover, the deposition tool102may deposit a second portion of the lower capping layer224directly on the first portion of the lower capping layer224over the bottom side or the back side of the substrate302(e.g., without an intervening buffer layer between the first portion and the second portion). The capping layer212and the second portion of the lower capping layer224may be formed as part of the same deposition procedure. The capping layer212and the second portion of the lower capping layer224may be formed of a low-stress material having a tensile strength of less than approximately 600 megapascals e.g., a silicon oxide (SiOx), a silicon nitride (SixNy), a boron nitride (BN), or another material having a tensile strength of less than approximately 600 megapascals) to promote adhesion between to the lower capping layer224and the substrate302, and to reduce peeling, delamination, and/or warpage between the lower capping layer224and the substrate302.

In some implementations, the first portion and the second portion of the lower capping layer224may combine into a single continuous capping layer, and the lower capping layer224may be referred to as a single capping layer. In some implementations, due to the first portion and the second portion being formed as part of separate deposition procedures, the lower capping layer224may be referred to as a plurality of capping layers, where a thin layer of residual native oxide may be disposed between the plurality of capping layers. In these examples, the first portion of the lower capping layer224may be referred to as a first capping layer, and the second portion of the lower capping layer224may be referred to as a second capping layer.

FIG.3Gillustrates another bottom-up view and another cross-sectional view along the line AA of the substrate302. As shown inFIG.3G, a semiconductor processing tool may form a hard mask layer226directly on the lower capping layer224(or directly on the second portion or the second capping layer of the lower capping layer224) over the back side or the bottom side of the substrate302. As an example, the deposition tool102may deposit the hard mask layer226using a spin-coating process, a PVD process, a CVD process, an ALD process, or another type of deposition process.

FIG.3Hillustrates another bottom-up view and another cross-sectional view along the line AA of the substrate302. As shown inFIG.3H, one or more semiconductor processing tools may form a pattern in the hard mask layer226. For example, the deposition tool102may deposit a photoresist on the hard mask layer226. The photoresist may be patterned by exposing the photoresist to a radiation source (e.g., using the exposure tool104) and removing either the exposed portions or the non-exposed portions of the photoresist (e.g., using developer tool108). The pattern in the hard mask layer226may be formed by etching a plurality of portions of the hard mask layer226based on the pattern in the photoresist. The photoresist removal tool110may remove the remaining portions of the photoresist layer (e.g., using a chemical stripper and/or another technique). The pattern in the hard mask layer226may be used to etch the capping layer212, the function layer214, the capping layer216, the buffer layer218, the lower capping layer224, and the substrate302to form or define a pellicle210and a pellicle frame220of the photomask assembly200.

FIG.3Iillustrates a bottom-up view and another cross-sectional view along the line AA of the substrate302. As shown inFIG.3I, a semiconductor processing tool may etch a plurality of openings304into the lower capping layer224on the bottom side or the back side of the substrate302to define an inner perimeter and an outer perimeter of the photomask assembly200. For example, the etch tool106may etch an opening304ainto the lower capping layer224based on the pattern in the hard mask layer226to define an outer perimeter of the photomask assembly200, and may etch an opening304binto the lower capping layer224based on the pattern in the hard mask layer226to define an inner perimeter of the photomask assembly200. The etch tool106may perform a wet etching technique and/or a dry (e.g., plasma-based) etching technique to etch the openings304into the lower capping layer224.

FIG.3Jillustrates another bottom-up view and another cross-sectional view along the line AA of the substrate302. As shown inFIG.3J, one or more semiconductor processing tools may etch through the substrate302from the bottom of the substrate302to define the pellicle frame220. For example, the etch tool106may etch through the substrate302from the opening304ato define an outer side222b, may etch through the substrate302from the opening304bto define an inner side222a, and/or the like. Moreover, the etch tool106may etch through the buffer layer218on the top side of the substrate302and the layers of the pellicle210on the top side of the substrate302from the opening304ato define the perimeter of the pellicle210. The etch tool106may perform a wet etching technique and/or a dry (e.g., plasma-based) etching technique to define the pellicle frame220and the pellicle210.

As further shown inFIG.3J, one or more semiconductor processing tools may form a cooling layer202on the capping layer212above the top side (e.g., top side222c) of the pellicle frame220. For example, the deposition tool102may form the cooling layer202by a deposition process, such as a spin-coating process, a PVD process, a CVD process, an ALD process, or another type of deposition process.

FIG.3Killustrates another bottom-up view and another cross-sectional view along the line AA of the substrate302. As shown inFIG.3K, one or more semiconductor processing tools may remove a portion of the buffer layer218from a bottom side of the capping layer216. For example, the etch tool106may perform a plasma etch (e.g., an isotropic plasma etch) to remove the portion of the buffer layer218between the inner side (e.g., inner side222a) of the pellicle frame220. Moreover, the etch tool106may etch a portion of the buffer layer218between the top side (e.g., top side222c) of the pellicle frame220and the bottom side of the buffer layer218.

As shown inFIG.3L, a photomask frame230may be attached to the photomask assembly200. Attaching the photomask frame230to the photomask assembly200may include attaching a bracket232to a bottom of the pellicle frame220(e.g., to the hard mask layer226on the bottom side222dof the pellicle frame220) using a buffer layer228, attaching the bracket232to a sidewall234with a filter236disposed between the bracket232and the sidewall234, and attaching the sidewall to a gasket238.

As shown inFIG.3M, a photomask240may be attached to the photomask frame230. For example, the photomask240may be attached to the photomask frame230using a buffer layer242.

As indicated above,FIGS.3A-3Mare provided as one or more examples. Other examples may differ from what is described with regard toFIGS.3A-3M.

FIG.4is a diagram of a cross-sectional view of another example of the photomask assembly200described herein. In the example inFIG.4, the photomask assembly200may include a similar arrangement of components as shown inFIG.2. For example, the photomask assembly200may include the cooling layer202on the pellicle210that includes the capping layer212, the function layer214, and the capping layer216. The pellicle210may be on the buffer layer218. The buffer layer218may be on the pellicle frame220. The pellicle frame may have a plurality of sides, such as an inner side222a, an outer side222b, a top side222c, and a bottom side222d. The lower capping layer224may be located directly on the bottom side222dof the pellicle frame220, and the hard mask layer226may be located directly on the lower capping layer224. The photomask frame230may be attached to the pellicle frame220at the hard mask layer226with a buffer layer228in between the photomask frame and the hard mask layer. The bracket232may attach to the hard mask layer226via the buffer layer228, the bracket232may attach to the sidewall234with the filter236disposed between the bracket232and the sidewall234, and the sidewall may attach to the gasket238. The photomask240may attach to the photomask frame230via a buffer layer242.

In the example inFIG.4, the photomask assembly200may additionally include a plurality of stress relieve trenches402. The one or more stress relief trenches402may be formed in the top side222cof the pellicle frame220. In particular, the one or more stress relief trenches402may be formed in an inner portion of the top side222c(e.g., a portion of the top side222ctoward or located near the inner side222a) adjacent to the outer portion in which the pellicle210is attached to the pellicle frame220. The one or more stress relief trenches402may provide stress relief for the pellicle210during operation of the exposure tool (e.g., during a lithography patterning process). In particular, the one or more stress relief trenches402permit the inner portion of the pellicle frame220to bend or deform along with the pellicle210when the pellicle210contacts the pellicle frame220(e.g., due to deformation of the pellicle210). The deformation of the pellicle frame220resulting from the one or more stress relief trenches402reduces the amount of force or pressure applied to or exerted on the pellicle210by the pellicle frame220during deformation of the pellicle210, for example, when the photomask assembly200is used in an exposure tool (in particular, when the exposure tool is pressurized to a vacuum).

As shown inFIG.4, the width x across the one or more stress relief trenches402may span a portion of the width y of top side222cof the pellicle frame220. For example, the width y of the top side222cof the pellicle frame220may be in a range from approximately 1 millimeters (mm) to approximately 5 mm, whereas the width x across the one or more stress relief trenches402may be in a range from approximately 5 microns (μm) to approximately 10 μm. Moreover, as shown in the close-up view inFIG.4, each stress relief trench402may have a depth a and width b. In some implementations, the depth a of a stress relief trench402is greater than the width b of the stress relief trench402. In some implementations, the depth a of a stress relief trench402is approximately equal to the width b of the stress relief trench402. In some implementations, the depth a of a stress relief trench402is less than the width b of the stress relief trench402. An example range for a depth a of a stress relief trench402may be within a range from approximately 1 μm to approximately 5 μm. In some implementations, all of the stress relief trenches402may have approximately the same depth a and/or the same width b. In some implementations, two or more stress relief trenches402may have different depths a and/or different widths b. Moreover, the spacing c between adjacent stress relief trenches402may be the same for all stress relief trenches or may be different for at least a subset of the stress relief trenches402.

The photomask assembly200, as illustrated inFIG.4, may be formed based on a set of procedures and/or techniques illustrated and described above in connection withFIGS.3A-3M. However, an additional procedure may be performed by one or more semiconductor processing tools to form the one or more stress relief trenches402in the substrate302. For example, the deposition tool102may form a photoresist layer on the substrate302, the exposure tool104may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool108may develop and remove portions of the photoresist layer to expose the pattern, the etch tool106may etch the one or more portions of substrate302to form the one or more stress relief trenches402in the top side of the substrate302, and the photoresist removal tool110may remove the remaining portions of the photoresist layer (e.g., using a chemical stripper and/or another technique) after the etch tool106etches the substrate302. The buffer layer218may be formed on the top side of the substrate302after formation of the one or more stress relief trenches402, which may cause material of the buffer layer218to fill at least a portion of the one or more stress relief trenches402. Accordingly, the material of the buffer layer218may also be removed from the one or more stress relief trenches402during etching the portion of the buffer layer218between the portion of the top side222cin the pellicle frame220.

The number and arrangement of components, structures, and/or layers shown inFIG.4are provided as one or more examples. In practice, there may be additional components, structures, and/or layers; fewer components, structures, and/or layers; different components, structures, and/or layers; and/or differently arranged components, structures, and/or layers than those shown inFIG.4.

FIG.5is a diagram illustrating an example exposure tool500. As shown inFIG.5, the exposure tool500may include an exposure source (or radiation source)502that emits radiation energy504, a plurality of optical components (e.g., optical component506, optical component508, and/or the like), a photomask assembly510, a photomask stage512configured and designed to secure the photomask assembly510, and a wafer stage514that is configured to secure a wafer516. The exposure tool500may be designed to perform a lithography exposure process in a suitable mode, such as a step-and-scan mode, a scanning mode, a stepping mode, and/or the like. The photomask assembly510may include the photomask assembly200ofFIG.2orFIG.4, or another photomask assembly.

The exposure source502may include any suitable light source, such a UV light source, a deep UV (DUV) source, an extreme UV (EUV) source, an X-ray source, an e-beam source, and/or the like. In some implementations, the exposure source502may include a mercury lamp having a wavelength of approximately 436 nm or approximately 365 nm, a Krypton Fluoride (KrF) excimer laser with a wavelength of approximately 248 nm, an Argon Fluoride (ArF) excimer laser with a wavelength of approximately 193 nm, a Fluoride (F2) excimer laser with a wavelength of approximately 157 nm, or another light source having a desired wavelength (e.g., below approximately 100 nm). In some implementations, the light source is an EUV source having a wavelength of approximately 13.5 nm or less.

The optical components506and508may receive the radiation energy504from the exposure source502, may modulate the radiation energy504through the pattern of the photomask assembly510, and may direct the radiation energy504to a resist layer coated on the wafer516. In some implementations, each of the optical components506and508includes one or more lenses or lens systems that are designed to have a refractive mechanism. In some implementations, such as where the exposure tool500is an EUV-based exposure tool, each of the optical components506and508includes one or more reflective elements or mirrors having a reflective mechanism.

The optical component506may include an illumination unit such as a condenser lens, a condenser mirror, and/or the like. The optical component506may include a single lens or a lens module having multiple lenses and/or other lens components. For example, the optical component506may include a micro-lens array, a shadow mask, and/or another structure designed to aid in directing radiation energy504from the exposure source502onto the photomask assembly510.

The optical component508may include a projection unit such as a projection lens, a projection mirror, and/or the like. The optical component508may have a single lens element or a plurality of lens elements configured to provide proper illumination to the resist layer on the wafer516. The exposure tool500may further include additional components such as an entrance pupil and an exit pupil to form an image of the photomask assembly510on the wafer516, and/or the like.

The photomask stage512is configured and designed to secure the photomask assembly510by a clamping mechanism, such as vacuum chuck or e-chuck. The photomask stage512may be further designed to be operable to move for various actions, such as scanning, stepping, and/or the like. During a lithography exposing process (or exposure process), the photomask assembly510may be secured on the photomask stage512and positioned such that an integrated circuit pattern (or a layer of a pattern) defined thereon may be transferred to or imaged on the resist layer coated on the wafer516.

The wafer stage514is configured and designed to secure the wafer516. The wafer stage514is further designed to provide various motions, such as transitional motion and/or rotational motion. In some implementations, the wafer414includes a semiconductor substrate having an elementary semiconductor material such as crystal silicon, polycrystalline silicon, amorphous silicon, germanium, or diamond, a compound semiconductor material such as silicon carbide or gallium arsenic, an alloy semiconductor material such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), or gallium indium phosphorous (GaInP), or a combination thereof. The wafer414may be coated with the resist layer that is resistive to etch and/or ion implantation and is sensitive to the radiation energy504.

The wafer516may include a plurality of fields having integrated circuits defined therein for one or more dies. During a lithography exposing process, the wafer516may be exposed one field at a time. For example, the exposure tool500scans the integrated circuit pattern defined in the photomask assembly510and transfers the integrated circuit pattern to one field, then steps to a next field and repeats the scanning until all of the fields of the wafer516are exhausted. A field includes one or more circuit dies and a frame region at a boundary area. After the lithography exposure process is applied to the resist layer coated on the wafer516, the resist layer may be further developed by a developing chemical to form a patterned resist layer that has various openings for subsequent semiconductor processing, such as etching or ion implantation.

In some implementations, the exposure tool500is designed for immersion lithography. An immersion liquid, such as water, is filled in the space between the optical component508and the wafer stage514such that the optical refractive index is increased and the optical resolution of the lithography exposure process is enhanced. In some implementations, the exposure tool500includes various components designed and configured to provide, hold, and drain the immersion liquid.

As indicated above,FIG.5is provided as an example. Other examples may differ from what is described with regard toFIG.5.

FIG.6is a diagram of example components of a device600. In some implementations, the deposition tool102, the exposure tool104, the etch tool106, the developer tool108, the photoresist removal tool110, the transport device112, and/or the exposure tool500may include one or more devices600and/or one or more components of device600. As shown inFIG.6, device600may include a bus610, a processor620, a memory630, a storage component640, an input component650, an output component660, and a communication component670.

Bus610includes a component that enables wired and/or wireless communication among the components of device600. Processor620includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor620is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor620includes one or more processors capable of being programmed to perform a function. Memory630includes a random access memory, a read only memory, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory).

Storage component640stores information and/or software related to the operation of device600. For example, storage component640may include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, and/or another type of non-transitory computer-readable medium. Input component650enables device600to receive input, such as user input and/or sensed inputs. For example, input component650may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, and/or an actuator. Output component660enables device600to provide output, such as via a display, a speaker, and/or one or more light-emitting diodes. Communication component670enables device600to communicate with other devices, such as via a wired connection and/or a wireless connection. For example, communication component670may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

Device600may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory630and/or storage component640) may store a set of instructions (e.g., one or more instructions, code, software code, and/or program code) for execution by processor620. Processor620may execute the set of instructions to perform one or more processes described herein. In some implementations, execution of the set of instructions, by one or more processors620, causes the one or more processors620and/or the device600to perform one or more processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown inFIG.6are provided as an example. Device600may include additional components, fewer components, different components, or differently arranged components than those shown inFIG.6. Additionally, or alternatively, a set of components (e.g., one or more components) of device600may perform one or more functions described as being performed by another set of components of device600.

FIG.7is a flowchart of an example process700associated with form a photomask assembly. In some implementations, one or more process blocks ofFIG.7may be performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools102-110). Additionally, or alternatively, one or more process blocks ofFIG.7may be performed by one or more components of device600, such as processor620, memory630, storage component640, input component650, output component660, and/or communication component670.

As shown inFIG.7, process700may include forming a buffer layer on a first side of a substrate of a photomask assembly and on a second side of the substrate (block710). For example, a semiconductor processing tool (e.g., the deposition tool102) may form a buffer layer218on a first side (e.g., the top side) of a substrate302of a photomask assembly200and on a second side of the substrate302, as described above.

As further shown inFIG.7, process700may include removing the buffer layer from the second side of the substrate (block720). For example, one or more semiconductor processing tools (e.g., the deposition tool102, the exposure tool104, the etch tool106, the developer tool108, and/or another semiconductor processing tool) may remove the buffer layer218from the second side (e.g., the bottom side or the back side) of the substrate302, as described above.

As further shown inFIG.7, process700may include forming a first capping layer of the photomask assembly, where the first capping layer is formed on the buffer layer over the first side of the substrate, and where the first capping layer is formed directly on the second side of the substrate (block730). For example, a semiconductor processing tool (e.g., the deposition tool102) may form a first capping layer216of the photomask assembly200, as described above. In some implementations, the first capping layer216is formed on the buffer layer218over the first side of the substrate302. In some implementations, the first capping layer216(e.g., the first portion of a lower capping layer224or the first capping layer of the lower capping layer224) is formed directly on the second side of the substrate302.

As further shown inFIG.7, process700may include forming a second capping layer directly on the first capping layer over the second side of the substrate, where the first capping layer and the second capping layer combine to form a lower capping layer directly on the second side of the substrate (block740). For example, a semiconductor processing tool (e.g., the deposition tool102) may form a second capping layer212directly on the first capping layer216over the second side of the substrate302, as described above. In some implementations, the first capping layer216and the second capping layer212combine to form a lower capping layer224directly on the second side of the substrate302.

As further shown inFIG.7, process700may include forming a hard mask layer on the lower capping layer over the second side of the substrate (block750). For example, the semiconductor processing tool may form a hard mask layer226on the lower capping layer224over the second side of the substrate302, as described above.

As further shown inFIG.7, process700may include etching, based on a pattern of the hard mask layer, the lower capping layer and the substrate to form a pellicle frame of the photomask assembly (block760). For example, the semiconductor processing tool may etch, based on a pattern of the hard mask layer226, the lower capping layer224and the substrate302to form a pellicle frame220of the photomask assembly200, as described above.

Process700may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.

In a first implementation, process700includes forming (e.g., using the deposition tool102) a pellicle210of the photomask assembly200over the first side of the substrate302, and forming (e.g., using the deposition tool102) a cooling layer202on the pellicle210. In a second implementation, alone or in combination with the first implementation, forming the pellicle includes forming the first capping layer216on the buffer layer218over the first side of the substrate302, forming a function layer214on the first capping layer216over the first side of the substrate302, forming the second capping layer212on the function layer214over the first side of the substrate302, and etching through the first capping layer216, the function layer214, and the second capping layer212to form the pellicle.

In a third implementation, alone or in combination with one or more of the first and second implementations, process700includes removing (e.g., using the etch tool106) a portion of the buffer layer218between the pellicle210and the pellicle frame220. In a fourth implementation, alone or in combination with one or more of the first through third implementations, forming the first capping layer216includes forming the first capping layer216of a material that has a tensile strength that is less than approximately 600 megapascals to reduce delamination of the first capping layer216from the substrate302.

In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process700includes attaching a photomask frame230to the hard mask layer, and attaching a photomask240to the photomask frame. In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, process700includes forming (e.g., using the deposition tool102, the exposure tool104, the etch tool106, the developer tool108, and/or another semiconductor processing tool) a plurality of stress relief trenches402in the first side of the substrate302, where forming the buffer layer218on the first side of the substrate302includes forming the buffer layer218on the first side of the substrate302after forming the plurality of stress relief trenches402in the first side of the substrate302.

In a seventh implementation, alone or in combination with one or more of the first through sixth implementations, process700includes removing (e.g., using the etch tool106) material of the buffer layer218from the plurality of stress relief trenches402after etching the substrate302to form the pellicle frame220.

AlthoughFIG.7shows example blocks of process700, in some implementations, process700may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.7. Additionally, or alternatively, two or more of the blocks of process700may be performed in parallel.

In this way, a portion of a buffer layer on a backside of a substrate of a photomask assembly may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate, and a hard mask layer may be formed directly on the one or more capping layers. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.

As described in greater detail above, some implementations described herein provide a photomask assembly. The photomask assembly includes a pellicle frame. The photomask assembly includes a capping layer formed directly on a bottom side of the pellicle frame. The photomask assembly includes a hard mask layer formed directly on the capping layer. The photomask assembly includes a photomask attached to the hard mask layer.

As described in greater detail above, some implementations described herein provide a method. The method includes forming a buffer layer on a first side of a substrate of a photomask assembly and on a second side of the substrate. The method includes removing the buffer layer from the second side of the substrate. The method includes forming a first capping layer of the photomask assembly. The first capping layer is formed on the buffer layer over the first side of the substrate, and the first capping layer is formed directly on the second side of the substrate. The method includes forming a second capping layer directly on the first capping layer over the second side of the substrate. The first capping layer and the second capping layer combine to form a lower capping layer directly on the second side of the substrate. The method includes forming a hard mask layer on the lower capping layer over the second side of the substrate. The method includes etching, based on a pattern of the hard mask layer, the substrate to form a pellicle frame of the photomask assembly.

As described in greater detail above, some implementations described herein provide a photomask assembly. The photomask assembly includes a pellicle frame. The photomask assembly includes a buffer layer on a top side of the pellicle frame. The photomask assembly includes a pellicle on the buffer layer. The photomask assembly includes a first capping layer directly on a bottom side of the pellicle frame. The photomask assembly includes a second capping layer directly on the first capping layer. The photomask assembly includes a hard mask layer directly on the second capping layer. The photomask assembly includes a photomask attached to the hard mask layer by a photomask frame.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.