Patent ID: 12224247

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

An Integrated Fan-Out (“InFO”) package including one or more dummy dies and methods of forming the same are provided in accordance with various exemplary embodiments. A ratio of an area of the InFO package in a plan view to an area of the package covered by main dies and dummy die(s) may be less than about 2.5. The inclusion of the dummy dies and/or the lowering of the ratio to be less than or equal to about 2.5 may improve warpage characteristics of the InFO package. In some embodiments, the InFO package may experience less warpage and/or more symmetrical warpage when one or more dummy dies are included in the InFO package, and/or the ratio about 2.5 or less. The intermediate stages of forming the InFO package are illustrated and variations of embodiments are discussed.

Referring toFIG.1, a plan view of a wafer100is depicted. Wafer100comprises a plurality of InFO packages102on a surface of the wafer100. In some embodiments, InFO packages102may cover all or substantially all of the surface of wafer100. Each InFO package102comprises one or more main dies104. Although one main die104is depicted in each InFO package102ofFIG.1, in some embodiments more than one main die104may be present in each InFO package102. InFO packages102may have the same number of main dies104as adjacent InFO packages102, or InFO packages102may have different numbers of main dies104as adjacent InFO packages102. Main dies104may have same dimensions in adjacent InFO packages102, or main dies104may have different dimensions in adjacent InFO packages102. Main dies104may be functional dies comprising circuits and/or active or passive devices. Any suitable main dies104may be included. For example, main dies104may include static random access memory (SRAM) chips or dynamic random access memory (DRAM) chips, processor chips, memory chips, logic chips, analog chips, digital chips, central processing units (CPUs), graphics processing units (GPUs), or a combination thereof, or the like.

A ratio of an area of the InFO package102in a plan view to an area covered by the one or more main dies104in the plan view of the InFO package102may be determined. InFIG.1, the area of the InFO package102covered by the main die104is determined according to the relation: die_area=B×D, where B and D are lengths of sidewalls of a rectangular main die104in a plan view. If main die104has a different shape than a rectangle in a plan view, then any suitable relation for determining the area of the main die104in a plan view of the InFO package102may be used. The area of the InFO package102is determined according to the relation package_area=A×C, where A and C are sidewalls of a rectangular InFO package102in a plan view. If InFO package102has a different shape than a rectangle in a plan view, then any suitable relation for determining the area of the InFO package102in a plan view of the InFO package102may be used.

In some embodiments, when the ratio of the area of the InFO package102in the plan view to the area covered by the one or more main dies104in the plan view of the InFO package102is greater than about 2.5, then wafer100and/or respective InFO packages102may experience unacceptable warpage. For example, main dies104may have an effective CTE of around 3.0 due to the semiconductor material (e.g., silicon) present in such dies104. The InFO packages may further comprise various other materials (e.g., a molding compound42and/or TIVs33(SeeFIGS.12A-C)), which may have a higher effective CTE. The CTE mismatch between the main dies104and the other materials of the InFO package102may result in unacceptable warpage when the wafer100and the InFO packages102are at room temperature (e.g., around 25° Celsius) as well as when the wafer100and the InFO packages102are exposed to high temperatures (e.g., around 260° Celsius or higher) when the ratio is about 2.5 or greater. For example, wafer100may have an unacceptably large “crying” profile, as illustrated inFIG.2Awhere a middle portion of the wafer100is higher than edge portions of the wafer100. In some embodiments, a distance T1between the middle portion of the wafer100and edge portions of the wafer100, as illustrated inFIG.2A, may be about 100 μm to about 1300 μm. The wafer100may also have an unacceptably large smiling profile, as illustrated inFIG.2C. In some embodiments, a distance T2between the middle portion of the wafer100and the edge portions of the wafer100, as illustrated inFIG.2C, may be about 100 μm to about 1300 μm. The warpage experienced by wafer100may be asymmetrical. The unacceptable warpage of wafer100may decrease performance and reliability of the wafer100.

The unacceptable warpage of wafer100is attributable at least in part to unacceptable warpage of respective InFO packages102on the surface of wafer100. For example, the respective InFO packages102may have an unacceptably large “crying” profile, as illustrated inFIG.2Awhere a middle portion of the InFO package102is higher than edge portions of the InFO package102. In some embodiments, a distance T1between the middle portion of the InFO package102and edge portions of the InFO package102, as illustrated inFIG.2A, may be about 60 μm to about 120 μm. The InFO packages102may also have an unacceptably large smiling profile, as illustrated inFIG.2C. In some embodiments, a distance T2between the middle portion of the InFO packages102and the edge portions of the InFO packages102, as illustrated inFIG.2C, may be about 60 μm to about 120 μm. The warpage experienced by respective InFO packages102may be asymmetrical. The unacceptable warpage of respective InFO packages102may decrease performance and reliability of the InFO package102.

Referring toFIG.3, in some embodiments, one or more dummy dies (e.g., dummy dies106) may be inserted in InFO packages102in order to reduce CTE mismatch and improve the warpage profile of the resulting InFO packages102and wafer100. A number of dummy dies106, and a size of dummy dies106, may be determined so that a ratio of the area of each InFO package102to the area of the InFO package102covered by the one or more main dies104and the dummy dies106in the plan view of the InFO package102is about 2.5 or less. While main dies104may be functional dies containing devices, circuits, and the like, dummy dies106may be non-functional dies and in some embodiments may not contain any devices and/or functional electrical circuits.

In some embodiments, the size of one of the dummy dies106may be determined according to the relation dummy_area=F×E, where F and E are dimensions of sidewalls of a rectangular dummy die106in a plan view of the InFO package102. When dummy die106is not rectangular in shape, any suitable relation may be used to determine the area of the dummy die in the plan view of the InFO package102. If an InFO package102comprises more than one dummy die106, the area covered by each dummy die may in an InFO package102be determined, and a total area covered by all dummy dies in the InFO package (total_dummy_area) may be determined by adding the areas covered by each dummy die.

The area of the InFO package covered by the main die104is determined according to the relation die_area=B×D, where B and D are lengths of sidewalls of a rectangular main die104in a plan view. If main die104has a different shape than a rectangle in a plan view, then any suitable relation for determining the area of the main die104in a plan view of the InFO package102may be used. If an InFO package102comprises more than one main die104, the area covered by each main die104in an InFO package102be determined, and a total area covered by all main dies104in the InFO package102(total_die_area) may be determined by adding the areas covered by each main die104.

The area of the InFO package102is determined according to the relation package_area=A×C, where A and C are sidewalls of a rectangular InFO package102in a plan view. If InFO package102has a different shape than a rectangle in a plan view, then any suitable relation for determining the area of the InFO package102in a plan view of the InFO package102may be used.

The ratio of the of the area of the InFO package102to the area of the InFO package102covered by the one or more main dies104and the dummy dies106in the plan view may then be determined according to the relation ratio=package_area/(total_die_area+total_dummy_area). When the ratio is about 2.5 or less, warpage experienced by the respective InFO packages102and the wafer100may be reduced and/or more symmetrical. In some embodiments, when wafer100comprises InFO packages102having a ratio of about 2.5 or less, wafer100may have a substantially level lateral surface as illustrated byFIG.2B. By including dummy dies106and lowering the ratio to 2.5 or less, a difference between a highest and lowest point of the wafer100having a crying profile (dimension T1inFIG.2A) may be reduced. In some embodiments, a distance T1between the middle portion and the edge portions may be about 50 μm to about 1100 μm. By including dummy dies106and lowering the ratio to 2.5 or less, a difference between a highest and lowest point of the wafer100having a smiling profile (dimension T2inFIG.2C) may be reduced. In some embodiments, a distance T2between the middle portion and the edge portions may be about 50 μm to about 1100 μm.

In some embodiments, respective InFO packages102having a ratio of about 2.5 or less may also result in the InFO packages102having substantially level lateral surfaces as illustrated byFIG.2B. By including dummy dies106and lowering the ratio to 2.5 or less, a difference between a highest and lowest point of respective InFO packages102having a crying profile (dimension T1inFIG.2A) may be reduced. In some embodiments, a distance T1between the middle portion and the edge portions may be about 0 μm to about 55 μm. By including dummy dies106and lowering the ratio to 2.5 or less, a difference between a highest and lowest point of respective InFO packages102having a smiling profile (dimension T2inFIG.2C) may be reduced. In some embodiments, a distance T2between the middle portion and the edge portions may be about 0 μm to about 55 μm.

Dummy dies106may comprise any suitable material for adjusting the effective CTE of the InFO package102to a desired level. The dummy dies106may include a material for lowering the effective CTE of an InFO package102, such as silicon, glass or ceramic. In other embodiments, the dummy die106may include a material for raising the effective CTE, such as copper or a polymer. In some embodiments, dummy dies106are composed of or comprise the same materials that are comprised in the main dies104. For example, in some embodiments dummy dies106may be selected so that an effective CTE of the dummy dies106are the same or similar to an effective CTE of the main dies104.

FIGS.4through16A-D illustrate cross-sectional views of intermediate steps in forming a semiconductor package in accordance with some embodiments. Referring first toFIG.4, there is shown a carrier substrate20having a release layer22formed thereon. Generally, the carrier substrate20provides temporary mechanical and structural support during subsequent processing steps. The carrier substrate20may include any suitable material, such as, for example, silicon based materials, such as a silicon wafer, glass or silicon oxide, or other materials, such as aluminum oxide, a ceramic material, combinations of any of these materials, or the like. In some embodiments, the carrier substrate20is planar in order to accommodate further processing.

The release layer22is an optional layer formed over the carrier substrate20that may allow easier removal of the carrier substrate20. As explained in greater detail below, various layers and devices will be placed over the carrier substrate20, after which the carrier substrate20may be removed. The optional release layer22aids in the removal of the carrier substrate20, reducing damage to the structures formed over the carrier substrate20. The release layer22may be formed of a polymer-based material. In some embodiments, the release layer22is an epoxy-based thermal release material, which loses its adhesive property when heated, such as a Light-to-Heat-Conversion (LTHC) release coating. In other embodiments, the release layer22may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV light. The release layer22may be dispensed as a liquid and cured. In other embodiments, the release layer22may be a laminate film laminated onto the carrier substrate20. Other release layers may be utilized.

Referring toFIG.4, buffer layer24is formed over release layer22. Buffer layer24is a dielectric layer, which may be a polymer (such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like), a nitride (such as silicon nitride or the like), an oxide (such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or a combination thereof, or the like), or the like, and may be formed, for example, by spin coating, lamination, Chemical Vapor Deposition (CVD), or the like. In some embodiments, buffer layer24is a planar layer having a uniform thickness, wherein the thickness may be between about 2 μm and about 6 μm. The top and the bottom surfaces of buffer layer24are also planar.

Referring now toFIGS.5to9, there is shown an optional formation of through vias (“TVs”)33(seeFIG.9) in accordance with some embodiments. The through vias33provide an electrical connection from one side of the InFO package102to another side of the InFO package102. For example, as will be explained in greater detail below, a main die104and a dummy die106will be mounted to the buffer layer24and a molding compound will be formed around the through vias and the die. Subsequently, another device, such as another die, package, substrate, or the like, may be attached to the die and the molding compound. The through vias33provide an electrical connection between the another device and the backside of the package without having to pass electrical signals through the main die104mounted to the buffer layer24.

The through vias33may be formed, for example, by forming a conductive seed layer26over the buffer layer24, as shown inFIG.5. In some embodiments, seed layer26is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. Seed layer26may26may be made of copper, titanium, nickel, gold, or a combination thereof, or the like. In some embodiments, seed layer26comprises a titanium layer and a copper layer over the titanium layer. Seed layer26may be formed using, for example, physical vapor deposition (PVD), CVD, atomic layer deposition (ALD), a combination thereof, or the like. In some embodiments, seed layer26comprises a titanium layer and a copper layer over the titanium layer. In alternative embodiments, seed layer26is a copper layer.

Turning toFIG.6, a mask layer, such as patterned photoresist layer28, may be deposited and patterned, wherein openings30in the mask layer expose the seed layer26. Referring toFIG.7, openings30may be filled with a conductive material using, for example, an electroless plating process or an electrochemical plating process, thereby creating metal features32. The plating process may uni-directionally fill openings (e.g., from seed layer26upwards) in the patterned photoresist layer28. Uni-directional filling may allow for more uniform filling of such openings. Alternatively, another seed layer may be formed on sidewalls of openings30in the patterned photoresist layer28, and such openings may be filled multi-directionally. Metal features32may comprise copper, aluminum, tungsten, nickel, solder, or alloys thereof. The top-view shapes of metal features32may be rectangles, squares, circles, or the like. The heights of metal features32are determined by the thickness of the subsequently placed main dies104and/or dummy dies106(shown inFIGS.10A-C), with the heights of metal features32greater than the thickness of main dies104and/or dummy dies106in some embodiments.

Next, the mask layer may be removed, for example in an ashing and/or wet strip process, as shown inFIG.8. Referring toFIG.9, an etch step is performed to remove the exposed portions of seed layer26, wherein the etching may be an anisotropic etching. The portions of seed layer26that are overlapped by metal features32, on the other hand, remain not etched. Metal features32and the remaining underlying portions of seed layer26form through vias33. Although seed layer26is shown as a layer separate from metal features32, when seed layer26is formed of a material similar to or the same as the respective overlying metal features32, seed layer26may be merged with metal features32with no distinguishable interface between. In some embodiments, there exist distinguishable interfaces between seed layer26and the overlying metal features32. The through vias33can also be realized with metal wire studs placed by a wire bonding process, such as a copper wire bonding process. The use of a wire bonding process may eliminate the need for depositing seed layer26, depositing and patterning mask layer28, and plating to form the through vias33.

FIGS.10A-Cillustrated attaching a main die104and a dummy die106to the backside of buffer layer24in accordance with some embodiments. Each of main die104and dummy die106are adhered to buffer layer24by an adhesive layer36, such as a die-attach film (DAF). A thickness of the adhesive layer36may be in a range from about 5 μm to about 50 μm, such as about 10 um. One main die104and one dummy die106may be used as illustrated inFIGS.10A-C, or in some embodiments more than one main die104and/or more than one dummy die106may be used. For each of the embodiments depicted inFIGS.10A-10C, a ratio of an area of the InFO package102in a plan view to an area of the InFO package102covered by the main die(s)104and the dummy die(s)106is about 2.5 or less. As such, the InFO packages102depicted in each ofFIGS.10A-Cmay experience reduced warpage and/or more symmetric warpage, which may increase reliability and increase performance of the InFO package102.

The main die(s)104and the dummy die(s)106may be attached to a suitable location for a particular design or application. For example,FIGS.10A-Cillustrate embodiments in which the main die104and the dummy die106are mounted in a center region wherein the through vias33are positioned around a perimeter. In other embodiments, the main die104and/or the dummy die106may be offset from a center.

Before being attached to the buffer layer24, the main die104may be processed according to applicable manufacturing processes to form integrated circuits in the main die104. Main dies104may include a semiconductor substrate35, where a backside of the semiconductor substrate is attached to adhesive layer36. In some exemplary embodiments, main die104includes metal pillars40(such as copper posts) that are electrically coupled to devices such as transistors (not shown) in main dies104. In some embodiments, dielectric layer38is formed at the top surface of the main dies104, with metal pillars40having at least lower portions in dielectric layer38. The top surfaces of metal pillars40may also be level with the top surfaces of dielectric layer38in some embodiments. Alternatively, dielectric layer38is not formed, and metal pillars40protrude above a top layer of the respective main die104.

FIGS.10A-Cdepict various embodiments of dummy dies106that may be included in InFO package102. InFIGS.10A-Cthrough15A-D, Figures ending in “A” depict a first embodiment, figures ending in “B” depict a second embodiment, Figures ending in “C” depict a third embodiment, and Figures ending in “D” depict a fourth embodiment.

Referring toFIG.10A, dummy die106may include a semiconductor substrate35, where a backside of the semiconductor substrate35is attached to adhesive layer36. In some embodiments, semiconductor substrate35may comprise a same material as semiconductor substrate35of main die104. A dielectric layer38is optionally included on a surface of semiconductor substrate35of dummy die106that is opposite to the surface that contacts the adhesive layer. Dielectric layer38of dummy die106may comprise a same material as dielectric layer38of main die104. In the embodiment depicted inFIG.10A, electrical contacts (such as metal pillars40) are not included in the dummy die106. Alternatively, metal pillars40are included in dielectric layer38of dummy die106, as shown inFIG.10B. In some embodiments metal pillars40comprise copper or the like.

Dummy die106has a same thickness as main die104in the embodiments depicted inFIG.10AandFIG.10B, where the thickness is measured in a direction that is parallel to through vias33. Alternatively, as depicted inFIG.10C, dummy die106may have a thickness that is less than the thickness of main die104. In some embodiments, main die104may have a thickness T3of 40 μm to 300 μm, while dummy die106may have a thickness T4of 40 μm to 300 μm. In some embodiments, a ratio of thickness T4of the dummy die106to a thickness T3of the main die104may be about 40% to about 100%.

Referring toFIGS.11A-C, molding material42is molded on main dies104, dummy dies1106and TVs33. Molding material42fills the gaps between main die104and main die106, between main die104and TVs33, and between dummy die106and TVs33, and may be in contact with buffer layer24. Furthermore, molding material42is filled into the gaps between metal pillars40when metal pillars40are protruding metal pillars. The molding material42may be molded on the main die104, dummy die106, and TVs33, for example, using compression molding. In some embodiments, the molding material42is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material42, wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof. The top surface of molding material42is higher than the top ends of metal pillars40on main die104and TVs33.

Next, a grinding step is performed to thin molding material42, until metal pillars40on main die104and TVs33are exposed. The resulting structures are shown inFIGS.12A-C. Due to the grinding, the top ends of metal features32are substantially level (coplanar) with the top ends of metal pillars40on main die104, and are substantially level (coplanar) with the top surface of molding material42. In embodiments in which dummy die106has a same thickness as main die104, the grinding step exposes a top surface of dummy die106. For example, the grinding process may expose a dielectric layer38of dummy die106and/or metal pillars40of dummy die106.

In embodiments in which dummy die106has a thickness that is less than a thickness of main die104, the grinding step does not expose the dummy die106as shown inFIG.12C. After the grinding step, molding material covers the surface of dummy die106that is farthest from the carrier substrate20.

As a result of the grinding, metal residues such as metal particles may be generated, and left on the top surfaces of the molding material42and main die104. Accordingly, after the grinding, a cleaning may be performed, for example, through a wet etching, so that the metal residue is removed.

Next, referring toFIGS.13A-C, one or more redistribution layers (RDLs)43are formed. Generally, RDLs provide a conductive pattern that allows a pin-out contact pattern for a completed package different than the pattern of through vias33and/or metal pillars40, allowing for greater flexibility in the placement of through vias33and main dies104. The RDLs may be utilized to provide an external electrical connection to main die104and/or to through vias33. The RDLs may further be used to electrically couple main dies104to through vias33, which may be electrically coupled to one or more other packages, package substrates, components, the like, or a combination thereof. The RDLs comprise conductive lines44and via connections48, wherein via connections48connect an overlying line (e.g., an overlying conductive lines44) to an underlying conductive feature (e.g., through vias33, metal pillars40, and/or conductive lines44). Conductive lines44may extend along any direction.FIGS.13A-Cillustrates three layers of RDLs, while there may be one, two, or more than three layers of RDLs43, depending on the routing requirement of the respective InFO package102.

The RDLs43may be formed using any suitable process. For example, in some embodiments, dielectric layer50is formed on the molding material42and over main die104and dummy die106. In some embodiments, dielectric layer50is formed of a polymer, which may be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, that may be patterned using lithography. In other embodiments, dielectric layer50is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or the like. Dielectric layer50may be formed by spin coating, lamination, CVD, the like, or a combination thereof. Dielectric layer50is then patterned to form openings to expose metal pillars40of main die104and the through vias33. In embodiments in which conductive lines44are electrically connected to dummy die106(seeFIG.13D), electrical connectors on dummy die106are exposed as well. In embodiments in which dielectric layer50is formed of a photo-sensitive material, the patterning may be performed by exposing dielectric layer50in accordance with a desired pattern and developed to remove the unwanted material. Other methods, such as using a patterned mask and etching, may also be used to pattern dielectric layer50.

A seed layer (not shown) is formed over dielectric layer50and in the openings formed in dielectric layer50. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD, or the like. A mask is then formed and patterned on the seed layer in accordance with a desired redistribution pattern, such as the pattern illustrated inFIGS.13A-D. In some embodiments, the mask is a photoresist formed by spin coating or the like and exposed to light for patterning. The patterning forms openings through the mask to expose the seed layer. A conductive material is formed in the openings of the mask and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed, are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the conductive lines44and via connections48. Dielectric layer52is formed over dielectric layer50to provide a more planar surface for subsequent layers and may be formed using similar materials and processes as used to form dielectric layer50. In some embodiments, dielectric layer52is formed of polymer, a nitride, an oxide, or the like. In some embodiments, dielectric layer52is PBO formed by a spin-on process.

The above process describes the formation of one layer of RDLs43. The above process may be repeated as desired to form additional RDLs43if desired.

As discussed above, in some embodiments the dummy die106is formed without any electrical connectors for electrically connecting the dummy die106to external components. As such, there is no need for any via connectors48or conductive lines44of RDLs43for connection to a dummy die106. Examples of embodiments in which dummy die106has no metal pillars40are shown inFIGS.13A and13C. In other embodiments dummy die106may be formed with metal pillars40on a surface of dummy die106that is farthest from the carrier substrate20. Examples of embodiments in which the dummy die106comprises metal pillars40are shown inFIGS.13B and13D. As shown inFIG.13B, in some embodiments no conductive vias48or conductive lines44of RDLs43are formed to connect to metal pillars40in dummy dies106. As such, metal pillars40may contact a dielectric layer of RDLs43and be electrically isolated from any conductive vias48or conductive lines44of RDLs43. Referring toFIG.13D, in some embodiments conductive vias48and conductive lines may be formed in RDL43and be electrically connected to metal pillars40in dummy die106. In some embodiments metal pillars40of dummy die106may be electrically connected to a ground node of InFO package102using metal pillars40.

FIGS.14A-Dillustrate an under bump metallization (UBM)70formed and patterned over an uppermost metallization pattern of the structures shown inFIGS.13A-Din accordance with some embodiments, thereby forming an electrical connection with an uppermost metallization layer. The UBM70provides an electrical connection upon which an electrical connector, e.g., a solder ball/bump, a conductive pillar, or the like, may be placed. In an embodiment, the under bump metallization70includes a diffusion barrier layer, a seed layer, or a combination thereof. The diffusion barrier layer may include Ti, TiN, Ta, TaN, or combinations thereof. The seed layer may include copper or copper alloys. However, other metals, such as nickel, palladium, silver, gold, aluminum, combinations thereof, and multi-layers thereof, may also be included. In an embodiment, under bump metallization70is formed using sputtering. In other embodiments, electro plating may be used.

Connectors68are formed over the under bump metallization70in accordance with some embodiments. The connectors68may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, combination thereof (e.g., a metal pillar having a solder ball attached thereof), or the like. The connectors68may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the connectors68comprise a eutectic material and may comprise a solder bump or a solder ball, as examples. The solder material may be, for example, lead-based and lead-free solders, such as Pb—Sn compositions for lead-based solder; lead-free solders including InSb; tin, silver, and copper (SAC) compositions; and other eutectic materials that have a common melting point and form conductive solder connections in electrical applications. For lead-free solder, SAC solders of varying compositions may be used, such as SAC105(Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC305, and SAC405, as examples. Lead-free connectors such as solder balls may be formed from SnCu compounds as well, without the use of silver (Ag). Alternatively, lead-free solder connectors may include tin and silver, Sn—Ag, without the use of copper. The connectors68may form a grid, such as a ball grid array (BGA). In some embodiments, a reflow process may be performed, giving the connectors68a shape of a partial sphere in some embodiments. Alternatively, the connectors68may comprise other shapes. The connectors68may also comprise non-spherical conductive connectors, for example.

In some embodiments, the connectors68comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like, with or without a solder material thereon. The metal pillars may be solder free and have substantially vertical sidewalls or tapered sidewalls.

Next, carrier substrate20is de-bonded from the package. Release layer22is also cleaned from the package. The resulting structure is shown inFIGS.15A-D. As a result of the removal of release layer22, buffer layer24is exposed.

In subsequent processing (not shown), if a plurality of InFO packages are formed simultaneously, the InFO packages may singulated into a plurality of InFO packages102.

Referring toFIGS.16A-C, a top package300may be bonded to InFO package102. The top package300includes a substrate302and one or more stacked dies308(308A and308B) coupled to the substrate302. The substrate302may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate302may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate302is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used for substrate302.

The substrate302may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the semiconductor package300. The devices may be formed using any suitable methods.

The substrate302may also include metallization layers (not shown) and through vias306. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate302is substantially free of active and passive devices.

The substrate302may have bond pads303on a first side the substrate302to couple to the stacked dies308, and bond pads304on a second side of the substrate302, the second side being opposite the first side of the substrate302, to couple to the conductive connectors314. In some embodiments, the bond pads303and304are formed by forming recesses (not shown) into dielectric layers (not shown) on the first and second sides of the substrate302. The recesses may be formed to allow the bond pads303and304to be embedded into the dielectric layers. In other embodiments, the recesses are omitted as the bond pads303and304may be formed on the dielectric layer. In some embodiments, the bond pads303and304include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads303and304may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. In an embodiment, the conductive material of the bond pads303and304is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof. In an embodiment, the bond pads303and304are UBMs that are formed using the same or similar processes as described earlier in connection with UBMs70.

In the illustrated embodiment, the stacked dies308are coupled to the substrate302by wire bonds310, although other connections may be used, such as conductive bumps. In an embodiment, the stacked dies308are stacked memory dies. For example, the stacked memory dies308may include low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules.

In some embodiments, the stacked dies308and the wire bonds310may be encapsulated by a molding material312. The molding material312may be molded on the stacked dies308and the wire bonds310, for example, using compression molding. In some embodiments, the molding material312is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material312, wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof.

In some embodiments, the stacked dies308and the wire bonds310are buried in the molding material312, and after the curing of the molding material312, a planarization step, such as a grinding, is performed to remove excess portions of the molding material312and provide a substantially planar surface for the second packages300.

After the top packages300are formed, the top packages300are bonded to the InFO packages102by way of conductive connectors314and the bond pads304. In some embodiments, the stacked memory dies308may be coupled to the main die104through the wire bonds310, the bond pads303and304, through vias306, the conductive connectors314, and the through vias33.

The conductive connectors314may be similar to the connectors68described above and the description is not repeated herein, although the conductive connectors314and68need not be the same. In some embodiments, before bonding the conductive connectors314, the conductive connectors314are coated with a flux (not shown), such as a no-clean flux. The conductive connectors314may be dipped in the flux or the flux may be jetted onto the conductive connectors314.

In some embodiments, the conductive connectors314may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the top package300is attached to the InFO package102. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors314. In some embodiments, an underfill (not shown) may be formed between the top package300and the InFO package102and surrounding the conductive connectors314. The underfill may be formed by a capillary flow process after the top package300is attached or may be formed by a suitable deposition method before the top package300is attached.

The bonding between the top package300and the InFO package102may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding. In an embodiment, the top package300is bonded to the InFO package102by a reflow process. During this reflow process, the conductive connectors314are in contact with the bond pads304and the through vias33to physically and electrically couple the top package300to the InFO package102.

In accordance with some embodiments, an InFO package includes one or more main dies and one or more dummy dies. A ratio of an area of the InFO package in a plan view to an area of the package covered by main dies and dummy dies is less than about 2.5. The inclusion of the dummy dies and/or the lowering of the ratio to be less than or equal to about 2.5 may improve warpage characteristics of the InFO package. In some embodiments, the InFO package may experience less warpage and/or more symmetrical warpage when the ratio about 2.5 or less.

A structure is provided in accordance with some embodiments. The structure includes one or more main dies and one or more dummy dies, a dummy die of the one or more dummy dies being positioned beside a main die of the one or more main dies. The structure also includes molding material extending along sidewalls of the one or more main dies and the one or more dummy dies. The structure also includes a plurality of redistribution layers including a plurality of vias and a plurality of conductive lines, the one or more main dies extending along a first surface of the plurality of redistribution layers. The structure also includes a plurality of external connectors extending along a second surface of the plurality of redistribution layers, the first surface and the second surface being opposite surfaces of the plurality of redistribution layers.

A structure is provided in accordance with some embodiments. The structure includes one or more main dies. The structure also includes one or more dummy dies, a first dummy die of the one or more dummy dies being positioned beside a main die of the one or more main dies. The structure also includes a plurality of through vias, where a through via of the plurality of through vias is positioned beside a second dummy die of the one or more dummy dies. The structure also includes a molding material extending along sidewalls of the one or more main dies, the one or more dummy dies, and the plurality of through vias. The structure also includes a redistribution layer over the one or more main dies and the one or more dummy dies, where the redistribution layer includes a plurality of conductive lines and a plurality of vias, and where the plurality of conductive lines are electrically connected to the one or more main dies.

Another structure is provided in accordance with some embodiments. The structure includes one or more main dies and one or more dummy dies. The structure also includes a molding material extending along sidewalls of the one or more main dies, the one or more dummy dies, and the plurality of through vias. The structure also includes a redistribution layer over the one or more main dies and the one or more dummy dies, where the redistribution layer includes a plurality of conductive lines and a plurality of vias. An area of the structure in a plan view of the structure is a first area, an area of the structure covered by the one or more main dies and the one or more dummy dies in the plan view of the structure is a second area, and a ratio of the first area to the second area is 2.5 or less.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.