Patent ID: 12255550

DETAILED DESCRIPTION

Referring toFIG.1, a first current source inverter (CSI)100is shown in accordance with an illustrative embodiment. First CSI100may include an inverter switching circuit102, an inductor104, and a capacitive filter106. Capacitive filter106may include a first capacitor108, a second capacitor110, and a third capacitor112. Inverter switching circuit102is connected between inductor104and capacitive filter106. Inverter switching circuit102may include a commutation switch114, a commutation diode116, a first inverter leg120, a second inverter leg122, and a third inverter leg124. First inverter leg120may include a first switch126and a second switch128. Second inverter leg122may include a third switch130and a fourth switch132. Third inverter leg124may include a fifth switch134and a sixth switch136. Commutation switch114and commutation diode116form a reverse blocking (RB) commutation switch118.

A source line138, a first bus line142, a second bus line140, a commutation switch line144, a first bridge line146, a second bridge line148, a first phase line150, a second phase line152, a third phase line154, and a filter line156can be used to describe connectivity between the electrical circuit elements of first CSI100where the term line may indicate any type of conductor, wire, or other conduit by which electrical energy is transmitted between electrical circuit elements.

Inductor104may be one or more inductors connected in series of various types with various inductance values. Though not shown, inductor104further may include one or more inductors connected in series on second bus line140between a DC current source614(shown referring toFIG.6A) and inverter switching circuit102. As understood by a person of skill in the art, an inductor is a passive two-terminal electrical component that stores energy in a magnetic field when electric current flows through it. An inductance value for inductor104may be selected to carry a load current based on an application area of first CSI100as understood by a person of skill in the art. Inductor104is connected on source line138between DC current source614and inverter switching circuit102. First bus line142and second bus line140provide connections to inverter switching circuit102to/from DC current source614through inductor104.

A capacitor of first capacitor108, second capacitor110, and third capacitor112is associated with each inverter leg of first inverter leg120, second inverter leg122, and third inverter leg124, respectively. First capacitor108is connected between first phase line150and filter line156. Second capacitor110is connected between second phase line152and filter line156. Third capacitor112is connected between third phase line154and filter line156. Each capacitor of capacitive filter106may be a capacitor of various types and with various ratings. As understood by a person of skill in the art, a capacitor is a passive two-terminal electrical component that stores electrical energy in an electric field and has an associated rated capacitance value. A rating of each capacitor of capacitive filter106may be selected to carry inductive current from an alternating current (AC) load616(shown referring toFIG.6A) without requiring the switches of first inverter leg120, second inverter leg122, and third inverter leg124to provide a current flow-path. In alternative embodiments, other types of filters may be used based on AC load616.

Commutation switch114may include a semiconductor switch formed of one or more of various types of semiconductors such as a MOSFET, a high electron mobility transistor (HEMT), etc. For example, referring toFIG.2, commutation switch114may be implemented using an n-channel, enhancement mode MOSFET200with a gate terminal202, a source terminal204, and a drain terminal206. As understood by a person of skill in the art, the terminals of different types of semiconductor devices may be labeled differently based on the type of switch. For example, for a MOSFET or an HEMT, a first terminal, a second terminal, and a third terminal may be referred to as a drain, a gate, and a source, respectively. A voltage applied to the second terminal determines a switching state of the semiconductor device, as in an on-state or as in an off-state. In the off-state, there is little or no conduction between drain terminal206and source terminal204. In the on-state, there is current flow from drain terminal206to source terminal204.

Gate terminal202and source terminal204may be connected to a pulse width modulated (PWM) signal generator208of a controller602(shown referring toFIG.6A). Drain terminal206may be connected to commutation switch line144. Source terminal204may be connected to the anode of commutation diode116. Gate terminal202and source terminal204may be connected to switch together under control of PWM signal generator208. Commutation switch114may be in an off-state when an off-state control signal is provided by PWM signal generator208of controller602to gate terminal202. Commutation switch114may be in an on-state when an on-state control signal is provided by PWM signal generator208of controller602to gate terminal202and source terminal204. For illustration, commutation switch114may be a silicon-carbide (SiC)-MOSFET switch.

Commutation diode116may be a diode of various types such as a p-n junction type, a Schottky barrier type, etc. with various ratings. As understood by a person of skill in the art, a diode is a two-terminal electrical component that conducts current primarily in one direction from an anode to a cathode. Commutation diode116is connected in series between commutation switch114and second bus line140with the anode of commutation diode116connected to receive current from commutation switch114and to provide current flow to second bus line140.

First switch126, second switch128, third switch130, fourth switch132, fifth switch134, and sixth switch136may be dual-gate bidirectional (DGBD) switches with controlled current flow in both polarities in addition to having reverse-voltage-blocking capability. Each DGBD includes a first semiconductor switch and a second semiconductor switch that are separately controllable by controller102.

For example, referring toFIG.3A, a first DGBD switch300is shown in accordance with an illustrative embodiment. First DGBD switch300can be used as first switch126, second switch128, third switch130, fourth switch132, fifth switch134, and sixth switch136. First DGBD switch300may include a first IGBT301, a second IGBT302, a first diode304, and a second diode306, where first IGBT301with first diode304is the first semiconductor switch, and second IGBT302with second diode306is the second semiconductor switch. First IGBT301may include a first gate terminal308, a first emitter terminal310, and a first collector terminal312. Second IGBT302may include a second gate terminal314, a second emitter terminal316, and a second collector terminal318. First diode304is connected anti-parallel across first IGBT301between a first diode terminal320and second collector terminal318. First diode terminal320is tied to first emitter terminal310and to the anode of first diode304. The cathode of first diode304is connected to second collector terminal318. Second diode306is connected anti-parallel across second IGBT302between a second diode terminal322and first collector terminal312. Second diode terminal322is connected to the anode of second diode306. The cathode of second diode306is connected to first collector terminal312. Second diode terminal322is tied to second emitter terminal316. First collector terminal312is tied to second collector terminal318. First gate terminal308and first emitter terminal310may be connected to switch together under control of a first PWM signal generator324of controller602. Second gate terminal314and second emitter terminal316may be connected to switch together under control of a second PWM signal generator326of controller602.

A first input/output (I/O) terminal328is connected between first diode terminal320and first emitter terminal310. A second I/O terminal329is connected between second emitter terminal316and second diode terminal322. First I/O terminal328provides a first connection to first DGBD switch300, and second I/O terminal329provides a second connection to first DGBD switch300. Current may flow through first DGBD switch300from first I/O terminal328to second I/O terminal329or vice versa to provide the current flow in both polarities.

First DGBD switch300can be operated in one of four states: 1) a first DGBD switch on-state when an on-state signal is provided by PWM signal generator324of controller602to first gate terminal308and an on-state signal is provided by PWM signal generator326of controller602to second gate terminal314, 2) a second DGBD switch on-state when an on-state signal is provided by PWM signal generator324of controller602to first gate terminal308and an off-state signal is provided by PWM signal generator326of controller602to second gate terminal314, 3) a third DGBD switch on-state when an on-state signal is provided by PWM signal generator326of controller602to second gate terminal314and an off-state signal is provided by PWM signal generator324of controller602to first gate terminal308, and 4) a DGBD switch off-state when an off-state signal is provided by PWM signal generator324of controller602to first gate terminal308and an off-state signal is provided by PWM signal generator326of controller602to second gate terminal314.

When first DGBD switch300is in the DGBD switch off-state, no current flows through first DGBD switch300. When first DGBD switch300is in the first DGBD switch on-state, current can flow from first I/O terminal328to second I/O terminal329(positive polarity) or from second I/O terminal329to first I/O terminal328(negative polarity) with no reverse voltage blocking. When first DGBD switch300is in the second DGBD switch on-state, current flows from first I/O terminal328to second I/O terminal329with reverse voltage blocking in a first direction. When first DGBD switch300is in the third DGBD switch on-state, current flows from second I/O terminal329to first I/O terminal328with reverse voltage blocking in a second direction with a reverse polarity to the first direction.

As another example, referring toFIG.3B, a second DGBD switch330is shown in accordance with an illustrative embodiment. Second DGBD switch330can be used as first switch126, second switch128, third switch130, fourth switch132, fifth switch134, and sixth switch136. Second DGBD switch330may include first IGBT301, second IGBT302, first diode304, and second diode306. First diode304is connected anti-parallel across first IGBT301between a first diode terminal320and a third diode terminal332. First diode terminal320is connected to the anode of first diode304. The cathode of first diode304is connected to third diode terminal332. First diode terminal320is tied to first emitter terminal310. Third diode terminal332is tied to first collector terminal312. Second diode306is connected anti-parallel across second IGBT302between second diode terminal322and a fourth diode terminal334. Second diode terminal322is connected to the anode of second diode306. The cathode of second diode306is connected to fourth diode terminal334. Second diode terminal322is tied to second emitter terminal316. Fourth diode terminal334is tied to second collector terminal318. First gate terminal308and first emitter terminal310may be connected to switch together under control of first PWM signal generator324of controller602. Second gate terminal314and second emitter terminal316may be connected to switch together under control of second PWM signal generator326of controller602. First PWM signal generator324also may be connected to second emitter terminal316, first diode terminal320, and second diode terminal322at a common terminal336. Second PWM signal generator326also may be connected to first emitter terminal310, first diode terminal320, and second diode terminal322at common terminal336.

First I/O terminal328is connected between fourth diode terminal334and second collector terminal318. Second I/O terminal329is connected between third diode terminal332and first collector terminal312. First I/O terminal328provides the first connection to second DGBD switch330, and second I/O terminal329provides the second connection to second DGBD switch330. Current may flow through second DGBD switch330from first I/O terminal328to second I/O terminal329or vice versa to provide the current flow in both polarities. Similar to first DGBD switch300, second DGBD switch330can be operated in one of the four states.

As yet another example, referring toFIG.3C, a third DGBD switch340is shown in accordance with an illustrative embodiment. Third DGBD switch340can be used as first switch126, second switch128, third switch130, fourth switch132, fifth switch134, and sixth switch136. Third DGBD switch340may include a first MOSFET342and a second MOSFET344, where first MOSFET342is the first semiconductor switch, and second MOSFET344is the second semiconductor switch. A first gate terminal346, a first source terminal348, and a second source terminal354may be connected to switch together under control of first PWM signal generator358of controller602. A second gate terminal352, first source terminal348, and second source terminal354may be connected to switch together under control of a second PWM signal generator362of controller602. A signal terminal360is connected between first PWM signal generator358and second PWM signal generator362and to first source terminal348and second source terminal354.

A first drain terminal350is also first I/O terminal328, and a second drain terminal356is also second I/O terminal329. First I/O terminal328provides the first connection to third DGBD switch340, and second I/O terminal329provides the second connection to third DGBD switch340.

Current may flow through third DGBD switch340from first I/O terminal328to second I/O terminal329or vice versa to provide the current flow in both polarities. Third DGBD switch340can be operated in one of four states: 1) a first DGBD switch on-state when an on-state signal is provided by PWM signal generator358of controller602to first gate terminal346and an on-state signal is provided by PWM signal generator362of controller602to second gate terminal352, 2) a second DGBD switch on-state when an on-state signal is provided by PWM signal generator358of controller602to first gate terminal346and an off-state signal is provided by PWM signal generator362of controller602to second gate terminal352, 3) a third DGBD switch on-state when an on-state signal is provided by PWM signal generator362of controller602to second gate terminal352and an off-state signal is provided by PWM signal generator358of controller602to first gate terminal346, and 4) a DGBD switch off-state when an off-state signal is provided by PWM signal generator358of controller602to first gate terminal346and an off-state signal is provided by PWM signal generator362of controller602to second gate terminal352.

When third DGBD switch340is in the DGBD switch off-state, no current flows through third DGBD switch340. When third DGBD switch340is in the first DGBD switch on-state, current can flow from first I/O terminal328to second I/O terminal329(positive polarity) or from second I/O terminal329to first I/O terminal328(negative polarity) with no reverse voltage blocking. When third DGBD switch340is in the second DGBD switch on-state, current flows from first I/O terminal328to second I/O terminal329with reverse voltage blocking in a first direction. When third DGBD switch340is in the third DGBD switch on-state, current flows from second I/O terminal329to first I/O terminal328with reverse voltage blocking in a second direction with a reverse polarity to the first direction.

The switches ofFIGS.2and3A-3Care merely examples of a semiconductor switch and DGBD switches that may be used. For further reference, example semiconductor switches and bidirectional switches are described in H. Dai, T. M. Jahns, R. A. Torres, M. Liu, B. Sarlioglu, and S. Chang, “Development of High-Frequency WBG Power Modules with Reverse-Voltage-Blocking Capability for an Integrated Motor Drive using a Current-Source Inverter,” 2018 IEEE Energy Conyers. Congr. Expo, pp. 1808-1815, 2018; J. W. Wu et al., “1200V, 25 A bidirectional Si DMOS IGBT fabricated with fusion wafer bonding,” Proc. Int. Symp. Power Semicond. Devices ICs, pp. 95-98, 2014; M. Baus et al., “Fabrication of Monolithic Bidirectional Switch (MBS) devices with MOS-controlled emitter structures,” Power Semicond. Devices IC's, 2006 IEEE Int. Symp., pp. 1-4, 2006; S. Chowdhury, C. W. Hitchcock, Z. Stum, R. P. Dahal, I. B. Bhat, and T. P. Chow, “Operating Principles, Design Considerations, and Experimental Characteristics of High-Voltage 4H-SiC Bidirectional IGBTs,” IEEE Trans. Electron Devices, vol. 64, no. 3, pp. 888-896, 2017; H. Umeda, Y. Yamada, K. Asanuma, F. Kusama, and Y. Kinoshita, “High Power 3-phase to 3-phase Matrix Converter Using Dual-gate GaN Bidirectional Switches,” in 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), 2018, pp. 894-897; T. Morita et al., “650 V 3.1 mΩcm2 GaN-based monolithic bidirectional switch using normally-off gate injection transistor,” in 2007 IEEE International Electron Devices Meeting, 2007, pp. 865-868; P. Wheeler and D. Grant, “Optimised input filter design and low-loss switching techniques for a practical matrix converter,” IEE Proc.—Electr. Power Appl., vol. 144, no. 1, p. 53, 1997; and M. Hornkamp, M. Loddenkotter, M. Munzer, O. Simon, and M. Bruckmann, “ECONOMAC THE FIRST ALL-IN-ONE IGBT MODULE FOR MATRIX CONVERTERS,” 2001, p. 640.

A gate terminal and/or a source terminal of first switch126(e.g., first gate terminal346and second gate terminal352of third DGBD switch340) may be connected to a PWM signal generator (e.g., first PWM signal generator358and second PWM signal generator362of third DGBD switch340) controlled by controller602. The first connection of first switch126(e.g., first I/O terminal328of third DGBD switch340) may be connected to first bridge line146, and the second connection of first switch126(e.g., second I/O terminal329of third DGBD switch340) may be connected to first phase line150. For illustration, first switch126may be implemented using GaN-HEMTs or SiC-MOSFET transistors.

A gate terminal and/or a source terminal of second switch128(e.g., first gate terminal346and second gate terminal352of third DGBD switch340) may be connected to a PWM signal generator (e.g., first PWM signal generator358and second PWM signal generator362of third DGBD switch340) controlled by controller602. The first connection of second switch128(e.g., first I/O terminal328of third DGBD switch340) may be connected to first phase line150, and the second connection of second switch128(e.g., second I/O terminal329of third DGBD switch340) may be connected to second bridge line148. For illustration, second switch128may be implemented using GaN-HEMTs or SiC-MOSFET transistors.

A gate terminal and/or a source terminal of third switch130(e.g., first gate terminal346and second gate terminal352of third DGBD switch340) may be connected to a PWM signal generator (e.g., first PWM signal generator358and second PWM signal generator362of third DGBD switch340) controlled by controller602. The first connection of third switch130(e.g., first I/O terminal328of third DGBD switch340) may be connected to first bridge line146, and the second connection of third switch130(e.g., second I/O terminal329of third DGBD switch340) may be connected to second phase line152. For illustration, third switch130may be implemented using GaN-HEMTs or SiC-MOSFET transistors.

A gate terminal and/or a source terminal of fourth switch132(e.g., first gate terminal346and second gate terminal352of third DGBD switch340) may be connected to a PWM signal generator (e.g., first PWM signal generator358and second PWM signal generator362of third DGBD switch340) controlled by controller602. The first connection of fourth switch132(e.g., first I/O terminal328of third DGBD switch340) may be connected to second phase line152, and the second connection of fourth switch132(e.g., second I/O terminal329of third DGBD switch340) may be connected to second bridge line148. For illustration, fourth switch132may be implemented using GaN-HEMTs or SiC-MOSFET transistors.

A gate terminal and/or a source terminal of fifth switch134(e.g., first gate terminal346and second gate terminal352of third DGBD switch340) may be connected to a PWM signal generator (e.g., first PWM signal generator358and second PWM signal generator362of third DGBD switch340) controlled by controller602. The first connection of fifth switch134(e.g., first I/O terminal328of third DGBD switch340) may be connected to first bridge line146, and the second connection of fifth switch134(e.g., second I/O terminal329of third DGBD switch340) may be connected to third phase line154. For illustration, fifth switch134may be implemented using GaN-HEMTs or SiC-MOSFET transistors.

A gate terminal and/or a source terminal of sixth switch136(e.g., first gate terminal346and second gate terminal352of third DGBD switch340) may be connected to a PWM signal generator (e.g., first PWM signal generator358and second PWM signal generator362of third DGBD switch340) controlled by controller602. The first connection of sixth switch136(e.g., first I/O terminal328of third DGBD switch340) may be connected to third phase line154, and the second connection of sixth switch136(e.g., second I/O terminal329of third DGBD switch340) may be connected to second bridge line148. For illustration, sixth switch136may be implemented using GaN-HEMTs or SiC-MOSFET transistors.

First phase line150, second phase line152, and third phase line154are connected between the pair of switches of first inverter leg120, second inverter leg122, and third inverter leg124, respectively, and to AC load616through capacitive filter106.

First CSI100converts an input DC current from DC current source614on source line138to a three-phase current output signal with a first phase current signal output on first phase line150, with a second phase current signal output on second phase line152, and with a third phase current signal output on third phase line154. Capacitive filter106may be configured to reduce voltage spikes by reducing a rate of rise and fall of the first phase current signal, the second phase current signal, and the third phase current signal. First phase line150, second phase line152, and third phase line154may be connected to provide the three-phase current output signal to AC load616such as an induction motor, an electric utility grid, a local electric grid such as in a residence, etc.

First CSI100may be modified to support a greater or a fewer number of phases of the current output signal. For example, referring toFIG.4, a second CSI400is shown in accordance with an illustrative embodiment. Second CSI400is similar to first CSI100except that second CSI400generates a single-phase current output signal instead of the three-phase current output signal from first CSI100. Second CSI400may include a second switching circuit402, inductor104, and a second capacitive filter404. Second capacitive filter404may include first capacitor108. Second switching circuit402is connected between inductor104and second capacitive filter404. Second switching circuit402may include commutation switch114, commutation diode116, first inverter leg120, and second inverter leg122. First capacitor108is connected between first phase line150and second phase line152.

Second CSI400converts the input DC from DC current source614on source line138to a single-phase current output signal output on first phase line150. Second capacitive filter404may be configured to reduce voltage spikes by reducing a rate of rise and fall of the first phase current signal. First phase line150may be connected to provide the single-phase current output signal to AC load616.

As another example, referring toFIG.5, a third CSI500is shown in accordance with an illustrative embodiment. Third CSI500may be similar to first CSI100except that third current source inverter400generates a four-phase current output signal instead of the three-phase current output signal from first CSI100. Third CSI500may include a third switching circuit502, inductor104, and a third capacitive filter504. Third capacitive filter504may include first capacitor108, second capacitor110, third capacitor112, and a fourth capacitor514. Third switching circuit502is connected between inductor104and third capacitive filter504. Third switching circuit502may include commutation switch114, commutation diode116, first inverter leg120, second inverter leg122, third inverter leg124, and a fourth inverter leg506. Fourth inverter leg506may include a ninth switch508and a tenth switch510. Fourth capacitor514is connected between a fourth phase line512and filter line156.

A gate terminal and/or a source terminal of ninth switch508(e.g., first gate terminal346and second gate terminal352of third DGBD switch340) may be connected to a PWM signal generator (e.g., first PWM signal generator358and second PWM signal generator362of third DGBD switch340) controlled by controller602. The first connection of ninth switch508(e.g., first I/O terminal328of third DGBD switch340) may be connected to first bridge line146, and the second connection of ninth switch508(e.g., second I/O terminal329of third DGBD switch340) may be connected to fourth phase line512. For illustration, ninth switch508may be a SiC-MOSFET switch.

A gate terminal and/or a source terminal of tenth switch510(e.g., first gate terminal346and second gate terminal352of third DGBD switch340) may be connected to a PWM signal generator (e.g., first PWM signal generator358and second PWM signal generator362of third DGBD switch340) controlled by controller602. The first connection of tenth switch510(e.g., first I/O terminal328of third DGBD switch340) may be connected to fourth phase line512, and the second connection of tenth switch510(e.g., second I/O terminal329of third DGBD switch340) may be connected to second bridge line148. For illustration, tenth switch510may be a SiC-MOSFET switch.

Third CSI500converts the input DC from DC current source614on source line138to a four-phase current output signal with first phase current signal output on first phase line150, with second phase current signal output on second phase line152, with third phase current signal output on third phase line154, and with a fourth phase current signal output on fourth phase line512. Third capacitive filter504may be configured to reduce voltage spikes by reducing a rate of rise and fall of the first phase current signal, the second phase current signal, the third phase current signal, and the fourth phase current signal. First phase line150, second phase line152, third phase line154, and fourth phase line512may be connected to provide the four-phase current output signal to AC load616.

Referring toFIG.6A, a block diagram of a power conversion system600is shown in accordance with an illustrative embodiment. Power conversion system600may include controller602, DC current source614, AC load616, a sensor(s)618, and one or more of first CSI100, second CSI400, third CSI500, etc. For example, DC current source614may be a DC current source such as a battery, a solar panel, a current source rectifier, etc. Controller602may be electrically connected to DC current source614and to AC load616to receive voltage, current, and/or power values used to define the parameters that control the energy transfer between DC current source614and AC load616through first CSI100, second CSI400, third CSI500, etc. For brevity, hereafter CSI100,400,500refers to any of first CSI100, second CSI400, third CSI500, as well as other CSI that support additional phases. Controller602is also electrically connected to CSI100,400,500to receive a value of the DC-link current, for example, as well as to provide the gating signals, for example, to first PWM signal generator358and second PWM signal generator362of each inverter leg switch, and to PWM signal generator208of commutation switch114to control transmission of each on-state switching signal and each off-state switching signal. The voltage, current, and/or power values may be received for each switching frequency interval, also referred to herein as a switching period Ts, or may be received less frequently or more frequently depending on the dynamic needs of power conversion system600.

Power conversion system600may include one or more sensors618of the same or different type to measure system characteristics that may warrant a transition of power conversion system600from an inverting operating mode where energy is transferred from DC current source614to AC load616to a regenerating operating mode where energy is transferred from AC load616to DC current source614. Sensor(s)618may measure a physical quantity in an environment to which the sensor is associated and generate a corresponding measurement datum that may be associated with a time that the measurement datum is generated. Illustrative sensors include a pressure sensor, a temperature sensor, a position or location sensor, a voltage sensor, a current sensor, a frequency sensor, a speed sensor, etc. that may be mounted to various components used as part of a system to which power conversion system600is providing and/or receiving power.

Controller602may include an input interface604, an output interface606, a computer-readable medium608, a processor610, a control application612, and control data613. Fewer, different, and additional components may be incorporated into controller602. For example, controller602may include a communication interface (not shown). The communication interface provides an interface for receiving and transmitting data between devices using various protocols, transmission technologies, and media as understood by those skilled in the art. The communication interface may support communication using various transmission media that may be wired and/or wireless.

Input interface604provides an interface for receiving information from a user or from other devices for entry into controller602as understood by those skilled in the art. For example, controller602may receive a signal from sensor(s)618continuously, periodically, when an event occurs, etc. through input interface604. Input interface604may further interface with various input technologies including, but not limited to, a keyboard, a mouse, a display, a track ball, a keypad, one or more buttons, etc. to allow the user to enter information into controller602or to make selections in a user interface displayed on the display. The same interface may support both input interface604and output interface606. Controller602may have one or more input interfaces that use the same or a different input interface technology. Inputs through input interface604may include the voltage, current, and/or power values received from DC current source614and/or AC load616.

Output interface606provides an interface for outputting information for review by a user of controller602and for input to another device. For example, output interface606may interface with various output technologies including, but not limited to, the display. Controller602may have one or more output interfaces that use the same or a different interface technology. Additional outputs through output interface606from controller602may be the switching signals sent to CSI100,400,500, for example, by one or more of the PWM signal generators to each switch depending on the embodiment. For example, control application612may determine which switches of CSI100,400,500are in an on-state (e.g., first on-state, second on-state) and which are in an off-state. These signals may be provided to the switches of CSI100,400,500through output interface606using a respective PWM signal generator.

Computer-readable medium608is an electrical holding place or storage for information so the information can be accessed by processor610as understood by those skilled in the art. Computer-readable medium608can include, but is not limited to, any type of random access memory (RAM), any type of read only memory (ROM), any type of flash memory, etc. such as magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips, . . . ), optical disks (e.g., compact disc (CD), digital versatile disc (DVD), . . . ), smart cards, flash memory devices, etc. Controller602may have one or more computer-readable media that use the same or a different memory media technology. For example, computer-readable medium608may include different types of computer-readable media that may be organized hierarchically to provide efficient access to the data stored therein as understood by a person of skill in the art. As an example, a cache may be implemented in a smaller, faster memory that stores copies of data from the most frequently/recently accessed main memory locations to reduce an access latency. Controller602also may have one or more drives that support the loading of a memory media such as a CD, DVD, an external hard drive, etc. One or more external hard drives further may be connected to controller602using the communication interface.

Processor610executes instructions as understood by those skilled in the art. The instructions may be carried out by a special purpose computer, logic circuits, or hardware circuits. Processor610may be implemented, for example, as a field programmable gate array. Processor610may be implemented in hardware and/or firmware. Processor610executes an instruction, meaning it performs/controls the operations called for by that instruction. The term “execution” is the process of running an application or the carrying out of the operation called for by an instruction. The instructions may be written using one or more programming language, scripting language, assembly language, etc. Processor610operably couples with input interface604, with output interface606, and with computer-readable medium608to receive, to send, and to process information. Processor610may retrieve a set of instructions from a permanent memory device and copy the instructions in an executable form to a temporary memory device that is generally some form of RAM. Controller602may include a plurality of processors that use the same or a different processing technology.

Control application612performs operations associated with implementing some or all of the control of CSI100,400,500possibly based on sensor measurements from sensor(s)618among other sensors included as part of DC current source614and AC load616. The operations may be implemented using hardware, firmware, software, or any combination of these methods. Referring to the example embodiment ofFIG.6A, control application612is implemented in software (comprised of computer-readable and/or computer-executable instructions) stored in computer-readable medium608and accessible by processor610for execution of the instructions that embody the operations of control application612. Control application612may be written using one or more programming languages, assembly languages, scripting languages, etc.

Referring toFIG.6B, example operations associated with control application612are described. Additional, fewer, or different operations may be performed depending on the embodiment of control application612. The order of presentation of the operations ofFIG.6Bis not intended to be limiting. Some of the operations may not be performed in some embodiments. Although some of the operational flows are presented in sequence, the various operations may be performed simultaneously, for example, using multiple threads, in various repetitions and/or in other orders than those that are illustrated, for example, using interrupts.

Though not shown, control data613may be read into a RAM type of computer readable medium608by control application612when controller602is executing. For example, control data613may include various switching frequency timing parameters precomputed for control application612for power conversion system600as described further below.

In an operation620, a phase of AC load616may be received. A phase-locked-loop may be used to obtain a current three-phase voltage relationship at an output terminal from CSI100,400,500to AC load616.

In an operation622, a signal may be received from sensor(s)618that may determine whether power conversion system600should be in the inverting operating mode or the regenerating operating mode. For example, when power conversion system600is implemented in an electric vehicle (EV), regenerative braking may be used to extend the range of the EV and to save as much as 25% of the total energy required to operate the EV. The EV may typically be in the inverting operating mode until a foot brake signal is detected. Thus, sensor618may include a foot brake depression sensor. When the foot brake signal is received by controller602, controller602changes the switching signals sent to CSI100,400,500to affect a transition to the regenerating operating mode as described further below.

For other applications, such as in a construction crane or an elevator, a speed-loop may be employed to detect when to affect a transition to the regenerating operating mode. Thus, sensor618may include a speed sensor. Specifically, when the crane is lowering its freight, a kinetic energy due to a presence of the freight tends to speed up the crane. When this happens, the speed-loop detects the overspeed situation and switches the inverter driving the crane motor to the regenerating operating mode. As a result, the excess energy is fed back to DC current source614and the speed of the freight is maintained at the desired level. The EV, crane, elevator, etc. may remain in the regenerating operating mode until sensor(s)618no longer indicates the regenerating operating mode is appropriate based on the system operating rules.

In addition to a motor drive application, a bidirectional power flow may be used in a residence between a residence battery and a utility grid and/or a local grid defined for the residence. The time when the inverter should operate in the inverting operating mode or the regenerating operating mode can be determined by a local energy management system of the residence. Though not shown, since the DC-link voltage reverses its direction, to interface with DC current source614, a power electronics circuit is needed to change the voltage polarity.

In an operation624, a determination is made concerning whether CSI100,400,500should be in the inverting operating mode. For example, sensor measurements or logical rules may be used to determine whether CSI100,400,500should be in the inverting operating mode. When CSI100,400,500should be in the inverting operating mode, processing continues in an operation626. When CSI100,400,500should not be in the inverting operating mode, processing continues in an operation630.

In operation626, an on-state or an off-state signal determination is made for commutation switch114.

In an operation628, a first DGBD switch on-state, a second DGBD switch on-state, or an DGBD off-state signal determination is made for each inverter leg switch of CSI100,400,500, and processing continues in operation620to continue to determine an operating mode and/or switching signals. When CSI100,400,500is switching to the inverting operating mode from the regenerating operating mode, the phase received in operation620may be used to select a next set of switching signals.

Referring toFIGS.7A-7F, control signal time period snapshots for the example of first CSI100are shown for the inverting operating mode in accordance with an illustrative embodiment. The control signal time period snapshots shown referring toFIGS.7A-7Fare used to determine whether each inverter leg switch is in the first DGBD switch on-state, the second DGBD switch on-state, or the DGBD switch off-state, and to determine the on-state or the off-state for commutation switch114for the inverting operating mode as described further below.

In operation630, the first DGBD switch on-state or the DGBD off-state signal determination is made for each inverter leg switch of CSI100,400,500, and processing continues in operation620. Referring toFIGS.9A-9F, control signal time period snapshots for the example of first CSI100are shown for the regenerating operating mode in accordance with an illustrative embodiment. The control signal time period snapshots shown referring toFIGS.9A-9Fare used to determine whether each inverter leg switch is in the first DGBD switch on-state or the DGBD switch off-state as described further below.

In an operation632, commutation switch114is switched to the on-state if in the off-state, and processing continues in operation620to continue to determine an operating mode and/or switching signals.

To define the modulation of first CSI100, for example, consider a three-phase balanced set of sinusoidal voltage waveforms desired at the output of capacitive filter106that is input to AC load616. A first-phase output waveform (current, voltage, or power), which may be referred as an A-phase waveform, is created by operation of first inverter leg120and is output on first phase line150. A second-phase output waveform (current, voltage, or power), which may be referred as a B-phase waveform, is created by operation of second inverter leg122and is output on second phase line152. A third-phase output waveform (current, voltage, or power), which may be referred as a C-phase waveform, is created by operation of third inverter leg124and is output on third phase line154. As understood by a person of skill in the art, the current and voltage waveforms are 360/m degrees out of phase with each other, where m represents a number of phases. Thus, VA, VB, and VCand IA, IB, and ICare 120 degrees out of phase with each other.

A time interval of one period of the three-phase output waveforms can be divided into six sectors, depending on which of the phase voltages is the most positive and which of the phase voltages is the most negative. For example, in sector I, VAis the most positive and VBis the most negative; in sector II, VAis the most positive and VCis the most negative; in sector III, VBis the most positive and VCis the most negative; in sector IV, VBis the most positive and VAis the most negative; in sector V, VCis the most positive and VAis the most negative; and in sector VI, VCis the most positive and VBis the most negative. CSI100,400,500remains in a sector for ⅙ of a fundamental period. For example, a fundamental period may be 1/60. Once CSI100,400,500completes one fundamental period, CSI100,400,500returns to the first sector.

When in the inverting operating mode, control application612implements a control algorithm that operates first CSI100from sector I to sector VI as summarized inFIGS.7A-7Frespectively, and back to sector I in a continuous loop to continually respond to DC current source614and/or AC load616.FIG.7Arepresents sector I.FIG.7Brepresents sector II.FIG.7Crepresents sector III.FIG.7Drepresents sector IV.FIG.7Erepresents sector V.FIG.7Frepresents sector VI. Of course, when first CSI100implements a fewer or a greater number of phase currents, there are a fewer or a greater number of sectors. For example, second CSI400has two sectors, and third CSI500has fourteen sectors though implemented in a similar manner.

Referring toFIGS.7A-7F, S1aindicates the on-state for the first semiconductor switch of first switch126, S1bindicates the on-state for the second semiconductor switch of first switch126, S2aindicates the on-state for the first semiconductor switch of sixth switch136, S2bindicates the on-state for the second semiconductor switch of sixth switch136, S3aindicates the on-state for the first semiconductor switch of third switch130, S3bindicates the on-state for the second semiconductor switch of third switch130, S4aindicates the on-state for the first semiconductor switch of second switch128, S4bindicates the on-state for the second semiconductor switch of second switch128, S5aindicates the on-state for the first semiconductor switch of fifth switch134, S5bindicates the on-state for the second semiconductor switch of fifth switch134, S6aindicates the on-state for the first semiconductor switch of fourth switch132, S6bindicates the on-state for the second semiconductor switch of fourth switch132, and S7indicates the on-state of commutation switch114.

When the on-state for the first semiconductor switch and the on-state for the second semiconductor switch of the same DGBD switch occur at the same time, the respective DGBD switch is in the first DGBD switch on-state. When the on-state for the first semiconductor switch and the off-state for the second semiconductor switch occur at the same time, the respective DGBD switch is in the second DGBD switch on-state. The pulses indicate when the respective semiconductor switches are turned on. The non-designated switches in each sector are in the DGBD switch off-state. For example, “S1aS6a” indicates that the respective pair of first semiconductor switches of first switch126and fourth switch132are in the on-state based on an on-state control signal provided by the respective PWM signal generator. As another example, “S1bS6b” indicates that the respective pair of second semiconductor switches of first switch126and fourth switch132are in the on-state based on an on-state control signal provided by the respective PWM signal generator. As yet another example, “S7” indicates that commutation switch114is in the on-state based on an on-state control signal provided by the respective PWM signal generator such as PWM signal generator208.

Referring toFIG.7A, a sector I pulse sequence720is shown in accordance with an illustrative embodiment. A first pulse700is initiated at a time designated as zero and is ended at a time designated as Ta; a second pulse701is initiated at the time designated as Taand is ended at a time designated as Tb; a third pulse702is initiated at the time designated as Tband is ended at a time designated as Tsto show a single switching period. In sector I, first pulse700is generated for S1aS6a(first switch126and fourth switch132), second pulse701is generated for S1aS2a(first switch126and sixth switch136), and third pulse702is generated for S1aS6a.

In sector I, a fourth pulse703is also initiated at the time designated as zero and is ended at a time designated as Tn1; a fifth pulse704is also initiated at a time designated as Tn2and is ended at a time designated as Tn3; a sixth pulse705is also initiated at a time designated as Tn4and is ended at a time designated as Tn5; and a seventh pulse706is also initiated at a time designated as Tn6and is ended at the time designated as Ts. In sector I, fourth pulse703, fifth pulse704, sixth pulse705, and seventh pulse706are generated for S7, which is commutation switch114.

In sector I, an eighth pulse707is also initiated at a time designated as To1and is ended at a time designated as To2; a ninth pulse708is also initiated at a time designated as To3and is ended at a time designated as To4; and a tenth pulse709is also initiated at a time designated as To5and is ended at a time designated as To6. In sector I, eighth pulse707is generated for S1bS6b(first switch126and fourth switch132), ninth pulse708is generated for S1bS2b(first switch126and sixth switch136), and tenth pulse709is generated for S1bS6b. Thus, in sector I, first switch126and fourth switch132and first switch126and sixth switch136are “active” at least a portion of the time, where active indicates that the first on-state or the second on-state is applied to a switch during a switching period defined by Ts.

Referring toFIGS.8A-8F, a description of a switching portion716is provided in accordance with an illustrative embodiment. Referring toFIG.8A, first switch126and fourth switch132are each in the first DGBD switch state, for example, from the time designated as To1to the time designated as To2. First switch126and fourth switch132are fully turned on to conduct the DC-link current through active state S1S6.

Referring toFIG.8B, first switch126and fourth switch132are each in the second DGBD switch state, for example, from the time designated as To2to the time designated as Tn2. First switch126and fourth switch132are behaving as reverse voltage blocking switches.

Referring toFIG.8C, first switch126and fourth switch132are each in the second DGBD switch state, and commutation switch114is receiving the on-state signal, for example, from the time designated as Tn2to the time designated as Ta. First switch126, fourth switch132, and commutation switch114are behaving as reverse voltage blocking switches to avoid an interphase short-circuit.

Referring toFIG.8D, first switch126and sixth switch136are each in the second DGBD switch state, and commutation switch114is receiving the on-state signal, for example, from the time designated as Tato the time designated as Tn3. First switch126, sixth switch136, and commutation switch114are behaving as reverse voltage blocking switches. A current path for inductor104is provided due to commutation switch114receiving the on-state signal, and a transition from switch S6(fourth switch132) to S2(sixth switch136) can be made under zero-current switching (ZCS) conditions. Due to the rise/fall times and propagation delays associated with the switch turn on/off processes, the conduction time of S7(commutation switch114) is long enough to cover the complete transition process.

Referring toFIG.8E, first switch126and sixth switch136are each in the second DGBD switch state, and commutation switch114is receiving the off-state signal, for example, from the time designated as Tn3to the time designated as To3. First switch126and sixth switch136are behaving as reverse voltage blocking switches. Since S1and S2are now conducting to provide a current path for the DC-link current, S7can be turned off.

Referring toFIG.8F, first switch126and sixth switch136are each in the first DGBD switch state, from the time designated as To3to the time designated as To4. The gates of the second semiconductor switches of S1and S2are also turned on to reduce the conduction loss of each switch.

The time values can be determined based on known time values for a conventional CSI using six switches that are not bidirectional (H6-CSI), for example, as described in B. Wu,High-Power Converters and AC Drives, Ch. 10, pp. 189-218, Wiley, 2006. Tsis the inverter switching period, and fsis a switching frequency, where

Ts=1fs·Iref
is a desired inverter output current waveform peak value, Idis an inverter DC-link current value, and mais a modulation index that ranges from 0 to 1, where

ma=IrefId·T1
is the H6-CSI space vector S1S6's dwell time in one Tswithout considering overlap time, and θ is an angle of the space vector, where

T1=ma·sin⁡(π6-θ)·Ts·T2
is the H6-CSI space vector S1S2's dwell time in one Tswithout considering overlap time, where

T2=ma·sin(π6+θ)·Ts.T0
is the H6-CSI space vector zero state's dwell time in one Tswithout considering overlap time, where T0=Ts−T1−T2. Using these values,

Ta=T12+38⁢T0,Tb=Ta+T2+14⁢T0,Tn⁢⁢1=T04,Tn⁢⁢2=Ta-T08,Tn⁢⁢3=Ta+T08,Tn⁢⁢4=Tb-T08,Tn⁢⁢5=Tb+T08,and⁢⁢Tn⁢⁢6=Ts-T04.

A first time period710is defined between the end of fourth pulse703and the initiation of eighth pulse707. A second time period711is defined between the end of eighth pulse707and the initiation of fifth pulse704. A third time period712is defined between the end of fifth pulse704and the initiation of ninth pulse708. A fourth time period713is defined between the end of ninth pulse708and the initiation of sixth pulse705. A fifth time period714is defined between the end of sixth pulse705and the initiation of tenth pulse709. A sixth time period715is defined between the end of tenth pulse709and the initiation of seventh pulse706. First time period710, second time period711, third time period712, fourth time period713, fifth time period714, and sixth time period715are approximately equal and may be referred to as a dead-band time period TDB. The dead-band time period TDBis inserted between switching the state of commutation switch114from on to off or off to on and switching the second on-state from on to off or off to on for whichever switches (e.g., first switch126, second switch128, third switch130, fourth switch132, fifth switch134, and/or sixth switch136) are in the first on-state to avoid a short-circuit. Increasing the dead-band time period TDBincreases the conduction loss, however, so the value may be selected to avoid the short-circuit, but not too long to avoid increasing the conduction loss. Based on the dead-band time period TDB, To1=Tn1+TDB, To2=Tn2−TDB, To3−Tn3+TDB, To4=Tn4−TDB, To5=Tn5=TDB, and To6=Tn6−TDB.

Referring toFIG.7B, a sector II pulse sequence722is shown in accordance with an illustrative embodiment. In sector II, first pulse700is generated for S1aS2a(first switch126and sixth switch136), second pulse701is generated for S2aS3a(sixth switch136and third switch130), third pulse702is generated for S1aS2a, eighth pulse707is generated for S1bS2b, ninth pulse708is generated for S2bS3b, and tenth pulse709is generated for S1bS2b.

Referring toFIG.7C, a sector III pulse sequence724is shown in accordance with an illustrative embodiment. In sector III, first pulse700is generated for S2aS3a(sixth switch136and third switch130), second pulse701is generated for S3aS4a(third switch130and second switch128), third pulse702is generated for S2aS3a, eighth pulse707is generated for S2bS3b, ninth pulse708is generated for S3bS4b, and tenth pulse709is generated for S2bS3b.

Referring toFIG.7D, a sector IV pulse sequence726is shown in accordance with an illustrative embodiment. In sector IV, first pulse700is generated for S3aS4a(third switch130and second switch128), second pulse701is generated for S4aS5a(second switch128and fifth switch134), third pulse702is generated for S3aS4a, eighth pulse707is generated for S3bS4b, ninth pulse708is generated for S4bS5b, and tenth pulse709is generated for S3bS4b.

Referring toFIG.7E, a sector V pulse sequence728is shown in accordance with an illustrative embodiment. In sector V, first pulse700is generated for S4aS5a(second switch128and fifth switch134), second pulse701is generated for S5aS6a(fifth switch134and fourth switch132), third pulse702is generated for S4aS5a, eighth pulse707is generated for S4bS5b, ninth pulse708is generated for S5bS6b, and tenth pulse709is generated for S4bS5b.

Referring toFIG.7F, a sector VI pulse sequence730is shown in accordance with an illustrative embodiment. In sector VI, first pulse700is generated for S5aS6a(fifth switch134and fourth switch132), second pulse701is generated for S1aS6a(first switch126and fourth switch132), third pulse702is generated for S5aS6a, eighth pulse707is generated for S5bS6b, ninth pulse708is generated for S1bS6b, and tenth pulse709is generated for S5bS6b. Processing continuously repeats the cycle fromFIGS.7A-7Funtil there is a change indicated to switch to the regenerating operating mode. Thus, once sector VI pulse sequence730is sector I pulse sequence720is started again.

When in the regenerating operating mode, control application612implements a control algorithm that operates first CSI100from sector I to sector VI as summarized inFIGS.9A-9F, respectively, and back to sector I in a continuous loop to continually respond to DC current source614and/or AC load616.FIG.9Arepresents sector I.FIG.9Brepresents sector II.FIG.9Crepresents sector III.FIG.9Drepresents sector IV.FIG.9Erepresents sector V.FIG.9Frepresents sector VI.

Referring toFIG.9A, a sector I pulse sequence910for the regenerating operating mode is shown in accordance with an illustrative embodiment. A first pulse900is initiated at a time designated as Tn1and is ended at a time designated as Tn2; a second pulse901is initiated at the time designated as Tn3and is ended at a time designated as Tn4; a third pulse902is initiated at the time designated as Tn5and is ended at a time designated as Tn6. In sector I, first pulse900is generated for S3aS4aand for S3bS44b(third switch130and second switch128are each in the first DGBD switch state), second pulse901is generated for S4aS5aand for S4bS5b(second switch128and fifth switch134are each in the first DGBD switch state), and third pulse902is generated for S3aS4aand for S3bS44b. When in the regenerating operating mode, the on-state signal is continually sent to commutation switch114as indicated by a fourth pulse903.

A first time period905is defined between the time designated as zero and the initiation of first pulse900. A second time period906is defined between the end of first pulse900and the initiation of second pulse901. A third time period907is defined between the end of second pulse901and the initiation of third pulse902. As defined above,

Tn⁢⁢1=T04,Tn⁢⁢2=Ta-T08,Tn⁢⁢3=Ta+T08,Tn⁢⁢4=Tb-T08,Tn⁢⁢5=Tb+T08,and⁢⁢Tn⁢⁢6=Ts-T04.
In sector I, third switch130and second switch128are each in the first DGBD switch state, for example, from the time designated as Tn1to the time designated as Tn2and from the time designated as Tn5to the time designated as Tn6. In sector I, second switch128and fifth switch134are each in the first DGBD switch state, for example, from the time designated as Tn3to the time designated as Tn4.

Referring toFIG.9B, a sector II pulse sequence912for the regenerating operating mode is shown in accordance with an illustrative embodiment. In sector II, first pulse900is generated for S4aS5aand for S4bS5b(second switch128and fifth switch134are each in the first DGBD switch state), second pulse901is generated for S5aS6aand for S5bS6b(fifth switch134and fourth switch132are each in the first DGBD switch state), and third pulse902is generated for S4aS5aand for S4bS5b.

Referring toFIG.9C, a sector III pulse sequence914for the regenerating operating mode is shown in accordance with an illustrative embodiment. In sector III, first pulse900is generated for S5aS6aand for S5bS6b(fifth switch134and fourth switch132are each in the first DGBD switch state), second pulse901is generated for S1aS6aand for S1bS6b(first switch126and fourth switch132are each in the first DGBD switch state), and third pulse902is generated for S5aS6aand for S5bS6b.

Referring toFIG.9D, a sector IV pulse sequence916for the regenerating operating mode is shown in accordance with an illustrative embodiment. In sector IV, first pulse700is generated for S1aS6aand for S1bS6b(first switch126and fourth switch132are each in the first DGBD switch state), second pulse701is generated for S1aS2aand for S1bS2b(first switch126and sixth switch136are each in the first DGBD switch state), and third pulse702is generated for S1aS6aand for S1bS6b.

Referring toFIG.9E, a sector V pulse sequence918for the regenerating operating mode is shown in accordance with an illustrative embodiment. In sector V, first pulse900is generated for S1aS2aand for S1bS2b(first switch126and sixth switch136are each in the first DGBD switch state), second pulse901is generated for S2aS3aand for S2bS3b(sixth switch136and third switch130are each in the first DGBD switch state), and third pulse902is generated for S1aS2aand for S1bS2b.

Referring toFIG.9F, a sector VI pulse sequence920for the regenerating operating mode is shown in accordance with an illustrative embodiment. In sector VI, first pulse900is generated for S2aS3aand for S2bS3b(sixth switch136and third switch130are each in the first DGBD switch state), second pulse901is generated for S3aS4aand for S3bS4b(third switch130and second switch128are each in the first DGBD switch state), and third pulse902is generated for S2aS3aand for S2bS3b. Processing continuously repeats the cycle fromFIGS.9A-9Funtil there is a change indicated to switch to the inverting operating mode.

To summarize, in the inverting operating mode, for each sector, a pair of DGBD switches in different inverter legs is switched between the first DGBD switch state and the second DGBD switch state or vice versa, and commutation switch114is switched between the on-state and the off-state when a state changes for one of the pair of DGBD switches in the different inverter legs. In the regenerating operating mode, for each sector, commutation switch114is in the on-state, and a pair of DGBD switches in different inverter legs is switched between the first DGBD switch state and the DGBD switch off-state.

Fast-switching CSIs are alternatives to conventional voltage-source inverters (VSIs) due to a higher fault-tolerance, improved reliability, sinusoidal output voltage waveforms, higher temperature capability, and suitability for medium-voltage applications. BD switches can block bidirectional voltages and conduct bidirectional currents, while RB switches block bidirectional voltages, but only conduct unidirectional current. Therefore, when a BD switch is gated on, it can provide a path for reverse-flowing current, which is not the case for an RB switch such as commutation switch114. Differences in the current-voltage characteristics complicate a direct replacement of RB switches with BD switches in a traditional H6-CSI topology, creating risks of transient overvoltage or overcurrent. Furthermore, the increased switching frequency of BD switches typically leads to elevated common-mode (CM) electro-magnetic interference (EMI) generation in power converters that can pose serious problems for the power electronics and machine loads.

The combination of commutation switch114implemented as an RB switch and replacement of the inverter switches with DGBD switches overcomes these issues. The modulation schemes described byFIGS.7A-7FandFIGS.9A-9Fsolve an issue of short-circuits that result when simply replacing the inverter switches with bidirectional switches and further achieve higher efficiency compared to the H6-CSI topology and noticeably reduce a conducted CM EMI.

To compare the efficiency of the H6-CSI using RB switches and the H7-CSI using DGBD switches shown as first CSI100, two inverters were designed. Both inverters were designed to operate with a 50 kilohertz (kHz) switching frequency, a 100 Hz fundamental frequency, 195 volts of line-to-line root mean square voltage, with 2.0 kilowatts (kW) output. The load for both inverters was a 3-phase resistive-inductive load with 19.1 ohms and 1.6 millihenries (mH) per phase. The H6-CSI topology (labeled as Case 1) used the “FET+Diode” RB switch shown for RB commutation switch118. For the H7-CSI topology, two cases, Case 2 and Case 3, were considered. In Case 2, hybrid BD switches were adopted using two discrete SiC-MOSFET devices connected as shown inFIG.3C. More specifically, Case 2 used six dual-gate hybrid BD switches for S1-S6. In addition, a hybrid “FET+Diode” RB switch was used for S7. For Case 3, switches S1-S6were implemented as projected monolithic BD switches that have the same on-state resistance as standard SiC-MOSFETs with the same voltage and current ratings. Case 3 assumed that the monolithic BD switches adopted a common-drain configuration. A monolithic common-drain BD switch can have nearly identical on-state resistance as a standard switch with the same ratings. All of the other passive components were identical for the three inverter cases.

Inductor104was split into two halves with one half of 250 microhenries (μH) connected in source line138and the other half of 250 μH connected in second bus line140. The split inductor arrangement reduces the conducted CM EMI. An overlap time for the H6-CSI was 120 nanoseconds (ns) and the dead-band time period TDBwas 120 ns for Case 2 and Case 3, and ma=0.952. First capacitor108, second capacitor110, and third capacitor112were 3.9 microfarads. The DC-link current was 8.835 Amps (A) for the H6-CSI and was 8.671 A for Case 2 and Case 3.

The H7-CSI using DGBD switches with the modulation scheme ofFIGS.7A-7Fgenerated nearly sinusoidal output voltage and current that was nearly identical to those generated by the H6-CSI using RB switches. Table I below summarizes the loss and simulated efficiency results for all three cases.

TABLE ICase123InverterH6-CSIH7-CSIH7-CSISwitching lossS1-S6: 6.61 WS1-S6: 0 WS1-S6: 0 WS7: 6.66 WS7: 6.66 WConduction lossS1-S6: 30.54 WS1-S6: 19.56 WS1-S6: 11.91 WS7: 1.35 WS7: 1.35 WInductor Loss15.0W15.0W15.0WOutput capacitors4.5W4.5W4.5Wand other lossesTotal Loss56.65W44.41W36.76WOutput power1964W1962W1962WEfficiency97.20%97.79%98.16%

The switches S1-S6in the H6-CSI operated under hard switching conditions and experienced significant switching loss. On the contrary, switches S1-S6of first CSI100operated under nearly ZCS conditions resulting in nearly zero switching loss due to the placement of zero states using S7, commutation switch114. Instead, all of the switching loss is induced in S7, commutation switch114, and its switching loss is close to the total switching loss in H6-CSI. The use of DGBD switches (either hybrid or monolithic) can reduce first CSI100's conduction loss significantly compared to H6-CSI using RB switches. S7's conduction loss in Case 2 and Case 3 is very low even though it uses an RB switch because S7only conducts during the zero-state of first CSI100, which is very short for large modulation index conditions. For low modulation index conditions, the conduction loss of S7is still lower than the conduction loss of the H6-CSI using RB switches during the zero-state because two RB switches must conduct the DC-link current during the zero-state in the H6-CSI compared to the single switch S7conducting in first CSI100.

Experiments were conducted to examine the performance of the H6-CSI and first CSI100. Due to the lack of monolithic BD switches, only Case 1 and Case 2 were evaluated. For Case 1, three half-bridges corresponding to the three switch groups (S1, S4), (S3, S6) and (S5, S2) were fabricated. Each hybrid RB switch consisted of a SiC-MOSFET and a SiC-Schottky diode. The device models were identical to those described above relative to Case 1.

Similarly, for Case 2, three half-bridges were built. For each hybrid DGBD switch, two SiC-MOSFETs were connected in an anti-series configuration, with their sources connected as shown inFIG.3C. Two gate drives were employed for the two independent gates of the MOSFETs. A separate DC-link printed circuit board (PCB) was used for both inverters. The half-bridges and the DC-link board were mounted on a motherboard. When testing the H6-CSI, the same motherboard was used. However, switch S7was removed from the DC-link board, and the three half bridges used the hybrid RB switches.

The modulation algorithms were implemented using a Xilinx FPGA controller. For the H6-CSI, the zero state was realized by the simultaneous conduction of S1and S4. During each state transition, the overlap time was imposed to ensure a current path for inductor104. The measured output voltage and current waveforms using first CSI100were high-quality sinusoids and nearly identical to the H6-CSI waveforms.

A Yokogawa WT1806 power analyzer was used to measure the efficiencies of the H6-CSI and first CSI100. Referring toFIG.10, a first efficiency curve1000shows the efficiency of first CSI100as a function of the inverter power, and a second efficiency curve1002shows the efficiency of H6-CSI as a function of the inverter power. First CSI100achieved significantly improved efficiency compared to the H6-CSI using RB switches. The measured results agree with the simulated efficiency results shown in Table I at 2 kW.

The CM-EMIs of the H6-CSI and first CSI100were measured. Referring toFIG.11, a first CM-EMI curve1100shows the CM-EMI of first CSI100as a function of the frequency, and a second CM-EMI curve1102shows the CM-EMI of the H6-CSI as a function of the frequency. First CSI100exhibited lower CM-EMI compared to the H6-CSI, confirming this benefit of first CSI100with the modulation scheme ofFIGS.7A-7F.

Referring toFIG.12, a first regenerating efficiency curve1200shows the efficiency of first CSI100as a function of the inverter power when in the regenerating operating mode, and a second regenerating efficiency curve1202shows the efficiency of the H6-CSI as a function of the inverter power when in the regenerating operating mode. First CSI100achieved significantly improved efficiency compared to the H6-CSI using RB switches.

Referring toFIG.13A, a simulated three-phase voltage generated by first CSI100before, during, and after a transition1312from providing power to the AC load to receiving power from the AC load is shown in accordance with an illustrative embodiment. Transition1312from the inverting operating mode to the regenerating operating mode occurred at ˜2 seconds. A first-phase voltage curve1300shows an A-phase voltage waveform. A second-phase voltage curve1302shows a B-phase voltage waveform. A third-phase voltage curve1304shows a C-phase voltage waveform.

Referring toFIG.13B, a simulated three-phase current generated by first CSI100before, during, and after transition1312is shown in accordance with an illustrative embodiment. A first-phase current curve1306shows an A-phase current waveform. A second-phase current curve1308shows a B-phase current waveform. A third-phase current curve1310shows a C-phase current waveform. Once regeneration begins, first CSI100absorbs energy from AC load616and supplies such energy to DC current source614. Therefore, the current has a 180-degree phase shift as compared to its phase during the inverting operating mode. The voltage phase does not change.

The word “illustrative” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “illustrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Further, for the purposes of this disclosure and unless otherwise specified, “a” or “an” means “one or more”. Still further, using “and” or “or” in the detailed description is intended to include “and/or” unless specifically indicated otherwise.

The foregoing description of illustrative embodiments of the disclosed subject matter has been presented for purposes of illustration and of description. It is not intended to be exhaustive or to limit the disclosed subject matter to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the disclosed subject matter. The embodiments were chosen and described in order to explain the principles of the disclosed subject matter and as practical applications of the disclosed subject matter to enable one skilled in the art to utilize the disclosed subject matter in various embodiments and with various modifications as suited to the particular use contemplated.