Patent ID: 12232434

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A resistive random access memory (RRAM) cell includes a data storage structure (e.g., one or more oxide layer(s)) arranged between a top electrode and a bottom electrode. The RRAM cell is disposed over a semiconductor substrate. A variable resistance of the data storage structure represents a data unit, such as a bit of data. Depending on a voltage applied between the top and bottom electrodes, the variable resistance undergoes a reversible change between a high resistance state and a low resistance state corresponding to data states of the data unit. The high resistance state is high in that the variable resistance exceeds a threshold, and the low resistance state is low in that the variable resistance is below the threshold.

Before an RRAM cell can be used to store data, an initial conductive path (i.e., conductive filament) is typically formed across the data storage structure. Formation of the initial conductive path makes subsequent write operations (that form the conductive path) easier to perform. To form the initial conductive path, at the end of the RRAM manufacturing process a forming voltage is applied across the top and bottom electrodes. In some types of RRAM cells, the conductive path may include vacancies (e.g., oxygen vacancies). In such devices the forming voltage may knock oxygen atoms out of a lattice of the data storage structure, thereby forming localized oxygen vacancies. These localized oxygen vacancies tend to align to form the conductive path which extends through the data storage structure. Thereafter, set or reset voltages can be applied across the top and bottom electrodes to change resistivity of the data storage structure between the high resistance state and the low resistance state. Generally, the forming voltage is greater than the set voltage. Typically, one or more transistors (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) disposed on/over the semiconductor substrate provide voltages to the RRAM cell, such that the forming voltage, the set voltage, and the reset voltage may be applied across the top electrode and the bottom electrode.

In some embodiments in which the conductive filament is formed before the RRAM cell is used to store data, the data storage structure may be or comprise an undoped metal oxide structure (e.g., undoped aluminum oxide (AlOx)). In such embodiments, the forming voltage may be relatively high. In an effort to improve device density and device performance, feature sizes of the one or more transistors and/or RRAM cell are continually being scaled down. However, as the feature sizes of the one or more transistors are scaled down, the relatively high forming voltage becomes problematic (e.g., due to the reduced feature sizes of the one or more transistors reducing breakdown voltages). The relatively high forming voltage may be greater than a safe output voltage of the one or more transistors. Accordingly, if the one or more transistors are operated to output the relatively high forming voltage, the one or more transistors may be damaged and/or destroyed.

The present application, in some embodiments, is directed toward an RRAM cell that has a low forming voltage. The RRAM cell includes a top electrode, a bottom electrode, and a data storage structure disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material (e.g., aluminum oxide (AlOx)) multi-doped with multiple dopants. For example, the multiple dopants may include a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and/or a third dopant (e.g., hafnium). Because the data storage structure is multi-doped with the first dopant, second dopant, and/or third dopant, a forming voltage of the RRAM cell may be improved (e.g., reduced) while maintaining good reliability of the RRAM cell. For example, doping the data storage structure with the first dopant may reduce or eliminate the forming voltage of the RRAM cell, doping the data storage structure with the second dopant may increase or maintain reliability of the RRAM cell (e.g., good retention performance), and doping the data storage structure with the third dopant may reduce a current leakage path of the RRAM cell (e.g., good endurance performance). Accordingly, an integrated chip comprising the RRAM cell may have one or more transistor(s) with scaled down feature sizes that can safely provide the low forming voltage to the RRAM cell. This, in turn, facilitates shrinking the feature sizes of the RRAM cell and the one or more transistor(s) and/or reducing a power consumption of the integrated chip while mitigating damage to the RRAM cell and/or the one or more transistors(s).

FIG.1illustrates a schematic view of some embodiments of a memory device100including a memory cell104having a data storage structure108that is multi-doped and has a low forming voltage.

The memory device100includes the memory cell104electrically coupled to a transistor102, such that the memory device100is in a one transistor-one resistive memory cell (1T1R) configuration. In some embodiments, the transistor102may, for example, be a metal-oxide-semiconductor field-effect transistor (MOSFET). The memory cell104includes a bottom electrode106, a top electrode112, a capping layer110, and the data storage structure108disposed between the bottom and top electrodes106,112. In some embodiments, the bottom electrode106is referred to as a lower conductive structure and the top electrode112is referred to as an upper conductive structure. A bit line (BL) is electrically coupled to one end of the data storage structure108through the top electrode112, and a source line (SL) is electrically coupled to an opposite end of the data storage structure108by way of the transistor102. A word line (WL) is electrically coupled to a gate electrode of the transistor102. Thus, application of a suitable WL voltage to the gate electrode of the transistor102couples the memory cell104between the BL and the SL. Consequently, in some embodiments, by providing suitable bias conditions, the memory cell104can be switched between two states of electrical resistance, a low resistance state and a high resistance state, to store data.

In some embodiments, the data storage structure108comprises a dielectric material (e.g., aluminum oxide (AlOx)) multi-doped with multiple dopants. For example, the multiple dopants may include a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and/or a third dopant (e.g., hafnium). In some embodiments, the dielectric material may be a metal oxide. Thus, in various embodiments, the data storage structure108may comprise aluminum oxide, nitrogen, tantalum, and hafnium and/or may have a thickness within a range of about 10 to 60 angstroms. In further embodiments, between about 5 to 10 percent of a chemical composition of the data storage structure108is the first dopant (e.g., nitrogen). In yet further embodiments, between about 12 to 18 percent of a chemical composition of the data storage structure108is the second dopant (e.g., tantalum). In some embodiments, between about 15 to 22 percent of a chemical composition of the data storage structure108is the third dopant (e.g., hafnium). In yet further embodiments, the data storage structure108may be referred to as a multi-dopant switching layer (MDSL). In some embodiments, the memory cell104may be configured as a resistive random access memory (RRAM) cell, such that the data storage structure108comprises material(s) having a variable resistance configured to undergo a reversible phase change between a high resistance state and a low resistance state.

In some embodiments, before the memory cell104may be used to store data, an initial conductive path (i.e., conductive filament) is typically formed within a region114across the data storage structure108. Formation of the initial conductive path makes subsequent write operations (that form the conductive path) easier to perform. In further embodiments, to formed the initial conductive path, a forming voltage is applied across the top electrode112and the bottom electrode106by the transistor102and the BL. The initial conductive path may include vacancies (e.g., oxygen vacancies). In such embodiments, the forming voltage may knock oxygen atoms out of a lattice of the data storage structure108, thereby forming localized oxygen vacancies. These localized vacancies tend to align with the region114to form the initial conductive path which extends within the data storage structure108from the bottom electrode106to the capping layer110. Thereafter, set or reset voltages can be applied across the bottom and top electrodes106,112by way of the transistor102and the BL, to change resistivity of the data storage structure108between the high resistance state and the low resistance state.

In various embodiments, by virtue of the data storage structure108comprising the first dopant (e.g., nitrogen), the forming voltage may be reduced and/or eliminated. For example, in some embodiments, formation of the initial conductive path may not be performed before a set operation is performed on the memory cell104, such that a forming voltage is not applied across the data storage structure108and/or the transistor102. This in turn facilitates shrinking the feature sizes of the memory cell104and/or the transistor102while mitigating damage to the memory cell104and/or the transistor102. In some embodiments, the forming voltage may be equal to a set voltage. In further embodiments, by virtue of the data storage structure108comprising the second dopant (e.g., tantalum), data retention of the memory cell104may be improved. In such embodiments, the second dopant has a strong bond with oxygen atoms within the data storage structure108, such that heat applied to the data storage structure108during formation and/or operation of the data storage structure108may not break the strong bond between the second dopant and oxygen atoms. In various embodiments, by virtue of the data storage structure108comprising the first dopant (e.g., nitrogen) and the second dopant (e.g., tantalum), the data retention of the memory cell104may be future improved. In yet further embodiments, by virtue of the data storage structure108comprising the third dopant (e.g., hafnium), endurance of the memory cell104may be improved. In such embodiments, the third dopant is configured to reduce a current leakage path in the RRAM cell. In various embodiments, by virtue of the data storage structure108comprising the first dopant (e.g., nitrogen) and the third dopant (e.g., hafnium), the current leakage path in the memory cell104is further decreased. Thus, because the data storage structure108is multi-doped with the first dopant, second dopant, and/or third dopant, the forming voltage of the memory cell104may be improved (e.g., reduced or eliminated) while maintaining good data retention and good endurance of the memory cell104.

FIG.2illustrates a cross-sectional view of some embodiments of a memory device200including the memory cell104having the data storage structure108that comprises the first dopant, the second dopant, and/or the third dopant.

In some embodiments, the memory device200includes an interconnect dielectric structure216and a substrate202. In some embodiments, the substrate202may, for example, be or comprise a semiconductor body such as monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), a silicon-on-insulator (SOI), or another suitable semiconductor substrate material and/or the substrate202may comprise a first doping type (e.g., p-type). The transistor102is disposed over/within the substrate202. In some embodiments, the transistor102may, for example, be or comprise a metal oxide semiconductor field effect transistor (MOSET), a high voltage transistor, a bipolar junction transistor (BTJ), an n-channel metal oxide semiconductor (nMOS) transistor, a p-channel metal oxide semiconductor (pMOS) transistor, or another suitable transistor. It will be appreciated that the transistor102being configured as another semiconductor device is also within the scope of the disclosure. In further embodiments, the transistor102may, for example, be configured as a gate-all-around FET (GAAFET), a gate-surrounding FET, a multi-bridge channel FET (MBCFET), a nanowire FET, a nanoring FET, a nanosheet field-effect transistor (NSFET), or the like. In further embodiments, the transistor102may include source/drain regions204, a gate dielectric layer206, a gate electrode208, and/or a sidewall spacer structure210. The source/drain regions204may be disposed within the substrate202and/or may comprise a second doping type (e.g., n-type) opposite the first doping type.

A lower interconnect via212is disposed within the interconnect dielectric structure216and overlies a source/drain region204of the transistor102. In some embodiments, the interconnect dielectric structure216may, for example, be or comprise one or more inter-level dielectric (ILD) layers. The one or more ILD layers may, for example, respectively be or comprise silicon oxide, a low-κ dielectric material, an extreme low-κ dielectric material, another suitable dielectric material, or any combination of the foregoing. As used herein, a low-κ dielectric material may be or comprise, for example, a dielectric material with a dielectric constant less than about 3.9, 3, 2, or 1.5. A lower interconnect wire214overlies the lower interconnect via212. In some embodiments, the lower interconnect via and wire212,214may, for example, respectively be or comprise copper, aluminum, tungsten, ruthenium, titanium nitride, tantalum nitride, ruthenium, another conductive material, or any combination of the foregoing. A bottom electrode via218is disposed within the interconnect dielectric structure216and overlies the lower interconnect wire214. A top electrode via220overlies the bottom electrode via218. The memory cell104is disposed within the interconnect dielectric structure216between the bottom electrode via218and the top electrode via220. An upper interconnect via222is disposed over the top electrode via220, and an upper interconnect wire224overlies the upper interconnect via222.

In some embodiments, the memory cell104includes the bottom electrode106, the capping layer110, the top electrode112, and the data storage structure108disposed between the bottom and top electrodes106,112. During operation, the memory cell104relies on redox reactions to form and dissolve a conductive path228in a region114of the data storage structure108between the bottom electrode106and the capping layer110. The existence of the conductive path228in the region114between the bottom electrode106and the capping layer110produces a low resistance state, while the absence of the conductive path228in the region114results in a high resistance state. Thus, the memory cell104can be switched between the high resistance state and the low resistance state by applying appropriate biases to the memory cell104to produce or dissolve the conductive path228in the region114. In further embodiments, the conductive path228may, for example, include oxygen vacancies226disposed within the region114and extending between the bottom electrode106and the capping layer110.

In some embodiments, the data storage structure108may comprise a multi-doped dielectric material, such that the data storage structure108includes a dielectric material, a first dopant, a second dopant, and a third dopant. In some embodiments, the dielectric material may, for example, be or comprise a high-κ dielectric material, aluminum oxide (e.g., Al2O3), tantalum oxide (e.g., Ta2O5), hafnium oxide (e.g., HfO2), another dielectric material, or any combination of the foregoing. As used herein, a high-κ dielectric material may, for example, be or comprise a dielectric material with a dielectric constant greater than approximately 3.9, 9.34, 9.9, or 11.54. In some embodiments, the first dopant may, for example, be or comprise nitrogen, silicon, fluorine, or the like. It will be appreciated that the first dopant comprising other elements is also within the scope of the disclosure. In further embodiments, the second dopant may, for example, be or comprise tantalum, cerium, or the like. It will be appreciated that the second dopant comprising other elements is also within the scope of the disclosure. In yet further embodiments, the third dopant may, for example, be or comprise hafnium, zirconium, or the like. It will be appreciated that the third dopant comprising other elements is also within the scope of the disclosure. Thus, in some embodiments, the data storage structure108may, for example, be or comprise aluminum oxide (e.g., Al2O3) doped with the first dopant, the second dopant, and the third dopant, where the first, second, and third dopants are each different from one another. In various embodiments, the first dopant may be configured to reduce a forming voltage of the data storage structure108, the second dopant may be configured to increase data retention of the data storage structure108, and the third dopant is configured to increase endurance of the data storage structure108, thereby increasing a performance of the memory device200.

In various embodiments, between about 5 to 10 percent of a chemical composition of the data storage structure108is the first dopant (e.g., nitrogen, silicon, fluorine, etc.). It will be appreciated that the data storage structure108comprising other chemical composition percentages of the first dopant is also within the scope of the disclosure. In some embodiments, if the first dopant is a relatively small percent (e.g., less than about 5 percent) of the chemical composition of the data storage structure108, then the forming voltage of the memory cell104may not be reduced. In further embodiments, if the first dopant is a relatively large percent (e.g., greater than about 10 percent) of the chemical composition of the data storage structure108, then an endurance of the memory cell104may be reduced, thereby decreasing a number of set and/or reset operations that may be performed on the data storage structure108.

Further, in some embodiments, between about 12 to 18 percent of the chemical composition of the data storage structure108is the second dopant (e.g., tantalum, cerium, etc.). It will be appreciated that the data storage structure108comprising other chemical composition percentages of the second dopant is also within the scope of the disclosure. In some embodiments, if the second dopant is a relatively small percent (e.g., less than about 12 percent) of the chemical composition of the data storage structure108, then data retention of the memory cell104may not be increased. In further embodiments, if the second dopant is a relatively large percent (e.g., greater than about 18 percent) of the chemical composition of the data storage structure108, then a number of set and/or reset operations that may be performed on the data storage structure108is reduced.

In further embodiments, between about 15 to 22 percent of the chemical composition of the data storage structure108is the third dopant (e.g., hafnium, zirconium, etc.). It will be appreciated that the data storage structure108comprising other chemical composition percentages of the third dopant is also within the scope of the disclosure. In some embodiments, if the third dopant is a relatively small percent (e.g., less than about 15 percent) of the chemical composition of the data storage structure108, then the endurance of the memory cell104may not be increased. In further embodiments, if the third dopant is a relatively large percent (e.g., greater than about 22 percent) of the chemical composition of the data storage structure108, then the forming voltage of the data storage structure108may be increased.

Furthermore, in various embodiments, between about 7 to 15 percent of the chemical composition of the data storage structure108is aluminum. It will be appreciated that the data storage structure108comprising other chemical composition percentages of aluminum is also within the scope of the disclosure. In some embodiments, between about 38 to 48 percent of the chemical composition of the data storage structure108is oxygen. It will be appreciated that the data storage structure108comprising other chemical composition percentages of oxygen is also within the scope of the disclosure. In some embodiments, the data storage structure108comprises a first atomic percentage of the first dopant, a second atomic percentage of the second dopant, a third atomic percentage of the third dopant, a fourth atomic percentage of aluminum, and a fifth atomic percentage of oxygen. In further embodiments, the first atomic percentage is less than the second atomic percentage and the second atomic percentage is less than the third atomic percentage. In yet further embodiments, the first atomic percentage may be within a range of about 5 to 10 percent, the second atomic percentage may be within a range of about 12 to 18 percent, the third atomic percentage may be within a range of about 15 to 22 percent, the fourth atomic percentage may be within a range of about 7 to 15 percent, and/or the fifth atomic percentage may be within a range of about 38 to 48 percent. It will be appreciated that the first through fifth atomic percentages respectively comprising other values is within the scope of the disclosure. In various embodiments, a thickness of the data storage structure108is within a range of about 10 to 60 angstroms. It will be appreciated that the thickness of the data storage structure108having other values is within the scope of the disclosure. In further embodiments, if the thickness of the data storage structure108is relatively small (e.g., less than about 10 angstroms), then high current leakage may occur between the bottom electrode106and the capping layer110. In yet further embodiments, if the thickness of the data storage structure108is relatively large (e.g., greater than about 60 angstroms), then the forming voltage of the memory cell104may be increased. In various embodiments, the data storage structure108may, for example, consist of or consist essentially of a compound of the dielectric material, the first dopant, and the second dopant (e.g., AlTaON); a compound of the dielectric material, the first dopant, and the third dopant (e.g., AlHfON); a compound of the dielectric material, the first dopant, the second dopant, and the third dopant (e.g., AlTaHfON); or another suitable material.

In some embodiments the bottom and/or top electrode vias218,220may, for example, respectively be or comprise copper, aluminum, tungsten, another suitable conductive material, or any combination of the foregoing. In some embodiments, the capping layer110may, for example, be or comprise tantalum, titanium, tantalum nitride, titanium nitride, any combination of the foregoing, or the like. In further embodiments, the bottom and/or top electrodes106,112may, for example, respectively be or comprise titanium nitride, tantalum nitride, tantalum, titanium, platinum, nickel, hafnium, zirconium, ruthenium, iridium, another conductive material, or any combination of the foregoing. Thus, in some embodiments, the capping layer110may comprise the first dopant (e.g., nitrogen) and/or the second dopant (e.g., tantalum). In further embodiments, the top and bottom electrodes106,112may respectively comprise the first dopant (e.g., nitrogen), the second dopant (e.g., tantalum), and/or the third dopant (e.g., hafnium).

FIGS.3-5illustrate cross-sectional views of some embodiments of different states of the memory cell104ofFIGS.1and/or2during operation of the memory cell104. In some embodiments,FIG.3illustrates a first state300, in which the memory cell104is in a low resistance state (e.g., storing a logical “1”). In further embodiments,FIG.4illustrates a second state400, in which the memory cell104is in a high resistance state (e.g., storing a logical “0”). In yet further embodiments,FIG.5illustrates a third state500, in which the memory cell104is in a low resistance state (e.g., storing a logical “1”).

AlthoughFIGS.3-5describe a memory cell as having a conductive path formed of oxygen vacancies, it will be appreciated that the disclosed data storage structure is not limited to a memory cell having such paths. For example, in some embodiments, the data storage structure may be used in memory devices having a conductive path that is formed of conductive ions and oxygen vacancies or formed of conductive ions and not oxygen vacancies.

FIG.3illustrates one embodiment of the first state300of the memory cell104, in which a forming operation was performed on the memory cell104. The memory cell104includes the data storage structure108, the bottom electrode106, the top electrode112, and the capping layer110(e.g., as illustrated and described inFIGS.1and/or2). In some embodiments, the capping layer110may include a metal layer110a(e.g., comprising a metal material such as tantalum, tantalum nitride, titanium, titanium nitride, or the like) overlying a metal oxide layer110b(e.g., comprising an oxide of the metal material). In some embodiments, during the forming operation, a forming voltage is applied across the bottom and top electrode106,112. In such embodiments, the forming voltage is configured to knock oxygen atoms out of a lattice of the data storage structure108, and the metal oxide layer110bis configured to receive the oxygen atoms, thereby forming oxygen vacancies226in the data storage structure108. The oxygen vacancies226tend to align within a region114of the data storage structure108to form a conductive path228(e.g., an initial conductive path) which extends through the data storage structure108. In some embodiments, the oxygen vacancies226are offset from a peripheral region126pof the data storage structure108, where the peripheral region126platerally encloses the region114. Thus, after the forming operation, the memory cell104is in a low resistance state (e.g., storing a logical “1”). In some embodiments, by virtue of the data storage structure108comprising the first dopant (e.g., nitrogen), the forming voltage may be reduced and/or eliminated. For example, in some embodiments, the forming voltage may be approximately equal to a set voltage (e.g., seeFIG.5) of the memory cell104, such that the formation process is eliminated and a set operation is performed on the memory cell104to achieve the first state300. This in turn facilitates shrinking feature sizes of the memory cell104while mitigating damage to the memory cell104.

FIG.4illustrates one embodiment of the second state400of the memory cell104, in which a reset operation was performed on the memory cell104. In some embodiments, during the reset operation, a reset voltage is applied across the bottom and top electrodes106,112. In such embodiments, the reset voltage is configured to knock oxygen atoms from the metal oxide layer110bto a middle region404of the data storage structure108, thereby dissolving at least a portion of the conductive path (228ofFIG.3) such that the memory cell104is in a high resistance state (e.g., storing a logical “0”). In further embodiments, the data storage structure108comprises a lower region402, an upper region406, and the middle region404disposed vertically between the lower and upper regions402,406. In various embodiments, after performing the reset operation, oxygen vacancies226may remain in the lower and upper regions402,406, and at least a majority of the oxygen vacancies226may be removed from the middle region404. By virtue of the data storage structure108comprising the first dopant (e.g., nitrogen), the second dopant (e.g., tantalum), and/or the third dopant (e.g., hafnium), a height h1of the middle region404may be reduced, thereby reducing the set and/or reset voltages and increasing a switching efficiency of the memory cell104. In further embodiments, the third dopant (e.g., hafnium) is configured to reduce current leakage paths in the data storage structure108while in the high resistance state, thereby increasing discrete data states and an endurance of the memory cell104. For example, the third dopant can increase an energy level of the oxygen vacancies within the data storage structure108such that oxygen atoms may more easily recombine in the data storage structure108during the reset operation, thereby decreasing current leakage paths in the memory cell104while in the high resistance state.

FIG.5illustrates one embodiments of the third state500of the memory cell104, in which a set operation was performed on the memory cell104. In some embodiments, during the set operation, a set voltage is applied across the bottom and top electrodes106,112. In further embodiments, the set voltage is configured to knock oxygen atoms from the middle region404of the data storage structure108to the metal oxide layer110b, thereby forming the conductive path228in the region114of the data storage structure. Thus, the memory cell104is in the low resistance state (e.g., storing a logical “1”). By virtue of the data storage structure108comprising the first dopant, second dopant, and/or third dopant, data retention and the switching efficiency of the memory cell104may be improved.

In some embodiments, by virtue of the data storage structure108comprising the first dopant (e.g., nitrogen) and the second dopant (e.g., tantalum), an energy used to complete the forming operation ofFIG.3is significantly reduced such that the forming voltage is substantially equal to the set voltage. In such embodiments, the forming operation may be omitted and the set operation may be performed in place of the forming operation. In yet further embodiments, the forming voltage may be within a range of about 0 to 25 percent greater than the set voltage. In some embodiments, if the set voltage is about 2 volts (V), then the forming voltage is less than about 2.5 V. In some embodiments, the first dopant (e.g., nitrogen) may, for example, decrease energy required to form the oxygen vacancies226within the data storage structure108, thereby increasing an ability to form localized oxygen vacancies within the region114. In further embodiments, by virtue of the data storage structure108comprising the second dopant (e.g., tantalum), data retention of the memory cell104may be improved. In such embodiments, the second dopant has a strong bond with oxygen atoms within the data storage structure108, such that the strong bond may not be broken by high heat (e.g., greater than about 250 degrees Celsius) applied to the memory cell104during formation and/or operation of the memory cell104. In some embodiments, the strong bond between the second dopant and the oxygen atoms may be greater than about 600 kilojoules per mole (kJ/mol). For example, if the second dopant is tantalum, then the strong bond between tantalum and oxygen may be within a range of about 800 to 845 kJ/mol. In further embodiments, the strong bond between the second dopant (e.g., tantalum) and oxygen is greater than a bond between the first dopant (e.g., nitrogen) and oxygen, and the bond between the first dopant and oxygen is greater than a bond between aluminum and oxygen. In some embodiments, the strong bond between the second dopant and oxygen is greater than a bond between the third dopant (e.g., hafnium) and oxygen. For example, the bond between the third dopant and oxygen may be within a range of about 550 to 700 kJ/mol. Thus, because the data storage structure108is multi-doped with the first, second, and third dopants, the forming voltage of the memory cell104may be improved (e.g., reduced or eliminated) while maintaining good data retention of the memory cell104and increasing a switching performance of the memory cell104.

FIG.6illustrates a cross-sectional view of some embodiments of a memory device600that corresponds to some alternative embodiments of the memory device200ofFIG.2, where the data storage structure108comprises a data storage layer604overlying a multi-doped data storage layer602. Further, the conductive path (e.g., the conductive path228ofFIG.2) may be selectively produced or dissolved within the region114, where the region114continuously extends across the multi-doped data storage layer602and the data storage layer604. In some embodiments, the data storage layer604may, for example, be or comprise undoped hafnium oxide, undoped tantalum oxide, another dielectric material, or any combination of the foregoing. In yet further embodiments, the multi-doped data storage layer602comprises a dielectric material (e.g., aluminum oxide (AlOx)) multi-doped with multiple dopants. For example, the multiple dopants may include a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and a third dopant (e.g., hafnium). In various embodiments, the multi-doped data storage layer602may, for example, be or comprise a compound of the dielectric material, the first dopant, and the second dopant (e.g., AlTaON); a compound of the dielectric material, the first dopant, and the third dopant (e.g., AlHfON); a compound of the dielectric material, the first dopant, the second dopant, and the third dopant (e.g., AlTaHfON); or another suitable material. Thus, in some embodiments, the multi-doped data storage layer602may comprise a same chemical composition and/or multi-doped material as described in relation to the data storage structure108ofFIGS.1and/or2. In yet further embodiments, the data storage layer604may, for example, be or comprise undoped hafnium oxide, undoped tantalum oxide, another dielectric material, or any combination of the foregoing. In some embodiments, the data storage layer604may be devoid of the first dopant (e.g., nitrogen).

FIG.7illustrates a cross-sectional view of some embodiments of a memory device700that corresponds to some alternative embodiments of the memory device200ofFIG.2, where the data storage structure108comprises a first data storage layer702, a second data storage layer704, and a third data storage layer706. In some embodiments, the first data storage layer702comprises a first dielectric material (e.g., aluminum oxide) doped with the first dopant (e.g., nitrogen), the second data storage layer704comprises a second dielectric material (e.g., hafnium oxide) doped with the first dopant, and/or the third data storage layer706comprises a third dielectric material (e.g., tantalum oxide) doped with the first dopant. In further embodiments, the first, second, and third dielectric materials each comprise a high-κ dielectric material (e.g., aluminum oxide, hafnium oxide, tantalum oxide, etc.) different from one another.

FIG.8illustrates a cross-sectional view of some embodiments of an integrated chip800having a memory cell104disposed within an interconnect structure812that overlies a substrate202. In some embodiments, the memory cell104ofFIG.8is configured as the memory cell104ofFIG.1,2,6, or7. It will be appreciated that, in some embodiments, the integrated chip800may comprise a plurality of the memory cells104disposed in a memory array.

The integrated chip800includes a semiconductor device806disposed on the substrate202. In some embodiments, the semiconductor device806may be a metal-oxide semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BTJ), a high-electric-mobility transistor (HEMT), or any other front-end-of-line semiconductor device. In further embodiments, the semiconductor device806may comprise a gate dielectric layer808, a gate electrode810overlying the gate dielectric layer808, and a pair of source/drain regions804a-b. An isolation structure802is disposed within the substrate202and is configured to electrically isolate the semiconductor device806from other devices (not shown) disposed within and/or on the substrate202.

An interconnect structure812is disposed over the substrate202and the semiconductor device806. In some embodiments, the interconnect structure812comprises an interconnect dielectric structure816, a plurality of conductive contacts814, a plurality of conductive lines818(e.g., metal lines), and a plurality of conductive vias820(e.g., metal vias). The plurality of conductive contacts814, the plurality of conductive lines818, and the plurality of conductive vias820are electrically coupled in a predefined manner and configured to provide electrical connections between various devices disposed throughout the integrated chip800. In further embodiments, the plurality of conductive contacts814, the plurality of conductive lines818, and/or the plurality of conductive vias820may, for example, respectively be or comprise titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, another conductive material, or any combination of the foregoing. In yet further embodiments, the interconnect dielectric structure816may comprises one or more ILD layers, which may respectively comprise a low-κ dielectric material, an oxide (e.g., silicon dioxide), another dielectric material, or any combination of the foregoing. In further embodiments, the memory cell104is disposed in an upper region of the interconnect structure812, such that the memory cell104is vertically above the plurality of conductive contacts814and/or vertically above one or more layers of the conductive lines818and the conductive vias820. The memory cell104comprises the bottom electrode106, the data storage structure108that is multi-doped with multiple dopants, the capping layer110, and the top electrode112.

A first one of the plurality of conductive lines818is denoted as818wland may be referred to as a word line. In some embodiments, the word line818wlmay be electrically coupled to the gate electrode810of the semiconductor device806via the interconnect structure812. A second one of the plurality of conductive lines818is denoted as818sland may be referred to as a source line. In further embodiments, the source line818slmay be electrically coupled to a first source/drain region804aof the semiconductor device806via the interconnect structure812. A third one of the plurality of conductive lines818is denoted as818bland may be referred to as a bit line. In yet further embodiments, the bit line818blmay be electrically coupled to the top electrode112of the memory cell104and the bottom electrode106may be electrically coupled to a second source/drain region804bof the semiconductor device806via the interconnect structure812.

In some embodiments, the memory cell104is electrically coupled to a second source/drain region804bof the semiconductor device806via the interconnect structure812. Thus, in some embodiments, application of a suitable word line voltage to the word line818wlmay electrically couple the memory cell104between the bit line818bland the source line818sl. Consequently, by providing suitable bias conditions, the memory cell104can be switched between two data states.

FIG.9illustrates a cross-sectional view of some embodiments of an integrated chip800having a device gate stack902overlying a substrate202. In some embodiments, the device gate stack902comprises the memory cell104, such that the memory cell104ofFIG.9may be referred to as a front-end-of-line resistive memory cell.

The device gate stack902is disposed over the substrate202and is spaced laterally between the pair of source/drain regions804a-b. In some embodiments, the device gate stack902includes a gate dielectric layer808, a gate electrode810, the data storage structure108, and the top electrode112. Thus, in various embodiments, the device gate stack902may include the memory cell104directly overlying the gate electrode810. In some embodiments, the gate electrode810may be referred to as a bottom electrode. In some embodiments, the memory cell104comprises the top electrode112and the data storage structure108, where the data storage structure108comprises the multi-doped data storage layer602and the data storage layer604. In yet further embodiments, the memory cell104ofFIG.9is configured as the memory cell104ofFIG.1,2,6, or7. In yet further embodiments, the capping layer (110ofFIG.1) is disposed between the top electrode112and the data storage structure108(not shown). In some embodiments, the word line818wlmay be electrically coupled to the data storage structure108via the interconnect structure812. Thus, by providing suitable bias conditions to the word line818wl, the bit line818bl, and/or the source line818sl, the data storage structure108can be switched between two data states.

In some embodiments, the gate dielectric layer808may, for example, be or comprise a high-κ dielectric material, an oxide (e.g., silicon dioxide), another dielectric material, or any combination of the foregoing and/or may have a thickness within a range of about 1,000 to 1,100 angstroms, or another suitable thickness value. In further embodiments, the gate electrode810may, for example, be or comprise ruthenium, aluminum, titanium nitride, tantalum nitride, another conductive material, or any combination of the foregoing and/or may have a thickness within a range of about 150 to 250 angstroms, or another suitable thickness value. In yet further embodiments, the multi-doped data storage layer602may, for example, be or comprise a dielectric material (e.g., aluminum oxide) multi-doped with the first dopant (e.g., nitrogen), the second dopant (e.g., tantalum), and the third dopant (e.g., hafnium) and/or may have a thickness of about 13 angstroms, a thickness within a range of about 10 to 15 angstroms, or another suitable thickness value. In various embodiments, the data storage layer604may, for example, be or comprise hafnium oxide, tantalum oxide, hafnium and tantalum oxide, another high-κ dielectric material, or any combination of the foregoing and/or may have a thickness of about 30 angstroms, a thickness within a range of about 20 to 40 angstroms, or another suitable thickness value. In some embodiments, the multi-doped data storage layer602may comprise Al0.10Ta0.17Hf0.20O0.46N0.06, such that an atomic percentage of aluminum is about 10%, an atomic percentage of oxygen is about 46%, an atomic percentage of the first dopant (e.g., nitrogen) is about 6%, an atomic percentage of the second dopant (e.g., tantalum) is about 17%, and an atomic percentage of the third dopant (e.g., hafnium) is about 20%. It will be appreciated that the multi-doped data storage layer602comprising other atomic percentages of the aforementioned elements and/or dopants is also within the scope of the disclosure.

The isolation structure802may be configured as a shallow trench isolation (STI) structure or another suitable isolation structure. In further embodiments, the isolation structure802may, for example, be or comprise silicon dioxide, silicon nitride, silicon carbide, another dielectric material, or any combination of the foregoing. In some embodiments, the substrate202comprises a first doping type (e.g., p-type) and the pair of source/drain regions804a-bcomprise a second doping type (e.g., n-type) that is opposite the first doping type.

FIGS.10-14illustrate cross-sectional views1000-1400of some embodiments of a method for forming a memory cell having a data storage structure that is multi-doped with a first dopant, a second dopant, and/or a third dopant according to the present disclosure. Although the cross-sectional views1000-1400shown inFIGS.10-14are described with reference to a method, it will be appreciated that the structures shown inFIGS.10-14are not limited to the method but rather may stand alone separate of the method. AlthoughFIGS.10-14are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

As shown in cross-sectional view1000ofFIG.10, a lower inter-level dielectric (ILD) layer1002is formed over a substrate202, and a lower interconnect wire214is formed within the lower ILD layer1002. In some embodiments, the lower ILD layer1002may, for example, be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition or growth process. In further embodiments, the lower interconnect wire214may be formed by a single damascene process, a dual damascene process, or another suitable formation process. In some embodiments, the substrate202may, for example, be or comprise a semiconductor body such as monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), a silicon-on-insulator (SOI), or another suitable semiconductor substrate material and/or the substrate202may comprise a first doping type (e.g., p-type). In various embodiments, the lower interconnect wire214may, for example, be or comprise aluminum, copper, ruthenium, titanium nitride, tantalum nitride, another conductive material, or any combination of the foregoing. In some embodiments, the lower ILD layer1002may, for example, be or comprise a low-κ dielectric material, an oxide (e.g., silicon dioxide), another suitable dielectric material, or any combination of the foregoing.

As shown in cross-sectional view1100ofFIG.11, a bottom electrode106is formed over the lower interconnect wire214and a data storage structure108is formed over the bottom electrode106. In some embodiments, the bottom electrode106and/or the data storage structure108may respectively be formed by, for example, CVD, PVD, ALD, sputtering, co-sputtering, electroless plating, electroplating, or another suitable growth or deposition process.

In some embodiments, the data storage structure108is formed in such a manner that the data storage structure108comprises a dielectric material (e.g., aluminum oxide (e.g., Al2O3)) multi-doped with a first dopant (e.g., nitrogen), a second dopant (e.g., tantalum), and/or a third dopant (e.g., hafnium). In some embodiments, the dielectric material may, for example, be or comprise a high-κ dielectric material, aluminum oxide (e.g., Al2O3), tantalum oxide, hafnium oxide, another suitable dielectric material, or any combination of the foregoing. In some embodiments, the first dopant may, for example, be or comprise nitrogen, silicon, fluorine, or the like. In further embodiments, the second dopant may, for example, be or comprise tantalum, cerium, or the like. In yet further embodiments, the third dopant may, for example, be or comprise hafnium, zirconium, or the like. Further, the data storage structure108may, for example, be formed such that the data storage structure108comprises a first atomic percentage of the first dopant, a second atomic percentage of the second dopant, a third atomic percentage of the third dopant, a fourth atomic percentage of aluminum, and a fifth atomic percentage of oxygen. In yet further embodiments, the first atomic percentage may be within a range of about 5 to 10 percent, the second atomic percentage may be within a range of about 12 to 18 percent, the third atomic percentage may be within a range of about 15 to 22 percent, the fourth atomic percentage may be within a range of about 7 to 15 percent, and/or the fifth atomic percentage may be within a range of about 38 to 48 percent.

Furthermore, a process for forming the data storage structure108may include depositing a compound (e.g., the compound comprises the dielectric material (e.g., aluminum oxide), the second dopant (e.g., tantalum), and the third dopant (e.g., hafnium)) by a deposition process (e.g., CVD, PVD, ALD, sputtering, co-sputtering, etc.)) while concurrently exposing the compound to the first dopant (e.g., nitrogen) such that the data storage structure108comprises a multi-doped dielectric material (e.g., aluminum oxide multi-doped with the first, second, and third dopants). In yet further embodiments, the data storage structure108may be formed in a processing chamber where the processing chamber is heated to a temperature of about 250 to 300 degrees Celsius during formation of the data storage structure108. In yet further embodiments, the data storage structure108is formed to a thickness within a range of about 10 to 60 angstroms. In various embodiments, the data storage structure108may, for example, be formed such that it comprises a compound of the dielectric material, the first dopant, and the second dopant (e.g., AlTaON); a compound of the dielectric material, the first dopant, and the third dopant (e.g., AlHfON); a compound of the dielectric material, the first dopant, the second dopant, and the third dopant (e.g., AlTaHfON); or another suitable material.

In addition, another process for forming the data storage structure108may include performing a co-sputter process to deposit a compound comprising aluminum oxide, the second dopant, and the third dopant in a plasma environment (e.g., co-sputtering aluminum oxide, tantalum oxide, and hafnium oxide), where the plasma comprises, for example, nitrogen (e.g., N2). In further embodiments, a process for forming the data storage structure108may include performing a CVD process or an ALD process to deposit a compound (e.g., the compound comprises aluminum oxide, tantalum oxide, and hafnium oxide) in a plasma environment, where the plasma comprises N2or NH3. In yet further embodiments, a process for forming the data storage structure108may include performing a CVD process or an ALD process to form a material (e.g., aluminum oxide) in a chamber using a first precursor, a second precursor, and/or a third precursor, in which the first precursor ensures the material is doped with the first dopant, the second precursor ensure the material is doped with the second dopant, and the third precursor ensure the material is doped with the third dopant. In some embodiments, the first precursor may, for example, be or comprise (NH4)OH or another suitable precursor. In further embodiments, the second precursor may, for example, be or comprise TaCl5, Ta(OC2H5)5, or another suitable precursor. In yet further embodiments, the third precursor may, for example, be or comprise HfCl4or another suitable precursor.

As illustrated in cross-sectional view1200ofFIG.12, a capping layer110is formed over the data storage structure108and a top electrode112is formed over the capping layer110, thereby forming a memory cell layer stack1202over the lower interconnect wire214. In some embodiments, the memory cell layer stack1202comprises the bottom electrode106, the data storage structure108, the capping layer110, and the top electrode112. In further embodiments, the capping layer110and/or the top electrode112may respectively be formed by, for example, CVD, PVD, ALD, sputtering, electroless plating, electro plating, or another suitable deposition or growth process. Subsequently, a masking layer1204is formed over the memory cell layer stack1202. In some embodiments, the masking layer1204covers a middle region of the memory cell layer stack1202and leaves a peripheral region of the memory cell layer stack1202exposed.

As illustrated in cross-sectional view1300ofFIG.13, a patterning process is performed on the memory cell layer stack (1202ofFIG.12) according to the masking layer (1204ofFIG.12), thereby forming a memory cell104. In some embodiments, the pattering process may include: exposing unmasked regions of the memory cell layer stack (1202ofFIG.12) to one or more etchants; and performing a removal process (not shown) to remove the masking layer (1204ofFIG.12).

As illustrated in cross-sectional view1400ofFIG.14, an upper ILD layer1402is formed over and around the memory cell104, an upper interconnect via222is formed over the memory cell104, and an upper interconnect wire224is formed over the upper interconnect via222. In some embodiments, the upper ILD layer1402may, for example, be formed by PVD, CVD, ALD, or another suitable deposition or growth process. In further embodiments, the upper interconnect via and/or wire222,224may, for example, respectively be formed by a single damascene process, a dual damascene process, or another suitable formation process. In some embodiments, the upper ILD layer1402may, for example, be or comprise a low-κ dielectric material, an oxide (e.g., silicon dioxide), another suitable dielectric material, or any combination of the foregoing. In various embodiments, the upper interconnect via and wire222,224may, for example, respectively be or comprise aluminum, copper, ruthenium, titanium nitride, tantalum nitride, another conductive material, or any combination of the foregoing.

FIG.15illustrates a method1500for forming a memory cell having a data storage structure that is multi-doped with a first dopant, a second dopant, and/or a third dopant according to the present disclosure. Although the method1500is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At act1502, a lower conductive wire is formed over a substrate.FIG.10illustrates a cross-sectional view1000corresponding to some embodiments of act1502.

At act1504, a bottom electrode is formed over the lower conductive wire.FIG.11illustrates a cross-sectional view1100corresponding to some embodiments of act1504.

At act1506, a data storage structure is formed over the bottom electrode, where the data storage structure comprises a multi-doped dielectric material that comprises a first dopant, a second dopant, and/or a third dopant.FIG.11illustrates a cross-sectional view1100corresponding to some embodiments of act1506.

At act1508, a capping layer is formed over the data storage structure and a top electrode is formed over the capping layer.FIG.12illustrates a cross-sectional view1200corresponding to some embodiments of act1508.

At act1510, the top electrode, the capping layer, the data storage structure, and the bottom electrode are patterned, thereby forming a memory cell.FIG.13illustrates a cross-sectional view1300corresponding to some embodiments of act1510.

At act1512, an upper conductive via and an upper conductive wire are formed over the memory cell.FIG.14illustrates a cross-sectional view1400corresponding to some embodiments of act1512.

FIG.16illustrates a method1600for forming an integrated chip comprising a front-end-of-line resistive memory cell having a data storage structure that is multi-doped with a first dopant, a second dopant, and/or a third dopant according to the present disclosure. Although the method1600is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At act1602, an isolation structure is formed in a substrate.

In some embodiments, the isolation structure may be substantially similar to the isolation structure802ofFIG.9. In further embodiments, a process for forming the isolation structure may include: patterning the substrate202ofFIG.9to define an isolation structure opening in the substrate202; depositing (e.g., by PVD, CVD, ALD, etc.) a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide, or the like) in the isolation structure opening; and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) into the dielectric material, thereby defining the isolation structure.

At act1604, a gate dielectric layer is formed over the substrate and a gate electrode is formed over the gate dielectric layer.

In some embodiments, the gate dielectric layer may be substantially similar to the gate dielectric layer808ofFIG.9and the gate electrode may be substantially similar to the gate electrode810ofFIG.9. In further embodiments, the gate dielectric layer and the gate electrode may respectively be deposited by CVD, PVD, ALD, electro plating, electroless plating, or another suitable deposition or growth process.

At act1606, a data storage structure is formed over the gate electrode, where the data storage structure comprises a multi-doped dielectric material that comprises a first dopant, a second dopant, and/or a third dopant.

In some embodiments, the data storage structure may be substantially similar to the data storage structure108ofFIG.9, where the data storage structure comprises the multi-doped data storage layer602and the data storage layer604. In further embodiments, a process for forming the data storage structure may include depositing the multi-doped data storage layer over the gate electrode, and depositing the data storage layer over the multi-doped data storage layer. In some embodiments, the multi-doped data storage layer may be formed over the gate electrode by process(es) substantially similar to process(es) described above regarding formation of the data storage structure108ofFIG.11. In further embodiments, the data storage layer may be formed over the multi-doped data storage layer by, for example, CVD, PVD, ALD, co-sputtering, or another suitable deposition or growth process.

At act1608, a capping layer is formed over the data storage structure, and a top electrode is formed over the capping layer. In some embodiments, the capping layer and the top electrode may be formed over the data storage structure by process(es) substantially similar to process(es) described above regarding formation of the capping layer110and the top electrode112ofFIG.12.

At act1610, the top electrode, the capping layer, the data storage structure, the gate electrode, and the gate dielectric layer are patterned, thereby forming a device gate stack over the substrate.

In some embodiments, the device gate stack may be substantially similar to the device gate stack902ofFIG.9. In further embodiments, the device gate stack may be patterned by process(es) substantially to process(es) described above regarding the patterning process ofFIG.13.

At act1612, a pair of source/drain regions are formed in the substrate on opposite sides of the gate dielectric layer.

In some embodiments, the pair of source/drain regions may be substantially similar to the pair of source/drain regions804a-bofFIG.9. In further embodiments, a process for forming the pair of source/drain regions may include selectively doping the substrate with a second doping type (e.g., n-type).

At act1614, an interconnect structure is formed over the substrate.

In some embodiments, the interconnect structure may be substantially similar to the interconnect structure812ofFIG.9. In such embodiments, the interconnect dielectric structure816may be formed by one or more deposition process(es) (e.g., CVD, PVD, ALD, etc.), and the conductive contacts814, the conductive lines818, and/or the conductive vias820may respectively be formed by a single damascene process, a dual damascene process, or another suitable formation process.

Accordingly, in some embodiments, the present disclosure relates to a memory cell comprising a top electrode, a bottom electrode, and a data storage structure disposed between the top and bottom electrodes, where the data storage structure comprises a dielectric material multi-doped with a first dopant, a second dopant, and/or a third dopant.

In some embodiments, the present application provides a memory device including a substrate; a bottom electrode overlying the substrate; a top electrode overlying the bottom electrode; and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure comprises a dielectric material doped with a first dopant and a second dopant, wherein the first dopant is different from the second dopant.

In some embodiments, the present application provides an integrated chip including a substrate; and a resistive random access memory (RRAM) cell overlying the substrate, wherein the RRAM cell includes a top electrode, a bottom electrode, and a data storage structure disposed between the top and bottom electrodes, wherein the data storage structure comprises a first high-κ dielectric material and a plurality of dopants, wherein the plurality of dopants comprises a first dopant, a second dopant, and a third dopant that are respectively different from one another.

In some embodiments, the present application provides a method for forming a memory device, the method including: depositing a bottom electrode over a substrate; depositing a data storage structure over the bottom electrode such that the data storage structure comprises a dielectric material doped with a first dopant, a second dopant, and a third dopant; depositing a top electrode over the data storage structure; and performing a patterning process on the bottom electrode, the data storage structure, and the top electrode, thereby forming a memory cell over the substrate.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.