Patent ID: 12237457

Use of the same reference numbers in different figures indicates similar or identical elements.

While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure covers all modifications, equivalents, and alternatives falling within the spirit of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives and equivalents, as will be appreciated by those of skill in the art.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

As used in the specification and claims, the singular forms “a”, “an” and “the” include plural references unless the context clearly dictates otherwise.

The term “comprising” as used herein will be understood to mean that the list following is non-exhaustive and may or may not include any other additional suitable items, for example one or more further feature(s), component(s) and/or element(s) as appropriate.

The terms “device” and “micro device” and “optoelectronic device” are used herein interchangeably. It would be clear to one skilled in the art that the embodiments described here are independent of the device size.

The terms “donor substrate” and “temporal substrate” are used herein interchangeably. However, it is clear to one skilled in the art that the embodiments described herein are independent of the substrate.

The terms “system substrate” and “receiver substrate” are used herein interchangeably. However, it is clear to one skilled in the art that the embodiments described here are independent of substrate type.

The present disclosure relates to methods for lateral conduction manipulation of vertical solid state devices, particularly optoelectronic devices. More specifically, the present disclosure relates to micro or nano-optoelectronic devices in which device performance is being affected by size reduction. Also, described is a method to create an array of vertical devices by modifying the lateral conduction without isolating the active layers. Also, disclosed is an array of LEDs using vertical conductivity engineering to enable current transport in a horizontal direction and control to the pixel area, so there is no need to pattern the LEDs.

Herein also is described a method of LED structure modification to simplify the integration of monolithic LED devices with backplane circuitry in an LED display while preserving device efficiency and uniformity. The present methods and resulting structures increase the number of LED devices fabricated within a limited wafer area and may result in lower fabrication cost, decrease the number of fabrication steps, and provide higher resolution and brightness for LED displays. LED devices in a substrate may be bonded to an electronic backplane, which drives the devices or pixels in a passive or active manner. Although the following methods are explained with one type of LED device, they can be easily used with other LED and non-LED vertical devices, such as sensors. LED devices in a substrate as herein described may be bonded to an electronic backplane which drives these devices (i.e., pixels) in a passive or active manner.

Also described herein is a method to improve the performance of an optoelectronic device by manipulating the internal electrical field of the device. In particular, limiting the lateral current flow of vertical solid-state devices may improve the performance of the devices. In particular, diverging current from the perimeter of a vertical device may be accomplished by modifying the lateral conduction. The resistance of the conductive layers may be modified by oxidation, and the lateral resistance of the conductive layers may be modified by modifying the bias condition. A contact can also be used as a mask to modify the lateral resistance of the conductive layer. The present devices may also have conductive layers on the sides and functional layers in the middle.

Also provided is a method of pixelating a display device by defining the pixel pad connection in a backplane and attaching the LED device with vertical conduction modulation to the backplane. In one embodiment, the current spreader may be removed, or its thickness may be reduced to modulate the vertical conduction. In another embodiment, some of the micro device layers may be etched to create vertical conduction modulation. A bonding element may be used to hold the device to the backplane. Structures and methods are described to define micro devices on a device layer by forming contact pads on the device layer before transferring the device layer to a receiver substrate. Also described are structures and methods to define the micro devices by contact pads or bumps on the receiver substrate in an integrated micro device array system comprising a transferred monolithic array of micro devices and a system substrate.

Also described are methods to manipulate the top conductive layer of a vertical device in which the functionality of the device predominantly is defined by the vertical currents. In one embodiment the method comprises: top layer resistance engineering in which the lateral resistance of the top layer may be manipulated by changing the thickness or specific resistivity of the top layer; full or partial etching modulation in which the top layer of the vertical device may be modulated by any means of etching; and material conductivity modulation in which the resistance of the top layer may be modulated by various methods including but not limited to etching, counter doping, and laser ablation. The contact pads on the top device layer may define the size of the individual micro devices. After transferring micro devices, a common electrode may be deposited on the transferred monolithic array of micro devices to improve the conductivity. The common electrodes may be formed through vias in the top buffer or dielectric layers transferred or deposited on the monolithic array of micro devices. Also, the top layer of the transferred monolithic array of micro devices may be modulated by any removal means. In this case, optical elements may be formed in the removed regions of the modulated top layer.

Also described is a method to form an array of micro devices on an integrated structure in which the device layer, prepared according to the aforementioned methods, is transferred to a receiving substrate wherein the contact pads on the top of the receiving substrate may be bonded to the device layer and the size of the individual micro devices may be defined partially by the size of the contact pads or bumps on the receiver substrate. Spacers or banks may be formed around contact pads or bumps to fully define the size of the micro devices. The spacers or banks around contact pads or bumps may be adhesives to promote bonding the device layer to the receiver substrate. The top layer of the integrated micro device array may be modulated by any means of removing. In one embodiment, the optical elements may be formed in the removed regions of the modulated top layer.

In an embodiment, the at least one MIS structure may be formed with one of the device faces as the semiconductor layer. The structure may be used to manipulate the device's internal electrical field to control the charge transition and accumulation. The MIS structure may be formed prior to moving the device into the system substrate, or after the device is formed into the system substrate. The electrode in the MIS structure may be transparent to let the light pass through, or the electrode may be reflective or opaque to control the direction of the light. Preferably, the device output comprises visible light to create an array of pixels in a display. The electrode in the MIS structure may be shared with one of the device's functional electrodes. The electrode in the MIS structure may also have a separate bias point. The input or output of the micro devices may be any form of electromagnetic wave. Non-limiting examples of the device are an LED and a sensor. Structures and methods to improve micro optoelectronic devices are also described herein. The device performance may be improved by manipulating the internal electric field. In one case, the MIS structure is used to modulate the internal electrical field.

In micro device system integration, devices may be fabricated in their native ambient conditions, and may be then transferred to a system substrate. To pack more micro devices in a system substrate or reduce the cost of material, the size of micro devices may be as small as possible. In one example, the micro devices may be 25 μm or smaller and in another example 5 μm or smaller. As the original devices and layers on the donor substrate are being patterned to a smaller area, the leakage and other effects increase which reduces the performance of the devices. Although passivation may improve the performance to some extent, it cannot address other issues such as non-radiative recombination.

Another embodiment is an optoelectronic micro device where it consists of first and second conductive layers, active layers between said first and second conductive layers, contacts to the first and second conductive layers on the same surface, metal-insulator-semiconductor formed between at least one of conductive or active layers and a gate electrode and a dielectric layer to separate the contact to the said gate electrode and one of the conductive layer.

Various embodiments in accordance with the present structures and processes provided are described below in detail.

Vertical Devices with Metal-insulator-Semiconductor (MIS) Structures

Described is the use of an MIS structure to modulate the internal electric field of a vertical device to reduce the unwanted effects caused by size reduction. In one embodiment, the structure is fully formed on the devices in the donor or temporal substrate and then moved to the system substrate. In another case, the MIS structure is formed on the devices integrated on the receiver or system substrate. In another case, the MIS structure is formed partially on the devices prior to being integrated into the receiver substrate, and the MIS structure is completed after transferring the device into the receiver substrate.

The system substrate may be any substrate and may be rigid or flexible. The system substrate may be made of glass, silicon, plastics, or any other commonly used material. The system substrate may also have active electronic components, such as but not limited to transistors, resistors, capacitors, or any other electronic component commonly used in a system substrate. In some cases, the system substrate may be a substrate with electrical signal rows and columns. In one example, the device substrate may be a sapphire substrate with LED layers grown monolithically thereon, and the system substrate may be a backplane with circuitry to derive micro-LED devices. As part of the vertical devices, MIS structures may be formed from a layer of metal, a layer of insulating material, and a layer of semiconductor material.

With reference toFIG.1A, a micro device100includes two functional contacts A102and B104. Biasing the micro device100causes a current106to flow through the bulk of the micro device100. For light emitting devices, the charges recombine in light emitting layer(s) and create photons. For sensing devices, the external stimulation (e.g., light, chemical, Tera Hz, X-ray) modulates the current. However, non-idealities may affect the efficiency of the micro device100in both cases. One example is the leakage current108mainly caused by the defects in the sidewalls. Other non-idealities may be non-radiative recombination, such as auger recombination, charge crowding, or charge imbalance. These issues become more dominant as the size of the device is reduced.

With reference toFIG.1B, the micro device100further includes an MIS structure110to modulate the internal field and reduce some of the aforementioned issues. At least one MIS structure110is formed on one of the faces of the micro device100. The MIS structure110is biased through an electrode112. If the MIS structure110is formed on more than one surface of the micro device100, it can be a continuous structure or a few separate MIS structures. The electrodes112can be connected to the same biases for all faces or different biases. The MIS structure can be on different sides of the device to improve performance or offer different functionality.

FIG.1B-1shows another exemplary structure with different MIS structure possibilities. The MIS structure110on the same side as the device electrodes (102,104) can control the flow of the current from the electrodes (102,104) to the edge sides, while other MIS structures on the sides with no device electrode can confine the charges and also control the flow of the current. A device may use one or more of these MIS structures110. At least two of the MIS structures110on different sides of the device may have the same electrode.

In an exemplary embodiment illustrated inFIG.1C, the MIS structure110surrounds the micro device100in one continuous form on or around a plurality of faces of the micro device100. Applying bias to the MIS structure110may reduce the leakage current108and/or avoid band bending under high current density to avoid non-radiative recombination and/or assist one of the charges to enhance the charge balance and avoid current crowding. The biasing conditions may be chosen to fix the dominant issue. For example, in the case of a red LED, leakage current is the major source of efficiency loss at moderate to low current densities. In this case, the biasing condition may block/reduce the leakage current to allow a significant efficiency boost. In another case, such as a green LED, Auger recombination may be the main issue. The biasing condition may be adjusted to reduce this type of recombination. It is noted that one bias condition may eliminate/reduce more than other bias conditions and LED types. Dynamically adjusting the biasing condition may also provide better performance. For example, in lower current density, one effect, such as leakage current may be the dominant effect, but at a higher current density, charge crowding, and other issues may be the dominant effect. As such, the bias may be modified accordingly to offer better performance. The bias may be adjusted as a single device, cluster of devices, or the entire array of devices. The bias may also be different for different devices. For example, LED versus sensors, or red versus green LEDs may all have different biasing conditions.

The process to form the MIS structure112on the micro device100is described inFIGS.2A to2C. The order of the steps in these processes may be changed without affecting the final results. Moreover, each step may be a combination of a few smaller steps.

With reference toFIG.2A, in a first step200, the micro devices100are formed. During step200, the micro devices100are formed by either patterning or selective growth. During step202the micro devices100are prepared for transfer which may include cleaning or moving to a temporary substrate. During step204, the MIS structure112is formed on one surface of the micro device100. During step206, the device100is again prepared for transfer, which may include a lift-off process, a cleaning process, and/or other steps. In addition, during step206, connection pads or electrodes for device function electrodes or for the MIS structure112may be deposited and/or patterned. During step208, selected devices100are transferred to a receiver substrate by various methods, including but not limited to pick-and-place or direct transfer. In step210, connections are formed for the device100and the MIS structure112. In addition, other optical layers and devices may be integrated to the system substrate after the transfer process.

Another example of a process to form the MIS structure112on the micro device100is illustrated inFIG.2B. First the micro devices100are formed in step200. During step200, the micro devices100may be formed by patterning or by selective growth. During step202, the micro devices100are prepared for transfer, which may include cleaning or moving to a temporary substrate. During step204-1, part of the MIS structure112is formed, for example by deposition and patterning a dielectric layer, on one surface of the micro device100. During step206, the micro devices100are again prepared for transfer, which may include a lift-off process, cleaning process, and/or other steps. In addition, during step206, connection pads or electrodes for micro devices100or MIS structure112are deposited and/or patterned. During step208, selected micro devices100may be transferred to a receiver substrate. The transfer may be done by various methods including but not limited to pick-and-place or direct transfer. The MIS structure112may then be completed during step204-2, which may include deposition and patterning of a conductive layer. During step210, connections are formed for the micro devices100and the MIS structure (or structures)112. Other optical layers and devices may be integrated to the system substrate after the transfer process. Step210may be the same as step204-2or a different and/or separated step. Other process steps may also be executed in between steps204-2and210. In one example, a passivation or planarization layer may be deposited and/or patterned prior to step210to avoid shorts between MIS electrodes and other connections.

With reference toFIG.2C, another example of a process to form MIS structure112on the micro device100is illustrated. First the micro devices100are formed in step200by patterning or by selective growth. During step202, the devices100are prepared for transfer, which may include cleaning or moving to a temporary substrate. In addition, during step202, connection pads or electrodes for the function of the micro device100and/or for the MIS structure112may be deposited and/or patterned. During step208, selected micro devices100may be transferred to the receiver substrate by various methods, such as but not limited to pick-and-place or direct transfer. The MIS structure112is then formed during step204, e.g. on the receiver substrate, after the final transfer, which may include deposition and patterning of dielectric and conductive layers. During the following step210, connections are formed for the micro devices100and the MIS structures112. In addition, other optical layers and devices may be integrated to the system substrate after the transfer process. Step210may share some of the same process steps with step204or be a completely separate step. In the latter case, other process steps may be done between204and210. In one example, a passivation or planarized layer may be deposited and/or patterned prior to step210to avoid shorts between MIS electrodes and other connections.

After patterning the micro devices100, depending on the patterning process, each micro device100may have straight or sloped walls. The following descriptions are based on selected sloped embodiments, but similar or modified processing steps may be used for other embodiments as well. In addition, depending on the transfer method, each micro device face connected to the receiver substrate may vary and therefore affect the slope of the device wall. The processing steps described next may be used directly or modified to be used with other slopes and device structures.

FIG.3illustrates a plurality of micro devices306, similar to micro devices100, which have been transferred to a system or receiver substrate300. The micro devices306include a sidewall of faces with a negative slope i.e. at an acute angle with a top of the micro device306and an obtuse angle with the bottom of the micro device306or with the system substrate300. Each micro device306is connected to a circuit layer302through at least one contact pad304. Depending on the slope of the sidewalls, an MIS structure may be formed using normal or polymer deposition. The methods described herein may be used with some modifications or directly for this case. However, if the slope is too steep, the preferred way is to prepare the MIS structure on the micro devices306prior to transfer. An exemplary method for creating an MIS structure prior to transfer will be described hereinafter.

FIG.4illustrates a process flowchart for a basic wafer etching process1000for forming a mesa structure formation. In step1001, the wafers may be cleaned, e.g. using piranha etching containing sulfuric acid and hydrogen peroxide, followed by cleaning with hydrochloric diluted DI water. Step1002may include deposition of a dielectric layer. In step1006, the dielectric layer may be etched to create an opening on the layer for subsequent wafer etching. In step1008, the wafer substrate may be etched using a dry etching technique and chlorine chemistry to develop mesa structures. In step1010, hard mask may be removed by a wet or dry etching method, and the wafer may then be subsequently cleaned in step1012.

Embodiments of a method to form an MIS structure in accordance with process1000are illustrated with reference toFIGS.5A to5D. The micro devices406may include a vertical sidewall structure, a negative slope sidewall structure or a positive slope sidewall structure (i.e., the sidewalls are at an acute angle with the base of the micro device406and the system substrate400). InFIG.5A, each of the micro devices406are transferred to a system substrate400, and connected to a circuit layer402, which is formed or mounted on the system substrate400, through at least one connection pad404. After this step, the MIS structure may be initiated and completed or simply completed. While traditional lithography, deposition, and patterning processes are applicable to create or complete such structures and to connect the micro devices to proper bias connections, different methods may be used with further tolerance to misplacement of the micro devices. Specifically, in large area processes, micro device placement inaccuracy may be a few micrometers.

With reference toFIG.5B, in this embodiment a dielectric layer408may be deposited around the micro devices406to cover unwanted exposed portions of the contact pads404. Openings for vias418may be formed (e.g., etched) in the dielectric layer408to connect a conductive layer412of the MIS structure to the circuit layer402. A similar or different dielectric layer410may be deposited on at least one side of each of the micro devices406, as part (i.e., the insulator part) of the MIS structure. The dielectric layer410deposition step may be conducted prior to transferring the micro device406to the system substrate400, at the same time as the dielectric layer408, or after deposition of layer408. Subsequently, the conductive layer412may be deposited and patterned around and between each micro device406, to complete the MIS structure. In an embodiment, the conductive layer414may connect at least two micro device/MIS structures together. In addition, or alternatively, the conductive layer416may connect the MIS structure to a contact pad404of the micro device406. The conductive layer412may be transparent to enable other optical structures to be integrated into the system substrate400. Alternatively, the conductive layer412may be reflective to assist with light extraction, direction, reflection, or absorption. The conductive layer412may also be opaque for some applications. Further processing steps may be carried out after forming the MIS structure, such as but not limited to depositing a common electrode or integrating optical structure/devices.

FIGS.5C and5Dillustrate an exemplary structure for depositing a common electrode426on an opposite side of the MIS structure to the system substrate400. The upper surface of the MIS structure is planarized (e.g., using a dielectric material) similar to dielectric layer408, and then patterned (e.g. etched) to provide access points to connect the common electrode426to the micro devices406. The common electrode426may be coupled to either the micro device406, the MIS structure (i.e., conductive layer412), or the circuit layer402through patterning (e.g., openings420,422, and424).

The common electrode426may be transparent to the light from micro devices406to enable the light to pass therethrough, reflective to the light from the micro devices406to reflect the light back through the system substrate400, or opaque to the light from the micro devices406to minimize reflection. The common electrode426may also be patterned to create addressable lines. Several other methods may be used for deposition of the common electrode426. Other optical devices and structures may be integrated onto the system substrate or into the circuit layer before or after the common electrode426.

With reference toFIGS.6A to6C, an alternative process includes forming part or most of the MIS structure on a donor (or intermediate or original) substrate560prior to transferring micro devices504to a system substrate500. The initial process steps may be conducted on the original substrate used for micro devices504fabrication or on any intermediate substrate. With reference toFIG.6A, a first dielectric layer516may be deposited prior to forming the MIS structure, which may avoid any unwanted short/coupling between the MIS layer and the other contacts after transfer. The MIS structure is formed by a gate conductive layer512and a dielectric layer510deposited around and between the micro devices504. The dielectric layer510may be similar to first dielectric layer516or different. The first dielectric layer510may also be a stack of different dielectric material layers. In example MIS structures550and552, no top dielectric layer518is deposited on top of the conductive layer512. In example MIS structure552, the gate conductive layer512is recessed down from the top edge of the micro device504to avoid any short with a top electrode. However, the gate conductive layer512may cover the top edge of the micro device504, if desired. In example MIS structure554, the gate conductive layer512may include a wing portion that extends outwardly from an angled portion parallel to the donor substrate560beyond a dielectric layer518to create easier access to create connections after transfer to a system substrate. In addition, the micro device504may be covered with a second dielectric layer518with openings to connect to the micro device504and the extended electrode512. Example MIS structure556may use the second dielectric518to cover only the top side of the conductive layer512and the micro device504, except for an opening for the top electrode to contact the micro device504.

FIGS.6B and6Cshow the micro devices504with MIS structures after they were transferred to the system substrate500. During the transfer process, the micro devices504may be flipped so that the bottom surface connected to the donor substrate560is also connected to the system substrate500. A connection pad506may be provided between each micro device504and the system substrate500to couple the micro devices504to the circuit layer502. Different methods may be used including the one described above to create a connection for the MIS structure and other electrodes (e.g., a common electrode). In another embodiment, the example MIS structures550and552include a top electrode541covering both the micro device504and the gate conductive layer512of the MIS structure. The top electrode542may be connected to the circuit layer502with a via532extending through the dielectric layer516or the electrode541may be connected at the edge of the system substrate500through bonding. In example MIS structure554, an extension540of the conductive layer512may be used to couple the MIS structure (i.e., the conductive layer512) to the circuit layer502. The first dielectric layer516may be extended on the system substrate500to cover the connection pads506between micro device504and the system substrate500to avoid possible shorts between the MIS structure and other connections. A top electrode542may be provided, as in example MIS structures554and556, which extends through an opening in the top dielectric layer518into contact with the micro device504. With regards to example MIS structure556, the MIS structure (e.g. the conductive layer512) may be shorted to the device contact pads506or the MIS structure may be aligned properly to have its own contact on the system substrate500. For both example MIS structures554and556, different post-processing steps may be used, similar to other structures disclosed herein. One example may be a common electrode deposition with or without planarization, as inFIG.5D. Another example may be light confinement structure or other optical structures.

FIGS.7A and7Billustrate an alternative process, in which part or most of the MIS structure are formed on the donor (or intermediate or original) substrate560prior to their transfer to the system substrate500. The process may be done on the original substrate used for fabrication of the device or on any intermediate substrate.FIG.7Aillustrates several different example MIS structures650,652and654, which may be formed on micro devices604. However, other structures may be used as well. A dielectric layer616may be deposited prior to forming the MIS structures, which may avoid any unwanted short/coupling between the MIS structure and other contacts after transfer. The MIS structure includes a conductive layer612, and a dielectric (i.e., insulating) layer610. The dielectric layer610may be similar to516or different. The dielectric layer610may also be a stack of different dielectric material layers. In addition, a connection pad614may be formed on each micro device604that extends through an opening in the dielectric layer610. In example MIS structure650and652, no dielectric may be deposited on top of the conductive layer612. However, in example MIS structure654an additional layer of dielectric618may be provided for planarization and extra insulation between the contact pad614and the conductive layer612. In example MIS structure652, the conductive layer612may be contiguous (i.e., the same) as the contact pad614. The conductive layer612may be recessed from the edge of the micro device604or the conductive layer612may cover the edge of the device604. In structure654, the conductive layer612includes an extension that extends parallel to the system substrate660to create easier access to create connections after transfer to system substrate660. In addition, the micro device604may be covered with a dielectric layer618with openings for connection of the contact pad614to the micro device604and the extended electrode612to the system substrate660.

FIG.7Bshows the micro devices604with MIS structures after being transferred to the system substrate600. A connection pad614may be provided between each micro device604and the system substrate600to couple each micro device604to the circuit layer602. Different methods may be used, including the ones described above, to create connections between the MIS structures and other electrodes (e.g. a common electrode). Another method is illustrated inFIG.7B, for MIS structure650and654, in which the negative slope of the micro device604is used to create a connection between the MIS structures650and654, and the system substrate600through an electrode618that extends from the conductive layer612parallel to the system substrate600along the top of the dielectric layer621. A conductive metal via620may extend through a passivation or planarization (e.g., dielectric) layer621, into contact with the circuit layer602. The passivation or planarization layer621may be deposited prior to the electrode618deposition and patterning. The micro device604may be covered during electrode deposition or the conductive layer612may be removed from the top of the micro device604by patterning and etching. Using the negative slope of the micro device604and the conductive layer612to separate the top electrode622of the micro device604and the MIS electrode618, minimizes misalignment therebetween, which is crucial for high throughput placement of the micro devices604. The negative slope of the side face of the micro device604and the conductive layer612forms an acute angle with the circuit layer602and the system substrate600. For all structures, different post-processing steps may be used, similar to other structures disclosed herein. One example may be a common electrode deposition with or without planarization. Another example may be light confinement, or reflective structure or another optical structure.

The methods described herein may be used for different structures and the methods are just examples and may be modified without affecting the outcome. In one example, any one of the top and bottom electrodes622and614and the conductive layers612may be either transparent, reflective, or opaque. Different processing steps may be added between each step to improve the device or integrate a different structure into the device without affecting the outcome of creating the MIS structure.

Vertical Devices with Conductivity Modulation Engineering

FIG.8Aillustrates a schematic of a vertical solid state micro device, similar to micro devices406,504, and604, showing lateral current components flowing from a top electrode layer, which is capable of directing current through the bulk of the micro device in a device layer701. The device layer701is formed on a device substrate700with contact pads703(i.e., the top electrode) formed (e.g., etched) on the device layer701. A voltage source704may be connected to the contact pads703and a common bottom electrode702, mounted on the device substrate700, to generate current to power the micro devices. The functionality of device layer701is predominantly defined by the vertical current. However, due to the top surface lateral conduction of the device layer701, current705with lateral components flows between the contact pads703and the common electrode702. In order to reduce or eliminate the lateral current flow705, these techniques are suggested:1. Top layer resistance engineering.2. Full/partial etching modulation.3. Material conductivity modulation.

In this way, the lateral current flow structure may be divided into three main structures:1) at least one conductive layer703with resistance engineering;2) a full or partial etching of one or more conductive layers703, and3) a material for conductivity modulation (e.g., alternating conductive and non-conductive sections or conductive sections separated by non-conductive sections).

The conductive layer703with resistance engineering may be described as follows. The semiconducting top layer of the device layer701, just before the metallic contact703, may be engineered to limit the lateral current flow by manipulating the conductivity or thickness of the conductive layer703. In one embodiment, when the top layer of the device layer701is a doped semiconducting layer, decreasing the concentration of active dopants and/or the thickness of the layer may significantly limit the lateral current flows. Also, the contact area may be defined to limit the lateral conduction. In another case, the thickness of the conductive layer703(or more than one conductive layer) may be reduced. After that, the contact layer703may be deposited and patterned. Deposition of the contact layer703may occur on an array of interconnected or contiguous micro devices or on non-isolated micro devices. As a result, the active layers of the device layer701are not etched or separated to create individual micro devices. Therefore, no defect is created at the perimeter of the isolated micro devices, since the isolation is developed electrically by controlling the current flow.

Similar techniques may be used on isolated micro devices to diverge the current from the perimeter of each micro device. In another embodiment, after the micro device is transferred to another substrate, the other conductive layer(s) are exposed. The thickness of the device layer701may be chosen to be high to improve device fabrication. After the contact layer703is exposed, the thickness may be reduced, or the dopant density decreased, however, some of the contact layers703may also have a blocking role for the opposite charge. As a result, removing some of the conductive layers of the contact layer703to thin the total contact layer resistance may reduce the device performance. However, conductive layer removal may be very efficient for single layer engineering.

With reference toFIG.8B, another embodiment of a micro device structure in accordance with the present invention includes a partially etched top layer716of a micro device layer718. In this embodiment, the top conductive layer716may be a p- or-n-doped layer in a diode. The material for conductivity modulation directs current through the bulk of the vertical solid state device in the device layer718. At least one of the conductive layers (e.g., top conductive layer716) in the device layer718may be partially or fully etched, to form alternating raised conductive layer sections and open non-conductive areas. The top conductive layer716below top contact712and on top of the device layer718may be fully or partially etched to eliminate or limit the lateral current flow in the micro devices714formed in the device layer718. Each micro device714is defined by the size of the top contact pad712. This is especially beneficial for micro devices714in which the resistance manipulation of the top layer716will adversely affect the device performance. The thickness of the top conductive layer716between adjacent devices714is reduced to make a higher resistance for the current to flow in the lateral direction. An etching process may be done using, for example, dry etching, wet etching or laser ablation. In many cases, the top contact712may be metallic and/or used as the mask for the etching step. With full etching, the etching may stop at a function layer of the device layer718. In one embodiment, the top contact712may be deposited on top of the conductive layer716, and may be used as the mask for etching the conductive layer(s)716, potentially enabling fewer processing steps and a self-aligned structure. This is especially beneficial for micro devices714in which the resistance manipulation of the conductive layer716will adversely affect the vertical device performance. In this embodiment, the thickness of the conductive layer716is reduced in selected areas to make a higher resistance for the current to flow in the lateral direction. After the bottom conductive layers of the device layer718are exposed either by transfer mechanism or etching substrate710, the same etching process may be performed. Again, the contact712may be used as the mask for etching the device layers716and718.

With reference toFIG.8C, another embodiment of a micro device structure in accordance with the present invention includes a top conductive modulation layer722on the device layer718. As shown, the resistance of a (non-conductive or reduced-conductive) modulation area720of the top conductive modulation layer722between adjacent contact pads712is manipulated (e.g., increased to greater than conductive layer722) to limit the lateral current flow components. Counter doping, ion implantation, and laser ablation modulation are examples of processes that may be used to form the modulation areas720in this embodiment. The ion implantation or counter doping may extend beyond the conductive layer722into the device layer718to further enhance the isolation between the current flowing through adjacent micro devices714. Similar to the full/partial modulation scheme, in this embodiment the top contact712may be deposited on the top conductive layer722first, and then used as a mask for the doping/implantation of the areas720. In another embodiment, oxidation may be used to form the modulation areas720. In one method, a photoresist is patterned to match the modulation area720, and then the devices are exposed to oxygen or another chemical oxidant to oxidize the modulation areas720. Then, the top contacts712may be deposited and patterned. In another method, the top contacts712are deposited and patterned first, and then the top contact712is used as a mask for oxidation of the modulation areas720. The oxidation step may be done on isolated devices or non-isolated devices. In another embodiment, prior to oxidation, the total thickness of the conductive layer(s)722may be reduced. The reduction step may be done on selected modulation areas720for oxidation only. In another case, the oxidation may be done on the walls of the micro devices714, which is especially applicable for isolated devices. Also, the bottom layer of the device layer718may be modulated similarly after being exposed. In another embodiment, the material conductivity modulation may be done through electrical biasing. The bias for the areas720that require high resistance is modified. In one embodiment, the effect on the areas720may be extended to the device layers718. Here, the conductive layer722may be modified (e.g., etched or implanted) with other methods described herein as well. In one embodiment, charge may be implanted underneath area720inside device layers718. The implantation may be partial or all the way to the other side of the device layer718.

In one embodiment, the bias modulation may be provided using an MIS structure, and the metal layer may be replaced with any other conductive material. For example, to prevent the current from the contact712from going further away from the contact laterally, an MIS structure is formed around the contact712. The MIS structure may be formed before or after the contact is in place. In all above-mentioned embodiments, the area of the active micro device714is defined by the top contact pads712formed on the device layer718.

The definition of the active device area by the top contact pad712may be more readily applied to micro devices714with pillar structures.FIG.8Dillustrates a cross section of an MIS structure surrounding a single contact layer712; however, it is understood that the same may be done for more than one contact layer712. The device layer718is a monolithic layer comprising or consisting of pillar structures722. Since the pillar structures722are not connected laterally, no lateral current component exists in the device layer718. One example of these devices is nanowire LEDs, in which each LED device consists of several nanowire LED structures fabricated on a common substrate710. In this case, as shown inFIG.8D, the top metallic contact712defines the active area of the LED structure714. Device layers718with no lateral conduction are not limited to pillar structures and may be extended to device layers718with separated active regions, such as layers with embedded nano or microspheres, or other forms.

InFIG.8E, another embodiment of a micro device structure in accordance with the present invention includes an MIS structure715surrounding the contact layer712. The MIS structure715comprises a top conductive layer716, a middle insulator (e.g., dielectric) layer717, and a bottom semiconductor layer723, which may be a top layer of the device layer718. Biasing the conductive layer716of the MIS structure715to an off voltage causes limited or no current to pass through the MIS structure715laterally. The MIS structure715may be formed on the device layer718or may be part of the transferred substrate, and the MIS structure715defines the direction of lateral conduction. Other configurations are conceivable, such as the conductive layer716may extend to both sides of MIS structure715, such that the dielectric717may extend over other conductive layers712. The MIS structure715may be an open or closed structure, or alternatively, a continuous or one-piece structure. In another embodiment, the dielectric717may comprise the oxidation layers from a photoresist or masking step. Another dielectric layer may be deposited on top of the oxidation layer, or a deposited dielectric layer may be used by itself. In another embodiment, the conductive layer(s)716may be removed so that the dielectric layer717is in contact with a semiconductor layer723. The MIS structure715may also be formed on the walls of the micro device714to further deter current from travelling to the edge of the micro device714. The micro device surface may also be covered by a dielectric layer. For example, a gate conductive layer may be deposited and patterned for a gate electrode716, and then a dielectric layer717may be patterned using the gate electrode716as a mask. In another method, the dielectric layer717, which is an insulator, is patterned first, and then the gate electrode716is deposited after. The gate electrode716and the contact712may be patterned at the same time or separately. A similar MIS structure may also be made on the other side of the device layer718after it is exposed. The thickness of conductive layers716of the micro device714may be reduced to improve the effectiveness of the MIS structure715. Where selective etching or modulation of the conductive layer716on either side of the vertical micro device714is difficult, the MIS structure method may be more practical, in particular if etching or resistance modulation may damage the active device layer718. In the described vertical structures, the active device area714is defined by the top contact area712. Here, the ion implantation in the dielectric layer717or the charge storage in a floating gate716may be used to permanently bias the MIS structure715.

FIGS.8F and8Gillustrate a structure highlighting the use of a dielectric layer712-1between the contact pads712. The contact pads712define the micro devices in a device layer701on top of a substrate700, which may be sapphire or any other type of substrate. The micro devices include a conductive layer702and a contact pad712. InFIG.8F, the conductive layer702is intact, but inFIG.8Gthe conductive layer702is either etched, modified, or doped between each contact pad712with a different carrier or ions. Some extra bonding layers712-2may be placed on top of the contact pads712, or the contact pads712may comprise the bonding layers712-2. The bonding layers712-2may be for eutectic bonding, thermocompression, or anisotropic conductive adhesive/film (ACA/ACF) bonding. During the bonding, the dielectric layer712-1may prevent the contact pads712from expanding to other areas and creating contacts. In addition, the dielectric layer712-1may also be a reflector or a black matrix to confine the light further. This embodiment is applicable to the embodiments demonstrated inFIG.8-11and all other related embodiments. The methods described here can be applied to either side of the micro devices.

Method for Manufacturing LED Displays

Methods for manufacturing LED displays are described using LED devices grown on a common (e.g., sapphire) substrate. Each LED may comprise a substrate750, a first doped conductive layer752(e.g., n-type layer) active layers754, and a second doped conductive layer756(e.g., p-type layer) formed on the substrate750. The following is described with reference to a Gallium Nitride-based (GaN) LED; however, the presently described vertical device structure may be used for any type of LEDs with different material systems.

With reference toFIG.9A, the GaN LEDs are fabricated by depositing a stack of material on the sapphire substrate750. The GaN LED device includes the substrate750, such as sapphire, an n-type GaN layer752formed on the substrate750or a buffer layer (for example GaN), an active layer754, such as a multiple quantum well (MQW) layer, and a p-type GaN layer756. A transparent conductive layer758, such as Ni/Au or ITO, is usually formed on the p-doped GaN layer756for better lateral current conduction. Conventionally, a p-type electrode760, such as Pd/Au, Pt, or Ni/Au is then formed on the transparent conductive layer758. Since the substrate750(sapphire) is an insulator, the n-type GaN layer752is exposed to make an n-contact762to the n-type layer752. This step is usually done using a dry etch process that exposes the n-type GaN layer752, and then deposits the appropriate metal contacts for the n-contact762. In LED display applications where display pixels are single device LEDs, each LED is bonded to a driving circuit which controls the current flowing into the LED device. Here, the driving circuit may be a thin film transistor (TFT) backplane conventionally used in LCD or organic light-emitting diode (OLED) display panels. Due to the typical pixel sizes (10-50 μm), the bonding may be performed at a wafer level scale. In this scheme, an LED wafer, comprised of isolated individual LED devices, may be aligned and bonded to a back-plane which is compatible with the LED wafer in terms of pixel sizes and pixel pitches. Here, the LED wafer substrate may be removed using various processes such as laser lift-off or etching.

FIG.9Billustrates a fabrication process of an LED display, including the integration process of a device substrate801with micro devices in a device layer805defined by top contacts802, and bonding of the device substrate801to a system substrate803. Micro devices are defined using the top contact802formed on top of the device layer805, which may be bonded and transferred to the system substrate803with corresponding and aligned contact pads804. For example, the micro devices may be micro LEDs with sizes defined by the area of their top contact802using any methods explained above. The system substrate803may be a backplane with transistor circuitry to drive individual micro LEDs. In this process, the LED devices are isolated by dry etching and passivation layers. Fully isolating the devices may create defects in the active or functional layers, reducing the efficiency and imposing non-uniformities. Since the perimeter compared to the area of the micro devices is more substantial as the device becomes smaller, the effect of defects become more noticeable. In one embodiment, a monolithic LED device is converted into individual micro LEDs without etching the active area and using lateral conductive manipulation. As a result, there is no sidewall within the micro LED to create defects. The surrounding walls across the array of LEDs may be thereby extended until they have no effect on the peripheral LED devices. Alternatively, a set of dummy LED devices around the array may be used to reduce the effect of the peripheral walls on the active micro LED devices. This technique may also be used to prevent or reduce the current going through the sidewalls.

In another embodiment, illustrated inFIG.9C, an LED wafer may be fabricated such that the device layer805includes a first doped conductive (e.g., an n-type) layer852on a substrate801with the second doped conductive layer (e.g., a p-type) layer854as the top layer, and the monolithic active layer856therebetween. Each contact802defines an illumination area860. The thickness of the second doped conductive (e.g., p-type) layer854and conductivity may be manipulated to control the lateral conduction through the device. This may be done by either etching the pre-deposited conductive layer854or by depositing a thinner second (e.g., p-type) conductive layer854during the LED structure fabrication. For the etching method, accurate thickness control may be achieved using a dry etching process. In addition, the material structure of the second (e.g., p-type) layer854may be modified based on layer doping level to increase the layer's lateral resistance. The second doped conductive layer854does not have to be limited to the p-type layer and may be extended to other top layers in the LED structure. As a result of this modification, the illumination area860may be defined solely by the area of the deposited contact layer802on top of the p-type film854.

In another embodiment illustrated inFIG.9D, to further limit the lateral illumination, the second doped conductive layer (e.g., p-layer)854between two adjacent pixels may be fully or partially etched. This process step may be done after the contact layer (e.g., contacts802) is deposited in a process such as dry etching. In this case, the contact layer802may be used as a mask for etching the second conductive layer854. Preferably the present structure limits or eliminates the wall passivation of pixels, which results in a higher number of pixels in a specific area of the wafer or higher pixels per inch (PPI). This may also be translated to fewer process steps and a lower fabrication cost compared to fully isolated LEDs with wall passivation.

In another embodiment illustrated inFIG.9E, an LED wafer structure is defined by the top contacts802and a sub-divided second doped conductive (e.g., p-type) layer854including individual sections defined by laser etching for example. Here, the second conductive layer854(e.g., p-type) may be partially or fully removed using laser ablation etching of the top conductive material (e.g., GaN). In this case, laser fluence defines the ablation rate, and any thickness of the second conductive (e.g., p-type GaN) layer854may be etched precisely. One example of such a laser is a femtosecond laser at red or infrared wavelengths. Here, the top metal contacts802or other protective layers are used as a mask in the laser etching process steps. Alternatively, the laser beam size may be defined using special optics to match the desired etching region dimensions. In another example, shadow masks may be used to define the sections of the second conductive layer854(i.e., the etching regions) between contacts802. Laser ablation etching may also be extended to the other layers (e.g., at least one of the active layer856and the first conductive layer, such as n-type, layer852, of the LED structure). In this case, the individual LED devices may be isolated fully or partially from each other. In this scenario, it may be required to passivate LED etched walls by depositing dielectric layers.

In the above-mentioned embodiments, contacts865for the first conductive layer852(e.g., n-layer contacts) may be formed after the first conductive layer852is exposed either by bonding and removing the LED wafer substrate801that connects to the backplane circuitry803or any other substrate, or by etching the substrate801. In this embodiment, the first (e.g., n-type) layer contact865may be a transparent conductive layer to enable light illumination therethrough. In this embodiment, the first (e.g., n-type) layer contact865may be common for all or part of the bonded LEDs, as shown inFIG.9F, which illustrates an LED wafer, as herein described with particular reference toFIGS.9C to9E, with the substrate801removed and replaced with a common transparent n-contact865, and the contacts802bonded to bonding pads804of the backplane structure803. In cases where the LED device structure is grown on a semiconductor buffer layer, for example an undoped GaN substrate, in place of substrate801, this buffer layer may be removed after the LED transfer process to access the first conductive, (e.g., n-type) layer852. In the embodiment shown inFIG.9F, the entire GaN buffer layer is removed using processes such as dry/wet etching. As demonstrated inFIG.9Gin another embodiment, the first conductive (e.g., n-type) layer852may be connected to the common electrode865with a layer of alternating dielectric sections871and doped conductive sections (e.g., n-type)872, with the conductive sections872superposed over a corresponding contact802to define the illumination areas. The second conductive (e.g., p-type) layer854may be connected to the contacts802. In another embodiment, both the first (e.g., n-type) and the second (e.g., p-type) layers852and854may be connected to a controlling electrode (e.g.,865) or a backplane (e.g.,803) for further pixelation.

FIG.10Aillustrates an integrated device900with micro devices defined by top contacts903bonded to a system substrate904, which may include bonding pads905. A common electrode906, may be formed on top of the structure. After transferring and bonding the device layer902, which comprises a first conductive (e.g., n-type) layer, a second conductive (e.g., p-type) layer, and an active layer therebetween, a common top electrode906may be deposited on the structure. For some optical device layers, the common top electrode906may be a transparent or a reflective conductive layer. The second conductive (e.g., p-type) layer may be thinned to reduce the light scattering effect before depositing the top contacts903. In addition, a bank structure that has alternating first conductive material, n-type, and dielectric sections, may be used to define the pixels where the wall of the banks (i.e., dielectric layer) are opaque or reflective layers, as described with reference toFIG.9G.

With reference toFIG.10Bin an alternative embodiment, the LED wafer900includes a buffer (e.g. dielectric) layer908and one or more common metallic contacts910(e.g., n-contact vias) extending through the buffer layer908into contact with the device layer902(e.g., first conductive, such as n-type). The integrated device900′ includes micro devices defined by top contacts903bonded to a system substrate904, ideally using contact pads905. The common electrodes910may be formed at the edges of the device layer902and through the buffer layer908on top of the device layer structure902. As shown, the buffer layer908is patterned around the edge to extend vias through the buffer layer908to make metallic contacts to the first conductive (e.g., n-type) layer. The top layer of the integrated device layer structure902may be a layer with low conductivity. For example, the top layer may be a buffer layer used during the growth of the device layer902. In this case, the common electrodes910may be formed by making vias through the buffer layer908, for example at the edge of the structure to avoid the top buffer layer.

With reference toFIG.10C, a transferred LED wafer900″ includes a device layer902with a patterned first conductive (e.g., n-type) layer. Underneath the n-type layer is an active layer and a p-type layer, as hereinbefore described. To further decrease the lateral light propagation or adjust the device definition, the first conductive (e.g., n-type) layer is patterned by partially or fully removing the first conductive layer to form open channel grooves907between first conductive sections, using the same structure as the front metallic contact910. Alternatively, the thickness of the first conductive layer may be reduced. The first (e.g., n-type) contact may be formed by depositing a transparent conductive layer on top of the device layer structure902. The integrated device900″ with micro devices defined by the top contacts903may be bonded to a system substrate904. The top of the device layer structure902is patterned to isolate micro devices electrically. The other layers (e.g., active and second conductive) and device layer902may be patterned or modulated to further isolate micro devices electrically and/or optically.

FIGS.10D and10Eillustrate another embodiment of a transferred LED wafer with a patterned first conductive (e.g., n-type) layer of the device layer902. In cases where the buffer layer908is present, both the buffer layer908and the first conductive (e.g., n-type) layer are patterned with open channel grooves907between superposed first conductive and buffer layer sections. In one embodiment, the patterned grooves907may be further processed and filled with a material that improves the light propagation through the patterned area. An example of this is surface roughening to suppress total internal reflection and a reflective material that prevents vertical light propagation in the grooves907. The integrated device900′″ comprises micro devices defined by top contacts903bonded to a system substrate904using bonding pads905. The top of the structure is patterned to isolate micro devices electrically and optically, and common contacts910are formed at the edge of the device layer structure902. If the buffer layer908exists, the buffer layer908needs to be patterned or modulated as well to isolate micro devices. Similar to the embodiment shown inFIG.10B, the common contacts910may be formed, for example, at the edge of the active layer structure902through vias in the buffer layer908. In addition, color conversion layers (or color filter layers) may be deposited on top of the patterned buffer or conductive layers908and902to create a color display. In one case, the color conversion layers (or color filter layers) may be separated by a bank structure that may be reflective as well.

An integrated device900″″, illustrated inFIG.10F, includes micro devices defined by top contacts903bonded to a system substrate904with optical elements914formed in the grooves907between adjacent micro devices. As shown, the open channel grooves907may be filled by a layer or a stack of optical layers914to improve the performance of isolated micro devices. For example, in optical micro devices, the optical elements914may comprise some reflective material to better outcouple the light generated by the micro devices in a vertical direction.

FIG.10Gillustrates another embodiment of a transferred LED wafer900′″″ including the device layer902comprising a first conductive (e.g., n-type) layer921, a second conductive (e.g., p-type) layer922, and a monolithic active layer923therebetween. The second conductive layer922is electrically connected to the backplane904using the contacts903and corresponding contact pads905on the backplane904. The first conductive layer921and the buffer layer908are patterned to form open channel grooves907between raised first conductive layer portions. As hereinbefore described, the grooves907may include light management elements914(e.g., reflective material to direct light vertically and prevent scattering between micro devices).

In LED display applications where display pixels are single device LEDs, each LED should be bonded to a driving circuit which controls the current flowing into the LED devices. Here, the driving circuit may be a TFT (Thin Film Transistor) backplane904conventionally used in LCD or OLED display panels. Due to the typical pixel sizes (10-50 μm), the bonding may be performed at a wafer level scale. In an embodiment, an LED wafer comprises isolated individual LED devices aligned and bonded to the backplane904, which is compatible with the LED wafer (e.g.,900′ or900″) in terms of pixel sizes and pixel pitches. Here, the LED wafer substrate may be removed using various processes, such as laser lift-off or etching. In this embodiment, it is important to isolate the LED devices by dry etching and passivation layers.

In another embodiment, illustrated inFIG.10H, the original LED wafer is fabricated with the second conductive (e.g., n-type) layer922as the top layer. After the second conductive layer922is bonded to the backplane904using the contacts903and the contact pads905, the original substrate is removed to expose the first contact (e.g., p-layer)921. The thickness and conductivity of the first conductive (e.g., p-type) layer921is manipulated to control the lateral conduction. This may be done by either etching the deposited first conductive (e.g., p-type) layer921or by depositing a thinner p-layer to form alternating second conductive layer sections921aand dielectric layer sections925during the LED device layer structure902fabrication. For the etching scenario, an accurate thickness control may be achieved using a dry etching process. In addition, the material structure of the first conductive (e.g., p-type) layer921may be modified in terms of the layer doping level to form alternating high and low doped second conductive layer sections921ato increase the layer's lateral resistance. The modifications to the top layer are not limited to the first conductive (e.g., p-type) layer921and may be extended to other top layers in an LED device layer structure902. As a result of this modification, the illumination area may be defined solely by the deposited conductive layer area on top of the p-type film.

To further limit the lateral illumination, the second conductive (e.g., n-type) layer922between two adjacent pixels may be fully or partially etched. This process step may be done after the conductive layer deposition in a process such as dry etching, as inFIGS.9D and9E. In this case, the contacts903in the contact layer may be used as a mask. One important advantage of this scheme is eliminating the wall passivation of pixels which results in a higher number of pixels in a specific area of the wafer, or higher pixels-per-inch (PPI). This may also be translated to fewer process steps and a lower fabrication cost compared to fully isolated LEDs with wall passivation.

FIG.10Halso shows an exemplary embodiment to integrate a color filter or color conversion layers930(and/or other optical devices) on top of the top electrode906. Here, individual color filter sections of the layer930may be separated by a bank (dielectric or insulating material) structure931. The bank structure931may be reflective or opaque to ensure that the light remains in the light emitting areas above the contacts903. The bank structure931may extend the dielectric layer925that is used to separate second conductive layer sections921a, as illustrated inFIG.10I. In the embodiment ofFIG.10I, the top common electrode906includes recesses that extend upwardly adjacent to the color filter sections930, to receive the bank/dielectric structures931/925that extend through both the second conductive layer921and the color filter section layer930.

Other layers may be deposited on top of the color conversion and/or color filter layers930. The structures ofFIGS.10H and10Imay be applied to other embodiments, for example any ofFIGS.9and10, in which any one or more of the n-type layer, the buffer layer, and the p-type layer are patterned, thinned, or modulated with material modification techniques. The color conversion layer930may be comprised of one or more materials such as phosphors, and nano materials, such as quantum dots. The color conversion layer930may blanket or cover selected areas. For a blanket deposition, the bank structure931may be eliminated. If the conductivity of the underlying first conductive (e.g., n-type) layer921is sufficient that the top common electrode906may be eliminated.

With reference toFIG.10J, the bank structure931may be replaced with first conductive layer sections921a, which extend from the first conductive (e.g., n-type) layer921. The first conductive (e.g., n-type) layer921may act as a common electrode or a common electrode906may also be provided. There may be a dielectric layer that separates part of the common electrode layer906from the first conductive layer section921ato create further pixel isolation. The color conversion layer and/or color filter layers930may be deposited on the first conductive layer921, although some other buffer layers may be used. The color conversion/filter layers930may be conductive to enable the top electrode906to power the device layer923, or an additional conductive layer935may be included adjacent to or along with the color conversion/filter layers930. The top electrode906may be deposited on top of the color conversion/first conductive layer section921alayers, if the conductivity of the first conductive layer921with the contact structure902is not sufficient. The top common contact906may be transparent to enable generated light to pass therethrough, reflective to reflect generated light back through the structure902, or opaque to absorb light and further enhance the pixel isolation.

In another embodiment, illustrated inFIG.10K, the first conductive layer921may be etched to create pillar sections to form a bank between the color filter sections930. The top and portions of the sidewalls of the pillar sections may be covered by the top electrode906, reflective layers, or opaque layers. The valleys in the first conductive layer921may be filled with the color conversion and/or color filter layers930. An additional conductive layer935(e.g., transparent) may be deposited only at the bottom of the valleys or all over the area including the sidewalls to define the light emitting area. There may be a top common electrode906or other layer deposited over the entire structure902, with raised sections that extend into the valleys into contact with the additional conductive layer of the color filter layers930. There may be a dielectric layer that separates part of the common electrode layer906from the first conductive layer section921ato create further pixel isolation.

In another embodiment, illustrated inFIG.10L, a second device layer902′ may be transferred and mounted on top of the first device layer902. The second device layer902′ includes an additional first conductive layer921′, an additional second conductive layer922′, and an additional active layer923′. Additional contacts903′ and906′ are also provided to supply power to the illumination areas. The stacked devices902and902′ may include a first planarization layer and/or dielectric layer940around the first device layer902and between the first and second devices902and902′, as well as a second planarization and/or dielectric layer941around the second device layer902′. In one embodiment, the surface of the first device layer902is planarized first. Then, openings for electrical vias945may be opened (e.g., etched) in the first planarization layer940to create contact with the backplane904. The contact (i.e., the vias)945, may be at an edge or in the middle of the first device layer902. The second contact layer903′, comprising traces and islands, are then deposited and patterned on top of the first planarization layer940. Finally, the second device layer902′ is transferred on top of the second contact layer903′. The process may continue for transferring additional device layers902. In another embodiment, the top contact906of the first device layer902may be shared with the bottom contact903′ of the second device layer902′. In this case, the planarization layer940between the first and second device layers902and902′ may be eliminated.

In another embodiment illustrated inFIGS.11A and11B, a device layer952, originally fabricated on a device substrate950, is mounted on a system substrate958using substrate contact pads or bumps954, which may define the micro device illumination areas. The micro devices in the integrated structure are partially defined by the contact bumps954on the system substrate958. In this embodiment, the device layer952may not have any top contact to define the micro device area. The device layer952on the substrate950is bonded to a system substrate958with an array of contact pads or bumps954separated by an insulation (e.g., dielectric) layer956. The bonding may be made between the metallic contact pads954and the device layer952. This bonding process may be performed using any bonding procedure, such as but not limited to heat and/or pressure bonding or laser heating bonding. An advantage of this procedure is eliminating the alignment process during the micro device transfer to the system substrate958. The micro device size960and pitch962are partially defined by the size of the contact pad/bump954. In one example, the device layer952may be LED layers on a sapphire substrate950and the system substrate958may be a display backplane with circuitry required to drive individual micro LEDs that are defined partially by the contact bumps on the backplane.

FIGS.12A and12Billustrate another integration process of a device substrate950and a system substrate958. The micro devices in the integrated structure are fully defined by the contact bumps954on the system substrate958. To precisely define the micro device size960and micro device pitch962, a bank layer958may be deposited and patterned (e.g., etched) onto the system substrate958. The bank layer958, which may include openings around each contact pad954, may fully define the micro device size960and micro device pitch962. In one embodiment, the bank layer958may be an adhesive material to fix the device layer952to the insulation or dielectric layer956(i.e., to the system substrate958).

FIG.12Cshows the integrated device substrate950transferred and bonded to the system substrate958, andFIG.12Dshows a common top electrode966formed on top of the device layer structure952. After bonding the micro device substrate950to the system substrate958, the micro device substrate950may be removed using various methods, and the common contact966may be formed above the integrated structure952. For optical micro devices, such as but not limited to micro LEDs, the common electrode966may be a transparent conductive layer or a reflective conductive layer. The bank structure964may be used to eliminate the possibility of a short circuit between adjacent pads954after a possible spreading effect due to pressure on the pads954during assembly. Other layers, such as color conversion layers, may be deposited after the bonding process.

FIGS.13A and13Billustrate another embodiment of an integrated structure in which a device layer952is mounted on a system substrate958using one or a plurality of bonding elements968at the edge of the backplane958. In this embodiment, adhesive bonding elements968may be used at the edge of the backplane958to bond the device layer952to the system substrate958or to the insulation layer956of the device layer952. In one embodiment, the bonding elements968may be used to temporarily hold the device layer952to the system substrate952for the bonding process of contact pads954to the device layer952. In another embodiment, the bonding elements968permanently attach the micro device layer952to the system substrate958.

FIGS.14A to14Cillustrate another embodiment of an integration process of the device substrate950and the system substrate958with a post bonding patterning of the device layer952and the common electrode966. In this embodiment, the device layer952may be patterned to include raised contact sections (e.g., 1.5×-3.0× the thickness of the remainder of the conductive layer) over the contact pads954, after being transferred to the system substrate958. The patterning970may be designed and implemented to isolate micro devices electrically and/or optically. After patterning the device layer952, the common top electrode966may be deposited on the device layer952formed around and on top of the raised contact sections. For optical devices, such as LEDs, the common electrode966may be a transparent conductive layer or a reflective conductive layer.

FIGS.15A to15Cillustrate an alternative embodiment of an integration process for the device substrate950and system substrate958with a post bonding patterning step, optical element, and common electrode966formation. As illustrated, after transferring and patterning the device layer952, similar toFIGS.14A to14C, additional layers970may be deposited and/or formed between isolated micro devices to enhance the performance of micro devices. In one example, the elements970may passivate the sidewalls of the isolated micro devices to help to vertical out coupling of light in the case of optical micro devices, such as but not limited to micro LEDs.

In the embodiments illustrated inFIGS.8to10and all other related embodiments, a black matrix or reflective layer may be deposited between the pads (703,712,954,908) to increase the light output. A reflective layer or black matrix may be part of the electrode.

In the presently explained methods, a protective layer may be finally formed on top of the integrated structure to act as a barrier and scratch resistance layer. Also, an opaque layer may be deposited after the micro device and patterned to form the pixel. This layer may sit anywhere in the stack. The opening allows light to pass through only the pixel array and reduces the interference.

The micro devices as described herein may be developed, for example, by etching a wafer and forming mesa structures. Mesa formation may be done using a dry or wet etching technique. Reactive ion etching (RIE), inductively coupled plasma (ICP)-RIE and chemical assisted ion beam etching (CAIBE) may be employed for dry etching the wafer substrate. Chlorine-based gases such as Cl2, BCl3, or SiCl4may be used to etch the wafer. Carrier gases including but not limited to Ar, O2, Ne, and N2may be introduced into the reactor chamber to increase the degree of anisotropic etching and sidewall passivation.

With reference toFIGS.16A to16C, a device structure1100includes a device layer1202deposited on a wafer surface1200. Following the wafer cleaning step, a hard mask1206is formed on the device layer1202. In an embodiment, a dielectric layer1204, such as SiO2or Si3N4, is formed on the device layer1202using appropriate deposition techniques, such as plasma-enhanced chemical vapour deposition (PECVD). The hard mask photoresist1206is then applied on the dielectric layer1204. In the photolithography step, a desired pattern is formed on the photoresist layer1206. For example, PMMA (Poly(methyl methacrylate)) may be formed on the dielectric layer1202followed by a direct e-beam lithography technique to form the openings in the PMMA1206.

FIG.16Billustrates the device structure1100with the dielectric layer1204etched to create openings on the device layer1202for subsequent wafer etching. A dry etch method with fluorine chemistry may be employed to selectively etch the dielectric layer1204. Carrier gases, including but not limited to N2, Ar, or O2, may be introduced to control the degree of anisotropic etching. Gas flow rate and mixture ratio, type of carrier gases, RF and DC powers, as well as substrate temperature may be adjusted to achieve the desired etching rate and high degree of anisotropy.

FIG.16Cillustrates mesa structures1208and1210after the wafer device layer1202etching step. In one embodiment, mesa structures1208with straight sidewalls (e.g., perpendicular to the upper surface of the substrate1200) may be formed. In another embodiment, mesa structures1210with sloped side walls (e.g., forming an acute angle with the upper surface of the substrate1200) may be formed. The gas mixture ratio, type of gases in the reactor, and relevant etching conditions may be adjusted in order to modify the slope of the sidewalls. Depending on the desired mesa structure1208and1210, a straight, positive, or negative slope sidewall may be formed. In an embodiment, sidewall passivation during the etching step may be used to create a desired sidewall profile. In addition, a cleaning step may be used to remove the passivation layer or the native oxide from the sidewall. Cleaning may be done using acetone or isopropyl alcohol followed by surface treatment using (NH4)2and/or NH4OH.

In an embodiment, an MIS structure may be formed after the mesa structure formation ofFIGS.16A to16C. With reference toFIGS.17and18A to18D, a process flow1000B to form an MIS structure includes process steps1114and1116, in which dielectric and metal layers1402and1404are deposited on mesa structures (e.g.,1208and1210) to form MIS structures. Following the deposition of the dielectric layer1402, in process1116, a metal film1404is deposited on the dielectric layer1402using a variety of methods, such as thermal evaporation, e-beam deposition, and sputtering (FIG.18A). In process step1118, a desired pattern is formed on the wafer using a photolithography step. In step1120, the metal layer1404is etched using dry or wet etching to form an opening on the top side of the mesa structure above the dielectric layer1402(FIG.18B). In step1122, a photolithography step may be used to define the dielectric etch area. In another embodiment, the etched metal layer1404may be used as a mask to etch the dielectric layer1402(FIG.18C). In step1126, a second dielectric layer1406may be deposited on the metal interlayer1404(FIG.18D). In step1128, an ohmic (e.g., p-type) contact1408may be deposited on the micro device mesa structures1208and1210, as shown inFIG.18E. In process step1130, a thick metal1410is deposited on the contact1408for subsequent bonding of the mesa structures1208and1210to a temporary substrate in wafer lift-off process steps from the native substrate.

FIG.18Ashows the dielectric layer1402and the metal layer1404deposited on the mesa structure to form an MIS structure. A variety of dielectric layers1402may be used, which include but are not limited to Si3N4and oxides such as SiO2, HfO2, Al2O3, SrTiO3, Al-doped TiO2, LaLuO3, SrRuO3, HfAlO, and HfTiOx. The thickness of the dielectric layer1402may be a few nanometers or up to a micrometer. A variety of methods, such as CVD, PVD, or e-beam deposition, may be used to deposit the dielectric layer1402. In an embodiment, a high-k oxide dielectric layer1402may be deposited using an atomic layer deposition (ALD) method. ALD enables very thin and high-K dielectric layers to be formed on the wafer. During ALD deposition of the dielectric oxide layer, precursors are introduced in the reaction chamber sequentially to form a thin insulator layer. Metal precursors for the metal layer1404include halides, alkyls and alkoxides, and beta-diketonates. Oxygen gas may be provided using water, ozone, or O2. Depending on the process chemistry, dielectric film deposition may be done at room temperature or at an elevated temperature. Deposition of Al2O3may also be done using trimethylaluminum (TMA) and water precursors. For HfO2ALD deposition, both HfCl4and H2O precursors may be used. Metal electrodes1410serve as biasing contacts for electric field modulation in the device. Metal contacts1408include but are not limited to Ti, Cr, Al, Ni, Au, or a metal stack layer.

FIG.18Bshows the wafer with a pattern formed using a photolithography step.FIG.18Cillustrates the wafer with a dry-etched dielectric layer1402dry-etched (e.g., using fluorine chemistry). An etch stop for etching the dielectric layer1402may be the top surface of the mesa structure1208and1210. As illustrated inFIG.18D, the second dielectric layer1406may be deposited on the metal interlayer1404for subsequent p-contact deposition in order to prevent shorting with the device functional electrodes1408and1410. Subsequently, the second dielectric layer1406on top of the mesa structure may be etched to create an opening on the top surface of the mesa structures.

With reference toFIG.18E, the ohmic (e.g., p-type) contact1408may then be deposited on the mesa structure to enable power from external electrical power sources to be input to the micro devices. The contact1408may be deposited using thermal evaporation, sputtering, or e-beam evaporation. Au alloys such as Au/Zn/Au, AuBe, Ti/Pt/Au, Pd/Pt/Au/Pd, Zn/Pd/Pt/Au, or Pd/Zn/Pd/Au may also be used for the contact1408. The subsequent patterning step removes metal from unwanted areas allowing the contact1408to be formed only on the top surface of the mesa structures. A thick metal1410may be deposited on the contact1408to subsequently bond the mesa structures to the temporary substrate during the wafer lift-off process steps from the native substrate.

The scope of this invention is not limited to LEDs. One can use these methods to define the active area of any vertical device. Different methods, such as laser lift-off (LLO), lapping, or wet/dry etching may be used to transfer micro devices from one substrate to another. Micro devices may be first transferred to another substrate from a growth substrate and then transferred to the system substrate. The present devices are further not limited to any particular substrate. Mentioned methods may be applied on either the n-type or p-type layer. For the example LED structures above, n-type and p-type layer positions should not limit the scope of the invention.

Although an MIS structure was disclosed in this document as the method to manipulate the electric field in the micro device to manipulate the vertical current flow, one can implement other structures and methods for this purpose. In an embodiment, electric field modulation may be done using a floating gate as a charge storage layer or conductive layer.FIG.19shows an exemplary embodiment of a micro device1500with a floating gate structure. The structure comprises a floating gate1514that may be charged with different methods to bias the MIS structure. One method is using a light source. Another method is using a control gate1512that is isolated with a dielectric layer1516from the floating gate1514. The biasing control gate1512enables charges to be stored in the floating gate1514. Stored charges in the floating gate1514manipulate the electric field in the device. When the micro device1500is biased through the functional electrodes1502and1504, the current flows vertically which results in the generation of light. The manipulated electric field in the micro device1500limits lateral current flow, resulting in enhanced light generation.

FIG.20illustrates a schematic structure of the micro device1500with a floating gate charge storage layer1514. The illustrated micro device1500includes angled sidewalls as an example, but the micro device1500may include different (e.g., vertically, negatively, and positively) angled sidewall. First, a thin dielectric layer1516is formed on the micro device1500. The thickness of dielectric layer1516may be between 5 nm to 10 nm to enable quantum mechanical tunneling of charges through the dielectric layer1516. Oxide or nitride based dielectric materials may be used to form the thin dielectric layer1516, including but not limited to HfO2, Al2O3, SiO2, and Si3N4. The floating gate1514may be formed on the thin dielectric layer1516. The floating gate1514may be formed from thin polysilicon or a metal layer as a charge storage layer. In another embodiment, the floating gate1514may be replaced with dielectric material to form a charge trapping layer. The dielectric in the floating gate1514may be the same as the thin dielectric1516or a different layer. The dielectric layer of the floating gate1514may be charged by different techniques such as implantation. The dielectric materials include but are not limited to HfO2, Al2O3, HfAlO, Ta2O5, Y2O3, SiO2, Tb2O3, SrTiO3, and Si3N4or a combination of different dielectric materials to form a stack of layers that may be used for the charge trapping layer. In another embodiment, semiconductor or metal nanocrystals, or graphene may be used as the charge trapping layer. Nanocrystals including but not limited to Au, Pt, W, Ag, Co, Ni, Al, Mo, Si, and Ge may be used for charging trap sites. The nanocrystals create isolated trap sites. This in turn reduces the chance of charge leakage due to the presence of defects on the thin dielectric layer1516. In addition, if charges leak from one nanocrystal, it will not affect the adjacent sites as they are isolated from each other. On top of the floating gate or charge trapping layer1514, a second, thick dielectric layer1518isolates the floating gate1514in order to prevent charge leakage. The second dielectric layer1518may be made of various dielectric materials, including but not limited to HfO2, Al2O3, HfAlO, Ta2O5, Y2O3, SiO2, Tb2O3, or SrTiO3with a thickness of 10 nm to 90 nm. On top of the second dielectric layer1518, a control gate1512is provided, which is responsible for floating gate1514charging. The control gate1512may be comprised of one or more conductive layers, such as metal, transparent conductive oxides, or polymers.

With reference toFIG.21, a process flow2000to develop a floating gate structure on the sidewalls of a micro device1500includes a first step1600to form the micro devices1500(e.g., as in any of the methods hereinbefore described). During step1600, either the micro devices1500are formed by patterning or by selective growth. During step1602the devices1500are transferred to a temporary or system substrate. During step1604, the thin dielectric layer1516is formed on the micro device1500. In step1606, the floating gate or charge trapping layer1514is formed on the thin dielectric layer1516. During step1608, the second, thick isolation dielectric layer1518is formed on the floating gate1514. In step1610, the control gate1512is formed on the thick dielectric layer1518. In step1612, a protective layer is formed on the structure. The order of these steps in these processes may be changed without affecting the final results. Also, each step may be a combination of a few smaller steps. For example, the structure may be formed before transferring the micro device1500from the donor substrate to the acceptor substrate. In another embodiment, parts of the floating gate structure may be formed before the micro device transfer process and the floating gate structure may be completed after the transfer step. In another embodiment, the entire floating gate structure may be formed after the micro device transfer step.

Accordingly, a process of forming a micro device with a floating gate or charge trapping structure, comprises forming the micro devices including a functional electrode; and forming a first dielectric layer or a change trapping layer on the first sidewall of the micro device.

In addition, the process may include forming a floating gate layer or a charge trapping layer on the first dielectric layer.

In addition, the process may include forming a second dielectric layer on the floating gate or charge trapping layer.

In addition, the process may include forming a control gate on the second dielectric layer.

An alternative embodiment of this process, wherein the first dielectric layer may be between 5 nm to 10 nm thick to enable quantum mechanical tunneling of charges therethrough.

An alternative embodiment of the process, wherein the second dielectric layer may be between 10 and 90 nm thick to isolate the floating gate in order to prevent charge leakage.

An alternative embodiment of the process, wherein the floating gate may be comprised of polysilicon or a metal layer as a charge storage layer.

An alternative embodiment of the process, wherein the charge trapping layer comprises semiconductor nanocrystals, metal nanocrystals, or graphene.

An alternative embodiment of the process, wherein the nanocrystals may be selected from the group consisting of Au, Pt, W, Ag, Co, Ni, Al, Si, and Ge.

An alternative embodiment of the process, further comprising biasing the control gate and the functional electrodes to generate an electric field to enable charges to be injected from a charge transport layer in the micro device into the floating gate through the thin dielectric layer.

An alternative embodiment of the process, wherein the charge injection comprises Fowler-Nordheim tunneling or a hot electron injection mechanism.

An alternative embodiment of the process, wherein the charge injection may be conducted by photoexcitation of the charge transport layer.

An alternative embodiment of the process, wherein the charge injection comprises exposing the micro device to ultraviolet light resulting in high energetic charges that overcome a potential barrier between the charge transport layer and the first dielectric layer.

An alternative embodiment of the process, wherein the floating gate or charge trap layer comprises a combination of two different dielectric layers.

In an alternate embodiment, a first electrode contact extends from a bottom contact layer of the micro device on one side of the micro device; a second electrode contact extends upwardly from a top contact layer of the micro device; and a third electrode contact extends upwardly from the floating gate on another side of the micro device.

In an alternate embodiment, the first and third electrode contacts extend upward from the same side of the micro device.

In an alternate embodiment, the first and third electrode contacts extend upwardly from an opposite side of the micro device.

In an alternate embodiment, the first and second electrode contacts extend outwardly from opposite top and bottom surfaces of the micro device.

Accordingly, another process of forming a micro device with a floating gate or charge trapping structure comprises:

forming the micro devices including a functional electrode; and

forming a first dielectric layer or a charge trapping layer on the first sidewall of the micro device.

In addition, the process may include charging the first dielectric layer.

The process may include forming a second dielectric layer on the charged first dielectric layer.

An alternative embodiment of the process, wherein the step of charging the first dielectric layer comprises ion bombardment to create fixed unneutralized charges on a surface of the first dielectric layer.

An alternative embodiment of the process, wherein the ions are selected from the group consisting of Ba, Sr, I, Br, and Cl.

An alternative embodiment of the process, further comprising implanting semiconductor ions in the first semiconductor layer to form a charge trap layer.

An alternative embodiment of the process, wherein the semiconductor ions may be selected from the group consisting of Si+ and Ge+.

An alternative embodiment of the process, further comprising annealing the first dielectric layer to cure stress on the dielectric layer after ion bombardment, and also enable diffusion of ions into the first dielectric layer.

Accordingly, another process of forming a micro device with enhanced sidewalls comprises forming the micro devices including a functional electrode; and creating an intrinsic charges interface at the sidewalls by depositing semiconductor layers on a first sidewall with a different band diagram compared to the sidewalls.

Referring toFIG.22, a floating gate or charge trapping layer1714may be charged by employing a variety of methods. In one embodiment, a control gate1706and one of the functional electrodes1702or1704are biased so that a generated electric field allows charges1708to be injected from the highly doped charge transport layer in micro device1700into the floating gate1714through the thin dielectric layer1716. Charge injection may be Fowler-nordheim tunneling or a hot electron injection mechanism. For hot electron injection, charge injection may be done by applying high voltage bias so that energetic charges can overcome the potential barrier between the charge transport layer and the thin dielectric layer1716. In another embodiment, charge injection may be done by photoexcitation of the charge transport layer. In this case, the device1700may be exposed to ultraviolet light, resulting in high energetic charges that can overcome the potential barrier between the charge transport layer and the thin dielectric layer1714.

In another embodiment illustrated inFIG.23, a floating gate or charge trap layer1810formed on the first, thin dielectric layer1816may be a combination of two different dielectric layers. A biasing control gate1806, enables charging an intermediate dielectric layer1808. The charged intermediate dielectric layer1808creates image charges opposite to the floating gate or charge trap layer1810. With this technique, the floating gate1810may be controlled to be positive or negative to allow electric field propagation direction to inward or outward from the micro device sidewall.

In another embodiment, illustrated inFIG.24, an electric field modulation structure may be formed without using a control gate. A dielectric layer1908is formed on the sidewall of a micro device1900. The formed dielectric layer1908may be permanently charged by ion bombardment or implantation to form a charge layer1906. The charge layer1906may be at either side or in the middle of the dielectric layer1908. Dielectric materials including but not limited to HfO2, Al2O3, HfAlO, Ta2O5, Y2O3, SiO2, Tb2O3, SrTiO3, and Si3N4or a combination of different dielectric materials to form a stack of layers may be used for charge trapping layer1906. Ion bombardment creates fixed unneutralized charges in the charged layer1906, hence creating an electric field in the body of the semiconductor. The ions may be positive or negative, such as barium and strontium, iodine, bromine, or chlorine. In addition, semiconductor ions such as Si+ and Ge+ may be implanted to form a charge trap layer. Following the ion implantation, the dielectric layer1906may be annealed to cure stress on the dielectric layer1906after ion bombardment, and also enable diffusion of ions into the dielectric layer1908. Following the ion implantation and subsequent annealing, a thick dielectric layer1908is formed as an isolation and protective layer. The fixed charges in the dielectric layer1908manipulate the electric field at the semiconductor/dielectric layer interface to pull away charges in the semiconductor from the interface toward the middle of device1900to limit lateral current flow. Here, the ion/charge implantation may be done directly in the dielectric layer1908. A barrier layer may be used between the dielectric layer1908and the micro device1900to protect the micro device1900from the high energy ion particles during the creation of the charging layer1906.

With reference toFIGS.25and26, in another embodiment related to biasing an MIS structure2016on a micro device2010, either contact/electrode2012or2014of a micro device2010may be extended over the MIS gate (the gate may be an actual layer, such as a conductive layer, or only a position in a dielectric or other material to hold the charge) while a dielectric layer2018aseparates the MIS biasing gate and the micro device electrode2012.

With reference toFIG.25A, the contacts2012and2014of the micro device2010may extend upwardly. To create an MIS structure2016(i.e. including a gate, such as a conductive layer) and a dielectric layer, for such devices, an MIS contact/gate pad2022to the MIS gate also extends upwardly. This structure may simplify the process of integrating the micro devices2010into a receiver substrate as similar bonding or coupling processes may be used for both MIS contact2022and the micro device contacts2012and2014. To avoid a short circuit between the micro device2010layers and the MIS2016gate, a dielectric layer2020ais deposited. The dielectric layer2020amay be part of the MIS structure or a separate dielectric layer deposited independently. In addition, to avoid shorts during the bonding and/or integration of the micro device2010into a system (i.e., receiver) substrate, one or more dielectric layers2018aand2018bmay cover the MIS structure2016. To create the contact to the micro device2010for one of the electrodes2012and2014, the dielectric layer2020bmay be removed or opened (e.g., etched). The dielectric layer2020bmay be the same as any one or more of dielectric layers2018b,2020a, and2018a, or a separate layer altogether. The space between the contacts2014,2022, the MIS structure2016and the micro device2010may be filled with a different type of materials, such as polymer or dielectrics. The filler may be the same as the dielectric layers2018aand2018b, or different. The position of the MIS contact/gate pad2022and the micro device contact2014may be different relative to the micro device2010or positioned symmetrically on either side thereof. In another embodiment, the MIS structure may be formed using a charged layer and therefore no MIS contact2022will be needed.

In another embodiment presented inFIG.25B, the contacts2012and2014on the microdevice2010electrodes are on the same surface. To create an MIS structure2016for such devices, one can put the contact2022to the MIS gate on the same surface as the micro device contacts. This structure can simplify the process of integrating said micro devices into a

receiver substrate as similar bonding or coupling processes can be used for both the MIS contact and the micro device contacts. In this structure, the gate pad2022is deposited on top of the vertical device structure. Therefore, at least one of the MIS layers is extended above the top of the device to provide space for the pads. In addition, to avoid shorts during the bonding and/or integration of the micro device into the system (i.e., receiver) substrate, a dielectric layer2018aand2018bcovers the MIS structure. To create a contact2014to the micro device for one of the electrodes, the dielectric layer2020bcan be removed or opened. The dielectric layer2020bcan be the same as either dielectric layers2018aor2018b. The space between the contacts2014,2022, and the MIS2016(or micro device2010) can be filled with different types of materials such as polymer or dielectrics. This filler can be the same as the2018aand2018bdielectric layer.

In an embodiment presented inFIG.25C, a micro device consists of a mesa structure2010, contacts2012,2014, and2022, and the MIS structure2016. The contacts2012and2014of the micro device2010electrodes are on the same surface. This structure can simplify the process of integrating said micro devices into a receiver substrate as similar bonding or coupling processes can be used for both the MIS contact and the micro device contacts. To avoid the short between the micro device2010layers and the MIS2012gate, a dielectric layer2020ais deposited. The connection2014-bto a mesa layer is extended by a trace2014-afor the contact2014and the MIS structure2016.

In another embodiment, shown inFIG.25D, there is no MIS underneath the trace transferring the contact2012. Here, the trace2014-acan be developed by patterning the same layer as the metal (conductive) layer of the MIS2016.

FIG.25Eshows another embodiment where the contact for MIS electrode2022and one of the device contacts (or pads)2012is on the first side of the device2010and at least one contact2014for the device is on a side different from the first side where device2010is located.

FIG.25Fshows another embodiment where the contact for MIS electrode2022and one of the device contacts (or pads)2012is on the first side of the device2010and at least one contact2014for the device is on a side different from the first side where device2010is located. Here, the MIS contact2022is on top of the vertical device.

It is possible for all embodiments that the MIS contact2022is partially sitting on top of the device, on the side of the device, or on the etched layers.

The dielectric layers in different embodiments can be stacks of different layers. In one case, a thin ALD layer can be used first and then a PECVD deposited dielectric (e.g., SiN) layer can be used to get better coverage and avoid shorts at the edges and corners. Also, the biasing can be created or developed through band engineering. Using different layers with different band structure can create an intrinsic potential that can bias the edge (i.e., side walls or top and bottom surface) of the micro devices. Also, other biasing and integration methods presented here for MIS structures can be used with said micro device structure with contact to the electrode on the same surface.

The position of the MIS contact2022and the micro device contact2014can be different relative to the micro device2010.

FIG.26Aillustrates a top view of the micro device2010with the MIS contact2022and the micro device bottom contact2014located on opposite sides thereof.

FIG.26B, the MIS contact2022and the micro device bottom contact2014are located on the same side of the micro device2010. In this case, the dielectric layers2020aand2020bmay be the same layer2020.

FIG.26C, the MIS contact2022and the micro device bottom contact2014are located on two neighboring sides of the micro device2010. The micro device2010may have other cross-sectional shapes, such as a circle, and the aforementioned positions may be modified to accommodate the micro device shape. The dielectrics2018and2020may be a stack of different layers, and the conductive (gate) layers may be metal, any other conductive material, or a stack of different materials.

FIG.26Dshows an exemplary top view of a micro device2010with the MIS contact2022, while the micro device contact2014is located on a different part of the device. Here, the conductive layer2016-aand the dielectric layer2016-bform the MIS structure. Here, the dielectric layer2018covers at least where the trace2014-apasses. The MIS structure can be underneath trace2014-aor outside of that area. If there is no MIS underneath the trace2014, the dielectric layer2018can be the same as the MIS dielectric layer2016-b. In this case, the trace2014can also be the same as the conductive layer2016-aof the MIS structure.

FIG.26Eshows another embodiment where the contact for the MIS electrode2022and the devices2014and2012are in one direction.

The following embodiments, illustrated inFIGS.27to30, include arrays of optoelectronic devices, in which the pixelation may be developed by creating pillars of the ohmic contact layer(s)/conductive layer and bonding an array of separated pads to the ohmic contact layer/conductive layer. The pillars may be smaller than the pads. Some of the semiconductor layers after the ohmic layer may be patterned. In some embodiments, the patterning of the semiconductor layers follows the same pattern as the pillars of the ohmic layer.

With reference toFIG.27A, different conductive and active layers2022are deposited on top of a device substrate2020, followed by other conductive or blocking layers2024. The first conductive layer2024may be p-type, n-type, or intrinsic. To create pixelated devices, the conductivity of the first conductive layer(s)2024may modulate into pillars of higher performance electrical connectivity. The pillars may be smaller (e.g., ½ to 1/10 the pixel size, such as pad2032or smaller) whereby at least 1 to 10, preferably 2 to 8, and more preferably more than 4, pillars contact each contact pad2032. In one embodiment, the pillars are between 1 nm to 100 nm cubes. In one approach, the first conductive layer(s)2024or part of the first conductive layer(s) may be patterned (e.g., through lithography, stamping, and other methods). In another embodiment, a very thin pillar layer2026is deposited on the first conductive layer2024, and then ideally annealed. The annealing process may be thermal or optical or a combination thereof. The annealing may be done in ambient condition, vacuum, or with a different gas. In one embodiment, the pillar layer2026may comprise ITO, gold, silver, ZnO, Ni, or other materials. The pillar layer2026may be deposited by various means, such as e-beam, thermal, or sputtering. After creating the pillars2026-i, a pad substrate2030, which includes pads2032, and may include driving circuitry, is bonded to the surface with the pillars2026-i. The bonding may be thermal compression, thermal/optical curing adhesive, or eutectic. In one embodiment, the first conductive layer2024may comprise varied materials. In an embodiment, part of the first conductive layer2024may be deposited to include the pillar layer2026, and another part is part of the bonding pads2032. For example, in the case of GaN LEDs the p-ohmic contact is comprised of Ni and Au. In one case, layer2026may include both Ni and Au. In another case, the layer2026comprises only Ni and the pads2032(e.g., include an Au layer at the interface). After the bonding, the pressure and heat applied to the samples will assist in diffusing them into separate layers and create an improved ohmic contact.

The space between the pads2032may be filled with diverse types of filler to enhance the reliability of the bonding process. The filler may include materials such as polyamide or thermally/optically annealed adhesives.

Subsequently, the device substrate2020may be removed, and a second contact layer of the device layer2022may be exposed. The second contact layer may then undergo any of the aforementioned process steps (e.g.,FIGS.8to10) to provide top contacts (e.g., an array of top contact pads and/or a common electrode). Alternatively, the device substrate2020is utilized as the common electrode.

FIG.28illustrates a micro device structure in which different conductive and active layers2022are deposited on top of the substrate2020followed by other conductive or blocking layers2024. The first conductive layer2024may be p-type, n-type, or intrinsic. To create pixelated devices, the conductivity of the first conductive layer(s)2024are modulated (e.g., formed) into separate pillars of higher performance electrical connectivity. The pillars may be smaller than (e.g., 1/10 or smaller, the pixel size such as pad2032) whereby at least 2 to 10, preferably 4 to 8, pillar contact each contact pad2032. In a preferred embodiment, the pillars are between 1 nm to 100 nm wide. In one embodiment, the first conductive layer2024or part of the first conductive layer2024may be patterned (e.g., through lithography, stamping, and other methods). In another embodiment, a very thin pillar layer2026may be deposited on top of the first conductive layer2024and annealed. The annealing process may be thermal, optical, or a combination thereof. The annealing may be done in ambient condition, vacuum, or a different gas. In one embodiment, the pillar layer2026may be comprised of any one or more of ITO, gold, silver, ZnO, Ni, or other metallic or conductive materials. The pillar layer2026may be deposited by a few different means, such as e-beam, thermal, or sputtering. In addition to the formation of pillars2026-i, the top conductive layer2024may also be separated (e.g., etched) into a distinct set of conductive layer pillars2024-i. The pillars2026-imay act as a hard mask or a new mask may be used to etch the top conductive layer2024and form the conductive layer pillars2024-i. For example, in the case of GaN, the pillars2026-imay be comprised of Ni, which is a natural hard mask used to etch the first conductive (e.g., p-GaN) layer2024, to form conductive layer pillars2024-i(e.g., using an inductively coupled plasma (ICP) etcher). The first conductive layer(s)2024may be etched partially or fully. For example, the top conductive layer(s)2024may include both a p-layer and a blocking layer. In which case, the p-layer may be etched, and the blocking layer may be left alone.

After creating the pillars2026-i, the substrate2030which includes pads2032, and may include driving circuitry, is bonded to the surface with the pillars2026-l(FIG.28D). The bonding can be thermal compression, thermal/optical curing adhesive, or eutectic. In one embodiment, the first conductive layer2024may contain varied materials. In this case, part of the first conductive layer2024may be deposited as the pillar layer2026and another part may be part of the bonding pads2032. For example, for GaN LEDs, the pillar layer2026(e.g., p-ohmic contact) may comprise one or more of Ni and Au. In one embodiment, the pillar layer2026may comprise both Ni and Au. In another embodiment, the pillar layer2026may comprise only Ni, and the pads2032include an Au layer at the interface. After the bonding, the pressure and heat applied to the samples will assist in diffusing the separate layers and creating an improved ohmic contact.

With reference toFIG.28D, in another embodiment, there may be the array of pillars comprising redundant pillars that are not bonded to the array of pads. For the redundant array of pillars, there may be provided a fixed voltage2032-2for enhancing the performance of the displays (e.g. isolating the pixels) or it can be coupled to a circuit for using the redundant pillars as a different function. In one case, the redundant pillars can be used as sensors. The sensor can be either an image sensor or motion sensor. In one case, the sensor can detect the eye (or hand) movement. In another case, the light from the other pillars' pixels reflect from the eye and can be used to detect the eye movement. In one case, another light source can be used to eliminate eyes and the sensor detects the reflection.

Subsequently, the device substrate2020may be removed, and a second contact layer of the device layer2022may be exposed. The second contact layer may then undergo any of the aforementioned process steps (e.g.,FIGS.8to10) to provide top contacts (e.g., an array of top contact pads and/or a common electrode). Alternatively, the device substrate2020is utilized as the common electrode.

With reference toFIG.29, an alternative method includes all of the aforementioned steps fromFIGS.27and28, and further includes an extra passivation layer2028deposited between the pillars2024-i, on the sidewall of the pillars2024-i, or on top of the pillars2024-i. The passivation layer2028may comprise an ALD (e.g., dielectric) layer, a PECVD (e.g., dielectric), layer, or a polymer. The area between the pads2032may be filled with different fillers to enhance the reliability of the bonding process. The fillers may be comprised of a variety of different materials, such as polyamide, or thermally/optically annealed adhesives.

Subsequently, the device substrate2020may be removed, and a second contact layer of the device layers2022may be exposed. The second contact layer may then undergo any of the aforementioned process steps (e.g.,FIGS.8to10) to provide top contacts (e.g., an array of top contact pads and/or a common electrode). Alternatively, the device substrate2020is utilized as the common electrode.

FIG.30illustrates an embodiment in which an extra structure (layers)2029may be developed between the first conductive layer(s)2024and the active layers of the device layers2022. The passivation layer2028-A may also be deposited after the device layers2022. The passivation layer2028-A may passivate some of the defects2029A, such as trailing dislocation. Then, the passivation layer2028-A may be either patterned (FIG.30A) or removed from the surface (FIG.30B). The first conductive layer(s)2024may be deposited after. The passivation layer2028-A may be comprised of an ALD, PECVD, organic, or polymer layer. In another embodiment, a different plasma treatment, such as nitrogen, oxygen, or hydrogen plasma, may be used to create surface passivation.

According to one embodiment, an optoelectronic device may be provided. The optoelectronic device may comprising: a pad substrate comprising an array of pads connected to a driving circuit, a device layer structure deposited on a substrate, wherein the device layer structure including a plurality of active layers and conductive layers; and a pillar layer formed on at least a part of a first conductive layer, wherein the pillar layer is patterned into array of pillars to create pixelated micro devices and wherein the array of pillars is bonded to the array of pads.

According to further embodiments, the pillars may be smaller in size than the pads.

According to yet further embodiments, at least a part of the first conductive layer may be patterned. The patterning of the first conductive layer may follow the same pattern as the patterning of the pillar layer.

According to some embodiments, the array of pillars may comprise redundant pillars that are not bonded to the array of pads. A fixed voltage may be provided to the redundant pillars or a circuit is coupled to the redundant pillars to enhance the performance of the device. The redundant pillars may comprise sensors one of: an image sensor or a motion sensor to detect a movement.

According to yet another embodiment, the method may further comprising a passivation layer deposited between the pillars, on the sidewall of the pillars or on top of the pillars. The passivation layer comprises one of an ALD layer, a PECVD layer, or a polymer. The material of the pillar layer comprises one of: ITO, gold, silver, ZnO, and Ni and a space between the pads is filled with a filler material to enhance bonding. The filler material comprises polyamide or thermally/optically annealed adhesives.

According to some embodiments, the bonding between the array of pillars and array of pads may be one of: thermal compression bonding, thermal bonding, optical bonding and eutectic bonding. A pressure or heat may further be applied between the array of pillars bonded to the array of pads to enhance bonding.

According to one embodiment, a method of fabricating an optoelectronic device comprising forming a device layer structure, including a plurality of active layers and conductive layers, on a substrate, forming a pillar layer on at least a part of a first conductive layer, wherein the pillar layer is patterned into array of pillars to create pixelated micro devices; and bonding a pad substrate comprising an array of pads connected to a driving circuit, to a top surface of the array of pillars.

According to further embodiments, the pillars are smaller in size than the pads. At least a part of the first conductive layer may be patterned. The array of pillars may comprise redundant pillars that are not bonded to the array of pads. A fixed voltage may be provided to the redundant pillars or a circuit is coupled to the redundant pillars to enhance the performance of the device and the redundant pillars may comprise sensors one of: an image sensor or a motion sensor to detect movement.

While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and are described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims.