Patent ID: 12206183

DETAILED DESCRIPTION

FIG.1shows a block diagram of a (high resolution) phase shifter100. Phase shifter100may comprise a differential quadrature hybrid splitter200(shown inFIG.2), two phase inverting variable (X-type) attenuators400(shown inFIG.4), and a differential power combiner300(shown inFIG.3). In some embodiments, phase shifter100may be fabricated entirely on a single CMOS die.

The phase shifter100may be configured to apply a phase shift to an input signal using a Cartesian phase interpolation technique. A differential input signal110may be split into an I-component signal and a Q-component signal using the differential quadrature hybrid splitter200. Amplitude scaling, either by amplification or attenuation, with or without phase inversion, may be separately applied to the I-component signal and to the Q-component signal using phase-inverting variable attenuators400to produce a scaled I-component signal and a scaled Q-component signal. The scaled component signals may be combined using differential power combiner300to produce a phase-shifted signal in reference to the differential input signal110.

In reference toFIG.2, the differential quadrature hybrid splitter200may be configured to receive an input signal210and to output (e.g., over two differential output ports) an I-component signal220and a Q-component signal230that may correspond to the input signal210. In some embodiments, the differential quadrature hybrid splitter200may be an inductive-type lumped analog of a coupled-line hybrid coupler that may have smaller footprint than a distributed hybrid coupler.

Each of the two differential output ports of the differential quadrature hybrid splitter200(e.g., I and Q) may be coupled to the input terminals (410and420) of a phase-inverting variable attenuator400of the two phase inverting variable attenuators included in phase shifter100. The output terminals (430and440) of each of the two phase inverting variable attenuators400may be coupled to a differential input port (e.g., of the two differential input ports310and320) of the differential power combiner300.

In reference toFIG.3, the differential power combiner300may be configured to combine the signals provided at its input ports (310and320) and to output a combined signal through output port330. In some embodiments, the differential power combiner300may be a lumped analog Wilkinson power combiner (e.g., as shown inFIG.3), wherein a lumped analog Wilkinson power combiner may have smaller footprint than a standard (e.g., distributed) Wilkinson power combiner.

In reference toFIG.4, the phase inverting variable attenuator400may comprise a differential input port comprising a first input terminal410and a second input terminal420, and a differential output port comprising a first output terminal430and a second output terminal440. The phase inverting variable attenuator400may comprise a first transistor M1that may be coupled to the first input terminal410and to the first output terminal430, a second transistor M2that may be coupled to the second input terminal420and to the second output terminal440, a third transistor M3that may be coupled to the first input terminal410and to the second output terminal440, and a fourth transistor M4that may be coupled to the second input terminal420and to the first output terminal430. In some embodiments, the first transistor M1, the second transistor M2, the third transistor M3and the fourth transistor M4(e.g., herein transistors M1to M4) may be Field-Effect Transistors (FET).

The phase inverting variable attenuator400may be in one of two phase states, corresponding to a 0° phase (e.g., no phase inversion) and a 1800 phase (e.g., phase inversion). In some embodiments, the phase state of the phase inverting variable attenuator400may be controlled by control voltages VC+(450) and VC−(460). The phase state of phase inverting variable attenuator400may be flipped when the control voltages VC+(450) and VC−(460) are flipped. Control voltage450may be coupled to the gate terminals of transistors M1and M2. Control voltage460may be coupled to the gate terminals of transistors M3and M4. The control voltages450and460may be coupled to the respective gate terminals of transistors M1to M4through “choke” resistors470, wherein using resistors470for said coupling may improve (e.g., reduce) an insertion loss characteristic of the phase inverting variable attenuator400, and wherein the insertion loss may result from leakage through the gate capacitances of transistors M1to M4. The source and drain terminals of transistors M1to M4may be biased at 0 Volts for at least the purpose of reducing a loss property of the phase inverting variable attenuator400, e.g., by eliminating the Body Effect and maximizing the allowed gate-source voltage (VGS).

The coupling of the control voltages VC+(450) and VC−(460) to the respective gate terminals of transistors M1to M4through resistors470may be advantageous. As described further herein, at least a phase-shifting resolution property of phase shifter100may be affected by a maximum attenuation (attenuation range) that phase inverting variable attenuator400may exhibit. Phase inverting variable attenuator400may be configured to exhibit maximum attenuation when the control voltages VC+(450) and VC−(460) may be of a same level. When the control voltages VC+(450) and VC−(460) may be of a same level, the (maximum) attenuation may be limited by signal leakage through parasitic capacitances (e.g., of transistors M1to M4). Using resistors470may enable reducing the size of transistors M1to M4while maintaining low (minimum) insertion loss, wherein reducing the size of transistors M1to M4may result in lower parasitic capacitances and higher maximum attenuation (e.g., better phase-shifting resolution).

In some embodiments, a resistance value of resistors470(e.g., RC) may be selected as high as possible for at least the purpose of reducing the insertion loss while maintaining a settling time of the control voltages450and460at the respective gates of transistors M1to M4as low as may be needed. For example, an antenna may comprise one or more phase shifters100and a steering speed property of the antenna may be limited, among other things, by a settling time of the one or more phase shifters100(that may depend on a settling time of the control voltages450and460at the respective gates of transistors M1to M4). Thus, the selection of a resistance value for resistors470may comprise considering a required steering speed property of an antenna with one or more phase shifters100and selecting the resistance value so that the steering speed property of the antenna is not limited (or acceptably limited) by a settling time of the control voltages450and460at the respective gates of transistors M1to M4.

In some embodiments, the phase-shifting resolution (θmin) of phase shifter100may be determined by the full attenuation range (R) of the phase inverting variable attenuator400, for example in accordance with the formula: θmin=2*ARCSIN(1/R), wherein ARCSIN is the trigonometric inverse sine function. For example, a phase shifter100that may comprise a phase inverting variable attenuator400configured to exhibit an attenuation range of 40 dB (e.g., 1/R=1/100) may exhibit a phase-shifting resolution of roughly 1.15 degrees. As previously described, using resistors470may improve the attenuation range of the phase inverting variable attenuator400, hence allow achieving finer phase-shifting resolution (e.g., lower values of θmin).

Let RM1to RM4denote the channel resistances of transistors M1to M4, respectively. Let Rthruand Rshntbe defined as follows:

Rthru={RM⁢1,RM⁢2,phase=0∘RM⁢3,RM⁢4,phase=180∘Rs⁢h⁢n⁢t={RM⁢3,RM⁢4,phase=0∘RM⁢1,RM⁢2,phase=180∘

It may follow from the above definition that Rthrumay always be lower than Rshnt. Neglecting parasitic resistances, the insertion loss (S21), the input return loss (S11) and the output return loss (S22) characteristics of phase inverting variable attenuator400may be calculated as follows, wherein Zo may denote the characteristic impedance of the (differential) input and output ports of the phase inverting variable attenuator400:

S2⁢1=Rs⁢h⁢n⁢t-Rthru(Rthru+Rs⁢h⁢n⁢t)2⁢S1⁢1=S2⁢2=Rthru·Rs⁢h⁢n⁢t-Z02Z0·(Rthru+Rs⁢h⁢n⁢t+Z0)+Rthru·Rs⁢h⁢n⁢t

Two observations may be derived from the above equations. First, both the insertion loss (attenuation level) (S21) and the return losses (S11and S22) characteristics of the phase inverting variable attenuator400are affected (determined) by Rthruand Rshnt. Second, if the minimum resistance values of Rthruand Rshntare limited (e.g., for at least the purpose of maintaining low parasitic capacitances), there is a tradeoff between a range of possible attenuation levels and the return loss characteristics of phase inverting variable attenuator400.

In order to enable use of an entire range of sets of attenuation levels and return loss values, the channel resistances Rthruand Rshntof transistors M1to M4may be controlled by two separate bias circuits, as shown inFIG.5. Each bias circuit of the two bias circuits500may be configured to generate a gate control voltage, e.g., Vthruor Vshnt, corresponding to a channel resistance Rthruor Rshnt, respectively. Bias circuits500may comprise two multiplexers (561and562) that may be controlled by a common control signal570and configured to route any of the gate control voltages Vthruand Vshntto transistors M1thru M4in accordance with the control signal570and the definitions of the corresponding channel resistances Rthruand Rshntas provided above. The two input terminals of each of the two multiplexers may be coupled to both gate control voltages, Vthruor Vshnt, but in opposite orders. For example, the Vthrugate control voltage may be coupled to a first input of multiplexer561and to a second input of multiplexer562, whereas the Vshntgate control voltage may be coupled to a second input of multiplexer561and to a first input of multiplexer562. Furthermore, the output terminal of multiplexer561may be coupled to provide the control voltage VC+(450) to the phase inverting variable attenuator400, and the output terminal of multiplexer562may be coupled to provide the control voltage VC−(460) to the phase inverting variable attenuator400. Thus, the phase state of phase inverting variable attenuator400may be flipped using the common control signal570.

Each bias circuit of the two bias circuits500may comprise a transistor510that may be of similar characteristics as any of the transistors M1to M4of the phase inverting variable attenuator400. In some embodiments, where transistors M1to M4may be FET transistors, transistors510may also be FET transistors of characteristics similar to those of transistors M1to M4. The bias current of each transistor510, e.g., Ithruor Ishnt, may be set using a current digital to analog converter (IDAC). In addition, the drain voltage of each transistor510may be set in accordance with a reference voltage520(Vref), for example using a control loop (540,550) that comprises an operational amplifier530. Each control loop (540,550) may be configured to maintain a gate control voltage, Vthruor Vshnt, for the respective transistor510so that:

R5⁢1⁢0=VrefID⁢A⁢C

Wherein the bias current IDACis either Ithruor Ishnt, as per the respective control loop. In some embodiments, the reference voltage520(Vref) may be set to a lowest voltage that may be supported by the operational amplifier(s)530, e.g., for at least the purpose of operating any of the transistors510at roughly the same operating conditions as those of transistors M1to M4of the phase inverting variable attenuator400. In some embodiments, the reference voltage520(Vref) may be set to approximately 100 millivolts (mV). In some embodiments, the physical gate width of transistors510may be smaller than the gate width of any of the transistors M1to M4of the phase inverting variable attenuator400for at least the purpose of reducing power consumption of transistors510.

Since Rthrumay be always lower than Rshnt, the IDAC in the “thru” control loop540may always be required to provide higher current than the IDAC in the “shnt” control loop550. To maximize an attenuation range of phase inverting variable attenuator400per given silicon area and simplify control over the bias circuits500by maintaining a same number of control bits in both IDAC devices, bias circuits500may comprise a low current IDAC for the “shnt” control loop550and a high current IDAC for the “thru” control loop540. In some embodiments, both the low current IDAC and the high current IDAC may be 5-bit IDACs.

In some embodiments, the attenuation (S21) and the return losses (S11and S22) characteristics of the phase inverting variable attenuator400may be maintained over temperature and process variations. Considering that temperature-dependent and process-dependent parasitic capacitances may be negligible, the said characteristics may be maintained as long as the reference voltage (Vref) and the bias currents (Ithruand Ishnt) remain constant.

FIG.6shows a block diagram of an example phased array antenna600and a block diagram of an example phased array antenna650. Phased array antenna600may be configured to be at least a transmitting antenna, whereas phased array antenna650may be configured to be at least a receiving antenna. In some embodiments, each of the phased array antennas600and650may be configured to use a dedicated aperture. In other embodiments, phased array antennas600and650may be configured to share a single (common) aperture. The phased array antennas600and650, whether using dedicated apertures or a common aperture, may also be configured for satellite communications in any of the Ku-band or the Ka-band. The phased array antennas600and650, whether using dedicated apertures or a common aperture, may also be configured to be used as airborne antennas.

Phased array antenna600may comprise a plurality of array elements coupled to an input port610. An input signal may be received via input port610and then split to feed each of the array elements of the plurality of array elements. Each array element of the plurality of array elements may comprise at least a (high resolution) phase shifter100, an amplifier620(e.g., a power amplifier), and a radiating (antenna) element630. The phase shifter100may be configured to apply at least a phase-shift to the signal fed to the array element, wherein the phase-shift may vary in accordance with variations in a radiation pattern of phased array antenna600. The phase-shifted signal may be amplified by amplifier620and the amplified signal may be transmitted using the radiating element630. In some embodiments, each array element of the plurality of array elements of antenna600may further comprise an up converter (not shown inFIG.6), wherein a common local oscillator signal may be provided to the up converters in all the plurality of array elements. In such embodiments, in each of the array elements, the phase shifter100may be used for applying a phase-shift to the local oscillator signal rather than to the signal fed to the array element. In such embodiments, the phase shifter100may be used at a limited number of frequencies (for example, at a single frequency) and therefore would exhibit high phase-shifting performance stability (as one of the variables affecting phase-shifting performance is reduced or eliminated).

Phased array antenna650may comprise a plurality of array elements that may be coupled to an output port680. Each antenna element of the plurality of antenna elements may comprise at least a receiving (antenna) element660, a low-noise amplifier670, and a (high resolution) phase shifter100. In each array element, a signal received by the receiving element660may be amplified by the low-noise amplifier670, and the amplified signal may be phase-shifted by the phase shifter100, wherein the phase-shift may vary in accordance with variations in a reception pattern of phased array antenna650. The phase-shifted signals from the plurality of array elements may be combined together to form an output signal that may be transmitted at output port680of phased array antenna650. In some embodiments, each array element of the plurality of array elements of antenna650may further comprise a down converter (not shown inFIG.6), wherein a common local oscillator signal may be provided to the down converters in all the plurality of array elements. In such embodiments, in each of the array elements, the phase shifter100may be used for applying a phase-shift to the local oscillator signal rather than to the amplified received signal. In such embodiments, the phase shifter100may be used at a limited number of frequencies (for example, at a single frequency) and therefore would exhibit high phase-shifting performance stability.