Patent ID: 12262609

REFERENCE SIGN LIST

1base substrate2first gate insulation layer3first signal line4second gate insulation layer5second signal line6interlayer insulation layer7source/drain metal layer8planarization layer71residual conductive material

DETAILED DESCRIPTION

In order to make the objects, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments.

For an OLED display product, in order to provide a maximum display region, a narrow bezel needs to be provided.FIG.1is a planar view of a wiring region of a display substrate, andFIG.2is a sectional view of the display substrate along line AA′ inFIG.1. As shown inFIG.2, the wiring region of the display substrate includes a base substrate1, a first gate insulation layer2on the base substrate1, a first signal line3made of a first gate metal layer on the first gate insulation layer2, a second gate insulation layer4, a second signal line5made of a second gate metal layer on the second gate insulation layer4, an interlayer insulation layer6, and an active pattern layer made of a source/drain metal layer7on the interlayer insulation layer6.

At the wiring region, the first signal lines3and the second signal lines5are parallel to each other and arranged alternately. The lines are arranged densely at the wiring region, so a distance between the first signal line3and the second signal line5is small. After the formation of the second gate insulation layer4and the interlayer insulation layer6, a plurality of grooves is formed in a surface of the interlayer insulation layer6away from the base substrate1. After the formation of the active pattern layer the source/drain metal layer7, a residual conductive material71is kept in the groove. At this time, a short circuit occurs between the adjacent signal lines, and thereby the yield of a display substrate is adversely affected. In order to ensure the yield of the display substrate, it is necessary to provide a large distance between the signal lines, but at this time, it is adverse to the narrow bezel of the display product. In addition, when a short circuit occurs between the adjacent lines at the active pattern layer, such defects as a burn of a display panel, a defective white bar for a conductive pin and poor reliability may easily occur in an aging test.

An object of the present disclosure is to provide a display substrate, a manufacturing method thereof and a display device, so as to achieve a narrow bezel of the display substrate.

The present disclosure provides in some embodiments a display substrate, which includes a display region and a wiring region surrounding the display region. The wiring region includes: a gate line layer including a plurality of signal lines parallel to each other; an insulation layer covering the gate line layer, a groove being formed in the insulation layer at a position corresponding to a gap between adjacent signal lines; a planarization layer at a side of the insulation layer away from the gate line layer; and an active pattern layer at a side of the planarization layer away from the gate line layer.

According to the embodiments of the present disclosure, the planarization layer is arranged at a side of the insulation layer away from the gate line layer, and the active pattern layer is formed on the planarization layer. Due to the formation of the active pattern layer on a flat surface, even if a distance between lines of the active pattern layer is small, there is no residual conductive material between the adjacent lines of the active pattern layer after the formation of the active pattern layer through the conductive material, so it is able to prevent the occurrence of a short circuit between the adjacent lines of the active pattern layer. In this regard, it is able to provide a small distance between the adjacent lines of the active pattern layer, thereby to achieve a narrow bezel of a display device. In addition, it is also able to prevent the occurrence of such defects as a burn of a display panel, a white bar defect of a conductive pin and poor reliability during an aging test.

In the embodiments of the present disclosure, the gate line layer and the active pattern layer are any two adjacent layers of signal lines at the wiring region.

In the embodiments of the present disclosure, as shown inFIG.3andFIG.4, the gate line layer includes: a first gate insulation layer2on a base substrate1; a first signal line3made of a first gate metal layer at a side of the first gate insulation layer2away from the base substrate1; a second gate insulation layer4at a side of the first signal line3away from the base substrate1; and a second signal line5made of a second gate metal layer at a side of the second gate insulation layer4away from the base substrate1. The first signal line3and the second signal line5are parallel to each other and arranged alternately.

The insulation layer covering the gate line layer may be an interlayer insulation layer6. As shown inFIG.3andFIG.4, a surface of the interlayer insulation layer6at a side away from the base substrate1includes grooves and a protrusion between the adjacent grooves, and the planarization layer8fills in the grooves to provide a flat surface for the active pattern layer. After the formation of the active pattern layer through the source/drain metal layer8, there is no residual source/drain metal layer7between the adjacent lines of the active pattern layer, so it is able to prevent the occurrence of the short circuit between the adjacent lines of the active pattern layer. In this way, it is able to provide a small distance between the adjacent lines of the active pattern layer, thereby to achieve the narrow bezel of the display device. In some embodiments of the present disclosure, a distance between the first signal line and the adjacent second signal line is less than 10 μm.

In the embodiments of the present disclosure, the gate line layer is made of, but not limited to, the gate metal layer, and the active pattern layer is made of, but not limited to, the source/drain metal layer, i.e., the gate line layer and active pattern layer may also be made of any other metal layers.

The planarization layer8may be made of an organic insulation material and may be formed through a coating process. A surface height of a surface of the planarization layer8away from the base substrate1is not less than a surface height of a surface of the protrusion away from the base substrate1. In other words, a maximum thickness of the planarization layer in a direction perpendicular to the base substrate is not less than a depth of the groove, i.e., the planarization layer8at least completely fills in the groove. In some embodiments of the present disclosure, as shown inFIG.3, the planarization layer8may just fill in the groove, and in other embodiments of the present disclosure, as shown inFIG.4, the surface height of the planarization layer8is greater than the surface height of the surface of the protrusion away from the base substrate1.

According to the embodiments of the present disclosure, the planarization layer is arranged at a side of the insulation layer away from the gate line layer, and the active pattern layer is formed on the planarization layer. Due to the formation of the active pattern layer on a flat surface, even if the distance between the lines of the active pattern layer is small, there is no residual conductive material between the adjacent lines of the active pattern layer after the formation of the active pattern layer through the conductive material, so it is able to prevent the occurrence of the short circuit between the adjacent lines of the active pattern layer. In this regard, it is able to provide a small distance between the adjacent lines of the active pattern layer, thereby to achieve a narrow bezel of a display device.

The present disclosure further provides in some embodiments a display panel which includes the above-mentioned display substrate.

The present disclosure further provides in some embodiments a display device which includes the above-mentioned display panel.

The display device includes, but not limited to, a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power source. It should be appreciated that, the display device may not be limited thereto, i.e., it may include more or fewer members, or some members may be combined, or the members may be arranged in different modes. In the embodiments of the present disclosure, the display device may include, but not limited to, display, mobile phone, flat-panel computer, television, wearable electronic device or navigator.

The display device may be any product or member having a display function, such as a television, a display, a digital photo frame, a mobile phone or a tablet computer. The display device further includes a flexible circuit board, a printed circuit board and a back plate.

The present disclosure further provides in some embodiments a method for manufacturing a display substrate. The display substrate includes a display region and a wiring region surrounding the display region. The method includes: forming a gate line layer at the wiring region, the gate line layer including a plurality of signal lines parallel to each other; forming an insulation layer covering the gate line layer, a groove being formed in the insulation layer at a position corresponding to a gap between the adjacent signal lines; forming a planarization layer at a side of the insulation layer away from the gate line layer; and forming an active pattern layer at a side of the planarization layer away from the gate line layer.

According to the embodiments of the present disclosure, the planarization layer is arranged at a side of the insulation layer away from the gate line layer, and the active pattern layer is formed on the planarization layer. Due to the formation of the active pattern layer on a flat surface, even if a distance between lines of the active pattern layer is small, there is no residual conductive material between the adjacent lines of the active pattern layer after the formation of the active pattern layer through the conductive material, so it is able to prevent the occurrence of a short circuit between the adjacent lines of the active pattern layer. In this regard, it is able to provide a small distance between the adjacent lines of the active pattern layer, thereby to achieve a narrow bezel of a display device. In addition, it is also able to prevent the occurrence of such defects as a burn of a display panel, a white bar defect of a conductive pin and poor reliability during an aging test.

In the embodiments of the present disclosure, the gate line layer and the active pattern layer are any two adjacent layers of signal lines at the wiring region.

In some embodiments of the present disclosure, as shown inFIG.3andFIG.4, the forming the gate line layer includes the following steps.

At first, the first gate insulation layer2is formed on the base substrate1. The base substrate1is a glass substrate or a quartz substrate. To be specific, the first gate insulation layer2with a thickness of 500 Å to 5000 Å is deposited on the base substrate1through a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the first gate insulation layer2is made of an oxide, a nitride, or an oxynitride.

Next, the first signal lines3are formed through a first gate metal layer at a side of the first gate insulation layer away from the base substrate. To be specific, the first gate metal layer with a thickness of about 500 Å to 4000 Å is deposited through sputtering or thermal evaporation, and the first gate material layer may be made of Cuprum (Cu), Aluminium (Al), Argentum (Ag), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Nickel (Ni), Manganese (Mn), Titanium (Ti), Tantalum (Ta), Tungsten (W), or an alloy thereof. The first gate metal layer may have a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, or Mo\Al\Mo. A photoresist is coated on the first gate metal layer, and exposed through a mask to form a photoresist reserved region corresponding to a region where a pattern of the first signal lines3is located, and a photoresist unreserved region corresponding to a region other than the pattern. Next, a developing process is performed so as to completely remove the photoresist at the photoresist unreserved region and maintain a thickness of the photoresist thickness at the photoresist reserved region. Then, the first gate metal layer at the photoresist unreserved region is fully etched through an etching process, and the remaining photoresist is removed, so as to form the pattern of the first signal line3.

Next, the second gate insulation layer is formed at a side of the first signal line3away from the base substrate1. To be specific, the second gate insulation layer4with a thickness of 500 Å to 5000 Å is deposited on the base substrate1through a PECVD method, and the second gate insulation layer4may be made of an oxide, a nitride, or an oxynitride.

Finally, the second signal line5is formed through a second gate metal layer at a side of the second gate insulation layer away from the base substrate1. The first signal line3and the second signal line5are parallel to each other and arranged alternately. To be specific, the second gate metal layer with a thickness of about 500 Å to 4000 Å is deposited through sputtering or thermal evaporation, and the second gate material layer may be made of Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W or an alloy thereof. The second gate metal layer may have a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, or Mo\Al\Mo. Next, a photoresist is coated on the second gate metal layer, and exposed through a mask to form a photoresist reserved region corresponding to a region where a pattern of the second signal lines5is arranged, and a photoresist unreserved region corresponding to a region other than the pattern. Next, a developing process is performed, so as to completely remove the photoresist at the photoresist unreserved region, and maintain a thickness of the photoresist thickness at the photoresist reserved region. Then, the second gate metal layer at the photoresist unreserved region is fully etched through an etching process, and the remaining photoresist is removed, so as to form the pattern of the second signal lines5.

In the embodiments of the present disclosure, the gate line layer is made of, but not limited to, the gate metal layer, and the active pattern layer is made of, but not limited to, the source/drain metal layer, i.e., the gate line layer and active pattern layer may also be made of any other metal layers.

In some embodiments of the present disclosure, the forming the planarization layer include coating an organic material on a surface of the insulation layer away from the gate line layer, and curing the organic material to form the planarization layer. The insulation layer includes the grooves and a protrusion between the adjacent grooves, and a maximum thickness of the planarization layer in a direction perpendicular to the base substrate is not less than a depth of the groove.

The insulation layer covering the gate line layer may be the interlayer insulation layer6. As shown inFIG.3andFIG.4, a surface of the interlayer insulation layer6at a side away from the base substrate1includes grooves and a protrusion between the adjacent grooves, and the planarization layer8fills in the grooves to provide a flat surface for the active pattern layer. After the formation of the active pattern layer through the source/drain metal layer8, there is no residual source/drain metal layer7between the adjacent lines of the active pattern layer, so it is able to prevent the occurrence of the short circuit between the adjacent lines of the active pattern layer. In this way, it is able to provide a small distance between the adjacent lines of the active pattern layer, thereby to achieve the narrow bezel of the display device. In some embodiments of the present disclosure, a distance between the first signal line and the adjacent second signal line is less than 10 μm.

In some embodiments of the present disclosure, as shown inFIG.3, the planarization layer8may just fill in the groove, and in other embodiments of the present disclosure, as shown inFIG.4, the surface height of the planarization layer8is greater than the surface height of the surface of the protrusion away from the base substrate1. In other words, a maximum thickness of the planarization layer8in a direction perpendicular to the base substrate1is not less than a depth of the groove, i.e., the planarization layer8at least completely fills in the groove.

In the embodiments of the present disclosure, the order of the steps is not limited to the serial numbers thereof. For a person skilled in the art, any change in the order of the steps shall also fall within the scope of the present disclosure if without any creative effort.

It should be further appreciated that, the above embodiments have been described in a progressive manner, and the same or similar contents in the embodiments have not been repeated, i.e., each embodiment has merely focused on the difference from the others. Especially, the method embodiments are substantially similar to the product embodiments, and thus have been described in a simple manner.

Unless otherwise defined, any technical or scientific term used herein shall have the common meaning understood by a person of ordinary skills. Such words as “first” and “second” used in the specification and claims are merely used to differentiate different components rather than to represent any order, number or importance. Similarly, such words as “one” or “one of” are merely used to represent the existence of at least one member, rather than to limit the number thereof. Such words as “include” or “including” intends to indicate that an element or object before the word contains an element or object or equivalents thereof listed after the word, without excluding any other element or object. Such words as “connect/connected to” or “couple/coupled to” may include electrical connection, direct or indirect, rather than to be limited to physical or mechanical connection. Such words as “on”, “under”, “left” and “right” are merely used to represent relative position relationship, and when an absolute position of the object is changed, the relative position relationship will be changed too.

It should be appreciated that, in the case that such an element as layer, film, region or substrate is arranged “on” or “under” another element, it may be directly arranged “on” or “under” the other element, or an intermediate element may be arranged therebetween.

In the above description, the features, structures, materials or characteristics may be combined in any embodiment or embodiments in an appropriate manner.

The above embodiments are for illustrative purposes only, but the present disclosure is not limited thereto. Obviously, a person skilled in the art may make further modifications and improvements without departing from the spirit of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.