Patent ID: 12243872

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIGS.1-33Eshow exemplary sequential processes for manufacturing a semiconductor device structure100, in accordance with some embodiments. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.1-33Eand some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIGS.1-16are perspective views of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. As shown inFIG.1, a stack of semiconductor layers104is formed over a substrate101. The substrate101may be a semiconductor substrate. In some embodiments, the substrate101includes a single crystalline semiconductor layer on at least the surface of the substrate101. The substrate101may include a single crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In this embodiment, the substrate101is made of Si. In some embodiments, the substrate101is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxide.

The substrate101may include one or more buffer layers (not shown) on the surface of the substrate101. The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain (S/D) regions to be grown on the substrate101. The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, germanium tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, and InP. In one embodiment, the substrate101includes SiGe buffer layers epitaxially grown on the silicon substrate101. The germanium concentration of the SiGe buffer layers may increase from 30 atomic percent germanium for the bottom-most buffer layer to 70 atomic percent germanium for the top-most buffer layer.

The substrate101may include various regions that have been suitably doped with impurities (e.g., p-type or n-type impurities). The dopants are, for example boron for a p-type field effect transistor (FET) and phosphorus for an n-type FET.

The stack of semiconductor layers104includes first semiconductor layers106and second semiconductor layers108. The first semiconductor layers106and the second semiconductor layers108are made of semiconductor materials having different etch selectivity and/or oxidation rates. For example, the first semiconductor layers106are made of Si and the second semiconductor layers108are made of SiGe. In some embodiments, the stack of semiconductor layers104includes alternating first and second semiconductor layers106,108. The first semiconductor layers106or portions thereof may form nanostructure channel(s) of the semiconductor device structure100at a later stage. The semiconductor device structure100may include a nanostructure transistor. The term nanostructure is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. The nanostructure channel(s) of the semiconductor device structure100may be surrounded by the gate electrode layer. The nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode layer surrounding the channels. The use of the first semiconductor layers106to define a channel or channels of the semiconductor device structure100is further discussed below. In some embodiments, the first and second semiconductor layers106,108are replaced with a single semiconductor material connected to the substrate101, and the device is a FinFET. The nanostructure transistors may be used in any suitable application. In some embodiments, the nanostructure transistors may form static random-access memory (SRAM).

It is noted that 3 layers of the first semiconductor layers106and 3 layers of the second semiconductor layers108are alternately arranged as illustrated inFIG.1, which is for illustrative purposes and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of first and second semiconductor layers106,108can be formed in the stack of semiconductor layers104; the number of layers depending on the predetermined number of channels for the semiconductor device structure100. In some embodiments, the number of first semiconductor layers106, which is the number of channels, is between 3 and 8.

The first and second semiconductor layers106,108are formed by any suitable deposition process, such as epitaxy. By way of example, epitaxial growth of the layers of the stack of semiconductor layers104may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes.

A mask structure110is formed over the stack of semiconductor layers104. The mask structure110may include an oxygen-containing layer112and a nitrogen-containing layer114. The oxygen-containing layer112may be a pad oxide layer, such as a SiO2layer. The nitrogen-containing layer114may be a pad nitride layer, such as Si3N4. The mask structure110may be formed by any suitable deposition process, such as chemical vapor deposition (CVD) process.

FIG.2is a perspective view of one of the various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments. As shown inFIG.2, fins202aand202bare formed. In some embodiments, each fin202a,202bincludes a substrate portion102a,102bformed from the substrate101, a portion of the stack of semiconductor layers104, and a portion of the mask structure110. The fins202a,202bmay be fabricated using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins202a,202bby etching the stack of semiconductor layers104and the substrate101. The etch process can include dry etch, wet etch, reactive ion etch (RIE), and/or other suitable processes. As shown inFIG.2, two fins are formed, but the number of the fins is not limited to two.

In some embodiments, the fins202a,202bmay be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) over the mask structure110, exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a patterned resist. In some embodiments, patterning the resist to form the patterned resist may be performed using an electron beam (e-beam) lithography process. The patterned resist may then be used to protect regions of the substrate101, and layers formed thereupon, while an etch process forms trenches204in unprotected regions through the mask structure110, the stack of semiconductor layers104, and into the substrate101, thereby leaving the extending fins202a,202b. The trenches204may be etched using a dry etch (e.g., RIE), a wet etch, and/or combination thereof.

FIG.3is a perspective view of one of the various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments. As shown inFIG.3, a liner304is formed over the substrate101and the fins202a,202b. In some embodiments, an optional liner302may be formed on the substrate101and fins202a,202b, and the liner304is formed on the optional liner302. The liner304may be made of a semiconductor material, such as Si. In some embodiments, the liner304is made of the same material as the substrate101. The optional liner302may be made of an oxygen-containing material, such as an oxide. The liner304may be a conformal layer and may be formed by a conformal process, such as an atomic layer deposition (ALD) process. The term “conformal” may be used herein for ease of description upon a layer having substantial same thickness over various regions. The optional liner302may be a conformal layer and may be formed by a conformal process, such as an ALD process.

FIG.4is a perspective view of one of the various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments. As shown inFIG.4, an insulating material402is formed on the substrate101. The insulating material402fills the trench204(FIG.2). The insulating material402may be first formed over the substrate101so that the fins202a,202bare embedded in the insulating material402. Then, a planarization operation, such as a chemical mechanical polishing (CMP) process and/or an etch-back process, is performed such that the tops of the fins202a,202b(e.g., the liner304) are exposed from the insulating material402, as shown inFIG.4. The insulating material402may be made of an oxygen-containing material, such as silicon oxide or fluorine-doped silicate glass (FSG); a nitrogen-containing material, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; a low-K dielectric material; or any suitable dielectric material. The insulating material402may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD).

Next, as shown inFIG.5, the insulating material402may be recessed by removing a portion of the insulating material402located between adjacent fins202a,202bto form trenches502. The trenches502may be formed by any suitable removal process, such as dry etch or wet etch that selectively removes the insulating material402but not the semiconductor material of the liner304. The recessed insulating material402may be the shallow trench isolation (STI). The insulating material402includes a top surface504that may be level with or below a surface of the second semiconductor layers108in contact with the substrate portions102a,102bof the substrate101.

Next, as shown inFIG.6, a cladding layer602is formed on the exposed surface of the liner304(FIG.5), and the optional liner302is omitted for clarity. The liner304may be diffused into the cladding layer602during the formation of the cladding layer602. Thus, in some embodiments where the optional liner302does not exist, the cladding layer602is in contact with the stack of semiconductor layers104, as shown inFIG.6. In some embodiments, the cladding layer602includes a semiconductor material. The cladding layer602grows on semiconductor materials but not on dielectric materials. For example, the cladding layer602includes SiGe and is grown on the Si of the liner304but not on the dielectric material of the insulating material402. In some embodiments, the cladding layer602may be formed by first forming a semiconductor layer on the liner304and the insulating material402, and followed by an etch process to remove portions of the semiconductor layer formed on the insulating material402. The etch process may remove some of the semiconductor layer formed on the top of the fins202a,202b, and the cladding layer602formed on the top of the fins202a,202bmay have a curved profile instead of a flat profile. In some embodiments, the cladding layer602and the second semiconductor layers108include the same material having the same etch selectivity. For example, the cladding layer602and the second semiconductor layers108include SiGe. The cladding layer602and the second semiconductor layer108may be removed subsequently to create space for the gate electrode layer.

Next, as shown inFIG.7, a liner702is formed on the cladding layer602and the top surface504of the insulating material402. The liner702may include SiO2, SiN, SiCN, SiOC, SiOCN, or a low-K dielectric material (e.g., a material having a K value lower than that of SiO2). The liner702may be formed by a conformal process, such as an ALD process. The liner702may have a thickness ranging from about 1 nm to about 6 nm. The liner702may function as a shell to protect a flowable oxide material to be formed in the trenches502(FIG.5) during subsequent removal of the cladding layer602. Thus, if the thickness of the liner702is less than about 1 nm, the flowable oxide material may not be sufficiently protected. On the other hand, if the thickness of the liner702is greater than about 6 nm, the trenches502(FIG.5) may be filled.

A dielectric material704is formed in the trenches502(FIG.5) and on the liner702, as shown inFIG.7. The dielectric material704may be an oxygen-containing material, such as an oxide, formed by FCVD. The oxygen-containing material may have a K value less than about 7, for example less than about 3. A planarization process, such as a CMP process, may be performed to remove portions of the liner702and the dielectric material704formed over the fins202a,202b. The portion of the cladding layer602disposed on the nitrogen-containing layer114may be exposed after the planarization process.

Next, as shown inFIG.8, the liner702and the dielectric material704are recessed to the level of the topmost first semiconductor layer106. For example, in some embodiments, after the recess process, the dielectric material704may include a top surface802that is substantially level with a top surface804of the topmost first semiconductor layer106. The top surface804of the topmost first semiconductor layer106may be in contact with the mask structure110, such as in contact with the oxygen-containing layer112. The liner702may be recessed to the same level as the dielectric material704. The recess of the liners702and the dielectric material704may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. In some embodiments, a first etch process may be performed to recess the dielectric material704followed by a second etch process to recess the liner702. The etch processes may be selective etch processes that do not remove the semiconductor material of the cladding layer602. As a result of the recess process, trenches806are formed between the fins202a,202b.

A dielectric material904is formed in the trenches806(FIG.8) and on the dielectric material704, the liner702, as shown inFIG.9. The dielectric material904may include SiO, SiN, SiC, SiCN, SiON, SiOCN, AlO, AlN, AlON, ZrO, ZrN, ZrAlO, HfO, or other suitable dielectric material. In some embodiments, the dielectric material904includes a high-K dielectric material (e.g., a material having a K value higher than that of SiO2). The dielectric material904may be formed by any suitable process, such as a CVD, PECVD, FCVD, or ALD process. The dielectric material904may have a thickness ranging from about 5 nm to about 20 nm. The dielectric material904may fill the trenches806(FIG.8). Thus, if the thickness of the dielectric material904is less than about 5 nm, the trenches806may not be filled. On the other hand, if the thickness of the dielectric material904is greater than about 20 nm, the manufacturing cost is increased without significant advantage.

A planarization process is performed to expose the nitrogen-containing layer114of the mask structure110, as shown inFIG.9. The planarization process may be any suitable process, such as a CMP process. The planarization process removes portions of the dielectric material904and the cladding layer602disposed over the mask structure110. The liner702, the dielectric material704, and the dielectric material904together may be referred to as a dielectric feature906. The dielectric feature906includes a bottom portion908having a shell, which is the liner702, and a core, which is the dielectric material704. The dielectric feature further includes a top portion, which is the dielectric material904. The dielectric feature906may be a dielectric fin that separates adjacent source/drain (S/D) epitaxial features1502(FIG.15) and adjacent gate electrode layers2006(FIG.20F).

Next, as shown inFIG.10, the cladding layers602are recessed, and the mask structures110are removed. The recess of the cladding layers602may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. The recess process may be controlled so that the remaining cladding layers602are substantially at the same level as the top surface804of the topmost first semiconductor layer106in the stack of semiconductor layers104. The etch process may be a selective etch process that does not remove the dielectric material904. The removal of the mask structures110may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. The removal of the mask structure110exposes the top surfaces804of the topmost first semiconductor layers106in the stacks of semiconductor layers104.

The top portion of the dielectric feature906(e.g., the dielectric material904) may have a height H1along the Z direction. The height H1may range from about 15 nm to about 50 nm. The dielectric material904may be disposed on the top surface802of the dielectric material704, and the top surface802may be coplanar with the top surface804of the topmost first semiconductor layer106of the stack of semiconductor layers104.

Next, as shown inFIG.11, one or more sacrificial gate stacks1102are formed on the semiconductor device structure100. The sacrificial gate stack1102may include a sacrificial gate dielectric layer1104, a sacrificial gate electrode layer1106, and a mask structure1108. The sacrificial gate dielectric layer1104may include one or more layers of dielectric material, such as SiO2, SiN, a high-K dielectric material, and/or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer1104includes a material different than that of the dielectric material904. In some embodiments, the sacrificial gate dielectric layer1104may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable process. The sacrificial gate electrode layer1106may include polycrystalline silicon (polysilicon). The mask structure1108may include an oxygen-containing layer1110and a nitrogen-containing layer1112. In some embodiments, the sacrificial gate electrode layer1106and the mask structure1108are formed by various processes such as layer deposition, for example, CVD (including both LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof.

The sacrificial gate stacks1102may be formed by first depositing blanket layers of the sacrificial gate dielectric layer1104, the sacrificial gate electrode layer1106, and the mask structure1108, followed by pattern and etch processes. For example, the pattern process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etch process may include dry etch (e.g., RIE), wet etch, other etch methods, and/or combinations thereof. By patterning the sacrificial gate stack1102, the stacks of semiconductor layers104of the fins202a,202bare partially exposed on opposite sides of the sacrificial gate stack1102. As shown inFIG.11, two sacrificial gate stacks1102are formed, but the number of the sacrificial gate stacks1102is not limited to two. More than two sacrificial gate stacks1102are arranged along the Y direction in some embodiments.

As shown inFIG.12, a spacer1202is formed on the sidewalls of the sacrificial gate stacks1102. The spacer1202may be formed by first depositing a conformal layer that is subsequently etched back to form sidewall spacers1202. For example, a spacer material layer can be disposed conformally on the exposed surfaces of the semiconductor device structure100. The conformal spacer material layer may be formed by an ALD process. Subsequently, anisotropic etch is performed on the spacer material layer using, for example, RIE. During the anisotropic etch process, most of the spacer material layer is removed from horizontal surfaces, such as the tops of the fins202a,202b, the cladding layer602, the dielectric material904, leaving the spacers1202on the vertical surfaces, such as the sidewalls of sacrificial gate stack1102. The spacer1202may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. In some embodiments, the spacer1202includes multiple layers, such as main spacer walls, liner layers, and the like.

Next, exposed portions of the fins202a,202b, exposed portions of the cladding layers602, exposed portions of the dielectric material904not covered by the sacrificial gate stacks1102and the spacers1202are selectively recessed by using one or more suitable etch processes, such as dry etch, wet etch, or a combination thereof. In some embodiments, exposed portions of the stacks of semiconductor layers104of the fins202a,202bare removed, exposing portions of the substrate portions102a,102b, respectively. As shown inFIG.12, the exposed portions of the fins202a,202bare recessed to a level at or below the top surface504of the insulating material402. The recess processes may include an etch process that recesses the exposed portions of the fins202a,202band the exposed portions of the cladding layers602.

In some embodiments, the etch process may reduce the height of the exposed top portion (e.g., the dielectric material904) of the dielectric feature906from H1to H2, as shown inFIG.12. Thus, a first portion1204of the dielectric material904under the sacrificial gate stack1102and the spacers1202has the height H1, while a second portion1206of the dielectric material904located between S/D epitaxial features1502(FIG.15) has the height H2less than the height H1.

At this stage, end portions of the stacks of semiconductor layers104under the sacrificial gate stacks1102and the spacers1202have substantially flat surfaces which may be flush with corresponding spacers1202. In some embodiments, the end portions of the stacks of semiconductor layers104under the sacrificial gate stacks1102and spacers1202are slightly horizontally etched.

Next, as shown inFIG.13, the edge portions of each second semiconductor layer108and edge portions of the cladding layers602are removed, forming gaps1302. In some embodiments, the portions of the second semiconductor layers108and cladding layers602are removed by a selective wet etch process that does not remove the first semiconductor layers106. For example, in cases where the second semiconductor layers108are made of SiGe, and the first semiconductor layers106are made of silicon, a selective wet etch including an ammonia and hydrogen peroxide mixtures (APM) may be used.

Next, as show inFIG.14, dielectric spacers1402are formed in the gaps1302. In some embodiments, the dielectric spacers1402may be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. In some embodiments, the dielectric spacers1402may be formed by first forming a conformal dielectric layer using a conformal deposition process, such as ALD, followed by an anisotropic etch to remove portions of the conformal dielectric layer other than the dielectric spacers1402. The dielectric spacers1402may be protected by the first semiconductor layers106and the spacers1202during the anisotropic etch process. In some embodiments, the dielectric spacers1402may be flush with the spacers1202.

Next, as shown inFIG.15, S/D epitaxial features1502are formed on the substrate portions102a,102bof the fins202a,202b. The S/D epitaxial feature1502may include one or more layers of Si, SiP, SiC and SiCP for an n-channel FET or Si, SiGe, Ge for a p-channel FET. The S/D epitaxial features1502may grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the substrate portions102a,102b. The S/D epitaxial features1502are formed by an epitaxial growth method using CVD, ALD or MBE. The S/D epitaxial features1502are in contact with the first semiconductor layers106and dielectric spacers1402(FIG.14). The S/D epitaxial features1502may be the S/D regions. In this disclosure, a source and a drain are interchangeably used, and the structures thereof are substantially the same.

Next, as shown inFIG.16, a contact etch stop layer (CESL)1602may be formed on the S/D epitaxial features1502, the dielectric features906, and adjacent the spacers1202. The CESL1602may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, the like, or a combination thereof. The CESL1602may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL1602is a conformal layer formed by the ALD process. An interlayer dielectric (ILD) layer1604may be formed on the CESL1602. The materials for the ILD layer1604may include an oxide formed by tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer1604may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer1604, the semiconductor device structure100may be subject to a thermal process to anneal the ILD layer1604.

A planarization process is performed to expose the sacrificial gate electrode layer1106, as shown inFIG.16. The planarization process may be any suitable process, such as a CMP process. The planarization process removes portions of the ILD layer1604and the CESL1602disposed on the sacrificial gate stacks1102. The planarization process may also remove the mask structure1108(FIG.11). The ILD layer1604may be recessed to a level below the top of the sacrificial gate electrode layer1106, and a nitrogen-containing layer1606, such as a SiCN layer, may be formed on the recessed ILD layer1604, as shown inFIG.16. The nitrogen-containing layer1606may protect the ILD layer1604during subsequent etch processes.

FIGS.17A-19Aare perspective views of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.17B-19Bare cross-sectional side views of various stages of manufacturing the semiconductor device structure100taken along line A-A ofFIG.17A, in accordance with some embodiments.FIG.17Aillustrates a perspective view of the semiconductor device structure100ofFIG.16, andFIG.17Ashows a cross-section of the stack of semiconductor layers104and the sacrificial gate electrode layer1106and a cross-section of the insulating material402and dielectric feature906.FIG.17Bis a cross-sectional side view of the semiconductor device structure100taken along line A-A ofFIG.17A. As shown inFIG.17A, a plurality of sacrificial gate stacks1102are disposed over the fins202a,202b. The nitrogen-containing layers1606are omitted for clarity inFIGS.17A-19A.

As shown inFIG.18A, one or more of the sacrificial gate electrode layers1106are removed, and the portions of the stacks of semiconductor layers104and the portions of the fins202a,202bdisposed thereunder are also removed. The removal process may be one or more etch processes. In some embodiments, because the sacrificial gate electrode layers1106, the portions of the stacks of semiconductor layers104, and the portions of the fins202a,202bare all made from a semiconductor material, a single etch process is performed to remove the sacrificial gate electrode layers1106, the portions of the stacks of semiconductor layers104, and the portions of the fins202a,202b. In some embodiments, multiple etch processes are performed to remove the sacrificial gate electrode layers1106, the portions of the stacks of semiconductor layers104, and the portions of the fins202a,202b. A mask (not shown) is disposed on the other sacrificial gate electrode layers1106to protect them from the removal process. A dielectric material1804is formed in the opening formed from the removal of the sacrificial gate electrode layers1106, the portions of the stacks of semiconductor layers104, and the portions of the fins202a,202b. The dielectric material1804may be any suitable dielectric material, such as SiN. In some embodiments, a liner1802is formed in the opening, and the dielectric material1804is formed on the liner1802. The dielectric material1804functions to isolate devices, such as a group of transistors.

After forming the liner1802and the dielectric material1804, the mask (not shown) is removed to expose the remaining sacrificial gate electrode layers1106. As shown inFIGS.18A and18B, the sacrificial gate electrode layers1106are recessed to a level just above a top surface1808of the dielectric material904. In some embodiments, the portion of the recessed sacrificial gate electrode layer1106disposed on the top surface1808of the dielectric material904has a thickness T1. The thickness T1may be the same as or less than the height H1of the dielectric material904(FIG.12), such as from about 0.5 times H1to about 1.5 times H1. Trenches1806are formed between adjacent portions of the ILD layer1604as a result of the recessing of the sacrificial gate electrode layers1106, as shown inFIG.18A.

As shown inFIGS.19A and19B, a mask structure1902is formed on the semiconductor device structure100. In some embodiments, the mask structure1902is a tri-layer photoresist. For example, the mask structure1902may include a bottom layer1904and a middle layer1906disposed on the bottom layer1904. The bottom layer1904and the middle layer1906are made of different materials such that the optical properties and/or etching properties of the bottom layer1904and the middle layer1906are different from each other. In some embodiments, the bottom layer1904may be an absorber layer, such as a chromium layer, and the middle layer1906may be a silicon-rich layer designed to provide an etch selectivity between the middle layer1906and the bottom layer1904. The mask structure1902further includes a photoresist layer1908that may be a chemically amplified photoresist layer and can be a positive tone photoresist or a negative tone photoresist. The photoresist layer1908may include a polymer, such as phenol formaldehyde resin, a poly(norbornene)-co-malaic anhydride (COMA) polymer, a poly(4-hydroxystyrene) (PHS) polymer, a phenol-formaldehyde (bakelite) polymer, a polyethylene (PE) polymer, a polypropylene (PP) polymer, a polycarbonate polymer, a polyester polymer, or an acrylate-based polymer, such as a poly (methyl methacrylate) (PMMA) polymer or poly (methacrylic acid) (PMAA). The photoresist layer1908may be formed by spin-on coating.

As shown inFIGS.19A and19B, the photoresist layer1908is patterned so one or more openings1910are formed in the photoresist layer1908. The one or more openings1910are formed over the dielectric material904of one or more dielectric features906. The photoresist layer1908is disposed over the other dielectric features906. In other words, at least one dielectric feature906is disposed below the opening1910, and the rest of the dielectric features906are disposed below the photoresist layer1908. A portion of the middle layer1906is exposed in the opening1910.

FIGS.20A-20Iare cross-sectional side views of various stages of manufacturing the semiconductor device structure100taken along line A-A ofFIG.17A, in accordance with some embodiments. As shown inFIG.20A, the exposed portion of the middle layer1906and the portion of the bottom layer1904disposed thereunder are removed by any suitable process. The removal of the portions of the middle layer1906and the bottom layer1904extends the opening1910in the middle layer1906and the bottom layer1904to expose a portion of the sacrificial gate electrode layer1106.

As shown inFIG.20B, the exposed portion of the sacrificial gate electrode layer1106is removed by any suitable process, and the top surface1808of the dielectric material904is exposed in the opening1910. As described above in theFIG.18B, the sacrificial gate electrode layer1106is recessed so the portion of the sacrificial gate electrode layer1106disposed on the top surface1808of the dielectric material904has the thickness T1, which is substantially less than the thickness of the portion of the sacrificial gate electrode layer1106disposed on the top surface1808of the dielectric material904prior to the recess process. The thickness T1ranges from about 0.5 times H1to about 1.5 times H1in order to increase the processing window for the process described inFIG.20B. For example, if the sacrificial gate electrode layer1106is not recessed to a level shown inFIG.18B, the process to remove the portion of the sacrificial gate electrode layer1106shown inFIG.20Bmay take longer. As a result, the sacrificial gate electrode layer1106may be over etched, and the first semiconductor layers106may be damaged. With the recessed sacrificial gate electrode layer1106shown inFIG.18B, the process to remove the portion of the sacrificial gate electrode layer1106shown inFIG.20Bhas a larger processing window due to the thickness T1, which is substantially smaller than the thickness of the sacrificial gate electrode layer1106before the recess process. As a result, over etching of the sacrificial gate electrode layer1106may be avoided.

As shown inFIG.20C, the mask structure1902is removed by any suitable process. In some embodiments, the mask structure1902is removed by multiple etch processes. Each etch process does not substantially affect the sacrificial gate electrode layer1106and the dielectric material904. Next, as shown inFIG.20D, the exposed dielectric material904is removed by any suitable process. In some embodiments, the dielectric material904includes a high-K dielectric material, such as HfO2, and a chlorine based dry etch process is performed to remove the dielectric material904. For example, the dry etch process is performed in an etch chamber with a chamber pressure ranging from about 5 mTorr to about 40 mTorr. The processing temperature ranges from about 80 degrees Celsius to about 150 degrees Celsius. The transformer coupled plasma (TCP) power range from about 200 W to about 2000 W, and a bias voltage ranges from about 0 V to about 200 V. The etchant may be BCl3with a flow rate ranging from about 10 sccm to about 250 sccm or Cl2ranging from about 0 sccm to about 200 sccm. Other gases, such as Ar, He, and/or N2may be flowed along with the chlorine containing gas. The flow rate of Ar, He, and N2may range from about 50 sccm to about 200 sccm. With the process conditions described above, the HfO2etch process with chlorine containing etchant can achieve high selectivity to Si and SiN.

In some embodiments, as shown inFIG.20E, the exposed dielectric material904is recessed and not completely removed. The remaining dielectric material904may have a thickness T2ranging from about 1 nm to about 20 nm. If the thickness T2is less than about 1 nm, the risk of over etching is increased, and the dielectric material704may be damaged by the recess process. On the other hand, if the thickness T2is greater than about 20 nm, the remaining dielectric material904may be unintentionally cutting off a gate electrode layer, such as the gate electrode layer2006(FIG.20F). The dielectric material904protected by the sacrificial gate electrode layer1106has a thickness T3ranging from about 15 nm to about 50 nm. The thickness T3may be the same as the height H1(FIG.10). The thickness T3is substantially greater than the thickness T2. A top surface of the remaining dielectric material904and the side surface of the remaining dielectric material904may form an acute angle A. In some embodiments, the angle A ranges from about 10 degrees to about 80 degrees.

As shown inFIG.20F, which is an enlarged view of a portion of the semiconductor device structure100shown inFIG.20E, the remaining sacrificial gate electrode layer1106, sacrificial gate dielectric layer1104, the cladding layer602, and the second semiconductor layers108are removed, and oxygen-containing layers2002, gate dielectric layer2004, and gate electrode layer2006are formed. For example, the sacrificial gate electrode layer1106and the sacrificial gate dielectric layer1104are first removed, exposing the cladding layers602and the stacks of semiconductor layers104. Next, the cladding layers602and the second semiconductor layers108are removed. The removal processes expose the dielectric spacers1402and the first semiconductor layers106. The removal process may be any suitable processes, such as dry etch, wet etch, or a combination thereof. The etch process may be a selective etch process that removes the cladding layers602and the second semiconductor layers108but not the spacers1202, the CESL1602, the nitrogen-containing layer1606, the dielectric material904, and the first semiconductor layers106. Next, the oxygen-containing layers2002may be formed around the exposed surfaces of the first semiconductor layers106and the substrate portions102a,102b. The gate dielectric layers2004are then formed on the oxygen-containing layers2002and the dielectric features906, as shown inFIG.20F. The oxygen-containing layer2002may be an oxide layer, and the gate dielectric layer2004may include the same material as the sacrificial gate dielectric layer1104(FIG.11). In some embodiments, the gate dielectric layer2004includes a high-K dielectric material. The oxygen-containing layers2002and the gate dielectric layers2004may be formed by any suitable processes, such as ALD processes. In some embodiments, the oxygen-containing layers2002and the gate dielectric layers2004are formed by conformal processes.

Next, the gate electrode layers2006are formed on the gate dielectric layers2004. The gate electrode layer2006is formed on the gate dielectric layer2004to surround a portion of each first semiconductor layer106. The gate electrode layer2006includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate electrode layers2006may be formed by PVD, CVD, ALD, electro-plating, or other suitable method.

Next, the gate electrode layers2006are recessed to a level below top surfaces2008of the dielectric material904that is not recessed, as shown inFIG.20F. The gate electrode layers2006is disposed over the recessed dielectric material904in embodiments that the dielectric material904is recessed but not completely removed as described inFIG.20E. As a result of the recess process, some adjacent channel regions (first semiconductor layers106) may share the gate electrode layer2006, while other adjacent channel regions may include distinct gate electrode layers2006. For example, channel regions formed from the fin202aand fin202bshare the gate electrode layer2006, and channel regions formed from the fin202band the fin (not shown, on the other side of the dielectric feature906) adjacent the fin202binclude distinct gate electrode layers2006. If the gate electrode layer2006is shared by the adjacent channel regions, a single signal (i.e., an electrical current) sent to the gate electrode layer2006may control both adjacent channel regions. If the gate electrode layers2006are cut-off by the dielectric features906that are not recessed, then independent signal (i.e., independent electrical current) may be sent to each gate electrode layer2006to separately control each of the adjacent channel region. As described above, the recessed dielectric material904may have the thickness T2ranging from about 1 nm to about 20 nm. If the thickness T2is greater than about 20 nm, the gate electrode layer2006may be unintentionally cut-off by the recessed dielectric material904. The dielectric material904may be removed or recessed by the processes described inFIG.20Dfor the purpose of sharing the gate electrode layer2006.

The recess of the gate electrode layers1906may be any suitable process, such as a dry etch, a wet etch, or a combination thereof. In some embodiments, the recess process may be a selective dry etch process that does not substantially affect the nitrogen-containing layer1606, the spacer1202, and the CESL1602. As a result of the recess process, some adjacent gate electrode layers2006are separated, or cut-off, by the dielectric feature906.

FIG.20Gshows the semiconductor device structure100according to an alternative embodiment in which the dielectric material904is completely removed as described inFIG.20D. As shown inFIG.20G, the gate dielectric layer2004is disposed on the liner702and the dielectric material704.

As shown inFIG.20H, a conductive layer2010is selectively formed on the gate electrode layer2006. The conductive layer2010may include any suitable metal, such as fluorine-free tungsten (FFW), which selectively grows on the gate electrode layer2006but not the gate dielectric layer2004. As shown inFIG.20I, a dielectric material2012is formed over the dielectric features906and the conductive layer2010. The dielectric material2012may include SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, ZrN, or SiCN. The dielectric material2012may be formed by any suitable process, such as PECVD. A conductive feature2014may be formed through the dielectric material2012and in contact with the conductive layer2010. The conductive feature2014may include a material having one or more of Ru, Mo, Co, Ni. W, Ti, Ta, Cu, Al, TiN and TaN. The conductive feature2014may provide a signal, such as an electrical current, to the gate electrode layer2006shared by the channel regions formed from the fins202a,202b.

The semiconductor device structure100shown inFIGS.20A-20Iillustrate a process to use the dielectric material904of the dielectric feature906to cut-off the gate electrode layer2006. One or more of the dielectric features906may have the dielectric material904removed or recessed in order to share the gate electrode layer2006in adjacent channel regions. In some embodiments, a different approach to cut-off and to share the gate electrode layer2006is provided.

FIGS.21A-32Aare cross-sectional side views of various stages of manufacturing the semiconductor device structure100taken along line B-B ofFIG.16, in accordance with some embodiments.FIGS.21B-32Bare cross-sectional side views of various stages of manufacturing the semiconductor device structure100taken along line C-C ofFIG.16, in accordance with some embodiments.FIGS.22C-32Care cross-sectional side views of various stages of manufacturing the semiconductor device structure100taken along line D-D ofFIG.16, in accordance with some embodiments.

As shown inFIGS.21A and21B, after planarization process to expose the sacrificial gate electrode layer1106and the formation of the nitrogen-containing layer1606as shown inFIG.16, the sacrificial gate electrode layer1106, the sacrificial gate dielectric layer1104, the cladding layers602, and the second semiconductor layers108are removed. The processes described inFIGS.18A to20Eare omitted. The removal of the sacrificial gate electrode layer1106, the sacrificial gate dielectric layer1104, the cladding layers602, and the second semiconductor layers108may be performed by one or more etch processes. The one or more etch processes may remove a portion of the dielectric material904, such as removing a portion of the first portion1204of the dielectric material904. In some embodiments, the remaining first portion1204has a height H3that is substantially less than the height H1but substantially greater than the height H2. In some embodiments, the height H3ranges from about 20 nm to about 24 nm. The portions of the dielectric material904disposed under the spacers1202are protected by the spacers1202during the removal of the sacrificial gate electrode layer1106, the sacrificial gate dielectric layer1104, the cladding layers602, and the second semiconductor layers108. As a result, the portion of the dielectric material904disposed under the spacers1202has the height H1.

As shown inFIGS.22A-22C, the oxygen-containing layers2002, the gate dielectric layers2004, and the gate electrode layers2006are formed. The gate electrode layers2006are recessed to the same level as the top surface of the first portion1204of the dielectric material904. The recess of the gate electrode layers2006creates trenches2202. The trench2202includes various sections having different bottoms, such as the first portions1204of the dielectric features906as shown inFIG.22Aand the gate electrode layer2006as shown inFIG.22B.FIG.22Cillustrates the portion of the semiconductor device structure100under the trench2202along the X direction. In some embodiments, as shown inFIG.22C, the top surfaces of the gate electrode layer2006and the top surfaces of the dielectric materials904are substantially coplanar. Thus, the gate electrode layers2006are not connected and are separated by the dielectric features906. In other words, at the current stage, each channel region (first semiconductor layers106) includes a distinct gate electrode layer2006.

As shown inFIG.22C, additional fins202c,202d,202emay be formed from the substrate101. The fins202a,202b,202c,202d,202emay have different widths. For example, fins202a,202beach has a width less than a width of each of the fins202c,202d,202e. A wider fin width leads to a wider channel, and different devices may have different channel widths. For example, devices with wider channels may be more suitable for high-speed applications, such as NAND devices. Devices with narrower channels may be more suitable for low-power and low-leakage applications, such as inverter devices. The distances between adjacent gate electrode layers2006may be different. In other words, the widths of the dielectric features906may be different. For example, the dielectric feature906disposed between the gate electrode layer2006over the substrate portion102aand the gate electrode layer2006over the substrate portion102eis wider than the dielectric feature906disposed between the gate electrode layer2006over the substrate portion102aand the gate electrode layer2006over the substrate portion102b, as shown inFIG.22C.

As shown inFIGS.23A-23C, a conductive layer2302is formed on the nitrogen-containing layers1606, adjacent the spacers1202and on the bottom of the trench2202, such as the dielectric material904and the gate electrode layer2006. The conductive layer2302may include the same material as the conductive layer2010. However, the conductive layer2302is formed on all the exposed surfaces of the semiconductor device structure100, while the conductive layer2010is selectively formed on the gate electrode layers2006. The conductive layer2302may be formed by any suitable process, such as ALD, CVD, PECVD, or PVD. In some embodiments, the conductive layer2302is formed by PVD, and portions of the conductive layer2302formed on horizontal surfaces, such as the nitrogen-containing layer1606, the dielectric material904, and the gate electrode layer2006, may be thicker than portions of the conductive layer2302formed on vertical surfaces, such as the spacers1202, due to a less conformal deposition process.

Next, as shown inFIGS.24A-24C, portions of the conductive layer2302disposed adjacent the spacers1202are removed. The removal may be performed by any suitable process, such as a wet etch. The wet etch removes the portions of the conductive layer2302disposed on vertical surfaces to expose the spacers1202. The portions of the conductive layer2302disposed on horizontal surfaces are not completely removed, because the portions of the conductive layer2302disposed on vertical surfaces are thinner than the portions of the conductive layer2302disposed on horizontal surfaces. The remaining conductive layer2302disposed on the bottom of the trench2202may have a thickness ranging from about 2 nm to about 10 nm.

Next, a mask2502is formed in the trench2202and over the nitrogen-containing layers1606, as shown inFIGS.25A-25C. The mask2502may include an oxygen-containing material and/or a nitrogen-containing material. In some embodiments, the mask2502is a photoresist. Portions of the mask2502disposed on the conductive layer2302over the nitrogen-containing layers1606may be removed, as shown inFIGS.26A-26C. The portions of the mask2502may be removed by any suitable process, such as a dry etch, a wet etch, or a combination thereof. The portion of the mask2502in the trench2202is not affected by the removal process. The removal process exposes portions of the conductive layer2302disposed on the nitrogen-containing layers1606.

Next, as shown inFIGS.27A-27C, the portions of the conductive layer2302disposed on the nitrogen-containing layers1606are removed, followed by the removal of the portion of the mask2502in the trench2202to expose the portion of the conductive layer2302formed on the bottom of the trench2202. The portions of the conductive layer2302disposed on the nitrogen-containing layer1606may be removed by any suitable process, such as a dry etch, a wet etch, or a combination thereof. In some embodiments, as shown inFIGS.26A-26B and27A-27B, the portions of the mask2502and the portions of the conductive layer2302disposed on the nitrogen-containing layers1606are removed by two etch processes. Alternatively, the portions of the mask2502and the portions of the conductive layer2302disposed on the nitrogen-containing layer1606are removed by a planarization process, such as a CMP process.

The portion of the mask2502disposed in the trench2202may be removed by any suitable process, such as a dry etch, a wet etch, or a combination thereof. The removal of the portion of the mask2502may be selective, so the nitrogen-containing layers1606, the spacers1202, and the conductive layer2302disposed on the bottom of the trench2202are not substantially affected due to different etch selectivity. As shown inFIG.27C, multiple gate electrode layers2006are electrically connected to the conductive layer2302.

Next, as shown inFIGS.28A-28C, a mask structure2802is formed in the trenches2202. The mask structure2802includes a bottom layer2804, a middle layer2806, and a photoresist layer2808. The mask structure2802may be the mask structure1902, the bottom layer2804may be the bottom layer1904, the middle layer2806may be the middle layer1906, and the photoresist layer2808may be the photoresist layer1908. As shown inFIGS.29A-29C, an opening2902is formed in the mask structure2802. The opening2902may be formed by multiple processes. The opening2902exposes a portion of the conductive layer2302disposed on one of the dielectric features906.

As shown inFIGS.30A-30C, the exposed portion of the conductive layer2302is removed by any suitable process, and the dielectric material904is exposed. In some embodiments, portions of the gate electrode layer2006may be also exposed. In some embodiments, the conductive layer2302includes FFW, and a fluorine based dry etch process is performed to remove the exposed portion of the conductive layer2302. For example, the dry etch process is performed in an etch chamber with a chamber pressure ranging from about 3 mTorr to about 20 mTorr. The processing temperature ranges from about 10 degrees Celsius to about 30 degrees Celsius. The etchant may be SF6with a flow rate ranging from about 0 sccm to about 50 sccm, NF3with a flow rate ranging from about 0 sccm to about 50 sccm, and/or CF4ranging from about 0 sccm to about 50 sccm. Other gases, such as Ar and/or N2may be flowed along with the fluorine containing gas. The flow rate of Ar may range from about 50 sccm to about 200 sccm, and the flow rate of N2may range from about 50 sccm to about 140 sccm. With the process conditions described above, the FFW etch process with fluorine containing etchant can achieve high selectivity to the material of the gate electrode layer2006(e.g. TiN), the material of the dielectric material904(e.g. HfO2), and the material of the spacer1202(e.g. SiN). In some embodiments, the dry etch process removes about less than 80 percent of the thickness of the spacer1202, about less than 10 percent of the gate electrode layer2006, and about less than 10 percent of the dielectric material904.

As shown inFIGS.31A-31C, a dielectric material3102is formed in the opening2902and on the dielectric material904. The dielectric material3102may include any suitable dielectric material, such as SiN. Next, the mask structure2802is removed, and a dielectric material3202is formed in the trench2202, as shown inFIGS.32A-32C. The dielectric material3202may include the same material as the dielectric material3102. As shown inFIG.32C, the conductive layer2302may be separated into segments. For example, a first segment of the conductive layer2302electrically connects the gate electrode layers2006disposed over the fins202aand202e, and second segment of the conductive layer2302electrically connects the gate electrode layers2006disposed over the fins202b,202c, and202d. The first and second segments of the conductive layer2302are separated by the dielectric material3102. Thus,FIGS.21A to32Cillustrate a process to cut-off and to share the gate electrode layer2006, according to an alternative embodiment compared to the process shown inFIGS.20A-20I.

FIGS.33A-33Eare cross-sectional side views of various stages of manufacturing the semiconductor device structure100taken along line B-B ofFIG.16, in accordance with alternative embodiments. In some embodiments, the conductive layer2302is formed by a conformal process, such as an ALD process, and the conductive layer2302may be a conformal layer, as shown inFIG.33A. Next, as shown inFIG.33B, a sacrificial layer3302is formed in the trench2202. The sacrificial layer3302may include any material that has a different etch selectivity compared to the conductive layer2302, the spacers1202, and the nitrogen-containing layer1606. In some embodiments, the sacrificial layer3302is a bottom anti-reflective coating (B ARC) layer.

As shown inFIG.33C, the sacrificial layer3302is recessed to expose the portions of the conductive layer2302formed on the nitrogen-containing layer1606and formed on a portion of each spacer1202. Next, as shown inFIG.33D, the exposed portions of the conductive layer2302are removed by any suitable process, such as the dry etch process described inFIGS.30A-30C. The remaining sacrificial layer3302is then removed by any suitable process, as shown inFIG.30E. The remaining conductive layer2302may have a “U” shaped cross-section in the Y-Z plane, unlike the bar shaped cross-section shown inFIG.27A. Subsequent processes, such as the processes described inFIGS.28A-32C, may be performed on the conductive layer2302to cut-off and to share the gate electrode layer2006.

The present disclosure in various embodiments provide a semiconductor device structure100including a first channel region (the plurality of semiconductor layers106), a second channel region (the plurality of semiconductor layers106) disposed adjacent the first channel region, a gate electrode layer2006disposed in the first and second channel regions, a first dielectric feature906disposed adjacent the gate electrode layer2006, and a second dielectric feature906disposed between the first and second channel regions. The first dielectric feature906includes a first dielectric material904having a first thickness T3, and the second dielectric feature906includes a second dielectric material904having a second thickness T2substantially less than the first thickness T3. Some embodiments may achieve advantages. For example, the first dielectric material904having the thickness T3can separate the gate electrode layers2006, while the second dielectric material904having the thickness T2allows adjacent channel regions to share a gate electrode layer2006.

An embodiment is a semiconductor device structure. The semiconductor device structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Another embodiment is a method. The method includes forming first and second fins from a substrate, the first fin includes a first plurality of semiconductor layers, and the second fin includes a second plurality of semiconductor layers. The method further includes forming first and second dielectric features, the first dielectric feature is disposed adjacent the first fin, the second dielectric feature is disposed between the first and second fins, the first dielectric feature includes a first dielectric material, and the second dielectric feature includes a second dielectric material. The method further includes forming a sacrificial gate electrode layer over the first fin, the second fin, the first dielectric feature, and the second dielectric feature, recessing the sacrificial gate electrode layer to a level above a top surface of the second dielectric material, forming a mask structure over the first dielectric feature, removing a portion of the sacrificial gate electrode layer disposed on the second dielectric material to expose the second dielectric material, removing the mask structure, and recessing the second dielectric material.

A further embodiment is a method. The method includes forming first and second fins from a substrate, the first fin includes a first plurality of semiconductor layers, and the second fin includes a second plurality of semiconductor layers. The method further includes forming a dielectric feature between the first and second fins, and the dielectric feature includes a first dielectric material. The method further includes forming an interlayer dielectric layer over the substrate, forming a gate electrode layer surrounding the first and second pluralities of semiconductor layers, recessing the gate electrode layer to a level of a top surface of the first dielectric material, forming a conductive layer on the gate electrode layer, the first dielectric material, and over the interlayer dielectric layer, removing a portion of the conductive layer disposed over the interlayer dielectric layer, forming a mask structure on the conductive layer, forming an opening in the mask structure to expose a portion of the conductive layer disposed on the first dielectric material, removing the exposed portion of the conductive layer to expose the first dielectric material, and forming a second dielectric material on the first dielectric material.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.