Patent ID: 12222376

It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific illustrative embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made without departing from the scope of the present teachings. The following description is, therefore, merely illustrative.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or “over” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there may be no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure provide a peak voltage detection circuit with reduced charge loss as compared to conventional peak voltage detectors. Conventional circuits may exhibit charge loss in the form of “voltage droop,” i.e., a gradual reduction in the stored peak voltage over time. Embodiments of the disclosure provide a peak voltage detector having an input node coupled to an input line through a first electrically actuated switch, and an output node. A capacitor is coupled to the output node of the peak voltage detector through a second electrically actuated switch. The input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch. During operation, the electrically actuated switches may close in response to a detected incoming signal, thus allowing passage of the signal into the peak voltage detection circuit. At the end of the signal pulse, the electrically actuated switches may re-open to disconnect the peak voltage detector and the capacitor from the reset of the circuit, thus retaining the charge stored within the capacitor.

FIG.1depicts a schematic view of a device100in which embodiments of the disclosure, i.e., a circuit structure (simply “circuit” hereafter)102having voltage peak detection and hold (“PDH”) features, may be implemented. As discussed elsewhere herein, circuit102may include a sub-circuit for sensing of peak voltages and another sub-circuit for holding the magnitude of the detected peak voltage, and various additional components for interconnecting these sub-circuits to each other and/or to input and output nodes of circuit102. Device100may be a temperature stabilization structure for a micro ring modulator (MRM)104, in which device100includes, or is coupled to, circuit102to identify the highest voltage amplitude transmitted to or from device100. Although a temperature stabilization structure may be one type of device100usable with circuit102, it is understood that circuit102may be implemented with a variety of contexts and/or other types of devices100. In various implementations, embodiments of circuit102may be implemented in applications such as light detection and ranging (LiDAR), silicon-photonic circuits, nuclear electronics, etc. Regardless of which device(s)100are used, circuit102senses whether the input voltage approaches this threshold and signals device100to temporarily cease operating upon detecting a sufficiently high peak voltage.

As discussed herein, device100may be a thermal stabilization structure for MRM104, i.e., a device for monitoring the temperature of MRM104as it operates in a volatile environment to increase or decrease the temperature of MRM104during operation. MRM may include a set of four ports, including various input and output ports for receiving and transmitting optical signals passing therethrough. A drop port106(i.e., a particular type of output port) may transmit modulated optical signals from MRM104to a photonic device108coupled thereto. Other ports of MRM104are omitted fromFIG.1solely for clarity of illustration. Photonic device108then may interpret and/or process the optical signals transmitted via drop port106according to any available mechanism(s) therein.

Device100may include a thermal stabilization feedback loop110coupled to photonic device108(e.g., by one or more temperature sensors such as a proportionate to absolute temperature (PTAT) voltage circuit (not shown)) to monitor the thermal properties of photonic device108as it receives signals transmitted from MRM104via drop port106. The function of thermal stabilization feedback loop110is to measure the temperature of photonic device108as it operates, and to indirectly raise or lower the temperature of photonic device108by modifying the operating settings of MRM104, e.g., by adjusting a thermal tuner112configured to regulate the temperature of MRM104. Thermal stabilization feedback loop110may operate in part by relating voltage magnitudes within photonic device108with operating temperatures associated with such voltage levels, e.g., using logic, a look up table, and/or various other formulas and/or data within thermal stabilization feedback loop110. Further mechanisms for monitoring and adjusting the temperature(s) of MRM104and/or photonic device108are known in the art and thus not described in further detail herein. Thermal stabilization feedback loop110may use a transimpedance amplifier (TIA) or similar current-to-voltage converter to indicate the operating voltage of photonic device108. Thermal stabilization feedback loop may transmit such an output (“TIA output” inFIG.1) to circuit102, which in turn transmits a reference voltage via a reference voltage line (“VREF” inFIG.1). The reference voltage line VREFindicates the highest value (“peak”) voltage within the voltage waveform provided to circuit102.

FIG.2depicts a schematic diagram of circuit102to illustrate structural features thereof for reducing charge loss according to embodiments of the disclosure. As shown, circuit102has an input line “Vsig” coupled to thermal stabilization feedback loop110(FIG.1) to receive a voltage signal therefrom (e.g., TIA output ofFIG.1discussed herein). Input line “Vsig” may be the sole input signal provided to circuit102, and thus the only input pathway from thermal stabilization feedback loop110to circuit102. A reference voltage line VREFprovides an electrical output from circuit102, carrying a peak voltage signal to thermal stabilization feedback loop110. Circuit102may include a peak voltage detector circuit (“peak detector”)114coupling an input line Vsig of circuit102to a hold capacitor (“hold cap.”)116coupled between peak detector114and the output node of circuit102. The capacitance of hold capacitor116may be set to a particular value to reduce manufacturing costs and/or parasitic charging during operation.

According to an example, hold capacitor116may have a capacitance of at most approximately sixty picofarads (pF). Various other components of circuit102for capturing the peak voltage detected by peak detector114, storing the peak voltage in hold capacitor116, and transmitting the peak voltage via reference voltage line VREFare discussed in more detail herein.

Peak detector114may include a first operational transconductance amplifier (“OTA”)118coupling to a first input node of peak detector114(i.e., at input line Vsig), and a second input node (i.e., at one terminal of a first electrically actuated switch120) to an amplifier output node (“AmOut”). OTA118is an amplifier configured for producing an output current based on the difference of its input voltages (e.g., Vsig at one input and the output from peak detector114at the other input), multiplied by a conversion factor known as the “transconductance” of OTA118. The output from OTA118may be coupled to amplifier output node AmOut. Amplifier output node AmOut, in turn, is coupled to the source or drain of a first transistor M1, as well as the gate terminals of first transistor M1and a second transistor M2. In this configuration, current flow through transistors M1, M2will not be enabled unless the output current from OTA118is of a threshold value for activating transistors M1, M2. The other source/drain terminal of first transistor M1may be coupled to a supply voltage (Vdd) for circuit102, such that supply voltage is coupled between source/drain terminals of first transistor M1and second transistor M2as shown. The other source or drain terminal of second transistor M2in turn may be coupled to a second electrically actuated switch122. The threshold voltage to actuate first electrically actuated switch120and second electrically actuated switch122may be defined based on supply voltage Vdd, e.g., it may be a predetermined voltage difference of one half Vdd. In a specific example, the voltage to actuate switches120,122may be approximately fifty millivolts greater than one half of supply voltage Vdd. Thus, supply voltage Vdd and switches120,122may prevent miniscule signal pulses from input line Vsig from activating peak detector114and hold capacitor116.

First electrically actuated switch120and second electrically actuated switch122each may include two terminals (i.e., an input and output terminal denoted by open circles inFIG.2) and a control node (indicated with an arrow inFIG.2) for controlling whether each switch120,122opens or closes. In some cases, electrically actuated switches120,122may take the form of a field effect transistor (FET) or another voltage controlled device, a bipolar junction transistor (BJT) or other current controlled device, and/or electrically operated components for switching or otherwise electrically controlling current flow between two terminals. However embodied, electrically actuated switches120,122may create open circuit junctions except when a sufficiently high current or voltage is transmitted to each control node thereof. Transmitting at least a threshold voltage or threshold current to the control node of each electrically actuated switch120,122may cause each switch120,122to close the connection through its first and second terminals.

A skewed buffer (“buffer”)124may electrically couple input line Vsig to the control node of each electrically actuated switch120,122. Buffer124may take the form of a component for delaying a signal transmitted therethrough without significantly affecting the amplitude, frequency, or other properties of signals transmitted therethrough. Buffer124may include, e.g., a group of serially intercoupled inverters. Buffer124may be known as a “skewed” electrical element because it delays the timing of signals passing therethrough, and thus desynchronizes the transmitted signal relative to a clock signal for driving the input signal (Vsig) to circuit102. Electrically actuated switches120,122may be in an open state when the voltage of their control nodes is below a threshold value. A rising and/or peak incoming voltage may increase the voltage of input line Vsig to a magnitude that is sufficient to actuate (i.e., close) electrically actuated switches120,122. Buffer124may delay incoming signals to account for any time needed for incoming signals Vsig to pass through peak detector114, including OTA118and transistors M1, M2therein. Thus, electrically actuated switches120,122and buffer124may only allow incoming signals to circuit102to pass through peak detector114when they are at least of a minimum current or frequency magnitude.

Second electrically actuated switch122may couple the output of peak detector114to additional components for holding, resetting, and/or transmitting the detected peak voltage(s) back to thermal stabilization feedback loop110via reference voltage line VREF. Hold capacitor116may electrically couple the second terminal of second electrically actuated switch122to ground (“GND”), such that the voltage leaving peak detector114is converted into a charge stored in hold capacitor116. Due to the presence of switches120,122in circuit102, no signals will pass to hold capacitor116from peak detector114when electrically actuated switches120,122are open. In addition, the charge stored in hold capacitor116will not leak through peak detector114when electrically actuated switches120,122are open. A third transistor M3may be coupled to ground in parallel with hold capacitor116, and a gate terminal of third transistor M3may be coupled to a “reset” line for selectively enabling or disabling source to drain current flow through third transistor M3. When current flow through third transistor M3is disabled, the charge in hold capacitor116will be retained. When current flow through third transistor M3is enabled, the charge in hold capacitor116will dissipate to ground, and hence the peak voltage will be reset.

Hold capacitor116may be coupled to reference voltage line VREFthrough a second transconductance amplifier (“OTA2”)126that is coupled to reference voltage line VREF. The output current may be derived from, e.g., the charge stored in hold capacitor116, as discussed herein. Thus, any charge lost from hold capacitor116will negatively affect the accuracy of the peak voltage signal transmitted through reference voltage line VREF. Embodiments of circuit102thus prevent charge loss from hold capacitor116by including electrically actuated switches120,122to prevent current flow from hold capacitor116into peak detector114when a voltage peak is not being transmitted to circuit102.

FIG.3, discussed herein in conjunction with the schematic diagram ofFIG.2, further illustrates the function of electrically actuated switches120,122in circuit102. As discussed herein, each electrically actuated switch120,122includes a control node for determining whether switch120,122is closed (i.e., conductive) or open (i.e., non-conductive). A threshold voltage “Vth” of each electrically actuated switch120,122defines the minimum control node voltage for closing electrically actuated switch120,122. An input voltage signal may be provided to circuit102at input line Vsig as discussed in detail elsewhere herein. The voltage in input line Vsig in the illustrated plot initially may be at an initial value or “common node” (“Vcm”) but rises to a peak value before sharply returning to the common mode value. The difference between the common mode voltage and threshold voltage is designated by variable “ΔVth” inFIG.3.

As shown inFIG.3, the increase to the voltage of input line Vsig initially may have no effect on the voltage level of the control node until it exceeds threshold voltage Vth. Buffer124may be included in circuit102as discussed herein such that the voltage Vswitch applied to the control nodes of switches120,122is substantially simultaneous with the voltage of input line Vsig exceeding threshold voltage Vth. As a result, the voltage (Vswitch) applied to the control node of switches120,122does not rise above threshold voltage Vth until after voltage of input line Vsig exceeds threshold voltage Vth. The time delay of buffer124may be adjusted to better synchronize the increase and decrease in voltage Vswitch with when input line Vsig exceeds or falls below threshold voltage Vth.FIG.3thus illustrates that current flow through electrically actuated switches120,122is permitted concurrently with when the voltage of input line Vsig exceeds threshold voltage Vth.

FIG.4, discussed in conjunction withFIG.2, depicts a comparative plot of voltage versus time for circuit102over an illustrative operating period. The illustrative operating period may include two signal pulses to input line Vsig, separated from each other by a time difference (Δt) as shown. Circuit102receives these two pulses at input line Vsig such that peak detector114detects the peak voltage in input line Vsig and hold capacitor116stores the peak voltage by being coupled to peak detector114. The second solid line inFIG.4illustrates, for sake of comparison, the voltage stored in a hold capacitor of a conventional PDH circuit. When circuit102according to embodiments of the disclosure is not implemented, the voltage stored in a conventional PDH circuit will decay significantly over time, e.g., due to parasitic currents and charge losses through any couplings to the rest of a device through a peak detector and/or other components. This gradual delay in stored voltage of a PDH circuit is known as “voltage droop.” By contrast, the dotted line illustrates the stored voltage in hold capacitor116of circuit102for the same two signal pulses. In embodiments of the disclosure, electrically actuated switches120,122will substantially prevent charge loss and/or other parasitic losses from hold capacitor116by creating open circuits where charge could otherwise dissipate from hold capacitor116.

FIG.5provides another illustrative plot comparing voltage droop for several capacitance values for hold capacitor116. In the comparative plot, hold capacitances of the same value are implemented in an embodiment of circuit102and a conventional PDH circuit to compare the amount of voltage droop for each device. The solid line illustrates voltage droop versus hold capacitance for circuit102, the dashed line illustrates voltage droop versus hold capacitance for a conventional PDH circuit, and the dot-dash line illustrates the percent reduction in voltage droop for circuit102relative to the conventional PDH circuit for the same hold capacitance. Applicants have determined that embodiments of circuit102provide substantially less voltage droop than conventional PDH circuits even when using the same hold capacitor in each type of circuit. Moreover, increasing the capacitance of hold capacitor116in circuit102produces further reductions in voltage droop in circuits with higher capacitance hold capacitors116. By contrast, the voltage droop in a conventional circuit will increase significantly as the hold capacitance increases. As shown, implementing a hold capacitor116of at least approximately 30 pF with electrically actuated switches120,122in peak detector114produces at least a ninety percent reduction in voltage droop. This voltage droop reduction arises, e.g., from the ability to open any electrical connections between peak detector114and hold capacitor116when an increase to input line Vsig is not detected.

Embodiments of the disclosure may provide several technical advantages, examples of which are discussed herein. Advantages of the disclosure provide significantly less voltage droop in a PDH circuit without changing the hold capacitance of hold capacitor116, e.g., by way of electrically actuated switches120,122. Electrically actuated switches120,122, moreover, eliminate the need for complex external switching logic by using the incoming voltage signal to directly influence whether current can or cannot flow from peak detector114to hold capacitor116. In turn, the use of electrically actuated switches120,122prevents the need to transmit and process a clock signal to embodiments of circuit102. These and other aspects of circuit102discussed herein impose significantly less surface area and power requirements on device100, regardless of the applicable technical settings.

The method and structure as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a center processor.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately,” and “substantially,” are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate +/−10% of the stated value(s).

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.