Patent ID: 12238435

MODE FOR CARRYING OUT THE INVENTION

Embodiments are described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and the description thereof is not repeated in some cases. The same components are denoted by different hatching patterns in different drawings, or the hatching patterns are omitted in some cases.

Even in the case where a single component is illustrated in a circuit diagram, the component may be composed of a plurality of parts as long as there is no functional inconvenience. For example, in some cases, a plurality of transistors that operate as a switch are connected in series or in parallel. In some cases, capacitors are divided and arranged in a plurality of positions.

One conductor has a plurality of functions such as a wiring, an electrode, and a terminal in some cases. In this specification, a plurality of names are used for the same component in some cases. Even in the case where elements are illustrated in a circuit diagram as if they were directly connected to each other, the elements may actually be connected to each other through one conductor or a plurality of conductors. In this specification, even such a structure is included in direct connection.

Embodiment 1

In this embodiment, an imaging device of one embodiment of the present invention is described with reference to drawings.

One embodiment of the present invention is an imaging device having an additional function such as image processing. The imaging device can hold analog data (image data) obtained by an image capturing operation in a pixel and extract data obtained by multiplying the analog data by a predetermined weight coefficient.

Furthermore, difference data between adjacent light-receiving devices can be obtained in a pixel, and data on luminance gradient can be obtained. When the data is taken in a neural network or the like, inference of distance data or the like can be performed. Since enormous volume of image data in the state of analog data can be held in pixels, processing can be performed efficiently.

Obtaining distance data in an image can support picking operation by a robot, autonomous driving of a moving object, distance measurement, or the like. In addition, it becomes possible for a smartphone or the like to obtain distance data with one camera, although a plurality of cameras have been used to obtain distance data, so that the manufacturing cost can be reduced.

<Imaging Device>

FIG.1is a block diagram illustrating the imaging device of one embodiment of the present invention. The imaging device includes a pixel array300, a circuit301, a circuit302, a circuit303, a circuit304, and a circuit305. Note that each of the structures of the circuit301to the circuit305is not limited to a single circuit and may consist of a combination of a plurality of circuits. Furthermore, any two or more of the circuits described above may be combined. Moreover, a circuit other than the above circuits may be connected.

The pixel array300has an image capturing function and an arithmetic function. The circuit301has an arithmetic function. The circuit302has an arithmetic function or a data conversion function. The circuits303and304each have a selection function. The circuit305has a function of supplying a potential for product-sum operation to a pixel. As a circuit having a selection function, a shift register, a decoder, or the like can be used. Note that the circuits301and302may be provided outside.

The pixel array300includes a plurality of pixel blocks200. The pixel block200includes a pixel array210and a circuit220as illustrated inFIG.2.

The pixel array210includes the plurality of pixels100arranged in a matrix, each of the pixels100is electrically connected to a wiring151and a wiring152, and the wiring151and the wiring152are electrically connected to the circuit220.

The circuit220is a reading circuit and includes a circuit230and a circuit240. The circuit230is a current source circuit and has a function of controlling current flowing through the pixel array210and the circuit240. The circuit240is a difference extraction circuit, and for example, a correlated double sampling circuit (CDS circuit) can be used.

The circuit230, the circuit240, and the pixel array210are preferably formed such that two or more of the circuits have an overlapped region. This structure can reduce the area of the pixel block200, leading to higher resolution. Note that the circuit240can also be provided outside the pixel block200.

Note that the number of pixels included in the pixel array210is 3×3 in an example illustrated inFIG.2but is not limited to this. For example, the number of pixels can be 2× 2, 4×4, or the like. Alternatively, the number of pixels in a horizontal direction and the number of pixels in a vertical direction may differ from each other. Alternatively, the number of pixels may be variable by providing a switch or the like between the pixel100and each of the wiring151and the wiring152. Furthermore, some pixels may be shared by adjacent pixel blocks200. An amplifier circuit or a gain control circuit may be electrically connected to the wiring151.

The pixel100can perform acquisition of image data, generation of arithmetic data using the image data, generation of data that is obtained by adding the arithmetic data and weight coefficient, or the like. The pixel block200with the above structure can operate as a product-sum operation circuit.

<Pixel Circuit>

FIG.3illustrates a structure example of the pixel100. The pixel100includes circuits10aand10b, a circuit20, and a circuit30.

The circuits10aand10bare light-receiving circuits and have a function of generating imaging data using a photoelectric conversion device. The circuit20is a differential amplifier circuit and has a function of outputting a data potential amplified in accordance with a difference between data input from the circuit10aand the circuit10b. The circuit30is an arithmetic circuit and has a function of holding a data potential output from the circuit20and a function of adding a weight (a potential corresponding to a weight coefficient) to the data potential.

<Light-Receiving Circuit>

The circuits10aand10bcan have the same structure and include a photoelectric conversion device101(a photoelectric conversion device101aor101b), a transistor102(a transistor102aor102b), a transistor103(a transistor103aor103b), and a capacitor106(a capacitor106aor106b).

One electrode of the photoelectric conversion device101is electrically connected to one of a source and a drain of the transistor102. The other of the source and the drain of the transistor102is electrically connected to one of a source and a drain of the transistor103and one electrode of the capacitor106.

The other electrode of the photoelectric conversion device101is electrically connected to a wiring114. The other of the source and the drain of the transistor103is electrically connected to a wiring115. A gate of the transistor102is electrically connected to a wiring116. A gate of the transistor103is electrically connected to a wiring117.

Here, a point where the other of the source and the drain of the transistor102, the one of the source and the drain of the transistor103, and the one electrode of the capacitor106are electrically connected is referred to as a node FD (a node FDa or a node FDb).

The wirings114and115can each have a function of a power supply line. For example, the wiring114can function as a high potential power supply line, and the wiring115can function as a low potential power supply line. The wirings116and117can function as signal lines for controlling the electrical conduction of the respective transistors.

As the photoelectric conversion device101, a photodiode can be used. There is no limitation on the kind of photodiode, and a Si photodiode containing silicon in a photoelectric conversion layer, an organic photodiode including an organic photoconductive film in a photoelectric conversion layer, or the like can be used. In order to increase the light detection sensitivity under low illuminance conditions, an avalanche photodiode is preferably used.

The transistor102can have a function of controlling the potential of the node FD. The transistor103can have a function of initializing the potential of the node FD.

In the case where an avalanche photodiode is used as the photoelectric conversion device101, a high voltage is sometimes applied and thus a transistor with a high withstand voltage is preferably used as a transistor connected to the photoelectric conversion device101. As the transistor with a high withstand voltage, a transistor using a metal oxide in its channel formation region (hereinafter, an OS transistor) or the like can be used, for example. Specifically, an OS transistor is preferably used as the transistor102.

The OS transistor also has a feature of an extremely low off-state current. When OS transistors are used as the transistors102and103, the charge retention period of the node FD can be lengthened greatly. Therefore, a global shutter mode in which charge accumulation operation is performed in all the pixels at the same time can be used without complicating the circuit structure and operation method. Furthermore, while image data is held in the node FD, arithmetic operation using the image data can be performed a plurality of times.

On the other hand, in the case where high-speed operation is desired, a transistor using silicon in a channel formation region (hereinafter referred to as a Si transistor) and having high mobility is preferably used. Accordingly, Si transistors may be used as the transistors102and103.

Note that without limitation to the above, an OS transistor and a Si transistor may be used in combination freely. Examples of the Si transistor include a transistor including amorphous silicon and a transistor including crystalline silicon (microcrystalline silicon, low-temperature polysilicon, or single crystal silicon).

Note that the circuit structures of the circuits10aand10bdescribed above are examples, and the photoelectric conversion operation can also be performed with other circuit structures.

The circuits10aand10bmay include a transistor175(a transistor175aor175b) and a transistor176(a transistor176aor176b) as illustrated inFIG.4A.

A gate of the transistor175is electrically connected to the node FD. One of a source and a drain of the transistor175is electrically connected to a wiring118. The other of the source and the drain of the transistor175is electrically connected to one of a source and a drain of the transistor176. The other of the source and the drain of the transistor176is electrically connected to a wiring OUT. The wiring118may function as a power supply line and may be connected to the wiring115.

The transistor175is a component of a source follower that outputs data in accordance with the potential of the node FD. The transistor176functions as a selection transistor for selecting a light-receiving circuit to be read. Thus, with the use of the circuits10aand10bwith the structure inFIG.4A, image data can be read from the light-receiving circuits to the wiring OUT. With this structure, reading of image data can be performed in parallel with the operation of the circuit20.

<Differential Amplifier Circuit>

The circuit20can include transistors104(transistors104aand104b), transistors105(transistors105aand105b), a transistor107, a transistor108, and transistors131(transistors131aand131b).

One of a source and a drain of the transistor104ais electrically connected to a gate of the transistor105aand one of a source and a drain of the transistor107. One of a source and a drain of the transistor104bis electrically connected to a gate of the transistor105band the other of the source and the drain of the transistor107. One of a source and a drain of the transistor105ais electrically connected to one of a source and a drain of the transistor131a. One of a source and a drain of the transistor105bis electrically connected to one of a source and a drain of the transistor131band a gate thereof. The other of the source and the drain of the transistor105ais electrically connected to the other of the source and the drain of the transistor105band one of a source and a drain of the transistor108.

The other of a source and a drain of the transistor131is electrically connected to a wiring124. The other of the source and the drain of the transistor108is electrically connected to a reference potential line such as a GND wiring or the low potential power supply line. A gate of the transistor104ais electrically connected to a wiring121. A gate of the transistor104bis electrically connected to a wiring122. A gate of the transistor107is electrically connected to a wiring123.

The wiring124can have a function of, for example, a power supply line that supplies a high potential power. The wiring121, the wiring122, and the wiring123can have a function of signal lines that control the conduction of the transistors.

The transistor104functions as a switch. The other of the source and the drain of the transistor104ais electrically connected to the node FDa of the circuit10a. The other of the source and the drain of the transistor104bis electrically connected to the node FDb of the circuit10b. Thus, the transistors104can be regarded as components of the circuits10aand10b.

The transistors105function as a pair of differential transistors in a differential amplifier circuit. The gate of the transistor105afunctions as a first input terminal of the circuit20. The gate of the transistor105bfunctions as a second input terminal of the circuit20. Thus, data generated by the circuit10acan be input to the first input terminal. Data generated by the circuit10bcan be input to the second input terminal.

The transistor107functions as a switch, and can make the first input terminal and the second input terminal have the same potential. The switch can be used when reference data is obtained.

The transistor108functions as a current source, and an appropriate potential (Bias) is supplied to a gate thereof. Note that a resistor may be used instead of the transistor108.

The transistor131functions as a voltage converter circuit. Note that the transistor131is illustrated as a diode-connected p-channel transistor inFIG.3as an example, but may be a diode-connected n-channel transistor. Alternatively, a diode element, a resistor, or a cascode circuit may be used instead of the transistor131.

Part of a wiring that connects the one of the source and the drain of the transistor105bto the one of the source and the drain of the transistor131balso functions as an output terminal, and is represented by a node N inFIG.3. A data potential amplified in accordance with a difference between output data of the circuit10aand output data of the circuit10bcan be output to the output terminal (the node N).

Note that the circuit20may have a structure in which the transistor104and the transistor107are omitted as illustrated inFIG.4B. Although the transistor104and the transistor107are provided to make the first input terminal and the second input terminal have the same potential, when a potential (a reset potential) of the wiring115supplied through the transistor103is used as the potential, the transistor104and the transistor107can be omitted.

<Arithmetic Circuit>

The circuit30can have a structure including a transistor132, a transistor133, a transistor134, a transistor142, a transistor143, a transistor144, a capacitor135, and a capacitor145.

One of a source and a drain of the transistor132is electrically connected to one electrode of the capacitor135and a gate of the transistor133. The other electrode of the capacitor135is electrically connected to one of a source and a drain of the transistor134. One of a source and a drain of the transistor142is electrically connected to one electrode of the capacitor145and a gate of the transistor143. The other electrode of the capacitor145is electrically connected to one of a source and a drain of the transistor144.

A gate of the transistor132is electrically connected to a wiring125. A gate of the transistor142is electrically connected to a wiring126. A gate of the transistor134and a gate of the transistor144are electrically connected to a wiring127. The other of the source and the drain of the transistor132and the other of the source and the drain of the transistor142are each electrically connected to the node N. The other of the source and the drain of the transistor134and the other of the source and the drain of the transistor144are each electrically connected to a wiring128.

One of a source and a drain of the transistor133is electrically connected to the wiring151. One of a source and a drain of the transistor143is electrically connected to the wiring152. The other of the source and the drain of the transistor133and the other of the source and the drain of the transistor143are electrically connected to the reference potential line such as a GND wiring or the low potential power supply line.

The wiring125, the wiring126, and the wiring127can have a function of signal lines that control the conduction of the transistors. The wiring128is, for example, a wiring capable of supplying a potential corresponding to a weight coefficient (e.g., a filter for convolution processing), and is electrically connected to the circuit305(seeFIG.1). The wiring151is a wiring electrically connected to the circuit230and the circuit240, and the wiring152is a wiring electrically connected to the circuit230(seeFIG.2).

Here, a point (wiring) at which one of a source and a drain of the transistor132, one electrode of the capacitor135, and the gate of the transistor133are connected is referred to as a node P1. A point (wiring) at which the one of the source and the drain of the transistor142, the one electrode of the capacitor145, and the gate of the transistor143are connected is referred to as a node P2.

Data output by the circuit20can be stored in the node P1and the node P2. The node P1and the node P2can be floating. Thus, a potential (weight coefficient) supplied by the wiring128can be supplied to data held in the node P1and the node P2by capacitive coupling of the capacitor135or the capacitor145.

<Reading Circuit>

Next, a structure of the reading circuit220will be described. The reading circuit220includes a circuit230functioning as a current source circuit and a circuit240functioning as a difference extraction circuit.

<Current Source Circuit>

The circuit230can make a current flow in accordance with data held in the pixel100, and can have the structure illustrated inFIG.5A, for example. The circuit230can include a current supply portion225and a current mirror portion226.

FIG.5Aillustrates a structure including an n-channel transistor. The current supply portion225can include transistors222and252and transistors223and253.

One of a source and a drain of the transistor222is electrically connected to a signal line FG. The other of the source and the drain of the transistor222is electrically connected to a gate of the transistor223. One of a source and a drain of the transistor252is electrically connected to a signal line FGREF. The other of the source and the drain of the transistor252is electrically connected to a gate of the transistor253. A gate of the transistor222and a gate of the transistor252are electrically connected to a wiring213.

One of a source and a drain of the transistor223is electrically connected to the wiring151. One of a source and a drain of the transistor253is electrically connected to the wiring152. The other of the source and the drain of the transistor223and the other of the source and the drain of the transistor253are electrically connected to the high potential power supply line (VDD).

In the current supply portion225, an appropriate signal potential is supplied to the signal lines FG and FGREF, a high potential (“H”) is supplied to the wiring213to turn on the transistors222and252and the transistors223and253, whereby a current can be supplied to the wiring151and the wiring152.

The current mirror portion226can include a transistor254and a transistor224. A gate of the transistor254and one of a source and a drain thereof are electrically connected to the wiring152. One of a source and a drain of the transistor224is electrically connected to the wiring151. The other of the source and the drain of the transistor224and the other of a source and a drain of the transistor254are electrically connected to the low potential power supply line (VSS). A gate of the transistor224is electrically connected to the gate of the transistor254, and a current (ICM) that is the same as a current flowing through the transistor254can flow through the transistor224.

Note that the current supply portion225may include a p-channel transistor as illustrated inFIG.5B. An output side of a transistor262is electrically connected to the wiring152and a gate of a transistor261.

<Difference Extraction Circuit>

The circuit240is a difference extraction circuit, and can extract the product (product-sum operation result) of data and a weight coefficient by using currents flowing through the pixel100and the circuit230. As illustrated inFIG.2, the pixels100are electrically connected to each other through the wiring151. The circuit240can perform arithmetic operation using the sum of currents flowing through the transistors133in the pixels100.

The circuit240includes a capacitor202, a transistor203, a transistor204, a transistor205, a transistor206, and a transistor207as a voltage converter circuit. An appropriate analog potential (Bias) is applied to a gate of the transistor207.

One electrode of the capacitor202is electrically connected to one of a source and a drain of the transistor203and a gate of the transistor204. One of a source and a drain of the transistor204is electrically connected to one of a source and a drain of the transistor205and one of a source and a drain of the transistor206. The other electrode of the capacitor202is electrically connected to the wiring151and one of a source and a drain of the transistor207.

Here, a point at which the one electrode of the capacitor202, the one of the source and the drain of the transistor203, and the gate of the transistor204are connected is referred to as a node C.

The other of the source and the drain of the transistor203is electrically connected to a wiring218. The other of the source and the drain of the transistor204is electrically connected to a wiring219. The other of the source and the drain of the transistor205is electrically connected to the reference power supply line such as the GND wiring. The other of the source and the drain of the transistor206is electrically connected to a wiring212. The other of the source and the drain of the transistor207is electrically connected to the reference power supply line such as the GND wiring. A gate of the transistor203is electrically connected to a wiring216. A gate of the transistor205is electrically connected to a wiring215. A gate of the transistor206is electrically connected to a wiring214.

The wirings218and219can each have a function of a power supply line. For example, the wiring218can have a function of a wiring for supplying a reset potential (Vr) for reading operation. The wiring219can function as the high potential power supply line. The wirings214,215, and216can function as signal lines that control the conduction of the respective transistors. The wiring212is an output line and can be electrically connected to the circuit301illustrated inFIG.1, for example.

The transistor203can have a function of resetting the potential of the node C to the potential of the wiring218. The transistors204and205can have a function of a source follower circuit. The transistor206can have a function of controlling reading operation. Note that the circuit240has a function of a correlated double sampling circuit (CDS circuit), and can be replaced with a circuit with another structure that has the function.

Operation

Next, operation of the imaging device of one embodiment of the present invention is described. In one embodiment of the present invention, first, data (reference data) when there is no difference between output of the circuit10aand output of the circuit10bin the pixel100is obtained. Next, image data is obtained by photoelectric conversion in each of the circuit10aand the circuit10band difference data therebetween is obtained.

Next, a differential potential between data obtained by converting a current flowing from the circuit230to the circuit240into voltage on the basis of the reference data and the difference data and data obtained by converting a current flowing from the circuit230to the circuit240when weight is added to the reference data and the difference data into voltage is extracted in the circuit240.

The differential potential corresponds to data obtained by eliminating various offset components from a current flowing through the circuit220, and is data obtained by voltage conversion of a current represented by a term of the product of the difference data and the weight coefficient. In other words, the product of the difference data and the weight coefficient can be extracted.

In order to explain the whole flow of extraction of the product of the difference data and the weight coefficient, description of operation of the pixel100is omitted, and explanation is made on the assumption that a data potential X corresponding to difference data between the circuit10aand the circuit10b(a difference of data obtained by photoelectric conversion) is stored in the node P1and a data potential (reference data, ideally 0) output by the circuit20when there is no difference between outputs of the circuit10aand the circuit10bis stored in the node P2. Detailed operation of the pixel100will be described later.

The pixel block200can eliminate offset components other than the product of difference data (potential X) and a weight coefficient (potential W) and extract the objective WX. The following is a WX extraction process in the case of using the circuit illustrated inFIG.5Aas the circuit230.

First, in the circuit240, the transistor203is brought into a conduction state so that a potential Vr is written from the wiring218to the node C. Here, the potential Vr is a reset potential used for reading operation.

At this time, difference data (potential X) is assumed to be written to the node P1in the circuit30in the pixel100. Furthermore, reference data 0 is assumed to be written to the node P2. In addition, a weight coefficient written from the wiring128is assumed to be 0.

At this time, the sum of currents flowing from the circuit230to the transistors133in the pixels100is kΣ(X−Vth)2. The sum of currents flowing from the circuit230to the transistors143in the pixels100is kΣ(0−Vth)2. Here, k is a constant and Vthis the threshold voltage of each transistor.

In the circuit230, the sum of currents flowing through the transistor223is represented by IC, the sum of currents flowing through the transistor253is represented by ICFEF, and a current flowing through the transistor224and the transistor254is represented by ICM (seeFIG.5A).

At this time, ICREF0(ICREF when the weight is 0)=ICM0+kΣ(0−Vth)2, ICM0=ICREF0−kΣ(0−Vth)2.

Here, a current IR0(IR when the weight is 0) which flows through the transistor207in the circuit240is represented as follows: IR0=IC−ICM0−kΣ(X−Vth)2. This means IR0=IC−ICREF0+kΣ(0−Vth)2−kΣ(X−Vth)2.

Then, the transistor203in the circuit240is brought out of a conduction state, and the potential Vr is held in the node C.

Next, a potential corresponding to the weight coefficient (W) is supplied to the wiring128, and the weight coefficient (W) is supplied to the node P1and the node P2by capacitive coupling.

At this time, the sum of currents flowing from the circuit230to the transistors133in the pixels100is kΣ(X+W−Vth)2. The sum of currents flowing from the circuit230to the transistors143in the pixels100is k≥(W−Vth)2.

Thus, the current IR flowing through the transistor207in the circuit240is represented by IR=IC−ICM−KΣ(X+W−Vth)2. This means IR=IC−ICREF+kΣ(W−Vth)2−kΣ(X+W−Vth)2.

Here, the difference between IR0and IR is represented as follows: IR0−IR=kΣ(Vth2−(X−Vth)2−(W−Vth)2+(W+X−Vth)2)=kΣ(2WX). Thus, offset components are eliminated and a term consisting of WX can be extracted.

The above difference can be extracted by the circuit240. IR0is initialized as the potential Vr in the node C, and the potential of the wiring151changes from a state of weight coefficient 0 to a state of weight coefficient W while the node C is in a floating state, whereby a difference Y of the potential (corresponding to a difference between IR0and IR) is added to the node C by capacitive coupling of the capacitor202. Here, the node C becomes Vr+Y, and when the potential Vr is regarded as 0, Y is a potential itself obtained by converting the difference between IR0and IR into voltage. That is, WX can be extracted.

Next, operation of the pixel100and operation of the pixel block200are described in accordance with the timing chart inFIG.6. Note that the pixel100described here has the structure illustrated inFIG.3. Furthermore, a predetermined potential is supplied to the power supply line and the like.

<Operation of Pixel100>

At time T1, when the potential of the wiring116is set at “H”, the potential of the wiring117is set at “H”, the potential of the wiring121is set at “H”, the potential of the wiring122is set at “H”, and the potential of the wiring123is set at “L”, the transistor102and the transistor103are turned on and the potential of the node FDa and the potential of the node FDb become a reset potential (the potential of the wiring115) in the circuit10aand the circuit10b.

At time T2, when the potential of the wiring116is set at “L”, the potential of the wiring117is set at “L”, the potential of the wiring121is set at “L”, the potential of the wiring122is set at “L”, and the potential of the wiring123is set at “L”, the transistor102, the transistor103, and the transistor104are turned off and the reset potential is held in the node FDa and the node FDb. Furthermore, the photoelectric conversion device101starts accumulation operation.

At time T3, when the potential of the wiring116is set at “H”, the potential of the wiring122is set at “H”, and the potential of the wiring123is set at “H”, the transistor102is turned on and electric charges accumulated in the photoelectric conversion device101are transferred to the node FDa and the node FDb. After that, the potential of the wiring116is set at “L” and the potentials of the node FDa and the node FDb are held.

The transistor104band the transistor107are turned on, and the potential of the node FDb is input to a first input terminal (the gate of the transistor105a) and a second input terminal (the gate of the transistor105b) of the circuit20.

At this time, a data potential amplified in accordance with a difference between data input to the first input terminal and data input to the second input terminal is output to the output terminal (the node N) of the circuit20. Here, the data potential output to the output terminal (the node N) of the circuit20can be referred to as reference data. The reference data is output when there is no difference between the data input to the first input terminal and the data input to the second input terminal.

Note that in the case where the circuit20has the structure ofFIG.4B, the reference data is output when the node FDa and the node FDb are set at the reset potential.

At time T4, the potential of the wiring126is set at “H”, the potential of the output terminal (the node N) of the circuit20is written to the node P2in the circuit30. After that, the potential of the wiring126is set at “L” and the potential of the node P2is held. Note that before time T4, the potential of the wiring127is set at “H” and the potentials of the other electrodes of the capacitors135and145are set at the potential of the wiring128(e.g., 0).

At time T5, the potential of the wiring121is set at “H”, the potential of the wiring122is set at “H”, and the potential of the wiring123is set at “L”, the transistor104ais turned on, the transistor107is turned off, and the potential of the node FDa is written to the first input terminal of the circuit20. Note that the potential of the node FDb is written to the second input terminal of the circuit20.

Thus, a data potential amplified in accordance with a difference between the node FDa and the node FDb is output to the output terminal (the node N) of the circuit20. Here, the data potential output to the output terminal (the node N) of the circuit20is a potential amplified in accordance with a difference between image data obtained by the circuit10aand image data obtained by the circuit10b, and can be referred to as difference data. Alternatively, it can be referred to as image data or imaging data.

At time T6, when the potential of the wiring125is set at “H”, the potential of the output terminal (the node N) of the circuit20is written to the node P1in the circuit30. After that, the potential of the wiring125is set at “L” and the potential of the node P1is held.

At time T7, when the potential of the wiring121is set at “L”, the potential of the wiring122is set at “L”, and the potential of the wiring127is set at “L”, the transistor104, the transistor134, and the transistor144are turned off and a series of operations of the circuit10a, the circuit10b, and the circuit20are terminated.

<Operation of Circuit220and Circuit230>

At time T7, when the potential of the wiring213is set at “H”, an appropriate bias is supplied to gates of the transistor222and the transistor252in the circuit230, so that a current IC flows through the transistor223and a current ICREF flows through the transistor253(seeFIG.5A). Then, the potential of the wiring213is set at “L”.

Here, ICREF is the sum of a current (ICM) flowing through the transistor254and a current flowing through the transistor143in the circuit30. The current IC is the sum of a current (ICM) flowing through the transistor224, a current flowing through the transistor133in the circuit30, and a current flowing through the transistor207in the circuit240.

When the potential of the wiring151is determined in the above state, the potential of the wiring216is set at “H” and the potential “Vr” of the wiring218is written to the node C. Then, the potential of the wiring216is set at “L” and the node C is set into a floating state to hold the potential “Vr”.

At time T8, when the potential of the wiring127is set at “H”, the transistors134and144are turned on, and the potential W corresponding to the weight coefficient is supplied to the wiring128, the potential W is supplied to potentials held in the node P1and the node P2in the circuit30by capacitive coupling. At this time, the state of weight coefficient 0 is changed to the state of weight coefficient W, so that a current flowing through the transistor207in the circuit230changes.

At this time, the amount “Y” of change in the potential of the wiring151is added to the node C by capacitive coupling of the capacitor202. Here, the potential of the node C becomes “Vr+Y”, and when potential “Vr”=0, the potential of the node C becomes a potential “Y” obtained by converting a difference of current flowing through the transistor207into voltage. In other words, WX can be extracted in accordance with the aforementioned current equation.

At time T9, when the potential of the wiring214is set at “H” and an appropriate bias is supplied to the wiring215, due to the source follower operation, the circuit240can output a signal potential in accordance with WX to the wiring212.

At time T10, the potential of the wiring127is set at “L”, the potential of the wiring213is set at “L”, the potential of the wiring214is set at “L”, the potential of the wiring215is set at “L”, so that reading operation is terminated.

WX output from the circuit240in the above manner can be input to the circuit301.

Although an example in which simultaneous data is written to the node P1and the node P2and data based on the data is extracted is described above, there may be time difference between the data in the node P1and the data in the node P2. For example, data in a first frame is written to the node P1and data in a second frame is written to the node P2, whereby data including motion parallax can be extracted. Since data on the depth (distance) can be obtained from the motion parallax, stereoscopic vision can be formed.

<Circuits301and302>

FIG.7Ais a diagram illustrating the circuit302and the circuits301connected to the circuit240. The result data of product-sum operation output from the circuit240are sequentially input to the circuits301. The circuit301may have a variety of arithmetic functions. Alternatively, the function of the circuits301may be replaced by software processing.

For example, the circuits301can each include a circuit that performs arithmetic operation of an activation function. A comparator circuit can be used as the circuit, for example. A comparator circuit outputs a result of comparing input data and a set threshold as binary data. In other words, the pixel blocks200and the circuits301can operate as part of elements in a neural network.

The circuit301may include an A/D converter. When image data is output to the outside without product-sum operation or the like, analog data can be converted into digital data by the circuit301. For example, the circuit10aand the circuit10billustrated inFIG.4Acan be electrically connected to the circuit301through the wiring OUT.

Furthermore, in the case where the data output from the pixel blocks200, which corresponds to image data of a plurality of bits, can be binarized by the circuits301, the binarization can be rephrased as compression of image data.

Data output from the circuits301are sequentially input to the circuit302. The circuit302can have a structure including a latch circuit, a shift register, and the like, for example. With this structure, parallel-serial conversion can be performed and data input in parallel can be output to a wiring311as serial data. The connection destination of the wiring311is not limited. For example, it can be connected to a neural network, a memory device, a communication device, or the like.

Moreover, as illustrated inFIG.7B, the circuit302may have a neural network. The neural network includes memory cells arranged in a matrix, and each memory cell holds a weight coefficient. Data output from the circuits301are input to corresponding memory cells320, and product-sum operation can be performed. Note that the number of memory cells illustrated inFIG.7Bis an example, and the number is not limited.

The neural network illustrated inFIG.7Bincludes the memory cells320and reference memory cells325which are arranged in a matrix, a circuit330, a circuit350, a circuit360, and a circuit370.

FIG.8illustrates an example of the memory cells320and the reference memory cells325. The reference memory cells325are provided in an arbitrary one column. The memory cells320and the reference memory cells325have similar structures and each include a transistor161, a transistor162, and a capacitor163.

One of a source and a drain of the transistor161is electrically connected to a gate of the transistor162. The gate of the transistor162is electrically connected to one electrode of the capacitor163. Here, a point where the one of the source and the drain of the transistor161, the gate of the transistor162, and the one electrode of the capacitor163are connected is referred to as a node NM.

A gate of the transistor161is electrically connected to a wiring WL. The other electrode of the capacitor163is electrically connected to a wiring RW. One of a source and a drain of the transistor162is electrically connected to a reference potential wiring such as a GND wiring.

In the memory cell320, the other of the source and the drain of the transistor161is electrically connected to a wiring WD. The other of the source and the drain of the transistor162is electrically connected to a wiring BL.

In the reference memory cell325, the other of the source and the drain of the transistor161is electrically connected to a wiring WDref. The other of the source and the drain of the transistor162is electrically connected to a wiring BLref.

The wiring WL is electrically connected to the circuit330. As the circuit330, a decoder, a shift register, or the like can be used.

The wiring RW is electrically connected to the circuit301. Binary data output from the circuit301is written to each memory cell. Note that a sequential circuit such as a shift register may be included between the circuit301and the memory cells.

The wiring WD and the wiring WDref are electrically connected to the circuit350. As the circuit350, a decoder, a shift register, or the like can be used. The circuit350may include a D/A converter and an SRAM. The circuit350can output a weight coefficient to be written to the node NM.

The wiring BL and the wiring BLref are electrically connected to the circuit360. The circuit360can have a structure equivalent to that of the circuit240. By the circuit360, a signal of a product-sum operation result from which offset components are eliminated can be obtained.

The circuit360is electrically connected to the circuit370. The circuit370can also be referred to as an activation function circuit. The activation function circuit has a function of performing arithmetic operation for converting the signal input from the circuit360in accordance with a predefined activation function. As the activation function, for example, a sigmoid function, a tan h function, a softmax function, a ReLU function, a threshold function, or the like can be used. The signal converted by the activation function circuit is output to the outside as output data.

As illustrated inFIG.9A, a neural network NN can be formed of an input layer IL, an output layer OL, and a middle layer (hidden layer) HL. The input layer IL, the output layer OL, and the middle layer HL each include one or more neurons (units). Note that the middle layer HL may be composed of one layer or two or more layers. A neural network including two or more middle layers HL can also be referred to as a DNN (deep neural network). Learning using a deep neural network can also be referred to as deep learning.

Input data is input to each neuron in the input layer IL. A signal output from a neuron in the previous layer or the subsequent layer is input to each neuron in the middle layer HL. To each neuron in the output layer OL, output signals of the neurons in the previous layer are input. Note that each neuron may be connected to all the neurons in the previous and subsequent layers (full connection), or may be connected to some of the neurons.

FIG.9Billustrates an example of arithmetic operation with the neurons. Here, a neuron N and two neurons in the previous layer which output signals to the neuron N are illustrated. An output x1of a neuron in the previous layer and an output x2of a neuron in the previous layer are input to the neuron N. Then, in the neuron N, a total sum x1w1+x2w2of a multiplication result (x1w1) of the output x1and a weight w1and a multiplication result (x2w2) of the output x2and a weight w2is calculated, and then a bias b is added as necessary, so that the value a=x1w1+x2w2+b is obtained. Then, the value a is converted with an activation function h, and an output signal y=ah is output from the neuron N.

In this manner, the arithmetic operation with the neurons includes the arithmetic operation that sums the products of the outputs and the weights of the neurons in the previous layer, that is, the product-sum operation (x1w1+x2w2described above). This product-sum operation may be performed using a program on software or may be performed using hardware.

In one embodiment of the present invention, an analog circuit is used as hardware to perform product-sum operation. In the case where an analog circuit is used as the product-sum operation circuit, the circuit scale of the product-sum operation circuit can be reduced, or higher processing speed and lower power consumption can be achieved by reduced frequency of access to a memory.

The product-sum operation circuit preferably has a structure including an OS transistor. An OS transistor is suitably used as a transistor included in an analog memory of the product-sum operation circuit because of its extremely low off-state current. Note that the product-sum operation circuit may be formed using both a Si transistor and an OS transistor.

This embodiment can be combined with the other embodiments as appropriate.

Embodiment 2

In this embodiment, structure examples and the like of the imaging device of one embodiment of the present invention will be described.

Structure Example

FIG.10Ais a diagram illustrating a structure example of a pixel in an imaging device, and a stacked-layer structure of a layer561and a layer563can be employed.

The layer561includes the photoelectric conversion device101. The photoelectric conversion device101can include a layer565aand a layer565bas illustrated inFIG.11A. Note that a layer may be rephrased as a region, depending on the case.

The photoelectric conversion device101illustrated inFIG.11Ais a pn junction photodiode; for example, a p-type semiconductor can be used for the layer565a, and an n-type semiconductor can be used for the layer565b. Alternatively, an n-type semiconductor may be used for the layer565a, and a p-type semiconductor may be used for the layer565b.

The pn junction photodiode can be formed typically using single crystal silicon. A photodiode in which single crystal silicon is used for a photoelectric conversion layer has relatively wide spectral sensitivity to light from ultraviolet light to near-infrared light and can detect light of various wavelengths by being combined with an optical conversion layer described later.

Alternatively, a compound semiconductor may be used for the photoelectric conversion layer of the pn junction photodiode. As the compound semiconductor, gallium arsenic phosphide (GaAsP), gallium phosphide (GaP), indium gallium arsenide (InGaAs), lead sulfide (PbS), lead selenide (PbSe), indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), or the like can be used, for example.

The compound semiconductor is preferably a compound semiconductor including a Group 13 element (e.g., aluminum, gallium, or indium) and a Group 15 element (e.g., nitrogen, phosphorus, arsenic, or antimony) (such a compound semiconductor is also referred to as a Group III-V compound semiconductor) or a compound semiconductor including a Group 12 element (e.g., magnesium, zinc, cadmium, or mercury) and a Group 16 element (e.g., oxygen, sulfur, selenium, or tellurium) (such a compound semiconductor is also referred to as a Group II-VI compound semiconductor).

The use of the compound semiconductor, which can change the bandgap depending on the combination of constituent elements and the atomic ratio of the elements, enables formation of a photodiode having sensitivity to a wide wavelength range from ultraviolet light to infrared light.

Note that the wavelength of ultraviolet light can be generally defined as the vicinity of 0.01 μm to the vicinity of 0.38 μm, the wavelength of visible light can be generally defined as the vicinity of 0.38 μm to the vicinity of 0.75 μm, the wavelength of near-infrared light can be generally defined as the vicinity of 0.75 μm to the vicinity of 2.5 μm), the wavelength of mid-infrared light can be generally defined as the vicinity of 2.5 μm to the vicinity of 4 μm, and the wavelength of far-infrared light can be generally defined as the vicinity of 4 μm to the vicinity of 1000 μm.

For example, to form a photodiode having sensitivity to light from ultraviolet light to visible light, GaP or the like can be used for the photoelectric conversion layer. To form a photodiode having sensitivity to light from ultraviolet light to near-infrared light, silicon, GaAsP, or the like described above can be used for the photoelectric conversion layer. Furthermore, to form a photodiode having sensitivity to light from visible light to mid-infrared light, InGaAs or the like can be used for the photoelectric conversion layer. To form a photodiode having sensitivity to light from near-infrared light to mid-infrared light, PbS, InAs, or the like can be used for the photoelectric conversion layer. To form a photodiode having sensitivity to light from mid-infrared light to far-infrared light, PbSe, InSb, HgCdTe, or the like can be used for the photoelectric conversion layer.

Note that the photodiodes using the above-described compound semiconductors may be pin junction photodiodes as well as pn junction photodiodes. Furthermore, the pn junction and the pin junction may have a heterojunction structure without being limited to a homojunction structure.

For example, in the heterojunction, a first compound semiconductor can be used as one layer of the pn junction structure, and a second compound semiconductor that is different from the first compound semiconductor can be used as the other layer. Furthermore, a first compound semiconductor can be used as any one or two layers of the pin junction structure, and a second compound semiconductor that is different from the first compound semiconductor can be used as the other layer(s). Note that one of the first compound semiconductor and the second compound semiconductor may be a semiconductor of a single element such as silicon.

Note that different materials may be used for different pixels in forming photoelectric conversion layers of photodiodes. With this structure, an imaging device which includes any two kinds of pixels or three kinds of pixels among a pixel that detects ultraviolet light, a pixel that detects visible light, a pixel that detects infrared light, and the like can be formed.

The photoelectric conversion device101included in the layer561may have a stacked-layer structure of a layer566a, a layer566b, a layer566c, and a layer566das illustrated inFIG.11B. The photoelectric conversion device101illustrated inFIG.11Bis an example of an avalanche photodiode, and the layer566aand the layer566dcorrespond to electrodes and the layers566band566ccorrespond to a photoelectric conversion portion.

The layer566ais preferably a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a stacked layer thereof can be used.

A conductive layer having a high light-transmitting property with respect to visible light is preferably used as the layer566d. For example, indium oxide, tin oxide, zinc oxide, indium tin oxide, gallium zinc oxide, indium gallium zinc oxide, graphene, or the like can be used. Note that a structure in which the layer566dis omitted can also be employed.

A structure of a pn junction photodiode containing a selenium-based material in a photoelectric conversion layer can be used for the layers566band566cof the photoelectric conversion portion, for example. A selenium-based material, which is a p-type semiconductor, is preferably used for the layer566b, and gallium oxide or the like, which is an n-type semiconductor, is preferably used for the layer566c.

A photoelectric conversion device containing a selenium-based material has characteristics of high external quantum efficiency with respect to visible light. In the photoelectric conversion device, electrons are greatly amplified with respect to the amount of incident light by utilizing the avalanche multiplication. A selenium-based material has a high light-absorption coefficient and thus has advantages in production; for example, a photoelectric conversion layer can be formed using a thin film. A thin film of a selenium-based material can be formed by a vacuum evaporation method, a sputtering method, or the like.

As the selenium-based material, crystalline selenium (single crystal selenium or polycrystalline selenium) or amorphous selenium can be used. These selenium-based materials have sensitivity to light from ultraviolet light to visible light. Furthermore, a compound of copper, indium, and selenium (CIS), a compound of copper, indium, gallium, and selenium (CIGS), or the like can be used. These compounds have sensitivity to light from ultraviolet light to near-infrared light.

An n-type semiconductor is preferably formed using a material with a wide band gap and a light-transmitting property with respect to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or mixed oxide thereof can be used. In addition, these materials have a function of a hole-injection blocking layer, so that a dark current can be decreased.

The photoelectric conversion device101included in the layer561may have a stacked-layer structure of a layer567a, a layer567b, a layer567c, a layer567d, and a layer567eas illustrated inFIG.11C. The photoelectric conversion device101illustrated inFIG.11Cis an example of an organic photoconductive film; the layer567ais a lower electrode, the layer567eis an upper electrode having a light-transmitting property, and the layers567b,567c, and567dcorrespond to a photoelectric conversion portion.

One of the layers567band567din the photoelectric conversion portion can be a hole-transport layer and the other can be an electron-transport layer. The layer567ccan be a photoelectric conversion layer.

For the hole-transport layer, molybdenum oxide can be used, for example. For the electron-transport layer, fullerene such as C60or C70, or a derivative thereof can be used, for example.

As the photoelectric conversion layer, a mixed layer of an n-type organic semiconductor and a p-type organic semiconductor (bulk heterojunction structure) can be used. There are various organic semiconductors, and a material having sensitivity to light with an intended wavelength is selected as a photoelectric conversion layer.

For the layer563illustrated inFIG.10A, a silicon substrate can be used, for example. The silicon substrate includes a Si transistor or the like. With the use of the Si transistor, as well as a pixel circuit, a circuit for driving the pixel circuit, a circuit for reading out an image signal, an image processing circuit, a neural network, a communication circuit, or the like can be formed. Furthermore, a CPU (Central Processing Unit), an MCU (Micro Controller Unit), a memory circuit such as a DRAM (Dynamic Random Access Memory), or the like may be formed. Note that the above-described circuits except the pixel circuit are each referred to as a functional circuit in this embodiment.

For example, some or all of the transistors included in the pixel circuits (the pixels100) and the functional circuits (the circuits220,301,302,303,304,305, and the like) described in Embodiment 1 can be provided in the layer563.

The layer563may be a stack of a plurality of layers as illustrated inFIG.10B. AlthoughFIG.10Billustrates an example in which the layer563is composed of three layers563a,563b, and563c, a two-layer structure may be employed as well. Alternatively, the layer563may be a stack of four or more layers. These layers can be stacked by a bonding process, for example. With this structure, the pixel circuits and the functional circuits can be dispersed in a plurality of layers; thus, the pixel circuits and the functional circuits can be provided to overlap with each other, which enables a small-sized and high-performance imaging device to be manufactured.

Furthermore, the pixel may have a stacked-layer structure of the layer561, a layer562, and the layer563as illustrated inFIG.10C.

The layer562can include OS transistors. One or more of the functional circuits described above may be formed using OS transistors. Alternatively, one or more of the functional circuits may be formed using Si transistors included in the layer563and the OS transistors included in the layer562. Alternatively, the layer563may be a support substrate such as a glass substrate, and the functional circuits may be formed using the OS transistors included in the layer562.

A normally-off CPU (also referred to as “Noff-CPU”) can be formed using an OS transistor and a Si transistor, for example. Note that the Noff-CPU is an integrated circuit including a normally-off transistor, which is in a non-conduction state (also referred to as an off state) even when a gate voltage is 0 V.

In the Noff-CPU, power supply to a circuit that does not need to operate can be stopped so that the circuit can be brought into a standby state. The circuit brought into the standby state because of the stop of power supply does not consume power. Thus, the power usage of the Noff-CPU can be minimized. Moreover, the Noff-CPU can hold data necessary for operation, such as setting conditions, for a long time even when power supply is stopped. The return from the standby state requires only restart of power supply to the circuit and does not require rewriting of setting conditions or the like. In other words, high-speed return from the standby state is possible. As described here, the Noff-CPU can have a reduced power consumption without a significant decrease in operation speed.

The layer562may be a stack of a plurality of layers as illustrated inFIG.10D. AlthoughFIG.10Dillustrates an example in which the layer562is composed of two layers562aand563b, a stack of three or more layers may be employed as well. These layers can be formed to be stacked over the layer563, for example. Alternatively, the layers formed over the layer563and the layers formed over the layer561may be bonded to each other.

As a semiconductor material used for an OS transistor, a metal oxide whose energy gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, further preferably greater than or equal to 3 eV can be used. A typical example thereof is an oxide semiconductor containing indium; and a CAAC-OS, a CAC-OS, each of which will be described later, or the like can be used, for example. A CAAC-OS has a crystal structure including stable atoms and is suitable for a transistor that is required to have high reliability, and the like. A CAC-OS has high mobility and is suitable for a transistor that operates at high speed, and the like.

In an OS transistor, a semiconductor layer has a large energy gap, and thus the OS transistor has an extremely low off-state current of several yoctoamperes per micrometer (current per micrometer of a channel width). An OS transistor has features such that impact ionization, an avalanche breakdown, a short-channel effect, or the like does not occur, which are different from those of a Si transistor. Thus, the use of an OS transistor enables formation of a circuit having high withstand voltage and high reliability. Moreover, variations in electrical characteristics due to crystallinity unevenness, which are caused in the Si transistor, are less likely to occur in OS transistors.

A semiconductor layer in an OS transistor can be, for example, a film represented by an In-M-Zn-based oxide that contains indium, zinc, and M (one or more selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). The In-M-Zn-based oxide can be typically formed by a sputtering method. Alternatively, the In-M-Zn-based oxide may be formed by an ALD (Atomic layer deposition) method.

It is preferable that the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn-based oxide by a sputtering method satisfy In≥M and Zn≥M. The atomic ratio of metal elements in such a sputtering target is preferably, for example, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, or In:M:Zn=5:1:8. Note that the atomic ratio in the formed semiconductor layer may vary from the above atomic ratio of metal elements in the sputtering target in a range of +40%.

An oxide semiconductor with low carrier density is used for the semiconductor layer. For example, for the semiconductor layer, an oxide semiconductor whose carrier density is lower than or equal to 1×1017/cm3, preferably lower than or equal to 1×1015/cm3, further preferably lower than or equal to 1×1013/cm3, still further preferably lower than or equal to 1×1011/cm3, even further preferably lower than 1×1010/cm3, and higher than or equal to 1×10−9/cm3can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and can thus be referred to as an oxide semiconductor having stable characteristics.

Note that the composition is not limited to those described above, and a material having the appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics of the transistor (e.g., field-effect mobility and threshold voltage). To obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio between a metal element and oxygen, the interatomic distance, the density, and the like of the semiconductor layer be set to appropriate values.

When silicon or carbon, which is one of elements belonging to Group 14, is contained in the oxide semiconductor contained in the semiconductor layer, oxygen vacancies are increased, and the semiconductor layer becomes n-type. Thus, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is set to lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3.

Alkali metal and alkaline earth metal might generate carriers when bonded to an oxide semiconductor, in which case the off-state current of the transistor might be increased. Therefore, the concentration of alkali metal or alkaline earth metal in the semiconductor layer (the concentration obtained by secondary ion mass spectrometry) is set to lower than or equal to 1×1018atoms/cm3, preferably lower than or equal to 2×1016atoms/cm3.

When nitrogen is contained in the oxide semiconductor contained in the semiconductor layer, electrons serving as carriers are generated and the carrier density increases, so that the semiconductor layer easily becomes n-type. As a result, a transistor using an oxide semiconductor that contains nitrogen is likely to have normally-on characteristics. Hence, the nitrogen concentration (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably set to lower than or equal to 5×1018atoms/cm3.

When hydrogen is contained in the oxide semiconductor contained in the semiconductor layer, hydrogen reacts with oxygen bonded to a metal atom to be water, and thus sometimes forms oxygen vacancies in the oxide semiconductor. When the channel formation region in the oxide semiconductor includes oxygen vacancies, the transistor sometimes has normally-on characteristics. In some cases, a defect in which hydrogen enters oxygen vacancies functions as a donor and generates electrons serving as carriers. In other cases, bonding of part of hydrogen to oxygen bonded to a metal atom generates electrons serving as carriers. Thus, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

A defect in which hydrogen enters oxygen vacancies can function as a donor of the oxide semiconductor. However, it is difficult to evaluate the defects quantitatively. Thus, the oxide semiconductor is sometimes evaluated by not its donor concentration but its carrier concentration. Therefore, in this specification and the like, the carrier concentration assuming the state where an electric field is not applied is sometimes used, instead of the donor concentration, as the parameter of the oxide semiconductor. That is, “carrier concentration” in this specification and the like can be replaced with “donor concentration” in some cases.

Therefore, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration of the oxide semiconductor, which is obtained by secondary ion mass spectrometry (SIMS), is lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, further preferably lower than 5×1018atoms/cm3, still further preferably lower than 1×1018atoms/cm3. When an oxide semiconductor with sufficiently reduced impurities such as hydrogen is used for a channel formation region of a transistor, stable electrical characteristics can be given.

The semiconductor layer may have a non-single-crystal structure, for example. Examples of the non-single-crystal structure include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) including a c-axis aligned crystal, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among the non-single-crystal structures, the amorphous structure has the highest density of defect states, whereas the CAAC-OS has the lowest density of defect states.

An oxide semiconductor film having an amorphous structure has disordered atomic arrangement and no crystalline component, for example. Alternatively, an oxide film having an amorphous structure has, for example, a completely amorphous structure and no crystal part.

Note that the semiconductor layer may be a mixed film including two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a CAAC-OS region, and a region having a single crystal structure. The mixed film has, for example, a single-layer structure or a stacked-layer structure including two or more of the above regions in some cases.

The composition of a CAC (Cloud-Aligned Composite)-OS, which is one embodiment of a non-single-crystal semiconductor layer, will be described below.

A CAC-OS refers to one composition of a material in which elements constituting an oxide semiconductor are unevenly distributed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size, for example. Note that a state in which one or more metal elements are unevenly distributed and regions including the metal element(s) are mixed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size in an oxide semiconductor is hereinafter referred to as a mosaic pattern or a patch-like pattern.

Note that an oxide semiconductor preferably contains at least indium. It is particularly preferable that indium and zinc be contained. Moreover, in addition to these, one kind or a plurality of kinds selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.

For example, of the CAC-OS, an In—Ga—Zn oxide with the CAC composition (such an In—Ga—Zn oxide may be particularly referred to as CAC-IGZO) has a composition in which materials are separated into indium oxide (hereinafter, InOX1(X1 is a real number greater than 0)) or indium zinc oxide (hereinafter, InX2ZnY2OZ2(X2, Y2, and Z2 are real numbers greater than 0)), and gallium oxide (hereinafter, GaOX3(X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter, GaX4ZnY4OZ4(x4, Y4, and Z4 are real numbers greater than 0)), and a mosaic pattern is formed. Then, InOX1or InX2ZnY2OZ2forming the mosaic pattern is evenly distributed in the film (this composition is hereinafter also referred to as a cloud-like composition).

That is, the CAC-OS is a composite oxide semiconductor having a composition in which a region including GaOX3as a main component and a region including InX2ZnY2OZ2or InOX1as a main component are mixed. Note that in this specification, for example, when the atomic ratio of In to an element M in a first region is larger than the atomic ratio of In to the element M in a second region, the first region is regarded as having a higher In concentration than the second region.

Note that IGZO is a commonly known name and sometimes refers to one compound formed of In, Ga, Zn, and O. A typical example is a crystalline compound represented by InGaO3(ZnO)m1(m1 is a natural number) or In(1+x0)Ga(1−x0)O3(ZnO)m0(−1≤x0≤1; m0 is a given number).

The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis alignment and are connected in the a-b plane without alignment.

On the other hand, the CAC-OS relates to the material composition of an oxide semiconductor. The CAC-OS refers to a composition in which, in the material composition containing In, Ga, Zn, and O, some regions that include Ga as a main component and are observed as nanoparticles and some regions that include In as a main component and are observed as nanoparticles are randomly dispersed in a mosaic pattern. Therefore, the crystal structure is a secondary element for the CAC-OS.

Note that the CAC-OS is regarded as not including a stacked-layer structure of two or more kinds of films with different compositions. For example, a two-layer structure of a film including In as a main component and a film including Ga as a main component is not included.

Note that a clear boundary cannot sometimes be observed between the region including GaOX3as a main component and the region including InX2ZnY2OZ2or InOX1as a main component.

Note that in the case where one kind or a plurality of kinds selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like are contained instead of gallium, the CAC-OS refers to a composition in which some regions that include the metal element(s) as a main component and are observed as nanoparticles and some regions that include In as a main component and are observed as nanoparticles are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed by a sputtering method under a condition where a substrate is not heated intentionally, for example. Moreover, in the case of forming the CAC-OS by a sputtering method, any one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas are used as a deposition gas. Furthermore, the ratio of the flow rate of an oxygen gas to the total flow rate of the deposition gas at the time of deposition is preferably as low as possible, and for example, the ratio of the flow rate of the oxygen gas is preferably higher than or equal to 0% and lower than 30%, further preferably higher than or equal to 0% and lower than or equal to 10%.

The CAC-OS is characterized in that no clear peak is observed in measurement using θ/2θ scan by an Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. That is, it is found from the X-ray diffraction measurement that no alignment in the a-b plane direction and the c-axis direction is observed in a measured region.

In addition, in an electron diffraction pattern of the CAC-OS which is obtained by irradiation with an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-like high-luminance region (ring region) and a plurality of bright spots in the ring region are observed. It is therefore found from the electron diffraction pattern that the crystal structure of the CAC-OS includes an nc (nano-crystal) structure with no alignment in the plan-view direction and the cross-sectional direction.

Moreover, for example, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the CAC-OS in the In—Ga—Zn oxide has a composition in which regions including GaOX3as a main component and regions including InX2ZnY2OZ2or InOX1as a main component are unevenly distributed and mixed.

The CAC-OS has a composition different from that of an IGZO compound in which the metal elements are evenly distributed, and has characteristics different from those of the IGZO compound. That is, in the CAC-OS, the region including GaOX3or the like as a main component and the region including InX2ZnY2OZ2or InOX1as a main component are separated to form a mosaic pattern.

Here, a region including InX2ZnY2OZ2or InOX1as a main component is a region whose conductivity is higher than that of a region including GaOX3or the like as a main component. In other words, when carriers flow through the regions including InX2ZnY2OZ2or InOX1as a main component, the conductivity of an oxide semiconductor is exhibited. Accordingly, when the regions including InX2ZnY2OZ2or InOX1as a main component are distributed in an oxide semiconductor like a cloud, high field-effect mobility (μ) can be achieved.

By contrast, a region including GaOX3or the like as a main component is a region whose insulating property is higher than that of a region including InX2ZnY2OZ2or InOX1as a main component. In other words, when the regions including GaOX3or the like as a main component are distributed in an oxide semiconductor, a leakage current can be suppressed and favorable switching operation can be achieved.

Accordingly, when the CAC-OS is used for a semiconductor element, the insulating property derived from GaOX3or the like and the conductivity derived from InX2ZnY2OZ2or InOX1complement each other, whereby a high on-state current (Ion) and high field-effect mobility (μ) can be achieved.

A semiconductor element using the CAC-OS has high reliability. Thus, the CAC-OS is suitably used as a constituent material of a variety of semiconductor devices.

<Stacked-Layer Structure1>

Next, a stacked-layer structure of the imaging device will be described with reference to a cross-sectional view. Note that components such as insulating layers and conductive layers are described below as examples, and other components may be further included. Alternatively, some components described below may be omitted. A stacked-layer structure described below can be formed by a bonding process, a polishing process, or the like as needed.

FIG.12is an example of a cross-sectional view of a stack including a layer560, the layer561, and the layer563and including a bonding surface between the layer563aand the layer563bof the layer563.

<Layer563b>

The layer563bcan include a functional circuit provided on a silicon substrate611. Here, the transistor105, the transistor108, and the transistor131each included in the circuit20are illustrated as part of the functional circuit.

The silicon substrate611and insulating layers612,613,614,616,617, and618are provided in the layer563b. The insulating layer612functions as a protective film. The insulating layers613,613,616, and617function as interlayer insulating films and planarization films. The insulating layer618and a conductive layer619function as bonding layers. The conductive layer619is electrically connected to a gate of the transistor105.

As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used. As the interlayer insulating film and the planarization film, for example, an inorganic insulating film such as a silicon oxide film or an organic insulating film of an acrylic resin, a polyimide resin, or the like can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used. The bonding layers will be described later.

As a conductor that can be used for a wiring, an electrode, and a plug used for electrical connection between devices, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing any of the above metal elements as its component; an alloy containing a combination of the above metal elements; or the like is selected and used as appropriate. The conductor is not limited to a single layer, and may be a plurality of layers including different materials.

<Layer563a>

The layer563aincludes a component of the pixel100. In addition, a component of the functional circuit may be included. Here, the transistor102is shown as a component of the pixel100. Furthermore, the transistor104included in the circuit20is shown as a component of the functional circuit.

A silicon substrate632and insulating layers631,633,634,635,637, and638are provided in the layer563a. In addition, conductive layers636and639are provided.

The insulating layer631and the conductive layer639function as bonding layers. The insulating layers634,635, and637function as interlayer insulating films and planarization films. The insulating layer633functions as a protective film. The insulating layer638has a function of insulating the silicon substrate632from the conductive layer639. The insulating layer638can be formed using a material similar to that for another insulating layer. The insulating layer638may be formed using the same material as that for the insulating layer631.

The conductive layer639is electrically connected to the other of the source and the drain of the transistor105and the conductive layer619. The conductive layer636is electrically connected to the wiring114(seeFIG.3).

Si transistors illustrated inFIG.12are fin-type transistors including channel formation regions in the silicon substrates (the silicon substrates611and632).FIG.13Aillustrates a cross section (a cross section along A1-A2in the layer563ainFIG.12) in the channel width direction. Note that the Si transistors may each be a planar-type transistor as illustrated inFIG.13B.

Alternatively, as illustrated inFIG.13C, a transistor including a semiconductor layer545of a silicon thin film may be used. The semiconductor layer545can be single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer546on the silicon substrate611, for example.

<Layer561>

The layer561includes the photoelectric conversion device101. The photoelectric conversion device101can be formed over the layer563a.FIG.12illustrates the photoelectric conversion device101having a structure in which the organic photoconductive film illustrated inFIG.11Cis used as the photoelectric conversion layer. Here, the layer567ais a cathode, and the layer567eis an anode.

Insulating layers651,652,653, and654and a conductive layer655are provided in the layer561.

The insulating layers651,653, and654function as interlayer insulating films and planarization films. The insulating layer654is provided to cover an end portion of the photoelectric conversion device101, and has a function of preventing a short circuit between the layer567eand the layer567a. The insulating layer652functions as an element isolation layer. An organic insulating film or the like is preferably used as the element isolation layer.

The layer567acorresponding to the cathode of the photoelectric conversion device101is electrically connected to one of the source and the drain of the transistor102included in the layer563a. The layer567ecorresponding to the anode of the photoelectric conversion device101is electrically connected to the conductive layer636included in the layer563athrough the conductive layer655.

<Layer560>

The layer560is formed over the layer561. The layer560includes a light-blocking layer671, an optical conversion layer672, and a microlens array673.

The light-blocking layer671can suppress entry of light into an adjacent pixel. As the light-blocking layer671, a metal layer of aluminum, tungsten, or the like can be used. The metal layer and a dielectric film functioning as an anti-reflection film may be stacked.

When the photoelectric conversion device101has sensitivity to visible light, a color filter can be used as the optical conversion layer672. When colors of (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), and the like are assigned to the color filters of different pixels, a color image can be obtained. For example, as illustrated in a perspective view (including a cross section) ofFIG.19A, a color filter672R (red), a color filter672G (green), and a color filter672B (blue) can be assigned to different pixels.

When a wavelength cut filter is used as the optical conversion layer672in the appropriate combination of the photoelectric conversion device101and the optical conversion layer672, the imaging device can capture images in various wavelength regions.

For example, when an infrared filter that blocks light having a wavelength shorter than or equal to that of visible light is used as the optical conversion layer672, an infrared imaging device can be obtained. When a filter that blocks light having a wavelength shorter than or equal to that of near infrared light is used as the optical conversion layer672, a far-infrared imaging device can be obtained. When an ultraviolet filter that blocks light having a wavelength longer than or equal to that of visible light is used as the optical conversion layer672, an ultraviolet imaging device can be obtained.

Note that different optical conversion layers may be provided in one imaging device. For example, as illustrated inFIG.19B, the color filter672R (red), the color filter672G (green), the color filter672B (blue), and an infrared filter672IR can be assigned to different pixels. With this structure, a visible light image and an infrared light image can be obtained simultaneously.

Alternatively, as illustrated inFIG.19C, the color filter672R (red), the color filter672G (green), the color filter672B (blue), and an ultraviolet filter672UV can be assigned to different pixels. With this structure, a visible light image and an ultraviolet light image can be obtained simultaneously.

Furthermore, when a scintillator is used as the optical conversion layer672, an imaging device that obtains an image visualizing the intensity of radiation, which is used for an X-ray imaging device or the like, can be obtained. Radiation such as X-rays passes through an object and enters the scintillator, and then is converted into light (fluorescence) such as visible light or ultraviolet light owing to a photoluminescence phenomenon. Then, the photoelectric conversion device101detects the light to obtain image data. Furthermore, the imaging device having this structure may be used in a radiation detector or the like.

A scintillator contains a substance that, when irradiated with radiation such as X-rays or gamma-rays, absorbs energy of the radiation to emit visible light or ultraviolet light. For example, a resin or ceramics in which Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, Lil, ZnO, or the like is dispersed can be used.

Image capturing with the use of infrared light or ultraviolet light can provide the imaging device with an inspection function, a security function, a sensor function, or the like. For example, by image capturing with the use of infrared light, non-destructive inspection of products, sorting of agricultural products (e.g., sugar content meter function), vein authentication, medical inspection, or the like can be performed. Furthermore, by image capturing with the use of ultraviolet light, detection of ultraviolet light released from a light source or a frame can be performed, whereby a light source, a heat source, a production device, or the like can be controlled, for example.

The microlens array673is provided over the optical conversion layer672. Light passing through an individual lens of the microlens array673goes through the optical conversion layer672directly under the lens, and the photoelectric conversion device101is irradiated with the light. With the microlens array673, collected light can be incident on the photoelectric conversion device101; thus, photoelectric conversion can be efficiently performed. The microlens array673is preferably formed using a resin, glass, or the like having a high light transmitting property with respect to light with an intended wavelength.

<Bonding>

Next, bonding of the layer563band the layer563awill be described.

The insulating layer618and the conductive layer619are provided in the layer563b. The conductive layer619includes a region embedded in the insulating layer618. Furthermore, the surfaces of the insulating layer618and the conductive layer619are planarized to be level with each other.

The insulating layer631and the conductive layer639are provided in the layer563a. The conductive layer639includes a region embedded in the insulating layer631. Furthermore, the surfaces of the insulating layer631and the conductive layer639are planarized to be level with each other.

Here, a main component of the conductive layer619and a main component of the conductive layer639are preferably the same metal element. Furthermore, the insulating layer618and the insulating layer631are preferably formed of the same component.

For the conductive layers619and639, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used, for example. Preferably, Cu, Al, W, or Au is used for easy bonding. In addition, for the insulating layers618and631, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used.

That is, the same metal material described above is preferably used for the conductive layer619and the conductive layer639. Furthermore, the same insulating material described above is preferably used for the insulating layer618and the insulating layer631. With this structure, bonding can be performed at the boundary between the layer563band the layer563a.

Note that the conductive layer619and the conductive layer639may each have a multilayer structure of a plurality of layers; in that case, the outer layers (bonding surfaces) are formed of the same metal material. The insulating layer618and the insulating layer631may each have a multilayer structure of a plurality of layers; in that case, the outer layers (bonding surfaces) are formed of the same insulating material.

Through the above bonding, the electrical connection between the conductive layer619and the conductive layer639can be obtained. Moreover, the connection between the insulating layer618and the insulating layer631with mechanical strength can be obtained.

For bonding metal layers to each other, a surface activated bonding method in which an oxide film, a layer adsorbing impurities, and the like on the surface are removed by sputtering or the like and the cleaned and activated surfaces are brought into contact to be bonded to each other can be used. Alternatively, a diffusion bonding method in which the surfaces are bonded to each other by using temperature and pressure together can be used, for example. Both methods cause bonding at an atomic level, and therefore not only electrically but also mechanically excellent bonding can be obtained.

Furthermore, for bonding insulating layers to each other, a hydrophilic bonding method or the like can be used; in the method, after high planarity is obtained by polishing or the like, the surfaces of the insulating layers subjected to hydrophilicity treatment with oxygen plasma or the like are arranged in contact with and bonded to each other temporarily, and then dehydrated by heat treatment to perform final bonding. The hydrophilic bonding method can also cause bonding at an atomic level; thus, mechanically excellent bonding can be obtained.

When the layer563band the layer563aare bonded to each other, the insulating layers and the metal layers coexist on their bonding surfaces; therefore, the surface activated bonding method and the hydrophilic bonding method are performed in combination, for example.

For example, a method can be used in which the surfaces are made clean after polishing, the surfaces of the metal layers are subjected to antioxidant treatment and hydrophilicity treatment, and then bonding is performed. Furthermore, hydrophilicity treatment may be performed on the surfaces of the metal layers being hardly oxidizable metal such as Au. Note that a bonding method other than the above-mentioned methods may be used.

The above bonding allows the circuit included in the layer563bto be electrically connected to the components of the pixel100included in the layer563a.

Modification Example of Stacked-Layer Structure1

FIG.14is a modification example of the stacked-layer structure illustrated inFIG.12and differs fromFIG.12in the structure of the photoelectric conversion device101included in the layer561and part of the structure of the layer563a; a bonding surface is also included between the layer561and the layer563a.

The layer561includes the photoelectric conversion device101, insulating layers661,662,664, and665, and conductive layers685and686.

The photoelectric conversion device101is a pn junction photodiode and includes the layer565bcorresponding to a p-type region and the layer565acorresponding to an n-type region. Note that an example where a pn junction photodiode is formed over a silicon substrate is described here. The photoelectric conversion device101is a pinned photodiode, which can suppress a dark current and reduce noise with the thin p-type region (part of the layer565b) provided on the surface side (current extraction side) of the layer565a.

The insulating layer661and the conductive layers685and686function as bonding layers. The insulating layer662functions as an interlayer insulating film and a planarization film. The insulating layer664functions as an element isolation layer.

The silicon substrate is provided with a groove that separates pixels, and the insulating layer665is provided on the top surface of the silicon substrate and in the groove. The insulating layer665can suppress leakage of carriers generated in the photoelectric conversion device101to an adjacent pixel. The insulating layer665also has a function of suppressing entry of stray light. Therefore, color mixture can be suppressed with the insulating layer665. Note that an anti-reflection film may be provided between the top surface of the silicon substrate and the insulating layer665.

The insulating layer664can be formed by a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, an STI (Shallow Trench Isolation) method or the like may be used for the formation. As the insulating layer665, for example, an inorganic insulating film of silicon oxide, silicon nitride, or the like or an organic insulating film of a polyimide resin, an acrylic resin, or the like can be used. Note that the insulating layer665may have a multilayer structure. A space may be provided in part of the insulating layer665. The space may contain a gas such as the air or an inert gas. Moreover, the space may be in a reduced pressure state.

The layer565a(corresponding to the n-type region and the cathode) of the photoelectric conversion device101is electrically connected to the conductive layer685. The layer565b(corresponding to the p-type region and the anode) is electrically connected to the conductive layer686. The conductive layers685and686each include a region embedded in the insulating layer661. Furthermore, the surfaces of the insulating layer661and the conductive layers685and686are planarized to be level with each other.

In the layer563a, the insulating layer638is formed over the insulating layer637. In addition, a conductive layer683electrically connected to one of the source and the drain of the transistor102and a conductive layer684electrically connected to the conductive layer636are formed.

The insulating layer638and the conductive layers683and684function as bonding layers. The conductive layers683and684each include a region embedded in the insulating layer638. Furthermore, the surfaces of the insulating layer638and the conductive layers683and684are planarized to be level with each other.

Here, the conductive layers683,684,685, and686are the same bonding layers as the above-described conductive layers619and639. The insulating layers638and661are the same bonding layers as the above-described insulating layers618and631.

Thus, when the conductive layer683and the conductive layer685are bonded to each other, the layer565a(corresponding to the n-type region and the cathode) of the photoelectric conversion device101can be electrically connected to the one of the source and the drain of the transistor102. In addition, when the conductive layer684and the conductive layer686are bonded to each other, the layer565b(corresponding to the p-type region and the anode) of the photoelectric conversion device101can be electrically connected to the wiring114(seeFIG.3). When the insulating layer638and the insulating layer661are bonded to each other, electrical bonding and mechanical bonding of the layer561and the layer563acan be performed.

FIG.15illustrates a modification example having a difference from the above, in which the transistor102is provided in the layer561. In this structure, the one of the source and the drain of the transistor102is directly connected to the photoelectric conversion device101and the other of the source and the drain thereof functions as the node FD. This structure enables complete transfer of electric charges accumulated in the photoelectric conversion device101, leading to an imaging device with little noise.

Here, the other of the source and the drain of the transistor102included in the layer561is electrically connected to a conductive layer692. One of a source and a drain of the transistor104included in the layer563is electrically connected to a conductive layer691. The conductive layers691and692are bonding layers like the above-described conductive layers619and639.

<Stacked-Layer Structure2>

FIG.16is an example of a cross-sectional view of a stack including the layers560,561,562, and563and not including a bonding surface. Si transistors are provided in the layer563. OS transistors are provided in the layer562. Note that the structures of the layer563, the layer561, and the layer560are not described here because they are the same as the structures illustrated inFIG.12.

<Layer562>

The layer562is formed over the layer563. The layer562includes OS transistors. Here, the transistor102and the transistor104are illustrated. In the cross-sectional view illustrated inFIG.16, electrical connection between the transistors is not illustrated.

Insulating layers621,622,623,624,625,626, and628are provided in the layer562. Moreover, a conductive layer627is provided. The conductive layer627can be electrically connected to the wiring114(seeFIG.3).

The insulating layer621functions as a blocking layer. The insulating layers622,623,625,626, and628function as interlayer insulating films and planarization films. The insulating layer624has a function of a protective film.

As the blocking layer, a film that has a function of preventing hydrogen diffusion is preferably used. In a Si device, hydrogen is necessary to terminate dangling bonds; however, hydrogen in the vicinity of an OS transistor is one factor of generating carriers in an oxide semiconductor layer, which leads to a decrease in reliability. Therefore, a hydrogen blocking film is preferably provided between a layer in which the Si device is formed and a layer in which the OS transistor is formed.

For the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or yttria-stabilized zirconia (YSZ) can be used.

The other of the source and the drain of the transistor104is electrically connected to the gate of the transistor105through a plug. Furthermore, the conductive layer627is electrically connected to the wiring114(seeFIG.3A).

The one of the source and the drain of the transistor102is electrically connected to the cathode of the photoelectric conversion device101included in the layer561. The conductive layer627is electrically connected to the anode of the photoelectric conversion device101included in the layer561.

The details of an OS transistor are illustrated inFIG.17A. The OS transistor illustrated inFIG.17Ahas a self-aligned structure in which a source electrode705and a drain electrode706are formed through provision of an insulating layer over stacked layers of an oxide semiconductor layer and a conductive layer and provision of opening portions reaching the oxide semiconductor layer.

The OS transistor can include a gate electrode701and a gate insulating film702in addition to a channel formation region708, a source region703, and a drain region704, which are formed in the oxide semiconductor layer. At least the gate insulating film702and the gate electrode701are provided in the opening portion. The opening portion may further be provided with an oxide semiconductor layer707.

As illustrated inFIG.17B, the OS transistor may have a self-aligned structure in which the source region703and the drain region704are formed in the semiconductor layer with the gate electrode701as a mask.

As illustrated inFIG.17C, the OS transistor may be a non-self-aligned top-gate transistor including a region where the source electrode705or the drain electrode706overlaps with the gate electrode701.

Although the OS transistor has a structure with a back gate735, it may have a structure without a back gate. As illustrated in a cross-sectional view of the transistor in the channel width direction inFIG.17D, the back gate735may be electrically connected to a front gate of the transistor, which is provided to face the back gate. Note thatFIG.17Dillustrates an example of a B1-B2cross section of the transistor inFIG.17A, and the same applies to a transistor having any of the other structures. A structure where a fixed potential different from the potential supplied to the front gate is supplied to the back gate735may be employed.

Modification Example of Stacked-Layer Structure2

FIG.18is a modification example of the stacked-layer structure illustrated inFIG.17and differs fromFIG.17in the structure of the photoelectric conversion device101included in the layer561and part of the structure of the layer562; a bonding surface is included between the layer561and the layer562.

The photoelectric conversion device101included in the layer561is a pn junction photodiode and has a structure similar to that illustrated inFIG.14.

In the layer562, an insulating layer648is formed over the insulating layer628. In addition, a conductive layer688electrically connected to the one of the source and the drain of the transistor102and a conductive layer689electrically connected to the conductive layer627are formed.

The insulating layer648and the conductive layers688and689function as bonding layers. The conductive layers688and689each include a region embedded in the insulating layer648. Furthermore, the surfaces of the insulating layer648and the conductive layers683and684are planarized to be level with each other.

Here, the conductive layers688and689are the same bonding layers as the above-described conductive layers619and639. The insulating layer648is the same bonding layer as the above-described insulating layers618and631.

Thus, when the conductive layer688and the conductive layer685are bonded to each other, the layer565a(corresponding to the n-type region and the cathode) of the photoelectric conversion device can be electrically connected to the one of the source and the drain of the transistor102. In addition, when the conductive layer689and the conductive layer686are bonded to each other, the layer565b(corresponding to the p-type region and the anode) of the photoelectric conversion device can be electrically connected to the wiring114(seeFIG.3). When the insulating layer648and the insulating layer661are bonded to each other, electrical bonding and mechanical bonding of the layer561and the layer562acan be performed.

In the case where a plurality of Si devices are stacked, a polishing step and a bonding step are required to be performed a plurality of times. Consequently, there are issues such as a large number of manufacturing steps, the need for a dedicated apparatus, and a low yield, and the manufacturing cost is high. An OS transistor can be formed to be stacked over a semiconductor substrate on which a device is formed, and thus a bonding step can be skipped.

Note that the structure illustrated inFIG.15in which the transistor102is provided in the layer561may be applied to this structure.

<Package, Module>

FIG.20A1is an external perspective view of the top surface side of a package in which an image sensor chip is placed. The package includes a package substrate410to which an image sensor chip450(see FIG.20A3) is fixed, a cover glass420, an adhesive430for bonding them, and the like.

FIG.20A2is an external perspective view of the bottom surface side of the package. A BGA (Ball grid array) in which solder balls are used as bumps440on the bottom surface of the package is employed. Note that, other than the BGA, an LGA (Land grid array), a PGA (Pin Grid Array), or the like may be employed.

FIG.20A3is a perspective view of the package, in which parts of the cover glass420and the adhesive430are not illustrated. Electrode pads460are formed over the package substrate410, and the electrode pads460and the bumps440are electrically connected to each other via through-holes. The electrode pads460are electrically connected to the image sensor chip450through wires470.

FIG.20B1is an external perspective view of the top surface side of a camera module in which an image sensor chip is placed in a package with a built-in lens. The camera module includes a package substrate411to which an image sensor chip451(FIG.20B3) is fixed, a lens cover421, a lens435, and the like. Furthermore, an IC chip490(FIG.20B3) having functions of a driver circuit, a signal conversion circuit, and the like of an imaging device is provided between the package substrate411and the image sensor chip451; thus, the structure as an SiP (System in package) is included.

FIG.20B2is an external perspective view of the bottom surface side of the camera module. A QFN (Quad flat no-lead package) structure in which lands441for mounting are provided on the bottom surface and side surfaces of the package substrate411is employed. Note that this structure is only an example, and a QFP (Quad flat package) or the above-mentioned BGA may also be provided.

FIG.20B3is a perspective view of the module, in which parts of the lens cover421and the lens435are not illustrated. The lands441are electrically connected to electrode pads461, and the electrode pads461are electrically connected to the image sensor chip451or the IC chip490through wires471.

The image sensor chip placed in a package having the above-described form can be easily mounted on a printed substrate or the like, and the image sensor chip can be incorporated in a variety of semiconductor devices and electronic devices.

This embodiment can be combined with the other embodiments as appropriate.

Embodiment 3

As electronic devices that can use the imaging device of one embodiment of the present invention, display devices, personal computers, image memory devices or image reproducing devices provided with storage media, mobile phones, game machines including portable game machines, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (car audio players, digital audio players, and the like), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), vending machines, and the like are given.FIG.21AtoFIG.21Fillustrate specific examples of these electronic devices.

FIG.21Ais an example of a portable information terminal mobile phone, which includes a housing981, a display portion982, an operation button983, an external connection port984, a speaker985, a microphone986, a camera987, and the like. The display portion982of the portable information terminal is provided with a touch sensor. A variety of operations such as making a call and inputting text can be performed by touch on the display portion982with a finger, a stylus, or the like. The imaging device of one embodiment of the present invention and the operation method thereof can be used in the portable information terminal.

The camera987includes the imaging device of one embodiment of the present invention, and can obtain distance data of an object in an image obtained with the camera987. Part of the image obtained with the camera987can be processed on the basis of the distance data. For example, image processing of blurring the vicinity of a main object can be performed.

FIG.21Bis an information terminal, which includes a housing911, a display portion912, a speaker913, a camera919, and the like. A touch panel function of the display portion912enables input and output of information. Furthermore, a character or the like in an image that is captured by the camera919can be recognized and the character can be voice-output from the speaker913. The imaging device of one embodiment of the present invention and the operation method thereof can be used in the portable data terminal.

FIG.21Cis a surveillance camera, which includes a support base951, a camera unit952, a protection cover953, and the like. By setting the camera unit952provided with a rotating mechanism and the like on a ceiling, an image of all of the surroundings can be taken. The imaging device of one embodiment of the present invention and the operation method thereof can be used for obtaining an image in the camera unit. Note that a surveillance camera is a name in common use and does not limit the use thereof. A device that has a function of a surveillance camera can also be called a camera or a video camera, for example.

FIG.21Dis a video camera, which includes a first housing971, a second housing972, a display portion973, an operation key974, a lens975, a connection portion976, a speaker977, a microphone978, and the like. The operation key974and the lens975are provided for the first housing971, and the display portion973is provided for the second housing972. The imaging device of one embodiment of the present invention and the operation method thereof can be used in the video camera.

FIG.21Eis a digital camera, which includes a housing961, a shutter button962, a microphone963, a light-emitting portion967, a lens965, and the like. The imaging device of one embodiment of the present invention and the operation method thereof can be used in the digital camera.

FIG.21Fis a wrist-watch-type information terminal, which includes a display portion932, a housing and wristband933, a camera939, and the like. The display portion932is provided with a touch panel for performing the operation of the information terminal. The display portion932and the housing and wristband933have flexibility and fit a body well. The imaging device of one embodiment of the present invention and the operation method thereof can be used in the information terminal.

FIG.22Aillustrates an external view of an automobile as an example of a moving object. An automobile890includes a plurality of cameras891and the like, and can obtain data on the front, the rear, the left, the right, and the upper part of the automobile890. The imaging device of one embodiment of the present invention and the operation method thereof can be used in the cameras891. The automobile890is also provided with various sensors such as an infrared radar, a millimeter wave radar, and a laser radar (not illustrated) and the like. The automobile890judges traffic conditions therearound such as the presence of a guardrail or a pedestrian by analyzing images in a plurality of image capturing directions892taken by the cameras891, and thus can perform autonomous driving. The cameras891can be used in a system for navigation, risk prediction, or the like.

When arithmetic processing with a neural network or the like is performed on the obtained image data in the imaging device of one embodiment of the present invention, for example, processing such as an increase in image resolution, a reduction in image noise, face recognition (for security reasons or the like), object recognition (for autonomous driving or the like), image compression, image compensation (a wide dynamic range), restoration of an image of a lensless image sensor, positioning, character recognition, and reduction of glare and reflection can be performed.

Note that an automobile is described above as an example of a moving object and may be any of an automobile having an internal-combustion engine, an electric vehicle, a hydrogen vehicle, and the like. Furthermore, the moving object is not limited to an automobile. Examples of moving objects include a train, a monorail train, a ship, and a flying object (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket), and these moving objects can include a system utilizing artificial intelligence when equipped with the computer of one embodiment of the present invention.

This embodiment can be combined with the other embodiments as appropriate.

REFERENCE NUMERALS

10a: circuit,10b: circuit,20: circuit,30: circuit,100: pixel,101: photoelectric conversion device,101a: photoelectric conversion device,101b: photoelectric conversion device,102: transistor,102a: transistor,102b: transistor,103: transistor,103a: transistor,103b: transistor,104: transistor,104a: transistor,104b: transistor,105: transistor,105a: transistor,105b: transistor,106: capacitor,106a: capacitor,106b: capacitor,107: transistor,108: transistor,114: wiring,115: wiring,116: wiring,117: wiring,118: wiring,121: wiring,122: wiring,123: wiring,124: wiring,125: wiring,126: wiring,127: wiring,128: wiring,131: transistor,131a: transistor,131b: transistor,132: transistor,133: transistor,134: transistor,135: capacitor,142: transistor,143: transistor,144: transistor,145: capacitor,151: wiring,152: wiring,161: transistor,162: transistor,163: capacitor,175: transistor,175a: transistor,175b: transistor,176: transistor,176a: transistor,176b: transistor,200: pixel block,202: capacitor,203: transistor,204: transistor,205: transistor,206: transistor,207: transistor,210: pixel array,212: wiring,213: wiring,214: wiring,215: wiring,216: wiring,218: wiring,219: wiring,220: circuit,222: transistor,223: transistor,224: transistor,225: current supply portion,226: current mirror portion,230: circuit,240: circuit,252: transistor,253: transistor,254: transistor,261: transistor,262: transistor,300: pixel array,301: circuit,302: circuit,303: circuit,304: circuit,305: circuit,311: wiring,320: memory cell,325: reference memory cell,330: circuit,350: circuit,360: circuit,370: circuit,410: package substrate,411: package substrate,420: cover glass,421: lens cover,430: adhesive,435: lens,440: bump,441: land,450: image sensor chip,451: image sensor chip,460: electrode pad,461: electrode pad,470: wire,471: wire,490: IC chip,545: semiconductor layer,546: insulating layer,560: layer,561: layer,562: layer,562a: layer,563: layer,563a: layer,563b: layer,563c: layer,565a: layer,565b: layer,566a: layer,566b: layer,566c: layer,566d: layer,567a: layer,567b: layer,567c: layer,567d: layer,567c: layer,611: silicon substrate,612: insulating layer,613: insulating layer,614: insulating layer,616: insulating layer,617: insulating layer,618: insulating layer,619: conductive layer,621: insulating layer,622: insulating layer,623: insulating layer,624: insulating layer,625: insulating layer,626: insulating layer,627: conductive layer,628: insulating layer,631: insulating layer,632: silicon substrate,633: insulating layer,634: insulating layer,635: insulating layer,636: conductive layer,637: insulating layer,638: insulating layer,639: conductive layer,648: insulating layer,651: insulating layer,652: insulating layer,653: insulating layer,654: insulating layer,655: conductive layer,661: insulating layer,662: insulating layer,664: insulating layer,665: insulating layer,671: light-blocking layer,672: optical conversion layer,672B: color filter,672G: color filter,672IR: infrared filter,672R: color filter,672UV: ultraviolet filter,673: micro lens array,683: conductive layer,684: conductive layer,685: conductive layer,686: conductive layer,688: conductive layer,689: conductive layer,691: conductive layer,692: conductive layer,701: gate electrode,702: gate insulating film,703: source region,704: drain region,705: source electrode,706: drain electrode,707: oxide semiconductor layer,708: channel formation region,735: back gate,890: automobile,891: camera,892: image capturing direction,911: housing,912: display portion,913: speaker,919: camera,932: display portion,933: housing and wristband,939: camera,951: support base,952: camera unit,953: protection cover,961: housing,962: shutter button,963: microphone,965: lens,967: light-emitting portion,971: housing,972: housing,973: display portion,974: operation key,975: lens,976: connection portion,977: speaker,978: microphone,981: housing,982: display portion,983: operation button,984: external connection port,985: speaker,986: microphone,987: camera