Patent ID: 12218658

Specific details are set out in the following text, without being limited thereto, in order to provide a complete understanding of the present disclosure. However, it will be clear to a person skilled in the art that the present disclosure can be used in other exemplary embodiments which may differ from the details set out hereinbelow. For example, specific configurations and forms of a system are described in the following text which are not be regarded as limiting.

FIG.1shows, in diagrammatic form, a power distribution system having a current supply10, a power distributor20and an electric consumer40. The current supply10has a positive terminal12and a negative terminal14. The power distributor20has a positive terminal22and a negative terminal26on the input side. The power distributor20further has a positive terminal24on the output side. The power distributor20has a switching system30with which the consumer40can be switched on and off. The switching system30has a controller28. The controller28can be a higher-level controller. The electric consumer40has a positive terminal42and a negative terminal44.

The negative terminal14of the current supply10, the negative terminal26of the power distributor20and the negative terminal44of the consumer40are each connected to earth/ground50. The current supply10, the power distributor20and the consumer40thus have the same reference potential, in the present case, for example, ground/earth50.

The current supply10is connected via its positive terminal12to the positive terminal22on the input side of the power distributor20. The power distributor20is connected on the output side via its positive terminal24on the output side to the electric consumer40. Although, by way of example, only one consumer40is shown, a plurality of electric consumers40can thus be connected to the power distributor20, for example via further positive terminals, not shown inFIG.1, on the output side of the power distributor20. The switching system30is configured to switch the electric consumer40on and off. Where there is a plurality of electric consumers, the system is correspondingly configured to switch each of a plurality of electric consumers on and off. For this purpose, one or more such switching systems can be provided. If switching off is not possible, the switching system30provides a corresponding fault message to the controller28. The power distribution system can be in particular a power distribution system with high demands in terms of safety (and/or high demands in terms of reliability). In such systems, it is all the more important to be able to verify the functionality of the switches used (for switching the consumer40on and off).

FIG.2shows an exemplary configuration of a power distributor20fromFIG.1. The power distributor20has a positive terminal22on the input side. The power distributor20further has a positive terminal24on the output side. The power distributor further has a controller28. The negative terminal of the power distributor fromFIG.1is not shown inFIG.2for the sake of simplicity. InFIG.2, an exemplary configuration of the switching system30fromFIG.1is shown. According to this example, the switching system30has a phase generator32, a first semiconductor switch34a, a second semiconductor switch34band a comparator38. The first semiconductor switch34aand the second semiconductor switch34bserve to switch the electric consumer40on and off. The switch-off functionality in particular is to be monitored for reliability. The first semiconductor switch34aand the second semiconductor switch34bare connected in parallel with one another.

The phase generator32controls the first semiconductor switch34aand the second semiconductor switch34b, for example in each case with the aid of a control signal that is generated. A first acquisition component can acquire a profile of an electrical variable of the first semiconductor switch34acontrolled by means of a first control signal. A second acquisition component can acquire a profile of an electrical variable of the second semiconductor switch34bcontrolled by means of a second control signal. The electrical variable can be an electric current or an electric voltage, for example. The first and/or the second acquisition component can be part of the comparator38, as is provided, for example, inFIG.2, that is to say according toFIG.2the comparator38can have the first and/or the second acquisition component. Alternatively, the first and/or the second acquisition component can be configured and arranged in the form of devices that are separate from the comparator38.

The comparator38can, as an example of a determination unit, determine an output signal on the basis of the profile of the electrical variable of the first semiconductor switch34aand the profile of the electrical variable of the second semiconductor switch34b. The output signal can allow/enable a fault in the switching of the first semiconductor switch34aand/or of the second semiconductor switch34bto be identified. In other words, the acquired output signals of the first semiconductor switch34aand of the second semiconductor switch34bcan be compared with one another and evaluated in the comparator38. From the output signals of the first and second semiconductor switches, the comparator38generates a comparison signal as the output signal. It can be deduced from this comparison signal whether or not the first semiconductor switch34aand/or the second semiconductor switch34bactually switches/switch as intended, in particular switches off/switch off or is/are able to be switched off as intended. If a fault in switching, in particular in switching off, is detected, the controller28, for example, is informed. The controller28, as a higher-level body, for example, can take corresponding measures, such as, for example, switch off the electric consumer40itself or disconnect it from the power distributor20or transfer it into a safer state.

FIG.3shows a specific configuration, more precisely a possible circuit in the form of a hardware implementation, of the switching system30. The switching system30has a phase generator32. The phase generator32is configured to generate a first control signal V_phase1and a second control signal V_phase2. The first control signal V_phase1is inputted into a first gate driver62a. The second control signal V_phase2is inputted into a second gate driver62b. The first gate driver62ais connected to the gate terminal of the first semiconductor switch34a, which in the example ofFIG.3is in the form of a first MOSFET34aand is accordingly referred to in the following text as the first MOSFET34a. The second gate driver62bis connected to the gate terminal of the second semiconductor switch34b, which in the example ofFIG.3is in the form of a MOSFET34band is accordingly referred to as the second MOSFET34b. The source terminal of the first MOSFET34ais connected to ground/earth via a variable resistor, which illustrates the load40fromFIG.1in the circuit ofFIG.3and accordingly is likewise designated by the reference numeral40. The source terminal of the second MOSFET34bis connected to ground/earth via the variable resistor. The drain terminal of the first MOSFET34ais connected to a first current sense resistor64a. The first MOSFET34aand the first current sense resistor64aare connected in series with one another. The drain terminal of the second MOSFET34bis connected to a second current sense resistor64b. The second MOSFET34band the second current sense resistor64bare connected in series with one another. A current I1is generated via an earthed voltage source10. The voltage source10is designated by the reference numeral10inFIG.3since it can correspond to the current supply10ofFIG.1.

The first measuring amplifier66aand the second measuring amplifier66bofFIG.3can be regarded as a specific implementation of the first acquisition component and the second acquisition component (e.g. ofFIG.2). The first measuring amplifier66ais configured to acquire an electrical variable at the first current sense resistor64a. For example, the first measuring amplifier66acan be configured to acquire a voltage present at the first current sense resistor64a. Additionally or alternatively, the first measuring amplifier66acan be configured to acquire an electric current flowing through the first current sense resistor64a. The second measuring amplifier66bis configured to acquire an electrical variable at the second current sense resistor64b. For example, the second measuring amplifier66bcan be configured to acquire a voltage present at the second current sense resistor64b. Additionally or alternatively, the second measuring amplifier66bcan be configured to acquire an electric current flowing through the second current sense resistor64b.

The first and second measuring amplifiers66a,66binput their acquired/measured values into an averager68. Furthermore, the profile of the electrical variable measured by the first measuring amplifier66ais inputted into a positive (non-inverting) input of a first comparator70a, which is referred to hereinbelow as the operational amplifier70a. Furthermore, the profile of the electrical variable measured by the second measuring amplifier66bis inputted into a positive (non-inverting) input of a second comparator70b, which is referred to hereinbelow as the operational amplifier70b. Both the negative (inverting) input of the first operational amplifier70aand the negative (inverting) input of the second operational amplifier70bare fed by the averager68.

In the example shown inFIG.3, the operational amplifiers70a,70bare in the form of non-inverting operational amplifiers (non-inverting comparator). In such a non-inverting operational amplifier, the reference voltage, that is to say in the case ofFIG.3the average, is connected to the inverting input of the operational amplifier. The input signal, here the respective profile of the electrical variable of the semiconductor switches34a,34bfrom the measuring amplifiers66a,66b, is in each case connected to the non-inverting input of the operational amplifier. In a non-inverting operational amplifier, a digital 0 (a LOW level) is outputted as the output if the input voltage is smaller than the reference voltage. By contrast, if the input voltage is the same as or larger than the reference voltage, a digital 1 (a HIGH level) is outputted. Alternatively, it would be possible to provide inverting operational amplifiers inFIG.3.

The output of the first operational amplifier70ais connected to a first XOR gate72a. The first XOR gate72athus receives the output signal V_comp1of the first operational amplifier70aas a first input variable. The output of the second operational amplifier70bis connected to a second XOR gate72b. The second XOR gate72bthus receives the output signal V_comp2of the second operational amplifier70bas a first input variable. The first XOR gate72areceives the first control signal V_phase1as a second input variable. The second XOR gate72breceives the second control signal V_phase2as a second input variable. The first XOR gate72aaccordingly implements an XOR operation of the output of the first operational amplifier70a(signal V_comp1) and the first control signal V_phase1. The second XOR gate72baccordingly implements an XOR operation of the output of the second operational amplifier70b(signal V_comp2) and the second control signal V_phase2.

The outputs of the first XOR gate72a(signal V_out1) and of the second XOR gate72b(signal V_out2) are inputted into an OR gate74as input variables. The output of the OR gate74is therefore an overlay of the outputs of the first and second XOR gates72a,72b.

Problems or faults in the switching of the first MOSFET34aand/or of the second MOSFET34bcan be deduced from the output signal of the OR gate (signal V_out3).

The identification of a fault can be improved by connecting a time-delay element76downstream of the OR gate74. This can be achieved in that so-called spikes (spikes can be understood as being short peaks, i.e. peaks with a duration below a predefined time threshold) are excluded by the time-delay element76. The time-delay element76has the result that only abnormalities with a duration above a predefined time threshold are identified as faults. The signal outputted by the time— delay element76can consequently be referred to as a fault signal V_fehler. In other words, the time-delay element76can be referred to as a switch-on delay which has the result that only fault signals above a specific length are evaluated as valid, that is to say as actual/valid fault signals.

With reference toFIG.3, the comparator fromFIG.2can be implemented, for example, by the measuring amplifiers66a,66b, the averager68, the operational amplifiers70a,70b, the XOR gates72a,72band the OR gate74fromFIG.3. Alternative implementations are possible in which one or more of the above-mentioned components are omitted or replaced and/or further components are added.FIG.3is thus to be regarded merely as an example of a hardware implementation of the switching system ofFIG.2.

The functioning of the configuration ofFIG.3will now be described in greater detail with reference to exemplary signal profiles fromFIGS.4aand4b. InFIGS.4aand4b, the signal profiles are in each case shown over time. The ordinate in each case shows the respective electrical variable, for example current or voltage, and the abscissa shows the time. The abscissa is divided into a plurality of regions (more specifically nine regions), which are referred to herein as time slots Z1to Z9.

In the example, the two MOSFETS34a,34bare in the form of self-locking n-channel MOSFETS. Therefore, the MOSFETS34a,34bare in a closed state and conduct current when the voltage between the gate and the source exceeds a threshold. The threshold is in each case below the 5V taken as the maximum values of the control signals V_phase1, V_phase2inFIGS.4aand4b.

As can be seen in relation to the exemplary signal profiles inFIGS.4aand4b, the two control signals V_phase1, V_phase2begin in the first time slot Z1with a value of approximately 5V. This corresponds to a high level, also referred to as HIGH (digital 1). Owing to the HIGH level of the control signals V_phase1, V_phase2, a voltage that exceeds the threshold of the MOSFETS34a,34bis present between the gate and the source of the first MOSFET34aand between the gate and the source of the second MOSFET34b. Both MOSFETS34a,34bare therefore in a closed state.

In the exemplary configuration ofFIG.3, the total resistance from the first current sense resistor64aand the first MOSFET34acorresponds at least approximately exactly to the total resistance from the second current sense resistor64band the second MOSFET34b. If both MOSFETS34a,34bare closed, the current I1is therefore divided at least approximately equally over the parallel circuit of the two MOSFETS34a,34b. Therefore, at least approximately I1/2flows through both branches of the circuit. A first measuring amplifier66acan measure the current through the first current sense resistor64adirectly, for example. A second measuring amplifier66bcan measure the current through the second current sense resistor64bdirectly, for example. Alternatively, the first measuring amplifier66acan measure the voltage drop across the first current sense resistor64a. Furthermore, the second measuring amplifier66bcan measure the voltage drop across the second current sense resistor64b. Regardless of the measuring method, the first measuring amplifier66aand the second measuring amplifier66bdetermine an at least approximately equal electrical variable if both the first MOSFET34aand the second MOSFET34bare closed.

After a time, the first control signal V_phase1is set to a voltage of approximately 0V for a time period Vlow1in the first time slot Z1. This corresponds to a low level, also referred to as LOW level (digital 0). In this case, the voltage present between the gate and the source of the first MOSFET34ais, if at all, only very low and is below the threshold of the first MOSFET34a. The MOSFET34atherefore changes to an open state. During the same time period Vlow1of the first time slot Z1, the second control signal V_phase2continues to be at a HIGH level. The second MOSFET34bis therefore still closed. Since the first MOSFET34ais open in the first time period Vlow1of the first time slot Z1and the second MOSFET34bis closed in the first time period Vlow1of the first time slot Z1, the current I1flows at least almost entirely via the branch of the parallel circuit of the two MOSFETs in which the second MOSFET34bis located. The first measuring amplifier64atherefore determines a value of at least approximately 0 as the electrical variable. The second measuring amplifier64bat the same time determines a value which corresponds at least approximately to the current I1or the multiplication of the current I1and the current sense resistor64b. This corresponds to twice the average. The first measuring amplifier64adetermines in the same time period Vlow1a value of at least approximately 0 as the electrical variable.

The second control signal is switched to a low level, LOW level (digital 0), in a second time slot Z2for a time period Vlow2. In this case, the voltage present between the gate and the source of the second MOSFET34bis, if at all, only very low and is below the threshold of the second MOSFET34b. The MOSFET34btherefore changes to an open state. During the same time period Vlow2of the second time slot Z2, the first control signal V_phase1is at a HIGH level. The first MOSFET34ais therefore closed. Since the first MOSFET34ais closed in the time period Vlow2of the second time slot Z2and the second MOSFET34bis open in the time period Vlow2of the second time slot Z2, the current I1flows at least almost entirely via the branch of the parallel circuit of the two MOSFETs in which the first MOSFET34ais located. The first measuring amplifier64atherefore determines as the electrical variable a value which corresponds at least approximately to the current I1or the multiplication of the current I1and the current sense resistor64a. This corresponds to twice the average. The second measuring amplifier64bdetermines in the same time period Vlow2a value of at least approximately 0 as the electrical variable.

If the first MOSFET34aand the second MOSFET34bare each in a closed state, the two measuring amplifiers66a,66b, as described, determine an at least approximately equal value for the measured electrical variable. The averager68forms the average from the measured variables. In the case of equal values, the average of the electrical variable corresponds at least approximately to the measured value itself. Therefore, the operational amplifier70adoes not determine any difference between the variable V_cs1measured by the first measuring amplifier66aand the average V_avg from the averager68and accordingly outputs a HIGH level (a 1). Furthermore, the operational amplifier70bdoes not determine any difference between the variable V_cs2measured by the second measuring amplifier66band the average V_avg from the averager68and accordingly outputs a HIGH level (a 1).

If the first MOSFET34ais in an open state and the second MOSFET34bis in a closed state (see e.g. the time period Vlow1in the first time slot Z1and the third time slot Z3), the first measuring amplifier66adetermines a minimum value of 0 and the second measuring amplifier66bdetermines the maximum value. The averager68forms the average from the measured variables. Therefore, the first operational amplifier70adetermines that the value of the electrical output variable V_cs1of the first measuring amplifier66ais below the average and accordingly outputs a LOW level (digital 0). Furthermore, the operational amplifier70bdetermines that the value of the electrical output variable V_cs2of the second measuring amplifier66bis not below the average from the averager68and accordingly outputs a HIGH level (a 1) (see signal V_comp1).

If the first MOSFET34ais in a closed state and the second MOSFET34bis in an open state (see e.g. the time period Vlow2in the second time slot Z2and the fourth time slot Z4), the first measuring amplifier66adetermines a maximum value and the second measuring amplifier66bdetermines a minimum value of 0. The averager68forms the average from the measured variables. Therefore, the operational amplifier70adetermines that the value of the electrical output variable V_cs1of the first measuring amplifier66ais not below the average and accordingly outputs a HIGH level (digital 1). Furthermore, the operational amplifier70bdetermines that the value of the electrical output variable V_cs2of the second measuring amplifier66bis below the average from the averager68and accordingly outputs a LOW level (digital 0) (see signal V_comp2).

Therefore, when the first MOSFET34ais open, a double peak caused by transit time delays and/or switching delays is obtained as the output variable V_out1of the first XOR gate72aat approximately the time level of the LOW level of the first control signal V_phase1, that is to say approximately at the level of the time period Vlow1in the first time slot Z2and in the third time slot Z3. Therefore, when the second MOSFET34bis open, a double peak is obtained as the output variable V_out2of the second XOR gate72bat approximately the time level of the LOW level of the second control signal V_phase2, that is to say approximately at the level of the time period Vlow2in the second time slot Z2and in the fourth time slot Z4(and likewise in the sixth time slot Z6and the eighth time slot Z8). The outputs of the first XOR gate72aand of the second XOR gate72bare inputted as input variables into an OR gate74. The output of the OR gate74is therefore an overlay of the outputs of the first XOR gate72aand the second XOR gate72b. The output signal V_out3of the OR gate74therefore shows a double peak, which in each case indicates opening of the first or second MOSFET34a,34b, in the first time slot Z1to the fourth time slot Z4(and likewise in the sixth time slot Z6and the eighth time slot Z8).

If it is now assumed, by way of example, that in the fifth time slot Z5, seventh time slot Z7and ninth time slot Z9the first MOSFET34adoes not open correctly even though the first control signal V_phase1assumes a LOW level in the time period Vlow1, the MOSFET34aremains in the closed state in the fifth time slot Z5, seventh time slot Z7and ninth time slot Z9. As explained, the current I1is in this case divided at least approximately equally over the parallel circuit of the MOSFETS34a,34b. A current with a value of at least approximately I1/2therefore flows through each of the MOSFETS34a,34band thus through each current sense resistor64a,64b. The measuring amplifiers66a,66btherefore determine an at least approximately equal value. The two operational amplifiers70a,70btherefore do not determine a difference between the measured values of the measuring amplifiers66a,66band the average. In the fifth time slot Z5, seventh time slot Z7and ninth time slot Z9, the two operational amplifiers70a,70btherefore output a HIGH level for the signals V_comp1, V_comp2even during the time period Vlow1. The XOR operation of the output of the first operational amplifier72awith the first control signal V_phase1therefore leads to a (single) HIGH level approximately during the time period Vlow1of the fifth time slot Z5(V_out1), not to a double peak. The XOR operation of the output of the second operational amplifier72bwith the second control signal V_phase2leads to a LOW level (V_out2). The OR operation of the outputs of the two XOR gates72a,72btherefore leads in the fifth time slot Z5, seventh time slot Z7and ninth time slot Z9in each case to a (single) peak (at least approximately at the level of the time period Vlow1in the fifth time slot Z5, seventh time slot Z7and ninth time slot Z9). This one peak (instead of a double peak caused by transit time delays and/or switching delays with a smaller width of each peak) in the output signal of the OR gate74(V_out3) therefore indicates a fault.

The identification of a fault can be improved by connecting a time delay, which in some cases is referred to in the following text as a time-delay element76, downstream of the OR gate74. The time delay has the result that only peaks with a duration above a predefined time threshold are identified as faults. The duration of the double peaks in the first time slot Z1to the fourth time slot Z4(and likewise in the sixth time slot Z6and eighth time slot Z8) is in each case below the time threshold. Therefore, the output of the time-delay element76outputs a LOW level (see signal V_fehler). By contrast, the duration of the peaks in the fifth time slot Z5, seventh time slot Z7and ninth time slot Z9is above the time threshold. The time-delay element76therefore outputs a HIGH level (see signal V_fehler) for a specific time in the fifth time slot Z5, seventh time slot Z7and ninth time slot Z9.

According to a specific implementation of the time delay, the time-delay element76can be in the form of a switch-on delay or can effect a switch-on delay. In this case, the time-delay element76can effect time-delayed switching on or can switch on with a time delay, for example. The time delay can correspond at least to the magnitude (from the point of view of time) of one of the pulses of the double pulses of the signals Vout1, Vout2, Vout3or can be above that magnitude. As a result, the respective pulses of these double pulses are suppressed or faded out and only the longer pulses (i.e. the pulses with a width greater than the time delay or greater than the width of each peak of the double peak) are outputted, in each case shortened by the magnitude of the time delay in the fault signal V_fehler. This can be seen inFIG.4b, in which a valid fault signal V_fehler is shown. In the signal V_fehler, the rising edge of a fault pulse is always offset or shortened relative to the rising edge of a long peak by the magnitude of the switch-on delay, for example in the signal Vout3(i.e. shortened at least by the width of a pulse of a double pulse/double peak). By contrast, the falling edge of the pulse of the fault signal V_fehler falls at the same time as the corresponding pulse in the signal Vout3, since it is only a switch-on delay and not a switch-off delay. This concerns all time slots with faults, i.e. Z5, Z7and Z9. By contrast, the pulses of each double pulse are suppressed by the switch-on delay. These are ultimately not actual/valid fault pulses.

As a result, the output signal V_fehler of the time-delay element76only shows a peak if there is a fault in the switching of one of the MOSFETS64a,64b. By contrast, transit time delays are suppressed. The output of the time delay76can therefore be referred to as a fault signal V_fehler. By means of an identification circuit, the peaks in the fault signal V_fehler can be identified automatically. On the basis of the peaks and the control signals, the identification circuit can immediately conclude which of the two MOSFETS34a,34bhas not switched correctly. Therefore, not only can the fault be identified promptly, but the component in question can be replaced or another response to eliminate the fault can be taken promptly.

FIGS.3,4aand4bcan be summarized as follows. In the circuit shown inFIG.3, two power semiconductors (MOSFET)34a,34bare connected in parallel with one another together with in each case a current sense resistor (shunt)64a,64b. The two power semiconductors34a,34bare alternately switched off and on by a logic. In the ideal state (fault-free state), at least one power semiconductor34a,34bis always switched on. Via the two shunts64a,64b, the current through each of the two parallel paths is measured via a current measuring amplifier66a,66bfor each path. If both MOSFETs34a,34bare on (closed), approximately the same current (in each case half the load current I1) is measured via both measuring amplifiers66a,66b. As soon as one of the two MOSFETs34a,34bswitches off, the entire load current I1flows via one of the two paths while the other path no longer conducts any current. However, the average of the two currents remains the same. By means of two comparators (operational amplifiers)70a,70b, the output signal V_cs1, V_cs2of the two current measuring amplifiers66a,66bis compared with the average and converted into digital signals by the comparators70a,70b. The signal shape of the comparators70a,70bthus corresponds roughly to the signal sequence V_phase1, V_phase2with which the respective MOSFET34a,34bis controlled. By comparing the control signal V_phase1, V_phase2of the MOSFETs34a,34bwith the output signal V_comp1, V_comp2of the respective comparator70a,70bby means of exclusive OR operation (XOR operation), it is possible to detect whether the MOSFET34a,34bactually switches off. The two XOR signals V_out1, V_out2combined by XOR of the two MOSFETs34a,34bare then combined by an OR operation into a signal V_out3and filtered by a switch-on delay76. The switch-on delay76is advantageous for suppressing incorrect diagnoses triggered by signal transit times and/or switching delays. There is obtained as the output signal V_fehler a pulse sequence which corresponds approximately (although shortened) to the control pulses of the defective MOSFET34a,34b. The output signal V_fehler of the switch-on delay76can then be read in and processed by a higher-level controller (not shown, but see controller28inFIG.2). Alternatively, the pulse sequence can be converted into a static value by a storage element (not shown).

Although the description of the exemplary embodiments ofFIGS.2to4breferred to identifying whether the first semiconductor switch34aand/or the second semiconductor switch34bis correctly transferred from a closed state into an open state, it can correspondingly be identified from the signal profiles whether the first semiconductor switch34aand/or the second semiconductor switch34bis correctly transferred from an open state into a closed state.

The identification of a non-switching semiconductor switch of the first and/or second semiconductor switch34a,34bpermits the use of simple and inexpensive components and it is possible to dispense with a series connection of in each case a further semiconductor switch for redundancy purposes.

Although reference is always made in the description of the exemplary embodiments ofFIGS.2to4bto a first semiconductor switch34aand a second semiconductor switch34b, these exemplary embodiments and the invention in general are not limited to exactly two semiconductor switches connected in parallel. Three or more than three semiconductor switches can likewise be provided. In summary, therefore, at least two semiconductor switches can be present, and at least one non-switching semiconductor switch can be identified from these at least two semiconductor switches connected in parallel.

An advantage of connecting at least a third semiconductor switch in parallel with the first semiconductor switch34aand the second semiconductor switch34bwill now be described with reference toFIGS.3to4bwithout the at least a third semiconductor switch being shown in the figures.

As described, in the first time slot Z1the first semiconductor switch34ais opened if the first control signal V_phase1assumes a LOW level in the time period Vlow1. After the time period Vlow1has passed, the first control signal V_phase1again assumes a HIGH level. The first semiconductor switch34awould in this case close again. However, if the first semiconductor switch34ais defective, the first semiconductor switch34aremains open, that is to say it no longer closes even though the first control signal V_phase1has assumed a HIGH level again. As described, the second semiconductor switch34bis open in the second time slot Z2during the time period Vlow2since the second control signal assumes a LOW level during the time period Vlow2. Consequently, during the time period Vlow2, both the first semiconductor switch34ais open (since it no longer closes even though it should actually be closed) and the second semiconductor switch34bis open (owing to the LOW level of the second control signal V_phase2). Thus, the load switches off (briefly) during the time period Vlow2in time slots Z2, Z4, Z6, Z8.

By contrast, if at least a third semiconductor switch is connected in parallel, this third semiconductor switch—if switched correctly—can permit a kind of emergency operation. This is because the at least a third semiconductor switch will be in its closed state during the time period Vlow2with the aid of at least a third control signal, which assumes a HIGH level during the time period Vlow2. Accordingly, the load is not disconnected from the system and the current supply and is consequently not switched off.