Patent ID: 12211810

REFERENCE NUMBERS

100: drive chip;11: first edge;12: second edge;13: third edge;14: first area;141: empty area;1411: sub empty area;142: dummy pin area;15: second area;151: first sub area;152: second sub area;1521: peripheral pin area;1521a: first peripheral pin area;1521b: second peripheral pin area;1522: central pin area;1: substrate;2: first drive pin;3: second drive pin;4: dummy pin;200: display panel body;201: display area;202: bonding area;203: non-display area;204: fanout area;201: first bonding pad;22: second bonding pad;300: conductive particle.

DESCRIPTION OF EMBODIMENTS OF THE DISCLOSURE

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to appending drawings of the embodiments of the present application. Obviously, the described embodiments are merely a part of embodiments of the present application and are not all of the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by those of ordinary skill in the art without making any inventive effort are within the scope the present application. In addition, it should be understood that the specific embodiments described herein are merely for illustrating and interpreting the present application and the present application is not limited thereto. In the present application, direction words used herein, such as “upper” and “lower”, generally refer to the upper and lower of a device under an actual use or operation state, as the directions shown in the drawings, unless otherwise specified; “inner” and “outer” are for the contour of the device.

Please refer toFIG.1,FIG.2A to2B.FIG.1is a schematic diagram illustrating a first type of planar structure of a drive chip provided in an embodiment of the present application.FIG.2Ais a schematic diagram illustrating a bonding structure of a drive chip and a display panel body provided in an embodiment of the present application.FIG.2Bis a schematic diagram illustrating a cross-section of the drive chip and the display panel body inFIG.2Aalong an A-A line.

The embodiment of the present application provides a drive chip100. The drive chip100includes a first area14and a second area15. The drive chip100includes a substrate1and pins disposed on the substrate1. The density of the pins located in the first area14is lower than the density of the pins located in the second area15. The plurality of pins located in the second area15includes first drive pins2and second drive pins3. The first drive pins2are located at a side of the second area15away from the first area14.

Specifically, there is anisotropic conductive adhesive disposed between the pins and the display panel body200. A plurality of conductive particles are distributed among the anisotropic conductive adhesive. The pins and the display panel body200squeeze the conductive particles300such that electrical conduction is realized.

It can be understood that the density of the pins in the first area14is less than the density of the pins in the second area15such that the first drive pins2disposed in the first area14provides less support than the second drive pins3disposed in the second area15. As such, the substrate1will incline toward the first area14, causing the first drive pins2in the second area15to curl up such that the distance between the display panel body200and the face of the first drive pins2close to the display panel body200increases. As a result, the conductive particles300cannot be squeezed any longer to be deformed, and the first drive pins cannot be bonded to the display panel body200. This causes poor electrical conduction for the first drive pins2.

In view of this, in the embodiment of the present application, the distance d1between the substrate1and the face of the first drive pins2away from the substrate1is greater than the distance d2between the substrate1and the face of the second drive pins3away from the substrate1. The distance is designed in a differentiated manner for the first drive pins2and the second drive pins3. By this, the distance difference (d2−d1) between the two is used to compensate the height difference between the first drive pins and the display panel body200, caused because the first drive pins2are curled up. Therefore, the conductive particles300between the first drive pins2and the display panel body200are made able to be squeezed to be deformed such that it is ensured that the drive chip100can be bonded to the display panel body200normally and it is avoided the occurrence of poor electrical conduction of the conductive particles300.

It needs to be noted that specific location of the first area14and the second area on the drive chip100and specific location where the pins are disposed are not limited in the present application. The concepts proposed in this application is applicable to any situation associated with the “seesaw” effect in above descriptions.

Specifically, in an embodiment, the density of the pins of the first area14is 0, that is, the pins are disposed only in the second area15, no pins are disposed in the first area14, and the first drive pins2are located in the second area15. In another embodiment, the density of the pins of the first area14is greater than 0, that is, the pins are disposed in both the first area14and the second area15. The pins disposed in the first area14provide less support than the pins disposed in the second area15, causing part of the pins disposed in the second area15to curl up. For example, the number of the pins disposed in the first area14is less than the number of the pins disposed in the second area15. Of course, the invention is not limited to the cases enumerated in the embodiments of the present application, and other cases are not detailed herein.

To improve the layout and increase layout space, the embodiments of the present application are illustrated by taking an example of the pins disposed at a same side of the drive chip100. Of course, the invention is not limited to the cases enumerated in the embodiments of the present application, and other cases are not detailed herein.

Please refer toFIG.1again. Specifically, the drive chip100includes a first edge11and a second edge12that are disposed opposite to each other, and two third edges13connecting the first edge11and the second edge12. The first edge11and the second edge12are disposed in parallel. The two third edges13are disposed in parallel.

In the embodiment of the present application, a first direction D1is defined as a direction from the first14to the second area15, that is, the first direction D1is a direction from the first edge11to the second edge12. A second direction D2is perpendicular to the first direction D1.

Specifically, the first area14at least includes an empty area141. The second area15includes a first sub area151and a second sub area152sequentially arranged along the first direction D1. The second sub area152is disposed close to the second edge12. The first sub area151is located between the first area14and the second sub area152. The first drive pins2are located in the second sub area152. The second drive pins3are at least located in the first sub area151.

It can be understood that an area on the display panel body200corresponding to the empty area141is a layout area. Fanout wiring lines of the display panel body200are electrically connected to the first drive pins2and the second drive pins3via this layout area. As a result, the lower bezel of the display panel body200can be saved in space. It benefits an implementation of narrow bezel.

It needs to be noted that the location where the drive chip100curls up depends on the location of the empty area141and the position and layout of the first drive pins2and the second drive pins3. The location where the drive chip100of the present application will be described in detail with reference to specific embodiments.

FIG.3Ais a schematic diagram illustrating a second type of planar structure of a drive chip provided in an embodiment of the present application. The differences betweenFIG.3AandFIG.1are that the first area14further includes a dummy pin area142, the dummy pin area142extends along the second direction D2, and there are a plurality of dummy pins4disposed in the dummy pin area142.

It can be understood that both the first drive pins2and the second drive pins3will transmit electrical signals but the dummy pins4only play a role of support function and will not transmit electrical signals. When the drive chip100is bonded to the display panel body200, the dummy pins4and dummy pads on the display panel body200are connected in a one-to-one correspondence such that the second drive pins3in the second sub area152corresponding to the dummy pin area142are connected to pads on the display panel body200without the occurrence of curling up. Because the dummy pins4are not disposed in the empty area141, the first drive pins2in the second sub area152corresponding to the empty area141cannot be connected to pads on the display panel body200in a one-to-one correspondence, resulting in the occurrence of curling up.

Specifically, the empty area141includes two sub empty areas1411. The two sub empty areas1411are located at two opposite ends of the dummy pin area142, respectively. The two sub empty areas1411are close to the two third edges13, respectively. The second sub area152includes a central pin area1522and two peripheral pin areas1521that are arranged along the second direction D2. The two peripheral pin areas1521are located at two opposite ends of the central pin area1522, respectively. The two peripheral pin areas1521are close to the two third edges13, respectively. The first drive pins2are located in the peripheral pin areas1521. The second drive pins3are located in the first sub area151and the central pin area1522, that is, the location where the drive chip100is curled up is in the peripheral pin areas1521.

In the present embodiment, the first drive pins2in each of the peripheral pin areas1521are arranged in a single row. Specifically, the first drive pins2in the peripheral pin areas are arranged along the second direction D2in a single row. The first drive pins2and the second drive pins3in the central pin area1522are arranged along the second edge12. The first drive pins2and the second drive pins3in the central pin area1522are arranged in a same way. The first drive pins2and the second drive pins3are placed vertically.

It can be understood that in a direction from a location close to the central pin area1522to a location away from the central pin area1522, the more the first drive pins2are distanced from the dummy pins4, the higher the first drive pins2lift up. In the present application, in the aspect of arrangement in horizontal direction, the distance is designed in a differentiated way for the first drive pins2such that the distance between the substrate1and the face of the first drive pins2away from the substrate1increases along a direction from a location close to the central pin area1522to a location away from the central pin area1522, thereby overcoming afore-mentioned drawbacks.

Please refer toFIG.3Bfor an embodiment of the present application.FIG.3Bis a schematic diagram illustrating a third type of planar structure of a drive chip provided in an embodiment of the present application. The differences betweenFIG.3BandFIG.3Aare that the peripheral pin area1521includes a first peripheral pin area1521a, the first drive pins2in the first peripheral pin area1521aare arranged in at least two rows, each row of the first drive pins2includes at least two first drive pins disposed in parallel, wherein the distance between the substrate1and the face of the first drive pins2in the first peripheral pin area1521aaway from the substrate1increases along the first direction D1.

Specifically, the first drive pins2in the first peripheral pin area1521aare arranged along the second direction D2in at least two columns. The fanout wiring lines may be electrically connected to the first drive pins2at an end close to the third edge13from a side face of the first peripheral pin area1521asuch that layout space is saved. It helps reduce the lower bezel of the display panel body200in a further step.

In order to clearly illustrate the solution of the present embodiment, an example of three rows of the first drive pins in the first peripheral pin area1521ais taken below for simplicity.

Along the first direction D1, the first drive pins2are classified into a first row, a second row and a third row in order. The first drive pins2are placed horizontally and the second drive pins3are placed vertically. It can be understood that the first row of the first drive pins2is the nearest to the dummy pins4, and the lifted height is the smallest; the third row of the first drive pins2is the farthest from the dummy pins4, and the lifted height is the largest; the distance from the second row of the first drive pins2to the dummy pins4is between that of the first row of the first drive pins2and that of the second row of the first drive pins2, and the lifted height is also between that of the first row of the first drive pins2and the second row of the first drive pins2.

Base on this, the present embodiment utilizes a relation, the distance between the substrate1and the face of the first row of the first drive pins2away from the substrate1<the distance between the substrate1and the face of the second row of the first drive pins2away from the substrate1<the distance between the substrate1and the face of the third row of the first drive pins2away from the substrate1, that is, a design of gradually increasing along the first direction D1is adopted for the distance between the substrate1and the face of rows of the first drive pins2away from the substrate1for overcoming the afore-mentioned drawbacks.

Further, the distance d1between the substrate1and the face of the first drive pins2in the first peripheral pin area1521aaway from the substrate1increases along a direction from a location close to the central pin area1522to a location away from the central pin area1522for being adaptive to the first drive pins2with different degrees of curling up along the horizontal direction (i.e., the second direction D2).

Please refer toFIG.3Cfor an embodiment of the present application.FIG.3Cis a schematic diagram illustrating a fourth type of planar structure of a drive chip provided in an embodiment of the present application. The differences betweenFIG.3CandFIG.3Bare that an arrangement of “single row plus multiple rows” is adopted for the first drive pins2in the present embodiment in order to ensure that all the lifted first drive pins2can be bonded to the display panel body200.

Specifically, the peripheral pin area1521further includes a second peripheral pin area1521b. The second peripheral pin area1521bis located between the first peripheral pin area1521aand the central pin area1522. The first drive pins2in the second peripheral pin area1521bare arranged along the second direction D2in a single row. The distance between the substrate1and the face of the first drive pins2in the second peripheral pin area1521baway from the substrate1increases along a direction from a location close to the central pin area1522to a location away from the central pin area1522.

Please refer toFIG.3Dfor an embodiment of the present application.FIG.3Dis a schematic diagram illustrating a fifth type of planar structure of a drive chip provided in an embodiment of the present application. The differences betweenFIG.3DandFIG.3Aare that the peripheral pin area1521is inclined with respect to the central pin area1522, each of the peripheral pin areas1521includes a first end E1connecting to the central pin area1522and a second end E2away from the central pin area1522, and the distance from the first end E1to the first area14is less than the distance from the second end E2to the first area14.

Specifically, the distance from the first end E1to the first edge11is less than the distance from the second end E2to the first edge11; on the second direction D2, an included angle formed between connection lines between the first end E1and the second end E2of the peripheral pin areas1521is an obtuse angle.

In the present embodiment, the first drive pins2in the peripheral pin areas1521may also adopt the “single-row” arrangement. A part of each fanout wiring line may extend to a bonding area of the display panel body200corresponding to the second area such that a part of a fanout area of the display panel body200overlaps with the bonding area. In this way, a decrease of the lower bezel of the display panel body200can be realized, thereby realizing an extra narrow bezel design on the promise that high resolution pursued in the market is satisfied and the performance of the drive chip100is not lowered.

Please refer toFIG.3Efor an embodiment of the present application.FIG.3Eis a schematic diagram illustrating a sixth type of planar structure of a drive chip provided in an embodiment of the present application. The differences betweenFIG.3EandFIG.3Dare that in the present embodiment, the “multiple-row” arrangement is adopted for the first drive pins2in the peripheral pin area1521. Details of the distance between the substrate1and the face of the first drive pins2in the multiple-row arrangement away from the substrate1may be referred to that for the first drive pins2in the multiple-row arrangement in the afore-described embodiments shown inFIG.4B, which are not repeated herein.

Please refer toFIG.1for an embodiment of the present application. The differences betweenFIG.1andFIG.3Aare that the empty area141occupies the whole first area14, the first drive pins2are located in the whole second sub area152, and the second drive pins3are located in the first sub area151. That is, in this situation, the location where the drive chip is curled up is the whole second sub area152.

Specifically, since no dummy pins4are disposed in the first area14, all the pins in the second sub area152will lift up. All the pins in the second sub area152are the second drive pins3. The distance d1between the substrate1and the face of the first drive pins2away from the substrate1is greater than the distance d2between the substrate1and the face of the second dummy pins3away from the substrate1for overcoming the drawback of curling-up of the second drive pins3.

Please refer toFIG.4Afor an embodiment of the present application.FIG.4Ais a schematic diagram illustrating a seventh type of planar structure of a drive chip provided in an embodiment of the present application. The differences between theFIG.4AandFIG.3Dare that the empty area141is the whole first area14, the second sub area152includes the central pin area1522and the two peripheral pin areas1521that are arranged along the second direction D2, the two peripheral pin areas1521are located at two opposite sides of the central pin area1522, respectively, the first drive pins2are located in the peripheral pin areas1521, the second drive pins3are located in the first sub area151and the central pin area1522, that is, the location where the drive chip100is curled up is in the peripheral pin areas1521.

Each of the peripheral pin areas1521is inclined with respect to the central pin area1522, each of the peripheral pin areas1521includes a first end E1connecting to the central pin area1522and a second end E2away from the central pin area1522, and the distance from the first end E1to the first area14is less than the distance from the second end E2to the first area14.

Specifically, the distance from the first end E1to the first edge11is less than the distance from the second end E2to the first edge11; on the second direction D2, an included angle formed between connection lines between the first end E1and the second end E2of the peripheral pin areas1521is an obtuse angle.

In the present embodiment, the first drive pins2in the peripheral pin area1521are arranged from the first end E1to the second end E2in a single row. The distance d1between the substrate1and the face of the first drive pins2away from the substrate1increases along a direction from a location close to the central pin area1522to a location away from the central pin area1522.

It can be understood that in the present embodiment, no dummy pins4are disposed in the first area14; however, the first drive pins2are inclined, and the second drive pins3in the second sub area152are disposed in a middle of the drive chip100. Therefore, the second drive pins3in the second sub area152will not lift up. Only the first drive pins2will lift up. In the present application, in the direction along the connection line between the first end E1and the second end E2, the distance is designed in a differentiated way for the first drive pins2such that it is adaptive to different degrees of curling-up along the direction of connection line for the first drive pins2.

Please refer toFIG.4Bfor an embodiment of the present application.FIG.4Bis a schematic diagram illustrating an eighth type of planar structure of a drive chip provided in an embodiment of the present application. The differences betweenFIG.4BandFIG.4Aare that the first drive pins in the peripheral pin area1521are arranged in at least two rows, each row of the first drive pins2includes at least two first drive pins disposed in parallel; the distance between the substrate1and the face of the first drive pins2in the peripheral pin area1521away from the substrate1increases along the first direction D1. In the present application, a design of gradually increasing is adopted for the distance between the substrate1and the face of rows of the first drive pins2away from the substrate1for being adaptive to different degrees of curling-up along the first direction D1for the first drive pins2.

Further, the distance d1between the substrate1and the face of each row of the first drive pins2in the peripheral pin area1521away from the substrate1increases along a direction from a location close to the central pin area1522to a location away from the central pin area1522for being adaptive to different degrees of curling-up along the direction of connection line for each row of the first drive pins2.

Referring toFIGS.1,3A to3E and4A to4B, the first drive pins2and the second drive pins3in the second sub area152and the second drive pins3in the first sub area151are interlaced with each other for optimizing the layout space.

It needs to be noted that in the present application, the distance d1between the substrate1and the face of the first drive pins2away from the substrate1is greater than the distance between the substrate1and the face of the second drive pins3away from the substrate1, and more specifically, the thickness of the first drive pins2is greater than the thickness of the second drive pins3.

Specifically, the difference between the thickness of the first drive pins2and the thickness of the second drive pins3is greater than or equal to 0.1 micrometer.

FIG.5is a schematic diagram illustrating the planar structure of a display panel provided in an embodiment of the present application. The embodiment of the present application further provides a display panel. The display panel includes a display panel body200and the drive chip100of the afore-described embodiment. The display panel body200includes a display area201and a bonding area202located at a side of the display area201. The drive chip100is disposed in the bonding area202. The bonding area202includes a plurality of first bonding pads and a plurality of second bonding pads. The first bonding pads are electrically connected to the first drive pins2, and the second bonding pads are electrically connected to the second drive pins3.

Specifically, the display panel body200further includes a non-display area203. The non-display area203surrounds the display area201. The bonding area202is located in the non-display area203. At least one set of GOA (gate driving circuit) wiring lines are disposed in the non-display area203. The GOA wiring lines are illustrated by two sets of symmetrical GOA wiring lines, for example. Each of the two sets of the GOA wiring lines includes a parallel segment located outside of the display area201and located parallel to an edge of the display area201, and an inclined segment located in the non-display area203and pointing to the drive chip100. The inclined segment of the GOA wiring lines connects to the drive chip100for inputting scan signals, and the parallel segment of the GOA wiring lines connects to scan lines of pixel rows for outputting the scan signals.

The display area201includes a plurality of signal lines extending along the first direction D1and arranged along the second direction D2. For example, the signal lines may include data signal lines for transmitting data signals, or may include other signal lines known in the existing arts, such as touch control signal lines. They are not limited in the embodiments of the present application. The non-display area203includes a fanout area204. The fanout area204is located between the display area201and the bonding area202. A plurality of wiring lines are disposed in the fanout area204. One end of the fanout wiring lines is electrically connected to corresponding signal lines, and the other end of the fanout wiring lines is electrically connected to the first bonding pads and the second bonding pads. In such a way, the display panel body200is electrically connected to the drive chip100such that the drive chip100can propagate signals to the signal lines.

Specifically, the display panel body200may be a liquid crystal display panel. The display panel body200may also be an organic light-emitting diode display panel. Specifically, the display panel body200is a fringe field switching (FFS) liquid crystal display panel. It can be understood that the display panel body200may also be an in-plane switching (IP) liquid crystal display panel or a vertical alignment liquid crystal display panel.

Please refer toFIG.5andFIG.2B. The embodiment of the present application further provides a display panel. The display panel includes the display panel body200and the drive chip100. The display panel body200includes the display area201and the bonding area202located at a side of the display area201. The drive chip100is located in the bonding area202. The drive chip100includes the substrate1and the first drive pins2and the second drive pins3disposed on the substrate1. Both the first drive pins2and the second drive pins3are electrically connected to the display panel body200.

The drive chip100is in a lifted-up state. The distance between the substrate1and the face of the first drive pins2away from the substrate1is greater than the distance between the substrate1and the face of the second drive pins3away from the substrate1such that the height difference between the first drive pins2and the display panel body200, caused from the lifted first drive pins2, is compensated, playing a role of balancing by supporting the drive chip100. It is avoided the occurrence of poor electrical conduction of the conductive particles300, and it is ensured that the drive chip100can be bonded to the display panel body200normally.

The beneficial effects are described as follows. In the drive chip and the display panel provided in the present application, the distance between the substrate and the face of the pins on the drive chip away from the substrate is designed in a differentiated manner. The distance between the substrate and the face of the lifted-up first drive pins away from the substrate is greater than the distance between the substrate and the face of the non-lifted-up second drive pins away from the substrate such that the height difference between the first drive pins and the display panel body, caused because the first drive pins are lifted up, is compensated, playing a role of balancing by supporting the drive chip. It is avoided the occurrence of poor electrical conduction of the conductive particles, and it is ensured that the drive chip can be bonded to the display panel body normally.

While the preferred embodiments of the present application have been illustrated and described in detail, various modifications and alterations can be made by persons skilled in this art. The embodiment of the present application is therefore described in an illustrative but not restrictive sense. It is intended that the present application should not be limited to the particular forms as illustrated, and that all modifications and alterations which maintain the spirit and realm of the present application are within the scope as defined in the appended claims.