Patent ID: 12199001

DETAILED DESCRIPTION

In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.

Several embodiments of semiconductor devices, packages, and/or assemblies in accordance with the present technology can include one or more memory devices mounted over a logic device (e.g., GPU). The vertically stacked structure can include a thermal management configuration to reduce heat transfer between the logic device and the memory devices.

In some embodiments, the vertically stacked structure can include a thermally conductive layer (e.g., graphene structure) on the logic device for laterally (e.g., horizontally) transferring the heat generated by the logic device. A heat spreader can be mounted over the logic device and attached to peripheral portions of the thermally conductive layer. Accordingly, the heat generated by the logic device can be routed around the memory devices via the thermally conductive layer and dissipated over the memory devices using the heat spreader.

In some embodiments, the vertically stacked structure can include a thermal-insulation interposer between the logic device and the memory devices. The thermal-insulation interposer can be configured to reduce transfer of heat between the logic device and the memory devices. In one or more embodiments, the thermal-insulation interposer can include glass, ceramics, or other thermal insulators. In one or more embodiments, the thermal-insulation interposer can include a cavity configured to further reduce the heat transfer. For example, the cavity can maintain a vacuum condition for reducing the heat transfer. Also, the cavity can be filled with phase change material (PCM) that can absorb thermal energy. The PCM can include substances with relatively high heat of fusion that change the physical state (via, e.g., melting, boiling, solidifying, etc.) based on absorbing the thermal energy. Details regarding the thermal management configuration are described below.

FIG.2Ais a schematic cross-sectional view of a semiconductor device assembly200(“assembly200”) taken along line2A-2A ofFIG.2B, andFIG.2Bis a schematic cross-sectional view of the semiconductor device assembly200shown inFIG.2Ataken along line2B-2B ofFIG.2Ain accordance with embodiments of the technology. Referring toFIG.2AandFIG.2Btogether, the assembly200can include a package configured for high-performance operations, such as 3-dimensional graphics processing and/or network processing. The assembly200can include a logic device202and a set of memory devices204mounted over a substrate206(e.g., a printed circuit board (PCB)). In some embodiments, the logic device202can include a graphics processing unit (GPU). In some embodiments, the memory devices204can include high-bandwidth memory (HBM) devices.

As illustrated inFIG.2A, the assembly200can include the memory devices204, which can be mounted over the logic device202. The memory devices204can overlap the logic devices202, such as by being laterally within peripheral boundaries of the logic device202. Accordingly, the lateral footprint of the assembly200(i.e., the footprint in the view ofFIG.2B) can be less than that of the conventional assembly100ofFIG.1Aby eliminating laterally adjacent devices. The assembly200can also include vertical electrical connectors208(e.g., wires and/or conductive pillars) that electrically couple the memory devices204with the logic device202.

The assembly200can include a thermal management system for reducing the heat transfer between the logic device202and the memory devices204. For example, the thermal management system of the assembly200can include a thermally conductive layer210attached to a top surface of the logic device202. In some embodiments, the thermally conductive layer210can include a graphene structure that includes carbon atoms arranged along one or more planar layers (e.g., arranged in a hexagonal lattice along a horizontal plane). Accordingly, the graphene structure can provide relatively efficient transfer (e.g., in comparison to metallic material) of thermal energy across a transverse plane relative to an upper surface203of the logic device202(e.g., a horizontal plane parallel to the upper surface203of the logic device202). In one or more embodiments, the graphene structure can be attached to the logic device202using an adhesive211. For example, the graphene structure can include one or more depressions or holes. In some embodiments, the adhesive211(e.g., epoxy or thermal interface material (TIM)) can be applied such that it fills the holes and contacts the structures above and/or below the graphene structure (e.g., the logic device202, the memory devices204, and/or an interposer). Accordingly, when the adhesive material is cured (via, e.g., heat, light, and/or chemical agents), the graphene structure can be at least partially encapsulated by the adhesive211and affixed relative to the vertically adjacent structures.

The thermal management system of the assembly200can also include a heat spreader212mounted over the logic device202and the memory devices204. The heat spreader212can include a dissipation portion (e.g., fins) above the memory devices204. The dissipation portion can be integrally connected to peripheral columns/walls that extend vertically and attach to (via, e.g., TIM or other thermally conductive adhesives) peripheral portions of the heat spreader212. In some embodiments, the peripheral walls of the heat spreader212can be directly attached (via, e.g., direct contact and/or TIM) to a top surface of the thermally conductive layer210on peripheral portions thereof. In other embodiments, the peripheral walls of the heat spreader212can be directly attached to corresponding peripheral surfaces of the thermally conductive layer210. As such, the thermal energy from the logic device202preferentially flows through the peripheral portions of the heat spreader212and is dissipated via the dissipation portion. Accordingly, the heat from the logic device202can be directed around the memory devices204using the thermally conductive layer210and the heat spreader212, thereby reducing the heat transfer between the logic device202and the memory devices204(e.g., inhibiting heat generated by the logic device202from flowing to the memory devices204).

In some embodiments, the heat spreader212can include an opening213(e.g., as shown inFIG.2B) at least partially surrounded/defined by the peripheral walls of the heat spreader212. For example, the opening can allow air to flow across the logic device202and/or the memory devices204to further remove thermal energy. In other embodiments, the peripheral walls of the heat spreader212can encircle/surround the memory devices204along a lateral plane. Accordingly, an amount of contact between the heat spreader212and the logic device202and/or the thermally conductive layer210can be increased.

As a further example of the thermal management system, the assembly200can include a thermal-insulation interposer214disposed between the logic device202and at least a portion of the memory devices204. In some embodiments, the memory devices204can be directly attached to the thermal-insulation interposer214, such as via a thermally insulative adhesive. In some embodiments, the thermal-insulation interposer214can be over the thermally conductive layer210.

The thermal-insulation interposer214can include thermal insulators, such as glass or ceramic materials, and be configured to block and reduce heat transfer between the logic device202and the memory devices204. The thermal-insulation interposer214can be superimposed directly under the memory devices204such that the memory devices204are located at least partially within the peripheral edges of the thermal-insulation interposer214. In other words, the thermal-insulation interposer214can extend up to or beyond peripheral edges of the memory devices204(e.g., the memory devices204can be completely within a boundary defined by the lateral periphery of the thermal-insulation interposer214). Accordingly, the thermal-insulation interposer214reduces or eliminates direct lines of sight between the logic device202and the memory devices204to block or at least impede (e.g., reduce) the heat generated by the logic device202from reaching the memory devices204.

In some embodiments, the thermal-insulation interposer214can include a cavity216to further reduce the absorption or transfer of the thermal energy in or across the thermal-insulation interposer214. For example, the cavity216can be under a vacuum condition. Also, the cavity216can be filled with insulative gases and/or PCM.

The thermal-insulation interposer214can include openings215through which vertical interconnects can pass to electrically connect vertically adjacent structures. For example, the electrical connectors208can be located within the openings215. In some embodiments, the openings215of the thermal-insulation interposer214can be directly over (e.g., horizontally overlapping) the holes in the thermally conductive layer210. In other embodiments, the openings of the thermal-insulation interposer214and the holes in the thermally conductive layer210can be horizontally offset, such as to eliminate any vertically direct line-of-sight between the logic device202and the memory devices204. Accordingly, the electrical connectors208can include bends and/or can be aligned diagonally to pass through the openings of the thermal-insulation interposer214and the holes in the thermally conductive layer210.

FIG.3is a flow chart illustrating a method300of manufacturing a semiconductor device assembly in accordance with embodiments of the technology. The method300can be for manufacturing the semiconductor device assembly including a set of stacked semiconductor devices with a thermal management configuration for preventing heat transfer between the devices. For example, the method300can be for manufacturing the assembly200ofFIG.2A.

At block302, a substrate (e.g., the substrate206ofFIG.2A) can be provided. For example, a PCB can be provided. At block304, a logic device (e.g., the logic device202ofFIG.2A) can be mounted on the substrate. For example, a GPU can be directly attached to a top surface of the substrate based on reflowing solder and/or curing an adhesive disposed between the GPU and the substrate.

At block306, a thermally conductive layer (e.g., the thermally conductive layer210ofFIG.2A) can be provided over the logic device. Continuing with the above example, a graphene structure can be placed over the GPU. A thermally conductive adhesive material (e.g., epoxy and/or TIM) can be applied below, above, and/or within holes of the graphene structure. The adhesive material can be later cured to affix the graphene structure to the GPU. Accordingly, the graphene structure can directly contact the GPU through the thermally conductive adhesive and draw thermal energy out of the GPU. As described above, the graphene structure can be configured to transfer the thermal energy along a plane (e.g., horizontally as shown inFIG.2A).

At block308, a thermal-insulator interposer (e.g., the thermal-insulator interposer214ofFIG.2A) can be provided over the thermally conductive layer and the logic device. As shown inFIG.2B, a thermally insulative structure (e.g., glass, ceramic, etc.) can be placed over the thermally conductive layer. Along directions (e.g., in a plane parallel to the top surface203of the logic device202), the thermal-insulator interposer can extend up to, without extending beyond, peripheral edges of the thermally conductive layer. In some embodiments, the thermally insulative structure can contact the thermally conductive adhesive described above. Accordingly, as illustrated at block310, various structures (e.g., the logic device, the graphene structure, and/or the thermally insulative interposer) can be affixed relative to each other. In other words, the thermally conductive adhesive can be cured (via, e.g., chemical agents, light, temperature, etc.), thereby affixing the structures contacting the adhesive.

At block312, one or more memory devices (e.g., the memory devices204ofFIG.2A) can be attached over the thermal-insulator interposer and the logic device. In some embodiments, the memory devices can be attached directly (via, e.g., adhesive material) to the thermal-insulator interposer. In some embodiments, attaching the memory devices can include electrically coupling the memory devices to the logic device. At block314, one or more connectors (e.g., the vertically extending electrical connectors208ofFIG.2A) can be connected to the memory devices and/or the logic device. In some embodiments, the memory devices and/or the logic devices can be provided with conductors (e.g., wires and/or metallic columns) attached thereto. The thermally conductive layer and/or the thermal-insulator interposer can be provided with holes and/or openings therein. When placing/attaching the structures, the conductors can be placed within the holes and/or the openings. Accordingly, the thermal-insulator interposer and/or the thermally conductive layer can surround the conductors along a horizontal plane. The conductors can extend through the holes/openings and vertically across the thermally conductive layer and/or the thermal-insulator interposer, and thereby extend between the logic device and the memory devices. The conductors can be connected, such as based on reflowing solder, to the memory devices and the logic devices.

In some embodiments, the openings/holes in the thermally conductive layer and the thermal-insulator interposer can be aligned. In other embodiments, the openings/holes in the thermally conductive layer and the thermal-insulator interposer can be offset such that the holes/openings are not concentric or directly over each other, thereby reducing and/or eliminating a direct line-of-sight between the memory devices and the logic device. The conductors can extend, at least partially, along a horizontal direction based on the offset.

At block316, a heat spreader/sink (e.g., the heat spreader212ofFIG.2A) can be attached over the logic device202. The heat spreader212can include the dissipation portion and vertical portions. The heat spreader212can be placed such that the dissipation portion is over the memory devices204with the vertical portions horizontally adjacent to the peripheral sides of the memory devices204. The vertical portions of the heat spreader212can vertically extend past/across the thermal-insulator interposer214, and they can be attached to the thermally conductive layer. In some embodiments, the vertical portions of the heat spreader212can be attached (via, e.g., TIM) to a top surface of the thermally conductive layer. In other embodiments, the vertical portions of the heat spreader212can be attached to corresponding peripheral surface portions of the thermally conductive layer.

Accordingly, the thermal management system described above reduces and/or prevents heat transfer between vertically stacked devices. As such, the assembly200can include the memory devices204(e.g., the HBM devices) mounted over the logic device202(e.g., the GPU) without the heat from the logic device202affecting the memory devices204or vice versa. Thus, the assembly200can provide a reduced footprint in comparison to conventional assemblies (e.g., the assembly100ofFIG.1A) while reducing heat transfer between the logic device202and the memory devices204.

Any one of the semiconductor devices described above with reference toFIGS.2A-3can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system490shown schematically inFIG.4. The system490can include a semiconductor device400(“device400”) (e.g., a semiconductor device, package, and/or assembly), a power source492, a driver494, a processor496, and/or other subsystems or components498. The device400can include features generally similar to those devices described above. The resulting system490can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems490can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of the system490may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system490can also include remote devices and any of a wide variety of computer-readable media.

This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. In some cases, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although steps of methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the present technology may have been disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein, and the invention is not limited except as by the appended claims.

Throughout this disclosure, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Similarly, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the terms “comprising,” “including,” and “having” are used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. Reference herein to “one embodiment,” “an embodiment,” “some embodiments” or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.