Patent ID: 12205555

DETAILED DESCRIPTION OF EMBODIMENTS

In order to make the purpose, technical solutions, and effects of the present application clearer and more specific, the following further describes the present application in detail with reference to the accompanying figures and examples. It should be understood that the specific embodiments described here are only used to explain the present application, and are not used to limit the present application.

Please refer toFIGS.2and3, as shown inFIG.2, this embodiment provides a gate driving circuit. The gate driving circuit includes a plurality of cascaded gate driving units, and wherein a Nth stage gate driving unit configured to output a Nth stage gate driving signal G(N) includes a pull-up control module10and a node signal control module20. An output terminal of the pull-up control module10is electrically connected to a first pull-up node Q. A first input terminal of the node signal control module20is configured to receive a forward scan control signal U2D. A second input terminal of the node signal control module20is configured to receive a reverse scan control signal D2U. A first control terminal of the node signal control module20is configured to receive a first gate electrode driving signal. A second control terminal of the node signal control module20is configured to receive the second gate electrode driving signal. An output terminal of the node signal control module20is electrically connected to a pull-down node P.

It is understandable that in the gate driving circuit provided in this embodiment, by adjusting the signals received by the first input terminal, the second input terminal, the first control terminal, and the second control terminal of the node signal control module20to realize an original driving sequence without using clock signals, which reduces a number of clock signal lines, and reduces a space occupied by the frame. At the same time, because the currently driving time sequence can also be realized without using the clock signals, an overall load and an overall power consumption of the clock signals can be reduced.

It should be noted that a first gate driving signal can be, but is not limited to one of a N+1th stage gate driving signal, a N+2th stage gate driving signal G(N+2), a N+3th stage gate driving signal, and a N+4th stage gate driving signal, etc. Correspondingly, the second gate driving signal can be, but is not limited to one of a N−1th stage gate driving signal, a N−2th stage gate driving signal G(N−2), a N−3th stage gate driving signal, and a N−4th stage driving signal.

In one of the embodiments, the node signal control module20includes a first transistor NT3and a second transistor NT4. One of a source electrode and a drain electrode of the first transistor NT3is configured to receive the forward scan control signal U2D. A gate electrode of the first transistor NT3is configured to receive the first gate electrode driving signal. One of a source electrode and a drain electrode of the second transistor NT4is configured to receive the reverse scan control signal D2U. A gate electrode of the second transistor NT4is configured to receive the second gate electrode driving signal. Another one of the source electrode and the drain electrode of the second transistor NT4is electrically connected to the another one of the source electrode and the drain electrode of the first transistor NT3, and the pull-down node P.

It can be understood that, in this embodiment, there are only two thin film transistors in the node signal control module20. Compared with the structure shown inFIG.1, this embodiment can reduce one thin film transistor. Therefore, the gate driving circuit provided by this embodiment can further reduce a space occupied by the frame, which is beneficial to realize a narrower frame.

In one of the embodiments, a channel type of the first transistor NT3is the same as a channel type of the second transistor NT4. For example, the first transistor NT3and the second transistor NT4may both be N-channel thin film transistors, specifically, It can be an oxide thin film transistor.

In one of the embodiments, an input terminal of the pull-up control module10is electrically connected to a first input terminal of the node signal control module20. A control terminal of the pull-up control module10is electrically connected to a second control terminal of the pull-up control module10.

It is understandable that in this embodiment, the input terminal of the pull-up control module10and the first input terminal of the node signal control module20can share the forward scan control signal U2D, and the gate driving circuit can save one input signal. Correspondingly, a line space of one input signal line can be reduced, and a space occupied by the frame of the gate driving circuit can be further reduced. In a same way, the control terminal of the pull-up control module10and the second control terminal of the pull-up control module10can share the second gate driving signal. The gate driving circuit can save one input signal, and correspondingly, a line space of one input signal line can be reduced, the space occupied by the frame of the gate driving circuit can be further reduced.

The pull-up control module10may include a transistor NT1, one of a source electrode and a drain electrode of the transistor NT1is electrically connected to the one of the source electrode and the drain electrode of the first transistor NT3. A gate electrode of the transistor NT1is electrically connected to the gate electrode the second transistor NT4. Another one of the source electrode and the drain electrode of the transistor NT1is electrically connected to the first pull-up node Q.

It is understandable that the one of the source electrode and the drain electrode of the transistor NT1and the one of the source electrode and the drain electrode of the first transistor NT3can share the forward scan control signal U2D. The gate electrode of the transistor NT1and gate electrode of the second transistor NT4can share the second gate driving signal. The gate driving circuit can correspondingly save two input signals, and correspondingly, a line space of the two input signal lines can be reduced.

In one of the embodiments, the Nth stage gate driving unit further includes a reverse scanning auxiliary module30. An input terminal of the reverse scanning auxiliary module30is electrically connected to a second input terminal of the node signal control module20. A control terminal of the reverse scanning auxiliary module30is electrically connected to a first control terminal of the node signal control module20. The output terminal of the reverse scan auxiliary module30is electrically connected to the first pull-up node Q.

It can be understood that, in this embodiment, the input terminal of the reverse scan auxiliary module30and the second input terminal of the node signal control module20can share the reverse scan control signal D2U, and the gate driving circuit can further save one input signal, correspondingly, can further reduce a line space of an input signal line, and further reduce the space occupied by the frame of the gate driving circuit. In the same way, the control terminal of the reverse scan auxiliary module30and the first control terminal of the node signal control module20can share the first gate driving signal. The gate driving circuit can further save one input signal, and correspondingly, it can further reduce a line space of an input signal line, and further reduce the space occupied by the frame of the gate driving circuit.

The reverse scan auxiliary module30may include a transistor NT2, one of a source electrode and a drain electrode of the transistor NT2is electrically connected to one of the source electrode and the drain electrode of the second transistor NT4. A gate electrode of the transistor NT2is electrically connected to the gate electrode of the first transistor NT3. Another one of the source electrode and the drain electrode of the transistor NT2is electrically connected to the first pull-up node Q.

It should be noted that one of the source electrode and the drain electrode of the transistor NT2and one of the source electrode and the drain electrode of the second transistor NT4can share the reverse scan control signal D2U. The gate electrode of the transistor NT2and the gate electrode of first transistor NT3can share the first gate driving signal.

In one of the embodiments, the Nth stage gate driving unit further includes a first pull-down module40. An input terminal of the first pull-down module40receives a low electrical potential signal VGL. A control terminal of the first pull-down module40is electrically connected to an output terminal of the reverse scanning auxiliary module30. An output terminal of the first pull-down module40is electrically connected to the pull-down node P.

In one of the embodiments, the first pull-down module40may include a transistor NT6, one of a source electrode and a drain electrode of the transistor NT6configured to receive a low electrical potential signal VGL. A gate electrode of the transistor NT6is electrically connected to the another one of the source electrode and the drain electrode of the transistor NT2. Another one of the source electrode and the drain electrode of the transistor NT6is electrically connected to the pull-down node P.

In one of the embodiments, the Nth stage gate driving unit further includes a third transistor NT7. One of a source electrode and a drain electrode of the third transistor NT7is electrically connected to the first pull-up node Q. A gate electrode of the third transistor NT7is configured to receive a first global control signal GAS. Another one of the source electrode and the drain electrode of the third transistor NT7is electrically connected to a second pull-up node QA.

In one of the embodiments, the Nth stage gate driving unit further includes a first capacitor C1and a fourth transistor NT9. One terminal of the first capacitor C1is electrically connected to the first pull-up node Q. Another terminal of the first capacitor C1is configured to receive the low electrical potential signal VGL. A gate electrode of the fourth transistor NT9is electrically connected to the second pull-up node QA. One of a source electrode and a drain electrode of the fourth transistor NT9is configured to receive a first clock signal CK (N). Another one of the source electrode ad the drain electrode of the fourth transistor NT9is configured to output the Nth stage gate driving signal G(N).

In one of the embodiments, the Nth stage gate driving unit further includes a fifth transistor NT5, a sixth transistor NT10, a seventh transistor NT11, an eighth transistor NT12, a ninth transistor NT13, a tenth transistor NT14, and a second capacitor C2. One of a source electrode and a drain electrode of the fifth transistor NT5is electrically connected to the another terminal of the first capacitor C1. A gate electrode of the fifth transistor NT5is electrically connected to the pull-down node P. Another one of the source electrode and the drain electrode of the fifth transistor NT5is electrically connected to the first pull-up node Q. One of a source electrode and a drain electrode of the sixth transistor NT10is electrically connected to one of the source electrode and the drain electrode of the fifth transistor NT5. Another one of the source electrode and the drain electrode of the sixth transistor NT10is electrically connected to the another one of the source electrode and the drain electrode of the fourth transistor NT9. A gate electrode of the sixth transistor NT10is electrically connected to the pull-down node P. A gate of the seventh transistor NT11is electrically connected to one of a source electrode and a drain electrode of the seventh transistor NT11and receives a second global control signal GAS1. Another one of the source electrode and the drain electrode of the seventh transistor NT11is electrically connected to the another one of the source electrode and the drain electrode of the sixth transistor NT10. A gate electrode of the eighth transistor NT12is electrically connected to the gate electrode of the seventh transistor NT11. One of a source electrode and a drain electrode of the eighth transistor NT12is electrically connected to the one of source electrode and the drain electrode of the sixth transistor NT10. Another one of the source electrode and the drain electrode of the eighth transistor NT12is electrically connected to the pull-down node P. A gate electrode of the ninth transistor NT13and one of the source electrode and the drain electrode of the ninth transistor NT13receive a reset signal RESET. Another one of the source electrode and the drain electrode of the ninth transistor NT13is electrically connected to the pull-down node P. A gate electrode of the tenth transistor NT14receives a third global control signal GAS2. One of a source electrode and a drain electrode of the tenth transistor NT14is electrically connected to the another one of the source electrode and the drain electrode of the eighth transistor NT12. Another one of the source electrode and the drain electrode of the tenth transistor NT14is electrically connected to the another one of the source electrode and the drain electrode of the sixth transistor NT10. One terminal of the second capacitor C2is electrically connected to the pull-down node P. Another terminal of the second capacitor C2is electrically connected to the one of the source electrode and the drain electrode of the eighth transistor NT12.

It should be noted that the transistors NT1to the tenth transistor NT14in the above-mentioned embodiment can be, but are not limited to, N-channel thin film transistors. The transistors NT1to the tenth transistor NT14in the above-mentioned embodiment can also be P-channel thin film transistors, in this case, the electrical potential of each signal needs to be inverted.

The operating process of the above-mentioned gate driving circuit is shown inFIG.3, and the details are as follows:

Before stage t1: Before a start of a frame, the reset signal RESET will be set high, the ninth transistor NT13will be turned on, an electrical potential of the pull-down node P will be pre-pulled high, the fifth transistor NT5and the sixth transistor NT10will be turned on or conducted, and electrical potentials of the first pull-up node Q and the second pull-up node QA are pulled low, the fourth transistor NT9is turned off, and an initial electrical potential of the gate driving signal G(N) of the Nth stage is low. After that, the reset signal RESET is set low, and the ninth transistor NT13is turned off, waiting for an arrival of a stage t1.

Stage t1: The gate driving signal G(N−2) of the N−2th stage is at a high electrical potential, the transistor NT1is turned on, the forward scanning control signal U2D at the same electrical potential as the high potential signal VGH is input, an electrical potential of the first pull-up node Q is pulled up to the high electrical potential, the first capacitor C1is charged, the transistor NT6is turned on, an electrical potential of the pull-down node P is pulled down, the fifth transistor NT5and the sixth transistor NT10are turned off, and an electrical potential of the second pull-up node QA changes to the high electrical potential.

Stage t2: The gate driving signal G(N−2) of the N−2th stage becomes a low electrical potential, the transistor NT1is turned off, and the electrical potential of the first pull-up node Q is maintained at the high electrical potential through energy saved in the first capacitor C1, the electrical potential of the second pull-up node QA is maintained at the high electrical potential.

Stage t3: An electrical potential of the clock signal CK (N) turns high, and the electrical potential of the second pull-up node QA is affected by a bootstrap effect of the fourth transistor NT9, its electrical potential will rise and the fourth transistor NT9is fully turned on. At this time, the clock signal CK (N) can be output in full swing as the Nth gate driving signal G(N).

Stage t4: The electrical potential of the clock signal CK (N) turns to the low electrical potential, the electrical potential of the second pull-up node QA remains at the high electrical potential, and the first transistor NT3is still fully turned on. At this time, the electrical potential of the Nth gate driving signal G(N) is quickly pulled down to the low electrical potential.

Stage t5: The gate driving signal G(N+2) of the N+2 stage is at high electrical potential, the transistor NT2, the first transistor NT3are turned on, the electrical potential of the first pull-up node Q is pulled down, and the electrical potential of the pull-down node P is pulled to the high electrical potential, the fifth transistor NT5is turned on, the electrical potentials of the first pull-up node Q and the potential of the second pull-up node QA are pulled down, and the fourth transistor NT9is turned off. The sixth transistor NT10is turned on, and the gate driving signal G(N) of the Nth stage is maintained at the low electrical potential. During this process, the second capacitor C2is charged up, keeping the fifth transistor NT5, and the sixth transistor NT10in an on state, and maintaining a stability of the output.

It should be noted that the electrical potential of the aforementioned low potential signal VGL is the same as the electrical potential of the reverse scan control signal D2U, and both are low electrical potentials. The low electrical potential can turn off or close the N-channel thin film transistor. The electrical potential of the high electrical potential signal VGH is the same as that of the reverse scan control signal D2U, both are high electrical potentials, which can turn on or electrically conduct a N-channel thin film transistor.

In one of the embodiments, the present application provides a display panel including the gate driving circuit in at least one of the above embodiments, and the gate driving circuit is positioned in a non-display region of the display panel.

It is understandable that in the display panel provided in this embodiment, by adjusting the signals received by the first input terminal, the second input terminal, the first control terminal, and the second control terminal of the node signal control module20to realize an original driving sequence without using clock signals, which reduces a number of clock signal lines, and reduces a space occupied by the frame. At the same time, because the currently driving time sequence can also be realized without using the clock signals, an overall load and an overall power consumption of the clock signals can be reduced

It can be understood that, for those of ordinary skill in the art, equivalent replacements or changes can be made according to the technical solutions of the present application and its inventive concept, and all these changes or replacements shall fall within a protection scope of the appended claims of the present application.