Patent ID: 12205856

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIG.1AtoFIG.1Fare cross-sectional views of a method of forming a semiconductor structure in accordance with a first embodiment.

Referring toFIG.1A, a method of forming a semiconductor structure100(as shown inFIG.1F) includes following steps. First, an initial structure illustrated inFIG.1Ais provided. The initial structure includes a semiconductor substrate102, a device layer103, an interconnect structure104, a passivation layer110, a conductive material112, and a cap material114.

In some embodiments, the semiconductor substrate102may include silicon or other semiconductor materials. Alternatively, or additionally, the semiconductor substrate102may include other elementary semiconductor materials such as germanium. In some embodiments, the semiconductor substrate102is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide or indium phosphide. In some embodiments, the semiconductor substrate102is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate102includes an epitaxial layer. For example, the semiconductor substrate102has an epitaxial layer overlying a bulk semiconductor.

In some embodiments, the device layer103is formed over the semiconductor substrate102in a front-end-of-line (FEOL) process. The device layer103includes a wide variety of devices. In some embodiments, the devices comprise active components, passive components, or a combination thereof. In some embodiments, the devices may include integrated circuits devices. The devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the device layer103includes a gate structure, source and drain regions, and isolation structures, such as shallow opening isolation (STI) structures (not shown). In the device layer103, various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors or memories and the like, may be formed and interconnected to perform one or more functions. Other devices, such as capacitors, resistors, diodes, photodiodes, fuses and the like may also be formed over the semiconductor substrate102. The functions of the devices may include memory, processors, sensors, amplifiers, power distribution, input and/or output circuitry, or the like.

Referring toFIG.1A, the interconnect structure104is formed over the device layer103. In detail, the interconnect structure104includes an insulating material106and a plurality of metal features108. The metal features108are formed in the insulating material106and electrically connected to the device layer103. A portion of the metal features108, such as a top metal feature108a, is exposed by the insulating material106. In some embodiments, the insulating material106includes an inner-layer dielectric (ILD) layer on the device layer103, and at least one inter-metal dielectric (IMD) layer over the ILD layer. In some embodiments, the insulating material106includes silicon oxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, benzocyclobutene (BCB), SiLK™ (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric material, or combinations thereof. In some alternatively embodiments, the insulating material106may be a single layer or multiple layers. In some embodiments, the metal features108include plugs and metal lines. The plugs may include contacts formed in the ILD layer, and vias formed in the IMD layer. The contacts are formed between and in connect with the device layer103and a bottom metal line. The vias are formed between and in connect with two metal lines. The metal features108may be made of tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or a combination thereof. In some alternatively embodiments, a barrier layer (not shown) may be formed between the metal features108and the insulating material106to prevent the material of the metal features108from migrating to or diffusion to the device layer103. A material of the barrier layer includes tantalum, tantalum nitride, titanium, titanium nitride, cobalt-tungsten (CoW) or a combination thereof, for example.

Referring toFIG.1A, the passivation layer110is formed over the interconnect structure104. In some embodiments, the passivation layer110includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO) or a combination thereof and is formed by a suitable process such as spin coating, CVD or the like. In an embodiment, the passivation layer110may be a single layer structure, a bilayer structure, or a multilayer structure. As shown inFIG.1A, the passivation layer110includes a passivation material110aand a passivation material110bformed over the passivation material110b. The passivation materials110aand110bhave different materials. For example, the passivation material110amay include silicon nitride, while the passivation material110bmay include polyimide (PI) or any material different from silicon nitride.

Referring toFIG.1A, the conductive material112is formed over the passivation layer110and electrically connected to the top metal features108aand108bby plugs111which penetrate through the passivation layer110. The conductive material112and the metal features108may have different materials. In some embodiments, the conductive material112is softer than the metal features108. The conductive material112and the plugs111may have a same material. In some embodiments, the conductive material112and the plugs111respectively include a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof, which may be formed by patterning the passivation layer110to form a plurality openings to reach the metal features108, depositing a metal material layer to fill in the openings and cover the passivation layer110through a suitable process such as electro-chemical plating process, CVD, atomic layer deposition (ALD), PVD or the like, and then patterning the metal material layer.

Referring toFIG.1A, the cap material114is formed over the conductive material112. The cap material114may be a dielectric material, for example. In some embodiments, the cap material114includes a nitrogen-containing material, such as silicon oxynitride, silicon nitride or a combination thereof, and has a thickness of 50 nm to 100 nm. In another embodiment, the cap material114is referred to as an anti-reflective coating (ARC) layer, which may include an organic ARC material (e.g., polymer resin), an inorganic ARC material (e.g., SiON), or a combination thereof. In some alternatively embodiments, the cap material114may be a single layer or multiple layers and may be formed by a suitable process such as CVD, ALD, or the like.

Referring toFIG.1B, a mask pattern116is formed over the cap material114. In some embodiments, the mask pattern116is used to define a position of a to-be-formed pad122(as shown inFIG.1C). In one embodiment, the mask pattern116includes photoresist and is formed by a suitable process, such as a spin coating and a photolithography process.

Referring toFIG.1BandFIG.1C, after the mask pattern116is formed, a first etching process is performed by using the mask pattern116as an etching mask to remove portions of the cap material114and the conductive material112, so as to expose the passivation material110b. In some embodiments, the first etching process may include a dry etching process, a wet etching process, or a combination thereof. In the case, as shown inFIG.1C, a pad122and a cap layer124disposed over the pad122are formed. The pad122is electrically connected to the top metal feature108aby the plugs111. In some embodiments, the pad122may be aligned with or partially overlapped with the top metal feature108a. Although only one pad122and one cap layer124are illustrated inFIG.1C, the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of the pad122and the cap layer124may be adjusted by the need. After the pad122and the cap layer124are formed, the mask pattern116is removed.

Referring toFIG.1CandFIG.1D, a second etching process is performed on the cap layer124to expose the pad122. In one embodiment, the second etching process may include an isotropic etching process. In another embodiment, the second etching process may include a wet etching process or a combination of a wet etching process and a dry etching process. The wet etching process may be performed by using an etching solution which includes halogen, such as F, Cl, Br, or a combination thereof. For example, the etching solution may include a HF solution, a HCl solution, a HBr solution, or a combination thereof. The dry etching process may be performed by using an etching gas which includes halogen, such as F, Cl, Br, or a combination thereof. In the case, as shown inFIG.1D, a top surface or top portion122tof the pad122is modified, so that a resistance value of the top portion122tof the pad122is less than a resistance value of a bottom portion122bof the pad122.

In alternative embodiments, some residues123may be formed in or on the pad122. Herein, the residues123may be a chemical residue during the second etching process. Accordingly, the residues123may be from the cap layer124and the pad122which may have the nitrogen-containing material, such as silicon oxynitride, silicon nitride or a combination thereof, and the metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof. In some alternative embodiments, a resistance value of the pad122with the residues123is greater than a resistance value of the other pad without the residues (as shown inFIG.7). In an embodiment, the residues123may blanketly or continuously cover the pad122. Alternatively, the residues123may partially or non-continuously cover the pad122. In other embodiments, the charge accumulation may occur on the top surface or top portion122tof the pad122, which may affect the resistance value of the top portion122tof the pad122.

As shown inFIG.1D, after the cap layer124is removed, a circuit probing (CP) test is performed on the pad122. Specifically, a probe128may be used to electrically couple to the pad122for wafer or die testing to check whether the die is a good die. In some embodiments, the CP test is also referred to as wafer acceptance testing (WAT). In some embodiments, the pad122is used for electrical testing to check whether a first die101illustrated inFIG.1Dis a good die, but the disclosure is not limited thereto. The first die101may be selected to test different properties of the wafer or the die, such as leakage current, breakdown voltage, threshold voltage and effective channel length, saturation current, contact resistance and connections. It should be noted that the first die101is selected to proceed the following process when the first die101is identified as a known good die (KGD). In the case, as shown inFIG.1D, a probe mark127is formed at the top portion122tof the pad122, and the probe mark127may be a recess concaving or recessing into the top surface122tof the pad122. That is, the probe mark127has a concave surface or a curve concaving downward. Since the probe128may press or squeeze the residues123to electrically connect to the pad122during the CP test, the residues123underlying the probe mark127may be squeezed to two sides of the probe mark127after the CP test, as shown inFIG.1D. That is, the top portion122tunderlying the probe mark127may have a lower resistance than the top portion122taside the probe mark127. In some embodiments, the probe mark127may have a depth D1 of 50 nm to 2000 nm, and a width W1 of 1000 nm to 50000 nm. In some alternative embodiments, a ratio of the width W1 to the depth D1 is 0.5 to 1000. Herein, the depth D1 is a vertical distance between a topmost point (or the top surface122t) and a bottommost point of the probe mark127.

Referring toFIG.1E, after the CP test, a protective layer125is formed over the pad122. In detail, the protective layer125conformally covers and is in direct contact with the top surface122tand sidewalls122sof the pad122, the probe mark127, and a top surface of the passivation layer110. In the case, the protective layer125conformally covering the probe mark127has another concave surface corresponding to the concave surface of the probe mark127. Herein, when a layer described as “conformally cover”, the layer is formed with a uniform thickness and extends along the surface topography of the underlying layer or structure. In some embodiments, the protective layer125may include a dielectric layer, such as silicon nitride, silicon oxynitride, or a combination thereof, and has a thickness of 50 nm to 100 nm. When the thickness of the protective layer125is greater than the depth D1 of the probe mark127, the protective layer125may fill up the probe mark127. That is, a lowest point of a top surface of the protective layer125directly over the probe mark127may be higher than the top surface122tof the pad122. On the other hand, when the thickness of the protective layer125is less than the depth D1 of the probe mark127, the protective layer125may not fill up the probe mark127. That is, the lowest point of the top surface of the protective layer125directly over the probe mark127may be lower than the top surface122tof the pad122. In other embodiments, the lowest point of the top surface of the protective layer125directly over the probe mark127and the top surface122tof the pad122may be at the same level.

In another embodiment, the protective layer125is referred to as an anti-reflective coating (ARC) layer, which may include an organic ARC material (e.g., polymer resin), an inorganic ARC material (e.g., SiON), or a combination thereof. In some alternatively embodiments, the protective layer125may be a single layer or multiple layers and may be formed by a suitable process such as CVD, ALD, or the like. In other embodiments, the protective layer125and the cap layer124may have different materials.

After forming the protective layer125, a first bonding structure135is formed over the protective layer125. Specifically, as shown inFIG.1E, after the first die101is identified as the known good die, a bonding dielectric material130a(or referred as a first bonding dielectric material) is disposed over a front side101aof the first die101. In some embodiments, as shown inFIG.1E, the bonding dielectric material130acovers the protective layer125and fills in the probe mark127. In some embodiments, the bonding dielectric material130aincludes silicon oxide, silicon nitride, a polymer or a combination thereof. The bonding dielectric material130ais formed by a suitable process such as spin coating, CVD or the like.

InFIG.1E, a blocking layer130bis then formed to cover the bonding dielectric material130a. In some embodiments, the blocking layer130bincludes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and is formed by a suitable process such as CVD, ALD, or the like. In some embodiments, a thickness of the blocking layer130bis 50 μm to 100 μm.

InFIG.1E, another bonding dielectric material130c(or referred as a second bonding dielectric material) is formed over the blocking layer130b. That is, the blocking layer130bis disposed between the bonding dielectric materials130aand130c. In some embodiments, a material of the blocking layer130bis different from that of the bonding dielectric material130aand130c. For example, the blocking layer130bmay include silicon nitride, while the bonding dielectric materials130aand130cmay include silicon oxide. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the bonding dielectric material130aand130cand the blocking layer130bhave different materials. In some embodiments, the bonding dielectric material130cincludes silicon oxide, silicon nitride, polymer or a combination thereof. The bonding dielectric material130cis formed by a suitable process such as spin coating, CVD or the like. Thereafter, a planarization process may be performed on the bonding dielectric material130c, so that a top surface of the bonding dielectric material130chas a flat surface, in some embodiments. In alternative embodiments, the planarization process includes a CMP process, an etching back process, or a combination thereof.

After a bonding dielectric layer130which includes the bonding dielectric materials130aand130cand the blocking layer130bbetween the bonding dielectric materials130aand130cis formed, a bonding metal layer132is formed in the bonding dielectric layer130, thereby accomplishing a semiconductor structure100, as shown inFIG.1F. In some embodiments, the semiconductor structure100may include a semiconductor die, a semiconductor chip, a semiconductor wafer, or a combination thereof. In the embodiment, the semiconductor structure100includes the first die101and the first bonding structure135over the front side101aof the first die101. The first die101may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chips, for example.

InFIG.1F, the bonding metal layer132corresponds to and is electrically connected to the pad122. Herein, the bonding metal layer132may be landed on and in contact with the pad122. In some embodiments, the bonding metal layer132includes a via plug134and a metal feature136. The metal feature136is a via plug having a larger area than the via plug134, for example. As shown inFIG.1F, the via plug134penetrates through the bonding dielectric material130aand the protective layer125to land on and contact the pad122. The metal feature136penetrates through the bonding dielectric material130cand the blocking layer130bto connect to the via plug134. In other words, the metal feature136is electrically connected to the pad122through the via plug134. The bonding metal layer132is electrically connected to the top metal feature108athrough the pad122and the plugs111. In some embodiments, the bonding metal layer132is formed by a dual damascene method. In addition, although only one bonding metal layer132is illustrated inFIG.1F, the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of the bonding metal layer132may be adjusted by the need. For example, the number of the bonding metal layer132is plural, and the bonding metal layers132may be arranged as an array landing on the pad122.

In general, the bonding metal layer132may be formed by a trench first process, a via hole first process, or a self-aligned process, which is described in detail as below.

In some embodiments, the bonding metal layer132is formed as following steps (referred as the trench first process). The bonding dielectric material130cand the blocking layer130bare patterned by lithography and etching processes to form a trench137therein. The trench137corresponds to the pad122, which means the trench137may be aligned with or partially overlapped with the pad122. During the etching process, the blocking layer130bserves as an etching stop layer, and thus the blocking layer130bis exposed or penetrated by the trench137. Next, the bonding dielectric material130ais patterned by another lithography and etching processes with the protective layer125as an etching stop layer and then the protective layer125is etched to form a via hole133therein. In the embodiment, the protective layer125is referred to as an etching stop layer for forming the via hole133. In one embodiment, the etching process may include an anisotropic etching process with a plurality of etching steps, which are used to remove multiple layers with different materials. That is, the bonding dielectric material130aand the protective layer125may be removed by a plurality of etching steps with different etching gases. In another embodiment, the etching process may include a dry etching process. The dry etching process may be performed by using an etching gas which includes O2, N2, CH4, or a combination thereof. In the case, the dry etching process is able to further remove a portion of the residues123, so that the via hole133contacts with the pad122, and the protective layer125may be used to control a depth of the via hole133and avoid the pad122from being damaged during the etching process. The via hole133may expose the pad122. Thereafter, a conductive material layer and a barrier material layer (not shown) are formed on the bonding dielectric material130c, and fills into the trench137and the via hole133. The conductive material layer on the bonding dielectric material130cis then removed by a planarization process such as a CMP process, and thus the via plug134and the metal feature136are formed in the via hole133and the trench137respectively. In some alternative embodiments, the trench137may be referred to as a greater via hole than the via hole133.

In some other embodiments, the bonding metal layer132is formed as following steps (referred as a via hole first process). The bonding dielectric materials130aand130c, the blocking layer130band the protective layer125are patterned by lithography and etching processes to form via hole133. In the case, the protective layer125is referred to as an etching stop layer for forming the via hole133. In one embodiment, the etching process may include an anisotropic etching process. In another embodiment, the etching process may include a dry etching process. The dry etching process may be performed by using an etching gas which includes O2, N2, CH4, or a combination thereof. Next, the bonding dielectric material130cand the blocking layer130bare patterned by lithography and etching processes to form the trench137therein. During the etching process, the blocking layer130bis serves as an etching stop layer, and thus the blocking layer130bis exposed or penetrated by the trench137. Thereafter, the conductive material layer is formed and the planarization process is performed.

In alternative embodiments, the bonding metal layer132is formed as following steps (referred as the self-aligned process). After the bonding dielectric material130ais formed, the blocking layer130bis formed and patterned by lithography and etching processes to form via hole patterns therein. Next, the bonding dielectric material130cis formed over the blocking layer130bwith the via hole patterns. The bonding dielectric material130cfills into the via hole patterns of the blocking layer130band is in contact with the bonding dielectric material130a. Thereafter, a patterned mask with trench patterns is formed on the bonding dielectric material130cby a lithography process, some of the trench patterns are corresponding to the via hole patterns of the blocking layer130b. Thereafter, an etching process is performed on the bonding dielectric material130cby using the blocking layer130bas an etching stop layer, so that the trench137is formed. In one embodiment, the etching process may include an anisotropic etching process. In another embodiment, the etching process may include a dry etching process. The dry etching process may be performed by using an etching gas which includes O2, N2, CH4, or a combination thereof. At the same time, the bonding dielectric material130aand the protective layer125are etched by using the blocking layer130bwith the via hole patterns as a hard mask, so that via hole133is formed in the bonding dielectric material130aand the protective layer125, and self-aligned with the trench137. In the case, the protective layer125is referred to as an etching stop layer for forming the via hole133. Thereafter, the conductive material layer is formed and the planarization process is performed.

InFIG.1F, the blocking layer130bhas the same pattern as the bonding dielectric material130cand both have trench137. However, depending on the process, the blocking layer130bmay have the same pattern as the bonding dielectric material130aand both have the via hole133as indicated by the dashed lines. In other word, a bottom of the trench137over the pad122exposes a portion of the blocking layer130b, and the blocking layer130bunder the bottom of the trench137has a pattern of the via hole133.

As shown inFIG.1F, in one embodiment, a portion of the pad122(with the probe mark127) may be referred to as a test pad for the CP test, while another portion of the pad122(without the probe mark127) may be referred to as a connect pad which is electrically connected to or in contact with the bonding metal layer132. Specifically, the bonding metal layer132is landed over another portion of the pad122and separated from the probe mark127by a distance122dgreater than zero. That is, the bonding metal layer132is not in direct contact with the probe mark127. In the case, the connect pad is able to transfer the signal from the first die101to an overlying die. In some embodiments, the distance122dmay be less than a width of the pad122; however, the embodiments of the present disclosure are not limited thereto.

FIG.2AtoFIG.2Bare cross-sectional views of a method of forming a 3DIC structure in accordance with a second embodiment.

Referring toFIG.2A, a semiconductor structure200is provided. In detail, the semiconductor structure200includes a second die201and a second bonding structure235disposed over a front side201aof the second die201. In some embodiments, the semiconductor structure200may include a semiconductor die, a semiconductor chip, a semiconductor wafer, or a combination thereof. The second die201may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chips, for example. The second die201and the first die101may be the same type of dies or different types of dies.

In some embodiments, the second die201is similar to the first die101. That is, the second die201includes a semiconductor substrate202, a device region203, an interconnect structure204(including an insulating material206and a plurality of metal features208), a passivation layer210(including passivation materials210aand210b), a pad222, a probe mark227at a top portion of the pad222, and a protective layer225. The arrangement, material and forming method of the second die201are similar to the arrangement, material and forming method of the first die101. Thus, details thereof are omitted here. The first die101and the second die201illustrated inFIG.1Fmay have different sizes. Herein, the term “size” is referred to the length, width, or area. For example, as shown inFIGS.1F and2A, the length of the second die201is greater than the length of the first die101. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the size of the second die201may be the same as the size of the first die101.

In some embodiments, the second bonding structure235includes a bonding dielectric layer230, a first bonding metal layer232, a second bonding metal layer242, and a dummy metal feature238. In detail, the first bonding metal layer232includes a via plug234and a metal feature236. The via plug234penetrates through the bonding dielectric material230aand the protective layer225to land on and contact the second pad222. The metal feature236penetrates through the bonding dielectric material230cand the blocking layer230bto connect to the via plug234. In other words, the first bonding metal layer232is electrically connected to the top metal feature208a(or the interconnect structure204) by the pad222and the plugs211.

Similarly, the second bonding metal layer242includes a via plug244and a metal feature246. The via plug244penetrates through the bonding dielectric material230a, the protective layer225, and the passivation layer210to land on and contact the top metal feature208b. The metal feature246penetrates through the bonding dielectric material230cand the blocking layer230bto connect to the via plug244. That is, the second bonding metal layer242is electrically or physical connected to the top metal feature208b(or the interconnect structure204). In the case, a height of the second bonding metal layer242is greater than a height of the first bonding metal layer232. In the embodiment, as shown inFIG.2A, a height of the via plug244is greater than a height of the via plug234, while a height of the metal feature246is equal to a height of the metal feature236.

On the other hand, the dummy metal feature238is optionally formed aside the first bonding metal layer232. The dummy metal feature238is disposed in the bonding dielectric material230cand the blocking layer230band exposed by the bonding dielectric material230c. Herein, when elements are described as “dummy”, the elements are electrically floating or electrically isolated from other elements. For example, as shown inFIG.2A, the dummy metal feature238is electrically floating. In some embodiments, the dummy metal feature238is formed by a single damascene method.

In some embodiment, the dummy metal feature238and the metal features236and246are at substantially the same level. That is, tops of the dummy metal feature238and the metal feature236and246are substantially coplanar with the top surface of the bonding dielectric material230c.

In some embodiments, the first bonding metal layer232and the second bonding metal layer242may include copper, copper alloys, nickel, aluminum, tungsten, a combination of thereof. The dummy metal feature238may include copper, copper alloys, nickel, aluminum, tungsten, a combination of thereof. In some embodiments, the first bonding metal layer232, the second bonding metal layer242, and the dummy metal feature238may have the same material. In some alternatively embodiments, the first bonding metal layer232, the second bonding metal layer242, and the dummy metal feature238may have different materials.

In some embodiments, the first bonding metal layer232, the second bonding metal layer242, and the dummy metal feature238are formed simultaneously. In some other embodiments, the first bonding metal layer232, the second bonding metal layer242, and the dummy metal feature238are successively formed. The first bonding metal layer232, the second bonding metal layer242, and the dummy metal feature238are formed by a trench first process, a via hole first process, or a self-aligned process.

For example, the first bonding metal layer232, the second bonding metal layer242, and the dummy metal feature238are formed as following steps (referred as the trench first process). The bonding dielectric material230cand the blocking layer230bare patterned by lithography and etching processes to form trenches237,247, and239therein. The trench237corresponds to the pad222and the trench247corresponds to the top metal feature208b. During the etching process, the blocking layer230bserves as an etching stop layer, and thus the blocking layer230bis exposed or penetrated by the trenches237,247, and239. Next, the bonding dielectric material230ais patterned by another lithography and etching processes with the protective layer225as an etching stop layer and then the protective layer225is etched to form a via hole233therein. At the same time, the bonding dielectric material230a, the protective layer225, and the passivation layer210are patterned by the same lithography and etching processes to form a via hole243therein. In the embodiment, the etching process may include a dry etching process with a plurality of etching steps, which are used to remove multiple layers with different materials. That is, the protective layer225is referred to as an etching stop layer for forming the via holes233and243. Specifically, the via hole233may stop on the protective layer225until the via hole243reaches the protective layer225during a first etching step. A second etching step is then performed to remove portions of the protective layer225and the passivation layer210. In the second etching step, the pad222is referred to as an etching stop layer, namely, the via hole233may stop on the pad222until the via hole243reaches the top metal feature208b. Further, the second etching step is able to further remove a portion of the residues223to contact the pad222. As above, the protective layer225may be used to control depths of the via holes233and243, so that the via holes233and243with different depths are formed simultaneously. In other embodiments, the first bonding metal layer232, the second bonding metal layer242, and the dummy metal feature238may be formed in the via hole first process and the self-aligned process at the same time and are illustrated in above embodiments. Thus, details thereof are omitted here.

From another perspective, the semiconductor structure200may include a first region R1 and a second region R2. The pad222and the first bonding metal layer232contacting the pad222are located in the first region R1. The second bonding metal layer242is located in the second region R2. The structure in first region R1 is similar to the semiconductor structure100illustrated inFIG.1F. However, the embodiments of the present disclosure are not limited thereto. The structure in the first region R1 may be replaced by another structure (as shown inFIG.6).

Referring toFIG.2B, another semiconductor structure200′ is provided. In detail, the semiconductor structure200′ includes another second die201′ and another second bonding structure235′ disposed over a front side201a′ of the second die201′. The second dies201and201′ may be the same type of dies or different types of dies. The arrangement, material and forming method of the second die201′ and the second bonding structure235′ are similar to the arrangement, material and forming method of the second die201and the second bonding structure235. Thus, details thereof are omitted here.

Referring toFIG.2B, the semiconductor structure200′ is further turned upside down and mounted onto the semiconductor structure200. That is, the second die201′ and the second die201are face-to-face bonded together via the second bonding structure235′ and the second bonding structure235to form the 3DIC structure10(or referred as a die stack structure10). However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the second die201′ and the second die201may be face-to-back bonded together. Hereinafter, the second die201′ of the semiconductor structure200′ is referred to as a top die201′, and the second die201of the semiconductor structure200is referred to as a bottom die201.

In some embodiments, before the top die201′ is bonded to the bottom die201, the second bonding structure235′ and the second bonding structure235are aligned, so that the dummy metal features238are bonded together, the first bonding metal layers232are bonded together, the second bonding metal layers242are bonded together, and the bonding dielectric layers230are bonded together. In some embodiments, the alignment of the second bonding structure235′ and the second bonding structure235may be achieved by using an optical sensing method. After the alignment is achieved, the second bonding structure235′ and the second bonding structure235are bonded together by a hybrid bonding to form a hybrid bonding structure35.

The second bonding structure235′ and the second bonding structure235are hybrid bonded together by the application of pressure and heat. It is noted that the hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding such as dielectric-to-dielectric bonding or fusion bonding. As shown inFIG.2A, the hybrid bonding structure35includes the dummy metal features238bonded together by metal-to-metal bonding, the first bonding metal layers232bonded together by metal-to-metal bonding, the second bonding metal layers242bonded together by metal-to-metal bonding, and the bonding dielectric layers230bonded together by non-metal-to-non-metal bonding. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the second bonding structure235′ and the second bonding structure235may be bonded together by other bonding, such as fusion bonding.

FIG.3AtoFIG.3Dare cross-sectional views of a method of forming a semiconductor structure in accordance with a third embodiment.

Referring toFIG.3AandFIG.3B, a structure301′ is followed by the structure illustrated inFIG.1C. After the structure301′ is formed, a circuit probing (CP) test is performed on the pad122which the cap layer124is thereon. Specifically, a probe128may penetrate the cap layer124to electrically couple to the pad122for wafer or die testing to check whether the die is a good die. In some embodiments, the pad122is used for electrical testing to check whether a third die301illustrated inFIG.3Bis a good die, but the disclosure is not limited thereto. It should be noted that the third die301is selected to proceed the following process when the third die301is identified as a known good die (KGD). In the case, as shown inFIG.3B, a probe mark327is formed on a top surface122tof the pad122, and the probe mark327may be a recess concaving or recessing from a top surface124tof the cap layer124into the pad122. In some embodiments, the probe mark327may have a depth D2 of 50 nm to 2000 nm, and a width W2 of 1000 nm to 50000 nm. Herein, the depth D2 is a vertical distance between a topmost point (or the top surface124tof the cap layer124) and a bottommost point of the probe mark327. In some alternative embodiments, the depth D2 may be greater than the depth D1 illustrated inFIG.1D, and the width W2 may be greater than or equal to the width W1 illustrated inFIG.1Dby using the same probe in the same CP test apparatus.

Referring toFIG.3C, after the CP test, a protective layer125is formed over the pad122and the cap layer124. In detail, the protective layer125conformally covers and is in direct contact with the top surface124tof the cap layer124, the probe mark327, sidewalls122sof the pad122, and a top surface of the passivation layer110. In some embodiments, the protective layer125may include a dielectric layer, such as silicon nitride, silicon oxynitride or a combination thereof, and has a thickness of 50 nm to 100 nm. When the thickness of the protective layer125is greater than the depth D2 of the probe mark327, the protective layer125may fill up the probe mark327, as shown inFIGS.3B and3C. That is, a lowest point of a top surface of the protective layer125directly over the probe mark327may be higher than the top surface124tof the cap layer124. On the other hand, when the thickness of the protective layer125is less than the depth D2 of the probe mark327, the protective layer125may not fill up the probe mark327. That is, the lowest point of the top surface of the protective layer125directly over the probe mark327may be lower than the top surface124tof the cap layer124. In other embodiments, the lowest point of the top surface of the protective layer125directly over the probe mark327and the top surface124tof the cap layer124may be at the same level.

In another embodiment, the protective layer125is referred to as an anti-reflective coating (ARC) layer, which may include an organic ARC material (e.g., polymer resin), an inorganic ARC material (e.g., SiON), or a combination thereof. In some alternatively embodiments, the protective layer125may be a single layer or multiple layers and may be formed by a suitable process such as CVD, ALD, or the like. In other embodiments, the protective layer125and the cap layer124may have different materials. That is, an interface may be formed between the protective layer125and the cap layer124. In the case, as shown inFIG.3C, a dielectric material covering on the top surface122tof the pad122may have a thickness T1, wherein the dielectric material includes the protective layer125and the cap layer124. Another dielectric material covering on the sidewalls122sof the pad122may have a thickness T2, wherein the another dielectric material includes the protective layer125. The other dielectric material covering on the probe mark327may have a thickness T3, wherein the other dielectric material includes the protective layer125. In the embodiment, the thickness T1 may be greater than the thickness T2 or T3, and the thickness T2 may be equal to or less than the thickness T3.

Referring toFIG.3D, after forming the protective layer125, a first bonding structure135is formed over the protective layer125or a front side301aof the third die301, thereby forming a semiconductor structure300. The first bonding structure135includes a bonding metal layer132formed in a bonding dielectric layer130. The bonding metal layer132penetrates the bonding dielectric layer130, the protective layer125, and the cap layer124to land on and contact the pad122. The arrangement, material and forming method of the bonding metal layer132and the bonding dielectric layer130are illustrated in above embodiments. Thus, details thereof are omitted here.

FIG.4AtoFIG.4Dare cross-sectional views of a method of forming a semiconductor structure in accordance with a fourth embodiment.

Referring toFIG.4A, a structure401′ is similar to the structure illustrated inFIG.1B. A difference therebetween lies in that the structure401′ includes a protective material115disposed between the conductive material112and the cap material114. In some embodiments, the protective material115may include a dielectric layer, such as silicon nitride, silicon oxynitride or a combination thereof, and has a thickness of 50 nm to 100 nm. In another embodiment, the protective material115is referred to as an anti-reflective coating (ARC) layer, which may include an organic ARC material (e.g., polymer resin), an inorganic ARC material (e.g., SiON), or a combination thereof. In some alternatively embodiments, the protective material115may be a single layer or multiple layers and may be formed by a suitable process such as CVD, ALD, or the like. In other embodiments, the protective material115and the cap material114may have different materials.

Referring toFIG.4AandFIG.4B, after the mask pattern116is formed, a first etching process is performed by using the mask pattern116as an etching mask to remove portions of the cap material114, the protective material115, and the conductive material112, so as to expose the passivation material110b. In some embodiments, the first etching process may include a dry etching process, a wet etching process, or a combination thereof. In the case, as shown inFIG.4B, a pad122, a cap layer124, and a protective layer125disposed between the pad122and the cap layer124are formed. The pad122is electrically connected to the top metal feature108aby the plugs111. In some embodiments, the pad122may be aligned with or partially overlapped with the top metal feature108a. Although only one pad122, one protective layer125, and one cap layer124are illustrated inFIG.4B, the embodiments of the present disclosure are not limited thereto. In other embodiments, the number of the pad122, the protective layer125, and the cap layer124may be adjusted by the need.

Referring toFIG.4BandFIG.4C, after the mask pattern116is removed, a circuit probing (CP) test is performed on the pad122. Specifically, a probe128may penetrate the cap layer124and the protective layer125to electrically couple to the pad122for wafer or die testing to check whether the die is a good die. In some embodiments, the pad122is used for electrical testing to check whether a fourth die401illustrated inFIG.4Cis a good die, but the disclosure is not limited thereto. It should be noted that the fourth die401is selected to proceed the following process when the fourth die401is identified as a known good die (KGD). In the case, as shown inFIG.4C, a probe mark427is formed on a top surface122tof the pad122, and the probe mark427may be a recess concaving or recessing from a top surface124tof the cap layer124through the protective layer125and then into the pad122. In some embodiments, the probe mark427may have a depth D3 of 100 nm to 2000 nm, and a width W3 of 1000 nm to 50000 nm. Herein, the depth D3 is a vertical distance between a topmost point (or the top surface124tof the cap layer124) and a bottommost point of the probe mark427. In some alternative embodiments, the depth D3 may be greater than the depth D2 illustrated inFIG.3B, and the width W3 may be greater than or equal to the width W2 illustrated inFIG.3Bby using the same probe in the same CP test apparatus.

Referring toFIG.4D, after the CP test, a first bonding structure135is formed over a front side401aof the fourth die401, thereby forming a semiconductor structure400. The first bonding structure135includes a bonding metal layer132formed in a bonding dielectric layer130. In some embodiments, the bonding dielectric layer130(or the bonding dielectric material130a) is formed over the pad122and filled in the probe mark427. In the case, the bonding dielectric material130ais in contact with the pad122exposed by the probe mark427. That is, the bonding dielectric material130ais filled in and in direct contact with the probe mark427. The bonding metal layer132penetrates the bonding dielectric layer130, the cap layer124, and the protective layer125to land on and contact the pad122. The arrangement, material and forming method of the bonding metal layer132and the bonding dielectric layer130are illustrated in above embodiments. Thus, details thereof are omitted here.

FIG.5is a cross-sectional view showing a semiconductor structure in accordance with a fifth embodiment.

Referring toFIG.5, a semiconductor structure500is similar to the semiconductor structure400illustrated inFIG.4D. A difference therebetween lies in that the semiconductor structure500includes a fifth die501having a pad122and a protective layer125over the pad122. A probe mark527is formed on a top surface122tof the pad122, and the probe mark527may be a recess concaving or recessing from a top surface125tof the protective layer125into the pad122. In some embodiments, the probe mark527may have a depth D4 of 50 nm to 2000 nm, and a width W4 of 1000 nm to 50000 nm. Herein, the depth D4 is a vertical distance between a topmost point (or the top surface125tof the protective layer125) and a bottommost point of the probe mark527. In some alternative embodiments, the depth D4 may be less than the depth D3 illustrated inFIG.4C, and the width W4 may be less than or equal to the width W3 illustrated inFIG.4Cby using the same probe in the same CP test apparatus.

FIG.6is a cross-sectional view showing a semiconductor structure in accordance with a sixth embodiment.

Referring toFIG.6, a semiconductor structure600is similar to the semiconductor structure200illustrated inFIG.2B. A difference therebetween lies in that the structure in the first region R1 illustrated inFIG.6is replaced by the structure300ofFIG.3D. In the case, a probe mark627is formed on a top surface222tof the pad222, and the probe mark627may be a recess concaving or recessing from a top surface224tof the cap layer224into the pad222. However, the embodiments of the present disclosure are not limited thereto. The structure in the first region R1 may be replaced by the structure400ofFIG.4Dor the structure500ofFIG.5. On the other hand, one of the semiconductor structures100,300,400, and500may have the second bonding metal layer242and/or the dummy metal feature238. The second bonding metal layer242penetrates through the bonding dielectric layer230, the protective layer225, and the passivation layer210to land on and contact the top metal feature208b. The dummy metal feature238is disposed in the bonding dielectric material230cand the blocking layer230band exposed by the bonding dielectric material230c.

It should be noted that, in some embodiments, any two of the semiconductor structures100,200,200′,300,400,500, and600may be bonded together by the hybrid bonding structure35, so as to form the 3DIC structure. In some alternative embodiments, one of the semiconductor structures100,300,400, and500may optional have a second bonding metal layer and/or a dummy metal feature disposed aside the first bonding metal layer132, wherein the number and the arrangement of the first bonding metal layer132, the second bonding metal layer, and the dummy metal feature are not limited thereto.

In summary, a portion of the pad is referred to as the test pad for the CP test, and another portion of the pad is referred to as the connect pad for signal transfer. In the case, the semiconductor structure having the pad with multiple functions is able to increase the usage area efficiently. In addition, the protective layer at least covering the top surface of the pad is used as the etching stop layer, so that the first bonding metal layer is landed on the pad and the second bonding metal layer is landed on the top metal feature simultaneously. In the case, the protective layer is able to control the process better without over-etching the pad.

According to some embodiments, a semiconductor structure includes: an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.

According to some embodiments, a semiconductor structure includes: an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises: a metal pad; a protective layer on the metal pad; and a dielectric cap on the protective layer, wherein the pad structure has a probe mark recessed from a top surface of the dielectric cap through the protective layer and into a top surface of the metal pad; and a bonding structure, disposed over the pad structure, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the dielectric cap and the protective layer to contact the metal pad.

According to some embodiments, a die stack structure includes: a first semiconductor structure comprising: a first die having a first pad structure, wherein the first pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a first probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a first protective layer conformally covering the top surface of the dielectric cap and the first probe mark; and a first bonding structure disposed on the first die, wherein the first bonding structure at least comprises a first bonding metal layer penetrating through the first protective layer to contact the first pad structure having the first probe mark; and a second semiconductor structure comprising: a second die; and a second bonding structure disposed on the second die, wherein the first and second semiconductor structures are bonded together such that the first bonding structure contacts the second bonding structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.