Patent ID: 12206017

DETAILED DESCRIPTION

Explanation follows regarding an electrostatic protection element according to an exemplary embodiment of the present disclosure, with reference to the drawings. In the following explanation, an example of an electrostatic protection element according to the present exemplary embodiment will be explained for an embodiment in which a thyristor type electrostatic protection element is applied. Moreover, the electrostatic protection element according to the present exemplary embodiment is built into a semiconductor integrated circuit, is connected to an input/output terminal or the like of the semiconductor integrated circuit, and includes a function to protect an internal circuit from surge or the like. Note that the same reference numerals are appended in the following explanation to configuration elements and portions that are either the same or equivalent to each other, and detailed explanation thereof will be omitted.

Explanation follows regarding an electrostatic protection element10according to the present exemplary embodiment, with reference toFIG.1toFIG.4B.FIG.1illustrates a cross-section of the electrostatic protection element10. As illustrated inFIG.1, the electrostatic protection element10includes a semiconductor substrate11, a buried oxide layer12, an epitaxial layer13, a trench14a, polysilicon14b, an insulation film15, a first layer wiring16, an insulation film17, a second layer wiring18, a protection film19, an N-type layer20, a P-type layer21, a P-type layer22, an N-type layer23, an N-type layer24, a P-type layer25, an N-type layer26, and an N-type layer28.

FIG.2Aillustrates an example of connections of the electrostatic protection element10in a semiconductor integrated circuit30. The semiconductor integrated circuit30includes an internal circuit32and an input terminal34, and the electrostatic protection element10is connected between the input terminal34and a low potential side of a power source (serving as ground in the present exemplary embodiment). The electrostatic protection element10serves as a thyristor, and as illustrated inFIG.2A, an anode A is connected to the input terminal, and a cathode C is connected to ground, namely the electrostatic protection element10is connected in the forward direction. Due to adopting the connection described above, the electrostatic protection element10protects the internal circuit32from surge inrush from the input terminal34by letting the surge escape to ground before reaching, for example, an input buffer33of the internal circuit32. Note that, in the electrostatic protection element10the connection position is not limited to being connected to the input terminal34, and the electrostatic protection element10may, for example, be connected to an output terminal, a power source terminal, or the like.

A silicon on insulator (SOI) substrate is employed as an example of a substrate in the electrostatic protection element10according to the present exemplary embodiment. The semiconductor substrate11, the buried oxide layer (BOX)12, and the epitaxial layer13configure parts of the SOI substrate.

The trench14ais a groove formed from an upper face of the epitaxial layer13to a depth reaching the buried oxide layer12. An oxide film (not illustrated in the drawings) is formed to inside walls, except for at a bottom portion, of the trench14a, and the polysilicon14bis filled inside the trench14a, with the oxide film interposed therebetween. The trench14ahas a function to electrically separate the electrostatic protection element10from other circuit elements in the semiconductor integrated circuit30.

The insulation film15is an electrical separation film formed above the epitaxial layer13. In the electrostatic protection element10according to the present exemplary embodiment, electrical separation is achieved by employing, for example, a local oxidation of silicon (LOCOS) structure. As illustrated inFIG.1, the electrostatic protection element10includes a two layers of wiring layers. Namely, the first layer wiring16is formed above the insulation film15, and the second layer wiring18is formed on the other side of the insulation film17formed above the first layer wiring16. In the following the “first layer wiring” and the “second layer wiring” will be collectively referred to as “wiring”. The protection film19formed above the second layer wiring18is formed over the entire surface of the semiconductor integrated circuit30including over the electrostatic protection element10, and protects the semiconductor integrated circuit30from the external environment, such as humidity and the like.

The N-type layer20, the P-type layer21, the N-type layer23, the N-type layer24, and the P-type layer25configure a thyristor exhibiting the functionality of the electrostatic protection element10. A P-type layer is a region where a P-type impurity has been introduced into the epitaxial layer13, and an N-type layer is a region where an N-type impurity has been introduced into the epitaxial layer13. Note that the N-type layer20, the P-type layer21, the P-type layer25, the N-type layer24, and the N-type layer23are each respective examples of a “first impurity layer”, a “second impurity layer”, a “first contact layer”, a “second contact layer”, and a “third contact layer” according to the present disclosure.

As illustrated inFIG.2A, the thyristor serving as the electrostatic protection element10is generally configured by combining two bipolar-type transistors, a transistor T1and a transistor T2. The transistor T1is a PNP-type transistor, and the transistor T2is an NPN-type transistor.FIG.2Aillustrates, all together, equivalent positions of the N-type layer20, the P-type layer21, the N-type layer23, the N-type layer24, and the P-type layer25. Namely, the P-type layer25, the N-type layer20, and the P-type layer21respectively correspond to the emitter, base, and collector portions of the transistor T1, and the N-type layer20, the P-type layer21, and the N-type layer23respectively correspond to the collector, base, and emitter portions of the transistor T2. In this case the emitter of the transistor T1(the portion corresponding to the P-type layer25) is an anode A of the electrostatic protection element10, and the emitter of the transistor T2(the portion corresponding to the N-type layer23) is a cathode C. The anode A and the cathode C of the electrostatic protection element10are respectively connected to the input terminal34and to ground by, for example, the second layer wiring. Note that the “input terminal34” and “ground” are examples of a “first node” and a “second node” according to the present disclosure.

Returning toFIG.1, the N-type layer26is connected to a high potential side of a power source, and is an impurity layer for preventing an indeterminate potential state from occurring at initial startup of the electrostatic protection element10. The P-type layer22is an impurity layer for achieving a specific potential (ground in the present exemplary embodiment) as an initial state of an anode of a trigger structure. Note that the “N-type layer26” and the “P-type layer22” are respective examples of a “fourth contact layer” and a “fifth contact layer” according to the present disclosure.

Note that the thyristor electrostatic protection element10according to the present exemplary embodiment includes a trigger structure29. The trigger structure29is configured including the N-type layer24, the N-type layer28, and the P-type layer21, with the N-type layer28being an N-minus layer with a relatively low concentration formed at a periphery of the N-type layer24, which is an N-plus layer with a relatively high concentration. The present configuration is adopted to alleviate the electric field at avalanche breakdown (except for electric field avalanche breakdown at an impurity layer end portion). A “trigger structure” is a structure that, at first operation of the electrostatic protection element10, operates the NPN transistor T2by allowing some current to flow. Namely, when there is avalanche breakdown of the trigger, some current flows to ground, and the base potential of the transistor T2rises due to parasitic resistance, such that the transistor T2enters an ON state. In this manner the thyristor electrostatic protection element10also transitions overall to an ON state. The trigger structure may, as illustrated inFIG.2B, be equivalently represented by a tuner diode35and a resistance36. Namely, the N-type layer24corresponds to a position of the cathode of the tuner diode35. The resistance36equivalently represents the parasitic resistance mentioned above. Note that although in the present exemplary embodiment an example explained is the electrostatic protection element10(thyristor) including a trigger structure, the trigger structure is configuration to make startup operation of the electrostatic protection element10more certain, and is not essential configuration. Note that the “N-type layer28” is an example of a “third impurity layer” according to the present disclosure.

Here, in the electrostatic protection element10as described above, it is important to make a resistance value as low as possible for a path to upper layer wiring from the second layer onwards in the multilayer wiring, from each of the impurity layers (the N-type layer20, the P-type layer21, the P-type layer22, the N-type layer23, the N-type layer24, the P-type layer25, and the N-type layer26). Thus in the electrostatic protection element10according to the present exemplary embodiment a stack structure is adopted in which contact and through hole are integrated together. A “contact” in the present exemplary embodiment is via structure directly connected to an impurity layer, and a “through hole” is via structure between wiring. Due to adopting the present stack structure, there is no wiring portion on the path from the impurity layers to upper layer wiring, enabling the connection resistance thereof to be made smaller.

A path of current flowing in the electrostatic protection element10(current path) and parasitic resistance on the current path will now be explained, with reference toFIG.3. A main current Is1flows from the anode A toward the cathode C through the N-type layer20and the P-type layer21, and a trigger current Is2flows from the N-type layer24, which is a cathode of a trigger structure, toward the cathode C. On these current paths there are respective resistances Rp2, Rp3, Rp4, Rp5, and Rp6present as parasitic resistances due to contact and through hole at respective positions of the N-type layer26, the P-type layer25, the N-type layer24, the N-type layer23, and the P-type layer22. Moreover, there is also a total resistance Rp1present for the N-type layer20and the P-type layer21. For example, the resistances Rp3, Rp1, and Rp5are present on the path of the main current Is1flowing from the anode A toward the cathode C. In the electrostatic protection element10, a stack structure is adopted at these positions to reduce as much as possible the parasitic resistance arising due to contact and through hole.

Detailed explanation follows regarding a stack structure according to the present exemplary embodiment, with reference toFIG.4A.FIG.4Aillustrates, as an example, a stack structure formed on the P-type layer22, however, similar configuration may be adopted for other stack structures. As described above, the electrostatic protection element10includes the first layer wiring16formed on the insulation film15, and a second layer wiring of the second layer wiring18formed above the first layer wiring16, with the first layer wiring16and the insulation film17interposed therebetween. As illustrated inFIG.4A, a stack structure27according to the present exemplary embodiment includes the first layer wiring16connected to the P-type layer22, and the second layer wiring18directly above the P-type layer22and connected through a through hole to the first layer wiring16. The stack structure27enables resistance on the path from the P-type layer22to the second layer wiring18to be reduced by as much as possible due to the first layer wiring16itself not being present on this path. The resistances, namely the discharge resistances, on the paths of the currents Is1, Is2are thereby able to be made as small as possible.

Explanation follows regarding function of the stack structure27, with reference toFIG.4B.FIG.4Billustrates changes in a current I (A: amperes) with respect to a voltage V (V: volts) between the anode A and the cathode C (hereafter referred to as “V-I characteristics”). At <1> inFIG.4B, the V-I characteristics according to the present exemplary embodiment are illustrated for a case in which the stack structure27according to the present exemplary embodiment is adopted and resistance due to the first layer wiring16itself is eliminated. At <2> inFIG.4B, the V-I characteristics according to a conventional technology are illustrated for a case in which the stack structure27according to the present exemplary embodiment is not adopted and the resistance of the first layer wiring16itself is present.

The V-I characteristics approximate to straight lines at <1> and <2> ofFIG.4B. When the resistances are computed, a resistance R1(=V/I) found by approximating the V-I characteristics according to the present exemplary embodiment to a straight line L1is clearly smaller than a resistance R2(=V/I) found by approximating the V-I characteristics according to the related technology to a straight line L2. From actual computation, R1is approximately equal to R2/4, namely the wiring resistance for cases in which the stack structure27employed in the present exemplary embodiment Example is about ¼ that of the wiring according to the related technology. Thus, it is apparent that the stack structure27according to the present exemplary embodiment effectively contributes to reducing the wiring path resistance.

A manufacturing method of the electrostatic protection element10including the stack structure27is as summarized below.

Namely, each of the impurity layers (the N-type layer20, the P-type layer21, the P-type layer22, the N-type layer23, the N-type layer24, the P-type layer25, the N-type layer26, and the N-type layer28) are first formed on the semiconductor substrate11.

The insulation film15is then formed.

Then through holes are formed in the insulation film15at positions corresponding to the P-type layer22, the N-type layer23, the N-type layer24, the P-type layer25, and the N-type layer26.

The first layer wiring16is then formed over the entire surface of the first layer wiring16and patterning performed thereon.

The insulation film17is then formed.

Then through holes are formed in the insulation film17at positions corresponding to the P-type layer22, the N-type layer23, the N-type layer24, the P-type layer25, and the N-type layer26. Namely, through holes are formed in the insulation film17directly above the through holes of the insulation film15.

Then the second layer wiring18is formed over the entire surface and patterning performed thereon.

The protection film19is then formed.

Note that although in the electrostatic protection element according to the exemplary embodiment described above an example is illustrated of an embodiment in which a thyristor is applied as an element configuring the electrostatic protection element, there is no limitation thereto, and, for example, an embodiment in which a diode is applied may be adopted.

Moreover, although in the exemplary embodiment described above an example is illustrated of an embodiment in which a stack structure is formed by two-layers of wiring, there is no limitation thereto, and an embodiment may be adopted in which a stack structure is formed with multilayer wiring of three or more layers.