Patent ID: 12211882

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. It is apparent, however, that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are illustrated in block diagram form in order to avoid unnecessarily obscuring various exemplary embodiments. Further, various exemplary embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concepts.

Unless otherwise specified, the illustrated exemplary embodiments are to be understood as providing exemplary features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an exemplary embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements.

When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, when images are illustrated using the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z-axes, and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Although the terms “first,” “second,” “third,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element or third element, etc. without departing from the teachings of the disclosure.

Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Various exemplary embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized exemplary embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are illustrated. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

Parts that are irrelevant to the description will be omitted to clearly describe the present invention, and the same elements will be designated by the same reference numerals throughout the specification.

The size and thickness of each configuration illustrated in the drawings are arbitrarily illustrated for better understanding and ease of description, but the present invention is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. The thicknesses of some layers and areas are exaggerated for convenience of explanation.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. The word “on” or “above” means positioned on or below the object portion, and does not necessarily mean positioned on the upper side of the object portion based on a gravitational direction.

Unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

The phrase “in a plan view” means viewing an object portion from the top, and the phrase “in a cross-sectional view” means viewing a cross-section of which the object portion is vertically cut from the side.

A display device according to an embodiment of the present invention will now be described with reference to accompanying drawings.

FIG.1illustrates a display device according to an embodiment. Referring toFIG.1, the display device may be a display device in which a plurality of display panels are sequentially disposed. That is, regarding a big-area display device, the big area may be realized by sequentially disposing a plurality of display panels instead of one big display panel.

Referring toFIG.1, the display device includes a first display panel DP1and a second display panel DP2.

The first display panel DP1includes a first substrate110a, a first scan driver210apositioned on the first substrate110a, a first scan line151aconnected from the first scan driver210a, and a plurality of pixels PX connected to the first scan line151a.

In a like manner, the second display panel DP2includes a second substrate110b, a second scan driver210bpositioned on the second substrate110b, a second scan line151bconnected from the second scan driver210b, and a plurality of pixels PX connected to the second scan line151b.

For ease of description,FIG.1illustrates the configuration of the first scan driver210aand the second scan driver210b. A data driver, a data divider, and a timing controller may also be positioned on the first substrate110aand the second substrate110b. Also, for ease of illustration, the first and second scan lines151aand151band the pixels PX are illustrated as one row, but they may be disposed on a plurality of rows.

Referring toFIG.1, the first display panel DP1and the second display panel DP2overlap each other in a region in which the first display panel DP1and the second display panel DP2are connected to each other. An overlapping area (OA) of the first display panel DP1and the second display panel DP2is illustrated using a dotted line. The first substrate110aand the second substrate110bare connected using an L-shaped configuration150within the OA.

In conjunction with the L-shaped configuration, as illustrated inFIG.1, a portion of the first substrate110aof the first display panel DP1in the overlapping area (OA) is thinner than portions of the first substrate110ain non-overlapping areas. In a like manner, a portion of the second substrate110bof the second display panel DP2in the overlapping area (OA) is thinner than portions of the second substrate110bnon-overlapping areas. In this instance, a sum of thicknesses of the first substrate110aand the second substrate110bin the overlapping area (OA) may be similar to a thickness of the first substrate110aor a thickness of the second substrate110bin non-overlapping areas.

In an embodiment, a third scan driver may be respectively positioned in the overlapping area (OA) of the first display panel DP1and the second display panel DP2. The third scan driver may be respectively positioned on a front side of the first substrate110aof the first display panel DP1and a rear side of the second substrate110bof the second display panel DP2in the overlapping area (OA). Therefore, the third scan driver may not be visible on the front side of the display device. The front side of the display device may refer to the side illustrated inFIG.1in which the first scan driver210a, pixels PX, first scan line151a, etc. are illustrated. A detailed formed shape of the second scan driver will be described in another part of the present specification with reference toFIG.2andFIG.3.

Regarding the display device in which a plurality of display panels are connected to each other, gaps among the pixels PX may be different near the area occupied by the third scan driver on the connection portion of the first display panel DP1and the second display panel DP2. However, as show illustrated n inFIG.1, when the third scan driver is in the overlapping area of the first display panel DP1and the second display panel DP2, it may be possible to maintain the gap among the pixels PX on the connection portion of the first display panel DP1is and the second display panel DP2. The connection portion may refer to the OA.

FIG.2illustrates a configuration of a first display panel DP1described with reference toFIG.1. Referring toFIG.2, the first substrate110aincludes a first thick portion110a1and a first thin portion110a2. The first thick portion110a1is a portion not overlapping the second display panel DP2, and a first scan driver210amay be positioned on one edge of the first thick portion110al. The first scan driver210ais connected to the first scan line151a, and a plurality of pixels PX are positioned to be connected to the first scan line151a. A third scan driver220ais positioned on the first thin portion110a2of the first substrate110a. The third scan driver220ais also connected to the first scan line151a. The pixel PX is not positioned on the first thin portion110a2of the first substrate110a.

Illustrated with a dotted line D1, the first thin portion110a2may be formed in a single continuous body with the first substrate110a. In other embodiments, the first thin portion110a2may be formed in a separate operation than the first substrate110a.

FIG.3illustrates a configuration of a second display panel DP2described with reference toFIG.1. Referring toFIG.3, the second substrate110bincludes a thick second thick portion110b1and a thin second thin portion110b2. The second thick portion110b1does not overlap the first display panel DP1, and a second scan driver210bis positioned on one edge of the second thick portion110b1. The second scan driver210bis connected to the second scan line151b, and a plurality of pixels PX are positioned to be connected to the second scan line151b.

A fourth scan driver220bis positioned on a rear side of the second thin portion110b2of the second substrate110b. The fourth scan driver220bmay be connected to the second scan line151b. The second scan line151bmay wrap around the second thin portion110b2and reach the rear side of the second thin portion110b2from the front side of the second thin portion110b2of the second substrate110bover a lateral side of the second thin portion110b2. Each pixel PX may be connected to the second scan line151bpositioned on the front side of the second thin portion110b2.

The display device illustrated inFIG.1may be formed when the first display panel DP1ofFIG.2and the second display panel DP2ofFIG.3overlap each other in the OA and are connected to each other. In this instance, an insulating layer (IL) may be positioned on the OA between the first display panel DP1and the second display panel DP2.

FIG.4illustrates a cross-section with respect to a line A-A′ ofFIG.1.FIG.4illustrates an overlapping shape of the respective third and fourth scan drivers220aand220bin the overlapping area (OA). That is, as illustrated inFIG.4, the first display panel DP1overlaps the second display panel DP2in the overlapping area. The third scan driver220ais positioned on the first thin portion110a2of the first substrate110aof the first display panel DP1, and the fourth scan driver220bis positioned on the second thin portion110b2of the second substrate110bof the second display panel DP2.

As illustrated inFIG.4, an insulating layer (IL) is positioned between the third scan driver220aof the first display panel DP1and the fourth scan driver220bof the second is display panel DP2. Therefore, the third scan driver220aof the first display panel DP1may be insulated from the fourth scan driver220bof the second display panel DP2.

When the first display panel DP1and the second display panel DP2are formed to overlap each other in the overlapping area OA, and the respective third and fourth scan drivers220aand220bare positioned in the overlapping area, a problem in which a disposal gap of the pixels PX that becomes different in the connection region of the display panel may be addressed.

FIG.5illustrates a display device in which a first display panel DP1does not overlap a second display panel DP2. Referring toFIG.5, a first scan driver210aand a seventh scan driver220a1are positioned on respective edges of the first display panel DP1. Further, the second scan driver210band an eighth scan driver220b1are positioned on respective edges of the second display panel DP2.

Because the respective display panels have big areas, it is desired to dispose the scan drivers on the respective edges of the display panels. When the scan drivers are not positioned on the respective edges, image quality may be degraded because of deviation of charging rates of the respective pixels.

As the scan drivers are positioned on respective edges of the display panels, a gap between the pixels PX on the connection portion where the respective display panels are connected to each other may become different, as illustrated inFIG.5. That is, as illustrated inFIG.5, a pixel gap (b) between neighboring display panels becomes longer than a pixel gap (a) within one display panel.

FIG.6illustrates part of a display device according to the present embodiment. Referring toFIG.6, regarding the display device according to the present embodiment, the first display panel DP1and the second display panel DP2overlap each other in the overlapping area (OA). Further, the third scan driver of the first display panel DP1and the fourth scan driver of the second display panel DP2may be positioned in the overlapping area (OA) of the first display panel DP1and the second display panel DP2as illustrated inFIG.1toFIG.3. The third scan driver is positioned in the overlapping area (OA) of the first display panel DP1and the second display panel DP2so it is not visible from the outside. Therefore, as illustrated inFIG.6, the pixel gap (a) within one display panel and the pixel gap (b) between neighboring display panels may be substantially the same, thereby improving display quality. In this instance, a difference between the pixel gap (a) on the display panel and the pixel gap (b) between neighboring display panels may be less than 10%.

A display device according to another embodiment will now be described with reference toFIG.7toFIG.9. According to an embodiment described with reference toFIG.1toFIG.4, the first scan driver210aand the third scan driver220aare positioned on the first display panel DP1, and the second scan driver210band the fourth scan driver220bare positioned on the second display panel DP2. However, according to an embodiment described with reference toFIG.7toFIG.9, the configuration of the fourth scan driver220bon the second display panel DP2is omitted, and the second display panel DP2may receive a signal from the third scan driver220aof the first display panel DP1.

FIG.7illustrates a configuration of a first display panel DP1in a display device according to the present embodiment. Referring toFIG.7, the configuration of the first display panel DP1corresponds to an embodiment described with reference toFIG.1toFIG.4. That is, the first substrate110aof the first display panel DP1includes the first thick portion110a1and a first thin portion110a2, a first scan driver210ais positioned on the first thick portion110a1, and a third scan driver220ais positioned on the first thin portion110a2. Other same constituent elements to will not be described.

FIG.8illustrates a configuration of a second display panel DP2in a display device according to the present embodiment. Referring toFIG.8, the second substrate110bof the second display panel DP2according to the present embodiment includes the second thick portion110b1and the second thin portion110b2. The second scan driver210bis positioned on one edge of the second thick portion110b1. The second scan driver210bis connected to the second scan line151b, and a plurality of pixels PX are positioned to be connected to the second scan line151b.

No scan driver is positioned on the second thin portion110b2of the second substrate110b. That is, differing from an embodiment described with reference toFIG.3, regarding the second display panel DP2according to the present embodiment, the second scan driver210bis positioned on the second thick portion110b1of the second substrate110b, and a fourth scan driver is not positioned on the second thin portion110b2. The second scan line151bextends to the rear side of the second thin portion110b2of the second substrate110bof the second display panel DP2, and the second scan line151bmay directly contact the third scan driver220aof the first display panel DP1and may receive a scan signal from the third scan driver220a.

FIG.9illustrates a cross-section on a same position asFIG.4, illustrating a configuration in which the third scan driver220aof the first display panel DP1contacts the second scan line151bof the second display panel DP2in the overlapping area of the first display panel DP1and the second display panel DP2.

Referring toFIG.9, the third scan driver220ais positioned on the first thin portion110a2of the first substrate110aof the first display panel DP1. Further, the second scan line151bis positioned on the second thin portion110b2of the second substrate110bof the second display panel DP2.

As illustrated inFIG.9, no insulating layer is positioned between the third scan driver220aof the first display panel DP1and the second scan line151bof the second display panel DP2. The third scan driver220aof the first display panel DP1directly contacts the second scan line151bof the second display panel DP2. Therefore, the second display panel DP2may receive the scan signal of the third scan driver220aof the first display panel DP1, and the configuration of the fourth scan driver of the second display panel DP2may be omitted. Therefore, the configuration of the display device and the manufacturing process thereof may be simplified.

FIG.10illustrates a display device according to another embodiment. The is embodiment described with reference toFIG.10corresponds to the embodiment described with reference toFIG.1toFIG.4except that the display device includes a first display panel DP1, a second display panel DP2, and a third display panel DP3. No same constituent elements will be described. As illustrated inFIG.10, the third display panel DP3is positioned between the first display panel DP1and the second display panel DP2.

FIG.11illustrates a first display panel DP1ofFIG.10,FIG.12illustrates a third display panel DP3ofFIG.10, andFIG.13illustrates a second display panel DP2ofFIG.10.

Referring toFIG.10andFIG.11, the configuration of the first display panel DP1according to the present embodiment corresponds to the configuration described with reference toFIG.2. Similar terms may be used as described in various places. That is, the first substrate110aof the first display panel DP1according to the present embodiment includes the first thick portion110a1and a first thin portion110a2, and a first scan driver210ais positioned on the first thick portion110a1and a third scan driver220ais positioned on the first thin portion110a2. To be additionally described, the third scan driver220aof the first display panel DP1may contact a third scan line151cof the third display panel DP3and may be directly connected to the same.

Referring toFIG.10andFIG.12, the third display panel DP3according to the present embodiment includes a third substrate110c, and the third substrate110cincludes a third thick portion110c1, a third thin portion110c2, and a fourth thin portion110c3. The third thin portion110c2and the fourth thin portion110c3of the third substrate110cmay be positioned on respective edges of the third thick portion110c1.

Referring toFIG.12, the third display panel DP3does not include a scan driver. However, as illustrated inFIG.12, the third scan line151cextends on the rear side of the third thin portion110c2and fourth thin portion110c3of the third substrate110c. To be described in detail hereinafter, the third display panel DP3may receive a scan signal from the neighboring first display panel DP1or the second display panel DP2through the third scan line151c.

FIG.13illustrates a second display panel DP2ofFIG.10. Referring toFIG.13, the configuration of the second display panel DP2according to the present embodiment corresponds to what is described with reference toFIG.3. No same constituent elements will be described.

That is, the second substrate110bof the second display panel DP2includes the second thick portion110b1and the second thin portion110b2. The second thick portion110b1does not overlap the first display panel DP1, and a second scan driver210bis positioned on one edge of the second thick portion110b1. The second scan driver210bis connected to the second scan line151b, and a plurality of pixels PX are positioned to be connected to the second scan line151b. The first scan line151amay be connected to the third scan line151cvia the second scan line151b. Though labeled separately for the understanding of the reader, they may all be considered part of a same scan line.

A fourth scan driver220bis positioned on the second thin portion110b2of the second substrate110b. The fourth scan driver220bmay be connected to the second scan line151b. To be additionally described hereinafter, the fourth scan driver220bof the second is display panel DP2may be directly connected to the third scan line151cof the third display panel DP3.

FIG.14illustrates a cross-section with respect to a line B-B′ ofFIG.10. Referring toFIG.14, a third scan driver220ais positioned on the first thin portion110a2of the first substrate110aof the first display panel DP1. Further, the third scan line151cis positioned on the third thin portion110c2and the fourth thin portion110c3of the third substrate110cof the third display panel DP3. The third scan line151cof the third display panel DP3contacts the third scan driver220aof the first display panel DP1. That is, the third scan line151cof the third display panel DP3contacts the third scan driver220aof the first display panel DP1on the rear side of the third thin portion110c2of the third substrate110c, and may receive the scan signal therefrom.

FIG.15illustrates a cross-section with respect to a line C-C′ ofFIG.10. Referring toFIG.15, a fourth scan driver220bis positioned on the second thin portion110b2of the second substrate110bof the second display panel DP2, and near this, the third scan line151cis positioned on the fourth thin portion110c3of the third substrate110cof the third display panel DP3. That is, the third scan line151cof the third display panel DP3contacts the fourth scan driver220bof the second display panel DP2on the rear side of the fourth thin portion110c3of the third substrate110c, and it may receive a scan signal therefrom.

That is, according to an embodiment described with reference toFIG.10toFIG.15, the third display panel DP3positioned between the first display panel DP1and the second is display panel DP2may not include an additional scan driver, and it may be respectively connected to the third scan driver220aof the neighboring first display panel DP1and the fourth scan driver220bof the second display panel DP2through the third scan line151cto receive the scan signal. Therefore, no additional scan driver is positioned on the third display panel DP3, thereby simplifying the structure of the display device and also simplifying the manufacturing process.

FIG.16toFIG.19show a display device according to another embodiment. The display device ofFIG.16toFIG.19includes a first display panel DP1, a second display panel DP2, and a third display panel DP3positioned between the first display panel DP1and the second display panel DP2, which corresponds to an embodiment described with reference toFIG.10toFIG.15. No same constituent elements will be described.

FIG.17illustrates a first display panel DP1ofFIG.16. Referring toFIG.17, the configuration of the first display panel DP1according to the present embodiment corresponds to the configuration described with reference toFIG.2. No same constituent elements will be described. That is, the first substrate110aof the first display panel DP1according to the present embodiment includes the first thick portion110a1and a first thin portion110a2, a first scan driver210ais positioned on the first thick portion110al, and a third scan driver220ais positioned on the first thin portion110a2.

FIG.18illustrates a third display panel DP3ofFIG.16. Referring toFIG.18, the third substrate110cof the third display panel DP3includes the third thick portion110c1and is the third thin portion110c2and a fifth thin portion110c4. The third thin portion110c2may be positioned co-planar with the front side of the third display panel DP3. The fifth thin portion110c4may be disposed co-planar with the rear side of the third display panel DP3. The third thin portion110c2and the fifth thin portion110c4of the third substrate110cmay be positioned on respective edges of the third thick portion110c1.

Referring toFIG.18, a fifth scan driver210cand a sixth scan driver220care positioned on the front side of the fifth thin portion210c4or the rear side of the third thin portion110c2positioned on respective edges of the third thick portion110c1. As illustrated inFIG.18, the fifth scan driver210cmay be positioned on the rear side of the third thin portion110c2. Further, the sixth scan driver220cmay be positioned on the front side of the fifth thin portion110c4. The fifth scan driver210cis connected to the third scan line151c, and the third scan line151cis connected to the pixel PX. In a like manner, the sixth scan driver220cis connected to the third scan line151c, and the third scan line151cis connected to the pixel PX.

FIG.19illustrates a second display panel DP2ofFIG.16. Referring toFIG.19, the configuration of the second display panel DP2according to the present embodiment corresponds to the configuration described with reference toFIG.3. No same constituent elements will be described. That is, the second substrate110bof the second display panel DP2includes the second thick portion110b1and a thin second thin portion110b2. The second thick portion110b1does not overlap the first display panel DP1, and the second scan driver210bis positioned on one edge of the second thick portion110b1. The second scan driver210bis is connected to the second scan line151b, and a plurality of pixels PX are positioned to be connected to the second scan line151b. A fourth scan driver220bis positioned on the second thin portion110b2of the second substrate110b. The fourth scan driver220bmay be connected to the scan line151b.

FIG.20illustrates a cross-section with respect to a line D-D′ ofFIG.16. Referring toFIG.20, an insulating layer (IL) is positioned between the third scan driver220aof the first display panel DP1and the fifth scan driver210cof the third display panel DP3. Therefore, the third scan driver220aof the first display panel DP1and the sixth scan driver220cof the third display panel DP3may be insulated.

FIG.21illustrates a cross-section with respect to a line E-E′ ofFIG.16. Referring toFIG.21, an insulating layer (IL) is positioned between the sixth scan driver220cof the third display panel DP3and the fourth scan driver220bof the second display panel DP2. Therefore, the sixth scan driver220cof the third display panel DP3and the fourth scan driver220bof the second display panel DP2may be insulated.

FIG.22illustrates a display device including a plurality of display panels.FIG.22illustrates a display device including a first display panel DP1, a second display panel DP2, a third display panel DP3, and a fourth display panel DP4. This is, however, an example, and a number of display panels is modifiable. An overlapping shape of the display panel in the overlapping area (OA) inFIG.22may be one ofFIG.1toFIG.9.

FIG.23illustrates a display device according to another embodiment. Referring is toFIG.23, the display device according to the present embodiment may be included.FIG.23illustrates a configuration including a first display panel DP1, a second display panel DP2, a third display panel DP3, a fourth display panel DP4, a fifth display panel DP5, a sixth display panel DP6, a seventh display panel DP7, an eighth display panel DP8, and a ninth display panel DP9, which may be an example, and the number of display panels may be variable. An overlapping shape of the display panel in the overlapping area (OA) ofFIG.23may correspond to what is illustrated with reference toFIG.10toFIG.15.

FIG.24illustrates a display device according to another embodiment. Referring toFIG.23, a display device according to the present embodiment may be included.FIG.23illustrates a configuration including a first display panel DP1, a second display panel DP2, a third display panel DP3, a fourth display panel DP4, a fifth display panel DP5, a sixth display panel DP6, a seventh display panel DP7, an eighth display panel DP8, and a ninth display panel DP9, which may be an example, and the number of display panels is changeable. An overlapping shape of the display panel in the overlapping area (OA) inFIG.24may correspond to what is illustrated with reference toFIG.16toFIG.20.

A circuit diagram of a pixel PX according to the present embodiment will now be described.FIG.25illustrates an equivalent circuit diagram of one pixel PX in a display device according to an embodiment.FIG.25is, however, an example, and the present invention is not limited thereto. The pixel PX may have various circuit diagrams in addition to what is illustrated inFIG.25.

Referring toFIG.25, the pixel PX of the emissive display device includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7connected to various signal lines127,151,152,153,158,171,172, and741, a storage capacitor Cst, and a light emitting diode (LED).

The emissive display device includes a display area configured to display images, and the pixel PX is arranged in the display area in various forms.

A plurality of transistors T1, T2, T3, T4, T5, T6, and T7include a driving transistor T1, include switching transistors connected to the scan line151, that is, a second transistor T2and a third transistor T3, and include other transistors (hereinafter, compensation transistors) configured to perform operations to operate the light emitting diode (LED). The compensation transistors (T4, T5, T6, and T7) may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

A plurality of signal lines127,151,152,153,158,171,172, and741may include a scan line151, a previous-stage scan line152, an emission control line153, a bypass control line158, a data line171, a driving voltage line172, an initialization voltage line127, and a common voltage line741. The bypass control line158may be part of the previous-stage scan line152or may be electrically connected thereto. In another way, the bypass control line158may be part of the scan line151or may be electrically connected thereto.

The scan line151is connected to the gate driver and transmits the scan signal (Sn) to the second transistor T2and the third transistor T3. The previous-stage scan line152is connected to the gate driver and transmits a previous-stage scan signal Sn−1 applied to the pixel is PX positioned on a previous stage to the fourth transistor T4. The emission control line153is connected to an emission controller, and transmits an emission control signal (EM) configured to control a time for the light emitting diode (LED) to emit light to the fifth transistor T5and the sixth transistor T6. The bypass control line158transmits a bypass signal (GB) to the seventh transistor T7.

The data line171is a wire to transmit a data voltage (Dm) generated by the data driver, and luminance of light emitted by the light emitting diode (LED) (also referred to as a light-emitting device) is changed according to the data voltage (Dm). The driving voltage line172applies a driving voltage (ELVDD). The initialization voltage line127transmits an initialization voltage (Vint) configured to initialize the driving transistor T1. The common voltage line741applies a common voltage (ELVSS). Voltages applied to the driving voltage line172, the initialization voltage line127, and the common voltage line741may be constant.

A plurality of transistors will now be described.

The driving transistor T1controls a size of the current output according to the applied data voltage (Dm). The output driving current (Id) is applied to the light emitting diode (LED) to control brightness of the light emitting diode (LED) according to the data voltage (Dm). For this purpose, the first electrode S1of the driving transistor T1is disposed to receive the driving voltage (ELVDD). The first electrode S1is connected to the driving voltage line172through the fifth transistor T5. Further, the first electrode S1of the driving transistor T1is connected to the second electrode D2of the second transistor T2to receive the data voltage is (Dm). The second electrode (D1, output electrode) of the driving transistor T1is disposed to output the current to the light emitting diode (LED). The second electrode D1of the driving transistor T1is connected to the anode of the light emitting diode (LED) through the sixth transistor T6. In addition, the gate electrode G1is connected to one electrode (second storage electrode) E2of the storage capacitor Cst. The voltage at the gate electrode G1changes according to the voltage stored in the storage capacitor Cst, and the driving current (Id) output by the driving transistor T1changes.

The second transistor T2receives the data voltage (Dm) into a pixel PX. The gate electrode G2is connected to the scan line151, and the first electrode S2is connected to the data line171. The second electrode D2of the second transistor T2is connected to the first electrode S1of the driving transistor T1. When the second transistor T2is turned on according to the scan signal (Sn) transmitted through the scan line151, the data voltage (Dm) transmitted through the data line171is transmitted to the first electrode S1of the driving transistor T1.

The third transistor T3transmits the compensation voltage ((Dm+Vth) volts) changed when the data voltage (Dm) passes through the driving transistor T1to the second storage electrode E2of the storage capacitor Cst. The gate electrode G3is connected to the scan line151, and the first electrode S3is connected to the second electrode D1of the driving transistor T1. The second electrode D3of the third transistor T3is connected to the second storage electrode E2of the storage capacitor Cst and the gate electrode G1of the driving transistor T1. The third transistor T3is turned on by the scan signal (Sn) received through the is scan line151to connect the gate electrode G1of the driving transistor T1and the second electrode D1, and to also connect the second electrode D1of the driving transistor T1and the second storage electrode E2of the storage capacitor Cst.

The fourth transistor T4initializes the gate electrode G1of the driving transistor T1and the second storage electrode E2of the storage capacitor Cst. The gate electrode G4is connected to the previous-stage scan line152, and the first electrode S4is connected to the initialization voltage line127. The second electrode D4of the fourth transistor T4is connected to the second storage electrode E2of the storage capacitor Cst and the gate electrode G1of the driving transistor T1through the second electrode D3of the third transistor T3. The fourth transistor T4transmits the initialization voltage (Vint) to the gate electrode G1of the driving transistor T1and the second storage electrode E2of the storage capacitor Cst according to the previous-stage scan signal Sn−1 received through the previous-stage scan line152. Accordingly, a gate voltage at the gate electrode G1of the driving transistor T1and the storage capacitor Cst are initialized. The initialization voltage (Vint) may have a low voltage value and may turn on the driving transistor T1.

The fifth transistor T5transmits the driving voltage (ELVDD) to the driving transistor T1. The gate electrode G5is connected to the emission control line153, and the first electrode S5is connected to the driving voltage line172. The second electrode D5of the fifth transistor T5is connected to the first electrode S1of the driving transistor T1.

The sixth transistor T6transmits the driving current (Id) output by the driving is transistor T1to the light emitting diode (LED). The gate electrode G6is connected to the emission control line153, and the first electrode S6is connected to the second electrode D1of the driving transistor T1. The second electrode D6of the sixth transistor T6is connected to the anode of the light emitting diode (LED).

The fifth transistor T5and the sixth transistor T6are simultaneously turned on by the emission control signal (EM) received through the emission control line153, and when the driving voltage (ELVDD) is applied to the first electrode S1of the driving transistor T1through the fifth transistor T5, the driving transistor T1outputs the driving current (Id) according to the voltage (i.e., the voltage at the second storage electrode E2of the storage capacitor Cst) at the gate electrode G1of the driving transistor T1. The output driving current (Id) is transmitted to the light emitting diode (LED) through the sixth transistor T6. The current (Iled) flows to the light emitting diode (LED), and the light emitting diode (LED) emits light.

The seventh transistor T7initializes the anode of the light emitting diode (LED). The gate electrode G7is connected to the bypass control line158, the first electrode S7is connected to the anode of the light emitting diode (LED), and the second electrode D7is connected to the initialization voltage line127. The bypass control line158may be connected to the previous-stage scan line152, and a signal with the same timing as the previous-stage scan signal Sn−1 is applied as the bypass signal (GB). The bypass control line158is not connected to the previous-stage scan line152, and it may transmit a signal that is different from the previous-stage scan signal Sn−1. When the seventh transistor T7is turned on by the bypass is signal (GB), the initialization voltage (Vint) is applied to the anode of the light emitting diode (LED) to be initialized.

The first storage electrode E1of the storage capacitor Cst is connected to the driving voltage line172, and the second storage electrode E2is connected to the gate electrode G1of the driving transistor T1, the second electrode D3of the third transistor T3, and the second electrode D4of the fourth transistor T4. As a result, the second storage electrode E2determines the voltage at the gate electrode G1of the driving transistor T1, and it receives the data voltage (Dm) through the second electrode D3of the third transistor T3or receives the initialization voltage (Vint) through the second electrode D4of the fourth transistor T4.

In addition, the anode of the light emitting diode (LED) is connected to the second electrode D6of the sixth transistor T6and the first electrode S7of the seventh transistor T7, and the cathode is connected to the common voltage line741to transmit the common voltage (ELVSS).

The pixel circuit according to an embodiment described with reference toFIG.25includes seven transistors (T1to T7) and one capacitor Cst, and without being limited thereto, the number of transistors and capacitors, and their connections, are modifiable in many ways.

FIG.25illustrates the configuration in which one light emitting diode (LED) is connected to the circuit ofFIG.25, and a light-emitting device group in which a plurality of light-emitting devices are connected to each other may be connected thereto.

While this invention has been described in connection with what is presently is considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.