Patent ID: 12236839

DETAILED DESCRIPTION

Hereinafter, the present disclosure will be described in detail hereinafter with reference to the accompanying drawings, in which examples of the present disclosure are shown. As those skilled in the art would realize, the described examples may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In the flowchart described with reference to drawings in this description, the operation order may be changed, several operations may be merged, certain operations may be divided, and specific operations may not be performed.

In the description, expressions described in the singular in this specification may be interpreted as the singular or plural unless an explicit expression such as “one” or “single” is used. Although terms of “first,” “second,” and the like are used to explain various constituent elements, the constituent elements are not limited to such terms. These terms are only used to distinguish one constituent element from another constituent element.

FIG.1is a block diagram showing an example of a display system.

For example, display system10includes an artificial reality system, such as a VR system, an AR system, a mixed reality (MR) system, a hybrid reality system, or some combination and/or derivative system thereof. Artificial reality systems may be implemented on a variety of platforms, including head mounted displays (HMD), mobile devices, computing systems, or other hardware platforms capable of providing artificial reality content to one or more viewers. In some implementations, the display system10may be mounted on an electronic device having an image display function. For example, electronic devices may include smartphones, tablet personal computers, portable multimedia players (PMPs), cameras, wearable devices, televisions, digital video disk (DVD) players, refrigerators, air conditioners, air purifiers, set-top boxes, robots, drones, various medical devices, navigation devices, global positioning system (GPS) receivers, vehicle devices, furniture, and various measuring devices.

Referring toFIG.1, the display system10includes a host processor100and a display device200. The display device200includes a display driving circuit220and a display panel270.

The host processor100may generate an input image signal IS to be displayed on the display panel270and transmit the input image signal IS and a control command CTRL to the display driving circuit220. The input image signal IS may include frame data corresponding to each frame. The control command CTRL may include setting information about luminance, gamma, frame frequency, and operation mode of the display driving circuit220. For example, the operating mode may include a driving mode and a test mode including a DC level measurement mode and a slew rate measurement mode. Here, the slew rate may be a parameter indicating the operating speed of the OP Amp and may indicate the degree to which the output voltage can change per unit time.

The host processor100may be a graphics processor. However, the present disclosure is not limited thereto, and the host processor100may be implemented with various types of processors, such as a central processing unit (CPU), microprocessor, multimedia processor, and application processor. In some implementations, the host processor100may be implemented as an integrated circuit (IC) or system on chip (SoC).

The display device200may receive the input image signal IS from the host processor100and display the input image signal IS. The display device200may display a two-dimensional or three-dimensional image to the user. In some implementations, the display device200may be a device in which the display driving circuit220and the display panel270are implemented as a single module. For example, the display driving circuit220may be mounted on a substrate of the display panel270, or the display driving circuit220and the display panel270may be electrically connected through a connection member such as a flexible printed circuit board (FPCB).

The display device200may include the display panel270and the display driving circuit220.

The display panel270may display an image to the user according to the input image signal IS received from the host processor100. The display panel270may be a display device that receives an electrically transmitted image signal and display a two-dimensional image, such as a thin film transistor-liquid crystal display (TFT-LCD), an organic light emitting diode (OLED) display, a field emission display, a plasma display panel (PDP).

In some implementations, there may be one or more display panels270. For example, two display panels270may provide images for each eye of the user.

The display driving circuit220may generate a plurality of analog signals for driving the display panel270based on the input image signal IS received from the host processor100. For example, the plurality of analog signals may include gate signals and data signals that drive the plurality of pixels included in the display panel270. The display driving circuit220may provide gate signals and data signals to a plurality of pixels. The display panel270may emit image light corresponding to the input image signal IS by a signal provided by the display driving circuit220.

The display driving circuit220may include a driving controller250and a voltage generator260.

The driving controller250may control the voltage generator260to generate a plurality of gray scale voltages and a plurality of reference voltages. In some implementations, the driving controller250may generate image data corresponding to the image signal IS. In some implementations, the driving controller250may measure the DC level of the source signal based on a comparison value between the source signal and the reference voltage provided to the display panel270in response to image data. Additionally, the driving controller250may measure the slew rate level of the source signal based on a comparison value between the source signal and the reference voltage provided to the display panel270in response to the image data.

The driving controller250may correct image data based on the DC level of the source signal and the slew rate level of the source signal. In some implementations, the driving controller250may transmit the DC level of the source signal and the slew rate level of the source signal to the host processor100. The host processor100may correct the image signal IS based on the DC level of the source signal and the slew rate level of the source signal.

The voltage generator260may generate a plurality of gray scale voltages to be provided to the display panel270under the control of the driving controller250. In addition, the voltage generator260may generate a reference voltage necessary to measure the DC level of the source signal and the slew rate of the source signal. In some implementations, the reference voltage may be a sawtooth wave voltage or a DC voltage.

FIG.2is a block diagram showing an example of a display device.

Referring toFIG.2, the display device200includes a pixel array210including a plurality of pixels PX and the display driving circuit220.

The pixel array210includes a plurality of gate lines GL0-GLh−1, a plurality of source lines SL0-SLk−1; SL disposed in a direction intersecting the plurality of gate lines GL0-GLh−1; GL, and a plurality of pixels PX arranged in a region where the plurality of gate lines GL and the plurality of source lines SL intersect.

For example, if the display device200is a thin film transistor (TFT) liquid crystal display, each pixel PX may include a TFT with a gate electrode and a source electrode connected to a gate line and a data line, respectively, a liquid crystal capacitor connected to a drain electrode of the TFT, and a storage capacitor. When a specific gate line is selected among the plurality of gate lines GL, the TFTs of the pixels PX connected to the selected gate line are turned on, and then data voltages may be applied to each of the plurality of source lines SL by a source driver240. The data voltage is applied to the liquid crystal capacitor and the storage capacitor through the TFT of the corresponding pixel PX, and the liquid crystal capacitor and the storage capacitor may be driven to display an image.

InFIG.2, the pixel PX is shown as connected to one source line SL and one gate line GL, but the connection structure of the signal line of the pixel PX of the display device is not limited thereto. For example, various signal lines may be additionally connected in accordance with the circuit structure of the pixel PX.

The display drive circuit220may convert the externally received input image signal IS into a plurality of analog signals, such as a plurality of data voltages, for driving the pixel array210, and provide the converted plurality of analog signals to the pixel array210.

The display driving circuit220may include a gate driver230, a source driver240, a driving controller250, and a voltage generator260. A configuration including the driving controller250and the voltage generator260may be referred to as a main logic201. The main logic201may further include a memory storing arbitrary data for controlling the configuration within the display device200. However, the present disclosure is not limited thereto, and the memory may be positioned outside of the display device200.

The gate driver230is connected to the plurality of gate lines GL of the pixel array210and may sequentially drive the plurality of gate lines GL of the pixel array210. The gate driver230may provide a plurality of gate signals G0, G1, G2, . . . , Gh−1 to the pixel array210. The plurality of gate signals G0, G1, G2, . . . , Gh−1 may be pulse signals having an enable level and a disable level. The plurality of gate signals G0, G1, G2, . . . , Gh−1 may be applied to the plurality of gate lines GL.

The gate driver230may apply the plurality of gate signals G0, G1, G2, . . . , Gh−1 to the plurality of gate lines GL in different ways based on a control signal CONT1of the driving controller250. For example, when an enable level gate signal is applied to a pixel PX connected to one of the plurality of gate lines GL, the source signal applied to the source line connected to the corresponding pixel PX among the plurality of source lines SL may be transmitted to the pixel PX.

The source driver240is connected to k source lines SL0to SLk−1 and may output source signals for driving the pixel array210through the k source lines. The source driver240may implement one frame by outputting source signals for each of h gate lines GL0to GLh−1.

The source driver240may receive data DATA in the form of a digital signal from the driving controller250. In addition, the source driver240may receive a plurality of voltages VOL and reference voltages V_REF from the voltage generator260. The plurality of voltages VOL may include a plurality of gray scale voltages. The source driver240may convert the image data DATA received from the driving controller250into source signals S0, S1, S2, . . . , Sk−1 in the form of analog signals based on a plurality of gray scale voltages (or, referred to as gamma voltages) within the plurality of voltages VOL.

The source driver240may receive image data DATA in data units corresponding to the plurality of pixels PX included in one horizontal line of the pixel array210. The image data DATA may include grayscale information corresponding to each pixel PX for displaying the input image signal IS on the pixel array210. The source driver240may output the plurality of source signals S0, S1, S2, . . . , Sk−1 to the pixel array210in horizontal line units through the plurality of source lines SL0to SLk−1. Specifically, the source driver240may transmit the plurality of source signals S0, S1, S2, . . . , Sk−1 to the pixel array210according to a source driver control signal CONT2provided from the driving controller250. The source driver240may also be referred to as a data driver.

Since the source driver240includes a plurality of amplifiers and decoders as will be described later, even if the plurality of source signals S0, S1, S2, . . . , Sk−1 corresponding to the image data DATA are generated, there may be differences between the plurality of generated source signals S0, S1, S2, . . . , Sk−1 and the source signals that are actually output.

In some implementations, the source driver240is connected to m return lines RL0to RLm−1, and may receive return signals R0, R1, . . . , Rm−1 output from the pixel array210in response to the source signal through the m return lines. For example, the return signals R0, R1, . . . , Rm−1 may be signals actually output through the source driver240in response to the image data DATA. InFIG.2, the return line RL is not shown, but each of the plurality of return lines RL0to RLm−1 may be connected to each of the plurality of source lines SL, and the present disclosure is not limited thereto. For example, the source driver240may output the plurality of source signals S0, S1, S2, . . . , Sk−1 in the form of analog signals through an arbitrary source line, and receive the plurality of the return signals R0, R1, . . . , Rm−1 through a source line adjacent to the corresponding source line. Alternatively, the source driver240may output a source signal in the form of an analog signal through an arbitrary source line and receive a return signal through the same source line. In some implementations, the source driver240may output a source signal through some source lines among a plurality of source lines, and some source lines may not output source signals.

The source driver240may obtain a count value COUNT_NUM based on the plurality of source signals S0, S1, S2, . . . , Sk−1 and the return signals R0, R1, . . . , Rm−1 corresponding to each of the plurality of source signals S0, S1, S2, . . . , Sk−1.

Here, the count value COUNT_NUM may represent the difference between the source signal and the return signal. Specifically, the source driver240may compare the plurality of reference voltages the return signals R0, R1, . . . , Rm−1 to obtain the count value COUNT_NUM representing a DC level of the return signals R0, R1, . . . , Rm−1 and the count value COUNT_NUM representing a slew rate of the return signals R0, R1, . . . , Rm−1.

Thereafter, the source driver240may transmit the obtained count value COUNT_NUM to the driving controller250.

The driving controller250may control the overall operation of the display driving circuit220. For example, the driving controller250may control configurations of the display driving circuit220so that the image signal IS may be displayed on the pixel array210, based on the image signal IS and the drive control signal CTRL from the host device, e.g., host processor100ofFIG.1).

For example, the drive control signal CTRL may include a horizontal synchronization signal, a vertical synchronization signal, a main clock signal, and a data enable signal. Specifically, the driving controller250may generate image data DATA by dividing the input image signal IS into one frame unit based on the vertical synchronization signal and dividing the input image signal IS into a plurality of gate line GL units based on the horizontal synchronization signal.

In some implementations, the driving controller250may generate output image data DATA by converting the format to match the interface specifications with the source driver240based on the received input image signal IS, and output the image data DATA to the source driver240.

The driving controller250may control the source driver240, the gate driver230, and the voltage generator260based on control commands that the driving controller250generates independently, separately from the drive control signal CTRL received from a host device, e.g., host processor100inFIG.1, or in addition to the drive control signal CTRL.

In some implementations, the driving controller250may control the operation timing of the display driving circuit220. The driving controller250may control the operation timing of the source driver240, the gate driver230, and the voltage generator260so that the input image signal IS is displayed on the pixel array210. Specifically, the driving controller250may generate various control signals CONT1, CONT2, CONT3to control the timing of the gate driver230, source driver240, and the voltage generator260. The driving controller250may output the first control signal CONT1to the gate driver230, output the second control signal CONT2to the source driver240, and output the third control signal CONT3to the voltage generator260. The first control signal CONT1may include a control signal that controls the gate level of the plurality of pixels PX. In addition, the second control signal CONT2may include a switch control signal within the source driver240, an amplifier control signal, and other components. The third control signal CONT3may be a signal that causes the voltage generator260to generate a reference voltage.

The driving controller250may receive the count value COUNT_NUM from the source driver240. The driving controller250may modify the image data DATA based on the received count value COUNT_NUM. For example, when the count value COUNT_NUM is greater than a predetermined value, the driving controller250may correct the image data DATA based on the count value COUNT_NUM and provide the corrected image data to the source driver240as the image data DATA. For example, the driving controller250may correct the image data DATA corresponding to the input image signal IS using a lookup table corresponding to the count value COUNT_NUM. For example, the driving controller250may receive a first count value from the source driver240and select a lookup table corresponding to the first count value. The driving controller250may apply the data value corresponding to the first count value to the image data DATA and output the image data to which the data value is applied as new image data DATA to the source driver240. For example, applying a count value may mean adding or subtracting a specific value from image data DATA.

However, the present disclosure is not limited thereto, and the source driver240may generate a source signal corrected based on the image data DATA received from the driving controller250based on the count value COUNT_NUM. Specifically, the source driver240may generate a source signal based on the image data DATA received from the driving controller250, and transmit the corrected source signal to the pixel array210through the plurality source lines SL0to SLk−1 by generating a corrected source signal using a lookup table corresponding to the count value COUNT_NUM.

The voltage generator260may generate various voltages necessary to drive the display device200. The voltage generator260may receive a power source voltage from the outside and generate the plurality of voltages VOL based on the power source voltage. Additionally, the voltage generator260may generate the plurality of reference voltages V_REF. The reference voltage V_REF may be a voltage used by the driving controller250to measure the DC level and slew rate for the source signal.

In some implementations, the configuration of the display driving circuit220of the present disclosure may include additional configurations. For example, the configuration of the display driving circuit220may be implemented to include a memory that stores input image signals IS frame by frame, or a memory that stores a lookup table in which correction data corresponding to the count value COUNT_NUM is stored to correct the image data DATA.

Memory may be referred to as, for example, graphic random access memory (RAM) or a frame buffer. Memory may include volatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), or non-volatile memory such as ROM or Flash memory, resistive random access memory (ReRAM), and magnetic random access memory (MRAM). In some implementations, the display driving circuit220may further include other general-purpose components, for example, a clock generator, etc.

InFIG.2, the gate driver230, the source driver240, the driving controller250, and the voltage generator260are shown as different functional blocks. In some implementations, each component may be implemented with a different semiconductor chip. In some implementations, at least two components of the gate driver230, the source driver240, the driving controller250, and the voltage generator260may be implemented as one semiconductor chip. For example, the gate driver230, the source driver240, and the voltage generator260may be integrated into one semiconductor chip. Additionally, some components may be integrated on the pixel array210. For example, the gate driver230may be integrated on the pixel array210.

FIG.3is a diagram showing an example of a display device.

As shown inFIG.3, the display device1000includes a pixel array1010and a display driving circuit1020. The display driving circuit1020includes a gate driver1030, a source driver1040, a driving controller1050, and a voltage generator1060. A configuration including the driving controller1050and the voltage generator1060may be referred to as a main logic1001. The main logic1001may further include a memory storing arbitrary data for controlling the configuration within the display device1000. However, the present disclosure is not limited thereto, and the memory may be positioned outside of the display device1000.

The pixel array1010may include a plurality of pixels PX. The pixel array1010may include a plurality of gate lines GL0, . . . , GLh−1 and a plurality of source lines SL0, . . . , SLk−1 connected to the plurality of pixels PX.

The gate driver1030may transmit gate signals G0, . . . , Gh−1 to the plurality of gate lines GL0, . . . , GLh−1 based on the first control signal CONT1received from the driving controller1050.

The driving controller1050may drive the display device1000in a plurality of modes.

For example, when the display device1000operates in a driving mode, the driving controller1050may generate the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3corresponding to the driving mode. The display device1000may display an image corresponding to the image signal IS while operating in the driving mode. In this case, the second control signal CONT2may be a signal that controls a plurality of switches SW11to SW16within the source driver1040.

For another example, when the display device1000operates in a test mode, the driving controller1050may generate the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3corresponding to the test mode. The display device1000may be in a mode for measuring the DC level and slew rate of a source signal Si output by the source driver1040while operating in the test mode.

In some implementations, the driving controller1050may measure the DC level and the slew rate of the source signal Si output by a channel amplifier1021connected to a source line SLi through a second channel amplifier1031connected to the adjacent source line SLi+1 of the source line SLi. Specifically, a plurality of source lines SL within the pixel array1010may include a first test mode in which a 2n−1th (wherein n is a natural number greater than 1) disposed source line operates in a driving mode and a 2nth disposed source line operates in a comparator mode, and a second test mode in which a 2nth disposed source line operates in a driving mode and a 2n−1th (wherein n is a natural number greater than 1) disposed source line operates in a comparator mode.

Specifically,FIG.3is a diagram illustrating an example where the display device1000operates in the first test mode. For example, a first source line1110may operate in an operation mode, and a second source line1210may operate in a test mode.

When the display device1000is operating in the first test mode, the driving controller1050may generate the first control signal CONT1corresponding to the first test mode, the second control signal CONT2corresponding to the first test mode, and the third control signal CONT3corresponding to the first test mode.

When the display device1000operates in the second test mode, the driving controller1050may generate the first control signal CONT1corresponding to the second test mode, the second control signal CONT2corresponding to the first test mode, and the third control signal CONT3corresponding to the first test mode.

The voltage generator1060may generate various voltages required to drive the display device1000under the control of the driving controller1050. For example, the voltage generator1060may include the plurality of voltages VOL and the reference voltage V_REF including a plurality of gray scale voltages.

The source driver1040may include logic units1025and1035, decoders1023and1033, channel amplifiers1021and1031, and a selector1011.

The output terminal of the channel amplifier1021may be connected to the selector1011, the first input terminal of the channel amplifier1021may be connected to the selector1011, and the second input terminal may be connected to the decoder1023. The selector1011may be connected to the output terminal of the channel amplifier1021, the first input terminal of the channel amplifier1021, the output terminal of the channel amplifier1031, the first input terminal of the channel amplifier1031, the source line SLi, the source line SLi+1, the logic unit1025, and the logic unit1035.

The source driver1040may convert the image data DATA received from the driving controller1050into the source signal Si and output the source signal Si through the first source line (SLi, i is an integer greater than 0 and less than or equal to k−2). In addition, the source driver1040may convert the image data DATA received from the driving controller1050into the source signal Si+1 and output the source signal Si+1 through the second source line (SLi+1, i is an integer greater than 0 and less than or equal to k−2).

In some implementations, the source driver1040may measure the DC level difference between the source signal Si output through the channel amplifier1021and a decoder signal S_DEC1output to the channel amplifier1021through the decoder1023. Additionally, the source driver1040may measure the slew rate of the source signal Si. The source driver1040may generate the count value COUNT_NUM based on the measured DC level and slew rate.

The logic units1025and1035may receive image data DATA from the driving controller1050and transmit the count value COUNT_NUM to the driving controller1050. The present disclosure is not limited thereto, and the logic units1025and1035may transmit the count value COUNT_NUM to the host processor (100inFIG.1) or separate test equipment.

The first logic unit1025may include a latch1027and a counter1029. The second logic unit1035may include a latch1037and a counter1039.

The latches1027and1037may receive image data DATA from the driving controller1050. The latches1027and1037may sample and store image data DATA under the control of the driving controller1050. The latches1027and1037may transmit sampled image data to the decoders1023and1033. In some implementations, the latches1027and1037may include a sampling circuit that samples data and a holding latch that stores data sampled by the sampling circuit.

The counters1029and1039generate a first count value COUNT_NUM1based on a counter input signal CNT_S1received from the selector1011. The counter1039generates a second count value COUNT_NUM2based on a counter input signal CNT_S2received from the selector1011. Here, the counter input signal CNT_S1may be a signal indicating the source signal Si or a signal indicating the comparison result of comparing the source signal Si+1 and the reference voltage V_REF, and the counter input signal CNT_S2may be a signal indicating the source signal Si+1 or a signal indicating a comparison result of comparing the source signal Si and the reference voltage V_REF.

Each of the counters1029and1039may transmit the generated first count value COUNT_NUM1and the second count value COUNT_NUM2to the driving controller1050. Alternatively, the counter1029may transmit the generated first count value COUNT_NUM1to the latch1027or the generated second count value COUNT_NUM2to the latch1039.

InFIG.3, the latch1027and the counter1029are shown as being included in the logic unit1025, and the latch1037and the counter1039are shown as being included in the logic unit1035. However, the present disclosure is not limited thereto, and the latch and counter may be configured separately from the source driver1040.

The decoders1023and1033may receive sampled image data from the corresponding latches1027and1037. The decoder1023may receive a plurality of voltages VOL from the voltage generator1060. The plurality of voltages VOL may include gamma voltages corresponding to various levels of luminances of the display device1000. The number of gamma voltages may be determined based on the number of colors to be displayed through the pixel array1010or the number of bits of digital data provided from outside the display device1000. In some implementations, the decoder1023may select one of the plurality of voltages VOL in response to sampled image data. The decoder1023may output the selected gamma voltage(s) to the channel amplifier1021. The decoder1033may receive the reference voltage V_REF from the voltage generator1060. For example, the reference voltage V_REF may be a DC voltage or a sawtooth waveform. In some implementations, the decoders1023and1033may be implemented as digital-to-analog converters.

The channel amplifier1021may receive the gamma voltage selected from the decoder1023, amplify the gamma voltage selected by the decoder1023in response to the second control signal CONT2received from the driving controller1050, and transmit the selected gamma voltage to the selector1011as the source signal Si. The channel amplifier1021may be implemented as an operational amplifier. For example, the channel amplifier1021may output the source signal Si through the first source line SLi. As the channel amplifier1021is connected to the corresponding source line SLi, the channel amplifier1021and the decoder1023may control the driving of the source line SLi.

In some implementations, the channel amplifier1021may include a first input terminal, a second input terminal through which a gamma voltage is input from the decoder1023, and an output terminal through which an output voltage is output. The channel amplifier1031may include a first input terminal, a second input terminal through which a reference voltage is input from the voltage generator1060, and an output terminal. The first input terminal of each of the channel amplifiers1021and1031may be connected to the output terminal of each of the channel amplifiers1021and1031. In some implementations, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

For example, the output voltage of the channel amplifiers1021and1031may be input as an input voltage to the inverting input terminal of the channel amplifiers1021and1031. The channel amplifiers1021and1031may be implemented as unit buffers.

The selector1011may be connected to the first channel amplifier1021and the second channel amplifier1031, and to two adjacent source lines SLi, SLi+1. The selector1011may include first to sixth switches SW11, SW12, SW13, SW14, SW15, and SW16. The selector1011may control the connection relationship between the plurality of switches SW11to SW16within the selector1011based on the second control signal CONT2received from the driving controller1050. Specifically, the first switch SW11may be connected between the first source line SLi and the output terminal of the first channel amplifier1021, and the second switch SW12may be connected between the second source line SLi+1 and the output terminal of the second channel amplifier1031. The third switch SW13may be connected to one end of the first switch SW11(e.g., the output terminal of the first channel amplifier1021) and the first input terminal of the second channel amplifier1031. The fourth switch SW14may be connected to one end of the second switch SW12(e.g., the output terminal of the second channel amplifier1031) and the first input terminal of the first channel amplifier1021. The fifth switch SW15may connect one end of the first switch SW11(e.g., the output terminal of the first channel amplifier1021) and the logic unit1025according to the second control signal CONT2or connect one end of the first switch SW11and the first input terminal of the first channel amplifier1021. The sixth switch SW16may connect one end of the first switch SW12(e.g., the output terminal of the second channel amplifier1031) and the logic unit1035according to the second control signal CONT2or connect one end of the second switch SW12and the first input terminal of the second channel amplifier1031. InFIG.3, the fifth switch SW15and the sixth switch SW16are each shown as a single-pole double-throw (SPDT) switch, but the present disclosure is not limited thereto. Each of the fifth switch SW15and the sixth switch SW16may be implemented as two switches.

In some implementations, when the display device1000operates in a driving mode, the driving controller1050may generate the second control signal CONT2corresponding to the driving mode and transmit the second control signal CONT2to the selector1011, as described above. For example, the second control signal CONT2may be a signal that controls the plurality of switches SW11through SW16such that the channel amplifier1021is connected to the corresponding source line SLi and the channel amplifier1031is connected to the corresponding source line SLi+1.

Based on the second control signal CONT2, the first switch SW11and the second switch SW12may be turned on, the third switch SW13and the fourth switch SW14may be turned off, the fifth switch SW15may be connected to the first input terminal of the first channel amplifier1021, and the sixth switch SW16may be connected to the first input terminal of the second channel amplifier1031. Accordingly, the selector1011may receive the first source signal Si from the first channel amplifier1021and transmit the first source signal Si to the source line SLi and may receive the second source signal Si+1 from the second channel amplifier1031and transmit the second source signal Si+1 to the source line SLi+1. The third control signal CONT3may be a signal that controls the voltage generator1060to generate a voltage provided to the display driving circuit1020. For example, the third control signal CONT3may be a signal that controls the transmission of a plurality of gray scale voltages to the decoders1023and1033as the plurality of voltages VOL. Alternatively, the third control signal CONT3may be a signal that controls the voltage generator1060to generate a plurality of reference voltages and transmit the plurality of reference voltages to the channel amplifier1021or the channel amplifier1031through the decoders1023and1033.

In some implementations, when the display device1000operates in a test mode, the driving controller1050may generate the second control signal CONT2corresponding to the test mode and transmit the second control signal CONT2to the selector1011, as described above. The second control signal CONT2may be a signal that controls the plurality of switches SW11to SW16so that the output of the channel amplifier1021or the channel amplifier1031is connected to the first input terminal of the adjacent channel amplifier.

For example, in the case of the first test mode, based on the second control signal CONT2corresponding to the first test mode, the first switch SW11, the second switch SW12, and the third switch SW13may be turned on, the fourth switch SW14may be turned off, the fifth switch SW15may connect one end of the first switch SW11and the first input terminal of the first channel amplifier1021, and the sixth switch SW16may connect the output of the second channel amplifier1031and the logic unit1035. Accordingly, the selector1011may receive the first source signal Si from the first channel amplifier1021and transmit the first source signal Si to the source line SLi and transmit the first source signal Si to the first input terminal of the second channel amplifier1031through the third switch SW13. The second channel amplifier1031may compare the first source signal Si input to the first input terminal and the reference voltage received from the second decoder1033, and transmit the comparison result to the logic unit1035through the sixth switch SW16. The third control signal CONT3may be a signal that controls the voltage generator1060to transmit a plurality of gray scale voltages to the decoder1023as the plurality of voltages VOL and the reference voltage V_REF to the decoder1033. In this case, the reference voltage V_REF may be input to the second channel amplifier1031through the decoder1033.

For another example, in the case of the second test mode, based on the second control signal CONT2corresponding to the second test mode, the first switch SW11, the second switch SW12, and the fourth switch SW14may be turned on, the third switch SW13may be turned off, the fifth switch SW15may connect one end of the first switch SW11and the logic unit1025, and the sixth switch SW16may connect one end of the second switch SW12and the first input terminal of the second channel amplifier1031. Accordingly, the selector1011may receive the second source signal Si+1 from the second channel amplifier1031and transmit the second source signal Si+1 to the source line SLi+1 and transmit the second source signal Si+1 to the first input terminal of the second channel amplifier1031through the fourth switch SW14. The first channel amplifier1021may compare the second source signal Si+1 input to the first input terminal and the reference voltage received from the first decoder1023, and transmit the comparison result to the logic unit1025through the fifth switch SW15. The third control signal CONT3may be a signal that controls the voltage generator1060to transmit a plurality of gray scale voltages to the decoder1023as the plurality of voltages VOL and the reference voltage V_REF to the decoder1033. In this case, the reference voltage V_REF may be input to the first channel amplifier1021through the decoder1023.

In general, the1-line pixel charging time of panel is continuously decreasing to drive high-frequency and high-resolution displays.

Additionally, a greater number of source lines may be required within the display driving circuit to support high resolution. An increase in the number of source lines may increase the load when transmitting the gamma voltage, thereby slowing down the settling time of the gamma voltage. The slowing down of the settling time may worsen the stabilization time of the source line and cause issues in driving the display device at high speed.

FIG.4is a flowchart showing an example of a method when the display device ofFIG.3operates in a DC level measurement mode.FIG.5is a timing diagram showing an example of the operation of the display device ofFIG.3when the display device operates in a DC level measurement mode. Specifically,FIGS.5and6illustrate the reference voltage V_REF output from the voltage generator1060and the outputs of the source signal Si and the logic units1025and1035when the display device1000is operating in DC level measurement mode.

The display device1000compares the first reference voltage and the target voltage to generate a first comparison result (S401). In some implementations, the display device1000may generate a plurality of first reference voltages and compare each of the plurality of first reference voltages with the target voltage to generate a plurality of first comparison results. InFIG.5, the case where the display device1000generates two first comparison results is described as an example, but the present disclosure is not limited thereto, and the display device1000may generate an appropriate number of first comparison results.

Hereinafter, the signal to be the target of the comparison is referred to as a target voltage, and the signal to be the reference of the comparison is referred to as a reference voltage.

The voltage generator1060may generate a first sawtooth waveform5011having an arbitrary DC level. The first sawtooth waveform5011may be input to the second input terminal of the first channel amplifier1021through the first decoder1023. Thereafter, the output from the first channel amplifier1021may be input to the first input terminal of the second channel amplifier1031. In some implementations, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

The voltage generator1060may generate the first reference voltage5001with a DC level of a first value as the reference voltage V_REF, and the first reference voltage5001may be output as a second decoder signal S_DEC2through the second decoder1033.

InFIG.5, the first value is shown as VDD/2, but the present disclosure is not limited thereto, and the reference voltage V_REF may be a DC voltage having an arbitrary level.

The second channel amplifier1031may compare the first reference voltage5001and the first sawtooth waveform5011, and output the comparison result to the logic unit1035as a counter signal CNT_S2. When the first sawtooth waveform5011has a first DC level, the first sawtooth waveform5011has a higher value than the first reference voltage5001during t102to t105, so a counter signal CNT_S2_REF1may have a high level.

The counter1039may generate a count value COUNT_NUM12by counting the time for which the counter signal CNT_S2_REF1maintains a certain level. Thereafter, the logic unit1035may transmit the generated count value COUNT_NUM12to the driving controller1050as a reference count value. The driving controller1050may obtain a count value according to the DC level of the first sawtooth waveform5011with respect to the first reference voltage5001.

In some implementations, the voltage generator1060may generate the first reference voltage5001with the first value as the reference voltage V_REF, and the first reference voltage5001may be output as the second decoder signal S_DEC2through the second decoder1033. The second channel amplifier1031may compare the first reference voltage5001and the first sawtooth waveform5011, and output the comparison result to the logic unit1035as a counter signal CNT_S2.

The counter1039in the logic unit1035may generate the count value COUNT_NUM12by counting the time for which the counter signal CNT_S2, that is, the count signal CNT_S2_REF1, maintains a certain level. Thereafter, the logic unit1035may transmit the generated count value COUNT_NUM12to the driving controller1050as a reference count value.

Accordingly, the driving controller1050may obtain a count value representing the DC level of the first sawtooth waveform5011with respect to one reference voltage V_REF. The driving controller1050may compare the target voltage, which is a plurality of sawtooth waveforms, and the first reference voltage, which is a DC voltage, to measure a change in the count value as the DC level of the target voltage changes, and the result of this comparison may be referred to as a first comparison result.

In some implementations, the driving controller1050may store a plurality of first comparison results in the form of a lookup table.

The display device1000compares the source signal and the second reference voltage to generate a second comparison result (S403).

The voltage generator1060may generate a plurality of gray scale voltages as a plurality of voltages VOL and input the plurality of gray scale voltages to the first decoder1023. The first decoder1023may select a gray scale voltage corresponding to the image data DATA from among the plurality of voltages VOL and output the gray scale voltage to the first channel amplifier1021as the decoder signal S_DEC1. The first channel amplifier1021may output the source signal Si as a target voltage. The source signal Si output through the first channel amplifier1021may be input to the first input terminal of the second channel amplifier1031through the third switch SW13.

The voltage generator1060may generate a first sawtooth waveform5015having an arbitrary DC level as a reference voltage. In this case, the first sawtooth waveform5015may be the target voltage in step S401of generating the first comparison result. The first sawtooth waveform5015may be input to the second input terminal of the second channel amplifier1031through the second decoder1033. Thereafter, the output from the first channel amplifier1021may be input to the first input terminal of the second channel amplifier1031. The second channel amplifier1031may compare the source signal Si and the first sawtooth waveform5015, and output the comparison result as the counter signal CNT_S2to the logic unit1035. The counter signal CNT_S2, that is, the counter signal CNT_S2_REF1, may have a high level during t104to t105.

The counter1039may generate the count value COUNT_NUM12by counting the time for which the counter signal CNT_S2_REF1maintains a certain level. The driving controller1050may obtain a count value according to the DC level of the source signal5003with respect to the second reference voltage, which is the first sawtooth waveform5015.

The driving controller1050may generate a value obtained by subtracting the count value of the second comparison result from the count value of the first comparison result as the final count value. For example, inFIG.5, the count value of the DC level of the first sawtooth waveform5011for the first reference voltage5001is the first value (corresponding to t102to t105), and the count value of the DC level of the source signal5003for the first reference voltage, which is the first sawtooth waveform5015, may be the second value (corresponding to t104to t105). The driving controller1050may determine a value obtained by subtracting the second value from the first value, that is, a value calculated by counting the time (t102to t104) during which the final count signal COUNT_NUM_REF1maintains a certain level, as the final count value.

In some implementations, the voltage generator1060may generate a second sawtooth waveform5013having a different DC level from the first sawtooth waveform5011. The second sawtooth waveform5013may be input to the second input terminal of the first channel amplifier1021through the first decoder1023. Thereafter, the output from the first channel amplifier1021may be input to the input terminal of the second channel amplifier1031.

In some implementations, the voltage generator1060may generate the first reference voltage5001with the first value as the reference voltage V_REF, and the first reference voltage5001may be output as the second decoder signal S_DEC2through the second decoder1033. The second channel amplifier1031may compare the first reference voltage5001and the second sawtooth waveform5013, and output the comparison result to the logic unit1035as the counter signal CNT_S2. When the second sawtooth waveform5013has a second DC level, the second sawtooth waveform5013has a higher value than the first reference voltage5001during t101to t105, so the count signal CNT_S2_REF2may have a high level.

The driving controller1050may obtain a count value according to the DC level of the second sawtooth waveform5013with respect to the first reference voltage5001.

Similarly, the display device1000may generate a second sawtooth waveform5017having an arbitrary DC level as a reference voltage. In this case, the second sawtooth waveform5017may be the target voltage in step S401of generating the first comparison result. The second sawtooth waveform5017may be input to the second input terminal of the second channel amplifier1031through the second decoder1033. Thereafter, the output from the first channel amplifier1021may be input to the first input terminal of the second channel amplifier1031. The second channel amplifier1031may compare the source signal Si and the second sawtooth waveform5017and output the comparison result as the counter signal CNT_S2to the logic unit1035. The counter signal CNT_S2, that is, the counter signal CNT_S2_REF2, may have a high level during t103to t105.

The counter1039may generate the count value COUNT_NUM12by counting the time for which the count signal CNT_S2_REF2maintains a certain level. The driving controller1050may obtain a count value based on the DC level of the source signal5003, that is, the second sawtooth waveform5017, with respect to the reference voltage.

The display device1000generates a final count value based on the first comparison result and the second comparison result (S403).

The count value of the DC level of the second sawtooth waveform5013with respect to the first reference voltage5001may be a third value (corresponding to t101to t105), and the count value of the DC level of the source signal5003with respect to the second sawtooth waveform5017may be a fourth value (t103to t105). The driving controller1050may determine a value obtained by subtracting the fourth value from the third value, that is, a value calculated by counting the time (t101to t103) during which the final count signal COUNT_NUM_REF2maintains a certain level, as the final count value.

The driving controller1050may obtain the counter value CNT_S2_REF1indicating a value of the first sawtooth waveform5011relative to the first reference voltage5001, and the counter value CNT_S2_REF1indicating a value of the source signal5003relative to the first sawtooth waveform5011.

Additionally, the driving controller1050may obtain the counter value CNT_S2_REF2indicating a value of the first sawtooth waveform5011relative to the second reference voltage, e.g., first sawtooth waveform5015, and the counter value CNT_S2_REF2indicating a value of the source signal5003relative to the second sawtooth waveform5013. The driving controller1050may obtain a count value indicating the source signal regardless of the type of reference voltage. That is, the driving controller1050may obtain a count value indicating the source signal regardless of the offset level of the reference voltage, and thus can accurately measure the source voltage.

The display device1000measures the DC level of the source signal based on the final count value (S407).

In some implementations, the driving controller1050may have a DC level difference corresponding to the count value set in advance based on a plurality of first comparison results. The driving controller1050may measure the DC level of the source signal5003based on the final count value. In some implementations, the higher the DC level of the source signal5003, the smaller the final count value may be.

The driving controller1050may change the image data DATA based on the DC level of the measured source signal. For example, when the source signal5003has a high DC level, the driving controller1050may generate modified image data by adding an arbitrary value to the image data DATA and transmit the modified image data to the source driver1040.

As described above,FIG.5shows the reference voltages, e.g., first reference voltage5001, first sawtooth waveform5015, and second sawtooth waveform5017, the source signal5003and count value CNT_S2when the display device1000is operating in the first test mode, e.g., when the source line SLi is operating in the driving mode and the source line SLi+1 is operating in the test mode.

However, the present disclosure is not limited thereto, and it may be possible for the display device1000to operate in the second test mode.

In summary, inFIG.5, the voltage generator1060generated a sawtooth waveform and a DC voltage, set the sawtooth waveform as a target voltage and the DC voltage as a reference voltage, and compared the target voltage to the reference voltage to generate a first comparison result. Then, a case where the voltage generator1060generates a source signal and a sawtooth waveform, sets the source signal as a target voltage and sets the sawtooth waveform as a reference voltage to compare the target voltage to the reference voltage to generate a second comparison result, and measures the DC level of a source signal based on the first comparison result and the second comparison result is shown. However, the present disclosure is not limited thereto, and the voltage generator1060may measure the DC level of the source signal by using a waveform other than a sawtooth waveform as a target voltage or reference voltage.

The operation of the display device1000from t101to t105may be similar to the operation of the display device1000from t106to t110.

FIG.6is a timing diagram showing an example of the operation of the display device ofFIG.3when the display device operates in a DC level measurement mode.

In some implementations, voltage generator1060may measure the DC level of the source signal using a voltage that has the form of a ramp waveform. Depending on the type of voltage used by the display device1000to measure the DC level of the source signal, the absolute count value according to the comparison result may vary. However, since the display device1000measures the DC level of the source signal based on the difference between the reference first comparison result and the measured second comparison result, the DC level may not be affected by the type of voltage used.

Specifically,FIG.6shows a timing diagram when the voltage generator1060measures the DC level of the source signal using a voltage having a ramp waveform. The description of the operation of the display device1000described above with reference toFIGS.4and5when operating in the DC level measurement mode may also be applied toFIG.6unless otherwise specified.

The voltage generator1060may generate a ramp waveform6011having an arbitrary DC level. The ramp waveform6011may be input to the second input terminal of the first channel amplifier1021through the first decoder1023. Thereafter, the output from the first channel amplifier1021may be input to the first input terminal of the second channel amplifier1031. In some implementations, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

The voltage generator1060may generate the DC voltage6001with the first value as the reference voltage V_REF, and the DC voltage6001may be output as the second decoder signal S_DEC2through the second decoder1031. InFIG.6, the first value is shown as VDD/2, but the present disclosure is not limited thereto, and the reference voltage V_REF may be a DC voltage having an arbitrary level.

The second channel amplifier1031may compare the DC voltage6001and the ramp waveform6011and output the comparison result as the counter signal CNT_S2to the logic unit1035. When the ramp waveform6011has a first DC level, the ramp waveform6011has a higher value than the first reference voltage, e.g., DC waveform6001, during t201to t203, so the counter signal CNT_S2_REF1may have a high level.

The counter1039may generate the count value COUNT_NUM12by counting the time for which the counter signal CNT_S2_REF maintains a certain level. Thereafter, the logic unit1035may transmit the generated count value COUNT_NUM12to the driving controller1050as a reference count value. The driving controller1050may obtain a count value according to the DC level of the ramp waveform6011with respect to the first reference voltage, e.g., DC waveform6001.

The voltage generator1060may generate a plurality of gray scale voltages as the plurality of voltages VOL and input the plurality of gray scale voltages to the first decoder1023. The first decoder1023may select a gray scale voltage corresponding to the image data DATA from among the plurality of voltages VOL and output the gray scale voltage to the first channel amplifier1021as the decoder signal S_DEC1. The first channel amplifier1021may output the source signal Si as a target voltage. The source signal Si output through the first channel amplifier1021may be input to the first input terminal of the second channel amplifier1031through the third switch SW13.

The display device1000may generate a second sawtooth waveform5017having an arbitrary DC level as a reference voltage. At this time, the second ramp waveform6013may have the same voltage as the ramp waveform6011. The second channel amplifier1031may compare the source signal Si and the first sawtooth waveform5015and output the comparison result as the counter signal CNT_S2to the logic unit1035. The counter signal CNT_S2_REF may have a certain level during t202to t203.

The counter1039may generate the count value COUNT_NUM12by counting the time for which the count signal CNT_S2_REF maintains a certain level. The driving controller1050may obtain a count value according to the DC level of the second ramp waveform6013, that is, the source signal Si with respect to the reference voltage.

Next, the driving controller1050may generate a value obtained by subtracting the count value of the second comparison result from the count value of the first comparison result as the final count value. For example, inFIG.6, the count value of the DC level of the first target value, e.g., ramp waveform6011, for the reference voltage, e.g., DC voltage6001, may be the first value (corresponding to t201to t203), and the count value of the DC level of the second target voltage6003for the reference voltage, e.g., second ramp waveform6013, may be the second value (corresponding to t202to t203). The driving controller1050may determine a value obtained by subtracting the second value from the first value, that is, a value calculated by counting the time (t201to t202) during which the final count signal COUNT_NUM_REF maintains a certain level, as the final count value. InFIG.6, the count value of the DC level of the first target value, e.g., ramp waveform6011, for the reference voltage, e.g., DC voltage6001, may be the first value (corresponding to t201to t203), and the count value of the DC level of the second target voltage6003for the reference voltage, e.g., second ramp waveform6013, may be the second value (corresponding to t201to t202). The driving controller1050may determine a value obtained by subtracting the first value from the second value, that is, a value calculated by counting the time (t201to t202) during which the final count signal COUNT_NUM_REF maintains a certain level, as the final count value.

The driving controller1050may measure the DC level of the source signal5003based on the final count value. In some implementations, the higher the DC level of the source signal5003, the smaller the final count value may be.

The driving controller1050may change the image data DATA based on the DC level of the measured source signal.

The driving controller1050may set an appropriate reference voltage according to the shape of the waveform of the source signal. For example, if there is a lot of data indicating white in the image data DATA, there is a high probability that the waveform of the source signal will have a low value. In this case, the driving controller1050may measure the DC level of the waveform of the source signal using the ramp signal as a reference voltage.

FIG.7is a flowchart showing an example of a method when the display device ofFIG.3operates in a slew rate measurement mode.FIG.8is a timing diagram showing an example of the operation of the display device ofFIG.3when the display device operates in a slew rate measurement mode. Specifically,FIGS.7and8illustrate the reference voltage V_REF output from the voltage generator1060and the outputs of the source signal Si and the logic units1025and1035when the display device1000is operating in DC level measurement mode.

The display device1000compares the first reference voltage and the source signal to generate a first comparison result (S701).

The voltage generator1060may generate a plurality of gray scale voltages as the plurality of voltages VOL and input the plurality of gray scale voltages to the first decoder1023. The first decoder1023may select a gray scale voltage corresponding to the image data DATA from among the plurality of voltages VOL and output the gray scale voltage to the first channel amplifier1021as the decoder signal S_DEC1. The first channel amplifier1021may output the source signal Si as a target voltage. The source signal Si output through the first channel amplifier1021may be input to the first input terminal of the second channel amplifier1031through the third switch SW13. In some implementations, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

The voltage generator1060may generate a DC voltage8001with the first value as the reference voltage V_REF, and the DC voltage8001may be output as the second decoder signal S_DEC2through the second decoder1033. InFIG.8, the first value is shown as having a VTOP value, and the VTOP value may be, for example, a value that is 90% of a power source voltage VDD.

The second channel amplifier1031may compare the DC voltage8011and a source signal8003and output the comparison result as the counter signal CNT_S2to the logic unit1035. Since the source signal8003has a value greater than the DC voltage8011during t302to t303, a counter signal CNT_S21may have a high level during t302to t303.

The counter1039may generate the count value COUNT_NUM12by counting the time for which the count signal CNT_S21maintains a certain level. Thereafter, the logic unit1035may transmit the generated count value COUNT_NUM12to the driving controller1050as a reference count value.

The display device1000compares the second reference voltage and the source signal to generate a second comparison result (S703).

The voltage generator1060may generate a DC voltage8013with the second value as the reference voltage V_REF, and the DC voltage8013may be output as the second decoder signal S_DEC2through the second decoder1033. InFIG.8, the first value is shown as having a VBOTTOM value, and the VBOTTOM value may be, for example, a value of 10% of the power source voltage VDD.

The second channel amplifier1031may compare the DC voltage8013and a source signal8003and output the comparison result as the counter signal CNT_S2to the logic unit1035. Since the source signal8003has a value greater than the DC voltage8013during t301to t304, a counter signal CNT_S22may have a high level during t301to t304.

The counter1039may generate the count value COUNT_NUM12by counting the time for which the count signal CNT_S22maintains a certain level. Thereafter, the logic unit1035may transmit the generated count value COUNT_NUM12to the driving controller1050as a reference count value.

In some implementations, the display device1000may count the count signal CNT_S21and CNT_S22based on an internal clock.

The display device1000generates a final count value based on the first comparison result and the second comparison result (S705).

The driving controller1050may determine the final count value by performing an OR operation based on the count signal CNT_S21and CNT_S22. As shown inFIG.8, the final count value is shown as the result signal COUNT_NUM_REF, which may be a signal obtained by subtracting the count signal CNT_S21from the count signal CNT_S22. That is, the final result value may indicate a case where the source signal8003has a value between the VTOP voltage value and the VBOTTOM voltage value.

Accordingly, the driving controller1050may obtain a count value according to the slew rate of the source signal8003for the DC voltage8011and the DC voltage8013.

The display device1000measures the slew rate of the source signal8003based on the final count value (S707).

The display device1000may obtain the final count value and measure the slew rate of the source signal based on the final count value. For example, if the final count value is small, the voltage level of the source signal8003rapidly increases, so the source signal8003may have a high slew rate. For another example, when the final count value is large, the voltage level of the source signal8003gradually increases, so the source signal8003may have a low slew rate.

The driving controller1050may determine whether there is a difference between the predetermined slew rate and the slew rate measured for the source signal. If the predetermined slew rate is greater than the slew rate measured for the source signal, the driving controller1050may control the voltage generator1060to reduce the voltage provided to the channel amplifiers1021and1031. If the predetermined slew rate is smaller than the slew rate measured for the source signal, the driving controller1050may control the voltage generator1060to increase the voltage provided to the channel amplifiers1021and1031.

A display device can use a channel amplifier positioned on a source lines to measure the DC level and slew rate of the source signal of an adjacent source line. Typically, the source lines are operating in driving mode while measuring, which can make it measuring the DC level and slew rate of the source signal difficult. In other words, it may not be possible to perform tests on source signals in real time when the display device1000is driven.

FIG.9is a diagram showing an example of a display device.

As shown inFIG.9, a display device2000includes a pixel array2010and a display driving circuit2020. The display driving circuit2020includes a gate driver2030, a source driver2040, a driving controller2050, and a voltage generator2060. The configuration including the driving controller2050and the voltage generator2060may be referred to as a main logic2001. The main logic2001may further include a memory storing arbitrary data for controlling the configuration within the display device2000. However, the present disclosure is not limited thereto, and the memory may be positioned outside of the display device2000.

The pixel array2010may include a plurality of pixels PX. The pixel array2010may include the plurality of gate lines GL0, . . . , GLh−1 connected to the plurality of pixels PX, a plurality of source lines SL0, . . . , SLk−1, and a plurality of return lines RL0, . . . , RLk−1 connected to each of the plurality of source lines SL0, . . . , SLk−1.

The gate driver2030may transmit gate signals G0, . . . , Gh−1 to the plurality of gate lines GL0, . . . , GLh−1 based on the first control signal CONT1received from the driving controller2050.

The driving controller2050may drive the display device2000in a plurality of modes. For example, when the display device2000operates in a driving mode, the driving controller2050may generate the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3corresponding to the driving mode. In this case, the second control signal CONT2may be a signal that controls a plurality of switches SW21to SW26within a selector2011.

For another example, when the display device2000operates in a test mode, the driving controller2050may generate the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3corresponding to the test mode. In some implementations, the driving controller2050may measure the DC level and slew rate of the source signal Si output through the source line SLi through the return line RLi connected to the target source line SLi. The plurality of return lines RL may be connected to each of the plurality of source lines SL through a switch.

Specifically, the plurality of source lines SL within the pixel array2010may include a first test mode in which a 2n−1th (wherein n is a natural number greater than 1) disposed source line operates in a driving mode and a 2nth disposed source line operates in a comparator mode, and a second test mode in which a 2nth disposed source line operates in a driving mode and a 2n −1th (wherein n is a natural number greater than 1) disposed source line operates in a comparator mode.

When the display device2000is operating in the first test mode, the driving controller2050may generate the first control signal CONT1corresponding to the first test mode, the second control signal CONT2corresponding to the first test mode, and the third control signal CONT3corresponding to the first test mode.

When the display device2000operates in the second test mode, the driving controller2050may generate the first control signal CONT1corresponding to the second test mode, the second control signal CONT2corresponding to the first test mode, and the third control signal CONT3corresponding to the first test mode.

The voltage generator2060may generate various voltages required to drive the display device2000under the control of the driving controller2050. For example, the voltage generator2060may include the plurality of voltages VOL and the reference voltage V_REF including a plurality of gray scale voltages.

The source driver2040may include logic units2025and2035, decoders2023and2033, channel amplifiers2021and2031, and the selector2011.

Unless otherwise specified, the description of the logic units1025and1035, the decoders1023and1033, and the channel amplifiers1021and1031described with reference toFIG.3may be applied to the logic units2025and2035, the decoders2023and2033, and the channel amplifiers2021and2031.

The selector2011may be connected to the first channel amplifier2021and the second channel amplifier2031, and may be connected to the return lines RLi and RLi+1 each connected to two adjacent source lines SLi and SLi+1.

The selector2011may include first to sixth switches SW21, SW22, SW23, SW24, SW25, and SW26. The selector2011may control the connection relationship between the plurality of switches SW21to SW26within the selector2011based on the second control signal CONT2received from the driving controller2050. Specifically, the first switch SW21may connect the output terminal of the first channel amplifier2021and the first source line SLi or connect the first return line RLi. The second switch SW22may connect the output terminal of the second channel amplifier2031and the second source line SLi+1 or connect the second return line RLi+1. The third switch SW23may be connected to one end of the first switch SW21(e.g., the output terminal of the first channel amplifier2021) and the first input terminal of the second channel amplifier2031. The fourth switch SW24may be connected to one end of the second switch SW22(e.g., the output terminal of the second channel amplifier2031) and the first input terminal of the first channel amplifier2021. The fifth switch SW25may connect one end of the first switch SW12(e.g., the output terminal of the first channel amplifier2021) and the logic unit2025according to the second control signal CONT2or connect one end of the second switch SW12and the first input terminal of the first channel amplifier2021. The sixth switch SW26may connect one end of the first switch SW22(e.g., the output terminal of the second channel amplifier2031) and the logic unit2035according to the second control signal CONT2or connect one end of the second switch SW22and the first input terminal of the second channel amplifier2031. InFIG.3, the first switch SW21, the second switch SW22, the fifth switch SW25, and the sixth switch SW26are each shown as one SPDT switch, but the present disclosure is not limited thereto. In some implementations, each of the first switch SW21, the second switch SW22, the fifth switch SW25, and the sixth switch SW26may be implemented as two switches.

When the display device2000operates in a driving mode, the driving controller2050may generate the second control signal CONT2corresponding to the driving mode and transmit the second control signal CONT2to the selector2011, as described above. Based on the second control signal CONT2corresponding to the driving mode, the first switch SW21may connect the output terminal of the first channel amplifier2021and the first source line SLi, and the second switch SW22may connect the output terminal of the second channel amplifier2031and the second source line SLi+1. The third switch SW23, the fourth switch SW24, the fifth switch SW25, and the sixth switch SW26may be turned off. Accordingly, the selector2011may receive the first source signal Si from the first channel amplifier2021and transmit the first source signal Si to the source line SLi and may receive the second source signal Si+1 from the second channel amplifier2031and transmit the second source signal Si+1 to the source line SLi+1.

When the display device2000operates in a test mode, the driving controller2050may generate the second control signal CONT2corresponding to the test mode and transmit the second control signal CONT2to the selector2011, as described above.

For example, when the display device2000is operating in the first test mode, the second control signal CONT2may be a signal that controls the selector1011to output the source signal Si to the corresponding source line SLi and controls the selector2022to transmit the source signal Si to the first input end of the channel amplifier2021connected to the source line SLi.

In the case of the first test mode, based on the second control signal CONT2corresponding to the first test mode, the first switch SW21may be connected to the first return line RLi, the second switch SW22may be connected to the second source line SLi+1, the third switch SW23may be turned on, the fourth switch SW24may be turned off, the fifth switch SW25may connect one end of the first switch SW21and the first input terminal of the first channel amplifier2021, and the sixth switch SW26may connect the output terminal of the second channel amplifier2031and the logic unit2035. Accordingly, the selector2011may receive the first return signal Ri from the first channel amplifier2021and transmit the first return signal Ri to the first input terminal of the second channel amplifier2031through the third switch SW23. The second channel amplifier2031may compare the first return signal Ri input to the first input terminal and the reference voltage received from the second decoder2033, and transmit the comparison result to the logic unit2035through the sixth switch SW26.

In some implementations, the return signal Ri input to the first input terminal of the second channel amplifier2031through the return line RLi may be a signal from a corresponding source line SLi that has been transmitted to the pixel spaced far away from the source driver2040through the plurality of gate lines GL and then returned.

In this case, the switch connecting the return line RLi and the source line SLi may be turned on. Since the return signal Ri is a signal that is transmitted through a plurality of gate lines GL and then returns again, the return signal Ri may be different from the source signal Si output from the output terminal of the first channel amplifier2021. In some implementations, the first input terminal of the channel amplifier may be an inverting input terminal of the channel amplifier, and the second input terminal may be a non-inverting input terminal of the channel amplifier.

The third control signal CONT3may be a signal that controls the voltage generator2060to transmit a plurality of gray scale voltages to the decoder2023as the plurality of voltages VOL and the reference voltage V_REF to the decoder2033. In this case, the reference voltage V_REF may be input to the second channel amplifier2031through the decoder2023.

For another example, in the case of the second test mode, based on the second control signal CONT2corresponding to the second test mode, the first switch SW21may be connected to the first source line SLi, the second switch SW22may be connected to the second source line RLi+1, the third switch SW23may be turned off, the fourth switch SW24may be turned on, the fifth switch SW25may connect the output terminal of the first channel amplifier2021and the logic unit2025, and the sixth switch SW26may connect the output terminal of the second channel amplifier2031and the first input terminal of the second channel amplifier2031. Accordingly, the selector2011may receive the second return signal Ri+1 from the second channel amplifier2031and transmit the second return signal Ri+1 to the first input terminal of the first channel amplifier2021through the fourth switch SW24. The first channel amplifier2021may compare the second return signal Ri+1 input to the first input terminal and the reference voltage received from the first decoder2023, and transmit the comparison result to the logic unit2025through the fifth switch SW25.

The second control signal CONT2may be a signal that controls the selector2011to output the source signal Si+1 to the source line SLi+1 and controls the selector2011to transmit the source signal Si+1 as the return signal RLi+1 to the first input end of the channel amplifier2021through the return line RLi+1 connected to the source line SLi+1. The third control signal CONT3may be a signal that controls the voltage generator2060to transmit a plurality of gray scale voltages to the second decoder2033as the plurality of voltages VOL and the reference voltage V_REF to the first decoder2023. In this case, the reference voltage V_REF may be input to the first channel amplifier2021through the first decoder2023.

FIG.10is a diagram showing an example of a display device.

As shown inFIG.10, a display device3000includes a pixel array3010and a display driving circuit3020. The display driving circuit3020includes a gate driver3030, a source driver3040, a driving controller3050, and a voltage generator3060. A configuration including the driving controller3050and the voltage generator3060may be referred to as a main logic3001. The main logic3001may further include a memory storing arbitrary data for controlling the configuration within the display device3000. However, the present disclosure is not limited thereto, and the memory may be positioned outside of the display device3000.

The pixel array3010may include a plurality of pixels PX. The pixel array3010may include the plurality of gate lines GL0, . . . , GLh−1 connected to the plurality of pixels PX, a plurality of source lines SL0, . . . , SLk−1, and a plurality of return lines RL0, . . . , RLk−1 connected to each of the plurality of source lines SL0, . . . , SLk−1.

The gate driver3030may transmit gate signals G0, . . . , Gh−1 to the plurality of gate lines GL0, . . . , GLh−1 based on the first control signal CONT1received from the driving controller3050.

The driving controller3050may drive the display device3000in a plurality of modes. For example, when the display device3000operates in a driving mode, the driving controller3050may generate the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3corresponding to the driving mode. In this case, the second control signal CONT2may be a signal that controls a plurality of switches SW31to SW34within a selector3011. The third control signal CONT3may be a signal that controls the voltage generator3060to generate a voltage provided to the source driver3040.

For another example, when the display device3000operates in a test mode, the driving controller3050may generate the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3corresponding to the test mode. In some implementations, the driving controller3050may measure the DC level and slew rate of the source signal Si output through the source line SLi through the return line RLi connected to the target source line SLi.

When the display device3000operates in the test mode, the driving controller3050may generate the first control signal CONT1corresponding to the test mode, the second control signal CONT2corresponding to the test mode, and the third control signal CONT3corresponding to the test mode. For example, when the display device3000is operating in the test mode, the second control signal CONT2may be a signal that controls the selector3011to output the source signal Si to the corresponding source line SLi and controls the selector3011to transmit the return signal Ri corresponding to the source signal Si to a comparator3101.

The third control signal CONT3may be a signal that controls the voltage generator3060to generate a plurality of gray scale voltages as the plurality of voltages VOL and transmit the plurality of gray scale voltages to a decoder3103and generate reference voltages V_REF1and V_REF2and transmit the reference voltages V_REF1and V_REF2to the comparator3101.

The voltage generator3060may generate various voltages required to drive the display device3000under the control of the driving controller3050. For example, the voltage generator3060may generate a plurality of voltages VOL and a plurality of reference voltages V_REF1and V_REF2including a plurality of gray scale voltages.

The source driver3040may include a logic unit3105, the decoder3103, a channel amplifier3102, the comparator3101, and the selector3011.

The source driver1040may convert the image data DATA received from the driving controller3050into the source signal Si and output the source signal Si through the second source line (SLi, i is an integer greater than 0 and less than or equal to k−2). The source driver3040may generate a count value COUNT_NUM31based on the DC level and slew rate measured based on the return signal Ri corresponding to the source signal Si and the reference voltage.

The logic unit3105may receive image data DATA from the driving controller3050and transmit the count value COUNT_NUM31to the driving controller3050.

The logic unit3105may include a latch3107and a counter3109.

The latch3107may receive image data DATA from the driving controller3050. The latch3107may sample and store image data DATA under the control of the driving controller3050. The latch3107may transmit sampled image data to the decoder3103. In some implementations, the latch3107may include a sampling circuit that samples data and a holding latch that stores data sampled by the sampling circuit.

The counter3109generates a first count value COUNT_NUM31based on a counter input signal CNT_S received from the comparator3101. Here, the counter input signal CNT_S may be a signal indicating the comparison result of comparing the source signal Si and the reference voltage or the comparison result of comparing the return signal Ri corresponding to the source signal Si and the reference voltage. The counter3109may transmit the generated count value COUNT_NUM31to the driving controller3050.

InFIG.10, the latch3107and the counter3109are shown as being included in the logic unit3105. However, the present disclosure is not limited thereto, and the latch3107and the counter3109may be configured in separate configurations.

The decoder3103may receive sampled image data from the latch3107and receive the plurality of voltages VOL from the voltage generator3060. The plurality of voltages VOL may include gamma voltages corresponding to various levels of luminances of the display device3000. In some implementations, the decoder1023may select one of the plurality of voltages VOL in response to sampled image data. The decoder3103may output the selected gamma voltage(s) to the channel amplifier3102. For example, decoder3103may be implemented as a digital-to-analog converter.

The channel amplifier3102may receive the gamma voltage selected from the decoder3103, amplify the gamma voltage selected by the decoder3103in response to the second control signal CONT2received from the driving controller3050, and transmit the selected gamma voltage to the selector3011as the source signal Si.

The selector3011may be connected to the channel amplifier3102, the comparator3101, the source line SLi, the return line RLi, and the voltage generator3060. The selector3011may include first to fourth switches SW31, SW32, SW33, and SW34. The selector3011may control the connection relationship between the plurality of switches SW31to SW34within the selector3011based on the second control signal CONT2received from the driving controller3050. Specifically, the first switch SW31may be connected between a voltage line providing the first reference voltage V_REF1and the first input terminal of the comparator3101. The second switch SW32may connect the second input terminal of the comparator3101and the return line RLi or connect the return line RLi and the source line SLi. The third switch SW33may be connected between the second input terminal of the comparator3101and a voltage line providing the second reference voltage V_REF2. The fourth switch SW34may be connected between the output terminal of the channel amplifier3102and the source line SLi. InFIG.10, each of the second switches SW32are shown as one SPDT switch, but the present disclosure is not limited thereto. For example, the second switch SW32may be implemented as two switches.

When the display device3000operates in a driving mode, the driving controller3050may generate the second control signal CONT2corresponding to the driving mode and transmit the second control signal CONT2to the selector3011, as described above.

Based on the second control signal CONT2corresponding to the driving mode, the first switch SW31and the fourth switch SW32may be turned on, the second switch SW32may connect the comparator3101and the return line RLi or the source line SLi, and the third switch SW33may be turned off. Accordingly, the selector3011may receive the source signal Si from the channel amplifier3102and transmit the source signal Si to the source line SLi through the fourth switch SW34.

The display device3000may operate in a test mode at the same time as operating in a driving mode. For example, when the display device3000operates in the DC level measurement mode, the first switch SW31and the fourth switch SW34may be turned on, the second switch SW32may connect the comparator3101and the return line RLi or the source line SLi, and the third switch SW33may be turned off. In some implementations, the first reference voltage V_REF1may be a sawtooth waveform voltage used to measure the DC level of the source signal Si. When the display device3000operates in the DC level measurement mode, the driving controller3050may compare the return signal Ri or the source signal Si and the first reference voltage V_REF1.

When comparing the first reference voltage V_REF1and the second reference voltage V_REF2to measure the DC level of the source signal Si, the first switch SW31may connect the comparator3101and the first reference voltage V_REF1, and the third switch SW33may be turned on. Accordingly, the comparator3101may compare the first reference voltage V_REF1and the second reference voltage V_REF2.

For another example, when the display device3000operates in the slew rate measurement mode, the first switch SW31and the fourth switch SW34may be turned on, the second switch SW32may connect the comparator3101and the return line RLi or the source line SLi, and the third switch SW33may be turned off. In some implementations, the second reference voltage V_REF2may be a DC voltage used to measure the slew rate of the source signal Si. When the display device3000operates in the slew rate measurement mode, the driving controller3050may compare the return signal Ri and the second reference voltage V_REF2. When the display device3000operates in the slew rate measurement mode, the second switch SW32may be set to connect the comparator3101and the return line RLi to accurately measure the change in the source signal Si.

The source driver3040includes a plurality of comparators, and each of the plurality of comparators is connected to the plurality of source lines SLi and each of the plurality of return lines RLi corresponding to the plurality of source lines Si. Therefore, the display device3000may measure the DC level or slew rate of the source signal Si even when operating in driving mode.

Accordingly, the display device3000may correct image data in real time based on the DC level or slew rate of the source signal Si measured while the display device3000operates in a driving mode. In some implementations, the display device3000may also correct the image signal (IS inFIG.1) in real time based on the DC level or slew rate of the source signal Si measured while the display device3000operates in a driving mode.

FIG.11is a diagram showing an example of a display device.

As shown inFIG.11, a display device4000includes a pixel array4010and a display driving circuit4020. The display driving circuit4020may include a gate driver4030, a source driver4040, a driving controller4050, and a voltage generator4060. The configuration including the driving controller4050and the voltage generator4060may be referred to as the main logic201. A main logic4001may further include a memory storing arbitrary data for controlling the configuration within the display device4000. However, the present disclosure is not limited thereto, and the memory may be positioned outside of the display device4000.

Unless otherwise specified, the display device4000may be similar to the display device3000described with reference toFIG.10.

As shown inFIG.11, the source driver4040may have comparators connected to only source line SL0and source line SLk−1 positioned at both ends of the plurality of source lines SL0, . . . , SLk−1 within the pixel array4010.

As the number of source lines increases, the load applied to the display panel may further increase. Accordingly, in order to reduce the load on the source line SL connected to the pixel array4010, a representative characteristic of the source signals Si, Sk−1 provided to both ends of the pixel array4010can be measured. However, the present disclosure is not limited thereto, and the configuration of the source driver including a comparator to measure the characteristics of the source signal Si may be disposed on any source line SL.

FIG.12is a diagram showing unless otherwise specified a display device.

As shown inFIG.12, a display device5000includes a pixel array5010and a display driving circuit5020. The display driving circuit5020includes a gate driver5030, a source driver5040, a driving controller5050, and a voltage generator5060. The configuration including the driving controller5050and the voltage generator5060may be referred to as the main logic201. A main logic201may further include a memory storing arbitrary data for controlling the configuration within the display device5000. However, the present disclosure is not limited thereto, and the memory may be positioned outside of the display device5000.

The pixel array5010may include a plurality of pixels PX. The pixel array5010may include the plurality of gate lines GL0, . . . , GLh−1 connected to the plurality of pixels PX, the plurality of source lines SL0, . . . , SLk−1, and the plurality of return lines RL0, . . . , RLk−1 connected to each of the plurality of source lines SL0, . . . , SLk−1.

The gate driver5030may transmit the gate signals G0, . . . , Gh−1 to the plurality of gate lines GL0, . . . , GLh−1 based on the first control signal CONT1received from the driving controller5050.

The driving controller5050may drive the display device5000in a plurality of modes. For example, when the display device5000operates in a driving mode, the driving controller5050may generate the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3corresponding to the driving mode. In this case, the second control signal CONT2may be a signal that controls a plurality of switches SW51to SW53within a selector5111. The third control signal CONT3may be a signal that controls the voltage generator5060to generate a voltage provided to the source driver5040.

For example, when the display device5000operates in a test mode, the driving controller5050may generate the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3corresponding to the test mode. In some implementations, the driving controller5050may measure the DC level and slew rate of the source signal Si output through the source line SLi through the return line RLi connected to the target source line SLi.

When the display device5000operates in the test mode, the driving controller5050may generate the first control signal CONT1corresponding to the test mode, the second control signal CONT2corresponding to the test mode, and the third control signal CONT3corresponding to the test mode. For example, when the display device5000is operating in the test mode, the second control signal CONT2may be a signal that controls the selector5111to output the source signal Si to the corresponding source line SLi and controls the selector5111to transmit the return signal Ri corresponding to the source signal Si to a channel amplifier5101.

The third control signal CONT3may be a signal that controls the voltage generator5060to generate a plurality of gray scale voltages as the plurality of voltages VOL and transmit the plurality of gray scale voltages to a decoder5103and generate reference voltages V_REF1and V_REF2and transmit the reference voltages V_REF1and V_REF2to the channel amplifier5101.

The voltage generator5060may generate various voltages required to drive the display device5000under the control of the driving controller5050. For example, the voltage generator5060may generate a plurality of voltages VOL and a plurality of reference voltages V_REF1and V_REF2including a plurality of gray scale voltages.

The source driver5040may include a channel amplifier5101, a comparator5102, a decoder5103, a logic unit5105, a counter5109, and a selector5111.

The source driver5040may convert the image data DATA received from the driving controller5050into the source signal Si and output the source signal Si through the second source line (SLi, i is an integer greater than 0 and less than or equal to k−2). The source driver5040may generate a count value COUNT_NUM51based on the DC level and slew rate measured based on the return signal Ri corresponding to the source signal Si and the reference voltage.

The logic unit5105may receive image data DATA from the driving controller5050. The logic unit5105may include a latch5107. The latch5107may receive image data DATA from the driving controller5050. The latch5107may sample and store image data DATA under the control of the driving controller5050. The latch5107may transmit sampled image data to the decoder5103. In some implementations, the latch5107may include a sampling circuit that samples data and a holding latch that stores data sampled by the sampling circuit.

The counter5109generates a count value COUNT_OUT based on the counter input signal CNT_S received from the comparator5102. Here, the counter input signal CNT_S may be a signal indicating the comparison result of comparing the source signal Si and the reference voltage or the comparison result of comparing the return signal Ri corresponding to the source signal Si and the reference voltage. The counter5109may transmit the generated count value COUNT_OUT to the driving controller5050. For example, the counter5109may transmit the count value COUNT_OUT to the logic unit5105, and the logic unit5105may transmit the count value COUNT_OUT received from the counter5109to the driving controller5050.

The decoder5103may receive sampled image data from the latch5107and may receive the plurality of voltages VOL from the voltage generator5060. The plurality of voltages VOL may include gamma voltages corresponding to various levels of luminances of the display device5000. In some implementations, the decoder5103may select one of the plurality of voltages VOL in response to sampled image data. The decoder5103may output the selected gamma voltage(s) to the channel amplifier5101. For example, the decoder5103may be implemented as a digital-to-analog converter.

The channel amplifier5101may receive the gamma voltage selected from the decoder5103, amplify the gamma voltage selected by the decoder5103in response to the second control signal CONT2received from the driving controller5050, and transmit the selected gamma voltage to the selector5111as the source signal Si.

The selector5111may be connected to the channel amplifier5101, the comparator5102, the source line SLi, the return line RLi, and the voltage generator5060. The selector5111may include first to fourth switches SW51, SW52, and SW53. The selector5111may control the connection relationship between the plurality of switches SW51to SW53within the selector5111based on the second control signal CONT2received from the driving controller5050. Specifically, the first switch SW51may connect the first input terminal of the comparator5102and the return line RLi or connect the first input terminal of the comparator5102and the source line SLi. The second switch SW52may be connected between the second input terminal of the comparator5102and a voltage line providing the second reference voltage V_REF2. The third switch SW53may be connected between the output terminal of the channel amplifier5101and the source line SLi. InFIG.10, each of the first switches SW51are shown as one SPDT switch, but the present disclosure is not limited thereto. In some implementations, the first switch SW51may be implemented as two switches.

When the display device5000operates in a driving mode, the driving controller5050may generate the second control signal CONT2corresponding to the driving mode and transmit the second control signal CONT2to the selector5111, as described above.

Based on the second control signal CONT2corresponding to the driving mode, the first switch SW51may connect the channel amplifier5101and the return line RLi or the source line SLi, the second switch SW52may be turned off, and the third switch SW53may be turned on. Accordingly, the selector5111may receive the source signal Si from the channel amplifier5101and transmit the source signal Si to the source line SLi through the third switch SW53.

The display device5000may operate in a test mode at the same time as operating in a driving mode. For example, when the display device5000operates in the DC level measurement mode, the first switch SW51may connect the channel amplifier5101and the return line RLi or the source line SLi, the second switch SW52may be turned off, and the third switch SW53may be turned on. In some implementations, the first reference voltage V_REF1may be a sawtooth waveform voltage used to measure the DC level of the source signal Si. When the display device5000operates in the DC level measurement mode, the driving controller5050may compare the return signal Ri or the source signal Si and the first reference voltage V_REF1.

When comparing the first reference voltage V_REF1and the second reference voltage V_REF2to measure the DC level of the source signal Si, the first switch SW31may be turned off, the second switch SW52may be connected to the second reference voltage V_REF2, and the third switch SW53may be turned on or turned off. Accordingly, the comparator3101may compare the first reference voltage V_REF1and the second reference voltage V_REF2.

For example, when the display device5000operates in the slew rate measurement mode, the first switch SW51may connect the channel amplifier5101and the return line RLi or the source line SLi, the second switch SW52may be turned off, and the third switch SW53may be turned on. In some implementations, the second reference voltage V_REF2may be a DC voltage used to measure the slew rate of the source signal Si. When the display device5000operates in the slew rate measurement mode, the first switch SW51may be set to connect the comparator3101and the return line RLi to accurately measure the change in the source signal Si.

The source driver5040includes a comparator connected to the plurality of source lines SL and may measure the DC level or slew rate of the source signal Si for all source lines SL through the comparator5102by controlling the source signal Si input into the comparator5102.

FIG.13is a diagram of an example of a display system.

Referring toFIG.13, a display system1300includes a processor1310, a memory1320, a display device1330, and a peripheral device1340that are electrically connected to a system bus1350.

The processor1310controls the input and output of data from the memory1320, the display device1330, and the peripheral device1340, and may perform image processing of image data transmitted between the corresponding devices.

The memory1320may include volatile memory such as dynamic random access memory (DRAM) and/or non-volatile memory such as flash memory. The memory1320may include DRAM, phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), NOR flash memory, NAND flash memory, and fusion flash memory (for example, memory combined with static random access memory (SRAM) buffer and NAND flash memory and NOR interface logic).

The memory1320may store image data obtained from the peripheral device1340or an image signal processed by the processor1310.

The display device1330includes a display panel1331and may display image data transmitted through the system bus1350on the display panel1331. The display panel1331may be a display panel. The display panel1331may include a driving circuit1332. The driving circuit1332may measure the DC level for the source signal provided from the driving circuit1332to the display panel1331and the slew rate of the source signal. Thereafter, the driving circuit1332may modify the image data based on the measured DC level and slew rate.

The peripheral device1340may be a device that converts moving images or still images, such as a camera, scanner, or webcam, into electrical signals. Image data obtained through the peripheral device1340may be stored in the memory1320or displayed on the display panel1331in real time.

The display system1300may be provided in a mobile electronic product such as a smartphone, but is not limited thereto, and may be provided in various types of electronic products that display images.

While examples of the present disclosure have been described in detail, it is to be understood that the disclosure is not limited to the disclosed examples, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

In some implementations, each constituent element or combination of two or more constituent elements described with reference toFIGS.1to13may be implemented as a digital circuit, a programmable or non-programmable logic device or array, or an application specific integrated circuit (ASIC), and the like.

While this disclosure contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed. Certain features that are described in this disclosure in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a combination can in some cases be excised from the combination, and the combination may be directed to a subcombination or variation of a subcombination.

While the embodiments of the present disclosure have been described in detail, it is to be understood that the disclosure is not limited to the disclosed implementations, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.