Patent ID: 12213391

DETAILED DESCRIPTION

To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

FIG.1toFIG.7are schematic cross-sectional views illustrating the steps of a manufacturing process for forming a resistive random access memory (RRAM) according to an embodiment of the present invention. Please refer toFIG.1. A substrate10is provided10. Subsequently, a first dielectric layer16is formed on the substrate10, and a bottom electrode20is formed on the first dielectric layer16.

According to an embodiment of the present invention, the resistive random access memory may be formed in a dielectric layer of an interconnecting structure on the substrate10. The substrate10may have finished the front-end-online (FEOL) processes and may include, for example, isolations structures, transistors and contacts formed therein. The substrate10may also have finished a portion of the back-end-online (BEOL) process and may include dielectric layers and conductive structures formed therein. For the sake of simplicity, only a dielectric layer14and a conductive structure12formed in the dielectric layer14are shown inFIG.1. According to an embodiment of the present invention, the first dielectric layer16may include an etching stop layer16aand a pad layer16bdisposed on the etching stop layer16a. A conductive via18may be formed in the first dielectric layer16and penetrates through the pad layer16band the etching stop layer16ato be electrically connected to the conductive structure12.

The dielectric layer14and the pad layer16bmay include dielectric materials such as silicon oxide (SiO2), undoped silica glass (USG), or low-k dielectric materials such as fluorinated silica glass (FSG), hydrogenated silicon oxycarbide (SiCOH), spin-on glass, porous low-k dielectric materials, or organic polymer dielectric materials, but are not limited thereto. According to an embodiment of the present invention, the dielectric layer14includes a low-k dielectric material, and the pad layer16bincludes silicon oxide. The etching stop layer16amay include a nitrogen-containing dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or nitride doped silicon carbide (NDC), but is not limited thereto. According to an embodiment of the present invention, the etching stop layer16amay include nitride doped silicon carbide. The bottom electrode20, the conductive structure12, and the conductive via18may include metals, such as cobalt (Co), copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), platinum (Pt), tantalum (Ta), titanium (Ti), compounds of the above materials, composite layers of the above materials, or alloys of the above materials, but are not limited thereto. According to an embodiment of the present invention, the bottom electrode20may include titanium nitride (TiN), the conductive structure12may include copper (Cu), and the conductive via18may include tungsten (W). According to an embodiment of the present invention, a barrier layer (not shown) may be disposed between the conductive via18and the first dielectric layer16and the conductive structure12. The barrier layer may include a single layer or multiple layers formed by, for example, titanium, titanium nitride, tantalum, and/or tantalum nitride.

Please refer toFIG.2. Following, a second dielectric layer22is formed on the first dielectric layer16and covers the bottom electrode20. The material of the second dielectric layer22may be selected from the dielectric materials for the dielectric layer14and the pad layer16bpreviously illustrated, and will not be repeated here for the sake of simplicity. According to an embodiment of the present invention, the second dielectric layer22may include a low-k dielectric material.

Please refer toFIG.3. Subsequently, a patterning process (such as a photolithography-etching process) may be carried out to form an opening24in the second dielectric layer22directly above the bottom electrode20. A portion of the top surface20aof the bottom electrode20is exposed from the opening24. The width of the opening24may be approximately equal to or smaller than the width of the bottom electrode20. In the embodiment shown inFIG.3, the width of the opening24is smaller than the width of the bottom electrode20, and a sidewall24aof the opening24may be disposed on the top surface20aof the bottom electrode20and is not aligned with the sidewall of the bottom electrode20. The top corner20bof the bottom electrode20may be encompassed by the second dielectric layer22and not exposed.

Please refer toFIG.4. Subsequently, a spacer26is formed on the sidewall24aof the opening24. According to an embodiment of the present invention, the spacer26may be formed by a self-aligned spacer process. For example, an atomic layer deposition (ALD) process may be performed to form a spacer material layer (not shown) conformally covering the top surface of the second dielectric layer22, the sidewall24aof the opening24, and the top surface20aof the bottom electrode20. After that, an anisotropic etching process may be performed to etch the spacer material layer until the top surface of the second dielectric layer22and the top surface20aof the bottom electrode20are exposed, and a portion of the spacer material layer is remained on the sidewall24aof the opening24to form the spacer26. It should be understood that the spacer26may be formed along the sidewall24aof the opening24and completely surrounds the opening24. According to an embodiment of the present invention, the spacer26may include aluminum oxide (Al2O3) or silicon oxide (SiO2), but is not limited thereto. It is noteworthy that, an inner sidewall26aof the spacer26is exposed from the opening24and may include a curved cross-sectional profile due to the anisotropic etching process. An outer sidewall26bof the spacer26contacts the second dielectric layer22and may include a cross-sectional profile conformal to the sidewall24aof the opening24. For example, the outer sidewall26bof the spacer26may include a straight cross-sectional profile.

Please refer toFIG.5. After forming the spacer26, a variable-resistance material layer28is formed on the second dielectric layer22. The variable-resistance material layer28partially fills the opening24and covers along the outer sidewall26aof the spacer26and the top surface20aof the bottom electrode20. Subsequently, a top electrode material layer30is formed on the variable-resistance material layer28and completely fills the opening24. The top electrode material layer30may include transition metal oxides (TMO), such as nickel oxide (NiO), titanium dioxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (TaO), but is not limited thereto. The material of the top electrode material layer30may be selected from the metals for the bottom electrode20, such as titanium nitride (TiN).

Please refer toFIG.6. Subsequently, a planarization process such as a chemical mechanical polishing (CMP) process may be performed to remove the top electrode material layer30and the variable-resistance material layer28outside the opening24until the top surface of the second dielectric layer22is exposed. The top electrode material layer30and the variable-resistance material layer28remaining in the opening24become the top electrode30aand the variable-resistance layer28a, respectively. According to an embodiment of the present invention, after the planarization process, a top surface of the spacer26between the top electrode30aand the second dielectric layer22may be exposed and flush with the top surface of the top electrode30a, the top surface of the variable-resistance layer28a, and the top surface of the second dielectric layer22along the horizontal direction.

Please continue to refer toFIG.6. The memory cell100of the resistive random access memory according to an embodiment of the present invention includes a bottom electrode20, a variable-resistance layer28adisposed on the bottom electrode20and having a U-shaped cross-sectional profile, a top electrode30adisposed on the variable-resistance layer28aand completely filling the recess28R in the variable-resistance layer28a, and a spacer26disposed on the bottom electrode20and aside the variable-resistance layer28a. To be more detailed, the variable-resistance layer28amay include a horizontal portion28band a vertical portion28clocated on the horizontal portion28b. The horizontal portion28bis substantially between the top electrode30band the bottom electrode20along the vertical direction, while the vertical portion28cis substantially between the top electrode30band the spacer26along the horizontal direction. It should be noted that the process parameters for forming the variable-resistance material layer28(seeFIG.5) may be adjusted to make the thickness T1of the horizontal portion28bof the variable-resistive layer28aalong the vertical direction larger than the thickness T2of the vertical portion28calong the horizontal direction. In this way, when the thickness T1of the horizontal portion28breaches the required specification, the thickness T2of the vertical portion28cmay be smaller to provide a recess28R with a larger width, so that the top electrode30ain the recess28R may be formed with a larger width, which may provide a larger process window for the conductive via34(seeFIG.7) to land on the top electrode30aand electrically connect to the top electrode30a. According to an embodiment of the present invention, the thickness T2of the vertical portion28cmay be approximately between ¼ and 1/10 of the thickness T1of the horizontal portion28b.

Please refer toFIG.7. Following, a third dielectric layer32is formed on the second dielectric layer22. A conductive via34is formed in the third dielectric layer32directly above the top electrode30aand electrically connected to the top electrode30a. The material of the third dielectric layer32may be selected from the dielectric materials for the dielectric layer14and the pad layer16bpreviously illustrated, and will not be repeated here for the sake of simplicity. According to an embodiment of the present invention, the third dielectric layer32and the second dielectric layer22may include a same material, such as a low-k dielectric material. The third dielectric layer32is in direct contact with the top surface of the top electrode30a, the top surface of the vertical portion28cof the variable-resistance layer28a, the top surface of the spacer26, and the top surface of the second dielectric layer22. The material of the conductive via34may be selected from the metals for the conductive structure12, such as copper (Cu). According to an embodiment of the present invention, a barrier layer (not shown) may be disposed between the conductive via34and the third dielectric layer32and the top electrode30a. The barrier layer may include a single layer or multiple layers formed by, for example, titanium, titanium nitride, tantalum, and/or tantalum nitride.

FIG.8,FIG.9andFIG.10are schematic top views of the resistive random access memories at the step shown inFIG.6according to some embodiments of the present invention. As shown in the top view, the resistive random access memory includes a plurality of memory cells100that are arranged into an array and are spaced apart from each other by a distance S1. The shape of the top electrode30aof the memory cell100is substantially determined by the shape of the opening24. For example, the top electrode30amay have a circular shape (FIG.8), a square shape (FIG.9), or a rectangular shape (FIG.10), but is not limited thereto. The area of the top electrode30ais smaller than the area of the opening24because of the spacer26formed in the opening24. The top electrode30ais completely surrounded by the variable-resistive layer28(specifically, by the vertical portion28cof the variable-resistive layer28), and the variable-resistive layer28is completely surrounded by the spacer26.

One feature of the present invention is that the memory cells100of the resistive random access memory are formed by a process similar to a damascene process, which includes the steps of forming the second dielectric layer22, forming the openings24corresponding to the memory cells to be formed in the second dielectric layer22, forming the variable-resistance material layer28and the top electrode material layer30on the second dielectric layer22and filling the openings24, and then removing the variable-resistance material layer28and the top electrode material layer30outside the openings24to obtain the variable-resistance layer28aand the top electrode30aof the memory cells100. There is no need for the present invention to form a dielectric layer to fill the gaps between the memory cells100, so that voids caused by insufficient gap fill capability of the dielectric layer may be prevented. In this way, the distance S1between memory cells100may be further reduced without being limited by the gap fill capability of the dielectric layer, and a higher array density and memory capacity may be achieved.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.