Patent ID: 12205668

DETAILED DESCRIPTION

FIGS.1and2are block diagrams provided in order to describe operations of memory systems according to an example embodiment.FIG.1illustrates, as a comparative example, a schematic block diagram of a general memory system10.FIG.2illustrates a schematic block diagram of a memory system100according to an example embodiment.

First, referring toFIG.1, a general memory system10according to the comparative example may include a host20and a memory device30.

The host20may include a controller23capable of controlling the memory device30, may exchange a data signal DQ with the memory device30through a controller interface21, and may transmit a command signal CMD and an address signal ADDR to the memory device30.

The memory device30may be connected to the host20through the memory interface31, and may include a logic circuit33, a memory cell array34, and the like. A plurality of signal transmission paths may be formed between pads22of the controller interface21and pads32of the memory interface31.

The memory device30may operate based on clock signals CK0and CK1, data strobe signals DQS0and DQS1, and the like, transmitted by the host20. The clock signals CK0and CK1may have opposite phases, and the data strobe signals DQS0and DQS1may also have opposite phases.

In the general memory system10, the memory device30may receive or output the data signal DQ based on the data strobe signals DQS0and DQS1. Accordingly, a data transfer rate between the host20and the memory device30may be increased by increasing frequencies of the data strobe signals DQS0and DQS1. However, the ability to increase the data transfer rate between the host20and the memory device30by increasing frequencies of the data strobe signals DQS0and DQS1may be limited.

Next, referring toFIG.2, the memory system100according to an example embodiment may include a host110and a memory device120.

The host110may be or include an arithmetic processing device such as an application processor, a central processing unit, or a system-on-chip, and may include a controller interface111and a controller113.

The memory device120may include a memory interface121, a logic circuit123, a memory cell array124, and the like.

A plurality of signal transmission paths may be formed between pads112of the controller interface111and pads122of the memory interface121.

The memory device120may receive clock signals CK (e.g., a first clock signal CK0, a second clock signal CK1, a third clock signal CK2, and a fourth clock signal CK3), a command signal CMD, an address signal ADDR, and the like, from the host110, and exchange a data signal DQ with the host110, through the memory interface121.

In further detail, the host110may transmit the first to fourth clock signals CK0to CK3having different phases to the memory device120. The memory device120may generate data strobe signals using at least some of first to fourth clock signals CK0to CK3. The memory device120may not separately receive the data strobe signals DQS0and DQS1, unlike the comparative example illustrated inFIG.1.

In the example embodiment described with reference toFIG.2, a data transfer rate between the host110and the memory device120may be improved using the first to fourth clock signals CK0to CK3.

In an example embodiment, the second clock signal CK1may have a phase difference of 90° with respect to the first clock signal CK0, the third clock signal CK2may have a phase difference of 180° with respect to the first clock signal CK0, and the fourth clock signal CK3may have a phase difference of 270° with respect to the first clock signal CK0. Accordingly, rising edges of each of the first to fourth clock signals CK0to CK3may appear in order. When the memory device120receives the data signal DQ, the memory device120may sample the data signal DQ at the rising edges of each of the first to fourth clock signals CK0to CK3. Accordingly, the data transfer rate between the host110and the memory device120may be increased by using the first to fourth clock signals CK0to CK3having the same frequency as the data strobe signals DQS0and DQS1in the comparative example illustrated inFIG.1.

When comparing the comparative example ofFIG.1and the example embodiment ofFIG.2with each other, in the example embodiment illustrated inFIG.2, the data signal DQ may be processed using the first to fourth clock signals CK0-CK3as the data strobe signals, and thus, there may be no separate signal paths through which the data strobe signals are transmitted. Accordingly, the number of signal transmission paths connecting the host110and the memory device120to each other may be the same as that in the comparative example ofFIG.1. In other words, the numbers of pads112and122included respectively in the controller interface111and the memory interface121may be the same as in those in the comparative example ofFIG.1.

Under some conditions, it is possible that phase skew between the first to fourth clock signals CK0to CK3may occur due to various causes, and a difference between effective time periods during which the data signal may be sampled in sampling circuits sampling the data signal DQ in synchronization with the first to fourth clock signals CK0to CK3may occur.

With reference to the above, in an example embodiment, the host110may remove phase skew between the first to fourth clock signals CK0to CK3, align phases of the first to fourth clock signals CK0to CK3and the data signal DQ with each other, and transmit the first to fourth clock signals CK0to CK3and the data signal DQ to the memory device120.

As an example, the controller interface111of the host110may intentionally misalign the first to fourth clock signals CK0to CK3and the data signal DQ with each other, and then output the first to fourth clock signals CK0to CK3and the data signal DQ so that the phases of the data signal DQ and the first to fourth clock signals CK0to CK3may be aligned with each other in the sampling circuits inside the memory device120. This will be described in additional detail below.

FIGS.3and4are, respectively, a schematic block diagram and a schematic circuit diagram illustrating a memory device according to an example embodiment.

Referring toFIG.3, a memory device150according to an example embodiment may be a storage device based on a semiconductor element. The memory device150may be a random access memory (RAM) device such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double date rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase-change RAM (PRAM), a magnetic RAM (MRAM), or a resistive RAM (RRAM).

The memory device150may store data received through the data signal DQ or may output data as the data signal DQ in response to an address signal ADDR and a command signal CMD received from an external host (e.g., a central processing unit (CPU), an application processor (AP), or a system-on-chip (SoC)).

The memory device150may include a memory cell array151, a control logic152, a row decoder153, a column decoder154, a sense amplifier155, and an input/output circuit156.

The memory cell array151may include a plurality of memory cells. The plurality of memory cells may be connected to the row decoder153and the sense amplifier155through a plurality of word lines WL and a plurality of bit lines BL. The plurality of memory cells may be positioned, respectively, at points where the plurality of word lines WL and the plurality of bit lines BL intersect each other. The plurality of memory cells may be arranged in a matrix form in the memory cell array210, and each of the plurality of memory cells may include at least one memory element for storing data.

In the case that the memory device150is the DRAM, each of the plurality of memory cells MC may include a switch element SW and a cell capacitor CC, as illustrated inFIG.4. Data may be written to the memory cell MC by charging or discharging electric charges in or from the cell capacitor CC by the sense amplifier155.

The control logic152may receive the address signal ADDR and the command signal CMD from the host. The address signal ADDR may include a row address indicating a row in the memory cell array210and a column address indicating a column in the memory cell array210. As an example, the row decoder153may select at least one of the plurality of word lines WL with reference to the row address, and the column decoder154may select at least one of the plurality of bit lines BL by referring to the column address.

The sense amplifier155may include a plurality of bit line sense amplifiers connected to the memory cell array151through the plurality of bit lines. A bit line sense amplifier connected to a selected bit line selected by the column decoder154among the plurality of bit line sense amplifiers may read data from at least one of memory cells connected to the selected bit line. The input/output circuit156may output the data read by the bit line sense amplifier as the data signal DQ.

FIG.5is a schematic block diagram illustrating a memory system according to an example embodiment.

Referring toFIG.5, a memory system SYS according to an example embodiment may include a host200and a memory device300.

The host200may generate first to fourth clock signals CK0to CK3and output the first to fourth clock signals CK0to CK3to the memory device300.

The memory device300may operate in synchronization with the first to fourth clock signals CK0to CK3. As an example, using the first to fourth clock signals CK0to CK3, the memory device300may generate a system clock signal that is used for an operation. In an example embodiment, the memory device300may generate the system clock signal using a pair of the clock signals, e.g., the first and third clock signals CK0and CK2, having opposite phases, i.e., a phase difference of 180° therebetween.

The host200may include a plurality of transmitters TX0to TX3outputting the first to fourth clock signals CK0to CK3. In the host200, output terminals of the plurality of transmitters TX0to TX3may be connected to a plurality of clock pads201to204, respectively.

In the host200, first to fourth clock delay cells211to214may be connected to input terminals of the plurality of transmitters TX0to TX3, respectively. A controller220of the host200may control each of the first to fourth clock delay cells211to214to adjust a phase of each of the first to fourth clock signals CK0to CK3.

The first to fourth clock delay cells211to214and the plurality of transmitters TX0to TX3may provide clock output circuits of the host200.

The host200may include a data pad205in addition to first to fourth clock pads201to204. The data pad205may be connected to an output terminal of a transmitter TX (for outputting a data signal DQ to the memory device300) and an input terminal of a receiver RX (for receiving a data signal DQ from the memory device300). The transmitter TX and the receiver RX may provide a data transmission/reception circuit transmitting and receiving data in the host200.

The input terminal of the transmitter TX may be connected to a data delay cell215, and the controller220may control the data delay cell215to adjust a phase of the data signal DQ output to the data pad205.

In an example embodiment, the first to fourth clock delay cells211to214and the data delay cell215may include a phase lock circuit.

The host200may include a plurality of data pads205. Each of the plurality of data pads205included in the host200may be connected to one data transmission/reception circuit. A respective data delay cell215may be connected to each of the plurality of data pads205. Accordingly, the controller220may independently adjust phases of the data signals DQ output through each of the plurality of data pads205.

The memory device300may include first to fourth clock pads301to304connected respectively to the first to fourth clock pads201to204of the host200. The first to fourth clock pads301to304may be connected to input terminals of the first to fourth receivers RX0to RX3receiving the first to fourth clock signals CK0to CK3, respectively.

The memory device300may include a data pad305for connection to the data pad205of the host200. The data pad305may be connected to a plurality of transmitters TX and a plurality of receivers RX. As an example, the plurality of transmitters TX may be paired with the plurality of receivers RX, respectively, to provide a plurality of data transmission/reception circuits311to314, and may be connected to the data pad305.

Each of the plurality of data transmission/reception circuits311to314may include a sampling circuit connected to an output terminal of the receiver RX. The sampling circuit may operate in synchronization with one of the first to fourth clock signals CK0to CK3.

For example, a first sampling circuit included in a first data transmission/reception circuit311may sample an output of the receiver RX at a rising edge of the first clock signal CK0, a second sampling circuit included in a second data transmission/reception circuit312may sample an output of the receiver RX at a rising edge of the second clock signal CK1, a third sampling circuit included in a third data transmission/reception circuit313may sample an output of the receiver RX at a rising edge of the third clock signal CK2, and a fourth sampling circuit included in a fourth data transmission/reception circuit314may sample an output of the receiver RX at a rising edge of the fourth clock signal CK3.

The second clock signal CK1, the third clock signal CK2, and the fourth clock signal CK3may have phase differences of 90°, 180°, and 270°, respectively, with respect to the first clock signal CK0. Accordingly, data transmitted as the data signal DQ may be sequentially sampled by the first to fourth sampling circuits.

Under some conditions, it is possible that a phase skew may exist between the first to fourth clock signals CK0to CK3input to the first to fourth sampling circuits of the memory device300and the data signal DQ, which may result in a difference between effective time periods during which the data signal DQ may be sampled in at least some of the first to fourth sampling circuits. In such a case, the data signal DQ may not be accurately sampled in at least one of the first to fourth sampling circuits.

With reference to the above, in an example embodiment, the host200may execute a training operation for adjusting phases of the first to fourth clock signals CK0to CK3and the data signal DQ, so that the memory device300may accurately receive the data signal DQ transmitted from the host200.

As an example, the host200may compare the first clock signal CK0and the data signal DQ with each other, and adjust delay amounts of the first clock delay cell211and/or the data delay cell215so that a phase skew between the first clock signal CK0and the data signal DQ is minimized and the rising edge of the first clock signal CK0is aligned with the center of an eye opening of the data signal DQ. Thereafter, the host200may adjust a delay amount of each of the second to fourth clock delay cells212to214to adjust a phase of each of the second to fourth clock signals CK1to CK3based on the first clock signal CK0or the data signal DQ.

The host200may also adjust, e.g., increase or decrease, a magnitude of a reference voltage input to the receivers RX receiving the data signal DQ in the memory device300in the training operation.

In addition, in an example embodiment, the host200may control a delay amount of each of the second to fourth clock delay cells212to214to adjust a phase of each of the second to fourth clock signals CK1to CK3based on the first clock signal CK0, on which the delay amount of the first delay cell211is applied. Accordingly, the phase skew between the first to fourth clock signals CK0to CK3may be removed. Thereafter, the host200may adjust a delay amount of the data delay cell215so that the rising edge of each of the first to fourth clock signals CK0to CK3is aligned with the eye opening of the data signal DQ.

As described above, in the memory system SYS according to an example embodiment, the host200may adjust the phase of each of the data signal DQ and the first to fourth clock signals CK0to CK3, and then output the data signal DQ and the first to fourth clock signals CK0to CK3so that the data signal DQ and the first to fourth clock signals CK0to CK3are accurately aligned with each other in the sampling circuits receiving the data signal DQ in the memory device300. In this regard, the phase skew between the data signal DQ and the first to fourth clock signals CK0to CK3may need to be minimized in the sampling circuits of the memory device300, rather than in transmission paths between the host200and the memory device300. Accordingly, in the memory system SYS, at least some of the data signal DQ output from the host310and the first to fourth clock signals CK0to CK3may be misaligned with each other in the transmission path between the host200and the memory device300.

In an example embodiment, the training operation may be executed in a booting operation in which the host200and the memory device300are connected to start an operation. As an example, the host200may execute a training operation on frequencies that the first to fourth clock signals CK0to CK3and the data signal DQ may have at the time of performing booting. In this case, when the frequencies of the first to fourth clock signals CK0to CK3and/or the data signal DQ are changed, settings of the first to fourth clock delay cells211to214and the data delay cell215determined in the training operation executed at the time of performing the booting may be invoked and applied. In another implementation, the host200may perform the training operation whenever the frequency of at least one of the first to fourth clock signals CK0to CK3and the data signal DQ transmitted to the memory device300is changed. This will be described in additional detail below.

FIG.6is a schematic block diagram illustrating a memory device according to an example embodiment.

Referring toFIG.6, a memory device400according to an example embodiment may include a plurality of pads401to405, a plurality of receivers RX0to RX3, and a plurality of sampling circuits411to414.

The plurality of pads401to405may be connected to pads of an external host through signal transmission paths. The plurality of pads401to405may include first to fourth clock pads401to404receiving first to fourth clock signals CK0to CK3and a data pad405receiving a data signal DQ.

Each of the plurality of sampling circuits411to414may include a receiver comparing the data signal DQ with a reference voltage VREF, and a flip-flop storing an output of the receiver.

First to fourth receivers RX0to RX3may receive the first to fourth clock signals CK0to CK3output from the host through the first to fourth clock pads401to404, respectively. The first to fourth clock signals CK0to CK3received by the first to fourth receivers RX0to RX3may be input to first to fourth sampling circuits411to414, respectively. Accordingly, the first sampling circuit411may operate in synchronization with the first clock signal CK0, the second sampling circuit412may operate in synchronization with the second clock signal CK1, the third sampling circuit413may operate in synchronization with the third clock signal CK2, and the fourth sampling circuit414may operate in synchronization with the fourth clock signal CK3.

In a training operation of aligning phases of the first to fourth clock signals CK0to CK3and the data signal DQ with each other, the memory device400may receive the data signal DQ including sample data, which is generated by the host for training.

The data signal DQ transferred through the data pad405may be simultaneously input to the first to fourth sampling circuits411to414. Since the first to fourth clock signals CK0to CK3determine operation timings of the first to fourth sampling circuits411to414and have respectively different phases, the first to fourth sampling circuits411to414may sample data included in the data signal DQ at different timings.

In an example embodiment, each of the first to fourth sampling circuits411to414may sample data included in the data signal DQ by comparing the data signal DQ at a rising edge of each of the first to fourth clock signals CK0to CK3with the reference voltage VREF.

In an example embodiment, the data signal DQ may include first to fourth data DOUT0to DOUT3, which are sequentially received at the data pad405. The first sampling circuit411may sample the first data DOUT0at the rising edge of the first clock signal CK0, and the second sampling circuit412may sample the second data DOUT1at the rising edge of the second clock signal CL1having a phase difference of 90° with respect to the first clock signal CK0. The second sampling circuit412may not sample the first data DOUT0.

Similarly, the third sampling circuit413may sample the third data DOUT2at the rising edge of the third clock signal CK2having a phase difference of 180° with respect to the first clock signal CK0. Since the rising edge of the third clock signal CK2does not appear while the first data DOUT0and the second data DOUT1are input to the third sampling circuit413, the third sampling circuit413may not sample the first data DOUT0and the second data DOUT1.

Similarly, the fourth sampling circuit414may sample the fourth data DOUT3at the rising edge of the fourth clock signal CK3having a phase difference of 270° with respect to the first clock signal CK0.

Accordingly, during a time corresponding to one cycle of each of the first to fourth clock signals CK0to CK3, the data signal DQ received by the memory device400from the host may include four pieces of data, i.e., the first to fourth data DOUT0to DOUT3.

The memory device400may convert the first to fourth data DOUT0to DOUT3sampled by the first to fourth sampling circuits411to414into the data signal DQ, and transmit the data signal DQ to the host through the data pad405. The memory device400may write the first to fourth data DOUT0to DOUT3to a memory cell array and read the first to fourth data DOUT0to DOUT3again to generate the data signal DQ. Alternatively, in an example embodiment, the memory device400may write the first to fourth data DOUT0to DOUT3to a separate register other than the memory cell array, generate the data signal DQ, and then transmit the data signal DQ to the host through the data pad405.

The host receiving the data signal DQ including the first to fourth data DOUT0to DOUT3may compare the first to fourth data DOUT0to DOUT3with the sample data transmitted to the memory device400, and execute a training operation of adjusting phases of the first to fourth clock signals CK0to CK3and the data signal DQ. For example, the host may adjust a magnitude of the reference voltage VREFinput to each of the first to fourth sampling circuits411to414of the memory device400during the training operation.

The training operation may be continued until the rising edge of each of the first to fourth clock signals CK0to CK3is positioned at the center of an eye opening of the data signal DQ in each of the first to fourth sampling circuits411to414.

FIG.7is a waveform diagram provided in order to describe a training operation of a host connected to a memory device according to an example embodiment.

Referring toFIG.7, a data signal DQ and first to fourth clock signals CK0to CK3transmitted from the host to the memory device are illustrated. As an example, the data signal DQ and the first to fourth clock signals CK0to CK3illustrated inFIG.7may be signals input to sampling circuits included in the memory device.

The first to fourth clock signals CK0to CK3may have different phases. As an example, the second to fourth clock signals CK1to CK3may have phase differences of 90°, 180°, and 270° with respect to the first clock signal CK0, respectively. The first to fourth clock signals CK0to CK3may have the same frequency.

A frequency of the data signal DQ may be different from the frequency of each of the first to fourth clock signals CK0to CK3. As an example, the frequency of the data signal DQ may be twice the frequency of each of the first to fourth clock signals CK0to CK3.

The host may position a rising edge of each of the first to fourth clock signals CK0to CK3at the center of an eye opening EO of the data signal DQ by executing the training operation.

As an example, during the training operation, the host may adjust phases of the data signal DQ and at least one of the first to fourth clock signals CK0to CK3transmitted to the memory device. In addition, during the training operation, the host may adjust a magnitude of the reference voltage VREFinput to the sampling circuits in the memory device.

FIG.8is a flowchart provided in order to describe an operation of a memory system according to an example embodiment.

Referring toFIG.8, a memory system according to an example embodiment may include a host50and a memory device60. The host50may transmit a plurality of clock signals to the memory device60, and the memory device60may operate using the plurality of clock signals. As an example, the host50may transmit four clock signals having different phases to the memory device60.

When the memory system including the host50and the memory device60is booted, the host50may start a training operation (S10). Alternatively, when an operating frequency of the memory device60is changed, the host50may start a training operation. The training operation may be an operation of adjusting phases of clock signals and a data signal transmitted from the host50to the memory device60. The data signal and the clock signals may be accurately aligned with each other sampling circuits or the like sampling the data signal in the memory device60by the training operation.

When the training operation starts, the host50may generate sample data (S11). As an example, the sample data may be any data generated by the host50for the training operation. The host50may transmit the data signal including the sample data to the memory device60together with the clock signals (S12).

The memory device60may sample the data signal received from the host50(S13). As described above with reference toFIG.6, the memory device60may sequentially sample the sample data included in the data signal in four sampling circuits, and the four sampling circuits may operate in synchronization with respective ones of the four clock signals received from the host50. The memory device60may store the sampled data in a register (S14). However, according to example embodiments, the sampled data may be stored in a memory cell array of the memory device60rather than the register.

The memory device60may generate a data signal including the data stored in the register and transmit the data signal to the host50(S15). As an example, the memory device60may generate a data signal including the data stored in the register in response to a data transmission request from the host50, and transmit the data signal to the host50.

The host50may compare the data included in the data signal received from the memory device60with sample data, and adjust the phases of the data signal and the clock signals based on a comparison result (S16). As an example, the host50may adjust phases of a first clock signal of the clock signals and the data signal, and then adjust phases of the second to fourth clock signals based on the first clock signal or the data signal. In addition, in an example embodiment, the host50may adjust the phases of the second to fourth clock signals based on the first clock signal, adjust the phase of the data signal, and align the data signal and the first to fourth clock signals with each other. According to example embodiments, the host50may adjust a magnitude of a reference voltage input to the sampling circuits of the memory device60together with the phases of the data signal and the clock signals.

FIG.9is a flowchart provided in order to describe an operation of a memory system according to an example embodiment.

Referring toFIG.9, an operation of the memory system according to an example embodiment may start with outputting the data signal and the first to fourth clock signals to the memory device by the host (S20). The second to fourth clock signals may have respective phase differences of 90°, 180°, and 270° with respect to the first clock signal.

The host may start a training operation of adjusting phases of the data signal and the first to fourth clock signals output to the memory device to align rising edges of the first to fourth clock signals with the center of an eye opening of the data signal (S21). As an example, the training operation may be an operation of aligning the eye opening of the data signal and the rising edges of the first to fourth clock signals with each other in each of circuits inside the memory device, for example, sampling circuits that sample data included in the data signal.

In the example embodiment illustrated inFIG.9, the host may first adjust the phase of each of the first to fourth clock signals (S22). As an example, the host may select one of the first to fourth clock signals as a reference clock and adjust phase differences between the reference clock and other clock signals. When the first clock signal is selected as the reference clock, the host may adjust delay amounts of delay cells connected to transmitters outputting the second to fourth clock signals so that the second to fourth clock signals have phase differences of 90°, 180°, and 270° with respect to the first clock signal, respectively.

When the phase of each of the first to fourth clock signals is adjusted, the host may adjust the phase of the data signal based on the first to fourth clock signals (S23). While the first to fourth clock signals (for which the adjustment of the phases in S22is completed) are input to the sampling circuits of the memory device, the host may change the phase of the data signal (which includes the sample data) and transmit the data signal to the memory device, and may receive a data signal transmitted by the memory device after the memory device samples the data signal. The host may compare data included in the data signal received from the memory device with sample data transmitted earlier, in order to determine whether or not the received data coincides with the sample data.

As an example, the host may receive the data signal from the memory device while retarding or advancing the phase of the data signal, and may determine whether or not data included in the received data signal coincides with the sample data. In such a manner, the host may determine the eye opening of the data signal received by the memory device, and determine the phase of the data signal so that the rising edges of the first to fourth clock signals may be stably positioned within the eye opening.

FIGS.10to12are waveform diagrams provided in order to describe an operation of a semiconductor device according to an example embodiment.

First,FIG.10is a waveform diagram illustrating a data signal DQ and first to fourth clock signals CK0to CK3received by the memory device from the host before a training operation.

Before the training operation, as illustrated inFIG.10, phases of the data signal DQ and the first to fourth clock signals CK0to CK3received by the memory device may not be accurately aligned with each other. As an example, a rising edge of the first clock signal CK0may not be positioned at the center of an eye opening of the data signal DQ.

When the training operation starts, the host may first adjust the phase of each of the first to fourth clock signals CK0to CK3, as illustrated inFIG.11. In an example embodiment illustrated inFIG.11, the host may adjust the phases of the second to fourth clock signals CK1to CK3based on the first clock signal CK0. In an ideal case, phase differences of the second to fourth clock signals CK1to CK3with respect to the first clock signal CK0may be 90°, 180°, and 270°, respectively.

Referring toFIG.11, the host may determine a delay amount of the second clock delay cell determining the phase of the second clock signal CK1as a second delay amount ΔD1so that that a phase difference between the first clock signal CK0and the second clock signal CK1is 90°. In addition, referring toFIG.11, the host may determine a delay amount of the fourth clock delay cell determining the phase of the fourth clock signal CK3as a fourth delay amount ΔD3so that that the fourth clock signal CK3has a phase difference of 270° with respect to the first clock signal CK0. Through the operations described above, the phases of the first to fourth clock signals CK0to CK3may be aligned with each other within the memory device.

Next, referring toFIG.12, the host may adjust the phase of the data signal DQ so that rising edges of the first to fourth clock signals CK0to CK3are aligned with the center of the eye opening of the data signal DQ or to be as close to the center of the eye opening of the data signal DQ as possible. In an example embodiment illustrated inFIG.12, the host may advance the phase of the data signal DQ to align the center of the eye opening of the data signal DQ and the rising edges of the first to fourth clock signals CK0to CK3with each other. Accordingly, after the training operation, a phase difference between the data signal DQ and each of the first to fourth clock signals CK0to CK3as well as the phase differences between the first to fourth clock signals CK0to CK3may be adjusted.

The data signal DQ and the first to fourth clock signals CK0to CK3of which the phases are adjusted as illustrated inFIG.12may be signals received by the memory device, and may be, for example, signals at receiving ends of the sampling circuits that sample the data signal DQ. It is possible that lengths of transmission paths from the pads receiving the data signal DQ and the first to fourth clock signals CK0to CK3to the receiving ends of the sampling circuits may be different from each other. Accordingly, in the pads of the memory device, the phases of the data signal DQ and the first to fourth clock signals CK0to CK3may appear different from phases illustrated inFIG.12. As an example, the data signal DQ and the first to fourth clock signals CK0to CK3may be misaligned with each other in the pads of the memory device after the training operation.

FIGS.13to15are waveform diagrams provided in order to describe an operation of a semiconductor device according to an example embodiment.

First,FIG.13is a waveform diagram illustrating a data signal DQ and first to fourth clock signals CK0to CK3received by the memory device from the host before a training operation.

As described above, before the training operation, phases of the data signal DQ and the first to fourth clock signals CK0to CK3received by the memory device may not be accurately aligned with each other. In an example embodiment illustrated inFIG.13, a rising edge of each of the first to third clock signals CK0to CK2may be offset from the center of an eye opening of the data signal DQ.

In the training operation, the host may first adjust the phase of each of the first to fourth clock signals CK0to CK3as illustrated inFIG.14. Referring toFIG.14, the host may determine a delay amount of the second clock delay cell determining the phase of the second clock signal CK1as a second delay amount ΔD1so that that a phase difference between the first clock signal CK0and the second clock signal CK1is 90°. In addition, the host may determine a delay amount of the third clock delay cell determining the phase of the third clock signal CK2as a third delay amount ΔD2so that that a phase difference between the first clock signal CK0and the third clock signal CK2is 180°. In addition, the host may determine a delay amount of the fourth clock delay cell determining the phase of the fourth clock signal CK3as a fourth delay amount ΔD3so that that the fourth clock signal CK3has a phase difference of 270° with respect to the first clock signal CK0.

When the phase differences between the first to fourth clock signals CK0to CK3are adjusted, the host may adjust the phase of the data signal DQ. Referring toFIG.15, the host may align the rising edges of the first to fourth clock signals CK0to CK3and the center of the eye opening of the data signal DQ with each other by retarding the phase of the data signal DQ. Similar to that described above, the data signal DQ and the first to fourth clock signals CK0to CK3of which the phases are adjusted as illustrated inFIG.15may be signals received by the memory device, for example, signals at receiving ends of the sampling circuits sampling the data signal DQ and outputting the data included in the data signal.

FIG.16is a flowchart provided in order to describe an operation of a memory system according to an example embodiment.

Referring toFIG.16, an operation of the memory system according to an example embodiment may start with outputting the data signal and the first to fourth clock signals to the memory device by the host (S30). Each of the second to fourth clock signals may have a phase difference of 90°, 180°, and 270° with respect to the first clock signal.

The host may start a training operation of adjusting phases of the data signal and the first to fourth clock signals output to the memory device to align rising edges of the first to fourth clock signals with the center of an eye opening of the data signal (S31). In an example embodiment illustrated inFIG.16, the host may first adjust the phases of one of the first to fourth clock signals and the data signal (S32). As an example, the host may adjust the phases of the data signal and the first clock signal to align the rising edge of the first clock signal with the center of the eye opening of the data signal.

When the phases of the data signal and the first clock signal are aligned with each other, the host may adjust the phase of each of the second to fourth clock signals based on the first clock signal (S33). The host may adjust delay amounts of clock delay cells connected to transmitters outputting the second to fourth clock signals so that the second to fourth clock signals have phase difference of 90°, 180°, and 270° with respect to the first clock signal, respectively.

FIGS.17to21are waveform diagrams provided in order to describe an operation of a semiconductor device according to an example embodiment.

FIG.17is a waveform diagram illustrating a data signal DQ and first to fourth clock signals CK0to CK3received by the memory device from the host before a training operation. Before the training operation, as illustrated inFIG.17, phases of the data signal DQ and the first to fourth clock signals CK0to CK3received by the memory device may not be accurately aligned with each other.

When the training operation starts, the host may adjust the phases of one of the first to fourth clock signals CK0to CK3and the data signal DQ. In the example embodiment illustrated inFIG.18, the phase of the data signal DQ may be adjusted based on the first clock signal CK0. Accordingly, the host may change a delay amount of the data delay cell connected to the transmitter outputting the data signal DQ. Referring toFIG.18, the host may align a rising edge of the first clock signal CK0with the center of the eye opening of the data signal DQ by advancing the phase of the data signal DQ.

Next, the host may adjust the phase of each of the second to fourth clock signals CK1to CK3based on the data signal DQ or the first clock signal CK0. First, referring toFIG.19, the host may adjust the phase of the second clock signal CK1based on the first clock signal CK0or the data signal DQ. For example, the host may adjust the phase of the second clock signal CK1so that the second clock signal has a phase difference of 90° with respect to the first clock signal CK0. In addition, in an example embodiment, the host may adjust the phase of the second clock signal CK1so that a rising edge of the second clock signal CK1is positioned at the center of the eye opening of the data signal DQ.

Next, referring toFIGS.20and21, the host may adjust the phase of each of the third clock signal CK2and the fourth clock signal CK3based on the data signal DQ or the first clock signal CK0. As described with reference toFIG.19, the host may adjust delay amounts of delay cells connected to transmitters outputting the third clock signal CK2and the fourth clock signal CK3so that the third clock signal CK2and the fourth clock signal CK3have phase differences of 180° and 270° with respect to the first clock signal CK0, respectively. Alternatively, for the third clock signal CK2and the fourth clock signal CK3, the host may adjust delay amounts of delay cells connected to transmitters outputting the third clock signal CK2and the fourth clock signal CK3so that a rising edge of each of the third clock signal CK2and the fourth clock signal CK3is positioned at the center of the eye opening of the data signal DQ.

In the example embodiment described with reference toFIGS.19to21, the phases of the second to fourth clock signals CK1to CK3may be simultaneously adjusted. In addition, when the training operation is executed in a manner of aligning the rising edge of each of the second to fourth clock signals CK1to CK3with the center of the eye opening of the data signal DQ, the phase differences between the first clock signal CK0and the second to fourth clock signals CK1to CK3after the training operation ends may not be 90°, 180°, and 270°, respectively.

In various example embodiments, the data signal DQ may be a multi-level signal capable of transmitting two or more bits of data at a time. When the data signal DQ is a multi-level signal capable of transmitting two bits of data at a time, the data signal DQ may have one of four levels, and each of the sampling circuits of the memory device may compare the data signal DQ with three different reference voltages. Accordingly, in the training operation of aligning the phases of the clock signals and the data signal DQ with each other, described above, the host may adjust magnitudes of the three reference voltages for sampling the data signal DQ together.

FIG.22is a schematic block diagram illustrating a memory system according to an example embodiment.

A memory system500according to an example embodiment illustrated inFIG.22may be a solid state drive (SSD). The memory system500may have a form factor according to an M.2 standard, and may communicate with an external central processing unit, a system-on-chip, an application processor, or the like, according to a peripheral component interconnect express (PCIe) protocol.

The memory system500may include a power management integrated circuit (PMIC)510, a controller520, a NAND memory530, a DRAM540, and the like. The PMIC510, the controller520, the NAND memory530, the DRAM540, and the like, may be mounted on a system board550, and connector pins560and component elements570may be disposed on the system board550. The connector pins560may be in contact with pins of a computer device and/or a server device in which the memory system500is mounted. The component elements570may include passive elements such as resistors and capacitors required for an operation of the memory system500.

The controller520may control the memory system500according to a control command from the computer device and/or the server device. The controller520may store data received through the connector pins560in the NAND memory530and/or the DRAM540or may read data stored in the NAND memory530and/or the DRAM540and output the read data to the computer device and/or the server device. The PMIC510may distribute power supplied to the connector pins560to the controller520, the NAND memory530, the DRAM540, and the like.

The controller520may be connected to the NAND memory530and the DRAM540through wirings formed on the system board550. As an example, the controller520may provide a plurality of clock signals required for operations of the NAND memory530and/or the DRAM540, and may exchange a data signal with the NAND memory530and the DRAM540. In an example embodiment, the controller520may execute a training operation of adjusting phases of clock signals and a data signal so that the phases of the clock signals and the data signal are aligned with each other within the NAND memory530and/or the DRAM540. As an example, the controller520may execute the training operation when the memory system500is initially booted or when an operating frequency of the NAND memory530and/or the DRAM540is changed.

By way of summation and review, in order to improve a communication rate between a memory device and a controller, a plurality of clock signals having different phases may be used as strobe signals.

Example embodiments may provide a semiconductor device capable of increasing a data transfer rate and reliability of data transfer by aligning the clock signals and a data signal with each other through training. According to example embodiments, phases of four clock signals and data signal may be aligned with each other in a semiconductor device communicating with a memory device, so that a phase skew between the four clock signals received by the memory device is removed and phase errors between the four clock signals and the data signal are minimized in the memory device.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.