Patent ID: 12222797

Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

DETAILED DESCRIPTION

The present disclosure is generally directed to dynamic configuration of processor sub-components for power efficiency. Physical considerations can limit a processor's performance. As the additional processor components operate, the components can contribute to the processor's power consumption. Power consumption and the associated heat generation can adversely affect a processor's performance. Various techniques can address power consumption via software-based conditions that can trigger throttling a processor or components thereof. Such techniques are often abstracted from the processor hardware such that the throttling can take hundreds to thousands of cycles to respond to triggers. Such techniques can also be restricted in a granularity of observing and analyzing the processor. As will be explained in greater detail below, implementations of the present disclosure can implement a control circuit coupled to and in physical proximity of a functional unit of a processor and/or a sub-component thereof. The control circuit can observe whether a utilization of the functional unit and/or sub-component is outside of a desired utilization range and throttle portions of the processor as needed. By using a control circuit in such an arrangement, the systems and methods described herein can advantageously improve power efficiency and heat generation at a granular level with relatively low latency.

As will be described in greater detail below, the instant disclosure describes various systems and methods for dynamically configuring processor sub-components for improved power efficiency. The systems and methods described herein observe how a functional unit is utilized and throttle the functional unit if its utilization is outside a desired utilization range.

In one example, a device for dynamic configuration of processor sub-components includes a functional unit of a processor comprising at least one sub-component including a target sub-component and a control circuit coupled to the target sub-component. The control circuit is configured to observe a utilization of the target sub-component and detect that the utilization is outside a desired utilization range. The controller is also configured to throttle, in response to the detection, at least one sub-component of the functional unit to reduce a power consumption of the functional unit.

In some examples, the control circuit is further configured to observe a workload that is input into the target sub-component. In some examples, the at least one sub-component of the functional unit is selected for throttling based on reducing the workload that is input into the target sub-component. In some examples, the at least one sub-component of the functional unit is selected for throttling based on a workload type of the workload. In some examples, the workload corresponds to a minimal workload and the at least one sub-component corresponds to the target sub-component.

In some examples, throttling the at least one sub-component includes putting the at least one sub-component into a low-power state. In some examples, throttling the at least one sub-component includes throttling the functional unit.

In some examples, the control circuit is further configured to detect that the utilization is within the desired utilization range and dethrottle the at least one sub-component in response to detecting that the utilization is within the desired utilization range.

In some examples, the target sub-component corresponds to a micro-operation queue for storing predecoded instructions, and the functional unit further includes at least a first sub-component and a second sub-component each providing predecoded instructions to the micro-operation queue. In addition, the at least one sub-component corresponds to at least one of the first and second sub-components.

In some examples, the functional unit corresponds to at least one of an arithmetic logic unit (ALU), a floating-point unit (FPU), or a load-store unit (LSU). In some examples, the processor corresponds to a multi-core processor and the functional unit corresponds to a core of the multi-core processor.

In some examples, the device further includes a second functional unit of the processor comprising a second target sub-component, a second control circuit coupled to the second target sub-component, and a higher-level control circuit coupled to the control circuit and the second control circuit. The higher-level control circuit is configured to detect the throttling of the at least one sub-component of the functional unit and coordinate throttling of sub-components by the control circuit and the second control circuit.

In one example, a method for dynamic configuration of processor sub-components includes observing, using a control circuit coupled to a target sub-component of a functional unit of a processor, a utilization of the target sub-component based on a workload that is input into the target sub-component and detecting that the utilization is outside a desired utilization range for the workload. The method further includes throttling at least one sub-component of the functional unit to reduce a power consumption of the functional unit.

In some examples, the at least one sub-component of the functional unit is selected for throttling based on reducing the workload that is input into the target sub-component. In some examples, the workload corresponds to a minimal workload and the at least one sub-component corresponds to the target sub-component.

In some examples, the target sub-component corresponds to a micro-operation queue for storing predecoded instructions. The functional unit further includes at least a first sub-component and a second sub-component each providing predecoded instructions to the micro-operation queue. The at least one sub-component corresponds to at least one of the first and second sub-components.

In some examples, the method further includes detecting, using a higher-level control circuit coupled to the control circuit, the throttling of the at least one sub-component of the functional unit. The higher-level control circuit is further coupled to a second control circuit that is coupled to a second target sub-component of a second functional unit of the processor. The method also includes coordinating, using the higher-level control circuit, throttling of sub-components by the control circuit and the second control circuit.

In one implementation, a system for dynamic configuration of processor sub-components includes a physical memory and at least one physical processor including a functional unit and a control circuit. The functional unit includes at least one sub-component that has a target sub-component. The control circuit is coupled to the target sub-component and configured to observe a workload and a utilization of the target sub-component and detect that the utilization is outside a desired utilization range for the workload. The control circuit is also configured to throttle at least one sub-component of the functional unit to reduce a power consumption of the physical processor.

In some examples, the at least one sub-component of the functional unit is selected for throttling based on reducing the workload that is input into the target sub-component. In some examples, the target sub-component corresponds to a micro-operation queue for storing predecoded instructions, the functional unit further includes at least a first sub-component and a second sub-component each providing predecoded instructions to the micro-operation queue, and the at least one sub-component corresponds to at least one of the first and second sub-components.

Features from any of the implementations described herein can be used in combination with one another in accordance with the general principles described herein. These and other implementations, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and claims.

The following will provide, with reference toFIGS.1-5, detailed descriptions of systems and methods for dynamic configuration of processor sub-components. Detailed descriptions of various example processors having control circuits for dynamic configuration of sub-components will be provided in connection withFIGS.1-3. Detailed descriptions of an example dual pipeline for a micro-op cache will be provided in connection withFIG.4. In addition, detailed descriptions of corresponding methods will also be provided in connection withFIG.5.

FIG.1is a block diagram of an example system100for dynamic configuration of processor sub-components for power efficiency. System100corresponds to a computing device, such as a desktop computer, a laptop computer, a server, a tablet device, a mobile device, a smartphone, a wearable device, an augmented reality device, a virtual reality device, a network device, and/or an electronic device. As illustrated inFIG.1, system100includes one or more memory devices, such as memory105. Memory105generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and/or computer-readable instructions. Examples of memory105include, without limitation, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, Hard Disk Drives (HDDs), Solid-State Drives (SSDs), optical disk drives, caches, variations or combinations of one or more of the same, and/or any other suitable storage memory.

As illustrated inFIG.1, example system100includes one or more physical processors, such as processor110. Processor110generally represents any type or form of hardware-implemented processing unit capable of interpreting and/or executing computer-readable instructions. In some examples, processor110accesses and/or modifies data and/or instructions stored in memory105. Examples of processor110include, without limitation, microprocessors, microcontrollers, Central Processing Units (CPUs), graphics processing units (GPUs), Field-Programmable Gate Arrays (FPGAs) that implement softcore processors, Application-Specific Integrated Circuits (ASICs), systems on chip (SoCs), portions of one or more of the same, variations or combinations of one or more of the same, and/or any other suitable physical processor.

In some implementations, the term “instruction” refers to computer code that can be read and executed by a processor. Examples of instructions include, without limitation, macro-instructions (e.g., program code that requires a processor to decode into processor instructions that the processor can directly execute) and micro-operations (e.g., low-level processor instructions that are decoded from a macro-instruction and that form parts of the macro-instruction).

As further illustrated inFIG.1, processor110includes a control circuit120and a functional unit130. Control circuit120includes circuitry and/or instructions for dynamic configuration of a processor sub-component, such as functional unit130. Functional unit130corresponds to any component and/or sub-component of processor110, as described further herein. Functional unit130corresponds to an execution unit, such as an arithmetic logic unit (ALU), a floating-point unit (FPU), a load-store unit (LSU), etc., and/or sub-components thereof. In addition, althoughFIG.1illustrates a single control circuit120and a single functional unit130, in other implementations processor110includes multiple different iterations of each, as described further herein.

As processor110operates, processor110powers on and shuts off functional unit130as needed to improve power efficiency and reduce heat generation. For example, as workload needs increase, processor110generally powers on and utilizes functional unit130accordingly. As the workload needs decrease, in particular if functional unit130is not needed, processor110shuts off functional unit130, puts functional unit130into a low-power mode, or otherwise throttles functional unit130. A control scheme determines when to throttle functional unit130. Some control schemes rely on software, such as optimized code that more efficiently utilizes processor110and functional unit130. Other control schemes observe workloads to processor110and predict workload trends to throttle functional unit130. Yet other control schemes observe a performance of processor110to determine when to throttle functional unit130. However, such control schemes for throttling functional unit130can be relatively slow, taking hundreds to thousands of processing cycles to react. For instance, such control schemes can be limited in granularity as to which components are powered on/off such that the powering on/off itself can be a relatively slow process.

Control circuit120resides in the hardware of processor110to provide a control scheme that is more localized to functional unit130than the previously described control schemes. Physical proximity and direct coupling to functional unit130reduces reaction time latency to a scale of tens of cycles. In addition, control circuit120is configured to dynamically configure (e.g., via powering on/off, throttling, etc.) functional unit130and/or one or more sub-components of functional unit130, and further one or more pipelines that lead into functional unit130. In addition, control circuit120is coupled to functional units that enable parallelism in processor110. When control circuit120powers down functional unit130, processor110can still operate on a pipeline that is parallel to functional unit130. Thus, control circuit120provides a level of granularity regarding observation and configuration that may not be achievable with higher level control schemes.

FIG.2illustrates an example processor210, which corresponds to processor110. Processor210includes a functional unit232, which corresponds to functional unit130, a functional unit234, which corresponds to another iteration of functional unit130, and a control circuit226, which corresponds to control circuit120. Functional unit232includes a sub-component233and a control circuit222, which corresponds to control circuit120. Functional unit234includes a sub-component235and a control circuit224, which corresponds to control circuit120.

Control circuit222observes functional unit232during operation. The physical proximity of control circuit222allows a granular level of observation of functional unit232. Control circuit222observes, in some examples, a utilization of sub-component233and dynamically configure sub-component233accordingly. For instance, if the utilization is outside of a desired utilization range, control circuit222can throttle sub-component233and/or functional unit232. The desired utilization range relates to a type of functional unit232and/or sub-component233. For example, if sub-component233corresponds to a queue, the desired utilization range includes an upper limit relating to how full the queue is before having to reject new entries and a lower limit relating to how empty the queue is before the queue's usefulness is reduced.

If the utilization is below the desired utilization range, the under-utilization can indicate that functional unit232is not needed for a current workload type. For example, if the current workload corresponds to integer operations and functional unit232corresponds to an FPU, the current workload does not require the FPU or otherwise provides a minimal workload to the FPU, as indicated by the under-utilization. In response, control circuit222throttles sub-component235and/or functional unit232to reduce power consumption of processor210.

If the utilization is above the desired utilization range, the over-utilization can indicate that functional unit232is not able to perform the current workload. Control circuit222throttles sub-component233to reduce the workload input into functional unit232. For example, sub-component233corresponds to a pipeline that inputs the workload into functional unit232. Control circuit222throttles or shuts off the pipeline to reduce the workload burden on functional unit232. In some examples, control circuit222queues portions of the workload and burst the queued workload once functional unit232returns to the desired utilization.

In other examples, control circuit222takes preventative and/or predictive actions based on detecting trigger actions. For example, control circuit222detects a first stall event in functional unit234and a second stall event, which indicates a high probability of a third stall event. To prevent the third stall event, control circuit222accordingly throttles sub-component233.

When control circuit222detects that the utilization is within the desired utilization range, control circuit222dethrottles sub-component233or otherwise reverses any throttling actions previously performed. Because of the latency available due to physical proximity, control circuit222is able to quickly react to such changes detected in the utilization of sub-component233and/or functional unit232.

In some examples, control circuit224dynamically configures functional unit234and/or sub-component235, similar to control circuit222as described above, and in other examples is tailored based on a type of functional unit234. For instance, control circuit224observes and/or responds to different aspects of a utilization and/or workload of functional unit234and/or sub-component235.

In some implementations, control circuit224coordinates with control circuit222. For example, control circuit226is coupled to control circuit222and control circuit224to facilitate coordination. Control circuit226detects, based on feedback from control circuit222and/or control circuit224, utilization trends for functional unit232and functional unit234. Control circuit226instructs control circuit222and/or control circuit224to be more aggressive in throttling their respective functional units if the utilizations trend outside the desired utilization ranges (e.g., if the utilization is outside the desired utilization range at an increasing rate). Control circuit226instructs control circuit222and/or control circuit224to be less aggressive in throttling their respective functional units if the utilizations trend within the desired utilization ranges (e.g., if the utilization is outside the desired utilization range at a decreasing rate).

Additionally and/or alternatively, control circuit226instructs one of control circuit222and control circuit224to act in response to the other. For instance, if control circuit222throttles sub-component233, control circuit226can instruct control circuit224to also throttle sub-component235. Moreover, control circuit226allows graceful throttling and dethrottling of functional units and sub-components. Powering on multiple functional units simultaneously can cause undesirable power spikes in processor210. Control circuit226coordinates staggered powering on of functional units to prevent such power spikes. Similarly, control circuit226coordinates staggered throttling of functional units to prevent excessive voltage drops in processor210. Thus, control circuit226provides additional information for control circuit222and/or control circuit224for dynamically configuring their respective functional units.

FIG.3illustrates an example multi-core processor310, which corresponds to processor110. Processor310includes a core332, which corresponds to functional unit130, a core334, which can corresponds another iteration of functional unit130, and a control circuit326, which corresponds to control circuit120. Core332includes a control circuit322, which corresponds to control circuit120. Core334includes a control circuit324, which corresponds to control circuit120.

In some examples, the dynamic configuration allows throttling of one or more cores (e.g., core332and/or core334) of a multi-core processor (e.g., processor310). Control circuit322throttles core332and/or sub-components thereof based on observing a utilization of core332and/or a workload of core332as described herein. Similarly, control circuit324throttles core334and/or sub-components thereof based on observing a utilization of core334and/or a workload of core334as described herein. Control circuit326coordinates dynamic configuration between control circuit322and control circuit324as described herein.

The physical proximities of control circuit322to core332and control circuit324to core334advantageously allow relatively low latency in dynamically configuring the respective cores. In addition, the control circuits allow virtualizing a big core into a smaller core (e.g., with respect to power consumption and heat generation) transparently to a software and/or operating system (OS). For example, control circuit322throttles one or more sub-components of core332when a full performance of core332is not needed. Alternatively, control circuit322and/or control circuit326throttles core332itself if core334can sufficiently handle a current workload. In some examples, the software and/or OS can signal or request reduced performance of processor310.

FIG.4illustrates a simplified example dual pipeline400(e.g., a CPU core front-end subsystem) for a micro-op cache430, which corresponds to functional unit130, of a processor such as processor110to a micro-op queue434.FIG.4includes a first pipeline433A from micro-op cache430to micro-op queue434and a second pipeline433B from micro-op cache430to micro-op queue434.FIG.4further includes a control circuit420, which corresponds to control circuit120, a cache415(e.g., an L1 cache or other cache of a processor/core, such as L2, L3, etc.), an address translation431A, an address translation431B, a decoder432A, a decoder432B and a dispatcher436.

An instruction cycle of a processor includes a fetch stage, decode stage, and an execute stage. During the fetch stage, a next instruction, which is encoded, is fetched from a memory. During the decode stage, the instruction is decoded into micro-operations. During the execute stage, the decoded micro-operations are executed.FIG.4illustrates components that are used during the decode stage.

During the decode stage, the processor fetches instructions from cache415for decoding by decoder432A and/or decoder432B. Fetching the instructions for a requested memory address requires translation to fetch from cache415. Each decoder uses a respective address translation unit (e.g., address translation431A for decoder432A and address translation431B for decoder432B). After fetching instructions, the decodes (e.g., decoder432A and/or decoder432B) decodes the instructions. The decoded instructions (e.g., micro-operations) are stored in a micro-op queue, such as micro-op queue434until the processor is ready to execute more micro-operations. A dispatcher such as dispatcher436selects micro-operations from micro-op queue434that are ready to be executed.

In the instruction cycle, particularly the decode stage, the process of decoding instructions can be relatively time consuming. To reduce the time required for decoding instructions, certain instructions can be predecoded and stored in a micro-op cache, such as micro-op cache430. For example, certain instructions that are predicted to be accessed repeatedly are predecoded and stored in micro-op cache430. Micro-op queue434is provided decoded instructions from micro-op cache430(e.g., via first pipeline433A and/or second pipeline433B) rather than directly from decoder432A and/or decoder432B.

In some examples, the processor has a high enough throughput (e.g., a large micro-op cache and/or large micro-op queue) such that micro-op cache430supports receiving instructions from more than one instruction pipeline or workload source.FIG.4illustrates a dual pipeline in which two independent pipelines (e.g., first pipeline433A and second pipeline433B, although in other examples micro-op queue434may be fed data/requests from multiple workload sources such as decoder432A and/or address translation431A and decoder432B and/or address translation431B) access and share micro-op cache430.

However, in some scenarios, micro-op cache430is not used optimally. In some examples, the dual pipelines have caused over-utilization of micro-op queue434. Micro-op queue434does not have enough free entries such that micro-op cache430can throttle its throughput. For instance, micro-op cache430is able to immediately accept read requests from address translation431A (alternatively first pipeline433A) but delay servicing requests from address translation431B (alternatively second pipeline433B). Operating requests from address translation431B under these conditions can unnecessarily consume power.

In some examples, control circuit420is configured to detect and respond to these conditions. Control circuit420is coupled to micro-op cache430and/or micro-op queue434to observe its workload. Control circuit420observes the workload for a period of time, such as 30 cycles. Control circuit420can observe that the utilization of micro-op queue434is above a desired range, which in some examples is based on workload outputs of first pipeline433A and second pipeline433B, and in other examples is additionally or alternatively based on workload outputs from workload sources such as address translation431A, address translation431B, decoder432A, decoder432B, etc. For example, each of decoder432A and decoder432B outputs 6 entries per cycle. Control circuit420can observe (e.g., based on tokens) that a number of free entries during the period of time has remained at a low amount, such as 6-10 free entries, which would not support the output of both pipelines (e.g., 12 entries). During this period of time, micro-op queue434has rejected new entries from decoder432B, causing a stall in second pipeline433B. Because micro-op queue434is not able to support both first pipeline433A and second pipeline433B, control circuit420throttles second pipeline433B to save power. Because second pipeline433B is already stalled, throttling second pipeline433B does not cause a significant reduction in performance or throughput. When control circuit420detects that the utilization is within the desired range (e.g., 12 or more free entries), micro-op queue434can be able to support both first pipeline433A and second pipeline433B. Control circuit420accordingly dethrottles second pipeline433B (e.g., by accepting entries from decoder432B).

FIG.5is a flow diagram of an exemplary computer-implemented method500for dynamically configuring processor sub-components. The steps shown inFIG.5can be performed by any suitable computer-executable code and/or computing system, including the system(s) illustrated inFIGS.1and/or2. In one example, each of the steps shown inFIG.5can represent an algorithm whose structure includes and/or is represented by multiple sub-steps, examples of which will be provided in greater detail below.

As illustrated inFIG.5, at step502one or more of the systems described herein observes, using a control circuit coupled to a target sub-component of a functional unit of a processor, a utilization of the target sub-component. For example, control circuit120observes a utilization of functional unit130and/or a sub-component thereof.

The systems described herein can perform step502in a variety of ways. In one example, control circuit120observes a workload that is input into the target sub-component. In some examples, the target sub-component corresponds to a micro-operation cache (e.g., micro-op cache430) and/or micro-operation queue (e.g., micro-op queue434) for storing predecoded instructions. The functional unit includes at least a first sub-component (e.g., decoder432A, address translation431A, and/or first pipeline433A) and a second sub-component (e.g., decoder432B, address translation431B, and/or second pipeline433B) each providing predecoded instructions and/or requests to the micro-operation cache and/or micro-operation queue. The at least one sub-component corresponds to at least one of the first and second sub-components.

In some examples, control circuit420observes micro-op queue434and its utilization via tokens as available to micro-op cache430(e.g., token levels as described herein), whether micro-op queue434is blocked by downstream stalls, and/or a rate of output/dispatches of micro-op queue434.

In some examples, the functional unit corresponds to at least one of an arithmetic logic unit (ALU), a floating-point unit (FPU), or a load-store unit (LSU). In some examples, the processor corresponds to a multi-core processor and the functional unit corresponds to a core of the multi-core processor (see, e.g.,FIG.4).

At step504one or more of the systems described herein detects that the utilization is outside a desired utilization range. For example, control circuit120detects that the utilization of functional unit130is outside a desired utilization range. The desired utilization range is based on a type of functional unit and/or a type of workload as described herein.

At step506one or more of the systems described herein throttles, in response to the detection, at least one sub-component of the functional unit to reduce a power consumption of the functional unit. For example, control circuit120throttles functional unit130and/or a sub-component thereof.

The systems described herein can perform step506in a variety of ways. In one example, throttling the at least one sub-component includes putting the at least one sub-component into a low-power state. In some examples, throttling the at least one sub-component includes reducing an output rate of the at least one sub-component. In some examples, throttling the at least one sub-component includes throttling the functional unit itself.

In some examples, control circuit120selects a particular sub-component of functional unit130for throttling that is different from the target sub-component (e.g., the sub-component being observed). In some examples, the at least one sub-component of the functional unit is selected for throttling based on reducing the workload that is input into the target sub-component. Control circuit120selects a sub-component from one of multiple pipelines or workload sources for a micro-op cache and/or micro-op queue to reduce a workload that is input into the micro-op cache and/or micro-op queue. For instance, control circuit420selects address translation431B, decoder432B, and/or micro-op cache430(e.g., to throttle one of first pipeline433A and second pipeline433B) to reduce a workload that is input into micro-op queue434. Control circuit420can select a sub-component that is already stalled or can select a sub-component that is causing another sub-component to stall. In other examples, control circuit420selects the target sub-component itself (e.g., micro-op queue434being observed) for throttling.

In some examples, the at least one sub-component of the functional unit is selected for throttling based on a workload type of the workload. For instance, control circuit120selects an integer unit for throttling if the workload corresponds to floating-point operations.

In some examples, the workload corresponds to a minimal workload and the at least one sub-component corresponds to the target sub-component. For instance, control circuit120detects that a current phase of the workload for an FPU does not require floating-point operations and accordingly throttles the FPU.

In some examples, control circuit120also detects that the utilization is within the desired utilization range (e.g., in response to a previous throttling of the at least one sub-component) and dethrottles the at least one sub-component in response to detecting that the utilization is within the desired utilization range. For instance, control circuit120previously shut off the selected sub-component from one of multiple pipelines to a micro-op cache and/or micro-op queue. After detecting the micro-op cache and/or micro-op queue is within the desired utilization range, control circuit120reenables the shut off sub-component to restore the corresponding pipeline to the micro-op cache and/or micro-op queue.

As illustrated inFIG.4, in some examples, the target sub-component corresponds to a micro-operation queue for storing predecoded instructions and the functional unit further includes at least a first sub-component and a second sub-component each providing predecoded instructions and/or entries to the micro-operation queue. The at least one sub-component corresponds to at least one of the first and second sub-components.

In some examples, a higher-level control circuit (e.g., control circuit226) coupled to the control circuit (e.g., control circuit222) detects the throttling of the at least one sub-component (e.g., sub-component233) of the functional unit (e.g., functional unit232). The higher-level control circuit is coupled to a second control circuit (e.g., control circuit224) that is coupled to a second target sub-component (e.g., sub-component235) of a second functional unit (e.g., functional unit234) of the processor. The higher-level control circuit coordinates throttling of sub-components by the control circuit and the second control circuit.

As described herein, the present disclosure provides systems and methods for dynamically configuring processor sub-components. A program can have various phases as it executes, such as integer operations, floating point operations, loops, etc. A control circuit can identify a program phase and which sub-components are needed for executing the program phase. The control circuit can power off or throttle sub-components that are not needed for the identified program phase. Because the control circuit can reside in physical proximity to the sub-components it observes and throttles, the control circuit can respond at a higher granularity and higher frequency than other techniques can allow. For example, the control circuit is able to observe a workload of the sub-components more directly rather than relying on feedback provided by the functional unit.

For example, a sub-component can receive inputs from multiple pipelines. The control circuit can observe a current workload of the sub-component and determine that operating the multiple pipelines does not produce a performance benefit for the current workload. The control circuit can accordingly maintain a single pipeline and shut down the other pipelines (e.g., by shutting down one or more sub-components along the respective pipelines) to reduce power consumption. Thus, the systems and methods described herein can advantageously allow maximum performance for high-throughput workloads using multiple pipelines while minimizing power consumption for low-throughput workloads.

As detailed above, the computing devices and systems described and/or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions, such as those contained within the units or circuits described herein. In their most basic configuration, these computing device(s) each include at least one memory device and at least one physical processor.

In some examples, the term “memory device” generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and/or computer-readable instructions. In one example, a memory device stores, loads, and/or maintains one or more of the units described herein. Examples of memory devices include, without limitation, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, Hard Disk Drives (HDDs), Solid-State Drives (SSDs), optical disk drives, caches, variations or combinations of one or more of the same, or any other suitable storage memory.

In some examples, the term “physical processor” generally refers to any type or form of hardware-implemented processing unit capable of interpreting and/or executing computer-readable instructions. In one example, a physical processor accesses and/or modifies one or more units stored in the above-described memory device. Examples of physical processors include, without limitation, microprocessors, microcontrollers, Central Processing Units (CPUs), Field-Programmable Gate Arrays (FPGAs) that implement softcore processors, Application-Specific Integrated Circuits (ASICs), systems on a chip (SOCs), portions of one or more of the same, variations or combinations of one or more of the same, or any other suitable physical processor.

In some implementations, the term “computer-readable medium” generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, without limitation, transmission-type media, such as carrier waves, and non-transitory-type media, such as magnetic-storage media (e.g., hard disk drives, tape drives, and floppy disks), optical-storage media (e.g., Compact Disks (CDs), Digital Video Disks (DVDs), and BLU-RAY disks), electronic-storage media (e.g., solid-state drives and flash media), and other distribution systems.

The process parameters and sequence of the steps described and/or illustrated herein are given by way of example only and can be varied as desired. For example, while the steps illustrated and/or described herein are shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and/or illustrated herein can also omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.

The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary implementations disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The implementations disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the present disclosure.

Unless otherwise noted, the terms “connected to” and “coupled to” (and their derivatives), as used in the specification and claims, are to be construed as permitting both direct and indirect (i.e., via other elements or components) connection. In addition, the terms “a” or “an,” as used in the specification and claims, are to be construed as meaning “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives), as used in the specification and claims, are interchangeable with and have the same meaning as the word “comprising.”