Patent ID: 12225824

DETAILED DESCRIPTION

As will be described in detail in what follows, according to an aspect of the present solution the microelectromechanical structure has a piezoelectric stack having a variable section, in particular with reference to a variable thickness of the corresponding piezoelectric material region.

The piezoelectric stack is formed on an underlying patterned structure, having an appropriate conformation, which corresponds to the aforesaid variable section of the piezoelectric stack.

As will be highlighted, the effect of the variable section is, in general, that of improving the performance and electrical characteristics of the piezoelectric microelectromechanical structure.

In detail, and with initial reference toFIG.2, a piezoelectric microelectromechanical structure10according to an aspect of the present solution has a main extension in a horizontal plane xy and comprises a piezoelectric stack11formed by stacking on top of one another: a bottom-electrode region12of an appropriate conductive material; a piezoelectric material region14in particular constituted by a thin film of PZT (lead zirconate titanate (Pb/Zr/Ti)) arranged on the aforesaid bottom-electrode region12; and a top-electrode region16of an appropriate conductive material arranged on the piezoelectric material region14.

The aforesaid piezoelectric stack11is arranged on a supporting element18, which is deformable along a vertical axis z orthogonal to the aforesaid horizontal plane xy. The supporting element18, for example of polysilicon, may be a membrane suspended above an underlying opening or cavity30and is separated from the piezoelectric stack11by a dielectric region19, for example, of silicon oxide, interposed between the supporting element18and the bottom-electrode region12.

In particular, the top-electrode region16is substantially flat (in the aforesaid horizontal plane xy), in a resting condition, i.e., in the absence of deformation; the bottom-electrode region12is, instead, patterned in a manner corresponding to an underlying patterned structure17, in this case entirely constituted by the aforesaid dielectric region19.

Consequently, the piezoelectric stack11has a variable section (in a plane transverse to the horizontal plane xy, in the example ofFIG.2in the plane xz), and in particular the piezoelectric material region14has a first thickness w1 along the vertical axis z at a first area14′ thereof, and a second thickness w2 along the same vertical axis z in a second area14″ thereof, the second thickness w2 being smaller than the first thickness w1.

In greater detail, the piezoelectric material region14has projections14ahaving the first thickness w1, which jointly define the aforesaid first area14′, and recesses14bwith the second thickness w2 along the same vertical axis z, which jointly define the aforesaid second area14″, the aforesaid projections14abeing interposed between the recesses14balong a first horizontal axis x of the horizontal plane xy.

The dielectric region19has, in a corresponding manner, respective projections19a, at the recesses14bof the overlying piezoelectric material region14; and respective recesses19b, at the projections14aof the overlying piezoelectric material region14.

As will be discussed in detail hereinafter, the piezoelectric material region14is formed by means of sol-gel deposition spin-coating techniques, which enable, thanks to the intrinsic properties of planarization (in particular, with the stacked layers constituting the PZT film that progressively assume a planar conformation starting from the underlying patterned structure17), the formation of the structure described, with the top-electrode region16, formed on the piezoelectric material region14, that is substantially flat (even though the piezoelectric material region14is formed on, and shaped like, the underlying patterned structure17).

In a possible embodiment, the first thickness w1 may, for example, be comprised between 2 μm and 3 μm. The second thickness (which corresponds to the minimum thickness of the PZT film) may be greater than or equal to 0.5 μm, preferably smaller than 1.2 μm (these values allowing to achieve a good uniformity in the deposition and subsequent planarization of the piezoelectric material region14).

As also illustrated inFIG.3, in the embodiment where the piezoelectric microelectromechanical structure10operates as a piezoelectric actuator, the aforesaid projections14aand the aforesaid recesses14bof the piezoelectric material region14(and in a corresponding manner the respective projections19aand the respective recesses19bof the dielectric region19) have a strip-like shape, elongated along a second horizontal axis y, which is orthogonal to the first horizontal axis x and forms with the first horizontal axis x the horizontal plane xy.

The piezoelectric microelectromechanical structure10has, in this case, a plurality of elementary units that repeat along the first horizontal axis x, each formed by a respective projection14aand a respective recess14bof the piezoelectric material region14.

In greater detail, again with reference toFIG.2(which is not in scale, just as with the other Figures), in a possible embodiment, the aforesaid projections14aof the piezoelectric material region14have a width, designated by La, along the first horizontal axis x, preferably greater than or equal to 6 μm; the aforesaid recesses14bof the piezoelectric material region14have a width, designated by Lb, along the same first horizontal axis x, preferably greater than or equal to 5 μm; and the total size A occupied by the piezoelectric microelectromechanical structure10, once again along the first horizontal axis x, is equal to n·(La+Lb), where n is the number of elementary units of the piezoelectric microelectromechanical structure10.

During operation, application of a biasing voltage Vb between the top-electrode region16and the bottom-electrode region12causes deformation of the supporting element18in the direction of the vertical axis z.

In particular,FIG.4Ashows the vertical deformation of the supporting element18in the direction of the width, as the biasing voltage Vb applied between the bottom-electrode region12and the top-electrode region16varies, on the hypothesis that the supporting element18has a thickness of 4 μm and the recesses14bof the piezoelectric material region14(having the first thickness w1 of 2 μm) have a width Lb of 5 μm.

A maximum deformation occurs at the center of the membrane, having a maximum extension of 330 nm (i.e. 300 nm, corresponding to the case of an applied biasing voltage Vb of 40 V, plus 30 nm, corresponding to the case of a zero applied voltage).

Comparing this plot with the example ofFIG.1B(corresponding to a micromechanical structure having substantially the same configuration and size, except for the piezoelectric stack11), it is noted a 10% increase of the maximum deformation that can be obtained.

FIG.4Bshows the same plot on the hypothesis that, with the other dimensions being the same, the recesses14bof the piezoelectric material region14(having once again the first thickness w1 equal to 2 μm) have a width Lb of 10 μm.

A maximum deformation is obtained at the center of the membrane, having in this case a maximum extension of 346 nm (i.e. 280 nm, corresponding to the case of a biasing voltage Vb applied of 40 V, plus 66 nm, corresponding to the case of a zero applied voltage); therefore, in this case, a 15% increase is obtained as compared to the case of constant uniform thickness of the piezoelectric material region (shown inFIG.1B).

In general, the presence of the piezoelectric film with variable thickness enables generation, between the top and bottom electrodes, of locally variable electrical fields, and the consequent improvement in the piezoelectric performance. This improvement in performance is moreover due to the contribution of the piezoelectric coefficient d35, which intervenes in the case of PZT with variable thickness, whereas it is not exploited in the case of constant thickness.

A possible process for manufacturing the previously described piezoelectric microelectromechanical structure10is now discussed.

As shown inFIG.5A, the process starts with the provision of an semiconductor (silicon) on insulator (SOI) wafer20, comprising, stacked on top of one another, a supporting layer21, an insulating layer22, and an active layer23, the latter being of polycrystalline silicon and having a top surface23a. Alternatively, as will be on the other hand evident, the following may be envisaged: oxidation of an initial silicon layer and epitaxial growth of an overlying polysilicon layer, followed by planarization of a corresponding top surface (using the CMP—Chemical Mechanical Polishing—technique).

The process initially envisages growth of a thermal-oxide layer24on the top surface23aof the active layer23.

Then, inFIG.5B, the thermal-oxide layer24is subjected to a photolithographic process, for defining, by means of dry etching and subsequent cleaning, openings25which traverse the entire thickness of the thermal-oxide layer24, at regular intervals along the first horizontal axis x. Remaining portions of the thermal-oxide layer24(having substantially a same width as the recesses14bof the piezoelectric material region14that will then be formed) remain between consecutive openings25along the first horizontal axis x.

As shown inFIG.5C, a further oxide layer26is then deposited on the top surface23aof the active layer23; this further oxide layer26covers the underlying remaining portions of the thermal-oxide layer24and fills the bottom of the previously formed openings25(in contact with the aforesaid top surface23a). In particular, this further oxide layer26forms, together with the remaining portions of the thermal-oxide layer24, the dielectric region19of the piezoelectric microelectromechanical structure10, in particular the corresponding projections19a, at the aforesaid remaining portions of the thermal-oxide layer24, and the corresponding recesses19b, at the aforesaid openings25.

A conductive layer is then deposited so as to form, on the dielectric region19, the bottom-electrode region12.

Next, as shown inFIG.5D, the step of sol-gel deposition by means of spin coating is carried out to form the piezoelectric material region14on the bottom-electrode region12.

In particular, as mentioned previously, thanks to the intrinsic capacity of planarization of the PZT thin film thus formed, the resulting piezoelectric material region14has a variable section with the projections14ahaving the first thickness w1 and the recesses14bhaving the second thickness w2 along the same vertical axis z.

On the piezoelectric material region14, in particular on the corresponding planar top surface (in the horizontal plane xy), a further conductive layer is then deposited to form, on the dielectric region19, the top-electrode region16.

Next, as shown inFIG.5E, patterning of the top-electrode region16and of the piezoelectric material region14is carried out, by means of a dry photolithographic etching using a first etching mask (here not illustrated). In particular, with this etching, the total size A occupied by the piezoelectric microelectromechanical structure10along the first horizontal axis x is defined.

Next, as shown inFIG.5F, patterning of the bottom-electrode region12is carried out, by means of a dry photolithographic etching using a second etching mask (which is not illustrated either), having dimensions such as to entirely cover the piezoelectric material region14and the top-electrode region16, which have been defined in the previous step of the manufacturing process. At the end of this patterning step, the piezoelectric stack11of the piezoelectric microelectromechanical structure10is thus completely formed.

As shown inFIG.5G, a passivation layer28is next deposited on the piezoelectric stack11; the same passivation layer28is then subjected to etching to form through openings, which are filled with conductive material for the formation of a first conductive via29aand a second conductive via29bthrough the passivation layer28, which are designed to contact the bottom-electrode region12and, respectively, the top-electrode region16.

As shown inFIG.5H, the manufacturing process terminates with release, starting from the aforesaid active layer23, of the supporting element18, in this case configured as a membrane, by means of a dry etching from the back of the supporting layer21of the SOI wafer20, which leads to formation of an opening30, underneath the supporting element18.

A further embodiment of the present solution is now described, with the piezoelectric microelectromechanical structure10operating jointly as a piezoelectric actuator and as a piezoelectric detector. This solution may be advantageously used for providing an ultrasonic transducer, which is able to transmit ultrasound waves, at a frequency higher than 20 kHz, and moreover receive the echo of the waves reflected by an obstacle, for example to obtain time of flight (ToF) information from processing of the reflected signal.

As shown inFIG.6, the first area14′ of the piezoelectric material region14, with the first thickness w1 along the vertical axis z (inFIG.6, a projection14ais shown defining said first area14′), contributes (with an associated electronic circuitry, here not illustrated) to providing the piezoelectric detector for detecting ultrasound waves reflected as echo; whereas the second area14″, with the second thickness w2 along the same vertical axis z, smaller than the first thickness w1 (in the figure a recess14bis shown defining said second area14″), contributes (with an associated electronic circuitry, here not illustrated) to providing the piezoelectric actuator for generation of the ultrasound waves.

Consequently, in this embodiment, the first area14′ and the second area14″ of the piezoelectric material region14are separate and distinct (instead of being continuous and uniform, as in the first embodiment discussed previously with reference toFIG.2), arranged at a separation distance D along the first horizontal axis x; moreover, separate and distinct respective bottom-electrode and-top electrode regions12,16are provided, respectively for biasing the piezoelectric actuator by means of a biasing voltage Vb and for reading an output signal Vout supplied by the piezoelectric detector.

In general, the presence of the piezoelectric stack11with variable section enables optimization of the detection performance, without penalizing the actuation performance. In fact, the greater thickness of the piezoelectric material region14at the first area14′ dedicated to detection allows to have a greater distance between the top and bottom electrodes12,16and, consequently, a smaller capacitance to be charged during operation as detector (in a known manner, the capacitance being inversely proportional to the distance between the electrodes) and a greater detection voltage acquired at output between the same electrodes.

Simulations and experimental tests for the disclosed structure have shown the possibility of obtaining an output voltage Vout that is substantially doubled, by exploiting the aforesaid variable section of the piezoelectric stack11, as compared to a traditional solution with uniform thickness that is constant throughout the piezoelectric material region14.

As will be evident, a same bottom electrode could alternatively be used for the piezoelectric actuator and the piezoelectric detector, the common bottom electrode constituting in this case a same ground reference.

In this regard,FIG.7Ashows a further embodiment of the piezoelectric microelectromechanical structure10, in which a single bottom-electrode region12is present, in common for the projections14aand the recesses14bof the piezoelectric material region14(which has, also in this case, the first and second areas14′,14″ that are distinct and separate from one another, dedicated, respectively, to piezoelectric detection and actuation).

Furthermore, in this embodiment, the aforesaid projections14aof the piezoelectric material region14are obtained only in part in the underlying dielectric region19(as in the embodiments discussed previously), given that they extend also through a surface portion of the underlying supporting element18; in other words, in this embodiment, the patterned structure17underneath the piezoelectric stack11, which determines the variable section thereof, is jointly defined by the aforesaid dielectric region19and by the aforesaid top portion of the supporting element18.

As schematically shown also inFIG.7B, in a possible embodiment the projections14aof the piezoelectric region14define a ring around the recess14b, arranged at the center and having a substantially circular shape in plan view; this ring is moreover arranged at the periphery of the membrane defined by the supporting element18, which may itself have a circular shape in plan view, or a generically polygonal shape.

The position of the projections14a, dedicated, as discussed, to piezoelectric detection, in this case corresponds to the area of greater stress of the membrane, so as to maximize the detection sensitivity.

It will be noted that the value of the distance D between the first and second areas14′,14″ of the piezoelectric material region14along the first horizontal axis x (i.e., in the direction of separation in the horizontal plane xy between the first and second areas14′,14″) is a further factor that affects the degree of piezoelectric response and the value of the output voltage Vout provided by the piezoelectric microelectromechanical structure10.

Considering a width of the projections14aalong the first axis x approximately equal to 24 μm and a width of the recess14balong the same first axis x approximately equal to 1232 μm, a value of the first thickness w1 equal to 2 μm, a value of the second thickness w2 equal to 1 μm, a thickness along the vertical axis z of the dielectric region19of 0.5 μm, and a thickness of the supporting element18of 4 μm, the following values are found for maximum displacement T_max along the vertical axis z of the piezoelectric detector (i.e., in the first area14′ of the piezoelectric material region14) and of maximum output voltage Vout_max as the distance D varies, applying a biasing voltage of 5 Vdc+50 mVpp at 68 kHz to the piezoelectric actuator (i.e., at the second area14″ of the same piezoelectric material region14): D=100 μm, T_max=2.5 μm, Vout_max=0.05 V; D=150 μm, T_max=2.8 μm, Vout_max=0.12 V; D=200 μm, T_max=2.8 μm, Vout_max=0.175 V; D=250 μm, T_max=2.2 μm, Vout_max=0.08 V; and D=300 μm, T_max=2.2 μm, Vout_max=0.0055 V.

In the configuration described, it is therefore advantageous to have a distance D between the first and second areas14′,14″ of the piezoelectric material region14along the first horizontal axis x approximately equal to 200 μm. In the same configuration, but on the hypothesis (as in known solutions) of using a uniform thickness for the piezoelectric material region14(equal to 1 μm), a maximum output voltage Vout_max of 0.09 V, which is equal to approximately half the value that can be obtained with the solution described previously, is achieved with the piezoelectric material region14having a variable section.

With reference once again to the embodiment ofFIG.7A, a possible process for manufacturing the corresponding piezoelectric microelectromechanical structure10is now described.

As shown inFIG.8A, also in this case the process starts with the provision of an SOI wafer20, comprising, stacked on one another, a supporting layer21, an insulating layer22(for example, with a thickness of 0.5 μm), and an active layer23(for example, with a thickness of 4 μm), the latter consisting of polycrystalline silicon and having a top surface23a. Alternatively, also in this case, oxidation of an initial silicon layer and epitaxial growth of an overlying polysilicon layer may be envisaged, followed by planarization of a corresponding top surface, using the CMP (Chemical Mechanical Polishing) technique.

The process initially envisages growth of a thermal-oxide layer24, on the top surface23aof the active layer23, also having, for example, a thickness of 0.5 μm.

Then,FIG.8B, the aforesaid thermal-oxide layer24and the underlying active layer23are subjected to a photolithographic process, for defining, by means of a dry etching and subsequent cleaning, openings25, which traverse the entire thickness of the thermal-oxide layer24and a surface portion of the active layer23; for example, these openings25have an extension t of 1 μm along the vertical axis z. The openings25define, for example, a ring in plan view, internally to which the first area14′ of the piezoelectric material region14(see in this regard also the foregoing discussion) will be formed.

As shown inFIG.8C, a further oxide layer26is then thermally deposited, filling the bottom of the previously formed openings25. In particular, the further oxide layer26forms, together with the remaining portions of the thermal-oxide layer24, the dielectric region19of the piezoelectric microelectromechanical structure10(and part of the patterned structure17).

As shown inFIG.8D, a conductive layer is then deposited so as to form the bottom-electrode region12on the dielectric region19.

This step is followed by spin coating sol-gel deposition, for the formation of the piezoelectric material region14on the bottom-electrode region12.

In particular, as previously mentioned, thanks to the intrinsic capacity of planarization of the PZT thin film thus formed, the resulting piezoelectric material region14has a variable section with the first thickness w1 at the openings25previously formed, and the second thickness w2 elsewhere.

A further conductive layer is then deposited on the piezoelectric material region14, in particular on the corresponding planar top surface (in the horizontal plane xy), so as to form, above the dielectric region19, the top-electrode region16.

Next, as shown inFIG.8E, patterning of the top-electrode region16and of the piezoelectric material region14is carried out by means of a dry photolithographic etching by using an etching mask. Following this etch, the first and second areas14′,14″ of the piezoelectric material region14are in particular defined, which are separate and distinct from one another; moreover, the respective top-electrode regions16are defined (in this case the bottom-electrode region12being, instead, in common).

Next, as shown inFIG.8F, a passivation layer28is deposited on the piezoelectric stack11, which is then subjected to etching for formation of through openings, which are then filled with a conductive material so as to form a first conductive via29aand a second conductive via29bthrough the same passivation layer28, which are designed to contact, respectively, the bottom-electrode region12and, in this case, in a separate and independent manner, the top-electrode regions16associated to the first and second areas14′,14″ of the piezoelectric material region14.

With reference once again to what is shown inFIG.7A, the manufacturing process terminates with release of the supporting element18, in this case configured as a membrane, by means of a dry etching from the back of the supporting layer21of the SOI wafer20, which leads to formation of the opening30underneath the same supporting element18.

The advantages of the described solution emerge clearly from the foregoing discussion.

In any case, it is again underlined that formation of the piezoelectric stack11with the piezoelectric material region14having a variable thickness enables an improvement in the piezoelectric performance, both as regards piezoelectric actuation (in terms of displacement that can be obtained) and as regards piezoelectric detection (in terms of sensitivity).

Advantageously, the manufacturing process does not envisage substantial modifications as compared to known solutions, therefore not entailing a substantial increase in terms of time and costs; in fact, as described in detail, the intrinsic capacity of planarization of sol-gel deposition of the PZT material is exploited in order to provide the aforesaid piezoelectric stack11having a variable section, on the underlying patterned structure17.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the appended claims.

In particular, as on the other hand already highlighted previously, the aforesaid patterned structure17may be obtained just in the dielectric region19underlying the piezoelectric stack11, or may also extend through the surface portion of the underlying layer of material in which the supporting element18of the piezoelectric stack11is defined.

In addition, different shapes and configurations may be envisaged for the aforesaid patterned structure17and for the piezoelectric material region14, different from the strip-like or ring-like configurations represented previously.

For instance, the projections14aof the piezoelectric material region14could have an elliptical shape in plan view, be arranged in the form of a grating or as concentric rings, either continuous or interrupted but connected in series through a metallization, with the aim once again of improving the performance (for example, of reducing the capacitance and increasing the voltage generated in the piezoelectric detector case).

The supporting element18could moreover have different shapes or configurations, for example being made by cantilever elements or the like.

It is also highlighted that the solution described may possibly be used in combination with other known solutions to improve piezoelectric performance, such as envisaging use of a doped-PZT solution or a so-called gradient-free approach in order to obtain a further improvement of performance.

Finally, it is clear that the solution described may be advantageously applied to all MEMS devices in which piezoelectric actuation and/or detection are used, for example in print-heads, micromirrors, ultrasound generators, linear actuators, micro-tweezers, nano-positioners for hard disks, etc.