Patent ID: 12244155

Like reference numerals refer to corresponding parts throughout the several views of the drawings.

DETAILED DESCRIPTION

FIG.1illustrates an RF signal generating apparatus or system100. The RF signal may be generated in response to a user command entered at a keyboard. In one embodiment, the RF signal is generated in response to the identification of a target by a target detector101, such as a camera utilizing computer vision algorithms. Consider the case of an unmanned aerial vehicle or drone, the target detector101collects a signature characterizing the flight attributes of the drone. The target detector101also collects free space parameters associated with the drone, such as azimuth angle, elevation and range. Embodiments described collect this information when the target is 500 to 300 meters from the target detector101. The signature and free space parameters are passed from the target detector to a central computer102.

The central computer102classifies the target and selects RF waveform parameters, which are passed to an RF signal generator103. In various implementations, the RF signal generator103can be programmable and controlled by the computer102to change various parameters of the generated RF signal including but not limited to frequency and power of the RF signal. The RF signal generator103creates RF signals in accordance with the RF waveform parameters. Each RF signal has a waveform of the frequency, pulse width, pulse repetition interval and intra-pulse modulation specified by the RF waveform parameters received from the central computer102. The frequency, pulse width, pulse repetition interval and intra-pulse modulation of the generated RF signal can be changed by the computer102in real-time or sufficiently real-time.

The RF signal generator103produces RF signals for multiple channels that are applied to amplifier chains104_1through104_N. The RF signals for the multiple channels are phase shifted relative to one another in accordance with RF frequency waveform parameters. In one embodiment, the phase shifting is digitally performed within the RF signal generator103. Alternately, analog phase shifters may shift the RF signals prior to applying them to the amplifier chains104_1through104_N. In some implementations, the amplitude of some of the RF signals for the multiple channels can be attenuated as compared to the amplitude of some other of the RF signals for the multiple channels. Although, in the illustrated implementation, the computer102is distinct from the RF signal generator103, in various other implementations, the computer102and the RF signal generator103can be integrated together.

Each amplifier chain has a plurality of solid-state power amplifiers, each of which has a gate voltage on set point derived from an automatic calibration operation, as detailed below. Some of the plurality of solid-state power amplifiers may be arranged serially/sequentially in some implementations. Some of the plurality of solid-state power amplifiers may be arranged in a power combining configuration. Each amplifier chain produces an amplified RF signal. In one embodiment, a few mW RF signal from the RF signal generator103is amplified to a few kWs. The amplifier chain may utilize a combination of solid-state amplifiers, including silicon laterally diffused metal-oxide semiconductors, Gallium Nitride, Scandium Aluminum Nitride, GaAs and InP.

The channels of RF signals from the amplifier chains104_1through104_N are applied to an antenna array106. Each amplifier chain has a corresponding antenna in the antenna array106. The antenna array106broadcasts the channels of RF signals as a steered composite RF signal with Megawatts of radiated power. That is, individual RF signals emitted from different antennae in the antenna array106interact in free space to generate a composite RF signal that is directed to a specified location corresponding to the location of the target. The antenna array106may include a mechanical gimbal to position individual antennae. In various implementations, the antenna array106can further amplify the RF signal by about 10-1000 times.

The RF signal generator103also sends control signals to the power sequencer105. The control signals gate amplifiers in the amplifier chains104_1through104_N to produce the channels of RF signals. The control signals ensure that little (e.g., micro to nano amps) leakage or quiescent current is drawn when an RF signal is not being generated. The leakage and quiescent current can be quite large in high power amplifiers circuits if not gated. In one embodiment, the RF signals and power gating signals are turned on and off in 10s of nanoseconds.

The amplified RF signals from the amplifier chains104_1through104_N are applied to an antenna array106. The phased array RF signals form a steered composite RF signal to disable a target, typically when it is approximately 100 meters from the antenna array106. The steered composite RF signal has Megawatts of radiated power.

System100also includes an AC power source107for the different elements of system100. The AC power source may operate with a power distributor108, which applies power to the power sequencer105. In one embodiment, the power distributor108converts from AC to DC power. Generally, the conversion from AC to DC can happen either locally at each amplifier or at the system level.

FIG.2illustrates details of certain components in system100. Central computer102includes a processor or central processing unit200connected to a memory202. The memory202stores instructions executed by processor200. The instructions include a target classifier204. In one embodiment, the target classifier204matches the signature of the attributes of the target to a waveform in a waveform look-up table206. The waveform selector208designates a waveform to disable the target. The designated waveform also includes free space parameters to ensure that the steered composite RF signal intercepts the target. The steered composite RF signal is formed by a collection of phase offset RF signals. The central computer passes RF waveform parameters to the RF signal generator103. The RF waveform parameters include information about azimuth angle and elevation angle of the target, azimuth and elevation angle of friendly targets that do not need to be disabled, frequency of the RF waveform, pulse width and duty cycle of the RF pulses, position and height/depth of peaks/nulls in the RF beam.

In one embodiment, the RF signal generator103is implemented as an RF system on a Chip Field Programmable Gate array (RFSoC FPGA). The RFSoC FPGA103includes a gate array210and a direct digital synthesizer212that creates waveforms of the frequency, pulse width, pulse repetition interval and intra-pulse modulation specified by the RF frequency waveform parameters generated by the central computer102. The gate array210is configured to perform a variety of functions including but not limited to determining the time intervals at which different components of the amplifier is powered up and powered down. The waveforms are passed to a collection of digital-to-analog (DAC) converters214_1through214_N. Outputs from the DACs214_1through214_N are optionally conditioned by signal conditioning units (SCUs). In various implementations, the SCUs can comprise filters216_1through216_N as depicted inFIG.2. The filters216_1through216_N may filter the RF signals to a frequency band of interest. In some implementations, the SCUs can comprise one or more phase shifters and/or attenuators that can achieve the desired azimuth and elevation angles for the generated RF beam. The outputs from the RF signal generator103are applied to amplifier chains104_1through104_N. Each amplifier chain terminates in an antenna of antenna array106, such as antennae220_1through220_N. The RFSoC FPGA103allows digital formation of signal beams which has several advantages including but not limited to increasing/maximizing signal power in certain regions of space and decreasing/minimizing signal power in certain other regions of space. Accordingly, signal power can be focused on targets in certain regions of space while reducing the signal power on targets in certain other regions of space. Digitally forming signal beams as discussed above also advantageously allow the power, frequency and other parameters of the signal beam to be changed in sufficiently real-time (e.g., in less than 1 millisecond).

FIG.3is a block diagram of different components ofFIGS.1and2, including the RF signal generator103, power sequencer105, and an amplifier chain104_1. The RF signal generator103receives a control signal from central computer102on node301. A synchronizing clock signal is received on node303.

A broadcast signal on node304, an Ethernet signal in one embodiment, is sent to a plurality of power sequencing smart slave units (or circuits or devices)309_1and309_2. In the one embodiment, the broadcast signal is distributed through a router307. The broadcast signal initiates a calibration mode in smart slave circuits, such that they identify the optimal “on” set point gate voltage for the power amps311.

The RF signal generator103sends a very fast signal with deterministic delay, such as a Low Voltage Differential Signal (LVDS) to power sequencer105. The power sequencer105operates as a master power sequencing gating unit that simultaneously controls smart slave devices309_1and309_2. In particular, the power sequencer105sends a master voltage to the slave units309_1and309_2. The slave units309_1and309_2offset this master voltage with their individual voltage offsets that they established in calibration mode, so that each power amplifier has an optimal gate voltage. Many power amplifiers have different optimal set gate voltages for “on” operation; the disclosed circuits can be configured such that each individual power amp311has its own set point.

The RF signal generator103synchronizes using “on” signals applied to the power sequencers105. The RF signal generator103also applies an RF signal on node310, which is propagated through power amps311. The power amp chain may have one or more filters312. A portion of the RF signal from the amplifier can be tapped by a coupler313and sent back to the RF signal generator103or the computer102for monitoring purposes. The monitored information can include information regarding the phase, amplitude, power level and timing of the power amplifiers. The monitored information is considered to update timing and control algorithms.

The RF signal is amplified through the power amplifiers311and is sent to an antenna314of the antenna array106. The output from the different antennae of the antenna array106form a steered composite RF signal.

Power efficiency and linearity are important figures of merits (FoMs) for amplifier based systems. Power efficiency in field effect transistor (FET) amplifier (e.g., gallium nitride (GaN) FET amplifier) based systems can be improved by controlling the voltages provided to the gate and the drain terminals of a FET amplifier. Various implementations of a FET or a High Electron Mobility Transistor (HEMT) amplifier that is configured to be operated in saturation can benefit from a bipolar gate supply which can source and sink current. The bipolar gate supply can advantageously maintain the gate voltage at a desired voltage level.

Various implementations described herein include a bipolar high impedance gate driver that can source or sink current when the amplifier is operated at or near saturation. In addition to maintaining the gate voltage at a desired level, the bipolar high impedance gate driver can draw minimal amount of DC current and dynamically provide current to the gate terminal of the amplifier when the signal to be amplified is input to the amplifier. Various implementations of a bipolar high impedance gate driver described herein comprise an operational amplifier (opamp). The bipolar high impedance gate driver can improve various measures of efficiency for amplifier-based systems including drain efficiency, power-added efficiency, total efficiency, amplifier efficiency and wall-plug efficiency.

FIG.4Aillustrates an implementation of a system comprising a plurality of high power amplifiers (e.g., amplifier410) that are driven by corresponding bipolar high impedance gate drivers (e.g., driver407). The voltage and/or current output from the bipolar high impedance gate drivers is controlled by a power controller (e.g., controller309). As discussed above, the power controller can comprise a master control unit (e.g., power sequencer105discussed above) and a plurality of slave control units (e.g., slave units309_1and309_2discussed above). In some embodiments, the master control unit and the slave control units can be implemented as separate devices. In some other embodiments, the master control unit and the slave control units can be implemented as a single device.

Referring toFIG.4A, the RF signal generator103applying an “on” signal from node408to the power sequencer105, operates as a master power gating and sequencing circuit that controls slave power amplifiers311. In one embodiment, this signal is a Low voltage differential signal (LVDS) that controls a switch403, which causes current from power supply404to flow during an “on” state and stops current flow in “off” state. The power supply voltage can provide an offset voltage, which is added to an off voltage VOFF406when the switch403is closed. In some embodiments, the amplifier410can be Gallium Nitride devices. In such embodiments, the off voltage VOFF406can be about −5 Volts and the power supply voltage can be about 3 volts. Accordingly, the output voltage at node409is about −2 Volts, which is approximately the gate voltage that turns on Gallium Nitride amplifiers410. When the switch is open, the output voltage on node409defaults back to the off voltage VOFF, which is −5 Volts in one embodiment, which is the gate voltage that turns Gallium Nitride transistors off and reduces leakage current down to about 10 microamps. The value of the off voltage VOFF and the offset voltage can be different from −5 Volts and 3 Volts respectively depending on the turn-on voltage of the amplifier410. Node411carries a broadcast signal that initiates the auto-calibrate operation of the smart slave circuits309_1and309_2. In one embodiment, each smart slave circuit is implemented with an FPGA configured to determine the optimal gate voltage set point for turning on a slave amplifier.

Digital to analog converter (DAC)413provides an offset voltage that gets added to the master voltage on node409. This offset voltage is tuned to each individual power amplifier410to provide optimal set point bias voltage VG1on node414and maximum power out from the power amp410. It also enables optimum voltage in the “off” state and minimizes leakage current. The master-slave architecture facilitates fine grained voltage offsets, which is advantageous in efficient operation of many transistors, which may be sensitive to gate voltage offsets at the millivolt level. In some implementations, the disclosed technology maximizes voltage offset resolution. For example, the master-slave architecture can advantageously change the voltage provided to the gate terminal of the amplifier in increments of 1 millivolt or less.

The smart slave circuit309_1or309_2controls a plurality of DACs413and stores different optimum set points for both the on and off states for each power amplifier. In the auto-calibration mode, the current sensor415is used to feedback a current reading to the smart slave circuit. This voltage offset on DAC413is tuned very slightly, by the millivolt in one embodiment, until the current sensed from sensor415reaches an optimum current value, as per the data sheets for the power amplifiers410. This voltage offset is stored. This process is repeated to minimize the current in “off” state. The current can also be sensed during active operation to determine the viability of the power amp. If the current starts to degrade or change or significantly decrease, this can indicate that the amplifier is damaged and needs to be replaced or can indicate that the temperature is out of range for optimal operation. This method of adjusting the voltage offset on DAC413based on the current sensed from415is explained in further detail below with reference toFIGS.8-13.

The capacitor416can be tuned (manually or electronically) to change the rise and fall time for the gate bias signal on node414. For example, in some embodiments, capacitor416is real time programmable by the smart control FPGA309, such as by a series of switches, to include a variable amount of capacitance in the feedback path across capacitor416. This is a useful feature because different power amplifiers410can each have a different gate capacitance. Capacitor416can be tuned based on the gate capacitance for optimal operation. Tuning capacitor416affects how fast or slow the rise time is on the gate voltage at node414, this effects speed and efficiency of the power gating. Changing the charge on capacitor416can also change the amount of time the power amplifier rings or oscillates. In other embodiments, capacitor416is configured to tune the rise and fall time for very fast operation.

As discussed above, the computer102receives a signal from the target detector101, such as a sensor/camera in some embodiments or radar in other embodiments, and triggers a target detection algorithm. The computer102classifies the target and selects a waveform that can disable the target. Various parameters of the waveform and details about the target are transmitted to the RF generator. The computer102also triggers the various amplifier chains104_1to104_N with a signal to start the power sequencing for each amplifier in the amplifier chains. The signals are sent to each amplifier in the amplifier chains such that the power sequence is started at the same time, in a coherent, synchronized way. The voltage sequence timing diagram is shown and described below with reference toFIGS.5and6. As used herein, power sequencing comprises providing appropriate values to the various terminals of an amplifier (e.g., gate, source and drain) turn on/turn off the amplifiers.

Power sequencing also turns on the power gating circuitry, which switches on the voltage/current supply to the amplifiers (e.g., the high voltage power amplifiers). The RF waveform digital circuitry is triggered simultaneously to send an array of RF signal inputs to the amplifier chains. As discussed below with reference toFIGS.5and6, the amplifiers are turned on for short period when a target has been acquired which advantageously allows the system to emit RF signals high peak power (e.g., of the order of Megawatts) with low average power (e.g., less than 5 kW).

FIG.4Bschematically illustrates an implementation of a gate biasing system that is triggered automatically by an incoming RF signal. The gate biasing system comprises a switching element420which is triggered by the incoming RF signal.FIG.4Cshows an implementation of the switching element420. The switching element420can comprise a Schottky detector422and a comparator/switch424. When the signal generator103outputs a RF signal, the Schottky detector produces a RF detect voltage which is greater than a reference voltage of the comparator/switch424thereby causing the comparator/switch424to be in the closed state and output a bias voltage VON which turns on the amplifier311. For an implementation of the amplifier311comprising a GaN device, the output voltage VON can be in a range between −2V and −5V. The smart slave unit309_1or309_2can provide a tunable offset voltage which can the adjust the bias voltage VON to optimize one or more performance metrics of the amplifier311. In the absence of the RF signal from the signal generator103, the switch424may be considered to be in the open state which causes a voltage VOFF to be provided to the amplifier311which turns the amplifier311off. For an implementation of the amplifier311comprising a GaN device, the output voltage VOFF can be less than −5.5V, such as, for example, between about −12V and about −6V. The schematic shown inFIGS.4B and4Ccan be an alternate implementation which is triggered by the RF signal itself instead of a control signal from the RF signal generator103.

FIG.5illustrates waveforms that may be used in conjunction with the circuitry ofFIG.4. The supply voltage501(VSUPPLY inFIG.4A) to the power amp (410inFIG.4A) is turned on first. Alternately, it may be left on all the time. The gate voltage waveform502is applied to node414ofFIG.4A. Then, the RF signal from RF signal generator103is applied to node414. This example is for a 65 Volt Gallium Nitride (GaN) solid state power amplifier, but the principle may generally apply to any solid-state power amplifier. The drain voltage501toggles from 0 Volts to 65 Volts. Then, the source current is tuned from −5 Volts to −2 Volts, where it is considered “open” and the transistor is “on” so that a quiescent current starts to flow. Finally, the RF input signal503is applied and the transistor draws active power once the RF power is on, in some embodiments, up to 30 amps of current create 1,500 watts of power out of the transistor410.

The RF signal503is sent out as a short pulse, for example, as short as 10 ns or as long as milliseconds. The length of the pulse depends on the type of target. After the RF pulse is complete, the source voltage is pinched off back down to −6 Volts, and then shortly after the drain voltage is tuned from 65 Volts down to 0 Volts and the transistor is off and therefore draws minimal current.

FIG.6illustrates a timing diagram showing a non-linear pulse train601with uneven pulses. The pulse train601is sent through power amp410, where the RF and voltage bias is turned on and off very quickly (e.g., 10s of nanoseconds). In one embodiment, the pulses are in an arbitrary pattern at a frequency of 1 GHz.

FIG.7illustrates a system700corresponding the system100ofFIG.1. However, in this embodiment, the antenna array106transmits its RF power signal to a reflector710. For example, 16 antennae operating at the L-band frequency with half-wavelength spacing may transmit into a 3 meter reflector dish. The reflector dish may have a subreflector. A mechanical gimbal702may control the position of the reflector710in response to control signals from central computer102.

The 3 meter reflector dish provides 28.1 dBi, or645X linear magnification of the energy. In one embodiment, the reflector dish is fed by a 16 element phased array antenna in a 4×4 array. At a 1% duty cycle and 70% power efficiency, the power system only requires 550 watts of DC power output, enabling a small power supply.

The implementations of the phased array systems described above are configured to be software defined via element level digital control of each channel of the phased array. The RF signal input to the phased array can be generated digitally without requiring RF or analog components using novel transmitter schemes (e.g., a monobit transmitter).

Power Management Systems to Adjust Bias Condition of RF Amplifiers

FIG.8Aillustrates another implementation of the system100ofFIG.2. The system100is illustrated as being augmented with a plurality of power management systems809_1to809_N configured to provide the required voltages and currents to efficiently operate the amplifiers in the amplifier chains104_1to104_N. In various implementations, the power management systems809_1to809_N can comprise or be associated with a power distributing system similar to the power distributor108and/or a power sequencing system similar to the power sequencer105. Individual power management systems809_1to809_N are configured to (i) in response to receiving a signal from the RF generator103provide appropriate bias voltages and currents to turn-on the amplifiers in the corresponding amplifier chains104_1to104_N prior to/synchronously with the arrival of the RF signal from the RF generator103; (ii) adjust or change the bias voltages and currents to the amplifiers based on information obtained about the input signal characteristics, output signal characteristics, system operating conditions (e.g., operating temperature, operating currents/voltages at various terminals of the amplifier/system, etc.), an input received from a user or an electronic processing system controlling the biasing systems and/or by information obtained from look-up tables that provide an understanding of the state of the amplifier; and/or (iii) reduce the bias voltages and currents to turn-off the amplifiers in the corresponding amplifier chains104_1to104_N in response to absence of signal to be amplified or a sensed characteristic (e.g., input signal power, output signal power, temperature, gate current/voltage or drain current/voltage) being outside a range of values.

As discussed above, the plurality of power management systems809_1to809_N can comprise sensors (e.g., current sensors) that can sense current values (e.g., drain and/or gate current values) of the individual amplifiers in the amplifier chains104_1to104_N. The power management systems809_1to809_N can be configured to sense the current values of the individual amplifiers in the amplifier chains104_1to104_N intermittently (e.g., periodically). In some implementations, the power management systems809_1to809_N can be configured to sense the current values of the individual amplifiers in the amplifier chains104_1to104_N continuously. In various implementations, the output from the current sensor can be sampled using an analog to digital converter (ADC) and averaged over a number of samples (e.g., 128 samples, 512 samples, etc.) to obtain the sensed current value.

The sensed current value can be analyzed by the power management systems809_1to809_N to determine an operational or a physical characteristic (e.g., temperature, input/output signal power, voltage/current at various terminals of the amplifier) of the individual amplifier. For example, a sensed current value above a first threshold current value when the amplifier is not turned on can be indicative of a defect in the amplifier or a defect in the circuit board on which the amplifier is mounted. As another example, a sensed current value above a second threshold current value when the amplifier is turned on but no signal to be amplified is provided to the input can be indicative of a defect in the amplifier or a rise in the temperature of the amplifier. As yet another example, a sensed current value above a third threshold current value when the amplifier is turned on and a signal to be amplified is provided to the input can be indicative of a defect in the amplifier or a rise in the temperature of the amplifier. Accordingly, the power management systems809_1to809_N can be configured to compare individual amplifier current values to target amplifier current values to identify an amplifier state error. In response to determining that the amplifier current value of a particular amplifier has deviated from a target amplifier current value (e.g., first, second or third threshold values discussed above), the power management system controlling that particular amplifier is configured to determine the amount by which values of the voltages/current provided to the amplifier should be offset to achieve efficient operation of the amplifier and provide that offset value. In various implementations, one or more of tasks of correlating the sensed current values to a physical characteristic of the amplifier or determining the amount by which values of the voltages/current provided to the amplifier should be offset by to achieve efficient operation of the amplifier can be performed by the computer102instead of the power management systems809_1to809_N.

The target amplifier current values may be based upon several factors for optimal system operation. For example, the target amplifier current values may be calibration amplifier current values for specified temperatures. The target amplifier current values may be calibration amplifier current values to compensate for amplifier manufacturing process variations. The target amplifier current values may be calibration amplifier current values to compensate for voltage variations. The target amplifier current values may be calibration amplifier current values to compensate for radio frequency phase variations. The target amplifier current values may be historical performance amplifier current values. The historical performance amplifier current values may be used to identify amplifier degradation over time.

Without any loss of generality, the plurality of power management systems809_1to809_N can comprise a variety of sensors. For example, the plurality of power management systems809_1to809_N can comprise voltage sensors configured to measure voltages at the various parts of the amplifiers in the amplifier chains104_1to104_N. As another example, the plurality of power management systems809_1to809_N can comprise temperature sensors configured to measure temperature of the amplifiers in the amplifier chains104_1to104_N. The temperature sensors can be configured to measure the device temperature of the amplifiers in the amplifier chains104_1to104_N or temperature of the housing or the mount on which the amplifiers in the amplifier chains104_1to104_N are disposed.

The system100can be configured as a phased array comprising a plurality of phased array elements, each phased array element comprising one of the amplifier chains104_1to104_N and the corresponding antenna220_1to220_N of the antenna array106. Without any loss of generality, the amplifiers in the amplifier chains104_1to104_N can comprise three terminal semiconductor devices, such as, for example, a field effect transistor (FET). The power management systems809_1to809_N can advantageously increase or optimize one of more figures of merit (e.g., output power, power efficiency, linearity, etc.) of the amplifiers and accordingly the phased array system is discussed below. As a part of initialization procedure of the phased array system100, the different amplifiers in the amplifier chains104_1to104_N are characterized to correlate the different bias settings (e.g., gate voltage, drain voltage, drain current, gate current) to the gain and/or the power output from the amplifiers at different temperatures. The characterized information is stored in a memory associated with the power management systems809_1to809_N. The characterization can be done when the phased array system is built and then subsequently as part of maintenance of the phased array system. For example, after the initial characterization when the phased array system100is built, further characterization of the amplifiers can be performed once or twice a year. In some other implementations, the amplifiers can be characterized before a mission. As used herein, a mission refers to the phased array being in a state where it is ready to emit electromagnetic pulsed radiation. The period of a mission can range from a few minutes to a year or a few years. For example, a mission period can be a few minutes, half an hour, an hour, a few hours, a week, a month, a few months, a year, or a few years.

When the phase array is turned on at the start of the mission, the voltage at the drain terminal of the amplifiers in the amplifier chains104_1to104_N is set to a threshold drain bias voltage. In some implementations, the threshold drain bias voltage can correspond to a drain bias voltage that maximizes the power output from the amplifiers. In some implementations, the threshold drain bias voltage can correspond to a drain bias voltage that is required to operate the amplifiers in saturation or close to saturation. In some implementations, the threshold drain bias voltage can correspond to a drain voltage that optimizes the power output from the amplifiers and the drain efficiency. In yet some other implementations, the threshold drain bias voltage can correspond to a drain voltage that is a maximum allowable drain bias voltage that doesn't cause the amplifier to break down. The bias voltage at the gate terminal of the amplifiers in the amplifier chains104_1to104_N is set to a voltage that is below the turn-on voltage of the amplifier. Upon receiving indication that electromagnetic radiation will be input to the amplifiers in the amplifier chains104_1to104_N, the power management systems809_1to809_N can apply an offset voltage to gate terminals of the amplifiers in the corresponding amplifier chains104_1to104_N that would raise the voltage at the gate terminal of individual amplifiers in the amplifier chains104_1to104_N to a level that would cause a threshold amount of drain current to flow through the amplifier. The threshold amount of drain current can be a drain current that maximizes the output power from the amplifier. The threshold amount of drain current can be a drain current that optimizes power out from the amplifier as well as the power efficiency. The threshold amount of drain current can correspond to a drain current that optimizes output power, linearity and efficiency. The threshold drain current and the gate bias voltage (or offset voltage) which causes the threshold drain current to flow through the amplifier may be different for different amplifiers in the amplifiers chains104_1to104_N. The difference in the threshold drain current and the gate bias voltage (or offset voltage) can be attributed to variation in temperature across the elements of the phased array, variation in voltage across the elements of the phased array, variation in load and/or impedance across the elements of the phased array, or process variations between the different amplifiers. The energy radiated from the phased array system is optimized by optimizing the power out from individual elements of the phased array system by setting the gate voltage (or the offset voltage) of an individual amplifier of the phased array system to a value that causes a threshold amount of drain to flow through the amplifier.

During the operation of the phased array system, the drain current can be sensed from time to time and the gate bias voltage (or offset voltage) is adjusted/modulated to maintain the drain current at the threshold current level. The drain current can be sensed periodically or intermittently. In some implementations, the drain current can be sensed every at intervals less than 10 microseconds (e.g., less than 1 microsecond, less than 5 microseconds) and the gate bias voltage (or the offset voltage) can be adjusted to maintain the drain current at the threshold amount. In some implementations, the drain current can be continually sensed and the gate bias voltage (or the offset voltage) can be continuously adjusted to maintain the drain current at the threshold level. In some implementations, the gate bias voltage and the drain bias voltage can be modulated together to maintain the drain current at the threshold amount.

In various implementations, the gate bias voltage and the drain bias voltage can be modulated based on other sensed parameters, such as, for example, temperature, input signal power, output signal power, a measure of linearity of the output signal, or Voltage Standing Wave Ratio (VSWR) characteristics in addition to or instead of the sensed drain current.

FIG.8Billustrates an implementation of the power management system809_1. The power management system809_1can include various functional sub-systems, such as an electronic processing system811, a control system815, a memory (not shown), a sensing system821, a power adapting system823, and an input/output system819. The various functional sub-systems can be integrated in a single housing or in separate housings. In implementations where the different functional sub-systems are integrated in separate housings, the separate housings can include processing electronics and communication systems to communicate and function properly. For example, in some implementations, the power adapting system823and the sensing system821can be integrated in a separate housing. In such implementations, the electronic processing system811in cooperation with the control system815and the memory can provide signals to the power adapting system823to turn-on/turn-off the biasing voltages and currents to the amplifiers in response to receiving a signal from the RF generator103indicating the start/end of the RF signal and/or receiving information from the sensors that one or more sensed parameters are out of a range of values.

The power management system809_1can be implemented with a form factor of a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). The ASIC implementation may be advantageous to realize smaller form factors, such as, for example, a chip having a size of a 10 mm×10 mm, 5 mm×5 mm or 3 mm×3 mm. The power management system809_1is configured to obtain information about the signals to be amplified and monitor various currents and voltages of the amplifier to optimize and control operating currents and voltages of the amplifier. The power management system809_1can obtain the information about the signals to be amplified and the currents/voltages at various terminals of the amplifier in real time or substantially in real time. For example, the power management system809_1can obtain the information about the signals to be amplified and the currents/voltages at various terminals of the amplifier in a time interval less than about 1 second, in a time interval greater than or equal to about 1 millisecond and less than about 1 second, in a time interval greater than or equal to about 1 second and less than about 10 seconds, in a time interval greater than or equal to about 10 seconds and less than about 30 seconds, in a time interval greater than or equal to about 30 seconds and less than about 1 minute and/or in a range defined by any of these values.

The power management system809_1can provide several benefits including but not limited to increasing/optimizing power efficiency for a desired performance criterion. For example, consider that an amplifier in the amplifier chain104_1being controlled by the power management system809_1is operated in a high gain regime to provide a certain amount of RF output power. The power efficiency of that amplifier can be higher than a similar amplifier that is operated in a high gain regime to provide the same amount of RF output power but is not controlled by the power management system809_1. As another example, consider that an amplifier in the amplifier chain104_1controlled by the power management system809_1is operated to provide a certain amount of gain and linearity. The power efficiency of that amplifier can be higher than a similar amplifier that is operated to provide the same amount of gain and linearity but is not controlled by the power management system809_1. The use of the power management system809_1can also reduce direct current (DC) power consumption during operation of an amplifier as compared to direct current (DC) power consumption by an amplifier driven without a power management system809_1. The power management system809_1can improve linearity of an amplifier, help in automatic calibration of an amplifier over temperature, voltage and process variations, and/or autocalibration of a phased array system.

The electronic processing system811can comprise a hardware processor that is configured to execute instructions stored in the memory which will cause the power management system809_1to perform a variety of functions including, but not limited to, turning on/off or reduce voltages/currents provided to various terminals of an amplifier in response to detecting that the signal to be amplified is turned on/off or sensing individual amplifier current values and change the values of different voltages and currents in response to the deviations of the sensed current values from target values.

The input/output system819can be configured to provide wired/wireless connection with external devices and systems. For example, the input/output system819can comprise an Ethernet port (e.g., a Gigabit Ethernet (GbE) connector) that provides connection to the computer102and/or a router, one or more connectors that provide connection to the RF signal generator103, a connector that provides connection with an external power supply, a plurality of connectors that provide voltages/currents to one or more amplifiers, a plurality of connectors that can receive voltage/current information from the one or more amplifiers, and connectors that provide connection with a user interface (e.g., a display device). In various implementations, the input/output system819can comprise a command and control link to receive messages from the RF generator103and/or computer102.

The input/output system819can be configured to receive as input, a signal/trigger/information from the RF signal generator103and use the information from this input to determine the voltages and current for an amplifier in the amplifier chain104_1. As discussed above, the input received from the RF signal generator can be a trigger that conveys information that the RF signal will be turning on in a short while and causes the power management system809_1to start the power sequencing process and provide appropriate voltages and/or currents to bias the amplifiers in the corresponding amplifier chain104_1prior to the arrival of the RF signal. For example, the input from the RF signal generator can be a pulse enable signal which is high when the RF signal is on and low when the RF signal is off. In various implementations, the input from the RF signal generator103can be representative of the waveform being output by the DAC214_1of the RF generator103. In some implementations, the input can include instructions and/or settings to power on the power management system809_1, to power up an amplifier in the amplifier chain104_1, and other data to operate the power management system809_1and an amplifier in the amplifier chain104_1.

The input/output system819can comprise a communication system configured to communicate with external devices and systems. For example, the input/output system819can comprise Ethernet connectivity to send information including but not limited to amplifier health information, and efficiency statistics to the computer102. Ethernet connectivity can also help in synchronizing an array of many power management systems in phased array applications. The input/output system819comprises a plurality of connectors that are configured to provide voltages/currents to at least one terminal of an amplifier in the amplifier chain104_1. For example, the voltages and currents required to bias at least one of the gate, source and/or drain terminal of an amplifier in the amplifier chain104_1can be provided through the output ports of the power management system809_1. The power management system809_1can be configured to provide bias voltage and/or current to a plurality of amplifiers. For example, the power management system809_1can be configured to provide bias voltage and/or current to two, four, six or more amplifiers.

The sensing system821can be configured to sense current values at one or more terminals of the amplifier as discussed above. In various implementations, the sensing system821comprises at least one current sensor and an analog to digital converter (ADC) configured to sample and average the output of the current sensor (e.g., sensor415) to obtain a sensed current value. In another implementation of the sensing system821, the voltage drop across a resistor (e.g., a shunt resistor) connected to the drain terminal is measured. The drain current is obtained from the measured voltage drop and the value of the resistor. In such an implementation, the sensing circuit is designed to have low offset voltage and low noise which allows for greater accuracy in the measurement of the drain current. In various implementations, the current sensor need not be integrated with the other components of the sensing system821and/or the other sub-systems of the power management system809_1. Instead, the current sensor can be integrated with the amplifier. The number of current sensors can vary based on the number of amplifiers being controlled by the power management system809_1and the number of currents that are being monitored. For example, if the power management system809_1is configured to control four distinct amplifiers and it is desired to monitor the drain current of each of the four separate amplifiers, then the power management system809_1comprises four current sensors configured to monitor the drain current of each of the four distinct amplifiers.

The power adapting system823can be configured to convert power from an external power supply825(e.g., an AC power line, a battery source, a generator, etc.) to voltage and current waveforms required for operating the amplifiers being controlled by the power management system809_1. For example, in various implementations, the power adapting system823is configured to convert a 60V DC bus and generate appropriate voltage and current inputs for the various terminals of the amplifier. In some implementations, the power adapting system823may be configured to convert an incoming AC power line to DC power (e.g., DC voltages between about +20 Volts DC and about +80 Volts DC). The power adapting system823is configured to step up/down the converted DC voltage to appropriate voltages for the amplifier (e.g., in a voltage range between about +45 Volts and +70 Volts high voltage Gallium Nitride power amplifiers) through DC/DC converters. The stepped up/down voltages are provided to the various terminals of the amplifier (e.g., gate, drain, and/or source) in a sequence as discussed above in response to receiving a signal from the RF signal generator103and/or the computer102that the signal to be amplified is turned on/being turned on.

In various implementations, the power management system809_1comprises a “power gating” feature where the bias voltage/current at various terminals (e.g., gate, source, and/or drain) of the amplifier is adjusted in response to a sensed characteristic of the system. The sensed characteristics can comprise one or more of drain current, source current, gate current, gate voltage, drain voltage, voltage at different nodes of the amplifier system, current at different nodes of the amplifier system. In various implementations, in addition to or instead of modulating the gate and/or the drain bias voltage, voltages or currents at other nodes can be modulated to optimize the performance of the amplifier. The other nodes can comprise the source terminal, the back bias, the RF input circuits, RF output circuits, etc. In various implementations, the power management system809_1can provide offset voltages that raise and lower the biasing voltage to turn on/turn off the power amplifier in response to the turning on and turning off the RF signal. For example, in an implementation of the amplifier chain104_1comprising a GaN power amplifier, the power management system809_1can toggle the gate voltage between about −5V (pinch off or turn off) and about −2.5V (saturation or turn on) at a frequency greater than or equal to 1 kHz and less than or equal to about 500 MHz. As another example, the gate voltage can be toggled between pinch off and saturation at a rate greater than or equal to about 10 MHz and less than or equal to about 100 MHz. Without any loss of generality, the power management system809_1can be configured to turn-on and turn-off the amplifier in between pulses of a pulsed waveform. This can advantageously allow heat to dissipate from the amplifier in between pulses thereby reducing the rate at which the amplifier heats up and increase lifetime. Turning on and off the amplifier in between pulses of a pulsed waveform can also advantageously increase the power efficiency of the amplifier.

The control system815can be configured to control and/or manage various functions and processes of the power management system809_1. For example, the control system815independently or in co-operation with the computer102and/or the RF generator103can control the order in which the voltage and current levels at various terminals of the amplifier are changed to power up/down the amplifier. As another example, the control system815independently or in co-operation with the computer102and/or the RF generator103can control the raising and lowering of the voltage/current levels at the gate terminal of the amplifier synchronously with the incoming signal to be amplified. As yet another example, the control system815independently or in co-operation with the computer102and/or the RF generator103can control the timing of turning on the various amplifiers in the amplifier chains104_1to104_N.

As discussed above, the power management system809_1can be configured to use the information about the signal to be amplified to adjust/tune bias voltages and currents that power up/down one or more amplifiers in the amplifier chain104_1to improve various figures of merit (e.g., power efficiency, linearity, etc.).FIG.8Cis a schematic illustration of an amplifier828in the amplifier chain104_1that is being controlled by the power management system809_1. The amplifier828is a FET amplifier having a gate terminal830and a drain terminal832. As discussed above, the power management system809_1is configured to provide voltage/current to the gate terminal830and the drain terminal832of the amplifier as well as adjust the voltage/current levels at the gate terminal830and the drain terminal832based on information regarding the incoming signal and/or information regarding the temperature and other physical characteristics of the amplifier828.

The signal to be amplified can be input to the gate terminal830via an input matching circuit834. The amplified signal can be output from the drain terminal832via an output matching circuit836. To ease the burden on the power adapting system823, one or more storage capacitors838are placed near the drain terminal832of the amplifier828. The illustrated implementation comprises a single storage capacitor838. The storage capacitors can have a capacitance value between about 700 microfarads and 2000 microfarads. The presence of the storage capacitors838are advantageous in high power applications and/or applications in which the signal has a high duty cycle. In implementations comprising a plurality of capacitors, the plurality of capacitors can be arranged in parallel. As discussed above, the power management system809_1comprises a plurality of current sensors840and842that are configured to sense/monitor drain and gate current respectively. The current sensor840configured to monitor/sense drain current can be positioned downstream of the storage capacitor838as shown in the illustrated embodiment or upstream of the storage capacitor838in other embodiments. As discussed above, the power management system809_1can also comprise a temperature sensor844configured to sense/monitor the ambient temperature in the vicinity of the amplifier828. For example, the temperature sensor844can be configured to measure the temperature of the circuit board on which the amplifier828is mounted.

In various implementations, the power management system809_1can be configured to protect the amplifiers from damage. The power management system809_1can be configured to monitor voltages and/or currents at various terminals of the amplifier and turn-off the amplifier if the current and/or voltage at one or more terminals of the amplifier exceeds a certain limit. For example, the power management system809_1can be configured to turn off an amplifier in the amplifier chain104_1if the drain current of that amplifier exceeds a preset threshold. The threshold drain current for the various amplifiers controlled by the power management system809_1can be programmed and stored in a memory accessible by the power management system809_1. The threshold drain current can be different when the RF signal is on and off. As another example, the power management system809_1is configured to turn-off the amplifier if the rate of increase of the drain current of an amplifier during power up sequence is below a threshold rate. The threshold rate of increase of the drain current for the various amplifiers controlled by the power management system809_1can be programmed and stored in a memory accessible by the power management system809_1. In various implementations, the power management system809_1can be configured to monitor the duration of time an amplifier is on and turn off the amplifier if an amplifier is on for an amount time greater than a preset amount of time even if the RF signal is on. The preset amount of time can be programmed and stored in a memory accessible by the power management system809_1. In various implementations, an input switch can be provided in the input signal path of the amplifier. In such implementations, the power management system809_1can be configured to open the input switch and disconnect the RF signal from the input to the amplifier if the voltage, current and/or duration of time the amplifier is on exceeds a limit. In various implementations, a load switch can be provided in the drain path of the amplifier. In such implementations, the load switch can be opened to disconnect the drain and prevent damage to the amplifier if the drain current exceeds a limit.

The bias voltage/current of an amplifier (e.g., a GaN power amplifier) that optimizes the power efficiency of amplifier can vary based on the device temperature. Thus, the power efficiency of an amplifier can degrade from an optimum power efficiency as the temperature of the amplifier changes. Without relying on any particular theory, the temperature of the amplifier can increase over the duration of time that the amplifier is in use. Thus, it is advantageous to intermittently obtain a measurement/estimate of the temperature of the amplifier during use and adjust the bias voltage/current to optimize power efficiency and/or other figures of merit of the amplifier. The bias voltage/current that optimizes power efficiency can also be affected due to degradation in the device performance due to defects during manufacturing, aging or a defect in the circuitry surrounding the amplifier.

While the temperature sensor844inFIG.8Cmay provide information regarding the ambient temperature around the amplifier828. In many implementations, it may not be practical to use a temperature sensor to obtain an estimate of the device temperature of the amplifier828. However, the drain current can be correlated to the device temperature of the amplifier828and can be used to measure the device temperature of the amplifier828.FIG.9illustrates the correlation between the drain current and the device temperature for an implementation of a FET amplifier. InFIG.9, the embodiment of the FET amplifier is biased at a gate voltage of −2.763V and the drain current changes from about a few milliamps to about 225 milliamps as the temperature of the embodiment of the FET amplifier rises from about 40 degrees Celsius to about 100 degrees Celsius. The variation of the drain current versus temperature can be different when the biasing gate voltage is changed.

The drain current can also provide an indication of a degradation in the performance of the amplifier828as a result of defects due to manufacturing/aging or a defect in the circuitry surrounding the amplifier. Thus, adjusting the biasing voltages/currents based on measuring the drain current can advantageously aid in optimizing power efficiency and other figures of merit of the amplifier828. The drain current can be obtained under bias condition when the signal to be amplified is absent, when the signal to be amplified is present and/or in between signal pulses. For example, in some implementations, the sensor840can be configured to sense the drain current continuously or almost continuously. As discussed above, analog-to-digital converters in the power management system809_1sample the sensed current. A measurement of the drain current is obtained by averaging over a plurality of samples of the sensed current. The electronic processing system811can be configured to correlate the measured drain current to the device temperature of the amplifier828. The electronic processing system811can be configured to correlate the measured drain current to the device temperature of the amplifier828using algorithms and/or look-up-tables (LUTs).

As the device temperature of the amplifier828changes the drain current also changes as discussed with reference toFIG.9. To achieve the desired output power level, efficiency and other metrics, the electronic processing system811of the power management system809_1is configured to adjust the gate bias voltage of the amplifier as the temperature changes to maintain the threshold amount of drain current through the amplifier. The electronic processing system811can be configured to obtain the amount by which the gate voltage should be changed (also referred to herein as gate offset voltage) using algorithms and/or look-up-tables (LUTs). The gate offset voltage can be in a range between about 1 mV and about 500 mV. In various implementations, the signal to be amplified is turned off before changing the gate voltage by the offset amount. In some implementations wherein the signal to be amplified comprises pulses, the gate voltage is changed by the offset amount in the time interval between pulses. In some implementations, the gate voltage is changed by the offset amount when the signal to be amplified is on.

In addition to optimizing power efficiency based on device temperature and/or achieving a desired power efficiency at different temperatures, the power management system809_1can also help in preventing a rapid increase in the device temperature by adjusting the gate bias voltage as the drain current changes to maintain an optimal gain and/or power efficiency. This is discussed in further detail with reference toFIG.10. An implementation of an amplifier controlled by the power management system809_1is operated in two modes. In both the operating modes, the bias voltage to the gate terminal of the amplifier is turned on a short time before a RF signal is input to the amplifier and turned off a short time after the RF signal is turned off. For example, the gate bias voltage can be turned on/off at a duty cycle of 1%. However, in the first operating mode the gate bias voltage is maintained at a constant voltage, while in the second operating condition the gate bias voltage is changed to maintain the drain current at the threshold amount. The effect of changing the gate bias voltage to maintain the threshold amount of drain current not only increases/maximizes the gain provided by the amplifier over time but also prevents a rapid increase in the temperature of the amplifier over time. This is illustrated inFIG.10which shows a curve1002exhibiting a rapid rise in the temperature of an amplifier over time when operated in the first operating mode and a curve1004exhibiting a gradual rise in the device temperature of an amplifier over time when operated in the second operating mode. As noted from curve1002, the temperature of the amplifier can increase from about 22 degrees Celsius to about 48 degrees Celsius in less than 500 seconds when the amplifier is operated in the first operating mode. In contrast, the temperature of the amplifier increases gradually from about 22 degrees Celsius to about 32 degrees Celsius in about 3000 seconds when the amplifier is operated in the second operating mode. Accordingly, systems including amplifiers controlled by a power management system809_1that is configured to turn on/off the amplifier based on the presence/absence of the signal to be amplified as well as adjust the gate bias voltage based on the monitored drain current can operate efficiently and/or provide nearly constant gain at a wide range of temperatures (e.g., between about −20 degrees Celsius and about 90 degrees Celsius). In various implementations, by adjusting the gate bias voltage based on monitored drain current can maintain substantially constant power efficiency across a range of temperatures between about −20 degrees Celsius and about 90 degrees Celsius. For example, by adjusting the gate bias voltage based on monitored drain current the power efficiency can be maintained to be within ±10% of a desired value for temperatures between −20 degrees Celsius and about 90 degrees Celsius. The desired power efficiency value can be in a range between 40% and 75%. Such systems can also operate without the need for large and/or expensive cooling systems. In fact, many systems including amplifiers controlled by a power management system809_1that is configured to turn on/off the amplifier based on the presence/absence of the signal to be amplified as well as adjust the gate bias voltage based on the monitored drain current can function without any cooling systems, such as for example, electrical or electro-mechanical cooling systems.

Another advantage of synchronizing the turning on/off the bias voltage to the gate terminal with the turning on/off the input signal is an increase in power efficiency. As discussed above, a storage capacitor838may be provided near the drain terminal of the amplifier828in various implementations. Depending on the pulse width and duty cycle requirements, the storage capacitor838can have a large capacitance value (e.g., between 700 μF and 2000 μF). If the drain current is turned on/off synchronously with the input signal, a large amount of energy is required to charge the storage capacitor838as shown inFIG.11A. In contrast, the capacitors near the gate terminal have lower capacitance values and the energy required to charge those capacitors can be between 10-20 times lower than the energy required to charge the storage capacitor838as shown inFIG.11B. Accordingly turning on/off the gate bias voltage (referred to herein as gate switching) instead of modulating the drain current/voltage (referred to herein as drain switching) can advantageously increase power efficiency of the amplifier.

FIG.12illustrates a flow chart of operations performed by the power management system809_1. The drain and/or gate current from the amplifier can be monitored as shown in block1204. As discussed above, the drain and/or gate current can be monitored using the sensing system821. The drain and/or gate current can be sensed continuously or intermittently (e.g., periodically). As discussed above, the sensed current can be sampled and averaged to obtain a measurement of the current. The current can be correlated to a temperature as discussed above. In various implementations, a range for the drain and/or gate current defined by an upper current threshold value and a lower current threshold value can be provided for various gate bias voltages. For a given gate bias voltage, the power efficiency of the amplifier is optimized if the drain and/or gate current is within the provided current range. Accordingly, if the measured current is different from a threshold value (upper current threshold or lower current threshold) as shown in block1206, then the gate bias voltage can be changed as shown in block1208. The power management system809_1can change the gate bias voltage when the incoming signal is turned off or in-between pulses of the incoming signal. Otherwise, the operation can continue as shown in block1210.

FIG.13illustrates a process implemented by the smart slave circuit309_1or309_2. A reset command is received to commence an initialization operation1300. The digital-to-analog converter is initialized1302. That is, the voltage range of DAC413is set to appropriate output values for an amplifier being controlled, such as +/−5V.

Once the DAC voltage is set, an idle state is entered1304. The idle state is maintained until a tune command is received. A tune command invokes a DAC prepare state1306, where the voltage is set to a specified level, such as −5V. A sensor calibration state1308is then entered. In one embodiment, the sensor is calibrated for a 0 amp voltage offset. The offset is subtracted from all incoming samples at the analog-to-digital converter interface that can receive the current sense signal from current sensor415. If the offset is less than a threshold, an error state1312is entered. Otherwise, a tune state1310is entered. In this state, a new bias voltage (Vg) is used to direct the current sense signal to the desired value. If the DAC is maxed out, the error state1312is entered. Otherwise, a completion state1314is entered to determine whether processing should return to state1306to try to obtain an improved current sense signal.

The operations ofFIG.13may be substituted with other approaches to establish an optimal current range. For example, the current range can be experimentally tested ahead of time and manually programmed or hard coded into the system. The system can also use machine learning or artificial intelligence techniques to find the optimal current. In other embodiments, signals are fed back into the tuning algorithm instead of just the current. Other signals include the RF output signal421. A coupler (e.g.,313inFIG.3) can be used to determine the RF output level. For example, a bias voltage may be applied, a test RF signal is sent, which is read through the coupler into the RF signal generator103. This procedure is repeated until an optimal saturated RF power output value is obtained. Different optimization criteria are available, such as optimize for power out, such as to achieve 3 dB into power amplifier saturation. Another criterion is to optimize for linearity, such that the RF power is in the linear range. In one embodiment, a pre-programmed voltage bias is used and then 10 mV adjustments above and below the pre-programmed voltage are used until the optimal voltage is achieved.

The RF output power can be tracked by coupler313. This information is relayed to the power management system809_1. As the RF power out for a given bias voltage or current for a given bias voltage starts to drop, the power management system809_1recognizes that the amplifier is degrading. The amount of degradation is mapped to the lifetime of the amplifier. Reports on amplifier state are periodically issued by the power management system809_1.

The power management system809_1can include instructions executed by electronic processing system811to render to display device the state of the various amplifiers being controlled by the power management system809_1.FIG.14illustrates the display of a display device showing the health of a system comprising, for instance, 144 amplifiers arranged in twelve columns and twelve rows. Each amplifier is represented by a circle1402. A printed circuit board or power supply board is associated with each column, as represented by a square1404. Indicia is provided to characterize the operational state of each element. For example, a down arrow or color red may represent a failed state. Side arrows or amber color may represent a state transition. An up arrow or color green may represent a healthy state. Absent indicia may represent an off state.

Various embodiments described herein maintain amplifier health in a number of ways. For example, as discussed above, the power management system809_1may enforce a limit on the bias voltage, drain current, duration of time the amplifier is turned on. Additionally, the measured characteristics (e.g., drain current/voltage, gate current/voltage, etc.) of the amplifier received by the power management system809_1can be analyzed to identify changes/degradation in the performance of the amplifier. Pre-emptive maintenance/repairs can be performed on the amplifier and the driving circuitry on the basis of the identified changes/degradation in the performance.

Dynamic Gate Biasing of RF Amplifier

Various applications comprising RF amplifiers may require optimizing/maximizing multiple figures of merit. The multiple figures of merit can include reliability, power efficiency, output power, linearity, bandwidth, signal-to-noise ratio, and temperature. Depending on the application, one or more of these figures of merit can be maximized or a pareto optimization of these figures of merit can be achieved. Pareto optimization refers to a situation in which no individual figure of merit can be improved without degrading at least one other figure of merit. The bias voltage provided to the amplifier can affect linearity, power efficiency and output power of the amplifier. The input signal power can affect the spurious-free dynamic range (SFDR) and linearity of the amplifier. Accordingly, various implementations of the power management system809_1described above can be configured to adjust the biasing power of the amplifier to optimize multiple figures of merit based on a user specification or a desired application. In various implementations, the power management system809_1can be configured to provide feedback to the RF signal generator103and/or the computer102that can be used to change/alter the characteristics of the input signal (e.g., input power, carrier frequency, waveform type, modulation, pulse width, duty cycle, etc.) to maximize/pareto optimize one or more figures of merit.

In various implementations, the power management system809_1in cooperation with the computer102and/or the RF signal generator103can be configured to adjust the bias voltages/currents provided to the amplifiers in the amplifier chain104_1and/or the power of the RF signal input to the amplifier to optimize linearity, output power and/or signal-to-noise ration of the RF signal output from the amplifiers in the amplifier chain104_1. The optimization methods and systems can be implemented for RF signals over a broad range of frequencies and waveform characteristics as well as over a wide range of temperature of the amplifier. Additionally, the power management system809_1in cooperation with the computer102and/or the RF signal generator103can be configured to adjust the bias voltages/currents provided to the amplifiers in the amplifier chain104_1and/or the power of the RF signal input to the amplifier to reduce damage and/or to prevent failure of one or more amplifiers in the amplifier chain104_1. Further, the power management system809_1in cooperation with the computer102and/or the RF signal generator103can be configured to adjust the gain bias voltage provided to the gate terminal of the amplifier in the amplifier chain104_1to optimize power efficiency and/or power of the RF signal output from the amplifiers in the amplifier chain104_1for different temperatures. Machine learning (ML) techniques/algorithms can be used to determine the bias voltages/currents, and/or the power levels and waveform characteristics of the input signal that would optimize output power and/or power efficiency over a range of frequencies and/or temperatures.

As discussed in further detail below, the power management system809_1in cooperation with the computer102and/or the RF signal generator103can be configured to dynamically adjust the bias voltages/currents and/or characteristics of the input RF signal (e.g., frequency, pulse width, duty cycle, power level, etc.) to maximize/optimize linearity of the amplifier. The power management system809_1in cooperation with the computer102and/or the RF signal generator103can be configured to dynamically adjust the bias voltages/currents and/or characteristics of the input RF signal (e.g., frequency, pulse width, duty cycle, power level, etc.) to maximize/optimize power efficiency of the amplifier. Machine learning (ML) techniques/algorithms can be used to determine the bias voltages/currents and/or characteristics of the input RF signal that would optimize linearity and/or power efficiency.

FIG.15schematically illustrates an implementation of a power management system1501that is configured to dynamically adjust the bias power provided to an implementation of an amplifier1511. The amplifier1511can be a FET amplifier (e.g., a HEMT transistor). The power management system1501can be similar to the power management system809_1discussed above. Accordingly, the power management system1501can share all or many of the architectural/functional/operational characteristics of the power management system809_1discussed above. The power management system1501comprises a control system1503, an electronic processing system1505configured to execute machine learning algorithms, a drain bias voltage/current sensor and modulator module1507, and a gate bias voltage/current sensor and modulator module1509. In various implementations, the drain bias voltage/current sensor and modulator module1507and the gate bias voltage/current sensor and modulator module1509can be combined in a single module. In some implementations, the drain bias voltage/current sensor can be separate from the drain bias current/voltage modulator. Similarly, the gate bias voltage/current sensor can be separate from the gate bias current/voltage modulator in some implementations. The power management system1501can comprise other sensors (e.g., temperature sensor) as discussed above with reference toFIGS.8A-8C. In various implementations, the power management system1501can be configured to interface with a power distributing unit that is configured to convert power from a power source (e.g., AC power line, battery, generator, etc.) to voltages/currents required to bias the amplifier1511. In various implementations, the power management system1501can be configured to control the power distributing unit, as discussed above. The power distributing unit can be similar to the power adapting system823and/or the power distributor108. In various implementations, the power management system1501can be configured to communicate with components in the input signal path (e.g., RF signal generator103, amplifiers or other electrical components) to the amplifier1511through a master controller (e.g., computer102) and provide information that can be used to control characteristics of the input signal (e.g., frequency, waveform characteristics, input power level, pulse width, duty cycle, etc.). In various implementations, the power management system1501can be configured to directly communicate with and/or control components in the input signal path to vary characteristics of the input signal (e.g., frequency, waveform characteristics, input power level, pulse width, duty cycle, etc.).

The drain bias voltage/current sensor and modulator module1507is configured to (i) sense the drain current and voltage; and (ii) adjust the drain bias voltage and/or current of the amplifier1511. The gate bias voltage/current sensor and modulator module1509is configured to (i) sense the gate current and voltage; and (ii) adjust the gate bias voltage and/or current of the amplifier. Adjusting the gate bias voltage/current and/or the drain bias voltage/current can change output power, gain provided by the amplifier, efficiency, thermal performance and/or linearity of the amplifier1511. Without subscribing to any particular theory, linearity of the amplifier can be characterized by an amount of 3rd order intermodulation distortion (IMD3) and/or 5th order intermodulation distortion (IMD5). As discussed above, the drain current can be used to determine the temperature of the amplifier1511and/or the health of the amplifier1511. Accordingly, the power management system1501can be used to check the health of the amplifier1511and preventive maintenance can be performed on the amplifier by changing the gate bias voltage and/or drain bias voltage in case there's a degradation in the health of the amplifier. In some implementations, the power management system1501can be configured to provide warnings regarding the health of the amplifier which can be used to replace systems/devices with failing amplifiers.

Various implementations of the power management system1501can be configured to store the values of the sensed current and voltage at the gate and drain terminals and temperature in corresponding registers from where they can be read through digital interface. In various implementations, the current, voltage and temperature values stored in the registers can be obtained by averaging over multiple current, voltage and temperature values.

As discussed above, the power management system1501can be configured to dynamically adjust (or modulate) the bias voltage/current provided to the gate and the drain terminals of the amplifier1511based on sensed voltages/currents at various terminals of the amplifier and/or characteristics of the input signal or output signal to maximize/pareto optimize one or more figures of merit including but not limited to linearity, power efficiency, and output power. Without relying on any particular theory, the output power of the amplifier1511will reach a maximum value at a certain value of gate bias voltage, drain bias voltage and input power level. Any further increase in the input power level, the gate bias voltage or the drain bias voltage/current will not increase the output power beyond the maximum value. This operating state is referred to as saturation. The efficiency of the amplifier1511is also maximum when the amplifier1511is operated close to saturation. However, the linearity of the amplifier may decrease when the amplifier is operated close to saturation. This is depicted inFIG.16which shows the variation in the amount of two-tone 3rd order intermodulation distortion (IMD3) as a function of drain efficiency for an implementation of the amplifier1511. Without any loss of generality, the increase in efficiency is obtained by increasing the bias voltage at the gate terminal and/or the bias voltage at the drain terminal of the amplifier1511.

InFIG.16, curve1601shows the variation in the amount of two-tone 3rd order intermodulation distortion (IMD3) as a function of drain efficiency for a first input power level and a first bias voltage level provided to the gate terminal which results in an output power of 50 dBm. InFIG.16, curve1603shows the variation in the amount of two-tone 3rd order intermodulation distortion (IMD3) as a function of drain efficiency for a second input power level and a second bias voltage level provided to the gate terminal which results in an output power of 55 dBm. InFIG.16, curve1605shows the variation in the amount of two-tone 3rd order intermodulation distortion (IMD3) as a function of drain efficiency for a third input power level and a third bias voltage level provided to the gate terminal which results in an output power of 60 dBm. The second bias voltage level is greater than the first bias voltage level and the third bias voltage level is greater than the second bias voltage level. At the third bias voltage level, the implementation of the amplifier1511is operated close to saturation. It is noted fromFIG.16that when operated close to saturation, the efficiency of the implementation of the amplifier1511is greater than the efficiency when operated at the first or second bias voltage level. However, at the third bias voltage level the amount of two-tone 3rd order intermodulation distortion (IMD3) is also greater than the amount of two-tone 3rd order intermodulation distortion (IMD3) when operated in the first or second bias voltage level. A higher amount of two-tone 3rd order intermodulation distortion (IMD3) corresponds to an increase in non-linearity. Accordingly, by adjusting the bias voltage level at the gate terminal and/or the power level of the input signal, the linearity of the amplifier can be improved. Without any loss of generality, adjusting the bias voltage provided to the drain terminal and/or the power level of the input signal can also affect linearity of the amplifier.

It is further noted fromFIG.16, that for a given output power lower than the saturated output power, a small sacrifice in the efficiency can provide a marked reduction in the amount of two-tone 3rd order intermodulation distortion (IMD3). For example, with reference to curve1603, the amount of two-tone 3rd order intermodulation distortion (IMD3) decreases from about −30 dBc at an efficiency of about 0.35 to −42 dBc at an efficiency of about 0.34. Thus, efficiency and linearity can be optimized by adjusting the bias voltage/current levels at the gate and/or drain terminals of the amplifier. In the illustrated implementation the input power level and the bias voltage/current levels can be adjusted to operate the amplifier1511near the dip in the curve1603designated by point A to pareto optimize efficiency and linearity.

Based on a specification from a user or requirements of an application, the power management system1501can be configured to modulate the bias voltage/current levels at the gate and/or drain terminals to change the amount of power output from the amplifier1511, the degree of linearity (as indicated by the amount of IMD3) and the efficiency of the amplifier1511. This is further explained with reference toFIG.16. The power management system1501can be configured to set the bias voltage/current level at the gate and/or drain terminals to a first setting such that the output power of the amplifier1511is below the maximum output power. For example, the amplifier1511can be configured to operate at/near point A of curve1603or at/near point B of curve1601when biased at the first setting. In this setting, the amount of IMD3 is close to a minimum resulting in an increase in the linearity of the amplifier1511. The power management system1501can change the bias voltage/current level at the gate and/or drain terminals to a second setting such that the output power of the amplifier1511, the efficiency and/or the degree of linearity is changed. For example, the amplifier1511can be configured to operate at/near point C of curve1603or at/near point D of curve1601. Although the amplifier1511is configured to operate in the linear regime when biased at the second setting, the amount of IMD3 is not reduced to the lowest possible value for that output power. The power management system1501can be further configured to change the bias voltage/current level at the gate and/or drain terminals to a third setting such that the amplifier is configured to output the maximum possible output power. In this setting, the amplifier is operated at or near saturation, such as for example along the curve1605. In this setting, the amplifier is configured to operate in the non-linear regime.

The power management system1501can be configured to change the bias current/voltage levels at the gate and/or drain terminals instantaneously or sufficiently instantaneously. For example, the time taken to switch the bias current/voltage levels from the first setting to the second or third setting can be in the range from a few nanoseconds to a few milliseconds. The power management system1501can be configured to change the Dbias current/voltage levels to change the operating state of the amplifier1511to points along the curve1601/1603or to points between curves1601,1603and1605.

Referring toFIG.17, curve1703is a power transfer curve that illustrates the variation of the output power of the amplifier1511with variation of the input power of the amplifier. As noted fromFIG.17, the variation of output power to the variation of input power is along the line1701or close to the line1701when the input power level is less than Pin-1indicating a linear relationship between the output power and the input power. The amplifier is considered to operate in a linear regime when the input power is below Pin-1. The output power starts to deviate from the line1701for input power greater than Pin-1indicating a non-linear relationship between the output power and the input power. The output power saturates at a level P2when the input power is greater than Pin-3. Any increase in power beyond Pin-3will not cause any further increase in the output power. The amplifier is considered to operate in the saturated regime for input power greater than Pin-3. The amplifier is considered to operate in the non-linear regime for input power between Pin-1and Pin-3. In addition to changing the bias voltage/current level at the gate and/or drain terminal of the amplifier, the power management system1501can provide feedback/instructions to change the power of the RF signal input to the amplifier to change the operating state of the amplifier smoothly along the curve1703from linear regime to non-linear regime to saturation regime. For instance, changing the operating state of the amplifier smoothly can involve making continuous transitions along the curve1703. This feature of the power management system1501can be advantageous as discussed below with reference toFIG.18.

Consider a RF system (e.g., an electromagnetic pulsed radiation system) comprising an amplifier1511controlled by the power management system1501. It may be desirable to operate the RF system in three different operating modes—a first radar mode, a second EMP mode, and a third communication mode. In the first mode, it may be advantageous to operate the amplifier1511in the non-linear regime. In the second mode, it may be advantageous to operate the amplifier1511in the saturation regime such that the output power is maximized. In the third mode, it may be advantageous to operate the amplifier1511in the linear regime. For such a system, the power management system1501can provide instructions/feedback to control the input power level to change the operating state of the amplifier1511between first, second and third mode. Additionally, the power management system1501can vary the bias voltage/current levels at the gate and drain terminals of the amplifier1511to improve linearity of the amplifier1511, the efficiency of the amplifier1511and/or other figures of metric discussed above.

FIG.18shows the variation of the power output from the amplifier1511with time for the three different operating modes. InFIG.18, the amplifier1511is configured to operate in the first mode between times t1and t2, t5and t6and t9and t10. In this mode, the output power from the amplifier1511is set to P1. The output power P1can have a value between P1max and P1min shown inFIG.17. The corresponding input power can have a value between Pin-1and Pin-2shown inFIG.17. The amplifier1511is configured to operate in the second mode between times t2and t3, t6and t7and t10and t11. In this mode, the output power from the amplifier1511is set to P2which is greater than P1. The corresponding input power can have a value greater than or equal to Pin-1. The amplifier1511is configured to operate in the third mode between times t3and t4, t7and t8and t11and t12. In this mode, the output power from the amplifier1511is set to P3which is lesser than P1. The output power P3can have a value less than P1min shown inFIG.17. The corresponding input power can have a value less than Pin-1. As discussed above, the bias voltage/current levels can be adjusted to optimize various figures of merit for each of the first, second and third operating modes. As shown inFIG.18, the time duration in each of the three operating modes as well as the duration of inactive time can be variable. The bias settings and/or input power level can be changed instantaneously or sufficiently instantaneously (e.g., in a range from about 1 nanosecond to about 1 millisecond) between the different operating modes.

The amplifier1511can be calibrated to determine the input power level and the bias voltage/current levels corresponding to the first, second and third operating modes. The determined bias voltage/current levels can be stored in a memory accessible to the power management system1501. The power management system1501can be configured to change the operating mode of the amplifier1511based on an input received from a user or a controller. In various implementations, the power management system1501can be configured to turn off the amplifier1511during periods of inactivity between times t4and t5, and t8and t9, as discussed above to improve thermal management. In addition to changing the bias current/voltage levels to change the operating mode of the amplifier1511, the power management system1501can be configured to modulate the bias voltage to the gate terminal in response to one or more sensed characteristic of the amplifier, such as, for example drain current to improve efficiency or thermal performance of the amplifier1511.

Further to helping in improving thermal performance of the amplifier, adjusting the gain bias voltage can also change the class of the amplifier1511. For example, changing the gate bias voltage can change the conduction angle which denotes the class of the amplifier. As the gate bias voltage increases, the conduction angle decreases from 360 degrees to 0 degrees corresponding to a change in amplifier class. The different classes of amplifier can include but not be limited to class A, class B, class AB, class C, class D, class E, class F, class G, class H, class S and class T. Accordingly, the power management system1501can be configured to change the amplifier class from one of class A, class AB, class B, class C, class D, class E, class F, class G, class H, class S and class T to another one of class A, class AB, class B, class C, class D, class E, class F, class G, class H, class S and class T. Adjusting the bias voltage/current level to the drain can optimize the efficiency of the amplifier1511for a particular class of amplifier.

The high power microwave systems described herein are capable of generating high electric field (e-field) strengths and effective radiated power (ERP) levels with minimal power and cooling infrastructure. Various systems described herein can generate electromagnetic pulsed radiation with pulses that can last up to a few milliseconds. In addition, the voltage requirements to operate the systems described herein can be much lower than the operating voltage requirements of other existing systems.

Long Range Charging

The high-power microwave systems described herein can be used to deliver power wirelessly. For example, the electromagnetic radiation generated by an implementation of the high-power microwave system described herein can be capable of charging batteries, such as, for example cellphone batteries, batteries of mobile radios, etc. The systems described herein are able to provide such charging capability due to the following characteristics: ability to provide Megawatts of radiated power; high power AC-to-DC circuits to convert electricity from power grids to DC power which allows implementation of Direct-Current (DC) approaches to charge batteries which can be much faster at charging than alternating current (AC) approaches; parallelized and digitally controlled power architectures that are able to take advantage of commercial components to keep prices and complexity low; highly efficient (greater than 95% power efficiency) components with sophisticated digital thermal management to manage power transfer of this magnitude without adverse thermal issues; and having real time current flow management which is advantageous in battery charging which is a non-linear phenomenon.

Various implementation of the systems configured to deliver wireless charging power comprise parallelized array of power supply boards (PSB) that take in AC voltage of up to 240 volts and convert to DC voltages using super capacitor banks and other novel circuits. Each of the PSBs in the parallelized array are connected to an intelligent power management master processor and software (e.g., the power management system809_1) using an interconnection network, so that the power levels of each of the PSBs can be managed, throttled and switched appropriately. The power management processor can comprise a multi-chip synchronization port to be completely scalable to an arbitrary large array of PSBs and thus arbitrarily large power levels. The power management processor can use real time machine intelligence to manage the flow of power through various switches (e.g., GaN-on-SiC solid state switches) in the system to achieve real time power management capability.

The intelligent power management master processor is unique in the industry with ability to sense current levels and voltages up to 700 Volts DC (VDC), above the 600 VDC standard the military uses. These high voltage sensors enable the intelligent power management master processor to get real time feedback from the voltage level and current flow from the GaN-on-SiC switches and optimize the power flow to the battery. Battery charging can be a non-linear where the start and end of the charging cycle can be slower as compared to the middle of the charging cycle which can be full-on at much faster rates, the intelligent power management master processor can help manage the charging rate of the battery as well as provide health and status feedback of the charging process. The intelligent power management master processor also has multiple built in safety features to ensure operator safety which is useful in these high voltage applications.

The systems described herein may be capable of delivering an electromagnetic charging beam with a 3 dB beam width greater than about 4 degrees, such as for example, greater than or equal to about 6 degrees and less than or equal to about 60 degrees. The charging beam may be capable to wirelessly charging electronics at a distance greater than or equal to about 1 meter and less than or equal to about 2 kilometers, such as, for example, range greater than or equal to 0.5 m and less than or equal to 10 m, greater than or equal to 5 m and less than or equal to 10 m, greater than or equal to 10 m and less than or equal to 100 m, greater than or equal to 100 m and less than or equal to 500 m, greater than or equal to 500 m and less than or equal to 1 km, greater than or equal to 1 km and less than or equal to 2 km, or any distance in a range defined by any of the numbers above.

In some implementations the systems described herein may be capable of transmitting RF signals in a diverse frequency range of interest. For example, system may be capable of transmitting signals in a wavelength range from about 20 MHz and about 20 GHz.

The long range charging system discussed herein relies on a high power radio frequency (RF) system configured to generate and transmit electromagnetic radiation wirelessly to a receiver system. The receiver system can comprise an antenna system configured to receive the radiated energy from the RF systems, a rectifier circuit configured to convert the received RF energy to DC power, and a power storage device which can be used to charge one or more devices.FIG.19illustrates an implementation of a receiver system1900that is configured to receive radiated energy wirelessly from a high power RF system or transmitter1905. The RF system1905can be similar to the systems100and700described above. The RF system1905is configured to radiate energy to the receiver system1900. The electromagnetic radiation transmitted by the RF system1905can be in a wavelength range between about 20 MHz and about 20 GHz. For example, the frequency of the energy radiated by the RF system1905can be in the SHF band, the UHF band, the L band, the S band, the Ka band, or the Ku band. The receiver system1900can be integrated with one or more devices (e.g., laptops, tablets, cell phones, mobile radios, etc.) that can be charged wirelessly by the high power RF system1905. Some implementations of the receiver system1900can comprise electrical ports or outlets to charge one or more devices. The one or more devices can include devices employed in residential, commercial or military applications.

Receiver system1900comprises a rectenna (rectifying antenna) system1902and a power storage system or device1904. Without any loss of generality, the rectenna system1902can comprise an antenna system configured to receive the radiated energy from the RF system1905and a rectifying circuit configured to convert the AC power at the output of the antenna system into DC power. The rectenna system1902can comprise additional electrical components such as for example, an amplifier (e.g., high power GaN amplifiers), a capacitor, diodes, switching circuits, impedence matching circuit, etc. connected internally or externally to the antenna system. As discussed above, the rectenna system1902converts the energy received from the high power RF transmitter1905to DC power and transmits the converted DC power to the power storage device1904. The power storage device1904can include battery system, switches, one or more capacitors, etc.

In various implementations, the rectenna system1902can comprise a loop antenna, a dipole antenna, helical antenna, dish antenna, parabolic antenna, a monopole antenna, foldable antenna, rod antenna, or other types of antennae. In various implementations, the antenna can have a low inductance, for example, about 0.2 μH. The antenna of the rectenna system1902can be a directional antenna with a gain factor greater than 1 or an omni directional antenna. In various implementations, the rectenna system1902can comprise an array of antennae connected to an array of corresponding rectifying circuits. In such implementations, the spacing between adjacent antenna of the array of antenna can be about λ/2, λ, 2λ, 5λ, or 10-20 times λ. The spacing between adjacent antennae of the antenna array can increase the amount of radiated energy from the transmitter1905that is captured by the rectenna system1902which can improve the power conversion efficiency of the long range charging system. In various implementations, the rectenna system1902can comprise a combination of antennas to receive radiated energy in different frequency bands, such as, for example, in low frequency range (3-300 KHz) or high frequency range (300 KHz-30 MHz) or very high frequency range (30-300 MHz) or ultra-high frequency range (300 MHz-3 GHz) or Super high frequency range (3-40 GHz), etc.

Without any loss of generality, the amount of DC power generated by the receiving system1900can depend on the gain of the antenna of the rectenna system1902, the distance of the receiving system1900from the transmitter1905, the size and geometry of the antenna of the rectenna system1902. Accordingly, the size and the geometry of the antenna of the rectenna system1902can be selected to deliver a desired amount of DC power to the power storage device1904. For example, when the transmitter1905is configured to radiate energy in the L-band, the rectenna system1902can be located at a distance of about 500 m from transmitter1905and comprise a small loop antenna having an area between about 4 square cm and about 60 square cm to generate DC power in a range from a few hundred milliWatts to a few Watts. As another example, when the transmitter1905is configured to radiate energy in the L-band, the rectenna system1902can be located at a distance of about 500 m from transmitter1905and comprise a dish antenna having a size between about 1 meter and about 5 meter to generate DC power in a range from a few tens of Watts to a few hundred Watts. In such implementations, the dish antenna can be configured to be foldable so as to make it portable. The dish antenna can be mounted on a tripod during operation.

Various implementations of the receiver system1900can be configured to be small in size and light weight such that it can be easily portable. The portable implementations of the receiver system can be easily carried by a user in a backpack to allow the user to wirelessly charge one or more devices on the go. In some implementations, the receiver system1900can comprise larger antennas that are mounted on vehicles.

The implementations of wireless charging system comprising the transmitter1905and the receiver system1900can be configured to provide sufficient wireless charging capacity to charge one or more devices. For example, the frequency, power and duty cycle of the radiated energy from the transmitter as well as the size and gain of the antenna of the rectenna system1902can be adjusted to generate DC power in a range from 100 milliwatts to about 150 Watts. The frequency, power and duty cycle of the radiated energy from the transmitter as well as the size and gain of the antenna of the rectenna system1902can be adjusted to achieve a wireless power conversion efficiency greater than or equal to about 70%. Without any loss of generality, the size and geometry of the antenna of the rectenna system1902depends on the frequency, power and duty cycle of the radiated energy from the transmitter1905. For example, as the duty cycle of the radiated energy beam from the transmitter1905increases, the size of the antenna of the rectenna system can decreases. The size and gain of the antenna can also depend on the frequency and beam width of the radiated energy from the transmitter1905. Depending of the application and the location of the transmitter1905and the receiver system1900, the power of the energy radiated from the transmitter1905can be configured to meet the limits set by FCC (federal communications commission).

The power management system809_1described above can be can be integrated with the receiver system1900. The power management system809_1can be configured to control the rate of charging of the power storage device1904as well as control the operation of the rectifying circuit to increase the efficiency with which the received power from the transmitter1905is converted to DC power and stored in the power storage device1904.

Various implementations of the receiver system1900can be configured to provide auxiliary power in systems that comprise a photovoltaic cell that is configured as the primary source of power. For example, the receiver system1900can be integrated with a solar blanket that comprises a photovoltaic cell as described further below with reference toFIG.20.

FIG.20illustrates an implementation of a receiver system2000configured to receive energy from transmitter1905(which can facilitate wireless charging) integrated with a photovoltaic device. The receiver system2000comprises one or more photovoltaic cell2002, DC/DC converter2010that is configured to convert the DC power generated by the photovoltaic (PV) cell to DC power levels required to charge a battery2018. The battery2018can comprise an array of cells, a capacitor bank or other power storage devices. The receiver system2000further comprises a sensing system2004configured to sense the power generated by the PV cell2002. The rectenna system1902described above can be integrated in the receiver system2000to provide additional power when the power from the PV cell isn't sufficient. A DC/DC converter2008can be configured to convert the DC power generated by the rectenna system1902to DC power levels required to charge the battery2018. A sensing system2006can be configured to sense the power generated by the rectenna system1902. A device2012can be used to direct the DC power generated by the PV cell2002and the rectenna system1902to the battery2018. The device2012can comprise a power combiner or a diplexer. An electronic control system2014can be configured to control the device2012based on output of the sensing systems2004and2006.

The receiver system2000can be configured as a solar blanket. When additional power is need, the transmitter1905can transmit high power electromagnetic radiation which is received by the rectenna system1902of the receiver system2000. The DC power generated by the rectenna can be used to recharge the battery2018which can be used to charge one or more devices, such as, for example, a laptop, a mobile phone, a radio, a tablet, etc.

Other Variations

Features, materials, characteristics, or groups described in conjunction with a particular aspect, embodiment, or example are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The protection is not restricted to the details of any foregoing embodiments. The protection extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made. Those skilled in the art will appreciate that in some embodiments, the actual steps taken in the processes disclosed and/or illustrated may differ from those shown in the figures. Depending on the embodiment, certain of the steps described above may be removed, others may be added. For example, the actual steps and/or order of steps taken in the disclosed processes may differ from those described and/or shown in the figure. Depending on the embodiment, certain of the steps described above may be removed, others may be added. For instance, the various components illustrated in the figures and/or described may be implemented as software and/or firmware on a processor, controller, ASIC, FPGA, and/or dedicated hardware. Furthermore, the features and attributes of the specific embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure.

In some cases, there is provided a non-transitory computer readable medium storing instruction, which when executed by at least one computing or processing device, cause performing any of the methods as generally shown or described herein and equivalents thereof.

Any of the memory components described herein can include volatile memory, such random-access memory (RAM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), double data rate (DDR) memory, static random-access memory (SRAM), other volatile memory, or any combination thereof. Any of the memory components described herein can include non-volatile memory, such as magnetic storage, flash integrated circuits, read only memory (ROM), Chalcogenide random access memory (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, or any combination thereof), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), other discrete NVM (non-volatile memory) chips, or any combination thereof.

Any user interface screens illustrated and described herein can include additional and/or alternative components. These components can include menus, lists, buttons, text boxes, labels, radio buttons, scroll bars, sliders, checkboxes, combo boxes, status bars, dialog boxes, windows, and the like. User interface screens can include additional and/or alternative information. Components can be arranged, grouped, displayed in any suitable order.

Conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or steps. Thus, such conditional language is not generally intended to imply that features, elements and/or steps are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without other input or prompting, whether these features, elements and/or steps are included or are to be performed in any particular embodiment. The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. Also, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list.

Disjunctive language such as the phrase “at least one of X, Y, Z,” unless specifically stated otherwise, is otherwise understood with the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present.

Language of degree used herein, such as the terms “approximately,” “about,” “generally,” and “substantially” as used herein represent a value, amount, or characteristic close to the stated value, amount, or characteristic that still performs a desired function or achieves a desired result. For example, the terms “approximately”, “about”, “generally,” and “substantially” may refer to an amount that is within less than 10% of, within less than 5% of, within less than 1% of, within less than 0.1% of, or within less than 0.01% of the stated amount.

Unless otherwise explicitly stated, articles such as “a” or “an” should generally be interpreted to include one or more described items. Accordingly, phrases such as “a device configured to” are intended to include one or more recited devices. Such one or more recited devices can also be collectively configured to carry out the stated recitations.

The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the disclosure. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the disclosed embodiments. Thus, the foregoing descriptions of specific embodiments are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed; obviously, many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, they thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the claims as presented herein or as presented in the future and their equivalents define the scope of the protection.