Patent ID: 12255184

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Semiconductor packages and methods of forming the same are disclosed, according to some embodiments. In particular, a first redistribution structure is formed having redistribution lines. A first via is formed extending from a surface of a first conductive feature. A second via is formed extending from a gap between a second and third conductive feature. The second via is longer than the first via. Conductive connectors, such as solder, are attached to the back side of the first redistribution structure. A first conductive connector is coupled to the first conductive feature, and is offset from the first via. As a result, an intermetallic compound (IMC) formed during reflow does not extend laterally to the first via. A second conductive connector is coupled to the second and third conductive features, and is aligned with the second via. As a result, when an IMC formed during reflow, copper is diffused from the second via, and not from the second and third conductive features. Avoiding diffusion of copper from the second and third conductive features may avoid delamination of seed layers used during formation of the vias.

FIGS.1through14are various views of intermediate steps during a process for forming a device package200, in accordance with some embodiments.FIGS.1through14are cross-sectional views. The device package200may be referred to as an integrated fan-out (InFO) package.

InFIG.1, the device package200is shown at an intermediate stage of processing including a release layer102formed on a carrier substrate100. A package region600for the formation of the device package200is illustrated. Although only one package region is shown, there may be many package regions formed.

The carrier substrate100may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate100may be a wafer, such that multiple packages can be formed on the carrier substrate100simultaneously. The release layer102may be formed of a polymer-based material, which may be removed along with the carrier substrate100from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer102is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer102may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer102may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate100, or may be the like. The top surface of the release layer102may be leveled and may have a high degree of coplanarity.

InFIG.2, a dielectric layer104is formed on the release layer102. The bottom surface of the dielectric layer104may be in contact with the top surface of the release layer102. In some embodiments, the dielectric layer104is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer104is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer104may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof.

InFIG.3, a seed layer106is formed over the dielectric layer104. In some embodiments, the seed layer106is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer106includes a titanium layer and a copper layer over the titanium layer. The seed layer106may be formed using, for example, PVD or the like.

InFIG.4, a metallization pattern108is formed over the dielectric layer104. A photo resist (not shown) is formed and patterned on the seed layer106. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern108. The patterning forms openings through the photo resist to expose the seed layer106. A conductive material is formed in the openings of the photo resist and on the exposed portions of the seed layer106. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may be a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. Then, the photo resist and portions of the seed layer106on which the conductive material is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer106are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer106and conductive material form the metallization pattern108.

The conductive features of the metallization pattern108may be referred to as redistribution layers or redistribution lines. The redistribution lines may not be formed to have a uniform width, and some of the redistribution lines may include multiple conductive features. First redistribution lines108A may each include a single conductive feature that will be electrically connected to devices of the device package200. Second redistribution lines108B may each include a plurality of conductive features that are separated by a gap110, and are electrically connected together and to devices of the device package200. The combined width WB of the second redistribution lines108B may be substantially equal to the width WA of the first redistribution lines108A, or may be different.

In some embodiments, the conductive features of the second redistribution lines108B are formed separately during formation of the metallization pattern108, e.g., each conductive feature may correspond to an opening in the photo resist exposing the seed layer106. In some embodiments, a single conductive feature is formed during formation of the metallization pattern108, and the gaps110are formed afterwards using acceptable etching techniques to divide the single conductive feature into a plurality of conductive features. The gaps110are formed to have a width WG. The gaps110may extend from top surfaces of the second redistribution lines108B to bottom surfaces of the second redistribution lines108B such that the dielectric layer104is exposed. The gaps110may be formed in a center of the second redistribution lines108B such that the conductive features of the second redistribution lines108B are a same length, or may be formed offset from the center of the second redistribution lines108B such that the conductive features of the second redistribution lines108B are a different length.

InFIG.5, a dielectric layer112is formed on the metallization pattern108and the dielectric layer104. In some embodiments, the dielectric layer112is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the dielectric layer112is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer112may be formed by spin coating, lamination, CVD, the like, or a combination thereof.

The dielectric layer112is then patterned to form openings114to expose portions of the metallization pattern108. The patterning may be by an acceptable process, such as by exposing the dielectric layer112to light when the dielectric layer is a photo-sensitive material or by etching using, for example, an anisotropic etch. First openings114A are formed exposing the first redistribution lines108A, and second openings114B are formed exposing the second redistribution lines108B. The second openings114B are formed over the gaps110of the second redistribution lines108B; as such, sides of the conductive features are exposed, portions of the top surfaces of the conductive features are exposed, and portions of the dielectric layer104are exposed. In the illustrated embodiment, the first openings114A and second openings114B each have a same width WO. In other embodiments, the first openings114A and second openings114B have different widths. The width WOof the openings114is greater than the width WGof the gaps110.

The openings114may be formed over a center of each of the metallization patterns108, or may be formed offset from the center. In the embodiment shown, the first openings114A are formed offset from the centers of the metallization patterns108, and the second openings114B are formed over centers of the metallization patterns108.

The dielectric layers104and112and the metallization patterns108may be referred to as a back-side redistribution structure116. As illustrated, the back-side redistribution structure116includes the two dielectric layers104and112and one metallization pattern108. In other embodiments, the back-side redistribution structure116can include any number of dielectric layers, metallization patterns, and vias. One or more additional metallization patterns and dielectric layers may be formed in the back-side redistribution structure116by repeating the processes for forming the metallization patterns108and dielectric layer112. Vias may be formed during the formation of a metallization pattern by forming the seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer. The vias may therefore interconnect and electrically couple the various metallization patterns.

InFIG.6, a seed layer118is formed over the back-side redistribution structure116and in the openings114. The seed layer118is over the dielectric layer112, exposed portions of the metallization pattern108, and exposed portions of the dielectric layer104. In some embodiments, the seed layer118is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer118comprises a titanium layer and a copper layer over the titanium layer. The seed layer118may be formed using, for example, PVD or the like.

InFIG.7, a photo resist120is formed and patterned on the seed layer118. The photo resist120may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist120corresponds to through vias that will be subsequently formed. The patterning forms openings through the photo resist120to expose the seed layer118. The openings through the photo resist120are disposed over the openings114in the dielectric layer112, and may have a same width WPover both the first openings114A and second openings114B. The width WPof the openings is greater than the width WOof the openings114.

InFIG.8, a conductive material is formed in the openings of the photo resist120and on the exposed portions of the seed layer118. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may be a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. The photo resist120and portions of the seed layer118on which the conductive material is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer118are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form through vias122electrically connected to the redistribution lines.

Because the seed layer118is formed in the gaps110of the second redistribution lines108B, second vias122B are formed extending through the second redistribution lines108B. Conversely, first vias122A are formed on the first redistribution lines108A, and do not extend through the first redistribution lines108A. The first vias122A and second vias122B may both have the same width WPover the dielectric layer112, and the same width WOin the openings114. The second vias122B have also the width WGin the gaps110. Because the second vias122B have three different widths, each of a descending width, the second vias122B may be referred to as having a ladder structure. Because the first openings114A were formed offset from the centers of the metallization patterns108, the first vias122A are formed offset from the centers of the first redistribution lines108A.

Although the first vias122A are illustrated as having one change in widths, and the second vias122B are illustrated as having two changes in widths, it should be appreciated that the first vias122A and second vias122B may have any quantity of changes in widths in other embodiments. According to embodiments, the second vias122B have more changes in widths than the first vias122A.

InFIG.9, integrated circuit dies124are adhered to the dielectric layer112by an adhesive126. As illustrated inFIG.4, one integrated circuit die124is adhered in the package region600. In other embodiments, multiple integrated circuit dies124may be adhered in each region. The integrated circuit dies124may be bare dies, such as, logic dies (e.g., central processing unit, microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof. Also, in some embodiments, the integrated circuit dies124in the different package regions (now shown) may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, the integrated circuit dies124may be the same size (e.g., same heights and/or surface areas).

Before being adhered to the dielectric layer112, the integrated circuit dies124may be processed according to applicable manufacturing processes to form integrated circuits in the integrated circuit dies124. For example, the integrated circuit dies124each include a semiconductor substrate128, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate128and may be interconnected by interconnect structures130formed by, for example, metallization patterns in one or more dielectric layers on the semiconductor substrate128to form an integrated circuit.

The integrated circuit dies124further comprise pads132, such as aluminum pads, to which external connections are made. The pads132are on what may be referred to as respective active sides of the integrated circuit dies124. Passivation films134are on the integrated circuit dies124and on portions of the pads132. Openings are through the passivation films134to the pads132. Die connectors136, such as conductive pillars (for example, comprising a metal such as copper), are in the openings through the passivation films134and are mechanically and electrically coupled to the respective pads132. The die connectors136may be formed by, for example, plating, or the like. The die connectors136electrically couple the respective integrated circuits of the integrated circuit dies124.

A dielectric material138is on the active sides of the integrated circuit dies124, such as on the passivation films134and the die connectors136. The dielectric material138laterally encapsulates the die connectors136, and the dielectric material138is laterally coterminous with the respective integrated circuit dies124. The dielectric material138may be initially formed to bury or cover the die connectors136; when the die connectors136are buried, the top surface of the dielectric material138may have an uneven topology. The dielectric material138may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof, and may be formed, for example, by spin coating, lamination, CVD, or the like.

The adhesive126is on back-sides of the integrated circuit dies124and adheres the integrated circuit dies124to the back-side redistribution structure116, such as the dielectric layer112in the illustration. The adhesive126may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive126may be applied to a back-side of the integrated circuit dies124, such as to a back-side of the respective semiconductor wafer or may be applied over the surface of the carrier substrate100. The integrated circuit dies124may be singulated, such as by sawing or dicing, and adhered to the dielectric layer112by the adhesive126using, for example, a pick-and-place tool.

Although the integrated circuit dies124are illustrated and described above as being bare dies (e.g., unpackaged dies), in other embodiments, the integrated circuit dies124may be packaged chips (e.g., one or more bare dies integrated with other package features, such as, redistribution structures, passive devices, etc.). For example, the integrated circuit dies124may be a memory package (e.g., a hybrid memory cube) comprising a plurality of stacked and interconnected memory dies.

InFIG.10, an encapsulant140is formed on the various components. The encapsulant140may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. The encapsulant140may be formed over the carrier substrate100such that the die connectors136of the integrated circuit dies124and/or the through vias122are buried or covered. The encapsulant140is then cured.

InFIG.11, a planarization process is performed on the encapsulant140to expose the through vias122and the die connectors136. The planarization process may also grind the dielectric material138. Top surfaces of the through vias122, die connectors136, dielectric material138, and encapsulant140are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, the planarization may be omitted, for example, if the through vias122and die connectors136are already exposed. As noted above, the second vias122B extend through the metallization pattern108. As such, after the planarization process, the second vias122B are longer than the first vias122A when the first vias122A and the second vias122B are connected to a same metallization layer of the back-side redistribution structure116.

InFIG.12, a front-side redistribution structure142is formed on the encapsulant140, the through vias122, and the die connectors136. The front-side redistribution structure142includes multiple dielectric layers and metallization patterns. For example, the front-side redistribution structure142may be patterned as a plurality of discrete metallization patterns separated from each other by respective dielectric layer(s).

In some embodiments, the dielectric layers are formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, may be patterned using a lithography mask. In other embodiments, the dielectric layers are formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layers may be formed by spin coating, lamination, CVD, the like, or a combination thereof.

After formation, the dielectric layers are patterned to expose underlying conductive features. The bottom dielectric layer is patterned to expose portions of the through vias122and the die connectors136, and intermediate dielectric layer(s) are patterned to expose portions of underlying metallization patterns. The patterning may be by an acceptable process, such as by exposing the dielectrics layer to light when the dielectric layers are a photo-sensitive material, or by etching using, for example, an anisotropic etch. If the dielectric layers are photo-sensitive materials, the dielectric layers can be developed after the exposure.

Metallization patterns with vias are formed on each dielectric layer. A seed layer (not shown) is formed over the dielectric layer and in openings through the dielectric layer. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a deposition process, such as PVD or the like. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern. The patterning forms openings through the photo resist to expose the seed layer. A conductive material is formed in the openings of the photo resist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. Then, the photo resist and portions of the seed layer on which the conductive material is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern and vias for one metallization level of the front-side redistribution structure142.

The front-side redistribution structure142is shown as an example. More or fewer dielectric layers and metallization patterns than shown may be formed in the front-side redistribution structure142. One having ordinary skill in the art will readily understand which steps and processes would be omitted or repeated to form more or fewer dielectric layers and metallization patterns.

The top dielectric layer of the front-side redistribution structure142is patterned to expose portions of the metallization patterns for the formation of conductive pads. The conductive pads are used to couple to conductive connectors, and may be referred to as under bump metallurgies (UBMs)144. The patterning may be by an acceptable process, such as by exposing the top dielectric layer to light when the top dielectric layer is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the top dielectric layer is a photo-sensitive material, the top dielectric layer can be developed after the exposure. The UBMs144are then formed on the exterior side of the front-side redistribution structure142. The UBMs144are formed extending through openings in the top dielectric layer to contact the metallization layers of the front-side redistribution structure142.

As an example to form the UBMs144, a seed layer (not shown) is formed over the top dielectric layer and in openings through the top dielectric layer. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a deposition process, such as PVD or the like. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the pattern of the conductive pads in the front-side redistribution structure142. The patterning forms openings through the photo resist to expose the seed layer. A conductive material is formed in the openings of the photo resist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. Then, the photo resist and portions of the seed layer on which the conductive material is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the UBMs144.

Conductive connectors146are formed on the UBMs144. The conductive connectors146may be BGA connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors146may be formed of a metal or metal alloy, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors146are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors146are metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the UBMs144. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

InFIG.13, a carrier substrate de-bonding is performed to detach (de-bond) the carrier substrate100from the back-side redistribution structure116, e.g., the dielectric layer104. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer102so that the release layer102decomposes under the heat of the light and the carrier substrate100can be removed. The structure is then flipped over and placed on tape148.

Further inFIG.13, openings150are formed through the dielectric layer104to expose portions of the metallization pattern108. The openings may be formed, for example, using laser drilling, acceptable etching techniques, or the like. First openings150A are formed exposing the first redistribution lines108A, and second openings150B are formed exposing the second redistribution lines108B. The first openings150A are formed offset from centers of the first vias122A, such that the first openings150A are disposed a distance DOfrom portions of the first vias122A in the dielectric layer112. The second openings150B are formed centered under the second vias122B such that the seed layer118and portions of the seed layer106extending through the second redistribution lines108B are exposed.

InFIG.14, portions of the seed layers106and118exposed by the openings150are thinned or completely removed. The exposed portions of the seed layers106and118may be thinned or removed by an acceptable etching process, such as by wet or dry etching. In embodiments where the seed layers106and118include multiple layers, the etching process may remove some or all of the exposed multiple layers. In embodiments where the seed layers106and118include a titanium layer over the dielectric layer104and a copper layer over the titanium layer, the etching process may remove the titanium layer and leave the copper layer intact, thereby thinning the layer. In such embodiments, the etching process is performed with one or more etchants that are selective to the titanium layer (e.g., that etch the titanium layer at a substantially higher rate than the copper layer). In other embodiments, the exposed portions of the seed layers106and118are completely removed (e.g., all layers are removed).

FIGS.15through18are various views of intermediate steps during a process for forming a package structure400, in accordance with some embodiments.FIGS.15through18are cross-sectional views. The package structure400may be referred to a package-on-package (PoP) structure.

InFIG.15, a device package300is bonded to the device package200. The device package300may be bonded to the device package200in each package region600. The device package300includes a substrate302and one or more stacked dies308(308A and308B) coupled to the substrate302. Although a singular stack of dies308(308A and308B) is illustrated, in other embodiments, a plurality of stacked dies308(each having one or more stacked dies) may be disposed side by side coupled to a same surface of the substrate302.

The substrate302may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate302may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate302is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used for substrate302.

The substrate302may include active and/or passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the device package300. The devices may be formed using any suitable methods.

The substrate302may also include metallization layers (not shown) and through vias306. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate302is substantially free of active and passive devices.

The substrate302may have bond pads303on a first side the substrate202to couple to the stacked dies308, and bond pads304on a second side of the substrate302, the second side being opposite the first side of the substrate302, to couple to the conductive connectors314. In some embodiments, the bond pads303and304are formed by forming recesses (not shown) into dielectric layers (not shown) on the first and second sides of the substrate302. The recesses may be formed to allow the bond pads303and304to be embedded into the dielectric layers. In other embodiments, the recesses are omitted as the bond pads303and304may be formed on the dielectric layer. In some embodiments, the bond pads303and304include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads303and304may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. The conductive material of the bond pads303and304may be copper, tungsten, aluminum, silver, gold, nickel, the like, or a combination thereof.

In an embodiment, the bond pads303and304are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. For example, the bond pads304may include a layer of titanium (not shown), a main copper portion304A, and a nickel finish304B. The nickel finish304B may improve the shelf life of the device package300, which may be particularly advantageous when the device package300is a memory device such as a DRAM module. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBMs303and304. Any suitable materials or layers of material that may be used for the UBMs303and304are fully intended to be included within the scope of the current application. In some embodiments, the through vias306extend through the substrate302and couple at least one bond pad303to at least one bond pad304.

In the illustrated embodiment, the stacked dies308are coupled to the substrate302by wire bonds310, although other connections may be used, such as conductive bumps. In an embodiment, the stacked dies308are stacked memory dies. For example, the stacked memory dies308may include low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules. As noted above, in such embodiments, the bond pads304may have a nickel finish304B.

In some embodiments, the stacked dies308and the wire bonds310may be encapsulated by a molding material312. The molding material312may be molded on the stacked dies308and the wire bonds310, for example, using compression molding. In some embodiments, the molding material312is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material312, wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof.

In some embodiments, the stacked dies308and the wire bonds310are buried in the molding material312, and after the curing of the molding material312, a planarization step, such as a grinding, is performed to remove excess portions of the molding material312and provide a substantially planar surface for the device package300.

After the device package300is formed, the device package300is mechanically and electrically bonded to the device package200by way of conductive connectors314, the bond pads304, and the metallization pattern108. In some embodiments, the stacked memory dies308are coupled to the integrated circuit dies124through the wire bonds310, bond pads303and304, through vias306, conductive connectors314, through vias122, and front-side redistribution structure142.

The conductive connectors314may be similar to the conductive connectors146described above and the description is not repeated herein, although the conductive connectors314and the conductive connectors146need not be the same. The conductive connectors314may be disposed on an opposing side of the substrate302as the stacked memory dies308. In some embodiments, a solder resist (not shown) may also be formed on the side of the substrate302opposing the stacked memory dies308. The conductive connectors314may be disposed in openings in the solder resist (not shown) to be electrically and mechanically coupled to conductive features (e.g., the bond pads304) in the substrate302. The solder resist may be used to protect areas of the substrate302from external damage.

In some embodiments, before bonding the conductive connectors314, the conductive connectors314are coated with a flux (not shown), such as a no-clean flux. The conductive connectors314may be dipped in the flux or the flux may be jetted onto the conductive connectors314. In another embodiment, the flux may be applied to the surfaces of the metallization patterns108.

In some embodiments, the conductive connectors314may have an optional epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the device package300is attached to the device package200. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors314.

Optionally, an underfill material316may be formed between the device packages200and300. In an embodiment, the underfill material316is a protective material used to cushion and support the device packages200and300from operational and environmental degradation, such as stresses caused by the generation of heat during operation. The underfill material316may be injected or otherwise formed in the space between the device packages200and300and may, for example, be a liquid epoxy that is dispensed between the device packages200and300, and then cured to harden.

FIGS.16A,16B,16C, and16Dare detailed views of the conductive connectors314and metallization patterns108after a bonding process is performed to physically and electrically couple the device packages200and300. The bonding between the device packages200and300may be solder bonding. In an embodiment, the device package300is bonded to the device package200by a reflow process.FIGS.16A and16Bare, respectively, cross-sectional and plan views showing a connection for the first redistribution lines108A.FIGS.16C and16Dare, respectively, cross-sectional and plan views showing a connection for the second redistribution lines108B.

InFIGS.16A,16B,16C, and16D, the bonding process is performed to reflow the conductive connectors314such that they are in contact with the bond pads304and metallization patterns108. After the bonding process, an intermetallic compound (IMC)318may form at interfaces of the metallization patterns108and conductive connectors314. Because exposed portions of the seed layers106and118were partially or fully removed, the IMC318may extend partially or completely through the metallization patterns108. The IMC318may also extend laterally along the metallization patterns108a distance DIfrom sides of the first openings150.

The bonds formed by the bonding process include the conductive connectors314(e.g., solder) contacting two different metals. In an embodiment, the metallization patterns108are formed of copper, and the bond pads304have a nickel finish304B, resulting in nickel-solder-copper connections. When such connections are formed, copper diffuses from the metallization patterns108into the conductive connectors314and toward the nickel finish304B during reflow. A gradient of diffused copper is formed in the conductive connectors314, in the direction of the solid arrows. Excessive diffusion of copper from the metallization patterns108proximate the seed layers118may cause delamination of the seed layer118from the metallization patterns108. In particular, diffusion of copper from portions of the metallization patterns108between the seed layers118and the dielectric layer104may cause delamination of the seed layers118.

InFIGS.16A and16B, the first openings150A in the dielectric layer104are disposed laterally a distance DOfrom portions of the first vias122A in the dielectric layer112. As such, the conductive connectors314are disposed laterally the distance DOfrom sides of the first vias122A in a plan view, and are not disposed along the longitudinal axes of the first vias122A. The distance DOis chosen to be sufficiently large such that the IMC318A does not extend laterally to sides of the first vias122A. In other words, the distance DOis greater than the distance DI, and may be at least twice as large as the distance DI. In an embodiment, the distance DImay be from about 2 μm to about 13 μm, such as about 13 μm, and the distance DOmay be from about 25 μm to about 35 μm, such as about 35 μm. Forming the first openings150A (see, e.g.,FIG.13) such that the IMC318A does not extend laterally to sides of the first vias122A may avoid diffusion of copper from portions of the first redistribution lines108A between the seed layers118and the dielectric layer104, avoiding delamination of the seed layers118.

InFIGS.16C and16D, the second openings150B in the dielectric layer104are disposed laterally aligned with the gaps110in the second redistribution lines108B. As such, the conductive connectors314are not spaced laterally from sides of the second vias122B in a plan view, and are disposed along the longitudinal axes of the second vias122B. Because exposed portions of the seed layers106and118were partially or fully removed, the IMC318B extends in a longitudinal direction into the second vias122B. Forming the IMC318B such that it extends into the second vias122B may result in some diffused copper being sourced from the second vias122B, instead of the metallization patterns108. This may reduce the copper diffused from the metallization patterns108, avoiding delamination of the seed layers118, and also avoiding reduction of the thickness of the second redistribution lines108B.

As further shown, the metallization pattern108includes slots322disposed around the periphery of the conductive connectors314and the through vias122. The slots322provide stress relief, improving reliability of the electrical connections. In particular, the slots322provide additional sidewalls for the metallization patterns108, improving the adhesion between the metallization patterns108and polyimide materials such as the dielectric layer112. The slots322are disposed at least partially around the conductive connectors314in the first redistribution lines108A, and may be disposed completely around the conductive connectors314in the second redistribution lines108B.

InFIG.17, a singulation process320is performed by singulating along scribe line regions e.g., between adjacent package regions. In some embodiments, the singulation process320includes a sawing process, a laser process, or a combination thereof. The singulation process320singulates the package region600from adjacent package regions (not shown). The resulting package structure400is shown after singulation, which may be from the package region600.

FIG.18shows the package structure400after it is attached to a substrate500. The substrate500may be referred to a package substrate500. The package structure400is attached to the substrate500by mounting the device package200to the substrate500using the conductive connectors146.

The package substrate500may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the package substrate500may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate500is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for package substrate500.

The package substrate500may include active and passive devices (not shown. As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the package structure400. The devices may be formed using any suitable methods.

The package substrate500may also include metallization layers and vias (not shown) and bond pads502over the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate500is substantially free of active and passive devices.

In some embodiments, the conductive connectors146are reflowed to attach the device package200to the bond pads502. The conductive connectors146electrically and/or physically couple the package substrate500, including metallization layers in the package substrate500, to the device package200. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not illustrated) may be attached to the device package200(e.g., bonded to the bond pads502) prior to mounting on the package substrate500. In such embodiments, the passive devices may be bonded to a same surface of the device package200as the conductive connectors146.

The conductive connectors146may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the device package200is attached to the package substrate500. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors146. In some embodiments, an underfill (not shown) may be formed between the device package200and the package substrate500and surrounding the conductive connectors146. The underfill may be formed by a capillary flow process after the device package200is attached or may be formed by a suitable deposition method before the device package200is attached.

Embodiments may achieve advantages. Disposing the conductive connectors314laterally a sufficient distance DOfrom sides of the first vias122A in a plan view may avoid diffusion of copper from the metallization patterns108proximate the seed layers118. Forming the IMC318B such that it extends into the second vias122B may result in some diffused copper being sourced from the second vias122B, instead of the metallization patterns108. Reducing the amount of copper diffused from the metallization patterns108under the seed layers118may avoid delamination of the seed layers118, improving the reliability of resulting devices.

In accordance with some embodiments, a device includes: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.

In some embodiments, the device further includes: a second device package including a first bond pad and a second bond pad, the first conductive connector coupled to the first bond pad, the second conductive connector coupled to the second bond pad. In some embodiments, the first bond pad and the second bond pad have a nickel finish. In some embodiments, the first redistribution line and the second redistribution line are formed from copper. In some embodiments, the first redistribution structure further includes: a first dielectric layer, the first redistribution line and the second redistribution line disposed on the first dielectric layer; and a second dielectric layer on the first dielectric layer. In some embodiments, the second via is longer than the first via.

In accordance with some embodiments, a method includes: forming a first redistribution structure including: depositing a first dielectric layer over a carrier substrate; forming a first conductive feature on the first dielectric layer; forming a second conductive feature on the first dielectric layer; forming a third conductive feature on the first dielectric layer; and depositing a second dielectric layer on the first conductive feature, the second conductive feature, and the third conductive feature; forming a first via on the first conductive feature; forming a second via on the second conductive feature, on the third conductive feature, and between the second conductive feature and the third conductive feature; attaching a die to the first redistribution structure adjacent the first via and the second via; encapsulating the die, the first via, and the second via with an encapsulant; planarizing the encapsulant, the first via, and the second via; and forming a second redistribution structure over the encapsulant, the first via, the second via, and the die.

In some embodiments, the method further includes: debonding the carrier substrate from the first redistribution structure; and attaching a device package to the first redistribution structure, the device package attached to the first conductive feature with a first connector, the device package attached to the second conductive feature and the third conductive feature with a second connector. In some embodiments, the first connector is not disposed along a longitudinal axis of the first via. In some embodiments, the second connector is disposed along a longitudinal axis of the second via. In some embodiments, the first via is longer than the second via after the planarizing.

In accordance with some embodiments, a method includes: depositing a first seed layer on a first dielectric layer; plating a first conductive feature and a second conductive feature on the first seed layer; depositing a second dielectric layer on the first conductive feature and the second conductive feature; forming a first opening in the second dielectric layer, the first opening exposing the first conductive feature, the second conductive feature, and the first dielectric layer; depositing a second seed layer on the second dielectric layer and in the first opening; plating a first via from portions of the second seed layer in the first opening; attaching a die to the second dielectric layer; and encapsulating the first via and the die with an encapsulant.

In some embodiments, the method further includes: forming a second opening in the first dielectric layer, the second opening exposing the first seed layer and the second seed layer; forming a reflowable material in the second opening, the reflowable material disposed along a longitudinal axis of the first via; and reflowing the reflowable material to form an intermetallic compound from the reflowable material and conductive material of the first seed layer, the second seed layer, and the first via. In some embodiments, the method further includes: attaching a device package to the first conductive feature and the second conductive feature with the reflowable material. In some embodiments, reflowing the reflowable material includes diffusing portions of the conductive material of the first via into the reflowable material. In some embodiments, the method further includes: forming a third conductive feature on the first dielectric layer; depositing the second dielectric layer on the third conductive feature; forming a second opening in the second dielectric layer, the second opening exposing the third conductive feature; depositing the second seed layer in the second opening; and plating a second via from portions of the second seed layer in the second opening. In some embodiments, the method further includes: forming a third opening in the first dielectric layer, the third opening exposing the first seed layer; forming a reflowable material in the third opening, the reflowable material disposed along a different axis than a longitudinal axis of the second via; and reflowing the reflowable material to form an intermetallic compound from the reflowable material and conductive material of the first seed layer. In some embodiments, reflowing the reflowable material includes diffusing portions of the conductive material of the third conductive feature into the reflowable material. In some embodiments, no portion of the intermetallic compound is formed between the second via and the first dielectric layer. In some embodiments, the method further includes: planarizing the first via, the second via, and the encapsulant, the first via being longer than the second via after the planarizing.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.