Patent ID: 12262611

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to make the objectives, technical solutions, and advantages of embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, embodiments of the present disclosure. Under the condition of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments attainable by those ordinarily skilled in the art without involving any inventive effort are within the protection scope of the present disclosure.

Unless defined otherwise, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by those ordinarily skilled in the art to which the present disclosure belongs. The “first”, “second” and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The word “include” or “comprise”, and other similar words mean that a component or an article that precedes the word is inclusive of the component or article listed after the word and equivalents thereof, but does not exclude other components or articles. Similar words such as “connection” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that dimensions and shapes of various figures in the drawings are not to truly scale and are intended to be merely illustrative of the present disclosure. The same or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout.

As shown inFIG.1, a display panel provided by an embodiment of the present disclosure may include a base substrate1000, and a plurality of sub-pixels spx in a display region A1of the base substrate1000. Exemplarily, as shown inFIG.1andFIG.2A, at least one sub-pixel spx of the plurality of sub-pixels spx may include: a pixel driving circuit0121and a light emitting device0120. The pixel driving circuit0121has a transistor and a capacitor, and generates an electrical signal through the interaction between the transistor and the capacitor, and the generated electrical signal is input to a first electrode of the light emitting device0120. In addition, a corresponding voltage is applied to a second electrode of the light emitting device0120to drive the light emitting device0120to emit light.

As shown inFIG.2A, the pixel driving circuit0121may include: a driving control circuit0122, a first light emitting control circuit0123, a second light emitting control circuit0124, a data writing circuit0126, a storage circuit0127, a threshold compensation circuit0128, and a reset circuit0129.

The driving control circuit0122may include a control terminal, a first terminal and a second terminal. The driving control circuit0122is configured to provide the light emitting device0120with a driving current for driving the light emitting device0120to emit light. For example, the first light emitting control circuit0123is connected to the first terminal of the driving control circuit0122and a first power terminal VDD. The first light emitting control circuit0123is configured to realize on or off of connection between the driving control circuit0122and the first power terminal VDD.

The second light emitting control circuit0124is electrically connected to the second terminal of the driving control circuit0122and the first electrode of the light emitting device0120. The second light emitting control circuit0124is configured to realize on or off of connection between the driving control circuit0122and the light emitting device0120.

The data writing circuit0126is electrically connected to the first terminal of the driving control circuit0122. The second light emitting control circuit0124is configured to write a signal on a data line VD into the storage circuit0127under the control of a signal on a scanning line GA2.

The storage circuit0127is electrically connected to the control terminal of the driving control circuit0122and the first power terminal VDD. The storage circuit0127is configured to store a data signal.

The threshold compensation circuit0128is electrically connected to the control terminal and the second terminal of the driving control circuit0122. The threshold compensation circuit0128is configured to perform threshold compensation on the driving control circuit0122.

The reset circuit0129is electrically connected to the control terminal of the driving control circuit0122and the first electrode of the light emitting device0120. The reset circuit0129is configured to reset the control terminal of the driving control circuit0122and the first electrode of the light emitting device0120under the control of signals on a gate line GA1.

The light emitting device0120may be configured as an electroluminescent diode, such as at least one of an OLED or a QLED. The light emitting device0120may include the first electrode, a light emitting function layer, and the second electrode that are stacked. Exemplarily, the first electrode may be an anode, and the second electrode may be a cathode. The light emitting functional layer may include a light emitting layer. Further, the light emitting functional layer may also include film layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the light emitting device0120may be designed and determined according to the requirements of practical application environments, which is not limited herein.

Exemplarily, as shown inFIG.2A, the driving control circuit0122includes a driving transistor T1, the control terminal of the driving control circuit0122includes a gate of the driving transistor T1, the first terminal of the driving control circuit0122includes a first electrode of the driving transistor T1, and the second terminal of the driving control circuit0122includes a second electrode of the driving transistor T1.

Exemplarily, as shown inFIG.2A, the data writing circuit0126includes a data writing transistor T2. The storage circuit0127includes a storage capacitor CST. The threshold compensation circuit0128includes a threshold compensation transistor T3. The first light emitting control circuit0123includes a first light emitting control transistor T4. The second light emitting control circuit0124includes a second light emitting control transistor T5. The reset circuit0129includes a first reset transistor T6and a second reset transistor T7.

Specifically, a first electrode of the data writing transistor T2is electrically connected to the first electrode of the driving transistor T1, a second electrode of the data writing transistor T2is configured to be electrically connected to the data line VD to receive the data signal, and a gate of the writing transistor T2is configured to be electrically connected to a second scanning line GA2to receive a scanning signal.

A first electrode of the storage capacitor CST is electrically connected to the first power terminal VDD, and a second electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor T1.

A first electrode of the threshold compensation transistor T3is electrically connected to the second electrode of the driving transistor T1, a second electrode of the threshold compensation transistor T3is electrically connected to the gate of the driving transistor T1, and a gate of the threshold compensation transistor T3is configured to be electrically connected to a second scanning line GA2to receive a scanning signal.

A first electrode of the first reset transistor T6is configured to be electrically connected to a first reset signal line VINIT1to receive a first reset signal, a second electrode of the first reset transistor T6is electrically connected to the gate of the driving transistor T1, and a gate of the first reset transistor T6is configured to be electrically connected to a first scanning line GA1to receive a control signal.

A first electrode of the second reset transistor T7is configured to be electrically connected to a second reset signal line VINIT2to receive a second reset signal, a second electrode of the second reset transistor T7is electrically connected to the first electrode of the light emitting device0120, and a gate of the second reset transistor T7is configured to be electrically connected to a first scanning line GA1to receive a control signal.

A first electrode of the first light emitting control transistor T4is electrically connected to the first power terminal VDD, a second electrode of the first light emitting control transistor T4is electrically connected to the first electrode of the driving transistor T1, and a gate of the first light emitting control transistor T4is configured to be electrically connected with a light emitting control line EM to receive a light emitting control signal.

A first electrode of the second light emitting control transistor T5is electrically connected to the second electrode of the driving transistor T1, a second electrode of the second light emitting control transistor T5is electrically connected to the first electrode of the light emitting device0120, and a gate of the second light emitting control transistor T5is configured to be electrically connected to a light emitting control line EM to receive a light emitting control signal.

The second electrode of the light emitting device0120is electrically connected to a second power terminal VSS. The first electrodes and the second electrodes of the above transistors may be determined as source electrodes or drain electrodes according to the practical applications, which is not limited herein.

Exemplarily, as shown inFIG.2A, the threshold compensation transistor T3may include: a first sub-compensation transistor T31and a second sub-compensation transistor T32.

A gate of the first sub-compensation transistor T31is electrically connected to the second scanning line GA2, a first electrode of the first sub-compensation transistor T31is electrically connected to the gate of the driving transistor T1, and a second electrode of the first sub-compensation transistor T31is electrically connected to a first electrode of the second sub-compensation transistor T32.

A gate of the second sub-compensation transistor T32is electrically connected to the second scanning line GA2, and a second electrode of the second sub-compensation transistor T32is electrically connected to the second electrode of the driving transistor T1.

Exemplarily, one of the first power terminal VDD and the second power terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal. For example, in the embodiment shown inFIG.2A, the first power terminal VDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage; and the second power terminal VSS may be a voltage source to output a constant first voltage, and the second voltage is a negative voltage, etc. For example, in some examples, the second power terminal VSS may be grounded. The first reset signal line VINIT1and the second reset signal line VINIT2are the same signal line.

A signal timing diagram corresponding to the pixel driving circuit shown inFIG.2Ais shown inFIG.2B. In one frame of display time, a working process of the pixel driving circuit has three stages: T10stage, T20stage, and T30stage, ga1represents a signal transmitted on the first scanning lines GA1, ga2represents a signal transmitted on the second scanning lines GA2, and em represents a signal transmitted on the light emitting control lines EM.

In the T10stage, the signal ga1controls the first reset transistor T6and the second reset transistor T7to be turned on. The turned-on first reset transistor T6provides the signal transmitted on the first reset signal line VINIT1to the gate of the driving transistor T1to reset the gate of the driving transistor T1. The turned-on second reset transistor T7provides the signal transmitted on the first reset signal line VINIT1to the first electrode of the light emitting device0120to reset the first electrode of the light emitting device0120. In addition, in this stage, the signal ga2controls the data writing transistor T2, the first sub-compensation transistor T31, and the second sub-compensation transistor T32to be turned off. The signal em controls both the first light emitting control transistor T4and the second light emitting control transistor T5to be turned off.

In the T20stage, the signal ga2controls the data writing transistor T2, the first sub-compensation transistor T31, and the second sub-compensation transistor T32to be turned on, so that the data signal transmitted on the data line VD can charge the gate of the driving transistor T1, and the voltage of the gate of the driving transistor T1becomes: Vdata+|Vth|. Vth represents a threshold voltage of the driving transistor T1, and Vdata represents a voltage of the data signal. Moreover, in this stage, the signal ga1controls both the first reset transistor T6and the second reset transistor T7to be turned off. The signal em controls both the first light emitting control transistor T4and the second light emitting control transistor T5to be turned off.

In the T30stage, the signal em controls both the first light emitting control transistor T4and the second light emitting control transistor T5to be turned on. The turned-on first light emitting control transistor T4provides a voltage Vdd of the first power terminal VDD to the first electrode of the driving transistor T1, so that the voltage of the first electrode of the driving transistor T1is Vdd. The driving transistor T1generates a driving current according to its gate voltage Vdata+|Nth| and the voltage Vdd of the first electrode. The driving current is provided to the light emitting device0120through the turned-on second light emitting control transistor T5to drive the light emitting device0120to emit light. Moreover, in this stage, the signal ga1controls both the first reset transistor T6and the second reset transistor T7to be turned off. The signal ga2controls the data writing transistor T2, the first sub-compensation transistor T31and the second sub-compensation transistor T32to be turned off.

It should be noted that, in the embodiment of the present disclosure, the pixel driving circuit in each sub-pixel may not only have the structure shown inFIG.2A, but also may be a structure including other quantities of transistors, which is not limited in the embodiment of the present disclosure.

FIG.3is a schematic diagram of a layout structure of a pixel driving circuit provided by some embodiments of the present disclosure.FIGS.4A to4Eare schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the present disclosure. Examples shown inFIGS.3to4Etake a pixel driving circuit of a sub-pixel spx as an example.FIGS.3to4Ealso show the first scanning line GA1, the second scanning line GA2, the first reset signal line VINIT1(the first reset signal line VINIT1and the second reset signal line VINIT2are the same signal line, so the first reset signal line VINIT1is shown), the light emitting control line EM, the data line VD, a main power line VDD1, and an auxiliary power line VDD2that are electrically connected to the pixel driving circuit0121. The main power line VDD1is electrically connected to the first power terminal VDD to input a driving voltage (i.e., the first voltage) to the first power terminal VDD. Exemplarily, a plurality of data lines VD may be arranged in the first direction F1.

Exemplarily, as shown inFIGS.3,4a, and5, a semiconductor layer500of the pixel driving circuit0121is shown. The semiconductor layer500may be formed by patterning a semiconductor material. The semiconductor layer500may be configured to make active layers of the above driving transistor T1, the data writing transistor T2, a first sub-compensation transistor T31, a second sub-compensation transistor T32, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6and the second reset transistor T7, and each active layer may include a source region, a drain region and a channel region between the source region and the drain region. For example,FIG.4Aillustrates a channel region T1-A of the driving transistor T1, a channel region T2-A of the data writing transistor T2, a first channel region T31-A of the first sub-compensation transistor T31, a second channel region T31-A of the first sub-compensation transistor T31, a second channel region T32-A of the sub-compensation transistor T32, a channel region T4-A of the first light emitting control transistor T4, a channel region T5-A of the second light emitting control transistor T5, a channel region T6-A of the first reset transistor T6, and a channel region T7-A of the second reset transistor T7.

Moreover, exemplarily, the active layers of the transistors may be integrally disposed. Further, the semiconductor layer500may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the above source regions and drain regions may be regions doped with n-type impurities or p-type impurities.

Exemplarily, as shown inFIG.5, a first gate insulating layer610is formed on the above semiconductor layer500and configured to protect the above semiconductor layer500. As shown inFIGS.3,4B, and5, a gate conductive layer300of the pixel driving circuit0121is shown. The gate conductive layer300is disposed on a side of the first gate insulating layer610away from the base substrate1000so as to be insulated from the semiconductor layer500. The gate conductive layer300may include: a plurality of scanning lines, the second electrode CC2aof the storage capacitor CST, the light emitting control line EM, and the gates of the driving transistor T11, the data writing transistor T2, the first sub-compensation transistor T31, the second sub-compensation transistor T32, the first light emitting control transistor T4, the second light emitting control transistor T5, the first reset transistor T6and the second reset transistor T7. Exemplarily, the plurality of scanning lines includes, for example, a plurality of first gate lines GA1and a plurality of second gate lines GA2.

For example, as shown inFIGS.3to4B, the gate of the data writing transistor T2may be a first part where the second scanning line GA2overlaps the semiconductor layer500(for example, a first part where the second scanning line GA2overlaps the channel region T2-A of the data writing transistor T2), the gate of the first light emitting control transistor T4may be a first part where the light emitting control line EM overlaps the semiconductor layer500, the gate of the second light emitting control transistor T5may be a second part where the light emitting control line EM overlaps the semiconductor layer500, the gate of the first reset transistor T6is a first part where the first scanning line GA1overlaps the semiconductor layer500, the gate of the second reset transistor T7is a second part where the first scanning line GA1overlaps the semiconductor layer500, the threshold compensation transistor T3may be a thin film transistor of a double-gate structure, the gate of the second sub-compensation transistor T32may be a second part where the second scanning line GA2overlaps the semiconductor layer500(for example, a second part where the second scanning line GA2overlaps the second channel region T32-A of the second sub-compensation transistor T32), and the gate of the first sub-compensation transistor T31may be a part where a protrusion portion320protruding from the second scanning line GA2overlaps the semiconductor layer500. Exemplarily, the gate of the driving transistor T1may be set as the second electrode CC2aof the storage capacitor CST. That is, the gate of the driving transistor T1and the second electrode CC2aof the storage capacitor CST are of an integral structure.

It should be noted that each dashed rectangular frame inFIG.4Ashows each part where the gate conductive layer300overlaps the semiconductor layer500in one sub-pixel spx.

Exemplarily, as shown inFIGS.3and4B, the first scanning line GA1, the second scanning line GA2, and the light emitting control line EM are arranged in the second direction F2, and an orthographic projection of the second scanning line GA2on the base substrate1000is located between an orthographic projection of the first scanning line GA1on the base substrate1000and an orthographic projection of the light emitting control line EM on the base substrate1000.

Exemplarily, as shown inFIGS.3and4B, in the second direction F2, an orthographic projection of the second electrode CC2aof the storage capacitor CST on the base substrate1000is located between the orthographic projection of the second scanning line GA2on the base substrate1000and the orthographic projection of the light emitting control line EM on the base substrate1000. An orthographic projection of the protrusion portion320protruding from the second scanning line GA2on the base substrate1000is located on a side of the orthographic projection of the second scanning line GA2on the base substrate1000away from the orthographic projection of the light emitting control line EM on the base substrate1000.

Exemplarily, as shown inFIGS.3and4B, in the second direction F2, the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the gate of the second reset transistor T7are all located on a first side of the gate of the driving transistor T1, and the gate of the first light emitting control transistor T4and the gate of the second light emitting control transistor T5are both located on a second side of the gate of the driving transistor T1.

For example, in some embodiments, as shown inFIGS.3and4B, in the first direction F1, the gate of the data writing transistor T2and the gate of the first light emitting control transistor T4are both located in a third side of the gate of the driving transistor T1. A first gate of the threshold compensation transistor T3, the gate of the second light emitting control transistor T5and the gate of the second reset transistor T7are all located on a fourth side of the gate of the driving transistor T1. The third side and the fourth side of the gate of the driving transistor T1are two opposite sides of the gate of the driving transistor T1in the first direction F1.

Exemplarily, as shown inFIG.5, a second gate insulating layer620is formed on the above gate conductive layer300and configured to protect the above gate conductive layer300. As shown inFIGS.3,4C, and5, a capacitor electrode layer400of the pixel driving circuit0121is shown. The capacitor electrode layer400is disposed on a side of the second gate insulating layer620away from the base substrate1000. The capacitor electrode layer400may include the first electrode CC1aof the storage capacitor CST, the first reset signal line VINIT1, and a voltage stabilizing portion410. Exemplarily, an orthographic projection of the first electrode CC1aof the storage capacitor CST on the base substrate1000and an orthographic projection of the second electrode CC2aof the storage capacitor CST on the base substrate1000at least partially overlap to form the storage capacitor CST. An orthographic projection of the voltage stabilizing portion410on the base substrate1000and an orthographic projection of the source region of the active layer of the data writing transistor T2on the base substrate1000have an overlapping region. The orthographic projection of the voltage stabilizing portion410on the base substrate1000and an orthographic projection of the drain region of the active layer of the first reset transistor T6on the base substrate1000have an overlapping region. In addition, the orthographic projection of the voltage stabilizing portion410on the base substrate1000and an orthographic projection of an adjacent conductor region between the first channel region T31-A of the first sub-compensation transistor T31and the second channel region T32-A of the second sub-compensation transistor T32on the base substrate1000has an overlapping region so as to reduce current leakage caused by a photoelectric effect.

Exemplarily, as shown inFIG.5, an interlayer dielectric layer630is formed on the above capacitor electrode layer400and configured to protect the above capacitor electrode layer400. As shown inFIGS.3,4D, and5, a first conductive layer100of the pixel driving circuit0121is shown. The first conductive layer100is disposed on a side of the interlayer dielectric layer630away from the base substrate1000. The first conductive layer100may include: the data line VD, the main power line VDD1, and bridge portions341a,342a, and343a. The data line VD and the main power line VDD1are disposed at an interval.

Exemplarily, as shown inFIG.5, an interlayer insulating layer640is formed on the above first conductive layer100and configured to protect the above first conductive layer100. As shown inFIGS.3,4E, and5, a second conductive layer200of the pixel driving circuit0121is shown. The second conductive layer200is disposed on a side of the interlayer insulating layer640away from the base substrate1000. The second conductive layer200may include the auxiliary power line VDD2and a transfer portion351a. In addition, the interlayer insulating layer640has a first power via hole, and the main power line VDD1and the auxiliary power line VDD2are electrically connected to each other through the first power via hole to achieve the effect of reducing resistance. Further, an orthographic projection of the main power line VDD on the base substrate1000and an orthographic projection of the auxiliary power line VDD2on the base substrate1000have an overlapping region. Exemplarily, the auxiliary power line may be configured as a power line that transmits the driving voltage (i.e., the first voltage).

FIG.5is a schematic diagram of a cross-sectional structure in an AA’ direction in the schematic diagram of the layout structure shown inFIG.3. The first gate insulating layer610is disposed between the semiconductor layer500and the gate conductive layer300, the second gate insulating layer620is disposed between the gate conductive layer300and the capacitor electrode layer400, the interlayer dielectric layer630is disposed between the capacitor electrode layer400and the first conductive layer100, and the interlayer insulating layer640is disposed between the first conductive layer100and the second conductive layer200. Further, a planarization layer650is disposed on a side of the second conductive layer200away from the base substrate1000, and a first electrode layer600is disposed on a side of the planarization layer650away from the base substrate1000. A pixel defining layer660, the light emitting function layer0122, and a second electrode layer0123are sequentially disposed on a side of the first electrode layer600away from the base substrate1000. The first electrode layer600may include a plurality of first electrodes spaced apart from each other, and the first electrodes are electrically connected to the transfer portion351athrough via holes penetrating the planarization layer650. It should be noted thatFIG.5does not show the via holes of the transfer portion351aand the planarization layer650.

As shown inFIG.3andFIG.5, the sub-pixel spx may include a first connection through hole, a second connection through hole, a third connection through hole and a fourth connection through hole. The first connection through hole penetrates through the first gate insulating layer610, the second gate insulating layer620, and the interlayer dielectric layer630; the second connection through hole penetrates through the second gate insulating layer620and the interlayer dielectric layer630; the third connection through hole penetrates through the interlayer dielectric layer630; and the fourth connection through hole penetrates through the interlayer insulating layer640.

Exemplarily, the sub-pixel spx may include first connection through holes381a,382a,384a,387a, and388a. The sub-pixel spx may include a second connection through hole385a. The sub-pixel spx may include third connection through holes386aand3832a. The sub-pixel spx includes fourth connection through holes385aand3831a. The data line VD is electrically connected to a source region T2-S of the data writing transistor T2in the semiconductor layer500through at least one first connection through hole381a. The main power line VDD1is electrically connected to the source region of the corresponding first light emitting control transistor T4in the semiconductor layer500through at least one first connection through hole382a. One end of the bridge portion341ais electrically connected to the drain region of the corresponding first sub-compensation transistor T31in the semiconductor layer500through at least one first connection through hole384a. The other end of the bridge portion341ais electrically connected to the gate (that is, the second electrode CC2aof the storage capacitor CST) of the driving transistor T1in the gate conductive layer300through at least one second connection through hole385a. One end of the bridge portion342ais electrically connected to the first reset signal line VINIT1through at least one third connection through hole386a, and the other end of the bridge portion342ais electrically connected to a source region T6-S of the first reset transistor T6in the semiconductor layer500through at least one first connection through hole387a. The bridge portion343ais electrically connected to the drain region of the second light emitting control transistor T5in the semiconductor layer500through at least one first connection through hole388a. The main power line VDD1is electrically connected to the first electrode CC1aof the storage capacitor CST in the capacitor electrode layer400through at least one third connection through hole3832a. The main power line VDD1is also electrically connected to the auxiliary power line VDD2in the second conductive layer200through at least one fourth connection through hole3831a(i.e., the first power via hole). The transfer portion351ais electrically connected to the bridge portion343athrough at least one fourth connection through hole385a.

Exemplarily, each of the first connection through holes381a,382a,384a,387a, and388ain the sub-pixel may be disposed one or two or more. In practical applications, this may be designed and determined according to the requirements of practical application environments, which is not limited herein.

Exemplarily, one or two or more second connection through holes385ain the sub-pixel may be disposed. In practical applications, this may be designed and determined according to the requirements of the practical application environments, which is not limited herein.

Exemplarily, one or two or more third connection through holes386aand one or two or more third connection through holes3832ain the sub-pixel may be disposed. In practical applications, this may be designed and determined according to the requirements of the practical application environments, which is not limited herein.

Exemplarily, one or two or more fourth connection through holes385aand one or two or more fourth connection through holes3831ain the sub-pixel may be disposed. In practical applications, this may be designed and determined according to the requirements of the practical application environments, which is not limited herein.

For example, as shown inFIGS.3to4E, in the second direction F2, the first scanning line GA1, the second scanning line GA2, and the first reset signal line VINIT1are all located on the first side of the gate of the driving transistor T1, and the light emitting control line EM is located on the second side of the driving transistor T1.

Exemplarily, the first scanning line GA1, the second scanning line GA2, and the light emitting control line EM may be located in the same layer (i.e., the gate conductive layer300). The main power line VDD1and the data line VD are located in the same layer (i.e., the first conductive layer100).

It should be noted that a position arrangement relationship of the transistors in each sub-pixel spx is not limited to the examples shown inFIGS.3to4E, and the positions of the above transistors may be specifically set according to practical application requirements.

It should be noted that the first direction F1may be a row direction of the sub-pixel, and the second direction F2may be a column direction of the sub-pixel. Or, the first direction F1may also be the column direction of the sub-pixel, and the second direction F2may be the row direction of the sub-pixel. In practical applications, setting is made according to the practical application requirements, which is not limited herein.

In practical applications, generally, the scanning lines and other conductive film layers will have a facing area, which will generate coupling capacitance. Since the scanning lines generally transmit a signal that controls the transistors to be turned-on or turned-off, due to the existence of the coupling capacitance, loading of the signal transmitted on the scanning lines is larger, which will reduce the stability of the signal transmitted on the scanning lines, thereby affecting the display effect.

In specific implementation, in the embodiment of the present disclosure, as shown inFIGS.2ato11, a first insulating layer may include: the second gate insulating layer620and the interlayer dielectric layer630. The auxiliary power line VDD2may include: a plurality of sub-auxiliary power lines110and a plurality of auxiliary conduction lines120. The plurality of sub-auxiliary power lines110are arranged in the first direction F1and extend in the second direction F2, and adjacent two of at least part of the sub-auxiliary power lines110are electrically connected by at least one auxiliary conduction line120. In addition, an orthographic projection of at least one of the plurality of auxiliary conduction lines120on the base substrate1000does not overlap an orthographic projection of the scanning lines on the base substrate1000. In this way, the facing area between the auxiliary conduction lines120and the scanning lines can be avoided, so that the coupling capacitance between the auxiliary conduction lines120and the scanning lines is avoided, the stability of the signal transmitted on the scanning lines can be improved, and the display effect can be improved.

Exemplarily, as shown inFIG.6andFIG.8, the orthographic projection of at least one of the plurality of auxiliary conduction lines120on the base substrate1000does not overlap an orthographic projection of the first scanning line GA1on the base substrate1000. The orthographic projection of at least one of the plurality of auxiliary conduction lines120on the base substrate1000does not overlap an orthographic projection of the second scanning line GA2on the base substrate1000. Further, an orthographic projection of each auxiliary conduction line120on the base substrate1000does not overlap the orthographic projection of the first scanning line GA1on the base substrate1000. The orthographic projection of each auxiliary conduction line120on the base substrate1000does not overlap the orthographic projection of the second scanning line GA2on the base substrate1000.

It should be noted that the plurality of sub-auxiliary power lines110extend in the second direction F2, which may mean that these sub-auxiliary power lines110extend substantially in the second direction F2. In practical applications, these sub-auxiliary power lines110may extend in the second direction F2in a zigzag manner.

Exemplarily, as shown inFIGS.3and6to8, the second scanning line GA2may include a scanning line portion310and a plurality of protrusion portions320that are electrically connected to each other. The scanning line portion310extends in the first direction F1, and the protrusion portions320extend in the second direction F2. In addition, the protrusion portions320may serve as the gates of the transistors, and the orthographic projection of each auxiliary conduction line120on the base substrate1000does not overlap an orthographic projection of the protrusion portions320on the base substrate1000. In this way, the facing area between the auxiliary conduction lines120and the protrusion portions320can be avoided, and the coupling influence of the auxiliary conduction lines120on the gates of the transistors can be further reduced.

Exemplarily, as shown inFIGS.3,4B, and6, a protrusion portion320may serve as the gate of the first sub-compensation transistor T31, and part of the scanning line portion310may serve as the gate of the second sub-compensation transistor T32. In this way, the facing area between the auxiliary conduction lines120and the protrusion portion320can be avoided, and the coupling influence of the auxiliary conduction lines120on the gate of the first sub-compensation transistor T31can be further reduced.

It should be noted that the scanning line portion310extends in the first direction F1, which may mean that this scanning line portion310extends substantially in the first direction F1. In practical applications, the scanning line portion310may extend to form a straight line, or the scanning line portion310may also extend in the first direction F1in a zigzag manner.

Exemplarily, as shown inFIGS.6to12, the display panel further includes: a plurality of repeating elements001. The repeating elements001include a plurality of sub-pixels spx; and the plurality of repeating elements001are arranged in the first direction F1to form a repeating element row01, and the repeating element row01is arranged in the second direction F2. Exemplarily, the repeating elements001in two adjacent repeating element rows01are arranged in a misalignment manner. Exemplarily, the repeating element001in two adjacent repeating element rows01differs by ½of the size of the repeating element001. It should be noted that the size of one repeating element001described above may be a distance between centers of the sub-pixels of the same color in two adjacent repeating elements001in the first direction F1. For example, the size of one repeating element001described above may be a distance between centers of first electrodes of first-color sub-pixels010in two adjacent repeating elements001in the second direction F2.

Or, for example, the repeating elements in the adjacent repeating element rows are misaligned from each other in the first direction, that is, the adjacent repeating elements in the adjacent repeating element rows have a certain offset in the first direction. Therefore, the sub-pixels of the same color in the adjacent repeating element rows are not aligned in the second direction. In some examples, the offset of the sub-pixels of the same color in the adjacent repeating element rows in the first direction may be half of the size of the repeating element in the first direction. For example, the size of one repeating element in the first direction may be a pitch of the repeating element in the first direction.

In specific implementation, in the embodiment of the present disclosure, as shown inFIGS.6to12, the sub-pixels in the plurality of repeating elements include: the first-color sub-pixels110, second-color sub-pixel pairs020and third-color sub-pixels030that are arranged in the first direction F1. Each second-color sub-pixel pair020may include two second-color sub-pixels arranged in the second direction F2. For example, each second-color sub-pixel pair020may include: a first second-color sub-pixel021and a second second-color sub-pixel022arranged in the second direction F2. Exemplarily, the first-color sub-pixels010are configured to emit light of a first color, the second-color sub-pixels021and022are configured to emit light of a second color, and the third-color sub-pixels are configured to emit light of a third color. In some examples, the first color, the second color and the third color may be selected from red, green, and blue. For example, the first color is red, the second color is green, and the third color is blue. Thus, the repeating elements001are of an arrangement structure of the red, green and blue sub-pixels. Of course, the embodiment of the present disclosure includes but is not limited thereto. The above first color, second color and third color may also be other colors.

In specific implementation, in the embodiment of the present disclosure, as shown inFIGS.3,6and11, the auxiliary conduction lines120may include first auxiliary conduction lines121. Adjacent two of part of the sub-auxiliary power lines110are electrically connected by at least one first auxiliary conduction line121. Exemplarily, adjacent two of part of the sub-auxiliary power lines110are electrically connected by one first auxiliary conduction line121. Or, adjacent two of part of the sub-auxiliary power lines110are electrically connected by two first auxiliary conduction lines121. Or, adjacent two of part of the sub-auxiliary power lines110are electrically connected by three first auxiliary conduction lines121, or more first auxiliary conduction lines121. This may be designed and determined according to the requirements of the practical application environments, which is not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown inFIG.6andFIG.11, one repeating element row01may correspond to one first scanning line GA1, one second scanning line GA2, and at least one first auxiliary conduction line121. Exemplarily, one repeating element row01may correspond to one, two, three or more first auxiliary conduction lines121. This may be designed and determined according to the requirements of the practical application environments, which is not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown inFIG.6andFIG.11, for the first scanning line GA1, the second scanning line GA2, and the first auxiliary conduction line121that correspond to the same repeating element row01, an orthographic projection of the first auxiliary conduction line121on the base substrate1000is located between orthographic projections of the protrusion portions320of the first scanning line GA1and the second scanning line GA2on the base substrate1000.

In specific implementation, in the embodiment of the present disclosure, as shown inFIG.6,FIG.12andFIG.13, the first electrode layer600may include a plurality of first electrodes spaced apart from each other. One sub-pixel is provided with one first electrode. For example, the first-color sub-pixels010are provided with first electrodes611, the first second-color sub-pixels021are provided with first electrodes621, the second second-color sub-pixels022are provided with first electrodes622, and the third-color sub-pixels030are provided with first electrodes631. In addition, the orthographic projection of the first auxiliary conduction lines121on the base substrate1000does not overlap an orthographic projection of the first electrodes on the base substrate1000.

In specific implementation, in the embodiment of the present disclosure, as shown inFIGS.6to12, each of at least part of the second-color sub-pixel pairs corresponds to one first auxiliary conduction line121. Exemplarily, each of part of the second-color sub-pixel pairs may correspond to one first auxiliary conduction line121. Each of all the second-color sub-pixel pairs may also correspond to one first auxiliary conduction line121. This may be designed and determined according to the requirements of the practical application environments, which is not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown inFIGS.3and6to12, the orthographic projection of the first auxiliary conduction line121on the base substrate may be located between orthographic projections of two first electrodes in the corresponding second-color sub-pixel pair on the base substrate. Exemplarily, the orthographic projection of the first auxiliary conduction lines121on the base substrate1000may be located between the orthographic projection of the first electrodes621in the corresponding first second-color sub-pixel021and the orthographic projection of the first electrodes622in the corresponding second second-color sub-pixel022on the base substrate1000.

In specific implementation, as shown inFIG.3andFIG.6, the data writing transistors in a column of sub-pixels are electrically connected to one data line. For the second-color sub-pixel pair020and the first-color sub-pixel010in the same repeating element001, an orthographic projection of the first auxiliary conduction line121corresponding to the second-color sub-pixel pair020on the base substrate1000and an orthographic projection of the data line VD electrically connected to the first-color sub-pixel010on the base substrate1000have an overlapping region. Further, in specific implementation, as shown inFIG.3andFIG.6, for the second-color sub-pixel pair020and the first-color sub-pixel010in the same repeating element001, the orthographic projection of the first auxiliary conduction line121corresponding to the second-color sub-pixel pair020on the base substrate1000and an orthographic projection of a first connection via hole in the first-color sub-pixel010on the base substrate1000have an overlapping region. The first connection through hole381aserves as the first connection via hole.

In specific implementation, as shown inFIG.3andFIG.6, the first reset transistor in each sub-pixel is electrically connected to the first reset signal line through a second connection via hole. The orthographic projection of the first auxiliary conduction line121on the base substrate and an edge of an orthographic projection of the second connection via hole in the second second-color sub-pixel on the base substrate have an overlapping region. Exemplarily, the first connection through hole387aserves as the second connection via hole.

In specific implementation, as shown inFIG.3andFIG.6, the first auxiliary conduction lines121extend in a linear shape in the first direction, so that the resistance can be reduced. Of course, the embodiment of the present disclosure includes but is not limited thereto, and the implementation of the above first auxiliary conduction lines121may also have other shapes.

In specific implementation, as shown inFIG.6, the auxiliary conduction lines may also include second auxiliary conduction lines122. Adjacent two the rest of the sub-auxiliary power lines110are electrically connected by at least one second auxiliary conduction line122. In this way, every two adjacent sub-auxiliary power lines110may be electrically connected by the auxiliary conduction lines. Exemplarily, adjacent two the rest of the sub-auxiliary power lines110are electrically connected by one second auxiliary conduction line122. Adjacent two the rest of the sub-auxiliary power lines110are electrically connected by two, three or more second auxiliary conduction lines122. This may be designed and determined according to the requirements of the practical application environments, which is not limited herein.

In specific implementation, as shown inFIGS.3to12, for the first-color sub-pixels010in one repeating element row01and the third-color sub-pixels030in the adjacent repeating element row and closest to the first-color sub-pixels010, an orthographic projection of one second auxiliary conduction line122on the base substrate1000is disposed between an orthographic projection of the first electrode611in the first-color sub-pixel010on the base substrate1000and an orthographic projection of the first electrode631in the third-color sub-pixel030on the base substrate1000. Further, for the first-color sub-pixels010in one repeating element row01and the third-color sub-pixels030in the adjacent repeating element row and closest to the first-color sub-pixels010, the orthographic projection of the second auxiliary conduction line122on the base substrate1000is closer to the orthographic projection of the first electrode631in the third-color sub-pixel030on the base substrate1000than the orthographic projection of the first electrode611in the first-color sub-pixel010on the base substrate1000.

In specific implementation, as shown inFIGS.3to12, by providing the first auxiliary conduction lines121and the second auxiliary conduction lines122, the sub-auxiliary power lines110and the auxiliary conduction lines can roughly form a grid structure.

On the other hand, the long-term light emitting stability of the light emitting device is generally also an important specification or index of the display panel. In the research, the publishers of the present application have noticed that: there are many factors that affect the long-term light emitting stability of the light emitting device, in addition to the life of a light emitting material itself, the working state of the transistors in the pixel driving circuit has a certain degree of influence on light emitting brightness and long-term light emitting stability.

In this regard, embodiments of the present disclosure provide some display panels. As shown inFIGS.6to13, the display panel may include a base substrate1000, pixel driving circuits, and a first electrode layer600; and the first electrode layer600includes a plurality of first electrodes. One pixel driving circuit and one first electrode are arranged in a one-to-one correspondence manner, and each pixel driving circuit may include a threshold compensation transistor T3; and the display panel may also include a first pixel driving circuit2657and a second pixel driving circuit2658that are arranged adjacently, orthographic projections of a channel region of a threshold compensation transistor T3in the pixel driving circuit2657and a channel region of a threshold value compensation transistor T3in the second pixel driving circuit2658on the base substrate1000both have overlapping regions with an orthographic projection of the first electrode corresponding to the first pixel driving circuit2657on the base substrate. Therefore, the channel region of the threshold compensation transistor in the first pixel driving circuit and the channel region of the threshold compensation transistor in the second pixel driving circuit can be simultaneously shielded by the first electrode, thereby improving the stability and life of the threshold compensation transistors, so that the long-term light emitting stability and life of the display panel are improved.

It should be noted that the “first” and “second” in the above first pixel driving circuit and the second pixel driving circuit are only used to distinguish two pixel driving circuits in text. The specific structures of the two pixel driving circuits are the same.

In specific implementation, in the embodiments of the present disclosure, the orthographic projections of the channel region of the threshold compensation transistor T3in the first pixel driving circuit2657and the channel region of the threshold compensation transistor T3in the second pixel driving circuit2658on the base substrate1000both overlap the orthographic projection of the first electrode corresponding to the first pixel driving circuit2657on the base substrate, so that the first electrode corresponding to the first pixel driving circuit2657may partially shield or completely shield the channel region of the threshold compensation transistor T3in the first pixel driving circuit2657and the channel region of the threshold compensation transistor T3in the second pixel driving circuit2658. Therefore, the display panel in the embodiments of the present disclosure can improve the stability and life of the threshold compensation transistor T3in the first pixel driving circuit and the threshold compensation transistor T3in the second pixel driving circuit2658, thereby improving the long-term light emitting stability and life of the display panel.

In some examples, the channel region of the threshold compensation transistor T3in the first pixel driving circuit2657and the channel region of the threshold compensation transistor T3in the second pixel driving circuit2658may both fall into the orthographic projection of the first electrode corresponding to the first pixel driving circuit2657on the base substrate1000, and the first electrode corresponding to the first pixel driving circuit2657may completely shield the channel region of the threshold compensation transistor T3in the first pixel driving circuit2657and the channel region of the threshold compensation transistor T3in the second pixel driving circuit2658, thereby further improving the stability and life of the threshold compensation transistors, so that the long-term light emitting stability and life of the display panel are improved.

In some examples, as shown inFIGS.2A,3,4A and6, each threshold compensation transistor T3may be a thin film transistor of a double-gate structure, so that the reliability of the threshold compensation transistor may be improved. An active layer of the threshold compensation transistor T3includes a first channel region T31-A and a second channel region T32-A arranged at an interval, and a common conductive region SE between the first channel region T31-A and the second channel region T32-A. In addition, orthographic projections of the common conductive region SE of the threshold compensation transistor T3in the first pixel driving circuit2657and the common conductive region SE of the threshold compensation transistor T3in the second pixel driving circuit2658on the base substrate1000both have overlapping regions with the orthographic projection of the first electrode corresponding to the first pixel driving circuit2657on the base substrate1000. Therefore, the first electrode corresponding to the first pixel driving circuit2657may partially or completely shield the common conductive region SE of the threshold compensation transistor T3in the first pixel driving circuit2657and the common conductive region SE of the threshold compensation transistor T3in the second pixel driving circuit2658, thereby further improving the stability and life of the threshold compensation transistors, so that the long-term light emitting stability and life of the display panel are improved.

Exemplarily, as shown inFIGS.6,12and13, the first pixel driving circuit2657and the second pixel driving circuit2658are disposed in a first direction F1. The first pixel driving circuit2657is electrically connected to a first electrode631in one repeating element001correspondingly. The second pixel driving circuit2658is electrically connected to a first electrode621in another repeating element001correspondingly. In addition, the first electrode631electrically connected to the first pixel driving circuit2657and the first electrode621electrically connected to the second pixel driving circuit2658are respectively located in different repeating element rows01, and the repeating element rows01where the first electrode631electrically connected to the first pixel driving circuit2657and the first electrode621electrically connected to the second pixel driving circuit2658are adjacent.

Exemplarily, as shown inFIGS.5,6,12and13, the pixel defining layer660includes a plurality of openings; and the plurality of openings includes a first opening1951, a second opening19521, a third opening19522and a fourth opening1953. The first opening1951is disposed corresponding to the first electrode611and exposes the first electrode611, the second opening19521is disposed corresponding to the first electrode621and exposes the first electrode621, the third opening19522is disposed corresponding to the first electrode622and exposes the first electrode611, and the fourth opening1953is disposed corresponding to the first electrode631and exposes the first electrode631.

Exemplarily, as shown inFIGS.6,12and13, the first electrode611includes a first body portion6111and a first connection portion6112that are electrically connected to each other, an orthographic projection of the first opening1951on the base substrate1000falls within an orthographic projection of the first body portion6111on the base substrate1000, and the first connection portion6112is electrically connected to the pixel driving circuit corresponding to the first electrode611.

Exemplarily, as shown inFIGS.6,12, and13, the first electrode621includes a second body portion6211and a second connection portion6212that are electrically connected to each other, an orthographic projection of the second opening19521on the base substrate1000falls within an orthographic projection of the second body portion6211on the base substrate1000, and the second connection portion6212is electrically connected to the pixel driving circuit corresponding to the first electrode621.

Exemplarily, as shown inFIGS.6,12, and13, the first electrode622includes a third body portion6221and a third connection portion6222that are electrically connected to each other, an orthographic projection of the third opening19522on the base substrate1000falls within an orthographic projection of the third body portion6221on the base substrate1000, and the third connection portion6222is electrically connected to the pixel driving circuit corresponding to the first electrode622.

Exemplarily, as shown inFIGS.6,12, and13, the first electrode631includes a fourth body portion6311and a fourth connection portion6312, an orthographic projection of the fourth opening1953on the base substrate1000falls within an orthographic projection of the fourth body portion6311on the base substrate1000, and the fourth connection portion6312is electrically connected to the pixel driving circuit (for example, the above first pixel driving circuit2657) corresponding to the first electrode631.

In some examples, as shown inFIGS.6,12, and13, a shape of the first body portion6111is approximately the same as that of the first opening1951; a shape of the second body portion6211is approximately the same as that of the second opening19521; a shape of the third body portion6221is approximately the same as that of the third opening19522; and a shape of the fourth body portion6311is approximately the same as that of the fourth opening1953. For example, when the shape of the fourth opening1953is a hexagon, the shape of the fourth body portion6311is also a hexagon. Of course, the shapes of the fourth opening and the fourth body portion are not limited to hexagons, for example, other shapes such as ellipses.

In some examples, as shown inFIGS.4A,6,12, and13, the first electrode631may further include a first supplement portion6313. Orthographic projections of the first channel region T31-A and the second channel region T32-A of the threshold compensation transistor T3in the first pixel driving circuit2657corresponding to the first electrode631on the base substrate1000respectively overlap an orthographic projection of the first supplement portion6313on the base substrate1000. In the display panel, by adding the first supplement portion to the first electrode, the first electrode may overlap or cover the two channel regions of the threshold compensation transistor in the corresponding pixel driving circuit, thereby improving the stability and life of the threshold compensation transistor, so that the long-term light emitting stability and life of the display panel are improved.

In some examples, as shown inFIGS.6,12, and13, the first supplement portion6313protrudes from the fourth body portion6311towards the first electrode622, and the first supplement portion6313is located on a side of the fourth connection portion6312close to the fourth body portion6311.

In some examples, as shown inFIGS.6,12, and13, the first supplement portion6313is electrically connected to the fourth body portion6311and the fourth connection portion6312. Therefore, the display panel can make full use of an area on the display panel, and the first electrode may be arranged closely, so that the resolution ratio of the display panel can be ensured.

In some examples, as shown inFIGS.6,12and13, the orthographic projection of the channel region of the threshold compensation transistor T3in the pixel driving circuit corresponding to the first electrode611on the base substrate1000falls within an orthographic projection of the first body part6111on the base substrate1000.

In some examples, as shown inFIGS.6,12and13, the orthographic projection of the second channel region T32-A of the threshold compensation transistor T3in the pixel driving circuit265corresponding to the first electrode622on the base substrate1000falls within an orthographic projection of the third body portion6221on the base substrate1000.

Further, as shown inFIG.14, the first electrode631may also include a second supplement portion6314; and the orthographic projection of the first channel region T31-A of the threshold compensation transistor T3in the second pixel driving circuit2658on the base substrate1000overlaps an orthographic projection of the second supplement portion6314on the base substrate1000. By adding the second supplement portion to the first electrode, the first electrode may partially or even completely cover the first channel region T31-A of the threshold compensation transistor T3in the second pixel driving circuit2658, thereby improving the stability and life of the threshold compensation transistor, so that the long-term light emitting stability and life of the display panel are improved.

In some examples, as shown inFIG.14, the second supplement portion6314protrudes from the fourth body portion6311towards the adjacent first electrode611in the first direction.

It should be noted that, as shown inFIG.14, the orthographic projection of the second channel region T32-A of the threshold compensation transistor T3in the second pixel driving circuit2658on the base substrate1000may fall within an orthographic projection of the fourth body portion6311on the base substrate1000.

In some examples, as shown inFIG.14, the common conductive region SE of the threshold compensation transistor T3in the first pixel driving circuit2657overlaps the orthographic projection of the first supplement portion6313on the base substrate1000. The orthographic projection of the common conductive region SE of the threshold compensation transistor T3in the two pixel driving circuits2658on the base substrate1000overlaps the orthographic projection of the fourth body portion6311of the first electrode631corresponding to the first pixel driving circuit2657on the base substrate1000.

Further, as shown inFIG.14, the first electrode611may also include a third supplement portion6113, which protrudes from the first body portion6111towards the first electrode622, and orthographic projections of a gate of a driving thin film transistor T1and a drain region of the threshold compensation transistor T3in the pixel driving circuit corresponding to the first electrode611on the base substrate1000fall within an orthographic projection of the third supplement portion6113on the base substrate1000. Therefore, the display panel can stabilize potentials on the gate of the driving thin film transistor T1and a drain electrode of the threshold compensation transistor T3through the third supplement portion6113, thereby further improving the long-term light emitting stability and life of the display panel.

Further, as shown inFIG.14, the first electrode622may also include a fourth supplement portion6223, and the orthographic projection of the first channel region T31-A of the threshold compensation transistor T3in the pixel driving circuit corresponding to the first electrode622on the base substrate1000falls within an orthographic projection of the fourth supplement portion6223on the base substrate1000. Therefore, the third body portion6221and the fourth supplement portion6223of the first electrode622may partially or completely shield the first channel region T31-A and the second channel region T32-A of the threshold compensation transistor T3in the pixel driving circuit corresponding to the first electrode622, thereby improving the stability and life of the threshold compensation transistor, so that the long-term light emitting stability and life of the display panel are improved.

Based on the same inventive concept, an embodiment of the present disclosure also provides a display apparatus, including the above display panel provided by the embodiments of the present disclosure. The display apparatus may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a displayer, a notebook computer, a digital photo frame, a navigator, and the like. Other indispensable components of the display apparatus are understood by those ordinarily skilled in the art, will not be repeated here, and should not be used as a limitation to the present disclosure. The implementation of the display apparatus may refer to the embodiments of the above display panel, and the repetition is not repeated herein.

Although the preferred embodiments of the present disclosure have been described, additional variations and modifications may be made to these embodiments by those skilled in the art once the basic inventive concept is known. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiments and all variations and modifications that fall within the scope of the present disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present disclosure without departing from the spirit or scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and its equivalent technology, the present disclosure is also intended to include these modifications and variations.