Patent ID: 12237247

DETAILED DESCRIPTION

Example aspects are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this Disclosure.

This Disclosure includes packaged semiconductor devices including an analog IC (e.g., having a voltage reference circuit) and a second circuit (e.g., a large area high capacitance density filter capacitor) attached to an analog IC with a gap over the stress sensitive circuitry of the analog IC. The area of the second circuit can be less than the area of the analog IC die, or more than the area of the analog IC. The second circuit provides a dual-function by isolating the stress sensitive regions on the surface of the analog IC die110from stress resulting from the mold compound, and also provides a circuit function such as a low pass filter for filtering noise signals in the voltage reference output without the inherent leakage current errors that would be experienced if these circuit nodes where to be conventionally coupled to a filter capacitor on a PCB. The substrate of the analog IC and the substrate of the second circuit can be matched, such as both comprising silicon, so that their coefficient of thermal expansion (CTE) can be essentially identical, which avoids the CTE induced stress into the analog IC due to the second circuit.

FIG.1Ais a top perspective view depiction of an example packaged IC100comprising an analog IC die (analog IC)110and a dual-function second circuit120with second circuit bond pads attached by an attachment layer125to a top surface of the analog IC110. The packaged IC100comprises a leadframe including a die pad105and leads106around the die pad105that the analog IC110is mounted on with a die attach adhesive115. Although not shown, the leads106can be on all 4 sides of the package. The disclosed integration of the second circuit120within the package avoids problems such as output voltage inaccuracy due to PCB leakage in the case the analog IC110includes a voltage reference circuit and the system design conventionally includes a filter capacitor on a PCB.

The second circuit120is shown including second circuit bond pads120a,120bshown attached to the top side of the analog IC die110by the attachment layer125. The second circuit120can comprise a silicon, glass, ceramic, or an alumina substrate. The attachment layer125generally occupies 2% to 20% of an area of the top one of the second circuit120(as shown inFIG.1A) and analog IC110(seeFIG.2Cdescribed below). The second circuit120can comprise an active circuit including transistor(s), or a passive circuit such as an inductor or filter capacitor.

The attachment layer125can generally be any attachment arrangement with a gap that provides a mechanical bond. The attachment layer125is formed in a ring with an inner gap (see gap126inFIG.2Adescribed below) that can comprise a printable low modulus die attach material, such as DOW7920which comprises polydimethylsiloxane and silica, where the gap creates an open cavity stress-free region over a portion of the analog IC110. Although the packaged IC100includes an encapsulating mold compound (see the mold compound220inFIG.2Adescribed below), the mold compound is not shown inFIG.1Ato avoid obscuring package IC100features. Moreover, although the second circuit120is shown having a planar bottom side, the second circuit120can also have a back side cavity that can increase the distance between the back side of the second circuit120over the cavity and the top side of the analog IC110.

The attachment layer125configured as a ring having an inner gap generally can comprise a printable low modulus elastomer, a glass-to-glass peripheral fusion or anodic bond, where the attachment layer125secures the second circuit120to the analog IC110top side up or with a flip chip arrangement with solder balls or solder capped pillars. The electrical connections between the second circuit bond pads120aand120bof the second circuit120and the first bond pads111on the analog IC110can comprise conventional wire bonding for the second circuit120top side up arrangement as shown as bond wires131inFIGS.1A and1nFIG.2Adescribed below, or a flipchip attachment for the second circuit120with solder ball127connections or solder tipped pillars that also functions as a mechanical attachment shown inFIG.1BandFIG.2Bdescribed below. The electrical connections between the first bond pads111on the analog IC110and the leads106can also comprise bond wires131.

The analog IC110can comprise a relatively sensitive circuit such as a clock generator, an ADC, a DAC, an operational amplifier, or a sensor. In the case of a sensor, for example, a hall sensor on the analog IC110needs to be essentially free of stress to minimize offset errors. In applications where external magnetic flux is accurately measured by nulling at the hall sensor with a bucking coil, where the coil current at null is a representation of the external flux magnitude, the second circuit120can be a bucking coil/inductor.

Other sensors that can benefit from disclosed aspects include anisotropic magneto resistor types as well as temperature sensors. The IC may have needed stable performance of for example −50 ppm or less from thermal hysteresis, high-temperature operating life (HTOL), and temperature coefficient (TC) lumped together. Normally the unpackaged electrical circuit may have a “pure” TC just due to the circuit design. That TC may be trimmed (e.g., laser trimmed) to a very small number. Packaging stress adds additional TC to the device. That TC is also “mixed” with thermal hysteresis because the materials that are mechanically stressed are hysteretic in that they may mechanically relax with repeated thermal excursions. The second circuit120is generally an IC die (e.g., silicon die) that can comprise an active circuit including at least one transistor, and/or passive circuitry such as at least one capacitator, inductor, or resistor.

FIG.1Bis a top perspective view depiction of an example packaged IC150comprising an analog IC110including sensitive circuitry such as a voltage reference circuit and a dual-function second circuit120attached to a top surface of the analog IC110with a gap (see gap126inFIG.2Bdescribed below) over the analog IC. The second circuit bond pads120a,120bof the second circuit120are flipchip attached by solder balls127to some of the first bond pads111on the analog IC110(seeFIG.2B). The solder balls127are generally in the gap provided by the attachment layer125and spaced away from attachment layer125. Solder balls127can be replaced by solder capped pillars.

FIG.2Ais a cross sectional depiction of the packaged IC100shown inFIG.1A, according to an example aspect. Mold compound is shown as220. The attachment layer125provides an open center gap126which acts as a mold barrier during molding to enable being free of mold compound220that is between the sensitive surface circuit regions of the analog IC110and the second circuit120. This essentially eliminates the effect of mold compound220surface stress on the analog IC110having the gap126because the gap126provides a low stress environment for the portion of the analog IC110with the gap126thereover. This arrangement is analogous to a relatively costly open cavity ceramic package.

FIG.2Bis a cross sectional depiction of a packaged IC150shown inFIG.1Bthat has the second circuit bond pads120a,120bof the second circuit120flipchip attached by solder balls127to some of the first bond pads111on the analog IC110, according to an example aspect. Packaged IC150also creates an environment for the analog IC110over the gap126that is similar to an open cavity ceramic package.

Another arrangement can combine aspects shown inFIG.2AandFIG.2Bby having a disclosed top circuit that includes through silicon vias (TSVs) to provide the interconnect to connect to the first bond pads111on the analog IC110. In this arrangement there are solder balls or solder capped pillars to make the die-to-die connection as in a flipchip arrangement, but where the second circuit would be top side up, not flipped. In such a configuration, there can be a combination of wire bonds (to make connections to the leadframe) and solder balls or pillars to connect the TSVs to bond pads on the analog IC110.

FIG.2Cshows yet another packaged IC180arrangement where the top circuit is shown as a mixed signal IC110′ contains a stress sensitive component comprising a sensitive circuit or sensor, and the bottom die on the die pad105is an second circuit120′ that comprises an analog or mixed signal circuit that interfaces with the stress sensitive component. This arrangement involves a flip chip configuration. An air gap is created between the bottom die shown as second circuit120′ and the top die being mixed signal IC110′ that is flipchip die attached which serves as a stress buffer for the stress sensitive component on the mixed signal IC110′. In this arrangement, the second circuit120′ being the bottom die can also be a larger sized passive element, that is physically larger than the mixed signal IC110′ that has the sensitive circuit being protected. The second circuit120′ has second circuit bond pads120a,120band120c, where the first bond pads111of the mixed signal IC110′ are attached by the solder balls to the second circuit bond pads120aand120b, and the second circuit bond pads120care bonded by bond wires131to the leads106.

This Disclosure also includes a semiconductor assembly method described for the case the second circuit is on top of the analog IC that comprises providing a leadframe (generally provided as a LF sheet) including a die pad and leads around the die pad, an analog IC die110having first bond pads111on its active top side with its bottom side attached to the die pad. A second circuit120with second circuit bond pads120ais attached to the active top side of the analog IC die's first bond pads111by solder balls127or pillars and held in place by an attachment layer125that is configured (e.g., a printed elastomer) as a ring with a hollow center providing an inner gap126. Bond wires are added for coupling at least some of the bond pads111to the leads106. The second circuit120and IC die110are encapsulated (e.g., using injection molding) by molding a mold compound, wherein the attachment layer125prevents the mold compound from entering the gap126.

FIG.3shows an example mixed signal stacked die device300that includes sensitive circuitry shown as a mixed signal IC110′ comprising a SAR ADC310with a voltage reference circuit315comprising a voltage reference generator315athat is known to be sensitive circuitry which provides a pre-buffered reference voltage output (VREF′) that is coupled to a buffer315b(with its output resistance shown as RO) which provides a buffered output shown as VREFthat is used as an input by the SAR ADC310(shown as a VREFinput). There is a dual-function second circuit120′ comprising at least one filter capacitor shown as CL1which together with a resistor shown as R318generally on the voltage reference circuit315provides a low pass filter for filtering the output from the voltage reference generator315ato provide VREF′. R318is generally a high value resistance (e.g., several k ohms to several giga ohms) that makes the circuit sensitive to DC leakage, particularly in conventional arrangements (not shown) where CL1is external.

The VREFoutput from the buffer315bis also shown low pass filtered by filter capacitors shown as CL2and CL3hooked in parallel that together with their associated equivalent series resistance (ESR) provide low pass filtering for VREF. Filter capacitors CL2and CL3along with the resistor shown as ESR are part of another disclosed second circuit shown as120″.

For a disclosed packaged device for the mixed signal stacked die device300, the arrangement can follow the packaged IC100inFIG.1Aor the packaged IC150inFIG.1Bdescribed above, where the attachment layer125secures the second circuit120′ and second circuit120″ to the top of the mixed signal IC110′ that provides a gap126which would be over the voltage reference circuit315. The gap126being free of mold compound in the packaged IC formed between the voltage reference circuit315of the mixed signal IC110′ and the second circuits120′,120″ creates a low stress environment for the voltage reference circuit315, similar to a costly open cavity ceramic package. Although the second circuits120′ and120″ are described above both being on top of the voltage reference circuit315, one or both of the second circuits120′,120″ can cover the SAR ADC310, as both of these circuits are generally stress sensitive.

In operation, the SAR ADC310converts an analog input voltage received shown as Vin to a digital code shown only by example for simplicity as a 3 bit digital output (shown as Dout). The overall mixed signal IC300accuracy and repeatability depend on how effectively the SAR ADC310executes this conversion process. The ADC's310actual transfer function has an offset-voltage error and a gain error. The ADC's310output code is directly proportional to the Vin level and inversely proportional to the combination of the Vref value plus the gain error. The DC shift of the voltage reference generator315ainversely impacts the gain accuracy of the ADC310, which is minimized by the gap126within the attachment layer125that secures the second circuit120′ to the top of the mixed signal IC110′ being over the voltage reference circuit315, along with minimizing the parasitic s due to the second circuit120′ being within the package with the mixed signal IC110′ as opposed to conventionally being mounted on a PCB.

Applied to ICs with reference voltage circuits, for a given voltage reference circuit topology, compared to conventional arrangements having filter capacitors on the PCB, disclosed packaged ICs having filter capacitor(s) within the package provides a lower reference voltage shift due to mainly reduced parasitics, lower sensitivity to humidity changes due to the gap being absent of hydroscopic mold compound, less thermal hysteresis as the gap helps the Δ CTE, as well as better long term Vref stability because the stress induced by the package mold compound changes over time. Initially this is due to additional curing of the mold compound, but also there is relaxation of stress with thermal cycling. Soldering vaporizes moisture absorbed in the hydroscopic material, shifting its stress. Soldering is in itself a thermal hysteresis cycle which changes stress. Attachment to the PCB adds an additional stress due to CTE mismatch of the PCB coupled to the IC via the mold compound and leadframe. Disclosed arrangements for reference circuits also provide higher Vref accuracy by avoiding errors due to PCB leakage.

Disclosed aspects can be integrated into a variety of assembly flows to form a variety of different packaged IC devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

Those skilled in the art to which this Disclosure relates will appreciate that many variations of disclosed aspects are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the above-described aspects without departing from the scope of this Disclosure.