Patent ID: 12230707

DETAILED DESCRIPTION

Reference now will be made in detail to embodiments of the disclosed invention, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, it will be apparent to those skilled in the art that modifications and variations can be made in the present technology without departing from the scope thereof. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents.

The terms “lateral” and “horizontal” refer to a direction or a plane parallel to the plane or surface of a substrate without regard to orientation. The term “vertical” refers to a direction perpendicular to the horizontal. Terms, such as “on”, “above”, “bottom”, “top”, “side”, “upper”, and “over”, are defined with respect to the horizontal plane. The term “monotonically decreasing” refers to always decreasing or remaining constant, and not increasing.

The lightly doped drain (LDD) region of a lateral diffusion field effect transistor (LDFET) provides the device with an increased breakdown voltage at the expense of increasing the on-resistance of the transistor. Increasing the breakdown voltage of the transistor can be achieved by decreasing the doping level of the LDD or by extending the lateral expanse of the LDD. Both of these approaches, however, increase the on-resistance of the LDFET either by reducing the conductivity of the LDD or increasing the length of the LDD region, which is directly proportional to the impedance of the region in the direction of current flow. This interrelationship presents a difficult design problem because the on-state resistance of a power device must be kept low or the device will burn a significant amount of power when it sinks the large currents that power devices are meant to handle.

The present disclosure describes a semiconductor structure that includes at least one lateral diffusion field effect transistor with a source contact and a gate shield (also referred to as a “shield plate”) structure that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size for a given fabrication process. In particular, the gate shield structure defines a bottom recess above the ohmic region that is narrower than the minimum contact feature size, and a flared section that flares outward with distance from the ohmic region to extend above and beyond the ohmic region. Equivalently, the flared section may be characterized as a tapered section that has a lateral width that decreases from a top portion of the tapered section to a bottom portion of the tapered section. In some examples, the flared/tapered section monotonically flares outward with increasing distance from the ohmic region and monotonically tapers inward with decreasing distance from the ohmic region. By providing a wider area for the formation of the source contact, the flared gate shield section allows the width of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.

FIG.3shows an example n-channel LDFET50according to an embodiment. The LDFET50exhibits a narrower cell pitch as a result of having a gate shield48that defines a support structure for forming a bottom portion52of the source contact54that is narrower than the minimum contact feature size. In particular, a configuration in which the bottom portion52of the source contact54is narrower than the minimum contact feature size allows the gate56to be laterally positioned closer to the source contact54(e.g., as measured along the lateral dimension58) without violating the contact spacing requirements specified for the fabrication process. This allows the cell pitch to be shortened. In some examples, the width of the ohmic region70is at least as wide as the lateral dimension corresponding to the combined width of the bottom portion of the source contact54and the widths of the vertical extensions71,73of the gate shield48from the bottom of the gate shield on the ohmic region70.

The LDFET50includes an active region59. The active region59includes a source region60, a channel region62, a lightly doped drain region64, and a drain region66. The source region60, the lightly doped drain region64, and the drain region66can include doped semiconductor material formed by, for example, the implant of impurities into the active region59. The doped semiconductor material of each of the source region60, the lightly doped drain (LDD) region64, and the drain region66has a similar conductivity type (e.g., n-type), which is the opposite conductivity type of the channel62(e.g., p-type). Each region60,64, and66can be formed with the same dopant species by implanting the same kind of dopant in the respective region. The lightly doped drain (LDD) region64has a lower dopant concentration than the source region60. The lightly doped drain (LDD) region64improves the performance of the LDFET50by blocking large voltages and sinking large currents without degrading. Source region60is electrically coupled to a source contact54through the ohmic region70and the gate shield48. The drain region66is electrically coupled to the drain contact68. The drain region66can be a highly doped drain region and can form an electrically conductive path between the drain contact68and the lightly doped drain (LDD) region64.

The LDFET50also includes a gate56overlying a gate oxide layer57on the active region59. In the illustrated example, the gate56includes a bottom electrically conductive layer74(e.g., polysilicon) and a metal silicide (e.g., cobalt or tungsten silicide) top layer76.

The source contact54and drain contact68provide electrical connections to the LDFET50from other circuitry that may or may not be integrated with the LDFET50on the same integrated circuit. In the illustrated example, the source region60and the body region72are electrically coupled to the source contact54through the gate shield48by a silicide layer70that is formed on the surface of the source region60and a body region72. In general, the source region60and the body region72can be electrically coupled to the source contact54using any process that forms an ohmic or non-rectifying contact with the two regions of the structure. The connection between the drain contact68and the drain region66can include any of the variations described above in connection with the source contact54and the source region60. The source contact54and the drain contact68can include a metal, metal alloy, metal silicide, or an electrically conductive semiconductor material such as doped polysilicon. Exemplary metals, metal alloys, and metal silicides can each include copper, tungsten, molybdenum, and aluminum.

In various embodiments, the active region59can be a doped portion of the bulk of a semiconductor wafer, a localized well formed in a larger doped portion of a semiconductor wafer, the active region of a semiconductor-on-insulator (SOI) wafer, or a localized well formed in an SOI wafer. In the illustrated example, the active region59is a thin film formed over a buried insulator67of a SOI substrate69(e.g., a p-type or n-type substrate).

In an example operation of the LDFET50, a conduction current flows from the source contact54to the source region60, through the channel region62, the lightly doped drain region64, and the drain region66, and into the drain contact68. In this process, the source contact54may be tied to ground potential and the drain68may be biased at a positive voltage level. The LDFET50operates as a switch by presenting a variably electrically conductive path between the drain contact68and the source contact54through the channel62, which has a first conductivity type (e.g., p-type) and separates the source region60and the LDD region64, each of which has a second conductivity type (e.g., n-type). The voltage applied to the gate56controls the polarity of free carriers in the channel62. When the free charge in the channel62is of the same conductivity type as the source and the LDD regions60,64current will flow in the channel62, where the magnitude of the gate voltage controls the magnitude of the free charge current of the same conductivity type as the source and the LDD regions60,64.

The gate shield48is located above the gate electrode56and the LDD region64. The gate shield48is electrically coupled to the source region60and the body region72by a silicide layer70(e.g., a metal silicide layer, such as tungsten silicide, titanium silicide, and cobalt silicide) that forms an ohmic contact between the gate shield48and the source and body regions60,72. In some examples, during or after the gate56has been formed, a first dielectric layer (e.g., silicon nitride or an interlayer dielectric) is deposited on the gate56and patterned (e.g., by etching) to create a via for depositing the silicide layer for the ohmic contact70and create a surface corresponding to the desired shape of the gate shield48. The gate shield48is formed by depositing an electrically conductive material (e.g., Ti—TiN) on the patterned dielectric layer and etching the deposited material to create the gate shield48. A second dielectric layer (e.g., an interlayer dielectric layer) is deposited on the gate shield48. A source contact via is etched into the second dielectric layer to the gate shield and filled with an electrically conductive plug (e.g., a metal, such as Ti/TiN/W) to form the source contact54. A drain contact via is etched into the second dielectric layer to the drain region66and filled with an electrically conductive material (e.g., a metal plug, such as Ti/TiN/W).

FIG.4shows an example LDFET80according to another embodiment that corresponds to a p-channel version of the LDFET50described above in connection withFIG.3. The LDFET80exhibits a narrower cell pitch as a result of having a gate shield82that defines a support structure for forming a bottom portion84of the source86that is narrower than the minimum contact feature size.

FIG.5shows an example LDFET90according to another embodiment that corresponds to the LDFET50described above except that, instead of contacting the source and body regions60,72with an ohmic region70at the top surface of the active region59, as shown inFIG.3, the source contact92extends vertically into the active region94to contact the source and body regions96,98,104. In the illustrated example, the source contact92is electrically connected to the deep P+ region104through the gate shield100and metal silicide ohmic region102. The LDFET90exhibits a narrower cell pitch as a result of having a gate shield100that defines a support structure for forming a bottom portion105of the source contact92above the active region94that is narrower than the minimum contact feature size.

In some embodiments, the deep P+ region104of the LDFET90shown inFIG.5extends upward to surround the sides of the silicide region102and partially into the N+ regions (e.g., region96) adjacent the bottom portion of the shield plate100surrounding the narrowed bottom portion105of the source contact92.

FIG.6shows an example LDFET110according to another embodiment that corresponds to a p-channel version of the LDFET90described above in connection withFIG.5. The LDFET110exhibits a narrower cell pitch as a result of having a gate shield112that defines a support structure for forming a bottom portion114of the source contact116that is narrower than the minimum contact feature size. In some embodiments, the deep N+ region104of the LDFET110shown inFIG.6extends upward to surround the sides of the silicide region and partially into the overlying P+ regions adjacent the bottom portion of the shield plate112surrounding the narrowed bottom portion114of the source contact116.

FIG.7shows an example top semitransparent projection view of the LDFET50half cell shown inFIG.3taken along the line7-7in which multiple pairs of n-type source60and p-type body regions72are arranged orthogonally with respect to the length of the gate electrode56, which extends into the plane of the drawing shown inFIG.3.

FIG.8shows an example top semitransparent projection view of the LDFET50half cell shown inFIG.3taken along the line7-7in which multiple pairs of n-type source60and p-type body regions72are alternately arranged in parallel with respect to the length of the gate electrode56, which extends into the plane of the drawing shown inFIG.3.

While the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.