Patent ID: 12237557

DETAILED DESCRIPTION OF THE INVENTION

The present disclosure will be described below with reference to the accompanying drawings, where like features are denoted by the same reference labels throughout the detail description of the drawings and in connection with embodiments.

The terms “first,” “second,” and the like herein are used to distinguish similar objects and are not necessarily used to describe a particular order or order of precedence.

Embodiments of the present disclosure provide a power divider.FIG.3is a schematic structural diagram of a power divider according to an embodiment of the present disclosure. As shown inFIG.3, the power divider includes M power division units, wherein the M power division units are cascade connected to form a cascade structure of N levels (i.e. First Level, Second Level, . . . , Nth Level), each of the power division units includes one input port and two output ports, and power division units in a Kth level in the cascade structure satisfies relationships of: input impedance of the Kth level of power division units conjugate-matches output impedance of a unit connected to an input port of the power division unit in the Kth level, and output impedance of the power division unit in the Kth level conjugate-matches load impedance of the power division unit in the Kth level, where N, K, and M are positive integers greater than or equal to 1. The power divider comprises Input Port, Output Port 1, Output Port 2, Output Port 3, Output Port 4, Output Port (2N−3) Output Port (2N−2), Output Port (2N−1), Output Port (2N)), characteristic resistance ZS, Z01, Z02, . . . , Z0N, Z1, Z2, . . . , ZN.

According to the embodiments of the present disclosure, since the input impedance of power division units in each level conjugate-matches the output impedance of the unit connected to the input port of power division units in the respective level, and the output impedance of power division units in each level conjugate-matches the load impedance of power division units in the respective level. In this way, the inter-level impedance of the power divider is no longer a fixed impedance value, and may be a specified complex impedance, such that a length of power division units in each level is shortened, the problem of a larger area of the power divider due to a longer length of a signal line of the power divider is solved, an overall area of the power divider is reduced, and the loss of the power divider is reduced.

In an embodiment, in a case where N, M, and K are equal to 1, input impedance of a power division unit in a first level conjugate-matches target source impedance of the power divider, and output impedance of the power division unit in the first level conjugate-matches target load impedance of the power divider, where the target source impedance and the target load impedance of the power divider are pre-determined. In a case where M is greater than or equal to 3, N is greater than or equal to 2, and K is equal to 1, the input impedance of the power division unit in the first level conjugate-matches the target source impedance of the power divider, and the output impedance of the power division unit in the first level conjugate-matches load impedance of the power division unit in the first level. In a case where M is greater than or equal to 3, N is greater than or equal to 2, and K is greater than or equal to 2 and less than N, input impedance of the power division unit in the Kth level conjugate-matches output impedance of a power division unit in a (K−1)th level, and output impedance of the power division unit in the Kth level conjugate-matches load impedance of the power division unit in the Kth level, where K is a positive integer in a range of 2 to N−1. In a case where M is greater than or equal to 3, N is greater than or equal to 2, and K is equal to N, the input impedance of the power division unit in the Kth level conjugate-matches the output impedance of the power division unit in the (K−1)th level, and the output impedance of the power division unit in the Kth level conjugate-matches the target load impedance of the power divider.

In an embodiment, the power divider further includes an impedance isolation unit. The impedance isolation unit is connected between the two output ports of each power division unit. The impedance isolation unit is configured to regulate output impedance of the power division unit so that the output impedance of the power division unit conjugate-matches the load impedance of the power division unit.

In an embodiment, the impedance isolation unit includes a resistor and a capacitor connected in parallel.

In an embodiment, in a case where M is greater than or equal to 3 and N is greater than or equal to 2, input impedance and/or output impedance corresponding to all or some of intermediate ports in the power divider are not equal to the target source impedance or the target load impedance of the power divider, where the intermediate ports are input ports or output ports in the power divider between a power divider input port and a power divider output port.

When the power divider includes two or more levels of power division units, the input impedance or the output impedance of some or all of the intermediate ports may not be equal to the target source impedance or the target load impedance of the power divider, where the intermediate ports are input ports or output ports in the power divider between the power divider input port and the power divider output port. For example, the intermediate ports include all ports connected between the output ports of the power division units in the first level of the power divider and the input ports of the power division units in the last level of the power divider, and further includes the output ports of the power division unit in the first level and the input ports of the power division units in the last level.

Embodiments of the present disclosure further provide a regulation method applicable to a power divider, for example, the power divider described in the above embodiments.FIG.4is a flowchart of a regulation method according to an embodiment of the present disclosure. As shown inFIG.4, the regulation method includes steps as follows.

In S402, input impedance of a power division unit in a Kth level is regulated so that the input impedance of the power division unit in the Kth level conjugate-matches output impedance of a unit connected to an input port of the power division unit in the Kth level.

In S404, output impedance of the power division unit in the Kth level is regulated so that the output impedance of the power division unit in the Kth level conjugate-matches load impedance of the power division unit in the Kth level. Herein the power divider includes M power division units, the M power division units are cascade connected to form a cascade structure of N levels, and each of the power division units includes one input port and two output ports, where N, K, and M are positive integers greater than or equal to 1.

According to the aforementioned steps, since the input impedance of power division units in each level conjugate-matches the output impedance of the unit connected to the input port of power division units in the respective level, and the output impedance of power division units in each level conjugate-matches the load impedance of power division units in the respective level. In this way, the inter-level impedance of the power divider is no longer fixed impedance value, and may be specified complex impedance, such that a length of power division units in each level is shortened, the problem of a larger area of the power divider due to a longer length of a signal line of the power divider is solved, an overall area of the power divider is reduced, and the loss of the power divider is reduced.

In an embodiment, the steps of regulating the input impedance of the power division unit in the Kth level so that the input impedance of the power division unit in the Kth level conjugate-matches the output impedance of the unit connected to the input port of the power division unit in the Kth level and regulating the output impedance of the power division unit in the Kth level so that the output impedance of the power division unit in the Kth level conjugate-matches the load impedance of the power division unit in the Kth level include steps as follows.

In a case where N, M, and K are equal to 1, input impedance of a power division unit in a first level is regulated to conjugate-match the target source impedance of the power divider, and output impedance of the power division unit in the first level is regulated to conjugate-match the target load impedance of the power divider, where the target source impedance and the target load impedance of the power divider are pre-determined. In a case where M is greater than or equal to 3, N is greater than or equal to 2, and K is equal to 1, the input impedance of the power division unit in the first level is regulated to conjugate-match the target source impedance of the power divider, and the output impedance of the power division unit in the first level is regulated to conjugate-match the load impedance of the power division unit in the first level. In a case where M is greater than or equal to 3, N is greater than or equal to 2, and K is greater than or equal to 2 and less than N, the input impedance of the power division unit in the Kth level is regulated to conjugate-match output impedance of a power division unit in a (K−1)th level, and output impedance of the power division unit in the Kth level is regulated to conjugate-match load impedance of the power division unit in the Kth level, where K is a positive integer in a range of 2 to N−1. In a case where M is greater than or equal to 3, N is greater than or equal to 2, and K is equal to N, the input impedance of the power division unit in the Kth level is regulated to conjugate-match the output impedance of the power division unit in the (K−1)th level, and the output impedance of the power division unit in the Kth level is regulated to conjugate-match the target load impedance of the power divider.

In an embodiment, the output impedance of the power division unit in the Kth level is regulated by: regulating a characteristic impedance and/or a length of microstrip line of the power division unit, and/or regulating output impedance of the power division unit by an impedance isolation unit connected between the two output ports of the power division unit.

In an embodiment, in a case where M is greater than or equal to 3 and N is greater than or equal to 2, input impedance and/or output impedance corresponding to all or some of intermediate ports in the power divider after regulation are not equal to the target source impedance or the target load impedance of the power divider, where the intermediate ports are input ports or output ports in the power divider between a power divider input port and a power divider output port.

Embodiments of the present disclosure further provide a power allocation method, including performing power allocation using the power divider as described in any of the above embodiments.

The embodiment of the present disclosure provides a method for configuring a miniaturized power divider, through which a power divider having an area reduced to at least one third of an original area and a reduced transmission loss can be obtained.

FIG.5is a schematic flowchart of implementing a miniaturized power divider according to an embodiment of the present disclosure. As shown inFIG.5, the method for configuring a miniaturized power divider according to the embodiment of the present disclosure includes steps as follows.

In a first step, it is determined that a one-2Npower divider with source impedance ZSand load impedance ZLis required, for example, target source impedance and target load impedance of the power divider are pre-determined so that input impedance and output impedance of the power divider conjugate-match the source impedance and the load impedance.

In a second step, one-two power divider with input impedance of Zin1and output impedance matching load impedance of ZL1is obtained.

According to the embodiment of the present disclosure, the input port of the power divider matches the signal source impedance ZS, the input impedance is Zin1=ZS*, and the load impedance of the one-two power divider in the first level is ZL1. The microstrip line used in the power divider has characteristic impedance of Z01and a length of l1.

The output impedance and the load impedance of the one-two power divider in the first level conjugate-match each other to obtain good transmission characteristics. An impedance isolation unit is connected between two output ports of the one-two power divider in the first level, and the impedance isolation unit Z1may be formed by a resistor R1and a capacitor C1connected in parallel. The resistor R1and the capacitor C1not only serve to improve isolation, but also regulate the output impedance to conjugate-match the load impedance.

In a third step, one-two power dividers in a second level with input impedance of Zin2and output impedance matching load impedance of ZL2are obtained and then cascade connected with the power divider obtained in the second step to obtain a one-four power divider.

According to the embodiment of the present disclosure, the input ports of the one-two power dividers in the second level match the output impedance ZL1* of the one-two power divider in the first level, and the input impedance is Zin2=ZL1. The microstrip line used in the power divider has characteristic impedance of Z02and a length of l2.

The output impedance and the load impedance of the one-two power dividers in the second level conjugate-match each other to obtain good transmission characteristics. An impedance isolation unit is connected between two output ports of the one-two power divider in the second level, and the impedance isolation unit Z2may be formed by a resistor R2and a capacitor C2connected in parallel. The resistor R2and the capacitor C2not only serve to improve isolation, but also regulate the output impedance to conjugate-match the load impedance.

One-two power dividers with input impedance of Zinkand output impedance matching load impedance of ZLkare obtained and then cascade connected with the power divider obtained in the third step to obtain a one-2kpower divider, where k=2, 3, . . . , N−1.

According to the embodiment of the present disclosure, the input ports of the one-two power dividers in the kth level match the output impedance ZL(k−1)* of the one-two power dividers in the (k−1)th level, and the input impedance is Zink=ZL(k−1). The load impedance of the one-two power dividers in the kth level is ZLk. The relationship between Zinkand ZLkis defined by:

Zink=12·Z0⁢k⁢ZLk+jZ0⁢k⁢tan⁢(β⁢lk)Z0⁢k+jZLk⁢tan⁢(β⁢lk),
where Z0kis characteristic impedance of the one-two power dividers in the kth level, lkis a length of the one-two power dividers in the kth level, ZLk is load impedance of one-two power dividers in the kth level, Zinkis input impedance of the one-two power dividers in the kth level, and β=2π/λ, where λ is a wavelength.

The output impedance and the load impedance of the one-two power dividers in the kth level conjugate-match each other to obtain good transmission characteristics. An impedance isolation unit is connected between two output ports of the one-two power divider in the kth level, and the impedance isolation unit Zkmay be formed by a resistor Rkand a capacitor Ckconnected in parallel. The resistor Rkand the capacitor Cknot only serve to improve isolation, but also regulate the output impedance to conjugate-match the load impedance.

In a fourth step, one-two power dividers in a Nth level with input impedance of ZinNand output impedance matching load impedance of ZLNare obtained and then cascade connected with the power divider obtained in the previous step to obtain a one-2N power divider.

According to the embodiment of the present disclosure, the input ports of the one-two power dividers in the Nth level match the output impedance ZL(N−1)* of the one-two power dividers in the (N−1)th level, and the input impedance of the input ports of the one-two power dividers in the Nth level is ZinN=ZL(N−1). The load impedance of the one-two power dividers in the Nth level is ZLN=ZL. The microstrip line used in the power divider has characteristic impedance of Z0Nand a length of lN.

The output impedance and the load impedance of the one-two power dividers in the Nth level conjugate-match each other to obtain good transmission characteristics. An impedance isolation unit is connected between two output ports of the one-two power divider in the Nth level, and the impedance isolation unit ZNmay be formed by a resistor RNand a capacitor CNconnected in parallel. The resistor RNand the capacitor CNnot only serve to improve isolation, but also regulate the output impedance to conjugate-match the load impedance.

In a fifth step, the above power dividers are cascade connected to form a one-2Npower divider.

According to the embodiment of the present disclosure, the one-2Npower divider with N levels is formed by connecting 2N−1 power dividers. A one-two power divider is provided in the first level, two one-two power dividers are provided in the second level, four one-wo power dividers are provided in the third level, and so on, N−1 power dividers are provided in the N level.

An input port of the one-two power divider in the first level is connected to the source impedance, and a signal is transferred from the source impedance to the input port of the one-two power divider in the first level. Two output ports of the one-two power divider in the first level are respectively connected to input ports of two one-two power dividers in the second level, such that the signal is divided equally into four quarters by the power dividers in the first and second levels. By analogy, an input port of an one-two power divider in a kth level connects an output port of an one-two power divider in a (k−1)th level; 2koutput ports of one-two power dividers in the kth level connect input ports of one-two power dividers in the (k+1)th level. two output ports of a one-two power divider in the (N−1)th level are respectively connected to input ports of two one-two power dividers in the Nth level, such that the signal is divided equally into 2Ndivisions by the power dividers in the first to Nth levels.

The conventional Wilkinson power divider uses power dividers with arm lengths of one-quarter wavelength to achieve matching of the output ports and the input ports to 50 ohm. In the embodiment of the present disclosure, with the flexible impedance matching, the multiple levels of one-two power dividers do not need to be limited to the one-quarter wavelength, thereby reducing the arm lengths of the power dividers and reducing the size of the power divider. This method is applicable and effective both in board-level circuits and in chip circuits. With the method according to the embodiment of the present disclosure, transmission loss, area and manufacturing cost are reduced.

A one-sixteen power divider designed according to the theory discussed in the embodiments of the present disclosure effectively solves the problems of the conventional power divider. The overall structure of the power divider is shown inFIG.6, which is a specific example of the one-2Npower divider inFIG.3. As shown inFIG.6, the power divider comprises 4 levels (i.e. First Level, Second Level, Third Level, Fourth Level), further comprises Input Port, Output Port 1, Output Port 2, Output Port 3, Output Port 4, . . . , Output Port 13, Output Port 14, Output Port 15, Output Port 16, characteristic impedance ZS, Z01, Z02, Z03, Z04, Z1, Z2, Z3, Z4.

In each level of one-two power dividers designed in the embodiment of the present disclosure, the relationship between input impedance Zinand load impedance ZLis defined by:

Zin=12·Z0⁢ZL+jZ0⁢tan⁢(β⁢l)Z0+jZL⁢tan⁢(β⁢l)
where,

β=2⁢π/λg,λg=λ/εr,
λgis a wavelength of a signal in microstrip medium, λ is a wavelength of the signal in vacuum, and εris a dielectric constant of the microstrip medium.

Different from the conventional power divider designs, the Zinand ZLherein are not constant to 50 ohm, but an intermediate impedance value that can be implemented. Similarly, the arm lengths l of the power dividers is not one-quarter wavelength, but a value determined by the input impedance and output impedance.

The power divider of the embodiment of the present disclosure includes microstrip lines, and a signal line is thick metal layer at a top layer, a bottom layer of metal serves as a ground plane, a working frequency band is 37 GHz to 40 GHz, the one-quarter wavelength is about 1200 m, and the input impedance and output impedance are 50 ohm.

In a one-two power divider in the first level of the one-sixteen power divider according to the embodiment of the present disclosure, input impedance needs to match 50 ohm, and output impedance does not need to match 50 ohm, so that a length of a microstrip line does not need to be a length of one-quarter wavelength. The characteristic impedance of the microstrip line is 50 ohm, the output impedance of the output ports is 56 ohm-j25 ohm, the length is 387 μm and is one third of one-quarter wavelength. Isolation between output ports is optimized by isolation resistance and capacitance.

In one-two power dividers in the second level of the one-sixteen power divider according to the embodiment of the present disclosure, input impedance is 56 ohm+j25 ohm that matches the power divider in the first level, and a microstrip line with characteristic impedance of 50 ohm is also used to realize dividing the power into two halves. The microstrip line has a length of 330 μm and is one third of one-quarter wavelength. The output impedance of the output port is 40 ohm-j40 ohm, and isolation between the output ports is optimized by the isolation resistance and capacitance.

In one-two power dividers in the third level of the one-sixteen power divider according to the embodiment of the present disclosure, input impedance is 40 ohm+j40 ohm that matches the power dividers in the second level, and a microstrip line with characteristic impedance of 50 ohm is also used to realize dividing the power into two halves. The microstrip line has a length of 290 m. The output impedance of the output port is 30 ohm-j42 ohm, and isolation between the output ports is optimized by the isolation resistance and capacitance.

In one-two power dividers in the fourth level of the one-sixteen power divider according to the embodiment of the present disclosure, input impedance is 30 ohm+j42 ohm that matches the power dividers in the third level, and output impedance needs to match 50 ohm. Isolation between the output ports is optimized by the isolation resistance and capacitance.

The first level of one-two power divider, the second level of one-two power dividers, the third level of one-two power dividers and the fourth level of one-two power dividers are cascade connected to obtain a one-sixteen power divider. In the one-sixteen power divider according to the embodiment of the present disclosure, a one-two power divider is provided in the first level, two one-two power dividers are provided in the second level, four one-two power dividers are provided in the third level and eight one-two power dividers are provided in the fourth level. The length of one-two power dividers in each level of the conventional Wilkinson power divider is one-quarter wavelength, while the length of the one-two power dividers in each level of the power divider according to the embodiment of the present disclosure is merely one third of the former. The total area of the power divider is 1.3 mm*1.3 mm, which greatly reduces the area cost of the chip compared with the conventional power divider.

In addition, the length of the one-sixteen power divider is shortened, and loss due to parasitism of the microstrip signal line is also reduced, such that the transmission loss of the power divider according to the embodiment of the present disclosure is reduced.

In the frequency band of 37 GHz to 40 GHz, the loss of the one-sixteen power divider is less than 1 dB, the isolation between the output ports is less than −20 dB, and the return loss of the input port S11is less than −10 dB. A graph of the return loss (dB) vs. frequency (GHz) of the one-sixteen power divider is shown inFIG.7.

In conclusion, the one-sixteen power divider is configured based on the method for configuring a one-2Npower divider provided in the embodiment of the present disclosure, and has improved performance indexes and an area reduced to about one third of that of the traditional Wilkinson power divider, which greatly saves the cost for circuit design and is suitable for popularization in the circuit design.

In the description of the above embodiments, the method according to the above embodiments may be implemented by software and a necessary general hardware platform, or may be implemented by hardware. The technical solutions of the present disclosure may essentially be embodied in the form of a software product stored in a storage medium (e.g., Read-Only Memory, Random Access Memory, magnetic disk, optical disk) including instructions for causing a terminal device (which may be a mobile phone, a computer, a server, a network device, or the like) to implement the method according to the embodiments of the present disclosure.

Embodiments of the present disclosure further provide a computer-readable storage medium which stores a computer program, when executed by a processor, causing the processor to implement the method according to any one of the embodiments described above.

In an embodiment, the computer-readable storage medium may be configured to store a computer program, when executed by a processor, causing the processor to implement steps as follows.

Step 1, input impedance of a power division unit in a Kth level is regulated so that the input impedance of the Kth level of power division units conjugate-matches output impedance of a unit connected to an input port of the power division unit in the Kth level.

Step 2, output impedance of the power division unit in the Kth level is regulated so that the output impedance of the power division unit in the Kth level conjugate-matches load impedance of the power division unit in the Kth level. Herein the power divider includes M power division units, the M power division units are cascade connected to form a cascade structure of N levels, and each of the power division units includes one input port and two output ports, where N, K, and M are positive integers greater than or equal to 1.

According to the aforementioned steps, since the input impedance of power division units in each level conjugate-matches the output impedance of the unit connected to the input port of power division units in the respective level, and the output impedance of power division units in each level conjugate-matches the load impedance of power division units in the respective level. In this way, the inter-level impedance of the power divider is no longer fixed impedance value, and may be specified complex impedance, such that a length of power division units in each level is shortened, the problem of a larger area of the power divider due to a longer length of a signal line of the power divider is solved, an overall area of the power divider is reduced, and the loss of the power divider is reduced.

In an embodiment, the storage medium may include, but is not limited to, a USB flash drive, a ROM, a RAM, a mobile hard disk drive, a magnetic disk, an optical disk, or other medium capable of storing a computer program.

Embodiments of the present disclosure further provide an electronic device including a memory storing a computer program and a processor configured to execute the computer program to implement the method according to any one of the embodiments described above.

In an embodiment, the electronic device may further include a transmission device and an input and output device. Both the transmission device and the input and output device are connected to the processor.

In an embodiment, the processor may be configured to execute the computer program to implement steps as follows.

Step 1, input impedance of a power division unit in a Kth level is regulated so that the input impedance of the power division unit in the Kth level conjugate-matches output impedance of a unit connected to an input port of the power division unit in the Kth level.

Step 2, output impedance of the power division unit in the Kth level is regulated so that the output impedance of the power division unit in the Kth level conjugate-matches load impedance of the power division unit in the Kth level. Herein the power divider includes M power division units, the M power division units are cascade connected to form a cascade structure of N levels, and each of the power division units includes one input port and two output ports, where N, K, and M are positive integers greater than or equal to 1.

According to the aforementioned steps, since the input impedance of power division units in each level conjugate-matches the output impedance of the unit connected to the input port of power division units in the respective level, and the output impedance of power division units in each level conjugate-matches the load impedance of power division units in the respective level. In this way, the inter-level impedance of the power divider is no longer a fixed impedance value, and may be a specified complex impedance, such that a length of power division units in each level is shortened, the problem of a larger area of the power divider due to a longer length of a signal line of the power divider is solved, an overall area of the power divider is reduced, and the loss of the power divider is reduced.

For specific examples in this embodiment, reference may be made to the examples described in the above embodiments which will not be repeated herein.

The modules or steps of the present disclosure described above may be implemented with a general purpose computing device, and may be centralized on a single computing device, or distributed over a network of multiple computing devices, optionally, may be implemented by program code executable by the computing device such that they may be stored in a storage device for execution by the computing device, and in some cases, the steps shown or described may be performed in a different order than described herein, or they may be fabricated separately as a plurality of integrated circuit modules, or multiple modules or steps among them may be fabricated as a single integrated circuit module. As such, the present disclosure is not limited to any particular combination of hardware and software.