Patent ID: 12222611

Like reference numerals refer to corresponding parts throughout the several views of the drawings.

DESCRIPTION OF IMPLEMENTATIONS

Reference will now be made in detail to implementations, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described implementations. However, it will be apparent to one of ordinary skill in the art that the various described implementations may be practiced without these specific details. In other instances, well-known methods, procedures, components, mechanical structures, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the implementations.

This application introduces a new output pad sequence design to significantly reduce the fan-out area (specifically, the height of the fan-out area) to fit into a substantially narrow bezel of a display screen. The new output pad sequence design is incorporated on a driver chip that is disposed in proximity to the fan-out area and flip-chip coupled to wires formed on a display substrate of the display screen. The display substrate is optionally made of glass, and the driver chip is coupled to the display substrate via chip-on-glass (COG) bonding. Interconnects coupling display and/or capacitive sense elements to pads of the driver chip are adjusted according to the new output pad sequence design. For example, a subset of interconnects are routed to take a detour to access corresponding pads in the new output pad sequence design from side edges of the driver chip, rather than accessing the corresponding pads from a top edge of the driver chip directly. This addresses the challenge of routing all of the interconnects from the top edge, thereby reducing the height of the fan-out area and the width of a bezel area containing the fan-out area. Thinner bezels help maximize the screen real estate of a laptop and make multiple desktop displays look more like a single screen when placed side by side.

FIG.1Ais a block diagram illustrating an electronic device100, in accordance with some implementations, andFIG.1Bis an exploded view of a display screen125of the electronic device inFIG.1A, including a plurality of structural layers, in accordance with some implementations. The electronic device100includes a processing device110that is electrically coupled to the display screen125having a display pixel array. The display pixel array further includes a plurality of display elements driven between a plurality of display electrodes and one or more common electrodes. Each display element is disposed between a display electrode and a common electrode. In a display driving state, a voltage bias is generated by the processing device110and applied between the display and common electrodes of each display element to enable display of a color on the respective display element. In the depicted implementation, the display and/or common electrodes are electrically coupled to the processing device110via a bus124, and configured to receive display driving signals (e.g., the voltage bias that enables display of the color on each display pixel) from the processing device110via the bus124.

In some implementations, the display screen125further includes a capacitive sense array128including a two-dimensional array of capacitive sense elements. Each capacitive sense element is formed by a respective intersection of (i) a respective row electrode in a first electrode layer and (ii) a respective column electrode in a second electrode layer. The processing device110operates in a touch sensing state in addition to a display driving state. In the touch sensing state, the processing device110is configured to measure capacitance variations at the row and column electrodes and detect one or more touches on or proximate to a surface of the display screen125. In some implementations, the processing device110alternates between the display driving state and the touch sensing state according to a predetermined duty cycle (e.g., 80%) for the display driving state, and detects a contact with or a proximity to a touch sensing surface associated with the display pixel array at a distinct duty cycle, thereby avoiding interfering with display operations of the display pixel array during the predetermined duty cycle. In some implementations, the processing device110operates in the display driving state and the touch sensing state concurrently by two separate circuit blocks (e.g., a pixel drive circuit102and a capacitance sense circuit101). These circuits implement display operations via the display pixel array and detect a contact with or a proximity to a touch sensing surface associated with the display pixel array. The capacitive sense array128is coupled to the processing device110via a bus122, and the capacitive sense array128is configured to provide capacitive sense signals to the capacitance sense circuit101of the processing device110via the bus122.

In some implementations, the processing device110includes analog and/or digital general purpose input/output (“GPIO”) ports107. The GPIO ports107may be programmable. The GPIO ports107may be coupled to a Programmable Interconnect and Logic (“PIL”), which acts as an interconnect between the GPIO ports107and a digital block array of the processing device110(not shown). In some implementations, the digital block array is configured to implement a variety of digital logic circuits (e.g., DACs, digital filters, or digital control systems) using configurable user modules (“UMs”). The digital block array may be coupled to a system bus. The processing device110may also include memory, such as random access memory (“RAM”)105and non-volatile memory (“NVM”)104. The RAM105may be static RAM (“SRAM”). The non-volatile memory104may be flash memory, which may be used to store firmware (e.g., control algorithms executable by processing core109to implement operations described herein). The processing device110may also include a memory controller unit (“MCU”)103coupled to the memory and the processing core109. The processing core109is a processing element configured to execute instructions or perform operations stored in the memory for the purposes of driving the display pixel array or detecting touches on the touch sensing surface. It should also be noted that the memory may be internal to the processing device110or external to it.

Some or all of the operations of the processing core109may be implemented in firmware, hardware, software, or some combination thereof. The processing core109may provide display information to the pixel drive circuit102, such that the pixel drive circuit102can be configured to drive individual display elements in the display screen125to display images or videos based on the display information. In some implementations, the processing core109includes the pixel drive circuit102. In some implementations, the processing core109includes some or all functions of the pixel drive circuit102(e.g., part or all of the pixel drive circuit102is integrated into the processing core109). Additionally, in some implementations, the processing core109receives signals from the capacitance sense circuit101, determine the state of the capacitive sense array128(e.g., determining whether an object is detected on or in proximity to the touch sensing surface), resolve where the object is on the sense array (e.g., determining the location of the object), track the motion of the object, or generate other information related to an object detected at the touch sensor. In some implementations, the processing core109includes the capacitance sense circuit101. In some implementations, the processing core109performs some or all the functions of capacitance sense circuit101.

In some implementations, the processing core109generates a display driving enable signal121used to enable a display driving state (e.g., decouple the capacitance sense circuit101from the capacitive sense array128and couple the pixel drive circuit102to the common electrodes). In such a display driving state, the pixel drive circuit102enables a bias voltage and a reference voltage corresponding to an intended color on each display element of the display pixel array. The display element displays the intended color when the bias voltage and the reference voltage are applied on the display electrode and the common electrode of the respective display element. In some implementations, the processing core109generates both a touch detection enable signal120and a display driving enable signal121, which are synchronized to control the capacitance sensing circuit101and the pixel drive circuit102to detect touch locations and drive individual display elements, respectively. The touch detection enable signal120is used to enable a touch sensing state in which one or more touch locations are thereby detected if one or more objects touch the touch sensing surface of the electronic device100. The touch detection enable signal120and the display driving enable signal121can be enabled sequentially and share operation time of electrodes that are shared by the display pixel array and the capacitive sense array.

The processing device110may include internal oscillator/clocks106and a communication block (“COM”)108. In some implementations, the processing device110includes a spread-spectrum clock (not shown). The oscillator/clocks106provides clock signals to one or more of the components of processing device110. The communication block108may be used to communicate with an external component, such as an application processor150, via an application interface (“I/F”) line151. In some implementations, the processing device110may also be coupled to an embedded controller154to communicate with the external components, such as a host150. In some implementations, the processing device110is configured to communicate with the embedded controller154or the host150to send and/or receive data. The host150, as illustrated inFIG.1A, may include decision logic153that performs some or all of the operations of the processing core109. Operations of the decision logic153may be implemented in firmware, hardware, software, or a combination thereof. The host150may include a high-level Application Programming Interface (API) in the applications152, which perform routines on the received data, such as compensating for sensitivity differences, other compensation algorithms, baseline update routines, start-up and/or initialization routines, interpolation operations, or scaling operations. The operations described with respect to the processing core109may be implemented in the decision logic153, the applications152, or in other hardware, software, and/or firmware external to the processing device110. In some other implementations, the processing device110includes the host150. As such, instead of performing the operations of the processing core109locally, the processing device110may send the raw data or partially-processed data to the host150under some circumstances.

The processing device110may reside on a common carrier substrate such as an integrated circuit (“IC”) die substrate, a multi-chip module substrate, or the like. In some implementations, the components of the processing device110includes one or more separate integrated circuits and/or discrete components. In some implementations, the processing device110includes one or more other processing devices known by those of ordinary skill in the art, such as a microprocessor or central processing unit, a controller, a special-purpose processor, a digital signal processor (“DSP”), an application specific integrated circuit (“ASIC”), a field programmable gate array (“FPGA”), or the like.

In some implementations, the electronic device100is used in a tablet computer. In some implementations, the electronic device100is used in other applications, such as a notebook computer, a mobile handset, a personal data assistant (“PDA”), a keyboard, a television, a remote control, a monitor, a handheld multi-media device, a handheld media (audio and/or video) player, a handheld gaming device, a signature input device for point of sale transactions, an eBook reader, a global position system (“GPS”), or a control panel. In some implementations, the electronic device100further includes one or more alternative sense elements156configured to communicate with the processing device110via a bus157. Each alternative sense element156is optionally a capacitance based sensor or a non-capacitance sensor. Example alternative sense elements156include, but are not limited to, an ambient light sensor, a capacitive touch button, and a side touch sensor.

Referring toFIG.1B, the plurality of structural layers of a display screen125include a display element assembly166that is protected by a top glass or dielectric layer174. The display element assembly166includes a common electrode layer168and a display electrode layer170, which are separated by an intermediate LCD display layer172. The display electrode layer170and common electrode layer168are applied directly above and below the LCD display layer172to form display electrodes and common electrodes on which a voltage bias is applied to drive LCD display cells in the LCD display. In some implementations, the display screen125of the electronic device100further includes a bottom glass or dielectric layer176and/or an electric shielding178, which are disposed under the display element assembly166to support the display pixel array mechanically and shield the display pixel array from electrical noises.

In some implementations not shown inFIG.1B, a touch display screen125of the electronic device further includes a touch detection assembly having a first electrode layer, a second electrode layer, and a dielectric layer separating the first and second electrode layers. In the stack shown inFIG.1B, the touch detection assembly is optionally placed under the display element assembly166or inserted between the top glass or dielectric layer174and the display element assembly166. In some implementations, the first electrode layer, the second electrode layer, the display electrode layer170, and the common electrode layer168are distinct from each other. In some implementations, one of the first and second electrode layers is used as the display electrode layer170or common electrode layer168. For example, when the LCD display layer172is disposed below the touch detection assembly, the display electrode layer170is optionally used as the second electrode layer, and the row or column electrodes made from the second electrode layer may be reconfigured to the display electrodes of the display electrode layer170to drive the LCD display cells formed in the LCD display layer172.

In some implementations, the display screen125includes one or more additional routing layers180distinct from the display and common electrode layers applied in each display element. In a touch display screen125, the one or more additional routing layers180are also distinct from the first and second electrode layers applied in each capacitive sense element. The one of more additional routing layers180are configured to provide the buses122,124, and/or157electrically coupling the processing device110to the display screen125, thereby enabling display, touch sensing, and/or alternative sensing capabilities on the display screen125. More details on the one or more additional routing layers180are discussed below with reference toFIGS.2A-6.

FIG.2Ais an example electronic device200having a display screen125using a driver chip202, in accordance with some implementations. The display screen125includes a display area204on which display elements are formed from a common electrode layer168, a display electrode layer170, and an LCD display layer172. In some implementations, the display area204further includes an array of capacitive sense elements that are formed from two electrode layers and an intermediate dielectric layer. The display area204is surrounded by a bezel206on the display screen125. The bezel206has four bezel regions206T,206L,206R, and206B. The bottom bezel region206B includes a driver area208and a fan-out area210. The driver chip202is disposed on the driver area208and in proximity to a display edge204A of the display area204. The driver area208and the display area204are separated by the fan-out area210of the display screen125. A plurality of interconnects are routed on the fan-out area210to electrically couple the display elements and capacitive sense elements (if any) on the display area204to the driver chip202disposed on the driver area208of the display screen125. The bezel206has a bezel width D1in the bottom bezel region206B, and the fan-out area has a fan-out area height D2measured from the display edge204A of the display area204to a first edge202A of the driver chip202. In some situations, the fan-out area height D2is critical for narrowing the bezel width D1of the bottom bezel region206B, and any reduction of the fan-out area height D2helps reduce the bezel width D1of the bottom bezel region206B directly.

In some implementations, the bezel206has a bezel width that varies between the four sides of the touch display screen125(e.g., the left bezel region206L and the right bezel region206R are narrower than the bottom bezel region206B). Typically, the bezel width is identical on the left side and on the right side of the display area125. In many situations, given that the driver chip202is placed on the bottom bezel region206B, the bottom bezel region206B can only be reduced to a bezel width limit that is greater than the bezel width of any other bezel regions206T,206L and206B. In some implementations, the bezel width is reduced below a threshold bezel width at least on the left side and on the right side of the display screen125. Conversely, in some implementations, the bezel width is reduced below a threshold width at all four sides of the display screen125. For example, an industrial definition for a bezel-less electronic device requires the threshold width to be less than 2 mm, and the bezel width has to be reduced below 2 mm at all four sides of the display screen125. In some examples, a cathode ray tube has a bezel width of two inches or more, and an LCD display has a bezel width less than one inch. A small bezel width (e.g., less than 2 mm) makes the display area204of the display screen125look larger, and multiple touch display screens125look more like a single screen when placed side by side.

The driver chip202has a first edge202A facing the display area204, two second edges202B connected to the first edge202A, and a third edge202C opposite the first edge202A. The display screen125further includes a fan-in area212in proximity to the third edge202C of the driver chip202when the driver chip202is disposed on the driver area208. In some implementations, a first end of a flexible printed circuit (FPC) cable214is disposed on the fan-in area212. Interconnects are routed on the fan-in area212to electrically couple at least the driver chip202to the FPC cable214, such that the FPC cable214can provide one or more input signals to the driver chip202or receive one or more output signals from the driver chip202. The FPC cable214has a second end opposite the first end. In some implementations, the second end of the FPC cable214is electrically coupled to a processor216(e.g., a processing core109inFIG.1A), and the FPC cable214is configured to facilitate exchanging the input and output signals between the driver chip202and the processor216.

In some implementations, the interconnects routed on the fan-out area210and fan-in area212are formed on the same routing layer180. In some situations, the same routing layer180is only formed on the bezel206of the display screen125, and electrodes formed on the display and common electrode layers170and168are substantially limited on the display area204and electrically coupled to the interconnects of the routing layer180via electrical contacts located around the display area204. Alternatively, in some situations, the routing layer180is extended from one of the display and common electrode layers170and168, and the other one of the electrodes layers170and168is electrically coupled to the interconnects of the routing layer180via electrical contacts located around the display area204. Further, in some implementations, the display area204includes both display elements and capacitive sense elements. Electrodes that are formed on first and second electrode layers associated with the capacitive sense elements are substantially limited on the display area204, and electrically coupled to the interconnects of the routing layer180via electrical contacts located around the display area204. Alternatively, in some situations, the routing layer180is extended from one of the first and second electrode layers associated with the capacitive sense elements. The other one of the first and second electrode layers associated with the capacitive sense elements, display electrode layers170, and common electrode layer168are electrically coupled to the interconnects of the routing layer180via electrical contacts located around the display area204.

FIG.2Bis an example electronic device250having a display screen125using a plurality of driver chips202, in accordance with some implementations. The display elements and capacitive sense elements (if any) are electrically coupled to multiple driver chips202. The bottom bezel region206B includes a plurality of driver areas208and a fan-out area210. Each driver chip202is disposed on a respective driver area208and in proximity to a display edge204A of the display area204. The driver areas208and the display area204are separated by the fan-out area210of the display screen125. The plurality of interconnects are routed on the fan-out area210to electrically couple each driver chip202to a respective subset of the display elements and capacitive sense elements (if any) on the display area204.

Each driver chip202has a first edge202A facing the display area204, two second edges202B connected to the first edge202A, and a third edge202C opposite the first edge202A. The display screen125further includes a fan-in area212in proximity to the third edge202C of the driver chips202when the driver chips202are disposed on the driver areas208. In some implementations, interconnects are routed on the fan-in area212to electrically couple at least two immediately adjacent driver chips202to each other. In some implementations, a first end of a flexible printed circuit (FPC) cable214(also called a display data link) is disposed on the fan-in area212. Interconnects are routed on the fan-in area212to electrically couple at least a subset of the driver chips202to the FPC cable214, such that the FPC cable214can provide one or more input signals to the subset of driver chips202or receive one or more output signals from the subset of driver chips202. In some implementations, a second end of the FPC cable214is electrically coupled to a processor216(e.g., a processing core109inFIG.1A), and the FPC cable214is configured to facilitate exchange of the input and output signals between the driver chips202and the processor216and allow the processor216to coordinate operations of the driver chips202.

Referring toFIG.2A, in some implementations, the display edge204A of the display area204is substantially larger than the first edge202A of the driver chip202. In an example, the display edges204A and first edge202A are approximately 13 inches and 1 inch, respectively. A lateral width (WL) of each interconnect is measured in a direction parallel to the first edge202A of the driver chip202, and is fixed once a dimension of the first edge202A and a total number of interconnects are known. A minimal titling angle (TA) is determined for the interconnects routed on the fan-out area210based on the lateral width and a minimum feature size (MS) of each interconnect. This minimal titling angle is associated with the leftmost interconnect, and sets a minimum value for the fan-out area height D2of the fan-out area210based on a lateral distance (LD) of the leftmost interconnect. In contrast, referring toFIG.2B, the first edge202A of each driver chip202only corresponds to a portion of the display edge204A of the display area204. For example, four driver chip202are applied, and each driver chip202corresponds to a quarter of the display area204. The portion of the display edge204A and the first edge202A are approximately 2.25 inches and 1 inch, respectively. For each driver chip202, the same minimal titling angle (TA) associated with the leftmost interconnect applies. The lateral distance of the leftmost interconnect of each driver chip202is reduced, so are the fan-out area height D2of the fan-out area210and the bezel width D1of the bottom bezel region206B.

FIG.2Ca block diagram of a periphery system280coupled to a display screen125in an electronic device200or250, in accordance with some implementations. The periphery system280includes the driver chip202, a frame buffer218, and a processor216. The driver chip202includes a timing controller220and a plurality of source drivers222, and each source driver222corresponds to a respective subset of the display area204. The frame buffer218stores digital display data provided by the processor216on a frame basis. The timing controller220processes the display data received from a source (e.g., the frame buffer218, the processor216, or external computing systems including a set-top box, digital video disk player) and generates display panel interface signals for driving the source drivers222. The timing controller220receives display and control data from the processor216and generates control and data signals to cause the display data to be displayed on the display screen125. In some implementations, the timing controller220stores the received display data in the frame buffer218. The frame buffer218includes a memory configured to store the display data. To individually address each display element, the timing controller220applies control and data signals to a specified row driver and source driver222to enable or disable the pixel located at the intersection of the specified row and column. In some implementations, each display element within a column of pixels included in the display screen125is connected to a source driver222via one or more data bus lines124. The magnitude of the voltage of the display data signal carried by the one or more data bus lines124determines the amount of light transmission supplied by each corresponding display element located in the display screen125.

In some implementations, the driver chip202includes the source drivers222, and does not include the timing controller220. The timing controller220interfaces with the display screen125using the FPC cable214(also called display data link214). The display data link214includes multiple point-to-point interconnects that couple the output of the timing controller220to each source driver222. In an example, the display data link214is a point-to-point intra panel interface that conforms to the Scalable Intra Panel Interface (SIPI) standard.

The source driver222receives multi-bit digital display data from the timing controller220via a signal line included in the display data link214, converts the display data to analog voltage signals, and sends the analog voltage signals to a specified column of sub-pixels using the column line. The number of data bits used to represent a display data value determines the number of light levels that a particular sub-pixel may produce. For example, 10-bit display data may be converted into 1024 analog signal levels generated by the output buffers included in a source driver222. A measure of the intensity of the light emitted by each sub-pixel may be represented as a gray level. In one implementation, the gray level is represented by a multi-bit value ranging from 0, corresponding to black, to a maximum value. In one example, a gray level is a 10-bit value representing one of 1024 values, with a maximum value of 1023.

The source drivers222are part of the pixel drive circuit102, and are optionally integrated into a single driver chip202(FIG.2A) or a plurality of driver chips (FIG.2B). The timing controller220is also part of the pixel driver circuit102, and is optionally located on the driver chip(s)202or on an IC chip or circuit board integrating remaining components of the processing device110. In some implementations, programs enabling functions of the pixel drive circuit102may be generated and compiled for incorporation into other integrated circuits. For example, behavioral level code describing the pixel drive circuit102, or portions thereof, may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a machine-accessible medium (e.g., NVM104, RAM105, CD-ROM, hard disk, floppy disk, or flash memory). Furthermore, the behavioral level code can be compiled into register transfer level (“RTL”) code, a netlist, or a circuit layout, and stored onto a machine-accessible medium. The behavioral level code, the RTL code, the netlist, and the circuit layout may represent various levels of abstraction to describe and control the functions of the pixel drive circuit102.

The periphery system280further includes one or more of: a power management integrated circuit (PMIC) component224, a backlight light emitting diode (LED) component226, and a backlight driver228. The PMIC component224is configured to provide and manage power for the periphery system280coupled to the display screen125. The backlight LED component226is configured to apply LEDs to provide backlight illumination for LCD display cells in the display screen125, and the backlight driver228is configured to drive the backlight LED component226.

FIG.3is an example bezel region300of a display screen125in which all interconnects302contact a driver chip202from a single edge202A of the driver chip202, in accordance with some implementations. The bezel region300is immediately adjacent to a display area204, and includes a fan-out area210and a driver area208that is covered by the driver chip202. The driver chip202is disposed on the driver area208such that the first edge202A of the driver chip202is adjacent to the display area204. The driver chip202further includes one or more rows of electronic pads304proximate to the first edge202A. The display screen125further includes a plurality of interconnects302that extend from the display edge204A of the display area204to the one or more rows of electronic pads304of the driver chip202. At the display edge204A of the display area204, the plurality of interconnects302include m interconnects, where m is an integer number, and are arranged according to a predefined connection order. Starting from a right most interconnect302, the plurality of interconnects302are numbered from 1 to m successively. At the first edge202A of the driver chip202, the electronic pads304include at least m pads to be consistent with the plurality of interconnects302and are arranged according to the predefined connection order to receive the plurality of interconnects302. Starting from a right most pad onFIG.3, the one or more rows of electronic pads304are numbered from 1 to m successively.

FIG.4Ais an example bezel region400of a display screen125in which interconnects402extending from a display area204contact a single row of a driver chip202from two or more edges of the driver chip202, in accordance with some implementations. The bezel region400is immediately adjacent to a display area204, and includes a fan-out area210and a driver area208that is covered by the driver chip202. The driver chip202is disposed on the driver area208such that the first edge202A of the driver chip202is immediately adjacent to the display area204, i.e., the first edge202A faces a display edge204A of the display area204and is closer to the display area204than any other edge of the driver chip202. The driver chip202further includes a first row of electronic pads404proximate to the first edge202A. In an example, the first row of electronic pads404extends along a straight first row line406that is substantially parallel to the first edge202A. As explained above, the display screen125is used in one of a laptop display, a tablet computer display, and a mobile phone display, and the driver chip202includes at least a plurality of source drivers222configured to drive a plurality of display elements. In some implementations, the driver chip202includes a timing controller220configured to control driving of the plurality of display elements in a synchronous manner.

The display screen125further includes a plurality of interconnects402that extends from the display edge204A of the display area204to the driver area208. The driver chip202is flip-chip disposed onto the driver area208, allowing the plurality of interconnects402to reach and form electrical contacts with the first row of electronic pads404of the driver chip202. The plurality of interconnects402contact the first row of electronic pads404from at least two edges of the driver chip202, e.g., enter the driver area208from the first edge202A and one or more second edges202B of the driver chip202to come into contact with the first row of electronic pads404. In an example, the one or more second edges202B includes one or two side edges connected to the first edge202A of the driver chip202. The plurality of interconnects402are allowed to route across both the first edge202A and the one or more second edges202B to access the first row of electronic pads404. The fan-out area210is not limited to an area between the display area204and the driver chip202, and is expanded to include at least areas immediately adjacent to the one or more second edges202B of the driver chip202and partially surround the driver area208that supports the driver chip202. Stated another way, the driver chip202is partially surrounded by the fan-out area210.

The first row of electronic pads404have a first subset of end pads404A at a first end of the first row, a second subset of end pads404B at a second opposite end of the first row, and a first subset of intermediate pads404C located between the first subset of end pads404A and the second subset of end pads404B. The first subset of end pads404A physically contact a first subset of interconnects402A from the first edge202A of the driver chip202, and the first subset of intermediate pads404C physically contact a second subset of interconnects402B from the one or more second edges202B. At the display edge204A of the display area204, the plurality of interconnects402include m interconnects, where m is an integer number, and are arranged according to a predefined connection order. Starting from a right most interconnect402onFIG.4A, the plurality of interconnects402are numbered from 1 to m successively. At the first edge202A of the driver chip202, the electronic pads404include at least m pads to receive the plurality of interconnects402, and however, are arranged according to a distinct connection order. For example, the first subset of intermediate pads404C have a first number N of electronic pads, and the first subset of end pads404A have a second number L of electronic pads. Starting from a right most pad onFIG.4A, the first subset of end pads404A correspond to the (N+1)-th to (N+L)-th interconnects402successively, consistent with the predefined connection order of the interconnects402. The first subset of intermediate pads404C immediately follow the first subset of end pads404A and correspond to the N-th to first interconnects402successively in a reverse order, which is opposite to the predefined connection order of the interconnects402. By these means, at least the second subset of interconnects402B associated with the first subset of intermediate pads404C do not need to access the electronic pads via the first edge202A of the driver chip202, thereby facilitating reduction of the fan-out area height D2.

In some implementations, the first row of electronic pads404further include a second subset of intermediate pads404D. The first subset of intermediate pads404C are located between the second subset of intermediate pads404D and the first subset of end pads404A, and the second subset of intermediate pads404D physically contact a third subset of interconnects402C from the first edge202A. Further, in some implementations not shown inFIG.4A, each of the third subset of interconnects402C is shorter than that of the first subset of interconnects402A, and at least partially has a respective serpentine shape with a respective length that matches that of the first subset of interconnects402A.

Referring toFIG.4A, the second subset of end pads404B physically contact a corresponding subset of interconnects402D from the first edge202A. In some implementations, the first subset of end pads404A include more than one pad that are located at the first end of the first row, and the second subset of end pads404B include more than one pad that are located at the second opposite end of the first row.

In some implementations, the second subset of interconnects402B includes a first number N of interconnects corresponding to the first subset of intermediate pads404C. The first number N is determined based on a length of the two side edges202B connecting to the first edge. The plurality of interconnects402further include a remaining number P of interconnects402that physically access the first row of electronic pads404from the first edge202A of the driver chip202. A height of the fan-out area (i.e., the fan-out area height D2) is configured to accommodate the remaining number P of interconnects402that are routed from the display area204to the first row of electronic pads404via the first edge202A of the driver chip202. In some situations, the remaining number P of interconnects402are formed between the first subset of interconnects402A and another subset of interconnects402D contacting the second subset of end pads404B.

In some implementations, the plurality of interconnects402are formed on a single layer of conductive material (e.g., the routing layer180inFIG.1B), cannot cross each other, and are spatially ordered on a display substrate of the display screen125(e.g., in a glass substrate). Given the single layer of conductive material, only outmost interconnects402(e.g.,402B) can be routed across, and contact the first row of electronic pads404from, the one or more second edges202B of the driver chip202. In this application, the outmost interconnects402are not electrically coupled to the leftmost and rightmost pads404A and404B in the first row of electronic pads404. The outmost interconnects402optionally includes a single interconnect or more than one interconnect crossing either one of a left side and a right side of the driver chip202.

In some implementations, an overall routing pattern of the plurality of interconnects402is symmetric with respect to a central axis240of the display screen125. The second subset of interconnects402B access the intermediate pads404C from the right edge of the driver chip202, and a corresponding subset of interconnects402E access another subset of intermediate pads404E from the left edge of the driver chip202. The driver chip202is preferably symmetric with respect to the central axis240of the display screen125. Alternatively, in some implementations, the overall routing pattern of the plurality of interconnects402is asymmetric with respect to the central axis240of the display screen125. The driver chip202is shifted with respect to the central axis240of the display screen125to reduce the fan-out area height D2. For example, a subset of leftmost interconnects402E is connected to the second subset of end pads404B rather than a subset of intermediate pads404E, and the entire driver chip202is shifted towards the left of the central axis240of the display screen125.

It is noted that the interconnects402routed via the first edge202A are shorter interconnects402routed via the one or more second edges202B and that the interconnects402routed via the first edge202A have different lengths based on their positions relative to the driver chip202. In some implementations, each of the first subset of interconnects402A at least partially has a respective serpentine shape with a respective length that matches that of the second subset of interconnects402B. In some implementations, each of the third subset of interconnects402C at least partially has a respective serpentine shape and has a respective length that matches that of the first subset of interconnects402A. Additionally, in some implementations, the driver chip202includes an interconnect compensation component configured to generate electrical signals that compensate for parasitic s (e.g., parasitic resistance) of one or more interconnects of the plurality of interconnects402actively.

FIG.4Bis another example bezel region450of a display screen125in which interconnects402extending from a display area204contact two rows of pads of a driver chip202from two or more edges of the driver chip202, in accordance with some implementations. Compared with the driver chip202inFIG.4A, the driver chip202inFIG.4Bfurther includes a second row of electronic pads408proximate to the first edge202A and the first row of electronic pads404. The second row of electronic pads408include a third subset of end pads408A at a third end of the second row, a fourth subset of end pads408B at a fourth end of the second row, and a second subset of intermediate pads408C located between the third subset of end pads408A and the fourth subset of end pads408B. The third subset of end pads408A physically contacts a third subset of interconnects402C′ from the first edge202A of the driver chip202. The second subset of intermediate pads408C physically contact a fourth subset of interconnects402D′ from the one or more second edges202B of the driver chip202. The first subset of interconnects402A and third subset of interconnects402C′ interleave with each other, and the second subset of interconnects402B and fourth subset of interconnects402D′ interleave with each other.

Additionally, in some implementations not shown inFIG.4B, the driver chip202further including one or more third rows of electronic pads proximate to the first edge202A and the second row of electronic pads408. Each of the one or more third rows of electronic pads include a fifth subset of end pads at a fifth end of the respective third row, a sixth subset of end pads at a sixth opposite end of the respective third row, and a third subset of intermediate pads located between the fifth subset of end pads and the sixth subset of end pads. The fifth subset of end pads physically contacts a fifth subset of interconnects from the first edge. The first subset of interconnects402A, third subset of interconnects402C′, and fifth subset of interconnects interleave with each other. The third subset of intermediate pads physically contact a sixth subset of interconnects from the one or more second edges202B of the driver chip. The second subset of interconnects402B, fourth subset of interconnects402D′, and the sixth subset of interconnects interleave with each other, and get access to their respective electronic pads from the one or more second edges202B.

FIG.5Ais an example bezel region500of a display screen125in which interconnects402contact one or more rows of electronic pads of a driver chip202from two or more edges using an alternating scheme, in accordance with some implementations, andFIGS.5B-5Eare exploded views of interleaving pad subsets520,530,540, and550in accordance with some implementations. The bezel region500is immediately adjacent to a display area204, and includes a fan-out area210and a driver area208that is covered by the driver chip202. The driver chip202is disposed on the driver area208such that the first edge202A of the driver chip202is adjacent to the display area204. The driver chip202further includes at least a first row of electronic pads404proximate to the first edge202A. The first row of electronic pads404have a first subset of end pads404A at a first end of the first row, a second subset of end pads404B at a second opposite end of the first row, and a first subset of intermediate pads404C located between the first subset of end pads404A and the second subset of end pads404B.

In some implementations, the first row of electronic pads404further include a plurality of adjacent subsets of intermediate pads504that are located between the first subset of end pads404A and the second subset of end pads404B and spatially ordered in the first row. The plurality of adjacent subsets of intermediate pads504alternatingly contact respective subsets of interconnects502routed from a respective second edge202B and from the first edge202A, i.e., the subsets of interconnects502crossing the respective second edge202B and the subsets of interconnects502crossing the first edge202A alternatingly come into contact with the plurality of adjacent subsets of intermediate pads504. For example, referring toFIGS.5B and5C, four subsets of intermediate pads504A,504B,504C, or504D are successively arranged from right to left. According to this alternating scheme, the first subset of interconnects502A pass the first edge202A to contact and electrically couple to a corresponding subset of intermediate pads504A, the second subset of interconnects502B pass the second edge202B to contact and electrically couple to a corresponding subset of intermediate pads504B, the third subset of interconnects502C pass the first edge202A to contact and electrically couple to a corresponding subset of intermediate pads504C, the fourth subset of interconnects502D pass the second edge202B to contact and electrically couple to a corresponding subset of intermediate pads504D, and so on. In this example ofFIG.5B, each adjacent subset504A-504D of intermediate pads includes a single intermediate pad. In another example ofFIG.5C, each adjacent subset504A-504D of intermediate pads includes two or more intermediate pads, i.e., every two or more immediately adjacent intermediate pads504contact interconnects502from the same first or second edge202A or202B of the driver chip202.

Additionally, in some implementations, the alternating scheme is applied to two or more rows of electronic pads (e.g., rows404and408). For each row of electronic pads, two end pads at two opposite ends of the respective row contact their corresponding interconnects402routed via the first edge202A of the driver chip202, and the intermediate pads between the two end pads can be grouped into pad subsets (e.g.,504A-504D) that alternatingly contact the corresponding interconnect subsets502A-502D routed via the first edge202A and second edges202B of the driver chip202. Additionally, each pad subset of one of the two or more rows is associated and grouped with a respective counterpart subset of the other row(s), such that the pad subsets504A-504D alternate between the corresponding interconnect subsets502A-502D routed via the first edge202A and second edges202B concurrently for all of the two or more rows. Any interconnect402accessing a first row of electronic pads404from the second edge202B passes through an open space between two neighboring pads of a second row of electronic pads408. Any interconnect402accessing the second row of electronic pads408from the first edge202A passes through an open space between two neighboring pads of the row of electronic pads404.

In the example shown inFIG.5D, each pad subset (e.g.,504A) includes a pad from the first row404and an adjacent pad from the second row408, and is followed by a respective adjacent pad subset (e.g.,504B) includes a neighboring pad from the first row404and a neighboring pad of the adjacent pad from the second row408. The respective pad subset (e.g.,504A) is connected to a correspond interconnect subset (e.g.,502A) routed from one of the first and second edges of the driver chip202, and the respective adjacent pad subset (e.g.,504B) is connected to another correspond interconnect subset routed from the other one (e.g.,502B) of the first and second edges of the driver chip202. Alternatively, in an example shown inFIG.5E, each pad subset (e.g.,504A) includes two or more neighboring pads from the first row404and two or more adjacent neighboring pads from the second row. Each corresponding interconnect subset (e.g.,502A) includes a plurality of interconnects to access the two or more neighboring pads in the two rows404and408alternatingly, from the same first or second edge of the driver chip202.

The plurality of interconnects402include m interconnects, where m is an integer number, and are arranged according to a predefined connection order at the display edge204A of the display area204. Starting from a right most interconnect402, the plurality of interconnects402are numbered from 1 to m successively. Referring toFIG.5A, each row of electronic pads404or408include at least m/2 pads to be consistent with the plurality of interconnects402, and are arranged according to a mixed connection order different from the predefined connection order. Specifically, in each row of electronic pads404or408, a first type of pads corresponding to the interconnects that access the electronic pads404and408from the first edge202A follow the predefined connection order, and a second type of pads corresponding to the interconnects that access the electronic pads404and408from the one or more second edges202B have a reversed connection order and are inserted into the first type of pads. The first type of pads have a plurality of pad subsets506-1that follows the predefined connection order, and the second type of pads having a plurality of pad subsets506-2that reverses the predefined connection order. In some implementations, the alternating scheme (e.g.,FIGS.5B-5E) includes a plurality of in-sequence pad subsets506-1and a plurality of reversely-ordered pad subsets506-2, and the in-sequence pad subsets506-1are interleaved with the reversely-ordered pad subsets506-2.

FIG.6is an example bezel region600of a display screen125in which interconnects402contact electronic pads of a driver chip202from at least a bottom edge of the driver chip202, in accordance with some implementations. The bezel region600is immediately adjacent to a display area204, and includes a fan-out area210and a driver area208that is covered by the driver chip202. The driver chip202is disposed on the driver area208such that the first edge202A of the driver chip202is adjacent to the display area204. The driver chip202further includes at least a first row of electronic pads404proximate to the first edge202A. The first row of electronic pads404have a first subset of end pads404A at a first end of the first row, a second subset of end pads404B at a second opposite end of the first row, and a first subset of intermediate pads404C located between the first subset of end pads404A and the second subset of end pads404B. The first subset of end pads404A physically contact a first subset of interconnects402A from the first edge202A of the driver chip202, and the first subset of intermediate pads404C physically contact a second subset of interconnects402B from the one or more second edges202B of the driver chip202.

In some implementations, the one or more second edges202B are distinct from the first edge202A and include a third edge202C (also called a bottom edge) of the driver chip202. The third edge202C of the driver chip202opposes and is parallel to the first edge202A of the driver chip202. The third edge202C of the driver chip includes a first portion602and a second portion604. The second subset of interconnects402B access the first subset of intermediate pads404C from the first portion602. A plurality of input electronic pads606are formed on the driver chip202and adjacent to the bottom edge of the driver chip202, thereby allowing the plurality of input electronic pads606to be located adjacent to a fan-in area212of the display screen125.

It should be noted that details of a display fan-out scheme described with respect to each ofFIGS.4A-4B,5A-5D, and6are also applicable to any other display fan-out schemes described with respect to other figures ofFIGS.4A-4B,5A-5D, and6in an analogous manner. Each of the display fan-out schemes inFIGS.4A-4B,5A-5D, and6can be applied to route a subset of interconnects extending from the display area204to each of a subset or all of the plurality of driver chips202inFIG.2B. Particularly, each of the plurality of driver chips202has a first edge202A placed adjacent to the display area204, one or more second edges202B distinct from the first edge202A, and a first row of electronic pads404proximate to the first edge202A. The first row of electronic pads404has a first subset of end pads404A at a first end of the first row, a second subset of end pads404B at a second opposite end of the first row, and a first subset of intermediate pads404C located between the first subset of end pads404A and the second subset of end pads404B. The first subset of end pads404A physically contact a first subset of interconnects402A from the first edge202A, and the first subset of intermediate pads404C physically contact a second subset of interconnects402B from the one or more second edges202B. By these means, the height of the fan-out area210is reduced not only by using multiple driver chips202, but also by routing a subset of the interconnects from the one or more second edges202B of the respective driver chip202.

FIGS.7A and7Bare two example bezel regions700and750of a display screen125in which interconnects702extending from a display area204contact a plurality of pad groups704of a driver chip202having different distances from the display area204, in accordance with some implementations. Each of the bezel regions700and750is immediately adjacent to a display area204, and includes a fan-out area210and a driver area208that is covered by the driver chip202. The driver chip202is disposed on the driver area208such that the first edge202A of the driver chip202is adjacent to the display area204, The first edge202A faces a display edge204A of the display area204and is closer to the display area204than any other edges of the driver chip202(e.g., a first side edge202B-1, a second side edge202B-2, and a third edge202C). In some implementations, the first edge202A of the driver chip202is substantially parallel to the display edge204A of the display area204. The plurality of interconnects702of the display screen125extend from the display edge204A of the display area204to the driver area208. The driver chip202is flip-chip disposed onto the driver area208of a display substrate, thereby facilitating the plurality of interconnects702to reach and form electrical contacts with the pad groups704of the driver chip202. As explained above, the display screen125can be used in a laptop display, a tablet computer display, or a mobile phone display, and the driver chip202includes at least a plurality of source drivers222configured to drive a plurality of display elements. In some implementations, the driver chip202includes a timing controller220configured to control driving of the plurality of display elements of the display screen125in a synchronous manner by way of the interconnects702and pad groups704. It is noted that in some implementations, all of the plurality of interconnects702are formed on a single layer of conductive material, cannot cross each other, and are spatially ordered on the display substrate.

Each of the plurality of pad groups704(e.g.,704A,704B,704C,704D, and704E) includes at least one respective row of electronic pads that is arranged substantially in parallel with the first edge202A of the driver chip202and electrically coupled to a respective subset of display elements (not shown) via a respective subset of interconnects702routed on a respective region of the fan-out area210. The plurality of pad groups704includes at least a first pad group704A and a second pad group704B, and the first and second pad groups have two different distances d1and d2from the first edge202A and correspond to two different subsets of interconnects702A and702B routed on two non-overlapping regions of the fan-out area210. Further, in some implementations, the plurality of pad groups704includes a third pad group704C. The third pad group704C and second pad group704B are symmetric with respect to a central axis240of the driver chip202. The central axis240is perpendicular to the first edge202A and configured to divide the driver chip202into two equal halves. The second and third pad groups704B and704C have the same distance d1from the first edge202A. Further, in some implementations, the central axis240crosses the first pad group704A, and the first pad group704A is symmetric with respect to the central axis240of the driver chip202.

In some implementations, for each pad group704, the electronic pads have a predefined pad size and are arranged in the respective row according to a pad pitch. A respective lateral shift S is optionally measured from a side edge202B to an electronic pad that is closest to the side edge202B among the electronic pads in the respective pad group704. The first and second pad groups704A and704B have two distinct lateral shifts S1and S2from either one of the two side edges202B of the driver chip202connecting to the first edge202A. For example, the first pad group704A has a first lateral shift S1from the side edge202B and a first distance d1from the first edge202A, and the second pad group704B has a second lateral shift52from the side edge202B and a second distance d2from the first edge202A. The first lateral shift S1is greater than the second lateral shift S2, and the first distance d1is less the second distance d2. In another example not shown inFIG.7A, the first lateral shift S1is greater than the second lateral shift S2, and the first distance d1is also greater than the second distance d2. In some situations, projections of the first and second pad groups704A and704B to the first edge202A of the driver chip202do not overlap. Stated another way, all electronic pads of the second pad group704B are closer to a side edge202B-1than any of the electronic pads of the first pad group704A. That is, an electronic pad that is furthest from a side edge202B-1among the electronic pads in the second pad group704B is closer to the side edge202B-1than an electronic pad that is closest to the side edge202B-1among the electronic pads in the first pad group704A.

The respective row of electronic pads of the first pad group704A is coupled to a first subset of interconnects702A, and the respective row of electronic pads of the second pad group704B is coupled to a second subset of interconnects702B. In some implementations, each of the first subset of interconnects702A at least partially has a respective serpentine shape and has a respective length that matches that of the second subset of interconnects702B. Alternatively, in some implementations, the driver chip202includes an interconnect compensation component configured to generate electrical signals that compensate for parasitic s of one or more interconnects of the plurality of interconnects702actively.

In some implementations, the plurality of pad groups704include three or more pad groups704. The driver chip202has a central axis240that is perpendicular to the first edge202A and configured to divide the driver chip to two equal halves including a first half202-1. Each pad group704A,704B, or704D that is partially or entirely formed on the first half202-1of the driver chip202has a respective lateral shift S′ from the central axis240, and a respective distance D from the first edge202A. On the first half of each pad group (e.g.,704B), the respective distance (e.g., d2) from the first edge202A is distinct from that of any other pad group, and the respective lateral shift (e.g., S2′) from the central axis240is distinct from that of any other pad group.

In some implementations, for the plurality of pad groups704, the respective distance D from the first edge202A of each pad group704increases with the respective lateral shift S′ from the central axis240. Referring toFIG.2A, given the minimum feature size (MS) and minimal titling angle (TA) of interconnects702, a set702LM of leftmost interconnects and a set702RM of rightmost interconnects come into contact with a portion of the driver chip202that has a distance d3from the first edge202A. As such, the driver chip202is moved closer to the display edge204A of the display area204by a distance equal to d3−d1, and a width of the fanout area210is therefore reduced by the distance of d3−d1. In an example, this distance of d3−d1is equal to 0.8 millimeters, and the fanout area is reduced by approximately 10%.

In some implementations, a furthest pad group704D of the plurality of pad groups704is disposed adjacent to a second edge202B-1(also called a side edge) connecting to the first edge202A and a third edge202C opposing the first edge202A. One or more interconnects702LM of the subset of interconnects702D associated with the furthest pad group704D access the row of electronic pads of the furthest pad group704D from the second edge202B-1. In some implementations, the fan-out area210at least partially surrounds the driver area208where the driver chip202is disposed. Additionally, a plurality of input electronic pads706are formed on the driver chip202and adjacent to the third edge202C (also called a bottom edge) of the driver chip202, thereby allowing the plurality of input electronic pads706to be located adjacent to a fan-in area212of the display screen125. In some implementations not shown inFIG.7A, a subset of input electronic pads706are disposed between the furthest pad group704D and the third edge202C. Alternatively, in some implementations, there are no input electronic pads706disposed between the furthest pad group704D and the third edge202C. Stated another way, the driver chip202includes the third edge202C that opposes and is parallel to the first edge202A. The third edge202C includes a first portion202C-1and a second portion202C-2. The plurality of pad groups704include a pad group704D located immediately adjacent to the first portion202C-1of the third edge202C. The second portion202C-2includes a plurality of input electronic pads706and is adjacent to a fan-in area212of the display substrate. A flexible printed circuit (FPC)214is disposed on the fan-in area212to provide one or more input signals to the driver chip202.

In some implementations, the plurality of interconnects702are spatially arranged according to a first order, and the respective row of electronic pads of each pad group704is spatially arranged according a second order that is consistent with the first order. The first and second orders are observed along a direction parallel with the first edge202A. The driver chip202is flip-chip assembled to the display substrate, thereby facilitating the respective row of electronic pads of each pad group704to physically contact the subset of interconnects702corresponding to the respective pad group704.

In some implementations, each of the plurality of pad groups704includes a respective number of electronic pads, and every two pad groups704optionally have the same or distinct numbers of electronic pads, while each pad group704has a respective distance D from the first edge202A and a respective lateral shift S′ from the central axis240. For example, the plurality of pad groups704is divided from a single row of electronic pads (e.g., the pads404inFIG.4A, having a distance of d1from the first edge202A). Except the first pad group704A, each pad group704is moved in parallel with the central axis240to the respective distance from the first edge202A. The further away from the central axis240a pad group704, the larger the respective lateral shift is, thereby allowing the drive chip202to be closer to the display edge204A and allowing the fan-out area210to be reduced.

Referring toFIG.7B, in some implementations, each pad group704includes two rows of electronic pads, including a respective first row of electronic pads and a respective second row of electronic pads arranged immediately adjacent to the respective first row. For each pad group, the respective second row of electronic pads is arranged substantially in parallel with the first edge202A of the driver chip202and electrically coupled to another respective subset of display elements (not shown) via another respective subset of interconnects702routed on the same respective region of the fan-out area210. The fan-out area210supports the respective subset of interconnects702connecting to the respective first row of electronic pads. For each pad group704, the interconnects coupled to the first and second rows of electronic pads are interleaved with each other in the same respective region of the fan-out area210. In some implementations, the first and second rows of a pad group704have the same number of electronic pads and are aligned to each other. One or more of the interconnects connecting to the second row are routed around electronic pads of the first row. Alternatively, in some implementations, for each pad group704, the respective second row of electronic pads is shifted with respect to the respective first row of electronic pads by a portion of a pad pitch of the respective first rows of electronic pads along a first direction that is parallel with the first edge202A, allowing the interconnects connecting to the second row to pass between the electronic pads of the first row directly without routing around the electronic pads of the first row. In some implementations, for each pad group704, the respective first and second rows of electronic pads have the same pad size, the same pad pitch, and the same number of electronic pads, independently of whether the two rows of electronic pads are aligned or not.

From a different perspective, for each pad group704, the respective first row of electronic pads and the respective second row of electronic pads have two lateral shifts S′ from the central axis240. The two lateral shifts S′ are substantially identical (e.g., less than a predetermined shift tolerance, which is equal to three times of a pad pitch). The respective first row of electronic pads and the respective second row of electronic pads also have two different distances D from the first edge204A. The difference of the two distances D is flexible based on whether the first and second rows of the respective pad group704are disposed close to or far away from each other.

In some implementations not shown inFIGS.7A and7B, each pad group704includes three or more rows of electronic pads. The respective pad group704includes one or more respective third rows of electronic pads. Each respective third row of electronic pads is arranged substantially in parallel with the first edge202A, adjacent to the respective second row of electronic pads, and electrically coupled to a respective third subset of display elements via a respective third subset of interconnects routed on the corresponding region of the fan-out area210. This also supports the respective subsets of interconnects702connecting to the respective first and second rows of electronic pads. The interconnects coupled to the first, second, and third rows of electronic pads are interleaved with each other on the same region of the fan-out area210. Within each pad group704, the three or more rows of electronic pads are optionally aligned or shifted with respect to each other. In some implementations, for each pad group704, the respective three or more rows of electronic pads have the same pad size, the same pad pitch, and the same number of electronic pads.

It should be noted that details of each of the display fan-out schemes inFIGS.7A and7Bcan be applied to route a subset of interconnects extending from the display area204to each of a subset or all of the plurality of driver chips202inFIG.2B. Particularly, each of the plurality of driver chips202has a first edge202A placed adjacent to the display area204, second edges202B (e.g., side edges) connecting to the first edge202A, a third edge202C opposing the first edge202A, and a plurality of pad groups704each having one or more rows of closely spaced electronic pads. For each driver chip202, each pad group has a distinct distance from the first edge202A from any other pad group on the same half of the driver chip202. For example, the plurality of pad groups704includes a first pad group704A and a second pad group704B, and the first and second pad groups704A and704B have two different distances d1and d2from the first edge202A and correspond to two different subsets of interconnects702A and702B routed on two non-overlapping regions of the fan-out area210of each driver chip202. In an example, the first pad group704A is proximate to the first edge202A, while the second pad group704B is proximate to the third edge202C opposing to the first edge202A. By these means, the height of the fan-out area210is reduced not only by using multiple driver chips202, but also by routing a subset of the interconnects to a plurality of pad groups704having different distances from the first edge202A of each driver chip202.

Referring toFIG.2B, in some implementations, two identical driver chips, a first driver chip202-1and a second driver chip202-2, are disposed in the driver area208. The first edges202A (seeFIG.2A) of the first and second driver chips202-1and202-2are aligned and arranged in parallel with the display edge204A of the display area204. Further, in some implementations, one or more third driver chips202-3that are identical to the first driver chip202-1are disposed in the driver area, and the first edges202A of the first, second and third driver chips202-1,202-2, and202-3are aligned and arranged in parallel with the display edge204A of the display area204. In some implementations, the first, second, and third driver chips are equally spaced (e.g., every two adjacent driver chips are separated by a predefined separation). In some implementations, each of the first, second, and third driver chips202adopts a first pad arrangement scheme shown inFIGS.4A-4B,5A, and6or a second pad arrangement scheme shown inFIGS.7A-7B, independently of the other driver chips202. In some implementations, all of the first, second, and third driver chips202adopts the same pad arrangement scheme selected from those described with reference toFIGS.4A-4B,5A,6, and7A-7B.

FIG.8is an example bezel region800of a display screen125in which a first subset of interconnects802A extend above a gap804between adjacent pad groups806of a driver chip202, in accordance with some implementations. The bezel region800is immediately adjacent to a display area204, and includes a fan-out area210and a driver area208that is covered by, and hidden under, the driver chip202. The driver chip202is disposed on the driver area208, such that the first edge202A of the driver chip202is adjacent to the display area204, e.g., separated from the display area204by part of the fan-out area210. The first edge202A faces a display edge204A of the display area204and is closer to the display area204than any other edge of the driver chip202(e.g., two side edges202B-1and202B-2connected to the first edge202A, a third edge202C that opposes and is parallel to the first edge202A). In some implementations, the first edge202A is parallel to the display edge204A of the display area204, and the two side edges202B are perpendicular to the first edge202A.

The driver chip202further includes a plurality of pad groups806(e.g., including pad groups806A-806C and806A′-806C′). Each pad group806includes a respective row of electronic pads that are electrically coupled to a respective subset of display elements via a respective subset of interconnects802(e.g., including interconnects802A-802C,802A′, and802B′) routed on the fan-out area210of a display substrate of the display screen125. In some implementations, respective rows of electronic pads of the plurality of pad groups806are parallel to each other. In some implementations, for each pad group806, the respective row of electronic pads is arranged substantially in parallel with the first edge202A and has a respective distinct distance from the first edge202A.

The plurality of pad groups806include a first pad group806A and a second pad group806B. The second pad group806B is disposed immediately adjacent to the first pad group806A, and there is no additional pad group806disposed between the first and second pad groups806A and806B. The first subset of interconnects802A cross one of the two side edges202B-1, and extend above a gap804formed between respective rows of electronic pads of the first and second pad groups806A and806B to reach the first pad group806A. Referring to the cross-sectional view A-A′ inFIG.8, the driver chip202is flip-chip disposed onto the driver area208of the display substrate of the display screen125. The first subset of interconnects802A are formed on the display area204of the display substrate and float above the gap804formed between the respective rows of electronic pads of the first and second pad groups806A and806B.

In some implementations, the first pad group806A is closer to the first edge202A of the driver chip202and the display area204than the second pad group806B. Further, in some implementations, the third edge202C of the driver chip202opposing the first edge202A are connected to the two side edges202B. A second subset of interconnects802B that are electrically coupled to the second pad group806B cross the third edge202C of the driver chip202and does not extend above the gap804between the respective rows of electronic pads of the first and second pad groups806A and806B. Additionally, in some implementations, the plurality of pad groups806include an input/output pad group806-IO located immediately adjacent to the third edge202C. The second pad group806B and the input/output pad group806-IO are aligned with a virtual pad line808that is parallel with the first and third edges202A and202C. The input/output pad group806-IO are configured to provide one or more of a plurality of power supplies, input signals, and output signals. In some implementations, a subset of the input/output pad group806-IO is coupled to a gate on array (GOA) driver. The GOA driver is configured to generate a plurality of high voltage output signals to drive a GOA circuit on a display screen125. The GOA driver is optionally a standalone chip or integrated in the driver chip202. For example, referring toFIG.8, the driver chip202includes the GOA driver.

In some implementations, each of the first pad group806A and the second pad group806B includes a predefined number of pads, and the first and second pad groups806A and806B are aligned at two ends of the respective rows of electronic pads of the first and second pad groups806A and806B. Alternatively, in some implementations, the gap804of the respective rows of electronic pads of the first and second pad groups806A and806B is formed between a subset of the first pad group806A and a subset of the second pad group806B, and each of the subsets of the first and second pad groups806A and806B includes at least two electronic pads. Alternatively, in some embodiments, the first pad group806A and the second pad group806B include different number of pads and are parallel with each other. At least two electronic pads of the first pad group806A face, and form the gap804with, at least two electronic pads of the second pad group806B.

In some implementations, the plurality of pad groups806further includes a third pad group806C adjacent to the first pad group806A, and no interconnect is routed to extend above a second gap810between the respective rows of electronic pads of the first and third pad groups806A and806C. In some implementations, referring toFIG.8, the third pad group806C are electrically coupled to a third subset of interconnects802C, which are routed between the display edge204A and first edge202A and cross the first edge202A of the display chip202to access the third pad group806C.

Referring toFIG.8, in some implementations, each of the display area204, fan-out area210, and driver area208is symmetric with respect to a central axis240of the display screen125, so is the display chip202disposed symmetrically with respect to the central axis240. The plurality pad groups806of the display chip202and the plurality of interconnects802of the fan-out area210are also arranged symmetrically with respect to the central axis240. For example, each of the respective rows of electronic pads of the first, second, and third pad groups806A,806B, and806C corresponds to a respective row of electronic pads of pad group806A′,806B′, and806C′. Each of the subsets of interconnects802A and802B corresponds to a respective subset of interconnects802A′ or802B′. The subset of interconnects802C passes the entire length of the first edge202A of the display chip202in a symmetric manner with respect to the central axis240to access the pad groups806C and806C′.

In some implementations, the driver chip202includes integrated circuit configured to drive the plurality of display elements formed on the display area204. The integrated circuit includes a plurality of source drivers configured to drive the plurality of display elements. For each pad group806, the respective row of electronic pads are electrically coupled to a respective subset of source drivers, allowing the respective subset of source drivers to be electrically coupled to the respective subset of display elements via the respective subset of interconnects802routed on the fan-out area210. Particularly, referring toFIG.8, the second pad group806B and the third pad group806C are located immediately adjacent to the third edge202C and the first edge202A of the driver chip202, respectively. The second subset of interconnects802B and the third subset of interconnects802C cross the third edge202C and the first edge202A to access the second pad group806B and the third pad group806C, which are coupled to different source drivers, respectively. As such, the second pad group806B and third pad group806C are folded output pads of the different source drivers configured to provide display signals to drive the plurality of display elements on the display area204of the display screen125. Stated another way, the second pad group806B includes a set of input-side source driver folded output pads of the source drivers of the driver chip202, and the third pad group806C includes a set of output-side source driver folded output pads of the source drivers.

Some implementations of this application are directed to a driver chip202that is configured to be disposed on a display substrate including a display area204, a driver area208, and a fan-out area210. The driver area208is configured to receive the driver chip202, and the fan-out area210has a plurality of interconnects802and is configured to provide electrical accesses to a plurality of display elements of the display area204. The driver chip202further includes a first edge202A configured to be adjacent to the display area204, two side edges202B connected to the first edge202A, and a plurality of pad groups806. Each pad group806includes a respective row of electronic pads that are electrically coupled to a respective subset of display elements via a respective subset of interconnects802routed at least partially on the fan-out area210. The plurality of pad groups806include a first pad group806A and a second pad group806B disposed immediately adjacent to the first pad group806A. A first subset of interconnects802A cross one of the two side edges202B-1, and extend above a gap804between respective rows of electronic pads of the first and second pad groups806A and806B to reach the first pad group806A.

FIG.9is another example bezel region900of a display screen125in which a first subset of interconnects802A access, and extend above a gap804between, adjacent pad groups806of a driver chip202, in accordance with some implementations. The driver chip202includes a plurality of pad groups806(e.g., including pad groups806A-806C and806A′-806C′). Each pad group806includes a respective row of electronic pads that are electrically coupled to a respective subset of display elements via a respective subset of interconnects802routed on the fan-out area210of a display substrate of the display screen125. The plurality of pad groups806include a first pad group806A and a second pad group806B. The second pad group806B is disposed immediately adjacent to the first pad group806A, and there is no additional pad group806disposed between the first and second pad groups806A and806B. The first subset of interconnects802A cross one of the two side edges202B-1, and extend above a gap804formed between respective rows of electronic pads of the first and second pad groups806A and806B to reach the first pad group806A.

Referring toFIG.9, in some embodiments, a second subset of interconnects802B that are electrically coupled to the second pad group806B cross the same one of the two side edges202B-1, and extend above the gap804between the respective rows of electronic pads of the first and second pad groups806A and806B. In an example, the second pad group806B is disposed immediately adjacent to and in parallel with the third edge202C of the driver chip202. The second subset of interconnects802B do not cross the third edge202C to access the second pad group806B. In another example not shown inFIG.9, the second pad group806B is separated from each of the first edge202A and third edge202C of the driver chip202by at least one pad group806.

FIGS.10A-10Care enlarged areas of three example bezel regions1000,1020, and1040of display screens125each having interconnects coupled to electronic pads of a driver chip202, in accordance with some implementations. The driver chip202includes a plurality of pad groups806. Each pad group806includes a respective row of electronic pads that are electrically coupled to a respective subset of interconnects802routed on a fan-out area210of a display substrate of a display screen125. The plurality of pad groups806include a first pad group806A and a second pad group806B disposed immediately adjacent to the first pad group806A. The first subset of interconnects802A cross one of the two side edges202B-1, and extend above the gap804formed between respective rows of electronic pads of the first and second pad groups806A and806B to reach the first pad group806A.

Referring toFIG.10A, in some implementations, the second pad group806B is closer to the first edge202A of the driver chip202and the display area204than the first pad group806A. A second subset of interconnects802B that are electrically coupled to the second pad group806B cross the first edge202A of the driver chip202and does not extend above the gap804between the respective row of electronic pads of the first and second pad groups806A and806B.

In some implementations, each of the first and second pad groups806A and806B is separated from a respective edge202A or202C by one or more pad group806. The second pad group806B is optionally closer to or further away from the first edge202A of the driver chip202and the display area204than the first pad group806A. The second subset of interconnects802B are electrically coupled to the second pad group806B. Further, referring toFIG.10B, in some implementations, both the first subset of interconnects802A and the second subset of interconnects802B cross the same one of the second edges202B-1of the driver chip202and extend above the gap804between the respective row of electronic pads of the first and second pad groups806A and806B. Alternatively, referring toFIG.10C, in some implementations, the second subset of interconnects802B that are electrically coupled to the second pad group806B cross the one of the two side edges202B-1, and extend above a second gap1002between the respective rows of electronic pads of the second pad group806B and a third pad group (not shown). In some implementations, the third pad group is immediately adjacent to the second pad group806B.

As explained above, the driver chip202includes at least two pad groups806A and806B that intersect a vertical axis1004perpendicular to the first and third edges202A and202C and form the gap804to route at least the first subset of interconnects802A. In some embodiments, the driver chip202includes more than two pad groups806(e.g.,8pad groups) that intersect the vertical axis1004perpendicular to the first and third edges202A and202C. Except for a top pad group that can be accessed via the first edge202A, remaining pad groups in the more than two pad groups806can be accessed from the two side edges202B-1and202B-2, thereby reducing a number of interconnects routed in the part of the fan-out area210that located between the display edge204A and first edge202A. By these means, an open space of the fan-out area210that is next to the two side edges202B of the driver chip202is utilized to reduce a height of the fan-out area210(i.e., D1inFIGS.8and9).

FIGS.11A-11Care enlarged areas of another three example bezel regions1100,1120, and1140of display screens125each having interconnects802coupled to electronic pads806of a driver chip202, in accordance with some implementations. Each pad group806includes two or more rows of electronic pads, and the two or more rows are parallel to each other and staggered. Particularly, in some implementations, the plurality of interconnects802are formed on a single layer of conductive material and cannot cross each other. For each pad group, a respective subset of interconnects802accesses the two or more rows of electronic pads in an interleaving manner. In some embodiments, each of the first, second, and third pad groups806A-806C includes a respective first row of electronic pads (e.g.,806A-1) and a respective second row of electronic pads (e.g.,806A-2).

For example, for the first pad group806A, the second row of electronic pads806A-2are arranged substantially in parallel with the first edge202A and immediately adjacent to the first row of electronic pads806A-1. In some implementations, the first and second rows of electronic pads806A-1and806A-2have the same pad size, the same pad pitch, and the same number of electronic pads. The second row of electronic pads806A-2are shifted with respect to the first row of electronic pads806A-1by a portion of a pad pitch of the first rows of electronic pads806A-1along a first direction that is parallel with the first edge202A. The first subset of interconnects802include both interconnects coupled to the first row of electronic pads806A-1and interconnects coupled to the second row of electronic pads806A-2. The interconnects coupled to the first row of electronic pads806A-1are interleaved with the interconnects coupled to the second row of electronic pads806A-2, which access the second row of electronic pads806A-2via spaces separating immediately adjacent electronic pads in the first row806A-1.

Further, in some implementations not shown, for each pad group806, the respective pad group806includes one or more respective third rows of electronic pads. Each respective third row of electronic pads are arranged substantially in parallel with the first edge202A and immediately adjacent to the respective second row of electronic pads (e.g.,806A-2). For example, in the first pad group806A, interconnects coupled to the third row of electronic pads806A-3interleave with both the interconnects coupled to the first row of electronic pads806A-1and the interconnects coupled to the second row of electronic pads806A-2, and access the third row of electronic pads806A-3via the spaces separating immediately adjacent electronic pads in the first row806A-1and via the spaces separating immediately adjacent electronic pads in the second row806A-2.

Referring toFIG.11A, in some implementations, the interconnects802A to both the first and second rows of electronic pads806A-1and806A-2of the first pad group806A cross one of the two side edges202B-1and extend above a gap804between the first and second pad groups806A and806B. A third pad group806C is adjacent to the first pad group808A. In this example, the second pad group806B is immediately adjacent to the third edge202C, and the second subset of interconnects802B cross the third edge202C to access the second pad group806B. The third pad group806C is immediately adjacent to the first edge202A, and the third subset of interconnects802C cross the first edge202A to access the third pad group806C.

Referring toFIG.11B, in addition to the interconnects802A to the electronic pads of the first pad group806A, the interconnects802B to both the first and second rows of electronic pads806B-1and806B-2of the second pad group806B also cross one of the two side edges202B-1and extend above the gap804between the first and second pad groups806A and806B. Further, the second pad group806B is immediately adjacent to the third edge202C of the driver chip202or separated from the third edge202C by one or more pad groups806.

Referring toFIG.11C, in some implementations, the interconnects802A to both the first and second rows of electronic pads806A-1and806A-2of the first pad group806A cross one of the two side edges202B-1and extend above a gap804between the first and second pad groups806A and806B, so do the interconnects802B to both the first and second rows of electronic pads806B-1and806B-2of the second pad group806B. The plurality of pad groups806further include a third pad group806C and a fourth pad group806D that are immediately adjacent to the first and third edges202A and202C, respectively. The subsets of interconnects802C and802D cross the first and third edges202A and202C to access the respective rows of electronic pads of the third and fourth pad groups806C and806D, respectively.

It is noted that in some implementations, all interconnects802(e.g., including the interconnects802A and802B) cross the first edge202A to access the plurality of electronic pads806of the driver chip202inFIG.3with the fan-out area height D2. The fan-out area height D2is expanded to accommodate all of the interconnects802. Referring toFIGS.11B and11C, the interconnects802A,802B,802A′, and802B′ are moved to access the pad groups806A and806B via the second side edges. The number of interconnects802that need to cross the first edge202A decreases, thereby requiring a smaller height D2of the fan-out area210between the display edge204A and the first edge202A. In an example, 10% of the interconnects802(e.g., approximately 100 interconnects) are moved to access the pad groups806from the two side edges202B, and reduce a width of a bezel region by 10%. By these means, a display screen125is developed to have no or litter display border area.

FIG.12is an example bezel region1200of a display screen125in which a first subset of interconnects802having different interconnect pitches over different regions of a fan-out area210, in accordance with some implementations. The bezel region1200is immediately adjacent to a display area204, and includes a fan-out area210and a driver area208that is covered by, and hidden under, the driver chip202. The display area204has a plurality of display elements (not shown). The fan-out area210has a plurality of interconnects1202that are configured to provide electrical accesses to the plurality of display elements of the display area204. The fan-out area210is further divided to a plurality of fan-out regions, e.g., a first fan-out region210A, a second fan-out region210B, and a third fan-out region210C. In some implementations (e.g., inFIG.14), the driver area208is immediately adjacent to the fan-out area210. Alternatively, in some implementations, the fan-out area210includes the driver area208, e.g., in the first fan-out region210A. The driver chip202is disposed on the driver area208, such that a first edge202A of the driver chip202is adjacent to the display area204, e.g., separated from the display area204by part of the fan-out area210. The first edge202A faces a display edge204A of the display area204and is closer to the display area204than any other edge of the driver chip202(e.g., two side edges202B-1and202B-2connected to the first edge202A, a third edge202C that opposes and is parallel to the first edge202A). In some implementations, the first edge202A is parallel to the display edge204A of the display area204, and the two side edges202B are perpendicular to the first edge202A.

The driver chip202includes a plurality of pads1204, and each pad1204is electrically coupled to a respective display element via a respective interconnect1202routed on the fan-out area210. The plurality of pads1204are optionally arranged in one or more rows on the driver chip202. The plurality of interconnects1202routed on the display substrate include a subset of first interconnects1202A. Each first interconnect1202A is configured to be electrically coupled to a respective first pad1204A of the driver chip202, and passes both a first fan-out region210A and a second fan-out region210B to access a respective first display element on the display area204. A first portion1202A-1of the subset of first interconnects1202A is formed on the first fan-out region210A with a first interconnect pitch P1. A second portion1202A-2of the subset of first interconnects1202A is formed on the second fan-out region210B with a second interconnect pitch P2. The second interconnect pitch P2is different from the first interconnect pitch P1. Specifically, in some embodiments, the second interconnect pitch P2is greater than the first interconnect pitch P1.

In some implementations, the subset of first interconnects1202A includes two interconnects1202A. In some implementations, the subset of first interconnects1202A includes three or more interconnects1202A. In some implementations, the subset of first interconnects1202A include all interconnects1202that cross the display edge204A in the second fan-out region210B. In some implementations, the subset of first interconnects1202A include a subset of (i.e., less than all) interconnects1202that cross the display edge204A in the second fan-out region210B. Two subsets of interconnects1202that cross the display edge204A in the second fan-out region210B optionally have equal or distinct interconnect pitches in the second fan-out region210B.

In some implementation, the fan-out area210further includes a third fan-out region210C connected to the second fan-out region210B. The second fan-out region210B is located between the first and third fan-out regions210A and210C. Each of the subset of first interconnects1202A also passes the third fan-out region210C to access the respective first display element. Further, in some implementations, a third portion1202A-3of the subset of first interconnects1202A is formed on the third fan-out region210C with a third interconnect pitch P3. The second interconnect pitch P2is greater than the first interconnect pitch P1and less than the third interconnect pitch P3. Stated another way, a pitch at a certain location of the subset of first interconnects1202A increases with a corresponding distance from the central axis240. In some embodiments, the first fan-out region210A includes the driver area208onto which the driver chip202is flip-chip disposed. Further, in some implementations, the subset of first interconnects1202A cross the first edge202A to access the subset of first pads1204A. Alternatively, in some implementations, the subset of first interconnects1202A cross the side edge202B-1to access the subset of first pads1204A. The first portion1202A-1of the subset of first interconnects1202A is partially or entirely concealed between the driver area208of the display substrate and the driver chip204, and the second portion1202A-2of the subset of first interconnects1202A lies on the display substrate without being concealed by the driver chip204.

In some implementations, the plurality of interconnects1202further include one or more second interconnects1202B passing the first fan-out region210A. Each second interconnect1202B electrically couples a respective second pad1204B on the driver chip202and a respective second display element on the display area204without extending to the second fan-out region210B. Further, in some implementations, the one or more second interconnect1202B have a substantially uniform pitch equal to the first interconnect pitch P1of the subset of first interconnects1202A in the first fan-out region210A. Additionally, in some implementations, the one or more second interconnects1202B further include a second interconnect1202B-1, and each portion of the second interconnect1202B-1is substantially parallel to a respective portion of each first interconnect1202A.

In some implementation, the fan-out area210includes a central axis240and is symmetric with respect to the central axis240. The central axis240is located in the first fan-out region210A and external to the second fan-out region210B. The first fan-out region210A is optionally symmetric with respect to the central axis240. Further, in some implementations, the fan-out area210further includes a fourth fan-out region210D. The second and fourth fan-out regions210B and210D are symmetric with respect to the central axis240. A first portion1202C-1of a subset of third interconnects1202C is formed on the first fan-out region210A with the first interconnect pitch P1, and a second portion1202C-2of the subset of third interconnects1202C is formed on the fourth fan-out region210D with the second interconnect pitch P2.

In some implementations, the first fan-out region210A has a region width WD1equal to a driver width of the driver chip, and the plurality of interconnects1202passes the first fan-out region210A to access the plurality of pads1204of the driver chip204. The first fan-out region210A includes the driver area208onto which the driver chip202is flip-chip disposed. Each of the interconnects1202A,1202B, and1202C has a respective portion that is routed on the first fan-out portion210A and contacts a respective pad1204A,1204B, or1204C of the driver chip204.

In some embodiments, the fan-out region210is laterally divided into the plurality of fan-out regions (e.g.,210A-210D), which are arranged along a direction perpendicular to the central axis240or parallel with the first edge204A. The second fan-out region210B is immediately adjacent to the first fan-out region210A. The second interconnect pitch P2of the subset of first interconnects1202A in the second fan-out region210B is determined based on a first interconnect length L1of the subset of first interconnects1202A. Specifically, in an example, the plurality of interconnects1202include a subset of second interconnects1202B, and each second interconnect1202B is electrically coupled to a respective second pad1204B and passes the first fan-out region210A, but not the second fan-out region210B, to access a respective second display element on the display area204. The subset of second interconnects1202B have an alternative interconnect pitch and an alternative interconnect length. The second interconnect pitch P2of the subset of first interconnects1202A in the second fan-out region210B is determined based on the first interconnect length L1of the subset of first interconnects1202A, the alternative interconnect pitch, and the alternative interconnect length. In an example, the alternative interconnect pitch is equal to the first interconnect pitch P1. Additionally, in some situations, the first interconnect length L1is the longest interconnect length of the subset of first interconnects1202A, and the alternative interconnect length is the longest interconnect length of the subset of second interconnects1202B. Alternatively, in some situations, the first interconnect length L1is an average or median interconnect length of the subset of first interconnects1202A, and the alternative interconnect length is an average or median interconnect length of the subset of second interconnects1202B.

In some implementations, this application is directed to an electronic device including both a display substrate and a driver chip204. Alternatively, in some implementations, this application is directed to a display substrate that is configured to receive the driver chip204. The display substrate further includes (1) a display area204having a plurality of display elements, (2) a fan-out area210divided to a plurality of fan-out regions and having a plurality of interconnects1202that are configured to provide electrical accesses to the plurality of display elements of the display area204, and (3) a driver area208adjacent to the fan-out area210and configured to receive the driver chip202including a plurality of pads1204. Each pad1204is configured to be electrically coupled to a respective display element via a respective interconnect1202routed on the fan-out area210. The plurality of interconnects1202include a subset of first interconnects1202A. Each first interconnect1202A is configured to be electrically coupled to a respective first pad1204A of the driver chip202, and passes a first fan-out region210A and a second fan-out region210B to access a respective first display element. A first portion1202A-1of the subset of first interconnects1202A is formed on the first fan-out region210A with a first interconnect pitch P1, and a second portion1202A-2of the subset of first interconnects1202A is formed on the second fan-out region210-B with a second interconnect pitch P2, The second interconnect pitch P2is different from (e.g., greater than) the first interconnect pitch P1.

FIGS.13A and13Bare enlarged areas of two example bezel regions1300and1350of display screens125having interconnects1202of variable width, in accordance with some implementations. A fan-out area210of a display substrate is divided into a plurality of fan-out regions including a first fan-out region210A, a second fan-out region210B, and a transition region210T connecting the first and second fan-out regions210A and210B. A subset of first interconnects1202A pass a first fan-out region210A and a second fan-out region210B. A first portion1202A-1of the subset of first interconnects1202A is formed on the first fan-out region210A with a first interconnect pitch P1, and a second portion1202A-2of the subset of first interconnects1202A is formed on the second fan-out region210-B with a second interconnect pitch P2. A pitch of the subset of first interconnects1202A increases from the first interconnect pitch P1to the second interconnect pitch P2within the transition region210T.

In some implementations, the first and second fan-out regions210A and210B have distinct heights H1and H2, respectively. The transition region210T has a height HTidentical to the height H2of the second fan-out region210B. The first fan-out region210A includes the driver area208on which the driver chip202is disposed. Alternatively, in some implementations not shown, the first and second fan-out regions210A and210B have the same height, and the transition region210T covers the same height.

In some implementations, for each first interconnect1202A, a width of the first interconnect1202A increases from a first interconnect width W1to a second interconnect width W2within the transition region210T. The second interconnect width W2is greater than the first interconnect width W1. In some implementations, each first interconnect1202A is routed in part with a respective angle to couple the first portion1202A-1to the second portion1202A-2in the transition region210T. A titling portion1202AT of the respective first interconnect1202A has a fixed interconnect width. The fixed interconnect width is equal to one of the first interconnect width W1, the second interconnect width W2, and an intermedia intermediate width that is greater than the first interconnect width W1and less than less the second interconnect width W2. Further, referring toFIG.13A, in some implementations, the tilting portion1202AT of a first interconnect1202A has the first interconnect width W1. In the transition region210T, the first interconnect1202A corresponds to a spatial rate in which an end of the tilting portion1202AT extends to an end of the second portion1202A-2. The first interconnect width W1of the tilting portion1202AT gradually increases to the second interconnect width of the second portion of the tilting portion1202AT according to the spatial rate in the transition region210T. Alternatively, referring toFIG.13B, in some implementations, independently of the fixed width of the tilting portion1202AT, two ends of the tilting portion1202AT of each first interconnect1202A are connected to the first portion1202A-1and second portion1202A-2of the respective first interconnect1202in the transition region210T, respectively.

The subset of first interconnects1202A correspond to an interconnect gap G between two immediately adjacent first interconnects1202A. In some embodiments not shown, the interconnect gap G of two of the subset of first interconnects1202A remains constant on the first and second fan-out regions210A and210B, independently of the pitch of the subset of first interconnects1202A. A width of each interconnect1202A increases from the first fan-out region210A to the second fan-out region210B. Alternatively, referring toFIGS.13A and13B, in some implementations, the interconnect gap G of two of the subset of first interconnects1202A increases with the pitch of the subset of first interconnects1202A, e.g., by keeping a constant ratio between the interconnect gap and the pitch. The first portion1202A-1of the subset of first interconnects1202A corresponds to a first interconnect gap on the first fan-out region210A, and the second portion1202A-2of the subset of first interconnects1202A corresponds to a second interconnect gap on the second fan-out region210B. The second interconnect gap is greater than the first interconnect gap. Alternatively, in some implementations not shown, while the width of the first interconnect1202A increases from the first interconnect width in the first fan-out region210A to the second interconnect width in the second fan-out region210B, the first interconnect gap of the first interconnects1202A in the first fan-out region210A is smaller than the second interconnect gap of the first interconnects1202A in the second fan-out region210B,

FIG.14is another example bezel region1400of a display screen125in which a subset of first interconnects1202A having different interconnect pitches over different regions of a fan-out area210, in accordance with some implementations. The bezel region1400is immediately adjacent to a display area204, and includes a fan-out area210and a driver area208that is covered by, and hidden under, the driver chip202. The display area204has a plurality of display elements (not shown). The fan-out area210has a plurality of interconnects1202that are configured to provide electrical accesses to the plurality of display elements of the display area204, and the fan-out area210is divided to a plurality of fan-out regions, e.g., a first fan-out region210A, a second fan-out region210B. In this example, the first fan-out region210A has a first height h1, and the second fan-out region210B has a second height h2. The driver area208is immediately adjacent to the first fan-out region210A of the fan-out area210. The driver chip202is disposed on the driver area208, such that a first edge202A of the driver chip202is adjacent to the display area204, e.g., separated from the display area204by the first fan-out area210A. The first edge202A faces, and is parallel to, a display edge204A of the display area204.

The driver chip202includes a plurality of pads1204that are arranged in a row immediately adjacent to the first edge202A. The plurality of interconnects1202cross the first edge202A to access the plurality of pads1204. The plurality of pads1204are configured to be electrically coupled to the plurality of display elements of the display area204via the plurality of interconnects1202. The plurality of pads1204include a subset of first pads1204A and a second subset of second pads1204B. The subset of first pads1204A are electrically coupled to a subset of first interconnects1202A. Each first interconnect1202A contacts a respective first pad1204A and passes the first fan-out region210A and second fan-out region210B successively to access a respective first display element. A first portion1202A-1of the subset of first interconnects1202A is formed on the first fan-out region210A with a first interconnect pitch P1, and a second portion1202A-2of the subset of first interconnects1202A is formed on the second fan-out region210B with a second interconnect pitch P2. The second interconnect pitch P2is different from (e.g., greater than) the first interconnect pitch P1. Conversely, the subset of second pads1204B are electrically coupled to a subset of second interconnects1202B. Each second interconnect1202B contacts a respective second pad1204B and passes the first fan-out region210A to access a respective second display element. The second interconnects1202B does not pass the second fan-out region210B. The subset of second interconnects1202B is formed on the first fan-out region210A with the first interconnect pitch P1.

The subset of first interconnects1202A are longer than the subset of second interconnects1202B because the first interconnects1202A have to extend to the second fan-out region210B to reach the display edge204A. Given greater lengths, the subset of first interconnects1202A tend to have more parasitic capacitance, resistance, and inductance if none of their pitch, gap, and width is adjusted to suppress at least part of parasitic effects. Parasitic capacitance, resistance, and inductance of the first interconnects1202A compromises electrical performance of these interconnects1202. In various implementations of this application, the pitch, gap, and/or width is controlled to counteract the loss of electrical performance caused by the length-induced parasitic effects.

It should be understood that the particular implementations inFIG.12-14have been described are merely exemplary and are not intended to indicate that the described implementations are the only implementations in which interconnects having variable widths can be routed. One of ordinary skill in the art would recognize various ways to route interconnects1202. Also, one of ordinary skill in the art would recognize various ways to place a plurality of pads1204on the driver chip202. Additionally, it should be noted that details of other electronic devices described above with respect toFIGS.1A-11Care also applicable in an analogous manner to the electronic devices described above with respect toFIGS.12-14. For brevity, these details are not repeated here.

The foregoing description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The implementations were chosen in order to best explain the principles underlying the claims and their practical applications, to thereby enable others skilled in the art to best use the implementations with various modifications as are suited to the particular uses contemplated.

Referring toFIGS.12-14, some implementations of this application are summarized as follows:

Clause 1. an electronic device, comprising: a display substrate further including a display area having a plurality of display elements; a fan-out area, the fan-out area having a plurality of interconnects that are configured to provide electrical accesses to the plurality of display elements of the display area, wherein the fan-out area is divided to a plurality of fan-out regions; and a driver area adjacent to the fan-out area and configured to receive a driver chip including a plurality of pads, each pad configured to be electrically coupled to a respective display element via a respective interconnect routed on the fan-out area; wherein the plurality of interconnects include a subset of first interconnects, and each first interconnect is configured to be electrically coupled to a respective first pad of the driver chip, and passes a first fan-out region and a second fan-out region to access a respective first display element; and wherein a first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch, the second interconnect pitch different from the first interconnect pitch.

Clause 2. The electronic device of clause 1, wherein the second interconnect pitch of the subset of first interconnects in the second fan-out region is greater than the first interconnect pitch of the subset of first interconnects in the first fan-out region.

Clause 3. The electronic device of clause 1 or 2, wherein the first portion of the subset of first interconnects has a first interconnect width, and the second portion of the subset of first interconnects has a second interconnect width, the second interconnect width greater than the first interconnect width.

Clause 4. The electronic device of any of clauses 1-3, wherein the fan-out area further includes a third fan-out region, the second fan-out region located between the first and third fan-out regions, and each first interconnect passes the third fan-out region.

Clause 5. The electronic device of clause 4, wherein a third portion of the subset of first interconnects is formed on the third fan-out region with a third interconnect pitch, the second interconnect pitch greater than the first interconnect pitch and less than the third interconnect pitch.

Clause 6. The electronic device of any of clauses 1-5, wherein the plurality of interconnects include a second interconnect passing the first fan-out region to electrically couple a second pad and a second display element, and the second interconnect does not extend to the second fan-out region and has a substantially uniform pitch equal to the first interconnect pitch of the subset of first interconnects in the first fan-out region.

Clause 7. The electronic device of any of clauses 1-6, where the first fan-out region has a region width equal to a driver width of the driver chip, and the plurality of interconnects passes the first fan-out region to access the plurality of pads of the driver chip.

Clause 8. The electronic device of any of clauses 1-7, wherein the driver chip includes an interconnect compensation component configured to generate electrical signals that compensate for parasitic s of one or more interconnects of the plurality of interconnects actively.

Clause 9. The electronic device of any of clauses 1-8, wherein the driver chip is flip-chip assembled to the display substrate, thereby facilitating each first interconnect to contact the respective first pad of the driver chip.

Clause 10. The electronic device of any of clauses 1-9, wherein the electronic device is one of a laptop display, a tablet computer display, and a mobile phone display, and the driver chip includes at least a source driver configured to drive the plurality of display elements and a timing controller configured to control driving of the plurality of display elements in a synchronous manner.

Clause 11. The electronic device of any of clauses 1-10, wherein: the second fan-out region is immediately adjacent to the first fan-out region; and the second interconnect pitch of the subset of first interconnects in the second fan-out region is determined based on a first interconnect length of the subset of first interconnects.

Clause 12. The electronic device of clause 11, wherein: the plurality of interconnects include a subset of second interconnects, and each second interconnect is electrically coupled to a respective second pad and passes the first fan-out region to access a respective second display element; and the subset of second interconnects have an alternative interconnect pitch and an alternative interconnect length; and the second interconnect pitch of the subset of first interconnects in the second fan-out region is determined based on the first interconnect length of the subset of first interconnects, the alternative interconnect pitch, and the alternative interconnect length.

Clause 13. The electronic device of any of clauses 1-12, wherein: the plurality of fan-out regions include a transition region connecting the first and second fan-out regions; a pitch of the subset of first interconnects increases from the first interconnect pitch to the second interconnect pitch within the transition region.

Clause 14. The electronic device of clause 13, wherein for each first interconnect, a width of the first interconnect increases from a first interconnect width to a second interconnect width within the transition region, the second interconnect width greater than the first interconnect width.

Clause 15. The electronic device of any of clauses 1-14, wherein the first portion of the subset of first interconnects is partially or entirely concealed between the display substrate and the driver chip, and the second portion of the subset of first interconnects lies on the display substrate without being concealed by the driver chip.

Clause 16. The electronic device of any of clauses 1-15, wherein the plurality of interconnects include a second interconnect, and the second interconnect is electrically coupled to a second pad of the driver chip and passes the first fan-out region to access a second display element, and at least a portion of the second interconnect is substantially parallel to a respective portion of each first interconnect.

Clause 17. The electronic device of any of clauses 1-16, wherein the fan-out area includes and is symmetric with respect to a central axis, and the central axis is located in the first fan-out region and external to the second fan-out region.

Clause 18. The electronic device of clause 17, wherein: the fan-out area further includes a fourth fan-out region; the second and fourth fan-out regions are symmetric with respect to the central axis; and a portion of a subset of third interconnects is formed on the fourth fan-out region with the second interconnect pitch.

Clause 19. The electronic device of any of clauses 1-18, wherein the plurality of interconnects are formed on a single layer of conductive material, cannot cross each other, and are spatially ordered on the display substrate.

Clause 20. The electronic device of any of clauses 1-19, further comprising: the driver chip coupled to the driver area and including the plurality of pads.

It will also be understood that, although the terms first and second are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first fastener can be termed a second fastener, and, similarly, a second fastener can be termed a first fastener, without departing from the scope of the various described implementations. The first fastener and the second fastener are both fasteners, but they are not the same fastener.

The terminology used in the description of the various described implementations herein is for the purpose of describing particular implementations only and is not intended to be limiting. As used in the description of the various described implementations and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, components, structures and/or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, structures, and/or groups thereof.

As used herein, the term “if” means “when” or “upon” or “in response to determining” or “in response to detecting” or “in accordance with a determination that,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” means “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event]” or “in accordance with a determination that [a stated condition or event] is detected,” depending on the context.