Patent ID: 12239027

DETAILED DESCRIPTION

Quantum computing entails coherently processing quantum information stored in the qubits of a quantum computer. Superconducting quantum computing is one implementation of quantum computing technology in which quantum information processing devices are formed, in part, from superconducting materials. Fabrication of integrated quantum information processing devices with superconducting components typically involves depositing and patterning superconducting materials, dielectrics and metal layers. Some quantum information processing devices, such as qubits, can be constructed using Josephson junctions.

A Josephson junction may be made by sandwiching a layer or “barrier” of a non-superconducting material between two layers of a superconducting material. The layer of non-superconducting material is thin enough to allow electrons to quantum mechanically tunnel through the non-superconducting material from one superconducting layer to another. That is, until a critical current is reached, a supercurrent can flow across the barrier and electron pairs can tunnel across the barrier without any resistance. For quantum computing a superconducting logic applications, the barrier material is an insulator, e.g., aluminum oxide.

One technique for fabricating Josephson junctions is a double-angle deposition liftoff process. During this process, a first superconductor layer is deposited at a first angle relative to patterned resist features on a wafer, followed by an oxidation of the first superconductor layer, and then followed by a second superconductor deposition at a second angle relative to the patterned resist. The two angles of the deposition result in two shifted images of the resist pattern. This technique relies on shadowing from the resist stack to mask off segments of the pattern to create two electrically distinct metal regions that are connected through the junction oxide in a well-defined overlap region in the pattern.

Josephson Junctions with Reduced Stray Inductance

The present disclosure provides methods and devices for fabricating Josephson junctions with reduced stray series inductance of junction leads using a double-angle deposition process.

FIG.1Ais a schematic diagram of an example double-angle Josephson junction. Regions102a,102brepresent a lithographically defined portion of the circuit. Regions104a,104b,104crepresent the superconductor that is deposited in the two angle steps as will be described below. The region enclosed by the dashed line108represents the region of overlap that forms the junction, and region106represents a portion of the pattern that is masked off by the resist during the two deposition steps.FIG.1Bis a schematic diagram of example deposition angles with respect to a wafer. Unlike other double angle deposition techniques, the first deposition is represented by arrow152along the negative x axis (as opposed to deposition along the + axis). The first deposition is 45θ from the wafer upper surface (the surface on which the components are formed), however in some cases the first deposition angle may take other values. The second deposition is represented by arrow154along the positive y axis (as opposed to deposition along the − axis). The second deposition is also 45° from the wafer upper surface, however this is an example only and in some cases the second deposition angle may take other values.

The double-angle deposition technique used in this specification requires that the leads connecting the junctions to the rest of the circuit are long and narrow. The width of these leads must be sufficiently small to enable masking from the resist stack, and their length is usually constrained by minimum spacing design rules of the process. For example, the leads may be 2 μm in length and 0.3-0.7 μm in width, even if the junction itself measures several μm across.

A consequence of the geometry of the junction leads is that the leads present a substantial series inductance leading to the junction, which is unacceptable in applications such as Josephson logic, Josephson amplifiers, and microwave components. Furthermore, because of the high aspect ratio of the leads, their inductance may be more difficult to control with respect to variations in the fabrication process.

One exemplary process for fabricating Josephson junctions with reduced stray inductance is described as follows with reference toFIG.2andFIGS.3A-3D.

FIG.2is a flow diagram of a first example process200for forming a Josephson junction with reduced stray inductance. For example, the process200may be used to form the Josephson junction illustrated inFIG.3Dof the present application.

A substrate including a first resist layer that has been patterned to expose an opening region is provided (step202).FIG.3Ashows a schematic of the provided substrate.

The first resist layer may have been patterned using optical lithography, and may have a height between approximately 0.1 microns to approximately 4 microns. In some implementations the first resist layer may include a bilayer resist stack where the bottom part of the stack is an undercut layer, and the top part is an imaging layer.

The opening region includes a central opening portion, a first elongated opening portion having a length that extends from a first side of the central opening portion along a first direction, and a second elongated portion having a length that extends from a second side of the central opening portion along a second direction different from, e.g., orthogonal to, the first direction.

The width of the first elongated portion is smaller than the width of the first side of the central opening. In addition, the width of the second elongated portion is smaller than the length of the second side of the central opening. In some implementations, an aspect ratio between the height of the first resist layer and the width of the first elongated opening portion or the width of the second elongated opening portion may be between 1:1 and 10:1.

A first superconductor material is deposited on the patterned resist layer at a first non-normal angle with respect to the substrate to form a first superconductor layer within the central opening portion and the first elongated opening portion of the opening region (step204).FIG.3Bshows a schematic of the substrate after a first superconductor material is deposited on the first resist layer.

An insulator layer is formed on a portion of the first superconductor layer (step206).FIG.3Cshows a schematic of the substrate an insulator layer is formed on a portion of the first superconducting layer.

A second superconductor material is deposited on the insulator layer and the patterned resist layer at a second non-normal angle with respect to the substrate to form a second superconductor layer within the central opening portion and the second elongated opening portion of the opening region (step208). The first superconductor layer, the insulator layer, and the second superconductor layer within the central opening portion provide a superconductor tunnel junction.

In some implementations, the first superconductor layer may be formed in a first section of the central opening portion, and the second superconductor layer may be formed in a second section of the central opening portion, wherein the first section of the central opening portion and the second section of the central opening portion only partially overlap. In these implementations the superconductor tunnel junction may be formed where the first section of the central opening portion and the second section of the central opening portion partially overlap.

A third superconductor layer is formed directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second separate contact to the superconductor tunnel junction, respectively (step212).FIG.3Dshows a schematic of the substrate after a third superconductor layer has been formed directly on a portion of the surface of the first superconductor layer and a portion of the surface of the second superconductor layer.

Forming the third superconductor layer may include forming a second resist layer on the first superconductor layer and on the second superconductor layer (step210), patterning the second resist layer to form a first contact opening and a second contact opening (step210), and depositing the third superconductor material on the patterned second resist layer. The third superconductor material may be deposited at an angle that is normal relative to the substrate. Forming the third superconductor layer may then further include removing the second resist layer to form the first contact and the second contact. Optionally, an ion mill may be performed on a surface of the first superconductor layer exposed in the first contact opening and on a surface of the second superconductor layer exposed in the second contact opening prior to depositing the third superconductor layer.

In implementations where the superconductor tunnel junction is formed where the first section of the central opening portion and the second section of the central opening portion partially overlap, the first contact may be formed on the surface of the first superconductor layer outside of where the first section of the central opening portion and the second section of the central opening portion partially overlap. Similarly, the second contact may be formed on the surface of the second superconductor layer outside of where the first section of the central opening portion and the second section of the central opening portion partially overlap.

In some implementations, the first contact may be formed on the surface of the first superconductor layer that is within the first elongated opening portion. In some implementations the second contact may be formed on the surface of the second superconductor layer that is within the second elongated opening portion. The width of the first contact may be greater than the width of the first superconductor layer within the first elongated portion. In addition, the width of the second contact may be greater than the width of the second superconductor layer within the second elongated portion.

For convenience, the process200has been described with reference to forming a single Josephson junction using a first resist layer that has been patterned to expose a single opening region. However, in some implementations the first resist layer may include multiple opening regions so that the process200can be used to form multiple Josephson junctions in parallel.

The device formed by process200, e.g., the device shown inFIG.3Dbelow, may be provided for use in various applications. For example, the device may be provided for use as an element in a quantum circuit, a Josephson amplifier or as a microwave component. As another example, the device may be provided for use as an element in an analog circuit, e.g., a microwave component such as a switch, mixer, phase shifter, resonator, filter or detector.

FIGS.3A-3Dare schematic diagrams of a plan view and cross-sectional views of an example substrate302during the first example process200for forming a Josephson junction with reduced stray inductance.

FIG.3Ashows a schematic of a provided substrate302in plan-view300a, cross-sectional view300bthrough axis A-A′, and cross-sectional view300cthrough axis B-B′. The provided substrate302corresponds to the substrate provided at step202ofFIG.2.

The substrate302includes a first resist layer304that is used to define the Josephson junction. In some implementations, the height of the first resist layer304may be, e.g., between approximately 0.1 microns to approximately 4 microns. The first resist layer304is patterned to expose an opening region306defined by the dashed lines. The size of the area of the opening306is dependent on the process and the circuit to which the junction will be connected. However, the size of the area of the opening306may be limited by factors such as defectivity, stray capacitance of the junction and fabrication considerations. As an example, the size of the area of the opening306may be smaller than 5.0 μm by 5.0 μm. In some implementations, the first resist layer304may be patterned using optical lithography.

The opening region306includes a central opening portion306a, a first elongated opening portion306b, and a second elongated opening portion306c.

The first elongated opening portion306bhas a length that extends from a first side308aof the central opening portion306aalong a first direction. The width310of the first elongated opening portion306bis smaller than the length312of the first side308aof the central opening306a(or, equivalently, narrower than the width of the central opening portion306a). In some implementations the width310may be approximately equal to 0.3 μm. In some implementations the length L1of the first elongated opening portion306bmay be approximately equal to 2 μm. In some implementations an aspect ratio between a height of the first resist layer304and a width310of the first elongated opening portion306bs between 1:1 and 10:1.

The second elongated portion306chas a length that extends from a second side308bof the central opening portion306aalong a second direction that is different from the first direction. For example, the first direction is orthogonal to the second direction. The width314of the second elongated portion306cis smaller than the length of the second side308bof the central opening portion306a(or, equivalently, narrower than the height316of the central opening portion306a). In some implementations the width314may be approximately equal to 0.3 μm and/or the height316of the central opening portion306amay be approximately equal to 3.5 μm. In some implementations an aspect ratio between a height of the first resist layer304and a width314of the second elongated opening portion306cmay be between 1:1 and 10:1.

Each of the elongated portions306b,306cmay be coupled to a first and second device or component,318b,318c, respectively, that are formed on the substrate302. For example, devices or components318b,318cmay include a ground connection, a capacitor, an inductor, another Josephson junction, a co-planar waveguide, a qubit, a qubit readout resonator, a qubit control element (e.g., a qubit Z-control or qubit XY control element), among other circuit elements.

FIG.3Bshows a schematic of the substrate302in plan-view300d, cross-sectional view300ethrough axis C-C′, and cross-sectional view300fthrough axis D-D′ after a first superconductor material320is deposited on the first resist layer304shown inFIG.3A. For example, the schematic of the substrate302shown inFIG.3Bcorresponds to step204ofFIG.2. In some implementations, the first superconductor material320may be aluminum.

The first superconductor material320may be deposited on the first resist layer304at a first non-normal angle with respect to an upper surface of the substrate302, as described above with reference toFIG.1B. In some implementations, the first non-normal angle may be 45 degrees. Depositing the first superconductor material320at the first non-normal angle with respect to the substrate surface302forms a first superconductor layer322(defined by the dashed lines) within the central opening portion306aand the first elongated opening portion306bof the opening region306.

FIG.3Cshows a schematic of the substrate302in plan-view300g, cross-sectional view300hthrough axis E-E′, and cross-sectional view300ithrough axis F-F′ after an insulator layer360, e.g., an oxide layer, is formed on a portion of the first superconducting layer322ofFIG.3Band a second superconductor material326is deposited on the insulator layer360and the first resist layer304shown inFIG.3A. For example, the schematic of the substrate302shown inFIG.3Ccorresponds to step206ofFIG.2. In some implementations, the second superconductor material326may be aluminum.

The second superconductor material326may be deposited on the insulator layer360and the first resist layer304at a second non-normal angle with respect to the substrate302, as described above with reference toFIG.1B. In some implementations, the second non-normal angle may be 45 degrees. Depositing the second superconductor material326at the second non-normal angle with respect to the substrate surface302forms a second superconductor layer328(defined by the dotted lines) within the central opening portion306aand the second elongated opening portion306cof the opening region306.

The portions of the first superconductor layer322, the insulator layer360, and the second superconductor layer328that lie within the central opening portion306aand that overlap provide a superconductor tunnel junction. In some implementations, a first section of the central opening portion306ain which the first superconductor layer322is formed and a second section of the central opening portion306ain which the second superconductor layer328is formed may only partially overlap, e.g., in area330. In the example shown inFIG.3C, the superconductor tunnel junction is defined within the region enclosed by dashed lines324.

FIG.3Dshows a schematic of the substrate302after a third superconductor layer has been formed directly on a portion of the surface of the first superconductor layer322ofFIG.3Cand a portion of the surface of the second superconductor layer328ofFIG.3C. For example, the schematic of the substrate302shown inFIG.3Dcorresponds to step212ofFIG.2.

The third superconductor layer provides a first contact332ato the superconducting tunnel junction330and a second separate contact332bto the superconductor tunnel junction330, respectively. Deposition of the third superconductor layer provides electrical contact to the superconductor tunnel junction330and to the rest of the circuit (e.g., lithographically defined portions318aand318b) to provide a current path.

In some implementations, the first contact332amay be formed on the surface of the first superconductor layer322outside of where the first section of the central opening portion306aand the second section of the central opening portion306apartially overlap, e.g., outside of region330. In these implementations the first contact332amay be formed on the surface of the first superconductor layer322that is within the first elongated opening portion306b.

Similarly, in some implementations the second contact332bmay be formed on the surface of the second superconductor layer328outside of where the first section of the central opening portion306aand the second section of the central opening portion306apartially overlap, e.g., outside of region330. In these implementations the second contact332bmay be formed on the surface of the second superconductor layer328that is within the second elongated opening portion306c.

The width334aof the first contact332ais greater than the width of the first superconductor layer322within the first elongated portion306b(e.g., width310ofFIG.3A). Similarly, the width334bof the second contact332bis greater than the width of the second superconductor layer328within the second elongated portion306b(e.g., width314ofFIG.3A). In some implementations, the width334aof the first contact332aand/or width334bof the second contact332bmay be approximately equal to 2 μm, or equal to a value between 2 μm and 5 μm. Such widths can reduce the Josephson junction lead stray inductance to approximately 2 pH per lead. In cases where a wider contact is required, additional width can be realized by extending other elements, e.g., lithographically defined portions318aand318b.

Another exemplary process for fabricating Josephson junctions with reduced stray inductance is described as follows with reference toFIG.4andFIGS.5A-5C.

FIG.4is a flow diagram of a second example process400for forming a Josephson junction with reduced stray inductance. For example, the process400may be used to form the Josephson junction illustrated inFIG.5Dof the present application.

A substrate including a first resist layer patterned to include an opening region that exposes a surface of the substrate is provided (step402). In some implementations the first resist layer may be a bilayer, i.e., a later suitable for angled deposition techniques. In some implementations, the first resist layer may have been patterned using optical lithography, and may have a height between approximately 0.1 microns to approximately 4 microns.

The opening region may be, e.g., in the shape of a rectangle (such as a square) that is laterally enclosed on all sides by the first resists layer. For instance, the opening region is a central opening region that is without any elongated opening portions that extend outwardly from the central opening region. The size of the area of the central opening region is dependent on the deposition angle and the resist thickness. For example, the area of the central opening region may be at least 1 μm by 1 μm for a 1 μm thick resist and 45 degree deposition angle. A schematic of the substrate provided at step402is shown inFIG.5A.

A first superconductor material is deposited on the patterned resist layer at a first non-normal angle with respect to the substrate along a first direction to form a first superconductor layer within the opening region (step404). The patterned resist layer blocks the first superconductor layer from forming in at least a first part of the opening region.FIG.5Bshows a schematic of the substrate after a first superconductor material is deposited on the first resist layer.

An insulator layer is formed on a portion of the first superconductor layer (step406).

A second superconductor material is deposited on the insulator layer and the patterned resist layer at a second non-normal angle with respect to the substrate along a second direction to form a second superconductor layer within the opening region (step408). The patterned resist layer blocks the second superconductor layer from forming in at least a second part of the opening region, and the first superconductor layer, the insulator layer, and the second superconductor layer within the opening region provide a superconductor tunnel junction.FIG.5Cshows a schematic of the substrate after an insulator layer is formed on a portion of the first superconducting layer and a second superconductor material is deposited on the insulator layer and the first resist layer.

In some implementations, the first superconductor layer may be formed in a first section of the opening region, and the second superconductor layer may be formed in a second section of the opening region. The first section of the opening region and the second section of the opening region may only partially overlap. In these implementations, the superconductor tunnel junction may be formed where the first section of the opening region and the second section of the opening region partially overlap.

A third superconductor layer is formed directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer (after a second patterning step, as described below) to provide a first contact to the superconducting tunnel junction and a second separate contact to the superconductor tunnel junction, respectively (step410). The first contact may be formed on the surface of the first superconductor layer outside of where the first section of the opening region and the second section of the opening region partially overlap. Similarly, the second contact may be formed on the surface of the second superconductor layer outside of where the first section of the opening region and the second section of the opening region partially overlap.FIG.5Dshows a schematic of the substrate after a third superconductor layer has been formed directly on a portion of the surface of the first superconductor layer and a portion of the surface of the second superconductor layer.

In some implementations, the first contact extends away from a first side of the opening region, and the second contact extends away from a second different side of the opening region. In these implementations the first contact and the second contact may extend along orthogonal directions.

Forming the third superconductor layer may include forming a second resist layer on the first superconductor layer and the second superconductor layer, patterning the second resist layer to form a first contact opening and a second contact opening, and depositing the third superconductor on the patterned second resist layer and removing the second resist layer to form the first contact and the second contact. Optionally, an ion mill may be performed on a surface of the first superconductor layer exposed in the first contact opening and on a surface of the second superconductor layer exposed in the second contact opening prior to depositing the third superconductor layer.

For convenience, the process400has been described with reference to forming a single Josephson junction using a first resist layer that has been patterned to expose a single opening region. However, in some implementations, the first resist layer may include multiple opening regions so that the process400can be used to form multiple Josephson junctions in parallel.

The device formed by process400, e.g., the device shown inFIG.5Dbelow, may be provided for use in various applications. For example, the device may be provided for use as an element in a quantum circuit, a Josephson amplifier or as a microwave component. As another example, the device may be provided for use as an element in an analog circuit, e.g., as a microwave component such as a switch, mixer, phase shifter, resonator, filter or detector.

FIGS.5A-5Dare schematic diagrams of a plan view of an example substrate502during the second example process400for forming a Josephson junction with reduced stray inductance.

FIG.5Ashows a schematic of the provided substrate502. The substrate502includes a first resist layer504that is used to define the Josephson junction. In some implementations the height of the first resist layer504may be between approximately 0.1 microns to approximately 4 microns. The first resist layer504is patterned to include an opening region506that exposes a surface of the substrate502. For example, the first resist layer504may be patterned using optical lithography. The opening region506includes, e.g., a rectangular opening region (such as a square opening region) that is laterally enclosed on all sides by the first resist layer504. For instance, the opening region506is a central opening region that is without any elongated opening portions (such as elongated portions306c,306bshown inFIG.3A) that extend outwardly from the central opening region506. The schematic of the substrate502shown inFIG.5Acorresponds to step402ofFIG.4.

FIG.5Bshows a schematic of the substrate502after a first superconductor material508is deposited on the first resist layer504shown inFIG.5A. The schematic of the substrate502shown inFIG.5Bcorresponds to step404ofFIG.4. In some implementations, the first superconductor material508may be aluminum.

The first superconductor material508may be deposited on the first resist layer504at a first non-normal angle along a first direction with respect to the upper surface of the substrate502, as described above with reference toFIG.1B. In some implementations the first non-normal angle may be 45 degrees. Depositing the first superconductor material508at the first non-normal angle along the first direction with respect to the substrate502forms a first superconductor layer510(defined by the dotted lines) within the opening region506. As shown inFIG.5B, the patterning of the resist layer504blocks the first superconductor layer510from forming in at least a first part of the opening region506, e.g., in the top section of the opening region506. An insulator layer, e.g., an oxide layer, can be formed on a portion of the first superconducting layer510, which can serve as a barrier layer of a superconductor tunnel junction or a Josephson junction.

FIG.5Cshows a schematic of the substrate502after an insulator layer, e.g., an oxide layer, is formed on a portion of the first superconducting layer510ofFIG.5Band a second superconductor material512is deposited on the insulator layer and the first resist layer504shown inFIG.5A. The schematic of the substrate502shown inFIG.5Ccorresponds to step406ofFIG.4. In some implementations, the second superconductor material512may be aluminum.

The second superconductor material512may be deposited on the insulator layer and the first resist layer504at a second non-normal angle along a second direction with respect to the upper surface of the substrate502, as described above with reference toFIG.1B. In some implementations, the second non-normal angle may be 45 degrees. Depositing the second superconductor material512at the second non-normal angle along the second direction with respect to the substrate502forms a second superconductor layer514(defined by the shaded area) within the opening region506. As shown inFIG.5C, the patterning of the resist layer504blocks the second superconductor layer514from forming in at least a second part of the opening region506, e.g., in the right most section of the opening region506, leaving the right uppermost corner having no superconductor layer formed on the exposed portion of the substrate.

The first superconductor layer510, the insulator layer, and the second superconductor layer514within the opening region506provide a superconductor tunnel junction. In some implementations, a first section of the opening portion506in which the first superconductor layer510is formed and a second section of the opening portion506in which the second superconductor layer514is formed may only partially overlap, e.g., in area516. In these implementations, the superconductor tunnel junction may be formed where the first section of the opening portion506and the second section of the opening portion506partially overlap. In the example shown inFIG.5C, the superconductor tunnel junction is defined within the region enclosed by dashed lines518.

FIG.5Dshows a schematic of the substrate502after a third superconductor layer has been formed directly on a portion of the surface of the first superconductor layer510ofFIG.5Band a portion of the surface of the second superconductor layer514ofFIG.5C. The third superconductor layer provides a first contact520ato the superconducting tunnel junction518and a second separate contact520bto the superconductor tunnel junction518, respectively. The schematic of the substrate502shown inFIG.5Dcorresponds to step410ofFIG.4.

In some implementations, the first contact520amay be formed on the surface of the first superconductor layer510outside of where the first section of the opening portion506and the second section of the opening portion506partially overlap, e.g., outside of region516ofFIG.5C. Similarly, in some implementations, the second contact520bmay be formed on the surface of the second superconductor layer514outside of where the first section of the opening portion506and the second section of the opening portion506partially overlap, e.g., outside of region516ofFIG.5C.

As shown inFIG.5D, the first contact520amay extend away from a first side522aof the opening region506, and the second contact520bmay extend away from a second different side522bof the opening region. In some implementations, the first contact520aand the second contact520bmay extend along orthogonal directions, i.e., the first side522aand second side522bmay be orthogonal.

Deposition of the third superconductor layer in this manner provides electrical contact to the superconductor tunnel junction518and to the rest of the circuit, e.g., circuit elements524aand524b, to provide a low inductance current path. Circuit elements524aand524bmay include, e.g., other components formed on the substrate including, e.g., ground connections, inductors, capacitors, other Josephson junctions, a qubit, a co-planar waveguide, a qubit readout resonator, a qubit control element (e.g., a qubit Z-control element or a qubit XY-control element), among other circuit elements. Although not shown inFIG.5D, in some implementations circuit elements520a,520b,524a, and524bmay be wider than the junction leads514and510(if needed, e.g., to reduce inductance).

An example of a superconducting material that can be used in the formation of quantum circuit elements is aluminum. Aluminum may be used in combination with a dielectric to establish Josephson junctions, which are a common component of quantum circuit elements. Examples of quantum circuit elements that may be formed with aluminum include circuit elements such as superconducting co-planar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), inductors, capacitors, transmission lines, ground planes, among others. Other superconductor materials may include, e.g., niobium or titanium nitride.

Aluminum may also be used in the formation of superconducting classical circuit elements that are interoperable with superconducting quantum circuit elements as well as other classical circuit elements based on complementary metal oxide semiconductor (CMOS) circuitry. Examples of classical circuit elements that may be formed with aluminum include rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are energy-efficient versions of RSFQ that does not use bias resistors. Other classical circuit elements may be formed with aluminum as well. The classical circuit elements may be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form.

Another example of a superconducting material that can be used in the formation of quantum circuit elements is Niobium. Niobium may be used in the formation of wiring, waveguides, inductors or capacitors. In some implementations different types of superconducting materials may be used in a same circuit element. For example, a first type of superconductor material, e.g. Niobium, may be used for wiring, waveguides, inductors, capacitors, etc., and a second type of superconductor, e.g., Aluminum, may be used for forming Josephson junctions.

Processes described herein may entail the deposition of one or more materials, such as superconductors, dielectrics and/or metals. Depending on the selected material, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. Processes described herein may also entail the removal of one or more materials from a device during fabrication. Depending on the material to be removed, the removal process may include, e.g., wet etching techniques, dry etching techniques, lift-off processes, or chemical-mechanical polishing.

Implementations of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, analog electronic circuitry, suitable quantum circuitry or, more generally, quantum computational systems, in tangibly-embodied software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term “quantum computational systems” may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

The terms quantum information and quantum data refer to information or data that is carried by, held or stored in quantum systems, where the smallest non-trivial system is a qubit, i.e., a system that defines the unit of quantum information. It is understood that the term “qubit” encompasses all quantum systems that may be suitably approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., with two or more levels. By way of example, such systems can include atoms, electrons, photons, ions or superconducting qubits. In many implementations the computational basis states are identified with the ground and first excited states, however it is understood that other setups where the computational states are identified with higher level excited states are possible.

Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, the quantum circuit elements are configured to make use of quantum-mechanical phenomena, such as superposition and entanglement, to perform operations on data in a non-deterministic manner. Certain quantum circuit elements, such as qubits, can be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUID or DC-SQUID), among others.

In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to collectively carry out instructions of a computer program by performing basic arithmetical, logical, and/or input/output operations on data, in which the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to transmit data to and/or receive data from the quantum circuit elements through electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuitry, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices and ERSFQ devices, which are an energy-efficient version of RSFQ that does not use bias resistors.

In certain cases, some or all of the quantum and/or classical circuit elements may be implemented using, e.g., superconducting quantum and/or classical circuit elements. Fabrication of the superconducting circuit elements can entail the deposition of one or more materials, such as superconductors, dielectrics and/or metals. Depending on the selected material, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. Processes for fabricating circuit elements described herein can entail the removal of one or more materials from a device during fabrication. Depending on the material to be removed, the removal process can include, e.g., wet etching techniques, dry etching techniques, lift-off processes, or chemical-mechanical polishing. The materials forming the circuit elements described herein can be patterned using known lithographic techniques (e.g., photolithography or e-beam lithography).

During operation of a quantum computational system that uses superconducting quantum circuit elements and/or superconducting classical circuit elements, such as the circuit elements described herein, the superconducting circuit elements are cooled down within a cryostat to temperatures that allow a superconductor material to exhibit superconducting properties. A superconductor (alternatively superconducting) material can be understood as material that exhibits superconducting properties at or below a superconducting critical temperature. Examples of superconducting material include aluminum (superconductive critical temperature of 1.2 Kelvin) and niobium (superconducting critical temperature of 9.3 Kelvin). Accordingly, superconducting structures, such as superconducting traces and superconducting ground planes, are formed from material that exhibits superconducting properties at or below a superconducting critical temperature.

In certain implementations, control signals for the quantum circuit elements (e.g., qubits and qubit couplers) may be provided using classical circuit elements that are electrically and/or electromagnetically coupled to the quantum circuit elements. The control signals may be provided in digital and/or analog form.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.