Patent ID: 12230219

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. Suffixes may be attached to reference numerals for distinguishing identical elements from each other. The drawings referred to herein should not be understood as being drawn to scale unless specifically noted. Also, the drawings are often simplified and details or components omitted for clarity of presentation and explanation. The drawings and discussion serve to explain principles discussed below, where like designations denote like elements.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the disclosure or the application and uses of the disclosure. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background, summary, or the following detailed description. The term “coupled” as used herein means connected directly to or connected through one or more intervening components or circuits.

A display driver that drives a display panel may be configured to receive image data from an external entity (e.g., a host, a controller, a processor, or other devices configured to provide the image data). Image data transfer from the external entity to the display driver may be asynchronous or synchronous with a vertical sync signal generated in the display driver.

In an asynchronous mode, the external entity may encapsulate image data in one or more commands and send the one or more commands to the display driver at arbitrary timing, asynchronously with the vertical sync signal generated in the display driver. In this case, the display driver may retrieve the image data from the commands and update the display panel based on the retrieved image data.

In a synchronous mode, the external entity may send image data to the display driver with external sync control inputs, such as external sync packets (e.g., vertical sync packets and horizontal sync packets), and external sync signals (e.g., an external vertical sync signal and an external horizontal sync signal). In this case, the display driver may generate the vertical sync signal based on the external sync control inputs and update the display panel based on the image data in synchronization with the generated vertical sync signal.

Some display drivers are adapted to both asynchronous and synchronous image data transfer. Such a display driver may be configured to, in an asynchronous mode, update the display panel based on image data encapsulated in one or more commands received asynchronously with the vertical sync signal. The display driver may be further configured to, in a synchronous mode, receive image data and external sync control inputs (e.g., vertical sync packets and an external vertical sync signal) from the external source, generate the vertical sync signal based on the external sync control inputs, and update the display panel based on the received image data in synchronization with the generated vertical sync signal.

Mode switching from the asynchronous mode to the synchronous mode may cause display image artifacts since the mode switching may disturb the periodicity of the vertical sync signal generated in the display driver. The disturbed vertical sync signal may cause unsuccessful timing control in updating or controlling the display panel, resulting in display image artifacts. For example, in embodiments where light emission of display elements in the display panel are controlled in synchronization with the vertical sync signal, the disturbed periodicity of the vertical sync signal may disorder the light emission control, causing luminance unevenness in the display image.

The present disclosure provides various measures to mitigate display artifact potentially caused by the mode switching. In one or more embodiments, a display driver includes a graphic random access memory (GRAM), a data driver, and a control circuit. The data driver is configured to, in a first mode, update a plurality of display elements of a display panel based at least in part on a command provided to the display driver asynchronously with a display vertical sync signal generated in the display driver. The data driver is further configured to, in a second mode, update the display elements of the display panel based at least in part on first image data stored in the GRAM in synchronization with the display vertical sync signal. The data driver is further configured to, in a third mode, update the display elements of the display panel in synchronization with an external vertical sync signal. The control circuit is configured to switch the display driver from the first mode to a second mode in response to a first command. The control circuit is further configured to, in the second mode, adjust the display vertical sync signal based at least in part on an external vertical sync signal. The control circuit is further configured to switch the display driver to the third mode after achieving synchronization of the display vertical sync signal with the external vertical sync signal.

In such embodiments, the second mode uses the GRAM while adjusting the display vertical sync signal based on the external vertical sync signal. Accordingly, switching the display driver to the second mode may effectively improve flexibility in achieving synchronization between the external vertical sync signal and the display vertical sync signal. In one embodiment, the use of the second mode may mitigate display image artifacts potentially caused by disturbance in the periodicity of the display vertical sync signal. In the following, a detailed description is given of various embodiments of the present disclosure.

FIG.1shows an example configuration of a display device1000, according to one or more embodiment. In the shown embodiment, the display device1000comprises a display panel100and a display driver200. The display panel100may be a self-luminous display panel such as an organic light emitting diode (OLED) display panel and a micro light emitting diode (μLED) display panel. The display device1000is configured to display an image on the display panel100based on image data received from an external source300. Examples of the external source300include a host, a controller, a processor, or other devices suitable for providing the image data.

In the shown embodiment, the display panel100includes a display area110, a gate scan driver120, and an emission scan driver130. The display area110includes display elements112, gate lines114, emission lines116, and source lines118. The gate lines114are coupled to the gate scan driver120and the emission lines116are coupled to the emission scan driver130. The source lines118are coupled to the display driver200. Each row of display elements112is coupled to a corresponding gate line114and a corresponding emission line116, while each column of display elements is coupled to a corresponding source line118. Each display element112is configured to be updated or programed with a data voltage received from the display driver200and emit light with a luminance level corresponding to the data voltage. In embodiments where the display panel100is an OLED display panel, each display element112may include an OLED element configured to emit light according to the data voltage. In one or more embodiments, programing a display element112with a data voltage is achieved by asserting the gate line114coupled to the display element112while the display driver200generates the data voltage on the source line118coupled to the display element112.

The gate scan driver120is configured to control update or programing of display elements112of respective “horizontal lines.” A “horizontal line” referred herein is a row of display elements112coupled to the same gate line114and the same emission line116. In one implementation, the gate scan driver120is configured to sequentially assert the gate lines114to sequentially allow programming of the display elements112of respective horizontal lines with data voltage generated by the display driver200. The operation of the gate scan driver120may be controlled by a gate scan start pulse signal GSTV and a gate scan clock GCK received from the display driver200.

The emission scan driver130is configured to control light emission of display elements112of respective horizontal lines with the emission lines116. The emission scan driver130may be configured to, when allowing display elements112of a horizontal line to emit light, assert the emission line116coupled to the display elements112of the horizontal line. The emission scan driver130may be further configured to, when prohibiting display elements112of a horizontal line from emitting light, deassert the emission line116coupled to the display elements112of the horizontal line. The operation of the emission scan driver130may be controlled by an emission scan start pulse signal ESTV and an emission scan clock ECK received from the display driver200.

The display driver200is configured to update the display elements112based at least in part on image data received from the external source300. In one implementation, the image data include graylevels of the respective display elements112. The display driver200may be configured to generate data voltages corresponding to the graylevels of the respective display elements112and update or program the display elements112with the generated data voltages via the source lines118.

The display driver200is further configured to control the gate scan driver120with a gate scan start pulse signal GSTV and a gate scan clock GCK. The gate scan driver120may be configured to scan the gate lines114in response to the gate scan start pulse signal GSTV in synchronization with the gate scan clock GCK.

The display driver200is further configured to control the emission scan driver130with an emission scan start pulse signal ESTV and an emission scan clock ECK. The emission scan driver130may be configured to assert selected ones of the emission lines116in response to the emission scan start pulse signal ESTV in synchronization with the emission scan clock ECK. In one implementation, the emission scan start pulse signal ESTV carries emission pulses that control the display brightness level of the display device1000. The display brightness level may be the overall brightness level of the image displayed on the display panel100. Details of the control of the display brightness level based on the emission pulses in the emission scan start pulse signal ESTV will be described later in detail.

The display driver200is configured to receive external sync control inputs from the external source300. The external sync control inputs may include vertical sync (Vsync) packets and horizontal sync (Hsync) packets. The Vsync packets may indicate starts of respective frame periods and thereby define the frame periods (or vertical sync periods). The Hsync packets may indicate starts of respective line periods (or horizontal sync periods) and thereby define the line periods. In other embodiments, the external sync control inputs may include an external vertical sync signal and an external horizontal sync signal. The display driver200may be configured to generate a display vertical sync signal and a display horizontal sync signal in response to the external sync control inputs and use the display vertical sync signal and the display horizontal sync signal for timing control in the display device1000. For example, the display driver200may be configured to generate the gate scan start pulse signal GSTV and the emission scan start pulse signal ESTV based at least in part on the display vertical sync signal and the display horizontal sync signal.

In one or more embodiments, the display device1000is adapted to two image data transfer schemes: a command mode and a video through mode. In the command mode, the external source300provides one or more commands that encapsulate image data to display driver200only when desiring update of one or more display elements112in the display panel100. The use of the command mode effectively reduces the power consumption of the display device1000. In the command mode, the external source300provides one or more commands at arbitrary timing, not providing the external sync control inputs to the display driver200. The display driver200generates the display vertical sync signal and the display horizontal sync signal by itself without using the external sync control inputs. The command mode can be considered as a sort of the asynchronous mode described above.

In the video through mode, the external source300continuously provides video packets that encapsulate image data to the display driver200(e.g., in the form of a video data stream) and the display driver200updates the display panel100based on the image data every frame period (or every vertical sync period). In the video through mode, the external source300provides the external sync control inputs as well as the video packets and the display driver200generates the display vertical sync signal and the display horizontal sync signal based on the external sync control inputs. The video through mode can be considered as a sort of the synchronous mode described above.

The mode switching from the command mode to the video through mode may cause display image artifacts since the mode switching may cause disturbance in the periodicity of the display vertical sync signal. In the following, the display brightness control is first described and then occurrence of a display image artifact caused by the mode switching is discussed.

FIGS.2A and2Billustrates example control of the display brightness level of the display device1000based on emission pulses carried by the emission scan start pulse signal ESTV, according to one or more embodiments. The top parts ofFIGS.2A and2Bshow example waveforms of the emission scan start pulse signal ESTV and the emission scan clock ECK while the bottom parts show example images displayed on the display panel100at certain instances of time (instances of time t1and t2forFIG.2Aand instances of time t3and t4forFIG.2B). InFIGS.2A and2B, the numerals201denote non-light-emitting regions in which no display elements112emit light. In one implementation, emission lines116in the non-light-emitting regions are deasserted by the emission scan driver130to prohibit emit light from display elements112coupled to the emission lines116. The display brightness level is controlled by the total area of the non-light-emitting regions in the display image.

The middle parts ofFIGS.2A and2Bshow example over-time changes in horizontal lines located in non-light-emitting regions. The vertical axis represents horizontal lines while the horizontal axis represents the time. The hatched areas202indicate horizontal lines located in non-light-emitting regions.

In one or more embodiments, emission pulses carried by the emission scan start pulse signal ESTV controls the number and widths of non-light-emitting regions201in the display panel100. Each emission pulse indicates the emission scan driver130(shown inFIG.1) to introduce a non-light-emitting region201from the top edge of the display area110. The width of the introduced non-light-emitting region201is based on the width of the emission pulse. In one implementation, the emission scan driver130introduces the non-light-emitting region201while the emission pulse is appearing on the emission scan start pulse signal ESTV. The introduced non-light-emitting region201is then scrolled or shifted downward of the display panel100in synchronization with the emission scan clock ECK. The number of the non-light-emitting regions201in the display area110is controlled by the number of emission pulses that appear in the emission scan start pulse signal ESTV per frame period (which is defined by the display Vsync signal) while the width of the non-light-emitting regions201is controlled by the width of emission pulses. In one implementation, the number of the non-light-emitting regions201is equal to the number of the emission pulses per frame period and the width of the non-light-emitting regions are proportional to the width of the emission pulses.FIG.2Ashows the case where one emission pulse appears in the emission scan start pulse signal ESTV during each frame period whileFIG.2Bshows the case where four emission pulses appear during each frame period. The display brightness level is lower as the number and/or width of non-light-emitting regions increases.

In an ideal operation (as shown inFIGS.2A and2B), the emission scan start pulse signal ESTV is generated in synchronization with the display Vsync signal such that emission pulses appear at regular time intervals with a fixed periodicity. If the emission pulses are not generated at regular time intervals, this may cause irregularity in the arrangement of the non-light-emitting regions201, potentially resulting in a display image artifact.

Mode switching (e.g., from the command mode to the video through mode) may generate irregularity in the emission pulses in the emission scan start pulse signal ESTV since the mode switching may disturb the periodicity of the display Vsync signal, which is used to generate the emission scan start pulse signal ESTV.FIG.2Cshows an example display artifact caused by the disturbance in the periodicity of the display Vsync signal caused by mode switching. In the shown operation, the timing at which the display Vsync signal is second asserted is delayed due to the mode switching. The delay in the assertion timing of the display Vsync signal causes irregularity in the emission pulses. In the shown operation, the pulse width of an emission pulse denoted by “1” inFIG.2Cis erroneously enlarged, and the enlarged pulse width causes an undesirably enlarged width of the corresponding non-light-emitting region, indicated by the numeral203. The region204indicates that an increased number of horizontal lines belong to the enlarged non-light-emitting region203. The undesired enlargement in the non-light-emitting region width may generate irregularity in the arrangement of the non-light-emitting regions, causing a display image artifact.

FIG.3shows an example configuration of the display driver200adapted to mitigate display image artifacts potentially caused by mode switching, according to one or more embodiments. In the shown embodiment, the display driver200includes an interface (I/F) circuit205, a drive circuitry210, a control circuit230, a brightness controller250, an emission pulse generator260, and a gate in panel (GIP) pulse generator270.

The interface circuit205is configured to receive image data from the external source300and forward the received image data to the drive circuitry210. The image data may be transferred to the display driver200in the form of commands or video packets as described in relation toFIG.1. The interface circuit205is further configured to receive various commands from the external source300. The commands received from the external source300may include a mode switching command. The display driver200is configured to switch the operation mode in response to the mode switching command as discussed later in detail.

The interface circuit205is further configured to generate an external vertical sync (Vsync) signal and an external horizontal sync (Hsync) signal based at least in part on the external sync control inputs received from the external source300. In embodiments where the external sync control inputs include Vsync packets and Hsync packets, the interface circuit205may be configured to generate the external Vsync signal in synchronization with the Vsync packets and generate the external Hsync signal in synchronization with the Hsync packets. The external Vsync signal and external Hsync signal are provided to the control circuit230. In other embodiments, the external sync control inputs may include an external Vsync signal and an external Hsync signal. In this case, the interface circuit205forwards the external Vsync signal and the external Hsync signal to the control circuit230.

The drive circuitry210is configured to update or program the display elements112of the display panel100based at least in part on the image data received from the external source300via the interface circuit205. In the shown embodiment, the drive circuitry210include a selector212, a line buffer214, a graphic random access memory (GRAM)216, a selector218, an image processing circuit220, a line latch222, and a data driver224. The selector212is configured to selectively forward the commands or video packets, which are received from the external source300, to the line buffer214. The line buffer214is configured to store image data for one horizontal line of the display panel100and forward the stored image data to the GRAM216. The GRAM216is configured to store image data for one frame image to be displayed on the display panel100. The image data stored in the GRAM216is successively updated with the image data received from the line buffer214. The selector218is configured to selectively couple the output of the line buffer214or the output of the GRAM216to the image processing circuit220depending on the operation mode of the display driver200. The image processing circuit220is configured to process image data received from the line buffer214or the GRAM216and provide the processed image data to the line latch222. The line latch222is configured to latch the processed image data from the image processing circuit220in units of horizontal lines and forward the processed image data to the data driver224. The data driver224is configured to update or program the display elements112of the display panel100based at least in part on the processed image data. In one implementation, the processed image data may include graylevels of the respective display elements112and the data driver224may be configured to update or program the display elements112with data voltages corresponding to the graylevels the respective display elements112.

The control circuit230is configured to generate the display vertical sync (Vsync) signal and the display horizontal sync (Hsync) signal, which are used for timing control in the display driver200. The display Vsync signal defines frame periods (or vertical sync periods) and the display Hsync signals defines line periods (or horizontal sync periods). In one or more embodiments, the control circuit230is configured to generate an internal Hsync signal based on an internal oscillator clock OSC_CLK generated by an internal oscillator (not shown) disposed in the display driver200and select the display Hsync signal from between the internal Hsync signal and the external Hsync signal. The control circuit230is further configured to generate an internal Vsync signal based on the display Hsync signal and select the display Vsync signal from between the internal Vsync signal and the external Vsync signal. Details of the configuration and operation of the control circuit230will be describe later.

The brightness controller250is configured to control the display brightness level of the display device1000. As discussed in relation toFIGS.2A and2B, the display brightness level is controllable with widths of emission pulses carried by the emission scan start pulse signal ESTV and the number of the emission pulses per frame period (or per vertical sync period). In one implementation, the brightness controller250is configured to determine the periodicity of emission pulses and the widths of the emission pulses in accordance with a target display brightness level.

The emission pulse generator260is configured to generate the emission scan start pulse signal ESTV, which carries emission pulses, using the display Vsync signal and the display Hsync signal received from the control circuit230. The emission scan start pulse signal ESTV is generated such that the emission pulses have periodicity and pulse widths as indicated by the brightness controller250.

The GIP pulse generator270is configured to generate the gate scan start pulse signal GSTV using the display Vsync signal and the display Hsync signal. As described in relation toFIG.1, the gate scan start pulse signal GSTV is used to control the gate scan driver120.

In the following, a description is given of details of the control circuit230. In the shown embodiment, the control circuit230includes an internal Hsync generator232, a selector234, an internal Vsync generator236, a selector238and a display mode controller240. The internal Hsync generator232is configured to generate an internal Hsync signal using an internal oscillator clock OSC_CLK generated by an internal oscillator (not shown) disposed in the display driver200. In one implementation, the internal Hsync signal may be generated by counting the internal oscillator clock OSC_CLK. The selector234is configured to select the display Hsync signal from between the internal Hsync signal and the external Hsync signal. The selection of the display Hsync signal is based on an Hsync mode signal received from the display mode controller240. The internal Vsync generator236is configured to generate an internal Vsync signal using the display Hsync signal. In one implementation, the internal Vsync signal may be generated by counting the display Hsync signal. The selector238is configured to select the display Vsync signal from between the internal Vsync signal and the external Vsync signal. The selection of the display Vsync signal is based on a Vsync mode signal received from the display mode controller240.

In the shown embodiment, the control circuit230further includes an emission synchronization (EMsync) generator242, a delay measurement circuit244, a long-H dimming circuit246, an external1H measurement circuit247, and a long-V dimming circuit248. The emission synchronization (EMsync) generator242, the delay measurement circuit244, the long-H dimming circuit246, the external1H measurement circuit247, and the long-V dimming circuit248are collectively configured to control the internal Hsync generator232and the internal Vsync generator236to adjust the internal Hsync signal and the internal Vsync signal (and thereby adjust the display Hsync signal and the display Vsync signal).

The EMsync generator242is configured to generate an emission synchronization signal EMsync using the external Vsync signal and the external Hsync signal. In one implementation, the EMsync generator242is configured to generate the emission synchronization signal EMsync such that the emission synchronization signal is synchronous with the external vertical sync signal and has the same periodicity as the periodicity of the emission pulses, which is determined by the brightness controller250.

The delay measurement circuit244is configured to measure the delay between an assertion of the display Vsync signal and an assertion of the emission synchronization signal. In some embodiments, the delay measurement circuit244is configured to measure the delay from an assertion of the display Vsync signal and a subsequent assertion of the emission synchronization signal. In other embodiments, the delay measurement circuit244is configured to measure the delay from an assertion of the emission synchronization signal to a subsequent assertion of the display Vsync signal.

The long-H dimming circuit246is configured to perform “long-H dimming” based on the delay measured by the delay measurement circuit244. The “long-H dimming” referred herein is a process to synchronize the display Vsync signal with the emission synchronization signal EMsync by adjusting the internal Hsync signal (and thereby adjusting the display Hsync signal). The time interval of two consecutive assertions of the display Vsync signal corresponds to the duration of the frame period (or vertical sync period) defined by the two consecutive assertions while the frame period includes a plurality of line periods (or horizontal sync periods). As the periodicity of the display Hsync signal corresponds to the duration of line periods (or horizontal sync periods), the duration of a frame period is adjustable by adjusting the display Hsync signal. In one implementation, the “long-H dimming” extends a predetermined number of frame periods by adjusting the display Hsync signal to synchronize the display Vsync signal with the synchronization signal EMsync.

The external1H measurement circuit247is configured to measure the periodicity of the external Hsync signal received from the interface circuit205(or the time interval between two consecutive assertions of the external Hsync signal). The internal Hsync generator232is configured to adjust the internal Hsync signal based on the measured periodicity of the external Hsync signal such that the internal Hsync signal has the same periodicity as the external Hsync signal.

The long-V dimming circuit248is configured to perform “long-V dimming” based on the external Vsync signal and the internal Vsync signal. The “long-V dimming” is a process to synchronize the display Vsync signal with the external Vsync signal by adjusting the internal Vsync signal (and thereby adjusting the display Vsync signal). The synchronization of the display Vsync signal with the external Vsync signal is achieved by extending one or more frame periods in increments of the periodicity of emission pulses.

FIG.4shows an example overall operation of the display driver200ofFIG.3in mode switching from the command mode to the video through mode, according to one or more embodiments. In the shown embodiment, the display driver200is initially in the command mode. In the command mode, as shown inFIG.5A, one or more commands that carry image data are transferred from the external source300to the display driver200. It is noted that no external sync control inputs (e.g., Vsync packets and Hsync packets) are provided to the display driver200in the command mode and the display driver200generates the display Vsync signal and the display Hsync signal without using the external sync control inputs (e.g., by using the oscillator clock OSC_CKL generated in the display driver200). The internal Vsync signal and the internal Hsync signal are selected as the display Vsync signal and the display Hsync signal, respectively, in the command mode. The received commands are forwarded to the GRAM216via the selector212and the line buffer214, and the GRAM216stores therein image data carried by the commands. The image data stored in the GRAM216is forwarded to the image processing circuit220via the selector218and processed by the image processing circuit220. The processed image data is forwarded to the data driver224via the line latch222and the display elements112of the display panel100are updated (or programed) by the data driver224based on the processed image data.

Referring back toFIG.4, at step1, the external source300sends a mode switching command that instructs the display driver200to go into the video through mode. The external source300then starts providing video packets and external sync control inputs to the display driver200(also shown inFIG.6A). The video packets carry image data for every frame period and the display driver200updates the display elements112of the display panel100every frame period based on the image data carried by the video packets. The external sync control inputs may include Vsync packets and Hsync packets as discussed in relation toFIG.3.

As shown inFIG.4, the display driver200is configured to go into a “video RAM mode” in response to reception of the mode switching command before going into the video through mode. During the “video RAM mode”, the display driver200uses the GRAM216to provide the image data to the data driver224while adjusting the display Vsync signal to synchronize the display Vsync signal with the external Vsync signal generated based on the external sync control inputs (which may include Vsync packets and/or Hsync packets). The display driver200is further configured to go into the video through mode upon achieving synchronization of the display Vsync signal with the external Vsync signal.

FIG.5Bshows an example operation of the display driver200in the video RAM mode, according to one or more embodiments. In the video RAM mode, the display driver200receives video packets from the external source300. The video packets are forwarded to the GRAM216via the selector212and the line buffer214, and the GRAM216stores therein image data carried by the video packets. The image data stored in the GRAM216is forwarded to the image processing circuit220via the selector218and processed by the image processing circuit220. The processed image data is forwarded to the data driver224via the line latch222and the display elements112of the display panel100are updated (or programed) by the data driver224based on the processed image data.

Referring back toFIG.4, in one or more embodiments, the adjustment of the display Vsync signal during the video RAM mode includes steps2,3and4as discussed in the following. At step2, the delay between an assertion of the display Vsync signal and an assertion of the emission synchronization signal EMsync is measured (e.g., by the delay measurement circuit244shown inFIG.3). It is noted that, inFIG.4(and other figures), the display Vsync signal and the display Hsync signal are shown as being asserted when pulled down to the low level while the emission synchronization signal EMsync is shown as being asserted when pulled up to the high level. As discussed in relation toFIG.3, the emission synchronization signal EMsync is synchronous with the external Vsync signal and has the same periodicity as the periodicity (indicated by EM_PER inFIG.4) of the emission pulses carried by the emission scan start pulse signal ESTV. In the shown embodiment, the delay from an assertion of the display Vsync signal to a subsequent assertion of the emission synchronization signal EMsync is measured.

At step3, the “long-H dimming” process is performed to compensate the delay measured at step2. As discussed in relation toFIG.3, the “long-H dimming” process synchronizes the display Vsync signal with the emission synchronization signal EMsync by adjusting the internal Hsync signal (and thereby adjusting the display Hsync signal). It is noted that the internal Vsync signal and the internal Hsync signal are selected as the display Vsync signal and the display Hsync signal, respectively, during the “long-H dimming” process. In one implementation, the long-H dimming extends one or more frame periods by decreasing the frequency of the internal Hsync signal (or increasing durations of line periods defined by the internal Hsync signal). In embodiments where two or more frame periods are extended by the long-H dimming, the extension amounts assigned to the extended frame periods are determined based on the delay measured at step2. In one implementation, the sum of the extension amounts is equal to the delay from an assertion of the display Vsync signal to a subsequent assertion of the emission synchronization signal EMsync. When the “long-H dimming” process is completed as desired, the timing skew between the display Vsync signal and the external Vsync signal is the same as the periodicity of the emission pulses or a multiple of periodicity of the emission pulses.

At step4, the “long-V dimming” process is performed. As discussed in relation toFIG.3, the “long-V dimming” process synchronizes the display Vsync signal with the external Vsync signal by adjusting the internal Vsync signal to extend one or more frame periods in increments of the periodicity of the emission pulses. It is noted that, during the “long-V dimming” process, the internal Vsync signal is selected as the display Vsync signal while the external Hsync signal is are selected as the display Hsync signal. In some embodiments, a vertical front porch (VFP) period(s) of the one or more frame periods are extended during the “long-V dimming” process. InFIG.4, the extended portion of the vertical front porch period of the extended frame period is indicated by “VFP_EXT.”

At step5, which follows step4, the display driver200goes into the video through mode to complete the mode switching. In the video through mode, the external Vsync signal is selected as the display Vsync signal and the emission scan start pulse signal ESTV, which carries emission pulses, is generated in synchronization with the external Vsync signal.

FIG.5Cshows an example operation of the display driver200in the video through mode, according to one or more embodiments. In the video through mode, the image data carried by the video packets is transferred to the data driver224, bypassing the GRAM216, and the GRAM216is deactivated to reduce power consumption. More specifically, the video packets received from the external source300are forwarded to the image processing circuit220via the selector212, the line buffer214, and the selector218. The image processing circuit220processes the image data carried by the video packets. The processed image data is forwarded to the data driver224via the line latch222and the display elements112of the display panel100are updated (or programed) by the data driver224based on the processed image data.

FIG.6Bshows a detailed example operation of the display driver200after receiving the mode switching command, according to one or more embodiments. In the shown embodiment, the display driver200starts generating the external Vsync signal and the external Hsync signal in response to the external sync control inputs (e.g., Vsync packets and Hsync packets) and further starts generating the emission synchronization signal EMsync. In embodiments where the display driver200is configured as shown inFIG.3, the external Vsync signal and the external Hsync signal are generated by the interface circuit205and the emission synchronization signal EMsync is generated by the EMsync generator242. It is noted however that the display driver200still selects the internal Vsync signal as the display Vsync signal and the internal Hsync signal as the display Hsync signal just after the reception of the mode switching command.

The display driver200further adjusts the internal Hsync signal such that the internal Hsync signal has the same periodicity as the external Hsync signal.FIG.7shows an example adjustment process of the internal Hsync signal, according to one or more embodiments. The adjustment of the internal Hsync signal begins with measuring the periodicity of the external Hsync signal (which is indicated as “External1H” inFIG.7). In embodiments where the display driver200is configured as shown inFIG.3, the external1H measurement circuit247measures the periodicity of the external Hsync signal.

The internal Hsync signal is then adjusted based on the measured periodicity of the external Hsync signal to have the same periodicity as the external Hsync signal. In embodiments where the display driver200is configured as shown inFIG.3, the internal Hsync generator232adjusts the internal Hsync signal based on the measured periodicity of the external Hsync signal. In one implementation, the periodicity of the internal Hsync signal is adjusted with a “dimming” scheme in which the periodicity of the internal Hsync signal is gradually changed to the periodicity of the external Hsync signal. The “dimming” scheme avoids an abrupt change in the periodicity of the internal Hsync signal, mitigating display image artifacts potentially caused by a change in the internal Hsync signal.

Referring back toFIG.6B, after the adjustment of the internal Hsync signal is completed, the delay between an assertion of the display Vsync signal and an assertion of the emission synchronization signal EMsync is measured as discussed in relation toFIG.4. In the shown embodiment, the delay from an assertion of the display Vsync signal to a subsequent assertion of the emission synchronization signal EMsync is measured.

The “long-H dimming” process is then performed to synchronize the display Vsync signal with the emission synchronization signal EMsync by adjusting the internal Hsync signal, which is used to generate the display Hsync signal and the display Vsync signal at this stage. As discussed in relation toFIG.4, the “long-H dimming” process is based on the delay between the assertion of the display Vsync signal and the assertion of the emission synchronization signal EMsync. In one or more embodiments, the “long-H dimming” is achieved by extending one or more frame periods by temporarily increasing the periodicity of the internal Hsync signal (and the periodicity of the display Hsync signal).

In some embodiments, two or more frame periods are extended during the “long-H dimming” process to achieve the synchronization of the display Vsync signal with the emission synchronization signal EMsync. In such embodiments, extension amounts of the two or more frame periods are determined based on the delay between an assertion of the display Vsync signal and a subsequent assertion of the emission synchronization signal EMsync. The extension amount is the amount of time in which the corresponding frame period is extended. In one implementation, the “long-H dimming” process includes assigning extension amounts to the two or more extended frame periods such that the sum of the extension amounts of the extended frame periods is equal to the delay between the assertion of the display Vsync signal to the subsequent assertion of the emission synchronization signal EMsync. Extension amounts that are assigned to frame periods may be referred to as assigned extension amounts.

FIG.8Ashows an example “long-H dimming” process, according to one or more embodiments. In the shown embodiment, four frame periods are extended after the measurement of the delay between an assertion of the display Vsync signal and a subsequent assertion of the emission synchronization signal EMsync. InFIG.8A, “Tbase” indicates a nominal duration of a frame period and “T” indicates the delay between the assertion of the display Vsync signal and the subsequent assertion of the emission synchronization signal EMsync. In the shown embodiment, the nominal duration of a frame period “Tbase”, the delay “T”, and the extension amounts assigned to the extended frame periods are each measured as the number of clocks contained therein, as indicated by the notation “[clk]”. For example, the nominal duration of a frame period is measured as Tbase clocks is indicated as Tbase [clk] inFIG.8A.

FIG.9Ashows an example assignment of extension amounts to the four extended frame periods, according to one or more embodiments. The extension amounts are assigned to the four extended frame periods such that the frame period duration first increases stepwise and then decreases stepwise. More specifically, the extension amount assigned to the second one of the four extended frame periods is longer than the extension amount assigned to the first one of the four extended frame periods while the extension amount assigned to the third one of the four extended frame periods is shorter than the extension amount assigned to the second one of the four extended frame periods. In the shown embodiment, the extension amount assigned to the first one of the four extended frame periods is T×(¼) (more strictly, the integer part of T×(¼)) clocks, the extension amount assigned to the second one is T×( 2/4) clocks, and the extension amount assigned to the third one is T×(¼) clocks. The extension amount assigned to the fourth one of the four extended frame periods is the remainder when T is divided by 4. The extension amount assignment in which the frame period duration first increases stepwise and then decreases stepwise suppresses the change in the frame period duration between two consecutive frame periods, and thereby reduces changes in the periodicity of the display Hsync signal during the “long-H dimming” process. The reduction in the changes in the periodicity of the display Hsync signal may mitigate display image artifacts potentially caused by the changes in periodicity of the display Hsync signal.

The number of extended frame periods during the “long-H dimming” process may be variously modified, not limited to four.FIG.8Bshows another example “long-H dimming” process, according to one or more embodiments. In the shown embodiment, six frame periods are extended after the measurement of the delay between an assertion of the display Vsync signal and a subsequent assertion of the emission synchronization signal EMsync.FIG.9Bshows an example assignment of extension amounts to the six extended frame periods, according to one or more embodiments. The extension amounts are assigned to the six extended frame periods such that the frame period duration first increases stepwise and then decreases stepwise as is the case withFIG.9A. More specifically, the extension amount assigned to the second, third, fourth ones of the six extended frame periods are longer than the first one of the six extended frame periods while the extension amount assigned to the fifth one of the six extended frame periods is shorter than the extension amount to the second, third, and fourth ones of the six extended frame periods. In the shown embodiment, the extension amount assigned to the first one of the six extended frame periods is T×(⅛) (more strictly, the integer part of T×(⅛)) clocks, the extension amount assigned to the second, third, and fourth ones is T×( 2/8) clocks, and the extension amount assigned to the fifth one is T×(⅛) clocks. The extension amount assigned to the sixth one of the six extended frame periods is the remainder when T is divided by 8. Further,FIG.9Cshows an example assignment of extension amounts in embodiments where the number of extended frame periods is eight. Also, in the embodiment shown inFIG.9C, the extension amounts are assigned to the eight extended frame periods such that the frame period duration first increases stepwise and then decreases stepwise.

Referring back toFIG.6B, the “long-H dimming” process is followed by the “long-V dimming” process, which synchronizes the display Vsync signal with the external Vsync signal by adjusting the internal Vsync signal, which is used to generate the display Vsync signal at this stage. It is noted that the display Hsync signal is switched from the internal Hsync signal to the external Hsync signal upon the transition to the “long-V dimming” process. As discussed in relation toFIG.3, the “long-V dimming” process synchronizes the display Vsync signal with the external Vsync signal by adjusting the internal Vsync signal to extend one or more frame periods in increments of the periodicity of the emission pulses. In some embodiments, a vertical front porch (VFP) period(s) of the one or more frame periods are extended during the “long-V dimming” process. InFIG.6B, the extended portion of the vertical front porch period of the extended frame period is indicated by “VFP_EXT.”

FIG.10Ashows an example “long-V dimming” process, according to one or more embodiments. When the “long-H dimming” process is completed as desired, the timing skew between the display Vsync signal and the external Vsync signal is the same as the periodicity of the emission pulses or a multiple of the periodicity of the emission pulses. Accordingly, it is possible to synchronizes the display Vsync signal with the external Vsync signal by extending one or more frame periods in increments of the periodicity of the emission pulses. In the shown embodiment, the timing skew between the display Vsync signal and the external Vsync signal is twice of the periodicity of the emission pulses.

In one or more embodiments, the “long-V dimming” process begins with determining the timing skew between the display Vsync signal and the external Vsync signal. In one implementation, the timing skew between the display Vsync signal and the external Vsync signal may be determined based on a count value of an EMsync counter configured to count assertions of the emission synchronization signal EMsync and a count value of an emission counter configured to count emission pulses carried by the emission scan start pulse signal ESTV. The EMsync counter may be disposed in the EMsync generator242(shown inFIG.3) and configured to be reset upon an assertion of the external Vsync signal and then count up upon each assertion of the emission synchronization signal EMsync. The emission counter may be disposed in the emission pulse generator260(shown inFIG.3) and configured to be reset upon an assertion of the display Vsync signal and then count up upon generation of each emission pulse in the emission scan start pulse signal ESTV. In one implementation, the timing skew between the display Vsync signal and the external Vsync signal is determined as the difference between the count value of the EMsync counter and the count value of the emission counter.

The “long-V dimming” process achieves synchronization of the display Vsync signal with the external Vsync signal in the “long-V dimming” by extending one or more frame periods to compensate the timing skew between the display Vsync signal and the external Vsync signal. When the timing skew is determined as N times of the periodicity of the emission pulses, one or more frame periods are extended such that the total extension amount is N times of the periodicity of the emission pulses. In the embodiment shown inFIG.10A, the timing skew is determined as twice of the periodicity of the emission pulses and a vertical front porch (VFP) period of one frame period is extended by twice of the periodicity of the emission pulses. The extended portion of VFP period is indicated by “VFP_EXT” inFIG.10A.

FIG.10Bshows another example “long-V dimming” process, according to one or more embodiments. In the shown embodiment, the timing skew between the display Vsync signal and the external Vsync signal is also determined as twice of the periodicity of the emission pulses while two frame periods are each extended by the periodicity of the emission pulses. Extending multiple frame periods to compensate the timing skew during the “long-V dimming” process suppresses changes in the frame period duration, mitigating the display image artifacts potentially caused by the changes in the frame period duration.

FIG.11shows an example configuration of a display device2000, according to other embodiments. In the shown embodiment, the display device2000includes two display panels100A and100B, and two display drivers200A and200B. The display device2000is configured to be foldable with the display panels100A and100B coupled with a hinge140. The display panels100A and100B may be each configured identically to the display panel100ofFIG.1. InFIG.11, only the emission scan drivers130A and130B are shown for simplicity. The display driver200A is configured to drive the display panel100A and the display driver200B is configured to drive the display panel100B. The display drivers200A and200B are configured similarly to the display driver200shown inFIG.3except for that the display driver200A is configured to control operation timing of the display driver200B by providing the display Vsync signal and the emission synchronization signal EMsync to the display driver200B. The display driver200B uses the display Vsync signal received from the display driver200A as the external Vsync signal. The display driver200A, which is configured to control the display driver200B, may be hereinafter also referred to as “master driver” while the display driver200B may be hereinafter also referred to as “slave driver.”

In one or more embodiments, the display device2000has two modes: an individual mode and a two panel sync mode. In the individual mode, the display driver200A and200B operate individually to display independent images, which are not related to each other, on the display panels100A and100B. In the two panel sync mode, the display driver200A, which operates as the master driver, provides the display Vsync signal and the emission synchronization signal EMsync to the display driver200B, which operates as the slave driver. The display driver200B uses the display Vsync signal and the emission synchronization signal EMsync received from the display driver200A as external sync control inputs and operates synchronously with the display Vsync signal and the emission synchronization signal EMsync received from the display driver200A to display synchronized images on the display panels100A and100B. Since the display Vsync signal generated in the display driver200A may be asynchronous with the display Vsync signal generated in the display driver200B in the individual mode, mode switching from the individual mode to the two panel sync mode may cause display image artifacts since the mode switching may disturb the periodicity of the display Vsync signal in the display driver200B. A description is given below of embodiments to mitigate display image artifacts potentially caused by the mode switching from the individual mode to the two panel sync mode.

FIG.12shows an example operation of the display device2000ofFIG.11in mode switching from the individual mode to the two panel sync mode, according to one or more embodiments. In the shown embodiment, the display device2000is initially in the individual mode in which the display driver200A and200B operate individually. The display driver200A and200B individually receive commands that encapsulate image data from an external source and update the display panels100A and100B based on the image data encapsulated in the received command.

At step1, an external source (e.g., a host, a controller, a processor, or other devices configured to provide commands) sends a mode switching command to the display driver200A and200B to instruct the display driver200A and200B to go into the two panel sync mode. The display driver200B (which functions as the slave driver) is configured to go into a “transition mode” in response to reception of the mode switching command before going into the two panel sync mode. During the “transition mode”, the display driver200B adjusts the display Vsync signal generated by the display driver200B based on the display Vsync signal and the emission synchronization signal EMsync which are both received from the display driver200A such that the display Vsync signal generated by the display driver200B is synchronized with the display Vsync signal received from the display driver200A.

The adjustment of the display Vsync signal in the display driver200B includes steps2,3and4as discussed in the following. At step2, the display driver200B measures the delay between an assertion of the display Vsync signal generated by the display driver200B and an assertion of the emission synchronization signal EMsync received from the display driver200A. In the shown embodiment, the display driver200B measures the delay from an assertion of the display Vsync signal generated by the display driver200B to a subsequent assertion of the emission synchronization signal EMsync.

At step3, the display driver200B performs a “long-H dimming” process to compensate the delay measured at step2. The “long-H dimming” process synchronizes the display Vsync signal generated by the display driver200B with the emission synchronization signal EMsync received from the display driver200A by adjusting the internal Hsync signal (and the display Hsync signal) generated by the display driver200B. In one implementation, the display driver200B extends one or more frame periods by decreasing the frequency of the internal Hsync signal (or increasing durations of line periods defined by the internal Hsync signal) generated by the display driver200B during the long-H dimming process. In embodiments where two or more frame periods are extended by the long-H dimming, the extension amounts assigned to the extended frame periods are determined based on the delay measured at step2. In one implementation, the sum of the extension amounts is equal to the delay from an assertion of the display Vsync signal generated by the display driver200B to a subsequent assertion of the emission synchronization signal EMsync received from the display driver200A. When the “long-H dimming” is completed as desired, the timing skew between the display Vsync signal generated by the display driver200B and the display Vsync signal received from the display driver200A is the same as the periodicity of the emission pulses or a multiple of periodicity of the emission pulses.

At step4, the display driver200B performs a “long-V dimming” process. The “long-V dimming” process synchronizes the display Vsync signal generated by the display driver200B with the external Vsync signal received from the display driver200A by adjusting the internal Vsync signal generated by the display driver200B to extend one or more frame periods in increments of the periodicity of the emission pulses. In some embodiments, the display driver200B extends a vertical front porch (VFP) period(s) of the one or more frame periods during the “long-V dimming” process. InFIG.12, the extended portion of the vertical front porch period of the extended frame period is indicated by “VFP_EXT.”

At step5, the display driver200B goes into the two panel sync mode to complete the mode transition. In the two panel sync mode, the display driver200B updates the display panel100B in synchronization with the display Vsync signal received from the display driver200A.

Method1300ofFIG.13illustrates example steps for driving a display panel (e.g., the display panels100,100A, and100B ofFIGS.1and11), according to one or more embodiments. It is noted that one or more of the steps shown inFIG.13may be omitted, repeated, and/or performed in a different order. It is further noted that two or more steps may be implemented at the same time.

The method1300includes generating, based at least in part on a display vertical sync (Vsync) signal, emission pulses that control light emission of display elements of a display panel (e.g., the display panel100shown inFIG.1) at step1302. The method1300further includes updating, in a first mode (e.g., the command mode shown inFIGS.4and6Band the individual mode shown inFIG.12), the display elements based at least in part on a command provided to a display driver (e.g., the display driver200shown inFIG.1and the display driver200B shown inFIG.11) asynchronously with the display vertical sync signal at step1304. The method1300further includes switching the display driver from the first mode to a second mode (e.g., the command mode shown inFIGS.4and6Band the individual mode shown inFIG.12) in response to a first command (e.g., the mode switching command shown inFIGS.4,6A,6B, and12) at step1306. The method1300further includes updating, in the second mode, the display elements of the display panel based at least in part on first image data stored in a GRAM (e.g., the GRAM216shown inFIG.3) of the display driver at step1308. The method1300further includes adjusting, in the second mode, the display vertical sync signal based at least in part on an external vertical sync signal at step1310. The method1300further includes switching the display driver to a third mode (e.g., the video through mode shown inFIGS.4and6Band the two panel sync mode shown inFIG.12) after achieving synchronization of the display vertical sync signal with the external vertical sync signal at step1312. The method1300further includes updating, in the third mode, the display elements of the display panel in synchronization with the external vertical sync signal at step1314.

While many embodiments have been described, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope. Accordingly, the scope of the invention should be limited only by the attached claims.