Patent ID: 12224273

DETAILED DESCRIPTION

Embodiments of the present invention will be described below with reference to the drawings.

Note that the drawings are schematic or conceptual, and the relationships between thicknesses and widths of portions, the proportions of sizes between portions, and the like are not necessarily the same as the actual values thereof. Further, the dimensions and the proportions may be illustrated differently between the drawings, even in a case in which the same portion is illustrated.

Note that, in the specification and the drawings, elements similar to those described in relation to a drawing thereinabove are denoted using like reference signs, and a detailed description is omitted as appropriate.

First Embodiment

FIG.1is a schematic cross-sectional view illustrating a portion of an image display device according to an embodiment.

A pixel constituting an image displayed on the image display device is constituted by a plurality of sub-pixels.FIG.1schematically illustrates a configuration of sub-pixels20-1,20-2of the image display device of the present embodiment.

In the following, description is sometimes made using a three-dimensional coordinate system of XYZ. The sub-pixels20-1,20-2are arrayed on a two-dimensional plane along with other sub-pixels. The two-dimensional plane in which the sub-pixels20-1,20-2are arrayed is defined as an XY plane. A plurality of sub-pixels including the sub-pixels20-1,20-2are arrayed in an X-axis direction and a Y-axis direction.

FIG.1schematically illustrates a cross section when the sub-pixels20-1,20-2are cut at a plane parallel to the XZ plane.

The sub-pixel20-1includes a light-emitting surface151S1substantially parallel to the XY plane. The sub-pixel20-2includes a light-emitting surface151S2substantially parallel to the XY plane. These light-emitting surfaces151S1,151S2emit light mainly in a positive direction of a Z axis orthogonal to the XY plane.

As illustrated inFIG.1, the sub-pixel20-1of the image display device of the present embodiment includes a transistor103-1, a light-emitting element150-1, and a plug116a1. The sub-pixel20-2includes a transistor103-2, a light-emitting element150-2, and a plug116a2. The sub-pixels20-1,20-2include a substrate102, a first wiring layer110, a first interlayer insulating film112, a second interlayer insulating film156, and a second wiring layer159. In the plurality of sub-pixels including the sub-pixels20-1,20-2, the substrate102, the first wiring layer110, the second wiring layer159, the first interlayer insulating film112, and the second interlayer insulating film156are shared.

In the present embodiment, the substrate102on which circuit elements including the transistors103-1,103-2are formed is a light-transmitting substrate, and is, for example, a glass substrate. The substrate102includes a first surface102a, and the transistors103-1,103-2are formed on the first surface102a. The transistors103-1,103-2are, for example, thin film transistors (TFTs). The light-emitting elements150-1,150-2are driven by such TFTs formed on the glass substrate. The process of forming circuit elements including the TFT on a large glass substrate is established for the manufacture of a liquid crystal panel, an organic electroluminescent (EL) panel, and the like, resulting in the advantage that an existing plant can be utilized.

The sub-pixels20-1,20-2further include a color filter180. The color filter180is shared by the plurality of sub-pixels including the sub-pixels20-1,20-2. The color filter (wavelength conversion member)180is provided on a surface resin layer170with a transparent thin film adhesive layer188interposed therebetween. The surface resin layer170is provided on the second interlayer insulating film156and the second wiring layer159.

A configuration of the sub-pixels20-1,20-2of the image display device of the present embodiment will now be described in detail.

The transistors103-1,103-2are formed on a TFT lower layer film106formed on the first surface102aof the substrate102. The TFT lower layer film106is provided to ensure flatness when the transistors103-1,103-2are formed, and to protect TFT channels104-1,104-2of the transistors103-1,103-2, respectively, from contamination and the like during heat treatment. The TFT lower layer film106is an insulating film such as SiO2, for example.

In addition to the transistors103-1,103-2for driving the light-emitting elements150-1,150-2, other circuit elements such as a transistor and a capacitor are formed on the substrate102, and these circuit elements are connected by wiring portions and the like, forming a circuit101. For example, the transistors103-1,103-2correspond to a drive transistor26illustrated inFIG.2described below.

Hereinafter, the circuit101is a circuit that includes the TFT channels104-1,104-2, an insulating layer105, an insulating film108, vias111s1,111s2,111d1,111d2, and the first wiring layer110. The structure including the substrate102, the TFT lower layer film106, the circuit101, and the first interlayer insulating film112may be referred to as a circuit substrate100.

The transistors103-1,103-2are p-channel TFTs in this example. The transistor103-1includes the TFT channel104-1and a gate107-1. The transistor103-2includes the TFT channel104-2and a gate107-2. The transistors103-1,103-2are preferably formed by a low temperature polysilicon (LTPS) process. The TFT channels104-1,104-2are regions of polycrystalline Si formed on the substrate102. The TFT channels104-1,104-2are polycrystallized and activated by annealing regions formed as amorphous Si by laser irradiation. The TFTs are formed in an LTPS process to achieve a sufficiently high mobility.

The TFT channel104-1includes regions104s1,104i1,104d1. The TFT channel104-2includes regions104s2,104i2,104d2. The regions104s1,104i1,104d1and the regions104s2,104i2,104d2are all provided on the TFT lower layer film106. The region104i1is provided between the regions104s1,104d1. The region104i2is provided between the regions104s2,104d2. The regions104s1,104d1and the regions104s2,104d2are doped with a p-type impurity such as boron ions (B+) or boron fluoride ions (BF2+). The regions104s1,104d1are respectively ohmic connected to the vias111s1,111d1. The regions104s2,104d2are respectively ohmic connected to the vias111s2,111d2.

The gate107-1is provided on the TFT channel104-1with the insulating layer105interposed therebetween. The gate107-2is provided on the TFT channel104-2with the insulating layer105interposed therebetween. The insulating layer105insulates the TFT channel104-1and the gate107-1, and insulates the TFT channel104-2and the gate107-2. The insulating layer105is also provided for insulating the area between adjacent circuit elements.

In the transistor103-1, when a voltage lower than that of region104s1is applied to the gate107-1, a channel may be formed in the region104i1. A current flowing between the region104s1and the region104d1is controlled by the voltage across the region104s1of the gate107-1. Similarly, in the transistor103-2, when a voltage lower than that of region104s2is applied to the gate107-2, a channel may be formed in the region104i2. Therefore, a current flowing between the region104s2and the region104d2is controlled by the voltage across the region104s2of the gate107-2.

The insulating layer105is, for example, SiO2. The insulating layer105may be a multi-layer insulating layer including SiO2, Si3N4, or the like in accordance with the covered region.

The gates107-1,107-2are, for example, polycrystalline Si. The polycrystalline Si film of the gates107-1,107-2can be generally created by a chemical vapor deposition (CVD) process.

In this example, the gates107-1,107-2and the insulating layer105are covered by the insulating film108. The insulating film108is, for example, SiO2or Si3N4. The insulating film108functions as a flattening film for forming the first wiring layer110. The insulating film108is a multi-layer insulating film containing SiO2or Si3N4, for example.

The vias111s1,111d1are provided through the insulating film108. The vias111s2,111d2are provided through the insulating film108. The first wiring layer (first wiring layer)110is formed on the insulating film108. The first wiring layer110includes a plurality of wiring portions that can differ in potential, and includes wiring portions110s1,110d1and wiring portions110s2,110d2. In the wiring layer in the cross-sectional views ofFIG.1and subsequent drawings, the reference sign of the wiring layer is displayed at a position lateral to one wiring portion included in the denoted wiring layer.

The via111s1is provided between the wiring portion110s1and the region104s1. The via111s1electrically connects the wiring portion110s1and the region104s1. The via111d1is provided between the wiring portion110d1and the region104d1. The via111d1electrically connects the wiring portion110d1and the region104d1. The via111s2is provided between the wiring portion110s2and the region104s2. The via111s2electrically connects the wiring portion110s2and the region104s2. The via111d2is provided between the wiring portion110d2and the region104d2. The via111d2electrically connects the wiring portion110d2and the region104d2.

The wiring portions110s1,110s2are electrically connected to a power source line3illustrated inFIG.2described below. Accordingly, the region104s1is electrically connected to the power source line3via the wiring portion110s1, and the region104s2is electrically connected to the power source line3via the wiring portion110s2. The wiring portion (first wiring portion)110d1is electrically connected to a p-type semiconductor layer153-1of the light-emitting element150-1via a connecting portion115a1, the plug116a1, and a conductive thin film117a1. The wiring portion (second wiring portion)110d2is electrically connected to a p-type semiconductor layer153-2of the light-emitting element150-2via a connecting portion115a2, the plug116a2, and a conductive thin film117a2.

The first wiring layer110, the vias111s1,111d1, and the vias111s2,111d2are formed of Al, an Al alloy, or a layered film of Al and Ti or the like, for example. In a layered film of Al and Ti, for example, Al is layered on a thin film of Ti, and Ti is further layered on Al.

The first interlayer insulating film112is provided on the insulating film108and the first wiring layer110, and is provided on a lateral surface of the connecting portions115a1,115a2. The first interlayer insulating film (first insulating film)112is an organic insulating film such as phosphorus silicon glass (PSG) or boron phosphorus silicon glass (BPSG), for example. The first interlayer insulating film112is provided to achieve uniform bonding in wafer bonding. The first interlayer insulating film112also functions as a protective film that protects a front surface of the circuit substrate100.

The wiring layer (third wiring layer)116is provided on the first interlayer insulating film112. The wiring layer116includes the plugs116a1,116a2and a wiring portion116k. In this example, the conductive thin film117a1is provided over the plug116a1. The conductive thin film117a2is provided over the plug116a2. A conductive thin film117kis provided over the wiring portion116k.

The plug (first plug)116a1is connected to the wiring portion110d1via the connecting portion115a1. The plug (second plug)116a2is connected to the wiring portion110d2via the connecting portion115a2. The wiring portion (third wiring portion)116kis connected to a ground line4inFIG.2described below, for example.

The wiring layer116is formed of a metal material similar to that of the first wiring layer110, the via111s1, and the like, for example. The conductive thin films117a1,117a2,117kare preferably conductive films having hole injection properties such as an indium tin oxide (ITO) film.

The light-emitting element150-1is provided on the conductive thin film117a1. The light-emitting element150-2is provided on the conductive thin film117a2.

The light-emitting element150-1includes the p-type semiconductor layer (first semiconductor layer)153-1, a light-emitting layer152-1, and an n-type semiconductor layer (second semiconductor layer)151-1. The p-type semiconductor layer153-1, the light-emitting layer152-1, and the n-type semiconductor layer151-1are layered in this order from the side of the conductive thin film117a1toward the side of the light-emitting surface151S1.

The light-emitting element150-2includes the p-type semiconductor layer153-2, a light-emitting layer152-2, and an n-type semiconductor layer151-2. The p-type semiconductor layer153-2, the light-emitting layer152-2, and the n-type semiconductor layer151-2are layered in this order from the side of the conductive thin film117a2toward the side of the light-emitting surface151S2.

The light-emitting element150-1is provided on the conductive thin film117a1, and thus the conductive thin film117a1is electrically connected to the p-type semiconductor layer153-1. The light-emitting element150-2is provided on the conductive thin film117a2, and thus the conductive thin film117a2is electrically connected to the p-type semiconductor layer153-2. In the case of the conductive thin films117a1,117a2being conductive films having hole injection properties, the light-emitting elements150-1,150-2can be driven at a lower voltage.

The light-emitting elements150-1,150-2have substantially square or rectangular shapes in an XY plane view, for example, but a corner portion may be rounded. The light-emitting elements150-1,150-2may have, for example, an elliptical shape or a circular shape in an XY plane view. With appropriate selection of the shape, the arrangement, and the like of the light-emitting element in plan view, a degree of freedom of the layout is improved.

As the light-emitting elements150-1,150-2, a gallium nitride compound semiconductor including a light-emitting layer such as InXAlYGa1-X-YN (where 0≤X, 0≤Y, X+Y<1), for example, is preferably used. Hereinafter, the gallium nitride compound semiconductor described above may be simply referred to as gallium nitride (GaN). The light-emitting elements150-1,150-2in one embodiment of the present invention are so-called light-emitting diodes, and a wavelength of light emitted by the light-emitting elements150-1,150-2is about 467 nm±20 nm, for example. The wavelength of light emitted by the light-emitting elements150-1,150-2may be a blue violet emission of about 410 nm±20 nm. The wavelength of the light emitted by the light-emitting element150is not limited to the values described above and may be an appropriate value.

An area of the light-emitting element in an XY plane view is set in accordance with the light emission colors of red, green, and blue sub-pixels. The areas of the light-emitting elements150-1,150-2in an XY plane view are set as appropriate according to visibility, a conversion efficiency of a color conversion unit182of the color filter180, and the like. In this example, the areas of the two light-emitting elements150-1,150-2in an XY plane view are the same. The light-emitting elements150-1,150-2are respectively mounted on the conductive thin films117a1,117a2, each having a surface substantially parallel to the XY plane, and thus the areas of the light-emitting elements150-1,150-2in an XY plane view are the areas of the regions surrounded by outer peripheries of the light-emitting elements150-1,150-2projected onto the XY plane.

The outer periphery of the light-emitting element150-1is located within an outer periphery of the plug116a1when the light-emitting element150-1is projected onto the plug116a1in an XY plane view.

Similarly, the outer periphery of the light-emitting element150-2is located within an outer periphery of the plug116a2when the light-emitting element150-2is projected onto the plug116a2in an XY plane view.

Preferably, the plugs116a1,116a2are formed of a metal material having light reflectivity, and the conductive thin films117a1,117a2have light transmittance. Therefore, the plug116a1functions as a light-reflecting plate that reflects light scattering downward of the light-emitting element150-1toward the light-emitting surface151S1side. Further, the plug116a2functions as a light-reflecting plate that reflects light scattering downward of the light-emitting element150-2toward the light-emitting surface151S2side. By appropriately selecting the material of the plugs116a1,116a2, the scattering of light downward of the light-emitting elements150-1,150-2can be reflected toward the light-emitting surface151S1,151S2side, and thus improving a light emission efficiency.

The plug116a1reflects the scattering of light downward of the light-emitting element150-1toward the light-emitting surface151S1side, making it possible to ensure that the scattering light does not reach the transistor103-1. Similarly, the plug116a2reflects the scattering of light downward of the light-emitting element150-2toward the light-emitting surface151S2side, making it possible to ensure that the scattering light does not reach the transistor103-2. The plugs116a1,116a2block light scattering downward of the light-emitting elements150-1,150-2, thereby inhibiting the light from reaching the transistors103-1,103-2and making it possible to prevent malfunction of the transistors103-1,103-2.

The second interlayer insulating film156covers the first interlayer insulating film112, the plugs116a1,116a2, the wiring portion116k, the conductive thin films117a1,117a2,117k, and the light-emitting elements150-1,150-2. The second interlayer insulating film156, by covering the light-emitting elements150-1,150-2, the plugs116a1,116a2, the wiring portion116k, and the like, protects these from a surrounding environment, such as dust and humidity, and the like. The second interlayer insulating film156, by covering the light-emitting elements150-1,150-2, the plugs116a1,116a2, the wiring portion116k, and the like, insulates these from other conductors. A front surface of the second interlayer insulating film156need only be flat enough to allow formation of the second wiring layer159on the second interlayer insulating film156.

The organic insulating material used for the second interlayer insulating film156is preferably a white resin. The second interlayer insulating film156that is a white resin can reflect the laterally emitted light of the light-emitting elements150-1,150-2and the return light caused by the interface of the color filter180and the like, and substantially improve the light emission efficiency of the light-emitting elements150-1,150-2.

The white resin is formed by dispersing scattering microparticles having a Mie scattering effect on a transparent resin such as a silicon-based resin such as spin-on glass (SOG) or a novolac phenolic resin. The microparticles are colorless or white, and have a diameter of about one-tenth to several times the wavelength of the light emitted by the light-emitting elements150-1,150-2. Microparticles having a diameter of about one-half the wavelength of the light are suitably used as the scattering microparticles. Examples of such scattering microparticles include TiO2, Al2SO3, and ZnO. Alternatively, the white resin can also be formed by utilizing a number of fine pores or the like dispersed within a transparent resin. The second interlayer insulating film156may be whitened by using a SiO2film or the like formed by atomic layer deposition (ALD) or CVD, for example, instead of SOG or the like.

The second interlayer insulating film156may be a black resin. With the second interlayer insulating film156being a black resin, the scattering of light within the sub-pixels20-1,20-2is suppressed, and stray light is more effectively suppressed. An image display device in which stray light is suppressed can display a sharper image.

An opening158-1is formed at a position corresponding to the light-emitting element150-1of the second interlayer insulating film156. The light-emitting surface151S1is exposed from the second interlayer insulating film156through the opening158-1. An opening158-2is formed at a position corresponding to the light-emitting element150-2of the second interlayer insulating film156. The light-emitting surface151S2is exposed from the second interlayer insulating film156through the opening158-2. The light-emitting surfaces151S1,151S2exposed from the openings158-1,158-2are roughened. In a case in which the light-emitting surfaces151S1,151S2are roughened, the light emission efficiency of the light-emitting elements150-1,150-2is improved.

An opening162is formed at a position corresponding to the wiring portion116kof the second interlayer insulating film156. The conductive thin film117kformed over the wiring portion116kis exposed from the second interlayer insulating film156through the opening162.

The second wiring layer159is provided on the second interlayer insulating film156. The second wiring layer159includes a light-transmitting electrode159k. The light-transmitting electrode159kis connected to the conductive thin film117kvia the opening162. The light-transmitting electrode159kis connected to the light-emitting surface151S1via the opening158-1. The light-transmitting electrode159kis connected to the light-emitting surface151S2via the opening158-2. The light-transmitting electrode159kis provided across the openings162,158-1,158-2and electrically connects the conductive thin film117kand the n-type semiconductor layers151-1,151-2. The second wiring layer159is formed by a light-transmitting conductive film and is formed by an ITO film, for example.

The wiring portion116kand the conductive thin film117kare connected to the ground line4illustrated inFIG.2described below, for example. Accordingly, the n-type semiconductor layers151-1,151-2of the light-emitting elements150-1,150-2are electrically connected to the ground line4via the light-transmitting electrode159k, the conductive thin film117k, and the wiring portion116k.

The p-type semiconductor layer153-1of the light-emitting element150-1is electrically connected to the region104d1via the conductive thin film117a1, the plug116a1, the connecting portion115a1, the wiring portion110d1, and the via111d1. The region104d1corresponds to a drain electrode of transistor103-1. The region104s1is electrically connected to the power source line3illustrated inFIG.2by the via111s1and wiring portion110s1. The region104s1corresponds to a source electrode of the transistor103-1.

The p-type semiconductor layer153-2of the light-emitting element150-2is electrically connected to the region104d2via the conductive thin film117a2, the plug116a2, the connecting portion115a2, the wiring portion110d2, and the via111d2. The region104d2corresponds to a drain electrode of transistor103-2. The region104s2is electrically connected to the power source line3illustrated inFIG.2by the via111s2and wiring portion110s2. The region104s2corresponds to a source electrode of transistor103-2.

The surface resin layer170covers the second interlayer insulating film156and the second wiring layer159. The surface resin layer170is a transparent resin and provides a flat surface for protecting the second interlayer insulating film156and the second wiring layer159, and for adhering the color filter180.

The color filter180includes a light-blocking portion181and the color conversion unit182. The color conversion unit182is provided directly above the light-emitting surfaces151S1,151S2of the light-emitting element150in accordance with the shapes of the light-emitting surfaces151S1,151S2. In the color filter180, a portion other than the color conversion unit182is the light-blocking portion181. The light-blocking portion181is a so-called black matrix, and can reduce bleeding caused by the color mixing of light emitted from the adjacent color conversion unit182and the like, and thus display a sharp image.

The color conversion unit182is one layer or two or more layers. InFIG.1, a case in which the color conversion unit182is two layers is illustrated. Whether the color conversion unit182is one layer or two layers is determined by the color, that is, the wavelength, of the light emitted by the sub-pixel20. In a case in which the light emission color of the sub-pixel20is red or green, the color conversion unit182is preferably the two layers of a color conversion layer183and a filter layer184through which red light or green light passes, which are described below. In a case in which the light emission color of the sub-pixel20is blue, one layer is preferred.

In a case in which the color conversion unit182is two layers, a first layer closer to the light-emitting element150is the color conversion layer183, and a second layer is the filter layer184. That is, the filter layer184is layered on the color conversion layer183.

The color conversion layer183is a layer that converts the wavelength of the light emitted by the light-emitting element150to a desired wavelength. In a case in which the sub-pixel20emits red light, the color conversion layer183converts light of 467 nm±20 nm, which is the wavelength of the light-emitting element150, to light having a wavelength of about 630 nm±20 nm, for example. In a case in which the sub-pixel20emits green light, the color conversion layer183converts light of 467 nm±20 nm, which is the wavelength of the light-emitting element150, to light having a wavelength of about 532 nm±20 nm, for example.

The filter layer184blocks the wavelength component of the remaining blue light emission without color conversion by the color conversion layer183.

In a case in which the color of the light emitted by the sub-pixel20is blue, the sub-pixel20may output the light via the color conversion layer183or may output the light as is and not via the color conversion layer183. In a case in which the wavelength of the light emitted by the light-emitting element150is about 467 nm±20 nm, the sub-pixel20may output the light not via the color conversion layer183. In a case in which the wavelength of the light emitted by the light-emitting element150is set to 410 nm±20 nm, it is preferable to provide the one layer of the color conversion layer183in order to convert the wavelength of the light to be output to about 467 nm±20 nm.

Even in the case of the sub-pixel20having a blue color, the sub-pixel20may include the filter layer184. With the filter layer184through which blue light is transmitted provided to the blue sub-pixel20, minute reflection of external light other than the blue light generated at a front surface of the light-emitting element150is suppressed.

FIG.2is a schematic block diagram illustrating an image display device according to the present embodiment.

As illustrated inFIG.2, an image display device1according to the present embodiment includes a display region2. The sub-pixels20are arrayed in the display region2. The sub-pixels20are arrayed, for example, in a lattice pattern. For example, n sub-pixels20are arrayed along the X axis, and m sub-pixels20are arrayed along the Y axis.

A pixel10includes a plurality of the sub-pixels20that emit different colors of light. A sub-pixel20R emits red light. A sub-pixel20G emits green light. A sub-pixel20B emits blue light. The three types of sub-pixels20R,20G,20B emit light at a desired brightness, and thus the light emission color and brightness of one pixel10are determined.

One pixel10includes the three sub-pixels20R,20G,20B, and the sub-pixels20R,20G,20B are arrayed in a linear shape on the X axis, for example, as in the example illustrated inFIG.2. In each pixel10, sub-pixels of the same color may be arrayed in the same column or, as in this example, sub-pixels of different colors may be arrayed on a per column basis.

The image display device1further includes the power source line3and the ground line4. The power source line3and the ground line4are wired in a lattice pattern along the array of the sub-pixels20. The power source line3and the ground line4are electrically connected to each sub-pixel20, and power is supplied to each sub-pixel20from a direct current power source connected between a power source terminal3aand a ground (GND) terminal4a. The power source terminal3aand the GND terminal4aare respectively provided at end portions of the power source line3and the ground line4, and are connected to a direct current power source circuit provided outside the display region2. A positive voltage is supplied to the power source terminal3abased on the GND terminal4a.

The image display device1further includes a scanning line6and a signal line8. The scanning line6is wired in a direction parallel to the X axis. That is, the scanning line6is wired along the array of the sub-pixels20in a row direction. The signal line8is wired in a direction parallel to the Y axis. That is, the signal line8is wired along the array of the sub-pixels20in a column direction.

The image display device1further includes a row selection circuit5and a signal voltage output circuit7. The row selection circuit5and the signal voltage output circuit7are provided along an outer edge of the display region2. The row selection circuit5is provided in the Y-axis direction of the outer edge of the display region2. The row selection circuit5is electrically connected to the sub-pixel20of each column via the scanning line6, and supplies a selection signal to each sub-pixel20.

The signal voltage output circuit7is provided in the X-axis direction of the outer edge of the display region2. The signal voltage output circuit7is electrically connected to the sub-pixel20of each row via the signal line8, and supplies a signal voltage to each sub-pixel20.

The sub-pixel20includes a light-emitting element22, a selection transistor24, the drive transistor26, and a capacitor28. InFIG.2, the selection transistor24may be denoted as T1, the drive transistor26may be denoted as T2, and the capacitor28may be denoted as Cm.

The light-emitting element22is connected in series with the drive transistor26. In the present embodiment, the drive transistor26is a p-channel TFT, and an anode electrode of the light-emitting element22connected to the p-type semiconductor layer is connected to a drain electrode that is a main electrode of the drive transistor26. The series circuit of the light-emitting element22and the drive transistor26is connected between the power source line3and the ground line4. The drive transistor26corresponds to the transistors103-1,103-2inFIG.1, and the light-emitting element22corresponds to the light-emitting elements150-1,150-2inFIG.1. The current flowing to the light-emitting element22is determined by the voltage applied across the gate-source of the drive transistor26, and the light-emitting element22emits light at a brightness corresponding to the flowing current.

The selection transistor24is connected between a gate electrode of the drive transistor26and the signal line8via the main electrode. A gate electrode of the selection transistor24is connected to the scanning line6. The capacitor28is connected between the gate electrode of the drive transistor26and the power source line3.

The row selection circuit5selects one row from the array of m rows of the sub-pixels20to supply a selection signal to the scanning line6. The signal voltage output circuit7supplies a signal voltage having the required analog voltage value to each sub-pixel20in the selected row. The signal voltage is applied across the gate-source of the drive transistor26of the sub-pixels20of the select row. The signal voltage is held by the capacitor28. The drive transistor26introduces a current corresponding to the signal voltage to the light-emitting element22. The light-emitting element22emits light at a brightness corresponding to the current flowing in the light-emitting element22.

The row selection circuit5supplies the selection signal by sequentially switching the selected row. That is, the row selection circuit5scans the rows in which the sub-pixels20are arrayed. A current corresponding to the signal voltage flows in the light-emitting element22of the sub-pixels20sequentially scanned, and light is emitted. Each pixel10emits light of the light emission color and brightness determined by the light emission color and the brightness emitted by the sub-pixels20of each RGB color, and an image is displayed in the display region2.

A manufacturing method of the image display device1according to the present embodiment will now be described.

FIGS.3A to8Bare schematic cross-sectional views illustrating the manufacturing method of the image display device according to the present embodiment.

As illustrated inFIG.3A, in the manufacturing method of the image display device1of the present embodiment, at least one semiconductor growth substrate is prepared. In this example, a plurality of the semiconductor growth substrates (second substrates)1194-1,1194-2are prepared. The semiconductor growth substrates1194-1,1194-2each include a semiconductor layer1150formed on a crystal growth substrate (first substrate)1001. The crystal growth substrate1001is a Si substrate or a sapphire substrate, for example. Preferably, a Si substrate is used.

The semiconductor layer1150includes an n-type semiconductor layer1151, a light-emitting layer1152, and a p-type semiconductor layer1153. The n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153are layered in the order of the n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153from the crystal growth substrate1001side. For formation of the semiconductor layer1150, a chemical vapor deposition (CVD) method, for example, is used, and metal-organic chemical vapor deposition (MOCVD) method is suitably used. The semiconductor layer1150is, for example, InXAlYGa1-X-YN (0≤X, 0≤Y, and X+Y<1).

In the early stage of crystal growth, crystal defects may occur due to inconsistency of crystal lattice constants, and a crystal with a crystal defect exhibits an n-shape. Therefore, as in this example, in a case in which layering is from the n-type semiconductor layer1151to the crystal growth substrate1001, a margin in terms of the production process is increased, resulting in the advantage that yield is readily improved.

A metal layer (second metal layer)1130is formed on each of the semiconductor growth substrates1194-1,1194-2on which the semiconductor layer1150is formed. The metal layer1130is formed on the p-type semiconductor layer1153. A surface of the p-type semiconductor layer1153on which the metal layer1130is formed is a surface facing the surface on which the light-emitting layer1152is provided. In a case in which the metal layer1130is formed on the surface of the p-type semiconductor layer1153, the p-type semiconductor layer1153can be protected by the metal layer1130, which has the advantage that the semiconductor growth substrate1194is readily retained.

Preferably, a conductive layer1170is formed on the p-type semiconductor layer1153before formation of the metal layer1130. The conductive layer1170is formed between the metal layer1130and the p-type semiconductor layer1153. The conductive layer1170is a layer of a conductive layer or conductive thin film having hole injection properties, such as an ITO film.

As illustrated inFIG.3B, a circuit substrate1100is prepared. The circuit substrate (third substrate)1100includes the circuit101described inFIG.1and the like. Contact holes h1, h2are respectively formed at positions corresponding to the wiring portions110d1,110d2on the first interlayer insulating film112of the circuit substrate1100. The contact holes h1, h2have depths that reach the wiring portions110d1,110d2. The contact holes h1, h2may be formed deeper by overetching the wiring portions110d1,110d2.

As illustrated inFIG.4A, a metal layer (first metal layer)1160is formed on the first interlayer insulating film112. When the metal layer1160is formed, the material forming the metal layer1160is embedded in the contact holes h1, h2, and the connecting portions115a1,115a2are formed.

As illustrated inFIG.4B, the semiconductor growth substrates1194-1,1194-2are inverted upside down and bonded to the circuit substrate1100on which the metal layer1160is formed. More specifically, bonding surfaces of the semiconductor growth substrates1194-1,1194-2are exposed surfaces of the metal layer1130. A bonding surface of the circuit substrate1100is an exposed surface of the metal layer1160. These surfaces face each other and are bonded together.

In this example, the plurality of semiconductor growth substrates1194-1,1194-2are adhered to one circuit substrate1100. A position X1is a position at which respective end portions of the semiconductor growth substrates1194-1,1194-2are disposed in a case in which the semiconductor growth substrates1194-1,1194-2are disposed adjacent to each other. As will be described in detail below, in the circuit substrate1100, the light-emitting elements150-1,150-2are not formed in a predetermined region including the position X1.

In the process of wafer bonding, for example, each of the substrates are heated and then bonded together by thermal compression bonding. When thermal compression bonding is performed, a low melting point metal or a low melting point alloy may be used. The low melting point metal is, for example, Sn or In, and the low melting point metal can be, for example, an alloy having Zn, In, Ga, Sn, Bi, or the like as a main component.

In wafer bonding, in addition to the above, the bonding surface of each substrate may be flattened using chemical mechanical polishing (CMP) or the like, and the bonding surfaces may be cleaned by a plasma treatment in a vacuum and brought into close contact.

Two modified examples in relation to the wafer bonding process are illustrated inFIG.5AtoFIG.6B. In the wafer bonding process, the processes ofFIG.5AtoFIG.5Ccan be used instead of the processes ofFIGS.3A and4B. Further, the processes ofFIGS.6A and6Bmay be used instead of the processes ofFIGS.3A and4B.

InFIGS.5A to5C, after formation of the semiconductor layer1150on the crystal growth substrate1001, the semiconductor layer1150is transferred to a support substrate1190different from the crystal growth substrate1001.

As illustrated inFIG.5A, semiconductor growth substrates1294-1,1294-2are prepared. The semiconductor growth substrates1294-1,1294-2each include the semiconductor layer1150. The semiconductor layer1150includes the p-type semiconductor layer1153, the light-emitting layer1152, and the n-type semiconductor layer1151. The p-type semiconductor layer1153, the light-emitting layer1152, and the n-type semiconductor layer1151are layered on the crystal growth substrate1001in the order of the p-type semiconductor layer1153, the light-emitting layer1152, and the n-type semiconductor layer1151from the side of the crystal growth substrate1001.

As illustrated inFIG.5B, after the semiconductor layer1150is formed on the crystal growth substrate1001, the support substrate1190is adhered to the exposed surface of the n-type semiconductor layer1151. The support substrate1190is formed of, for example, Si or quartz. After the support substrate1190is adhered to the semiconductor layer1150, the crystal growth substrate1001is removed. To remove the crystal growth substrate1001, wet etching or laser lift-off, for example, is used.

As illustrated inFIG.5C, the metal layer1130is formed on the exposed surface of the p-type semiconductor layer1153. As illustrated inFIG.4A, the circuit substrate1100on which the metal layer1160is formed is prepared. The metal layer1130faces the metal layer1160, and the metal layers1130,1160are bonded together. Subsequently, the support substrate1190is removed by laser lift-off or the like.

In the example illustrated inFIGS.6A and6B, a buffer layer1140is provided on the crystal growth substrate1001, and then the semiconductor layer1150is formed on the buffer layer1140.

As illustrated inFIG.6A, semiconductor growth substrates1194a-1,1194a-2are prepared. The semiconductor growth substrates1194a-1,1194a-2each include the buffer layer1140and the semiconductor layer1150. The buffer layer1140is formed on one surface of the crystal growth substrate1001. The semiconductor layer1150is formed on the crystal growth substrate1001with the buffer layer1140interposed therebetween. As the buffer layer1140, a nitride such as AlN is suitably used. By crystal growth of the semiconductor layer1150with the buffer layer1140interposed therebetween, mismatch at the interface between the GaN crystal and the crystal growth substrate1001can be mitigated.

The semiconductor layer1150includes the n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153. The n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153are layered on the crystal growth substrate1001in the order of the n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153from the crystal growth substrate1001side.

On the prepared semiconductor growth substrates1194a-1,1194a-2, the metal layer1130is formed on the exposed surface of the p-type semiconductor layer1153. As illustrated inFIG.3A, the conductive layer1170is formed between the metal layer1130and the p-type semiconductor layer1153.

As illustrated inFIG.6B, the circuit substrate1100on which the metal layer1160is formed is prepared. The exposed surface of the metal layer1130faces the exposed surface of the metal layer1160, and the metal layers1130,1160are bonded together.

In this example, the buffer layer1140remains on the n-type semiconductor layer1151after removal of the crystal growth substrate1001, and thus the buffer layer1140is removed in any subsequent process. The process of removing the buffer layer1140may be performed after the process of forming the light-emitting element, or may be performed before formation of the light-emitting element, for example. To remove the buffer layer1140, wet etching, for example, is used.

The description of the manufacturing process after wafer bonding will now continue.

As illustrated inFIG.7A, the crystal growth substrate1001is removed by wet etching, laser lift-off, or the like. The bonded metal layers1130,1160form a metal layer1160a.

As illustrated inFIG.7B, the semiconductor layer1150illustrated inFIG.7Ais molded into a desired shape by etching, forming the light-emitting elements150-1,150-2. For the formation of the light-emitting elements150-1,150-2, a dry etching process, for example, is used, and anisotropic ion etching (reactive ion etching (RIE)) is suitably used. Subsequently, the bonded metal layer1160aillustrated inFIG.7Ais etched to form the wiring layer (third wiring layer)116. The wiring layer116includes the plugs116a1,116a2and the wiring portion116k. The conductive layer1170illustrated inFIG.7Ais also etched simultaneously with the metal layer1160aand is molded into the conductive thin films117a1,117a2,117k. The conductive thin film117a1covers the plug116a1, and the conductive thin film117a2covers the plug116a2. The conductive thin film117kcovers the wiring portion116k.

The outer periphery of the plug116a1is molded so that the outer periphery of the light-emitting element150-1projected onto the plug116a1is located within the outer periphery of the plug116a1in an XY plane view. The outer periphery of the plug116a2is molded so that the outer periphery of the light-emitting element150-2projected onto the plug116a2is located within the outer periphery of the plug116a2in an XY plane view.

The light-emitting elements150-1,150-2are formed at positions sufficiently distant from the position X1. The position X1is a position corresponding to the end portions of the semiconductor layer1150illustrated inFIG.4B, and the crystal quality of the semiconductor layer1150readily deteriorates at and near the position corresponding to the position X1. Therefore, on the positive direction side of the X axis from the position X1, the light-emitting elements150-1,150-2are formed at positions sufficiently distant from the end portion. On the negative direction side of the X axis from the position X1, in this example, no other circuit elements are formed, including the light-emitting elements, and the wiring portion116kis formed.

The second interlayer insulating film156is formed covering the first interlayer insulating film112, the plugs116a1,116a2, the wiring portion116k, the conductive thin films,117a1,117a2,117k, and the light-emitting elements150-1,150-2.

As illustrated inFIG.8A, a portion of the second interlayer insulating film156is etched until the n-type semiconductor layer151-1is reached to form the opening158-1. The portion of the second interlayer insulating film156that is removed is at a position corresponding to the light-emitting element150-1. The light-emitting surface151S1is exposed from the second interlayer insulating film156. A portion of the second interlayer insulating film156is etched until the n-type semiconductor layer151-2is reached to form the opening158-2. The portion of the second interlayer insulating film156that is removed is at a position corresponding to the light-emitting element150-2. The light-emitting surface151S2is exposed from the second interlayer insulating film156. A portion of the second interlayer insulating film156is etched until the conductive thin film117kis reached to form the opening162. The portion of the second interlayer insulating film156that is removed is at a position corresponding to the wiring portion116k. The conductive thin film117kis exposed from the second interlayer insulating film156. The openings158-1,158-2,162are formed simultaneously, for example. As described above, in the process of forming the second interlayer insulating film156, the front surface of the second interlayer insulating film156need only have a level of flatness that can cover the light-emitting elements150-1,150-2. The exposed light-emitting surface151S1of the n-type semiconductor layer151-1and the exposed light-emitting surface151S2of the n-type semiconductor layer151-2are roughened to improve the light emission efficiency.

As illustrated inFIG.8B, the second wiring layer159is formed on the second interlayer insulating film156. The second wiring layer159includes the light-transmitting electrode159k. The light-transmitting electrode159kis formed across the surface of the conductive thin film117kexposed from the second interlayer insulating film156by the opening162and the light-emitting surfaces151S1,151S2. The light-transmitting electrode159kelectrically connects the n-type semiconductor layers151-1,151-2to the conductive thin film117kand the wiring portion116k.

In the above, a configuration in which the metal layers1130,1160are formed on both the semiconductor growth substrates1194-1,1194-2and the circuit substrate1100has been described, but the metal layer1160need only be provided on at least the circuit substrate1100side.

The portion of the circuit other than the sub-pixels20-1,20-2is formed in the circuit substrate1100. For example, the row selection circuit5illustrated inFIG.2is formed in the circuit substrate1100along with drive transistors, selection transistors, and the like. That is, the row selection circuit5may be incorporated at the same time by the manufacturing process described above. On the other hand, it is desirable to incorporate the signal voltage output circuit7into a semiconductor device manufactured by a manufacturing process that permits high integration by microprocessing. The signal voltage output circuit7is mounted on another substrate together with a central processing unit (CPU) and other circuit elements, and is interconnected with the wiring portions of the circuit substrate1100before incorporation of, for example, a color filter described below, or after incorporation of the color filter.

The circuit substrate1100includes the substrate102composed of a glass substrate and including the circuit101, and the substrate102is substantially rectangular, for example. The circuit101for one image display device1is formed on the circuit substrate1100as described above. Further, the circuit101for a plurality of image display devices may be formed on the circuit substrate1100. In the case of a larger screen size or the like, the circuit101for constituting one image display device may be divided into a plurality of the circuit substrates1100, and the divided circuits may all be combined to constitute one image display device.

The semiconductor layer1150having substantially the same dimensions as those of the crystal growth substrate1001is formed on the crystal growth substrate1001. For example, the crystal growth substrate1001can be rectangular with the same dimensions as those of the rectangular circuit substrate1100. The crystal growth substrate is not limited to having the same shape or a similar shape as that of the circuit substrate1100, and may have another shape. For example, the crystal growth substrate1001may have a generally circular wafer shape or the like having a diameter such that includes the circuit101formed in the rectangular circuit substrate1100.

FIG.9is a perspective view illustrating a manufacturing method of the image display device according to the present embodiment.

As illustrated inFIG.9, the plurality of semiconductor growth substrates1194-1,1194-2,1194-3, and the like may be prepared to bond the semiconductor layer1150formed on the plurality of crystal growth substrates1001to one circuit substrate1100. The semiconductor growth substrate1194-3is the same as the semiconductor growth substrates1194-1,1194-2described above, and the semiconductor layer1150is formed on the crystal growth substrate1001illustrated inFIG.3Aand the like on the semiconductor growth substrates1194-1,1194-2,1194-3, and the like.

In the circuit substrate1100, a plurality of the circuits101are disposed in a lattice pattern, for example, on one substrate102. The circuit101includes all sub-pixels20-1,20-2and the like required for one image display device1. An interval about a scribe line width is provided between the circuits101adjacently disposed. Circuit elements and the like are not disposed at an end portion or near an end portion of the circuit101.

The semiconductor layer1150is formed with an end portion thereof matching an end portion of the crystal growth substrate1001. Thus, the end portions of the semiconductor growth substrates1194-1,1194-2,1194-3are matchingly arranged and bonded with the end portions of the circuits101, thereby making it possible to match the end portions of the semiconductor layer1150and the end portions of the circuit101after bonding.

When the semiconductor layer1150is grown on the crystal growth substrate1001, the crystal quality readily deteriorates at and near the end portions of the semiconductor layer1150. Therefore, by matching the end portions of the semiconductor layer1150and the end portions of the circuits101, regions near the end portions of the semiconductor layer1150on the semiconductor growth substrates1194-1,1194-2,1194-3that readily deteriorate in crystal quality can be ensured not to be used for the display region of the image display device1. Here, there are various degrees of freedom in the method of arranging the crystal growth substrate1001. For example, as described above in connection withFIGS.4B and7Bmentioned above, in a case in which a plurality of the semiconductor layers1150are bonded to one circuit substrate1100, a circuit arrangement in which the light-emitting elements150-1,150-2are not formed at the boundary or in a region near the boundary of two semiconductor layers1150adjacent to each other or the like is preferred.

Contrary to the above, a plurality of circuit substrates1100may be prepared to bond the plurality of circuit substrates1100to the semiconductor layer1150formed on one semiconductor growth substrate.

FIG.10is a schematic cross-sectional view illustrating the manufacturing method of the image display device according to the present embodiment.

InFIG.10, to avoid complexities, the structure in the circuit substrate1100, the first interlayer insulating film112, the connecting portions115a1,115a2, the plugs116a1,116a2, the wiring portion116k, the conductive thin films117a1,117a2,117k, the second wiring layer159, and the like are omitted. Further, inFIG.10, a portion of the color conversion member such as the color filter180is illustrated. InFIG.10, the structure including the light-emitting elements150-1,150-2, the second interlayer insulating film156, the surface resin layer170, the plugs omitted in the illustration, and the like is referred to as a light-emitting circuit portion172. Further, the structure in which the light-emitting circuit portion172is provided on the circuit substrate1100is referred to as a structure1192.

As illustrated inFIG.10, one surface of the color filter (wavelength conversion member)180is adhered to the structure1192. The other surface of the color filter180is adhered to the glass substrate186. The one surface of the color filter180is provided with the transparent thin film adhesive layer188and adhered to a surface of the structure1192on the side of the light-emitting circuit portion172with the transparent thin film adhesive layer188interposed therebetween.

In the color filter180, in this example, color conversion units are arrayed in the positive direction of the X axis in the order of red, green, and blue. A color conversion layer183R of a red color is provided in a first layer for red, a color conversion layer183G of a green color is provided in the first layer for green, and the filter layer184is provided in a second layer for both. For blue, a single layer of a color conversion layer183B may be provided and the filter layer184may be provided. While the light-blocking portion181is provided between each color conversion unit, the frequency characteristics of the filter layer184, needless to say, can be changed for each color of the color conversion unit.

The color filter180is adhered to the structure1192with the positions of the color conversion layers183R,183G,183B of each color aligned to the position of the light-emitting element150.

FIGS.11A to11Dare schematic cross-sectional views illustrating a modified example of the manufacturing method of the image display device according to the present embodiment.FIGS.11A to11Dillustrate a method of forming the color filter by ink jetting.

As illustrated inFIG.11A, the structure1192in which the light-emitting circuit portion172is adhered to the circuit substrate1100is prepared.

As illustrated inFIG.11B, the light-blocking portion181is formed on the structure1192. The light-blocking portion181is formed using, for example, screen printing or a photolithography technique.

As illustrated inFIG.11C, a phosphor corresponding to the light emission color is ejected from an inkjet nozzle to form the color conversion layer183. The phosphor colors the region where the light-blocking portion181is not formed. As the phosphor, for example, a fluorescent coating that uses a typical phosphor material, a perovskite phosphor material, or a quantum dot phosphor material is used. Use of a perovskite phosphor material or a quantum dot phosphor material makes it possible to realize each light emission color, high chromaticity, and high color reproducibility, and is thus preferred. After the drawing by the inkjet nozzle, drying is performed at an appropriate temperature and for an appropriate time. A thickness of the coating film at the time of coloring is set thinner than a thickness of the light-blocking portion181.

As already described, in a case in which the color conversion unit is not to be formed for a blue light-emitting sub-pixel, the color conversion layer183is not formed. Further, for a blue light-emitting sub-pixel, in a case in which the color conversion unit need only be a single layer when the blue color conversion layer is formed, a thickness of the coating film of the blue phosphor is preferably about the same as the thickness of the light-blocking portion181.

As illustrated inFIG.11D, the coating for the filter layer184is ejected from an inkjet nozzle. The coating is applied so as to overlap the coating film of the phosphor. The total thickness of the coating film of the phosphor and the coating is about the same as the thickness of the light-blocking portion181.

Effects of the image display device1of the present embodiment will now be described.

In the manufacturing method of the image display device1of the present embodiment, the semiconductor layer1150is bonded to the circuit substrate1100including circuit elements such as the transistors103-1,103-2for driving the light-emitting elements150-1,150-2. Subsequently, the semiconductor layer1150is etched to form the light-emitting elements150-1,150-2. Therefore, the process of transferring the light-emitting elements150-1,150-2can be significantly shortened compared to individually transferring separated pieces of light-emitting elements to the circuit substrate1100.

For example, the number of sub-pixels exceeds 24 million in an image display device with 4K image quality, and exceeds 99 million in the case of an image display device with 8K image quality. To individually mount such a large number of light-emitting elements onto a circuit substrate requires an enormous amount of time, making it difficult to realize an image display device that uses micro LEDs at a realistic cost. Further, individually mounting a large number of light-emitting elements reduces yield due to connection failure and the like during mounting, and thus further increases in cost cannot be avoided.

As described above, in the manufacturing method of the image display device1of the present embodiment, the entire semiconductor layer1150is adhered to the circuit substrate1100prior to separating the semiconductor layer1150into pieces, and thus the transfer process is completed in one undertaking.

Further, because the semiconductor layer1150is adhered to the circuit substrate1100at the wafer level without being separated into pieces in advance or forming electrodes at positions corresponding to the circuit elements, alignment is not required. Therefore, the adhering process can be easily performed in a short period of time. Without alignment required at the time of adherence, the size of the light-emitting element150is readily reduced, which is suitable for a high-definition display.

In the present embodiment, a TFT formed on a glass substrate can be used as the circuit substrate1100, for example, making it possible to utilize an existing flat panel manufacturing process and plant.

In the present embodiment, the plugs116a1,116a2are formed in the circuit substrate1100. The plug116a1is electrically connected to the transistor103-1for driving. The plug116a2is electrically connected to the transistor103-2for driving. The semiconductor layer1150is etched, thereby respectively forming the light-emitting elements150-1,150-2on the plugs116a1,116a2. Therefore, the light-emitting element150-1is reliably electrically connected to the transistor103-1, and the light-emitting element150-2is reliably electrically connected to the transistor103-2. Accordingly, a reduction in yield due to connection failure of a light-emitting element or the like is suppressed.

In the present embodiment, the wiring layer116including the wiring portion116kis formed in the same layer as that of the plugs116a1,116a2. Because the wiring portion116kis formed on the same circuit substrate1100as that of the plugs116a1,116a2, the wiring portion116kcan be utilized as a wiring portion required for low impedance, such as the power source line and the ground line, making it possible to increase the degree of freedom in the layout of the wiring portions and arrangement of the circuit101. The wiring portion116kis formed simultaneously with the plugs116a1,116a2, and thus a wiring portion having low impedance can be readily realized without adding a process for the wiring portion116k.

In the present embodiment, the electrical connection on the light-emitting surface151S1,151S2side is made via the light-transmitting electrode159k. Therefore, the area of the light-emitting surfaces151S1,151S2can be sufficiently ensured, and high light emission efficiency can be achieved.

In the image display device1of the present embodiment, the plugs116a1,116a2also function as light-reflecting plates. The light scattered downward from the light-emitting elements150-1,150-2is reflected by the plugs116a1,116a2and distributed on the light-emitting surface151S1,151S2side. Therefore, the light emission efficiency of the light-emitting elements150-1,150-2is substantially improved.

The plugs116a1,116a2function as light-reflecting plates as well as light-blocking plates. The plugs116a1,116a2block light scattering downward of the light-emitting elements150-1,150-2. This makes it possible to suppress the irradiation of light to circuit elements in the vicinity below the light-emitting elements150-1,150-2and prevent malfunction and the like of the circuit elements.

In the present embodiment, wiring portions such as the power source line and the ground line are defined as the wiring portion116kand the first wiring layer110, thereby making it possible to improve the degree of freedom of the wiring pattern of the power source line, the ground line, and the like, and improve a design efficiency of the image display device.

Second Embodiment

FIG.12is a schematic cross-sectional view illustrating a portion of an image display device according to the present embodiment.

FIG.12schematically illustrates a cross section when a sub-pixel220is cut at a plane parallel to the XZ plane.

The present embodiment differs from the embodiment described above in that a flattening film214is provided, and a plug216kis embedded in the flattening film214. Note that, in the present embodiment, one sub-pixel220is described. However, as in the case of the other embodiments, a plurality of the sub-pixels220are provided in the XY plane and arrayed in the X-axis direction and the Y-axis direction. Further, an area of a light-emitting element250may also be a different area depending on the light emission color and the like. Components that are the same as those of the other embodiment described above are denoted by the same reference signs, and detailed descriptions thereof will be omitted as appropriate.

As illustrated inFIG.12, the sub-pixel220of the image display device of the present embodiment includes a transistor203, the first wiring layer110, the first interlayer insulating film112, the plug216k, the light-emitting element250, the second interlayer insulating film156, and a second wiring layer160. The sub-pixel220further includes the color filter180as in the other embodiment described above.

The transistor203is formed on the substrate102. The transistor203is an n-channel TFT in this example. The transistor203includes a TFT channel204and the gate107. The transistor203is formed by an LTPS process or the like as in the other embodiment described above. In the present embodiment, the circuit101includes the TFT channel204, the insulating layer105, the insulating film108, the vias111s,111d, and the first wiring layer110.

The TFT channel204includes regions204s,204i,204d. The regions204s,204i,204dare provided on the TFT lower layer film106. The regions204s,204dare doped with an n-type impurity such as phosphorous (P). The region204sis ohmic connected to the via111s. The region204dare ohmic connected to the via111d.

The gate107is provided on the TFT channel204with the insulating layer105interposed therebetween. The insulating layer105insulates the TFT channel204and the gate107.

In the transistor203, when a voltage higher than that of the region204sis applied to the gate107, a channel is formed in the region204i. A current flowing between the regions204s,204dis controlled by the voltage across the region204sof the gate107. The TFT channel204and the gate107are formed of a material and by a manufacturing method that are the same as those of the TFT channels104-1,104-2and the gates107-1,107-2in the other embodiment described above.

The vias111s,111dare provided through the insulating film108. The via111sis provided between the wiring portion110sand the region204s. The via111selectrically connects the wiring portion110sand the region204s. The via111dis provided between the wiring portion110dand the region204d. The via111delectrically connects the wiring portion110dand the region204d. The vias111s,111dare formed of a material and by a manufacturing method that are the same as those of the vias111s1,111d1, and the like in the other embodiment described above.

The wiring portion110sis electrically connected to the ground line4of the circuit illustrated inFIG.15described below, for example. The wiring portion110dis electrically connected to an n-type semiconductor layer251via a connecting portion215k, the plug216k, and a light-reflecting plate230a.

The flattening film214is provided on the first interlayer insulating film112. The flattening film214is a film or a layer having insulating properties and is, for example, similar to the first interlayer insulating film112, an organic insulating film such as PSG or BPSG, or an inorganic insulating film such as spin-on glass (SOG).

The plug216kis provided on the first interlayer insulating film112. A lateral surface of the plug216kis covered with the flattening film214. That is, the plug216kis embedded in the flattening film214. The plug216kand the flattening film214each include the same surface substantially parallel to the XY plane. The surface of the plug216kand the flattening film214is collectively flattened as described below.

The connecting portion215kis provided between the plug216kand the wiring portion110d. The connecting portion215kis formed of a conductive member and electrically connects the plug216kand the wiring portion110d. The plug216kand the connecting portion215kare formed of the same material as that of the first wiring layer110, for example.

The light-emitting element250is provided on the plug216kwith the light-reflecting plate230ainterposed therebetween. The light-emitting element250includes the n-type semiconductor layer (first semiconductor layer)251, a light-emitting layer252, and a p-type semiconductor layer (second semiconductor layer)253. The n-type semiconductor layer251, the light-emitting layer252, and the p-type semiconductor layer253are layered in the order of the n-type semiconductor layer251, the light-emitting layer252, and the p-type semiconductor layer253from the side of the first interlayer insulating film112toward the side of a light-emitting surface253S. Accordingly, the n-type semiconductor layer251is electrically connected to the plug216kvia the light-reflecting plate230a.

The light-emitting element250has the same shape as that of the light-emitting elements150-1,150-2of the other embodiment described above in an XY plane view. An appropriate shape is selected according to the layout of the circuit elements and the like.

The light-emitting element250is a light-emitting diode similar to those of the light-emitting elements150-1,150-2of the other embodiment described above. That is, the wavelength of the light emitted by the light-emitting element250corresponds to blue light emission having a wavelength of, for example, about 467 nm±20 nm or blue violet light emission having a wavelength of about 410 nm±20 nm. The wavelength of the light emitted by the light-emitting element250is not limited to the values described above and may be an appropriate value.

The second wiring layer (second wiring layer)160is provided on the second interlayer insulating film156. The second wiring layer160includes a wiring portion160a. The wiring portion160ais connected to the power source line3of the circuit illustrated inFIG.15described below, for example. The second wiring layer160is formed of the same material as that of the first wiring layer110and the like, for example.

In this example, a third wiring layer230is provided on the flattening film214and the plug216k. The third wiring layer230includes the light-reflecting plate230a. The light-reflecting plate230ais provided for each sub-pixel and the plurality of light-reflecting plates230aare electrically insulated. As described above, the light-emitting elements250are respectively provided on the light-reflecting plates230a.

The third wiring layer230and the light-reflecting plate230aare formed of a material having high conductivity. The light-reflecting plate230aincludes, for example, Ti, Al, and alloys of Ti and Sn. Cu, V, or the like, or a noble metal having high light reflectivity such as Ag or Pt may be included. With the light-reflecting plate230abeing formed of such a metal material or the like having high conductivity, the light-emitting element250and the circuit101are electrically connected at a low resistance.

In an XY plane view, an outer periphery of the light-emitting element250is located within an outer periphery of the light-reflecting plate230awhen the light-emitting element250is projected onto the light-reflecting plate230a. The outer periphery of the light-emitting element250being located within the outer periphery of the light-reflecting plate230aalso refers to the outer peripheries matching each other. Thus, the light-reflecting plate230acan reflect light scattering downward of the light-emitting element250toward the light-emitting surface253S side. By reflecting the light scattering downward of the light-emitting element250toward the light-emitting surface253S side, the light emission efficiency of the light-emitting element250can substantially be improved. Further, by reflecting the light scattering downward of the light-emitting element250toward the light-emitting surface253S side, malfunction of circuit elements, such as the transistor203, caused by the light scattering downward can be prevented.

A light-transmitting electrode159ais provided over the wiring portion160a. The light-transmitting electrode159ais provided over the light-emitting surface253S of the p-type semiconductor layer253that is open. The light-transmitting electrode159ais provided between the wiring portion160aand the light-emitting surface253S, and electrically connects the wiring portion160aand the p-type semiconductor layer253.

The n-type semiconductor layer251is electrically connected to the region204dvia the light-reflecting plate230a, the plug216k, the connecting portion215k, the wiring portion110d, and the via111d. The region204dcorresponds to a drain electrode of the transistor203. The region204scorresponds to a source electrode of the transistor203and is electrically connected to the ground line4through the via111sand the wiring portion110s.

The p-type semiconductor layer253is electrically connected to the power source line3via the light-transmitting electrode159aand the wiring portion160a.

Modified Example

FIG.13is a schematic cross-sectional view illustrating a portion of a modified example of an image display device of the present embodiment.

As illustrated inFIG.13, in a sub-pixel220aof this modified example, the plug216kis connected to the wiring portion110dwithout being via the connecting portion215killustrated inFIG.12.

As described in relation toFIG.12, in a case in which the plug216kis connected to the wiring portion110dvia the connecting portion215k, an outer periphery of the plug216kcan be formed protruding outward beyond an outer periphery of the wiring portion110din an XY plane view. In a case in which the outer periphery of the plug216kis inward of the outer periphery of the wiring portion110din an XY plane view, as in the present modified example, the plug216kcan be provided directly on the wiring portion110dand not via the connecting portion215k. That is, in accordance with a positional relationship between the plug and the wiring portion of the connection destination as well as the respective shapes of the plug and the wiring portion of the connection destination, the wiring portion and the element can be connected to each other with or without the connecting portion being provided. This is the same for each of the embodiments and modified examples described below as well.

FIGS.14A and14Bare schematic cross-sectional views illustrating portions of modified examples of the image display device according to the present embodiment. In the cross-sectional views of the sub-pixels inFIG.14Aand subsequent drawings, illustration of the surface resin layer170, the transparent thin film adhesive layer188, and the color filter180is omitted in order to avoid complexity. Unless otherwise specified, the surface resin layer170, the transparent thin film adhesive layer188, and the color filter180are provided on the second interlayer insulating film and the second wiring layer. The same applies to the other embodiments and other modified examples described below as well.

In the case of a sub-pixel220bof the modified example illustrated inFIG.14A, the structure of the wiring portion for electrical connection to the light-emitting surface253S side differs from that of the second embodiment. Other components are the same as those of the second embodiment, are denoted by the same reference signs, and detailed descriptions thereof will be omitted as appropriate.

As illustrated inFIG.14A, the sub-pixel220bincludes the second wiring layer160, and the second wiring layer160includes a wiring portion160a1. The wiring layer160a1is provided on the second interlayer insulating film156. In the present modified example, the wiring portion160a1is electrically connected to the p-type semiconductor layer253by connecting one end of the wiring portion160a1to a surface including the light-emitting surface253S. The surface connecting the one end of the wiring portion160a1is coplanar with the light-emitting surface253S. In the present modified example, the light-transmitting electrode is not provided, and thus the process of forming the light-transmitting electrode can be omitted. The light-emitting surface253S is preferably roughened as in this example.

In the case of a sub-pixel220cof the modified example illustrated inFIG.14B, the configuration of a second interlayer insulating film256and a wiring portion160a2differs from that of the second embodiment.

As illustrated inFIG.14B, the sub-pixel220cincludes the second interlayer insulating film256. The second wiring layer160includes the wiring portion160a2, and the wiring portion160a2is provided on the second interlayer insulating film256. The second interlayer insulating film256is a transparent resin. The second interlayer insulating film256is not provided with an opening corresponding to the position of the light-emitting surface253S. The wiring portion160a2of the second wiring layer160is directly connected to the light-emitting surface253S.

A light-emitting element250aemits light from the light-emitting surface253S via the second interlayer insulating film256. In the present modified example, the process of forming an opening in the second interlayer insulating film256and roughening the surface of the p-type semiconductor layer253acan be omitted.

The second interlayer insulating film256is, for example, formed of a transparent organic insulating material. As a transparent resin material, silicon-based resins such as spin-on glass (SOG), novolac phenolic resin, and the like can be used. As in the other embodiments described above, the second interlayer insulating film256is insulation between the light-emitting elements and is provided for protection from the external environment. A front surface of the second interlayer insulating film256, as in the second interlayer insulating film156, need only be flat enough to allow formation of the second wiring layer160.

In any of the modified examples as well, the configuration including the surface resin layer170, the transparent thin film adhesive layer188, and the color filter180is provided in the same manner as in the other embodiments described above.

FIG.15is a schematic block diagram illustrating an image display device according to the present embodiment.

As illustrated inFIG.15, an image display device201of the present embodiment includes the display region2, a row selection circuit205, and a signal voltage output circuit207. In the display region2, a sub-pixel220is arrayed in a lattice pattern on the XY plane, for example, as in the other embodiment described above.

The pixel10, as in the other embodiment described above, includes a plurality of the sub-pixels220that emit light of different colors. A sub-pixel220R emits red light. A sub-pixel220G emits green light. A sub-pixel220B emits blue light. The three types of sub-pixels220R,220G,220B emit light at a desired brightness, thereby determining the light emission color and brightness of one pixel10.

One pixel10is formed of the three sub-pixels220R,220G,220B, and the sub-pixels220R,220G,220B are arrayed in a linear shape on the X axis, for example, as in this example. In each pixel10, sub-pixels of the same color may be arrayed in the same column or, as in this example, sub-pixels of different colors may be arrayed on a per column basis.

The sub-pixel220includes a light-emitting element222, a selection transistor224, a drive transistor226, and a capacitor228. InFIG.15, the selection transistor224may be denoted as T1, the drive transistor226may be denoted as T2, and the capacitor228may be denoted as Cm.

In the present embodiment, the light-emitting element222is provided on the power source line3side, and the drive transistor226connected in series with the light-emitting element222is provided on the ground line4side. That is, the drive transistor226is connected to a potential side lower than that of the light-emitting element222. The drive transistor226is an n-channel transistor.

The selection transistor224is connected between a gate electrode of the drive transistor226and a signal line208. The capacitor228is connected between the gate electrode of the drive transistor226and the ground line4.

The row selection circuit205and the signal voltage output circuit207supply a signal voltage of a polarity different from that of the other embodiment described above to the signal line208in order to drive the drive transistor226that is an n-channel transistor.

In the present embodiment, the polarity of the drive transistor226is the n-channel, and thus the polarity of the signal voltage and the like differ from those of the other embodiment described above. That is, the row selection circuit205supplies a selection signal to a scanning line206, sequentially selecting one row from the array of m rows of the sub-pixels220. The signal voltage output circuit207supplies a signal voltage having the required analog voltage value for each sub-pixel220in the selected row. The drive transistor226of the sub-pixels220of the selected row introduces a current corresponding to the signal voltage to the light-emitting element222. The light-emitting element222emits light at a brightness in accordance with the flowing current.

In the present embodiment, any of the configurations of the sub-pixels220,220a,220b,220cdescribed above can be included. Further, the embodiments described below may also apply modified examples of sub-pixels as in the present embodiment.

A manufacturing method of the image display device according to the present embodiment will now be described.

FIGS.16A to20Care schematic cross-sectional views illustrating the manufacturing method of the image display device according to the present embodiment.

FIGS.16A to18Billustrate a procedure of forming a plug on the circuit substrate1100. In the present embodiment, a formation method of a plug different from the plug formation method described in the first embodiment is employed.

As illustrated inFIG.16A, the circuit substrate1100is prepared. The prepared circuit substrate1100may be the same as that in the first embodiment.

As illustrated inFIG.16B, the contact hole h is formed in the first interlayer insulating film112. The location where the contact hole h is formed is a position corresponding to the wiring portion110d. The contact hole h is formed deeper than the depth reaching the wiring110dfrom the first interlayer insulating film112as in this example. In a case in which an exposed area of the wiring portion110dcan be sufficiently ensured during formation of the contact hole h, the depth of the contact hole h may be set to a front surface of the wiring portion110d.

As illustrated inFIG.17A, a metal layer1116is formed over the first interlayer insulating film112. During formation of the metal layer1116, the contact hole h illustrated inFIG.16Bis embedded with the same material as that of the metal layer1116. The connecting portion215kis formed in the embedded portion.

As illustrated inFIG.17B, the plug216kis molded into a desired shape from the metal layer1116illustrated inFIG.17Aby photolithography, dry etching, or the like.

As illustrated inFIG.18A, a flattening film1114is applied, covering the first interlayer insulating film112and the plug216k, and then baked.

As illustrated inFIG.18B, a front surface of the flattening film1114illustrated inFIG.18Ais polished, exposing a surface of the plug216k. After the surface of the plug216kis exposed, the plug216kand the flattening film214are collectively polished and flattened. CMP, for example, is used for polishing the flattening film1114. In this way, the plug216k, the connecting portion215k, and the flattening film214are formed.

In the case of the sub-pixel220aof the modified example illustrated inFIG.13, in the process illustrated inFIG.16B, the first interlayer insulating film112is etched at least until the front surface of the wiring portion110dis reached, in accordance with the shape of the plug216k. Subsequently, as illustrated inFIG.17AandFIG.17B, the metal layer1116is formed and then the metal layer1116is molded into the desired shape of the plug216k. As illustrated inFIGS.18A and18B, the flattening film1114is formed and then can be flattened all at once by CMP or the like to form the plug216kand the flattening film214.

Subsequently, the process of forming the light-emitting element and the like by bonding a semiconductor growth substrate to a circuit substrate on which a plug is formed will be described.

As illustrated inFIG.19A, a semiconductor growth substrate1294is prepared. The semiconductor growth substrate1294includes the crystal growth substrate1001, the buffer layer1140, and the semiconductor layer1150. The buffer layer1140is formed on the crystal growth substrate1001. The semiconductor layer1150is formed on the buffer layer1140. The semiconductor layer1150includes the p-type semiconductor layer1153, the light-emitting layer1152, and the n-type semiconductor layer1151. The p-type semiconductor layer1153, the light-emitting layer1152, and the n-type semiconductor layer1151are layered in the order of the p-type semiconductor layer1153, the light-emitting layer1152, and the n-type semiconductor layer1151from the buffer layer1140side. The metal layer1130is formed on the exposed surface of the n-type semiconductor layer1151.

As illustrated inFIG.19B, the semiconductor growth substrate1294on which the metal layer1130is formed and the circuit substrate (third substrate)1100on which the plug216kis formed are prepared. The plug216kof the circuit substrate1100and the formed surface of the flattening film214are disposed facing the exposed surface of the metal layer1130of the semiconductor growth substrate1294. The surfaces facing each other are bonded to each other. The bonding of the substrates is the same as in the other embodiments described above. Further, the modified example of the manufacturing method described in relation toFIG.5AtoFIG.5Cmay be applied. Furthermore, as the semiconductor growth substrate, a substrate in which the semiconductor layer1150is directly formed on the crystal growth substrate1001without providing the buffer layer1140may be used.

As illustrated inFIG.20A, the crystal growth substrate1001illustrated inFIG.19Bis removed by laser lift-off or the like. In this example, before the semiconductor layer1150is etched, the buffer layer1140illustrated inFIG.19Bis removed by wet etching or the like. The buffer layer1140may be removed after the semiconductor layer1150has been etched.

As illustrated inFIG.20B, the semiconductor layer1150and the metal layer1130illustrated inFIG.20Aare molded into desired shapes by RIE or the like. The third wiring layer230is formed from the metal layer1130, and the third wiring layer230includes the light-reflecting plate230a. In this example, the semiconductor layer1150is overetched, thereby molding the outer periphery of the light-reflecting plate230ato substantially match the outer periphery of the light-emitting element250projected onto the light-reflecting plate230ain an XY plane view.

In a case in which the semiconductor layer1150is not overetched, the semiconductor layer1150is etched to form the light-emitting element250, and then the metal layer1130is etched to form the third wiring layer230. In this case, the outer periphery of the light-emitting element250projected onto the light-reflecting plate230ais located within the outer periphery of the light-reflecting plate230ain an XY plane view; the outer periphery of the light-reflecting plate230acan be larger than the outer periphery of the light-emitting element250.

As illustrated inFIG.20C, the second interlayer insulating film156is formed covering the flattening film214, the third wiring layer230, and the light-emitting element250. At a position of the second interlayer insulating film156corresponding to the light-emitting element250, a portion of the second interlayer insulating film156is removed by etching to form an opening158, and the light-emitting surface253S is exposed from the second interlayer insulating film156. The exposed light-emitting surface253S of the p-type semiconductor layer253is roughened in order to improve the light emission efficiency.

The second wiring layer160is formed on the second interlayer insulating film156. In the second wiring layer160, each wiring portion including the wiring portion160ais formed by photolithography. Note that, in this example, the wiring portion160ais provided at a position distant from the p-type semiconductor layer253.

A light-transmitting conductive film covering the second wiring layer160, the second interlayer insulating film156, and the light-emitting surface253S is formed. An ITO film, a ZnO film, or the like is suitably used as the light-transmitting conductive film. The desired light-transmitting electrode159ais formed by photolithography.

The light-transmitting electrode159ais provided over the wiring portion160a. The light-transmitting electrode159ais formed over the light-emitting surface253S. The light-transmitting electrode159ais formed between the wiring portion160aand the light-emitting surface253S. Accordingly, the wiring portion160aand the p-type semiconductor layer253are electrically connected by the light-transmitting electrode159a.

FIGS.21A to22Bare schematic cross-sectional views illustrating manufacturing methods of the modified examples of the image display device of the present embodiment.

FIGS.21A and21Billustrate a manufacturing process for forming the sub-pixel220bof the modified example illustrated inFIG.14A.FIGS.22A and22Billustrate a manufacturing process for forming the sub-pixel220cof the modified example illustrated inFIG.14B. All processes inFIGS.21A and22Aare executed after the processes illustrated inFIG.20B, and thus the processes followingFIG.20Bwill be described in the descriptions below.

First, the manufacturing method of the sub-pixel220bwill be described.

As illustrated inFIG.21A, in the sub-pixel220bof the modified example, the second interlayer insulating film156is formed covering the flattening film214, the third wiring layer230, and the light-emitting element250, and then the opening158is formed. The opening158is formed by removing a portion of the second interlayer insulating film156, thereby exposing the light-emitting surface253S from the second interlayer insulating film156. In this example, the light-emitting surface253S is roughened.

As illustrated inFIG.21B, the second wiring layer160is formed. The second wiring layer160includes the wiring portion160a1. The wiring portion160a1is connected to a surface of the p-type semiconductor layer253including the light-emitting surface253S at one end of the wiring portion160a1. The surface on which the one end of the wiring portion160a1is connected is parallel to the light-emitting surface253S.

Subsequently, the manufacturing method of the sub-pixel220cwill be described.

As illustrated inFIG.22A, in the sub-pixel220cof the modified example, the second interlayer insulating film256is formed covering the flattening film214, the third wiring layer230, and the light-emitting element250. The second interlayer insulating film256is formed of a transparent resin.

As illustrated inFIG.22B, the contact hole is formed in the second interlayer insulating film256, and then the second wiring layer160is formed. The second wiring layer160includes the wiring portion160a2. The wiring portion160a2is connected to a surface of the p-type semiconductor layer253including the light-emitting surface253S via the contact hole.

Then, the color filter180and the like are provided, thereby forming the sub-pixel220of the image display device201of the present embodiment and the sub-pixels220a,220b,220cof the modified examples.

Effects of the image display device of the present embodiment will now be described. In the image display device of the present embodiment, in addition to the effects of the other embodiment described above, the sub-pixels220,220a,220b,220cinclude the light-reflecting plate230ain addition to the plug216k, and thus the plug216kcan be made smaller.

Third Embodiment

FIG.23is a schematic cross-sectional view illustrating a portion of an image display device according to the present embodiment.

FIG.23schematically illustrates a cross section in a case in which a sub-pixel320is cut at a plane parallel to the XZ plane.

In the present embodiment, the light-emitting element150differs from those of the second embodiment and the modified examples thereof in being provided on the plug216awithout a light-reflecting plate interposed therebetween. Components that are the same as those of the other embodiments described above are denoted by the same reference signs, and detailed descriptions thereof will be omitted as appropriate.

As illustrated inFIG.23, the sub-pixel320of the image display device of the present embodiment includes a transistor103, the light-emitting element150, and the plug216a. The transistor103is formed on the first surface102aof the substrate102as in the other embodiments described above.

The transistor103includes the TFT channel104and a gate107. The TFT channel104includes regions104s,104i,104d. The regions104s,104i,104dare provided on the TFT lower layer film106. The region104iis provided between the regions104s,104d. The regions104s,104dare ohmic connected to the vias111s,111d. The transistor is a p-channel TFT.

The gate107is provided on the TFT channel104with the insulating layer105interposed therebetween. The TFT channel104and the gate107are insulated from each other by the insulating layer105.

The regions104s,104i,104dof the TFT channel104and the gate107are formed of the same materials and by the same manufacturing methods as those of the first embodiment.

The vias111s,111dand the wiring portions110s,110dare configured in the same manner as in the second embodiment and the modified examples thereof, and are formed of the same materials and by the same manufacturing methods.

The light-emitting element150is provided on the plug216a. The plug216ais connected to the wiring portion110dvia the connecting portion215a. The light-emitting element150includes the p-type semiconductor layer153, the light-emitting layer152, and the n-type semiconductor layer151. The p-type semiconductor layer153, the light-emitting layer152, and the n-type semiconductor layer151are layered in the order of the p-type semiconductor layer153, the light-emitting layer152, and the n-type semiconductor layer151from the side of the plug216atoward the side of the light-emitting surface151S. Accordingly, the p-type semiconductor layer153is electrically connected to the region104dvia the plug216a, the connecting portion215a, the wiring portion110d, and the via111d. The wiring portion110sis connected to the power source line3of the circuit illustrated inFIG.2. The wiring portion110sis connected to the region104sthrough the via111s. Accordingly, the region104sis electrically connected to the power source line3through the via111sand the wiring portion110s.

An outer periphery of the light-emitting element150is located within the outer periphery of the plug216aincludes when the light-emitting element150is projected onto the plug216ain an XY plane view. The plug216afunctions as a light-reflecting plate. The plug216areflects light scattering downward of the light-emitting element150toward the light-emitting surface151S side. The plug216ablocks the light scattering downward of the light-emitting element150, inhibiting the light from reaching circuit elements such as the transistor103.

The n-type semiconductor layer151includes the light-emitting surface151S, and the light-emitting surface151S is exposed from the second interlayer insulating film156by the opening158.

The second wiring layer160is formed on the second interlayer insulating film156. The second wiring layer160includes a wiring portion260k. The wiring portion260kis connected to the ground line4of the circuit illustrated inFIG.2, for example. A light-transmitting electrode259kis provided over the wiring portion260k. The light-transmitting electrode259kis provided over the light-emitting surface151S. The light-transmitting electrode259kis provided between the wiring portion260kand the light-emitting surface151S. Accordingly, the n-type semiconductor layer151is electrically connected to the ground line4via the light-transmitting electrode259kand the wiring portion260k.

The color filter180and the like are further provided as in the other embodiments described above.

A manufacturing method of the image display device according to the present embodiment will now be described.

FIGS.24A to25Care schematic cross-sectional views illustrating the manufacturing method of the image display device of the present embodiment.

As illustrated inFIG.24A, a semiconductor growth substrate1194is prepared. The semiconductor growth substrate1194includes the crystal growth substrate1001, the buffer layer1140, and the semiconductor layer1150. In the semiconductor growth substrate1194, the buffer layer1140is formed on the crystal growth substrate1001. The semiconductor layer1150is formed on the buffer layer1140. The semiconductor layer1150includes the n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153. The n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153are layered in the order of the n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153from the buffer layer1140side. As in the other embodiments described above, a metal layer may be formed on the exposed surface of the p-type semiconductor layer1153. In a case in which the metal layer is formed, a light-transmitting conductive film may be provided between the p-type semiconductor layer1153and the metal layer.

As illustrated inFIG.24B, the semiconductor growth substrate1194and the circuit substrate (second substrate)1100on which the plug216ais formed are prepared. The plug216aand the connecting portion215aare formed by applying the manufacturing processes described in relation toFIGS.16A to18B.

The prepared semiconductor growth substrate1194and the circuit substrate1100on which the plug216ais formed are bonded to each other. The bonding surface of the semiconductor growth substrate1194is an exposed surface of the p-type semiconductor layer1153. The exposed surface of the p-type semiconductor layer1153faces the surface on which the light-emitting layer1152is provided. The bonding surface of the circuit substrate1100on which the plug216ais formed is the flattened surface of the plug216aand the flattening film214.

As illustrated inFIG.25A, after the wafer bonding of the semiconductor layer1150and the circuit substrate1100, the crystal growth substrate1001is removed.

As illustrated inFIG.25B, the semiconductor layer1150illustrated inFIG.25Ais etched, forming the light-emitting element250. In this example, the buffer layer1140and the semiconductor layer1150illustrated inFIG.25Aare molded simultaneously by RIE or the like.

As illustrated inFIG.25C, the buffer layer240is removed, and then the second interlayer insulating film156covering the flattening film214, the plug216a, and the light-emitting element150is formed. A portion of the second interlayer insulating film156is removed, thereby forming the opening158in the second interlayer insulating film156, and the light-emitting surface151S exposed from the opening158is roughened. Subsequently, the second wiring layer160including the wiring portion260kis formed, and the light-transmitting electrode259kis formed on the second wiring layer160by an ITO film or the like.

Effects of the image display device of the present embodiment will now be described. The present embodiment has the same effects as those of the other embodiments described above. In addition, because the plug216ais utilized as a light-reflecting plate, the process of forming the light-reflecting plate separately can be omitted.

Because a light-reflecting plate is not provided between the plug216aand the p-type semiconductor layer153, the resistance between the p-type semiconductor layer153and the transistor103can be reduced.

Fourth Embodiment

FIG.26is a schematic cross-sectional view illustrating a portion of an image display device according to the present embodiment.

FIG.26schematically illustrates a cross section in a case in which a sub-pixel420is cut at a plane parallel to the XZ plane.

In the present embodiment, the configuration of the light-emitting element150is the same as that of the third embodiment. That is, the light-emitting element150includes the p-type semiconductor layer153, the light-emitting layer152, and the n-type semiconductor layer151layered from the lower layer toward the upper layer. The transistor103for driving the light-emitting element150is a p-channel transistor, and the circuit configuration illustrated inFIG.2is applied to the drive circuit of the sub-pixel420, for example. Components that are the same as those of the other embodiments described above are denoted by the same reference signs, and detailed descriptions thereof will be omitted as appropriate.

As illustrated inFIG.26, the sub-pixel420of the image display device of the present embodiment includes the transistor103, the light-emitting element150, a third wiring layer430, and a plug416a. In the present embodiment, the p-type semiconductor layer153is connected to a drain electrode of the transistor103via a wiring portion430aof the third wiring layer430and the plug416a. The n-type semiconductor layer151is connected to the ground line4of the circuit illustrated inFIG.2, for example, via the light-transmitting electrode259kof the second wiring layer159and a wiring portion430kof the third wiring layer430.

The structure of the transistor103, the structure of the upper portion of the transistor103, and the structure of the wiring portions in the circuit substrate100are the same as those of the third embodiment described above, and detailed description thereof will be omitted.

The flattening film214and the plug416kare formed on the first interlayer insulating film112. The flattening film214is also provided on a lateral surface of the plug416a. That is, the plug416ais embedded in the flattening film214. The exposed surface of the plug416afrom the flattening film214is formed in substantially the same plane as that of the flattening film214. This plane is substantially parallel to the XY plane. The plug416ais connected to the wiring portion110dby the connecting portion215aprovided in the first interlayer insulating film112.

The third wiring layer (third wiring layer)430is provided on the flattening film214and the plug416a. The third wiring layer430includes the wiring portions430aand430k. The wiring portion430ais provided on the plug416a, and the wiring portion430aand the plug416aare electrically connected.

The light-emitting element150is provided on the wiring portion430a. The light-emitting element150is layered in the order of the p-type semiconductor layer153, the light-emitting layer152, and the n-type semiconductor layer151from the side of the wiring layer430atoward the side of the light-emitting surface151S. That is, the top of the wiring portion430ais connected to the p-type semiconductor layer153. Preferably, the wiring portion430ais ohmic connected to the p-type semiconductor layer153and is connected to the wiring portion110dvia the plug416aand the connecting portion215a.

The wiring portion430aalso functions as a light-reflecting plate. That is, the outer periphery of the light-emitting element150projected onto the wiring portion430ais located within an outer periphery of the wiring portion430aincludes in an XY plane view.

The wiring portion430kis connected to the ground line4of the circuit illustrated inFIG.2, for example. The wiring portion430ksurrounds the wiring portion430a, for example.

The second interlayer insulating film156is formed on the flattening film214, the third wiring layer430, and the light-emitting element150. The second interlayer insulating film156includes the openings158,462. The opening158is provided at a position corresponding to the light-emitting element150. The opening158, with a portion of the second interlayer insulating film156being removed, exposes the light-emitting surface151S from the second interlayer insulating film156. The opening462is provided at a position corresponding to the wiring portion430k. The opening462, with a portion of the second interlayer insulating film156being removed, exposes a portion of the wiring portion430kfrom the second interlayer insulating film156.

The light-transmitting electrode259kis provided over the light-emitting surface151S. The light-transmitting electrode259kis provided over the wiring portion430kexposed from the second interlayer insulating film156via the opening462. The light-transmitting electrode259kis provided across the wiring portion430kexposed from the light-emitting surface151S and the second interlayer insulating film156. The light-transmitting electrode259kelectrically connects the n-type semiconductor layer151and the wiring portion430k.

Modified Example of Sub-Pixel

FIG.27is a schematic cross-sectional view illustrating a portion of a modified example of the image display device according to the present embodiment.

In this modified example, the light-emitting element150differs from that of the fourth embodiment described above in being driven by the transistor203of an n-channel. The configuration of the light-emitting element150is the same as that of the fourth embodiment. The circuit configuration illustrated inFIG.15, for example, is applied to the drive circuit that drives the light-emitting element150by the transistor203.

In the modified example of this sub-pixel, a sub-pixel420aincludes a plug416k. The plug416kis connected to the wiring portion110dvia a connecting portion415k.

The wiring portion430kis provided on the plug416k, and the plug416kis electrically connected to the wiring portion430k. The wiring portion430kis exposed from the second interlayer insulating film156via the opening462. The wiring portion430kexposed from the second interlayer insulating film156is connected to the light-transmitting electrode259k. The light-transmitting electrode259kis provided over the light-emitting surface151S and connected to the n-type semiconductor layer151.

The p-type semiconductor layer153is provided on the wiring portion430a, and the p-type semiconductor layer153is electrically connected to the wiring portion430a. The wiring portion430ais electrically connected to the power source line3illustrated inFIG.15, for example. That is, in the present modified example, a drive circuit such as illustrated inFIG.15that drives the light-emitting element150provided on the power source line3side by the transistor203provided on the ground line4side is applied.

A manufacturing method of the image display device according to the present embodiment will now be described.

FIGS.28A and28Bare schematic cross-sectional views illustrating the manufacturing method of the image display device of the present embodiment.

In the present embodiment, the processes up to the semiconductor layer1150on which the metal layer1130is formed being bonded to the circuit substrate1100on which the plug is formed are the same as those in the second embodiment, for example, described above, as illustrated inFIG.19AtoFIG.20A. Hereinafter, the manufacturing processes following the wafer bonding and the removal of the crystal growth substrate1001will be described. Note that, in the second embodiment, while the p-type semiconductor layer1153is formed on the crystal growth substrate1001side as illustrated inFIGS.19A to20Aand the like, in the present embodiment, a semiconductor growth substrate in which the n-type semiconductor layer1151is formed on the crystal growth substrate1001side, and the metal layer1130is formed on the exposed surface of the p-type semiconductor layer1153, as illustrated inFIG.3Aand the like, is used. A layer of a conductive thin film having hole injection properties may be provided between the p-type semiconductor layer1153and the metal layer1130.

As illustrated inFIG.28A, the semiconductor layer1150is processed by RIE or the like to form the light-emitting element150. After formation of the light-emitting element150, the metal layer1130is processed by dry etching or wet etching to form the third wiring layer430including the wiring portions430a,430k.

As illustrated inFIG.28B, the second interlayer insulating film156is formed, covering the third wiring layer430, the flattening film214, and the light-emitting element150.

The openings158,462are formed in the second interlayer insulating film156. A portion of the second interlayer insulating film156is etched until the opening158reaches the n-type semiconductor layer151, exposing the light-emitting surface151S from the second interlayer insulating film156. The light-emitting surface151S is roughened. A portion of the second interlayer insulating film156is etched until the opening462reaches the wiring portion430k, exposing the wiring portion430kfrom the second interlayer insulating film156.

The second wiring layer159is formed on the second interlayer insulating film156. The second wiring layer159includes the light-transmitting electrode259k. The light-transmitting electrode259kelectrically connects the n-type semiconductor layer151and the wiring portion430k.

Thereafter, the color filter is formed as in the other embodiments.

In this way, the image display device of the present embodiment can be manufactured.

Effects of the image display device of the present embodiment will now be described. The image display device of the present embodiment achieves the same effects as those of the other embodiments described above, and further has the following effects.

The sub-pixel420of the image display device of the present embodiment is electrically connected on the light-emitting surface151S side by the light-transmitting electrode259k, and electrically connected on the side of the surface facing the light-emitting surface151S via the wiring portion430a, the plug416a, and the connecting portion215a. Therefore, all wiring portions on the light-emitting surface151S side can be light-transmitting electrodes, making it possible to improve the light emission efficiency of the light-emitting element150and reduce the cost of the wiring process.

By using light-transmitting electrodes for all wiring layers on the light-emitting surface151S side and using the third wiring layer430that is an inner layer for wiring portions such as the power source line and the ground line, the degree of freedom of the wiring pattern of the power source line, the ground line, and the like can be improved, and thus improving the design efficiency of the image display device.

With regard to the sub-pixel420aof the modified example as well, the electrical connection on the light-emitting surface151S side is made by the light-transmitting electrode259k, making it possible to improve the light emission efficiency of the light-emitting element150and reduce the wiring process cost. Further, by changing the connection destinations of the plugs430k,416k, an appropriate circuit can be selected as the drive circuit as desired.

Fifth Embodiment

In an image display device of the present embodiment, circuit elements such as a transistor is formed on a flexible substrate instead of a glass substrate. In other respects, components that are the same as those of the other embodiments described above are denoted by the same reference signs, and detailed descriptions thereof will be omitted as appropriate.

FIG.29is a schematic cross-sectional view illustrating a portion of the image display device according to the present embodiment.

FIG.29schematically illustrates a cross section when sub-pixels520-1,520-2are cut at a plane parallel to the XZ plane.

As illustrated inFIG.29, the image display device of the present embodiment includes the sub-pixels520-1.520-2. The sub-pixels520-1,520-2include a substrate402that is common to both. The substrate402includes the first surface402a. Circuit elements such as the transistors103-1,103-2are provided on the first surface402a. In the sub-pixels520-1,520-2, an upper structure including circuit elements, wiring layers, and the like is formed on the first surface402a.

The substrate402is flexible. The substrate402is, for example, formed of a polyimide resin. The first interlayer insulating film112, the second interlayer insulating film156, the first wiring layer110, the second wiring layer159, and the like are preferably formed of a material having a certain degree of flexibility in accordance with the flexibility of the substrate402. Note that the element having the highest risk of destruction during bending is the first wiring layer110having the longest wiring length. Therefore, it is desirable to adjust various film thicknesses, film qualities, and material qualities, thereby positioning, on the first wiring layer110, a neutral surface including a plurality of protective films and the like added to the front surface and the back surface as needed.

In this example, the structure above the TFT lower layer film106is the same as that in the first embodiment described above. Configurations of the other embodiments can also be readily applied.

A manufacturing method of the image display device according to the present embodiment will now be described.

FIGS.30A and30Bare schematic cross-sectional views illustrating the manufacturing method of the image display device of the present embodiment.

As illustrated inFIG.30A, in the present embodiment, a circuit substrate5100different from those of the other embodiments described above is prepared. The circuit substrate (third substrate)5100includes the two layers of the substrates102,402. As described above, the substrate102is, for example, a glass substrate. The substrate (fourth substrate)402is provided on the first surface102aof the substrate102. For example, the substrate402is formed by, for example, applying and then baking a polyimide material on the first surface102aof the substrate102. An inorganic film such as SiNxmay be further interposed between the two layers of the substrates102,402. The TFT lower layer film106, the circuit101, and the first interlayer insulating film112are provided on the first surface402aof the substrate402. The first surface402aof the substrate402is the surface facing the surface on which the substrate102is provided.

In such a circuit substrate5100, an upper structure of the sub-pixels520-1,520-2is formed by applying the processes described inFIGS.3A to11D, for example.

As illustrated inFIG.30B, the substrate102is removed from the structure in which an upper structure including the color filter (not illustrated) and the like are formed, forming a new circuit substrate5100a. To remove the substrate102, laser lift-off is used, for example. Removal of the substrate102is not limited to the point in time described above, and can be performed at another appropriate point in time. For example, the substrate102may be removed after wafer bonding or before formation of the color filter. By removing the substrate102at an earlier point in time, defects such as cracking and chipping during the manufacturing process can be reduced.

Effects of the image display device of the present embodiment will now be described. The substrate402is flexible and thus can be bent as an image display device and can be adhered to a curved surface or utilized with a wearable terminal or the like without any discomfort.

Sixth Embodiment

In the present embodiment, a plurality of light-emitting surfaces corresponding to a plurality of light-emitting elements are formed in a single semiconductor layer including a light-emitting layer, thereby realizing an image display device having a higher light emission efficiency. In the description below, components that are the same as those of the other embodiments described above are denoted by the same reference signs, and detailed descriptions thereof will be omitted as appropriate.

FIG.31is a schematic cross-sectional view illustrating a portion of an image display device according to the present embodiment.

As illustrated inFIG.31, the image display device includes a sub-pixel group620. The sub-pixel group620includes the plurality of transistors103-1,103-2, a first wiring layer610(first wiring layer), the first interlayer insulating film (first insulating film)112, plugs616a1,616a2, a semiconductor layer650, a second interlayer insulating film (second insulating film)656, and a second wiring layer (second wiring layer)660.

In the present embodiment, the transistors103-1,103-2of a p-channel are turned on, thereby injecting holes into the semiconductor layer650via the plugs616a1,616a2and injecting electrons into the semiconductor layer650via the second wiring layer660, causing a light-emitting layer652to emit light. The circuit configuration illustrated inFIG.2, for example, is applied to the drive circuit. The n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer can be vertically interchanged by using the other embodiments described above to make a configuration in which the semiconductor layer is driven by an n-channel transistor. In such a case, the circuit configuration ofFIG.15, for example, is applied to the drive circuit.

The semiconductor layer650includes two light-emitting surfaces651S1,651S2, and the sub-pixel group620substantially includes two sub-pixels. In the present embodiment, the display region is formed by arraying the sub-pixel group620substantially including two sub-pixels in a lattice pattern, as in the other embodiments described above.

The transistors103-1,103-2are respectively formed in TFT channels104-1,104-2. In this example, the TFT channels104-1,104-2each include a p-doped region, and a channel region is interposed between these regions.

On the TFT channel104-1,104-2, the insulating layer105is formed and gates107-1,107-2are formed with the insulating layer105interposed therebetween. The gates107-1,107-2are gates of the transistors103-1,103-2. In this example, the transistors103-1,103-2are p-channel TFTs.

The insulating film108covers the two transistors103-1,103-2. The first wiring layer610is formed on the insulating film108.

The vias111s1,111d1are provided between the p-type doped region of the transistor103-1and the first wiring layer610. The vias111s2,111d2are provided between the p-type doped region of the transistor103-2and the first wiring layer610.

The first wiring layer610includes wiring portions610s1,610s2,610d1,610d2. The wiring portion610s1is connected to a region corresponding to the source electrode of the transistor103-1by the via111s1. The wiring portion610s2is connected to a region corresponding to the source electrode of the transistor103-2by the via111s2. The wiring portion610d1is connected to a region corresponding to the drain electrode of the transistor103-1by the via111d1. The wiring portion610d2is connected to a region corresponding to the drain electrode of the transistor103-2by the via111d2.

The first interlayer insulating film112covers the insulating film108, the first wiring layer610, and connecting portions615a1,615a2.

The flattening film214is formed on the first interlayer insulating film112. The plugs616a1,616a2are embedded in the flattening film214, and the flattening film214and the plugs616a1,616a2each include a surface in the same plane in an XY plane view. This surface faces the surface on the first interlayer insulating film112side. That is, the flattening film214is provided between the plugs616a1,616a2.

The connecting portion615a1is provided between the plug616a1and the wiring portion610d1. The connecting portion615a1electrically connects the plug616a1and the wiring portion610d1. The connecting portion615a2is provided between the plug616a2and the wiring portion610d2. The connecting portion615a2electrically connects the plug616a2and the wiring portion610d2.

The semiconductor layer650is provided on the flattening film214and the plugs616a1,616a2.

The semiconductor layer650includes a p-type semiconductor layer653, the light-emitting layer652, and an n-type semiconductor layer651. The semiconductor layer650is layered in the order of the p-type semiconductor layer653, the light-emitting layer652, and the n-type semiconductor layer651from the side of the plugs616a1,616a2toward the side of the light-emitting surfaces651S1,651S2. The plugs616a1,616a2are connected to the p-type semiconductor layer653.

The second interlayer insulating film (second insulating film)656covers the flattening film214and the plugs616a1,616a2. The second interlayer insulating film656covers a portion of the semiconductor layer650. Preferably, the second interlayer insulating film656covers a surface of the n-type semiconductor layer651, excluding the light-emitting surfaces (exposed surfaces)651S1,651S2of the semiconductor layer650. The second interlayer insulating film656covers a lateral surface of the semiconductor layer650. The second interlayer insulating film656is preferably a white resin. A material similar to that of the second interlayer insulating film156in the other embodiments described above is used as the white resin.

Openings658-1,658-2are formed in portions of the semiconductor layer650not covered by the second interlayer insulating film656. The openings658-1,658-2are formed at positions corresponding to the light-emitting surfaces651S1,651S2. The light-emitting surfaces651S1,651S2are formed in distant positions on the n-type semiconductor layer651. The light-emitting surface651S1is provided on the n-type semiconductor layer651at a position closer to the transistor103-1. The light-emitting surface651S2is provided on the n-type semiconductor layer651at a position closer to the transistor103-2.

The openings658-1,658-2have, for example, square or rectangular shapes in an XY plane view. The shape is not limited to rectangular, and may be circular, elliptical, or polygonal such as hexagon. The light-emitting surfaces651S1,651S2also have square, rectangular, other polygonal, or circular shape, or the like in an XY plane view. The shape of the light-emitting surfaces651S1,651S2may be similar to or different from the shape of the openings658-1,658-2.

The second wiring layer660is provided on the second interlayer insulating film656. The second wiring layer660includes a wiring portion660k. The wiring portion660kis provided between the openings658-1,658-2. The second interlayer insulating film656provided with the wiring portion660kis provided on the n-type semiconductor layer651. The wiring portion660kis connected to a ground line (not illustrated). Note that, inFIG.31, the reference sign of this second wiring layer660is denoted in conjunction with the reference sign of the wiring portion660k, and the second wiring layer660includes the wiring portion660k. The same applies toFIG.34described below.

A light-transmitting electrode659kis provided over each of the light-emitting surfaces651S1,651S2exposed from the openings658-1,658-2. The light-transmitting electrode659kis provided over the wiring portion660k. The light-transmitting electrode659kis provided between the light-emitting surface651S1and the wiring portion660k, and is provided between the light-emitting surface651S2and the wiring portion660k. The light-transmitting electrode659kelectrically connects the light-emitting surfaces651S1,651S2and the wiring portion660k. The light-transmitting electrode659kis formed of, for example, an ITO film.

As described above, the light-transmitting electrode659kis connected to the light-emitting surfaces651S1,651S2exposed from the openings658-1,658-2. Therefore, electrons supplied from the light-transmitting electrode659kare respectively supplied to the n-type semiconductor layer651from the exposed light-emitting surfaces651S1,651S2. On the other hand, holes are respectively supplied to the p-type semiconductor layer653via the plugs616a1,616a2.

The transistors103-1,103-2are drive transistors of adjacent sub-pixels and are driven sequentially. Accordingly, holes supplied from either one of the two transistors103-1,103-2are injected into the light-emitting layer652, electrons supplied from the wiring portion660kare injected into the light-emitting layer652, and the light-emitting layer652emits light.

The opening658-1and the light-emitting surface651S1are provided in positions closer to the transistor103-1than the position of the transistor103-2. Therefore, when the transistor103-1is turned on, holes are injected via the wiring portion610d1, the connecting portion615a1, and the plug616a1, causing the light-emitting surface651S1to emit light.

The opening658-2and the light-emitting surface65152are provided in positions closer to the transistor103-2than the position of the transistor103-1. Therefore, when the transistor103-2is turned on, the light-emitting surface651S2emits light via the wiring portion610d2, the connecting portion615a2, and the plug616a2.

Outer peripheries of the plugs616a1,616a2are located within an outer periphery of the semiconductor layer650. That is, an area of the plugs616a1,616a2in an XY plane view is set smaller than an area of the semiconductor layer650in an XY plane view. Nevertheless, the plugs616a1,616a2also function as light-reflecting plates, as follows.

An outer periphery of the light-emitting surface651S1is located within the outer periphery of the plug616a1includes in an XY plane view. An outer periphery of the light-emitting surface651S2is located within the outer periphery of the plug616a2in an XY plane view.

In the present embodiment, a resistance of the n-type semiconductor layer651and the p-type semiconductor layer653suppresses a drift current flowing in a direction parallel to the XY plane. Therefore, the electrons injected from the light-emitting surfaces651S1,651S2and the holes injected from the plugs616a1,616a2travel substantially straight. An area outside the light-emitting surfaces651S1,651S2is rarely an emission source. Accordingly, with the outer periphery of the light-emitting surface651S1located within the outer periphery of the plug616a1, and the outer periphery of the light-emitting surface651S2located within the outer periphery of the plug616a2, the plugs616a1,616a2function as light-reflecting plates. That is, the light scattering downward from the semiconductor layer650is reflected by the plugs616a1,616a2toward the side of the light-emitting surfaces651S1,651S2. The plugs616a1,616a2function as light-blocking plates. The light scattering downward from the semiconductor layer650is inhibited from reaching the transistors103-1,103-2by the plugs6161a1,616a2.

A manufacturing method of the image display device according to the present embodiment will now be described.

FIGS.32A to33Bare schematic cross-sectional views illustrating the manufacturing method of the image display device of the present embodiment.

As illustrated inFIG.32A, the semiconductor growth substrate1194and a circuit substrate6100on which the plugs616a1,616a2are formed are prepared. The semiconductor growth substrate1194includes the crystal growth substrate1001, the buffer layer1140, and the semiconductor layer1150. The semiconductor growth substrate1194includes the semiconductor layer1150formed with the buffer layer1140provided on the crystal growth substrate1001interposed therebetween. The semiconductor layer1150includes the n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153. The n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153are layered in the order of the n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153from the buffer layer1140side. The semiconductor layer1150is formed by epitaxial growth by MOCVD or the like as in the other embodiments described above.

The exposed surface of the p-type semiconductor layer1153is bonded, by wafer bonding, to the flat surface of the plugs616a1,616a2and the flattening film214formed on the circuit substrate6100.

The processes illustrated inFIG.16AtoFIG.18Bof the second embodiment can be used for the procedure of forming the plugs616a1,616a2and the connecting portions615a1,615a2on the circuit substrate6100. The circuit substrate6100has the same circuit configuration as that of the first embodiment and the third embodiment, and has the same structure as already described in most portions. In the following, the reference signs for the first wiring layer610and the wiring portions included in the first wiring layer610are replaced and the other components are the same as those in the first embodiment and the third embodiment, and thus detailed descriptions will be omitted as appropriate.

As illustrated inFIG.32B, after wafer bonding, the crystal growth substrate1001illustrated inFIG.32Ais removed.

As illustrated inFIG.33A, the semiconductor layer1150illustrated inFIG.32Bis etched by RIE or the like to form the semiconductor layer650.

As illustrated inFIG.33B, the second interlayer insulating film656that covers the flattening film214, the plugs616a1,616a2, and the semiconductor layer650is formed.

The second wiring layer660is formed on the second interlayer insulating film656, and the wiring portion660kand the like are formed by etching.

A portion of the second interlayer insulating film656at a position corresponding to that of the light-emitting surface651S1is removed, forming the opening658-1. A portion of the second interlayer insulating film656at a position corresponding to that of the light-emitting surface651S2is removed, forming the opening658-2.

The light-emitting surfaces651S1,651S2exposed from the second interlayer insulating film656are each roughened. Subsequently, the light-transmitting electrode659kis formed on the second interlayer insulating film656. The light-transmitting electrode659kelectrically connects the n-type semiconductor layer651and the wiring portion660kvia the light-emitting surface651S1. The light-transmitting electrode659kelectrically connects the n-type semiconductor layer651and the wiring portion660kvia the light-emitting surface651S2.

In this manner, the sub-pixel group620including the semiconductor layer650that uses the two light-emitting surfaces651S1,651S2in common is formed.

In the present example, the two light-emitting surfaces651S1,651S2are provided in one semiconductor layer650, but the number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces can be provided on one semiconductor layer650. As an example, one or two columns of sub-pixels may be realized by a single semiconductor layer650. As a result, as described below, a recombination current that does not contribute to light emission per light-emitting surface can be reduced and the effect of realizing a finer light-emitting element can be increased.

Modified Example

FIG.34is a schematic cross-sectional view illustrating a portion of an image display device according to a modified example of the present embodiment.

The present modified example differs from the sixth embodiment described above in that two n-type semiconductor layers6651a1,6651a2are provided on the light-emitting layer652. In other respects, components that are the same as those of the sixth embodiment are denoted by the same reference signs, and detailed descriptions thereof will be omitted as appropriate.

As illustrated inFIG.34, the image display device of the present modified example includes a sub-pixel group620a. The sub-pixel group620aincludes a semiconductor layer650a. The semiconductor layer650aincludes the p-type semiconductor layer653, the light-emitting layer652, and the n-type semiconductor layers6651a1,6651a2. The p-type semiconductor layer653, the light-emitting layer652, and the n-type semiconductor layers6651a1,6651a2are layered in this order from the side of the first interlayer insulating film112toward the side of light-emitting surfaces6651S1,6651S2.

The n-type semiconductor layers6651a1,6651a2are distant in the X-axis direction on the light-emitting layer652. The second interlayer insulating film656is provided between the n-type semiconductor layers6651a1,6651a2, and the n-type semiconductor layers6651a1,6651a2are separated by the second interlayer insulating film656.

The n-type semiconductor layers6651a1,6651a2have substantially the same shape in an XY plane view, and the shape thereof is substantially square or rectangular, and may be another polygonal shape, circular, or the like.

The n-type semiconductor layers6651a1,6651a2respectively include light-emitting surface6651S1,6651S2. The light-emitting surfaces6651S1,6651S2are surfaces of the n-type semiconductor layers6651a1,6651a2respectively exposed by the openings658-1,658-2.

The light-emitting surfaces6651S1,6651S2have substantially the same shape in an XY plane view and have a substantially square shape or the like, similar to the shape of the light-emitting surfaces in the sixth embodiment. The shape of the light-emitting surfaces6651S1,6651S2is not limited to a rectangular shape such as in the present embodiment, and may be circular, elliptical, or polygonal such as hexagonal. The shape of the light-emitting surfaces6651S1,6651S2may be similar to or different from the shape of the openings658-1,658-2.

The light-transmitting electrode659kis provided on each of the light-emitting surfaces6651S1,6651S2. The light-transmitting electrode659kis also provided on the wiring portion660k. The light-transmitting electrode659kis provided between the wiring portion660kand the light-emitting surface6651S1, and is provided between the wiring portion660kand the light-emitting surface6651S2. The light-transmitting electrode659kelectrically connects the wiring portion660kand the light-emitting surfaces6651S1,6651S2.

A manufacturing method of the present modified example will now be described.

FIGS.35A and35Bare schematic cross-sectional views illustrating the manufacturing method of the image display device of the present modified example.

In the present modified example, until the bonding of the circuit substrate6100on which the plugs616a1,616a2and the connecting portions615a1,615a2are formed to the semiconductor layer1150, the same processes as those described inFIG.32AandFIG.32Bin the sixth embodiment are applied. In the following, the processes following the process described inFIG.32Bwill be described.

As illustrated inFIG.35A, in the present modified example, the semiconductor layer1150illustrated inFIG.32Bis etched to form the light-emitting layer652and the p-type semiconductor layer653. Etching is further performed to form the two n-type semiconductor layers6651a1,6651a2.

The n-type semiconductor layers6651a1,6651a2may be formed by deeper etching. For example, the etching for forming the n-type semiconductor layers6651a1,6651a2may be performed to a depth that reaches inside the light-emitting layer652and inside the p-type semiconductor layer653. In a case in which the n-type semiconductor layers are thus deeply etched, an etching position of the n-type semiconductor layer1151is preferably separated from outer peripheries of the light-emitting surfaces6651S1,6651S2of the n-type semiconductor layer described below by 1 μm or more. By separating the etching position from the outer peripheries of the light-emitting surfaces6651S1,6651S2, a recombination current can be suppressed.

As illustrated inFIG.35B, an interlayer insulating film covering the flattening film214, the plugs616a1,616a2, and the semiconductor layer650ais formed. The second wiring layer660is formed on the second interlayer insulating film656, and the wiring portion660kand the like are formed by etching.

The openings658-1,658-2are each formed by removing a portion of the second interlayer insulating film656at a position corresponding to the respective light-emitting surfaces6651S1,6651S2. The light-emitting surfaces6651S1,6651S2of the p-type semiconductor layer exposed by the openings658-1,658-2are each roughened. Subsequently, the light-transmitting electrode659kis formed.

In this manner, the sub-pixel group620aincluding the two light-emitting surfaces6651S1,6651S2is formed.

In the case of the present modified example as well, as in the case of the sixth embodiment, the number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces may be provided on one semiconductor layer650a.

Effects of the image display device of the present embodiment will now be described.

FIG.36is a graph showing features of a pixel LED element.

The vertical axis inFIG.36indicates light emission efficiency (%). The horizontal axis indicates the current density of the current flowing in the pixel LED element by a relative value.

As shown inFIG.36, in regions where the relative value of the current density is less than 1.0, the light emission efficiency of the pixel LED element is substantially constant or increases monotonically. In regions where the relative value of the current density is greater than 1.0, the light emission efficiency decreases monotonically. That is, in the pixel LED element, there exists an appropriate current density that results in the greatest light emission efficiency.

It is expected that a highly efficient image display device is realized by suppressing the current density to the extent that sufficient brightness can be acquired from the light-emitting element. Nevertheless, it is shown byFIG.36that, at low current densities, the light emission efficiency tends to decrease as the current density decreases.

For example, as described in the first embodiment to the fifth embodiment, the light-emitting elements are formed by individually separating all layers of the semiconductor layer1150including the light-emitting layers by etching or the like. At this time, a bonding surface between the light-emitting layers and the n-type semiconductor layer is exposed at an end portion. Similarly, a bonding surface between the light-emitting layers and the p-type semiconductor layer is exposed at an end portion.

If such an end portion is present, electrons and holes are recombined at the end portion. On the other hand, such a recombination does not contribute to light emission. Recombination at the end portion occurs almost regardless of the current flowing in the light-emitting element. Recombination is thought to occur depending on a length, at the end portion, of the bonding surface that contributes to light emission.

When two cubic-shaped light-emitting elements having the same dimensions are made to emit light, recombination can occur at a total of eight end portions because the end portions are formed in four directions for each light-emitting element.

In contrast, in the present embodiment, in the semiconductor layers650,650aincluding two light-emitting surfaces, there are four end portions. Because the region between the openings658-1,658-2has few injections of electrons and holes and hardly contributes to light emission, the number of end portions contributing to light emission can be regarded as six. Thus, in the present embodiment, the number of end portions of the semiconductor layer is substantially reduced, making it possible to reduce the recombination that does not contribute to light emission and reduce the drive current by the reduction in the recombination current.

For high definition and the like, in a case in which the distance between sub-pixels is reduced or a case in which the current density is relatively high or the like, the distance between the light-emitting surfaces651S1,651S2is shortened in the sub-pixel group620of the sixth embodiment. In this case, when the p-type semiconductor layer653is shared, there is a risk that a portion of the electrons injected on the side of the adjacent light-emitting surface may be diverted, causing the light-emitting surface on the side not being driven to emit a small amount of light. In the modified example, the p-type semiconductor layer is separated from the light-emitting surfaces, making it possible to reduce the occurrence of small light emission in the light-emitting surface on the side not being driven.

In the present embodiment, the semiconductor layer including the light-emitting layer is layered in the order of the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer from the side of the first interlayer insulating film112, and the exposed surface of the p-type semiconductor layer is roughened, which is preferred from the viewpoint of improving the light emission efficiency. As in the other embodiments described above, instead of the layered order of the p-type semiconductor layer and the n-type semiconductor layer, the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer may be layered in this order.

Specific examples of the respective sub-pixels and sub-pixel groups of the image display devices according to the embodiments described above have been described. Each of the specific examples is merely an example, and other configuration examples can be obtained by combining the configurations, processes, and procedures of these embodiments as appropriate. For example, in the first embodiment, the p-type semiconductor layer can be used as the light-emitting surface instead of the n-type semiconductor layer and, in the second embodiment, the n-type semiconductor layer can be used as the light-emitting surface instead of the p-type semiconductor layer.

Seventh Embodiment

The image display device described above can be, as an image display module including an appropriate number of pixels, a computer display, a television, a mobile terminal such as a smartphone, or a car navigation system, for example.

FIG.37is a block diagram illustrating an image display device according to the present embodiment.

A main portion of a configuration of a computer display is illustrated inFIG.37.

As illustrated inFIG.37, an image display device701includes an image display module702. The image display module702is, for example, an image display device provided with the configuration of the first embodiment described above. The image display module702includes the display region2in which the plurality of sub-pixels including the sub-pixels20-1,20-2are arrayed, the row selection circuit5, and the signal voltage output circuit7.

The image display device701further includes a controller770. The controller770inputs control signals separated and generated by an interface circuit (not illustrated) to control the drive and drive sequence of each sub-pixel with respect to the row selection circuit5and the signal voltage output circuit7.

Modified Example

The image display device described above can be, as an image display module including an appropriate number of pixels, a computer display, a television, a mobile terminal such as a smartphone, or a car navigation system, for example.

FIG.38is a block diagram illustrating an image display device according to a modified example of the present embodiment.

FIG.38illustrates a configuration of a high-definition, flat-screen television.

As illustrated inFIG.38, an image display device801includes an image display module802. The image display module802is, for example, the image display device1provided with the configuration of the first embodiment described above. The image display device801includes a controller870and a frame memory880. The controller870controls the drive sequence of each sub-pixel in the display region2on the basis of the control signal supplied by a bus840. The frame memory880stores the display data of one frame and is used for processing, such as smooth video playback.

The image display device801includes an I/O circuit810. The I/O circuit810provides an interface circuit and the like for connection to an external terminal, device, or the like. The I/O circuit810includes, for example, a universal serial bus (USB) interface for connecting an external hard disk device or the like, and an audio interface.

The image display device801includes a receiving unit820and a signal processing unit830. The receiving unit820is connected with an antenna822to separate and generate necessary signals from radio waves received by the antenna822. The signal processing unit830includes a digital signal processor (DSP), a central processing unit (CPU), and the like, and signals separated and generated by the receiving unit820are separated and generated into image data, audio data, and the like by the signal processing unit830.

Other image display devices can be made as well by using the receiving unit820and the signal processing unit830as high-frequency communication modules for transmission/reception of mobile phones, Wi-Fi, global positioning system (GPS) receivers, and the like. For example, an image display device provided with an image display module with an appropriate screen size and resolution may be made into a mobile information terminal such as a smartphone or a car navigation system.

The image display module in the case of the present embodiment is not limited to the configuration of the image display device in the first embodiment, and may be the configuration of a modified example or other embodiment.

FIG.39is a perspective view schematically illustrating the image display devices according to the first to sixth embodiments and the modified examples thereof.

As illustrated inFIG.39, the light-emitting circuit portion172including the plurality of sub-pixels is provided on the circuit substrate100. The color filter180is provided on the light-emitting circuit portion172. Note that, in the seventh embodiment, the structures including the circuit substrate100, the light-emitting circuit portion172, and the color filter180are the image display modules702,802and are incorporated into the image display devices701,801.

According to the embodiments described above, an image display device manufacturing method and an image display device that reduce a transfer process of a light-emitting element and improve yield are realized.

While several embodiments of the present invention have been described above, these embodiments have been presented by way of example, and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and variations thereof are included in the scope and spirit of the invention, and are within the scope of the invention described in the claims and equivalents thereof. Further, each of the aforementioned embodiments may be implemented in combination with each other.