Patent ID: 12250805

DETAILED DESCRIPTION

Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

It shall be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

The terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limited to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be further understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Unless the context indicates otherwise, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientations, layouts, locations, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

In the present disclosure, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device. Specifically, semiconductor devices of embodiments of the present disclosure may be dynamic random-access memory devices.

FIG.1Ais a schematic plane view of a semiconductor device1in accordance with some embodiments of the present disclosure.FIG.1Bis a schematic cross-sectional view illustrating the semiconductor device1taken along an A-A line shown inFIG.1A.FIG.1Cis a schematic cross-sectional view illustrating the semiconductor device1taken along a B-B line shown inFIG.1A.

It should be noted that, in the description of the present disclosure, above (or up) corresponds to the direction of the arrow of the direction Z, and below (or down) corresponds to the opposite direction of the arrow of the direction Z.

Referring toFIG.1A, the semiconductor device1includes a plurality of active regions105defined in a semiconductor substrate. The plurality of active regions105include doped regions107. The plurality of active regions105may be surrounded by an isolation layer103. For simplicity, the isolation layer103is not shown inFIG.1A.

In some embodiments, the semiconductor substrate may be a semiconductor wafer. The semiconductor substrate may be a silicon substrate. Alternatively, the semiconductor substrate may comprise another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or combinations thereof. In other embodiments, the semiconductor substrate may include for example, an insulating layer such as a SiO2or a Si3N4layer in addition to a semiconductor substrate portion. Thus, the term substrate also includes silicon-on-glass, silicon-on-sapphire substrates. Also, the semiconductor substrate may be any other base on which a layer is formed, for example, a glass or metal layer. Accordingly, the substrate may be a wafer such as a blanket wafer or may be a layer applied to another base material, e.g., an epitaxial layer grown onto a lower layer.

Each of the plurality of active regions105may include a rectangular shape or a square shape. Each of the plurality of active regions105includes a sub-active region1051and a sub-active region1052. The sub-active region1051is separated from the sub-active region1052by a separation channel109. The sub-active region1051and the sub-active region1052are symmetric. Each of the sub-active regions has substantially a same length, width, and height. Each of the sub-active regions has substantially a same top surface area. Since each active region105has two sub-active regions, the active region105has double bit capacity. Also, the rectangular shape or the square shape of the active region105could increase the surface area of the active region105. In addition, the double bit capacity of the active region105would be stable and balanced due to the same top surface area.

Each of the plurality of active regions105may include four corners or chamfers. The corners are angled. The corners are right angles. The adjacent two corners are symmetric.

FIG.1Bis a schematic cross-sectional view illustrating the semiconductor device1taken along an A-A line shown inFIG.1A. The active regions105are formed in a semiconductor substrate101. Each of the active regions105includes the sub-active region1051and the sub-active region1052. The separation channel109separates the sub-active region1051from the sub-active region1052. The sub-active region1051is defined by the separation channel109and the isolation layer103. The sub-active region1052is defined by the separation channel109and the isolation layer103.

Each of the active regions105is surrounded by an isolation layer/isolation region103. A depth D2of the separation channel109is substantially identical to a thickness D1of the isolation layer103. The isolation layer103may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. In some embodiments, silicon oxynitride refers to a substance which contains silicon, nitrogen, and oxygen and in which a proportion of oxygen is greater than that of nitrogen. Silicon nitride oxide refers to a substance which contains silicon, oxygen, and nitrogen and in which a proportion of nitrogen is greater than that of oxygen.

The doped region107is disposed in the active region105. A top surface of the doped region107and a top surface of the isolation layer103are substantially coplanar.

FIG.1Cis a schematic cross-sectional view illustrating the semiconductor device1taken along a B-B line shown inFIG.1A.

The isolation layer103is disposed between two active regions105.

FIG.1Dis a schematic plane view of a semiconductor device1′ in accordance with some embodiments of the present disclosure. The depicted structure ofFIG.1Dis similar to the structure depicted inFIG.1A, except that corners or chamfers105C1,105C2,105C3,105C4of the active region105ofFIG.1Dare obtuse angles. The corners105C1and105C2of the active region105are symmetric. The corners105C3and105C4of the active region105are symmetric.

FIG.2Ais a schematic plane view of a semiconductor device2in accordance with some embodiments of the present disclosure.FIG.2Bis a schematic cross-sectional view illustrating the semiconductor device2taken along an A-A line shown inFIG.2A.FIG.2Cis a schematic cross-sectional view illustrating the semiconductor device2taken along a B-B line shown inFIG.2A.

Referring toFIG.2A, the semiconductor device2includes a plurality of active regions105defined in a semiconductor substrate. The plurality of active regions105include doped regions107. The plurality of active regions105may be surrounded by an isolation layer103. For simplicity, the isolation layer103is not shown inFIG.2A.

The structures of the active regions105and doped regions107are similar to those of the active regions105and doped regions107illustrated inFIG.1A. In some embodiments, the structures of the active regions105and doped regions107are similar to those of the active regions105and doped regions107illustrated inFIG.1D.

A word line structure201is disposed in a word line trench203. The word line trench203extends over the active regions105. The word line trench203intersects the sub-active region1051and the sub-active region1052of each of the active regions105.

The word line structure201is disposed in the word line trench203. The word line structure201includes a word line insulating layer205and a word line capping structure209. The word line structure201intersects the active regions105. The word line structure201intersects the respective sub-active regions1051and the respective sub-active regions1052of the active regions105. There are two word line structures201intersecting one active region105. In some embodiments, there are three word line structures201intersecting one active region105.

FIG.2Bis a schematic cross-sectional view illustrating the semiconductor device2taken along an A-A line shown inFIG.2A. The active regions105are formed in a semiconductor substrate101. Each of the active regions105includes the sub-active region1051and the sub-active region1052. The separation channel109separates the sub-active region1051from the sub-active region1052. A depth D2of the separation channel109is substantially identical to a thickness D1of the isolation layer103. The sub-active region1051and the sub-active region1052of the active region105are sandwiched by two word line structures201.

The doped region107is disposed in the active region105. A top surface of the doped region107and a top surface of the isolation layer103are substantially coplanar.

The word line structure201is disposed in the word line trench203and adjacent to the active region105. The word line structure201includes the word line insulating layer205, a word line electrode207, and the word line capping structure209. A thickness D3of the word line structure201is less than the thickness D1of the isolation layer103. In some embodiments, the thickness D3of the word line structure201may be identical to the thickness D1of the isolation layer103.

The word line insulating layer205covers inner side surfaces of the word line trench203. The word line electrode207is disposed on the word line insulating layer205. The word line capping structure209is disposed on the word line electrode207. The word line insulating layer205, the word line electrode207, and the word line capping structure209are disposed in the word line trench203. A top surface of the word line capping structure209and the top surface of the isolation layer103are substantially coplanar.

FIG.2Cis a schematic cross-sectional view illustrating the semiconductor device2taken along a B-B line shown inFIG.2A.

The isolation layer103is disposed between two active regions105.

FIGS.3to25illustrate stages of a method of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of the aspects of the present disclosure. In some embodiments, the semiconductor device1inFIGS.1A,1B,1C, and1D may be manufactured by the operations described below with respect toFIGS.3to12. In some embodiments, the semiconductor device2inFIGS.2A,2B, and2Cmay be manufactured by the operations described below with respect toFIGS.3to25.

As shown inFIG.3, a substrate101having a top surface101-1is provided. The substrate101may be formed of, for example, silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium phosphide, indium gallium phosphide, or any other IV-IV, III-V or I-VI semiconductor material.

FIGS.4to6illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance withFIG.3.

As shown inFIG.4, a plurality of active regions105are defined in the substrate101through lithographic processes. The plurality of active regions105may be patterned by multi-layer hard masks. The multi-layer hard masks may include a plurality of dielectric layers. The plurality of active regions105may be defined in one step. In some embodiments, the plurality of active regions105may be defined in sequence.

The plurality of active regions105may have bar shapes. The plurality of active regions105may be parallel to each other. The shapes of the plurality of active regions105may be patterned as a rectangle or a square, and top surface areas (i.e., island areas) of the plurality of active regions105would be increased. In some embodiments, each active region105may have four chamfers with obtuse angles.

As shown inFIGS.5and6, an isolation layer/region103may be formed in the substrate101and the plurality of active regions105of the substrate101may be defined by the isolation layer103. The isolation region103may be formed through an STI (shallow trench isolation) process. A photolithography process may be performed to pattern the substrate101to define positions of the plurality of active regions105. An etch process may be performed after the photolithography process to form a plurality of isolation trenches in the substrate101. After the etch process, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate, may be used to fill the plurality of isolation trenches by a deposition process. A planarization process, such as chemical mechanical polishing, may be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps and conformally form the isolation layer103and the plurality of active regions105. The isolation layer103has a depth D1. For simplicity, the isolation layer103is not shown inFIG.3.

FIG.7illustrates, in a schematic top-view diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIGS.8and9illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance withFIG.7. For simplicity, the isolation layer103is not shown inFIG.7.

As shown inFIGS.7to9, a plurality of doped regions107are formed in the plurality of active regions105. The plurality of doped regions107are formed by an implantation process using a dopant. The plurality of doped regions107may have a dopant concentration ranging from about 1017atoms/cm3to about 1019atoms/cm3.

In some embodiments, the doped regions107may be doped with an N-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb). In some other embodiments, the doped regions107may be doped with a P-type dopant such as boron (B) or indium (In). In some embodiments, the doped regions107may be doped with dopants or impurity ions having the same or different conductivity types.

FIG.10illustrates, in a schematic top-view diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIGS.11and12illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance withFIG.10. For simplicity, the isolation layer103is not shown inFIG.10.

A photolithography process may be performed to pattern an active region105to define a sub-active region1051and a sub-active region1052of the active region105. An etch process may be performed after the photolithography process to form a separation channel109in the active region105. Subsequently, the photolithography process and the etching process may be performed to pattern another active region105to form a separation channel109, a sub-active region1051, and a sub-active region1052of said active region105. A size (i.e., a length, a width, a height) of the sub-active region1051is substantially the same as a size of the sub-active region1052. The sub-active region1051and the sub-active region1052are symmetric. Said active region105has double bit capacity due to the sub-active region1051and the sub-active region1052. The sub-active regions1051and the sub-active regions1052of the plurality of active regions105are formed in sequence. Through the above operations, a large etching window could be obtained. Maximum island areas of the sub-active regions1051and the sub-active regions1052of the plurality of active regions105would be obtained. A depth of each separation channel109may be exactly controlled without etching errors. That is, over-etching or insufficient etching could be avoided. Accordingly, cut/space depth bias hard control defects due to micro etching loading effect would be eliminated.

In some embodiments, a depth bias resulting from an etching process may be controlled between 0 to 25%. The depth bias resulting from an etching process may be controlled between 0 to 15%. The depth bias resulting from an etching process may be controlled between 0 to 5%. The depth bias resulting from an etching process may be controlled substantially as 0. Compared with the embodiments, a depth bias formed by a conventional etching process normally exceeds 25%.

As shown inFIGS.11and12, the separation channel109has a depth D2. The depth D2of the separation channel109is substantially the same as the depth D1of the isolation layer103. A top surface of the isolation layer103and a top surface of the sub-active region1051or the sub-active region1052of the active region105are substantially coplanar. The semiconductor device1is formed. The semiconductor device1has double bit capacity, and the active region105still keeps its dimension without increasing its length or width.

FIG.13illustrates, in a schematic top-view diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIGS.14and15illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance withFIG.13. For simplicity, the isolation layer103is not shown inFIG.13.

As shown inFIGS.13to15, a plurality of word line trenches203are formed in the substrate101. A photolithography process may be performed to pattern the substrate101to define positions of the plurality of word line trenches203. An etch process may be performed after the photolithography process to form the plurality of word line trenches203in the substrate101. The plurality of word line trenches203may extend in a direction Y to intersect the plurality of active regions105. One of the plurality of word line trenches203may extend in a direction Y to intersect the sub-active region1051and the sub-active region1052of the active region105. One of the plurality of active regions105may intersect two of the plurality of word line trenches203. In some embodiments, one of the plurality of active regions105may intersect three of the plurality of word line trenches203. A word line may be formed in the substrate101. The word line may be formed in the word line trench203.

As shown inFIG.14, the word line trench203has a depth D3. The depth D3of the word line trench203is less than the depth D1of the isolation layer103. In some embodiments, the depth D3of the word line trench203may be the same as the depth D1of the isolation layer103depending on need.

FIG.16illustrates, in a schematic top-view diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIGS.17and18illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance withFIG.16. For simplicity, the isolation layer103is not shown inFIG.16.

As shown inFIGS.16to17, a plurality of word line insulating layers205are correspondingly formed to conformally cover inner surfaces of the plurality of word line trenches203. In some embodiments, the plurality of word line insulating layers205may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluoride-doped silicate, or the like. Alternatively, in another embodiment, the plurality of word line insulating layers205may be formed of, for example, barium strontium titanate, lead zirconium titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, or the like.

FIG.19illustrates, in a schematic top-view diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIGS.20and21illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance withFIG.19. For simplicity, the isolation layer103is not shown inFIG.19.

As shown inFIGS.19to20, a plurality of word line electrodes207may be correspondingly formed on the plurality of word line insulating layers205in the plurality of word line trenches203. In some embodiments, a metal layer formed of a conductive material, for example, doped polysilicon, a metal, or a metal silicide, may be disposed into the plurality of word line trenches203by a metallization process. After the metallization process, an etch process may be performed on the metal layer to leave a lower portion of the metal layer in the plurality of word line trenches203. The plurality of word line electrodes207may be correspondingly formed on the plurality of word line insulating layers205in the plurality of word line trenches203. The metal may be, for example, aluminum, copper, tungsten, cobalt, or an alloy thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like.

FIG.22illustrates, in a schematic top-view diagram, part of the flow of fabricating the semiconductor device in accordance with one embodiment of the present disclosure.FIGS.23and24illustrate, in schematic cross-sectional diagrams, part of the flow of fabricating the semiconductor device in accordance withFIG.22. For simplicity, the isolation layer103is not shown inFIG.22.

As shown inFIGS.22to23, a plurality of word line capping structures209may be correspondingly formed on the plurality of word line electrodes207in the plurality of word line trenches203. The plurality of word line capping structures209may correspondingly fill the plurality of word line trenches203. Top surfaces of the word line capping structures209may be at the same vertical level as a vertical level of a top surface of the substrate101. The top surface of the word line capping structure209and a top surface of the isolation layer103are substantially coplanar.

Each of the plurality of word line capping structures209may be formed as a stacked layer or a single layer. For example, in the embodiment depicted, the plurality of word line capping structures209may be formed of single layers including barium strontium titanate, lead zirconium titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, or the like. Alternatively, in another embodiment, the plurality of word line capping structures209may be formed of stacked layers. Each stacked layer may include a bottom layer and a top layer. The bottom layers may be correspondingly disposed on the plurality of word line electrodes207. The top layers may be disposed on the bottom layer and the top surfaces of the top layers may be at the same vertical level as that of the top surface of the substrate101. The bottom layers may be formed of, for example, a high dielectric-constant material such as barium strontium titanate, lead zirconium titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, or the like. The top layers may be formed of, for example, a low dielectric-constant material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluoride-doped silicate, or the like. The top layers formed of the low dielectric-constant material may reduce an electric field at the top surface of the substrate101, such that leakage current may be reduced. The plurality of word line trenches203, the plurality of word line insulating layers205, the plurality of word line electrodes207, and the plurality of word line capping structures209together form the plurality of word lines201. The semiconductor device2is formed.

According to the structure, the semiconductor device2may have double bit capacity.

In some embodiments, according to some needs, a dielectric layer may be subsequently formed on the top surface101-1of the substrate101to cover the isolation layer103and the word lines201. The dielectric layer may be a single layer or multiple layers. The dielectric layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), etc. Subsequently, the dielectric layer may be patterned to form an opening, and then, a bit-line structure may be formed in the opening. The bit-line structure may include a bit-line, a bit line hard mask layer and a spacer. The bit-line structure may be electrically connected to the doped region107. The semiconductor device2may additionally include the dielectric layer and the bit-line structure according to some needs.

FIG.25illustrates a flow chart of a method250of manufacturing a semiconductor device in accordance with some embodiments of the present disclosure.

In some embodiments, the method250may include a step S251of providing a semiconductor substrate. For example, as shown inFIG.3, the semiconductor substrate101includes a top surface101-1. The following processes may be performed on the top surface101-1of the semiconductor substrate101.

In some embodiments, the method250may include a step S252of defining a plurality of active regions in the semiconductor substrate by corresponding lithographic operations. For example, as shown inFIGS.4-6, the plurality of active regions105may be patterned by multi-layer hard masks. Shapes of the plurality of active regions105may correspond to shapes of the multi-layer hard masks

In some embodiments, the method250may include a step S253of forming an isolation layer in the semiconductor substrate to surround the plurality of active regions. For example, as shown inFIGS.4-6, the isolation layer103may be formed through an STI (shallow trench isolation) process. The isolation layer103may have a thickness D1. The isolation layer103may separate the plurality of active regions105from one another.

In some embodiments, the method250may include a step S254of defining a first sub-active region and a second sub-active region for each of the plurality of active regions by corresponding lithographic operations and removing a portion of each active region to form a separation channel of each active region, wherein a depth of the separation channel is substantially identical to a thickness of the isolation layer. For example, as shown inFIGS.10-12, one active region105may be patterned by a photolithography process to define the sub-active region1051and the sub-active region1052of the active region105. An etch process may be performed after the photolithography process to form a separation channel109in the active region105. The separation channel109has a depth D2which is substantially identical to the thickness D1of the isolation layer103.

Subsequently, the photolithography process and the etching process may be repeatedly performed to pattern another active region105to form the separation channel109, the sub-active region1051, and the sub-active region1052of said active region105.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.