Patent ID: 12261573

DESCRIPTION

The methods and apparatuses disclosed herein provide operative systems for an amplifier with stacked transconducting cells in “current mode combining”. In one or more embodiments, the system of the present disclosure provides a power amplifier architecture that is more compact (e.g., by comprising a single-input, single-output matching network, for example refer to (M1)520ofFIG.5Aand (M2)530ofFIG.5B) compared to conventional parallel input/output architectures of a similar type (e.g., refer to amplifier100ofFIG.1). As such, the disclosed amplifier architecture allows for a more compact device layout, which reduces chip area and cost. Moreover, the disclosed amplifier architecture reduces the stacked device's gate/base loss mechanism (as compared to the conventional “voltage mode” stacked devices), thereby improving output power and efficiency. Lastly, the disclosed amplifier topology can be extended to multi-stage power amplifiers.

Currently, power amplifiers with current sharing of series stacked transistor devices in “voltage mode combining” have been proposed to create amplifiers with low break-down voltage technology for high-voltage fixed supply systems. These architectures have limitations of the total number of stacked devices due to the stacked device's gate/base resistive losses, thereby limiting efficiency. Moreover, in parallel input/output combining implementations, a large die area is consumed by the combining networks. The disclosed approach is a “current mode” implementation of stacked devices that simplifies the structure to a single-input and single-output matching/combining network, which reduces layout size and alleviates gate/base stacked device losses, thereby improving die size as well as output power and efficiency.

Previous solutions have proposed stacked field-effect transistor (FET) topologies, in which the gates of the stacked devices are loaded with an impedance (i.e., a capacitive division) that allows for the gate voltages to track the source/drain voltages in such a way that the voltage swings across each device are below the device critical break-down voltage. This approach has a limitation in that the gate/base resistive losses provide a leakage path for the RF current, thereby limiting the efficiency. This limitation generally restricts this amplifier approach to FET technology (as opposed to BJT technology), which can have base resistive losses. Furthermore, parallel-input and parallel-output implementations of this topology require a large die area as the combining networks are often implemented as Wilkinson power combiners/dividers (e.g., refer to220and230ofFIG.2). Lastly, the conventional topologies of a voltage mode stacked FET have a strict dependency on performance relative to the absolute value of the gate capacitance and, as such, these topologies are process variation intolerant.

The system of the present disclosure provides a unique way of combining the RF current of devices in cascade (e.g., refer toFIG.5D), while in a cascode (e.g., refer toFIG.5C), current shared direct current (DC) configuration. It should be noted that the term “cascode” is defined herein as and used throughout to mean “a plurality of units with a first unit having the following plurality of units connected on top of the first unit in a ‘stacked’ succession.” Also, the term “cascade” is defined herein as and used throughout to mean “a plurality of units with a first unit having a plurality of other units connected following the first unit in a ‘serial’ succession.” As such, the resulting architecture for the disclosed system will then only require a single input matching network and a single output matching network. Due to the parallel combining of the devices with a single input matching network, the resistive losses of the gate/base can be neglected with a properly designed matching network. Furthermore, due the matching network simplification, die area can be saved with simplistic matching networks. Lastly, for the disclosed architecture, the dependency on the value of gate/base capacitance value on performance is alleviated (e.g., only large DC blocking capacitances are needed for the disclosed architecture, which are process variation tolerant).

In the following description, numerous details are set forth in order to provide a more thorough description of the system. It will be apparent, however, to one skilled in the art, that the disclosed system may be practiced without these specific details. In the other instances, well known features have not been described in detail, so as not to unnecessarily obscure the system.

Embodiments of the present disclosure may be described herein in terms of functional and/or logical components and various processing steps. It should be appreciated that such components may be realized by any number of hardware, software, and/or firmware components configured to perform the specified functions. For example, an embodiment of the present disclosure may employ various integrated circuit components (e.g., memory elements, digital signal processing elements, logic elements, look-up tables, or the like), which may carry out a variety of functions under the control of one or more processors, microprocessors, or other control devices. In addition, those skilled in the art will appreciate that embodiments of the present disclosure may be practiced in conjunction with other components, and that the systems described herein are merely example embodiments of the present disclosure.

For the sake of brevity, conventional techniques and components related to signal amplifiers, and other functional aspects of the overall system may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent example functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in one or more embodiments of the present disclosure.

FIG.1is a schematic circuit diagram of a conventional two-stage amplifier100, in which the second stage (i.e., stage 2) employs stacked devices (e.g., unit element FET devices110a,110b,110c,110d) with parallel-input and parallel-output power combining networks (e.g., an interstage power dividing network120and an output matching/combining network130). In particular, the conventional two-stage amplifier100ofFIG.1utilizes a current-shared stacked-device architecture, in which a high voltage supply (Vs) is divided across a cascading of common-source cells, each with a unit element FET device110a,110b,110c,110d. The power supply voltage (Vs) (e.g., 24 volts) is divided across the drain-to-source of each unit element FET device110a,110b,110c,110dto alleviate voltage breakdown of the unit element FET device110a,110b,110c,110d. A commonly shared DC drain-to-source current (i.e., “current sharing”) exists through each common-source cell and unit element FET device110a,110b,110c,110d. Specifically, the architecture illustrates a two-stage (i.e., stage 1 and stage 2) architecture with a one-to-four stage-to-stage device fan-out. The second stage (i.e., stage 2) of the amplifier100uses a single-input to four-output power splitter (i.e., interstage power dividing network120) and power combiner (i.e., output matching/combining network130) to split and combine the input and output power of the four unit element FET devices110a,110b,110c,110dof the second stage, respectively. It should be noted that for the amplifier100ofFIG.1, the FET devices110a,110b,110c,110dare connected in cascode for the DC supply current (which travels down the devices), and are connected in parallel (not in cascade) for the AC RF signals (e.g., AC RF input and output currents) (which travel across the devices).

FIG.2is an illustration of an exemplary fabricated IC layout200of the conventional two-stage amplifier100ofFIG.1. InFIG.2, the power splitter (i.e., interstage power dividing network120) and the power combiner (i.e., output matching/combining network130) of the amplifier100ofFIG.1are implemented by a Wilkinson-type splitter220and a Wilkinson-type combiner230, respectively. While this architecture illustrates an approach to implement low break-down devices in a high voltage system with the current-sharing stacked FET technique, this architecture has the disadvantageous consequence of consuming large IC area because of the use of power splitters and combiners, which are large in size.

FIG.3is a schematic circuit diagram of a conventional single-stage amplifier300, which employs stacked devices (i.e., unit element FET devices310a,310b,310c,310d) in “voltage mode combining” with a single-input single-output input matching network (M1)320and a single-input single-output output matching network (M2)330. The amplifier300ofFIG.3illustrates a similar architecture to the amplifier100ofFIG.1, in which the high voltage supply is distributed across each drain-to-source of the cascoded unit element FET devices310a,310b,310c,310d, thereby alleviating device break down as well as sharing a common DC current (Idc) through each unit element FET device310a,310b,310c,310d.

In particular,FIG.3illustrates a single-stage amplifier300with a single-input to single-output input matching network (M1)320driving a single unit element transconductance device creating a commonly shared alternating current (AC) current (irf) through each unit element FET device310a,310b,310c,310d. Following the bottom transconducting unit element FET device310dis a cascoded unit element FET device310cwith an optimally tuned gate capacitance (C1) to create a voltage divider between the cascoded unit element FET device's310cdrain-to-gate and gate-to-source capacitance such that the device voltage break down is never exceeded over an RF cycle.

It should be noted that for the amplifier300ofFIG.3, the FET devices310a,310b,310c,310dare connected in cascode for the DC supply current (Idc) (which travels down the devices), and are connected in cascode (not in cascade) for the AC RF signal (irf) (which travels down the devices).

To achieve the desired output power, each cascode unit element FET device gate capacitance (Cn) is scaled for each additional cascode to correspondingly scale the cascode's unit element FET device source impedance (Ropt is a function of Cn), thereby scaling the voltage swings across the unit element FET device310a,310b,310c, as the cascode source voltage swing is proportional to Ropt-irf. As each additional cascode unit element FET device is added310a,310b,310c, Cn correspondingly scales, increasing the voltage swings of the drain, gate, and source of each cascode unit element FET device310a,310b,310c. A single-input to single-output output matching network (M2)330is used to provide NRopt to the drain of the final cascode unit element FET device310a. By this construct, the amplifier300is said to be operating in “voltage mode combining”, as the voltage swings scale with each additional cascode, thereby ensuring that the drain-to-gate and gate-to-source of each unit element FET device310a,310b,310cnever exceeds Vdd/N (which is set as the break-down voltage of a device), while simultaneously producing a large output voltage swing.

For class A operation and at peak input-signal drive for the “voltage mode” amplifier300, the AC current amplitude of irf is Idc, with a peak current magnitude of 2·Idc delivered to the output matching network (M2)330. The AC voltage amplitude of vrf is Vdd with a peak voltage magnitude of 2·Vdd.

FIG.4is an illustration400of class A biasing of “voltage mode combining” of the conventional single-stage amplifier300ofFIG.3. For ideal class A operation of the amplifier300ofFIG.3, as illustrated inFIG.4, the efficiency of the architecture approaches fifty (50) percent (%), neglecting non-ideal losses. As illustrated inFIG.4, the peak drain voltage of the final Nth cascode unit element FET device310ais 2·Vdd providing a large output voltage swing.

Referring back toFIG.3, the voltage mode architecture of the conventional amplifier300has the advantage of having a single-input to single-output input matching network (M1)320and a single-input to single-output output matching network (M2)330, which allow for a reduced IC layout area because they each comprise only a single input and only a single output.

However, there are several disadvantages to this architecture. A first disadvantage of amplifier300is that the previously described “floating gate” capacitive division is possible only in FET technologies that do not have a lossy resistive gate/base. For example, BJT bipolar unit element devices with a resistive base are not viable for this architecture. As such, this topology is limited to complementary-metal-oxide-semiconductor (CMOS) FET type unit element devices (e.g.,310a,310b,310c,310d) only.

A second disadvantage of amplifier300is that due to the Cn path to ground, any resistive losses from the gate allows for power dissipation from the floating gate signal, thereby reducing output power efficiency. Again, this limitation prohibits the use of other resistive gate/base unit element devices.

A third disadvantage of amplifier300is that the architecture's voltage breakdown reliability of each unit element FET device (e.g.,310a,310b,310c,310d) is dependent on strict tuning of the gate capacitance (Cn), thereby presenting reliability concerns over process fabrication variation.

A fourth disadvantage of amplifier300is that the “voltage mode” mechanism of the architecture creates further reliability constraints on the unit element FET device (e.g.,310a,310b,310c,310d) as the voltage swings may be as large as 2·Vdd. Specifically, for bulk CMOS devices, the drain and source to body junction diode for large voltage swings can create non-linear distortion limiting the linear performance of the power amplifier (PA). At extreme cases of large voltage swings, the junction can break down and damage the device. This mechanism often restricts the technology to complementary-metal-oxide-semiconductor-silicon-on-insulator (CMOS-SOI) devices, which alleviate the parasitic body junction diodes for the unit element FET device (e.g.,310a,310b,310c,310d). As such, conventional amplifiers100,300employing stacked devices with power combining networks, or “voltage mode” combining, have strict limitation of IC layout area or reliability, thereby motivating the design of the system of the present disclosure, which alleviates these constraints.

FIGS.5A and5Btogether are a schematic circuit diagram of the disclosed single-ended single-stage “current mode” amplifier500, in accordance with at least one embodiment of the present disclosure. The disclosed amplifier500utilizes a DC cascode of transconducting cells510a,510b,510c,510dsharing a common current (Idc), and splitting the power supply voltage (Vdd) across the transconducting cells510a,510b,510c,510d, thereby reducing voltage reliability concerns. The amplifier500has a parallel RF input signal (RFIN) control while summing the cascade output RF current (IRF_OUT) of each of the transconducting cells510a,510b,510c,510d, thereby defining the amplifier500as “current mode”. The present disclosed amplifier500alleviates the previously described concerns of large IC layout area power splitting/combining networks as single input/output matching networks (e.g., a single-input single-output input matching network (M1)520and a single-input single-output output matching network (M2)530) may be utilized, and alleviates voltage swing reliability concerns as no large voltage swings are present.

The disclosed amplifier500utilizes a cascode stack of ‘N’ number of unit element transconducting cells510a,510b,510c,510d, which each take as an input: a supply current (Idc), an AC RF input current (IRF_IN), and an RF input signal (RFIN); and each produce as an output: a DC current (Idc) and an AC RF output current (IRF_OUT). The transconducting cells510a,510b,510c,510dare cascoded in terms of the DC input and output current, such that a common current (Idc) is shared amongst each of the transconducting cells510a,510b,510c,510d, and a DC supply voltage drop of Vdd/N is across each of the transconducting cells510a,510b,510c,510d. The transconducting cells510a,510b,510c,510dare cascaded such that each transconducting cell's output current (IRF_OUT) is the input to the following cascaded transconducting cell's input current (IRF_IN). An input signal source (Vin) (along with a source resistor (Rs)) is followed by an input matching network (M1)520, which drives each transconducting cell's RF input signal (RFIN) in parallel. The final output current (IRF_OUT) of the last transconducting cell510dis applied to an output matching network (M2)520to deliver power to a load impedance (RL).

FIG.5Cis a schematic circuit diagram of the disclosed single-stage “current mode” amplifier500ofFIG.5Adenoting the cascode connection of the transconducting cells510a,510b,510cfor the DC supply current (Idc), in accordance with at least one embodiment of the present disclosure. As previously mentioned above, the term “cascode” is defined herein as and used throughout to mean “a plurality of units (e.g., transconducting cells) with a first unit having the following plurality of units connected on top of the first unit in a ‘stacked’ succession.”

FIG.5Dis a schematic circuit diagram of the disclosed single-stage “current mode” amplifier500ofFIG.5Adenoting the cascade connection of the transconducting cells510a,510b,510cfor the AC RF input current (IRF_IN) and output current (IRF_OUT), in accordance with at least one embodiment of the present disclosure. As previously mentioned above, the term “cascade” is defined herein as and used throughout to mean “a plurality of units (e.g., transconducting cells) with a first unit having a plurality of other units connected following the first unit in a ‘serial’ succession.”

FIG.5Eis a schematic circuit diagram of the disclosed single-stage “current mode” amplifier500ofFIG.5Ashowing the input matching network (M1)520driving each transconducting cell's510a,510b,510cRF input signal (RFIN) in parallel, in accordance with at least one embodiment of the present disclosure.

FIG.5Fis a flow chart showing the disclosed method for505operation of the disclosed single-ended single-stage “current mode” amplifier (e.g., amplifier500inFIGS.5A and5B), in accordance with at least one embodiment of the present disclosure. At the start515of the disclosed method505, a DC supply current (Idc), an AC RF input current (IRF_IN), and an RF input signal (RFIN) are all inputted into each transconducting cell of a plurality of transconducting cells525. Also, each of the transconducting cells of the plurality of transconducting cells outputs the DC supply current (Idc) and an AC RF output current (IRF_OUT). In one or more embodiments, the transconducting cells are connected together in cascode (refer toFIG.5C) for the DC supply current (Idc), and are connected together in cascade (refer toFIG.5D) for the AC RF input and output currents535. Then, the method505ends545.

It should be noted that, in one or more embodiments of the present disclosure, the disclosed amplifier (e.g.,500ofFIGS.5A and5B,600ofFIGS.6A and6B, and700ofFIGS.7A and7B) implements each transconducting cell as a common source/emitter unit element. The common source/emitter unit element stages each have a RF unit element device that may be implemented utilizing any device technology (e.g., a FET device as in the amplifier600ofFIGS.6A and6B, or a BJT device as in the amplifier700ofFIGS.7A and7B). For example,FIGS.6A and6Btogether are a schematic circuit diagram of the disclosed single-ended single-stage “current mode” amplifier600, with transconductance cells610a,610b,610c,610dimplemented as common-source cells with RF unit element devices as a MOSFET, and in particular, an NMOS, in accordance with at least one embodiment of the present disclosure. And,FIGS.7A and7Btogether are a schematic circuit diagram of the disclosed single-ended single-stage “current mode” amplifier700, with transconductance cells710a,710b,710c,710dimplemented with common-emitter cells and RF unit element devices as a BJT, in accordance with at least one embodiment of the present disclosure.

For the disclosed amplifier500,600,700, each RF unit element device (e.g., NMOS or BJT) within a common source/emitter element (e.g., the transconducting cells510a,510b,510c,510d) will have a drain-to-source (or collector-to-emitter) DC voltage of Vdd/N provided by a DC series connection of: a power supply Vdd, N number of inductive elements (L∞), and N number of unit element common source/emitter cells (e.g., the transconducting cells510a,510b,510c,510d) with RF unit element devices (e.g., NMOS or BJT). A common DC current (Idc) is shared through the series connection of the power supply (Vdd), N number of inductive elements (L∞), and N number of unit element common source/emitter stages (e.g., the transconducting cells510a,510b,510c,510d) with RF unit element devices (e.g., NMOS or BJT). The DC bias of each RF unit element device (e.g., NMOS or BJT) is provided by a voltage (Vbias N) and a large gate/base biasing resistance (Rb) such that each unit element device (e.g., NMOS or BJT) can be biased independently insuring a current Idc and nominal division of Vdd voltage across each unit element drain-to-source or collector-to-emitter.

The input RF signal following the single-input to single-output input matching network (M1)520, drives the gate/base of each unit element device (e.g., NMOS or BJT) in parallel through large RF passing capacitors (C∞) at each unit element gate/base within each common source/emitter cell. Within the common source/emitter cell (e.g., the transconducting cells510a,510b,510c,510d), each unit element device (e.g., NMOS or BJT) acts as a common source/emitter transconductor with a large source/emitter capacitance (C∞) to ground and drain/collector RF inductive choke (L∞). The input RF signal from the input source (Vin) is power transformed via the single-input to single-output input matching network (M1)520to drive each common source/emitter unit element gate/base in parallel producing an AC current irf from each unit element device drain/collector. The output AC current of each unit element device (e.g., NMOS or BJT) is summed through an RF series connection of large RF capacitors (C∞), thereby creating a total AC output current of N-irf. The total output AC current (N-irf) is presented an impedance of Ropt/N (e.g., a resistance value chosen to optimize power and efficiency) transformed by a single-input to single-output output matching network (M2)530from a load impedance RL. At peak input power drive of the amplifier, the total output AC current has an amplitude swing of N·Idc with a peak current magnitude of (N+1)·Idc delivered to Ropt/N, thereby producing an AC voltage amplitude swing of Vdd/N and a peak magnitude of 2 Vdd/N.

FIG.8is an illustration of class A biasing of the “current mode” amplifier500,600,700ofFIGS.5A and5B,6A and6B, and7A and7B, in accordance with at least one embodiment of the present disclosure. For ideal class A operation of the amplifier500,600,700, as illustrated inFIG.8, the efficiency of the architecture approaches 50%, neglecting non-ideal losses. Due to the nature of summing output currents of the common source/emitter cells (e.g., the transconducting cells510a,510b,510c,510d) in RF series, the amplifier architecture is in “current mode”, which is in clear distinction from the conventional stacked “voltage mode” amplifiers (e.g., amplifier100ofFIG.1and amplifier300ofFIG.3).

The design of matching input network (M1)520and matching output network (M2)530can follow a traditional matching network design with either lumped elements or transmission line stubs. For example, L number of matching networks can be utilized to form a compact IC area. For higher efficiency applications, the current mode amplifier500,600,700may adapt the architecture from class A biasing to non-class A biasing by adjusting Vbias appropriately for the given class of operation following conventional amplifier design. In addition, harmonic termination for waveform shaping may be absorbed into the output matching network (M2)530.

As such,FIGS.5A and5B,FIGS.6A and6B, andFIGS.7A and7Billustrate embodiments for the disclosed single-stage amplifier500,600,700, which has a single-stage power gain, which is denoted by “G” in decibels (dB). The disclosed amplifier500,600,700improves upon the conventional amplifier designs (e.g., amplifier100ofFIG.1and amplifier300ofFIG.3) with several advantages. A first advantage of the disclosed amplifier500,600,700is that it employs a single-input single-output input matching network (M1)520and a single-input single-output output matching network (M2)530, which can significantly reduce the chip area occupation on an IC, as compared to the conventional amplifier100ofFIG.1.

A second advantage of the disclosed amplifier500,600,700is that any unit element device technology may be used to implement the architecture, such as a FET or BJT. A third advantage of the disclosed amplifier500,600,700is that there is no reliance on strict gate capacitance matching to maintain voltage swing reliability of device breakdown, as in the conventional amplifier300ofFIG.3.

A fourth advantage of the disclosed amplifier500,600,700is that there is no gate/base leakage path to ground of the cascoded devices, thereby reducing efficiency as in the conventional amplifier300ofFIG.3. Finally, a fifth advantage of the disclosed amplifier500,600,700is that due to the current mode operation, there are no large voltage swings on the devices, thereby improving reliability of body junction breakdown as well as linearity.

A differential embodiment for the disclosed amplifier900may be adopted, as is shown inFIGS.9A and9B.FIGS.9A and9Btogether are a schematic circuit diagram of the disclosed differential single-stage “current mode” amplifier900, in accordance with at least one embodiment of the present disclosure.

The disclosed differential single-stage “current mode” amplifier900, illustrated inFIGS.9A and9B, utilizes a cascode stack of N number of differential unit element transconducting cells910a,910b,910c,910d, which each take as an input: a supply current Idc, a differential AC RF current (IRF_IN), and a differential RF input signal (RFIN); and produce as an output: DC current (Idc) and differential AC RF current (IRF_OUT). The transconducting cells910a,910b,910c,910dare cascoded in terms of the DC input and output current, such that a common current (Idc) is shared amongst each transconducting cell910a,910b,910c,910d, and a DC supply voltage drop of Vdd/N is across each transconducting cell910a,910b,910c,910d. The transconducting cells910a,910b,910c,910dare cascaded such that each transconducting cell's differential output current (IRF_OUT) is the input to the following cascaded transconducting cell's differential input current (IRF_IN). An input signal source (Vin) (along with a source resistor Rs) is followed by a single-input single-output input matching network (M1)920, which drives each transconducting cell's RFINin parallel. The final output current of the last transconducting cell's910dIRF_OUTis applied to a single-input single-output output matching network (M2)930to deliver power to a load impedance RL. Differential-to-single-ended baluns may be used to convert the differential RFINto a single-ended input and convert a differential IRF_OUTto a single-ended output.

In one or more embodiments of the present disclosure, the disclosed amplifier (e.g.,900ofFIGS.9A and9B, and1000ofFIGS.10A,10B, and10C) implements each transconducting cell as a differential common source/emitter unit element. The common source/emitter unit element stages each have a RF unit element device that may be implemented in any device technology (e.g., a FET device as in the amplifier1000ofFIGS.10A,10B, and10C; or a BJT device).FIGS.10A,10B, and10Ctogether are a schematic circuit diagram of the disclosed differential single-stage “current mode” amplifier1000, with transconductance cells1010a,1010b,1010c,1010dimplemented as common-source cells with RF unit element devices each as a MOSFET, and in particular, an NMOS, in accordance with at least one embodiment of the present disclosure.

For the disclosed amplifier900,1000, each RF unit element device (e.g., NMOS or BJT) within the common source/emitter element (e.g., the transconducting cells1010a,1010b,1010c,1010d) will have a drain-to-source (or collector-to-emitter) DC voltage of Vdd/N provided by a DC series connection of: power supply Vdd, N number of inductive elements (L∞), and N number of unit element common source/emitter cells (e.g., the transconducting cells1010a,1010b,1010c,1010d) with RF unit element devices (e.g., NMOS or BJT). A common DC current (Idc) is shared through the series connection of power supply (Vdd), N number of inductive elements (L∞), and N number of unit element common source/emitter stages (e.g., the transconducting cells1010a,1010b,1010c,1010d) with RF unit element devices (e.g., NMOS or BJT). The DC bias of each RF unit element device (e.g., NMOS or BJT) is provided by a voltage (VbiasN) and large gate/base biasing resistance (Rb), such that each unit element device can be biased independently insuring a current Idc and nominal division of Vdd voltage across each unit element drain-to-source or collector-to-emitter.

Similarly, the differential version of the disclosed amplifier (e.g., amplifier900ofFIGS.9A and9B, and amplifier1000ofFIGS.10A,10B, and10C) may be designed in class A or non-class A biasing with a corresponding matching network design, as previously described. The efficiency for the differential architecture for the amplifier900,1000for class A biasing, ideally approaches 50%, while maintaining the architecture advantages of compact simple matching networks (e.g., single-input single-output input matching network (M1)920and single-input single-output output matching network (M2)930) as well as reliability.

A multi-stage embodiment for the disclosed amplifier (e.g., amplifier500ofFIGS.5A and5B) may be adopted, as is shown inFIGS.11A,11B and11C. In particular,FIGS.11A,11B, and11C together are a schematic circuit diagram of the disclosed multi-stage “current mode” amplifier1100with M number (in this example, three (3)) of first stage transconducting cells1110a,1110b,1110c, and N number (in this example, three (3)) of second stage transconducting cells1110d,1110e,1110f, where the power supply voltage (Vdd) is applied to the first transconducting cell1110a, in accordance with at least one embodiment of the present disclosure.

The disclosed single-ended multi-stage “current mode” amplifier1100, illustrated inFIGS.11A,11B, and11C, utilizes as its first stage, a cascode stack of M number of unit element transconducting cells1110a,1110b,1110c, and as its second stage, a cascode stack of N number of unit element transconducting cells1110d,1110e,1110f. Each of the transconducting cells1110a,1110b,1110c,1110d,1110e,1110ftakes as an input: a DC supply current (Idc), an AC RF input current (IRF_IN), and a RF input signal (RFIN); and produces as an output: the DC current (Idc) and an AC RF output current (IRF_OUT). The transconducting cells1110a,1110b,1110c,1110d,1110e,1110fare cascoded in terms of the DC input and output currents, such that a common current (Idc) is shared amongst each of the transconducting cells1110a,1110b,1110c,1110d,1110e,1110f, and such that a DC supply voltage drop of Vdd/(M+N) is across each of the transconducting cells1110a,1110b,1110c,1110d,1110e,1110f. The transconducting cells1110a,1110b,1110c,1110d,1110e,1110fwithin each stage (e.g., stage 1 and stage 2) are cascaded such that each transconducting cell's output current (IRF_OUT) is the input to the following cascaded transconducting cell's input current (IRF_IN).

An input signal source (Vin) (along with a source resistor Rs) is followed by a single-input single-output input matching network (M1)1120, which drives each transconducting cell's RF input signal (RFIN) in parallel of the first stage transconducting cells1110a,1110b,1110c. The output current of the last transconducting cell's1110cIRF_OUTof the first stage is applied to a single-input single-output inner stage matching network (M2)1125to deliver power to the second stage. The output current (IRF_OUT) of the final stage of the amplifier1100is followed by a single-input single-output output matching network (M3)1130to deliver power to a load resistor (RL). It should be apparent that, in one or more embodiments, the preceding embodiment description might be extended to a multi-stage amplifier having more than two stages, with each stage having an independently defined number of transconducting cells.

It should be noted that, in one or more embodiments, each of the transconducting cells1110a,1110b,1110c,1110d,1110e,1110fof the amplifier1100may comprise a MOSFET device (e.g., refer to transconductance cell610aofFIG.6A) or comprise a BJT device (e.g., refer to transconductance cell710aofFIG.7A). In addition, in one or more embodiments, the amplifier1100ofFIGS.11A,11B, and11Cmay be configured to be a differential amplifier (e.g., refer to amplifier900ofFIGS.9A and9B).

FIGS.12A,12B, and12Ctogether are a schematic circuit diagram of the disclosed multi-stage “current mode” amplifier1200with M number (in this example, three (3)) of first stage transconducting cells1210a,1210b,1210c, and N number (in this example, three (3)) of second stage transconducting cells1210d,1210e,1210f, where the power supply voltage (Vdd) is applied to a transconducting cell1210dother than the first transconducting cell1210a, in accordance with at least one embodiment of the present disclosure.

Also, in this example, an input signal source (Vin) (along with a source resistor Rs) is followed by a single-input single-output input matching network (M1)1220, which drives each transconducting cell's RF input signal (RFIN) in parallel of the first stage transconducting cells1210a,1210b,1210c. The output current of the last transconducting cell's1210cIRF_OUTof the first stage is applied to a single-input single-output inner stage matching network (M2)1225to deliver power to the second stage. The output current (IRF_OUT) of the final stage of the amplifier1200is followed by a single-input single-output output matching network (M3)1230to deliver power to a load resistor (RL).

The amplifier1200ofFIGS.12A,12B, and12Cmaintains the same DC current (Idc) and RF signal flow as the amplifier1100ofFIGS.11A,11B, and11C, with the exception of the location of the supply voltage (Vdd). The supply voltage (Vdd) need not necessarily originate from the first transconducting unit cell1210aof the first stage, but may originate at any transconducting cell1210a,1210b,1210c,1210d,1210e,1210fof any stage (e.g., stage 1 or stage 2). For illustration, the amplifier1200inFIGS.12A,12B, and12Cdepicts a two-stage amplifier1200with the power supply voltage (Vdd) originating from the first transconducting cell1210dof the second stage, and the DC current from the second stage supplies the DC current of the first stage.

It should be noted that, in one or more embodiments, each of the transconducting cells1210a,1210b,1210c,1210d,1210e,1210fof the amplifier1200may comprise a MOSFET device (e.g., refer to transconductance cell610aofFIG.6A) or comprise a BJT device (e.g., refer to transconductance cell710aofFIG.7A). In addition, in one or more embodiments, the amplifier1200ofFIGS.12A,12B, and12Cmay be configured to be a differential amplifier (e.g., refer to amplifier900ofFIGS.9A and9B).

Although particular embodiments have been shown and described, it should be understood that the above discussion is not intended to limit the scope of these embodiments. While embodiments and variations of the many aspects of the invention have been disclosed and described herein, such disclosure is provided for purposes of explanation and illustration only. Thus, various changes and modifications may be made without departing from the scope of the claims.

Where methods described above indicate certain events occurring in certain order, those of ordinary skill in the art having the benefit of this disclosure would recognize that the ordering may be modified and that such modifications are in accordance with the variations of the present disclosure. Additionally, parts of methods may be performed concurrently in a parallel process when possible, as well as performed sequentially. In addition, more steps or less steps of the methods may be performed.

Accordingly, embodiments are intended to exemplify alternatives, modifications, and equivalents that may fall within the scope of the claims.

Although certain illustrative embodiments and methods have been disclosed herein, it can be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods can be made without departing from the true spirit and scope of this disclosure. Many other examples exist, each differing from others in matters of detail only. Accordingly, it is intended that this disclosure be limited only to the extent required by the appended claims and the rules and principles of applicable law.