Patent ID: 12218639

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, various embodiments of the inventive concept are described with reference to the accompanying drawings.

FIG.1is a block diagram illustrating an interface circuit according to an example embodiment.

Referring toFIG.1, an interface circuit10may receive an input signal Yin and output an output signal Yout. The interface circuit10may be a receiver circuit, and the receiver circuit may receive the input signal Yin through a pin P and output the output signal Yout. The interface circuit10may be a receiver RX included in a memory interface and may be connected to an external device through the pin P. The interface circuit10may perform a noise removal operation on the output signal Yout received through the pin P, an error voltage correction operation on the output signal Yout, or an equalization operation on the output signal Yout.

The interface circuit10may include a first amplifier100and a code generator200. The first amplifier100may receive the input signal Yin, output the output signal Yout, and perform the noise removal operation, the error voltage correction operation, and the equalization operation. In some embodiments, the first amplifier100may be a differential amplifier. Specifically, the first amplifier100may generate the output signal Yout based on the input signal Yin received through the pin P and a reference voltage signal ref voltage generated by the interface circuit10. In some embodiments, the first amplifier100may generate the output signal Yout based on the input signal Yin received through the pin P and an input signal received through another pin. The first amplifier100may include a variable impedance circuit110. The variable impedance circuit110may have impedance which varies based on a control code. The variable impedance circuit110may be connected to an output node where the output signal Yout is output. With the impedance varying based on the control code, a plurality of operations regarding the output signal Yout may be performed. The variable impedance circuit110may include a plurality of transistors connected in parallel, and each of the plurality of transistors may be switched according to the control code. The noise removal operation may be described with reference toFIGS.4to6, the error voltage correction operation may be described with reference toFIGS.7to9, and the equalization operation may be described with reference toFIGS.10and11.

The code generator200may generate different control codes CODE for the first amplifier100to perform a plurality of operations. The impedance of the variable impedance circuit110may be different for each operation. Specifically, transistors to be switched among the plurality of transistors included in the variable impedance circuit110may be different for each operation.

The interface circuit10according to an example embodiment may perform a plurality of operations using a single circuit by controlling the variable impedance circuit110to have different impedances for each operation. Accordingly, the interface circuit10according to an example embodiment may not have separate circuits for each operation, and thus provide improved degree of integration and lower power consumption.

FIG.2is a circuit diagram illustrating an interface circuit according to an example embodiment.

With reference toFIG.2, an interface circuit10amay include a first amplifier100a, a code generator200a, and a reference voltage generator130a. The first amplifier100amay be a differential amplifier. That is, a first output signal Y_out and a second output signal Y_outb may be generated based on a difference between a first input signal Y_in and a second input signal Y_inb. The terms “first,” “second,” etc. may be used herein merely to distinguish one element or signal from another. The first output signal Y_out may be a voltage of a second output node ON2, and the second output signal Y_outb may be a voltage of a first output node ON1.

The interface circuit10amay be a receiver circuit configured to receive the first input signal Y_in from the pin P. The first amplifier100amay receive the first input signal Y_in from the pin P and receive the second input signal Y_inb from the reference voltage generator130a. In some embodiments, the first amplifier100amay receive the second input signal Y_inb from a separate pin (e.g., P′). The first amplifier100amay include a first input transistor P1configured to receive the first input signal Y_in through a gate terminal, and a second input transistor P2configured to receive the second input signal Y_inb through a gate terminal. In some embodiments, the first input transistor P1and the second input transistor P2may be a P-type transistor. In this specification, transistors may have or include any structure or types of transistors. For example, transistors may include a fin field effect transistor (FinFET) formed of active patterns extending in the form of a fin, and gate electrodes. The transistors may include a multi-bridge channel FET (MBCFET) formed of multiple nanosheets extending parallel to each other and gate electrodes. The transistors may include a ForkFET including nanosheets for P-type transistors and nanosheets for N-type transistors, which are separated into dielectric walls, allowing N-type transistors and P-type transistors to have a closer structure. The transistors may include a vertical FET (VFET) which includes source/drain areas spaced apart from each other in a vertical direction (e.g., in the Z-axis direction) relative to a substrate, and a gate electrode surrounding a channel area. The transistors may include not only a field effect transistor (FET) such as a complementary FET (CFET), a negative FET (NCFET), a carbon nanotube FET (CNTFET), etc. but may also include a bipolar junction transistor and other three-dimensional transistors.

The first amplifier100amay include a current source120a. The current source120amay supply a constant current regardless of changes in impedance of a first impedance circuit110_1aand a second impedance circuit110_2a. In some embodiments, the current source120amay supply a current which varies based on a common mode feedback signal CMFB.

The first amplifier100amay include a first sensing resistor R1and a second sensing resistor R2. The first sensing resistor R1may be connected between the first output node ON1and a feedback node FN. The second sensing resistor R2may be connected between the second output node ON2and the feedback node FN. The common mode feedback signal CMFB may be output from the feedback node FN. A level of current provided by the current source120amay vary according to a result of comparison between the common mode feedback signal CMFB and a reference signal reference CM.

The first amplifier100amay include the first impedance circuit110_1aand the second impedance circuit110_2a. The impedance of the first impedance circuit110_1amay be a first impedance Z1, and the impedance of the second impedance circuit110_2amay be a second impedance Z2.

The first impedance circuit110_1amay be connected between the first output node ON1and a ground node. The first impedance circuit110_1amay include a first load resistor RL1, a second load resistor RL2, and a plurality of transistors M1to M3.

The plurality of transistors M1to M3may be connected to each other in parallel. Each of the plurality of transistors M1to M3may be switched based on first control codes PCODE[0] to PCODE[2]. The first transistor M1may be switched by receiving the PCODE[0] through a gate terminal, and the second transistor M2may be switched by receiving the PCODE[1] through a gate terminal, and the third transistor M3may be switched by receiving the PCODE[2] through a gate terminal. With reference toFIG.2, the first impedance circuit110_1ais described as including three transistors, i.e., the first, second, and third transistors M1, M2, and M3; however, embodiments are not limited thereto. The greater the number of turned-on transistors among the plurality of transistors M1to M3, the less the first impedance Z1may become.

The plurality of transistors M1to M3and the first load resistor RL1may be connected in parallel. Accordingly, even when the plurality of transistors M1to M3are turned off, as a current may flow from the first output node ON1to the ground node, a voltage according to the first load resistor RL1may be generated as the second output signal Y_outb.

The first load resistor RL1and the second load resistor RL2may be connected in series. The second load resistor RL2may be connected to the first output node ON1. As the second load resistor RL2is arranged between the first output node ON1and the plurality of transistors M1to M3, the noise, which may be generated in regard to the second output signal Y_outb when the plurality of transistors M1to M3are switched, may be reduced or prevented by the second load resistor RL2. However, embodiments are not limited thereto, and the second load resistor RL2may be arranged between the ground node and the plurality of transistors M1to M3.

The second impedance circuit110_2amay be connected between the second output node ON2and the ground node. The second impedance circuit110_2amay include a third load resistor RL3, a fourth load resistor RL4, and a plurality of transistors M4to M6. The plurality of transistors M4to M6may be connected to each other in parallel.

Each of the plurality of transistors M4to M6may be switched based on second control codes NCODE[0] to NCODE[2]. The fourth transistor M4may be switched by receiving the NCODE[0] through a gate terminal, and the fifth transistor M5may be switched by receiving the NCODE[1] through a gate terminal, and the sixth transistor M6may be switched by receiving the NCODE[2] through a gate terminal. With reference toFIG.2, the second impedance circuit110_2ais described as including three transistors, i.e., the fourth, fifth, and sixth transistors M4, M5, and M6; however, embodiments are not limited thereto. The greater the number of turned-on transistors among the plurality of transistors M4to M6, the less the second impedance Z2may become.

The plurality of transistors M4to M6and the third load resistor RL3may be connected in parallel. Accordingly, even when the plurality of transistors M4to M6are turned off, as a current may flow from the second output node ON2to the ground node, a voltage according to the third load resistor RL3may be generated as the first output signal Y_out.

The third load resistor RL3and the fourth load resistor RL4may be connected in series. The fourth load resistor RL4may be connected to the second output node ON2. As the fourth load resistor RL4is arranged between the first output node ON2and the plurality of transistors M4to M6, the noise, which may be generated in regard to the first output signal Y_out when the plurality of transistors are switched, may be reduced or prevented by the fourth load resistor RL4. However, embodiments are not limited thereto, and the fourth load resistor RL4may be arranged between the ground node and the plurality of transistors M4to M6.

The gate terminal of the first input transistor P1may receive the first input signal Y_in, and a size (e.g., amperage) of current flowing in the first input transistor P1may be determined based on the first input signal Y_in. Specifically, in some embodiments, as the first input transistor P1may be a P-type transistor, the smaller a size (e.g., magnitude of current or voltage) of the first input signal Y_in is, the higher a current flowing in the first input transistor P1may become. However, embodiments are not limited thereto, and when the first input transistor P1is an N-type transistor, the greater the size of the first input signal Y_in is, the higher the current flowing in the first input transistor P1may become. In this specification, for convenience of explanation, the first input transistor P1may be described as a P-type transistor.

The gate terminal of the second input transistor P2may receive the second input signal Y_inb, and a size of current flowing in the second input transistor P2may be determined based on the second input signal Y_inb. In some embodiments, as the second input transistor P2may be a P-type transistor, the smaller a size of the second input signal Y_inb is, the higher a current flowing in the second input transistor P2may become. However, embodiments are not limited thereto, and when the second input transistor P2is an N-type transistor, the greater the size of the second input signal Y_inb is, the higher the current flowing in the second input transistor P2may become. In this specification, for convenience of explanation, the second input transistor P2may be described as a P-type transistor.

The size of the second output signal Y_outb may be understood as the first impedance Z1multiplied by the current flowing in the first input transistor P1by or responsive to the first input signal Y_in. Accordingly, the size of the second output signal Y_outb may be determined based on the first impedance Z1and the size of the first input signal Y_in. For example, when the first impedance Z1decreases, the second output signal Y_outb may be reduced, and when the size of the first input signal Y_in increases, the second output signal Y_outb may be reduced.

The size of the first output signal Y_out may be understood as the second impedance Z2multiplied by the current flowing in the second input transistor P2by or responsive to the second input signal Y_inb. Accordingly, the size of the first output signal Y_out may be determined based on the second impedance Z2and the size of the second input signal Y_inb. For example, when the second impedance Z2decreases, the first output signal Y_out may be reduced, and when the size of the second input signal Y_inb increases, the first output signal Y_out may be reduced.

When the second output signal Y_outb is greater than the first output signal Y_out, logic levels indicated by the first and second output signals Y_out and Y_outb may be determined as a logic low level. Accordingly, in some embodiments in which the first impedance Z1is less than the second impedance Z2, the size of the first input signal Y_in may need to be smaller than the size of the second input signal Y_inb so that the first and second output signals Y_out and Y_outb may have a logic low level. In some embodiments in which the first impedance Z1is greater than the second impedance Z2, even when the size of the first input signal Y_in is greater than the size of the second input signal Y_inb, the first and second output signals Y_out and Y_outb may have a logic low level.

When the first output signal Y_out is greater than the second output signal Y_outb, logic levels indicated by the first and second output signals Y_out and Y_outb may be determined as a logic high level. Accordingly, in some embodiments in which the first impedance Z1is greater than the second impedance Z2, the size of the second input signal Y_inb may need to be smaller than the size of the first input signal Y_in so that the first and second output signals Y_out and Y_outb may have a logic high level. In some embodiments in which the first impedance Z1is less than the second impedance Z2, even when the size of the second input signal Y_inb is greater than the size of the first input signal Y_in, the first and second output signals Y_out and Y_outb may have a logic high level.

That is, the interface circuit10aaccording to an example embodiment may determine a logic level indicated by the first and second output signals Y_out and Y_outb by adjusting the sizes of the input signals Y_in and Y_inb according to the first and second impedances Z1and Z2.

The code generator200amay include a first control code generator210aand a second control code generator220a. The first control code generator210amay generate a first control code PCODE to control the first impedance circuit110_1a. The second control code generator220amay generate a second control code NCODE to control the second impedance circuit110_2a. The code generator200amay be a digital generator that generates signals represented by bits, or may be an analog generator that generates signals having a continuous size. That is, in this specification, the first control code PCODE and the second control code NCODE may be a digital signal represented by “1” or “0,” or an analog signal having a continuous size or represented by a continuous wave.

FIG.3is a block diagram illustrating an interface circuit according to an example embodiment. With reference toFIG.3, an interface circuit10′ may include a first to third amplifiers100′,300′, and400′. The first to third of amplifiers100′,300′, and400′ may be connected in series. However, the number and/or electrical interconnections of amplifiers included in the interface circuit10′ is not limited thereto, and at least two of the amplifiers may be connected in parallel.

The first amplifier100′ may be an example of amplifiers100and100aillustrated inFIGS.1and2. Accordingly, the first amplifier100′ may include a variable impedance circuit110′, and the variable impedance circuit110′ may include, for example, the first impedance circuit110_1aand the second impedance circuit110_2aillustrated inFIG.2. The first amplifier100′ may receive the first input signal Y_in and output a first output signal Y_preo. The first output signal Y_preo may correspond to the output signal Yout ofFIG.1. In some embodiments, the first output signal Y_preo may have a voltage level that is not recognized as a logic high level or a logic low level. Accordingly, the first output signal Y_preo may be amplified to a voltage range recognized as a logic high level or a logic low level through the second amplifier300′ and/or the third amplifier400′.

The second amplifier300′ may receive the first output signal Y_preo and output a second output signal Y_a. The second amplifier300′ may be an inverting amplifier or a non-inverting amplifier. The second output signal Y_a may have a voltage range recognized as a logic high level or a logic low level. For example, the second output signal Y_a may have a high level input voltage (VIH), which is a voltage range recognized as a logic high level, or have a low level input voltage (VIL), which is a voltage range recognized as a logic low level.

The third amplifier400′ may receive the second output signal Y_a and output a third output signal Y_out. The third amplifier400′ may be an inverting amplifier or a non-inverting amplifier. The third output signal Y_out may be or correspond to a positive supply voltage VDD or a negative supply voltage VSS. When the third output signal Y_out is a positive supply voltage VDD, a logic level of the third output signal Y_out may be recognized as a logic high level, and when the third output signal Y_out is a negative supply voltage VSS, a logic level of the third output signal Y_out may be recognized as a logic low level.

FIG.4is a circuit diagram illustrating an interface circuit according to an example embodiment.FIG.5is a graph illustrating the relationship between logic levels and input signals for noise removal according to an example embodiment.FIG.6is a graph illustrating noise removal effects according to an example embodiment. With reference toFIG.4, an interface circuit10bmay include a first amplifier100b, a second amplifier300b, a third amplifier400b, and a code generator200b. Descriptions provided above with reference toFIG.2may be omitted hereinafter. The interface circuit10bmay receive the first input signal Y_in and the second input signal Y_inb, and output a fourth output signal Y_out and a fifth output signal Y_outb. The fifth output signal Y_outb may have a voltage level opposite to that of the fourth output signal Y_out. That is, when the fourth output signal Y_out is or corresponds to a positive supply voltage VDD, the fifth output signal Y_outb may be or correspond to a negative supply voltage VSS, and when the fourth output signal Y_out is or corresponds to a negative supply voltage VSS, the fifth output signal Y_outb may be or correspond to a positive supply voltage VDD. The interface circuit10bmay perform the noise removal operation by controlling a first impedance circuit110_1bbased on the fourth output signal Y_out, and controlling a second impedance circuit110_2bbased on the fifth output signal Y_outb. More specific operations may be described later.

The second amplifier300bmay be an amplifier including a current source320band a plurality of transistors P3, P4, M5, and M6. The second amplifier300bmay be a single-stage differential amplifier. That is, the second amplifier300bmay receive a first output signal Y_preo and a second output signal Y_preob and output a third output signal Y_a. The second amplifier300bmay generate a third output signal Y_a by amplifying a difference between the first output signal Y_preo and the second output signal Y_preob. The third output signal Y_a may have a voltage range recognized as a logic high level or a logic low level. For example, the third output signal Y_a may have a VIH, which is a voltage range recognized as a logic high level, or have a VIL, which is a voltage range recognized as a logic low level. For example, when a size of the first output signal Y_preo is greater than a size of the second output signal Y_preob, the third output signal Y_a may have a voltage range recognized as a logic high level, and when the size of the second output signal Y_preob is greater than the size of the first output signal Y_preo, the third output signal Y_a may have a voltage range recognized as a logic low level.

The third amplifier400bmay receive the third output signal Y_a and output the fourth output signal Y_out and the fifth output signal Y_outb. The polarity of the fourth output signal Y_out may be identical to the polarity of the third output signal Y_a. The fourth output signal Y_out may have a voltage level opposite to that of the fifth output signal Y_outb. When the fourth output signal Y_out is or corresponds to a positive supply voltage VDD, and the fifth output signal Y_outb is or corresponds to a negative supply voltage VSS, it may be understood that the fourth and fifth output signals Y_out and Y_outb have a logic high level. When the fourth output signal Y_out is or corresponds to a negative supply voltage VSS, and the fifth output signal Y_outb is or corresponds to a positive supply voltage VDD, it may be understood that the output signals have a logic low level.

The code generator200bmay include a first code generator210band a second code generator220b.

The code generator200bmay generate control codes PCODE and NCODE based on the fourth output signal Y_out and the fifth output signal Y_outb. During the noise removal operation, the first code generator210bmay control the first impedance circuit110_1bby generating the first control code PCODE based on the fourth output signal Y_out. The second code generator220bmay control the second impedance circuit110_2bby generating the second control code NCODE based on the fifth output signal Y_outb.

In some embodiments, when the fourth output signal Y_out is or corresponds to a positive supply voltage VDD and the fifth output signal Y_outb is or corresponds to a negative supply voltage VSS, i.e., when the fourth and fifth output signals Y_out and Y_outb have a logic high level, the code generator200bmay perform the noise removal operation by generating control codes PCODE and NCODE so that the first impedance Z1becomes less than the second impedance Z2. For the logic level of the fourth output signal Y_out and the fifth output signal Y_outb to become a logic low level, the size of the second output signal Y_preob may need to be greater than the size of the first output signal Y_preo. Accordingly, when the first impedance Z1is less than the second impedance Z2, the size of the first input signal Y_in may need to be smaller than the size of the second input signal Y_inb.

For example, as shown inFIG.5, for the logic level of the fourth output signal Y_out and the fifth output signal Y_outb to change or transition to a logic low level from a logic high level, the first input signal Y_in may be required to have a voltage level lower than that of the second input signal Y_inb by a second reference level ΔV2. Hence, when the fourth output signal Y_out and the fifth output signal Y_outb have a logic high level, as the logic high level may be maintained even when the size or voltage level of the first input signal Y_in becomes slightly less due to noise, the noise removal effects may occur.

In some embodiments, the code generator200bmay control the number of turned-on transistors among the plurality of transistors M1to M3included in the first impedance circuit110_1bto be greater than the number of turned-on transistors among the plurality of transistors M4to M6included in the second impedance circuit110_2b.

In some embodiments, when the fifth signal Y_outb is or corresponds to a positive supply voltage VDD, and the fourth output signal Y_out is or corresponds to a negative supply voltage VSS, i.e., the fourth and fifth output signals Y_out and Y_outb have a logic low level, the code generator200bmay perform the noise removal operation by generating the control codes PCODE and NCODE so that the second impedance Z2becomes less than the first impedance Z1. For the logic level of the fourth output signal Y_out and fifth output signal Y_outb to become a logic high level, the size of the first output signal Y_preo may need to be greater than the size of the second output signal Y_preob. Accordingly, when the second impedance Z2is less than the first impedance Z1, the size of the first input signal Y_in may need to be smaller than the size of the second input signal Y_inb.

For example, as illustrated inFIG.5, for the logic level of the fourth output signal Y_out and the fifth output signal Y_outb to change or transition to a logic high level from a logic low level, the first input signal Y_in may need to have a voltage level greater than the second input signal Y_inb by a first reference level ΔV1. Hence, when the fourth output signal Y_out and the fifth output signal Y_outb have a logic low level, as the logic low level may be maintained even when the size or voltage level of the first input signal Y_in becomes slightly greater due to noise, the noise removal effects may occur.

In some embodiments, the code generator200bmay control the number of turned-on transistors among the plurality of transistors M1to M3included in the first impedance circuit110_1bto be greater than the number of turned-on transistors among the plurality of transistors M4to M6included in the second impedance circuit110_2b.

With reference toFIG.5, when the output signals Y_out and Y_outb have a logic low level, the logic level may become a logic high level at a first time t1when the first input signal Y_in becomes greater than the second input signal Y_inb by the first reference level ΔV1.

Meanwhile, when the output signals Y_out and Y_outb have a logic high level, the logic level may become a logic low level at a time t2when the first input signal Y_in becomes less than the second input signal Y_inb by the second reference level ΔV2.

With reference toFIG.6, noise may be generated in regard to the first and second input signals Y_in and Y_inb. For example, the first and second input signals Y_in and Y_inb may have a logic high level from a third time t3to a sixth time t6, and have a logic low level at the rest of the time periods; however, there may be time periods in which accurate logic levels may not be easily recognized due to noise.

In case1where the code generator200bdoes not generate a control code, when the first input signal Y_in is greater than the second input signal Y_inb, the fourth output signal Y_out may have a logic high level, and when the first input signal Y_in is smaller than the second input signal Y_inb, the fourth output signal Y_out may have a logic low level. Accordingly, at the first time t1to the second time t2when the noise occurs, the fourth output signal Y_out may be misrecognized as having a logic high level, and at the fourth time t4to the fifth time5, it may be misrecognized as having a logic low level.

In case2where the code generator200bgenerates control codes, noise between the first time t1to the second t2and the fourth time t4to the fifth time t5may be removed. Specifically, even if the first input signal Y_in becomes greater than the second input signal Y_inb momentarily due to the noise of the first and second input signals Y_in and Y_inb, when a difference between the first input signal Y_in and the second input signal Y_inb is less than the first reference level ΔV1, the fourth output signal Y_out may maintain the logic low level, as illustrated inFIG.6. Also, even if the first input signal Y_in becomes smaller than the second input signal Y_inb momentarily between the fourth time t4and the fifth time t5, when the difference between the first input signal Y_in and the second input signal Y_inb is less than the second reference level ΔV2, the fourth output signal Y_out may maintain the logic high level, as illustrated inFIG.6.

As described above, the interface circuit according to the example embodiments may control the first impedance Z1based on the fourth output signal Y_out, and control the second impedance Z2based on the fifth output signal Y_outb to perform the noise removal operation in regard to the output signals Y_out and Y_outb.

FIG.7is a circuit diagram of an interface circuit according to an example embodiment.FIG.8is a diagram illustrating an error voltage correction operation according to an example embodiment.FIG.9is a graph illustrating an error voltage correction operation according to an example embodiment.FIG.10is a timing diagram illustrating an error voltage correction operation according to an example embodiment. With reference toFIG.7, an interface circuit10caccording to an example embodiment may include a first amplifier100c, a second amplifier300c, a third amplifier400c, and a code generator200c. Descriptions provided above with reference toFIGS.2and4may be omitted hereinafter.

The code generator200cmay generate control codes PCODE and NCODE based on first and second error voltage control signals ofs_ctrl1and ofs_ctrl2. Specifically, a first code generator210cmay switch the plurality of transistors M1to M3to adjust a voltage level of the second output signal Y_preob according to the first error voltage control signal ofs_ctrl1. A second code generator220cmay switch the plurality of transistors M4to M6to adjust a voltage level of the first output signal Y_preo according to the second error voltage control signal ofs_ctrl2. That is, unlike the code generator200bofFIG.4, the code generator200cmay receive the first and second error voltage control signals ofs_ctrl1and ofs_ctrl2, and output a predetermined calibration code as the first control code PCODE and the second control code NCODE to separately control the first output signal Y_preo and the second output signal Y_preob. When the size of the first impedance Z1becomes smaller than the size of the second impedance Z2, the size of the second output signal Y_preob may become smaller as well. When the size of the second impedance Z2becomes smaller than the size of the first impedance Z1, the size of the first output signal Y_preo may become smaller as well.

With reference toFIG.8, the code generator220cmay generate a 3-bit first control code PCODE and a 3-bit second control code NCODE, respectively. Each bit may represent a signal applied to the gate terminal of the plurality of transistors M1to M6.

With reference toFIG.8, the code generator220cmay control the first impedance Z1by the plurality of transistors M1to M3by generating the first control code PCODE based on the first error voltage control signal ofs_ctrl1and thus, control the size of the second output signal Y_preob. For example, when the first control code PCODE is “000,” the first to third transistors M1to M3may become turned off, and thus, the size of the first impedance Z1may be the greatest. The code generator220cmay adjust the second impedance Z2by the plurality of transistors M4to M6by generating the second control code NCODE based on the second error voltage control signal ofs_ctrl2and thus, control the size of the first output signal Y_preo. For example, when the second control code NCODE is “000,” the fourth to sixth transistors M4to M6may become turned off, and thus, the size of the second impedance Z2may be the greatest.

As described above with reference toFIGS.7and8, during the error correction operation which separately adjusts the sizes of the first and second output signals Y_out and Y_outb, duty ratio correction effects may occur, as described later with reference toFIGS.9and10.

With reference toFIG.9, a duty ratio of the output signals Y_out and Y_outb may be adjusted according to the control codes PCODE and NCODE. The more transistors the first control code PCODE turns on, the smaller the size of the first impedance Z1becomes, which leads to an increased duty ratio. For example, when the 3-bit first control code PCODE turns on all of the first, second, and third transistors M1, M2, and M3, the duty ratio of the output signals Y_out and Y_outb may be 50+ΔD1%. That is, as described with reference toFIG.5, in the case where the size of the first impedance Z1becomes less, the logic level of the fourth output signal Y_out may change when the size of the first input signal Y_in is smaller than the size of the second input signal Y_inb, which leads to an increased duty ratio. The more transistors the second control code NCODE turns on, the smaller the size of the second impedance Z2becomes, which leads to a reduced duty ratio. For example, when the 3-bit second control code NCODE turns on all of the fourth, fifth, and sixth transistors M4, M5, and M6, the duty ratio of the output signals Y_out and Y_outb may be 50−ΔD2%. That is, as described with reference toFIG.5, in the case where the size of the second impedance Z2becomes less, the logic level of the fourth output signal Y_out may change when the size of the first input signal Y_in is greater than the size of the second input signal Y_inb, which leads to a reduced duty ratio.

With reference toFIG.10, even when the input signals Y_in and Y_inb have the same waveform, the duty ratio of the fourth output signal Y_out may change according to the first impedance Z1and the second impedance Z2. Specifically, in case1where the first impedance Z1is greater than the second impedance Z2, the duty ratio may be 50−ΔD2%. In case2where the first impedance Z1is identical to the second impedance Z2, the duty ratio may be 50%. In case3where the second impedance Z2is greater than the first impedance Z1, the duty ratio may be 50+ΔD1%.

The interface circuit10caccording to an example embodiment may control a duty ratio of an output signal by varying impedance through a predetermined control code. Further, as the interface circuit10cmay have the same structure as the interface circuit10bofFIG.4, it may perform both of the noise removal operation and the error voltage correction operation using a single structure. Accordingly, as it is not required to provide separate circuits for each of the noise removal operation and the error voltage correction operation, the degree of integration of the circuit may be improved.

FIG.11is a circuit diagram of an interface circuit according to an example embodiment.FIG.12is a graph illustrating the relationship between logic levels and input signals for an equalization operation according to an example embodiment.FIG.13is a timing diagram illustrating an equalization operation according to an example embodiment.

With reference toFIG.11, an interface circuit10dmay include a first amplifier100d, a second amplifier300d, a third amplifier400d, and a code generator200d. Descriptions provided above with reference toFIGS.2,4, and8may be omitted hereinafter.

The first amplifier100dmay receive the first input signal Y_in from the pin P. In some embodiments, the first amplifier100dmay receive the first input signal Y_in from a separate pin P′, and receive the second input signal Y_inb from a reference signal generator. The pin P may be connected to a channel, and transmission data Tx_DTA transmitted by an external device may be provided through the channel. That is, as the transmission data Tx_DTA passes through the channel, inter-symbol interference (ISI) may occur, and a signal including the ISI may be received as the first input signal Y_in.

The interface circuit10daccording to an example embodiment may perform the equalization operation to remove the ISI. Specifically, the code generator200dmay include a first code generator210dand a second code generator220d. The first code generator210dmay control a first impedance circuit110d_1dbased on the fifth output signal Y_outb, and the second generator220dmay control a second impedance circuit110d_2dbased on the fourth output signal Y_out. For example, when the fourth and fifth output signals Y_out and Y_outb have a logic high level, i.e., when the fourth output signal Y_out is a positive supply voltage VDD, the second code generator220dmay generate the second control code NCODE to lower the second impedance Z2. Alternatively, the first code generator210dmay generate the first control code PCODE to increase the first impedance Z1. With reference toFIG.12, the first and second generators210dand220dmay generate the control codes PCODE and NCODE to control the logic level of the output signals to change to a logic low level from the fourth time t4where the first input signal Y_in is greater than the second input signal Y_inb by a fourth reference level ΔV4or less. In other words, the transition to logic low level may occur when the first input signal Y_in is within the fourth reference level ΔV4of the second input signal Y_inb. That is, even when the first input signal Y_in is greater than the second input signal Y_inb, the logic level of output signals may change to a logic low level.

In addition, when the fourth and fifth output signals Y_out and Y_outb have a logic low level, i.e., when the fifth output signal Y_outb is a positive supply voltage VDD, the first code generator210dmay generate the first control code PCODE to lower the first impedance Z1. Alternatively, the second code generator220dmay generate the second control code NCODE to increase the second impedance Z2. With reference toFIG.12, the first and second generators210dand220dmay generate the control codes PCODE and NCODE to control the logic level of the output signals to change to a logic high level from the third time t3where the first input signal Y_in is smaller than the second input signal Y_inb by a third reference level ΔV3or less. In other words, the transition to logic high level may occur when the first input signal Y_in is within the third reference level ΔV3of the second input signal Y_inb. That is, even when the first input signal Y_in is less than the second input signal Y_inb, the logic level of the output signal may change to a logic high level.

With reference toFIG.13, the transmission data Tx_DTA may be pulse data without noise. As the transmission data Tx_DTA passes through the channel, inter-symbol interference may occur, and the first input signal Y_in may have a different waveform than the transmission data Tx_DTA. Specifically, due to the inter-symbol interference between the fifth time t5and the sixth time t6, the first input signal Y_in may be maintained to be greater than the second input signal Y_inb.

With reference toFIG.13, in case1where the equalization operation is performed, the waveform of the fourth output signal Y_out may be identical to the waveform of the transmission data Tx_DTA. That is, the interface circuit10daccording to an example embodiment may change the logic level of the output signal Y_out to a logic low level by adjusting the impedance even when the first input signal Y_in is greater than the second input signal Y_inb (e.g., between time t5and time t6), and change the logic level of the output signal Y_out to a logic high level even when the first input signal Y_in is less than the second input signal Y_inb (e.g., between time t7and time t8). That is, according to an example embodiment, the equalization operation to remove the inter-symbol interference occurred in regard to the first input signal Y_in may be performed.

With reference toFIG.13, in case2where the equalization operation is not performed, the waveform of the fourth output signal Y_out may be different than the waveform of the transmission data Tx_DTA. Specifically, due to the inter-symbol interference between the fifth time t5and the sixth time t6, the first input signal Y_in may be maintained to be greater than the second input signal Y_inb. Accordingly, the fourth input signal Y_out may be recognized as having a logic high level. Further, due to the inter-symbol interference between the seventh time t7and the eighth time t8, the first input signal Y_in may be maintained to be less than the second input signal Y_inb. Accordingly, the fourth input signal Y_out may be recognized as having a logic low level.

The interface circuit10daccording to an example embodiment may change the logic level of the output signal Y_out to a logic low level by adjusting the impedance even when the first input signal Y_in is greater than the second input signal Y_inb, and change the logic level of the output signal Y_out to a logic high level even when the first input signal Y_in is less than the second input signal Y_inb. That is, according to an example embodiment, the equalization operation to remove the inter-symbol interference occurred in regard to the first input signal Y_in may be performed. Further, as the interface circuit10dmay have the same structure as the interface circuits10band10cofFIGS.4and7, it may perform all of the noise removal operation, the error voltage correction operation, and the equalization operation using a single structure. Accordingly, as it is not required to provide separate circuits for each of the noise removal operation, the error voltage correction operation, and the equalization operation, the degree of integration of the circuit may be improved.

FIG.14is a circuit diagram of an interface circuit according to an example embodiment.

With reference toFIG.14, an interface circuit10emay include a first amplifier100e, a second amplifier300e, a third amplifier400e, a code generator200e, and a selection circuit500e. The selection circuit500emay include a first selection circuit510eand a second selection circuit520e. Descriptions provided above with reference toFIGS.4,7, and11may be omitted hereinafter.

The code generator200emay include a first code generator210eand a second code generator220e. The first selection circuit510emay select one of a plurality of signals Y_out, Y_outb, and Duty_ctrl (shown as ofs_ctrl1) based on a mode selection signal mode_sel and provide the selected signal to the first code generator210e. The second selection circuit520emay select one of a plurality of signals Y_out, Y_outb, and Duty_ctrl (shown as ofs_ctrl2) based on the mode selection signal mode_sel and provide the selected signal to the second code generator220e.

The mode selection signal mode_sel may be a signal representing at least one mode of the noise removal mode, the error voltage correction mode, and the equalization mode.

The first selection circuit510emay provide the fourth output signal Y_out to the first code generator210ewhen the mode selection signal mode_sel represents the noise removal mode. The first code generator210emay control the first impedance circuit110_1ebased on the fourth output signal Y_out, as described above with reference toFIGS.4to6. The second selection circuit520emay provide the fifth output signal Y_outb to the second code generator220ewhen the mode selection signal mode_sel represents the noise removal mode. The second code generator220emay control the second impedance circuit110_2ebased on the fifth output signal Y_outb, as described above with reference toFIGS.4to6.

The first selection circuit510emay provide the predetermined calibration code as the first control code PCODE to the first code generator210ewhen the mode selection signal mode_sel represents the error voltage correction mode. The second selection circuit520emay provide the predetermined calibration code as the second control code NCODE to the second code generator220ewhen the mode selection signal mode_sel represents the error voltage correction mode. Specific descriptions thereon are provided above with reference toFIGS.7to10.

The first selection circuit510emay provide the fifth output signal Y_outb to the first code generator210ewhen the mode selection signal mode_sel represents the equalization mode. The first code generator210emay control the first impedance circuit110_1ebased on the fifth output signal Y_outb, as described above with reference toFIGS.11and13. The second selection circuit520emay provide the fourth output signal Y_out to the second code generator220ewhen the mode selection signal mode_sel represents the equalization mode. The second code generator220emay control the second impedance circuit110_2ebased on the fourth output signal Y_out, as described above with reference toFIGS.11and13.

By including the selection circuit, the interface circuit10eaccording to an example embodiment may selectively perform the noise removal operation, the error voltage correction operation, and the equalization operation. Accordingly, as it is not required to provide separate circuits for each of the operations, the degree of integration of the circuit may be improved, and the size of the circuit may be reduced.

FIG.15is a flowchart illustrating operations of an interface circuit according to an example embodiment.

With reference toFIG.15, operations of an interface circuit including a plurality of amplifiers may include multiple operations S100, S200, and S300. The interface circuit may receive a first input signal and a second input signal, and output a first output signal and a second output signal. A first amplifier of the plurality of amplifiers may receive the first input signal and the second input signal. The first amplifier may be, for example, the first amplifier100eofFIG.14. The first input signal may a signal received from an outside or external device through the pin P, and the second input signal may be a signal received from the reference voltage generator. A second amplifier of the plurality of amplifiers may receive a first output signal and a second output signal. The second amplifier may be, for example, the second amplifier300eor the third amplifier400eofFIG.14. The interface circuit may be identical to the interface circuits described above with reference to at least one ofFIGS.1to14.

In operation S100, the interface circuit may select one of the first output signal, the second output signal, and the error voltage control signal as a signal to control output impedance.

Operation modes may include the noise removal mode, the error voltage correction mode, and the equalization mode. The first amplifier may include two output terminals. The two output terminals may be connected to the impedance circuit which varies according to the control codes. For example, the first output terminal may be connected to the first impedance circuit, and the second output terminal may be connected to the second impedance circuit.

In some embodiments, the interface circuit may select the first output signal as a signal to control the first impedance circuit when the operation mode is the noise removal mode, and the second output signal as a signal to control the second impedance circuit. When the operation mode is the error voltage correction mode, the error voltage control signal may be selected as a signal to control the first impedance circuit and the second impedance circuit. When the operation mode is the equalization mode, the second output signal may be selected as a signal to control the first impedance circuit, and the first output signal as a signal to control the second impedance circuit.

In operation S200, the interface circuit may adjust the impedance connected to the output terminal of the first amplifier based on the selected signal. Each of the first impedance and the second impedance may include a plurality of transistors. In operation S200, the interface circuit may adjust the impedance by switching the plurality of transistors based on the selected signal. Specific operations are described above with reference toFIGS.1to14.

In operation S300, the interface circuit may generate an output signal based on the adjusted impedance. The interface circuit may selectively perform a plurality of operations in regard to the output signal by adjusting the impedance based on different signals according to the operation modes.

FIG.16is a block diagram illustrating a memory system employing an interface circuit according to an example embodiment.

With reference toFIG.16, a memory system1000may include a memory controller1100and a memory device1200. A plurality of pins P1to P9connected to the memory controller1100may be connected to a plurality of pins P1′ to P9′ connected to the memory device1200, respectively. The first to eight pins P1to P8and P1′ to P8′ may be referred to as DQ pins, and the nineth pins P9and P9′ may be referred to as DQS pins. The number of pins is not limited thereto. The DQ pin may be a pin configured to transmit and receive data, addresses, etc., and the DQS pin may be a pin configured to transmit and receive strobe signals to be synchronized with data transmitted to the DQ pin.

The memory controller1100may include a memory interface1110and an internal circuit1120. The memory interface1110may include a first to ninth receiver circuits1111to1113connected to the plurality of pins P1to P9. Each of the first to ninth receiver circuits1111to1113may be implemented as one example of the interface circuit described above with reference toFIGS.1to14. For example, the first receiver circuit1111may receive signals from the first pin P1and output signals to the internal circuit1120. The memory interface1110may further include a plurality of transmitter circuits (although they are not shown in the drawings), and the transmitter circuits may be connected to at least one pin. Further, the memory device1200may be provided with a memory interface including a receiver circuit and a transmitter circuit, and the receiver circuit included in the memory device1200may be implemented by the interface circuit describe above with reference toFIGS.1to14.

The internal circuit1120may perform operations to generally control the memory device1200. For example, the internal circuit1120may generate and provide commands, addresses, and data to the memory device1200. The memory controller1100may be connected to a host (although it is not shown in the drawings), and receive a request for access to the memory device1200from the host.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.