Patent ID: 12219760

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

It will be understood that the terms “first,” “second,” “third,” etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an embodiment may be described as a “second” element in another embodiment.

It should be understood that descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments, unless the context clearly indicates otherwise.

As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

FIG.1is a view schematically showing an electronic system including a semiconductor device according to an embodiment of the disclosure.

Referring toFIG.1, an electronic system1000according to an embodiment of the disclosure may include a semiconductor device1100, and a controller1200electrically connected to the semiconductor device1100. The electronic system may be a storage device including one semiconductor device1100or a plurality of semiconductor devices1100, or an electronic device including the storage device. For example, the electronic system1000may be a solid state drive (SSD) device, a universal serial bus (USB) computing system, a medical device, or a communication device which includes one semiconductor device1100or a plurality of semiconductor devices1100.

The semiconductor device1100may be a non-volatile memory device. For example, the semiconductor device1100may be a NAND flash memory device. The semiconductor device1100may include a first structure1100F, and a second structure1100S disposed on the first structure1100F. In embodiments, the first structure1100F may be disposed at one side of the second structure1100S. The first structure1100F may be, for example, a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S may be, for example, a memory cell structure including a bit line BL, a common source line CSL, a plurality of word lines WL, first and second upper gate lines UL1and UL2, first and second lower gate lines LL1and LL2, and a plurality of memory cell strings CSTR disposed between the bit line BL and the common source line CSL.

In the second structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2may be varied in accordance with embodiments.

In embodiments, the upper transistors UT1and UT2may include a string selection transistor, and the lower transistors LT1and LT2may include a ground selection transistor. The lower gate lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively. The upper gate lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

The common source line CSL, the first and second lower gate lines LL1and LL2, the word lines WL, and the first and second upper gate lines UL1and UL2may be electrically connected to the decoder circuit1110via first connecting lines1115extending from the first structure1100F to the second structure1100S. The bit lines BL may be electrically connected to the page buffer1120via second connecting lines1125extending from the first structure1100F to the second structure1100S.

In the first structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation for a selection memory cell transistor of at least one of the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through input/output pads1101electrically connected to the logic circuit1130. The input/output pads1101may be electrically connected to the logic circuit1130via an input/output connecting line1135extending from the first structure1100F to the second structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In accordance with embodiments, the electronic system1000may include a plurality of semiconductor devices1100. In this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control overall operations of the electronic system1000including the controller1200. The processor1210may operate in accordance with predetermined firmware, and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221for processing communication with the semiconductor device1100. A control command for controlling the semiconductor device1100, data to be written in the memory cell transistors MCT of the semiconductor device1100, data to be read out from the memory cell transistors MCT of the semiconductor device1100, etc., may be transmitted through the NAND interface1221. The host interface1230may provide a communication function between the electronic system1000and an external host. Upon receiving a control command from an external host via the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.2is a perspective view schematically showing an electronic system including a semiconductor device according to an embodiment of the disclosure.

Referring toFIG.2, an electronic system2000according to an embodiment of the disclosure may include a main substrate2001, a controller2002mounted on the main substrate2001, at least one semiconductor package2003, and a dynamic random access memory (DRAM)2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by wiring patterns2005formed on the main substrate2001.

The main substrate2001may include a connector2006including a plurality of pins that may be coupled to an external host. The number and arrangement of the plurality of pins in the connector2006may be varied in accordance with a communication interface between the electronic system2000and the external host. In embodiments, the electronic system2000may communicate with the external host in accordance with any one of interfaces such as, for example, a universal serial bus (USB) interface, a peripheral component interconnect express (PCI-Express) interface, a serial advanced technology attachment (SATA) interface, an M-PHY interface for universal flash storage (UFS), etc. In embodiments, the electronic system2000may operate using power supplied from the external host. The electronic system2000may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller2002and the semiconductor package2003.

The controller2002may write data in the semiconductor package2003or may read out data from the semiconductor package2003. The controller2002may also increase an operation speed of the electronic system2000.

The DRAM2004may be a buffer memory that reduces a speed difference between the semiconductor package2003, which is a data storage space, and the external host. The DRAM2004, which may be included in the electronic system2000, may also operate as a type of cache memory. The DRAM2004may provide a space for temporarily storing data in a control operation for the semiconductor package2003. When the DRAM2004is included in the electronic system2000, the controller2002may further include a DRAM controller that controls the DRAM2004, in addition to the NAND controller that controls the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003b, which may be spaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200disposed on the package substrate2100, bonding layers2300respectively disposed at lower surfaces of the semiconductor chips2200, a connecting structure2400that electrically connects the semiconductor chips2200and the package substrate2100, and a molding layer2500covering the semiconductor chips2200and the connecting structure2400on the package substrate2100.

The package substrate2100may be a printed circuit board (PCB) including upper package pads2130. Each of the semiconductor chips2200may include input/output pads2210. The input/output pads2210may correspond to the input/output pads1101ofFIG.1. Each of the semiconductor chips2200may include gate stack structures3210and memory channel structures3220.

In embodiments, the connecting structure2400may be bonding wires that electrically connect the input/output pads2210and the upper package pads2130, respectively. Accordingly, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200thereof may be electrically interconnected in a wire bonding manner, and may be electrically connected to the corresponding upper package pads2130of the package substrate2100. In accordance with embodiments, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically interconnected by a connecting structure including through-silicon vias (TSVs) in place of the bonding wire type connecting structure2400.

In embodiments, the controller2002and the semiconductor chips2200may be included in one package. In an embodiment, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate different from the main substrate2001. In this case, the controller2002and the semiconductor chips2200may be interconnected by wirings formed at the interposer substrate.

FIGS.3and4are cross-sectional views schematically showing semiconductor packages according to an embodiment of the disclosure.FIG.3corresponds to a cross-sectional view taken along line I-I′ inFIG.2.FIG.4corresponds to a cross-sectional view taken along line II-II′ inFIG.2.

Referring toFIG.3, the package substrate2100included in the semiconductor package2003may be a printed circuit board. The package substrate2100may include a package substrate body2120, upper package pads2130disposed at an upper surface of the substrate body2120, lower pads2125disposed at a lower surface of the package substrate body2120or exposed through the lower surface of the package substrate body2120, and inner wirings2135electrically connecting the upper package pads2130and the lower pads2125within the package substrate body2120. The upper package pads2130may be electrically connected to the connecting structures2400. The lower pads2125may be connected to the wiring patterns2005of the main substrate2010of the electronic system2000, as shown inFIG.2, via, for example, interconnections2800.

Each of the semiconductor chips2200may include a semiconductor substrate3010, and a first structure3100and a second structure3200sequentially stacked on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region including peripheral wirings3110. The second structure3200may include a common source line3205, a gate stack structure3210disposed on the common source line3205, memory channel structures3220and isolation structures3230extending through the gate stack structure3210, bit lines3240electrically connected to the memory channel structures3220, and gate connecting wirings electrically connected to word lines (see WL inFIG.1) of the gate stack structure3210.

Each of the semiconductor chips2200may include a through-wiring3245electrically connected to the peripheral wirings3110of the first structure3100while extending into the second structure3200. The through-wiring3245may extend through the gate stack structure3210, and may be disposed outside the gate stack structure3210. Each of the semiconductor chips2200may further include an input/output connecting wiring3265electrically connected to the peripheral wirings3110of the first structure3100while extending into the second structure3200, and an input/output pad2210electrically connected to the input/output connecting wiring3265.

Referring toFIG.4, the semiconductor package2003may be a chip-to-chip (C2C) structure. The C2C structure may mean a structure in which an upper chip including a cell region is manufactured on a first wafer, a lower chip including a peripheral circuit region is manufactured on a second wafer different from the first wafer, and the upper chip and the lower chip are interconnected in a bonding manner using a bonding method. For example, a bonding method may mean a method in which a bonding metal formed at an uppermost metal layer of the upper chip and a bonding metal formed at an uppermost metal layer of the lower chip are electrically interconnected. For example, when the bonding metal is made of copper (Cu), the bonding method may be a Cu—Cu bonding method. The bonding metal may also be made of, for example, aluminum or tungsten.

FIG.5is a cross-sectional view of a portion of a semiconductor chip according to an embodiment of the disclosure.FIG.6is a plan view corresponding to a portion ofFIG.5taken along line III-III′ inFIG.5.FIG.7is an enlarged cross-sectional view of region B inFIG.5.FIG.8is an enlarged cross-sectional view of region C inFIG.5.

FIG.5corresponds to a cross-sectional view taken along line IV-IV′ inFIG.6, andFIG.6corresponds to region A inFIG.2. InFIG.6, positions where vertical structures VS, dummy vertical structure DVS, and common source plugs CSP will be formed are shown by dotted lines to represent relative positions of elements.

Referring toFIGS.5to8, a semiconductor substrate10may correspond to the semiconductor substrate3010and/or the first structure3100described with reference toFIGS.3and4. The substrate10may include a cell array region CAR and a connecting region CNR. The cell array region CAR may be a region in which cells that store data are disposed. The connecting area CNR may be a region in which a peripheral circuit that provides an electrical signal for data storage to the cell array region CAR is disposed.

The substrate10may be a semiconductor substrate such as, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A well region101V may be provided at an upper portion of the substrate10within the substrate10. The substrate10may have a first conductivity type, and the well region10W may include impurities having a second conductivity type different from the first conductivity type. For example, the first conductivity type may be P type, and the second conductivity type may be N type. In accordance with some embodiments, the well region10W may be omitted. In an embodiment, an upper surface of the cell array region CAR of the substrate10may be a flat surface.

A source structure SC, a support pattern SP, and an electrode structure ST may be sequentially stacked on the substrate10. The source structure SC and the electrode structure ST may be sequentially stacked in a first direction D1(thickness direction) perpendicular to an upper surface of the substrate10.

The source structure SC may be interposed between the substrate10and the electrode structure ST, and may be provided on the well region10W. In some embodiments, the source structure SC may be provided on the substrate10or the well region10W. The source structure SC may include the common source line CSL described with reference toFIG.1.

The source structure SC may extend under the electrode structure ST in a second direction D2parallel to the upper surface of the substrate10.

In an embodiment, the source structure SC may be directly disposed on (e.g., may directly contact) the substrate10. For example, the source structure SC may directly contact the well region10W. In some embodiments, an insulating film may be provided between the source structure SC and the well region10W.

In an embodiment, the source structure SC may include a semiconductor material doped with an impurity having a second conductivity type. For example, the source structure SC may include polysilicon doped with an N-type impurity (for example, phosphorous (P) or arsenic (As)). In accordance with an embodiment, the source structure SC may have recessed side surfaces.

In an embodiment, the source structure SC may include oxidized regions SCoa oxidized to a predetermined thickness at portions of the source structure SC contacting common source plugs CSP, respectively.

The support pattern SP may support the electrode structure ST from the substrate10or the well region10W. The support pattern SP may be disposed on the source structure SC at a portion thereof. The support pattern SP may be directly interposed between the substrate10or the well region10W and the electrode structure ST at the other portion thereof.

In an embodiment, the support pattern SP may overlap at least a part of regions where the common source plugs CSP are disposed, regions where the dummy vertical structures DVS are disposed, and the connecting region CNR. In an embodiment, the support pattern SP may extend along regions where the dummy vertical structures DVS in the cell array region CAR are disposed (for example, in the second direction D2). In accordance with an embodiment, the support pattern SP may be disposed over the entire surface of the connecting region CNR.

The support pattern SP may include a semiconductor material doped with an impurity having a second conductivity type. For example, the support pattern SP may include polysilicon doped with an N-type impurity (for example, phosphorous (P) or arsenic (As)). In an embodiment, the impurity concentration of the support pattern SP may differ from the impurity concentration of the source structure SC. For example, the impurity concentration of the support pattern SP may be lower than the impurity concentration of the source structure SC. That is, the concentration of the N-type impurity may be greater in the source structure SC than in the support pattern SP. The etch selectivity of the support pattern SP may differ from the etch selectivity of the source structure SC.

The other portion of the support pattern SP may cover a portion of an upper surface of the source structure SC, and may extend to the recessed side surfaces of the source structure SC to cover the recessed side surfaces. In an embodiment, the one portion of the support pattern SP may cover the recessed side surfaces of the source structure SC, and may contact the substrate10or the well region10W.

In an embodiment, the source structure SC may be locally provided on the cell array region CAR, and the support pattern SP may be provided on both the cell array region CAR and the connecting area CNR.

The electrode structure ST may extend from the cell array region CAR to the connecting area CNR in the second direction D2parallel to the upper surface of the substrate10.

The electrode structure ST may include a lower electrode structure LST, an upper electrode structure UST, and a planarizing insulating film50provided between the lower electrode structure LST and the upper electrode structure UST. The planarizing insulating film50may also be referred to as a second insulating film. The lower electrode structure LST may include lower gate electrodes111,112and113and lower insulating films110awhich are alternately stacked on the source structure SC in the first direction D1. The lower insulating films110amay also be referred to as first insulating films. The upper electrode structure UST may include upper gate electrodes114and115and upper insulating films110bwhich are alternately stacked on the planarizing insulating film50in the first direction D1. The upper insulating films110bmay also be referred to as third insulating films. The numbers of the lower gate electrodes111,112and113, the lower insulating films110a, the upper gate electrodes114and115, and the upper insulating films110bare not limited to those shown in the drawings, and may vary according to embodiments.

The planarizing insulating film50may be interposed between an uppermost one of the lower gate electrodes111,112and113, that is, the uppermost lower gate electrode113, and a lowermost one of the gate electrodes114. Each of the lower insulating films110a, the upper insulating films110b, and the planarizing insulating film50may have a thickness in the first direction D1. The planarizing insulating film50may have a greater thickness than the lower and upper insulating films110aand110b. An uppermost one of the lower and upper insulating films110aand110b, that is, the uppermost insulating film110b, may be thicker than the remaining ones of the lower and upper insulating films110aand110b.

Each of the lower insulating films110a, the upper insulating films110b, and the planarizing insulating film50may include, for example, a silicon oxide film and/or a low-k dielectric film.

The lower gate electrodes111,112and113may include a cell gate electrode111, an erase control gate electrode112disposed on the cell gate electrode111, and a ground selection gate electrode113disposed on the erase control gate electrode112. A lowermost one of the lower gate electrodes111,112and113(for example, the cell gate electrode111) may be adjacent to the source structure SC. The erase control gate electrode112and the ground selection gate electrode113may correspond to respective electrodes of the lower transistors LT1and LT2shown inFIG.1.

A lowermost one of the lower insulating films110amay be interposed between the cell gate electrode111and the support pattern SP (or the source structure SC). The erase control gate electrode112may be used as a gate electrode of an erase control transistor controlling an erase operation (for example, one of the lower transistors LT1and LT2shown inFIG.1). In an embodiment, the erase control gate electrode112may have a structure extending in the second direction D2. In an embodiment, the ground selection gate electrode113may have the form of a line extending in the second direction D2, and the ground selection gate electrode113may be spaced apart from a ground selection gate electrode adjacent thereto. The ground selection gate electrode113may be disposed on the erase control gate electrode112. The ground selection gate electrode113may be used as a gate electrode of a ground selection transistor (for example, the other one of the lower transistors LT1and LT2shown inFIG.1).

The upper gate electrodes114and115may include cell gate electrodes114and a string selection gate electrode115. The cell gate electrodes114may be provided between the ground selection gate electrode113and the string selection gate electrode115, and may be disposed at different heights from the upper surface of the substrate10. The cell gate electrodes114may be used as gate electrodes of the memory cell transistors MCT shown inFIG.1. The upper gate electrodes114and115may include a plurality of cell gate electrodes114, but are not limited to the number of the cell gate electrodes114as shown. In this case, the ground selection gate electrodes113may be disposed under line portions of a lowermost one of the cell gate electrodes114, respectively.

The string selection gate electrode115may include a pair of string selection gate electrodes115_1and115_2horizontally spaced apart from each other. The pair of string selection gate electrodes115_1and115_2may be spaced apart from each other in a third direction D3. The pair of string selection gate electrodes115_1and115_2may be isolated from each other by an isolation insulating film which is interposed between the string selection gate electrodes115_1and115_2while having the form of a line extending in the second direction D2and including an insulating material (for example, a silicon oxide film). The string selection gate electrode115may be used as the gate electrode of the string selection transistor described with reference toFIG.1. In accordance with some embodiments, an additional string selection gate electrode115may be provided between an uppermost one of the cell gate electrodes114and the string selection gate electrode115. In this case, the additional string selection gate electrode115may include a pair of additional string selection gate electrodes115_1and115_2spaced apart from each other in the third direction D3, and the string selection gate electrodes114may be used as the gate electrodes of the string selection transistors described with reference toFIG.1. In an embodiment, lengths of the gate electrodes111,112,113and114of the electrode structure ST (lengths in the second direction D2) may be gradually reduced as the gate electrodes111,112,113and114are disposed farther from the substrate10. The gate electrodes111,112,113and114of the electrode structure ST may include electrode pads forming a stepped structure in the connecting region CNR.

Each of the lower gate electrodes111,112and113and the upper gate electrodes114may include a doped semiconductor (for example, doped silicon, etc.), a metal (for example, tungsten, copper, aluminum, etc.), a conductive metal nitride (for example, titanium nitride, tantalum nitride, etc.) and/or a transition metal (for example, titanium, tantalum, etc.).

The vertical structures VS may be disposed in the cell array region CAR of the substrate10. A part of the dummy vertical structures DVS may be disposed in the cell array region CAR of the substrate10, and the other part of the dummy vertical structures DVS may be disposed in the connecting area CNR of the substrate10.

Each of the vertical structures VS may extend in the first direction D1such that the vertical structure VS may extend through the electrode structure ST. That is, the vertical structures VS may extend through the upper electrode structure UST, the planarizing insulating film50, and the lower electrode structure LST in a vertical direction (for example, the first direction D1). In an embodiment, each of the vertical structures VS does not extend through the source structure SC and the support pattern SP. That is, in an embodiment, each of the vertical structures VS may be directly disposed on (e.g., may directly contact) the source structure SC or the support pattern SP. For example, each of the vertical structures VS may be disposed above the source structure SC such that the vertical structure VS may contact the source structure SC at a bottom portion thereof. For example, the vertical structures VS may be arranged in the second direction D2in a zigzag manner when viewed in a plan view. In an embodiment, each of the dummy vertical structures DVS may extend through a corresponding one of the electrode pads and the electrode structure ST under the corresponding electrode pad. Each of the vertical structures VS and the dummy vertical structures DVS may have a width in a direction parallel to the upper surface of the substrate10. In accordance with an embodiment, widths of the vertical structures DVS disposed in the connecting region CNR may be greater than widths of the vertical structures VS, and widths of the dummy vertical structures DVS disposed in the cell array region CAR may be about equal to the widths of the vertical structures VS. In an embodiment, depths of the dummy vertical structures DVS disposed in the cell array region CAR may be greater than depths of the vertical structures VS.

Each of the vertical structures VS may include a vertical semiconductor pattern VSP. The vertical semiconductor pattern VSP may extend in the first direction D1such that the vertical semiconductor pattern VSP may extend through the electrode structure ST and may extend to an upper surface of the source structure SC. The vertical semiconductor pattern VSP may have the form of a pipe closed at a lower end thereof.

In an embodiment, the vertical semiconductor pattern VSP may have the form of a cup opened at an upper end thereof while being closed at a lower end thereof. That is, in an embodiment, the vertical semiconductor pattern VSP may have a cup shape having an opened upper end and a closed lower end. For example, the cup shape of the vertical semiconductor pattern VSP may include a bottom portion VSPb and a side portion VSPa extending upward from the bottom portion VSPb, thus forming the opened upper end and the closed lower end. The vertical semiconductor pattern VSP may contact the source structure SC. In an embodiment, the bottom portion VSPb of the vertical semiconductor pattern VSP may contact the source structure SC.

The vertical semiconductor pattern VSP may include a semiconductor material such as, for example, silicon (Si), germanium (Ge) or a compound thereof. In addition, the vertical semiconductor pattern VSP may be a semiconductor doped with an impurity or an intrinsic semiconductor in an impurity-undoped state. The vertical semiconductor pattern VSP may be used as channels of the upper transistors UT1and UT2, the lower transistors LT1and LT2, and the memory cell transistors MCT described with reference toFIG.1.

Each of the vertical structures VS may include a data storage pattern DSP interposed between the vertical semiconductor pattern VSP and the electrode structure ST. The data storage pattern DSP may extend in the first direction D1, and may surround a side wall of the vertical semiconductor pattern VSP. The data storage pattern DSP may have the form of a pipe opened at upper and lower ends thereof. The data storage pattern DSP may contact the source structure SC at a bottom portion thereof. The data storage pattern DSP may include a data storage film of a NAND flash memory device. The data storage pattern DSP may include a charge storage film172disposed between the vertical semiconductor pattern VSP and the electrode structure ST, a blocking insulating film171disposed between the electrode structure ST and the charge storage film172, and a tunnel insulating film173disposed between the vertical semiconductor pattern VSP and the charge storage film172. For example, the charge storage film172may include at least one of a silicon nitride film, a silicon oxynitride film, a silicon-rich nitride film, nanocrystalline silicon, or a laminated trap layer. The blocking insulating film171may include a material having a greater bandgap than the charge storage film172. The blocking insulating film171may include a high-k dielectric film such as, for example, an aluminum oxide film, a hafnium oxide film, etc. The tunnel insulating film173may include a material having a greater bandgap than the charge storage film172. For example, the tunnel insulating film173may include a silicon oxide film.

Each of the vertical structures VS may include an insulating pattern160filling an interior of the vertical semiconductor pattern VSP. The insulating pattern160may include, for example, a silicon oxide.

Each of the vertical structures VS may include a conductive pad150disposed on the vertical semiconductor pattern VSP. The conductive pattern may cover an upper surface of the insulating pattern160and an uppermost surface of the vertical semiconductor pattern VSP. The conductive pad150may include an impurity-doped semiconductor material and/or a conductive material.

The data storage pattern DSP may extend from a side surface of the vertical semiconductor pattern VSP to a surface of the conductive pad150such that the data storage pattern DSP is disposed on the surface of the conductive pad150. The data storage pattern DSP may surround the side surface of the conductive pad150, and an uppermost surface of the data storage pattern DSP may be substantially flush with an upper surface of the conductive pad150.

Both the data storage pattern DSP and the vertical semiconductor pattern VSP may be disposed above the source structure SC.

Each of the dummy vertical structures DVS disposed in the cell array region CAR may include a dummy data storage pattern DSPa. In an embodiment, the data storage pattern DSPa may have the form of a cup opened at an upper end thereof while being closed at a lower end thereof. The data storage pattern DSPa may include portions171a,172aand173aforming a side wall surrounded by the electrode structure ST, and portions171b,172band173bforming a bottom portion. The dummy vertical structures DVS disposed in the cell array region CAR may be directly disposed on (e.g., may directly contact) the support pattern SP. The portions171b,172band173b, which form the bottom portion, may contact the support pattern SP. In an embodiment, the dummy vertical structures DVS disposed in the cell array region CAR may extend into the support pattern ST. In an embodiment, the dummy vertical structures DVS disposed in the cell array region CAR do not extend through the support pattern SP. The portions171b,172band173b, which form the bottom portion, may be disposed below an upper surface of the support pattern ST.

Common source plugs CSP may be provided at opposite sides of the electrode structure ST, respectively. The common source plugs CSP may extend in the third direction D3, and may be disposed in the cell array region CAR and the connecting area CNR. The common source plugs CSP may be connected to the substrate10or the well region10W in a predetermined region.

The common source plugs CSP may extend through the source structure SC and the support pattern SP in the predetermined region. The common source plugs CSP may be directly disposed on (e.g., may directly contact) the support pattern SP in a region other than the predetermined region. The common source plugs CSP may extend in the second direction D2, and may be spaced apart from each other in the third direction D3under the condition that the electrode structure ST is interposed between the common source plugs CSP. For example, the common source plugs CSP may include a conductive material. In an embodiment, lowermost ends of the common source plugs CSP may be directly disposed on (e.g., may directly contact) the substrate10or the well region10W in a predetermined region. In this case, the upper surface of the substrate10or the well region10W may be substantially flat, irrespective of whether the upper surface contacts the common source plugs CSP.

Side insulating spacers SS may be provided at opposite sides of the electrode structure ST, respectively. Each of the side insulating spacers SS may be interposed between a corresponding one of the common source plugs CSP and the electrode structure ST. Each of the side insulating spacers SS may extend between the corresponding common source plug CSP and the source structure SC and/or the support pattern SP, and may contact the substrate10, the well region10W, or the support pattern SP. For example, the side insulating spacers SS may include polysilicon or silicon nitride.

A capping insulating film120may cover an upper surface of the electrode structure ST, an upper surface of the conductive pad150, and an upper surface of the upper insulating film110b. An upper surface of the capping insulating film120may be substantially flush with upper surfaces of the common source plugs CSP.

An interlayer insulating film130may be provided on the capping insulating film120and may cover the upper surfaces of the common source plugs CSP.

The lower insulating film110a, the upper insulating film110b, the capping insulating film120, and the interlayer insulating film130may include an insulating material (for example, silicon oxide).

A first contact125may be provided on the conductive pad150. The first contact125may extend through the capping insulating film120such that the first contact125may be connected to the conductive pad150. A second contact135may extend through the interlayer insulating film130such that the second contact135may be connected to the first contact125. The first contact125and the second contact135may include a conductive material.

Bit lines BL may be provided on the interlayer insulating film130. The bit lines BL may extend in the third direction D3while being spaced apart from one another in the second direction D2.

Each of the dummy vertical structures DVS disposed in the cell array region CAR may be a cell dummy vertical structure including a cell dummy vertical semiconductor pattern that is not connected to the first contact125or the second contact135. Each vertical semiconductor pattern VSP of the vertical structures VS, except the cell dummy vertical structures, may be electrically connected to a corresponding one of the bit lines BL via the first contact125and the second contact135. The bit lines BL may include a conductive material.

Conductive contacts CT formed in the connecting region CNR may be connected to electrode pads of the gate electrodes111,112,113and114, respectively.

FIGS.9to17are cross-sectional views showing a method of manufacturing a semiconductor chip in accordance with an embodiment of the disclosure.

The semiconductor chip manufacturing method may include of the processes described with reference to FUGs.9to17.

First, referring toFIG.9, a first sacrificial layer220, a support pattern SP, lower sacrificial structures111s,112sand113s, lower insulating films110a, and a planarizing insulating film50may be formed on a substrate10or a well region10W.

After covering an upper surface of the substrate10, the first sacrificial layer220may be formed with a trench TRC exposing a portion of the upper surface of the substrate10or an upper surface of the well region10W. The support pattern SP on the first sacrificial layer220may be formed to extend into the trench TRC such that the support pattern SP may include a region contacting the substrate10or the well region10W.

In an embodiment, the first sacrificial layer220may include a first sub-sacrificial film221, a second sub-sacrificial film222, and a third sub-sacrificial film223, which are sequentially stacked. The second sub-sacrificial film222may be disposed between the first sub-sacrificial film221and the third sub-sacrificial film223. The second sub-sacrificial film222may include at least one of, for example, a silicon nitride film, a silicon oxynitride film, a silicon-rich nitride film, nanocrystalline silicon, or a laminated trap layer. Each of the first sub-sacrificial film221and the third sub-sacrificial film223may include, for example, an aluminum oxide film, a hafnium oxide film, or a silicon oxide film. In an embodiment, etch selectivity of each of the first sub-sacrificial film221, the second sub-sacrificial film222, and the third sub-sacrificial film223of the first sacrificial layer220may differ from etch selectivity of each of a blocking insulating film171, a charge storage film172, and a tunnel insulating film173of a data storage pattern DSP.

Thereafter, a plurality of first channel holes CHHa and a plurality of first word line cuts WLCa may be formed to extend through the lower sacrificial structures111s,112sand113s, the lower insulating films110a, and the planarizing insulating film50. The plurality of first channel holes CHHa and the plurality of first word line cuts WLCa may be formed through execution of an anisotropic etching process for the lower sacrificial structures111s,112sand113s, the lower insulating films110a, the planarizing insulating film50, and the support pattern SP. In accordance with an embodiment, an anisotropic etching process is performed for the lower sacrificial structures111s,112sand113s, the lower insulating films110a, and the planarizing insulating film50while using the support pattern SP as an etch stop layer, and an isotropic etching process is subsequently performed for the support pattern SP while using the first sacrificial layer220as an etch stop layer. Positions where the plurality of first word line cuts WLCa are formed may include positions where common source plugs CSP will be produced. Positions where the plurality of first channel holes CHHa are formed may include positions where vertical structures VS and dummy vertical structures DVS will be produced. The first channel holes CHHa formed at the positions where the dummy vertical structures DVS will be produced may be referred to as dummy channel holes.

In an embodiment, the support pattern SP may be removed from regions where the plurality of first channel holes CHHa and the plurality of first word line cuts WLCa overlap the first sacrificial layer220, thereby exposing the first sacrificial layer220. In an embodiment, the support pattern SP is not removed from regions where the plurality of first channel holes CHHa and the plurality of first word line cuts WLCa overlap with the trench TRC and, as such, may be exposed at the regions. In an embodiment, the plurality of first channel holes CHHa and the plurality of first word line cuts WLCa may have a greater depth in the regions exposing the support pattern SP than in the regions from which the support pattern SP is removed. That is, the support pattern SP may be over-etched in the trench TRC through an anisotropic etching process for forming the plurality of first channel holes CHHa and the plurality of first word line cuts WLCa.

Subsequently, referring toFIG.10, a second sacrificial layer210filling the plurality of first channel holes CHHa and the plurality of first word line cuts WLCa may be formed. For example, the second sacrificial layer210may include polysilicon or tungsten (W).

Thereafter, referring toFIG.11, upper sacrificial structures114sand115smay be formed on the lower sacrificial structures111s,112sand113s, the lower insulating films110a, the planarizing insulating film50, and the second sacrificial layer210. Subsequently, a plurality of second channel holes CHHb may be formed to extend through the upper sacrificial structures114sand115s. The plurality of second channel holes CHHb may be formed by etching the upper sacrificial structures114sand115sthrough an anisotropic etching process. Positions where the plurality of second channel holes CHHb is formed may overlap positions where the plurality of first channel holes CHHa is formed, respectively. The plurality of second channel holes CHHb may extend through the upper sacrificial structures114sand115s, thereby exposing the second sacrificial layer210.

The second sacrificial layer210filling the plurality of first channel holes CHHa may then be removed. The second sacrificial layer210may be removed through an etching process having etch selectivity with respect to the lower sacrificial structures111s,112sand113s, the upper sacrificial structures114sand115s, and the first sacrificial layer220. Accordingly, the plurality of second channel holes CHHb formed at positions corresponding to the plurality of first channel holes CHHa may be connected to the plurality of first channel holes CHHa, respectively.

Thereafter, referring toFIG.12, a data storage pattern DSPa, a vertical semiconductor pattern VSP, an insulating pattern160, and a conductive pad150may be formed at the plurality of first channel holes CHHa and the plurality of second channel holes CHHb. In an embodiment, the data storage pattern DSPa, the vertical semiconductor pattern VSP, the insulating pattern160, and the conductive pad150may be formed by depositing materials corresponding thereto to uniform thicknesses, respectively, using a method such as, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD), and then performing a planarization process.

Subsequently, referring toFIG.13, a capping insulating film120may be formed on the upper sacrificial structures114sand115s. A plurality of second word line cuts WLCb may then be formed. The plurality of second word line cuts WLCb may be formed through an etching process in which the capping insulating film120and the upper sacrificial structures114sand115sare removed from regions overlapping the remaining portions of the second sacrificial layer210that have not been removed, and the remaining portions of the second sacrificial layer210are then removed. The etching process may be an etching process having etch selectivity with respect to the capping insulating film120, the lower sacrificial structures111s,112sand113s, and the upper sacrificial structures114sand115s. In accordance with an embodiment, an etching process having etch selectivity with respect to the capping insulating film120and the upper sacrificial structures114sand115smay be performed, and an etching process for removing the second sacrificial layer210may then be performed.

Positions where the plurality of second word line cuts WLCb is produced may overlap the positions where the plurality of first word line cuts WLCa was produced, respectively. The plurality of second word line cuts WLCb may expose the sacrificial layer220and/or the support pattern SP.

Subsequently, referring toFIG.14, a side insulating spacer SS may be formed on an inner surface of each of the second word line cuts WLCb. The side insulating spacer SS may be formed to cover the inner surface of the second word line cut WLCb to a uniform thickness while filling the second word line cut WLCb.

Thereafter, referring toFIG.15, the first sacrificial layer220may be removed. The first sacrificial layer220may be removed through an etching process having etch selectivity with respect to the substrate10and the support pattern SP. Referring toFIGS.14and15, in accordance with an embodiment, when the first sacrificial layer220is removed, portions171b,172band173bforming a bottom portion of the data storage pattern DSPa in each of the vertical structures VS may also be removed and, as such, a shape of the data storage pattern DSP may be provided.

Subsequently, referring toFIG.16, a source structure material SCa may be formed under the support pattern SP. In an embodiment, the source structure material SCa may be injected through the plurality of second word line cuts WLCb. The source structure material SCA may be exposed in regions overlapping regions where the plurality of second word line cuts WLCb is formed.

In accordance with an embodiment, the source structure material SCa may be formed along inner surfaces (side walls) of the plurality of second word line cuts WLCb, and may be oxidized in the exposed regions thereof.

Thereafter, referring toFIGS.16and17, the source structure material SCa may be removed from regions including the exposed regions through an etch-back process. An oxidized region SCoa may be formed by oxidizing, to a predetermined thickness, an inner surface of the source structure material SCa exposed through the etch-back process. As a result, a source structure including the oxidized region SCoa may be formed.

In an embodiment, a replacement process may then be performed to replace the lower sacrificial structures111s,112sand113sand the upper sacrificial structures114sand115swith a lower electrode structure LST and an upper electrode structure UST.

In accordance with an embodiment, a nitride may remain inside the plurality of second word line cuts WLCb after removal of the source structure material SCa from predetermined regions through an etch-back process. In this case, a process for removing the nitride may be performed. In this case, an oxidized portion of the source structure material SCa (including, for example, the oxidized region SCoa) may protect the source structure from external factors. For example, the oxidized region SCoa may prevent a non-oxidized region of the source structure from being exposed and, as such, may protect the source structure in a subsequent process.

Next, a semiconductor chip according to an embodiment of the disclosure will be described. For convenience of explanation, a further description of elements and technical aspects previously described may be omitted.

FIG.18is a cross-sectional view showing a portion of a semiconductor chip according to an embodiment of the disclosure.

Referring toFIGS.6,7and18, the semiconductor chip according to an embodiment differs from an embodiment ofFIG.7in that a source structure SC_1contacts a lower insulating film110aand a side portion VSPa of a vertical semiconductor pattern VSP.

In an embodiment, the source structure SC_1may contact a lowermost one of lower insulating films110adisposed on a support pattern SP. In an embodiment, the height of the source structure SC_1may be lower than the height of a lower surface of a lowermost one of lower gate electrodes111,112and113(for example, a cell gate electrode111). That is, in an embodiment the source structure SC_1does not contact the lower gate electrodes111,112and113.

In an embodiment, the source structure SC_1may contact a bottom portion VSPb of the vertical semiconductor pattern VSP and a part of the side portion VSPa of the vertical semiconductor pattern VSP.

FIG.19is a cross-sectional view showing a portion of a semiconductor chip according to an embodiment of the disclosure.

Referring toFIGS.6,7and19, the semiconductor chip according to an embodiment differs from an embodiment ofFIG.7in that a bottom portion VSPb of a vertical semiconductor pattern VSP_1is omitted.

In an embodiment, the vertical semiconductor pattern VSP_1may have the form of a pipe opened at upper and lower ends thereof. In this case, the height of an upper surface of a source structure SC_2may be greater than the height of an upper surface of a support pattern SP (in regions contacting vertical structures VS). The height of the upper surface of the source structure SC_2may be smaller than the height of a lower surface of an erase control gate electrode112.

As apparent from the above description, in accordance with embodiments of the disclosure, a common source line may be connected to lower portions of channels.

In addition, in the manufacture of a semiconductor chip, a high aspect ratio contact (HARC) etching process may be efficiently performed.

While the present disclosure has been particularly shown and described with reference to the embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.