Patent ID: 12245470

DETAILED DESCRIPTION

Reference will now be made in more detail to aspects of some example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the example embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, in the present specification, “at least one of A and B” indicates only A, only B, both A and B, or variations thereof.

It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, because sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.

In the present specification, “A and/or B” means A or B, or A and B.

It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, it may be “directly connected” to the other layer, region, or component and/or may be “indirectly connected” to other layer, region, or component with other layer, region, or component interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “electrically connected” to another layer, region, or component, it may be “directly electrically connected” to the other layer, region, or component and/or may be “indirectly electrically connected” to other layer, region, or component with other layer, region, or component interposed therebetween.

FIG.1is a perspective view of a display device1according to some example embodiments.

Referring toFIG.1, the display device1includes a first area OA and a display area DA, which is a second area at least partially surrounding the first area OA. The display device1may provide an image (e.g., a set or predetermined image) by using light emitted from a plurality of pixels arranged (e.g., located or placed) in the display area DA. The first area OA may be entirely surrounded by the display area DA. The first area OA may be an area in which a component described below with reference toFIG.2is arranged or located.

A middle area MA as a third area may be arranged (e.g., located) between the first area OA and the display area DA, which is the second area. The display area DA may be surrounded by a peripheral area PA, which is a fourth area. According to some example embodiments the middle area MA and the peripheral area PA may be a non-display area in which pixels are not placed. The middle area MA may be entirely surrounded by the display area DA, and the display area DA may be entirely surrounded by the peripheral area PA.

Hereinafter, though an organic light-emitting display device is described as an example of the display device1according to some example embodiments, the display device is not limited thereto. According to some example embodiments, the display device1may be a display device such as an inorganic light-emitting display and a quantum dot light-emitting display.

Though it is shown inFIG.1that one first area OA is provided and has a circular shape, the embodiments are not limited thereto. The number of first areas OA may be two or more. Each first area OA may have various shapes such as a circular shape, an elliptical shape, a polygonal shape, a star shape, and a diamond shape.

FIGS.2and3are cross-sectional views of the display device1according to some example embodiments, respectively, taken along the line II-II′ ofFIG.1.

Referring toFIG.2, the display device1may include a display panel10, an input sensing layer40, and an optical functional layer50placed on the display panel10. The display panel10, the input sensing layer40, and the optical functional layer50may be covered by a window60. The display device1may be various kinds of electronic apparatuses such as mobile phones, notebook computers, and smartwatches.

The display panel10may display an image. The display panel10includes pixels located in the display area DA. Each of the pixels may include a display element and a pixel circuit connected to the display element. The display element may be an organic light-emitting diode or a quantum dot organic light-emitting diode.

The input sensing layer40obtains coordinate information corresponding to an external input, for example, a touch event. The input sensing layer40may include a sensing electrode (or a touch electrode) and trace lines, the trace lines being connected to the sensing electrode. The input sensing layer40may be on the display panel10. The input sensing layer40may sense an external input by using a mutual cap method and/or a self cap method.

In some embodiments, the input sensing layer40may be directly on the display panel10, or separately formed and then coupled to the display panel10by using an adhesive layer such as an optically clear adhesive. For example, the input sensing layer40may be successively formed after a process of forming the display panel10. In this case, the input sensing layer40may be a portion of the display panel10and an adhesive layer may not be placed between the input sensing layer40and the display panel10. Though it is shown inFIG.2that the input sensing layer40is located between the display panel10and the optical functional layer50, the input sensing layer40may be on the optical functional layer50in some other embodiments.

The optical functional layer50may include a reflection prevention layer. The reflection prevention layer may reduce reflectivity of the light (e.g., external light) incident towards/on the display panel10from the outside through the window60. The reflection prevention layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal-type retarder. The retarder may include a λ/2 retarder and/or a λ/4 retarder. The polarizer may include a film-type polarizer or a liquid crystal-type polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal-type polarizer may include liquid crystals placed in a set or predetermined arrangement. Each of the retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves, or a protective film may be defined as a base layer of the reflection prevention layer.

In some other embodiments, the reflection prevention layer may include a black matrix and color filters. The color filters may be placed by taking into account colors of light emitted respectively from the pixels of the display panel10. In some other embodiments, the reflection prevention layer may include a destructive interference structure. The destructive interference structure may include a first reflection layer and a second reflection layer respectively placed on different layers. First-reflected light and second-reflected light respectively reflected by the first reflection layer and the second reflection layer may create destructive-interference and thus the reflectivity of external light may be reduced.

The optical functional layer50may also include a lens layer. The lens layer may improve emission efficiency of the light emitted from the display panel10or reduce color deviation. The lens layer may include a layer having a concave or convex lens shape and/or include a plurality of layers having different refractive indexes. The optical functional layer50may include both the reflection prevention layer and the lens layer, or one of these layers.

In an embodiment, the optical functional layer50may be successively formed after a process of forming the display panel10and/or the input sensing layer40. In this case, an adhesive layer may not be placed between the optical functional layer50and the display panel10and/or the input sensing layer40.

The display panel10, the input sensing layer40, and/or the optical functional layer50each may include an opening. With regard to this, it is shown inFIG.2that the display panel10, the input sensing layer40, and the optical functional layer50respectively include a first opening10H, a second opening40H, and a third opening50H, the first opening, the second opening40H, and the third opening50H overlapping one another. The first opening10H, the second opening40H, and the third opening50H may correspond to the first area OA. In some other embodiments, at least one of the display panel10, the input sensing layer40, and the optical functional layer50may not include an opening. For example, one or two of the display panel10, the input sensing layer40, and the optical functional layer50may not include an opening. Alternatively, as shown inFIG.3, the display panel10, the input sensing layer40, and the optical functional layer50may not include an opening.

As described above, the first area OA may be a component area (e.g., a sensor area, a camera area, a speaker area, etc.) in which a component20is located, the component20may add various functions to the display device1. As shown inFIG.2, the component20may be located inside the first to third openings10H,40H, and50H. Alternatively, as shown inFIG.3, the component20may be located below the display panel10.

The component20may include an electronic element. For example, the component20may include an electronic element that uses light or sound. For example, an electronic element may be a sensor such as an infrared sensor that emits and/or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure a distance or recognize a fingerprint, a small lamp that outputs light, or a speaker that outputs sound. An electronic element that uses light may use light in various wavelength bands such as visible light, infrared light, and ultraviolet light. In an embodiment, the first area OA may be a transmission area through which light and/or sound, which are output from the component20to the outside or propagate toward the electronic element from the outside, may pass.

In the case where the display device1is used as a smartwatch or as an instrument panel for an automobile, the component20may be a member such as clock hands or a needle indicating set or predetermined information (e.g., the velocity of a vehicle, etc.). In the case where the display device1includes clock hands or an instrument panel for an automobile, the component20may pass through the window60and may be exposed to the outside. In such a case, the window60may include an opening corresponding to the first area OA.

The component20may include an element(s) related to a function of the display panel10as described above, or may include an element such as an accessory that increases the aesthetic sense of the display panel10. Though not shown inFIGS.2and3, a layer including an optically clear adhesive may be located between the window60and the optical functional layer50.

FIGS.4A-4Dare cross-sectional views of a display panel according to an embodiment.

Referring toFIG.4A, the display panel10includes a display layer200located on a substrate100. The substrate100may include a glass material or a polymer resin. The substrate100may include a multi-layer. For example, the substrate100may include a first base layer101, a first barrier layer102, a second base layer103, and a second barrier layer104as shown in an enlarged view ofFIG.4A.

The first base layer101and the second base layer103each may include a polymer resin. For example, the first base layer101and the second base layer103may include a polymer resin including polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose tri acetate (TAC), and cellulose acetate propionate (CAP). The polymer resin may be transparent.

The first barrier layer102and the second barrier layer104are barrier layers reducing or preventing the penetration of external foreign substances and may include a single layer or a multi-layer including an inorganic material such as silicon nitride (SiNx) and silicon oxide (SiOx).

The display layer200may include a plurality of pixels. The display layer200may include a display element layer200A and a pixel circuit layer200B, the display element layer200A including a display element for each pixel, and the pixel circuit layer200B including a pixel circuit and insulating layers for each pixel. The display element layer200A may include a pixel electrode, an opposite electrode, and a stacked structure therebetween. Each display element may be an organic light-emitting diode OLED. Each pixel circuit (e.g.,200B) may include a thin film transistor and a storage capacitor.

Display elements of the display layer200may be covered by an encapsulation member such as a thin-film encapsulation layer300. The thin-film encapsulation layer300may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In the case where the display panel10includes the substrate100and the thin-film encapsulation layer300, the substrate100including a polymer resin, and the thin-film encapsulation layer300including an inorganic encapsulation layer and an organic encapsulation layer, the flexibility of the display panel10may be improved.

The display panel10may include the first opening10H passing through the display panel10. The first opening10H may be located in the first area OA. In this case, the first area OA may be an opening area. It is shown inFIG.4Athat the substrate100and the thin-film encapsulation layer300respectively include through holes100H and300H each corresponding to the first opening10H of the display panel10. The display layer200may include a through hole200H corresponding to the first area OA.

In some other embodiments, as shown inFIG.4B, the substrate100may not include a through hole corresponding to the first area OA. The display layer200may include the through hole200H corresponding to the first area OA. The thin-film encapsulation layer300may not include a through hole corresponding to the first area OA. In some other embodiments, as shown inFIG.4C, the display layer200may not include the through hole200H corresponding to the first area OA.

Though it is shown inFIGS.4A-4Cthat the display element layer200A is not located in the first area OA, the embodiments are not limited thereto. In some other embodiments, as shown inFIG.4D, an auxiliary display element layer200C may be located in the first area OA. The auxiliary display element layer200C may include a display element that has a structure that is different from that of the display element of the display element layer200A and/or operates in a way that is different from that of the display element of the display element layer200A.

In an embodiment, each pixel of the display element layer200A may include an active-type organic light-emitting diode, and the auxiliary display element layer200C may include pixels each including a passive-type organic light-emitting diode. In the case where the auxiliary display element layer200C includes a passive-type organic light-emitting diode as a display element, there is no element constituting a pixel circuit below the passive-type organic light-emitting diode. For example, a portion of the pixel circuit layer200B under the auxiliary display element layer200C does not include a transistor and a storage capacitor.

In some other embodiments, though the auxiliary display element layer200C may include the same type of display element (e.g., an active-type organic light-emitting diode) as that of the display element layer200A, a structure of a pixel circuit therebelow may be different. For example, a pixel circuit (e.g., a pixel circuit including a light-blocking layer between a substrate and a transistor) below the auxiliary display element layer200C may have a structure different from that of a pixel circuit below the display element layer200A. Alternatively, display elements of the auxiliary display element layer200C may operate according to a control signal different from a control signal of the display elements of the display element layer200A. A component (e.g., an infrared sensor) that does not require a relatively high transmittance may be located in the first area OA in which the auxiliary display element layer200C is located. In this case, the first area OA may be a component area and an auxiliary display area.

FIG.5is a plan view of a display panel10according to an embodiment, andFIG.6is an equivalent circuit representation of one of the pixels in a display panel according to an embodiment.

Referring toFIG.5, the display panel10may include the first area OA, the display area DA, which is the second area, the middle area MA, which is the third area, and the peripheral area PA, which is the fourth area.FIG.5illustrates the substrate100of the display panel10. For example, the substrate100may include the first area OA, the display area DA, the middle area MA, and the peripheral area PA.

The display panel10includes a plurality of pixels P placed in the display area DA. As shown inFIG.6, each pixel P may include a pixel circuit PC and an organic light-emitting diode OLED as a display element, the display element being connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red, green, blue, or white light from an organic light-emitting diode OLED.

The second thin film transistor T2may include a switching thin film transistor, may be connected to a scan line SL and a data line DL, and may transfer a data voltage input to the data line DL to the first thin film transistor T1based on a switching voltage input to the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2and a driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transferred from the second thin film transistor T2and a first power voltage ELVDD supplied through the driving voltage line PL.

The first thin film transistor T1is a driving thin film transistor, may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage value (or charge) stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a set or predetermined brightness according to the driving current. An opposite electrode (e.g., a cathode) of the organic light-emitting diode OLED may receive a second power voltage ELVSS.

Though it is shown inFIG.6that the pixel circuit PC includes two thin film transistors and one storage capacitor, the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may be variously modified depending on a design of the pixel circuit PC. For example, the pixel circuit PC may further include four or more thin film transistors in addition to the two thin film transistors.

Referring toFIG.5again, the middle area MA may surround the first area OA in a plan view. The middle area MA is an area in which a display element such as an organic light-emitting diode that emits light is not placed. Signal lines may pass across the middle area MA, the signal lines providing a signal to the pixels P located around the first area OA. A scan driver1100, a data driver1200, and a main power line (not shown) may be placed in the peripheral area PA, the scan driver1100providing a scan signal to each pixel P, the data driver1200providing a data signal to each pixel P, and the main power line providing a first power voltage and a second power voltage. Although it is shown inFIG.5that the data driver1200is adjacent to one side of the substrate100, the data driver1200may be located on a flexible printed circuit board (FPCB) electrically connected to a pad located on one side of the display panel10in some other embodiments.

FIG.7is a plan view of a portion of a display panel according to an embodiment, andFIG.8is a cross-sectional view of an organic light-emitting diode of one of the pixels in a display panel according to an embodiment. For convenience of description, inFIG.8, a thin-film encapsulation layer, which is an encapsulation member, is omitted.

Referring toFIG.7, pixels P are placed around the first area OA in the display area DA. The first area OA may be defined between (e.g., among) the pixels P. For example, pixels P may be vertically placed around the first area OA in a plan view, and pixels P may be horizontally placed around the first area OA in a plan view.

As shown inFIG.8, each pixel P may include an organic light-emitting diode OLED. The organic light-emitting diode OLED may include a pixel electrode221, an opposite electrode223, and an intermediate layer222, the opposite electrode223facing the pixel electrode221, and the intermediate layer222being between the pixel electrode221and the opposite electrode223.

The pixel electrode221is located on a planarization layer PNL. The pixel electrode221may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In some other embodiments, the pixel electrode221may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. In some other embodiments, the pixel electrode221may further include a layer including ITO, IZO, ZnO, or In2O3over/under the reflective layer.

A pixel-defining layer PDL may be on the pixel electrode221. The pixel-defining layer PDL may include an opening that may expose a top surface of the pixel electrode221and cover edges of the pixel electrode221. The pixel-defining layer PDL may include an organic insulating material. Alternatively, the pixel-defining layer PDL may include an organic insulating material and an inorganic insulating material.

The intermediate layer222includes an emission layer222b. The intermediate layer222may include a first functional layer222aunder the emission layer222band/or a second functional layer222con the emission layer222b. The emission layer222bmay include a polymer or low molecular weight organic material that emits light of a set or predetermined color.

The first functional layer222amay include a single layer or a multi-layer. For example, in the case where the first functional layer222aincludes a polymer material, the first functional layer222amay be a hole transport layer (HTL), which has a single-layered structure. The first functional layer222amay include poly-(3,4)-ethylene-dihydroxy thiophene (PEDOT) or polyaniline (PANI). In the case where the first functional layer222aincludes a low molecular weight material, the first functional layer222amay include a hole injection layer (HIL) and a hole transport layer (HTL).

In some embodiments, the second functional layer222cmay be optional. For example, in the case where the first functional layer222aand the emission layer222binclude a polymer material the second functional layer222cmay be formed. The second functional layer222cmay include a single layer or a multi-layer. The second functional layer222cmay include an electron transport layer (ETL) and/or an electron injection layer (EIL).

The emission layer222bof the intermediate layer222may be placed for each pixel. For example, the emission layer222bmay be patterned to correspond to the pixel electrode221. Unlike the emission layer222b, each of the first functional layer222aand/or the second functional layer222cof the intermediate layer222may be formed as one body so as to correspond to a plurality of pixels

An opposite electrode223may include a conductive material having a low work function. For example, the opposite electrode223may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Alternatively, the opposite electrode223may further include a layer including ITO, IZO, ZnO, or In2O3on the (semi) transparent layer including the above material. The opposite electrode223may be located in not only the display area DA but also the middle area MA. The first functional layer222a, the second functional layer222c, and the opposite electrode223may be formed by thermal deposition.

A capping layer230may be located on the opposite electrode223. For example, the capping layer230may include LiF and be formed by thermal deposition. In an embodiment, the capping layer230may be omitted.

A layer(s) including an organic material among layers provided to the display panel may provide a path through which moisture may propagate. The first functional layer222aand/or the second functional layer222cincluded in the stacked structure of the organic light-emitting diode OLED include an organic material and thus may provide a path through which moisture may propagate. However, because the first functional layer222aand/or the second functional layer222care disconnected or separated by grooves G (as shown inFIG.7) provided in the middle area MA, the above-described moisture transmission issue and damage to the organic light-emitting diode OLED may be prevented or reduced.

As shown inFIG.7, one or more grooves G may be located in the middle area MA. As shown inFIG.7, in a plan view, grooves G may have a ring shape surrounding the first area OA and be apart from each other.

A groove G may be located in a multi-layer including a plurality of layers, and the groove G that is concave in a depth direction of the multi-layer may have an undercut structure. The multi-layer and a structure of the groove G are described below with reference toFIGS.9A-9F.

FIGS.9A-9Fare the cross-sectional views of one of the grooves in a display panel according to an embodiment. For convenience of description,FIGS.9A-9Fomit a thin-film encapsulation layer, which is an encapsulation member.

Referring toFIGS.9A-9F, a multi-layer ML includes an upper layer UL, a lower layer LL. The lower layer LL and/or the upper layer UL including a plurality of sub-layers.

Referring toFIGS.9A and9B, the multi-layer ML includes the lower layer LL and the upper layer UL. The lower layer LL may include a first sub-lower layer LL1and a second sub-lower layer LL2under the first sub-lower layer LL1. The upper layer UL may include a single layer.

The lower layer LL and the upper layer UL may include different materials. For example, the first sub-lower layer LL1and the second sub-lower layer LL2may include an organic material, for example, an organic insulating material. The upper layer UL may include an inorganic material.

The organic insulating material of the lower layer LL may include an organic insulating material including a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof.

The inorganic material of the upper layer UL may include a material different from an organic material containing carbon element, the material including a conductive oxide such as IZO, ITO, ZnO, In2O3, IGO, and/or AZO. Alternatively, the inorganic material of the upper layer UL may include a metal such as Mo, Al, Cu, and/or Ti. Alternatively, the inorganic material of the upper layer UL may include an insulating material such as silicon nitride, silicon oxide, and/or silicon oxynitride.

The groove G may be located in a depth direction of the multi-layer ML. The groove G may include a top-hole UL-h passing through the upper layer UL, and a bottom-hole or a bottom-recess located in the lower layer LL. In an embodiment, as shown inFIG.9A, the groove G may include a top-hole UL-h of the upper layer UL, a first bottom-hole LL1-hof the first sub-lower layer LL1, and a second recess LL2-rof the second sub-lower layer LL2. Alternatively, as shown inFIG.9B, the groove G may include a top-hole UL-h of the upper layer UL, a first bottom-hole LL1-hof the first sub-lower layer LL1, and a second bottom-hole LL2-hof the second sub-lower layer LL2. A depth d of the groove G may be less than a thickness t of the lower layer LL, and a bottom surface of the groove G may be located between a top surface and a bottom surface of the second sub-lower layer LL2(seeFIG.9A). Alternatively, a depth d of the groove G may be equal to the thickness t of the lower layer LL, and the bottom surface of the groove G may be located on the same surface as a bottom surface of the second sub-lower layer LL2(seeFIG.9B).

The groove G may have an undercut structure. Referring toFIGS.9A and9B, a first width W1of the top-hole UL-h may be less than a width of the lower layer LL, for example, a second width W2of the first bottom-hole LL1-hof the first sub-lower layer LL1. Ends of the upper layer UL that protrude toward the groove G, for example, a center of the groove G may constitute a pair of tips PT. A protruding length d1of each tip PT may be less than a depth d of the groove G. The protruding length d1of the tip PT may be less than 2 μm. For example, the protruding length d1of the tip PT may be about 1 μm to about 1.5 μm. The depth d of the groove G may be 2 μm or more, 2.5 μm or more, 3 μm or more, or 3.5 μm or more.

An organic material layer(s) included in the stacked structure of the organic light-emitting diode OLED (seeFIG.8) described with reference toFIGS.7and8may be disconnected or separated by the groove G. For example, as shown inFIGS.9A and9B, the first functional layer222aand the second functional layer222cmay be disconnected or separated around the groove G. Likewise, the opposite electrode223and the capping layer230may be disconnected or separated around the groove G. Though it is shown inFIGS.9A,9BandFIGS.9C-19discussed below that the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230are disconnected or separated around the groove G, the embodiments are not limited thereto. As described above, the second functional layer222cand/or the capping layer230may be omitted. In this case, there is no second functional layer222cand/or capping layer230around the groove G.

As described with reference toFIGS.9A and9B, the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230may be disconnected or separated by the groove G, and the multi-layer ML in which the groove G is located may have not only the structure shown inFIGS.9A and9Bbut also various structures described below with reference toFIGS.9C-9F.

Referring toFIG.9C, the groove G is located in the multi-layer ML. A lower layer LL′ of the multi-layer ML may include a first sub-lower layer LL1, a second sub-lower layer LL2under the first sub-lower layer LL1, and a third sub-lower layer LL3under the second sub-lower layer LL2.

Two or three of the first sub-lower layer LL1, the second sub-lower layer LL2, and the third sub-lower layer LL3may include different materials. For example, the first sub-lower layer LL1may include an organic insulating material, and the second sub-lower layer LL2and the third sub-lower layer LL3may include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride.

Though it is shown inFIG.9Cthat the lower layer LL′ includes two inorganic insulating material layers, for example, the second sub-lower layer LL2and the third sub-lower layer LL3, the embodiments are not limited thereto. In some other embodiments, the lower layer LL′ includes the first sub-lower layer LL1and one or three or more sub-layer(s) placed under the first sub-lower layer LL1and including an inorganic insulating material.

As described with reference toFIG.9A, the upper layer UL may include a single layer or a multi-layer and includes an inorganic material. The upper layer UL may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. Alternatively, the upper layer UL may include a conductive oxide such as IZO or may include a metal such as Mo, Ti, and Cu.

The groove G may have an undercut shape. A protruding length d1of a pair of tips PT that protrude toward a center of the groove G, a depth d of the groove G, and a characteristic in which the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230are disconnected around the groove G are the same as those described with reference toFIGS.9A and9B. Though it is shown inFIG.9Cthat a bottom surface of the groove G is located between a top surface and a bottom surface of the third sub-lower layer LL3, the bottom surface of the groove G may be located on the same surface as the bottom surface of the third sub-lower layer LL3in some other embodiments.

Referring toFIG.9D, the groove G is located in the multi-layer ML, and as described with reference toFIG.9C, the lower layer LL′ of the multi-layer ML may include the first sub-lower layer LL1, the second sub-lower layer LL2, and the third sub-lower layer LL3. In some other embodiments, the lower layer LL′ ofFIG.9Dmay have the structure of the lower layer LL described with reference toFIGS.9A and9B.

A upper layer UL′ of the multi-layer ML may include a first sub-upper layer UL1and a second sub-upper layer UL2on the first sub-upper layer UL1. The upper layer UL may include an inorganic material, and the first sub-upper layer UL1and the second sub-upper layer UL2may have different materials. For example, the first sub-upper layer UL1may include a conductive oxide such as IZO or may include a metal such as Al, Mo, and Ti. The second sub-upper layer UL2may include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride.

A lateral surface UL1-S of the first sub-upper layer UL1that faces the groove G may be covered by the second sub-upper layer UL2. The lateral surface UL1-S of the first sub-upper layer UL1may be alongside a lateral surface UL2-S of the second sub-upper layer UL2. In an embodiment, in the case where the first sub-upper layer UL1includes three layers of titanium, aluminum, and titanium, aluminum is damaged more than titanium during a process of manufacturing the display panel and thus unevenness may be formed in the lateral surface UL1-S of the first sub-upper layer UL1. In contrast, according to an embodiment, because the lateral surface UL1-S of the first sub-upper layer UL1is covered by the second sub-upper layer UL2, the lateral surface UL1-S of the first sub-upper layer UL1may be saved or prevented from being damaged.

The first sub-upper layer UL1and the second sub-upper layer UL2may extend further to the center of the groove G than a lateral surface of the lower layer LL, thereby defining a pair of tips PT. A protruding length d1of each tip PT and the depth d of the groove G are the same as those described above.

Though it is shown inFIG.9Dthat the bottom surface of the groove G is between a top surface and a bottom surface of the third sub-lower layer LL3, the embodiments are not limited thereto. In some other embodiments, similar to that described with reference toFIG.9B, the bottom surface of the groove G may be located on the same surface as the bottom surface of the third sub-lower layer LL3.

Referring toFIG.9E, the upper layer UL′ of the multi-layer ML is the same as that described with reference toFIG.9Dand the multi-layer ML ofFIG.9Eis different from the multi-layer ML ofFIG.9Din that a lower layer LL″ is a single layer. The lower layer LL″ may include an organic insulating material. A depth d of the groove G may be equal to or less than a thickness of the lower layer LL″.

Though it is shown inFIG.9Ethat the bottom surface of the groove G is between a top surface and a bottom surface of the lower layer LL″, the bottom surface of the groove G may be located on the same surface as the bottom surface of the lower layer LL″ in some other embodiments.

Referring toFIG.9F, the lower layer LL of the multi-layer ML may include the first sub-lower layer LL1and the second sub-lower layer LL2as shown above inFIGS.9A and9B. In some other embodiments, the lower layer LL may include the bottom layers LL′ and LL″ as described with reference toFIGS.9C-9E.

A upper layer UL″ of the multi-layer ML may include a plurality of layers. For example, the upper layer UL″ may include a first sub-upper layer UL1, a second sub-upper layer UL2on the first sub-upper layer UL1, and a third sub-upper layer UL3on the second sub-upper layer UL2. Two or more of the first sub-upper layer UL1, the second sub-upper layer UL2, and the third sub-upper layer UL3may include different materials.

For example, the first sub-upper layer UL1and the third sub-upper layer UL3may include a conductive oxide such as IZO or a metal, and the second sub-upper layer UL2may include an insulating material such as silicon nitride. Alternatively, the first sub-upper layer UL1and the third sub-upper layer UL3may include an insulating material such as silicon nitride, and the second sub-upper layer UL2may include a conductive oxide such as IZO or a metal.

Though it is shown inFIG.9Fthat the upper layer UL″ includes three sub-layers, the embodiments are not limited thereto. The upper layer UL″ may include two sub-layers including the first sub-upper layer UL1and the second sub-upper layer UL2. Alternatively, the upper layer UL″ may include four or more sub-layers.

The first sub-upper layer UL1, the second sub-upper layer UL2, and the third sub-upper layer UL3extend further toward the center of the groove G than a lateral side of the lower layer LL, thereby defining a pair of tips PT. A protruding length d1of each tip PT and the depth d of the groove G are the same as those described above.

Though it is shown inFIG.9Fthat the bottom surface of the groove G is between a top surface and a bottom surface of the second sub-lower layer LL2, the embodiments are not limited thereto. In some other embodiments, as described with reference toFIG.9B, the bottom surface of the groove G may be located on the same surface as the bottom surface of the second sub-lower layer LL2.

FIG.10is a plan view of a portion of a display panel according to an embodiment.

Referring toFIG.10, the middle area MA is between the first area OA and the display area DA, and a plurality of grooves G are located in the middle area MA. ThoughFIG.10shows three grooves G, the number of grooves G may be four or more.

Lines may bypass around an edge of the first area OA in the middle area MA. Signal lines connected to pixels P apart from each other around the first area OA may extend along the edge of the first area OA in the middle area MA.

In a plan view ofFIG.10, at least one data line DL passing across the display area DA may extend in a y-direction so as to provide a data signal to pixels P vertically placed around the first area OA and extend along the edge of the first area OA in the middle area MA. Similarly, at least one of scan lines SL passing across the display area DA may extend in an x-direction so as to provide a scan signal to pixels P horizontally placed around the first area OA and extend along the edge of the first area OA in the middle area MA.

A bypass portion (or a circuitous portion) SL-D of the scan line SL may be located on the same layer on which an extension portion SL-L crossing (e.g., intersecting) the display area DA is placed and may be formed as one body. A bypass portion DL-D1of at least one (referred to as a first data line DL1, hereinafter) of data lines DL may be located on a layer different from a layer on which an extension portion DL-L1crossing the display area DA is located, and the bypass portion DL-D1of the data line DL may be connected to the extension portion DL-L1through a contact hole CNT. A bypass portion DL-D2of at least one (referred to as a second data line DL2, hereinafter) of the data lines DL may be located on the same layer on which an extension portion DL-L2is located and may be formed as one body.

FIG.11is a cross-sectional view of a display panel according to an embodiment,FIGS.12A-12Care cross-sectional views of a process of manufacturing a display panel according to some example embodiments and show a middle area, andFIG.13is a cross-sectional view of one of the groove areas.FIG.11may correspond to a cross-section taken along the line X-X′ ofFIG.10.

Referring toFIG.11, the middle area MA is between the first area OA and the display area DA, and a pixel circuit PC and an organic light-emitting diode OLED that correspond to each pixel P (seeFIG.10) are located in the display area DA.

First, referring to the display area DA ofFIG.11, the substrate100may include a glass material or a polymer resin. In an embodiment, as shown in an enlarged view ofFIG.4A, the substrate100may include a plurality of sub-layers.

A buffer layer201may be on the substrate100. The buffer layer201may reduce or prevent impurities from penetrating into a semiconductor layer Act of a thin film transistor TFT. The buffer layer201may include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride and may also include a single layer or a multi-layer including the above mentioned inorganic insulating materials.

A pixel circuit PC may be on the buffer layer201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include the semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. A data line DL of the pixel circuit PC may be electrically connected to a switching thin film transistor (not shown) included in the pixel circuit PC. Though the present embodiment shows a top gate-type thin film transistor TFT in which a gate electrode GE is placed over a semiconductor layer Act with a gate insulating layer203therebetween, the thin film transistor TFT may be a bottom gate-type thin film transistor TFT in an embodiment.

The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including Mo, Al, Cu, and Ti, and may include a single layer or a multi-layer including the above materials.

The gate insulating layer203between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer203may include a single layer or a multi-layer including the above materials.

The source electrode SE and the drain electrode DE may be located on the same layer on which the data line DL is placed, and may include the same material as that of the data line DL. The source electrode SE, the drain electrode DE, and the data line DL may include a material having a relatively high (e.g., an excellent) conductivity. The source electrode SE and the drain electrode DE may include a conductive material including Mo, Al, Cu, and Ti, and may include a single layer or a multi-layer including the above materials. In an embodiment, the source electrode SE, the drain electrode DE, and the data line DL may each include a multi-layer of Ti/Al/Ti.

The storage capacitor Cst may include a bottom electrode CE1and a top electrode CE2, the bottom electrode CE1overlapping the top electrode CE2with a first interlayer insulating layer205therebetween. The storage capacitor Cst may overlap the thin film transistor TFT. With regard to this, it is shown inFIG.11that the gate electrode GE of the thin film transistor TFT serves as the bottom electrode CE1of the storage capacitor Cst. In some other embodiments, the storage capacitor Cst may not overlap the thin film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer207. The top electrode CE2of the storage capacitor Cst may include a conductive material including Mo, Al, Cu, and Ti, and may include a single layer or a multi-layer including the above materials.

The first interlayer insulating layer205and the second interlayer insulating layer207may include an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The first interlayer insulating layer205and the second interlayer insulating layer207may include a single layer or a multi-layer including the above materials.

The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by a first organic insulating layer209. The first organic insulating layer209may include an approximately flat top surface.

The pixel circuit PC may be electrically connected to the pixel electrode221. For example, as shown inFIG.11, a contact metal layer CM may be placed between the thin film transistor TFT and the pixel electrode221. The contact metal layer CM may be connected to the thin film transistor TFT through a contact hole in the first organic insulating layer209, and the pixel electrode221may be connected to the contact metal layer CM through a contact hole in a second organic insulating layer211on the contact metal layer CM. The contact metal layer CM may include a conductive material including Mo, Al, Cu, and Ti, and may include a single layer or a multi-layer including the above materials. In an embodiment, the contact metal layer CM may include three layers of Ti/Al/Ti.

The first organic insulating layer209and the second organic insulating layer211may include an organic insulating material including a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof. In an embodiment, the first organic insulating layer209and the second organic insulating layer211may include polyimide.

The pixel electrode221may be located on the second organic insulating layer211. The second organic insulating layer211may be the planarization layer described above with reference toFIG.8. Edges of the pixel electrode221may be covered by a pixel-defining layer215. The pixel-defining layer215may include an opening that overlaps a central portion of the pixel electrode221. A spacer217may be located on the pixel-defining layer215. The spacer217may include a material different from that of the pixel-defining layer215or may include the same material as that of the pixel-defining layer215. In an embodiment, the pixel-defining layer215and the spacer217may include the same material and may be concurrently formed during a mask process that uses a halftone mask. In an embodiment, the pixel-defining layer215and the spacer217may include polyimide.

The intermediate layer222includes the emission layer222b. The intermediate layer222may include the first functional layer222aand/or the second functional layer222c, the first functional layer222abeing under the emission layer222b, and the second functional layer222cbeing on the emission layer222b. The emission layer222bmay include a polymer or low molecular weight organic material that emits light having a set or predetermined color. The opposite electrode223may be located on the intermediate layer222, and the capping layer230may be located on the opposite electrode223. The capping layer230may be omitted.

Materials, structures, and characteristics of the pixel electrode221, the intermediate layer222, and the opposite electrode223are the same as those described with reference toFIG.8.

The organic light-emitting diode OLED is covered by the thin-film encapsulation layer300. The thin-film encapsulation layer300may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. It is shown inFIG.11that the thin-film encapsulation layer300includes a first and a second inorganic encapsulation layers310and330, and an organic encapsulation layer320therebetween. In some other embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and a stacking sequence may be modified.

The first and second inorganic encapsulation layers310and330may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon nitride, silicon oxide, and silicon oxynitride. The first and second inorganic encapsulation layers310and330may include a single layer or a multi-layer including the above materials. The organic encapsulation layer320may include a polymer-based material. The polymer-based material may include an acrylic-based resin, an epoxy-based resin, polyimide, and polyethylene. In an embodiment, the organic encapsulation layer320may include acrylate.

A thickness of the first inorganic encapsulation layer310may be different from a thickness of the second inorganic encapsulation layer330. The thickness of the first inorganic encapsulation layer310may be greater than the thickness of the second inorganic encapsulation layer330. Alternatively, the thickness of the second inorganic encapsulation layer330may be greater than the thickness of the first inorganic encapsulation layer310, or the thickness of the first inorganic encapsulation layer310may be the same as the thickness of the second inorganic encapsulation layer330.

Referring to the middle area MA ofFIG.11, the middle area MA may include a first sub-middle area SMA1and a second sub-middle area SMA2, the first sub-middle area SMA1being relatively distant from the first area OA, and the second sub-middle area SMA2being relatively close to the first area OA.

Lines, for example, signal lines may be located in the first sub-middle area SMA1. The bypass portions DL-D1and DL-D2of the first and second data lines DL1and DL2described above with reference toFIG.10may be located in the first sub-middle area SMA1ofFIG.11. The first sub-middle area SMA1may be a line area and a bypass area in which the data lines DL bypass. The data lines DL located in the middle area MA described with reference toFIG.10may include the first data lines DL1and the second data lines DL2that are alternately placed on and under the first organic insulating layer209with the first organic insulating layer209therebetween. With regard to this, it is shown inFIG.11that the bypass portion DL-D1of the first data line DL1and the bypass portion DL-D2of the second data line DL2neighbor each other and are respectively placed on and under the first organic insulating layer209. In this case, a gap (or a pitch Δd) between the first data line DL1and the second data line DL2that neighbor each other, for example, between the bypass portion DL-D1of the first data line DL1and the bypass portion DL-D2of the second data line DL2, may be reduced.

Grooves G are located in the second sub-middle area SMA2. The grooves G are located in the multi-layer ML. In an embodiment, as shown inFIGS.11and12A, the multi-layer ML may include the first organic insulating layer209, the second organic insulating layer211, and an inorganic layer213. The first organic insulating layer209and the second organic insulating layer211may respectively correspond to the first sub-bottom layer and the second sub-bottom layer of the multi-layer ML described with reference toFIGS.9A and9B, and the inorganic layer213may correspond to the top layer.

The inorganic layer213may include a material different from that of the pixel electrode221. The inorganic layer213may include a conductive oxide such as IZO, ITO, ZnO, In2O3, IGO, and/or AZO, may include a metal such as Mo, Cu, and/or Ti, or may include an insulating material such as silicon nitride, silicon oxide, and/or silicon oxynitride.

Referring toFIG.12A, the groove G may include a hole213hof the inorganic layer213, a hole211hof the second organic insulating layer211, and a recess209rof the first organic insulating layer209. In this case, a bottom surface of the groove G may be located between a top surface and a bottom surface of the first organic insulating layer209. In some other embodiments, the first organic insulating layer209may include a hole passing through the first organic insulating layer209instead of the recess209r. In this case, the bottom surface of the groove G may be placed on the same surface as the bottom surface of the first organic insulating layer209or a top surface of the second interlayer insulating layer207.

The inorganic layer213may include a pair of tips PT extending toward the groove G. A protruding length d1of the tip PT may be less than about 2 μm as described above. A depth d of the groove G may be 2 μm or more, 2.5 μm or more, 3 μm or more, or 3.5 μm or more.

A partition wall PW may be located in the middle area MA. The partition wall PW may be located between grooves G that neighbor each other. The partition wall PW may be formed while a portion211P of a layer constituting the second organic insulating layer211, a portion215P of a layer constituting the pixel-defining layer215, and a portion217P of a layer constituting the spacer217are sequentially stacked (e.g., arranged). A height from a top surface of the substrate100to a top surface of the partition wall PW may be less than a height from the top surface of the substrate100to a top surface of the spacer217.

The intermediate layer MA may include an inorganic contact region ICR. The inorganic contact region ICR may be located between the grooves G that neighbor each other. The inorganic contact region ICR is a region in which layers including an inorganic material directly contact each other. It is shown inFIG.11that the inorganic layer213directly contacts the second interlayer insulating layer207. The inorganic layer213may contact the second interlayer insulating layer207through openings209OP and211OP respectively located in the first organic insulating layer209and the second organic insulating layer211.

A first groove G1, a second groove G2, and a third groove G3are formed before a process of forming the intermediate layer222is performed. The first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230may be disconnected or separated by the grooves G as described above with reference toFIGS.11and12A-12B.

Referring toFIG.12C, the first inorganic encapsulation layer310, the organic encapsulation layer320, and the second inorganic encapsulation layer330may be sequentially formed. The first inorganic encapsulation layer310may be formed by chemical vapor deposition, etc. Unlike the first functional layer222a, the second functional layer222c, the opposite electrode223, and the capping layer230, the first inorganic encapsulation layer310has a relatively large (e.g., excellent) step coverage. Therefore, as shown inFIGS.11,12C, and13, the first inorganic encapsulation layer310may continuously cover an inner surface of the first groove G1. For example, the first inorganic encapsulation layer310may continuously extend so as to cover a top surface, a lateral surface, and a bottom surface of the inorganic layer213, a lateral surface of the second organic insulating layer211, and a lateral surface of the first organic insulating layer209.

As shown inFIG.13, a first thickness t1of a first portion of the first inorganic encapsulation layer310on a top surface of the inorganic layer213may be greater than a second thickness t2of a second portion of the first inorganic encapsulation layer310under a bottom surface of the inorganic layer213. Also, the first thickness t1may be greater than a third thickness t3of a third portion of the first inorganic encapsulation layer310on a lateral surface of the second organic insulating layer211.

The first inorganic encapsulation layer310may include a single layer or a plurality of sub-layers. For example, the first inorganic encapsulation layer310may include two layers of silicon oxynitride that have different membraneous materials. In such a case, the capping layer230may be omitted. Alternatively, the first inorganic encapsulation layer310may include silicon oxynitride and silicon oxide, silicon oxynitride and silicon nitride, or silicon nitride and silicon oxide.

As shown inFIGS.11and12C, the organic encapsulation layer320may cover a portion of the display area DA and the middle area MA. An end of the organic encapsulation layer320that neighbors the first area OA may be adjacent to one lateral surface of the partition wall PW.

The second inorganic encapsulation layer330is located on the organic encapsulation layer320and may directly contact the first inorganic encapsulation layer310in the middle area MA. For example, the first inorganic encapsulation layer310may directly contact the second inorganic encapsulation layer330in an area between the first area OA and the partition wall PW.

Similar to the first inorganic encapsulation layer310, the second inorganic encapsulation layer330may have relatively large (e.g., excellent) step coverage. Therefore, the second inorganic encapsulation layer330may continuously cover an inner lateral surface of the grooves G located between the first area OA and the partition wall PW. Similar to the first inorganic encapsulation layer310described inFIG.13, a thickness of a fourth portion of the second inorganic encapsulation layer330on a top surface of the inorganic layer213may be greater than a thickness of a fifth portion of the second inorganic encapsulation layer330under a bottom surface of the inorganic layer213.

A structure shown inFIG.11may be a structure surrounding the first area OA in a plan view. For example, as shown inFIG.10, the grooves G ofFIG.11may have a ring shape surrounding the first area OA in a view in a direction perpendicular to the top surface of the substrate100. Similarly, the partition wall PW may have a ring shape surrounding the first area OA in a view in a direction perpendicular to the top surface of the substrate100.

FIG.14is a cross-sectional view of a display panel according to an embodiment, taken along the line X-X′ ofFIG.10. A display panel10-2ofFIG.14may have a structure similar to that of the display panel10-1described with reference toFIG.11, etc. A difference is mainly described below.

Referring toFIG.14, a multi-layer ML of the display panel10-2may include the first organic insulating layer209, the second organic insulating layer211, and an inorganic layer213′. The inorganic layer213′ may include an inorganic insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. The first organic insulating layer209and the second organic insulating layer211may respectively correspond to the first sub-bottom layer and the second sub-bottom layer of the multi-layer ML described with reference toFIGS.9A and9B, and the inorganic layer213′ may correspond to the top layer.

The inorganic layer213′ is located in the display area DA and may be formed during the same process as a process of forming a passivation layer212including an inorganic insulating material. The inorganic layer213′ includes a pair of tips PT extending toward the groove G, and a protruding length of the tip PT and structural characteristics of the groove G such as a depth of the groove G are the same as those described above.

The middle area MA may include a plurality of inorganic contact regions ICR. With regard to this,FIG.14shows an inorganic contact region ICR that neighbors the partition wall PW, and an inorganic contact region ICR between grooves G that neighbor each other. The plurality of inorganic contact regions ICR described with reference toFIG.14are applicable to the embodiments described with reference toFIG.11, embodiments described with reference toFIGS.15-19, and embodiments derived therefrom.

Though it is shown inFIG.14that the passivation layer212located in the display area DA is located on the second organic insulating layer211, the passivation layer212may be located under the second organic insulating layer211in some other embodiments.

FIG.15is a cross-sectional view of the first area OA and the middle area MA in a display panel10-3according to an embodiment, taken along the line X-X′ ofFIG.10. The display panel10-3shown inFIG.15includes a plurality of grooves G located in the middle area MA, and a first groove G1among the plurality of grooves G that neighbors the display area DA may be located over signal lines. With regard to this, it is shown inFIG.15that the first groove G1overlaps the bypass portions DL-D1and DL-D2of the data lines extending along the edge of the first area OA.

The grooves G located between the first area OA and the first groove G1may be defined in a multi-layer different from that of the first groove G1. The grooves G except for the first groove G1may be in a multi-layer (referred to as a first multi-layer ML1, hereinafter) including the first organic insulating layer209, the second organic insulating layer211, and the inorganic layer213. A specific structure thereof is the same as that described with reference toFIGS.11-13.

The first groove G1may be in a multi-layer (referred to as a second multi-layer ML2, hereinafter) including the second organic insulating layer211, the pixel-defining layer215, and an inorganic layer216. The second organic insulating layer211and the pixel-defining layer215may correspond to the bottom layer described with reference toFIGS.9A and9B, and the inorganic layer216may correspond to the top layer.

The pixel-defining layer215may include an organic insulating material, and the inorganic layer216may include a conductive oxide such as IZO, or include an inorganic insulating material such as silicon nitride. Alternatively, the inorganic layer216may include a metal such as Mo and Ti. The inorganic layer216of the second multi-layer ML2may include a material that is the same as or different from a material of the inorganic layer213of the first multi-layer ML1.

The first groove G1may include a hole216hof the inorganic layer216, a hole215hof the pixel-defining layer215, and a recess211rof the second organic insulating layer211. The inorganic layer216may include a pair of tips PT extending toward a center of the first groove G1. A protruding length of the tip PT and the depth of the first groove G1are the same as those described with reference toFIG.9A.

FIG.16is a cross-sectional view of the first area OA and the middle area MA in a display panel10-4according to an embodiment, taken along the line X-X′ ofFIG.10. Because the display panel10-4ofFIG.16is different from the display panel10-3shown inFIG.15in the structure of the first groove G1, a difference is mainly described.

The first groove G1is located in a second multi-layer ML2′, and a top layer of the second multi-layer ML2′ may include a plurality of inorganic layers. With regard to this, it is shown inFIG.16that the second multi-layer ML2′ includes the second organic insulating layer211, the pixel-defining layer215, a first inorganic layer216a, and a second inorganic layer216b. As described with reference toFIG.9F, the second organic insulating layer211and the pixel-defining layer215may correspond to the bottom layer, and the first inorganic layer216aand the second inorganic layer216bmay correspond to the top layer. Though it is shown inFIG.16that the top layer includes two layers including the first inorganic layer216aand the second inorganic layer216b, the top layer may include three or more inorganic layers as described with reference toFIG.9F.

The first groove G1may include a hole216bhof the second inorganic layer216b, a hole216ahof the first inorganic layer216a, the hole215hof the pixel-defining layer215, and the recess211rof the second organic insulating layer211. As described with reference toFIG.15, the first groove G1may overlap the bypass portions DL-D1and DL-D2of the first and second data lines.

The first inorganic layer216amay include a material different from that of the second inorganic layer216b. For example, the first inorganic layer216amay include a conductive oxide such as IZO, and the second inorganic layer216bmay include an insulating material such as silicon nitride. The first inorganic layer216aand the second inorganic layer216bmay include tips PT protruding toward a center of the first groove G1, and conditions for a protruding length of the tip PT and the depth of the first groove G1are the same as those described above.

Thought it is shown inFIG.16that the inorganic layer213, which is a top layer of the first multi-layer ML1, includes a single layer, the inorganic layer213may include two or more layers in some other embodiments. A top layer of the second multi-layer ML2′ and a top layer of the first multi-layer ML1may have different stacked structures or include different materials. In an embodiment, the top layer of the second multi-layer ML2′ may include two sub-layers including the first inorganic layer216aand the second inorganic layer216b, but the inorganic layer213, which is the top layer of the first multi-layer ML1, may include one or three or more sub-layers.

The above-described characteristics described with reference toFIGS.15and16, for example, a characteristic in which the first groove G1that neighbors the display area DA is located on a layer different from a layer on which other grooves G are placed, a characteristic in which the first groove G1overlaps wirings, and a structure of the second multi-layers ML2and ML2′ are applicable to the embodiments described with reference toFIGS.8-14, embodiments described below with referenced toFIGS.17-19, and embodiments derived therefrom.

FIG.17is a cross-sectional view of a display panel10-5according to an embodiment.FIG.17may correspond to a cross-section taken along the line X-X′ ofFIG.10.

Referring toFIG.17, the display panel10-5includes the grooves G in the multi-layer ML. The multi-layer ML may include the first organic insulating layer209, the second interlayer insulating layer207, the first interlayer insulating layer205, and the inorganic layer210. The first organic insulating layer209, the second interlayer insulating layer207, and the first interlayer insulating layer205may respectively correspond to the first sub-bottom layer, the second sub-bottom layer, and the second sub-bottom layer of the multi-layer described with reference toFIG.9C, and the inorganic layer210may correspond to the top layer.

The inorganic layer210may include a material different from those of the data line DL and the contact metal layer CM, the contact metal layer CM connecting the thin film transistor TFT to the pixel electrode221. The inorganic layer210may include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride. Alternatively, the inorganic layer210may include a conductive oxide such as IZO. Alternatively, the inorganic layer210may include a metal such as Mo and Ti.

The inorganic layer210may include a pair of tips PT extending toward a center of the groove G, and characteristics for a protruding length of the tip PT and the depth of the groove G are the same as those described above.

Though it is shown inFIG.17that the bottom layer of the multi-layer ML include three sub-layers, the embodiments are not limited thereto. In some other embodiments, the bottom layer of the multi-layer ML may include two sub-layers including the first organic insulating layer209and the second interlayer insulating layer207. Alternatively, the bottom layer of the multi-layer ML may further include the gate insulating layer203in addition to the sub-layers ofFIG.17.

The partition wall PW located in the middle area MA may be formed while a portion209P of a layer including the first organic insulating layer209, a portion215P of a layer including the pixel-defining layer215, and a portion217P of a layer including the spacer217are sequentially stacked. The structure of the partition wall PW shown inFIG.17is applicable to the embodiments described with reference toFIGS.11-16, embodiments described below with reference toFIG.19, and/or embodiments derived therefrom.

FIG.18is a cross-sectional view of a display panel10-6according to an embodiment.FIG.18may correspond to a cross-section taken along the line X-X′ ofFIG.10. Because the display panel10-6ofFIG.18is different from the display panel10-5shown inFIG.17in the structure of the top layer of the multi-layer ML, a difference is mainly described below.

Referring toFIG.18, the multi-layer ML may include the first organic insulating layer209, the second interlayer insulating layer207, the first interlayer insulating layer205, the first inorganic layer210a, and the second inorganic layer210b. The first organic insulating layer209, the second interlayer insulating layer207, and the first interlayer insulating layer205may respectively correspond to the first sub-bottom layer, the second sub-bottom layer, and the second sub-bottom layer. The first inorganic layer210aand the second inorganic layer210bmay respectively correspond to the first sub-top layer and the second sub-top layer. Though it is shown inFIG.18that the bottom layer of the multi-layer ML includes three sub-layers, the bottom layer may include a single layer as described with reference toFIG.9Ein some other embodiments. In this case, the bottom layer of the multi-layer ML may include the first organic insulating layer209, which is a bottom layer, the first inorganic layer210a, and the second inorganic layer210b, which are top layers.

The first inorganic layer210amay include the same material as that of the contact metal layer CM. For example, the first inorganic layer210amay have a structure of Ti/Al/Ti that are sequentially stacked. The second inorganic layer210bmay include an insulating material such as silicon nitride, silicon oxide, and silicon oxynitride.

A lateral surface of the first inorganic layer210afacing a center of the groove G may be covered by the second inorganic layer210b. The first inorganic layer210a, which has a three-layered structure of Ti/Al/Ti, may be formed during the same mask process as a process of forming the contact metal layer CM. The second inorganic layer210bmay prevent or reduce damage to the first inorganic layer210a. For example, in the case where the first inorganic layer210aincludes a multi-layer including aluminum, which may be damaged during a process, and titanium, which may not be damaged during a process, a lateral surface of the first inorganic layer210amay be made not to include unevenness by reducing or preventing damage to aluminum.

The top layer including the first inorganic layer210aand the second inorganic layer210bmay include a pair of tips PT. Characteristics for a protruding length of the tip PT and the depth of the groove G are the same as those described above.

Though it is shown inFIG.18that the bottom layer of the multi-layer ML includes three sub-layers, the embodiments are not limited thereto. In some other embodiments, the bottom layer of the multi-layer ML may include two sub-layers including the first organic insulating layer209and the second interlayer insulating layer207. Alternatively, the bottom layer of the multi-layer ML may further include the gate insulating layer203in addition to the sub-layers ofFIG.18.

FIG.19is a cross-sectional view of a display panel10-7according to an embodiment, andFIG.20is a cross-sectional view of a display panel10-8according to an embodiment.FIGS.19and20may correspond to cross-sections taken along the line X-X′ ofFIG.10.

The display panel10-7ofFIG.19and the display panel10-8ofFIG.20may include a planarization organic material layer420located on the thin-film encapsulation layer300in the middle area MA. In an embodiment, a structure of the display panel10-7ranging from the substrate100to the thin-film encapsulation layer300is the same as that described above with reference toFIG.11. In some other embodiments, as shown inFIG.20, the display panel10-8may include a plurality of partition walls PW and PW′ in the middle area MA. A groove may not be located between the plurality of partition walls PW and PW′. Alternatively, a groove may be located between the plurality of partition walls PW and PW′. The plurality of partition walls PW and PW′ may control a flow of a material constituting the organic encapsulation layer320during a process of forming the organic encapsulation layer320and/or control a height of the organic encapsulation layer320. With regard to this, though it is shown inFIG.20that a portion of the organic encapsulation layer320is between the partition walls PW and PW′ that neighbor each other, an end of the organic encapsulation layer320may be located on one side of the partition wall PW that neighbors the display area DA depending on a flow control condition in some other embodiments. As shown inFIGS.19and20, the planarization organic material layer420may be located in the middle area MA. The planarization organic material layer420may be located in only the intermediated area MA, for example, between the first area OA and the display area DA. The planarization organic material layer420may include an organic insulating layer. The planarization organic material layer420may include a polymer-based material. For example, the planarization organic material layer420may include a silicon-based resin, an acrylic-based resin, an epoxy-based resin, polyimide, and polyethylene. In an embodiment, the planarization organic material layer420may include a material different from that of the organic encapsulation layer320.

The planarization organic material layer420may cover at least one groove G located in the middle area MA. The planarization organic material layer420may increase flatness of the display panel10-7around the first area OA by covering a region of the middle area MA that is not covered by the organic encapsulation layer320. Therefore, separation or falling apart of the input sensing layer40(seeFIG.2or3) and/or the optical functional layer50(seeFIG.2or3) on the display panel10-7may be reduced or prevented. A portion of the planarization organic material layer420may overlap the organic encapsulation layer320. One edge of the planarization organic material layer420, for example, a first edge420ethat neighbors the display area DA may be located on the second inorganic encapsulation layer330.

The planarization organic material layer420may be located in the middle area MA during an exposure and developing process. In the case where external foreign substances, for example, moisture progresses in a lateral direction (or a direction parallel to the top surface of the substrate100, an x-direction) of the display panel10-7during some processes (e.g., a washing process) among processes of forming the planarization organic material layer420, an organic light-emitting diode OLED in the display area DA may be damaged. However, because insulating layers, for example, a first insulating layer410and a second insulating layer430are respectively arranged or placed under and on the planarization organic material layer420, the issue related to moisture penetration and/or floating of a layer located around the planarization organic material layer420may be reduced or prevented during and after a process of forming the planarization organic material layer420.

The first insulating layer410and the second insulating layer430may respectively directly contact a bottom surface and a top surface of the planarization organic material layer420. The first insulating layer410and the second insulating layer430may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The first insulating layer410and the second insulating layer430each may include a single layer or a multi-layer including the above materials.

The planarization organic material layer420may form a step difference with a layer(s) thereunder. A portion of the planarization organic material layer420that includes the first edge420emay form a step difference with a top surface of the first insulating layer410. To reduce or prevent an issue that the planarization organic material layer420is separated or floated from a layer thereunder due to the above-described step difference during and/or after a process of manufacturing the display panel10-7, a cover layer440may be located on the first edge420e.

The cover layer440may include a metal. The first insulating layer410, the second insulating layer430, and a third insulating layer450described below each extend to not only the intermediate layer MA but also the display area DA. In contrast, the cover layer440may cover the first edge420eof the planarization organic material layer420with a set or predetermined width. The cover layer440on the planarization organic material layer420may extend toward the display area DA beyond the first edge420e, but does not extend toward the display area DA.

The third insulating layer450may be located on the cover layer440. The third insulating layer450may include an organic insulating material. For example, an organic insulating material of the third insulating layer450may include a photoresist (e.g., a negative or positive photoresist) or a polymer-based organic material, and may extend toward the display area DA so as to cover the display area DA.

The structure shown inFIGS.19and20is equally applicable to the embodiments described with reference toFIGS.13-18and embodiments derived therefrom.

Though it is shown that each of the display panels described with reference toFIGS.11-20includes the first opening10H corresponding to the first area OA, and the substrate100also includes a through hole corresponding to the first area OA, the embodiments are not limited thereto. In some other embodiments, as described with reference toFIG.4B, the display panel may not include a hole passing through the substrate100.

The display panel according to embodiments may reduce or prevent external impurities such as moisture around the first area from damaging display elements.

It will be understood that, although the terms “first”, “second”, “third”, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed herein could be termed a second element, component, region, layer or section, without departing from the scope of the present disclosure.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure”. Also, the term “exemplary” is intended to refer to an example or illustration. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it may be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.

Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of features. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims, and their equivalents.