Patent ID: 12213321

DETAILED DESCRIPTION

The memory device described herein includes volatile memory cells in which each of the memory cells can include two transistors (2T). One of the two transistors has a charge storage structure, which can form a memory element of the memory cell to store information. The memory device described herein can have a structure (e.g., a 4F2 cell footprint) that allows the size (e.g., footprint) of the memory device to be relatively smaller than the size (e.g., footprint) of similar conventional memory devices. The described memory device can include a single access line (e.g., word line) to control two transistors of a corresponding memory cell. This can lead to reduced power dissipation and improved processing. Each of the memory cells of the described memory device can include a cross-point gain cell structure (and cross-point operation), such that a memory cell can be accessed using a single access line (e.g., word line) and single data line (e.g., bit line) during an operation (e.g., a read or write operation) of the memory device. The described memory device can include a conductive shield structure adjacent a side of the memory cell. The conductive shield structure can suppress or prevent potential leakage of current in the memory cell. This can improve retention of information stored in the memory cell. Other improvements and benefits of the described memory device and its variations are discussed below with reference toFIG.1throughFIG.23C.

FIG.1shows a block diagram of an apparatus in the form of a memory device100including volatile memory cells, according to some embodiments described herein. Memory device100includes a memory array101, which can contain memory cells102. Memory device100can include a volatile memory device such that memory cells102can be volatile memory cells. An example of memory device100includes a dynamic random-access memory (DRAM) device. Information stored in memory cells102of memory device100may be lost (e.g., invalid) if supply power (e.g., supply voltage Vcc) is disconnected from memory device100. Hereinafter, supply voltage Vcc is referred to as representing some voltage levels; however, they are not limited to a supply voltage (e.g., Vcc) of the memory device (e.g., memory device100). For example, if the memory device (e.g., memory device100) has an internal voltage generator (not shown inFIG.1) that generates an internal voltage based on supply voltage Vcc, such an internal voltage may be used instead of supply voltage Vcc.

In a physical structure of memory device100, each of memory cells102can include transistors (e.g., two transistors) formed vertically (e.g., stacked on different layers) in different levels over a substrate (e.g., semiconductor substrate) of memory device100. Memory device100can also include multiple levels (e.g., multiple decks) of memory cells where one level (e.g., one deck) of memory cells can be formed over (e.g., stacked on) another level (e.g., another deck) of additional memory cells. The structure of memory array101, including memory cells102, can include the structure of memory arrays and memory cells described below with reference toFIG.2throughFIG.23C.

As shown inFIG.1, memory device100can include access lines104(e.g., “word lines”) and data lines (e.g., bit lines)105. Memory device100can use signals (e.g., word line signals) on access lines104to access memory cells102and data lines105to provide information (e.g., data) to be stored in (e.g., written) or read (e.g., sensed) from memory cells102.

Memory device100can include an address register106to receive address information ADDR (e.g., row address signals and column address signals) on lines107(e.g., address lines). Memory device100can include row access circuitry108(e.g., X-decoder) and column access circuitry109(e.g., Y-decoder) that can operate to decode address information ADDR from address register106. Based on decoded address information, memory device100can determine which memory cells102are to be accessed during a memory operation. Memory device100can perform a write operation to store information in memory cells102and a read operation to read (e.g., sense) information (e.g., previously stored information) in memory cells102. Memory device100can also perform an operation (e.g., a refresh operation) to refresh (e.g., to keep valid) the value of information stored in memory cells102. Each of memory cells102can be configured to store information that can represent at most one bit (e.g., a single bit having a binary 0 (“0”) or a binary 1 (“1”), or more than one bit (e.g., multiple bits having a combination of at least two binary bits).

Memory device100can receive a supply voltage, including supply voltages Vcc and Vss, on lines130and132, respectively. Supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc can include an external voltage supplied to memory device100from an external power source such as a battery or an alternating current to direct current (AC-DC) converter circuitry.

As shown inFIG.1, memory device100can include a memory control unit118, which includes circuitry (e.g., hardware components) to control memory operations (e.g., read and write operations) of memory device100based on control signals on lines (e.g., control lines)120. Examples of signals on lines120include a row access strobe signal RAS*, a column access strobe signal CAS*, a write-enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock-enable signal CKE. These signals can be part of signals provided to a DRAM device.

As shown inFIG.1, memory device100can include lines (e.g., global data lines)112that can carry signals DQ0through DQN. In a read operation, the value (e.g., “0” or “1”) of information (read from memory cells102) provided to lines112(in the form of signals DQ0through DQN) can be based on the values of the signals on data lines105. In a write operation, the value (e.g., “0” or “1”) of information provided to data lines105(to be stored in memory cells102) can be based on the values of signals DQ0through DQN on lines112.

Memory device100can include sensing circuitry103, select circuitry115, and input/output (I/O) circuitry116. Column access circuitry109can selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Select circuitry115can respond to the signals on lines114to select signals on data lines105. The signals on data lines105can represent the values of information to be stored in memory cells102(e.g., during a write operation) or the values of information read (e.g., sensed) from memory cells102(e.g., during a read operation).

I/O circuitry116can operate to provide information read from memory cells102to lines112(e.g., during a read operation) and to provide information from lines112(e.g., provided by an external device) to data lines105to be stored in memory cells102(e.g., during a write operation). Lines112can include nodes within memory device100or pins (or solder balls) on a package where memory device100can reside. Other devices external to memory device100(e.g., a hardware memory controller or a hardware processor) can communicate with memory device100through lines107,112, and120.

Memory device100may include other components, which are not shown inFIG.1so as not to obscure the example embodiments described herein. At least a portion of memory device100(e.g., a portion of memory array101) can include structures and operations similar to or the same as any of the memory devices described below with reference toFIG.2throughFIG.23C.

FIG.2shows a schematic diagram of a portion of a memory device200including a memory array201, according to some embodiments described herein. Memory device200can correspond to memory device100ofFIG.1. For example, memory array201can form part of memory array101ofFIG.1. As shown inFIG.2, memory device200can include memory cells210through217, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or identical elements among memory cells210through217are given the same labels.

Each of memory cells210through217can include two transistors T1and T2. Thus, each of memory cells210through217can be called a 2T memory cell (e.g., 2T gain cell). Each of transistors T1and T2can include a field-effect transistor (FET). As an example, transistor T1can be a p-channel FET (PFET), and transistor T2can be an n-channel FET (NFET). Part of transistor T1can include a structure of a p-channel metal-oxide semiconductor (PMOS) transistor. Thus, transistor T1can include an operation similar to that of a PMOS transistor. Part of transistor T2can include an n-channel metal-oxide semiconductor (NMOS). Thus, transistor T2can include an operation similar to that of a NMOS transistor.

Transistor T1of memory device200can include a charge-storage based structure (e.g., a floating-gate based). As shown inFIG.2, each of memory cells210through217can include a charge storage structure202, which can include the floating gate of transistor T1. Charge storage structure202can form the memory element of a respective memory cell among memory cells210through217. Charge storage structure202can store charge. The value (e.g., “0” or “1”) of information stored in a particular memory cell among memory cells210through217can be based on the amount of charge in charge storage structure202of that particular memory cell. For example, the value of information stored in a particular memory cell among memory cells210through217can be “0” or “1” (if each memory cell is configured as a single-bit memory cell) or “00”, “01”, “10”, “11” (or other multi-bit values) if each memory cell is configured as a multi-bit memory cell.

As shown inFIG.2, transistor T2(e.g., the channel region of transistor T2) of a particular memory cell among memory cells210through217can be electrically coupled to (e.g., directly coupled to (contact)) charge storage structure202of that particular memory cell. Thus, a circuit path (e.g., current path) can be formed directly between transistor T2of a particular memory cell and charge storage structure202of that particular memory cell during an operation (e.g., a write operation) of memory device200. During a write operation of memory device200, a circuit path (e.g., current path) can be formed between a respective data line (e.g., data line271or272) and charge storage structure202of a particular memory cell through transistor T2(e.g., through the channel region of transistor T2) of the particular memory cell.

Memory cells210through217can be arranged in memory cell groups2010and2011.FIG.2shows two memory cell groups (e.g.,2010and2011) as an example. However, memory device200can include more than two memory cell groups. Memory cell groups2010and2011can include the same number of memory cells. For example, memory cell group2010can include memory cells210,212,214, and216, and memory cell group2011can include memory cells211,213,215, and217.FIG.2shows four memory cells in each of memory cell groups2010and2011as an example. The number of memory cells in memory cell groups2010and2011can be different from four.

Memory device200can perform a write operation to store information in memory cells210through217and a read operation to read (e.g., sense) information from memory cells210through217. Memory device200can be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a container for a capacitor, memory device200can store information in the form of charge in charge storage structure202(which can be a floating gate structure). As mentioned above, charge storage structure202can be the floating gate of transistor TL. During an operation (e.g., a read or write operation) of memory device200, an access line (e.g., a single access line) and a data line (e.g., a single data line) can be used to access a selected memory cell (e.g., target memory cell).

As shown inFIG.2, memory device200can include access lines (e.g., word lines)241,242,243, and244that can carry respective signals (e.g., word line signals) WL1, WL2, LW3, and WLn. Access lines241,242,243, and244can be used to access both memory cell groups2010and2011. In the physical structure of memory device200, each of access lines241,242,243, and244can be structured as (can be formed from) a conductive line (e.g., a single conductive line).

Access lines241,242,243, and244form control gates for respective memory cells (e.g., memory cells210through217inFIG.2) of memory device200to control access to the memory cells during an operation (e.g., read or write operation) of memory device200.

Memory device200can include conductive shield structures261and262, which are symbolically shown inFIG.2as lines (conductive lines). In the physical structure of memory device200, each of conductive shield structures261and262can be structured as conductive lines (e.g., conductive regions) that can have respective lengths parallel to the lengths of access lines241,242,243, and244.

Conductive shield structures261and262are not access lines (e.g., not word lines) of memory device200. The operations and functions of conductive shield structures261and262are unlike those of access lines241,242,243, and244. In a read or write operation, memory device200uses access lines241,242,243, and244as selected and unselected access lines to control (e.g., turn on or turn off) transistors T1and T2of selected memory cells and unselected memory cells. However, in a read or write operation of memory device200, each of conductive shield structures261and262is neither an access line (e.g., selected access line) for a selected memory cell (or selected memory cells) nor an access line (e.g., unselected access line) for unselected memory cells of memory device200. The conductive shield structures (e.g., conductive shield structures261and262) of memory device200allow relaxing of the threshold voltage of transistor T2, improve retention of the memory cells, and other improvements and benefits described below.

As shown inFIG.2, conductive shield structures261and262can be applied with a signal SHIELD. Signal SHIELD can be provided with a voltage during read and write operations of memory device200. The voltage applied to signal SHIELD during a read operation can be the same as (or can be different from) the voltage applied to signal SHIELD during a write operation. Signal SHIELD can be also provided with a voltage during a non-read operation (when a read operation is not performed) and during a non-write operation (when a write operation is not performed). Such non-read and non-write operations can occur in (e.g., can include) an idle mode, a standby mode, or in other inactive modes of memory device200. Conductive shield structures261and262can be biased at a constant bias (e.g., a constant voltage can be applied to signal SHIELD during read and write operations and during non-read and non-write operations (e.g., in inactive modes).

InFIG.2, access lines241,242,243, and244can be selectively activated (e.g., activated one at a time) during an operation (e.g., read or write operation) of memory device200to access a selected memory cell (or selected memory cells) among memory cells210through217. A selected memory cell can be referred to as a target memory cell. In a read operation, information can be read from a selected memory cell (or selected memory cells). In a write operation, information can be stored in a selected memory cell (or selected memory cells).

In memory device200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or turn off) transistors T1and T2of a respective memory cell during either a read or write operation of memory device200. Some conventional memory devices may use multiple (e.g., two separate) access lines to control access to a respective memory cell during read and write operations. In comparison with such conventional memory devices (that use multiple access lines for the same memory cell), memory device200uses a single access line (e.g., shared access line) in memory device200to control both transistors T1and T2of a respective memory cell to access the respective memory cell. This technique can save space and simplify operation of memory device200. Further, some conventional memory devices may use multiple data lines to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. In memory device200, a single data line (e.g., data line271or272) can be used to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. This may also simplify the structure, operation, or both of memory device200in comparison with conventional memory devices that use multiple data lines to access a selected memory cell.

In memory device200, the gate (not labeled inFIG.2) of each of transistors T1and T2can be part of a respective access line (e.g., a respective word line). As shown inFIG.2, the gate of each of transistors T1and T2of memory cell210can be part of access line241. The gate of each of transistors T1and T2of memory cell211can be part of access line241. For example, in the physical structure of memory device200, four different portions of a conductive material (e.g., four different portions of a continuous piece of metal or polysilicon) that forms access line241can form the gates (e.g., four gates) of transistors T1and T2of memory cell210and the gates of transistors T1and T2of memory cell211, respectively.

The gate of each of transistors T1and T2of memory cell212can be part of access line242. The gate of each of transistors T1and T2of memory cells213can be part of access line242. For example, in the structure of memory device200, four different portions of a conductive material (e.g., four different portions of a continuous piece of metal or polysilicon) that forms access line242can form the gates (e.g., four gates) of transistors T1and T2of memory cell212and the gates of transistors T1and T2of memory cell213, respectively.

The gate of each of transistors T1and T2of memory cell214can be part of access line243. The gate of each of transistors T1and T2of memory cell215can be part of access line243. For example, in the structure of memory device200, four different portions of a conductive material (e.g., four different portions of a continuous piece of metal or polysilicon) that forms access line243can form the gates (e.g., four gates) of transistors T1and T2of memory cell214and the gates of transistors T1and T2of memory cell215, respectively.

The gate of each of transistors T1and T2of memory cell216can be part of access line244. The gate of each of transistors T1and T2of memory cell217can be part of access line244. For example, in the structure of memory device200, four different portions of a conductive material (e.g., four different portions of a continuous piece of metal or polysilicon) that forms access line244can form the gates (e.g., four gates) of transistors T1and T2of memory cell216and the gates of transistors T1and T2of memory cell217, respectively.

In this description, a material can include a single material or a combination of multiple materials. A conductive material can include a single conductive material or combination multiple conductive materials.

Memory device200can include data lines (e.g., bit lines)271and272that can carry respective signals (e.g., bit line signals) BL1and BL2. During a read operation, memory device200can use data line271to obtain information read (e.g., sensed) from a selected memory cell of memory cell group2060, and data line272to read information from a selected memory cell of memory cell group2011. During a write operation, memory device200can use data line271to provide information to be stored in a selected memory cell of memory cell group2010, and data line272to provide information to be stored in a selected memory cell of memory cell group2011.

Memory device200can include a ground connection (e.g., ground plate)297coupled to each of memory cells210through217. Ground connection297can be structured from a conductive plate (e.g., a layer of conductive material) that can be coupled to a ground terminal of memory device200.

As an example (e.g., likeFIG.6D), ground connection297can be part of a common conductive structure (e.g., a common conductive plate) that can be formed on a level of memory device200that is under the memory cells (e.g., memory cells210through217) of memory device200. In this example, the elements (e.g., part of transistors T1and T2or the entire transistors T1and T2) of each of the memory cells (e.g., memory cells210through217) of memory device200can be formed (e.g., formed vertically) over the common conductive structure (e.g., a common conductive plate) and electrically coupled to the common conductive structure.

In another example (e.g., likeFIG.6E), ground connection297can be part of separate conductive structures (e.g., separate conductive strips) that can be formed on a level of memory device200that is under the memory cells (e.g., memory cells210through217) of memory device200. In this example, the elements (e.g., part of transistors T1and T2) of each of the memory cells (e.g., memory cells210through217) of memory device200can be formed over (e.g., formed vertically) respective conductive structures (e.g., respective conductive strips) among the separate conductive structures (e.g., separate conductive strips) and electrically coupled to the respective conductive structures.

As shown inFIG.2, transistor T1(e.g., the channel region of transistor T1) of a particular memory cell among memory cells210through217can be electrically coupled to (e.g., directly coupled to) ground connection297and electrically coupled to (e.g., directly coupled to) a respective data line (e.g., data line271or272). Thus, a circuit path (e.g., current path) can be formed between a respective data line (e.g., data line271or272) and ground connection297through transistor T1of a selected memory cell during an operation (e.g., a read operation) performed on the selected memory cell.

Memory device200can include read paths (e.g., circuit paths). Information read from a selected memory cell during a read operation can be obtained through a read path coupled to the selected memory cell. In memory cell group2010, a read path of a particular memory cell (e.g., memory cell210,212,214, or216) can include a current path (e.g., read current path) through a channel region of transistor T1of that particular memory cell, data line271, and ground connection297. In memory cell group2011, a read path of a particular memory cell (e.g., memory cell211,213,215, s) can include a current path (e.g., read current path) through a channel region of transistor T1of that particular memory cell, data line272, and ground connection297. In the example where transistor T1is a PFET (e.g., a PMOS), the current in the read path (e.g., during a read operation) can include a hole conduction (e.g., hole conduction in the direction from data line271to ground connection297through the channel region (e.g., p-channel region) of transistor T1). Since transistor T1can be used in a read path to read information from the respective memory cell during a read operation, transistor T1can be called a read transistor and the channel region of transistor T1can be called a read channel region.

Memory device200can include write paths (e.g., circuit paths). Information to be stored in a selected memory cell during a write operation can be provided to the selected memory cell through a write path coupled to the selected memory cell. In memory cell group2010, a write path of a particular memory cell can include transistor T2(e.g., can include a write current path through a channel region of transistor T2) of that particular memory cell and data line271. In memory cell group2011, a write path of a particular memory cell (e.g., memory cell211,213,215, or217) can include transistor T2(e.g., can include a write current path through a channel region of transistor T2) of that particular memory cell and data line272. In the example where transistor T2is an NFET (e.g., NMOS), the current in a write path (e.g., during a write operation) can include an electron conduction (e.g., electron conduction in the direction from data line271to charge storage structure202) through the channel region (e.g., n-channel region) of transistor T2. Since transistor T2can be used in a write path to store information in a respective memory cell during a write operation, transistor T2can be called a write transistor and the channel region of transistor T2can be called a write channel region.

Each of transistors T1and T2can have a threshold voltage (Vt). Transistor T1has a threshold voltage Vt1. Transistor T2has a threshold voltage Vt2. The values of threshold voltages Vt1and Vt2can be different (unequal values). For example, the value of threshold voltage Vt2can be greater than the value of threshold voltage Vt1. The difference in values of threshold voltages Vt1and Vt2allows reading (e.g., sensing) of information stored in charge storage structure202in transistor T1on the read path during a read operation without affecting (e.g., without turning on) transistor T2on the write path (e.g., path through transistor T2). This can prevent leaking of charge (e.g., during a read operation) from charge storage structure202through transistor T2of the write path.

In a structure of memory device200, transistors T1and T2can be formed (e.g., engineered) such that threshold voltage Vt1of transistor T1can be less than zero volts (e.g., Vt1<0V) regardless of the value (e.g., “0” or “1”) of information stored in charge storage structure202of transistor T1, and Vt1<Vt2. Charge storage structure202can be in state “0” when information having a value of “0” is stored in charge storage structure202. Charge storage structure202can be in state “1” when information having a value of “1” is stored in charge storage structure202. Thus, in this structure, the relationship between the values of threshold voltages Vt1and Vt2can be expressed as follows: Vt1for state “0”<Vt1for state “1”<0V, and Vt2=0V (or alternatively Vt2>0V).

In an alternative structure of memory device200, transistors T1and T2can be formed (e.g., engineered) such that Vt1for state “0”<Vt1for state “1,” where Vt1for state “0”<0V (or alternatively Vt1for state “0”=0V). Vt1for state “1”>0V, and Vt1<Vt2.

In another alternative structure, transistors T1and T2can be formed (e.g., engineered) such that Vt1for state “0”<Vt1for state “1.” where Vt1for state “0”=0V (or alternatively Vt1for state “0”>0V), and Vt1<Vt2.

During a read operation of memory device200, only one memory cell of the same memory cell group can be selected one at a time to read information from the selected memory cell. For example, memory cells210,212,214, and216of memory cell group2010can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells210,212,214, and216in this example). In another example, memory cells211,213,215, and217of memory cell group2011can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells211,213,215, and217in this example).

During a read operation, memory cells of different memory cell groups (e.g., memory cell groups2010and2011) that share the same access line (e.g., access line241,242,243, or244) can be concurrently selected (or alternatively can be sequentially selected). For example, memory cells210and211can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells210and211. Memory cells212and213can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells212and213. Memory cells214and215can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells214and215. Memory cells216and217can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells216and217.

The value of information read from the selected memory cell of memory cell group2010during a read operation can be determined based on the value of a current detected (e.g., sensed) from a read path (described above) that includes data line271, transistor T1of the selected memory cell (e.g., memory cell210,212,214, or216), and ground connection297. The value of information read from the selected memory cell of memory cell group2011during a read operation can be determined based on the value of a current detected (e.g., sensed) from a read path that includes data line272, transistor T1of the selected memory cell (e.g., memory cell211,213,215, or217), and ground connection297.

Memory device200can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) a current (e.g., current I1, not shown) on a read path that includes data line271and detect a current (e.g., current I2, not shown) on a read path that includes data line272. The value of the detected current can be based on the value of information stored in the selected memory cell. For example, depending on the value of information stored in the selected memory cell of memory cell group2010, the value of the detected current (e.g., the value of current I1) on data line271can be zero or greater than zero. Similarly, depending on the value of information stored in the selected memory cell of memory cell group2011, the value of the detected current (e.g., the value of current I2) on data line272can be zero or greater than zero. Memory device200can include circuitry (not shown) to translate the value of a detected current into the value (e.g., “0,” “1,” or a combination of multi-bit values) of information stored in the selected memory cell.

During a write operation of memory device200, only one memory cell of the same memory cell group can be selected at a time to store information in the selected memory cell. For example, memory cells210,212,214, and216of memory cell group2010can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cell210,212,214, and216in this example). In another example, memory cells211,213,215, and217of memory cell group2011can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cell211,213,215, and217in this example).

During a write operation, memory cells of different memory cell groups (e.g., memory cell groups2010and2011) that share the same access line (e.g., access line241,242,243, or244) can be concurrently selected. For example, memory cells210and211can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells210and211. Memory cells212and213can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells212and213. Memory cells214and215can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells214and215. Memory cells216and217can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells216and217.

Information to be stored in a selected memory cell of memory cell group2010during a write operation can be provided through a write path (described above) that includes data line271and transistor T2of the selected memory cell (e.g., memory cell210,212,214, or216). Information to be stored in a selected memory cell of memory cell group2011during a write operation can be provided through a write path (described above) that includes data line272and transistor T2of the selected memory cell (e.g., memory cell211,213,215, or217). As described above, the value (e.g., binary value) of information stored in a particular memory cell among memory cells210through217can be based on the amount of charge in charge storage structure202of that particular memory cell.

In a write operation, the amount of charge in charge storage structure202of a selected memory cell can be changed (to reflect the value of information stored in the selected memory cell) by applying a voltage on a write path that includes transistor T2of that particular memory cell and the data line (e.g., data line271or272) coupled to that particular memory cell. For example, a voltage having one value (e.g., 0V) can be applied on data line271(e.g., provide 0V to signal BL1) if information to be stored in a selected memory cell among memory cells210,212,214, and216has one value (e.g., “0”). In another example, a voltage having another value (e.g., a positive voltage) can be applied on data line271(e.g., provide a positive voltage to signal BL1) if information to be stored in a selected memory cell among memory cells210,212,214, and216has another value (e.g., “1”). Thus, information can be stored (e.g., directly stored) in charge storage structure202of a particular memory cell by providing the information to be stored (e.g., in the form of a voltage) on a write path (that includes transistor T2) of that particular memory cell.

FIG.3shows memory device200ofFIG.2including example voltages V1, V2, V3, and VSHIELD_Rused during a read operation of memory device200, according to some embodiments described herein. The example ofFIG.3assumes that memory cells210and211are selected memory cells (e.g., target memory cells) during a read operation to read (e.g., to sense) information stored (e.g., previously stored) in memory cells210and211. Memory cells212through217are assumed to be unselected memory cells. This means that memory cells212through217are not accessed, and information stored in memory cells212through217is not read while information is read from memory cells210and211in the example ofFIG.3. In this example, access line241can be called a selected access line (e.g., selected word line), which is the access line associated with (e.g., coupled to) selected memory cells (e.g., memory cells210and211in this example). In this example, access lines242,243, and244can be called unselected access lines (e.g., unselected word lines), which are the access lines associated with (e.g., coupled to) unselected memory cells (e.g., memory cells212through217in this example).

InFIG.3, voltages V1, V2, and V3can represent different voltages applied to respective access lines241,242,243, and244and data lines271and272during a read operation of memory device200. Voltage V1can be applied to the selected access line (e.g., access line241). In a read operation, Voltage V2can be applied to the unselected access lines (e.g., access lines242,243, and244).

Voltages V1, V2, and V3can have different values. As an example, voltages V1, V2, and V3can have values −1V, 0V, and 0.5V, respectively. The specific values of voltages used in this description are only example values. Different values may be used. For example, voltage V1can have a negative value range (e.g., the value of voltage V1can be from −3V to −1V).

In the read operation shown inFIG.3, voltage V1can have a value (voltage value) to turn on transistor T1of each of memory cells210and211(selected memory cells in this example) and turn off (or keep off) transistor T2of each of memory cells210and211. This allows information to be read from memory cells210and211. Voltage V2can have a value, such that transistors T1and T2of each of memory cells212through217(unselected memory cells in this example) are turned off (e.g., kept off). Voltage V3can have a value, such that a current (e.g., read current) may be formed on a read path that includes data line271and transistor T1of memory cell210and a read path (a separate read path) that includes data line272and transistor T1of memory cell212. This allows a detection of current on the read paths (e.g., on respective data lines271and272) coupled to memory cells210and211, respectively. A detection circuitry (not shown) of memory device200can operate to translate the value of the detected current (during reading of information from the selected memory cells) into the value (e.g., “0”, “1”, or a combination of multi-bit values) of information read from the selected memory cell. In the example ofFIG.3, the value of the detected currents on data lines271and272can be translated into the values of information read from memory cells210and211, respectively.

In the read operation shown inFIG.3, the voltages applied to respective access lines241,242,243, and244can cause transistors T1and T2of each of memory cells212through217, except transistor T1of each of memory cells210and211(selected memory cells), to turn off (or to remain turned off). Transistor T1of memory cell210(selected memory cell) may or may not turn on, depending on the value of the threshold voltage Vt1of transistor T1of memory cell210. Transistor T1of memory cell211(selected memory cell) may or may not turn on, depending on the value of the threshold voltage Vt1of transistor T1of memory cell211. For example, if transistor T1of each of memory cells (e.g.,210through217) of memory device200is configured (e.g., structured) such that the threshold voltage of transistor T1is less than zero (e.g., Vt1<−1V) regardless of the value (e.g., the state) of information stored in a respective memory cell210, then transistor T1of memory cell210, in this example, can turn on and conduct a current on data line271(through transistor T1of memory cell210). In this example, transistor T1of memory cell211can also turn on and conduct a current on data line272(through transistor T1of memory cell211). Memory device200can determine the value of information stored in memory cells210and211based on the value of the currents on data lines271and272, respectively. As described above, memory device200can include detection circuitry to measure the value of currents on data lines271and272during a read operation.

Voltage VSHIELD_Rcan have a negative value, zero volts, or a positive value. For example, voltage VSHIELD_Rcan have a range from −1V to +1V. Other values can be used. In some operations (e.g., read operations and non-read operations) of memory device200, using a negative value (or zero volts) for voltage VSHIELD_Rcan offer more benefit than using a positive value for voltage VSHIELD_R. For example, voltage VSHIELD_Rhaving a negative value (or zero volts) applied to conductive shield structure261can suppress or prevent potential leakage of current in memory cells that are adjacent conductive shield structure261or262, or both. This can improve retention of information stored in the adjacent memory cells.

FIG.4shows memory device200ofFIG.2including example voltages V4, V5, V6, V7, and VSHIELD_Wused during a write operation of memory device200, according to some embodiments described herein. The example ofFIG.4assumes that memory cells210and211are selected memory cells (e.g., target memory cells) during a write operation to store information in memory cells210and211. Memory cells212through217are assumed to be unselected memory cells. This means that memory cells212through217are not accessed and information is not to be stored in memory cells212through217while information is stored in memory cells210and211in the example ofFIG.4.

InFIG.4, voltages V4. V5. V6, and V7can represent different voltages applied to respective access lines241,242,243, and244and data lines271and272during a write operation of memory device200. In a write operation, voltage V4can be applied to the selected access line (e.g., access line241). Voltage V5can be applied to the unselected access lines (e.g., access lines242,243, and244).

Voltages V4, V5. V6, and V7can have different values. As an example, voltages V4and V5can have values of 3V and 0V, respectively. These values are example values. Different values may be used.

The values of voltages V6and V7can be the same or different depending on the value (e.g., “0” or “1”) of information to be stored in memory cells210and211. For example, the values of voltages V6and V7can be the same (e.g., V6=V7) if the memory cells210and211are to store information having the same value. As an example, V6=V7=0V if information to be stored in each memory cell210and211is “0”. In another example, V6=V7=V+ (e.g., V+ is a positive voltage (e.g., from 1V to 3V)) if information to be stored in each memory cell210and211is “1”.

In another example, the values of voltages V6and V7can be different (e.g., V6≠V7) if the memory cells210and211are to store information having different values. As an example, V6=0V if “0” is to be stored in memory cell210, and V7=V+ (e.g., V+ is a positive voltage (e.g., from 1V to 3V)) if “1” is to be stored in memory cell211. As another example, V6=V+ (e.g., V+ is a positive voltage (e.g., from 1V to 3V)) if “1” is to be stored in memory cell210, and V7=0V if “0” is to be stored in memory cell211.

The range of voltage of 1V to 3V is used here as an example. A different range of voltages can be used. Further, instead of applying 0V (e.g., V6=0V or V7=0V) to a particular write data line (e.g., data line271or272) for storing information having a value of “0” to the memory cell (e.g., memory cell210or211) coupled to that particular write data line, a positive voltage (e.g., V6>0V or V7>0V) may be applied to that particular data line.

In a write operation of memory device200ofFIG.4, voltage V5can have a value (e.g., V5=0V or V5<0V) such that transistors T1and T2of each of memory cells212through217(unselected memory cells, in this example) are turned off (e.g., kept off). Voltage V4can have a value (e.g., V4>0V) to turn on transistor T2of each of memory cells210and211(selected memory cells in this example) and form a write path between charge storage structure202of memory cell210and data line271and a write path between charge storage structure202of memory cell211and data line272. A current (e.g., write current) may be formed between charge storage structure202of memory cell210(selected memory cell) and data line271. This current can affect (e.g., change) the amount of charge on charge storage structure202of memory cell210to reflect the value of information to be stored in memory cell210. A current (e.g., another write current) may be formed between charge storage structure202of memory cell211(selected memory cell) and data line272. This current can affect (e.g., change) the amount of charge on charge storage structure202of memory cell211to reflect the value of information to be stored in memory cell211.

In the example write operation ofFIG.4, the value of voltage V6may cause charge storage structure202of memory cell210to discharge or to be charged, such that the resulting charge (e.g., charge remaining after the discharge or charge action) on charge storage structure202of memory cell210can reflect the value of information stored in memory cell210. Similarly, the value of voltage V7in this example may cause charge storage structure202of memory cell211to discharge or to be charged, such that the resulting charge (e.g., charge remaining after the discharge or charge action) on charge storage structure202of memory cell211can reflect the value of information stored in memory cell211.

Voltage VSHIELD_Wcan have a negative value, zero volts, or a positive value. For example, voltage VSHIELD_Rcan have a range from −1V to +1V. Other values can be used. Voltage VSHIELD_Wcan have a value that is the same as (equal) or different from the value of voltage VSHIELD_R. In some operations (e.g., write operations and non-write operations) of memory device200, using a negative value (or zero volts) for voltage VSHIELD_Wcan offer more benefit (e.g., improved retention, as described above) than using a positive value for voltage VSHIELD_R.

FIG.5A,FIG.5B, andFIG.6AthroughFIG.6Dshow different views of a structure of memory device200ofFIG.2with respect to the X, Y, and Z directions, according to some embodiments described herein.FIG.6Eshows a memory device200E, which is an alternative structure of memory device200ofFIG.6D. For simplicity, cross-sectional lines (e.g., hatch lines) are omitted from most of the elements shown inFIG.5AthroughFIG.6Eand other figures (e.g.,FIG.8AthroughFIG.23C) in the drawings described herein. Some elements of memory device200(and other memory devices described herein) may be omitted from a particular figure of the drawings so as to not obscure the description of the element (or elements) being described in that particular figure. The dimensions (e.g., physical structures) of the elements shown in the drawings described herein are not scaled.

FIG.5AandFIG.5Bshow different 3-dimensional views (e.g., isometric views) of memory device200including memory cell210with respect to the X, Y, and Z directions.FIG.6Ashows a side view (e.g., cross-sectional view) of memory device200including memory cells210,211,218,219with respect to the X-Z direction taken along line6A-6A ofFIG.6C.FIG.6Bshows a view (e.g., cross-sectional view) taken along line6B-6B ofFIG.6AandFIG.6C.FIG.6Cshows a top view (e.g., plan view) of memory device200ofFIG.6Aincluding relative locations of data lines271,272,273, and274(and associated signals BL1, BL2, BL3, and BL4), and access lines241,242,243, and244(associated signals WL1, WL2, WL3, and WL4).FIG.6Dshows a top view (e.g., plan view) of memory device200ofFIG.6Cincluding portions of data lines271,272,273, and274and common conductive structure (e.g., a common conductive plate) including semiconductor material596and ground connection297over substrate599.

As shown inFIG.5AandFIG.5B, memory device200can include conductive shield structures261and262located adjacent respective sides of memory cells210,212,214, and216. For example, conductive shield structure261is between and adjacent sides of memory cells210and212. Conductive shield structure262is between and adjacent sides of memory cells214and216.

Each of access lines241,242,243, and244can be located on a side of a respective memory cell that is opposite from the side of the respective memory cell where conductive shield structure261or262is located. Each of access line241and each of conductive shield structures261and262can include a structure (e.g., a piece (e.g., a layer)) of conductive material (e.g., metal, conductively doped polysilicon, or other conductive materials). Conductive shield structures261and262can have the same material as (or alternatively different materials from) access lines241,242,243, and244.

The following description refers toFIG.5AthroughFIG.6D.FIG.5Aand shows the structure of one memory cell (e.g., memory cell210) of memory device200with data line271shown in exploded view (separated from memory cell210) to show elements of memory cell210located below (under) data line271.FIG.5Ashows details of memory cell210. The structures of other memory cells (e.g., memory cells211through217inFIG.2) of memory device200can be similar to or the same as the structure of memory cell210inFIG.5AthroughFIG.6D. InFIG.2throughFIG.6C, the same elements are given the same reference numbers. Some portions (e.g., gate oxide and cell isolation structures) of memory device200are omitted fromFIG.5AthroughFIG.6Dso as to not obscure the elements of memory device200in the embodiments described herein.

As shown inFIG.5A, memory device200can include a substrate599over which memory cell210(and other memory cells (not shown) of memory device200) can be formed. Transistors T1and T2of memory cell210can be formed vertically with respect to substrate599. Substrate599can be a semiconductor substrate (e.g., silicon-based substrate) or other type of substrate. The Z-direction (e.g., vertical direction) is a direction perpendicular to (e.g., outward from) substrate599. The Z-direction is also perpendicular to (e.g., extended vertically from) the X-direction and the Y-direction. The X-direction and Y-direction are perpendicular to each other.

As shown inFIG.5A, ground connection297can include a structure (e.g., a piece (e.g., a layer)) of conductive material (e.g., conductive region) located over (formed over) substrate599. Example materials for ground connection297include a piece of metal, conductively doped polysilicon, or other conductive materials. Ground connection297can be coupled to a ground terminal (not shown) of memory device200.FIG.5Ashows ground connection297contacting (e.g., directly coupled to) substrate599, as an example. In an alternative structure, memory device200can include a dielectric (e.g., a layer of dielectric material, not shown) between ground connection297and substrate599.

As shown inFIG.5A, memory device200can include a semiconductor material596formed over ground connection297. Semiconductor material596can include a structure (e.g., a piece (e.g., a layer)) of silicon, polysilicon, or other semiconductor material, and can include a doped region (e.g., p-type doped region), or other conductive materials.

FIG.6Ashows memory cells218and219and associated data lines273and274that are not shown inFIG.2. However, as shown inFIG.6A, memory cells218and219can share access line241with memory cells210and211.FIG.6Ashows conductive shield structure261and access line241can be located on opposite sides (e.g., front side and back side with respect the Y-direction) of each of memory cells210,211,218, and219. Conductive shield structure261can have a length in the X-direction. Only a portion (e.g., cutaway view) of conductive shield structure261in the X-direction is shown inFIG.6Ato expose details of memory cells210,211,218, and219.

As shown inFIG.6A, conductive shield structure261can have a height H2in the Z-direction. As shown inFIG.6AandFIG.6B, access line241can have a height H1in the Z-direction. As shown inFIG.6B, the Z-direction is perpendicular to the Y-direction, which is also a direction from one memory cell to the next memory cell (e.g., from memory cell210to memory cell212) in the Y-direction. Heights H1and H2and can be the same (equal in dimension). However (e.g.,FIG.7), conductive shield structure261can be structured (e.g., formed) such that conductive shield structure261can have a height H2′ (FIG.6A) greater than height H2. Thus, the height of conductive shield structure261can be the same as the height of access line241(e.g., H2=H1) or greater than the height of access line241(e.g., H2′>H1).

As shown inFIG.6B, access line241can have a thickness W1the Y-direction, which is parallel to a direction from memory one memory cell to the next memory cell (e.g., from memory cell210to memory cell212) in the Y-direction. As shown inFIG.6B, conductive shield structure261can have thickness W2. Thickness W2can be greater than thickness W1(e.g., W2>W1). However (e.g.,FIG.8), conductive shield structure261can be structured (e.g., formed), such that conductive shield structure261can have a thickness (in the Y-direction) that is the same as (equal to) the thickness of access line241.

As shown inFIG.6B, like access line241, each of access lines242,243, and244can have height H1and thickness W1. Like conductive shield structure261, other conductive shield structures (e.g., conductive shield structure262) of memory device200can have height H2and a thickness W2.

As shown inFIG.6B, memory device200can include trenches290,291,292,293, and294that have different (unequal) widths (trench width) TW1and TW2. Each of trenches291and292can have width TW1. Trench292(also trenches290and294) can have width TW2. Width TW2can be greater than width TW1. Alternatively, trenches290,291,292,293, and294and have the same (equal) width. For example, in an alternative structure of memory device200, each of trenches291and291can have a width TW1′ (not shown), and trench292(also trenches290and294) can have a width TW2′ (not shown) where width TW1′ can be the same as width TW2′ (e.g., TW1′=TW2′).

As shown inFIG.6B, access lines241,242,243, and244and conductive shield structures261and262can be located in respective trenches290.291,292,293, and294. In memory device200, as shown inFIG.6B, not all trenches (fewer than all trenches)290,291,292,293, and294have an access line (or access lines) located in them. For example, trenches291and293do not have an access line located in them. Thus, trenches291and293are void of an access line (among access lines241,242,243, and244). This mean that none of access lines241,242,243, and244is located in trenches291and293. The trenches that do not have a conductive shield structure (e.g., conductive shield structures261or262) can have an access line (e.g., access line241in trench290or access line244in trench294) or multiple access lines (e.g., access lines242and243in trench292).

As shown inFIG.6B, memory device200can include dielectric materials545located in trenches290,291,292,293, and294to electrically separate access lines241,242,243, and244and conductive shield structures261and262from other elements (e.g., read and write channel regions, and charge storage structures) of the memory cells (e.g., memory cells210,212,214, and216) of memory device200.

Each of memory cells210,212,214, and216can be located between and adjacent two respective trenches among trenches290,291,292,293, and294. For example, memory cell210can be located between trenches290and291. Memory cell212can be located between trenches291and292.

Thus, as shown inFIG.6B, each memory cell can have opposite sides (e.g., left side and right side in the Y-direction). Each access line (e.g.,242) can be located in a trench (e.g.,292) and adjacent a side of a memory cell (e.g., right side of memory cell212) in the Y-direction. Each conductive shield structure can be located in trench (e.g.,291) and adjacent a side of a memory cell (e.g., left side of memory cell212) in Y-direction.

As shown inFIG.6B, each of conductive shield structures261and262in a particular trench (among trenches290,291,292,293, and294) can be electrically separated from the elements of adjacent memory cells by dielectric materials545in that particular trench. For example, as shown inFIG.6B, each of memory cells210,212,214, and216can include material (e.g., write channel region)520formed over charge storage structure202. Conductive shield structure261can be electrically separated from materials520of memory cells210and212by respective dielectric materials545in trench291. As shown inFIG.6B, dielectric materials545in trench291can be adjacent (e.g., can contact or indirectly contact) materials520and charge storage structures202of respective memory cells210and212. Conductive shield structure261can be between dielectric materials545and adjacent (e.g., contacting or indirectly contacting) dielectric materials545.

Charge storage structure202(FIG.5AthroughFIG.6D) of each memory cell of memory device200can include a charge storage material (or a combination of materials), which can include a piece (e.g., a layer) of semiconductor material (e.g., polysilicon), a piece (e.g., a layer) of metal, or a piece of material (or materials) that can trap charge. The materials for charge storage structure202and the access lines (e.g., access line241) of memory device200can be the same or can be different. As shown inFIG.5A,FIG.6A, andFIG.6B, charge storage structure202can include a portion (e.g., bottom portion) that is closer (e.g., extends in the Z-direction closer) to substrate599than the bottom of access line241.

As shown inFIG.6A, each charge storage structure202can include an edge (e.g., top edge)202′, and access line241can include an edge (e.g., bottom edge)241E.FIG.6Ashows an example where edge202′ is at a specific distance (e.g., distance shown inFIG.6A) from edge241E. However, the distance between edge202′ of charge storage structure202and edge241E of access line241can vary. For example,FIG.6Ashows edge241E being below edge202′ with respect to the Z-direction, such that access line241can overlap (in the Z-direction) charge storage structure202. However, edge241E can alternatively be above edge202′ with respect to the Z-direction, such that access line241may not overlap (in the Z-direction) charge storage structure202.

As shown inFIG.6A, material520can be located between data line271and charge storage structure202. Material520can be electrically coupled to (e.g., directly coupled to (contact)) data line271. Material520can also be electrically coupled to (e.g., directly coupled to (contact)) charge storage structure202of memory cell210. As described above, charge storage structure202of memory cell210can form the memory element of memory cell210. Thus, memory cell210can include a memory element (which is charge storage structure202) located between substrate599and material520with respect to the Z-direction and the memory element contacts (e.g., directly coupled to) material520.

Material520can form a source (e.g., source terminal), a drain (e.g., drain terminal), and a channel region (e.g., write channel region) between the source and the drain of transistor T2of memory cell210. Thus, as shown inFIG.5A.FIG.6A, andFIG.6B, the source, channel region, and the drain of transistor T2of memory cell210can be formed from a single piece of the same material (or alternatively, a single piece of the same combination of materials), such as material520. Therefore, the source, the drain, and the channel region of transistor T2of memory cell210can be formed from the same material (e.g., material520) of the same conductivity type (e.g., either n-type or p-type). Other memory cells of memory device200can also include material520like memory cell210.

Material520can include a structure (e.g., a piece (e.g., a layer)) of semiconductor material. In the example where transistor T2is an NFET (as described above), material520can include n-type semiconductor material (e.g., n-type silicon).

In another example, the semiconductor material that forms material520can include a structure (e.g., a piece) of oxide material. Examples of the oxide material used for material520include semiconducting oxide materials, transparent conductive oxide materials, and other oxide materials.

As an example, material520can include at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxide nitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

Using the materials listed above in memory device200provides improvement and benefits for memory device200. For example, during a read operation, to read information from a selected memory cell (e.g., memory cell210), charge from charge storage structure202of the selected memory cell may leak to transistor T2of the selected memory cell. Using the material listed above for the channel region (e.g., material520) of transistor T2can reduce or prevent such a leakage. This improves the accuracy of information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory device (e.g., memory device200) described herein.

The materials listed above are examples of material520. However, other materials (e.g., a relatively high band-gap material) different from the above-listed materials can be used.

As shown inFIG.5A,FIG.6A, andFIG.6B, material520and charge storage structure202of memory cell210can be electrically coupled (e.g., directly coupled) to each other, such that material520can contact charge storage structure202of memory cell210without an intermediate material (e.g., without a conductive material) between charge storage structure202of memory cell210and material520. In an alternative structure (not shown), material520can be electrically coupled to charge storage structure202of memory cell210, such that material520is not directly coupled to (not contacting) charge storage structure202of memory cell210, but material520is coupled to (e.g., indirectly contacting) charge storage structure202of memory cell210through an intermediate material (e.g., a conductive material) between charge storage structure202of memory cell210and material520.

As shown inFIG.5A,FIG.6A,FIG.6C, andFIG.6D, memory cell210can include a material510, which can include a structure (e.g., a piece (e.g., a layer)) of semiconductor material. Example materials for material510can include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon-germanium, or other semiconductor materials and semiconducting oxide materials (oxide semiconductors, e.g., SnO or other oxide semiconductors).

As described above with reference toFIG.2, transistor T1of memory cell210includes a channel region (e.g., read channel region). InFIG.5A,FIG.6A.FIG.6C, andFIG.6D, the channel region of transistor T1of memory cell210can include (e.g., can be formed from) material510. Material510can be electrically coupled to (e.g., directly coupled to (contact) data line271. As described above with reference toFIG.2, memory cell210can include a read path. InFIG.5AandFIG.6AthroughFIG.6D, material510(e.g., the read channel region of transistor T1of memory cell210) can be part of the read path of memory cell210that can carry a current (e.g., read current) during a read operation of reading information from memory cell210. For example, during a read operation, to read information from memory cell210, material510can conduct a current (e.g., read current (e.g., holes)) between data line271and ground connection297(through part of semiconductor material596). The direction of the read current can be from data line271to ground connection297(through material510and part of semiconductor material596). In the example where transistor T1is a PFET and transistor T2is an NFET, the material that forms material510can have a different conductivity type from material520. For example, material510can include p-type semiconductor material (e.g., p-type silicon) regions, and material520can include n-type semiconductor material (e.g., n-type gallium phosphide (GaP)) regions.

As shown inFIG.5AandFIG.6A, memory cell210can include dielectric materials515A and515B. Dielectric materials515A and515B can be gate oxide regions that electrically separate each of charge storage structure202and material520from material510(e.g., the channel region of transistor T1). Dielectric materials515A and515B can also electrically separate charge storage structure202from semiconductor material596.

Example materials for dielectric materials515A and515B include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials. In an example structure of memory device200, dielectric materials515A and515B include a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide). Using such a high-k dielectric material (instead of silicon dioxide) can improve the performance (e.g., reduce current leakage, increase drive capability of transistor T1, or both) of memory device200.

As shown inFIG.5AandFIG.6A, the memory cells (e.g., memory cells210,211,218, and219) of memory device200can share (e.g., can electrically couple to) semiconductor material596. For example, as shown inFIG.6A, the read channel regions of the memory cells (e.g., material510of each of memory cells210,211,218, and219) of memory device200can contact (e.g., can be electrically coupled to) semiconductor material596.

As shown inFIG.5AandFIG.6A, memory device200can include a conductive region597(e.g., a common conductive plate) under the memory cells (e.g., memory cells210,211,216, and217inFIG.6A) of memory device200. Conductive region597can include at least one of the materials (e.g., doped polysilicon) of semiconductor material596and the material (e.g., metal or doped polysilicon) of ground connection297. For example, conductive region597can include the material of semiconductor material596, the material of ground connection297, or the combination of the materials of semiconductor material596and ground connection297. Thus, as shownFIG.6A, the memory cells (e.g., memory cells210,211,216, and217) of memory device200can share conductive region597(which can include any combination of semiconductor material596and ground connection297).

As shown inFIG.5AandFIG.6A, access line241can be adjacent part of material510and part of material520and can span across (e.g., overlap in the X-direction) part of material510and part of material520. As described above, material510can form part of a read channel region of transistor T1and material520can form part of a write channel region of transistor T2. Thus, as shown inFIG.5AandFIG.6A, access line241can span across (e.g., overlap) part of (e.g., on a side (e.g., front side) in the Y-direction) both read and write channels of transistors T1and T2, respectively. As shown inFIG.6A, access line241can also span across (e.g., overlap in the X-direction) pail of material510(e.g., a portion of the read channel region of transistor T1) and part of material520(e.g., a portion of write channel region of transistor T2) of other memory cells (e.g., memory cells211,218, and219) of memory device200. The spanning (e.g., overlapping) of access line241across material510and material520allows access line241(a single access line) to control (e.g., to turn on or turn off) both transistors T1and T2of memory cells210,211,218, and219.

As shown inFIG.6A, memory device200can include dielectric material (e.g., silicon dioxide)526that can form a structure (e.g., a dielectric) to electrically separate (e.g., isolate) parts of two adjacent (in the X-direction) memory cells of memory device200. For example, dielectric material526between memory cells210and211can electrically separate material520(e.g., write channel region of transistor T2) of memory cell210from material520(e.g., write channel region of transistor T2) of memory cell211, and electrically separate charge storage structure202of memory cell210from charge storage structure202of memory cell211.

As shown inFIG.6A, memory device200can include dielectric portions555. Material (e.g., read channel region)510of two adjacent memory cells (e.g., memory cells211and218) can be electrically separated from each other by one of dielectric portions555. Some of portions (e.g., materials) of the memory cells of memory device200can be formed adjacent (e.g., formed on) a side wall (e.g., vertical portion with respect to the Z-direction) of a respective dielectric portion among dielectric portions555. For example, as shown inFIG.6A, material510(e.g., semiconductor material portion) of memory cell210can be formed adjacent (e.g., formed on) a side wall (not labeled) of dielectric portion555(on the left of memory cell210). In another example, material510(e.g., semiconductor material portion) of memory cell211can be formed adjacent (e.g., formed on) a side wall (not labeled) of dielectric portion555between memory cells211and216.

Dielectric materials545can be the same as (or alternatively, different from) the material (or materials) of dielectric materials515A and515B. Example materials for dielectric materials545can include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

The above description focuses on the structure of memory cell210. Other memory cells (e.g., memory cells211,218, and219inFIG.6A) of memory device200can include elements structured in ways similar or the same as the elements of memory cell210, described above. For example, as shown inFIG.6A, memory cell211can include charge storage structure202, material (e.g., write channel region)520, material510(e.g., read channel region), and dielectric materials525A and525B. The material (or materials) for dielectric materials525A and525B can the same as the material (or materials) for dielectric materials515A and515B. Memory cells218and219can include elements structured in ways similar or the same as the elements of memory cells210and211, respectively.

FIG.6Cshows a top view (e.g., plan view) of a portion of memory device200ofFIG.2.FIG.6A, andFIG.6B. For simplicity, some elements of memory device200are omitted fromFIG.6C.FIG.6Cshows relative locations of data lines271,272,273, and274(and associated signals BL1, BL2, BL3, and BL4), and access lines241,242,243, and244(associated signals WL1, WL2, WL3, and WL4).FIG.6Calso shows relative locations of trenches290,291,292,293, and294(also shown inFIG.6B).

The following description describes data line271. Other data lines (e.g., data lines272,273, and274) of memory device200can have similar structure and material as data line271. As shown inFIG.5A,FIG.5B,FIG.6A,FIG.6B, andFIG.6C, data line271(associated with signal BL1) can have a length in the Y-direction, a width in the X-direction, and a thickness in the Z-direction. Data line271can include a conductive material (or a combination of materials) that can be structured as a conductive line (e.g., conductive region) having a length in the Y-direction. Example materials for data line271include metal, conductively doped polysilicon, or other conductive materials. Other data lines272,273, and274(associated with signals BL2, BL3, and BL4, respectively) can have a length, a width, a thickness, and a material similar to or the same as data line271.

FIG.6Dshows a top view of memory device200including a common conductive structure (e.g., a common conductive plate) including semiconductor material596and ground connection297over substrate599.

FIG.6Eshows a top view of memory device200E including separate conductive structures (e.g., separate conductive strips) unlike the common conductive structure (e.g., a common conductive plate) ofFIG.6D. As shown inFIG.6E, semiconductor material596and ground connection297can be divided (e.g., patterned) into separate conductive structures having length along the Y-direction, which is also the direction of (e.g., parallel to) the length of each of data lines271,272,273, and274. Memory cells coupled to the same data line can share a respective conductive structure (formed under memory cells). In an alternative structure (not shown) of memory device200E, semiconductor material596and ground connection297can be divided (e.g., patterned) into separate conductive structures having length along the X-direction, which is also the direction of (e.g., parallel to) the length of each of access lines241,242,243, and244. Each of the conductive strips having the length in the Y-direction in the structure shown inFIG.6E(or having length in the X-direction (not shown) in an alternative structure) can be individually coupled ground during an operation (e.g., read or write operation) of memory device200E.

The structure of memory device200allows it to have a relatively smaller size (e.g., smaller footprint) and improved (e.g., reduced) power consumption (as result of using a single access line (e.g., word line) to control two transistors of a corresponding memory cell). Other improvements and benefits of memory device200are described below.

In the 2T memory cell structure of memory device200, the threshold voltage (e.g., Vt2) of transistor T2can be relatively high for proper operation of memory device200. For example, the threshold voltage of transistor T2can be relatively high, so that transistor T2can be properly turn on (e.g., during a write operation) and properly turn off (e.g., during a read operation). Including conductive shield structures (e.g., conductive shield structures261and262) in memory device200can allow transistor T2to have a relatively more relaxed threshold voltage (e.g., a reduced Vt2).

The conductive shield structures can also suppress or prevent potential leakage of current (e.g., leakage through transistor T2) in the memory cell. This can improve retention of information stored in the memory cell.

Further, the conductive shield structures of memory device200can reduce capacitive coupling between adjacent access lines. This can mitigate disturbance between the charge storage structures of adjacent memory cells associated with different access lines.

Moreover, the conductive shield structures may boost the capacitance of the charge storage structure (e.g., charge storage structure202) of memory device200. This can lead to improve operation (e.g., read operation) of memory device200.

FIG.7shows a memory device700including conductive shield structures261and262having respective heights (e.g., H2′) greater than the heights (e.g., H1) of access lines241242,243, and244, according to some embodiments described herein. As shown inFIG.7, each of heigh H2′ and H1is measured (e.g., in nanometers) in the Z-direction and height H2′ is greater than heigh H1(e.g., H2′ >H1) as also described above with reference toFIG.6A. Memory device700can have improvements and benefits similar to those of memory device200described above.

FIG.8shows a memory device800including conductive shield structures261and262and access lines241242,243, and244having the same thickness W3, according to some embodiments described herein. As shown in FIG.8, memory device800can include trenches (not labeled but they can be like trenches290,291,292,293, and294inFIG.6B) having respective widths TW1and TW2(like widths TW1and TW2inFIG.6B). Alternatively, the trenches of memory device800can have the same (equal) width. For example, in an alternative structure (not shown) of memory device800, trenches of memory device800can have the same width (e.g., width TW1=TW2, not shown inFIG.8). Memory device800can have improvements and benefits similar to those of memory device200described above.

As described above with reference toFIG.5AthroughFIG.8, memory devices200,200E (FIG.6E),70, and800can have conductive shield structures261and262, access lines241242,243, and244, and trenches290,292,293,294, and295with corresponding thicknesses and widths (e.g., W1, W2, W3, H1, H2, H2′, TW1, TW1′, TW2, and TW2′) shown inFIG.5AthroughFIG.8. However, the memory device described herein can be structured (e.g., can be formed) to include any combination of thicknesses and widths described above. For example, the thicknesses of widths of respective conductive shield structures261and262, access lines241242,243, and244, and trenches290,292,293,294, and295can be any combination of W1, W2, W3, H1, H2, H2′, TW1, TW1′, TW2, and TW2′.

FIG.9throughFIG.22Cshow different views of elements during processes of forming a memory device900, according to some embodiments described herein. Some or all of the processes used to form memory device900can be used to form memory devices200,200E,700, and800described above with reference toFIG.2throughFIG.8.

FIG.9shows memory device900after different levels (e.g., layers) of materials are formed in respective levels (e.g., layers) of memory device900in the Z-direction over a substrate999. The different levels of materials include a dielectric material930, a semiconductor material996, and a conductive material997. Dielectric material930, semiconductor material996, and conductive material997can be formed in a sequential fashion one material after another over substrate999. For example, the processes used inFIG.9can include forming (e.g., depositing) conductive material997over substrate999, forming (e.g., depositing) semiconductor material996over conductive material997, and forming (e.g., depositing) dielectric material930over semiconductor material996.

Substrate999can be similar to or identical to substrate599ofFIG.5. Conductive material997can include a material (or materials) similar to or identical to that of the material for ground connection297of memory device200(FIG.5throughFIG.8). For example, conductive material997can include metal, conductively doped polysilicon, or other conductive materials.

Semiconductor material996includes a material (or materials) similar to or identical to that of the material for semiconductor material596of memory device200(FIG.5AandFIG.6A). For example, semiconductor material996can include silicon, polysilicon, or other semiconductor material, and can include a doped region (e.g., p-type doped region). As described below in subsequent processes of forming memory device900, semiconductor material996can be structured to form part of a channel region (e.g., read channel region) for a respective memory cell of memory device900.

Dielectric materials930ofFIG.9can include a nitride material (e.g., silicon nitride (e.g., Si3N4)), oxide material (e.g., SiO2), or other dielectric materials. As described below in subsequent processes of forming memory device900, dielectric material930can be processed into dielectric portions to form part of cell isolation structures to electrically isolate one memory cell from another memory cell of memory device900.

FIG.10shows memory device900after trenches (e.g., openings)1001and1002are formed. Forming trenches1001and1002can include removing (e.g., by patterning) part of dielectric material930(FIG.9) at the locations of trenches1001and1002and leaving portions (e.g., dielectric portions)1031,1032, and1033(which are remaining portions of dielectric material930) as shown inFIG.10.

Each of trenches1001and1002can have a length in the Y-direction, a width (shorter than the length) in the X-direction, and a bottom (not labeled) resting on (e.g., bounded by) a respective portion of semiconductor material996. Each of trenches1001and1002can include opposing side walls (e.g., vertical side walls) formed by respective portions1031,1032, and1033. For example, trench1001can include a side wall1011(formed by portion1031) and a side wall1012(formed by portion1032). Trench1002can include a side wall1013(formed by portion1032) and a side wall1014(formed by portion1033).

FIG.11shows memory device900after a material1110′ and a material1110″ are formed (e.g., deposited) in trenches1001and1002, respectively. As shown inFIG.11, material1110′ can be formed on side walls1011and1012and on the bottom (e.g., on a portion of semiconductor material996) of trench1001. Material1110″ can be formed on side walls1013and1014and on the bottom (e.g., on another portion of semiconductor material996) of trench1002.

Materials1110′ and1110″ can be the same material. An example of material1110′ and material1110″ includes a semiconductor material. Materials1110′ and1110″ can have the same properties as the materials that form portions510A,510B,511A, and511B (e.g., read channel regions) of transistors T1of respective memory cells of memory device200ofFIG.5AandFIG.6A. As described below in subsequent processes (e.g.,FIG.19A) of forming memory device900, materials1110′ and1110″ can be structured to form channel regions (e.g., read channel regions) of transistors (e.g., transistors T1) of respective memory cells of memory device900. Thus, each of materials1110′ and1110″ can conduct a current (e.g., conduct holes) during an operation (e.g., a read operation) of memory device900.

The process of forming materials1110′ and1110″ can include a doping process. Such a doping process can include introducing dopants into materials1110′ and1110″ to allow a transistor (e.g., transistor T1) of a respective memory cell of memory device900to include a specific structure. For example, the doping process used inFIG.9can include introducing dopants (e.g., using a laser anneal process) with different dopant concentrations for different parts of materials1110′ and1110″, such that the transistor that includes material1110′ (or material1110″) can have a PFET structure. In such a PFET structure, part of material1110′ (or material1110″) can form a channel region (e.g., read channel region) to conduct currents (e.g., holes) during an operation (e.g., read operation) of memory device900.

FIG.12shows memory device900after dielectric materials (e.g., oxide materials)1215′ and1215″ are formed (e.g., deposited) on materials1110′ and1110″, respectively. Dielectric materials1215′ and1215″ can be deposited, such that dielectric materials1215′ and1215″ can be conformal to materials1110′ and1110″, respectively. Materials1215′ and1215″ can have the same properties as the materials (e.g., oxide materials) that form dielectric materials515A,515B.525A, and525B of memory device200ofFIG.5AandFIG.6A.

FIG.13shows memory device900after materials (e.g., charge storage materials)1302′,1302″,1302′″, and1302″″ are formed on respective side walls of materials1215′ and1215″. Materials1302′,1302″,1302′″, and1302″″ are electrically separated from each other. As described below in subsequent processes (FIG.19) of forming memory device900, each of materials1302′,1302″,1302′″,1302″″ can be structured to form a charge storage structure of a respective memory cell of memory device900. Materials1302′.1302″,1302′″,1302′″ can include material (e.g., polysilicon) similar or identical to the material of charge storage structure202of the memory cells (e.g., memory cell210or211) of memory device200(FIG.5AandFIG.6A).

FIG.14shows memory device900after dielectric materials1426′ and1426″ are formed (e.g., filled) in opened spaces in trenches1001and1002, respectively. Dielectric materials1426′ and1426″ can include an oxide material. As described below in subsequent processes of forming memory device900, dielectric materials1426′ and1426″ can form part of an isolation structure that can electrically isolate parts of (e.g., charge storage structures) two adjacent (in the X-direction) memory cells of memory device900.

FIG.15shows memory device900after dielectric materials1526′ and1526″ are formed at locations1501and1502, respectively. Forming dielectric materials1526′ and1526″ can include removing (e.g., by using an etch process) part (e.g., top part) of each of dielectric materials1426′ and1426″ (FIG.14), such that the remaining parts of dielectric materials1426′ and1426″ are dielectric materials1526′ and1526″ (FIG.15), respectively.

FIG.16shows memory device900after materials1602′,1602″,1602′″, and1602″″ are formed at locations1611and1612, respectively. Forming materials1602′,1602″,1602′″, and1602″″ can include removing (e.g., by using an etch process) part (e.g., top part) of each of dielectric materials1302′,1302″,1302′″, and1302″″ (FIG.13), such that the remaining parts of materials1302′.1302″,1302′″, and1302″″ are materials1602′,1602″,1602′″, and1602″″ (FIG.16), respectively.

InFIG.14.FIG.15, andFIG.16, part (e.g., top part) of dielectric materials1426′ and1426″ (FIG.14) and part (e.g., top part) of materials1302′,1302″,1302′″,1302″″ (FIG.14) were removed in separate processes (e.g., multiple steps) as described with reference toFIG.15andFIG.16. However, a single process (e.g., single step) can be used to remove part of dielectric materials1426′ and1426″ (FIG.14) and part of materials1302′,1302″,1302′″,1302″″ (FIG.14).

FIG.17shows memory device900after materials1720′,1721′,1720″, and1721″ are formed. Forming materials1720′,1721′,1720″, and1721″ can include depositing an initial material (or materials) on dielectric materials1526′ and1526″ and materials1602′,1602″,1602′″, and1602″″. Then, the process used inFIG.17can include removing (e.g., by using an etch process) a portion of the initial material at locations1701and1702. Materials1720′,1721′,1720″, and1721″ are the remaining portions of the initial material. As shown inFIG.17, materials1720′,1721′,1720″, and1721″ are electrically separated from each other. However, materials1720′,1721′,1720″, and1721″ are electrically coupled to (e.g., directly coupled to) materials1602′,1602″,1602′″, and1602″″, respectively.

Materials1720′,1721′,1720″, and1721″ can include materials similar or identical to material (e.g., write channel region)520(FIG.5AandFIG.6A) of transistor T2of memory device200ofFIG.5AandFIG.6A. As described below in subsequent processes (FIG.19) of forming memory device900, each of materials1720′,1721′,1720″, and1721″ can form a channel region (e.g., write channel region) of a transistor (e.g., transistor T2) of a respective memory cell of memory device900. Thus, each of materials1720′,1721′,1720″, and1721″ can conduct a current (e.g., conduct electrons) during an operation (e.g., a write operation) of memory device900.

FIG.18shows memory device900after dielectric materials1826′ and1826″ are formed at (e.g., filled in) locations1701and1702. Dielectric materials1826′ and1826″ can be the same as dielectric materials1426′ and1426″. As described below in subsequent processes of forming memory device900, dielectric materials1826′ and1826″ can form part of an isolation structure that can electrically isolate parts of (e.g., write channel regions) two adjacent (in the X-direction) memory cells of memory device900.

FIG.19Ashows memory device900after trenches1911,1912, and1913are formed (in the X-direction) across the materials of memory device900. Each of trenches1911,1912, and1913can have a length in the X-direction, a width (shorter than the length) in the Y-direction, and a bottom (not labeled) resting on (e.g., bounded by) a respective portion of semiconductor material996. Alternatively, each of trenches1911,1912, and1913can have a bottom (not labeled) resting on (e.g., bounded by) a respective portion of conductive material997(instead of semiconductor material996). Forming trenches1911,1912, and1913can include removing (e.g., by cutting (e.g., etching) in the Z-direction) part of the materials of memory device900at locations of trenches1911,1912, and1913and leaving portions (e.g., slices) of the structure of memory device900shown inFIG.19A.

After portions (at the locations of trenches1911,1912, and1913) of memory device900are removed (e.g., cut), the remaining portions can form parts of memory cells of memory device900. For example, memory device900can include memory cells210′,211′,210″, and211″ in one row along the X-direction, and cells212′,213′,212″, and213″ in another row along the X-direction. Memory cells210′ and211′ can correspond to memory cells210and211, respectively, of memory device200(FIG.2andFIG.7). Memory cells212′ and213′ inFIG.19Acan correspond to memory cells212and213, respectively, of memory device200(FIG.2).

For simplicity, only some of similar elements (e.g., portions) of memory device900inFIG.19Aare labeled. For example, memory device900can include dielectric portions (e.g., cell isolation structures)1931,1932,1933,1934,1935, and1936, and dielectric materials1926A and1926B. Dielectric portions1931and1932can correspond to two respective dielectric portions555of memory device200ofFIG.6A.

FIG.19Bshows an enlarged portion of memory device900ofFIG.19A. As shown inFIG.19B, memory cell210′ can include portions1910A and1910B (which can be part of the read channel region of memory cell210′), dielectric materials1915A and1915B, material (e.g., write channel region)1920, and charge storage structure1902(directly below material1920). Memory cell211′ can include portions1911A and1911B (which can be part of the read channel region of memory cell211′), dielectric materials1925A and1925B, material (e.g., write channel region)1921, and charge storage structure1902(directly below material1921).

As described above with reference toFIG.9throughFIG.19C, part of each of the memory cells of memory device900can be formed from a self-aligned process, which can include formation of trenches1001and1002(FIG.10A) in the Y-direction and trenches1911,1912, and1913(FIG.19A) in the X-direction. The self-aligned process can improve (e.g., increase) memory cell density, improve process (e.g., provide a higher process margin), or both.

FIG.20shows memory device900after dielectrics2045(e.g., oxide regions) are formed. Dielectrics2045can be concurrently formed (e.g., formed from the same process step and the same material). The material (or materials) for dielectrics2045can be the same as (or alternatively, different from) the material (or materials) of dielectric materials515A,515B,525A, and525B (FIG.6A). Example materials for dielectrics2045can include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

FIG.21shows memory device900after access lines2141and2142and conductive shield structure2161are formed. Access lines2141and2142and conductive shield structure2161can be concurrently formed (e.g., formed from the same process step and the same material). As shown inFIG.21, each of dielectric materials2045can be between respective memory cells and either an access line (e.g., access line2141or2142) or a conductive shield structure (e.g., conductive shield structure2161). Each of access lines2141and2142and conductive shield structure261can contact a respective dielectric material2045.

Access lines2141and2412can correspond to access lines214and242, respectively, of memory device200(FIG.2throughFIG.6D). Conductive shield structure2161can correspond to conductive shield structure261memory device200(FIG.2throughFIG.6D). The processes associated withFIG.21can form other access lines and conductive shield structures of memory device900similar to or the same as the access lines and conductive shield structures of memory device200described above with reference toFIG.2toFIG.6D.

InFIG.21, each of access lines2141and2142and conductive shield structure2161can include metal, conductively doped polysilicon, or other conductive materials. As shown inFIG.21, access lines2141and2142and conductive shield structure2161are electrically separated from memory cells210′,211′,210″,211″,212′,213′,212″, and213″ by respective dielectric materials2045.

Access line2141can be structured as a conductive line (e.g., conductive region) that can be used to control the read and write transistors (e.g., transistor T1and T2, respectively) of respective memory cells210′,211′,210″, and211″. Access line2142can be structured as a conductive line (e.g., conductive region) that can be used to control the read and write transistors (e.g., transistor T1and T2, respectively) of respective memory cells212′,213′,212″, and213″.

Conductive shield structure2161is neither an access line (e.g., word line) of memory cells210′,211′,210″, and211″ nor an access line (e.g., word line) of memory cells212′,213′,212″, and213″. Conductive shield structure2161can correspond to (operate in ways similar to) conductive shield structure261memory device200(FIG.2throughFIG.6D).

FIG.22Ashows memory device900after a dielectric material2235is formed. Dielectric material2235can fill the structure of memory device900as shown inFIG.22A. Portion1910A and material1920(e.g., read channel region and write channel region, respectively) of respective memory cells212′ and213′ are exposed. Portion1911A and material1921(e.g., read channel region and write channel region, respectively) of memory cell211′ are exposed.

FIG.22Bshows memory device900after a conductive material2220is formed. Conductive material2220can be formed (e.g., deposited) over exposed portion1910A, material1920, portion1911A, and material1921(shown inFIG.22A) and over other elements of memory device900.

FIG.22Cshows memory device900after data lines2271,2272,2273, and2274are formed. Data lines2271,2272,2273, and2274can correspond to data lines data lines221,222,223, and224, respectively, of memory device200(FIG.6AandFIG.6C).

Data lines2271,2272,2273, and2274can be concurrently formed. For example, a process (e.g., patterning process) can be performed to remove a portion of conductive material2200(FIG.22B). InFIG.22C, data lines2271,2272,2273, and2274are the remaining portion of conductive material2200.

As shown inFIG.22C, data lines2271,2272,2273, and2274are electrically separated from each other. Each of data lines2271,2272,2273, and2274can have a length in the Y-direction, a width in the X-direction, and a thickness in the Z-direction.

The description of forming memory device900with reference toFIG.9throughFIG.22Ccan include other processes to form a complete memory device. Such processes are omitted from the above description so as to not obscure the subject matter described herein.

The process of forming memory device900as described above can have a relatively reduced number of masks (e.g., reduced number of critical masks) in comparison with some conventional processes. For example, by forming trenches1001and1002in the process associated withFIG.10A, and forming trenches1911,1912, and1913in the process ofFIG.19A, the number of critical masks used to form the memory cells of memory device900can be reduced. The reduced number of masks can simplify the process, reduce cost, or both, of forming memory device900. Further, the access lines (e.g., access lines2141and2142) and the conductive shield structures (e.g., conductive shield structure2161) of memory device900allows it to have improvements and benefits similar to those of memory device200(FIG.2throughFIG.6D).

FIG.23A.FIG.23B, andFIG.23Cshow different views of a structure of a memory device2300including multiple decks of memory cells, according to some embodiments described herein.FIG.23Ashows an exploded view (e.g., in the Z-direction) of memory device2300.FIG.23Bshows a side view (e.g., cross-sectional view) in the X-direction and the Z-direction of memory device2300.FIG.23Cshows a side view (e.g., cross-sectional view) in the Y-direction and the Z-direction of memory device2300.

As shown inFIG.23A, memory device2300can include decks (decks of memory cells)23050,23051,23052, and23053that are shown separately from each other in an exploded view to help ease of viewing the deck structure of memory device2300. In reality, decks23050,23051,23052, and23053can be attached to each other in an arrangement where one deck can be formed (e.g., stacked) over another deck over a substrate (e.g., a semiconductor (e.g., silicon) substrate)2399. For example, as shown inFIG.23BandFIG.23C, decks23050,23051,23052, and23053can be formed in the Z-direction perpendicular to substrate2399(e.g., formed vertically in the Z-direction with respect to substrate2399).

As shown inFIG.23A,FIG.23B, andFIG.23C, each of decks23050,23051,23052, and23053can have memory cells arranged in the X-direction and the Y-direction (e.g., arranged in rows in the X-direction and in columns in the Y-direction). For example, deck23050can include memory cells23100,23110,23120, and23130(e.g., arranged in a row), memory cells23200,23210,23220, and23230(e.g., arranged in a row), and memory cells23300,23310,23320, and23330(e.g., arranged in a row).

Deck23051can include memory cells23101,23111,23121, and23131(e.g., arranged in a row), memory cells23201,23211,23221, and23231(e.g., arranged in a row), and memory cells23301,23311,23321, and23331(e.g., arranged in a row).

Deck23052can include memory cells23102,23112,23122, and23132(e.g., arranged in a row), memory cells23202,23212,23222, and23232(e.g., arranged in a row), and memory cells23302,23312,23322, and23332(e.g., arranged in a row).

Deck23053can include memory cells23103,23113,23123, and23133(e.g., arranged in a row), memory cells23203,23213,23223, and23233(e.g., arranged in a row), and memory cells23303,23313,23323, and23333(e.g., arranged in a row).

As shown inFIG.23A,FIG.23B, andFIG.23C, decks23050,23051,23052, and23053can be located (e.g., formed vertically in the Z-direction) on levels (e.g., portions)2350,2351,2352, and2353, respectively, of memory device2300. The arrangement of decks23050,23051,23052, and23053forms a 3-dimensional (3-D) structure of memory cells of memory device2300in that different levels of the memory cells of memory device2300can be located (e.g., formed) in different levels (e.g., different vertical portions)2350,2351,2352, and2353of memory device2300.

Decks23050,23051,23052, and23053can be formed one deck at a time. For example, decks23050,23051,23052, and23053can be formed sequentially in the order of decks23050,23051,23052, and23053(e.g., deck23051is formed first and deck23053is formed last). In this example, the memory cell of one deck (e.g., deck23051) can be formed either after formation of the memory cells of another deck (e.g., deck23050) or before formation of the memory cells of another deck (e.g., deck23052). Alternatively, decks23050,23051,23052, and23053can be formed concurrently (e.g., simultaneously), such that the memory cells of decks23050,23051,23052, and23053can be concurrently formed. For example, the memory cells in levels2350,2351,2352, and2353of memory device2300can be concurrently formed.

The structures decks23050,23051,23052, and23053can include the structures of the memory devices above with reference toFIG.1throughFIG.22C. For example, memory device2300can include data lines (e.g., bit lines) and access lines (e.g., word lines) to access the memory cells of decks23050,23051,23052, and23053. For simplicity, data lines and access lines of memory cells are omitted fromFIG.23A. However, the data lines and access lines of memory device2300can be similar to the data lines and access lines, respectively, of the memory devices described above with reference toFIG.1throughFIG.22C.

FIG.23A,FIG.23B, andFIG.23Cshow memory device2300including four decks (e.g.,23050,23051,23052, and23053) as an example. However, the number of decks can be different from four.FIG.23Ashows each of decks23050,23051,23052, and23053including one level (e.g., layer) of memory cells as an example. However, at least one of the decks (e.g., one or more of decks23050,23051,23052, and23053) can have two (or more) levels of memory cells.FIG.23Ashows an example where each of decks23050,23051,23052, and23053includes four memory cells (e.g., in a row) in the X-direction and three memory cells (e.g., in a column) in the Y-direction. However, the number of memory cells in a row, in a column, or both, can vary. Since memory device2300can include the structures of memory devices200,200E,700,800, and900, memory device2300can also have improvements and benefits like memory devices200,200E,700,800, and900.

The illustrations of apparatuses (e.g., memory devices100,200,200E,700,800,900, and2300) and methods (e.g., methods of forming memory device900) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of apparatuses that might make use of the structures described herein. An apparatus herein refers to, for example, either a device (e.g., any of memory devices100,200,200E,700,800,900, and2300) or a system (e.g., an electronic item that can include any of memory devices100,200,200E,700,800,900, and2300).

Any of the components described above with reference toFIG.1throughFIG.23Ccan be implemented in a number of ways, including simulation via software. Thus, apparatuses (e.g., memory devices100,200,200E,700,800,900, and2300) or part of each of these memory devices described above, may all be characterized as “modules” (or “module”) herein. Such modules may include hardware circuitry, single- and/or multi-processor circuits, memory circuits, software program modules and objects and/or firmware, and combinations thereof, as desired and/or as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and ranges simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.

The memory devices (e.g., memory devices100,200,200E,700,800,900, and2300) described herein may be included in apparatuses (e.g., electronic circuitry) such as high-speed computers, communication and signal processing circuitry, single- or multi-processor modules, single or multiple embedded processors, multicore processors, message information switches, and application-specific modules including multilayer, multichip modules. Such apparatuses may further be included as subcomponents within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group. Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.

The embodiments described above with reference toFIG.1throughFIG.23Cinclude apparatuses and methods of forming and operating the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials. Other embodiments, including additional apparatuses and methods, are described.

In the detailed description and the claims, the term “on” used with respect to two or more elements (e.g., materials), one “on” the other, means at least some contact between the elements (e.g., between the materials). The term “over” means the elements (e.g., materials) are in close proximity, but possibly with one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither “on” nor “over” implies any directionality as used herein unless stated as such.

In the detailed description and the claims, a list of items joined by the term “at least one of” can mean any combination of the listed items. For example, if items A and B are listed, then the phrase “at least one of A and B” means A only; B only; or A and B. In another example, if items A, B, and C are listed, then the phrase “at least one of A, B, and C” means A only; B only; C only; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A. B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

In the detailed description and the claims, a list of items joined by the term “one of” can mean only one of the list items. For example, if items A and B are listed, then the phrase “one of A and B” means A only (excluding B), or B only (excluding A). In another example, if items A, B, and C are listed, then the phrase “one of A. B, and C” means A only; B only; or C only. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

The above description and the drawings illustrate some embodiments of the inventive subject matter to enable those skilled in the art to practice the embodiments of the inventive subject matter. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.