Patent ID: 12224748

DETAILED DESCRIPTION

FIG.1depicts an integrated-circuit (IC) die100in accordance with one embodiment. Die100includes a pseudo-differential receiver105that compares an input signal RXi, received via a pad110, with a reference voltage Vref on a like-named voltage terminal or node to produce an output signal RXo. Die100also includes programmable on-die termination (ODT) circuitry115that can be programmed to provide either of two common termination topologies for high-speed communications: the so-called “rail-to-rail” topology and the so-called “half-supply” topology. The choice of termination topology is then left to the discretion of the user of IC die100. An external source or internal memory120can deliver a signal S/P to temporarily or permanently select one of the two configurations.

ODT circuitry115includes two termination legs extending from the communication port between pad110and receiver105. The upper termination leg includes a first termination impedance125and a first termination switch130. Switch130includes three switch nodes, two of which are connected to supply voltage Vodt and reference voltage Vref, respectively. The third switch node is coupled to the communication port via termination impedance125. The lower termination leg includes a second termination impedance135and a second termination switch140similar to switch130. Two switch nodes of switch140are connected to ground and reference voltage Vref, respectively, while the third is coupled to the communication port via termination impedance135. Both switches130and140are two position switches responsive to signal S/P from memory120to selectively couple one of the first and second switch nodes to the third switch node.

In rail-to-rail or serial terminations, the communication channel is coupled to each of two opposite supply voltages via a pair of termination impedances. To select a rail-to-rail termination topology, switches130and140are switched to supply nodes Vodt and ground, respectively. In that case, the input terminal to receiver105is coupled to Vodt and ground via respective impedances125and135. Termination voltage Vodt on the like-named supply node is supply voltage Vdd in some embodiments, but may be a different fixed voltage or a variable voltage in other embodiments.

In half-supply or parallel terminations, the communication channel is coupled to a reference voltage between the two supply voltages. To select a half-supply termination topology, switches130and140are both switched to voltage Vref, in which case the input terminal to receiver105is coupled to the reference voltage terminal Vref via parallel impedances125and135. As the name implies, the reference voltage in half-supply terminations is typically half the difference between the voltages on the supply nodes (e.g., Vref=½ (Vdd−Gnd)), but voltage Vref may be a different fixed voltage or a variable voltage in other embodiments.

IC die100optionally includes a coupling switch145between pad110and the input terminal of receiver105. An external or internal signal, such as from memory120, can deliver a signal AC/DC to temporarily or permanently open or close switch145. When switch145is closed, receiver105is DC coupled to pad110: when open, receiver105is AC coupled to pad110via a capacitor150.

Impedances125and135may be adjustable and capable of calibration. Suitable calibration methods and circuits are detailed in U.S. Pat. No. 6,924,660 entitled “Calibration Methods and Circuits for Optimized On-Die Termination,” which is incorporated herein. Switches130,140, and145can be fashioned of transistors, as is well understood by those of skill in the art. Capacitor150may also be adjustable using methods and circuits detailed below in connection withFIG.6.

FIG.2depicts a communication system200in accordance with another embodiment. System200has features in common with IC die100ofFIG.1, like-numbered elements being the same or similar. System200includes ODT circuitry that can selectively introduce filter elements that may be useful for low power configurations. Further, the selection can be accomplished dynamically in some embodiments, which allows system200to select appropriate ODT characteristics for high and low-frequency communication. This flexibility is useful for example in systems that support both a low-frequency, power-saving mode and a high-frequency, high-performance mode.

System200includes a transmitter IC die205coupled to a receiver IC die210via a single-ended communication port made up of pads215, a channel220, and related conductors on dies205and210. Die205includes a transmitter225and a pair of termination legs230. Legs230may be the same or similar to the termination legs detailed in connection with the receiver dies100and210ofFIGS.1and2. Transmitter225conveys a signal TX to receiver105on die210via pad215and the other elements of the associated communication port.

IC die210includes ODT circuitry235that can select either a filtered or unfiltered half-supply termination topology. The termination topology is then left to the discretion of the user of IC die210. The topology may be fixed, defined at start up, or allowed to change dynamically to support different performance modes. In the depicted embodiment, termination select logic240issues a control signal L/H, the state of which identifies either a lower-performance, lower-power mode, or a higher-performance, higher-power mode.

ODT circuitry235includes two termination legs extending from the communication port between pad215and receiver105of die210. The upper termination leg includes a first termination impedance245and a first termination switch250. Switch250includes three switch nodes, two of which are connected to reference voltage Vref, one directly and the other via a filter capacitor255. The third switch node is coupled to the communication port via termination impedance245. The lower termination leg is substantially the same. The switches of the upper and lower termination legs are responsive to signal L/H from termination select logic240.

The switches of both termination legs connect their respective termination resistors directly to voltage node Vref in a high-performance mode, and to voltage node Vref via a respective filter capacitor in a low-frequency mode. Filtering the input signal in the low-frequency mode advantageously dampens high-frequency noise components. The filter capacitors may be adjustable in some embodiments to allow filter tuning. Fixed or adjustable resistors in series and/or in parallel with the filter capacitors can also be included.

FIG.3depicts an IC die300in accordance with another embodiment. Die300includes a receiver305that compares an input signal RXi with a reference voltage Vref on a like-named voltage node to produce an output signal RXo. Die300also includes programmable ODT circuitry310that can be programmed to provide filtered or unfiltered rail-to-rail or a half-supply termination topologies, and thus combines the functionality of the embodiments ofFIGS.1and2.

ODT circuitry310includes two termination legs. Each leg includes switches315and320, a filter capacitor325, and a termination impedance330. Switches315and320support four modes as follows:1. Unfiltered Rail-to-Rail: Switches320are closed and switches315of the upper and lower termination legs select nodes Vodt and Ground, respectively.2. Filtered Rail-to-Rail: Switches320are open and switches315of the upper and lower termination legs select nodes Vodt and Ground, respectively.3. Unfiltered Half-Supply: Switches320are closed and switches315both select node Vref.4. Filtered Half-Supply: Switches320are open and switches315both select node Vref.
ODT circuitry310can be adapted to support more modes. Additional supply voltages can be supported, for example, and the impedances and capacitances can be adjustable.

FIG.4depicts a communication system400that employs configurable ODT circuitry in accordance with another embodiment. The configurable ODT circuitry allows a transmitter die405to select between two or more termination voltages when transmitting data to a receiver die410over a differential communication channel415. The resulting output common-mode voltage can thus be tailored to the needs of a receiver on die410. If, for example, multiple receivers timeshare a common bus but require or benefit from different receive termination voltages, then the associated transmitter or transmitters can use the termination voltage best suited for the receiver with which they are communicating. A communication channel may also support different operational modes that require or benefit from different termination voltages. A transmitter might, for example, support a loop-back communication mode for self test or initialization that employs a first termination voltage, and additionally support one or more operational modes that employ different termination voltages suitable for one or more target receivers.

Die405includes a differential transmitter with two identical or nearly identical termination legs. Each leg includes a fixed or adjustable termination impedance417and a voltage-select switch420. The state of switches420are controlled using select signal S that may be provided externally or internally, as by a memory425. Control logic can be included to dynamically alter the states of switches420, which can alternatively select either of two termination voltages V1and V2. In other embodiments, a variable voltage source is used in lieu of switches420and the two supply nodes.

FIG.5depicts a communication system500in accordance with yet another embodiment. Communication system500includes a transmitting die505communicating with a receiving die510via a differential channel515. The transmitting die includes differential output pads513coupled via the channel to input pads517of the receiving die. In one embodiment, communication system500includes a transmitter520that employs low-voltage differential signaling (LVDS) for serial data transmission to a corresponding receiver525, though other types of signaling may also be used. System500optionally includes an external differential termination resistor530(in phantom).

Die510includes programmable ODT circuitry that can select from a number of possible termination topologies. In support of this selectivity, die510includes three termination legs that extend from a common node535, two to the differential input terminals to receiver525and one to a reference voltage node, e.g. ground. Each of the first two termination legs includes a termination impedance540and a switch545connected in series. The third termination leg includes a capacitance550, a termination impedance555, and a switch560. The inclusion of impedances540and as associated switches545allows for the omission of external resistor530. The third leg allows for the selective incorporation of a noise-reducing RC filter. The impedances and capacitance of the ODT circuitry ofFIG.5are variable in some embodiments, which allows filter and termination values to be trimmed for improved performance. Switches545and560can be controlled by external or internal control signals applied to switch control terminals (not shown). The various capacitive and resistive elements can be similarly controlled.

FIG.6depicts a configurable RC circuit600that can be used in place of the third termination leg of die510ofFIG.5, which extends between node535and ground. Circuit600includes some memory605, the outputs of which are coupled to the control terminals of a plurality of transistors610. The transistors610selectively couple one or more differently sized capacitors615between node535and ground. In addition to controlling the capacitance, the resistance between nodes535and ground can be adjusted by selecting various combinations of transistors. The width-to-length ratios of transistors610may be varied to provide various impedances so that enabling different combinations of transistors provides different levels of termination impedance.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “de-asserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits.

An output of a process for designing an integrated circuit, or a portion of an integrated circuit, comprising one or more of the circuits described herein may be a computer-readable medium such as, for example, a magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing circuitry that may be physically instantiated as an integrated circuit or portion of an integrated circuit. Although various formats may be used for such encoding, these data structures are commonly written in Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), or Electronic Design Interchange Format (EDIF). Those of skill in the art of integrated circuit design can develop such data structures from schematic diagrams of the type detailed above and the corresponding descriptions and encode the data structures on computer readable medium. Those of skill in the art of integrated circuit fabrication can use such encoded data to fabricate integrated circuits comprising one or more of the circuits described herein.

While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example, the embodiments can be adapted for use with various single-ended and differential communication schemes over unidirectional and bidirectional channels. Specific examples include Series Stub Terminated Logic (SSTL) and double-data-rate (DDR) signaling, though this is by no means an exhaustive list. Embodiments may also be used for channels employing various modulation schemes, including those that employ multi-pulse-amplitude-modulation (multi-PAM) and single-PAM signals. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or “coupling,” establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. § 112.