Patent ID: 12262540

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over, or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” “top,” “bottom” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In general, 3D memory systems have been growing in popularity for their ability to have high performance, low power, and area reduction. Still, there is a growing need for memory devices that are both fast and able to store a dense amount memory in various applications such as CIM applications. For CIM applications, memory devices can have multiple functions such as storing memory but also computing. In order to optimize performance and area reduction, it is advantageous for the memory device that is used for storing memory and the memory device for computing have different structures and operations. In the existing technologies that do not use the disclosed devices and methods, 3D memory chips have only one type of memory that can disadvantageously limit the multi-functionality of CIM applications. Thus, the existing 3D memory systems have not been entirely satisfactory in every aspect.

The present disclosure relates to a 3D memory device and methods of manufacturing the same. The 3D memory device, as disclosed herein, includes two types of memory cells. Each type of memory cell can form their own array and banks, and those banks can be formed adjacent to each other. The first type of memory array can include high-endurance memory cells that can be used for high-bandwidth computing. The second type of memory array can include 2-bit memory cells which can be used for mass data storage. By having the two types of memory arrays fabricated on the same chip, the memory device can be used, for example, for CIM applications. In various embodiments, the high-endurance memory cells share source/select line between two adjacent memory cells, and the 2-bit memory cells store more data in a given area. Accordingly, the memory device can include a higher number of 3D memory devices to reduce a cost of fabrication per 3D memory system. By including two types of memory cells on the same chip, even more area can be reduced on a circuit board because two different types of memory chips are not needed. Furthermore, for next generation CIM applications, it is beneficial to have the computing and data storage memories close to each other because it reduces latency and increases performance.

FIGS.1A and1Brespectively illustrate two example structures of a 3D memory device, in accordance with some embodiments. It should be appreciated that the 3D memory device ofFIGS.1A-Bare merely illustrative examples, and thus, the 3D memory device can include any of various other components, while remaining within the scope of present disclosure.

Referring first toFIG.1A,3Dmemory device100A includes a memory bank102a, a memory bank104a, and a bank isolation region108. The memory bank102aincludes a plurality of memory arrays (or sub-arrays)102b, which includes a plurality of memory cells102c. The memory bank104aincludes a plurality of memory arrays (or sub-arrays)104b, which includes a plurality of memory cells104c. Memory arrays102bare separated from each other within the memory bank102aby sub-array isolation layers106, and the memory arrays104bare separated from each other within the memory bank104aby the sub-array isolation layers106. The bank isolation region108includes an insulation layer that separates the memory bank102aand memory bank104afrom each other. Although the memory device100A is shown to have a certain number of cells, embodiments are not limited thereto, and there can be more or fewer memory cells and still be within the scope of the present disclosure. Furthermore, the memory cells102and104are shown to have a cubic shape for simplicity purposes only and embodiments are not limited thereto.

The memory device100A includes a 2×4 structure on both of the memory banks102aand104a. There are 2 rows and 4 columns of memory arrays102bin the memory bank102a, and 2 rows and 4 columns of memory arrays104bin memory bank104a. However, embodiments are not limited thereto, and the memory device100A can include any combination of memory arrays102band104b.

The memory cells102ccan include high endurance 3D (“HE”) memory cells in which two adjacent HE memory cells are connected to a common source/select line (“SL”). The memory cell102bcan be advantageous for high-bandwidth computing operations because the common SL can be used to increase performance. The memory cell104bcan include a 2-bit 3D memory cell that can be used for mass data storage before computing because the 2 bits per cell can increase density. In this disclosure, the memory cells102band104binclude ferroelectric memory cells, but embodiments are not limited thereto, and any type of 3D memory cell can be used.

Referring next toFIG.1B, 3D memory device100B includes a memory bank112a, a memory bank114a, and a bank isolation region118. The memory bank112aincludes a plurality of memory arrays (or sub-arrays)112b, which includes a plurality of memory cells112c. The memory bank114aincludes a plurality of memory arrays (or sub-arrays)114b, which includes a plurality of memory cells114c. Memory arrays112bare separated from each other within the memory bank112aby sub-array isolation layers116, and the memory arrays114bare separated from each other within the memory bank114aby the sub-array isolation layers116. The bank isolation region118includes an insulation layer that separates the memory bank112aand memory bank114afrom each other. Although the memory device100B is shown to have a certain number of cells, embodiments are not limited thereto, and there can be more or fewer memory cells and still be within the scope of the present disclosure. Furthermore, the memory cells112and114are shown to have a cubic shape for simplicity purposes only and embodiments are not limited thereto.

The memory cells112ccan include high endurance 3D (“HE”) memory cells in which two adjacent HE memory cells are connected to a common source/select line. The memory cell112bcan be advantageous for high-bandwidth computing operations because the common SL can be used to increase performance. The memory cell114bcan include a 2-bit 3D memory cell that can be used for mass data storage before computing because the 2 bits per cell can increase density. In this disclosure, the memory cells112band114binclude ferroelectric memory cells, but embodiments are not limited thereto, and any type of 3D memory cell can be used.

The memory device100B includes a 4×2 structure on both of the memory banks112aand114a. There are 4 rows and 2 columns of memory arrays112bin the memory bank112a, and 4 rows and 2 columns of memory arrays114bin memory bank114a. However, embodiments are not limited thereto, and the memory device100B can include any number of rows and columns of memory arrays112band114b.

FIG.2Aillustrates a cross-sectional view of an example memory structure200of a number of the disclosed HE memory cells (e.g.,102c,112cofFIGS.1A-B), in accordance with some embodiments.

The memory structure200includes a pair of gate electrodes (or gate stacks)202, a pair of memory layers203, and a pair of semiconductor channels210. Each of the gate electrodes202is disposed on one of the sides of the memory structure200; each of the memory layers203is disposed on one of the sides of the memory structure200; and each of the semiconductor channels210is disposed on one of the sides of the memory structure200, as illustrated inFIG.2A. Further, the memory structure200includes first and second bit lines (BL)204and208and common select/source line (SL)206interposed between (e.g., coupled to) such pairs of gate electrodes202, memory layers203, and semiconductor channels210. The BLs204and208and SL206can be electrically isolated from one another by an isolation region212. Each of the gate electrode202, memory layers203, semiconductor channels210, BL204, SL206, BL208is formed as an upright structure that extends along a vertical direction, which will be discussed in further detail below.

In some embodiments, a first portion of one of the semiconductor channels210, a first portion of one of the memory layers203, and a first portion of one of the gate electrodes202can at least partially form an HE memory cell200a; and a second portion of one of the semiconductor channels210, a second portion of one of the memory layers203, and a second portion of one of the gate electrodes202can at least partially form an HE memory cell200b, as illustrated inFIG.2A. Although a certain number of structures are shown for simplicity and clarity, and embodiments are not limited thereto. Furthermore, the shapes and sizes of the structures are not necessarily drawn to scale. Although this disclosure includes a detailed description of a ferroelectric transistor for the HE memory cell, embodiments are not limited thereto, and any non-volatile 3D memory is within the scope of disclosure.

To operate the HE memory cells200aand200b, the semiconductor channel210includes a first source/drain (S/D) region coupled to the first BL204, a second S/D region coupled to the common SL206, and a third S/D region coupled to the second BL208. The HE memory cell200acan include the first and second S/D regions of the semiconductor channel210, and the HE memory cell200bcan include the second and third S/D regions of the semiconductor channel210. Accordingly, the HE memory cells200aand200bcan share the second S/D region which is connected to the common SL206. During operation, a conductive channel can be formed in the semiconductor channel210between the first and second S/D regions, and another conductive channel can be formed in the semiconductor channel210between the second and third S/D.

The gate electrode202can be connected or also be part of a word line (WL). The memory layer203can be formed of ferroelectric material, and dipoles are dispersed throughout the memory layer203. A memory device includes such a ferroelectric material serving as its memory layer is sometimes be referred to as a ferroelectric memory device, which will be discussed in further detail below.

In general, a ferroelectric memory device (sometimes referred to as a “ferroelectric random access memory (FeRAM)” device or a ferroelectric field effect transistor (FeFET)) contains a ferroelectric material to store information. The ferroelectric material acts as the memory material of the memory device. The dipole moment of the ferroelectric material is programmed in two different orientations (e.g., “up” or “down” polarization positions based on oxygen atom position in the crystal lattice) depending on the polarity of the applied electric field to the ferroelectric material to store information in the ferroelectric material. The different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment of the ferroelectric material. For example, the orientation of the dipole moment can be detected by measuring electrical current passing through a semiconductor channel provided adjacent to the ferroelectric material. Although the following discussed embodiments of the disclosed 3D memory device are directed to a ferroelectric memory device, it should be appreciated that some of the embodiments may be used in any of various other types of 3D non-volatile memory devices (e.g., magnetoresistive random access memory (MRAM) devices, phase-change random access memory (PCRAM) devices, etc.), while remaining within the scope of the present disclosure.

A ferroelectric memory device (e.g., FeFET) can encode its datum in its threshold voltage. When the dipole moment is programmed to have an “up” polarization position, the threshold voltage of the ferroelectric memory device has a threshold voltage that is raised to a high threshold voltage (HVT) state (e.g., logic 1). When the dipole moment is programmed to have a “down” polarization position, the threshold voltage of the ferroelectric memory device has a threshold voltage that is lowered to a low threshold voltage (LVT) state (e.g., logic 0).

The memory cell200acan be programmed to have the LVT state by setting the word line (connected to the gate electrode202) to a program voltage Vpgm, the first BL204to about 0V, and the common SL206to about 0V. The memory cell200acan be programmed to have the HVT state (or erased) by setting the word line to the −Vpgm/2, the first BL204to Vpgm/2, and the common SL to about 0V. Similarly, the memory cell200bcan be programmed to have the LVT state by setting the word line to the program voltage Vpgm, the second BL208to about 0V, and the common SL206to about 0V. The memory cell200acan be programmed to have the HVT state (or erased) by setting the word line to the −Vpgm/2, the second BL208to the Vpgm/2, and the common SL to about 0V. When the memory cell200aor200bis in an LVT state, the memory cell200aor200bstores the logic 0, and when the memory cell200aor200bis in an HVT state, the memory cell200aor200bstores the logic 1.

The above-described (e.g., voltage) signals can be applied to the BL(s)/SL through respective interconnect structures. For example inFIG.2A, the memory structure200further includes an interconnect structure (e.g., electrically) coupled to the first BL204, hereinafter “bit line1(BL1).” The BL1can extend along a lateral direction (e.g., Y direction) perpendicular to a lengthwise direction of the gate electrodes202, memory layers203, and semiconductor channels210, as shown. The memory structure200further includes an interconnect structure (e.g., electrically) coupled to the common SL206and to the second BL208, hereinafter “source line1(SL1)” and “bit line2(BL2),” respectively. Similarly, the SL1and BL2can extend in parallel with the BL1.

FIG.2Billustrates a cross-sectional view of a memory structure260, in accordance with some embodiments. The memory structure260is similar to the memory structure200ofFIG.2Aexcept that the memory layer263(similar to the memory layer203) laterally surrounds the semiconductor channel270(similar to the semiconductor channel210), and the gate electrode262(similar to the gate electrode202) laterally surrounds the memory layer263. As such, in the configuration of memory structure200(FIG.2A), the BLs and common SL,204to208, are coupled to (e.g., used by) four HE memory cells, which include the HE memory cells200aand200band two other HE memory cells (not shown) formed by the others of the gate electrode202, memory layer203, and semiconductor channel210. By contrast, in the configuration of memory structure260(FIG.2B), the BLs and common SL,204to208, may not be coupled to (e.g., used by) HE memory cells other than200aand200b.

FIG.3Aillustrates a cross-sectional view of an example memory structure300of a number of the disclosed 2-bit memory cells (e.g.,104c,114cofFIGS.1A-B), in accordance with some embodiments.

The memory structure300includes a pair of gate electrodes (or gate stacks)302, a pair of memory layers303, a pair of semiconductor channels310on each side of the memory structure300. Each of the gate electrodes302is disposed on one of the sides of the memory structure300; each of the memory layers303is disposed on one of the sides of the memory structure300; and each of the semiconductor channels310is disposed on one of the sides of the memory structure300, as illustrated inFIG.3A. Further, the memory structure300includes BL304and SL306interposed between (e.g., coupled to) such pairs of gate electrodes302, memory layers303, and semiconductor channels310. The BL304and SL306can be electrically isolated from each other by an isolation region312. Each of the gate electrode302, memory layers303, semiconductor channels310, BL304, and SL306is formed as a upright structure that extends along a vertical direction, which will be discussed in further detail below.

In some embodiments, a first portion of one of the semiconductor channels310, a first portion of one of the memory layers303, and a first portion of one of the gate electrodes302can at least form a first 2-bit memory cells300a; and a second portion of one of the semiconductor channels310, a second portion of one of the memory layers303, and a second portion of one of the gate electrodes302can at least partially form a second 2-bit memory cell300b, as illustrated inFIG.3A. The semiconductor channel310can include a first S/D region310aand a second S/D region310b, where the first S/D region310ais coupled to the BL304and the second S/D region310bis coupled to the SL306. Although a certain number of structures are shown for simplicity and clarity, and embodiments are not limited thereto. Furthermore, the shapes and sizes of the structures are not necessarily drawn to scale. Although this disclosure includes a detailed description of a ferroelectric transistor for the 2-bit memory cell, embodiments are not limited thereto, and any non-volatile 3D memory is within the scope of disclosure. Furthermore, although the 2-bit memory cell300ais primarily described, similar descriptions apply to the 2-bit memory cell300b.

Dipoles are dispersed throughout the memory layer303. In particular, memory layer303includes a first set of dipoles314aat the second end of the memory layer303, and a second set of dipoles314bat the first end of the memory layer303. The first set of dipoles314ahas a first polarization. The second set of dipoles314bhas a second polarization where the second polarization is substantially opposite the first polarization. Each dipole314aand each dipole314bis correspondingly represented inFIG.3Aby an arrow. As used herein, the arrow head of the dipole represents a positively charged end of the dipole and the tail represents a negatively charged end of the dipole. Accordingly, each dipole314aand each dipole314bcorrespondingly represents separation of positive and negative charges, and vice-versa, within the memory layer303. For simplicity of illustration, two dipoles314aand two dipoles314bare shown inFIG.3A; as a practical matter, a great many dipoles present in the memory layer303and which have correspondingly the orientations of dipole314aor314b.

InFIG.3A, regarding a first dipole which has the positively charged end pointing upward and the negatively charged end pointing downward, the following is assumed: the first dipole represents a first polarization state; the first dipole, e.g., dipole314a, is shown as an arrow whose head is pointing upward and whose tail is pointing downward; and the first dipole represents a logic 0. Also inFIG.3A, regarding a second dipole which has the negatively charged end pointing upward and the positively charged end pointing downward, the following is assumed: the second dipole represents a second polarization state; the second dipole, e.g., dipole314b, is shown as an arrow whose tail is pointing upward and whose head is pointing downward; and the second dipole represents a logic 1. Accordingly, inFIG.3A, relative to the X-direction, the polarization of the memory layer303is asymmetric. For example, the polarization of the memory layer303is asymmetric because the first end of the memory layer303(which is proximal to the first S/D region310a) has the second polarization and the second end of the memory layer303(which is proximal to the second S/D region310b) has the first polarization.

In one or more embodiments, an invertible region316extends through the semiconductor channel310between the first S/D region310aand the second S/D region310b. In some embodiments, the semiconductor substrate has N-type doping such that the charge carriers are electrons (−) and 2-bit memory cell300ais an N-type FeFET. In some embodiments, the N-type 2-bit memory cell300ais described as an N-type Metal Oxide Semiconductor FET (MOSFET) which further includes a ferroelectric layer (e.g., memory layer303) inserted between the gate electrode (e.g., gate electrode302) and the invertible region (e.g., invertible region316). In some embodiments, the semiconductor substrate has P-type doping such that the charge carriers are holes (+) and 2-bit memory cell300ais a P-type FeFET. In some embodiments, the 2-bit memory cell300aincludes a metal ferroelectric insulator semiconductor (MFIS), a single cell transistor capable of holding an electrical field polarization to retain one or more steady states in the absence of any electrical bias or the like.

If memory layer303were not present, and in the absence of a voltage on gate electrode302, invertible region316would represent a depletion region that does not support the flow of charge carriers. If memory layer303was not present, in the presence of a sufficient voltage on gate electrode302, i.e., a voltage greater than the threshold voltage, Vt, invertible region316would be inverted and would support the flow of charge carriers and so would represent a channel extending from the first S/D region310ato the second S/D region310b.

If both overlying portions of the memory layer303have the first polarization state, and in the absence of voltages correspondingly on the gate electrode302, the first S/D region310aand the second S/D region310b, then the corresponding portions of the invertible region316correspondingly are depletion regions that do not support the flow of charge carriers. However, if both overlying portions of the memory layer303have the second polarization state, and in the absence of voltages correspondingly on the gate electrode302, the first S/D region310aand the second S/D region310b, then the corresponding portions of invertible region316do support the flow of charge carriers.

InFIG.3A, a first portion of invertible region316is proximal to the first end of the memory layer303and to first S/D region310a, and a second portion of invertible region316is proximal to the second end of the memory layer303and to the second S/D region310b. InFIG.3A, a channel band barrier (CBB) portion318ais different than CBB portion318bfor the second portion of the invertible region316. In some embodiments, the CBB represents the bottom edge of the depletion region within the invertible region316, wherein the bottom edge of the depletion region is distal from the memory layer303and the top edge of the depletion region is proximal to the memory layer303.

In one or more embodiments, the 2-bit memory cell300ais configured to store one of four possible 2-bit data states, namely (0,1), (1,0), (1,1) or (0,0). In some embodiments, a bit represented by the polarization of the second end of the memory layer303proximal to the second S/D region310bis referred to as the first bit or bit zero (b0) of the 2-bit memory structure which 2-bit memory cell300arepresents, and a bit represented by the polarization of the first end of the memory layer303proximal to the first S/D region310ais referred to as the second bit or bit one (b1) of the 2-bit memory cell300a. Accordingly, the two bits are representable as (b1,b0), where (b1,b0) is one of (0,1), (1,0), (1,1) or (0,0).

Relative to the X-direction, gate electrode302is shown between first and second S/D regions310aand310b. In some embodiments, the gate electrode302and the memory layer303partially abuts first S/D region310aand/or second S/D region310b. In some embodiments, the gate electrode302and the memory layer303cover substantially all of first S/D region310aand/or the second S/D region310bon one side in the Y-direction. In some embodiments, the first S/D region310ahas a first doping type and the second S/D region310bhas a second doping type that is opposite to the first doping type. In some embodiments, while having the same doping type, the first S/D region310ahas a different doping concentration than the second S/D region310b. For example, in some embodiments, the first S/D region310ahas a lower doping concentration than second S/D region310b. In some embodiments, the lower doping concentration of the first and second S/D regions310aand310bmitigates gate induced drain leakage (GIDL) current in FeFETs. In some embodiments, the semiconductor channel310is an opposite dopant type relative to a dopant type of the first and second S/D regions310aand310b. For example, if the first and second S/D regions310aand310bare n-type, then semiconductor channel310is p-type, and vice-versa.

In general, subjecting memory layer303to an electric field of sufficient magnitude orients dipoles in the memory layer303into a corresponding one of two possible polarization states (bistable states), e.g., dipole314aand dipole314b. The corresponding field-induced polarization state remains after the field is removed, i.e., each of the bistable polarization states is non-volatile. In terms of the FeFET as a whole, the two possible polarization states of the layer of ferroelectric material manifest as two corresponding possible states of the FeFET, namely an erased state and a programmed state.

InFIG.3A, bit b1of the 2-bits of data stored by the 2-bit memory cell300bis shown as being a logic 1 and so is represented by the first end of memory layer303(which is proximal to the S/D region310a) having the second polarization as represented by dipoles314b; and bit b0of the 2-bits of data stored by 2-bit memory cell300ais shown as being a logic 0 and so is represented by the second end of memory layer303(which, again, is proximal to the S/D region310b) having the first polarization as represented by dipoles314a.

In some embodiments, setting a bit to a logic 1, i.e., programming the bit, in 2-bit memory cell300ais performed by applying an appropriate value of a gate voltage (Vg) and applying a corresponding appropriate value of a source/drain voltage (Vs/d) to the selected one of the first or second S/D region310aor310bthat is to be set to a logic 1. For example, Vs/d is applied to the first S/D region310a(through BL304) and/or the second S/D region310b(through SL306) based upon which one of the four 2-bit data states is to be stored in the 2-bit memory cell300a, where the 2-bits (b1,b0) have the state (0,1), (1,0), (1,1) or (0,0). In some embodiments, both of bits b1and b0are set to logic 1, i.e., programmed, in the 2-bit memory cell300ausing Vg of about 3V and using Vs/d of about 0V for each of first S/D region310aand second S/D region310b. In some embodiments, to program one of bits b1and b0, e.g., bit b0, Vg is set to about 3V, the second S/D region310bis about 0V, while the first S/D region310ais left floating or receives about 1V.

In some embodiments, both of bits b1and b0are set to logic 0, i.e., erased, in 2-bit memory cell300ausing Vg of about −2V and using Vs/d of about 1V for each of the first S/D region310aand the second S/D region310b. In some embodiments, to erase one of bits b1and b0, e.g., bit b0, Vg is set to of about −2V, second S/D region310bis about 1V, while first S/D region310ais left floating or receives of about 0V.

In general, to change the polarization state of a portion of a ferroelectric layer, the portion of the ferroelectric layer is subjected to an electric field of sufficient magnitude to orient the dipoles of the portion of the ferroelectric layer which are in the path of the electric field according to the direction of the electric field. In some embodiments, an electric field of sufficient magnitude to orient the dipoles of the ferroelectric layer is referred to as a coercive field (Ec). In some embodiments, and in the context of the 2-bit memory cell300a, a voltage difference between Vg and Vs/d which is of sufficient magnitude to induce Ec is referred to as a coercive voltage (Vc). In some embodiments, Vc is at least about 3V.

For example, to manipulate the polarization of dipoles314aso that bit b0represents a logic 1, a combination of voltage values for Vg and Vs/d (applied to the second S/D region310b) (Vsd_310b) is applied wherein the resulting difference is equal to or greater than Vc. In some embodiments, to change the polarization of dipoles314aso as to represent a logic 0, a combination of Vg of about −2V and Vsd_310bof about 1V is used. In a circumstance in which second S/D region310bhas a higher positive potential than gate electrode302, (e.g., Vg of about −2V and Vsd_310bof about 1V), dipoles314abecome orientated with the negative ends proximal to second S/D region310band the positive ends proximal to gate electrode302, resulting in the negative ends being proximal to invertible region316. To avoid altering the state of bit b1which is represented by the polarization of dipoles314b, e.g., while the polarization of dipoles314ais being manipulated, a voltage value of Vs/d that is applied to first S/D region310a(Vsd_310a) is selected so that a combination of voltage values for Vg and Vsd_310aresults in a voltage difference that is less than Vc and thus dipoles314bat first S/D region310aare not altered from their previous state. In some embodiments, to avoid altering the state of bit b1while the polarization of dipoles314ais being manipulated (in part by setting Vg of about −2V), first S/D region310ais left floating. In some embodiments, to avoid altering the state of bit b1while the polarization of dipoles314ais being manipulated (in part by setting Vg of about −2V), Vsd_310aof about 0V. In some embodiments, to avoid altering the state of bit b1while the polarization of dipoles314ais being manipulated (in part by setting Vg of about −2V), Vsd_310aof VSS.

The polarization of the second end of memory layer303, which is proximal to second S/D region310b, thickens the depletion region proximal to second S/D region310brelative to the Y-direction, and correspondingly raises/increases CBB portion318bproximal to second S/D region310b. This raising/increasing of CBB portion318bis discussed in more detail below.

FIGS.3B-3Dillustrate waveforms that illustrate a read operation for the 2-bit memory cell300a, in accordance with some embodiments. During phase1(see alsoFIG.3C), the voltages are configured to read bit b1of the 2-bit data stored by the 2-bit memory cell300a, where bit b1is stored at the first end of memory layer303which is proximal to the first S/D region310a. A bias voltage (Vbias) is applied to the gate electrode302, a read voltage (Vread) is applied to the second S/D region310b, and a non-disturbing voltage (Vdnd) is applied to the first S/D region310a. During phase2, the voltages are configured to read bit b0, where bit b0is stored at the second end of memory layer303which is proximal to the second S/D region310b. During phase2, bit b0is read, wherein bit b0is stored at the second end of memory layer303, the second end being proximal to second S/D region310b. During phase2, Vg of Vbias is applied to gate electrode302, Vdnd is applied to the second S/D region310band Vread is applied to the first S/D region310a. AlthoughFIGS.3B-3Dare described with an example of bit b1having the logic 1 and bit b0having the logic 0, embodiments are not limited thereto, and the bit b1can have logic 1 or logic 0, and the bit b0can have logic 1 or logic 0.

FIGS.3B-3Dillustrate waveforms319,320and328that illustrate the operation of the 2-bit memory cell300a, in accordance with some embodiments. The waveforms319,320and328include channel band barrier portions318aand318bunder correspondingly different conditions, in accordance with some embodiments.

InFIG.3B, waveform319represents channel band barrier (CBB) portions318aand318bfor the 2-bit memory cell300aduring quiescent conditions. In some embodiments, during quiescent conditions for the 2-bit memory cell300a, each of gate electrode302, first S/D region310aand second S/D region310bis left floating.

In waveform319, CBB portion318bhas a first quiescent CBB value which corresponds to the first polarization state and so corresponds to a logic 0. Hereinafter, the first quiescent CBB value is referred to as QCBB0. In waveform319, CBB portion318ahas a second quiescent CBB value which corresponds to the second polarization state and so corresponds to a logic 1. Hereinafter, the second quiescent CBB value is referred to as QCBB1.

InFIG.3C, waveform320represents CBB portions318aand318bduring phase1of the two-phase read operation. During phase1, bit b1is read, wherein bit b1is stored at the first end of memory layer303, the first end being proximal to first S/D region310a. During phase1, Vg of Vbias is applied to the gate electrode302, Vdnd is applied to the first S/D region310aand Vread is applied to the second S/D region310b.

InFIG.3D, waveform328represents CBB portions318aand318bduring phase2of the two-phase read operation. During phase2, bit b0is read, wherein bit b0is stored at the second end of memory layer303, the second end being proximal to second S/D region310b. During phase2, Vg of Vbias is applied to gate electrode302, Vdnd is applied to the second S/D region310band Vread is applied to the first S/D region310a.

RegardingFIGS.3C-3D, in effect, relative to the side of the 2-bit memory cell300afor which the stored bit value is being read (read-side), Vread is applied to the opposite side of the 2-bit memory cell300a(non-read-side), which might seem counterintuitive at first. However, the values for Vread and Vg of Vbias are configured to ensure that the portion of invertible region316on the non-read-side of the 2-bit memory cell300ais manipulated to support temporarily a flow of charge carriers. In some embodiments, the temporary duration of the support corresponds to the period of time in which the values for Vread and Vg of Vbias are applied which ensure that the portion of invertible region316on the non-read-side of the 2-bit memory cell300asupports a flow of charge carriers. By manipulating the non-read-side of the 2-bit memory cell300ato support temporarily a flow of charge carriers, whether or not a current flows between S/D regions310aand310bis then controlled by whether or not the portion of invertible region316on the read-side of the 2-bit memory cell300asupports the flow of charge carriers.

Recalling the particular circumstances in which the second end of memory layer303has the first polarization representing a logic 0 value, the portion of invertible region316under the second end of memory layer303has CBB portion318b, and that CBB portion318baccordingly has QCBB0, a value for Vg of Vbias is selected to be less than Vt for the particular circumstances. However, for the particular circumstances, the combination of Vg of Vbias and Vread is greater than Vt. Accordingly, in some embodiments, because Vg of Vbias is less than Vt for the particular circumstances, Vg of Vbias is described as sub-threshold voltage.

In general, assuming the non-read-side is being manipulated to support temporarily a flow of charge carriers, if the read-side of the 2-bit memory cell300astores a logic 0 because the read-side of memory layer303is in the first polarization state, then the portion of invertible region316on the read-side of the 2-bit memory cell300adoes not support the flow of charge carriers, resulting in substantially no current flowing between S/D regions310aand310b, which is interpreted as the read-side bit of the 2-bit memory cell300astoring a logic 0.

Also, in general, assuming the non-read-side is being manipulated to support temporarily a flow of charge carriers, if the read-side of the 2-bit memory cell300astores a logic 1 because the read-side of memory layer303is in the second polarization state, then the portion of invertible region316on the read-side of the 2-bit memory cell300adoes support the flow of charge carriers, resulting in a significant flow of current between S/D regions310aand310b, which is interpreted as the read-side of the 2-bit memory cell300astoring a logic 1. In some embodiments, a significant flow current is a current flow that would not be regarded as merely a leakage current.

RegardingFIG.3C, recalling that bit b1is logic 1 because the first end of memory layer303has the second polarization and that bit b0of logic 0 because the second end of memory layer303has the first polarization,FIG.3Cassumes that Vg having Vbias is being applied to gate electrode302, Vdnd of about 0V is being applied to first S/D region310a, and Vread of about −1V is being applied to second S/D region310b.

In the context ofFIG.3C, the voltage difference between Vg of Vbias and Vread (the latter being applied to second S/D region310b) in combination with the first polarization state of the second end of memory layer303is sufficient to overcome the first polarization at the second end of memory layer303and consequently is sufficient to draw charge carriers into the portion of invertible region316that is proximal to second S/D region310b, with a result that the portion of invertible region316which is proximal to first S/D region310asupports temporarily a flow of charge carriers. Because of the second polarization at the first end of memory layer303, the portion of invertible region316proximal to first S/D region310asupports the flow of charge carriers under quiescent conditions. Accordingly, the portion of invertible region316proximal to first S/D region310aalso supports the flow of charge carriers when Vg of Vbias is being applied to gate electrode302and Vdnd of about 0V is being applied to first S/D region310a. As a temporary result, both the portion of invertible region316proximal to first S/D region310aand the portion of invertible region316proximal to second S/D region310bsupport the flow of charge carriers, and consequently current flows from first S/D region310ato second S/D region310bas indicated by reference number330inFIG.3C, which is interpreted as the bit b1of the 2-bit memory cell300astoring a logic 1.

RegardingFIG.3D, recalling that bit b1has the logic 1 because the first end of memory layer303has the second polarization and that bit b0has logic 0 because the second end of memory layer303has the first polarization,FIG.3Dassumes that Vg of Vbias is being applied to the gate electrode302, Vread of about −1V is being applied to the first S/D region310a, and Vdnd of about 0V is being applied to the second S/D region310b.

In the context ofFIG.3D, because of the second polarization at the first end of memory layer303, the portion of invertible region316proximal to S/D region310asupports the flow of charge carriers under quiescent conditions. Accordingly, the portion of invertible region316proximal to S/D region310aalso supports the flow of charge carriers when Vg of Vbias is being applied to gate electrode302and Vread of about −1V is being applied to the first S/D region310a. The voltage difference between Vg and Vdnd (the latter being applied to the second S/D region310b) in combination with the second polarization state of the first end of memory layer303is not sufficient to overcome the first polarization at the second end of memory layer303and consequently is not sufficient to draw charge carriers into the portion of invertible region316that is proximal to second S/D region310b, with a result that the portion of invertible region316which is proximal to first S/D region310adoes not support a flow of charge carriers. As a further result, only the portion of invertible region316proximal to first S/D region310asupports the flow of charge carriers, and consequently no current flows from first S/D region310ato second S/D region310bas indicated by reference number329inFIG.3D, which is interpreted as the bit b0of the 2-bit memory cell300astoring a logic 0.

FIG.4illustrates a flow chart of an example process400of manufacturing a memory device, in accordance with some embodiments. For example, at least some of the operations (or steps) of the process400can be used to form a 3D memory device. It is noted that the process400is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the process400ofFIG.4, and that some other operations may only be briefly described herein. In some embodiments, operations of the process400may be associated with perspective and/or top views of an example 3D memory device at various fabrication stages as shown inFIGS.5A-5M, respectively, which will be discussed in further detail below.

In brief overview, the process400starts with operation402of providing a substrate including a first area and a second area. The process400continues to operation404of providing a stack of insulating layers and sacrificial layers over both the first and second areas. The process400continues to operation406of forming a memory layer extending through the stack. The process400continues to operation408of forming a semiconductor channel layer extending through the stack. The process400continues to operation410of cutting, in the first area, the semiconductor channel layer into a plurality of second semiconductor channels. The process400continues to operation412of cutting, in the second area, the semiconductor channel into a plurality of second semiconductor channels. The process400continues to operation414of forming, in the first area, a triplet of first conductive structures. The process400continues to operation416of forming, in the second area, a pair of second conductive structures.

FIGS.5A-5Meach illustrates a perspective view of an example 3D memory device500during various fabrication stages, in accordance with some embodiments. Such a 3D memory device may include at least a first memory structure (device) that has one or more HE memory cells, and at least a second memory structure (device) that has one or more 2-bit memory cells. For example,FIGS.5A-5Iapply to the fabrication of both the memory structures200(e.g.,FIG.2A) and300(e.g.,FIG.3A);FIGS.5J and5Lapply to the fabrication of the memory structure200; andFIGS.5K and5Mapply to the fabrication of the memory structure300.

Corresponding to operations402and404ofFIG.4,FIG.5Ais a perspective view of the 3D memory device500including a stack502formed over a semiconductor substrate501at one of the various stages of fabrication, in accordance with various embodiments.

The substrate501may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate501may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate501may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GainAs, GainP, and/or GainAsP; or combinations thereof. Other materials are within the scope of the present disclosure.

The stack502includes a number of insulating layers504and a number of sacrificial layers506alternately stacked on top of one another over the substrate501along a vertical direction (e.g., the Z direction). Although five insulating layers504and four sacrificial layers506are shown in the illustrated embodiment ofFIG.5A, it should be understood that the stack502can include any number of insulating layers and any number of sacrificial layers alternately disposed on top of one another, while remaining within the scope of the present disclosure. Further, although the stack502directly contacts the substrate501in the illustrated embodiment ofFIG.5A, it should be understood that the stack502is separated from the substrate501(as mentioned above). For example, a number of (planar and/or non-planar) transistors may be formed over the substrate501, and a number of metallization layers, each of which includes a number of contacts electrically connecting to those transistors, may be formed between the substrate501and the stack502. As used herein, the alternately stacked insulating layers504and sacrificial layers506refer to each of the sacrificial layers506being adjoined by two adjacent insulating layers504. The insulating layers504may have the same thickness thereamongst, or may have different thicknesses. The sacrificial layers506may have the same thickness thereamongst, or may have different thicknesses. In some embodiments, the stack502may begin with the insulating layer504(as shown inFIG.5A) or the sacrificial layer506.

The insulating layers504can include at least one insulating material. The insulating materials that can be employed for the insulating layer504include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are generally known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. Other materials are within the scope of the present disclosure. In one embodiment, the insulating layers504can be silicon oxide.

The sacrificial layers506may include an insulating material, a semiconductor material, or a conductive material. The material of the sacrificial layers506is a sacrificial material that can be subsequently removed selective to the material of the insulating layers504. Non-limiting examples of the sacrificial layers506include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial layers506can be spacer material layers that include silicon nitride or a semiconductor material including at least one of silicon or germanium. Other materials are within the scope of the present disclosure.

The stack502can be formed by alternately depositing the respective materials of the insulating layers504and sacrificial layers506over the substrate501. In some embodiments, one of the insulating layers504can be deposited, for example, by chemical vapor deposition (CVD), followed by depositing, for example, using CVD or atomic layer deposition (ALD), one of the sacrificial layers506. Other methods of forming the stack502are within the scope of the present disclosure.

Although the stack502is formed as being in contact with the substrate501, which is implemented as a semiconductor wafer, in the illustrated embodiment ofFIG.5A(and the following figures), it should be appreciated that a number of layers can be formed between such a semiconductor substrate501and the stack502. For example, a number of metallization layers, each of which includes a number of interconnect structure therein, can be disposed between the substrate501and the stack502, while remaining within the scope of present disclosure. In some other embodiments where the stack502is in direct contact with the substrate501, such a substrate501, formed of a dielectric material (e.g., silicon nitride), may serve an etch stop layer for forming a number of conductive structures (e.g., SLs, BLs) extending through the stack502.

Referring still toFIG.5A, the substrate501can include at least a first area501aand a second area501b. In some embodiments, in the first area501a, a first memory structure (device) having a number of HE memory cells are formed; and in the second area501b, a second memory structure (device) having a number of 2-bit memory cells are formed. As mentioned above, some of the features/components of the memory device500can be concurrently formed in the first and second areas (for the first and second memory structures, respectively), and thus, such features are together discussed up toFIG.5IBeyondFIG.5I,FIGS.5J and5Lare directed to discussion of the first memory structure in the first area501a; andFIGS.5K and5Mare directed to discussion of the second memory structure in the second area501b.

Further, in the example ofFIG.5A, the areas501aand501bare disposed next to each other along the Y-direction, which is similar to the example ofFIG.1A. Thus, it should be understood that such two areas may be disposed next to each other along the X-direction, while remaining within the scope of present disclosure.

FIG.5Bis a perspective view of the memory device500after a plurality of first trenches508extending in the X-direction have been formed through the stack502by etching the stack502in the z-direction at one of the various stages of fabrication, in accordance with various embodiments. A plurality of first trenches508are formed through the stack in the first direction (e.g., the X-direction). The first trenches508have been formed through the stack502up to the substrate501by etching the stack502in the Z-direction. The etching process for forming the plurality of first trenches508may include a plasma etching process, which can have a certain amount of anisotropic characteristic. For example, the first trenches508may be formed, for example, by depositing a photoresist or other masking layer on a top surface of the memory device500, i.e., the top surface of the topmost insulating layer504of the stack502, and a pattern corresponding to the first trenches508defined in the masking layer (e.g., via photolithography, e-beam lithography, or any other suitable lithographic process). In other embodiments, a hard mask may be used.

Subsequently, the stack508may be etched using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof to form the first trenches508. As a non-limiting example, a source power of about 10 Watts to about 3,000 Watts, a bias power of about 0 watts to about 3,000 watts, a pressure of about 1 millitorr to about 5 torr, and an etch gas flow of about 0 sccm to about 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated. As shown inFIG.5B, the etch used to form the plurality of first trenches508etches through each of the sacrificial layers506and insulating layers504of the stack502such that each of the plurality of first trenches508extend form the topmost insulating layer504through the bottommost insulating layer504to the substrate501.

FIG.5Cis a top, perspective view of the memory device500after partially etching exposed surfaces of the sacrificial layers506that are located in the first trenches508at one of the various stages of fabrication, in accordance with some embodiments. For example, the exposed surfaces extend in the X-direction and etching the exposed surfaces of the sacrificial layers506reduces a width of the insulating layers504on either side of the sacrificial layers506in the Y-direction. In some embodiments, the sacrificial layers506may be etched using a wet etch process (e.g., hydrofluoric etch, buffered hydrofluoric acid). In other embodiments, the exposed surfaces of the sacrificial layers506may be partially etched using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof. As a non-limiting example, a source power of about 10 Watts to about 3,000 Watts, a bias power of about 0 watts to about 3,000 watts, a pressure of about 1 millitorr to about 5 torr, and an etch gas flow of about 0 sccm to about 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated. Partially etching the sacrificial layers in the Y-direction reduces a width of the sacrificial layers506relative to the insulating layers504disposed in the stack502.

FIG.5Dis a perspective view of the memory device500after forming the gate layers (e.g., gate electrode, gate structure)510located in the first trenches508at one of the various stages of fabrication, in accordance with some embodiments. In various embodiments, an adhesive layer is deposited in the cavities formed by the etched sacrificial layers506. The adhesive layer may include a material that has good adhesion with each of the insulating layers504, the sacrificial layers506, and the gate layer510, for example, Ti, Cr, etc. The adhesive layers may be deposited using any suitable method including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In some embodiments, the adhesive layer may have a thickness in a range of about 0.1 nm to about 5 nm, inclusive.

In various embodiments, the gate layers510are formed by filling a gate dielectric and/or gate metal in the cavities over the adhesive layer, such that the gate layers510inherit the dimensions and profiles of the cavities. In various embodiments, the gate layers510may be formed from a high-k dielectric material. Although, each of gate layer510shown inFIG.5Dis shown as a single layer, in other embodiments, the gate layer510can be formed as a multi-layer stack (e.g., including a gate dielectric layer and a gate metal layer), while remaining within the scope of the present disclosure. The gate layers510may be formed of different high-k dielectric materials or a similar high-k dielectric material. Example high-k dielectric materials include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate layers510can be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.

The gate metal may include a stack of multiple metal materials. For example, the gate metal may be a p-type work function layer, an n-type work function layer, multi-layers thereof, or combinations thereof. The work function layer may also be referred to as a work function metal. Example p-type work function metals may include TIN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vtis achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.

Formation of the gate layers510in the cavities may cause radial edges of the gate layers510in the Y-direction to protrude radially outwards of the cavities, i.e., radially outwards of the corresponding edges of the insulating layers504, and/or the material forming the gate layers510may also be deposited on exposed radial surfaces of the insulating layers504that face the first trenches508and/or the substrate501. The protruding radial edges of the gate layers510and/or the extra deposited gate material are etched, for example, using a selective wet etching or dry etching process (e.g., RIE, DRIE, etc.) until any gate material deposited on the radial surfaces of the insulating layers504and/or the substrate501, and radial edges of the gate layers510facing the first trenches508are substantially axially aligned with corresponding radial edges of the insulating layers504.

Corresponding to operations406and408,FIG.5Eis a perspective view of the memory device500after formation of the memory layer (or memory layer)512, a semiconductor channel layer514, and an insulation layer516. The memory layer512may include a ferroelectric material, for example, lead zirconate titanate (PZT), PbZr/TiO3, BaTiO3, PbTiO2, etc. The memory layer512may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof. A conformal coating may be deposited such that the memory layer512is continuous on the walls of the first trenches508.

The semiconductor channel layer514is formed on a radially inner surface of the memory layer512in the Y-direction. In some embodiments, the semiconductor channel layer514may be formed from a semiconductor material, for example, Si (e.g., polysilicon or amorphous silicon), Ge, SiGe, silicon carbide (SiC), etc. The semiconductor channel layer514may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof. A conformal coating may be deposited such that the semiconductor channel layer514is continuous on the radially inner surface of the memory layer512.

Each of the first trenches508is then filled with an insulating material (e.g., SiO, SiN, SiON, SiCN, SiC, SiOC, SiOCN, the like, or combinations thereof) so as to form the insulation layer516. In some embodiments, the insulation layer516may be formed from the same material as the plurality of insulating layers504(e.g., SiO2). The insulation layer516may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof, a high aspect ratio process (HARP), another applicable process, or combinations thereof.

FIG.5Fis a perspective view of the memory device500after forming a plurality of second trenches518at one of the various stages of fabrication, in accordance with some embodiments. As with the first trenches508, the second trenches518are formed by etching the stack502in the Z-direction up to the substrate501.

The plurality of second trenches518may be formed using the same process used to form the plurality of first trenches508. For example, the second trenches518may be formed, for example, by depositing a photoresist or other masking layer on a top surface of the memory device500, i.e., the top surface of the topmost insulating layer504of the stack502, and a pattern corresponding to the second trenches518defined in the masking layer (e.g., via photolithography, e-beam lithography, or any other suitable lithographic process). In other embodiments, a hard mask may be used. Subsequently, the second trenches518may be etched using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof to form the second trenches518. As a non-limiting example, a source power of about 10 Watts to about 3,000 Watts, a bias power of about 0 watts to about 3,000 watts, a pressure of about 1 millitorr to about 5 torr, and an etch gas flow of about 0 sccm to about 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated. As shown inFIG.5F, the etch used to form the plurality of second trenches518etches through each of the sacrificial layers506and insulating layers504of the stack502such that each of the plurality of second trenches518extend form the topmost insulating layer504through the bottommost insulating layer504to the substrate501.

FIG.5Gis a perspective view of the memory device500after forming a second set of gate layers510adjacent to the previously formed gate layers510at one of the various stages of fabrication, in accordance with some embodiments. The remaining portions of the sacrificial layers506may be etched using the same process as described with respect toFIG.5C, by etching exposed portions of the sacrificial layers506in the second set of trenches518until the sacrificial layers506are completely removed. This leaves cavities between adjacent layers of insulating layers504, and adjacent to the gate layers. Adhesive layer is deposited on walls of the newly formed cavities.

FIG.5His a perspective view of the memory device500after a gate layer material is deposited in the cavities so as to fill the cavities to form a second set of gate layers510adjacent to the previously formed gate layers510at one of the various stages of fabrication, in accordance with some embodiments. The two gate layers abut each other with the adhesive layer disposed therebetween (collectively called gate layer510). The second set of gate layers510may be etched back such that radial edges of the second set of gate layers510facing the second trenches518are substantially axially aligned with corresponding radial edges of the insulating layers504.

FIG.5Iis a perspective view of the memory device500after depositing additional memory layers512, semiconductor channel layers514, and insulation layers516at one of the various stages of fabrication, in accordance with some embodiments. The additional memory layers512, semiconductor channel layers514, and insulation layers516can be deposited in the same or similar way as described with respect toFIG.5E. Accordingly, the memory device500includes 5 segments520of memory cells.

FIGS.5J and5Lare described with respect to the fabrication of a first memory device portion500ain the first area501aof the substrate501, andFIGS.5K and5Mare described with respect to the fabrication of a second memory device portion500bin the second area501bof the substrate501. The first memory device portion500aand the second memory device portion500bcan be two different portions of the memory device500. Memory structures in the first memory device portion500aare similar to the memory structures200that includes a number of HE memory cells, and memory structures in the second memory device portion500bare similar to the memory structures300that includes a number of 2-bit memory cells. Accordingly, both the HE memory cells (e.g., memory device102c,112cand memory structure200) and the 2-bit memory cells (e.g., memory device104c,114cand memory structure300) can be formed on the same semiconductor wafer or die.

Referring to operation410,FIG.5Jis a perspective view of the first memory device portion500aafter the semiconductor channel layer514has been cut into a plurality of semiconductor channels (or semiconductor channel layers)524at one of the various stages of fabrication, in accordance with some embodiments. Referring to operation412,FIG.5Kis a perspective view of the second memory device portion500bafter the semiconductor channel layer514has been cut into a plurality of semiconductor channels (or semiconductor channel layers)534at one of the various stages of fabrication, in accordance with some embodiments.

To form a plurality of memory structures200and a plurality of memory structures300, a plurality of cavities are etched through the semiconductor channel layer514and the insulation layer516at predetermined space intervals. The space intervals for the memory structures200may be different from the space intervals for the memory structures300. The cavities may be etched using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof to form the cavities. As a non-limiting example, a source power of about 10 Watts to about 3,000 Watts, a bias power of about 0 watts to about 3,000 watts, a pressure of about 1 millitorr to about 5 torr, and an etch gas flow of about 0 sccm to about 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated.

The etched cavities are then filled with an insulating material (e.g., SiO2) to form the isolation structures522. The insulating material may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof, a high aspect ratio process (HARP), another applicable process, or combinations thereof. Etching the semiconductor channel layer514and the insulation layer516to form the isolation structures522separates the semiconductor channel layer514into portions such that a semiconductor channel524is included in each active device structure526(or memory structure200) and a semiconductor channel534is included in each active device structure536(or memory structure300).

Thus, as shown in each ofFIG.5J, each active device structure526includes an inner spacer528formed from a portion of the insulation layer516extending between adjacent isolation structures522in the X-direction. The semiconductor channel524is disposed on radially outer surfaces of the inner spacer528in the Y-direction, and the memory layer512is disposed on radially outer surfaces of the semiconductor channel524in the Y-direction. One or more gate layers510are in contact with radially outer surfaces of the memory layer512, as previously described herein. As shown in eachFIG.5K, each active device structure536includes an inner spacer538formed from a portion of the insulation layer516extending between adjacent isolation structures522in the X-direction. The semiconductor channel534is disposed on radially outer surfaces of the inner spacer538in the Y-direction, and the memory layer512is disposed on radially outer surfaces of the semiconductor channel534in the Y-direction. One or more gate layers510are in contact with radially outer surfaces of the memory layer512, as previously described herein.

One or more gate layers510are in contact with radially outer surfaces of the memory layer512, as previously described herein. Each memory layer512and each gate layer510are continuous such that each memory layer512and at least one gate layer510(e.g., the bottommost gate layer510that is most proximate to the substrate501) are shared by each active device structure526in a particular row of active device structures526and shared by each active device structure536in a particular row of active device structures536.

In some embodiments, a length of each of the active device structure536(for the memory structure300) can be shorter in the X-direction than a length of each active structure526(for the memory structure200). However, embodiments are not limited thereto, and depending on the embodiments, the length of each of the active structure536may be the same length or longer in the X-direction than the length of each active structure526.

Referring to operations414and416,FIGS.5L and5Mare perspective views of the first memory device portion500aand second memory device portion500bafter a plurality of conductive structures have been formed at one of the various stages of fabrication, in accordance with some embodiments.

The conductive structures for the first memory device portion500a,537A,537B,357C, may be formed by first etching through axial ends and a middle portion of each of the inner spacers528to the substrate501. The conductive structures537A to537C may be example implementations of the BL208, SL206, and BL204discussed with respect toFIG.2A, respectively. The conductive structures for the second memory device portion500b,539A and539B, may be formed by first etching through axial ends of each the inner spacers538to the substrate501. The conductive structures539A to539B may be example implementations of the BL304and SL306discussed with respect toFIG.3A, respectively.

The axial ends of the inner spacers528and538, and the middle portion of the inner spacer528, may be concurrently or respectively etched using a plasma etching process. For example, the axial ends and the middle portion of the inner spacers528may be first etched, followed by etching the axial ends of the inner spacers538. The plasma etching process includes radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE, or the like. In the plasms etching process, gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof. As a non-limiting example, a source power of about 10 Watts to 3,000 Watts, a bias power of about 0 watts to about 3,000 watts, a pressure of about 1 millitorr to about 5 torr, and an etch gas flow of about 0 sccm to about 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated.

Next, the conductive structures537A-C for the first memory device portions500aand conductive structures539A-B for the second memory device portion500bmay be formed, for example, using an epitaxial layer growth process. As shown inFIGS.5L and5M, the conductive structures537A and537C are located on opposite axial ends of the inner spacers528, with the conductive structure537B disposed in the middle portion of the inner spacer528; and the conductive structures539A and539B are located on opposite axial ends of the inner spacers538, with no conductive structure disposed therebetween.

In some embodiments, a control deposition step may be performed for forming the conductive structures,537A-C and539A-B, such that the deposition step is stopped when a height of the conductive structures in the Z-direction are about equal to a height of the stack502. A CMP operation may be performed after the deposition step so as to ensure a top surface of each of the topmost insulating layer504, the memory layer512, the semiconductor channels524and534, the inner spacers528and538(FIGS.5J and5K), and the conductive structures,537A-C and539A-B lie in the same X-Y plane or are level with a top surface of the topmost insulating layer504.

In-situ doping (ISD) may be applied to form the conductive structures,537A-C and539A-B, thereby creating the junctions for each active memory device526and536. N-type and p-type FETs are formed by implanting different types of dopants to selected regions (e.g., the source and drain regions) of the active device structures526and536to form the junction(s). N-type devices can be formed by implanting arsenic (As) or phosphorous (P), and p-type devices can be formed by implanting boron (B).

Vias are formed over the conductive structures,537A-C and539A-B, respectively. To form the vias, an array of cavities may be formed in the interlayer dielectric (not shown) to the underlying conductive structures,537A-C and539A-B. The cavities may be formed, for example, using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof. As a non-limiting example, a source power of about 10 Watts to about 3,000 Watts, a bias power of about 0 watts to about 3,000 watts, a pressure of about 1 millitorr to about 5 torr, and an etch gas flow of about 0 sccm to about 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated.

The array of cavities are then filled with an electrically conducting material, for example, tungsten (W), copper (Cu), cobalt (Co). etc., or a high-k dielectric material, for example, hafnium oxide (HfO), tantalum nitride (TaN), etc. The electrically conducting material may be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof, a high aspect ratio process (HARP), another applicable process, or combinations thereof.

A plurality of interconnect (e.g., metal) structures may be formed as signal lines over the vias in one of the various stages of fabrication, in accordance with some embodiments. Referring toFIG.5L, a plurality of first signal lines (e.g., bit lines BL1_1, BL1_2, BL1_3, and BL1_4and common source/select lines SL1_1and SL1_2) are formed that each couple one of the conductive structures537A-C to one another in the second direction (e.g., the Y-direction). The bit lines BL1_1, BL1_2, BL1_3, and BL1_4are connected to a first bit line driver (not shown), and the common source/select lines SL1_1and SL1_2are connected to a first source/select line driver (not shown). Referring toFIG.5M, a plurality of second signal lines (e.g., bit lines BL2_1, BL2_2, BL2_3and source/select lines SL2_1, SL2_2, SL2_3) are formed that each couple one of the conductive structures539A-B to one another in the Y-direction. The bit lines BL2_1, BL2_2, BL2_3are connected to a second bit line driver (not shown), and the source/select lines SL2_1, SL2_2, SL2_3are connected to a second source/select line driver (not shown). Although a certain number of bit lines and source/select lines are shown, embodiments are not limited thereto, and any number of bit lines and source/select lines are within the disclosure.

The signal lines may be formed from a conducting material, for example, tungsten (W), copper (Cu), cobalt (Co), etc. The signal lines may also be formed using a dual damascene process, for example, after formation of the through vias before removing the spacer layer. While the memory device500is shown without the spacer layer, in some embodiments, the spacer layer may remain included in the final memory device500.

FIG.6Aillustrates a top view the first memory device portion500a, in accordance with some embodiments. Bit lines BL1_1, BL1_2, BL1_3, and BL1_4and the common source/select lines SL1_1and SL1_2are connected to a plurality of HE memory structures540a,540b,540c,540d,540e,540f,540g,540h,540i, and540j. Each of the HE memory structures ofFIG.6Ais similar or the same as the memory structure200and may be controlled and operated as described above with reference to the memory structure200.

The bit line BL1_1is connected to the first S/D region of each of the HE memory structures540a,540b,540c,540d, and540e. The common source SL1_1is connected to the second S/D region of each of the HE memory structures540a,540b,540c,540d, and540e. The bit line BL1_2is connected to the third S/D region of each of the HE memory structures540a,540b,540c,540d, and540e. The bit line BL1_3is connected to the first S/D region of each of the HE memory structures540f,540g,540h,540i, and540j. The common source SL1_2is connected to the second S/D region of each of the HE memory structures540f,540g,540h,540i, and540j. The bit line BL1_3is connected to the third S/D region of each of the HE memory structures540f,540g,540h,540i, and540j. Accordingly, the first bit line driver and the first common source/select line driver can control the HE memory structures540a-540jusing the bit lines BL1_1, BL1_2, BL1_3, and BL1_4and the common source/select lines SL1_1and SL1_2with the word lines (not shown).

FIG.6Bshows a top view of the second memory device portion500b, in accordance with some embodiments.FIG.6Bshows the bit lines BL2_1, BL2_2, BL2_3, and the source/select lines SL2_1, SL2_2, SL2_3are connected to a plurality of 2-bit memory structures550a,550b,550c,550d,550e,550f,550g,550h,550i,550j,550k,550l,550m,550n, and550o. Each of the 2-bit memory structures550a-550ois similar or the same as the memory structure300and may be controlled and operated as described above with reference to the memory structure300.

The bit line BL2_1is connected to the first S/D region of each of the 2-bit memory structures550a,550b,550c,550d, and550e. The bit line BL2_2is connected to the first S/D region of each of the 2-bit memory structures550f,550g,550h,550i, and550j. The bit line BL2_3is connected to the first S/D region of each of the 2-bit memory structures550k,550l,550m,550n, and550o. The source/select line SL2_1is connected to the second S/D region of each of the 2-bit memory structures550a,550b,550c,550d, and550e. The source/select line SL2_2is connected to the second S/D region of each of the 2-bit memory structures550f,550g,550h,550i, and550j. The source/select line SL2_3is connected to the second S/D region of each of the 2-bit memory structures550k,550l,550m,550n, and550o.

In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a substrate including a first area and a second area. The semiconductor device in the first area includes a first memory layer extending along a vertical direction and a first semiconductor channel extending along the vertical direction and coupled to a portion of the first memory layer. The semiconductor device in the first area also includes first, second, and third conductive structures extending along the vertical direction. The first and third conductive structures are coupled to end portions of a sidewall of the first semiconductor channel, with the second conductive structure coupled to a middle portion of the sidewall of the first semiconductor channel. The semiconductor device in the second area includes a second memory layer extending along the vertical direction and a second semiconductor channel extending along the vertical direction and coupled to a first portion of the second memory layer. The semiconductor device in the second area includes fourth and fifth conductive structures extending along the vertical direction. The fourth and fifth conductive structures are coupled to end portions of a sidewall of the second semiconductor channel, with no vertically extending conductive structure interposed between the fourth and fifth conductive structures.

In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a first memory array comprising a plurality of first memory cells and a second memory array comprising a plurality of second memory cells. The first and second memory arrays abut each other with an isolation structure interposed therebetween. The two adjacent ones of the plurality of first memory cells are operatively coupled to a common source line. Each of the plurality of second memory cells is operatively coupled to a respective single source line.

In yet another aspect of the present disclosure, a method for fabricating memory devices is disclosed. The method includes providing a substrate including a first area and a second area, forming a stack over both the first and second areas, the stack comprising a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on top of each other, and forming a memory layer extending through the stack, the memory layer extending along a vertical direction and a lateral direction. The method also includes forming a semiconductor channel layer extending through the stack, the semiconductor channel layer also extending along the vertical direction and the lateral direction. The method further includes cutting, in the first area, the semiconductor channel layer into a plurality of first semiconductor channels and cutting, in the second area, the semiconductor channel layer into a plurality of second semiconductor channels. The method also includes forming, in the first area, a triplet of first conductive structures extending in the vertical direction to be in contact with each of the plurality of first semiconductor channels and forming, in the second area, a pair of second conductive structures extending in the vertical direction to be in contact with each of the plurality of second semiconductor channels.

As used herein, the terms “about” and “approximately” generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, about 1000 would include 900 to 1100.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.