Patent ID: 12237870

Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

FIG.1Adepicts an example of two devices150,160configured to communicate with each other over a communication network170.

Each of device150and160may be an electronic device configured to communicate over a wired or wireless network such as communication network170. This electronic device may be a portable or non-portable device. In some implementations, devices150and160are optical devices and can include, but are not limited to, lasers, optical sub-assemblies, original equipment manufacturer (OEM) modules, optical transceivers, sensors, switches, filters, detectors, emitters, and amplifiers.

Device150can include a transmitter (Tx)152to transmit data to other devices, e.g., device160, using the communication network170. Device150can also include a receiver (Rx)154to receive data from other devices, e.g., device160, via the communication network170. Similarly, device160can include a transmitter (Tx)162to transmit data to other devices, e.g., device150, through communication network170, and a receiver (Rx)164to receive data from other devices, e.g., device150, via communication network170. For example, Tx152can transmit one or more modulated optical signals to Rx164through an optical communication path in the communication network170. A description of an example of transmitters152and162is provided below with respect toFIGS.1B and2. A description of an example of receivers154and164is provided below with respect toFIGS.1B and2.

The communication network170can be a wired or wireless network to facilitate communication between multiple electronic devices or components. In some implementations, the communication network170can inlude an optical communication network with optical fiber cables that enable transmission of data in the form of light signals between multiple network nodes and devices, such as devices150and160. The optical communication network can include various components and devices to facilitate the transmission of data across the network. These devices include, for example, amplifiers to amplify a modulated optical signal at various locations along an optical communication path in the optical communication network.

In some implementations, the network nodes may include primary nodes, also referred to as hub nodes, and secondary nodes, also referred to as leaf nodes. A primary node can communicate with multiple secondary nodes. For instance, a primary node may transmit optical subcarriers in a downstream direction to multiple secondary nodes. In some implementations, a primary node can have a data capacity to receive one or more gigabits of data per second for transmission to secondary nodes. Each secondary node may receive and output to a user or customer a portion of the data received from the primary node.

FIG.1Bdepicts an example transmitter100that includes a plurality of switches SW and circuits that include a transmitter Digital Signal Processor DSP (Tx DSP)102and a D/A and optics block101. In some cases, transmitter100can correspond to transmitter152or162shown inFIG.1A. In the example shown inFIG.1B, twenty switches (SW-0to SW-19) are shown, although more or fewer switches can be used. Each switch SW can, in some instances, have two inputs: the first input can receive user data, and the second input can receive control information or signals (CNT). Each switch SW-0to SW-19can receive a respective one of control signals SWC-0to SWC-19output from control circuit171, which can include a microprocessor, field programmable gate array (FPGA), or other processor circuit. Based on the received control signal, each switch SW-0to SW19can selectively output any one of the data streams D-0to D-19, or a control signal CNT-0to CNT-19. Control signals CNT can be any combination of configuration bits for control and/or monitoring purposes. For example, control signals CNT can include instructions to one or more of secondary nodes112to change the data output from such secondary nodes112, such as by identifying the subcarriers associated with such data. In another example, the control signals can include a series of known bits used in secondary nodes112to “train” the receiver to detect and process such bits so that the receiver can further process subsequent bits. In a further example, the control channel CNT can include information that can be used by the polarization mode dispersion (PMD) equalizer circuits to correct for errors resulting from polarization rotations of the X and Y components of one or more subcarriers (SC). In another example, control information CNT can be used to restore or correct phase differences between laser transmit-side laser108and a local oscillator laser in each of the secondary nodes112. In a further example, control information CNT can be used to recover, synchronize, or correct timing differences between clocks provided in the primary (110) and secondary nodes112.

In another, example, one or more of switches SW can be omitted, and control signals CNT can be supplied directly to DSP102. Moreover, each input to DSP102, such as the inputs to FEC encoders202described below (seeFIG.2A), receives, in another example, a combination of control information described above as well as user data.

In a further example, control signal CNT includes information related to the number of subcarriers that can be output from each of secondary nodes112. Circuit such as primary node DSP102can similarly be included in a secondary node Tx DSP to adjust or control the number of subcarriers output therefrom.

Based on the outputs of switches SW-0to SW-19, DSP102can supply a plurality of outputs to D/A and optics block101including digital-to-analog conversion (DAC) circuits104-1to104-4, which convert digital signal received from DSP102into corresponding analog signals. D/A and optics block101also includes driver circuits106-1to106-2that receive the analog signals from DACs104-1to104-4and adjust the voltages or other characteristics thereof to provide drive signals to a corresponding one of modulators110-1to110-4.

D/A and optics block101further includes modulators110-1to110-4, each of which can be, for example, a Mach-Zehnder modulator (MZM) that modulates the phase and/or amplitude of the light output from laser108. The optical light signal output from laser108, also included in block101, is split such that a first portion of the light is supplied to a first MZM pairing, including MZMs110-1and110-2, and a second portion of the light is supplied to a second MZM pairing, including MZMs110-3and110-4. The first portion of the optical light signal is split further into third and fourth portions, such that the third portion is modulated by MZM110-1to provide an in-phase (I) component of an X (or TE) polarization component of a modulated optical signal, and the fourth portion is modulated by MZM110-2and fed to phase shifter112-1to shift the phase of such light by 90 degrees in order to provide a quadrature (Q) component of the X polarization component of the modulated optical signal. Similarly, the second portion of the optical light signal is further split into fifth and sixth portions, such that the fifth portion is modulated by MZM110-3to provide an I component of a Y (or TM) polarization component of the modulated optical signal, and the sixth portion is modulated by MZM110-4and fed to phase shifter112-2to shift the phase of such light by 90 degrees to provide a Q component of the Y polarization component of the modulated optical signal.

The optical outputs of MZMs110-1and110-2are combined to provide an X polarized optical signal including I and Q components and are fed to a polarization beam combiner (PBC)114provided in block101. In addition, the outputs of MZMs110-3and110-4are combined to provide an optical signal that is fed to polarization rotator113, further provided in block101, that rotates the polarization of such optical signal to provide a modulated optical signal having a Y (or TM) polarization. The Y polarized modulated optical signal also is provided to PBC114, which combines the X and Y polarized modulated optical signals to provide a polarization multiplexed (“dual-poi”) modulated optical signal onto optical fiber116, for example, which can be included as a segment of optical fiber in an optical communication path.

Subcarriers SC0-SC19each have X and Y polarization components and I and Q components. Moreover, each subcarrier SC0to SC19can be associated with or corresponds to a respective one of the outputs of switches SW-0to SW-19. In one example, switches SW2, SW7, SW12can supply control information carried by a respective one of control signals CNT-2, CNT-7, CNT-12. Based on such control signals, DSP102provides outputs that result in optical subcarriers SC2, SC7, SC12carrying data indicative of the control information carried by CNT-2, CNT-7, CNT-12, respectively. In addition, remaining subcarriers SC0, SC1, SC3to SC6, SC8to SC11, SC13to SC19carry information indicative of a respective one of data streams D-0, D-1, D-3to D-6, D-8to D-11, D-13to D-19output from a corresponding one of switches SW0, SW1, SW3to SW-6, SW-8to SW11, SW13to SW19.

FIG.2Ashows an example of Tx DSP102in greater detail. Tx DSP102can include FEC encoders202-0to202-19, each of which can receive a respective one of a plurality of the outputs from switches SW0to SW19. FEC encoders202-0to202-19carry out forward error correction coding on a corresponding one of the switch outputs, such as, by adding parity bits to the received data. In addition, FEC encoders202-0to202-19can interleave data.

Each of FEC encoders202-0to202-19provides an output to a corresponding one of a plurality of bits-to-symbol circuits,204-0to204-19(collectively referred to herein as “204”). Each of bits-to-symbol mapping circuits (mappers)204can map the m encoded bits to symbols (where m is a whole number greater than or equal to 2) on a complex plane. Examples of such mappings are shown inFIGS.2B and2C. In the example depicted inFIG.2B, a 3 bit 8-PSK consellation is shown. The symbols are the located on approximately every 45° of a circular pattern having a radius that is equivalent to the magnitude of the real and imaginary parts of the symbols. This magnitude, which is equivalent to the distance from the origin to the symbol, can also provide power information of signal carrying these symbols.

FIG.2Cillustrates a constellation associated with a 16-QAM modulation format consistent with an additional aspect of the present disclosures. As generally understood, each point of the constellation corresponds to a particular symbol, and each symbol has an associated power or amplitude and phase on an IQ plane. For example, constellation point P1represents a first symbol having an associated power or amplitude A1corresponding to a distance from the origin of the IQ plane. Constellation point P2represents a second symbol having an associated power or amplitude A2corresponding to a different distance from the origin. Point P1has an associated first phase, represented by angle Φ1, and point P2has an associated second phase, represented by angle Φ2.

In some implementations, the bits-to-symbol mappers204can map four bits (m=4) to an X symbol+Y symbol in a dual-polarization QPSK constellation. Each of bits-to-symbol mappers204provide first symbols, having the complex representation XI+j*XQ, associated with a respective one of the switch outputs, such as D-0, to DSP102. Data indicative of such first symbols is carried by the X polarization component of each subcarrier SC0-SC19.

Each of bits-to-symbol mappers204further can provide second symbols having the complex representation YI+j*YQ, also associated with a corresponding output of switches SW0-SW19. Data indicative of such second symbols, however, is carried by the Y polarization component of each of subcarriers SC-0to SC-19.

Such mapping, as performed by mappers204-0to204-19define, in one example, a particular modulation format for each subcarrier. That is, such circuit can define a mapping for all the optical subcarrier that is indicative of a binary phase shift keying (BPSK) modulation format, a quadrature phase shift keying (QPSK) modulation format, or an m-quadrature amplitude modulation (QAM, where m is a positive integer, e.g., 4, 8, 16, or 64) format. In another example, one or more of the optical subcarriers can have a modulation format that is different than the modulation format of other optical subcarriers. That is, one of the optical subcarriers can have a QPSK modulation format and another optical subcarrier can have a different modulation format, such as 8-QAM or 16-QAM. In another example, one of the optical subcarriers has an 8-QAM modulation format and another optical subcarrier has a 16 QAM modulation format. Accordingly, although all the optical subcarriers can carry data at the same data and or baud rate, consistent with an aspect of the present disclosure one or more of the optical subcarriers can carry data at a different data or baud rate than one or more of the other optical subcarriers. Moreover, modulation formats, baud rates and data rates can be changed over time depending on, for example, capacity requirements. Adjusting such parameters can be achieved, for example, by applying appropriate signals to mappers204based on control information or data described herein and the communication of such data as further disclosed herein between primary and secondary nodes.

As further shown inFIG.2A, each of the first symbols output from each of bits-to-symbol mappers204is supplied to a respective one of first overlap and save buffers205-0to205-19(collectively referred to herein as overlap and save buffers205) that can buffer, for example, 256 symbols. Each of overlap and save buffers205can receive, for example, 128 of the first symbols or another number of such symbols at a time from a corresponding one of bits-to-symbol mappers204. Thus, overlap and save buffers205can combine, for example, 128 new symbols from bits to symbol circuits205, with the previous 128 symbols received from bits to symbol circuits205.

Each overlap and save buffer205can supply an output, which is in the time domain, to a corresponding one of fast Fourier Transform (FFT) circuits206-0to206-19(collectively referred to as “FFTs 206”). In one example, the output includes 256 symbols or another number of symbols. Each of FFTs206can convert the received symbols to the frequency domain using or based on, for example, a fast Fourier transform. Each of FFTs206can provide the frequency domain data to bins and switches blocks221-0to221-19. Bins and switches blocks221can include, for example, memories or registers, also referred to as frequency bins (FB) or points, that store frequency components associated with each subcarrier SC.

Each switch SW can selectively supply either frequency domain data output from one of FFT circuits206-0to206-19or a predetermined value, such as 0. In order to block or eliminate transmission of a particular subcarrier, the switches SW associated with the group of frequency bins FB associated with that subcarrier are configured to supply the zero value to corresponding frequency bins. Replicator components207as well as other components and circuits in DSP102can further process the zero (0) values to provide drive signals to modulators110, such that subcarrier SC0is omitted from the optical output from the modulators.

On the other hand, some switches SW (not shown) can be configured to supply the outputs of FFTs206, i.e., frequency domain data FD, to corresponding frequency bins FB. Further processing of the contents of frequency bins FB by replicator components207and other circuits in DSP102can result in drive signals supplied to modulators110, whereby, based on such drive signals, optical subcarriers are generated that correspond to the frequency bin groupings associated with that subcarrier.

Each of replicator components or circuits207-0to207-19can replicate the contents of the frequency bins FB and store such contents (e.g., for T/2 based filtering of the subcarrier) in a respective one of the plurality of replicator components. Such replication can increase the sample rate. In addition, replicator components or circuits207-0to207-19can arrange or align the contents of the frequency bins to fall within the bandwidths associated with pulse shaped filter circuits208-0to208-19described below.

Each of pulse shape filter circuits208-0to208-19can apply a pulse shaping filter to the data stored in the frequency bins of a respective one of the plurality of replicator components or circuits207-0to207-19to thereby provide a respective one of a plurality of filtered outputs, which are multiplexed and subject to an inverse FFT, as described below. Pulse shape filter circuits208-1to208-19calculate the transitions between the symbols and the desired subcarrier spectrum so that the subcarriers can be packed together spectrally for transmission, e.g., with a close frequency separation. Pulse shape filter circuits208-0to208-19also can be used to introduce timing skew between the subcarriers to correct for timing skew induced by links between nodes in the transmitter100, for example. Multiplexer component209, which can include a multiplexer circuit or memory, can receive the filtered outputs from pulse shape filter circuits208-0to208-19, and multiplex or combine such outputs together to form an element vector.

Next, IFFT circuit or component210-1can receive the element vector and provide a corresponding time domain signal or data based on an inverse fast Fourier transform (IFFT). In one example, the time domain signal can have a rate of 64 GSample/s. Take last buffer or memory circuit211-1, for example, can select the last 1024 samples, or another number of samples, from an output of IFFT component or circuit210-1and supply the samples to DACs104-1and104-2(seeFIG.1B) at 64 GSample/s, for example. As noted above, DAC104-1is associated with the in-phase (I) component of the X pol signal, and DAC104-2is associated with the quadrature (Q) component of the X pol signal. Accordingly, consistent with the complex representation XI+jXQ, DAC104-1receives values associated with XI and DAC104-2receives values associated with jXQ. As indicated byFIG.1B, based on these inputs, DACs104-1and104-2can provide analog outputs to MZMD106-1and MZMD106-2, respectively, as discussed above.

As further shown inFIG.2A, each of bits-to-symbol mapping circuits (mappers)204-0to204-19can output a corresponding one of symbols indicative of data carried by the Y polarization component of the polarization multiplexed modulated optical signal output on fiber116. As further noted above, these symbols can have the complex representation YI+j*YQ. Each such symbol can be processed by a respective one of overlap and save buffers215-0to215-19, a respective one of FFT circuits216-0to216-19, a respective one of replicator components or circuits217-0to217-19, pulse shape filter circuits218-0to218-19, multiplexer or memory219, IFFT210-2, and take last buffer or memory circuit211-2, to provide processed symbols having the representation YI+j*YQ in a manner similar to or the same as that discussed above in generating processed symbols XI+j*XQ output from take last circuit211-1. In addition, symbol components YI and YQ are provided to DACs104-3and104-4(FIG.1B), respectively. Based on these inputs, DACs104-3and104-4can provide analog outputs to MZMD106-3and MZMD106-4, respectively, as discussed above.

WhileFIG.2Ashows DSP102as including a particular number and arrangement of functional components, in some implementations, DSP102can include additional functional components, fewer functional components, different functional components, or differently arranged functional components. In addition, typically the number of overlap and save buffers, FFTs, replicator circuits, and pulse shape filters associated with the X component can be equal to the number of switch outputs, and the number of such circuits associated with the Y component can also be equal to the number of switch outputs. However, in other examples, the number of switch outputs can be different from the number of these circuits.

As noted above, based on the outputs of MZMDs106-1to106-4, a plurality of optical subcarriers SC0to SC19can be output onto optical fiber116(FIG.1B), which is coupled to a primary node110.

Consistent with an aspect of the present disclosure, the number of subcarriers transmitted from primary node110to secondary nodes112can vary over time based, for example, on capacity requirements at the primary node and the secondary nodes. For example, if less downstream capacity is required initially at one or more of the secondary nodes, transmitter100in primary node110can be configured to output fewer optical subcarriers. On the other hand, if further capacity is required later, transmitter100can provide more optical subcarriers.

In addition, if, for example, based on changing capacity requirements, a particular secondary node112should be adjusted, the output capacity of such secondary node can be increased or decreased by, in a corresponding manner, increasing or decreasing the number of optical subcarriers output from the secondary node.

By storing and subsequently processing zeros (0s) or other predetermined values in frequency bin FB groupings associated with a given subcarrier SC, the subcarrier can be removed or eliminated. To add or reinstate such subcarrier, frequency domain data output from the FFTs206can be stored in frequency bins FB and subsequently processed to provide the corresponding subcarrier. Thus, subcarriers can be selectively added or removed from the optical outputs of primary node transmitter100, such that the number of subcarriers output from such transmitters can be varied, as desired.

In the above example, zeros (0s) or other predetermined values are stored in selected frequency bins FBs to prevent transmission of a particular subcarrier SC. Such zeroes or values can, instead, be provided, for example, in a manner similar to that described above, at the outputs of corresponding replicator components207or stored in corresponding locations in memory or multiplexer209. Alternatively, the zeroes or values noted above can be provided, for example, in a manner similar to that described above, at corresponding outputs of pulse shape filters208.

In a further example, a corresponding one of pulse shape filters208-1to208-19can selectively generate zeroes or predetermined values that, when further processed, also cause one or more subcarriers SC to be omitted from the output of either primary node or secondary node. For instance, pulse shape filters208-0to208-19can include groups of multiplier circuits M0-0to M0-nM19-0to M19-n(not shown, also individually or collectively referred to as M). Each multiplier circuit M constitutes part of a corresponding butterfly filter. In addition, each multiplier circuit grouping is associated with a corresponding one of subcarriers SC.

Each multiplier circuit M receives a corresponding one output from replicator components207. In order to remove or eliminate one of subcarriers SC, multiplier circuits M receiving the outputs within a particular grouping associated with that subcarrier multiply such outputs by zero (0), such that each multiplier M within that group generates a product equal to zero (0). The zero products then can be subject to further processing similar to that described above to provide drive signals to modulators110that result in a corresponding subcarrier SC being omitted from the output of the transmitter100.

On the other hand, in order to provide a subcarrier SC, each of the multiplier circuits M within a particular grouping can multiply a corresponding one of replicator outputs RD by a respective one of coefficients C0-0to C0-n. . . C19-0to C19-n, which results in at least some non-zero products being output. Based on the products output from the corresponding multiplier grouping, drive signals are provided to modulators110to output the desired subcarrier SC from the transmitter100.

Accordingly, for example, in order to block or eliminate subcarrier SC0, each of multiplier circuits M0-0to M0-n(associated with subcarrier SC0) multiplies a respective one of replicator outputs RD0-0to RD0-nby zero (0). Each such multiplier circuit, therefore, provides a product equal to zero, which is further processed, such that resulting drive signals cause modulators110to provide an optical output without SC0. In order to reinstate SC0, multiplier circuits M0-0to M0-nmultiply a corresponding one of appropriate coefficients C0-0to C0-nby a respective one of replicator outputs RD0-0to RD0-nto provide products, at least some of which are non-zero. Based on these products, as noted above, modulator drive signals are generated that result in subcarrier SC0being output.

The above examples are described in connection with generating or removing the X component of a subcarrier SC. The processes and circuitry described above can be employed or included in Tx DSP102and optical circuitry used to generate the Y component of the subcarrier to be blocked. For example, switches and bins circuit blocks222-0to222-19, have a similar structure and operate in a similar manner as switches and bins circuit blocks221described above to provide zeroes or frequency domain data as the case can be to selectively block the Y component of one or more subcarriers SC.

When signals are transmitted over an optical fiber116or, in general, across a channel310to another device using, for example, the transmitter100, the quality of the transmitted signal can be compromised and/or the receiver (Rx) may not be synchronized to the transmission of data from the transmitter100. To address such problems, certain circuits can be implemented to provide different levels of synchronization. Furthermore, in some cases, different layers of synchronization can be implemented to facilitate communication between a transmitter Tx and a receiver Rx. Such layers are generally implemented as a set of agreements between a transmitter Tx and a receiver Rx. Examples of these agreements are baud rate, data rate and modulation format.

This disclosure provides details of an example agreement directed to the frame structure of signals communicated between a transmitter Tx such as transmitter100and a receiver Rx such as receiver502described with reference to the figures. A frame structure determines the format of one full cycle of data transmission between a transmitter Tx and a receiver Rx. This format can include the position of header symbols (if any), the position of pilot symbols (if any), and the position of payloads. The frame structure can also be used to determine the position of symbols relative to others and can inform a receiver Rx where to look for various types of symbols within a sequence of received symbols.

FIG.8depicts an example of a payload frame structure800having length L. The payload frame structure800includes an alternating sequence of payload symbols (pa)810and pilot symbols (pi)820. The payload frame structure800can be generated by inserting a pilot symbol (pi)820at the beginning of the payload data and additional pilot symbols (pi)820after a predetermined interval of payload symbols (pa)810following the first pilot symbol. This can be dones for all payload data to be transmitted in a frame. In this manner, the pilot symbols820are uniformly distributed between the payload symbols810. However, one issue with using this structure is that it is difficult for a receiver Rx to detect the beginning of the frame or estimate a frequency offset. Without determining the beginning of the frame, a receiver Rx may not be able to properly synchronize the data it received with the data transmitted by transmitter100.

FIG.9depicts an example of a frame structure900that includes a frame header920and a payload800. Frame structure900includes a payload800that is the same as the payload800shown inFIG.8and additionally includes a frame header of H symbols preceding the payload800. The frame header920can be used to indicate the beginning of a frame.

The frame structure900includes three types of symbols, namely a frame symbol (fs)910, a payload symbol (pa)810, and a pilot symbol (pi)820. A frame symbol910is inserted at the beginning of each frame. The frame symbol910can be used for frequency offset estimation, BER calculation, and framing. A payload symbol810can carry information to be communicated to the receiver Rx and is located after the frame header. Pilot symbols820can be uniformly distributed between other symbols. For example, as shown inFIG.9, pilot symbols820are uniformly distributed across the frame header920and the payload800and can separate frame symbols910and payload symbols810.

The payload portion of a frame can be thousands of symbols long, e.g., 200,000 symbols, and pilot symbols can be inserted after regular intervals, e.g., every 32 or 64 payload symbols. The frame header can be hundreds of symbols in length and the pilot symbols can be inserted every 32 or 64 frame symbols. The order of pilot symbols can be stored in a look up table (LUT) and can be shared with a receiver Rx as part of a frame structure agreement. Pilot symbols820can be used for training-based equalization, and cycle slip detection/correction. However, to perform operations such as training-based equalization, the location of the pilot symbols820should be known first.

A receiver Rx would know where to look for the particular symbols in a sequence of receiver symbols by virtue of having a frame structure agreement in place between a transmitter Tx and the receiver Rx. As an example, inFIG.9, by detecting the presence and location of frame symbols910, a receiver Rx can be able to identify the beginning of transmitted frame. Furthermore, through the use of a LUT, the receiver Rx can use the sequence of pilot symbols to determine the correct sequence of transmitted data.FIGS.3and4describe how a transmitter Tx can be configured to generate a frame structure with header and frame symbols910.FIGS.5,5A,6, and7describe how a receiver Rx can be configured to detect the beginning of a transmitted frame (framer index).

The operations shown inFIGS.3and4can be executed by the Tx DSP102described inFIGS.1and2. In some implementations, a Tx framer circuit320can be included in the Tx DSP102to execute these operations. The Tx framer circuit320can be included in different locations of the Tx DSP102before the symbols are processed by the overlap and safe buffer205. For example, in some implementations, the Tx framer circuit320can be implemented between the mappers204an the overlap and save buffers205. In some implementations, the Tx framer circuit320can be implemented between the FEC encoders202and the mappers204.

In general, the Tx framer circuit320can include hardware and/or software that can execute commands to implement the operations described in this specification. Instructions for executing one or more of these operations can be stored in a storage device integrated with, coupled to, or accessible by the Tx DSP102. After the Tx DSP102obtains these instructions, the Tx framer circuit320can execute the operations according to the commands in the stored instructions in the manner described below with respect toFIGS.3and4.

After mappers204(e.g., mappers204-0to204-19shown inFIGS.2A and3) generate symbols from bits, a sequence of payload symbols (pa)810with intervening pilot symbols (pi)820can be generated. In some implementations, before FFT operations are performed, e.g., by FFT206-0to206-19and216-0to216-19shown inFIG.2A, the Tx framer circuit320can add a header with frame symbols (fs)910to the frame structure as described with reference toFIG.4.

FIG.4depicts an example of interleaving framer symbols910and pilot 820 symbols in a frame header920. The frame header920can be of various sizes, e.g., various multiples of 32 symbols. In the example shown inFIG.4, a frame header920having 192 symbols is to be generated. In such instances, half (96) the number of symbols can be selected to be used as framer symbols410. In some implementations, the selection is made randomly. In some implementations, the selection of framer symbols410must satisfy a power constraint such that the average power of framer symbols410is equal to the average power of the payload symbols (pa)810. In such implementations, the Tx DSP102can additionally perform an operation to check the average power of the symbols (pa)810and the framer symbols410when selecting the framer symbols410. As noted above, the average power can be determined using the amplitude and phase associated with the symbols.

Next, an equal number (96) of scrambler symbols420as framer symbols410can be obtained and multiplied with each framer symbol to yield scrambled framer symbols430. The scrambler symbols420have random values of 1 or −1. As shown inFIG.4, a first processing path can include the scrambled framer symbols430. The initial framer symbols410can occupy a second processing path. An interleaving operation can then be performed such that the scrambled framer symbols430from the first processing path are interleaved with framer symbols410from the second processing path to generate a header portion440.

The interleaving can be implemented in various ways. In some cases, the framer symbols410and the scrambled framer symbols430can be concatenated one after another. In some cases, the framer symbols410and the scrambled framer symbols430can be designated to be located an even and odd index positions in the sequence of pilots. In some cases, a fixed number of framer symbols410are placed first followed by the same number symbols of the scrambled framer symbols430. This continues until all symbols from the two processing paths are consumed.

In some implementations, after generating the interleaved sequence of symbols resulting in header portion440, every 32ndsymbol can be designated as the pilot symbol. In some implementations, a pilot symbol can be inserted into every 32ndsymbol slot of the interleaved structure. A scrambled version of the pilot symbols can also be inserted after every 32ndsymbol (not at the same position as the pilot symbol) of the interleaved structure to be able to get a peak cross correlation. The position of the scrambled pilot symbols with respect to the pilot symbols can depend on the interleaving period. Two header symbols in every set of 32 pilots can be removed from the interleaved sequence to accommodate the insertion of the pilot and scrambled pilot symbols while keeping the total symbol count to 192 header symbols. In this manner, a frame header920structure with framer symbols (fs)910separated by pilot symbols (pi)820can be generated. Information for each pilot symbol can be stored in a look up table and shared with a receiver Rx. For example, in the illustrated frame header920structure, 6 pilot symbols are present at positions 1, 33, 65, 97, 129, and 161. And 6 scrambled pilot symbols are present at positions 4, 36, 68, 100, 132, and 164 if we interleave every 3 symbols (interleaving period). The position of the scrambled pilot symbols can vary if the interleaving period is changed. The remaining 180 symbols in the frame header920are framer symbols.

As shown inFIG.3, after the addition of the frame header920to the payload800, the frame can be processed by other components of the Tx DSP102and transmitter100(seeFIGS.1and2) before being transmitted over a channel310towards a receiver Rx, which includes a Rx DSP550to process the received signal. As discussed in more detail below inFIGS.5,5A,6, and7, the Rx DSP includes a Rx framer circuit710that can detect the beginning of the frame using the framer symbols (fs)910in the frame header920.

FIG.5depicts an example of a receiver Rx such as receiver502that includes an Rx optics and A/D block500and Rx DSP550to carry out coherent detection. In some cases, receiver502can correspond to receiver Rx154or164shown inFIG.1A. The Rx optics and A/D block500can include a polarization splitter (PBS)505with first and second outputs, a splitter505-3, a local oscillator (LO) laser510, 10 degree optical hybrid circuits or mixers520-1and520-2(referred to generally as hybrid mixers520and individually as hybrid mixer520), detectors530-1and530-2(referred to generally as detectors530and individually as detector530, each including either a single photodiode or balanced photodiode), AC coupling capacitors532-1and532-2, transimpedance amplifiers/automatic gain control circuits TIA/AGC534-1and534-2, ADCs540-1and540-2(referred to generally as ADCs540and individually as ADC540).

Polarization beam splitter (PBS)505can include a polarization splitter that receives an input polarization multiplexed optical signal including optical subcarriers SC0to SC19supplied by optical fiber link501, which can be, for example, an optical fiber segment as part of one of optical communication path116. PBS505can split the incoming optical signal into the two X and Y orthogonal polarization components. The Y component can be supplied to a polarization rotator506that rotates the polarization of the Y component to have the X polarization. Hybrid mixers520can receive and combine the X and rotated Y polarization components with light from local oscillator laser510, which, in one example, is a tunable laser. For example, hybrid mixer520-1can combine a first polarization signal (e.g., the component of the incoming optical signal having a first or X (TE) polarization output from a first PBS port with light from local oscillator510, and hybrid mixer520-2can combine the rotated polarization signal (e.g., the component of the incoming optical signal having a second or Y (TM) polarization output from a second PBS port) with the light from local oscillator510. In one example, polarization rotator510can be provided at the PBS output to rotate Y component polarization to have the X polarization.

Detectors530can detect mixing products output from the optical hybrids, to form corresponding voltage signals, which are subject to AC coupling by capacitors532-1and532-1, as well as amplification and gain control by TIA/AGCs534-1and534-2. The outputs of TIA/AGCs534-1and534-2and ADCs540can convert the voltage signals to digital samples. For example, two detectors (e.g., photodiodes)530-1can detect the X polarization signals to form the corresponding voltage signals, and a corresponding two ADCs540-1can convert the voltage signals to digital samples for the first polarization signals after amplification, gain control and AC coupling. Similarly, two detectors530-2can detect the rotated Y polarization signals to form the corresponding voltage signals, and a corresponding two ADCs540-2can convert the voltage signals to digital samples for the second polarization signals after amplification, gain control and AC coupling. Rx DSP550can process the digital samples associated with the X and Y polarization components to output data associated with one or more subcarriers within a group of subcarriers. For example, as shown inFIG.5A, SC0to SC19can be encompassed by the bandwidth (one of bandwidths BWj, BWk, BWI, and BWm) associated with a secondary node housing the DSP550. In particular, subcarriers SC0to SC8are within bandwidth BWj, and such subcarriers can be processed by the receiver in a secondary node112. Subcarriers SC5to SC13can be located within bandwidth BWk and processed by the receiver in secondary node112. That is, bandwidths BWj and BWk overlap, such that subcarriers within the overlapped portions of these bandwidths, namely, subcarriers SC5to SC8, will be processed by the receivers in one or more secondary nodes112. Similarly, subcarriers SC10to SC18are within bandwidth BWI and subcarriers SC11to SC19are within bandwidth BWm, which substantially overlaps with BWm, as shown inFIG.5A.

WhileFIG.5shows receiver502as including a particular number and arrangement of components, in some implementations, receiver502can include additional components, fewer components, different components, or differently arranged components. The number of detectors530and/or ADCs540can be selected to implement an receiver502that is capable of receiving a polarization multiplexed signal. In some instances, one of the components illustrated inFIG.5can carry out a function described herein as being carry out by another one of the components illustrated inFIG.5.

Consistent with the present disclosure, in order to select a particular subcarrier or group of subcarriers at a secondary node112, local oscillator510can be tuned to output light having a wavelength or frequency relatively close to the selected subcarrier wavelength(s) to thereby cause a beating between the local oscillator light and the selected subcarrier(s). Such beating will either not occur or will be significantly attenuated for the other non-selected subcarriers so that data carried by the selected subcarrier(s) is detected and processed by Rx DSP550.

As noted above, each secondary node112can have a smaller bandwidth than the bandwidth associated with primary node110. The subcarriers encompassed by each secondary node112can be determined by the frequency of the local oscillator laser510in the receiver502. For example, as shown inFIG.5A, bandwidth BWj associated with a secondary node112-jcan be centered about local oscillator frequency fLOj, bandwidth BWk associated with secondary node112-kcan be centered about local oscillator frequency fLOk, bandwidth BWI associated with secondary node112-lcan be centered about local oscillator frequency fLOl, and bandwidth BWm associated with secondary node112-mcan be centered about local oscillator frequency fLOm. Accordingly, each bandwidth BWj to BWm can shift depending on the frequency of each secondary node local oscillator laser510. Tuning the local oscillator frequency, for example, by changing the temperature of the local oscillator laser510can result in corresponding shifts in the bandwidth to encompass a different group of subcarriers than were detected prior to such bandwidth shift. The temperature of the local oscillator laser510can be controlled with a thin film heater. Alternatively, the local oscillator laser can be frequency tuned by controlling the current supplied to the laser. The local oscillator laser510can be a semiconductor laser, such as a distributed feedback laser or a distributed Bragg reflector laser.

The maximum bandwidth or number of subcarriers that can be received, detected, and processed by an receiver502, however, can be restricted based on hardware limitations of the various circuit components in receiver502, as noted above, and, therefore, can be fixed. Accordingly, as noted above, the bandwidth associated with each secondary node112can be less than a bandwidth associated with primary node110. Further, consistent with the present disclosure, the number of secondary nodes can be greater than the number of subcarriers output from primary node110. In addition, the number of upstream subcarriers received by primary node110can be equal to the number of subcarriers transmitted by primary node110in the upstream direction. Alternatively, the number of subcarriers transmitted in the upstream direction collectively by secondary nodes112can less than or greater than the number of downstream subcarriers output from the primary node. Further, in another example, one or more of secondary nodes112can output a single subcarrier.

As shown inFIG.5A, in some implementations, the bandwidths associated with secondary nodes112can overlap, such that, as further noted above, certain subcarriers SC can be detected by multiple secondary nodes112. If the data associated with such subcarriers SC is intended for one of those secondary nodes, but not the other, switch circuitry, as noted above, can be provided in the secondary nodes to output the data selectively at the intended secondary node but not the others.

In some implementations, guard bands or frequency gaps can be provided between adjacent subcarriers SC. A guard band can be provided between subcarriers SC4and SC5, and another guard band can be provided between subcarriers SC5and SC6. Additional guard bands can be provided between remaining adjacent pairs of subcarriers. Such guard bands can be provided in order to detect and process each subcarrier more accurately by reducing crosstalk or other interference between the subcarriers.

As further shown inFIG.5, switches or circuits SW-0to SW-19can be provided at the output of Rx DSP550to selectively output the data detected from the received subcarriers based on a respective one of control signals CNT-0to CNT-19output from control circuit571, which, like control circuit171noted above can include a microprocessor, FPGA, or other processor circuit. Control signals can designate the output of each respective switch. Accordingly, for example, if data carried by predetermined subcarriers is intended to be output at a particular secondary node112, switches SW at that secondary node can be configured, based on the received control signals CNT, to supply the desired data, but block data not intended for that node.

FIG.6illustrates exemplary components of the Rx DSP550. As noted above, analog-to-digital (A/D) circuits540-1and540-2(FIG.5) output digital samples corresponding to the analog inputs supplied thereto. In one example, the samples can be supplied by each A/D circuit at a rate of 64 GSamples/s. The digital samples may correspond to symbols carried by the X polarization of the optical subcarriers and can be represented by the complex number XI+jXQ. The digital samples can be provided to overlap and save buffer605-1, as shown inFIG.6. FFT component or circuit610-1can receive the 2048 vector elements from the overlap and save buffer605-1and convert the vector elements to the frequency domain using, for example, a fast Fourier transform (FFT). The FFT component610-1can convert the 2048 vector elements to 2048 frequency components, each of which can be stored in a register or “bin” or other memory, as a result of carrying out the FFT.

The frequency components can be demultiplexed by demultiplexer611-1, and groups of such components can be supplied to a respective one of chromatic dispersion equalizer circuits CDEQ612-1-0to612-1-19, each of which can include a finite impulse response (FIR) filter that corrects, offsets or reduces the effects of, or errors associated with, chromatic dispersion of the transmitted optical subcarriers. Each of CDEQ circuits612-1-0to612-1-19supplies an output to a corresponding polarization mode dispersion (PMD) equalizer circuit625-0to625-19(which individually or collectively can be referred to as625). Without loss of generality, PMD equalizer can be done in frequency domain as shown inFIG.6or it can be done in time domain after IFFT630and before carrier phase correction640.

Digital samples output from A/D circuits540-2associated with Y polarization components of subcarrier SC1can be processed in a similar manner to that of digital samples output from A/D circuits540-1and associated with the X polarization component of each subcarrier. Namely, overlap and save buffer605-2, FFT610-2, demultiplexer611-2, and CDEQ circuits612-2-0to612-2-19can have a similar structure and operate in a similar fashion as buffer605-1, FFT610-1, demultiplexer611-1, and CDEQ circuits612-1-0to612-1-19, respectively. For example, each of CDEQ circuits612-2-0to612-19can include an FIR filter that corrects, offsets, or reduces the effects of, or errors associated with, chromatic dispersion of the transmitted optical subcarriers. In addition, each of CDEQ circuits612-2-0to612-2-19provide an output to a corresponding one of PMDEQ625-0to625-19.

As further shown inFIG.6, the output of one of the CDEQ circuits, such as CDEQ612-1-0can be supplied to clock phase detector circuit613to determine a clock phase or clock timing associated with the received subcarriers. Such phase or timing information or data can be supplied to ADCs540-1and540-2to adjust or control the timing of the digital samples output from ADCs540-1and540-2.

Each of PMDEQ circuits625can include another FIR filter that corrects, offsets or reduces the effects of, or errors associated with, PMD of the transmitted optical subcarriers. Each of PMDEQ circuits625can supply a first output to a respective one of IFFT components or circuits630-0-1to630-19-1and a second output to a respective one of IFFT components or circuits630-0-2to630-19-2, each of which can convert a 256-element vector, in this example, back to the time domain as 256 samples in accordance with, for example, an inverse fast Fourier transform (IFFT).

Time domain signals or data output from IFFT630-0-1to630-19-1are supplied to a corresponding one of Xpol carrier phase correction circuits640-0-1to640-19-1, which can apply carrier recovery techniques to compensate for X polarization transmitter (e.g., laser108) and receiver (e.g., local oscillator laser510) linewidths. In some implementations, each carrier phase correction circuit640-0-1to640-19-1can compensate or correct for frequency and/or phase differences between the X polarization of the transmit signal and the X polarization of light from the local oscillator510based on an output of Xpol carrier recovery circuits640-0-1to640-19-1, which performs carrier recovery in connection with one of the subcarrier based on the outputs of IFFTs630-0-1to630-19-1. After such X polarization carrier phase correction, the data associated with the X polarization component can be represented as symbols having the complex representation xi+j*xq in a constellation, such as a QPSK constellation or a constellation associated with another modulation formation, such as an m-quadrature amplitude modulation (QAM), m being an integer. In some implementations, the taps of the FIR filter included in one or more of PMDEQ circuits625can be updated based on the output of at least one of carrier phase correction circuits640-0-1to640-19-01.

In a similar manner, time domain signals or data output from IFFT630-0-2to630-19-2are supplied to a corresponding one of Ypol carrier phase correction circuits640-0-2to640-19-2, which can compensate or correct for Y polarization transmitter (e.g., laser108) and receiver (e.g., local oscillator laser510) linewidths. In some implementations, each carrier phase correction circuit640-0-2to640-19-2also can correct or compensate for frequency and/or phase differences between the Y polarization of the transmit signal and the Y polarization of light from the local oscillator510. After such Y polarization carrier phase correction, the data associated with the Y polarization component can be represented as symbols having the complex representation yi+j*yq in a constellation, such as a QPSK constellation or a constellation associated with another modulation formation, such as an m-quadrature amplitude modulation (QAM), m being an integer. In some implementations, the output of one of circuits640-0-2to640-19-2can be used to update the taps of the FIR filter included in one or more of PMDEQ circuits625instead of, or in addition to, the output of at least one of the carrier recovery circuits640-0-1to640-19-1.

The equalizer, carrier recovery, and clock recovery can be further enhanced by utilizing the known (training) bits that can be included in control signals CNT, for example by providing an absolute phase reference between the transmitted and local oscillator lasers.

Each of the symbols-to-bits circuits or components645-0-1to645-19-1can receive the symbols output from a corresponding one of circuits640-0-1to640-19-1and map the symbols back to bits. For example, each of the symbol-to-bits components645-0-1to645-19-1can demap one X polarization symbol, in a QPSK or m-QAM constellation, to Z bits, where Z is an integer. For dual-polarization QPSK modulated subcarriers, Z is two. Bits output from each of component645-0-1to645-19-1are provided to a corresponding one of FEC decoder circuits660-0to660-19.

Y polarization symbols are output form a respective one of circuits640-0-2to640-19-2, each of which has the complex representation yi+j*yq associated with data carried by the Y polarization component. Each Y polarization, like the X polarization symbols noted above, can be provided to a corresponding one of symbols-to-bits circuits or components (demappers)645-0-2to645-19-2, each of which has a similar structure and operates in a similar manner as symbols-to-bits component645-0-1to645-19-1. Each of circuits645-0-2to645-19-2can provide an output to a corresponding one of FEC decoder circuits660-0to660-19.

Each of FEC decoder circuits660can remove errors in the outputs of symbol-to-bit circuits645using, for example, forward error correction. Such error corrected bits, which can include user data for output from secondary node112, can be supplied to a corresponding one of switch circuits SW-0to SW-19. As noted above, switch circuits SW-0to SW-19in each secondary node112can selectively supply or block data based on whether such data is intended to be output from the secondary node. In addition, if one of the received subcarriers' control information (CNT), such as information identifying switches SW that output data and other switches SW that block data, the control information can be output from one of the switches and, based on such control information, control circuit571in the secondary nodes to generate the control signals CNT.

Consistent with another aspect of the present disclosure, data can be blocked from output from Rx DSP550without the use of switches SW-0to SW-19. In one example similar to an example described above, zero (0) or other predetermined values can be stored in frequency bins associated with the blocked data, as well as the subcarrier corresponding to the blocked data. Further processing described above of such zeroes or predetermined data by circuitry in Rx DSP550can result in null or zero data outputs, for example, from a corresponding one of FEC decoders660. Switch circuits provided at the outputs of FFTs610-1and610-2, like switch circuits SW described above inFIG.2A, can be provided to selectively insert zeroes or predetermined values for selectively blocking corresponding output data from DSP550. Such switches also can be provided at the output of or within demultiplexers611-1and611-2to selectively supply zero or predetermined values.

In another example, zeroes (0s) can be inserted in chromatic dispersion equalizer (CDEQ) circuits612associated with both the X and Y polarization components of each subcarrier. In particular, multiplier circuits (provided in corresponding butterfly filter circuits), like multiplier circuits M described above, can selectively multiply the inputs to the CDEQ circuit612by either zero or a desired coefficient. Multiplication by a zero generates a zero product. When such zero products are further processed by corresponding circuitry in DSP550, e.g., corresponding IFFTs630, carrier phase correction components640, symbol-to-bits components645, and FEC decoder660, a corresponding output of DSP550will also be zero. Accordingly, data associated with a subcarrier SC received by a secondary node receiver112, but not intended for output from that receiver, can be blocked.

If, on the other hand, capacity requirements change and such previously blocked data is to be output from a given secondary node receiver DSP550, appropriately coefficients can be supplied to the multiplier circuits, such that at least some of the inputs thereto are not multiplied by zero. Upon further processing, as noted above, data associated with the inputs to the multiplier circuits and corresponding to a particular subcarrier SC is output from secondary node receiver DSP550.

WhileFIG.6shows DSP550as including a particular number and arrangement of functional components, in some implementations, DSP650can include additional functional components, fewer functional components, different functional components, or differently arranged functional components.

FIG.7depicts an example of a receiver Rx DSP550that includes a Rx framer circuit710to perform framer index and frequency offset estimation among various other functions. In general, the Rx framer circuit710can include hardware and/or software that can execute commands to implement the operations described in this specification. Instructions for executing one or more of these operations can be stored in a storage device integrated with, coupled to, or accessible by the Rx DSP550. After the Rx DSP550obtains these instructions, the Rx framer circuit710can execute the operations according to the commands in the stored instructions in the manner described below.

The Rx framer circuit710can be placed in different parts of the Rx DSP550. For instance, in some cases, e.g., when there is a single carrier, the Rx framer circuit710can be placed at the beginning of the Rx DSP550immediately after the ADCs540. In some cases, e.g., when there is are multiple carriers, the Rx framer circuit710can be placed immediately after the DEMUX components or circuits611. In both cases, single or multiple carriers systems, the Rx framer circuit710can be placed before the equalizer612when operating in the sample domain and after performing time domain conversion. When operating in the symbol domain, the Rx framer circuit710can be placed after the IFFT components or circuits630.

Due do the flexibility of implementing the Rx framer circuit710in different parts of the Rx DSP550, the Rx framer circuit710is not shown inFIG.6. However, as an example,FIG.7depicts an instance in which the Rx framer circuit710is implemented after the IFFT components or circuits630perform time domain conversion.

As explained above with respect toFIGS.5and6, a signal501can be received over an optical fiber link501or channel310and processed by Rx optics and A/D block500. The output from the ADC540is fed to the Rx DSP550for further processing. The Rx framer circuit710can execute a framer index estimation algorithm that utilizes a sliding window720to process received symbols as shown inFIG.7. The window720can be equal to the width of the header symbols inserted at the Tx side. For instance, in the example shown inFIG.4, the frame header920has 192 symbols. The Rx DSP550can control the window720such that it slides one symbol at a time to process each symbol. While the window720is applied to the symbols, the received symbols can be temporarily stored in a buffer.

Symbols within the sliding window720can be de-interleaved every preset number of symbols, e.g., 3 symbols. The sequence of received symbols are deinterleaved into two symbol sequences (sequence730and sequence740) to recover the original arrangement of framer symbols410and scrambled symbols430, respectively, as implemented by the Tx DSP102(seeFIG.4). Sequence740, which corresponds to a sequence of scrambled symbols430, can then be multiplied by the same random number scrambler symbol sequence420used in the Tx DSP102. The product of this multiplication operation is a set of descrambled symbols750that can be cross correlated with symbol sequence730, which can correspond to framer symbols410. In some implementations, the multiplication operation can be performed by multiplying symbol sequence730with scrambler symbol sequence420(instead of symbol sequence740) and subsequently cross correlating the product with symbol sequence740.

If the absolute square value of the determined cross correlation is greater than a threshold, the Rx DSP550saves the shift index of the window720, the resulting complex value of the cross correlation, and the absolute square value of the determined cross correlation as a new maximum cross correlation value. The Rx DSP550can then shift the slide window720by one symbol and repeat the operations performed by the Rx framer710until all the symbols have been processed. The absolute square values of the determined cross correlation at the different symbol positions/locations can then be aggregated so that information regarding the cross correlation across all the symbols in a frame or frame header920can be obtained.

FIG.10displays an example graph of the determined absolute square value of the cross correlation (y-axis) as a function of the symbol index (x-axis). As can be seen inFIG.10, the determined absolute square value can have several different values across the numerous symbols in a received signal, e.g., 18,000 symbols are shown inFIG.10. However, the absolute squared value of the cross correlation will generate a single strong peak at the position of the framer header at which the sliding window720fits exactly the framer header920indicating that the sliding window720is located at the starting position of the framer header920. The remaining absolute squared value values do not have a particular pattern, and, consequently, their cross-correlation values can average out to a small value (e.g., close to zero). If the length L of the frame header920is long enough, the chance of getting similar or stronger absolute square value anywhere other than the start of the frame header920is negligible.

In some implementations, after detecting the highest peak in the determined absolute square values of the cross correlation, a value of the highest peak can be compared to a threshold level to determine if the highest peak value satisfies (e.g., greater than) the threshold level. If the highest peak value satisfies the threshold level, the location (e.g., symbol index position) at which the highest peak value occurs is determined as a starting position of the frame header920. In some implementations, if the highest peak value satisfies the threshold level, the Rx DSP550may stop sliding the sliding window720as the starting position of the frame header920has likely been determined.

By performing the operations depicted inFIG.7, the Rx framer710can detect a peak in the determined absolute square values of the cross correlation operation and determine that the symbol index at which the peak is located corresponds to the beginning of a frame header, e.g., frame header920. By identifying the beginning of the frame header920, the Rx DSP550can synchronize processing of the received signal to the transmission of data by the transmitter100.

For example, based on information of the starting position of the frame header920, the Rx DSP550can then determine the position of all the following framer symbols910, pilot symbols820, and payload symbols810since the frame and payload structure is predefined. For example, the Rx DSP550can utilize information it possess according to the agreement between the receiver Rx502and transmitter100that specifies the distance or number of symbols, e.g., 31 symbols, separating each pilot symbol820. By knowing the location of the starting pilot symbol820, the Rx DSP550can determine the position of each pilot symbol being located every 32 symbols from the preceding pilot symbol. In some implementations, the location of the symbols relative to the starting point of the frame header920can also be provided in LUT.

Non-Linear Filtering

The foregoing description described, in part, how the beginning of a frame and, more generally, the location of a frame header in transmitted data can be estimated (hereinafter referred to as framer index estimation) when a single frame is being processed. In practice though, data transmissions can include multiple transmitted data frames. When multiple frames are transmitted, the Rx DSP550can perform additional processing to improve the accuracy of the framer index estimation.

To understand the issues when performing framer index estimation across multiple frames, consider a scenario in which the Rx DSP550begins processing symbols in a received data signal at an arbitrary position to search for the framer index. The Rx DSP550can perform the operations described above with respect toFIGS.5-7for multiple consecutive frames, e.g., 10 frames. The Rx DSP550can determine the framer index for 9 out of 10 frames correctly, e.g., at index position300, within a certain accuracy threshold (e.g., ±2 symbols). However, for one of the frames, an error due, for example to noise, can cause the Rx DSP550to determine the framer index at index position90,000. When the results are averaged across all 10 frames, the incorrectly determined framer index has a substantial effect on the calculated average value resulting in an incorrect shift of the average index position away from the correct index position, e.g., index position300.

To address such problems when performing framer index estimation across multiple frames, in some implementations, the Rx DSP550can first determine the positions of the framer indices across multiple frames. Then, using a non-linear filter, positions that are outliers, e.g., greater than a threshold distance away from the median or mode framer index position across the multiple frames, can be removed. The remaining index position values can be averaged and generally yield a framer index position that is more accurate then determining a framer index position based on a single frame.

An example of implementing non-linear filtering to improve the framer index estimate is shown inFIG.11. In the implementation depicted inFIG.11, the Rx DSP550can perform the operations described above with respect toFIGS.5-7to determine the estimated framer index position indices for multiple consecutive frames. The estimated indices can be placed horizontally and vertically in a grid-like manner and subtracted from each other to generate a Subtract Matrix1110as shown inFIG.11. Each element of the Subtract Matrix1110is compared against a subtraction threshold value th11120, and the result is stored in an Error Indicator Matrix1130. For example, an element from row i, column j of the Subtract Matrix1110can be compared to the subtraction threshold th11120and if the element is greater than the subtraction threshold th11120, a zero is placed in row i, column j of the Error Indicator Matrix1130. If an element from row i, column k of the Subtract Matrix1110is compared to a subtraction threshold th11120and the element is less than or equal to the subtraction threshold th11120, a one is placed in row i, column k of the Error Indicator Matrix1130.

Next, the Rx DSP550can determine the sum1140of each column of the Error Indicator Matrix1130. If the sum for a column is greater than a summation threshold th21150, the index corresponding to the sum of a particular column is added to the list of acceptable estimated indices. If the sum for a column is less than or equal to a summation threshold th21150, the index corresponding to the sum of a particular column is removed from the list of acceptable estimated indices.

After this step is completed for each column of Error Indicator Matrix1130, the estimated indices for multiple frames on the list of acceptable estimated indices can be averaged to determine the estimated framer index across the multiple frames. In some implementations, the summation1140operation can be performed by determining the sum1140of each row of the Error Indicator Matrix1130(instead of each column) and repeating the subsequent operations1150,1160,1170.

Lock Indicator

A framer index lock indicator is another feature that can improve framer index estimation. In general, when multiple frames are transmitted in a stream of data, the frame header position in the multiple frames is fixed. However, in processing the data at the receiver502, the Rx DSP550can not always determine the same position for the frame header position across the multiple frames. The ability to consistently and accurately estimate the framer index can be a performance indicator of a receiver.

FIG.12illustrates a flowchart of operations that can be performed by the Rx framer circuit710or the Rx DSP550to address the uncertainty in estimating the framer index across multiple frames. In one operation (1210), the estimated framer index from a frame being processed by the Rx framer710can be compared against a framer index previously determined and confirmed as being within a threshold of the actual location of the framer index as transmitted. This comparison can be repeated for multiple frames. The Rx framer710can determine the number of frames that have an estimated framer index within a certain threshold of the confirmed framer index (1220). Next, the Rx framer710can determine the ratio of the number of these frames that have an estimated framer index within a certain threshold of the confirmed framer index to the total number of frames that have been compared (1230). The ratio is indicative of the quality of the framer index estimation. For example, the higher the ratio the greater the quality of the framer index estimation for a set of frames. The lower the ratio, the lower the quality of the framer index estimation for a set of frames.

In some implementations, the Rx DSP550can randomly select a set of frames from received data to determine the quality of the framer index estimation. In some implementations, the Rx DSP550can determine the quality of the framer index estimation after a determined period of time or periodically after a certain number of frames have been processed, e.g., after every 200,000 frames. In some implementations, the Rx DSP550can determine the quality of the framer index estimation in response to a trigger condition, such as the reception of a new stream of data.

When the ratio of the number of these frames that have an estimated framer index within a certain threshold of the confirmed framer index to the total number of frames that have been compared is greater than or equal to a ratio threshold, the Rx framer710can generate a lock indicator signal or flag that indicates that a framer index estimation is being and can be reliably performed (1240). The lock indicator signal can be sent to other components of the Rx DSP550. In some implementations, certain operations such as frequency offset estimation, as described in more detail, are only performed after the lock indicator signal has been generated. In some implementations, certain processing operations or storing of received data are not permitted until the lock indicator signal is generated. In some implementations in which a lock indicator flag is used, the lock indicator flag can be set to a first value, e.g., 1, to indicate that the determined ratio satisfied the ratio threshold, and to a second value, e.g., 0, to indicate that the determined ratio did not satisfy the ratio threshold.

Quantization and Sign Bit Processing

In communication systems, symbols can be transmitted over signals, e.g., pulse symbols, and each symbol can encode several bits, e.g., 7 or 10 bits. Consequently, the cross-correlation operation described above can involve a computationally intensive process. As an example, if each symbol encodes 10 bits and96descrambled symbols750are generated, the cross-correlation operation can involve doing a 10-bit by 10-bit correlation for 96×96 symbols, which could consume substantial system and computational resources.

To save system and computational resources, each symbol can be further quantized by a quantizer1310, as shown inFIG.13. The quantizer1310can execute various suitable quantization methods to further quantize the symbols which would then reduce the computation involved in performing the cross-correlation operation.

In the example shown inFIG.13, a quantizer1310can be implemented immediately before the Rx framer circuit710. If the Rx framer circuit710is implemented after the IFFT630, then the quantizer1310can be implemented between the Rx framer circuit710and the IFFT630.

FIG.13also depicts one example of quantizing the symbols. For instance, inFIG.13, the quantizer1310can quantize the symbols to 3 levels (−1, 0, 1), although it can be configured to perform quantization for many different levels. The real and imaginary parts of a symbol are compared against the symbol threshold th. If the real or imaginary part is greater than the threshold th, the symbol can be quantized to 1. If the real or imaginary part is less than a negative threshold value −th, the symbol can be quantized to 1. If the real or imaginary part is equal to or between a positive threshold value th and a negative threshold value −th, the symbol can be quantized to 0.

In this manner, the 10-bit per symbol calculations have been reduced to 2-bit per symbol calculations. Furthermore, because the values for the quantization levels are −1, 0, and 1, simple and fast multiplication can be executed for cross correlation operations.

Frequency Offset Detection and Estimation

FIG.14depicts an example of frequency offset detection and estimation using the above-described systems and methods within the Rx DSP550. As shown inFIGS.13and14, after some processing by the Rx DSP550, e.g., by the IFFTs630, a stream of symbols can be quantized1310/1410through a N-level quantization operation as described above with respect to claim13. “N” can be a whole number and refers to the level of quantization. In the example shown inFIG.13, a three level (N=3) quantization operation is performed to quantize the symbols to −1, 0, or 1. The quantized symbols can then be processed by the Rx framer circuit710, which implements the receiver cross-correlation operations described with respect toFIG.7, to estimate the framer index (est_idx). As part of the cross-correlation operations, the Rx framer710can also determine a complex cross correlation value at the position of the estimated framer index (xCorr_max_val).

The confirm block1430represents buffering and storing operations performed by the Rx framer circuit710and a buffer coupled to the Rx framer circuit710. As explained above, framer index estimation can be performed over multiple frames. A confirm buffer can store data indicative of a fixed number of estimated framer indices. The Rx framer circuit710can perform filtering operations and generate a lock indicator signal (or set a lock indicator flag) indicative of the quality of the framer index estimation being performed across multiple frames.

For example, after a number of estimated framer indices have been determined, the Rx framer circuit710can perform the non-linear filtering operations, as described above with respect toFIG.11, to determine and confirm the likely location of the framer index. The Rx framer circuit710can generate a framer_idx_est signal identifying the confirmed likely location of the framer index and set a confirm flag to 1 to indicate that the framer index location identified by the framer_idx_est signal is confirmed. The Rx framer circuit710can also generate good_idx_flags flags that indicate which estimated framer indices in the confirm buffer are valid and which framer indices are outliers and were not included while determining the likely location of the confirmed framer index.

When the confirm flag is set to 1 (e.g., confirm_flag=1), the Rx framer circuit710can initiate check lock operation1440that include the operations described above with respect toFIG.12. For example, the Rx framer circuit710can determine the number of estimated framer indices that are close to the confirmed framer index within a certain threshold, and generate a lock indicator signal or set the lock indicator flag to a first value, e.g., 1.

When the lock is complete, e.g., the lock indicator flag is set to the first value, e.g., 1, the estimated framer index has a very high probability of being accurate. The Rx framer circuit710can then calculate the frequency offset from the complex value of the cross correlation xCorr_max_val at the position of the peak of the latest processed frame if the good_idx_flags corresponding to a frame being processed is 1. In particular, a look up table (LUT) including different angles for different cross correlation xCorr_max_val values (also described below with respect toFIG.17) can be created and stored in a storage unit, such as a database. The size of the LUT can depend on the cross correlation xCorr_max_val bitwidth. The frequency offset can then be calculated easily from the angle LUT. As an example,FIG.19shows that the frequency offset {circumflex over (f)}ocan be calculated from the angle of the cross correlation xCorr_max_val. In particular, the cross correlation xCorr_max_val at the header position for each carrier or subcarrier can be represented by the expression Axx/yyej2πfo×4fs. In this example, the interleaving period is 4. The frequency offset estimation can vary according to the sampling frequency fsand interleaving period. When multiple subcarriers are being processed (e.g., inFIG.19, data from four subcarriers sub1, sub2, sub3, and sub4is being processed), the complex cross correlation value of selected subcarriers that have good_idx_flags=1 at the position of the framer index for the latest frame can be summed and averaged to estimate the frequency offset {circumflex over (f)}o.

Half-Symbol Rectification

In communication systems, when a receiver receives a signal, the receiver can perform sampling, e.g., to digitize a received analog signal. Complications can arise though when processing symbols and there is a delay in transmission or reception of data. For instance, when symbols are received with a delay that is not a multiple integer factor of a symbol interval and only a single symbol is available during a sampling interval, a symbol can undesirably be sampled by a receiver system at a fractional (e.g., half) portion of the symbol interval. This can lead to incorrect sampling and can introduce errors with the processing of a received signal by the receiver.

A solution to the half symbol delay problem is shown inFIG.15. As shown inFIG.15, every two adjacent framer symbols are set identical and every two adjacent scrambler sequences are set identical along with interleaving scrambled and non-scrambled sequences for example every 2 symbols. The transmission of symbols inFIG.15is similar to the transmission of symbols described with respect toFIGS.3and4with a few differences.

InFIG.4, a number of symbols, e.g., 96, are selected as the framer symbols410. InFIG.15, half the number of symbols, e.g., 48, are selected, duplicated, and then arranged in pairs to yield another set of 96 framer symbols1510although these framer symbols1510consist of 48 pairs of symbols.

Like the scrambler symbols420inFIG.4, an equal number (96) of scrambler symbols1520having random values of 1 or −1 can be obtained and can be multiplied with each framer symbol. Half the number of scrambler symbols, e.g., 48, are selected, duplicated, and then arranged in pairs to yield another set of 96 scrambler symbols1520. As shown inFIG.15, a first processing path can include scrambled framer symbols1530that are the product of the multiplied scrambler symbols1520and pairs of framer symbols1510. The initial framer symbols1510can occupy a second processing path. An interleaving operation can then be performed such that the scrambled framer symbols1530from the first processing path are interleaved with framer symbols1510from the second processing path.

The interleaving can be implemented in various ways. In some cases, the framer symbols1510and the scrambled framer symbols1530can be concatenated one after another. In some cases, the framer symbols1510and the scrambled framer symbols1530can be designated to be located an even and odd index positions in the sequence of pilots. In some cases, a fixed number of framer symbols1510are placed first followed by the same number symbols of the scrambled framer symbols1530. This continues until all symbols from the two processing paths are consumed. The remaining transmitting steps such as the insertion of pilot symbols can be performed in the same way as described above with respect toFIGS.3and4.

The half symbol rectification solution is also useful to address intersymbol interference (ISI) that could arise from Differential Group Delay (DGD). By duplicating each framer symbol so that the framer symbols1510are arranged in pairs, as shown inFIG.15, effectively the interval for each symbol is doubled which can decrease issues arising from ISI or DGD.

In some implementations, to increase the DGD tolerance, the Tx DSP102can implement a course interleaver (as part of the Tx framer circuit320). The course interleaver can interleave the scrambler symbols1520with the framer symbols1510by alternating between two sequences every three symbols. The sequence of scrambler symbols1520is also held identical for every three consecutive symbols. By alternating between two sequences every three symbols instead of alternating after every symbol or pair of symbols, the DGD tolerance can increase although there can be less tolerance against phase-noise and frequency offset.

Sampling Rate Compensation

Data from one transmitter100can be transmitted to different receivers that can respectively operate with different components and consequently have different sampling rates to sample received signals. When the Rx framer circuit710is situated towards the beginning of the Rx DSP550and performs some of the earlier processing steps of the Rx DSP550, the framer index estimation by the Rx framer circuit710can be sensitive to any up-sampling if the sampling rate of the receiver502is too high. In practice, the sampling rate can often be higher than the symbol rate of transmitted signals. The higher sampling rate can cause misalignment between the number of samples and the actual number of symbols. To compensate for this misalignment, the Rx framer circuit710can apply a modified sliding window720to the interleaved symbols and a modified scrambler sequence to deinterleave the symbols.

As shown inFIG.16, the quantizer1310and Rx framer circuit710are located towards the beginning of the Rx DSP550and can receive a sampled and digitized signal from the ADC540. The quantizer130performs the quantization, e.g., 3-level quantization operation, as described above. In the configuration shown inFIG.16, the sampling rate of the receiver502can be higher than the symbol rate. For example, the received signal can have been upsampled by a factor of 4/3, i.e., 4 samples for every 3 symbols. The Rx DSP550can be aware of the upsampling factor and can receive information regarding the frame header. For instance, the Rx DSP550can know that a framer header920of 192 symbols is used, as shown in the example ofFIG.4. Typically, the Rx DSP550can use a sliding window720that has the same symbol size as the frame header920. However, because of the upsampling, using the same sized sliding window720can lead to errors in extracting the correct sequence of symbols.

Accordingly, to compensate for the upsampling, the Rx framer circuit710can resize the sliding window1620according to the upsampling factor. In this example, because the framer header920had a size of 192 symbols and the upsampling factor is 4/3, the modified size of the sliding window1620is 256 samples, which can be obtained by multiplying the previous sliding window size (or frame header size) by the upsampling factor (e.g., 192 symbols*(4 samples/3 symbols)=256 samples).

In addition to resizing the sliding window1620, the Rx framer circuit710also modifies the size of the scrambler symbol sequence1630according to the upsampling factor to accommodate the larger number of samples. In particular, the modified size of the scrambler symbol sequence1630can be obtained by multiplying the previous size of the scrambler symbol sequence420by the upsampling factor (e.g., 96 symbols*(4 samples/3 symbols)=128 samples based on the examples above and inFIGS.4and7).

As shown inFIG.16, the sliding window1620has a size of 256 samples. The sliding window1620can be used to process the received samples and deinterleave them. The Rx framer circuit710can perform the deinterleaving in a similar to the process described above with respect toFIG.7except that the Rx framer circuit710alternates every 3 symbols (or 4 samples) of the framer symbols and every 3 symbols of the scrambled framer symbols. The128deinterleaved symbols can then be multiplied with an equal-sized scrambler symbol sequence1630to yield 128 descrambled symbols1640which can then be used to perform a cross correlation operation and to determine frequency offset and the framer index similar to the processes described above with respect toFIGS.7,11,12, and14.

Systems with Digital Subcarriers

In optical communication systems with digital subcarriers, data transmission from a transmitter100to a receiver502can often be performed through multiple independent subcarriers. When multiple subcarriers are used, the framing of symbols and detection of frame header can be performed per subcarrier in the manner described above. Consequently, transmitters100and receivers502can have multiple copies of a framer index. However, it is desirable for data received through all the subcarriers to be synchronized. Although data across the multiple subcarriers can be synchronized by the transmitter100, it is possible that data received by the receiver502in the different subcarriers is compromised differently, e.g., data in different subcarriers can have different delay. In some implementations, the receiver502can include one or more circuits to synchronize multiple subchannels. This additional circuits can include a buffer, AND logic unit, and/or barrel shifter (not shown), and can be coupled to or incorporated within the Rx framer circuit710or the Rx DSP550.

Recall from the frequency offset estimation example shown inFIG.14that a symbol stream can be quantized1410and estimation1420, confirmation1430, check lock1440, and frequency offset estimation1450operations can be performed. InFIG.14, these operations were described with respect to a single carrier. When multiple subcarriers are being processed, these operations are performed for each subcarrier. For example,FIG.17shows multiple operation blocks17000-1700m(m+1 being the number of subcarriers) that include operations1420,1430, and1440as described above with respect toFIG.14(the quantization operation1410is not shown but can be performed before the subcarrier operations are executed). The respective stream of symbols from each subcarrier is referred to as “SC0” to “SCm” and each block17001-1700mrepresents the frequency offset estimation operations performed for data received from each subcarrier 0−m, respectively. These operations can generate a framer index (est_idx), a complex cross correlation value at the position of the estimated framer index (xCorr_max_val), a lock indicator flag, a framer_idx_est signal, a confirm flag, and a good_idx_flags flag for each subcarrier in a similar manner to the operations described with respect toFIG.14.

In the example shown inFIG.17, there are four subcarriers and m ranges from 0 to 3. Block1710represents the inter subcarrier operations and depicts the operations that are performed across the various subcarriers. A buffer can receive and store one or more of the framer index estimation (framer_est_idx), the complex cross correlation value at the position of the estimated framer index (xCorr_max_val), the lock indicator flag, the confirm flag, and the good_idx_flags flag for each subcarrier SC0, SC1, SC2, SC3. The size of this buffer can be selected to accommodate the maximum expected delay of any of the subcarriers. The buffer can provide the confirm flags from each of the subcarriers to an AND logic unit, which performs an AND operation1720.

The AND logic unit can output or set a set_BS_flag flag, which signals to the barrel shifter to perform a shifting operation1730(described in more detail below). The AND logic unit can set the set_BS_flag flag to zero if one or more of the subcarrier confirm flags has a zero value indicating that the framer index location associated with a particular subcarrier has not been confirmed (1720). The AND logic unit can set the set_BS_flag flag to one if all the subcarrier confirm flags have a one value indicating that the framer index location associated with a particular subcarrier has been confirmed (1720).

A barrel shifter can receive the output from the AND logic unit and is configured to perform a shift operation1730when the set_BS_flag flag has a value of one. The shift operation1730can compensate for delays experienced by the individual subcarriers, which would otherwise have an adverse impact on the synchronization of transmitted and received data.

In more detail, as data from the different subcarriers is processed and the positions of the frame headers920in the respective subcarriers is determined, the confirm flag and framer index estimation (framer_est_idx) data is written or stored in the buffer in the order the estimation is completed and confirm flags are set. The buffer can store order information indicative of the order in which each subcarrier's framer index estimation was completed and the positions of the frame headers920in the respective subcarriers. Due to, e.g., the delays that can occur in the transmission and reception of data in each subcarrier, the order in which each subcarrier's framer index estimation was completed can not be consistent with the order of data that was transmitted by the transmitter100. This results in the receiver502being unsynchronized with the transmitter100.

To address this delay problem, in response to receiving the set_BS_flag flag having a value of one, the barrel shifter can compensate the determined framer index estimation (framer_est_idx) for each subcarrier to make the framer index order the same or similar to the one implemented by the transmitter100(1730). In some implementations, to perform the compensation, the barrel shifter can instruct the buffer to output (e.g., when executing a read operation) the data regarding the frames in the order data was transmitted by the transmitter100. For example, the read operation can start from the position of the estimated frame index for the subcarrier that was the first subcarrier across which the transmitter100transmitted data. After the first subcarrier, the read operation can continue to read data from the position of the estimated frame index for the second subcarrier across which the transmitter100transmitted data. This process is continued sequentially until data for all the subcarriers is read.

InFIG.17, the check lock operation1440can start after all subcarriers SC0-SCmconfirmed on the estimated framer index for the corresponding subcarrier. The lock flag can be set to one or the lock indicator signal is generated when all the subcarriers SC0-SCmdeclare lock independently (indicating that a framer index estimation is being and can be reliably performed). The frequency offset estimation operation1450is executed (described in part with respect toFIGS.14and19) after receiving the lock indicator signal or in response to the lock flag being set to one. Since all subcarriers experience the same frequency offset, the estimated frequency offset from all subcarriers can be averaged to generate the final estimation of the frequency offset.

Chromatic Dispersion Estimation

Delays in different subcarriers can also be attributed to chromatic dispersion and noise. In particular, for communication systems with digital subcarriers, the relative offset between estimated framer indices for different subcarriers can be due to the effect of the chromatic dispersion and noise. In an ideal scenario with zero chromatic dispersion and negligible noise effect, the estimated framer indices across different subcarriers is the same. In a non-ideal scenario, the Rx framer circuit710can be used to estimate the chromatic dispersion. In some implementations, when the value of the chromatic dispersion is known, the relative delay between the framer indices of all the subcarriers SC0-SCmcan be estimated and used as an approximate value to compensate the framer index estimations determined by the Rx framer circuit710. When the value of the chromatic dispersion is not known, the chromatic dispersion (CD) effect and delay can be determined using Equations 1 and 2.
β2=4πcDλ2×10−21Equation 1:
delay=−4π×fc×β2×fb×μ  Equation 2:

fbis the subcarrier baud rate; fcis the center frequency of the subcarrier; is the laser wavelength in nanometers (nm); D is the dispersion in picoseconds (ps)/nm; c is the speed of light through fiber; and μ is the number of samples per symbol (up sampling factor).

FIG.18depicts operations performed to estimate the chromatic dispersion. As shown inFIG.18, an operation1810to estimate the framer index for multiple subcarriers SC0-SCMis performed in a similar manner as described above. Information from the estimated framer indices for the multiple subcarriers SC0-SCMcan then be used to calculate the delay and CD effect for the subcarriers in operations1820and1830using Equations 1 and 2. An example of these calculations is provided below.

For instance, in a communication system with eight (8) subcarriers centered at center frequencies fc=[−7, −5, −3, −1, 1, 3, 5, 7]×4e9 HZ, with baud rate fb=8e9 HZ, up sampling factor μ=4/3. If the chromatic dispersion D=10000 ps/nm is known, the relative delay between subcarriers in terms of number of samples is calculated as
delay=[11.9674,8.5481,5.1289,1.7096,−1.7096,−5.1289,−8.5481,−11.9674]
which can be rounded to
delay=[12,9,5,2,−2,−5,−9,−12]

Having the set of integer delays, the estimated CD is [12534, 13161, 12186, 14623, 14623, 12186, 13161, 12534] with average value equal to 13,126 ps/nm. The coefficients of the CDEQ equalizer circuits612in the Rx DSP550can then be tuned according to the estimated CD to compensate for the CD effect.

While this specification contains many specifics, these should not be construed as limitations on the scope of the disclosure or of what can be claimed, but rather as descriptions of features specific to particular implementations. Certain features that are described in this specification in the context of separate implementations can also be combined. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. Moreover, although features can be described above as acting in certain combinations and can even be claimed as such, one or more features from a claimed combination can, in some cases, be excised from the combination, and the claimed combination can be directed to a sub-combination or variation of a sub-combination. For example, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations.

Terms used herein and in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including, but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes, but is not limited to,” etc.).

Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims can contain usage of the phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to implementations containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations.

In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” is used, in general such a construction is intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together. The term “and/or” is also intended to be construed in this manner.

The use of the terms “first,” “second,” “third,” etc., are not necessarily used herein to connote a specific order or number of elements. Generally, the terms “first,” “second,” “third,” etc., are used to distinguish between different elements as generic identifiers. Absent a showing that the terms “first,” “second,” “third,” etc., connote a specific order, these terms should not be understood to connote a specific order. Furthermore, absence a showing that the terms “first,” “second,” “third,” etc., connote a specific number of elements, these terms should not be understood to connote a specific number of elements. For example, a first widget can be described as having a first side and a second widget can be described as having a second side. The use of the term “second side” with respect to the second widget can be to distinguish such side of the second widget from the “first side” of the first widget and not to connote that the second widget has two sides.