Patent ID: 12211551

DETAILED DESCRIPTION

Embodiments provide a semiconductor memory device capable of performing a write operation at a higher speed.

In general, according to one embodiment, a semiconductor memory device includes a memory string, a plurality of word lines, a sense amplifier unit, and a control circuit. The memory string includes a first select transistor having a first end connected to a bit line, a second select transistor having a first end connected to a source line, and a plurality of memory cell transistors connected in series between a second end of the first select transistor and a second end of the second select transistor. The plurality of word lines are connected to the gates of the plurality of memory cell transistors, respectively. The sense amplifier unit is connected to the bit line, and includes a latch circuit storing data to be written to the memory cell transistors, and a sense amplifier circuit capable of applying a voltage to the bit line based on the data stored in the latch circuit. The control circuit is configured to control voltages applied to the plurality of word lines, the bit line, and the source line. The control circuit executes a first pulse application operation, a precharge operation, and then a second pulse application operation when executing a write operation on a first memory cell transistor, which is one of the memory cell transistors. In the first pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a first voltage is applied to a first word line connected to a gate of the first memory cell transistor, and a second voltage lower than the first voltage is applied to the bit line, so that a threshold voltage of the first memory cell transistor is lowered. In the precharge operation, in a state in which the first select transistor and the second select transistor are turned on, a third voltage lower than the first voltage is applied to the first word line, and a fourth voltage higher than the third voltage is applied to the source line, so that the bit line is charged. In the second pulse application operation, in a state in which the bit line is set to a floating state by the sense amplifier unit by turning on the first select transistor and turning off the second select transistor, the first voltage is applied to the first word line.

Hereinafter, embodiments will be described with reference to the drawings. In order to facilitate understanding of the description, in each drawing, the same components are denoted by the same reference numerals as much as possible, and redundant descriptions are omitted.

1. FIRST EMBODIMENT

A semiconductor memory device according to a first embodiment will be described. The semiconductor memory device according to this embodiment is a non-volatile memory device configured as a NAND flash memory.

1.1. Configuration of Memory System

FIG.1illustrates a configuration example of a memory system including a semiconductor memory device2. This memory system includes a memory controller1and the semiconductor memory device2. The memory system inFIG.1can be connected to a host (not illustrated). The host is, for example, an electronic device such as a personal computer or a mobile terminal.

The memory controller1controls writing of data to the semiconductor memory device2based on a write request from the host. In addition, the memory controller1also controls reading of data from the semiconductor memory device2based on a read request from the host.

A chip enable signal/CE, a ready/busy signal/RB, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal/WE, read enable signals/RE and RE, a write protect signal/WP, data signals DQ<7:0>, and data strobe signals DQS and/DQS are transmitted and received between the memory controller1and the semiconductor memory device2.

The chip enable signal/CE is a signal for enabling the semiconductor memory device2. The ready/busy signal/RB is a signal indicating whether the semiconductor memory device2is in a ready state or a busy state. The “ready state” is a state in which an external command can be received. The “busy state” is a state in which an external command cannot be received. The command latch enable signal CLE is a signal indicating that the signal DQ<7:0> is a command. The address latch enable signal ALE is a signal indicating that the signal DQ<7:0> is an address. The write enable signal/WE is a signal for taking in the signal received by the semiconductor memory device2and is asserted each time the memory controller1transmits a command, an address, and data. The memory controller1instructs the semiconductor memory device2to take in the signals DQ<7:0> while the signal/WE is at an “L (Low)” level.

The read enable signals RE and/RE are signals for allowing the memory controller1to read data from the semiconductor memory device2. The read enable signals RE and/RE are used, for example, to control the operation timing of the semiconductor memory device2when the signals DQ<7:0> are output from the semiconductor memory device2. The write protect signal /WP is a signal for instructing the semiconductor memory device2to prohibit writing and erasing of data. The signals DQ<7:0> contain data transmitted and received between the semiconductor memory device2and the memory controller1and include commands, addresses, and data. The data strobe signals DQS and/DQS are signals for controlling input/output timings of the signals DQ<7:0>.

The memory controller1includes a RAM11, a processor12, a host interface13, an ECC circuit14, and a memory interface15. The RAM11, the processor12, the host interface13, the ECC circuit14, and the memory interface15are interconnected via an internal bus16.

The host interface13outputs requests received from the host, the user data (write data), or the like to the internal bus16. The host interface13also transmits the user data read from the semiconductor memory device2and responses from the processor12to the host.

The memory interface15controls the process of writing the user data and the like to the semiconductor memory device2and the process of reading the data from the semiconductor memory device2based on instructions from the processor12.

The processor12controls the memory controller1. The processor12is, for example, a CPU, an MPU, or the like. When receiving a request from the host via the host interface13, the processor12performs control based on the request. For example, the processor12instructs the memory interface15to write the user data and the parity to the semiconductor memory device2based on the request from the host. The processor12also instructs the memory interface15to read the user data and the parity from the semiconductor memory device2based on the request from the host.

The processor12determines a storage area (memory area) in the semiconductor memory device2for the user data accumulated in the RAM11. The user data is stored in the RAM11via the internal bus16. The processor12performs determination of the memory area for the data (page data) in units of a page, which is a unit of writing. The user data stored in one page of the semiconductor memory device2is hereinafter also referred to as “unit data”. The unit data is generally encoded and stored as a code word in the semiconductor memory device2. The encoding is optional in this embodiment. The memory controller1may store the unit data in the semiconductor memory device2without the encoding, butFIG.1illustrates a configuration in which the encoding is performed as a configuration example. When the memory controller1does not perform the encoding, the page data matches the unit data. In addition, one code word may be generated based on one unit data, or one code word may be generated based on divided data obtained by dividing the unit data. In addition, one code word may be generated by using a plurality of the unit data.

The processor12determines a memory area of the semiconductor memory device2as a writing destination for each unit data. A physical address is assigned to the memory area of the semiconductor memory device2. The processor12manages the memory area of the writing destination of the unit data by using the physical address. The processor12instructs the memory interface15to specify the determined memory area (physical address) and write the user data to the semiconductor memory device2. The processor12manages correspondence between the logical address of the user data (logical address managed by the host) and physical address. When the processor12receives the read request including the logical address from the host, the processor12identifies the physical address corresponding to the logical address, designates the physical address, and instructs the memory interface15to read the user data.

The ECC circuit14encodes the user data stored in the RAM11to generate code words. The ECC circuit14also decodes code words read from the semiconductor memory device2.

The RAM11temporarily stores the user data received from the host until the user data is stored in the semiconductor memory device2and temporarily stores the data read from the semiconductor memory device2until the data is transmitted to the host. The RAM11is a general-purpose memory such as an SRAM or a DRAM.

FIG.1illustrates a configuration example in which the memory controller1includes the ECC circuit14and the memory interface15, respectively. However, the ECC circuit14may be built into the memory interface15. In addition, the ECC circuit14may be incorporated in the semiconductor memory device2. The specific configuration and arrangement of each element illustrated inFIG.1are not particularly limited.

When receiving the write request from the host, the memory system ofFIG.1operates as follows. The processor12temporarily stores data that is a writing target to the RAM11. The processor12reads the data stored in the RAM11and inputs the data to the ECC circuit14. The ECC circuit14encodes the input data and inputs a code word to the memory interface15. The memory interface15writes the input code word to the semiconductor memory device2.

When receiving the read request from the host, the memory system ofFIG.1operates as follows. The memory interface15inputs the code word read from the semiconductor memory device2to the ECC circuit14. The ECC circuit14decodes the input code word and stores the decoded data in the RAM11. The processor12transmits the data stored in the RAM11to the host via the host interface13.

1.2 Configuration of Semiconductor Memory Device

As illustrated inFIG.2, the semiconductor memory device2includes two planes PL1and PL2, an input/output circuit21, a logic control circuit22, a sequencer41, a register42, a voltage generation circuit43, an input/output pad group31, a logic control pad group32, and a power supply input terminal group33.

The plane PL1has a memory cell array110, a sense amplifier120, and a row decoder130. The plane PL2has the same configuration as the plane PL1and includes a memory cell array210, a sense amplifier220, and a row decoder230. The number of planes provided in the semiconductor memory device2may be two as in this embodiment, but may be one, or may be three or more.

The sense amplifier120of the plane PL1is a circuit for adjusting the voltage applied to the bit lines of the memory cell array110, and reading the current or voltage of the bit lines, to convert the current or voltage into data. When reading data, the sense amplifier120acquires read data read from the memory cell transistors of the memory cell array110to the bit lines and transfers the acquired read data to the input/output circuit21. When writing data, the sense amplifier120transfers write data to the memory cell transistors of the memory cell array110via the bit lines.

The row decoder130of the plane PL1is a circuit configured as a switch group (not illustrated) for applying a voltage to each word line of the memory cell array110. The row decoder130receives a block address and a row address from the register42, selects a corresponding block based on the block address, and selects a corresponding word line based on the row address. The row decoder130switches between opening and closing of the switch group so that a voltage from the voltage generation circuit43is applied to the selected word line.

The memory cell array210of the plane PL2has the same configuration as the memory cell array110of the plane PL1, the sense amplifier220of the plane PL2has the same configuration as the sense amplifier120of the plane PL1, and the row decoder230of the plane PL2has the same configuration as the row decoder130of plane PL1.

The memory cell arrays110and210are parts for storing data. Each of the memory cell arrays110and210includes a plurality of the memory cell transistors associated with the word lines and the bit lines.

The input/output circuit21transmits and receives the signals DQ<7:0> and data strobe signals DQS and/DQS to and from the memory controller1. The input/output circuit21transfers the command and the address in the signals DQ<7:0> to the register42. The input/output circuit21also transmits and receives the write data and the read data to and from the sense amplifiers120and220.

The logic control circuit22receives the chip enable signal/CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal/WE, the read enable signals/RE and RE, and the write protect signal/WP from the memory controller1. The logic control circuit22also transfers the ready/busy signal/RB to the memory controller1to notify the state of the semiconductor memory device2to the outside.

Both the input/output circuit21and the logic control circuit22are circuits for inputting/outputting signals to/from the memory controller1. The input/output circuit21and the logic control circuit22are hereinafter also referred to as an “interface circuit20”. The interface circuit20can be regarded as a part to and from which signals including the control signals relating to the operations of the planes PL1and PL2are input and output. The control signal is, for example, the command and the address in the signal DQ<7:0> input to the input/output circuit21, the command latch enable signal CLE input to the logic control circuit22, or the like.

The sequencer41controls the operation of each of the components such as the memory cell arrays110and210based on the control signal input from the memory controller1to the interface circuit20. In this embodiment, the sequencer41corresponds to the control circuit. The sequencer41and the logic control circuit22may also be used as the control circuit of this embodiment.

The register42temporarily stores the commands and the addresses. The command for instructing the write operations, the erasing operations, or the like of the planes PL1and PL2and the address corresponding to the command are input from the memory controller1to the input/output circuit21, and after that, are transferred from the input/output circuit21to the register42and stored in the register42.

The register42also stores status information indicating the state of the semiconductor memory device2. The sequencer41updates the status information stored in the register42. The status information is output from the input/output circuit21to the memory controller1as a status signal in response to a request from the memory controller1.

The voltage generation circuit43generates the voltage required for each of the write operation, the read operation, and the erasing operation of the data in the memory cell arrays110and210based on the instructions from the sequencer41. Such voltages include, for example, the voltages applied to the word lines and the bit lines, which will be described later.

The input/output pad group31is a portion provided with a plurality of terminals (pads) for transmitting and receiving the respective signals between the memory controller1and the input/output circuit21. A terminal is separately provided for each of the signals DQ<7:0> and the data strobe signals DQS and/DQS.

The logic control pad group32is a portion provided with a plurality of terminals (pads) for transmitting and receiving the respective signals between the memory controller1and the logic control circuit22. The terminals correspond respectively to the chip enable signal/CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal /WE, the read enable signals/RE and RE, the write protect signal/WP, and the ready-busy/signal /RB.

The power supply input terminal group33is provided with a plurality of terminals for receiving voltages required for the operation of the semiconductor memory device2. Voltages supplied to the respective terminals include power supply voltages Vcc, VccQ, and Vpp and a ground voltage Vss.

The power supply voltage Vcc is a circuit power supply voltage externally supplied as an operating power supply and is a voltage of, for example, about 3.3 V. The power supply voltage VccQ is, for example, a voltage of 1.2 V. The power supply voltage VccQ is a voltage used for signal transmission/reception between the memory controller1and the semiconductor memory device2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12 V.

1.3 Configuration of Memory Cell Array

FIG.3illustrates the configuration of the memory cell array110provided in the plane PL1. The memory cell array110is configured with a plurality of blocks BLK, but only one block BLK among the plurality of blocks BLK is illustrated inFIG.3. The configuration of other blocks BLK provided in the memory cell array110is the same as that illustrated inFIG.3.

As illustrated inFIG.3, the block BLK includes, for example, four string units SU (SU0to SU3). Each string unit SU also includes a plurality of the memory strings MS. Thus, the memory cell array110has the plurality of memory strings MS, and each memory string MS belongs to one of the plurality of string units SU. The number of string units SU may differ from the example ofFIG.3.

Each memory string MS includes, for example, eight memory cell transistors MT (MT0to MT7), a drain-side select transistor ST1, and source-side select transistors ST2and ST3and has a configuration in which these components are connected in series. In this embodiment, the drain-side select transistor ST1corresponds to the first select transistor, and the source-side select transistors ST2and ST3correspond to the second select transistors.

It is noted that the number of memory cell transistors MT provided in each memory string MS is not limited to eight, and may be, for example, 32, 48, 64, or 96. In addition, in order to improve the cutoff characteristics, each or any one of the drain-side select transistor ST1and the source-side select transistors ST2and ST3may be configured with a plurality of transistors instead of a single transistor. In addition, the configuration in which the source-side select transistor ST3is omitted may be used. Furthermore, a dummy cell transistor may be provided between the memory cell transistor MT and the drain-side select transistor ST1and between the memory cell transistor MT and the source-side select transistor ST2.

The respective memory cell transistors MT are connected in series between the drain-side select transistor ST1and to the source-side select transistor ST2. The memory cell transistor MT7on one end side is connected to the source of the drain-side select transistor ST1, and the memory cell transistor MT0on the other end side is connected to the drain of the source-side select transistor ST2.

The memory cell array110is provided with the m bit lines BL (BL0, BL1, . . . , and BL(m−1)). “m” is an integer representing the number of memory strings MS provided in one string unit SU.

Among the plurality of memory strings MS, the memory strings MS belonging to the same string unit SU are connected to the different bit lines BL via the drain-side select transistors ST1. The gates of the respective drain-side select transistors ST1belonging to the same string unit SU are commonly connected to the gate lines SGD0to SGD3, which are separately provided for each string unit SU. For example, the gates of the respective drain-side select transistors ST1belonging to the string unit SU0are commonly connected to the gate line SGD0provided corresponding to the string unit SU0.

The gates of the respective drain-side select transistors ST1belonging to other string units SU1and the like are similarly commonly connected to the gate line provided corresponding to the string unit SU. It is noted that the gate line SGD0is a gate line provided corresponding to the string unit SU0, the gate line SGD1is a gate line provided corresponding to the string unit SU1, the gate line SGD2is a gate line provided corresponding to the string unit SU2, and the gate line SGD3is a gate line provided corresponding to the string unit SU3.

In each string unit SU, the source of the source-side select transistor ST2is connected to the drain of the source-side select transistor ST3. The source of the source-side select transistor ST3is connected to the source line SL. The source line SL is commonly connected to each of the sources of the plurality of source-side select transistors ST2provided in the block BLK. In this manner, the plurality of memory strings MS are commonly connected to the same source line SL via the respective source-side select transistors ST2and ST3.

The gates of the source-side select transistors ST2provided in the block BLK are commonly connected to the same gate line SGS. Similarly, the gates of the source-side select transistors ST3provided in the block BLK are commonly connected to the same gate line SGSB.

The gates of the memory cell transistors MT0provided in the same block BLK are commonly connected to a word line WL0. The gates of the memory cell transistors MT1provided in the same block BLK are commonly connected to a word line WL1. The same applies to other memory cell transistors MT. That is, the gates of the memory cell transistors MT0to MT7are commonly connected to the word lines WL (one of WL0to WL7) respectively correspondingly provided.

A set of a plurality of the memory cell transistors MT connected to a common word line WL in one string unit SU is referred to as, for example, a cell unit CU. A set of 1-bit data stored in each memory cell transistor MT of one cell unit CU is referred to as a “page”. In this embodiment, 1-bit data is stored in each memory cell transistor MT. Therefore, data for one page is stored in each cell unit CU. Alternatively, data for a plurality of pages may be stored in each cell unit CU.

1.4 Structure of Memory Cell Array

FIG.4is an example of a cross-sectional structure of the memory cell array110and illustrates an extracted structure corresponding to one block BLK.

In the cross-sectional view ofFIG.4, some components such as an insulating layer (interlayer insulating film), wirings, and contacts are appropriately omitted in order to facilitate viewing of the drawings. In addition, the x direction illustrated inFIG.4corresponds to the extension direction of the bit line BL. The y direction corresponds to the extension direction of the word line WL. The z direction corresponds to the direction perpendicular to the upper surface of the semiconductor substrate300on which the semiconductor memory device2is formed.

As illustrated inFIG.4, the region of the semiconductor substrate300where the memory cell array110is formed includes, for example, a P-type well region320, an insulator layer321, four conductive layers322, eight conductive layers323, four conductive layers324, a plurality of memory pillars MP, conductive layers325,326, and328, and contacts327and329. It is noted that an insulating layer (not illustrated) is formed between conductive layers.

The P-type well region320is provided near the upper surface of the semiconductor substrate300. The P-type well region320is used as the source line SL. The P-type well region320includes an n+ impurity diffusion region NP and a p+ impurity diffusion region PP spaced apart from each other. Each of the n+ impurity diffusion region NP and the p+ impurity diffusion region PP is provided near the upper surface of the P-type well region320.

The insulator layer321is provided on the P-type well region320. The four conductive layers322stacked apart from each other are provided on the insulator layer321. The eight conductive layers323stacked apart from each other are provided above the uppermost conductive layer322. The four conductive layers324stacked apart from each other are provided above the conductive layer323. The conductive layer325is provided above the uppermost conductive layer324.

Each conductive layer322has a structure extending along an xy plane. The lowermost conductive layer322is used as the gate line SGSB. The three conductive layers322provided above the lowermost conductive layer322are used as the gate lines SGS. InFIG.4, the three source-side select transistors ST2and the one source-side select transistor ST3are provided. The same number of conductive layers322as the total number of source-side select transistors ST2and the source-side select transistors ST3are provided.

The conductive layer323has a structure extending along the xy plane. The eight conductive layers323are used as the word lines WL0, WL1, WL2, . . . , and WL7in this order from the lower layer.

The conductive layer324has a structure extending in the y direction. The conductive layer324is used as a select gate line SGD. In the example ofFIG.4, three drain-side select transistors ST1are provided. The same number of conductive layers324as the total number of drain-side select transistors ST1are provided.

The conductive layer325has a structure extending in the x direction. The conductive layer325is used as the bit line BL. The plurality of conductive layers325are arranged in the y direction.

Each memory pillar MP corresponds to one memory string MS. The memory pillars MP are arranged in each of the x direction and the y direction. As illustrated inFIG.4, each memory pillar MP arranged in the x direction is connected to the same conductive layer325(that is, the bit line BL).

Each memory pillar MP arranged in the y direction is connected to different conductive layers325(that is, the bit lines BL). As illustrated inFIG.4, these groups of the memory pillars MP arranged in the y direction belong to the same string unit SU.

Each memory pillar MP penetrates the insulator layer321, the four conductive layers322, the eight conductive layers323, and the four conductive layers324. All of the portions of the memory pillar MP intersecting the above conductive layers are parts of transistors. Among the plurality of transistors, those located at the portions intersecting the conductive layers322function as the source-side select transistors ST2and ST3. Among the plurality of transistors, those located at portions intersecting the conductive layers323function as memory cell transistors MT (MT0to MT7). Among the plurality of transistors, the one at the portion intersecting the conductive layers324functions as the drain-side select transistor ST1.

Each memory pillar MP includes a semiconductor film330and a ferroelectric film331. The semiconductor film330is formed, for example, in a columnar shape extending in the z direction. The ferroelectric film331is a film made of a ferroelectric material and covers the outer peripheral surface of the semiconductor film330.

FIG.5is a view illustrating a cross-sectional structure taken along line V-V inFIG.4and illustrates an example of the cross-sectional structure of the memory pillar MP in a layer including the conductive layer323.

As illustrated inFIG.5, in the layer including the conductive layer323, the semiconductor film330is provided, for example, in the central portion of the memory pillar MP. The ferroelectric film331covers the entire outer peripheral surface of the semiconductor film330. The conductive layer323functioning as a word line WL covers the entire outer peripheral surface of the ferroelectric film331. It is noted that an insulating film may be buried in a central part of the semiconductor film330.

As illustrated inFIG.4, the lower end of the semiconductor film330provided in the memory pillar MP is in contact with the P-type well region320. The upper portion of the semiconductor film330is in contact with the conductive layer325. It is noted that the upper portion of the semiconductor film330and the conductive layer325may be electrically connected through a contact, a wiring, or the like.

The semiconductor film330is made of, for example, undoped poly silicon. The semiconductor film330is a portion functioning as a channel of the memory string MS. The ferroelectric film331is made of a ferroelectric material such as hafnium oxide (HfO2). The ferroelectric film331functions as a block insulating film of the transistor. The ferroelectric film331changes the direction and magnitude of the spontaneous polarization according to the magnitude of the voltage applied to the conductive layer323(that is, word line WL). The data is stored in the memory cell transistor MT by utilizing such polarization reversal.

The conductive layer326is located, for example, in a wiring layer between the uppermost conductive layer324and the conductive layer325, and is used as a CELSRC. The CELSRC is used as a wiring for changing the voltage of the P-type well region320. The conductive layer326is electrically connected to the n+ impurity diffusion region NP via the contact327.

The conductive layer328is located, for example, in a wiring layer between the uppermost conductive layer324and the conductive layer325and is used as a CPWELL. The CPWELL is used as a wiring for changing the voltage of the P-type well region320. The conductive layer328is electrically connected to the p+ impurity diffusion region PP via the contact329.

The lowermost conductive layer322and the insulator layer321extend to the vicinity of the n+ impurity diffusion region NP. Accordingly, when the source-side select transistor ST3is turned on, the memory cell transistor MT0and the n+ impurity diffusion region NP are electrically connected by the channel formed near the upper surface of the P-type well region320.

1.5 Configuration of Sense Amplifier

FIG.6illustrates a configuration example of the sense amplifier120. The sense amplifier120includes a plurality of sense amplifier units SAU respectively associated with a plurality of the bit lines BL.FIG.6illustrates a detailed circuit configuration of one of the sense amplifier units SAU.

As illustrated inFIG.6, the sense amplifier unit SAU includes a sense amplifier circuit SA and latch circuits SDL and XDL. The sense amplifier circuit SA and the latch circuits SDL and XDL are connected via a bus LBUS so that data can be transmitted and received by each other.

For example, in a read operation, the sense amplifier circuit SA senses data read to the corresponding bit line BL and determines whether the read data is “0” or “1”. The sense amplifier circuit SA includes, for example, a transistor TR1which is a p-channel MOS transistor, transistors TR2to TR9which are n-channel MOS transistors, and a capacitor C10.

One end of the transistor TR1is connected to a power supply line, and the other end of the transistor TR1is connected to the transistor TR2. A gate of the transistor TR1is connected to a node INV in the latch circuit SDL. One end of the transistor TR2is connected to the transistor TR1, and the other end of the transistor TR2is connected to the node COM. A signal BLX is input to the gate of the transistor TR2. One end of the transistor TR3is connected to the node COM, and the other end of the transistor TR3is connected to the transistor TR4. A signal BLC is input to the gate of the transistor TR3. The transistor TR4is a high voltage MOS transistor. One end of the transistor TR4is connected to the transistor TR3. The other end of the transistor TR4is connected to the corresponding bit line BL. A signal BLS is input to the gate of the transistor TR4.

One end of the transistor TR5is connected to the node COM, and the other end of the transistor TR5is connected to a node SRC. The gate of the transistor TR5is connected to the node INV. One end of the transistor TR6is connected between the transistors TR1and TR2, and the other end of the transistor TR6is connected to a node SEN. A signal HLL is input to the gate of the transistor TR6. One end of the transistor TR7is connected to the node SEN, and the other end of the transistor TR7is connected to a node COM. A signal XXL is input to the gate of the transistor TR7.

One end of the transistor TR8is grounded, and the other end of the transistor TR8is connected to the transistor TR9. The gate of the transistor TR8is connected to the node SEN. One end of the transistor TR9is connected to the transistor TR8, and the other end of the transistor TR9is connected to the bus LBUS. A signal STB is input to the gate of the transistor TR9. One end of the capacitor C10is connected to the node SEN. A clock CLK is input to the other end of the capacitor C10.

The signals BLX, BLC, BLS, HLL, XXL, and STB are generated by, for example, the sequencer41. For example, Vdd which is an internal power supply voltage of the semiconductor memory device2is applied to the power supply line connected to one end of the transistor TR1, and for example, Vss which is the ground voltage of the semiconductor memory device2is applied to the node SRC. The internal power supply voltage Vdd is, for example, 1.5 V, and the ground voltage Vss is, for example, 0 V.

The latch circuits SDL and XDL temporarily store read data. The latch circuit XDL is connected to the input/output circuit21and used for inputting and outputting data between the sense amplifier unit SAU and the input/output circuit21.

The latch circuit SDL includes, for example, inverters IV11and IV12and transistors TR13and TR14which are n-channel MOS transistors. The input node of the inverter IV11is connected to a node LAT. The output node of the inverter IV11is connected to the node INV. The input node of the inverter IV12is connected to the node INV. The output node of the inverter IV12is connected to the node LAT. One end of the transistor TR13is connected to the node INV, and the other end of the transistor TR13is connected to the bus LBUS. A signal STI is input to the gate of the transistor TR13. One end of the transistor TR14is connected to the node LAT, and the other end of the transistor TR14is connected to the bus LBUS. A signal STL is input to the gate of the transistor TR14. For example, the data stored at the node LAT corresponds to the data stored in the latch circuit SDL. In addition, the data stored at the node INV corresponds to the inverted data of the data stored at the node LAT. Since a circuit configuration of the latch circuit XDL is the same as that of the latch circuit SDL, for example, description thereof will be omitted.

1.6 Configuration of Memory Cell Transistors

In the semiconductor memory device2according to this embodiment, the memory cell transistor MT is a so-called ferroelectric field-effect transistor (FeFET) storing data by spontaneous polarization of the ferroelectric film331.

Characteristics of the memory cell transistor MT will be described with reference toFIGS.7and8.FIG.7is a diagram illustrating a relationship between the applied voltage and the polarizability in the memory cell transistor MT. VG illustrated on the horizontal axis ofFIG.7is the voltage applied between the channel (semiconductor film330) of the memory cell transistor MT and the word line WL (conductor layer323). The vertical axis inFIG.7is the polarizability of the ferroelectric film331.FIGS.8A and8Bare cross-sectional views schematically illustrating the state of the memory cell transistor MT, specifically, the state of the spontaneous polarization of the ferroelectric film331and the like.

In the state indicated by P1inFIG.7, the voltage applied to the memory cell transistor MT is 0 V, and the ferroelectric film331is spontaneously polarized in the positive direction.FIG.8Aillustrates the state of the memory cell transistor MT at P1. In this state, positive charges are induced on the surface of the ferroelectric film331on the semiconductor film330side. On the surface of the semiconductor film330on the ferroelectric film331side, a state where the channels are connected as indicated by reference numeral “330A” by an electric field from the ferroelectric film331occurs. Accordingly, the memory cell transistor MT is turned on.

When the applied voltage is increased from the state indicated by P1to the negative side (that is, when the voltage applied to the word line WL is lowered), the polarizability of the ferroelectric film331changes in the direction of an arrow AR11along the hysteresis inFIG.7. When the applied voltage reaches V1, polarization reversal occurs, and the polarizability of the ferroelectric film331is in a state of being reversed in the negative direction. After that, after passing the voltage value at which the absolute value of the polarizability reaches the maximum point, when the applied voltage is changed to the positive side (that is, when the voltage applied to the word line WL is increased), the absolute value of the polarizability of the ferroelectric film331is slightly decreased in the direction of an arrow AR12along the hysteresis inFIG.7. When the applied voltage becomes 0 V, the state illustrated by P2is obtained, and the polarization state of P2is maintained even in a state where the voltage from the outside is 0 V.

In the state indicated by P2, the voltage applied to the memory cell transistor MT is 0 V, and the ferroelectric film331is spontaneously polarized in the negative direction. That is, as described above, the polarization reversal occurs from the state indicated by P1.FIG.8Billustrates the state of the memory cell transistor MT at P2. In this state, negative charges are induced on the surface of the ferroelectric film331on the semiconductor film330side. On the surface of the semiconductor film330on the ferroelectric film331side, the channel is cut off by the electric field from the ferroelectric film331. Accordingly, the memory cell transistor MT is turned off.

When the applied voltage is increased from the state indicated by P2to the positive side (that is, when the voltage applied to the word line WL is further increased), the polarizability of the ferroelectric film331is changed in the direction of an arrow AR21along the hysteresis inFIG.7. When the applied voltage becomes V2, the polarization reversal occurs again, and the polarizability of the ferroelectric film331is in a state of being reversed in the positive direction. After that, after passing the voltage value at which the absolute value of the polarizability reaches the maximum point, when the applied voltage is changed to the negative side (that is, when the voltage applied to the word line WL is lowered), the absolute value of the polarizability of the ferroelectric film331is slightly decreased in the direction of an arrow AR22along the hysteresis inFIG.7. When the applied voltage becomes 0 V, the state is returned to the state illustrated by P1, and the polarization state of P1is maintained even in a state where the voltage from the outside is 0 V.

As described above, in the memory cell transistor MT, by changing the voltage applied via the word line WL, the state where the ferroelectric film331is spontaneously polarized in the positive direction as illustrated inFIG.8Aand the state where the ferroelectric film331is spontaneously polarized in the negative direction as illustrated inFIG.8Bcan be alternately switched.

As illustrated inFIG.8A, in a state where the ferroelectric film331is spontaneously polarized in the positive direction, when the applied voltage is changed in the negative direction (that is, when the voltage applied to the word line WL is lowered), the channel is in a state of being cut off in the middle, and the memory cell transistor MT is turned off. That is, in a state where the ferroelectric film331is spontaneously polarized in the positive direction, a threshold voltage Vth of the memory cell transistor MT becomes a negative value.

On the other hand, in a state where the ferroelectric film331is spontaneously polarized in the negative direction as illustrated inFIG.8B, when the applied voltage is changed in the positive direction (that is, when the voltage applied to the word line WL is increased), the channel is in a state of being connected in the middle, and the memory cell transistor MT is turned on. That is, in a state where the ferroelectric film331is spontaneously polarized in the positive direction, the threshold voltage of the memory cell transistor MT becomes a positive value.

As described above, the memory cell transistor MT of this embodiment is configured such that the direction of the spontaneous polarization is changed according to the applied voltage between the word line WL and the channel, and the threshold voltage is also changed accordingly. Specifically, the memory cell transistor MT has a configuration in which, when a voltage is applied such that the voltage of the word line WL is higher than the voltage of the channel and exceeds the voltage that causes the polarization reversal to occur, the threshold voltage is lowered, and when a voltage is applied such that the voltage of the word line WL is lower than the voltage of the channel and exceeds the voltage that causes the polarization reversal to occur, the threshold voltage is raised.

FIG.9Aillustrates a correspondence relationship between the threshold voltage Vth (horizontal axis) and the probability that a memory cell transistor MT (vertical axis) has the threshold voltage Vth of the horizontal axis. When an SLC (Single Level Cell) method is adopted as the storage method of the memory cell transistors MT, the threshold voltages of the plurality of memory cell transistors MT form two distributions as illustrated inFIG.9A. These two threshold voltage distributions (corresponding to write states) are referred to as a Pr state and an Er state in ascending order of the threshold voltages.

The Pr state is the distribution of the threshold voltage Vth when the ferroelectric film331is spontaneously polarized in the positive direction as illustrated inFIG.8A. The Pr state is a state in which data is written, and for example, the data of “0” is assigned.

The Er state corresponds to the distribution of the threshold voltage Vth when the ferroelectric film331is spontaneously polarized in the negative direction as illustrated inFIG.8B. The Er state is a state in which data is erased, and for example, the data of “1” is assigned. When the erasing operation is performed, the threshold voltage distribution of the memory cell transistors MT changes from the Pr state to the Er state.

1.7 Write Operation

In the semiconductor memory device2of this embodiment, when among the plurality of bit lines BL0to BL(m−1) illustrated inFIG.3, the bit lines BL0, BL2, BL4, . . . are set as even-numbered bit lines and the bit lines BL1, BL3, BLS, . . . are set as odd-numbered bit lines, the read operation and the write operation are executed as divided into the even-numbered bit lines and the odd-numbered bit lines. In the following, the case of performing the writing to the memory cell transistors MT corresponding to the bit lines BL2and BL4will be described as an example.

FIGS.10and12to16are views illustrating simplifications of the memory strings MS11and MS12corresponding to the bit line BL2.FIG.11is a simplified representation of the memory strings MS21and MS22corresponding to the bit line BL4. InFIGS.10to16, among the transistors ST1, ST2, and ST3, those that are in the off state are marked with a cross. Characters such as “Vss”, “Vsgd”, “Vpass”, and “Vpgm” surrounded by rectangular frames inFIGS.10to16represent the voltage of each component.FIGS.10to16illustrate the voltages of each component when the write operation is performed. The process of adjusting the voltage of each component illustrated inFIGS.10to16is realized by allowing the sequencer41to control the sense amplifier120, the row decoder130, the voltage generation circuit43, and the like.

The write operation in this embodiment is selectively performed on a specific page. InFIGS.10to16, the memory cell transistor MT that is a writing target is surrounded by a one-dot dashed line. That is,FIGS.10to16illustrate the case where the string unit SU0is selected as a target of the write operation and the string unit SU1is not selected as a target of the write operation.

Hereinafter, the string unit SU0selected as a target of the write operation is referred to as the “selected string unit SU0”, and the string unit SU1not selected as a target of the write operation is referred to as the “non-selected string unit SU1”. In addition, in the selected string unit SU0, the memory cell transistor MT that is a writing target is referred to as a “selected memory cell transistor sMT”, and the word line WL connected to the selected memory cell transistor sMT is also referred to as a “selected word line sWL”. In this embodiment, the selected word line sWL corresponds to the first word line. In addition, in the selected string unit SU0, the memory cell transistors other than the selected memory cell transistor sMT are referred to as “non-selected memory cell transistors uMT”, and the word lines WL connected to the non-selected memory cell transistors uMT are also referred to as “non-selected word lines uWL”. In this embodiment, the selected memory cell transistor sMT corresponds to the first memory cell transistor.

It is noted that the selected memory cell transistor sMT also includes memory cell transistors MT of other memory strings MS belonging to the string unit SU0in addition to those illustrated inFIGS.10to16.

FIGS.17A to17Jare timing charts illustrating voltage transitions of various components of the memory cell array110when such a write operation is performed. InFIGS.17A to17J, “SGD0” indicates a transition in voltage on the gate line SGD0, and “SGD1” indicates a transition in voltage on the gate line SGD1. “sWL” indicates a transition in voltage on the selected word line sWL, and “uWL” indicates a transition in voltage on the non-selected word line uWL. “SGS and SGSB” indicate a transition in voltage on the gate lines SGS and SGSB, and “SEN” indicates a transition in voltage on the node SEN of the sense amplifier circuit SA. “BL2” indicates a transition in voltage on the bit line BL2, and “BL4” indicates a transition in voltage on the bit line BL4. “BL1, BL3, and BL5” indicate a transition in voltage on the bit lines BL1, BL3, and BL5, and “SL” indicates a transition in voltage on the source line SL.

FIGS.18A to18Eare timing charts illustrating transitions of the signals BLC, BLX, HLL, XXL, and STB applied to the sense amplifier120when the above write operation is performed.

As illustrated inFIGS.17A to17JandFIGS.18A to18E, in the write operation of this embodiment, the first program operation and the second program operation are performed in this order. The first program operation is an operation of writing data to the memory cell array110. In this embodiment, the first program operation corresponds to a first pulse application operation. The second program operation is an operation of rewriting data when the data cannot be written sufficiently by the first program operation. The second program operation may be repeated.

1.7.1 First Program Operation

InFIGS.17A to17JandFIGS.18A to18E, the time when the write operation is started, in other words, the time when the first program operation is started is indicated by “t10”. As illustrated inFIGS.17A to17J, the ground voltage Vss is applied to each part of the memory cell array110at a time before time t10. In addition, as illustrated inFIGS.18A to18E, each signal applied to the sense amplifier120is set to a low level.

When the first program operation is started at time t10, the write data is transferred from the input/output circuit21illustrated inFIG.2to the sense amplifier120. Accordingly, the data of “1” or the data of “0” is stored in the latch circuit SDL of the sense amplifier120illustrated inFIG.6. When the data of “0” is stored in the latch circuit SDL, the node LAT is set to a low level and the node INV is set to a high level. Therefore, the transistor TR1is turned off, and the transistor TR5is turned on. Meanwhile, when the data of “1” is stored in the latch circuit SDL, the node LAT is set to a high level, and the node INV is set to a low level. Therefore, the transistor TR1is turned on, and the transistor TR5is turned off.

As illustrated inFIGS.18A and18B, when the first program operation is started at time t10, the signals BLC and BLX are set to a high level. For this reason, the transistors TR2and TR3illustrated inFIG.6are turned on. At this time, when the data of “0” is stored in the latch circuit SDL, since the transistor TR1is turned off and the transistor TR5is turned on as described above, the transistor TR4is turned on, so that the voltage applied to the node SRC, that is, the ground voltage Vss is applied to the bit line BL. Therefore, for example, when writing the data of “0” to the selected memory cell transistor sMT corresponding to the bit line BL2, the ground voltage Vss is applied to the bit line BL2as illustrated inFIGS.10and17G. In this embodiment, the ground voltage Vss applied to the bit line BL2in the first program operation corresponds to the second voltage.

Meanwhile, when the data of “1” is stored in the latch circuit SDL illustrated inFIG.6, since the transistor TR1is turned on and the transistor TR5is turned off as described above, the transistor TR4is turned on, so that the internal power supply voltage Vdd is applied to the bit line BL. Therefore, for example, when writing the data of “1” to the selected memory cell transistor sMT corresponding to the bit line BL4, the internal power supply voltage Vdd is applied to the bit line BL4as illustrated inFIGS.11and17H.

As illustrated inFIG.17E, when the first program operation is started at time t10, the gate lines SGS and SGSB are maintained to be in a state where the ground voltage Vss is applied. Accordingly, as illustrated inFIGS.10and11, the respective source-side select transistors ST2and ST3of the selected string unit SU0and the non-selected string unit SU1are maintained to be in the off state.

Meanwhile, as illustrated inFIG.17A, when the first program operation is started at time t10, the voltage of the gate line SGD0of the selected string unit SU0is raised up to the voltage Vsgd. The voltage Vsgd can turn on the drain-side select transistor ST1when the ground voltage Vss is applied to the bit line BL, and the voltage Vsgd can turn off the drain-side select transistor ST1when the internal power supply voltage Vdd is applied to the bit line BL, and the voltage Vsgd is, for example, 1.5 V. Accordingly, as illustrated inFIG.10, the drain-side select transistor ST1of the selected string unit SU0corresponding to the bit line BL2is turned on. In contrast, as illustrated inFIG.11, the drain-side select transistor ST1of the selected string unit SU0corresponding to the bit line BL4is turned off. As a result, the channel of the memory string MS21of the selected string unit SU0is in a floating state.

In addition, as illustrated inFIG.17B, when the first program operation is started at time t10, the gate line SGD1of the non-selected string unit SU1is maintained to be in a state where the ground voltage Vss is applied. Accordingly, as illustrated inFIGS.10and11, since the drain-side select transistor ST1of the non-selected string unit SU1is maintained to be in the off state, the channel of each of the memory strings MS12and MS22of the non-selected string unit SU1are in a floating state.

As illustrated inFIGS.17C and17D, when the first program operation is started at time t10, the voltage of each of the selected word line sWL and the non-selected word lines uWL is raised up to a pass voltage Vpass. The pass voltage Vpass is set to a value as illustrated inFIG.9A, and specifically, is set to a voltage high enough to turn on the memory cell transistor MT and low enough to prevent writing, and the pass voltage Vpass is set to, for example, 3 V. As illustrated inFIG.9A, the pass voltage Vpass is set to a voltage higher than a maximum threshold voltage at the Er state of the memory cell transistor MT. Therefore, when the pass voltage Vpass is applied to the gate of the memory cell transistor MT, the memory cell transistor MT is turned on regardless of the stored data.

When the pass voltage Vpass is applied to the selected word line sWL and the non-selected word lines uWL, in the memory string MS11of the selected string unit SU0, the selected memory cell transistor sMT and the non-selected memory cell transistor uMT are turned on to such an extent that the writing is not performed. For this reason, as illustrated inFIG.10, the ground voltage Vss is applied from the bit line BL2to the channel of the memory string MS11of the selected string unit SU0via the drain-side select transistor ST1that is turned on.

Subsequently, as illustrated inFIG.17C, the voltage of the selected word line sWL is further raised up to the program voltage Vpgm at time t11. The program voltage Vpgm is a high voltage that turns on the memory cell transistor MT and writes to the memory cell transistor MT and is set to, for example, 6 V. In this embodiment, the program voltage Vpgm applied to the selected word line sWL in the first program operation corresponds to the first voltage. When the program voltage Vpgm is applied to the selected word line sWL, the ferroelectric film331of the selected memory cell transistor sMT provided in the memory string MS11of the selected string unit SU0is spontaneously polarized based on a voltage difference between the ground voltage Vss applied to the channel of the memory string MS11and the program voltage Vpgm applied to the selected word line sWL. That is, the threshold voltage Vth of the selected memory cell transistor sMT is lowered to the Pr state illustrated inFIG.9Ato transition to the state in which the data of “0” is stored in the selected memory cell transistor sMT. On the other hand, as illustrated inFIG.11, since the channel of the memory string MS21of the selected string unit SU0is in the floating state, even when the program voltage Vpgm is applied to the selected word line sWL, the ferroelectric film331of the selected memory cell transistor sMT of the memory string MS21is not spontaneously polarized. That is, the threshold voltage Vth of the selected memory cell transistor sMT of the memory string MS21is maintained at the Er state illustrated inFIG.9A, so that the state in which the data of “1” is stored is maintained. It is noted that, as illustrated inFIGS.10and11, since the channel of each of the memory strings MS12and MS22of the non-selected string unit SU1is in the floating state, even when the program voltage Vpgm is applied to the selected word line sWL, the writing to the memory cell transistor MT corresponding to the selected word line sWL is not performed.

As illustrated inFIG.17C, the voltage of the selected word line sWL is lowered from the program voltage Vpgm to the ground voltage Vss at time t12. In addition, as illustrated inFIGS.18A and18B, each of the signals BLC and BLX of the sense amplifier120is set to a low level at time t12. After that, each of the signals BLC, BLX, HLL, XXL, and STB of the sense amplifier120is maintained at a low level. Therefore, in the sense amplifier120illustrated inFIG.6, both transistors TR2and TR3are maintained to be in the off state. That is, the bit line BL2is maintained to be in a state where the bit line is not connected to the node SRC and the internal power supply voltage Vdd is not applied. In addition, as illustrated inFIG.17F, the voltage of the node SEN is maintained at the ground voltage Vss.

It is noted that, as illustrated inFIG.171, when the first program operation is started at time t10, the state where the voltages of the odd-numbered bit lines including the bit lines BL1and BL3arranged on both sides of the bit line BL2are raised up to the internal power supply voltage Vdd is maintained. Accordingly, the voltage fluctuation of the odd-numbered bit lines is avoided from affecting the voltage of the even-numbered bit lines. In this embodiment, the internal power supply voltage Vdd applied to the odd-numbered bit lines corresponds to a predetermined voltage.

Moreover, when writing the data of “0” to the selected memory cell transistor sMT provided in the memory string MS11of the selected string unit SU0in this manner, due to the individual difference, or the like, the variation as illustrated inFIG.9Bmay be present in the threshold voltage Vth of the selected memory cell transistor sMT after performing the write operation. In this embodiment, when the threshold voltage Vth of the selected memory cell transistor sMT after performing the write operation is lower than a verify voltage Vpvfy illustrated inFIG.9B, it is determined that the writing to the selected memory cell transistor sMT has completed, and on the other hand, when the threshold voltage Vth of the selected memory cell transistor sMT is the verify voltage Vpvfy or more, it is determined that the writing to the selected memory cell transistor sMT has not completed. In this embodiment, the verify voltage Vpvfy corresponds to a writing determination voltage.

In addition, in the present embodiment, as described above, following the first program operation, the second program operation of rewriting data to the selected memory cell transistor sMT for which the writing has not completed is performed. Specifically, in the second program operation, when the threshold voltage Vth of the selected memory cell transistor sMT after the writing is equal to or more than the verify voltage Vpvfy illustrated inFIG.9B, the writing the data to the selected memory cell transistor sMT is performed again. By performing the second program operation once or multiple times, the distribution of the threshold voltage Vth of the selected memory cell transistor sMT can be shifted to the distribution illustrated inFIG.9A, that is, the distribution of the threshold voltage Vth that is lower than the verify voltage Vpvfy.

1.7.2 Second Program Operation

As illustrated inFIGS.17A to17J, in the second program operation, the precharge operation, and the pulse application operation are performed in this order. The precharge operation is an operation of applying a voltage required for writing data again to the bit line BL. The pulse application operation is an operation of rewriting data to the selected memory cell transistor sMT by using the voltage applied to the bit line BL. In this embodiment, the pulse application operation of the second program operation corresponds to the second pulse application operation.

1.7.2.1 Precharge Operation of Second Program Operation

InFIGS.17A to17JandFIGS.18A to18E, the time when the second program operation is started, in other words, the time when the precharge operation is started is indicated by “t13”.

When the precharge operation is started at time t13, as illustrated inFIG.17C, the ground voltage Vss is applied to the selected word line sWL. In this embodiment, the ground voltage Vss applied to the selected word line sWL in the precharge operation corresponds to a third voltage. In addition, as illustrated inFIG.17D, a read pass voltage Vread is applied to the non-selected word lines uWL. In this embodiment, the read pass voltage Vread is set to, for example 3 V and is set to the same value as the pass voltage Vpass as illustrated inFIG.9B.

As illustrated inFIG.17J, the voltage of the source line SL is raised up to the internal power supply voltage Vdd at time t13. In this embodiment, the internal power supply voltage Vdd applied to the source line SL in the precharge operation corresponds to the fourth voltage. In addition, as illustrated inFIG.17A, the voltage of the gate line SGD0of the selected string unit SU0is raised up to the read pass voltage Vread at time t14, and as illustrated inFIG.17E, the voltage of each of the gate lines SGS and SGSB is also raised up to the read pass voltage Vread at time t15.

Accordingly, as illustrated inFIG.12, in the memory string MS11of the selected string unit SU0, the drain-side select transistor ST1, the source-side select transistors ST2and ST3, and the plurality of non-selected memory cell transistors uMT are turned on. At this time, the voltage corresponding to the write state of the selected memory cell transistor sMT is applied to the bit line BL2to charge the bit line.

Specifically, when the threshold voltage Vth of the selected memory cell transistor sMT belongs to the area A11illustrated inFIG.9B, that is, when the threshold voltage Vth of the selected memory cell transistor sMT is lower than the ground voltage Vss, the voltage of each component of the memory string MS11is as illustrated inFIG.12. As illustrated inFIG.12, in the channel of the memory string MS11, the internal power supply voltage Vdd is applied from the source line SL via the source-side select transistors ST2and ST3to the portion of the channel located closer to the source line SL than the selected memory cell transistor sMT. Therefore, the internal power supply voltage Vdd is applied to the source of the selected memory cell transistor sMT. Since the ground voltage Vss is applied to the selected word line sWL in this state, when the threshold voltage Vth of the selected memory cell transistor sMT is lower than the ground voltage Vss, the selected memory cell transistor sMT is turned on. At this time, in the channel of the memory string MS11, a voltage corresponding to the polarizability P1illustrated inFIG.7, specifically, a voltage corresponding to the absolute value |Vth| of the threshold voltage of the selected memory cell transistor sMT is generated in the portion located closer to the bit line BL2than the selected memory cell transistor sMT. This voltage |Vth| is applied to the bit line BL2via the drain-side select transistor ST1. At this time, the bit line BL2is not connected to any one of the node SRC and the internal power supply voltage Vdd. For this reason, the bit line BL2is charged with the voltage |Vth|.

It is noted that when the writing to the selected memory cell transistor sMT has completed, since the threshold voltage Vth of the selected memory cell transistor sMT is lower than the verify voltage Vpvfy illustrated inFIG.9B, a voltage higher than the absolute value |Vpvfy| of the verify voltage is applied to the bit line BL2as illustrated by a solid line inFIG.17G. On the other hand, when the writing to the selected memory cell transistor sMT has not completed, since the threshold voltage Vth of the selected memory cell transistor sMT satisfies “Vpvfy≤Vth<0”, as indicated by the one-dot dashed line inFIG.17G, a voltage that is the absolute value |Vpvfy| or less of the verify voltage and higher than the ground voltage Vss is applied to the bit line BL2.

On the other hand, when the threshold voltage Vth of the selected memory cell transistor sMT belongs to an area A12illustrated inFIG.9B, that is, when the threshold voltage Vth of the selected memory cell transistor sMT is the ground voltage Vss or more, the voltage of each component of the memory string MS11becomes as illustrated inFIG.13. In this case, when the internal power supply voltage Vdd is applied to the source of the selected memory cell transistor sMT and the ground voltage Vss is applied to the selected word line sWL, the selected memory cell transistor sMT is turned off. For this reason, in the channel of the memory string MS11, each of the voltage of the portion located closer to the bit line BL2than the selected memory cell transistor sMT and the voltage of the bit line BL2are maintained. Specifically, as indicated by a broken line inFIG.17G, the voltage of the bit line BL2is maintained at the ground voltage Vss.

As described above, by performing the precharge operation, the charging voltage of the bit line BL2is set as illustrated inFIG.19according to the threshold voltage Vth of the selected memory cell transistor sMT.

(a1) When the threshold voltage Vth of the selected memory cell transistor sMT satisfies “Vth<Vpvfy”, that is, when the writing to the selected memory cell transistor sMT has completed, the charging voltage Vb of the bit line BL2becomes the voltage |Vth|. At this time, the charging voltage Vb of the bit line BL2satisfies “Vb>|Vpvfy|”.

(a2) When the threshold voltage Vth of the selected memory cell transistor sMT satisfies “Vpvfy≤Vth<Vss”, that is, when the writing to the selected memory cell transistor sMT has not completed, the charging voltage Vb of the bit line BL2becomes the voltage |Vth|. At this time, the charging voltage Vb of the bit line BL2satisfies “Vss<Vb|Vpvfy|”.

(a3) When the threshold voltage Vth of the selected memory cell transistor sMT satisfies “Vss≤Vth”, that is, when the writing to the selected memory cell transistor sMT has not completed, the charging voltage Vb of the bit line BL2becomes the ground voltage Vss.

As illustrated inFIG.17E, the voltages of the gate lines SGS and SGSB are lowered from the read pass voltage Vread to the ground voltage Vss at time t16. In addition, as illustrated inFIGS.17A,17D, and17J, the gate line SGD0, the non-selected word lines uWL, and the source line SL are lowered to the ground voltage Vss at time t17.

1.7.2.2 Pulse Application Operation of Second Program Operation

InFIGS.17A to17JandFIGS.18A to18E, the time when the pulse application operation of the second program operation is started is indicated by “t18”.

As illustrated inFIG.17E, at the time when the pulse application operation is started at time t18, since the ground voltage Vss is applied to the gate lines SGS and SGSB, both the source-side select transistors ST2and ST3are turned off. Therefore, as illustrated inFIG.14, the bit line BL2is in a floating state while having the charging voltage Vb. By applying the charging voltage Vb of the bit line BL2to the channel of the memory string MS11, the writing to the selected memory cell transistor sMT is performed again.

Specifically, as illustrated inFIGS.17C and17D, when the pulse application operation is started at time t18, the voltage of each of the selected word line sWL and the non-selected word lines uWL is raised up to the pass voltage Vpass. Accordingly, as illustrated inFIG.14, the selected memory cell transistor sMT and the non-selected memory cell transistor uMT are turned on. In addition, as illustrated inFIG.17C, the voltage of the selected word line sWL is further raised up to the program voltage Vpgm at time t19.

Meanwhile, as illustrated inFIG.17A, when the pulse application operation is started at time t18, the voltage of the gate line SGD0is raised up to “Vth_sgd+|Vpvfy|”. The “Vth_sgd” is the threshold voltage of the drain-side select transistor ST1. By applying such “Vth_sgd+|Vpvfy|” to the gate line SGD0, the drain-side select transistor ST1is turned on or off according to the above states (a1) to (a3).

It is noted that, as illustrated inFIG.17C, the voltage of the selected word line sWL is lowered from the program voltage Vpgm to the ground voltage Vss at time t20.

1.7.2.2.1 in Case of (a2) where Writing has not Completed

In this case, the charging voltage Vb of the bit line BL2satisfies “Vss<Vb≤|Vpvfy|” as described above. For this reason, when the voltage of the gate line SGD0is set to “Vth_sgd+|Vpvfy|”, since a voltage difference generated between the drain and the gate of the drain-side select transistor ST1becomes the threshold voltage Vth_sgd or more, the drain-side select transistor ST1is turned on as illustrated inFIG.14. As a result, the voltage |Vth| which is the charging voltage Vb of the bit line BL2is applied to the channel of the memory string MS11via the drain-side select transistor ST1. At this time, the selected memory cell transistor sMT is spontaneously polarized according to a voltage difference between the voltage |Vth| applied to the channel of the memory string MS11and the program voltage Vpgm applied to the selected word line sWL. By spontaneously polarizing the selected memory cell transistor sMT in this manner, since the threshold voltage Vth of the selected memory cell transistor sMT for which the writing has not completed is shifted to a voltage lower than the verify voltage Vpvfy, the writing to the selected memory cell transistor sMT can be completed.

In addition, since a voltage higher than the ground voltage Vss is applied to the channel of the memory string MS11, as illustrated inFIG.10, a voltage difference generated in the selected memory cell transistor sMT can be reduced in comparison to the time of performing the first program operation where the ground voltage Vss is applied to the channel of the memory string MS11. Therefore, in comparison to the first program operation, the selected memory cell transistor sMT can be spontaneously polarized in a weaker manner. When the charging voltage Vb of the bit line BL2satisfies “Vss<Vb≤|Vpvfy|”, the selected memory cell transistor sMT is in a state where the writing has not completed but some writing is performed. For this reason, by spontaneously polarizing the selected memory cell transistor sMT in a weaker manner, the writing to the selected memory cell transistor sMT can be completed while avoiding excessive spontaneous polarization of the selected memory cell transistor sMT in the second program operation.

1.7.2.2.2 In Case of (a3) when Writing has not Completed

In this case, the charging voltage Vb of the bit line BL2is set to the ground voltage Vss. For this reason, when the voltage of the gate line SGD0is set to “Vth_sgd+|Vpvfy|”, since the voltage difference generated between the drain and the gate of the drain-side select transistor ST1is the threshold voltage Vth_sgd or more, as illustrated inFIG.15, the drain-side select transistor ST1is turned on. As a result, the ground voltage Vss which is the charging voltage Vb of the bit line BL2is applied to the channel of the memory string MS11via the drain-side select transistor ST1. At this time, the selected memory cell transistor sMT is spontaneously polarized according to the voltage difference between the ground voltage Vss applied to the channel of the memory string MS11and the program voltage Vpgm applied to the selected word line sWL. That is, the same write operation as the first program operation is performed on the selected memory cell transistor sMT.

When the charging voltage Vb of the bit line BL2satisfies “Vb=Vss”, the writing to the selected memory cell transistor sMT is hardly performed. By performing the same write operation as the first program operation on such a selected memory cell transistor sMT, the writing to the selected memory cell transistor sMT can be completed.

1.7.2.2.3 In Case of (a1) when Writing has Completed

In this case, the charging voltage Vb of the bit line BL2satisfies “Vb>|Vpvfy|”. For this reason, when the voltage of the gate line SGD0is set to “Vth_sgd+|Vpyfy|”, since a voltage difference between the drain and the gate of the drain-side select transistor ST1becomes lower than the threshold voltage Vth_sgd, as illustrated inFIG.16, the drain-side select transistor ST1is turned off. For this reason, the channel of the memory string MS11is in a floating state. As a result, even when the program voltage Vpgm is applied to the selected word line sWL, the selected memory cell transistor sMT is not further spontaneously polarized.

When the charging voltage Vb of the bit line BL2satisfies “Vb>|Vpyfy|”, the selected memory cell transistor sMT is in a state where the writing has completed. Since the selected memory cell transistor sMT is not further spontaneously polarized, the selected memory cell transistor sMT for which the writing has completed can be avoided from being excessively spontaneously polarized in the second program operation.

1.7.3. Operation of Sequencer

Next, the processing procedure of the write operation executed by the sequencer41will be specifically described with reference toFIGS.20and21. It is noted that the processing illustrated inFIG.20is executed for a predetermined string unit SU each time when the writing of data to the selected memory cell transistor sMT corresponding to the selected word line sWL is performed. It is noted that the initial value of the counter C illustrated inFIG.20is set to “0”.

As illustrated inFIG.20, the sequencer41first executes the first program operation (step S10). Specifically, the sequencer41executes the write operation to the selected memory cell transistor sMT corresponding to the selected word line sWL of the selected string unit SU.

Subsequently, the sequencer41executes the second program operation (step S11). The sequencer41executes the processing illustrated inFIG.21as the second program operation.

As illustrated inFIG.21, the sequencer41first executes the above-mentioned precharge operation (step S110). Specifically, the sequencer41turns on the drain-side select transistor ST1and the source-side select transistors ST2and ST3corresponding to the selected string unit SU and applies the internal power supply voltage Vdd to the source line SL. In addition, the sequencer41applies the ground voltage Vss to the selected word line sWL and also applies the read pass voltage Vread to the non-selected word lines uWL. Accordingly, the bit line BL corresponding to the selected memory cell transistor sMT to which the data of “0” is written can be charged with the voltage |Vth| or the ground voltage Vss.

Subsequently, the sequencer41executes the pulse application operation in the second program operation (step S111). Specifically, the sequencer41turns off the source-side select transistors ST2and ST3and applies “Vth_sgd+|Vpvfy|” to the gate line SGD0. In addition, the program voltage Vpgm is applied to the selected word line sWL. Accordingly, when the writing of the data of “0” to the selected memory cell transistor sMT has completed, since the drain-side select transistor ST1is turned off, an additional write operation to the selected memory cell transistor sMT is not performed. On the other hand, when the writing of the data of “0” to the selected memory cell transistor sMT has not completed, since the drain-side select transistor ST1is turned on and the charging voltage Vb of the bit line BL is applied to the channel of the memory string MS, the writing according to a voltage difference between the charging voltage Vb of the bit line BL and the program voltage Vpgm to the selected memory cell transistor sMT is performed.

When the second program operation illustrated inFIG.21has thus completed, the sequencer41increments the value of the counter C (step S12) as illustrated inFIG.20, and after that, it is determined whether the value of the counter C is the determination value Cth or more (step S13). The determination value Cth is set to an integer of 1 or more. When the value of the counter C is not the determination value Cth or more (step S13: NO), the sequencer41returns to the process of step S11to execute the second program operation again. The value of the counter C is incremented each time when the second program operation is executed. Therefore, the value of the counter C is equal to the number of times of execution of the second program operation. When the value of the counter C is the determination value Cth or more (step S13: YES), the sequencer41initializes the value of the counter C (step S14), and after that, the processing illustrated inFIG.20is ended.

1.8. Function and Effect

In the semiconductor memory device2of this embodiment, when the sequencer41executes the write operation on the selected memory cell transistor sMT which is one of the memory cell transistors MT, the first program operation and the second program operation are performed. In the first program operation, the sequencer41applies the program voltage Vpgm to the selected word line sWL corresponding to the selected memory cell transistor sMT in a state of turning on the drain-side select transistor ST1and turning off the source-side select transistors ST2and ST3and applies the ground voltage Vss lower than the program voltage Vpgm to the bit line BL, so that the threshold voltage Vth of the selected memory cell transistor sMT is lowered. The second program operation includes the precharge operation and the pulse application operation. In the precharge operation, the sequencer41applies the ground voltage Vss to the selected word line sWL in a state of turning on the drain-side select transistor ST1and the source-side select transistors ST2and ST3after the execution of the first program operation and applies the internal power supply voltage Vdd to the source line SL, so that the bit line BL is charged. In the pulse application operation, after the precharge operation, in a state where the bit line BL is maintained to be in a floating state by the sense amplifier circuit SA, the sequencer41applies the program voltage Vpgm to the selected word line sWL in a state where the drain-side select transistor ST1is turned on and the source-side select transistors ST2and ST3are turned off.

According to this configuration, since the rewriting to the selected memory cell transistor sMT by using the voltage charged to the bit line BL is performed, the process of allowing the sense amplifier120to read the data written in the selected memory cell transistor sMT and the process of setting the voltage to be applied to the bit line BL based on the data become unnecessary. Therefore, the write operation at a higher speed can be performed.

In the semiconductor memory device2of this embodiment, the sequencer41applies “Vth_sgd+|Vpyfy|” to the gate line SGD0of the drain-side select transistor ST1in the pulse application operation of the second program operation. “Vth_sgd+|Vpyfy|” is a voltage of turning on the drain-side select transistor ST1when the charging voltage Vb of the bit line BL is the absolute value |Vpyfy| or less of the verify voltage and turning off the drain-side select transistor ST1when the charging voltage Vb of the bit line BL is higher than the absolute value |Vpvfy| of the verify voltage.

According to this configuration, when the charging voltage Vb of the bit line BL is higher than the absolute value |Vpvfy| of the verify voltage, that is, when the writing to the selected memory cell transistor sMT has completed, the drain-side select transistor ST1is turned off. For this reason, as illustrated inFIG.16, when the program voltage Vpgm is applied to the selected word line sWL, further writing to the selected memory cell transistor sMT for which the writing has completed can be avoided.

When the charging voltage Vb of the bit line BL is the absolute value |Vpvfy| or less of the verify voltage, that is, when the writing to the selected memory cell transistor sMT has not completed, the drain-side select transistor ST1is turned on. For this reason, as illustrated inFIGS.14and15, when the program voltage Vpgm is applied to the selected word line sWL, since rewriting to the selected memory cell transistor sMT for which the writing has not completed is performed, the writing to the selected memory cell transistor sMT can be more reliably performed.

Furthermore, in the precharge operation provided in the second program operation, when the threshold voltage Vth of the selected memory cell transistor sMT is “Vpvfy≤Vth<Vss”, the charging voltage Vb of the bit line BL satisfies “Vss<Vb”, and when the threshold voltage Vth of the selected memory cell transistor sMT is “Vss≤Vth”, the charging voltage Vb of the bit line BL becomes the ground voltage Vss. That is, in the precharge operation, the charging voltage Vb of the bit line BL is set in a self-aligning manner according to the difference between the threshold voltage Vth and the verify voltage Vpvfy of the selected memory cell transistor sMT. Accordingly, in the pulse application operation provided in the second program operation, when the difference between the threshold voltage Vth and the verify voltage Vpvfy of the selected memory cell transistor sMT is large, the threshold voltage Vth of the selected memory cell transistor sMT fluctuates greatly, and when the difference between the threshold voltage Vth and the verify voltage Vpvfy of the selected memory cell transistor sMT is small, the threshold voltage Vth of the selected memory cell transistor sMT fluctuates slightly. Accordingly, the threshold voltages Vth of the memory cell transistors MT to which the data of “0” is written can be distributed in a range that is higher than the lower limit of the Pr state illustrated inFIG.9Band lower than the verify voltage Vpvfy. That is, the distribution of the threshold voltage Vth of the memory cell transistor MT can be narrowed.

When the value of the counter C illustrated inFIG.20is set to an integer of 2 or more, the sequencer41alternately executes the precharge operation and the pulse application operation provided in the second program operation multiple times.

According to this configuration, when there is a selected memory cell transistor sMT for which the writing has not completed, the precharge operation and the pulse application operation are repeatedly performed until the writing to the selected memory cell transistor sMT has completed, in other words, until the threshold voltage Vth of the selected memory cell transistor sMT is lower than the verify voltage Vpvfy. For this reason, the writing to the selected memory cell transistor sMT can be more reliably performed.

When executing the write operation on the selected memory cell transistor sMT, the sequencer41maintains the voltage applied to the bit lines BL1and BL3located adjacent to the bit line BL2connected to the selected memory cell transistor sMT to be the internal power supply voltage Vdd. In this embodiment, the bit line BL2corresponds to the first bit line, the bit lines BL1and BL3correspond to the second bit lines, and the internal power supply voltage Vdd corresponds to the fifth voltage.

According to this configuration, the voltage fluctuation of the bit lines BL1and BL3can be avoided from affecting the charging voltage Vb of the bit line BL2.

2. SECOND EMBODIMENT

Next, a second embodiment of the semiconductor memory device2will be described. The following description focuses on the differences from the semiconductor memory device2according to the first embodiment.

2.1. Operation of Sequencer

FIG.22illustrates the processing procedure of the second program operation executed by the sequencer41of this embodiment. It is noted that, in the following also, the case where the data of “0” is stored in the latch circuit SDL of the sense amplifier unit SAU corresponding to the bit line BL2, and the data of “1” is stored in the latch circuit SDL of the sense amplifier unit SAU corresponding to the bit line BL4will be described as an example.

After the execution of the pulse application operation (step S111), the sequencer41resets the voltage of the bit line BL of the selected string unit SU0(step S112). Specifically, as illustrated inFIG.23G, when the voltage of the bit line BL2is lowered to the ground voltage Vss at time t20, the signals BLC and BLX of the sense amplifier120are set to a high level as illustrated inFIGS.24A and24B. Accordingly, when the data of “1” is stored in the latch circuit SDL of the sense amplifier unit SAU, the voltage of the internal power supply voltage Vdd is applied to the bit line BL. On the other hand, when the data of “0” is stored in the latch circuit SDL of the sense amplifier unit SAU, the voltage of the node SRC, that is, the ground voltage Vss is applied to the bit line BL. Accordingly, as illustrated inFIG.23G, the voltage of the bit line BL2is lowered to the ground voltage Vss and reset at time t20. After that, at time t21, the second program operation is started again.

2.2. Function and Effect

In the semiconductor memory device2of this embodiment, after the sequencer41performs the pulse application operation of the second program operation and before performing the precharge operation of the next second program operation, the sense amplifier120performs the reset operation of resetting the voltage of the bit line BL based on the data stored in the latch circuit SDL.

According to this configuration, the next second program operation can be avoided from being started, for example, while maintaining the state where the bit line BL2is charged with the voltage |Vth|, that is, while the bit line BL2is maintained to be in a floating state. When the bit line BL2is in a floating state, since the voltage of the bit line BL2is likely to become unstable, the unstable state of the bit line BL2is eliminated by temporarily lowering the voltage of the bit line BL2to the ground voltage Vss, and thus, the next second program operation can be started. As a result, the second program operation at higher accuracy can be executed.

3. THIRD EMBODIMENT

Next, a third embodiment of the semiconductor memory device2will be described. The following description focuses on the differences from the semiconductor memory device2according to the first embodiment.

3.1 Configuration of Sense Amplifier

FIG.25illustrates a configuration example of a sense amplifier120of this embodiment. As illustrated inFIG.25, the sense amplifier unit SAU and the amplifier circuit AC are electrically connected in parallel to the bit line BL. The sense amplifier unit SAU has the same configuration as the sense amplifier unit SAU illustrated inFIG.6. The amplifier circuit AC is a circuit for amplifying the charging voltage Vb of the bit line BL. In this embodiment, the amplifier circuit AC corresponds to a voltage adjustment circuit.

3.2 Sequencer Operation

FIG.26illustrates a processing procedure of the second program operation executed by the sequencer41of this embodiment. It is noted that, in the following also, the case where the data of “0” is stored in the latch circuit SDL of the sense amplifier unit SAU corresponding to the bit line BL2, and the data of “1” is stored in the latch circuit SDL of the sense amplifier unit SAU corresponding to the bit line BL4will be described as an example.

After the execution of the precharge operation (step S110), the sequencer41executes an amplify operation of amplifying the charging voltage Vb of the bit line BL (step S113). Specifically, as illustrated inFIG.27E, after the voltages of the gate lines SGS and SGSB are lowered from the read pass voltage Vread to the ground voltage Vss at time t16, that is, after the source-side select transistors ST2and ST3are turned off, the charging voltage Vb of the bit line BL2is amplified by the amplifier circuit AC illustrated inFIG.25at time t16a. When the charging voltage Vb of the bit line BL2is higher than the absolute value |Vpvfy| of the verify voltage, the amplifier circuit AC raises the charging voltage Vb of the bit line BL2up to the internal power supply voltage Vdd as indicated by a solid line inFIG.27E. Therefore, when the writing to the selected memory cell transistor sMT has completed, the charging voltage Vb of the bit line BL2is set to the internal power supply voltage Vdd. On the other hand, when the charging voltage Vb of the bit line BL2is the absolute value |Vpvfy| or less of the verify voltage, the amplifier circuit AC lowers the charging voltage Vb of the bit line BL2down to the ground voltage Vss as indicated by a one-dot dashed line inFIG.27E. Therefore, when the writing to the selected memory cell transistor sMT has not completed, the charging voltage Vb of the bit line BL2is set to the ground voltage Vss.

As illustrated inFIG.26, the sequencer41executes the pulse application operation following the process of step S113(step S111). At this time, as illustrated inFIG.27A, when the pulse application operation is started at time t18, the voltage Vsgd is applied to the gate line SGD0of the selected string unit SU0. Accordingly, when the writing to the selected memory cell transistor sMT has completed and the charging voltage Vb of the bit line BL2is set to the internal power supply voltage Vdd, the drain-side select transistor ST1is turned off. For this reason, since the channel of the memory string MS11is in a floating state, the writing to the selected memory cell transistor sMT is not performed. On the other hand, when the writing to the selected memory cell transistor sMT has not completed and the charging voltage Vb of the bit line BL2is set to the ground voltage Vss, the drain-side select transistor ST1is turned on. For this reason, since the ground voltage Vss is applied to the channel of the memory string MS11, the selected memory cell transistor sMT is spontaneously polarized based on the voltage difference between the ground voltage Vss applied to the channel of the memory string MS11and the program voltage Vpgm applied to the selected word line sWL. Therefore, the writing to the selected memory cell transistor sMT is performed.

3.3 Function and Effect

The semiconductor memory device2further includes an amplifier circuit AC that adjusts the voltage charged on the bit line BL by the precharge operation of the second program operation.

According to this configuration, the voltage Vsgd used in the first program operation can be used as it is as the voltage applied to the gate line SGD0of the selected string unit SU0in the pulse application operation of the second program operation.

4. OTHER EMBODIMENTS

The present disclosure is not limited to the above specific examples.

For example, the magnitudes of various voltages such as the program voltage Vpgm and the internal power supply voltage Vdd can be freely changed. In addition, the voltage applied to the gate line SGD0of the drain-side select transistor ST1in the pulse application operation of the second program operation can be changed.

In the semiconductor memory device2according to the third embodiment, the sense amplifier unit SAU may incorporate the function of the amplifier circuit AC.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.