Patent ID: 12211554

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures, or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

NAND Flash memory devices can perform erase operations at the page/word line level, i.e., programming all the memory cells coupled to the same selected word line at the same time. During a program operation, in order to select certain memory cells in the selected word lines to be programmed, drain select gate (DSG) transistors and source select gate (SSG) transistors at the drain and source ends of each NAND memory string can be turned on or off. For a selected NAND memory string, the DSG transistor needs to be fully turned on to increase the programming efficiency. Whereas for an unselected NAND memory string, the DSG transistor needs to be completely turned off in order to form a channel coping potential in the unselected NAND memory string to reduce the program voltage disturbance caused by leakage current from the DSG transistor.

For three-dimensional (3D) NAND memory devices, one or more DSG transistors are usually formed as parts of the top conductive layers in the memory stacks, and the threshold voltages of the DSG transistors are trimmed (e.g., through program operations and/or erase operations) to a desired value or a range. However, due to the nature of the fabrication process in forming the memory stack, the DSG transistor in the top conductive layer has an inferior subthreshold slope (e.g., less steep slope) and high leakage current, thereby reducing the channel coupling potential in the unselected NAND memory string and increasing the program voltage disturbance. Moreover, the DSG transistor in the top conductive layer has inferior temperature characteristics. For example, the threshold voltage of the DSG transistor may increase as the operating temperature decreases, and the threshold voltage uniformity among different DSG transistors may also reduce. As a result, DSG transistors of some selected NAND memory strings may not be fully turned on at low temperatures, which then requires higher program voltage and/or more program voltage pulses, thereby increasing the program voltage disturbance as well as channel pass voltage disturbance.

To address the aforementioned issues, the present disclosure introduces a solution that avoids using the top conductive layer in the memory stack to form the DSG transistors of 3D NAND memory strings. Consistent with scope of the present disclosure, the transistors in the top conductive layer in the memory stack become dummy transistors, and the DSG transistors are formed in the conductive layers that are below the top conductive layer, which have better subthreshold slope and temperature characteristics than the top conductive layer. During program operations, a positive bias gate voltage, which is high enough to ensure that the dummy transistors can be fully turned on even at the low temperatures, is applied to the dummy transistors in the selected NAND memory strings, according to some aspects of the present disclosure.

As a result, the DSG transistors can have a better subthreshold slope and a lower leakage current, thereby reducing the program voltage disturbance for the unselected NAND memory strings. Also, due to the better temperature characteristics, the increase of the DSG transistors' threshold voltages at low temperatures can be reduced and become more uniform among different NAND memory springs, which help to fully turn on all the DSG transistors in selected NAND memory strings during operate operation. Thus, the program operation can be speed up with a smaller number of program voltage pulses and a lower program voltage level, thereby reducing the program voltage disturbance and channel pass voltage disturbance. Moreover, the threshold voltage window of the DSG transistors can be enlarged due to the better subthreshold slope and temperature characteristics, compared with the known NAND memory devices in which the DSG transistors are formed in the top conductive layer of the memory stacks.

FIG.1illustrates a block diagram of an exemplary system100having a memory device, according to some aspects of the present disclosure. System100can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown inFIG.1, system100can include a host108and a memory system102having one or more memory devices104and a memory controller106. Host108can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host108can be configured to send or receive data to or from memory devices104.

Memory device104can be any memory device disclosed in the present disclosure. As disclosed below in detail, memory device104, such as a NAND Flash memory device, can include a dummy transistor (drain dummy transistor) between the DSG transistor and the drain of each NAND memory string to avoid using such a transistor as the DSG transistor. For example, in a 3D NAND memory device, the top conductive layer of the memory stack may not be used to form the DSG transistor due to its inferior subthreshold slope (e.g., less steep slope) and temperature characteristics. Consistent with the scope the present disclosure, in a program operation, a drain dummy line voltage that is greater than the DSG voltage can be applied to the drain dummy line to fully turn on the drain dummy transistor in each selected NAND memory string, even at the lower bound of the operating temperature range of memory device104.

Memory controller106is coupled to memory device104and host108and is configured to control memory device104, according to some implementations. Memory controller106can manage the data stored in memory device104and communicate with host108. In some implementations, memory controller106is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller106is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller106can be configured to control operations of memory device104, such as read, erase, and program operations. Memory controller106can also be configured to manage various functions with respect to the data stored or to be stored in memory device104including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller106is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device104. Any other suitable functions may be performed by memory controller106as well, for example, formatting memory device104. Memory controller106can communicate with an external device (e.g., host108) according to a particular communication protocol. For example, memory controller106may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

Memory controller106and one or more memory devices104can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system102can be implemented and packaged into different types of end electronic products. In one example as shown inFIG.2A, memory controller106and a single memory device104may be integrated into a memory card202. Memory card202can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory card202can further include a memory card connector204coupling memory card202with a host (e.g., host108inFIG.1). In another example as shown inFIG.2B, memory controller106and multiple memory devices104may be integrated into an SSD206. SSD206can further include an SSD connector208coupling SSD206with a host (e.g., host108inFIG.1). In some implementations, the storage capacity and/or the operation speed of SSD206is greater than those of memory card202.

FIG.3illustrates a schematic circuit diagram of an exemplary memory device300including peripheral circuits302, according to some aspects of the present disclosure. Memory device300can be an example of memory device104inFIG.1. Memory device300can include a memory cell array301and peripheral circuits302coupled to memory cell array301. Memory cell array301can be a NAND Flash memory cell array in which memory cells306are provided in the form of an array of NAND memory strings308each extending vertically above a substrate (not shown). In some implementations, each NAND memory string308includes a plurality of memory cells306coupled in series and stacked vertically. Each memory cell306can hold a continuous, analog value, such as an electrical voltage or charge, which depends on the number of electrons trapped within a region of memory cell306. Each memory cell306can be either a floating gate type of memory cell including a floating-gate transistor or a charge trap type of memory cell including a charge-trap transistor.

In some implementations, each memory cell306is a single-level cell (SLC) that has two possible memory states and thus, can store one bit of data. For example, the first memory state “0” can correspond to a first range of voltages, and the second memory state “1” can correspond to a second range of voltages. In some implementations, each memory cell306is a multi-level cell (MLC) that is capable of storing more than a single bit of data in more than four memory states. For example, the MLC can store two bits per cell, three bits per cell (also known as triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, then the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

As shown inFIG.3, each NAND memory string308can also include a source select gate (SSG) transistor310at its source end and a drain select gate (DSG) transistor312at its drain end. SSG transistor310and DSG transistor312can be configured to activate selected NAND memory strings308(columns of the array) during read and program operations. In some implementations, the sources of NAND memory strings308in the same block304are coupled through a same source line (SL)314, e.g., a common SL. In other words, all NAND memory strings308in the same block304have an array common source (ASC), according to some implementations. The drain of each NAND memory string308is coupled to a respective bit line316from which data can be read or written via an output bus (not shown), according to some implementations. In some implementations, each NAND memory string308is configured to be selected or deselected by applying a select voltage or a deselect voltage to the gate of respective DSG transistor312through one or more DSG lines313and/or by applying a select voltage or a deselect voltage to the gate of respective SSG transistor310through one or more SSG lines315.

As shown inFIG.3, NAND memory strings308can be organized into multiple blocks304, each of which can have a common source line314, e.g., coupled to the ACS. In some implementations, each block304is the basic data unit for erase operations, i.e., all memory cells306on the same block304are erased at the same time. To erase memory cells306in a selected block304, source lines314coupled to selected block304as well as unselected blocks304in the same plane as selected block304can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20 V or more). Memory cells306of adjacent NAND memory strings308can be coupled through word lines318that select which row of memory cells306is affected by read and program operations. In some implementations, each word line318is coupled to a page320of memory cells306, which is the basic data unit for program operations. The size of one page320in bits can relate to the number of NAND memory strings308coupled by word line318in one block304. Each word line318can include a plurality of control gates (gate electrodes) at each memory cell306in respective page320and a gate line coupling the control gates.

FIGS.4A and4Billustrate a side view and a plan view of cross-sections of an exemplary memory cell array301including NAND memory strings308, respectively, according to some aspects of the present disclosure. As shown inFIG.4A, NAND memory string308can extend vertically through a memory stack404above a substrate402. Substrate402can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable materials. It is noted that x, y, and z axes are included inFIG.4Ato further illustrate the spatial relationship of the components in a memory device. Substrate402includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer on which the memory device can be formed, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on,” “above,” or “below” another component (e.g., a layer or a device) of the memory device is determined relative to substrate402of the memory device in the z-direction (the vertical direction perpendicular to the x-y plane) when substrate402is positioned in the lowest plane of the memory device in the z-direction. The same notion for describing the spatial relationships is applied throughout the present disclosure.

Memory stack404can include interleaved gate conductive layers406and gate-to-gate dielectric layers408. The number of the pairs of gate conductive layers406and gate-to-gate dielectric layers408in memory stack404can determine the number of memory cells306in memory cell array301. Gate conductive layer406can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, each gate conductive layer406includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer406includes a doped polysilicon layer. Each gate conductive layer406can include the control gates of memory cells306, the gates of DSG transistors312, or the gates of SSG transistors310, and can extend laterally as DSG line313in the upper portion of memory stack404, SSG line315in the lower portion of memory stack404, or word line318between DSG line313and SSG line315. It is understood that although one SSG line315and one DSG line313are shown inFIG.4A, the number of SSG lines315and the number of DSG lines313(as well as the numbers of SSG transistors310and DSG transistors312coupled to the SSG lines315and DSG lines313, respectively) may vary in other examples.

As described above, due to the nature of the fabrication process of forming interleaved gate conductive layers406and gate-to-gate dielectric layers408in memory stack404, the transistors in NAND memory strings308coupled to the top gate conductive layer may have inferior electrical performance (e.g., the less steep subthreshold slope and temperature characteristics), compared with the transistors coupled to lower gate conductive layer406. In some implementations, the electrical performance (e.g., the subthreshold slope and temperature characteristics) of the transistors in NAND memory strings308coupled to a lower gate conductive layer406is better than that of the transistors coupled to an upper gate conductive layer, such that the transistors coupled to the top gate conductive layer has the most inferior electrical performance. As described below in detail, consistent with the scope of the present disclosure, to reduce the impact of the inferior electrical performance, at least the top gate conductive layer does not include DSG line313or the gates of DSG transistors312, but instead, includes a drain dummy line323and gates of drain dummy transistors322, as shown inFIG.3, according to some implementations. In other words, in some implementations, DSG line313and the gates of DSG transistors312are not parts of the top gate conductive layer. It is understood that in some examples, one or more gate conductive layers406below the top gate conductive layer (e.g., gate conductive layers406immediately below the top gate conductive layer) may also include a drain dummy line and gates of drain dummy transistors, like the top gate conductive layer.

As shown inFIG.4A, NAND memory string308includes a channel structure412extending vertically through memory stack404. In some implementations, channel structure412includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel420) and dielectric material(s) (e.g., as a memory film418). In some implementations, semiconductor channel420includes silicon, such as polysilicon. In some implementations, memory film418is a composite dielectric layer including a tunneling layer426, a storage layer424(also known as a “charge trap/storage layer”), and a blocking layer422. Channel structure412can have a cylinder shape (e.g., a pillar shape). Semiconductor channel420, tunneling layer426, storage layer424, blocking layer422are arranged radially from the center toward the outer surface of the pillar in this order, according to some implementations. Tunneling layer426can include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer424can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Blocking layer422can include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, memory film418may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

As shown inFIG.4A, a well414(e.g., a P-well and/or an N-well) is formed in substrate402, and the source end of NAND memory string308is in contact with well414, according to some implementations, according to some implementations. For example, source line314may be coupled to well414to apply an erase voltage to well414, i.e., the source of NAND memory string308, during erase operations. In some implementations, NAND memory string308further includes a channel plug416at the drain end of NAND memory string308, e.g., as part of the drain of NAND memory string308.

As shown in the plan view ofFIG.4B, NAND memory strings308of memory cell array301can be arranged into blocks304by slit structures430(e.g., gate line slits (GLSs)), which electrically separate word lines318between adjacent blocks304, such that each block304can be individually controlled in read, program, and erase operations. In one example, each slit structure430may extend along the x-direction (e.g., the word line direction), and multiple blocks304may be arranged along they-direction (e.g., the bit line direction). In some implementations, each block304can be further divided into smaller areas (e.g., fingers434) by DSG cuts432, which electrically separate DSG lines313between adjacent fingers434, such that DSG lines313in different fingers434may be individually controlled in read and program operations. Also shown inFIGS.3and4A, in some implementations, as drain dummy line323(part of the top gate conductive layer) is above DSG line313, DSG cut432can also cut drain dummy line323into separate segments, e.g., multiple drain dummy lines323in multiple fingers434, respectively. That is, similar to DSG lines313, drain dummy lines323in different fingers434may be electrically separated by DSG cuts432and may be individually controlled in read and program operations.

Referring back toFIG.3, peripheral circuits302can be coupled to memory cell array301through bit lines316, word lines318, source lines314, SSG lines315, DSG lines313, and drain dummy lines323. Peripheral circuits302can include any suitable analog, digital, and mixed-signal circuits for facilitating the operations of memory cell array301by applying and sensing voltage signals and/or current signals to and from each target memory cell306through bit lines316, word lines318, source lines314, SSG lines315, DSG lines313, and drain dummy lines323. Peripheral circuits302can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technologies. For example,FIG.5illustrates some exemplary peripheral circuits including a page buffer/sense amplifier504, a column decoder/bit line driver506, a row decoder/word line driver508, a voltage generator510, control logic512, registers514, an interface516, and a data bus518. It is understood that in some examples, additional peripheral circuits not shown inFIG.5may be included as well.

Page buffer/sense amplifier504can be configured to read and program (write) data from and to memory cell array301according to the control signals from control logic512. In one example, page buffer/sense amplifier504may store one page of program data (write data) to be programmed into one page320of memory cell array301. In another example, page buffer/sense amplifier504may perform program verify operations to ensure that the data has been properly programmed into memory cells306coupled to selected word lines318. In still another example, page buffer/sense amplifier504may also sense the low power signals from bit line316that represents a data bit stored in memory cell306and amplify the small voltage swing to recognizable logic levels in a read operation. Column decoder/bit line driver506can be configured to be controlled by control logic512and select one or more NAND memory strings308by applying bit line voltages generated from voltage generator510.

Row decoder/word line driver508can be configured to be controlled by control logic512and select/deselect blocks304of memory cell array301and select/deselect word lines318of block304. Row decoder/word line driver508can be further configured to drive word lines318using word line voltages generated from voltage generator510. In some implementations, row decoder/word line driver508can also select/deselect and drive SSG lines315, DSG lines313, and drain dummy lines323as well.

Voltage generator510can be configured to be controlled by control logic512and generate the word line voltages (e.g., read voltage, program voltage, channel pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array301. As described below in detail, voltage generator510can also generate a drain dummy line voltage to be applied to drain dummy line323that are coupled to selected NAND memory strings308, which is high enough to ensure that drain dummy transistors322can be fully turned on even at the low temperatures during program operations. For example, the drain dummy line voltage may be greater than the DSG voltage to be applied to DSG lines313.

Control logic512can be coupled to each peripheral circuit described above and configured to control operations of each peripheral circuit. Registers514can be coupled to control logic512and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit. Interface516can be coupled to control logic512and act as a control buffer to buffer and relay control commands received from a host (e.g.,108inFIG.1) to control logic512and status information received from control logic512to the host. Interface516can also be coupled to column decoder/bit line driver506via data bus518and act as a data input/output (I/O) interface and a data buffer to buffer and relay the data to and from memory cell array301.

FIG.6illustrates subthreshold slopes of exemplary DSG transistors in different gate conductive layers and at different temperatures, according to some aspects of the present disclosure. The subthreshold slope is a feature of a metal-oxide-semiconductor field-effect transistor (MOSFET)'s drain current (Id)—gate voltage (Vg) characteristic. In the subthreshold region, the drain current behavior—though being controlled by the gate terminal—is similar to the exponentially decreasing current of a forward biased diode. Therefore, a plot of drain current versus gate voltage with drain, source, and bulk voltages fixed may exhibit approximately log linear behavior in this MOSFET operating regime. A device characterized by steep subthreshold slope exhibits a faster transition between off (low current) and on (high current) states. Its slope is the subthreshold slope. As shown inFIG.6, at the same temperate, either a high temperature (e.g., at 45° C.) or a low temperature (e.g., at 0° C.), the DSG transistors formed in the non-top gate conductive layers of the memory stack (non-top DSG, e.g., DSG transistors312inFIG.3) have a steeper subthreshold slope than the DSG transistors formed in the top gate conductive layer of the memory stack (top DSG, e.g., drain dummy transistors322inFIG.3). Thus, the non-top DSG may exhibits a faster transition between off (low current) and on (high current) states than the top DSG. As a result, the leakage current from the top DSG may be higher than that from the non-top DSG, which can increase the program voltage disturbance in unselected NAND memory strings during program operations.

Moreover, as shown inFIG.6, the threshold voltage (e.g., Vg@Id=0) of the top DSG more drastically increases as the temperature decreases, compared with that of the non-top DSG. Thus, the top DSG in a selected NAND memory string may not be fully turned on at the same DSG voltage when the operating temperature drops, thereby requiring a higher program voltage and/or more program voltage pulses, which may in turn increases both the program voltage disturbance in unselected NAND memory strings and channel pass voltage disturbance in selected NAND memory strings.

For example,FIG.7illustrates a program operation scheme for 3D NAND memory strings. 3D NAND memory device700includes a plurality of gate conductive layers in the vertical direction acting as word lines. 3D NAND memory device700further includes a set of lower dummy word lines704below word lines702and a set of upper dummy word lines706above word lines702. As shown inFIG.7, 3D NAND memory device700also includes a plurality of NAND memory strings708and710each extending vertically through word lines702and dummy word lines704and706. Each NAND memory string708or710includes memory cells coupled to word lines702, respectively, as well as dummy memory cells coupled to dummy word lines704and706, respectively.

As shown inFIG.7, 3D NAND memory device700also include SSG lines712and714through which NAND memory strings708and710extend vertically, respectively. Similarly, 3D NAND memory device700further include DSG lines716and718through which NAND memory strings708and710extend vertically, respectively. Each NAND memory string708or710also includes a respective SSG transistor below lower dummy word lines704and coupled to SSG lines712and714, respectively. Each NAND memory string708or710further includes a respective set of DSG transistors above upper dummy word lines706and coupled to DSG lines716and718, respectively. 3D NAND memory device700also includes bit lines722and724respectively coupled to the drains of NAND memory strings708and710. Thus, DSG lines716are between upper dummy word lines706and bit line722, and DSG lines718are between upper dummy word lines706and bit line724. That is, the DSG transistors coupled to DSG lines716and718inFIG.7include the top DSG as described above with respect toFIG.6, which has inferior subthreshold slope and temperature characteristics than the non-top DSG.

During the program operation of 3D NAND memory device700, a 0-V voltage is applied to both SSG lines712and714coupled to NAND memory string708and710, respectively. A positive bias DSG voltage Vdsg is applied to DSG line716coupled to NAND memory string708to select NAND memory string308, and a 0-V voltage is applied to DSG line718coupled to NAND memory string710to deselect NAND memory string710. Each word line702is sequentially programmed by subsequently applying a program voltage Vprogram to each word line702. For example, when programming memory cells coupled to a selected word line720, the program voltage is applied to selected word line720to program the memory cell of selected NAND memory string708coupled to selected word line720. When programming the memory cells coupled to selected word line720, each of the rest of word lines702is applied with a channel pass voltage Vpass to open the channel (e.g., semiconductor channel420inFIG.4A) of selected NAND memory string308, which enables the memory cell in selected NAND memory string708. Also, a set of dummy word line voltages are applied to each set of lower or upper dummy word lines704or706. As shown inFIG.7, a set of dummy word line voltages Vdmy_wl_1-Vdmy_wl_i are respectively applied to lower dummy word lines704, and another set of dummy word line voltages Vdmy_wl_1-Vdmy_wl_j are respectively applied to upper dummy word lines706.

During the program operation of 3D NAND memory device700, for unselected NAND memory string710, because the DSG transistors and SSG transistor at each end thereof are turned off, the channel of unselected NAND memory string710is floating. As each word line702is coupled to unselected NAND memory string710as well, the channel pass voltage applied to each of the rest of word lines702forms a channel coupling potential721in unselected NAND memory string710to suppress the programming of the memory cell in unselected NAND memory string710due to the program voltage applied to selected word line720. Channel coupling potential721is formed by channel coupling effect in unselected NAND memory string710, which is in a floating state, when the channel pass voltage is applied to the rest of word lines702. To achieve the desired suppression effect on the program voltage applied to selected word line720, the channel pass voltage needs to be large enough to generate channel coupling potential721that is comparable to the program voltage. However, for selected NAND memory string708, the channel pass voltage applied to word line702that has already been programmed (e.g., each word line702below selected word line720) may cause disturbance to the programmed memory cells if the channel pass voltage is too high, which is known as the “channel pass voltage disturbance” to selected NAND memory string708. On the other hand, for unselected NAND memory string710, if the program voltage is too high, channel coupling potential721may not effectively suppress the programming to the memory cell in unselected NAND memory string710, which is known as the “program voltage disturbance” to unselected NAND memory string710.

Because the DSG transistors of unselected NAND memory string710includes the top DSG described above with respect toFIG.6, the relatively high leakage current from the top DSG due to its less steep subthreshold slope can increase the program voltage disturbance in unselected NAND memory string710during the program operations. Moreover, because the DSG transistors of selected NAND memory string708also includes the top DSG described above with respect toFIG.6, the top DSG may not be fully turned on when the operating temperature drops, thereby requiring a higher program voltage and/or more program voltage pulses, which can in turn increases both the program voltage disturbance in unselected NAND memory string710and channel pass voltage disturbance in selected NAND memory string708.

Consistent with the scope of the present disclosure, the top DSG can be avoided in both selected NAND memory strings and unselected NAND memory strings during the program operations to decrease the program voltage disturbance and channel pass voltage disturbance because of the inferior electrical performance of the top DSG. For example,FIGS.8A and8Billustrate an exemplary program operation scheme for 3D NAND memory strings, according to some aspects of the present disclosure.FIG.9illustrates a timing diagram of the exemplary program operation scheme inFIGS.8A and8B, according to some aspects of the present disclosure. A 3D NAND memory device800inFIGS.8A and8Bmay be an example of memory device300inFIGS.3,4A,4B, and5, which include NAND memory strings808and810, which may be examples of NAND memory strings308.

As shown inFIG.8A, 3D NAND memory device800includes first NAND memory string808(a selected NAND memory string during program operations) and second NAND memory string810(an unselected NAND memory string during program operations), according to some implementations. 3D NAND memory device800can also include a first bit line822(a selected bit line during program operations) and a second bit line824(an unselected bit line during program operations) coupled to selected NAND memory string808and unselected NAND memory string810, respectively. 3D NAND memory device800can further include word lines802and dummy word lines804and806each extending laterally and coupled to selected NAND memory string808and unselected NAND memory string810. In some implementations, a set of lower dummy word lines804are below word lines802in the negative z-direction, i.e., towards the source ends of NAND memory strings808and810. In some implementations, a set of upper dummy word lines806are above word lines802in the positive z-direction, i.e., towards the drain ends of NAND memory strings808and810. 3D NAND memory device800can further include an SSG line812extending laterally and coupled to selected NAND memory string808and unselected NAND memory string810. As shown inFIG.8A, in some implementations, lower dummy word lines804are between SSG line812and word lines802in the vertical direction.

As shown inFIG.8A, 3D NAND memory device800can further include a first set of DSG lines816(selected DSG lines during program operations) each coupled to selected NAND memory string808, and a second set of DSG lines818(unselected DSG lines during program operations) each coupled to unselected NAND memory string810. That is, different from SSG line812that is coupled to both selected and unselected NAND memory strings808and810, DSG cuts (e.g.,432inFIGS.4A and4B) can separate a DSG line into selected DSG line816and unselected DSG line818coupled to selected and unselected NAND memory strings808and810, respectively, such that selected DSG line816and unselected DSG line818can be individually driven with different voltage signals during program operations.

Different from 3D NAND memory device700inFIG.7, 3D NAND memory device800can further include a first drain dummy line801(selected drain dummy line during program operations) coupled to selected NAND memory string808, and a second drain dummy line803(unselected drain dummy line during program operations) coupled to unselected NAND memory string810. Similar to selected and unselected DSG lines816and818, DSG cuts (e.g.,432inFIGS.4A and4B) can separate a drain dummy line into selected drain dummy line801and unselected drain dummy line803coupled to selected and unselected NAND memory strings808and810, respectively, such that selected drain dummy line801and unselected drain dummy line803can be individually driven with different voltage signals during program operations. In some implementations, selected drain dummy line801is between selected bit line822and selected DSG lines816in the vertical direction, and unselected drain dummy line803is between unselected bit line824and unselected DSG lines818in the vertical direction. As shown inFIG.8A, DSG lines816and818are above upper dummy word lines806and word lines802, and drain dummy lines801and803are above DSG lines816and818, according to some implementations. It is noted that drain dummy lines801and803are different from upper dummy word lines806at least because (1) they have different relative positions with respect to DSG lines816and818, i.e., drain dummy lines801and803are above DSG lines816and818, while upper dummy word lines806are below DSG lines816and818; and (2) selected drain dummy line801and unselected drain dummy line803are electrically separated and can be individually driven, while upper dummy word line806at the same level is a continuous line coupled to both selected and unselected NAND memory strings808and810.

It is understood that the spatial relationships (e.g., above, below, upper, lower, top, bottom, etc.) described herein with respect toFIGS.7,8A, and8Bmay use the substrate of 3D NAND memory device700or800as described above. Although the substrate of 3D NAND memory device700or800is not shown inFIGS.7,8A, and8B, it is understood that the source ends of NAND memory strings808and810may be toward the substrate, while the drain ends of NAND memory strings808and810may be away from the substrate. In other words, the source and drain ends of NAND memory strings808and810may be used as the references inFIGS.7,8A, and8Bto show the spatial relationships (e.g., above, below, upper, lower, etc.). For example, drain dummy line801may be above DSG lines816when drain dummy line801is more toward the drain end (or more far away from the source end) of NAND memory string808than DSG lines816, whereas upper dummy word lines806may be below DSG lines816when upper dummy word lines806are more toward the source end (or more far away from the drain end) of NAND memory string808than DSG lines816.

In some implementations, from top to bottom (e.g., along the negative z-direction), selected NAND memory string808includes a drain (selected drain) coupled to selected bit line822, a drain dummy transistor (selected drain dummy transistor) coupled to selected drain dummy line801, DSG transistors (selected DSG transistors) respectively coupled to selected DSG lines816, upper dummy memory cells respectively coupled to upper dummy word lines806, memory cells respectively coupled to word lines802, lower dummy memory cells respectively coupled to lower dummy word lines804, an SSG transistor coupled to SSG line812, and a source. Similarly, in some implementations, from top to bottom (e.g., along the negative z-direction), unselected NAND memory string810includes a drain (unselected drain) coupled to unselected bit line824, a drain dummy transistor (unselected drain dummy transistor) coupled to unselected drain dummy line803, DSG transistors (unselected DSG transistors) respectively coupled to unselected DSG lines818, upper dummy memory cells respectively coupled to upper dummy word lines806, memory cells respectively coupled to word lines802, lower dummy memory cells respectively coupled to lower dummy word lines804, an SSG transistor coupled to SSG line812, and a source.

Different from NAND memory strings708and710inFIG.7, selected NAND memory string808can further include the selected drain dummy transistor between the selected drain and the selected DSG transistor, and unselected NAND memory string810can further include the unselected drain dummy transistor between the unselected drain and the unselected DSG transistor. As described above with respect toFIGS.3,4A,4B, and6, the top DSG, which is in 3D NAND memory device700and has inferior electrical performance, can be avoided in 3D NAND memory device800, i.e., being replaced by the drain dummy transistors coupled to drain dummy lines801and803. In other words, each DSG transistor in 3D NAND memory device700is a non-top DSG, according to some implementations. It is understood that the number of DSG transistor in each NAND memory string808or810(the same as the number of drain dummy line801or803) is not limited to “1,” as shown inFIG.8A. For example, as shown inFIG.8B, 3D NAND memory device800may include a plurality selected drain dummy lines801coupled to selected NAND memory string808and a plurality of unselected drain dummy lines803coupled to unselected NAND memory string810. That is, NAND memory string808or810may include more than one drain dummy transistors. Nevertheless, drain dummy transistors and drain dummy lines801and803, as supposed to DSG transistors and DSG lines816and816, are formed in the top conductive layer of the memory stack of 3D NAND memory device800, according to some implementations.

Referring also toFIG.5, the peripheral circuits can be configured to perform a program operation on a target memory cell of selected NAND memory string808coupled to a selected word line820. To perform the program operation, column decoder/bit line driver506is configured to apply a select bit line voltage (e.g., 0-V, inFIG.9) to selected bit line822and a deselect bit line voltage (e.g., a positive bias voltage, such as the system voltage Vdd) to unselected bit line824, according to some implementations. To perform the program operation, row decoder/word line driver508is configured to apply an SSG voltage that is lower than the threshold voltage of the SSG transistors (e.g., 0-V, inFIG.9) to SSG line812to turn off the SSG transistors of both selected and unselected NAND memory strings808and810, according to some embodiments. Row decoder/word line driver508can be further configured to apply different DSG voltages to selected DSG lines816and unselected DSG lines818to turn on the selected DSG transistors of selected NAND memory string808and turn off the unselected DSG transistors of unselected NAND memory springs810. For example, row decoder/word line driver508may apply a positive bias DSG voltage Vdsg (e.g., inFIG.9) that is greater than the threshold voltage of the selected DSG transistors to selected DSG lines816, and apply a 0-V voltage (or any other voltage below the threshold voltage of the unselected DSG transistors) to unselected DSG lines818.

Different from the program operation scheme described above with respect toFIG.7, as shown inFIGS.8A and8B, row decoder/word line driver508can be further configured to apply a drain dummy line voltage Vdmy_d (e.g., inFIG.9) to selected drain dummy line(s)801to turn on the selected drain dummy transistor(s) coupled to selected drain dummy line(s)801. To overcome the inferior electrical performance of the drain dummy transistors (top DSG), for example, the less steep subthreshold slope, a higher gate voltage can be applied to the selected drain dummy transistor than the selected DSG transistor to ensure that the selected drain dummy transistors is fully turned on with a minimum leakage current. In some implementations, the drain dummy line voltage Vdmy_d applied to selected drain dummy line801(and the gate of the selected drain dummy transistor) is greater than the DSG voltage Vdsg applied to selected DSG line816(and the gate of the selected DSG transistor). To overcome the inferior electrical performance of the drain dummy transistors (top DSG), for example, the worse temperature characteristics, a gate voltage applied to the selected drain dummy transistors can be greater than the threshold voltage of the selected drain dummy transistor at the lower bound of the operating temperate range of 3D NAND memory device800(i.e., the maximum threshold volage in the operating temperate range). In some implementations, the drain dummy line voltage applied to selected drain dummy line801(and the gate of the selected drain dummy transistor) is greater than the threshold voltage of the selected drain dummy transistor at −40° C. to ensure that the selected drain dummy transistors of selected NAND memory string808can be fully turned on at any operating temperature. In some implementations, the drain dummy line voltage Vdmy_d is between 6 V and 8 V.

In case that more than one drain dummy transistor and drain dummy line801are formed, as shown inFIG.8B, row decoder/word line driver508can be configured to apply a set of drain dummy line voltages Vdmy_d_1 to Vdmy_d_k to drain drain dummy lines801, respectively, to turn on each of the drain dummy transistors. Each of the drain dummy line voltages Vdmy_d_1 to Vdmy_d_k is greater than the DSG voltage Vdsg, according to some implementations. In some implementations, each of the drain dummy line voltages Vdmy_d_1 to Vdmy_d_k is greater than the threshold voltage of the respective drain dummy transistor at the lower bound (e.g., −40° C.) of the operating temperate range of 3D NAND memory device800.

As to the unselected drain dummy transistor of unselected NAND memory string810, similar to the unselected DSG transistors, row decoder/word line driver508can be configured to apply a 0-V voltage (or any other voltage below the threshold voltage of the unselected drain dummy transistor) to unselected drain dummy line803to turn off the unselected drain dummy transistor of unselected NAND memory string810. As a result, the channel of unselected NAND memory string810can be turned off and floating during the program operation, and the channel of selected NAND memory string808can be turned on to allow programming on the target memory cell coupled to selected word line820.

To perform the program operation, row decoder/word line driver508can be further configured to apply a program voltage Vprogram (e.g., a positive bias voltage, inFIG.9) to selected word line820and a channel pass voltage Vpass (e.g., a positive bias voltage smaller than Vprogram, inFIG.9) to each unselected word line802. As a result, the target memory cell of selected NAND memory string808coupled to selected word line820can be programmed, while a channel coupling potential821can be formed in the channel of unselected NAND memory string810to suppress the programming to the memory cell of unselected NAND memory string810coupled to selected word line820. In some implementations, row decoder/word line driver508is further configured to apply a set of lower dummy word line voltages Vdmy_wl_1 to Vdmy_wl_i to lower dummy word lines804, respectively, and a set of upper dummy word line voltages Vdmy_wl_1 to Vdmy_wl_j (e.g., inFIG.9) to upper dummy word lines806, respectively. In some implementations, the upper dummy word line voltages Vdmy_wl_1 to Vdmy_wl_j are different from the drain dummy line voltage Vdmy_d. That is, different voltage signals can be applied to upper dummy word line806and drain dummy line801.

FIG.10illustrates a flowchart of a method1000for operating a memory device, according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein, such as memory devices300and800. Method1000may be implemented by peripheral circuit302, such as row decoder/word line driver508and column decoder/bit line driver506. It is understood that the operations shown in method1000may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.10.

Referring toFIG.10, method1000starts at operation1002, in which a first bit line voltage (a select bit line voltage, e.g., 0-V) is applied to the selected bit line. In some implementations, a second bit line voltage (a deselect bit line voltage, e.g., a positive bias voltage) is applied to the unselected bit line. For example, in a program operation, column decoder/bit line driver506may apply a select bit line voltage (e.g., 0 V) to selected bit line822coupled to the drain of selected NAND memory string808, and apply a deselect bit line voltage (e.g., Vdd) to unselected bit line824coupled to the drain of unselected NAND memory string810.

Method1000proceeds to operation1004, as illustrated inFIG.10, in which a DSG voltage is applied to the selected DSG line to turn on the selected DSG transistor. In some implementations, a 0-V voltage (or any suitable voltage smaller than the threshold voltage of the DSG transistor) is applied to the unselected DSG line to turn off the unselected DSG transistor. For example, in the program operation, row decoder/word line driver508may apply a positive bias DSG voltage Vdsg greater than the threshold voltage of the DSG transistor to selected DSG line816coupled to the DSG transistor of selected NAND memory string808, and apply a 0-V DSG voltage (or any suitable voltage smaller than the threshold voltage of the DSG transistor) to unselected DSG line818coupled to the DSG transistor of unselected NAND memory string810.

Method1000proceeds to operation1006, as illustrated inFIG.10, in which a drain dummy line voltage is applied to the selected drain dummy line to turn on the selected drain dummy transistor. The drain dummy line voltage can be greater than the DSG voltage. In some implementations, the drain dummy line voltage is greater than the threshold voltage of the selected drain dummy transistor at the lower bound of the operating temperate range of the memory device (e.g., −40° C.). In some implementations, a 0-V voltage (or any suitable voltage smaller than the threshold voltage of the unselected drain dummy transistor) is applied to the unselected drain dummy line to turn off the unselected drain dummy transistor. For example, in the program operation, row decoder/word line driver508may apply a positive bias drain dummy voltage Vdmy_d greater than the DSG voltage Vdsg to selected drain dummy line801coupled to the drain dummy transistor of selected NAND memory string808, and apply a 0-V DSG voltage (or any suitable voltage smaller than the threshold voltage of the drain dummy transistor) to unselected drain dummy line803coupled to the drain dummy transistor of unselected NAND memory string810. In some implementations, the drain dummy line voltage Vdmy_d is between 6 V and 8 V.

Method1000proceeds to operation1008, as illustrated inFIG.10, in which a dummy word line voltage is applied to the dummy word line. The dummy word line voltage can be different from the drain dummy line voltage. For example, in the program operation, row decoder/word line driver508may apply a set of positive bias dummy word line voltages Vdmy_wl_1 to Vdmy_wl_j to upper dummy word lines806coupled to the dummy memory cells of both selected NAND memory string808and unselected NAND memory string810. DSG lines816may be between upper dummy word lines806and drain dummy line801.

Method1000proceeds to operation1010, as illustrated inFIG.10, in which a program voltage is applied to the selected word line to program the target memory cell coupled to the selected word line and the selected memory string. For example, in the program operation, row decoder/word line driver508may apply a positive bias program voltage Vprogram to selected word line820to program the target memory cell of selected NAND memory string808.

Method1000proceeds to operation1012, as illustrated inFIG.10, in which a channel pass voltage is applied to the unselected word lines. The program voltage can be greater than the channel pass voltage. For example, in the program operation, row decoder/word line driver508may apply a positive bias channel pass voltage Vpass that is smaller than the program voltage Vprogram to each unselected word line802.

According to one aspect of the present disclosure, a memory device includes a first memory string including a first drain, a first DSG transistor, first memory cells, and a first drain dummy transistor between the first drain and the first DSG transistor. The memory device also includes a first bit line coupled to the first drain, a first drain dummy line coupled to the first drain dummy transistor, a first DSG line coupled to the first DSG transistor, word lines respectively coupled to the first memory cells, and a peripheral circuit configured to perform a program operation on a target memory cell of the first memory cells coupled to a selected word line of the word lines. To perform the program operation, the peripheral circuit includes a bit line driver coupled to the first bit line and configured to apply a first bit line voltage to select the first bit line, and a word line driver coupled to the first drain dummy line and the first DSG line and configured to apply a DSG voltage to the first DSG line to turn on the first DSG transistor, and apply a drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The drain dummy line voltage is greater than the DSG voltage.

In some implementations, the drain dummy line voltage is greater than a threshold voltage of the first drain dummy transistor at a lower bound of an operating temperate range of the memory device. In some implementations, the lower bound of the operating temperate range is −40° C.

In some implementations, the first memory string is a 3D NAND memory string, and the first DSG line is above the word lines, and the first drain dummy line is above the first DSG line.

In some implementations, the first memory cells include a dummy memory cell between the first DSG transistor and the target memory cell, the word lines include a dummy word line coupled to the dummy memory cell, and the word line driver is coupled to the dummy word line and further configured to apply a dummy word line voltage to the dummy word line. The dummy word line voltage can be different from the drain dummy line voltage.

In some implementations, to perform the program operation, the word line driver is coupled to the word lines and further configured to apply a program voltage to the selected word line, and apply a channel pass voltage to each of a rest of the word lines. The program voltage can be greater than the channel pass voltage.

In some implementations, the memory device further includes a second memory string including a second drain, a second DSG transistor, a plurality of second memory cells, and a second drain dummy transistor between the second drain and the second DSG transistor; a second bit line coupled to the second drain; a second drain dummy line coupled to the second drain dummy transistor, and a second DSG line coupled to the second DSG transistor. In some implementations, the plurality of word lines are respectively coupled to the second memory cells. In some implementations, to perform the program operation, the bit line driver is coupled to the second bit line and further configured to apply a second bit line voltage to deselect the second bit line, and the word line driver is coupled to the second DSG line and the second drain dummy line and further configured to apply a 0-V voltage to the second DSG line and the second drain dummy line.

In some implementations, the first and second DSG lines are electrically separated, and the first and second drain dummy lines are electrically separated.

According to another aspect of the present disclosure, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a first memory string including a first drain, a first DSG transistor, a plurality of first memory cells, and a first drain dummy transistor between the first drain and the first DSG transistor. The memory device also includes a first bit line coupled to the first drain, a first drain dummy line coupled to the first drain dummy transistor, a first DSG line coupled to the first DSG transistor, a plurality of word lines respectively coupled to the first memory cells, and a peripheral circuit configured to perform a program operation on a target memory cell of the first memory cells coupled to a selected word line of the word lines. To perform the program operation, the peripheral circuit includes a bit line driver coupled to the first bit line and configured to apply a first bit line voltage to select the first bit line, and a word line driver coupled to the first drain dummy line and the first DSG line and configured to apply a DSG voltage to the first DSG line to turn on the first DSG transistor, and apply a drain dummy line voltage to the first drain dummy line to turn on the first drain dummy transistor. The drain dummy line voltage is greater than the DSG voltage.

In some implementations, the system further includes a host coupled to the memory controller and configured to send or receive the data.

In some implementations, the drain dummy line voltage is greater than a threshold voltage of the first drain dummy transistor at a lower bound of an operating temperate range of the memory device. In some implementations, the lower bound of the operating temperate range is −40° C.

In some implementations, the first memory string is a 3D NAND memory string, and the first DSG line is above the word lines, and the first drain dummy line is above the first DSG line.

In some implementations, the first memory cells include a dummy memory cell between the first DSG transistor and the target memory cell, the word lines include a dummy word line coupled to the dummy memory cell, and the word line driver is coupled to the dummy word line and further configured to apply a dummy word line voltage to the dummy word line. The dummy word line voltage can be different from the drain dummy line voltage.

In some implementations, to perform the program operation, the word line driver is coupled to the word lines and further configured to apply a program voltage to the selected word line, and apply a channel pass voltage to each of a rest of the word lines. The program voltage can be greater than the channel pass voltage.

In some implementations, the memory device further includes a second memory string including a second drain, a second DSG transistor, a plurality of second memory cells, and a second drain dummy transistor between the second drain and the second DSG transistor; a second bit line coupled to the second drain; a second drain dummy line coupled to the second drain dummy transistor, and a second DSG line coupled to the second DSG transistor. In some implementations, the plurality of word lines are respectively coupled to the second memory cells. In some implementations, to perform the program operation, the bit line driver is coupled to the second bit line and further configured to apply a second bit line voltage to deselect the second bit line, and the word line driver is coupled to the second DSG line and the second drain dummy line and further configured to apply a 0-V voltage to the second DSG line and the second drain dummy line.

In some implementations, the first and second DSG lines are electrically separated, and the first and second drain dummy lines are electrically separated.

According to still another aspect of the present disclosure, a method for operating a memory device is provided. The memory device includes a first memory string including a first drain, a first DSG transistor, a plurality of first memory cells, and a first drain dummy transistor between the first drain and the first DSG transistor; a first bit line coupled to the first drain; a first drain dummy line coupled to the first drain dummy transistor; a first DSG line coupled to the first DSG transistor; and a plurality of word lines respectively coupled to the first memory cells. A program operation is performed on a target memory cell of the first memory cells coupled to a selected word line of the word lines. To perform the program operation, a first bit line voltage is applied to select the first bit line, a DSG voltage is applied to the first DSG line to turn on the first DSG transistor, and a drain dummy line voltage is applied to the first drain dummy line to turn on the first drain dummy transistor. The drain dummy line voltage is greater than the DSG voltage.

In some implementations, the drain dummy line voltage is greater than a threshold voltage of the first drain dummy transistor at a lower bound of an operating temperate range of the memory device. In some implementations, the lower bound of the operating temperate range is −40° C.

In some implementations, the first memory string is a 3D NAND memory string, and the first DSG line is above the word lines, and the first drain dummy line is above the first DSG line.

In some implementations, the first memory cells include a dummy memory cell between the first DSG transistor and the target memory cell, and the word lines include a dummy word line coupled to the dummy memory cell. In some implementations, to perform the program operation, a dummy word line voltage is applied to the dummy word line. The dummy word line voltage can be different from the drain dummy line voltage.

In some implementations, to perform the program operation, a program voltage is applied to the selected word line, and a channel pass voltage is applied to each of a rest of the word lines. The program voltage can be greater than the channel pass voltage.

In some implementations, the memory device further includes a second memory string including a second drain, a second DSG transistor, a plurality of second memory cells, and a second drain dummy transistor between the second drain and the second DSG transistor; a second bit line coupled to the second drain; a second drain dummy line coupled to the second drain dummy transistor, and a second DSG line coupled to the second DSG transistor. In some implementations, the plurality of word lines are respectively coupled to the second memory cells. In some implementations, to perform the program operation, a second bit line voltage is applied to deselect the second bit line, and a 0-V voltage is applied to the second DSG line and the second drain dummy line.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.