Patent ID: 12260087

DETAILED DESCRIPTION

The invention aims at providing a technical solution of a configurable, flexible, and adjustable input/output (I/O) interface circuit applied into an electronic device such as a flash memory controller chip circuit (not limited) to meet different requirements of different flash memory products and different flash memory standard specifications or different standard versions by using the same I/O circuit design. The I/O circuit design is associated with an output driving and input on-die termination/terminated (ODT) stage circuit mechanism which can be used as either an output driving stage circuit or an input ODT stage circuit.

FIG.1is a diagram of a circuit block of an input/output (I/O) interface circuit103of an electronic device100such as a flash memory controller chip circuit according to an embodiment of the invention.

The flash memory controller100comprises at least one I/O signal port, a processor circuit105, and at least one I/O interface circuit103corresponding to the at least one I/O signal port. The flash memory controller100is externally coupled to the flash memory101through the I/O signal port which may be a physical signal pad/pin. For example, the flash memory controller100may comprise multiple physical I/O signal pads/pins and multiple I/O interface circuits103respectively corresponding to the multiple physical I/O signal pads/pins. In addition, the I/O interface circuit103comprises a controlling circuit110, a transmission and on-die termination (TX/ODT) circuit115, a specific node N1coupled to the I/O signal port, a receiver (RX) circuit120, a retention circuit125, a TX node, a RX node, and multiple control nodes respectively coupled to the control signals TE, TR_DU, TR_DD, DU, and DD.

The processor circuit105, which can execute/perform at least one firmware program, is arranged to transmit or send a transmission signal STX to the flash memory101through the I/O signal port and the I/O interface circuit103, wherein the transmission signal STX may carry a digital waveform having a high level and a low level. The transmission signal STX, to be outputted from the I/O signal port, is transmitted to the I/O interface circuit103through the TX node and then is temporarily kept by the retention circuit125. The transmission signal STX then is transmitted from the retention circuit125into the I/O signal port through the TX/ODT circuit115which is controlled by the controlling circuit110to operate as an output driving stage circuit for driving and outputting the transmission signal STX into the flash memory101through the I/O signal port.

Alternatively, when the flash memory101sends a reception signal SRX into the flash memory controller100through the I/O signal port, the controlling circuit110controls the TX/ODT circuit115operating as an input ODT stage circuit for providing a corresponding matching termination resistance for the reception signal SRX that may carry a digital waveform having a high level and a low level and is to be received by the RX circuit120and retention circuit125. The reception signal SRX is also temporarily kept by the retention circuit125and then transmitted from the retention circuit125into the processor circuit105through the RX node.

The transmission signal STX or the reception signal SRX may be used to carry at least one of communication information, flash memory commands, address information, and data of a specific data unit size such as a page data, a block data, and so on.

The TX/ODT circuit115is arranged to operate as either the output driving stage circuit or the input ODT stage circuit, and the controlling circuit110is arranged for receiving at least one control signal such as TE, TR_DU, TR_DD, DU, and/or DD sent from the firmware program running on the processor circuit105so as to control TX/ODT circuit115providing the capability of output driving or input ODT resistance matching.

Further, in one embodiment, the controlling circuit110can control the TX/ODT circuit115forming a first tapped termination structure in response to a first product specification requirement and controls the TX/ODT circuit115forming a second tapped termination structure, different from the first tapped terminal structure, in response to a second product specification requirement. In one embodiment, the first tapped termination structure is a center tapped termination (CTT) structure, and the second tapped termination structure is a low tapped termination (LTT) structure. For example (but not limited), the first product specification requirement defines the NV-DDR3 data interface, and the second product specification requirement defines the NV-LPDDR4 data interface.

Further, in one embodiment, the controlling circuit110may control the TX/ODT circuit115generating and providing different matching termination resistances for the I/O signal port in response to different product specification requirements when the TX/ODT circuit115is used as the input on-die termination stage circuit.

Further, the control signals TE, TR_DU, TR_DD, DU, and/or DD can be preset or adjusted by the firmware program based on a user's design requirements. Thus, the circuit design becomes more flexible and configurable.

Refer toFIG.2.FIG.2is a circuit diagram of the TX/ODT circuit115ofFIG.1according to an embodiment of the invention. InFIG.2, the TX/ODT circuit115is used as a transmitter circuit (i.e. the output driving stage circuit) when the flash memory controller100operates under a signal transmission mode in which the I/O signal port is used as an output port, and it is used as an receiver (RX) impedance matching circuit such as the input ODT stage circuit when the flash memory controller100operates under a signal reception mode in which the I/O signal port is used as an input port.

The TX/ODT circuit115for example comprises a plurality of impedance circuits1151_0,1151_1, . . . ,1151_N, a plurality of first multiplexers1152_0,1152_1, . . . ,1152_N, and a plurality of second multiplexers1153_0,1153_1, . . . ,1153_N, and the specific node N1to be coupled between the retention circuit125and the I/O signal port.

InFIG.2, the plurality of impedance circuits1151_0,1151_1, . . . ,1151_N may respectively comprise a plurality of first resistor units RU_0, RU_1, . . . , RU_N, a plurality of first switch units SWU_0, SWU_1, . . . , SWU_N, a plurality of second resistor units RD_0, RD_1, . . . , RD_N, a plurality of second switch units SWD_0, SWD_1, . . . , SWD_N. The specific node N1is coupled between the first resistor units RU_0, RU_1, . . . , RU_N and the second resistor units RD_0, RD_1, . . . , RD_N. In addition, each impedance circuit1151_0,1151_1, . . . ,1151_N equivalently comprises a corresponding first switch unit, a corresponding first resistor unit, a corresponding second switch unit, and a corresponding second resistor unit. The resistances of the different impedance circuits may be different from each other.

Each corresponding first multiplexer1152_0,1152_1, . . . ,1152_N has a first input coupled to and arranged for receiving a first control signal such as a corresponding bit portion signal of the control signal TR_DU, a second input coupled to and arranged for receiving a second control signal such as a corresponding bit portion signal of the control signal DU, a control input coupled to a setting signal such as the control signal TE, and an output for transmitting and outputting the selected bit portion signal based on the setting signal TE to turn on/off the corresponding first switch unit. For example (but not limited), the first multiplexer1152_0selects the bit portion signal TR_DU[0] of the control signal TR_DU as the control signal for turning on/off the first switch unit SWU_0when the setting signal TE indicates the logic level ‘1’, and it selects the bit portion signal DU[0] of the control signal DU as the control signal for turning on/off the first switch unit SWU_0when the setting signal TE indicates the logic level ‘0’. For example (but not limited), the first switch unit SWU_0is turned on to become closed by the bit portion signal TR_DU[0] indicating the logic level ‘1’ or by the bit portion signal DU[0] indicating the logic level ‘1’, and it is turned off to become open by the bit portion signal TR_DU[0] indicating the logic level ‘0’ or by the bit portion signal DU[0] indicating the logic level ‘0’. The operations of the other first multiplexers1152_1, . . . ,1152_N and the other first switch units SWU_1, . . . , SWU_N are similar to the above-mentioned operations of the first multiplexer1152_0and first switch unit SWU_0, and are not detailed for brevity.

Similarly, each corresponding second multiplexer1153_0,1153_1, . . . ,1153_N has a first input coupled to and arranged for receiving a third control signal such as a corresponding bit portion signal of the control signal TR_DD, a second input coupled to and arranged for receiving a fourth control signal such as a corresponding bit portion signal of the control signal DD, a control input coupled to the setting signal such as the control signal TE, and an output for transmitting and outputting the selected bit portion signal based on the setting signal TE to turn on/off the corresponding second switch unit. For example (but not limited), the second multiplexer1153_0selects the bit portion signal TR_DD[0] of the control signal TR_DD as the control signal for turning on/off the second switch unit SWD_0when the setting signal TE indicates the logic level ‘1’, and it selects the bit portion signal DD[0] of the control signal DD as the control signal for turning on/off the second switch unit SWD_0when the setting signal TE indicates the logic level ‘0’. For example (but not limited), the second switch unit SWD_0is turned on to become closed by the bit portion signal TR_DD[0] indicating the logic level ‘1’ or by the bit portion signal DD[0] indicating the logic level ‘1’, and it is turned off to become open by the bit portion signal TR_DD[0] indicating the logic level ‘0’ or by the bit portion signal DD[0] indicating the logic level ‘0’. The operations of the other second multiplexers1153_1, . . . ,1153_N and the other second switch units SWD_1, . . . , SWD_N are similar to the above-mentioned operations of the second multiplexer1153_0and second switch unit SWD_0, and are not detailed for brevity.

In the impedance circuit1151_0, inFIG.2, the first switch unit, e.g. SWU_0, and the first resistor unit, e.g. RU_0, are coupled in series and disposed between the first reference level such as a supply reference voltage level VREF and the specific node N1(connected to the I/O signal port and the coupled to the retention circuit125) if the first switch unit, e.g. SWU_0, is at the closed state. The positions of the first switch unit, e.g. SWU_0, and the first resistor unit, e.g. RU_0, can be exchanged in other embodiments. In addition, the second switch unit, e.g. SWD_0, and the second resistor unit, e.g. RD_0, are coupled in series and disposed between the second reference level such as the ground level and the specific node (connected to the I/O signal port and the coupled to the retention circuit125) if the second switch unit, e.g. SWD_0, is at the closed state. The positions of the second switch unit, e.g. SWD_0, and the second resistor unit, e.g. RD_0, can be exchanged in other embodiments. The operations and circuit connections/structures of the circuit elements of the other impedance circuits are similar to those of the impedance circuit1151_0and are not detailed for brevity.

In one scenario example, when the TX/ODT circuit115is used as the input ODT stage circuit for the RX circuit120or the reception signal SRX if the I/O interface circuit103operates under a signal reception transmission mode (i.e. RX mode), the setting signal TE, sent from the processor circuit105and then outputted by the controlling circuit110, indicates the logic level/information ‘1’. In this situation the on/off states of the first switch units SWU_0, SWU_1, . . . , SWU_N are respectively controlled by the bit portion signals TR_DU[0], TR_DU[1], . . . , TR_DU[N], and the on/off states of the second switch units SWD_0, SWD_1, . . . , SWD_N are respectively controlled by the bit portion signals TR_DD[0], TR_DD[1], . . . , TR_DD[N]. Thus, the processor circuit105can send the two control signals TR_DU and TR_DD to control the TX/ODT circuit115providing/generating a better or optimal matching termination resistance value for the reception signal SRX which is to be received by the RX circuit120through the I/O signal port from the flash memory101.

For example (but not limited), the first switch units SWU_0, SWU_1, . . . , SWU_N and second switch units SWD_0, SWD_1, . . . , SWD_N may be implemented by using MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) respectively. In one embodiment, when the processor circuit105is arranged to control the TX/ODT circuit115operating in the CTT structure mode of the input ODT stage circuit, at least one first switch unit (e.g. SWU_0) and at least one second switch unit (e.g. SWD_0) disposed within at least one the same impedance circuit are used as at least one pull-up MOS transistor and at least one pull-down MOS transistor, and may be controlled by the corresponding bit portion signals TR_DU[0] and TR_DD[0] to be at the closed state. In another embodiment, when the processor circuit105is arranged to control the TX/ODT circuit115operating in the LTT structure mode of the input ODT stage circuit, at least one the first switch unit (e.g. SWU_0) and at least one the second switch unit (e.g. SWD_0) disposed within at least one the same impedance circuit may be controlled by the corresponding bit portion signals TR_DU[0] and TR_DD[0] to be at the open state and the closed state respectively; that is, the first switch unit (e.g. SWU_0) is open, and the at least one the second switch unit (e.g. SWD_0) is used as at least one pull-down MOS transistor. By doing so, the processor circuit105(or the flash memory controller100) can operate in the CTT mode or the LTT mode dynamically in response to the different product specification requirements and/or different specification standard versions. The circuit design or configuration is flexible and configurable.

Alternatively, in another example scenario, when the TX/ODT circuit115is used as the output driving stage circuit for the transmission signal STX if the I/O interface circuit103operates under a signal transmission mode (i.e. TX mode), the setting signal TE, sent from the processor circuit105and then outputted by the controlling circuit110, indicates the logic level/information ‘0’. Thus in this situation the on/off states (or conductance states) of the first switch units SWU_0, SWU_1, . . . , SWU_N are respectively controlled by the bit portion signals DU[0], DU[1], . . . , DU[N], and the on/off states (or conductance states) of the second switch units SWD_0, SWD_1, . . . , SWD_N are respectively controlled by the bit portion signals DD[0], DD[1], . . . , DD[N]. Thus, the processor circuit105can send the two control signals DU and DD to control the TX/ODT circuit115as a better or optimal signal driving circuit to drive and output the transmission signal STX into the flash memory101through the I/O signal port.

For example (but not limited), similarly, the first switch units SWU_0, SWU_1, . . . , SWU_N and second switch units SWD_0, SWD_1, . . . , SWD_N may be implemented by using MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) respectively. In one embodiment, when the processor circuit105is arranged to control the TX/ODT circuit115operating in the CTT structure mode of the output driving stage circuit, at least one first switch unit (e.g. SWU_0) and at least one second switch unit (e.g. SWD_0) disposed within at least one the same impedance circuit are used as at least one pull-up MOS transistor and at least one pull-down MOS transistor, and may be controlled by the corresponding bit portion signals DU[0] and DD[0] respectively; in this condition, the at least one first switch unit (e.g. SWU_0) and at least one second switch unit (e.g. SWD_0) can be used to replace the functions and operations of the pull-up and pull-down MOS transistors of a conventional scheme. That is, the at least one first switch unit (e.g. SWU_0) and at least one second switch unit (e.g. SWD_0) can be used as the role of an output driver with an input ODT circuit in the CTT structure mode.

In another embodiment, when the processor circuit105is arranged to control the TX/ODT circuit115operating in the LTT structure mode of the output driving stage circuit, at least one the first switch unit (e.g. SWU_0) and at least one the second switch unit (e.g. SWD_0) disposed within at least one the same impedance circuit are used as at least one pull-up MOS transistor and at least one pull-down MOS transistor, and may be controlled by the corresponding bit portion signals DU[0] and DD[0]. Similarly, in this condition, the at least one first switch unit (e.g. SWU_0) and at least one second switch unit (e.g. SWD_0) can be used to replace the functions and operations of the pull-up and pull-down MOS transistors of the conventional scheme. That is, the at least one second switch unit (e.g. SWD_0) can be used as the role of an output driver with an input ODT circuit in the LTT structure mode. By doing so, the processor circuit105(or the flash memory controller100) can operate in the CTT mode or the LTT mode dynamically in response to the different product specification requirements and/or different specification standard versions. The circuit design or configuration is flexible and configurable.

In one embodiment, the resistances of the first resistor units RU_0, RU_1, . . . , RU_N may be different from each other, and the resistances of the second resistor units RD_0, RD_1, . . . , RD_N may be different from each other. In addition, the resistances of a first resistor unit and a second resistor unit in the same impedance circuit may be equal or different in response to the design of a user.

Based on the above operations, in response to the user's different requirements for the different product specifications, the processor circuit105can generate and send the control signals such as TR_DU and TR_DD carrying different bit portion information for the different product specifications into the I/O interface circuit103so as to control the TX/ODT circuit115providing a first matching termination resistance for the reception signal SRX in response to a first product specification or providing a second matching termination resistance for the reception signal SRX in response to a second product specification which different from the first product specification. Similarly, the processor circuit105may generate and send the control signals such as DU and DD carrying different bit portion information for the different product specifications into the I/O interface circuit103so as to control the TX/ODT circuit115providing a third matching termination resistance for the transmission signal STX in response to the first product specification or providing a fourth matching termination resistance for the transmission signal STX in response to the second product specification which different from the first product specification. It is flexible and configurable for the design in response to the different product specifications when the flash memory controller100is applied into and manufactured as different products.

FIG.3is a circuit diagram of the TX/ODT circuit115according to another embodiment of the invention. InFIG.3, the TX/ODT circuit115comprises six impedance circuits1151_0,1151_1,1151_2,1151_3,1151_4,1151_5, six corresponding first multiplexers1152_0,1152_1,1152_2,1152_3,1152_4,1152_5, and six corresponding second multiplexers1153_0,1153_1,1153_2,1153_3,1153_4,1153_5. Each impedance circuits1151_0,1151_1,1151_2,1151_3,1151_4,1151_5comprises the corresponding circuit elements as shown inFIG.3and are not detailed for brevity. For example (but not limited), the resistances of the first resistor units and second resistor units are shown in the following table:

Resistor unitsConfigured Resistance ValuesRU_0, RD_0RRU_1, RD_1R2RU_2, RD_2R4RU_3, RD_3R8RU_4, RD_4R16RU_5, RD_5R32

‘R’ in the table indicates a configured reference resistance value. In this example, the resistances of the first resistor unit and second resistor unit disposed in the same impedance circuit are configured to be identical; this is not intended to be a limitation. In addition, the resistances of the first resistor units respectively disposed in the different impedance circuits are configured based on the plurality of weights of a binary numeration system, e.g.,

120,121,122,123,124,125.
Similarly, the resistances of the second resistor units respectively disposed in the different impedance circuits are configured based on the plurality of weights of a binary numeration system, e.g.,

120,121,122,123,124,125.
By doing so, the processor circuit105can for example control the states of the first switch units SWU_0, SWU_1, SWU_2, SWU_3, SWU_4, SWU_5to provide different resultant resistance value. For example (but not limited), the resultant resistance value of all the first resistor units inFIG.3may be equal to R if only one the switch unit SWU_0is closed and the other switch units SWU_1, SWU_2, SWU_3, SWU_4, SWU_5are open. The resultant resistance value of all the first resistor units inFIG.3may be equal to R/2 if only the switch unit SWU_1is closed and the other switch units SWU_0, SWU_2, SWU_3, SWU_4, SWU_5are open. The resultant resistance value of all the first resistor units inFIG.3may be equal to R/3 if only the two switch units SWU_0, SWU_1are closed and the other switch units SWU_2, SWU_3, SWU_4, SWU_5are open. The resultant resistance value of all the first resistor units inFIG.3may be equal to R/4 if only the switch unit SWU_2is closed and the other switch units SWU_0, SWU_1, SWU_3, SWU_4, SWU_5are open. Similarly, the resultant resistance value of all the first resistor units inFIG.3can be R/5 if only the switch unit SWU_0, SWU_2are closed and the other switch units SWU_1, SWU_3, SWU_4, SWU_5are open. Similarly, the resultant resistance value of all the first resistor units inFIG.3can be

R6⁢3
if all the first switch units are closed and no first switch units are open. By doing so, the resultant resistance value of all the first resistor units inFIG.3can be at the 64-levels control capability range which range from the maximum resistance level R to the minimum resistance level

R6⁢3.
Identically, the resultant resistance value of all the second resistor units inFIG.3can be at the 64-levels control capability range which range from the maximum resistance level R to the minimum resistance level

R6⁢3.
This effectively meets the different signal matching requirements of the transmission signal STX and the reception signal SRX. This also effectively reduces the signal reflection, and the signal quality can be significantly improved. The circuit cost can be reduced as well as the circuit design can become more flexible, scalable, and adjustable.

FIG.4is a flowchart diagram of the operations of the I/O interface circuit103inFIG.1according to an embodiment of the invention. Provided that substantially the same result is achieved, the steps of the flowchart shown inFIG.4need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate. Steps are detailed in the following:Step S405: Start;Step S410: Provide a transmission and on-die termination circuit operating as either an output driving stage circuit or an input on-die termination stage circuit;Step S415: Receive at least one control signal sent from a processor circuit;Step S417: Determine which mode the I/O interface circuit operates;Step S420: Use the at least one control signal to control the transmission and on-die termination circuit as the output driving stage circuit transferring and driving a transmission signal, sent from the processor circuit of the flash memory controller, to the flash memory through the I/O signal port;Step S425: Use the at least one control signal to control the transmission and on-die termination circuit as the input on-die termination stage circuit generating and providing a matching termination resistance for the I/O signal port; andStep S430: End.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.