Patent ID: 12230353

DETAILED DESCRIPTION

Embodiments provide a bridge chip, a semiconductor storage device, and a memory system capable of controlling a separation operation while keeping a distribution order.

In general, according to one embodiment, a bridge chip includes a first selection circuit, a second selection circuit, and a control circuit. The first selection circuit determines an output destination of input data and an input flag indicating whether the input data is valid or invalid based on a first selection signal. The second selection circuit determines an output destination of the input data and the input flag output from the first selection circuit based on a second selection signal. The control circuit generates the first selection signal and the second selection signal, and outputs the first selection signal and the second selection signal to the first selection circuit and the second selection circuit, respectively.

Hereinafter, embodiments will be described with reference to drawings.

First Embodiment

FIG.1is a block diagram showing an example of a configuration of a memory system according to a first embodiment. A memory system MS of at least one embodiment includes a controller1and a semiconductor storage device2. The memory system MS can be connected to a host. The host is, for example, an electronic device such as a personal computer and a portable terminal.

The semiconductor storage device2includes a bridge chip3and two memory chips4aand4b. The bridge chip3is disposed between the controller1and the two memory chips4aand4b. With such a configuration, the data transfer rate between the controller1and the memory chips4aand4bis improved almost twice as much as that in a configuration in which the controller1and the memory chips4aand4bare directly connected.

The semiconductor storage device2includes two memory chips4aand4b, but may have three or more memory chips. The data transfer rate between the controller1and three or more memory chips can be enhanced at a rate corresponding to the number of memory chips. Each of the bridge chip3and the memory chips4aand4bis formed as a semiconductor chip. In the semiconductor storage device2, the bridge chip3and the memory chips4aand4bmay be provided as different packages, or may be provided as a multi-chip package (MCP) in which the bridge chip3, the memory chips4aand4bare stacked. The memory chips4aand4bare memory chips of a nonvolatile memory such as a NAND type flash memory.

The controller1controls writing of data to the memory chips4aand4baccording to a write request from the host. The controller1controls reading of data from the memory chips4aand4baccording to a read request from the host. The configuration of the memory system MS shown inFIG.1shows each block related to a write operation and a signal transmitted/received between the blocks among the configurations related to writing of data to the semiconductor storage device2using the controller1.

The bridge chip3includes a clock generator11, a control device12, a controller side interface13, a FIFO buffer14, a demultiplexer15, and memory side interfaces16aand16b.

The clock generator11generates a control clock CK0, a first operation clock CK1, and a second operation clock CK2. The second operation clock CK2is a clock obtained by dividing the first operation clock CK1by two.

The clock generator11outputs the control clock CK0to the control device12. The clock generator11outputs the first operation clock CK1to the FIFO buffer14and the demultiplexer15, and outputs the second operation clock CK2to the demultiplexer15and the memory side interfaces16aand16b.

The control device12controls each block in the bridge chip3based on the control clock CK0. The control device12generates a reset signal RN and outputs the generated reset signal RN to the demultiplexer15. The control device12performs the reset by setting the reset signal RN to a low level for a certain period, and then releases the reset by raising the reset signal RN to a high level.

The transmission and reception of signals between the controller1and the semiconductor storage device2is, for example, specified by the Toggle standard. The controller1transfers 8-bit data DQ[7:0] to the semiconductor storage device2in a double data rate (DDR) format synchronized with both the rising and falling edges of a data strobe signal DQS according to the Toggle standard. The 8-bit data is input to the controller side interface13. The data strobe signal DQS is input to the controller side interface13and the FIFO buffer14.

The controller side interface13converts the 8-bit data DQ [7:0] input in the DDR format into 16-bit signal of a single data rate (SDR) format synchronized only with the rising edge of the data strobe signal DQS and outputs the converted signal to the FIFO buffer14.

The FIFO buffer14receives 16-bit data from the controller side interface13in synchronization with the rising edge of the data strobe signal DQS. The FIFO buffer14supplies the data received from the controller side interface13to the demultiplexer15as input data DI in synchronization with the rising edge of the first operation clock CK1supplied from the clock generator11. The FIFO buffer14generates an input flag FI indicating whether the input data DI to be supplied to the demultiplexer15is valid or invalid, and supplies the generated input flag FI to the demultiplexer15.

The demultiplexer15separates the input flag FI and the input data DI into a first output flag FO1, a first output data DO1, a second output flag FO2, and a second output data DO2. The demultiplexer15outputs the first output flag FO1and the first output data DO1to the memory side interface16a, and outputs the second output flag FO2and the second output data DO2to the memory side interface16b. Detailed configuration of the demultiplexer15is described with reference toFIG.2below.

The memory side interface16aconverts the 16-bit first output data DO1supplied from the demultiplexer15into 8-bit data DQ1[7:0]. The memory side interface16acontrols a stop and a restart of data strobe signal DQS1based on the value of the first output flag FO1. The memory side interface16asupplies the data DQ1[7:0] and a data strobe signal DQS1to the memory chip4ain the DDR format in synchronization with the rising and falling edges of the second operation clock CK2.

The memory side interface16bconverts the 16-bit second output data DO2supplied from the demultiplexer15into 8-bit data DQ2[7:0]. The memory side interface16bcontrols a stop and a restart of data strobe signal DQS2based on the value of the second output flag FO2. The memory side interface16bsupplies the data DQ2[7:0] and a data strobe signal DQS2to the memory chip4bin the DDR format in synchronization with the rising and falling edges of the second operation clock CK2.

FIG.2is a block diagram showing an example of the configuration of the demultiplexer according to the first embodiment. The demultiplexer15includes a control circuit21, multiplexers22a,22b,22c, and22d, and registers23a,23b,23c, and23das shown inFIG.2.

The first operation clock CK1input to the demultiplexer15is supplied to the control circuit21, the registers23aand23b. The second operation clock CK2input to the demultiplexer15is supplied to the registers23cand23d. The reset signal RN input to the demultiplexer15is supplied to the control circuit21, and the registers23a,23b,23c, and23d.

The input flag FI is input to the control circuit21. The input flag FI is added to the most significant bit of the input data DI. That is, the n-bit input data DI is added with the input flag FI as the most significant bit and input to the multiplexers22aand22bas (n+1)-bit data DAT.

The control circuit21generates an input sort signal IS and an output exchange signal OX based on the input flag FI, the first operation clock CK1, and the reset signal RN. The control circuit21outputs the input sort signal IS to the multiplexers22aand22b, and outputs the output exchange signal OX to the multiplexers22cand22d. Detailed configuration of the control circuit21is described with reference toFIGS.3and4as described below.

The data DAT is input to one input terminal of the multiplexer22a, and data fed back from the register23ais input to the other input terminal. The multiplexer22aselects one piece of the input data and outputs the selected data to the register23abased on the input sort signal IS supplied to the control terminal.

Specifically, when the input sort signal IS is a low-level signal, the multiplexer22aselects the data DAT and outputs the data to the register23a. On the other hand, when the input sort signal IS is at a high level, the multiplexer22aselects the data fed back from the register23aand outputs the selected data to the register23a.

The data fed back from the register23bis input to one input terminal of the multiplexer22b, and the data DAT is input to the other input terminal. The multiplexer22bselects one piece of the input data and outputs the selected data to the register23bbased on the input sort signal IS supplied to the control terminal.

Specifically, when the input sort signal IS is at a low level, the multiplexer22bselects the data fed back from the register23band outputs the selected data to the register23b. On the other hand, when the input sort signal IS is at a high level, the multiplexer22bselects the data DAT and outputs the selected data to the register23b.

Thus, when the input sort signal IS is at a low level, the data DAT is selected by the multiplexer22aand stored in the register23a. On the other hand, when the input sort signal IS is at a high level, the data DAT is selected by the multiplexer22band stored in the register23b. That is, the data DAT including the input flag FI and the input data DI is distributed to the registers23aor23bbased on the input sort signal IS generated by the control circuit21. Thus, the multiplexers22aand22bdetermine the output destination of the data DAT (input data DI and input flag FI) based on the input sort signal IS (a first selection signal). The multiplexers22aand22bare an example of the first selection circuit.

The register23astores (n+1)-bit data output from the multiplexer22ain synchronization with the rising edge of the first operation clock CK1. The data stored in the register23ais input to the multiplexers22cand22d. The data stored in the register23ais fed back to the other input terminal of the multiplexer22a.

The register23bstores (n+1)-bit data output from the multiplexer22bin synchronization with the rising edge of the first operation clock CK1. The data stored in the register23bis input to the multiplexers22cand22d. The data stored in the register23bis fed back to one input terminal of the multiplexer22b. Thus, the registers23aand23bfetch the outputs of the multiplexers22aand22bin synchronization with the rising edge of the first operation clock CK1. The registers23aand23bare an example of a first register.

The output of the register23ais input to one input terminal of the multiplexer22c, and the output of the register23bis input to the other input terminal. The multiplexer22cselects data input from either of the registers23aand23bbased on the output exchange signal OX supplied to the control terminal and outputs the data to the register23c. Specifically, when the output exchange signal OX is a low-level signal, the multiplexer22cselects the data output from the register23aand outputs the selected data to the register23c. On the other hand, when the output exchange signal OX is at a high level, the multiplexer22cselects the data output from the register23band outputs the selected data to the register23c.

The output of the register23bis input to one input terminal of the multiplexer22d, and the output of the register23ais input to the other input terminal. The multiplexer22dselects data input from either of the registers23aand23bbased on the output exchange signal OX supplied to the control terminal and outputs the data to the register23d. Specifically, when the output exchange signal OX is a low-level signal, the multiplexer22dselects the input data output from the register23band outputs the selected data to the register23d. On the other hand, when the output exchange signal OX is at a high level, the multiplexer22dselects the data output from the register23aand outputs the selected data to the register23d. Thus, the multiplexers22cand22dselectively exchange an output destination of the (n+1)-bit data input from the registers23aand23bbased on the output exchange signal OX (a second selection signal). The multiplexers22cand22dare an example of a second selection circuit.

Therefore, when the output exchange signal OX is at a low level, the output of the register23ais input to the register23c, and the output of the register23bis input to the register23d. On the other hand, when the output exchange signal OX is at a high level, the output of the register23ais input to the register23d, and the output of the register23bis input to the register23c. That is, the outputs of the registers23aand23bis exchanged and input to the registers23cand23d.

The register23cstores (n+1)-bit data output from the multiplexer22cin synchronization with the rising edge of the second operation clock CK2. After the data stored in the register23cis output from the register23c, the data is separated into n-bit first output data DO1and a 1-bit first output flag FO1, and supplied to the memory side interface16a.

The register23dstores (n+1)-bit data output from the multiplexer22din synchronization with the rising edge of the second operation clock CK2. After the data stored in the register23dis output from the register23d, the data is separated into n-bit second output data DO2and a 1-bit second output flag FO2, and supplied to the memory side interface16b. Thus, the registers23cand23dfetch the outputs of the multiplexers22cand22din synchronization with the rising edge of the second operation clock CK2. The registers23cand23dare an example of a second register.

FIG.3is a block diagram showing an example of the configuration of the control circuit according to the first embodiment. The control circuit21includes 1-bit counters31aand31b, a start circuit32, a mismatch detection circuit33, and a register34with an enable function as shown inFIG.3.

The input flag FI is input to the 1-bit counter31a, the start circuit32, and the register34with the enable function. Both the first operation clock CK1and the reset signal RN are input to the 1-bit counters31aand31b, the start circuit32, and the register34with the enable function.

When the reset signal RN at a low level is input for a certain period before the operation starts, the 1-bit counters31aand31b, the start circuit32, and the register34with the enable function are reset. The 1-bit counters31aand31b, the start circuit32, and the register34with the enable function output low-level signals respectively during a reset period.

When the reset signal RN rises to a high level, the control circuit21waits for the input flag FI to rise to a high level. When the input flag FI is at a low level at the time when the reset signal RN has risen, outputs of the 1-bit counters31aand31b, the start circuit32and the register34with the enable function does not change from the reset state until the input flag FI rises up to a high level.

The start circuit32outputs a high-level signal to the 1-bit counter31bwhen the input flag FI is at a high level at the time when the reset signal RN rises up to a high level, or when the reset signal RN rises up to a high level and then the input flag FI is changed from a low level to a high level. Thereafter, the output of the start circuit32is kept at a high level regardless of the value of the input flag FI.

The 1-bit counter31bstarts a counting operation when a high-level signal is input from the start circuit32. When the 1-bit counter31breceives a high-level signal (that is, when the 1-bit counter31bis started by the start circuit32), the 1-bit counter31boutputs the input sort signal IS whose level is inverted in synchronization with the rising edge of the first operation clock CK1. The input sort signal IS is input to the mismatch detection circuit33. The input sort signal IS is input from the control circuit21to the multiplexers22aand22bas the first selection signal.

The 1-bit counter31aoutputs an output sort signal OS whose level is inverted in synchronization with the rising edge of the first operation clock CK1to the mismatch detection circuit33when the input flag FI is at a high level. On the other hand, when the input flag FI is at a low level, the 1-bit counter31aoutputs the output sort signal OS to the mismatch detection circuit33without changing the level of the output sort signal OS.

Output sort signal OS output from the 1-bit counter31abecomes a signal indicating a correct distribution destination of the input data DI input to the demultiplexer15. The correct distribution destination of the input data DI is the first output data DO1when the output sort signal OS is at a low level, and the second output data DO2when the output sort signal OS is at a high level.

The mismatch detection circuit33detects whether the signal levels of the input sort signal IS and the output sort signal OS match or not. The mismatch detection circuit33outputs a low-level signal to the register34with the enable function when the signal levels of the input sort signal IS and the output sort signal OS match. On the other hand, the mismatch detection circuit33outputs a high-level signal to the register34with the enable function when the signal levels of the input sort signal IS and the output sort signal OS do not match.

When the input flag FI is at a low level, the register34with the enable function outputs the output exchange signal OX without changing the level of the output exchange signal OX. On the other hand, when the input flag FI is at a high level, the register34with the enable function fetches the output of the mismatch detection circuit33in synchronization with the rising edge of the first operation clock CK1and outputs the output as the output exchange signal OX. The output exchange signal OX is input from the control circuit21to the multiplexers22cand22das the second selection signal.

FIG.4is a circuit diagram showing an example of a configuration of the control circuit according to the first embodiment.FIG.4shows a detailed circuit configuration of the control circuit21as shown inFIG.3. In the circuit configuration shown inFIG.4, a part corresponding to each block inFIG.3is surrounded by a dashed line and the same reference character as each block inFIG.3is added.

The 1-bit counter31ais configured with an XOR gate41and a flip-flop42. The start circuit32is configured with an OR gate43and a flip-flop44. The 1-bit counter31bis configured with an XOR gate45and a flip-flop46. The mismatch detection circuit33is configured with an XOR gate47. The register34with the enable function is configured with a multiplexer48and a flip-flop49.

The input flag FI is input to one input terminal of the XOR gate41. The output sort signal OS fed back from the flip-flop42is input to the other input terminal of the XOR gate41.

The XOR gate41calculates an exclusive OR between the input flag FI and the output sort signal OS, and outputs the arithmetic result to the flip-flop42. Specifically, the XOR gate41outputs the output sort signal OS fed back from the flip-flop42to the flip-flop42without inverting the level of the output sort signal OS when the input flag FI is a low level, and outputs the output sort signal OS with inverting the level of the output sort signal OS to the flip-flop42when the input flag FI is a high level.

The flip-flop42fetches the output of the XOR gate41in synchronization with the rising edge of the first operation clock CK1and outputs the output as the output sort signal OS. The output sort signal OS is fed back to the XOR gate41and input to one input terminal of the XOR gate47. Thus, when the input flag FI is at a high level, the output sort signal OS whose level is inverted in synchronization with the rising edge of the first operation clock CK1is output from the 1-bit counter31a.

The input flag FI is input to one input terminal of the OR gate43. An output signal of the flip-flop44is fed back and input to the other input terminal of the OR gate43. The OR gate43performs an OR operation between the input flag FI and the signal fed back from the flip-flop44, and outputs the arithmetic result to the flip-flop44and the XOR gate45. The flip-flop44fetches the output of the OR gate43in synchronization with the rising edge of the first operation clock CK1and feeds the output back to the other input terminal of the OR gate43.

When the output of the flip-flop44is at a low level, the output of the OR gate43is at the same logic level as the input flag FI. The output of the OR gate43is at a high level when the output of the flip-flop44is at a high level. Therefore, when the input flag FI is at a high level after the reset signal RN has risen, the output of the flip-flop44is at a high level in synchronization with the rising edge of the first operation clock CK1. Since the output of the flip-flop44is fed back to the OR gate43, the output of the OR gate43is always kept at a high level regardless of the value of the input flag FI when the input flag FI is at a high level after the reset signal RN has risen.

The output signal of the OR gate43is input to one input terminal of the XOR gate45, and the input sort signal IS fed back from the flip-flop46is input to the other input terminal of the XOR gate45.

The XOR gate45calculates an exclusive OR between the output signal of the OR gate43and the input sort signal IS fed back from the flip-flop46, and outputs the arithmetic result to the flip-flop46. The XOR gate45does not invert the level of the input sort signal IS when the output signal of the OR gate43is at a low level, and inverts the level of the input sort signal IS and outputs the inverted input sort signal IS to the flip-flop46when the output signal of the OR gate43is at a high level.

The flip-flop46fetches the output of the XOR gate45in synchronization with the rising edge of the first operation clock CK1and outputs the output as the input sort signal IS. Thus, the input sort signal IS whose level is inverted in synchronization with the rising edge of the first operation clock CK1is output from the 1-bit counter31b.

The input sort signal IS is fed back to the other input terminal of the XOR gate45and input to the other input terminal of the XOR gate47. The input sort signal IS is supplied to the multiplexers22aand22bas the first selection signal.

The XOR gate47calculates an exclusive OR between the input sort signal IS and the output sort signal OS, and outputs the arithmetic result to the multiplexer48. The XOR gate47outputs a low-level output signal to the multiplexer48when the levels of the input sort signal IS and the output sort signal OS are equal, and outputs a high-level output signal to the multiplexer48when the levels of the input sort signal IS and the output sort signal OS are not equal.

The output signal of the XOR gate47is input to one input terminal of the multiplexer48. The output exchange signal OX fed back from the flip-flop49is input to the other input terminal of the multiplexer48. The input flag FI is input as a selection signal to a control terminal of the multiplexer48.

When the input flag FI is at a low level, the multiplexer48selects the output exchange signal ox fed back from the flip-flop49, and when the input flag FI is at a high level, the multiplexer48selects the output signal of the XOR gate47. The multiplexer48outputs the selected signal to the flip-flop49.

The flip-flop49fetches the output signal from the multiplexer48in synchronization with the rising edge of the first operation clock CK1and outputs the output signal as the output exchange signal OX. Thus, the output exchange signal Ox changes to the same value as the output signal of the XOR gate47in synchronization with the rising edge of the first operation clock CK1only when the input flag FI being the selection signal of the multiplexer48is at a high level. The output exchange signal OX is fed back to the other input terminal of the multiplexer48. The output exchange signal OX is supplied to the multiplexers22cand22das the second selection signal.

Next, the operation of the demultiplexer15configured in this manner is described.

FIG.5is a timing chart illustrating the operation of the demultiplexer in the first embodiment.

InFIG.5, as valid input data DI, input data D0to D13is supplied to the demultiplexer15. The demultiplexer15distributes the input data D0to D13to the first output data DO1of the even numbered input data D0, D2, D4, D6, D8, D10, and D12, and the second output data DO2of the odd numbered input data D1, D3, D5, D7, D9, D11, and D13.

After the reset signal RN rises from a low level to a high level at time T11, at time T12, the first input data D0is supplied at the same timing as the falling of the second operation clock CK2.

When the input flag FI rises from a low level to a high level after the reset signal RN rises from a low level to a high level, a high-level signal is output from the start circuit32to the 1-bit counter31b. The start circuit32outputs a high-level signal to the 1-bit counter31buntil the reset signal RN falls down to a low level.

When a high-level signal is input from the start circuit32, a 1-bit counter31boutputs the input sort signal IS whose level is inverted in synchronization with the rising edge of the first operation clock CK1. Therefore, the input sort signal IS inverts the level in synchronization with the rising edge of the first operation clock CK1until the reset signal RN falls down to a low level.

When the input flag FI rises from a low level to a high level after the reset signal RN rises from a low level to a high level, the 1-bit counter31aoutputs the output sort signal OS whose level is inverted in synchronization with the rising edge of the first operation clock CK1. The output sort signal OS inverts the level in synchronization with the rising edge of the first operation clock CK1during a period in which the input flag FI is at a high level, and does not change the level during a period in which the input flag FI is at a low level.

The input data D0to D5is selected by the multiplexer22aor22bbased on the input sort signal IS and input to the register23aor23b. When the input sort signal IS is at a low level, the input data DI is selected by the multiplexer22aand is fetched into the register23a. On the other hand, when the input sort signal IS is at a high level, the input data DI is selected by the multiplexer22band is fetched into the register23b. That is, the input data D0, D2, and D4are selected by the multiplexer22aand are fetched into the register23a. The input data D1, D3, and D5are selected by the multiplexer22band are fetched into the register23b.

Both input data fetched into the registers23aand23bare output to the multiplexers22cand22d. The multiplexer22cselects the input data output from the register23aor23bbased on the output exchange signal OX and outputs the selected input data to the register23c. The multiplexer22dselects the input data output from the register23aor23bbased on the output exchange signal OX and outputs the selected input data to the register23d.

When the signal levels of the input sort signal IS and the output sort signal OS are the same, a low-level signal is output from the mismatch detection circuit33to the register34with the enable function. When the input flag FI is at a high level, the register34with the enable function fetches the output of mismatch circuit33in the detection synchronization with the rising edge of the first operation clock CK1and outputs the output as the output exchange signal OX. Therefore, a low-level signal is input to multiplexers22cand22das the output exchange signal OX.

Thus, the input data D0, D2, and D4output from the register23aare selected by the multiplexer22cand are fetched into the register23c. The input data D1, D3, and D5output from the register23bare selected by the multiplexer22dand fetched into the register23d.

As a result, 6 pieces of the input data D0to D5are separated into even numbers and odd numbers, and are output as the first output data DO1and the second output data DO2, respectively.

After the input data D5is input and a period in which the input data DI is invalid elapses, the input data D0is supplied at the same timing as the rising of the second operation clock CK2at time T13. In this case, the input data D6, D8, D10, and D12are supplied during a period in which the input sort signal IS is at a high level, and the input data D7, D9, D11, and D13are supplied during a period in which the input sort signal IS is at a low level. Therefore, the even numbered input data D6, D8, D10, and D12are selected by the multiplexer22band fetched into the register23b, and the odd numbered input data D7, D9, D11, and D13are selected by the multiplexer22aand fetched into the register23a.

When the input flag FI rises up to a high level at time T13, the output sort signal OS whose level is inverted in synchronization with the rising edge of the first operation clock CK1is output from the 1-bit counter31a. In this case, since the levels of the input sort signal IS and the output sort signal OS do not match, a high-level signal is output from the mismatch detection circuit33to the register34with the enable function. Thus, the output exchange signal OX that rises up to a high level in synchronization with the rising edge of the first operation clock CK1is output from the register34with the enable function to the multiplexers22cand22d.

Thus, the even numbered input data D6, D8, D10, and D12are selected by the multiplexer22cand fetched into the register23c, and the odd numbered input data D7, D9, D11, and D13are selected by the multiplexer22dand fetched into the register23d.

As a result, 8 pieces of the input data D6to D13are separated into even numbers and odd numbers, and are output as the first output data DO1and the second output data DO2, respectively.

Thus, the control circuit21determines whether output destinations (distribution destinations) of the registers23aand23bshould be exchanged according to the states of the input sort signal IS and the output sort signal OS. When the control circuit21determines that the output destinations of the registers23aand23bshould not be exchanged, the control circuit21outputs the low-level output exchange signal OX to the multiplexers22cand22d. On the other hand, when the control circuit21determines that the output destinations of the registers23aand23bshould be exchanged, the control circuit21outputs the high-level output exchange signal OX to the multiplexers22cand22d.

By the above operation, the input data D0to D13(valid input data DI) are output with distributed to the first output data DO1and the second output data DO2in the arrival order during a period in which the input flag FI is at a high level. Even the input flag FI can be correctly distributed to the first output flag FO1and the second output flag FO2by being processed as an (n+1)-bit signal set with the input data DI.

Thus, even when the input flag FI is interrupted, the bridge chip3can control the separation operation while keeping the distribution order.

TheFIG.6is a timing chart illustrating the other operation of the demultiplexer in the first embodiment.

In the timing chart inFIG.5, the input data D0is supplied at the same timing as the falling of the second operation clock CK2, and the input data D6is supplied at the same timing as the rising of the second operation clock CK2.

In the timing chart inFIG.6, the input data D0is supplied at the same timing as the rising of the second operation clock CK2, and the input data D0is supplied at the same timing as the falling of the second operation clock CK2.

Specifically, after the reset signal RN rises from a low level to a high level at time T21, the first input data D0is supplied at the same timing as the rising of the second operation clock CK2at time T22. After the data D5is input and a period in which the input data DI is invalid elapses, the input data D0is supplied at the same timing as the falling of the second operation clock CK2at time T23.

When the input flag FI is at a high level and the signal levels of the input sort signal IS and the output sort signal OS do not match at time T23, the output exchange signal OX rises up to a high level in synchronization with the rising edge of the first operation clock CK1. Thus, the output destination of the input data DI is exchanged in the multiplexers22cand22dand the data is output to a correct output destination.

As a result, the input data D0to D13are separated into even numbers and odd numbers, and output as the first output data DO1and the second output data DO2, respectively.

FIG.7is a timing chart illustrating further another operation of the demultiplexer in the first embodiment.

After the reset signal RN rises from a low level to a high level at time T31, at time T32, the first input data D0is supplied at the same timing as the falling of the second operation clock CK2. Then, the input flag FI and the input data DI are input in a random period.

Even when the input flag FI and the input data DI are input in the random period, when the input flag FI is at a high level and the signal levels of the input sort signal IS and the output sort signal OS do not match at time T33, the output exchange signal OX rises up to a high level in synchronization with the rising edge of the first operation clock CK1. When the input flag FI is at a high level and the signal levels of the input sort signal IS and the output sort signal OS match at time T34, the output exchange signal OX falls down to a low level in synchronization with the rising edge of the first operation clock CK1.

As a result, the input data D0to D13are separated into even numbers and odd numbers, and output as the first output data DO1and the second output data DO2, respectively.

FIG.8is a timing chart illustrating still another operation of the demultiplexer in the first embodiment.

In the timing chart inFIG.7, the data D0is supplied at the same timing as the falling of the second operation clock CK2.

In the timing chart inFIG.8, the data D0is supplied at the same timing as the rising of the second operation clock CK2.

Specifically, after the reset signal RN rises from a low level to a high level at time T41, the first input data D0is supplied at the same timing as the rising of the second operation clock CK2at time T42. Then, the input flag FI and the input data DI are input in a random period.

Even when the input flag FI and the input data DI are input in the random period, when the input flag FI is at a high level and the signal levels of the input sort signal IS and the output sort signal OS do not match at time T43, the output exchange signal OX rises up to a high level in synchronization with the rising edge of the first operation clock CK1. When the input flag FI is at a high level and the signal levels of the input sort signal IS and the output sort signal OS match at time T44, the output exchange signal OX falls down to a low level in synchronization with the rising edge of the first operation clock CK1.

As a result, the input data D0to D13are separated into even numbers and odd numbers, and output as the first output data DO1and the second output data DO2, respectively.

Modification Example

FIG.9is a circuit diagram showing an example of a configuration of a control circuit according to a modification example. InFIG.9, the same reference character is added to the same configuration as that ofFIG.4and the description is omitted.

As shown inFIG.9, a control circuit21A is implemented by a 1-bit counter31cinstead of the 1-bit counter31bof the control circuit21shown inFIG.4. The 1-bit counter31cincludes an AND gate51, an inverter52, and the flip-flop46. That is, in the 1-bit counter31c, the XOR gate45of the 1-bit counter31bis replaced with a combination of the AND gate51and the inverter52.

The output signal of the OR gate43is input to one input terminal of the AND gate51. An output signal of the inverter52is input to the other input terminal of the AND gate51. The AND gate51performs an AND operation of the output signal of the OR gate43and the output signal of the inverter52, and outputs the arithmetic result to the flip-flop46.

The flip-flop46fetches the output signal of the AND gate51in synchronization with the rising edge of the first operation clock CK1and outputs the fetched output signal as the input sort signal IS. The inverter52inverts the level of the input sort signal IS output from the flip-flop46and outputs the input sort signal IS whose level is inverted to the AND gate51.

With such a configuration, when the output of the OR gate43is at a low level, the AND gate51outputs a low level, and when the output of the OR gate43is at a high level, the same logic level as the output of the inverter52is output to the flip-flop46. The output of the inverter52is a value obtained by inverting the level of the input sort signal IS which is an output of the flip-flop46.

Therefore, since the 1-bit counter31coutputs a low level until started by the start circuit32, that is, until the output of the OR gate43becomes at a high level, the counting operation is stopped. After being started by the start circuit32, that is, after the output of the OR gate43becomes at a high level, the 1-bit counter31cperforms a counting operation in which the logical level is inverted in synchronization with the rising edge of the first operation clock CK1.

Thus, the 1-bit counter31coutputs the input sort signal IS whose level is inverted in synchronization with the rising edge of the first operation clock CK1when started by the start circuit32, in the same way as the 1-bit counter31bshown inFIG.4. Therefore, the operation of the control circuit21A does not change from the operation before replacing the 1-bit counter31bwith the 1-bit counter31c.

Generally, the combination of the AND gate51and the inverter52has fewer transistors included in the circuit than the XOR gate45. Therefore, the 1-bit counter31ccan reduce the circuit area and the power consumption more than the 1-bit counter31b.

The 1-bit counter31cuses the combination of the AND gate51and the inverter52instead of the XOR gate45inFIG.4, but is not limited to such a configuration. For example, the combination of the NOR gate and the inverter may be used instead of the combination of the AND gate51and the inverter52. By replacing the AND gate51and the inverter52with the combination of the NOR gate and the inverter, the number of transistors included in the circuit can be further reduced, and the circuit area and power consumption can be further reduced than the 1-bit counter31c.

Second Embodiment

Next, a second embodiment is described.

FIG.10is a block diagram showing a configuration of a bridge chip according to the second embodiment. InFIG.10, the same reference character is added to the same configuration as that ofFIG.1. A bridge chip3A shown inFIG.10shows only the connection configuration of a demultiplexer in the bridge chip3A.

As shown inFIG.10, the bridge chip3A includes demultiplexers15aand15bin addition to the demultiplexer15. The demultiplexers15,15a, and15bare connected in a binary tree shape. Specifically, the demultiplexers15aand15bare connected to the output stage of the demultiplexer15.

The first output flag FO1and the first output data DO1output from the demultiplexer15are input to the demultiplexer15a, and the second output flag FO2and the second output data DO2are input to the demultiplexer15b.

By such a configuration, the demultiplexers15,15a, and15bdistributes the input flag FI and the input data DI to first′ output flags FO1′ to fourth′ output flags FO4′ and first′ output data DO1′ to fourth′ output data DO4′, respectively. The demultiplexers15aand15bare configured the same as the demultiplexer15shown inFIGS.2to4.

The clock generator11generates a third operation clock CK3in addition to the first operation clock CK1and the second operation clock CK2. The third operation clock CK3is a clock obtained by dividing the second operation clock CK2by two.

The first operation clock CK1, the second operation clock CK2and the reset signal RN are input to the demultiplexer15. The second operation clock CK2, the third operation clock CK3, and the reset signal RN are input to the demultiplexers15aand15b.

The demultiplexer15separates the input flag FI and the input data DI into the first output flag FO1, the first output data DO1, the second output flag FO2, and the second output data DO2based on the first operation clock CK1, the second operation clock CK2, and the reset signal RN. The demultiplexer15outputs the separated first output flag FO1and first output data DO1to the demultiplexer15a, and outputs the separated second output flag FO2and second output data DO2to the demultiplexer15b.

The demultiplexer15aseparates the first output flag FO1and the first output data DO1into the first′ output flag FO1′, the first′ output data DO1′, the third′ output flag FO3′, and the third′ output data DO3′ based on the second operation clock CK2, the third operation clock CK3, and the reset signal RN.

The demultiplexer15bseparates the second output flag FO2and the second output data DO2into the second′ output flag FO2′, the second′ output data DO2′, the fourth′ output flag FO4′, and the fourth′ output data DO4′ based on the second operation clock CK2, the third operation clock CK3, and the reset signal RN.

In the demultiplexers15aand15b, the second operation clock CK2and the third operation clock CK3perform the same functions as the first operation clock CK1and the second operation clock CK2in the demultiplexer15.

With such a configuration, when the semiconductor storage device2includes 4 memory chips, for example, the bridge chip3A separates the input flag FI and the input data DI into the first′ output flag FO1′ to the fourth′ output flag FO4′ and the first′ output data DO1′ to the fourth′ output data DO4′, and can transmit the separated flags and data to the 4 memory chips.

Third Embodiment

Next, a third embodiment is described.

FIG.11is a block diagram showing a configuration of a bridge chip according to the third embodiment. InFIG.11, the same reference character is added to the same configuration as that ofFIG.10and the description is omitted. A bridge chip3B shown inFIG.11shows only the connection configuration of the demultiplexer in the bridge chip3B.

As shown inFIG.11, the bridge chip3B includes demultiplexers15cto15fin addition to the demultiplexers15,15a, and15b. The demultiplexers15and15ato15fare connected in a binary tree shape. Specifically, the demultiplexers15aand15bare connected to the output stage of the demultiplexer15. The demultiplexers15cand15dare connected to the output stage of the demultiplexer15a. Further, the demultiplexers15eand15fare connected to the output stage of the demultiplexer15b.

The first′ output flag FO1′ and the first′ output data DO1′ output from the demultiplexer15aare input to the demultiplexer15c, and the third′ output flag FO3′ and the third′ output data DO3′ are input to the demultiplexer15d. The second′ output flag FO2′ and the second′ output data DO2′ output from the demultiplexer15bare input to the demultiplexer15e, and the fourth′ output flag FO4′ and the fourth′ output data DO4′ are input to the demultiplexer15f.

With such a configuration, the demultiplexer15, and15ato15fdistribute the input flag FI and the input data DI to a first″ output flag FO1″ to an eighth″ output flag FO8″ and first″ output data DO1″ to eighth″ output data DO8″, respectively. Each configuration of the demultiplexers15cto15fis the same as that of the demultiplexer15shown inFIGS.2to4.

The clock generator11generates a fourth operation clock CK4in addition to the first operation clock CK1, the second operation clock CK2, and the third operation clock CK3. The fourth operation clock CK4is a clock obtained by dividing the third operation clock CK3by two.

The third operation clock CK3, the fourth operation clock CK4and the reset signal RN are input to the demultiplexers15cto15f.

The first′ output flag FO1′ and the first′ output data DO1′ are input to the demultiplexer15cfrom the demultiplexer15a. The demultiplexer15cseparates the first′ output flag FO1′ and the first′ output data DO1′ into the first″ output flag FO1″, the first″ output data DO1″, the fifth″ output flag FO5″, and the fifth″ output data DO5″ based on the third operation clock CK3, the fourth operation clock CK4, and the reset signal RN.

The third′ output flag FO3′ and the third′ output data DO3′ are input to the demultiplexer15dfrom the demultiplexer15a. The demultiplexer15dseparates the third′ output flag FO3′ and the third′ output data DO3′ into the third″ output flag FO3″, the third″ output data DO3″, the seventh″ output flag FO7″, and the seventh″ output data DO7″ based on the third operation clock CK3, the fourth operation clock CK4, and the reset signal RN.

The second′ output flag FO2′ and the second′ output data DO2′ are input to the demultiplexer15efrom the demultiplexer15b. The demultiplexer15eseparates the second′ output flag FO2′ and the second′ output data DO2′ into the second″ output flag FO2″, the second″ output data DO2″, the sixth″ output flag FO6″, and the sixth″ output data DO6″ based on the third operation clock CK3, the fourth operation clock CK4, and the reset signal RN.

The fourth′ output flag FO4′ and the fourth′ output data DO4′ are input to the multiplexer15ffrom the demultiplexer15b. The demultiplexer15fseparates the fourth′ output flag FO4′ and the fourth′ output data DO4′ into the fourth″ output flag FO4″, the fourth″ output data DO4″, the eighth″ output flag FO8″, and the eighth″ output data DO8″ based on the third operation clock CK3, the fourth operation clock CK4, and the reset signal RN.

In the demultiplexers15cto15f, the third operation clock CK3and the fourth operation clock CK4perform the same functions as the first operation clock CK1and the second operation clock CK2in the demultiplexer15.

With such a configuration, when the semiconductor storage device2includes 8 memory chips, for example, the bridge chip3B can separate the input flag FI and the input data DI into the first″ output flag FO1″ to the eighth″ output flag FO8″ and the first″ output data DO1″ to the eighth″ output data DO8″, and can transmit the separated flags and data to the 8 memory chips.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of forms; other furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.