Patent ID: 12218542

DETAILED DESCRIPTION

In existing mobile computing devices, when the processor operates at a high level of power consumption, the battery may output larger amounts of electric current than the battery is designed to support. This rapid discharging may result in degradation of the battery and unreliable battery performance. The discharge rate of the battery is typically managed using a current control algorithm executed at the processor. The current control algorithm typically uses, as its inputs, measurements of the discharge rate of the battery sampled over a predefined time window. However, such a current control algorithm may respond slowly to rapid increases in current, thereby allowing the processor to draw amounts of electric current that may degrade the performance of the battery. In addition, software-based current control algorithms may be vulnerable to software malfunctions, which could cause undesirable delays or suspend operation of the control algorithm.

In order to address the challenges discussed above, a computing device10is provided, as shown inFIG.1according to one example embodiment. The computing device10may be a mobile computing device such as a smartphone, a tablet, a laptop computer, a portable video game system, or some other type of mobile computing device. The computing device10may include a battery14configured to store electric charge and to provide electrical power to other components of the computing device10. The computing device10may further include a processor12and memory13that are configured to receive electrical power from the battery14. The processor12and memory13may be communicatively coupled by a data bus. In some examples, as depicted inFIG.1, the processor12and/or the memory13may be included in a system-on-a-chip (SoC)20.

When the processor12receives electrical power from the battery14, the processor12may be configured to receive the electrical power via a voltage regulator22. The voltage regulator22may be included in the SoC20, as depicted in the example ofFIG.1. In other examples in which the processor12is not included in an SoC20, the voltage regulator22may be provided in another physical component of the computing device10. As discussed in further detail below, the voltage regulator22may be configured to transmit electric current data to the processor12. The voltage regulator22may be configured to receive an analog current signal30at an analog-to-digital converter (ADC)23and to generate digital current data32from the analog current signal30. The voltage regulator22may be further configured to transmit the digital current data32to the processor12in a current report34that may be utilized at the processor12to adjust the amount of electric current drawn by the processor12.

The computing device10may further include a power supply unit (PSU)24configured to supply electrical power to the computing device10. The PSU24may be configured to supply conditioned electrical power to the battery14and to one or more additional electronic components17of the computing device10while the PSU24is electrically coupled to an external power source27. The PSU24may be configured to convert an alternating current (AC) input supplied by the electrical power source to a direct current (DC) output supplied to the battery14and one or more additional electronic components17of the computing device10. The PSU24may be further configured to transform an input voltage supplied by the electrical power source into an output voltage that is suitable for charging the battery14and operating the computing device10. The PSU24may be detachably coupled to the computing device10such that the computing device10may be used in a mobile configuration in which the electronic components of the computing device10receive electrical power from the battery14and are not coupled to the external power source27. The computing device10may further include a charger15configured to receive electrical power from the PSU24and to transmit that electrical power to the battery14and the voltage regulator22.

In addition to the processor12, the memory13, the battery14, the voltage regulator22, the PSU24, and the charger15, the computing device10may further include one or more additional electronic components17, as discussed above. The one or more additional electronic components17may be configured to receive electrical power from the battery14. The one or more additional electronic components17may also be configured to receive electrical power from the PSU24when the PSU24is connected to the external power source27. At least one of, and typically each of, the one or more additional electronic components17may have a respective additional voltage regulator25configured to receive electric current flowing to that additional electronic component17.

In some examples, as shown inFIG.1, the one or more additional electronic components17may include a discharge rate detector26that is configured to measure a discharge C-rate44of the battery14. The C-rate of the battery14is the rate at which the battery14is charged or discharged, expressed as a proportion of the full capacity of the battery14that is charged or discharged per hour. The charge C-rate is the C-rate of the battery14when the battery14is charging, and the discharge C-rate44is the C-rate when the battery14is discharging. In some examples, the discharge rate detector26may be provided within the battery14.

The one or more additional electronic components17included in the computing device10may further include a microcontroller28. In examples in which the processor12, the memory13, and the voltage regulator22are included in an SoC20, the microcontroller28may be included in the computing device10as a separate component from the SoC20. The microcontroller28may be coupled to the processor12by a data bus and may be configured to control one or more settings of the processor12, as discussed in further detail below. In examples in which the computing device10includes a discharge rate detector26, the microcontroller28may be configured to receive C-rate threshold data from the discharge rate detector26, as discussed in further detail below.

As shown in the example ofFIG.1, the computing device10may further include a first current detector16A configured to detect a total battery discharge current IB,SYSflowing from the battery14to the processor12via the voltage regulator22and to the one or more additional electronic components17. The first current detector16A may be located along a current flow path leading from the battery14to the voltage regulator22and the one or more additional electronic devices17, as shown in the example ofFIG.1. In some examples, the first current detector16A may include a first sense resistor18A, which may, for example, have a resistance within a range between 5 and 10 mΩ. The first sense resistor18A may be located between the battery14and the processor12.

FIG.2shows the voltage regulator22in additional detail in a state when the voltage regulator22receives an analog current signal30. As shown in the example ofFIG.2, the voltage regulator22may be configured to receive a first analog current signal30A from the first current detector16A that indicates the total battery discharge current IB,SYS. The voltage regulator22may be configured to receive the first analog current signal30A. At the ADC23, the voltage regulator22may be configured to convert the first analog current signal30A into first digital current data32A. When the ADC23converts the first analog current signal30A into first digital current data32A, the ADC23may also be configured to perform data filtering31on the first analog current signal30A. The voltage regulator22may be further configured to transmit the first digital current data32A to the processor12in a current report34. Other data, such as digital current data32from one or more other current sensors, may also be included in the current report34.

Returning toFIG.1, the processor12may be configured to receive the first digital current data32A from the voltage regulator22in the current report34. The processor12may be further configured to determine a difference between the total battery discharge current IB,SYSflowing from the battery14to the processor12via the voltage regulator22and to the one or more additional electronic components17, as indicated by the first digital current data32A, and an available electric current limit36of the battery14. The available electric current limit36may be a threshold level at which the processor12is configured to perform processor throttling.

In response to at least determining the difference between the total battery discharge current IB,SYSand the available electric current limit36, the processor12may be further configured to adjust one or more performance parameters40of the processor12such that the difference is reduced. The processor12may be configured to adjust the one or more performance parameters40at least in part by executing a performance parameter adjustment module38included in firmware of the processor12. In some examples, the one or more performance parameters40may include a voltage VPsupplied to the processor12. This voltage VPmay be supplied by the battery14, and may be additionally supplied by the PSU24in some examples. Additionally or alternatively, the one or more performance parameters40may include a clock rate42of the processor12. Accordingly, when the total battery discharge current IB,SYSis above the available electric current limit36, the processor12may be configured to adjust the one or more performance parameters40to reduce the total battery discharge current IB,SYS. When total battery discharge current IB,SYSis below the available electric current limit36, the processor12may be configured to adjust the one or more performance parameters40to increase the total battery discharge current IB,SYS. Thus, the processor12may be configured to modify the amount of electric current it receives from the battery14to prevent the battery14from operating at high levels of current for durations that are likely to degrade battery performance. However, the processor12may also increase the amount of electric current drawn from the battery14when the total battery discharge current IB,SYSis below the available electric current limit36to allow for faster processing.

In some examples, the processor12may be configured to adjust the one or more performance parameters40at least in part by performing proportional-integral-derivative (PID) control of the one or more performance parameters40. A technical advantage of using PID control is that control may be effected only based on measurements of the current itself, without having to account for additional variables or model the control system in a fully deterministic manner. In such examples, the instructions for the processor12to execute the performance parameter adjustment module38may include a proportional-term coefficient, an integral-term coefficient, and/or a derivative-term coefficient of a PID control module. The available electric current limit36may be the setpoint of the PID control module.

The voltage regulator22may, in some examples, be further configured to transmit a general-purpose input/output (GPIO) signal80to the processor12when the first analog current signal30A indicates that a warn-level current82or a fault-level current of the processor12is exceeded. The warn-level current82may be a first current threshold at which the voltage regulator22is configured to transmit a GPIO warn signal to the processor12. The warn-level current82may be lower than a fault-level current84of the processor12at which the voltage regulator22is configured to transmit a GPIO fault signal to the processor12. When the warn-level current82or the fault-level current84is exceeded, the electric current received at the processor12may be near or at a level high enough to damage the processor12. Thus, the GPIO signal80may control the processor12to perform emergency throttling, and, in some examples, to initiate shutdown.

It will be appreciated that the embodiment ofFIG.1may include a single current detector, i.e., the first current detector16A. A potential technical advantage of such a configuration is that it is possible to detect the current flowing from the battery14to the processor12using only a single sensor, which has cost and compactness advantages. This enables the current limit control described herein to be effected when the computing device10is operated under the power of the battery14without the PSU24being connected to the external power source27.

In some examples, the computing device10may include one or more additional current detectors. In such examples, the analog current signal30may include data received from those additional current detectors in addition to the first current detector16A. As shown in the example ofFIG.1, the computing device10may include a second current detector16B configured to detect an electric current IPSUflowing to the computing device10via the PSU24. The analog current signal30may, in such examples, further include a second analog current signal30B that indicates the electric current IPSUmeasured at the second current detector16B, as shown inFIG.2. The second current detector16B may, in some examples, include a second sense resistor18B. In such examples, the second sense resistor18B may have a resistance between 5 mΩ and 10 mΩ and may be located between the PSU24and the charger15. It will be appreciated that these values are merely exemplary and that resistance values outside this range may be used in other examples. As described in more detail below, a technical advantage of including the second current detector16B is that the limit control described herein may be implemented not only when operating with the PSU24disconnected from the external power source27, but also when the PSU24of the computing device10is connected to the external power source27, since current flowing from the PSU24to the processor12without traveling through the battery14can be measured.

In examples in which the computing device10includes a second current detector16B, when the computing device10is connected to the PSU24, the voltage regulator22may be configured to receive a second analog current signal30B from the second current detector16B, as shown inFIG.2. The voltage regulator22may be further configured to convert the second analog current signal30B into second digital current data32B at the ADC23. The voltage regulator22may be further configured to transmit the second digital current data32B to the processor12. Thus, the second digital current data32B may be included in the current report34.

In response to at least receiving the second digital current data32B from the voltage regulator22, the processor12may be further configured to adjust the one or more performance parameters40of the processor12based at least in part on the second digital current data32B. For example, the processor12may be configured to increase the one or more performance parameters40when the processor12determines, as indicated by the second digital current data32B, that the PSU24has become connected to the external power source27. Thus, the processor12may operate with a higher voltage VPand/or a higher clock rate42without exceeding the available electric current limit36of the battery14. Conversely, when the processor12determines, as indicated by the second digital current data32B, that the PSU24has become disconnected from the external power source27, the processor12may be configured to reduce the one or more performance parameters40.

The processor12may be configured to modify the available electric current limit36based at least in part on current limit update instructions46received from the microcontroller28, as depicted in the example ofFIG.3. The processor12and microcontroller28are shown in additional detail inFIG.3when the processor12performs a current limit computation47at a CPU driver39to update the available electric current limit36. The discharge rate detector26may be configured to measure the discharge C-rate of the battery14and, based at least in part on the discharge C-rate, output a plurality of C-rate-based discharge thresholds44to the microcontroller28. In some examples, the plurality of C-rate-based discharge thresholds44may include a maximum sustained current44A and a maximum peak current44B of the battery14.

As shown in the example ofFIG.3, the microcontroller28may be configured to receive the plurality of C-rate-based discharge thresholds44from the discharge rate detector26. Based at least in part on the plurality of C-rate-based discharge thresholds44, the microcontroller28may be further configured to transmit current limit update instructions46to the processor12. In some examples, the microcontroller28may include a scaler45that is configured to generate the current limit update instructions46at least in part by applying a scaling factor to the value of the available electric current limit36as specified by the plurality of C-rate-based discharge thresholds44. The processor12may be further configured to modify the available electric current limit36in response to at least receiving the current limit update instructions46to thereby generate an updated current limit48. One technical advantage of updating the current limit is to allow the battery14to operate according to a schedule in which the battery14discharges at different C-rates for different allowed durations in order to account for changes in energy consumption over time, as discussed in further detail below.

In some examples, when the one or more additional electronic components17of the computing device10draw large amounts of electric current from the battery14, the microcontroller28may be configured to output current limit update instructions46that instruct the processor12to lower the available electric current limit36. Alternatively, when the amount of current drawn from the battery14by the one or more additional electronic components17is low, the microcontroller28may be configured to output current limit update instructions46that instruct the processor12to raise the available electric current limit36and allow the total electric current IB,SYSto increase. Thus, the available electric current limit36may be dynamically adjusted based at least in part on the amount of current the battery14transmits to the one or more additional electronic components17of the computing device10.

The SoC20is shown in additional detail in the example ofFIG.4. As shown inFIG.4, the processor12may be configured to execute a plurality of operating system (OS) threads12A. The processor12may be configured to execute the CPU driver39to perform the current limit computation47, as discussed above with reference toFIG.3, at the plurality of OS threads12A. In addition, the memory13may include a plurality of CPU registers13A associated with the processor12. Subsequently to computing the available electric current limit36, the processor12may be further configured to store the available electric current limit36in the plurality of CPU registers13A.

When the microcontroller28generates the current limit update instructions46, the microcontroller28may, in some examples, be configured to refer to a lookup table37of respective durations at which the processor12is configured to operate at a plurality of different discharge C-rates. Thus, the microcontroller28may be configured to map the C-rate-based discharge thresholds44received from the discharge rate detector26to corresponding time intervals and generate the current limit update instructions46based at least in part on those time intervals. The lookup table37may be stored in the plurality of CPU registers13A. Thus, the microcontroller28may be configured to read at least a portion of the lookup table37from the plurality of CPU registers13A and generate the current limit update instructions46based at least in part on the retrieved portion of the lookup table37.

As depicted inFIG.4, the processor12may be configured to execute the performance parameter adjustment module38at a hardware circuit12B. When the processor12executes the performance parameter adjustment module38, the hardware circuit12B of the processor12may be configured to read the available electric current limit36from the plurality of CPU registers13A. The hardware circuit12B may be further configured to receive the current report34that indicates the digital current data32from the voltage regulator22. At the hardware circuit12B, the processor12may be configured to adjust the one or more performance parameters40based at least in part on the available electric current limit36and the current report34as discussed above.

When the processor12updates the voltage VP, the processor12may be configured to transmit a voltage setting35from the hardware circuit12B to the voltage regulator22. The voltage regulator22may be configured to convey electrical power at the voltage setting35to the processor12. When the processor updates the clock rate42, the hardware circuit12B may be configured to output a CPU clock rate multiple43to the memory13. The clock rate multiple43may be stored in the CPU registers13A. A system clock19included in the SoC20may be configured to read the CPU clock rate multiple43from the plurality of CPU registers13A and transmit a clock signal to the processor12that has the indicated CPU clock rate multiple43. Accordingly, the clock rate42of the processor12may be adjusted at the hardware circuit12B.

The hardware circuit12B may be configured to operate independently from the plurality of OS threads12A executed at the processor12. Thus, the processor12may adjust the one or more performance parameters40even when the operating system malfunctions. In addition, the hardware circuit12B may be configured to respond to changes in the digital current data32more quickly than the plurality of OS threads12A are configured to perform the current limit computation47to update the available electric current limit36. Therefore, hardware control of the one or more performance parameters40may allow the processor12to adjust for sudden changes in electric current measurements more quickly.

FIG.5shows another example computing device100including a third current detector116C. The third current detector116C may be configured to detect a total system current ISYSflowing from the battery14and the PSU24to the processor12and to one or more additional electronic components17of the computing device10. The total system current ISYSmay be equal to the sum of the total battery discharge current IB,SYSand a charger system current IC,SYSflowing from the charger15to the processor12and the one or more additional electronic components17. The third current detector116C may, for example, include a third sense resistor118C. The third sense resistor118C may, in such examples, have a resistance between 5 mΩ and 10 mΩ and may be located along a current flow path that leads from the battery14to the one or more additional electronic components17. As in the example above, these resistance values should be understood as merely exemplary as other values may be adopted in other configurations.

In the example ofFIG.5, the voltage regulator22may be further configured to receive a third analog current signal30C indicating the total system current ISYSfrom the third current detector116C, as depicted inFIG.2, and convert the third analog current signal30C into third digital current data32C at the ADC23. The voltage regulator22may be further configured to transmit the third digital current data32C to the processor12. A technical advantage of including the third current detector116C in this configuration is that an accurate measurement of current flowing to the processor12and the one or more additional electronic components17from both the battery14and the charger15may be obtained, thereby allowing for more accurate measurement of the total current drawn by the system.

Subsequently to receiving the third digital current data32C, the processor12may be further configured to adjust the one or more performance parameters40of the processor12based at least in part on the third digital current data32C. In examples in which the digital current data32further includes first digital current data32A received from a first current detector16A configured to measure the total battery discharge current IB,SYSflowing from the battery14to the processor12and the one or more additional electronic components17, as depicted in the example ofFIG.5, the processor12may be configured to compute the charger system current IC,SYSby subtracting the total battery discharge current IB,SYSfrom the total system current ISYS. The processor12may, in such examples, be further configured to adjust the performance parameters40based at least in part on the charger system current IC,SYS. For example, when the PSU24supplies large amounts of current to the processor12and the one or more additional electronic components17via the charger15(e.g. when the PSU24is connected to the external power source27and the battery14is at or near full capacity), the processor12may be configured to increase the voltage VPand/or the clock rate42.

FIG.6shows the computing device10in an example in which the computing device10further includes a voltage detector60configured to detect a voltage VB,SYSsupplied to the processor12by the battery14via the voltage regulator22and to the one or more additional electronic components17. In the example ofFIG.6, the voltage regulator22may be further configured to receive analog voltage data62indicating the voltage VB,SYSfrom the voltage detector60. The voltage regulator22may be further configured to convert the analog voltage data62into digital voltage data64at the ADC23and transmit the digital voltage data64to the processor12.

In examples in which the processor12receives digital voltage data64from the voltage regulator22, the processor12may be further configured to adjust the one or more performance parameters40based at least in part on the digital voltage data64. In some examples, when the one or more performance parameters40of the processor12include the voltage VPsupplied to the processor12, the voltage regulator22may be configured to receive the analog voltage data62indicating the voltage VB,Psupplied to the processor12by the battery14with a higher sampling frequency than the frequency at which the processor12is configured to adjust the voltage VP. In such examples, the processor12may control the one or more performance parameters40more quickly than if the voltage VPwere controlled at the processor12without receiving the digital voltage data64from the voltage regulator22.

Returning toFIG.2, the voltage regulator22may further include a deglitching circuit70in some examples. The deglitching circuit70may be configured to remove, from the first analog current signal30, overshoot components72B for which the total battery discharge current IB,SYSreceived at the processor12and additional electronic components17from the battery14is greater than or equal to the available electric current limit36for less than a deglitching timer duration74. It will be appreciated that the deglitching circuit70may include an overshoot determiner72that is configured to output an overshoot indication72A via a GPIO signal80to the processor12when the total battery discharge current IB,SYSexceeds either a warn-level current value82or fault-level current value84for a period of time that is equal to the deglitching timer duration74. The overshoot determiner72may be part of the deglitching circuit70, as shown, or a separate circuit. The processor12is configured to reduce its power consumption by reducing its clock rate in response to a warn-level overshoot indication72A or shut down in response to a fault-level overshoot indication72A.

To avoid reporting intermittent current spikes that are shorter than would trigger an overshoot indication72A, when the electric current IB,SYSexceeds the available electric current limit36, the voltage regulator22may be configured wait for the deglitching timer duration74to elapse before generating the current report34. By waiting, the deglitching circuit70enables the overshoot determiner72to properly determine whether any overshoot occurred that was for greater than the deglitching timer duration74, and also enables the data filtering31to remove any overshoot components72B of the analog current signal30. By removing the one or more overshoot components72B that are shorter than the deglitching timer duration74from the electric current data30, the deglitching circuit70may generate one or more filtered electric current signals78, which do not contain intermittent current spikes that are too short to trigger an overshoot indication72A. The current report34that is transmitted to the processor12may be generated from the filtered electric current data78. This has the technical benefit of stabilizing the current measurements of the system, which results in more stable control.

FIGS.7A-7Bshow a first example plot90A and a second example plot90B of the total battery discharge current IB,SYSas a function of time t in examples in which the voltage regulator22includes a deglitching circuit70. In the first example plot90A ofFIG.7A, the deglitching circuit70has a first deglitching timer duration74A that is longer than a current spike duration92of the processor12. The current spike duration92may be a duration for which the processor12is configured to operate at a warn-level current82. In some examples, the value of the current spike duration92may be hardcoded at the processor12in the hardware circuit12B.

The electric current IB,SYSreceived at the system from the battery14in the first example plot90A ofFIG.7Astarts at a first current value I0at a time t0. The first current value I0may, for example, be a long-term current limit of the processor12. At time t1, the electric current IB,SYSincreases to a second current value I1, which is a current value at which the warn-level current82of the processor12is exceeded in the example ofFIG.7A. The system remains at the second current value I1for the current spike duration92and decreases the electric current IB,SYSdrawn from the battery14to a third current value I2at a time t2. The third current value I2may, for example, be a current level at which the processor12operates at a short-term current limit. Since the current spike duration92is shorter than the first deglitching timer duration74A, the digital current data32transmitted from the voltage regulator22to the processor12does not include the current spike.

In the second example plot90B ofFIG.7B, the deglitching circuit70has a second deglitching timer duration74B that is shorter than the current spike duration92for which the processor12is configured to operate at the warn-level current82. As in the example ofFIG.7A, the processor12and the one or more additional electronic devices17in the example ofFIG.7Binitially draw a total battery discharge current IB,SYSwith the first current value I0, and subsequently increases the total battery discharge current IB,SYSto the second current value I1at time t1. However, in the example ofFIG.7B, the voltage regulator22is configured to detect that the processor12has operated at the warn-level current82(which is reached when the total system current IB,SYSis equal to the second current value I1in the example ofFIG.7B) for the second deglitching timer duration74B. The detection of the current spike is therefore transmitted to the processor12in the GPIO signal80. In response to at least detecting that the processor12has operated at the available electric current limit36for the second deglitching timer duration74B, the processor12performs throttling of the one or more performance parameters40that reduces the total battery discharge current IB,SYSto a fourth current value I3that is between the first current value I0and the third current value I2. When the current spike duration92has elapsed, the total battery discharge current IB,SYSincreases to the third current value I2.

Returning toFIG.2, in some examples, the deglitching circuit70may additionally have a hysteresis parameter76that is utilized when filtering the analog current signal30during data filtering31and also during overshoot determination by the overshoot determiner72. The hysteresis parameter76may, for example, be an overshoot indication reset threshold. In such examples, subsequently to a prior overshoot indication72A, the overshoot determiner72of the deglitching circuit70may not detect an overshoot of the available electric current limit36until the total battery discharge current IB,SYShas changed by an amount exceeding the hysteresis parameter76. Thus, using a hysteresis parameter76at the deglitching circuit70may prevent the deglitching circuit70from determining overshoot exists where in fact overshoot conditions are not met, for example, when the voltage regulator22receives a noisy analog current signal30. In examples in which the voltage regulator22receives an analog current signal30from a plurality of current detectors, the plurality of current detectors may have a respective plurality of hysteresis parameters76. It will be appreciated that if no overshoot is detected at the overshoot determiner72due to the use of hysteresis parameters, then correspondingly no overshoot component72B is removed from the analog current signal30by logic associated with data filtering31.

FIG.7Cillustrates a third prophetic example plot of actual system current IB,SYSbeing controlled relative to an available electric current limit36, which in this example is a maximum current envelope, in a battery-only mode by the computing device10ofFIG.1. The available electric current limit36of the computing device10ofFIG.1may include a plurality of available electric current limits for a plurality of durations, as shown in Table 1 below. Typically, maximum sustained current44A IB,SUSMAXfor a first duration and a maximum peak current44B IB,PEAKMAXof the battery14may be specified. These values account for battery chemistry and other design factors. As discussed above, scaler45is configured to compute one or more scaled values intermediate the peak and sustainable limits, such as the maximum first intermediate current IB,INT1MAXand maximum second intermediate current IB,INT2MAXlisted below in Table 1. The currents listed in Table 1 form an example maximum current envelope IB,INT1MAX.

TABLE 1Maximum Current EnvelopeLimitSymbolC-RateDurationMAX PEAKIB,PEAKMAX1.8CAnyCURRENTMAX SECONDIB,INT2MAX1.4C100 SecsINTERMEDIATECURRENTMAX FIRSTIB,INT1MAX1.3C500 SecsINTERMEDIATECURRENTMAXIB,SUSMAX1.0CNo limitSUSTAINEDCURRENT

When placed in operation, multiple countdown timers implemented in parallel by the processor12to track the time the actual system current IB,SYSstays above each respective limit in the maximum current envelope. When a countdown timer for a particular limit expires, indicating that the duration of time associated with that limit has passed, then the limit is enforced, and the processor12adjusts its voltage VPor clock rate42to reduce power draw to below the limit.

A technical difficulty with implementing current limits in this manner using a software-based approach by which the current limit computation47is performed in a CPU driver39as shown inFIG.4, is that the response time for the driver to compute updated limits and communicate them to the processor12via CPU registers13A can be relatively slow, thereby leading to limit overshoot or significant undershoot. Three examples of this are illustrated inFIG.7C, at (A), (B), and (C). At (A), the dark line shows the actual system current IB,SYSexceeding the maximum second intermediate current IB,INT2MAX(after, for example, the expiration of a timer limiting current to under the maximum second intermediate current IB,INT2MAX) under control of the CPU driver39, without use of the hardware control loop based on current report34. Since the CPU driver39takes time t0update the maximum current envelope stored in the CPU registers13A, the processor12does not immediately take advantage of the additional performance available. On the other hand, the dashed line at (A) shows a prophetic illustration of the performance advantage offered by adjusting the performance parameters40of the processor12via the performance parameter adjustment module38based on the current report34of actual system current. Accordingly, the processor12may increase current draw to near the maximum second intermediate current IB,INT2MAXlimit and thereby increase performance. Via the hardware control loop, the processor12may avoid significant undershoot by responding more quickly than would have occurred under control of the software control loop through CPU driver39alone, in battery-only mode.

At (B) inFIG.7C, a sensed value for a spike in actual system current IB,SYSthat exceeds the maximum first intermediate current IB,INT1MAXis shown as being allowed by the control loop through the CPU driver39(without use of the hardware control loop enabled by current report34), because the software control loop fails to respond quickly enough to detect the current overshoot and enforce CPU limit parameters to prevent the overshoot. On the other hand, as shown by the dashed line at (B), the hardware control loop quickly reports the actual system current IB,SYSto the processor12via the current report34. The current report34may enable the performance parameter adjustment module38of the processor12to enforce the current limit by quickly adjusting performance parameters40to reduce the current draw of the processor12to below the maximum first intermediate current IB,INT1MAX. As a result, battery performance can be prevented from being degraded due to exceeding discharge limits, in battery-only mode.

At (C) inFIG.7C, the dark line shows actual system current IB,SYScontrolled by the software loop through CPU driver39controlling the CPU to draw down current after the maximum second intermediate current duration has been exceeded, without use of the hardware control loop enabled by current report34. As shown, the CPU driver39cannot react quickly enough to prevent overshoot at the instant the timer has expired for the maximum second intermediate current duration, which can result in battery degradation over time. Using the hardware-based control loop which reports the actual system current IB,SYSin current report34to the processor12may enable the processor12to react quickly to reduce the sensed current value to below the applicable limit by adjusting the performance parameters40, thereby avoiding overshoot. As a result, battery performance can be prevented from being degraded due to exceeding discharge limits in battery-only mode.

FIG.7Dillustrates a fourth prophetic example plot of actual system current IB,SYSbeing controlled relative to an available electric current limit36, which in this example is a maximum current envelope, in a battery-plus-PSU mode by the computing device ofFIG.1. In this example, the PSU24is connected to an external power source27at a point in time indicated by a triangle symbol. At the point in time at which the external power is connected, the PSU24begins supplying current IPSUto the computing device10. The charger15receives the current IPSUand transforms the current IPSUinto a charger output current IC.PSUthat has a suitable voltage for charging the battery14and supplying power to the SoC20and additional electronic components17. From this point on, the maximum current envelope IB,MAXis theoretically raised by the value of the maximum current that can be supplied by the PSU24via the charger15, IC.PSUMAX, as indicated in by a dashed line. The dotted line that extends in stair-step fashion to the left of the dashed line inFIG.7Dshows the lift provided by IC.PSUMAXacross all current limits in the maximum current envelope, which it will be appreciated are operating in parallel even at the point of connection to external power in the figure. Once the PSU24is connected, the processor12can increase its performance above the maximum current envelope IB,MAXfor the battery-only mode by adjusting performance parameters40. However, if the processor12increases to the adjusted maximum current envelope, which is computed as IB,MAX+IC.PSUMAX, then there is a risk of over-discharging the battery above its current limits that define the maximum current envelope IB,MAX. For this reason, the processor12is configured to compute a safe adjusted maximum current envelope, IC.PSU+(IB,MAX−IB,SYS), illustrated by a dot-dash line. By increasing performance parameters40based on the current report34to increase performance but still keep actual system current within the safe adjusted maximum current envelope as shown by the dashed line at (D), performance can be maximized while not exceeding the battery discharge limits specified in the maximum current envelope during the battery-plus-PSU mode.

FIG.8schematically depicts another example computing device200that includes a second current detector216B corresponding to the second current detector16B included in the computing device10ofFIG.1. In addition, the example computing device200includes a third current detector216C corresponding to the third current detector116C included in the computing device100ofFIG.5. The second current detector216B may include a second sense resistor218B located between the PSU24and the charger15. The third current detector216C may include a third sense resistor218C located downstream of the battery14and the charger15and upstream of the voltage regulator22and the one or more additional electronic components17of the computing device200. However, the example computing device200ofFIG.8does not include a current detector in a location corresponding to that of the first current detector16A ofFIG.1.

In the example ofFIG.8, the voltage detector22may be configured to receive an analog current signal30from the second current detector216B and the third current detector216C and convert that analog current signal30into digital current data32that is transmitted to the processor12. Based at least in part on the digital current data32, the processor12may be configured to determine the total battery discharge current IB,SYSflowing from the battery14to the processor12and to the one or more additional electronic components17. For example, the processor12may be configured to estimate the total battery discharge current IB,SYSby subtracting the PSU current IPSUmeasured by the second current detector216B from the total system current ISYSmeasured by the third current detector216C. The processor12may be further configured to adjust the one or more performance parameters40based at least in part on the estimated value of IB,SYSas discussed above for the example computing devices ofFIG.1andFIG.5.

A technical advantage of including the second current detector216B and third current detector216C in this configuration is that the PSU current IPSUmay be more accurately measured when the PSU24is connected to the external power source27while also allowing the total battery discharge current IB,SYSto be accurately measured when the PSU24is disconnected. The total system current ISYSmay be equal to the total battery discharge current IB,SYSwhen the PSU24is disconnected from the external power source27.

FIG.9Ashows a flowchart of method300for use with a computing device to perform processor throttling via a voltage regulator. The method300may be performed at the computing device10ofFIG.1, the computing device100ofFIG.5, the computing device200ofFIG.8, or some other computing device. At step302, the method300may include, at a processor, receiving electrical power from a battery via a voltage regulator included in the computing device. In some examples, the processor and the voltage regulator may be included in an SoC. At step304, the method300may further include receiving electrical power from the battery at one or more additional electronic components of the computing device. The one or more additional electronic components may, for example, include a battery discharge rate detector, a microcontroller, one or more input devices, one or more output devices, and/or one or more other types of additional electronic components.

At step306, the method300may include, at a first current detector, detecting a total battery discharge current flowing from the battery to the processor via the voltage regulator and to the one or more additional electronic components. The first current detector may, for example, include a first sense resistor located downstream of the battery and upstream of the voltage regulator and the one or more additional electronic components.

Steps308,310, and312of the method300may be performed at the voltage regulator. At step308, the method300may further include receiving a first analog current signal from the first current detector. The first analog current signal may include a plurality of sampled values of the electric current received from the battery at the processor via the voltage regulator and at the one or more additional electronic components. At step310, the method300may further include converting the first analog current signal into first digital current data at an ADC included in the voltage regulator. At step312, the method300may further include transmitting the first digital current data to the processor in a current report. Other data may also be included in the current report in some examples.

In some examples, when step310is performed, the voltage regulator may be configured to generate filtered electric current data at a deglitching circuit included in the voltage regulator. Filtering the electric current data may include removing, from the first analog current signal, one or more overshoot components for which the total battery discharge current from the battery is greater than or equal to the available electric current limit for less than a deglitching timer duration. Accordingly, the deglitching circuit may reduce noise in the electric current data by filtering out short intervals in which the electric current output by the battery is greater than or equal to the available electric current limit. In some examples, the deglitching timer duration may be longer than a current spike duration for which the processor is configured to operate at a warn-level current. The warn-level current may be a current level at which the voltage regulator is configured to output a GPIO signal to the processor that functions as a high-current warning signal for the processor to perform emergency throttling. The current spike duration may be hardcoded in a hardware circuit of the processor. In other examples, the deglitching timer duration may be shorter than the current spike duration for which the processor is configured to operate at the warn-level current.

Steps314and316of the method300may be performed at the processor subsequently to receiving the current report including the first digital current data. At step314, the method300may further include determining a difference between the total battery discharge current, as indicated by the first digital current data, and an available electric current limit of the battery. The difference between the electric current output by the battery and the available electric current limit may be computed at a hardware circuit of the processor that is configured to operate separately from an operating system executed at the processor. The available electric current limit may be retrieved by the hardware circuit from a memory register of the processor when the difference is computed.

At step316, in response to at least determining the difference between the total battery discharge current and the available electric current limit, the method300may further include adjusting one or more performance parameters of the processor such that the difference is reduced. The one or more performance parameters may include a voltage supplied to the processor. Additionally or alternatively, the one or more performance parameters may include a clock rate of the processor. In examples in which the one or more performance parameters include the voltage supplied to the processor, the processor may transmit a voltage setting to the voltage regulator. In examples in which the one or more performance parameters include the clock rate of the processor, the processor may store a CPU clock rate multiple in a plurality of CPU registers included in the memory. The CPU clock rate may then be accessed by a system clock included in the computing device.

FIG.9Bshows additional steps of the method300that may be performed in some examples when the computing device includes a PSU. At step318, the method300may further include, via the PSU, supplying electrical power to the computing device. The electrical power supplied to the computing device through the PSU may be received from an external power source. The PSU may transmit the electrical power to a charger that is configured to route electric current to the battery and to other components of the computing device. At step320, the method300may further include, at a second current detector, detecting an electric current flowing to the computing device via the PSU. The second current detector may, for example, include a sense resistor located between the PSU and the charger.

Steps322,324, and326of the method300may be performed at the voltage regulator. At step322, the method300may further include receiving a second analog current signal from the second current detector. At step324, the method300may further include converting the second analog current signal into second digital current data at the ADC. In examples in which the voltage detector includes a deglitching circuit, the second analog current signal may be filtered at the deglitching circuit when step324is performed. At step326, the method300may further include transmitting the second digital current data to the processor. The second digital current data may be included in the current report.

At step328, the method300may further include, at the processor, adjusting the one or more performance parameters of the processor based at least in part on the second digital current data. For example, the processor may detect when the PSU starts and stops receiving electrical power from the external power source. When the computing device starts receiving electrical power from the external power source, the processor may adjust the one or more performance parameters to increase the voltage received at the processor and/or to increase the clock rate of the processor. When the computing device stops receiving electrical power from the external power source, the processor may adjust the one or more performance parameters to decrease the voltage received at the processor and/or to decrease the clock rate of the processor.

FIG.9Cshows additional steps of the method300that may be performed in examples in which the computing device further includes a discharge rate detector. Steps330and332may be performed at the discharge rate detector. At step330, the method200may further include measuring a discharge C-rate of the battery. For example, the discharge rate detector may be configured to detect a total current output by the battery to the plurality of electronic components of the computing device to which the battery is configured to provide power. At step332, the method300may further include, based at least in part on the discharge C-rate, outputting a plurality of C-rate-based discharge thresholds to a microcontroller. The plurality of C-rate-based discharge thresholds may include a maximum sustained current and a maximum peak current of the battery.

Subsequently to step332, the method300may further include performing steps334, and336at the microcontroller included in the computing device. At step334, the method300may further include receiving the plurality of C-rate-based discharge thresholds from the discharge rate detector. Based at least in part on the plurality of C-rate-based discharge thresholds, the method300may further include, at step336, transmitting current limit update instructions to the processor. For example, the current limit update instructions may indicate a current limit update schedule according to which the available electric current limit is configured to be modified over time. The microcontroller may, in such examples, be configured to generate the current limit update instructions at least in part by referring to a lookup table stored in memory that indicates respective durations at which the battery is configured to operate at a plurality of different discharge C-rates. At step338, the method300may further include, at the processor, modifying the available electric current limit in response to at least receiving the current limit update instructions.

FIG.9Dshows additional steps of the method300that may be performed in some examples. At step340, the method300may further include, at a third current detector, detecting a total system current flowing from the battery and a power supply unit (PSU) to the processor and to one or more additional electronic components of the computing device. The total system current may be the sum of the total battery discharge current and a total charger current output by the charger.

Steps342,344, and346of the method300may be performed at the voltage regulator. At step342, the method300may further include receiving a third analog current signal from the third current detector. At step344, the method300may further include converting the third analog current signal into third digital current data at the ADC. In examples in which the voltage detector includes a deglitching circuit, the third analog current signal may be filtered at the deglitching circuit when step344is performed. At step346, the method300may further include transmitting the third digital current data to the processor.

At step348, the method300may further include, at the processor, adjusting the one or more performance parameters of the processor based at least in part on the third digital current data. In some examples, adjusting the one or more performance parameters based at least in part on the third digital current data may include computing a charger current by subtracting the total battery discharge current from the total system current. The processor may, in such examples, adjust the one or more performance parameters to account for the amount of current received from the PSU via the charger. The processor may, for example, increase the one or more performance parameters when the charger current increases and decrease the one or more performance parameters when the charger current decreases.

In some examples, the computing device includes current detectors corresponding to the second current detector and the third current detector without including a first current detector that measures the electric current flowing from the battery to the processor via the voltage regulator. In such examples, the electric current flowing from the battery to the processor may be estimated at least in part by subtracting the amount of electric current measured at the second current detector from the amount of electric current measured at the second current detector.

FIG.9Eshows additional steps of the method300that may be performed in some examples. The steps shown inFIG.9Emay be performed at the voltage regulator. At step350, the method300may further include, at a voltage detector, detecting a voltage supplied to the processor by the battery via the voltage regulator and to the one or more additional electronic components. The voltage detector may be located downstream of the battery and upstream of the voltage regulator and the one or more additional electronic components.

Steps352,354, and356of the method300may be performed at the voltage regulator. At step352, the method300may further include receiving analog voltage data from the voltage detector. At step354, the method300may further include, at the ADC included in the voltage regulator, converting the analog voltage data into digital voltage data. At step356, the method300may further include transmitting the digital voltage data to the processor. The digital voltage data may be transmitted to the processor in the current report along with the digital current data or in a separate signal.

At step358, the method300may further include, at the processor, adjusting the one or more performance parameters of the processor based at least in part on the digital voltage data. In some examples, the digital voltage data may indicate the voltage supplied to the processor by the battery with a sampling rate higher than the rate at which the processor is configured to adjust the voltage it receives. In such examples, the processor may adjust the one or more performance parameters with increased responsiveness to changes in received voltage.

Using the devices and methods discussed above, instructions for a processor to perform processor throttling may be generated at a voltage regulator rather than at the processor itself. Thus, processor throttling may be performed more quickly in response to increases in current received at the processor from the battery and may be performed more reliably under conditions in which software malfunctions occur at the processor. The devices and methods discussed above may therefore provide the battery of the computing device with more reliable protection from current levels that would degrade battery performance. In addition, when the processor operates below the available electric current limit, the performance of the processor may be increased. The processor may thereby utilize available power more fully to allow for increased performance while preserving the performance of the battery.

In some embodiments, the methods and processes described herein may be tied to a computing system of one or more computing devices. In particular, such methods and processes may be implemented as a computer-application program or service, an application-programming interface (API), a library, and/or other computer-program product.

FIG.10schematically shows a non-limiting embodiment of a computing system400that can enact one or more of the methods and processes described above. Computing system400is shown in simplified form. Computing system400may embody the computing device10described above and illustrated inFIG.1, the computing device100described above and illustrated inFIG.5, or the computing device200described above and illustrated inFIG.8. Computing system400may take the form of one or more personal computers, server computers, tablet computers, home-entertainment computers, network computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smart phone), and/or other computing devices, and wearable computing devices such as smart wristwatches and head mounted augmented reality devices.

Computing system400includes a logic processor402volatile memory404, and a non-volatile storage device406. Computing system400may optionally include a display subsystem408, input subsystem410, communication subsystem412, and/or other components not shown inFIG.10.

Logic processor402includes one or more physical devices configured to execute instructions. For example, the logic processor may be configured to execute instructions that are part of one or more applications, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions may be implemented to perform a task, implement a data type, transform the state of one or more components, achieve a technical effect, or otherwise arrive at a desired result.

The logic processor may include one or more physical processors (hardware) configured to execute software instructions. Additionally or alternatively, the logic processor may include one or more hardware logic circuits or firmware devices configured to execute hardware-implemented logic or firmware instructions. Processors of the logic processor402may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel, and/or distributed processing. Individual components of the logic processor optionally may be distributed among two or more separate devices, which may be remotely located and/or configured for coordinated processing. Aspects of the logic processor may be virtualized and executed by remotely accessible, networked computing devices configured in a cloud-computing configuration. In such a case, these virtualized aspects are run on different physical logic processors of various different machines, it will be understood.

Non-volatile storage device406includes one or more physical devices configured to hold instructions executable by the logic processors to implement the methods and processes described herein. When such methods and processes are implemented, the state of non-volatile storage device406may be transformed—e.g., to hold different data.

Non-volatile storage device406may include physical devices that are removable and/or built-in. Non-volatile storage device406may include optical memory (e.g., CD, DVD, HD-DVD, Blu-Ray Disc, etc.), semiconductor memory (e.g., ROM, EPROM, EEPROM, FLASH memory, etc.), and/or magnetic memory (e.g., hard-disk drive, floppy-disk drive, tape drive, MRAM, etc.), or other mass storage device technology. Non-volatile storage device306may include nonvolatile, dynamic, static, read/write, read-only, sequential-access, location-addressable, file-addressable, and/or content-addressable devices. It will be appreciated that non-volatile storage device306is configured to hold instructions even when power is cut to the non-volatile storage device306.

Volatile memory404may include physical devices that include random access memory. Volatile memory404is typically utilized by logic processor402to temporarily store information during processing of software instructions. It will be appreciated that volatile memory404typically does not continue to store instructions when power is cut to the volatile memory404.

Aspects of logic processor402, volatile memory404, and non-volatile storage device406may be integrated together into one or more hardware-logic components. Such hardware-logic components may include field-programmable gate arrays (FPGAs), program- and application-specific integrated circuits (PASIC/ASICs), program- and application-specific standard products (PSSP/ASSPs), system-on-a-chip (SOC), and complex programmable logic devices (CPLDs), for example.

The terms “module,” “program,” and “engine” may be used to describe an aspect of computing system400typically implemented in software by a processor to perform a particular function using portions of volatile memory, which function involves transformative processing that specially configures the processor to perform the function. Thus, a module, program, or engine may be instantiated via logic processor402executing instructions held by non-volatile storage device406, using portions of volatile memory404. It will be understood that different modules, programs, and/or engines may be instantiated from the same application, service, code block, object, library, routine, API, function, etc. Likewise, the same module, program, and/or engine may be instantiated by different applications, services, code blocks, objects, routines, APIs, functions, etc. The terms “module,” “program,” and “engine” may encompass individual or groups of executable files, data files, libraries, drivers, scripts, database records, etc.

When included, display subsystem408may be used to present a visual representation of data held by non-volatile storage device406. The visual representation may take the form of a graphical user interface (GUI). As the herein described methods and processes change the data held by the non-volatile storage device, and thus transform the state of the non-volatile storage device, the state of display subsystem408may likewise be transformed to visually represent changes in the underlying data. Display subsystem408may include one or more display devices utilizing virtually any type of technology. Such display devices may be combined with logic processor402, volatile memory404, and/or non-volatile storage device406in a shared enclosure, or such display devices may be peripheral display devices.

When included, input subsystem410may comprise or interface with one or more user-input devices such as a keyboard, mouse, touch screen, or game controller. In some embodiments, the input subsystem may comprise or interface with selected natural user input (NUI) componentry. Such componentry may be integrated or peripheral, and the transduction and/or processing of input actions may be handled on- or off-board. Example NUI componentry may include a microphone for speech and/or voice recognition; an infrared, color, stereoscopic, and/or depth camera for machine vision and/or gesture recognition; a head tracker, eye tracker, accelerometer, and/or gyroscope for motion detection and/or intent recognition; as well as electric-field sensing componentry for assessing brain activity; and/or any other suitable sensor.

When included, communication subsystem412may be configured to communicatively couple various computing devices described herein with each other, and with other devices. Communication subsystem412may include wired and/or wireless communication devices compatible with one or more different communication protocols. As non-limiting examples, the communication subsystem may be configured for communication via a wireless telephone network, or a wired or wireless local- or wide-area network, such as a HDMI over Wi-Fi connection. In some embodiments, the communication subsystem may allow computing system400to send and/or receive messages to and/or from other devices via a network such as the Internet.

The following paragraphs discuss several aspects of the present disclosure. According to one aspect of the present disclosure, a computing device is provided, including a battery, a processor configured to receive electrical power from the battery via a voltage regulator, one or more additional electronic components configured to receive electrical power from the battery, and a first current detector. The first current detector may be configured to detect a total battery discharge current flowing from the battery to the processor via the voltage regulator and to the one or more additional electronic components. The voltage regulator may be configured to receive a first analog current signal from the first current detector, convert the first analog current signal into first digital current data, and transmit the first digital current data to the processor. The processor may be further configured to determine a difference between the total battery discharge current, as indicated by the first digital current data, and an available electric current limit for the battery. In response to at least determining the difference between the total battery discharge current and the available electric current limit, the processor may be further configured to adjust one or more performance parameters of the processor such that the difference is reduced.

According to this aspect, the one or more performance parameters may include a voltage supplied to the processor.

According to this aspect, the one or more performance parameters may include a clock rate of the processor.

According to this aspect, the computing device may further include a power supply unit (PSU) configured to supply electrical power to the computing device. The computing device may further include a second current detector configured to detect an electric current flowing to the computing device via the PSU. The voltage regulator may be further configured to receive a second analog current signal from the second current detector, convert the second analog current signal into second digital current data, and transmit the second digital current data to the processor. The processor may be further configured to adjust the one or more performance parameters of the processor based at least in part on the second digital current data.

According to this aspect, the computing device may further include a microcontroller. The computing device may further include a discharge rate detector configured to measure a discharge C-rate of the battery, and, based at least in part on the discharge C-rate, output a plurality of C-rate-based discharge thresholds to the microcontroller. The microcontroller may be configured to receive the plurality of C-rate-based discharge thresholds from the discharge rate detector, and, based at least in part on the plurality of C-rate-based discharge thresholds, transmit current limit update instructions to the processor. The processor may be further configured to modify the available electric current limit in response to at least receiving the current limit update instructions.

According to this aspect, the plurality of C-rate-based discharge thresholds may include a maximum sustained current and a maximum peak current of the battery.

According to this aspect, the processor may be configured to adjust the one or more performance parameters at least in part by performing proportional-integral-derivative (PID) control of the one or more performance parameters.

According to this aspect, the computing device may further include a power supply unit (PSU) configured to supply electrical power to the computing device. The computing device may further include a third current detector configured to detect a total system current flowing from the battery and the PSU to the processor and to one or more additional electronic components of the computing device. The voltage regulator may be further configured to receive a third analog current signal from the third current detector, convert the third analog current signal into third digital current data, and transmit the third digital current data to the processor. The processor may be further configured to adjust the one or more performance parameters of the processor based at least in part on the third digital current data.

According to this aspect, the computing device may further include a voltage detector configured to detect a voltage supplied to the processor by the battery via the voltage regulator and to the one or more additional electronic components. The voltage regulator may be further configured to receive analog voltage data from the voltage detector, convert the analog voltage data into digital voltage data, and transmit the digital voltage data to the processor. The processor may be further configured to adjust the one or more performance parameters of the processor based at least in part on the digital voltage data.

According to this aspect, the voltage regulator may further include a deglitching circuit configured to remove, from the first analog current signal, one or more overshoot components for which the total battery discharge current is greater than or equal to the available electric current limit for less than a deglitching timer duration.

According to this aspect, the deglitching timer duration may be longer than a current spike duration for which the processor is configured to operate at a warn-level current.

According to this aspect, the deglitching timer duration may be shorter than a current spike duration for which the processor is configured to operate at a warn-level current.

According to another aspect of the present disclosure, a method for use with a computing device is provided. The method may include, at a processor, receiving electrical power from a battery via a voltage regulator. The method may further include, at one or more additional electronic components, receiving electrical power from the battery. The method may further include, at a first current detector, detecting a total battery discharge current flowing from the battery to the processor via the voltage regulator and to the one or more additional electronic components. The method may further include, at the voltage regulator, receiving a first analog current signal from the first current detector, converting the first analog current signal into first digital current data, and transmitting the first digital current data to the processor. The method may further include, at the processor, determining a difference between the total battery discharge current, as indicated by the first digital current data, and an available electric current limit for the battery. In response to at least determining the difference between the total battery discharge current and the available electric current limit, the method may further include adjusting one or more performance parameters of the processor such that the difference is reduced.

According to this aspect, the one or more performance parameters are selected from the group comprising a voltage supplied to the processor and a clock rate of the processor.

According to this aspect, the method may further include, via a power supply unit (PSU), supplying electrical power to the computing device. The method may further include, at a second current detector, detecting an electric current flowing to the computing device via the PSU. The method may further include, at the voltage regulator, receiving a second analog current signal from the second current detector, converting the second analog current signal into second digital current data, and transmitting the second digital current data to the processor. The method may further include, at the processor, adjusting the one or more performance parameters of the processor based at least in part on the second digital current data.

According to this aspect, the method may further include, at a discharge rate detector, measuring a discharge C-rate of the battery. The method may further include, based at least in part on the discharge C-rate, outputting a plurality of C-rate-based discharge thresholds to a microcontroller. The method may further include, at the microcontroller, receiving the plurality of C-rate-based discharge thresholds from the discharge rate detector, and, based at least in part on the plurality of C-rate-based discharge thresholds, transmitting current limit update instructions to the processor. The method may further include, at the processor, modifying the available electric current limit in response to at least receiving the current limit update instructions.

According to this aspect, the method may further include, at a third current detector, detecting a total system current flowing from the battery and a power supply unit (PSU) to the processor and to one or more additional electronic components of the computing device. The method may further include, at the voltage regulator, receiving a third analog current signal from the third current detector, converting the third analog current signal into third digital current data, and transmitting the third digital current data to the processor. The method may further include, at the processor, adjusting the one or more performance parameters of the processor based at least in part on the third digital current data.

According to this aspect, the method may further include, at a voltage detector, detecting a voltage supplied to the processor by the battery via the voltage regulator and to the one or more additional electronic components. The method may further include, at the voltage regulator, receiving analog voltage data from the voltage detector, converting the analog voltage data into digital voltage data, and transmitting the digital voltage data to the processor. The method may further include, at the processor, adjusting the one or more performance parameters of the processor based at least in part on the digital voltage data.

According to this aspect, the method may further include, at a deglitching circuit included in the voltage regulator, removing, from the first analog current signal, one or more overshoot components that indicate for which the total battery discharge current is greater than or equal to the available electric current limit for less than a deglitching timer duration.

According to another aspect of the present disclosure, a computing device is provided, including a battery, a power supply unit (PSU) configured to supply electrical power to the computing device, a processor configured to receive electrical power from the battery and the PSU via a voltage regulator, one or more additional electronic components configured to receive electrical power from the battery and the PSU, and a current detector. The current detector may be configured to detect a total system current flowing from the battery and the PSU to the processor and to one or more additional electronic components of the computing device. The computing device may further include an additional current detector configured to detect an electric current flowing from the PSU to the computing device. The voltage regulator may be configured to receive an analog current signal from the current detector and additional analog current signal from the additional current detector. The voltage regulator may be further configured to convert the analog current signal into digital current data and the additional analog current signal into additional digital current data. The voltage regulator may be further configured to transmit the digital current data and the additional digital current data to the processor. The processor may be further configured to, based at least in part on the digital current data, determine a total battery discharge current flowing from the battery to the processor and to the one or more additional electronic components. The processor may be further configured to determine a difference between the total battery discharge current and an available electric current limit of the battery. In response to at least determining the difference between the total battery discharge current and the available electric current limit, the processor may be further configured to adjust one or more performance parameters of the processor such that the difference is reduced.

It will be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated and/or described may be performed in the sequence illustrated and/or described, in other sequences, in parallel, or omitted. Likewise, the order of the above-described processes may be changed.

The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.