Patent ID: 12196695

DETAILED DESCRIPTION

Preferred embodiments and their advantages are best understood by reference toFIGS.1and2, wherein like numbers are used to indicate like and corresponding parts.

For the purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, an information handling system may be a personal computer, a personal digital assistant (PDA), a consumer electronic device, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include memory, one or more processing resources such as a central processing unit (“CPU”) or hardware or software control logic. Additional components of the information handling system may include one or more storage devices, one or more communications ports for communicating with external devices as well as various input/output (“I/O”) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more busses operable to transmit communication between the various hardware components.

For the purposes of this disclosure, computer-readable media may include any instrumentality or aggregation of instrumentalities that may retain data and/or instructions for a period of time. Computer-readable media may include, without limitation, storage media such as a direct access storage device (e.g., a hard disk drive or floppy disk), a sequential access storage device (e.g., a tape disk drive), compact disk, CD-ROM, DVD, random access memory (RA), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and/or flash memory; as well as communications media such as wires, optical fibers, microwaves, radio waves, and other electromagnetic and/or optical carriers; and/or any combination of the foregoing.

For the purposes of this disclosure, information handling resources may broadly refer to any component system, device or apparatus of an information handling system, including without limitation processors, service processors, BIOSs, buses, memories, I/O devices and/or interfaces, storage resources, network interfaces, motherboards, and/or any other components and/or elements of an information handling system.

For the purposes of this disclosure, a circuit board may broadly refer to a printed circuit board (PCB), printed wiring board (PWB), printed wiring assembly (PWA) etched wiring board, and/or any other board or similar physical structure operable to mechanically support and electrically couple electronic components (e.g., packaged integrated circuits, slot connectors, etc.). A circuit board may comprise a substrate of a plurality of conductive layers separated and supported by layers of insulating material laminated together, with conductive traces disposed on and/or in any of such conductive layers, with vias for coupling conductive traces of different layers together, and with pads for coupling electronic components (e.g., packaged integrated circuits, slot connectors, etc.) to conductive traces of the circuit board.

FIG.1illustrates a block diagram of selected components of an example information handling system102, in accordance with certain embodiments of the present disclosure. It is noted that the various components depicted inFIG.1may not be drawn to scale.

In some embodiments, information handling system102may comprise a server. In other embodiments, information handling system102may be a personal computer (e.g., a desktop computer, a laptop, notebook, tablet, handheld, smart phone, personal digital assistant, etc.). As depicted inFIG.1, information handling system102may include a circuit board101(e.g., a motherboard or backplane) having mounted and/or formed thereon a processor103, a memory104comprising a plurality of memory modules106communicatively coupled to processor103, and a management controller112communicatively coupled to processor103.

Processor103may include any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include, without limitation, a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, processor103may interpret and/or execute program instructions and/or process data stored in memory104and/or another component of information handling system102.

Memory104may be communicatively coupled to processor103and may include any system, device, or apparatus configured to retain program instructions and/or data for a period of time (e.g., computer-readable media). Memory104may include RAM, EEPROM, a PCMCIA card, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and/or array of volatile or non-volatile memory that retains data after power to information handling system102is turned off.

In some embodiments, one or more of processor103and memory modules106may be implemented using ball grid array integrated circuits, by which an integrated circuit package is electrically coupled to a circuit board via an array of solder balls, which are briefly heated during manufacturing to melt the solder balls sufficiently to create electrical connections between the integrated circuit and circuit board, before being cooled to return the solder to its solid state.

As depicted inFIG.1, each integrated circuit package of one or more of processor103and memory modules106may have one or more internal electrical couplings114between pairs of solder balls116. For purposes of clarity and exposition, each of processor103and memory modules106are shown inFIG.1having three internal electrical couplings114routed among solder balls116located at the corners of the integrated circuit packages of processor103and memory modules106. However, it is understood that processor103and/or a memory module106may have any suitable number of internal electrical couplings114, including as few as one internal electrical coupling114between two solder balls116, or significantly more electrical couplings114than the three shown inFIG.1. Further, it is also understood that internal electrical couplings114are not limited to being coupled between solder balls116located at the corners of integrated circuit packages of processor103and memory modules106, and may be coupled between solder balls116located at any suitable location within an integrated circuit package.

Furthermore, whileFIG.1, for purposes of clarity and exposition, depicts the presence of only four solder balls116at the corners of each of the integrated circuit packages for processor103and memory modules106, it is understood that an integrated circuit package may include numerous (e.g., dozens) of solder balls116of any suitable geometry, including many solder balls116arranged in a two-dimensional array.

In addition, each internal electrical coupling114may be routed between a pair of solder balls116within an integrated circuit package, but not necessarily routed within the integrated circuit (e.g., semiconductor die) itself. Accordingly, routing of internal electrical couplings114among solder balls116may be performed without modifications to integrated circuits themselves, meaning existing integrated circuits can be packaged within integrated circuit packages having the desired routing of internal electrical couplings114among solder balls116.

Management controller112may be configured to provide out-of-band management facilities for management of information handling system102. Such management may be made by management controller112even if information handling system102is powered off or powered to a standby state. Management controller112may include a processor, memory, out-of-band network interface separate from and physically isolated from an in-band network interface of information handling system102, and/or other embedded information handling resources. In certain embodiments, management controller112may include or may be an integral part of a baseboard management controller (BMC) or a remote access controller (e.g., a Dell Remote Access Controller or Integrated Dell Remote Access Controller). In other embodiments, management controller112may include or may be an integral part of a chassis management controller (CMC). In yet other embodiments, management controller112may include or may be an integral part of an embedded controller (EC). Management controller112may include firmware comprising a program of executable instructions configured to be read and executed by management controller112in order to carry out the functionality of management controller112, including functionality of management controller112described herein.

As also shown inFIG.1, the various internal electrical couplings114and solder balls116to which they are coupled may be arranged in a series configuration (e.g., with traces118formed on circuit board101electrically coupling solder balls116of different integrated circuit packages to one another. A general-purpose output (GPO) pin of management controller112may be electrically coupled to a first electrical node at one end of the series configuration and a general-purpose input (GPI) pin of management controller112may be coupled to a second electrical node at the other end of the series configuration.

In operation, if a mechanical strain force or torsion is applied to circuit board101capable of cracking solder, one or more of solder balls116may crack, resulting in an impedance discontinuity. In some instances, such impedance discontinuity may result in an open circuit, while in other instances, such impedance discontinuity may result from a partial crack in one or more of solder balls116, and thus may result in a significant increase in impedance through the series configuration.

Accordingly, in order to detect whether such an impedance discontinuity has occurred, management controller112may output a known signal (e.g., 3.3 volts) on its GPO pin, and determine if the same signal is received at its GPI pin. If the known signal is received at the GPI pin, then no strain-force induced event is determined to have occurred. However, if the known signal is not received at the GPI pin (e.g., significantly less than 3.3 volts), then a strain-force induced event may have occurred.

In addition to processor103, memory104, and management controller112, information handling system102may include one or more other information handling resources.

FIG.2illustrates a flow chart of an example method200for detecting and processing mechanical strain on a ball (e.g., a solder ball116) of a ball grid array, in accordance with embodiments of the present disclosure. According to certain embodiments, method200may begin at step202. As noted above, teachings of the present disclosure may be implemented in a variety of configurations of information handling system102as shown inFIG.1. As such, the preferred initialization point for method200and the order of the steps comprising method200may depend on the implementation chosen. In these and other embodiments, method200may be implemented as firmware, software, applications, functions, libraries, or other instructions.

At step202, management controller112may set its GPO pin to a known signal (e.g., 3.3 volts). At step204, management controller112may determine if the known signal is received at its GPI pin. If the known signal (e.g., 3.3 V) is received at the GPI pin, no impedance discontinuity exists within solder balls116, and method200may end. Otherwise if the known signal is not received at the GPI pin (e.g., a voltage significantly less than 3.3 volts is received), then an impedance discontinuity may exist within one or more solder balls116, and method200may proceed to step206.

At step206, management controller112may log the strain event. As a result, at step208, a basic input/output system (BIOS) setup menu may be invoked (e.g., at a subsequent startup or boot session of information handling system102) notifying a user of information handling system102of the event and/or providing options to such user of how to remedy the event. After completion of step208, method200may end.

AlthoughFIG.2discloses a particular number of steps to be taken with respect to method200, method200may be executed with greater or fewer steps than those depicted inFIG.2. In addition, althoughFIG.2discloses a certain order of steps to be taken with respect to method200, the steps comprising method200may be completed in any suitable order.

Method200may be implemented using information handling system102, components thereof, or any other system such as that shown inFIG.1operable to implement method200. In certain embodiments, method200may be implemented partially or fully in software and/or firmware embodied in computer-readable media.

As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

Although exemplary embodiments are illustrated in the figures and described above, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the figures and described above.

Unless otherwise specifically noted, articles depicted in the figures are not necessarily drawn to scale.

All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.

Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description.

To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.