Patent ID: 12237419

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Various embodiments provide a gate structure in a transistor device and methods of forming same. The gate structure may be formed without first forming any dummy gate structures (e.g., a polysilicon gate structure). For example, an interlayer dielectric (ILD) may be deposited directly on channel regions and source/drain regions of a substrate. The ILD may then be etched to define openings exposing the channel regions, and various layers of gate dielectrics and gate electrode materials may be deposited in the openings, thereby forming gate stacks. Accordingly, various advantages can be achieved, such as a simplified process flow, easier processing (e.g., without having to pattern high aspect ratio, dummy gates), and reduced manufacturing cost.

FIG.1illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. The FinFET comprises a fin52on a substrate50(e.g., a semiconductor substrate). Isolation regions56are disposed in the substrate50, and the fin52protrudes above and from between neighboring isolation regions56. Although the isolation regions56are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fin52is illustrated as a single, continuous material as the substrate50, the fin52and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fin52refers to the portion extending between the neighboring isolation regions56.

A gate dielectric layer92is along sidewalls and over a top surface of the fin52, and a gate electrode94is over the gate dielectric layer92. Source/drain regions82are disposed in opposite sides of the fin52with respect to the gate dielectric layer92and gate electrode94.FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of the gate electrode94and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions82of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin52and in a direction of, for example, a current flow between the source/drain regions82of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through a source/drain region of the FinFET. Subsequent figures refer to these reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), or the like.

FIGS.2through17Care cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.2through6illustrate reference cross-section A-A illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.7A,8A,9A,10A,11A,12A,13A,14A,15A,16A, and17Aare illustrated along reference cross-section A-A illustrated inFIG.1, andFIGS.7B,8B,9B,10B,11B,12B,13B,14B,15B,16B, and17Bare illustrated along a similar cross-section B-B illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.7C,8C,8D,8E,9C,16C, and17Care illustrated along reference cross-section C-C illustrated inFIG.1, except for multiple fins/FinFETs.

InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.

The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region50N may be physically separated from the p-type region50P (as illustrated by divider51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P.

InFIG.3, fins52are formed in the substrate50. The fins52are semiconductor strips. In some embodiments, the fins52may be formed in the substrate50by etching trenches in the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic.

The fins may be patterned by any suitable method. For example, the fins52may be patterned using one or more photolithography and etching processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins52.

InFIG.4, an insulation material54is formed over the substrate50and between neighboring fins52. The insulation material54may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material54is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material54is formed such that excess insulation material54covers the fins52. Although the insulation material54is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not shown) may first be formed along a surface of the substrate50and the fins52. Thereafter, a fill material, such as those discussed above may be formed over the liner.

InFIG.5, a removal process is applied to the insulation material54to remove excess insulation material54over the fins52. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the fins52such that top surfaces of the fins52and the insulation material54are level after the planarization process is complete. In embodiments in which a mask remains on the fins52, the planarization process may expose the mask or remove the mask such that top surfaces of the mask or the fins52, respectively, and the insulation material54are level after the planarization process is complete.

InFIG.6, the insulation material54is recessed to form Shallow Trench Isolation (STI) regions56. The insulation material54is recessed such that upper portions of fins52in the n-type region50N and in the p-type region50P protrude from between neighboring STI regions56. Further, the top surfaces of the STI regions56may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions56may be formed flat, convex, and/or concave by an appropriate etch. The STI regions56may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material54(e.g., etches the material of the insulation material54at a faster rate than the material of the fins52). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used.

The process described with respect toFIGS.2through6is just one example of how the fins52may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins52. For example, the fins52inFIG.5can be recessed, and a material different from the fins52may be epitaxially grown over the recessed fins52. In such embodiments, the fins52comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together.

Still further, it may be advantageous to epitaxially grow a material in n-type region50N (e.g., an NMOS region) different from the material in p-type region50P (e.g., a PMOS region). In various embodiments, upper portions of the fins52may be formed from silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

Further inFIG.6, appropriate wells (not shown) may be formed in the fins52and/or the substrate50. In some embodiments, a P well may be formed in the n-type region50N, and an N well may be formed in the p-type region50P. In some embodiments, a P well or an N well are formed in both the n-type region50N and the p-type region50P.

In the embodiments with different well types, the different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist and/or other masks (not shown). For example, a photoresist may be formed over the fins52and the STI regions56in the n-type region50N. The photoresist is patterned to expose the p-type region50P of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as between about 1016cm−3and about 1018cm−3. After the implant, the photoresist is removed, such as by an acceptable ashing process.

Following the implanting of the p-type region50P, a photoresist is formed over the fins52and the STI regions56in the p-type region50P. The photoresist is patterned to expose the n-type region50N of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as between about 1016cm−3and about 1018cm−3. After the implant, the photoresist may be removed, such as by an acceptable ashing process.

After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

FIGS.7A through17Cillustrate various additional steps in the manufacturing of embodiment devices.FIGS.7A through17Cillustrate features in either of the n-type region50N and the p-type region50P. For example, the structures illustrated inFIGS.7A through17Cmay be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure.

InFIGS.7A through8Depitaxial source/drain regions82are formed in the fins52. In some embodiments the epitaxial source/drain regions82may extend into, and may optionally penetrate through, the fins52. Referring toFIGS.7A through7C, recesses62are patterned into the fins using a combination of photolithography and etching. For example, a hard mask60may be formed over the fins52. The hard mask60may comprise silicon nitride, silicon oxynitride, or the like that allows the hard mask60to be patterned at a faster rate than the underlying features, such as the STI56and the fins52, The hard mask60may be deposited by CVD, ALD, PVD, or the like. Subsequently, the hard mask60may be patterned using one or more photolithography and etching processes, including double-patterning or multi-patterning processes.

One or more etching process may then be applied to pattern the recesses62in the fins52. In the illustrated embodiments, the recesses62may extend below a top surface of the STI regions56(seeFIG.7C) such that top surfaces of the fins52are below a top surface of the STI regions56in the cross-section C-C. In other embodiments, a top surface of the fins52may be level with or above the top surface of the STI regions56. The recesses62may be spaced apart by respective channel regions58of the fins52(seeFIG.7B), and gate structures may be formed over and along sidewalls of the channel regions58in subsequent processing steps. After the recesses62are patterned, the hard mask60may be removed using, for example, one or more wet cleaning processes, or the like.

InFIGS.8A through8D, epitaxial source/drain regions82may be formed in the recesses62. A material of the epitaxial source/drain regions82may be selected to exert stress in the respective channel regions58, thereby improving performance. The epitaxial source/drain regions82in the n-type region50N may be formed by masking the p-type region50P. Then, the epitaxial source/drain regions82in the n-type region50N are epitaxially grown in the recesses62. The epitaxial source/drain regions82may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions82in the n-type region50N may include materials exerting a tensile strain in the channel region58, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions82in the n-type region50N may have surfaces raised from respective surfaces of the fins52and may have facets.

The epitaxial source/drain regions82in the p-type region50P may be formed by masking the n-type region50N. Then, the epitaxial source/drain regions82in the p-type region50P are epitaxially grown in the recesses62. The epitaxial source/drain regions82may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions82in the p-type region50P may comprise materials exerting a compressive strain in the channel region58, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions82in the p-type region50P may have surfaces raised from respective surfaces of the fins52and may have facets.

The epitaxial source/drain regions82and/or the fins52may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1019cm−3and about 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions82may be in situ doped during growth.

As a result of the epitaxy processes used to form the epitaxial source/drain regions82in the n-type region50N and the p-type region50P, upper surfaces of the epitaxial source/drain regions82have facets which expand laterally outward beyond sidewalls of the fins52. Further, the upper surfaces of the epitaxial source/drain regions82may extend above an upper surface of the fins52by a distance D1. The distance D1may be greater than 10 nm, such as greater than 20 nm in some embodiments. In other embodiments, upper surfaces of the epitaxial source/drain regions82may be level with an upper surface of the fins52(seeFIGS.8A and8B). In some embodiments, these facets cause adjacent source/drain regions82of a same FinFET to merge as illustrated byFIG.8C. In other embodiments, adjacent source/drain regions82remain separated (e.g., remain unmerged) after the epitaxy process is completed as illustrated byFIG.8E. In some embodiments, a single chip may include both merged and unmerged source/drain regions82depending on circuit design and device density.

InFIGS.9A through9C, a first interlayer dielectric (ILD)88is deposited over the structure illustrated inFIGS.8A through8E. AlthoughFIGS.9A through9Cand subsequent figures only illustrates processing on the embodiments of merged, epitaxial source/drain regions82with raised upper surfaces (e.g., according toFIGS.8B and8C), similar processes may also be applied to unmerged, epitaxial source/drain regions82(e.g., seeFIG.8D) and/or epitaxial source/drain regions82without raised upper surfaces (e.g., seeFIG.8E).

The first ILD88may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. After deposition, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD88. The first ILD88may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)87is disposed between the first ILD88and the epitaxial source/drain regions82and the fins52. The CESL87may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, having a lower etch rate than the material of the overlying first ILD88. The first ILD88and the CESL87may cover the channel regions58and may further extend continuously between neighboring pairs of the epitaxial source/drain regions82. In some embodiments, a thickness T1of the CESL87may be in a range of about 2 nm to about 10 nm. Notably, the first ILD88and the CESL87may be formed prior to forming any gate structures (e.g., any dummy gates or any functional gates).

As further illustrated byFIGS.9A through9C, a hard mask90may be formed and patterned over the first ILD88to expose areas corresponding to subsequently formed gate stacks. The hard mask90may comprise silicon nitride, silicon oxynitride, or the like that allows the hard mask90be patterned at a faster rate than the underlying features, such as the first ILD88. The hard mask90may be deposited by CVD, ALD, PVD, or the like. Subsequently, the hard mask90may be patterned using one or more photolithography and etching processes, including double-patterning or multi-patterning processes.

InFIGS.10A through10B, openings91are etched through the first ILD88and the CESL87using the hard mask90as an etching mask. The openings91may be etched using a wet etch process, a dry etch process, combinations thereof, or the like. The etching may be anisotropic. The openings91may extend through the first ILD88and the CESL87to expose a top surface of the fins52, such as, the channel regions of the fins52. The openings91may be disposed between adjacent epitaxial source/drain regions82.

As a result of the etching process, sidewalls of the first ILD88may be curved (e.g., concave) at bottoms of the openings91. This region of the first ILD88(e.g., with curved sidewalls) may be referred to as footing regions88A. In some embodiments, a length L1of the footing regions88A may be in a range of about 0.5 nm to about 2 nm. The length L1may refer to a lateral distance between a vertical sidewall of the first ILD88and a farthest point that the first ILD88extends into the openings91. In other embodiments, the footing regions88A may have a different length. The footing region88A may further result in the bottoms of in the openings91tapering and decreasing in width in a direction towards the fins52.

InFIGS.11A and11B, a spacer layer93is deposited along sidewalls and a bottom surface of the recesses91. The spacer layer93may be formed by conformally depositing an insulating material, such as, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, a thickness T2of the spacer layer93may be in a range of about 2 nm to about 10 nm, for example. Due to the footing regions88A of the first ILD88, bottom portions of the spacer layer93may also have curved sidewalls.

Subsequently, as illustrated inFIGS.12A and12B, an anisotropic etching process may be performed to remove lateral portions of the spacer layer93, thereby forming sidewall spacers95. In some embodiments, portions of the sidewall spacers95in the footing regions88A may have curved sidewalls, and the spacers may taper (e.g., decrease) in width adjacent to the footing regions88A. The sidewall spacers95may line sidewalls of the recesses91to provide insulation and an appropriate spacing between subsequently formed gate stacks and the epitaxial source/drain regions82.

InFIGS.13A and13B, gate dielectric layers92and gate electrodes94are formed for replacement gates. Gate dielectric layers92include one or more layers deposited in the recesses91, such as on the top surfaces and the sidewalls of the fins52and on sidewalls of the sidewall spacers95. The gate dielectric layers92may also be formed on the top surface of the first ILD88. In some embodiments, the gate dielectric layers92comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layers92include an interfacial layer92A of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material92B, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The high-k dielectric material92B may have a k value greater than about 7.0, for example. The formation methods of the gate dielectric layers92may include Molecular-Beam Deposition (MBD), PVD, ALD, PECVD, and the like.

The gate electrodes94are deposited over the gate dielectric layers92, respectively, and fill the remaining portions of the recesses91. The gate electrodes94may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. The gate electrode94may comprise any number of liner layers94A (e.g., diffusion barrier layers, adhesion layers, and/or the like), any number of work function tuning layers94B, and a fill material94C. In some embodiments, one or more of the liner layers94A may be interposed between the work function tuning layers94B and the fill material94C. After the filling of the recesses91, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers92and the material of the gate electrodes94, which excess portions are over the top surface of the first ILD88. The remaining portions of material of the gate electrodes94and the gate dielectric layers92thus form functional gates of the resulting FinFETs. The gate electrodes94and the gate dielectric layers92may be collectively referred to as a “gate stack96.” The gate stacks96may extend along sidewalls of a channel region58of the fins52.

In some embodiments, the gate stacks96may have curved sidewalls adjacent to the footing regions88A of the first ILD88, and a portion of the CESL87may extend directly under the gate stacks96/the sidewall spacers95. Further, the gate stacks96may have a maximum width W1(e.g., a width at a top surface of the first ILD88) that is in a range of about 10 nm to about 100 nm. The lower portions of the gate stacks96may taper (e.g., decrease) in width in a direction towards the fins52. Further, a width W2of the first ILD88between adjacent ones of the gate stacks96may be in a range of about 10 nm to about 100 nm.

In various embodiments the gate stacks96may be formed without first forming any other gate stacks (including any dummy gates). As a result, the manufacturing process for forming a semiconductor device can be simplified, thereby reducing manufacturing costs. Further, relatively thin sidewall spacers can be formed, thereby enlarging a process window for forming the gate stack96and reducing an aspect ratio during the depositing process for forming the layers of the gate stack96(e.g., the gate dielectric layers92and the gate electrodes94). It has been observed that by providing sidewall spacers95with thicknesses in a range of about 2 nm to about 10 nm, manufacturing defects due to high aspect ratio gap fill can be reduced while still providing adequate isolation between the gate stacks96and subsequently formed source/drain contacts.

The formation of the gate dielectric layers92in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectric layers92in each region are formed from the same materials, and the formation of the gate electrodes94may occur simultaneously such that the gate electrodes94in each region are formed from the same materials. In some embodiments, the gate dielectric layers92in each region may be formed by distinct processes, such that the gate dielectric layers92may be different materials, and/or the gate electrodes94in each region may be formed by distinct processes, such that the gate electrodes94may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

InFIGS.14A through15B, a gate mask98is formed over the gate stacks96(including a gate dielectric layer92and a corresponding gate electrode94), and the gate mask may be disposed between opposing portions of the gate spacers86. In some embodiments, forming the gate mask98includes recessing the gate stacks96so that a recess is formed directly over the gate stack and between opposing portions of sidewall spacers95. After recessing, a height H1of the gate stacks96may be in a range of about 10 nm to about 80 nm. A gate mask98comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess (seeFIGS.14A through14B), followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD88(seeFIGS.15A through15B). After planarization, a thickness H2of the gate mask98may be in a range of about 10 nm to about 89 nm. The gate mask98may be thicker than, thinner than, or have an equal thickness as the gate stacks96. The gate mask98is optional and may be omitted in some embodiments. In such embodiments, the gate stack may remain level with top surfaces of the first ILD88.

InFIGS.16A through16C, first level source/drain contacts100are formed through the first ILD88in accordance with some embodiments. Openings for the source/drain contacts100are formed through the first ILD88. The openings may be formed using acceptable photolithography and etching techniques. In some embodiments, forming the openings may also etch upper portions of the epitaxial source/drain region. In some embodiments, a distance that the epitaxial source/drain regions82extend above the fins52after forming the openings may be at least about 10 nm. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the first ILD88. The remaining liner and conductive material form the source/drain contacts100in the openings. An anneal process may be performed to form a silicide101at the interface between the epitaxial source/drain regions82and the source/drain contacts100. The source/drain contacts100are physically and electrically coupled to the epitaxial source/drain regions82.

InFIGS.17A through17C, a second ILD104is deposited over the first ILD88. In some embodiments, the second ILD104is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD104is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. An optional etch stop layer102may be formed between the first ILD88and the second ILD104. In some embodiments the etch stop layer (ESL)102may comprise silicon nitride, silicon oxynitride, silicon oxide, or the like and may be deposited by CVD, PVD, ALD, or the like.

As also illustrated inFIGS.17A through17C, gate contacts110and source/drain contacts112are formed through the second ILD104and the ESL102in accordance with some embodiments. Openings for the source/drain contacts112are formed through the second ILD104and the ESL102, and openings for the gate contact110are formed through the second ILD104and the gate mask98(if present). In some embodiments, the openings for the source/drain contacts112and/or the gate contact110may further etch the source/drain contacts100and/or the gate electrode94, respectively. The openings may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD104. The remaining liner and conductive material form the source/drain contacts112and gate contacts110in the openings. The source/drain contacts112are physically and electrically coupled to the epitaxial source/drain regions82through the source/drain contacts100, and the gate contacts110are physically and electrically coupled to the gate electrodes94. The source/drain contacts112and gate contacts110may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts112and gate contacts110may be formed in different cross-sections, which may avoid shorting of the contacts.

In some embodiments (e.g., as illustrated byFIGS.17A through17C), the first level source/drain contacts100has contacting the sidewalls spacers95, and may further extend continuously from a first sidewall spacer95to an adjacent sidewall spacer95(not explicitly illustrated). In other embodiments, a portion of the first ILD88may remain between and physically separate the source/drain contacts100and the sidewall spacers95as illustrated byFIGS.18A through18C.FIG.18Ais illustrated along reference cross-section A-A illustrated inFIG.1, andFIG.18Bis illustrated along a similar cross-section B-B illustrated inFIG.1, except for multiple fins/FinFETs.FIG.18Cillustrated along reference cross-section C-C illustrated inFIG.1, except for multiple fins/FinFETs.

The disclosed FinFET embodiments could also be applied to other types of transistors such as planar transistors, nanostructure devices such as nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), or the like. In a planar transistor embodiment, the fins52are excluded, and the gate stack96is formed on a flat surface of a semiconductor substrate.FIG.19illustrates an embodiment planar device where like reference numerals indicate like elements formed by like processes as the embodiments ofFIGS.2through17C. InFIG.19, the fins52are excluded, and the gate stacks96do not extend along the sidewalls of any channel regions58.

In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source/drain regions are formed in a manner similar to the above-described embodiments. Gate isolation structures are also formed to extend through the dummy gate stacks as described above. After the dummy gate stacks are removed, the sacrificial layers can be partially or fully removed in channel regions. The replacement gate structures are formed in a manner similar to the above-described embodiments, the replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments.

FIG.20illustrates a perspective view of a NSFET according to some embodiments.FIGS.21A through21Cillustrate cross-sectional views of various embodiments—in a NSFET context. Referring toFIG.20, NSFET devices comprise nanostructures55(e.g., nanosheets, nanowire, or the like) over fins52on a substrate50(e.g., a semiconductor substrate), wherein the nanostructures55act as channel regions for the NSFET devices. The nanostructure55may include p-type nanostructures, n-type nanostructures, or a combination thereof. The STI regions56are disposed between adjacent fins52, which may protrude above and from between neighboring STI regions56. The gate dielectric material92is over top surfaces of the fins52and along top surfaces, sidewalls, and bottom surfaces of the nanostructures55. Gate electrodes94are over the gate dielectric material92. Epitaxial source/drain regions82are disposed on the fins52on opposing sides of the gate stacks92/94.

FIG.20further illustrates reference cross-sections that are used in later figures. Cross-section X-X is along a longitudinal axis of a gate electrode94and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source/drain regions82of a NSFET devices. Cross-section Y-Y is perpendicular to cross-section X-X and is parallel to a longitudinal axis of a fin52of the NSFET devices and in a direction of, for example, a current flow between the epitaxial source/drain regions82of the NSFET devices.FIG.21Aillustrates an embodiment NSFET device incorporating a gate stack96(e.g., as formed and described above inFIGS.2through15C) along the cross-section X-X ofFIG.20, andFIG.21Billustrates the NSFET device incorporating the gate stack96along the cross-section Y-Y ofFIG.20. Various features ofFIGS.21A and21Bmay be similar to those described above inFIGS.1through17Cwhere like reference numerals indicate like elements formed by like processes. For example, inFIGS.21A and21B, the gate stacks96may be formed prior to any other gate structures (e.g., dummy gates) by directly etching openings in the first ILD88to expose channel regions and forming the gate stacks96in the openings. Lower portions of the gate stacks96may taper (e.g., decrease) in width in a direction towards the underlying substrate50. Further, gate sidewall spacers may be disposed between the gate stacks96and the epitaxial source/drain regions82to prevent electrical shorts.

Various embodiments provide a gate structure in a transistor device and methods of forming same. The gate structure may be formed without first forming any dummy gate structures (e.g., a polysilicon gate structure). For example, an interlayer dielectric (ILD) may be deposited directly on channel regions and source/drain regions of a substrate. The ILD may then be etched to define openings exposing the channel regions, and various layers of gate dielectrics and gate electrode materials may be deposited in the openings, thereby forming gate stacks. Accordingly, various advantages can be achieved, such as a simplified process flow, easier processing (e.g., without having to pattern high aspect ratio, dummy gates), and reduced manufacturing cost.

In an embodiment, a method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers. Optionally, in some embodiments, a width of the opening in a lower region of the opening decreases in width in a direction towards the semiconductor fin. Optionally, in some embodiments, an interface between the first sidewall spacers and the first dielectric layer is curved. Optionally, in some embodiments, an interface between the first sidewall spacers and the gate stack is curved. Optionally, in some embodiments, the method further includes prior to depositing the first dielectric layer depositing a contact etch stop layer (CESL) on an upper surface of the semiconductor fin, over the first source/drain region, and over the second source/drain region, wherein patterning the opening comprises etching the CESL. Optionally, in some embodiments, depositing the first dielectric layer comprises depositing a portion of the first dielectric layer to extend continuously from the first source/drain region to the second source/drain region; depositing the CESL comprises depositing a portion of the CESL to extend continuously from the first source/drain region to the second source/drain region; and etching an opening comprises removing the portion of the first dielectric layer and removing the portion of the CESL. Optionally, in some embodiments, a thickness of each of the first sidewall spacers is in a range of 2 nm to 10 nm. Optionally, in some embodiments, the method further includes recessing the gate stack and forming an insulating gate mask over the gate stack.

In an embodiment, a method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a contact etch stop layer over the semiconductor fin, the first source/drain region, and the second source/drain region; depositing a first dielectric layer over contact etch stop layer; etching the first dielectric layer and the contact etch stop layer to form an opening that exposes the semiconductor fin, wherein after forming the opening, the first dielectric layer comprises a footing region with a curved sidewall that extends into the opening; and forming a gate stack in the opening, wherein at least a lower portion of the gate stack tapers in width in a direction towards the semiconductor fin. Optionally, in some embodiments, a lateral distance between a vertical sidewall of the first dielectric layer and a farthest point that the footing region extends into the opening is in a range of 0.5 nm to 2 nm. Optionally, in some embodiments, the method further includes depositing a spacer layer on sidewalls and a bottom surface of the opening; and etching the spacer layer to form sidewall spacers on sidewalls of the opening. Optionally, in some embodiments, a thickness of the spacer layer is in a range of 2 nm to 10 nm. Optionally, in some embodiments, at least a lower portion of each of the sidewall spacers tapers in width in a direction towards the semiconductor fin. Optionally, in some embodiments, the method further includes forming a first source/drain contact through the first dielectric layer, wherein the first source/drain contact is electrically connected to the first source/drain region; and forming a second source/drain contact through the first dielectric layer, wherein the second source/drain contact is electrically connected to the second source/drain region.

In an embodiment, a device includes a semiconductor fin extending from a semiconductor substrate; a first source/drain region and a second source/drain region in a semiconductor fin; a interlayer dielectric over the semiconductor substrate; a gate stack between the first source/drain region and the second source/drain region, wherein at least a lower portion of the gate stack decreases in width in a direction towards the semiconductor substrate; a first source/drain contact extending through the interlayer dielectric to the first source/drain region; and a second source/drain contact extending through the interlayer dielectric to the second source/drain region. Optionally, in some embodiments, the device further includes a contact etch stop layer on a top surface of the semiconductor fin, wherein the contact etch stop layer is disposed directly under the gate stack. Optionally, in some embodiments, the lower portion of the gate stack has a curved sidewall. Optionally, in some embodiments, the device further includes a first sidewall spacer between the gate stack and the first source/drain contact; and a second sidewall spacer between the gate stack and the second source/drain contact. Optionally, in some embodiments, the first sidewall spacer and the second sidewall spacer each decrease in width in a direction towards the semiconductor substrate. Optionally, in some embodiments, a thickness of the first sidewall spacer is in a range of 2 nm to 10 nm, and wherein a thickness of the second sidewall spacer is in a range of 2 nm to 10 nm.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.