Patent ID: 12245422

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

It can be known from the background that the conductivity of the bit lines and the electrical performance of the semiconductor structure need to be improved.

The bit lines usually include a bit line contact layer and a conductive layer arranged in a stack. With the improvement of the integration degree of DRAM, the physical size of the bit lines is further reduced. As the area is reduced, the contact resistance between the bit line contact layer and the conductive layer is increased, and the conductivity of the bit line itself is decreased; further, the contact area between the bit line contact layer and the substrate is also reduced, resulting in increased contact resistance between the line and the substrate; at the same time, the conductivity of the bit line contact layer is usually lower than that of the conductive layer. Thus, the greater ratio the bit line contact layer is in the bit lines, the higher overall resistance of the bit lines will be.

The present application provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure, since there is a non-planar contact portion in a direction away from the bottom surface of the trench, the conductive layer is in contact with the non-planar contact portion, that is, the conductive layer and the bit line contact layer. On the one hand, in the plane perpendicular to the direction of the bit line contact layer pointing to the conductive layer, while ensuring that the cross-sectional area of the bit line contact layer and the conductive layer on this plane is small, it is beneficial to increase the contact area between the bit line contact layer and the conductive layer, thereby reducing the resistance of the bit line itself including the bit line contact layer and the conductive layer; the bigger area proportion of the bit line contact layer in the total bit lines is beneficial to improving the overall conductivity of the bit lines. The above two aspects are beneficial in reducing the resistance of the bit lines, thereby helping to improve the electrical performance of the semiconductor structure, and to improve the access speed of the semiconductor structures. In addition, the second protrusion is intertwined with the grooves, also is beneficial to contribute to the stability of the connection between the bit line contact layer and the conductive layer.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that, in each embodiment of the present application, many technical details are provided for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be realized.

Referring toFIG.1toFIG.3,FIG.2is a schematic cross-sectional structural diagram of a conductive layer in the semiconductor structure inFIG.1.FIG.3is a schematic cross-sectional structural diagram of a bit line contact layer in the semiconductor structure shown inFIG.1.

The semiconductor structure includes: a substrate100with word lines101arranged at intervals in the substrate100, and a trench between adjacent word lines101; a bit line contact layer112, the bottom surface of the bit line contact layer112is in contact with the bottom surface b of the trench, and the bit line contact layer112has a non-planar contact portion132in the direction away from the bottom surface b of the trench.

Wherein, the substrate100may include but not limited to a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, when the substrate100is a single crystal substrate or a polycrystalline substrate, it may also be an intrinsic silicon or a doped silicon substrate, further, an N-type polysilicon substrate or a P-type polysilicon substrate.

In some embodiments, the substrate100is doped, doped regions120and undoped regions110are formed on the substrate100, and the word lines101pass through the doped regions120. The doping ions may be phosphorous (P) ions, arsenic (As) ions, or boron (B) ions, or the like. In other embodiments, the substrate may also be doped in all regions.

In some embodiments, the word lines101include a metal layer111and a diffusion barrier layer121, and the diffusion barrier layer121is located in most of the peripheral regions of the metal layer111, which is beneficial to prevent the metal material in the metal layer111from diffusing into the adjacent structures of the word lines101. In addition, the top surfaces of the word lines101are covered with a gate insulating layer141, and the other periphery of the word lines101is surrounded by the gate oxide layer131. The diffusion barrier layer121can be used as an adhesive to attach the metal layer111and the gate oxide layer131better, and the gate oxide layer131and the gate insulating layer141are jointly used to achieve insulation between the word lines101and other structures in the substrate100. The material of the metal layer111may be at least one of metal materials such as tungsten, aluminum, copper or titanium, the material of the diffusion barrier layer121may be titanium nitride. The materials of the gate oxide layer131and the gate insulating layer141can be materials at least one of insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

In some embodiments, both the bit line contact layer112and the conductive layer122are integral parts of the bit lines102. The material of the bit line contact layer112may be polysilicon, and the material of the conductive layer122may be at least one of metal materials such as tungsten, aluminum, copper, or titanium.

In some embodiments, the non-planar contact portion132of the bit line contact layer112has a first protrusion142and at least one groove surrounded by the first protrusion142, and the conductive layer122is at a position corresponding to the groove a. There is a second protrusion152(seeFIG.2), and the second protrusion152is intertwined in the groove a.

Since the second protrusion152is intertwined in the groove a, on the one hand, the bottom surface and the side surface of the groove a are in contact with the second protrusion152, which increases the contact area between the bit line contact layer112and the conductive layer122. On the premise of ensuring that the bit lines102have a smaller structure dimension, it is beneficial to reduce the resistance of the bit lines102itself; on the other hand, the bit line contact layer112has a groove a, and the second protrusion152of the conductive layer122fills the groove a, which is beneficial to reduce the proportion of the bit line contact layer112in the bit lines102, thereby improving the overall conductivity of the bit lines102. The above two aspects are beneficial in reducing the resistance of the bit lines102by itself, thereby helping to improve the electrical performance of the semiconductor structure, and to improve the access speed of the semiconductor structure. In addition, the second protrusion152is intertwined in the groove a, which increases the total contact area between the bit line contact layer112and the conductive layer122, thereby helping to increase the distance between the bit line contact layer112and the conductive layer122. For example, the side surface of the groove a abuts the side surface of the second protrusion152, which hinders the relative sliding between the bit line contact layer112and the conductive layer122in the direction perpendicular to the side surface of the guide groove a, therefore improve the stability of the relative connection between the bit line contact layer112and the conductive layer122.

In some embodiments, the bottom surface of the conductive layer122is higher than the top surface of the word line101, and the same conductive layer122is in contact with at least two non-planar contact portions132.

It should be noted that, in general, the bit lines102are located above the word lines101, and the extension direction of the bit lines102is different from the extension direction of the word lines101. There is an insulating material between the bit lines102and the word lines101to realize isolation. InFIG.1, as an example, the bottom surface of the bit line contact layer112closest to the bottom surfaces of the trenches is lower than the top surface of the word lines101adjacent to the conductive layer122. When the conductive layer122is located above the word lines101, the bit line contact layer112is only located in the trenches between adjacent word lines101to avoid the situation where the bit line contact layer112touches the word lines101along the extension direction of the conductive layer122, wherein the extension direction of the conductive layer122is the same as the bit lines102extension direction. Therefore, the same conductive layer122is in contact with at least two non-planar contact portions132of the bit line contact layer112, that is, the same bit line102includes one conductive layer122and at least two parts of the bit line contact layer112.

In other embodiments, the bottom surface of the bit line contact layer closest to the bottom surfaces of the trenches can be not lower than the top surfaces of the word lines adjacent to the conductive layer, and the same conductive layer may be in contact with at least two top surfaces of the bit line contact layer. That is, the same bit line may also include one conductive layer and at least two bit line contact layers. In addition, when the bottom surface of the bit line contact layer closest to the bottom surfaces of the trenches is higher than the top surfaces of the word lines adjacent to the conductive layer, the bit line contact layer can be located not only in the trench between adjacent word lines, but also located above multiple word lines, the bit line contact layer and the conductive layer may have the same extension direction, that is, the same bit line may include a conductive layer and a bit line contact layer. In practical applications, the disclosure does not limit the relative height relationship between the bottom surface of the bit line contact layer closest to the bottom surfaces of the trenches and the top surface of the word line adjacent to the conductive layer.

In addition, it should be noted that inFIG.1, the side surfaces of the trenches comprise gate oxide layers131as one example, but in practical applications, the side surfaces of the trenches may also be directly on the substrate.

The semiconductor structure may further includes: a protective layer103located on the surfaces of the substrate100and the gate oxide layer131to prevent the surface of the substrate100from being exposed. In some embodiments, the top surface of the first protrusion142away from the bottom surface b of the trench is flush with the top surface of the protective layer103away from the substrate100. In other embodiments, the top surface of the first protrusion away from the bottom surface of the groove may also be flush with the surface of the substrate. It should be noted that, in practical applications, there is no limiting requirement regarding to the relative relationship between the top surface of the first protrusion away from the bottom surface of the groove and its adjacent structures. The material of the protective layer103may be at least one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

In some embodiments, referring toFIGS.4to8, there is one first protrusion142, and the orthographic projection of the first protrusions142on the substrate100(refer toFIG.1) is an axisymmetric figure.

Since the orthographic projection of the first protrusion142on the substrate100is an axisymmetric figure, the center axis of the first protrusion142can be coincident with the center axis of the cross section of the bit line102shown inFIG.1. If the non-planar contact portions132of the bit line contact layer112are evenly distributed, the grooves a made by the first protrusions142are evenly distributed in the non-planar contact portions132of the bit line contact layer112. In addition, the second protrusion152(refer toFIG.2) and the grooves a are intertwined with each other, so the central axis of the second protrusion152also coincides with the central axis of the grooves a. Under the stress on the bit lines102, there might be a relative sliding tendency between the bit line contact layer112and the conductive layer122. The attaching force between the second protrusion152and the first protrusion142is evenly distributed on the first protrusion142and the second protrusion152, preventing the deformation of the first protrusion142and the second protrusion152, therefore improving the stability of the connection between the bit line contact layer112and the conductive layer122.

The specific distribution of the first protrusions142and the grooves a in the non-planar contact portion132of the bit line contact layer112will be described below with reference toFIGS.4to8, as examples of the embodiment the application. Schematic diagrams of five cross-sectional structures of the first protrusion142with the grooves a in the middle. It should be noted that, in order to help viewing the protruding the first protrusions142and the grooves a, the first protrusions142are filled with patterns.

In some examples, referring toFIGS.4and5, the orthographic projection of the first protrusion142on the substrate100(refer toFIG.1) is annular inFIG.4, the orthographic projection of the first protrusion142on the substrate100is a ring, and the orthographic projection of the groove a on the substrate100is a circle; or, referring toFIG.5, the first protrusion142is in the orthographic projection of the substrate100is a rectangular ring, and the orthographic projection of the groove a on the substrate100is also a rectangle.

In other examples, referring toFIG.6, the orthographic projection of the first protrusions142on the substrate100(refer toFIG.1) is a cross, and the side surfaces of the trenches between the first protrusions142and the adjacent word lines101together form four grooves a.

In still other examples, referring toFIG.7, the figure enclosed by the orthographic projection of the outer edges of the first protrusion142on the base100(refer toFIG.1) is a rectangle, and the orthographic projection of the groove a on the base100enclosed by the first protrusion142is a circle.

In still other examples, referring toFIG.8, the figure enclosed by the orthographic projection of the outer edge of the first protrusion142on the substrate100(refer toFIG.1) is a circle, and the orthographic projection of the groove a on the substrate100has the shape of a rectangle.

It should be noted that, in practical applications, the embodiment of the present application does not limit the shape of the figure formed by the orthographic projection of the outer edge of the first protrusion on the base, and also does not limit shape of the groove formed by the first protrusion is on the base. In other embodiments, the orthographic projection of the first protrusion on the substrate may not be an axisymmetric figure. In addition, in the above example, the relative positions of the first protrusions and the grooves can be switched, as long as the second protrusions and the first protrusions in the conductive layer related to the grooves are intertwined with each other to form a bit line.

In other embodiments, referring toFIGS.9to12, the number of the first protrusions142is at least two, and the combined structure is composed of the two first protrusions142which has positive axisymmetric figure projection on the substrate100(refer toFIG.1). And the orthographic projection of the groove a on the substrate100is an axisymmetric figure.

Since the orthographic projection of the combined structure composed of at least two first protrusions142on the substrate100is an axisymmetric figure, it is beneficial to make the two first protrusions142evenly and symmetrically distributed in the non-planar contact portion132of the bit line contact layer112, and the orthographic projection of the groove a surrounded by at least two first protrusions142on the substrate100is an axisymmetric figure, that is, the groove a is also evenly distributed in the non-planar contact portion132of the bit line contact layer112. Therefore, the second protrusion152(refer toFIG.2) and the groove a are intertwined with each other. When the bit line102is affected by the stress, and the bit line contact layer112and the conductive layer122tend to slide to each other relatively, the attaching force between the second protrusion152with the first protrusions142is evenly distributed on the first protrusions142and the second protrusions152, preventing the deformation of the first protrusions142and the second protrusions152, thereby improving the stability of the connection between the bit line contact layer112and the conductive layer122.

The specific distribution of the at least two first protrusions142and the groove a in the non-planar contact portion132of the bit line contact layer112will be described below with reference toFIGS.9to12, which are the schematic diagrams of other four cross-sectional structures of the first protrusion142and the groove a in an embodiment of present application. It should be noted that, in order to visualize the first protrusions142and the grooves a, only the first protrusions142are filled with patterns.

In some examples, referring toFIGS.9and10, the non-planar contact portion132of the bit line contact layer112has two first protrusions142, and the orthographic projection of the groove a on the substrate100is a ring or a cross. InFIG.10, the orthographic projection of the first protrusion142at the outermost edge on the base100is a ring, the orthographic projection of the first protrusion142at the center on the base100is a circle, and the orthographic projection of the groove a on the base100is a circular ring; or, referring toFIG.9, the orthographic projection of the first protrusion142at the outermost edge on the base100is a square ring, and the orthographic projection of the first protrusion142at the center on the base100is a rectangle. The orthographic projection of the groove a on the substrate100is a square ring.

In other examples, referring toFIG.11, the non-planar contact portion132of the bit line contact layer112has four first protrusions142, and the orthographic projection on the substrate100of the groove a enclosed by the four first protrusions142is a cross.

In still other examples, referring toFIG.12, the non-planar contact portion132of the bit line contact layer112has six first protrusions142, and the first protrusions142are arranged in an array. The first protrusions142and trenches form grooves a together. InFIG.12, three first protrusions142are in a row, and six first protrusions142together form two rows. As an example, the orthographic projection of each first protrusion142on the substrate100is a circle. In a practical application, the number of rows and columns of the plurality of first protrusions, the number of first protrusions included in each row or each column, and the shape of the orthographic projection of the first protrusions on the substrate are not limited to the above description.

In addition, it should be noted that, in practical applications, the embodiments of the present application do not limit the shape of the orthographic projection of the combined structure composed of at least two first protrusions on the substrate. The shape of the orthographic projection of the grooves on the substrate is also not limited. In other embodiments, the orthographic projection of the combined structure composed of at least two first protrusions on the substrate may not be an axisymmetric figure. In addition, in the above example, the relative positions of the first protrusions and the grooves can be switched, as long as the second protrusions and the first protrusions in the conductive layer corresponding to the grooves are intertwined with each other to form a bit line.

In the above various embodiments, on the one hand, referring toFIG.1andFIG.13, in the direction perpendicular to the surface of the substrate100, the bottom surface of a single groove a may have at least two regions with different depths.

Since the bottom surface of a single groove a can have at least two regions with different depths, it is beneficial to further increase the total contact area where the second protrusion152(refer toFIG.2) that is intertwined with the groove a is in contact with the groove a. On the one hand, it is beneficial to reduce the contact resistance between the bit line contact layer112and the conductive layer122in order to reduce the resistance of the bit line102itself, thereby improving the electrical performance and access speed of the semiconductor structure. The attaching force between the line contact layer112and the conductive layer122avoids relative sliding between the bit line contact layer112and the conductive layer122, thereby improving the stability of the connection between the bit line contact layer112and the conductive layer122.

The specific shape of the bottom surface of a single groove a will be described below with reference toFIG.1,FIG.13andFIG.14.FIG.1,FIG.13andFIG.14show the three cross-sectional views of the specific shapes in the bottom surfaces of the single groove type in an embodiment of the application.

In some examples, continue to refer toFIG.1, the bottom surface of the groove a may be a concave surface recessed toward the substrate100. In this way, it is beneficial to further reduce the volume of the bit line contact layer112, thereby reducing the proportion of the bit line contact layer112in the bit line102, so as to improve the conductivity of the bit line102itself, thereby helping to improve the electrical performance of the semiconductor structure. and access speed.

In other examples, referring toFIG.13, the bottom surface of the groove a may be wavy. In this way, it is beneficial to further increase the total contact area where the second protrusion152(refer toFIG.2) is intertwined with the groove a is in contact with the groove a, thereby reducing the contact area between the bit line contact layer112and the conductive layer122, reducing the contact resistance of the bit line102itself, thereby improving the electrical performance and access speed of the semiconductor structure.

In still other embodiments, referring toFIG.14, the non-planar contact portion132(refer toFIG.3) is located in the trench, and the non-planar contact portion132has a convex surface that protrudes away from the bottom surface b of the trench. In this way, it is also beneficial to increase the total contact area where the bit line contact layer112is in contact with the conductive layer122, thereby reducing the contact resistance between the bit line contact layer112and the conductive layer122, thereby reducing the resistance of the bit line102itself, improving the electrical performance and access speed of semiconductor structures.

In other embodiments, the bottom surface of the groove may have be arranged to have the shape of stairs. Correspondingly, the second protrusions intertwined with the grooves are also stairs-like, this is beneficial in increasing the volume of the conductive layer and increasing the ratio of the conductive layer in the bit lines, thereby helping to reduce the resistance of the bit line itself, helping to improve the electrical performance and access speed of the semiconductor structure.

It should be noted that, with reference toFIG.3, as an example, inFIG.1,FIG.13andFIG.14, in the direction perpendicular to the sidewalls of the trenches, the first protrusion142has a part of the same width at the end away from the substrate100, but in practical applications, the width of the first protrusion may gradually decrease in the direction away from the substrate.

In the above various embodiments, on the other hand, referring toFIGS.15and16, the non-planar contact portion132(refer toFIG.3) may have at least two grooves a arranged at intervals. In this way, it is beneficial to further increase the attaching force between the bit line contact layer112and the conductive layer122, avoid the relative sliding between the bit line contact layer112and the conductive layer122, and thereby improve the stability of the connection relationship between the bit line contact layer112and the conductive layer122.

The specific arrangement of the depths of the at least two grooves a will be described below with reference toFIG.15andFIG.16.FIGS.15and16are the schematic diagram of the two cross-sectional structures of the specific arrangements of the depths of the at least two grooves a in an embodiment of the application.

In some examples, referring toFIG.15, the non-planar contact portion132may have four grooves a arranged at intervals, and in the direction Z perpendicular to the surface of the substrate100, the depths of each groove a are the same. It should be noted thatFIG.15has four grooves a as an example. In practical applications, the number of grooves a is not limited, and the arrangement of multiple grooves a is not limited.

In other examples, referring toFIG.16, the non-planar contact portion132may have four grooves a arranged at intervals, and in the direction Z perpendicular to the surface of the substrate100, the depths of the grooves a are different. In practical applications, some grooves may have the same depth, and some grooves may have different depths.

In addition, on the basis of the above embodiments, referring toFIGS.17and18, in the direction perpendicular to the surface of the substrate100, the bottom surface b of the trench may have at least two regions with different depths. In this way, it is beneficial to increase the contact area between the substrate100located under the bottom surface b of the trench and the bit line contact layer112, so as to reduce the contact resistance between the bit line contact layer112and the substrate100located under the bottom surface b of the trench. Therefore, it is beneficial to improve the electrical performance and access speed of the semiconductor structure.

The specific shape of the groove bottom surface b will be described below with reference toFIG.17andFIG.18.

In some examples, referring toFIG.17, the trench bottom surface b may be a convex surface raised toward the bit line contact layer112. Such a way is beneficial to further reduce the volume of the bit line contact layer112, so as to further reduce the proportion of the bit line contact layer112in the bit line102, so as to reduce the resistance of the bit line102itself, thereby improving the electrical performance and access speed of the semiconductor structure.

In other examples, referring toFIG.18, the bottom surface b of the groove may be wavy. In other examples, the bottom surface of the groove can also has a stepped shape.

It should be noted that, in practical applications, the substrate under the bottom surface of the trench may have third protrusions, wherein the third protrusions are related to the second protrusions of the conductive layer, that is, various types of protrusions configured in the second protrusions may apply to the third protrusion. In addition, the bit line contact layer in contact with the bottom surface of the trench may have a fourth protrusion at the end, wherein the fourth protrusion are related to the first protrusion, that is, various shapes included in the first protrusion can be applied to the fourth protrusion.

To sum up, the second protrusion152is intertwined in the groove a. On the one hand, in the plane perpendicular to the direction of the bit line contact layer112to the conductive layer122, it is ensured that the bit line contact layer112and the conductive layer122in the cross-sectional area on the plane is small, it is beneficial to increase the contact area between the bit line contact layer112and the conductive layer122, thereby reducing the resistance of the bit line102itself; on the other hand, the bit line contact layer112forms a concave groove a, and the second protrusion152of the conductive layer122fills the groove a, this is beneficial to reduce the ratio of the bit line contact layer112in the bit line102, thereby improving the overall conductivity of the bit line102. The above two aspects are useful in reducing the resistance of the bit line102itself, thereby helping to improve the electrical performance of the semiconductor structure, so as to improve the access speed of the semiconductor structure. In addition, the second protrusion152is intertwined in the groove a, which is beneficial to improve the stability of the connection between the bit line contact layer112and the conductive layer122.

Another embodiment of the present application further provides a method for fabricating a semiconductor structure, and the method can be used to fabricate the semiconductor structure provided in the above embodiment. The manufacturing method of the semiconductor structure provided by another embodiment of the present application will be described in detail below with reference to the accompanying drawings.

FIG.19toFIG.22are schematic cross-sectional structural diagrams corresponding to each step in a method for fabricating a semiconductor structure according to another embodiment of the present application.

Referring toFIG.19toFIG.22, the method for fabricating a semiconductor structure includes the following process steps:

Referring toFIG.19, providing a substrate100, and forming a plurality of word lines101at intervals in the substrate100; forming trenches c in the substrate100between adjacent word lines101.

In some embodiments, the substrate100includes a doped region120and an undoped region110; the word lines101includes a metal layer111and a diffusion barrier layer121; the top surfaces of the word lines101are disposed with a gate insulating layer141, the periphery areas of the word lines101are surrounded by the gate oxide layer131; the bit line contact layer112and the conductive layer122are both components of the bit line102(FIG.18); the protective layer103is formed on the surface above the doped region of the substrate and gate insulating layer141. The relevant details of the above-mentioned various structures are the same as those of the foregoing embodiments, and are not repeated here.

It should be noted that, inFIG.19, the substrate100can be etched to expose part of the sidewalls of the gate oxide layer131as an example (not shown). In practical applications, in the step of etching the substrate to form the trench, the sidewalls of the trench may also be the substrate.

InFIG.3andFIG.20toFIG.22, a bit line contact layer112is formed, the bottom surface of the bit line contact layer112is in contact with the trench bottom surface b, and the bit line contact layer112has a non-planar contact portion132in a direction away from the trench bottom surface b.

In some embodiments, forming the bit line contact layer112may include the following process steps:

Referring toFIG.20, forming an initial bit line contact layer162to fill the trench c (refer toFIG.19). Herein, when the surface of the substrate100has the protective layer103, the top surface of the initial bit line contact layer162away from the substrate100is flush with the top surface of the protective layer103away from the substrate100. In other embodiments, when the substrate surface is exposed, the top surface of the initial bit line contact layer away from the substrate may be flush with the substrate surface.

Referring toFIG.21, a mask layer104is formed on the surface of the substrate100and the surface of the initial bit line contact layer162. The mask layer104has one or more openings that expose at least part of the surface of the initial bit line contact layer162. It should be noted that the number of openings in the mask layer104may be one, or two, and the embodiment of the present application provides no limits to the orthographic projection of the openings of the mask layer104on the substrate100, and the shape and arrangement of the openings.

The material of the mask layer104includes at least one of hard mask materials such as silicon nitride, silicon oxide, or silicon oxynitride, and the method for forming the mask layer104includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc.

Referring toFIG.3andFIG.21toFIG.22in combination, the initial bit line contact layer162is etched by using the mask layer104to pattern the bit line contact layer112, and then the mask layer104is removed.

In some embodiments, the non-planar contact portion132has a first protrusion142and at least one groove a surrounded by the first protrusion142, and a subsequently formed conductive layer has second protrusion at a position related to the groove a, and the second protrusion is intertwined in the groove a. In some embodiments, the material of the initial bit line contact layer162is polysilicon, the method for etching the initial bit line contact layer162includes a dry etching process, and the etching gas includes carbon tetrafluoride and argon.

With the dry etching processing, in the direction Z perpendicular to the surface of the substrate100, the depth of the groove a gradually increases, and the etching gas first contacts the sidewalls of the groove a, then penetrates deeper to the bottom surface of the groove a contact, so that the probability of the etching gas contacting and reacting with the sidewalls of the groove a is greater than the probability of contacting and reacting with the bottom surface of the groove a, thereby facilitating the formation of the bottom surface of the groove recessed toward the bottom surface b of the groove.

The ratio of the gas flow rate of carbon tetrafluoride to the gas flow rate of argon is 3-6. For example, the ratio of the gas flow rate of carbon tetrafluoride to the gas flow rate of argon gas may be 5, which is beneficial to ensure that the formed bit line contact layer112has high dimensional accuracy, and at the same time, the rate of etching the substrate100is fast, Therefore, it is beneficial to improve the efficiency of forming the bit line contact layer112.

In some embodiments, the material of the mask layer104is silicon nitride, to remove the silicon nitride, hot phosphoric acid can be used. In other embodiments, the material of the mask layer104is silicon oxide, diluted hydrofluoric acid can be used, in a ratio of hydrofluoric acid to water1:300, for example, to remove silicon oxide.

In addition, in the direction Z perpendicular to the surface of the substrate100, the depth of the groove a is 3 nm˜7 nm. It should be noted that the depth of the groove a refers to the distance between the position where the groove a is closest to the bottom surface b of the trench and the top surface of the bit line contact layer112away from the substrate100. For example, the depth of the groove a maybe 5 nm, so as to ensure that the overall size of the subsequently formed bit line has an appropriate size.

In other embodiments, after the initial bit line contact layer is etched by using the mask layer as a mask to form the initial groove, the initial groove may also be etched again to form a bottom surface with a wavy shape and a stepped bottom surface or other shaped grooves.

In still other examples, after the trenches are formed and before the initial bit line contact layer is formed, the substrate exposed by the trenches may also be processed to form a substrate with a localized region protruding toward the opening of the trenches. For example, a first mask layer is formed on the bottom surface and sidewalls of the trench, and the first mask layer surrounds a through hole; a second mask layer is formed that fills the through hole; the second mask layer is used as a mask to etch the first mask layer to expose a part of the substrate; the part of the substrate is etched, and then the second mask layer is removed to form a substrate with a local area protruding toward the opening of the trench. Wherein, the material of the first mask layer and the material of the second mask layer are different, and the material of the first mask layer and the material of the second mask layer can both be one of silicon nitride, silicon oxide, monocrystalline silicon, polycrystalline silicon, or silicon oxynitride. It should be noted that the above description is only an exemplary illustration of how to form a substrate with a local area protruding toward the groove opening, and the embodiments of the present application do not limit the method for forming a substrate with a local area protruding toward the groove opening.

InFIG.1toFIG.3, a conductive layer122is formed, the conductive layer122is in contact with the non-planar contact portion132of the bit line contact layer112, the conductive layer122has a second protrusion152(seeFIG.2) at a position corresponding to the groove a, the second protrusion152is intertwined in the groove a.

The material of the conductive layer122may be at least one of the metal materials such as tungsten, aluminum, copper or titanium, and the bit line contact layer112and the conductive layer122are both components of the bit lines102.

To sum up, forming the bit line contact layer112having the first protrusion142and the groove a and the conductive layer122having the second protrusion152, herein the second protrusion152is intertwined in the groove a. In one aspect, in a plane perpendicular to the direction in which the bit line contact layer112points to the conductive layer122, it is beneficial to increase the contact area between the bit line contact layer112and the conductive layer122, while ensuring that the cross-sectional areas of the bit line contact layer112and the conductive layer122on the plane being small, thereby reducing the resistance of the bit line102itself. In another aspect, the bit line contact layer112has a groove a, and the second protrusion152of the conductive layer122filling the groove a, it is beneficial to reduce the proportion of the bit line contact layer112in the bit line102, thereby helping to improve the overall conductivity of the bit line102. The above two aspects are beneficial reducing the resistance of the bit line102itself, thereby helping to improve the electrical performance of the semiconductor structure, so as to improve the access speed of the semiconductor structure. In addition, the second protrusion152is intertwined in the groove a, which is beneficial to improve the stability of the connection between the bit line contact layer112and the conductive layer122.

Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific examples for realizing the present application, and in practical applications, various changes in form and details can be made without departing from the spirit and the scope of the present application. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subjected to the scope defined by the claims.