Patent ID: 12217796

DETAILED DESCRIPTION

As disclosed herein, a memory array may be used to implement a Bloom filter. The Bloom filter of the memory array may allow a read to be compared to many reference sequences or portions of reference sequences in parallel. The Bloom filter may provide an output indicating the read absolutely does not match the reference sequence or an output indicating the read may match the reference sequence. The possible matches may be compared to the read on a nucleotide-by-nucleotide basis or other technique to confirm which (if any) reference sequences the read matches. In some applications, the ability of the Bloom filter to compare the read to reference sequences in parallel and provide absolute negatives for matches (no match found) may reduce computation times for aligning reads to reference sequences, even when possible matches are further analyzed for confirmation of the match.

While memory devices have been traditionally seen as data storage devices that support computing devices, memories are increasingly being used as computing devices themselves. For example, memories have been configured to perform signed division and vector operations such as described in U.S. Pat. Nos. 9,741,399, 9,947,376, and 10,409,557, which are incorporated herein by reference for any purpose. In another example, memory arrays, such as resistive memory arrays, have been used to implement Bayesian networks for machine learning applications as described in U.S. patent application Ser. No. 17/006,602, which is incorporated herein by reference for any purpose. In some applications, utilizing memory arrays for certain computations may increase parallelization of the computations and/or reduce loads on a processor, a host system, and/or other computing device interacting with the memory.

FIG.1is a block diagram of an apparatus in the form of a computing system100including a memory device103in accordance with a number of embodiments of the present disclosure. As used herein, a memory device103, memory array110, and/or a host102, for example, might also be separately considered an apparatus.

In this example, the computing system100includes a host102coupled to memory device103via an interface104. The computing system100can be a personal laptop computer, a desktop computer, or an Internet-of-Things (IoT) enabled device, among various other types of computing devices and/or systems. In some examples, the system100may be in communication with or included in a system for genetic sequencing, such as a NGS system. In some examples, the host102may be included in a different device from the memory device103. For example, host102may be included in genetic sequencing system121and the memory device103may be included in a separate computing device in communication with the genetic sequencing system121. In some examples, the computing system100may be included in one or more computing devices in communication with the genetic sequencing system121(e.g., via host102). Host102may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing memory device103(e.g., via one or more memory controllers101). The computing system100may include separate integrated circuits, or both the host102and the memory device103may be on the same integrated circuit. For example, the host102may be a system controller of a memory system comprising multiple memory devices103, with the system controller providing access to the respective memory devices103by another processing resource such as a central processing unit (CPU).

For clarity, the computing system100has been simplified to focus on features with particular relevance to the present disclosure. The memory array110may be a dynamic random access memory (DRAM) array, synchronous DRAM (SDRAM) array, spin-transfer torque (STT) RAM array, phase change (PC) RAM array, thyristor RAM (TRAM) array, resistive RAM array, NAND flash array, NOR flash array, and/or 3D cross-point array, for instance. The array110may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as bit lines, digit lines or data lines).

Although the memory array110is shown as a single memory array, the memory array110may represent a plurality of memory arrays110, which in some examples may be arranged in banks BANK0-BANKN116-1,116-2of the memory device103as indicated by arrow120. Each bank116-1,116-2may include one or more memory arrays110. Or conversely, memory array110may be organized into one or more banks, where each bank BANK0-BANKN includes a region of the memory array110.

The memory device103includes address circuitry106to latch address signals provided over the interface104. The interface104may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data/address/command bus). Such protocol may be custom or proprietary, or the interface104may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCie), Gen-Z interconnect, cache coherent interconnect for accelerators (CCIX), or the like. Address signals are received and decoded by a row decoder108and a column decoder112to access the memory arrays110. Data may be read from memory arrays110by sensing voltage and/or current changes on the sense lines using sensing circuitry111. The sensing circuitry111may be coupled to the memory arrays110. Each memory array110and corresponding sensing circuitry111may constitute a bank of the memory device103in some examples. The sensing circuitry111may include, for example, sense amplifiers that may read and latch a page (e.g., row) of data from the memory array110. The I/O circuitry107may be used for bi-directional data communication with the host102over the interface104. The read/write circuitry113is used to write data to the memory arrays110or read data from the memory arrays110. As an example, the circuitry113may include various drivers, latch circuitry, etc.

Control circuitry105decodes signals provided by the host102. The signals may be commands provided by the host102. These signals may include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array110, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry105is responsible for executing instructions from the host102. The control circuitry105may comprise a state machine, a sequencer, and/or some other type of control circuitry, which may be implemented in the form of hardware, firmware, or software, or any combination thereof. In some examples, the host102may be a controller external to the memory device103. For example, the host102may be a memory controller which is coupled to a processing resource of a computing device, or alternatively host102may include one or more memory controllers101. Data may be provided to the memory array110and/or from the memory array via the data lines coupling the memory array110to the I/O circuitry107.

In various instances, the memory array110may be a resistive memory array. The resistive memory array may be a resistive programmable device. That is, the memory array110may be programmed by modifying the resistance of the memory cells of the memory array110. The memory cells may be programed to a specific resistance and/or conductance. The resistance/conductance of the memory cells may represent values that can be used in the performance of operations. For instance, the conductance of the memory cells can be used to perform a multiplication operation, among other types of operations.

In various examples, the resistance of the memory cells can be programmed to represent nucleotides of genetic sequences. For example, different resistances (e.g., resistance values) may represent A, C, G, T, and/or U. In some examples, resistance of the memory cells may be programmed to represent a “don't care” value. While reference is made to programming resistance values to memory cells, it is understood that programming resistance values results in programming corresponding conductance values to memory cells as conductance (G)=1/resistance (R). Accordingly, references to programming resistance values and conductance values may be used interchangeably herein.

In some examples, the memory cells may be programmed by providing appropriate voltages to the word lines and/or bit lines. In some examples, values to be programmed to the memory cells may be converted from digital signals to analog signals by digital-to-analog converters (DACs)114. In some examples, outputs from the memory array110may be converted to digital signals utilizing the analog-to-digital converters (ADCs)115. Although the DACs114and ADCs115are illustrated as being coupled directly to the memory array110, it some embodiments the DACs114and/or ADCs115may be coupled to the memory array110via the sensing circuitry111, the row decoder108, or the column decoder112. Further, although not shown inFIG.1, in some examples, some or all of the DACs114and/or ADCs115may be coupled between the memory array110and/or sense circuitry111and I/O circuitry107.

In some embodiments, the various components of the memory device103outside the memory array110, such as control circuitry105, row decoder108, and column decoder112may be shared by multiple memory arrays110and/or banks116. In other embodiments, memory device103may include multiple ones of various components for the memory arrays110and/or banks116. For example, in some embodiments, each bank116-1and116-2may be associated with different row decoders108and column decoders112.

According to embodiments of the present disclosure, the memory device103may be used to implement a Bloom filter. A Bloom filter compares a pattern to a dataset and provides a result indicating whether the dataset includes the pattern (e.g., there is a match). Results from Bloom filters do not include false negatives, but may provide false positives. That is, if the Bloom filter indicates the pattern is not located in the dataset (e.g., negative), the pattern is absolutely not located in the dataset. However, if the Bloom filter indicates one or more locations where the pattern is found in the dataset (e.g., positive), the data at those locations must be analyzed to confirm the positive result.

The memory array110may be used to store one or more genetic sequences. For example, different portions of a reference genetic sequence (e.g., reference sequence) may be stored in memory cells along each bit line of the memory array110. Each memory cell may be programmed with a resistance corresponding to the nucleotide at that location in the sequence. In some examples, each memory array110may store a different genetic sequence. In some examples, each bank116may store a different genetic sequence.

The memory array110may receive another genetic sequence, such as a read acquired from a sample. In some examples, each word line may be provided a voltage corresponding to a nucleotide at that location in the read. Utilizing the memory device103as a Bloom filter, the read may be compared to all of the sequences (or portions thereof) stored in one or more memory arrays110and/or banks116in parallel. The Bloom filter may indicate whether any of the portions of the sequence or sequences do not match and/or potentially match the read.

While the positive results of the Bloom filter may need confirmation (e.g., via additional analysis), the ability to definitively eliminate non-matches and compare the read to multiple portions of a reference sequence and/or multiple reference sequences in parallel may reduce the computation time required for determining where reads align.

FIG.2illustrates a portion of a memory array in accordance with a number of embodiments of the present disclosure. The memory array210includes memory cells233. The memory cells233are coupled to sense lines235and access lines236, organizing the memory cells233in columns and rows, respectively. In some examples, memory array210may be included in memory array110. Additional circuitry coupled to memory array210is also shown inFIG.2, such as sense circuitry211, DACs214, and ADC215. In some examples, sense circuitry211may be included in sense circuitry211, DACs214may be included in DACs114, and/or ADC215may be included in ADCs114.

In some examples, such as the one shown inFIG.2, the memory cells233may be resistive memory cells. The resistive memory cells233may include terminals that couple the memory cells233to the sense lines235and the access lines236. The terminals of the memory cells233may be coupled to each other via a resistive element234. The resistive element234may be a resistance variable material (e.g., a material programmable to multiple different resistance states, which may represent multiple different data states, such as different nucleotides) such as, for example, a transition metal oxide material, or a perovskite including two or more metals (e.g., transition metals, alkaline earth metals, and/or rare earth metals). Other examples of resistance variable materials that may be included in the storage element of resistive memory cells233may include various materials employing trapped charges to modify or alter conductivity, chalcogenides formed of various doped or undoped materials, binary metal oxide materials, colossal magnetoresistive materials, and/or various polymer based resistive variable materials, among others. Embodiments are not limited to a particular resistance variable material or materials. In various instances, the conductance of the memory cells233may be programmed by programming the resistive element234. For instance, control circuitry of a memory device can program the resistive element234. Actions performed by a memory device, the memory array210, the memory cells233sense circuitry211, DACs214, and/or ADCs215may be said to be performed by or caused by control circuitry of the memory device (e.g., control circuitry105).

As described herein, the memory array210and/or banks of the memory array210may be used to implement a Bloom filter. The memory array210, or a portion thereof, may generate a Bloom filter output responsive to receipt of an input. The output can be generated using the resistance of the memory cells233and the input to the memory array210. The resistive elements234can be programmed by providing inputs via the sense lines235and the access lines236. Bloom filter operations of the memory array210may be performed by providing inputs through one of the sense lines235or the access lines236.

In some examples, the inputs may be provided by sense lines235and/or the access lines236. The inputs may be voltage inputs. In some examples, the inputs may be provided by DACs214. The inputs provided by the DACs214may be based, at least in part, on control signals received from control circuitry (e.g., control circuitry105) and/or signals provided from I/O circuitry (e.g., I/O circuitry107).

In some examples, the outputs may be provided via the sense lines235or the access lines236. In some examples, the outputs can be interpreted as current signals by the sense circuitry211. The outputs can be provided to the ADCs215. In some examples, the sense circuitry211may receive a current from each access line236and output a voltage, but in other examples, the sense circuitry211may provide a current for each access line236to the ADCs215. In these examples, the ADCs215may receive a current and can output a voltage corresponding to each access line236and provide a corresponding output (e.g., a voltage). In some examples, the output from the ADCs215may be stored in registers (not shown) of a memory device (e.g., memory device103), another array of the memory device, provided to control circuitry of the memory device, and/or provided to I/O circuitry of the memory device. In some examples, the outputs and/or data based on the outputs may be provided to a device external to the memory device, such as host102.

Although the memory cells233are depicted as resistive memory cells with resistive elements234, the present disclosure is not limited to this particular type of memory cell. For example, DRAM transistor memory cells operated in a sub-voltage threshold regime may be used.

FIG.3illustrates a portion of a memory array in accordance with a number of embodiments of the present disclosure. The memory array310includes memory cells333. The memory cells333are coupled to sense lines335and access lines336. In some examples, memory array310may be included in memory array110and/or memory array210.

In some embodiments, to implement a Bloom filter, the memory array310may act as a multiply-accumulator (MAC). A resistive element334of each memory cell333may be programmed to have a desired resistance (R). As used herein, the terms resistance and resistance values are used interchangeably. Voltage (V) inputs may be provided along each access line336. As used herein, the terms voltage and voltage values are used interchangeably. The resulting current through each memory cell333due to the application of the voltage inputs is provided to a sense line335, which may provide a current output. The voltage inputs may be provided by DACs, such as DACs114and/or214in some examples. The current output may be provided to sense circuitry such as sense circuitry111and211in some examples.

In the example shown inFIG.3, a voltage V1is provided along access line336A to a memory cell333A having a conductance G1and a voltage V2is provided along access line336B to a memory cell333B having a conductance G2. As is understood in the art, the conductance of the memory cells333may be based on the resistance of resistive elements334. The resulting current I1through memory cell333A is equal to V1*G1. Current I1is provided to sense line335. The resulting current I2through memory cell333B is equal to V2*G2is also provided to sense line335. The total current I on sense line335is the sum of I1and I2. Thus, the total current is the sum of the multiplication operations at each of the memory cells333along the sense line335to implement the multiply-accumulate operation:
I=I1+I2=(V1×G1)+(V2×G2)  Equation 1

Thus, the total current for a sense line335is a sum of all the products of the voltage values along the access lines336and the conductance values of the memory cells333along the corresponding sense line335. As is understood in the art, if the states of the memory cells333are represented as resistance (R), where G=1/R, the total current I would be the sum of division operations:
I=I1+I2=(V1÷R1)+(V2÷R2)  Equation 2

Although only one sense line335and two memory cells333are shown inFIG.3, the voltage inputs along access lines336may be provided to memory cells along multiple sense lines simultaneously, or near simultaneously. Multiple sense lines may provide outputs simultaneously or near simultaneously. Thus, multiple multiply-accumulate operations may be performed in parallel in the memory array310.

According to embodiments of the present disclosure, the resistance levels and voltage levels can represent data, such as data that corresponds to a nucleotide of a genetic sequence. For example, each nucleotide type A, C, G, T, and/or U may correspond to a different level (e.g., value) of resistance (e.g., conductance) and/or voltage. A genetic sequence may be stored in one or more memory cells333along a sense line335of the memory array, and another genetic sequence may be provided as an inputs along access lines336. The stored genetic sequence may be stored as a set of resistances, and the input genetic sequence may be provided as a set of voltages. This may result in a current output along sense line335. The resulting current may be used to determine whether the input genetic sequence possibly matches the genetic sequence stored in the memory cells333stored along sense line335.

FIG.4illustrates an example of a multiply-accumulate operation for a genetic sequence in accordance with a number of embodiments of the present disclosure. Genetic sequence440includes multiple nucleotides444. In this example, genetic sequence440is a DNA sequence that includes nucleotides A, C, G, and T, but in other examples, genetic sequence440may be an RNA sequence or other genetic sequence. Each nucleotide type is assigned a different resistance/conductance value and a different voltage value compared to the other nucleotide types. In the simple example shown inFIG.4, each nucleotide type is assigned a same value for both resistance/conductance and voltage as shown in legend442. In other examples, each nucleotide type may be assigned different values for resistance and voltage. Further, although values 1, 2, 3, and 4 are used in the present example, other values may be used in other examples. For example, prime numbers (e.g., 1, 3, 5, and 7) may be used.

The genetic sequence440is multiplied with itself on a nucleotide-by-nucleotide basis. In the example shown inFIG.4, the multiplication operations are G×G (3×3), AxA (1×1), T×T (4×4), T×T (4×4), A×A (1×1), C×C (2×2), and A×A (1×1). The voltage assigned to each nucleotide444of sequence440is multiplied with the conductance assigned to the corresponding nucleotide444of sequence440to provide a resulting current value446for each nucleotide444. The resulting currents for all of the nucleotides444in the sequence440are then summed (e.g., accumulated) to provide a total current448. The total current in the example shown inFIG.4is 48 (e.g., uAmp, mAmp, etc.).

The resulting total current448indicates an expected total current (e.g., target value) from a multiply-accumulate operation when an input genetic sequence matches a genetic sequence stored along a sense line (e.g., sense line235,335) of a memory array (e.g., memory array110,210,310). When the resulting current of a sense line does not match the target value for an input genetic sequence, the genetic sequence stored along the sense line may be definitively determined not to be a match of the input sequence. When the resulting current of the sense line does match the expected resulting current for the input sequence, it indicates a potential match. The input sequence provided to the memory array and the genetic sequence stored along the sense line of the memory array may be compared by another technique to confirm the match. Thus, a memory array performing multiply-accumulation operations may act as a Bloom filter.

FIG.5illustrates an example of storing a reference sequence in a memory array in accordance with a number of embodiments of the present disclosure. The memory array510may be included in memory array110,210, and/or310in some embodiments. The memory array510may include memory cells533along sense lines535and access lines536. Memory cells533may be implemented by memory cells233and/or333in some examples. Sense lines535may be implemented by sense lines235and/or335in some examples. Access lines536may be implemented by access lines236and/or336in some examples. While for illustration, memory array510is shown including seven access lines536, it is understood that memory array510may include any number of access lines536. Furthermore, although only four sense lines535are shown inFIG.5, memory array510may include any number of sense lines535. While each memory cell533may include a resistive element (e.g., resistive element234and/or334) or other element capable of performing a multiply-accumulate operation, for ease of illustration, the memory cells533are illustrated as blocks with letters indicating the nucleotide stored in the memory cell533(e.g., based on a resistance programmed in the memory cell533).

A reference sequence550may be provided to the memory array510(e.g., via control circuitry105and/or I/O circuitry107) for storage in the memory array510. A portion of the reference sequence550may be stored along each sense line535. In some examples, a sliding window501having a length of the sense line535may be progressed along the reference sequence550, and each sense line535may store the portion of the reference sequence550located within the sliding window501at a particular position in the progression. In some examples, such as the one shown inFIG.5, the sliding window501may be progressed one nucleotide at a time, and the portion of the reference sequence550stored in a sense line535may be shifted by one nucleotide compared to the adjacent sense line535. However, the sliding window501may be progressed by more than one nucleotide in other examples.

In some examples, the sliding window501may be progressed until the end of the reference sequence550. If the reference sequence550is long enough such that the memory array510“runs out” of sense lines535to store portions of the reference sequence550, the remaining portions of the reference sequence550may be stored in another memory array. In some examples, the remaining portions may be stored in a memory array of a same bank as memory array510. In some examples, the remaining portions may be stored in a memory array of a different bank as memory array510.

While one reference sequence550is shown inFIG.5, in some examples, multiple reference sequences may be stored in memory array510. In some examples, different reference sequences may be stored in different memory arrays of a bank including memory array510. In some examples, different banks may store different reference sequences. In some examples, how the reference sequence550is divided into portions, stored, and/or shifted in the memory array510(or across multiple memory arrays) is performed based on control signals provided by control circuitry, such as control circuitry105. In some examples, the control signals may be based, at least in part, on instructions/commands provided by a host, such as host102.

In some embodiments, once the reference sequence550is stored in memory array510based, at least in part, on resistance values of the memory cells533, reads may be provided to memory array510for comparison to the reference sequence550.

FIG.6illustrates an example of comparing reads to reference sequences stored in the memory array shown inFIG.5in accordance with a number of embodiments of the present disclosure. In some examples, read652may be provided as voltages along access lines536(e.g., via DACs114,214). For ease of illustration, rather than voltage levels along the access lines536, read652is illustrated as blocks with letters indicating the nucleotide represented by the voltage level. In some examples, data indicating the voltages to be provided for the read652may be stored in a register of the memory device including memory array510. In some examples, the data indicating the voltages to be provided for the read652may be provided in a different memory array and/or memory bank of the memory device. In some examples, the data indicating the voltages to be provided for the read652may be provided by control circuitry and/or I/O circuitry of the memory device (e.g., control circuitry105and I/O circuitry107).

In some examples, the read652may be the same length as the portions of the reference sequence550stored along each sense line535. In some examples, the length of the portions of the reference sequence550stored along each sense line535(e.g., the length of the sliding window) may be based, at least in part, on an expected shortest read generated by a sequencing system. In some examples, read652may be “padded” by values for voltages that indicate a “don't care” and/or that will not affect the results of the multiply-accumulate operation.

The read652may be provided to all of the portions of the reference sequence550along each of the sense lines535simultaneously or near simultaneously. The voltage corresponding to the nucleotide along each access line536may pass through the corresponding memory cells533of the access line536, generating a current. The current may be based on the voltage provided to the access line536and the resistance/conductance value programmed to each memory cell533. The current through each memory cell533may be provided to the corresponding sense line536. The currents along the sense line536may be summed, thus a multiply-accumulate operation may be performed along each sense line536. The sum of the currents of the memory cells533may be provided from the sense lines536to sense circuitry (e.g., sense circuitry111,211). In some examples, the sense circuitry may provide current outputs for analysis. In some examples, the sense circuitry may provide the sensed currents to ADCs (e.g., ADCs115,215) that may convert the currents into digital signals representing the currents as an output.

For ease of illustration, the outputs656associated with each of the sense lines536are illustrated as boxes with numerical values reflecting the result of the multiply-accumulate operations of the read652with the portions of the reference sequence550based on the values provided in legend442. As described with reference toFIG.4, the target value654(e.g., expected value) of the read652multiplied and summed against itself is 48. Several outputs656have values that are not equal to 48. These outputs are true negatives658. In some embodiments, there may be no mechanism for the MAC of the Bloom filter as disclosed herein to provide a false negative. Accordingly, the portions of the reference sequence550stored along sense lines535associated with the true negatives658may be ignored or discarded as potential matches for the read652.

While there may not be false negatives, there may be multiple combinations of conductance and voltage values that when multiplied and summed equal 48, which may lead to false positives. True positive660output correctly indicates a portion of the reference sequence550of a sense line535matches the read sequence652. However, false positive662also equals 48, even though the portion of the reference sequence550stored along the associated sense line535does not match read sequence652. Accordingly, outputs656that match the target value654may be further analyzed prior to confirming a potential alignment location of the read652in the reference sequence550. In some examples, the portions of the reference sequence550stored along the sense lines535having positive results (e.g., outputs656match the target value654) may be compared to the read652on a nucleotide-by-nucleotide basis. In some examples, other comparison techniques may be used. In some examples, this additional analysis may be performed on the memory device, such as by pattern matching circuitry, which may include a content addressable memory and/or one or more comparator circuits. In some examples, the portions of the reference sequence550and the read652may be provided to an external device, such as host102, which may perform the additional analysis. This additional analysis may filter out false positive662and retain true positive660.

Once confirmed, the true positive660indicates that the read sequence652may align to the reference sequence550at the location of the reference sequence550along the corresponding sense line535. Because it is known which portion of the reference sequence550is stored along each sense line535, it can be determined where in the reference sequence550read652may be aligned to. In some examples, such as when the memory confirms the true positive660, the memory may provide an output indicating a location in the reference sequence550that the read652aligns to (e.g., alignment location). The output may be stored in a register or memory array of the memory device, such as memory device103. In some examples, the output may be provided to an external device, such as host102. In other examples, such as when the external device performs the additional analysis, the alignment location may be provided to the memory device or another memory device for storage and/or used in further processing for recombining all of the analyzed reads into a longer sequence (e.g., a sequence of the sample from which the reads were acquired).

While positive results660,662may require additional computation time to confirm, the ability of the Bloom filter implemented by memory array510to compare the read652to many portions of the reference sequence550in parallel and definitively eliminate portions that are not matches, the overall computation time for aligning the read652to the reference sequence550(or determining the read652does not align to the reference sequence550when there are no matches) may be less.

While read652is shown as being compared against multiple portions of a reference sequence500in parallel in a single memory array510inFIG.6, in some examples, read652may be provided in parallel to multiple memory arrays and/or banks of memory arrays in parallel. Each memory array and/or bank may include one or more reference sequences. In some examples, reads may be provided to the memory device in series (e.g., one read at a time is compared to the reference sequence(s) in the memory array(s)). However, in some examples, multiple reads may be compared to reference sequences in parallel. For example, different reads may be provided to different memory arrays and/or banks in parallel.

As described with reference toFIG.6, any output656that does not match the target value654is discarded or ignored. However, a genomic sample from which reads are obtained does not typically have a sequence that exactly matches a reference sequence, even if the genomic sample is a same organism. For example, mutations may cause changes in the sequence between the sample and the original organism from which the reference sequence was obtained (e.g., alpha, beta, delta, and omicron variants and sub-variants thereof for COVID-19). Additionally, the process of obtaining reads from the sample is not perfect. Some reads may include one or more of a mismatched nucleotide (e.g., a transcription error), a deletion of a nucleotide and/or an insertion of a nucleotide.

In some applications, if only outputs656that exactly match the target value654are retained/further analyzed, the Bloom filter may not tolerate mutations or read errors. This may lead to an unacceptable number of reads marked as not aligning to the reference sequence. To increase error tolerance, in some embodiments, true negatives658with values within a range of the target value654may be retained/further analyzed. For example, true negatives658having a value within +/−2 of the target value654(e.g., between 46 and 50) may also be analyzed as a possible “close match.” Further analysis performed by the memory and/or host may determine whether the close matches are false close matches or “true” close matches due to a mutation and/or read error. The width of the range may be based, at least in part, on a length of the read652and/or a desired error tolerance. Increasing the error tolerance in some cases may increase computation time as it may lead to additional portions of the reference sequence550requiring additional analysis (e.g., nucleotide-by-nucleotide comparison and/or additional processing to determine error/mutation type).

In some applications, particularly when the Bloom filter is implemented by analog components, some margin of error around the target value654may be provided for outputs656that are analyzed as potential positives. For example, variations in resistances of memory cells533and/or sense circuitry may cause variations in the results of the multiply-accumulate operation. The variations may be due to processing variations, temperature, atomic/ion migration in components, and/or other factors. The margin of error may be based, at least in part, on material properties of the memory, operational properties of the memory, environmental factors, or a combination thereof.

FIG.7is a flowchart of a method in accordance with a number of embodiments of the present disclosure. In some examples, the method700may be performed at least in part by a computing system such computing system100shown inFIG.1. In some examples, the method700may be performed at least in part by a memory array, such as memory array110,210,310, and/or510.

At block702, “programming a plurality of resistance values to a plurality of memory cells” may be performed. In some examples, the plurality of resistance values may correspond to nucleotide types (e.g., A, C, G, T, and U). In some examples, the programming may be performed, at least in part, by control circuitry, such as control circuitry105. In some examples, programming of the plurality of resistance values may be based, at least in part, on a first genetic sequence. In some examples, the first genetic sequence may be a reference sequence.

At block704, “providing a plurality of voltage values to a plurality of access lines coupled to the plurality of memory cells.” In some examples, the plurality of voltage values correspond to the nucleotide types. In some examples, the plurality of voltage values may be based, at least in part on a second genetic sequence. In some examples, the second genetic sequence may be a read sequence. In some examples, the voltage values may be provided by one or more DAC, such as DAC114,214. In some examples, the DAC may provide the input responsive to signals received from the control circuitry. In examples including a DAC, providing the plurality of voltage values may include converting a digital input into the plurality of voltage values.

At block706“summing a plurality of currents along corresponding ones of a plurality of sense lines coupled to the plurality of memory cells” may be performed. In some examples, the plurality of currents may be functions of the plurality of voltage values and corresponding ones of the plurality of resistance values of the plurality of memory cells along corresponding ones of the plurality of sense lines, as described with reference toFIG.3and Equations 1-2.

At block708, “providing a plurality of outputs based, at least in part, on the summing” may be performed. In some examples, the outputs may be provided from the sense lines to sense circuitry, such as sense circuitry111,211. In some examples, the outputs may be provided from the sense circuitry to an ADC, such as ADC115,215. In some examples, the outputs may be provided from the ADC. In these examples, providing the plurality of outputs may include converting the summed plurality of currents from an analog signal to a digital signal. In some examples, method700may further include storing the outputs, such as in a register or a memory array of the memory device.

At block710, “comparing the plurality of outputs to a target value” may be performed. In some examples, the comparing may be performed by a memory device, such as memory device103. In some examples, the comparing may be performed by a host, such as host102. In some examples, the results of the comparing may be stored, such as in the memory device or another device.

In some embodiments, method700may further include “determining, based on the comparing, whether at least a portion of a first genetic sequence corresponding to the plurality of resistance values programmed in the plurality of memory cells matches a second genetic sequence corresponding to the plurality of voltage values” as indicated by block712. In some examples, a potential match may be determined when at least one of the plurality of outputs matches the target value. In some examples, a potential match may be determined when at least one of the plurality of outputs is within a range of the target value. As discussed previously, a range may be used to increase tolerance for mutations and errors in the reads in some applications

FIG.8is a flowchart of a method in accordance with a number of embodiments of the present disclosure. In some examples, the method800may be performed at least in part by a computing system such computing system100shown inFIG.1. In some examples, the method800may be performed at least in part by a memory array, such as memory array110,210,310, and/or510.

At block802, “assigning each of a plurality of nucleotide types one of a plurality of conductance values” may be performed.

At block804, “assigning each of the plurality of nucleotide types one of a plurality of voltage values” may be performed.

At block806, “multiplying a conductance value and a voltage value corresponding to a nucleotide type for each of a plurality of nucleotides of a first genetic sequence to generate a plurality of products” may be performed.

At block808, “summing the plurality of products to generate a target value corresponding to the first genetic sequence” may be performed. An example of performing blocks802-808is shown and described in reference toFIG.4.

At block810, “comparing at least one output of a Bloom filter to the target value” may be performed. For example, as shown and described with reference toFIG.6. In some examples, when the at least one output of the Bloom filter is equal to the target value, method800may further include comparing the first genetic sequence to a second genetic sequence corresponding to the at least one output on a nucleotide-by-nucleotide basis. The comparing may be performed by a memory device, such as memory device103and/or a host, such as host102. In some examples, when the at least one output of the Bloom filter is not equal to the target value, the at least one output may be ignored or discarded.

In some examples, the Bloom filter is configured to store at least one reference sequence. In some examples, the at least one reference sequence includes a genetic sequence of a virus or a bacterium. In some examples, the first genetic sequence corresponds to a read sequence acquired from a biological sample. In some examples, blocks806,808, and810may be repeated for each of a plurality of genetic sequences (e.g. multiple read sequences).

At block812, based on the comparing “determining whether the Bloom filter includes a match to the first genetic sequence” may be performed.

As indicated by block814, in some examples, method800may further include “providing an input corresponding to the first genetic sequence to the Bloom filter.” In some examples, the at least one output is based, at least in part, on the input.

In some examples, the Bloom filter is implemented by a memory array configured to store a second genetic sequence in a plurality of memory cells. In some of these examples, method800may further include programming a plurality of resistive elements of the plurality of memory cells with the plurality of conductance values corresponding to the second genetic sequence. In some of these examples, method800may further include storing a plurality of portions of the second genetic sequence along corresponding ones of a plurality of sense lines of the memory array. In some examples each of the plurality of sense lines includes a portion of the second genetic sequence shifted by at least one nucleotide. For example, as indicated by sliding window501shown inFIG.5.

Although the examples herein describe storing one or more reference sequences in memory and providing reads to the memory for comparison, reads may also be stored in the memory. For example, one or more reads may be stored in a memory array, and one or more reference sequences (or portions thereof) may be provided for comparison to the reads in the memory array. Thus, instead of a read being compared to multiple portions of a reference sequence, multiple reference sequences, and/or a combination thereof in parallel, a reference sequence may be compared to multiple reads in parallel. Further, instead of different reads being provided in series, different reference sequences, permutations of the reference sequence, and/or portions thereof may be provided in series.

While the examples herein refer to determining “correct” locations of reads and/or alignment locations of reads for a reference sequence based on confirmed positive outputs of the Bloom filter, the locations within the reference sequence determined from the Bloom filter may be candidate locations (may also be referred to as estimated or potential locations) locations for the reads. Genomic sequences may include regions where patterns of nucleotides are repeated. Thus, there may be several perfect and/or close matches for locations in the reference sequence where a read may be aligned. The chance of multiple candidate locations increases as the length of the read decreases and/or the length of the reference sequence increases.

After positive results have been confirmed, the memory device, host, and/or other device may perform additional processing to “narrow down” the potential alignment locations of reads provided by the Bloom filter when there are multiple potential alignment locations. In some applications, this may be based on one or more probabilistic methods known in the art of genetic sequencing. However, by using parallel processing capabilities of memory arrays, such as resistive memory arrays, as disclosed herein, the overall computing time for aligning reads to reference sequences may be reduced.

Certain details set forth herein provide a sufficient understanding of examples of the disclosure. However, it will be clear to one having skill in the art that examples of the disclosure may be practiced without these particular details. Moreover, the particular examples of the present disclosure described herein should not be construed to limit the scope of the disclosure to these particular examples. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the disclosure. Additionally, terms such as “couples” and “coupled” mean that two components may be directly or indirectly electrically coupled. Indirectly coupled may imply that two components are coupled through one or more intermediate components.

From the foregoing it will be appreciated that, although specific embodiments of the disclosure have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Accordingly, the scope disclosure should not be limited any of the specific embodiments described herein.