Patent ID: 12244302

DESCRIPTION OF EMBODIMENTS

Hereinafter, a semiconductor device according to the present invention is described based on an embodiment illustrated in drawings. The respective drawings are schematic drawings, and do not always strictly reflect actual sizes of constitutional elements.

Embodiment 1

1. Configuration of Power Conversion Circuit1According to Embodiment 1

First, a power conversion circuit1of the embodiment 1 is described. A bootstrap field effect transistor (FET) (a semiconductor device100according to the embodiment 1) that forms a semiconductor device of the present invention is mounted on the power conversion circuit1.FIG.1is a circuit diagram for describing the power conversion circuit according to the embodiment 1. The power conversion circuit1according to the embodiment 1 includes, as illustrated inFIG.1, a high-side switch Q1, a low-side switch Q2, a capacitor22, and a gate driver IC10.

The high-side switch Q1is connected to a direct current input power source Vin. One end of the low-side switch Q2is connected to the high-side switch Q1, and the other end of the low-side switch Q2is connected to a reference potential. A suitable switch element can be used as the high-side switch Q1and the low-side switch Q2. In the embodiment 1, a metal-oxide-semiconductor field-effect transistor (MOSFET) is used.

The high-side switch Q1and the low-side switch Q2form a part of a main circuit C1that forms a first circuit, and an output terminal OUT is connected to a node N between the high-side switch Q1and the low-side switch Q2. The main circuit C1is connected to the direct current input power source Vin (first power source).

One electrode of the capacitor22is connected to the node N between the high-side switch Q1and the low-side switch Q2, and the other electrode of the capacitor22is connected to a high-side drive circuit11of the gate driver IC10. The capacitor22is mounted as a part externally mounted the gate driver IC10.

The gate driver IC10includes the high-side drive circuit11, a low-side drive circuit12, the bootstrap FET (the semiconductor device100according to the embodiment 1), and a plurality of terminals (a terminal Vb, a terminal Vs, a terminal HO, a terminal LO, and a terminal GND).

The high-side drive circuit11controls turning on and off of the high-side switch Q1. The high-side drive circuit11is connected to the node N between the high-side switch Q1and the low-side switch Q2via the Vs terminal. The high-side drive circuit11is connected to the bootstrap FET (the semiconductor device100according to the embodiment 1), and is connected to the capacitor22via the Vb terminal. The high-side drive circuit11is connected to a gate electrode of the high-side switch Q1via the output terminal HO.

The low-side drive circuit12controls turning on and off of the low-side switch Q2. The low-side drive circuit12forms a part of the second circuit C2, is connected to a drive-use power source Vcc (second power source), is connected to the ground potential via a GND terminal, and is connected to a gate electrode of the low-side switch Q2via the output terminal LO. A second power source voltage that is an output voltage of the drive-use power source Vcc (second power source) is lower than a first power source voltage that is an output voltage of the direct current input power source Vin (first power source).

One electrode of the bootstrap FET (the semiconductor device100according to the embodiment 1) is connected to the low-side drive circuit12and the drive-use power source Vcc, and the other electrode of the bootstrap FET is connected to the capacitor22and the high-side drive circuit11. A gate electrode of the bootstrap FET (the semiconductor device100according to the embodiment 1) is connected to an electrode (one electrode) on a drive-use power source Vcc side, and a back gate BG of the bootstrap FET is connected to a reference potential. The bootstrap FET (the semiconductor device100according to the embodiment 1) and the capacitor22form a bootstrap circuit20.

As the bootstrap FET of the present invention, a field effect transistor can be used. However, in this embodiment, to incorporate the bootstrap FET in the gate driver IC10, the semiconductor device100according to the embodiment 1 is used where the high-side drive circuit11and the low-side drive circuit12are provided to the same semiconductor base body10of the semiconductor device100.

2. Configuration of Semiconductor Device100According to Embodiment 1

FIG.2is a cross-sectional view illustrating the semiconductor device100according to the embodiment 1. As illustrated inFIG.2, the semiconductor device100according to the embodiment 1 includes, a semiconductor base body110, a first electrode120, a first field plate122, a second electrode130, an isolation film140, insulation films150,152, a third electrode160, a second field plate162, a connecting portion164, and a fourth electrode170. Although not illustrated in the drawing, at least parts of the high-side drive circuit11and the low-side drive circuit12are provided to the semiconductor base body110. The semiconductor device100according to the embodiment 1 is incorporated in the gate driver IC10.

The semiconductor base body110is made of a predetermined semiconductor material. Over a whole area of a lower side portion of the semiconductor base body110, a p-type (p−-type) substrate111is formed. An n-type (n−-type) first semiconductor layer112is formed over the substrate111in a predetermined region. A p-type (p−-type) back gate region113is formed over the substrate111in a region disposed adjacently to the first semiconductor layer112. A boundary where the first semiconductor layer112and the back gate region113are disposed adjacently to each other is located at a position that faces the third electrode160described later in a state where the insulation film150formed over a surface of the semiconductor base body110is sandwiched between the boundary and the third electrode160. A part of the back gate region113is formed in a region that faces the third electrode160by way of an insulation film150.

The back gate region113has the same composition as the substrate111, and is continuously formed with the substrate111. The back gate region113is formed with a depth that allows the back gate region113to extend from the surface of the semiconductor base body110and reach the substrate111. A dopant concentration of the substrate111and the back gate region113falls within a range of 1×1010cm−3to 1×1015cm−3. Such a dopant concentration is low compared to a dopant concentration of a back gate region in general.

In the region where the first semiconductor layer112is formed, an n-type (n+-type) first contact region CR1is formed over a portion of a surface of the first semiconductor layer112in the region on a side opposite to a back gate region113side. In other words, the first contact region CR1is formed over the surface of the first semiconductor layer112on the side opposite to the back gate region113side with the isolation film140, described later, interposed between the first contact region CR1and the back gate region113. A dopant concentration of the first contact region CR1is set higher than a dopant concentration of the first semiconductor layer112.

In the region where the back gate region113is formed, an n-type (n+-type) second contact region CR2is formed over a portion of a surface of the back gate region113. A p-type (p+-type) third contact region CR3is formed over a portion of a surface of the back gate region113at a position remoter from the first semiconductor layer112than the second contact region CR2and spaced apart from the second contact region CR2. A dopant concentration of the second contact region CR2is set higher than a dopant concentration of the first semiconductor layer112, and a dopant concentration of the third contact region CR3is set higher than a dopant concentration of the substrate111.

The isolation film140is formed over the surface of the first semiconductor layer112at the center of the first semiconductor layer112. The insulation film152is formed over a surface of the semiconductor base body110(the first semiconductor layer112) on a side opposite to the back gate region113with respect to the isolation film140. The insulation film150is formed over the surface of the semiconductor base body110(the first semiconductor layer112and the back gate region113) on the back gate region113side with respect to the isolation film140. The isolation film140is a LOCOS film made of SiO2, and is embedded in the semiconductor base body110by an approximately half of a thickness of the isolation film140. The isolation film140, the substrate111of the semiconductor base body110and the first semiconductor layer112cooperatively form a reduced surface field (RESURF) structure. The insulation films150,152are each formed of a thermal oxidation film.

The first electrode120is disposed at a position over the semiconductor base body110, and on a side opposite to a side where the back gate region113is formed with respect to the isolation film140. The first electrode120is brought into contact with the first contact region CR1of the semiconductor base body110via an opening formed in the insulation film152. The first electrode120is connected to the high-side drive circuit11and the capacitor22, and is electrically connected to a main circuit C1via the capacitor22(seeFIG.1). The first electrode120is made of metal (for example, aluminum).

The first field plate122is formed so as to cover the insulation film152and the isolation film140ranging from the surface of the insulation film152to the surface of the isolation film140. The first field plate122is connected to the first electrode120. In the embodiment 1, the first field plate122is made of polysilicon. However, the first field plate122may be made of metal (for example, aluminum) or silicide (for example, metal silicide such as aluminum silicide (AlSi) or nickel silicide (NiSi)). Alternatively, the first field plate122may be made of other suitable conductors.

The second electrode130is disposed at a position above and opposite to the first electrode120with the isolation film140sandwiched between the first electrode120and the second electrode130(accordingly, the isolation film140being formed in a region between the first electrode120and the second electrode130). The second electrode130is electrically connected to the drive-use power source Vcc and the low-side drive circuit12disposed outside. The second electrode130is brought into contact with the second contact region CR2of the semiconductor base body110via an opening formed in the insulation film150. The second electrode130is made of metal (for example, aluminum).

The third electrode160is a membrane-like member disposed over the insulation film150at a position where the third electrode160is brought into contact with the isolation film140. In this embodiment 1, the third electrode160is a membrane-like member. However, the third electrode160may not be a membrane-like member. The third electrode160faces a portion of the back gate region113and a portion of the first semiconductor layer112by way of the insulation film150.

The second field plate162is connected to the third electrode160, and is formed over a surface of the isolation film140. The second field plate162is integrally formed with the third electrode160. In the embodiment 1, the third electrode160and the second field plate162are made of polysilicon. However, the third electrode160and the second field plate162may be made of metal (for example, aluminum) or silicide (for example, metal silicide such as aluminum silicide (AlSi) or nickel silicide (NiSi)). Alternatively, the third electrode160and the second field plate162may be made of other suitable conductors.

One side of the connecting portion164is connected to the second electrode130, and the other side of the connecting portion164extends over the second field plate162, and is connected to the second field plate162. The connecting portion164may be made of metal (for example, aluminum).

The fourth electrode170is connected to the third contact region CR3and the back gate region113of the semiconductor base body110via openings formed in the insulation film150. The fourth electrode170is connected to the reference potential outside and hence, the potential of the substrate111and the potential of the back gate region113become the reference potential.

3. Operation of Semiconductor Device100According to Embodiment 1

Next, the description is made with respect to the semiconductor device100according to the embodiment 1 that possesses a function as a rectifier element of the bootstrap circuit.FIG.3is a cross-sectional view for describing a mode of the semiconductor device100according to the embodiment 1 during a conductive period (during a charging period, Vcc>Vb).FIG.4is a cross-sectional view for describing a mode of the semiconductor device100according to the embodiment 1 during a non-conductive period (during a reverse bias applying period, Vcc<Vb).

(1) Conductive Period (Charging Period, Vcc>Vb)

Next, when a low-side switch Q2is turned on, a voltage Vcc of a drive-use power source becomes larger than a voltage Vb on a capacitor22side. In the semiconductor device100according to the embodiment 1, the first electrode120is connected to the capacitor22, and the second electrode130is connected to the drive-use power source Vcc. Accordingly, the semiconductor device100according to the embodiment 1 has substantially the same configuration as an n-channel metal oxide semiconductor (MOS) in which the first electrode120forms a source electrode of the n-channel MOS, the second electrode130forms a drain electrode of the n-channel MOS, and the third electrode160forms a gate electrode of the n-channel MOS (seeFIG.3). The third electrode160that forms the gate electrode is connected to the second electrode130that forms the drain electrode. Accordingly, a gate-source voltage is generated so that a state is brought about where the gate electrode is ON whereby a channel region113′ is formed in the back gate region113that faces the third electrode160with the insulation film150sandwiched between the third electrode160and the back gate region113. Accordingly, an electric current flows from the drive-use power source Vcc to the capacitor22via the second electrode130, the channel region113′, the first semiconductor layer112, the first contact region CR1, and the first electrode120so that the capacitor22is charged.

(2) Non-Conductive Period (Reverse Bias Applying Period of Body Diode Vcc<Vb)

When the low-side switch Q2is turned off by switching, a voltage Vs at the node N between the high-side switch Q1and the low-side switch Q2rises. Along with such rising of the voltage Vs at the node N, a voltage Vb also rises. Then, a voltage Vcc of the drive-use power source becomes smaller than a voltage Vb on a capacitor22side. Accordingly, the semiconductor device100according to the embodiment 1 has substantially the same configuration as an n channel MOS in which the first electrode120forms a drain electrode of the n-channel MOS, the second electrode130forms a source electrode of the n-channel MOS, and the third electrode160forms a gate electrode of the n-channel MOS (seeFIG.4). The third electrode160that forms the gate electrode is connected to the second electrode130that forms the source electrode. Accordingly, a gate-source voltage becomes 0 and hence, the channel region113′ is not formed in the back gate region113whereby a state is brought about where the semiconductor device100is not ON (the body diode formed of the p-type back gate region113and the n-type first semiconductor layer112being brought into a reverse bias applying state). Accordingly, when a voltage of the capacitor22is superposed on the high-side drive circuit11, an electric current does not flow from the capacitor22to the drive-use power source Vcc and hence, it is possible to prevent a reverse flow of the electric current from the capacitor22to the drive-use power source Vcc.

Next, a relationship between a voltage Vb and a charge current Ib that flows in the semiconductor device100is described.FIG.5is a graph illustrating a relationship between the voltage Vb and the charge current Ib that flows in the semiconductor device100.

As illustrated inFIG.5, when the voltage Vb is small, a voltage Vcc of the drive-use power source is larger than the voltage Vb on a capacitor22side so that the semiconductor device100is turned on and the charge current Ib flows from the drive-use power source Vcc to the capacitor22. When charging of the capacitor22continues, the voltage Vb is gradually increased, and when a difference between the voltage Vcc of the drive-use power source Vcc and the voltage Vb of the capacitor22becomes smaller, the charge current Ib becomes gradually smaller.

In such a phenomenon, the semiconductor device100according to the embodiment 1 that is a field effect transistor is used as a rectifier element and hence, unlike a case where a bootstrap diode is used, a voltage drop minimally occurs. Accordingly, the charge current Ib flows until the voltage Vb becomes a voltage near the voltage Vcc. Further, in the semiconductor device100according to the embodiment 1, a dopant concentration of the back gate region113is extremely low. Accordingly, even when a threshold voltage is extremely small so that the voltage Vb becomes near the voltage Vcc, a current of the charge current Ib can hold a predetermined value.

When the voltage Vcc of the second electrode becomes substantially equal to the voltage Vb of the first electrode, the charge current Ib is suddenly lowered and scarcely flows. When the voltage Vcc of the second electrode becomes smaller than the voltage Vb of the first electrode, the channel region of the semiconductor device100dissipates and becomes a reverse bias applying state and hence, the charge current Ib scarcely flows.

In this manner, the semiconductor device100according to the embodiment 1 functions as a rectifier element that controls charging and discharging of the capacitor.

4. Advantageous Effects of Semiconductor Device100According to Embodiment 1

According to the semiconductor device100of the embodiment 1, the semiconductor base body110has the n-type back gate region113that is formed in at least the region of the semiconductor base body110that faces the third electrode160by way of the insulation film150with the depth that allows the back gate region113to reach the substrate111. With such a configuration, the second electrode130, the back gate region113, the first semiconductor layer112, the insulation film150, and the third electrode160form a field effect transistor. Accordingly, when a voltage Vcc of the second electrode130is larger than a voltage Vb of the first electrode120, the third electrode160is turned on so that an electric current flows from the second electrode130to the first electrode120and a capacitor can be charged. On the other hand, when the voltage Vcc of the second electrode130is smaller than the voltage Vb of the first electrode120, the third electrode160is turned off so that the electric current can be shut off. Accordingly, the semiconductor device100can realize a function of a rectifier element in the same manner as a conventional bootstrap diode.

In a bootstrap circuit, in a case where a bootstrap diode is used as a rectifier element, a voltage drop amounting to a forward voltage that is a characteristic of a diode is generated. Accordingly, a voltage applied to the capacitor from a drive-use power source Vcc is lowered. Accordingly, it is difficult to charge the capacitor to a voltage near the drive-use power source Vcc. On the other hand, according to the semiconductor device100of the embodiment 1, the field effect transistor that is formed of the second electrode130, the back gate region113, the first semiconductor layer112, the insulation film150, and the third electrode160is used as the rectifier element. Accordingly, unlike the case where a bootstrap diode is used, there is no possibility that a voltage drop amounting to a forward voltage is generated and hence, the capacitor22can be charged to a voltage near the drive-use power source Vcc (seeFIG.5).

To turn on a field effect transistor, it is necessary to apply a voltage higher than a source electrode between a gate and a source. Accordingly, in a case where a field effect transistor is used as a rectifier element in a bootstrap circuit, the field effect transistor cannot be turned on unless a voltage higher than drive-use power source Vcc is applied to a gate electrode (a third electrode). In a case where it is intended to set a voltage to be applied to a substrate low, a substrate bias effect is generated so that a threshold voltage becomes higher whereby it is necessary to set the voltage applied to the gate electrode (third electrode) further higher. On the other hand, according to the semiconductor device100of the embodiment 1, a dopant concentration in the back gate region113falls within the range of 1×1010cm−3to 1×1015cm−3and hence, a threshold voltage becomes extremely small (near 0V) and hence, a channel region113′ can be easily formed. Further, an electric field that expands to the back gate region113can be made small and hence, an influence exerted by a substrate bias effect can be reduced. As a result, it is unnecessary to apply a high voltage more than necessary to the third electrode160to turn on the semiconductor device and hence, the semiconductor device can be turned on and off with an appropriate voltage.

The reason a dopant concentration of the back gate region113is set to 1×1010cm−3or more is as follows. In a case where a dopant concentration of the back gate region113is less than 1×1010cm−3, a pn junction between the back gate region113and the first semiconductor layer112cannot form a sufficient potential barrier during a reverse bias applying period and hence, there is a possibility that a reverse current flows between the first electrode120and the second electrode130during the reverse bias applying period whereby it is difficult for the semiconductor device100to hold a function as a rectifier element. The reason the dopant concentration of the back gate region113is set to 1015cm−3or less is as follows. In a case where the dopant concentration of the back gate region113exceeds 1015cm−3, a threshold voltage is increased so that it is difficult to form the channel region113′ whereby it is necessary to apply a relatively high voltage to the third electrode160.

According to the semiconductor device100of the embodiment 1, the semiconductor base body110has the p-type back gate region113that is formed in at least the region of the semiconductor base body110that faces the third electrode160by way of the insulation film150with the depth that allows the back gate region113to reach the substrate111so that a parasitic transistor that causes a parasitic current flowing between the second electrode130and the substrate111is minimally formed. Accordingly, drawbacks such as the increase of a leak current and lowering of a withstand voltage generated by a parasitic current and a breakdown of an element minimally occur and hence, a rectifier element can be formed over the semiconductor base body. As a result, the rectifier element can be incorporated in the gate driver IC.

Further, the semiconductor device100according to the embodiment 1 includes the isolation film140that is formed over the surface of the semiconductor base body110in the region between the first electrode120and the second electrode130so that a semiconductor device having a RESURF structure is formed by the substrate111and the first semiconductor layer112of the semiconductor base body110and the isolation film140. Accordingly, a relatively high voltage applied to the first electrode120of a can be lowered by a voltage drop so that the voltage is made to approximate a voltage of the second electrode130connected to a circuit of a relatively low voltage. Accordingly, a region of a relatively high voltage and a region of a relatively low voltage can be formed over the same substrate.

According to the semiconductor device100of the embodiment 1, the third electrode160is connected to the second electrode130. Accordingly, even when the semiconductor device100does not include a drive circuit or the like for switching, when the voltage Vcc of the second electrode130is larger than the voltage Vb of the first electrode120, a forward bias is generated, while when the voltage Vcc of the second electrode130is smaller than the voltage Vb of the first electrode120, a reverse bias is generated. With such a configuration, the semiconductor device100of the embodiment 1 becomes a semiconductor device that functions as a rectifier element having a simple configuration.

According to the semiconductor device100of the embodiment 1, the substrate111is connected to a reference potential and hence, the channel region113′ is easily formed in the back gate region113even when a voltage applied to the third electrode160is small. An electric field that expands to the back gate region113becomes small and hence, an influence exerted by by a substrate bias effect can be reduced.

According to the semiconductor device100of the embodiment 1, the first electrode120is electrically connected to the drive circuit (high-side drive circuit11) that controls turning on and off of the high-side switch Q1of the main circuit C1and the capacitor22, and the second electrode130is electrically connected to the drive-use power source Vcc. Accordingly, the semiconductor device100of the embodiment 1 becomes a semiconductor device that functions as a rectifier element of a bootstrap circuit.

According to the semiconductor device100of the embodiment 1, the semiconductor device100is formed over the same semiconductor base body at which the high-side drive circuit11and the low-side drive circuit12that control turning on and off of the switches Q1, Q2of the first circuit are formed. Accordingly, the semiconductor device100that forms a rectifier element can be incorporated in the gate driver IC and hence, it is possible to provide a semiconductor device that can satisfy a demand for downsizing of electric equipment.

According to the semiconductor device100of the embodiment 1, the semiconductor base body110has the n-type second contact region CR2having a higher concentration than the first semiconductor layer112formed in a region connected to the second electrode130, and the back gate region113is also formed in the region between the second contact region CR2and the substrate111. Accordingly, the semiconductor base body110can be formed by merely forming the n-type first semiconductor layer112, the first contact region CR1, the second contact region CR2, and the third contact region CR3on the p-type semiconductor substrate and hence, it is possible to provide a semiconductor device having the above-mentioned advantageous effects with the simple configuration.

Embodiment 2

FIG.6is a cross-sectional view for describing a semiconductor device101according to the embodiment 2.

The semiconductor device101according to the embodiment 2 has basically substantially the same configuration as the semiconductor device100according to the embodiment 1. However, the semiconductor device101according to the embodiment 2 differs from the semiconductor device100according to the embodiment 1 with respect to points that the fourth electrode170is not disposed in the semiconductor device101according to the embodiment 2, and the semiconductor device101according to the embodiment 2 further includes an n-type semiconductor region118. That is, in the semiconductor device101according to the embodiment 2, as illustrated inFIG.6, the semiconductor base body110has the n-type semiconductor region118having lower concentration than a second contact region CR2formed in a region surrounding the second contact region CR2. A dopant concentration of the n-type semiconductor region118is lower than a dopant concentration of a first semiconductor layer112.

In the semiconductor device101according to the embodiment 2, although the fourth electrode170in the embodiment 1 is not formed, a substrate111is connected to a reference potential. Further, a second electrode130and a third electrode160are not connected to each other, and a channel can be formed in a back gate region113aby applying a voltage to the third electrode160.

In this manner, the semiconductor device101according to the embodiment 2 differs from the semiconductor device100according to the embodiment 1 with respect to the points that the fourth electrode170is not formed in the semiconductor device101according to the embodiment 2, and the semiconductor device101according to the embodiment 2 further includes the n-type semiconductor region118. However, in the same manner as the semiconductor device100according to the embodiment 1, a semiconductor base body110ahas the p-type back gate region113athat is formed in at least the region of the semiconductor base body110athat faces the third electrode160by way of an insulation film150with a depth that allows the back gate region113ato reach the substrate111so that a parasitic transistor that causes a parasitic current flowing between the second electrode130and the substrate111is minimally formed. Accordingly, drawbacks such as the increase of a leak current and lowering of a withstand voltage generated by a parasitic current and a breakdown of an element minimally occur and hence, a rectifier element can be formed over the semiconductor base body. As a result, the rectifier element can be incorporated in a gate driver IC.

In the semiconductor device101according to the embodiment 2, the semiconductor base body110includes, in a region connected to the second electrode130, the n-type second contact region CR2having a higher concentration than a first semiconductor layer112, and the n-type semiconductor region118formed in a region surrounding the second contact region CR2and having a lower concentration than the second contact region CR2. Accordingly, during a reverse vias applying period, it is possible to ensure a withstand voltage between the third electrode160that forms a gate electrode and the second electrode130that forms a source electrode.

The semiconductor device101according to the embodiment 2 has substantially the same configuration as the semiconductor device100according to the embodiment 1 except for the points that the fourth electrode170is not disposed in the semiconductor device101according to the embodiment 2, and the semiconductor device101according to the embodiment 2 further includes the n-type semiconductor region118. Accordingly, the semiconductor device101of the embodiment 2 acquires corresponding advantageous effects found amongst all advantageous effects that the semiconductor device100according to the embodiment 1 acquires.

Embodiment 3

FIG.7is a cross-sectional view for describing a semiconductor device102according to the embodiment 3.

The semiconductor device102according to the embodiment 3 has basically substantially the same configuration as the semiconductor device101according to the embodiment 2. However, the semiconductor device102according to the embodiment 3 differs from the semiconductor device101according to the embodiment 2 with respect to a point that an n-type semiconductor region118ais brought into contact with a substrate (seeFIG.7). That is, in the semiconductor device102according to the embodiment 3, the n-type semiconductor region118ais formed in a region that is brought into contact with a second electrode130with a depth that allows the n-type semiconductor region118ato reach a substrate111. That is, the n-type semiconductor region118ais brought into contact with the substrate111.

As methods of forming the n-type semiconductor region118aand a back gate region113b, suitable methods can be selectively used. In the embodiment 3, a semiconductor base body is prepared by stacking the substrate111and an n-type semiconductor layer to each other, and a columnar (having a columnar shape in cross section) back gate region is formed over the n-type semiconductor layer so that the n-type semiconductor layer is formed in a separated manner as an n-type first semiconductor layer112and the n-type semiconductor region118a. Accordingly, a dopant concentration of the n-type semiconductor region118aand a dopant concentration of the first semiconductor layer112are equal, and the back gate region113bforms a columnar region that is formed in a region that faces a third electrode160by way of an insulation film150with a depth that allows the back gate region113bto reach the substrate111.

The semiconductor device102according to the embodiment 3 differs from the semiconductor device101according to the embodiment 2 with respect to the point that the n-type semiconductor region is brought into contact with the substrate. However, in the same manner as the semiconductor device101according to the embodiment 2, a semiconductor base body110bhas the p-type back gate region113bthat is formed in at least a region of the semiconductor base body110bthat faces the third electrode160by way of the insulation film150with a depth that allows the back gate region113bto reach the substrate111so that a parasitic transistor that causes a parasitic current flowing between the second electrode130and the substrate111is minimally formed. Accordingly, drawbacks such as the increase of a leak current and lowering of a withstand voltage generated by a parasitic current and a breakdown of an element minimally occur and hence, a rectifier element can be formed over the semiconductor base body. As a result, the rectifier element can be incorporated in a gate driver IC.

In the semiconductor device102according to the embodiment 3, a dopant concentration of the n-type semiconductor region118ais equal to a dopant concentration of the first semiconductor layer112. Accordingly, by forming a columnar back gate region in the n-type semiconductor layer, the n-type semiconductor layer can be formed in a separated manner into the n-type first semiconductor layer112and the n-type semiconductor region118a. Accordingly, it is unnecessary to add a new step for forming the n-type semiconductor region118aand hence, a semiconductor device can be manufactured by a simple method.

The semiconductor device102according to the embodiment 3 has substantially the same configuration as the semiconductor device101according to the embodiment 2 except for the point that the n-type semiconductor region is brought into contact with the substrate. Accordingly, the semiconductor device102of the embodiment 3 acquires corresponding advantageous effects found amongst all advantageous effects that the semiconductor device101according to the embodiment 2 acquires.

The present invention has been described based on the above-mentioned embodiments heretofore. However, the present invention is not limited to the above-mentioned embodiments. Various modes are conceivable without departing from the gist of the present invention. For example, the following modifications are conceivable.

(1) The numbers, the materials, the shapes, the positions, the sizes, and the like of the constitutional elements described in the above-mentioned embodiments are provided for an exemplifying purpose, and these factors can be changed within a scope that the advantageous effects of the present invention are not impaired.
(2) In the above-mentioned embodiment 1, the substrate111is connected to the reference potential by providing the fourth electrode. However, the present invention is not limited to such a configuration. The potential of the substrate111may be set as the reference potential without providing the fourth electrode, or the substrate111may not be connected to the reference potential. Further, in the embodiments 2 and 3, the fourth electrode is not provided. However, the present invention is not limited to such a configuration. The substrate111may be connected to the reference potential by providing the fourth electrode, or the potential of the substrate111may be set to a potential different from the reference potential.
(3) In the above-mentioned embodiment 1, the third electrode is connected to the second electrode. However, the present invention is not limited to such a configuration. The semiconductor device may be turned on and off by applying a voltage to the third electrode without connecting the third electrode to the second electrode. Further, in the embodiments 2 and 3, the semiconductor device is turned on and off by applying a voltage to the third electrode without connecting the third electrode to the second electrode. However, the present invention is not limited to such a configuration. The third electrode may be connected to the second electrode.
(4) In the above-mentioned respective embodiments, the back gate region is connected to the substrate111. However, the present invention is not limited to such a configuration. The back gate region may not be connected to the substrate111. Further, the dopant concentration of the substrate111and the dopant concentration of the back gate region may differ from each other.
(5) In the above-mentioned respective embodiments, the semiconductor device is used as the rectifier element of the bootstrap circuit. However, the present invention is not limited to such a configuration. The semiconductor device may be used as a rectifier element other than the rectifier element of the bootstrap circuit.

REFERENCE SIGNS LIST

10: high-side drive circuit20: low-side drive circuit22: capacitor100,101,102: semiconductor device110: semiconductor base body111: substrate112: first semiconductor layerCR1: first contact regionCR2: second contact regionCR3: third contact region113,113a,113b: back gate region118,118a: n-type semiconductor region120: first electrode130: second electrode140: isolation film150,152: insulation film160: third electrode170: fourth electrodeC1: first circuitC2: second circuit