Patent ID: 12219280

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the exemplary embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and the description to refer to the same or like components.

Certain terms are used throughout the specification and appended claims of the disclosure to refer to specific components. Those skilled in the art should understand that electronic device manufacturers may refer to the same components by different names. This article does not intend to distinguish those components with the same function but different names. In the following description and rights request, the words such as “comprise” and “include” are open-ended terms, and should be explained as “including but not limited to . . . ”.

The term “electrically connection (or coupling)” used throughout the whole specification of the present application (including the appended claims) may refer to any direct or indirect connection means. For example, if the text describes that a first device is electrically connected (or coupled) to a second device, it should be interpreted that the first device may be directly connected to the second device, or the first device may be indirectly connected through other devices or certain connection means to be connected to the second device. The terms “first”, “second”, and similar terms mentioned throughout the whole specification of the present application (including the appended claims) are merely used to name discrete elements or to differentiate among different embodiments or ranges. Therefore, the terms should not be regarded as limiting an upper limit or a lower limit of the quantity of the elements and should not be used to limit the arrangement sequence of elements. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and the embodiments represent the same or similar parts. Reference may be mutually made to related descriptions of elements/components/steps using the same reference numerals or using the same terms in different embodiments.

An electronic device of the disclosure may be, for example, a varactor antenna, a fingerprint sensor or an X-ray flat panel detector (FPD). An electronic unit of the disclosure may be, for example, a voltage controlled unit or a sensing unit (e.g. a photodiode). It should be noted that, the electronic device of the disclosure may be manufactured using a display panel process, and related transistors and electronic components are fabricated on a glass substrate.

It should be noted that in the following embodiments, the technical features of several different embodiments may be replaced, recombined, and mixed without departing from the spirit of the disclosure to complete other embodiments. As long as the features of each embodiment do not violate the spirit of the disclosure or conflict with each other, they may be mixed and used together arbitrarily.

FIG.1is a schematic diagram of an electronic device according to an embodiment of the disclosure. Referring toFIG.1, the electronic device100includes an electronic unit110, a sensing circuit120and a circuit130. The sensing circuit120is electrically connected to the electronic unit110through a sensing node N1. The circuit130is electrically connected to the sensing node N1, and configured to apply a specific voltage to the sensing node N1. In other embodiments of the disclosure, the circuit130may be a bias circuit or a reset circuit. In the embodiment of the disclosure, the electronic device100is configured to perform a calibration mode and a sensing mode. When the electronic device100performs the calibration mode, the sensing circuit120may sense the sensing node N1with applying the specific voltage by the circuit. The electronic device100may generate a sense signal corresponding to a voltage of the sensing node N1. When the electronic device100performs the sensing mode, the sensing circuit120may sense the sensing node N1after the specific voltage is applied to the sensing node N1.

FIG.2Ais a schematic diagram of an electronic device according to an embodiment of the disclosure.FIG.2Bis a schematic diagram of a relationship between an output voltage and a data voltage according to an embodiment of the disclosure. Referring toFIG.2AandFIG.2B, an electronic device200includes an active matrix pixel array including a plurality of pixels, and a circuit architecture of at least one of the pixels may be the same as a pixel201ofFIG.2A. The electronic device200may be an active matrix voltage controlled unit. In the embodiment of the disclosure, the electronic device200includes the pixel201, a readout circuit240, a control data line CDL, a sense data line SDL, a control scan line CSL and a sense scan line SSL. The control data line CDL and the sense data line SDL may be electrically connected to multiple pixels in one column of the active matrix pixel array, respectively. The control scan line CSL and the sense scan line SSL may be electrically connected to multiple pixels in one row of the active matrix pixel array, respectively. The pixel201includes a scan transistor Ts, an electronic unit210, a bias circuit230(corresponding to the circuit130ofFIG.1) and a sensing circuit220.

In the embodiment of the disclosure, the sensing circuit220is electrically connected to the electronic unit210through a sensing node N1. The bias circuit230is electrically connected to the sensing node N1. The sensing circuit220is electrically connected to the sense scan line SSL for receiving a sense scan signal, and is electrically connected to the sense data line SDL for providing a sense signal. The sense scan signal is used to control (enable) the sensing circuit220. The bias circuit230and the scan transistor Ts is electrically connected to the control scan line CSL for receiving a scan signal, and is electrically connected to the control data line CDL for receiving a control signal with a data voltage Vdata. That is, the bias circuit230receives the control signal through the control data line CSL according to the scan signal. A control terminal of the scan transistor Ts is electrically connected to the control scan line CSL. A first terminal of the scan transistor Ts is electrically connected to the control data line CDL. That is, the scan transistor Ts is electrically connected between the control data line CDL and the bias circuit230, and receives the scan signal. A second terminal of the scan transistor Ts is electrically connected to the sensing node N1. The readout circuit240is electrically connected to the sense data line SDL for receiving the sense signal provided by the sensing circuit220. The scan signal is used to control (enable) the bias circuit230and the scan transistor Ts. However, in one embodiment of the disclosure, it is optional that the bias circuit230is controlled by the control scan signal provided by the control scan line CSL. In addition, the scan transistor Ts may be a N-type transistor, such as a N-type metal oxide semiconductor (NMOS). In other embodiments of the disclosure, the scan transistor Ts may be a P-type transistor, such as a P-type metal oxide semiconductor (PMOS).

In the embodiment of the disclosure, the scan transistor Ts may be turned-on to provide the control signal with the data voltage Vdata to the bias circuit230through the sensing node N1, so that the bias circuit230may apply a voltage to the sensing node N1. That is, the bias circuit230may receive the control signal through the control data line CDL according to the scan signal. In the embodiment of the disclosure, the data voltage Vdata may be a programmable voltage. The sensing circuit220may perform a loop back calibration to sense the sensing node N1to generate the sense signal according to a voltage of the sensing node N1, so that the readout circuit240receives the sense signal from the sense data line SDL. The readout circuit240provides an output signal with an output voltage Vout to an external processing circuit according to the sense signal. In the embodiment of the disclosure, the control data line CDL may provide the control scan signal with different data voltages, so that the readout circuit240may correspondingly provide the output signal with different output voltages. Therefore, the external processing circuit may compare the data voltage Vdata and the output voltage Vout to obtain a calibration data corresponding a relationship between the output voltage Vout and the data voltage Vdata as shown inFIG.2B.

FIG.3is a schematic diagram of an electronic device according to an embodiment of the disclosure. Referring toFIG.3, an electronic device300includes an active matrix pixel array including a plurality of pixels, and a circuit architecture of at least one of the pixels may be the same as a pixel301. In the embodiment of the disclosure, the pixels of the electronic device300may be configured to perform an antenna function, and the electronic device300may be an active matrix voltage controlled unit, such as a varactor antenna, but the disclosure is not limited thereto. In the embodiment of the disclosure, the electronic device300includes the pixel301, a readout circuit340, a source driver integrated circuit (IC)350, a control data line CDL and a sense data line SDL. There is a stray resistance R1on the control data line CDL. There is a stray resistance R2on the sense data line SDL. The pixel301includes a scan transistor Ts, an electronic unit310, a bias circuit330(corresponding to the circuit130ofFIG.1) and a (voltage) sensing circuit320. In one embodiment, the electronic unit310may be a voltage controlled device. The bias circuit330includes a storage capacitor Cst. The readout circuit340may be composed of a bias current source341and a voltage amplifier342. The sensing circuit320includes a first sense transistor T1and a second sense transistor T2. The source driver IC350includes a digital to analog converter (DAC)351.

In the embodiment of the disclosure, the DAC351of the source driver IC350is electrically connected to the control data line CDL. A first terminal of the scan transistor Ts is electrically connected to the control data line CDL. An output terminal of the DAC351is electrically connected to the first terminal of the scan transistor Ts through the control data line CDL having the stray resistance R1. A control terminal of the scan transistor Ts receives a scan signal SC. A second terminal of the scan transistor Ts is electrically connected to a sensing node N1. A first terminal of the storage capacitor Cst is electrically connected to a voltage V1. A second terminal of the storage capacitor Cst is electrically connected to the second terminal of the scan transistor Ts and the sensing node N1. The electronic unit310is electrically connected between the sensing node N1and a voltage V0. A first terminal of the first sense transistor T1is electrically connected to the sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A first terminal of the second sense transistor T2is electrically connected to a voltage V2. A control terminal of the second sense transistor T2is electrically connected to the sensing node N1. A second terminal of the first sense transistor T1is electrically connected to a second terminal of the second sense transistor T2. A first terminal of the bias current source341is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R2. A second terminal of the bias current source341is electrically connected to a voltage V3. An input terminal of the voltage amplifier342is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R2. An output terminal of the voltage amplifier342may be electrically connected to an external processing circuit.

In the embodiment of the disclosure, the scan transistor Ts, the first sense transistor T1and the second sense transistor T2may be a N-type transistor, respectively, such as a N-type metal oxide semiconductor (NMOS). The above-mentioned first terminal and the second terminal of the transistor may include a drain terminal and a source terminal, respectively, and the above-mentioned control terminal of the transistor may be a gate terminal. In other embodiments of the disclosure, at least one of the scan transistor Ts, the first sense transistor T1and the second sense transistor T2may also be a P-type transistor, such as a P-type metal oxide semiconductor (PMOS). In addition, in the embodiment of the disclosure, the voltage V2may be greater than the voltage V3.

FIG.4is a schematic diagram of related signals and voltages according to the embodiment ofFIG.3of the disclosure. Referring toFIG.3andFIG.4, the electronic device300may be operated in a first test mode during a first test period TP1to perform a loop back calibration, a second test mode during a second test period TP2and a normal bias operation mode during a normal operation period NP. The first test mode is used to test or calibrate the sensing circuit320, and the second test mode is used to test or calibrate the bias circuit330.

During the first test period TP1from time t0to time t1, referring to a current path P11, the DAC351outputs a control signal with a data voltage Vdata to the control data line CDL. The scan transistor Ts is turned-on to transmit the data voltage Vdata to the storage capacitor Cst, the sensing node N1and the control terminal of the second sense transistor T2according to the scan signal SC with a high voltage level. Thus, a voltage V_N1of the sensing node N1may be equal to the data voltage Vdata. Then, referring to a current path P12, the first sense transistor T1is turned-on to readout a voltage of the second terminal (source terminal) of the second sense transistor T2corresponding to the voltage V_N1of the sensing node N1(i.e. a voltage of the control terminal (gate terminal) of the second sense transistor T2) according to the sense scan signal SE with the high voltage level, so as to readout a sense signal to the sense data line SDL. That is, the calibration mode of the electronic device300is activated when scan transistor Ts and the first sense transistor T1are simultaneously turned-on. Thus, the voltage amplifier342may output an output voltage Vout according to the sense signal, and the output voltage Vout may be equal to a voltage of the data voltage Vdata minus a first delta voltage dV1(Vdata−dV1). It should be noted that, in the embodiment of the disclosure, the first delta voltage dV1may be caused by a threshold voltage of the second sense transistor T2, the first sense transistor T1, the stray resistance R2and the bias current source341. Therefore, the external processing circuit may compare the data voltage Vdata and the output voltage Vout to obtain a calibration data corresponding a relationship between the output voltage Vout and the data voltage Vdata as shown inFIG.2B. Moreover, the external processing circuit may further calculate a voltage of the output voltage Vout minus the data voltage Vdata (Vout-Vdata) to obtain an actual voltage value of the first delta voltage dV1, so as to obtain the influence of the internal circuit characteristics of the sensing circuit320and the readout circuit340for the output voltage.

During the second test period TP2from time t1to time t2, referring to a current path P21, the scan transistor Ts is turned-off according to the scan signal SC with a low voltage level. The voltage of the voltage V_N1of the sensing node N1may be changed to a voltage of the data voltage Vdata minus a second delta voltage dV2. It should be noted that, in the embodiment of the disclosure, the second delta voltage dV2may be caused by a leak current of the electronic unit310. Then, referring to a current path P22, the first sense transistor T1is turned-on to readout a voltage of the second terminal (source terminal) of the second sense transistor T2corresponding to the voltage V_N1of the sensing node N1(i.e. a voltage of the control terminal (gate terminal) of the second sense transistor T2) according to the sense scan signal SE with the high voltage level, so as to provide the sense signal to the sense data line SDL. Thus, the voltage amplifier342may output an output voltage Vout according to the sense signal, and the output voltage Vout may be equal to a voltage of the data voltage Vdata minus the first delta voltage dV1and minus the second delta voltage dV2(Vdata−dV1−dV2). The external processing circuit may calculate a voltage of the output voltage Vout minus the data voltage Vdata (Vout−Vdata) to obtain a voltage value of the negative first delta voltage dV1minus the second delta voltage dV2(−dV1−dV2). Due to the actual voltage value of the first delta voltage dV1has been obtained in the previous calculation, the external processing circuit may further obtain an actual voltage value of the second delta voltage dV2.

During the normal operation period NP from time t2to time t3, the scan transistor Ts and the second sense transistor T2are turned-off according to the scan signal SC and the sense scan signal SE with the low voltage level, respectively. Based on the bias circuit330is previously programed by the data voltage Vdata, the voltage of the voltage V_N1of the sensing node N1may be the voltage of the data voltage Vdata minus the second delta voltage dV2. That is to say, due to the actual voltage value of the second delta voltage dV2has been obtained in the previous calculation, the external processing circuit may obtain the influence of the leak current of the electronic unit310, and correspondingly calibrate the bias circuit330and adjust the data voltage Vdata of the control signal, so as to properly operate the voltage controlled unit310during the normal operation period NP.

FIG.5is a schematic diagram of an electronic device according to an embodiment of the disclosure. Referring toFIG.5, an electronic device500includes an active matrix pixel array including a plurality of pixels, and a circuit architecture of at least one of the pixels may be the same as a pixel501. In the embodiment of the disclosure, the pixels of the electronic device500may be configured to perform an antenna function, and the electronic device500may be an active matrix voltage controlled unit, such as a varactor antenna, but the disclosure is not limited thereto. In the embodiment of the disclosure, the electronic device500includes the pixel501, a readout circuit540, a source driver integrated circuit (IC)550, a control data line CDL and a sense data line SDL. There is a stray resistance R1on the control data line CDL. There is a stray resistance R2on the sense data line SDL. The pixel501includes a scan transistor Ts1, an electronic unit510, a bias circuit530(corresponding to the circuit130ofFIG.1) and a (voltage) sensing circuit520. In one embodiment, the electronic unit510may be a voltage controlled device. The bias circuit530includes a storage capacitor Cst, a drive transistor Td and a scan transistor Ts2. The readout circuit540may be composed of a bias current source541and a voltage amplifier542. The sensing circuit520includes a first sense transistor T1and a second sense transistor T2. The source driver IC550includes a digital to analog converter (DAC)551.

In the embodiment of the disclosure, the DAC551of the source driver IC550is electrically connected to the control data line CDL. A first terminal of the scan transistor Ts1is electrically connected to the control data line CDL. An output terminal of the DAC551is electrically connected to the first terminal of the scan transistor Ts through the control data line CDL having the stray resistance R1. A control terminal of the scan transistor Ts1receives a scan signal SC. A second terminal of the scan transistor Ts0is electrically connected to a sensing node N1. A first terminal of the storage capacitor Cst is electrically connected to a voltage V1. A first terminal of the drive transistor Td is electrically connected to the voltage V1. A second terminal of the drive transistor Td is electrically connected to the sensing node N1. A control terminal of the drive transistor Td is electrically connected to a second terminal of the storage capacitor Cst. A first terminal of the scan transistor Ts2is electrically connected to the second terminal of the storage capacitor Cst and the control terminal of the drive transistor Td. A second terminal of the scan transistor Ts2is electrically connected to the sensing node N1. A control terminal of the scan transistor Ts2receives the scan signal SC. The drive transistor Td may be operated as a source follower amplifier electrically connected to the sensing node N1. The electronic unit510is electrically connected between the sensing node N1and a voltage V0. A first terminal of the first sense transistor T1is electrically connected to the sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A first terminal of the second sense transistor T2is electrically connected to a voltage V2. A control terminal of the second sense transistor T2is electrically connected to the sensing node N1. A second terminal of the first sense transistor T1is electrically connected to a second terminal of the second sense transistor T2. A first terminal of the bias current source541is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R2. A second terminal of the bias current source541is electrically connected to a voltage V3. An input terminal of the voltage amplifier542is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R2. An output terminal of the voltage amplifier542may be electrically connected to an external processing circuit.

In the embodiment of the disclosure, the scan transistor Ts1, the scan transistor Ts2, the drive transistor Td, the first sense transistor T1and the second sense transistor T2may be a N-type transistor, respectively, such as a N-type metal oxide semiconductor (NMOS). The above-mentioned first terminal and the second terminal of the transistor may include a drain terminal and a source terminal, respectively, and the above-mentioned control terminal of the transistor may be a gate terminal. In other embodiments of the disclosure, the scan transistor Ts may be a P-type transistor, such as a P-type metal oxide semiconductor (PMOS). In addition, in the embodiment of the disclosure, the voltage V1may be greater than the voltage V0, and the voltage V2may be greater than the voltage V3.

FIG.6is a schematic diagram of related signals and voltages according to the embodiment ofFIG.5of the disclosure. Referring toFIG.5andFIG.6, the electronic device500may be operated in a first test mode during a first test period TP1to perform a loop back calibration, a second test mode during a second test period TP2and a normal bias operation mode during a normal operation period NP. The first test mode is used to test or calibrate the sensing circuit520, and the second test mode is used to test or calibrate the bias circuit530.

During the first test period TP1from time t0to time t1, referring to a current path P31, the DAC551outputs a control signal with a data voltage Vdata to the control data line CDL. The scan transistor Ts1and the scan transistor Ts2are turned-on to store the data voltage Vdata into the storage capacitor Cst, the sensing node N1and the control terminal of the second sense transistor T2according to the scan signal SC with a high voltage level. Thus, a voltage V_N1of the sensing node N1may be equal to the data voltage Vdata. Then, referring to a current path P32, the first sense transistor T1is turned-on to readout a voltage of the second terminal (source terminal) of the second sense transistor T2corresponding to the voltage V_N1of the sensing node N1(i.e. a voltage of the control terminal (gate terminal) of the second sense transistor T2) according to the sense scan signal SE with the high voltage level, so as to provide a sense signal to the sense data line SDL. That is, the calibration mode of the electronic device500is activated when the scan transistor Ts1, the scan transistor Ts2and the first sense transistor T1are simultaneously turned-on. Thus, the voltage amplifier542may output an output voltage Vout according to the sense signal, and the output voltage Vout may be equal to a voltage of the data voltage Vdata minus a first delta voltage dV1(Vdata−dV1). It should be noted that, in the embodiment of the disclosure, the first delta voltage dV1may be caused by a threshold voltage of the second sense transistor T2, the first sense transistor T1, the stray resistance R2and the bias current source541. Therefore, the external processing circuit may compare the data voltage Vdata and the output voltage Vout to obtain a calibration data corresponding a relationship between the output voltage Vout and the data voltage Vdata as shown inFIG.2B. Moreover, the external processing circuit may further calculate a voltage of the output voltage Vout minus the data voltage Vdata (Vout−Vdata) to obtain an actual voltage value of the first delta voltage dV1, so as to obtain the influence of the internal circuit characteristics of the sensing circuit520and the readout circuit540for the output voltage.

During the second test period TP2from time t1to time t2, referring to a current path P41, the scan transistor Ts1and the scan transistor Ts2are turned-off according to the scan signal SC with a low voltage level. The voltage of the voltage V_N1of the sensing node N1may be changed to a voltage of the data voltage Vdata minus a second delta voltage dV2. It should be noted that, in the embodiment of the disclosure, the second delta voltage dV2may be caused by a threshold voltage of the drive transistor Td and a leak current of the electronic unit510. Then, referring to a current path P42, the first sense transistor T1is turned-on to readout a voltage of the second terminal (source terminal) of the second sense transistor T2corresponding to the voltage V_N1of the sensing node N1(i.e. a voltage of the control terminal (gate terminal) of the second sense transistor T2) according to the sense scan signal SE with the high voltage level, so as to provide the sense signal to the sense data line SDL. Thus, the voltage amplifier542may output an output voltage Vout according to the sense signal, and the output voltage Vout may be equal to a voltage of the data voltage Vdata minus the first delta voltage dV1and minus the second delta voltage dV2(Vdata−dV1−dV2). The external processing circuit may calculate a voltage of the output voltage Vout minus the data voltage Vdata (Vout−Vdata) to obtain a voltage value of the negative first delta voltage dV1minus the second delta voltage dV2(−dV1−dV2). Due to the actual voltage value of the first delta voltage dV1has been obtained in the previous calculation, the external processing circuit may further obtain an actual voltage value of the second delta voltage dV2.

During the normal operation period NP from time t2to time t3, the scan transistor Ts1, the scan transistor Ts2and the second sense transistor T2are turned-off according to the scan signal SC and the sense scan signal SE with the low voltage level, respectively. Based on the bias circuit530is previously programed by the data voltage Vdata, the voltage of the voltage V_N1of the sensing node N1may be the voltage of the data voltage Vdata minus the second delta voltage dV2. That is to say, due to the actual voltage value of the second delta voltage dV2has been obtained in the previous calculation, the external processing circuit may obtain the influence of the threshold voltage of the drive transistor Td of the bias circuit530and the leak current of the voltage controlled unit510, and correspondingly calibrate the bias circuit530and adjust the data voltage Vdata of the control signal, so as to properly operate the voltage controlled unit510during the normal operation period NP.

FIG.7Ais a first type of the sensing circuit and the readout circuit according to an embodiment of the disclosure. Referring toFIG.7A, the sensing circuits320,520and the readout circuits340,540of the above-mentioned embodiments ofFIG.3andFIG.5may be realized as the sensing circuit720A and the readout circuit740A of the voltage sensing circuit ofFIG.7A. In the embodiment of the disclosure, the sensing circuit720A includes a first sense transistor T1and a second sense transistor T2. The readout circuit740A may be composed of a bias current source741A and a voltage amplifier742A. In the embodiment of the disclosure, the first sense transistor T1and the second sense transistor T2may be a N-type transistor, respectively, such as a N-type metal oxide semiconductor (NMOS). In the embodiment of the disclosure, the sensing circuit720A is a voltage mode sensing circuit, and the readout circuit740A is a voltage mode readout circuit.

In the embodiment of the disclosure, a first terminal of the first sense transistor T1is electrically connected to a sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A first terminal of the second sense transistor T2is electrically connected to a voltage (may have a high voltage level). A control terminal of the second sense transistor T2is electrically connected to a sensing node N1. A second terminal of the first sense transistor T1is electrically connected to a second terminal of the second sense transistor T2. A first terminal of the bias current source741A is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL. A second terminal of the bias current source741A is electrically connected to another voltage (may have a low voltage level). An input terminal of the voltage amplifier742A is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL. An output terminal of the voltage amplifier742A may be electrically connected to an external processing circuit.

In the embodiment of the disclosure, the second sense transistor T2may be operated as a source follower amplifier. When a voltage of the sensing node N1rises (during the above-mentioned test modes) and the first sense transistor T1is turned-on by the sense scan signal SE having a high voltage level, a voltage of the first terminal of the first sense transistor T1is correspondingly pulled-up by the second sense transistor T2. Thus, a current corresponding to the voltage of the sensing node N1is formed to flow from the first terminal of the first sense transistor T1to the bias current source741A through the sense data line SDL. Then, the input terminal of the voltage amplifier742A may receive the voltage of the first terminal of the first sense transistor T1, so that an output voltage Vout output by the output terminal of the voltage amplifier742A is correspondingly pulled-up. Therefore, the external processing circuit may effectively receive a sensing result of the voltage of the sensing node N1for calibration of the sensing circuit720A according to the output voltage Vout.

FIG.7Bis a second type of the sensing circuit and the readout circuit according to an embodiment of the disclosure. Referring toFIG.7B, the sensing circuits320,520and the readout circuits340,540of the above-mentioned embodiments ofFIG.3andFIG.5may be realized as the sensing circuit720B and the readout circuit740B of the voltage sensing circuit ofFIG.7B. In the embodiment of the disclosure, the sensing circuit720B includes a first sense transistor T1and a second sense transistor T2. The readout circuit740B may be composed of a bias current source741B and a voltage amplifier742B. In the embodiment of the disclosure, the first sense transistor T1may be a N-type transistor, such as a N-type metal oxide semiconductor (NMOS), and the second sense transistor T2may be a P-type transistor, such as a P-type metal oxide semiconductor (PMOS). In the embodiment of the disclosure, the sensing circuit720B is a voltage mode sensing circuit, and the readout circuit740B is a voltage mode readout circuit.

In the embodiment of the disclosure, a first terminal of the first sense transistor T1is electrically connected to a sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A first terminal of the second sense transistor T2is electrically connected to a voltage (may have a low voltage level). A control terminal of the second sense transistor T2is electrically connected to a sensing node N1. A second terminal of the first sense transistor T1is electrically connected to a second terminal of the second sense transistor T2. A first terminal of the bias current source741B is electrically connected to another voltage (may have a high voltage level). A second terminal of the bias current source741B is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL. An input terminal of the voltage amplifier742B is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL. An output terminal of the voltage amplifier742B may be electrically connected to an external processing circuit.

In the embodiment of the disclosure, the second sense transistor T2may be operated as a source follower amplifier. When a voltage of the sensing node N1drops (during the above-mentioned test modes) and the first sense transistor T1is turned-on by the sense scan signal SE having a high voltage level, a voltage of the first terminal of the first sense transistor T1is correspondingly pulled-down by the second sense transistor T2. Thus, a current corresponding to the voltage of the sensing node N1is formed to flow from the bias current source741B to the first terminal of the first sense transistor T1through the sense data line SDL. Then, the input terminal of the voltage amplifier742B may receive the dropped voltage of the first terminal of the first sense transistor T1, so that an output voltage Vout output by the output terminal of the voltage amplifier742B is correspondingly pulled-down. Therefore, the external processing circuit may effectively receive a sensing result of the voltage of the sensing node N1for calibration of the sensing circuit720B according to the output voltage Vout.

FIG.7Cis a third type of the sensing circuit and the readout circuit according to an embodiment of the disclosure. Referring toFIG.7C, the sensing circuits320,520and the readout circuits340,540of the above-mentioned embodiments ofFIG.3andFIG.5may be realized as the sensing circuit720C and the readout circuit740C of the voltage sensing circuit ofFIG.7C. In the embodiment of the disclosure, the sensing circuit720C includes a first sense transistor T1and a second sense transistor T2. The readout circuit740C may be composed of a bias voltage source741C, an operational amplifier742C, a capacitor743C and a switch744C to form a charge integrator to convert current to voltage. In the embodiment of the disclosure, the first sense transistor T1and the second sense transistor T2may be a N-type transistor, respectively, such as a N-type metal oxide semiconductor (NMOS). In the embodiment of the disclosure, the sensing circuit720C is a current mode sensing circuit, and the readout circuit740C is a current mode readout circuit.

In the embodiment of the disclosure, a first terminal of the first sense transistor T1is electrically connected to a sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A first terminal of the second sense transistor T2is electrically connected to a voltage (may have a low voltage level). A control terminal of the second sense transistor T2is electrically connected to a sensing node N1. A second terminal of the first sense transistor T1is electrically connected to a second terminal of the second sense transistor T2. A first terminal of the bias voltage source741C is electrically connected to a first input terminal of the operational amplifier742C. A second terminal of the bias voltage source741C is electrically connected to another voltage (may have the low voltage level). A second input terminal of the operational amplifier742C is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL. A first terminal of the capacitor743C is electrically connected to an output terminal of the operational amplifier742C. A second terminal of the capacitor743C is electrically connected to the second input terminal of the operational amplifier742C. A first terminal of the switch744C is electrically connected to an output terminal of the operational amplifier742C. A second terminal of the switch744C is electrically connected to the second input terminal of the operational amplifier742C.

In the embodiment of the disclosure, the second sense transistor T2may be operated as a current driver. When a voltage of the sensing node N1rises (during the above-mentioned test modes) and the first sense transistor T1is turned-on by the sense scan signal SE having a high voltage level, a current of the first terminal of the first sense transistor T1is correspondingly sink by the second sense transistor T2. Thus, a current corresponding to the voltage of the sensing node N1is formed to flow from the second input terminal of the operational amplifier742C to the first terminal of the first sense transistor T1through the sense data line SDL. Then, an output voltage Vout output by the output terminal of the operational amplifier742C is correspondingly pulled up to keep a voltage of the second terminal of the operational amplifier742C as same as a voltage of the first terminal of the operational amplifier742C through the capacitor743C. Therefore, the external processing circuit may effectively receive a sensing result of the voltage of the sensing node N1for calibration of the sensing circuit720C according to the output voltage Vout.

FIG.7Dis a fourth type of the sensing circuit and the readout circuit according to an embodiment of the disclosure. Referring toFIG.7D, the sensing circuits320,520and the readout circuits340,540of the above-mentioned embodiments ofFIG.3andFIG.5may be realized as the sensing circuit720D and the readout circuit740D of the voltage sensing circuit ofFIG.7D. In the embodiment of the disclosure, the sensing circuit720D includes a first sense transistor T1and a second sense transistor T2. The readout circuit740D may be composed of a capacitor743D and a switch744D to form a charge integrator to convert current to voltage. In the embodiment of the disclosure, the first sense transistor T1may be an N-type transistor, such as an N-type metal oxide semiconductor (NMOS), and the second sense transistor T2may be a P-type transistor, such as a P-type metal oxide semiconductor (PMOS). In the embodiment of the disclosure, the sensing circuit720D is an operational amplifier, and the readout circuit740D is a current mode readout circuit.

In the embodiment of the disclosure, a first terminal of the first sense transistor T1is electrically connected to a sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A first terminal of the second sense transistor T2is electrically connected to a voltage (may have a low voltage level). A control terminal of the second sense transistor T2is electrically connected to a sensing node N1. A second terminal of the first sense transistor T1is electrically connected to a second terminal of the second sense transistor T2. A first input terminal of the operational amplifier742D is electrically connected to another voltage (may have the low voltage level). A second input terminal of the operational amplifier742D is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL. A first terminal of the capacitor743D is electrically connected to an output terminal of the operational amplifier742D. A second terminal of the capacitor743D is electrically connected to the second input terminal of the operational amplifier742D. A first terminal of the switch744D is electrically connected to an output terminal of the operational amplifier742D. A second terminal of the switch744D is electrically connected to the second input terminal of the operational amplifier742D.

In the embodiment of the disclosure, the second sense transistor T2may be operated as a current driver. When a voltage of the sensing node N1drops (during the above-mentioned test modes) and the first sense transistor T1is turned-on by the sense scan signal SE having a high voltage level, a current flowing through the first terminal of the first sense transistor T1is correspondingly sourced from the second sense transistor T2. Thus, a current corresponding to the voltage of the sensing node N1is formed to flow from the first terminal of the first sense transistor T1to the second input terminal of the operational amplifier742D through the sense data line SDL. Then, an output voltage Vout output by the output terminal of the operational amplifier742D is correspondingly pulled down to keep a voltage of the second terminal of operational amplifier742D as same as a voltage of the first terminal of the operational amplifier742D through the capacitor743D. Therefore, the external processing circuit may effectively receive a sensing result of the voltage of the sensing node N1for calibration of the sensing circuit720D according to the output voltage Vout.

FIG.8Ais a schematic diagram of an electronic device according to an embodiment of the disclosure.FIG.8Bis a schematic diagram of a relationship between an output voltage and a test voltage according to an embodiment of the disclosure. Referring toFIG.8AandFIG.8B, an electronic device800includes an active matrix pixel array including a plurality of pixels, and a circuit architecture of at least one of the pixels may be the same as a pixel801ofFIG.8A. The electronic device800may be an active matrix sensing unit. In the embodiment of the disclosure, the electronic device800includes the pixel801, a readout circuit840, a sense data line SDL, a test line TL and a sense scan line SSL. The sense data line SDL may be electrically connected to multiple pixels in one column of the active matrix pixel array, respectively. The test line TL and the sense scan line SSL may be electrically connected to multiple pixels in one row of the active matrix pixel array, respectively. The pixel801includes an electronic unit810, a sensing circuit820and a test circuit830(corresponding to the circuit130ofFIG.1). The test circuit830includes a test transistor Tt.

In the embodiment of the disclosure, the sensing circuit820is electrically connected to the electronic unit810through a sensing node N1. The test circuit830is electrically connected to the sensing node N1. The sensing circuit820is electrically connected to the sense scan line SSL for receiving a sense scan signal, and is electrically connected to the sense data line SDL for providing a sense signal. The sense scan signal is used to control (enable) the sensing circuit820. The test circuit830is electrically connected to the test line TL for receiving a test control signal. A control terminal of the test transistor Tt is electrically connected to the test line TL. A first terminal of the test transistor Tt is electrically connected to the sensing node N1. A second terminal of the test transistor Tt is electrically connected to a common voltage source to receive a reset signal with the test voltage Vtest. The readout circuit840is electrically connected to the sense data line SDL for receiving the sense signal provided by the sensing circuit820. In addition, the test transistor Tt may be an N-type transistor, such as an N-type metal oxide semiconductor (NMOS). In other embodiments of the disclosure, the test transistor Tt may be a P-type transistor, such as a P-type metal oxide semiconductor (PMOS).

In the embodiment of the disclosure, the test transistor Tt may be turned-on to apply the test voltage Vtest to the electronic unit810through the sensing node N1. In the embodiment of the disclosure, the sensing circuit820and the test circuit830may perform a loop back calibration to sense the sensing node N1to generate the sense signal according to a voltage of the sensing node N1, so that the readout circuit840receives the sense signal from the sense data line SDL. The readout circuit840provides an output signal with an output voltage Vout to an external processing circuit according to the sense signal. In the embodiment of the disclosure, the test line TL may provide the different test voltages Vtest to the sensing node N1, so that the readout circuit840may correspondingly provide the output signal with different output voltages. Therefore, the external processing circuit may compare the test voltage Vtest and the output voltage Vout to obtain a calibration data corresponding a relationship between the output voltage Vout and the test voltage Vtest as shown inFIG.8B.

FIG.9is a schematic diagram of an electronic device according to an embodiment of the disclosure. Referring toFIG.9, an electronic device900includes an active matrix pixel array including a plurality of pixels, and a circuit architecture of at least one of the pixels may be the same as a pixel901. In the embodiment of the disclosure, the pixels of the electronic device900may be configured to sense light, and the electronic device900may be an active matrix sensor, such as a fingerprint sensor or an X-ray flat panel detector (FPD), but the disclosure is not limited thereto. In the embodiment of the disclosure, the electronic device900includes the pixel901, a readout circuit940and a sense data line SDL. There is a stray resistance R on the sense data line SDL. The pixel901includes a storage capacitor Cst, an electronic unit910, a (voltage) sensing circuit920and a reset circuit930(corresponding to the circuit130ofFIG.1). The readout circuit940may be composed of a bias current source941and a voltage amplifier942. The sensing circuit920includes a first sense transistor T1and a second sense transistor T2. The reset circuit930includes a reset transistor Tr (may be used as the test transistor Tt of embodiment ofFIG.8Ain a calibration mode). In the embodiment of the disclosure, the electronic unit910may be a photodiode, but the disclosure is not limited thereto.

In the embodiment of the disclosure, a first terminal (cathode) of the electronic unit910is electrically connected to a voltage V1. A second terminal (anode) of the electronic unit910is electrically connected to a sensing node N1. A first terminal of the reset transistor Tr is electrically connected to the sensing node N1. A second terminal of the reset transistor Tr is electrically connected to a reset voltage Vrst (may be used as the test voltage Vtest of embodiment ofFIG.8A). A control terminal of the reset transistor Tr receives a reset signal (may be used as the test control signal of embodiment ofFIG.8A). A first terminal of the storage capacitor Cst is electrically connected to the sensing node N1. A second terminal of the storage capacitor Cst may be electrically connected to a specific DC voltage (e.g. a ground voltage). A first terminal of the first sense transistor T1is electrically connected to the sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A first terminal of the second sense transistor T2is electrically connected to a voltage V2. A control terminal of the second sense transistor T2is electrically connected to the sensing node N1. A second terminal of the first sense transistor T1is electrically connected to a second terminal of the second sense transistor T2. A first terminal of the bias current source941is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R. A second terminal of the bias current source941is electrically connected to a voltage V3. An input terminal of the voltage amplifier942is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R. An output terminal of the voltage amplifier942may be electrically connected to an external processing circuit.

In the embodiment of the disclosure, the reset transistor Tr, the first sense transistor T1and the second sense transistor T2may be an N-type transistor, respectively, such as an N-type metal oxide semiconductor (NMOS). The above-mentioned first terminal and the second terminal of the transistor may include a drain terminal and a source terminal, respectively, and the above-mentioned control terminal of the transistor may be a gate terminal. In addition, in the embodiment of the disclosure, the voltage V1may be greater than the reset voltage Vrst, and the voltage V2may be greater than the voltage V3.

In the embodiment of the disclosure, the second sense transistor T2may be operated as a source follower amplifier. When a voltage of the sensing node N1rises and the first sense transistor T1is turned-on by the sense scan signal SE having a high voltage level, a voltage of the first terminal of the first sense transistor T1is correspondingly pulled-up by the second sense transistor T2. Thus, a current corresponding to the voltage of the sensing node N1is formed to flow from the first terminal of the first sense transistor T1to the bias current source941through the sense data line SDL. Then, the input terminal of the voltage amplifier942may receive the voltage of the first terminal of the first sense transistor T1, so that an output voltage Vout output by the output terminal of the voltage amplifier942is correspondingly pulled-up. Therefore, the external processing circuit may effectively receive a sensing result of the voltage of the sensing node N1for calibration of the sensing circuit920according to the output voltage Vout.

FIG.10is a schematic diagram of related signals and voltages of a normal mode according to the embodiment ofFIG.9of the disclosure. Referring toFIG.9andFIG.10, the electronic device900may be operated in a normal mode (i.e. the sensing mode) during a reset period RP to perform a reset operation, an expose period EP to perform an expose operation and a sense period SP to perform a sense operation.

During to the reset period RP from time t0to time t1, the reset transistor Tr is turned-on according to the reset signal RS having a high voltage level, and the first sense transistor T1is turned-off according to the sense scan signal SE having a low voltage level. Thus, a voltage V_N1of the sensing node N1may be changed to the reset voltage Vrst, and the output voltage Vout may be the voltage V3.

During to the expose period EP from time t2to time t3, the reset transistor Tr is turned-off according to the reset signal RS changing to the low voltage level, and the first sense transistor T1is turned-off according to the sense scan signal SE having the low voltage level. The electronic unit910may perform the expose operation. Thus, the voltage V_N1of the sensing node N1may be pulled-up by receiving a photo leak current from the electronic unit910. After time t3, the voltage V_N1of the sensing node N1may become a voltage of the reset voltage Vrst plus a first delta voltage dV1. It should be noted that, in the embodiment of the disclosure, the first delta voltage dV1may be caused by the photo leak current from the electronic unit910when the electronic unit910senses a target object. The first delta voltage dV1may correspond to an accurate sensing value of the target object.

During to sense period SP from time t4to time t6, the reset transistor Tr is turned-off according to the reset signal RS having the low voltage level, and the first sense transistor T1is turned-on according to the sense scan signal SE having the high voltage level. Thus, the sensing circuit920may sense the voltage V_N1of the sensing node N1, and the voltage amplifier942may correspondingly output the output voltage Vout as a sensing result to the external processing circuit. The output voltage Vout may be a voltage of the reset voltage Vrst plus the first delta voltage dV1, and minus a second delta voltage dV2. It should be noted that, in the embodiment of the disclosure, the second delta voltage dV2may be caused by a threshold voltage of the second sense transistor T2, the first sense transistor T1, the stray resistance R and the bias current source941.

FIG.11is a schematic diagram of related signals and voltages of a calibration mode according to the embodiment ofFIG.9of the disclosure. Referring toFIG.9andFIG.11, the electronic device900may be operated in a calibration mode during a calibration period CP to perform a loop back calibration. During the calibration period CP form time ta to time tb, the reset transistor Tr is turned-on according to the reset signal RS having the high voltage level, and the first sense transistor T1is turned-on according to the sense scan signal SE having the high voltage level. That is, the calibration mode of the electronic device900is activated when the reset transistor Tr and the first sense transistor T1are simultaneously turned-on. In the embodiment of the disclosure, the reset voltage Vrst may be used as a test voltage. The voltage V_N1of the sensing node N1may be changed to the reset voltage Vrst, and the output voltage Vout may be a voltage of the reset voltage Vrst minus a second delta voltage dV2. Thus, the external processing circuit may compare the reset voltage Vrst (i.e. test voltage) and the output voltage Vout to obtain a calibration data corresponding a relationship between the output voltage Vout and the reset voltage Vrst (i.e. test voltage) as shown inFIG.8B. Moreover, the external processing circuit may calculate the second delta voltage dV2by subtracting the output voltage Vout from the reset voltage Vrst. Therefore, the external processing circuit may effectively calibrate the above-mentioned sensing result to obtain the first delta voltage dV1representing the real sensing result.

FIG.12is a schematic diagram of an electronic device according to an embodiment of the disclosure. Referring toFIG.12, an electronic device1200includes an active matrix pixel array including a plurality of pixels, and a circuit architecture of at least one of the pixels may be the same as a pixel1201. In the embodiment of the disclosure, the pixels of the electronic device1200may be configured to sense light, and the electronic device1200may be an active matrix sensor, such as a fingerprint sensor or an X-ray flat panel detector (FPD), but the disclosure is not limited thereto. In the embodiment of the disclosure, the electronic device1200includes the pixel1201, a readout circuit1240and a sense data line SDL. There is a stray resistance R on the sense data line SDL. The pixel1201includes a storage capacitor Cst, an electronic unit1210, a (voltage) sensing circuit1220and a reset circuit1230. The readout circuit1240may be composed of a bias voltage source1241, an operational amplifier1242and a capacitor1243to form an charge integrator to convert current to voltage. The sensing circuit1220includes a first sense transistor T1and a second sense transistor T2. The reset circuit1230includes a reset transistor Tr (may be used as the test transistor Tt of embodiment ofFIG.8Ain a calibration mode). In the embodiment of the disclosure, the electronic unit1210may be a photodiode, but the disclosure is not limited thereto.

In the embodiment of the disclosure, a first terminal (cathode) of the electronic unit1210is electrically connected to a voltage V1. A second terminal (anode) of the electronic unit1210is electrically connected to a sensing node N1. A first terminal of the reset transistor Tr is electrically connected to the sensing node N1. A second terminal of the reset transistor Tr is electrically connected to a reset voltage Vrst (may be used as the test voltage Vtest of embodiment ofFIG.8A). A control terminal of the reset transistor Tr receives a reset signal (may be used as the test control signal of embodiment ofFIG.8A). A first terminal of the storage capacitor Cst is electrically connected to the sensing node N1. A second terminal of the storage capacitor Cst may be electrically connected to a specific DC voltage (e.g. a ground voltage). A first terminal of the first sense transistor T1is electrically connected to the sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A second terminal of the first sense transistor T1is electrically connected to a first terminal of the second sense transistor T2. A second terminal of the second sense transistor T2is electrically connected to a voltage V2. A control terminal of the second sense transistor T2is electrically connected to the sensing node N1. A first terminal of the bias voltage source1241is electrically connected to a first input terminal of the operational amplifier1242, and provides a voltage V3. A second terminal of the bias voltage source1241may be electrically connected to a specific DC voltage (e.g. a ground voltage). A second input terminal of the operational amplifier1242is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R. A second input terminal of the operational amplifier1242is electrically connected to an output terminal of the operational amplifier1242through the capacitor1243. An output terminal of the operational amplifier1242may be electrically connected to an external processing circuit.

In the embodiment of the disclosure, the reset transistor Tr, the first sense transistor T1and the second sense transistor T2may be an N-type transistor, respectively, such as an N-type metal oxide semiconductor (NMOS). The above-mentioned first terminal and the second terminal of the transistor may include a drain terminal and a source terminal, respectively, and the above-mentioned control terminal of the transistor may be a gate terminal. In addition, in the embodiment of the disclosure, the voltage V1may be greater than the reset voltage Vrst, and the voltage V3may be greater than the voltage V2.

In the embodiment of the disclosure, the second sense transistor T2may be operated as a current driver. When a voltage of the sensing node N1rises (during the above-mentioned test modes) and the first sense transistor T1is turned-on by the sense scan signal SE having a high voltage level, a current of the first terminal of the first sense transistor T1is correspondingly sink by the second sense transistor T2. Thus, a current corresponding to the voltage of the sensing node N1is formed to flow from the second terminal of the operational amplifier1242to the first terminal of the first sense transistor T1through the sense data line SDL. Then, an output voltage Vout output by the output terminal of the operational amplifier1242is correspondingly pulled up to keep a voltage of the second terminal of operational amplifier1242as same as a voltage of the first terminal of the operational amplifier1242through the capacitor1243. Therefore, the external processing circuit may effectively receive a sensing result of the voltage of the sensing node N1for calibration of the sensing circuit1220according to the output voltage Vout.

It should be noted that a normal mode (i.e. the sensing mode) and a calibration mode of electronic device1200may be implemented by analogy with the above-mentioned embodiments ofFIG.10andFIG.11, and thus will not be repeated here.

FIG.13is a schematic diagram of an electronic device according to an embodiment of the disclosure. Referring toFIG.13, an electronic device1300includes an active matrix pixel array including a plurality of pixels, and a circuit architecture of at least one of the pixels may be the same as a pixel1301. In the embodiment of the disclosure, the pixels of the electronic device1300may be configured to sense light, and the electronic device1300may be an active matrix sensor, such as a fingerprint sensor or an X-ray flat panel detector (FPD), but the disclosure is not limited thereto. In the embodiment of the disclosure, the electronic device1300includes the pixel1301, a readout circuit1340and a sense data line SDL. There is a stray resistance R on the sense data line SDL. The pixel1301includes a storage capacitor Cst, an electronic unit1310, a (voltage) sensing circuit1320and a reset circuit1330. The readout circuit1340may be composed of a bias current source1341and a voltage amplifier1342. The sensing circuit1320includes a first sense transistor T1and a second sense transistor T2. The reset circuit1330includes a reset transistor Tr (may be used as the test transistor Tt of embodiment ofFIG.8Ain a calibration mode). In the embodiment of the disclosure, the electronic unit1310may be a photodiode, but the disclosure is not limited thereto.

In the embodiment of the disclosure, a first terminal (cathode) of the electronic unit1310is electrically connected to a sensing node N1. A second terminal (anode) of the electronic unit1310is electrically connected to a voltage V1. A first terminal of the reset transistor Tr is electrically connected to a reset voltage Vrst (may be used as the test voltage Vtest of embodiment ofFIG.8A). A second terminal of the reset transistor Tr is electrically connected to the sensing node N1. A control terminal of the reset transistor Tr receives a reset signal (may be used as the test control signal of embodiment ofFIG.8A). A first terminal of the storage capacitor Cst is electrically connected to the sensing node N1. A second terminal of the storage capacitor Cst may be electrically connected to a specific DV voltage (e.g. a ground voltage). A first terminal of the first sense transistor T1is electrically connected to the sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A second terminal of the second sense transistor T2is electrically connected to a second terminal of the first sense transistor T1. A control terminal of the second sense transistor T2is electrically connected to the sensing node N1. A first terminal of the second sense transistor T2is electrically connected to a voltage V2. A first terminal of the bias current source1341is electrically connected to a voltage V3. A second terminal of the bias current source1341is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R. An input terminal of the voltage amplifier1342is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R. An output terminal of the voltage amplifier1342may be electrically connected to an external processing circuit.

In the embodiment of the disclosure, the reset transistor Tr and the first sense transistor T1may be a N-type transistor, such as a N-type metal oxide semiconductor (NMOS), and the second sense transistor T2may be a P-type transistor, such as a P-type metal oxide semiconductor (PMOS). The above-mentioned first terminal and the second terminal of the transistor may include a drain terminal and a source terminal, respectively, and the above-mentioned control terminal of the transistor may be a gate terminal. In addition, in the embodiment of the disclosure, the reset voltage Vrst may be greater than the voltage V1, and the voltage V3may be greater than the voltage V2.

In the embodiment of the disclosure, the second sense transistor T2may be operated as a source follower amplifier. When a voltage of the sensing node N1drops (during the above-mentioned test modes) and the first sense transistor T1is turned-on by the sense scan signal SE having a high voltage level, a voltage of the first terminal of the first sense transistor T1is correspondingly pulled-down by the second sense transistor T2. Thus, a current corresponding to the voltage of the sensing node N1is formed to flow from the bias current source1341to the first terminal of the first sense transistor T1through the sense data line SDL. Then, the input terminal of the voltage amplifier1342may receive the dropped voltage of the first terminal of the first sense transistor T1, so that an output voltage Vout output by the output terminal of the voltage amplifier1342is correspondingly pulled-down. Therefore, the external processing circuit may effectively receive a sensing result of the voltage of the sensing node N1for calibration of the sensing circuit1320according to the output voltage Vout.

It should be noted that a normal mode (i.e. the sensing mode) and a calibration mode of electronic device1300may be implemented by analogy with the above-mentioned embodiments ofFIG.10andFIG.11, and thus will not be repeated here.

FIG.14is a schematic diagram of an electronic device according to an embodiment of the disclosure. Referring toFIG.14, an electronic device1400includes an active matrix pixel array including a plurality of pixels, and a circuit architecture of at least one of the pixels may be the same as a pixel1401. In the embodiment of the disclosure, the pixels of the electronic device1400may be configured to sense light, and the electronic device1400may be an active matrix sensor, such as a fingerprint sensor or an X-ray flat panel detector (FPD), but the disclosure is not limited thereto. In the embodiment of the disclosure, the electronic device1400includes the pixel1401, a readout circuit1440and a sense data line SDL. There is a stray resistance R on the sense data line SDL. The pixel1401includes a storage capacitor Cst, an electronic unit1410, a (voltage) sensing circuit1420and a reset circuit1430. The readout circuit1440may be composed of an operational amplifier1442and a capacitor1443to form a charge integrator to convert current to voltage. The sensing circuit1420includes a first sense transistor T1and a second sense transistor T2. The reset circuit1430includes a reset transistor Tr (may be used as the test transistor Tt of embodiment ofFIG.8Ain a calibration mode). In the embodiment of the disclosure, the electronic unit1410may be a photodiode, but the disclosure is not limited thereto.

In the embodiment of the disclosure, a first terminal (cathode) of the electronic unit1210is electrically connected to a sensing node N1. A second terminal (anode) of the electronic unit1210is electrically connected to a voltage V1. A first terminal of the reset transistor Tr is electrically connected to a reset voltage Vrst (may be used as the test voltage Vtest of embodiment ofFIG.8A). A second terminal of the reset transistor Tr is electrically connected to the sensing node N1. A control terminal of the reset transistor Tr receives a reset signal (may be used as the test control signal of embodiment ofFIG.8A). A first terminal of the storage capacitor Cst is electrically connected to the sensing node N1. A second terminal of the storage capacitor Cst may be electrically connected to a specific DC voltage (e.g. a ground voltage). A first terminal of the first sense transistor T1is electrically connected to the sense data line SDL. A control terminal of the first sense transistor T1receives a sense scan signal SE. A second terminal of the second sense transistor T2is electrically connected to a voltage V2. A first terminal of the second sense transistor T2is electrically connected to a second terminal of the first sense transistor T2. A control terminal of the second sense transistor T2is electrically connected to the sensing node N1. A first input terminal of the operational amplifier1442is electrically connected to a voltage V3. A second input terminal of the operational amplifier1442is electrically connected to the first terminal of the first sense transistor T1through the sense data line SDL having the stray resistance R. A first terminal of the capacitor1443is electrically connected to an output terminal of the operational amplifier1442. A second terminal of the capacitor1443is electrically connected to the second input terminal of the operational amplifier1442. An output terminal of the operational amplifier1442may be electrically connected to an external processing circuit.

In the embodiment of the disclosure, the reset transistor Tr and the first sense transistor T1may be an N-type transistor, respectively, such as an N-type metal oxide semiconductor (NMOS), and the second sense transistor T2may be a P-type transistor, such as a P-type metal oxide semiconductor (PMOS). The above-mentioned first terminal and the second terminal of the transistor may include a drain terminal and a source terminal, respectively, and the above-mentioned control terminal of the transistor may be a gate terminal. In addition, in the embodiment of the disclosure, the reset voltage Vrst may be greater than the voltage V1, and the voltage V2may be greater than the voltage V3.

In the embodiment of the disclosure, the second sense transistor T2may be operated as a current driver. When a voltage of the sensing node N1drops (during the above-mentioned test modes) and the first sense transistor T1is turned-on by the sense scan signal SE having a high voltage level, a current flowing through the first terminal of the first sense transistor T1is correspondingly sourced from the second sense transistor T2. Thus, a current corresponding to the voltage of the sensing node N1is formed to flow from the first terminal of the first sense transistor T1to the second input terminal of the operational amplifier1442through the sense data line SDL. Then, an output voltage Vout output by the output terminal of the operational amplifier1442is correspondingly pulled down to keep a voltage of the second terminal of operational amplifier as same as a voltage of the first terminal of the operational amplifier through the capacitor. Therefore, the external processing circuit may effectively receive a sensing result of the voltage of the sensing node N1for calibration of the sensing circuit1420according to the output voltage Vout.

It should be noted that a normal mode (i.e. the sensing mode) and a calibration mode of electronic device1400may be implemented by analogy with the above-mentioned embodiments ofFIG.10andFIG.11, and thus will not be repeated here.

In summary, the electronic device of the disclosure can effectively calibrate the sensing circuit by means of the loop back calibration without any additional calibration instrument and calibration equipment.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.