Patent ID: 12211445

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, and thus, should not be limited to the embodiments set forth herein.

Like reference numerals may designate like elements throughout the specification.

It is to be understood that when one component is referred to as being “connected” or “coupled” to another component, it may be directly connected or coupled to the other component or another component may be located therebetween.

Singular forms are to include plural forms unless the context clearly indicates otherwise.

FIG.1illustrates a schematic block diagram of a display device according to an exemplary embodiment of the present invention.

The display device includes a display unit10, a scan driver20, a data driver30, a light emission driver40, a power supply50, and a signal controller60. The display device described herein with reference toFIG.1may include more or fewer constituent elements than those listed above.

The display unit10includes a plurality of pixels PX that are each connected to a corresponding one of a plurality of scan lines PS1to PSn, a corresponding one of a plurality of data lines D1to Dm, and a corresponding one of a plurality of light emission control lines EM1to EMn. Each of the plurality of pixels PX emits light according to a data signal transmitted thereto, and thus, the display unit10may display an image.

The plurality of scan lines PS1to PSn extend in a row direction and are substantially parallel to each other. The plurality of light emission control lines EM1to EMn extend in a row direction and are substantially parallel to each other. The plurality of data lines D1to Dm extend in a column direction and are substantially parallel to each other.

Each of the plurality of pixels PX receives power supply voltages ELVDD and ELVSS from the power supply50.

The scan driver20is connected to the display unit10through the plurality of scan lines PS1to PSn. The scan driver20generates a plurality of scan signals depending on a control signal CONT2and transmits them to a corresponding one of the plurality of scan lines PS1to PSn.

The control signal CONT2is an operational control signal of the scan driver20generated and transmitted by the signal controller60. The control signal CONT2may include a scan start signal, clock signals switching to a low level at different times, a holding control signal, and the like. The scan start signal is a signal for generating a first scan signal for displaying an image of one frame. The clock signals included in the control signal CONT2are synchronous signals for applying a scan signal to the plurality of scan lines PS1to PSn. The holding control signal is a signal for controlling the scan driver20so that the scan driver20does not output a scan signal while being driven at a low frequency.

The data driver30is connected to each pixel PX of the display unit10through the plurality of data lines D1to Dm. The data driver30receives an image data signal DATA and transmits a data signal to a corresponding one of the plurality of data lines D1to Dm depending on a control signal CONT1.

The control signal CONT1is an operational control signal of the data driver30generated and transmitted by the signal controller60.

The data driver30selects a gray voltage depending on the image data signal DATA and transmits the selected gray voltage to the plurality of data lines D1to Dm as a data signal. For example, the data driver30samples and holds the image data signal DATA inputted depending on the control signal CONT1and transmits the plurality of data signals to the plurality of data lines D1to Dm. The data driver30may apply a data signal having a predetermined voltage range to the plurality of data lines D1to Dm while a low level scan signal is applied.

The light emission driver40generates a plurality of light emission control signals depending on a control signal CONT3. The control signal CONT3may include a light emission start signal, light emission clock signals switching to a low level at different times, a holding control signal, and the like. The light emission start signal is a signal for generating a first light emission control signal for displaying an image of one frame. The clock signals included in the control signal CONT3are synchronous signals for applying a light emission control signal to the plurality of light emission control lines Em1to EMn. The holding control signal is a signal for controlling the light emission driver40so that the light emission driver40continuously outputs a light emission signal while being driven at a low frequency.

The signal controller60receives an input video signal (or image signal) IS inputted from the outside and an input control signal for controlling a display thereof. The image signal IS may include luminance information divided into grays of each of the pixels PX of the display unit10.

The input control signal transmitted to the signal controller60includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a main clock signal MCLK.

The signal controller60generates the control signals CONT1to CONT4and the image data signal DATA depending on the image signal IS, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync and the main clock signal MCLK.

The signal controller60appropriately processes the image signal IS according to an operation condition of the display unit10and the data driver30based on the inputted image signal IS and the input control signal. For example, the signal controller60may generate the image data signal DATA through an image processing process such as gamma correction and luminance compensation for the image signal IS.

For example, the signal controller60generates the control signal CONT1for controlling the operation of the data driver30and transmits the generated control signal CONT1to the data driver30together with the image data signal DATA in addition, the signal controller60transmits the control signal CONT2for controlling the operation of the scan driver20to the scan driver20. Further, the signal controller60may transmit the control signal CONT3to the light emission driver40to operate the light emission driver40.

The signal controller60may control the driving of the power supply50. The power supply50may supply the power supply voltages ELVDD and ELVSS for driving each pixel PX. For example, the signal controller60may transmit the control signal CONT4to the power supply50to drive the power supply50. The power supply50may be connected to a power supply line formed in the display unit10.

Next, the pixel of the display device will be described in detail with reference toFIG.2.

FIG.2illustrates a circuit diagram of the pixel included in the display device ofFIG.1.

Referring toFIG.2, a pixel PX1includes a first transistor T1, a second transistor T2, a third transistor3, a storage capacitor Cst, and an organic light emitting diode OLED.

In the pixel PX1, a gate of the first transistor T1is connected to one end of the storage capacitor Cst, a source of the first transistor T1is connected to the first power supply voltage ELVDD, and a drain of the first transistor T1is electrically connected to an anode of the organic light emitting diode OLED via the third transistor T3. The first transistor T1receives a data signal D[j] according to a switching operation of the second transistor T2and supplies a driving current to the organic light emitting diode OLED.

A gate of the second transistor T2is connected to a corresponding scan line PSi, a source of the second transistor T2is connected to a corresponding data line Dj, and a drain of the second transistor T2is connected to one end of the storage capacitor Cst together with the gate of the first transistor T1.

The second transistor T2is turned on according to a scan signal PS[i] to perform a switching operation of transmitting the data signal D[j] to one end of the storage capacitor Cst.

A gate of the third transistor T3is connected to a light emission control line a source of the third transistor T3is connected to the drain of the first transistor T1, and a drain of the third transistor T3is connected to the anode of the organic light emitting diode OLED.

The other end of the storage capacitor Cst is connected to the first power supply voltage ELVDD, and the cathode of the organic light emitting diode OLED is connected to the second power supply voltage ELVSS. Therefore, the organic light emitting diode OLED receives a driving current from the first transistor T1and emits light, so that the display device displays an image. The capacitor Cst charges a voltage corresponding to the data signal D[j] applied to the gate of the first transistor T1and maintains the voltage even after the second transistor T2is turned off.

Hereinafter, a low-frequency driving method will be described with reference toFIG.3.

As shown inFIG.3(a), the display device may display one frame during a predetermined period T1, thus, several (k) frames may be included in a predetermined period T2(T2=k*T1). For example, when the display device displays a motion picture, it is driven at a driving frequency 1/T1of 60 Hz, thereby displaying 60 frames during 1 second (T2).

Each frame may include a scan period S for writing a data signal to the pixel PX, and a light emission period E which is a period during which the pixel PX emits light depending on the data signal written to the pixel PX.

As shown inFIG.3(b), the display device may display one frame during a predetermined period T2. For example, when the display device displays a still image, it is driven at a driving frequency 1/T2of 1 Hz, thereby displaying one frame during 1 second (T2).

One frame may include a scan period S for writing a data signal to the pixel PX, and a light emission period E which is a period during which the pixel PX emits light depending on the data signal written to the pixel PX.

A length of the light emission period E may be a length excluding the scan period S in the period T2and the scan signals transmitted to the display unit10during the light emission period E may have a disable level, and the light emission control signals may have an enable level.

Hereinafter, a low-frequency driving method of the display device will be described in detail with reference toFIG.4.

FIG.4illustrates a timing chart of a low-frequency driving method of the display device ofFIG.1.

In one frame, a low level scan signal PS[1] is applied to a first scan line PS1during a period of t1to t2, and a low level scan signal PS[2] is applied to a second scan line PS2during a period of t2to t3. Similarly, low level scan signals are sequentially applied to third to (n−1)-th scan lines during a period of t3to t4, and a low level scan signal PS[n] is applied to the scan line PSn during a period of t4to t5.

After the scan signal PS[1] of a low level L is applied to the first scan line PS1during the period of t1to t2, a light emission control signal EM[1] of a low level L is applied to a corresponding light emission control line Em1at time t2. For example, the light emission control signal EM[1] of a high level H transitions to the low level L at the time t2.

After the scan signal PS[2] of a low level L is applied to the second scan line PS2during the period of t2to t3, a light emission control signal. EM[2] of a low level L is applied to a corresponding light emission control line EM2at time t3. For example, the light emission control signal. EM[2] of a high level H transitions to the low level L at the time t3.

After the scan signal PS[n] of the low level L is applied to the last scan line PSn during the period of t4to t5, a light emission control signal EM[n] of the low level L is applied to a corresponding light emission control line EMn at time t5. For example, the light emission control signal EM[n] of a high level H transitions to the low level L at the time t5.

After the light emission control signals of a low level are applied to all of the light emission control lines, a low level holding control signal BPC is applied at time t6. The low level holding control signal BPC is maintained until time t7before the light emission period ends.

The holding control signal BPC is a signal for controlling the scan driver20and the light emission driver40. For example, the holding control signal BPC is provided to the scan driver20and the light emission driver40so that the scan driver20applies the high level scan signal to the plurality of scan lines PS1to PSn and the light emission driver40applies the low level light emission control signal to the plurality of light emission control lines Em1to EMn. This will be described later with reference toFIG.5toFIG.9.

The light emission period of one frame ends at time t8. Thereafter, the scan signal PS[1] of the low level L is applied to the first scan line PS1again during a period of t9to t10thus a next frame is started.

Hereinafter, the scan driver20ofFIG.1will be described with reference toFIG.5toFIG.8.

FIG.5illustrates a schematic diagram of a scan driver according to an exemplary embodiment of the present invention.

Referring toFIG.5, the scan driver20includes a plurality of stages PST1to PSTn. Each of the plurality of stages PST1to PSTn is connected to a corresponding one of the scan lines PS1to PSn and is driven in synchronization with first and second clock signals CLK1and CLK2. The plurality of stages PST1to PSTn may have the same circuit structure.

Each of the plurality of stages PST1to PSTn receives an output signal (e.g., a scan signal) or a scan start signal PSSP of a previous stage. For example, the first stage PST1receives the scan start signal PSSP, and the remaining stages PST2to PSTn receive an output signal of a corresponding previous stage.

Each of the plurality of stages PST1to PSTn receives the first clock signal CLK1and the second clock signal CLK2. The first clock signal CLK1and the second clock signal CLK2have the same period, and their phases do not overlap each other. For example, when a period during which the scan signal is supplied to one scan line is one horizontal period (1H), each of the clock signals CLK1and CLK2may have a period of 2H, and may be switched to the low level L in a different horizontal period from each other.

FIG.6illustrates a circuit diagram as an example of a stage included in a scan driver according to an exemplary embodiment of the present invention. InFIG.6, although transistors are shown as P-type transistors, the present invention is not limited thereto. For example, the transistors may be N-type transistors.

Referring toFIG.6, one stage PST1includes a first driver210, a second driver220, an output unit230and a holding portion240.

The output unit230controls a level of the scan signal PS[1] supplied to an output terminal209in response to voltages applied to a first node N1and a second node N2. To accomplish this, the output unit230includes a fourth transistor PT4, a fifth transistor PT5a first capacitor C1, and a second capacitor C2.

The fourth transistor PT4is positioned between a first voltage VGH and the output terminal209, and a gate thereof is connected to the first node N1. The fourth transistor P14controls a connection between the first voltage VGH and the output terminal209in response to a voltage applied to the first node N1. In this case, the first voltage VGH is set to a high level, for example, a high-level voltage.

The fifth transistor PT5is positioned between the output terminal209and a second input terminal203, and a gate thereof is connected to the second node N2. The fifth transistor PT5controls a connection between the output terminal209and the second input terminal203in response to a voltage applied to the second node N2.

The first capacitor C1is connected between the second node N2and the output terminal209. The first capacitor C1charges voltages corresponding to the turning-on and turning-off of the fifth transistor PT5.

The second capacitor C2is connected between the first node N1and the first voltage VGH. The second capacitor C2charges a voltage applied to the first node N1.

The first driver210controls voltages of the second node N2and a third node N3in response to signals supplied to a first input terminal201to a third input terminal205. To accomplish this, the first driver210includes a first transistor PT1, a second transistor PT2and a third transistor PT3, and an eighth transistor PT8.

The first transistor PT1is positioned between the third input terminal205and the third node N3, and a gate thereof is connected to the first input terminal201. The first transistor PT1controls a connection between the third input terminal205and the third node N3in response to a voltage supplied to the first input terminal201.

A second transistor PT2and the third transistor PT3are connected in series between the third node N3and the first voltage VGH. For example, the second transistor PT2is positioned between the third transistor PT3and the third node N3, and a gate thereof is connected to the second input terminal203. The second transistor PT2controls a connection between the third transistor PT3and the third node N3in response to a voltage applied to the second input terminal203.

The third transistor PT3is positioned between the second transistor PT2and the first voltage VGH, and a gate thereof is connected to the first node N1. The third transistor PT3controls a connection between the second transistor PT2and the first voltage VGH in response to a voltage level of the first node N1.

The eighth transistor PT8is positioned between the second node N2and the third node N3, and a gate thereof is connected to a second voltage VGL. The eighth transistor PT8is turned on by the second voltage VGL to connect the second node N2and the third node N3to each other. In this case, the second voltage VGL is set to a low level, for example, a low-level voltage.

The second driver220controls a voltage of the first node N1in response to voltage levels of the first input terminal201and the third node N3. To accomplish this, the second driver220includes a sixth transistor PT6and a seventh transistor PT7.

The sixth transistor PT6is positioned between the first node N1and the first input terminal201, and a gate thereof is connected to the third node N3. The sixth transistor PT6controls a connection between the first node N1and the first input terminal201in response to a voltage level of the third node N3.

The seventh transistor PT7is positioned between the first node N1and the second voltage VGL, and a gate thereof is connected to the first input terminal201. The seventh transistor PT7controls a connection between the first node N1and the second voltage VGL in response to a voltage level of the first input terminal201.

The holding portion240controls a voltage of the first node N1in response to a signal supplied to a fourth input terminal207. To accomplish this, the holding portion240includes a ninth transistor PT9.

The ninth transistor PT9is positioned between the first node N1and the second voltage VGL and a gate thereof is connected to the fourth input terminal207. The ninth transistor PT9controls a connection between the first node N1and the second voltage VGL in response to a level of the holding control signal BPC supplied to the fourth input terminal207.

FIG.7illustrates a timing chart of a driving method of a scan driver according to an exemplary embodiment of the present invention.

Referring toFIG.7, the first clock signal CLK1and the second clock signal CLK2are switched to the low level L at different times (e.g., CLK1: ta1, ta5, ta9, etc., CLK2: ta3, ta7, ta11, etc.) at an interval of 1H. A low level scan start signal PSSP is supplied to be synchronized with the first clock signal CLK1supplied to the first input terminal201.

For example, when the first clock signal CLK1is switched to the low level L at time ta5, the scan start signal PSSP is switched to the low level L.

When the first clock signal CLK1of the low level L is supplied, the first transistor PT1and the seventh transistor PT7are turned on. When the first transistor PT1is turned on, the third input terminal205and the third node N3are electrically connected to each other. The third node N3is set to a low-level voltage by the scan start signal PSSP of the low level supplied to the third input terminal205. When the third node N3is set to the low-level voltage, the sixth transistor PT6is turned on.

In addition, the second node N2is also set to the low-level voltage through the turned-on eighth transistor PT8. When the second node N2is set to the low-level voltage, the fifth transistor PT5is turned on.

When the fifth transistor PT5is turned on, the second input terminal203and the output terminal209are electrically connected. In this case, since the second clock signal CLK2applied to the second input terminal203is the high level, the high level voltage is outputted to the output terminal209.

When the sixth transistor PT6is turned on, the first input terminal201and the first node N1are electrically connected. Then, the voltage of the first clock signal CLK1supplied to the first input terminal201, in other words, the low-level voltage is supplied to the first node N1. Additionally, the seventh transistor PT7is turned on in response to the first clock signal CLK1, so that the voltage of the second voltage VGL is supplied to the first node N1. In this case, the voltage of the second voltage VGL is set to the same voltage as (or a voltage similar to) the low level of the first clock signal CLK1, so that the first node N1stably maintains the low-level voltage.

When the low-level voltage is supplied to the first node N1, the fourth transistor PT4and the third transistor PT3are turned on. When the third transistor PT3is turned on, the first voltage VGH and the second transistor PT2are electrically connected. In this case, since the second transistor PT2is set to an off state, even though the third transistor PT3is turned on, the third node N3stably maintains the low-level voltage. When the fourth transistor PT4is turned on, the first voltage VGH is supplied to the output terminal209. In this case, the first voltage VGH is set to the same voltage as the high-level voltage supplied to the second input terminal203, so that the output terminal209stably maintains the high level.

At time ta6, the scan start signal PSSP and first clock signal CLK1are switched to the high level. Then, the first transistor PT1and the seventh transistor PT7are turned off. In this case, the fifth transistor PT5and the sixth transistor PT6maintain the turned-on state corresponding to a voltage stored in the first capacitor C1.

When the fifth transistor PT5maintains the turned-on state, the output terminal209and the second input terminal203maintain the electrically connected state. Accordingly, the output terminal209receives the high-level voltage from the second input terminal203.

In addition, since the sixth transistor PT6maintains the turned-on state, the first node N1and the first input terminal201are electrically connected. In this case, the voltage of the first input terminal201is set to the high-level voltage corresponding to the first clock signal CLK1of the high level, so that the first node N1is also set to the high-level voltage. When the high-level voltage is supplied to the first node N1, the fourth transistor PT4is turned off.

At time ta7, the second clock signal CLK2is switched to the low level. The second clock signal CLK2of the low level is supplied to the second input terminal203. In this case, since the fifth transistor PT5is set to the turned-on state, the second clock signal CLK2supplied to the second input terminal203is supplied to the output terminal209. In this case, the output terminal209outputs the second clock signal CLK2as the scan signal PS[1] to the scan line PS1. Furthermore, in the low level period (ta7to ta8) of the second clock signal CLK2, the voltage of the first node N1is a level L0which is lower than the low level L.

After the scan signal PS[1] is outputted to the scan line PS1, the first clock signal CLK1is switched to the low level at time ta9. When the first clock signal CLK1of the low level is supplied, the first transistor PT1and the seventh transistor PT7are turned on. When the first transistor PT1is turned on, the third input terminal205and the third node N3are electrically connected. In this case, the supplied scan start signal PSP is the high level, so that the third input terminal205is set to the high-level voltage. Accordingly, when the first transistor PT1is turned on, the high-level voltage is supplied to the third node N3, so that the fifth transistor PT5and the sixth transistor PT6are turned off.

When the seventh transistor PT7is turned on the second voltage VGL is supplied to the first node N1, so that the third transistor PT3and the fourth transistor PT4are turned on. When the fourth transistor PT4is turned on, the first voltage VGH is supplied to the output terminal209. Then, the fourth transistor PT4and the third transistor P13maintain the turned-on state corresponding to a voltage charged in the second capacitor C2, so that the output terminal209stably receives the first voltage VGH.

Additionally, when the second clock signal CLK2is switched to the low level at time ta11, the second transistor PT2is turned on. In this case, the third transistor PT3is set to the turned-on state, and the first voltage VGH is supplied to the third node N3. In this case, the fifth transistor PT5and the sixth transistor PT6stably maintain the off state.

The outputting of the low level scan signals PS[1] to PS[n] to the scan lines PS1to PSn is completed at time ta14. Then, at time ta15, the holding control signal BPC is switched to the low level. In this case, the first clock signal CLK1the second clock signal CLK2may stop clocking. In other words, the first clock signal CLK1and the second clock signal CLK2may maintain a high level.

When the holding control signal BPC is switched to the low level, since the second voltage VGL is supplied to the first node N1, the fourth transistor PT4is turned on. Then, the first voltage VGH is supplied to the output terminal209through the turned-on fourth transistor PT4. In other words, none of the stages PST1to PSTn of the scan driver20output the scan signals PS[1] to PS[n] of the low level. For example, the scan signals PS[1] to PS[n] are kept high.

Therefore, the scan driver20according to the present exemplary embodiment may stably maintain the scan signals PS[1] to PS[n] at the high level for a predetermined period for the low-frequency driving of the display device.

As can be gleaned, inFIG.7, the signal cycle of ta1to ta15repeats starting at ta16and proceeding at least through ta27.

FIG.8illustrates a circuit diagram as another example of a stage included in a scan driver according to an exemplary embodiment of the present invention.

As shown inFIG.8, a stage PST1′ includes the first to seventh transistors PT1to PT7, the ninth transistor PT9, the first capacitor C1, and the second capacitor C2, but not the eighth transistor P18, as compared with the stage PST1shown inFIG.6. Since a driving method of the stage PST1′ is about the same as the driving method ofFIG.7, a description thereof will be omitted.

In the stage PST1′ ofFIG.8, the holding control signal BPC is switched to the low level. Therefore, the second voltage VGL is supplied to the first node N1through the turned-on ninth transistor PT9such that the fourth transistor PT4is turned on. Then, the first voltage VGH is supplied to the output terminal209through the turned-on fourth transistor PT4. In other words, none of the stages PST1′ to PSTn′ of the scan driver20output the scan signal PS[1] to PS[n] of the low level.

Therefore, the scan driver20according to the present exemplary embodiment may maintain the scan signals PS[1] to PS[n] at the high level for a predetermined period for the low-frequency driving of the display device.

Hereinafter, the light emission driver40ofFIG.1will be described with reference toFIG.9toFIG.11.

FIG.9illustrates a schematic diagram of a light emission driver according to an exemplary embodiment of the present invention.

The light emission driver40includes the plurality of stages EST1to ESTn. Each of the plurality of stages EST1to ESTn is connected to a corresponding one of light emission control lines Em1to EMn, and is driven in synchronization with first and second clock signals ECLK1and ECLK2. The plurality of stages EST1to ESTn may have the same circuit structure.

The plurality of stages EST1to ESTn sequentially output light emission control signals. The light emission control signals overlap each other for a predetermined period when they are outputted.

Each of the plurality of stages EST1to ESTn receives an output signal (e.g., a light emission control signal) or a light emission start signal ESP of a previous stage. For example, the first stage EST1receives the light emission start signal ESP, and the remaining stages EST2to ESTn receive an output signal of a corresponding previous stage.

Each of the plurality of stages EST1to ESTn receives the first clock signal ECLK1and the second clock signal ECLK2. The first clock signal ECLK1and the second clock signal ECLK2have the same period, and their phases do not overlap each other.

FIG.10illustrates a circuit diagram as an example of a stage included in a light emission driver according to an exemplary embodiment of the present invention. InFIG.10, although transistors are shown as P-type transistors, the present invention is not limited thereto. For example, the transistors may be N-type transistors.

Referring toFIG.10, one stage EST1includes a first driver310, a second driver320, an output unit330, and a holding portion340.

The output unit330controls a level of the light emission control signal EM[1] supplied to an output terminal309in response to voltages applied to a first node N11and a second node N12. To accomplish this, the output unit330includes an eighth transistor ET8, a ninth transistor ET9, a tenth transistor ET10, and a third capacitor EC3.

The eighth transistor ET8is positioned between the first voltage VGH and the first node N11, and a gate thereof is connected to the second node N12. The eighth transistor ET8controls a connection between the first voltage VGH and the first node N11in response to a voltage applied to the second node N12. In this case, the first voltage VGH is set to a high level, for example, a high-level voltage.

The ninth transistor ET9is positioned between the first voltage VGH and the output terminal309, and a gate thereof is connected to the first node N11. The ninth transistor ET9controls a connection between the first voltage VGH and the output terminal309in response to a voltage applied to the first node N11.

The tenth transistor ET10is positioned between the output terminal309and the second voltage VGL, and a gate thereof is connected to the second node N12. The tenth transistor ET10controls a connection between the output terminal309and the second voltage VGL in response to a voltage applied to the second node N12. In this case, the second voltage VGL is set to the low level, for example, the low-level voltage.

The third capacitor EC3is connected between the first node N11and the first voltage VGH. The third capacitor EC3charges a voltage applied to the first node N11.

The first driver310controls voltages of the second node N12and the third node N13in response to signals supplied to a first input terminal301and a third input terminal305. To accomplish this, the first driver210includes a first transistor ET1to a third transistor ET3.

The first transistor ET1is positioned between the third input terminal305and the second node N12, and a gate thereof is connected to the first input terminal301. The first transistor ET1controls a connection between the third input terminal305and the second node N12in response to a voltage supplied to the first input terminal301.

A second transistor ET2is positioned between the third node N13and the first input terminal301, and a gate thereof is connected to the second node N12. The second transistor ET2controls a connection between the first input terminal301and the third node N13in response to a voltage level of the second node N12.

The third transistor ET3is positioned between the third node N13and the second voltage VGL, and a gate thereof is connected to the first input terminal301. The third transistor ET3controls a connection between the third node N13and the second voltage VGL in response to a voltage supplied to the first input terminal301.

The second driver320controls voltages of the first node N11, the second node N12, and a fourth node N14in response to voltage levels of a second input terminal303and the third node N13. To accomplish this, the second driver320includes a fourth transistor ET4, a fifth transistor ET5, a sixth transistor ET6, a seventh transistor ET7, a first capacitor EC1and a second capacitor EC2.

The fourth transistor ET4and the fifth transistor ET5are connected in series between the second node N12and the first voltage VGH. For example, the fourth transistor ET4is positioned between the fifth transistor ET5and the second node N12, and a gate thereof is connected to the second input terminal303. The fourth transistor ET4controls a connection between the fifth transistor ET5and the second node N12in response to a voltage supplied to the second input terminal303.

The fifth transistor ET5is positioned between the fourth transistor ET4and the first voltage VGH, and a gate thereof is connected to the third node N13. The fifth transistor ET5controls a connection between the fourth transistor ET4and the first voltage VGH in response to a voltage level of the third node N13.

The sixth transistor ET6is positioned between the fourth node N14and the second input terminal303, and a gate thereof is connected to the third node N13. The sixth transistor ET6controls a connection between the fourth node N14and the second input terminal303in response to a voltage level of the third node N13.

The seventh transistor ET7is positioned between the fourth node N14and the first node N11, and a gate thereof is connected to the second input terminal303. The seventh transistor ET7controls a connection between the fourth node N14and the first node N11in response to a voltage level of the second input terminal303.

The first capacitor EC1is connected between the second node N12and the second input terminal303, and the second capacitor EC2is connected between the first node N11and the fourth node N14.

The holding portion340controls a voltage of the second node N12in response to a signal supplied to a fourth input terminal307. To accomplish this, the holding portion340includes an eleventh transistor ET11.

The eleventh transistor ET11is positioned between the second node N12and the second voltage VGL, and a gate thereof is connected to the fourth input terminal307. The eleventh transistor ET11controls a connection between the second node N12and the second voltage VGL in response to a level of the holding control signal BPC supplied to the fourth input terminal307.

FIG.11illustrates a timing chart of a driving method of a light emission driver according to an exemplary embodiment of the present invention.

Referring toFIG.11, a first clock signal ECLK1and the second clock signal ECLK2are switched to the low levels L at different times (e.g., ECLK1: tb1, tb5, tb9, etc., ECLK2: tb3, tb7, tb11, etc.). A high level light emission start signal ESP is supplied to be synchronized with the first clock signal ECLK1supplied to the first input terminal301.

For example, when the first clock signal ECLK1is switched to the low level L at time tb1, the light emission start signal ESP is switched to the high level H. The light emission start signal ESP is provided only to the first stage EST1, and may maintain the high level for the period of time tb1to time tb9.

When the first clock signal ECLK1of the low level L is supplied, the first transistor ET1and the third transistor ET3are turned on.

When the first transistor ET1is turned on, the third input terminal305and the second node N12are electrically connected. The second node N12is set to the high-level voltage by the high level light emission start signal ESP supplied to the third input terminal305. When the second node N12is set to the high-level voltage, the second transistor ET2, the eighth transistor ET8, and the tenth transistor ET10are turned off.

When the third transistor ET3is turned on, the third node N13and the second voltage VGL are electrically connected, and thus, the second voltage VGL is supplied to the third node N13. In this case, the voltage of the second voltage VGL is set to the same voltage as (or a voltage similar to) the low level of the first clock signal ECLK1.

When the third node N13is set to the low-level voltage, the fifth transistor ET5and the sixth transistor ET6are turned on.

When the fifth transistor ET5is turned on, the first voltage VGH and the fourth transistor ET4are electrically connected. In this case, since the fourth transistor ET4is set to an off state, even though the fifth transistor ET5is turned on, the second node N12maintains the high level.

When the sixth transistor ET6is turned on, the second input terminal303and the fourth node N14are electrically connected. In this case, since the second clock signal ECLK2applied to the second input terminal303has the high level, the high-level voltage is also outputted to the fourth node N14.

The seventh transistor ET7is in an off state by the second clock signal ECLK2having the high level. The voltage of the first node N11maintains the high level by the third capacitor EC3. Since the voltage of the first node N11maintains the high level, the ninth transistor ET9is in the off state. Accordingly, the light emission control signal EM[1] maintains the low-level voltage.

At time tb3, the second clock signal ECLK2is switched to the low level. The light emission start signal ESP and the first clock signal ECLK1maintain the high level.

The first transistor ET1and the third transistor ET3are in the off state by the first clock signal ECLK1having the high level. Since the voltage of the second node N12maintains the high level, the second transistor ET2, the eighth transistor ET8, and the tenth transistor ET10are in the off state.

The second clock signal ECLK2of the low level is supplied to the second input terminal303. In this case, the fourth transistor ET4and the seventh transistor ET7are turned on. In addition, since the voltage of the third node N13is the low level, the fifth transistor ET5and the sixth transistor ET6are in an on state.

The voltage of the third node N13is bootstrapped by a potential change amount of the second clock signal ECLK2by the coupling of the second capacitor EC2. In other words, in the low level period (tb3to tb4) of the second clock signal ECLK2, the voltage of the third node N13is a level L2which is lower than the low level L in the low level period (tb11to tb12) of the second clock signal ECLK2, the voltage of the second node N12is a level L1which is lower than the low level L.

The second clock signal ECLK2having the low level is provided to the first node N11through the turned-on sixth and seventh transistors ET6and ET7. Accordingly, at time tb3, the voltage of the first node N11is the low level. Since the voltage of the first node N11is the low level, the ninth transistor ET9is turned on.

Since the ninth transistor ET9is turned on and the tenth transistor ET10is in the off state, the light emission control signal EM[1] is switched to the high level.

At time tb9, the first dock signal ECLK1is switched to the low level, and the light emission start signal ESP is switched to the low level. The second clock signal ECLK2maintains the high level.

The first clock signal ECLK1having the low level is provided to the gate of the first transistor ET1and the gate of the third transistor ET3. Accordingly, the first transistor ET1and the third transistor ET3are turned on.

The light emission start signal ESP having the low level is provided to the gate of the second transistor ET2and the second node N12through the turned-on first transistor ET1. Accordingly, the voltage of the second node N12is the low level, and the second transistor ET2is turned on.

The first clock signal ECLK1having the low level is provided to the third node N13through the turned-on second transistor ET2, and the first voltage VGL is provided to the third node N13through the turned-on third transistor ET3. Accordingly, the voltage of the third node N13is the low level.

The second clock signal ECLK2having the high level is provided to the fourth transistor ET4and the seventh transistor ET7. Accordingly, the fourth and seventh transistors ET4and ET7are in the off state.

Since the voltage of the second node N12is the low level, the eighth transistor ET8is turned on. The first voltage VGH is provided to the first node N11through the turned-on eighth transistor ET8. Accordingly, the voltage of the first node N11is the high level. Since the voltage of the first node N11is the high level, the ninth transistor ET9is turned off.

Since the voltage of the second node N12is the low level, the tenth transistor ET10is turned on. The second voltage VGL is provided to the output terminal309by the turned-on tenth transistor ET10. Accordingly, the first light emission control signal EM[1] has the low level.

At time tb19, the output of the scan signal EM[n] of the low level is started from the last stage ESTn to the light emission control line EMn. Then, at time tb21, the holding control signal BPC is switched to the low level. In this case, the first clock signal ECLK1and the second clock signal ECLK2may stop clocking. For example, the first dock signal ECLK1may be kept high and the second clock signal ECLK2may be kept high. Time tb21ofFIG.11may correspond to time ta15ofFIG.7.

When the holding control signal BPC is switched to the low level, since the second voltage VGI, is supplied to the second node N12, the tenth transistor ET10is turned on. Then, the second voltage VGL is supplied to the output terminal309through the turned-on tenth transistor ET10. In other words, all of the stages EST1to ESTn of the light emission driver40maintain the outputs of the low level light emission control signals EM[1] to EM[n].

Therefore, the light emission driver40according to the present exemplary embodiment may stably maintain the light emission control signals EM[1] to EM[n] at the low level for a predetermined period for the low-frequency driving of the display device.

As can be gleaned, inFIG.11, the signal cycle of tb1to tb21repeats starting at tb22and proceeding at least through tb27.

Hereinafter, a display device according to another exemplary embodiment of the present invention will be described with reference toFIG.12toFIG.17.

FIG.12illustrates a schematic block diagram of a display device according to another exemplary embodiment of the present invention.

The display device includes a display unit11, a first scan driver21, a second scan driver22, a data driver31, a light emission driver41, a power supply51, and a signal controller61. The display device described herein with reference toFIG.12may include more or fewer elements than those listed above.

Descriptions of the same or similar elements to those of the display device ofFIG.1among the elements of the display device shown inFIG.12may be omitted.

The display unit11includes a plurality of pixels PX that are each connected to a corresponding one of the plurality of first scan lines PS0to PSn, a corresponding one of the plurality of second scan lines NS0to NSn, a corresponding one of the plurality of data lines D1to Dm, and a corresponding one of a plurality of light emission control lines EM1to EMn. Each of the plurality of pixels PX emits light according to a data signal transmitted thereto, and thus, the display unit11may display an image.

A plurality of first scan lines PS0to PSn extend in a row direction and are substantially parallel to each other. A plurality of second scan lines NS0to NSn extend in a row direction and are substantially parallel to each other. The plurality of light emission control lines EM1to EMn extend in a row direction and are substantially parallel to each other. The plurality of data lines D1to Dm extend in a column direction and are substantially parallel to each other.

Each of the plurality of pixels PX receives an initialization voltage Vint and the power supply voltages ELVDD and ELVSS from the power supply51.

The second scan driver22is connected to the display unit11through the plurality of second scan lines NS0to NSn. The second scan driver22generates a plurality of scan signals depending on the control signal CONT12and transmits them to a corresponding one of the plurality of scan lines PS0to PSn.

The signal controller61receives an input video signal (or image signal) IS inputted from the outside and an input control signal for controlling display thereof. The signal controller61generates control signals CONT11to CONT15and the image data signal DATA depending on the image signal IS, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the main clock signal MCLK.

The signal controller61may control the driving of the power supply51. The power supply51may supply the initialization voltage Vint for initializing a gate of a first transistor included in each pixel PX of the display unit11and an anode of an organic light emitting diode to a predetermined voltage. In addition, the power supply51may provide the power supply voltages ELVDD and ELVSS for driving each pixel PX. For example, the signal controller61may transmit the control signal CONT15to the power supply51to drive the power supply51. The power supply51may be connected to a power supply line formed in the display unit11.

Hereinafter, the pixel of the display device will be described in detail with reference toFIG.13.

FIG.13illustrates a circuit diagram of a pixel included in the display device ofFIG.12.

Referring toFIG.13, a pixel PX2of a display device according to another exemplary embodiment of the present invention includes first to seventh transistors T11, T12, T13, T14, T15, T16, and T17, a storage capacitor Cst, and an organic light emitting diode OLED.

In the pixel PX2, a gate of the first transistor T11is connected to one end of the storage capacitor Cst, a source of the first transistor T11is connected to the first power supply voltage ELVDD via the fifth transistor T15, and a drain of the first transistor T11is electrically connected to an anode of the organic light emitting diode OLED via the sixth transistor T16. The first transistor T11receives the data signal D[j] according to a switching operation of the second transistor T12to supply a driving current to the organic light emitting diode OLED.

A gate of the second transistor T12is connected to a corresponding first scan line PSi, a source of the second transistor T12is connected to a corresponding data line Dj, and a drain of the second transistor T12is connected to the source of the first transistor T11and is connected to the first power supply voltage ELVDD via the fifth transistor T15.

The second transistor T12performs a switching operation in which the second transistor T12is turned on depending on the scan signal PS[i] to transmit the data signal D[j] to the source of the first transistor T11.

A gate of the third transistor T13is connected to a corresponding second scan line NSi, a source of the third transistor T13is connected to the drain of the first transistor T11and is connected to the anode of the organic light emitting diode OLED via the sixth transistor T16, and a drain of the third transistor T13is connected to one end of the storage capacitor Cst, a source of the fourth transistor T14, and the gate of the first transistor T11.

The third transistor T13is turned on depending on the second scan signal NS[i] received through the corresponding second scan line NSi to connect the gate and the drain of the first transistor T11to each other, thereby diode-connecting the first transistor T11.

A gate of the fourth transistor T14is connected to a previous second scan line NSi−1, drain of the fourth transistor114is connected to the initialization voltage Vint, and the source of the fourth transistor T14is connected to the drain of the third transistor T13.

The fourth transistor T14is turned on depending on a scan signal NS[i−1] received through the previous second scan line NSi−1 to transmit the initialization voltage Vint to the gate of the first transistor T11, thus an operation for initializing a voltage of the gate of the first transistor T11is performed.

A gate of the fifth transistor T15is connected to a corresponding light emission control line EMi, a source of the fifth transistor T15is connected to the first power supply voltage ELVDD, and a drain of the fifth transistor T15is connected to the source of the first transistor T11and the drain of the second transistor T12.

A gate of the sixth transistor T16is connected to the corresponding light emission control line EMi, a source of the sixth transistor T16is connected to the drain of the first transistor T11and the source of the third transistor T13, and a drain of the sixth transistor T16is connected to the anode of the organic light emitting diode OLED and the source of the seventh transistor T17.

The fifth transistor T15and the sixth transistor T16are simultaneously turned on depending on the light emission control signal EM[i] received through the light emission control line Emi. In this case, a driving current flows through the organic light emitting diode OLED by the first power supply voltage ELVDD and the voltage stored in the storage capacitor Cst.

A gate of the seventh transistor T17is connected to a previous first scan line (PSi−1), a drain of the seventh transistor T17is connected to the initialization voltage Vint, and a source of the seventh transistor T17is connected to the anode of the organic light emitting diode OLED and the drain of the sixth transistor T16.

The seventh transistor T17is turned on depending on a scan signal PS[i−1] received through the previous first scan line PSi−1. In this case, the seventh transistor T17performs an operation for initializing a voltage of the anode of the organic light emitting diode OLED with the initialization voltage Vint.

The other end of the storage capacitor Cst is connected to the first power supply voltage ELVDD, and the cathode of the organic light emitting diode OLED is connected to the second power supply voltage ELVSS. Accordingly, the organic light emitting diode OLED receives a driving current from the first transistor T11to emit light, so that the display device displays an image.

The pixel PX2includes an oxide semiconductor thin film transistor and a low temperature poly silicon (LTPS) thin film transistor.

The oxide semiconductor thin film transistor includes a gate, a source, and a drain. The oxide semiconductor thin film transistor includes an active layer made of an oxide semiconductor. Herein, the oxide semiconductor may include an amorphous or crystalline oxide semiconductor. The oxide semiconductor thin film transistor may be an N-type transistor.

The LTPS thin film transistor includes a gate, a source, and a drain. The LTPS thin film transistor includes an active layer made of polysilicon. The LTPS thin film transistor may be a P-type or N-type thin film transistor. In the present exemplary embodiment, the LTPS thin film transistor is a P-type transistor.

The LTPS thin film transistor has high electron mobility and thus a fast driving characteristic.

The oxide semiconductor thin film transistor may be manufactured by a low temperature process, and it has lower charge mobility than the LTPS thin film transistor. The oxide semiconductor thin film transistor has an excellent off-current characteristic.

The first transistor T11, the second transistor T12, the fifth transistor115, the sixth transistor T16, and the seventh transistor T17may be P-type LTPS thin film transistors, and the third transistor T13and the fourth transistor T14may be N-type oxide semiconductor thin film transistors.

In the present exemplary embodiment, when the third transistor T13and the fourth transistor T14connected to the second node NA2are the oxide semiconductor thin film transistors, a leakage current from the second node NA2is minimized, thus an image with a desired luminance may be displayed.

In addition, in the present exemplary embodiment, the first transistor T11, the sixth transistor T16, and the seventh transistor T17, which are positioned at a current supply path for supplying a current to the organic light emitting diode OLED, are the LTPS thin film transistors. When the first, sixth and seventh transistors T11, T16, and T17positioned at the current supply path are the LTPS thin film transistors, a current may be stably supplied to the organic light emitting diode OLED by fast driving characteristics thereof.

Hereinafter, a low-frequency driving method of the display device ofFIG.12will be described in detail with reference toFIG.14.

FIG.14illustrates a timing chart of the low-frequency driving method of the display device ofFIG.12.

In one frame, during a period of t0to t1, a low-level first scan signal PS[0] is applied to a dummy first scan line PS0, and a high-level second scan signal NS[0] is applied to a dummy second scan line NS0. During a period of t1to t2, the low-level first scan signal PS[1] is applied to the first-first scan line PS1, and the high-level second scan signal NS[1] is applied to the first-second scan line NS1. Similarly, the low-level first scan signals are sequentially applied to the second to (n−1)-th first scan lines PS2to PSn−1, and the low-level second scan signals are sequentially applied to the second to (n−1)-th second scan lines NS2to NSn−1. During a period of t4to t5, the low-level first scan signal PS[n] is applied to the n-th first scan line PSn, and the high-level second scan signal NS[n] is applied to the n-th second scan line NSn.

After the first the scan signal PS[1] of the low level L and the second scan signal NS[1] of the high level11are respectively applied to the first-first scan line PS1and the first-second scan line NS1during the period of t1to t2, the light emission control signal EM[1] of the low level L is applied to a corresponding light emission control line Em1at time t2.

After the first scan signal PS[2] of the low level L and the second scan signal NS[2] of the high level H are respectively applied to the second-first scan line PS2and the second-second scan line NS2during a period of t2to t3, the light emission control signal EM[2] of the low level L is applied to a corresponding light emission control line EM2at time t3.

After the first scan signal PS[n] of the low level L and the second scan signal NS[n] of the high level H are respectively applied to the last-first scan line PSn and the last-second scan line NSn during the period of t4to t5, the light emission control signal EM[n] of the low level L is applied to a corresponding light emission control line EMn at time t5.

After the low level light emission control signals EM[1] to EM[n] are applied to all of the light emission control lines Em1to EMn, the low level holding control signal BPC is applied at time t6. The low level holding control signal BPC is maintained until time t7before the light emission period ends.

The holding control signal BPC is a signal for controlling the first and second scan drivers21and22and the light emission driver41, and is provided to the first and second scan drivers21and22and the light emission driver41so that the first scan driver21applies the high level first scan signal to the plurality of scan lines PS1to PSn, the second scan driver22applies the low-level second scan signal to the plurality of scan lines NS1to NSn, and the light emission driver41applies the low level light emission control signal to the plurality of light emission control lines EM1to EMn.

Next, the light emission period of one frame ends at time t8. During a subsequent period of t9to t10, the first scan signal PS[0] of the low level L and the second scan signal NS[0] of the high level H are respectively applied to the dummy first scan line PS0and the dummy second scan line NS0again, and thereby a next frame is started and proceeds at least to t13.

Hereinafter, the second scan driver22ofFIG.12will be described with reference toFIG.15toFIG.18.

FIG.15illustrates a schematic diagram of a scan driver according to another exemplary embodiment of the present invention, andFIG.16illustrates a circuit diagram of a stage included in a scan driver according to another exemplary embodiment of the present invention.

Referring toFIG.15, the second scan driver22includes a plurality of stages NST0to NSTn. Each of the plurality of stages NST0to NSTn is connected to a corresponding one of scan lines NS0to NSn and is driven in synchronization with clock signals ECLK1, ECLK2, and NCLK. The plurality of stages NST0to NSTn may have the same circuit structure.

Each of the plurality of stages NST0to NSTn receives an output signal of a previous stage (e.g., a second scan signal) or a second scan start signal NSSP. For example, the first stage NST0receives the second scan start signal NSSP, and the remaining stages NST1to NSTn receive an output signal of a corresponding previous stage.

Each of the plurality of stages NST0to NSTn receives the first clock signal ECLK1and the second clock signal ECLK2. The first clock signal ECLK1and the second clock signal ECLK2have the same period, and their phases do not overlap each other.

The plurality of stages NST0to NSTn receive the scan clock signal NCLK. The scan clock signal NCLK has a period different from the first clock signal ECLK1and the second clock signal ECLK2. When a period during which the scan signal is supplied to one scan line NS0is one horizontal period (1H), the scan clock signal NCLK may have a period of 1H, and may be switched to the high level L.

Referring toFIG.16, one stage NST0includes a first driver410, a second driver420, an output unit430, and a holding portion440. InFIG.16, although transistors are shown as P-type transistors, the present invention is not limited thereto. For example, the transistors may be N-type transistors.

The output unit330controls a level of the scan signal NS[0] supplied to an output terminal409in response to a voltage applied to a first node N21and a second node N22. To accomplish this, the output unit430includes an eighth transistor NT8, a ninth transistor NT9, tenth transistor NT10, and a third capacitor NC3.

The eighth transistor NT8is positioned between the fourth input terminal407provided with the scan clock signal NCLK and the first node N21, and a gate thereof is connected to the second node N22. The eighth transistor NT8controls a connection between the fourth input terminal407and the first node N21in response to a voltage applied to the second node N22.

The ninth transistor NT9is positioned between the fourth input terminal407and the output terminal409, and a gate thereof is connected to the first node N21The ninth transistor NT9controls a connection between the fourth input terminal407and the output terminal409in response to a voltage applied to the first node N21.

The tenth transistor NT10is positioned between the output terminal409and the second voltage VGL, and a gate thereof is connected to the second node N22. The tenth transistor NT10controls a connection between the output terminal409and the second voltage VGL in response to a voltage applied to the second node N22. In this case, the second voltage VGL is set to a low level, for example, a low-level voltage.

The third capacitor NC3is connected between the first node N21and the first voltage VGH. The third capacitor NC3is charged with a voltage applied to the first node N21.

The first driver410controls voltages of the second node N22and the third node N23in response to signals supplied to a second input terminal403, a third input terminal405, and a fourth input terminal407. To accomplish this, the first driver410includes an eleventh transistor NT11, and a first transistor NT1to a third transistor NT3.

The eleventh transistor NT11is positioned between the third input terminal405and the first transistor NT1, and a gate thereof is connected to the fourth input terminal407. The eleventh transistor NT11controls a connection between the third input terminal405and the first transistor NT1in response to a voltage supplied to the fourth input terminal407.

The first transistor NT1is positioned between the eleventh transistor NT11and the second node N22, and a gate thereof is connected to the second input terminal403. The first transistor NT1controls a connection between the eleventh transistor NT11and the second node N22in response to a voltage supplied to the second input terminal403.

In other words, the eleventh transistor NT11and the first transistor NT1may transmit the second scan start signal NSSP to the second node N22depending on the levels of the scan clock signal NCLK and the second clock signal ELCK2.

The second transistor NT2is positioned between the third node N23and the second input terminal403, and a gate thereof is connected to the second node N22. The second transistor NT2controls a connection between the second input terminal403and the third node N23in response to a voltage level of the second node N22.

The third transistor NT3is positioned between the third node N23and the second voltage VGL, and a gate thereof is connected to the second input terminal403. The third transistor NT3controls a connection between the third node N23and the second voltage VGL in response to a voltage supplied to the second input terminal403.

The second driver420controls voltages of the first node N21, the second node N22, and a fourth node N24in response to voltage levels of a first input terminal401and the second node N22. To accomplish this, the second driver420includes a fourth transistor NT4, a fifth transistor NT5, a sixth transistor NT6, a seventh transistor NT7, a first capacitor NC1, and a second capacitor NC2.

The fourth transistor NT4is positioned between the first input terminal401and the fifth transistor NT5, and a gate thereof is connected to the second node N22. The fourth transistor NT4controls a connection between the fifth transistor NT5and the first input terminal401in response to a voltage level of the second node N22.

The fifth transistor NT5is positioned between the fourth transistor NT4and the first voltage VGH, and a gate thereof is connected to the third node N23. The fifth transistor NT5controls a connection between the fourth transistor NT4and the first voltage VGH in response to a voltage level of the third node N23.

The sixth transistor NT6is positioned between the fourth node N24and the first input terminal401, and a gate thereof is connected to the third node N23. The sixth transistor NT6controls a connection between the fourth node N24and the first input terminal401in response to a voltage level of the third node N23.

The seventh transistor NT7is positioned between the fourth node N24and the first node N21, and a gate thereof is connected to the first input terminal401. The seventh transistor NT7controls a connection between the fourth node N24and the first node N21in response to a voltage level of the first input terminal401.

The first capacitor NC1is connected to a node between the fourth transistor NT4and the fifth transistor NT5and to the second node N22, and the second capacitor NC2is connected to a node between the fifth transistor NT5and the sixth transistor NT6and to the fourth node N24.

The holding portion440controls a voltage of the second node N22in response to a signal supplied to a fifth input terminal411. To accomplish this, the holding portion440includes a twelfth transistor NT12.

The twelfth transistor NT12is positioned between the second node N22and the second voltage VGL, and a gate thereof is connected to the fifth input terminal411. The twelfth transistor NT12controls a connection between the second node N22and the second voltage VGL in response to a level of the holding control signal BPC supplied to the fifth input terminal411.

FIG.17illustrates a timing chart of a driving method of a scan driver according to another exemplary embodiment of the present invention.

Referring toFIG.17, the first clock signal ECLK1and the second clock signal ECLK2are switched to the low level L at different times (e.g., ECLK1: tc1, tc5, tc9, etc., ECLK2: tc3, tc7, tc11, etc). The high level second scan start signal NSSP is supplied to be synchronized with the first clock signal ECLK1supplied to the first input terminal401.

For example, the first clock signal ECLK1is switched to the low level at time tc1the second scan start signal NSSP and the scan clock signal NCLK maintain the low level, and the second dock signal ECLK2maintains the high level. In addition, the voltages of the first node N21and the second node N22have the low level.

Since the voltage of the second node N22is the low level, the second transistor NT2, the fourth transistor NT4, the eighth transistor NT8, and the tenth transistor NT10are in the on state.

The high level second clock signal ECLK2is provided to the third node N23by the second transistor NT2of the on state. In other words, the voltage of the third node N23is the high level H.

The second voltage VGL is supplied to the output terminal409by the tenth transistor NT10of the on state. The stage NST0of the scan driver22outputs the low-level second scan signal NS[0].

The low level scan clock signal NCLK is supplied to the first node N21by the eighth transistor NT8of the on state. The voltage of the first node N21stably maintains the low level.

Since the voltage of the first node N21is the low level, the ninth transistor NT9is in the on state. The low level scan clock signal NCLK is supplied to the output terminal409by the ninth transistor NT9of the on state. The stage NST0of the scan driver22stably outputs the low-level second scan signal NS[0].

During a period of tc1to tc2, the low-level first clock signal ECLK1is supplied to the first input terminal401. The voltage of one end of the first capacitor NC1is changed by a potential change amount of the first clock signal ECLK1by the fourth transistor NT4of the on state. The voltage of the second node N22is bootstrapped by the potential change amount of the first clock signal ECLK1by coupling of the first capacitor NC1. In other words, in the low level period (tc1to tc2) of the first clock signal ECLK1, the voltage of the second node N22is a level L4which is lower than the low level L.

The seventh transistor NT7is turned on by the low-level first clock signal ECLK1. The first node N21and the fourth node N24are electrically connected by the turned-on seventh transistor NT7. Since the voltage of the first node N21is the low level, the voltage of the fourth node N24is the low level.

Then, the second capacitor NC2charges a voltage difference between the third node N23of the high level H and the fourth node N24of the low level.

At time tc3, the second clock signal ECLK2is switched to the low level L. The scan clock sig al NCLK maintains the low level, and the first clock signal ECLK1maintains the high level.

Before the second clock signal ECLK2is switched to the low level L, the second scan start signal NSSP is switched to the high level H. The second scan start signal NSSP is provided only to the first stage NST0, which may maintain the high level within a period of tc3to about tc7. The first clock signal ECLK1maintains the high level to tc5.

The eleventh transistor NT11is in the on state by the scan clock signal NCLK of the low level L. When the second clock signal ECLK2of the low level L is supplied, the first transistor NT1and the third transistor NT3are turned on. Then, the second scan start signal NSSP of the high level H is provided to the second node N22through the turned-on first transistor NT1, and the second voltage VGL is supplied to the third node N23through the turned-on third transistor NT3. Accordingly, the voltage of the second node N22is the high level, and the voltage of the third node N23is the low level.

Since the voltage of the third node N23is the low level, the fifth transistor NT5and the sixth transistor NT6are turned on. Since the first voltage VGH is provided to one end of the first capacitor NC1connected to the fourth transistor NT4through the turned-on fifth transistor NT5, the high level voltage is applied to opposite ends of the first capacitor NC1to be discharged.

The first clock signal ECLK1of the high level H is provided to the fourth node N24through the turned-on sixth transistor NT6. Then, the second capacitor NC2charges a voltage difference between the first clock signal ECLK1of the high level H and the third node N23of the low level.

At time tc5, the first clock signal ECLK1is switched to the low level L. The first clock signal ECLK1and the second scan start signal NSSP maintain the high level.

Before the first clock signal ECLK1is switched to the low level L, the scan clock signal NCLK is switched to the high level H. The scan clock signal NCLK may maintain the high level within a period tc5to about tc9.

The eleventh transistor NT11is turned off by the scan clock signal NCLK having the high level.

In addition, before the first clock signal ECLK1is switched to the low level L, the voltage of the second node N22is the high level, and the voltage of the third node N23is the low level.

Since the voltage of the second node N22is the high level, the second transistor NT2, the fourth transistor NT4, the eighth transistor NT8, and the tenth transistor NT10are in the off state.

Since the voltage of the third node N23is the low level, the fifth transistor NT5and the sixth transistor NT6are in the on state.

The first voltage VGH is provided to one end of the first capacitor NC1connected to the fourth transistor NT4through the fifth transistor NT5of the on state.

The voltage of one end of the second capacitor NC2is changed by a potential change amount of the first clock signal ECLK1by the sixth transistor NT6of the on state. The voltage of the third node N23is bootstrapped by the potential change amount of the first clock signal ECLK1by the coupling of the second capacitor NC2. In other words, in the low level period (tc5to tc6) of the first clock signal ECLK1the voltage of the third node N23is a level L5which is lower than the low level L.

In addition, the low-level first clock signal ECLK1is provided to the fourth node N24by the sixth transistor NT6of the on state.

The seventh transistor NT7is turned on by the low-level first clock signal ECLK1. The fourth node N24and the first node N21are electrically connected by the turned-on seventh transistor NT7.

Since the voltage of the fourth node N24is the low level, the voltage of the first node N21maintains the low level.

Since the voltage of the first node N21is the low level, the ninth transistor NT9is in the on state. The high level scan clock signal NCLK is provided to the output terminal409by the ninth transistor NT9of the on state. Then, the stage NST0of the scan driver22outputs the high level second scan signal NS[0].

At time tc7, the second clock signal ECLK2is switched to the low level L. The scan clock signal NCLK maintains the high level, and the first clock signal ECLK1maintains the high level.

Before the second clock signal ECLK2is switched to the low level L, the second scan start signal NSSP is switched to the low level L.

The seventh transistor NT7is in the off state by the low-level first clock signal ECLK1, and the eleventh transistor NT11is in the off state by the scan clock signal NCLK of the high level H.

When the second clock signal ECLK2of the low level L is supplied, the first transistor NT1and the third transistor NT3are turned on. Then, the turned-on first transistor NT1electrically connects the eleventh transistor NT11and the second node N22, and the second voltage VGL is supplied to the third node N23through the turned-on third transistor NT3. Accordingly, the voltage of the second node N22maintains the high level H, and the voltage of the third node N23maintains the low level.

Since the voltage of the third node N23is the low level, the fifth transistor NT5and the sixth transistor NT6are turned on. Since the first voltage VGH is provided to one end of the first capacitor NC1connected to the fourth transistor NT4through the turned-on fifth transistor NT5, the high level voltage is applied to opposite ends of the first capacitor NC1to be discharged.

The first clock signal ECLK1of the high level H is provided to the fourth node N24through the turned-on sixth transistor NT6. Then, the second capacitor NC2charges a voltage difference between the first clock signal ECLK1of the high level H and the third node N23of the low level.

After time tc8, the scan clock signal NCLK is switched to the low level. Then, the low level scan clock signal NCLK is provided to the output terminal409through the ninth transistor NT9of the on state. In other words, the stage NST0of the scan driver22outputs the low-level second scan signal NS[0].

Furthermore, at time tc9, the voltage of the first node N21is a level L3which is lower than the low level L.

After time tc18when the scan clock signal NCLK is switched to the low level, the output of the high level scan signal NS[n] from the last stage INSTn to the second scan line NSn is terminated. Then, at time tc23, the holding control signal BPC is switched to the low level. In this case, the first clock signal ECLK1, the second clock signal ECLK2, and the scan clock signal NCLK may stop clocking.

When the holding control signal BPC is switched to the low level, since the second voltage VGL is supplied to the second node N22, the tenth transistor NT10is turned on. Then, the second voltage VGL is supplied to the output terminal409through the turned-on tenth transistor NT10, in other words, all of the stages NST0to NSTn of the second scan driver22maintain the output of the low-level second scan signals NS[0] to NS[n].

Therefore, the second scan driver22according to the present exemplary embodiment may maintain the second scan signals NS[0] to NS[n] at the high level for a predetermined period for the low-frequency driving of the display device.

As can be gleaned, inFIG.17, the signal cycle of tc1to tc23repeats starting at tc24and proceeding at least through tc29.

Hereinafter, an exemplary embodiment of the present invention in which the scan drivers20,21, and22and the holding portions240,340, and440of each of the light emission drivers40and41are provided as one constituent element will be described with reference toFIG.18.

FIG.18illustrates a schematic diagram of a display device including a holding portion according to another exemplary embodiment of the present invention.

As shown inFIG.18, a display unit10of the display device includes a display area DA for displaying an image and a non-display area NDA surrounding the display area DA.

The scan driver20and the light emission driver40may be positioned in the non-display area NDA. The scan driver20includes a plurality of stages (PST1, PST2, PST3, . . . ), and the light emission driver40includes a plurality of stages (EST1, EST2EST3, . . . ).

In addition, a holding portion70may be positioned in the non-display area NDA. The holding portion70may be spaced apart from the scan driver20and the light emission driver40.

The holding portion70includes at least one transistor and is connected to first and second holding lines HL1and HL2. The first holding line HL1is connected to all of the stages (EST1, EST2, EST3, . . . ) of the light emission driver40, and the second holding line HL2is connected to all of the stages (PST1, PST2, PST3, . . . ) of the scan driver20.

For example, the first holding line HL1is connected to the second node N12of the stage EST1shown inFIG.10. The second holding line HL2is connected to the first node N1of the stage PST1shown inFIG.6. In addition, the second holding line HL2is connected to the second node N22of the stage NST0shown inFIG.1.6.

Then, the holding portion70provides the second voltage VGL to the first and second holding lines HL1and HL2depending on the level of the holding control signal BPC.

Exemplary embodiments of the present invention provide a driving device and a display device including the same that may apply signals with the same level for a relatively long period during low-frequency driving.

Exemplary embodiments of the present invention provide a driving device and a display device including the same that may apply signals with the same level without applying a clock signal during low-frequency driving.

According to exemplary embodiments of the present invention, it is possible to increase display quality of a display device.

According to exemplary embodiments of the present invention, it is possible to reduce power consumption of a display device.

According to exemplary embodiments of the present invention, it is possible to stably operate a display device.

While this invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various modifications may be made thereto without departing from the spirit and scope of the present invention as defined by the appended claims.