Patent ID: 12191823

DESCRIPTION

The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

A power amplifier is generally designed to provide maximum efficiency at the maximum rated output power for the amplifier. The maximum output power for some third generation and/or fourth generation (3G/4G) amplifier systems is approximately 25 decibel-milliwatts (dBm) antenna power. However, some power amplifiers that are configured to operate efficiently at high power levels may be inefficient when operating at low power levels (e.g., at 0 dBm antenna power). For example, specifications of the power amplifier, including the number of stages, amplifier transistor sizes, and/or bias networks, may be chosen to optimize performance at high power levels (e.g., 25 dBm), leading to significant efficiency tradeoffs when operating at a lower power (e.g., 0 dBm).

Some power amplifiers (including some 3G/4G handset amplifiers) have multiple gain stages to achieve a desired amount of gain between the transceiver and antenna at the highest output power. To reduce the dynamic range requirement of the transceiver, it is desirable to have significantly reduced gain at lower output powers. For example, for some power amplifiers it is desirable to have 25-30 dB gain at high power and 10-15 dB gain at low power. It is also desirable to maintain efficient current consumption at low output power levels with lower gain. However, 10-15 dB gain at low power can be difficult to achieve on a multi-stage power amplifier designed for 25-30 dB gain at high power.

One option for improving efficiency and lower gain at low output power levels involves reducing bias current within the power amplifier. For example, quiescent current levels may be reduced as much as possible to support a lower output power. However, reducing bias current can lead to degraded linearity of the power amplifier. Generally, the lower the current that a power amplifier is operated at, the worse the linearity of the power amplifier. Moreover, particularly for power amplifiers having multiple gain stages, lowering bias current may be ineffective for lowering the gain of the power amplifier. Accordingly, solutions involving lowering bias current may also require incorporating attenuation at the power amplifier in order to effectively reduce the gain, and attenuation may cause performance issues for the power amplifier.

Some embodiments described herein provide enhanced high-power mode (HPM) and/or low-power mode (LPM) efficiency through use of cascode HPM and/or LPM stages. In some embodiments, each of a HPM stage and a LPM stage may connect to a single switch arm at a band switch. Some embodiments involve connecting the switch arm to parallel HPM cascode and LPM cascodes. In this way, the number of switch arms at the band switch is minimized and the size of the power amplifier may be limited to allow efficient current consumption at low output power levels with lower gain.

FIG.1shows a power amplifier including a HPM stage, in accordance with some embodiments. In the embodiment shown inFIG.1, the amplifier10includes a radio frequency (RF) input11that may deliver current to an input matching circuit12including two series capacitors and a shunt inductor. A first stage of the power amplifier10may include a common-emitter transistor13that may be connected to a driver matching circuit14between a driver stage and a final stage of the power amplifier10. The term “connected” is used herein according to its broad and ordinary meaning and may refer to a physical coupling or connection between components of a circuit. A person having ordinary skill in the art will understand that a connection may refer to a connection to a common wire and/or node.

A first bias source15may provide a base bias current for the common-emitter transistor13driver stage to set the quiescent current. The driver matching circuit14may include a supply inductor, a series capacitor, two shunt inductors, and a series inductor. The driver matching circuit14may feed into a HPM cascode16comprising a common-emitter transistor17and a common-base transistor18. A second bias source19may provide a base bias current for the final stage to set the quiescent current. The collector of the common-base transistor18may be connected to a capacitor circuit19configured to provide harmonic termination to support the class of operation of the power amplifier. An RF output20may feed a band switch through matching inductance.

FIG.2shows one embodiment of a multi-stage cascode power amplifier having a HPM stage and a LPM stage, the power amplifier including separate switch arms for each stage in accordance with some embodiments. The power amplifier25may comprise a HPM stage26and a LPM stage27. The HPM stage26may be optimized for higher power levels (e.g., 25 dBm) while the LPM stage27may be optimized for lower power levels (e.g., 0 dBm). In some embodiments, the LPM stage27may be configured to reduce current at low power levels in order to reduce gain. The power amplifier25may comprise a band switch28for switching between a plurality of bands29(e.g., a 3G band, 4G band, etc.). In some embodiments, the HPM stage26may have an associated HPM switch arm30and the LPM stage27may have an associated LPM switch arm31at the band switch28. During high-power modes, the HPM stage26may be active while during low-power modes, the LPM stage27may be active. In this way, HPM performance and LPM performance can be effectively decoupled to allow for optimization of both modes. However, including multiple switch arms in the band switch28may require increased complexity, size, and/or cost of the band switch28and/or the power amplifier25relative to power amplifiers comprising a single band switch arm.

In some embodiments, the band switch28may comprise multiple parallel sets of switch paths32. For example, if there are two switch arms, there may be a set of switch paths32for each switch arm. In the example shown inFIG.2, there may be ten switch paths; five for the HPM switch arm30and five for the LPM switch arm31. Accordingly, as the number of bands29and/or switch arms increases, the size of the band switch28can increase exponentially, which can result in drastic increases in size and/or cost of the power amplifier25.

FIG.3shows another embodiment of a multi-stage cascode power amplifier having a HPM stage and a LPM stage, the power amplifier including separate switch arms for each stage in accordance with some embodiments. The power amplifier35may include a RF input36which may be fed into a dedicated LPM stage37. In some embodiments, the power amplifier35may include a switch to connect the RF input to the LPM stage37and a HPM stage38. The LPM stage37may include an input matching circuit39which may feed into a common-emitter transistor40. The collector of the common-emitter transistor may be connected to a supply voltage41via an inductor42. The common-emitter transistor40may feed into a harmonic termination circuit43and provide an LPM output44to a band switch. The power amplifier35may further include HPM output45for the HPM stage38to the band switch. Accordingly, the band switch for the power amplifier may include separate switch arms for the HPM stage38and the LPM stage37, with one switch arm connected to the LPM output44and another switch arm connected to the HPM output45.

FIG.4shows a multi-stage cascode power amplifier for connecting a HPM stage and an LPM stage to a single band switch arm, in accordance with some embodiments. The power amplifier47may comprise a HPM stage48and a LPM stage49. In some embodiments, the power amplifier47may comprise additional stages. The HPM stage48may be optimized for high power (e.g., 25 dBm) and the LPM stage49may be optimized for low power (e.g., 0-10 dBm). In some embodiments, the power amplifier47may comprise an input switch59configured to alternatively supply current from an RF input56source to the HPM stage48or the LPM stage49.

The LPM stage49may include a LPM cascode50comprising a first common-emitter transistor51and a first common-base transistor52. In some embodiments, the first common-emitter transistor51and the first common-base transistor52may be in a cascode configuration, in which the collector of the first common-emitter transistor51is connected to the emitter of the first common-base transistor52.

In some embodiments, the HPM stage48includes a HPM cascode53comprising a second common-emitter transistor54and a second common-base transistor55. The second common-emitter transistor54and the second common-base transistor55may be in a cascode configuration in which the collector of the second common-emitter transistor54is connected to the emitter of the second common-base transistor55. In some embodiments, the base of the first common-base transistor52and/or the base of the second common-base transistor55may be coupled to ground via a capacitor, as shown inFIG.4.

In some embodiments, the base of the first common-emitter transistor51may be connected to the input switch59which is connected to the RF input56. The collector of the first common-base transistor52may be connected to the collector of the second common-base transistor55, for example at a node60. As shown inFIG.4, a network of inductors and/or capacitors may be connected between the node60and the band switch58.

The base of the second common-emitter transistor54may be connected to a battery voltage source (“VBATT”), the input switch59, and/or to a collector of a third common-emitter transistor57. The base of the third common-emitter transistor57may be connected to the input switch59. In some embodiments, each of the first common-emitter transistor51, the first common-base transistor52, the second common-emitter transistor54, the second common-base transistor55, and the third common-emitter transistor57may be any type of transistor, for example a bipolar junction transistor (BJT).

In the LPM configuration, the first common-base transistor51may perform the function of a switch so that a designated LPM switch at the band switch58is not required. Rather, both of the first common-emitter transistor52and the second common-emitter transistor55may be connected to a single switch arm61. In this way, the size, cost, and/or complexity of the power amplifier47may be reduced relative to devices having two or more switches at a band switch. Moreover, the LPM stage49may provide limited loading at the HPM stage48without degrading the HPM stage48. In some embodiments, the LPM stage49may act as a single-stage amplifier. Accordingly, lower gain levels (e.g., 10-15 dB) may be achieved without linearity degradation.

In some embodiments, one or more of the first common-emitter transistor51, the first common-base transistor52, the second common-emitter transistor54, and the second common-base transistor55may comprise a plurality of transistors in parallel. For example, each of the first common-emitter transistor51and the first common-base transistor52may comprise two transistors in parallel while each of the second common-base transistor55and the second common-emitter transistor54may comprise eighteen transistors in parallel.

Switching between the HPM stage48and the LPM stage49may be performed at the input switch59. The input switch59may be configured to alternatively supply current to the HPM stage48or the LPM stage49. In some embodiments, the LPM cascode50may be activated by switching the input switch59such that bias current from the RF input56is fed to the LPM stage49side. Similarly, the HPM cascode53may be activated by switching the input switch59such that bias current from the RF input56is fed to the HPM stage48side. If the first common-emitter transistor51is active, bias current may flow through the LPM stage49. If the second common-emitter transistor54is active, bias current may flow through the HPM stage48. In some embodiments, voltage may be shared between the HPM cascode53and the LPM cascode50.

FIG.5shows another multi-stage cascode power amplifier for connecting a HPM stage and an LPM stage to a single band switch arm, in accordance with some embodiments. The power amplifier65comprises an RF input66which may be fed alternatively into the HPM stage67or the LPM stage68. The LPM stage may comprise a matching circuit69and a common-emitter transistor70. The collector of the common-emitter transistor may feed into a LPM common-base transistor71. The base of the LPM common-base transistor71may share a node with a HPM common-base transistor72. By providing a source current to a first bias source73, the LPM stage68may be activated and the common-emitter transistor70may conduct collector current, which may in turn activate the LPM common-base transistor71. When the LPM stage68is activated, there may be no current running through the HPM stage67, resulting in a high isolation stage. Conversely, activating the HPM stage67may cause quiescent current to pass through the HPM transistors. In this way, either stage may be selected based on where bias current is applied. Each of the HPM stage67and the LPM stage68may connect to a common node74which may connect to a switch arm at a band switch. Because both stages connect to the same switch arm, only one switch arm may be needed at the band switch for the combined HPM stage67and the LPM stage68.

FIG.6shows a process600for limiting average current values at a power amplifier that can be implemented with embodiments herein. Steps of the process600may be performed in any order and in some cases steps may be removed and/or added as needed.

In block602, a bias current may be generated. In some embodiments, the bias current may be fed through a switch to allow the bias current to flow through either a HPM stage or a LPM stage of a power amplifier.

In decision block604, it may be determined whether the bias current flows through the HPM stage or the LPM stage. If the bias current flows through the HPM stage, the HPM stage may be active and the process600continues to block606. If the bias current flows through the LPM stage, the LPM stage may be active and the process602continues to block608.

In block606, a switch arm at a band switch may be controlled/managed based on the HPM stage. In some embodiments, the switch arm may be connected to the HPM stage at a collector of a common-base transistor of the HPM stage.

In block608, the switch arm may be controlled/managed based on the LPM stage. In some embodiments, the switch arm may be connected to the LPM stage at a collector of a common-base transistor of the LPM stage.

FIG.7shows that in some embodiments, some or all of a front-end architecture having one or more features as described herein can be implemented in a module. Such a module can be, for example, a front-end module (FEM). In the example ofFIG.7, a module300can include a packaging substrate302, and a number of components can be mounted on such a packaging substrate. For example, a control component102, a power amplifier assembly104, an antenna tuner component106, and a duplexer assembly108can be mounted and/or implemented on and/or within the packaging substrate302. Other components such as a number of SMT devices304and an antenna switch module (ASM)306can also be mounted on the packaging substrate302. Although all of the various components are depicted as being laid out on the packaging substrate302, it will be understood that some component(s) can be implemented over other component(s).

In some implementations, a device and/or a circuit having one or more features described herein can be included in an RF device such as a wireless device. Such a device and/or a circuit can be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc.

FIG.8depicts an example wireless device400having one or more advantageous features described herein. In the context of a module having one or more features as described herein, such a module can be generally depicted by a dashed box300, and can be implemented as, for example, a front-end module (FEM).

Referring toFIG.8, power amplifiers420can receive their respective RF signals from a transceiver410that can be configured and operated in known manners to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver410is shown to interact with a baseband sub-system408that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver410. The transceiver410can also be in communication with a power management component406that is configured to manage power for the operation of the wireless device400. Such power management can also control operations of the baseband sub-system408and the module300.

The baseband sub-system408is shown to be connected to a user interface402to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system408can also be connected to a memory404that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user.

In the example wireless device400, outputs of the power amplifiers420are shown to be routed to their respective duplexers420. Such amplified and filtered signals can be routed to an antenna416through an antenna switch414for transmission. In some embodiments, the duplexers420can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g.,416). InFIG.8, received signals are shown to be routed to “Rx” paths (not shown) that can include, for example, a low-noise amplifier (LNA).

As described herein, one or more features of the present disclosure can provide a number of advantages when implemented in systems such as those involving the wireless device ofFIG.8. For example, a controller102, which may or may not be part of the module300, can monitor base currents associated with at least some of the power amplifiers420. Based on such monitored base currents, an antenna tuner106(which may or may not be part of the module300), can be adjusted to provide a desired impedance to the corresponding power amplifier.

The present disclosure describes various features, no single one of which is solely responsible for the benefits described herein. It will be understood that various features described herein may be combined, modified, or omitted, as would be apparent to one of ordinary skill. Other combinations and sub-combinations than those specifically described herein will be apparent to one of ordinary skill, and are intended to form a part of this disclosure. Various methods are described herein in connection with various flowchart steps and/or phases. It will be understood that in many cases, certain steps and/or phases may be combined together such that multiple steps and/or phases shown in the flowcharts can be performed as a single step and/or phase. Also, certain steps and/or phases can be broken into additional sub-components to be performed separately. In some instances, the order of the steps and/or phases can be rearranged and certain steps and/or phases may be omitted entirely. Also, the methods described herein are to be understood to be open-ended, such that additional steps and/or phases to those shown and described herein can also be performed.

Some aspects of the systems and methods described herein can advantageously be implemented using, for example, computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software can comprise computer executable code stored in a computer readable medium (e.g., non-transitory computer readable medium) that, when executed, performs the functions described herein. In some embodiments, computer-executable code is executed by one or more general purpose computer processors. A skilled artisan will appreciate, in light of this disclosure, that any feature or function that can be implemented using software to be executed on a general purpose computer can also be implemented using a different combination of hardware, software, or firmware. For example, such a module can be implemented completely in hardware using a combination of integrated circuits. Alternatively or additionally, such a feature or function can be implemented completely or partially using specialized computers designed to perform the particular functions described herein rather than by general purpose computers.

Multiple distributed computing devices can be substituted for any one computing device described herein. In such distributed embodiments, the functions of the one computing device are distributed (e.g., over a network) such that some functions are performed on each of the distributed computing devices.

Some embodiments may be described with reference to equations, algorithms, and/or flowchart illustrations. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented as computer program products either separately, or as a component of an apparatus or system. In this regard, each equation, algorithm, block, or step of a flowchart, and combinations thereof, may be implemented by hardware, firmware, and/or software including one or more computer program instructions embodied in computer-readable program code logic. As will be appreciated, any such computer program instructions may be loaded onto one or more computers, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer(s) or other programmable processing device(s) implement the functions specified in the equations, algorithms, and/or flowcharts. It will also be understood that each equation, algorithm, and/or block in flowchart illustrations, and combinations thereof, may be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer-readable program code logic means.

Furthermore, computer program instructions, such as embodied in computer-readable program code logic, may also be stored in a computer readable memory (e.g., a non-transitory computer readable medium) that can direct one or more computers or other programmable processing devices to function in a particular manner, such that the instructions stored in the computer-readable memory implement the function(s) specified in the block(s) of the flowchart(s). The computer program instructions may also be loaded onto one or more computers or other programmable computing devices to cause a series of operational steps to be performed on the one or more computers or other programmable computing devices to produce a computer-implemented process such that the instructions which execute on the computer or other programmable processing apparatus provide steps for implementing the functions specified in the equation(s), algorithm(s), and/or block(s) of the flowchart(s).

Some or all of the methods and tasks described herein may be performed and fully automated by a computer system. The computer system may, in some cases, include multiple distinct computers or computing devices (e.g., physical servers, workstations, storage arrays, etc.) that communicate and interoperate over a network to perform the described functions. Each such computing device typically includes a processor (or multiple processors) that executes program instructions or modules stored in a memory or other non-transitory computer-readable storage medium or device. The various functions disclosed herein may be embodied in such program instructions, although some or all of the disclosed functions may alternatively be implemented in application-specific circuitry (e.g., ASICs or FPGAs) of the computer system. Where the computer system includes multiple computing devices, these devices may, but need not, be co-located. The results of the disclosed methods and tasks may be persistently stored by transforming physical storage devices, such as solid state memory chips and/or magnetic disks, into a different state.

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

The disclosure is not intended to be limited to the implementations shown herein. Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention provided herein can be applied to other methods and systems, and are not limited to the methods and systems described above, and elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.