Patent ID: 12205622

BEST MODE FOR CARRYING OUT THE INVENTION

Examples of embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention is not to be construed as being limited to the content of the embodiments included herein.

Note that the position, the size, the range, or the like of each structure illustrated in drawings and the like is not accurately represented in some cases for easy understanding. Therefore, embodiments of the present invention are not necessarily limited to such a position, size, range, or the like disclosed in the drawings and the like.

In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not mean limitation of the number of components.

Embodiment 1

In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the invention disclosed herein will be described with reference toFIG.1,FIGS.2A and2B,FIGS.3A to3H,FIGS.4A to4G,FIGS.5A to5D,FIG.6,FIGS.7A and7B,FIGS.8A and8B, andFIGS.9A and9B.

<Circuit Configuration of Semiconductor Device>

FIG.1illustrates an example of a circuit configuration of a semiconductor device. The semiconductor device includes a transistor160formed using a material other than an oxide semiconductor, and a transistor162formed using an oxide semiconductor.

Here, a gate electrode of the transistor160is electrically connected to one of a source electrode and a drain electrode of the transistor162. A first wiring (a 1st line, also referred to as a source line) is electrically connected to a source electrode of the transistor160. A second wiring (a 2nd line, also referred to as a bit line) is electrically connected to a drain electrode of the transistor160. A third wiring (a 3rd line, also referred to as a first signal line) is electrically connected to the other of the source electrode and the drain electrode of the transistor162. A fourth wiring (a 4th line, also referred to as a second signal line) is electrically connected to a gate electrode of the transistor162.

Since the transistor160including a material other than an oxide semiconductor can operate at sufficiently high speed, stored data can be read out at high speed by using the transistor160. Moreover, the transistor162including an oxide semiconductor has extremely low off-state current. For that reason, a potential of the gate electrode of the transistor160can be held for an extremely long time by turning off the transistor162.

Writing, holding, and reading of data can be performed in the following manner, using the advantage that the potential of the gate electrode can be held.

Firstly, writing and holding of data will be described. First, a potential of the fourth wiring is set to a potential at which the transistor162is turned on, and the transistor162is turned on. Thus, a potential of the third wiring is supplied to the gate electrode of the transistor160(writing). After that, the potential of the fourth wiring is set to a potential at which the transistor162is turned off, and the transistor162is turned off, whereby the potential of the gate electrode of the transistor160is held (holding).

Since the off-state current of the transistor162is extremely low, the potential of the gate electrode of the transistor160is held for a long time. For example, when the potential of the gate electrode of the transistor160is a potential at which the transistor160is turned on, the on state of the transistor160is kept for a long time. Moreover, when the potential of the gate electrode of the transistor160is a potential at which the transistor160is turned off, the off state of the transistor160is kept for a long time.

Secondly, reading of data will be described. When a predetermined potential (a low potential) is supplied to the first wiring in a state where the on state or the off state of the transistor160is kept as described above, a potential of the second wiring varies depending on the on state or the off state of the transistor160. For example, when the transistor160is on, the potential of the second wiring becomes lower than the potential of the first wiring. In contrast, when the transistor160is off, the potential of the second wiring is not changed.

In such a manner, the potential of the second wiring and a predetermined potential are compared with each other in a state where data is held, whereby the data can be read out.

Thirdly, rewriting of data will be described. Rewriting of data is performed in a manner similar to that of the writing and holding of data. That is, the potential of the fourth wiring is set to a potential at which the transistor162is turned on, and the transistor162is turned on. Thus, a potential of the third wiring (a potential for new data) is supplied to the gate electrode of the transistor160. After that, the potential of the fourth wiring is set to a potential at which the transistor162is turned off, and the transistor162is turned off, whereby the new data is stored.

In the semiconductor device according to the invention disclosed herein, data can be directly rewritten by another writing of data as described above. For that reason, erasing operation which is necessary for a flash memory or the like is not needed, so that a reduction in operation speed because of erasing operation can be prevented. In other words, high-speed operation of the semiconductor device can be realized.

Note that an n-channel transistor in which electrons are majority carriers is used in the above description; it is needless to say that a p-channel transistor in which holes are majority carriers can be used instead of the n-channel transistor.

<Planar Structure and Cross-Sectional Structure of Semiconductor Device>

FIGS.2A and2Billustrate an example of a structure of the semiconductor device.FIG.2Aillustrates a cross section of the semiconductor device, andFIG.2Billustrates a plan view of the semiconductor device. Here,FIG.2Acorresponds to a cross section along line A1-A2and line B1-B2inFIG.2B. The semiconductor device illustrated inFIGS.2A and2Bincludes the transistor160including a material other than an oxide semiconductor in a lower portion, and the transistor162including an oxide semiconductor in an upper portion. Note that the transistors160and162are n-channel transistors here; alternatively, a p-channel transistor may be used. In particular, it is easy to use a p-channel transistor as the transistor160.

The transistor160includes a channel formation region116provided in a substrate100including a semiconductor material, impurity regions114and high-concentration impurity regions120(these regions can be collectively referred to simply as impurity regions) provided so as to sandwich the channel formation region116, a gate insulating layer108aprovided over the channel formation region116, a gate electrode110aprovided over the gate insulating layer108a, and a source electrode or drain electrode (hereinafter referred to as a source/drain electrode)130aand a source/drain electrode130belectrically connected to the impurity regions114.

A sidewall insulating layer118is provided on a side surface of the gate electrode110a. The high-concentration impurity region120is placed in a region of the substrate100that does not overlap with the sidewall insulating layer118when seen in the cross-sectional view. A metal compound region124is placed over the high-concentration impurity region120. An element isolation insulating layer106is provided over the substrate100so as to surround the transistor160. An interlayer insulating layer126and an interlayer insulating layer128are provided so as to cover the transistor160. Each of the source/drain electrode130aand the source/drain electrode130bis electrically connected to the metal compound region124through an opening formed in the interlayer insulating layers126and128. That is, each of the source/drain electrodes130aand130bis electrically connected to the high-concentration impurity region120and the impurity region114through the metal compound region124. An electrode130cthat is formed in a manner similar to that of the source/drain electrodes130aand130bis electrically connected to the gate electrode110a.

The transistor162includes a gate electrode136dprovided over the interlayer insulating layer128, a gate insulating layer138provided over the gate electrode136d, an oxide semiconductor layer140provided over the gate insulating layer138, and a source/drain electrode142aand a source/drain electrode142bthat are provided over the oxide semiconductor layer140and electrically connected to the oxide semiconductor layer140.

Here, the gate electrode136dis provided so as to be embedded in an insulating layer132formed over the interlayer insulating layer128. Like the gate electrode136d, an electrode136a, an electrode136b, and an electrode136care formed in contact with the source/drain electrode130a, the source/drain electrode130b, and the electrode130c, respectively.

A protective insulating layer144is provided over the transistor162so as to be in contact with part of the oxide semiconductor layer140. An interlayer insulating layer146is provided over the protective insulating layer144. Openings that reach the source/drain electrode142aand the source/drain electrode142bare formed in the protective insulating layer144and the interlayer insulating layer146. An electrode150dand an electrode150eare formed in contact with the source/drain electrode142aand the source/drain electrode142b, respectively, through the respective openings. Like the electrodes150dand150e, an electrode150a, an electrode150b, and an electrode150care formed in contact with the electrode136a, the electrode136b, and the electrode136c, respectively, through openings provided in the gate insulating layer138, the protective insulating layer144, and the interlayer insulating layer146.

Here, the oxide semiconductor layer140is preferably a highly purified oxide semiconductor layer from which impurities such as hydrogen are sufficiently removed. Specifically, the concentration of hydrogen in the oxide semiconductor layer140is 5×1019/cm3or less, preferably 5×1018/cm3or less, more preferably 5×1017/cm3or less.

Moreover, the oxide semiconductor layer140which is highly purified by a sufficient reduction in hydrogen concentration has a carrier concentration of 5×1014/cm3or less, preferably 5×1012/cm3or less. The transistor162with excellent off-state current characteristics can be obtained with the use of such an oxide semiconductor that is highly purified by a sufficient reduction in hydrogen concentration and becomes intrinsic or substantially intrinsic. For example, when the drain voltage Vd is +1 V or +10 V and the gate voltage Vg is in the range of −5 V to −20 V, the off-state current is 1×10−13A or less. The oxide semiconductor layer140which is highly purified by a sufficient reduction in hydrogen concentration is used so that the off-state current of the transistor162is reduced, whereby a semiconductor device with a novel structure can be realized. Note that the concentration of hydrogen in the oxide semiconductor layer140is measured by secondary ion mass spectrometry (SIMS).

An insulating layer152is provided over the interlayer insulating layer146. An electrode154a, an electrode154b, an electrode154c, and an electrode154dare provided so as to be embedded in the insulating layer152. The electrode154ais in contact with the electrode150a. The electrode154bis in contact with the electrode150b. The electrode154cis in contact with the electrode150cand the electrode150d. The electrode154dis in contact with the electrode150e.

That is, in the semiconductor device illustrated inFIGS.2A and2B, the gate electrode110aof the transistor160and the source/drain electrode142aof the transistor162are electrically connected through the electrodes130c,136c,150c,154c, and150d.

<Method for Manufacturing Semiconductor Device>

Next, an example of a method for manufacturing the semiconductor device will be described. First, a method for manufacturing the transistor160in the lower portion will be described below with reference toFIGS.3A to3H, and then a method for manufacturing the transistor162in the upper portion will be described with reference toFIGS.4A to4GandFIGS.5A to5D.

<Method for Manufacturing Lower Transistor>

First, the substrate100including a semiconductor material is prepared (seeFIG.3A). As the substrate100including a semiconductor material, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like; a compound semiconductor substrate made of silicon germanium or the like; an SOI substrate; or the like can be used. Here, an example of using a single crystal silicon substrate as the substrate100including a semiconductor material is described. Note that in general, the term “SOI substrate” means a substrate where a silicon semiconductor layer is provided on an insulating surface. In this specification and the like, the term “SOI substrate” also includes a substrate where a semiconductor layer formed using a material other than silicon is provided over an insulating surface in its category. That is, a semiconductor layer included in the “SOI substrate” is not limited to a silicon semiconductor layer. Moreover, the SOI substrate can be a substrate having a structure in which a semiconductor layer is provided over an insulating substrate such as a glass substrate, with an insulating layer therebetween.

A protective layer102serving as a mask for forming an element isolation insulating layer is formed over the substrate100(seeFIG.3A). As the protective layer102, an insulating layer formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like can be used, for example. Note that before or after this step, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate100in order to control the threshold voltage of the transistor. When the semiconductor material included in the substrate100is silicon, phosphorus, arsenic, or the like can be used as the impurity imparting n-type conductivity. Boron, aluminum, gallium, or the like can be used as the impurity imparting p-type conductivity.

Next, part of the substrate100in a region that is not covered with the protective layer102(i.e., in an exposed region) is removed by etching, using the protective layer102as a mask. Thus, an isolated semiconductor region104is formed (seeFIG.3B). As the etching, dry etching is preferably performed, but wet etching may be performed. An etching gas and an etchant can be selected as appropriate depending on a material of a layer to be etched.

Then, an insulating layer is formed so as to cover the semiconductor region104, and the insulating layer in a region overlapping with the semiconductor region104is selectively removed, so that element isolation insulating layers106are formed (seeFIG.3B). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like. As a method for removing the insulating layer, any of etching treatment and polishing treatment such as CMP can be employed. Note that the protective layer102is removed after the formation of the semiconductor region104or after the formation of the element isolation insulating layers106.

Next, an insulating layer is formed over the semiconductor region104, and a layer including a conductive material is formed over the insulating layer.

Because the insulating layer serves as a gate insulating layer later, the insulating layer preferably has a single-layer structure or a layered structure using a film containing silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like formed by a CVD method, a sputtering method, or the like. Alternatively, the insulating layer may be formed in such a manner that a surface of the semiconductor region104is oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment. The high-density plasma treatment can be performed using, for example, a mixed gas of a rare gas such as He, Ar, Kr, or Xe and a gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. There is no particular limitation on the thickness of the insulating layer; the insulating layer can have a thickness of 1 nm to 100 nm inclusive, for example.

The layer including a conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The layer including a conductive material may be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. There is no particular limitation on the method for forming the layer containing a conductive material, and a variety of film formation methods such as an evaporation method, a CVD method, a sputtering method, or a spin coating method can be employed. Note that this embodiment shows an example of the case where the layer containing a conductive material is formed using a metal material.

After that, the insulating layer and the layer including a conductive material are selectively etched, so that the gate insulating layer108aand the gate electrode110aare formed (seeFIG.3C).

Next, an insulating layer112that covers the gate electrode110ais formed (seeFIG.3C). Then, the impurity regions114with a shallow junction depth are formed by adding phosphorus (P), arsenic (As), or the like to the semiconductor region104(see FIG.3C). Note that phosphorus or arsenic is added here in order to form an n-channel transistor; an impurity element such as boron (B) or aluminum (Al) may be added in the case of forming a p-channel transistor. With the formation of the impurity regions114, the channel formation region116is formed in the semiconductor region104below the gate insulating layer108a(seeFIG.3C). Here, the concentration of the impurity added can be set as appropriate; the concentration is preferably increased when the size of a semiconductor element is extremely decreased. The step in which the impurity regions114are formed after the formation of the insulating layer112is employed here; alternatively, the insulating layer112may be formed after the formation of the impurity regions114.

Next, the sidewall insulating layers118are formed (seeFIG.3D). An insulating layer is formed so as to cover the insulating layer112and then subjected to highly anisotropic etching, whereby the sidewall insulating layers118can be formed in a self-aligned manner. At this time, it is preferable to partly etch the insulating layer112so that a top surface of the gate electrode110aand top surfaces of the impurity regions114are exposed.

Then, an insulating layer is formed so as to cover the gate electrode110a, the impurity regions114, the sidewall insulating layers118, and the like. Next, phosphorus (P), arsenic (As), or the like is added to regions in contact with the impurity regions114, so that the high-concentration impurity regions120are formed (seeFIG.3E). After that, the insulating layer is removed, and a metal layer122is formed so as to cover the gate electrode110a, the sidewall insulating layers118, the high-concentration impurity regions120, and the like (seeFIG.3E). A variety of film formation methods such as a vacuum evaporation method, a sputtering method, or a spin coating method can be employed for forming the metal layer122. The metal layer122is preferably formed using a metal material that reacts with a semiconductor material included in the semiconductor region104to be a low-resistance metal compound. Examples of such a metal material are titanium, tantalum, tungsten, nickel, cobalt, and platinum.

Next, heat treatment is performed so that the metal layer122reacts with the semiconductor material. Thus, the metal compound regions124that are in contact with the high-concentration impurity regions120are formed (seeFIG.3F). Note that when the gate electrode110ais formed using polycrystalline silicon or the like, a metal compound region is also formed in a region of the gate electrode110ain contact with the metal layer122.

As the heat treatment, irradiation with a flash lamp can be employed, for example. Although it is needless to say that another heat treatment method may be used, a method by which heat treatment for an extremely short time can be achieved is preferably used in order to improve the controllability of chemical reaction in formation of the metal compound. Note that the metal compound regions are formed by reaction of the metal material and the semiconductor material and have sufficiently high conductivity. The formation of the metal compound regions can properly reduce the electric resistance and improve element characteristics. Note that the metal layer122is removed after the metal compound regions124are formed.

Then, the interlayer insulating layer126and the interlayer insulating layer128are formed so as to cover the components formed in the above steps (seeFIG.3G). The interlayer insulating layers126and128can be formed using an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Moreover, the interlayer insulating layers126and128can be formed using an organic insulating material such as polyimide or acrylic. Note that a two-layer structure of the interlayer insulating layer126and the interlayer insulating layer128is employed here; however, the structure of an interlayer insulating layer is not limited to this structure. After the formation of the interlayer insulating layer128, a surface of the interlayer insulating layer128is preferably planarized with CMP, etching, or the like.

Then, openings that reach the metal compound regions124are formed in the interlayer insulating layers, and the source/drain electrode130aand the source/drain electrode130bare formed in the openings (seeFIG.3H). The source/drain electrodes130aand130bcan be formed in such a manner, for example, that a conductive layer is formed in a region including the openings by a PVD method, a CVD method, or the like and then part of the conductive layer is removed by etching, CMP, or the like.

Note that in the case where the source/drain electrodes130aand130bare formed by removing part of the conductive layer, the process is preferably performed so that the surfaces are planarized. For example, when a thin titanium film or a thin titanium nitride film is formed in a region including the openings and then a tungsten film is formed so as to be embedded in the openings, excess tungsten, titanium, titanium nitride, or the like is removed and the planarity of the surface can be improved by subsequent CMP. The surface including the source/drain electrodes130aand130bis planarized in such a manner, so that an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps.

Note that only the source/drain electrodes130aand130bin contact with the metal compound regions124are shown here; however, an electrode that is in contact with the gate electrode110a(e.g., the electrode130cinFIG.2A) and the like can also be formed in this step. There is no particular limitation on a material used for the source/drain electrodes130aand130b, and a variety of conductive materials can be used. For example, a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium can be used.

Through the above steps, the transistor160using the substrate100including a semiconductor material is formed. Note that an electrode, a wiring, an insulating layer, or the like may be further formed after the above step. When the wirings have a multi-layer structure of a layered structure including an interlayer insulating layer and a conductive layer, a highly integrated semiconductor device can be provided.

<Method for Manufacturing Upper Transistor>

Next, steps for manufacturing the transistor162over the interlayer insulating layer128will be described with reference toFIGS.4A to4GandFIGS.5A to5D. Note thatFIGS.4A to4GandFIGS.5A to5Dillustrate steps for manufacturing electrodes, the transistor162, and the like over the interlayer insulating layer128; therefore, the transistor160and the like placed below the transistor162are omitted.

First, the insulating layer132is formed over the interlayer insulating layer128, the source/drain electrodes130aand130b, and the electrode130c(seeFIG.4A). The insulating layer132can be formed by a PVD method, a CVD method, or the like. The insulating layer132can be formed using an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide.

Next, openings that reach the source/drain electrodes130aand130band the electrode130care formed in the insulating layer132. At this time, an opening is also formed in a region where the gate electrode136dis to be formed later. Then, a conductive layer134is formed so as to be embedded in the openings (seeFIG.4B). The openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as light exposure using a photomask. Either wet etching or dry etching may be used as the etching; dry etching is preferably used in terms of microfabrication. The conductive layer134can be formed by a film formation method such as a PVD method or a CVD method. The conductive layer134can be formed using a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy or a compound (e.g., a nitride) of any of these materials, for example.

Specifically, it is possible to employ a method, for example, in which a thin titanium film is formed in a region including the openings by a PVD method and a thin titanium nitride film is formed by a CVD method, and then, a tungsten film is formed so as to be embedded in the openings. Here, the titanium film formed by a PVD method has a function of reducing an oxide film at the interface with the insulating layer132to decrease the contact resistance with lower electrodes (here, the source/drain electrodes130aand130b, the electrode130c, and the like). The titanium nitride film formed after the formation of the titanium film has a barrier function of preventing diffusion of the conductive material. A copper film may be formed by a plating method after the formation of the barrier film of titanium, titanium nitride, or the like.

After the conductive layer134is formed, part of the conductive layer134is removed by etching, CMP, or the like, so that the insulating layer132is exposed and the electrodes136a,136b, and136cand the gate electrode136dare formed (seeFIG.4C). Note that when the electrodes136a,136b, and136cand the gate electrode136dare formed by removing part of the conductive layer134, the process is preferably performed so that the surfaces are planarized. The surfaces of the insulating layer132, the electrodes136a,136b, and136c, and the gate electrode136dare planarized in such a manner, whereby an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps.

Next, the gate insulating layer138is formed so as to cover the insulating layer132, the electrodes136a,136b, and136c, and the gate electrode136d(seeFIG.4D). The gate insulating layer138can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer138is preferably formed using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer138may have a single-layer structure or a layered structure. For example, the gate insulating layer138made of silicon oxynitride can be formed by a plasma CVD method using silane (SiH4), oxygen, and nitrogen as a source gas. There is no particular limitation on the thickness of the gate insulating layer138; the gate insulating layer138can have a thickness of 10 nm to 500 nm inclusive, for example. In the case of employing a layered structure, for example, the gate insulating layer138is preferably a stack of a first gate insulating layer having a thickness of 50 nm to 200 nm inclusive, and a second gate insulating layer with a thickness of 5 nm to 300 nm inclusive over the first gate insulating layer.

Note that an oxide semiconductor that becomes intrinsic or substantially intrinsic by removal of impurities (a highly purified oxide semiconductor) is quite susceptible to the interface level and the interface charge; therefore, when such an oxide semiconductor is used for an oxide semiconductor layer, the interface with the gate insulating layer is important. In other words, the gate insulating layer138that is to be in contact with a highly purified oxide semiconductor layer needs to have high quality.

For example, the gate insulating layer138is preferably formed by a high-density plasma CVD method using a microwave (2.45 GHz) because the gate insulating layer138can be dense and have high withstand voltage and high quality. When a highly purified oxide semiconductor layer and a high-quality gate insulating layer are in close contact with each other, the interface level can be reduced and interface characteristics can be favorable.

It is needless to say that, even when a highly purified oxide semiconductor layer is used, another method such as a sputtering method or a plasma CVD method can be employed as long as a high-quality insulating layer can be formed as a gate insulating layer. Moreover, it is possible to use an insulating layer whose quality and interface characteristics are improved with heat treatment performed after the formation of the insulating layer. In any case, an insulating layer that has favorable film quality as the gate insulating layer138and can reduce interface level density with an oxide semiconductor layer to form a favorable interface is formed as the gate insulating layer138.

In a gate bias-temperature stress test (BT test) at 85° C. with 2×106V/cm for 12 hours, if an impurity is added to an oxide semiconductor, a bond between the impurity and a main component of the oxide semiconductor is broken by a high electric field (B: bias) and high temperature (T: temperature), and a dangling bond generated causes a drift of the threshold voltage (Vth).

In contrast, impurities of an oxide semiconductor, particularly hydrogen and water, are reduced to a minimum and interface characteristics between the oxide semiconductor and the gate insulating layer are made favorable as described above, whereby a transistor that is stable through the BT test can be obtained.

Next, an oxide semiconductor layer is formed over the gate insulating layer138and processed by a method such as etching using a mask, so that the island-shaped oxide semiconductor layer140is formed (seeFIG.4E).

As the oxide semiconductor layer, it is preferable to use an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, a Sn—Al—Zn—O-based oxide semiconductor layer, an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer, which is preferably amorphous in particular. In this embodiment, as the oxide semiconductor layer, an amorphous oxide semiconductor layer is formed by a sputtering method using a target for depositing an In—Ga—Zn—O-based oxide semiconductor. Note that since crystallization of an amorphous oxide semiconductor layer can be suppressed by adding silicon to the amorphous oxide semiconductor layer, an oxide semiconductor layer may be formed, for example, using a target containing SiO2of 2 wt % to 10 wt % inclusive.

As a target used for forming an oxide semiconductor layer by a sputtering method, a metal oxide target containing zinc oxide as its main component can be used, for example. Moreover, a target for depositing an oxide semiconductor containing In, Ga, and Zn (a composition ratio of In2O3:Ga2O3:ZnO=1:1:1 [mol %] and In:Ga:Zn=1:1:0.5 [atom %]) can be used, for example. Furthermore, a target for depositing an oxide semiconductor containing In, Ga, and Zn (a composition ratio of In:Ga:Zn=1:1:1 [atom %] or a composition ratio of In:Ga:Zn=1:1:2 [atom %]) may be used. The filling rate of a target for depositing an oxide semiconductor is 90% to 100% inclusive, preferably greater than or equal to 95% (e.g., 99.9%). A dense oxide semiconductor layer is formed using a target for depositing an oxide semiconductor with a high filling rate.

The atmosphere in which the oxide semiconductor layer is formed is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen. Specifically, it is preferable to use a high-purity gas, for example, from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed so that the concentration is in the ppm range (preferably the ppb range).

In forming the oxide semiconductor layer, the substrate is held in a treatment chamber that is maintained at reduced pressure and the substrate temperature is set to 100° C. to 600° C. inclusive, preferably 200° C. to 400° C. inclusive. The oxide semiconductor layer is formed while the substrate is heated, so that the impurity concentration of the oxide semiconductor layer can be reduced. Moreover, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor layer is formed using metal oxide as a target. An entrapment vacuum pump is preferably used in order to remove moisture remaining in the treatment chamber. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. An evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber that is evacuated with the cryopump, a hydrogen atom and a compound containing a hydrogen atom such as water (H2O) (and preferably also a compound containing a carbon atom), for example, are removed, whereby the impurity concentration of the oxide semiconductor layer formed in the deposition chamber can be reduced.

The oxide semiconductor layer can be formed under the following conditions, for example: the distance between the substrate and the target is 100 mm; the pressure is 0.6 Pa; the direct-current (DC) power supply is 0.5 kW; and the atmosphere is oxygen (the flow rate ratio of oxygen is 100%). Note that it is preferable to use a pulse direct current (DC) power supply because powder substances (also referred to as particles or dust) generated in film deposition can be reduced and the thickness distribution is uniform. The thickness of the oxide semiconductor layer is 2 nm to 200 nm inclusive, preferably 5 nm to 30 nm inclusive. Note that an appropriate thickness differs depending on an oxide semiconductor material, and the thickness is set as appropriate depending on the material to be used.

Note that before the oxide semiconductor layer is formed by a sputtering method, dust on a surface of the gate insulating layer138is preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated. Here, the reverse sputtering is a method by which ions collide with a surface to be processed so that the surface is modified, in contrast to normal sputtering by which ions collide with a sputtering target. An example of a method for making ions collide with a surface to be processed is a method in which high-frequency voltage is applied to the surface in an argon atmosphere so that plasma is generated near a substrate. Note that an atmosphere of nitrogen, helium, oxygen, or the like may be used instead of an argon atmosphere.

As an etching method for the oxide semiconductor layer, either dry etching or wet etching may be employed. It is needless to say that dry etching and wet etching can be used in combination. The etching conditions (e.g., an etching gas or an etching solution, etching time, and temperature) are set as appropriate depending on the material so that the oxide semiconductor layer can be etched into a desired shape.

An example of an etching gas used for dry etching is a gas containing chlorine (a chlorine-based gas such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), or carbon tetrachloride (CCl4)). Moreover, a gas containing fluorine (a fluorine-based gas such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3)), hydrogen bromide (HBr), oxygen (O2), any of these gases to which a rare gas such as helium (He) or argon (Ar) is added, or the like may be used.

As the dry etching method, a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used. In order to etch the oxide semiconductor layer into a desired shape, etching conditions (e.g., the amount of electric power applied to a coiled electrode, the amount of electric power applied to an electrode on the substrate side, and the electrode temperature on the substrate side) are set as appropriate.

As an etchant used for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid, an ammonia peroxide mixture (hydrogen peroxide solution of 31 wt % ammonia solution of 28 wt %:water=5:2:2), or the like can be used. An etchant such as ITO07N (produced by KANTO CHEMICAL CO., INC.) may also be used.

Then, first heat treatment is preferably performed on the oxide semiconductor layer. The oxide semiconductor layer can be dehydrated or dehydrogenated with the first heat treatment. The temperature of the first heat treatment is greater than or equal to 300° C. and less than or equal to 750° C., preferably greater than or equal to 400° C. and less than the strain point of the substrate. For example, the substrate is introduced into an electric furnace in which a resistance heating element or the like is used and the oxide semiconductor layer140is subjected to heat treatment at 450° C. for one hour in a nitrogen atmosphere. The oxide semiconductor layer140is not exposed to the air during the heat treatment so that entry of water and hydrogen can be prevented.

The heat treatment apparatus is not limited to the electric furnace and can be an apparatus for heating an object by thermal radiation or thermal conduction from a medium such as a heated gas. For example, a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with an object by heat treatment, for example, nitrogen or a rare gas such as argon is used.

For example, as the first heat treatment, a GRTA process may be performed as follows. The substrate is put in an inert gas that has been heated to a high temperature of 650° C. to 700° C., heated for several minutes, and taken out of the inert gas. The GRTA process enables high-temperature heat treatment for a short time. Moreover, the GRTA process can be employed even when the temperature exceeds the strain point of the substrate because it is heat treatment for a short time.

Note that the first heat treatment is preferably performed in an atmosphere that contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is greater than or equal to 6 N (99.9999%), preferably greater than or equal to 7 N (99.99999%) (i.e., the impurity concentration is less than or equal to 1 ppm, preferably less than or equal to 0.1 ppm).

Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer is sometimes crystallized to be microcrystalline or polycrystalline. For example, the oxide semiconductor layer sometimes becomes a microcrystalline oxide semiconductor layer having a degree of crystallization of 90% or more, or 80% or more. Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer containing no crystalline component.

Furthermore, in the oxide semiconductor layer, a microcrystal (the grain size is 1 nm to 20 nm inclusive, typically 2 nm to 4 nm inclusive) is sometimes mixed in an amorphous oxide semiconductor (e.g., a surface of the oxide semiconductor layer).

The electrical characteristics of the oxide semiconductor layer can be changed by aligning microcrystals in an amorphous semiconductor. For example, when the oxide semiconductor layer is formed using a target for depositing In—Ga—Zn—O-based oxide semiconductor, the electrical characteristics of the oxide semiconductor layer can be changed by formation of a microcrystalline portion in which crystal grains of In2Ga2ZnO7with electrical anisotropy are aligned.

Specifically, for example, when the crystal grains are arranged so that the c-axis of In2Ga2ZnO7is perpendicular to a surface of the oxide semiconductor layer, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved and insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Furthermore, such a microcrystalline portion has a function of suppressing entry of an impurity such as water or hydrogen into the oxide semiconductor layer.

Note that the oxide semiconductor layer including the microcrystalline portion can be formed by heating the surface of the oxide semiconductor layer by a GRTA process. Further, the oxide semiconductor layer can be formed in a more preferred manner by using a sputtering target in which the amount of Zn is smaller than that of In or Ga.

The first heat treatment for the oxide semiconductor layer140can be performed on the oxide semiconductor layer that has not yet been processed into the island-shaped oxide semiconductor layer140. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography step is performed.

Note that the above-described heat treatment can be referred to as dehydration treatment, dehydrogenation treatment, or the like because of its effect of dehydration or dehydrogenation on the oxide semiconductor layer140. Such dehydration treatment or dehydrogenation treatment can be performed, for example, after the oxide semiconductor layer is formed, after a source electrode and a drain electrode are stacked over the oxide semiconductor layer140, or after a protective insulating layer is formed over the source and drain electrodes. Such dehydration treatment or dehydrogenation treatment may be performed once or plural times.

Next, the source/drain electrode142aand the source/drain electrode142bare formed in contact with the oxide semiconductor layer140(seeFIG.4F). The source/drain electrodes142aand142bcan be formed in such a manner that a conductive layer is formed so as to cover the oxide semiconductor layer140and then is selectively etched.

The conductive layer can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. As a material for the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten; an alloy containing any of these elements as a component; or the like can be used. Moreover, one or more materials selected from manganese, magnesium, zirconium, beryllium, or thorium may be used. Aluminum combined with one or more of elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium may be used. The conductive layer can have a single-layer structure or a layered structure including two or more layers. For example, the conductive layer can have a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order.

Here, ultraviolet light, KrF laser light, or ArF laser light is preferably used for light exposure in forming a mask used for etching.

The channel length (L) of the transistor is determined by a distance between a lower edge portion of the source/drain electrode142aand a lower edge portion of the source/drain electrode142b. Note that for light exposure in the case where the channel length (L) is less than 25 nm, light exposure for forming a mask is performed with extreme ultraviolet rays whose wavelength is several nanometers to several hundreds of nanometers, which is extremely short. The resolution of light exposure with extreme ultraviolet rays is high and the depth of focus is large. For these reasons, the channel length (L) of the transistor to be formed later can be in the range of 10 nm to 1000 nm, and the circuit can operate at higher speed. Moreover, the off-state current is extremely low, which prevents power consumption from increasing.

The materials and etching conditions of the conductive layer and the oxide semiconductor layer140are adjusted as appropriate so that the oxide semiconductor layer140is not removed in etching of the conductive layer. Note that in some cases, the oxide semiconductor layer140is partly etched in the etching step and thus has a groove portion (a recessed portion) depending on the materials and the etching conditions.

An oxide conductive layer may be formed between the oxide semiconductor layer140and the source/drain electrode142aand between the oxide semiconductor layer140and the source/drain electrode142b. The oxide conductive layer and a metal layer for forming the source/drain electrodes142aand142bcan be successively formed. The oxide conductive layer can function as a source region and a drain region. The placement of such an oxide conductive layer can reduce the resistance of the source region and the drain region, so that the transistor can operate at high speed.

In order to reduce the number of masks to be used and reduce the number of steps, an etching step may be performed with the use of a resist mask formed using a multi-tone mask which is a light-exposure mask through which light is transmitted to have a plurality of intensities. A resist mask formed with the use of a multi-tone mask has a plurality of thicknesses (has a stair-like shape) and further can be changed in shape by ashing; therefore, the resist mask can be used in a plurality of etching steps for processing into different patterns. That is, a resist mask corresponding to at least two kinds of different patterns can be formed by using a multi-tone mask. Thus, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can also be reduced, whereby a process can be simplified.

Note that plasma treatment is preferably performed with the use of a gas such as N2O, N2, or Ar after the above step. This plasma treatment removes water or the like attached on an exposed surface of the oxide semiconductor layer. Plasma treatment may be performed using a mixed gas of oxygen and argon.

Next, the protective insulating layer144is formed in contact with part of the oxide semiconductor layer140without exposure to the air (seeFIG.4G).

The protective insulating layer144can be formed by a method by which impurities such as water and hydrogen are prevented from being mixed to the protective insulating layer144, such as a sputtering method, as appropriate. The protective insulating layer144has a thickness of at least 1 nm. The protective insulating layer144can be formed using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. The protective insulating layer144can have a single-layer structure or a layered structure. The substrate temperature in forming the protective insulating layer144is preferably higher than or equal to room temperature and lower than or equal to 300° C. The atmosphere for forming the protective insulating layer144is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen.

If hydrogen is contained in the protective insulating layer144, the hydrogen may enter the oxide semiconductor layer or extract oxygen in the oxide semiconductor layer, whereby the resistance of the oxide semiconductor layer on the backchannel side might be decreased and a parasitic channel might be formed. Therefore, it is important not to use hydrogen in forming the protective insulating layer144so that the oxide insulating layer144contains hydrogen as little as possible.

Moreover, the protective insulating layer144is preferably formed while water left in the treatment chamber is removed, in order that hydrogen, a hydroxyl group, or moisture is not contained in the oxide semiconductor layer140and the protective insulating layer144.

An entrapment vacuum pump is preferably used in order to remove moisture remaining in the treatment chamber. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. An evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber that is evacuated with the cryopump, a hydrogen atom and a compound containing a hydrogen atom, such as water (H2O), are removed, for example; thus, the impurity concentration of the protective insulating layer144formed in the deposition chamber can be reduced.

As a sputtering gas used for forming the protective insulating layer144, it is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed so that the concentration is in the ppm range (preferably the ppb range).

Next, second heat treatment is preferably performed in an inert gas atmosphere or an oxygen gas atmosphere (at 200° C. to 400° C. inclusive, for example, at 250° C. to 350° C. inclusive). For example, the second heat treatment is performed at 250° C. for one hour in a nitrogen atmosphere. The second heat treatment can reduce variation in electric characteristics of the transistor.

Furthermore, heat treatment may be performed at 100° C. to 200° C. for one hour to 30 hours in the air. This heat treatment may be performed at a fixed heating temperature; alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from room temperature to a temperature of 100° C. to 200° C. and then decreased to room temperature. This heat treatment may be performed under a reduced pressure before the protective insulating layer is formed. The heat treatment time can be shortened under the reduced pressure. This heat treatment may be performed instead of the second heat treatment or may be performed before or after the second heat treatment, for example.

Next, the interlayer insulating layer146is formed over the protective insulating layer144(seeFIG.5A). The interlayer insulating layer146can be formed by a PVD method, a CVD method, or the like. The interlayer insulating layer146can be formed using an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. After the formation of the interlayer insulating layer146, a surface of the interlayer insulating layer146is preferably planarized with CMP, etching, or the like.

Next, openings that reach the electrodes136a,136b, and136cand the source/drain electrodes142aand142bare formed in the interlayer insulating layer146, the protective insulating layer144, and the gate insulating layer138. Then, a conductive layer148is formed so as to be embedded in the openings (seeFIG.5B). The openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as light exposure using a photomask. Either wet etching or dry etching may be used as the etching; dry etching is preferably used in terms of microfabrication. The conductive layer148can be formed by a film formation method such as a PVD method or a CVD method. The conductive layer148can be formed using a conductive material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy or a compound (e.g., a nitride) of any of these materials, for example.

Specifically, it is possible to employ a method, for example, in which a thin titanium film is formed in a region including the openings by a PVD method and a thin titanium nitride film is formed by a CVD method, and then, a tungsten film is formed so as to be embedded in the openings. Here, the titanium film formed by a PVD method has a function of reducing an oxide film at the interface with the interlayer insulating layer146to decrease the contact resistance with lower electrodes (here, the electrodes136a,136b, and136cand the source/drain electrodes142aand142b). The titanium nitride film formed after the formation of the titanium film has a barrier function of preventing diffusion of the conductive material. A copper film may be formed by a plating method after the formation of the barrier film of titanium, titanium nitride, or the like.

After the conductive layer148is formed, part of the conductive layer148is removed by etching, CMP, or the like, so that the interlayer insulating layer146is exposed and the electrodes150a,150b,150c,150d, and150eare formed (seeFIG.5C). Note that when the electrodes150a,150b,150c,150d, and150eare formed by removing part of the conductive layer148, the process is preferably performed so that the surfaces are planarized. The surfaces of the interlayer insulating layer146and the electrodes150a,150b,150c,150d, and150eare planarized in such a manner, whereby an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps.

Then, the insulating layer152is formed, and openings that reach the electrodes150a,150b,150c,150d, and150eare formed in the insulating layer152. After a conductive layer is formed so as to be embedded in the openings, part of the conductive layer is removed by etching, CMP, or the like. Thus, the insulating layer152is exposed and the electrodes154a,154b,154c, and154dare formed (seeFIG.5D). This step is similar to the step of forming the electrode150aand the like; therefore, the detailed description is not repeated.

In the case where the transistor162is formed by the above-described method, the hydrogen concentration of the oxide semiconductor layer140is 5×1019/cm3or less and the off-state current of the transistor162is 1×10−13A or less. The transistor162with excellent characteristics can be obtained by the application of the oxide semiconductor layer140that is highly purified by a sufficient reduction in hydrogen concentration as described above. Moreover, it is possible to manufacture a semiconductor device that has excellent characteristics and includes the transistor160formed using a material other than an oxide semiconductor in the lower portion and the transistor162formed using an oxide semiconductor in the upper portion.

Note that silicon carbide (e.g., 4H-SiC) is a semiconductor material that can be compared to an oxide semiconductor. An oxide semiconductor and 4H-SiC have some things in common. One example is carrier density. Using the Femi-Dirac distribution at room temperature, the density of minority carriers in the oxide semiconductor is estimated to be approximately 1×10−7/cm3, which is as extremely low as 6.7×10−10/cm3of 4H-SiC. When the minority carrier density of the oxide semiconductor is compared with the intrinsic carrier density of silicon (approximately 1.4×1010/cm3), it is easy to understand that the minority carrier density of the oxide semiconductor is significantly low.

In addition, the energy band gap of the oxide semiconductor is 3.0 eV to 3.5 eV and that of 4H-SiC is 3.26 eV, which means that both the oxide semiconductor and silicon carbide are wide bandgap semiconductors.

In contrast, there is a major difference between the oxide semiconductor and silicon carbide, that is, the process temperature. Heat treatment for activation at 1500° C. to 2000° C. is usually needed in a semiconductor process using silicon carbide, so that it is difficult to form a stack of silicon carbide and a semiconductor element formed using a semiconductor material other than silicon carbide. This is because a semiconductor substrate, a semiconductor element, and the like are damaged by such high temperature. On the other hand, the oxide semiconductor can be formed with heat treatment at 300° C. to 500° C. (at a temperature equal to or lower than the glass transition temperature, approximately 700° C. at the maximum); therefore, a semiconductor element can be formed using an oxide semiconductor after an integrated circuit is formed using another semiconductor material.

The oxide semiconductor has an advantage over silicon carbide in that a low heat-resistant substrate such as a glass substrate can be used. Moreover, the oxide semiconductor also has an advantage in that energy costs can be sufficiently reduced as compared to silicon carbide because heat temperature at high temperature is not necessary.

Note that considerable research has been done on properties of oxide semiconductors, such as the density of states (DOS); however, the research does not include the idea of sufficiently reducing the DOS itself. According to one embodiment of the invention disclosed herein, a highly purified oxide semiconductor is manufactured by removing water and hydrogen which might affect the DOS from the oxide semiconductor. This is based on the idea of sufficiently reducing the DOS itself. Thus, excellent industrial products can be manufactured.

Further, it is also possible to realize a more highly purified (i-type) oxide semiconductor in such a manner that oxygen is supplied to metal dangling bonds generated by oxygen vacancy so that the DOS due to oxygen vacancy is reduced. For example, an oxide film containing an excessive amount of oxygen is formed in close contact with a channel formation region and oxygen is supplied from the oxide film, whereby the DOS due to oxygen vacancy can be reduced.

A defect of the oxide semiconductor is said to be attributed to a shallow level of 0.1 eV to 0.2 eV below the conduction band due to excessive hydrogen, a deep level due to shortage of oxygen, or the like. The technical idea that hydrogen is drastically reduced and oxygen is adequately supplied in order to eliminate such a defect would be right.

An oxide semiconductor is generally considered as an n-type semiconductor; however, according to one embodiment of the invention disclosed herein, an i-type semiconductor is realized by removing impurities, particularly water and hydrogen. In this respect, it can be said that one embodiment of the invention disclosed herein includes a novel technical idea because it is different from an i-type semiconductor such as silicon added with an impurity.

Note that this embodiment shows a bottom-gate structure as the structure of the transistor162; however, one embodiment of the present invention is not limited to this. For example, the transistor162can have a top-gate structure. Alternatively, the transistor162can have a dual-gate structure in which two gate electrode layers are provided above and below a channel formation region with gate insulating layers therebetween.

<Electrical Conduction Mechanism of Transistor Including Oxide Semiconductor>

An electrical conduction mechanism of a transistor including an oxide semiconductor will be described with reference toFIG.24,FIGS.25A and25B,FIGS.26A and26B, andFIG.27. Note that the following description is just a consideration and does not deny the validity of the invention.

FIG.24is a cross-sectional view of a dual-gate transistor (thin film transistor) including an oxide semiconductor. An oxide semiconductor layer (OS) is provided over a gate electrode layer (GE1) with a gate insulating layer (GI1) therebetween, and a source electrode (S) and a drain electrode (D) are formed thereover. Moreover, a gate insulating layer (GI2) is provided so as to cover the oxide semiconductor layer (OS), the source electrode (S), and the drain electrode (D). A gate electrode (GE2) is provided over the oxide semiconductor layer (OS) with the gate insulating layer (GI2) therebetween.

FIGS.25A and25Bare energy band diagrams (schematic diagrams) of the cross section A-A′ inFIG.24.FIG.25Aillustrates the case where the potential difference between the source and the drain is zero (the source and the drain have the same potential, VD=0 V).FIG.25Billustrates the case where the potential of the drain is higher than that of the source (VD>0).

FIGS.26A and26Bare energy band diagrams (schematic diagrams) of the cross section B-B′ inFIG.24.FIG.26Aillustrates a state where a positive potential (+VG) is applied to the gate (G1), that is, an on state where carriers (electrons) flow between the source and the drain.FIG.26Billustrates a state where a negative potential (−VG) is applied to the gate (GI), that is, an off state (a state where minority carriers do not flow).

FIG.27illustrates the relation between the vacuum level, the work function (φM) of a metal, and the electron affinity (χ) of an oxide semiconductor.

A conventional oxide semiconductor is an n-type semiconductor. The Fermi level (Ef) is distant from the intrinsic Fermi level (Ei) at the center of the band gap and is located near the conduction band. Note that it is known that part of hydrogen in an oxide semiconductor serves as a donor, which is one of the factors that make the oxide semiconductor an n-type semiconductor.

In contrast, the oxide semiconductor according to one embodiment of the invention disclosed herein is an intrinsic (an i-type) or substantially intrinsic oxide semiconductor obtained in the following manner: hydrogen, which is a factor that makes an n-type semiconductor, is removed from the oxide semiconductor for high purification so that the oxide semiconductor contains an element other than its main element (i.e., an impurity element) as little as possible. In other words, the oxide semiconductor according to one embodiment of the invention disclosed herein is a highly purified i-type (intrinsic) semiconductor or a substantially intrinsic semiconductor obtained by removing impurities such as hydrogen and water as much as possible, not by adding an impurity element. Thus, the Fermi level (Ef) can be comparable with the intrinsic Fermi level (Ei).

The electron affinity (χ) of the oxide semiconductor is said to be 4.3 eV in the case where the band gap (Eg) is 3.15 eV. The work function of titanium (Ti) included in the source electrode and the drain electrode is substantially equal to the electron affinity (χ) of the oxide semiconductor. In this case, the Schottky barrier for electrons is not formed at the interface between the metal and the oxide semiconductor.

That is to say, in the case where the work function (φM) of the metal is equal to the electron affinity (χ) of the oxide semiconductor and the metal and the oxide semiconductor are in contact with each other, an energy band diagram (a schematic diagram) illustrated inFIG.25Ais obtained.

InFIG.25B, a black dot (•) indicates an electron. When a positive potential is applied to the drain, the electron crosses over a barrier (h) and is injected into the oxide semiconductor, and flows toward the drain. The height of the barrier (h) changes depending on the gate voltage and drain voltage. When a positive drain voltage is applied, the height of the barrier is smaller than that of the barrier inFIG.25Awhere no voltage is applied, that is, smaller than ½ of the band gap (Eg).

At this time, as illustrated inFIG.26A, the electron travels in the vicinity of the interface between the gate insulating layer and the highly purified oxide semiconductor (the lowest part of the oxide semiconductor, which is energetically stable).

As illustrated inFIG.26B, when a negative potential is applied to the gate electrode (G1), a hole which is a minority carrier does not exist substantially, so that the current value is substantially close to 0.

In such a manner, the oxide semiconductor layer becomes intrinsic (an i-type semiconductor) or substantially intrinsic by being highly purified so as to contain an element other than its main element (i.e., an impurity element) as little as possible. Thus, characteristics of the interface between the oxide semiconductor and the gate insulating layer become obvious. For that reason, the gate insulating layer needs to form a favorable interface with the oxide semiconductor. Specifically, it is preferable to use the following insulating layer, for example: an insulating layer formed by a CVD method using high-density plasma generated with a power supply frequency in the range of the VHF band to the microwave band, or an insulating layer formed by a sputtering method.

When the interface between the oxide semiconductor and the gate insulating layer is made favorable while the oxide semiconductor is highly purified, in the case where the transistor has a channel width W of 1×104μm and a channel length L of 3 μm, for example, it is possible to realize an off-state current of 1×10−13A or less and a subthreshold swing (S value) of 0.1 V/dec at room temperature (with a 100-nm-thick gate insulating layer).

The oxide semiconductor is highly purified as described above so as to contain an element other than its main element (i.e., an impurity element) as little as possible, so that the thin film transistor can operate in a favorable manner.

MODIFICATION EXAMPLE

FIG.6,FIGS.7A and7B,FIGS.8A and8B, andFIGS.9A and9Billustrate modification examples of structures of semiconductor devices. The semiconductor devices in each of which the transistor162has a structure different from that described above will be described below as modification examples. That is, the structure of the transistor160is the same as the above.

FIG.6illustrates an example of a semiconductor device including the transistor162in which the gate electrode136dis placed below the oxide semiconductor layer140and the source/drain electrodes142aand142bare in contact with a bottom surface of the oxide semiconductor layer140. Note that the planar structure can be changed as appropriate to correspond to the cross section; therefore, only the cross section is shown here.

A big difference between the structure inFIG.6and the structure inFIG.2Ais the position at which the oxide semiconductor layer140is connected to the source/drain electrodes142aand142b. That is, a top surface of the oxide semiconductor layer140is in contact with the source/drain electrodes142aand142bin the structure inFIG.2A, whereas the bottom surface of the oxide semiconductor layer140is in contact with the source/drain electrodes142aand142bin the structure inFIG.6. Moreover, the difference in the contact position results in a different arrangement of other electrodes, an insulating layer, and the like. The details of each component are the same as those ofFIGS.2A and2B.

Specifically, the semiconductor device illustrated inFIG.6includes the gate electrode136dprovided over the interlayer insulating layer128, the gate insulating layer138provided over the gate electrode136d, the source/drain electrodes142aand142bprovided over the gate insulating layer138, and the oxide semiconductor layer140in contact with top surfaces of the source/drain electrodes142aand142b.

Here, the gate electrode136dis provided so as to be embedded in the insulating layer132formed over the interlayer insulating layer128. Like the gate electrode136d, the electrode136a, the electrode136b, and the electrode136care formed in contact with the source/drain electrode130a, the source/drain electrode130b, and the electrode130c, respectively.

The protective insulating layer144is provided over the transistor162so as to be in contact with part of the oxide semiconductor layer140. The interlayer insulating layer146is provided over the protective insulating layer144. Openings that reach the source/drain electrode142aand the source/drain electrode142bare formed in the protective insulating layer144and the interlayer insulating layer146. The electrode150dand the electrode150eare formed in contact with the source/drain electrode142aand the source/drain electrode142b, respectively, through the respective openings. Like the electrodes150dand150e, the electrodes150a,150b, and150care formed in contact with the electrodes136a,136b, and136c, respectively, through openings provided in the gate insulating layer138, the protective insulating layer144, and the interlayer insulating layer146.

The insulating layer152is provided over the interlayer insulating layer146. The electrodes154a,154b,154c, and154dare provided so as to be embedded in the insulating layer152. The electrode154ais in contact with the electrode150a. The electrode154bis in contact with the electrode150b. The electrode154cis in contact with the electrode150cand the electrode150d. The electrode154dis in contact with the electrode150e.

FIGS.7A and7Beach illustrate an example of a structure of a semiconductor device in which the gate electrode136dis placed over the oxide semiconductor layer140.FIG.7Aillustrates an example of a structure in which the source/drain electrodes142aand142bare in contact with a bottom surface of the oxide semiconductor layer140.FIG.7Billustrates an example of a structure in which the source/drain electrodes142aand142bare in contact with a top surface of the oxide semiconductor layer140.

A big difference between the structures inFIGS.7A and7Band those inFIG.2AandFIG.6is that the gate electrode136dis placed over the oxide semiconductor layer140. Furthermore, a big difference between the structure inFIG.7Aand the structure inFIG.7Bis that the source/drain electrodes142aand142bare in contact with either the bottom surface or the top surface of the oxide semiconductor layer140. Moreover, these differences result in a different arrangement of other electrodes, an insulating layer, and the like. The details of each component are the same as those ofFIGS.2A and2B, and the like.

Specifically, the semiconductor device illustrated inFIG.7Aincludes the source/drain electrodes142aand142bprovided over the interlayer insulating layer128, the oxide semiconductor layer140in contact with top surfaces of the source/drain electrodes142aand142b, the gate insulating layer138provided over the oxide semiconductor layer140, and the gate electrode136dover the gate insulating layer138in a region overlapping with the oxide semiconductor layer140.

The semiconductor device inFIG.7Bincludes the oxide semiconductor layer140provided over the interlayer insulating layer128, the source/drain electrodes142aand142bprovided to be in contact with a top surface of the oxide semiconductor layer140, the gate insulating layer138provided over the oxide semiconductor layer140and the source/drain electrodes142aand142b, and the gate electrode136dover the gate insulating layer138in a region overlapping with the oxide semiconductor layer140.

Note that in the structures inFIGS.7A and7B, a component (e.g., the electrode150aor the electrode154a) is sometimes omitted from the structure inFIGS.2A and2Bor the like. In this case, a secondary effect such as simplification of a manufacturing process can be obtained. It is needless to say that a nonessential component can be omitted in the structures inFIGS.2A and2Band the like.

FIGS.8A and8Beach illustrate an example of the case where the size of the element is relatively large and the gate electrode136dis placed below the oxide semiconductor layer140. In this case, a demand for the planarity of a surface and the coverage is relatively moderate, so that it is not necessary to form a wiring, an electrode, and the like to be embedded in an insulating layer. For example, the gate electrode136dand the like can be formed by patterning after formation of a conductive layer. Note that although not illustrated here, the transistor160can be formed in a similar manner.

A big difference between the structure inFIG.8Aand the structure inFIG.8Bis that the source/drain electrodes142aand142bare in contact with either the bottom surface or the top surface of the oxide semiconductor layer140. Moreover, this difference results in other electrodes, an insulating layer, and the like being arranged in a different manner. The details of each component are the same as those ofFIGS.2A and2B, and the like.

Specifically, the semiconductor device inFIG.8Aincludes the gate electrode136dprovided over the interlayer insulating layer128, the gate insulating layer138provided over the gate electrode136d, the source/drain electrodes142aand142bprovided over the gate insulating layer138, and the oxide semiconductor layer140in contact with top surfaces of the source/drain electrodes142aand142b.

The semiconductor device inFIG.8Bincludes the gate electrode136dprovided over the interlayer insulating layer128, the gate insulating layer138provided over the gate electrode136d, the oxide semiconductor layer140provided over the gate insulating layer138overlapping with the gate electrode136d, and the source/drain electrodes142aand142bprovided to be in contact with a top surface of the oxide semiconductor layer140.

Note that also in the structures inFIGS.8A and8B, a component is sometimes omitted from the structure inFIGS.2A and2Bor the like. Also in this case, a secondary effect such as simplification of a manufacturing process can be obtained.

FIGS.9A and9Beach illustrate an example of the case where the size of the element is relatively large and the gate electrode136dis placed over the oxide semiconductor layer140. Also in this case, a demand for the planarity of a surface and the coverage is relatively moderate, so that it is not necessary to form a wiring, an electrode, and the like to be embedded in an insulating layer. For example, the gate electrode136dand the like can be formed by patterning after formation of a conductive layer. Note that although not illustrated here, the transistor160can be formed in a similar manner.

A big difference between the structure inFIG.9Aand the structure inFIG.9Bis that the source/drain electrodes142aand142bare in contact with either the bottom surface or the top surface of the oxide semiconductor layer140. Moreover, this difference results in other electrodes, an insulating layer, and the like being arranged in a different manner. The details of each component are the same as those ofFIGS.2A and2B, and the like.

Specifically, the semiconductor device inFIG.9Aincludes the source/drain electrodes142aand142bprovided over the interlayer insulating layer128, the oxide semiconductor layer140in contact with top surfaces of the source/drain electrodes142aand142b, the gate insulating layer138provided over the source/drain electrodes142aand142band the oxide semiconductor layer140, and the gate electrode136dprovided over the gate insulating layer138in a region overlapping with the oxide semiconductor layer140.

The semiconductor device inFIG.9Bincludes the oxide semiconductor layer140provided over the interlayer insulating layer128, the source/drain electrodes142aand142bprovided to be in contact with a top surface of the oxide semiconductor layer140, the gate insulating layer138provided over the source/drain electrodes142aand142band the oxide semiconductor layer140, and the gate electrode136dprovided over the gate insulating layer138in a region overlapping with the oxide semiconductor layer140.

Note that also in the structures inFIGS.9A and9B, a component is sometimes omitted from the structure inFIGS.2A and2Bor the like. Also in this case, a secondary effect such as simplification of a manufacturing process can be obtained.

As described above, a semiconductor device with a novel structure can be realized according to one embodiment of the invention disclosed herein. In this embodiment, the examples in each of which the semiconductor device is formed by stacking the transistor160and the transistor162are described; however, the structure of the semiconductor device is not limited to this structure. Moreover, this embodiment shows the examples in each of which the channel length direction of the transistor160is perpendicular to that of the transistor162; however, the positional relation between the transistors160and162is not limited to this example. In addition, the transistor160and the transistor162may be provided to overlap with each other.

In this embodiment, the semiconductor device with a minimum storage unit (one bit) is described for simplification; however, the structure of the semiconductor device is not limited thereto. A more advanced semiconductor device can be formed by connecting a plurality of semiconductor devices as appropriate. For example, a NAND-type or NOR-type semiconductor device can be formed by using a plurality of the above-described semiconductor devices. The wiring configuration is not limited to that inFIG.1and can be changed as appropriate.

The semiconductor device according to this embodiment can store data for an extremely long time because the transistor162has low off-state current. That is, refresh operation which is necessary in a DRAM and the like is not needed, so that power consumption can be suppressed. Moreover, the semiconductor device according to this embodiment can be used as a substantially non-volatile semiconductor device.

Since writing or the like of data is performed with switching operation of the transistor162, high voltage is not necessary and deterioration of the element does not become a problem. Furthermore, data is written and erased depending on on and off of the transistor, whereby high-speed operation can be easily realized. In addition, it is also advantageous in that there is no need of operation for erasing data, which is necessary in a flash memory and the like.

Since a transistor including a material other than an oxide semiconductor can operate at sufficiently high speed, stored data can be read out at high speed by using the transistor.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

Embodiment 2

In this embodiment, a circuit configuration and operation of a storage element in a semiconductor device according to one embodiment of the present invention will be described.

FIG.10illustrates an example of a circuit diagram of a storage element (hereinafter also referred to as a memory cell) included in a semiconductor device. A memory cell200illustrated inFIG.10includes a first wiring SL (a source line), a second wiring BL (a bit line), a third wiring S1 (a first signal line), a fourth wiring S2 (a second signal line), a fifth wiring WL (a word line), a transistor201(a first transistor), a transistor202(a second transistor), and a transistor203(a third transistor). The transistors201and203are formed using a material other than an oxide semiconductor. The transistor202is formed using an oxide semiconductor.

A gate electrode of the transistor201and one of a source electrode and a drain electrode of the transistor202are electrically connected to each other. The first wiring and a source electrode of the transistor201are electrically connected to each other. A drain electrode of the transistor201and a source electrode of the transistor203are electrically connected to each other. The second wiring and a drain electrode of the transistor203are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor202are electrically connected to each other. The fourth wiring and a gate electrode of the transistor202are electrically connected to each other. The fifth wiring and a gate electrode of the transistor203are electrically connected to each other.

Next, operation of the circuit will be specifically described.

When data is written into the memory cell200, the first wiring, the fifth wiring, and the second wiring are set to 0 V and the fourth wiring is set to 2 V. The third wiring is set to 2 V in order to write data “1” and set to 0 V in order to write data “0”. At this time, the transistor203is turned off and the transistor202is turned on. Note that at the end of the writing, before the potential of the third wiring is changed, the fourth wiring is set to 0 V so that the transistor202is turned off.

As a result, a potential of a node (hereinafter referred to as a node A) connected to the gate electrode of the transistor201is set to approximately 2 V after the writing of the data “1” and set to approximately 0 V after the writing of the data “0”. Electric charge corresponding to the potential of the third wiring is stored at the node A; since the off-state current of the transistor202is extremely low or substantially 0, the potential of the gate electrode of the transistor201is held for a ling time.FIG.11illustrates an example of a timing chart of writing operation.

Then, when data is read from the memory cell, the first wiring, the fourth wiring, and the third wiring are set to 0 V; the fifth wiring is set to 2 V; and a reading circuit connected to the second wiring is set to an operation state. At this time, the transistor203is turned on and the transistor202is turned off.

The transistor201is off when the data “0” has been written, that is, the node A is set to approximately 0 V, so that the resistance between the second wiring and the first wiring is high. On the other hand, the transistor201is on when the data “1” has been written, that is, the node A is set to approximately 2 V, so that the resistance between the second wiring and the first wiring is low. The reading circuit can read data “0” or data “1” from the difference of the resistance state of the memory cell. Note that the second wiring at the time of the writing is set to 0 V; alternatively, it may be in a floating state or may be charged to have a potential higher than 0 V. The third wiring at the time of the reading is set to 0 V; alternatively, it may be in a floating state or may be charged to have a potential higher than 0 V.

Note that data “1” and data “0” are defined for convenience and may be reversed. Moreover, the above-described operation voltages are one example. The operation voltages are set so that the transistor201is turned off in the case of data “0” and turned on in the case of data “1”, the transistor202is turned on at the time of writing and turned off in periods except the time of writing, and the transistor203is turned on at the time of reading. In particular, a power supply potential VDD of a peripheral logic circuit may be used instead of 2 V.

FIG.12is a block circuit diagram of a semiconductor device with a storage capacity of (m×n) bits according to one embodiment of the present invention.

The semiconductor device according to one embodiment of the present invention includes m fourth wirings, m fifth wirings, n second wirings, n third wirings, a memory cell array210in which a plurality of memory cells200(1,1) to200(m,n) are arranged in a matrix of m rows by n columns (m and n are each a natural number), and peripheral circuits such as a circuit211for driving the second wirings and the third wirings, a circuit213for driving the fourth wirings and the fifth wirings, and a reading circuit212. As another peripheral circuit, a refresh circuit or the like may be provided.

The memory cell200(i,j) is considered as a typical example of the memory cells. Here, the memory cell200(i,j) (i is an integer of 1 to m and j is an integer of 1 to n) is connected to the second wiring BL(j), the third wiring SI(j), the fifth wiring WL(i), the fourth wiring S2(i), and the first wiring. A first wiring potential Vs is supplied to the first wiring. The second wirings BL(1) to BL(n) and the third wirings S1(1) to S1(n) are connected to the circuit211for driving the second wirings and the third wirings and the reading circuit212. The fifth wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the circuit213for driving the fourth wirings and the fifth wirings.

Operation of the semiconductor device illustrated inFIG.12will be described. In this structure, data is written and read per row.

When data is written into the memory cells200(i,1) to200(i,n) of the i-th row, the first wiring potential Vs is set to 0 V; the fifth wiring WL(i) and the second wirings BL(1) to BL(n) are set to 0 V; and the fourth wiring S2(i) is set to 2 V. At this time, the transistor202is turned on. Among the third wirings S1(1) to S1(n), a column in which data “1” is to be written is set to 2 V and a column in which data “0” is to be written is set to 0 V. Note that at the end of the writing, before the potentials of the third wirings S1(1) to S1(n) are changed, the fourth wiring S2(i) is set to 0 V so that the transistor202is turned off. Moreover, a non-selected fifth wiring and a non-selected fourth wiring are set to 0 V.

As a result, the potential of the node (referred to as the node A) connected to the gate electrode of the transistor201in a memory cell to which data “1” has been written is set to approximately 2 V, and the potential of the node A in a memory cell to which data “0” has been written is set to approximately 0 V. The potential of the node A in a non-selected memory cell is not changed.

When data is read from the memory cells200(i,1) to200(i,n) of the i-th row, the first wiring potential Vs is set to 0 V; the fifth wiring WL(i) is set to 2 V; the fourth wiring S2(i) and the third wirings S1(1) to S1(n) are set to 0 V; and the reading circuit connected to the second wirings BL(1) to BL(n) is set to an operation state. The reading circuit can read data “0” or data “1” from the difference of the resistance state of the memory cell, for example. Note that a non-selected fifth wiring and a non-selected fourth wiring are set to 0 V. Note that the second wiring at the time of the writing is set to 0 V; alternatively, it may be in a floating state or may be charged to have a potential higher than 0 V. The third wiring at the time of the reading is set to 0 V; alternatively, it may be in a floating state or may be charged to have a potential higher than 0 V.

Note that data “1” and data “0” are defined for convenience and may be reversed. Moreover, the above-described operation voltages are one example. The operation voltages are set so that the transistor201is turned off in the case of data “0” and turned on in the case of data “1”, the transistor202is turned on at the time of writing and turned off in periods except the time of writing, and the transistor203is turned on at the time of reading. In particular, the power supply potential VDD of a peripheral logic circuit may be used instead of 2 V.

Next, another example of a circuit configuration and operation of the storage element according to one embodiment of the present invention will be described.

FIG.13illustrates an example of a memory cell circuit included in a semiconductor device. A memory cell220illustrated inFIG.13includes the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, the fifth wiring WL, the transistor201(the first transistor), the transistor202(the second transistor), and the transistor203(the third transistor). The transistors201and203are formed using a material other than an oxide semiconductor. The transistor202is formed using an oxide semiconductor.

In the circuit of the memory cell220inFIG.13, the directions of the third wiring and the fourth wiring are different from those in the circuit of the memory cell200inFIG.10. In other words, in the circuit of the memory cell220inFIG.13, the third wiring is placed in the direction of the fifth wiring (in the row direction) and the fourth wiring is placed in the direction of the second wiring (in the column direction).

A gate electrode of the transistor201and one of a source electrode and a drain electrode of the transistor202are electrically connected to each other. The first wiring and a source electrode of the transistor201are electrically connected to each other. A drain electrode of the transistor201and a source electrode of the transistor203are electrically connected to each other. The second wiring and a drain electrode of the transistor203are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor202are electrically connected to each other. The fourth wiring and a gate electrode of the transistor202are electrically connected to each other. The fifth wiring and a gate electrode of the transistor203are electrically connected to each other.

The circuit operation of the memory cell220inFIG.13is similar to that of the memory cell200inFIG.10; therefore, the detailed description is not repeated.

FIG.14is a block circuit diagram of a semiconductor device with a storage capacity of (m×n) bits according to one embodiment of the present invention.

The semiconductor device according to one embodiment of the present invention includes m third wirings, m fifth wirings, n second wirings, n fourth wirings, a memory cell array230in which a plurality of memory cells220(1,1) to220(m,n) are arranged in a matrix of m rows by n columns (m and n are each a natural number), and peripheral circuits such as a circuit231for driving the second wirings and the fourth wirings, a circuit233for driving the third wirings and the fifth wirings, and a reading circuit232. As another peripheral circuit, a refresh circuit or the like may be provided.

In the semiconductor device inFIG.14, the directions of the third wiring and the fourth wiring are different from those in the semiconductor device inFIG.12. In other words, in the semiconductor device inFIG.14, the third wiring is placed in the direction of the fifth wiring (in the row direction) and the fourth wiring is placed in the direction of the second wiring (in the column direction).

The memory cell220(i,j) is considered as a typical example of the memory cells. Here, the memory cell220(i,j) (i is an integer of 1 to m and j is an integer of 1 to n) is connected to the second wiring BL(j), the fourth wiring S2(j), the fifth wiring WL(i), the third wiring S1(i), and the first wiring. The first wiring potential Vs is supplied to the first wiring. The second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2(n) are connected to the circuit231for driving the second wirings and the fourth wirings and the reading circuit232. The fifth wirings WL(1) to WL(m) and the third wirings S1(1) to S1(m) are connected to the circuit233for driving the third wirings and the fifth wirings.

Operation of the semiconductor device illustrated inFIG.14will be described. In this structure, data is written per column and read per row.

When data is written into the memory cells220(1,j) to220(m,j) of the j-th column, the first wiring potential Vs is set to 0 V; the fifth wirings WL(1) to WL(m) and the second wiring BL(j) are set to 0 V; and the fourth wiring52(j) is set to 2 V. Among the third wirings S1(1) to S1(m), a row in which data “1” is to be written is set to 2 V and a row in which data “0” is to be written is set to 0 V. Note that at the end of the writing, before the potentials of the third wirings S1(1) to S1(m) are changed, the fourth wiring52(j) is set to 0 V so that the transistor202is turned off. Moreover, a non-selected second wiring and a non-selected fourth wiring are set to 0 V.

As a result, the potential of the node (referred to as the node A) connected to the gate electrode of the transistor201in a memory cell to which data “1” has been written is set to approximately 2 V, and the potential of the node A in a memory cell to which data “0” has been written is set to approximately 0 V. The potential of the node A in a non-selected memory cell is not changed.

When data is read from the memory cells200(i,1) to200(i,n) of the i-th row, the first wiring is set to 0 V; the fifth wiring WL(i) is set to 2 V; the fourth wirings S2(1) to S2(n) and the third wiring S1(i) are set to 0 V; and the reading circuit connected to the second wirings BL(1) to BL(n) is set to an operation state. The reading circuit can read data “0” or data “1” from the difference of the resistance state of the memory cell, for example. Note that a non-selected fifth wiring and a non-selected third wiring are set to 0 V. Note that the second wiring at the time of the writing is set to 0 V; alternatively, it may be in a floating state or may be charged to have a potential higher than 0 V. The third wiring at the time of the reading is set to 0 V; alternatively, it may be in a floating state or may be charged to have a potential higher than 0 V.

Note that data “1” and data “0” are defined for convenience and may be reversed. Moreover, the above-described operation voltages are one example. The operation voltages are set so that the transistor201is turned off in the case of data “0” and turned on in the case of data “1”, the transistor202is turned on at the time of writing and turned off in periods except the time of writing, and the transistor203is turned on at the time of reading. In particular, the power supply potential VDD of a peripheral logic circuit may be used instead of 2 V.

Since the off-state current of a transistor including an oxide semiconductor is extremely low, stored data can be retained for an extremely long time by using the transistor. In other words, power consumption can be adequately reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied.

Further, high voltage is not needed to write data, and deterioration of the element does not become a problem. Furthermore, data is written depending on the on state and the off state of the transistor, whereby high-speed operation can be easily realized. In addition, there is no need of operation for erasing data, which is necessary in a flash memory and the like.

Since a transistor including a material other than an oxide semiconductor can operate at sufficiently high speed, stored data can be read out at high speed by using the transistor.

Embodiment 3

In this embodiment, an example of a circuit configuration and operation of a storage element that is different from those in Embodiment 2 will be described.

FIG.15illustrates an example of a circuit diagram of a memory cell included in a semiconductor device. A memory cell240illustrated inFIG.15includes the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, the fifth wiring WL, the transistor201(the first transistor), the transistor202(the second transistor), and a capacitor204. The transistor201is formed using a material other than an oxide semiconductor. The transistor202is formed using an oxide semiconductor.

A gate electrode of the transistor201, one of a source electrode and a drain electrode of the transistor202, and one of electrodes of the capacitor204are electrically connected to each other. The first wiring and a source electrode of the transistor201are electrically connected to each other. The second wiring and a drain electrode of the transistor201are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor202are electrically connected to each other. The fourth wiring and a gate electrode of the transistor202are electrically connected to each other. The fifth wiring and the other of the electrodes of the capacitor204are electrically connected to each other.

Next, operation of the circuit will be specifically described.

When data is written into the memory cell240, the first wiring, the fifth wiring, and the second wiring are set to 0 V and the fourth wiring is set to 2 V. The third wiring is set to 2 V in order to write data “1” and set to 0 V in order to write data “0”. At this time, the transistor202is turned on. Note that at the end of the writing, before the potential of the third wiring is changed, the fourth wiring is set to 0 V so that the transistor202is turned off.

As a result, the potential of the node (referred to as the node A) connected to the gate electrode of the transistor201is set to approximately 2 V after the writing of the data “1” and set to approximately 0 V after the writing of the data “0”.

When data is read from the memory cell240, the first wiring, the fourth wiring, and the third wiring are set to 0 V; the fifth wiring is set to 2 V; and a reading circuit connected to the second wiring is set to an operation state. At this time, the transistor202is turned off.

The state of the transistor201in the case where the fifth wiring is set to 2 V will be described. The potential of the node A, which determines the state of the transistor201, depends on a capacitance C1 between the fifth wiring and the node A and a capacitance C2 between the gate and the source and drain of the transistor201.

FIG.16illustrates a relation between the potential of the fifth wiring and the potential of the node A. Here, as an example, C1/C2>>1 is satisfied when the transistor201is off and C1/C2=1 is satisfied when the transistor201is on. The threshold voltage of the transistor201is 2.5 V. Under the condition where the fifth wiring is set to 2 V as in the graph illustrated inFIG.16, the node A is set to approximately 2 V in the case where data “0” has been written, and the transistor201is off. On the other hand, the node A is set to approximately 3.25 V in the case where data “1” has been written, and the transistor201is on. The memory cell has a low resistance when the transistor201is on and has a high resistance when the transistor201is off. Therefore, the reading circuit can read data “0” or data “1” from the difference of the resistance state of the memory cell. Note that when data is not read out, that is, when the potential of the fifth wiring is 0 V, the node A is set to approximately 0 V in the case where data “0” has been written and set to approximately 2 V in the case where data “1” has been written, and the transistor201is off in both of the cases.

Note that the third wiring at the time of the reading is set to 0 V; alternatively, it may be in a floating state or may be charged to have a potential higher than 0 V. Data “1” and data “0” are defined for convenience and may be reversed.

The above-described operation voltages are one example. The potential of the third wiring at the time of writing can be selected from the potentials of data “0” and data “1” as long as the transistor202is turned off after the writing and the transistor201is off in the case where the potential of the fifth wiring is set to 0 V. The potential of the fifth wiring at the time of reading can be selected so that the transistor201is turned off in the case where data “0” has been written and is turned on in the case where data “1” has been written. Furthermore, the above-described threshold voltage of the transistor201is an example. The transistor201can have any threshold voltage as long as the above state of the transistor201is not changed.

A semiconductor device illustrated inFIG.17according to one embodiment of the present invention includes m fourth wirings, m fifth wirings, n second wirings, n third wirings, a memory cell array250in which a plurality of memory cells240(1,1) to240(m,n) are arranged in a matrix of m rows by n columns (m and n are each a natural number), and peripheral circuits such as the circuit211for driving the second wirings and the third wirings, the circuit213for driving the fourth wirings and the fifth wirings, and the reading circuit212. As another peripheral circuit, a refresh circuit or the like may be provided.

The memory cell240(i,j) is considered as a typical example of the memory cells. Here, the memory cell240(i,j) (i is an integer of 1 to m and j is an integer of 1 to n) is connected to the second wiring BL(j), the third wiring SI(j), the fifth wiring WL(i), the fourth wiring S2(i), and the first wiring. The first wiring potential Vs is supplied to the first wiring. The second wirings BL(1) to BL(n) and the third wirings S1(1) to S1(n) are connected to the circuit211for driving the second wirings and the third wirings and the reading circuit212. The fifth wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the circuit213for driving the fourth wirings and the fifth wirings.

Operation of the semiconductor device illustrated inFIG.17will be described. In this structure, data is written and read per row.

When data is written into the memory cells240(i,1) to240(i,n) of the i-th row, the first wiring potential Vs is set to 0 V; the fifth wiring WL(i) and the second wirings BL(1) to BL(n) are set to 0 V; and the fourth wiring S2(i) is set to 2 V. At this time, the transistor202is turned on. Among the third wirings S1(1) to S1(n), a column in which data “1” is to be written is set to 2 V and a column in which data “0” is to be written is set to 0 V. Note that at the end of the writing, before the potentials of the third wirings S1(1) to S1(n) are changed, the fourth wiring S2(i) is set to 0 V so that the transistor202is turned off. Moreover, a non-selected fifth wiring and a non-selected fourth wiring are set to 0 V.

As a result, the potential of the node (referred to as the node A) connected to the gate electrode of the transistor201in a memory cell to which data “1” has been written is set to approximately 2 V, and the potential of the node A after data “0” is written is set to approximately 0 V. The potential of the node A in a non-selected memory cell is not changed.

When data is read from the memory cells240(i,1) to240(i,n) of the i-th row, the first wiring potential Vs is set to 0 V; the fifth wiring WL(i) is set to 2 V; the fourth wiring S2(i) and the third wirings S1(1) to S1(n) are set to 0 V; and the reading circuit connected to the second wirings BL(1) to BL(n) is set to an operation state. At this time, the transistor202is turned off. Note that a non-selected fifth wiring and a non-selected fourth wiring are set to 0 V.

The state of the transistor201at the time of reading will be described. Assuming that C1/C2>>1 is satisfied when the transistor201is off and C1/C2=1 is satisfied when the transistor201is on as has been described, the relation between the potential of the fifth wiring and the potential of the node A is represented byFIG.16. The threshold voltage of the transistor201is 2.5 V. In non-selected memory cells, the potential of the fifth wiring is set to 0 V. Thus, the node A in a memory cell having data “0” is set to approximately 0 V and the node A in a memory cell having data “1” is set to approximately 2 V, and the transistor201is off in both of the cases. In the memory cells of the i-th row, the potential of the fifth wiring is set to 2 V. Thus, the node A in a memory cell having data “0” is set to approximately 2 V and the transistor201is off, whereas the node A in a memory cell having data “1” is set to approximately 3.25 V and the transistor201is on. The memory cell has a low resistance when the transistor201is on and has a high resistance when the transistor201is off. As a result, only a memory cell having data “0” has a low resistance among the memory cells of the i-th row. The reading circuit can read data “0” or data “1” depending on the difference of load resistance connected to the second wiring.

Note that the third wiring at the time of the reading is set to 0 V; alternatively, it may be in a floating state or may be charged to have a potential higher than 0 V. Data “1” and data “0” are defined for convenience and may be reversed.

The above-described operation voltages are one example. The potential of the third wiring at the time of writing can be selected from the potentials of data “0” and data “1” as long as the transistor202is turned off after the writing and the transistor201is off in the case where the potential of the fifth wiring is set to 0 V. The potential of the fifth wiring at the time of reading can be selected so that the transistor201is turned off in the case where data “0” has been written and is turned on in the case where data “1” has been written. Furthermore, the above-described threshold voltage of the transistor201is an example. The transistor201can have any threshold voltage as long as the above state of the transistor201is not changed.

Since the off-state current of a transistor including an oxide semiconductor is extremely low, stored data can be retained for an extremely long time by using the transistor. In other words, power consumption can be adequately reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied.

Further, high voltage is not needed to write data, and deterioration of the element does not become a problem. Furthermore, data is written depending on the on state and the off state of the transistor, whereby high-speed operation can be easily realized. In addition, there is no need of operation for erasing data, which is necessary in a flash memory and the like.

Since a transistor including a material other than an oxide semiconductor can operate at sufficiently high speed, stored data can be read out at high speed by using the transistor.

Next, another example of a circuit configuration and operation of the storage element according to one embodiment of the present invention will be described.

FIG.18illustrates an example of a memory cell circuit included in a semiconductor device. A memory cell260illustrated inFIG.18includes the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, the fifth wiring WL, the transistor201, the transistor202, and the capacitor204. The transistor201is formed using a material other than an oxide semiconductor. The transistor202is formed using an oxide semiconductor.

In the circuit of the memory cell260inFIG.18, the directions of the third wiring and the fourth wiring are different from those in the circuit of the memory cell240inFIG.15. That is, in the memory cell260inFIG.18, the third wiring is placed in the direction of the fifth wiring (in the row direction) and the fourth wiring is placed in the direction of the second wiring (in the column direction).

A gate electrode of the transistor201, one of a source electrode and a drain electrode of the transistor202, and one electrode of the capacitor204are electrically connected to each other. The first wiring and a source electrode of the transistor201are electrically connected to each other. The second wiring and a drain electrode of the transistor201are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor202are electrically connected to each other. The fourth wiring and a gate electrode of the transistor202are electrically connected to each other. The fifth wiring and the other electrode of the capacitor204are electrically connected to each other.

The circuit operation of the memory cell260inFIG.18is similar to that of the memory cell240inFIG.15; therefore, the detailed description is not repeated.

FIG.19is a block circuit diagram of a semiconductor device with a storage capacity of (m×n) bits according to one embodiment of the present invention.

The semiconductor device according to one embodiment of the present invention includes m third wirings, m fifth wirings, n second wirings, n fourth wirings, a memory cell array270in which a plurality of memory cells260(1,1) to260(m,n) are arranged in a matrix of m rows by n columns (m and n are each a natural number), and peripheral circuits such as the circuit231for driving the second wirings and the fourth wirings, the circuit233for driving the third wirings and the fifth wirings, and the reading circuit232. As another peripheral circuit, a refresh circuit or the like may be provided.

In the semiconductor device inFIG.19, the directions of the third wiring and the fourth wiring are different from those in the semiconductor device inFIG.17. That is, in the semiconductor device inFIG.19, the third wiring is placed in the direction of the fifth wiring (in the row direction) and the fourth wiring is placed in the direction of the second wiring (in the column direction).

The memory cell260(i,j) is considered as a typical example of the memory cells. Here, the memory cell260(i,j) (i is an integer of 1 to m and j is an integer of 1 to n) is connected to the second wiring BL(j), the fourth wiring S2(j), the fifth wiring WL(i), the third wiring S1(i), and the first wiring. The first wiring potential Vs is supplied to the first wiring. The second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2(n) are connected to the circuit231for driving the second wirings and the fourth wirings and the reading circuit232. The fifth wirings WL(1) to WL(m) and the third wirings S1(1) to S1(m) are connected to the circuit233for driving the third wirings and the fifth wirings.

The operation of the semiconductor device inFIG.19is similar to that of the semiconductor device inFIG.17; therefore, the detailed description is not repeated.

Since the off-state current of a transistor including an oxide semiconductor is extremely low, stored data can be retained for an extremely long time by using the transistor. In other words, power consumption can be adequately reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied.

High voltage is not needed to write data, and deterioration of the element does not become a problem. Furthermore, data is written depending on the on state and the off state of the transistor, whereby high-speed operation can be easily realized. In addition, there is no need of operation for erasing data, which is necessary in a flash memory and the like.

Since a transistor including a material other than an oxide semiconductor can operate at sufficiently high speed, stored data can be read out at high speed by using the transistor.

Embodiment 4

In this embodiment, an example of a circuit configuration and operation of a storage element that is different from those in Embodiments 2 and 3 will be described.

FIGS.20A and20Beach illustrate an example of a circuit diagram of a memory cell included in a semiconductor device. In a memory cell280aillustrated inFIG.20Aand a memory cell280billustrated inFIG.20B, the first transistor and the third transistor that are connected in series are replaced with each other, as compared to those in the memory cell200inFIG.10and the memory cell220inFIG.13, respectively.

In the memory cell280ainFIG.20A, a gate electrode of the transistor201and one of a source electrode and a drain electrode of the transistor202are electrically connected to each other. The first wiring and a source electrode of the transistor203are electrically connected to each other. A drain electrode of the transistor203and a source electrode of the transistor201are electrically connected to each other. The second wiring and a drain electrode of the transistor201are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor202are electrically connected to each other. The fourth wiring and a gate electrode of the transistor202are electrically connected to each other. The fifth wiring and a gate electrode of the transistor203are electrically connected to each other.

In the memory cell280binFIG.20B, the directions of the third wiring and the fourth wiring are different from those in the memory cell circuit inFIG.20A. In other words, in the memory cell circuit inFIG.20B, the fourth wiring is placed in the direction of the second wiring (in the column direction) and the third wiring is placed in the direction of the fifth wiring (in the row direction).

The circuit operations of the memory cell280ainFIG.20Aand the memory cell280binFIG.20Bare similar to those of the memory cell200inFIG.10and the memory cell220inFIG.13, respectively; therefore, the detailed description is not repeated.

Embodiment 5

In this embodiment, an example of a circuit configuration and operation of a storage element that is different from those in Embodiments 2 to 4 will be described.

FIG.21illustrates an example of a circuit diagram of a memory cell included in a semiconductor device. A circuit of a memory cell290inFIG.21additionally includes a capacitor between the node A and the first wiring as compared to the memory cell200inFIG.10.

The memory cell290illustrated inFIG.21includes the first wiring SL, the second wiring BL, the third wiring S1, the fourth wiring S2, the fifth wiring WL, the transistor201, the transistor202, the transistor203, and a capacitor205. The transistors201and203are formed using a material other than an oxide semiconductor. The transistor202is formed using an oxide semiconductor.

A gate electrode of the transistor201, one of a source electrode and a drain electrode of the transistor202, and one electrode of the capacitor205are electrically connected to each other. The first wiring, a source electrode of the transistor201, and the other electrode of the capacitor205are electrically connected to each other. A drain electrode of the transistor201and a source electrode of the transistor203are electrically connected to each other. The second wiring and a drain electrode of the transistor203are electrically connected to each other. The third wiring and the other of the source electrode and the drain electrode of the transistor202are electrically connected to each other. The fourth wiring and a gate electrode of the transistor202are electrically connected to each other. The fifth wiring and a gate electrode of the transistor203are electrically connected to each other.

The operation of the memory cell circuit inFIG.21is similar to that of the memory cell circuit inFIG.10; therefore, the detailed description is not repeated. When the memory cell includes the capacitor205, data retention characteristics are improved.

Embodiment 6

An example of a reading circuit included in a semiconductor device according to one embodiment of the present invention will be described with reference toFIG.22.

A reading circuit illustrated inFIG.22includes a transistor206and a differential amplifier207.

At the time of reading, a terminal A is connected to a second wiring connected to a memory cell from which data is read. Moreover, a bias voltage Vbias is applied to a gate electrode of the transistor206, and a predetermined current flows through the transistor206.

A memory cell has a different resistance corresponding to data “1” or data “0” stored therein. Specifically, when the transistor201in a selected memory cell is on, the memory cell has a low resistance; whereas when the transistor201in a selected memory cell is off, the memory cell has a high resistance.

When the memory cell has a high resistance, the potential of the terminal A is higher than a reference potential Vref and data “1” is output from an output of the differential amplifier. On the other hand, when the memory cell has a low resistance, the potential of the terminal A is lower than the reference potential Vref and data “0” is output from the output of the differential amplifier.

In such a manner, the reading circuit can read data from the memory cell. Note that the reading circuit in this embodiment is an example, and a known circuit may be used. For example, the reading circuit may include a precharge circuit. A second wiring for reference may be connected instead of the reference potential Vref A latch sense amplifier may be used instead of the differential amplifier.

Embodiment 7

In this embodiment, examples of electronic devices each including the semiconductor device according to any of the above-described embodiments will be described with reference toFIGS.23A to23F. The semiconductor device according to the above embodiment can retain data even when power is not supplied. Moreover, degradation due to writing or erasing does not occur. Furthermore, the semiconductor device can operate at high speed. For these reasons, an electronic device with a novel structure can be provided by using the semiconductor device. Note that the semiconductor devices according to the above embodiment are integrated and mounted on a circuit board or the like, and placed inside an electronic device.

FIG.23Aillustrates a notebook personal computer including the semiconductor device according to the above embodiment. The notebook personal computer includes a main body301, a housing302, a display portion303, a keyboard304, and the like. The semiconductor device according to one embodiment of the present invention is applied to a notebook personal computer, whereby the notebook personal computer can hold data even when power is not supplied. Moreover, degradation due to writing or erasing does not occur. Further, the notebook personal computer can operate at high speed. For these reasons, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a notebook personal computer.

FIG.23Billustrates a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. A main body311is provided with a display portion313, an external interface315, operation buttons314, and the like. A stylus312that is an accessory is used for operating the PDA. The semiconductor device according to one embodiment of the present invention is applied to a PDA, whereby the PDA can hold data even when power is not supplied. Moreover, degradation due to writing or erasing does not occur. Further, the PDA can operate at high speed. For these reasons, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a PDA.

FIG.23Cillustrates an e-book reader320as an example of electronic paper including the semiconductor device according to the above embodiment. The e-book reader320includes two housings: a housing321and a housing323. The housing321and the housing323are combined with a hinge337so that the e-book reader320can be opened and closed with the hinge337as an axis. With such a structure, the e-book reader320can be used like a paper book. The semiconductor device according to one embodiment of the present invention is applied to electronic paper, whereby the electronic paper can hold data even when power is not supplied. Moreover, degradation due to writing or erasing does not occur. Further, the electronic paper can operate at high speed. For these reasons, it is preferable to apply the semiconductor device according to one embodiment of the present invention to electronic paper.

A display portion325is incorporated in the housing321and a display portion327is incorporated in the housing323. The display portion325and the display portion327may display one image or different images. When the display portion325and the display portion327display different images, for example, the right display portion (the display portion325inFIG.23C) can display text and the left display portion (the display portion327inFIG.23C) can display images.

FIG.23Cillustrates an example in which the housing321is provided with an operation portion and the like. For example, the housing321is provided with a power switch331, operation keys333, a speaker335, and the like. Pages can be turned with the operation key333. Note that a keyboard, a pointing device, or the like may also be provided on the surface of the housing, on which the display portion is provided. Furthermore, an external connection terminal (e.g., an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing. Further, the e-book reader320may have a function of an electronic dictionary.

The e-book reader320may send and receive data wirelessly. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.

Note that electronic paper can be applied to devices in a variety of fields as long as they display information. For example, electronic paper can be used for posters, advertisement in vehicles such as trains, display in a variety of cards such as credit cards, and the like in addition to e-book readers.

FIG.23Dillustrates a mobile phone including the semiconductor device according to the above embodiment. The mobile phone includes two housings: a housing340and a housing341. The housing341is provided with a display panel342, a speaker343, a microphone344, a pointing device346, a camera lens347, an external connection terminal348, and the like. The housing340is provided with a solar cell349for charging the mobile phone, an external memory slot350, and the like. In addition, an antenna is incorporated in the housing341. The semiconductor device according to one embodiment of the present invention is applied to a mobile phone, whereby the mobile phone can hold data even when power is not supplied. Moreover, degradation due to writing or erasing does not occur. Further, the mobile phone can operate at high speed. For these reasons, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a mobile phone.

The display panel342has a touch panel function. A plurality of operation keys345displayed as images are shown by dashed lines inFIG.23D. Note that the mobile phone includes a booster circuit for boosting a voltage output from the solar cell349to a voltage necessary for each circuit. Moreover, the mobile phone can include a contactless IC chip, a small recording device, or the like in addition to the above structure.

The direction of display on the display panel342is changed as appropriate depending on applications. Further, the camera lens347is provided on the same surface as the display panel342, so that the mobile phone can be used as a videophone. The speaker343and the microphone344can be used for videophone calls, recording and playing sound, and the like as well as voice calls. Moreover, the housings340and341in a state where they are developed as illustrated inFIG.23Dcan be slid so that one is lapped over the other. Therefore, the size of the mobile phone can be reduced, which makes the mobile phone suitable for being carried.

The external connection terminal348can be connected to a variety of cables such as an AC adapter or a USB cable, so that the mobile phone can be charged or can perform data communication. Moreover, the mobile phone can store and move a larger amount of data by inserting a recording medium into the external memory slot350. Further, the mobile phone may have an infrared communication function, a television reception function, or the like in addition to the above functions.

FIG.23Eillustrates a digital camera including the semiconductor device according to the above embodiment. The digital camera includes a main body361, a display portion (A)367, an eyepiece portion363, an operation switch364, a display portion (B)365, a battery366, and the like. The semiconductor device according to one embodiment of the present invention is applied to a digital camera, whereby the digital camera can hold data even when power is not supplied. Moreover, degradation due to writing or erasing does not occur. Further, the digital camera can operate at high speed. For these reasons, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a digital camera.

FIG.23Fillustrates a television set including the semiconductor device according to the above embodiment. In a television set370, a display portion373is incorporated in a housing371. Images can be displayed on the display portion373. Here, the housing371is supported by a stand375.

The television set370can be operated by an operation switch of the housing371or a separate remote controller380. With operation keys379of the remote controller380, channels and volume can be controlled and images displayed on the display portion373can be controlled. Moreover, the remote controller380may include a display portion377for displaying data output from the remote controller380. The semiconductor device according to one embodiment of the present invention is applied to a television set, whereby the television set can hold data even when power is not supplied. Moreover, degradation due to writing or erasing does not occur. Furthermore, the television set can operate at high speed. For these reasons, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a television set.

Note that the television set370is preferably provided with a receiver, a modem, and the like. A general television broadcast can be received with the receiver. Moreover, when the television set is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) data communication can be performed.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

This application is based on Japanese Patent Application serial No. 2009-251261 filed with Japan Patent Office on Oct. 30, 2009, the entire contents of which are hereby incorporated by reference.

EXPLANATION OF REFERENCE

100: substrate,102: protective layer,104: semiconductor region,106: element isolation insulating layer,108a: gate insulating layer,110a: gate electrode,112: insulating layer,114: impurity region,116: channel formation region,118: sidewall insulating layer,120: high-concentration impurity region,122: metal layer,124: metal compound region,126: interlayer insulating layer,128: interlayer insulating layer,130a: source/drain electrode,130b: source/drain electrode,130c: electrode,130d: electrode,132: insulating layer,134: conductive layer,136a: electrode,136b: electrode,136c: electrode,136d: gate electrode.138: gate insulating layer,140: oxide semiconductor layer.142a: source/drain electrode,142b: source/drain electrode,144: protective insulating layer,146: interlayer insulating layer,148: conductive layer,150a: electrode,150b: electrode.150c: electrode,150d: electrode,150e: electrode,152: insulating layer,154a: electrode,154b: electrode,154c: electrode,154d: electrode,154e: electrode,160: transistor,162: transistor,200: memory cell.201: transistor,202: transistor.203: transistor,204: capacitor,205: capacitor,206: transistor,210: memory cell array,211: circuit for driving second wiring and third wiring,212: reading circuit.213: circuit for driving fourth wiring and fifth wiring,220: memory cell,230: memory cell array,231: circuit for driving second wiring and fourth wiring,232: reading circuit,233: circuit for driving third wiring and fifth wiring,240: memory cell,250: memory cell array,260: memory cell,270: memory cell array,280a: memory cell,280b: memory cell,290: memory cell,301: main body,302: housing,303: display portion,304: keyboard,311: main body,312: stylus,313: display portion,314: operation button,315: external interface,320: e-book reader,321: housing,323: housing,325: display portion,327: display portion,331: power switch,333: operation key,335: speaker,337: hinge,340: housing,341: housing,342: display panel,343: speaker,344: microphone,345: operation key,346: pointing device,347: camera lens,348: external connection terminal,349: solar cell,350: external memory slot,361: main body,363: eyepiece portion,364: operation switch,365: display portion (B),366: battery,367: display portion (A),370: television set,371: housing,373: display portion,375: stand,377: display portion,379: operation key,380: remote controller