Patent ID: 12254349

The foregoing and other objects, features and advantages of the present invention, as well as the invention itself, will be more fully understood from the following description of preferred embodiments, when read together with the accompanying drawings.

DETAILED DESCRIPTION

The present disclosure relates to the field of on-chip communication architecture, and more particularly to on-chip communication architecture for facilitating the distribution of tasks within a heterogenous system.

The principles of the present invention and their advantages are best understood by referring toFIG.1toFIG.7. In the following detailed description of illustrative or exemplary embodiments of the disclosure, specific embodiments in which the disclosure may be practiced are described in sufficient detail to enable those skilled in the art to practice the disclosed embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims and equivalents thereof. References within the specification to “one embodiment,” “an embodiment,” “embodiments,” or “one or more embodiments” are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure.

FIG.1Ais a block diagram showing the basic structure and functionality of an example of the proposed architecture in accordance with the present disclosure.FIG.1Bshows a reconfigurable interface structure according to an embodiment of the present disclosure.

The structure100is of part of the hardware part of the overall architecture. The structure100comprises a first static part102, a dynamic region110, and a second static part116. The first static part102is a hardware manager102.

The hardware manager102exchanges data104with the dynamic region110. The data104includes task information, data, and a header. The header is metadata of the data. The header includes information on the identification of the data, the destination of the data communicated, the size of the data, and the identifier of the transmitter module. The header information is located in a user-defined hardware library. This library contains all the information concerning the system (number of software and hardware modules, the data size of each module and the communicating modules in matrix format).

The dynamic region110comprises an adapter111. The dynamic region110may also be termed the reconfigurable region110. Each reconfigurable region110has its own adapter111. The role of this adapter111is to adapt the input/output signals and the data size between two different blocks at input and output. The communication architecture requires a specific data format at the output of the adapter. A header is added to the data at the output of the adapter. The size of the header is set by the user.

The dynamic region110comprises a partially reconfigurable region113. The partially reconfigurable region113contains the application module and is a consistent part of an application whose interface with the rest of the application is reduced. The partially reconfigurable region exchanges data112at input and output with adapter111.

The second static part116and comprises modules117to120. The modules117to120can be implemented in hardware as well as software. The modules117to120transmit data114to the partially reconfigurable region113.

FIG.2shows the architecture of the hardware component according to an embodiment of the present disclosure.

The structure200is part of the hardware part of the overall architecture. The structure200comprises a first static part202, a dynamic region210, and a second static part216. The first static part202is a hardware manager202. The dynamic region210comprises a plurality of hardware reconfigurable regions206. A hardware reconfigurable region206comprises a plurality of hardware modules. The second static part216comprises a plurality of hardware sub-components.

The hardware reconfigurable region206comprises a hardware adapter that is configured with a configured hardware library containing all the information to communicate the modules with each other. When a hardware module changes in a hardware reconfigurable region206, the hardware adapter calls the library to identify who the loaded hardware module will communicate with.

The second static part216communicates the hardware modules between them and ensures the exchange of data between the software part and the hardware part. In case of a request sent by software modules, the hardware manager202can send this information to the dedicated hardware interfaces.

The second static part216comprises a memory component unit209at the end of each reconfigurable region206. The role of the memory component209is to act as a first-in first-out mailbox that receives data-in207from the hardware reconfigurable region206and outputs the data-out208. The number of memory components209is configured by the user and depends on the number of reconfigurable regions206and the size of the data.

The second static part216comprises a first communication interface218(for transmission) and a second communication interface219(for reception). Depending on the information communicated by the processor to the hardware part, the communication interfaces218and219can manage the communication either between the hardware modules themselves, or between the software part and the hardware modules and vice versa.

The second static part216also comprises a crossbar220, buffers223, a wrapper225, and an AXI bus224.

FIG.3shows the communication between two hardware modules according to an embodiment of the present disclosure.

The structure300is part of the hardware part of the overall architecture.

The parameters of the first direction of communication from one hardware reconfigurable region306to another comprise the CPU loading the hardware module located in the appropriate software module and sending a control signal301containing the identifier information for each target hardware reconfigurable region306.

The hardware manager302routes the communication information304for the appropriate reconfigurable region306and the hardware adapter configures the data header.

The first communication interface318routes the data320according to the information located in the header. The second communication interface319then routes the data322to the dedicated module according to the information located in the input.

The hardware receiver module, located in the reconfigurable region306, receives the data, performs calculations, and saves its output in the memory component309dedicated to it. At the end of the data transmission, the interconnection between the two reconfigurable regions306will be unlocked.

FIG.4shows the communication between two hardware modules according to the embodiment of the present disclosure.

The structure400is part of the hardware part and software part of the overall architecture. The structure400comprises a CPU430. The software part comprises a CPU430comprises a software manager432and a central interconnect434. The central interconnect acts as a communication bridge between the software part and the hardware part.

To configure the communication interface418and419, the identifier information sent by the CPU430is necessary to authorize the instantiation of several hardware modules in the same hardware reconfigurable region406and to allocate a hardware module to multiple hardware reconfigurable regions406. The identification information ensures the data follows the correct interconnection path to its destination.

If during the communication between a first hardware module406and a second hardware module407, the transmitter module has been replaced by another hardware module, the communication interfaces418and419must adapt to the changes made without having a loss of data. This comprises a method of the CPU430sending a control signal401via the central interconnect434containing new communications parameters to the hardware manager402. The hardware manager402routes the information for the appropriate reconfigurable region and the hardware adapter configures the first hardware module's406data header. The second hardware module checks if the memory component's409memory is empty before starting the calculation. If the memory component's409memory is empty, the second hardware module407begins performing calculations and the communication interface418routes the data420to the correct destination according to the information located in the data header.

In embodiments of the present disclosure, and in embodiments as disclosed herein, if during the communication the receiver module has been replaced by another module, the interface connected with the transmitter module must detect these modifications. The communication between the two modules will be interrupted. The receiving communication interface module must copy the data from the modified module to the DDR memory.

FIG.5shows the communication between a hardware module and a software module according to an embodiment of the present disclosure.

The structure500is part of the hardware part and the software part of the overall architecture. The structure500comprises a method of exchanging data between the hardware part and the software part based on the CPU530based on the FPGA. The software part comprises a CPU and comprises a software manager532, a central interconnect534, software modules536with cache memory542, a PL to memory interconnect (PLM)538, and memory interfaces544.

The software module536send a request to the hardware manager502via the central interconnect534containing the identifier of the requestor.

The hardware manager502communicates this request538to the hardware adapter to configure the data header.

The hardware module checks if the memory component509associated with the hardware module506is empty or not. If the memory is empty, the communication interface518selects the output port (connected with the crossbar520) in order to transport the data to the PLM module538via the AXI bus524. The data travels from the crossbar520, through buffers523, through a wrapper525to arrive at the AXI bus524.

The PLM module538checks whether the cache memory542of the software module536concerned is empty. If the cache memory542is empty, the PLM538will transmit the data directly to the software module536. If the cache memory542is full, the processor can apply one of the cache replacement techniques (first-in first-out (FIFO), last-in first-out (LIFO), random) to replace the new data in place of the old data. Otherwise, the memory interfaces544must copy the data to the external DDR memory540.

In embodiments of the present disclosure, if during the communication between the software part and the hardware part, the hardware reconfigurable region containing the hardware module has been changed, the communication interface must react to prevent the data from being mixed up. The method comprises the processor loading the new hardware module into its region. The hardware adapter configures the data header and the adaptation of the communication interface with the new parameters occurs. If the memory component is empty, the newly loaded hardware module begins performing its calculations. If the memory component is full, the new module will either wait for the memory component to be empty before performing its calculations or the hardware interface will manage copying the data in the memory component to the external DDR memory.

In embodiments of the present disclosure as disclosed herein, if the current software module has been moved to a hardware reconfigurable region, a method comprises the processor loading the new hardware module into its region and the new hardware module checking that the memory component is empty before performing its calculations. Where the memory component is full, the communication interface must dump the existing data into the external DDR memory.

FIG.6shows the communication between a software module and a hardware module according to an embodiment of the present disclosure.

The structure600is part of the hardware part and the software part of the overall architecture. The structure600comprises a method of exchanging data between a software module and a hardware module.

The CPU630loads the hardware module in its region and the software manager632sends the communication information to the hardware manager602via the central interconnect634.

The hardware manager602communicates this information to the hardware adapter to configure the header.

The receiving communication interface619configures the direction of the data (crossbar620side) and simultaneously sends the software part a request626containing the identifier of the requested data. This data is transported via the AXI bus624to the PLM638.

The PLM638refers to the cache and memory controller642to inquire about the location of the data. The memory cache and memory controller642will recover the data if it has located it in the cache memories. Otherwise, the PLM638refers to the memory interfaces644which will look for the data in the external DDR memory640.

The data is transported to the crossbar620via the AXI bus624. The AXI bus624routes the data to the correct destination.

After receiving the data, the hardware module606will perform its calculations if the memory component's memory is empty609.

In embodiments of the present disclosure as disclosed herein, if during the communication between the software module and the hardware module, the hardware reconfigurable region has been loaded by another hardware module, the communication interface reacts, wherein the new module loaded by the CPU waits for the memory component dedicated to it to be empty before beginning its calculations. Backup of data is calculated by the software module in the cache or the external DDR memory. Complete unloading of the memory component dedicated to the hardware reconfigurable region to the external DDR memory before the new hardware module begins these calculations. Configuration of the data header of the new hardware module. Configuration of the communication interface of the new hardware module to start a new communication. The new hardware module begins its new calculations.

FIG.7shows the communication between two software modules according to an embodiment of the present disclosure.

The structure700is part of the software part of the overall architecture. The software part comprises a first software module736, a second software module737, cache and controller memory742and743, memory interfaces744, and external DDR memory740. The structure700comprises a method of exchanging data between two software modules.

The first software module736requires data that is calculated by the second software module737.

The first software module736communicates directly to the second software module737by sending the address of the data it needs. If the second software module's737cache and controller memory743contains the requested information, it sends it to the first software module736. Otherwise, there is a cache defect.

In the event of a cache miss, the cache and controller memory743continues to access the external DDR memory740which sends information stored in the box back to the first software module736. The line containing the address is stored in the cache for future access.

If the cache and controller memory742of the first software module736is busy while the second software module's737data is being transmitted in, the processor applies a data replacement technique (FIFO, LIFO, or random).

In embodiments of the present disclosure, the implementation approach involves a dynamic deployment of tasks depending on the execution context of the system. This approach uses for this the division into software tasks running on the processor part, and into hardware tasks integrated in the form of IP blocks on the FPGA. The same functionality can then be defined in both integration domains (i.e., as a software task and a hardware task). The present disclosure aims to relieve the designer of the modules of an application of the following task: if a module is intended to communicate with a software module, this module will have a certain interface; if this same module is intended to communicate with a hardware module, then it would have to have another interface. It would, therefore, be necessary to have two application versions (compiled) depending on whether the following module is software or hardware. If this module has interfaces, no longer with1, but with N other modules that can each be software or hardware, the combination of compiled modules to be designed would be 2 to the power of N (2n). The present disclosure allows the designer to create only one module (executable and therefore compiled).

In embodiments of the present disclosure, an application vendor may want to create an application with an FPGA module, and for performance, cost, space, or other reasons, the same application with the same module can be implemented (created) in software. For example, if an application is made of three interconnected modules (A, B, and C). Wherein, A and C are in software and B is either in software or in hardware. The supplier would have to develop the interfaces twice (once for software, once for hardware). In addition, there would be two final products: one made of three modules including a hardware module and the other made of three software modules (so six modules in all). The present disclosure aims to standardise these interfaces and make transparent the fact that a module is of the software or hardware type. As a further example, there are three tasks (A, B, and C): modules A and C are developed in software and module B is developed in two types-software and hardware. This makes four modules in total. In addition, in operation, to be able to switch from a homogenous configuration (all software) to a heterogenous configuration (software/hardware), there are only four modules that need to be implemented on the physical medium (electronic board).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. The disclosures and the description herein are intended to be illustrative and are not in any sense limiting the present disclosure, defined in scope by the following claims.

Many changes, modifications, variations and other uses and applications of the present disclosure will become apparent to those skilled in the art after considering this specification and the accompanying drawings, which disclose the preferred embodiments thereof. All such changes, modifications, variations and other uses and applications, which do not depart from the spirit and scope of the present disclosure, are deemed to be covered by the invention, which is to be limited only by the claims which follow.