Patent ID: 12191420

DETAILED DESCRIPTION

With respect to a semiconductor light emitting element that includes an active layer having a multiple quantum well structure in which well layers and barrier layers are alternately stacked, doping the barrier layers with an n-type impurity is believed to reduce the resistance of the light emitting element to thereby reduce the forward voltage. However, an increased n-type impurity concentration of the barrier layers tends to facilitate the consumption of the holes supplied by the p-side semiconductor layer by the well layers positioned closer to the p-side semiconductor layer in the active layer. This consequently makes it difficult to increase the light emission efficiency because holes cannot be readily supplied to the well layers near the center of the active layer.

Embodiments of the present disclosure were developed as a result of diligent study based on the knowledge described above, and may provide light emitting elements having improved light emission efficiency as a whole by adjusting the n-type impurity concentrations of the barrier layers.

A specific structure of the active layer that can effectively function in this manner has a plurality of stacks that include well layers and barrier layers, in which the well layers include a plurality of first well layers positioned closer to the n-side nitride semiconductor layer and a plurality of second well layers positioned closer to the p-side nitride semiconductor layer, and the barrier layers in each stack include a first barrier layer and a second barrier layer that is positioned closer to the p-side nitride semiconductor layer than the first barrier layer.

The first barrier layers include an n-type impurity. With respect to the n-type impurity concentrations of the first barrier layers, the n-type impurity concentrations of the first barrier layers positioned between the first well layers are set higher than the n-type impurity concentrations of the first barrier layers positioned between the second well layers. Furthermore, the n-type impurity concentrations of the second barrier layers are set lower than those of the first barrier layers.

With respect to the relationship between the first and second barrier layers in terms of the n-type impurity concentration, the n-type impurity concentration difference between at least one of the first barrier layers and at least one of the second barrier layers positioned between the first well layers is set higher than the n-type impurity concentration difference between at least one of the first barrier layers and at least one of the second barrier layers positioned between the second well layers. Setting the n-type impurity concentrations in this manner can facilitate the supply of holes to the well layers that are positioned near the center of the active layer. As a result, electron-hole recombination can be efficiently facilitated in the well layers near the center of the active layer; i.e., the well layers that readily contribute to emission of light can be increased and the light emission efficiency can thus be improved. Furthermore, the degradation of the crystallinity of the semiconductor layers can also be lessened and the light emission efficiency can thus be improved.

A more specific embodiment will be explained below. In the nitride semiconductor light emitting elements according to the embodiments described below, the nitride semiconductors that can be used include the group III-V nitride semiconductors (InXAlYGa1-X-YN (0≤X, 0≤Y, X+Y≤1)), those in which B is used for some of the group III elements, and mixed crystals in which the group V element N is replaced with P, As, or Sb. These nitride semiconductor layers can be formed by, for example, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular-beam epitaxy (MBE), or the like.

As a nitride semiconductor light emitting element according to any of the embodiments, a nitride semiconductor light emitting element having relatively high In content in the well layers of the active layer and a peak emission wavelength of at least 500 nm (for example, a green light emitting element in which the InGaN well layers having the In percentage of about 20.0˜28.0%) will be illustrated for explanation purposes. The peak emission wavelength is not limited to the wavelength described above. In the present specification, when a range is described using numbers such as in A to B, the instance in which the value is A and the instance in which the value is B are included.

Nitride Semiconductor Light Emitting Element

First Embodiment

A nitride semiconductor light emitting element according to a first embodiment of the present disclosure will be explained below with reference toFIG.1andFIG.2. The nitride semiconductor light emitting element100according to this embodiment includes a substrate1, an n-side nitride semiconductor layer10disposed on the substrate1, a p-side nitride semiconductor layer20, and an active layer5positioned between the n-side nitride semiconductor layer10and the p-side nitride semiconductor layer20. The n-side nitride semiconductor layer10includes a base layer2, an n-side contact layer3, and an n-side superlattice layer4. The p-side nitride semiconductor layer20includes a p-type barrier layer6and a p-side contact layer7. The active layer5in the nitride semiconductor light emitting element of the present disclosure will be explained first, followed by the detailed description of the substrate1, the n-side nitride semiconductor layer10, and the p-side nitride semiconductor layer20in succession.

Active Layer5

The active layer5includes a plurality of stacks5bweach including a well layer and one or more barrier layers. In the embodiment illustrated inFIG.2, a stack structure has four stacks5bw, in each of which a well layer is stacked on barrier layers.

A nitride semiconductor containing In may be used as a well layer as an example, and suitably setting the In composition ratio allows for the emission of blue to green light. In the case of using (InXAlYGa1-X-YN (0≤X, 0≤Y, X+Y≤1), for example, by setting the In composition ratio x to a desired value, the peak emission wavelength within a range of 430 nm to 570 nm for the nitride semiconductor light emitting element can be achieved, for example, within a range of 500 nm to 570 nm for green light emission.

The well layers (seeFIG.2) in the active layer5include a plurality of first well layers5w1(two layers in the example shown inFIG.2) positioned closer to the n-side nitride semiconductor layer10, and a plurality of second well layers5w2(two layers in the example shown inFIG.2) positioned closer to the p-side nitride semiconductor layer20than the first well layers5w1. In order to reduce the decomposition of InGaN in the first well layers5w1and the second well layers5w2, an interlayer5cmay be stacked on each well layer.

The first well layers5w1may have reduced contribution to emission as compared to the well layers closer to the p-side nitride semiconductor layer20than the first well layers5w1. The thickness of each first well layer5w1is set to fall, for example, within a range of 0.5 to 4.0 nm, preferably within a range of 1.0 to 2.5 nm, more preferably within a range of 1.2 to 1.9 nm. In the embodiment illustrated inFIG.2, the thickness is set as 1.6 nm.

The second well layers5w2are the layers that allow for efficient recombination of the electrons supplied via the first well layers5w1and the holes supplied from the p-side nitride semiconductor layer20to thereby achieve high output light emission. The second well layers5w2may have a larger thickness than the first well layers5w1. Forming the second well layers5w2thicker than the first well layer5w1can increase the quantity of electrons that are recombined with holes in the second well layers that readily contribute to light emission. The thickness of each second well layer5w2is set to fall, for example, within a range of 1.5 to 5.5 nm, preferably within a range of 2.0 to 4.0 nm range, more preferably within a range of 2.5 to 3.2 nm. In the embodiment illustrated inFIG.2, the thickness is set as 3.0 nm.

The barrier layers in the active layer5are formed of a material that can trap carriers in the well layers, and may be formed of, for example, GaN, InGaN, or AlGaN having a larger band gap than the well layers. The barrier layers are interposed between the well layers, and include in each stack a first barrier layer5b1positioned closer to the n-side nitride semiconductor layer10and a second barrier layer5b2positioned closer to the p-side nitride semiconductor than the first barrier layers5b1.

The first barrier layers5b1contain an n-type impurity. The first barrier layers5b1containing an n-type impurity can reduce the forward voltage of the light emitting element. For the n-type impurity, for example, Si or Ge may be used, and in this embodiment, Si is used. With respect to the n-type impurity concentrations of the first barrier layers5b1, the n-type impurity concentration of the first barrier layer5b1positioned between the first well layers5w1is set higher than the n-type impurity concentration of the first barrier layer5b1positioned between the second well layers5w2. The n-type impurity concentration of the first barrier layer5b1positioned between the first well layers5w1may be set to fall, for example, within a range of 1.0×1017to 1.0×1019/cm3, preferably within a range of 3.0×1017to 5.0×1018/cm3, more preferably within a range of 5.0×1017to 2.0×1018/cm3. The n-type impurity concentration of the first barrier layer5b1positioned between the second well layers5w2may be set to fall, for example, within a range of 1.0×1017to 1.0×1019/cm3, preferably within a range of 3.0×1017to 5.0×1018/cm3, more preferably within a range of 4.0×1017to 1.0×1018/cm3. In the embodiment shown inFIG.2as an example, the n-type impurity concentration of the first barrier layer5b1positioned between the first well layers5w1is 1.3×1018/cm3and n-type impurity concentration of the first barrier layer5b1positioned between the second well layers5w2is 8.8×1017/cm3.

The thickness of the first barrier layer5b1positioned between the first well layers5w1may be larger than the thickness of the first barrier layer5b1positioned between the second well layers5w2. Making the first barrier layer5b1positioned between the first well layers5w1thicker than the first barrier layer5b1positioned between the second well layers5w2can facilitate the supply of holes to the second well layers5w2and the well layers near the center of the active layer that can readily contribute to light emission. The thickness of the first barrier layer5b1positioned between the first well layers5w1may be set to fall, for example, within a range of 5 to 30 nm range, preferably within a range of 10 to 25 nm, more preferably within a range of 14 to 18 nm. The thickness of the first barrier layer5b1positioned between the second well layers5w2may be set to fall, for example, within a range of 5 to 30 nm, preferably within a range of 6 to 16 nm, more preferably within a range of 8 to 11 nm. In the embodiment shown inFIG.2as an example, the thickness of the first barrier layer5b1positioned between the first well layers5w1is 15.8 nm, and the thickness of the first barrier layer5b1positioned between the second well layers5w2is 9.5 nm.

The second barrier layers5b2contain a lower concentration n-type impurity than the concentration of the n-type impurity in the first barrier layers5b1. Furthermore, making the second barrier layer5b2positioned between the first well layers5w1an undoped semiconductor layer can reduce the crystallinity degradation of the second barrier layer5b2positioned between the first well layers5w1and the semiconductor layers formed onward. On the other hand, the n-type impurity concentration of the second barrier layer5b2positioned between the second well layers5w2may be set to fall, for example, within a range of 1.0×1017to 1.0×1019/cm3, preferably within a range of 2.0×1017to 1.0×1018/cm3, more preferably within a range of 3.0×1017to 8.0×1017/cm3. In the embodiment shown inFIG.2as an example, the n-type impurity concentration of the second barrier layer5b2positioned between the second well layers5w2is 6.3×1017/cm3. An undoped semiconductor layer means a semiconductor layer formed without supplying an n-type impurity gas during the process of forming the layer. Accordingly, a semiconductor layer incorporating the n-type impurity already present in the reaction chamber even if no n-type impurity gas is supplied during the forming process is also considered as an undoped semiconductor layer. For example, an undoped semiconductor layer can have an n-type impurity concentration of 1.7×1017/cm3at most.

Furthermore, the thickness of the second barrier layer5b2positioned between the first well layers5w1may be set to fall, for example, within a range of 0.5 to 5.0 nm, preferably within a range of 0.5 to 1.5 nm, more preferably within a range of 0.5 to 0.8 nm. The thickness of the second barrier layer5b2positioned between the second well layers5w2may be set to fall, for example, within a range of 0.5 to 5.0 nm, preferably within a range of 0.5 to 1.5 nm, more preferably within a range of 0.5 to 0.8 nm. In the embodiment shown inFIG.2as an example, the second barrier layer5b2positioned between the first well layers5w1, and the second barrier layer5b2positioned between the second well layers5w2are both 0.6 nm in thickness. The thicknesses are not limited to these examples, and they may have different thicknesses.

With respect to such an n-type impurity concentration relationship between the first barrier layer5b1and the second barrier layer5b2, the n-type impurity concentration difference between the first barrier layer5b1and the second barrier layer5b2positioned between the first well layers5w1is set to be higher than the n-type impurity concentration difference between the first barrier layer5b1and the second barrier layer5b2positioned between the second well layers5w2. In the embodiment shown inFIG.2as an example, the n-type impurity concentration difference between the first barrier layer5b1and the second barrier layer5b2positioned between the first well layers5w1is 1.3×1018/cm3(1.3×1018/cm3for the first barrier layer and the second barrier layer is an undoped semiconductor layer), and the n-type impurity concentration difference between the first barrier layer5b1and the second barrier layer5b2positioned between the second well layers5w2is 2.5×1017/cm3(8.8×1017/cm3for the first barrier layer and 6.3×1017/cm3for the second barrier layer).

Here, the reason for setting the n-type impurity concentrations as described above will be explained while considering the valence band of the active layer. In the valence band of a semiconductor constructed with an undoped semiconductor layer as a barrier layer, the large energy level gap between a well layer and a barrier layer makes it difficult for holes to go over the barrier layer. As a result, holes are not readily supplied to the well layers near the center of the active layer.

On the other hand, in the case of the valence band constructed with a first barrier layer5b1containing an n-type impurity and a second barrier layer5b2containing a lower concentration n-type impurity than the concentration of the n-type impurity in the first barrier layer5b1as the barrier layers positioned between the second well layers5w2, the energy level can be reduced at the position where the well layers and the barrier layers are adjacent. This can make the differences between the energy levels of the well layers and the energy levels of the barrier layers smaller as compared to the case in which the barrier layers are undoped semiconductor layers. As a result, holes can readily go over the barrier layers. This can facilitate the supply of electrons even to the well layers near the center of the active layer, thereby improving the light emission efficiency. Furthermore, with respect to the barrier layers positioned between the first well layers5w1, by making the second barrier layer5b2an undoped layer or have a lower n-type impurity concentration than that of the second barrier layer5b2positioned between the second well layers5w2, the degradation of semiconductor crystallinity attributable to doping with an n-type impurity can be reduced. As a result, the n-type impurity concentration difference between the first barrier layer and the second barrier layer positioned between the first well layers is larger than the n-type impurity concentration difference between the first barrier layer and the second barrier layer positioned between the second well layers.

Next, the constituent elements other than the active layer5in the nitride semiconductor light emitting element according to the present disclosure will be explained.

Undoped Semiconductor Layer5u

An undoped semiconductor layer5umay be disposed between the p-side nitride semiconductor layer20and the second well layer5w2that is closest to the p-side nitride semiconductor layer20. Providing an undoped semiconductor layer5ucan suppress the diffusion of the p-type impurity from the p-side nitride semiconductor layer20into the active layer5, thereby reducing the degradation of the reliability of the light emitting element. The material for the undoped semiconductor layer5ucan be any that can properly reduce the diffusion of the p-type impurity, and from the standpoint of the ease of film forming, the same material for the first and second barrier layers (GaN, InGaN, AlGaN, or the like) may be used. A different material may be used. The thickness of the undoped semiconductor layer5umay be set to fall, for example, within a range of 0.5 to 15 nm, preferably within a range of 2 to 10 nm, more preferably within a range of 4 to 6 nm.

Substrate1

For the substrate1(seeFIG.1), for example, an insulating substrate, such as sapphire and spinel (MgAl2O4) having C-, R-, or A-plane as a main surface can be used. Among them, in the case of using a nitride semiconductor for the nitride semiconductor light emitting element100, a C-plane sapphire substrate is preferably used. As the substrate1, SiC (including 6H, 4H, 3C), ZnS, ZnO, GaAs, Si or the like may alternatively be used. The light emitting element does not have to include a substrate1at the end.

N-Side Nitride Semiconductor Layer10

As shown inFIG.1, the n-side nitride semiconductor layer10includes successively from the substrate1side, a base layer2, an n-side contact layer3, and an n-side superlattice layer4. The n-side nitride semiconductor layer10includes at least one n-type semiconductor layer containing an n-type impurity. For the n-type impurity, for example, Si, Ge or the like can be used.

The base layer2is disposed between the substrate1and the n-side contact layer3. Providing a base layer2allows for the formation of a high crystallinity n-side contact layer3on the upper face of the base layer2. The base layer2may be, for example, AlGaN or GaN. A buffer layer may be formed between the base layer2and the substrate1. The buffer layer is a layer for reducing the lattice mismatch between the substrate1and the base layer2, and for example, undoped AlGaN or GaN can be used.

The n-side contact layer3is disposed on the upper face of the base layer2, and contains an n-type impurity at least in one portion. As shown inFIG.1, an n-electrode8is formed on the upper face of the n-side contact layer3. Because the n-side contact layer3supplies electrons from the n-electrode8to the active layer5, it is preferably doped with a relatively high concentration of an n-type impurity. The n-type impurity concentration of the n-side contact layer3can be set to fall, for example, within a range of 6×1018to 1×1019/cm3. The n-side contact layer3is preferably formed of GaN, AlGaN, AlN, or InGaN. The n-side contact layer3may have a multilayer structure in which, for example, undoped GaN and GaN doped with an n-type impurity are alternately stacked. The thickness of the n-side contact layer3may be, for example, 5 μm to 20 μm.

The n-side superlattice layer4is disposed on the upper face of the n-side contact layer3. Providing an n-side superlattice layer4can reduce lattice relaxation between the n-side contact layer3and the active layer5, thereby improving the crystallinity of the active layer5. The n-side superlattice layer4has a structure in which semiconductor layers having different lattice constants are alternately stacked. The n-side superlattice layer4includes, for example, n pairs of an undoped InGaN layer and an undoped GaN layer. The quantity of pairs n may be set to fall, for example, within a range of 10 to 40, preferably within a range of 15 to 35, more preferably within a range of 25 to 35.

P-Side Nitride Semiconductor Layer20

As shown inFIG.1, the p-side nitride semiconductor layer20includes a p-type barrier layer6and a p-side contact layer7successively from the active layer5side. The p-side nitride semiconductor layer20includes at least one p-type semiconductor layer containing a p-type impurity. For the p-type impurity, for example, Mg or the like can be used.

The p-type barrier layer6of the p-side nitride semiconductor layer20is positioned closest to the active layer5. The p-type barrier layer6is a layer disposed to trap electrons, and may be constructed with, for example, GaN or AlGaN containing a p-type impurity such as Mg or the like. The band gap energy of the p-type barrier layer6is larger than the band gap energy of the first barrier layers5b1in the active layer5. The thickness of the p-type barrier layer6can be, for example, 10 nm to 50 nm. The p-type impurity concentration of the p-type barrier layer6can be set, for example, to 2×1020/cm3to 6×1020/cm3.

The p-side contact layer7is a layer on which a p-electrode9is formed. The p-side contact layer7may be constructed with, for example, GaN or AlGaN containing a p-type impurity such as Mg. The thickness of the p-side contact layer7may be, for example, 10 nm to 150 nm.

As explained above, according to the nitride semiconductor light emitting element100of this embodiment, holes can be more readily supplied to the well layers near the center of the active layer. This can facilitate efficient electron-hole recombination in the well layers near the center of the active layer, thereby improving the light emission efficiency. Moreover, the degradation of the crystallinity of the semiconductor layers can be reduced.

Second Embodiment

Next, a second embodiment of the present disclosure will be explained with reference toFIG.3. The explanation of the same constituent elements as those in the first embodiment (the substrate1, the base layer2disposed on the substrate1, the n-side nitride semiconductor layer10, and the p-side nitride semiconductor layer20) will be omitted.

The well layers in the active layer of the second embodiment, for example, may include two first well layers5w1and three second well layers5w2as shown inFIG.3. In other words, the quantity of the second well layers5w2is greater than the quantity of the first well layers5w1. The quantity of the first well layers5w1and the second well layers5w2is not limited to this as long as the quantity of the second well layers5w2that contribute to light emission is greater than the quantity of the first well layers5w1. For example, there may be five first well layers5w1and eight second well layers5w2. Such a layering structure can increase the quantity of second well layers5w2that readily contribute to light emission, thereby increasing the amount of light emitted by the second well layers5w2.

In this embodiment, between the first well layer5w1positioned closest to the p-side nitride semiconductor layer20and the second well layer5w2positioned closest to the n-side nitride semiconductor layer, a third barrier layer5b3and a fourth barrier layer5b4that is positioned closer to the p-side nitride semiconductor layer20than the third barrier layer5b3may be included (seeFIG.3).

The third barrier layer5b3contains an n-type impurity. The n-type impurity concentration of the third barrier layer5b3may be set to fall, for example, within a range of 1.0×1017to 1.0×1019/cm3, preferably within a range of 2.0×1017to 1.0×1018/cm3, more preferably within a range of 3.0×1017to 8.0×1017/cm3. In the embodiment shown inFIG.3as an example, the n-type impurity concentration of the third barrier layer5b3is 6.3×1017/cm3. The thickness of the third barrier layer5b3may be set to fall, for example, within a range of 5 to 30 nm, preferably within a range of 10 to 20 nm, more preferably within a range of 13 to 16 nm. In the embodiment shown inFIG.3as an example, the thickness of the third barrier layer5b3is 15.75 nm.

The fourth barrier layer5b4contains an n-type impurity. The n-type impurity concentration of the fourth barrier layer5b4may be set to fall, for example, within a range of 1.0×1017to 1.0×1019/cm3, preferably within a range of 2.0×1017to 1.0×1018/cm3, more preferably within a range of 3.0×1017to 8.0×1017/cm3. In the embodiment shown inFIG.3as an example, the n-type impurity concentration of the fourth barrier layer5b4is 6.3×1017/cm3. The thickness of the fourth barrier layer5b4may be set to fall, for example, within a range of 0.5 to 5.0 nm, preferably within a range of 0.5 to 1.5 nm, more preferably within a range of 0.5 to 0.8 nm. In the embodiment shown inFIG.3as an example, the thickness of the fourth barrier layer5b4is 0.6 nm.

In this embodiment, the thickness of the third barrier layer5b3may be set larger than the thickness of each first barrier layer5b1positioned between the second well layers5w2. In the embodiment shown inFIG.3as an example, the thickness of each first barrier layer5b1positioned between the second well layers5w2is 9.5 nm as compared to the thickness of the third barrier layer5b3that is 15.75 nm. Forming the third barrier layer5b3thicker than the first barrier layers5b1positioned between the second well layers5w2can improve the crystallinity of the third barrier layer5b3and the layers formed onward. The crystallinity can be evaluated based on, for example, an x-ray diffraction (XRD) spectrum analysis. Sharp diffraction peaks appear when a layer subject to measurement has a high degree of crystallinity, and broad diffraction peaks appear when the layer has a low degree of crystallinity.

In this embodiment, furthermore, the n-type impurity concentration of the third barrier layer5b3is lower than the n-type impurity concentration of the first barrier layer5b1positioned between the first well layers5w1. Making the n-type impurity concentration of the third barrier layer5b3lower than the n-type impurity concentration of the first barrier layer5b1positioned between the first well layers5w1can improve the crystallinity of the third barrier layer5b3and the layers formed onward. In the embodiment shown inFIG.3as an example, the n-type impurity concentration of the third barrier layer5b3is 6.3×1017/cm3as compared to the n-type impurity concentration of the first barrier layer5b1positioned between the first well layers5w1of 1.3×1018/cm3. The second barrier layer5b2positioned between the first well layers5w1is preferably an undoped semiconductor layer to allow holes to be readily supplied to the second well layers5w2and the well layers near the center of the active layer that readily contribute to light emission.

Similar to the first embodiment 1, an undoped semiconductor layer5umay be disposed between the p-side nitride semiconductor layer20and the second well layer5w2closest to the p-side nitride semiconductor layer20.

Method of Manufacturing Nitride Semiconductor Light Emitting Element

A method of manufacturing a nitride semiconductor light emitting element according to the present disclosure, as shown inFIG.4, includes forming an n-side nitride semiconductor layer, forming an active layer, forming a p-side nitride semiconductor layer, and forming an electrode. The n-side nitride semiconductor layer forming process includes forming a base layer, forming an n-side contact layer, and forming an n-side superlattice layer. The p-side nitride semiconductor layer forming process includes forming a p-type barrier layer and forming a p-side contact layer. The method of manufacturing a nitride semiconductor light emitting element according to the present disclosure will be explained below in succession. Specifically, the method of manufacturing the embodiment illustrated inFIG.3will be explained.

N-Side Nitride Semiconductor Layer Forming Process

Base Layer Forming Process

For example, a base layer2is formed on the C-plane of a sapphire substrate1by metal-organic chemical vapor deposition (MOCVD). A buffer layer may be formed on the substrate1before forming a base layer2, followed by forming a base layer2via the buffer layer. Here, the buffer layer is formed by growing AlGaN on the substrate1, for example, by setting the growth temperature at 600° C. at most and using TMA (trimethyl aluminum), TMG (trimethyl gallium), and ammonia as source gases. The base layer2is formed by growing a GaN layer on the buffer layer by using, for example, TMG and ammonia as source gases.

N-Side Contact Layer Forming Process

In the process of forming an n-side contact layer, an n-side contact layer3is formed by growing a GaN layer doped with an n-type impurity. In growing a GaN layer doped with an n-type impurity, TMG and ammonia are used as source gases, and monosilane as an n-type impurity gas. The growth temperature for the n-side contact layer3may be set, for example, at 1150° C.

N-Side Superlattice Layer Forming Process

In the process of forming an n-side superlattice layer, an n-side superlattice layer4is formed by alternately stacking undoped GaN layers and undoped InGaN layers. The growth temperature for the n-side superlattice layer4is preferably set lower than the growth temperature for the n-side contact layer3and can be set, for example, at about 910° C. In growing undoped GaN layers, TEG (triethyl gallium), ammonia, and the like are used as source gases. In growing undoped InGaN layers, TEG, TMI (trimethyl indium), ammonia and the like are used as source gases. When growing undoped GaN layers, a gas containing H2may be used as a carrier gas. Using such a carrier gas can reduce the formation of V-pits on the surface of a GaN layer. Here, V-pits refer to recess-shaped pits created on the surface of a semiconductor layer attributable to the dislocation generated in the semiconductor layer.

Active Layer Forming Process

Barrier Layer Forming Process

The barrier layer forming process includes forming a first barrier layer containing an n-type impurity, and forming a second barrier layer positioned closer to the p-side nitride semiconductor layer than the first barrier layer.

In the first barrier layer forming process, a first barrier layer containing an n-type impurity is formed at the forming temperature of 910° C. to 1010° C. In order to allow the first barrier layer to contain an n-type impurity, GaN containing an n-type impurity may be formed by using monosilane as an n-type impurity gas. The gas flow rate may be set to about 7 sccm and the pressure in the chamber about 600 Torr to allow the n-type impurity concentration of the first barrier layer5b1positioned between the first well layers5w1to fall within a range of 5.0×1017/cm3to 2.0×1018/cm3. The gas flow rate may be set to about 5 sccm and the pressure in the chamber about 600 Torr to allow the n-type impurity concentrations of the first barrier layers5b1positioned between the second well layers5w2to fall within a range of 4.0×1017/cm3to 1.0×1018/cm3. In other words, in the process of forming the first barrier layers, the barrier layers are formed such that the n-type impurity concentration of the first barrier layer5b1positioned between the first well layers5w1is higher than the n-type impurity concentrations of the first barrier layers5b1positioned between the second well layers5w2.

In the second barrier layer forming process, a second barrier layer containing an n-type impurity is formed at the forming temperature of 780 to 830° C. In other words, for the process of forming the second barrier layers, the forming temperature is set lower than the forming temperature for the process of forming the first barrier layers. Moreover, the n-type impurity gas flow rate in forming the second barrier layers can be set lower than the n-type impurity gas flow rate in forming the first barrier layers. Here, for the second barrier layer5b2positioned between the first well layers5w1, an undoped semiconductor layer may be formed. On the other hand, in the case of forming a second barrier layer5b2positioned between the second well layers5w2, GaN containing an n-type impurity may be formed by using monosilane for adding the n-type impurity. The gas flow rate may be set at about 1 sccm and the pressure in the chamber at about 600 Torr in order to allow the n-type impurity concentration of the second barrier layers5b2positioned between the second well layers5w2to fall within a range of 3.0×1017/cm3to 8.0×1017/cm3.

In the barrier layer forming process, with respect to the n-type impurity concentration relationship between the first barrier layers5b1and the second barrier layers5b2, the barrier layers are formed such that the difference between the n-type impurity concentration of the first barrier layer5b1and the n-type impurity concentration of the second barrier layer5b2that are positioned between the first well layers5w1is larger than the difference between the n-type impurity concentrations of the first barrier layers5b1and the n-type impurity concentrations of the second barrier layers5b2that are positioned between the second well layers5w2.

As another method of accomplishing the n-type impurity concentration relationship between the first barrier layers5b1and the second barrier layers5b2described above, the n-type impurity gas flow rate when forming the first barrier layer positioned between the first well layers may be set higher than the n-type impurity gas flow rate when forming the first barrier layers positioned between the second well layers.

Furthermore, a first barrier layer5b1is formed at a relatively high temperature (910° C. to 1010° C.), and a second barrier layer5b2is formed on the first barrier layer5b1at a relatively low temperature (780° C. to 830° C.), and a well layer is formed on the second barrier layer5b2, This can reduce the crystallinity degradation of the well layer. The reason for this will be explained now. Barrier layers need to be formed at a relatively high temperature in order to reduce crystallinity degradation. On the other hand, well layers need to be grown at a lower temperature than that for barrier layers in order to suppress the group III elements from being released. Lowering the temperature to that suited for forming a well layer by suspending semiconductor formation after forming a barrier layer might raise a concern of generating crystal defects attributable to the suspension of semiconductor layer formation. Accordingly, it is considered possible to reduce crystallization degradation by burying the crystal defects, which are caused by suspending semiconductor layer formation after forming a barrier layer at a relatively high temperature, with a barrier layer formed at a relatively low temperature. This can consequently reduce the light emission efficiency decline attributable to crystallinity degradation. Furthermore, doping the barrier layer with an n-type impurity as described above can reduce the energy level difference between the well layer and the barrier layer. By also doping a barrier layer formed at a relatively low temperature with an n-type impurity, the energy level difference between the well layer and the barrier layer can be further reduced. Furthermore, doping the barrier layer with a lower concentration n-type impurity than that of the barrier layer formed at a relatively high temperature can suppress the crystallinity degradation attributable to doping with an n-type impurity while reducing the energy level difference between the well layer and the barrier layer.

The barrier layer forming process in manufacturing the second embodiment described above may include forming a third barrier layer5b3and a fourth barrier layer5b4positioned closer to the p-side nitride semiconductor layer than the third barrier layer5b3. The third barrier layer5b3and the fourth barrier layer5b4are positioned between the first well layer5w1positioned closest to the p-side nitride semiconductor layer and the second well layer5w2positioned closest to the n-side nitride semiconductor layer.

In the process of forming a third barrier layer5b3, the third barrier layer5b3containing an n-type impurity is formed at a forming temperature of 910° C. to 1010° C. In order to allow the third barrier layer5b3to contain an n-type impurity, GaN containing an n-type impurity may be formed by using monosilane as an n-type impurity gas. In order to make the n-type impurity concentration of the third barrier layer5b3to be 5.0×1017/cm3to 2.0×1018/cm3and the thickness to be 13 nm to 16 nm, the gas flow rate may be set to about 3 sccm and the pressure in the chamber about 600 Torr.

In the process of forming a fourth barrier layer5b4, the fourth barrier layer5b4containing an n-type impurity is formed at a forming temperature of 780° C. to 830° C. In order to allow the fourth barrier layer5b4to contain an n-type impurity, GaN containing an n-type impurity may be formed by using monosilane as an n-type impurity gas. In order to make the n-type impurity concentration of the fourth barrier layer5b4to be 5.0×1017/cm3to 2.0×1018/cm3and the thickness to be 0.5 nm to 0.8 nm, the gas flow rate may be set to about 1 sccm and the pressure in the chamber about 600 Torr.

In this manner, the thickness of the third barrier layer5b3is made larger than those of the first barrier layers5b1positioned between the well layers5w2, and the n-type impurity concentration of the third barrier layer5b3is made lower than the n-type impurity concentration of the first barrier layer positioned between the first well layers5w1. This can improve the crystallinity of the third barrier layer5b3and the layers formed onward.

The barrier layer forming process may include forming an undoped semiconductor layer5ubetween the p-side nitride semiconductor layer and the second well layer5w2closest to the p-side nitride semiconductor layer. Forming an undoped semiconductor layer5ucan reduce the diffusion of the p-type impurity into the active layers5.

The process of forming an undoped semiconductor layer5uforms an undoped semiconductor layer without supplying an n-type impurity gas as compared to the process of forming the first barrier layer5b1positioned closest to the p-side nitride semiconductor layer; the forming temperature, the gas flow rate for anything other than the n-type impurity gas, and the pressure in the chamber can be set in substantially the same manner as those for forming the first barrier layer5b1.

Well Layer Forming Process

The well layer forming process includes forming a plurality of first well layers and a plurality of second well layers5w2positioned closer to the p-side nitride semiconductor layer than the first well layers5w1.

In the process of forming a first well layer, InGaN is formed by using TEG (triethyl gallium), TMI, and ammonia as source gases and setting the temperature at 780 to 830° C. In the process of forming a second well layer, InGaN is formed by using TEG, TMI, and ammonia as source gases and setting the temperature at 780 to 830° C. such that the quantity of the second well layers5w2is greater than the quantity of the first well layers5w1. Because a larger quantity of second well layers5w2that tend to have greater contribution to light emission are formed in the well layer forming process, more light can be generated by the second well layers5w2.

P-Side Nitride Semiconductor Layer Forming Process

P-Type Barrier Layer Forming Process

In the p-type barrier layer forming process, an AlGaN layer containing a p-type impurity is formed as a p-type barrier layer6by using, for example, TEG, TMA, and ammonia as source gases, and Cp2Mg (bis(cyclopentadienyl)magnesium) as a p-type impurity gas.

P-Side Contact Layer Forming Process

In the p-side contact layer forming process, an undoped GaN layer is grown by using, for example, TMG, TMA, and ammonia as source gases. Subsequently, a p-side contact layer7is formed on the undoped GaN layer by growing a GaN layer containing a p-type impurity by using TMG, TMA, and ammonia as source gases and Cp2Mg (bis(cyclopentadienyl)magnesium) as a p-type impurity gas. The impurity concentration of the p-side contact layer7is preferably set higher than that of the p-type barrier layer6.

After growing the semiconductor layers in the processes described above, the wafer is annealed in a reaction chamber in a nitrogen atmosphere at a temperature, for example, of about 700° C.

Electrode Forming Process

After annealing, a portion of the surface of the n-side contact layer3is exposed by partially removing the p-side nitride semiconductor layer20, the active layer5, and the n-side nitride semiconductor layer10.

Subsequently, a p-electrode9is formed on a portion of the surface of the p-side contact layer7, and an n-electrode8is formed on a portion of the surface of the exposed n-side contact layer3. By following the processes described above, a nitride semiconductor light emitting element100is produced.

As described above, the method of manufacturing a nitride semiconductor light emitting element according to the present embodiment can manufacture a nitride semiconductor light emitting element having improved light emission efficiency.

EXAMPLE

One preferable example of a nitride semiconductor light emitting element according to the present disclosure will be explained. As a substrate1, a sapphire substrate was used. A buffer layer that is an undoped AlGaN layer was formed on the upper face of the substrate1. A base layer2was formed on the buffer layer.

An n-side contact layer3was formed on the upper face of the base layer2. The n-side contact layer3is a GaN layer doped with Si as an n-type impurity. The thickness of the n-side contact layer3was about 8 μm.

An n-side superlattice layer4was formed on the upper face of the n-side contact layer3. An Si doped GaN layer of about 80 nm in thickness was formed. This was followed by forming 27 pairs of about a 3 nm thick undoped GaN layer and about a 1.5 nm thick undoped InGaN layer. Then three pairs of about a 3 nm thick undoped GaN layer and about a 1.5 nm thick Si doped InGaN layer were formed. Subsequently, six pairs of about a 10 nm thick Si doped AlGaN layer and about a 1 nm thick Si doped InGaN layer were formed. By forming these semiconductor layers, the n-side superlattice layer4including a plurality of semiconductor layers was formed.

An active layer5was formed on the upper face of the n-side superlattice layer4.

First, about a 6 nm thick Si doped InGaN layer, about a 2.3 nm thick undoped GaN layer as a barrier layer, about a 0.6 nm thick undoped GaN layer as a barrier layer, about a 1.6 nm thick undoped InGaN layer as a well layer, and about a 1.6 nm thick undoped GaN layer as an interlayer were formed.

This was followed by forming about a 15.8 nm thick Si doped GaN layer (n-type impurity concentration: 7.0×1017/cm3) as a barrier layer, about a 0.6 nm thick undoped GaN layer as a barrier layer, about a 1.6 nm thick undoped InGaN layer as a first well layer5w1, and about a 1.6 nm thick undoped GaN layer as an interlayer5c.

Then about a 15.8 nm thick Si doped GaN layer as a first barrier layer5b1, about a 0.6 nm thick undoped GaN layer as a second barrier layer5b2, about a 1.6 nm thick undoped InGaN layer as a first well layer5w1, and about a 1.6 nm thick undoped GaN layer as an interlayer5cwere formed. These processes of forming the first barrier layer5b1, the second barrier layer5b2, the first well layer5w1, and the interlayer5cwere repeated three times. In this process, the n-type impurity concentration of each first barrier layer5b1was set to be 7.0×1017/cm3.

Then about a 15.8 nm thick Si doped GaN layer as a barrier layer (n-type impurity concentration: 7.0×1017/cm3), about a 0.6 nm thick Si doped GaN layer as a barrier layer (n-type impurity concentration: 3.5×1017/cm3), about a 3.0 nm thick undoped InGaN layer as a well layer, and about a 1.6 nm thick undoped GaN layer as an interlayer were formed.

Then about a 15.8 nm thick Si doped GaN layer as a third barrier layer5b3(n-type impurity concentration: 3.5×1017/cm3), about a 0.6 nm thick Si doped GaN layer as a fourth barrier layer5b4(n-type impurity concentration: 3.5×1017/cm3), about a 3.0 nm thick undoped InGaN layer as a well layer, and about a 1.6 nm thick undoped GaN layer as an interlayer were formed.

This was followed by forming about a 15.8 nm thick Si doped GaN layer as a third barrier layer5b3(n-type impurity concentration: 3.5×1017/cm3), about a 0.6 nm thick Si doped GaN layer as a fourth barrier layer5b4(n-type impurity concentration: 3.5×1017/cm3), about a 3.0 nm thick undoped InGaN layer as a second well layer5w2, and about a 1.6 nm thick undoped GaN layer as an interlayer5c.

Then about a 9.5 nm thick Si doped GaN layer as a first barrier layer5b1, about a 0.6 nm thick Si doped GaN layer as a second barrier layer5b2, about a 3.0 nm thick undoped InGaN layer as a second well layer5w2, and about a 1.6 nm thick undoped GaN layer as an interlayer5cwere formed. These process of forming the first barrier layer5b1, the second barrier layer5b2, the second well layer5w2, and the interlayer5cwere repeated four times. In this process, the n-type impurity concentration of each first barrier layer5b1was set to be 4.9×1017/cm3and the n-type impurity concentration of each second barrier layer5b2was set to be 3.5×1017/cm3.

Subsequently, about a 9.5 nm thick Si doped GaN layer as a barrier layer (n-type impurity concentration: 4.9×1017/cm3), about a 0.6 nm thick undoped GaN layer as a barrier layer, about a 3.4 nm thick undoped InGaN layer as a well layer, about a 1.6 nm thick undoped GaN layer as an interlayer, and about an 18.4 nm thick undoped GaN layer as an undoped semiconductor layer5uwere formed. By forming the semiconductor layers described above, an active layer5that included a plurality of semiconductor layers was formed.

In forming the active layer5, the forming temperature for the barrier layers (including the first barrier layers5b1) adjacent to the interlayers was set to be 910° C. to 1010° C., and the forming temperature for the barrier layers (including the second barrier layers5b2) immediately under the well layers was set to be 780° C. to 830° C.

On the upper face of the active layer5, a p-type barrier layer6of about 11 nm in thickness was formed. The p-type barrier layer6is an AlGaN layer containing Mg as a p-type impurity. In the p-type barrier layer6, the Al percentage was set to be about 12.5%.

On the upper face of the p-type barrier layer6, a p-side contact layer7was formed. About an 80 nm thick undoped GaN was formed, that was followed by forming Mg doped GaN of about 20 nm in thickness.

After growing the semiconductor layers as described above, the wafer was heat treated in the reaction chamber in a nitrogen atmosphere at about 700° C.

After the heat treatment, a portion of the surface of the n-side contact layer3was exposed by partially removing the p-side nitride semiconductor layer20, the active layer5, and the n-side nitride semiconductor layer10.

Subsequently, a p-electrode9was formed on a portion of the surface of the p-side contact layer7, and an n-electrode8was formed on a portion of the exposed surface of the n-side contact layer3.

In such an example, the n-type impurity concentration of the first barrier layers5b1positioned between the first well layers5w1(7.0×1017/cm3) is higher than the n-type impurity concentration of the first barrier layers5b1positioned between the second well layers5w2(4.9×1017/cm3).

In the present example, furthermore, the n-type impurity concentration difference between the first barrier layers5b1and the second barrier layers5b2positioned between the first well layers5w1(7.0×1017/cm3) is larger than the n-type impurity concentration difference between the first barrier layers5b1and the second barrier layers5b2positioned between the second well layers5w2(1.4×1017/cm3).

In the present example, moreover, the thickness of each first barrier layer5b1positioned between the first well layers5w1(about 15.8 nm) is larger than the thickness of each first barrier layer5b1positioned between the second well layers5w2(about 9.5 nm).

In the present example, an undoped semiconductor layer5uis further provided between the p-side nitride semiconductor layer and the second well layer5w2that is closest to the p-side nitride semiconductor layer among the plurality of second well layers5w2.

In the present example, moreover, at least one of the barrier layers that are positioned between the first well layer5w1closest to the p-side nitride semiconductor layer and the second well layer5w2closest to the n-side nitride semiconductor layer includes a third barrier layer5b3containing an n-type impurity and a fourth barrier layer5b4containing an n-type impurity and positioned closer to the p-side nitride semiconductor than the third barrier layer5b3.

The thickness of the third barrier layer5b3(about 15.8 nm) is larger than the thickness of the first barrier layers (about 9.5 nm) positioned between the second well layers5w2, and the n-type impurity concentration of the third barrier layer5b3(3.5×1017/cm3) is lower than the n-type impurity concentration of the first barrier layers5b1positioned between the first well layers5w1(7.0×1017/cm3).

In the present example, the quantity of second well layers5w2(5 layers) is greater than the quantity of first well layers5w1(4 layers).

In the present example, moreover, the second barrier layers5b2positioned between the first well layers5w1are undoped semiconductor layers.

In the present example, the n-type impurity is Si.

In the present example described above, the light emission efficiency of the nitride semiconductor light emitting element measured when applying a 100 mA current was 43.9%.

The embodiments disclosed in the foregoing are provided for exemplification purposes in every respect, and do not constitute any ground for limited interpretations. Accordingly, the technical scope of the present invention shall not be interpreted based solely on the embodiments described above, but rather is defined by the scope of claims. The technical scope of the present invention encompasses the meanings equivalent to the scope of claims and all modifications that can be made within the scope of the claims.