Patent ID: 12228461

DETAILED DESCRIPTION

Hereinafter, some example embodiments according to the technical concepts of the present disclosure will be described referring to the accompanying drawings.

While the term “same,” “equal” or “identical” is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%).

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “about” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.

FIG.1is a block diagram of an electronic system according to an example embodiment.

Referring toFIG.1, an electronic system10may include a system on chip100, an external memory190, a display device195, and the like.

In some example embodiments, the electronic system10may include a personal computer (PC), a laptop, a mobile phone, a smart phone, a tablet PC, and the like. For example, the electronic system10may include a telephone, a smartphone, a tablet PC (tablet personal computer), a PDA (personal digital assistant), an EDA (enterprise digital assistant), a digital still camera, a digital video camera, a PMP (portable multimedia player), a PND (personal navigation device or portable navigation device), and the like.

The system on chip (SoC) may include a processor110, a clock management unit120, a timer130, a display controller140, a memory controller150, a non-volatile memory160, a main memory170, a bus180, and a temperature sensing unit200. Example embodiments of the present disclosure are not limited thereto, and the system on chip100may further include configurations different from the aforementioned configuration. For example, the system on chip100may further include a power management IC.

The processor110may include a CPU (central processing unit), an AP (application processor), and the like. The processor110may process or execute program or data stored in the external memory190. For example, the processor110may process or execute the program or data in response to an operating clock signal that is output from the clock management unit120. The processor110may be implemented as a multi-core processor. The multi-core processor may be a single computing component having two or more independent substantive processors. The processors may read and execute the program commands.

The programs or data stored in the non-volatile memory160, the main memory170, and the external memory190may be loaded into the memory of the processor110as needed. The non-volatile memory160may store permanent programs or data. The non-volatile memory160may be implemented as an EPROM (erasable programmable read only memory) or an EEPROM (electrically erasable programmable read only memory). The main memory170may temporarily store the program or data. For example, the program or data stored in the non-volatile memory160and the external memory190may be temporarily stored in the main memory170in accordance with the control of the processor110or a booting code stored in the non-volatile memory160. The main memory170may include a DRAM (dynamic RAM), a SRAM (static RAM), and the like.

The timer130may output a count value indicating the time, on the basis of an operating clock signal that is output from the clock management unit120. The clock management unit120may generate the operating clock signal. For example, the clock management unit120may include a clock signal generator such as a phase locked loop (PLL), a delayed locked loop (DLL) or a crystal oscillator. The operating clock signal may be provided to other components, for example, the processor110or the memory controller150. Further, the operating clock signal may be provided to the temperature sensing unit200.

The memory controller150may interface the external memory190and the system on chip100. The memory controller150may generally control the operation of the external memory190, and may control the data exchange between the host and the external memory190. For example, the memory controller150may program data in the external memory190or read data from the external memory190in response to a request from the host. Here, the host may be a processor110, a display controller140, or the like. The external memory190may be storage medium for storing data, and may store an OS, a program or data. The external memory190may be, but is not limited to, a volatile memory. In some example embodiments, the external memory190may be a non-volatile memory device.

The display controller140may control the operation of the display device195. The display device195may display the image signal that is output from the display controller140. For example, the display device195may include an LCD (liquid crystal display), an LED (light emitting diode) display, an OLDE (organic LED) display, a flexible display, and the like.

The processor110, the clock management unit120, the timer130, the display controller140, the memory controller150, the non-volatile memory160, the main memory170, and the like may communicate with each other through the bus180.

The temperature sensing unit200may be located inside the system on chip100to measure the temperature of the system on chip100. For example, the temperature sensing unit200may measure the temperature of the processor110. As the system on chip100operates, power is consumed, and the temperature of the system on chip100may rise accordingly. That is, the temperature of the processor110may rise, and it is desired to measure the temperature. The temperature sensing unit200may monitor the temperature of the system on chip100or the processor110. The temperature sensing unit200may receive an operating clock signal from the clock management unit120, and may measure the temperature on the basis of the operating clock signal. The configuration and operation of the temperature sensing unit200will be described in detail in the following specification.

FIG.2is a block diagram of a temperature sensing system according to an example embodiment.

Referring toFIG.2, the temperature sensing system20may include a processor110, a temperature sensing unit200and a clock management unit120. Here, the temperature sensing system20may be implemented by an internal configuration of the system on chip100. The temperature sensing unit200may be embedded in the processor110. For example, the temperature sensing unit200may be formed simultaneously during a manufacturing process of the processor110. That is, the temperature sensing unit200may be a part of the processor110. For example, when the processor110is manufactured in a FinFET process, the temperature sensing unit200may also be manufactured in the FinFET process. However, example embodiments of the present disclosure are not limited thereto, and the temperature sensing unit200may be located separately from the processor110. That is, the operation of the temperature sensing unit200may be performed separately from the operation of the processor110.

The clock management unit120may provide the operating clock signal to the processor110and the temperature sensing unit200. The processor110may operate on the basis of the operating clock signal, and the temperature sensing unit200may also operate on the basis of the provided operating clock signal. Further, the processor110may control the clock management unit120.

FIG.3is a block diagram for explaining a temperature sensing unit according to an example embodiment.FIG.4is a diagram for explaining the temperature sensing unit ofFIG.3.FIG.5is a graph for explaining the operation of the temperature sensor ofFIG.3.

Referring toFIG.3, the temperature sensing unit200may include an analog circuit AC and a digital circuit DC. The analog circuit AC may be manufactured through the FinFET process. The analog circuit AC may be implemented on the system on chip100. Also, the analog circuit AC may be placed adjacent to the processor110. That is, the analog circuit AC may be placed adjacent to the processor110or may be built into the processor110so that the temperature of the processor110may be sensed. Thus, the analog circuit AC may be a part of the processor110. The digital circuit DC may be connected to the analog circuit AC. The analog circuit AC may receive a signal from the digital circuit DC and perform the operation. For example, the analog circuit AC may convert an analog signal that is output from the digital circuit DC into a digital signal. Further, the digital circuit DC may process converted digital signal. The digital circuit DC may display the temperature measured through the analog circuit AC accordingly. Here, the digital circuit DC may be implemented by the processor110, the clock management unit120, or the like. That is, unlike the analog circuit AC, the digital circuit DC may be a synthesizable circuit and may be implemented differently depending on programming. However, example embodiments of the present disclosure are not limited thereto.

Referring toFIG.4, the analog circuit AC, a first resistor R1, a second resistor R2, and the digital circuit DC may be implemented on the substrate. The temperature sensing unit200ofFIG.4may be formed inside the system on chip100. The analog circuit AC may be located on one side of the temperature sensing unit200, and the first resistor R1and the second resistor R2may be placed adjacent to the analog circuit AC. The digital circuit DC may be formed in a portion except the analog circuit AC and the first resistor R1and the second resistor R2. Here, the area occupied by the digital circuit DC may be greater than the area occupied by the analog circuit AC. That is, a ratio occupied by the analog circuit AC may be smaller than a ratio occupied by the digital circuit DC, and thus the temperature sensing unit200having a small area may be provided. Here, in the digital circuit DC, the second controller260may be implemented by the processor110and the clock management unit120, and correspond to a synthesizable circuit. In the circuit, the analog circuit AC, the first resistor R1, the second resistor R2, and the digital circuit DC that make up the temperature sensing unit200may all be connected to perform the temperature sensing.

Referring toFIG.3again, the analog circuit AC may include a temperature sensor210and a comparator220. The temperature sensor210may be connected to the comparator220, and the comparator220may process the signal sent from the temperature sensor210and provide the signal to the digital circuit DC. Further, the temperature sensor210may operate on the basis of the signal that is output from the digital circuit DC. That is, the analog circuit AC may be controlled by the digital circuit DC.

The temperature sensor210may include a first temperature sensor210aand a second temperature sensor210b. Although the first temperature sensor210aand the second temperature sensor210bmay be placed separately, example embodiments of the present disclosure are not limited thereto.

The first temperature sensor210amay include a first resistor R1, a first capacitor C1, a first switch SW1, a second switch SW2, a third switch SW3and the like. The first resistor R1may be located between the first switch SW1and the third switch SW3. The first resistor R1may connect the first switch SW1and the third switch SW3. A portion of the first switch SW1opposite to the first resistor R1may be connected to a ground voltage VSS. Here, the first switch SW1may operate on the basis of the clock signal P0. For example, when the clock signal P0is a high signal, the first switch SW1may be closed, and when the clock signal P0is a low signal, the first switch SW1may be opened.

A portion of the third switch SW3opposite to the first resistor R1may be connected to a node. Here, the node may be connected to the first capacitor C1, the second switch SW2and the comparator220. That is, the first capacitor C1, the second switch SW2, the third switch SW3, and the comparator220may be connected in common to the node. A first voltage VN of the node may be formed by the operation of the first capacitor C1, the second switch SW2, the third switch SW3and the comparator220. One end of the second switch SW2may be connected to a power supply voltage VDD, and the other end of the second switch SW2may be connected to the node.

The third switch SW3may operate on the basis of a first delay clock signal P1BD. Here, when the first delay clock signal P1BD is a low signal, the third switch SW3may be closed, and when the first delay clock signal P1BD is a high signal, the third switch SW3may be opened. Here, the third switch SW3may operate unlike (e.g., differently from) the first switch SW1and the second switch SW2. The second switch SW2may operate on the basis of the first clock signal P1. One end of the first capacitor C1may be connected to the node, and the other end of the first capacitor C1may be connected to the ground voltage VSS. The clock signal P0, the first clock signal P1, and the first delay clock signal P1BD that operate the first temperature sensor210amay be provided from the digital circuit DC. That is, the first temperature sensor210amay be controlled by the digital circuit DC. The first resistor R1may be a metal wire formed inside a substrate in the semiconductor device. That is, the first resistor R1may correspond to a parasitic resistor of the semiconductor device rather than a poly resistor element. The first resistor R1may be metal routing, and may include a metal layer that connects the semiconductor elements. Here, the first resistor R1may be manufactured by the FinFET process.

The second temperature sensor210bmay include a second resistor R2, a second capacitor C2, a first switch SW1′, a second switch SW2′, a third switch SW3′, and the like. The second resistor R2may be located between the first switch SW1′ and the third switch SW3′. The second resistor R2may connect the first switch SW1′ and the third switch SW3′. A portion of the first switch SW1′ opposite to the second resistor R2may be connected to the power supply voltage VDD. Here, the first switch SW1′ may operate on the basis of the clock signal P0. Here, the clock signal P0may be the same as that provided to the first switch SW1.

A portion of the third switch SW3′ opposite to the second resistor R2may be connected to the node. Here, the node may be connected to the second capacitor C2, the second switch SW2′ and the comparator220. That is, the second capacitor C2, the second switch SW2′, the third switch SW3′ and the comparator220may be connected in common to the node. The second voltage VP of the node may be formed by the operation of the second capacitor C1, the second switch SW2′, the third switch SW3′ and the comparator220. One end of the second switch SW2′ may be connected to the ground voltage VSS, and the other end of the second switch SW2′ may be connected to the node.

The third switch SW3may operate on the basis of the first delay clock signal P1BD. Here, the first delay clock signal P1BD may be the same as the first delay clock signal P1BD applied to the third switch SW3. The second switch SW2′ may operate on the basis of the first clock signal P1. Here, the first clock signal P1may be the same as the first clock signal P1applied to the second switch SW2. One end of the second capacitor C2may be connected to the node, and the other end of the second capacitor C2may be connected to the ground voltage VSS. The clock signal P0, the first clock signal P1, and the first delay clock signal P1BD that operate the second temperature sensor210bmay be provided from the digital circuit DC. That is, the second temperature sensor210bmay be controlled by the digital circuit DC. The second resistor R2may be a metal wire formed inside the substrate in the semiconductor device. That is, the second resistor R2may correspond to the parasitic resistor of the semiconductor device rather than a poly resistor element. The second resistor R2may be metal routing, and may include a metal layer that connects the semiconductor elements. Here, the second resistor R2may be manufactured by the FinFET process.

The first resistor R1and the second resistor R2may be located inside the system on chip100. Also, the first resistor R1and the second resistor R2may be placed adjacent to the processor110. The first resistor R1and the second resistor R2may correspond to an element whose resistance value increases in proportion to the temperature. For example, as the temperature of the processor110increases, the resistance values of the first resistor R1and the second resistor R2may increase. The temperature sensor210may provide an RC temperature sensor, by utilizing the first and second resistors R1and R2, and the first and second capacitors C1and C2.

According to the example embodiment, the first temperature sensor210amay include the first resistor R1and the first capacitor C1, and the first temperature sensor210agenerates the first voltage VN applied to at least one of the first resistor R1or the first capacitor C1based on the clock signal P0and the first clock signal P1. The first clock signal P1may be a signal generated by delaying the clock signal P0. Further, the second temperature sensor210bmay include the second resistor R2and the second capacitor C2, and the first temperature sensor generates the second voltage VP applied to at least one of the second resistor R2or the second capacitor C2based on the first clock signal and the second clock signal.

Referring toFIG.5, the time of a cross point formed by a first curve CV1when the temperature of the system on chip100is low may be smaller than the time of a cross point formed by a second curve CV2when the temperature of the system on chip100is high. That is, the first curve CV1may increase or decrease more rapidly than the second curve CV2. The reason is that because the resistance values of the first resistor R1and the second resistor R2at a low temperature are small, the increase or decrease time of the voltage is small, and because the resistance values of the first resistor R1and the second resistor R2at a high temperature are large, the increase or decrease time of the voltage is large. That is, the temperature of the system on chip100may be converted into voltage by the first and second resistors R1and R2, and may be subsequently converted into the time. That is, the first and second resistors R1and R2correspond to temperature-proportional elements. However, example embodiments of the present disclosure are not limited thereto. More detailed operation of the temperature sensor210will be provided below.

Referring toFIG.3again, the comparator220may be connected to the first temperature sensor210aand the second temperature sensor210b, and may be connected to the digital circuit DC. The comparator220may operate in synchronization with the clock signal CLK provided from the digital circuit DC. The comparator220may receive the first voltage VN from the first temperature sensor210aand receive the second voltage VP from the second temperature sensor210bto perform the comparison operation. The comparator220may generate a comparison signal COMP based on the first voltage VN and the second voltage VP. For example, the comparator220may compare the first voltage VN and the second voltage VP to generate the comparison signal COMP. That is, the comparator220may output a high signal when the first voltage VN is higher than the second voltage VP, and the comparator220may output a low signal when the first voltage VN is lower than or equal to the second voltage VP. The comparator220may correspond to a latch comparator. The comparator220may provide the comparison signal COMP to the digital circuit DC.

The digital circuit DC may include a first controller230, a delay locked loop circuit240, a selector250, a selector251, a latch252and a second controller260. Here, the digital circuit DC except the delay locked loop circuit240may be implemented by the processor110. However, example embodiments of the present disclosure are not limited thereto.

The selector250may be connected to the comparator220and the latch252, and may output at least one of the comparison signal COMP output from the comparator220or the signal output from the latch252, depending on the mode. For example, when the mode is 0, the selector250may output the comparison signal COMP, and when the mode MODE is 1, the selector250may output the latched second clock signal P2. Here, each mode MODE may be changed according to the time interval.

The signal output from the selector250may be sent to the first controller230, and the first controller230may output at least one of a control signal CS, a temperature-proportional digital signal DPTAT, or a reference digital signal DREF, on the basis of the received signal. Here, the control signal CS may be sent to the delay locked loop circuit240, and the temperature-proportional digital signal DPTAT and the reference digital signal DREF may be sent to the selector251. More detailed operation of the selector250will be described below.

The selector251may be connected to the first controller230, and may send one of the temperature-proportional digital signal DPTAT or the reference digital signal DREF output from the first controller230to the second controller260, depending on the mode. That is, when the mode MODE is 0, the selector251may output the temperature-proportional digital signal DPTAT, and when the mode MODE is 1, the selector251may output the reference digital signal DREF.

The second controller260may generate and output a temperature digital signal DTEMP, using the temperature-proportional digital signal DPTAT or the reference digital signal DREF received from the selector251. Further, the second controller260may generate a clock signal CLK, a clock signal P0and a first clock signal P1to be provided to the analog circuit AC, and may generate a mode MODE and a second clock signal P2to be provided to the digital circuit DC.

The delay locked loop circuit240may delay the first clock signal P1, a first clock signal P1B and/or the second clock signal P2, on the basis of the control signal CS received from the first controller230. That is, the delay locked loop circuit240may output the first delay clock signal P1BD or the second delay clock signal P2D. The first delay clock signal P1BD may be provided to the temperature sensor210, and the temperature sensor210may operate on the basis of the first delay clock signal P1BD. The second delay clock signal P2D may be provided to the latch252, and the latch252may operate in synchronization with the second delay clock signal P2D. The latch252may output the second clock signal P2which is latched in synchronization with the second delay clock signal P2D.

Hereinafter, the operation of the temperature sensing unit200will be described in more detail referring to the drawings.

FIG.6is a flowchart for explaining the operation of the temperature sensing unit according to an example embodiment.

Referring toFIG.6, the temperature sensing unit200may include a plurality of operations. For example, the temperature sensing unit200may sense the temperature (S300). Resistance values of the first resistor R1and the second resistor R2of the temperature sensor210of the analog circuit AC may change depending on the temperature of the system on chip100. Accordingly, the degree of change in the voltage to be output from the temperature sensor210may vary, and the temperature sensing unit200may output the changed temperature data on the basis of the signal to be output (e.g., the voltage to be output from the temperature sensor210).

The temperature sensing unit200may perform the first operation cycle (S301). Subsequently, the temperature sensing unit200may perform the second operation cycle (S302). Here, the second operation cycle may be performed after the first operation cycle is performed. That is, the time during which the first operation cycle is performed may precede the time during which the second operation cycle is performed, and the times may not overlap. The temperature-proportional digital signal DPTAT may be output as a result of performing the first operation cycle, and the reference digital signal DREF may be output as a result of performing the second operation cycle. Finally, the temperature sensing unit200may calculate a temperature digital signal DTEMP (S303). Here, the temperature digital signal DTEMP may be generated on the basis of the temperature-proportional digital signal DPTAT output at the first operation cycle, and the reference digital signal DREF output at the second operation cycle. Performance of the temperature sensing operation and the first operation cycle will be described in more detail referring toFIGS.7to15.

FIG.7is a block diagram for explaining the first controller ofFIG.3.

Referring toFIG.7, the first controller230may include a determiner231, a digital signal generator232, a control signal generator233, and the like. The configurations of the first controller230may not be limited to those shown. For example, the first controller230may include more configurations or may include fewer configurations. The first controller230may also correspond to a counter that counts the comparison signal COMP. In the following description, although the description will be provided on the assumption that the temperature code data TCODE or the temperature-proportional digital signal DPTAT are 5 bits, example embodiments of the present disclosure are not limited thereto. For example, the temperature code data TCODE or the temperature-proportional digital signal DPTAT may be 12 bits.

The determiner231may receive the comparison signal COMP and generate temperature code data TCODE on the basis of the comparison signal COMP. When the comparison signal COMP is 1, the temperature code data TCODE[n] may be 1, and when the comparison signal COMP is 0, the temperature code data TCODE[n] may be 0. Here, n may vary depending on the bits to be processed. For example, if the bits to be processed are 5 bits, n may correspond to 4 to 0. The determiner231may provide the generated temperature code data TCODE to the digital signal generator232and the control signal generator233.

The digital signal generator232may generate a temperature-proportional digital signal DPTAT on the basis of the temperature code data TCODE. Here, the temperature-proportional digital signal DPTAT may correspond to 5 bits, and may be generated, using nthbit values of the temperature code data TCODE. For example, when the temperature code data TCODE[4] is 1, the temperature-proportional digital signal DPTAT may be 10000. However, this description is merely an example, and example embodiments of the present disclosure are not limited thereto.

The control signal generator233may generate a control signal CS on the basis of the temperature code data TCODE. Here, the control signal CS may correspond to 5 bits and may indicate one of the values from 0 to 31. For example, when the control signal CS having a value of 0 is sent to the delay locked loop circuit240, the delay locked loop circuit240may not delay the first clock signal P1. However, when the control signal CS having a value of 15 is sent to the delay locked loop circuit240, the delay locked loop circuit240may delay the first clock signal P1by a half cycle. Referring toFIG.3, the first delay clock signal P1BD or the second delay clock signal P2D delayed by the control signal CS may be sent to the temperature sensor210or the latch252, and the delay locked loop operation or feedback of the temperature sensing unit200may be performed. However, this description is merely an example, and example embodiments of the present disclosure are not limited thereto.

FIG.8is a timing diagram for explaining the operation of the temperature sensing unit according to an example embodiment.FIG.9is a flowchart for explaining the operation of the temperature sensing unit.FIGS.10to12are diagrams for explaining the operation of the temperature sensing unit according to time.

Referring toFIG.8, the temperature sensing unit200may perform the temperature sensing operation during the first cycle PR1. Here, the first cycle PR1may be included in the first operation cycle described inFIG.6.

Referring toFIGS.3,7, and8, the first clock signal P1and the clock signal P0may be provided to the temperature sensor210. At the first time t1, the first clock signal P1may be a high signal, and the clock signal P0may be a low signal.

Referring toFIGS.8and10, the first clock signal P1which is the high signal, and the clock signal P0which is the low signal may be applied to the temperature sensor210at the first time t1. At this time, third switches SW3and SW3′ may be closed by the first delay clock signal P1BD applied to the third switches SW3and SW3′. The second switches SW2and SW2′ may be closed by the first clock signal P1, and the first switches SW1and SW1′ may be opened by the clock signal P0. Accordingly, the power supply voltage VDD may be applied to the first capacitor C1, and the ground voltage VSS may be applied to the second capacitor C2. The first voltage VN applied to the first capacitor C1may be the power supply voltage VDD corresponding to the high signal, and the second voltage VP applied to the second capacitor C2may be the ground voltage VSS corresponding to the low signal. Regardless of the previous status of the temperature sensor210, the first voltage VN as the high signal, and the second voltage VP as the low signal may be sent to the comparator220. Accordingly, the comparator220may output a comparison signal COMP corresponding to the high signal, that is, corresponding to 1.

Referring toFIGS.8and11, the first clock signal P1as the low signal, and the clock signal P0as the high signal may be applied to the temperature sensor210at the second time t2. The corresponding first clock signal P1and clock signal P0may be applied during the remaining first cycle PR1(e.g., the remaining time of the first cycle PR1after the second time t2). At this time, the second switches SW2and SW2′ may be opened by the first clock signal P1, and the first switches SW1and SW1′ may be closed by the clock signal P0. The first voltage VN may be reduced by the clock signal P0and the first clock signal P1, and the second voltage VP may be increased by the clock signal P0and the first clock signal P1. This is because all the first temperature sensors210aare connected to the ground voltage VSS, and the second temperature sensor210bis connected to the power supply voltage VDD and the ground voltage VSS.

At this time, because the magnitude of the resistance values of the first and second resistors R1and R2is proportional to the temperature, as the higher the temperature is, the higher the change in the first voltage VN and the second voltage VP may be. Also, the lower the temperature is, the lower the change in the first voltage VN and the second voltage VP may be. Even after the second time t2, because the first voltage VN is higher than the second voltage VP, the comparison signal COMP corresponding to the high signal may be output.

Referring toFIGS.3and12, the first delay clock signal P1BD may be converted into a high signal at the third time t3. Here, the first delay clock signal P1BD may be a signal generated by delay of the first clock signal P1. For example, the delay locked loop circuit240may delay the first clock signal P1by a delay amount I0to generate the first delay clock signal P1BD. At the first cycle PR1, the delay locked loop circuit240may not receive the control signal CS from the first controller230, and may generate the first delay clock signal P1BD without being based on the control signal CS. For example, the first delay clock signal P1BD may have a difference from the first clock signal P1by half the first cycle PR1.

The first delay clock signal P1BD may be maintained at a high signal during the first cycle PR1after the third time t3. The first delay clock signal P1BD may be applied to the third switches SW3and SW3′, and the third switches SW3and SW3′ may be opened in response to this. In response to the application of the first delay clock signal P1BD which is the high signal, the first voltage VN and the second voltage VP may be maintained at the first voltage VN and the second voltage VP corresponding to the third time t3. In this example embodiment, because the first voltage VN is greater than the second voltage VP at the third time t3, the comparator220may output the comparison signal COMP having the high level.

The selector250may send the comparison signal COMP as the high signal to the first controller230.

Referring toFIG.9, the first controller230determines whether the first voltage VN is smaller than the second voltage VP when the first delay clock signal P1BD is input (S310). When the first voltage VN is smaller than the second voltage VP (S310-Y), the selector250may output the comparison signal COMP which is the low signal (S311). That is, the selector250may output a comparison signal COMP having 0. Further, when the first voltage VN is not smaller than the second voltage VP (S310-N), the selector250may output the comparison signal COMP, which is the high signal (S313). That is, the selector250may output the comparison signal COMP having 1.

The determiner231may generate temperature code data TCODE, on the basis of the comparison signal COMP that is output from the selector250when the first delay clock signal P1BD is input (S312). Here, the temperature code data TCODE[n] may be 0. Furthermore, the determiner231may generate the temperature code data TCODE, on the basis of the comparison signal COMP that is output from the selector250when the first delay clock signal P1BD is input (S314). Here, the temperature code data TCODE[n] may be 1. In the determiner231, because the comparison signal COMP corresponds to 1 when the first delay clock signal P1BD is input at the first cycle PR1, the temperature code data TCODE[n] may be 1. In the present specification, since the description will be provided on the assumption that the temperature-proportional digital signal DPTAT is 5 bits, n may be 4 and the temperature code data TCODE[4] may be 1 at the first cycle PR1.

The determiner231may provide the temperature code data TCODE to the digital signal generator232and the control signal generator233.

The first controller230may generate the control signal CS and the temperature-proportional digital signal DPTAT on the basis of the temperature code data TCODE (S315). The digital signal generator232may generate the temperature-proportional digital signal DPTAT on the basis of the temperature code data TCODE. Here, the temperature-proportional digital signal DPTAT may be generated on the basis of the previously generated temperature code data TCODE. For example, when the temperature code data TCODE[4] is 1 and the temperature code data TCODE[3] is 1, the temperature-proportional digital signal DPTAT to be output may be 11000.

The control signal generator233may generate the control signal CS on the basis of the temperature code data TCODE. For example, when the temperature code data TCODE[4] is 1, the control signal CS may increase the delay amount of the first clock signal P1. Further, when the temperature code data TCODE[4] is 0, the control signal CS may reduce the delay amount of the first clock signal P1. Here, the operation of generating the first delay clock signal P1BD1on the basis of the control signal CS may be performed during the second cycle PR2. That is, the delay operation performed during the first cycle PR1may be performed without the control signal CS, and the delay operation performed during the second cycle PR2may be performed on the basis of the control signal CS. By adjusting the delay amount of the first clock signal P1through the delay locked loop circuit240, the delay amount of the first clock signal P1may be the same as the time interval at which the first voltage VN matches (e.g., equalizes) the second voltage VP. That is, the temperature-proportional digital signal DPTAT having a value proportional to the temperature may be output through the delayed fixed loop way. This may correspond to a successive approximation type analog-to-digital conversion circuit (e.g., Successive approximation ADC). That is, the temperature sensing unit200may be a successive approximation register-controlled delay locked loop (SAR DLL) circuit.

The temperature sensing unit200may control the delay locked loop circuit240on the basis of the control signal CS (S316). This operation may be performed at the second cycle PR2and may respond to feedback.

Subsequently, the operation of the temperature sensing unit200at the second cycle PR2to the fifth cycle PR5will be described referring toFIGS.13to15.

FIG.13is a timing diagram for explaining the operation of the temperature sensing unit according to an example embodiment.FIGS.14and15are diagrams for explaining the operation of the temperature sensing unit according to time.

Referring toFIGS.13and14, the temperature sensing unit200may perform the operation at the second cycle PR2. Here, the second cycle PR2may correspond to the time interval subsequent to the first cycle PR1. That is, the first delay clock signal P1BD2may be a signal generated on the basis of the control signal CS1that is output through the operation of the first cycle PR1. That is, the first delay amount I1of the first delay clock signal P1BD2may be greater than the delay amount I0at the first cycle PR1. Here, the first delay clock signal P1BD2may be generated, using the first clock signal P1B. The first clock signal P1B may have a phase difference from the first clock signal P1by half the second cycle PR2. However, example embodiments of the present disclosure are not limited thereto, and the first delay clock signal P1BD2may be generated to have a different phase difference on the basis of the first clock signal P1.

The clock signal P0and the first clock signal P1may be continuously input to the temperature sensor210. The first voltage VN may decrease as the clock signal P0becomes a high signal, and the second voltage VP may decrease as the clock signal P0becomes a high signal. The first voltage VN and the second voltage VP may be constant as the first delay clock signal P1BD1is output. When the first delay clock signal P1BD1is output, that is, at the fourth time t4, the magnitude of the first voltage VN is smaller than the magnitude of the second voltage VP, and the second controller230may generate temperature code data TCODE[3] corresponding to 0. The temperature-proportional digital signal DPTAT generated on the basis of the temperature code data TCODE[3] may be 10000, and the subsequently generated control signal CS2may control the first delay clock signal P1BD2at the third cycle PR3so that the second delay amount I2becomes smaller than the first delay amount H.

Referring toFIGS.13and15, the temperature sensing unit200may perform the operation at the third cycle PR3. Here, the third cycle PR3may correspond to the time interval subsequent to the second cycle PR2. That is, the first delay clock signal P1BD3may be a signal generated on the basis of the control signal CS2that is output through the operation of the second cycle PR2. That is, the second delay amount I2of the first delay clock signal P1BD3may be smaller than the first delay amount I1at the second cycle PR2. Here, the first delay clock signal P1BD3may be generated, using the first clock signal P1B.

The clock signal P0and the first clock signal P1may be continuously input to the temperature sensor210. The first voltage VN and the second voltage VP may be constant, as the first delay clock signal P1BD2is output. When the first delay clock signal P1BD2is output, that is, at the fifth time t5, the magnitude of the first voltage VN is greater than the magnitude of the second voltage VP, and the first controller230may generate temperature code data TCODE[2] corresponding to 1. The temperature-proportional digital signal DPTAT generated on the basis of the temperature code data TCODE[2] may be 10100, and the subsequently generated control signal CS may control the first delay clock signal P1BD3at the fourth cycle PR4so that the third delay amount I3becomes greater than the second delay amount I2.

By continuing the operation at the first cycle PR1to the third cycle PR3, a rising edge of the first delay clock signal P1BD may become the same as the time point at which the first voltage VN becomes the same as the second voltage VP. That is, the comparator220, the first controller230and the delay locked loop circuit240may fix the delay amount of the first delay clock signal P1BD. For example, the temperature-proportional digital signal DPTAT that is output after the fifth cycle PR5may be 10101, and the first operation cycle may be finished. That is, the temperature-proportional digital signal DPTAT, which is proportional to the system on chip, may be output. Unlike a phase locked loop way which locks the phase, the temperature measurement time may be reduced by utilizing the delay locked loop circuit240. Also, an accurate temperature measurement may be performed within less time. Further, the temperature sensing unit200may utilize the power supply voltage and the ground voltage used by the processor110, and the power consumption may be reduced. The temperature sensing unit200including the digital circuit DC has a smaller area, and the digital circuit DC corresponds to a synthesizable circuit, and may be flexibly designed. Further, because the area occupied by the analog circuit AC is reduced, the power consumption may be reduced and the noise may be reduced.

Hereinafter, the operation S302of the temperature sensing unit200according to the second operation cycle will be described referring toFIGS.16to20.

FIG.16is a timing diagram for explaining the operation of the temperature sensing unit according to an example embodiment.FIG.17is a flowchart for explaining the operation of the temperature sensing unit.FIG.18is a diagram for explaining the operation of the temperature sensing unit according toFIGS.16and17.

Referring toFIGS.16to18, the mode MODE of the selector250and the selector251may be 1. That is, the selector250does not output the comparison signal COMP, may output the latched second clock signal P2, and the selector251may output the reference digital signal DREF. That is, at the second operation cycle, the temperature sensor210and the comparator220may not operate or may not output a signal, and instead, the latch252may operate. Here, the latch252may include a flip-flop.

The second clock signal P2, and the second delay clock signal P2D obtained by delaying the second clock signal P2may be input to the latch252. The latch252may latch the second clock signal P2in synchronization with the second delay clock signal P2D. That is, the latch252may output the latched second clock signal P2. For example, the latch252may output the second clock signal P2which is latched only during application of the second delay clock signal P2D. That is, the second clock signal P2latched only during the time interval may correspond to 1.

The first controller230may determine whether the latch252and the selector250output 0 (S320). When the latch252outputs 0 (S320-Y), the first controller230may generate the reference code data REFCODE corresponding to 0 (S321). Further, when the latch252does not output 0 (S320-N), that is, when the latch252outputs 1, the first controller230may generate the reference code data REFCODE corresponding to 1 (S322). For example, at the first operation cycle, the latch252may output 1, and the first controller230may generate the reference code data REFCODE[4] corresponding to 1.

The first controller230may generate the control signal CS and the reference digital signal DREF on the basis of the reference code data REFCODE (S323). The temperature sensing unit200may control the delay fixed loop circuit240on the basis of the control signal CS (S324). That is, the output control signal CS may increase the delay amount of the second delay clock signal P2D with respect to the second clock signal P2. In contrast, the control signal CS generated on the basis of the reference code data REFCODE corresponding to 0 may reduce the delay amount of the second delay clock signal P2D with respect to the second clock signal P2.

A falling edge of the second clock signal P2may become the same as a rising edge of the second delay clock signal P2D through the operation at the second operation cycle. That is, the latch252may compare the time of the falling edge of the second clock signal P2with the time of the rising edge of the second delay clock signal P2D. Accordingly, the first controller230may output the reference digital signal DREF, and the reference digital signal DREF may have a data value corresponding to the time at which the second clock signal P2is applied.

FIG.19is a diagram for explaining the operation of the second controller according to an example embodiment.FIG.20is a graph for explaining the effect of the second controller ofFIG.19.

Referring toFIG.19, the second controller260may receive the temperature-proportional digital signal DPTAT and the reference digital signal DREF. The second controller260may generate the temperature digital signal DTEMP on the basis of the temperature-proportional digital signal DPTAT generated at the first operation cycle and the reference digital signal DREF generated at the second operation cycle. Here, the temperature digital signal DTEMP may be a ratio of the temperature-proportional digital signal DPTAT to the reference digital signal DREF.

The temperature sensing unit200may convert the temperature into a time domain, but the operation may be affected by changes in PVT (process/voltage/temperature). Therefore, by dividing the temperature-proportional digital signal DPTAT by the reference digital signal DREF corresponding to the delay time of the second clock signal P2, it is possible to reduce the influence of PVT changes. That is, the PVT changes may be offset.

Referring toFIG.20, an amount of change in the temperature code data TCODE when there is no PVT compensation may vary with an increase in temperature. That is, the temperature sensing unit200may output the temperature code data TCODE affected by the PVT changes. However, the temperature code data TCODE when there is a PVT compensation may have a constant amount of change with an increase in temperature. That is, the PVT changes may be compensated by the compensatory operation of the second controller260.

Hereinafter, a temperature sensing unit200′ including a time-digital converter TDC which performs the time-digital conversion operation will be described referring toFIG.21.

FIG.21is a block diagram of the temperature sensing unit according to an example embodiment. For convenience of explanation, repeated parts of contents explained usingFIGS.1to20will be briefly explained or omitted.

Referring toFIG.21, the temperature sensing unit200′ may include a temperature sensor210, a time-digital converter TDC, and a delay locked loop circuit240. Here, the temperature sensor210and the delay locked loop circuit240may correspond to the temperature sensor210and the delay locked loop circuit240of the temperature sensing unit200described referring toFIGS.1to20. The time-digital converter TDC may be connected to the temperature sensor210and the delay locked loop circuit240to send and receive data. For example, the time-digital converter TDC may include a comparator220, a selector250, a selector251, a latch252, a first controller230, a second controller260, and the like. However, example embodiments of the present disclosure are not limited thereto, and the time-digital converter TDC may include only a partial configuration.

The time-digital converter TDC may generate the temperature-proportional digital signal DPTAT on the basis of the first voltage VN and second voltage VP that are received from the temperature sensor210. For example, as explained above, the time interval from the time point at which the first voltage VN and the second voltage VP start to change to the time point at which the first voltage VN and the second voltage VP are the same may be converted into the temperature-proportional digital signal DPTAT. That is, temperature data may be converted into voltage, time, and digital data.

At this time, the delay fixed loop circuit240may delay the first clock signal P1using the control signal CS generated on the basis of the generated temperature-proportional digital signal DPTAT, and generate the first clock delay signal P1BD. The first clock delay signal P1BD may be provided to the temperature sensor210to perform accurate time-digital conversion. This operation is performed by the delay locked loop way, and thus, the consumption time may be reduced.

Hereinafter, the temperature sensing system30will be described referring toFIG.22.

FIG.22is a block diagram of the temperature sensing system according to an example embodiment. For convenience of explanation, repeated parts of contents explained usingFIGS.1to21will be briefly described or omitted.

Referring toFIG.22, the temperature sensing system30may include a processor110, a clock management unit120, and a temperature sensing unit200. Here, the temperature sensing unit200may include an analog circuit AC and a delay locked loop circuit240separated from each other inside. The temperature sensing unit200may be placed separately from the processor110. That is, unlike the example embodiment described referring toFIG.2in which the temperature sensing unit200is included in the processor110, the temperature sensing unit200may measure the temperature, using the analog circuit AC adjacent to the processor110outside the processor110. At this time, although the temperature sensing unit200may be controlled by the processor110and the clock management unit120, example embodiments of the present disclosure are not limited thereto.

Any functional blocks shown in the figures and described above may be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the disclosed example embodiments without substantially departing from the principles of the present disclosure. Therefore, the disclosed example embodiments of the inventive concepts are used in a generic and descriptive sense only and not for purposes of limitation.