Patent ID: 12261133

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The present disclosure is generally related to an interposer that can be disposed on top of a substrate to provide electrical connection between the substrate and chip structures disposed on the interposer. Materials expand or contract depending on their thermal expansion coefficients. As will be described, an insight provided by the present disclosure is that undesired warpage on the interposer can be caused during manufacturing of the chip structures. For example, in a semiconductor device, layers of different materials are in close contact, and mismatch in thermal expansion coefficients can cause thermal stresses in adjacent materials. For example, during a thermal process, the interposer can be caused to bend undesirably by the chip structures. For addressing this, various embodiments provide techniques to deposit different materials in the interposer in a controlled manner. These materials are selected for their characteristics of thermal expansion. In various embodiments, warpage characteristics in the interposer is identified, and trenches are formed in the interposer based on the identified warpage characteristic, and one or more materials are selected to be deposited in the interposer in the trenches to reduce the warpage.

FIGS.1A and1Bare cross-sectional views of various stages of a process for forming a chip package structure, in accordance with some embodiments. As shown inFIG.1A, a substrate110is provided, in accordance with some embodiments. In some embodiments, the substrate110is a wafer. The substrate110includes a semiconductor structure111, conductive vias112, an insulating layer113, a redistribution structure114, and conductive pads115, in accordance with some embodiments.

The semiconductor structure111has surfaces111aand111b, in accordance with some embodiments. In some embodiments, the semiconductor structure111is made of an elementary semiconductor material including silicon or germanium in a single crystal, poly crystal, or amorphous structure. In some other embodiments, the semiconductor structure111is made of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), an alloy semiconductor (e.g., SiGe or GaAsP), or a combination thereof. The semiconductor structure111may also include multi-layer semiconductors, semiconductor on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.

In some embodiments, the substrate110is an interposer wafer. The conductive vias112are formed in the semiconductor structure111, in accordance with some embodiments. The conductive vias112may be formed to extend from the surface111ainto the semiconductor structure111.

The insulating layer113is formed over the semiconductor structure111, in accordance with some embodiments. The insulating layer113is between the conductive vias112and the semiconductor structure111, in accordance with some embodiments. The insulating layer113is configured to electrically insulate the conductive vias112from the semiconductor structure111, in accordance with some embodiments. The insulating layer113is made of an oxide-containing material such as silicon oxide, in accordance with some embodiments. The insulating layer113is formed using an oxidation process, a deposition process, or another suitable process.

In some other embodiments, the substrate110is a device wafer that includes active devices or circuits. The active devices may include transistors (not shown) formed at the surface111a. The substrate110may also include passive devices (not shown) formed in or over the semiconductor structure111, in accordance with some embodiments. The passive devices include resistors, capacitors, or other suitable passive devices.

The redistribution structure114is formed over the semiconductor structure111, in accordance with some embodiments. The conductive pads115are formed over the redistribution structure114, in accordance with some embodiments. The redistribution structure114includes a dielectric layer114a, wiring layers114b, and conductive vias114c, in accordance with some embodiments. The dielectric layer114ais formed over the surface111a, in accordance with some embodiments. The wiring layers114bare formed in the dielectric layer114a, in accordance with some embodiments. In some embodiments, the redistribution structure114provides interconnections between chip structures120,130, and140, and to the semiconductor structure111.

As shown inFIG.1A, the conductive vias114care electrically connected between different wiring layers114band between the wiring layer114band the conductive pads115, in accordance with some embodiments. For the sake of simplicity,FIG.1Aonly shows one of the wiring layers114b, in accordance with some embodiments. The conductive vias112are electrically connected to the conductive pads115through the wiring layers114band the conductive vias114c, in accordance with some embodiments.

As shown inFIG.1A, the chip structures120,130, and140are bonded to the substrate110through the conductive bumps150between the chip structures120,130and140and the substrate110, in accordance with some embodiments. The chip structure120or130includes a chip, such as a system on chip (SoC), in accordance with some embodiments. In some other embodiments, the chip structure120or130includes a chip package structure.

In some embodiments, the chip structure140includes multiple semiconductor dies. As shown inFIG.1A, the chip structure140includes semiconductor dies141,142,143, and144, in accordance with some embodiments. In some embodiments, the chip structure140includes a molding layer145that encapsulates and protects the semiconductor dies142,143and144. The molding layer145may include an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof.

In some embodiments, the semiconductor dies142,143and144are memory dies. The memory dies may include memory devices such as static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, other suitable devices, or a combination thereof. In some embodiments, the semiconductor die141is a control die that is electrically connected to the memory dies (e.g., the semiconductor dies142,143and144) stacked thereon. The chip structure140may function as a high bandwidth memory (HBM).

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the chip structure140includes a single semiconductor chip. The semiconductor chip may be a system on chip.

In some embodiments, conductive bonding structures146are formed between the semiconductor dies141,142,143and144to bond them together, as shown in FIG.1A. In some embodiments, each of the conductive bonding structures146includes metal pillars and/or solder bumps.

In some embodiments, underfill layers147are formed between the semiconductor dies141,142,143and144to surround and protect the conductive bonding structures146. In some embodiments, the underfill layer147includes an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof.

In some embodiments, multiple conductive vias148are formed in the semiconductor dies141,142, and143, as shown inFIG.1A. Each conductive via148penetrates through one of the semiconductor dies141,142, and143and is electrically connected to the conductive bonding structures146thereunder and/or thereover. Electrical signals can be transmitted between these vertically stacked semiconductor dies141,142,143and144through the conductive vias148.

As shown inFIG.1A, an underfill layer160is formed into a gap G1between the substrate110and each of the chip structures120,130, and140, in accordance with some embodiments. As shown inFIG.1A, a gap G2between the chip structures130and140is filled with a portion162of the underfill layer160, in accordance with some embodiments.

As shown inFIG.1A, a gap G3between the chip structures120and130is filled with the underfill layer160, in accordance with some embodiments. The underfill layer160surrounds the chip structures120,130, and140, in accordance with some embodiments. The underfill layer160is referred to as a protective layer, in accordance with some embodiments. The underfill layer160includes a polymer material, in accordance with some embodiments

As shown inFIG.1A, a molding layer170is formed over the substrate110to surround the chip structures120,130and140and the conductive bumps150, in accordance with some embodiments. The molding layer170includes a polymer material, in accordance with some embodiments.

As shown inFIG.1B, a lower portion of the semiconductor structure111is removed, in accordance with some embodiments. The removal process includes a chemical mechanical polishing process, in accordance with some embodiments. After the removal process, the conductive vias112and the insulating layer113are exposed, in accordance with some embodiments.

The conductive vias112and the insulating layer113pass through the semiconductor structure111, in accordance with some embodiments. The conductive vias112are also referred to as through-substrate vias (TSVs) or through-silicon vias when the semiconductor structure111is a silicon substrate, in accordance with some embodiments.

In accordance with some embodiments, the semiconductor structure111includes additional interconnect structures, besides the TSVs shown inFIG.1B. For example, the additional interconnect structures can include metal interconnect lines formed in dielectric layers. In some embodiments, the semiconductor structure111is divided into routing regions111-1and non-routing regions111-2. The interconnect structures are disposed in the routing regions111-1, and no interconnect structures are disposed in the non-routing regions111-2. In accordance with some embodiments, the non-routing regions111-2are available for modification without affecting the bonding and interconnection of the chip package. For example, the non-routing regions111-2can be used for forming stress and warpage relief structures, as described below.

FIG.2is a cross-sectional view of an exemplary IC chip package structure having an interposer with warpage-reducing trenches, in accordance with some embodiments. As shown inFIG.2, an integrated circuit (IC) chip package structure200includes an interposer210having a substrate211and an insulator layer212and conductive interconnect structures (213,216, and217) disposed in and on the substrate211.

The chip package structure200also includes a redistribution layer215formed on the interposer210, in accordance with some embodiments. The redistribution layer215includes contact and interconnect structures213in dielectric layer215-1made of one or more insulating materials, such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments. The redistribution layer215is configured to provide interconnections between chip structures and to the interposer210.

According to some embodiments, the interposer210and redistribution layer215are similar to interposer110and the redistribution structure114described above in connection withFIGS.1A and1B. The materials and formation processes described above also applied to the device structures depicted inFIG.2. In some embodiments, the redistribution layer can be made part of the interposer, as shown inFIGS.1A and1B.

The chip package structure200also includes IC chip structures201,202, and203bonded through conductive bumps207to redistribution layer215, which is connected to the interposer210. The chip structures201,202, and203can include a chip, such as a system on chip (SoC), in accordance with some embodiments, similar to chip structures120and130described above in connection toFIGS.1A and1B. In some other embodiments, the chip structures201,202, and203can include a chip package structure including multiple semiconductor dies, similar to the chip structure140described above in connection toFIGS.1A and1B.

The interposer210has two opposite surfaces: a front surface210aand a back surface210b. The front surface210afaces IC chip structures201,202, and203. The back surface210bis the opposite surface, and faces a package substrate (not shown), in accordance with some embodiments. The interposer210includes a substrate211and an insulator layer212and conductive interconnect structures (214,216, and217) disposed in and on the substrate211. The redistribution layer215includes contact and conductive interconnect structures213formed in insulator layer215-1.

The substrate211is made of a fiber material, a polymer material, a semiconductor material, a glass material, a metal material, or another suitable material. The fiber material includes, for example, a glass fiber material. The semiconductor material includes, for example, silicon or germanium. Insulating layer212is made of a dielectric material suitable for a silicon integrated circuit process, such as silicon oxide or silicon nitride, etc. The substrate211also includes conductive structures for electrical connections between various dies and with a package substrate.

For example, these interconnect structures include contact pads213, through-substrate vias (TSVs)214, and conductive structures216and217, etc. The interconnect and conductive structures are made of a conductive material, such as metal (e.g. copper, aluminum, or tungsten), in accordance with some embodiments.

The interposer substrate211has a thickness ranging from about 50 μm to about 300 μm, in accordance with some embodiments. However, it is understood that the thickness and spacing ranges are only cited as examples, and variations can be made depending on the applications.

The insulating layers212and215-1is made of an insulating material, such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments. Other suitable insulating material can also be used. Contact and interconnect structures213,216, and217are formed in the insulating layers215-1and212, respectively. In some cases, the contact and interconnect structures213are formed for connecting the bumps207with the interposer210. The contact and interconnect structures213are made of a suitable conductive material, such as metals (e.g. copper, aluminum, or tungsten, etc., or other suitable metals), in accordance with some embodiments. The contact and interconnect structures213can also include a surface finish material (e.g., nickel, palladium, and/or gold) or a solder material, such as Sn and Ag or another suitable conductive material, in accordance with some embodiments.

A molding compound material or an underfill material (not shown) is formed between the chip structures201,202, and203and the contact and interconnect structures213and surrounds the bumps207. The molding compound material and underfill material can include epoxy and filler material, or other suitable materials, in accordance with some embodiments. In some embodiments, the molding layer can surround the interposer210, the chips201-203, the conductive bumps207, and the underfill layer that are disposed on a package substrate as shown inFIGS.1A and1B.

In accordance with some embodiments, the interposer210includes additional interconnect structures, besides those shown inFIG.2. For example, the additional interconnect structures can include metal interconnect lines, contact structures, TSVs, etc. formed in dielectric layers. In some embodiments, the interposer210includes routing regions210-1and non-routing regions210-2and210-3. The interconnect structures are disposed in the routing regions210-1, and no interconnect structures are disposed in the non-routing regions210-2and210-3. The routing regions have conductive interconnect structures in and on the substrate for connecting to a group of IC dies. The processes for forming the contact and conductive interconnect structures are similar to those described above in connection toFIGS.1A and1B.

In accordance with some embodiments, the non-routing regions210-2and210-3are available for modification without affecting the bonding and interconnection structures of the chip package. For example, the non-routing regions210-2can be used for forming stress and warpage relief structures.

As shown inFIG.2, the group of IC dies is bonded to the interposer210through redistribution layer215to form an IC chip package200. The interposer210includes a first plurality of warpage-reducing trenches221in a first non-routing region210-2of the interposer210. The first plurality of warpage-reducing trenches221are characterized by a first trench width W1, first trench spacing S1, first trench depth D1, and first trench length (not shown inFIG.2). A first warpage-relief material221-1is deposited in the first plurality of warpage-reducing trenches221.

As shown inFIG.2, the interposer includes a second plurality of warpage-reducing trenches222in a second non-routing region210-3of the interposer210. The second plurality of warpage-reducing trenches222are characterized by a second trench width W2, second trench spacing S2, second trench depth D2, and second trench length (not shown inFIG.2). A second warpage-relief material222-1is deposited in the second plurality of warpage-reducing trenches222.

In accordance to some embodiments, the trenches221and222are sized and positioned and deposited with a stress relief material according to the warpage characteristic of the chip package structure to reduce warpage. Depending on the embodiments, some of the trenches are formed in insulator layer212, and some of trenches can be formed in insulator layer212and extend into substrate211, depending on trench depth required for warpage relief.

As described below, the trenches can have elongated shapes with long sides perpendicular to a warpage direction in accordance with some embodiments. In some cases, the warpage-relief material comprises a tensile film to counter compressive stress in the interposer. In other cases, the warpage-relief material comprises a compressive film to counter tensile stress in the interposer.

In some embodiments, the first plurality of warpage-reducing trenches221includes trenches having elongated shapes with long sides perpendicular to a first direction of a compressive stress in the interposer, and the first warpage-relief material is a tensile film deposited in the first plurality of warpage-reducing trenches.

In some embodiments, the second plurality of warpage-reducing trenches222includes trenches having elongated shapes with long sides perpendicular to a second direction of a tensile stress in the interposer, and a second warpage-relief material is a compressive film deposited in the second plurality of warpage-reducing trenches

In some embodiments, the tensile film includes a metal film, such as aluminum, copper, tungsten, titanium, or other suitable film, or combination thereof. The compressive film includes a silicon oxide film, a silicon nitride film, or a combination thereof.

In accordance with some embodiments, the warpage-reducing trenches may have different trench widths, trench spacings, trench depths, trench lengths, and trench densities, depending on the warpage characteristics of the interposer, as described in more detail below. In some embodiments, the first and second pluralities of warpage-reducing trenches may have different trench widths, trench spacings, trench depths, trench lengths, and trench densities, For example, Further details of the trench forming process are also explained below.

A chip package structure that includes regions where dies are disposed adjacent to one another is susceptible to warpage after thermal cycling, such as after a reflow process to reflow the solder balls or bumps. In some examples, a coefficient of thermal expansion (CTE) of the dies or encapsulant (e.g., molding compound) and/or other components on the interposer is greater than a CTE of the interposer. Hence, when the chip package structure is heated during a reflow process, the dies and the molding compound can expand a different amount than the interposer. The difference in the amount of expansion can cause warpage of the package.

FIG.3shows a top view of an exemplary IC chip package structure and images of measured warpages, in accordance with some embodiments. As shown inFIG.3, chip package structure300includes a processor die301, and memory dies311,312,313, and314bonded to an interposer320. As described above inFIGS.1A,1B, and2, dies301and311-314are bonded to interposer320using conductive bumps (not seen inFIG.3).

Chip package structure300also shows two rectangular regions,321and322, drawn by broken lines, which indicate high stress regions in chip package structure300. Rectangular regions321and322, where dies are disposed adjacent to one another, are susceptible to warpage after thermal cycling, such as after a reflow process to reflow the solder balls or bumps. In some examples, a coefficient of thermal expansion (CTE) of the dies or encapsulant (e.g., molding compound) and/or other components on the interposer320is greater than a CTE of the interposer320. Hence, when the package300is heated during a reflow process, the dies and the molding compound can expand a different amount than the interposer320. The difference in the amount of expansion can cause warpage of the chip package structure300.

InFIG.3, diagrams350and360illustrate Shadow Moire images showing warpage in chip package structure300before and after a thermal process, in accordance with some embodiments. Shadow Moiré is a non-contact optical technique that uses geometric interference between a reference grating and its shadow on a sample to measure relative vertical displacement at each pixel position in the resulting image. The imaging is produced using a grating, a light source at approximately 45 degrees to the grating, and a camera perpendicular to the grating. A phase stepping technique can be applied to Shadow Moiré to increase measurement resolution and provide automatic ordering of the interference fringes.

InFIG.3, diagram350illustrates a Shadow Moire image of chip package structure300showing an upward-bending warpage before a thermal process. Diagram360shows a shadow Moire image of chip package structure300showing a downward-bending warpage after the thermal process, caused by a compressive stress on the interposer320. If the stress is sufficiently large, a breakage of the package could occur, as illustrated inFIG.3. Even if the stress is not large enough to cause breakage, the integrity of the package can be compromised. For example, electrical contact points in the high stress regions can be affected, resulting in increased contact resistance, or even contact failures.

With identification of warpage in the interposer having been illustrated, attention is now directed toFIG.4, which illustrates an example of selecting materials to deposit in warpage-relieving trenches to strengthen the interposer for addressing the warpage. As can be seen, on the left ofFIG.4, cross-sectional views of a portion of a substrate for an example interposer in accordance with some embodiments. On the right ofFIG.4, a graph of warpage data is shown. InFIG.4, a structure410including a substrate401is shown for forming an interposer. As also shown, trenches402are formed in the substrate401so materials can be deposited in those trenches. In this example, each trench402has trench sidewalls403and a bottom405.

In various implementations, the substrate401can be made of a fiber material, a polymer material, a semiconductor material, a glass material, a metal material, or any another suitable material. In some embodiments, the substrate401is made of a semiconductor material, such as silicon or germanium. To form the trenches, a patterned mask (not shown) is formed on the substrate401using patterning and etching process. The mask can be a photoresist mask or a hard mask. In some examples, the hard mask is made of silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN) or silicon nitride (SiN or Si3N4), or another suitable material. The hard mask is formed using deposition, photolithography, and etching processes. With the patterned mask, the trenches can be etched in the substrate401. The etching processes may include a reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, or another suitable process, or a combination thereof.

As mentioned, for addressing the warpage, a warpage-relief material is selected and formed in the trenches to counteract or reduce the warpage in the interposer substrate caused by the packaging operation. For example, metal tends to have higher thermal expansion coefficients than semiconductors such as silicon, germanium, etc. depending on processing conditions. Dielectrics, such as silicon oxide, silicon nitride, etc., tend to have lower thermal expansion coefficients than semiconductors. Therefore, at room temperature, dielectric films tend to be under compressive stress, or have compressive strains. In contrast, metal films tend to be under tensile stress, or have tensile strains. These properties can be used to deposit different materials in the trenches to affect the warpage. For example, if the chip package structure causes the interposer to exhibit an upward warpage, then the warpage-relief material can be chosen such that after going through the packaging thermal cycle, the warpage-relief material causes the substrate to bend downward to counter the warpage. Similarly, if the chip package structure causes the interposer to exhibit a downward warpage, then the warpage-relief material can be chosen such that after going through the packaging thermal cycle, the substrate is caused to bend downward to counter the warpage.

InFIG.4, a second structure420shows a layer of material421deposited on the trench sidewalls403and bottom405. The trenches may be filled with the insulating material using a deposition process, such as chemical vapor deposition (CVD), flowable CVD (FCVD), a spin-on-glass (SOG) process, or another suitable process. The deposition process can be followed by a planarization process, such as a chemical-mechanical polishing (CMP) process or an etching process.

InFIG.4, diagram430shows plots of substrate warpage as a function of the thickness of the material421deposited in the trenches, in accordance with some embodiments. In diagram430, the horizontal axis is the position along the wafer radius. The vertical axis shows the amount of warpage as a function of a thickness of material421, from 0 to 300 in a normalized unit. In this experiment, the material421is silicon oxide. The data points shown in open triangles431are for deposited material of a base line thickness, labeled STD. The data points shown in open squares432are for the deposited material having a thickness 10% thinner than the base line thickness. The data points shown in open rhombus433are for the deposited material having a thickness 20% thinner than the base line thickness. It can be seen from diagram430that the deposited silicon oxide material in the trenches appears to exert a stress that causes the substrate to concave downwards. Further, reducing the thickness of the deposited material appears to reduce the extent of warpage.

FIG.5shows a diagram500illustrating substrate warpage as a function of the trench density, in accordance with some embodiments. In diagram500, the horizontal axis is the trench density in percentage (%), in a normalized unit. The vertical axis shows the amount of warpage as a function of the trench density, in another normalized unit. The data points shown in rhombus501illustrate the increase in warpage magnitude with increasing trench percentage after the formation of the trenches. The data points shown in triangles502illustrate the increase in warpage magnitude with increasing trench percentage after the trenches are filled with TaN. The data points shown in rectangles503illustrate the increase in warpage magnitude with increasing trench percentage after the trenches are filled with TiN. It can be seen from diagram500that the amount of warpage can be adjusted with trench density and the trench-relief material formed inside the trenches.

FIG.6shows an example of trenches in a substrate to reduce warpage, in accordance with some embodiments. InFIG.6, diagram610is a top view of a substrate631with trenches633disposed in the substrate631. As shown, the trenches633in substrate631are formed to have elongated shapes with long sides perpendicular to the warpage direction, which is the X-direction in this example. As an example, the warpage direction in the X-direction is characterized by the Shadow Moire images in diagrams350and360inFIG.3. Diagram350shows a downward-bending warpage along the X direction, and diagram360shows an upward-bending warpage along the X direction. The trenches are sized and shaped based on the warpage characteristic of the chip package structure. Trenches633are warpage-reducing trenches formed in a non-routing region of the substrate631. The plurality of warpage-reducing trenches633are characterized by a trench width W6, trench spacing S6, trench length L6, and trench depth (not shown inFIG.6).

FIG.7shows an example of trenches in a substrate to reduce warpage, in accordance with some embodiments. InFIG.7, diagram730is a top view of a substrate731with trenches733disposed in the substrate731. As shown, the trenches733in substrate731are formed to have elongated shapes with long sides perpendicular to the warpage direction, which is the Y-direction in this example. In this example, the warpage direction is determined to be in the X-direction as characterized by the Shadow Moire images The trenches are sized and shaped based on the warpage characteristic of the chip package structure. Trenches733are warpage-reducing trenches formed in a non-routing region of the substrate731. The plurality of warpage-reducing trenches733are characterized by a trench width W7, trench spacing S7, trench length L7, and trench depth (not shown inFIG.7).

As described above, The trenches are sized and shaped based on the warpage characteristic of the chip package structure. The trench width, trench spacing, trench length, and trench depth can be selected based on the warpage characteristic of the chip package structure. For example, in some embodiments, the trench width W6and W7is in a range between 5 μm and 20 μm, for example 12 μm. The trench spacing S6and S7is in a range between 20 μm and 120 μm, for example=80 um. The trench length L6and L7is in a range between 10 μm and 2000 μm, for example=400 um. Further, the trench depth can be in a range between 5 μm and 250 μm, for example, 70 μm. Further, the global density of trenches can be increased to increase warpage effect.

Further, the warpage-relief material disposed in the trenches and the thickness of the film are also selected and determined based on the warpage characteristic of the chip package structure, for example, in accordance with principles shown inFIG.4. In various implementations, the warpage-relief material can be a compressive film to counter tensile stress in the chip package structure, and the warpage-relief material can be a tensile film to counter compressive stress in the chip package structure.

FIG.8shows additional examples of forming trenches in a substrate to reduce warpage, in accordance with some embodiments. InFIG.8, diagram810is a top view of a substrate811with trenches813disposed in the substrate811. In diagram810, trenches813are placed at corners of substrate811based on the warpage characteristic of the chip package structure, which indicates that warpage occurs at the corner. Therefore, the trenches are disposed at the corners, and a warpage relief material is deposited to reduce the warpage. In this example, a plurality of trenches813are formed near the corners of the substrate to counter the warpage at the corners of the substrate. For example, the trenches813are formed at an angle to the sides of the substrate adjacent to the corners. In some embodiments, the angle is between 30 to 70 degrees, for example 45 degrees. The trench width, trench spacing, trench length, trench depth, and trench density can be selected based on the warpage characteristic of the chip package structure. Depending on the embodiments, the trench width is in a range between 5 μm and 20 μm, for example 12 μm. The trench spacing is in a range between 20 μm and 120 μm, for example=80 um. The trench length is in a range between 10 μm and 2000 μm, for example=400 um. Further, the trench depth is in a range between 5 μm and 250 μm, for example, 70 μm, in accordance with some embodiments. Further, the global density of trenches can be increased to increase warpage effect.

Diagram830is a top view of a chip package structure, similar to chip package structure300inFIG.3, which includes a processor die801, labeled as CPU, and memory dies831,832,833, and834bonded to an interposer835. Diagram830also shows trenches837and838disposed on interposer835in non-routing regions, where there are no conductive interconnect structures and where spaces are available on the interposer to relieve warpage based on the warpage characteristic of the chip package structure.

For example, trenches837are formed to have elongated rectangles oriented horizontally between an edge of die801and an edge of the interposer835. In some embodiments, the length of the trenches is a fraction of the length of the edge of die801, for example from 10% to 70%. In some cases, the length of the trenches is a 25% of the length of the edge of die801.

As another example, trenches838are formed to have elongated rectangles oriented horizontally between die801and die833. In some embodiments, the length of the trenches is a fraction of the length of the space between two dies801and833, for example from 10% to 70%. In some cases, the length of the trenches is a 25% of the length of the space between two dies801and833.

As illustrated in the above examples, a method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, in accordance with some embodiment. The method also includes forming trenches in the substrate of the interposer, wherein the trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method further includes depositing a warpage-relief material in the trenches according to the warpage characteristic to reduce the warpage of the chip package structure. The method includes forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method also includes bonding the group of the selected IC dies to the interposer to form a chip package structure.

In accordance to some embodiments, the warpage characteristic of the chip package structure can be determined empirically by measuring the warpage of a chip package structure. For example, such measurement can be performed using a Shadow Moire method. Alternatively, in some embodiments, the warpage characteristic can be determined based on physical analysis and computer simulation. An example of a method based on the empirical approach is described below with reference toFIG.9.

FIG.9is a flowchart for a method for forming an integrated circuit (IC) chip package structure, in accordance with some embodiments. As shown inFIG.9, method900describes a method for forming a chip package structure with warpage-relief trench structures in the interposer substrate. The operations in method900are briefly summarized below with reference toFIGS.1-8described above, and additional information provided inFIGS.10-14. It is noted that method900as described below may not include all the details to produce a complete semiconductor device. Accordingly, additional processes can be provided before, during, and after those described in method900. It is also understood that the operations in method900can be performed in a different order, or some operations not performed, depending on specific applications.

Briefly, method900includes determining a warpage characteristic of a chip package structure including a first group of selected IC dies bonded to a first interposer without the trenches. The trench structures and warpage-relief materials are formed in a second interposer, before a second group of selected IC dies are bonded to the second interposer.

As shown inFIG.9, in operation910, the method includes providing a first substrate for a first interposer for connecting a first group of selected IC dies. An example of a chip package structure including a group of selected IC dies on an interposer is shown inFIG.2, in which chip package structure200includes IC chip structures201,202, and203bonded to an interposer210. The group of selected IC dies in IC chip structures201,202, and203can include processors, systems-on-chip, or memory chips. The interposer210includes a substrate211.

In operation920, a conductive interconnect structure is formed in and on the substrate for connecting the first group of the selected IC dies. An example of the conductive interconnect structure is shown inFIG.2, where the interconnect structures include through-silicon vias (TSVs)215, contact pads216, and interconnect structures217. The interconnect and conductive structures are made of a conductive material, such as metal (e.g. copper, aluminum, or tungsten), in accordance with some embodiments. The conductive interconnect structure can also include contact and interconnect structures213formed in insulating layer212on substrate211.

In operation930, the method includes bonding the first group of the selected IC dies to the first interposer to form a first IC chip package structure. As shown inFIG.2, chip structures201,202, and203are bonded to the interposer210by bumps207. In some embodiments, the bonding operation also includes forming a molding compound material or an underfill material between the chip structures201,202, and203and the contact and interconnect structures213and surrounding the bumps207, as described above in connection toFIG.2.

Method900also includes, in operation940, determining warpage characteristic of the first IC chip package structure. Examples of chip package structure warpage are shown inFIGS.3and4. As shown inFIG.3, chip package structure300includes a CPU die301and memory dies311,312,313, and314bonded to an interposer320. Chip package structure300also shows two rectangular regions,321and322, drawn by broken lines, that indicate high stress regions in chip package structure300. The different materials in the package can have residual strains from the fabrication processes. When the package300is heated up and cooled down during a reflow process, the components can expand or contract differently, which can cause warpage or even breakage of the package300. InFIG.3, diagrams350and360illustrate Shadow Moire images showing warpage in chip package structure300before and after a thermal process, in accordance with some embodiments. The amount of warpage can be determined by Shadow Moire imaging method or other suitable method. As described below, the warpage characteristic is used in modifying the interposer substrate to reduce the warpage.

In operation950, a second substrate is provided for a second interposer for connecting a second group of the selected IC dies. As described above regarding the first substrate, the substrate can be a suitable material. In some embodiments, the substrate is a silicon substrate.

In operation960, trenches are formed in the second substrate and a layer of warpage-relief material is deposited in the trenches based on the warpage characteristic of the first IC chip package structure. The trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure.FIGS.6-8shows examples of determining the sizes and shapes of the trenches based on the warpage characteristic determined in operation950. For example, in some embodiments, trenches are formed in the substrate that are aligned perpendicular to a direction of warpage. If the warpage occurs in the X-direction, then trenches that are elongated in the Y-direction can be used. Similarly, if the warpage occurs in the Y-direction, then trenches that are elongated in the X-direction can be used. Further, the number, size, and position of the trenches can be determined based on the warpage characteristic.

Different materials can be deposited in the trenches. For example, the warpage-relief material can be deposited in one or more trenches. In some cases, a tensile material can be deposited to counter compressive stress in the IC chip package structure. Similarly, a compressive material can be deposited to counter tensile stress in the IC chip package structure. Here, tensile materials refer to a material, e.g., a metal, that exhibits tensile strains or under tensile stress at room temperature. Similarly, compressive materials, e.g., a dielectric, refers to material that exhibits compressive strains or under compressive stress at room temperature. The thickness of the warpage-relief material can be varied based on the warpage characteristic.FIG.5illustrates the effect of varying the thickness of the material deposited in the trenches on the amount of warpage.

The design of the trenches can be determined empirically, through physical analysis, or simulation, in accordance with some embodiments. A process of forming the trenches is described below with reference toFIG.10. Variations of trench structures are described below with reference toFIGS.11-12.

In operation970, the conductive interconnect structures are formed in and on the second substrate for connecting the second group of the selected IC dies. Here, the process of forming the conductive interconnect structure is similar to the process described above in connection to operation920.

It is noted that, even though operation960of forming trenches and operation970of forming conductive interconnect structures are described sequentially, the detailed fabrication steps can be adjusted in different embodiments. For example, different components of the conductive interconnect structures can be formed before or after forming the warpage-relief trenches. For example, in some cases, the trenches can be formed in the substrate first. In other cases, TSVs in the conductive interconnect structures can be formed before the warpage-relief trenches are formed.

In operation980, the second group of the selected IC dies are bonded to the second interposer to form a second IC chip package structure. Here, the process of forming the conductive interconnect structure is similar to the process described above in connection to operation930.FIGS.13and14illustrate examples of IC chip package structures built on interposers with built-in warpage relief trenches.

FIG.10presents cross-sectional views illustrating a method for forming trenches in an interposer, in accordance with some embodiments. As shown inFIG.10, method1000illustrates a method for forming trenches in a substrate of an interpose for relieving warpage in a chip package structure. The method includes forming trenches and disposing a warpage-relief material in the trenches.

At operation1010, the method starts with forming a substrate1001for an interposer. Substrate1001can be made of a fiber material, a polymer material, a semiconductor material, a glass material, a metal material, or any another suitable material. In the embodiments described herein, the semiconductor material includes, for example, silicon or germanium. In some embodiments, the substrate is a silicon substrate.

Next, trenches1003are formed in substrate1001. To form the trenches1003, a patterned mask (not shown) is formed on the substrate1001using patterning and etching processes. The mask can be a photoresist mask or a hard mask. In some examples, the hard mask is made of silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN) or silicon nitride (SiN or Si3N4), or another suitable material. The hard mask is formed using deposition, photolithography, and etching processes. With the patterned mask, the trenches1003can be etched in the substrate1001. The etching processes may include a reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch or another suitable process, or a combination thereof. As shown inFIG.10, each trench1003has a top surface1004, a bottom surface1005, and sidewalls1006. Further, a warpage-relief material1011is disposed in trenches1003. The warpage-relief material1011can be selected as described above in connection withFIGS.5and9. The deposition process can be a chemical vapor deposition (CVD), flowable CVD (FCVD), a spin-on-glass (SOG) process, or another suitable process.

At operation1020, excess warpage-relief material1011from the top surface1004of the trenches is removed using a planarization process, such as a CMP process or an etching process.

At operation1030, a molding or underfill material1031is formed to cover the structure in operation1020. The molding compound material and underfill material can include epoxy and filler material, or other suitable materials, in accordance with some embodiments. The molding or underfill material can substantially fill the space in the trenches to provide a low step coverage and a flat surface for a subsequent bump process. In some embodiments, small voids1033can remain in the molding or underfill material1031.

FIG.11presents cross-sectional views of methods for forming trenches in an interposer, in accordance with some embodiments.FIG.11shows three substrate structures that have different designs of trench structures. InFIG.11, structure1110shows a substrate1101having a top surface1102and a back surface1103. Trenches1113are formed from the top surface1102of substrate1101.

Structure1120shows a substrate1101having a top surface1102and a back surface1103. Trenches1123are formed from the top surface1102of substrate1101. In this structure, the warpage-relief material will have an opposite effect as the same warpage-relief material disposed in the trenches formed the top surface of the substrate.

Structure1130shows a substrate1101having a top surface1102and a back surface1103. Trenches1131,1132, and1133are formed from the top surface1102of substrate1101. It is noted that trenches1131,1132, and1133have different depths.

FIG.12are cross-sectional views of additional methods for forming trenches in an interposer, in accordance with some embodiments. Similar toFIG.11,FIG.12shows three substrate structures that have different designs of trench structures. Unlike,FIG.11, however, the trench structures inFIG.12are substantially filled with a material characterized by a higher hardness than the substrate material. Examples of such materials include silicon carbide (SiC), diamond, etc., or other suitable materials. The increased hardness and rigidity can reduce warpage caused by the packaging materials and processes.

Structure1210shows a substrate1201having a top surface1202and a back surface1203. Trenches1213are formed from the top surface1202of substrate1201. Structure1220shows a substrate1201having a top surface1202and a back surface1203. Trenches1223are formed from the top surface1202of substrate1201. Structure1230shows a substrate1201having a top surface1202and a back surface1203. Trenches1231,1232, and1233are formed from the top surface1202of substrate1201. It is noted that trenches1231,1232, and1233have different depths.

FIG.13is an exemplary IC chip package structure having an interposer with trenches for reducing warpage, in accordance with some embodiments. As shown inFIG.13, an integrated circuit (IC) chip package structure1300includes an interposer1310having a substrate1311and an insulator layer1312and conductive interconnect structures (1313,1316, and1317) disposed in and on the substrate1311.

The chip package structure1300also includes a redistribution layer1315formed on the interposer1310, in accordance with some embodiments. The redistribution layer1315includes contact and interconnect structures1313in dielectric layer1315-1made of one or more insulating materials, such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments. The redistribution layer1315is configured to provide interconnections between chip structures and to the interposer1310.

According to some embodiments, the interposer1310and redistribution layer1315are similar to interposer110and the redistribution structure114described above in connection withFIGS.1A and1B. The materials and formation processes described above also applied to the device structures depicted inFIG.3. In some embodiments, the redistribution layer can be made part of the interposer, as shown inFIGS.1A and1B.

The chip package structure1300also includes IC chip structures1301,1302, and1303bonded through conductive bumps1307to redistribution layer1315, which is connected to the interposer1310. The chip structures1301,1302, and1303can include a chip, such as a system on chip (SoC), in accordance with some embodiments, similar to chip structures120and130described above in connection toFIGS.1A and1B. In some other embodiments, the chip structures1301,1302, and1303can include a chip package structure including multiple semiconductor dies, similar to the chip structure140described above in connection toFIGS.1A and1B.

The interposer1310has two opposite surfaces: a front surface1310aand a back surface1310b. The front surface1310afaces IC chip structures1301,1302, and1303. The back surface1310bis the opposite surface, and faces a package substrate (not shown), in accordance with some embodiments. The interposer1310includes a substrate1311and an insulator layer1312and conductive interconnect structures (1314,1316, and1317) disposed in and on the substrate1311. The redistribution layer1315includes contact and conductive interconnect structures1313formed in insulator layer1315-1.

The substrate1311is made of a fiber material, a polymer material, a semiconductor material, a glass material, a metal material, or another suitable material. The fiber material includes, for example, a glass fiber material. The semiconductor material includes, for example, silicon or germanium. Insulating layer1312is made of a dielectric material suitable for a silicon integrated circuit process, such as silicon oxide or silicon nitride, etc. The substrate1311also includes conductive structures for electrical connections between various dies and with a package substrate.

For example, these interconnect structures include contact pads1313, through-substrate vias (TSVs)1314, and conductive structures1316and1317, etc. The interconnect and conductive structures are made of a conductive material, such as metal (e.g. copper, aluminum, or tungsten), in accordance with some embodiments.

The interposer substrate1311has a thickness ranging from about 50 μm to about 300 μm, in accordance with some embodiments. However, it is understood that the thickness and spacing ranges are only cited as examples, and variations can be made depending on the applications.

The insulating layers1312and1315-1is made of an insulating material, such as a polymer material (e.g., polybenzoxazole, polyimide, or a photosensitive material), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or the like, in accordance with some embodiments. Other suitable insulating material can also be used. Contact and interconnect structures1313,1316, and1317are formed in the insulating layers1315-1and1312, respectively. In some cases, the contact and interconnect structures1313are formed for connecting the bumps1307with the interposer1310. The contact and interconnect structures1313are made of a suitable conductive material, such as metals (e.g. copper, aluminum, or tungsten, etc., or other suitable metals), in accordance with some embodiments. The contact and interconnect structures1313can also include a surface finish material (e.g., nickel, palladium, and/or gold) or a solder material, such as Sn and Ag or another suitable conductive material, in accordance with some embodiments.

A molding compound material or an underfill material (not shown) is formed between the chip structures1301,1302, and1303and the contact and interconnect structures1313and surrounds the bumps1307. The molding compound material and underfill material can include epoxy and filler material, or other suitable materials, in accordance with some embodiments. In some embodiments, the molding layer can surround the interposer1310, the chips1301-1303, the conductive bumps1307, and the underfill layer that are disposed on a package substrate as shown inFIGS.1A and1B.

In accordance with some embodiments, the interposer1310includes additional interconnect structures, besides those shown inFIG.13. For example, the additional interconnect structures can include metal interconnect lines, contact structures, TSVs, etc. formed in dielectric layers. In some embodiments, the interposer1310includes routing regions1310-1and non-routing regions1310-2and1310-3. The interconnect structures are disposed in the routing regions1310-1, and no interconnect structures are disposed in the non-routing regions1310-2and1310-3. The routing regions have conductive interconnect structures in and on the substrate for connecting to a group of IC dies. The processes for forming the contact and conductive interconnect structures are similar to those described above in connection toFIGS.1A and1B.

In accordance with some embodiments, the non-routing regions1310-2and1310-3are available for modification without affecting the bonding and interconnection structures of the chip package. For example, the non-routing regions1310-2can be used for forming stress and warpage relief structures.

As shown inFIG.13, the group of IC dies is bonded to the interposer1310through redistribution layer1315to form an IC chip package1300. The interposer1310includes a first plurality of warpage-reducing trenches1321in a first non-routing region1310-2of the interposer1310. The first plurality of warpage-reducing trenches1321are characterized by a first trench width W1, first trench spacing S1, first trench depth D1, and first trench length (not shown inFIG.13). A first warpage-relief material1321-1is deposited in the first plurality of warpage-reducing trenches1321.

As shown inFIG.13, the interposer includes a second plurality of warpage-reducing trenches1322in a second non-routing region1310-3of the interposer1310. The second plurality of warpage-reducing trenches1322are characterized by a second trench width W2, second trench spacing S2, second trench depth D2, and second trench length (not shown inFIG.13). A second warpage-relief material1322-1is deposited in the second plurality of warpage-reducing trenches1322.

In accordance to some embodiments, the warpage-reducing trenches1321and1322are sized and positioned and deposited with a stress relief material according to the warpage characteristic of the chip package structure to reduce warpage. Depending on the embodiments, some of the trenches are formed in insulator layer1312, and some of trenches can be formed in insulator layer1312and extend into substrate1311, depending on trench depth required for warpage relief.

As described below, the trenches have elongated shapes with long sides perpendicular to a warpage direction in accordance with some embodiments. In some cases, the warpage-relief material comprises a tensile film to counter compressive stress in the interposer. In other cases, the warpage-relief material comprises a compressive film to counter tensile stress in the interposer.

In some embodiments, the first plurality of warpage-reducing trenches1321includes trenches having elongated shapes with long sides perpendicular to a first direction of a compressive stress in the interposer, and the first warpage-relief material is a tensile film deposited in the first plurality of warpage-reducing trenches.

In some embodiments, the second plurality of warpage-reducing trenches1322includes trenches having elongated shapes with long sides perpendicular to a second direction of a tensile stress in the interposer, and a second warpage-relief material is a compressive film deposited in the second plurality of warpage-reducing trenches

In some embodiments, the tensile film includes a metal film, such as aluminum, copper, tungsten, titanium, or other suitable film, or combination thereof. The compressive film includes a silicon oxide film, a silicon nitride film, or a combination thereof.

In accordance with some embodiments, the warpage-reducing trenches may have different trench widths, trench spacings, trench depths, and trench lengths, depending on the warpage characteristics of the interposer, as described in more detail below. Further details of the trench forming process are also explained below.

FIG.14is another exemplary IC chip package structure having an interposer with trenches for reducing warpage, in accordance with some embodiments. As shown inFIG.14, an integrated circuit (IC) chip package structure1400, which is similar chip package structure1300inFIG.13, but with additional components bonded to the back surface1310bof interposer1310. In the embodiments, an IC chip structure1404is bonded to the back surface1310bof interposer1310through a second redistribution layer1415. In this case, the second redistribution layer1415also includes a second insulating layer1415-1on the back surface1411b, and interconnect structures1433formed in the second insulating layer1415. The second redistribution layer1415can be bonded to the interposer1310using a bonding method, such as hybrid bonding. IC chip structure1404, which can include one or more IC dies, is bonded to the second redistribution layer1415through bumps1437.

FIG.15is a cross-sectional view of another exemplary IC chip package structure having an interposer warpage-reducing with trenches, in accordance with some embodiments. As shown inFIG.15, an integrated circuit (IC) chip package structure1500, which is similar chip package structure1400inFIG.14, but with IC chip structure1302and associated contact and interconnect structures1313,1314,1316,1317,1433, and1437removed. This arrangement creates space for a third plurality of warpage-reducing trenches1523. In accordance to some embodiments, similar to the warpage-reducing trenches1321and1322, the third plurality of warpage-reducing trenches1523is sized and positioned and deposited with a stress relief material according to the warpage characteristic of the chip package structure to reduce warpage. Depending on the embodiments, some of the trenches are formed in insulator layer1312, and some of trenches can be formed in insulator layer1312and extend into substrate1311, depending on trench depth required for warpage relief. Other properties of warpage-reducing trenches1323are similar to those described above in connection to trenches1321and1322.

In accordance with some embodiments, warpage-relief trench structures are formed in the substrate of an integrated circuit (IC) chip package structure. The trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. For example, locations, sizes, and shapes of the trenches are designed to counteract the stress in the chip package structure. A warpage-relief material is deposited in the trenches according to the warpage characteristic to reduce the warpage of the chip package structure. The warpage characteristic can be measured, e.g., using Shadow Moire or other measuring methods. Alternatively, the warpage characteristic can be determined using theoretical analysis or computer simulation methods. In addition, machine learning using artificial intelligence methodology, such as neural network, liner regression, etc., can also be used to determine the warpage characteristic of the package. For example, a tensile material is used to counter compressive stress in the package, and a compressive material is used to counter tensile stress in the package. The large surface area along the sidewalls of the trenches can enhance the effectiveness of the warpage-relief material. Further, to counter warpage along the x-direction, trenches having elongated shapes are arranged with long sides perpendicular to the x-direction direction. To counter warpage along the y-direction, trenches having elongated shapes are arranged with long sides perpendicular to the y-direction direction. The techniques described herein can lead to reduction of stress, warpage, or breakage in IC chip package structures, and can improve the performance and yield of the product.

In accordance with some embodiments, a method for forming an integrated circuit (IC) chip package structure includes providing a first substrate for a first interposer for connecting a first group of selected IC dies, forming a conductive interconnect structure in and on the substrate for connecting the first group of the selected IC dies, and bonding the first group of the selected IC dies to the first interposer to form a first IC chip package structure. The method also includes determining a warpage characteristic of the first IC chip package structure. The method further includes providing a second substrate for a second interposer for connecting a second group of the selected IC dies. Moreover, the method includes forming trenches in the second substrate and depositing a layer of warpage relief material in the trenches based on the warpage characteristic of the first IC chip package structure, and forming the conductive interconnect structure in and on the second substrate for connecting the second group of the selected IC dies. In addition, the method also includes bonding the second group of the selected IC dies to the second interposer to form a second IC chip package structure.

In accordance with some embodiments, a method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming trenches in the substrate of the interposer. The trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the trenches according to the warpage characteristic to reduce the warpage of the chip package structure. The method further includes forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies, and bonding the group of the selected IC dies to the interposer to form a chip package structure. In some embodiments, the method also includes determining a warpage characteristic of a chip package structure including the group of selected IC dies bonded to an interposer without the trenches.

In accordance with some embodiments, an integrated circuit (IC) chip package structure includes an interposer having a substrate and a conductive interconnect structure disposed in and on the substrate. The IC chip package structure also includes trenches formed in the substrate, and the trenches are sized and positioned and deposited with a stress relief material according to a warpage characteristic of the chip package structure to reduce warpage. The IC chip package structure further includes IC dies bonded to the interposer.

In accordance with some embodiments, a method for forming an integrated circuit (IC) chip package structure includes providing an interposer including a substrate. The interposer includes routing regions and non-routing regions. The routing regions have conductive interconnect structures in and on the substrate for connecting to a group of IC dies, and the non-routing regions are without the conductive interconnect structures. The method includes forming a first plurality of warpage-reducing trenches in a first non-routing region of the interposer. The first plurality of warpage-reducing trenches characterized by a first trench width, first trench spacing, first trench length, and a first trench density based on warpage characteristics in the first non-routing region. A first warpage-relief material is deposited in the first plurality of warpage-reducing trenches. The method also includes forming a second plurality of warpage-reducing trenches in a second non-routing region of the interposer, the second plurality of warpage-reducing trenches characterized by a second trench width, a second trench spacing, a second trench length, and a second trench density, wherein the second trench width is different from the first trench width, the second trench spacing is different from the second trench spacing, and the second trench length is different from the first trench spacing, based on based on warpage characteristics in the second non-routing region. A second warpage-relief material is deposited in the second plurality of warpage-reducing trenches. The method further includes bonding the group of IC dies to the interposer to form an IC chip package.

In accordance with some embodiments, a method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.

In accordance with some embodiments, an integrated circuit (IC) chip package structure includes an interposer having a substrate and a conductive interconnect structure disposed in and on the substrate. The IC chip package structure also includes warpage-reducing trenches formed in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned and deposited with a warpage relief material according to a warpage characteristic of the chip package structure to reduce warpage, and IC dies bonded to the interposer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.