Patent ID: 12218194

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art, Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present disclosure.

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated to dearly illustrate various features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it may not only refer to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.

Hereinafter, in an embodiment of the present disclosure, a high aspect ratio pattern may include an opening, a contact hole, a trench, and source/drain recesses. As for the high aspect ratios, the height-to-width ratio may be greater than approximately 1:1. The high aspect ratio pattern may be filled with a contact plug. The lower portion of the high aspect ratio pattern may be filled with a pad. That is, a contact plug may be formed over the pad. The pad may also be referred to as a contact pad or a landing pad.

The pad may be filled with an epitaxial layer by a bottom-up growth process. The bottom-up growth process may include a Selective Epitaxial Growth (SEG) process.

FIG.1is a plan view illustrating a semiconductor device in accordance with an embodiment of the present disclosure.FIGS.2A and2Bare cross-sectional views illustrating an example of a semiconductor device in accordance with an embodiment of the present disclosure.

Referring toFIGS.1,2A and23, the semiconductor device may include a plurality of memory cells. Each memory cell may include a cell transistor including a buried word line107, a bit line112, and a memory element121.

An isolation layer102and an active region103may be formed in a substrate101. A plurality of active regions103may be defined by the isolation layer102. The substrate101may be formed of a material containing silicon. The substrate101may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multi-layer thereof. The substrate101may also include other semiconductor materials, such as germanium. The substrate101may include a III/V group semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs), The substrate101may include a Silicon-On-Insulator (SOI) substrate. The isolation layer102may be formed, for example, by a Shallow Trench Isolation (STI) process.

A line-shaped buried gate structure BG extending in a short axis direction of the active region103may be formed in the substrate101. The buried gate structure BG may include a gate dielectric layer106formed on the surface of a gate trench105, a gate electrode107formed over the gate dielectric layer106to fill the gate trench105, and a gate capping layer108.

To be specific, a line-shaped gate trench105extending in the short axis direction of the active region103may be formed in the substrate101. The gate trench105may be formed to a predetermined depth in a region defined by a hard mask layer104which is formed on the surface of the substrate101. The bottom surface of the gate trench105may be positioned at a higher level than the bottom surface of the isolation layer102. For example, the gate trench105may have a shallower depth than the isolation layer102. The bottom portion of the gate trench105may be flat. According to another embodiment of the present disclosure (not shown), the bottom portion of the gate trench105may have a curvature, According to another embodiment of the present disclosure, the isolation layer102of a direction that the gate trench105extends may be etched to a predetermined depth to form a fin region Fin in the active region103.

A gate dielectric layer106may be formed on the surface of the gate trench105. A gate electrode107filling a portion of the gate trench105may be formed over the gate dielectric layer106. A gate capping layer108filling the remaining portion of the gate trench105may be formed over the gate electrode107. The upper surface of the gate capping layer108may be positioned at the same level as the upper surface of the hard mask layer104. The upper surface of the gate electrode107may be positioned at a lower level than the upper surface of the substrate101. The gate electrode107may be formed of a low resistance metal material, including, for example, titanium nitride and tungsten that are sequentially stacked. According to another embodiment of the present disclosure, the gate electrode107may be formed of titanium nitride only. The gate electrode107may be referred to as a buried word line.

First and second impurity regions109and110may be formed in the substrate101. The first and second impurity regions109and110may be referred to as source/drain regions. The first and second impurity regions109and110may be spaced apart from each other by the gate trench105. The gate electrode107and the first and second impurity regions109and110may be referred to also as a cell transistor. The cell transistor may exhibit an improved short channel effect by the gate electrode107.

A bit line contact plug111may be formed over the first impurity region109of the substrate101. The bit line contact plug111may be coupled, e.g., by direct contact, to the first impurity region109. The bit line contact plug111may be positioned in the bit line contact hole. The bit line contact hole may expose the first impurity region109. The lower surface of the bit line contact plug111may be lower than the upper surface of the substrate101. The bit line contact plug111may be formed, for example, of polysilicon or a metal material. A portion of the bit line contact plug111may have a line width which is smaller than the diameter of the bit line contact hole. Accordingly, gaps G may be formed on both sides of the bit line contact plug111, respectively. The gaps G may be independently formed on both sides of the bit line contact plug111. As a result, one bit line contact plug111and a pair of gaps G may be positioned in the bit line contact hole, and the pair of gaps G may be isolated by the bit line contact plug111. A gap may be positioned between the bit line contact plug111and a contact plug120.

A bit line structure BL may be formed which includes the bit line contact plug111, a bit line112formed over the bit line contact plug111, and a bit line hard mask113formed over the bit line112. The bit line structure BL may have a line shape extending in a direction intersecting with the buried gate structure BG, that is, in the long axis direction of the active region103. A portion of the bit line112may be coupled, e.g., by direct contact, to the bit line contact plug111. From the perspective of a line A-A′ direction, the bit line112and the bit line contact plug111may have the same line width. Accordingly, the bit line112may extend in one direction while covering the bit line contact plug111. The bit line112may include a metal material. The bit line hard mask113may be formed of or include a dielectric material.

A bit line spacer114may be formed on a sidewall of the bit line structure BL. The bottom portion of the bit line spacer114may fill the gaps G on both sides of the bit line contact plug111. The bit line spacer114may be formed of or include a dielectric material. The bit line spacer114may be formed of or include, for example, silicon oxide, silicon nitride, or a combination thereof. The bit line spacer114may include a NON (Nitride-Oxide-Nitride) structure, According to another embodiment of the present disclosure, the bit line spacer114may include an air gap. For example, it may include a NAN (Nitride-Air gap-Nitride) structure.

From the perspective of a direction parallel to the bit line structure BL, the plug isolation layer115may be formed between the neighboring contact plugs120. The plug isolation layer115may be formed between the neighboring bit line structures BL, and may define a rectangular opening116of an island type separated from each other. The opening116may be an opening having a square shape which is defined by the bit line structure BL and the bit line isolation layer115. The upper-to-lower and left-to-right line widths of the opening116may be controlled by the bit line structure and the bit line spacers BL and114.

A recess116R may be formed in a bottom portion of the opening116. The recess116R may extend into the substrate101. The bottom surface of the recess116R may be positioned at a lower level than the upper surface of the substrate101. The bottom surface of the recess116R may have a higher level than the bottom surface of the bit line contact plug111.

A pad117in contact with the second source/drain regions110may be formed in the recess116R. The pad117may fill the recess116R. The pad117may couple the contact plug120and the second impurity region110to each other. The pad117may be formed, for example, by a selective Epitaxial Growth process.

The pad117may be formed, for example, by a Bottom-Up Growth process. The bottom-up growth process may include an epitaxial growth process. The epitaxial growth process may include a selective epitaxial growth process. The pad117may include a silicon-containing epitaxial layer. For example, the pad117may include a silicon epitaxial layer. The pad117may include SEG Si.

The pad117may include a dopant. Accordingly, the pad117may be a doped epitaxial layer. The dopant may include an N-type dopant. The N-type dopant may include phosphorus, arsenic, antimony, or a combination thereof. The pad117may include a silicon epitaxial layer doped with phosphorus formed by a selective epitaxial growth process, that is, heavily doped SEG SiP. Herein, in the low-concentration SEG SiP and the high-concentration SEG SiP, each of the low concentration and the high concentration may refer to the concentration of phosphorus.

According to another embodiment of the present invention, the pad117may include SEG SiGe doped with an N-type dopant or SEG SiC doped with an N-type dopant.

The recesses116R between the pads117may be gap-filled with the spacers118. That is, a spacer118may be formed on a sidewall of the bit line spacer114. The spacer118may be formed of or include a dielectric material. The spacer118may be formed of or include, for example, silicon oxide.

A plug liner119may be formed on a sidewall of the spacer118. The plug liner119may be formed on the upper portion of the pad117. The plug liner119may be formed of or include, for example, polysilicon.

The contact plug120may be formed on an upper portion of the pad117. The contact plug120may be formed between the neighboring bit line structures BL. The contact plug120may be formed in the opening116. The contact plug120may be coupled to the second impurity region110by the pad117. The contact plug120may be or include a conductive material. The contact plug120may be formed of or include, for example, polysilicon or a metal material.

According to an embodiment of the present disclosure, the plug liner119may serve as a contact plug together with the contact plug120. The plug liner119and the contact plug120may be referred to as a ‘storage node contact plug’. For example, the width of the storage node contact plug may be increased as much as the thickness of the plug liner119, thereby securing an overlay margin with the subsequently formed memory element121and reducing a contact resistance.

The memory element121may be formed over the contact plug120. The memory element121may include a capacitor including a storage node. The storage node, for example, may be or include a pillar type storage node. Although not illustrated, a dielectric layer and a plate node may be further formed over the storage node. In an embodiment, the storage node may have a cylinder shape. The storage node may be coupled, e.g., by direct contact, to the contact plug120.

According to another embodiment of the present disclosure, memory elements implemented in various ways over the contact plug120may be coupled to the contact plug120directly or indirectly.

FIGS.3A and3Bare cross-sectional views illustrating another example of the semiconductor device in accordance with an embodiment of the present disclosure.FIGS.3A and3Binclude a semiconductor device having a storage node contact plug SNC having a different structure from that ofFIGS.2A and2B.

Referring toFIGS.3A and3B, the semiconductor device may include a plurality of memory cells, Each memory cell may include a cell transistor including a gate electrode207, a bit line212, and a memory element223.

The gate electrode207and the bit line212may have the same structure as that ofFIGS.2A and2B.

Island-type rectangular openings216isolated by a plug separation layer215which is formed between the neighboring bit line structures BL may be defined. The vertical line width and the lateral line width of each opening216may be controlled by the bit line structure BL and the bit line spacer214.

The recess216R may be formed in a bottom portion of the opening216. The recess216R may extend into the substrate201. The bottom surface of the recess216R may be positioned at a lower level than the upper surface of the substrate201. The bottom surface of the recess216R may be positioned at a higher level than the bottom surface of the bit line contact plug211.

The pad217in contact with the second source/drain region210may be formed in the recess216R. The pad217may fill the recess216R. The pad217may couple the contact plug SNC and the second impurity region210. The pad217may be formed, for example, by a selective epitaxial growth process.

The pad217may be formed, for example, by a bottom-up growth process. The bottom-up growth process may include an epitaxial growth process. The epitaxial growth process may include a selective epitaxial growth process. The pad217may include a silicon-containing epitaxial layer. For example, the pad217may include a silicon epitaxial layer. The pad217may include SEG Si.

The recesses216R remaining between the pads217may be gap-filled with the first spacer218. The first spacer218may be formed on a sidewall of the bit line spacer214. The first spacer218may be formed of or include a dielectric material. The first spacer218may be formed of or include, for example, silicon oxide.

A plug liner219may be formed on a portion of each sidewall of the first spacer218. The plug liner219may be formed on the upper portion of the pad217. The plug liner219may be formed of or include, for example, polysilicon.

A first contact plug220may be formed over the pad217to directly contact an upper portion of the pad217. The first contact plug220may be formed between the neighboring bit line structures BL. The first contact plug220may be coupled to the second impurity region210via the pad217. The first contact plug220may be or include a conductive material. The first contact plug220may be formed of or include, for example, polysilicon or a metal material. The upper surface of the first contact plug220may be positioned at the same level as the upper surface of the plug liner219.

According to an embodiment of the present disclosure, the plug liner219may serve as a contact plug together with the first contact plug220.

A second spacer221may be formed over the plug liner219, The second spacer221may be formed on a portion of each of both sidewalls of the first spacer218. The second spacer221may be formed of or include a dielectric material. The second spacer221may be or include silicon nitride.

A second contact plug222may be formed over the first contact plug220. The second contact plug222may be in direct contact with the first contact plug220. The second contact plug222may include the same material as that of the first contact plug220, A contact plug structure SNC may be defined by the first contact plug220and the second contact plug222, Also, according to an embodiment of the present disclosure, the plug liner219may be included in the contact plug structure SNC. For example, the lower contact of the contact plug structure SNC may be the plug liner219and the first contact plug220, and the upper contact may be the second contact plug222. In this case, the lower contact may have a wider width than the upper contact.

According to another embodiment of the present disclosure, an ohmic contact layer and an interfacial doping layer may be further included between the first contact plug220and the second contact plug222.

A memory element223may be formed over the second contact plug222. The memory element223may be in direct contact with the second contact plug222.

FIGS.4A to4Uare cross-sectional views illustrating a method for fabricating a semiconductor device by presenting a cross section taken along a line A-A′ ofFIG.1.FIGS.5A to5Uare cross-sectional views illustrating a method for fabricating a semiconductor device by presenting a cross section taken along a line B-B′ ofFIG.1.

As illustrated inFIGS.4A and5A, an isolation layer12may be formed in the substrate11. The isolation layer12may define an active region13. The active region13may include a plurality of active regions13. The isolation layer12may be formed, for example, by a Shallow Trench Isolation (STI) process. The STI process may include etching the substrate11to form an isolation trench (not shown). The isolation trench may be filled with a dielectric material, thereby forming an isolation layer12. The isolation layer12may be formed of or include, for example, silicon oxide, silicon nitride, or a combination thereof. A Chemical Vapor Deposition (CVD) process or other deposition processes may be used to fill the isolation trench with a dielectric material. A planarization process such as a Chemical Mechanical Polishing (CMP) process may be additionally used.

Referring toFIGS.4B and5B, a buried gate structure may be formed in the substrate11. The buried gate structure may be referred to as a buried word line structure. The buried gate structure may include a gate trench15, a gate dielectric layer16covering the bottom surface and sidewalls of the gate trench15, a gate electrode17partially filling the gate trench15over the gate dielectric layer16, and a gate capping layer18formed over the gate electrode17.

The method of forming the buried gate structure may be as follows.

First, the gate trench15may be formed in the substrate11. The gate trench15may have a line shape intersecting with the active region13and the isolation layer12. The gate trench15may be formed by forming a mask pattern (not shown) over the substrate11and performing an etching process using the mask pattern as an etching mask. In order to form the gate trench15, the hard mask layer14may be used as an etch barrier. The hard mask layer14may be formed of or include TEOS. The gate trench15may be formed to be shallower than the isolation trench. For example, the bottom surface of the gate trench15may be positioned at a higher level than the bottom surface of the isolation layer12. The gate trench15may have a sufficient depth to increase the average cross-sectional area of the gate electrode17. Accordingly, the resistance of the gate electrode17may be reduced. The bottom edges of the gate trench15be may be straight. According to another embodiment of the present disclosure (not shown), the bottom edges of the gate trench15may have curvature. By forming the bottom edges of the gate trench15to have curvature, irregularities at the bottom portion of the gate trench15may be minimized, and thus, the gate electrode17may be filled more readily.

Although not illustrated, after the gate trench15is formed, a fin region may be formed. The fin region may be formed by recessing a portion of the isolation layer12.

Subsequently, a gate dielectric layer16may be formed on the bottom surface and sidewalls of the gate trench15. Before the gate dielectric layer16is formed, etching damage on the surface of the gate trench15may be cured. For example, in the curing process, a thermal oxidation process for curing the surface of the gate trench15and a process of removing the sacrificial oxide formed on the surface of the gate trench15by the thermal oxidation process may be sequentially performed.

The gate dielectric layer16may be formed, for example, by a thermal oxidation process. For example, the gate dielectric layer16may be formed by oxidizing the bottom and sidewalls of the gate trench15.

According to another embodiment of the present disclosure, the gate dielectric layer16may be formed, for example, by a vapor deposition method such as a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. The gate dielectric layer16may include, for example, a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include, for example, a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present disclosure, the high-k material may include, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, and a combination thereof. As for the high-k material, other known high-k materials may be used selectively.

According to another embodiment of the present disclosure, the gate dielectric layer16may be formed by depositing a liner polysilicon layer and then radically oxidizing the liner polysilicon layer.

According to yet another embodiment of the present disclosure, the gate dielectric layer16may be formed by forming a liner silicon nitride layer and then radically oxidizing the liner silicon nitride layer.

Subsequently, the gate electrode17may be formed over the gate dielectric layer16. To form the gate electrode17, a recessing process may be performed after forming a conductive layer (not shown) to fill the gate trench15. The recessing process may be performed as an etch-back process, or the recessing process may be performed by sequentially performing a CMP process and an etch-back process. The gate electrode17may have a recessed shape that only partially fills the gate trench15. For example, the surface of the upper portion of the low gate electrode17may be positioned at a lower level than the surface of the upper portion of the active region13. The gate electrode17may include, for example, a metal, a metal nitride, or a combination thereof. For example, the gate electrode17may be formed of titanium nitride (TiN), tungsten (W), or titanium nitride/tungsten (TiN/W). The titanium nitride/tungsten (TiN/W) may have a structure in which titanium nitride is conformally formed and then the gate trench15is partially filled with tungsten. As the gate electrode17, titanium nitride may be used alone, and this may be referred to as a gate electrode17having a ‘TiN Only’ structure.

Subsequently, a gate capping layer18may be formed over the gate electrode17. The gate capping layer18may be formed of or include a dielectric material. The remaining portion of the gate trench15over the gate electrode17may be filled with the gate capping layer18. The gate capping layer18may be formed of or include, for example, silicon oxide, According to yet another embodiment of the present disclosure, the gate capping layer18may have a NON (Nitride-Oxide-Nitride) structure. The surface of the upper portion of the gate capping layer18may be positioned at the same level as the surface of the upper portion of the hard mask layer14. To this end, when the gate capping layer18is formed, a Chemical Mechanical Polishing (CMP) process may be performed by setting the upper surface of the hard mask layer14as an etch stop target.

After the buried gate structure is formed as described above, the first impurity region19and the second impurity region20may be formed. The first impurity region19and the second impurity region20may be formed, for example, by a doping process, such as an implantation process. The first impurity region19and the second impurity region20may have the same depth. According to another embodiment of the present disclosure, the first impurity region19may be deeper than the second impurity region20. The first impurity region19and the second impurity region20may be referred to as source/drain regions. The first impurity region19may be a region to which a bit line contact plug is coupled. The second impurity region20may be a region to which the storage node contact plug is coupled.

A cell transistor of a memory cell may be formed by the gate electrode17, the first impurity region19, and the second impurity region20.

Referring toFIGS.4C and5C, a first contact hole21may be formed. The hard mask layer14may be etched by using a contact mask (not shown) to form the first contact hole21. The first contact hole21may have a circular shape or an elliptical shape when viewed from the perspective of a plan view. A portion of the substrate11may be exposed by the first contact hole21. The first contact hole21may have a diameter controlled to a predetermined line width. The first contact hole21may have a shape exposing a portion of the active region13. For example, the first impurity region19may be exposed through the first contact hole21. The first contact hole21may have a diameter which is larger than the width of the short axis of the active region13. Accordingly, in an etching process for forming the first contact hole21, the first impurity region19, the isolation layer12, and a portion of the gate capping layer18may be etched. For example, the gate capping layer18, the first impurity region19, and the isolation layer12below the first contact hole21may be recessed to a predetermined depth. Accordingly, the bottom portion of the first contact hole21may extend into the substrate11. As the first contact hole21extends, the surface of the first impurity region19may be recessed, and the surface of the first impurity region19may be positioned at a lower level than the surface of the active region13. The first contact hole21may be referred to as a ‘bit line contact hole’.

Referring toFIGS.4D and5D, a preliminary plug22A may be formed. The preliminary plug22A may be formed, for example, by a selective Epitaxial Growth (SEG) process. For example, the preliminary plug22A may include SEG SiP. For example, the preliminary plug22A may be formed without voids by the selective epitaxial growth. According to another embodiment of the present disclosure, the preliminary plug22A may be formed by depositing polysilicon and performing a CMP process. The preliminary plug22A may fill the first contact hole21. The surface of the upper portion of the preliminary plug22A may be positioned at the same level as the surface of the upper portion of the hard mask layer14.

Referring toFIGS.4E and5E, a conductive layer23A and a hard mask material layer24A may be stacked. A conductive layer23A and a hard mask material layer24A may be sequentially stacked over the preliminary plug22A and the hard mask layer14. The conductive layer23A may include a metal-containing material. The conductive layer23A may include a metal, a metal nitride, a metal silicide, or a combination thereof. According to an embodiment of the present disclosure, the conductive layer23A may include tungsten (W). According to another embodiment of the present disclosure, the conductive layer23A may include a stack of titanium nitride and tungsten (TiN/W). The titanium nitride may serve as a barrier. The hard mask material layer24A may be formed of a dielectric material having an etch selectivity with respect to the conductive layer23A and the preliminary plug22A. The hard mask material layer24A may be formed of or include, for example, silicon oxide or silicon nitride.

A bit line mask layer25may be formed over the hard mask material layer24A. The bit line mask layer25may be formed of a material having an etch selectivity with respect to the conductive layer23A and the hard mask material layer24A. The bit line mask layer25may include a photoresist pattern. The bit line mask layer25may be formed, for example, by a patterning method, such as SPT (spacer patterning technology) or DPI (double patterning technology). When viewed from the perspective of a plan view, the bit line mask layer25may have a line shape extending in one direction.

As illustrated inFIGS.4F and5F, a bit line23and a bit line contact plug22may be formed. The bit line23and the bit line contact plug22may be formed concurrently using a single etching process. The bit line23and the bit line contact plug22may be formed, for example, by an etching process using the bit line mask layer25(refer toFIG.4E).

The hard mask material layer24A (seeFIG.4E) and the conductive layer23A (seeFIG.4E) may be etched by using the bit line mask layer25as an etch barrier. Accordingly, a bit line structure including the bit line23and the bit line hard mask layer24may be formed. The bit line23may be formed by etching the conductive layer23A. The bit line hard mask layer24may be formed by etching the hard mask material layer24A.

Subsequently, the preliminary plug22A (refer toFIG.4E) may be etched with the same line width as that of the bit line23, As a result, the bit line contact plug22may be formed. The bit line contact plug22may be formed over the first impurity region19. The bit line contact plug22may couple the first impurity region19and the bit line23to each other. The bit line contact plug22may be formed in the first contact hole21. The line width of the bit line contact plug22may be smaller than the diameter of the first contact hole21. As a result, a gap G may be formed around the bit line contact plug22.

As described above, by forming the bit line contact plug22, the gap G may be formed inside the first contact hole21. This is because the bit line contact plug22is formed by being etched smaller than the diameter of the first contact hole21. The gap G may not have a surrounding shape that surrounds the bit line contact plug22but may be formed independently on each of both sidewalls of the bit line contact plug22. Consequently, one bit line contact plug22and a pair of gaps G may be positioned in the first contact hole21, and the pair of gaps G may be isolated by the bit line contact plugs22. The bottom surface of the gaps G may be positioned at the same level as the recessed upper surface of the first impurity region19. According to another embodiment of the present disclosure, the bottom surface of the gaps G may extend into the isolation layer12. For example, the bottom surface of the gaps G may be positioned at a lower level than the recessed upper surface of the first Impurity region19.

Subsequently, the bit line mask layer25(refer toFIG.4E) may be removed.

Referring toFIGS.4G and5G, a bit line spacer26may be formed. The bit line spacer26may be positioned on the sidewalls of the bit line contact plug22and the bit line23. The bit line spacer26may have a line shape extending in parallel to both sidewalk of the bit line23.

The lower end of the bit line spacer26may fill the gap G while covering both sidewalls of the bit line contact plug22. In order to form the bit line spacer26, a bit line spacer material (not shown) may be deposited and an etch-back process may be performed.

The bit line spacer26may be formed of or include, for example, silicon oxide, silicon nitride, or a combination thereof. The bit line spacer26may include a NON (Nitride-Oxide-Nitride) structure. According to another embodiment of the present disclosure, the bit line spacer26may include an air gap. For example, it may include a NAN (Nitride-Air gap-Nitride) structure.

Referring toFIGS.4H and5H, a sacrificial layer27may be formed. The sacrificial layer27may gap-fill the space between the bit line structures BL. The sacrificial layer27may be formed of or include, for example, silicon oxide. The sacrificial layer27may include, for example, a Spin-On-Dielectric material (SOD). The sacrificial layer27may be formed by forming a dielectric material for gap-filling the space between bit line structures and then performing a planarization process. The upper surface of the sacrificial layer27may be positioned at the same level as the upper surface of the bit line structure.

Referring toFIGS.4I and5I, a plug isolation mask layer28may be formed over the sacrificial layer27. The plug isolation mask layer28may be formed of a material having an etch selectivity with respect to the bit line hard mask layer24and the sacrificial layer27. The plug isolation mask layer28may include a photoresist. The plug isolation mask layer28may be formed in a line shape. The plug isolation mask layer28may have a line shape extending in a direction intersecting with the bit line23. For example, the plug isolation mask layer28may have a line shape extending in a direction parallel to the gate electrode17. The plug isolation mask layer28may be formed not to overlap with the gate electrode17. For example, the plug isolation mask layer28may be patterned so that a portion overlapping with the gate electrode17is opened.

Referring toFIGS.4J and5J, the sacrificial layer27may be etched by using the plug isolation mask layer28as an etch barrier. As a result, a plug isolation portion29may be formed.

Referring toFIGS.4K and5K, the plug isolation mask layer28(refer toFIG.4J) may be removed.

Subsequently, a plug isolation layer30may be formed in the plug isolation portion29. In order to form the plug isolation layer30, a dielectric material may be formed to fill the plug isolation portion29, and then a planarization process may be performed. The plug isolation layer30may include a material having an etch selectivity with respect to the sacrificial layer27. For example, the plug separation layer30may be made of or include silicon nitride.

Referring toFIGS.4L and5L, the remaining sacrificial layer27(refer toFIG.4K) may be removed. The remaining sacrificial layer27may be removed, for example, by a wet etching process. The remaining sacrificial layer may be removed, for example, by a dip-out process. The process of removing the remaining sacrificial layer27may be performed under the conditions having an etching selectivity with respect to the plug isolation layer30and the bit line hard mask layer24. Accordingly, only the remaining sacrificial layer27may be selectively removed without loss of other structures.

As the remaining sacrificial layer is removed, openings31may be formed by the plug isolation layer30and the bit line structure BL, The openings31may have a shape of individually separated islands. The openings31may be referred to as storage node contact holes.

As described above, the opening31may be formed by depositing the sacrificial layer27, forming the plug isolation portion29, forming the plug isolation layer30, and removing the sacrificial layer27sequentially. A series of the processes may be referred to as a ‘damascene process’, and the opening31may be formed by the damascene process.

From the perspective of a plan view, the opening31may have a rectangular shape. The size of the opening31may be determined by the bit line spacer26and the plug isolation layer30.

Referring toFIGS.4M and5M, a portion of the plug isolation layer30and a portion of the bit line spacer26may be etched to increase the width of the opening31.

Subsequently, a recess31R may be formed below the opening31. To form the recess31R, the hard mask layer14, the isolation layer12, and the second impurity region20may be etched to a predetermined depth. The recess31R may extend into the substrate11. The bottom surface of the recess31R may be positioned at a lower level than the upper portion surface of the bit line contact plug22. The bottom surface of the recess31R may be positioned at a higher level than the bottom surface of the bit line contact plug22.

Referring toFIGS.4N and5N, a pad32may be formed to fill a portion of the recess31R. The pad32may be formed, for example, by a bottom-up growth process. The pad32may be formed, for example, by a selective epitaxial growth (SEG) process. The pad32may be grown by using the second impurity region20as a seed. The pad32may include a silicon-containing material. The pad32may be an epitaxial layer. The pad32may be, for example, a silicon-containing epitaxial layer. The pad32may include, for example, SEG Si, SEG SiGe or SEG SiC, According to another embodiment of the present disclosure, the pad32may include, for example, SEG Si doped with an N-type dopant, SEG SiGe doped with an N-type dopant, or SEG SiG doped with an N-type dopant. For example, the pad32may include SEG SiP. The pad32may be formed by using a silicon source gas and an additive gas. The silicon source gas may include silane (SiH4), dichlorosilane (SiH2Cl2, DCS), or a mixture thereof. The additive gas may contain HCl.

The upper surface of the pad32may be positioned at a lower level than the upper surface of the bit line contact plug22.

As above, since selective epitaxial growth is performed to form the pad32, the process may be simplified. Also, the inside of the recess31R may be filled with the pad32without voids.

In particular, in this embodiment, the plug isolation layer30may be formed to define openings31of an individually separated island type by a plug isolation layer30and a bit line structure, and by forming the pads32at the bottom portion of the opening31, it is possible to prevent a short caused by a bridge between the storage node contact plugs. That is, since the pad32is formed only inside the island-type opening31, epitaxial growth may be performed regardless of the growth extent of the pad32. Accordingly, it is possible to employ detailed conditions for controlling the growth of the pad32, thereby reducing the process difficulty.

According to an embodiment of the present disclosure, after the pad32is formed, in-situ annealing may be performed in the ambient of hydrogen (H2). Silicon migration may occur due to the in-situ annealing in the ambient of a hydrogen.

For example, the pad32may be formed of SEG Si or SEG SiP. When the pad32is formed of SEG SiP, the contact resistance with the silicon active region may be improved. SEG SiP may be formed by co-flowing PH3gas during the SEG process.

A method of forming the pad32of SEG SiP may be as follows.

SEG SiP may be formed by using a phosphorus-containing gas, a silicon-containing gas, and a chlorine-containing gas. The chlorine-containing gas may include HO. The phosphorus-containing gas and the silicon-containing gas may be referred to as a phosphorus-containing precursor and a silicon-containing precursor, respectively. For example, the phosphorus-containing gas may be or include phosphine (PH3). Also, for example, the silicon-containing gas may include silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2: DCS), or a combination thereof. In the selective epitaxial growth (SEG), it may be difficult to secure a selectivity for a dielectric material. Accordingly, in this embodiment, epitaxial growth may be performed by mixing dichlorosilane (DCS) and silane (SiH4) to secure a selectivity with respect to a dielectric material. Accordingly, the growth rate may be increased as adsorption is accelerated by controlling the Cl functional group on the surface of the epitaxy growth. Accordingly, the window for securing a selectivity by HCl may become larger. When dichlorosilane (SiH2Cl2) and silane (SiH4) are mixed, the doping level of phosphorus in SEG SiP may be increased.

The formation of SEG SiP may include an in-situ doping process. For example, an in-situ doping process may be performed by co-flowing phosphine (PH3), while a silicon epitaxial layer is deposited.

As described above, SEG SiP may be formed at a low temperature of approximately 550° C. to 650° C. by using silane (SiH4), dichlorosilane (DCS), HCl, and phosphine (PH3).

Referring toFIGS.4O and5O, a first spacer layer33A may be formed. The first spacer layer33A may cover the pad32. The first spacer layer33A may cover the bit line spacer26. The first spacer layer33A may fill the remaining portion of the recess31R in which the pad32is formed. The first spacer layer33A may be formed of or include, for example, silicon oxide.

Referring toFIGS.4P and5P, a liner layer34A may be formed over the first spacer layer33A. The liner layer34A may be formed of or include, for example, polysilicon.

Referring toFIGS.4Q and5Q, the liner layer34A and the first spacer layer33A may be etched to expose the pad32.

Accordingly, the first spacer33and the plug liner34may be formed over the bit line spacer26(that is, the sidewall of the bit line spacer26). Namely, a spacer structure in which the bit line spacer26, the first spacer33and the plug liner34are stacked may be formed on the sidewall of the bit line23.

In particular, in the present embodiment, the parasitic capacitance of the bit line may be reduced by forming the first spacer33of an oxide. Also, by forming the plug liner34of silicon, it is possible to prevent the first spacer33from being damaged in the subsequent cleaning process. Moreover, since the plug liner34can serve as a storage node contact plug together with a conductive material filling the opening31in the subsequent process, the width of the storage node contact plug may be expanded.

After the etching process is completed, a cleaning process may be performed. Herein, loss of the first spacer layer33A (refer toFIG.4P) may be prevented by the liner layer34A (seeFIG.4P).

Referring toFIGS.4R and5R, a first plug35filling the lower portion of the opening31may be formed over the pad32. The first plug35may directly contact the pad32. The first plug35may be a silicon-containing material or a metal material. The first plug35may be formed of or include, for example, polysilicon. To form the first plug35, after depositing polysilicon to fill the opening31, a recessing process may be performed. The upper surface of the first plug35and the upper surface of the bit line23may be positioned at the same level. During the recessing process for forming the first plug35, the plug liner34may be recessed together so that it may remain only on the sidewall of the first plug35. For example, the plug liner34may have an upper surface at the same level as the first plug35. The plug liner34may serve as a contact plug together with the first plug35.

Referring toFIGS.45and55, a second spacer36may be formed over the plug liner34, that is, on a sidewall of the first spacer33. The second spacer36may be formed of or include silicon nitride.

Referring toFIGS.4T and5T, a second plug37filling the remaining portion of the opening31may be formed over the first plug35.

The second plug37may be a metal material. The second plug37may be formed of or include tungsten. The second plug37may be a material having a lower resistance than the first plug35. The second plug37may be formed of or include titanium, titanium nitride, tungsten, or a combination thereof. For example, the second plug27may be TiN/W in which tungsten is stacked over titanium nitride.

According to another embodiment of the present disclosure, an ohmic contact layer may be further formed between the first plug35and the second plug37. The ohmic contact layer may include a metal silicide. The ohmic contact layer may include cobalt silicide, titanium silicide, or nickel silicide. Contact resistance may be lowered by the ohmic contact layer.

According to another embodiment of the present disclosure, an interface doping layer may be further formed between the first plug35and the ohmic contact layer. The interface doping layer may be formed by doping an impurity in the upper portion region of the first plug35. The interface doping layer may be doped with phosphorus. The first plug35and the interface doped layer may be doped with the same dopant. The first plug35and the interface doping layer may have different dopant concentrations. The dopant concentration of the interface doping layer may be higher than that of the first plug35. Contact resistance may be lowered by the interface doping layer.

A contact plug SNC may be formed by the first plug35and the second plug37. The contact plug SNC may be referred to as a ‘storage node contact plug’. When the contact plug SNC is formed over the pad32, connection failure between the storage node contact plugs may be minimized.

Referring toFIGS.4U and5U, a memory element38including a capacitor may be formed over the second plug37.

The memory element38may include a capacitor including a storage node. The storage node, for example, may be or include a pillar type. Although not illustrated, a dielectric layer and a plate node may be further formed over the storage node. In an embodiment, the storage node may have a cylinder shape.

According to an embodiment of the present disclosure, the reliability of a semiconductor device may be improved by applying a pad formed by a Selective Epitaxial Growth (SEG) process to the bottom of each of the isolated openings.

While the present invention has been described with respect to the above specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.