Patent ID: 12205942

The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale.

DETAILED DESCRIPTION

The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.

As disclosed herein, an integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type region of one device on a side closest the other device. In some embodiments, such current reduction features add a resistance to the base electrode of a parasitic NPN transistor in the substrate, where the emitter electrode and collector electrode of the parasitic NPN transistor are the two N wells. Also, the integrated circuit includes conductive tie biasing structures where the conductive tie biasing structures are not electrically connected to each other or electrically coupled to each other by another conductive biasing structure. One of the conductive tie biasing structures is located between the two devices. Not electrically connecting the conductive tie biasing structures together or electrically coupling the two tie biasing structures together with a conductive biasing structure also adds to the resistance of the base electrode of the parasitic NPN transistor. During an ESD event, the added resistance in the base electrode reduces the base/emitter current of the parasitic NPN transistor, thereby inhibiting the flow of current between the two wells through the parasitic NPN transistor.

FIG.1is a partial top view of a prior art integrated circuit100. The view ofFIG.1shows two devices103and105located in a semiconductor substrate101with a P well102. Device103may be an N well of PNP transistor. Device105is a PNP transistor that is utilized for discharging current from an Electrostatic Discharge (ESD) event involving pad123. In one example, an ESD event may occur from a sudden flow of current between two electrically charged objects cause by their unintentional contact (e.g. an electrical short) or from a dielectric breakdown. However, an ESD event may be cause by other factors. For example, an ESD event may be caused by a human (a charged object) touching one pad (e.g.123) and the other pad (e.g.121) being grounded.

Device103includes an N well109located in substrate101. N well109is biased from a pad121located above the substrate101that is electrically connected (via an interconnect) to a conductive biasing structure114located on a N+ contact region116for biasing well109. A P+ contact region113in substate101surrounds N well109and is biased by ground pad125that is located over substrate101and connected to conductive biasing structure117, which is connected to P+ contact region113. The portion of P well102in proximity to P+ contact region113serves as an anode for a parasitic diode of device103and N well109serves as the cathode.

Device105is a PNP transistor for discharging ESD current from pad123during an ESD event. N well111forms the base of the PNP transistor and is biased by pad123which is connected to conductive biasing structure127, which is connected to N+ contact region126in substrate101. N well111is spaced apart from N well109by a spacing153. The emitter of the PNP transistor of device105is formed by P+ emitter finger regions (131) in substrate101that are biased by pad123through a conductive biasing structure (133) located on the P+ emitter figure region (131). The collector of the PNP transistor of device105is formed by P+ collector finger regions (143) in substrate101that are biased by pad125through a conductive biasing structure (141) located on the P+ collector region (143). An isolation P+ region115in substrate101surrounds N well111and is bias by ground pad125through conductive biasing structure119located on region115.

Referring toFIG.2, N well109, N well111, and P well102form a parasitic NPN transistor205where N well111is the collector, P well102is the base, and N well109is the emitter. The strength of the parasitic transistor205is dependent upon the distance of spacing153, along with other factors. Depending upon the spacing and voltages involved, the activation of parasitic transistor205during an ESD event may lead to substrate damage (e.g. filament formation).

During an ESD event between pads123and121where pad123is at a higher voltage than pad121, the PNP transistor of device105begins to conduct to discharge the charge on pad123. During such an ESD event, the conduction of the transistor of device105pulls the voltage of P well102above the voltage of pad121(e.g. by 1 volt or more in some examples). The voltage of P well102rising above the voltage of pad121causes parasitic transistor205to conduct current from pad123through P+ emitter finger regions (126), N well111, P well102, and N well109, to pad121.

The conduction of ESD current through parasitic transistor205pulls the voltage of N well111lower which causes parasitic PNP transistor207to conduct. The emitter of parasitic transistor207is the P+ emitter regions (131) of device105, the base is N well111, and the collector is P well102. Parasitic transistor207conducting may cause potentially damaging current to conduct from P+ emitter regions (131) of device105to P well102. Furthermore, because transistors205and207are in a thyristor configuration, current flowing through parasitic transistor207increases the voltage of P well102, which increases the conductivity of ESD current through transistor205, which further increases the current through parasitic transistor207in a positive feedback manner. Under certain high voltage conditions of an ESD event, the current through both parasitic transistors205and207can permanently damage the semiconductor devices as well as substate101.

Accordingly, in order to inhibit parasitic transistor205from conducting, embodiments of the present invention include conductivity reduction features to increase the resistance in a current path to the base electrode of transistor205to reduce the current flow from N well111to N well109and from P+ emitter regions (131) of device105to P well102during an ESD event.

FIG.3is a partial top view of an integrated circuit300. The view ofFIG.3shows two devices303and305located in substrate301of integrated circuit300. Device303is a PNP transistor and device305is a PNP transistor that is utilized for discharging current from an Electrostatic Discharge (ESD) event involving pad304. In other embodiments,303and305may be other types of devices such as e.g. diodes, poly capacitors, or PFETs. In one embodiment, device303is also an ESD device used for discharging ESD current. In other embodiments, device303may be utilized for other circuit functions.

In one embodiment, substrate301is made of a semiconductor material (e.g. silicon, silicon germanium, gallium nitride) and may include other devices (not shown) located outside the view ofFIG.3. In one embodiment, a P well302is formed by the selective ion implantation of P type dopants (e.g. Boron) into substrate301during wafer processing. In other embodiments, P well302may be in-situ doped during and epitaxial growth. In some embodiments, devices303and305may be designed to safely operate at voltages above 15V, depending upon the design of integrated circuit300.

Device303includes an N well307located in substrate301. In one embodiment, N well307is formed by the selective ion implantation of N-type dopants (phosphorous, arsenic) in substrate301such that well307has a net N type dopant concentration at a desired level. N well307is biased from a pad308which is located above the substrate301and above one or more interconnect layers (not shown) also located above substrate301. Pad308is electrically connected (via a conductive interconnect329) to a conductive biasing structure311located on a N+ contact region309for biasing well307. The conductive interconnects329are represented by a solid line inFIG.3and are located in the one or more interconnect layers (not shown) located above substrate301. N well307serves as the base region for the PNP transistor of device303.

The emitter of the PNP transistor of device303is implemented with P+ emitter finger regions (317) in substrate301that are biased by pad308through interconnects329and a conductive structure (319) located on the P+ emitter finger region (317). The collector of the PNP transistor of device303is formed by P+ collector finger regions (318) in substrate301that are biased by ground pad306through interconnects327and a conductive biasing structure (320) located on the P+ collector region (318).

Device305is a PNP transistor for discharging ESD current from pad304during an ESD event. N well337forms the base of the PNP transistor and is biased by pad304, which is connected through interconnect354to conductive biasing structure341, which is connected to N+ contact region339in substrate301.

The emitter of the PNP transistor of device305is implemented with P+ emitter finger regions (345) in substrate301that are biased by pad304through interconnects354and a conductive biasing structure (319) located on the P+ emitter finger region (345). The collector of the PNP transistor of device305is formed by P+ collector finger regions (351) in substrate301that are biased by ground pad306through interconnects327and a conductive biasing structure (353) located on the P+ collector region (351).

In one embodiment, the conductive biasing structures315,320,319,311,353,343, and341are formed on the semiconductor substrate and are in ohmic contact with the underlying semiconductor regions. In some embodiments, the conductive biasing structures are made of one or more metal layers (e.g. copper, aluminum, tungsten) formed on the substrate. The biasing structures may include barrier layers (e.g. titanium nitride, titanium tungsten). Also, the top surface of the semiconductor region beneath the conductive biasing structures may silicided for better electrical contact with the conductive biasing structure. In other embodiments, the conductive biasing structures may be made of other conductive materials such as doped poly silicon.

Conductive Biasing structures are used to effectively bias a semiconductor region from a pad (or other type of integrated circuit terminal such as a bump) by providing a low current path from the pad to the region. The conductive biasing structures are also utilized to provide a low resistance current path between different parts of a same semiconductor region for voltage equalization and current flow.

In order to prevent the activation of a parasitic NPN transistor between N wells307and337(similar to parasitic transistor205ofFIG.2), integrated circuit300includes conductivity reduction features for reducing the conductivity between semiconductor regions and external terminals and between different semiconductor regions in substrate. The embodiment ofFIG.3includes two types of conductivity reduction features that increase the resistance to the base electrode of the parasitic NPN transistor.

Device303includes a P+ isolation region313and a conductive biasing structure315located on top of region313for providing electrical isolation of device303. The combination of region313and conductive biasing structure315is located on three sides of device305(the top, bottom, and left sides relative to the view ofFIG.3). Accordingly, the biasing from pad306to region313is relatively uniform and there is a relatively low resistance path to all parts of region313on three sides of device303.

As a result of the inclusion of isolation region313and conductive structure315, a relatively strong parasitic diode366is formed between P well302and N well307around the three sides of device303(as shown by the diode symbols366inFIG.3).

On the right side (relative to the view shown inFIG.3) of device303at locations corresponding to the location of region313on the left side of device303, two conductivity reduction features inhibit the conductivity of current paths from that location to pad306and to the other locations of region313.

One type of conductivity reduction feature shown are the lower net conductivity doping gaps (both gap323and323) between P+ isolation region313and a similar P+ isolation region321located on the right side of device303(relative to the view shown inFIG.3). In one embodiment, region321is formed during the same selective ion implantation process as region313. The net P-type dopant concentration of gaps323and325is that of P well302, which is lower (e.g. 10-100 times lower) than the net P-type dopant concentration of regions313and321. Gaps323and325increase the resistance of the current paths from region321to region313and to pad306. In some embodiments, gaps323and325may be formed by an additional N type doping implant into the gap region to lower the net P type doping concentration.

Another type of conductivity reduction feature shown inFIG.3is a lack of a conductive biasing structure over region321. With no conductive biasing structure located over region321, region321is not biased directly by pad306nor is there a conductive biasing structure path from region313to region321. According, the conduction path from pad306or from region313is through relatively lower dopant concentration gaps323and325.

In the embodiment shown, device305includes the same conductivity reduction features as device303. Gaps349and347separate similarly doped P+ isolation regions333and352. In addition, region352, which is closer to device303than region333does not include a conductive biasing structure. However, in other embodiments, device305would not include some or all of the conductivity reduction features.

FIG.4is a circuit diagram of the devices ofFIG.3showing how the implementation of conductivity reduction features affects the circuit during an ESD event. InFIG.4, the parasitic NPN transistor408represents the NPN transistor where N well337is the collector, P well302is the base, and N well307is the emitter during an ESD event. Not shown inFIG.4is the PNP transistor of device303.

During an ESD event at pad304in which pad304is at a higher voltage than pad308, the activation of ESD transistor device305pulls up the voltage of P well302(which is biased by ground pad306). However, because of the conductivity reduction features shown inFIG.3which are represented as resistance R inFIG.4, the base emitter current of transistor408is significantly reduced due to the to higher resistance to the base electrode. Accordingly, most of the current from the higher voltage P well302and pad306to the lower voltage pad308flows through the parasitic diode366of device303. Because little to no current flows through the base emitter path of NPN parasitic transistor408, transistor408is not activated or only slightly activated. Because parasitic transistor408is relatively non active due to the conductivity reduction features, a parasitic PNP transistor of device305(not shown inFIG.4but similar to parasitic PNP transistor207inFIG.2) also remains relatively inactive. Accordingly, because device303implements the conductivity reduction features, the destructive current described earlier with respect to the thyristor of parasitic transistors205and207ofFIG.2is significantly reduced.

FIG.5is a partial top view of an integrated circuit500according to another embodiment of the present invention. The items ofFIG.5and the items ofFIG.3having the same reference numbers are similar.

Integrated circuit500includes two types of conductivity reduction features. One type of conductivity reduction feature is to provide a lower net P type doping concentration on the side closest to the other device. Location503is a location in substrate301on the right side of device303, relative to the view shown inFIG.5, that corresponds to the portion of region313on the left side of device305. Location503has a lower net P type doping concentration than region313due to location503not receiving the P+ doping implantation that formed region313. Likewise, location505has a lower net P type doping profile than region333of device305. The lower net P type doping concentration on the sides adjacent to the other device increases the resistance to the base of the parasitic NPN transistor (see transistor408ofFIG.4).

The other conductivity reduction feature type shown inFIG.5is that no conductive biasing structure is located over locations503and505.

FIG.6is a partial top view of an integrated circuit600according to another embodiment of the present invention. The items ofFIG.6and the items ofFIG.3having the same reference numbers are similar.

Similar to integrated circuit300ofFIG.3, integrated circuit600includes conductivity reducing gaps323,325,345, and347.

In addition, integrated circuit600includes resistors601and607that couple conductive biasing structure315to conductive biasing structure613. Conductive biasing structure613is located on P+ isolation region321. In one embodiment, resistors601and607are poly silicon resistors located over substrate101outside of the area of device303. In one embodiment, resistors601and607are in the range of 10-200 ohms and may be provided with a poly strip having a width in the range of 5-10 um. In other embodiments, resistors601and603are regions of substrate101doped to provide a specific resistance. Device305includes resistors603and609for providing resistance for the coupling of conductive biasing structure335to conductive biasing structure611, which is located on and is in ohmic contact with P+ isolation region352.

In some embodiments, using resistors to provide resistance in the conductive path between conductive biasing structures may provide for precisely defined resistances in the path to the base of the parasitic NPN transistor (408).

Utilizing conductivity reduction features for reducing the conductivity to a P type region of one device including an N well biased by one pad that is adjacent to another device including an N well biased by a second pad may provide for a mechanism to reduce harmful substrate currents during an ESD event. Such features may provide resistance to the base of a parasitic NPN transistor that includes the two N well regions thereby inhibiting the activation of the parasitic transistor during an ESD event and thereby inhibiting the activation of a parasitic thyristor in the substrate during the ESD event that may cause substrate damaging current. Accordingly, such features may allow for the closer placement of devices having N wells in a substrate without incurring the risk of damage during an ESD event, especially for higher voltage devices (e.g. greater than 15 volts).

Other integrated circuits may have other structures and/or configurations in other embodiments. For example, although the ESD device305is a PNP transistor, other types of ESD devices (e.g. diodes) with N wells may be implemented for ESD protection. Furthermore, PNP transistors having other configurations may be used. Also, in some embodiments, a device may only include one type of conductivity reduction feature (e.g. no conductive biasing structure over the region on the side of the device closest to the other device, or only resistors). Also, in some embodiments, an N type region may be located between the two devices (e.g.303and305) at the surface of the substrate. Furthermore, in some embodiments, the ESD device305does not include any conductivity reduction features.

As an example,FIG.7is a partial top view of an integrated circuit700according to another embodiment of the present invention. The items ofFIG.7and the items ofFIG.3having the same reference numbers are similar.

In the embodiment ofFIG.7, P+ isolation region313surrounds N well307including in the area between devices303and305. P+ isolation region333surrounds N well337including in the area between devices303and305. The conductivity reduction feature in the embodiment ofFIG.7is that conductive biasing structure315is absent over the portion of P+ isolation region313on a side that is laterally closest to device305. Also, conductive biasing structure335is absent is over the portion of P+ isolation region333on a side that is laterally closest to device303. Integrated circuit700includes P type regions750and758and N type regions752and756located between devices303and305. Integrated circuit700includes conductive tie biasing structures768and754which partially surround device303.

FIG.8shows a partial cutaway side view of integrated circuit700. As shown in the view ofFIG.8, conductive tie biasing structure768is in electrical contact with P+ regions821and827, N well region823, and N+ contact region825to form minority collector structure800. Regions821,823,825, and827extend under those portions of structure768in the view ofFIG.7. Conductive tie biasing structure754is in electrical contact with P+ regions803and811, N well region815, and N+ type contact region805to form minority collector structure800. Regions803,805,815, and811extend under those portions of structure754in the view ofFIG.7.

During operation, minority charge carriers (e.g. electrons) in P well302are collected by N well regions823and815. For each collected electron in the N well region, a hole is taken from an adjacent P+ region (P+ regions821and827for N well region823and P+ regions803and811for N well region815) to keep the N well region charge neutral. In this way, the minority carrier collector structures800and801“convert” electron current into hole current. By collecting in N well regions823and815, the electrons do not pass through to other semiconductor devices (e.g.305) adjacent to device303so as to not interfere with those devices during operation.

As shown inFIG.8, during an ESD event, a second parasitic bipolar transistor816forms in substrate301wherein N well region815is the emitter P well302is the base, and N well307is the collector. The current through parasitic transistor816reduces the current through parasitic transistor813.

Referring back toFIG.7, conductive tie biasing structures768and754are separated by a gap764. In addition, tie biasing structures768and754are not biased by any other conductive biasing structure of integrated circuit700or coupled together by another other conductive biasing structures. The regions of substrate701beneath tie biasing structure768(regions821,823,825, and827) are not contiguous with the regions of substrate701below tie biasing structure754(regions803,805,815, and811). In some embodiments, the fact that conductive tie biasing structure754is not connected or electrically coupled with other conductive biasing structures to tie biasing structure768may provide for a greater resistance in the base of a parasitic transistor e.g.813during an ESD event in that there is no conductive biasing structure path to tie basing structure768from tie biasing structure754. If conductive tie structures754and768were contiguous or coupled by another conducive biasing structure, then charge from an ESD event may flow from structure754to structure768, and then through P well302to region313at locations in which tie biasing structure768and biasing structure315are in close proximality (e.g. the top and left sides of device303relative to the view ofFIG.7). Accordingly, a lack of electrical coupling between tie biasing structures768and754reduces the current path form an area of P well302between devices303and305to ground pad306to raise the resistance of the base or a parasitic transistor (e.g.813) in substrate301. In some embodiments, tie biasing structure768(and collector structure800) may surround a greater or lessor portion of device303. For example, in one embodiment, structure768may only reside on the top side of device303relative to the view ofFIG.7. In other embodiments, tie biasing structure768may reside on the top, left, and bottom sides of device303, relative to the view shown inFIG.7, depending on the location of other devices on integrated circuit700. The embodimentsFIGS.3,4, and6may also include carrier collective structures similar to structures800and801as well.

As used herein, a P type region is a semiconductor region that has a net P type doping concentration such as P well302and P+ isolation region313. An N type region is a semiconductor region that has a net N type doping concentration such as N well307and N+ contact region309. The plus sign (+) after the P or N in the detailed description indicates that the region as a higher net concentration than a region without the “+” designation.

As disclosed herein, a first structure is “directly over” a second structure if the first structure is located over the second structure in a line having a direction that is perpendicular with the generally planar major side of the substrate. For example, inFIG.2, structure114is directly over region116. Structure114is not directly over region126. As disclosed herein, a first structure is “directly beneath” a second structure if the first structure is located beneath the second structure in a line having a direction that is perpendicular with the generally planar major side of the substrate. For example, inFIG.2, region116is directly beneath structure114. Region116is not directly beneath structure119. One structure is “directly between” two other structures in a line if the two structures are located on opposite sides of the one structure in the line. For example, inFIG.2, structure127is located directly between structures119and117in a line in the cut away side view ofFIG.2. Well109is not located directly between structure117and structure119in a line. A first structure is “directly lateral” to a second structure if the first structure and second structure are located in a line having a direction that is parallel with a generally planar major side of the substrate. For example, wells109and111are directly lateral to each other. Well109is not directly lateral to structure117. One structure is “directly laterally between” two other structures if the two structures are located on opposite sides of the one structure in a line that is parallel with a generally planar major side of the substrate. For example, inFIG.2, structure127is located directly laterally between structures117and119.

Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

In one embodiment, an integrated circuit includes a first semiconductor device including a first N type well located in a substrate and includes a first P type region located in the substrate and located at least on a first lateral side of the first N type well and at least partially surrounding the first N type well. The integrated circuit includes a second semiconductor device that is characterized as an ESD device. The second semiconductor device includes a second N type well located in the substrate spaced apart from the first N type well. The substrate includes a first area on a second lateral side of the first N type well opposite to the first lateral side and located in a corresponding area to the first P type region on the first lateral side of the first N type well. The second lateral side of first N type well is a closest lateral side to the second N type well. The integrated circuit includes a conductivity reduction feature that provides a greater resistivity in at least a portion of a current path from a first integrated circuit terminal to the first area than in a current path from the first integrated circuit terminal to the first P type region located on the first lateral side of the first N type well. The integrated circuit includes a first conductive tie biasing structure located directly over an N type region of the substrate and directly over a P type region of the substrate at a second area of the substrate that is located directly laterally between the first area and the second N type well. The first conductive tie biasing structure electrically connects the N type region and the P type region of which it is located directly over. The integrated circuit includes a second conductive tie biasing structure located directly over an N type region of the substrate and directly over an P type region of the substrate at a third area of the substrate. The first P type region is located directly laterally between the third area and the first N type well. The second conductive tie biasing structure electrically connects the N type region and the P type region of which it is located directly over. The first conductive tie biasing structure and the second conductive tie biasing structure are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

In one embodiment, an integrated circuit includes a first semiconductor device including a first N type well located in a substrate, a first P type region located in the substrate, and a first conductive biasing structure located directly above the first P type region and electrically connected to the first P type region. The first P type region and the first conductive biasing structure located at least on a first lateral side of the first N type well and at least partially surrounding the first N type well to provide a first conductivity level on the first lateral side of the first N type well. The integrated circuit includes a second semiconductor device that is characterized as an ESD device. The second semiconductor device including a second N type well located in the substrate spaced apart from the first N type well. The substrate includes a first area on a second lateral side of the first N type well opposite to the first lateral side and located in a corresponding area to the first P type region on the first lateral side of the first N type well. The second lateral side of first N type well is a closest lateral side to the second N type well. The first semiconductor device includes a conductivity reduction feature for reducing the conductivity from the first conductivity level in a conductive path from the first P type region on the first lateral side of the first N type well to the first area. The integrated circuit includes a first conductive tie biasing structure located directly over an N type region of the substrate and directly over a P type region of the substrate at a second area of the substrate that is located directly laterally between the first area and the second N type well. The first conductive tie biasing structure electrically connects the N type region and the P type region of which it is located directly over. The integrated circuit includes a second conductive tie biasing structure located directly over an N type region of the substrate and directly over an P type region of the substrate at a third area of the substrate. The first P type region is located directly laterally between the third area and the first N type well. The second conductive tie biasing structure electrically connects the N type region and the P type region of which it is located directly over. The first conductive tie biasing structure and the second conductive tie biasing structure are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure. The first conductive tie biasing structure and the second conductive tie biasing structure are characterized as partially surrounding the first semiconductor device with at least one gap where the first conductive tie biasing structure does not contact the second conductive tie biasing structure.

While particular embodiments of the present invention have been shown and described, it will be recognized to those skilled in the art that, based upon the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and thus, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention.