Patent ID: 12191237

MODE FOR CARRYING OUT THE INVENTION

The following describes preferred embodiments of a semiconductor module according to the present disclosure with reference to the drawings. In the following, the same or similar elements are provided with the same reference signs, and redundant descriptions are omitted.

FIGS.1to20illustrate a semiconductor module A1according to a first embodiment. The semiconductor module A1includes a plurality of semiconductor elements10, a conductive substrate2, a supporting substrate3, a plurality of input terminals41to43, a plurality of output terminals44, a plurality of control terminals45, a control terminal support5, a conducting member6, a first conductive bonding member71, a second conductive bonding member72, a plurality of wires731to735, a sealing resin8, resin members87, and resin-filling portions88.

FIG.1is a perspective view illustrating the semiconductor module A1.FIG.2is a perspective view corresponding toFIG.1but omitting the sealing resin8, the resin members87, and the resin-filling portions88.FIG.3is a perspective view corresponding toFIG.2but omitting the conducting member6.FIG.4is a plan view illustrating the semiconductor module A1.FIG.5is a plan view corresponding toFIG.4but showing the sealing resin8, the resin members87, and the resin-filling portions88with imaginary lines.FIG.6is a partially enlarged view showing a part ofFIG.5. InFIG.6, the imaginary lines of the sealing resin8, the resin members87, and the resin-filling portions88are omitted.FIG.7is a partially enlarged view showing a part ofFIG.6.FIG.8is a plan view corresponding toFIG.5but showing a part of the conducting member6(a second conducting member62described below) with an imaginary line.FIG.9is a front view illustrating the semiconductor module A1.FIG.10is a bottom view illustrating the semiconductor module A1.FIG.11is a left side view illustrating the semiconductor module A1.FIG.12is a right side view illustrating the semiconductor module A1.FIG.13is a cross-sectional view taken along line XIII-XIII ofFIG.5.FIG.14is a cross-sectional view taken along line XIV-XIV ofFIG.5.FIG.15is a partially enlarged view showing a part ofFIG.14.FIG.16is a cross-sectional view taken along line XVI-XVI ofFIG.5.FIG.17is a cross-sectional view taken along line XVII-XVII ofFIG.5.FIG.18is a cross-sectional view taken along line XVIII-XVIII ofFIG.5.FIG.19is a cross-sectional view taken along line XIX-XIX ofFIG.5. InFIGS.2,3,7,14, and18, the wires731to735are omitted.FIG.20shows an example of the circuit configuration of the semiconductor module A1. In the circuit diagram ofFIG.20, only one of a plurality of first semiconductor elements10A (described below) and only one of a plurality of second semiconductor elements10B (described below) are illustrated, and the rest of the first semiconductor elements10A and the second semiconductor elements10B are omitted.

For convenience, reference is made to three mutually perpendicular directions, i.e., x direction, y direction, and z direction. The z direction corresponds to the thickness direction of the semiconductor module A1. The x direction corresponds to the horizontal direction in the plan view (seeFIG.4) of the semiconductor module A1. The y direction corresponds to the vertical direction in the plan view (seeFIG.4) of the semiconductor module A1. One sense of the x direction is defined as x1 direction, and the other sense as x2 direction. Similarly, one sense of the y direction is defined as y1 direction, and the other sense as y2 direction. One sense of the z direction is defined as z1 direction, and the other sense as z2 direction. In the following description, a “plan view” is a view seen in the z direction. The z1 direction may be referred to as “downward”, and the z2 direction may be referred to as “upward”. The z direction is an example of the “thickness direction”, the x direction is an example of a “first direction”, and the y direction is an example of a “second direction”. In the following description, the mutually opposite senses in one direction are referred to as “one sense” and “the other sense”, respectively, but the present disclosure is not limited thereto. Specifically, the x2 direction is referred to as “one sense of the first direction”, and the x1 direction is referred to as “the other sense of the first direction”. Similarly, the y2 direction is referred to as “one sense of the second direction”, and the y1 direction is referred to as “the other sense of the second direction”. Furthermore, the z2 direction is referred to as “one sense of the thickness direction” and the z1 direction is referred to as “the other sense of the thickness direction”.

The semiconductor elements10form the functional core of the semiconductor module A1. The semiconductor elements10are made of a semiconductor material that mainly contains silicon carbide (SiC), for example. The semiconductor material is not limited to SiC, and may be silicon (Si), gallium arsenide (GaAs) or gallium nitride (GaN). Each of the semiconductor elements10has a switching function unit Q1(seeFIG.20) composed of a metal-oxide-semiconductor field-effect transistor (MOSFET), for example. The switching function unit Q1is not limited to a MOSFET, and may be another transistor, which is, for example, a field-effect transistor such as a metal-insulator-semiconductor FET or a bipolar transistor such as an IGBT. The semiconductor elements10are the same elements. The semiconductor elements10are n-channel MOSFETs, for example, but may be p-channel MOSFETs instead.

As shown inFIG.15, each of the semiconductor elements10has an element obverse surface101and an element reverse surface102. The element obverse surface101and the element reverse surface102of each semiconductor element10are spaced apart from each other in the z direction. The element obverse surface101faces in the z2 direction, and the element reverse surface102faces in the z1 direction.

The semiconductor elements10include a plurality of first semiconductor elements10A and a plurality of second semiconductor elements10B. In the present embodiment, the semiconductor module A1includes three first semiconductor elements10A and three second semiconductor elements10B. However, the number of first semiconductor elements10A and the number of second semiconductor elements10B are not limited thereto, and may be changed as appropriate according to the performance required for the semiconductor module A1. In the example shown inFIG.8, three first semiconductor elements10A and three second semiconductor elements10B are provided. The number of first semiconductor elements10A and the number of second semiconductor elements10B may each be one, two, or no less than four. The number of first semiconductor elements10A and the number of second semiconductor elements10B may be equal or different. The number of first semiconductor elements10A and the number of second semiconductor elements10B are determined according to the current capacity handled by the semiconductor module A1.

As shown inFIG.20, the semiconductor module A1may be configured as a half-bridge switching circuit. In this case, the first semiconductor elements10A constitute an upper arm circuit of the semiconductor module A1, and the second semiconductor elements10B constitute a lower arm circuit of the semiconductor module A1. In the upper arm circuit, the first semiconductor elements10A are connected in parallel to each other, and in the lower arm circuit, the second semiconductor elements10B are connected in parallel to each other. Each of the first semiconductor elements10A and each of the second semiconductor elements10B are connected in series to form a bridge layer.

As shown inFIGS.8and16, for example, the first semiconductor elements10A are mounted on the conductive substrate2. In the example shown inFIG.8, the first semiconductor elements10A are aligned in the y direction and spaced apart from each other. The first semiconductor elements10A are electrically bonded to the conductive substrate2(a first conductive portion2A described below) via the second conductive bonding member72. When the first semiconductor elements10A are bonded to the first conductive portion2A, the element reverse surfaces102face the first conductive portion2A.

As shown inFIGS.8and17, for example, the second semiconductor elements10B are mounted on the conductive substrate2. In the example shown inFIG.8, the second semiconductor elements10B are aligned in the y direction and spaced apart from each other. The second semiconductor elements10B are electrically bonded to the conductive substrate2(a second conductive portion2B described below) via the second conductive bonding member72. When the second semiconductor elements10B are bonded to the second conductive portion2B, the element reverse surfaces102face the second conductive portion2B. As is evident fromFIG.8, the first semiconductor elements10A and the second semiconductor elements10B overlap with each other as viewed in the x direction, but they may not necessarily overlap with each other.

Each of the semiconductor elements10(the first semiconductor elements10A and the second semiconductor elements10B) has a first obverse-surface electrode11, a second obverse-surface electrode12, and a reverse-surface electrode15. The configurations of the first obverse-surface electrode11, the second obverse-surface electrode12, and the reverse-surface electrode15, which are described below, are common to each of the semiconductor elements10. The first obverse-surface electrode11and the second obverse-surface electrode12are mounted on the element obverse surface101. The first obverse-surface electrode11and the second obverse-surface electrode12are insulated from each other by an insulating film (not illustrated). The reverse-surface electrode15is provided on the element reverse surface102.

The first obverse-surface electrode11is a gate electrode, for example, to which a drive signal (e.g., gate voltage) for driving the semiconductor element10is inputted. In the semiconductor element10, the second obverse-surface electrode12is a source electrode, for example, through which a source current flows. The reverse-surface electrode15is a drain electrode, for example, through which a drain current flows. The reverse-surface electrode15almost entirely covers the element reverse surface102. The reverse-surface electrode15may be formed by Ag plating.

Each of the semiconductor elements10switches between a connected state and a disconnected state according to a drive signal (gate voltage), which is input to the first obverse-surface electrode11(gate electrode) via the switching function unit Q1. The operation of switching between the connected state and the disconnected state is referred to as a switching operation. In the connected state, a current flows from the reverse-surface electrode15(drain electrode) to the second obverse-surface electrode12(source electrode). In the disconnected state, the current does not flow. In other words, each of the semiconductor elements10performs a switching operation through the switching function unit Q1. The semiconductor module A1converts a first power supply voltage (DC voltage) inputted between the input terminal41and the two input terminals42,43to a second power supply voltage (AC voltage) by the switching function units Q1of the semiconductor elements10, for example, and outputs the second power supply voltage from the output terminals44. The input terminals41to43and the output terminals44are power supply terminals that handle power supply voltage. The input terminals41to43are first power supply terminals that receive the first source voltage. The output terminals44are second power supply terminals that output the second source voltage.

Some (two in the example shown inFIG.8) of the semiconductor elements10each have a diode function unit D1(seeFIG.20) in addition to the switching function unit Q1. In the semiconductor module A1, one of the first semiconductor elements10A (i.e., the first semiconductor element10A offset furthest in the y2 direction inFIG.8) and one of the second semiconductor elements10B (i.e., the second semiconductor element10B offset furthest in the y1 direction inFIG.8) each include a diode function unit D1in addition to the switching function unit Q1. The function and role of the diode function unit D1is not particularly limited but one example of the diode function unit D1is a temperature detection diode. Note that the diode D2inFIG.20is, for example, a parasitic diode component of the switching function unit Q1.

As shown inFIG.8, each of the semiconductor elements10having the diode function units D1has a third obverse-surface electrode13, a fourth obverse-surface electrode14, and a fifth obverse-surface electrode16, in addition to the first obverse-surface electrode11, the second obverse-surface electrode12, and the reverse-surface electrode15. The configurations of the third obverse-surface electrode13, the fourth obverse-surface electrode14, and the fifth obverse-surface electrode16, which are described below, are common to each of the semiconductor elements10having the diode function units D1. The third obverse-surface electrode13, the fourth obverse-surface electrode14, and the fifth obverse-surface electrode16are formed on the element obverse surface101. In each of the semiconductor elements10having the diode function units D1, the third obverse-surface electrode13and the fourth obverse-surface electrode14are electrically connected to the diode function unit D1. The fifth obverse-surface electrode16is a source sense electrode, for example, through which a source current in the switching function unit Q1flows.

As shown inFIG.7, each of the first semiconductor elements10A has a first side191, a second side192, a third side193, and a fourth side194in plan view.FIG.7illustrates the first semiconductor element10A arranged in the middle in the y direction among the first semiconductor elements10A aligned in the y direction, but each of the other first semiconductor elements10A also similarly has a first side191, a second side192, a third side193, and a fourth side194. The first side191and the second side192extend in the y direction. The first side191is an edge located in the x2 direction in plan view, and the second side192is an edge located in the x1 direction in plan view. The third side193and the fourth side194extend in the x direction. The third side193is an edge located in the y2 direction in plan view, and the fourth side194is an edge located in the y1 direction in plan view. Since each of the first semiconductor elements10A has a rectangular shape in plan view, the four corners formed by the first side191, the second side192, the third side193, and the fourth side194are generally right-angled in plan view. As shown inFIG.7, the four corners do not overlap with the conducting member6(first conducting members61and a second conducting member62described below) in plan view. The third side193and the fourth side194are longer than the first side191and the second side192.

The conductive substrate2is also referred to as a lead frame. The conductive substrate2supports the semiconductor elements10. The conductive substrate2is bonded to the supporting substrate3via the first conductive bonding member71. The conductive substrate2has a rectangular shape in plan view, for example. The conductive substrate2, together with the conducting member6, forms the path of a main circuit current switched by the semiconductor elements10.

The conductive substrate2includes a first conductive portion2A and a second conductive portion2B. The first conductive portion2A and the second conductive portion2B are plate-like members made of metal. The metal is copper (Cu) or a Cu alloy, for example. The first conductive portion2A and the second conductive portion2B form a conductive path to the semiconductor elements10, together with the input terminals41to43and the output terminals44. As shown inFIGS.13to18, the first conductive portion2A and the second conductive portion2B are bonded to the supporting substrate3via the first conductive bonding member71. The first semiconductor elements10A are bonded to the first conductive portion2A via the second conductive bonding member72. The second semiconductor elements10B are bonded to the second conductive portion2B via the second conductive bonding member72. As shown inFIGS.3,8,13, and14, the first conductive portion2A and the second conductive portion2B are spaced apart from each other in the x direction. In the example shown in these figures, the first conductive portion2A is offset in the x2 direction relative to the second conductive portion2B. The first conductive portion2A and the second conductive portion2B each have a rectangular shape in plan view, for example. The first conductive portion2A and the second conductive portion2B overlap with each other as viewed in the x direction. The first conductive portion2A and the second conductive portion2B may each have a dimension of 15 mm to 25 mm (preferably about 20 mm) in the x direction, a dimension of 30 mm to 40 mm (preferably about 35 mm) in the y direction, and a dimension of 1.5 mm to 3.0 mm (preferably about 2.0 mm) in the z direction.

The conductive substrate2has an obverse surface201and a reverse surface202. As shown inFIGS.13,14, and16to18, the obverse surface201and the reverse surface202are spaced apart from each other in the z direction. The obverse surface201faces in the z2 direction, and the reverse surface202faces in the z1 direction. The obverse surface201is a combination of the upper surface of the first conductive portion2A and the upper surface of the second conductive portion2B. The reverse surface202is a combination of the lower surface of the first conductive portion2A and the lower surface of the second conductive portion2B. The reverse surface202faces the supporting substrate3and is bonded to the supporting substrate3. As shown inFIGS.5,8, and13, the obverse surface201is formed with a plurality of recessed portions201a. The recessed portions201aare recessed from the obverse surface201in the z direction. The degree of recession (depth) of each recessed portion201ais greater than 0 μm and less than or equal to 100 μm, for example. The recessed portions201aare formed during molding described below, for example. The recessed portions201ainclude those formed in the obverse surface201of the first conductive portion2A, and those formed in the obverse surface201of the second conductive portion2B. Two recessed portions201aformed in the obverse surface201of the first conductive portion2A are spaced apart from each other in the y direction and overlap with each other as viewed in the y direction. Two recessed portions201aformed in the obverse surface201of the second conductive portion2B are spaced apart from each other in the y direction and overlap with each other as viewed in the y direction.

The conductive substrate2(each of the first conductive portion2A and the second conductive portion2B) includes a base member21, an obverse-surface bonding layer22, and a reverse-surface bonding layer23that are stacked on each other. The base member21is a plate-like member made of metal. The metal is Cu or a Cu alloy. The obverse-surface bonding layer22is formed on the upper surface of the base member21. The obverse-surface bonding layer22is the surface layer of the conductive substrate2in the z2 direction. The upper surface of the obverse-surface bonding layer22corresponds to the obverse surface201of the conductive substrate2. The obverse-surface bonding layer22is a Ag plating layer, for example. The reverse-surface bonding layer23is formed on the lower surface of the base member21. The reverse-surface bonding layer23is the surface layer of the conductive substrate2in the z1 direction. The lower surface of the reverse-surface bonding layer23corresponds to the reverse surface202of the conductive substrate2. The reverse-surface bonding layer23is a Ag plating layer, for example, as is the obverse-surface bonding layer22.

The supporting substrate3supports the conductive substrate2. The supporting substrate3is a direct bonded copper (DBC) substrate, for example. The supporting substrate3includes an insulating layer31, a first metal layer32, a first bonding layer321, and a second metal layer33.

The insulating layer31is made of a ceramic with excellent thermal conductivity, for example. The ceramic may be aluminum nitride (AlN). The insulating layer31is not limited to a ceramic, and may be an insulating resin sheet, for example. The insulating layer31has a rectangular shape in plan view, for example.

The first metal layer32is formed on the upper surface (surface facing in the z2 direction) of the insulating layer31. The material of the first metal layer32contains Cu, for example. The material may contain Al instead of Cu. The first metal layer32includes a first portion32A and a second portion32B. The first portion32A and the second portion32B are spaced apart from each other in the x direction. The first portion32A is offset in the x2 direction relative to the second portion32B. The first portion32A is bonded to the first conductive portion2A and supports the first conductive portion2A. The second portion32B is bonded to the second conductive portion2B and supports the second conductive portion2B. The first portion32A and the second portion32B each have a rectangular shape in plan view, for example.

The first bonding layer321is formed on the upper surface of the first metal layer32(each of the first portion32A and the second portion32B). The first bonding layer321is a Ag plating layer, for example. The first bonding layer321is provided to enhance the solid-phase diffusion bonding with the first conductive bonding member71.

The second metal layer33is formed on the lower surface of the insulating layer31(surface facing in the z1 direction). The second metal layer33is made of the same material as the first metal layer32. In the example shown inFIG.10, the lower surface (a bottom surface302described below) of the second metal layer33is exposed from the sealing resin8. The lower surface may not be exposed from the sealing resin8, and may be covered with the sealing resin8. The second metal layer33may overlap with the first portion32A and the second portion32B in plan view.

As shown inFIGS.13to18, the supporting substrate3has a supporting surface301and a bottom surface302. The supporting surface301and the bottom surface302are spaced apart from each other in the z direction. The supporting surface301faces in the z2 direction, and the bottom surface302faces in the z1 direction. As shown inFIG.10, the bottom surface302is exposed from the sealing resin8. The supporting surface301is the upper surface of the first bonding layer321, i.e., a combination of the upper surface of the first portion32A and the upper surface of the second portion32B. The supporting surface301faces the conductive substrate2, and is bonded to the conductive substrate2. The bottom surface302is the lower surface of the second metal layer33. A heat dissipating member (e.g., heat sink) or the like, which is not illustrated in the figure, can be attached to the bottom surface302. The dimension of the supporting substrate3in the z direction (distance along the z direction from the supporting surface301to the bottom surface302) is 0.7 mm to 2.0 mm, for example.

Each of the input terminals41to43and the output terminals44is a plate-like metal plate. The metal plate is made of Cu or a Cu alloy, for example. In the example shown inFIGS.1to5,8, and10, the semiconductor module A1includes the three input terminals41to43and the two output terminals44.

Power supply voltage is applied to the three input terminals41to43. In the present embodiment, the input terminal41is a positive electrode (P terminal), and the two input terminals42and43are negative electrodes (N terminal). Alternatively, the input terminal41may be a negative terminal (N terminal), and the two input terminals42and43may be positive terminals (P terminals). In this case, the wiring in the package may be appropriately changed according to the change in the polarity of each terminal. Each of the three input terminals41to43and the two output terminals44includes a portion covered with the sealing resin8and a portion exposed from a resin side surface of the sealing resin8.

As shown inFIG.14, the input terminal41is formed integrally with the first conductive portion2A. Unlike this configuration, the input terminal41may be separated from the first conductive portion2A and electrically bonded to the first conductive portion2A. As shown inFIG.8, for example, the input terminal41is offset in the x2 direction relative to the first semiconductor elements10A and the first conductive portion2A (conductive substrate2). The input terminal41is electrically connected to the first conductive portion2A, and is electrically connected to the reverse-surface electrodes15(drain electrodes) of the first semiconductor elements10A via the first conductive portion2A. The input terminal41is an example of a “first input terminal”.

The input terminal41has an input-side bonding surface411and input-side side surfaces412. The input-side bonding surface411faces in the z2 direction and extends in the x2 direction. Each of the input-side side surfaces412is located at the periphery of the input-side bonding surface411as viewed in the z direction, and faces in a direction intersecting with the input-side bonding surface411. In the present embodiment, the input-side side surfaces412include a tip surface413and a pair of lateral surfaces414. The tip surface413is positioned at the end of the input terminal41in the x2 direction and faces in the x2 direction. The pair of lateral surfaces414are located at the respective ends of the input terminal41in the y direction, and face in the y1 direction and the y2 direction, respectively. Among the input-side side surfaces412, at least one of the tip surface413and the pair of lateral surfaces414has an input-side machining mark. The input-side machining mark is formed by the cutting process of a lead frame as described below.

As shown inFIG.8, the two input terminals42and43are spaced apart from the first conductive portion2A. The two input terminals42and43are bonded to the second conducting member62. As shown inFIG.8, for example, the two input terminals42and43are offset in the x2 direction relative to the first semiconductor elements10A and the first conductive portion2A (conductive substrate2). The two input terminals42and43are electrically connected to the second conducting member62, and are electrically connected to the second obverse-surface electrodes12(source electrodes) of the second semiconductor elements10B via the second conducting member62. The input terminal42is an example of a “second input terminal”, and the input terminal43is an example of a “third input terminal”.

The input terminal42has an input-side bonding surface421and input-side side surfaces422, and the input terminal43has an input-side bonding surface431and input-side side surfaces432. The input-side bonding surfaces421and431face in the z2 direction, and extend in the x2 direction. Each of the input-side side surfaces422is located at the periphery of the input-side bonding surface421as viewed in the z direction, and faces in a direction intersecting with the input-side bonding surface421. Each of the input-side side surfaces432is located at the periphery of the input-side bonding surface431as viewed in the z direction, and faces in a direction intersecting with the input-side bonding surface431. In the present embodiment, the input-side side surfaces422include a tip surface423and a pair of lateral surfaces424. The tip surface423is positioned at the end of the input terminal42in the x2 direction and faces in the x2 direction. The pair of lateral surfaces424are located at the respective ends of the input terminal42in the y direction, and face in the y1 direction and the y2 direction, respectively. Among the input-side side surfaces422, at least one of the tip surface423and the pair of lateral surfaces424has an input-side machining mark. The input-side machining mark is formed by the cutting process of a lead frame as described below. The input-side side surfaces432include a tip surface433and a pair of lateral surfaces434. The tip surface433is positioned at the end of the input terminal43in the x2 direction and faces in the x2 direction. The pair of lateral surfaces434are located at the respective ends of the input terminal43in the y direction, and face in the y1 direction and the y2 direction, respectively. Among the input-side side surfaces432, at least one of the tip surface433and the pair of lateral surfaces434has an input-side machining mark. The input-side machining mark is formed by the cutting process of a lead frame as described below.

As shown inFIGS.1to5,8, and10, for example, the three input terminals41to43of the semiconductor module A1protrude from the sealing resin8in the x2 direction. The three input terminals41to43are spaced apart from each other. The two input terminals42and43are located opposite from each other with the input terminal41therebetween in the y direction. The input terminal42is offset in the y2 direction relative to the input terminal41, and the input terminal43is offset in the y1 direction relative to the input terminal41. The three input terminals41to43overlap with each other as viewed in the y direction.

As is evident fromFIGS.8and14, the two output terminals44are integrally formed with the second conductive portion2B. Unlike this configuration, the output terminals44may be separated from the second conductive portion2B and electrically bonded to the second conductive portion2B. As shown inFIG.8, for example, the two output terminals44are offset in the x1 direction relative to the second semiconductor elements10B and the second conductive portion2B (conductive substrate2). The output terminals44are electrically connected to the second conductive portion2B, and are electrically connected to the reverse-surface electrodes15(drain electrodes) of the second semiconductor elements10B via the second conductive portion2B. The two output terminals44are examples of a “first output terminal” and a “second output terminal”.

Each of the output terminals44has an output-side bonding surface441and output-side side surfaces442. The output-side bonding surface441faces in the z2 direction and extends in the x1 direction. Each of the output-side side surfaces442is located at the periphery of the output-side bonding surface441as viewed in the z direction, and faces in a direction intersecting with the output-side bonding surface441. In the present embodiment, the output-side side surfaces442include a tip surface443and a pair of lateral surfaces444. The tip surface443is positioned at the end of the output terminal44in the x1 direction and faces in the x1 direction. The pair of lateral surfaces444are located at the respective ends of the output terminal44in the y direction, and face in the y1 direction and the y2 direction, respectively. Among the output-side side surfaces442, at least one of the tip surface443and the pair of lateral surfaces444has an output-side machining mark. The output-side machining mark is formed by the cutting process of a lead frame as described below. The number of output terminals44is not limited to two, and may be one or no less than three. When the number of output terminals44is one, it is desirable that the output terminal44be connected to the middle section of the second conductive portion2B in the y direction.

The control terminals45are pin-like terminals for controlling the semiconductor elements10. The control terminals45include a plurality of first control terminals46A to46E and a plurality of second control terminals47A to47D. The first control terminals46A to46E are used to control the first semiconductor elements10A. The second control terminals47A to47D are used to control the second semiconductor elements10B.

The first control terminals46A to46E are arranged at intervals in the y direction. As shown inFIGS.8and14, for example, the first control terminals46A to46E are supported by the first conductive portion2A via the control terminal support5(a first supporting portion5A described below). As shown inFIGS.5and8, the first control terminals46A to46E are located between the first semiconductor elements10A and the three input terminals41to43in the x direction.

The first control terminal46A is a terminal (gate terminal) used to input a drive signal for the first semiconductor elements10A. The first control terminal46A receives the drive signal for driving the first semiconductor elements10A (e.g., it receives application of gate voltage).

The first control terminal46B is a terminal (source sense terminal) used to detect a source signal for the first semiconductor elements10A. Voltage (corresponding to a source current) applied to the second obverse-surface electrodes12(source electrodes) of the first semiconductor elements10A is detected from the first control terminal46B.

The first control terminals46C and46D are terminals that are electrically connected to the diode function unit D1. The first control terminal46C is electrically connected to the third obverse-surface electrode13of the first semiconductor element10A having the diode function unit D1, and the first control terminal46D is electrically connected to the fourth obverse-surface electrode14of the first semiconductor element10A having the diode function unit D1.

The first control terminal46E is a terminal (drain sense terminal) used to detect a drain signal for the first semiconductor elements10A. Voltage (corresponding to a drain current) applied to the reverse-surface electrodes15(drain electrodes) of the first semiconductor elements10A is detected from the first control terminal46E.

The second control terminals47A to47D are arranged at intervals in the y direction. As shown inFIGS.5and18, for example, the second control terminals47A to47D are supported by the second conductive portion2B via the control terminal support5(a second supporting portion5B described below). As shown inFIGS.5and8, the second control terminals47A to47D are located between the second semiconductor elements10B and the two output terminals44in the x direction.

Each of the control terminals45(first control terminals46A to46E and the second control terminals47A to47D) includes a holder451and a metal pin452.

The holder451is made of a conductive material. As shown inFIG.15, the holder451is bonded to the control terminal support5(a first metal layer52described below) via a conductive bonding member459. The holder451includes a tubular portion, an upper-end flange portion, and a lower-end flange portion. The upper-end flange portion is joined to the top of the tubular portion, and the lower-end flange portion is joined to the bottom of the tubular portion. The metal pin452is inserted through at least the upper-end flange portion and the tubular portion of the holder451. The upper surface of the upper-end flange portion is exposed from the sealing resin8(a second protruding portion852described below), and is covered with the resin member87.

The metal pin452is a rod-like member extending in the z direction. The metal pin452is supported by being pressed into the holder451. The metal pin452is electrically connected to the control terminal support5(a first metal layer52described below) at least via the holder451. As shown in the example inFIG.15, when the lower end (end in the z1 direction) of the metal pin452is in contact with the conductive bonding member459within the insertion hole of the holder451, the metal pin452is electrically connected to the control terminal support5via the conductive bonding member459.

The control terminal support5supports the control terminals45. The control terminal support5is provided between the obverse surface201(conductive substrate2) and the control terminals45.

The control terminal support5includes a first supporting portion5A and a second supporting portion5B. The first supporting portion5A is arranged on the first conductive portion2A of the conductive substrate2, and supports the first control terminals46A to46E among the control terminals45. As shown inFIG.15, the first supporting portion5A is bonded to the first conductive portion2A via a bonding member59. The bonding member59may be conductive or insulative. For example, the bonding member59may be solder. The second supporting portion5B is arranged on the second conductive portion2B of the conductive substrate2, and supports the second control terminals47A to47D among the control terminals45. The second supporting portion5B is bonded to the second conductive portion2B via the bonding member59.

The control terminal support5(the first supporting portion5A and the second supporting portion5B) may be a DBC substrate, for example. Each of the supporting portions of the control terminal support5includes an insulating layer51, a first metal layer52, and a second metal layer53that are stacked on each other.

The insulating layer51is made of a ceramic, for example. The insulating layer51has a rectangular shape in plan view, for example.

As shown inFIG.15, for example, the first metal layer52is formed on the upper surface of the insulating layer51. The control terminals45are erected on the first metal layer52. The first metal layer52is made of Cu or a Cu alloy, for example. As shown inFIG.8, the first metal layer52includes a first portion521, a second portion522, a third portion523, a fourth portion524, and a fifth portion525. The first portion521, the second portion522, the third portion523, the fourth portion524, and the fifth portion525are spaced apart and insulated from each other.

A plurality of wires731are bonded to the first portion521, so that the first portion521is electrically connected to the first obverse-surface electrodes11(gate electrodes) of the semiconductor elements10via the wires731. As shown inFIG.8, the first control terminal46A is bonded to the first portion521of the first supporting portion5A, and the second control terminal47A is bonded to the first portion521of the second supporting portion5B.

A plurality of wires732are bonded to the second portion522, so that the second portion522is electrically connected to the second obverse-surface electrodes12(source electrodes) of the semiconductor elements10via the wires732. As shown inFIG.8, the first control terminal46B is bonded to the second portion522of the first supporting portion5A, and the second control terminal47B is bonded to the second portion522of the second supporting portion5B.

A wire733is bonded to the third portion523, so that the third portion523is electrically connected to the third obverse-surface electrode13of the semiconductor element10having the diode function unit D1via the wire733. As shown inFIG.8, the first control terminal46C is bonded to the third portion523of the first supporting portion5A, and the second control terminal47C is bonded to the third portion523of the second supporting portion5B.

A wire734is bonded to the fourth portion524, so that the fourth portion524is electrically connected to the fourth obverse-surface electrode14of the semiconductor element10having the diode function unit D1via the wire734. As shown inFIG.8, the first control terminal46D is bonded to the fourth portion524of the first supporting portion5A, and the second control terminal47D is bonded to the fourth portion524of the second supporting portion5B.

A wire735is bonded to the fifth portion525of the first supporting portion5A, and the fifth portion525is electrically connected to the first conductive portion2A. The fifth portion525of the second supporting portion5B is not electrically connected to other components. As shown inFIG.8, the first control terminal46E is bonded to the fifth portion525of the first supporting portion5A.

As shown inFIG.15, for example, the second metal layer53is formed on the lower surface of the insulating layer51. As shown inFIG.15, the second metal layer53of the first supporting portion5A is bonded to the first conductive portion2A via the bonding member59. The second metal layer53of the second supporting portion5B is bonded to the second conductive portion2B via the bonding member59.

The conducting member6, together with the conductive substrate2, forms the path of a main circuit current switched by the semiconductor elements10. The conducting member6is separated from the obverse surface201(conductive substrate2) in the z2 direction, and overlaps with the obverse surface201in plan view. In the present embodiment, the conducting member6is made of a metal plate-like member. The metal is Cu or a Cu alloy, for example. Specifically, the conducting member6is a metal plate-like member that is bent. Alternatively, the conducting member6may be formed with a metal foil member. In the present embodiment, the conducting member6includes a plurality of first conducting members61and a second conducting member62. The main circuit current includes a first main circuit current and a second main circuit current. The first main circuit current flows through a path between the input terminal41and the output terminals44. The second main circuit current flows through a path between the output terminals44and the input terminals42,43.

The first conducting members61are connected to the second obverse-surface electrodes12(source electrodes) of the first semiconductor elements10A and the second conductive portion2B, so that the second obverse-surface electrodes12of the first semiconductor elements10A are electrically connected to the second conductive portion2B. The first conducting members61and the second obverse-surface electrodes12(seeFIG.8) of the first semiconductor elements10A, as well as the first conducting members61and the second conductive portion2B, are bonded to each other via the conductive bonding member69. The conductive bonding member69may be made of solder, a metal paste material, or a sintered metal. As shown inFIG.8, each of the first conducting members61has a band shape extending along the x direction in plan view.

In the present embodiment, each of the first conducting members61has a rectangular portion connecting the first semiconductor element10A and the second conductive portion2B, and the rectangular portion is formed with an opening61h, as shown inFIG.6, for example. The opening61hmay be a through-hole that penetrates through in the z direction, and is preferably formed in the center of the rectangular portion in plan view. The opening61his formed so that when a flowable resin material is injected to form a sealing resin, the resin material can easily flow between the upper side (in the z2 direction) and the lower side (in the z1 direction) near the first conducting member61. In plan view, the opening61hmay have a perfectly circular shape, or may have another shape such as an oval shape or a rectangular shape. Each of the first conducting members61is not limited to having the configuration described above, and may not be formed with an opening61h.

In the present embodiment, the number of first conducting members61is three so as to correspond to the number of first semiconductor elements10A. Alternatively, a single first conducting member61common to the first semiconductor elements10A may be used, without depending on the number of first semiconductor elements10A.

The second conducting member62electrically connects the second obverse-surface electrodes12of the second semiconductor elements10B to the input terminals42and43. The second conducting member62may have a maximum dimension of 25 mm to 40 mm (preferably about 32 mm) in the x direction, and a maximum dimension of 30 mm to 45 mm (preferably about 38 mm) in the y direction. As shown inFIG.6, the second conducting member62includes a first wiring portion621, a second wiring portion622, a third wiring portion623, and a fourth wiring portion624.

The first wiring portion621is connected to the input terminal42. The first wiring portion621and the input terminal42are bonded with the conductive bonding member69. The first wiring portion621has a band shape extending in the x direction in plan view.

The second wiring portion622is connected to the input terminal43. The second wiring portion622and the input terminal43are bonded with the conductive bonding member69. The second wiring portion622has a band shape extending in the x direction in plan view. The first wiring portion621and the second wiring portion622are spaced apart from each other in the y direction and arranged substantially in parallel to each other. The second wiring portion622is offset in the y1 direction relative to the first wiring portion621.

The third wiring portion623is joined to the first wiring portion621and the second wiring portion622. The third wiring portion623has a band shape extending in the y direction in plan view. As is evident fromFIG.6, the third wiring portion623overlaps with the second semiconductor elements10B in plan view. As shown inFIG.17, the third wiring portion623is connected to the second semiconductor elements10B. The third wiring portion623has a plurality of recessed areas623a. As shown inFIG.17, the recessed areas623aare recessed in the z1 direction relative to the other areas of the third wiring portion623. The recessed areas623aof the third wiring portion623are bonded to the second semiconductor elements10B. The recessed areas623aof the third wiring portion623and the second obverse-surface electrodes12(seeFIG.8) of the second semiconductor elements10B are bonded with the conductive bonding member69.

The fourth wiring portion624is joined to the first wiring portion621and the second wiring portion622. The fourth wiring portion624is also connected to the third wiring portion623. The fourth wiring portion624is offset in the x2 direction relative to the third wiring portion623. As is evident fromFIG.6, the fourth wiring portion624overlaps with the first semiconductor elements10A in plan view. The fourth wiring portion624includes a first band portion625and a plurality of second band portions626.

The first band portion625is a part of the fourth wiring portion624that has a band shape in plan view, and is spaced apart from the third wiring portion623in the x direction. The first band portion625is joined to the first wiring portion621and the second wiring portion622. The first band portion625overlaps with the first semiconductor elements10A in plan view. The first band portion625has a plurality of protruding areas625a. As shown inFIG.16, the protruding areas625aprotrude in the z2 direction relative to the other areas of the first band portion625. As shown inFIG.6, the protruding areas625aoverlap with the first semiconductor elements10A in plan view. Since the first band portion625has the protruding areas625a, areas for bonding the first conducting members61are provided on the first semiconductor elements10A, as shown inFIG.16. This prevents the first band portion625from being in contact with the first conducting members61.

Each of the second band portions626is connected to the first band portion625and the third wiring portion623. Each of the second band portions626has a band shape extending in the x direction in plan view. The second band portions626are spaced apart from each other in the y direction and arranged substantially in parallel to each other. In plan view, one end of each band portion626is connected to a part of the first band portion625, which is located between two first semiconductor elements10A adjacent in the y direction, and the other end of each band portion626is connected to a part of the third wiring portion623, which is located between two second semiconductor elements10B adjacent in the y direction.

The first band portion625has a first edge627and a second edge628. As shown inFIG.7, the first edge627is offset in the x1 direction relative to the first side191in plan view, and extends at least from the third side193to the fourth side194in the y direction. As such, two corners171and172of each first semiconductor element10A in the x2 direction do not overlap with the second conducting member62in plan view. The two corners are the corner171formed by the first side191and the third side193, and the corner172formed by the first side191and the fourth side194. Accordingly, in each of the first semiconductor elements10A, parts of the two sides flanking the corners171and172are visible in plan view (specifically, when viewed as shown inFIG.7; the same applies hereinafter). As shown inFIG.7, the second edge628is offset in the x2 direction relative to the second side192in plan view, and extends at least from the third side193to the fourth side194in the y direction. As such, two corners173and174of each first semiconductor element10A in the x1 direction do not overlap with the second conducting member62in plan view. The two corners are the corner173formed by the second side192and the third side193, and the corner174formed by the second side192and the fourth side194. Accordingly, in each of the first semiconductor elements10A, parts of the two sides flanking the corners173and174are visible in plan view.

Regarding the corners171,172,173, and174, it is sufficient for each of the visible portions of the two sides flanking the corners171,172,173, and174to have a length greater than 0 μm and no greater than 200 μm in plan view. Furthermore, it is preferable that in plan view, the length of each of the visible portions of the two sides flanking the corners171,172,173, and174be no less than 5 μm and no greater than 150 μm. When the length of each of the visible portions of the two sides flanking the corners171,172,173, and174is no less than 2 μm, it is possible to detect the corners of each of the first semiconductor elements10A. When the length of each of the visible portions of the two sides is no less than 5 μm, it is possible to reliably detect the corners of each of the first semiconductor elements10A. When the length of each of the visible portions of the two sides is greater than 200 μm, the bonding areas between the first conducting members61and the first semiconductor elements10A become smaller than necessary, which is not desirable. It is preferable that the upper limit of the length of each of the visible portions of the two sides be no greater than 150 μm, because the bonding area between the first conducting members61and the first semiconductor elements10A is prevented from being too small.

As shown inFIG.6, the conducting member6(first conducting members61and the second conducting member62) has first portions601. The first portions601are areas that overlap with the semiconductor elements10(the first semiconductor elements10A and the second semiconductor elements10B) in plan view. At the second conducting member62, parts of the fourth wiring portion624(areas overlapping with the first semiconductor elements10A in plan view) and parts of the third wiring portion623(areas overlapping with the second semiconductor elements10B in plan view) constitute the first portions601.

As shown inFIGS.6and8, the obverse-surface electrodes11,13,14, and16of one of the first semiconductor elements10A (the first semiconductor element10A having the diode function unit D1) are aligned along the y direction at the end of the first semiconductor element10A in the x2 direction. In plan view, the first conducting members61and the second conducting member62do not overlap with the obverse-surface electrodes11,13,14, and16of the first semiconductor element10A or with the corners171and172thereof in the x2 direction. Furthermore, in plan view, the first conducting members61and the second conducting member62do not overlap with at least one of the corners173and174of the first semiconductor element10A in the x1 direction (opposite from the side where the obverse-surface electrodes are arranged). As such, at least three corners among the four corners171,172,173, and174of the semiconductor element10A are visible in plan view. This makes it possible to inspect whether the first semiconductor elements10A are correctly mounted by automatic visual inspection when the first semiconductor elements10A, the conducting members61, and the second conducting member62are mounted on the conductive substrate2. In plan view, the four corners171,172,173, and174of each of the first semiconductor elements10A may all be visible. Note that the obverse-surface electrodes11,13,14, and16of the first semiconductor element10A are examples of “obverse-surface electrodes on one side”.

As shown inFIG.6, each of the second semiconductor elements10B has a rectangular shape in plan view, similarly to the first semiconductor elements10A, and has four corners181,182,183, and184corresponding to the four corners171,172,173, and174of each first semiconductor element10A. The above-described relationship in plan view between the four corners171,172,173, and174of each first semiconductor element10A and the first and second conducting members61,62also holds for the relationship in plan view between the four corners181,182,183, and184of each second semiconductor element10B and the second conducting member62.

As shown inFIG.5, the second conducting member62includes first portions62A and second portions62B. The first portions62A overlap with the obverse surface201of the conductive substrate2(the obverse surface201of either the first conductive portion2A or the second conductive portion2B) in plan view, and do not overlap with any of the semiconductor elements10in plan view. The second portions62B overlap with the obverse surface201in plan view, and overlap with the semiconductor elements10in plan view. InFIG.5, the first portions62A are shown with hatching that diagonally rising to the right, and the second portions62B are shown with hatching that diagonally falling to the right. The first portions62A have openings63. As shown inFIGS.5and13, for example, the openings63are partially cut away portions in plan view. In the present embodiment, the openings63are provided at positions that overlap with the obverse surface201of the first conductive portion2A (conductive substrate2) in plan view, and that do not overlap with the semiconductor elements10in plan view. The openings63are through-holes that penetrate through in the z direction, for example. The openings63include one formed in the first wiring portion621and one formed in the second wiring portion622. The openings63are provided in the vicinity of at least two of the four corners of the conductive substrate2in plan view. For example, one of the openings63is provided at an area of the first wiring portion621in the x2 direction, and the other at an area of the second wiring portion622in the x2 direction. Note that the planar shape of each opening63is not limited. For example, the openings63may be holes as described in the present embodiment or notches unlike the present embodiment. The openings63may be formed by electroforming, for example. In this case, the second conducting member62has openings63in areas not electrodeposited with a metal, instead of the openings63formed by removing portions of the second conducting member62.

The second conducting member62is formed with openings625hin rectangular portions that overlap with the first semiconductor elements10A in plan view. In the present embodiment, it is preferable that the openings625hbe formed to overlap with the centers of the first semiconductor elements10A in plan view. The openings625hare through-holes (seeFIG.6) formed in the protruding areas625aof the first band portion625(fourth wiring portion624), for example. The openings625hare used, when the first conducting members61and the first semiconductor elements10A are bonded, to optically check the bonding state from above.

The second conducting member62is formed with openings623hin rectangular portions that overlap with the second semiconductor elements10B in plan view. In the present embodiment, it is preferable that the openings623hbe formed to overlap with the centers of the second semiconductor elements10B in plan view. The openings623hare through-holes formed in the recessed areas623aof the third wiring portion623, for example. The openings623hare used when the second conducting member62is positioned relative to the conductive substrate2. In plan view, each of the two types of openings623hand625hmay have a perfectly circular shape, or may have another shape such as an oval shape or a rectangular shape.

The second conducting member62is not limited to having the configuration described above, and may not include the fourth wiring portion624. However, the second conducting member62is preferably provided with the fourth wiring portion624in order to reduce the inductance value due to the current flowing through the second conducting member62.

The first conductive bonding member71is provided between the conductive substrate2and the supporting substrate3to electrically bond the conductive substrate2and the supporting substrate3. The first conductive bonding member71includes a conductive bonding portion that electrically bonds the first conductive portion2A to the first portion32A, and a conductive bonding portion that electrically bonds the second conductive portion2B to the second portion32B. As shown inFIG.15, the first conductive bonding member71includes a first base layer711, a first layer712, and a second layer713that are stacked on each other.

As shown inFIG.15, it is most preferable that a side surface of the first conductive bonding member71and a side surface of the first metal layer32, which is the top layer of the supporting substrate3, be flush with each other. It is preferable that in plan view, the side surface of the first metal layer32is positioned slightly more inward than the side surface of the first conductive bonding member71. That is, in plan view, bonding is performed such that the side surface of the first metal layer32does not extend outward from the side surface of the first conductive bonding member71. If the side surface of the first metal layer32extends more outward than the side surface of the first conductive bonding member71in plan view, the creepage distance between the first metal layer32and the second metal layer33becomes undesirably small. In plan view, the side surface of the first metal layer32is positioned more outward than a side surface of the base member21in the conductive substrate2.

The first base layer711is made of a metal, such as Al or an Al alloy. The first base layer711is made of a sheet material. The Young's modulus of aluminum (Al), which is the material of the first base layer711, is 70.3 GPa.

The first layer712is formed on the upper surface of the first base layer711. The first layer712is provided between the first base layer711and the conductive substrate2(each of the first conductive portion2A and the second conductive portion2B). The first layer712is a Ag plating layer, for example. The first layer712is bonded to the respective reverse-surface bonding layers23of the first conductive portion2A and the second conductive portion2B by the solid-phase diffusion of metal, for example. In other words, the first layer712and the reverse-surface bonding layers23of the first conductive portion2A and the second conductive portion2B are bonded by solid-phase diffusion. As a result, the first layer712and the reverse-surface bonding layers23are bonded in direct contact with each other at the bonding interface. In the present disclosure, “A and B are bonded by solid-phase diffusion” means that as a result of solid-phase diffusion bonding, A and B are fixed to each other in direct contact at the bonding interface, where A and B constitute a solid-phase diffusion layer. When solid-phase diffusion bonding is performed under an ideal condition, the bonding interface may not exist clearly due to the diffusion of metal elements. On the other hand, when an inclusion such as an oxidation film is formed on the surface layers of A and B, or when there is a gap between A and B, the inclusion or the gap may exist at the bonding interface.

The second layer713is formed on the lower surface of the first base layer711. The second layer713is provided between the first base layer711and the supporting substrate3(each of the first portion32A and the second portion32B). The second layer713is a Ag plating layer, for example. The second layer713is bonded to the first bonding layer321formed on each of the first portion32A and the second portion32B by solid-phase diffusion of metal. In other words, the second layer713and the first bonding layer321are bonded by solid-phase diffusion in direct contact with each other at the bonding interface. The Young's modulus of silver (Ag), which is the material of the first layer712and the second layer713, is 82.7 GPa.

Since the first base layer711, the first layer712, and the second layer713in the first conductive bonding member71are made of the materials described above, the Young's modulus of the first base layer711is smaller than the Young's modulus of each of the first layer712and the second layer713. The thickness (dimension in the z direction) of the first base layer711is greater than the thickness of each of the first layer712and the second layer713.

In the first conductive bonding member71, an end surface of the first base layer711, which is made of Al or an Al alloy, is not plated with Ag, so that the end surface of the first base layer711is exposed. Note that the end surface of the first base layer711may be plated with Ag. In view of reducing the manufacturing cost of the first conductive bonding member71, it is preferable to fabricate the first conductive bonding member71by forming Ag plating on both surfaces of a large sheet material and then cutting the Ag-plated sheet material. In this regard, it is preferable that the end surface of the first base layer711not be plated with Ag.

The second conductive bonding member72is provided between the conductive substrate2and the semiconductor elements10to electrically bond the conductive substrate2and the semiconductor elements10. The second conductive bonding member72includes a conductive bonding portion that electrically bonds the first semiconductor elements10A to the first conductive portion2A, and a conductive bonding portion that electrically bonds the second semiconductor elements10B to the second conductive portion2B. As shown inFIG.15, the second conductive bonding member72includes a second base layer721, a third layer722, and a fourth layer723that are stacked on each other.

The second base layer721is made of a metal, such as Al or an Al alloy. The second base layer721is made of a sheet material.

The third layer722is formed on the upper surface of the second base layer721. The third layer722is provided between the second base layer721and the semiconductor elements10. The third layer722is a Ag plating layer, for example. The third layer722is bonded to the reverse-surface electrodes15of the semiconductor elements10by the solid-phase diffusion of metal, for example. In other words, the third layer722and the reverse-surface electrodes15are bonded by solid-phase diffusion in direct contact with each other at the bonding interface.

The fourth layer723is formed on the lower surface of the second base layer721. The fourth layer723is provided between the second base layer721and the conductive substrate2(each of the first conductive portion2A and the second conductive portion2B). The fourth layer723is a Ag plating layer, for example. The fourth layer723is bonded to the respective obverse-surface bonding layers22of the first conductive portion2A and the second conductive portion2B by the solid-phase diffusion of metal, for example. In other words, the fourth layer723and the obverse-surface bonding layers22are bonded by solid-phase diffusion in direct contact with each other at the bonding interface.

Since the second base layer721, the third layer722, and the fourth layer723in the second conductive bonding member72are made of the materials described above, the Young's modulus of the second base layer721is smaller than the Young's modulus of each of the third layer722and the fourth layer723. The thickness (dimension in the z direction) of the second base layer721is greater than the thickness of each of the third layer722and the fourth layer723.

In the second conductive bonding member72, an end surface of the second base layer721, which is made of Al or an Al alloy, is not plated with Ag, so that the end surface of the second base layer721is exposed. Note that the end surface of the second base layer721may be plated with Ag. In view of reducing the manufacturing cost of the second conductive bonding member72, it is preferable to fabricate the second conductive bonding member72by forming Ag plating on both surfaces of a large sheet material and then cutting the Ag-plated sheet material. In this regard, it is preferable that the end surface of the second base layer721not be plated with Ag.

Each of the wires731to735electrically connects two members that are separated from each other. The wires731to735are bonding wires, for example. The material of each of the wires731to735contains one of gold (Au), Al, or Cu, for example.

As shown inFIG.8, each of the wires731is bonded to and electrically connects the first obverse-surface electrode11(gate electrode) of a semiconductor element10and a first portion521(first metal layer52) of the control terminal support5. As shown inFIG.8, the plurality of wires731include a plurality of first wires731aand a plurality of second wires731b. Each of the first wires731ais connected to the first obverse-surface electrode11(gate electrode) of one of the first semiconductor elements10A and the first portion521(first metal layer52) of the first supporting portion5A. As a result, the first control terminal46A is electrically connected to the first obverse-surface electrodes11(gate electrodes) of the first semiconductor elements10A via the first wires731a. Each of the second wires731bis connected to the first obverse-surface electrode11(gate electrode) of one of the second semiconductor elements10B and the first portion521(first metal layer52) of the second supporting portion5B. As a result, the second control terminal47A is electrically connected to the first obverse-surface electrodes11(gate electrodes) of the second semiconductor elements10B via the second wires731b.

As shown inFIG.8, each of the wires732is bonded to and electrically connects the second obverse-surface electrode12(source electrode) of a semiconductor element10and a second portion522(first metal layer52) of the control terminal support5. As for each of the semiconductor elements10having the diode function units D1, the wire732is bonded to the fifth obverse-surface electrode16(source sense electrode) instead of the second obverse-surface electrode12(source electrode).

As shown inFIG.8, each of the wires733is bonded to and electrically connects the third obverse-surface electrode13of one of the semiconductor elements10having the diode function units D1and a third portion523(first metal layer52) of the control terminal support5.

As shown inFIG.8, each of the wires734is bonded to and electrically connects the fourth obverse-surface electrode14of one of the semiconductor elements10having the diode function units D1and a fourth portion524(first metal layer52) of the control terminal support5.

As shown inFIG.8, the wire735is bonded to and electrically connects the obverse surface201of the first conductive portion2A (conductive substrate2) and the fifth portion525(first metal layer52) of the first supporting portion5A (control terminal support5).

The sealing resin8covers the semiconductor elements10, the conductive substrate2, the supporting substrate3(except the bottom surface302), parts of the input terminals41to43, parts of the output terminals44, parts of the control terminals45, the control terminal support5, the conducting member6, and the wires731to735. The sealing resin8is made of a black epoxy resin, for example. The sealing resin8may be formed by molding described below. The sealing resin8may have a dimension of about 35 mm to 60 mm in the x direction, a dimension of about 35 mm to 50 mm in the y direction, and a dimension of about 4 mm to 15 mm in the z direction. Each of these dimensions is the size of the largest portion along one of the directions. The sealing resin8has a resin obverse surface81, a resin reverse surface82, and a plurality of resin side surfaces831to834.

As shown inFIGS.9,11, and12, for example, the resin obverse surface81and the resin reverse surface82are spaced apart from each other in the z direction. The resin obverse surface81faces in the z2 direction, and the resin reverse surface82faces in the z1 direction. The control terminals45(first control terminals46A to46E and the second control terminals47A to47D) protrude from the resin obverse surface81. As shown inFIG.10, the resin reverse surface82has a frame shape surrounding the bottom surface302of the supporting substrate3(lower surface of the second metal layer33) in plan view. The bottom surface302of the supporting substrate3is exposed from the resin reverse surface82, and is flush with the resin reverse surface82, for example. The resin side surfaces831to834are joined to the resin obverse surface81and the resin reverse surface82, and are flanked by these surfaces in the z direction. As shown inFIG.4, the resin side surface831and the resin side surface832are spaced apart from each other in the x direction. The resin side surface831faces in the x1 direction, and the resin side surface832faces in the x2 direction. The two output terminals44protrude from the resin side surface831, and the three input terminals41to43protrude from the resin side surface832. As shown inFIG.4, for example, the resin side surface833and the resin side surface834are spaced apart from each other in the y direction. The resin side surface833faces in the y1 direction, and the resin side surface834faces in the y2 direction.

As shown inFIG.4, the resin side surface832is formed with a plurality of recessed portions832a. The recessed portions832aare recessed in the x direction in plan view. The recessed portions832ainclude one formed between the input terminal41and the input terminal42, and one formed between the input terminal41and the input terminal43in plan view. The recessed portions832aare provided to increase the creepage distance between the input terminal41and the input terminal42along the resin side surface832, and to increase the creepage distance between the input terminal41and the input terminal43along the resin side surface832.

As shown inFIGS.13and14, the sealing resin8has a plurality of first protrusions851, a plurality of second protrusions852, and resin voids86.

The first protrusions851protrude from the resin obverse surface81in the z direction. The first protrusions851are arranged near the four corners of the sealing resin8in plan view. The tip end (end in the z2 direction) of each of the first protrusions851is formed with a first protruding end surface851a. The first protruding end surfaces851aof the first protrusions851are substantially parallel to the resin obverse surface81and positioned on the same plane (x-y plane) as the resin obverse surface81. Each of the first protrusions851has a bottomed hollow truncated cone shape, for example. The first protrusions851are used for an apparatus that uses a power supply generated by the semiconductor module A1, and function as spacers when the semiconductor module A1is mounted on, for example, a control circuit board of the apparatus. Each of the first protrusions851has a recessed portion851band an inner wall surface851cformed in the recessed portion851b. It suffices for the first protrusions851to have a pillar shape, preferably a columnar shape. It is preferable that each of the recessed portions851bhave a columnar shape, and each of the inner wall surfaces851chave a single perfect circular shape in plan view. Each of the first protrusions851is an example of a “protrusion”, and each of the first protruding end surfaces851ais an example of a “protruding end surface”.

The semiconductor module A1may be mechanically fixed to a control circuit board or the like by, for example, a screwing method. In this case, the threads of female screws may be formed in the inner wall surfaces851cof the recessed portions851bin the first protrusions851. It is also possible to embed an insert nut in the recessed portion851bof each of the first protrusions851.

As shown inFIG.14, for example, the second protrusions852protrude from the resin obverse surface81in the z direction. The second protrusions852overlap with the control terminals45in plan view. The metal pins452of the control terminals45protrude from the second protrusions852. A part of each holder451(upper surface of each upper-end flange portion) is exposed from the upper end surface of each second protrusion852. Each of the second protrusions852has a truncated cone shape. The resin members87are provided on the second protrusions852.

As shown inFIG.13, each of the resin voids86passes from the resin obverse surface81to the recessed portion201aformed in the obverse surface201of the conductive substrate2in the z direction. Each of the resin voids86is formed to be tapered such that the cross-sectional area thereof decreases along the z direction from the resin obverse surface81to the recessed portion201a. A resin void edge861of each of the resin voids86, which is in contact with the obverse surface201, and a recess edge201bof each of the recessed portions201a, which is in contact with the obverse surface201, coincide with each other. The resin voids86are portions that are formed in a molding process described below, and in which the sealing resin8is not formed during the molding process.

The resin members87are provided on the second protrusions852of the sealing resin8. The resin members87cover parts of the control terminals45, i.e., parts (upper surfaces of the upper-end flange portions) of the holders451that are exposed from the sealing resin8, and parts of the metal pins452. For example, the resin members87are made of epoxy resin, as with the sealing resin8, but may be made of a material different from the material of the sealing resin8.

The resin-filling portions88are provided for the resin voids86to fill the resin voids86. For example, the resin-filling portions88are made of epoxy resin, as with the sealing resin8, but may be made of a material different from the material of the sealing resin8.

The following describes a method for manufacturing the semiconductor module A1, with reference toFIGS.21to29.FIG.21is a plan view illustrating a step of the method for manufacturing the semiconductor module A1.FIG.22is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor module A1.FIG.23is a plan view illustrating a step of the method for manufacturing the semiconductor module A1.FIG.24is a cut end view illustrating a step of the method for manufacturing the semiconductor module A1.FIG.24corresponds to the cross section shown inFIG.13. Each ofFIGS.25and28is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module A1, and corresponds to an enlarged view of a part of the cross-section inFIG.13. Each ofFIGS.26,27, and29is a partially enlarged cross-sectional view illustrating a step of the method for manufacturing the semiconductor module A1, and corresponds to an enlarged view of a part of the cross-section inFIG.14.

First, a plurality of semiconductor elements10, a conductive substrate2, a supporting substrate3, a plurality of input terminals41to43, and a plurality of output terminals44are prepared. The configurations of the semiconductor elements10, the conductive substrate2, and the supporting substrate3are as described above. At the stage of preparing them, the semiconductor elements10, the conductive substrate2, and the supporting substrate3are separately prepared and not bonded to each other. As shown inFIG.21, the conductive substrate2, the input terminals41to43, and the output terminals44are connected to each other, and may be made of the same lead frame. As shown inFIG.21, no recessed portion201ais formed in the obverse surface201of the conductive substrate2.

Next, as shown inFIG.22, the conductive substrate2is placed on the supporting substrate3via a first conductive bonding member71, and the semiconductor elements10are placed on the conductive substrate2via a second conductive bonding member72. Then, heat is applied while the lower surface of the supporting substrate3and the upper surfaces of the semiconductor elements10are held (see the thick arrows inFIG.22). As a result, the semiconductor elements10and the conductive substrate2are bonded to each other by solid-phase diffusion, and the conductive substrate2and the supporting substrate3are bonded to each other by solid-phase diffusion. Specifically, the following elements are collectively bonded to each other by solid-phase diffusion: a first bonding layer321(supporting substrate3) on a first metal layer32and a second layer713(first conductive bonding member71); a first layer712(first conductive bonding member71) and a reverse-surface bonding layer23(conductive substrate2); a fourth layer723(second conductive bonding member72) and an obverse-surface bonding layer22(conductive substrate2); and a third layer722(second conductive bonding member72) and reverse-surface electrodes15of the semiconductor elements10. As for the conditions of the solid-phase diffusion, the heat temperature during bonding may be in the range of 200° C. to 350° C. inclusive, and the pressure applied (force for the holding) during the bonding may be in the range of 1 MPa to 100 MPa inclusive. The solid-phase diffusion bonding is assumed to be performed in the atmosphere, but it may be performed in vacuum instead. As a result, the conductive substrate2is bonded to the supporting substrate3via the first conductive bonding member71, and the semiconductor elements10are bonded to the conductive substrate2via the second conductive bonding member72. Note that the bonding between the conductive substrate2and the supporting substrate3, and the bonding between the conductive substrate2and the semiconductor elements10may be performed separately rather than collectively. However, it is more preferable to perform the bonding collectively in order to improve manufacturing efficiency.

When the semiconductor elements10are placed on the conductive substrate2via the second conductive bonding member72, individual second conductive bonding members72corresponding to the respective semiconductor elements10may be provided as shown inFIGS.16and17. Alternatively, it is possible to provide a single second conductive bonding member72corresponding to the three semiconductor elements10shown inFIG.16.

Next, as shown inFIG.23, bonding of a control terminal support5, bonding of a plurality of holders451of a plurality of control terminals45, bonding of a plurality of wires731to735, bonding of a plurality of first conducting members61, and bonding of a second conducting member62are performed. The bonding of these elements may be performed in any suitable order.

Next, a sealing resin8is formed. The sealing resin8is formed by molding, for example. As shown inFIG.24, a mold91for a molding process is provided with pressing pins911as pressing members. The tip ends of the pressing pins911are in contact with the obverse surface201of the conductive substrate2. At this point, recessed portions201aare formed in the obverse surface201by the pressing force of the pressing pins911to the obverse surface201. The degree of recession (depth) of the recessed portions201achanges depending on the strength of the pressing force or the like. The pressing pins911in contact with the obverse surface201of a first conductive portion2A are inserted through openings63of the second conducting member62. Then, a flowable resin material is injected into a cavity space919of the mold91via a resin flow channel and a resin inlet (both not shown) in sequence. The injected flowable resin material solidifies to form the sealing resin8. The sealing resin8thus formed has first protrusions851, second protrusions852, and resin voids86, which are all described above, as shown inFIGS.25and26. As shown inFIG.25, a resin void edge861of each of the resin voids86, which is in contact with the obverse surface201, and a recess edge201bof each of the recessed portions201a, which is in contact with the obverse surface201, coincide with each other. As shown inFIG.26, the upper surface of each of the holders451is exposed from a second protrusion852and flush with the upper surface of the second protrusion852. As is evident fromFIGS.24and25, the resin voids86are formed by the pressing pins911as a result of the flowable resin material not being filled. Note that the pressing pins911may be movable pins. In this case, the pressing pins911are preferably provided in holes formed in the mold91and supported elastically. Each of the pressing members does not necessarily have a pin shape, and may have a block shape instead.

Next, the mold91is opened, and a molded body is taken out, where the molded body contains the lead frame including the conductive substrate2, and the sealing resin8. Then, the sealing resin8is separated from the resin that has solidified at the resin flow channel and the resin inlet. In this process, one or more resin separation marks are formed at either a first position or a second position on a resin side surface831of the sealing resin8in the x1 direction. Referring toFIG.1, the first position may correspond to at least one of two positions each close to a respective end of the resin side surface831in the y direction, or at least one of the edges of the respective ends. In the case where the separation mark is formed at one of the edges of the respective ends, it may be formed at a surface formed along the edge (C chamfered portion in plan view). Such an inclined surface may be a part of the resin side surface831of the sealing resin8in the x1 direction. The second position is located between the two output terminals44at the resin side surface831shown inFIG.1. The resin separation mark corresponds to the position of a resin inlet of the mold91, and is formed by separating the sealing resin8from the resin that has solidified at the resin inlet. In order to prevent unevenness of the resin flow, it is preferable that the resin be injected from the central position of the mold in the y direction. In this case, a resin separation mark is formed between the two output terminals44.

Next, as shown inFIG.27, metal pins452of the control terminals45are pressed into the respective holders451. Specifically, the metal pins452, each of which has a cross-sectional dimension slightly larger than the inner diameter of a tubular portion (seeFIG.26) of each of the holders451, are inserted with pressure. As a result, the holders451and the metal pins452are mechanically fixed and electrically connected to each other. The holders451and the metal pins452may be electrically connected with solder, for example. Then, resin members87and resin-filling portions88are formed as shown inFIGS.28and29. The resin members87and the resin-filling portions88may be formed by potting.

Next, the lead frame is cut appropriately to separate the input terminals41to43and the output terminals44. For each of the input terminals41to43and the output terminals44shown inFIG.21, the area near the connecting portion (portion indicated by a dashed line inFIG.21) between the terminal and the outer frame portion of the lead frame may be cut with a die or the like. At this point, the input terminals41to43are formed with tip surfaces413,423, and433, respectively, that have input-side machining marks. Each of the output terminals44is formed with a tip surface443that has an output-side machining mark. When the lead frame has tie bars that connect, in the y direction, terminals which are adjacent in the y direction, the tie bars may be cut with a die or the like. In this case, for each of the terminals, machining marks are formed on two side surfaces that face in the y direction. The semiconductor module A1shown inFIGS.1to20is manufactured through the steps described above.

The semiconductor module A1is mounted on a circuit board for control, for example. The metal pins452are inserted into pin holes of the circuit board on which the semiconductor module A1is mounted, and are connected to terminals near the pin holes. The input terminals41,42, and43have the input-side bonding surfaces411,421, and431, respectively, that face in one sense (z2 direction) of the z direction. Each of the output terminals44has the output-side bonding surface441facing in one sense (z2 direction) of the z direction. The input-side bonding surfaces411,421,431, and the output-side bonding surfaces441are connected with solder, for example, to the terminals of the circuit board on which the semiconductor module A1is mounted.

The following describes the current path from the input terminal41to the output terminals44in the semiconductor module A1in the present embodiment. The first main circuit current flows through a path that includes the input terminal41, the first conductive portion2A, the first semiconductor elements10A, the first conducting members61, the second conductive portion2B, and the output terminals44. The first main circuit current flows along the x direction between the second obverse-surface electrodes12of the first semiconductor elements10A and the second conductive portion2B via the first conducting members61. In the second conductive portion2B, the first main circuit current flows along the x direction and a direction slightly inclined from the x direction between the portions to which the first conducting members61are bonded and the output terminals44.

The path of a current from the output terminals44to the input terminal42and the input terminal43is described below. The second main circuit current flows through a path that includes the output terminals44, the second conductive portion2B, the second semiconductor elements10B, the second conducting member62, the input terminal42, and the input terminal43. The second conducting member62, forming the path of the second main circuit current, includes the third wiring portion623extending in the y direction and the first and second wiring portions621,622joined to the respective ends of the third wiring portion623so as to extend in the x2 direction. Thus, the second main circuit current flows through the third wiring portion623as well as the first wiring portion621and the second wiring portion622. Further, the path of the second main circuit current includes the two second band portions626disposed between the first wiring portion621and the second wiring portion622so as to extend in the x direction and also includes the first band portion625disposed between the first wiring portion621and the second wiring portion622so as to extend in the y direction. Thus, the second main circuit current flows through the first wiring portion621and the second wiring portion622.

The second main circuit current flows between the input terminals42,43, and the second obverse-surface electrodes12of the second semiconductor elements10B via a path including the first wiring portion621, the second wiring portion622, the third wiring portion623, the two second band portions626, and the first band portion625in the second conducting member62. In the first wiring portion621, the second wiring portion622, and the two second band portions626, the second main circuit current flows along the x direction. The direction in which the first main circuit current flows is opposite from the direction in which the second main circuit current flows.

The direction in which the first main circuit current flows in the first conducting members61is the x direction, and the direction in which the second main circuit current flows in the first wiring portion621, the second wiring portion622, and the two second band portions626in the second conducting member62is also the x direction.

The following describes the operation and advantages of the semiconductor module A1.

The semiconductor module A1includes the conductive substrate2, the input terminals41to43, the output terminals44, and the conducting member6. The conductive substrate2includes the first conductive portion2A to which the first semiconductor elements10A are bonded, and the second conductive portion2B to which the second semiconductor elements10B are bonded. The input terminal41is joined to the first conductive portion2A, and is electrically connected to the first semiconductor elements10A via the first conductive portion2A. The input terminal42and the input terminal43are electrically connected to the second semiconductor elements10B via the second conductive member62(conducting member6). The output terminals44are joined to the second conductive portion2B, and are electrically connected to the second semiconductor elements10B via the second conductive portion2B. The conducting member6includes the first conducting members61that electrically connect the first semiconductor elements10A and the second conductive portion2B, and the second conducting member62that electrically connects the second semiconductor elements10B and the input terminals42and43. The input terminals41to43are offset in the x2 direction relative to the conductive substrate2, and the output terminals44are offset in the x1 direction relative to the conductive substrate2. The two input terminals42and43are located opposite from each other with the input terminal41therebetween in the y direction. Suppose that a semiconductor module has a configuration different from the semiconductor module A1in a manner such that no input terminal43is provided, and the input terminals41and42are arranged side by side in the y direction. In this case, variations may occur in the path of current flowing from the input terminal41to the output terminals44via the first semiconductor elements10A, and in the path of current flowing from the output terminals44to the input terminal42via the second semiconductor elements10B. In view of this, the semiconductor module A1includes the two input terminals42and43, and the two input terminals42and43flank the input terminal41. This makes it possible to reduce variations in the path of a current flowing from the input terminal41to the output terminals44via the first semiconductor elements10A, and to reduce variations in the path of a current flowing from the output terminals44to the input terminals42and43via the second semiconductor elements10B. As a result, the parasitic inductance components of the semiconductor module A1can be reduced. In other words, the semiconductor module A1has a package configuration preferable for reducing parasitic inductance components.

In the semiconductor module A1, an upper arm current path and a lower arm current path overlap with each other in plan view. The upper arm current path is the path of a current flowing from the input terminal41to the output terminals44via the first conductive portion2A, the first semiconductor elements10A, the first conducting members61, and the second conductive portion2B. In the present embodiment, as seen fromFIG.5, the upper arm current path extends from the x2 direction side to the x1 direction side. The lower arm current path is the path of a current flowing from the output terminals44to the input terminal42via the second semiconductor elements10B and the second conductive member62. In the present embodiment, as seen fromFIG.5, the lower arm current path extends from the x1 direction side to the x2 direction side. With this configuration, the magnetic field generated by the current along the upper arm current path and the magnetic field generated by the current along the lower arm current path cancel each other out, thus enabling reduction of parasitic inductance components. In particular, the conducting member6(each of the first conducting members61and the second conducting member62) in the semiconductor module A1is made of a metal plate-like member, so that an area where the upper arm current path and the lower arm current path overlap with each other in plan view can be provided appropriately. In other words, the semiconductor module A1has a package configuration preferable for reducing parasitic inductance components.

In the semiconductor module A1, the second conducting member62that forms the lower arm current path includes the first wiring portion621, the second wiring portion622, the third wiring portion623, and the fourth wiring portion624. The first wiring portion621and the second wiring portion622extend in the x direction, and are respectively connected to the input terminal42and the input terminal43that are arranged opposite from each other with the input terminal41therebetween in the y direction. The third wiring portion623is joined to the first wiring portion621and the second wiring portion622, extends in the y direction, and is connected to the second semiconductor elements10B. The fourth wiring portion624is joined to the first wiring portion621and the second wiring portion622, and overlaps with the first semiconductor elements10A in plan view. The second conductive member62including the first wiring portion621, the second wiring portion622, the third wiring portion623, and the fourth wiring portion624is spaced apart from the obverse surface201(conductive substrate2) in the z direction, and overlaps with a wide area of the obverse surface201in plan view. This configuration can appropriately reduce variations in the path of a current flowing from the output terminals44to the input terminals42and43via the second semiconductor elements10B, and therefore is suitable in reducing parasitic inductance components.

The first semiconductor elements10A and the second semiconductor elements10B overlap with each other as viewed in the x direction. This configuration can suppress an increase in the dimension in the y direction of the conductive substrate2(first conductive portion2A and the second conductive portion2B) on which the first semiconductor elements10A and the second semiconductor elements10B are arranged, and can therefore reduce the size of the semiconductor module A1.

The fourth wiring portion624of the second conductive member62has the first band portion625and the second band portions626. The first band portion625is joined to the first wiring portion621and the second wiring portion622, extends in the y direction, and overlaps with the first semiconductor elements10A in plan view. Each of the second band portions626is connected to the first band portion625and the third wiring portion623, and has a band shape extending in the x direction in plan view. The second band portions626are spaced apart from each other in the y direction and arranged substantially in parallel to each other. In plan view, one end of each band portion626is connected to a part of the first band portion625, which is located between two first semiconductor elements10A adjacent in the y direction, and the other end of each band portion626is connected to a part of the third wiring portion623, which is located between two second semiconductor elements10B adjacent in the y direction. This configuration can increase the size of the fourth wiring portion624(second conductive member62) in plan view. This is more preferable for reducing parasitic inductance components.

The first band portion625has the protruding areas625aprotruding in the z2 direction relative to the other areas. The protruding areas625aoverlap with the first semiconductor elements10A in plan view. According to the configuration in which the first band portion625has the protruding areas625a, the first band portion625is prevented from making improper contact with the first conducting members61bonded to the first semiconductor elements10A.

The third wiring portion623has the recessed areas623arecessed in the z1 direction relative to the other areas. The recessed areas623aare bonded to the respective second semiconductor elements10B. This configuration can increase the size of the third wiring portion623(second conductive member62) in plan view while electrically connecting the third wiring portion623(second conductive member62) and the second semiconductor elements10B in a suitable manner.

The semiconductor module A1includes the conducting member6(first conducting members61and the second conducting member62) having the configuration described above, and further includes the first control terminals46A to46E and the second control terminals47A to47D for controlling the first semiconductor elements10A and the second semiconductor elements10B. The first control terminals46A to46E and the second control terminals47A to47D are provided on the obverse surface201of the conductive substrate2and extend along the z direction. The semiconductor module A1having this configuration can have a smaller size in plan view, and therefore is suitable for reducing the size in plan view while reducing parasitic inductance components.

The first control terminals46A to46E are supported by the first conductive portion2A and offset in the x2 direction relative to the first semiconductor elements10A. The second control terminals47A to47D are supported by the second conductive portion2B and offset in the x1 direction relative to the second semiconductor elements10B. The first control terminals46A to46E are arranged at intervals in the y direction, and the second control terminals47A to47D are also arranged at intervals in the y direction. As such, the first control terminals46A to46E and the second control terminals47A to47D are appropriately arranged in an area corresponding to the first semiconductor elements10A that constitute the upper arm circuit, and in an area corresponding to the second semiconductor elements10B that constitute the lower arm circuit, respectively. The semiconductor module A1having this configuration is more preferable for downsizing while reducing parasitic inductance components.

Each of the first semiconductor elements10A and the second semiconductor elements10B has a first obverse-surface electrode11(gate electrode) facing in the z2 direction. The first control terminal46A is connected to the first obverse-surface electrodes11(gate electrodes) of the first semiconductor elements10A via the first wires731a. The second control terminal47A is connected to the first obverse-surface electrodes11(gate electrodes) of the second semiconductor elements10B via the second wires731b. This makes it possible to appropriately input, to the first obverse-surface electrodes11, a drive signal for driving the first semiconductor elements10A (second semiconductor elements10B) that have a switching function, via the first control terminal46A (second control terminal47A) and the first wires731a(second wires731b).

When the semiconductor module A1is mounted on a circuit board, the metal pins452are inserted into the pin holes of the circuit board on which the semiconductor module A1is mounted, and are connected to terminals near the pin holes. The input terminals41,42, and43have the input-side bonding surfaces411,421, and431, respectively, that face in one sense (z2 direction) of the z direction. The output terminals44have the output-side bonding surfaces441facing in one sense (z2 direction) of the z direction. The input-side bonding surfaces411,421,431, and the output-side bonding surfaces441are connected with solder, for example, to the terminals of the circuit board on which the semiconductor module A1is mounted. With this configuration, the power system circuit board to which the input terminals41to43and the output terminals44are connected and the control system circuit board to which the metal pins452are connected can be arranged in separation in the z direction. This achieves the following improvements. Firstly, an improvement is made in the degree of freedom regarding the arrangement of a signal terminal in the semiconductor module A1. Secondly, an improvement is made in the degree of freedom regarding the routing and length of a signal wire in the semiconductor module A1. Thirdly, an improvement is made in the degree of freedom regarding the arrangement of a circuit board by a user when the semiconductor module A1is used.

In the semiconductor module A1, the control terminals45protrude from the resin obverse surface81and extend along the z direction. In a configuration different from that of the semiconductor module A1, the control terminals45may be arranged to extend along a plane (x-y plane) perpendicular to the z direction. This configuration has a limit to the size reduction in plan view. Accordingly, as in the semiconductor module A1, the control terminals45can be arranged to extend along the z direction, so that the size of the semiconductor module A1can be reduced in plan view. In other words, the semiconductor module A1has a package configuration preferable for the size reduction in plan view.

In the semiconductor module A1of the present embodiment, the control terminal support5is provided between the control terminals45and the obverse surface201(conductive substrate2). The control terminal support5has the insulating layer51, and the control terminals45are supported by the conductive substrate2via the control terminal support5. The configuration with the control terminal support5can support the control terminals45on the conductive substrate2appropriately while maintaining insulation from the conductive substrate2.

The control terminal support5has a layup structure in which the insulating layer51, the first metal layer52, and the second metal layer53are stacked on each other. The control terminals45are bonded to the first metal layer52, which is formed as the upper surface of the control terminal support5, via the conductive bonding member459. According to the configuration, the control terminals45can be electrically bonded to the control terminal support5(first metal layer52) while utilizing an existing layup structure (e.g., DBC substrate) as the control terminal support5.

Each of the semiconductor elements10has an element obverse surface101facing in the z2 direction, and an element reverse surface102facing in the z1 direction. A first obverse-surface electrode11(gate electrode) is provided on the element obverse surface101. The first obverse-surface electrode11of each of the semiconductor elements10and the first metal layer52(first portion521) are connected by a wire731that is electrically conductive. This makes it possible to input a drive signal for driving the semiconductor elements10having a switching function to the first obverse-surface electrodes11appropriately, via the control terminals45, the first metal layer52, and the wires731.

Each of the control terminals45includes a holder451and a metal pin452. The holder451is made of a conductive material, and includes a tubular portion. The metal pin452is a rod-like member extending in the z direction, and is pressed into the holder451. A part (the upper surface of the upper-end flange portion) of the holder451is exposed from the sealing resin8. According to this configuration, the sealing resin8is formed (by molding) such that the holder451is covered with the sealing resin8except a part (upper end surface) of the holder451, and the upper end surface of the holder451is exposed from the sealing resin8. This makes it possible to insert the metal pin452into the holder451after the sealing resin8is formed. Accordingly, with the configuration in which the control terminals45include the holders451and the metal pins452, it is possible to avoid complexity of the mold91for a molding process. For this reason, this configuration is suitable for efficiently manufacturing the semiconductor module A1.

The semiconductor module A1of the present embodiment includes the resin members87bonded to the sealing resin8. The resin members87cover parts (upper surfaces of the upper-end flange portions) of the holders451that are exposed from the sealing resin8, and parts of the metal pins452. This configuration prevents foreign matter from entering the connecting portions between the holders451and the metal pins452. The semiconductor module A1having the above configuration is preferable in terms of durability and reliability.

The sealing resin8has the second protrusions852protruding from the resin obverse surface81. The second protrusions852surround the respective control terminals45in plan view. The metal pins452of the control terminals45protrude from the second protrusions852. The resin members87are provided on the second protrusions852. According to this configuration, the creepage distance between adjacent control terminals45along the resin obverse surface81can be increased. This is preferable for increasing the withstand voltage of the adjacent control terminals45.

The conductive substrate2includes the first conductive portion2A and the second conductive portion2B that are spaced apart from each other in the x direction. The first conductive portion2A is offset in the x2 direction relative to the second conductive portion2B. The semiconductor elements10include the first semiconductor elements10A bonded to the first conductive portion2A, and the second semiconductor elements10B bonded to the second conductive portion2B. The control terminals45include the first control terminals46A to46E, and the second control terminals47A to47D. The first control terminals46A to46E are supported by the first conductive portion2A, and arranged between the first semiconductor elements10A and the input terminals41,42, etc., in the x direction. The second control terminals47A to47D are provided between the second semiconductor elements10B and the output terminals44in the x direction. With this configuration, the control terminals45(the first control terminals46A to46E, and the second control terminals47A to47D) are appropriately arranged in an area corresponding to the first semiconductor elements10A that constitute the upper arm circuit, and in an area corresponding to the second semiconductor elements10B that constitute the lower arm circuit. The configuration is preferable for downsizing the semiconductor module A1.

The sealing resin8has the first protrusions851protruding from the resin obverse surface81. The tip end of each of the first protrusions851is formed with a first protruding end surface851a. The first protruding end surfaces851aof the first protrusions851are substantially parallel to the resin obverse surface81and positioned on the same plane (x-y plane) as the resin obverse surface81. With this configuration, it is possible, in an apparatus that uses a power supply generated by the semiconductor module A1, to provide a predetermined gap between the surface of a control circuit board on which the semiconductor module A1is mounted and the resin obverse surface81. In this way, even when various functional components are mounted on a surface of the control circuit board that faces the semiconductor module A1, the functional components do not make improper contact with the sealing resin8.

The semiconductor module A1includes the conductive substrate2to which the semiconductor elements10are bonded. With this configuration, the heat generated by energization of the semiconductor elements10is transferred from the semiconductor elements10to the conductive substrate2and diffused at the conductive substrate2. As such, the semiconductor module A1has a package configuration preferable for improving the heat dissipation property of the semiconductor elements10.

In the semiconductor module A1, the conductive substrate2and the supporting substrate3are bonded to each other via the first conductive bonding member71. The first conductive bonding member71includes the first layer712and the second layer713. The first layer712is bonded to the conductive substrate2by the solid-phase diffusion of metal, and is in direct contact with the conductive substrate2at the bonding interface. The second layer713is bonded to the supporting substrate3by the solid-phase diffusion of metal, and is in direct contact with the supporting substrate3at the bonding interface. This configuration can increase the bonding strength between the conductive substrate2and the supporting substrate3as compared to the case where the conductive substrate2and the supporting substrate3are bonded by a bonding material such as solder. Accordingly, the semiconductor module A1has a package configuration preferable for suppressing the peeling between the conductive substrate2and the support substrate3.

In the semiconductor module A1, the semiconductor elements10and the conductive substrate2are bonded to each other via the second conductive bonding member72. The second conductive bonding member72includes the third layer722and the fourth layer723. The third layer722is bonded to the semiconductor elements10(reverse surface electrodes15) by the solid-phase diffusion of metal, and is in direct contact with the semiconductor elements10at the bonding interface. The fourth layer723is bonded to the conductive substrate2by the solid-phase diffusion of metal, and is in direct contact with the conductive substrate2at the bonding interface. This configuration can increase the bonding strength between the semiconductor elements10and the conductive substrate2as compared to the case where the semiconductor elements10and the conductive substrate2are bonded by a bonding material such as solder. Accordingly, the semiconductor module A1has a package configuration preferable for suppressing the peeling between the semiconductor elements10and the conductive substrate2.

In the semiconductor module A1of the present embodiment, the Young's modulus of the first base layer711in the first conductive bonding member71is smaller than the Young's modulus of the material of each of the first layer712and the second layer713. According to the configuration, when the first conductive bonding member71is bonded to the conductive substrate2and the supporting substrate3by solid-phase diffusion, the stress is alleviated by the relatively soft first base layer711, and the bonding boundary portion is thereby smoothed. As a result, the first layer712and the conductive substrate2, as well as the second layer713and the supporting substrate3, are more firmly bonded by solid-phase diffusion.

In the present embodiment, the first base layer711is thicker than each of the first layer712and the second layer713. Accordingly, when bonding by solid-phase diffusion is performed, the pressing force acting on the boundary portion between the first layer712and the conductive substrate2(reverse-surface bonding layer23) and on the boundary portion between the second layer713and the supporting substrate3(first bonding layer321) is made more uniform. As a result, the first layer712and the conductive substrate2, as well as the second layer713and the supporting substrate3, can be in a stronger conductive bonding state.

The material of each of the first layer712and the second layer713contains silver. With this composition, when bonding by solid-phase diffusion is performed with the first conductive bonding member71, oxidation of the first layer712and the second layer713is suppressed, thus enabling excellent solid-phase diffusion bonding. The reverse-surface bonding layer23and the first bonding layer321, which are bonded to the first layer712and the second layer713respectively, also contain silver, thus enabling better solid-phase diffusion bonding.

In the present embodiment, the Young's modulus of the second base layer721in the second conductive bonding member72is smaller than the Young's modulus of the material of each of the third layer722and the fourth layer723. According to the configuration, when the second conductive bonding member72is bonded to the semiconductor elements10(reverse-surface electrodes15) and the conductive substrate2by solid-phase diffusion, the stress is alleviated by the relatively soft second base layer721, and the bonding boundary portion is thereby smoothed. As a result, the third layer722and the semiconductor elements10(reverse-surface electrodes15), as well as the fourth layer723and the conductive substrate2, are more firmly bonded by solid-phase diffusion.

In the present embodiment, the second base layer721is thicker than each of the third layer722and the fourth layer723. Accordingly, when bonding by solid-phase diffusion is performed, the pressing force acting on the boundary portion between the third layer722and the semiconductor elements10(reverse-surface electrodes15) and on the boundary portion between the fourth layer723and the conductive substrate2(obverse-surface bonding layers22) is made more uniform. As a result, the third layer722and the semiconductor elements10(reverse-surface electrodes15), as well as the fourth layer723and the conductive substrate2, can be in a stronger conductive bonding state.

The material of each of the third layer722and the fourth layer723contains silver. With this material composition, when bonding by solid-phase diffusion is performed with the second conductive bonding member72, oxidation of the third layer722and the fourth layer723is suppressed, thus enabling excellent solid-phase diffusion bonding. The reverse-surface electrodes15and the obverse-surface bonding layers22, which are bonded to the third layer722and the fourth layer723respectively, contain silver, thus enabling better solid-phase diffusion bonding.

The first conductive bonding member71has a configuration where the first layer712and the second layer713, which are Ag plating layers, are formed on the surfaces (both surfaces) of the first base layer711, which is made of a sheet material containing A1. Similarly, the second conductive bonding member72has a configuration where the third layer722and the fourth layer723, which are Ag plating layers, are formed on the surfaces (both surfaces) of the second base layer721, which is made of a sheet material containing A1. With this configuration, the first conductive bonding member71and the second conductive bonding member72can be easily prepared.

In the semiconductor module A1, the second conducting member62is formed with the openings63. The openings63overlap with the obverse surface201(conductive substrate2) in plan view, and do not overlap with the semiconductor elements10in plan view. With this configuration, during a molding step (step for forming the sealing resin8) in the process for manufacturing the semiconductor module A1, the pressing pins911of the mold91can be inserted into the openings63. This allows the pressing pins911to press the conductive substrate2without interfering with the second conducting member62, thus suppressing the warpage of the supporting substrate3to which the conductive substrate2is bonded. The warpage occurs, for example, such that the outer sides of the supporting substrate3in the y direction are positioned more upward than the center thereof in the y direction. If warpage occurs on the supporting substrate3, the bonding strength between the conductive substrate2and the supporting substrate3may be lowered. Furthermore, during a molding process, a part of the sealing resin8may be formed on the bottom surface302due to resin leakage, causing a bonding failure of a heat dissipating member (e.g., heat sink) that can be bonded to the bottom surface302. Accordingly, the semiconductor module A1has a package configuration that is preferable for improving the bonding strength between the conductive substrate2and the supporting substrate3by suppressing the warpage of the supporting substrate3, and that is also preferable for suppressing the leakage of the sealing resin8to an unintended location.

The conductive substrate2includes the first conductive portion2A to which the first semiconductor elements10A are bonded, and the second conductive portion2B to which the second semiconductor elements10B are bonded. The first conductive portion2A and the second conductive portion2B are spaced apart from each other in the x direction, and the first conductive portion2A is offset in the x2 direction relative to the second conductive portion2B. The second conducting member62is connected to the second semiconductor elements10B and the input terminals42and43, and the openings63in the second conducting member62overlap with the obverse surface201of the first conductive portion2A in plan view. With this configuration, even when the second conducting member62is designed to have a large size in plan view, the pressing pins911of the mold91can press the conductive substrate2without interfering with the second conducting member62during the formation (during the molding process) of the sealing resin8. Note that the parasitic resistance components of the second conducting member62(conductive member6) that forms the path of the main circuit current can be suppressed by increasing the size of the second conducting member62in plan view.

The second conducting member62includes the first wiring portion621, the second wiring portion622, the third wiring portion623, and the fourth wiring portion624. The first wiring portion621and the second wiring portion622extend in the x direction, and are respectively connected to the input terminal42and the input terminal43that are arranged opposite from each other with the input terminal41therebetween in the y direction. The third wiring portion623is joined to the first wiring portion621and the second wiring portion622, extends in the y direction, and is connected to the second semiconductor elements10B. The openings63are formed in the areas of the first wiring portion621and the second wiring portion622that are offset in the x2 direction. As such, the openings63are provided near two corners of the conductive substrate2(first conductive portion2A) at respective outer sides of the conductive substrate2in the y direction. Accordingly, the openings63are provided near two corners of the supporting substrate3supporting the conductive substrate2(first conductive portion2A) at the respective outer sides of the supporting substrate3in the y direction. The configuration as described above allows the size of the second conducting member62to be relatively large in plan view and, during the formation of the sealing resin8(molding process), areas near the two corners of the conductive substrate2(first conductive portion2A) at the respective outer sides of the conductive substrate2in the y direction can be pressed with the pressing pins911of the mold91which are inserted into the openings63. As described above, the warpage of the supporting substrate3to which the conductive substrate2is bonded occurs such that the outer sides of the supporting substrate3in the y direction are positioned more upward than the center thereof in the y direction. However, the configuration described above can effectively suppress the warpage of the supporting substrate3during the molding process.

In the present embodiment, the conducting member6(the first conducting members61and the second conducting member62) is made of a metal plate-like member. This facilitates formation of the openings63in the second conducting member62. Furthermore, the conducting member6(the first conducting members61and the second conducting member62) made of a metal plate-like member can easily adapt to various shapes and sizes, and can increase the reliability of a bonding portion with another component by securing a sufficient bonding area with the other component.

Parts of the obverse surface201of the conductive substrate2(first conductive portion2A) overlap with the openings63in plan view and are formed with the recessed portions201a. The recessed portions201aare marks left by the pressing pins911applying a pressing force to the obverse surface201during the molding process. In the present embodiment, it is possible to devise an arrangement of the second conducting member62and the openings63formed therein, so that during the molding process, appropriate parts of the conductive substrate2(first conductive portion2A) can be pressed with the pressing pins911while avoiding interference with functional elements such as the semiconductor elements10.

The sealing resin8is formed with the resin voids86passing from the resin obverse surface81to the recessed portions201a. Each of the resin voids86is tapered such that the cross-sectional area thereof decreases from the resin obverse surface81to the recessed portion201a. The resin voids86are formed during a molding process (when the sealing resin8is formed). After the molding, the surfaces of the recessed portions201ain the obverse surface201of the conductive substrate2are exposed from the sealing resin8. In the present embodiment, the resin-filling portions88are provided for the resin voids86to fill the resin voids86. This configuration can prevent foreign matter (such as moisture) from entering the recessed portions201aexposed from the sealing resin8. The semiconductor module A1having the above configuration is preferable in terms of durability and reliability.

In the present embodiment, the openings63in the second conducting member62(conducting member6) are through-holes that penetrate through in the z direction. This configuration can prevent a deviation of the current path caused by forming the openings63in the second conducting member62(conducting member6) that forms the path of a main circuit current.

The semiconductor module A1includes the conducting member6. The conducting member6forms the path of a main circuit current switched by the semiconductor elements10. The conducting member6includes the first conducting members61connected to the first semiconductor elements10A, and the second conducting member62connected to the second semiconductor elements10B. The conducting member6(each of the first conducting members61and the second conducting member62) is made of a metal plate-like member. The main circuit current described above may have a relatively large value. In this case, it is preferable to suppress the parasitic resistance components in the conducting member6that forms the path of the main circuit current in order to reduce the power consumption of the semiconductor module A1. Accordingly, in the semiconductor module A1, the conducting member6is made of a metal plate-like member instead of a bonding wire as described above to suppress the parasitic resistance components of the conducting member6. In other words, the semiconductor module A1has a package configuration preferable for suppressing the parasitic resistance components.

In the semiconductor module A1, each of the first semiconductor elements10A has a rectangular shape in plan view, and the four corners of each of the first semiconductor elements10A in plan view do not overlap with the second conducting member62. According to this configuration, during the manufacturing process of the semiconductor module A1, it is possible to conduct visual inspection before forming the sealing resin8so as to check whether the first semiconductor elements10A are properly bonded. In other words, the semiconductor module A1allows for visual inspection regarding the bonding state of the first semiconductor elements10A during the manufacturing process (e.g., the stage shown inFIG.23). This makes it possible to determine whether the first semiconductor elements10A are properly bonded. For example, it is possible to measure respective distances to the four corners of each first semiconductor element10A by a laser ranging method, and determine that the first semiconductor element10A is properly bonded if the difference between the distances to the four corners is small. As described above, the semiconductor module A1can conduct visual inspection during the manufacturing process, and therefore has package configuration preferable for improving reliability. During the visual inspection, it is sufficient if at least three of the four corners of each of the first semiconductor elements10A are visible in plan view. For this reason, it is sufficient if three corners of each of the first semiconductor elements10A do not overlap with the second conducting member62. Similarly, as shown inFIG.5, four corners of each of the second semiconductor elements10B do not overlap with the second conducting member62. Accordingly, during the manufacturing process of the semiconductor module A1, it is possible to conduct visual inspection before forming the sealing resin8so as to check whether the second semiconductor elements10B are properly bonded. The visual inspection may be automatic visual inspection that uses image-capturing and image processing.

The second conducting member62includes the first wiring portion621, the second wiring portion622, the third wiring portion623, and the fourth wiring portion624. The first wiring portion621and the second wiring portion622extend in the x direction, and are respectively connected to the input terminal42and the input terminal43that are arranged opposite from each other with the input terminal41therebetween in the y direction. The third wiring portion623is joined to the first wiring portion621and the second wiring portion622, extends in the y direction, and is connected to the second semiconductor elements10B. The fourth wiring portion624is joined to the first wiring portion621and the second wiring portion622. The fourth wiring portion624is offset in the x2 direction relative to the third wiring portion623, and overlaps with the first semiconductor elements10A in plan view. The second conductive member62including the first wiring portion621, the second wiring portion622, the third wiring portion623, and the fourth wiring portion624overlaps with a wide area of the obverse surface201in plan view, and has a relatively large size in plan view. Increasing the size of the second conducting member62in plan view is preferable in terms of suppressing the parasitic resistance components of the second conducting member62(conductive member6) that forms the path of the main circuit current.

Each of the first semiconductor elements10A has a first side191, a second side192, a third side193, and a fourth side194in plan view. The first side191and the second side192extend in the y direction. The first side191is an edge located in the x2 direction in plan view, and the second side192is an edge located in the x1 direction in plan view. The third side193and the fourth side194extend in the x direction. The third side193is an edge located in the y2 direction in plan view, and the fourth side194is an edge located in the y1 direction in plan view. Since each of the first semiconductor elements10A has a rectangular shape in plan view, the four corners formed by the first side191, the second side192, the third side193, and the fourth side194are generally right-angled in plan view. The fourth wiring portion624(the first band portion625) of the second conducting member62has a first edge627and a second edge628. The first edge627is an edge of the fourth wiring portion624located in the x2 direction, and is offset in the x1 direction relative to the first side191in plan view. The first edge627extends at least from the third side193to the fourth side194in the y direction. As such, two corners171and172of each first semiconductor element10A in the x2 direction do not overlap with the second conducting member62in plan view. The second edge628is an edge of the fourth wiring portion624(first band portion625) located in the x1 direction, and is offset in the x2 direction relative to the second side192in plan view. The second edge628extends at least from the third side193to the fourth side194in the y direction. As such, two corners173and174of each first semiconductor element10A in the x1 direction do not overlap with the second conducting member62in plan view. With this configuration, the four corners of each of the first semiconductor elements10A in plan view do not overlap with the second conducting member62while the size of the second conducting member62in plan view is increased by providing the fourth wiring portion624with areas that overlap with the first semiconductor elements10A in plan view. This makes it possible to effectively suppress the parasitic resistance components of the second conducting member62(conducting member6), and to conduct visual inspection to check the bonding state of the first semiconductor elements10A during the manufacturing process of the semiconductor module A1.

The fourth wiring portion624(first band portion625) has the protruding areas625aprotruding in the z2 direction relative to the other areas. The protruding areas625aoverlap with the first semiconductor elements10A in plan view. According to the configuration in which the fourth wiring portion624has the protruding areas625a, the fourth wiring portion624is prevented from making improper contact with the first conducting members61bonded to the first semiconductor elements10A.

The third wiring portion623has the recessed areas623arecessed in the z1 direction relative to the other areas. The recessed areas623aare bonded to the respective second semiconductor elements10B. This configuration can increase the size of the third wiring portion623(second conductive member62) in plan view while electrically connecting the third wiring portion623(second conductive member62) and the second semiconductor elements10B in a suitable manner.

The first semiconductor elements10A and the second semiconductor elements10B overlap with each other as viewed in the x direction. This configuration can suppress an increase in the dimension in the y direction of the conductive substrate2(first conductive portion2A and the second conductive portion2B) on which the first semiconductor elements10A and the second semiconductor elements10B are arranged, and can therefore reduce the size of the semiconductor module A1.

The semiconductor module A1includes the conductive substrate2, the two input terminals41and42(or the two input terminals41and43), the output terminals44, and the conducting member6. The conductive substrate2includes the first conductive portion2A and the second conductive portion2B aligned in the x direction in plan view. The first semiconductor elements10A are electrically bonded to the first conductive portion2A. The second semiconductor elements10B are electrically bonded to the second conductive portion2B. The first semiconductor elements10A and the second semiconductor elements10B are arranged at intervals in the y direction. The two input terminals41and42(or the two input terminals41and43) are offset in the x2 direction relative to the first conductive portion2A. The input terminal41is a positive electrode, and is connected to the first conductive portion2A. The input terminal42(or the input terminal43) is a negative electrode. The output terminals44are offset in the x1 direction relative to the second conductive portion2B. The conducting member6includes the first conducting members61connected to the first semiconductor elements10A and the second conductive portion2B, and the second conducting member62connected to the second semiconductor elements10B and the input terminal42(or the input terminal43). According to this configuration, the path of the main circuit current switched by the semiconductor elements10(the first semiconductor elements10A and the second semiconductor elements10B) is formed along the x direction in plan view, and the axis of symmetry (see an auxiliary line Li inFIG.5) in the planar structure of the semiconductor module A1extends along the y direction in plan view. In other words, the axis of symmetry and the path of the main circuit current are perpendicular to each other. This reduces the difference in the current path to the first semiconductor elements10A and the second semiconductor elements10B regarding the main circuit current inputted from the two input terminals41and42(or the two input terminals41and43) and outputted from the output terminals44. Accordingly, it is possible to suppress variations in parasitic inductance components and variations in current in the semiconductor module A1. Accordingly, the semiconductor module A1has a package configuration preferable for equalizing the parasitic inductance components in the path of the main circuit current and for equalizing the amount of current to the semiconductor elements10.

The first semiconductor elements10A and the second semiconductor elements10B are spaced apart in the x direction. The first semiconductor elements10A and the second semiconductor elements10B are aligned along the y direction. Accordingly, the direction in which the semiconductor elements10are aligned is perpendicular to the direction in which the first main circuit current or the second main circuit current flows. In this way, when a plurality of switching elements are connected in parallel for use as in the present embodiment, the difference in the length of the path of the first main circuit current between the three first semiconductor elements10A can be reduced. This makes it possible to suppress the parasitic resistance components in the conducting member6that forms the path of the main circuit current.

The area in which the first main circuit current flows and the area in which the second main circuit current flows overlap with each other in plan view. In other words, the second conducting member62, which connects the output terminals44to the input terminals42and43that are negative electrode terminals to let the second main circuit current flow, is arranged above the area (the first conductive portion2A, the first conducting members61, and the second conductive portion2B) in which the first main circuit current flows. The direction in which the first main circuit current flows is opposite from the direction in which the second main circuit current flows. With the arrangement described above, the magnetic field generated by the first main circuit current and the magnetic field generated by the second main circuit current cancel each other out, thus enabling reduction of inductance.

The semiconductor module A1of the present embodiment includes the two input terminals42and43. The input terminals42and43are negative electrodes and flank the input terminal41in the y direction. The two input terminals42and43are connected to the second conducting member62. This configuration can further reduce variations in the path of a current flowing from the output terminals44to the input terminals42and43via the second semiconductor elements10B and the second conducting member62.

In the semiconductor module A1, the second conducting member62includes the first wiring portion621, the second wiring portion622, the third wiring portion623, and the fourth wiring portion624. The first wiring portion621and the second wiring portion622extend in the x direction, and are respectively connected to the input terminal42and the input terminal43that are arranged opposite from each other with the input terminal41therebetween in the y direction. The third wiring portion623is joined to the first wiring portion621and the second wiring portion622, extends in the y direction, and is connected to the second semiconductor elements10B. The fourth wiring portion624is offset in the x2 direction relative to the third wiring portion623, and is joined to the first wiring portion621, the second wiring portion622, and the third wiring portion623. The second conductive member62including the first wiring portion621, the second wiring portion622, the third wiring portion623, and the fourth wiring portion624overlaps with a wide area of the obverse surface201in plan view, and has a relatively large size in plan view. This configuration can appropriately reduce variations in the path of a current flowing from the output terminals44to the input terminals42and43via the second semiconductor elements10B and the second conducting member62. Accordingly, the semiconductor module A1of the present embodiment is more preferable for equalizing the parasitic inductance components in the path (second conducting member62) of the main circuit current and for equalizing the amount of current to the semiconductor elements10B.

The fourth wiring portion624is joined to the first wiring portion621and the second wiring portion622, and overlaps with the first semiconductor elements10A in plan view. The fourth wiring portion624(first band portion625) has the protruding areas625aprotruding in the z2 direction relative to the other areas. The protruding areas625aoverlap with the first semiconductor elements10A in plan view. This configuration can increase the size of the fourth wiring portion624(second conductive member62) in plan view, and can prevent the fourth wiring portion624from making improper contact with the first conducting members61bonded to the first semiconductor elements10A.

The first semiconductor elements10A and the second semiconductor elements10B overlap with each other as viewed in the x direction. This configuration can suppress an increase in the dimension in the y direction of the conductive substrate2(first conductive portion2A and the second conductive portion2B) on which the first semiconductor elements10A and the second semiconductor elements10B are arranged, and can therefore reduce the size of the semiconductor module A1.

FIGS.30to32illustrate a semiconductor module according to a second embodiment. A semiconductor module A2of the present embodiment is different from the semiconductor module A1of the first embodiment in the configuration of the second conducting member62.

The present embodiment is different from the first embodiment in the area occupied by the fourth wiring portion624of the second conducting member62. Specifically, the dimension of the first band portion625in the x direction is larger than that of the semiconductor module A1. As shown inFIGS.31and32, the second edge628of the first band portion625is offset in the x1 direction as compared to the second edge628in the semiconductor module A1. As shown inFIG.32, the second edge628is offset in the x1 direction relative to the second sides192of the first semiconductor elements10A in plan view. As such, two corners of each first semiconductor element10A in the x1 direction overlap with the second conducting member62(first band portion625) in plan view.

The semiconductor module A2of the present embodiment has the same advantages as the semiconductor module A1of the first embodiment. Furthermore, in the semiconductor module A2, the first band portion625(second conducting member62) of the fourth wiring portion624can have a larger size in plan view. This is more preferable for reducing parasitic inductance components.

FIGS.33and34illustrate a semiconductor module according to a third embodiment. A semiconductor module A3of the present embodiment is different from the semiconductor module A1of the first embodiment mainly in the configuration of the second conducting member62.

Unlike the above embodiments, the second conducting member62of the semiconductor module A3does not have any openings63. The mold91used to form the sealing resin8(by molding) in the manufacturing of the semiconductor module A3is not provided with the pressing pins911. Accordingly, as shown inFIG.34, the sealing resin8is not formed with the resin voids86, and the obverse surface201of the conductive substrate2(the first conductive portion2A and the second conductive portion2B) is not formed with the recessed portions201a. Since the sealing resin8is not formed with the resin voids86, the semiconductor module A3of the present embodiment does not have any resin-filling portions88which are used to fill the resin voids86in the first embodiment.

The semiconductor module A3of the present embodiment has the same advantages as the semiconductor module A1of the first embodiment.

The semiconductor module according to the present disclosure is not limited to the above embodiments. Various design changes can be made to the specific configurations of the elements of the semiconductor module in the present disclosure.

In the above embodiments, the first conductive portion2A and the second conductive portion2B are spaced apart from each other in the x direction, and the first semiconductor elements10A bonded to the first conductive portion2A and the second semiconductor elements10B bonded to the second conductive portion2B are aligned in the y direction. unlike such a configuration, the first conductive portion2A and the second conductive portion2B may be spaced apart from each other in the y direction. In this case, the first semiconductor elements10A bonded to the first conductive portion2A are aligned in the x direction, and the second semiconductor elements10B bonded to the second conductive portion2B are also aligned in the x direction. With this configuration, when the input terminals41to43are offset in the x2 direction relative to the conductive substrate2, and the output terminals44are offset in the x1 direction relative to the conductive substrate2, the upper arm current path in which a current flows from the first conductive portion2A to the second conductive portion2B via the first semiconductor elements10A and the first conducting members61and the lower arm current path in which a current flows from the second conductive portion2B to the second conducting member62via the second semiconductor elements10B align in the y direction. Furthermore, the direction of the current in the upper arm current path is opposite from the direction of the current in the lower arm current path. With this configuration, the magnetic field generated by the current along the upper arm current path and the magnetic field generated by the current along the lower arm current path cancel each other out, thus enabling reduction of parasitic inductance components.

In the above embodiments, the control terminals45(the first control terminals46A to46E, and the second control terminals47A to47D) extend along the z direction, but the present disclosure is not limited to this. For example, the control terminals45may extend along the plane (x-y plane) perpendicular to the z direction.

The present disclosure includes the configurations defined in the following clauses.

Clause 1.

A semiconductor module comprising:a conductive substrate having an obverse surface facing in one sense of a thickness direction, and a reverse surface facing away from the obverse surface in the thickness direction;a plurality of semiconductor elements electrically bonded to the obverse surface and having a switching function;a conducting member that forms a path of a main circuit current switched by the plurality of semiconductor elements;a first input terminal, a second input terminal, and a third input terminal that are offset in one sense of a first direction relative to the conductive substrate, the first direction being perpendicular to the thickness direction; andan output terminal arranged offset in another sense of the first direction relative to the conductive substrate,wherein the conductive substrate includes a first conductive portion and a second conductive portion,the plurality of semiconductor elements include a first semiconductor element electrically bonded to the first conductive portion, and a second semiconductor element electrically bonded to the second conductive portion,the second input terminal and the third input terminal are offset in one sense and another sense respectively of a second direction with the first input terminal disposed therebetween,the second direction being perpendicular to the thickness direction and the first direction,the first input terminal is one of a positive electrode and a negative electrode and electrically connected to the first conductive portion, andeach of the second input terminal and the third input terminal is the other of the positive electrode and the negative electrode.
Clause 2.

The semiconductor module according to clause 1,wherein the first input terminal is electrically connected to the first conductive portion,the output terminal is electrically connected to the second conductive portion, andthe conducting member includes a first conducting member and a second conducting member, the first conducting member being connected to the first semiconductor element and the second conductive portion, and the second conducting member being connected to the second semiconductor element, the second input terminal, and the third input terminal and overlapping with the first semiconductor element as viewed in the thickness direction.
Clause 3.

The semiconductor module according to clause 2,wherein the first conductive portion is offset in the one sense of the first direction, and the second conductive portion is offset in the other sense of the first direction, andthe second conducting member includes a first wiring portion connected to the second input terminal and extending in the first direction, a second wiring portion connected to the third input terminal and extending in the first direction, a third wiring portion connected to the first wiring portion and the second wiring portion, extending in the second direction, and connected to the second semiconductor element, and a fourth wiring portion connected to the first wiring portion and the second wiring portion, offset in the one sense of the first direction relative to the third wiring portion, and overlapping with the first semiconductor element as viewed in the thickness direction.
Clause 4.

The semiconductor module according to clause 3,wherein each of the first semiconductor element and the second semiconductor element includes a source electrode facing in the one sense of the thickness direction, and a drain electrode facing in another sense of the thickness direction,the first conducting member is connected to the source electrode of the first semiconductor element,the first conductive portion is connected to the drain electrode of first semiconductor element,the third wiring portion is connected to the source electrode of the second semiconductor element, andthe second conductive portion is connected to the drain electrode of the second semiconductor element.
Clause 5.

The semiconductor module according to clause 4, wherein the first semiconductor element and the second semiconductor element overlap with each other as viewed in the first direction.

Clause 6.

The semiconductor module according to clause 5,wherein the fourth wiring portion has a first band portion and a second band portion,the first band portion is spaced apart from the third wiring portion in the first direction, is connected to the first wiring portion and the second wiring portion, extends in the second direction, and overlaps with the first semiconductor element as viewed in the thickness direction, andone end of the second band portion is connected to a part of the first band portion between the first semiconductor element and another first semiconductor element adjacent thereto as viewed in the thickness direction, and another end of the second band portion is connected to a part of the third wiring portion between the second semiconductor element and another second semiconductor element adjacent thereto as viewed in the thickness direction.
Clause 7.

The semiconductor module according to clause 6, wherein the first band portion has a protruding area that protrudes in the one sense of the thickness direction relative to other areas of the first band portion, the protruding area overlapping with the first semiconductor element as viewed in the thickness direction.

Clause 8.

The semiconductor module according to any of clauses 3 to 7,wherein the third wiring portion has a recessed area that is recessed in the other sense of the thickness direction relative to other areas of the third wiring portion, andthe recessed area is bonded to the second semiconductor element.
Clause 9.

The semiconductor module according to any of clauses 3 to 8, further comprising a first control terminal and a second control terminal for controlling the first semiconductor element and the second semiconductor element,wherein the first control terminal and the second control terminal are arranged on the obverse surface and extend along the thickness direction.
Clause 10.

The semiconductor module according to clause 9,wherein the first control terminal is supported by the first conductive portion, and is offset in the one sense of the first direction relative to the first semiconductor element, andthe second control terminal is supported by the second conductive portion, and is offset in the other sense of the first direction relative to the second semiconductor element.
Clause 11.

The semiconductor module according to clause 10,wherein each of the first semiconductor element and the second semiconductor element has a gate electrode facing in the one sense of the thickness direction,the first control terminal is connected to the gate electrode of the first semiconductor element via a first wire that is electrically conductive, andthe second control terminal is connected to the gate electrode of the second semiconductor element via a second wire that is electrically conductive.
Clause 12.

The semiconductor module according to any of clauses 1 to 11, wherein the first input terminal, the second input terminal, and the third input terminal overlap with each other as viewed in the second direction.

Clause 13.

The semiconductor module according to any of clauses 1 to 12, wherein the conducting member is made of a metal plate-like member.

Clause 14.

The semiconductor module according to any of clauses 1 to 13,wherein each of the first input terminal, the second input terminal, and the third input terminal has an input-side bonding surface extending in the one sense of the first direction and facing in the one sense of the thickness direction, andthe output terminal has an output-side bonding surface extending in the other sense of the first direction and facing in the one sense of the thickness direction.
Clause 15.

The semiconductor module according to any of clauses 1 to 14,wherein each of the first input terminal, the second input terminal, and the third input terminal has an input-side side surface and an input-side machining mark, the input-side side surface being located at a periphery of the input-side bonding surface as viewed in the thickness direction and facing in a direction intersecting with the input-side bonding surface, the input-side machining mark being formed on the input-side side surface, andthe output terminal has an output-side side surface located at a periphery of the output-side bonding surface as viewed in the thickness direction and facing in a direction intersecting with the output-side bonding surface, and an output-side machining mark formed on the output-side side surface.
Clause 16.

The semiconductor module according to any of clauses 1 to 15, further comprising a sealing resin covering at least a part of the conductive substrate, the plurality of semiconductor elements, and the conducting member.

Clause 17.

The semiconductor module according to any of clauses 3 to 12, further comprising:a plurality of the first semiconductor elements arranged at intervals in the second direction; anda plurality of the second semiconductor elements arranged at intervals in the second direction.
Clause 18.

A semiconductor module comprising:a conductive substrate having an obverse surface facing in one sense of a thickness direction, and a reverse surface facing away from the obverse surface in the thickness direction;a plurality of semiconductor elements electrically bonded to the obverse surface and having a switching function;a conducting member that forms a path of a main circuit current switched by the plurality of semiconductor elements, and that is spaced apart from the obverse surface in one sense of the thickness direction;a first input terminal, a second input terminal, and a third input terminal that are offset in one sense of a first direction relative to the conductive substrate, the first direction being perpendicular to the thickness direction; andan output terminal arranged offset in another sense of the first direction relative to the conductive substrate,wherein the conductive substrate includes a first conductive portion and a second conductive portion that are spaced apart from each other as viewed in the thickness direction,the plurality of semiconductor elements include a plurality of first semiconductor elements electrically bonded to the first conductive portion, and a plurality of second semiconductor elements electrically bonded to the second conductive portion,the second input terminal and the third input terminal are offset in one sense and another sense respectively of a second direction with the first input terminal disposed therebetween, the second direction being perpendicular to the thickness direction and the first direction,the first input terminal is joined to the first conductive portion,the output terminal is joined to the second conductive portion, andthe conducting member includes a first conducting member and a second conducting member, the first conducting member being connected to the plurality of first semiconductor elements and the second conductive portion, the second conducting member being connected to the plurality of second semiconductor elements, the second input terminal, and the third input terminal and overlapping with the plurality of first semiconductor elements as viewed in the thickness direction.
Clause 19.

The semiconductor module according to clause 18,wherein the first conductive portion is offset in the one sense of the first direction, and the second conductive portion is offset in the other sense of the first direction,the plurality of first semiconductor elements and the plurality of second semiconductor elements are arranged at intervals along the second direction,the second conducting member includes a first wiring portion connected to the second input terminal and extending in the first direction, a second wiring portion connected to the third input terminal and extending in the first direction, a third wiring portion connected to the first wiring portion and the second wiring portion, extending in the second direction, and connected to the plurality of second semiconductor elements, and a fourth wiring portion connected to the first wiring portion and the second wiring portion, offset in the one sense of the first direction relative to the third wiring portion, and overlapping with the plurality of first semiconductor elements as viewed in the thickness direction.
Clause 20.

The semiconductor module according to clause 19,wherein each of the plurality of first semiconductor elements and the plurality of second semiconductor elements includes a source electrode facing in the one sense of the thickness direction, and a drain electrode facing in another sense of the thickness direction,the first conducting member is connected to the source electrodes of the plurality of first semiconductor elements,the first conductive portion is connected to the drain electrodes of the plurality of first semiconductor elements,the third wiring portion is connected to the source electrodes of the plurality of second semiconductor elements, andthe second conductive portion is connected to the drain electrodes of the plurality of second semiconductor elements.
Clause 21.

The semiconductor module according to clause 20, wherein the plurality of first semiconductor elements and the plurality of second semiconductor elements overlap with each other as viewed in the first direction.

Clause 22.

The semiconductor module according to clause 21,wherein the fourth wiring portion has a first band portion and a second band portion,the first band portion is spaced apart from the third wiring portion in the first direction, is connected to the first wiring portion and the second wiring portion, extends in the second direction, and overlaps with the plurality of first semiconductor elements as viewed in the thickness direction, andone end of the second band portion is connected to a part of the first band portion between an adjacent pair of the plurality of first semiconductor elements as viewed in the thickness direction, and another end of the second band portion is connected to a part of the third wiring portion between an adjacent pair of the plurality of second semiconductor elements.
Clause 23.

The semiconductor module according to clause 22, wherein the first band portion overlaps with the plurality of first semiconductor elements as viewed in the thickness direction, and has a plurality of protruding areas that protrude in the one sense of the thickness direction relative to other areas of the first band portion.

Clause 24.

The semiconductor module according to any of clauses 19 to 23,wherein the third wiring portion has a plurality of recessed areas that are recessed in the other sense of the thickness direction relative to other areas of the third wiring portion, andthe plurality of recessed areas are respectively bonded to the plurality of second semiconductor elements.
Clause 25.

The semiconductor module according to any of clauses 19 to 24, further comprising a plurality of first control terminals and a plurality of second control terminals for controlling the plurality of first semiconductor elements and the plurality of second semiconductor elements,wherein the plurality of first control terminals and the plurality of second control terminals are arranged on the obverse surface and extend along the thickness direction.
Clause 26.

The semiconductor module according to clause 25,wherein the plurality of first control terminals are supported by the first conductive portion, are offset in the one sense of the first direction relative to the plurality of first semiconductor elements, and are arranged at intervals in the second direction, andthe plurality of second control terminals are supported by the second conductive portion, are offset in the other sense of the first direction relative to the plurality of second semiconductor elements, and are arranged at intervals in the second direction.
Clause 27.

The semiconductor module according to clause 26, wherein each of the plurality of first semiconductor elements and the plurality of second semiconductor elements has a gate electrode facing in the one sense of the thickness direction,one of the plurality of first control terminals is connected to the gate electrodes of the plurality of first semiconductor elements via a plurality of first wires that are electrically conductive, andone of the plurality of second control terminals is connected to the gate electrodes of the plurality of second semiconductor elements via a plurality of second wires that are electrically conductive.
Clause 28.

The semiconductor module according to any of clauses 18 to 27, wherein the first input terminal, the second input terminal, and the third input terminal overlap with each other as viewed in the second direction.

Clause 29.

The semiconductor module according to any of clauses 18 to 28, wherein each of the first conducting member and the second conducting member is made of a metal plate-like member.

REFERENCE NUMERALS

A1, A2, A3: Semiconductor Module10: Semiconductor Element10A: First Semiconductor Element10B: Second Semiconductor Element101: Element Obverse Surface102: Element Reverse Surface11: First Obverse-Surface Electrode (Gate Electrode)12: Second Obverse-Surface Electrode (Source Electrode)13: Third Obverse-Surface Electrode14: Fourth Obverse-Surface Electrode15: Reverse-Surface Electrode (Drain Electrode)16: Fifth Obverse-Surface Electrode171,172,173,174,181,182,183,184: Corner191: First Side192: Second Side193: Third Side194: Fourth Side2: Conductive Substrate2A: First Conductive Portion2B: Second Conductive Portion201: Obverse Surface201a: Recessed Portion201b: Recess Edge202: Reverse Surface21: Base Member22: Obverse-Surface Bonding Layer23: Reverse-Surface Bonding Layer3: Supporting Substrate301: Supporting Surface302: Bottom Surface31: Insulating Layer32: First Metal Layer32A: First Portion32B: Second Portion321: First Bonding Layer33: Second Metal Layer41: Input Terminal (First Input Terminal)411: Input-Side Bonding Surface412: Input-Side Side Surface413: Tip Surface414: Lateral Surface42: Input Terminal (Second Input Terminal)421: Input-Side Bonding Surface422: Input-Side Side Surface423: Tip Surface424: Lateral Surface43: Input Terminal (Third Input Terminal)431: Input-Side Bonding Surface432: Input-Side Side Surface433: Tip Surface434: Lateral Surface44: Output Terminal441: Output-Side Bonding Surface442: Output-Side Side Surface443: Tip Surface444: Lateral Surface45: Control Terminal451: Holder452: Metal Pin459: Conductive Bonding Member46A,46B,46C,46D,46E: First Control Terminal47A,47B,47C,47D: Second Control Terminal5: Control Terminal Support51: Insulating Layer52: First Metal Layer521: First Portion522: Second Portion523: Third Portion524: Fourth Portion525: Fifth Portion53: Second Metal Layer59: Bonding Member6: Conducting Member601: First Portion61: First Conducting Member61h: Opening62: Second Conducting Member62A: First Portion62B: Second Portion621: First Wiring Portion622: Second Wiring Portion623: Third Wiring Portion623a: Recessed Area623h: Opening624: Fourth Wiring Portion625: First Band portion625a: Protruding Area625h: Opening626: Second Band portion627: First Edge628: Second Edge63: Opening69: Conductive Bonding Member71: First Conductive Bonding Member711: First Base Layer712: First Layer713: Second Layer72: Second Conductive Bonding Member721: Second Base Layer722: Third Layer723: Fourth Layer731: Wire (for connection between gate electrode and first metal layer)731a: First Wire731b: Second Wire732,733,734,735: Wire8: Sealing Resin81: Resin Obverse Surface82: Resin Reverse Surface831,832: Resin Side Surface832a: Recessed Portion833,834: Resin Side Surface851: First Protrusion (Protrusion)851a: First Protruding End Surface (Protruding End Surface)851b: Recessed Portion851c: Inner Wall Surface852: Second Protrusion86: Resin Void861: Resin Void Edge87: Resin Member88: Resin-Filling Portion91: Mold911: Pressing Pin