Patent ID: 12197334

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG.1illustrates a dual scalar/vector datapath processor according to a preferred embodiment of this invention. Processor100includes separate level one instruction cache (L1I)121and level one data cache (L1D)123. Processor100includes a level two combined instruction/data cache (L2)130that holds both instructions and data.FIG.1illustrates connection between level one instruction cache121and level two combined instruction/data cache130(bus142).FIG.1illustrates connection between level one data cache123and level two combined instruction/data cache130(bus145). In the preferred embodiment of processor100level two combined instruction/data cache130stores both instructions to back up level one instruction cache121and data to back up level one data cache123. In the preferred embodiment level two combined instruction/data cache130is further connected to higher level cache and/or main memory in a manner known in the art and not illustrated inFIG.1. In the preferred embodiment central processing unit core110, level one instruction cache121, level one data cache123and level two combined instruction/data cache130are formed on a single integrated circuit. This signal integrated circuit optionally includes other circuits.

Central processing unit core110fetches instructions from level one instruction cache121as controlled by instruction fetch unit111. Instruction fetch unit111determines the next instructions to be executed and recalls a fetch packet sized set of such instructions. The nature and size of fetch packets are further detailed below. As known in the art, instructions are directly fetched from level one instruction cache121upon a cache hit (if these instructions are stored in level one instruction cache121). Upon a cache miss (the specified instruction fetch packet is not stored in level one instruction cache121), these instructions are sought in level two combined instruction/data cache130. In the preferred embodiment the size of a cache line in level one instruction cache121equals the size of a fetch packet. The memory locations of these instructions are either a hit in level two combined instruction/data cache130or a miss. A hit is serviced from level two combined instruction/data cache130. A miss is serviced from a higher level of cache (not illustrated) or from main memory (not illustrated). As is known in the art, the requested instruction may be simultaneously supplied to both level one instruction cache121and central processing unit core110to speed use.

In the preferred embodiment of this invention, central processing unit core110includes plural functional units to perform instruction specified data processing tasks. Instruction dispatch unit112determines the target functional unit of each fetched instruction. In the preferred embodiment central processing unit110operates as a very long instruction word (VLIW) processor capable of operating on plural instructions in corresponding functional units simultaneously. Preferably a complier organizes instructions in execute packets that are executed together. Instruction dispatch unit112directs each instruction to its target functional unit. The functional unit assigned to an instruction is completely specified by the instruction produced by a compiler. The hardware of central processing unit core110has no part in this functional unit assignment. In the preferred embodiment instruction dispatch unit112may operate on plural instructions in parallel. The number of such parallel instructions is set by the size of the execute packet. This will be further detailed below.

One part of the dispatch task of instruction dispatch unit112is determining whether the instruction is to execute on a functional unit in scalar datapath side A115or vector datapath side B116. An instruction bit within each instruction called the s bit determines which datapath the instruction controls. This will be further detailed below.

Instruction decode unit113decodes each instruction in a current execute packet. Decoding includes identification of the functional unit performing the instruction, identification of registers used to supply data for the corresponding data processing operation from among possible register files and identification of the register destination of the results of the corresponding data processing operation. As further explained below, instructions may include a constant field in place of one register number operand field. The result of this decoding is signals for control of the target functional unit to perform the data processing operation specified by the corresponding instruction on the specified data.

Central processing unit core110includes control registers114. Control registers114store information for control of the functional units in scalar datapath side A115and vector datapath side B116in a manner not relevant to this invention. This information could be mode information or the like.

The decoded instructions from instruction decode113and information stored in control registers114are supplied to scalar datapath side A115and vector datapath side B116. As a result functional units within scalar datapath side A115and vector datapath side B116perform instruction specified data processing operations upon instruction specified data and store the results in an instruction specified data register or registers. Each of scalar datapath side A115and vector datapath side B116include plural functional units that preferably operate in parallel. These will be further detailed below in conjunction withFIG.2. There is a datapath117between scalar datapath side A115and vector datapath side B116permitting data exchange.

Central processing unit core110includes further non-instruction based modules. Emulation unit118permits determination of the machine state of central processing unit core110in response to instructions. This capability will typically be employed for algorithmic development. Interrupts/exceptions unit119enable central processing unit core110to be responsive to external, asynchronous events (interrupts) and to respond to attempts to perform improper operations (exceptions).

Central processing unit core110includes streaming engine125. Streaming engine125supplies two data streams from predetermined addresses typically cached in level two combined instruction/data cache130to register files of vector datapath side B. This provides controlled data movement from memory (as cached in level two combined instruction/data cache130) directly to functional unit operand inputs. This is further detailed below.

FIG.1illustrates exemplary data widths of busses between various parts. Level one instruction cache121supplies instructions to instruction fetch unit111via bus141. Bus141is preferably a 512-bit bus. Bus141is unidirectional from level one instruction cache121to central processing unit core110. Level two combined instruction/data cache130supplies instructions to level one instruction cache121via bus142. Bus142is preferably a 512-bit bus. Bus142is unidirectional from level two combined instruction/data cache130to level one instruction cache121.

Level one data cache123exchanges data with register files in scalar datapath side A115via bus143. Bus143is preferably a 64-bit bus. Level one data cache123exchanges data with register files in vector datapath side B116via bus144. Bus144is preferably a 512-bit bus. Busses143and144are illustrated as bidirectional supporting both central processing unit core110data reads and data writes. Level one data cache123exchanges data with level two combined instruction/data cache130via bus145. Bus145is preferably a 512-bit bus. Bus145is illustrated as bidirectional supporting cache service for both central processing unit core110data reads and data writes.

As known in the art, CPU data requests are directly fetched from level one data cache123upon a cache hit (if the requested data is stored in level one data cache123). Upon a cache miss (the specified data is not stored in level one data cache123), this data is sought in level two combined instruction/data cache130. The memory locations of this requested data is either a hit in level two combined instruction/data cache130or a miss. A hit is serviced from level two combined instruction/data cache130. A miss is serviced from another level of cache (not illustrated) or from main memory (not illustrated). As is known in the art, the requested instruction may be simultaneously supplied to both level one data cache123and central processing unit core110to speed use.

Level two combined instruction/data cache130supplies data of a first data stream to streaming engine125via bus146. Bus146is preferably a 512-bit bus. Streaming engine125supplies data of this first data stream to functional units of vector datapath side B116via bus147. Bus147is preferably a 512-bit bus. Level two combined instruction/data cache130supplies data of a second data stream to streaming engine125via bus148. Bus148is preferably a 512-bit bus. Streaming engine125supplies data of this second data stream to functional units of vector datapath side B116via bus149. Bus149is preferably a 512-bit bus. Busses146,147,148and149are illustrated as unidirectional from level two combined instruction/data cache130to streaming engine125and to vector datapath side B116in accordance with the preferred embodiment of this invention.

Steaming engine data requests are directly fetched from level two combined instruction/data cache130upon a cache hit (if the requested data is stored in level two combined instruction/data cache130). Upon a cache miss (the specified data is not stored in level two combined instruction/data cache130), this data is sought from another level of cache (not illustrated) or from main memory (not illustrated). It is technically feasible in some embodiments for level one data cache123to cache data not stored in level two combined instruction/data cache130. If such operation is supported, then upon a streaming engine data request that is a miss in level two combined instruction/data cache130, level two combined instruction/data cache130should snoop level one data cache123for the stream engine requested data. If level one data cache123stores this data its snoop response would include the data, which is then supplied to service the streaming engine request. If level one data cache123does not store this data its snoop response would indicate this and level two combined instruction/data cache130must service this streaming engine request from another level of cache (not illustrated) or from main memory (not illustrated).

In the preferred embodiment of this invention, both level one data cache123and level two combined instruction/data cache130may be configured as selected amounts of cache or directly addressable memory in accordance with U.S. Pat. No. 6,606,686 entitled UNIFIED MEMORY SYSTEM ARCHITECTURE INCLUDING CACHE AND DIRECTLY ADDRESSABLE STATIC RANDOM ACCESS MEMORY.

FIG.2illustrates further details of functional units and register files within scalar datapath side A115and vector datapath side B116. Scalar datapath side A115includes global scalar register file211, L1/S1 local register file212, M1/N1 local register file213and D1/D2 local register file214. Scalar datapath side A115includes L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226. Vector datapath side B116includes global scalar register file231, L2/S2 local register file232, M2/N2/C local register file233and predicate register file234. Vector datapath side B116includes L2 unit241, S2 unit242, M2 unit243, N2 unit244, C unit245and P unit246. There are limitations upon which functional units may read from or write to which register files. These will be detailed below.

Scalar datapath side A115includes L1 unit221. L1 unit221generally accepts two 64-bit operands and produces one 64-bit result. The two operands are each recalled from an instruction specified register in either global scalar register file211or L1/S1 local register file212. L1 unit221preferably performs the following instruction selected operations: 64-bit add/subtract operations; 32-bit min/max operations; 8-bit Single Instruction Multiple Data (SIMD) instructions such as sum of absolute value, minimum and maximum determinations; circular min/max operations; and various move operations between register files. The result may be written into an instruction specified register of global scalar register file211, L1/S1 local register file212, M1/N1 local register file213or D1/D2 local register file214.

Scalar datapath side A115includes S1 unit222. S1 unit222generally accepts two 64-bit operands and produces one 64-bit result. The two operands are each recalled from an instruction specified register in either global scalar register file211or L1/S1 local register file212. S1 unit222preferably performs the same type operations as L1 unit221. There optionally may be slight variations between the data processing operations supported by L1 unit221and S1 unit222. The result may be written into an instruction specified register of global scalar register file211, L1/S1 local register file212, M1/N1 local register file213or D1/D2 local register file214.

Scalar datapath side A115includes M1 unit223. M1 unit223generally accepts two 64-bit operands and produces one 64-bit result. The two operands are each recalled from an instruction specified register in either global scalar register file211or M1/N1 local register file213. M1 unit223preferably performs the following instruction selected operations: 8-bit multiply operations; complex dot product operations; 32-bit bit count operations; complex conjugate multiply operations; and bit-wise Logical Operations, moves, adds and subtracts. The result may be written into an instruction specified register of global scalar register file211, L1/S1 local register file212, M1/N1 local register file213or D1/D2 local register file214.

Scalar datapath side A115includes N1 unit224. N1 unit224generally accepts two 64-bit operands and produces one 64-bit result. The two operands are each recalled from an instruction specified register in either global scalar register file211or M1/N1 local register file213. N1 unit224preferably performs the same type operations as M1 unit223. There may be certain double operations (called dual issued instructions) that employ both the M1 unit223and the N1 unit224together. The result may be written into an instruction specified register of global scalar register file211, L1/S1 local register file212, M1/N1 local register file213or D1/D2 local register file214.

Scalar datapath side A115includes D1 unit225and D2 unit226. D1 unit225and D2 unit226generally each accept two 64-bit operands and each produce one 64-bit result. D1 unit225and D2 unit226generally perform address calculations and corresponding load and store operations. D1 unit225is used for scalar loads and stores of 64 bits. D2 unit226is used for vector loads and stores of 512 bits. D1 unit225and D2 unit226preferably also perform: swapping, pack and unpack on the load and store data; 64-bit SIMD arithmetic operations; and 64-bit bit-wise logical operations. D1/D2 local register file214will generally store base and offset addresses used in address calculations for the corresponding loads and stores. The two operands are each recalled from an instruction specified register in either global scalar register file211or D1/D2 local register file214. The calculated result may be written into an instruction specified register of global scalar register file211, L1/S1 local register file212, M1/N1 local register file213or D1/D2 local register file214.

Vector datapath side B116includes L2 unit241. L2 unit221generally accepts two 512-bit operands and produces one 512-bit result. The two operands are each recalled from an instruction specified register in either global vector register file231, L2/S2 local register file232or predicate register file234. L2 unit241preferably performs instruction similar to L1 unit221except on wider 512-bit data. The result may be written into an instruction specified register of global vector register file231, L2/S2 local register file222, M2/N2/C local register file233or predicate register file234.

Vector datapath side B116includes S2 unit242. S2 unit242generally accepts two 512-bit operands and produces one 512-bit result. The two operands are each recalled from an instruction specified register in either global vector register file231, L2/S2 local register file232or predicate register file234. S2 unit242preferably performs instructions similar to S1 unit222except on wider 512-bit data. The result may be written into an instruction specified register of global vector register file231, L2/S2 local register file222, M2/N2/C local register file233or predicate register file234.

Vector datapath side B116includes M2 unit243. M2 unit243generally accepts two 512-bit operands and produces one 512-bit result. The two operands are each recalled from an instruction specified register in either global vector register file231or M2/N2/C local register file233. M2 unit243preferably performs instructions similar to M1 unit222except on wider 512-bit data. The result may be written into an instruction specified register of global vector register file231, L2/S2 local register file232or M2/N2/C local register file233.

Vector datapath side B116includes N2 unit244. N2 unit244generally accepts two 512-bit operands and produces one 512-bit result. The two operands are each recalled from an instruction specified register in either global vector register file231or M2/N2/C local register file233. N2 unit244preferably performs the same type operations as M2 unit243. There may be certain double operations (called dual issued instructions) that employ both M2 unit243and the N2 unit244together. The result may be written into an instruction specified register of global vector register file231, L2/S2 local register file232or M2/N2/C local register file233.

Vector datapath side B116includes C unit245. C unit245generally accepts two 512-bit operands and produces one 512-bit result. The two operands are each recalled from an instruction specified register in either global vector register file231or M2/N2/C local register file233. C unit245preferably performs: “Rake” and “Search” instructions; up to 512 2-bit PN*8-bit multiplies I/Q complex multiplies per clock cycle; 8-bit and 16-bit Sum-of-Absolute-Difference (SAD) calculations, up to 512 SADs per clock cycle; horizontal add and horizontal min/max instructions; and vector permutes instructions. C unit245includes also contains 4 vector control registers (CUCR0to CUCR3) used to control certain operations of C unit245instructions. Control registers CUCR0to CUCR3are used as operands in certain C unit245operations. Control registers CUCR0to CUCR3are preferably used: in control of a general permutation instruction (VPERM); and as masks for SIMD multiple DOT product operations (DOTPM) and SIMD multiple Sum-of-Absolute-Difference (SAD) operations. Control register CUCR0is preferably used to store the polynomials for Galios Field Multiply operations (GFMPY). Control register CUCR1is preferably used to store the Galois field polynomial generator function.

Vector datapath side B116includes P unit246. P unit246performs basic logic operations on registers of local predicate register file234. P unit246has direct access to read from and write to predication register file234. These operations include AND, ANDN, OR, XOR, NOR, BITR, NEG, SET, BITCNT, RMBD, BIT Decimate and Expand. A commonly expected use of P unit246includes manipulation of the SIMD vector comparison results for use in control of a further SIMD vector operation.

FIG.3illustrates global scalar register file211. There are 16 independent 64-bit wide scalar registers designated A0to A15. Each register of global scalar register file211can be read from or written to as 64-bits of scalar data. All scalar datapath side A115functional units (L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226) can read or write to global scalar register file211. Global scalar register file211may be read as 32-bits or as 64-bits and may only be written to as 64-bits. The instruction executing determines the read data size. Vector datapath side B116functional units (L2 unit241, S2 unit242, M2 unit243, N2 unit244, C unit245and P unit246) can read from global scalar register file211via crosspath117under restrictions that will be detailed below.

FIG.4illustrates D1/D2 local register file214. There are 16 independent 64-bit wide scalar registers designated D0 to D16. Each register of D1/D2 local register file214can be read from or written to as 64-bits of scalar data. All scalar datapath side A115functional units (L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226) can write to global scalar register file211. Only D1 unit225and D2 unit226can read from D1/D1 local scalar register file214. It is expected that data stored in D1/D2 local scalar register file214will include base addresses and offset addresses used in address calculation.

FIG.5illustrates L1/S1 local register file212. The embodiment illustrated inFIG.5has 8 independent 64-bit wide scalar registers designated AL0to AL7. The preferred instruction coding (seeFIG.13) permits L1/S1 local register file212to include up to 16 registers. The embodiment ofFIG.5implements only 8 registers to reduce circuit size and complexity. Each register of L1/S1 local register file212can be read from or written to as 64-bits of scalar data. All scalar datapath side A115functional units (L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226) can write to L1/S1 local scalar register file212. Only L1 unit221and S1 unit222can read from L1/S1 local scalar register file212.

FIG.6illustrates M1/N1 local register file213. The embodiment illustrated inFIG.6has 8 independent 64-bit wide scalar registers designated AM0to AM7. The preferred instruction coding (seeFIG.13) permits M1/N1 local register file213to include up to 16 registers. The embodiment ofFIG.6implements only 8 registers to reduce circuit size and complexity. Each register of M1/N1 local register file213can be read from or written to as 64-bits of scalar data. All scalar datapath side A115functional units (L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226) can write to M1/N1 local scalar register file213. Only M1 unit223and N1 unit224can read from M1/N1 local scalar register file213.

FIG.7illustrates global vector register file231. There are 16 independent 512-bit wide vector registers. Each register of global vector register file231can be read from or written to as 64-bits of scalar data designated B0to B15. Each register of global vector register file231can be read from or written to as 512-bits of vector data designated VB0to VB15. The instruction type determines the data size. All vector datapath side B116functional units (L2 unit241, S2 unit242, M3 unit243, N2 unit244, C unit245and P unit246) can read or write to global scalar register file231. Scalar datapath side A115functional units (L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226) can read from global vector register file231via crosspath117under restrictions that will be detailed below.

FIG.8illustrates P local register file234. There are 8 independent 64-bit wide registers designated P0to P15. Each register of P local register file234can be read from or written to as 64-bits of scalar data. Vector datapath side B116functional units L2 unit241, S2 unit242, C unit244and P unit246can write to P local register file234. Only L2 unit241, S2 unit242and P unit246can read from P local scalar register file234. A commonly expected use of P local register file234includes: writing one bit SIMD vector comparison results from L2 unit241, S2 unit242or C unit244; manipulation of the SIMD vector comparison results by P unit246; and use of the manipulated results in control of a further SIMD vector operation.

FIG.9illustrates L2/S2 local register file232. The embodiment illustrated inFIG.9has 8 independent 512-bit wide vector registers. The preferred instruction coding (seeFIG.13) permits L2/S2 local register file232to include up to 16 registers. The embodiment ofFIG.9implements only 8 registers to reduce circuit size and complexity. Each register of L2/S2 local vector register file232can be read from or written to as 64-bits of scalar data designated BL0to BL7. Each register of L2/S2 local vector register file232can be read from or written to as 512-bits of vector data designated VBL0to VBL7. The instruction type determines the data size. All vector datapath side B116functional units (L2 unit241, S2 unit242, M2 unit233, N2 unit24, C unit245and P unit246) can write to L2/S2 local vector register file232. Only L2 unit241and S2 unit242can read from L2/S2 local vector register file232.

FIG.10illustrates M2/N2/C local register file233. The embodiment illustrated inFIG.10has 8 independent 512-bit wide vector registers. The preferred instruction coding (seeFIG.13) permits L1/S1 local register file212to include up to 16 registers. The embodiment ofFIG.10implements only 8 registers to reduce circuit size and complexity. Each register of M2/N2/C local vector register file233can be read from or written to as 64-bits of scalar data designated BM0to BM7. Each register of M2/N2/C local vector register file233can be read from or written to as 512-bits of vector data designated VBM0to VBM7. All vector datapath side B116functional units (L2 unit241, S2 unit242, M2 unit243, N2 unit244, C unit245and P unit246) can write to M2/N2/C local vector register file233. Only M2 unit233, N2 unit244and C unit245can read from M2/N2/C local vector register file233.

The provision of global register files accessible by all functional units of a side and local register files accessible by only some of the functional units of a side is a design choice. This invention could be practiced employing only one type of register file corresponding to the disclosed global register files.

Crosspath117permits limited exchange of data between scalar datapath side A115and vector datapath side B116. During each operational cycle one 64-bit data word can be recalled from global scalar register file A211for use as an operand by one or more functional units of vector datapath side B116and one 64-bit data word can be recalled from global vector register file231for use as an operand by one or more functional units of scalar datapath side A115. Any scalar datapath side A115functional unit (L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226) may read a 64-bit operand from global vector register file231. This 64-bit operand is the least significant bits of the 512-bit data in the accessed register of global vector register file232. Plural scalar datapath side A115functional units may employ the same 64-bit crosspath data as an operand during the same operational cycle. However, only one 64-bit operand is transferred from vector datapath side B116to scalar datapath side A115in any single operational cycle. Any vector datapath side B116functional unit (L2 unit241, S2 unit242, M2 unit243, N2 unit244, C unit245and P unit246) may read a 64-bit operand from global scalar register file211. If the corresponding instruction is a scalar instruction, the crosspath operand data is treated as any other 64-bit operand. If the corresponding instruction is a vector instruction, the upper 448 bits of the operand are zero filled. Plural vector datapath side B116functional units may employ the same 64-bit crosspath data as an operand during the same operational cycle. Only one 64-bit operand is transferred from scalar datapath side A115to vector datapath side B116in any single operational cycle.

Streaming engine125transfers data in certain restricted circumstances. Streaming engine125controls two data streams. A stream consists of a sequence of elements of a particular type. Programs that operate on streams read the data sequentially, operating on each element in turn. Every stream has the following basic properties. The stream data have a well-defined beginning and ending in time. The stream data have fixed element size and type throughout the stream. The stream data have fixed sequence of elements. Thus programs cannot seek randomly within the stream. The stream data is read-only while active. Programs cannot write to a stream while simultaneously reading from it. Once a stream is opened streaming engine125: calculates the address; fetches the defined data type from level two combined instruction/data cache130(which may require cache service from a higher level memory); performs data type manipulation such as zero extension, sign extension, data element sorting/swapping such as matrix transposition; and delivers the data directly to the programmed data register file within central processing unit core110. Streaming engine125is thus useful for real-time digital filtering operations on well-behaved data. Streaming engine125frees these memory fetch tasks from the corresponding CPU enabling other processing functions.

Streaming engine125provides the following benefits. Streaming engine125permits multi-dimensional memory accesses. Streaming engine125increases the available bandwidth to the functional units. Streaming engine125minimizes the number of cache miss stalls since the stream buffer bypasses level one data cache123. Streaming engine125reduces the number of scalar operations required to maintain a loop. Streaming engine125manages address pointers. Streaming engine125handles address generation automatically freeing up the address generation instruction slots and D1 unit224and D2 unit226for other computations.

Central processing unit core110operates on an instruction pipeline. Instructions are fetched in instruction packets of fixed length further described below. All instructions require the same number of pipeline phases for fetch and decode, but require a varying number of execute phases.

FIG.11illustrates the following pipeline phases: program fetch phase1110, dispatch and decode phases1110and execution phases1130. Program fetch phase1110includes three stages for all instructions. Dispatch and decode phases include three stages for all instructions. Execution phase1130includes one to four stages dependent on the instruction.

Fetch phase1110includes program address generation stage1111(PG), program access stage1112(PA) and program receive stage1113(PR). During program address generation stage1111(PG), the program address is generated in the CPU and the read request is sent to the memory controller for the level one instruction cache121. During the program access stage1112(PA) the level one instruction cache121processes the request, accesses the data in its memory and sends a fetch packet to the CPU boundary. During the program receive stage1113(PR) the CPU registers the fetch packet.

Instructions are always fetched sixteen 32-bit wide slots, constituting a fetch packet, at a time.FIG.12illustrates 16 instructions1201to1216of a single fetch packet. Fetch packets are aligned on 512-bit (16-word) boundaries. The preferred embodiment employs a fixed 32-bit instruction length. Fixed length instructions are advantageous for several reasons. Fixed length instructions enable easy decoder alignment. A properly aligned instruction fetch can load plural instructions into parallel instruction decoders. Such a properly aligned instruction fetch can be achieved by predetermined instruction alignment when stored in memory (fetch packets aligned on 512-bit boundaries) coupled with a fixed instruction packet fetch. An aligned instruction fetch permits operation of parallel decoders on instruction-sized fetched bits. Variable length instructions require an initial step of locating each instruction boundary before they can be decoded. A fixed length instruction set generally permits more regular layout of instruction fields. This simplifies the construction of each decoder which is an advantage for a wide issue VLIW central processor.

The execution of the individual instructions is partially controlled by a p bit in each instruction. This p bit is preferably bit0of the 32-bit wide slot. The p bit determines whether an instruction executes in parallel with a next instruction. Instructions are scanned from lower to higher address. If the p bit of an instruction is 1, then the next following instruction (higher memory address) is executed in parallel with (in the same cycle as) that instruction. If the p bit of an instruction is 0, then the next following instruction is executed in the cycle after the instruction.

Central processing unit core110and level one instruction cache121pipelines are de-coupled from each other. Fetch packet returns from level one instruction cache121can take different number of clock cycles, depending on external circumstances such as whether there is a hit in level one instruction cache121or a hit in level two combined instruction/data cache130. Therefore program access stage1112(PA) can take several clock cycles instead of 1 clock cycle as in the other stages.

The instructions executing in parallel constitute an execute packet. In the preferred embodiment an execute packet can contain up to sixteen instructions. No two instructions in an execute packet may use the same functional unit. A slot is one of five types: 1) a self-contained instruction executed on one of the functional units of central processing unit core110(L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225, D2 unit226, L2 unit241, S2 unit242, M2 unit243, N2 unit244, C unit245and P unit246); 2) a unitless instruction such as a NOP (no operation) instruction or multiple NOP instruction; 3) a branch instruction; 4) a constant field extension; and 5) a conditional code extension. Some of these slot types will be further explained below.

Dispatch and decode phases1110include instruction dispatch to appropriate execution unit stage1121(DS), instruction pre-decode stage1122(D1); and instruction decode, operand reads stage1222(D2). During instruction dispatch to appropriate execution unit stage1121(DS) the fetch packets are split into execute packets and assigned to the appropriate functional units. During the instruction pre-decode stage1122(D1) the source registers, destination registers and associated paths are decoded for the execution of the instructions in the functional units. During the instruction decode, operand reads stage1222(D2) more detail unit decodes are done, as well as reading operands from the register files.

Execution phases1130includes execution stages1131to1135(E1to E5). Different types of instructions require different numbers of these stages to complete their execution. These stages of the pipeline play an important role in understanding the device state at CPU cycle boundaries.

During execute1stage1131(E1) the conditions for the instructions are evaluated and operands are operated on. As illustrated inFIG.11, execute1stage1131may receive operands from a stream buffer1141and one of the register files shown schematically as1142. For load and store instructions, address generation is performed and address modifications are written to a register file. For branch instructions, branch fetch packet in PG phase is affected. As illustrated inFIG.11, load and store instructions access memory here shown schematically as memory1151. For single-cycle instructions, results are written to a destination register file. This assumes that any conditions for the instructions are evaluated as true. If a condition is evaluated as false, the instruction does not write any results or have any pipeline operation after execute1stage1131.

During execute2stage1132(E2) load instructions send the address to memory. Store instructions send the address and data to memory. Single-cycle instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For 2-cycle instructions, results are written to a destination register file.

During execute3stage1133(E3) data memory accesses are performed. Any multiply instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For 3-cycle instructions, results are written to a destination register file.

During execute4stage1134(E4) load instructions bring data to the CPU boundary. For 4-cycle instructions, results are written to a destination register file.

During execute5stage1135(E5) load instructions write data into a register. This is illustrated schematically inFIG.11with input from memory1151to execute5stage1135.

FIG.13illustrates an example of the instruction coding1300of functional unit instructions used by this invention. Those skilled in the art would realize that other instruction codings are feasible and within the scope of this invention. Each instruction consists of 32 bits and controls the operation of one of the individually controllable functional units (L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225, D2 unit226, L2 unit241, S2 unit242, M2 unit243, N2 unit244, C unit245and P unit246). The bit fields are defined as follows.

The creg field1301(bits29to31) and the z bit1302(bit28) are optional fields used in conditional instructions. These bits are used for conditional instructions to identify the predicate register and the condition. The z bit1302(bit28) indicates whether the predication is based upon zero or not zero in the predicate register. If z=1, the test is for equality with zero. If z=0, the test is for nonzero. The case of creg=0 and z=0 is treated as always true to allow unconditional instruction execution. The creg field1301and the z field1302are encoded in the instruction as shown in Table 1.

TABLE 1ConditionalcregzRegister31302928Unconditional0000Reserved0001A0001zA1010zA2011zA3100zA4101zA5110zReserved11xx

Execution of a conditional instruction is conditional upon the value stored in the specified data register. This data register is in the global scalar register file211for all functional units. Note that “z” in the z bit column refers to the zero/not zero comparison selection noted above and “x” is a don't care state. This coding can only specify a subset of the 16 global registers as predicate registers. This selection was made to preserve bits in the instruction coding. Note that unconditional instructions do not have these optional bits. For unconditional instructions these bits in fields1301and1302(28to31) are preferably used as additional opcode bits.

The dst field1303(bits23to27) specifies a register in a corresponding register file as the destination of the instruction results.

The src2/cst field1304(bits18to22) has several meanings depending on the instruction opcode field (bits4to12for all instructions and additionally bits28to31for unconditional instructions). The first meaning specifies a register of a corresponding register file as the second operand. The second meaning is an immediate constant. Depending on the instruction type, this is treated as an unsigned integer and zero extended to a specified data length or is treated as a signed integer and sign extended to the specified data length.

The src1 field1305(bits13to17) specifies a register in a corresponding register file as the first source operand.

The opcode field1306(bits4to12) for all instructions (and additionally bits28to31for unconditional instructions) specifies the type of instruction and designates appropriate instruction options. This includes unambiguous designation of the functional unit used and operation performed. A detailed explanation of the opcode is beyond the scope of this invention except for the instruction options detailed below.

The e bit1307(bit2) is only used for immediate constant instructions where the constant may be extended. If e=1, then the immediate constant is extended in a manner detailed below. If e=0, then the immediate constant is not extended. In that case the immediate constant is specified by the src2/cst field1304(bits18to22). Note that this e bit1307is used for only some instructions. Accordingly, with proper coding this e bit1307may be omitted from instructions which do not need it and this bit used as an additional opcode bit.

The s bit1307(bit1) designates scalar datapath side A115or vector datapath side B116. If s=0, then scalar datapath side A115is selected. This limits the functional unit to L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226and the corresponding register files illustrated inFIG.2. Similarly, s=1 selects vector datapath side B116limiting the functional unit to L2 unit241, S2 unit242, M2 unit243, N2 unit244, P unit246and the corresponding register file illustrated inFIG.2.

The p bit1308(bit0) marks the execute packets. The p-bit determines whether the instruction executes in parallel with the following instruction. The p-bits are scanned from lower to higher address. If p=1 for the current instruction, then the next instruction executes in parallel with the current instruction. If p=0 for the current instruction, then the next instruction executes in the cycle after the current instruction. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to twelve instructions. Each instruction in an execute packet must use a different functional unit.

There are two different condition code extension slots.

Each execute packet can contain one each of these unique 32-bit condition code extension slots which contains the 4-bit creg/z fields for the instructions in the same execute packet.FIG.14illustrates the coding for condition code extension slot0andFIG.15illustrates the coding for condition code extension slot1.

FIG.14illustrates the coding for condition code extension slot0having 32 bits. Field1401(bits28to31) specify4creg/z bits assigned to the L1 unit221instruction in the same execute packet. Field1402(bits27to24) specify4creg/z bits assigned to the L2 unit241instruction in the same execute packet. Field1403(bits19to23) specify4creg/z bits assigned to the S1 unit222instruction in the same execute packet. Field1404(bits16to19) specify4creg/z bits assigned to the S2 unit242instruction in the same execute packet. Field1405(bits12to15) specify4creg/z bits assigned to the D1 unit225instruction in the same execute packet. Field1406(bits8to11) specify4creg/z bits assigned to the D2 unit245instruction in the same execute packet. Field1407(bits6and7) is unused/reserved. Field1408(bits0to5) are coded a set of unique bits (CCEX0) to identify the condition code extension slot0. Once this unique ID of condition code extension slot0is detected, the corresponding creg/z bits are employed to control conditional execution of any L1 unit221, L2 unit241, S1 unit222, S2 unit242, D1 unit224and D2 unit225instruction in the same execution packet. These creg/z bits are interpreted as shown in Table 1. If the corresponding instruction is conditional (includes creg/z bits) the corresponding bits in the condition code extension slot0override the condition code bits in the instruction. Note that no execution packet can have more than one instruction directed to a particular execution unit. No execute packet of instructions can contain more than one condition code extension slot0. Thus the mapping of creg/z bits to functional unit instruction is unambiguous. Setting the creg/z bits equal to “0000” makes the instruction unconditional. Thus a properly coded condition code extension slot0can make some corresponding instructions conditional and some unconditional.

FIG.15illustrates the coding for condition code extension slot1having 32 bits. Field1501(bits28to31) specify4creg/z bits assigned to the M1 unit223instruction in the same execute packet. Field1502(bits27to24) specify4creg/z bits assigned to the M2 unit243instruction in the same execute packet. Field1503(bits19to23) specify4creg/z bits assigned to the C unit245instruction in the same execute packet. Field1504(bits16to19) specify4creg/z bits assigned to the N1 unit224instruction in the same execute packet. Field1505(bits12to15) specify4creg/z bits assigned to the N2 unit244instruction in the same execute packet. Field1506(bits5to11) is unused/reserved. Field1507(bits0to5) are coded a set of unique bits (CCEX1) to identify the condition code extension slot1. Once this unique ID of condition code extension slot1is detected, the corresponding creg/z bits are employed to control conditional execution of any M1 unit223, M2 unit243, C unit245, N1 unit224and N2 unit244instruction in the same execution packet. These creg/z bits are interpreted as shown in Table 1. If the corresponding instruction is conditional (includes creg/z bits) the corresponding bits in the condition code extension slot1override the condition code bits in the instruction. Note that no execution packet can have more than one instruction directed to a particular execution unit. No execute packet of instructions can contain more than one condition code extension slot1. Thus the mapping of creg/z bits to functional unit instruction is unambiguous. Setting the creg/z bits equal to “0000” makes the instruction unconditional. Thus a properly coded condition code extension slot1can make some instructions conditional and some unconditional.

It is feasible for both condition code extension slot0and condition code extension slot1to include a p bit to define an execute packet as described above in conjunction withFIG.13. In the preferred embodiment, as illustrated inFIGS.14and15, code extension slot0and condition code extension slot1preferably have bit0(p bit) always encoded as 1. Thus neither condition code extension slot0nor condition code extension slot1can be in the last instruction slot of an execute packet.

There are two different constant extension slots. Each execute packet can contain one each of these unique 32-bit constant extension slots which contains 27 bits to be concatenated as high order bits with the 5-bit constant field1305to form a 32-bit constant. As noted in the instruction coding description above only some instructions define the src2/cst field1304as a constant rather than a source register identifier. At least some of those instructions may employ a constant extension slot to extend this constant to 32 bits.

FIG.16illustrates the fields of constant extension slot0. Each execute packet may include one instance of constant extension slot0and one instance of constant extension slot1.FIG.16illustrates that constant extension slot01600includes two fields. Field1601(bits5to31) constitute the most significant 27 bits of an extended 32-bit constant including the target instruction scr2/cst field1304as the five least significant bits. Field1602(bits0to4) are coded a set of unique bits (CSTX0) to identify the constant extension slot0. In the preferred embodiment constant extension slot01600can only be used to extend the constant of one of an L1 unit221instruction, data in a D1 unit225instruction, an S2 unit242instruction, an offset in a D2 unit226instruction, an M2 unit243instruction, an N2 unit244instruction, a branch instruction, or a C unit245instruction in the same execute packet. Constant extension slot1is similar to constant extension slot0except that bits0to4are coded a set of unique bits (CSTX1) to identify the constant extension slot1. In the preferred embodiment constant extension slot1can only be used to extend the constant of one of an L2 unit241instruction, data in a D2 unit226instruction, an S1 unit222instruction, an offset in a D1 unit225instruction, an M1 unit223instruction or an N1 unit224instruction in the same execute packet.

Constant extension slot0and constant extension slot1are used as follows. The target instruction must be of the type permitting constant specification. As known in the art this is implemented by replacing one input operand register specification field with the least significant bits of the constant as described above with respect to scr2/cst field1304. Instruction decoder113determines this case, known as an immediate field, from the instruction opcode bits. The target instruction also includes one constant extension bit (e bit1307) dedicated to signaling whether the specified constant is not extended (preferably constant extension bit=0) or the constant is extended (preferably constant extension bit=1). If instruction decoder113detects a constant extension slot0or a constant extension slot1, it further checks the other instructions within that execute packet for an instruction corresponding to the detected constant extension slot. A constant extension is made only if one corresponding instruction has a constant extension bit (e bit1307) equal to 1.

FIG.17is a partial block diagram1700illustrating constant extension.FIG.17assumes that instruction decoder113detects a constant extension slot and a corresponding instruction in the same execute packet. Instruction decoder113supplies the 27 extension bits from the constant extension slot (bit field1601) and the 5 constant bits (bit field1305) from the corresponding instruction to concatenator1701. Concatenator1701forms a single 32-bit word from these two parts. In the preferred embodiment the 27 extension bits from the constant extension slot (bit field1601) are the most significant bits and the 5 constant bits (bit field1305) are the least significant bits. This combined 32-bit word is supplied to one input of multiplexer1702. The 5 constant bits from the corresponding instruction field1305supply a second input to multiplexer1702. Selection of multiplexer1702is controlled by the status of the constant extension bit. If the constant extension bit (e bit1307) is 1 (extended), multiplexer1702selects the concatenated 32-bit input. If the constant extension bit is 0 (not extended), multiplexer1702selects the 5 constant bits from the corresponding instruction field1305. Multiplexer1702supplies this output to an input of sign extension unit1703.

Sign extension unit1703forms the final operand value from the input from multiplexer1703. Sign extension unit1703receives control inputs Scalar/Vector and Data Size. The Scalar/Vector input indicates whether the corresponding instruction is a scalar instruction or a vector instruction. The functional units of data path side A115(L1 unit221, S1 unit222, M1 unit223, N1 unit224, D1 unit225and D2 unit226) can only perform scalar instructions. Any instruction directed to one of these functional units is a scalar instruction. Data path side B functional units L2 unit241, S2 unit242, M2 unit243, N2 unit244and C unit245may perform scalar instructions or vector instructions. Instruction decoder113determines whether the instruction is a scalar instruction or a vector instruction from the opcode bits. P unit246may only preform scalar instructions. The Data Size may be 8 bits (byte B), 16 bits (half-word H), 32 bits (word W), 64 bits (double word D), quad word (128 bit) data or half vector (256 bit) data.

Table 2 lists the operation of sign extension unit1703for the various options.

TABLE 2InstructionOperandConstantTypeSizeLengthActionScalarB/H/W/D5 bitsSign extend to 64 bitsScalarB/H/W/D32 bitsSign extend to 64 bitsVectorB/H/W/D5 bitsSign extend to operandsize and replicateacross whole vectorVectorB/H/W32 bitsReplicate 32-bitconstant across each32-bit (W) laneVectorD32 bitsSign extend to 64 bitsand replicate acrosseach 64-bit (D) lane

It is feasible for both constant extension slot0and constant extension slot1to include a p bit to define an execute packet as described above in conjunction withFIG.13. In the preferred embodiment, as in the case of the condition code extension slots, constant extension slot0and constant extension slot1preferably have bit0(p bit) always encoded as 1. Thus neither constant extension slot0nor constant extension slot1can be in the last instruction slot of an execute packet.

It is technically feasible for an execute packet to include a constant extension slot0or1and more than one corresponding instruction marked constant extended (e bit=1). For constant extension slot0this would mean more than one of an L1 unit221instruction, data in a D1 unit225instruction, an S2 unit242instruction, an offset in a D2 unit226instruction, an M2 unit243instruction or an N2 unit244instruction in an execute packet have an e bit of 1. For constant extension slot1this would mean more than one of an L2 unit241instruction, data in a D2 unit226instruction, an S1 unit222instruction, an offset in a D1 unit225instruction, an M1 unit223instruction or an N1 unit224instruction in an execute packet have an e bit of 1. Supplying the same constant extension to more than one instruction is not expected to be a useful function. Accordingly, in one embodiment instruction decoder113may determine this case an invalid operation and not supported. Alternately, this combination may be supported with extension bits of the constant extension slot applied to each corresponding functional unit instruction marked constant extended.

Special vector predicate instructions use registers in predicate register file234to control vector operations. In the current embodiment all these SIMD vector predicate instructions operate on selected data sizes. The data sizes may include byte (8 bit) data, half word (16 bit) data, word (32 bit) data, double word (64 bit) data, quad word (128 bit) data and half vector (256 bit) data. Each bit of the predicate register controls whether a SIMD operation is performed upon the corresponding byte of data. The operations of P unit245permit a variety of compound vector SIMD operations based upon more than one vector comparison. For example a range determination can be made using two comparisons. A candidate vector is compared with a first vector reference having the minimum of the range packed within a first data register. A second comparison of the candidate vector is made with a second reference vector having the maximum of the range packed within a second data register. Logical combinations of the two resulting predicate registers would permit a vector conditional operation to determine whether each data part of the candidate vector is within range or out of range.

L1 unit221, S1 unit222, L2 unit241, S2 unit242and C unit245often operate in a single instruction multiple data (SIMD) mode. In this SIMD mode the same instruction is applied to packed data from the two operands. Each operand holds plural data elements disposed in predetermined slots. SIMD operation is enabled by carry control at the data boundaries. Such carry control enables operations on varying data widths.

FIG.18illustrates the carry control. AND gate1801receives the carry output of bit N within the operand wide arithmetic logic unit (64 bits for scalar datapath side A115functional units and 512 bits for vector datapath side B116functional units). AND gate1801also receives a carry control signal which will be further explained below. The output of AND gate1801is supplied to the carry input of bit N+1 of the operand wide arithmetic logic unit. AND gates such as AND gate1801are disposed between every pair of bits at a possible data boundary. For example, for 8-bit data such an AND gate will be between bits7and8, bits15and16, bits23and24, etc. Each such AND gate receives a corresponding carry control signal. If the data size is of the minimum, then each carry control signal is 0, effectively blocking carry transmission between the adjacent bits. The corresponding carry control signal is 1 if the selected data size requires both arithmetic logic unit sections. Table 3 below shows example carry control signals for the case of a 512 bit wide operand such as used by vector datapath side B116functional units which may be divided into sections of 8 bits, 16 bits, 32 bits, 64 bits, 128 bits or 256 bits. In Table 3 the upper 32 bits control the upper bits (bits128to511) carries and the lower 32 bits control the lower bits (bits0to127) carries. No control of the carry output of the most significant bit is needed, thus only 63 carry control signals are required.

TABLE 3Data SizeCarry Control Signals8bits (B)−000 0000 0000 0000 0000 0000 0000 00000000 0000 0000 0000 0000 0000 0000 000016bits (H)−101 0101 0101 0101 0101 0101 0101 01010101 0101 0101 0101 0101 0101 0101 010132bits (W)−111 0111 0111 0111 0111 0111 0111 01110111 0111 0111 0111 0111 0111 0111 011164bits (D)−111 1111 0111 1111 0111 1111 0111 11110111 1111 0111 1111 0111 1111 0111 1111128bits−111 1111 1111 1111 0111 1111 1111 11110111 1111 1111 1111 0111 1111 1111 1111256bits−111 1111 1111 1111 1111 1111 1111 11110111 1111 1111 1111 1111 1111 1111 1111

It is typical in the art to operate on data sizes that are integral powers of 2 (2N). However, this carry control technique is not limited to integral powers of 2. One skilled in the art would understand how to apply this technique to other data sizes and other operand widths.

FIG.19illustrates one view showing the cooperation between central processing unit core110and a program memory controller1930. Central processing unit core110regularly generates addresses for needed instructions for its operation. In the preferred embodiment of this invention, central processing unit core110operates on virtual memory addresses. Also in the preferred embodiment the instructions cached in level one instruction cache121are accessed by these virtual addresses. As illustrated inFIG.19, this virtual address is expressed in 48 bits in the preferred embodiment. In the preferred embodiment, level two combined instruction/data cache130and other memories operate upon a physical address, requiring a conversion between the virtual address and the physical address for any cache misses to level one instruction cache121serviced by level two combined instruction/data cache130.

Program memory controller1930includes a micro table look-aside buffer (μTLB)1931for address translation. If a tag comparison with TAGRAM1934determines the requested fetch packet is not stored in level one instruction cache121(miss), then this fetch packet is requested from level two combined instruction/data cache130. Because level one instruction cache121is virtually tagged and level two combined instruction/data cache130is physically tagged, this requires an address translation. The virtual address is supplied to micro table look-aside buffer1931. Address translation is typically performed using a table of most significant bits of virtual addresses and the corresponding most significant bits of physical addresses. In this example upon detecting the correct address pair, the address translation substitutes the most significant physical address bits from the table for the most significant virtual address bits of the requested address. It is typical that the least significant bits of the virtual address are the same as the least significant bits of the physical address. In this example, a complete virtual address/physical address translation table is stored in memory management unit (MMU)1920. In addition, level one instruction cache121includes micro table look-aside buffer1931which stores a subset of some of the address translation table entries in a cache-like fashion. When servicing an address translation, the requested virtual address is compared with address translation table entries stored in micro table look-aside buffer1931. If the virtual address matches a table entry in micro table look-aside buffer1931, the matching table entry is used for address translation. If the virtual address does not match any table entry in micro table look-aside buffer1931, then these address translation parameters are fetched from the memory management unit1920. Micro table look-aside buffer1931transmits a page translation entry request for the virtual address to memory management unit1920. Memory management unit1920finds the corresponding address translation entry and returns this entry to micro table look-aside buffer1931. Micro table look-aside buffer1931stores this newly fetched translation entry, typically casting out a currently stored entry to make room. Following address translation the physical address passes to level two combined instruction/data cache130.

Branch predictor1911supplies the virtual fetch address to program memory controller1930as well as a prefetch count. Branch prediction typically stores the memory address of each conditional branch instruction encountered in the program code as it executes. This enables branch predictor1911to recognize a conditional branch it has encountered. Associated with the conditional instruction address is a taken/not taken branch prediction and any branching history used in dynamic branch prediction. This branch prediction information will always be limited to a fairly small section of the program code due to limits in the amount of memory and circuits which are included within branch predictor1911. However, based upon the current instruction memory location and the predicted path through the program code due to branch prediction, branch predictor1911can determine a predicted number of linearly following instruction fetch packets to be used after the current instruction fetch packet access before a branch is predicted to be taken off this linear path. This number is called the fetch packet count or the prefetch count.

Central processing unit core110exchanges emulation information with emulation support unit1932which is a part of program memory controller1930.

Central processing unit core110receives instructions in the form of instruction fetch packets from program memory controller1930. As illustrated inFIG.19, these fetch packets are 512 bits (64 bytes) in the preferred embodiment. In the preferred embodiment level one instruction cache121, level two combined instruction/data cache130and any other memory store fetch packets aligned with 64 byte boundaries. Depending upon where the instructions are stored, this fetch packet may be recalled from level one instruction cache121, level two combined instruction/data cache130or other memory.

Program memory controller1930compares a portion of the fetch address received from central processing unit core110with entries in TAGRAM1934. TAGRAM1934stores tag data for each cache line stored in level one instruction cache121. Corresponding most significant bits of the fetch address are compared with each set of tags in TAGRAM1934. A match between these bits of the fetch address and any tag (hit) indicates that the instructions stored at the fetch address are stored in level one instruction cache121at a location corresponding to the matching tag. Upon such a match, program memory controller1930recalls the instructions from level one instruction cache121for supply as a fetch packet to central processing unit core110.

The failure of a match between these bits of the fetch address and any tag (miss) indicates that the instructions stored at the fetch address are not stored in level one instruction cache121. Program memory controller1930transmits a cache request to unified memory controller (UMC)1940to seek the instructions in level two combined instruction/data cache130(FIG.1). The cache request is accompanied by a physical address translated from the virtual address as discussed above. If the instructions at this address are stored in level two combined instruction/data cache130(hit), the request is serviced from this cache. Otherwise the request is supplied to a higher level memory (not illustrated).

Program memory controller1930includes coherency support unit1935. Coherence support unit1935makes sure that data movements preserve the most recent instructions for supply to central processing unit core110.

FIG.20illustrates another view of the interface between the central processing unit core110and program memory controller1930. In the preferred embodiment, level one instruction cache121has a fixed cache size of 32 KB. Level one instruction cache121maximizes performance of the code execution and facilitates fetching instructions at a fast clock rate. Level one instruction cache121hides the latency associated with executing code store in a slower system memory. Each central processing unit core110interfaces with a separate program memory controller1930, which interface with the unified memory controller1940for level two combined instruction/data cache130.

In the preferred embodiment level one instruction cache121and program memory controller1930include the following attributes. They comprise a 32 KB 4-way instruction cache. They are virtually indexed and virtually tagged cache with a 49-bit virtual address. They include virtualization support having an integrated micro table look-aside buffer1931. The cache lines have a size of 64 bytes. In the preferred embodiment this is the same size as a fetch packet. They can queue up to 8 pairs of fetch packet requests to unified memory controller1940to enable prefetch in a program pipeline.

Even though level one instruction cache121line size is 64 bytes, the PMC-UMC interface is optimized so that the unified memory controller1940returns up to 2 dataphases (128 bytes). According to this invention more fully described below, extra returned instructions can be conditionally stored upon a service of a level one instruction cache miss.

Central processing unit core110transmits a fetch address and a fetch packet count upon each instruction fetch request. The fetch packet count is generated by branch predictor1911(FIG.19). The fetch packet count indicates a predicted number of sequential 64-byte cache lines to be returned to central processing unit core110starting from the given address. Program memory controller1930fetch finite state machine2024issues a prefetch for each of the packets and combines them into pairs in scoreboard2041whenever an incoming request to the scoreboard can be satisfied by the second dataphase of the previous request. A fetch packet count of 0 indicates central processing unit core110requests for program memory controller1930in an incremental mode to fetch 64-byte lines with no fetch ahead. Central processing unit core110must request a flush for program memory controller1930to exit incremental mode and resume normal operation.

FIG.21illustrates how a fetch address2100is parsed for handling by program memory controller1930. Fetch address2100is divided into: offset2101; set2102; and tag2103. Cache lines in level one instruction cache121are 64 bytes long. Assuming memory is byte addressable, then the location within a cache line of level one instruction cache121serves as a proxy for the six least significant bits of the address (offset2101). Set bits2102correspond directly to a physical location within level one instruction cache121. If level one instruction cache121stores an instruction, it is in a location corresponding to set bits2102. The tag bits2103are stored for comparison with the fetch address. A match (hit) indicates that the addressed instruction(s) are stored in level one instruction cache121. If no match is found (miss), then the instructions of the requested fetch packet must be obtained from another source than level one instruction cache121.

Program memory controller1930operates in plural instruction phases.FIG.20illustrates phases:2010;2020;2030;2040; and2050. Operations take place simultaneously during phase2010,2020,2030,2040and2050on differing fetch requests.

Instruction fetch unit111(part of central processing unit core110, seeFIG.1) determines the memory address of the next instruction fetch packet. This fetch address is supplied to one input of multiplexer2011active in phase2010. This fetch address is also supplied to fetch address register2022active in phase2020. As part of branch prediction, instruction fetch unit111also supplies a fetch packet count register2023active in phase2020.

The combination of multiplexers2011and2012supply one of three addresses to TAGRAM1934for tag comparison. Multiplexer2011selects between the fetch address received from central processing unit core110and a prefetch address from prefetch finite state machine2024. Formation of this prefetch address is described above. Multiplexer2012selects between the output of multiplexer2011and the virtual address in program memory controller scoreboard2041corresponding to a return from unified memory controller1940. An access from program memory controller scoreboard2041has greatest priority. An access from central processor unit core110has the next highest priority. An access from prefetch finite state machine2024has the lowest priority.

During phase2020prefetch finite state machine (FSM)2024optionally generates a prefetch request. The prefetch request includes an address calculated from the central processing unit core110request address and the fetch packet count as described above. Prefetch finite state machine2024supplies the next prefetch address to multiplexer2011. Prefetch finite state machine2024supplies a micro table look-aside buffer request to micro table look-aside buffer2035for page translation data for the prefetch address if it is a different page than the initial request from central processing unit core110.

Also during phase2020the address selected by the multiplexers2011and2012in the prior phase2010are supplied to TAGRAM1934to begin tag comparison.

In phase2030the tag comparison completes. In the example illustrated inFIG.20, tag compare2031separately compares the tag portion2103of the presented address with data stored in the four banks of TAGRAM1934. The comparison generates either a hit or a miss. A hit indicates that instructions at the requested address are stored in memory121. In this case multiplexer2036supplies these instructions from memory121to central processing unit core110.

The tag compare of program memory controller1930obtains way information in parallel with information on the requested line. For cache hits the way information is needed to locate the requested fetch packet. For cache misses the way information determines the cache line evicted (written-over) by data returned from a higher level memory. On a level one instruction cache miss, program memory controller1930stores this way information in scoreboard2041with other data on the requested line. Once the data returns from level two combined instruction/data cache130, program memory controller1930consults scoreboard2041to determine which way to store. A line to be allocated (whether demand or prefetch) is invalidated once the request is generated to avoid false hits by newer accesses while return data of the requested line is pending.

Upon a miss, program memory controller1930operating in phase2040seeks the instructions stored at that address from level two combined instruction/data cache130via unified memory controller1940. This includes: establishing an entry in program memory controller scoreboard2041; receiving way information from FIFO replacement unit2033selected by multiplexer2034; and receiving the translated physical address from micro table look-aside buffer1931. Program memory controller scoreboard2041generates a request signal to unified memory controller1940for the instructions stored at this translated physical address.

Program memory controller1930does not search in-flight requests stored in scoreboard2041for possible match between prior requests. Thus it is possible that two or more requests for the same cache line to be allocated to different ways of the same set. This could cause two or more matches upon tag compare if the same set is requested in the future. Whenever this occurs, program memory controller1930invalidates one of the duplicated tags and the corresponding cache way to free up the way for a new entry. This invalidation only occurs when a set with duplicate tags is accessed for a hit/miss decision on another request. In the preferred embodiment program memory controller1930keeps the most significant valid way (i.e. the way denoted by the MSB of the set's valid bits) while invalidating other ways. For example, if way0and way2have identical tags and are valid, then way2is kept and way0is invalidated. L1P does not invalidate duplicate tags on emulation accesses.

In phase2050(which may include more than one phase depending upon the location of the instructions sought) unified memory controller1940services the instruction request. This process includes determining whether the requested instructions are stored in level two combined instruction/data cache130. On a cache hit to level two combined instruction/data cache130, unified memory controller1940supplies the instructions from level two combined instruction/data cache130. On a cache miss to level two combined instruction/data cache130, unified memory controller1940seeks these instructions from another memory. This other memory could be an external third level cache or and an external main memory. The number of phases required to return the requested instructions depend upon whether they are cached in level two combined instruction/data cache130, they are cached in an external level three cache or they are stored in external main memory.

All instructions returned from unified memory controller1940are stored in memory121. Thus these instructions are available for later use by central processing unit core110. If the instruction request triggering the request to unified memory controller1940was directly from central processing unit core110(demand fetch), multiplexer2036contemporaneously supplies the returned instructions directly to central processing unit core110. If the request triggering the request to unified memory controller1940was a prefetch request, then multiplexer2036blocks supply of these instructions to central processing unit core110. These instructions are merely stored in memory121based upon an expectation of future need by central processing unit core110.

FIG.22is a partial schematic diagram illustrating relevant parts of unified memory controller1940. Program memory controller1930supplies a requested address to unified memory controller1940upon a level one cache miss.

Unified memory controller1940receives requests from program memory controller1930in the form of requested addresses. Program memory controller1930makes these requests upon a cache miss into level one instruction cache121. The instructions stored at the requested address are not stored in level one instruction cache121and are sought for level two unified instruction/data cache130. Thus program memory controller1930sends requested address to unified memory controller1940.

The requested address is transmitted to tags2201. In a manner known in the art, the requested address is compared with partial addresses store in tags2201to determine whether level two combined instruction/data cache130stores the instructions at the requested address. Upon detecting no match (miss), unified memory controller1940transmits a service request to a next level memory. This next level memory could be an external level three cache or an external main memory. This next level memory will ultimately return the data or instructions at the requested address. This return data or instructions are stored in level two combined instruction/data cache130. This storage typically involves casting out and replacing another entry in level two combined instruction/data cache130. The original request is then serviced from level two combined instruction/data cache130.

Upon detecting a match (hit), tags2201transmits an indication of the address to level two combined instruction/data cache130. This indication enables level two combined instruction/data cache to locate and recall a cache line corresponding to the requested address. This recalled cache line is stored in register2201.

Register2202is illustrated as having an upper half and a lower half. The cache line size in level two combined instruction/data cache130is twice the cache line size in level one instruction cache121. Thus, recall of one cache line from level two combined instruction/data cache130can supply two cache lines for level one instruction cache121. Multiplexer2203and multiplexer controller2204select either the upper half or the lower half of the level two combined instruction/data cache line for supply to program memory controller1930.

Multiplexer controller2204receives the requested address from program memory controller1930. In most circumstances one bit of this address controls the selection of multiplexer2203. If this address bit is 0, then the requested address is in the lower half of the level two combined instruction/data cache line stored in register2202. Multiplexer controller2204causes multiplexer2202to select the lower half of register2203for supply to program memory controller1930. If this address bit is 1, then the requested address is in the upper half of the level two combined instruction/data cache line stored in register2202, and multiplexer controller2204causes multiplexer2202to select this upper half. In the preferred embodiment cache lines in level one instruction cache121are 64 bytes and cache lines in level two combined instruction/data cache130are 128 bytes. For this cache line size selection, the controlling address bit is bit7, because 27equals 128.

In the prior art the unselected half of the level two combined instruction/data cache line stored in register2202would not be used. In the prior art it is discarded by being written over upon the next recall of a cache line from level two combined instruction/data cache.

This invention is an exception to this prior art process. This invention is applicable to a demand fetch. A demand fetch is a requested set of instruction directly from central processing unit core110and not a prefetch from prefetch finite state machine2024. This invention is applicable to such a demand fetch that is a miss to level one instruction cache121and a hit to the upper half of the level two combined instruction/data cache line130. Under these circumstances (demand fetch which is level one cache miss and a hit to the upper half of level two combined instruction/data cache line), initially the upper half stored in register2202is selected by multiplexer2203for supply to program memory controller1930. Upon the next memory cycle multiplexer controller2204controls multiplexer2203to supply the lower half of register2202. Upon the return to program memory controller1930this is treated as a prefetch return. The difference in treatment of demand fetch returns and prefetch returns is described below.

FIG.23is a flow chart of operation2300according to a prefetch technique of this invention. Operation2300illustrates only the part of the operation of program memory controller1930and unified memory controller1940relevant to this invention. Operations relevant to this aspect of the invention begin at start block2301upon an instruction fetch.

Test block2302determines if the fetch address of an instruction fetch just submitted for tag match results in a miss within program memory controller190. If the fetch address was not a miss (No at test block2302), then this invention is not applicable. Flow proceeds to continue block2303to other aspects of the fetch process not relevant to this invention. In this case, if a fetch address is not a miss, then it is a hit. The instructions sought are stored in level one instruction cache121. This fetch is thus serviced from level one instruction cache121. These processes are not relevant to this invention.

If the fetch was a miss (Yes at test block2302), then the fetch is submitted to unified memory controller1940for service. As a part of this process, test block2304determines if this is a hit to tags2201. If this is a hit (yes at test block2304), then flow proceeds to continue block2305to other aspects of the fetch process not relevant to this invention. In this case if it is not a hit (No at test block2404), then it is a miss. The instruction fetch is serviced by higher level memory, which would typically be an external level three cache or an external main memory.

If test block2304determines the requested address is a hit into unified memory controller (Yes at test block2304), then block2306fetches and buffers the instructions at the requested address. As illustrated inFIG.22, the tag matching the requested address permits identification of the storage location within level two combined instruction/data cache130. The instructions stored at the corresponding line within level two combined instructions/data cache130are recalled and stored in register2202in upper and lower halves as illustrated inFIG.22.

Next test block2307determines if the fetch address was a demand fetch to the upper half of a cache line in level two combined instruction/data cache130. A fetch request is a demand fetch if the request was issued directly from central processing unit core110. A fetch request issued by prefetch finite state machine2024is a prefetch request and not a demand fetch. As described above the size of cache lines in level one instruction cache121is half the same as the size of cache lines in level two combined instruction/data cache130. The addresses of these cache lines are aligned so that each cache line of level one instruction cache121corresponds to one of the lower half or the upper half of a cache line in level two combined instruction/data cache130. If the instruction fetch was not both a demand fetch and to the upper half of a cache line in level two combined instruction/data cache130(No at test block2307), then process2300proceeds to continue block2308to other aspects of the fetch process not relevant to this invention. This invention is not applicable to a demand fetch to a lower half a cache line in level two combined instruction/data cache130or to a prefetch request. Process2300proceeds according to this invention only if the instruction fetch was a demand fetch to the upper half of a cache line in level two combined instruction/data cache130(yes at test block2307).

If the fetch address was a demand fetch to the upper half of a cache line in level two combined instruction/data cache130(yes at test block2307), then block2309supplies the upper half level two combined instruction/data cache line to program memory controller1930as a demand fetch. There is preferably a side channel to the instruction return to program memory controller1930to indicate if the returned instructions were in response to a demand fetch or in response to a prefetch. As noted below inFIG.24, program memory controller1930handles these two types of fetches differently.

On the next memory cycle, block2310supplies the lower half level two combined instruction/data cache line to program memory controller1930as a prefetch. Signaling program memory controller1930this return is a prefetch changes how it is handled as noted inFIG.24. This provides a virtual prefetch of the lower half level two combined instruction/data cache line that is handled similarly to a prefetch request issued by prefetch finite state machine2024.

Handling the prefetch of this invention differs slightly from handling other prefetches.

FIG.24is a flow chart2400illustrating the response of program memory controller1930to a return from unified memory controller1940. Operation2400illustrates only the part of the operation of program memory controller1930relevant to this invention. Operations relevant to this aspect of the invention begin at start block2401.

Test block2402determines whether a cache service is received from unified memory controller1940. If there is no cache service return (no at test block2402), then this invention is not applicable. Process2400continues with continue block2403.

Upon receipt of a cache service return from unified memory controller1940(yes at test block2402), test block2404determines whether the cache service return is to a demand request. As noted above, a demand request is issued directly from central processing unit core110. If this is a demand request return (yes at test block2404), then block2405forwards the returned instructions to central processing unit core110. Because central processing unit core110has directly requested these instructions (demand fetch), central processing unit core110is waiting for the instructions. Central processing unit core110may even be stalled and not producing results. Thus the cache service return is forwarded directly to central processing unit core110with the goal to reduce any stall time. Process2400then advances to block2406.

If this is not a demand request return (no at test block2404) or if this was a demand request return (yes at test block2404) following block2406suppling demand request returned instructions to central processing unit core110, then block2406stores the returned instructions in level one instruction cache121. The existence a cache service return from unified memory controller1940(test block2402) implies a cache miss in program memory controller1930. Thus the returned instruction should be stored in level one instruction121whether the triggering event was a demand request or a prefetch request. In this regard the supply of the lower half level two cache line following an upper half L2 hit is treated as a prefetch request.

The prefetch of this invention differs from a prefetch issued by prefetch finite state machine2024in several regards. Firstly, the prefetch of this invention is issued under different circumstances that a prefetch issued by prefetch finite state machine2024. Prefetch finite state machine2024issues a prefetch requests following a demand request if the prefetch count is nonzero. Unified memory controller1940issues the prefetch of this invention upon a level one instruction cache miss and a level two combined instruction/data cache hit to an upper half of a level two cache line.

Secondly, the processes in response differ. A prefetch request issued by prefetch finite state machine2024submits a request address to TAGRAM1934to determine whether the fetch packet is stored in level one instruction cache121. The prefetch address is based upon the address of the demand fetch and the prefetch count. Upon a cache hit, program memory controller1930takes no further action. Upon a cache miss, program memory controller1930submits the prefetch address to unified memory controller1940for cache service. In contrast the present invention starts with a level one instruction cache121demand fetch miss. The same service request to unified memory controller1940to service the initial demand fetch miss triggers a prefetch of the other half of the corresponding level two combined instruction/data cache130.

The prefetch of this invention uses a minimum of resources of the digital data processing system. This prefetch is begun by a level one instruction cache miss. The hardware for making such a level one instruction cache hit/miss determination is needed for normal operation. This invention does not require additional hardware or processes of the program memory controller. This invention does no level one instruction cache tag compare on the prefetch address (lower half of the level two unified cache line), assuming this is a miss. This prefetch requires a level two cache hit. The hardware for making such a level two cache hit/miss determination is needed for normal operation. This invention does not require additional hardware or processes of the unified memory controller. Because level two cache lines are twice the size of level one instruction cache lines, the unified memory controller must include some technique to select the upper half line or the lower half line of the level two cache for supply to the level one instruction cache. This invention uses this technique to support prefetch. Rather than being discarded, the lower half level two cache line is supplied to level one instruction cache121the next cycle. Thus this invention performs a prefetch which requires minimal additional resources.

Other prefetch techniques query the tag RAMS, compare tags for hit/miss determination and advance independently through the pipeline for each prefetch request. This incurs additional latency penalties and power consumption. This invention ties the prefetch to the corresponding demand access and neither reads tag RAMS, nor does a tag compare. In this invention the prefetch request inherits the miss determination of the corresponding demand access and uses its individual way information from discrete registers.

This invention has been described in conjunction with a very long instruction word (VLIW) central processing unit core. Those skilled in the art would realize the teachings of this application are equally applicable to a central processing unit core fetching individual instructions that are serviced by a level one instruction cache having a cache line size equal to the length of plural instructions.