Patent ID: 12199082

DESCRIPTION

This disclosure describes example direct-bonded light emitting diode (LED) arrays and applications. New processes for forming actively driven mLED (microLED) structures and display cells are described, including example processes of array-bonding III-V compound semiconductor mLEDs to silicon driver chips to form actively driven mLED display cells. Some of these processes may be used to mass-produce mLED array displays.

Example Processes and Structures

FIG.1shows an example of a conventional epilayer structure50of a light emitting diode (LED) over a sapphire substrate100, illustrating and comparing some LED components used in example structures and processes described herein. The example conventional LED structure50may produce green or blue light, for example. Semiconductor materials are layered on a carrier, such as a sapphire substrate100. The large mismatches in lattice constants and thermal expansion coefficients between GaN and sapphire100would cause high crystalline defect densities in the GaN films, which leads to degradation of device performance; hence a lattice and CTE matched buffer material101is deposited on sapphire100to grow GaN. Optoelectronic devices like the conventional LED structure50utilize semiconductor doping, for example, a small amount of silicon or germanium is added to gallium nitride (GaN) to make the GaN a conductor for electrons (n-type) n-GaN102, and a small amount of magnesium is added to the gallium nitride (GaN) to make the GaN into a conductor for holes (electron holes) (p-type) p-GaN104. Between the layer of n-GaN102and the layer of p-GaN104is sandwiched an ultrathin layer of a light-producing quantum well or multiple quantum well (MQW) material, that has a smaller band gap (and slightly less conductivity) than either the n-GaN102and the p-GaN104, such as indium gallium nitride InGaN, a semiconductor material made of a mix of gallium nitride (GaN) and indium nitride (InN). InGaN is a ternary group III/group V direct band gap semiconductor. The example InGaN/GaN or InGaN MQW layer106provides quantum confinement, or discrete energy subbands, in which the carriers can have only discrete energy values, providing better performance in optical devices. Conventional LED structures50may have many variations in the number or layers used, and the materials used for each layer. InFIG.1, the layers, and especially the MQW layer106, are not shown to relative scale.

The example conventional LED structure50is characterized by an n contact108and a p contact110at different vertical levels on different surfaces of the conventional LED structure50. The difference in vertical heights between p contact110and n contact108is conventionally compensated for by wire bond or solder connections. Or, an example conventional structure50may have an n contact108that is not exposed (not shown).

FIGS.2-3show an example LED structure200and process overview, for direct-bonding LED components containing III-V semiconductor elements to driver circuitry, for making mLED array displays. The example LED structure200provides an ultra-flat bonding interface202, made flat by chemical-mechanical polishing (CMP) for example, with both n contact108and p contact110surrounded by an insulator204, such as a silicon oxide, and exposed on the ultra-flat bonding interface202with respective coplanar conductive footprints206&208on the ultra-flat bonding interface202.

The n contact108and p contact110may be made of a metal, or combination of alloyed metals, or laminated metals that enhance direct bonding. Besides metal composition, the ultra-flat bonding interface202itself also facilitates direct bonding between the n and p contacts108&110and respective conductive surfaces being bonded to. The ultra-flat bonding interface202fabricated by damascene methods, for example, is also ultra-clean, and flat within a few tens of nanometers, such as less than ¼ the wavelength of an illumination source of monochromatic green light at the 546.1 nm or helium-neon red laser light at 632.8 nm. In some embodiments the roughness of the flat polished surface202is less than 5% of the wavelength of an illumination source and preferably less than 10 nm.

FIG.3shows an example direct-bonding process300between the example LED structure200ofFIG.2, and a driver circuit302on a chip304, to form LED circuitry, such as thin-film transistor (TFT) drivers. The example direct-bonding process300can be performed at the level of individual chips, or at a chip array level, or at wafer level. For subsequent lift-off and thinning, wafer level direct-bonding may be the best approach.

In an implementation, the mLED ultra-flat bonding interface202can be bonded to the respective ultra-flat bonding interface306of a silicon-based driver integrated circuit (IC)304, for example. The ultra-flat bonding interface306may have a contacting surface that is topped with a flat silicon oxide layer and copper (Cu) pads to facilitate direct-bonding, for example direct-bonding via a ZiBond® brand process or a DBI® brand process, to form LED circuitry (Xperi Corporation, San Jose, CA). In an implementation, the sapphire substrate100may then be laser-lifted off. If desirable, both top and bottom sides can be thinned further to make the entire stack flexible.

FIG.4shows stages of example structure fabrication, illustrating an example process flow for making an LED structure200suitable for direct-bonding with a silicon driver ICs304, for example.

In a first stage400of the example process flow, an example wafer, such as a sapphire substrate100, is built up with beginning epitaxial layers of n-GaN102, InGaN MQW106, and p-GaN104.

In a second stage402of the example process flow, the top epitaxial layers are patterned and etched to expose the n-GaN layer102at specific locations404. Although the single exposed location404is shown at the edge at the die, there may be more than one location. For example, one or more through-vias may expose the n-GaN layer102. The patterning resist can be left on.

In a third stage406of the example process flow, an insulator or dielectric, such as a silicon oxide layer204is deposited to cover both the exposed p-GaN104and the exposed n-GaN102, at least at the location of the contacting pads.

In a fourth stage408of the example process flow, the silicon oxide layer204is patterned and etched over the p-GaN104and n-GaN102layers to make cavities410through the silicon oxide204for conductive metals to become the electrodes of the LED structure200. In an implementation, the total thickness of the p-GaN104layer and the MQW106layer is approximately 2 μm, making the structure at this stage suitable for one-step etching and metallization (MQW layer106not shown to scale). One or more of such cavities410can be formed to form one or more electrodes contacting the n-GaN102layer and the p-GaN104layer.

In an alternative implementation, the example process deposits a flat silicon oxide layer204as in the third stage406above, then bonds this oxide surface directly with the driving chip(s)304using a ZiBond® brand direct-bonding process, or other direct bonding technique. Then, through-silicon-vias (TSVs) are drilled to create the electrical connectivity from the n contact108and the p contact110to the driver chip304.

In a fifth stage412of the example process flow, the cavities410can be metalized with a conductive material414. In an implementation, barrier and seed layer coatings416may be applied and formed, then cavities filled with the conductor414, followed by annealing, and chemical-mechanical planarization (CMP). In an implementation, a low melting temperature metal, such as indium, may be coated in the cavities.

In a sixth stage418of the example process, a top surface of the example LED structure200is plasma-activated420for the direct-bonding operation. Plasma-activation420may be optional for some types of direct-bonding techniques, while in others, the plasma-activation step420enhances the bond strength between two metal surfaces, for example, during contact bonding. Plasma-activation420may also be applied to the opposing surfaces to be bonded on the driver chip(s)304.

In various implementations, the example process flow depicted inFIG.4may include picking and transferring many small LED chips with high throughput, and direct-bonding at very fine pitch, for example at a pitch of less than 1 mm (even smaller pitch for making micro-projectors), and at a 0.05 mm spacing, and in various implementations all the way down to a 12 um pitch with 6 um bump. The pixel array optics achieve high parallelity of the LED dies200to the Si dies304. Post-processing, such as thinning and laser lift-offs, can be accomplished because the direct-bonding applied results in the flat topography and strong bonding interfaces achieved.

FIGS.5-9show an example process for creating a thin, transparent, and flexible mLED array display500, in which a wafer502with the LED structures200made by the process ofFIG.4are now bonded to (for example) a CMOS driver chip wafer504to make the transparent and flexible array display500.

InFIG.5, in an implementation, after the flat and activated surface on the LED device wafer502is formed, the CMOS wafer504is planarized with CMP or other means of obtaining an ultra-flat surface, and plasma-activated420.

InFIG.6, the two wafers502&504are bonded. For example, the first wafer502with the LED structures200and with coplanar bonding surfaces of the n contacts108and p contacts110, and the second wafer504with CMOS driver chips304, are brought together for direct-bonding between metallic conductors and in an implementation, between nonmetallic dielectric surfaces602also. Exposed silicon oxide of the first wafer502in contact with exposed silicon oxide of the second wafer504bonds first through oxide bonding, as with a ZiBond® brand direct-bonding process. The metal contact pads of the respective wafers502&504form a metal-to-metal bond during higher-than-room-temperature annealing, as with a DBI® brand direct-bonding process. The bonding interface604may be annealed at approximately 100-200° C. to form a strong direct bond interface, such as the ZiBond® or DBI® brand direct-bond interface.

An optical reflective coating, such as distributed Bragg reflector (DBR)606(not shown to relative scale), can be deposited to increase light output of the package by choosing different types and thickness of the dielectric layers on top of wafer502at the interface (606) between the first wafer502and the second wafer504. Alternatively, the DBR606could also be formed on top of the second wafer504prior to bonding. In this orientation of a DBR606, light can escape from the sapphire side of the device. If DBRs606are formed on the first wafer502, then the thin dielectrics need to be deposited at the end of the second stage402or the third stage406of the process shown inFIG.4. The DBR606is a structure formed from multiple layers of alternating materials with varying refractive index, or by periodic variation of some characteristic, for example, thickness of the dielectrics, resulting in periodic variation in the effective refractive index. These thin layers of dielectric coatings may be the combination of silicon oxide, magnesium fluoride, tantalum pentoxide, zinc sulfide, and titanium dioxide, for example. A silicon oxide SiOx layer on a top surface of the compound wafer502can also serve as the last of the coatings which is then bonded directly with direct bonding techniques, such as a ZiBond® or a DBI® process, to wafer504.

In another embodiment, DBR may be formed at between sapphire and n-GaN. In this orientation, the light will be reflected towards CMOS wafer504. However, less amount of light will escape as CMOS chip would be obstructing the escape route.

InFIG.7, the thin-film transistor (TFT) backplane can be thinned702, which can be facilitated by a ZiBond® brand direct-bonding process. Then the non-transistor parts704of the thinned backplane can also be etched away. In this embodiment, the location of one or more n-contacts108and p-contacts110can be designed such that they may be exposed from the backside after etching of the backplane; and hence can be contacted for power delivery from the back side.

InFIG.8, the thinned and etched transistor surface may be coated with a polyimide (PI) layer802or any other dielectric material for protection.

InFIG.9, a laser-lift-off of the sapphire substrate layer100may be performed, and this exposed side of the wafer502then coated with a flexible organic substrate902.

In another embodiment, the process to etch and backfill by the transistor backplane by PI may be skipped before a laser-lift-off of the sapphire substrate layer100. In this embodiment, one or more through-electrodes may be needed in the backplane for power delivery to the electrodes.

FIG.10shows operational access available on all sides of example transparent and flexible mLED array displays500created with direct-bonding. This versatility is due at least in part to the strong bonds possible with direct bonding, such as DBI® and ZiBond® brand bonding processes, which result in a final structure able to tolerate further processing on multiple sides of the structure500. For example, besides lifting off the transparent (e.g., sapphire) substrate100to make a flexible display500bonded to a flexible organic substrate902, post grinding may be applied and further lift-off performed to make the display thinner, more transparent, and more flexible.

The backside of the mLED array display500may be added onto with backside build-up layers1002for further 3D integration to attach to memory, printed circuit boards (PCBs), tactile and other sensors, and so forth.

One or more optical waveguides1004may be integrated on top of the transparent substrate902to transmit optical signals from the LED elements, and also lines for electrical signals may be added. In an implementation, the one or more optical waveguides1004are attached to the example LED array display500by a direct-bonding technique.

On the sides of the example mLED array display500, an edge emitting configuration1006may be added, and/or optical waveguides on the sides, similar to the one or more optical waveguides1004on top. In this embodiment, reflectors may be needed on both sides of the LED devices200, at layer902, as well as at the direct-bond (e.g., ZiBond®) interface604/606.

The structure of the example mLED array display500enables multi-junction stacking of compound semiconductors, for solar cells and solar panels, for example.

The sides of the example mLED array display500can also accommodate cooling structures1008.

After removing sapphire layer100, as inFIG.8, the surface may be roughened and indium tin oxide (ITO) added to improve the electrical conductivity of the LEDs.

The example steps just described and illustrated above provide direct-bonded light emitting diode (LED) arrays500, for example arrays of mLEDs, wherein group III-V semiconductor elements are direct-bonded to LED driver circuitry, in wafer-level processes, for example. The arrays500, made through a direct-bonding process, may be flexible, and possess an optically transparent surface.

In general, the example compound semiconductor-based LED array devices500are made with a flat surface composed of coplanar metal regions and dielectric regions. The coplanar metal regions are electrically connected to the active regions of the compound semiconductors of each LED element.

The above compound semiconductor-based LED array structures500may include bonds to a CMOS based device connected in a direct-bonding manner. The metal regions and the dielectric regions of the compound semiconductor-based LED array device500may be bonded directly to the respective metal regions and dielectric regions of the CMOS based device. Although described with respect to a wafer level process, the example process ofFIGS.5-9can be used not only for wafer-to-wafer (W2 W) processes, but also die-to-die (D2D), or one or multiple dies-to-wafer (D2 W) processes.

The resulting example LED array structures500may also have other characteristics and features:

The resulting LED array structures500may have an absence of substrate where the group III-V-based semiconductor light-emitting devices are grown. Further, a surface of the microstructure of the group III-V semiconductor-based light-emitting devices can be advantageously roughened for improved light extraction.

The electrode shape for electrically connecting to the n-GaN102and p-GaN104active regions via a direct-bonding process, such as a DBI® brand direct-bonding process, can be specially designed, such as frame-traced dot arrays for the electrode or contact108of the n-GaN102region, and a dot array in a circular or square area for the electrode or contact110of the p-GaN104region.

Example Processes

FIG.11shows an example method1100of making a direct-bonded LED structure. In the flow diagram, operations of the example method1100are shown in individual blocks.

At block1102, a LED structure is fabricated with electrical contacts to p-type and n-type semiconductor elements coplanar on a first surface comprising a flat bonding interface of the LED structure.

At block1104, the first surface is direct-bonded to a second surface comprising a flat bonding interface of a driver circuit for the LED structure.

The direct-bonding operation used in the example method1100, such as a ZiBond® or a DBI® brand direct-bonding process, may be applied in a wafer level, single chip-level, or a chip array-level process.

In the specification and appended claims: the terms “connect,” “connection,” “connected,” “in connection with,” and “connecting,” are used to mean “in direct connection with” or “in connection with via one or more elements.” The terms “couple,” “coupling,” “coupled,” “coupled together,” and “coupled with,” are used to mean “directly coupled together” or “coupled together via one or more elements.”

While the present disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations possible given the description. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the disclosure.