Patent ID: 12217672

DETAILED DESCRIPTION

In order to clearly illustrate the technical solution of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described. It is apparent that the described drawings are only related to some embodiments of the present disclosure and thus are not limitative of the present disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the description and the claims of the present application for disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. The terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. “On,” “under,” “right,” “left” and the like are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly

In a display device that is integrated with an imaging element, providing the imaging element in a display area of the display device helps to increase a screen-to-body ratio, for example, to realize full-screen display. The display area is provided with a display device, which may affect a light transmission rate of the imaging element and further affect a sensing effect. For example, light-emitting elements and light-proof routings in sub-pixels may prevent the imaging element from absorbing light, thereby affecting the imaging quality.

For example, the light transmission of the display area with the imaging element may be improved by reducing pixel circuit structures in the display area, and the display area with the imaging element is referred to as a transparent display area, for example. For example, the pixel circuit connected with the light-emitting element of the transparent display area may be arranged in a display area outside the transparent display area, that is, the light-emitting elements connected with some pixel circuits are moved to the transparent display area without emitting light on site, so that the display uniformity is improved, and the light transmission rate of the transparent display area is also increased.

For example, one implementation manner is to form the transparent display area by reducing the number of pixel circuits without changing the size of the pixel circuit. For example, the pixel circuits that are originally located in the transparent display area are removed directly. Since the number of the pixel circuits corresponds to the number of the light-emitting elements driven by the pixel circuits, the number of the light-emitting elements needs to be reduced correspondingly. For example, the arrangement density of the effective light-emitting elements in the transparent display area may be reduced. This way may reduce the uniformity of the display brightness.

For example, one way is to reduce the size of the pixels without changing the number of the pixel circuits, thereby reserving a space of the transparent display area. For example, the size of the pixel circuit is reduced in a horizontal direction (a row direction), and is unchanged in the longitudinal direction (a column direction). This may provide sufficient pixel circuits to drive the same number of light-emitting elements, so that the density of the light-emitting elements is not affected. For example, the light-emitting elements have uniform density in the display area. This way may further improve the display uniformity and reduce the influence of the transparent display area on the display effect.

Generally, pixel electrodes of the light-emitting elements need to be connected with the pixel circuits driving the light-emitting elements through connection lines or connection electrodes. It is discovered by the inventor that parasitic capacitance generated between the connection line or connection electrode and other conductive structures may have an adverse effect on the display effect of the light-emitting element. For example, the parasitic capacitor may increase the charging time of the pixel electrode, thereby postponing the lighting time of the light-emitting element, causing the reduction of the light-emitting time.

For example, the connection between the light-emitting element located in the transparent display area and the pixel circuit driving the light-emitting element outside the transparent display area needs a long connection line, which results in large parasitic capacitor at the pixel electrode, so that the charging time needed by the pixel electrode at a light-emitting stage is increased; and for example, at the light-emitting stage, the time for charging a potential of the pixel electrode to reach a lighting voltage of the light-emitting element is longer (for example, compared with the in-situ light-emitting sub-pixel in the display area outside the transparent display area), so that the light-emitting time is shortened, which finally results in non-uniformity of the brightness. Furthermore, in the transparent display area, different lengths, shapes or positions of the connection line connected with the pixel electrode of the light-emitting element may also cause different parasitic capacitance, which may lead to inconsistent lighting time of the light-emitting elements at the light-emitting stage, causing display Mura.

At least one embodiment of the present disclosure provides a pixel circuit including a driving sub-circuit, a data write sub-circuit, a compensation sub-circuit, a first switch sub-circuit and a first light-emitting control sub-circuit. The driving sub-circuit includes a control terminal connected with a first node, a first terminal connected with a second node and a second terminal connected with a third node, and the driving sub-circuit is configured to control a driving signal from the first node to the third node for driving the light-emitting element according to a voltage of the first node; the data write sub-circuit is connected with the second node and configured to write a data signal to the second node in response to a first scanning signal; the compensation sub-circuit is connected with the first node and the third node and configured to electrically connect the first node and the third node in response to a second scanning signal so as to control the driving sub-circuit to write a compensation voltage to the first node according to the data signal written to the second node; the first switch sub-circuit is configured to control the conduction of the driving signal between the third node and the fourth node according to the voltage of the third node in response to a first switch control signal; and the first light-emitting control sub-circuit is connected with a fifth node and connected with a first electrode of the light-emitting element through the fifth node, and the first light-emitting control sub-circuit is configured to control the conduction of the driving signal between the fourth node and the fifth node in response to the first light-emitting control signal, so that the driving signal can be applied to the light-emitting element.

For example, the driving signal may be a driving voltage or a driving current used to drive the light-emitting element.

According to the pixel circuit provided by the embodiment of the present disclosure, the fourth node N4, where parasitic capacitance is prone to generate, of the first light-emitting control sub-circuit is spaced apart from the fifth node N5that is directly connected with the light-emitting element, and the first light-emitting control sub-circuit may control the conduction between the fourth node N4and the fifth node N5, so that the fourth node may be charged in advance before the light-emitting stage; for example, sufficient time is provided for charging the fourth node before the beginning of the light-emitting stage, so that after the circuit enters the light-emitting stage, the influence of the parasitic capacitance at the fourth node on the lighting time of the light-emitting element is reduced, and the display Mura is alleviated. For example, at the light-emitting stage, the first light-emitting control sub-circuit is turned on in response to the first light-emitting control signal to conduct the driving signal between the fourth node and the fifth node, and the potential of the fourth node is copied to the fifth node that is connected with the light-emitting element; and since the fourth node is charged in advance, the potential of the fifth node may reach the lighting voltage of the light-emitting element rapidly, so that the lighting time is not affected by the parasitic capacitance at the fourth node N4anymore.

FIG.1Ais a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure. As shown inFIG.1A, the pixel circuit includes a driving sub-circuit122, a data write sub-circuit126, a compensation sub-circuit128, a first switch sub-circuit124and a first light-emitting control sub-circuit170.

The driving sub-circuit122includes a control terminal122aconnected with a first node N1, a first terminal122bconnected with a second node N2and a second terminal122cconnected with a third node N3; and the driving sub-circuit122is configured to control a driving signal from the first node N1to the third node N3for driving a light-emitting element120according to a voltage of the first node N1. For example, the driving signal may be a driving voltage or a driving current used to drive the light-emitting element.

The data write sub-circuit126is connected with the second node N2, and configured to write a data signal Vd to the second node N2in response to a first scanning signal Ga1. For example, the data write sub-circuit126includes a control terminal126a, a first terminal126band a second terminal126c; the control terminal126ais configured to receive the first scanning signal Ga1; the first terminal126bis configured to receive the data signal Vd; and the second terminal126cis connected with the second node N2. For example, at a data write and compensation stage, the data write sub-circuit126may be turned on in response to the first scanning signal Ga1, so that the data signal may be written to the first terminal122b(the second node N2) of the driving sub-circuit122and stored, so that the driving signal for driving the light-emitting element120to emit light may be generated according to the data signal at the light-emitting stage, for example.

The compensation sub-circuit128is connected with the first node N1and the third node N3, and configured to conduct the first node N1and the third node N3in response to a second scanning signal Ga2, so that the driving sub-circuit122is controlled to write a compensation voltage to the first node N1according to the data signal Vd written to the second node N2. For example, the compensation sub-circuit128includes a control terminal128a, a first terminal128band a second terminal128c; the control terminal128ais configured to receive the second scanning signal Ga2; the first terminal128bis connected with the third node N3; and the second terminal128cis connected with the first node N1.

For example, the first scanning signal Ga1may be the same as the second scanning signal Ga2. For example, the first scanning signal Ga1and the second scanning signal Ga2may be connected to a same signal output terminal. For example, the first scanning signal Ga1and the second scanning signal Ga2may be transmitted by a same scanning line.

In other examples, the first scanning signal Ga1may be different from the second scanning signal Ga2. For example, the first scanning signal Ga1and the second scanning signal Ga2may be connected to different signal output terminals. For example, the first scanning signal Ga1and the second scanning signal Ga2may be transmitted respectively by different scanning lines.

The first switch sub-circuit124is configured to control the conduction of the driving signal between the third node N3and the fourth node N4according to a voltage of the third node N3in response to a first switch control signal SW1. For example, the first switch sub-circuit124includes a control terminal124a, a first terminal124band a second terminal124c; the control terminal124ais configured to receive the first switch control signal SW1; and the first terminal124band the second terminal124care connected with the third node N3and the fourth node N4respectively.

The first light-emitting control sub-circuit170is connected with a fifth node N5and connected with a first electrode134of the light-emitting element120through the fifth node N5; and the first light-emitting control sub-circuit170is configured to control the conduction of the driving signal between the fourth node N4and the fifth node N5in response to a first light-emitting control signal EM1, so that the driving signal may be applied to the light-emitting element120. For example, the first light-emitting control sub-circuit170includes a control terminal170a, a first terminal170band a second terminal170c; the control terminal170ais configured to receive the first light-emitting control signal EW1; and the first terminal170band the second terminal170care connected with the fourth node N4and the fifth node N5respectively.

The first light-emitting control sub-circuit170is arranged between the fourth node N4and a pixel electrode (i.e. the first electrode134of the light-emitting element) to avoid the direct connection between the fourth node N4and the pixel electrode, so that the influence of a possible parasitic capacitor Cp (an example of a second capacitor of the present disclosure) at the fourth node N4on the pixel electrode may be reduced effectively. For example, before the light-emitting stage, the first switch sub-circuit124may be turned on, and the first light-emitting control sub-circuit170may be turned off, so that the fourth node N4may be pre-charged (for example, charged to the lighting voltage of the light-emitting element); and at the light-emitting stage, the first switch sub-circuit124and the first light-emitting control sub-circuit170are turned on simultaneously, and under the action of the driving current, the prepared potential on the fourth node N4is copied to the fifth node N5rapidly, so that the display Mura phenomenon caused by the occupation of the charging time needed by the parasitic capacitance on the lighting time is avoided, and the light-emitting uniformity is improved.

For example, at the light-emitting stage, the first light-emitting control sub-circuit170is turned on in response to the first light-emitting control signal EM1provided by a first light-emitting control terminal EM1, and meanwhile, the first switch sub-circuit124is also turned on, so that the driving sub-circuit122may be connected with the light-emitting element120electrically through the first switch sub-circuit124and the first light-emitting control sub-circuit170, thereby driving the light-emitting element120to emit light under the control of the driving signal; and at the non-light-emitting stage, the first light-emitting control sub-circuit170is turned off in response to the first light-emitting control signal EM1, thereby preventing current from flowing through the light-emitting element120and causing the light-emitting element to emit light, and improving the contrast of a corresponding display device.

For example, the parasitic capacitor Cp includes a first electrode Cpa and a second electrode Cpb; the first electrode Cpa is connected with the fourth node; the second electrode Cpb may be, for example, the first electrode134of the light-emitting element120or other signal routings, that is, the parasitic capacitor Cp is formed between the second terminal170bof the first light-emitting control sub-circuit170and the first electrode134of the light-emitting element120or other signal routings.

For example, the pixel circuit may also include a simulation capacitor Cm (an example of a first capacitor of the present disclosure). The simulation capacitor Cm includes a first electrode Cma and a second electrode Cmb; the first electrode Cma is connected with the fourth node; and the second electrode Cmb is, for example, configured to apply the same voltage as the second electrode135of the light-emitting element120, such as a second power supply voltage VSS. Thus, the simulation capacitor Cm may simulate the capacitor of the light-emitting element120, thereby constructing for the fourth node N4a same or similar environment as the fifth node N5, so that the potential of the fourth node N4is copied to the fifth node N5rapidly at the light-emitting stage.

For example, the pixel circuit may also include a first reset sub-circuit129;and the first reset sub-circuit129is connected with the fifth node N5and configured to write a first reset voltage Init1to the fourth node N4in response to a first reset control signal Rst1.

For example, the pixel circuit may also include a second reset sub-circuit125; and the second reset sub-circuit125is connected with the first node N1and configured to write a second reset voltage Init2to the first node N1in response to a second reset control signal Rst2.

For example, the pixel circuit may also include a second light-emitting control sub-circuit123; and the second light-emitting control sub-circuit123is connected with a first power supply voltage terminal VDD and the second node N2and configured to write a first power supply voltage VDD from the first power supply voltage terminal VDD to the second node N2in response to a second light-emitting control signal EM2. For example, the second light-emitting control signal and the first switch control signal SW1may be a same signal or different signals.

For another example, at an initialization stage, the second light-emitting control sub-circuit123may also be turned on in response to the second light-emitting control signal, so as to perform a reset operation on the driving sub-circuit122and the light-emitting element120combining with the reset circuit.

For example, the first reset voltage Init1and the second reset voltage Init2may be a same voltage signal or different voltage signals. For example, the first reset control signal Rst1and the second reset control signal Rst2may be a same signal or different signals.

For example, the first reset sub-circuit129and the second reset sub-circuit125may be turned on respectively in response to the first reset control signal Rst1and the second reset control signal Rst2, so that the first reset voltage Init1may be applied to the first electrode134of the light-emitting element120, and the second reset voltage Init2may be applied to the first node N1respectively, thereby performing the reset operation on the driving sub-circuit122, the compensation sub-circuit128and the light-emitting element120, and eliminating the influence of a previous light-emitting stage.

For example, the pixel circuit may also include a storage sub-circuit127; the storage sub-circuit127includes a first terminal127aand a second terminal127b; and the first terminal127aand the second terminal127bare connected with the first power supply voltage terminal VDD and the first node N1respectively. For example, at the data write and compensation stage, the compensation sub-circuit128may be turned on in response to the second scanning signal Ga2, so that the data signal written by the data write sub-circuit126may be stored in the storage sub-circuit127; and at the same time, the compensation sub-circuit128may electrically connect the first node N1and the third node N3, that is, the control terminal122aand the second terminal122cof the driving sub-circuit122are connected electrically, so that relevant information of a threshold voltage of the driving sub-circuit122is correspondingly stored in the storage sub-circuit, for example, the stored data signal and threshold voltage may be used to control the driving sub-circuit122at the light-emitting stage, and the driving sub-circuit122is compensated.

For example, the light-emitting element120includes a first electrode134and a second electrode135; the first electrode134of the light-emitting element120is configured to be connected with the second terminal122cof the driving sub-circuit122; and the second electrode135of the light-emitting element120is configured to be connected with a second power supply voltage terminal VS S.

It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, the fourth node N4and the fifth node and a sixth node described below do not necessarily indicate actual parts, but indicate joint points of relevant circuits in a circuit diagram.

It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd may indicate both a data signal terminal and a level of the data signal; similarly, the symbols Ga1and Ga2may indicate the first scanning signal and the second scanning signal, and may also indicate a first scanning signal terminal and a second scanning signal terminal; EM1and EM2may indicate the first light-emitting control signal and the second light-emitting control signal, and may also indicate a first light-emitting control terminal and a second light-emitting control terminal; Rst1and Rst2may indicate the first reset control signal and the second reset control signal, and may also indicate a first reset control terminal and a second reset control terminal; the symbols Init1and Init2may indicate the first reset voltage terminal and the second reset voltage terminal, and may also indicate a first reset voltage and a second reset voltage; the symbol VDD may indicate the first power supply voltage terminal, and may also indicate the first power supply voltage; and the symbol VSS may not only indicate the second power supply voltage terminal, but also the second power supply voltage. The following embodiments are the same as the above and are note repeated here.

FIG.1Billustrates a circuit diagram of a specific example of the circuit shown inFIG.1A. As shown inFIG.1B, the pixel circuit includes first to eighth transistors T1, T2, T3, T4, T5, T6, T7and T8and a storage capacitor Cst.

For example, as shown inFIG.1B, the driving sub-circuit122may be implemented as the first transistor T1(i.e. a driving transistor). A gate electrode of the first transistor T1serves as a control terminal122aof the driving sub-circuit122and is connected with the first node N1; a first electrode of the first transistor T1serves as the first terminal122bof the driving sub-circuit122and is connected with the second node N2; and a second electrode of the first transistor T1serves as the second terminal122cof the driving sub-circuit122and is connected with the third node N3.

For example, as shown inFIG.1B, the data write sub-circuit126may be implemented as the second transistor T2. The gate electrode of the second transistor T2is connected with a first scanning line (a first scanning signal terminal Ga1) so as to receive the first scanning signal; the first electrode of the second transistor T2is connected with a data line (a data signal terminal Vd) so as to receive the data signal; and the second electrode of the second transistor T2is connected with the first terminal122b(the second node N2) of the driving sub-circuit122.

For example, as shown inFIG.1B, the compensation sub-circuit128may be implemented as the third transistor T3(i.e. a compensation transistor). The gate electrode, the first electrode and the second electrode of the third transistor T3serve as a control terminal128a, a first terminal128band a second terminal128cof the compensation sub-circuit respectively. The gate electrode of the third transistor T3is configured to be connected with a second scanning line (a second scanning signal terminal Ga2) to receive the second scanning signal; the first electrode of the third transistor T3is connected with the second terminal122c(the third node N3) of the driving sub-circuit122; and the second electrode of the third transistor T3is connected with the control terminal122a(the first node N1) of the driving sub-circuit122.

For example, as shown inFIG.1B, the first light-emitting control sub-circuit170may be implemented as the eighth transistor T8(an example of a light-emitting control transistor of the present disclosure). The gate electrode of the eighth transistor T8is connected with a first light-emitting control line (a first light-emitting control terminal EM1) to receive the first light-emitting control signal EM1; the first electrode of the eighth transistor T8is connected with the fourth node N4; and the second electrode of the eighth transistor T8is connected with the fifth node N5.

For example, as shown inFIG.1B, the second light-emitting control sub-circuit123may be implemented as the fourth transistor T4. The gate electrode of the fourth transistor T4is connected with a second light-emitting control line (a second light-emitting control terminal EM2) to receive the second light-emitting control signal EM2; the first electrode of the fourth transistor T4is connected with the first power supply voltage terminal VDD to receive the first power supply voltage VDD; and the second electrode of the fourth transistor T4is connected with the first terminal122b(the second node N2) of the driving sub-circuit122.

For example, as shown inFIG.1B, the first switch sub-circuit124may be implemented as the fifth transistor T5; and the gate electrode, the first electrode and the second electrode of the fifth transistor T5serve as the control terminal124a, the first terminal124band the second terminal124cof the first switch sub-circuit124respectively. For example, the second light-emitting control signal EM2also serves as the first switch control signal SW1; in this case, the second light-emitting control line or the second light-emitting control terminal is also connected with the gate electrode of the fifth transistor T5to provide the first switch control signal SW1; the first electrode of the fifth transistor T5is connected with the second terminal122c(the third node N3) of the driving sub-circuit122; and the second electrode of the fifth transistor T5is connected with the first terminal170b(the fourth node N4) of the first light-emitting control sub-circuit170.

For example, as shown inFIG.1B, the storage sub-circuit127may be implemented as the storage capacitor Cst; the storage capacitor Cst includes a first capacitive electrode Ca and a second capacitive electrode Cb; the first capacitive electrode Ca is connected with the first power supply voltage terminal VDD; and the second capacitive electrode Cb is connected with the control terminal122aof the driving sub-circuit122.

For example, the first reset sub-circuit129may be implemented as the seventh transistor T7, and the second reset sub-circuit125may be implemented as the sixth transistor T6. The gate electrode of the seventh transistor T7is configured to be connected with the first reset control terminal Rst1to receive the first reset control signal Rst1; the first electrode of the seventh transistor T7is connected with the first reset voltage terminal Init1to receive the first reset voltage Init1; and the second electrode of the seventh transistor T7is configured to be connected with the fifth node N5. The gate electrode of the sixth transistor T6is configured to be connected with the second reset control terminal Rst2to receive the second reset control signal Rst2; the first electrode of the sixth transistor T6is connected with the second reset voltage terminal Init2to receive the second reset voltage Init2; and the second electrode of the sixth transistor T6is configured to be connected with the first node N1. For example, the first reset voltage terminal Init1and the second reset voltage terminal Init2may be the same voltage terminal.

For example, the light-emitting element120is specifically implemented as a light emitting diode (LED), for example, may be an organic light emitting diode (OLED), a quantum light emitting diode (QLED) or an inorganic light emitting diode, for example, may be a micro light emitting diode (Micro LED) or micro OLED. For example, the light-emitting element120may be a top emitting structure, a bottom emitting structure or a double-side emitting junction. The light-emitting element120may emit red light, green light, blue light or white light. The embodiments of the present disclosure do not limit a specific structure of the light-emitting element. For example, the light-emitting element120includes a first electrode134, a second electrode135and a light-emitting layer arranged between the first electrode134and the second electrode135.

For example, the first electrode134(that is also referred to as a pixel electrode such as an anode) of the light-emitting element120is connected with the fourth node N4and is configured to be connected to the second terminal122cof the driving sub-circuit122through the first switch sub-circuit124; and the second electrode135(such as a cathode) of the light-emitting element120is connected with the second power supply voltage terminal VSS to receive the second power supply voltage VSS, and the current flowing into the light-emitting element120from the second terminal122cof the driving sub-circuit122determines the brightness of the light-emitting element. For example, the second power supply voltage terminal may be grounded, that is, VSS may be 0V. For example, the second voltage power supply voltage VSS may also be a negative voltage.

It should be noted that the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors or other switch devices with the same characteristics, and the embodiments of the present disclosure all are described by taking the thin film transistors as examples. Source and drain electrodes of the transistor used here may be symmetrical in structure, so that the source and drain electrodes may not be different in structure. In the embodiments of the present disclosure, in order to distinguish the other two electrodes of the transistor other than the gate electrode, one electrode is described directly as the first electrode, and the other electrode is described as the second electrode.

Furthermore, the transistors may be classified into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistors are the P-type transistors, the turn-on voltage is a low-level voltage (such as 0V, −5V, −10V or other appropriate voltages), and the turn-off voltage is a high-level voltage (such as 5V, 10V or other appropriate voltages); and when the transistors are the N-type transistors, the turn-on voltage is a high-level voltage (such as 5V, 10V or other appropriate voltages), and the turn-off voltage is a low-level voltage (0V, −5V, −10V or other appropriate voltages). For example, the transistors (T1-T9) adopted by at least some embodiments of the present disclosure all are P-type transistors, such as low-temperature polycrystalline silicon thin-film transistors. However, the type of the transistors is not specified by the embodiments of the present disclosure, and when the type of the transistors is changed, the connection relationship in the circuit shall be adjusted correspondingly.

A working principle of the pixel circuit shown inFIG.1Bis described below in conjunction with a signal sequence diagram shown inFIG.1C. As shown inFIG.1C, a display process of each frame of image includes four stages, i.e. an initialization stage1, a data write and compensation stage2, a pre-charging stage3and a light-emitting stage4.

As shown inFIG.1C, in the present embodiment, the first scanning signal Ga1and the second scanning signal Ga2adopt a same signal, and the first switch control signal SW1and the second light-emitting control signal EM2adopt a same signal; the first reset control signal Rst1and the first scanning signal Ga1/the second scanning signal Ga2have the same waveform, that is, the second reset control signal Rst2and the first scanning signal Ga1/the second scanning signal Ga2may adopt the same signal; and the second reset signal Rst2of the present row of sub-pixels has the same waveform as the first scanning signal Ga1/the second scanning signal Ga2of a previous row of sub-pixels, that is, the same signal is adopted. However, the above is not used as a limitation to the present disclosure; and in other embodiments, different signals may be used as the first scanning signal Ga1, the second scanning signal Ga2, the first reset control signal Rst1and the second reset control signal Rst2respectively; and different signals are used as the first switch control signal SW1and the second light-emitting control signal EM2respectively.

At the initialization stage1, the second reset control signal Rst2is inputted to turn on the sixth transistor T6, and the second reset voltage Init2is applied to the gate electrode of the first transistor T1so as to reset the first node N1.

At the data write and compensation stage2, the first scanning signal Ga1, the second scanning signal Ga2and the data signal Vd are inputted and the second transistor T2and the third transistor T3are turned on; the data signal Vd is written to the second node N2by the second transistor T2, and the first node N1is charged through the first transistor T1and the third transistor T3by the data signal Vd, and until the potential of the first node N1is changed to Vd+Vth, the first transistor T1is turned off, wherein Vth is the threshold voltage of the first transistor T1. The potential of the first node N1is stored in the storage capacitor Cst to be maintained, that is, the voltage information with the data signal and threshold voltage Vth are stored in the storage capacitor Cst so as to be used to provide the gray-level display data and compensate the threshold voltage of the first transistor T1at the light-emitting stage subsequently.

At the data write and compensation stage2, the first reset control signal Rst1may also be inputted to turn on the seventh transistor T7, and the first reset voltage Init1is applied to the fifth node N5, thereby resetting the fifth node N5. For example, the fifth node N5may also be reset at the initialization stage1, for example, the first reset control signal Rst1and the second reset control signal Rst2may be the same, which is not limited by the embodiments of the present disclosure.

At the pre-charging stage3, the first switch control signal SW1, the second light-emitting control signal EM2and the first light-emitting control signal EM1are inputted to turn on the fifth transistor T5and the fourth transistor T4respectively and turn off the eighth transistor T8so as to charge the fourth node N4, so that the potential of the fourth node N4reaches a preset value, for example, a lighting voltage V0of the light-emitting element120; and for example, a voltage difference between the lighting voltage V0and the voltage (such as the second power supply voltage VSS) of the second terminal135of the light-emitting element120is the turn-on voltage of the light-emitting element120, for example, the turn-on voltage is the voltage difference between the two terminals of the light-emitting element when the light-emitting element emits the light with the brightness of 1 cd/m2. When the second terminal135of the light-emitting element120is grounded, the lighting voltage V0is equal to a numerical value of the turn-on voltage of the light-emitting element. For example, the duration of the pre-charging stage3is related to the parasitic capacitor Cp at the fourth node N4, and the greater the value of the parasitic capacitor Cp, the longer the duration of the pre-charging stage3.

At the light-emitting stage4, the first switch control signal SW1, the second light-emitting control signal EM2and the first light-emitting control signal EM1are inputted to turn on the fifth transistor T5, the fourth transistor T4and the eighth transistor T8respectively, and the eighth transistor T8applies the potential of the fourth node N4to the fifth node and applies the driving current to the OLED so as to enable the OLED to emit light. Since the potential of the fourth node N4is already pre-charged, the voltage difference between the two terminals of the OLED can reach the turn-on voltage of the light-emitting element rapidly, thereby lighting light-emitting element120. The value of the driving current I flowing by the OLED may be obtained according to the following formula:
I=K(VGS−Vth)2=K[(Vdata+Vth−VDD)−Vth]2=K(Vdata−VDD)2,
wherein K is an electrical conductivity coefficient of the first transistor.

In the above formula, Vth indicates the threshold voltage of the first transistor T1, VGS indicates the voltage between the gate electrode and the source electrode (i.e. the first electrode here) of the first transistor T1, and K is a constant value related to the first transistor T1itself. It may be seen from the above calculation formula I that the driving current I flowing by the OLED is not related to the threshold voltage Vth of the first transistor T1, so that the pixel circuit may be compensated, the drift problem of the threshold voltage caused by the technological process and long-time operation of the driving transistor (the first transistor T1in the embodiment of the present disclosure) is solved, the influence on the driving current I is eliminated, and the display effect of the display device adopting the OLED may be improved.

FIG.2Ais a schematic diagram of the pixel circuit provided by another embodiment of the present disclosure. The main difference between the pixel circuit provided by the present embodiment and the pixel circuit shown inFIG.1Ais that the first reset sub-circuit129is connected with the fourth node N4and configured to write the first reset voltage Init1to the fourth node N4in response to the first reset control signal. Because after the first light-emitting control sub-circuit170is turned on, the potential of the fourth node N4may be copied to the fifth node N5rapidly, so that resetting the fourth node N4is equivalent to resetting the fifth node N5. For example, referring toFIG.1C, at the data write and compensation stage2, the first reset sub-circuit129is turned on in response to the first reset control signal Rst1to reset the fourth node N4; and meanwhile, the first light-emitting control sub-circuit170is turned on in response to the first light-emitting control signal EM1, and the potential of the fourth node N4is copied to the fifth node N5so as to reset the fifth node N5.

FIG.2Billustrates a circuit diagram of a specific example of the circuit shown inFIG.2A; and the specific description may refer to the description ofFIGS.1B and1snot repeated here.

FIG.3Ais a schematic diagram of the pixel circuit provided by another embodiment of the present disclosure. The pixel circuit provided by the present embodiment differs from the pixel circuit shown inFIG.1Amainly in that the pixel circuit also includes a second switch sub-circuit180, the second switch sub-circuit180is connected with the fourth node N4, and the first reset sub-circuit129is connected with a sixth node N6and connected with the second switch sub-circuit180through the sixth node N6.

The first reset sub-circuit129is configured to write the first reset voltage Init1to the sixth node in response to the first reset control signal Rst1; and the second switch sub-circuit180is configured to control the conduction of the fourth node N4and the sixth node N6in response to the second switch control signal SW2, so that the first reset voltage Init1from the first reset sub-circuit129may be written to the fourth node N4, thereby resetting the fourth node N4.

For example, the second switch control signal SW2and the first light-emitting control signal EM1may be the same signal. For example, referring toFIG.1C, at the data write and compensation stage2, the first light-emitting control signal EM1/the second switch control signal SW2are turn-on signals; the second switch sub-circuit180is turned on, so that the second switch sub-circuit180does not affect the reset operation of the first reset sub-circuit129on the fourth node N4.

In the circuit layout of an actual display substrate, the second switch sub-circuit180may be used as an auxiliary sub-circuit and used to improve the uniformity (such as the etching uniformity) of the display substrate.

FIG.3Billustrates a circuit diagram of a specific example of the circuit shown inFIG.3A; for example, as shown inFIG.3B, the second switch sub-circuit180may be implemented as a ninth transistor T9; the gate electrode of the ninth transistor T9is configured to receive the second switch control signal SW2; and the first electrode and the second electrode of the ninth transistor T9are connected with the fourth node N4and the sixth node N6respectively. The specific description may refer to the description ofFIG.1B, and is not repeated here.

At least one embodiment of the present disclosure also provides a driving method of a pixel circuit, which is used to drive the pixel circuit provided by any embodiment. The driving method at least includes: at the data write and compensation stage, the data write sub-circuit is turned on, and the first switch sub-circuit and the first light-emitting control sub-circuit are turned off, so that the data signal is written to the second node, and the driving sub-circuit is compensated; at the pre-charging stage, the first switch sub-circuit is turned on, and the first light-emitting control sub-circuit is turned off so as to charge the fourth node, so that the potential of the fourth node reaches a preset value; and at the light-emitting stage, the first switch sub-circuit and the first light-emitting control sub-circuit are turned on, the potential of the fourth node is applied to the fifth node, and the driving signal is applied to the light-emitting element, so that the light-emitting element emits light. The specific description may refer to the above descriptions, and is not repeated here. For example, the driving signal may be a driving voltage or a driving current used to drive the light-emitting element.

At least one embodiment of the present disclosure also provides a display substrate, which includes the pixel circuit provided by any embodiment.

FIG.4Ais a first schematic plan view of the display substrate provided by an embodiment of the present disclosure, andFIG.4Aillustrates the layout of a display area of the display substrate. As shown inFIG.4A, a display area101of the display substrate20is divided into a main display area21and relevant areas of a photosensitive element (such as a camera). For example, the relevant areas include a first display area22and a second display area23, and the first display area at least partially or totally surrounds the second display area23. For example, the photosensitive element is provided corresponding to the second display area23.

FIG.4Bis a second schematic plan view of the display substrate provided by an embodiment of the present disclosure, andFIG.4Billustrates a pixel layout of the display substrate. As shown inFIG.4B, the display substrate20includes a plurality of pixel circuits100located in the display area101, andFIG.4Bschematically illustrates the pixel circuit100with a rectangular block. For example, each pixel circuit100may adopt the pixel circuit provided by any one embodiment of the present disclosure. For example, the structure of the pixel circuit100may be adjusted correspondingly when the area where the pixel circuit100is located is different.

As shown inFIG.4B, the plurality of pixel circuits100are arranged in multiple rows and multiple columns along a first direction D1and a second direction D2; and the first direction D1and the second direction D2are different, for example, the two are orthogonal. For example, the pixel rows and the pixel columns do not necessarily extend linearly, may also extend along a curve (such as a fold line), and the curve generally extends along the first direction D1or the second direction D2. For example, the density of the pixel circuits in the first display area22and that in the main display area21are the same, thereby improving the uniformity of the process.

For example, in the main display area21, a connection line between the pixel circuit and the light-emitting element driven by the pixel circuit of each sub-pixel is relatively short, for example, the pixel circuit and the light-emitting element of the sub-pixel both are located in the main display area, which may realize the in-situ light emission. For example, the pixel circuits100in the main display area21may adopt the pixel circuits shown inFIGS.1A-1BorFIGS.2A-2B.

For example, the pixel circuit structure in the second display area23is not complete, and a part of the pixel circuit structure may be in the second display area, which aims at increasing the light transmission rate of the second display area23, thereby improving the photosensitive effect of the photosensitive element. For example, in order to improve the display uniformity, the light-emitting element is arranged in the second display area23, but a main structure of the pixel circuit driving the light-emitting element is arranged in the first display area22on the periphery of the second display area23.FIG.4Bschematically illustrates the light-emitting element in the second display area23with a circle, and the light-emitting element is connected with the pixel circuit structure or a signal line in the first display area22through a connection line (illustrated as the fold line inFIG.4B). When one side of the display substrate opposite to the display side is provided with the photosensitive element, the to-be-detected light reaches the photosensitive element mainly via the second display area23, which is described in detail below.

For example, in the first display area22, the pixel circuits of some sub-pixels are used to drive the light-emitting elements located in the second display area23. In order to facilitate the description, these sub-pixels are referred to as first sub-pixels hereinafter.

For example, the size of the pixel circuits in the first display area22is reduced in the first direction D1, so that the number of the pixel circuits is greater than the number of the light-emitting elements. For example, the pixel circuits of the sub-pixels may adopt the pixel circuits shown inFIGS.3A-3B. For example, there are some in-situ light-emitting sub-pixels in the first display area22.

For example, the driving sub-circuit122and the first switch sub-circuit124of the first sub-pixel are located in the first display area22, and the first light-emitting control sub-circuit170and the light-emitting element120are located in the second display area23; and the second terminal of the first light-emitting control sub-circuit is connected with the first electrode of the light-emitting element120electrically, and the first terminal of the first light-emitting sub-circuit is connected electrically with the first switch sub-circuit located in the first display area22through a connection line (corresponding to the fourth node N4).

For example, the connection line extends to the first display area22from the second display area23, and is prone to form parasitic capacitance with other conductive structures during the extension; the first light-emitting control sub-circuit170is arranged in the second display area, that is, arranged at one end of the connection line close to the light-emitting element, and can space the connection line apart from the light-emitting element effectively, which prevents the connection line from being connected with the light-emitting element directly, so that the adverse effect of the parasitic capacitor at the connection line on the light emission is reduced effectively. For example, before the light-emitting stage, the first switch sub-circuit124may be turned on, and the first light-emitting control sub-circuit170is turned off, so that the connection line may be pre-charged (for example, charged to the lighting voltage of the light-emitting element); and at the light-emitting stage, the first switch sub-circuit124and the first light-emitting control sub-circuit170are turned on simultaneously, and under the action of the driving signal, the prepared potential on the connection line is copied to the pixel electrode rapidly, so that the display Mura phenomenon caused by the occupation of the charging time needed by the parasitic capacitor on the light-emitting time is avoided, and the light-emitting uniformity is improved.

As shown inFIG.4B, the display substrate includes a plurality of gate lines11and a plurality of data lines12. For example, the gate lines11extend along the first direction D1, and the data lines12extend along the second direction D2.FIG.4Bonly illustrates a general position relationship of the gate lines11, the data lines12and the pixel circuits100in the display substrate, and details may be designed according to actual requirements.FIG.4Billustrates that each gate line11and each data line12pass through the first display area21and the second display area22, which is only used for facilitating the drawing, but shall not be used as the limitation to the present disclosure.

For example, as shown inFIG.4B, the display substrate20includes a non-display area102located outside the display area101. The display substrate may also include a gate driving circuit13and a data driving circuit14located in the non-display area. The gate driving circuit13is connected with a pixel circuit unit100through the gate lines11to provide various scanning signals and control signals, and the data driving circuit14is connected with the pixel circuits100through the data lines12to provide the data signal Vd.

For example, the display substrate20may also include a control circuit (not shown). For example, the control circuit is configured to control the data driving circuit14to apply the data signal and control the gate electrode driving circuit to apply the scanning signal. One example of the control circuit is a sequence control circuit (T-con). The control circuit may be in various forms, for example, including a processor and a storage device; and the storage device includes an executable code, and the processor runs the executable code to execute the above detecting method.

For example, the processor may be a central processing unit (CPU) or other forms of processing devices with data processing capacity and/or instruction execution capacity, and may include, for example, a microprocessor, a programmable logic controller (PLC), etc.

For example, the storage device may include one or more computer program products; and the computer program product may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. The volatile memory, for example, may include a random access memory (RAM) and/or a cache. The nonvolatile memory, for example, may include a read only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer readable storage media; and the processor may run desirable functions of the program instruction. Various application programs and various data may also be stored in the computer readable storage media.

The structure of the display substrate provided by at least one embodiment of the present disclosure is exemplarily explained below by taking the pixel circuits shown inFIGS.3A-3Badopted by the first sub-pixel as an example in conjunction withFIGS.5A-5C,FIG.6,FIGS.7A-7B,FIGS.8A-8BandFIGS.9A-9B, but this does not limit the present disclosure.

FIG.5Ais a schematic diagram of a first sub-pixel in a display substrate20provided by at least one embodiment of the present disclosure;FIG.5Bis a sectional view ofFIG.5Aalong a sectional line I-I′; andFIG.5Cis a sectional view ofFIG.5Aalong a sectional line II-II′. It should be noted that for the sake of clarity,FIG.5BandFIG.5Crespectively omit some structures without direct electrical connection at the sectional line.

As shown inFIGS.5A-5B, except for the first light-emitting control sub-circuit (T8), other sub-circuits in the pixel circuit of the first sub-pixel all are located in the first display area22; and the first light-emitting control sub-circuit and the light-emitting element120of the first sub-pixel are located in the second display area23. The first light-emitting control sub-circuit is connected with a pixel structure located in the first display area22through the connection line270. One end of the connection line270is connected with the first light-emitting control sub-circuit electrically through a via hole352and the connection line270extends to the first display area22from the second display area23so as to be connected with the first switch sub-circuit and the second switch sub-circuit electrically. For example, the other end of the connection line270is connected with the second terminal (i.e. T5d) of the first switch sub-circuit and the first terminal (i.e. T9s) of the second switch sub-circuit electrically through a via hole351. For example, the connection line270is made of a transparent conductive material, which is conducive to increasing the light transmission rate of the second display area23.FIG.5Aonly illustrates the connecting structure at two ends of the connection line270, and schematically illustrates a structure of a middle portion of the connection line with a dotted line. The sectional line I-I′ extends to the second display area23from the first display area22along the connection line270.

It may be seen fromFIGS.5A-5Cthat a semiconductor layer102, a first insulating layer301, a first conductive layer201, a second insulating layer302, a second conductive layer202, a third insulating layer303, a third conductive layer203, a fourth insulating layer304, a fourth conductive layer204, a fifth insulating layer305, a fifth conductive layer205, a sixth insulating layer306, a sixth conductive layer206, a seventh insulating layer307and a seventh conductive layer207are arranged on an base substrate101successively, thereby forming the structure of the display substrate as shown inFIG.5A.

Corresponding toFIG.5A,FIG.6illustrates the semiconductor layer102and the first conductive layer (a gate electrode layer)201of the transistors T1-T7and T9in the first display area22in the pixel circuit of the first sub-pixel;FIG.7Aillustrates the second conductive layer202;FIG.7Billustrates the second conductive layer202on the basis ofFIG.6;FIG.8Aillustrates the third conductive layer203;FIG.8Billustrates the third conductive layer203on the basis of theFIG.7B; andFIG.9AandFIG.9Billustrate the fourth conductive layer204and the fifth conductive layer205respectively.

To facilitate the description, Tng, Tns, Tnd and Tna are used to indicate the gate electrode, the first electrode, the second electrode and an active layer of the nthtransistor Tn respectively in the following description, wherein n is 1-9.

It should be noted that the term “arranged in the same layer” in the present disclosure means that two (or more than two) structures are formed by a same deposition process and patterned by a same patterning process, and are made from the same or different materials. The term “integrated structure” in the present disclosure means that two (or more than two) structures are interconnected structures that are formed by the same deposition process and patterned by the same patterning process, and are made from the same or different materials.

For example, as shown inFIG.6, the first conductive layer201includes a gate electrode of each transistor and some scanning lines and control lines.FIG.6illustrates the gate electrodes T1g-T7gand T9gof the transistors T1-T7and T9in the first sub-pixel with a dashed line box.

The semiconductor layer102includes active layers T1a-T7aand T9aof the transistors T1-T7and T9. As shown inFIG.6, the active layers of the transistors T1-T7and T9are connected with each other into an integrated structure. For example, referring toFIG.5C, the first conductive layer also includes a gate electrode T8gof the eighth transistor T8located in the second display area23, and the semiconductor layer102also includes an active layer T8aof the eighth transistor T8.

For example, the display substrate20adopts a self-alignment process, and the first conductive layer201is used as a mask to perform conducting processing (such as doping processing) on the semiconductor layer102, to enable a portion of the semiconductor layer102that is not covered by the first conductive layer201to become a conductor, so that portions of the semiconductor layer located at two sides of the active layer (a channel area) of each transistor become conductors, thereby forming the first electrode and the second electrode of the transistor respectively.

The stability of the gate electrode voltage of the driving transistor greatly influences the display uniformity of the display substrate. For example, if the leakage phenomenon of the gate electrode of the driving transistor is serious, the gate electrode voltage of the driving transistor may be compensated insufficiently at a threshold compensation stage, that is, the threshold voltage of the driving transistor may not be compensated completely, so that the driving current at the light-emitting stage is still related to the threshold voltage Vth of the driving transistor, resulting in the reduction of the brightness uniformity of the display device.

For example, as shown inFIG.6, the third transistor T3and the sixth transistor T6adopt a double-gate structure respectively, so that the gate control capacity of the transistor may be improved, and the leakage current may be reduced. Since the third transistor T3and the sixth transistor T6both are directly connected with the gate electrode of the first transistor T1(i.e. the driving transistor), the stability of the third transistor T3and the sixth transistor T6affects the stability of the voltage of the gate electrode (the node N1) of the first transistor T1directly. The double-gate structure is used to improve the gate control capacity of the third transistor T3and the sixth transistor T6, which is conducive to reducing the leakage current of the transistor and maintaining the voltage of the node N1, so that at the compensation stage, the threshold voltage of the first transistor T1can be compensated sufficiently, thereby improving the display uniformity of the display substrate at the light-emitting stage.

For example, the first conductive layer201also includes a plurality of scanning lines210, a plurality of reset control lines220and a plurality of light-emitting control lines230that are insulated to each other. For example, as shown inFIG.6, each row of sub-pixels corresponds to a reset control line220, a scanning line210, a second light-emitting control line230and a first light-emitting control line (280,290).

The scanning line210is connected (or integrated) with the gate electrode of the second transistor T2in a corresponding row of sub-pixels to provide the first scanning signal Ga1; the reset control line220is connected with the gate electrode of the sixth transistor T6in a corresponding row of sub-pixels electrically to provide the second reset control signal Rst2; and the second light-emitting control line230is connected with the gate electrode of the fourth transistor T4in a corresponding row of sub-pixels electrically to provide the second light-emitting control signal EM2.

For example, as shown inFIG.6, the scanning line210is also connected with the gate electrode of the third transistor T3electrically to provide the second scanning signal Ga2, that is, the first scanning signal Ga1and the second scanning signal Ga2may be the same signal; and the light-emitting control line230is also connected with the gate electrode of the fifth transistor T5electrically to provide the first switch control signal SW1, that is, the first light-emitting control signal EM1and the second light-emitting control signal EM2are the same signal.

Referring toFIG.5AandFIG.5Ctogether, the first light-emitting control line includes a first light-emitting control line portion280(an example of an auxiliary light-emitting control line of the present disclosure) located in the first display area22and a second light-emitting control line portion290located in the second display area23; and the first light-emitting control line portion280and the second light-emitting control line portion290are connected electrically with each other (as shown by the dotted line inFIG.5A). The second light-emitting control line portion290is connected with (or integrated with) the gate electrode of the eighth transistor T8(an example of the light-emitting control transistor of the present disclosure) of a corresponding row of sub-pixels to provide the first light-emitting control signal EM1; and the first light-emitting control line portion280is connected with (or integrated with) the gate electrode of the ninth transistor T9of a corresponding row of sub-pixels electrically to provide the second switch control signal SW2, that is, in the embodiments of the present disclosure, the first light-emitting control signal EM1and the second switch control signal SW2are the same signal, but this does not limit the present disclosure. For example, the second light-emitting control line portion290is made of a transparent conductive material to increase the light transmission rate of the second display area23.

For example, the main display area21is provided with second sub-pixels, for example, the second sub-pixel is an in-situ light-emitting sub-pixel; and all sub-circuits (transistors) in the pixel circuit of the second sub-pixel are located in the main display area21, that is, the first light-emitting control sub-circuit and other sub-circuits are not separated as shown inFIG.5A. For example, the pixel circuit of the second sub-pixel may not include the second switch sub-circuit, for example, may adopt the pixel circuits shown inFIGS.1A-1BorFIGS.2A-2B; in this case, the first light-emitting control sub-circuit may be located at a position where the second switch sub-circuit shown inFIG.5Ais located, that is, the eighth transistor T8is located at the position where the ninth transistor T9is located; and the first light-emitting control line portion280shown inFIG.5Aserves as the first light-emitting control signal EM1that controls the first light-emitting control sub-circuit.

Therefore, in the pixel circuit shown inFIG.5A, the arrangement of the second switch sub-circuit (T9) and the first light-emitting control line portion280is conducive to improving the layout uniformity of the pixel circuits of the second display area23and the first display area21, thereby improving the process uniformity of a production process.

For example, the gate electrode of the seventh transistor T7of the present row of pixel circuits is connected electrically with the reset control line220corresponding to the next row of pixel circuits (that is, the pixel circuit rows corresponding to the scanning line that is turned on sequentially after the scanning line corresponding to the present row according to a scanning sequence of the scanning lines) to receive the first reset control signal Rst1.

For example, as shown inFIGS.7A-7B, the second conductive layer202includes the first capacitive electrode Ca. The first capacitive electrode Ca overlaps with the gate electrode T1gof the first transistor T1in a direction perpendicular to the base substrate101to form the storage capacitor Cst, that is, the gate electrode T1gof the first transistor T1serves as the second capacitive electrode Cb of the storage capacitor Cst. For example, the first capacitive electrode Ca includes an opening222; and the opening222exposes at least part of the gate electrode T1gof the first transistor T1to allow the gate electrode T1gto be connected electrically with other structures.

For example, the second conductive layer202may also include a plurality of reset voltage lines240extending along the first direction D1, and the plurality of reset voltage lines240are respectively connected with the plurality of rows of sub-pixels in a one-to-one correspondence. The reset voltage line240is connected electrically with the first electrode of the sixth transistor T6in the corresponding row of sub-pixels to provide the second reset voltage Init2.

For example, referring toFIG.7BandFIG.8B, the first electrodes of the seventh transistors T7in the present row of sub-pixels are connected electrically with the reset voltage line240corresponding to the next row of sub-pixels to receive the first reset voltage Init1.

For example, as shown inFIGS.7A-7B, the second conductive layer202may also include a shielding electrode221. For example, the shielding electrode221overlaps with the first electrode T2sof the second transistor T2in a direction perpendicular to the base substrate101, so that the signal in the first electrode T2sof the second transistor T2is protected against the interference of other signals. Since the first electrode T2sof the second transistor T2is configured to receive the data signal Vd, and the data signal Vd determines a display gray level of the sub-pixel, the shielding electrode221improves the stability of the data signal, thereby improving the display performance.

For example, referring toFIG.7BandFIG.6, the shielding electrode221also at least partially overlaps with the second electrode T6dof the sixth transistor T6in the direction perpendicular to the base substrate101to improve the stability of the signal on the second electrode T6d, so that the stability of the sixth transistor T6is improved, and the gate electrode voltage of the first transistor T1is further stabilized.

For example, the shielding electrode221and the first electrode T2sof the second transistor T2right opposite to (overlapping with) the shielding electrode and the second electrode T6dof the sixth transistor T6form the stable capacitor. For example, the shielding electrode221is configured to load the constant voltage; and since the voltage difference between the two ends of the capacitor cannot be changed suddenly, the stability of the voltage on the first electrode T2cof the second transistor T2, the conductive area T3cof the third transistor T3and the second electrode T6dof the sixth transistor T6is improved. For example, the shielding electrode221is connected with a power supply line250in the third conductive layer203to load the first power supply voltage VDD.

For example, as shown inFIGS.7A-7B, the shielding electrode221is L-shaped or V-shaped, and includes a first branch221aand a second branch221bwith different extension directions. The first branch221aat least partially overlaps with the second electrode T6dof the sixth transistor T6in the direction perpendicular to the base substrate101; and the second branch221bat least partially overlaps with the first electrode T2sof the second transistor T2in the direction perpendicular to the base substrate101. For example, the first branch221aextends along the second direction D2, and the second branch221bextends along the first direction D1.

For example, as shown inFIGS.8A-8B, the third conductive layer203includes a plurality of power supply lines250extending along the second direction D2. For example, the plurality of power supply lines250are respectively electrically connected with the plurality of columns of sub-pixels to provide the first power supply voltage VDD in a one-to-one correspondence. Referring toFIG.6, the power supply line250is connected with the first capacitive electrodes Ca in a corresponding column of sub-pixels through a via hole342, and connected with the first electrode T4dof the fourth transistor T4electrically through a via hole343. For example, the power supply line250is also connected with the shielding electrode221electrically through the via hole341, so that the shielding electrode221has a constant potential, and the shielding capacity of the shielding electrode is improved. For example, the via hole342and the via hole341each passes through the third insulating layer303; and the via hole343passes through the first insulating layer301, the second insulating layer302and the third insulating layer303.

For example, the third conductive layer203also includes a plurality of data lines12extending along the second direction D2. For example, the plurality of data lines12are respectively electrically connected with a plurality of columns of sub-pixels to provide the data signal in a one-to-one correspondence. For example, the data line12is connected with the first electrode T2sof the second transistor T2in a corresponding column of sub-pixels electrically through a via hole346to provide the data signal. For example, the via hole346passes through the first insulating layer301, the second insulating layer302and the third insulating layer303.

For example, the data line12includes a data line main body extending along the second direction D2; since the data line main body is small in width, the data line12also includes a data line projection121extending from the data line main body for facilitating the arrangement of the via hole, and the data line projection121at least partially overlaps with the via hole346in the direction perpendicular to the base substrate.

For example, as shown inFIGS.5A-5BandFIGS.8A-8B, the third conductive layer203also includes a connection electrode231, one end of the connection electrode231is electrically connected with the gate electrode T1g(i.e. the second capacitive electrode Cb) of the first transistor T1through the opening222in the first capacitive electrode Ca and the via hole344in the insulating layer, and the other end of the connection electrode231is connected with the second electrode T3dof the third transistor T3through the via hole345, so that the second capacitive electrode Cb is connected with the second electrode T3dof the third transistor T3electrically. For example, the via hole344passes through the second insulating layer302and the third insulating layer303. For example, the via hole345passes through the first insulating layer301, the second insulating layer302and the third insulating layer303.

As shown inFIGS.5A-5B,FIG.6andFIGS.8A-8B, the third conductive layer203also includes a connection electrode232; and the connection electrode232is electrically connected with the second electrode T5dof the fifth transistor T5through a via hole349, and also electrically connected with the connection line270through a via hole351. For example, the via hole349passes through the first insulating layer301, the second insulating layer302and the third insulating layer303. The via hole351passes through the fourth insulating layer304and the fifth insulating layer305.

For example, as shown inFIGS.8A-8B, the third conductive layer203also includes a connection electrode233; one end of the connection electrode233is connected with a reset voltage line240electrically through a via hole348, and the other end of the connection electrode233is connected with the first electrode T7sof the seventh transistor T7electrically through a via hole347, so that the first electrode T7sof the seventh transistor T7may receive the first reset voltage Init1from the reset voltage line240. For example, the via hole348passes through the third insulating layer303. For example, the via hole347passes through the first insulating layer301, the second insulating layer302and the third insulating layer303.

For example, as shown inFIGS.8A-8B, the third conductive layer203also includes a connection electrode234; and the connection electrode234is connected with the first electrode T9sof the ninth transistor T9and the second electrode T7dof the seventh transistor electrically through a via hole (not shown). The connection electrode234is arranged to be consistent with patterns of the third conductive layer203in the main display area21so as to improve the etching uniformity. For example, in the main display area21, the second electrode T7dof the seventh transistor is electrically connected with the first electrode of the light-emitting element through the connection electrode234.

For example,FIG.8Billustrates two reset voltage lines240; the reset voltage line240that is correspondingly connected with the first electrode of the seventh transistor T7in the previous row of sub-pixels is connected with the first terminal of the sixth transistor T6of the present row of sub-pixels to provide the second reset voltage Init2; and the reset voltage line240that is correspondingly connected with the first electrode of the seventh transistor T7in the present row of sub-pixels is connected with the sixth transistor T6of the next row of sub-pixels to provide the second reset voltage Init2.

As shown inFIG.9A, the fourth conductive layer204includes a connection electrode241and a shielding electrode242. Referring toFIG.3A, the connection electrode241is electrically connected with the connection electrode234through a via hole (not shown). The connection electrode241is arranged to be consistent with patterns of the fourth conductive layer204in the main display area21so as to improve the etching uniformity. For example, in the main display area21, the second electrode T7dof the seventh transistor is electrically connected with the first electrode of the light-emitting element through the connection electrode234and the connection electrode241.

For example, in the direction perpendicular to the base substrate, the shielding electrode242at least partially overlaps with the connection electrode231to shield the connection electrode231, so as to improve the stability of the gate electrode signal of the first transistor T1(i.e. the driving transistor). For example, the pixel circuit in the first display area22is electrically connected with the first light-emitting control sub-circuit in the second pixel area23through a connection line (referring to the connection line270′ ofFIG.9B), the connection line is prone to overlap with the connection electrode231in the direction perpendicular to the base substrate during the extension, and the signal on the connection line is prone to affect the gate signal on the connection electrode231. By arranging the shielding electrode242, the stability of the gate signal of the driving transistor may be improved, thereby improving the display quality. For example, the shielding electrode242is connected with a power supply line250electrically through a via hole (not shown) to load the first power supply voltage VDD.

For example, an orthographic projection of the shielding electrode242on the base substrate covers the orthographic projection of the connection electrode231on the base substrate, thereby improving the shielding effect.

For example, the shielding electrode242at least partially overlaps with the second electrode T6dof the sixth transistor T6in the direction perpendicular to the base substrate101to improve the stability of the signal on the second electrode T6d, so that the stability of the sixth transistor T6is improved, and the gate electrode voltage of the first transistor T1is further stabilized.

FIG.9Billustrates a pattern of the fifth conductive layer205corresponding to the position of the first sub-pixel. As shown inFIG.9B, besides the lowermost connection line270connected with the first sub-pixel, the fifth conductive layer205also includes a plurality of connection lines270′ connected with other sub-pixels; and the connection lines270′ pass through the position of the first sub-pixel during the extension.

Referring toFIG.5AandFIG.5C, the third conductive layer203may also include a connection electrode235located in the second display area23; and the fourth conductive layer204may also include a connection electrode243located in the second display area23. The connection electrode235and the connection electrode243correspond to the eighth transistor T8, for example, the number of the connection electrode235and the connection electrode243is two respectively; and the two connection electrodes235are arranged in a one-to-one correspondence with the two connection electrodes243, and correspond to the two ends of the gate electrode T8gof the eighth transistor T8, and the two ends of the gate electrode T8gare connected with the second light-emitting control line portion290located above respectively through the corresponding connection electrodes235and243.

For example, referring toFIGS.5A-5C, the third conductive layer203may also include a connection electrode236(an example of the first connection electrode of the present disclosure) and a connection electrode237located in the second display area23; the connection electrodes236and237correspond to the first electrode T8sand the second electrode T8dof the eighth transistor T8respectively; and the connection electrode236is electrically connected with the first electrode T8sof the eighth transistor T8through a via hole355(an example of the first via hole of the present disclosure), and the connection electrode237is electrically connected with the second electrode T8dof the eighth transistor through a via hole354(an example of the second via hole of the present disclosure). The connection electrode236is also connected electrically with the connection line270located above through a via hole352(another example of the first via hole of the present disclosure), so that the first electrode T8sof the eighth transistor T8is connected with the connection line270electrically. For example, the fourth conductive layer204may also include a connection electrode244; the connection electrode244corresponds to the connection electrode237and is connected with the connection electrode236electrically through a via hole353(another example of the second via hole of the present disclosure); and the connection electrode236is connected electrically with the first electrode134of the light-emitting element located above through a via hole340, so that the second electrode T8dof the eighth transistor T8is connected to the first electrode134of the light-emitting element electrically.

The connection electrodes235,236,237,243and244all serve as transfer electrodes, and lead the first electrode/the second electrode of the transistor located below out to be connected electrically with the conductive structure (the signal line or electrode) that is located above; the arrangement can avoid poor connection, broken line or unevenness caused by excessively deep filling depth of the conductive materials in the direction perpendicular to the base substrate due to the direct penetration of the via holes; and by arranging the transfer electrode, the depth of the via hole is reduced, and the contact yield is improved.

As shown inFIG.5B, the via holes340,353and354at the second electrode of the eighth transistor T8do not overlap with each other in the direction perpendicular to the base substrate.

Referring toFIGS.5A-5C, the fifth conductive layer205includes the connection line270; and the connection line270extends to the second display area23from the first display area22, so that the circuit structure located in the first display area22is connected with the circuit structure located in the second display area23. One end of the connection line270is connected electrically with the second electrode T5dof the fifth transistor T5/the first electrode T9sof the ninth transistor T9through the via hole351, and the other end of the connection line270is connected electrically with the first electrode T8sof the eighth transistor T8through the via hole352.

Referring toFIGS.5A-5C, the sixth conductive layer206includes a second light-emitting control line portion290, for example, the second light-emitting control line portion290is located in the second display area23, and the second light-emitting control line portion290is connected electrically with the connection electrode243located below through a via hole, so as to be connected to the gate electrode T8gof the eighth transistor T8to provide the first light-emitting control signal EM1.

Referring toFIGS.5A-5B, the seventh conductive layer207includes the first electrode134of the light-emitting element120.

For example, referring toFIGS.5A-5B, the display substrate20may also include a pixel defining layer308located on the first electrode of the light-emitting element. An opening is formed in the pixel defining layer308to expose at least part of the pixel electrode134, thereby defining an opening area (i.e. an effective light-emitting area)600of each sub-pixel of the display substrate. A light-emitting layer136of the light-emitting element120is at least formed in the opening (the light-emitting layer136may also cover part of the surface of the pixel defining layer at one side away from the first electrode of the light-emitting element), and the second electrode135is formed on the light-emitting layer136, thereby forming the light-emitting element120. For example, the second electrode135is a common electrode and is entirely arranged in the display substrate20. For example, the pixel electrode134is an anode of the light-emitting element, and the second electrode135is a cathode of the light-emitting element.

FIG.5Aillustrates a position of the opening area600on the first electrode of the light-emitting element. For example, the first electrode134includes an electrode main body portion134aand an electrode protrusion portion134b; the electrode main body portion134ais used to contact the light-emitting layer136of the light-emitting element; the electrode protrusion portion134bis connected with the connection electrode244electrically through the via hole340; and the electrode main body portion134adoes not overlap with the via hole340in the direction perpendicular to the base substrate, so that the via hole340is prevented from affecting the evenness of the light-emitting layer in the opening area and from affecting the light-emitting quality. For example, the electrode main body portion134ais in a polygonal shape, such as quadrangle, pentagon or hexagon. For example, the electrode main body portion134ahas a symmetrical axis extending along a second direction.

For example, as shown inFIGS.5A-5B, the orthographic projection of the first electrode134of the light-emitting element on the base substrate covers the orthographic projection of the connection electrode236on the base substrate completely. Because the connection electrode236is generally made of a metal material with low light transmission rate, the arrangement can prevent the connection electrode236from affecting the light transmission rate of the second display area23, and also can prevent the connection electrode236from occupying the effective opening area, thereby improving the opening rate of the display substrate.

For example, as shown inFIGS.5A-5B, the orthographic projection of the via hole340/353/354at the second electrode of the eighth transistor T8on the base substrate is further away from the orthographic projection of the electrode main body portion134aof the first electrode of the light-emitting element on the base substrate than the orthographic projection of the via hole352/355at the first electrode of the eighth transistor T8.

Since the number of the via holes at the second electrode of the eighth transistor T8is large, a total depth of the via holes is large, and the impact on the evenness of the first electrode of the light-emitting element located above is great, arranging the via holes at the second electrode of the eighth transistor T8away from the electrode main body portion134acan prevent the via holes from affecting the evenness of the electrode main body portion134aand the light-emitting layer thereon and from affecting the light-emitting quality.

For example, referring toFIGS.5A-5B, in the direction perpendicular to the base substrate, the connection line270is prone to at least partially overlap with other conductive structures (such as the first electrode134of the light-emitting element of the first sub-pixels and/or the first electrode of the light-emitting element of other sub-pixels) during the extension, thereby forming the parasitic capacitor Cp. The eighth transistor T8is arranged to be spaced between the connection line270and the first electrode of the light-emitting element, and the direct connection between the connection line270and the light-emitting element can be avoided, so that adverse effect of the parasitic capacitor at the connection line on the light emission can be reduced effectively. For example, before the light-emitting stage, the connection line may be pre-charged (for example, charged to the lighting voltage of the light-emitting element); and after entering the light-emitting stage, the prepared potential on the connection line270is copied to the first electrode of the light-emitting element rapidly, so that the display Mura phenomenon caused by the occupation of the charging time needed by the parasitic capacitor on the light-emitting time can be avoided, and the light-emitting uniformity is improved.

For example, referring toFIGS.5A-5B, in the direction perpendicular to the base substrate, the connection line270at least partially overlaps with the electrode main body portion of the first electrode of the light-emitting element; and the second light-emitting control line portion290at least partially overlaps with the first electrode of the light-emitting element but does not overlap with or hardly overlaps with the electrode main body portion134a. For example, in the direction perpendicular to the base substrate, the second light-emitting control line portion290is located at one side of the connection line270close to the first electrode134of the light-emitting element, so that the connection line270is prevented from affecting the evenness of the light-emitting layer in the opening area.

For example, the base substrate101may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., and may also be formed by a flexible material with good heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, poly acrylates, polyarylates, polyetherimide, polyethersulfone, polyethyleneterephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TCA), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc.

For example, the material of the semiconductor layer102includes but is not limited to a silicon material (amorphous silicon (a-Si), and polycrystalline (p-Si)), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (six thiophene, poly(thiophene), etc.).

For example, the materials of the first to the fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by combining the above metals, or conductive metal oxide materials such as indium tin oxide (ITO), indium-zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

For example, the materials of the fifth conductive layer205and the sixth conductive layer206are transparent conductive materials, such as metal oxide materials, such as indium tin oxide (ITO), indium-zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

For example, the light-emitting element120is a top emitting structure, and the first electrode (i.e. the pixel electrode)134has reflectivity, and the second electrode135has transmissivity or semi-transmissivity. For example, the first electrode134is an anode, and the second electrode135is a cathode. For example, the first electrode134is an ITO/Ag/ITO laminated structure; the transparent conductive material ITO is a high-work-function material, and when the transparent conductive material contacts the light-emitting material directly, a hole injection rate may be increased; and the metal material Ag is conducive to increasing the reflectivity of the first electrode. For example, the second electrode135is a low-work-function material serving as a cathode, such as semi-transparent metal or metal alloy material such as Ag/Mg alloy material.

For example, the first insulating layer301, the second insulating layer302, the third insulating layer303, the fourth insulating layer304, the fifth insulating layer305and the sixth insulating layer306, for example, are inorganic insulating layers such as silicon oxide, silicon nitride and silicon oxides such as silicon oxynitride, silicon nitride or silicon oxynitride, or insulating materials including metal oxynitride such as aluminum oxide and titanium nitride. For example, the seventh insulating layer307and the pixel defining layer308are organic insulating materials respectively such as polyimide (PI), acrylic acid, epoxy resin, polymethyl methacrylate (PMMA), etc. For example, the seventh insulating layer307is a flat layer; and for example, the material of the seventh insulating layer307is a photoresist material.

At least one embodiment of the present disclosure also provides a display device. The display device includes the display substrate20provided by any one of the above embodiments and a sensor.FIG.10Aillustrates a structural schematic diagram of the display device40provided by some embodiments of the present disclosure; andFIG.10Bis a sectional view ofFIG.10Aalong a sectional line C-C′.

As shown inFIG.10A, the sensor401is correspondingly arranged in the second display area23of the display substrate20and arranged at one side of the display substrate opposite to the display side, for example, arranged at the side of the base substrate101away from the light-emitting element. The sensor401is, for example, a photoelectric sensor, and is configured to receive light from the first side of the display substrate and convert the light into an electric signal for imaging. For example, the light reaches the sensor from the display side via the second display area23, and for example, the light is visible light or infrared light. For example, in the direction perpendicular to the base substrate, the sensor401at least partially overlaps with the first light-emitting control sub-circuit (such as the eighth transistor T8) of the first sub-pixel.

For example, the display device40also includes an encapsulation layer208and a cover plate209arranged on the display substrate20; the encapsulation layer208is configured to seal the light-emitting element in the display substrate20so as to prevent external moisture and oxygen from penetrating into the light-emitting element and the driving circuit to damage the devices. For example, the encapsulation layer208includes an organic film or includes a structure formed by alternately stacking organic films and inorganic films. For example, a water absorption layer (not shown) may also be arranged between the encapsulation layer208and the display substrate20and is configured to absorb residual vapor or sol of the light-emitting element in a preliminary production process. The cover plate208is, for example, a glass cover plate. For example, the cover plate209and the encapsulation layer208may be an integrated structure.

For example, the sensor401may be adhered on the back side (opposite to the display side) of the display substrate20. As shown inFIG.10B, an imaging element401is adhered at one side of the base substrate101away from the second electrode136of the light-emitting element. The sensor401, for example, may be implemented as a camera.

The display device, for example, may be any product or part with a display function, such as a digital photo frame, a smart wristband, a smart watch, a mobile phone, a tablet computer, a monitor, a notebook computer, a navigator and the like.

The above descriptions are only exemplary implementations of the present disclosure, and are not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.