Patent ID: 12190926

DETAILED DESCRIPTION

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “connect”, “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Referring toFIGS.1-6,FIGS.1-6illustrate a layout pattern and corresponding cross-section structures of a MRAM device according to an embodiment of the present invention, in which the right portions ofFIGS.1-6illustrate top views of the MRAM device, the left portions ofFIGS.1-6illustrate cross-section views of the MRAM device, and the dotted portions shown on left portions ofFIGS.1-6are principal elements corresponding to each figure also shown on right portions ofFIGS.1-6. As shown inFIG.1, a substrate12made of semiconductor material is provided, in which the substrate12could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs). Next, a first cell region14, a second cell region16, a third cell region18, and a fourth cell region20are defined on the substrate12, in which each of the cell regions or memory cell regions preferably include two sets of transistors and a MTJ for constituting a 2T1MTJ cell structure.

As shown on the left portion ofFIG.1, an active area22and a shallow trench isolation (STI)24made of silicon oxide separating the active area22are disposed on the substrate12, and active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and a dielectric layer34such as an interlayer dielectric (ILD) layer could also be formed on top of the substrate12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate12, in which the MOS transistors could include transistor elements such as gate structures or gate patterns26,28,30,32, source/drain regions or diffusion regions, spacers, epitaxial layers, and a contact etch stop layer (CESL). The dielectric layer34such as an ILD layer could be formed on the substrate12to cover the MOS transistors, and a plurality of contact plugs36could be formed in the dielectric layer34to electrically connect to the diffusion regions. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

As shown on the right portion ofFIG.1, a plurality of gate patterns26,28,30,32are disposed extending along a first direction such as Y-direction to overlap each of the cell regions. For instance, the gate patterns26,28are extending from the first cell region14to the third cell region18while the gate patterns30,32are extending from the second cell region16to the fourth cell region20. In this embodiment, each of the gate patterns26,28,30,32could include polysilicon gate patterns or metal gate patterns, which are all within the scope of the present invention. A plurality of diffusion regions38,40,42,44are disposed on the substrate12extending along a second direction such as X-direction adjacent to two sides of the gate patterns26,28,30,32. For instance, the diffusion regions38,40are extending from the first cell region14to the second cell region16along the X-direction, the diffusion regions42,44are extending from the third region18to the fourth region20also along the X-direction, and at least a contact plug36could be disposed on each of the diffusion regions38,40,42,44.

As shown on the left portion ofFIG.2, a plurality of metal patterns M1, V1are disposed in the dielectric layer34through single damascene or dual damascene process and connected to the contact plugs36, in which the metal patterns M1are preferably first level metal interconnections while the metal patterns V1are first level contact vias, each of the metal patterns M1include a trench conductor, and each of the metal patterns V1include a via conductor. It should be noted that in the first level metal interconnections or metal patterns M1, part of the metal patterns are bit line patterns BLRfor read operations.

Each of the metal patterns M1, V1could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. The dielectric layer34could include silicon oxide such as tetraethyl orthosilicate (TEOS) or ultra-low k dielectric material, but not limited thereto.

As shown on the right portion ofFIG.2, the metal patterns M1are disposed adjacent to two sides of the gate patterns26,28,30,32and overlapping the diffusion regions38,40,42,44, a bit line pattern BLRis disposed between the diffusion regions38,40and extending from the first cell region14to the second cell region16along the X-direction, and another bit line pattern BLRis disposed between the diffusion regions42,44and extending from the third cell region18to the fourth cell region20along the X-direction. The metal patterns V1made of via conductors are disposed adjacent to two sides of the gate patterns26,28,30,32and overlapping the metal patterns M1made of trench conductors.

As shown on the left portion ofFIG.3, the MRAM device also includes a plurality of metal patterns M2and metal patterns VW, V2disposed in the dielectric layer34and on the metal patterns V1according to single damascene or dual damascene process, in which the metal patterns M2are second level metal interconnections, the metal patterns V2are second level contact vias, each of the metal patterns M2include a trench conductor, and each of the metal patterns VW, V2include via conductors. It should be noted that part of the second level metal interconnections further include bit line patterns BLWfor write operations and source line patterns SL disposed directly under spin orbit torque (SOT) patterns46formed afterwards.

Similar to the aforementioned metal patterns M1and V1, each of the metal patterns M2, VW, V2could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). It should be noted that the metal pattern VWmade of via conductors and disposed directly under the SOT patterns46formed afterwards are preferably made of tungsten (W) while the other metal patterns V2also made of via conductors and directly under the SOT patterns46are preferably made of copper (Cu).

As shown on right portion ofFIG.3, the bit line patterns BLWfrom the second level metal patterns M2are extending from the first cell region14to the second cell region16and/or extending from the third cell region18to the fourth cell region20along the X-direction, the source line patterns SL are also extending from the first cell region14to the second cell region16and/or extending from the third cell region18to the fourth cell region20along the X-direction, the remaining second level metal patterns M2are disposed adjacent to one side such as left side of the gate patterns26,30and overlapping the diffusion regions38,40,42,44on the first cell region14, the second cell region16, the third cell region18, and the fourth cell region20, and the second level contact vias or metal patterns V2are disposed adjacent to one side such as left side of the gate patterns26,30and overlapping the second level metal interconnections or metal patterns M2on the first cell region14, the second cell region16, the third cell region18, and the fourth cell region20.

Next, as shown on the left portion ofFIG.4, the MRAM device includes a SOT layer or SOT pattern46and a MTJ48disposed on and directly contacting the metal pattern VW. Preferably, the SOT pattern46is serving as a channel for the MRAM device as the SOT pattern46could include metals such as tantalum (Ta), tungsten (W), platinum (Pt), or hafnium (Hf) and/or topological insulator such as bismuth selenide (BixSe1-x). It should be noted that since the present invention pertains to a top-pin SOT MRAM device, the bottom surface of the SOT pattern46is preferably connected to two metal patterns VWat the same time while the top surface of the SOT pattern46is connected to a pinned layer of the MTJ48.

In this embodiment, the formation of the MTJ48could be accomplished by sequentially depositing a pinned layer, a barrier layer, and a free layer on the SOT pattern46. Preferably, the pinned layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB) or cobalt-iron (CoFe). Alternatively, the pinned layer could also be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer could be altered freely depending on the influence of outside magnetic field.

As shown on the right portion ofFIG.4, the SOT patterns46are disposed adjacent to one side such as left side of the gate patterns26,30on the first cell region14, the second cell region16, the third cell region18, and the fourth cell region20and extending along the Y-direction while overlapping the lower level metal patterns M2including the bit line patterns BLWand the source line patterns SL. The MTJs48are also disposed adjacent to one side such as left side of the gate patterns26,30on the first cell region14, the second cell region16, the third cell region18, and the fourth cell region20. Preferably, the MTJs48are extending along the X-direction on the SOT patterns46.

Next, as shown on the left portion ofFIG.5, the MRAM device also includes a plurality of metal patterns M3and metal patterns V3in the dielectric layer34according to single damascene or dual damascene process and on top of the MTJ48and the metal patterns V2, in which the metal patterns M3are third level metal interconnections, the metal patterns V3are third level contact vias, each of the metal patterns M3include a trench conductor, and each of the metal patterns V3include a via conductor. Similar to the aforementioned metal patterns M2and V2, each of the metal patterns M3, V3could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP).

As shown on the right portion ofFIG.5, the third level metal interconnections or third level metal patterns M3are disposed adjacent to one side such as left side of the gate patterns26,30and overlapping the second level contact vias V2, the third level contact vias or metal patterns V3are also disposed adjacent to one side such as left side of the gate patterns26,30and overlapping the third level metal interconnections or metal patterns M3and MTJs48.

Lastly, as shown on the left portion ofFIG.6, the MRAM device further includes fourth level metal interconnections or metal pattern M4connecting to the third level contact vias of metal patterns V3underneath. Similar to the metal patterns M3, each of the metal patterns M4could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP).

As shown on the right portion ofFIG.6, the fourth level metal interconnections or metal patterns M4are disposed adjacent to one side such as left side of the gate patterns26,30on the first cell region14, the second cell region16, the third cell region18, and the fourth cell region20and extending along the Y-direction while overlapping the third level contact vias or metal patterns V3, MTJs48, SOT patterns46, and third level metal interconnections or metal patterns M3underneath.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.