Patent ID: 12249593

DETAILED DESCRIPTION

According to one embodiment, an electronic device includes a first chip, a second chip, a third chip, a first terminal, a second terminal, and an interconnect layer. The first chip includes a first conductive member, a first region, and a second region. The second chip includes a second conductive member, a third region, and a fourth region. The third chip includes a third conductive member, a fifth region, and a sixth region. The interconnect layer is provided between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the fifth region of the third chip, between the first terminal and the fourth region of the second chip, and between the second terminal and the sixth region of the third chip. The interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.

Various embodiments will be described hereinafter with reference to the accompanying drawings.

The drawings are schematic and conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and proportions may be illustrated differently among drawings, even for identical portions.

In the specification and drawings, components similar to those described or illustrated in a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

In the following embodiments, an electronic device is, for example, a semiconductor device.

First Embodiment

FIG.1Ais a schematic cross-sectional view illustrating an electronic device 1 according to a first embodiment.

FIGS.1B and1Care schematic enlarged cross-sectional views of a first chip10of the electronic device 1.

FIG.1Dis a schematic view showing the connectional relationship of the first chip10, a second chip20, and a third chip30of the electronic device 1.

FIG.2Ais a schematic plan view showing an arrangement example of the first chip10, the second chip20, and the third chip30of the electronic device 1.

FIG.2Bis a schematic plan view of the second chip20, the third chip30, and a resin portion51of the electronic device 1.

As shown inFIG.1A, the electronic device 1 according to the first embodiment includes an interconnect layer40, the first chip10, the second chip20, the third chip30, the resin portion51, multiple first terminals81, and multiple second terminals82.

The first chip10includes a first region10aand a second region10b. The second chip20includes a third region20aand a fourth region20b. The third chip30includes a fifth region30aand a sixth region30b.

The direction from the first region10aof the first chip10toward the third region20aof the second chip20is aligned with a first direction. The direction from the second region10bof the first chip10toward the fifth region30aof the third chip30is aligned with the first direction.

The first direction is taken as a Z-axis direction. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

For example, the interconnect layer40is aligned with the X-Y plane.

A second direction from the second chip20toward the third chip30crosses the first direction. In the example, the second direction is aligned with the X-axis direction.

The direction from the first region10aof the first chip10toward the fourth region20bof the second chip20crosses the first direction and the second direction. The direction from the second region10bof the first chip10toward the sixth region30bof the third chip30crosses the first direction and the second direction.

The interconnect layer40is provided between the first region10aof the first chip10and the third region20aof the second chip20, between the second region10bof the first chip10and the fifth region30aof the third chip30, between the fourth region20bof the second chip20and the first terminals81, and between the sixth region30bof the third chip30and the second terminals82.

As shown inFIG.1B, the first chip10includes a substrate12and an interconnect layer14. The thickness along the Z-axis direction of the substrate12is thicker than the thickness along the Z-axis direction of the interconnect layer14.

The substrate12is, for example, a silicon substrate or a glass substrate. The interconnect layer14is, for example, an interconnect layer formed by a damascene process and/or a semi-additive process. The interconnect layer14includes an insulating layer13and a first conductive member11. A high-resistance silicon substrate may be used as the substrate12in the case where the first chip10is a bridge chip that does not include an element and simply functions as only an interconnect. The specific resistance of the high-resistance silicon substrate is, for example, 10 Ωcm or more.

The first conductive member11is, for example, a metal member. The first conductive member11includes multiple electrode terminals11a, and a conductive layer11bconnected to the electrode terminals11a. The conductive layer11bis provided between the substrate12and the electrode terminals11a.

Or, as shown inFIG.1C, the first chip10includes only the interconnect layer14including the first conductive member11and does not include the substrate12. The substrate12can be removed after forming the interconnect layer14in the substrate12.

As shown inFIG.1A, an insulating portion55is provided between the first chip10and the interconnect layer40. For example, the insulating portion55is made of a resin material or an inorganic material. The insulating portion55covers the first conductive member11. For example, the insulating portion55can be injected after connecting the first conductive member11to the interconnect layer40. Or, a formation method may be used in which the insulating portion55is pre-formed in a region including the periphery of the first conductive member11; and the insulating portion55is connected to the interconnect layer40simultaneously with the first conductive member11.

The second chip20includes a second conductive member21as shown inFIG.1A. The second conductive member21is, for example, a metal member. The second conductive member21includes a first signal terminal21a, a first power supply terminal21b, and a conductive layer (not illustrated) connected to the first signal terminal21aand the first power supply terminal21b. The second chip20includes, for example, a logic element. For example, the logic element is used mainly for functions relating to the calculation/control of information.

The third chip30includes a third conductive member31as shown inFIG.1A. The third conductive member31is, for example, a metal member. The third conductive member31includes a second signal terminal31a, a second power supply terminal31b, and a conductive layer (not illustrated) connected to the second signal terminal31aand the second power supply terminal31b. The third chip30includes, for example, a memory element. For example, the memory element is used mainly for functions relating to the storage of information.

The interconnect layer40includes an insulating layer45, a fourth conductive member41, a fifth conductive member42, a sixth conductive member43, and a seventh conductive member44.

The insulating layer45is, for example, a resin layer. The insulating layer45is provided between the fourth conductive member41, the fifth conductive member42, the sixth conductive member43, and the seventh conductive member44. The insulating layer45insulatively separates between the fourth conductive member41, the fifth conductive member42, the sixth conductive member43, and the seventh conductive member44. The insulating layer45may be a layer of an inorganic insulating material.

The fourth conductive member41is provided between the first region10aof the first chip10and the third region20aof the second chip20and connects the first conductive member11of the first chip10and the first signal terminal21aof the second chip20. The fourth conductive member41extends along the Z-axis direction and is, for example, a metal via. Many inter-chip interconnect connections are possible by arranging multiple fourth conductive members41in an array configuration in the X-Y plane.

The fifth conductive member42is provided between the second region10bof the first chip10and the fifth region30aof the third chip30and connects the first conductive member11of the first chip10and the second signal terminal31aof the third chip30. The fifth conductive member42extends along the Z-axis direction and is, for example, a metal via. Many inter-chip interconnect connections are possible by arranging multiple fifth conductive members42in an array configuration in the X-Y plane.

The sixth conductive member43is provided between the fourth region20bof the second chip20and the first terminal81and connects the first power supply terminal21bof the second chip20and the first terminal81.

The seventh conductive member44is provided between the sixth region30bof the third chip30and the second terminal82and connects the second power supply terminal31bof the third chip30and the second terminal82.

The sixth conductive member43and the seventh conductive member44are, for example, metal interconnects. The first terminals81and the second terminals82are external terminals connecting the electronic device 1 to an external circuit. The first terminals81and the second terminals82are, for example, solder balls. The first terminals81and the second terminals82may be metal pads or metal bumps.

The first chip10is provided between the first terminals81and the second terminals82. The direction from the first terminals81toward the first chip10is aligned with the X-axis direction. The direction from the second terminals82toward the first chip10is aligned with the X-axis direction.

The resin portion51covers at least a portion of the side surfaces of the second chip20and the third chip30. The side surfaces cross the X-Y plane. Although an embodiment is shown in the example shown inFIG.1Ain which the surfaces of the second chip20and the third chip30opposite to the interconnect layer40also are covered with the resin portion51, the exposure from the resin portion51of the surfaces opposite to the interconnect layer40is arbitrary.

As shown inFIG.1A, the resin portion51includes a first resin region51a, a second resin region51b, and a third resin region51c. As shown inFIG.2B, the resin portion51further includes a fourth resin region51dand a fifth resin region51e. The first to fifth resin regions51ato51eare continuous with each other.

Although a configuration is used in the example shown inFIG.1Ain which the resin portion51is disposed also at the peripheral portion of the second conductive member21and the peripheral portion of the third conductive member31, the resin portion51may not be disposed at the peripheral portion of the second conductive member21and the peripheral portion of the third conductive member31; for example, a different insulating material may be disposed at the peripheral portion of the second conductive member21and the peripheral portion of the third conductive member31.

The second chip20is provided between the first resin region51aand the third resin region51c. The direction from the first resin region51atoward the third resin region51cis aligned with the X-axis direction. The third chip30is provided between the third resin region51cand the second resin region51b. The third resin region51cis provided between the second chip20and the third chip30. The direction from the third resin region51ctoward the second resin region51bis aligned with the X-axis direction.

The second chip20is provided between the fourth resin region51dand the fifth resin region51e. The third chip30is provided between the fourth resin region51dand the fifth resin region51e. The direction from the fourth resin region51dtoward the fifth resin region51eis aligned with the Y-axis direction.

The interconnect layer40is provided also between the first resin region51aand the first terminals81and between the second resin region51band the second terminals82.

The electronic device 1 according to the first embodiment further includes a fourth chip70, an eighth conductive member52, a ninth conductive member53, and a semiconductor package device60.

The fourth chip70includes, for example, an IPD (Integrated Passive Device) or a passive element. The passive element includes, for example, a discrete component such as a capacitor, an inductor, a resistance element, etc. For example, the fourth chip70is connected to the sixth conductive member43.

The interconnect layer40is provided between the fourth chip70and the fourth region20bof the second chip20. The direction from the fourth chip70toward the second chip20is aligned with the Z-axis direction.

The fourth chip70is provided between the first terminals81and the first chip10. The direction from the fourth chip70toward the first chip10is aligned with the X-axis direction.

The eighth conductive member52is, for example, a metal via having a columnar configuration extending in the Z-axis direction. The ninth conductive member53is, for example, a solder ball.

The semiconductor package device60includes, for example, a DRAM (Dynamic Random Access Memory) element or NVM (Non Volatile Memory) typified by flash memory, etc.

The eighth conductive member52, the ninth conductive member53, the second chip20, the third chip30, and the resin portion51are provided between the semiconductor package device60and the interconnect layer40.

The ninth conductive member53is provided between the eighth conductive member52and the semiconductor package device60and is connected to the eighth conductive member52and the semiconductor package device60.

The eighth conductive member52is provided between the interconnect layer40and the ninth conductive member53.

The eighth conductive member52is connected to the ninth conductive member53and to the sixth conductive member43and the seventh conductive member44of the interconnect layer40.

As shown inFIG.1AandFIG.2A, the length along the X-axis direction of the first chip10is shorter than the length along the X-axis direction of the second chip20and the length along the X-axis direction of the third chip30.

The first conductive member11of the first chip10is electrically connected to the first signal terminal21aof the second chip20via the fourth conductive member41. The first conductive member11of the first chip10is electrically connected to the second signal terminal31aof the third chip30via the fifth conductive member42. Accordingly, the first signal terminal21aof the second chip20is electrically connected to the second signal terminal31aof the third chip30via the fourth conductive member41, the first conductive member11of the first chip10, and the fifth conductive member42.

A power supply is supplied to the first power supply terminal21bof the second chip20via the first terminal81and the sixth conductive member43and supplied to the second power supply terminal31bof the third chip30via the second terminal82and the seventh conductive member44.

The fourth conductive member41and the sixth conductive member43are not connected to each other; and the fifth conductive member42and the seventh conductive member44are not connected to each other. Accordingly, the power supply is not supplied to the first chip10; and the first chip10functions simply as an interconnect member connecting the second chip20and the third chip30. The first chip10does not include a passive element or an active element such as a transistor, etc.

According to the electronic device 1 according to the first embodiment, the second chip20and the third chip30are connected to each other via the first chip10. For example, a high-density fine interconnect can be formed in the first chip10at a low cost using a wafer process. It is unnecessary to form a high-density fine interconnect for the inter-chip connection in the interconnect layer40to which the second chip20and the third chip30are mounted; and the interconnect can be only an interconnect having a rough line-and-space formable at the panel level having a large surface area. This not only makes a cost reduction possible but also reduces the source impedance to the second chip20and the third chip30via the sixth conductive member43and the seventh conductive member44and contributes to the electrical power supply performance improvement.

Also, the first chip10can have a structure of only an interconnect that does not include an active element, a passive element, etc.; and the cost can be reduced drastically. Further, the chip size of the first chip10can be downsized by the amount that an element is not included; and a wide region where the first terminals81and the second terminals82are arranged can be ensured. This makes it possible to reduce the distance between the first power supply terminal21bof the second chip20and the first terminal81and the distance between the second power supply terminal31bof the third chip30and the second terminal82; and the source impedances of the second chip20and the third chip30can be reduced. The decrease of the source impedance deters the fluctuation of the power supply voltage and makes stable operations possible.

The third chip30includes, for example, cache memory as a memory element. The semiconductor package device60may include, for example, DRAM as main memory having a larger memory capacity than the cache memory, or NVM (Non Volatile Memory) typified by flash memory or the like as storage memory. The second chip20can have a function of controlling the third chip30and the semiconductor package device60.

According to such an embodiment, compared to a configuration in which the cache memory is internally integrated in the second chip20, for example, cache memory that has a large capacity can be embedded as a system inside one package; the improvement of the system performance is realized; and a cost reduction of the inter-chip connection interconnect and high electrical power supply performance to each chip can be realized.

FIG.3AtoFIG.6Dare schematic cross-sectional views showing an example of the method for manufacturing the electronic device 1 according to the first embodiment.

As shown inFIG.3A, the interconnect layer40is formed on a supporter100. The interconnect layer40includes the insulating layer45, the fourth conductive member41, the fifth conductive member42, the sixth conductive member43, and the seventh conductive member44described above.

For example,FIGS.6A to6Dshow processes of forming the fourth conductive member41. The supporter100is not illustrated inFIGS.6B to6D.

Although a release layer also may be disposed between the interconnect layer40and the supporter100, such a release layer is not illustrated. The release layer is a laminar material for providing the function of separating the interconnect layer40and the supporter100by applying mechanical stress and/or optical energy (laser irradiation, etc.).

After forming a pad92on the supporter100, an insulating layer91that covers the pad92is formed. A hole91athat reaches the pad92is formed in the insulating layer91.

As shown inFIG.6B, a via93is formed inside the hole91a. The end portion of the via93is formed also on the insulating layer91. A conductive layer94that is included in the sixth conductive member43and a conductive layer95that is included in the seventh conductive member44are formed on the insulating layer91simultaneously with the via93.

As shown inFIG.6C, an insulating layer96is further stacked with the insulating layer91. A hole96athat reaches the end portion of the via93is formed in the insulating layer96. As shown inFIG.6D, a via97is formed inside the hole96a. Subsequently, an insulating layer may be formed; a hole may be formed in the insulating layer; and a via may be formed inside the hole.

The fourth conductive member41that has a stacked via structure including the multiple vias93and97connected to each other in the Z-axis direction is formed by multiply repeating the process of forming the insulating layer, the process of forming the hole in the insulating layer, and the process of forming the via inside the hole. The fifth conductive member42that has the same stacked via structure also is formed similarly to the fourth conductive member41. The via93and the via97are not limited to being arranged in linear configurations along the Z-axis direction; and the positions of the via93and the via97may be shifted in the X-axis direction (or the Y-axis direction) as shown inFIG.6E.

After forming the interconnect layer40, the eighth conductive member52is fixed to the interconnect layer40as shown inFIG.3B. Further, as shown inFIG.4A, the second chip20and the third chip30are fixed to the interconnect layer40. The second chip20and the third chip30may be fixed to the interconnect layer40before the eighth conductive member52.

The eighth conductive member52, the second chip20, and the third chip30are covered with the resin portion51as shown inFIG.4B. The resin portion51is stacked with the interconnect layer40.

The supporter100is removed after forming the resin portion51. The supporter100may be removed by utilizing the function provided by the release layer described above; or the supporter100may be removed by a method such as polishing, etching, etc. By these processes, the surface of the interconnect layer40that opposed the supporter100is exposed as shown inFIG.5A.

The first chip10and the fourth chip70are fixed to the exposed surface of the interconnect layer40as shown inFIG.5B. After fixing the first chip10to the interconnect layer40, the substrate12of the first chip10shown inFIG.1Bmay be removed.

Subsequently, the first terminals81and the second terminals82shown inFIG.1Aare fixed to the interconnect layer40; further, the semiconductor package device60is stacked. The order of stacking the semiconductor package device60may be after the first terminals81and the second terminals82are fixed.

Second Embodiment

FIG.7is a schematic cross-sectional view illustrating an electronic device 2 according to a second embodiment.

FIG.8Ais a schematic view showing the connectional relationship between a first chip110, the second chip20, and the third chip30of the electronic device 2.FIG.8Bis a schematic view in a plane illustrating the connectional relationship between the first chip110, the second chip20, and the third chip30. As shown inFIG.7, the electronic device 2 according to the second embodiment includes the interconnect layer40, the first chip110, the second chip20, the third chip30, the resin portion51, the multiple first terminals81, and the multiple second terminals82.

The first chip110includes a first conductive member111, a first region110a, and a second region110b. The direction from the first region110aof the first chip110toward the third region20aof the second chip20is aligned with the first direction. The direction from the second region110bof the first chip110toward the fifth region30aof the third chip30is aligned with the first direction.

The first region110aof the first chip110faces the third region20aof the second chip20and is a connection region connected to the third region20aof the second chip20. The third region20aof the second chip20faces the first region110aof the first chip110and is the region of the connection to the first region110aof the first chip110. The second region110bof the first chip110faces the fifth region30aof the third chip30and is a connection region connected to the fifth region30aof the third chip30. The fifth region30aof the third chip30faces the second region110bof the first chip110and is a connection region connected to the second region110bof the first chip110.

The direction from the first region110aof the first chip110toward the fourth region20bof the second chip20crosses the first direction and the second direction. The direction from the second region110bof the first chip110toward the sixth region30bof the third chip30crosses the first direction and the second direction.

The interconnect layer40is provided between the first region110aof the first chip110and the third region20aof the second chip20, between the second region110bof the first chip110and the fifth region30aof the third chip30, between the fourth region20bof the second chip20and the first terminals81, and between the sixth region30bof the third chip30and the second terminals82.

The fourth conductive member41of the interconnect layer40is provided between the first region110aof the first chip110and the third region20aof the second chip20and connects the first conductive member111of the first chip110and the signal terminal21aof the second chip20. Many inter-chip interconnect connections are possible by arranging multiple fourth conductive members41in an array configuration in the X-Y plane.

The fifth conductive member42of the interconnect layer40is provided between the second region110bof the first chip110and the fifth region30aof the third chip30and connects the first conductive member111of the first chip110and the fourth signal terminal31aof the third chip30. Many inter-chip interconnect connections are possible by arranging multiple fifth conductive members42in an array configuration in the X-Y plane.

The first chip110is provided between the first terminals81and the second terminals82. The direction from the first terminals81toward the first chip110is aligned with the X-axis direction. The direction from the second terminals82toward the first chip110is aligned with the X-axis direction.

The length along the X-axis direction of the first chip110is shorter than the length along the X-axis direction of the second chip20and the length along the X-axis direction of the third chip30.

Similarly to the first chip10of the first embodiment recited above, the first chip110includes the first conductive member111connecting between the second chip20and the third chip30. As shown inFIG.8A, the first chip110may further include a first memory element113. The first memory element113is, for example, cache memory.

The third chip30includes a second memory element115. The second memory element115is, for example, main memory and may be DRAM. In the case where the first chip110includes a first memory element113, the memory capacity of the second memory element115is larger than the memory capacity of the first memory element113.

An example is shown inFIG.7in which multiple third chips30are stacked in the Z-axis direction. The first memory element113has a faster operation speed than the second memory element115. Various methods may be used as the connection method between the multiple third chips30; and the connection method may be, for example, a TSV (Through Silicon Via) or a metal wire connection. Because the third chip30that includes the second memory element115is provided on the side opposite to the mounting surface of the electronic device 2 for the board, the stacking of the multiple third chips30is easy; and it is easy to increase the capacity of the second memory element115.

The second chip20includes, for example, a logic element and controls the first memory element113of the first chip110and the second memory element115of the third chip30. Or, the logic element of the second chip20may control only the second memory element115of the third chip30. In the specification, “control” includes the mutual data transfer between the logic element and the memory element, the control of the mutual data transfer, the data movement inside the memory element, and the control of the data movement.

As shown inFIG.8A, the first conductive member111of the first chip110includes multiple interconnects112connecting the second chip20and the third chip30. The interconnects112are, for example, metal interconnects. Or, the interconnects112may be optical interconnects (or optical waveguides). The interconnects112function as buses for the data transfer from the second chip20to the third chip30.

As shown inFIG.8AandFIG.8B, the second chip20includes multiple second signal terminals21aaand multiple third signal terminals21ab. The second signal terminals21aaand the multiple third signal terminals21abare provided in the third region20aof the second chip20.

The first chip110includes multiple first signal terminals113aelectrically connected to the first memory element113. The first signal terminals113aare provided in the first region110aof the first chip110.

The fourth conductive member41of the interconnect layer40includes multiple metal vias41aand multiple metal vias41b. The metal vias41aconnects the second signal terminals21aaof the second chip20and the first signal terminals113aof the first chip110. The metal vias41bconnects the third signal terminals21abof the second chip20and the interconnects112.

The third chip30includes multiple fourth signal terminals31aelectrically connected to the second memory element115. The fourth signal terminals31aare provided in the fifth region30aof the third chip30. The fourth signal terminals31aare connected to the interconnects112of the first chip110.

The interconnects112of the first chip110connect the third signal terminals21abof the second chip20and the fourth signal terminals31aof the third chip30. The interconnects112are not connected to the sixth conductive member43and the seventh conductive member44of the interconnect layer40which are interconnects for connecting the first chip110, the second chip20, and the third chip30to the outside. For example, the interconnects of the interconnect layer40also are metal interconnects. Or, the interconnects of the interconnect layer40may be optical interconnects (or optical waveguides).

The connections between the second chip20and the first memory element113are via connections provided by the metal vias41awithout going through the interconnects112.

A power supply is supplied to the first chip110including the first memory element113. The first conductive member111of the first chip110shown inFIG.7is electrically connected to the first terminals81via the sixth conductive member43. Or, the first conductive member111of the first chip110is electrically connected to the second terminals82via the seventh conductive member44. The power supply also may be performed to the first chip110via the second chip20or the third chip30.

The interconnects112that are provided in the first chip110are so-called on-chip interconnects formed by a semiconductor wafer process. Conversely, the sixth conductive member43and the seventh conductive member44which are interconnects of the interconnect layer40can be rough interconnects formed at the panel level which is larger than a semiconductor wafer. In other words, the minimum spacing of the interconnects112of the first chip110is smaller than the minimum spacing of the interconnects of the interconnect layer40.

In the electronic device 2 according to the second embodiment as well, the second chip20and the third chip30are connected to each other via the first chip110. For example, a high-density fine interconnect can be formed in the first chip110at a low cost using a wafer process. It is unnecessary to form a high-density fine interconnect for the inter-chip connection in the interconnect layer40to which the second chip20and the third chip30are mounted; and the interconnect can be only an interconnect having a rough line-and-space formable at the panel level. This makes a cost reduction possible.

The first chip110performs mainly the function of the inter-chip interconnect; and the chip size of the first chip110can be small. A wide region where the first terminals81and the second terminals82are disposed can be ensured by this amount. This makes it possible to reduce the distance between the first power supply terminal21bof the second chip20and the first terminal81and the distance between the second power supply terminal31bof the third chip30and the second terminal82; and the source impedances of the second chip20and the third chip30can be reduced. The decrease of the source impedance deters the fluctuation of the power supply voltage and makes stable operations possible.

Also, according to the second embodiment, the first chip110not only may perform the inter-chip connection but also may have a memory function. According to such a second embodiment, the improvement of the system performance and the higher capacity by the increased layers of the memory layer structure are possible.

Third Embodiment

FIG.9is a schematic view showing the connectional relationship between a first chip110′, the second chip20, and the third chip30of an electronic device according to a third embodiment.

The electronic device according to the third embodiment has the structure of the electronic device 2 according to the second embodiment shown inFIG.7in which the first chip110is replaced with the first chip110′. In other words, the first chip110′ also includes the interconnects112, the first region110a, and the second region110bsimilar to those of the first chip110.

As shown inFIG.9, the first chip110′ further includes the first memory element113and a controller114. The first memory element113is, for example, cache memory. The first chip110′ includes multiple first signal terminals113aelectrically connected to the first memory element113.

The third chip30includes the second memory element115, the multiple fourth signal terminals31a, and the multiple sixth signal terminals31b. The multiple fourth signal terminals31aand the multiple sixth signal terminals31bare connected to the second memory element115.

The second chip20includes the multiple second signal terminals21aa, the multiple third signal terminals21ab, and multiple fifth signal terminals21ac.

The controller114of the first chip110′ is connected to the sixth signal terminals31bof the third chip30via multiple metal vias42. The controller114controls the second memory element115of the third chip30. In other words, the first chip110′ has the function of controlling the second memory element115having the large capacity.

The controller114of the first chip110′ is connected to the first memory element113via multiple interconnects116inside the first chip110′ and controls the first memory element113.

Also, the controller114of the first chip110′ is connected to the fifth signal terminals21acof the second chip20via interconnects117provided in the interconnect layer40.

A power supply is supplied to the first chip110′ via the first terminals81and the sixth conductive member43. Or, the power supply is supplied to the first chip110′ via the second terminals82and the seventh conductive member44.

According to the configuration shown inFIG.9, the controller114of the first chip110′ can control both the second memory element115of the third chip30and the first memory element113of the first chip110′. This makes it possible to optimize the data placement of the memory layer structure without consuming the information processing time and the operating energy accompanying the control of both the first memory element113and the second memory element115of the logic element of the second chip20. For example, in the case where the first memory element113is cache memory, the appropriate movement of the data necessary for the logic element of the second chip20from the second memory element115of the third chip30to the first memory element113is realizable without relying on the control of the second chip20.

Fourth Embodiment

FIG.10is a schematic cross-sectional view illustrating an electronic device 3 according to a fourth embodiment.

The electronic device 3 according to the fourth embodiment includes an interconnect layer240, a first chip210, a second chip220, a third chip230, the resin portion51, the multiple first terminals81, and the multiple second terminals82.

The first chip210includes a first optical element211, a second optical element212, and an optical waveguide213. The first optical element211includes a first electrode terminal211a; and the second optical element212includes a second electrode terminal212a.

The first optical element211is, for example, a light-emitting element or a light receiving element. The second optical element212is, for example, a light-emitting element or a light receiving element. The optical waveguide213is provided between the first optical element211and the second optical element212. The first optical element211and the second optical element212are optically coupled to the optical waveguide213.

The second chip220includes a first region220aand a second region220b. The third chip230includes a third region230aand a fourth region230b.

The direction from the first optical element211of the first chip210toward the first region220aof the second chip20is aligned with the first direction. The direction from the second optical element212of the first chip210toward the third region230aof the third chip30is aligned with the first direction. The second direction from the second chip220toward the third chip230crosses the first direction. In the example, the second direction is aligned with the X-axis direction. The direction from the first optical element211toward the second optical element212is aligned with the second direction.

The direction from the first optical element211of the first chip210toward the second region220bof the second chip220crosses the first direction and the second direction. The direction from the second optical element212of the first chip210toward the fourth region230bof the third chip230crosses the first direction and the second direction.

The interconnect layer240is provided between the first optical element211of the first chip210and the first region220aof the second chip220, between the second optical element212of the first chip210and the third region230aof the third chip230, between the second region220bof the second chip220and the first terminals81, and between the fourth region230bof the third chip230and the second terminals82.

An insulating portion255is provided between the first chip210and the interconnect layer240. For example, the insulating portion255is made of a resin material or an inorganic material. The insulating portion255covers the first electrode terminal211aof the first optical element211and the second electrode terminal212aof the second optical element212. For example, the insulating portion255can be injected after connecting the first electrode terminal211aand the second electrode terminal212ato the interconnect layer240. Or, a formation method may be used in which the insulating portion255is pre-formed in a region including the peripheries of the first electrode terminal211aand the second electrode terminal212a; and the insulating portion255is connected to the interconnect layer240simultaneously with the first electrode terminal211aand the second electrode terminal212a.

The second chip220includes a first conductive member221. The first conductive member221is, for example, a metal member. The first conductive member221includes a first signal terminal221a, a first power supply terminal221b, and a conductive layer (not illustrated) connected to the first signal terminal221aand the first power supply terminal221b. The second chip220includes, for example, a logic element.

The third chip230includes a second conductive member231. The second conductive member231is, for example, a metal member. The second conductive member231includes a second signal terminal231a, a second power supply terminal231b, and a conductive layer (not illustrated) connected to the second signal terminal231aand the second power supply terminal231b. The third chip230includes, for example, a memory element or a logic element.

The interconnect layer240includes the insulating layer45, a third conductive member241, a fourth conductive member242, a fifth conductive member243, and a sixth conductive member244.

The insulating layer45is, for example, a resin layer. The insulating layer45is provided between the third conductive member241, the fourth conductive member242, the fifth conductive member243, and the sixth conductive member244.

The third conductive member241is provided between the first optical element211of the first chip210and the first region220aof the second chip220and electrically connects the first electrode terminal211aof the first optical element211and the first signal terminal221aof the second chip220. The third conductive member241is, for example, a metal via extending along the Z-axis direction. Many inter-chip interconnect connections are possible by arranging multiple third conductive members241in an array configuration in the X-Y plane.

The fourth conductive member242is provided between the second optical element212of the first chip210and the third region230aof the third chip230and electrically connects the second electrode terminal212aof the second optical element212and the second signal terminal231aof the third chip230. The fourth conductive member242extends along the Z-axis direction and is, for example, a metal via. Many inter-chip interconnect connections are possible by arranging multiple fourth conductive members242in an array configuration in the X-Y plane.

The fifth conductive member243is provided between the second region220bof the second chip220and the first terminals81and connects the first power supply terminal221bof the second chip220and the first terminals81.

The sixth conductive member244is provided between the fourth region230bof the third chip230and the second terminals82and connects the second power supply terminal231bof the third chip230and the second terminals82.

The first chip210is provided between the first terminals81and the second terminals82. The direction from the first terminals81toward the first chip210is aligned with the X-axis direction. The direction from the second terminals82toward the first chip210is aligned with the X-axis direction.

The resin portion51covers the second chip20and the third chip30. The resin portion51includes the first resin region51a, the second resin region51b, and the third resin region51c. The second chip220is provided between the first resin region51aand the third resin region51c. The third chip230is provided between the third resin region51cand the second resin region51b. The third resin region51cis provided between the second chip220and the third chip230.

A power supply is supplied to the first power supply terminal221bof the second chip220via the first terminals81and the fifth conductive member243and is supplied to the second power supply terminal231bof the third chip230via the second terminals82and the sixth conductive member244.

According to the electronic device 3 according to the fourth embodiment, the second chip220and the third chip230are connected to each other via the optical waveguide213that is formed in the first chip210. The first optical element211converts an electrical signal from the second chip220into an optical signal and outputs the optical signal to the optical waveguide213. Or, the first optical element211converts an optical signal from the optical waveguide213into an electrical signal and outputs the electrical signal to the second chip220. The second optical element212converts an electrical signal from the third chip230into an optical signal and outputs the optical signal to the optical waveguide213. Or, the second optical element212converts an optical signal from the optical waveguide213into an electrical signal and outputs the electrical signal to the third chip230.

According to such a fourth embodiment, high-speed signal transmission in a wide bandwidth is possible by using optical interconnects as a portion of the interconnects between the second chip220and the third chip230. It is unnecessary to form a high-density fine conductor interconnect and/or an optical waveguide for the inter-chip connection in the interconnect layer240in which the second chip220and the third chip230are mounted; and the interconnect can be only a rough interconnect formable at the panel level having a large surface area. This makes thermal isolation between the second chip220and the third chip230possible by using an optical waveguide in which a cost reduction, high-speed inter-chip communication, and signal transmission with low loss even over long distances are possible.

Fifth Embodiment

FIG.11Ais a schematic cross-sectional view illustrating an electronic device 4 according to a fifth embodiment.

FIG.12is a schematic plan view showing an arrangement example of a first chip310and the second chip20of the electronic device 4.

As shown inFIG.11A, the electronic device 4 according to the fifth embodiment includes a first interconnect layer340, the first chip310, the second chip20, the resin portion51, the multiple first terminals81, and the multiple second terminals82.

The first chip310includes a first region310aand a second region310b. The second chip20includes the third region20aand the fourth region20b.

The first chip310includes, for example, a memory element. The memory element is, for example, cache memory. The second chip20includes, for example, a logic element.

The direction from the first region310aof the first chip310toward the third region20aof the second chip20is aligned with the first direction. The first direction is aligned with the X-axis direction. The second direction crosses the first direction. In the example, the second direction is orthogonal to the first direction and is aligned with the Y-axis direction.

The direction from the first region310aof the first chip310toward the fourth region20bof the second chip20crosses the first direction and the second direction. The direction from the second region310bof the first chip310toward the third region20aof the second chip20crosses the first direction and the second direction.

The resin portion51covers at least a portion of the side surface of the second chip20. The resin portion51includes the first resin region51aand the second resin region51b. The second chip20is provided between the first resin region51aand the second resin region51b. Although the embodiment is shown in the example shown inFIG.11Ain which the surface of the second chip20opposite to the interconnect layer340also is covered with the resin portion51, the exposure from the resin portion51of the surface opposite to the interconnect layer340is arbitrary. Also, although the configuration in the example shown inFIG.11Aincludes the resin portion51disposed also at the peripheral portion of the second conductive member21, the resin portion51may not be at the peripheral portion of the second conductive member21; for example, a different insulating material may be at the peripheral portion of the second conductive member21.

The first interconnect layer340is provided between the first region310aof the first chip310and the third region20aof the second chip20, between the second region310bof the first chip310and the second resin region51b, between the fourth region20bof the second chip20and the first terminals81, between the first resin region51aand the first terminals81, and between the second resin region51band the second terminals82.

The first chip310includes a first conductive member311. The first conductive member311is, for example, a metal member and includes an electrode terminal and a conductive layer.

The insulating portion55is provided between the first chip310and the first interconnect layer340. For example, the insulating portion55is made of a resin material or an inorganic material. For example, the insulating portion55can be injected after connecting the first conductive member311to the first interconnect layer340. Or, a formation method may be used in which the insulating portion55is pre-formed in a region including the periphery of the first conductive member311; and the insulating portion55is connected to the first interconnect layer340simultaneously with the first conductive member311.

The second chip20includes the second conductive member21. The second conductive member21is, for example, a metal member. The second conductive member21includes the first signal terminal21a, the first power supply terminal21b, and a conductive layer (not illustrated) connected to the first signal terminal21aand the first power supply terminal21b.

The first interconnect layer340includes the insulating layer45, a third conductive member341, a fourth conductive member343, and a sixth conductive member344.

The insulating layer45is, for example, a resin layer. The insulating layer45is provided between the third conductive member341, the fourth conductive member343, and the sixth conductive member344. The insulating layer45may be an inorganic insulating material.

The third conductive member341is provided between the first region310aof the first chip310and the third region20aof the second chip20and connects the first conductive member311of the first chip310and the first signal terminal21aof the second chip20. The third conductive member341extends along the Z-axis direction and is, for example, a metal via. Many inter-chip interconnect connections are possible by arranging the multiple third conductive members341in an array configuration in the X-Y plane.

The fourth conductive member343is provided between the fourth region20bof the second chip20and the first terminals81and connects the first power supply terminal21bof the second chip20and the first terminals81.

The sixth conductive member344connects the first conductive member311of the first chip310and the second terminals82.

The first chip310is provided between the first terminals81and the second terminals82. The direction from the first terminals81toward the first chip310is aligned with the X-axis direction. The direction from the second terminals82toward the first chip310is aligned with the X-axis direction.

The first interconnect layer340is provided also between the first resin region51aand the first terminals81and between the second resin region51band the second terminals82.

Similarly to the electronic device 1 of the first embodiment shown inFIG.1Adescribed above, the electronic device 4 according to the fifth embodiment further includes the eighth conductive member52, the ninth conductive member53, and the semiconductor package device60.

The electronic device 4 further includes a third chip170and a fourth chip171. The third chip170and the fourth chip171include, for example, an IPD (Integrated Passive Device) or a passive element. The passive element includes, for example, a discrete component such as a capacitor, an inductor, a resistance element, etc.

For example, the third chip170is connected to the third conductive member343; and, for example, the fourth chip171is connected to the sixth conductive member344.

The first interconnect layer340is provided between the fourth region20bof the second chip20and the third chip170. The third chip170is provided between the first terminals81and the first chip310.

The first interconnect layer340is provided between the fourth chip171and the second region310bof the first chip310. The fourth chip171is covered with the second resin region51b.

As shown inFIG.11AandFIG.12, the length along the X-axis direction of the first chip310may be shorter than the length along the X-axis direction of the second chip20.

The first conductive member311of the first chip310is electrically connected to the first signal terminal21aof the second chip20via the third conductive member341.

The power supply is supplied to the first power supply terminal21bof the second chip20via the first terminals81and the fourth conductive member343. Also, the power supply is supplied to the first chip310via the second terminals82and the sixth conductive member344.

According to the electronic device 4 according to the fifth embodiment, the first chip310and the second chip20can be connected to each other not by an interconnect extending in a direction along the X-Y plane but by the third conductive member341having a via configuration extending in the Z-axis direction. It is unnecessary to form a high-density fine interconnect for the inter-chip connection in the first interconnect layer340; and the interconnect may be only an interconnect having a rough line-and-space formable at the panel level having a large surface area. This makes a cost reduction possible.

For example, the first region310aof the first chip310including the memory element is substantially the memory interface region; and the first region310aopposes the second chip20with the first interconnect layer40interposed in the Z-axis direction. The first chip310includes the second region310bthat does not oppose the second chip20.

Such a chip layout makes it possible to widen the region where the first terminals81are disposed and to reduce the distance between the first terminals81and the first power supply terminal21bformed in the fourth region20bof the second chip20. This reduces the source impedance of the second chip20. The decrease of the source impedance deters the fluctuation of the power supply voltage and makes stable operations possible.

The first chip310includes, for example, cache memory as a memory element. The semiconductor package device60includes, for example, DRAM as main memory having a larger memory capacity than the cache memory. The second chip20controls the first chip310and the semiconductor package device60.

In such a configuration, compared to a configuration in which the cache memory is internally integrated in the second chip20, cache memory that has a large capacity can be embedded as a system inside one package; the improvement of the system performance can be realized; and a cost reduction of the inter-chip connection interconnect and stable electrical power supply to the chips can be realized.

FIG.11Bis a schematic cross-sectional view of an electronic device 4′ of another example of the fifth embodiment.

Compared to the electronic device 4 ofFIG.11A, the electronic device 4′ further includes a second interconnect layer540. The second interconnect layer540is provided between the first interconnect layer340and multiple terminals83. The first interconnect layer340is provided between the second interconnect layer540and the resin portion51.

The terminals83are external terminals that connect the electronic device 4′ to an external circuit. The terminals83are, for example, solder balls. The terminals83may be metal pads or metal bumps.

The second interconnect layer540includes an insulating layer545and a fifth conductive member546.

The insulating layer545is, for example, a resin layer. The insulating layer545covers the first chip310and the third chip170.

The fifth conductive member546is, for example, a metal member and is connected to the fourth conductive member343and the sixth conductive member344of the first interconnect layer340and to the terminals83.

The insulating layer545includes an insulating portion545aprovided between the first chip310and the terminals83. The first chip310is provided between the insulating portion545aand the first interconnect layer340.

The power supply is supplied to the second chip20via the terminals83, the fifth conductive member546of the second interconnect layer540, and the fourth conductive member343of the first interconnect layer340.

The power supply is supplied to the first chip310via the terminals83, the fifth conductive member546of the second interconnect layer540, and the sixth conductive member344of the first interconnect layer340.

The multiple terminals83can be arranged over a wide region of the second interconnect layer540without constraints due to the arrangement position of the first chip310. This makes it possible to accommodate the increase of the number of external input/output terminals accompanying the expanded function of the electronic device 4′.

Sixth Embodiment

FIG.13is a schematic cross-sectional view illustrating an electronic device 5 according to a sixth embodiment.

FIG.14is a schematic view showing the connectional relationship between a first chip410and a second chip520of the electronic device 5.

As shown inFIG.13, the electronic device 5 according to the sixth embodiment includes an interconnect layer440, the first chip410, the second chip520, the resin portion51, and multiple third terminals181.

The first chip410includes a conductive member411; and the second chip520includes a conductive member521. The conductive member411and the conductive member521are, for example, metal members.

The resin portion51covers at least a portion of the side surface of the second chip520. The side surface crosses the X-Y plane. The resin portion51includes the first resin region51aand the second resin region51b. The second chip520is provided between the first resin region51aand the second resin region51b. Although an embodiment is shown in the example shown inFIG.13in which the surface of the second chip520opposite to the interconnect layer440also is covered with the resin portion51, the exposure from the resin portion51of the surface opposite to the interconnect layer440is arbitrary. Also, although the configuration in the example shown inFIG.13includes the resin portion51disposed also at the peripheral portion of the second conductive member521, the resin portion51may not be at the peripheral portion of the second conductive member521; and, for example, a different insulating material may be at the peripheral portion of the second conductive member521.

The interconnect layer440is provided between the first chip410and the second chip520, between the third terminals181and the second chip520, between the first resin region51aand the third terminals181, and between the second resin region51band the third terminals181.

The insulating portion55is provided between the first chip410and the interconnect layer440. For example, the insulating portion55is made of a resin material or an inorganic material. For example, the insulating portion55can be injected after connecting the first conductive member411to the interconnect layer440. Or, a formation method may be used in which the insulating portion55is pre-formed in a region including the periphery of the first conductive member411; and the insulating portion55is connected to the interconnect layer440simultaneously with the first conductive member411.

The interconnect layer440includes the insulating layer45, a first conductive member441, a second conductive member442, and a third conductive member443.

The insulating layer45is, for example, a resin layer. The insulating layer45is provided between the first conductive member441, the second conductive member442, and the third conductive member443.

The conductive member411of the first chip410is electrically connected to the conductive member521of the second chip520via the first conductive member441and the second conductive member442.

The third terminals181are external terminals connecting the electronic device 5 to an external circuit. The third terminals181are, for example, solder balls. The third terminals181may be metal pads or metal bumps.

The first chip410is provided between the multiple third terminals181.

The length along the X-axis direction of the first chip410is shorter than the length along the X-axis direction of the second chip520.

The interconnect layer440is provided also between the first resin region51aand the third terminals181and between the second resin region51band the third terminals181.

Similarly to the electronic device 1 of the first embodiment shown inFIG.1Adescribed above, the electronic device 5 according to the sixth embodiment further includes the eighth conductive member52, the ninth conductive member53, and the semiconductor package device60.

As shown inFIG.14, the first chip410includes a memory element421and a first capacitor422.

FIG.15is a schematic plan view showing the arrangement of a first element region621where the memory element421is disposed and a second element region622where the first capacitor422is disposed in the first chip410.

The memory element421is, for example, DRAM. The DRAM includes a transistor551and a second capacitor552.

The first capacitor422has the same structure as the second capacitor552of the DRAM (e.g., a stacked capacitor, a trench capacitor, etc.).

In the example shown inFIG.15, the second element region622is disposed between two first element regions621. An insulating separation portion650is provided between the first element region621and the second element region622. The insulating separation portion650is, for example, STI (Shallow Trench Isolation).

The insulating separation portion650interrupts the connection between the memory element421and the first capacitor422. The memory element421and the first capacitor422are connected neither physically nor electrically.

The second chip520includes, for example, a logic element controlling the memory element421of the first chip410. As shown inFIG.14, the conductive member521of the second chip520includes a first terminal521a, a second terminal521b, and a fourth terminal521c.

The first terminal521ais a signal terminal; the second terminal521bis a power supply terminal; and the fourth terminal521cis a ground terminal.

The conductive member411of the first chip410includes an electrode of the memory element421and an electrode of the first capacitor422.

The memory element421of the first chip410is electrically connected to the first terminal521aof the second chip520via the first conductive member441of the interconnect layer440.

The first capacitor422of the first chip410is electrically connected to the second terminal521band the fourth terminal521cof the second chip520via the second conductive member442of the interconnect layer440.

The first capacitor422of the first chip410and the second terminal521band the fourth terminal521cof the second chip520are electrically connected to the third terminals181via the third conductive member443of the interconnect layer440.

According to the electronic device 5 according to the sixth embodiment, the first chip410and the second chip520can be connected to each other not by an interconnect extending in a direction along the X-Y plane but by the first conductive member441and the second conductive member442having via configurations extending in the Z-axis direction. It is unnecessary to form a high-density fine interconnect for the inter-chip connection in the interconnect layer440; and the interconnect can be only an interconnect having a rough line-and-space formable at the panel level having a large surface area. This makes a cost reduction possible.

In the first chip410, the first capacitor422that is integrated with the memory element421is, for example, a decoupling capacitor connected to the power supply line of the second chip520and suppresses the fluctuation of the power supply voltage of the second chip520. This makes stable operations of the second chip520possible.

FIG.16Ais a schematic cross-sectional view showing the connectional relationship between the first chip10, the second chip20, and the third chip30of an electronic device according to a seventh embodiment.

The electronic device according to the seventh embodiment has the structure of the electronic device 1 shown inFIG.1Ain which the signal transfer portion between the first chip10and the second chip20and the signal transfer portion between the first chip10and the third chip30are not the conductive members41and42, which are replaced with an inductive coupling pair or a capacitive coupling pair.

The first chip10includes a first coupling element11dprovided in the first region10a, and a second coupling element11eprovided in the second region10b. The second chip20includes a third coupling element21dprovided in the third region20a. The third chip30includes a fourth coupling element31dprovided in the fifth region30a.

The insulating layer45of the interconnect layer40is provided between the first coupling element11dand the third coupling element21dand between the second coupling element11eand the fourth coupling element31d. The conductive members of the interconnect layer40between the first coupling element11dand the third coupling element21dand between the second coupling element11eand the fourth coupling element31dmay not be provided.

The direction from the first coupling element11dtoward the third coupling element21dis aligned with the Z-axis direction; and the direction from the second coupling element11etoward the fourth coupling element31dis aligned with the Z-axis direction. The direction from the first coupling element11dtoward the second coupling element11eis aligned with the X-axis direction; and the direction from the third coupling element21dtoward the fourth coupling element31dis aligned with the X-axis direction.

For example, the first chip10can be fixed to the interconnect layer40by a bonding agent. Or, the first chip10can be directly coupled to the interconnect layer40by utilizing a dehydrating condensation reaction.

The first coupling element11d, the second coupling element11e, the third coupling element21d, and the fourth coupling element31dare inductive coupling elements or capacitive coupling elements.

The first coupling element11dof the first chip10and the third coupling element21dof the second chip20have inductive coupling or capacitive coupling. The second coupling element11eof the first chip10and the fourth coupling element31dof the third chip30have inductive coupling or capacitive coupling.

Similarly to the first chip10of the first embodiment shown inFIG.1D, the first chip10further includes the conductive layer11b. The conductive layer11belectrically connects between the first coupling element11dand the second coupling element11e.

Signals are transmitted between the second chip20and the third chip30via the inductive coupling or the capacitive coupling between the first coupling element11dand the third coupling element21d, via the conductive layer11bof the first chip10, and via the inductive coupling or the capacitive coupling between the second coupling element11eand the fourth coupling element31d.

The seventh embodiment may include the following configuration:an electronic device, including:a first chip including a first coupling element, a second coupling element, and a first conductive member;a second chip including a third coupling element;a third chip including a fourth coupling element; andan insulating layer provided between the first coupling element and the third coupling element and between the second coupling element and the fourth coupling element,the first coupling element and the third coupling element having inductive coupling or capacitive coupling, the second coupling element and the fourth coupling element having inductive coupling or capacitive coupling,the first conductive member electrically connecting the first coupling element and the second coupling element.

FIG.16Bis a schematic cross-sectional view showing the connectional relationship between the first chip310and the second chip20of an electronic device according to an eighth embodiment.

The electronic device according to the eighth embodiment has the structure of the electronic device 4 shown inFIG.11Ain which the signal transfer portion between the first chip310and the second chip20is not the conductive member341, which is replaced with an inductive coupling pair or a capacitive coupling pair.

The first chip310includes a first coupling element311aprovided in the first region310a. The second chip20includes a second coupling element21eprovided in the third region20a.

The insulating layer45of the interconnect layer340is provided between the first coupling element311aand the second coupling element21e. The conductive members of the interconnect layer340are not provided between the first coupling element311aand the second coupling element21e.

The direction from the first coupling element311atoward the second coupling element21eis aligned with the Z-axis direction.

For example, the first chip310can be fixed to the interconnect layer340by a bonding agent. Or, the first chip310can be directly coupled to the interconnect layer340by utilizing a dehydrating condensation reaction.

The first coupling element311aand the second coupling element21eare inductive coupling elements or capacitive coupling elements.

The first coupling element311aof the first chip310and the second coupling element21eof the second chip20have inductive coupling or capacitive coupling.

The signals are transmitted between the first chip310and the second chip20via the inductive coupling or the capacitive coupling between the first coupling element311aand the second coupling element21e.

The eighth embodiment may include the following configuration:an electronic device, including:a first chip including a first coupling element;a second chip including a second coupling element; andan insulating layer provided between the first coupling element and the second coupling element,the first coupling element and the second coupling element having inductive coupling or capacitive coupling.

FIG.17is a schematic cross-sectional view of an electronic device 1′ of a modification of the electronic device 1 shown inFIG.1A.

The electronic device 1′ has the structure of the electronic device 1 shown inFIG.1Ain which the second interconnect layer540shown inFIG.11Bis provided. The multiple terminals83can be arranged over a wide region of the second interconnect layer540without constraints due to the arrangement position of the first chip10. This makes it possible to accommodate the increase of the number of external input/output terminals accompanying the expanded function of the electronic device 1′.

FIG.18is a schematic cross-sectional view of an electronic device 2′ of a modification of the electronic device 2 shown inFIG.7.

The electronic device 2′ has the structure of the electronic device 2 shown inFIG.7in which the second interconnect layer540shown inFIG.11Bis provided. The multiple terminals83can be arranged over a wide region of the second interconnect layer540without constraints due to the arrangement position of the first chip110. This makes it possible to accommodate the increase of the number of external input/output terminals accompanying the expanded function of the electronic device 1′.

FIG.19is a schematic cross-sectional view of an electronic device 3′ of a modification of the electronic device 3 shown inFIG.10.

The electronic device 3′ has the structure of the electronic device 3 shown inFIG.10in which the second interconnect layer540shown inFIG.11Bis provided. The multiple terminals83can be arranged over a wide region of the second interconnect layer540without constraints due to the arrangement position of the first chip210. This makes it possible to accommodate the increase of the number of external input/output terminals accompanying the expanded function of the electronic device 1′.

FIG.20is a schematic cross-sectional view of an electronic device 5′ of a modification of the electronic device 5 shown inFIG.13.

The electronic device 5′ has the structure of the electronic device 5 shown inFIG.13in which the second interconnect layer540shown inFIG.11Bis provided. The multiple terminals83can be arranged over a wide region of the second interconnect layer540without constraints due to the arrangement position of the first chip410. This makes it possible to accommodate the increase of the number of external input/output terminals accompanying the expanded function of the electronic device 1′.

FIG.21is a schematic cross-sectional view of an electronic device according to a ninth embodiment.

The electronic device according to the ninth embodiment has the structure of any of the electronic devices 1 to 5 described above in which a third interconnect layer700is provided.

The third interconnect layer700includes a conductive member701including a metal interconnect, a metal via, and a metal pad. Any of the electronic devices 1 to 5 is mounted on the third interconnect layer700via the multiple terminals81. The terminals81are connected to the conductive member701of the third interconnect layer700.

Multiple terminals84are provided on the opposite face of the mounting surface of the third interconnect layer700for the electronic devices 1 to 5. The terminals84are, for example, solder balls. The terminals84are connected to the conductive member701of the third interconnect layer700. The multiple terminals84can be arranged over a wide region of the third interconnect layer700without constraints due to the arrangement position of the first chip of the electronic devices 1 to 5 described above. This makes it possible to accommodate the increase of the number of external input/output terminals accompanying the expanded function of the electronic device.

An example will now be described with reference toFIG.22toFIG.26in which the electronic device of the second embodiment shown inFIG.7toFIG.9described above is applied to a large-scale system.

FIG.22is a schematic view showing the arrangement and the connections of the first chips110and110′, the second chips20, the third chips30, and the interconnect layer40. The interconnect layer40is schematically illustrated by one straight line.

FIG.23is a schematic plan view of the electronic device shown inFIG.22.

FIG.24is a schematic view in which the positions of the second chips20and the positions of the third chips30ofFIG.23are interchanged.

According to the example shown inFIG.22toFIG.24, the multiple first chips110and110′, the multiple second chips20, and the multiple third chips30are mounted to the interconnect layer40. The third chips30can function as shared memory between mutually-adjacent second chips20.

FIG.25is a schematic plan view showing an application example of the electronic device of the second embodiment to a neural network.

The input/output information, the connection information, etc., between the artificial neurons (the nodes) is stored in the second memory elements115of the third chips30; and the logic elements of the second chips20execute calculation processing based on the information. A large-scale parallel neural network can be realized by arranging the second chips20and the third chips30in a matrix configuration and by mutually connecting with the first chips10,110, and110′. The first chips may be used to store temporary calculation information in the case where memory elements are included in the first chips.

The data transfer to distal nodes may be executed by using the interconnects of the interconnect layer40or by sharing the memory of the third chips30. By uniformly mixing and densely connecting the multiple memory elements and the multiple logic elements, a scalable system can be configured while minimizing the data transfer energy.

FIG.26is a descriptive view of a neural network.

The neural network is a model that has problem solving ability in which artificial neurons (nodes) are formed in a network by the connections of synapses; and the connection strengths of the synapses are changed by learning. As shown inFIG.26, a neural network that is connected in multiple layers is called a deep neural network and has been utilized in various fields in recent years.

FIG.27is a schematic view showing an application example of the electronic device of the second embodiment to a neural network.

The input/output information, the connection information, etc., between the artificial neurons (the nodes) is stored in the second memory elements115of the third chips30and shared between the multiple second chips20; and the logic elements of the second chips20execute calculation processing based on the information.

In the processing of a neural network using a conventional GPU (Graphics Processing Unit), etc., it is necessary to repeat the data transfer between the memory elements and the logic elements for the calculation for each layer; and there is a limit to the energy efficiency and the processing performance.

In the embodiment as shown inFIG.27, by spatially dispersing the calculation processing of multiple layers and by executing in multi-parallel, it is possible to approach the information processing performance and the efficiency of an actual brain.

FIG.28is a schematic plan view showing the full grid tile structure of the first chips110and110′, the second chips20, and the third chips30.

The full grid tile structure is formed by the multiple second chips20and the multiple third chips30being densely connected by the multiple first chips110and110′.

The full grid tile structure shown inFIG.28also is applicable to a neural network as shown inFIG.29.

Compared to the configuration shown inFIG.25, the configuration shown inFIG.28can improve the calculation performance and increase the neural network processing efficiency per unit surface area.

The embodiments described above may include the following configuration.

The interconnect layers40,240,340,440, and540are aligned with a plane including the second direction and a third direction. The second direction is aligned with the X-axis direction; and the third direction crosses the second direction. For example, the third direction is orthogonal to the second direction and is aligned with the Y-axis direction.

The multiple first terminals81, the multiple second terminals82, the multiple third terminals181, and the multiple terminals83described above are arranged in the second direction and the third direction in a plane including the second direction and the third direction. In other words, the multiple first terminals81, the multiple second terminals82, the multiple third terminals181, and the multiple terminals83are arranged in an array configuration in a plane including the second direction and the third direction.

The conductive members41and42,241,242,341,441, and442described above are aligned with the first direction crossing the plane recited above. For example, the conductive members41and42,241,242,341,441, and442are aligned with a direction substantially perpendicular to the plane recited above.

The first chip10of the embodiment shown inFIGS.1A and1Bis an electrical interconnect member that has a chip configuration including the first conductive member11electrically connecting the second chip20and the third chip30and does not include a memory element, a transistor, or a passive element.

The first chip310or the second chip20shown inFIG.11A,FIG.11B, andFIG.16Bincludes a memory element.

FIG.30is a schematic cross-sectional view of an example of the third chip30of the above embodiments.

The third chip30has a stacked memory structure including a plurality of memory chips32and a logic chip33. The memory chips32are stacked on the logic chip33. Each of the memory chips32includes the second memory element115shown inFIG.8AtoFIG.9. The memory chips32are connected each other through a plurality of metal pads or metal bumps34. The memory chips32are electrically connected to the logic chip33through the metal pads or metal bumps34. The logic chip33is electrically connected to the signal terminals31a,31bof the third chip30shown inFIG.8Ato FIG.9. The memory chips32are molded by a resin35.

Note 1

An electronic device, comprising:a first chip including a first optical element, a second optical element, and an optical waveguide optically coupled to the first optical element and the second optical element;a second chip including a first conductive member, a first region, and a second region;a third chip including a second conductive member, a third region, and a fourth region;a first terminal;a second terminal; andan interconnect layer provided between the first optical element of the first chip and the first region of the second chip, between the second optical element of the first chip and the third region of the third chip, between the first terminal and the second region of the second chip, and between the second terminal and the fourth region of the third chip,the interconnect layer includinga third conductive member provided between the first optical element of the first chip and the first region of the second chip, the third conductive member connecting the first optical element of the first chip and the first conductive member of the second chip, anda fourth conductive member provided between the second optical element of the first chip and the third region of the third chip, the fourth conductive member connecting the second optical element of the first chip and the second conductive member of the third chip,the first chip being provided between the first terminal and the second terminal.
Note 2

The electronic device according to Note 1, whereinthe second chip further includes a first power supply terminal,the third chip further includes a second power supply terminal, andthe interconnect layer further includes a fifth conductive member and a sixth conductive member, the fifth conductive member connecting the first power supply terminal and the first terminal, the sixth conductive member connecting the second power supply terminal and the second terminal.
Note 3

An electronic device, comprising:a first chip including a memory element and a first capacitor; anda second chip including a first terminal and a second terminal, the first terminal being connected to the memory element, the second terminal being connected to the first capacitor.
Note 4

The electronic device according to Note 3, further comprising an interconnect layer provided between the first chip and the second chip,the interconnect layer includinga first conductive member provided between the memory element of the first chip and the first terminal of the second chip, the first conductive member connecting the memory element of the first chip and the first terminal of the second chip, anda second conductive member provided between the first capacitor of the first chip and the second terminal of the second chip, the second conductive member connecting the first capacitor of the first chip and the second terminal of the second chip.
Note 5
The electronic device according to Note 4, further comprising a third terminal,the interconnect layer further including a third conductive member provided between the third terminal and the second terminal of the second chip, the third conductive member connecting the third terminal and the second terminal of the second chip.
Note 6

The electronic device according to any one of Notes 3 to 5, wherein the first chip further includes an insulating separation portion provided between the memory element and the first capacitor.

Note 7

The electronic device according to any one of Notes 3 to 6, wherein the memory element is DRAM (Dynamic Random Access Memory) including a second capacitor.

Note 8

An electronic device, comprising:

a first chip including a first conductive member, a first region, and a second region;a second chip including a second conductive member, a third region, and a fourth region;a third chip including a third conductive member, a fifth region, and a sixth region;a first terminal;a second terminal; andan interconnect layer provided between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the fifth region of the third chip, between the first terminal and the fourth region of the second chip, and between the second terminal and the sixth region of the third chip,the interconnect layer includinga fourth conductive member provided between the first region of the first chip and the third region of the second chip, the fourth conductive member connecting the first conductive member of the first chip and the second conductive member of the second chip, anda fifth conductive member provided between the second region of the first chip and the fifth region of the third chip, the fifth conductive member connecting the first conductive member of the first chip and the third conductive member of the third chip,the first chip being provided between the first terminal and the second terminal.
Note 9

The electronic device according to Note 8, wherein the first chip is an electrical interconnect member connecting the second chip and the third chip via the first conductive member, the fourth conductive member, and the fifth conductive member.

Note 10

The electronic device according to Note 9, wherein the first chip does not include a substrate.

Note 11

The electronic device according to Note 9, wherein the third chip includes a memory element.

Note 12

The electronic device according to Note 8, wherein the first chip further includes a first memory element connected to the fourth conductive member.

Note 13

The electronic device according to Note 12, wherein the third chip further includes a second memory element connected to the fifth conductive member.

Note 14

The electronic device according to Note 13, wherein a memory capacity of the second memory element is larger than a memory capacity of the first memory element.

Note 15

The electronic device according to Note 13 or 14, wherein the first chip further includes a controller connected to the fifth conductive member.

Note 16

The electronic device according to any one of Notes 8 to 15, whereinthe second chip further includes a first power supply terminal,the third chip further includes a second power supply terminal, andthe interconnect layer further includes a sixth conductive member and a seventh conductive member, the sixth conductive member connecting the first power supply terminal and the first terminal, the seventh conductive member connecting the second power supply terminal and the second terminal.
Note 17

The electronic device according to Note 16, whereinthe interconnect layer further includes an insulating layer provided between the fourth conductive member and the sixth conductive member and between the fifth conductive member and the seventh conductive member,the fourth conductive member and the sixth conductive member are insulatively separated, andthe fifth conductive member and the seventh conductive member are insulatively separated.
Note 18

An electronic device, comprising:a first chip including a first conductive member, a first region, and a second region;a second chip including a second conductive member, a third region, and a fourth region;a resin portion including a first resin region and a second resin region;a terminal; anda first interconnect layer provided between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the first resin region, between the terminal and the fourth region of the second chip, and between the terminal and the second resin region,the first interconnect layer including a third conductive member provided between the first region of the first chip and the third region of the second chip, the third conductive member connecting the first conductive member of the first chip and the second conductive member of the second chip,the second chip being provided between the first resin region and the second resin region of the resin portion.
Note 19

The electronic device according to Note 18, whereinthe second chip further includes a power supply terminal, andthe first interconnect layer further includes a fourth conductive member connecting the power supply terminal and the terminal.
Note 20

The electronic device according to Note 18 or 19, further comprising a second interconnect layer provided between the first interconnect layer and the terminal,the second interconnect layer including a fifth conductive member and an insulating portion, the fifth conductive member being connected to the terminal, the insulating portion being provided between the terminal and the first chip,the first chip being provided between the insulating portion and the first interconnect layer.
Note 21

The electronic device according to any one of Notes 18 to 20, wherein the first chip or the second chip includes a memory element.

Note 22

An electronic device, comprising:a first chip including a first connection region and a second connection region;a second chip including a third connection region facing the first connection region of the first chip; anda third chip including a fourth connection region facing the second connection region of the first chip,the first chip including a first memory element and a plurality of first interconnects, the first chip including a plurality of first signal terminals provided in the first connection region and electrically connected to the first memory element, the plurality of first interconnects being provided in the first connection region and the second connection region,the second chip including a plurality of second signal terminals and a plurality of third signal terminals, the plurality of second signal terminals being provided in the third connection region, the plurality of third signal terminals being provided in the third connection region,the third chip including a second memory element and a plurality of fourth signal terminals electrically connected to the second memory element, the plurality of fourth signal terminals being provided in the fourth connection region,the second signal terminals of the second chip being connected to the first terminals of the first chip,the first interconnects being connected to the third signal terminals of the second chip and the fourth signal terminals of the third chip.
Note 23

The electronic device according to Note 22, further comprising an interconnect layer provided between the first chip and the second chip, and between the first chip and the third chip,the interconnect layer includinga plurality of first metal vias connecting the second signal terminals of the second chip and the first signal terminals of the first chip,a plurality of second metal vias connecting the first interconnects and the third signal terminals of the second chip,a plurality of third metal vias connecting the first interconnects and the fourth signal terminals of the third chip, anda plurality of second interconnects connecting the second chip and the third chip to an outside.
Note 24

The electronic device according to Note 23, wherein a minimum spacing of the multiple first interconnects provided in the first chip is smaller than a minimum spacing of the multiple second interconnects provided in the interconnect layer.

Note 25

The electronic device according to any one of Notes 22 to 24, wherein a memory capacity of the second memory element is larger than a memory capacity of the first memory element.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in electronic devices such as interconnect layers, electrical elements, optical elements, resin portions, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.

Further, any two or more components of the specific examples may be combined within the extent of technical feasibility and are included in the scope of the invention to the extent that the purport of the invention is included.

Moreover, all electronic devices, and methods for manufacturing the same practicable by an appropriate design modification by one skilled in the art based on the electronic devices, and the methods for manufacturing the same described above as embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included.

Various other variations and modifications can be conceived by those skilled in the art within the spirit of the invention, and it is understood that such variations and modifications are also encompassed within the scope of the invention.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.