Patent ID: 12200990

DESCRIPTION OF EMBODIMENTS

First Embodiment

FIG.1is a block diagram of a structure of a display device in accordance with a first embodiment. A display device10inFIG.1is an OLED display device including a display unit11, a display control circuit12, a scan line/control line drive circuit13, and a data line drive circuit14. Throughout the following description, m and n are an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n.

The display unit11includes in first scan lines GA1to GAm, (m+1) second scan lines GB0to Gam, in light-emission control lines E1to Em, n data lines S1to Sn, and (m×n) pixel circuits20. The first scan lines GA1to GAm, the second scan lines GB0to GBm, and the light-emission control lines E1to Em are disposed parallel to each other. The data lines S1to Sn are disposed parallel to each other so as to be perpendicular to, for example, the first scan lines GA1to GAm. The first scan lines GA1to GAm and the data lines S1to Sn form (m×n) intersections. The (m×n) pixel circuits20are disposed respectively for the intersections of the first scan lines GA1to GAm and the data lines S1to Sn. The pixel circuits20are fed with a HIGH power supply electrical potential ELVDD, a LOW power supply electrical potential ELVSS, and an initialization electrical potential Vini through electrically conductive members (not shown).

The display control circuit12outputs a control signal CS1to the scan line/control line drive circuit13and outputs a control signal CS2and a data signal Di to the data line drive circuit14, The scan line/control line drive circuit13is a circuit in which a scan line drive circuit and a control line drive circuit (neither shown) are integrated. The scan line/control line drive circuit13drives the first scan lines GA1to GAm, the second scan lines GB0to GBm, and the light-emission control lines E1to Em in accordance with the control signal CS1. The data line drive circuit14drives the data lines S1to Sn on the basis of the control signal CS2and the data signal Dl. The scan line/control line drive circuit13and the data line drive circuit14function as a drive circuit for driving the first scan lines GA1to GAm, the second scan lines GB0to GBm, and the data lines S1to Sn.

FIG.1shows the single scan line/control line drive circuit13disposed along a side of the display unit11so that the single scan line/control line drive circuit13can drive, for example, the first scan lines GA1to GAm from the left side. Alternatively, there may be provided two scan line/control line drive circuits13along opposite sides of the display unit11respectively so that the two scan line/control line drive circuits13can drive, for example, the first scan lines GA1to GAm from both sides.

FIG.2is a circuit diagram of the pixel circuit20. The pixel circuit20inFIG.2is a pixel circuit in row i, column j. The pixel circuit20includes eight TFTs T1, T2n, T2p, and T3to T7, an OLED L1, and a capacitor C1and is connected to the first scan line GAi, the second scan lines GBi−1 and GBi, the light-emission control line Ei, and the data line Sj. The second scan line GBi−1 is the second scan line that is selected immediately before the second scan line GBi. The TFTs T2pand T3to16are P-channel TFTs. The TFTs T1, T2n, and T7are N-channel TFTs. The P-channel. TFTs in the pixel circuit20, including the TFT T2p, are made of a low-temperature polysilicon. The N-channel TFTs in the pixel circuit20, including the TFT T2n, are made of an oxide semiconductor such as IGZO. The P-channel TFTs and the N-channel TFTs in the pixel circuit20may be made of other materials.

The HIGH power supply electrical potential ELVDD is applied to the source terminal of the TFT T5. One of the conduction terminals of the TFT T3(the right side terminal inFIG.2) is connected to the data line Sj. The drain terminal of the TFT T5and the other conduction terminal of the TFT T3are connected to the source terminal of the TFT T4. The drain terminal of the TFT T4is connected to the source terminal of the TFT T6. The drain terminal of the TFT T6is connected to the anode terminal of the OLED L1and the drain terminal of the TFT T7. The LOW power supply electrical potential ELVSS is applied to the cathode terminal of the OLED L1. The drain terminal of the TFT T1is connected to the gate terminal of the TFT T4. The initialization electrical potential Vini is applied to the source terminals of the TFTs T1and T7.

The TFTs T2nand T2pare connected in series and disposed between the gate terminal and the drain terminal (conduction terminal leading to the OLED L1) of the TFT T4. To describe it in more detail, the TFT T2phas a first conduction terminal (top side terminal inFIG.2) connected to the gate terminal of the TFT T4. The TFT T2phas a second conduction terminal connected to a second conduction terminal (top side terminal inFIG.2) of the TFT T2n. The TFT T2nhas a first conduction terminal connected to the drain terminal of the TFT T4and the source terminal of the TFT T6. The gate terminals of the TFTs T2pand T3are connected to the first scan line GAi. The gate terminal of the TFT T2nis connected to the second scan line GBi. The gate terminals of the TFTs T1and T7are connected to the second scan line GBi−1. The gate terminals of the TFTs T5and T6are connected to the light-emission control line Ei.

The OLED L1functions as a light-emitting element in the pixel circuit20. The TFT T4functions as a drive transistor of a first conductivity type for controlling the magnitude of the electric current flowing through the light-emitting element. The TFT T2pfunctions as a first compensation transistor of the first conductivity type, with the control terminal thereof being connected to the first scan line GAi. The TFT T2nfunctions as a second compensation transistor of a second conductivity type, with the control terminal thereof being connected to the second scan line GBi. The first compensation transistor and the second compensation transistor are connected in series and disposed between the control terminal of the drive transistor and the conduction terminal of the drive transistor that leads to the light-emitting element. The TFT T3functions as a write control transistor, with the control terminal thereof being connected to the first scan line GAi. The TFT T1functions as a first initialization transistor for initializing the electrical potential on the control terminal of the drive transistor. The TFT T7functions as a second initialization transistor for initializing the electrical potential on one of the terminals of the light-emitting element. The TFTs T5and T6function as light emission control transistors, with the control terminals thereof being connected to the light-emission control line Ei.

FIG.3is a timing chart for the pixel circuit20. The scan line/control line drive circuit13is fed with gate clocks GCK1and GCK2that change as shown inFIG.3. The scan line/control line drive circuit13selectively applies a HIGH potential and a LOW potential to the first scan lines GA1to GAm, the second scan lines GB0to GBm, and the light-emission control lines E1to Em on the basis of the gate clocks GCK1and GCK2. The electrical potential on each signal line changes with a delay that is equal to a prescribed length of time after the electrical potential on another signal line of the same type that is selected immediately before that signal line. For instance, the electrical potential on the first scan line GAi changes after the electrical potential on the first scan line GAi−1 with a delay of (t14−t12). The HIGH potential applied to the first scan line GAi is at the same level as the HIGH potential applied to the second scan line GBi. The LOW potential applied to the first scan line GAi is at the same level as the LOW potential applied to the second scan line GBi.

A description is now given of the operation of the pixel circuit20in row i, column j with reference toFIG.3in which the period from time t11to time t13is an initialization period, the period from time t13to time t14is a write period, and the period before time t11and the period after time t15are light-emitting periods. Before time t11, the electrical potential on the first scan line GAi is HIGH, and the electrical potentials on the second scan lines GBi−1 and GBi and the light-emission control line Ei are LOW. Therefore, the TFTs T1, T2p, T2n, T3, and T7are OFF, and the TFTs T5and T6are ON.

At time t11, the electrical potentials on the second scan line GBi−1 and the light-emission control line Ei go HIGH, turning on the TFTs T1and T7and turns off the TFTs T5and T6. That in turn renders the gate potential of the TFT T4and the anode potential of the OLED L1equal to the initialization electrical potential Vini. The initialization electrical potential Vini is dictated by the LOW potential which turns on the TFT T4at time t13. The electrical potential on the second scan line GBi goes HIGH at time t12, turning on the TFT T2n.

The electrical potentials on the first scan line GAi and the second scan line GBi−1 go LOW at time t13, turning off the TFTs T1and T7and turns on the TFTs T2pand T3. A data potential Vdata is applied to the data line Sj in accordance with a video signal Di at time t13onwards. That causes an electric current to flow from the data line Sj to the gate terminal of the TFT T4via the TFTs T3, T4, T2n, and T2p, increasing the gate potential of the TFT T4. When the gate-to-source voltage of the TFT T4becomes equal to a threshold voltage Vth (<0) of the TFT T4, the electric current stops flowing. The gate potential of the TFT T4is therefore equal to (Vdata+Vth) when the electric current stops flowing. The voltage across the capacitor C1is equal to the difference between the HIGH power supply electrical potential ELVDD and the gate potential of the TFT T4(ELVDD−Vdata−Vth). The electrical potential on the first scan line GAi goes HIGH at time t14, turning off the TFT T2p.

The electrical potentials on the second scan line GBi and the light-emission control line Ei go LOW at time t15, turning off the TFT T2nand turns on the TFTs T5and T6. At time t15onwards, an electric current Id flows from the electrically conductive member having the HIGH power supply electrical potential ELVDD to the electrically conductive member having the LOW power supply electrical potential ELVSS via the TFTs T5, T4, and T6and the OLED L1. The electric current Id is given by equation (1) below.
Id=k(Vgs+Vth)2(1)

where k is a constant, and Vgs is the gate-to-source voltage of the TFT T4. Since the voltage Vgs is equal to the voltage across the capacitor C1, the electric current Id is given by equation (2) below.
Id=k{(ELVDD−Vdata−Vth)+Vth}2=k(EVDD−Vdata)2(2)

The electric current Id changes with the data potential Vdata, not with the threshold voltage Vth of the TFT T4. The OLED L1therefore emits light at a luminance that matches the data potential Vdata, regardless of the threshold voltage Vth of the TFT T4. This enables internal compensation where the fluctuations and variations of the characteristics (threshold voltage) of the TFT T4are compensated for inside the pixel circuit20by controlling the electrical potentials on the signal lines connected the pixel circuit20as shown inFIG.3.

The electrical potential at which the TFT in the pixel circuit20is turned on is referred to as the ON potential, and the electrical potential at which the TFT in the pixel circuit20is turned off is referred to as the OFF potential. The LOW potential is the ON potential, and the HIGH potential is the OFF potential, in a P-channel TFT. The HIGH potential is the ON potential, and the LOW potential is the OFF potential, in a N-channel TEL

After both the TFTs T2pand T2nin the pixel circuit20are turned on, the TFT T2pis turned off earlier than the TFT T2n. The period in which the ON potential is applied to the first scan line GAi partially overlaps the period in which the ON potential is applied to the associated second scan line GBi. The period in which the ON potential is applied to the first scan line GAi does not overlap the period in which the ON potential is applied to the adjacent, first scan line GAi−1. The period in which the ON potential is applied to the second scan line GBi partially overlaps the period in which the ON potential is applied to the adjacent, second scan line GBi−1. The period in which the ON potential is applied to the second scan line GBi is longer than the period in which the ON potential is applied to the first scan line GAi.

FIG.4is a diagram of a part ofFIG.2.FIG.4shows a parasitic capacitance Cp between the gate terminal and the first conduction terminal of the TFT T2p.FIG.5is a diagram of a part ofFIG.3. A description is given next of the effects of the display device10including the pixel circuit20with reference toFIGS.4and5. Before time t12, the electrical potential on the first scan line GAi is HIGH, the electrical potential on the second scan line GBi is LOW, and both the TFTs T2nand T2pare OFF. The electrical potential on the second scan line GBi goes HIGH at time t12, turning on the TFT T2n. The electrical potential on the first scan line GAi goes LOW at time t13, turning on the TFT T2p. The gate potential of the TFT T4then changes to (Vdata+Vth). The pixel circuit20needs to maintain the gate potential of the TFT T4when the gate potential of the TFT T4changes to (Vdata+Vth).

The electrical potential on the first scan line GAi goes HIGH at time t14, turning off the TFT T2p. Due to the presence of the parasitic capacitance Cp, the gate potential of the TFT T4increases with an increase in the electrical potential on the first scan line GAL Since the TFT T4has a P-channel, an increase in the gate potential of the TFT T4causes a decrease in the electric current flowing through the TFT T4, which in turn decreases the luminance of the OLED L1In this manner, when the TFT T2pis turned off at time t14, the gate potential of the TFT T4changes in such a manner as to decrease the luminance of the OLED L1. No washed-out black is hence caused by the turning-off of the TFT T2p.

The electrical potential on the second scan line GBi goes LOW at time t15, turning off the TFT T2n. Since the TFT T2phas been OFF, the gate potential of the TFT T4does not change even if the electrical potential on the second scan line GBi decreases. Therefore, the electric current flowing through the TFT T4does not change, and the luminance of the OLED L1does not change. No washed-out black is hence caused by the turning-off of the TFT T2n.

The display device10in accordance with the present embodiment therefore does not cause a change in the data potential, thereby restraining washed-out black that could otherwise be caused by the turning-off of the TFT T2n, when the TFT T2n, which has a different conductivity type from the TFT T4, is used as a compensation transistor. In addition, the use of an IGZO- or other oxide semiconductor-based transistor as the TFT T2nenables low-frequency drive, thereby reducing the power consumption of the display device10.

As described above, the display device10in accordance with the present embodiment includes: the display unit11including the first scan lines GA1to GAm, the second scan lines GB0to GBm, the data lines S1to Sn, and the pixel circuits20; and the drive circuits (scan line/control line drive circuit13and data line drive circuit14) for driving the first scan lines GA1to GAm, the second scan lines GB0to GBm, and the data lines S1to Sn. Each pixel circuit20includes the light-emitting element (OLED L1), the drive transistor (TFT T4) of the first conductivity type (P-channel type) for controlling the magnitude of the electric current flowing through the light-emitting element, the first compensation transistor (TFT T2p) of the first conductivity type with the control terminal (gate terminal) thereof being connected to the first scan line GAi, and the second compensation transistor (TFT T2n) of the second conductivity type (N-channel type) with the control terminal thereof being connected to the second scan line GBi. The first and second compensation transistors are connected in series and disposed between the control terminal of the drive transistor and the conduction terminal (drain terminal) of the drive transistor that leads to the light-emitting element.

According to the display device10in accordance with the present embodiment, the first and second compensation transistors, which are connected in series and of different conductivity types, are disposed between the control terminal of the drive transistor and the conduction terminal of the drive transistor that leads to the light-emitting element, so as to enable suitable control of the conduction states of the first and second compensation transistors. The display device10in accordance with the present embodiment therefore can restrain the electrical potential on the control terminal of the drive transistor from changing in such a manner as to increase the luminance of the light-emitting element, which could otherwise be caused by the turning-off of the second compensation transistor of a different conductivity type from the drive transistor, thereby restraining washed-out black.

The first conduction terminal (top side terminal inFIG.2) of the first compensation transistor is connected to the control terminal of the drive transistor. The second conduction terminal of the first compensation transistor is connected to the second conduction terminal (top side terminal inFIG.2) of the second compensation transistor. The first conduction terminal of the second compensation transistor is connected to the conduction terminal of the drive transistor that leads to the light-emitting-element. After both the first and second compensation transistors in the pixel circuit20are turned on, the first compensation transistor is turned off earlier than the second compensation transistor. The electrical potential on the control terminal of the drive transistor therefore changes in such a manner as to decrease the luminance of the light-emitting element when the first compensation transistor is turned off and does not change when the second compensation transistor is turned off. This structure therefore can restrain the electrical potential on the control terminal of the drive transistor from changing in such a manner as to increase the luminance of the light-emitting element, which could otherwise be caused by the turning-off of the second compensation transistor of a different conductivity type from the drive transistor, thereby restraining washed-out black.

The first conductivity type has a P-channel. The transistors of the first conductivity type in the pixel circuit20, including the first compensation transistor, are made of a low-temperature polysilicon. The transistors of the second conductivity type in the pixel circuit20, including the second compensation transistor, are made of an oxide semiconductor. This structure prevents electric charge leak through the gate terminal of the drive transistor and fluctuation of the gate potential of the drive transistor, and can still restrain washed-out black. The structure can additionally implement low-frequency drive, thereby reducing the power consumption of the display device10.

The HIGH potential applied to the first scan line GAi is at the same level as the HIGH potential applied to the second scan line Ca. The LOW potential applied to the first scan line GAi is at the same level as the LOW potential applied to the second scan line GBi. Washed-out black can be restrained even when the electrical potentials applied to the first and second scan lines are specified in this manner.

The period in which the ON potential (LOW potential) is applied to the first scan line GAi partially overlaps the period in which the ON potential (HIGH potential) is applied to the associated second scan line GBi. The period in which the ON potential is applied to the first scan line GAi does not overlap the period in which the ON potential is applied to the adjacent, first scan lines GAi−1 and GAi+1. The period in which the ON potential is applied to the second scan line GBi partially overlaps the period in which the ON potential is applied to the adjacent, second scan lines GBi−1 and GBi+1.

The period in which the ON potential is applied to the second scan line G is longer than the period in which the ON potential is applied to the first scan line. Washed-out black can be restrained even when the periods in which the ON potential is applied to the first and second scan lines are specified in this manner.

The pixel circuit20includes the write control transistor (TFT T3) with the control terminal thereof being connected to the first scan line GAL This structure enables control of the write control transistor through the first scan line GAi used to control the first compensation transistor, thereby controlling writing to the pixel circuit20. The pixel circuit20includes: the first initialization transistor (TFT T1) for initializing the electrical potential on the control terminal of the drive transistor; and the second initialization transistor (TFT T7) for initializing the electrical potential on one of the terminals (anode terminal) of the light-emitting element. The first and second initialization transistors are made of an oxide semiconductor. The control terminals of the first and second initialization transistors are connected to the second scan line GBi−1, which is selected immediately before the second scan line GBi. This structure enables control of the first and second initialization transistors through the second scan line GBi−1 used to control the second compensation transistor, thereby enabling initializing the electrical potential on the control terminal of the drive transistor and the electrical potential on one of the terminals of the light-emitting element.

Second Embodiment

A display device in accordance with a second embodiment has the same structure as the display device in accordance with the first embodiment (seeFIG.1). The display device in accordance with the present embodiment differs from the display device in accordance with the first embodiment in that the pixel circuits20are replaced by the pixel circuits described below. The following description will focus on differences from the first embodiment.

FIG.6is a circuit diagram of a pixel circuit in the display device in accordance with the present embodiment. A pixel circuit30shown inFIG.6has the same structure as the pixel circuit20except that the TFT T2pand the TFT T2nare transposed. In the pixel circuit30, the TFT T2nhas a second conduction terminal (top side terminal inFIG.6) connected to the gate terminal of the TFT T4and a first conduction terminal connected to the first conduction terminal (top side terminal inFIG.6) of the TFT T2p. The TFT T2phas a second conduction terminal connected to the drain terminal of the TFT T4(conduction terminal leading to the OLED L1) and the source terminal of the TFT T6, The display device in accordance with the present embodiment operates as represented by the timing charts ofFIGS.3and5.

FIG.7is a diagram of a part ofFIG.6.FIG.7shows a parasitic capacitance Cp1between the gate terminal and the second conduction terminal of the TFT T2nand a parasitic capacitance Cp2between the gate terminal and the first conduction terminal of the TFT T2p. A description is given next of the effects of the display device in accordance with the present embodiment including the pixel circuit30

with reference toFIGS.5and7. Before time t14, the pixel circuit30operates in the same fashion as the pixel circuit20.

The electrical potential on the first scan line GAi goes HIGH at time t14, turning off the TFT T2p. Due to the presence of the parasitic capacitance Cp2and with the TFT T2nbeing ON, the gate potential of the TFT T4increases (the electrical potential is boosted up) with an increase in the electrical potential on the first scan line GAi. The electrical potential on the second scan line GBi goes LOW at time t15, turning off the TFT T2n. The gate potential of the TFT T4decreases (the electrical potential is boosted down) with a decrease in the electrical potential on the second scan line GBi due to the presence of the parasitic capacitance Cp1.

The gate potential of the TET T4increases (is boosted up) at time t14and decreases (boosted down) at time t15in this manner. The increase (boost-up) in the electrical potential cancels out the decrease (boost-down) in the electrical potential. The gate potential of the TFT T4at time t15onwards is therefore at the same level as the gate potential of the TFT T4before time t14. Hence, the use of the pixel circuit30can restrain washed-out black, which could otherwise be caused by the turning-off of the TFT T2n.

As described above, in the display device in accordance with the present embodiment, the second conduction terminal (top side terminal inFIG.8) of the second compensation transistor (TFT T2n) is connected to the control terminal (gate terminal) of the drive transistor TFT T4), the first conduction terminal of the second compensation transistor is connected to the first conduction terminal (top side terminal inFIG.8) of the first compensation transistor (TFT T2p), and the second conduction terminal of the first compensation transistor is connected to the conduction terminal (drain terminal) of drive transistor that leads to the light-emitting element. After both the first and second compensation transistors in the pixel circuit30are turned on, the first compensation transistor is turned off earlier than the second compensation transistor in the present embodiment, similarly to the previous embodiment.

The electrical potential on the control terminal of the drive transistor changes in such a manner as to decrease the luminance of the light-emitting element when the first compensation transistor is turned off and changes in such a manner as to increase the luminance of the light-emitting element when the second compensation transistor is turned off. The first and second changes in the electrical potential on the control terminal of the drive transistor are cancelled out. That can in turn restrain the electrical potential on the control terminal of the drive transistor from changing, which could otherwise be caused by the turning-off of the second compensation transistor of a different conductivity type from the drive transistor, thereby restraining washed-out black. In addition, the display device in accordance with the present embodiment can achieve the same effects as the display device10in accordance with the first embodiment.

The display devices in accordance with the first and second embodiments (hereinafter, the “preceding embodiments”) can be modified to constitute many variation examples.FIG.8is a circuit diagram of a pixel circuit in a display device in accordance with a first variation example. A pixel circuit40shown inFIG.8has the same structure as the pixel circuit30(FIG.6) in accordance with the second embodiment except that the former includes a capacitor C2. The capacitor C2is disposed between the control terminal of the drive transistor and the control terminal of the first compensation transistor. Specifically, one of the electrodes of the capacitor C2(top side electrode inFIG.8) is connected to the gate terminal of the TFT T4. The other electrode of the capacitor C2is connected to the gate terminal of the TFT T2p. This provision of the capacitor C2between the control terminal of the drive transistor and the control terminal of the first compensation transistor suitably cancels out the increase (boost-up) in the electrical potential through the parasitic capacitance (not shown) and the decrease (boost-down) in the electrical potential through the capacitor C2. That in turn restrains washed-out black, which could otherwise be caused by the turning-off of the second compensation transistor of a different conductivity type from the drive transistor.

In the display devices in accordance with the preceding embodiments, when both the first and second compensation transistors are OFF, the second compensation transistor (TFT T2n) is turned on earlier than the first compensation transistor (TFT T2p); and when both the first and second compensation transistors are ON, the first compensation transistor is turned off earlier than the second compensation transistor. In contrast, the first compensation transistor is turned on earlier than the second compensation transistor in a display device in accordance with a second variation example when both the first and second compensation transistors are OFF; and the second compensation transistor is turned off earlier than the first compensation transistor in a display device in accordance with a third variation example when both the first and second compensation transistors are ON. The display devices in accordance with the second and third variation examples can achieve the same effects as the display devices in accordance with the preceding embodiments. Alternatively, in the display device in accordance with the first variation example, the second compensation transistor may be turned off earlier than the first compensation transistor when both the first and second compensation transistors are ON. In this display device, the electrical potential on the control terminal of the drive transistor is increased (boosted up) through the parasitic capacitance (not shown) and thereafter decreased (boosted down) through the capacitor C2. The increase (boost-up) in the electrical potential hence suitably cancels out the decrease (boost-down) in the electrical potential.

The control terminals of the first and second initialization transistors (TFTs T1and T7) are connected to the second scan line GBi, which is selected immediately before the second scan line GBi, in the display devices in accordance with the preceding embodiments. The control terminal of the first initialization transistor is connected to the second scan line GBi−2, which is selected two second scan lines before the second scan line GBi, or to the second scan line that is selected before the second scan line GBi−2, in a display device in accordance with a fourth variation example. In a display device in accordance with a fifth variation example, the control terminal of the second initialization transistor is connected to the second scan line GBi or the second scan line that is selected two or more second scan lines before the second scan line GBi. The display devices in accordance with the fourth and fifth variation examples can achieve the same effects as the display devices in accordance with the preceding embodiments.

Each drive transistor has a P-channel in the pixel circuit in the display devices in accordance with t preceding embodiments. Each drive transistor may have a N-channel in the pixel circuit in a display device in accordance with a sixth variation example. In each pixel circuit in the display device in accordance with a seventh variation example, each transistor is of an opposite conductivity type to the corresponding transistor in the pixel circuit described above. The polarity of the electrical potential applied to each signal line connected to the pixel circuit in the display device in accordance with the seventh variation example is opposite to that for the original pixel circuit (the HIGH and LOW potentials are reversed).

The HIGH potential applied to the first scan line GAi is at the same level as the HIGH potential applied to the second scan line GBi; the LOW potential applied to the first scan line GAi is at the same level as the LOW potential applied to the second scan line GBi; and the voltage on the first scan line GAi has the same amplitude as the voltage on the second scan line GBi, in the display devices in accordance with the preceding embodiments. In a display device in accordance with an eighth variation example, the voltage on the first scan line GAi has a greater amplitude than the voltage on the second scan line GBi. Particularly, in the display device in accordance with the second embodiment, the voltage on the first scan line GAi preferably has a greater amplitude than the voltage of the second scan line GBi. The increase (boost-up) in the electrical potential and the decrease (boost-down) in the electrical potential can be suitably cancelled out by adjusting the amplitude of the voltage on the first scan line GAi and the amplitude of the voltage on the second scan line GBi in accordance with the electrostatic capacities of the parasitic capacitances Cp1and Cp2shown inFIG.7.

The first and second initialization transistors (TFTs T1and T7) are connected in parallel in the pixel circuits in the display device in accordance with the preceding embodiments. The first and second initialization transistors are made of an oxide semiconductor and connected in series in the pixel circuits in a display device in accordance with a ninth variation example.FIG.9is a circuit diagram of the pixel circuit in the display device in accordance with the ninth variation example.FIG.9shows a row i, column j pixel circuit50and a row (i+1), column j pixel circuit50. A description is given next of the row i, column j pixel circuit50.

In the row i, column j pixel circuit50, the gate terminal of the TFT T1is connected to the second scan line GBi−2; the gate terminal of the TFT T7is connected to the second scan line GBi−1; and the source terminal of the TFT T7is connected to the gate terminal of the TFT T4in the row (i+1), column j pixel circuit.

FIG.10is a timing chart for the display device in accordance with the ninth variation example. InFIG.10, the period from time t21to time t25is an initialization period, the period from time t25to time t26is a write period, and the period before time t21and the period after time t27are light-emitting periods. The electrical potential on the second scan line GBi−2 is HIGH from time t21to time t23. At this time, the TFT T1is turned on, and the gate potential of the TFT T4becomes equal to the initialization electrical potential Vini. The electrical potential on the second scan line GBi−1 is HIGH from time t22to time t25. At this time, the TFT T7is turned on, and the anode terminal of the OLED L1is fed with the initialization electrical potential Vini applied to the gate terminal of the TFT T4in the row (i+1), column j pixel circuit.

Since the two pixel circuits50are connected through the TFTs T1and T7, a leak current through the TFTs T1and T7in the pixel circuits50may cause the pixel circuits50to malfunction if the TFTs T1and17are made of a low-temperature polysilicon. The TFTs T1and17are therefore made of an oxide semiconductor such as IGZO in the display device in accordance with the ninth variation example, which prevents the pixel circuits50from malfunctioning due to the leak current through the TFTs T1and T7.

Connecting the TFTs T1and T7in series reduces the number of signal lines connected to the electrically conductive member having the initialization electrical potential Vini and hence reduces load on this electrically conductive member. Therefore, in the display device in accordance with the ninth variation example, the pixel circuits50are fed with an initialization electrical potential Vini that is stable to noise.

A description is given next of the effects of the use of the N-channel transistor, in place of the P-channel transistor, as the initialization transistor with reference toFIG.11. Assume here that the initialization electrical potential Vini is −5 V, the HIGH potential on the second scan line GBi−1 is 7 V, the LOW potential on the second scan line GBi−1 is −10 V, and the gate potential of the TFT T4is decreased by initialization from a preceding frame electrical potential (>Vini) to the initialization electrical potential Vini.

If the TFT T1is a P-channel transistor (FIG.11(a)), a gate-to-source voltage Vgs of the TFT T1decreases with the progress of initialization, eventually to −5 V On the other hand, if the TFT T1is a N-channel transistor (FIG.11(b)), since the TFT T1is grounded through the source terminal thereof, the gate-to-source voltage Vgs of the TFT T1is constant at 15 V irrespective of the progress of initialization. In addition, the TFT T1, which has a N-channel, exhibits a high drive capability when the gate-to-source voltage Vgs is equal to 15 V. The same applies to the TFT T7. For these reasons, the use of a N-channel transistor as the initialization transistor enables quick completion of the initialization of the gate potential of the TFT T4and the initialization of the anode potential of the OLED L1. That in turn renders the display device more adaptable to high frame frequency display.

The description has so far discussed OLED display devices including pixel circuits including OLEDs (organic light-emitting diodes) as an example of a display device including pixel circuits including light-emitting elements. The same description applies to inorganic LED display devices including pixel circuits including inorganic light-emitting diodes, QLED (quantum-dot light-emitting diode) display devices including pixel circuits including quantum-dot light-emitting diodes, LED display devices including pixel circuits including mini-LEDs or micro-LEDs. Any of the features of the display devices described above may be combined as far as the combination does not contradict the nature of the features, so as to constitute a display device that has both the features of any of the preceding embodiments and the features of any of the variation examples.