Patent ID: 12205661

DETAILED DESCRIPTION

FIG.1is a block diagram for explaining a memory system according to some example embodiments.

Referring toFIG.1, a memory system1according to some example embodiments may include a memory controller100and a memory device200.

The memory controller100may generally control the operation of the memory system1. The memory controller100may apply an operation command for controlling the memory device200to control the operation of the memory device200.

The memory controller100may control a data exchange between a host and the memory device200. The memory controller100may write data in the memory device200or read data from the memory device200in response to a request from the host.

For example, the memory controller100may transmit a clock signal CLK, a command CMD and an address ADDR to the memory device200, and send and receive data DQ to and from the memory device200. The memory device200may transmit a decoding state flag DSF or a fail row flag RFF to the memory controller100.

The decoding state flag DSF may include information about whether to detect an error occurring in the memory cell array300of the memory device200and whether to correct the detected error. The fail row flag RFF may include information about the fact that the row of the memory cell array300indicated by the read row address (included in the read address input together with a read command) is a fail row.

The memory device200may include a control logic210, a memory cell array300, an ECC (Error Correction Code) engine400, a row fail detector500, and a flag generator600.

In some example embodiments, the memory device200may be a DRAM (dynamic random access), a DDR4 (double data rate 4) SDRAM (synchronous DRAM), an LPDDR4 (low power DDR4) SDRAM or a LPDDR5 SDRAM, a DDR5 SDRAM, or a GDDR (graphic DDR) including dynamic memory cells. According to some example embodiments, the memory device200may be a static memory (SRAM) device that includes static memory cells (or bit cells).

The control logic210may generally control the operation of the memory device200.

The ECC engine400may detect an error of the read data, which are read from the memory cell array300, under the control of the control logic210, and may generate an error occurrence signal, correct the error, and output read data in which an error is corrected. The ECC engine400may generate a parity bit for the write data to be written in the memory cell array300under the control of the control logic210, and the parity bits thus generated may be written in the memory cell array300together with the write data.

The row fail detector500may periodically detect the fail row address based on the error occurrence signal that is output from the ECC engine400.

The flag generator600may generate a decoding state flag DSF or a fail row flag RFF based on the fail row address that is output from the row fail detector500and the error occurrence signal that is output from the ECC engine400. The decoding state flag DSF may indicate whether an error has been detected from the read data read from the memory cell array300and whether to correct the detected error. The fail row flag RFF may indicate that the read row address included in the read address is a fail row address.

The decoding state flag DSF and the fail row flag RFF may be made up of two or more bits and may have different values from each other. For example, the decoding state flag DSF and the fail row flag RFF may be made up of two bits, and may have different values from each other. The fail row flag may have a first value, and the decoding state flag DSF may have one of second to fourth values different from the first value. For example, the fail row flag RFF may have a value of ‘10’, and the decoding state flag DSF may have any one of values ‘00’, ‘01’ and ‘11’. The decoding state flag DSF may have a value of ‘00’ when no error is detected, may have a value of ‘01’ when an error is detected and the detected error is corrected, and may have a value of ‘11’ when the error is detected and the error is not corrected. The decoding state flag DSF and the fail row flag RFF may have fixed values, and the memory controller100may set a mode register set for setting the mode of the memory device200to change the type of error bits that indicate the decoding state flag DSF and the fail row flag RFF.

FIG.2is a block diagram for explaining the memory device ofFIG.1.

Referring toFIGS.1and2, a memory device200A may include the control logic210, an address register220, a bank control logic230, a row address multiplexer240, a refresh address generator245, a column address latch250, a row decoder260, a column decoder270, a sense amplifier285, an I/O gating circuit290, the memory cell array300, the ECC engine400, the row fail detector500, the flag generator600, and a data I/O buffer295.

The memory cell array300may include a plurality of memory cells MC for storing data. For example, the memory cell array300may include first to eighth bank arrays310to380. Each of the first to eighth bank arrays310to380may include a plurality of word lines WL, a plurality of bit lines BTL, and a plurality of memory cells MC formed at points where the word lines WL and the bit line BTL intersect.

The plurality of memory cells MC may include the first to eighth bank arrays310to380. AlthoughFIG.2shows the memory device200A including eight bank arrays310to380, embodiments are not limited thereto, and the memory device200A may include any number of bank arrays.

The control logic210may control the operation of the memory device200A. For example, the control logic210may generate the control signals such that the memory device200A performs an operation of writing the data or an operation of reading the data. The control logic210may include a command decoder211that decodes the command CMD received from the memory controller100, and a mode register212for setting the operating mode of the memory device200A.

For example, the command decoder211may decode a write enable signal /WE, a row address strobe signal /RAS, a column address strobe signal /CAS, a chip selection signal /CS, and the like to generate the control signals corresponding to the command CMD. The control logic210may also receive a clock signal CLK and a clock enable signal /CKE for driving the memory device200A in a synchronous manner.

The control logic210may control the refresh address generator245to generate a refresh row address REF_ADDR in response to a refresh command.

The address register220may receive the address ADDR from the memory controller100. For example, the address register220may receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register220may provide the received bank address BANK_ADDR to the bank control logic230, provide the received row address ROW_ADDR to the row address multiplexer240, and provide the received column address COL_ADDR to the column address latch250.

The bank control logic230may generate a bank control signal in response to the bank address BANK_ADDR received from the address register220. In response to the bank control signals, a bank row decoder corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders260ato260hmay be activated, and a bank column decoder corresponding to the bank address BANK_ADDR among first to eighth bank column decoders270ato270hmay be activated.

The row address multiplexer240may receive the row address ROW_ADDR from the address register220, and receive the refresh row address REF_ADDR from the refresh address generator245. The row address multiplexer240may selectively output the row address ROW_ADDR received from the address register220or the refresh row address REF_ADDR received from the refresh address generator245, as a row address RA. The row address RA that is output from the row address multiplexer240may be applied to each of the first to eighth bank row decoders260ato260h.

The refresh address generator245may generate a refresh row address REF_ADDR for refreshing the memory cells. The refresh address generator245may provide the refresh row address REF_ADDR to the row address multiplexer240. As a result, the memory cells placed on the word line corresponding to the refresh row address REF_ADDR may be refreshed.

The column address latch250may receive the column address COL_ADDR from the address register220and temporarily store the received column address COL_ADDR. The column address latch250may gradually increase the received column address COL_ADDR in a burst mode. The column address latch250may apply the temporarily stored or gradually increased column addresses COL_ADDR to each of the first to eighth bank column decoders270ato270h.

The row decoder260may include the first to eighth bank row decoders260ato260hconnected to each of the first to eighth bank arrays310to380. The column decoder270may include first to eighth bank column decoders270ato270hconnected to each of the first to eighth bank arrays310to380. The sense amplifier285may include first to eighth bank sense amplifiers285ato285hconnected to each of the first to eighth bank arrays310to380.

The bank row decoder activated by the bank control logic230among the first to eighth bank row decoders260ato260hmay decode the row address RA output from the row address multiplexer240to activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line drive voltage to the word line corresponding to the row address RA.

The bank column decoder activated by the bank control logic230among the first to eighth bank column decoders270ato270hmay activate the bank sense amplifiers285ato285hcorresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I/O gating circuit290.

The I/O gating circuit290may include an input data mask logic, read data latches for storing the data output from the first to eighth bank arrays310to380, and write drivers for writing data in the first to eighth bank arrays310to380, together with gating circuits for gating the I/O data.

A code word CW to be read from one of the first to eighth bank arrays310to380may be detected by the bank sense amplifiers285ato285hcorresponding to the one bank array, and may be stored in the read data latches. The ECC engine400may perform ECC decoding on the code word CW stored in the read data latches. When an error is detected from the data of the code word CW, the ECC engine400may output a first error occurrence signal EGS_R, while correcting the error, and may provide the corrected data DQ to the memory controller100through the data I/O buffer295. The first error occurrence signal EGS_R and a syndrome SDR generated in the process of detecting an error from data of the code word CW by the ECC engine400may be provided to the flag generator600.

Data DQ to be written in one of the first to eighth bank arrays310to380may be provided to the ECC engine400, the ECC engine400may generate the parity bits based on the data DQ, and provide the data DQ and the parity bits to the I/O gating circuit290. The I/O gating circuit290may write the data DQ and the parity bits on a subpage of the one bank array through the write drivers.

The data I/O buffer295may provide the data DQ to the ECC engine400based on the clock signal CLK provided from the memory controller100in the write operation, and may provide the data DQ provided from the ECC engine400to the memory controller100in the read operation.

The ECC engine400may perform ECC decoding on the code word that is read from each row in which the refresh operation is performed, in a section in which the refresh operation is performed on a plurality of rows included in the memory cell array300. The ECC engine400may perform the ECC decoding by reading a code word from each of the subpages that make up a single row. When an error is detected from the code word data that is read from each row, the ECC engine400may output a second error occurrence signal EGS_S, and may perform a scrubbing operation of correcting the error and writing the error-corrected data on the corresponding subpage again. Thus, the ECC engine400may output the second error occurrence signal EGS_S and perform the scrubbing operation in an error check and scrubbing section among the sections in which the refresh operation is performed on the plurality of rows included in the memory cell array300.

The row fail detector500may receive and count the second error occurrence signal EGS_S from the ECC engine400. For example, the row fail detector500may count the second error occurrence signal EGS_S for each row included in the memory cell array300, and detect the fail row based on this. The row fail detector500may provide the fail row address FAIL_ADDR corresponding to the fail row to the flag generator600.

The row fail detector500may detect fail rows in the error check and scrubbing section among the sections in which the refresh operation on a plurality of rows included in the memory cell array300is performed. Accordingly, the row fail detector500may periodically detect the fail row address FAIL_ADDR corresponding to the fail row.

The flag generator600may receive a read row address R_ADDR from the address register220, receive the syndrome SDR and the first error occurrence signal EGS_R from the ECC engine400, and receive the fail row address FAIL_ADDR from the row fail detector500. The flag generator600may generate the decoding state flag DSF or the fail row flag RFF based on the read row address R_ADDR, the fail row address FAIL_ADDR, the syndrome SDR, and the first error occurrence signal EGS_R, and may provide the decoding state flag DSF or the fail row flag RFF to the memory controller100.

The control logic210may generate a first control signal CTL1for decoding the command CMD to control the I/O gating circuit290, a second control signal CTL2for generating the ECC engine400, a third control signal CTL3for controlling the row fail detector500, and a fourth control signal CTL4and a comparison signal CTL_CE for controlling the flag generator600. The control logic210may generate the comparison signal CTL_CE based on the second error occurrence signal EGS_S provided from the ECC engine400.

FIG.3is a block diagram for explaining the ECC engine ofFIG.2. For convenience of explanation, the first bank array310is shown along with the ECC engine400.

Referring toFIG.3, the first bank array310may include a normal cell array NCA (memory cell array310a) and a redundancy cell array RCA (ECC cell array310b).

The ECC engine400may include an ECC encoding circuit410and an ECC decoding circuit420.

The ECC encoding circuit410may generate parity bits PRT related to the write data WDQ to be written in the memory cells of the normal cell array NCA (310a) in response to the second control signal CTL2. The parity bits PRT may be stored in the redundancy cell array RCA (310b). According to the present example embodiment, the ECC encoding circuit410may generate parity bits PRT on the write data WDQ to be written in the memory cells including the fail cell of the normal cell array NCA (310a) in response to the second control signal CTL2.

The ECC decoding circuit420may correct an error, using data RDQ that is read (i.e., read data) from the memory cells of the normal cell array NCA (310a) and the parity bits PRT read from the redundancy cell array RCA (310b) in response to the second control signal CTL2, and may output error-corrected data CDQ. According to the present example embodiment, the ECC decoding circuit420may correct an error, using the read data RDQ that is read from the memory cells including the fail cell of the normal cell array NCA (310a) and the parity bits read from the redundancy cell array RCA (310b) in response to the second control signal CTL2, and may output the error-corrected data CDQ. The ECC decoding circuit420may output the error occurrence signals EGS_R, EGS_S, while correcting the error. The ECC decoding circuit420may output the first error occurrence signal EGS_R at the time of the read operation of the memory device200, and may output the second error occurrence signal EGS_S at the time of the scrubbing operation of the memory device200.

FIG.4is a block diagram for explaining the ECC encoding circuit ofFIG.3.

Referring toFIG.4, the ECC encoding circuit410may include a parity generator412that receives write data WDQ and basis bit BB in response to the second control signal CTL2, and generates the parity bits PRT, using an XOR array calculation. The basis bit BB may be bits for generating the parity bits PRT of the write data WDQ. The basis bit BB may be made up of, for example, b′00000000 bits. The basis bit BB may utilize other specific bits instead of the b′00000000 bits.

FIG.5is a block diagram for explaining the ECC decoding circuit ofFIG.3.

Referring toFIG.5, the ECC decoding circuit420may include a syndrome generator422, a coefficient calculator424, an error position detector426, and an error corrector428.

The syndrome generator422may receive the read data RDQ and the parity bit PRT in response to the second control signal CTL2, and generate the syndrome SDR, using the XOR array calculation.

The coefficient calculator424may calculate a coefficient of an error position equation, using the syndrome SDR. The error position equation may be an equation in which a reciprocal of the error bit is a radix.

The error position detector426may calculate the position of a 1-bit error, using the calculated error position equation. The error position detector426may provide the error corrector428with an error position signal EPS indicating the position of a 1-bit error. When an error is detected from the read data RDQ, the error position detector426may output an error occurrence signal EGS, e.g., EGS_R and/or EGS_S.

The error corrector428may receive the read data RDQ and determine the position of the 1-bit error included in the read data RDQ based on the error position signal EPS. The error corrector428may correct the error by inverting the logic value of the bit in which the error has occurred among the read data RDQ according to the determined 1-bit error position information, and may output the error-corrected read data CDQ.

FIG.6is a block diagram for explaining the row fail detector ofFIG.2.

Referring toFIGS.2and6, the row fail detector500may include a counter510, a threshold register520, a comparator530, and a fail row address generator540.

The counter510may receive the second error occurrence signal EGS_S generated in the code word that is read from each row in which the refresh operation is performed from the ECC engine400. The counter510may receive the second error occurrence signal EGS_S and count the second error occurrence signal EGS_S. The counter510may provide a signal NOE indicating the number of error occurrences to the comparator530based on the counted second error occurrence signal EGS_S.

The threshold register520may store a threshold TH_F. The threshold TH_F may be, for example, a value that is set in response to a command CMD provided from the memory controller (100ofFIG.1).

The comparator530may compare the signal NOE indicating the number of error occurrences with the threshold TH_F read from the threshold register520, and output a comparison signal CS_E indicating a comparison result.

The fail row address generator540may receive the comparison signal CS_E and the read row, and may generate a fail row address FAIL_ADDR based on the comparison signal CS_E. For example, the fail row address generator540may determine a row as a fail row when the number of error occurrences occurring in the code word read from the row is equal to or greater than the threshold TH_F, and may output a row address S_ADDR indicated by the row as the fail row address FAIL_ADDR.

As a result, the row fail detector500may detect whether each row on which the refresh is performed is a fail row.

FIG.7is a block diagram for explaining the flag generator ofFIG.2.

Referring toFIGS.2and7, the flag generator600may include a register610, an address comparator620, and a signal generator630.

The fail row address FAIL_ADDR provided from the row fail detector500may be stored in the register610.

The address comparator620may receive the read row address R_ADDR included in the read address ADDR at the time of the read operation of the memory cell array300. The address comparator620may compare the read row address R_ADDR with the fail row address FAIL_ADDR read from the register610, and output a comparison signal CS_A indicating a comparison result.

The signal generator630may receive the comparison signal CS_A and output the decoding state flag DSF or the fail row flag RFF based on the comparison signal CS_A. The signal generator630may generate the fail row flag RFF when the read row address R_ADDR is the same as the fail row address FAIL_ADDR read from the register610. The signal generator630may generate the decoding state flag DSF when the read row address R_ADDR is not the same as the fail row address FAIL_ADDR read from the register610. The signal generator630may generate a decoding state flag DSF based on the comparison signal CTL_CE provided from the control logic210and the first error occurrence signal EGS_R provided from the ECC engine400.

FIG.8is a diagram for explaining the operation of the memory device ofFIG.2.

InFIG.8, a memory core/peri201is assumed to include the components, except for the ECC engine400, the row fail detector500, and the flag generator600, in the memory device200A ofFIG.2.

Referring toFIGS.2and8, the flag generator600may generate a decoding state flag DSF or a fail row flag RFF, based on the fail row address FAIL_ADDR provided from the row fail detector500and the first error occurrence signal EGS_R provided from the ECC engine400. The row fail detector500may detect a fail row based on the second error occurrence signal EGS_S provided from the ECC engine400and output the fail row address FAIL_ADDR.

The memory device200may include a first pin202and a second pin204different from each other.

The memory device200may send and receive data DQ to and from the memory controller100through the first pin202. The data DQ in which an error is corrected by the ECC engine400may be provided to the memory controller100through the first pin202. The first pin202may be, for example, a data pin.

The memory device200may provide the memory controller100with the decoding state flag DSF or the fail row flag RFF through the second pin204. The second pin204may be, for example, a DMI pin. The second pin204may be made up the first sub-pin and a second sub-pin different from each other, and the decoding state flag DSF or the fail row flag RFF may be made up of two bits accordingly.

FIG.9is a flowchart for explaining the operation of the memory device according to some example embodiments.FIG.10is a flowchart for explaining operation S140ofFIG.9.FIG.11is a flowchart for explaining operation S150ofFIG.9.FIG.12is a timing diagram for explaining the operation of the memory device according to the example embodiments ofFIG.9.

Referring toFIGS.1to9, a memory device200according to some example embodiments may receive a read command READ_CMD and a read address READ_ADDR from the memory controller100(S100). The read row address R_ADDR included in the read address READ_ADDR and the fail row address FAIL_ADDR detected from the row fail detector500may be provided to the address comparator620of the flag generator600.

The address comparator620may compare whether the read row address R_ADDR and the fail row address FAIL_ADDR are the same (S110). The address comparator620may output the comparison signal CS_A indicating the comparison result.

The signal generator630of the flag generator600may generate a fail row flag RFF when the read row address R_ADDR and the fail row address FAIL_ADDR are the same (S110, Y) based on the comparison signal CS_A (S120). The fail row flag RFF may be made up of two bits, and may have a value of ‘10’.

The data in which an error is corrected by the ECC engine400, and the fail row flag RFF generated by the flag generator600may be output (S130).

On the other hand, at operation S110, when the read row address R_ADDR and the fail row address FAIL_ADDR are not the same (S110, N) based on the comparison signal CS_A, the signal generator630of the flag generator600may determine whether the number of errors detected in the scrubbing operation of the memory device200is equal to or greater than a threshold TH_CE based on a comparison signal CTL_CE provided from the control logic210(S115). The threshold TH_CE may be, for example, a value that is set from the memory controller100, and may be set depending on the specifications of the memory device200.

When the comparison signal CTL_CE indicates that the number of errors detected is equal to or greater than the threshold TH_CE (S115, Y), the signal generator630may generate the decoding state flag DSF, without considering the threshold TH_CE (S140).

Referring to operation S140inFIG.10, when the ECC engine400has capability of SEDSEC (single bit error detection single bit error correction), the signal generator630may determine whether an error is detected from the read data and whether the error is corrected, based on a syndrome SDR provided from the ECC engine400and the number of counted first error occurrence signals EGS_R.

The signal generator630may determine whether the decoding result of the ECC engine400is a case where no error is detected from the read data (No Error; NE) (S141). For example, when the syndrome SDR is 0 and the number of counted first error occurrence signals EGS_R is 0, the signal generator630may determine that there is a case where no error is detected from the read data. At operation S141, when the decoding result of the ECC engine400is a case where no error is detected from the read data (S141, NE=Y), the signal generator630may generate a decoding state flag DSF indicating this (S142). The decoding state flag DSF may be made up of two bits and may have a value of ‘00’.

At operation S141, when the decoding result of the ECC engine400is not a case where no error is detected from the read data (S141, NE=N), the signal generator630may determine whether there is a case where one error is detected and corrected from the read data (Correctable Error; CE) (S143). For example, when the syndrome SDR is not 0 and the number of counted first error occurrence signals EGS_R is 1, the signal generator630may determine that there is a case one error is detected from the read data and corrected. At operation S143, when the decoding result of the ECC engine400is a case where one error is detected from the read data and corrected (S143, CE=Y), the signal generator630may generate the decoding state flag DSF indicating this (S144). The decoding state flag DSF may be made up of two bits, and may have a value of ‘01’ (DSF_CE(01)). At operation S143, when the decoding result of the ECC engine400is not a case where one error is detected from the read data and corrected (S143, CE=N), the signal generator630may generate a decoding state flag DSF indicating a case UE where two or more errors are found from the read data and are not corrected. The decoding state flag DSF may be made up of two bits, and may have a value of ‘11’ (DSF_UE(11)).

Referring toFIGS.1to9again, when the comparison signal CTL_CE at operation S115ofFIG.9indicates that the number of errors detected in the scrubbing operation of the memory device200is less than the threshold TH_CE (S115, N), the signal generator630may generate a decoding state flag DSF in consideration of the threshold TH_CE (S150).

Referring to operation S150inFIG.11, when the ECC engine400has capability of SEDSEC, the signal generator630may determine whether an error is detected from the read data and whether the error is corrected, based on the syndrome SDR provided from the ECC engine400and the first error occurrence signal EGS_R.

The signal generator630may determine whether the decoding result of the ECC engine400is a case NE where no error is detected from the read data (S151). For example, when the syndrome SDR is 0 and the number of counted first error occurrence signals EGS_R is 0, the signal generator630may determine that there is a case where no error is detected from the read data. At operation S151, when the decoding result of the ECC engine400is a case where no error is detected from the read data (S151, NE=Y), the signal generator630may generate a decoding state flag DSF indicating this (S152). The decoding state flag DSF may be made up of two bits, and may have a value of ‘00’ (DSF_NE(00)).

At operation S151, when the decoding result of the ECC engine400is not a case where no error is detected from the read data (S151, NE=N), the signal generator630may determine whether there is a case where one error is detected from the read data and corrected (S153). For example, when the syndrome SDR is not 0 and the number of counted first error occurrence signals EGS_R is 1, the signal generator630may detect that there is a case where one error is detected from the read data and corrected. When the decoding result of the ECC engine400at operation S153is a case where one error is detected from the read data and corrected (S153, CE=Y), the signal generator630may perform operation S152. Thus, the signal generator630may generate a decoding state flag DSF that is made up of two bits and has a value of ‘00’. The signal generator630may not generate a decoding state flag DSF having a value of ‘01’.

When the decoding result of the ECC engine400at operation S153is not a case where one error is detected from the read data and corrected (S153, CE=N), the signal generator630may generate a decoding state flag DSF indicating a case UE where two or more errors are found from the read data and not corrected. The decoding state flag DSF may be made up of two bits and may have a value of ‘11’ (DSF_UE(11)).

Referring toFIGS.1to9again, the data in which an error is corrected by the ECC engine400and the decoding state flag DSF generated by the flag generator600may be output (S160ofFIG.9). For example, the decoding state flag DSF may be made up of two bits, and may have any one value among ‘00’, ‘01’, ‘10’ and ‘11’.

Referring toFIG.12, the clock signal CLK may be provided from the memory controller100to the memory device200. A write clock signal WCK may be provided from the memory controller100together with the command CMD. A read strobe signal RDQS is a signal that is transmitted to the memory controller100together with the data DQ by the memory device200. A read latency RL may indicate a delay from the reception of the read command READ to the output of the data DQ.

The read data DQ may be provided to the memory controller100in burst units DQ_BRT through the first pin (202ofFIG.8).

The decoding state flag DSF or the fail row flag RFF may be provided to the memory controller100through the second pin204. The second pin (204ofFIG.8) may be a DMI pin (DMIP). The decoding state flag DSF or the fail row flag RFF may be output together with the read data DQ.

When generating the decoding state flag DSF in consideration of the threshold of correctable error as in operation S150, when it is less than the threshold of correctable error, the memory device200may only output a decoding state flag DSF indicating a case NE where no error is detected from the read data or a decoding state flag DSF indicating a case UE where two or more errors are found and not corrected. Therefore, the memory controller100may not determine whether there is a case CE where one error is detected in the read row address R_ADDR and corrected. Thus, even when the read row address R_ADDR is a fail row, the memory controller100may not determine this.

On the other hand, when the read row address R_ADDR is a fail row address as in operation S110, the memory device200according to some example embodiments may output a fail row flag RFF irrespective of the threshold of correctable error. As a result, the memory controller100may determine that it is a fail row, and may determine an error management policy based on this. Therefore, the reliability of the memory device200may be further improved or enhanced.

FIG.13is a block diagram for explaining the operation of the memory device according to some other example embodiments.FIG.14is a timing diagram for explaining the operation of the memory device according to the embodiment ofFIG.13.

Referring toFIGS.1to13, a memory device200according to some example embodiments may receive a read command READ_CMD and a read address READ_ADDR (S200), and compare whether the read row address R_ADDR and the fail row address FAIL_ADDR are the same (S210). Operations S200, S210, and S215may correspond to operations S100, S110, and S115ofFIG.10, respectively.

At operation S210, when the read row address R_ADDR and the fail row address FAIL_ADDR are the same based on the comparison signal CS_A (S210, Y), the signal generator630of the flag generator600may generate the decoding state flag DSF without considering the threshold TH_CE (S220). When the row address R_ADDR and the fail row address FAIL_ADDR are not the same based on the comparison signal CS_A at operation S210(S210, N), and the comparison signal CTL_CE indicates that the number of detected errors is equal to or greater than the threshold TH_CE at operation S215(S215, Y), the signal generator630of the flag generator600may perform the operation of S220. Operation S220may correspond to operation S140ofFIGS.9and10.

When the comparison signal CTL_CE at operation S215indicates that the number of detected errors is less than the threshold TH_CE (S215, N), the signal generator630may generate the decoding state flag DSF in consideration of the threshold TH_CE (S230). Operation S230may correspond to operation S150ofFIGS.9and10.

The data in which an error is corrected by the ECC engine400and the decoding state flag DSF generated by the flag generator600may be output (S240). For example, the decoding state flag DSF may be made up of two bits, and may have any one value among ‘00’, ‘01’, and ‘11’.

Referring toFIG.14, the read data DQ may be provided to the memory controller100in burst units DQ_BRT through the first pin (202ofFIG.8).

The decoding state flag DSF may be provided to the memory controller100through the second pin204. The second pin (204ofFIG.8) may be a DMI pin (DMIP). The decoding state flag DSF may be output together with the read data DQ. When the read row address R_ADDR is a fail row address, the memory device200according to some example embodiments may output the decoding state flag DSF indicating a case CE where one error is detected from the read data and corrected, regardless of the threshold of correctable error. As a result, the memory controller100may monitor the decoding state flag DSF of the read row address R_ADDR, and may determine the error management policy based on this. Therefore, the reliability of the memory device200may be further improved or enhanced.

FIG.15is a block diagram for explaining the memory device ofFIG.1according to some other example embodiments.FIG.16is a diagram for explaining the flag generator ofFIG.15. For convenience of explanation, points different from those explained referring toFIGS.1and2will be mainly explained.

Referring toFIGS.15and16, a memory device200B according to some other example embodiments may include a register650.

The row fail detector500may detect the fail row address of the memory cell array300and store the detected fail row address FAIL_ADDR in the register650. The row fail detector500may read the fail row address FAIL_ADDR from the register650and provide it to the flag generator600in response to the third control signal CTL3.

The flag generator600may receive the fail row address FAIL_ADDR to generate a decoding state flag DSF or a fail row flag RFF.

FIG.17is a block diagram for explaining the memory controller ofFIG.1.

Referring toFIGS.1and17, the memory controller100may include a decoding state flag or a fail row flag decoder120and a controller140.

The decoding state flag or fail row flag decoder120may decode the decoding state flag DSF or the fail row flag RFF provided from the memory device200to generate a decoding signal DS.

The controller140may monitor the fail row address of the memory cell array300or the row address in which an error is detected, based on the decoding signal DS. The controller140may determine the error management policy of the memory device200based on the decoding signal DS.

For example, when the decoding signal DS indicates a case NE where no error is detected from the read data (for example, when it has a value of ‘00’), the controller140may maintain the error management policy as it is.

When the decoding signal DS indicates that one error is detected from the read data and corrected CE (for example, when it has a value of ‘01’), the controller140may monitor that row. The controller140may monitor that row and determine whether it corresponds to a fail row.

When the decoding signal DS indicates a fail row address (e.g., when it has a value of ‘10’), the controller140may perform a page offline of that row. The controller140may change the error management policy so as not to use that row.

When the decoding signal DS indicates a case UE where two or more errors are found and are not corrected (when it has a value of ‘11’), since the data is data including an error, the controller140may retry to read the data to the memory device200. Thus, the read command may be provided to the memory device200again. Alternatively, the controller140may repair that row with an extra row. Alternatively, the controller140may change the error management policy so as not to use that row.

FIG.18is a block diagram for explaining a memory device according to some example embodiments.

Referring toFIG.18, a memory device700according to some example embodiments may be implemented using a 3D chip structure. The memory device700may include a host die710, a PCB720, and a memory group die730.

The host die710may be placed on the PCB720. The host die710may be connected to the PCB720through a flip chip bump FB. The host die710may be, for example, a SoC, CPG, or GPU.

The memory group die730may include a plurality of stacked memory dies D11to D14. The plurality of memory dies D11to D14may form an HBM structure. TSV lines (through silicon vias) may formed in the memory dies D11to D14to implement the HBM structure. The TSV lines may be electrically connected to micro bumps MCB formed between the memory dies D11to D14.

Although a buffer die or a logic die is omitted inFIG.18, the buffer die or the logic die may be placed between the memory die D11and the host die710.

FIG.19is a block diagram for explaining a mobile system to which the memory device according to some example embodiments is applied.

Referring toFIG.19, a mobile system800may include an application processor810, a connectivity820, a user interface830, a non-volatile memory device840, a volatile memory device850, and a power supply860. The volatile memory device850may include a memory cell array852and a channel interface circuit.

The application processor810may execute applications that provide Internet browsers, games, videos, and the like. The application processor810may include a memory controller812that controls the volatile memory device850.

The connectivity820may perform a wireless communication or a wired communication with an external device.

The volatile memory device850may store data processed by the application processor810or may function as a working memory. The volatile memory device850may include the memory cell array MCA852, a row fail detector854, and a flag generator856. The volatile memory device850may be implemented as the memory device described referring toFIGS.1to16. The memory controller812may monitor the fail row addresses accordingly.

The non-volatile memory device840may store a boot image for booting the mobile system800.

The user interface830may include one or more input devices such as keypads and touch screens, and/or one or more output devices such as speakers and display devices. The power supply860may supply the operating voltage of the mobile system800.

The mobile system800or the components of the mobile system800may be implemented using various forms of packages.

By way of summation and review, a reduction in a manufacturing process scale may lead to increased bit error rates and decreased yields.

As described above, embodiments may provide a memory device and a memory system in which reliability is improved.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.