Patent ID: 12199024

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments will now be described with respect to a system on chip along with an integrated fan out package. However, embodiments are not intended to be limited, and may be employed in a wide variety of embodiments.

With respect now toFIG.1, there is illustrated a first semiconductor device101and a second semiconductor device103. Each of the first semiconductor device101and the second semiconductor device103may be a semiconductor device such as a memory device, a logic device, a power device, combinations of these, or the like, that is designed to work in conjunction with other devices within the package. However, any suitable functionality may be utilized.

In an embodiment, each of the first semiconductor device101and the second semiconductor device103may comprise a first substrate105, first active devices (not separately illustrated), first metallization layers107, a first bond layer109, and first bonding metal111within the first bond layer109. The first substrate105may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

The first active devices comprise a wide variety of active devices and passive devices such as capacitors, resistors, inductors and the like that may be used to generate the desired structural and functional requirements of the design for the first semiconductor device101and the second semiconductor device103. The first active devices may be formed using any suitable methods either within or else on the first substrate105.

The first metallization layers107are formed over the first substrate105and the first active devices and are designed to connect the various active devices to form functional circuitry. In an embodiment the first metallization layers107are formed of alternating layers of dielectric and conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, etc.). In an embodiment there may be four layers of metallization separated from the first substrate105by at least one interlayer dielectric layer (ILD), but the precise number of first metallization layers107is dependent upon the design.

The first bond layer109is deposited over the first metallization layers107. The first bond layer109may be used for fusion bonding (also referred to as oxide-to-oxide bonding). In accordance with some embodiments, the first bond layer109is formed of a silicon-containing dielectric material such as silicon oxide, silicon nitride, or the like. The first bond layer109may be deposited using any suitable method, such as, CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), or the like. The first bond layer109may be planarized, for example, in a chemical mechanical polish (CMP) process.

The first bonding metal111may be formed within the first bond layer109. In an embodiment the first bonding metal111may be formed by first forming openings within the first bond layer109by first applying a photoresist over the top surface of the first bond layer109and patterning the photoresist. The photoresist is then used to etch the first bond layer109in order to form openings. The first bond layer109may be etched by dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, or the like.

Once the openings have been formed, the openings within the first bond layer109are filled with the first bonding metal111. In an embodiment the first bonding metal111may comprise a seed layer and a plate metal. The seed layer may be blanket deposited over top surfaces of the first bond layer109, and may comprise a copper layer. The seed layer may be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), or the like, depending upon the desired materials. The plate metal may be deposited over the seed layer through a plating process such as electrical or electro-less plating. The plate metal may comprise copper, a copper alloy, or the like. The plate metal may be a fill material. A barrier layer (not separately illustrated) may be blanket deposited over top surfaces of the first bond layer109before the seed layer. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like.

The first semiconductor device101and the second semiconductor device103additionally includes a plurality of through silicon vias (TSVs)113that extend through the first substrates105of the first semiconductor device101and the second semiconductor device103so as to provide a quick passage of data signals. In an embodiment the through substrate vias113may be formed by initially forming through silicon via (TSV) openings into the first substrates105. The TSV openings may be formed by applying and developing a suitable photoresist (not shown), and removing portions of the first substrates105that are exposed to the desired depth. The TSV openings may be formed so as to extend into the first substrates105at least further than the active devices formed within and/or on the first substrates105, and may extend to a depth greater than the eventual desired height of the first substrates105. Accordingly, while the depth is dependent upon the overall designs, the depth may be between about 20 μm and about 200 μm from the active devices on the substrates105, such as a depth of about 50 μm from the active devices on the substrates105.

Once the TSV openings have been formed within the first substrates105, the TSV openings may be lined with a liner. The liner may be, e.g., an oxide formed from tetraethylorthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may alternatively be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or a thermal process, may alternatively be used. Additionally, the liner may be formed to a thickness of between about 0.1 μm and about 5 μm, such as about 1 μm.

Once the liner has been formed along the sidewalls and bottom of the TSV openings, a barrier layer (also not independently illustrated) may be formed and the remainder of the TSV openings may be filled with first conductive material. The first conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may alternatively be utilized. The first conductive material may be formed by electroplating copper onto a seed layer (not shown), filling and overfilling the TSV openings. Once the TSV openings have been filled, excess liner, barrier layer, seed layer, and first conductive material outside of the TSV openings may be removed through a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

Once the TSVs113have been prepared, the first semiconductor device101and the second semiconductor device103may be singulated from each other. In an embodiment the first semiconductor device101may be singulated from the second semiconductor device103using one or more saw blades that separate the first semiconductor device101from the second semiconductor device103. However, any suitable method of singulation, including laser ablation or one or more wet etches, may also be utilized. After the singulation the first semiconductor device101may have a thickness of about 100 μm, an area of about 30 mm2, although any suitable dimensions may be utilized, and known good dies can be separated from defective dies.

FIG.2illustrates a bonding of the first semiconductor device101and the second semiconductor device103to a first wafer200. In an embodiment the first wafer200may be an application processor wafer in which semiconductor die (not separately illustrated) are formed to work in conjunction with the first semiconductor device101or the second semiconductor device103. However, any suitable functionality, such as additional memory or other functionality, may also be utilized.

The first wafer200may comprise a second substrate201and second active devices (not separately illustrated inFIG.2). In an embodiment the second substrate201and the second active devices may be similar to the first substrate105and the first active devices described above with respect toFIG.1. For example, the second substrate201may be a semiconductor substrate and the second active devices may be active and passives devices formed on or in the second substrate201. However, any suitable substrate and active devices may be utilized.

The first wafer200may also comprise a second metallization layer203, second bond layer205, and second bond metal207. In one embodiment, the second metallization layer203, the second bond layer205, and the second bond metal207may be similar to the first metallization layer107, the first bond layer109and the first bond metal111as described above with respect toFIG.1. For example, the second bond metal207may be a metal placed into the second bond layer205after the second bond layer205has been formed.

In another embodiment, the second bond metal207and the second bond layer205are formed as part of the second metallization layer203. For example, the second bond layer205may be formed as an initial dielectric layer overlying the active devices, while the second bond metal207may be formed within the second bond layer205and adjacent to the active devices, in what is known as a via0 configuration. However, any suitable arrangement for the second bond metal207and the second bond layer205may be utilized.

Once the second bond layer205and the second bond metal207have been formed, the first semiconductor device101and the second semiconductor device103may be bonded to the first wafer200. In an embodiment the first semiconductor device101and the second semiconductor device103may be bonded to the first wafer200using, e.g., a hybrid bonding process, whereby the first bond layer109is bonded to the second bond layer205and the first bond metal111is bonded to the second bond metal207. In this embodiment the top surfaces of the first wafer200, the first semiconductor device101and the second semiconductor device103may first be activated utilizing, e.g., a dry treatment, a wet treatment, a plasma treatment, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, or combinations thereof, as examples. However, any suitable activation process may be utilized.

After the activation process the first wafer200, the first semiconductor device101and the second semiconductor device103may be cleaned using, e.g., a chemical rinse, and then the first semiconductor device101and the second semiconductor device103are aligned and placed into physical contact with the first wafer200. The first wafer200, the first semiconductor device101and the second semiconductor device103are then subjected to thermal treatment and contact pressure to hybrid bond the first wafer200to the first semiconductor device101and the second semiconductor device103. For example, the first wafer200, the first semiconductor device101and the second semiconductor device103may be subjected to a pressure of about 200 kPa or less, and a temperature between about 200° C. and about 400° C. to fuse the first bond layer109and the second bond layer205. The first wafer200, the first semiconductor device101and the second semiconductor device103may then be subjected to a temperature at or above the eutectic point for material of the first bond metal111and the second bond metal207, e.g., between about 150° C. and about 650° C., to fuse the metal bond pads. In this manner, fusion of the first wafer200, the first semiconductor device101and the second semiconductor device103forms a hybrid bonded device. In some embodiments, the bonded dies are baked, annealed, pressed, or otherwise treated to strengthen or finalize the bond.

Additionally, while the above description describes the second bonding metal207as being within the second metallization layer203and the first bonding metal111being over the first metallization layer107, this is intended to be illustrative and is not intended to be limiting. Rather, any suitable combination, including the first bonding metal111being located within the first metallization layer107(e.g., within the via0 layer), may be utilized. In yet other embodiments, the first wafer200may be bonded to the first semiconductor device101and the second semiconductor device103by direct surface bonding, metal-to-metal bonding, or another bonding process. A direct surface bonding process creates an oxide-to-oxide bond or substrate-to-substrate bond through a cleaning and/or surface activation process followed by applying pressure, heat and/or other bonding process steps to the joined surfaces. In some embodiments, the first wafer200, the first semiconductor device101and the second semiconductor device103are bonded by metal-to-metal bonding that is achieved by fusing conductive elements. Any suitable bonding process may be utilized.

FIG.3illustrates a thinning of the first semiconductor device101and the second semiconductor device103in order to expose the TSVs113. In an embodiment the thinning of the first semiconductor device101and the second semiconductor device103may be performed utilizing a planarization process such as a chemical mechanical planarization process, whereby etchants and abrasives are utilized along with a grinding platen in order to react and grind away material until a planar surface is formed and the TSVs113are exposed. However, any other suitable method of exposing the TSVs113, such as a series of one or more etching processes, may also be utilized. In an embodiment the first semiconductor device101and the second semiconductor device103may be thinned to a thickness of about 20 μm, although any suitable dimensions may be utilized.

FIG.4illustrates a formation of first through interposer vias (TIVs)401onto the second bond metal207. In an embodiment the first TIVs401may be formed by initially placing and patterned a photoresist (not separately illustrated inFIG.4) over the second bond metal207(or over a separately placed seed layer if desired). In an embodiment the photoresist may be placed using, e.g., a spin coating technique. Once in place, the photoresist may then be patterned by exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern.

In an embodiment the pattern formed into the photoresist is a pattern for the first TIVs401. The first TIVs401are formed in such a placement as to be located on different sides of the first semiconductor device101and the second semiconductor device103. However, any suitable arrangement for the pattern of first TIVs401, such as by being located such that the first semiconductor device101and the second semiconductor device103are placed on opposing sides of the first TIVs401, may also be utilized.

Once the photoresist has been placed and patterned, the first TIVs401may be formed within the photoresist. In an embodiment the first TIVs401comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and may be formed, for example, by electroplating, electroless plating, or the like. In an embodiment, an electroplating process is used wherein the second bond metal207and the photoresist are submerged or immersed in an electroplating solution. The second bond metal207surface is electrically connected to the negative side of an external DC power supply such that the second bond metal207functions as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and is attached to the positive side of the power supply. The atoms from the anode are dissolved into the solution, from which the cathode, e.g., the second bond metal207, acquires the dissolved atoms, thereby plating the exposed conductive areas of the second bond metal207within the opening of the photoresist.

Once the first TIVs401have been formed using the photoresist and the second bond metal207, the photoresist may be removed using a suitable removal process. In an embodiment, a plasma ashing process may be used to remove the photoresist, whereby the temperature of the photoresist may be increased until the photoresist experiences a thermal decomposition and may be removed. However, any other suitable process, such as a wet strip, may alternatively be utilized.

In an embodiment the first TIVs401may be formed to have a thickness of about 30 μm. Additionally, the first TIVs401may be formed with a width of about 50 μm and has a pitch of about 70 μm. However, any suitable dimensions may be utilized.

In another embodiment the first TIVs401may be formed not just as a circular via, but in a wide variety of shapes. In one such embodiment the first TIVs401may be formed in a fin shape, wherein the fin shape has a length that is longer than a length of the first semiconductor device101and the second semiconductor device103. For example, the first TIVs401may have a length of between about 1 mm and about 30 mm, such as about 10 mm, and may also have a width of between about 10 μm and about 50 μm, such as about 30 μm. However, any suitable dimensions may be utilized.

FIG.5illustrates that, once the first TIVs401have been formed, the first substrates105(on both the first semiconductor device101and the second semiconductor device103) may be recessed. In an embodiment the first substrates105may be recessed using, e.g., one or more etching processes, such as a wet etching process or a dry etching process. However, any suitable method of recessing the first substrate105such that the TSVs113extend away from the first substrate105may be utilized.

Once the TSVs113extend away from the first substrate105, the first semiconductor device101, the second semiconductor device103, and the first TIVs401may be covered within a dielectric material501. In an embodiment the dielectric material501may be a dielectric such as a low temperature polyimide material, although any other suitable dielectric, such as PBO, an encapsulant, combinations of these, or the like may also be utilized.

Once the dielectric material501has been placed and cured, the first wafer200may be thinned and then singulated. In an embodiment a back side of the first wafer200may be thinned utilizing, for example, a planarization process such as a chemical mechanical planarization process. However, any suitable process for thinning the first wafer200, such as a series of one or more etches or a combination of polishing and etching, may also be utilized.

After the first wafer200has been thinned, the first wafer200may be singulated to form a first package503(e.g., a system on integrated circuit package (SoIC)) and a second package505. In an embodiment the first wafer200is singulated using one or more saw blades. However, any suitable method of singulation, including laser ablation or one or more wet etches, may also be utilized.

FIG.6illustrates a first carrier substrate601with an adhesive layer603and a polymer layer605over the adhesive layer603. In an embodiment the first carrier substrate601comprises, for example, silicon based materials, such as glass or silicon oxide, or other materials, such as aluminum oxide, combinations of any of these materials, or the like. The first carrier substrate601is planar in order to accommodate an attachment of semiconductor devices such as the first package503and the second package505(not illustrated inFIG.6but illustrated and discussed above with respect toFIG.5).

The adhesive layer603is placed on the first carrier substrate601in order to assist in the adherence of overlying structures (e.g., the polymer layer605). In an embodiment the adhesive layer603may comprise a light to heat conversion (LTHC) material or an ultra-violet glue, which loses its adhesive properties when exposed to ultra-violet light. However, other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, or the like, may also be used. The adhesive layer603may be placed onto the first carrier substrate601in a semi-liquid or gel form, which is readily deformable under pressure.

The polymer layer605is placed over the adhesive layer603and is utilized in order to provide protection to, e.g., the first package503and the second package505once the first package503and the second package505have been attached. In an embodiment the polymer layer605may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, may alternatively be utilized. The polymer layer605may be placed using, e.g., a spin-coating process to a thickness of between about 2 μm and about 15 μm, such as about 5 μm, although any suitable method and thickness may alternatively be used.

A seed layer (not separately illustrated) is formed over the polymer layer605. The seed layer is a thin layer of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. The seed layer may comprise a layer of titanium about 500 Å thick followed by a layer of copper about 3,000 Å thick. The seed layer may be created using processes such as sputtering, evaporation, or PECVD processes, depending upon the desired materials. The seed layer may be formed to have a thickness of between about 0.3 μm and about 1 μm, such as about 0.5 μm.

Once the seed layer is formed, a photoresist (also not illustrated) is placed and patterned over the seed layer. In an embodiment the photoresist may be placed on the seed layer using, e.g., a dry film lamination process or a spin coating technique to a height of between about 50 μm and about 250 μm, such as about 240 μm. Once in place, the photoresist may then be patterned by exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern.

In an embodiment the pattern formed into the photoresist is a pattern for second TIVs607. The second TIVs607are formed in such a placement as to be located on different sides of subsequently attached devices such as the first package503and the second package505. However, any suitable arrangement for the pattern of second TIVs607, such as by being located such that the first package503and the second package505are placed on opposing sides of the second TIVs607, may alternatively be utilized.

The second TIVs607are formed within the photoresist. In an embodiment the second TIVs607comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and may be formed, for example, by electroplating, electroless plating, or the like. In an embodiment, an electroplating process is used wherein the seed layer and the photoresist are submerged or immersed in an electroplating solution. The seed layer surface is electrically connected to the negative side of an external DC power supply such that the seed layer functions as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and is attached to the positive side of the power supply. The atoms from the anode are dissolved into the solution, from which the cathode, e.g., the seed layer, acquires the dissolved atoms, thereby plating the exposed conductive areas of the seed layer within the opening of the photoresist.

Once the second TIVs607have been formed using the photoresist and the seed layer, the photoresist may be removed using a suitable removal process. In an embodiment, a plasma ashing process may be used to remove the photoresist, whereby the temperature of the photoresist may be increased until the photoresist experiences a thermal decomposition and may be removed. However, any other suitable process, such as a wet strip, may alternatively be utilized. The removal of the photoresist may expose the underlying portions of the seed layer.

Once the second TIVs607have been formed, exposed portions of the seed layer are then removed. In an embodiment the exposed portions of the seed layer (e.g., those portions that are not covered by the second TIVs607) may be removed by, for example, a wet or dry etching process. For example, in a dry etching process reactants may be directed towards the seed layer, using the second TIVs607as masks. Alternatively, etchants may be sprayed or otherwise put into contact with the seed layer in order to remove the exposed portions of the seed layer. After the exposed portion of the seed layer has been etched away, a portion of the polymer layer605is exposed between the second TIVs607. The second TIVs607may be formed to a height of between about 180 μm and about 200 μm, with a critical dimension of about 190 μm and a pitch of about 300 μm.

FIG.7illustrates a placement of the first package503and the second package505onto the polymer layer605with, e.g., an adhesive701. In an embodiment the first package503and the second package505may be placed using, e.g. a pick and place process. However, any suitable method of placing the first package503and the second package505may be utilized.

FIG.8illustrates an encapsulation of the first package503and the second package505, and the second TIVs607. The encapsulation may be performed in a molding device (not individually illustrated inFIG.8), which may comprise a top molding portion and a bottom molding portion separable from the top molding portion. When the top molding portion is lowered to be adjacent to the bottom molding portion, a molding cavity may be formed for the first carrier substrate601, the second TIVs607, the first package503and the second package505.

During the encapsulation process the top molding portion may be placed adjacent to the bottom molding portion, thereby enclosing the first carrier substrate601, the second TIVs607, the first package503, and the second package505within the molding cavity. Once enclosed, the top molding portion and the bottom molding portion may form an airtight seal in order to control the influx and outflux of gasses from the molding cavity. Once sealed, an encapsulant801may be placed within the molding cavity. The encapsulant801may be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like. The encapsulant801may be placed within the molding cavity prior to the alignment of the top molding portion and the bottom molding portion, or else may be injected into the molding cavity through an injection port.

Once the encapsulant801has been placed into the molding cavity such that the encapsulant801encapsulates the first carrier substrate601, the second TIVs607, the first package503, and the second package505, the encapsulant801may be cured in order to harden the encapsulant801for optimum protection. While the exact curing process is dependent at least in part on the particular material chosen for the encapsulant801, in an embodiment in which molding compound is chosen as the encapsulant801, the curing could occur through a process such as heating the encapsulant801to between about 100° C. and about 130° C., such as about 125° C. for about 60 sec to about 3000 sec, such as about 600 sec. Additionally, initiators and/or catalysts may be included within the encapsulant801to better control the curing process.

However, as one having ordinary skill in the art will recognize, the curing process described above is merely an exemplary process and is not meant to limit the current embodiments. Other curing processes, such as irradiation or even allowing the encapsulant801to harden at ambient temperature, may alternatively be used. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

FIG.9illustrates a thinning of the encapsulant801in order to expose the second TIVs607, the first TIVs401, the first semiconductor device101, and the second semiconductor device103for further processing. The thinning may be performed, e.g., using a mechanical grinding or CMP process whereby chemical etchants and abrasives are utilized to react and grind away the encapsulant801, the first semiconductor device101and the second semiconductor device103until the second TIVs607, the first TIVs401, and the TSVs113have been exposed. As such, the second TIVs607, the first TIVs401, and the TSVs113may have a planar surface that is also coplanar with the encapsulant801. In an embodiment the thinning of the encapsulant801is continued until the encapsulant has a height of about 160 μm.

However, while the CMP process described above is presented as one illustrative embodiment, it is not intended to be limiting to the embodiments. Any other suitable removal process may alternatively be used to thin the encapsulant801, the first semiconductor device101, and the second semiconductor device103and expose the TSVs113. For example, a series of chemical etches may alternatively be utilized. This process and any other suitable process may alternatively be utilized to thin the encapsulant801, the first semiconductor device101, and the second semiconductor device103, and all such processes are fully intended to be included within the scope of the embodiments.

FIG.10illustrates a formation of a redistribution structure1000with one or more layers over the encapsulant801. In an embodiment the redistribution structure1000may be formed by initially forming a first redistribution passivation layer1001over the encapsulant801. In an embodiment the first redistribution passivation layer1001may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, such as a low temperature cured polyimide, may alternatively be utilized. The first redistribution passivation layer1001may be placed using, e.g., a spin-coating process to a thickness of between about 5 μm and about 17 μm, such as about 7 μm, although any suitable method and thickness may alternatively be used.

Once the first redistribution passivation layer1001has been formed, first redistribution vias1003may be formed through the first redistribution passivation layer1001in order to make electrical connections to the first semiconductor device101, the second semiconductor device103, the first TIVs401, and the second TIVs607. In an embodiment the first redistribution vias1003may be formed by using, e.g., a damascene process whereby the first redistribution passivation layer1001is initially patterned to form openings using, e.g., a photolithographic masking and etching process or, if the material of the first redistribution passivation layer1001is photosensitive, exposing and developing the material of the first redistribution passivation layer1001. Once patterned, the openings are filled with a conductive material such as copper and any excess material is removed using, e.g., a planarization process such as chemical mechanical polishing. However, any suitable process or materials may be utilized.

After the first redistribution vias1003have been formed, a first redistribution layer1005is formed over and in electrical connection with the first redistribution vias1003. In an embodiment the first redistribution layer1005may be formed by initially forming a seed layer (not shown) of a titanium copper alloy through a suitable formation process such as CVD or sputtering. A photoresist (also not shown) may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer that are located where the first redistribution layer1005is desired to be located.

Once the photoresist has been formed and patterned, a conductive material, such as copper, may be formed on the seed layer through a deposition process such as plating. The conductive material may be formed to have a thickness of between about 1 μm and about 10 μm, such as about 4 μm. However, while the material and methods discussed are suitable to form the conductive material, these materials are merely exemplary. Any other suitable materials, such as AlCu or Au, and any other suitable processes of formation, such as CVD or PVD, may alternatively be used to form the first redistribution layer1005.

Once the conductive material has been formed, the photoresist may be removed through a suitable removal process such as chemical stripping and/or ashing. Additionally, after the removal of the photoresist, those portions of the seed layer that were covered by the photoresist may be removed through, for example, a suitable etch process using the conductive material as a mask.

Optionally, if desired, after the first redistribution layer1005has been formed, a surface treatment of the first redistribution layer1005may be performed in order to help protect the first redistribution layer1005. In an embodiment the surface treatment may be a descum treatment such as a plasma treatment wherein the surface of the first redistribution layer1005is exposed to a plasma of, e.g., argon, nitrogen, oxygen or a mixed Ar/N2/O2ambient environment in order to improve the interface adhesion between the first redistribution layer1005and overlying layers (e.g., the second redistribution passivation layer1007). However, any suitable surface treatment may be utilized.

After the first redistribution layer1005has been formed, a second redistribution passivation layer1007may be formed and patterned to help isolate the first redistribution layer1005. In an embodiment the second redistribution passivation layer1007may be similar to the first redistribution passivation layer1001, such as by being a positive tone PBO, or may be different from the first redistribution passivation layer1001, such as by being a negative tone material such as a low-temperature cured polyimide. The second redistribution passivation layer1007may be placed to a thickness of about 7 μm. Once in place, the second redistribution passivation layer1007may be patterned to form openings using, e.g., a photolithographic masking and etching process or, if the material of the second redistribution passivation layer1007is photosensitive, exposing and developing the material of the second redistribution passivation layer1007. However, any suitable material and method of patterning maybe utilized.

After the second redistribution passivation layer1007has been patterned, a second redistribution layer1009may be formed to extend through the openings formed within the second redistribution passivation layer1007and make electrical connection with the first redistribution layer1005. In an embodiment the second redistribution layer1009may be formed using materials and processes similar to the first redistribution layer1005. For example, a seed layer may be applied and covered by a patterned photoresist, a conductive material such as copper may be applied onto the seed layer, the patterned photoresist may be removed, and the seed layer may be etched using the conductive material as a mask. In an embodiment the second redistribution layer1009is formed to a thickness of about 4 μm. However, any suitable material or process of manufacture may be used.

After the second redistribution layer1009has been formed, a third redistribution passivation layer1011is applied over the second redistribution layer1009in order to help isolate and protect the second redistribution layer1009. In an embodiment the third redistribution passivation layer1011may be formed of similar materials and in a similar fashion as the second redistribution passivation layer1007to a thickness of about 7 μm. For example, the third redistribution passivation layer1011may be formed of PBO or a low-temperature cured polyimide that has been applied and patterned as described above with respect to the second redistribution passivation layer1007. However, any suitable material or process of manufacture may be utilized.

After the third redistribution passivation layer1011has been patterned, a third redistribution layer1013may be formed to extend through the openings formed within the third redistribution passivation layer1011and make electrical connection with the second redistribution layer1009. In an embodiment the third redistribution layer1013may be formed using materials and processes similar to the first redistribution layer1005. For example, a seed layer may be applied and covered by a patterned photoresist, a conductive material such as copper may be applied onto the seed layer, the patterned photoresist may be removed, and the seed layer may be etched using the conductive material as a mask. In an embodiment the third redistribution layer1013is formed to a thickness of 5 μm. However, any suitable material or process of manufacture may be used.

After the third redistribution layer1013has been formed, a fourth redistribution passivation layer1015may be formed over the third redistribution layer1013in order to help isolate and protect the third redistribution layer1013. In an embodiment the fourth redistribution passivation layer1015may be formed of similar materials and in a similar fashion as the second redistribution passivation layer1007. For example, the fourth redistribution passivation layer1015may be formed of PBO or a low-temperature cured polyimide that has been applied and patterned as described above with respect to the second redistribution passivation layer1007. In an embodiment the fourth redistribution passivation layer1015is formed to a thickness of about 8 μm. However, any suitable material or process of manufacture may be utilized.

FIG.10additionally illustrates a formation of underbump metallizations1019and third external connectors1017to make electrical contact with the third redistribution layer1013. In an embodiment the underbump metallizations1019may each comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the underbump metallizations1019. Any suitable materials or layers of material that may be used for the underbump metallizations1019are fully intended to be included within the scope of the embodiments.

In an embodiment the underbump metallizations1019are created by forming each layer over the third redistribution layer1013and along the interior of the openings through the fourth redistribution passivation layer1015. The forming of each layer may be performed using a plating process, such as electrochemical plating, although other processes of formation, such as sputtering, evaporation, or PECVD process, may be used depending upon the desired materials. The underbump metallizations1019may be formed to have a thickness of between about 0.7 μm and about 10 μm, such as about 5 μm.

In an embodiment the third external connectors1017may be placed on the underbump metallizations1019and may be a ball grid array (BGA) which comprises a eutectic material such as solder, although any suitable materials may alternatively be used. In an embodiment in which the third external connectors1017are solder balls, the third external connectors1017may be formed using a ball drop method, such as a direct ball drop process. In another embodiment, the solder balls may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, and then performing a reflow in order to shape the material into the desired bump shape. Once the third external connectors1017have been formed, a test may be performed to ensure that the structure is suitable for further processing.

Additionally, a surface device1021may also be placed in contact with the third redistribution layer1013through the underbump metallizations1019. The surface device1021may be used to provide additional functionality or programming to the first package503, the second package505, or the package as a whole. In an embodiment the surface device1021may be a surface mount device (SMD) or an integrated passive device (IPD) that comprises passive devices such as resistors, inductors, capacitors, jumpers, combinations of these, or the like that are desired to be connected to and utilized in conjunction with the first package503or the second package505, or other parts of the package.

The surface device1021may be connected to the underbump metallizations1019, for example, by sequentially dipping connectors such as solder balls of the surface device1021into flux, and then using a pick-and-place tool in order to physically align the connectors of the surface device1021with individual ones of the underbump metallizations1019. In an embodiment in which the surface device1021uses connectors such as solder balls, once the surface device1021has been placed a reflow process may be performed in order to physically bond the surface device1021with the underlying underbump metallizations1019and a flux clean may be performed. However, any other suitable connector or connection process may be utilized, such as metal-to-metal bonding or the like. Once bonded, an underfill material may be applied.

FIG.11illustrates a debonding of the first carrier substrate601from the first package503and the second package505. In an embodiment the third external connectors1017and, hence, the structure including the first semiconductor device101and the second semiconductor device103, may be attached to a ring structure (not separately illustrated inFIG.11). The ring structure may be a metal ring intended to provide support and stability for the structure during and after the debonding process. In an embodiment the third external connectors1017are attached to the ring structure using, e.g., an ultraviolet tape (also not illustrated inFIG.11), although any other suitable adhesive or attachment may alternatively be used.

Once the third external connectors1017and, hence, the structure including the first semiconductor device101and the second semiconductor device103are attached to the ring structure, the first carrier substrate601may be debonded from the structure including the first semiconductor device101and the second semiconductor device103using, e.g., a thermal process to alter the adhesive properties of the adhesive layer603. In a particular embodiment an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser, is utilized to irradiate and heat the adhesive layer603until the adhesive layer603loses at least some of its adhesive properties. Once performed, the first carrier substrate601and the adhesive layer603may be physically separated and removed from the structure comprising the third external connectors1017, the first semiconductor device101, and the second semiconductor device103.

However, while a ring structure may be used to support the third external connectors1017, such a description is merely one method that may be used and is not intended to be limiting upon the embodiments. In another embodiment the third external connectors1017may be attached to a second carrier substrate using, e.g., a first glue. In an embodiment the second carrier substrate is similar to the first carrier substrate601, although it may also be different. Once attached, the adhesive layer603may be irradiated and the adhesive layer603and the first carrier substrate601may be physically removed.

FIGS.12A-12Billustrate a patterning of the polymer layer605in order to expose the second TIVs607. In an embodiment the polymer layer605may be patterned using, e.g., a laser drilling method. In such a method a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax layer (not separately illustrated inFIG.12A) is first deposited over the polymer layer605. Once protected, a laser is directed towards those portions of the polymer layer605which are desired to be removed in order to expose the underlying second TIVs607. During the laser drilling process the drill energy may be in a range from 0.1 mJ to about 30 mJ, and a drill angle of about 0 degree (perpendicular to the polymer layer605) to about 85 degrees to normal of the polymer layer605. In an embodiment the patterning may be formed to form openings over the second TIVs607to have a width of between about 100 μm and about 300 μm, such as about 200 μm.

In another embodiment, the polymer layer605may be patterned by initially applying a photoresist (not individually illustrated inFIG.12A) to the polymer layer605and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern, and the underlying exposed portion of the polymer layer605are removed with, e.g., a dry etch process. However, any other suitable method for patterning the polymer layer605may be utilized.

FIG.12Billustrates a top down view of the structure ofFIG.12Athrough line B-B′ inFIG.12A. As can be seen, in this embodiment the first TIVs401are in the shape of through interposer fins and are located on opposite sides of the first semiconductor device101. Additionally, the encapsulant801encapsulates both the first semiconductor device101as well as the second TIVs607.

FIG.13illustrates a bonding of a third package1301with the second TIVs607through the polymer layer605. In an embodiment the third package1301may comprise a third substrate, a third semiconductor device, a fourth semiconductor device (bonded to the third semiconductor device), a second encapsulant, and fourth external connections1303. In an embodiment the third substrate may be, e.g., a packaging substrate comprising internal interconnects (e.g., through substrate vias) to connect the third semiconductor device and the fourth semiconductor device to the second TIVs607.

In another embodiment, the third substrate may be an interposer used as an intermediate substrate to connect the third semiconductor device and the fourth semiconductor device to the second TIVs607. In this embodiment the third substrate may be, e.g., a silicon substrate, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. However, the third substrate may also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide a suitable protection and/or interconnection functionality. These and any other suitable materials may be used for the third substrate.

The third semiconductor device may be a semiconductor device designed for an intended purpose such as being a memory die (e.g., a DRAM die), a logic die, a central processing unit (CPU) die, combinations of these, or the like. In an embodiment the third semiconductor device comprises integrated circuit devices, such as transistors, capacitors, inductors, resistors, first metallization layers (not shown), and the like, therein, as desired for a particular functionality. In an embodiment the third semiconductor device is designed and manufactured to work in conjunction with or concurrently with the first semiconductor device101and the second semiconductor device103.

The fourth semiconductor device may be similar to the third semiconductor device. For example, the fourth semiconductor device may be a semiconductor device designed for an intended purpose (e.g., a DRAM die) and comprising integrated circuit devices for a desired functionality. In an embodiment the fourth semiconductor device is designed to work in conjunction with or concurrently with the first semiconductor device101, the second semiconductor device103, and/or the third semiconductor device. However, any suitable functionality may be utilized.

The fourth semiconductor device may be bonded to the third semiconductor device. In an embodiment the fourth semiconductor device is only physically bonded with the third semiconductor device, such as by using an adhesive. In this embodiment the fourth semiconductor device and the third semiconductor device may be electrically connected to the third substrate using, e.g., wire bonds, although any suitable electrical bonding may be alternatively be utilized.

Alternatively, the fourth semiconductor device may be bonded to the third semiconductor device both physically and electrically. In this embodiment the fourth semiconductor device may comprise fifth external connections (not separately illustrated inFIG.13) that connect with sixth external connections (also not separately illustrated inFIG.13) on the third semiconductor device in order to interconnect the fourth semiconductor device with the third semiconductor device.

The second encapsulant may be used to encapsulate and protect the third semiconductor device, the fourth semiconductor device, and the third substrate. In an embodiment the second encapsulant may be a molding compound and may be placed as described above with respect to the encapsulant801. For example, the third semiconductor device, the fourth semiconductor device and the third substrate may be placed into a molding device along with the second encapsulant. However, any suitable method of encapsulating the third semiconductor device, the fourth semiconductor device, and the third substrate may be utilized.

In an embodiment the fourth external connections1303may be formed to provide an external connection between the third substrate and, e.g., the second TIVs607. The fourth external connections1303may be contact bumps such as microbumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the fourth external connections1303are tin solder bumps, the fourth external connections1303may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc, to a thickness of, e.g., about 100 μm. Once a layer of tin has been formed on the structure, a reflow is performed in order to shape the material into the desired bump shape.

Once the fourth external connections1303have been formed, the fourth external connections1303are aligned with and placed over the second TIVs607, and a bonding is performed. For example, in an embodiment in which the fourth external connections1303are solder bumps, the bonding process may comprise a reflow process whereby the temperature of the fourth external connections1303is raised to a point where the fourth external connections1303will liquefy and flow, thereby bonding the third package1301to the second TIVs607once the fourth external connections1303resolidifies.

By utilizing the embodiments described herein, a low cost system-in-package (SiP) solution may be achieved with the integrated fan out process. This solution can integrate all functional chips by implementing chip-to-wafer known good dies for a chip on wafer level package. This system also provides solutions for heterogeneous, homogenous, and multi-chip stacks while still allowing for a flexible chip size integration. For example, only known good dies, splits or partition chips can be utilized to save costs, while still providing for good thermal dissipation and enhancing the signal transmission performance. Additionally, chip to wafer or wafer to wafer bonding processes can be implemented.

FIGS.14-18illustrate another embodiment in which the recessing of the first substrates105within the first semiconductor device101and the second semiconductor device103(described above with respect toFIG.5) is delayed until later during the process. With respect toFIG.14, the steps as described above with respect toFIG.1-7are the same except for the changes described herein. In a first embodiment the thinning of the first substrates105(described above with respect toFIG.3) is performed such that the first substrates105do not expose the TSVs113within the first substrates105. For example, the thinning may be performed such that the first semiconductor device101and the second semiconductor device103have a thickness of about 30 μm, although any suitable thickness may be utilized.FIG.14additionally illustrates that, once the thinning has been performed, the rest of the process may be continued and the encapsulant801may be placed around the first package503, the second package505, and the second TIVs607.

FIG.15illustrates that, once the encapsulant801has been placed, the encapsulant801is thinned in order to expose the second TIVs607and the first TIVs401while also exposing the TSVs113within the first semiconductor device101and the second semiconductor device103. The thinning may be performed, e.g., using a mechanical grinding or CMP process whereby chemical etchants and abrasives are utilized to react and grind away the encapsulant801, the first semiconductor device101and the second semiconductor device103until the second TIVs607, the first TIVs401, and the TSVs113have been exposed. As such, the second TIVs607, the first TIVs401, and the TSVs113may have a planar surface that is also coplanar with the encapsulant801.

FIG.16illustrates a recessing of the first substrates105after the thinning of the encapsulant801. In an embodiment the recessing of the first substrate105may be performed as described above with respect toFIG.5, such as by utilizing a wet or dry etching process to remove portions of the first substrate105such that the TSVs113extend away from the first substrates105. Additionally, the etchants utilized for the recessing may be selective to the material of the first substrate105such that a minimal amount or none of the surrounding materials, such as the dielectric material501, is removed. As such, a recess is formed within the dielectric material501to a depth of between about 0.5 μm and about 5 μm, such as about 2 μm, wherein the TSVs113extend into the recess within the dielectric material501.

FIG.17illustrates a placement of a second dielectric material1701within the recess and over the TSVs113. In an embodiment the second dielectric material1701may be similar to the dielectric material501, such as by being a low temperature cured polyimide material, although any suitable material may be utilized. Once the second dielectric material1701has been placed using, e.g., a spin coating process, the second dielectric material1701, similar to the dielectric material501, may be cured.

FIG.17additionally illustrates that, once the second dielectric material1701has been placed and cured, the second dielectric material1701is planarized in order to expose the TSVs113. In an embodiment the second dielectric material1701is planarized using a chemical mechanical polishing process, although any suitable planarization process may be utilized. By planarizing the second dielectric material1701, the second dielectric material1701is coplanar with the TSVs113, the encapsulant801, the first TIVs401, and the second TIVs607.

FIG.18illustrates that, once the second dielectric material1701is planarized and the first TIVs401exposed, the remainder of the steps as described above with respect toFIGS.10-14may be performed. For example, the redistribution structure1000may be formed, the fourth external connections1303are placed, and the third package1301may be bonded. However, any suitable steps may be performed.

FIGS.19-22illustrate another embodiment in which the recessing of the first substrates105are delayed until after the encapsulation. In this embodiment, however, the application of the dielectric material501is also not performed prior to the application of the encapsulant801. Looking first atFIG.19, the steps as described above with respect toFIG.14-18are the same, except the dielectric material501is not applied by this point in the process. As such, when the first package503and the second package505are placed onto the polymer layer605, the first TIVs401remain exposed and the TSVs113are not exposed. Additionally, when the encapsulant801is applied (as described above with respect toFIG.8), the encapsulant801will be in physical contact with both the first TIVs401and the second TIVs607. In particular, as the encapsulant801is placed into the molding chamber, the encapsulant801will flow between the second TIVs607, the first semiconductor device101and the second semiconductor device103.

FIG.20illustrates a thinning of the encapsulant801in order to expose the second TIVs607and the first TIVs401while also exposing the TSVs113within the first semiconductor device101and the second semiconductor device103. The thinning may be performed, e.g., using a mechanical grinding or CMP process whereby chemical etchants and abrasives are utilized to react and grind away the encapsulant801, the first semiconductor device101and the second semiconductor device103until the second TIVs607, the first TIVs401, and the TSVs113have been exposed. As such, the second TIVs607, the first TIVs401, and the TSVs113may have a planar surface that is also coplanar with the encapsulant801.

FIG.21illustrates a recessing of the first substrates105. In an embodiment the recessing of the first substrate105may be performed as described above with respect toFIG.5, such as by utilizing a wet or dry etching process to remove portions of the first substrate105such that the TSVs113extend away from the first substrates105. Additionally, the etchants utilized for the recessing may be selective to the material of the first substrate105such that a minimal amount or none of the surrounding materials, such as the encapsulant801, is removed. As such, a recess is formed within the encapsulant801, wherein the TSVs113extend into the recess within the encapsulant801.

FIG.22illustrates a placement of the second dielectric material1701within the recess and over the TSVs113. In an embodiment the second dielectric material1701may be similar to the dielectric material501, such as by being a low temperature cured polyimide material, although any suitable material may be utilized. Once the second dielectric material1701has been placed using, e.g., a spin coating process, the second dielectric material1701, similar to the dielectric material501, may be cured.

FIG.22additionally illustrates that, once the second dielectric material1701has been placed and cured, the second dielectric material1701is planarized in order to expose the TSVs113. In an embodiment the second dielectric material1701is planarized using a chemical mechanical polishing process, although any suitable planarization process may be utilized. By planarizing the second dielectric material1701, the second dielectric material1701is coplanar with the TSVs113, the encapsulant801, the first TIVs401, and the second TIVs607.

FIG.23illustrates that, once the second dielectric material1701is planarized and the first TIVs401exposed, the remainder of the steps as described above with respect toFIGS.10-14may be performed. For example, the redistribution structure1000may be formed, the fourth external connections1303are placed, and the third package1301may be bonded. However, any suitable steps may be performed.

FIGS.24-32illustrate another embodiment in which the first TIVs401and the second TIVs607(not illustrated inFIG.24) are formed simultaneously with each other. In this embodiment, and looking atFIG.24first, the first semiconductor device101and the second semiconductor device103are bonded to the second bond layer205and the second bond metal207as described above with respect toFIG.2. For example, the first semiconductor device101and the second semiconductor device103may be bonded using, for example, a hybrid bonding process. However, any suitable bonding process may be utilized.

FIG.24additionally illustrates a thinning of the first semiconductor device101and the second semiconductor device103. In an embodiment the first semiconductor device101and the second semiconductor device103may be thinned using a planarization process, such as a chemical mechanical polishing (CMP) process, although any suitable process may be utilized. However, in this embodiment the through substrate vias113are not exposed by the planarization process and the through substrate vias113remain covered by the semiconductor material.

FIG.25illustrates that, once the first semiconductor device101and the second semiconductor device have been thinned, the first wafer200may be thinned and then singulated. In an embodiment a back side of the first wafer200may be thinned utilizing, for example, a planarization process such as a chemical mechanical planarization process. However, any suitable process for thinning the first wafer200, such as a series of one or more etches or a combination of polishing and etching, may also be utilized.

After the first wafer200has been thinned, the first wafer200may be singulated to form the first package503(e.g., the system on integrated circuit package (SoIC)) and the second package505. In an embodiment the first wafer200is singulated using one or more saw blades. However, any suitable method of singulation, including laser ablation or one or more wet etches, may also be utilized.

FIG.25additionally illustrates that, at this point in the process of this embodiment, the first TIVs401have not yet been formed. Rather, certain ones of the second bond metal207(those that are not bonded to the first semiconductor device101and the second semiconductor device103) are left exposed during the singulation process. As such, the singulation process occurs without the presence of the first TIVs401.

FIG.26illustrates a placement of the first package503and the second package505onto the polymer layer605with, e.g., the adhesive701. In an embodiment the first package503and the second package505may be placed using, e.g. a pick and place process. However, any suitable method of placing the first package503and the second package505may be utilized.

FIG.26additionally illustrates that, at this point in the process of this embodiment, the first TIVs401still have yet to be formed. As such, the placement of the first package503and the second package505is also performed prior to the formation of the second TIVs607. Accordingly, the placement of the photoresist and the plating process that are described above as being utilized to form the second TIVs607are delayed until a later point in the process (described further below).

FIG.27illustrates a simultaneous formation of both the first TIVs401and the second TIVs607. In an embodiment, to initiate the formation of both the first TIVs401and the second TIVs607, a seed layer (not separately illustrated) is formed over the polymer layer605, the first package503, and the second package505. The seed layer is a thin layer of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. The seed layer may comprise a layer of titanium about 500 Å thick followed by a layer of copper about 3,000 Å thick. The seed layer may be created using processes such as sputtering, evaporation, or PECVD processes, depending upon the desired materials. The seed layer may be formed to have a thickness of between about 0.3 μm and about 1 μm, such as about 0.5 μm.

Once the seed layer is formed, a photoresist (also not illustrated) is placed and patterned over the seed layer. In an embodiment the photoresist may be placed on the seed layer using, e.g., a dry film lamination process or a spin coating technique to a height of between about 50 μm and about 250 μm, such as about 240 μm. Once in place, the photoresist may then be patterned by exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern.

In an embodiment the pattern formed into the photoresist is a pattern for the first TIVs401and the second TIVs607. The first TIVs401and the second TIVs607are formed in such a placement as to be located on different sides of the first package503and the second package505as well as on the first package503and the second package505. However, any suitable arrangement for the pattern of the first TIVs401and the second TIVs607may also be utilized.

The first TIVs401and the second TIVs607are formed within the photoresist. In an embodiment the first TIVs401and the second TIVs607comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and may be formed, for example, by electroplating, electroless plating, or the like. In an embodiment, an electroplating process is used wherein the seed layer and the photoresist are submerged or immersed in an electroplating solution. The seed layer surface is electrically connected to the negative side of an external DC power supply such that the seed layer functions as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and is attached to the positive side of the power supply. The atoms from the anode are dissolved into the solution, from which the cathode, e.g., the seed layer, acquires the dissolved atoms, thereby plating the exposed conductive areas of the seed layer within the opening of the photoresist.

Once the first TIVs401and the second TIVs607have been formed using the photoresist and the seed layer, the photoresist may be removed using a suitable removal process. In an embodiment, a plasma ashing process may be used to remove the photoresist, whereby the temperature of the photoresist may be increased until the photoresist experiences a thermal decomposition and may be removed. However, any other suitable process, such as a wet strip, may alternatively be utilized. The removal of the photoresist may expose the underlying portions of the seed layer.

Once the first TIVs401and the second TIVs607have been formed, exposed portions of the seed layer are then removed. In an embodiment the exposed portions of the seed layer (e.g., those portions that are not covered by the first TIVs401and the second TIVs607) may be removed by, for example, a wet or dry etching process. For example, in a dry etching process reactants may be directed towards the seed layer, using the first TIVs401and the second TIVs607as masks. In another embodiment, etchants may be sprayed or otherwise put into contact with the seed layer in order to remove the exposed portions of the seed layer. Any suitable method of removing the seed layer may be utilized.

FIG.28illustrates an encapsulation of the first TIVs401and the second TIVs607along with the first package503and the second package505. In an embodiment the encapsulant may be applied as described above with respect toFIG.8. However, in this embodiment the encapsulant801will be in physical contact with both the first TIVs401and the second TIVs607. In particular, as the encapsulant801is placed into the molding chamber, the encapsulant801will flow between the second TIVs607, the first semiconductor device101and the second semiconductor device103.

FIG.29illustrates a thinning of the encapsulant801in order to expose the second TIVs607and the first TIVs401while also exposing the TSVs113within the first semiconductor device101and the second semiconductor device103. The thinning may be performed, e.g., using a mechanical grinding or CMP process whereby chemical etchants and abrasives are utilized to react and grind away the encapsulant801, the first semiconductor device101and the second semiconductor device103until the second TIVs607, the first TIVs401, and the TSVs113have been exposed. As such, the second TIVs607, the first TIVs401, and the TSVs113may have a planar surface that is also coplanar with the encapsulant801.

FIG.30illustrates a recessing of the first substrates105. In an embodiment the recessing of the first substrate105may be performed as described above with respect toFIG.5, such as by utilizing a wet or dry etching process to remove portions of the first substrate105such that the TSVs113extend away from the first substrates105. Additionally, the etchants utilized for the recessing may be selective to the material of the first substrate105such that a minimal amount or none of the surrounding materials, such as the encapsulant801, is removed. As such, a recess is formed within the encapsulant801, wherein the TSVs113extend into the recess within the encapsulant801.

FIG.31illustrates a placement of the second dielectric material1701within the recess and over the TSVs113. In an embodiment the second dielectric material1701may be similar to the dielectric material501, such as by being a low temperature cured polyimide material, although any suitable material may be utilized. Once the second dielectric material1701has been placed using, e.g., a spin coating process, the second dielectric material1701, similar to the dielectric material501, may be cured.

FIG.31additionally illustrates that, once the second dielectric material1701has been placed and cured, the second dielectric material1701is planarized in order to expose the TSVs113. In an embodiment the second dielectric material1701is planarized using a chemical mechanical polishing process, although any suitable planarization process may be utilized. By planarizing the second dielectric material1701, the second dielectric material1701is coplanar with the TSVs113, the encapsulant801, the first TIVs401, and the second TIVs607.

FIG.32illustrates that, once the second dielectric material1701is planarized and the first TIVs401exposed, the remainder of the steps as described above with respect toFIGS.10-14may be performed. For example, the redistribution structure1000may be formed, the fourth external connections1303are placed, and the third package1301may be bonded. However, any suitable steps may be performed.

In accordance with an embodiment, a method of manufacturing a semiconductor device includes attaching a first semiconductor device and a second semiconductor device to a first wafer; forming first through interposer vias adjacent to the first semiconductor device and the second semiconductor device; exposing through substrate vias by removing a portion of the first semiconductor device and the second semiconductor device; applying a dielectric material around the first through interposer vias; singulating the first wafer to form a first package and a second package; attaching the first package and the second package to a carrier wafer, wherein second through interposer vias are located on the carrier wafer; encapsulating the first package, the second package, and the second through interposer vias with an encapsulant; thinning the encapsulant to expose the through substrate vias; and forming a redistribution structure over the encapsulant. In an embodiment, the attaching the first semiconductor device and the second semiconductor device forms a hybrid bond. In an embodiment, the method further includes thinning the first semiconductor device after the attaching the first semiconductor device and prior to the forming the first through interposer vias. In an embodiment, the exposing the through substrate vias is performed prior to the applying the dielectric material. In an embodiment, the exposing the through substrate vias is performed after the applying the dielectric material. In an embodiment, the method further includes applying a second dielectric material around the through substrate vias after the exposing the through substrate vias. In an embodiment the method further includes planarizing the second dielectric material to be coplanar with the dielectric material.

In accordance with another embodiment, a method of manufacturing a semiconductor device includes attaching a first die and a second die to a first wafer, the first die comprising first through substrate vias; thinning the first die and the second die without exposing the first through substrate vias; forming first through interposer vias on the first wafer after the thinning the first die and the second die; applying a dielectric material around the first die, the second die, and the first through interposer vias; singulating the first wafer to form a first package and a second package; encapsulating the first package, the second package, and second through interposer vias with an encapsulant; thinning the encapsulant to expose the first through substrate vias; recessing a portion of the first die and a portion of the second die after the thinning the encapsulant; applying a second dielectric material into the recess; and forming a redistribution structure over the second dielectric material. In an embodiment, the first package and the second package are attached to a polymer layer prior to the encapsulating the first package, the second package, and the second through interposer vias. In an embodiment, the method further includes forming an opening through the polymer layer. In an embodiment, the method further includes attaching a third package to the second through interposer vias through the opening in the polymer layer. In an embodiment, the attaching the first die and the second die is performed at least in part through a hybrid bonding process. In an embodiment, the attaching the first die is performed by bonding a first bond metal of the first die to a second bond metal of the first wafer, the first bond metal being within a first metallization layer. In an embodiment, the method further includes planarizing the second dielectric material at least until the second dielectric material is coplanar with the dielectric material.

In accordance with yet another embodiment, a method of manufacturing a semiconductor device includes thinning a first die and a second die without exposing first through substrate vias within the first die, wherein the first die is hybrid bonded to a first wafer prior to the thinning the first die; plating first through interposer vias onto the first wafer after the thinning the first die and the second die; forming a first package from the first die and the first wafer; forming a second package from the second die and the first wafer; plating second through interposer vias onto a carrier wafer; encapsulating the first package, the second package, and the second through interposer vias with an encapsulant, wherein the encapsulant is in physical contact with the first through interposer vias; planarizing the encapsulant to expose the first through substrate vias; exposing sidewalls of the first through substrate vias by removing a portion of the first die after the planarizing the encapsulant; and replacing the portion of the first die with a dielectric material. In an embodiment the method further includes planarizing the dielectric material until the dielectric material is coplanar with the encapsulant. In an embodiment the method further includes forming a redistribution structure over the dielectric material: and attaching a surface device to the redistribution structure. In an embodiment the method further includes attaching the first package and the second package to a polymer layer on the carrier wafer prior to the encapsulating the first package, the second package, and the second through interposer vias. In an embodiment the method further includes attaching a third package to the second through interposer vias through the polymer layer. In an embodiment the method further includes bonding a first bond metal of the first die to a second bond metal of the first wafer and bonding a first dielectric layer of the first die to a second dielectric layer of the first wafer, the first bond metal being within a first metallization layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.