Patent ID: 12198607

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the invention will be described hereinafter with reference to the accompanying drawings.

Although the invention may be modified in various manners and have additional embodiments, embodiments are illustrated in the accompanying drawings and will be mainly described in the specification. However, the scope of the invention is not limited to the embodiments in the accompanying drawings and the specification and should be construed as including all the changes, equivalents and substitutions included in the spirit and scope of the invention. Some of the parts which are not associated with the description may not be provided in order to describe embodiments of the invention and like reference numerals refer to like elements throughout the specification.

In the drawings, sizes and thicknesses of elements shown in the accompanying drawings may be enlarged for clarity and ease of description thereof. However, the invention is not limited to the illustrated sizes and thicknesses. In the drawings, the thicknesses of layers, films, panels, regions, and other elements, may be exaggerated for clarity. In the drawings, for better understanding and ease of description, the thicknesses of some layers and areas may be exaggerated.

Further, in the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a cross-sectional view” means when a cross-section taken by vertically cutting an object portion is viewed from the side.

When a layer, film, region, substrate, or area, is referred to as being “on” another layer, film, region, substrate, or area, it may be directly on the other layer, film, region, substrate, or area, or intervening layers, films, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, is referred to as being “directly on” another layer, film, region, substrate, or area, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further when a layer, film, region, substrate, or area, is referred to as being “below” another layer, film, region, substrate, or area, it may be directly below the other layer, film, region, substrate, or area, or intervening layers, films, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, is referred to as being “directly below” another layer, film, region, substrate, or area, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further, “over” or “on” may include positioning on or below an object and does not necessarily imply a direction based upon gravity.

The spatially relative terms “below”, “beneath”, “lower”, “above”, “upper”, or the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device illustrated in the drawing is turned over, the device positioned “below” or “beneath” another device may be placed “above” another device. Accordingly, the illustrative term “below” may include both the lower and upper positions. The device may also be oriented in other directions and thus the spatially relative terms may be interpreted differently depending on the orientations.

Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to another element, or “electrically connected” to another element with one or more intervening elements interposed therebetween. It will be further understood that when the terms “comprises,” “comprising,” “includes” and/or “including” are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or any combination thereof.

It will be understood that, although the terms “first,” “second,” “third,” or the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element or for the convenience of description and explanation thereof. For example, when “a first element” is discussed in the description, it may be termed “a second element” or “a third element,” and “a second element” and “a third element” may be termed in a similar manner without departing from the teachings herein.

“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 5% of the stated value.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this invention pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or excessively formal sense unless clearly defined in the specification. In the drawings, a reference character x used for indicating a direction is a first direction, y is a second direction perpendicular to the first direction, and z is a third direction perpendicular to the first direction and the second direction. The first direction x, the second direction y, and the third direction z may correspond to a horizontal direction, a vertical direction, and a thickness direction of the display device, respectively. It is to be noted that these first, second, and third directions may be substantially, horizontal, vertical and thickness directions.

Hereinafter, a display device (a light emitting display device as an example) according to embodiments will be described with reference to the drawings.

FIG.1illustrates a layout view of a display device1according to an embodiment.

The display device1may include a display panel10, a flexible printed circuit film20, a printed circuit board (PCB)40, and the like.

The display panel10may include a display area DA corresponding to a screen on which an image is displayed and a non-display area NA, and wires and/or circuits for generating and/or transferring various signals and voltages applied to the display area DA may be disposed in the non-display area NA. The non-display area NA may surround the display area DA.

Pixels PX may be disposed in, for example, a matrix form in the display area DA of the display panel10. A data line171for transferring a data signal, a driving voltage line172for transferring a driving voltage ELVDD, a common voltage line170for transferring a common voltage ELVSS, and an initialization voltage line173and a horizontal initialization voltage line153for transferring an initialization voltage may be disposed. Each pixel PX may receive the data signal, the driving voltage ELVDD, the common voltage ELVSS, and an initialization voltage from such respective wires. Herein, the driving voltage ELVDD and the common voltage ELVSS are power voltages applied to the respective pixels PX, and the driving voltage line172and the common voltage line170for transmitting the voltages are referred to as power voltage lines. The driving voltage ELVDD may be a voltage having a higher potential than the common voltage ELVSS.

A gate driver (not illustrated) may be disposed on opposite sides of the display area DA in the non-display area NA of the display panel10. The pixels PX may receive a scan signal generated by the gate driver and receive a data signal at a predetermined timing.

A driving voltage transfer line DVL connected to the driving voltage line172and a common voltage transfer line CVL connected to the common voltage line170may be disposed in the non-display area NA of the display panel10. Each of the driving voltage transfer line DVL and the common voltage transfer line CVL may include a portion extending in a substantially second direction y and a portion extending in a substantially first direction x.

As used herein, the term “portion” may include a part of a whole or part of an area of an element, a section or piece of an element, or a predetermined amount of an element, or any other definition as would be understood and appreciated by those of ordinary skill in the art.

The flexible printed circuit film20may have a first end bonded to the display panel10and a second end bonded to the printed circuit board40. A data driver30for applying a data voltage to the data line171may be disposed in the flexible printed circuit film20, and may be provided as an integrated circuit chip.

A power module50that generates a power voltage such as the driving voltage ELVDD or the common voltage ELVSS may be disposed in the printed circuit board40. The power module50may be provided as an integrated circuit chip. A signal controller for controlling the data driver30and the gate driver may be disposed in the printed circuit board40.

A configuration of the display device according to an embodiment has been described so far. The display device according to an embodiment will now be described in more detail.

FIG.2illustrates a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment.

Referring toFIG.2, one pixel PX may include transistors T1, T2, and T3, a capacitor Cst, and a light emitting diode ED.

The transistors T1, T2, and T3may include a first transistor T1, a second transistor T2, and a third transistor T3. A source electrode and a drain electrode, which will be described later, are used to distinguish two electrodes disposed on opposite sides of a channel of each of the transistors T1, T2, and T3, and they may be interchanged.

The first transistor T1may include a gate electrode G1, a source electrode S1, and a drain electrode D1. The gate electrode G1may be connected to a first electrode C1of the capacitor Cst, the source electrode S1may be connected to the driving voltage line for receiving the driving voltage ELVDD, and the drain electrode D1may be connected to an anode of the light emitting diode ED and a second electrode C2of the capacitor Cst. The first transistor T1may receive a data voltage DAT depending on a switching operation of the second transistor T2, may store the data voltage DAT in the capacitor Cst, and may supply a driving current to the light emitting diode ED depending on the stored voltage.

The second transistor T2may include a gate electrode G2, a source electrode S2, and a drain electrode D2. The gate electrode G2may be connected to a first scan line for transferring a first scan signal SC, the source electrode S2may be connected to a data line capable of transmitting the data voltage DAT or a reference voltage, and the drain electrode D2may be connected to the first electrode C1of the capacitor Cst and the gate electrode G1. The second transistor T2may be turned on depending on the first scan signal SC to transfer the reference voltage or the data voltage DAT to the gate electrode G1and the first electrode C1of the capacitor Cst.

The third transistor T3may include a gate electrode G3, a source electrode S3, and a drain electrode D3. The gate electrode G3may be connected to a second scan line for transferring a second scan signal SS, the source electrode S3may be connected to the second electrode C2of the capacitor Cst, the drain electrode D1, and the anode, and the drain electrode D3may be connected to an initialization voltage line carrying an initialization voltage INIT. The third transistor T3may be turned on in response to the second scan signal SS to initialize an anode voltage by transferring the initialization voltage INIT to the anode and the second electrode C2of the capacitor Cst.

The first electrode C1of the capacitor Cst may be connected to the gate electrode G1of the first transistor T1, and the second electrode C2of the capacitor Cst may be connected to the source electrode S3and the anode. A cathode of the light emitting diode ED may be connected to a common voltage line for transferring the common voltage ELVSS.

The light emitting diode ED may emit light having luminance (gray) depending on a driving current generated by the first transistor T1.

An example of an operation of a circuit illustrated inFIG.2, for operation during one frame, for example, will be described where the transistors T1, T2, and T3are all N-type channel transistors as an example.

When one frame is started, the first scan signal SC of a high level and the second scan signal SS of a high level are supplied in the initialization period, and the second transistor T2and the third transistor T3are turned on. A reference voltage from the data line is supplied to the gate electrode G1and the first electrode C1of the capacitor Cst through the turned-on second transistor T2, and the initialization voltage INIT is supplied to the drain electrode D1and the anode through the turned-on third transistor T3. During the initialization period, the drain electrode D1and the anode are initialized to the initialization voltage INIT. A voltage difference between the reference voltage and the initialization voltage INIT is stored in the capacitor Cst.

When the second scan signal SS is changed to a low level in a state where the first scan signal SC of a high level is maintained for a sensing period, the second transistor T2maintains a turn-on state and the third transistor T3is turned off. The gate electrode G1and the first electrode C1of the capacitor Cst maintain the reference voltage through the turned-on second transistor T2, while the drain electrode D1and the anode are disconnected from the initialization voltage INIT through the turned-off third transistor T3. The first transistor T1is turned off when the voltage of the gate electrode G1becomes “reference voltage—Vth” while a current flows from the source electrode S1to the drain electrode D1. Vthindicates a threshold voltage of the first transistor T1. A voltage difference between the gate electrode G1and the drain electrode D1is stored in the capacitor Cst, and sensing of the threshold voltage Vthof the first transistor T1is completed. A characteristic deviation of the first transistor T1which may be different for each pixel PX may be compensated by generating a data signal that is compensated by reflecting characteristic information sensed for the sensing period.

The second transistor T2is turned on and the third transistor T3is turned off when the first scan signal SC of the high level and a second scan signal SS of a low level are supplied for a data input period. The data voltage DAT from the data line is supplied to the gate electrode G1and the first electrode C1of the capacitor Cst through the turned-on second transistor T2. The drain electrode D1and anode may maintain almost the same potential of the sensing period by the first transistor T1which is in the turned-off state. The first transistor T1which is turned on by the data voltage DAT transferred to the gate electrode G1for a light emitting period generates a driving current depending on the data voltage DAT, and the driving current may allow the light emitting diode ED to emit light.

Hereinafter, a detailed structure of a display device according to an embodiment will be described with reference toFIG.3toFIG.6.

FIG.3illustrates a layout view of a pixel area of a display device according to an embodiment,FIG.4is a schematic cross-sectional view taken along line A-A′ ofFIG.3according to an embodiment,FIG.5illustrates a schematic cross-sectional view taken along line B-B′ ofFIG.3according to an embodiment, andFIG.6illustrates a schematic cross-sectional view taken along line C-C′ ofFIG.3according to an embodiment.FIG.3illustrates a planar structure of three neighboring pixels PX1, PX2, and PX3. Each of the pixels PX1, PX2, and PX3may include corresponding constituent elements, and thus a reference numeral of a constituent element of one of the pixels PX1, PX2, and PX3may be similarly applied to the corresponding constituent elements of the remaining pixels.

The display device according to the embodiment includes a substrate110. The substrate110may be made of an insulating material such as glass or plastic or other suitable insulating material.

A first conductive layer including a lower pattern111may be disposed on the substrate110. The lower pattern may also be referred to as a conductive pattern. The first conductive layer may include a conductive material such as a metal or a metal alloy. A thickness of the lower pattern111may be in a range of about several hundred angstroms to about several thousand angstroms.

A buffer layer120, which may be an insulating layer, may be disposed on the first conductive layer. As described later on, the buffer layer120may be comprised of a first layer120aand a second layer120b. The first layer120aand/or the second layer120bmay include an organic insulating material or an inorganic insulating material.

An active layer including active patterns130a,130b, and130cmay be disposed on the buffer layer120. The first conductive layer may be disposed between the substrate110and the active layer. The active patterns130a,130b, and130cdisposed at each of the pixels PX1, PX2, and PX3may include channel regions134a,134b, and134cthat form respective channels of the transistors T1, T2, and T3, and conductive regions connected to the channel regions134a,134b, and134c. The conductive regions of the active patterns130a,130b, and130cmay respectively include source regions133a,133b, and133cand drain regions135a,135b, and135cof the transistors T1, T2, and T3.

In each of the pixels PX1, PX2, and PX3, the active pattern130aand the active pattern130cmay be connected to or separated from each other.FIG.3illustrates an example in which the active pattern130aand the active pattern130care connected to each other. The drain region135aof the active pattern130amay be the source region133cof the active pattern130c.

The active layer may include a semiconductor material such as an oxide semiconductor, polysilicon, and amorphous silicon, for example. A thickness of the active layer may be less than the thickness of the lower pattern111, and may be about several hundred angstroms.

Insulating patterns144and145, which are first insulating layers, may be disposed on the active layer. The insulating pattern144may overlap the channel regions134a,134b, and134cof the active patterns130a,130b, and130c, and may be disposed on the channel regions134a,134b, and134c. The insulating pattern144may not substantially overlap the conductive regions of the active patterns130a,130b, and130c. The insulating pattern145may overlap auxiliary wires ALa, ALb, and ALc.

The term “overlap” may include layer, stack, face or facing, extending over, covering or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. When an element is described as ‘not overlapping’ or ‘to not overlap’ another element, this may include that the elements are spaced apart from each other, offset from each other, or set aside from each other or any other suitable term as would be appreciated and understood by those of ordinary skill in the art.

A second conductive layer may be disposed on the first insulating layer. The second conductive layer may include a first scan line151capable of transferring the first scan signal SC described above, a second scan line152capable of transferring the second scan signal SS, a horizontal initialization voltage line153capable of transferring the initialization voltage INIT, a horizontal driving voltage line172hcapable of transferring the driving voltage ELVDD, a driving gate electrode155, a second gate electrode154b, a third gate electrode154c, and auxiliary wires ALa, ALb, and ALc. InFIG.3, shaded areas correspond to regions where the auxiliary wires ALa, ALb, and ALc may be formed. The constituent elements included in the second conductive layer may be formed in a same layer by using a same process. Thus, manufacturing costs may be reduced. The gate electrode G1, the gate electrode G2, and the gate electrode G3in the circuit diagram ofFIG.2may correspond to a first gate electrode154aincluded in the driving gate electrode155, the second gate electrode154b, and the third gate electrode154c.

Each of the first scan line151, the second scan line152, the horizontal initialization voltage line153, and the horizontal driving voltage line172hmay extend in a substantially first direction x.

The driving gate electrode155may be disposed between the first scan line151and the second scan line152.

The second gate electrode154bmay be spaced apart from the first scan line151, and may extend substantially in a second direction y. The second gate electrode154bmay be directly connected to the first scan line151.

The third gate electrode154cmay be spaced apart from the second scan line152, and may extend substantially in the second direction y. The third gate electrode154cmay be directly connected to the second scan line152.

The driving gate electrode155disposed in each of the pixels PX1, PX2, and PX3may include a protrusion155athat protrudes upward, and the first gate electrode154athat protrudes downward and substantially extends in the second direction y.

The first gate electrode154acrosses the active pattern130a, and overlaps the channel region134aof the active pattern130a. The second gate electrode154bcrosses the active pattern130b, and overlaps the channel region134bof the active pattern130b. The third gate electrode154ccrosses the active pattern130c, and overlaps the channel region134cof the active pattern130c.

The auxiliary wires ALa, ALb, and ALc may be disposed at regions at which constituent elements other than the auxiliary wires ALa, ALb, and ALc, that is, the first scan line151, the second scan line152, the horizontal initialization voltage line153, the horizontal driving voltage line172h, the driving gate electrode155, the second gate electrode154b, and the third gate electrode154c, in the second conductive layer, are not formed. The auxiliary wires ALa, ALb, and ALc may be electrically connected to the power voltage lines such as driving voltage lines172a,172b, and172cand the common voltage line170, thereby reducing resistance of the power voltage lines.

Each of the auxiliary wires ALa, ALb, and ALc may extend substantially in the second direction y. Each of the auxiliary wires ALa, ALb, and ALc may include a portion overlapping pixel electrodes191a,191b, and191cin the pixels PX1, PX2, and PX3. Each of the auxiliary wires ALa, ALb, and ALc may include a portion overlapping the driving voltage lines172a,172band172c, the common voltage line170, and/or data lines171a,171band171c. In the embodiment illustrated therein, the auxiliary wire ALa overlaps the driving voltage line172aand the common voltage line170, the auxiliary wire ALb overlaps the driving voltage line172band the data line171a, and the auxiliary wire ALc overlaps the driving voltage line172cand the data line171b. The auxiliary wires ALa, ALb, and ALc may not overlap the active patterns130a,130b, and130c.

A second insulating layer160may be disposed on the second conductive layer. The second insulating layer160may cover the transistors T1, T2, and T3. The buffer layer120and/or the second insulating layer160may include contact holes24,26,60,61,62,63,64,65,66,67,68,69, and60′. As will be described later on, the second insulating layer160may be formed of multiple layers including at least a first layer160aand a second layer160b, and the first layer160aand/or the second layer160bmay include an organic insulating material or an inorganic insulating material.

A third conductive layer may be disposed on the second insulating layer160. The third conductive layer may include the data lines171a,171b, and171c, the driving voltage lines172a,172b, and172c, the common voltage line170, the initialization voltage line173, a capacitor electrode175, and connecting members174,176,177, and178.

Each of the data lines171a,171b, and171c, the driving voltage lines172a,172b, and172c, the common voltage line170, and the initialization voltage line173may extend substantially in the second direction y, and may cross the first scan line151and the second scan line152.

A group of pixels PX1, PX2, and PX3illustrated inFIG.3may be arranged in the first direction x to be substantially adjacent to each other, and may be repeatedly arranged in the first direction x and the second direction y. The common voltage line170may be disposed at left and right sides of the pixels PX1, PX2, and PX3of one group, for example. When three pixels PX1, PX2, and PX3are repeatedly contained in one group, the three data lines171a,171b, and171c, the three driving voltage lines172a,172b, and172c, and at least one initialization voltage line173may be disposed between two common voltage lines170that may be substantially adjacent in the first direction x.

Each of the data lines171a,171b, and171cmay be connected to the source region133bof the active pattern130bthrough the contact hole64of the second insulating layer160.

The driving voltage lines172a,172b, and172cmay be respectively disposed in the pixels PX1, PX2, and PX3. Each of the driving voltage lines172a,172b, and172cmay extend substantially in the second direction y.

The driving voltage lines172a,172b, and172cmay be connected to the source region133aof the active pattern130athrough the contact hole61of the second insulating layer160. The driving voltage lines172a,172b, and172cmay be connected to the horizontal driving voltage line172hthrough the contact hole60of the second insulating layer160. The horizontal driving voltage line172hmay transfer the driving voltage together with the driving voltage lines172a,172b, and172c. The horizontal driving voltage line172hand the driving voltage lines172a,172b, and172cmay be connected in a mesh form throughout the display device.

The driving voltage lines172a,172b, and172cmay be connected to respective auxiliary wires ALa, ALb, and ALc through contact holes60′ of the second insulating layer160. In other words, each of the driving voltage lines172a,172b, and172cmay be connected to a corresponding one of the auxiliary wires ALa, ALb, and ALc through a corresponding one of the contact holes60′ of the second insulating layer160. For example,FIG.5illustrates the driving voltage line172aconnected to the auxiliary wire ALa through the contact hole60′ of the second insulating layer160. The resistance of the driving voltage lines172a,172b, and172cmay be reduced, and a voltage drop of the driving voltage ELVDD transferred through the driving voltage lines172a,172b, and172cmay be reduced. The auxiliary wire ALa may overlap the common voltage line170as shown, but may not overlap the common voltage line170. The common voltage line170may be connected to the auxiliary wire ALa through a contact hole formed in the second insulating layer160.

The initialization voltage line173may be connected to the horizontal initialization voltage line153through the contact hole69of the second insulating layer160. The horizontal initialization voltage line153may transfer the initialization voltage together with the initialization voltage line173. The initialization voltage may be transferred to all three pixels PX1, PX2, and PX3through the horizontal initialization voltage line153even when one initialization voltage line173is disposed for every three pixels PX1, PX2, and PX3. The three pixels PX1, PX2, and PX3may receive the initialization voltage simultaneously through the horizontal initialization voltage line153, and may constitute one pixel group.

One capacitor electrode175may be disposed for the pixels PX1, PX2, and PX3. The capacitor electrode175may overlap the corresponding driving gate electrode155with the second insulating layer160therebetween to form the capacitor Cst. The first electrode C1and the second electrode C2of the capacitor Cst ofFIG.2may correspond to the driving gate electrode155and the capacitor electrode175, respectively.

The capacitor electrode175may include a protrusion175aextending downward. The protrusion175amay be connected to the drain region135aof the active pattern130aas illustrated inFIG.4for example or the source region133cof the active pattern130cthrough the contact hole62of the second insulating layer160. The capacitor electrode175may be connected to the lower pattern111through the contact hole68of the buffer layer120and the second insulating layer160as illustrated for example inFIG.4. The lower pattern111may be electrically connected to the drain region135aor the source region133c.

The connecting member174may be electrically connected to the second scan line152and the third gate electrode154cthrough the contact hole24of the second insulating layer160to electrically connect the second scan line152and the third gate electrode154c.

The connecting member176may be electrically connected to the first scan line151and the second gate electrode154bthrough the contact hole26of the second insulating layer160to electrically connect the first scan line151and the second gate electrode154b.

The connecting member177may be connected to the drain region135cof the active pattern130cthrough the contact hole63of the second insulating layer160in each of the pixels PX1, PX2, and PX3, to be connected to be the horizontal initialization voltage line153through the contact hole67of the second insulating layer160. The drain region135cof the active pattern130cmay be electrically connected to the horizontal initialization voltage line153.

The horizontal initialization voltage line153may extend substantially in the first direction x across three pixels PX1, PX2, and PX3. The horizontal initialization voltage line153may be disposed between two adjacent common voltage lines170, and may not intersect the two common voltage lines170. The horizontal initialization voltage line153may intersect the three neighboring data lines171a,171b, and171c, and may extend to the initialization voltage line173. As another example, the horizontal initialization voltage line153may intersect the three neighboring data lines171a,171b, and171c, and may extend to only the initialization voltage line173.

The connecting member178may be connected to the drain region135bof the active pattern130bthrough the contact hole65of the second insulating layer160in each of the pixels PX1, PX2, and PX3, and may be connected to be the protrusion155aof the driving gate electrode155through the contact hole66of the second insulating layer160. The connecting member178may electrically connect the drain region135bof the active pattern130band the protrusion155aof the driving gate electrode155.

Each of the first conductive layer, the second conductive layer, and the third conductive layer may include a metal such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta), or an alloy thereof. Each of the first conductive layer, the second conductive layer, and the third conductive layer may have a single layer or multilayer structure as understood by those of ordinary skill in the art.

The first transistor T1includes the channel region134a, the source region133a, the drain region135a, and the first gate electrode154a. Since the source region133aof the first transistor T1is electrically connected to the driving voltage lines172a,172b, and172c, the driving voltage may be applied thereto.

As illustrated for example inFIG.4, the lower pattern111corresponding to the first transistor T1may be formed to overlap the channel region134aof the first transistor T1between the channel region134aand the substrate110, to block external light from entering the channel region134a, thereby reducing a leakage current of the first transistor T1and characteristic deterioration. The lower pattern111may be electrically connected to the drain region135aof the first transistor T1through the capacitor electrode175.

The lower pattern111may entirely overlap the active pattern130a, and may overlap all of the source region133a, the channel region134a, and the drain region135aof the first transistor T1as illustrated inFIG.4for example. A region where the active pattern130ais formed may be positioned in a region where the lower pattern111is formed. Since the active pattern130adoes not intersect an edge of the lower pattern111, defects such as disconnection of the active pattern130anear the edge of the lower pattern111, which may be thicker than the active pattern130aand may form a relatively large step, as would be understood and appreciated by one of ordinary skill in the art, may be prevented. It may be possible to improve layout disposing efficiency in the vicinity of the lower pattern111and the active pattern130a.

The lower pattern111may be electrically connected to the pixel electrodes191a,191b, and191cthrough the capacitor electrode175to overlap the channel region134aof the first transistor T1, and thus a current change rate of a saturation region in a voltage-current characteristic graph may be lowered to widen a range of a region where an output current of the first transistor T1may be constant. Even when a source-drain voltage Vdsof the first transistor T1may be varied, an output current of the first transistor T1may be constant, thereby improving an output saturation characteristic. A luminance deviation between the pixels depending on the output current of the first transistor T1may be reduced, thereby improving the image quality.

The second transistor T2includes the channel region134b, the source region133b, the drain region135b, and the second gate electrode154b. The source region133bof the second transistor T2may be electrically connected to the data lines171a,171b, and171cto receive the data voltage or the reference voltage. The drain region135bof the second transistor T2may be electrically connected to the first gate electrode154athrough the driving gate electrode155.

The third transistor T3includes the channel region134c, the source region133c, the drain region135c, and the third gate electrode154c. The drain region135cof the third transistor T3may receive the initialization voltage from the horizontal initialization voltage line153.

A third insulating layer181may be disposed on the second insulating layer160and the third conductive layer. The third insulating layer181may include a contact hole83a overlapping the capacitor electrode175as illustrated for example inFIG.5and a contact hole81overlapping the common voltage line170as illustrated inFIG.3.

A fourth conductive layer including contact members190a,190b,190c, and190dmay be disposed on the third insulating layer181.

The contact members190a,190b, and190cmay be respectively disposed in the pixels PX1, PX2, and PX3, and may be in contact with and electrically connected to the capacitor electrode175through the contact hole83a.

As illustrated inFIG.6, for example, contact member190dmay be in contact with and electrically connected to the common voltage line170through the contact hole81.

The contact members190a,190b,190c, and190dmay improve adherence between the capacitor electrode175of the third conductive layer and the common voltage line170and other conductive layers, and may prevent oxidation of the third conductive layer. For example, when an upper layer of the third conductive layer contains copper, oxidation of the copper may be prevented. The fourth conductive layer may contain a conductive material that may be capable of preventing corrosion of the upper layer of the third conductive layer. For example, when the upper layer of the third conductive layer contains copper, the fourth conductive layer may contain a conductive material that may prevent copper corrosion by capping the upper layer of the third conductive layer. The fourth conductive layer may include a conductive material such as a metal oxide, for example, indium tin oxide (ITO) or indium zinc oxide (IZO) or other suitable material as would be appreciated and understood by those of ordinary skill in the art.

A fourth insulating layer182may be disposed on the third insulating layer181and the fourth conductive layer. The fourth insulating layer182may be disposed on the contact members190a,190b,190c, and190d, and may have a contact hole83boverlapping the contact hole83a. For example,FIG.5illustrates the fourth insulating layer182disposed on the contact member190aand having a contact hole83boverlapping the contact hole83a.

At least one of the buffer layer120, the first insulating layer, the second insulating layer160, the third insulating layer181, and the fourth insulating layer182may include an inorganic insulating material such as a silicon nitride (SiNx), a silicon oxide (SiOx), and a silicon oxynitride (SiON), and/or an organic insulating material. For example, the fourth insulating layer182may include an inorganic insulating material and/or an organic insulating material such as a polyimide, an acrylic-based polymer, a siloxane-based polymer, and the like, and may have a substantially flat upper surface.

A pixel electrode layer191including pixel electrodes191a,191b, and191cmay be disposed as a fifth conductive layer on the fourth insulating layer182. The pixel electrodes191a,191b, and191cmay be respectively disposed in the corresponding pixels PX1, PX2, and PX3. The pixel electrodes191a,191b, and191cdisposed at three pixels PX1, PX2, and PX3may differ in size and shape. The pixel PX1may represent red, the pixel PX2may represent green, and the pixel PX3may represent blue. The pixels PX1, PX2and PX3are not limited to the aforementioned respective colors and may be any one of red, green or blue. The region that emits light from each of the pixels PX1, PX2, and PX3may be substantially smaller than regions of the pixel electrodes191a,191b, and191c. Each of the pixel electrodes191a,191b, and191cmay include a portion overlapping the auxiliary wires ALa, ALb, and ALc.

The pixel electrodes191a,191b, and191cmay respectively contact the corresponding contact members190a,190b, and190cthrough the contact hole83bof the fourth insulating layer182, and may be electrically connected to the capacitor electrode175through the contact members190a,190b, and190c. Each of the pixel electrodes191a,191b, and191cmay be electrically connected to the drain region135aof the first transistor T1to receive a voltage from the first transistor T1.

The pixel electrode layer191may include a transflective conductive material or a reflective conductive material. The transflective or reflective conductive materials may include any such materials as would be understood and appreciated by those of ordinary skill in the art.

A fifth insulating layer350may be disposed on the fourth insulating layer182. The fifth insulating layer350may have an opening355disposed on the pixel electrodes191a,191b, and191c. The fifth insulating layer350may include an organic insulating material such as a polyacrylic-based resin or a polyimide-based resin.

A light emission layer370may be disposed on the fifth insulating layer350and the pixel electrode layer191. The light emission layer370may include a portion disposed in the opening355of the fifth insulating layer350as illustrated for example, inFIG.4. The light emission layer370may include an organic emission material or an inorganic emission material. At least a portion of the fifth insulating layer350may not be covered by the light emission layer370as illustrated for example inFIG.4.

The fifth insulating layer350and the light emission layer370may include a contact hole82overlapping the contact member190das illustrated for example inFIG.6.

A common electrode270may be disposed on the light emission layer370. The common electrode270may be continuously formed across the pixels PX1, PX2, and PX3. The common electrode270may be in contact with the contact member190dthrough the contact hole82to be electrically connected to the common voltage line170to receive the common voltage as illustrated for example inFIG.6.

The common electrode270may include a conductive transparent material.

The pixel electrodes191a,191b, and191cof the respective pixels PX1, PX2, and PX3, the light emission layer370, and the common electrode270together constitute a light emitting diode ED. One of the pixel electrodes191a,191b, and191c, and the common electrode270, serves as an anode, and the other serves as a cathode.

A sealing substrate (not illustrated) for sealing the light emitting diode ED may be disposed on the common electrode270, and a color filter (not illustrated) corresponding to each of the pixels PX1, PX2, and PX3may be disposed in the sealing substrate.

A display device according to an embodiment will be described with reference toFIG.7as well as the aforementioned drawings.

FIG.7illustrates a schematic cross-sectional view taken along line C-C′ ofFIG.3according to an embodiment.

The embodiment ofFIG.7is similar to most of the aforementioned embodiments, except that the fourth insulating layer182may include a contact hole81apositioned on the contact member190d, and the pixel electrode layer191may include a contact member191dthat contacts the contact member190dthrough a contact hole81a. The fifth insulating layer350and the light emission layer370may include a contact hole82aoverlapping the contact member191d. The common electrode270may be in contact with the contact member191dthrough the contact hole82ato be electrically connected to the common voltage line170to receive the common voltage.

A display device according to an embodiment will be described with reference toFIG.8andFIG.9as well as the aforementioned drawings.

FIG.8andFIG.9each illustrate a schematic cross-sectional view taken along line A-A′ ofFIG.3according to an embodiment.

The embodiment ofFIG.8is similar to most of the aforementioned embodiments, except that it may include a sixth insulating layer122disposed on the second conductive layer and a sixth conductive layer disposed between the sixth insulating layer122and the second insulating layer160.

The sixth insulating layer122may contact the upper surfaces of the conductive regions of the active patterns130a,130b, and130c. The sixth insulating layer122may include a contact hole61acorresponding to and overlapping the contact hole61of the second insulating layer160, and may include contact holes62aand68a.

In the embodiment ofFIG.8, a capacitor electrode157disposed in the sixth conductive layer may be included instead of the aforementioned capacitor electrode175. The capacitor electrode157may be connected to the lower pattern111through the contact hole68a, and may be connected to the drain region135aof the active pattern130athrough the contact hole62a.

The capacitor electrode157may have a planar shape similar to that of the capacitor electrode175described above. The capacitor electrode157may overlap the corresponding driving gate electrode155with the sixth insulating layer122therebetween to constitute the capacitor Cst.

The sixth conductive layer may include a connection pattern163. The connection pattern163may be in contact with the source region133aof the active pattern130athrough the contact hole61aof the sixth insulating layer122. The driving voltage line172amay be in contact with and electrically connected to the connection pattern163through the contact hole61of the second insulating layer160to be electrically connected to the source region133aof the active pattern130a.

In the embodiment ofFIG.8, the sixth conductive layer may include the auxiliary wires ALa, ALb, and Alc, which may be included in the second conductive layer in the aforementioned embodiment. For example, the auxiliary wires ALa, ALb, and ALc may be disposed at a region where constituent elements other than the auxiliary wires ALa, ALb, and Alc, i.e., the capacitor electrode157and the connection pattern163, are not formed in the sixth conductive layer. At least one of the auxiliary wires ALa, ALb, and ALc may be connected to the connection pattern163to be formed continuously with the connection pattern163. The capacitor electrode157, the connection pattern163, and the auxiliary wires ALa, ALb, and ALc, which are constituent elements included in the sixth conductive layer, may be formed in a same layer by using a same process.

The embodiment ofFIG.9is similar to most of the aforementioned embodiment, except that it may include a seventh insulating layer180disposed between the third conductive layer and the third insulating layer181, and a seventh conductive layer disposed between the seventh insulating layer180and the third insulating layer181.

The seventh conductive layer may include conductive patterns that extend in parallel with the data lines171a,171b, and171c, the driving voltage lines172a,172b, and172c, the common voltage line170, the initialization voltage line173, and the like of the third conductive layer, to be electrically connected thereto. For example, the seventh conductive layer may include a conductive pattern183and a conductive pattern185electrically connected to the driving voltage line172aand the common voltage line170through the contact holes of the seventh insulating layer180, respectively. The conductive patterns183and185may transfer a same voltage as that of the constituent elements of the third conductive layer connected thereto, to thereby reduce the voltage drop.

When the display device includes the seventh conductive layer, the third conductive layer may include some of the data lines171a,171b, and171c, the driving voltage lines172a,172b, and172c, the common voltage line170, the initialization voltage line173, the capacitor electrode175, and the connecting members174,176,177, and178, which may be included in the third conductive layer in the aforementioned embodiment, and the seventh conductive layer may include the other aforementioned elements, for example the conductive patterns183and185.

Hereinafter, the display device according to some embodiments will be described mainly regarding differences from the above-described embodiment.

FIG.10illustrates a layout view of a pixel area of a display device according to an embodiment,FIG.11illustrates a schematic cross-sectional view taken along line D-D′ ofFIG.10according to an embodiment, andFIG.12illustrates a schematic cross-sectional view taken along line E-E′ ofFIG.10according to an embodiment.

Referring toFIG.10,FIG.11, andFIG.12, the fourth conductive layer may include an auxiliary wire AL together with the contact members190a,190b,190c, and190d. InFIG.10, a shaded area corresponds to a region where the auxiliary wire AL may be formed. The auxiliary wire AL may be disposed apart from the contact members190a,190b,190c, and190din a region where the contact members190a,190b,190c, and190dare not formed, for example,FIG.12illustrates auxiliary wire AL disposed apart from contact member190din a region where contact member190dis not formed. The auxiliary wire AL may be separated from the contact members190a,190b,190c, and190d. The auxiliary wire AL may be formed in a same layer by using a same process as those of the contact members190a,190b,190c, and190d.

The auxiliary wire AL may be continuously formed across groups of the pixels PX1, PX2, and PX3. The auxiliary wire AL may be formed separately for each group of the pixels PX1, PX2, and PX3or for each of the pixels PX1, PX2, and PX3. The auxiliary wire AL may include a portion overlapping the common voltage line170, a portion overlapping the driving voltage lines172a,172b, and172c, as illustrated inFIG.11and a portion overlapping the data lines171a,171b, and171c. The auxiliary wire AL may be connected to the driving voltage lines172a,172b, and172cthrough a contact hole80′ of the third insulating layer181.FIG.11illustrates the auxiliary wire AL connected to the driving voltage line172athrough a contact hole80′ of the third insulating layer181. Although not illustrated, the auxiliary wire AL may be connected to the common voltage line170through a contact hole formed in the third insulating layer181. In the region of one group of pixels PX1, PX2, and PX3, the auxiliary wire AL is separated into at least two portions, a first one of which may be electrically connected to driving voltage lines (e.g.,172band172c) and a second one may be electrically connected to the common voltage line170. As described above, the auxiliary wire AL may be electrically connected to the power voltage lines such as the driving voltage lines172a,172b, and172cand the common voltage line170to reduce the resistance of the power voltage lines and voltage drops of power voltages transferred through the power voltage lines.

Referring toFIG.13, the auxiliary wire AL may be formed to not overlap at least a portion of the first scan line151in order to reduce the capacitance that may be formed between the auxiliary wire AL and the first scan line151. For similar reasons, the auxiliary wire AL may be formed to not overlap at least a portion of the second scan line152. The auxiliary wire AL may have an opening OP1overlapping the first scan line151and/or an opening OP2overlapping the second scan line152.

FIG.14illustrates a layout view of a pixel area of a display device according to an embodiment, andFIG.15illustrates a schematic cross-sectional view taken along line F-F′ ofFIG.14according to an embodiment.

Referring toFIG.14andFIG.15, the fourth conductive layer includes an auxiliary wire AL together with the contact members190a,190b,190c, and190din the embodiment, similar to the embodiment ofFIG.10toFIG.12. InFIG.14, a shaded portion corresponds to the auxiliary wire AL. The auxiliary wire AL may be separated and spaced apart from the contact members190a,190b, and190c, but may be connected to and continuously formed with the contact member190d. Since the contact member190dis connected to the common voltage line170through the contact hole81, the auxiliary wire AL may be electrically connected to the common voltage line170. Since the auxiliary wire AL may transfer the common voltage ELVSS together with the common voltage line170, the voltage drop of the common voltage ELVSS may be reduced.

The auxiliary wire AL may be continuously formed across groups of the pixels PX1, PX2, and PX3, but the auxiliary wire AL may be formed separately for each group of the pixels PX1, PX2, and PX3or for each of the pixels PX1, PX2, and PX3.

The auxiliary wire AL may be connected to the driving voltage lines172a,172b, and172cthrough the contact hole80′ of the third insulating layer181. The auxiliary wire AL may be connected to the common voltage line170through a contact hole81formed in the third insulating layer181as illustrated inFIG.15. In the region of one group of pixels PX1, PX2, and PX3, the auxiliary wire AL may be separated into at least two portions, a first one of which may be electrically connected to the common voltage line170and a second one may be electrically connected to driving voltage lines (e.g.,172band172c).

FIG.16illustrates a layout view of a pixel area of a display device according to an embodiment, andFIG.17illustrates a schematic cross-sectional view taken along line G-G′ ofFIG.16according to an embodiment.

Referring toFIG.16andFIG.17, the display device may include an auxiliary wire AL disposed between the substrate110and the buffer layer120. For example, the first conductive layer may include the auxiliary wire AL together with the lower pattern111, and the auxiliary wire AL may be formed in a same layer by using a same process as that of the lower pattern111. InFIG.16, a shaded area corresponds to a region where the auxiliary wire AL may be formed.

The auxiliary wire AL may be separated from the lower pattern111and spaced apart therefrom as illustrated inFIG.17. Since the lower pattern111overlaps the active pattern130a, the auxiliary wire AL does not overlap the active pattern130a. The auxiliary wire AL may not overlap the active patterns130band130cas well as the active pattern130ain order to prevent a back bias effect.

The driving voltage lines172a,172b, and172cmay be connected to the auxiliary wire AL through a contact hole602formed in the second insulating layer160and the buffer layer120. Accordingly, the auxiliary wire AL may reduce the resistance of a wire for transferring the driving voltage ELVDD and the voltage drop of the driving voltage ELVDD.

The common voltage line170may be connected to the auxiliary wire AL through the contact hole601formed in the second insulating layer160and the buffer layer120as illustrated inFIG.17. As illustrated inFIG.18, the auxiliary wire AL may be separated into at least two portions AL1and AL2such that the common voltage line170may be connected to a first portion AL1through the contact hole601formed in the second insulating layer160and the buffer layer120, and the driving voltage lines172a,172b, and172cmay be connected to a second portion AL2through a contact hole602formed in the second insulating layer160and the buffer layer120. InFIG.18, a shaded area corresponds to a region where the auxiliary wire AL may be formed.

The auxiliary wire AL may be formed to occupy a wide portion in the pixel region, whereby an undesired capacitor may be formed between the auxiliary wire AL and another wire. A thicker insulating layer may be formed on the auxiliary wire AL in order to reduce the capacitance of such a capacitor. To this end, the buffer layer120may be formed of multiple layers including at least a first layer120aand a second layer120b. The first layer120aand/or the second layer120bmay include an organic insulating material or an inorganic insulating material. Similarly, the second insulating layer160may be formed of multiple layers including at least a first layer160aand a second layer160b, and the first layer160aand/or the second layer160bmay include an organic insulating material or an inorganic insulating material. Increasing the thickness of the insulating layer in order to reduce the capacitance between the auxiliary wire AL and other wires in this way may be equally applied to the other embodiments described above.

In the above embodiments, the auxiliary wires AL, ALa, ALb, and ALc may be connected to the driving voltage transfer line DVL and/or the common voltage transfer line CVL in the non-display area NA illustrated inFIG.1. Although the auxiliary wires AL, ALa, ALb, and ALc are described as being electrically connected to a power voltage line such as the driving voltage lines172a,172b, and172cor the common voltage line170, the auxiliary wires AL, ALa, ALb, and ALc may be electrically connected to wires other than the power voltage line. For example, some of the auxiliary wires AL, ALa, ALb, and ALc may be electrically connected to the data lines171a,171b, and171c, thereby contributing to reducing the delay of the data signal.

While the invention has been illustrated and described with reference to the embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be formed thereto without departing from the spirit and scope of the invention.