Patent ID: 12191865

DETAILED DESCRIPTION

Embodiments of apparatuses and methods disclosed herein relate to phase lock loop (PLL) synchronization. In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips include respectively first, second, and third phase lock loop (PLL). The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. The first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals. These and other aspects of the present disclosure will be more fully described below.

While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (B and C); (A and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (B and C); (A and C); or (A, B, and C).

Language such as “top surface”, “bottom surface”, “vertical”, “horizontal”, and “lateral” in the present disclosure is meant to provide orientation for the reader with reference to the drawings and is not intended to be the required orientation of the components or to impart orientation limitations into the claims.

In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, it may not be included or may be combined with other features.

Many embodiments of the technology described herein may take the form of computer- or processor-executable instructions, including routines executed by a programmable computer, processor, controller, chip, and/or the like. Those skilled in the relevant art will appreciate that the technology can be practiced on computer/controller systems other than those shown and described above. The technology can be embodied in a special-purpose computer, controller, or processor that is specifically programmed, configured or constructed to perform one or more of the computer-executable instructions described above. Accordingly, the terms “computer,” “controller,” “processor,” or the like as generally used herein refer to any data processor and can include Internet appliances and hand-held devices (including palm-top computers, wearable computers, cellular or mobile phones, multi-processor systems, processor-based or programmable consumer electronics, network computers, mini computers, and the like). Information handled by these computers can be presented at any suitable display medium, including an organic light emitting diode (OLED) display or liquid crystal display (LCD).

FIG.1is an example illustration of a block diagram showing a daisy chain of integrated circuit (IC) chips configured to facilitate timing signal distribution in accordance with some embodiments of the present disclosure. Each chip of the plurality of IC chips100is identical or similar to each other. Each chip of a plurality of IC chips100is serially or sequentially electrically coupled with each other, thereby forming a daisy chain of chips. The plurality of IC chips100comprises P number of chips. A chip102(denoted as chip1or the first chip), a chip104(denoted as chip2or the second chip), and a chip106(denoted as chip P or the last chip) of the plurality of IC chips100are shown inFIG.1.

A modem108is configured to provide a timing signal, also referred to as L1sync, to chip102. The timing signal comprises a low frequency synchronization signal that has a square wave or a step wave shape. A reference clock110is configured to provide a reference clock signal to each chip of the plurality of IP chips100. The reference clock signal comprises a differential sinusoidal wave signal or a single-ended sinusoidal signal. In response, circuitry103included in chip102is configured to distribute or share the timing signal with the next chip in the daisy chain, namely, chip104. Circuitry103includes one or more amplifiers, amplifiers/buffers, flip-flops, and/or other electrical components arranged as shown inFIG.1. In some embodiments, a signal pathway length between adjacent chips may be in the order of approximately 10 centimeter (cm).

Circuitry105included in chip104, in turn, distributes the timing signal (L1sync) received from chip102to the next chip in the daisy chain (e.g., to chip3). The nth chip distributes the timing signal L1sync to the n+1th chip, including to the last chip106including circuitry107similar to circuitry103,105.

Hence, the same timing signal L1sync is distributed to each chip of the plurality of IC chips100. The timing signal L1sync is respectively distributed among the chips100with a predictable or known link—a predictable chip-to-chip distance. When modem108generates the next timing signal, such timing signal is similarly distributed from chip1, chip2, and so forth, to chip P as described above.

In some embodiments, each chip of the plurality of IC chips100also includes circuitry or components configured to use the timing signal L1sync. For instance, without limitation, circuitry/component sections113,115, and117included in respective chips102,104, and106may use the timing signal L1sync.

FIG.2Ais an example illustration of a block diagram showing generation of a first level reference time in each chip of the plurality of IC chips100in accordance with some embodiments of the present disclosure.FIG.2Bis an example illustration of a waveform diagram associated with generation of the first level reference time in each chip in accordance with some embodiments of the present disclosure. Referring toFIG.2A, chips240and242comprise chips of the plurality of IC chips100arranged in a daisy chain arrangement. Chip240may comprise the nth chip (where n<P) and chip242may comprise the Pth or last chip in the daisy chain arrangement. In some embodiments, chips240,242may be similar to respective chips104,106.

Each chip of the plurality of IC chips100includes one or more circuitry or component sections. For example, without limitation, chip240includes a circuitry section similar to circuitry105(not shown inFIG.2A) and a circuitry/component section208. If chip240comprises chip104ofFIG.1, then section208comprises section115. Chip240receives the timing signal (L1sync) from the immediately preceding chip (the n−1th chip), the reference clock signal (sinus_refclk) from the reference clock110, and a reset signal from modem108. Chip240is configured to distribute the timing signal (L1sync) to the next chip (the n+1th chip) as described above in connection withFIG.1. Chip240is further configured to generate a first level reference time signal (L1_reference_time). Each chip of the plurality of IC chips100may include circuitry and/or components such as circuitry105and section208.

In some embodiments, section208included in chip240is configured to receive the timing signal (L1sync) from the immediately preceding chip at a subsection200, perform appropriate signal processing (e.g., signal amplification, buffering, etc.) within subsection200, and provide the timing signal to a counter202. The reference clock signal (sinus_refclk) is received by an amplifier/buffer204included in section208. In some embodiments, amplifier/buffer204is configured to convert the reference clock signal, which has a sinusoidal waveform shape, into a converted reference clock signal (refclk) having a square waveform. The amplifier/buffer204may be part of a Schmitt trigger circuit, for example, to perform the waveform shape conversion. The converted reference clock signal is also an input to counter202. The reset signal (rstn) is an input to subsection206included in section208, which processes the reset signal as necessary, and then provides the (processed) reset signal as an input to counter202.

Although not shown, section208can further include associated electrical components and/or elements such as, but not limited to, buffers, digital flops, passive electrical elements, resistors, inductors, capacitors, feedback loops, and/or the like to process one or more of the input signals (e.g., timing signal, reference clock signal, reset signal) into formats suitable to be inputs to the counter202.

As shown inFIG.2B, the reference clock signal (sinus_refclk) is represented as a waveform210having a sinusoidal wave shape. As an example, the reference clock signal can have a frequency in the range of a few Megahertz (MHz) to a few hundred MHz. The reference clock signal comprises a continuous signal having a constant periodicity. Waveform212, having a square wave shape, represents the converted reference clock signal (refclk). The converted reference clock signal retains the same period as the reference clock signal (e.g., both waveforms210and212have the same period222). Waveform214having a step (or square) wave shape comprises the reset signal. Waveform216having a step (or square) wave shape comprises the timing signal (L1sync). As an example, the period associated with the timing signal may be a few kilohertz (kHz).

Counter202, also referred to as a L1_time_counter, is configured to generate and output the first level (L1) reference time signal based on the timing signal, converted reference clock signal, and reset signal. The first level reference time signal is also referred to as L1_reference_time, a L1reference timing signal, or the like. Counter202is configured to count the number of cycles, periods, or pulses of the converted reference clock signal received starting from a particular point in time as specified by the timing signal (L1sync). The timing signal (L1sync) changing to a high (or is at a rising edge) can comprise the particular point in time at which counter202is triggered to start counting the converted reference clock signal. This count is specified in the first level reference time signal. Because counter202continuously counts the number of cycles/periods/pulses of the converted reference clock signal, the first level reference time signal correspondingly provides the present or real-time count value.

In some embodiments, counter202counts during the timing signal's period and automatically resets to zero to start counting again starting at the point in time at which the next rising edge (or high) of the timing signal occurs. Thus, the count performed by counter202follows or tracks the periodicity of the timing signal (L1sync).

In some embodiments, counter202can, in addition and/or in the alternative, be configured to reset to a zero count (e.g., if a rising or falling edge of the reset signal is detected or if the reset signal is in a low state) or to continue counting (e.g., if the reset signal is not at a rising/falling edge or the reset signal in a high state) based on the particular state of the reset signal. The same (state of the) reset signal (waveform214) is provided to each chip of the plurality of IC chips100. The same (state of the) reference clock signal (waveform210) is also provided to each chip of the plurality of IC chips100. The timing signal (waveform216) is provided to all chips of the plurality of IC chips100via the daisy chain arrangement described above. The same timing signal (or state of the timing signal) is received by all of the chips100within a single period of the reference clock signal.

For example, the rising edge of waveform214(reset signal) shown inFIG.2Bspecifies to the counter202to reset its counter. The rising edge or a high state of waveform216(timing signal) (e.g., portion218of waveform216) is configured to occur and be received by all of the chips100within a same single period (e.g., period222) of waveform212(converted reference clock signal). Portion218of waveform216comprises the trigger or identification of a particular time point from which the counter202is to start counting. Portion218is configured not to violate any set up and/or hold constraints associated with the chip. Accordingly, detection of the particular period222of the converted reference clock signal causes counter202to increment by one so that the count now equals one. Alternatively, the period immediately after the particular period222may cause counter202to increment by 1 so that the count now equals one. In any case, all of the chips100are configured to conform to the same counter increment triggering convention. Counter202continues to increment with each successive cycle/period of the converted reference clock signal until a particular change to the reset signal is detected.

A counter included in each of the remaining chips100simultaneously performs the same counting function based on the same input signals. Thus, the first level reference time signals outputted by the counters of all of the chips100specify the same count value at each time point. The first level (L1) counters are synchronized between the chips of the plurality of IC chips100. The same count value specified by the first level reference time signals across all of the chips100can be used as a common or synchronized reference time for the chips100to synchronize or simultaneously perform one or more particular operations/actions in more than one chip of the plurality of IC chips100. For instance, when the first level reference time signal is at a count of 5,000, a first particular operation is to be performed in each chip of the plurality of IC chips100; when the first level reference time signal is at a count of 10,005, a second particular operation is to be performed by chip1, chip2, and chip40; when the first level reference time signal is at a count of 50,500, a third particular operation is to be performed by all of chips100; and the like.

FIG.3is an example illustration of a block diagram showing generation of a second level reference time in a chip in accordance with some embodiments of the present disclosure. In some embodiments, each of the chips100can include circuitry/components such as circuitry105associated with distribution of the timing signal L1sync in the daisy chain arrangement and a section300to generate a second level reference time signal. Section300can comprise section113,115, or117ofFIG.1. The second level reference time signal is also referred to as an L2_reference_time, a L2reference timing signal, or the like. The second level reference time signal comprises a higher resolution reference time based on the first level reference time signal. Thus, the first level reference time signal may be considered to be a coarse (resolution) reference time and the second level reference time signal may be considered to a fine or (higher resolution) reference time.

Section300is configured to generate and output the second level reference time signal (L2_reference_time) based on the timing signal (L1sync) and the reference clock signal (sinus_refclk). In section300, subsection301, first level counter302, and amplifier/buffer304are similar to respective subsection200, counter202, and amplifier/buffer204ofFIG.2A. Timing signal (L1sync) is an input to the first level counter302. The converted reference clock signal (refclk) generated by amplifier/buffer304comprises an input to each of the first level counter302and flip flop308. The first level reference time signal (L1_reference_time) and output of a second level register305comprise the inputs to a comparator306. The second level register305, also referred to as a L2_time_start register, is configured to store or specify a particular first level reference time signal count value (e.g., a pre-defined count value) associated with triggering actuation of a second level counter314.

Comparator306is configured to determine if the count value specified by the first level reference time signal at least equals (is equal to or greater than) the pre-defined count value specified in the second level register305. Flip flops308and312provided at the output of the comparator306are configured to generate a second level reference time start signal (L2sync) in accordance with the determination made by the comparator306. If the comparator306determines that the two count values are at least equal to each other, then the second level reference time start signal is configured to have a rising edge without delay, to specify a trigger similar to portion218shown inFIG.2Bbut for triggering start of counting by the second level counter314. If the comparator306determines that the two count values are not at least equal to each other (that the first level reference time signal count value is less than the second level register305pre-defined count value), then the second level reference time start signal is configured to not include a rising edge. The second level reference time start signal is analogous to the timing signal L1sync for the first level counter302or202but instead for the second level counter314. The second level reference time start signal is also referred to as a start signal, a second level timing signal, L2sync, and/or the like.

In some embodiments, flip flop308may be configured to generate an initial signal with a rising edge in accordance with the determination made by the comparator306, and flip flops312may be configured to detect the rising edge included in the initial signal and generate a final signal indicative of the detected rising edge to the second level counter314. The final signal to the second level counter314comprises the start signal, L2sync signal, and/or second level reference time start signal. The first pulse of the start signal starts or triggers the second level counter314.

Another input to the second level counter314comprises a reference digital clock signal (clk_dbf) from a reference clock phase lock loop (CLK PLL)316. In some embodiments, this digital clock signal (clk_dbf) comprises a sinusoidal waveform having a frequency of N times that of the reference clock signal (sinus_refclk). Digital clock signal (clk_dbf) is analogous to reference clock signal (sinus_refclk) inputted to the first level counter302/202, except due to its higher frequency, the period or cycle of digital clock signal (clk_dbf) is smaller than that of the reference clock signal (sinus_refclk) and thereby provides a better time resolution. The smaller periodicity of digital clock signal (clk_dbf), in turn, permits finer/smaller time resolution counting than associated with L1_reference_time and the first level counter202/302alone. Digital clock signal (clk_dbf) from CLK PLL316is also an input to the flip flops312to facilitate generation of L2sync to reset or resynchronize the second level counters in all of the chips100.

Second level counter314, also referred to as a L2_time_counter, is configured to start counting the number of periods or cycles of the digital clock signal (clk_dbf) starting from a trigger or start time point specified by the second level reference time start signal. In some embodiments, a rising edge detection in the first pulse of the second level reference time start signal (L2sync) comprises the trigger or start of counting by the second level counter314. The output of the second level counter314comprises the second level reference timing signal (L2_reference_time), which specifies the present or real-time count value. Once the second level counter314starts counting, the counter is free running and the next pulses of the second level reference time start signal do not reset or reinitialize the counter until another trigger from flip flop308is issued.

In an embodiment, without limitation, the second level reference timing signal (L2_reference_time) may comprise 32 bits, and may be stored in memory locations [31:0]. As an example, the second level reference timing signal (L2_reference_time) can be used to synchronize data read or write buffers or registers located in more than one chip of the plurality of IC chips100or otherwise synchronize performance of particular operations/actions at particular clock cycles across the chips100.

FIG.4Ais an example illustration of a block diagram showing generation of a modified second level reference time in a chip in accordance with some embodiments of the present disclosure. In some embodiments, each of the chips100can include circuitry/components such as circuitry105associated with distribution of the timing signal L1sync in the daisy chain arrangement and a section400to generate a modified second level reference time signal. Section400can comprise section113,115, or117ofFIG.1. The modified second level reference time signal is also referred to as a modified L2_reference_time, a modified L2reference timing signal, a L2′_reference_time, a L2′ reference timing signal, or the like. The modified second level reference time signal comprises a higher resolution reference time based on the first level reference time signal. Thus, the first level reference time signal may be considered to be a coarse (resolution) reference time and the modified second level reference time signal may be considered to a fine or (higher resolution) reference time.

In some embodiments, the count resolution per time offered by the modified second level reference time is the same as with the second level reference time. The second level reference time may be referred to as a first level L2_reference_time and the modified second level reference time may be referred to as a second level L2_reference_time. Second level reference time or modified second level reference time may be generally referred to as L2time.

In some embodiments, the second level reference time signal outputted by second level counter314may not be ideal for use in a different frequency environment associated with at least a portion of a chip. The second level reference time signal is based on a different frequency clock signal (clk_dbf) than the frequency environment associated with the at least a portion of the chip (e.g., the frequency associated with the clock signal used within the at least portion of the chip). A latency mismatch of the clock trees associated with the respective different frequencies can occur. The modified second level reference time generated in section400has a resolution, for example, that is four times better than the period of the clock signal (clk_dbf). This is achieved by controlling the initial phase of the clock signal (clk_dbf) applied to the modified second level counter418without the need for the clock signal (clk_dbf) to be at a higher frequency than it is. Section400may be implemented instead of section300in such a chip to retain the higher resolution possible with the second level time signal without latency mismatch.

Section400is configured to output the modified second level reference time signal based on the timing signal (L1sync) and the reference clock signal (sinus_refclk). In section400, a subsection401, first level counter402, amplifier/buffer404, second level register405, comparator406, and flip flop408are similar to respective subsection301, first level counter302, amplifier/buffer304, second level register305, comparator306, and flip flop308ofFIG.3.

In some embodiments, converted reference clock signal (refclk) generated by amplifier/buffer404comprises the input to a clock tree422. The clock tree422, also referred to as a low latency clock tree, comprises a plurality of flip flops. Clock tree422is configured to split the converted reference clock signal (refclk) into a plurality of split signals, in which each signal of the plurality of split signals comprises a signal phase shifted by a certain amount. Split signals are provided to various components included in a subsection410such as, but not limited to, the first level counter402and flip flop408.

First level counter402, second level register405, comparator406, flip flop408, and associated flip flops included in subsection410may be physically located proximate to each other to reduce clock tree latency.

A start signal (L2sync) outputted from flip flops408,412is similar to the start signal outputted from flip flops308,312. The start signal (L2sync) comprises an input to a phase selection and clock generator414.

A CLK PLL416is configured to generate a digital clock signal (clk_dbf) having, for example, a frequency of N times the frequency of the reference clock (sinus_refclk). CLK PLL416is similar to CLK PLL316. The digital clock signal (clk_dbf) from CLK PLL416comprises the input to a clock tree426. Clock tree426, also referred to as a low latency clock tree, comprises a plurality of flip flops configured to split the input signal into a plurality of split signals to provide to flip flops412and generator414with low latency. Clock tree426may be similar to clock tree422. In some embodiments, flip flops412and generator414are physically located proximate to each other to reduce clock tree latency.

Another input to generator414comprises selectable phase(s) from a phase selection register or similar component. The phase(s) is selected based on 360/N, where the resolution of phase selection is based on N*frequency of the clock signal (clk_dbf). This means the modified second level counter418can start counting with a resolution N times higher than the period of the clock signal (clk_dbf). Generator414is configured to generate the new digital clock signal in the same reference clock domain as the chip (or chip portion) in which the clock signal counts is to be used in accordance with the digital clock signal (clk_dbf) and selected phase(s). Generator414is configured to generate a new digital clock signal having a frequency which is the same as the clock signal (clk_dbf), but the phase can be programmed with a resolution that is N times better or higher. Generator414comprises a multi-phase programmable divider. Generator414may also be referred to as a phase selection and clock generation module.

For instance, the phase selection in generator414may be a 1080 MHz clock signal, while the reference clock domain of the chip (or chip portion) of interest is a 270 MHz environment (e.g., the reference clock of the chip/system clocks in at 270 MHz). A phase selection of 90 degree increments (or phase selections of 90, 180, 270, and 360 degrees) of 1080 MHz is inputted to generator414. In response, the generator414generates a new digital clock signal at 270 MHz, corresponding to one of the four selected phases of 1080 MHz. The 270 MHz frequency of the new digital clock signal has the correct phase to be used as the digital clock of the chip (or chip portion) of interest.

The output of generator414comprises the input to a clock tree424. Clock tree424comprises a high latency clock tree having a greater number of flip flops than either of clock trees422or426. Clock trees426and422, by contrast, each comprises a low latency clock tree having a relatively small number of flip flops. Clock tree424is configured to generate a plurality of split signals (e.g., four split signals) based on new digital clock signal generated by generator414.

The split signal(s) comprise the input to the modified second level counter418. Modified second level counter418is configured to duplicate the fine count resolution capability of the second level counter314, except the output of modified second level counter418comprises a modified second level reference time signal that is configured for use in the digital clock domain of the chip (or chip portion) of interest. The modified second level counter418is clocked by the new digital clock signal and generates the modified second level reference time signal that is indicative of sub-periods or phase increments of the new digital clock signal in accordance with the phase selection inputted to the generator414.

Continuing the above example, the counter418increments by one for each successive 90 degree phase of the new digital clock signal, for a total of four counts per period of the new digital clock signal. In contrast, the second level counter314is clocked by the digital clock signal (clk_dbf) and the count increments by one for each period of the digital clock signal (clk_dbf). Modified second level counter418is also referred to an L2_time_counter or a second level L2_time_counter.

In an embodiment, the modified second level reference time signal comprises a count value that is the same as would be for the second level reference time signal outputted from counter314.FIG.4Billustrates example clock signals in accordance with some embodiments of the present disclosure. Clock signals450and454represent clock or reference signals associated with different frequency clock domains or environments. InFIG.4B, clock signal454has a frequency that is 4 times greater than that of clock signal450. Within the time duration of a single period452of clock signal450, four periods456,457,458, and459of clock signal454occur. In other words, for every 90 degree phase (e.g., ¼ period) of clock signal450, a single period or cycle of clock signal454occurs. Counting each period/cycle of clock signal454is equivalent to counting each successive 90 degree phase or ¼ period portion of clock signal450.

Accordingly, if clock signal450is counted in 90 degree phase or ¼ period increments (instead of by each full period or cycle), then the count value associated with clock signal450can be the same as the count value associated with clock signal454. Such count value associated with clock signal450is at a higher resolution than the periodicity of clock signal450. Each period of clock signal450increments the counter by more than one (e.g., counter increments by four). For sub-period counting scheme, clock signal454can be used and permits the count value to be used in an environment where clock signal450comprises the clocking or reference signal and/or where, in the same environment, a higher or finer resolution count than the periodicity of clock signal450may be required to perform certain actions.

As an example, without limitation, clock signal450may be an example of the new digital clock signal generated by generator414and clock signal454may be an example of the higher frequency clock signal (clk_dbf) from CLK PLL416. The modified second level counter418is configured to provide an initial phase with a resolution that is smaller or finer than a period of the new digital clock signal.

It is understood that the sub-period phase accuracy scheme described above can be implemented in less or greater than four phases per period. For instance, without limitation, generator414, phase selection register, and/or clock tree424can be configured so that each 45 degree phase of the signal outputted by generator414increments the count in counter418, for a total of eight counts per signal period.

The modified second level reference time signal outputted by the modified second level counter418is used to synchronize and/or sequence certain actions in certain components/logic420included in chip(s).

FIG.4Cillustrates a block diagram showing an example use of the first level reference time signal, second level reference time signal, or modified second level reference time signal in accordance with some embodiments of the present disclosure. Counter460comprises any of counters202,314, or418which provides the first level reference time signal, second level reference time signal, or modified second level reference time signal, respectively. A plurality of chip/circuit blocks is associated with a plurality of trigger indices sets. In particular, chip/circuit blocks464,474, and484of the plurality of chip/circuit blocks are associated with respective look up tables (LUTs)462,472, and482of the plurality of LUTs. Chip/circuit blocks464,474, and484are examples of component/chip logic420.

Each chip/circuit block of the plurality of chip/circuit blocks comprises at least a portion of a chip, circuit, or component. Chip/circuit blocks464,474, and484can be the same or different from each other. Chip/circuit blocks464,474, and484can be included in the same chip or in more than one chip. Each LUT of the plurality of LUTs maintains one or more pre-defined trigger indices, each trigger index defining a particular count value at which a particular action is to be taken by a particular chip/circuit block or a portion thereof. The trigger indices between LUTs can be the same or different from each other. LUTs464,474, and/or484can be the same or different from each other. InFIG.4C, LUT462includes trigger indices1,2,3, etc.; LUT472includes trigger indices A, B, C, etc.; and LUT482includes trigger indices1′,2′,3′, etc. Trigger indices1,2,3, etc. included in LUT462comprise, at a minimum, all the trigger indices relevant for operation of chip/circuit block464. Trigger indices A, B, C, etc. and trigger indices1′,2′,3′, etc. are likewise included as relevant for respective chip/circuit blocks474,484.

In some embodiments, the current count value from counter460(e.g., the first, second, or modified second level reference time signal) is provided to each of LUTs462,472, and482. In response, each LUT (or associated processor component) determines whether the current count value is equal to a pre-defined count value associated with any of the trigger indices it maintains. If the current count value is equal to a pre-defined count value, then the chip/circuit block or portion thereof associated with that triggered index is actuated or otherwise commanded to perform a particular action. As an example, trigger index1of LUT462may specify triggering a write operation to register A in chip/circuit block464at a count value of 1000. If the current count value is 1000, then trigger index1would be triggered and the write operation to register A takes place.

In some embodiments, the trigger indices can be provided in a format other than in LUTs; LUTs462,472, and482may be combined into a single LUT; and/or the like.

FIG.5is an example illustration of an IC chip500included in the plurality of IC chips100in accordance with some embodiments of the present disclosure. Chip500comprises, for example, a digital beamformer (DBF) chip. Chip500includes, without limitation, a time synchronization section502, a transmit section504, a receive section506, and a section to distribute the L1sync signal similar to section105(not shown). Section504and/or506(or a portion thereof) comprises an example of the components/logic420.

Time synchronization section502comprises one of sections208,300, or400. Time synchronization section502receives as inputs the reference clock signal from the reference clock110and the timing signal L1sync from the proceeding chip in the daisy chain arrangement (or modem108if chip500is the first chip in the daisy chain arrangement). Transmit section504is configured to receive data beam(s) from the modem108and configure the data beam(s) into a format suitable for transmission by a plurality of antenna elements508. Transmit section504includes a digital baseband processing section510and a plurality of radio frequency (RF) processing sections516.

Each of the sections510and516, in turn, includes a plurality of electrical components or logic, one or more of which may be synchronized in operation between chips in the daisy chain arrangement via use of the first level, second level, or modified second level reference time signal (depending on particular reference time signal produced by section502). For example, a time delay filter512, plurality of phase shifters514, DACs518, and/or the like included in section504may be actuated or cause to perform its respective functions at particular count values of the reference time signal. The same components/logic in other chips of the plurality of IC chips100are actuated or caused to perform its functions at the same particular count values as in chip500via use of the respective reference time signals in the other chips.

Receive section506is configured to receive RF signals from the plurality of antenna elements508and process the RF signals to recover the underlying data beam(s) to provide to modem108. Receive section506includes a digital baseband processing section530and a plurality of RF processing sections536. Each of the sections530and536, in turn, includes a plurality of electrical components or logic, one or more of which may be synchronized in operation between chips in the daisy chain arrangement via use of the first level, second level, or modified second level reference time signal (depending on particular reference time signal produced by section502). For example, a time delay filter532, plurality of phase shifters534, analog-to-digital converters (ADCs)538, and/or the like included in section506may be actuated or cause to perform its respective functions at particular count values of the reference time signal. The same components/logic in other chips of the plurality of IC chips100are actuated or caused to perform its functions at the same particular count values as in chip500via use of the respective reference time signals in the other chips.

In some embodiments, only one of sections504or506may be included in chip500. The transmitter associated components can be implemented in the same or different chip as the chip including the receiver associated components.

Other examples of use of L2time include, without limitation, synchronization and/or sequencing of operations involving DBFs, DAC first in first outs (FIFOs), calibration, and/or the like.

FIG.6is an example illustration of a top view of an antenna lattice600in accordance with some embodiments of the present disclosure. Antenna lattice600(also referred to as a phased array antenna) includes a plurality of antenna elements602arranged in a particular pattern to define a particular antenna aperture. The antenna aperture is the area through which power is radiated by or to the antenna elements602. A phased array antenna synthesizes a specified electric field (phase and amplitude) across an aperture. Adding a phase shift to the signal received or transmitted by each antenna in an array of antennas allows the collective signal of these individual antennas to act as the signal of a single antenna.

A subset604of the plurality of antenna elements602can comprise the M antenna elements508associated with chip500and a subset606of the plurality of antenna elements602can comprise the M antenna elements associated with another chip of the plurality of IC chips100. The remaining subsets of antenna elements of the plurality of antenna elements602may be similarly associated with the remaining chips of the plurality of IC chips100.

In some embodiments, 50, 100, or more chips comprising the plurality of IC chips100may be distributed over a printed circuit board (PCB) that is 0.5 meter (m), 1 m, greater than 1 m in size, or the like. The timing signals generated by the chips100(e.g., the first level reference time signals, second level reference time signals, or modified second level reference time signals) permit time synchronization of operations in the chips100to be performed within less than a few tenth of a picosecond (ps), less than a few hundred ps, or the like of each other. The timing signals generated by the chips100(e.g., the first level reference time signals, second level reference time signals, or modified second level reference time signals) permit time synchronization of operations in the chips100to be performed at a higher accuracy of each other than with use of the chips' input reference clock signal (e.g., reference clock signal (sinus_refclk) from reference clock110).

Time delay filter512in chip500and time delay filters in transmit sections of other chips in the daisy chain arrangement may, for example, be actuated or caused to perform encoding time delay to the received data beams at 10,000 count value of the respective reference time signals. The plurality of phase shifters514in chip500and phase shifters in transmit sections of other chips in the daisy chain arrangement may, for example, by actuated or caused to perform encoding of phases to the received data beams at 14,700 count value of the respective reference time signals. The time synchronization scheme disclosed herein allows dynamic control of the plurality of chips100, especially control of time sensitive operations or actions in the chips100by linking/triggering particular operations/actions across the chips100to particular reference time signals. Each chip of the chips100generates and maintains a same reference time signal.

In this manner, RF signals to be transmitted will be provided at the same time to the plurality of antenna elements508for simultaneous transmission. RF signals to be transmitted will also be provided to respective subsets of plurality of antenna elements for the remaining chips so that all the antenna elements of the antenna lattice transmit or radiate at the same time.

In some embodiments, the chips of the plurality of IC chips100may be the same or different from each other. For example, without limitation, chip1may be a processor chip, chip2may be a DBF chip, chip3may be an amplifier chip, chip4may be memory chip, and the like. Each of these chips can include section105and one of sections208,300, or400so as to synchronize or simultaneously perform particular operations/actions at particular times.

FIG.7is an example illustration of a block diagram showing circuitry or component section700associated with a RF PLL synchronization scheme in accordance with some embodiments of the present disclosure. In some embodiments, each of the IC chips100can include circuitry/components such as circuitry105associated with distribution of the timing signal L1sync in the daisy chain arrangement and section700configured to provide RF PLL synchronization between the IC chips100as described in detail herein.

In some embodiments, section700includes a reference time generator702, a RF PLL register704, a comparator706, a state machine708, a synchronization trigger register710, flip flops712, a RF module714, and a clock tree730. The reference time generator702is configured to output a reference time signal, which is an input to the comparator706. The output of the RF PLL register704also comprises an input to the comparator706. The output of the comparator706comprises the input to the state machine708. The output of the synchronization trigger register710is also an input to the state machine708. The flip flops712are electrically coupled between the state machine708and the RF module714. The clock tree730is electrically coupled between the reference time generator702and RF module714.

In some embodiments, reference time generator702comprises one of sections208,300, or400, and correspondingly, the reference time signal outputted by reference time generator702comprises respective one of the first level, second level, or modified second level reference time signal. Alternatively, reference time generator702can comprise any of a variety of reference time generators capable of generating a reference time signal of sufficient count resolution to be able to facilitate performance of the RF PLL synchronization disclosed herein.

The RF PLL register704is configured to store, specify, or define a particular reference time signal count value (e.g., a pre-defined count value) associated with resetting a sigma delta modulator (SDM) included in a RF PLL718of the RF module714. RF PLL register704is also referred to as an Lx_RF_PLL register. If the reference time signal comprises the first level reference time signal (L1_reference_time), then the particular reference time signal count value stored in the RF PLL register704comprises a particular first level reference time signal count value (L1_RF_PLL). If the reference time signal comprises the second level reference time signal (L2_reference_time), then the particular reference time signal count value stored in the RF PLL register704comprises a particular second level reference time signal count value (L2_RF_PLL). Likewise, if the reference time signal comprises the modified second level reference time signal (modified L2_reference_time), then the particular reference time signal count value stored in the RF PLL register704comprises a particular modified second level reference time signal count value (modified L2_RF_PLL).

In some embodiments, RF PLL718included in RF module714as well as the RF PLLs included in each of the remaining IC chips100are started and once they have reached a locked state (e.g., have reached a steady operational state), a synchronization between the RF PLLs in the plurality of IC chips100can occur. The synchronization request is initiated via an update to a slave interface or synchronization trigger signal. The readiness of the RF PLLs of the IC chips100to be synchronized can be indicated by a particular value of the synchronization trigger register710. As an example, the register value of register710can transition from a “0” to a “1” in accordance with the synchronization request.

Comparator706is configured to determine if the reference time signal equals the pre-defined count value stored in the RF PLL register704. The output of the comparison is provided to the state machine708. The state machine708is configured to receive the value of the synchronization trigger register710, also referred to as a control register. If the reference time signal equals the pre-defined count value of the RF PLL register704and the value of the synchronization trigger register710is indicative of a synchronization request or readiness, then the state machine708is configured to generate and provide a particular signal to the RF PLL718via the flip flops712. The particular signal provided to the RF PLL718can be any signal that is recognized by the RF PLL718as the command to perform synchronization. In some embodiments, without limitation, the particular signal comprises a four refclk clock cycle pulse (e.g., a signal high comprising a pulse width of four periods of the reference clock signal generated by the reference clock110). Such particular signal is also referred to as an LxSYNC signal, an Lx time synchronization signal, an Lx time digital synchronization reset, a sync input signal, and/or the like. If both conditions are not met, the state machine708is configured to provide no signal or a signal that is not the particular signal to RF PLL718.

A state machine included in each of the remaining IC chips100is similarly configured to provide a particular signal to the respective RF PLL included in each of the remaining IC chips100. All the RF PLLs in the IC chips100can be simultaneously synchronized using particular signals in the IC chips100that are generated at the same time in accordance with the same reference time signal. In some embodiments, flip flops712comprise one or more flip flops configured to reduce latency of providing the particular signal to RF PLL718, to facilitate generation of the particular signal, and/or to facilitate providing the particular signal to RF PLL718in synchronicity with the RF PLLs in the remaining IC chips100.

RF module714includes a signal processing unit716, the RF PLL718, and a transmit section720. The signal processing unit716is configured to receive the reference clock signal (sinus_refclk) from the reference clock110and to process the signal into a format usable by other circuits/components of section700. Among other things, signal processing unit716can convert the reference clock signal (sinus_refclk), which comprises a sinusoidal waveform shape, into the converted reference clock signal (refclk) having a square waveform shape. The converted reference clock signal (refclk) can be provided, without limitation, to each of the clock tree730and RF PLL718.

RF PLL718is electrically coupled to the transmit section720. Transmit section720includes baseband processing and RF processing subsections associated with encoding one or more data signals for RF transmission. Transmit section720includes, among other things, a plurality of phase shifters722to facilitate signal encoding and/or beamforming. Transmit section720can be similar to transmit section504. The particular signal to the RF PLL718from the state machine708is used to synchronize the phases of the RF PLL718. Similar reference time signal synchronizes phase shifters722with the phases of the phase shifters in the other IC chips100. Accordingly, even though a distributed PLL scheme is implemented in the plurality of IC chips100, precise phase synchronization between the phase shifters in the plurality of IC chips100is possible.

The converted reference clock signal (refclk) is provided to each of the state machine708and reference time generator702via the clock tree730. Clock tree730is configured to reduce latency in the provision of the converted reference clock signal (refclk) to its intended recipients.

FIG.8is an example illustration of a block diagram showing circuitry or electrical components included in the RF PLL718in accordance with some embodiments of the present disclosure. In some embodiments, RF PLL718includes a reference divider/multiplier800, a phase detector802, a loop filter804, a voltage controlled oscillator (VCO)806, a frequency divider808, and a sigma delta modulator (SDM)810. The input to the RF PLL718is received by the reference divider/multiplier800. The phase detector802is electrically coupled between the reference divider/multiplier800and the loop filter804. The loop filter804is electrically coupled between the phase detector802and VCO806. The output of VCO806comprises the output of the RF PLL718and also comprises an input to the phase detector802via the frequency divider808. A first feedback loop is thereby formed comprising the phase detector802, loop filter804, VCO806, and frequency divider808. The output of frequency divider808comprises the input to SDM810. The output of SDM810comprises the input to frequency divider808. Frequency divider808also generates the clock for the SDM810.

RF PLL718is configured to be an integer-N PLL and/or a fractional-N PLL. Depending on the parameters associated with frequency divider808and SDM810, the frequency of the output signal of RF PLL718comprises an integer multiple or a non-integer multiple of the frequency of the input signal. Reference divider/multiplier800is configured to apply a certain divider or multiplier value to the input signal so as to obtain a reference signal. The phase detector802is configured to detect differences in the phase associated with the reference signal (the first signal) and the phase associated with the output of VCO806with the frequency divider ratio applied in accordance with frequency divider808(the second signal), and generates a (voltage) signal in accordance with the phase difference between the two signals. The phase detector802is also referred to as a phase comparator.

Loop filter804is configured to filter the output from the phase detector802to facilitate maintaining RF PLL stability. VCO806is configured to oscillate at a higher frequency than the reference signal. VCO806is tunable over an operational frequency band associated with the loop. The output of the loop filter804(e.g., the filtered error signal indicative of the phase difference) is applied to VCO806as the tuning voltage of VCO806. The frequency associated with the output signal of VCO806is tuned or defined in accordance with the output of the loop filter804.

Frequency divider808is configured to change the frequency of the signal from VCO806using a divider ratio selected via the SDM810. The divider ratio N, also referred to as the divider or ratio, is applied as 1/N or ÷N to the signal from VCO806to generate a signal having a frequency that is the frequency of the signal from VCO806divided by N. Such frequency divided signal comprises the second signal received by phase detector802.

If the output of VCO806comprises N times the frequency of the input signal, then the frequency divider808has a ratio of 1/N, near 1/N, or other ratio at that point in time. The divider ratio of the frequency divider808can change over time in accordance with the SDM810. The divider ratio of frequency divider808can vary over time just so long as the average frequency of the output signal over time is the desired frequency of the output signal.

Initially, the RF PLL718will be out of lock as the first and second signals will not be the same. When the two signals become equal in phase and frequency over time, the error signal (the output of phase detector802) will be constant and the RF PLL718is considered to be in a locked state. When all the RF PLLs in the plurality of IC chips100are in a locked state, register710in each of the IC chips100transitions to a value indicative of the readiness of the RF PLLs for synchronization.

FIG.9is an example illustration of a block diagram showing additional circuitry or component details of the RF PLL718in accordance with some embodiments of the present disclosure. In some embodiments, frequency divider808includes a plurality of modulators such as modulators900,902,904, and906. Each of modulators900-906is configured to select a particular divider value under control by the SDM810. Modulator902is electrically coupled between modulators900and904. Modulator904is electrically coupled between modulators902and906. SDM810is electrically coupled to each of modulators900-906. Modulators900-906is also referred to as selective divider modulator, divider modulators, and/or the like.

Each of modulators900,902, and904comprises divider I or I+1 (denoted as 1/I+1), where I is an integer. Modulator906comprises an integer divider between P to Q (denoted as P:1:Q), where P and Q are integers, P<Q, and I or I+1 can equal P. This combination is an example and other combinations of integer dividers can be also used. SDM810comprises a sigma-delta random number generator or sequence configured to specify the configuration of modulators900-906so as to define the divider ratio of the feedback divider808to apply in the first feedback loop. The sigma-delta sequence maps to selection of particular divider values in modulators900-906. The modulator sequence of modulators900-906comprises the divider ratio of the feedback divider808. The divider ratio can range between I*I*I*P to (I+1)*(I+1)*(I+1)*Q. The modulator sequence of the feedback divider808changes as the sigma-delta sequence of the SDM810changes.

For instance, divider I is selected in modulator900, divider I is selected in modulator902, divider I+1 is selected in modulator904, and divider P+2 is selected in modulator906in accordance with the SDM810. The modulator sequence thus defined is a divider ratio value equal to I*I*(I+1)*(P+2).

The modulator sequence of the feedback divider808changes as the sigma-delta sequence of the SDM810changes over time. The divider ratio at a given moment in time need not equal the desired divider ratio as long as the average divider ratio over a given time equals the desired divider ratio. The divider ratio at any given moment in time can be an integer value while the average divider ratio is a non-integer value. As an example, assume the desired divider ratio is 10.1 (a fractional mode value). In 1000 cycles of the first feedback loop, 90% of the divider ratio of feedback divider808is 10 and in the remaining 10% of the 1000 cycles, the divider ratio is 11. The average divider ratio over the 1000 cycles is 10.1=0.9*10+0.1*11.

In some embodiments, a synchronization unit908electrically coupled to SDM810is configured to receive signals associated with operation of SDM810. Alternatively, synchronization unit908can be included in SDM810. Examples of signals received by synchronization unit908include, without limitation, a SDON signal910to control the on and off states of SDM810, the LxSYNC signal912to initiate synchronization of SDM810, and a LxSYNCEN signal914to effect synchronization of SDM810when in fractional mode. The SDON signal910can be set to “0” or “1” to have SDM810in the off or on state, respectively. The LxSYNC signal912comprises the particular signal generated by the state machine708if both conditions are met. As shown inFIG.9, LxSYNC signal912comprises a pulse that is four refclk clock cycles or period wide. The LxSYNCEN signal914comprises an enable bit control signal that transitions from a low to a high prior to the LxSYNC signal912. In some embodiments, both the LxSYNC signal912and LxSYNCEN signal914are enabled for SDM810synchronization to occur in fractional mode. The LxSYNC signal912alone is sufficient to initiate synchronization of SDM810in integer mode. Alternatively, the LxSYNC signal912is sufficient to initiate synchronization for fractional and integer modes of RF PLL718.

Accordingly, the SDM of the RF PLL included in each chip of the IC chips100is synchronized to each other using the reference time signal. The reference time signal generated in each of the IC chips100is highly synchronized between the IC chips100as described above. Thus, the synchronization of the SDMs occurs simultaneous or nearly simultaneously of each other. The synchronization causes all the SDMs of the RF PLLs in the IC chips100to reset to the same point or value of the same sigma-delta sequence at the same (or near same) time so that, in turn, the same modulator sequence occurs in all the feedback dividers of the RF PLLs from that time onward. The same modulator sequence in all IC chips100results in setting the outputs of the RF PLLs across the IC chips100to the same frequency multiplier. In this manner, the RF PLLs, although distributed across the plurality of IC chips100, perform in synchronicity with each other, enabling alignment of other chip functions such as the phases of the phase shifters between IC chips100.

FIG.10is an example illustration of divider ratios over time in a plurality of IC chips100in accordance with some embodiments of the present disclosure. Plot1000shows the sequence of divider ratios associated with a first chip after implementation of the LxSYNC signal, and plot1002shows the sequence of divider ratios associated with a second chip different from the first chip after implementation of the LxSYNC signal. Notice the synchrony or sameness of the divider ratios between the first and second chips as a function of time following the SDM synchronization operation. Prior to synchronization, plots1000and1002would be offset from each other along the time axis.

In this manner, the SDMs in the RF PLLs can be reset or synchronized between the IC chips100using the same reference time signal generated in each of the IC chips100. The same reference time signals in the IC chips100is based on a same cycle of a common reference clock. In each chip of the IC chips100, a particular reference time count value at which the SDM is to be reset or synchronized is pre-set. The pre-set particular reference time count value is the same in all the IC chips100. In each chip of the IC chips100, the RF PLL is started and permitted to continue running.

Once the RF PLL has achieved a locked state, a signal indicative of the locked state or readiness for synchronization is provided to a component included in the chip. In each chip of the IC chips100, a synchronization trigger signal is generated (by the state machine) if the current reference time signal equals the pre-set particular reference time count value and there is a signal indicative of the RF PLL locked state/readiness of synchronization. The synchronization trigger signal comprises any signal recognized by the SDM as a trigger to initiate the reset or synchronization. As an example, without limitation, the synchronization trigger signal can comprise a pulse having a pulse width comprising a particular multiple of the reference clock cycle (e.g., a four refclk clock cycle pulse).

In response to the synchronization trigger, the same sigma-delta sequence included in each of the SDMs is reset or synchronized to the same point or value. Henceforth, the RF PLLs in the IC chips100will have the same divider ratio sequences and, by extension, the RF PLLs will also have the same frequency multiplier at its outputs. Prior to the synchronization operation, different starting points of the sigma-delta sequence may occur within the SDMs at each given point in time, causing the corresponding divider ratio sequences in the feedback dividers to be offset from each other.

In some embodiments, the plurality of IC chips100and the present disclosure herein can be included in a communications system, a wireless communications system, a satellite-based communications system, a terrestrial-based communications system, a non-geostationary (NGO) satellite communications system, a low Earth orbit (LEO) satellite communications system, one or more communication nodes of a communications system (e.g., satellites, user terminals associated with user devices, gateways, repeaters, base stations, etc.), and/or the like.

Examples of the devices, systems, and/or methods of various embodiments are provided below. An embodiment of the devices, systems, and/or methods can include any one or more, and any combination of, the examples described below.

Example 1 is an apparatus including a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal, wherein the second IC chip is electrically coupled between the first and third IC chips, wherein the first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal, wherein the first, second, and third IC chips include a respective first, second, and third phase lock loop (PLL), and wherein the first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals.

Example 2 includes the subject matter of Example 1, and further includes wherein the first, second, and third reference time signals are generated within a same first particular cycle of the reference clock signal, wherein synchronization of the first, second, and third PLLs is initiated during a same second particular cycle of the reference clock signal, and wherein the first particular cycle of the reference clock signal is a different cycle than the second particular cycle of the reference clock signal.

Example 3 includes the subject matter of any of Examples 1-2, and further includes wherein the first, second, and third PLLs include respective first, second, and third sigma delta modulators (SDMs), and wherein the first, second, and third SDMs include a same sigma-delta sequence.

Example 4 includes the subject matter of any of Examples 1-3, and further includes wherein the first, second, and third PLLs comprise radio frequency (RF) PLLs, and wherein the first, second, and third PLLs include respective first, second, and third sigma delta modulators (SDMs).

Example 5 includes the subject matter of any of Examples 1-4, and further includes wherein the first, second, and third PLLs include respective first, second, and third sigma delta modulators (SDMs) and respective first, second, and third feedback dividers, and wherein the first, second, and third SDMs control a divider ratio associated with the respective first, second, and third feedback dividers.

Example 6 includes the subject matter of any of Examples 1-5, and further includes wherein the first, second, and third PLLs include respective first, second, and third sigma delta modulators (SDMs), and wherein synchronization of the first, second, and third PLLs comprises synchronizing the first, second, and third SDMs to each other.

Example 7 includes the subject matter of any of Examples 1-6, and further includes wherein the first, second, and third PLLs include respective first, second, and third sigma delta modulators (SDMs), wherein the first, second, and third SDMs include a same sigma-delta sequence, and wherein synchronization of the first, second, and third PLLs comprises synchronizing a starting point of the sigma-delta sequence in the first, second, and third SDMs to each other.

Example 8 includes the subject matter of any of Examples 1-7, and further includes wherein the first IC chip is configured to generate a synchronization signal to trigger phase synchronization of the first PLL to the second and third PLLs if the first reference time signal equals a pre-set reference time signal count value and the first PLL is in a locked state.

Example 9 includes the subject matter of any of Examples 1-8, and further includes wherein the synchronization signal comprises a first synchronization signal, and wherein the second IC chip is configured to generate a second synchronization signal to trigger phase synchronization of the second PLL to the first and third PLLs if the second reference time signal equals the pre-set reference time signal count value and the second PLL is in a locked state.

Example 10 includes the subject matter of any of Examples 1-9, and further includes wherein the first PLL includes a feedback divider electrically coupled to a sigma delta modulator (SDM), and wherein the SDM is configured to define a divider ratio sequence of the feedback divider.

Example 11 includes the subject matter of any of Examples 1-10, and further includes wherein the SDM includes a sigma-delta sequence, and wherein the divider ratio sequence is a function of the sigma-delta sequence.

Example 12 includes the subject matter of any of Examples 1-11, and further includes wherein the feedback divider comprises a plurality of selective divider modulators, and wherein a first selective divider modulator of the plurality of selective divider modulators is different from a second selective divider modulator of the plurality of selective divider modulators.

Example 13 includes the subject matter of any of Examples 1-12, and further includes wherein each of the first, second, and third PLLs comprises one or both of an integer mode PLL or a fractional mode PLL.

Example 14 includes the subject matter of any of Examples 1-13, and further includes wherein at least two of the first, second, or third IC chips are identical to each other.

Example 15 includes the subject matter of any of Examples 1-14, and further includes wherein at least two of the first, second, or third IC chip are different from each other.

Example 16 includes the subject matter of any of Examples 1-15, and further includes wherein the first IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal, wherein the first IC chip is further configured to generate a fourth reference time signal based on the first reference time signal and the second reference clock signal, wherein the fourth reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal, and wherein the first PLL is synchronized based on the fourth reference time signal.

Example 17 includes the subject matter of any of Examples 1-16, and further includes wherein the fourth reference time signal has a finer count resolution than the first reference time signal within a same time period.

Example 18 is an apparatus including a first integrated circuit (IC) chip including a first phase lock loop (PLL), wherein the first PLL includes a first sigma delta modulator (SDM); a second IC chip including a second PLL, wherein the second PLL includes a second SDM; a third IC chip including a third PLL, wherein the third PLL includes a third SDM and the second IC chip is electrically coupled between the first and third IC chips; and a reference clock configured to generate and provide a reference clock signal to each of the first, second, and third IC chips, wherein the first, second, and third SDMs are reset based on the reference clock signal.

Example 19 includes the subject matter of Example 18, and further includes wherein the first, second, and third SDMs are reset based on a same particular cycle of the reference clock signal and when the first, second, and third PLLs are in a locked state.

Example 20 includes the subject matter of any of Examples 18-19, and further includes wherein the first, second, and third SDMs include a same sigma-delta sequence, and wherein resetting of the first, second, and third SDMs comprises aligning the sigma-delta sequence between the first, second, and third SDMs.

Example 21 includes the subject matter of any of Examples 18-20, and further includes wherein: the first IC chip is configured to receive a timing signal and the reference clock signal, the second IC chip is configured to receive the timing signal from the first IC chip and the reference clock signal, the third IC chip is configured to receive the timing signal from the second IC chip and the reference clock signal, the first, second, and third IC chips are configured to generate first, second, and third reference time signals based on the timing signal and the reference clock signal, and wherein resetting the first, second, and third SDMs comprises resetting based on the respective first, second, and third reference time signals.

Example 22 includes the subject matter of any of Examples 18-21, and further includes wherein the first, second, and third reference time signals are generated within a same particular cycle of the reference clock signal.

Example 23 includes the subject matter of any of Examples 18-22, and further includes wherein the first IC chip is configured to generate a first reference time signal based on a timing signal and the reference clock signal, wherein the first IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal, wherein the first IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal, wherein the second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal, and wherein the first SDM is reset based on the second reference time signal.

Example 24 includes the subject matter of any of Examples 18-23, and further includes wherein the second reference time signal has a finer count resolution than the first reference time signal for a same time period.

Example 25 includes the subject matter of any of Examples 18-24, and further includes wherein the reference clock signal comprises a first reference clock signal, wherein an IC chip, comprising any of the first, second, or third IC chip, includes a first counter configured to generate, based on a timing signal and the first reference clock signal, a first reference time signal indicative of a count of periods of the first reference clock signal, wherein the IC chip includes a second reference clock configured to generate a second reference clock signal having a second frequency different from a first frequency associated with the first reference clock signal, wherein the IC chip includes a clock generator configured to generate, based on the first reference clock signal, the second reference clock signal, and a phase selection, a third reference clock signal having a third frequency or phase shift different from the second reference clock signal, wherein the IC chip includes a second counter configured to generate a third reference time signal indicative of sub-periods of the third reference clock signal in accordance with the phase selection, and wherein a SDM included in the IC chip is reset using the third reference time signal.

Example 26 includes the subject matter of any of Examples 18-25, and further includes wherein the second frequency is greater than the first frequency and the third frequency is less than the second frequency.

Example 27 includes the subject matter of any of Examples 18-26, and further includes wherein the third reference time signal indicates a number of phase increments for each period of the third reference clock signal that is 360 divided by a phase increment associated with the phase selection.

Example 28 is a radio frequency (RF) phase lock loop (PLL) including an output line; a phase detector electrically coupled to the output line; a frequency divider configured to form a feedback loop between the output line and the phase detector, the feedback divider having a divider ratio; and a sigma delta modulator (SDM) electrically coupled to the frequency divider, the SDM including a sigma-delta sequence configured to define the divider ratio, wherein a particular cycle of a reference clock signal resets the sigma-delta sequence to a particular sequence point.

Example 29 includes the subject matter of Example 28, and further includes wherein the divider ratio comprises a fractional divider ratio or an integer divider ratio.

Example 30 includes the subject matter of any of Examples 28-29, and further includes wherein the RF PLL is included in a first integrated circuit (IC) chip, further comprising a second RF PLL included in a second IC chip, the second RF PLL including a second frequency divider and a second SDM, the second frequency divider including a second divider ratio, the second SDM including a second sigma-delta sequence configured to define the second divider ratio, and wherein the sigma-delta sequence and the second sigma-delta sequence are synchronized to a same sequence point based on the particular cycle of the reference clock signal.

Example 31 includes the subject matter of any of Examples 28-30, and further includes wherein the particular cycle of the reference clock signal is identified in accordance with a count of cycles of the reference clock signal, and wherein the count had a count resolution that is greater than a periodicity of the reference clock signal.

Although certain embodiments have been illustrated and described herein for purposes of description, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments described herein be limited only by the claims.