Patent ID: 12194884

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the following description to refer to the same or similar parts. While several illustrative embodiments are described herein, modifications, adaptations and other implementations are possible. For example, substitutions, additions, or modifications may be made to the components and steps illustrated in the drawings, and the illustrative methods described herein may be modified by substituting, reordering, removing, or adding steps to the disclosed methods. Accordingly, the following detailed description is not limited to the disclosed embodiments and examples. Instead, the proper scope of the invention is defined by the appended claims.

Embodiments of the present disclosure are directed to a novel battery management system and its application, in which a plurality of battery cells are individually monitored and controlled without a complex web of wires. The battery management system allows each battery cell to communicate with a central controller using the cables that are already placed on the battery cells. Another aspect of the present disclosure is directed to an integrated vehicle power system.

FIG.1is a schematic diagram illustrating an exemplary embodiment of an overall system100utilizing a battery management system (BMS)200, consistent with disclosed embodiments. As used herein, overall system100may represent a wide range of applications, such as electric vehicles, hybrid vehicles, building power reserve systems, or any other systems that can be powered partially or entirely by one or more batteries. Other applications are also within the scope of disclosed embodiments, in which different types of battery cells (e.g., lithium-ion batteries, NiMH batteries, NiCd batteries, or the like) and other types of individually packaged power sources, such as fuel cells, are used.

Overall system100includes a main control system110, a number of subsystems (e.g., subsystems A-C111-113), and BMS200. In some embodiments, BMS200may be one of the subsystems coupled with main control system110and other subsystems to operate overall system100. As used here, references to subsystems A-C111-113are intended to cover any number of systems, subsystems, modules, and devices in communication with main control system110.

In an embodiment in which overall system100corresponds to an electric vehicle, main control system110may correspond to an electronic control unit (ECU) for controlling various electronic systems of the vehicle, such as transmission, cruise control, steering, audio systems, charging, and/or other functionalities in the vehicle controlled by electronic components. Alternatively, main control system110may correspond to a vehicle control unit (VCU) for controlling torque coordination, operation and gearshift strategies, high-voltage and low-voltage coordination, charging control, on board diagnosis, thermal management, and/or other functionalities associated with powertrains. Each of the functionalities enumerated above may be implemented by subsystems (e.g., subsystems A-C111-113).

In some embodiments, each of main control system110, subsystems A-C111-113, and BMS200may comprise a processor (not shown), a memory (not shown), input/output (I/O) ports (not shown), and other electrical components suitable for their intended purposes.

The processor may include one or more dedicated processing units, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or various other types of processors or processing units. The processor may be configured to perform computations on signals processed via the I/O ports. The processor may be further configured to control other connected systems and subsystems by transmitting messages via the I/O ports.

The memory may be any type of computer-readable storage medium including volatile or non-volatile memory devices, or a combination thereof. The memory may store computer-readable program instructions, mathematical models, and/or algorithms that are used in signal processing. The memory may further store computer-readable program instructions for execution by the processor to perform its intended purposes.

The I/O ports may include various ports, interfaces, antennae suitable for interfacing with another system, subsystem, sensor, module, or device. One type of I/O port may include an array of individual ports on a circuit board configured to transmit and receive digital data communication or analog signals. Another type of I/O port may include ports that are connected to sensors such as a temperature sensor, touch sensor, humidity sensor, or the like for acquiring a measurement of surrounding environment. Yet another type of I/O port may include ports connected to output devices and input devices. The output devices may be used to report a result of the processor's activities to a user or another device. The output devices may include a user interface including a display or an auditory device such as a speaker. The display may be configured to display a result of the processor's activities, a status of various systems, subsystems, modules, and/or sensors, data stored at the memory, etc. The display may include, but is not limited to, cathode ray tube (CRT), liquid crystal display (LCD), light-emitting diode (LED), gas plasma, a touch screen, or other image projection devices for displaying information to a user. Additionally or alternatively, the display may include one or more LEDs that turn on or off or change color to represent different states. The input devices may be any type of computer hardware equipment used to receive data and control signals from a user. The input devices may include, but are not limited to, a keyboard, a mouse, a scanner, a digital camera, a joystick, a trackball, cursor direction keys, a touchscreen monitor, audio/video commanders, a switch, a button, graphical user interface (GUI) elements displayed on a display, etc. The I/O ports may further include a machine interface, such as an electrical bus connection or a wireless communications link configured to transfer data between two computer-implemented systems.

BMS200, in some embodiments, includes a battery management controller (BMC)500and an array of battery cells230-1to230-N producing high voltage (HV) direct current (DC) voltage. Each battery cell may have a battery management board (BMB)600installed thereon. The array of battery cells230-1to230-N is referred to herein collectively as battery cells230or individually as battery cell230. BMC500and battery cells230are connected by HV data cables221, HV bus bars222, and HV power cables223.

BMC500is configured to monitor and control battery cells230via HV data cables221and HV bus bars222, without the need for any other wires connecting BMC500directly to each battery cell230(or BMB600described below). HV bus bars222refer to the electrical connectors coupling positive and negative terminals of battery cells230except for one positive terminal (i.e., a most positive terminal211-1) and one negative terminal (i.e., a most negative terminal212-N) at each end of the array of battery cells230. Therefore, BMS200of the present disclosure adds only two cables (i.e., HV data cables221) to an array of battery cells230, while still allowing each battery cell230to be monitored. In some embodiments, BMC500may also be configured to analyze, process, and relay information on battery cells230to main control system110and subsystems A-C111-113.

Because of this ability to communicate with individual BMB600in each battery cell230using just two cables (i.e., HV data cables221), BMS200is able to interface with hundreds (e.g., up to 1024) or even thousands (e.g., up to 4096) of battery cells230without additional cables. An engineer would be able to interface BMC500to a different number of battery cells230just by adding or removing a desired number of battery cells230and connecting their positive and negative terminals with additional HV bus bars222. All other aspects of BMS200(e.g., communication protocol, HV data cables221, HV power cables223) can remain the same without affecting their functionality. Interfacing with even more battery cells230is also possible by changing communication protocol in software, which is also within the scope of the present disclosure.

For purposes of description, battery cells230includes N number of battery cells230, that number being scalable up or down based on user need without adding to the electrical complexity of BMS200. Battery cells230may be connected in series, in parallel, or in any configuration that can provide desired levels of voltage and current, as will be described below with respect toFIGS.3A-3C. In some embodiments, each battery cell230is capable of providing 1.8V to 5.0V DC, which may combine to provide HV DC voltage on the order of a few hundred volts (e.g., 350V or 480V) or even above 1000V (e.g., 1500V). This HV DC voltage is present on the electrical connections coupled to battery cells230(I.e., HV data cables221, HV bus bars222, and HV power cables223). The cables carrying this HV DC voltage are denoted inFIGS.1,2A-2C, and7as bolded lines. Other voltages for individual battery cell230(i.e., lower than 1.8V or higher than 5.0V can also be utilized and are within the scope of disclosed embodiments. Other levels of HV DC voltage are also within the scope of disclosed embodiments, where different number of battery cells230may be coupled to output any desired HV DC voltage.

As seen inFIGS.1,2A-2C, and7, the HV DC voltage is confined to select components of overall system100. These include BMC500, battery cells230, and a HV system120, such as an electric motor or any other system that is powered by battery cells230. While there may be other systems, subsystems, and devices not shown inFIG.1, not all components of overall system100are coupled to receive the HV DC voltage. Instead, the other components of overall system100may be powered by a lower voltage power source such as a 12V lead-acid battery found in conventional vehicles. Other lower voltage power sources of any voltage are also within the scope of disclosed embodiments.

Further, the components powered by the lower voltage power sources may be shielded from the HV DC voltage with isolating circuits. This is because powering every component using the HV DC voltage may be costly and dangerous. A short circuit in a device connected to receive or carry the HV DC voltage, for example, may cause irreparable damage to the connected device or to the user. As a further protection, all circuits of BMS200may be protected from incorrectly connected power sources, such that the circuit will not be damaged even when a power source is connected in with reverse polarity (e.g., a positive cable connected to a negative terminal).

Each battery cell (e.g.,230-1) comprises a BMB (e.g., BMB600-1), collectively BMBs600, configured to monitor the status of a single battery cell (e.g., battery cell230-1) to which it is coupled. While one BMB600is preferably coupled to each battery cell230in a one-to-one correspondence, other ratios of BMBs600to battery cells230are also within the scope of disclosed embodiments. As with BMC500, each BMB600may be configured to communicate with BMC500via HV data cables221and HV bus bars222, without the need for any other cables connecting BMB600directly to BMC500or to any other BMB600.

In addition, while it may be possible to eliminate excessive wires by configuring each component of the battery management system (e.g., BMC500and BMBs600) to communicate wirelessly using radiofrequency (RF) or Bluetooth signals, such wireless communication may cause problems. For example, the wireless signals can interfere with each other and with other wireless signals such as cellular, radio, and WIFI signals.

HV data cables221, HV bus bars222, and HV power cables223carry the HV DC voltage and are illustrated as such with thick lines. These HV connections are coupled to positive terminals211(i.e., cathodes) and negative terminals212(i.e., anodes) of battery cells230. Specifically, HV data cables221connect BMC500to most positive terminal211-1and most negative terminal212-N of battery cells230. HV bus bars222connect positive terminals and negative terminals of battery cells230in sequence based on different configurations described below with respect toFIG.3A-3C. HV power cables223also connect HV system120to most positive terminal211-1and most negative terminal212-N of battery cells230.

Because each set of cables—HV data cables221, HV bus bars222, and HV power cables223—are essentially three parallel sets of cables coupling most positive terminal211-1and most negative terminal212-N of battery cells230, these three types of cables carry the same voltage at any given moment in time. Nonetheless, BMC500, BMBs600, and HV system120are configured to extract data signals traveling in the cables without interference, as will be described below.

FIG.2is a perspective view of BMS200, consistent with disclosed embodiments. As described above, BMS200comprises BMC500, battery cells230-1to230-N, HV data cables221, HV bus bars222, and HV power cables223. As also described above and illustrated inFIG.2, HV data cables221, HV bus bars222, and HV power cables223are the only electrical connections necessary to achieve the functions of BMS200described herein.

FIG.3Ais a top-down view of BMS200having battery cells230connected in series, consistent with disclosed embodiments. BMC500is shown with HV data cables221connected to most positive terminal211-1and most negative terminal212-N of battery cells230. Individual HV bus bars222are also shown connecting each adjacent pair of positive terminal (e.g., positive terminal211-2of battery cell230-2) and negative terminal (e.g., negative terminal212-1of battery cell230-1). In this way, BMC500, and positive terminals211and negative terminals212of battery cells arranged in series, form a closed loop connected by HV data cables221and HV bus bars222.

FIG.3Bis a top-down view of another exemplary array of battery cells230connected in parallel, consistent with disclosed embodiments. The illustrated components are similar to those ofFIG.3Aexcept for the arrangement of positive terminals211and negative terminals212of battery cell230as well as HV bus bars222connected between adjacent terminals of the same polarity (e.g., negative terminal212-1and negative terminal212-2). Battery cells230-1,230-2, etc. ofFIG.3Aare arranged so that positive terminals and negative terminals alternate ( . . . +, −, +, − . . . ), whereas battery cells230-1,230-2, etc. ofFIG.3Bare arranged so that positive terminals211are arranged adjacent to each other on one side of the battery cell array and negative terminals212are arranged adjacent to each other on the other side of the battery cell array.

FIG.3Cis a top-down view of another exemplary array of battery cells230connected in series and in parallel, consistent with disclosed embodiments. Similar toFIGS.3A and3Bexcept for the arrangement of the terminals and how HV bus bars222are connected,FIG.3Cshows HV bus bars222connecting same polarity terminals of battery cells230connected in parallel (negative terminals212-1and212-2of battery cells230-1and230-2; and positive terminals211-3and211-4of battery cells230-3and230-4), and connecting the two sets of terminals (negative terminals212-1and212-2; and positive terminals211-3and211-4) together to connect the two sets of battery cells (battery cells230-1and230-2; and battery cells230-3and230-4) in series. It is noted that such a hybrid arrangement of battery cells230cannot be achieved in conventional battery management systems connecting a conventional BMC to individual conventional BMBs directly, since the wires and the signals traveling therein would interfere with each other.

FIGS.4A-4Dare different views of exemplary battery cells230of different embodiments for coupling BMB600to a battery cell230, consistent with disclosed embodiments. As described above, one BMB600is preferably coupled to each battery cell230. Even in other embodiments in which one BMB600is connected to a group of more than one battery cells230, the one BMB600may be installed on one of the battery cells230in a manner similar to that shown inFIGS.4A-4D.

FIG.4Ais a side view of an exemplary battery cell230with a slot240containing an exemplary BMB600, consistent with the disclosed embodiments. Here, slot240is positioned so that its opening extends into an external enclosure231of battery cell230and so that slot240is connected to the terminals of battery cell230internally via connections232. Using slot240to connect BMB600to battery cell230allows BMB600to be removable so that it can be replaced without having to replace the entire battery cell230. In some embodiments, slot240may be positioned on any side of external enclosure231, such as on top as shown inFIG.4A, the sides, or the bottom. Furthermore, slot240may be accessible from the outside without opening external enclosure231in some embodiments, while the opening of slot240may be covered by external enclosure231in others.

FIG.4Bis a side view of an upper portion of exemplary battery cell230ofFIG.4Awith BMB600positioned outside of slot240and intended for insertion into slot240, consistent with disclosed embodiments.

FIG.4Cis a top-down view of another exemplary battery cell230with slot240for receiving exemplary BMB600, consistent with disclosed embodiments. Here, slot240is positioned on a top portion of battery cell230and connected to the terminals externally via connections232. Slot240may be positioned anywhere on external enclosure231, such as on top as shown inFIG.4C, the sides, or the bottom.

FIG.4Dis a cross-sectional view of exemplary battery cell230ofFIG.4C, looking down into slot240, consistent with disclosed embodiments.

The circuit board of BMB600is shaped to fit slot240. The circuit board may also include one or more structural characteristics that allow BMB600to be inserted in only one correct orientation. The structural characteristics may include, for example, a notch or a mark at one particular corner, visual indications showing the correct orientation, or other structural characteristics known in the art. In further embodiments, the circuit board of BMB600may take the shape of a well-known form factor, such as a Secure Digital (SD) card or a microSD card. This may allow users to easily understand how to insert or replace BMB600.

FIG.5is a schematic diagram illustrating an exemplary embodiment of BMC500, consistent with disclosed embodiments. BMC500may be configured to acquire, manage, and/or monitor information related to the health of battery cells230. For example, BMC500may be configured to keep track of voltage, resistance, current, temperature, discharge and charge limits, charge balancing, and/or other information related to battery cell performance and health.

To this end, BMC500may be configured to poll all BMBs600periodically and refresh the information of each battery cell230based on each poll. In some embodiments, BMC500may poll all BMBs600in sequence from battery cell230-1to battery cell230-N and continue to cycle through all BMBs600over and over. The total time it takes to poll every BMBs600and receive responses is based on the particular communication protocol employed by BMS200. For example, BMS200comprising 1024 battery cells230(i.e., battery cell230-1to battery cell230-1024) and communicating at 256,000 bits per second may cycle through all BMBs in as little as 4 seconds.

In other embodiments, BMC500may be configured to operate in four operating modes—discharge, charge, idle, and sleep. The discharge mode may be considered a default operating mode, where BMC500continuously monitors BMBs600and HV system120is powered by battery cells230. During charge mode, BMC500may actively charge battery cells230and continuously poll BMBs600to monitor statuses of battery cells230. Additionally or alternatively, BMC500may be configured to poll BMBs600at predetermined intervals during discharge mode or charge mode instead of polling them continuously. In some embodiments, BMC500may also control charge shunting of BMBs600and the output of an external charger541for efficient and accurate cell balancing, as will be described below.

During idle mode, BMC500may instruct BMS200to operate in a low power idle mode, in which battery monitoring remains active but at reduced intervals. For example, BMC500may poll BMBs600every 1 minute in idle mode, instead of cycling through BMBs600continuously. In some embodiments, BMC500may further be programmed to enter sleep mode after five minutes in idle mode. Lastly, during sleep mode, BMC500may shut off entirely except for operation of a sleep controller550described below. Sleep controller550may wake up BMC500periodically to poll all BMBs600, run diagnostics, and notify a user or main system controller110of any problems.

As shown inFIG.5, BMC500comprises a BMC processor510, programmable I/O ports521, a controller area network (CAN) bus transceiver522, a display interface523, a current sensor530, a charger interface540, sleep controller550, a data storage560, and a BMB transceiver700.

BMC processor510may include one or more dedicated processing units, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or various other types of processors or processing units. BMC processor510may be configured to perform computations or perform tasks based on data received from sensors and other interfaces in communication with different systems, subsystems, and/or modules. For example, BMC processor510may be programmed to analyze voltage output from each battery cell230over time in order to identify any signs of wear or keep track of a number of charge cycles. BMC processor510may also be configured to control the other connected systems and subsystems by transmitting messages via the interfaces. For example, BMC processor510may detect that battery cells230are unable to output full power (e.g., due to cold weather) and send a message to main control system110to limit throttle of a vehicle powered by battery cells230.

Programmable I/O ports521may comprise programmable digital input receivers (not shown) and programmable digital output drivers (not shown). The programmable digital input receivers may be configured to receive information from the other connected systems and subsystems, while the programmable digital output drivers output information to the other connected systems and subsystems regarding various states of BMS200. For example, one output driver of programmable I/O ports521may correspond to the operational status of BMS200. This output driver may be connected to an LED, so that the LED turn on in green during normal operation, in red when there is a problem, and off when battery management system200is off. Other states of BMS200that may be output via programmable I/O ports521include, but not limited to, charging status of battery cells230, warning indicator for excessive battery cell temperature, or other measurements or statuses that can be represented by a simple indicator (e.g., LED, gauge, etc.).

CAN bus transceiver522may include a plurality of CAN bus transceivers be configured to allow BMS200to communicate more robustly with the other systems, subsystems, and/or modules through a CAN bus. The CAN bus may be configured to control communication traffic between different systems based on priority to allow more complex transmission of data as the different systems interoperate. In some embodiments, CAN bus transceiver522may include one or more bus channels, each dedicated to different CAN protocols (e.g., CANopen, DeviceNet, EnergyBus, ISO-TP, or other standardized messaging protocols). In further embodiments, CAN bus transceiver522may allow BMC500to be configured and monitored using a personal computer such as a laptop, PC, or other computing systems.

Display interface523is configured to connect to a display device (not shown) for communicating various states of BMS200. The display device may include, but is not limited to, cathode ray tube (CRT), liquid crystal display (LCD), light-emitting diode (LED), gas plasma, a touch screen, or other image projection devices for displaying information to a user. Additionally or alternatively, the display may include one or more LEDs that turn on or off or change colors to represent different states. Display interface523may comprise one or more standardized video interfaces such as VGA, DVI, HDMI, mini-DIN, SCART, HDI-45, DisplayPort, and the like.

Current sensor530is connected to one of HV power cables223to measure the current output from battery cells230. Any type of current sensors may be used, including hall effect current sensors, DC current sensors, Rogowski coils, split or solid core sensors, open or closed loop sensors, DC shunts, or any other type of sensor for measuring current. Current sensor530may allow an accurate and instantaneous reading of the current output, as an indicator of overall health of battery management system200. For example, a large current draw may indicate an overload of battery cells230to be addressed and prevent damage to connected systems and components. In some embodiments, BMC500may use the current sensor in conjunction with different measurements from BMBs600to assess the health of individual battery cells230. For example, a measurement of voltage output can be divided by a measurement of current to obtain battery resistance.

Charger interface540is an interface for connecting to an external charger541. Charger interface540and external charger541may utilize standardized charger connectors such as Type1and Type2chargers, CHAdeMO, Combined Charging System (CCS), or other charger connectors known in the art. Charger interface540may also accept and automatically switch between AC slow charging and DC fast charging protocols, as known in the art.

Sleep controller550is configured to control BMC500in sleep mode. Sleep controller550may be inactive when BMC500is in another operating mode and active when BMC500is in sleep mode. During sleep mode, sleep controller550may wake up BMC500periodically (e.g., every 1 hour) to check on battery cells230. Sleep controller550may put BMC500to sleep once the battery cell check is complete, thereby reducing power consumption significantly. In some embodiments, BMC500may consume only about 5 mA while sleeping, which allows BMS200to conserve energy and extend running time.

BMB transceiver700is a dedicated module for communicating with BMBs600installed on each battery cell230. BMB transceiver700may be constantly communicating with BMBs600or communicating at a predetermined interval under certain operating modes, as described above. Further structural and functional details of BMB transceiver700will be described below in more detail.

Data storage560may be any type of computer-readable storage medium including volatile or non-volatile memory devices, or a combination thereof. Data storage560may further comprise commercially available memory modules and storage devices such as flash memory, SSD, or HDD. Data storage560may also be integrated into BMC500as part of its circuit board or be modular and replaceable by a user.

Data storage560is configured to store information about battery cells230, which may include the measurements received from BMBs600and the information determined by BMC500described above. Data storage560may be shared by BMC processor510and BMB transceiver700, where BMB transceiver700continuously writes the information about battery cells230to data storage560as received from BMBs600and BMC processor510asynchronously retrieves the information as needed. Conversely, BMC processor510may store messages to BMBs600in data storage560, which may then be retrieved by BMC transceiver700and eventually transmitted to BMB600.

Having BMC processor510and BMB transceiver700communicate through data storage560without any direct connection results in separating BMB communication from the rest of the functions of BMC500. This allows uninterrupted, real time (or near real time) monitoring of battery cells230as BMC processor510does not need to devote any processing time to the BMB communication (which may take several seconds, as noted above).

In some embodiments, BMC500may also comprise a battery cell heater controller (not shown) and/or a battery cell cooler controller (not shown). Controlling temperature ensures proper operation of battery cells230, and there are many external and internal factors such as weather and prolonged use that affect temperature. The battery cell heater controller and the battery cell cooler controller may be configured to provide temperature control to battery cells230, so that battery cells230stay within an ideal operating temperature range. Many different heating and cooling modalities (e.g., fan, Peltier, liquid cooling system, resistance wires, thick film heaters, and the like) are available for interfacing with the battery cell heater controller and the battery cell cooler controller and are within the scope of disclosed embodiments.

FIG.6is a schematic diagram illustrating an exemplary embodiment of BMB600, consistent with disclosed embodiments. As described above, BMB600is a circuit board coupled to battery cell230and configured to manage various aspects of battery cell230. For example, BMB600may be configured to receive messages (e.g., requests for measurements or commands to control charge/discharge) from BMC500, measure current temperature and voltage of battery cell230, and adjust operational parameters such as discharge limit or charge limit.

BMB600is powered by battery cell230by connecting to positive terminal211and negative terminal212via connections232and does not require any external power source. As such, negative terminal212of battery cell230serves as a virtual ground of BMB600, and BMB600is not connected to a common ground of overall system100. This allows each BMB600to stay independent from the rest of BMS200, meaning that one BMB600need not be configured to communicate with other BMBs or be aware of the other BMBs in BMS200. Each BMB600is also free of any other wire connecting it to another component of BMS200or overall system100.

Consistent with disclosed embodiments, BMB600may not be connected to any other BMB600, BMC500, or power source (not shown) except for the two connections to positive terminal211and negative terminal212of battery cell230. In this way, each BMB600is a closed system of its own, which allow it to manage only the particular battery cell230it is connected to, keeping its functionalities relatively simple and minimizing power consumption. This also allows BMS200to significantly reduce the number of electrical connections needed to build an array of battery cells230. This, in turn, may allow significant savings in electrical complexity, thereby reducing cost of design, installation, and/or maintenance.

Turning to individual components, BMB600comprises a BMB processor610, a temperature sensor621, a voltage sensor622, an analog-to-digital (ADC) converter630, a cell balancing module640, and BMB transceiver700.

BMB processor610may include one or more dedicated processing units, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or various other types of processors or processing units. BMB processor610may be configured to perform computations or perform tasks based on data received from sensors or BMC500. For example, BMB processor610may acquire status information of battery cell230from associated sensors (e.g., temperature sensor621and/or voltage sensor622), determine discharge and charge limits, cell balancing, cell health, or any other information useful for assessing the health of battery cell230, and transmit them to BMC500via BMB transceiver700.

Temperature sensor621is configured to measure temperature of the particular battery cell230to which BMB600is connected. Temperature sensor621may be selected from any number of known temperature sensor modules, such as thermocouples, thermistors, integrated circuit (IC) temperature sensors, or the like. Similarly, voltage sensor622is configured to measure voltage output of the particular battery cell230to which BMB600is connected. Voltage sensor622may be selected from any number of known voltage sensor modules, such as capacitive type voltage sensors, resistive type voltage sensors, or the like. Other types of sensors for monitoring various aspects of battery cell230are also within the scope of the disclosed embodiments. BMB600may comprise such sensors in addition to or in place of temperature sensor621and voltage sensor622, of which descriptions will not be provided here for the sake of brevity.

In some embodiments, BMB processor610may use measurements from sensors to determine additional information about the status of battery cell230. For example, the temperature measurement may correspond to how much power battery cell230can provide. A correlation curve between temperature and discharge capacity may be unique to the type of battery cell230used in BMS200, but BMB processor610may be able to determine discharge capacity given a particular temperature and report it to BMC500, which may then use it to control other connected systems in the manner described above.

In other embodiments, BMB processor610may acquire and provide the temperature and voltage measurements to BMC500, and BMC processor510may be configured to determine the discharge capacity and other derivative parameters based on those measurements. For example, BMC processor510may use the voltage measurements from BMB processor610and measurements of current from current sensor530to determine the resistance of battery cell230connected to a particular BMB600. If the resistance is too high, BMC processor510may send a signal to main control system110or other subsystems (e.g., subsystems A-C111-113) to reduce power consumption (e.g., by reducing throttle of a vehicle).

ADC630is configured to convert an analog input into a digital output that can be read and understood by processing units such as BMB processor610. ADC630may be a dedicated IC or a functional unit inside either a sensor or BMB processor610. Here, ADC630may receive outputs from temperature sensor621and/or voltage sensor622, convert to a digital value proportional to a reference voltage (e.g., Vdd), and output the result to BMB processor610.

Capacities of individual battery cells230typically vary based on manufacturing variances, aging, impurities, and environmental exposure, which drift even further as battery cells230go through multiple charge and discharge cycles. Cell balancing module640is configured to compensate for such variation by allowing BMC500to charge individual battery cells230and/or individual battery cells within each battery cell230selectively based on their current capacity.

In some embodiments, BMC500uses information gathered from BMBs600to track the health of battery cells230. When BMC500detects a particular battery cell deviating from the overall state of battery cells230, BMC500may send a message to BMB600to control discharge and charge of battery cell230via cell balancing module640. In response, cell balancing module640controls charge shunting for the particular battery cell230to which it is connected by selectively connecting a shunt resistor (not shown) to deplete charge from the particular battery cell230until the voltage of the particular battery cell230matches the voltages of the other battery cells. The shunt resistor is sized to shunt a preset charging current when battery cell230is charged to a desired capacity. In some embodiments, the preset charging current may be 200 mA to 750 mA, and cell balancing module640may control the charge shunting to maintain voltages of battery cells230within a predetermined range of each other (e.g., ±5 mV).

Further, the ability for BMS200to interface with multiple battery cells230in series or in parallel while retaining control over individual battery cell230allows BMS200to control charge shunting for high current battery cells (e.g., 400 amp cells). Conventional systems are limited in their abilities to shunt high current battery cells due to the size of the shunt resistors therein and/or their electrical configuration requiring BMC500to control shunting for all battery cells230. In the present embodiment, BMC500directs individual BMB600to control shunting of the particular battery cell230to which it is connected, which distributes the load BMS200must bear while shunting the battery cells230.

Similar to BMB transceiver700shown inFIG.5, BMB transceiver700shown inFIG.6is dedicated to communicating with the other BMB transceivers700. The structural and functional characteristics of BMB transceiver700will be described below in more detail. In some embodiments, BMB600may implement a data storage similar to data storage560inFIG.5, so that data communication and other functions of BMB600are performed asynchronously. In other embodiments, BMB processor510and BMB transceiver700may communicate with each other directly. Keeping BMB transceiver700and BMB processor510separate as in BMC500may be unnecessary, because BMB600is only required to communicate with BMC500and not with the other BMBs600. BMC500, on the other hand, must communicate with all BMBs600in BMS200.

FIG.7is a schematic diagram illustrating an exemplary embodiment of BMB transceiver700, consistent with the disclosed embodiments. BMB transceiver700ofFIG.7is described as implemented on BMC500, but BMB transceiver700implemented on BMB600may be structured and function substantially similarly except that BMC processor510is replaced with BMB processor610. As noted above, BMB transceiver may be a dedicated module for transmitting and receiving data communication among BMB transceivers700located on BMBs600and BMC500. BMB transceiver700is also configured to perform signal conditioning, encoding/decoding, and modulation/demodulation of data signals so that they can be transmitted over the HV cables (i.e., HV data cables221, HV bus bars222, and HV power cables223).

As shown inFIG.7, BMB transceiver700comprises an encoder711and a decoder721pair, a modulator712and a demodulator722pair, an output signal conditioner715and an input signal conditioner725pair, an output buffer716and an input buffer726pair, and an output isolator717and an input isolator727pair. Further, HV data cables221are represented by thick lines as they were inFIG.1to indicate that they carry the HV DC voltage, while the other lines connecting components of BMB transceiver700are represented by regular thin lines to indicate that they carry low voltage AC/DC signal.

As described above, BMC processor510is configured to transmit messages to BMB600and receive status information from BMB600. BMB transceiver comprises of a transmit side circuit (the upper portion of BMB transceiver700) and a receive side circuit (the lower portion of BMB transceiver700). The transmit side is configured to receive outbound digital data731, convert it to an outbound signal735, and transmit it via HV data cables221, HV bus bars222, and HV power cables223as an injected signal750. The receive side is configured to receive injected signal750from the cables as an inbound signal745, convert it to an inbound digital data741, and output it to BMC processor510.

For BMB transceiver700of BMC500as shown inFIG.5, outbound digital data731may be a polling message to all BMBs600, requesting status information from every battery cell600, or a command to a particular BMB600, instructing it to stop charging to balance battery cells230. Inbound digital data741may be the status information received from each BMB600. For BMB transceiver700on BMB600as shown inFIG.6, outbound digital data731may be the status information of battery cell230to which it is connected. Inbound digital data741may be the polling message or the command from BMC500. Injected signal750, regardless of whether it originated from BMC500or BMB600, may be a HV DC voltage combined with a low voltage AC voltage representing digital data.

Since all injected signals750, whether from BMC500or any of BMBs600, share the same wires to reach their intended recipient, BMB transceiver700may also be capable of time-division multiplexing (TDM). In other words, injected signals750from various sources may be multiplexed over the same wires to minimize overlap. BMB transceiver700may implement TDM by utilizing various serial communication protocols natively supported by IC processing units found in BMB transceiver700.

Alternatively, BMC500and BMBs600may communicate sequentially, where each transmission of injected signal750is triggered by BMC500. For example, BMC500may transmit thae first polling message to BMB600-1, and BMB600-1may transmit a message back to BMC500in response. BMC500may then transmit a next polling message to BMB600-2, in response to which BMB600-2may transmit a message to BMC500. This exchange of messages may repeat until BMC500cycles through all available BMBs600. BMC500may then cycle through all available BMBs600repeatedly until BMC500enters sleep mode.

BMB transceiver700may also have in place additional safeguards against corrupted or jumbled signals. For example, every injected signal750is marked with a start bit and a stop bit that indicate the ends of one unit of communication (e.g., a message from BMC500to BMB600). Decoder721may also utilize error checking algorithms known in the art to discard any inbound signal that may have been corrupted. For example, when BMB transceiver700on BMC500fails to fully decode an incoming signal, BMB transceiver700may request a retransmission from the corresponding BMB600. If the retransmission is unsuccessful three consecutive times, BMC500may mark the corresponding BMB600as a failure and place BMS200in a reduced power mode. BMC500may also stop communicating with the failed BMB600.

In conventional systems, it would not be possible for BMC500and BMBs600to communicate with each other using injected signal750traveling on HV data cables221, HV bus bars222, and HV power cables223. In BMS200according to disclosed embodiments, injected signal750is only readable by another BMB transceiver700(on BMC500or BMB600) using the components described herein with respect toFIG.7. The other connected systems, subsystems, and devices that use the HV DC voltage as a power source are not affected by, or may even be oblivious to, the modulated signal added onto the HV DC voltage, because the amplitude of the modulated signal is significantly smaller compared to the voltage value of the HV DC voltage (e.g., 3.3V compared to 480V). Only BMC500or BMB600equipped with BMB transceiver700is able to extract the modulated signal from injected signal750and decode the information contained therein.

Major components of BMB transceiver700that convert outbound digital data731to injected signal750and back to inbound digital data741are described next. The first component is encoder711, which is configured to package outbound digital data731into a data packet according to a predetermined template900. An exemplary template for such a data packet is further described below with reference toFIG.9.

In some embodiments, encoder711may also output the data packet as an outbound bitstream732—a square wave representing the data packet in a binary sequence of logic 0s and 1s (exemplary signal shown inFIG.8). The bitstream may have a predetermined amplitude, such as 3.3V, 5V, or the like, and a bit width determined by a predetermined baud rate. For example, the bit width of outbound bitstream732encoded at 256,000 bits per second may be 4 microseconds. The baud rate of 256,000 bits per second is only exemplary and other rates may be equally applicable.

Next, modulator712is configured to accept outbound bitstream732and a carrier signal733as inputs and combine them to generate an outbound modulated signal734. Such modulation is used instead of using the HV DC voltage from battery cells230to carry a digital signal. Modulator712may implement any signal modulation scheme, such as Amplitude-Shift Keying (ASK), Continuous Phase Modulation (CPM), Frequency-Shift Keying (FSK), Minimum-Shift Keying (MSK), On-Off Keying (OOK), Wavelet Modulation (WDM), or the like. While modulator712described herein implements the OOK scheme, other types of modulator712implementing other signal modulation schemes are also within the scope of the disclosed embodiments. For example, modulator712implementing an FSK scheme may comprise two oscillator signal sources713configured to output two signals with distinct frequencies.

In the present embodiment, modulator712is configured to implement the OOK scheme and comprises of an oscillator signal source713and a mixer714. Oscillator signal source713includes circuits configured to provide a carrier signal713, such as a numerically controlled oscillator (NCO), a memory storing a plurality of digital oscillator signals, or a voltage-controlled oscillator (VCO). The carrier signal733is used as a base signal to be modulated with outbound bitstream732into an outbound modulated signal734, suitable for transmission over HV data cables221. Carrier signal733may be, for example, a sine wave of a fixed amplitude and frequency. Preferably, carrier signal733may match the amplitude of outbound bitstream732and a frequency higher than the baud rate, which may be, for example, 9 MHz. This frequency of 9 MHz is only exemplary and other frequencies may be equally applicable.

Mixer714includes circuits configured to mix outbound bitstream732with carrier signal733, such as a digital multiplier or a complex-valued digital multiplier. Mixer714may add, multiply, or perform other manipulation of outbound bitstream732and carrier signal733as appropriate for the chosen modulation scheme. In the present embodiment, for example, mixer714implements the OOK scheme and generates outbound modulated signal734by outputting carrier signal733during periods corresponding to logic 0 in outbound bitstream732and outputting nothing (i.e., 0V) during periods corresponding to logic 1. The resulting output is outbound modulated signal734(exemplary signal shown inFIG.8). While mixer714is described here implementing the OOK scheme, other types of mixers are also within the scope of the disclosed embodiments.

Output signal conditioner715includes one or more filters and amplifiers with different properties designed to minimize distortion, attenuation, or other degradations of signal from generating outbound modulated signal734. Any combination of filters and amplifiers may be used as appropriate for the chosen modulation scheme, including, but not limited to, low pass filter, high pass filter, and/or bandpass filter. The end result of output signal conditioner715is an outbound signal735.

Still further, output buffer716controls signal flow before outbound signal735is finally injected into HV data wire221across output isolator717. Output buffer716may be implemented in hardware circuit or in software code. Output buffer716may also comprise more than one buffer in series, and output buffer716of BMC500may be larger than output buffer716of BMB600in order to account for the larger number of communications that BMC500must respond to.

Output isolator717is configured to isolate BMB transceiver700from the HV DC voltage traveling in HV data cables221. Output isolator717prevents current flow between BMB transceiver700and HV data cables221and allows only the voltage signal, i.e., outbound signal735, to pass through. The end result is injected signal750, which corresponds to outbound signal735offset by the HV DC cables (exemplary signal shown inFIG.8). For example, outbound signal735with amplitude of 3.3V combining with the HV DC cables of 480V would yield an AC signal fluctuating between 480V and 483.3V. In some embodiments, output isolator717may comprise a galvanic isolator, an opto-isolator, a capacitance isolator, or the like.

Turning to the receive side, BMB transceiver700receives injected signal750across input isolator727to end up with an inbound signal745. Input isolator727may be substantially similar to output isolator717except for the direction of signal flow. Specifically, input isolator727also shields the HV DC voltage from injected signal750and allows only the data signal to enter BMB transceiver700.

As with output buffer716, input buffer726controls signal flow of inbound signal745before the signal is processed through the rest of the receive side. Input buffer726may also be implemented in hardware or in software code, and there may be more than one buffer in series. Input buffer726of BMC500may also be larger than input buffer726of BMB600.

Input signal conditioner725includes one or more filters and amplifiers with different properties designed to minimize distortion, attenuation, transient noise, or other degradations of signal introduced while injected signal750traveled in HV data cables221. Any combination of filters and amplifiers may be used as appropriate for the chosen modulation scheme, including, but not limited to, low pass filter, high pass filter, and/or bandpass filter. The end result of input signal conditioner725is an inbound modulated signal744.

In some embodiments, input signal conditioner725may also include an automatic gain control circuit (AGC) that dynamically adjusts gain to make the amplitude of resulting inbound modulated signal744consistent. A uniform amplitude is desired, because outbound bitstream732that corresponds to inbound modulated signal744would have been a square wave with a constant amplitude. Other configurations of input signal conditioner725are also within the scope of the disclosed embodiments. For example, an input signal conditioner for BMB transceiver700implementing the FSK scheme may comprise two sets of filters—one for high frequency and the other for low frequency.

Next, demodulator722is provided to remove the modulated portion of inbound modulated signal744and extract an inbound bitstream742. Demodulator722operates to reverse the manipulations performed by modulator712. As such, modulators and demodulators typically work in pairs to convert a bitstream into a modulated signal and vice versa. A demodulator implementing a signal modulation scheme different from that of a corresponding modulator would not be able to demodulate a signal generated by the modulator.

In the present embodiment, demodulator722is implemented using the OOK scheme as modulator712is. However, BMB transceivers700implementing other signal demodulation schemes and corresponding modifications to the version of BMB transceiver700described herein are also within the scope of disclosed embodiments.

Here, demodulator722comprises a high bit detector724and a comparator723. High bit detector724may be configured to output a high voltage when the input signal meets a specific condition. For example, when inbound modulated signal744comprises periods of modulated signal and zero voltage as generate by modulator712, high bit detector724may output a high voltage (equal to the amplitude of the high bit) every time it encounters a rising edge or a peak of the modulated signal. The resulting signal output by high bit detector724may be a semi-square wave that loosely corresponds to inbound bitstream742.

Comparator723is configured to shape the semi-square wave output from high bit detector724, so that it is closer to a square wave. Comparator723may output a high voltage where the input signal is above a reference voltage and a low voltage where the input signal is below. This output from comparator723, and thus demodulator722, is a square wave corresponding to inbound bitstream742. Thus, the shape of inbound bitstream742is substantially identical to that of outbound bitstream732used to generate injected signal750at the transmit side of another BMB transceiver700. In some embodiments, inbound bitstream742may go through another set of filters and/or amplifiers to remove any distortion or attenuation introduced by demodulator722and bring the amplitude to proper logic levels (e.g., Vdd).

Similar to how demodulator722demodulates the signal generated by modulator712, decoder721is configured to decode the signal encoded by encoder711. More specifically, decoder721may use predetermined template900to identify what each bit in inbound bitstream742represents and parse inbound digital data741out of inbound bitstream742.

FIG.8is a diagram showing different exemplary communication signals, consistent with disclosed embodiments. An exemplary bitstream810, an exemplary modulated signal820, and an exemplary injected signal830are shown. While amplitude, bit width, or bit sequence of bitstream810are only exemplary, bitstream810generally corresponds to a version of outbound bitstream732or inbound bitstream742consistent with disclosed embodiments. Similarly, modulated signal820generally corresponds to versiona of outbound modulated signal734or inbound modulated signal744; and injected signal830generally corresponds to a version of injected signal750, consistent with disclosed embodiments. In this example, bitstream810comprises a series of logic 1s811and 0s812. After modulation using the OOK scheme described above, bitstream810becomes modulated signal820. Modulated signal820has the same amplitude (i.e., 3.3V) as bitstream810but comprises periods of modulated signal821, where logic 1s811are brought to 0V and logic 0s812are replaced with an exemplary carrier signal (not shown). Injected signal830also has the same amplitude as bitstream810and modulated signal820but is offset by the HV DC voltage, e.g., 480V, so as to fluctuate between, e.g., 480V and 483.3V. All characteristics of the communication signals shown inFIG.8, including but not limited to voltage values, labels, waveforms, periods, and frequencies, are only intended to serve as example and are not intended to be limiting in any way.

FIG.9is an exemplary template900of a data packet used for communicating a message, consistent with the disclosed embodiments. As used herein, a data packet refers to a unit of communication, in which data (e.g., information, measurement, parameter, message, etc.) is packaged into a single sequence of hexadecimal values. Once a data packet is generated, transmitting the data packet using serial communication involves converting the hexadecimal values into binary values, thereby generating a bitstream referred to inFIG.7.

Here, template900may comprise of up to 16 bytes of data (DATA)920, accompanied by 1 byte of start of transmission (SOT) code 901, 1 byte of end of transmission (EOT) code 902, 1 byte of data length code (DLC) 903, and 3 bytes of message identification code (MID)910. In some embodiments, template900may be user-configurable and modifiable to comprise more or less information and/or to comprise different sections of different lengths or different values. Each section of template900and possible values are described below. The names, values, and structures of different sections described below are only intended to serve as examples.

SOT901and EOT902are standard, fixed value bytes that represent the start and end of a data packet. Here, they are predetermined to be 0x01 and 0x04, respectively. These values would be 000001 and 000100 in binary.

MID910comprises four different subsections: message transmission type (MT)911A, high nibble address of receiving BMB transceiver700(AD)911B, low byte of the address of the receiving BMB transceiver700(LBAD)912, and node function code (NFC)913.

MT911A and AD911B occupy only one hexadecimal digit, because that is sufficient to account for all possible values. Specifically, MT911A may take only two values, 0x0 or 0xf, where 0x0 represents a polled message intended for a specific BMB transceiver700(e.g., BMC500or BMB600-1), and where 0xf represents a broadcast message intended for all BMBs600. For example, a polled message may be a request to a specific BMB600for status information on the particular battery cell230that it is connected to. The receiving BMB600may then transmit another polled message to BMC500with the status information. On the other hand, a broadcast message may be an instruction to all BMB600to enter a particular mode (e.g., sleep mode). The BMBs600may perform appropriate actions (e.g., entering sleep mode) in response to such broadcast but while not transmitting any message back to BMC500.

AD911B and LBAD912combine to form a three hexadecimal digit representing an address. In some embodiments, every BMBs600and BMC500in BMS200may be assigned a number as its address. For example, 0x000 may always be set as BMC500, and numbers 0x001 to 0x400 may refer to each BMB600, from BMB600-1to BMB600-1024. Using this convention, up to 0xfff or 4096 distinct addresses are available, which means that BMS200can interface with up to 4096 battery cells230. In some embodiments, BMC500may include an auto-mapping feature to map the addresses of all battery cells230in BMS200during initialization.

NFC913may take different values based on whether it is BMC500or a BMB600that is transmitting a data packet. For example, 0x00 for NFC913may represent a command or code to control and monitor a particular BMB.

Considering all subsections of MID910together, the value 0x000100 would represent a polled message from BMC500to BMB600-1. The value 0x008000 would represent another polled messaged from BMC500to BMB600-128, as 0x080 is 128 in decimal. The value 0x000000 would represent a polled message from a particular BMB600to BMC500in response to, e.g., a request from BMC500for status information. It is noted that MID910may not contain an address of the particular BMB600that sent the polled message, because the polled message would be in response to an earlier message from BMC500to the particular BMB600. In other embodiments, template900may further comprise an additional section or subsection for encoding the address of a sending BMB600.

DATA920may take any value that represents the digital data intended for transmission (e.g., outbound digital data721), and DLC903may take the value equal to the length of the digital data. DLC903serves to provide an indication to decoder721that the next two bytes will be EOT902and that the previous 0xnn (the value of DLC903) bytes represent the digital data. In the current example, the digital data can be as large as 16 bytes. However, BMS200can be configured to allow even larger data to be transmittable just by increasing the length of DATA920in template900and noting the length in DLC903.

FIG.10Ais a flow chart illustrating an exemplary method1010for transmitting a signal, consistent with disclosed embodiments. Method1010may be performed by BMC500or BMB600. In particular, method1010may be performed by the transmit side circuit (the upper portion of BMB transceiver700) as disclosed herein. For example, BMC processor510and the circuit components of BMB transceiver700(e.g., encoder711) may perform steps of method1010. As another example, BMB processor610and the circuit components of BMB transceiver700may perform steps of method1010.

Method1010includes generating a message regarding one or more status parameters of a battery cell (step1011); encoding the message into a data packet for serial communication (step1012); converting the data packet into a bitstream (step1013); modulating the bitstream with a carrier signal to generate a modulated data signal (step1014); conditioning and buffering the modulated data signal (step1015); and injecting the modulated data signal onto a DC voltage line (step1016).

At step1011, BMC processor510or BMB processor610generates a message (i.e., outbound digital data731) regarding one or more status parameters of battery cell230. For example, the message may represent status parameters of battery cell230such as the current voltage and temperature. In another example, the message may represent a request for the status parameters.

At step1012, encoder711encodes the message into a data packet for serial communication. The data packet may follow predetermined template900and contain default values, sections, or subsections as described above. At step1013, encoder711also converts the data packet into outbound bitstream732comprised of a string of binary values. At this stage, the message generated at step1011is a signal wave, as opposed to digital data stored in memory.

At step1014, modulator712modulates outbound bitstream732with carrier signal733to generate outbound modulated signal734. The message generated at step1011may now exist as an analog signal wave, suitable for transmission over wires.

At step1015, output signal conditioner715and output buffer716conditions and buffers outbound modulated signal734to generate outbound signal735, respectively. The different conditioning circuits and processes may be performed on outbound modulated signal734, one after another, in parallel, or in any combination thereof. At this stage, the message generated at step1011is outbound signal735, ready to be transmitted to other BMB transceivers700.

At step1016, output isolator717injects outbound modulated signal734onto HV data cables221or HV bus bars222. Such injection effectively loads outbound modulated signal734onto the HV DC voltage, shifting the entire signal up by the amount of voltage carried by the HV DC voltage. Injected signal750may then travel to the other BMB transceivers700instantaneously, where it is received by the intended recipient and processed through the method ofFIG.10B.

FIG.10Bis a flow chart illustrating another exemplary method1020for receiving a signal, consistent with the disclosed embodiments. Method1020may be performed by BMC500or BMB600. In particular, method1020may be performed by the receive side circuit (the lower portion of BMB transceiver700) as disclosed herein. For example, BMC processor510and the circuit components of BMB transceiver700(e.g., decoder721) may perform steps of method1020. As another example, BMB processor610and the circuit components of BMB transceiver700may perform steps of method1020.

Method1020includes receiving a modulated data signal offset by a DC voltage (step1021); removing the DC voltage to extract the modulated data signal (step1022); conditioning and buffering the modulated data signal to remove transient noise and shape the modulated data signal to proper logic levels (step1023); demodulating the modulated data signal to extract a bitstream containing a data packet (step1024); decoding the data packet to parse a message regarding one or more status parameters of a battery cell230(step1025); and outputting the one or more status parameters (step1026).

At step1021, BMB transceiver700receives injected signal750offset by the HV DC voltage. At this point, it is unknown what data injected signal750contains. At step1022, input isolator727removes the HV DC voltage from injected signal750to extract inbound signal745by receiving it over input isolator727, which blocks the HV DC voltage.

At step1023, input signal conditioner725and input buffer726, respectively, conditions and buffers inbound signal745to remove transient noise and shape inbound signal745to proper logic levels. For example, passing inbound signal745through a low pass filter removes transient noise not blocked by input isolator727and passing the signal through a high pass filter removes high frequency noise that may have been caused by interference. At this stage, injected signal750received at step1021is cleaned to be inbound modulated signal744, but the signals may still be in more or less the same shape, which cannot as yet be read by a processor.

At step1024, demodulator722demodulates inbound modulated signal744to extract inbound bitstream742containing a data packet. The process for demodulating may depend substantially on how inbound modulated signal744was initially modulated, and one exemplary demodulator for demodulating a OOK modulated signal is provided above with respect toFIG.7. At this stage, injected signal750received at step1021has been converted into inbound bitstream742, which may loosely follow the shape of a digital signal.

At step1025, decoder721reads inbound bitstream742to obtain the data packet and decodes the data packet to parse a message regarding one or more status parameters of battery cell230. Similar to how demodulation was dependent on how the signal was modulated, decoding the data packet is also dependent on how the signal was encoded. One exemplary process of decoding a data packet generated based on template900is provided above with respect toFIGS.7and9. At this stage, injected signal750received at step1021is fully converted into a computer-readable message, which is output to either BMC processor510or BMB processor610at step1026.

BMS200addresses various shortcomings of conventional battery management systems. BMS200is generally applicable to power a system that requires significant electrical power. The advantages of BMS200and other techniques provide for a new vehicle power system for motive power to a vehicle having batteries in a safe, convenient, and economical manner.

In conventional vehicles powered by batteries, different components necessary for providing the motive power are scattered throughout the vehicle. This makes installation, maintenance, and repair of the power system difficult and costly. In this respect, the vehicle power system according to the present disclosure substantially departs the conventional concepts and designs of the prior art, and in doing so provides an apparatus for providing motive power to a vehicle having batteries in a safe, convenient, and economical manner.

Referring toFIG.11A, a vehicle power system1110of present disclosure provides motive power to a vehicle1112. Vehicle1112has a forward end1120, a rearward end1122, a left side1124, and a right side1126. Vehicle power system1110has an engine1114for providing motive power to vehicle1112and batteries1116for providing electrical power to engine1114. In some embodiments, engine1114may comprise a combustion engine, an electrical motor, or a combination of the two. The motive power and electrical power are provided in a safe, convenient, and economical manner. Furthermore, vehicle power system1110may be solid-state, where it is solely comprised of non-moving components. In other embodiments, vehicle power system1110may not comprise of any component with a belt or pulley system. For example, an alternator that may be found with a conventional internal combustion engine (ICE) (not shown) may be replaced with a DC-to-DC converter, and other conventional components of ICE, such as a water pump, a vacuum pump, or an air conditioner compressor, are replaced with electronic parts.

Engine1114is positioned in a forward region of vehicle1112(e.g., in an engine bay). Batteries1116are positioned in a rearward region of vehicle1112. Batteries1116and engine1114are operatively coupled. The positions of these components relative to each other and to vehicle1112is exemplary and can be altered without departing from the scope of the present disclosure. For example, engine1114may be positioned in the rearward region of vehicle1112and used in a pusher configuration as in a Type D school bus or other vehicles having a propulsion system in the rearward region. In some embodiments, batteries1116may be positioned in the intermediate region of vehicle1112or spread throughout the floor of vehicle1112. This may allow vehicle1112to minimize or eliminate the need for driveshaft obstructions. Further, having engine1114in the rearward region or batteries1116in the intermediate region may allow the floor of vehicle1112to be lowered, thus making the vehicle more accessible for occupants.

A power distributor unit1130is positioned in an intermediate region of vehicle1112. In some embodiments, power distributor unit1130may be positioned else where in vehicle1112, such as on the side of engine1114where a valve cover may be found in conventional vehicles.

An adaptor plate1134on a rearward end of engine1114couples engine1114to a transmission of the vehicle forwardly of power distributor unit1130. Adaptor plate1134may comprise one or more sensors that determine a location of a motor shaft using one or more encoders. The encoder(s) may comprise a rotary encoder with a toothed plate, where each tooth represents an angular location of the rotation of the motor shaft coupled to, e.g., a gearbox or a transmission. In some embodiments, other systems or subsystems of vehicle1112(e.g., main control system110or subsystems A-C111-112) may use outputs of the one or more sensors to control functionalities of vehicle1112such as indicators and/or warning lights on a dashboard of vehicle1112and power steering systems.

A radiator1138is coupled to vehicle1112forwardly of engine1114. A coolant input line1140and a coolant output line1142operatively couple radiator1138and engine1114.

Referring toFIG.11B, an inverter board1146is located above engine1114. A plurality of electrical components are provided and located above engine1114beneath inverter board1146. The plurality of electrical components include an air pump1148, an in-line heater pump1150, and a coolant pump1152adjacent to left side1124of vehicle1112. The plurality of electrical components also include an air conditioner compressor1154, an AC-to-DC power converter1156, and a cooling block pump1158adjacent to right side1126of vehicle1112. While not shown inFIG.11B, power distributor unit1130may also be placed on engine1114without departing from the scope of present disclosure.

FIGS.11C-11Fare different views of engine1114that illustrate relative positions of the components described above. Specifically,FIG.11Cis a left side view of engine1114, taken along a section line11C-11C inFIG.11B.FIG.11Dis a front side view of engine1114, taken along a section line11D-11D inFIG.11C.FIG.11Eis a rear side view of engine1114, taken along a section line11E-11E inFIG.11C. Lastly,FIG.11Fis a right side view of engine1114, taken along a section line11F-11F inFIG.11D. Referring toFIG.11G, electrical connectors1162are provided beneath engine1114to removably couple power distributor1130to the engine.

In some embodiments, a DC-to-DC converter (not shown) may be provided to replace or supplement an alternator system such as found in conventional vehicles. The DC-to-DC converter may be positioned beneath engine1114, such as where an oil pan may be found in conventional vehicles, in a charger unit (not shown) coupled to batteries1116. The charger unit may comprise various electronic components for interfacing with an external charging port. In some embodiments, the charger unit may comprise a charger, the DC-to-DC converter, and/or AC-to-DC power converter1156.

Engine1114and the other components described above form an integrated assembly of parts that provide motive power to vehicle1112. Compared to conventional systems that comprise discrete, unassembled parts that must be installed in a vehicle one by one, the integrated assembly according to disclosed embodiments simplifies manufacturing assembly lines by offering a single package that can be installed at together one time. Similarly, replacing the integrated assembly may also be simplified, where the integrated assembly can be removed and reinstalled together at one time.

The computer-readable storage medium of the present disclosure may be a tangible device that can store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.

The computer-readable program instructions of the present disclosure may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including an object-oriented programming language, and conventional procedural programming languages. The computer-readable program instructions may execute entirely on a computing device as a stand-alone software package, or partly on a first computing device and partly on a second computing device remote from the first computing device. In the latter scenario, the second, remote computing device may be connected to the first computing device through any type of network, including a local area network (LAN) or a wide area network (WAN).

The flowcharts and block diagrams in the figures illustrate examples of the architecture, functionality, and operation of possible implementations of systems, methods, and devices according to various embodiments. It should be noted that, in some alternative implementations, the functions noted in blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

It is understood that the described embodiments are not mutually exclusive, and elements, components, materials, or steps described in connection with one example embodiment may be combined with, or eliminated from, other embodiments in suitable ways to accomplish desired design objectives.

Reference herein to “some embodiments” or “some exemplary embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment. The appearance of the phrases “one embodiment” “some embodiments” or “another embodiment” in various places in the present disclosure do not all necessarily refer to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments.

It should be understood that the steps of the example methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely example. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments.

As used in the present disclosure, the word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word is intended to present concepts in a concrete fashion.

As used in the present disclosure, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a database may include A or B, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then, unless specifically stated otherwise or infeasible, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

Additionally, the articles “a” and “an” as used in the present disclosure and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form.

Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.

Although the elements in the following method claims, if any, are recited in a particular sequence, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the specification, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the specification. Certain features described in the context of various embodiments are not essential features of those embodiments, unless noted as such.

It will be further understood that various modifications, alternatives and variations in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of described embodiments may be made by those skilled in the art without departing from the scope. Accordingly, the following claims embrace all such alternatives, modifications and variations that fall within the terms of the claims.