Patent ID: 12198648

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the disclosure are described with reference to the drawings.

1. First Embodiment

1.1 Entire Configuration and Operation

FIG.2is a block diagram illustrating an entire configuration of a liquid-crystal display apparatus of a first embodiment. The liquid-crystal display apparatus includes a power supply circuit100, a timing controller (timing control circuit)200, a memory300, a gate driver (scanning signal line driver circuit)400, a source driver (video signal line driver circuit)500, and a display600.FIG.2is a functional block diagram and is thus different from an actual position relationship of elements.

The display600includes n source bus lines (video signal lines) SL(1) through SL(n) and m gate bus lines (scanning signal lines) GL(1) through GL(m). Pixel formation units6forming pixels are respectively arranged at the intersections of the n source bus lines SL(1) through SL(n) and the m gate bus lines GL(1) through GL(m). Specifically, the display600includes n×m pixel formation units6. Each pixel formation unit6includes a pixel thin-film transistor (TFT)60having a control terminal connected to the gate bus line GL passing through the corresponding intersection and a first conductive terminal connected to the source bus line SL passing through the corresponding intersection. Each pixel formation unit6further includes a pixel electrode61connected to a second conductive terminal of the TFT60, a common electrode64commonly arranged to the n×m pixel formation units6and an auxiliary capacitance electrode65, a liquid-crystal capacitance62formed by the pixel electrode61and the common electrode64, and an auxiliar capacitance63formed by the pixel electrode61and the auxiliary capacitance electrode65. A pixel capacitance66is formed by the liquid-crystal capacitance62and the auxiliar capacitance63.FIG.2illustrates only one pixel formation unit6. The display600is herein rectangular. Alternatively, the display600may be non-rectangular.

Operation of the elements inFIG.2is described below. By level-converting a system power supply voltage VO, the power supply circuit100generates power supply voltages VP1through VP3for logic operation and the analog power supply voltage AVDD for driving liquid crystals. The power supply voltages VP1through VP3for the logic operation may not necessarily be different from each other. When the analog power supply voltage AVDD is generated, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync provided by the timing controller200are referenced.

The timing controller200controls the operation of the power supply circuit100, the gate driver400, and the source driver500. Specifically, the timing controller200receives, from the outside, image data DAT and timing signal group TG (such as the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync) and then outputs a digital video signal DV, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to be supplied to the power supply circuit100, a gate control signal GCTL that controls the operation of the gate driver400, and a source control signal SCTL that controls the operation of the source driver500. The gate control signal GCTL includes a gate start pulse signal, a gate clock signal, and the like. The source control signal SCTL includes a source start pulse signal, a source clock signal, a latch strobe signal, and the like.

The memory300stores the image data DAT for one frame. The writing of the image data DAT onto the memory300and the reading of the image data DAT from the memory300are controlled by the timing controller200.

In response to the gate control signal GCTL from the timing controller200, the gate driver400periodically applies an active scanning signal to each gate bus line GL every vertical scanning period. Specifically, the gate driver400drives the m gate bus lines GL(1) through GL(m).

The source driver500applies a driving video signal to each source bus line SL in response to the digital video signal DV and the source control signal SCTL transmitted from the timing controller200. At the timing of the generation of a pulse of the source clock signal, the source driver500successively stores the digital video signal DV indicating a voltage to be applied to each source bus line SL. The digital video signal DV stored is converted into an analog voltage at the timing of the generation of a pulse of the latch strobe signal. The converted analog signal is applied as the driving video signal to the n source bus lines SL(1) through SL(n) at a time. In this way, the source driver500drives the n source bus lines SL(1) through SL(n). The source driver500includes a gradation voltage generator circuit that generates the analog power supply voltage AVDD from an analog voltage responsive to each gradation value indicated by the digital video signal DV.

An image responsive to the image data DAT coming in from the outside is displayed on the display600by applying a scanning signal to the gate bus line GL and a driving video signal to the source bus line SL.

1.2 Configuration of Boost DC-DC Converter

FIG.3illustrates a configuration that generates the analog power supply voltage AVDD in response to the system power supply voltage VO. From among the DC-DC converters included in the power supply circuit100,FIG.3illustrates only a boost DC-DC converter110that generates the analog power supply voltage AVDD that is supplied to the source driver500.

The boost DC-DC converter110includes, in addition to an input terminal18and an output terminal19, a coil (inductor)11, a thin-film transistor12serving as a switching element that varies an inductor current (a current flowing through the coil11), a capacitor13serving as a capacitance element, a diode14serving as a rectifying element, and a switching control circuit15. The input terminal18is supplied with the system power supply voltage VO of 3.3 V. One end of the coil11is connected to the input terminal18while the other end of the coil11is connected to a node17. The thin-film transistor12has the control terminal supplied with the control signal SC (the control signal SC including the switching pulse SWP) output from the switching control circuit15, the first conductive terminal connected to the node17(in other words, the other end of the coil11), and the second conductive terminal grounded. The capacitor13has one end grounded and the other end connected to the output terminal19. The diode14has an anode connected to the node17and a cathode connected to the output terminal19. In other words, the diode14allows a current to only flow from the other end of the coil11to the other end of the capacitor13. The switching control circuit15references a mode signal MD while outputting the control signal SC controlling an on/off operation of the thin-film transistor12. The switching control circuit15outputs the control signal SC in response to the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, a feedback voltage Vfb, a feedback current Ifb, and an enable signal ENA output from an enable signal generator circuit22in the timing controller200. The output terminal19is connected to the source driver500and the voltage at the other end of the capacitor13is output from the capacitor13as the analog power supply voltage AVDD. The analog power supply voltage AVDD as a power supply voltage boosted by the boost DC-DC converter110is thus supplied to the source driver500.

As described above, the switching control circuit15is supplied with the feedback voltage Vfb and the feedback current Ifb. According to the first embodiment, a control method called current mode control is employed. The disclosure is not limited to the current mode control. A control method (only voltage is fed back) called voltage control may also be employed.

In the liquid-crystal display apparatus including the power supply circuit100having the boost DC-DC converter110, one frame period includes an effective video period and a vertical blanking period. During the effective video period, the source driver500applies an effective driving video signal to the n source bus lines SL(1) through SL(n) and the gate driver400successively selects one by one the m gate bus lines GL(1) through GL(m). During the vertical blanking period, the gate driver400stops selecting the gate bus line GL. The boost DC-DC converter110operates in the effective video period as a heavy-load period while operating in the vertical blanking period as a light-load period.

Basically, when the vertical blanking period transitions to the effective video period, the switching control circuit15supplies the control terminal of the thin-film transistor12with the control signal SC such that an operation mode remains in a current continuation mode. When the effective video period transitions to the vertical blanking period, the switching control circuit15supplies the control terminal of the thin-film transistor12with the control signal SC such that the operation mode remains in a current discontinuation mode. However, the switching control circuit15supplies the control terminal of the thin-film transistor12with the control signal SC such that the operation mode transitions to the current continuation mode during at least a portion (a first predetermined period) of a time duration that continues from a moment when the operation mode transitions from the current continuation mode to the current discontinuation mode in response to transitioning from the effective video period to the vertical blanking period to a moment when the vertical blanking period transitions to the effective video period. Specifically, the control terminal of the thin-film transistor12is forcibly supplied with the switching pulse SWP having a relatively high frequency during the first predetermined period even in the vertical blanking period.

The timing controller200includes a setting register21and the enable signal generator circuit22. The setting register21stores, as set values, a value identifying a rising point of a pulse included in the enable signal ENA and a value identifying a pulse width of the pulse. The enable signal generator circuit22generates the enable signal ENA in response to the set values stored on the setting register21while referencing the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync. The enable signal ENA generated by the enable signal generator circuit22is supplied to the switching control circuit15in the boost DC-DC converter110.

FIG.4is a block diagram illustrating a configuration of the switching control circuit15. Referring toFIG.4, the switching control circuit15includes a feedback voltage monitor151, a forcing-pulse setting signal generator152and a switching pulse generator153.

The feedback voltage monitor151monitors the feedback voltage Vfb (namely, a boosted power supply voltage) and generates the flag signal FLG representing the monitoring results. Specifically, the feedback voltage monitor151compares a voltage value of the feedback voltage Vfb with a predetermined threshold and then generates the flag signal FLG representing the comparison results. According to the first embodiment, the voltage level of the flag signal FLG is maintained at a low level (with the flag in an off state). When the voltage value of the feedback voltage Vfb exceeds the threshold, the voltage value of the feedback voltage Vfb is maintained at a high level (with the flag in an on state) for a time duration having a predetermined time length (second predetermined period) from a moment when the feedback voltage monitor151detects the voltage value of the feedback voltage Vfb in excess of the threshold.

While referencing the mode signal MD, the forcing-pulse setting signal generator152generates, in response to the flag signal FLG and the enable signal ENA, the forcing pulse setting signal POUT that forcibly causes the switching pulse generator153to generate the switching pulse SWP. The mode signal MD indicates whether a control mode is a first mode or a second mode. If the control mode is the first mode, the flag signal FLG is determined to be valid and if the control mode is the second mode, the flag signal FLG is determined to be invalid. If the mode signal MD indicates that the control mode is the first mode, the forcing-pulse setting signal generator152outputs as the forcing pulse setting signal POUT a signal corresponding to a logical AND of the flag signal FLG and the enable signal ENA. If the mode signal MD indicates that the control mode is the second mode, the forcing-pulse setting signal generator152outputs as the forcing pulse setting signal POUT a signal having the same waveform as the enable signal ENA.

The analog power supply voltage AVDD having a desired voltage value is generated. To this end, in response to the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the feedback voltage Vfb and the feedback current Ifb, the switching pulse generator153generates the control signal SC such that the switching pulse SWP is generated at a relatively high frequency for the effective video period and the switching pulse SWP is generated at a relatively low frequency for the vertical blanking period. In response to the forcing pulse setting signal POUT, the switching pulse generator153generates the control signal SC such that the switching pulse SWP is generated at a relatively high frequency even for the vertical blanking period. According to the first embodiment, the control signal SC including the switching pulse SWP at a relatively high frequency is generated while the forcing pulse setting signal POUT is maintained at a higher level.

If the control mode is the first mode, the switching control circuit15sets, to be the first predetermined period, a time duration while a period (second predetermined period) having a predetermined time length from a moment when a boosted power supply voltage exceeds a threshold overlaps a period throughout which a pulse included in the enable signal ENA occurs. The switching control circuit15supplies the control terminal of the thin-film transistor12with the control signal SC including the switching pulse SWP at a relatively high frequency such that the operation mode transitions to the current continuation mode during the first predetermined period. On the other hand, if the control mode is the second mode, the switching control circuit15sets, to be the first predetermined period, a time duration which the pulse included in the enable signal ENA occurs and the switching control circuit15supplies the control terminal of the thin-film transistor12with the control signal SC including the switching pulse SWP at a relatively high frequency such that the operation mode transitions to the current continuation mode during the first predetermined period.

1.3 Measure Applied to Voltage Drop

Measure applied to the voltage drop is described below.

1.3.1 Outline

The outline of a measure applied to the voltage drop is described with reference toFIG.1. In the related art, if a generation frequency of the switching pulse SWP (switching frequency of the thin-film transistor12) becomes a relatively low frequency after the effective video period PA transitions to the vertical blanking period PB, the generation frequency of the switching pulse SWP maintains at a relatively low frequency until the vertical blanking period PB transitions to the effective video period PA (SeeFIGS.9and11). According to the first embodiment, as illustrated inFIG.1, the switching control circuit15generates the switching pulse SWP at a relatively high frequency for a predetermined period (the first predetermined period) before the vertical blanking period PB transitions to the effective video period PA after the switching pulse SWP changes to a relatively low frequency in response to the transitioning from the effective video period PA to the vertical blanking period PB. By increasing the switching frequency of the thin-film transistor12before the vertical blanking period PB transitions to the effective video period PA, the analog power supply voltage AVDD high enough to drive the liquid crystals may be output from the boost DC-DC converter110even if a voltage drop occurs during the vertical blanking period PB.

1.3.2 Detailed Control

Detailed control of the boost DC-DC converter110is described below. It is noted that the mode signal MD indicates that the control mode is the first mode. Control with the mode signal MD indicating that the control mode is the second mode will be described with reference to a second embodiment.

FIG.5is a waveform diagram illustrating the operation of the boost DC-DC converter110. A portion of the waveform of the analog power supply voltage AVDD inFIG.5denoted by broken line from time t14to time t16is obtained when the measure disclosed in the specification is not taken.

The time duration prior to time t10is the effective video period PA. During the effective video period PA, the switching pulse SWP at a relatively high frequency is generated. Specifically, the boost DC-DC converter110operates in the current continuation mode. During the time duration, the flag signal FLG, the enable signal ENA, and the forcing pulse setting signal POUT are kept at a lower level.

At time t10, the effective video period PA transitions to the vertical blanking period PB. The generation frequency of the switching pulse SWP changes to a relatively low frequency. Specifically, the switching pulse generator153(seeFIG.4) changes the generation frequency of the switching pulse SWP from a relatively high frequency to a relatively low frequency. The switching pulse generator153may detect the timing of transitioning from the effective video period PA to the vertical blanking period PB by counting pulses of the horizontal synchronization signal Hsync from the generating timing of the pulse of the vertical synchronization signal Vsync. Referring toFIG.5, the generation frequency of the switching pulse SWP changes at the time when the effective video period PA transitions to the vertical blanking period PB. However, there is a case in which the generation frequency of the switching pulse SWP changes when a predetermined time duration elapses from the transition from the effective video period PA to the vertical blanking period PB (seeFIG.1).

The analog power supply voltage AVDD gradually rises in voltage value during the vertical blanking period PB as illustrated in a portion71inFIG.5. At time t11, the voltage value of the analog power supply voltage AVDD exceeds a predetermined threshold VT. The feedback voltage monitor151(seeFIG.4) determines that the voltage value of the feedback voltage Vfb exceeds the threshold VT. The feedback voltage monitor151then causes the flag signal FLG to transition from a low level to a high level. The state that the flag signal FLG is at a high level is maintained for a predetermined period (11 horizontal scanning periods inFIG.5).

At time t12, the enable signal ENA transitions from a low level to a high level. The enable signal ENA is generated by the enable signal generator circuit22in the timing controller200(seeFIG.3) as described below. The generation of the enable signal ENA is based on the set value stored on the setting register21in the timing controller200.

According to the second embodiment, the set value is stored on the setting register21as illustrated inFIG.6. As described above, the setting register21stores as the set values the value identifying the rising time of the pulse included in the enable signal ENA and the value identifying the pulse width of the pulse. Referring toFIG.6, ST1identifies the rising point of a first pulse included in the enable signal ENA and W1identifies the pulse width of the first pulse included in the enable signal ENA. ST2identifies the rising point of a second pulse included in the enable signal ENA and W2identifies the pulse width of the second pulse included in the enable signal ENA. In this example, the value of ST2and the value of W2are “0.” The enable signal generator circuit22thus generates the enable signal ENA such that one pulse is generated during the vertical blanking period PB. Referring toFIG.6, the value of ST1is “4.” The enable signal generator circuit22then transitions the enable signal ENA from a low level to a high level four horizontal scanning periods before the transition from the vertical blanking period PB to the effective video period PA (namely, four horizontal scanning periods before the rising time of the vertical synchronization signal Vsync). W1is “11” inFIG.6. The enable signal generator circuit22then transitions the enable signal ENA from a high level to a low level11horizontal scanning periods after the enable signal ENA transitions from a low level to a high level. In this way, the enable signal generator circuit22generates the enable signal ENA including a pulse having a pulse width equal to 11 horizontal scanning periods.

Since the control mode is the first mode in this case, the flag signal FLG is valid and the forcing-pulse setting signal generator152(seeFIG.4) outputs the forcing pulse setting signal POUT corresponding to a signal of the logical AND of the flag signal FLG and the enable signal ENA. With this respect, both the flag signal FLG and the enable signal ENA are at a high level at time t13when the pulse of the horizontal synchronization signal Hsync occurs first after the enable signal ENA transitions from a low level to a high level at time t12. Referring toFIG.5, the forcing pulse setting signal POUT transitions from a low level to a high level at time13. In response to the transition of the forcing pulse setting signal POUT from a low level to a high level, the switching pulse generator153changes the generation frequency of the switching pulse SWP from a relatively low frequency to a relatively high frequency. At time t13, the switching frequency of the thin-film transistor12becomes higher. For a time duration subsequent to time t13, the boost DC-DC converter110operates in the current continuation mode.

At time t15, the vertical blanking period PB transitions to the effective video period PA. At time t17, the flag signal FLG transitions from a high level to a low level. In response, the forcing pulse setting signal POUT transitions from a high level to a low level. At time t17, the forcing pulse setting signal POUT transitions to a low level but since time t17is included in the effective video period PA, the generation frequency of the switching pulse SWP is maintained at a relatively high frequency. At time t18, the enable signal ENA transitions from a high level to a low level.

In this example, the time duration from time t13to time t17corresponds to the first predetermined period and the time duration from t11to time t17corresponds to the second predetermined period.

The following discussion focuses on the waveform of the analog power supply voltage AVDD for the time duration from time t14to time t16. A waveform denoted by a broken line inFIG.5may result if the measure described in the specification is not taken and the voltage value of the analog power supply voltage AVDD is substantially lower than a desired voltage value for a time duration immediately after the transition from the vertical blanking period PB to the effective video period PA. According to the first embodiment, in contrast, the switching frequency of the analog power supply voltage AVDD of the thin-film transistor12is at a relatively high frequency subsequent to time t13. The voltage value of the analog power supply voltage AVDD thus rises in a portion72inFIG.5. As a result, the voltage value of the analog power supply voltage AVDD is maintained high enough even for the time duration immediately after the transition from the vertical blanking period PB to the effective video period PA.

1.4 Effect

According to the first embodiment, the switching control circuit15in the boost DC-DC converter110sets to be a relatively high frequency the generation frequency of the switching pulse SWP supplied to the control terminal of the thin-film transistor12for a predetermined time duration prior to the transition from the vertical blanking period PB to the effective video period PA after the effective video period PA transitions to the vertical blanking period PB. The boost DC-DC converter110thus operates in the current continuation mode for the predetermined time duration prior to the transition from the vertical blanking period PB to the effective video period PA. As a result, even if a voltage drop occurs in the analog power supply voltage AVDD during the vertical blanking period PB, the analog power supply voltage AVDD high enough to drive the liquid crystals may be obtained immediately after the transition from the vertical blanking period PB to the effective video period PA. Instead of controlling the boost DC-DC converter to obtain an output voltage higher than an actually desired voltage value to achieve the above-described effect, a portion of the operation mode, which is the current discontinuation mode in the related art configuration, is simply modified to the current continuation mode in the first embodiment. The control related to the first embodiment involves only a slight increase in power consumption. According to the first embodiment, the boost DC-DC converter110consuming power lower than in the related art may provide a sufficiently higher output voltage subsequent to the transition from the vertical blanking period PB to the effective video period PA even when a voltage drop occurs in the output voltage during the vertical blanking period PB as a light-load period (the analog power supply voltage AVDD). A liquid-crystal display apparatus including the boost DC-DC converter110may thus be implemented.

2. Second Embodiment

2.1 Outline

The entire configuration of the liquid-crystal display apparatus, the configuration generating the analog power supply voltage AVDD from the system power supply voltage VO, and the configuration of the switching control circuit15remain unchanged from those of the first embodiment (see FIGS.2through4). According to the first embodiment, the mode signal MD indicates that the control mode is the first mode. In a second embodiment, in contrast, the mode signal MD indicates that the control mode is the second mode (namely, the flag signal FLG is invalid). According to the first embodiment, the boost DC-DC converter110is controlled such that the pulse of the enable signal ENA is generated once every vertical blanking period PB. According to the second embodiment, in contrast, the boost DC-DC converter110is controlled such that the pulse of the enable signal ENA is generated twice every vertical blanking period PB. In the second embodiment, as well, the boost DC-DC converter110operates during the effective video period PA as a heavy-load period and during the vertical blanking period PB as a light-load period.

2.2 Measure Applied to Voltage Drop

A measure applied to the voltage drop is described below with reference toFIG.7.FIG.7illustrates, out of the waveform of the analog power supply voltage AVDD, a waveform from time t20through time t25denoted by a broken line where the measure disclosed in the specification is not taken.

A time duration prior to time t20is the effective video period PA. During the time duration, the switching pulse SWP having a relatively high frequency is generated. Specifically, the boost DC-DC converter110operates in the current continuation mode. The enable signal ENA and the forcing pulse setting signal POUT are maintained at a low level for the time duration. Since the flag signal FLG is invalid, the flag signal FLG is maintained at a low level for a time duration throughout which the liquid-crystal display apparatus operates.

At time t20, the effective video period PA transitions to the vertical blanking period PB. Also, at time t20, the enable signal ENA transitions from a low level to a high level. As illustrated inFIG.8, the set values are stored on the setting register21. The value of ST1is “8,” the value of W1is “4,” the value of ST2is “1,” and the value W2is “5.” The set values are stored on the setting register21such that the pulse of the enable signal ENA is generated twice every vertical blanking period PB. Since the value of ST1is “8,” the enable signal generator circuit22causes the enable signal ENA to transition from a low level to a high level eight horizontal scanning periods before the transition from the vertical blanking period PB to the effective video period PA. Since the control mode is the second mode (with the flag signal FLG being invalid), the forcing-pulse setting signal generator152outputs as the forcing pulse setting signal POUT a signal having the same waveform as the enable signal ENA. At time t20, the forcing pulse setting signal POUT also transitions from a low level to a high level. Although the effective video period PA transitions to the vertical blanking period PB in response to the transition of the forcing pulse setting signal POUT from a low level to a high level, the switching pulse generator153maintains the generation frequency of the switching pulse SWP at a relatively high frequency. As a result, at and subsequent to time t20, the operation mode of the boost DC-DC converter110is maintained in the current continuation mode.

With the value of W1being “4,” the enable signal generator circuit22causes the enable signal ENA from a high level to a low level four horizontal scanning periods after the enable signal ENA transitions from a low level to a high level. Specifically, at time t21, the enable signal ENA transitions from a high level to a low level. In response, the forcing pulse setting signal POUT transitions from a high level to a low level at time t21. The switching pulse generator153causes the generation frequency of the switching pulse SWP to transition from a relatively high frequency to a relatively low frequency in response to the transition of the forcing pulse setting signal POUT from a high level to a low level. At time t21, the operation mode of the boost DC-DC converter110is in the current discontinuation mode.

With the value of ST2being “1,” the enable signal generator circuit22causes the enable signal ENA to transition from a low level to a high level one horizontal scanning period before the vertical blanking period PB transitions to the effective video period PA. In this example, at time t22, the enable signal ENA transitions from a low level to a high level. In this example, at time t22, the enable signal ENA transitions from a low level to a high level. In response, at time t22, the forcing pulse setting signal POUT transitions from a low level to a high level. The switching pulse generator153causes the generation frequency of the switching pulse SWP to change from a relatively low frequency to a relatively high frequency in response to the transition of the forcing pulse setting signal POUT from a low level to a high level. In this way, at time t22, the switching frequency of the thin-film transistor12becomes higher. For the time duration starting at time t22, the boost DC-DC converter110operates in the current continuation mode.

At time t23, the vertical blanking period PB transitions to the effective video period PA. At time t24, the enable signal ENA transitions from a high level to a low level. In response, at time t24, the forcing pulse setting signal POUT transitions from a high level to a low level. In this way, although the forcing pulse setting signal POUT is at a low level at time t24, time t24is included in the effective video period PA. The generation frequency of the switching pulse SWP is thus maintained at a relatively high frequency.

In this example, the time duration from time t20to time t21and the time duration from time t22to time t24correspond to the first predetermined period. The time duration from time t20to time t21and the time duration from time t22to time t24correspond to multiple period segments included in the first predetermined period (two time durations).

The following discussion focuses on the waveform of the analog power supply voltage AVDD for the time duration from time t20to time t25. If the measure disclosed in the specification is not taken, the voltage value of the analog power supply voltage AVDD is substantially lower than a desired voltage value during a time duration immediately after the transition from the vertical blanking period PB to the effective video period PA. According to the second embodiment, in contrast, a larger variation in the voltage value of the analog power supply voltage AVDD (namely, the occurrence of a larger ripple voltage) during the vertical blanking period PB may be controlled by supplying the control terminal of the thin-film transistor12with the switching pulse SWP at a relatively high frequency in response to the first pulse of the enable signal ENA. The falling of the voltage value of the analog power supply voltage AVDD below the desired voltage value during the time duration immediately after the transition from the vertical blanking period PB to the effective video period PA may be controlled by supplying the control terminal of the thin-film transistor12with the switching pulse SWP at a relatively high frequency in response to the second pulse of the enable signal ENA. As a result, as illustrated inFIG.7, the voltage value of the analog power supply voltage AVDD is maintained to be high enough during the time duration immediately after the transition from the vertical blanking period PB to the effective video period PA.

2.3 Effect

The second embodiment, like the first embodiment, may provide the boost DC-DC converter110that consumes power lower than in the related art and results in a sufficiently higher output voltage after the transition from the vertical blanking period PB to the effective video period PA as a heavy-load period even when a voltage drop occurs in the output voltage (the analog power supply voltage AVDD) during the vertical blanking period PB as a light-load period. A liquid-crystal display apparatus including such a boost DC-DC converter may also be implemented.

3. Modifications

According to the first embodiment, the pulse of the enable signal ENA is generated once every vertical blanking period PB and according to the second embodiment, the pulse of the enable signal ENA is generated twice every vertical blanking period PB. The disclosure is not limited to this method. The pulse of the enable signal ENA may be generated three or more times every vertical blanking period PB.

According to the first and second embodiments, the boost DC-DC converter110operates with the effective video period PA as the heavy-load period and with the vertical blanking period PB as the light-load period. The disclosure is not limited to this method. The heave-load period and the light-load period may be interchanged depending on a display image.

According to the first and second embodiments, the boost DC-DC converter110is used in the liquid-crystal display apparatus. The disclosure is not limited to this configuration. The disclosure in the specification may be applicable to the boost DC-DC converter110used in an apparatus other than the liquid-crystal display apparatus.

4. Additional Notes

The disclosure has been described. The description of the disclosure is quoted for exemplary purposes only and is not intended to limit the disclosure. A variety of modifications and changes are possible without departing from the scope of the disclosure.

The present disclosure contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2022-132321 filed in the Japan Patent Office on Aug. 23, 2022, the entire contents of which are hereby incorporated by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.