Patent ID: 12249349

DETAILED DESCRIPTION

FIGS.1and2show an example of a disk drive100with which the subject matter of the present disclosure may be used. In this particular example, disk drive100has three platters101,102,103, although any number of platters may be included in a disk drive with which the subject matter of the present disclosure may be used. As shown, each platter101,102,103has, on each of its upper and lower surfaces111,112, a coating110made from a material in which data can be stored, e.g., magnetically. The present disclosure also is relevant to a disk drive in which one or more platters includes coating110on only one of its surfaces, but such a disk drive would store less data in the same volume than a disk drive with two-sided platters. The platters101-103are mounted on a rotatable spindle104. Spindle motor105rotates spindle104to rotate platters101-103in the direction of arrow A (FIG.2). Although spindle motor105is shown connected directly to spindle104, in some cases spindle motor105may be located off-axis of spindle104and would be connected to spindle104through belts or gears (not shown).

Read/write head assembly120includes an actuator121that bears arms122-125, one of which is disposed adjacent to each surface111,112of a platter101,102,103that has a memory storage coating110. In this example, with heads on both surfaces of each of arms123,124, that amounts to four arms122-125, but in the single-sided platter example discussed above, there would be only three arms. In other examples, the number of arms would increase or decrease along with the number of platters.

Each arm122-125bears, at or near its end furthest from actuator121, and on both its upper and lower surfaces in the case of arms123,124, a plurality of read heads/sensors and write heads. In this case, two sensors131,132are shown, and may represent, respectively, read and write sensors, although it in some applications each arm123,124may bear more than one read head/sensor and more than one write head (not shown). In the configuration shown inFIGS.1and2, arms122-125are aligned along a radius of platters101-103, bringing heads131,132as close as they can get to spindle104. It should be noted thatFIGS.1and2are schematic only and not to scale. Normally, the spindle diameter would be larger relative to the disk diameter. Moreover, arms122-125normally cannot point directly at the center of the disk.

Each of read heads131,132is connected to a read channel301of a hard drive controller300(there is a corresponding write channel302) (FIG.3). Hard drive controller300also includes a processor310and memory311, as well as a connection312to a host processor (not shown).

As noted above, when writing user data to a hard disk drive, a preamble followed by user data is written first. When reading the data, a clock has to be recovered from the data that is read, and the preamble must be long enough for clock recovery to occur while the preamble is being read. However, the longer the preamble, the more disk space is occupied by preamble data, leaving less space for user data. Therefore, if clock or timing recovery is too slow, a longer preamble is required, reducing the disk space available for user data and lowering the storage efficiency of the disk drive. It would be desirable to shorten the preamble to increase the disk space available for user data.

When reading data from a hard disk drive, the signal from the disk drive read head originates as an analog signal, which is digitized for further processing. A clock has to be recovered from the data that is read, for among other things, clocking an analog-to-digital converter for digitizing the data. In typical analog timing recovery techniques, information is fed back from the digital domain to an analog clock source—e.g., a phase-locked loop (PLL)--that clocks the ADC. The feedback loop typically introduces substantial latency based on, e.g., the latency of zero-phase start circuitry, which adjusts the sampling phase, as well as the latency of timing accumulator circuitry. If the disk drive uses two heads, as in two-dimensional magnetic recording (TDMR) implementations, additional latency is introduced by any buffering needed to account for the distance between read heads.

However, a digital timing recovery technique may be provided which eliminates the effects of latency of zero-phase start operations and associated timing accumulation operations. In implementations of this technique, the analog timing is completely separated from the digital timing. The ADC in the analog domain, which digitizes the read-head signals, is clocked by a free-running clock (which may be provided, e.g., by a PLL). There is no feedback to that clock from the digital domain. However, in order to assure that the ADC conversion is not undersampled, the analog clock is deliberately oversampled so that is it certain to be no slower than the target clock to be recovered in the digital domain.

The digitized data from the read head or heads is buffered while zero-phase start operations are performed to determine a starting phase and magnitude which are fed forward (instead of being fed back as in analog timing recovery) to interpolation operations to recover the clock. If two or more heads are used, a delay or delays are used to align the respective signals from the different heads before buffering. However, zero-phase start operations will not function correctly on the oversampled signals. Therefore, in accordance with implementations of the subject matter of this disclosure, effects of the oversampling are removed by phase rotation, which may be thought of as equivalent to downsampling the signals back to their original sampling rate.

The zero-phase start operation begins with a DFT operation on the preamble data, to derive sine and cosine coefficients, which are accumulated to provide inputs to a CORDIC operation that determines the ZPS phase angle, which is converted into a sampling time adjustment. The preamble may be a 2T tone (11001100 . . . ), a 3T tone (111000111000 . . . ), or a 4T tone (1111000011110000 . . . ), requiring different CORDIC resolution. The number of CORDIC iterations may be selected for the highest required resolution. For example, ten iterations may provide the required resolution for the 4T case, without imposing a significant burden on the 2T or 3T case, even though fewer iterations may be sufficient in those cases. Once the ZPS angle has been determined, it may be converted to a ZPS time jump (i.e., sampling time adjustment) using, e.g., a single look-up table whose values may be multiplied by 2, 3 or 4, respectively, for a 2T, 3T or 4T preamble. A further correction may be implied taking into account the oversampling factor. Further adjustments or corrections may be applied by the user--in either the oversampled domain or the downsampled domain or both--to account for, e.g., constant errors due to media defects.

As noted above, phase rotation of the digitized oversampled signals may be performed prior to the zero-phase start operation to eliminate the effect of oversampling on the zero-phase start operation. In accordance with some implementations of the subject matter of this disclosure, the phase rotation may be performed by a two-tap finite-impulse-response (FIR) filter.

Coefficients of the phase rotation FIR filter may be calculated as described below, based on the ZPS length which determines the number of samples, and on the oversampling factor. In a disk drive, a separate set of phase rotation coefficients may be recomputed for each zone of each disk surface. Moreover, the coefficients change on each clock cycle for the then-current set of samples. There are multiple zones on every disk surface, two surfaces on every disk platter, and multiple platters in every drive, meaning that a large number of sets coefficients may be required.

The set of coefficients for the current zone of the current surface of the current platter may be read from a look-up table (e.g., under control of a read-channel processor). The coefficients may be computed in advance by software or firmware and loaded into the look-up table. However, given the large number of zones, the size of a look-up table needed to store all of the coefficients if precomputed could be prohibitive, except for the smallest drives. Once a drive reaches a certain size, it may be more efficient to use hardware circuitry to compute a new set of coefficients for a zone as the zone becomes active. This limits the size of the look-up table that would be needed to the size necessary to contain coefficients for the current zone and one upcoming zone. Moreover, the hardware computation may be faster than a software computation.

In an alternative simplified implementation, an approximation may be used for each set of coefficients, and appropriate biasing or correction factors may be applied during the zero-phase start operation to compensate for the approximation.

Implementations of the subject matter of this disclosure may be better understood by reference toFIGS.4-16.

The nature of the problem to be solved may be appreciated fromFIGS.4and5.FIG.4is a representation of a data packet400to be read from a hard disk drive. In addition to the actual user data payload401, data packet400includes a sync mark411to aid in locating packet400, and a preamble421from which zero-phase start circuitry may determine the starting phase. As seen inFIG.5, before the ZPS operation500, ADC samples501occur at seemingly random times during the clock cycle. ZPS operation500runs the initial bits of the preamble through a DFT operation, to derive a phase adjustment after which ADC samples510are regularly distributed relative to the clock.

In a two-head read channel circuit600configured for digital timing recovery, shown inFIG.6, signal602from leading read head601is processed through analog front end AFE-1(603) and then is digitized at analog-to-digital converter ADC-1(604). Signal612from trailing read head611is processed through analog front end AFE-2(613) and then is digitized at analog-to-digital converter ADC-2(614). Digitized leading-head signal605is delayed at606so that digitized trailing-head signal617can catch up and the two signals607,617are aligned.

Aligned delayed signals607,617can be buffered as long as necessary in separate buffers—DTR Buffer-1(715) and DTR Buffer-2(716)—for the signals from leading read-head601and the signals from trailing read-head611, respectively, until rotation operations in rotation filter714, and ZPS operations in ZPS circuitry629can be completed and the ZPS output717can be processed through timing accumulator718.

Instead of being fed back, the output of ZPS circuitry629is fed forward, to interpolation circuitry710that adjusts the clock phase as described below. There is no feedback from the digital clock domain701to the analog clock domain702. Accordingly, to ensure that the analog sampling clock730, which is not adjusted based on feedback, that clocks ADCs604,614is not too slow, PLL711, which has a free-running reference clock input712, is overclocked by oversampling factor (OSF)713. The digital clock domain701is thus divided into an oversampled clock subdomain751upstream of interpolation circuitry710, and a bit-rate clock subdomain761downstream of interpolation circuitry710.

Interpolation circuitry710may include separate interpolation filters—Interpolation Filter-1(719) and Interpolation Filter-2(720)—for the signals from leading read-head601and the signals from trailing read-head611, respectively, as well as an interpolation bank721which may select from among predetermined sets of coefficients for interpolation filters719,720based on ZPS output717as processed through timing accumulator718.

Interpolated data signals722,723from interpolation filters719,720are clocked into first-in-first-out (FIFO) circuit724based on oversampled clock730but are clocked out of FIFO circuit724based on bit-rate clock725. FIFO output signals726,727are equalized in finite impulse response filters FIR-1(608) and FIR-2(618) and the equalized signals609,619are combined at620. The combined signal621passes through a Viterbi detector622to derive user data401. The output623of Viterbi detector622is compared at624to signal621to yield a timing error signal626detected by timing error detector625. Timing error signal626passes through timing loop627and is combined in timing accumulator718with the phase correction717determined by ZPS circuitry629, providing selection signal728for interpolation bank721to select from among predetermined sets of coefficients for interpolation filters719,720as discussed above.

Selection signal728may represent a phase shift of the oversampled signal relative to the desired phase, determined as follows:if (PHASE SHIFT <0)NEXT PHASE SHIFT=PHASE SHIFT+1.0elseNEXT PHASE SHIFT=PHASE SHIFT−(OSF+phase_error)if (NEXT PHASE SHIFT <0)SKIP CLOCK=1elseSKIP CLOCK=0
That is, if the current phase shift (i.e., the phase of an interpolated sample relative to the desired phase) is negative, then the phase shift is increased by one clock period to make the phase shift positive. Otherwise, if the current phase shift is positive, the phase shift is decreased by the sum of the OSF and the measured phase error. And if the phase shift as so adjusted is still negative, then the phase skips forward one period.

Although digital timing recovery circuitry600is shown as accommodating two heads, digital timing recovery circuitry in accordance with implementations of this disclosure may work with only one head, or with three (or more) heads. In a one-head implementation, one of DTR Buffer-1(715) and DTR Buffer-2(716) and one of Interpolation Filter-1(719) and Interpolation Filter-2(720) may be omitted, or forced to zero, and rotation filter714and ZPS circuitry629may operate with a single input. Additional circuitry may be provided if there are additional heads.

As noted above, implementations of this disclosure are intended to minimize the length of the preamble to maximize the amount of space available for user data. Accordingly, using techniques in accordance with implementations of this disclosure may not speed up performance of the various calculations required (phase rotation, zero-phase start, etc.). Rather, because the digital data from the read head or heads may be held in the DTR buffer or buffers as long as is necessary for those calculations to be performed (which in some cases may actually increase the overall time required), the size of the preamble, and therefore the storage space for the preamble, is determined simply by the length of the Discrete Fourier Transform of the preamble tone, which may be a 2T tone, a 3T tone or a 4T tone.

ZPS circuitry629will not operate correctly on an oversampled clock. Therefore, digital timing recovery circuitry600includes a rotation filter714, upstream of ZPS circuitry629, to filter out the effect of OSF713.

Rotation filter714may be a two-tap FIR filter as shown inFIG.7. An input sample771is multiplied by coefficients f0nat tap772, and, after a delay773, by coefficients f1nat tap774. In accordance with implementations of the subject matter of this disclosure, the coefficients f0n, f1nmay implement a minimum mean square error (MMSE) rotation filter as follows:

f0n=cos⁢(n⁢π⁢xp)-cos⁢(π[(n-2)⁢x+2]p)1-cos⁢(2⁢π⁡(x-1)p)=cos⁢(n⁢π⁢xp)+cos⁢(π⁡(1-x)p)sin⁢(π⁡(1-x)p)·sin⁢(n⁢π⁢xp)andf1n=cos⁢(π[(n-1)⁢x+1]p)-cos⁢(π[(n+1)⁢x-1]p)1-cos⁢(2⁢π⁡(x-1)p)=-1sin⁢(π⁡(1-x)p)·sin⁢(n⁢π⁢xp)
where:

cos⁢(π⁢n⁢xp)
is the desired output,x is the oversampling factor,n=0, 1, 2, . . . , N−1 for the (n+1) th sample of an N-sample ZPS operation, andp=2, 3, 4 depending on whether signal has 2T preamble, a 3T preamble or a 4T preamble.

As seen inFIG.8, which is a simplified version800ofFIG.6, the rotation filter coefficients may be loaded into a look-up table (LUT)801, and the rotation filters714provide phase-rotated signals802which are combined at803for input to ZPS circuitry629. In the case, e.g., of a disk drive, the appropriate set of rotation filter coefficients is loaded (e.g., under control of read-channel processor310) for the zone being read, and cycle through the N rotation filter coefficients (n=0, . . . , N−1).

The rotation filter coefficients may be precomputed when the system (e.g., a disk drive) is set up, and loaded into LUT801. However, for a large system, such as a disk drive with multiple two-sided platters, a look-up table large enough to store all rotation filter coefficients for all zones may be impractical and it may take too long to precompute so many rotation filter coefficients. Therefore, in accordance with implementations of the subject matter of this disclosure, the rotation filter coefficients may be determined by circuitry configured for that purpose, as described below. In some implementations, that circuitry will operate to determine a set of rotation filter coefficients for the current zone and will load a look-up table with those currently-determined rotation filter coefficients.

FIG.9shows one simplified implementation of circuitry900for determining the rotation filter coefficients. Sine computation circuitry902may be hard-wired to determine the sine912of input901and the cosine computation circuitry903may be hard-wired to determine the cosine913of input901. Multiplier circuitry904may be hard-wired to determine the product of sine912and

-1sin⁢(π⁡(1-x)p)
to yield f1n. Similarly, multiplier circuitry905may be hard-wired to determine the product of

-cos⁢(π⁡(1-x)p)
and the output of multiplier circuitry904, and adder906may be hard-wired to determine the sum of the output of multiplier circuitry905and the output913of cosine computation circuitry903to yield f0n. The f0ncoefficients are thus a function of the f1ncoefficients.

One specific implementation1000of circuitry900for determining the rotation filter coefficients is shown inFIG.10. Because circuitry1000has to perform multiple calculations (seeFIG.9) for each nth iteration of the N samples of each ZPS operation, circuitry1000is configured for multiple pipelined computations. A plurality of separate circuits1001are provided, each of which is configured to perform a particular mathematical operation. Operations from different stages of the pipelined computations may be performed simultaneously.

In the implementation shown, circuits1001include one adder circuit1011, one accumulator circuit1021, three multiplier circuits1031, one CORDIC (Coordinate Rotation DIgital Computer) circuit1041for performing sine and cosine operations, one divider circuit1051, and two delay circuits or lines1061, as well as “variables” circuit1071that is configured to compute certain combinations of inputs that are used repeatedly, such as, e.g.,

n⁢π⁢xp.
A multi-input/multi-output multiplexer1002is a fully populated crossbar switch configured to make any connection between any of its inputs1012and any of its outputs1022, to enable any of the various circuits1001to accept as inputs the outputs of others of the various circuits1001, combined in the correct order or sequence, under control of controller circuit1003, which also supplies certain constants, including n, x, π/2, π/3, and π/4 to ones of inputs1012, to complete the required operations. Controller circuit1003may be implemented as a state machine configured with the foregoing expressions for f0nand f1n.

Alternatively, instead of using CORDIC circuit1041to compute sine and cosine values, one can use an alternate circuit (not shown) configured to perform a Taylor series to find sine values:

sin⁢(t)=∑i=0∞(-1)i(2⁢i+1)!⁢t(2⁢i+1)≈t-t33!+t55!-t77!+t99!
and then to use the known relationship between sine and cosine:

cos⁡(t)=sin⁢(t+π2)
to find cosine values. Alternatively, one can use the separate Taylor series for cosine values:

cos⁡(t)=∑i=0∞(-1)i(2⁢i)!⁢t(2⁢i)≈t-t22!+t44!-tó6!+t88!

Because the various intermediate computations performed by circuitry1000may have different numbers of decimal places and different orders of magnitude, the various circuits1001may be implemented for floating-point operations. However, digital timing recovery circuitry600may be implemented for fixed-point operations. Therefore, circuitry1000may include floating-point-to-fixed-point converters1004, to convert the floating-point outputs to fixed-point representations for storage in the coefficient memory1005, which may serve as look-up table801.

In some implementations, particularly for small oversampling factors x, the expressions for f0nand f1nmay be simplified, so that they are independent of each other. For example, for a 2T preamble (i.e., p=2) and x=0.05,

cos⁢(π⁡(1-x)p)sin⁢(π⁡(1-x)p)=0.0787,
which is close to zero, although it is somewhat larger for p=3 (0.6494) or p=4 (1.08179), and even larger for larger oversampling factors x. Nevertheless, if one assumes that

cos⁢(π⁡(1-x)p)sin⁢(π⁡(1-x)p)=0,
then one can approximate

f0n⁢as⁢cos⁡(n⁢π⁢xp),
which may be sufficient, particularly for small oversampling factors x.

Similarly, for a 2T preamble (i.e., p=2) and x=0.05,

1sin⁢(π⁡(1-x)p)=1.003,
which is close to 1, although it is somewhat larger for p=3 (1.19236) or p=4 (1.473186), and even larger for larger oversampling factors x. Nevertheless, if one assumes that

1sin⁢(π⁡(1-x)p)=1,
then one can approximate f1nas

-sin⁡(n⁢π⁢xp),
which may be sufficient, particularly for small oversampling factors x.

Accordingly, for implementations where the simplifications that

f0n=cos⁢(n⁢π⁢xp)⁢and⁢f1n=-sin⁢(n⁢π⁢xp)
are sufficient, simplified digital timing recovery circuitry1100, seen inFIG.11, may be provided. Digital timing recovery circuitry1100is similar to digital timing recovery circuitry800, except that MMSE rotation filter LUT801, which stores the unsimplified rotation filter coefficients, is replaced by rotation filter LUT1101, which stores the simplified rotation filter coefficients, and a magnitude and phase bias circuit1102is added as an input to ZPS circuitry629, to compensate for inaccuracies introduced by the use of the simplified coefficients.

Specifically,FIG.12shows how the detected magnitude1201varies about an average value1202below the actual magnitude1203. By using bias circuit1102to add a bias value1204, the resulting compensated detected magnitude1301varies closely about the actual magnitude1203, as seen inFIG.13. Similarly, as seen inFIG.14, the detected phase1401is slightly to the left of the actual phase1402as seen inFIG.14, but using bias circuit1102to add a phase bias to detected phase1401can shift the detected phase bias to more closely overlap the actual phase1402as seen inFIG.15.

A method1600according to implementations of the subject matter of this disclosure is diagrammed inFIG.16. Method1600begins at1601, where, for digital timing recovery from oversampled analog signals, filter coefficients for digitized samples of the oversampled analog signals are computed based on an oversampling factor of the oversampled analog signals. At1602, the filter coefficients are used in a rotation filter to compensate for the oversampling factor in the digitized samples of the oversampled analog signals. At1603, a starting phase and magnitude are derived from the compensated digitized samples of the oversampled analog signals. At1604, the starting phase and magnitude are used in a timing recovery loop to recover a clock from the compensated digitized samples of the oversampled analog signals. Method1600then ends.

Thus it is seen that a rotation filter to compensate, in digital timing recovery, for oversampling of analog signals, and techniques and circuitry for determining coefficients for such a filter, have been provided.

As used herein and in the claims which follow, the construction “one of A and B” shall mean “A or B.”

It is noted that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.