Patent ID: 12238917

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1is a schematic isometric view of a memory device100in accordance with some embodiments of the present disclosure.FIG.2is a schematic cross-sectional side view of the memory device100along a line A-A inFIG.1.FIG.3is a schematic cross-sectional side view of the memory device100along a line B-B inFIG.1.FIG.5is a schematic cross-sectional side view of the memory device100along a line C-C inFIG.1. In some embodiments, the memory device100includes several unit cells arranged in rows and columns.

In some embodiments, the memory device100includes a semiconductor substrate104. In some embodiments, the semiconductor substrate104is semiconductive in nature. In some embodiments, the semiconductor substrate104is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate104is a silicon substrate.

In some embodiments, the semiconductor substrate104is defined with a peripheral region (not shown) and an array region101. In some embodiments, the array region101is at least partially surrounded by the peripheral region. In some embodiments, the peripheral region is adjacent to a periphery of the semiconductor substrate104, and the array region101is adjacent to a central area of the semiconductor substrate104. In some embodiments, the array region101may include electronic components such as capacitors, transistors or the like. In some embodiments, several capacitors111are disposed within the array region101. In some embodiments, a boundary is disposed between the peripheral region and the array region101.

In some embodiments, a top electrodes pick up region102and a bottom electrodes pick up region103are further defined in the array region101. In some embodiments, top electrodes110of the capacitors111are connected to the top electrodes pick up region102, such that electrical signals from the top electrodes110can be gathered and picked up at the top electrodes pick up region102. In some embodiments, bottom electrodes106of the capacitors111are connected to the bottom electrodes pick up region103, such that electrical signals from the bottom electrodes106can be gathered and picked up at the bottom electrodes pick up region103.

In some embodiments, the memory device100includes an insulating layer105disposed over the semiconductor substrate104. In some embodiments, the insulating layer105is formed of a dielectric material, such as silicon oxide or the like. In some embodiments, a first insulating layer105ais disposed on the semiconductor substrate104.

In some embodiments, the memory device100includes a bottom electrode106disposed over the insulating layer105. In some embodiments, the bottom electrode106includes conductive material such as tungsten (W) or the like. In some embodiments, a first bottom electrode106ais disposed on the first insulating layer105a. In some embodiments, the first bottom electrode106acovers the first insulating layer105a.

In some embodiments, the memory device100includes a dielectric layer107disposed over the bottom electrode106. In some embodiments, the dielectric layer107is formed of a dielectric material, such as silicon oxide or the like. In some embodiments, a first dielectric layer107ais disposed on the first bottom electrode106a. In some embodiments, the memory device100includes a recess117extending through and laterally within the dielectric layer107. In some embodiments, the recess117exposes at least a portion of the bottom electrode106. In some embodiments, the portion of the bottom electrode106is in a strip shape. In some embodiments, a first recess117aextends through the first dielectric layer107aand exposes at least a portion of the first bottom electrode106a. In some embodiments, the first recess117aextends laterally within the first dielectric layer107a.

In some embodiments, the memory device100includes a capacitor dielectric (108and109) disposed conformal to the recess117and in contact with the bottom electrode106. In some embodiments, the capacitor dielectric (108and109) is disposed along a sidewall of the recess117and on the bottom electrode106exposed through the dielectric layer107. In some embodiments, the capacitor dielectric (108and109) extends laterally within and along the recess117. In some embodiments, the capacitor dielectric (108and109) has a cross-section in a U shape. In some embodiments, the capacitor dielectric (108and109) extends laterally over the bottom electrode106and the semiconductor substrate104.

In some embodiments, the capacitor dielectric (108and109) includes a nitride liner108conformal to the recess117and a high-k (high dielectric constant) liner109over the nitride liner108. In some embodiments, the nitride liner108includes titanium nitride (TiN) or the like, and the high-k liner109includes high-k dielectric material such as hafnium dioxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2) or the like. In some embodiments, a first capacitor dielectric (108aand109a) is disposed conformal to the first recess117aand on the first bottom electrode106aexposed through the first dielectric layer107a. In some embodiments, the first capacitor dielectric (108aand109a) extends laterally over the first bottom electrode106aand the semiconductor substrate104.

In some embodiments, the first capacitor dielectric (108aand109a) includes a first nitride liner108aconformal to the first recess117aand a first high-k liner109aover the first nitride liner108a. In some embodiments, the first nitride liner108ais in contact with the first bottom electrode106aexposed through the first dielectric layer107. In some embodiments, the first nitride liner108aand the first high-k liner109aextend laterally within and along the first recess117a.

In some embodiments, the memory device100includes a top electrode110disposed within the recess117and surrounded by the capacitor dielectric (108and109). In some embodiments, the top electrode110extends laterally within and along the recess117. In some embodiments, the top electrode110extends laterally over the bottom electrode106and the semiconductor substrate104. In some embodiments, the top electrode110includes conductive material such as tungsten (W) or the like. In some embodiments, a first top electrode110ais disposed within the first recess117aand is surrounded by the first capacitor dielectric (108aand109a). In some embodiments, the first top electrode110aextends laterally over the first bottom electrode106aand the semiconductor substrate104.

In some embodiments, a first capacitor111ais disposed at a first level. In some embodiments, the first capacitor111aincludes the first bottom electrode106a, the first capacitor dielectric (108aand109a) and the first top electrode110a. In some embodiments, the first capacitor111ais disposed on the first insulating layer105a. In some embodiments, the first capacitor111aand the first insulating layer105aare deemed as a first level of the memory device100.

In some embodiments, the memory device100includes a second insulating layer105bdisposed over the first top electrode110aand the first dielectric layer107a. In some embodiments, the second insulating layer105bis formed of a dielectric material, such as silicon oxide or the like. In some embodiments, the first insulating layer105aand the second insulating layer105binclude same material. In some embodiments, the first insulating layer105aand the second insulating layer105bare in similar configurations.

In some embodiments, the memory device100includes a second bottom electrode106bdisposed over the second insulating layer105b. In some embodiments, the second bottom electrode106bincludes conductive material such as tungsten (W) or the like. In some embodiments, the second bottom electrode106bcovers the second insulating layer105b. In some embodiments, the first bottom electrode106aand the second bottom electrode106bare in similar configurations.

In some embodiments, the memory device100includes a second dielectric layer107bdisposed over the second bottom electrode106b. In some embodiments, the second dielectric layer107bis formed of a dielectric material, such as silicon oxide or the like. In some embodiments, the first dielectric layer107aand the second dielectric layer107bare in similar configurations. In some embodiments, the memory device100includes a second recess117bextending through the second dielectric layer107band exposing at least a portion of the second bottom electrode106b. In some embodiments, the second recess117bextends laterally within the second dielectric layer107b. In some embodiments, the first recess117aand the second recess117bare in similar configurations.

In some embodiments, the memory device100includes a second capacitor dielectric (108band109b) conformal to the second recess117band in contact with the second bottom electrode106b. In some embodiments, the second capacitor dielectric (108band109b) extends laterally over the second bottom electrode106band the semiconductor substrate104. In some embodiments, the second capacitor dielectric (108band109b) includes a second nitride liner108bconformal to the second recess117band a second high-k liner109bover the second nitride liner108b. In some embodiments, the second nitride liner108bincludes titanium nitride (TiN) or the like, and the second high-k liner109bincludes high-k dielectric material such as hafnium dioxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2) or the like. In some embodiments, the first capacitor dielectric (108aand109a) and the second capacitor dielectric (108band109b) are in similar configurations.

In some embodiments, the memory device100includes a second top electrode110bdisposed within the second recess117band surrounded by the second capacitor dielectric (108band109b). In some embodiments, the second top electrode110bextends laterally over the second bottom electrode106band the semiconductor substrate104. In some embodiments, the second top electrode110bincludes conductive material such as tungsten (W) or the like. In some embodiments, the first top electrode110aand the second top electrode110bare in similar configurations. In some embodiments, the second top electrode110bis above the first top electrode110a. In some embodiments, the second top electrode110bis offset from the first top electrode110a.

In some embodiments, a second capacitor111bis disposed at a second level. In some embodiments, the second capacitor111bincludes the second bottom electrode106b, the second capacitor dielectric (108band109b) and the second top electrode110b. In some embodiments, the second capacitor111bis disposed on the second insulating layer105b. In some embodiments, the second capacitor111band the second insulating layer105bare deemed as a second level of the memory device100.

In some embodiments, the memory device100includes a third insulating layer105c, a third bottom electrode106c, a third dielectric layer107c, a third recess117c, a third capacitor dielectric (108cand109c) and a third top electrode110c. In some embodiments, the third insulating layer105is disposed over the second top electrode110band the second dielectric layer107b. In some embodiments, the third bottom electrode106cis disposed over the third insulating layer105c. In some embodiments, the third dielectric layer107cis disposed over the third bottom electrode106c. In some embodiments, the third recess117cextends through the third dielectric layer107c. In some embodiments, the third capacitor dielectric (108cand109c) is conformal to the third recess117cand in contact with the third bottom electrode106c. In some embodiments, the third top electrode110cis disposed within the third recess117cand surrounded by the third capacitor dielectric (108cand109c). In some embodiments, the third capacitor dielectric (108cand109c) and the third top electrode110cextend laterally over the third bottom electrode106cand the semiconductor substrate104.

In some embodiments, the third insulating layer105c, the third bottom electrode106c, the third dielectric layer107c, the third recess117c, the third capacitor dielectric (108cand109c) and the third top electrode110care in configurations similar to those of the first insulating layer105a, the first bottom electrode106a, the first dielectric layer107a, the first recess117a, the first capacitor dielectric (108aand109a) and the first top electrode110a, respectively. In some embodiments, the third insulating layer105c, the third bottom electrode106c, the third dielectric layer107c, the third recess117c, the third capacitor dielectric (108cand109c) and the third top electrode110care in configurations similar to those of the second insulating layer105b, the second bottom electrode106b, the second dielectric layer107b, the second recess117b, the second capacitor dielectric (108band109b) and the second top electrode110b, respectively.

In some embodiments, the third top electrode110cis disposed above the first top electrode110aand the second top electrode110b. In some embodiments, the third top electrode110cis vertically aligned with the first top electrode110a. In some embodiments, the third top electrode110cis offset from the second top electrode110b. In some embodiments, a portion of the second dielectric layer107bis disposed between the first top electrode110aand the third top electrode110c.

In some embodiments, a third capacitor111cis disposed at a third level. In some embodiments, the third capacitor111cincludes the third bottom electrode106c, the third capacitor dielectric (108cand109c) and the third top electrode110c. In some embodiments, the third capacitor111cis disposed on the third insulating layer105c. In some embodiments, the third capacitor111cand the third insulating layer105care deemed as a third level of the memory device100.

In some embodiments, the memory device100includes several of the first recesses117aextending through the first dielectric layer107a, several of the first capacitor dielectrics (108aand109a) conformal to the first recesses117a, respectively, and in contact with the first bottom electrode106a, and several of the first top electrodes110adisposed within the first recesses117a, respectively, and surrounded by the first capacitor dielectrics (108aand109a), respectively. In some embodiments, the first top electrodes110aare electrically connected to the first bottom electrode106a. In some embodiments, the first capacitor dielectrics (108aand109a) are electrically connected in parallel. In some embodiments, the first top electrodes110aare electrically connected in parallel. In some embodiments, top surfaces of the first top electrodes110aare substantially coplanar with each other. In some embodiments, the first top electrodes110aare disposed between the first bottom electrode106aand the second insulating layer105b. In some embodiments, lengths L1of the first top electrodes110aare substantially equal.

In some embodiments, as shown inFIGS.1,2,3and5, the memory device100has capacitors111arranged in three levels. However, it can be understood that the memory device100can have more levels and the capacitors111can be stacked in additional levels. In some embodiments, as shown inFIG.4, the memory device100has capacitors111arranged in five levels. In some embodiments, as shown inFIG.4, a fourth insulating layer105d, a fourth bottom electrode106d, a fourth dielectric layer107d, a fourth capacitor dielectric (not shown) and a fourth top electrode (not shown), a fifth insulating layer105e, a fifth bottom electrode106e, a fifth dielectric layer107e, a fifth capacitor dielectric (108eand109e) and a fifth top electrode (110e), are sequentially formed.

In some embodiments, the memory device100includes a last insulating layer115covering the capacitors111. In some embodiments, the last insulating layer115is formed of a dielectric material, such as silicon oxide or the like. In some embodiments, the last insulating layer115is disposed over the third dielectric layer107cand the third top electrode110c. In some embodiments, the last insulating layer115is disposed over the fifth dielectric layer107eand the fifth top electrode110e.

In some embodiments, the last insulating layer115is disposed on the first top electrode110aand the third top electrode110cat the top electrode pick up region102. In some embodiments, a length L1of the first top electrode110ais substantially greater than a length L2of the third top electrode110c. In some embodiments, a part of the memory device100at the top electrode pick up region102is in a stair configuration. In some embodiments, the third top electrode110cand the first top electrode110aare electrically connected in parallel by a first conductive feature112. In some embodiments, the first conductive feature112is disposed at the top electrode pick up region102and is at least partially exposed through a dielectric material119on the last insulating layer115. In some embodiments, the first conductive feature112includes conductive material such as copper, silver or the like.

In some embodiments, the first conductive feature112includes a first conductive via112ain contact with the first top electrode110a, a second conductive via112bin contact with the third top electrode110c, and a top electrode plate112ddisposed on the dielectric material119. In some embodiments, the first conductive via112aand the second conductive via112bextend through the dielectric material119. In some embodiments, a height of the first conductive via112ais substantially greater than a height of the second conductive via112b.

In some embodiments, as shown inFIG.4, the last insulating layer115is disposed over the first top electrode110a, the third top electrode110cand the fifth top electrode110eat the top electrode pick up region102. In some embodiments, the length L1of the first top electrode110ais substantially greater than the length L2of the third top electrode110c, and the length L2is substantially greater than a length L3of the fifth top electrode110e. In some embodiments, a part of the memory device100at the top electrode pick up region102is in a stair configuration.

In some embodiments, the fifth top electrode110e, the third top electrode110cand the first top electrode110aare electrically connected in parallel by the first conductive feature112. In some embodiments, the first conductive feature112is disposed at the top electrode pick up region102and is surrounded by a dielectric material119on the last insulating layer115. In some embodiments, the first conductive feature112includes conductive material such as copper, silver or the like.

In some embodiments, the first conductive feature112includes the first conductive via112ain contact with the first top electrode110a, the second conductive via112bin contact with the third top electrode110c, a third conductive via112cin contact with the fifth top electrode110e, and a top electrode plate112ddisposed on the dielectric material119. In some embodiments, the first conductive via112a, the second conductive via112band the third conductive via112cextend through the dielectric material119. In some embodiments, the height of the first conductive via112ais substantially greater than the height of the second conductive via112b, and the height of the second conductive via112bis substantially greater than a height of the third conductive via112c.

In some embodiments, as shown inFIG.5, the last insulating layer115is disposed on the third dielectric layer107cat the bottom electrodes pick up region103. In some embodiments, the first bottom electrode106a, the second bottom electrode106band the third bottom electrode106care electrically connected in parallel by a second conductive feature113. In some embodiments, the second conductive feature113is disposed at the bottom electrodes pick up region103and is at least partially exposed through the last insulating layer115. In some embodiments, the second conductive feature113includes conductive material such as copper, silver or the like.

In some embodiments, the second conductive feature113includes a fourth conductive via113ain contact with the first bottom electrode106a, a fifth conductive via113bin contact with the second bottom electrode106b, a sixth conductive via113cin contact with the third bottom electrode106c, and a bottom electrode plate113ddisposed on the last insulating layer115. In some embodiments, the fourth conductive via113aextends through the first dielectric layer107a, the second insulating layer105b, the second bottom electrode106b, the second dielectric layer107b, the third insulating layer105c, the third bottom electrode106c, the third dielectric layer107cand the last insulating layer115.

In some embodiments, the fifth conductive via113bextends through the second dielectric layer107b, the third insulating layer105c, the third bottom electrode106c, the third dielectric layer107cand the last insulating layer115. In some embodiments, the sixth conductive via113cextends through the third dielectric layer107cand the last insulating layer115. In some embodiments, the bottom electrode plate113dis disposed over the last insulating layer115and is in contact with the fourth conductive via113a, the fifth conductive via113band the sixth conductive via113c. In some embodiments, a height of the fourth conductive via113ais substantially greater than a height of the fifth conductive via113b. In some embodiments, the height of the fifth conductive via113bis substantially greater than a height of the sixth conductive via113c.

FIG.6is a flow diagram illustrating a method S200of manufacturing an intermediate structure of a memory device100in accordance with some embodiments of the present disclosure, andFIGS.7to28illustrate cross-sectional views of intermediate stages in formation of the intermediate structure of the memory device100as shown inFIG.1along the line A-A in accordance with some embodiments of the present disclosure.

The stages shown inFIGS.7to28are also illustrated schematically in the flow diagram inFIG.6. In following discussion, the fabrication stages shown inFIGS.7to28are discussed in reference to process steps shown inFIG.6. The method S200includes a number of operations, and description and illustration are not deemed as a limitation to a sequence of the operations. The method S200includes a number of steps (S201, S202, S203, S204, S205, S206and S207).

Referring toFIG.7, a semiconductor substrate104is provided according to step S201inFIG.6. In some embodiments, the semiconductor substrate104is semiconductive in nature. In some embodiments, the semiconductor substrate104is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate104is a silicon substrate. In some embodiments, the semiconductor substrate104is defined with a peripheral region (not shown) and an array region101. In some embodiments, a top electrodes pick up region102(shown inFIG.2) and a bottom electrodes pick up region103are further defined in the array region101.

Referring toFIG.8, a first insulating layer105ais disposed over the semiconductor substrate104according to step S202inFIG.6. In some embodiments, the disposing of the first insulating layer105aincludes disposing an insulating material such as oxide over the semiconductor substrate104by deposition or any other suitable process.

Referring toFIG.9, a first bottom electrode106ais disposed over the first insulating layer105aaccording to step S203inFIG.6. In some embodiments, the disposing of the first bottom electrode106aincludes disposing a conductive material such as tungsten (W) over the first insulating layer105aby deposition, chemical vapor deposition (CVD) or any other suitable process.

Referring toFIG.10, a first dielectric layer107ais disposed over the first bottom electrode106aaccording to step S204inFIG.6. In some embodiments, the disposing of the first dielectric layer107aincludes disposing an insulating material such as oxide over the first bottom electrode106aby deposition or any other suitable process.

Referring toFIGS.11and12, a portion of the first dielectric layer107ais removed to form a first recess117aextending through the first dielectric layer107aaccording to step S205inFIG.6. In some embodiments, the removal of the portion of the first dielectric layer107aincludes removing a first portion of the first dielectric layer107ato form an opening117a′ partially through the first dielectric layer107aas shown inFIG.11, and then removing a second portion of the first dielectric layer107aexposed through the opening117a′ to form the first recess117aat least partially exposing the first bottom electrode106aas shown inFIG.12. In some embodiments, the second portion of the first dielectric layer107ais removed by isotropic wet etching or any other suitable process.

Referring toFIGS.13and14, a first capacitor dielectric (108aand109a) is disposed conformal to the first recess117aand over the first bottom electrode106aaccording to step S206inFIG.6. In some embodiments, the disposing of the first capacitor dielectric (108aand109a) includes disposing a first nitride liner108aover the first dielectric layer107aand conformal to the first recess117aas shown inFIG.13, and then disposing a first high-k liner109aover the first nitride liner108aas shown inFIG.14. In some embodiments, the first nitride liner108aand the first high-k liner109aare disposed by deposition, CVD or any other suitable process.

In some embodiments, the first nitride liner108ais in contact with the first bottom electrode106aexposed through the first dielectric layer107a. In some embodiments, the first nitride liner108aincludes titanium nitride (TiN) or the like, and the first high-k liner109aincludes high-k dielectric material such as hafnium dioxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2) or the like.

Referring toFIGS.15and16, a first top electrode110ais formed within the first recess117aand surrounded by the first capacitor dielectric (108aand109a) according to step S207inFIG.6. In some embodiments, the formation of the first top electrode110aincludes disposing a conductive material such as tungsten (W) over the first high-k liner109aand within the first recess117aas shown inFIG.15, and then removing portions of the conductive material disposed over the first dielectric layer107ato form the first top electrode110aas shown inFIG.16.

In some embodiments, the conductive material is disposed by deposition, CVD or any other suitable process. In some embodiments, the portions of the conductive material are removed by planarization, chemical mechanical polishing (CMP) or any other suitable process. In some embodiments, portions of the first capacitor dielectric (108aand109a) disposed over the first dielectric layer107aare also removed. In some embodiments, the first capacitor dielectric (108aand109a) and the first top electrode110aextend laterally over the first bottom electrode106aand the semiconductor substrate104.

In some embodiments, steps similar to steps S202to S207are repeated after the formation of the first top electrode110aas shown inFIG.16. In some embodiments, as shown inFIG.17, a second insulating layer105bis disposed over the first top electrode110aand the first dielectric layer107a. In some embodiments, the disposing of the second insulating layer105bis similar to step S202.

In some embodiments, as shown inFIG.18, a second bottom electrode106bis disposed over the second insulating layer105b. In some embodiments, the disposing of the second bottom electrode106bis similar to step S203. In some embodiments, as shown inFIG.19, a second dielectric layer107bis disposed over the second bottom electrode106b. In some embodiments, the disposing of the second dielectric layer107bis similar to step S204.

In some embodiments, as shown inFIGS.20and21, a portion of the second dielectric layer107bis removed to form a second recess117bextending through the second dielectric layer107b. In some embodiments, the removal of the portion of the second dielectric layer107bincludes removing a first portion of the second dielectric layer107bto form an opening117b′ partially through the second dielectric layer107bas shown inFIG.20, and then removing a second portion of the second dielectric layer107bexposed through the opening117b′ to form the second recess117bat least partially exposing the second bottom electrode106bas shown inFIG.21. In some embodiments, the formation of the second recess117bis similar to step S205.

In some embodiments, as shown inFIGS.22and23, a second capacitor dielectric (108band109b) is disposed conformal to the second recess117band over the second bottom electrode106b. In some embodiments, the disposing of the second capacitor dielectric (108band109b) includes disposing a second nitride liner108bover the second dielectric layer107band conformal to the second recess117bas shown inFIG.22, and then disposing a second high-k liner109bover the second nitride liner108bas shown inFIG.23. In some embodiments, the disposing of the second capacitor dielectric (108band109b) is similar to step S206.

In some embodiments, as shown inFIGS.24and25, a second top electrode110bis formed within the second recess117band surrounded by the second capacitor dielectric (108band109b). In some embodiments, the formation of the second top electrode110bis similar to step S207. In some embodiments, the second capacitor dielectric (108band109b) and the second top electrode110bextend laterally over the second bottom electrode106band the semiconductor substrate104. In some embodiments, as shown inFIG.25, the first top electrode110ais offset from the second top electrode110b, and the first recess117ais offset from the second recess117b.

In some embodiments, steps similar to steps S202to S207are repeated after the formation of the second top electrode110bas shown inFIG.25. In some embodiments, as shown inFIG.26, a third insulating layer105cis disposed over the second top electrode110band the second dielectric layer107b. In some embodiments, after the disposing of the third insulating layer105c, steps similar to steps S203to S207are repeated.

In some embodiments, a last insulating layer115is disposed as shown inFIG.27. In some embodiments, the last insulating layer115is formed of a dielectric material, such as silicon oxide or the like. In some embodiments, the last insulating layer115is disposed by deposition or any other suitable process. In some embodiments, after the disposing of the last insulating layer115, an intermediate structure is formed as shown inFIGS.27and28.FIG.27illustrates a cross-sectional view of the intermediate structure along the line A-A ofFIG.1, andFIG.28illustrates a cross-sectional view of the intermediate structure along the line B-B ofFIG.1.

FIG.29is a flow diagram illustrating a method S300of manufacturing an intermediate structure of a memory device100in accordance with some embodiments of the present disclosure, andFIGS.30to47illustrate cross-sectional views of intermediate stages in formation of the intermediate structure of the memory device100as shown inFIG.1along the line B-B in accordance with some embodiments of the present disclosure.

The stages shown inFIGS.30to47are also illustrated schematically in the flow diagram inFIG.29. In following discussion, the fabrication stages shown inFIGS.30to47are discussed in reference to process steps shown inFIG.29. The method S300includes a number of operations, and description and illustration are not deemed as a limitation to a sequence of the operations. The method S300includes a number of steps (S301, S302, S303, S304and S305).

In some embodiments, the method S300is implemented after the method S200or after repetition of the method S200as described above. In some embodiments, the method S300is implemented after the formation of the intermediate structure as shown inFIG.28. Referring toFIG.30, a first photoresist layer118′ is disposed over the second insulating layer105band the last insulating layer115according to step S301inFIG.29. In some embodiments, the first photoresist layer118′ is disposed by spin coating or any other suitable process. Referring toFIG.31, a portion of the first photoresist layer118′ is removed to form a first patterned photoresist layer118according to step S302inFIG.29. In some embodiments, the portion of the first photoresist layer118′ is removed by etching or any other suitable process.

Referring toFIG.32, portions of the second insulating layer105b, the second bottom electrode106band the second dielectric layer107bexposed through the first patterned photoresist layer118are removed to expose at least a portion of the first top electrode110aaccording to step S303inFIG.29. In some embodiments, portions of the third insulating layer105c, the third bottom electrode106c, the third capacitor dielectric (108cand109c) and the third top electrode110care also removed to expose at least the portion of the first top electrode110a. In some embodiments, the portions of the second insulating layer105b, the second bottom electrode106band the second dielectric layer107b, the third insulating layer105c, the third bottom electrode106c, the third capacitor dielectric (108cand109c) and the third top electrode110care removed by etching or any other suitable process.

In some embodiments, a portion of the first patterned photoresist layer118is removed to form a second patterned photoresist layer120as shown inFIG.33, in a step similar to step S302. In some embodiments, a portion of the last insulating layer115exposed through the second patterned photoresist layer120is removed to expose at least a portion of the third top electrode110cas shown inFIG.34, in a step similar to step S303. In some embodiments, the second patterned photoresist layer120is then removed, as shown inFIG.35. In some embodiments, the second patterned photoresist layer120is removed by stripping, etching or any other suitable process.

Referring toFIG.36, a dielectric material119is disposed over the portion of the first top electrode110a, the portion of the third top electrode110cand the last insulating layer115according to step S304inFIG.29. In some embodiments, the dielectric material119is formed of a dielectric material, such as silicon oxide or the like. In some embodiments, the dielectric material119and the last insulating layer115include a same material. In some embodiments, the dielectric material119is disposed by deposition or any other suitable process.

In some embodiments, portions of the dielectric material119are removed to form a first trench121and a second trench122as shown inFIG.37. In some embodiments, the first trench121extends through the dielectric material119and exposes at least a portion of the first top electrode110a, and the second trench122extends through the dielectric material119and exposes at least a portion of the third top electrode110c. In some embodiments, the portions of the dielectric material119are removed by etching or any other suitable process.

Referring toFIGS.38and39, a first conductive plug112aextending through the dielectric material119and contacting the first top electrode110ais formed according to step S305inFIG.29. In some embodiments, a second conductive plug112bextending through the dielectric material119and contacting the third top electrode110cis also formed. In some embodiments, the first conductive plug112aand the second conductive plug112bare formed by disposing a conductive material into the first trench121and the second trench122. In some embodiments, a top electrode plate112dis also formed on the first conductive plug112aand the second conductive plug112b.

In some embodiments, the top electrode plate112dis formed by disposing the conductive material over the dielectric material119as shown inFIG.38, and then removing some portions of the conductive material as shown inFIG.39. In some embodiments, the conductive material includes copper or the like. In some embodiments, the conductive material is disposed by electroplating or any other suitable process. In some embodiments, the top electrode plate112dis electrically connected to the first top electrode110aand the third top electrode110cthrough the first conductive plug112aand the second conductive plug112b, respectively. In some embodiments, a memory device100as shown inFIG.3is formed as shown inFIG.39, which is a cross-sectional view of the memory device100along the line B-B ofFIG.1.

Referring toFIGS.40to47, steps for forming the memory device100as shown inFIG.4are similar to steps S301to S305of the method S300. In some embodiments, after the implementation of the method S200, an intermediate structure as shown inFIG.40is formed.FIG.40illustrates a cross-sectional view of the intermediate structure along the line B-B ofFIG.1. Referring toFIG.41, a first photoresist layer118′ is disposed over the last insulating layer115, in a step similar to step S301. Referring toFIG.42, a first patterned photoresist layer118is formed, in a step similar to step S302.

Referring toFIG.43, portions of the second insulating layer105b, the second bottom electrode106band the second dielectric layer107bexposed through the first patterned photoresist layer118are removed to expose at least a portion of the first top electrode110a, in a step similar to step S303. In some embodiments, steps similar to step S303are repeated to form an intermediate structure as shown inFIG.44. In some embodiments, the first top electrode110a, the third top electrode110cand the fifth top electrode110eare at least partially exposed.

Referring toFIG.45, a dielectric material119is disposed over the last insulating layer115, the first top electrode110a, the third top electrode110cand the fifth top electrode110e, in a step similar to step S304. Referring toFIG.46, portions of the dielectric material119are removed to form a first trench121, a second trench122and a third trench123extending through the dielectric material119. Referring toFIG.47, a first conductive plug112aextending through the dielectric material119and contacting the first top electrode110ais formed, in a step similar to step S305.

In some embodiments, the second conductive plug112bextending through the dielectric material119and contacting the third top electrode110cand the third conductive plug112cextending through the dielectric material119and contacting the fifth top electrode110eare also formed. In some embodiments, a top electrode plate112dcontacting the first conductive plug112a, the second conductive plug112band the third conductive plug112cis formed over the dielectric material119. In some embodiments, an intermediate structure ofFIG.4is formed as shown inFIG.47.

FIG.48is a flow diagram illustrating a method S400of manufacturing an intermediate structure of a memory device100in accordance with some embodiments of the present disclosure, andFIGS.49to56illustrate cross-sectional views of intermediate stages in formation of the intermediate structure of the memory device100as shown inFIG.5, which is a cross-sectional side view of the memory device ofFIG.1along the line C-C in accordance with some embodiments of the present disclosure.

The stages shown inFIGS.49to56are also illustrated schematically in the flow diagram inFIG.48. In following discussion, the fabrication stages shown inFIGS.49to56are discussed in reference to process steps shown inFIG.48. The method S400includes a number of operations, and description and illustration are not deemed as a limitation to a sequence of the operations. The method S400includes a number of steps (S401, S402, S403, S404and S405).

In some embodiments, the method S400is implemented after the method S200or after repetition of the method S200as described above. In some embodiments, the method S400is implemented after the formation of the intermediate structure as shown inFIGS.27and28. Referring toFIG.49, a third photoresist layer124′ is disposed over the second dielectric layer107b, the second insulating layer105band the last insulating layer115according to step S401inFIG.48. In some embodiments, the third photoresist layer124′ is disposed by spin coating or any other suitable process.

Referring toFIG.50, a mask125is disposed over the third photoresist layer124′ according to step S402inFIG.48. In some embodiments, an exposure process and a develop process are applied to the third photoresist layer124′ with the use of the mask125.

In some embodiments, the mask125includes a first region125a, a second region125band a third region125c. In some embodiments, the first region125ahas a first transmission rate equal to an amount of a predetermined electromagnetic radiation R (as shown inFIG.51) allowed to pass through the first region125a. In some embodiments, the second region125bhas a second transmission rate equal to an amount of the predetermined electromagnetic radiation R (as shown inFIG.51) allowed to pass through the second region125b. In some embodiments, the third region125chas a third transmission rate equal to an amount of the predetermined electromagnetic radiation R (as shown inFIG.51) allowed to pass through the third region125c.

In some embodiments, the first transmission rate is substantially different from the second transmission rate. In some embodiments, the first transmission rate is substantially different from the third transmission rate. In some embodiments, the first transmission rate is substantially greater than the second transmission rate. In some embodiments, the first transmission rate is substantially greater than the third transmission rate. In some embodiments, the second transmission rate is substantially greater than the third transmission rate.

In some embodiments, the first transmission rate is about 100%. That is, the predetermined electromagnetic radiation R can completely pass through the mask125via the first region125a. In some embodiments, the second transmission rate and the third transmission rate are less than 100%. That is, the predetermined electromagnetic radiation R can only partially pass through the mask125via the second region125band the third region125c. In some embodiments, the first region125ais a through hole, while the second region125band the third region125care partial through holes.

Referring toFIG.51, the predetermined electromagnetic radiation R is provided over the mask125according to step S403. In some embodiments, the predetermined electromagnetic radiation R is ultraviolet (UV) light, light or the like. Referring toFIG.51, the mask125is irradiated with the predetermined electromagnetic radiation R according to step S404. In some embodiments, different portions of the third photoresist layer124′ are exposed to different amount of the predetermined electromagnetic radiation R. In some embodiments, a fourth region124aof the third photoresist layer124′ vertically aligned with the first region125aof the mask125receives the predetermined electromagnetic radiation R completely passing through the first region125a. In some embodiments, the fourth region124aof the third photoresist layer124′ is exposed to 100% or nearly 100% of the predetermined electromagnetic radiation R.

In some embodiments, a fifth region124bof the third photoresist layer124′ vertically aligned with the second region125bof the mask125receives the predetermined electromagnetic radiation R partially passing through the second region125b. In some embodiments, the fifth region124bof the third photoresist layer124′ is exposed to less than 100% of the predetermined electromagnetic radiation R.

In some embodiments, a sixth region124cof the third photoresist layer124′ vertically aligned with the third region125cof the mask125receives the predetermined electromagnetic radiation R partially passing through the third region125c. In some embodiments, the sixth region124cof the third photoresist layer124′ is exposed to less than 100% of the predetermined electromagnetic radiation R.

In some embodiments, a remaining portion of the third photoresist layer124′ does not receive any predetermined electromagnetic radiation R. In some embodiments, the remaining portion of the third photoresist layer124′ is exposed to 0%, or substantially none, of the predetermined electromagnetic radiation R.

Referring toFIG.51, a third patterned photoresist layer124is formed from the third photoresist layer124′ according to step S405. In some embodiments, after the irradiation of the mask125with the predetermined electromagnetic radiation R, the portions of the third photoresist layer124′ exposed to the predetermined electromagnetic radiation R are removed to form the third patterned photoresist layer124. In some embodiments, the portions of the third photoresist layer124′ are removed by etching or any other suitable process. In some embodiments, after the removal, the third patterned photoresist layer124having a fourth recess124d, a fifth recess124eand a sixth recess124fis formed as shown inFIG.51. In some embodiments, the mask125is removed after the formation of the third patterned photoresist layer124as shown inFIG.52.

Referring toFIG.53, portions of the first dielectric layer107a, the second insulating layer105b, the second bottom electrode106b, the second dielectric layer107b, the third insulating layer105c, the third bottom electrode106c, the third dielectric layer107cand the last insulating layer115under the fourth recess124dare removed to form a fourth trench126exposing a portion of the first bottom electrode106a.

In some embodiments, portions of the second dielectric layer107b, the third insulating layer105c, the third bottom electrode106c, the third dielectric layer107cand the last insulating layer115under the fifth recess124eare removed to form a fifth trench127exposing a portion of the second bottom electrode106b. In some embodiments, portions of the third dielectric layer107cand the last insulating layer115under the sixth recess124fare removed to form a sixth trench128exposing a portion of the third bottom electrode106c. Referring toFIG.54, after the formation of the fourth trench126, the fifth trench127and the sixth trench128, the third patterned photoresist layer124is removed by stripping, etching or any other suitable process.

Referring toFIGS.55and56, a conductive material is disposed within the fourth trench126, the fifth trench127and the sixth trench128to form a fourth conductive plug113a, a fifth conductive plug113band a sixth conductive plug113c, respectively. In some embodiments, the conductive material is disposed by electroplating or any other suitable process. In some embodiments, the conductive material includes copper or the like.

In some embodiments, the conductive material is also disposed over the last insulating layer115as shown inFIG.55, and then a portion of the conductive material disposed over the last insulating layer115is removed to form a bottom electrode plate113das shown inFIG.56. In some embodiments, the bottom electrode plate113dis formed on the fourth conductive plug113a, the fifth conductive plug113band the sixth conductive plug113c. In some embodiments, the bottom electrode plate113dis electrically connected to the first bottom electrode106a, the second bottom electrode106band the third bottom electrode106cthrough the fourth conductive plug113a, the fifth conductive plug113band the sixth conductive plug113c. In some embodiments, a memory device100as shown inFIG.5is formed as shown inFIG.56, which illustrates a cross-sectional view of the memory device100along the line C-C ofFIG.1.

In an aspect of the present disclosure, a memory device is provided. The memory device includes a semiconductor substrate; a first insulating layer disposed over the semiconductor substrate; a first bottom electrode disposed over the first insulating layer; a first dielectric layer disposed over the first bottom electrode; a first recess extending through the first dielectric layer; a first capacitor dielectric conformal to the first recess and in contact with the first bottom electrode; and a first top electrode disposed within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.

In another aspect of the present disclosure, a memory device is provided. The memory device includes a semiconductor substrate; a first insulating layer disposed over the semiconductor substrate; a first bottom electrode disposed over the first insulating layer; a first dielectric layer disposed over the first bottom electrode; a first recess extending through the first dielectric layer; a second recess extending through the first dielectric layer; a first capacitor dielectric conformal to the first recess and in contact with the first bottom electrode; a second capacitor dielectric conformal to the second recess and in contact with the first bottom electrode; a first top electrode disposed within the first recess and surrounded by the first capacitor dielectric; and a second top electrode disposed within the second recess and surrounded by the second capacitor dielectric, wherein the first capacitor dielectric, the first top electrode, the second capacitor dielectric and the second top electrode extend laterally over the first bottom electrode and the semiconductor substrate.

In another aspect of the present disclosure, a method of manufacturing a memory device is provided. The method includes steps of providing a semiconductor substrate; disposing a first insulating layer over the semiconductor substrate; disposing a first bottom electrode over the first insulating layer; disposing a first dielectric layer over the first bottom electrode; removing a portion of the first dielectric layer to form a first recess extending through the first dielectric layer; disposing a first capacitor dielectric conformal to the first recess and over the first bottom electrode; and forming a first top electrode within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.

In conclusion, because each capacitor of the present disclosure extends laterally over a semiconductor substrate instead of standing upright above the semiconductor substrate, collapse of the capacitors can be prevented. Further, top electrodes of the capacitors arranged in different levels and vertically aligned with each other are configured in different lengths, and bottom electrodes of the capacitors extend over the semiconductor substrate and are configured in planar shapes. As such, all of the capacitors can be electrically connected in parallel instead of in series. Performance of a memory device and a process of manufacturing the memory device are thereby improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.