Patent ID: 12229447

DETAILED DESCRIPTION

In generally, according to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller.

Hereinafter, embodiments will be described with reference to the drawings. Some embodiments to be described below are mere exemplification of a device and method for embodying a technical idea, and the shape, configuration, arrangement, etc. of the components do not specify the technical idea. Each function block is implemented in the form of hardware, software, or a combination thereof. The function blocks are not necessarily separated as in the following examples. For example, some functions may be executed by a function block different from the function block to be described as an example. In addition, the function block to be described as an example may be divided into smaller function subblocks. In the following description, elements having the same function and configuration will be assigned the same reference symbol, and a repetitive description will be given only where necessary.

<1> First Embodiment

<1-1> Configuration

<1-1-1> Overview of Identification System

In the present embodiment, an identification system (device) using a neural network will be described. The identification system learns a parameter for identifying the contents of identification target data (input data) in a learning step, and identifies the identification target data based on the learning result in an identification step. The identification target data is data to be identified, and is image data, audio data, text data, or the like. Described below as an example is the case where the identification target data is image data and a neural network that identify image data is used.

As shown inFIG.1, in the identification system according to the present embodiment, multiple data items (a data set) for training are input to an identification device, which is part of the identification device, in the learning step. The identification device constructs a neural network (trained model) based on the data set.

Specifically, the identification device constructs a neural network for classifying identification target data. The identification device uses input data and an evaluation of the label when constructing a neural network. The evaluation of the label includes a “positive evaluation” indicating that the contents of data match the label, and a “negative evaluation” indicating that the contents of data do not match the label. The positive evaluation or negative evaluation is associated with a score (truth score, or identification score), such as “0” data or “1” data, and the score is also referred to as Ground Truth. The “score” is a numerical value, and is the signal itself, which is exchanged in the neural network. The identification device performs an arithmetic operation on an input data set, and adjusts a parameter used in the arithmetic operation to bring the identification score, which is the operation result (also referred to as an inference), closer to the truth score prepared in advance. The “identification score” indicates a degree of matching between the input data set and the label associated with the input data set. The “truth score” indicates an evaluation of the label associated with the input data set.

Once a neural network is constructed, the identification system identifies what the given data (the input data set) is by using the neural network in the identification step (output of an identification result).

<1-1-2> Configuration of Identification System

Next, the identification system according to the present embodiment will be described with reference toFIG.2.FIG.2is a block diagram showing a hardware configuration of the identification system.

As shown inFIG.2, the identification system1includes an input/output interface (I/F)2, a controller (central processing unit (CPU))3, a memory4, and an identification device5. The input/output interface2, the controller3, the memory4, and the identification device5are each connected to a controller bus.

The input/output interface2is, for example, an input/output control circuit (device) which receives a data set, and outputs an identification result. The input/output interface2may be a UFS interface based on the universal flash storage (UFS) standard, an SAS interface based on the serial attached SCSI (SAS) standard, or an interface based on another standard, or may be a communication cable itself.

The controller3controls the entire identification system1.

The memory4includes, for example, a random access memory (RAM) and a read only memory (ROM).

In the learning step, the identification device5learns features from, for example, a data set, and constructs a neural network. The constructed neural network is expressed as a weight coefficient (may be merely referred to as a weight) used in each arithmetic operation unit in the identification device5. Namely, the identification device5constructs a neural network that, when input data corresponding to, for example, an image including an image “X” is input, makes an output indicating that the input data is image “X”. The identification device5improves the accuracy of the neural network by receiving many input data items.

In the identification step, the identification device5obtains a weight coefficient in the neural network. When the neural network is updated, the identification device5obtains a new weight coefficient of the neural network to improve the identification accuracy. The identification device5which has obtained the weight coefficient receives input data to be identified. Then, the identification device5inputs input data in the neural network using the weight coefficient, and identifies the input data. Each function of the identification system1is realized by causing the controller3to read predetermined software into hardware such as the memory4, and reading data from and writing data in the memory4under control of the controller3.

<1-1-3> Identification Device

<1-1-3-1> Concept of Identification Device

The neural network is modeled on the human brain, and consists of a collection of models modeled on nerve cells called neurons.

The neural network includes an input layer, an intermediate layer, and an output layer.

Information output from a neuron in the input layer is input to a neuron in the intermediate layer, and information output from a neuron in the intermediate layer is input to a neuron in the output layer.

The input to each neuron is a value obtained by multiplying input data by a weight and adding a bias to the resultant value. The final output value is determined by subjecting the total value to a specific function. The function to determine the output value is an activation function. The activation function includes, for example, the sigmoid function, softmax function, identity function, and rectified linear unit (ReLU).

Next, a concept of the identification device5of the identification system according to the present embodiment will be described with reference toFIG.3.FIG.3is a block diagram showing a concept of the identification device5of the identification system according to the present embodiment. Here, a concept of the identification device5in the learning step will be described.

As shown inFIG.3, the identification device5includes the input layer51, the hidden layer52, and the output layer53.

In the input layer51, input nodes are arranged in parallel. The input nodes each obtain input data X and output (distribute) it to a node (nodes) included in the hidden layer52. The node of the present embodiment is a model modeled on a brain neuron. The node may be referred to as a neuron.

FIG.3shows the case where the input layer51includes four parallel nodes for simplification. InFIG.3, data items X1to X4are stored in the four nodes, respectively.

In the hidden layer52, processing nodes are arranged in parallel. The processing nodes each perform an arithmetic operation (product-sum operation) on processing data using a weight coefficient, and output an operation result (operation data) Y to a node or nodes of the subsequent layer.

FIG.3shows the case where the hidden layer52includes three parallel nodes for simplification. The results of the product-sum operations are stored in the nodes of the hidden layer as data items Y1to Y4. These data items Y1to Y4are input data for the next product-sum operations. A plurality of edges from the input layer51to the hidden layer52are associated with weights W11to W34.

Hereinafter, the relationship between data X, data Y, and weight W will be specifically described. The node in which data item Y1is stored stores the sum (ΣW1i×Wi) of a product of weight W11and data item X1, a product of weight W12and data item X2, a product of weight W13and data item X3, and a product of weight W14and data item X4. Similarly, the node in which data item Y2is stored stores the sum (ΣW2i×Wi) of a product of weight W21and data item X1, a product of weight W22and data item X2, a product of weight W23and data item X3, and a product of weight W24and data item X4. Also, the node in which data item Y3is stored stores the sum (ΣW3i×Wi) of a product of weight W31and data item X1, a product of weight W32and data item X2, a product of weight W33and data item X3, and a product of weight W34and data item X4. Accordingly, the relationship is expressed by Yk=ΣWki×Xi.

In the output layer53, output nodes, the number of which is the same as the number of labels, are arranged in parallel. The labels are each associated with identification target data. The output layer53performs an arithmetic operation using an activation function for each output node based on the data received from the hidden layer52, and outputs an identification score. Namely, the identification device5outputs an identification score for each label. For example, when the identification device5identifies three images of “car”, “tree”, and “human”, the output layer53has three output nodes arranged in correspondence with the three labels, “car”, “tree”, and “human”. The output nodes output an identification score corresponding to the label of “car”, an identification score corresponding to the label of “tree”, and an identification score corresponding to the label of “human”.FIG.3shows the case where the output layer53includes two parallel nodes for simplification. As a result of the arithmetic operation using the activation function, data items Z1and Z2are obtained from the nodes of the output layer53.

The above-described number of nodes included in each of the input layer51, hidden layer52and output layer53may be changed as appropriate. In particular, the hidden layer52includes only a single-stage processing node group in the figure, but may include a two or more-stage processing nodes. Providing the hidden layer52with a multi-stage processing node group will be referred to as “deep learning”.

<1-1-3-2> Specific Configuration of Identification Device

<1-1-3-2-1> Memory System

Here, as a specific hardware configuration for realizing the identification device5, a memory system400will be described as an example.

As shown inFIG.4, the memory system400includes a NAND flash memory100and a memory controller200. The memory controller200and NAND flash memory100may form one semiconductor device in combination, for example. The semiconductor device is, for example, a memory card such as an SD™ card, or a solid state drive (SSD).

The NAND flash memory100includes a plurality of memory cell transistors, and nonvolatilely stores data. The NAND flash memory100is connected to the memory controller200via NAND buses, and operates based on a host command (instruction) from the memory controller200. Specifically, the NAND flash memory100transmits and receives, for example, signals DQ0to DQ7(eight bits; hereinafter, where DQ0to DQ7are not distinguished from each other, the signals will be merely referred to as signal DQ or signal DQ[7:0]) to and from the memory controller200. Signals DQ0to DQ7include, for example, data, an address, and a command. The NAND flash memory100receives from the memory controller200, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn. The NAND flash memory100transmits a ready/busy signal R/Bn to the memory controller200.

The chip enable signal CEn is a signal for enabling the NAND flash memory100, and is asserted, for example, at the low (“L”) level. The command latch enable signal CLE is a signal indicating that signal DQ is a command, and is asserted, for example, at the high (“H”) level. The address latch enable signal ALE is a signal indicating that signal DQ is an address, and is asserted, for example, at the “H” level. The write enable signal WEn is a signal for taking a received signal into the NAND flash memory100, and is asserted, for example, at the “L” level whenever a command, an address, data, or the like is received from the memory controller200. Accordingly, whenever the write enable signal WEn is toggled, signal DQ is taken into the NAND flash memory100. The read enable signal REn is a signal for the memory controller200to read data from the NAND flash memory100. The read enable signal REn is asserted, for example, at the “L” level. The ready/busy signal R/Bn is a signal indicating whether the NAND flash memory100is in a ready state or in a busy state (in a state where a command is received from the memory controller200or in a state where a command isn't received therefrom), and is brought to the “L” level when the NAND flash memory100is in the busy state, for example.

The memory controller200instructions the NAND flash memory100to read, write, or erase data in response to, for example, a host command from the controller3. The memory controller200also manages the memory space of the NAND flash memory100.

The memory controller200includes a host interface circuit (host I/F)210, a memory (random access memory (RAM))220, a processor (central processing unit (CPU))230, a buffer memory240, a NAND interface circuit (NAND I/F)250, and an error correction circuit (ECC)260.

The host interface circuit210is connected to the outside (such as the controller3) via a controller bus, and controls communication with the outside. The host interface circuit210transfers a host command and data received from the outside to the processor230and the buffer memory240. The host interface circuit210also transfers data in the buffer memory240to the outside in response to an instruction of the processor230.

The NAND interface circuit250is connected to the NAND flash memory100via the NAND buses, and controls communication with the NAND flash memory100. The NAND interface circuit250transfers an instruction received from the processor230to the NAND flash memory100. At the time of writing data, the NAND interface circuit250transfers write data in the buffer memory240to the NAND flash memory100. At the time of reading data, the NAND interface circuit250transfers data read from the NAND flash memory100to the buffer memory240.

The processor230controls the operation of the entire memory controller200. The processor230also issues various commands in response to external host commands, and transmits them to the NAND flash memory100. For example, when externally receiving a write-related host command, the processor230transmits, in response thereto, a write-related NAND command to the NAND flash memory100. Similar processing is performed at the time of reading or erasing data. The processor230also executes various types of processing, such as wear leveling, for managing the NAND flash memory100. The processor230also executes various arithmetic operations. For example, the processor230executes data encryption processing, randomization processing, and the like.

The error correction circuit260executes error correction processing on data.

The memory220is a semiconductor memory such as a dynamic random access memory (DRAM) or a static RAM (SRAM), and is used as a work area of the processor230. The memory220retains firmware for managing the NAND flash memory100, various management tables, and the like.

Here, as a specific hardware configuration of the identification device5, the memory system400is described; however, the hardware configuration is not limited to the memory system400. As another example, it is possible to adopt the memory controller200as a hardware configuration of the controller3, and adopt the NAND flash memory100as a hardware configuration of the identification device5.

<1-1-3-2-2> NAND Flash Memory100

Next, a configuration of the NAND flash memory100will be described with reference toFIG.5. InFIG.5, some of the couplings between blocks are indicated by arrows; however, the couplings between blocks are not limited to those shown inFIG.5.

As shown inFIG.5, the NAND flash memory100includes an input/output circuit15, a logic control circuit16, a status register18, an address register19, a command register20, a sequencer17, a ready/busy circuit21, a voltage generator22, a memory cell array10, a row decoder11, a sense amplifier module12, a data register/bit counter13, and a column decoder14.

The input/output circuit15controls input/output of signal DQ to or from the memory controller200. Specifically, the input/output circuit15includes an input circuit and an output circuit. The input circuit transmits data DAT (write data WD) received from the memory controller200to the data register/bit counter13, transmits an address ADD to the address register19, and transmits a command CMD to the command register20. The output circuit transmits status information STS received from the status register18, data DAT (read data RD) received from the data register/bit counter13, and an address ADD received from the address register19to the memory controller200.

The logic control circuit16receives from the memory controller200, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn. The logic control circuit16controls the input/output circuit15and the sequencer17in accordance with the received signal.

The status register18temporarily retains status information STS on, for example, a data write, read, or erase operation, and notifies the memory controller200whether or not the operation has been normally completed.

The address register19temporarily retains the address ADD received from the controller200via the input/output circuit15. Then, the address register19transfers a row address RA to the row decoder11, and a column address CA to the column decoder14.

The command register20temporarily retains the command CMD received from the memory controller200via the input/output circuit15, and transfers it to the sequencer17.

The sequencer17controls the operation of the entire NAND flash memory100. Specifically, in accordance with the command CMD retained by the command register20, the sequencer17controls, for example, the status register18, the ready/busy circuit21, the voltage generator22, the row decoder11, the sense amplifier module12, the data register/bit counter13, the column decoder14, etc. to execute a write operation, read operation, erase operation, etc. The sequencer17includes a register (not shown).

The ready/busy circuit21transmits a ready/busy signal R/Bn to the memory controller200in accordance with the operation state of the sequencer17.

The voltage generator22generates voltages necessary for a write operation, read operation, and erase operation under control of the sequencer17, and supplies the generated voltages to, for example, the memory cell array10, the row decoder11, the sense amplifier module12, etc. The row decoder11and sense amplifier module12apply the voltage supplied by the voltage generator22to the memory cell transistors in the memory cell array10.

The memory cell array10includes blocks BLK0to BLKn (n is an integer not less than 0). The block BLK is a set of a plurality of nonvolatile memory cells, each of which is associated with a bit line and a word line, and corresponds to a data erase unit, for example. The NAND flash memory100may cause each memory cell to store two or more-bit data by adopting, for example, the multi-level cell (MLC) method.

The row decoder11decodes the row address RA. The row decoder11selects one of the blocks BLK and further selects one of the memory cell units based on the decoding result. The row decoder11applies a necessary voltage to the block BLK.

In a read operation, the sense amplifier module12senses data read from the memory cell array10. Then, the sense amplifier module12transmits read data RD to the data register/bit counter13. In a write operation, the sense amplifier module12transmits write data WD to the memory cell array10.

The data register/bit counter13includes a plurality of latch circuits. The latch circuits each retain write data WD and read data RD. For example, in a write operation, the data register/bit counter13temporarily retains write data WD received from the input/output circuit15, and transmits it to the sense amplifier module12. For example, in a read operation, the data register/bit counter13temporarily retains read data RD received from the sense amplifier module12, and transmits it to the input/output circuit15.

In, for example, a write operation, read operation, or erase operation, the column decoder14decodes the column address CA, and selects a latch circuit in the data register/bit counter13in accordance with the decoding result.

<1-1-3-2-3> Memory Cell Array

FIG.6is a circuit diagram showing a configuration example of the memory cell array10included in the NAND flash memory100according to the first embodiment, and shows a detailed circuit configuration of one block BLK in the memory cell array10. As shown inFIG.6, the block BLK includes, for example, four string units SU0to SU3.

Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0to BLm (m is an integer not less than 0), respectively. Each NAND string NS includes, for example, memory cell transistors MT0to MT7and select transistors ST1and ST2.

The memory cell transistors MT each include a control gate and a charge storage layer, and nonvolatilely stores data. The memory cell transistors MT0to MT7included in each NAND string NS are connected in series between the source of select transistor ST1and the drain of select transistor ST2. The control gates of memory cell transistors MT0of the NAND strings NS included in the same block BLK are connected in common to word line WL0. Similarly, the control gates of memory cell transistors MT1to MT7of the NAND strings NS included in the same block BLK are connected in common to respective word lines WL1to WL7. Hereinafter, a plurality of memory cell transistors MT connected to a common word line WL in each string unit SU are called a cell unit CU. The set of one-bit data stored in the cell unit is called a “page”. Therefore, when two-bit data is stored in one memory cell transistor MT, the cell unit stores data of two pages.

The select transistors ST1and ST2are used to select a string unit SU in various operations. The drains of select transistors ST1included in the NAND strings NS corresponding to the same column address are connected in common to a corresponding bit line BL. The gates of select transistors ST1included in string unit SU0are connected in common to select gate line SGD0. Similarly, the gates of select transistors ST1included in string units SU1to SU3are connected in common to respective select gate lines SGD1to SGD3. The sources of select transistors ST2in the same block BLK are connected in common to one source line SL, and the gates of select transistors ST2in the same block BLK are connected in common to one select gate line SGS.

In the above-described circuit configuration of the memory cell array10, the word lines WL0to WL7are provided for each block BLK. The bit lines BL0to BLm are shared by a plurality of blocks BLK. The source line SL is shared by a plurality of blocks BLK. The above-described number of string units SU included in each block BLK and number of each of the memory cell transistors MT and select transistors ST1and ST2included in each NAND string NS are mere examples, and may be any number. The number of each of the word lines WL and the select gate lines SGD and SGS is changed based on the number of each of the memory cell transistors MT and the select transistors ST1and ST2.

The threshold voltage distribution of the threshold voltages of a plurality of memory cell transistors MT of the memory cell array10is, for example, as shown inFIG.7.FIG.7shows a threshold voltage distribution and read voltages of memory cell transistors MT of the case where each memory cell transistor MT stores two-bit data, in which the vertical axis corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltages Vth of the memory cell transistors MT. As shown inFIG.7, the memory cell transistors MT form a plurality of threshold voltage distribution lobes depending on the bit numbers of data stored therein. Hereinafter, the multi-level cell (MLC) method, in which one memory cell transistor MT stores two-bit data, will be described as an example of the write method.

As shown inFIG.7, the memory cell transistors MT form four threshold voltage distribution lobes in the case of the MLC method. The four threshold voltage distribution lobes will be called an “Er” state, “A” state, “B” state, and “C” state in the ascending instruction of the threshold voltage. In the MLC method, for example, “11 (lower, upper)” data, “10” data, “00” data, and “01” data are allocated to the “Er” state, “A” state, “B” state, and “C” state, respectively.

In the above-described threshold voltage distribution, a read voltage is set between adjacent threshold voltage distribution lobes. For example, a read voltage AR is set between the maximum threshold voltage of the “Er” state and the minimum threshold voltage of the “A” state, and is used for an operation to determine whether the threshold voltage of a memory cell transistor MT is included in the “Er”—state threshold voltage distribution lobe or in the “A”—state threshold distribution lobe. When read voltage AR is applied to the memory cell transistor MT, the memory cell transistors in the “Er” state are turned on, and the memory cell transistors in the “A” state, “B” state, and “C” state are turned off. The other read voltages are set in a similar manner. Read voltage BR is set between the “A”—state threshold voltage distribution lobe and the “B”—state threshold voltage distribution lobe, and read voltage CR is set between the “B”—state threshold voltage distribution lobe and the “C”—state threshold voltage distribution lobe. A read pass voltage VREAD is set at a voltage higher than the maximum threshold voltage of the highest threshold voltage distribution lobe. When the read pass voltage VREAD is applied to the gate of a memory cell transistor MT, the memory cell transistor MT is turned on regardless of data stored therein.

The above-described bit number of data stored in one memory cell transistor MT and data allocation to the threshold voltage distribution lobes of memory cell transistors MT are mere examples. Various data allocations may be applied to the threshold voltage distribution lobes. The read voltages and read pass voltage may be set at the same voltage values or different values between the methods.

The memory cell array10may have a configuration other than the above-described one. The memory cell array may have the configuration described in U.S. patent application Ser. No. 12/407,403, entitled “THREE-DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY”, filed on Mar. 19, 2009, the configuration described in U.S. patent application Ser. No. 12/406,524, entitled “THREE-DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY”, filed on Mar. 18, 2009, U.S. patent application Ser. No. 12/679,991, entitled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF”, filed on Mar. 25, 2010, or U.S. patent application Ser. No. 12/532,030, entitled “SEMICONDUCTOR MEMORY and MANUFACTURING METHOD THEREOF”, filed on Mar. 23, 2009. The entire contents of these patent applications are incorporated herein by reference.

<1-1-3-2-4> Sense Amplifier Module12and Data Register/Bit Counter13

Next, a configuration of each of the sense amplifier module12and the data register/bit counter13will be described with reference toFIG.8.

As shown inFIG.8, the sense amplifier module12includes sense amplifiers SA(0) to SA(m) provided in correspondence with the respective bit lines BL0to BLm.

In a read operation, the sense amplifier SA senses data read out to the corresponding bit line BL, and determines whether the read data is “0” or “1”. In a write operation, a voltage is applied to the bit line BL based on write data WD.

The data register/bit counter13includes a data register13A and a bit counter13B.

The data register13A includes a latch circuit set130for each sense amplifier SA.

The latch circuit set130includes a plurality of latch circuits DL(0) to (X) (X is a given natural number), and latch circuit XDL, and an arithmetic operation circuit OP. The sense amplifier SA, latch circuits DL(0) to (X), and latch circuit XDL are connected to one another in such a manner that data are transmitted and received therebetween.

Latch circuits DL, for example, temporarily retain data. Latch circuit XDL temporarily retains read data RD received from the sense amplifier SA and write data WD received from the input/output circuit15. Specifically, write data WD received by the input/output circuit15is transferred to one of latch circuits DL and sense amplifier SA via latch circuit XDL. Read data RD received from the sense amplifier SA is transferred to the input/output circuit15via latch circuit XDL.

The arithmetic operation circuit OP performs an arithmetic operation (such as a product operation) based on data stored in latch circuits DL(0) to (X) and latch circuit XDL.

The bit counter13B receives a product operation result output from the latch circuit set130, and performs a sum operation.

<1-1-3-2-5> Sense Amplifier

A detailed circuit configuration of each of the above-described sense amplifiers SA is, for example, as shown inFIG.9.FIG.9shows an example of the detailed circuit configuration of one sense amplifier SA in the sense amplifier module12.

In, for example, a read operation, the sense amplifier SA senses data read out to the corresponding bit line BL, and determines whether the read data is “0” or “1”. As shown inFIG.9, the sense amplifier SA includes a PMOS transistor30, NMOS transistors31to37, and a capacitor38.

One end of transistor30is connected to a power line, and the gate of transistor30is coupled to node INV. One end of transistor31is connected to the other end of transistor30, the other end of transistor31is connected to node COM, and control signal BLX is input to the gate of transistor31. One end of transistor32is connected to node COM, the other end of transistor32is connected to the corresponding bit line BL, and control signal BLC is input to the gate of transistor32. One end of transistor33is connected to node COM, the other end of transistor33is connected to node SRC, and the gate of transistor33is connected to node INV. One end of transistor34is connected to the other end of transistor30, the other end of transistor34is connected to node SEN, and control signal HLL is input to the gate of transistor34. One end of transistor35is connected to node SEN, the other end of transistor35is connected to node COM, and control signal XXL is input to the gate of transistor35. Clock CLK is input to one end of transistor36, and the gate of transistor36is connected to node SEN. One end of transistor37is connected to the other end of transistor36, the other end of transistor37is connected to a bus LBUS, and control signal STB is input to the gate of transistor37. One end of the capacitor38is connected to node SEN, and clock CLK is input to the other end of the capacitor38.

FIG.9also shows an example of a latch circuit DL.

As shown inFIG.9, the latch circuit DL includes inverters40and41and NMOS transistors42and43.

Inverter40has an input terminal connected to node LAT, and an output terminal connected to node INV. Inverter41has an input terminal connected to node INV, and an output terminal connected to node LAT. One end of transistor42is connected to node INV, the other end of transistor42is connected to the bus LBUS, and control signal STI is input to the gate of transistor42. One end of transistor43is connected to node LAT, the other end of transistor43is connected to the bus LBUS, and control signal STL is input to the gate of transistor43. The circuit configurations of the other latch circuits DL are the same, and descriptions thereof are omitted.

The configuration of the data register/bit counter13in the embodiment is not limited to this. For example, the number of latch circuits DL included in the data register/bit counter13may be any number. In that case, the number of latch circuits is designed based on, for example, the bit number of data retained by one memory cell transistor MT. Described above as an example is the case where the sense amplifiers SA are in one-to-one correspondence with the bit lines BL; however, the configuration is not limited to this. For example, a plurality of bit lines BL may be connected to one sense amplifier SA via a selector.

<1-2> Operation

<1-2-1> Operation Flow

An operation flow of the memory system400in the identification step will be described with reference toFIG.10. Described here is the case where identification target data is input to the memory system400and the NAND flash memory100identifies the identification target data with a neural network stored in the memory cell array10.

When externally receiving identification target data, the memory controller200issues a product-sum operation command set including the received identification target data to the input/output circuit15of the NAND flash memory100. The product-sum operation command set is a command set for causing the NAND flash memory100to function as the above-described hidden layer52. A specific example of the product-sum operation command set will be described later.

Upon receipt of the product-sum operation command set, the input/output circuit15supplies a command in the product-sum operation command set to the sequencer17. The sequencer17receives the command, thereby performing a product-sum operation in the NAND flash memory100.

Upon receipt of the product-sum operation command set, the input/output circuit15supplies identification target data (input data) in the product-sum operation command set to the data register13A.

The data register13A stores the received input data in latch circuits DL.

The sequencer17causes the sense amplifiers SA to read weight coefficients (hereinafter referred to as weight data) from the memory cell array10based on the product-sum operation command set.

The sense amplifiers SA supply the weight data read from the memory cell array10to the data register13A. The weight data corresponds to the weight coefficients of the neural network, and is used when performing a product-sum operation on processing data.

The data register13A stores the received weight data in latch circuits DL. The latch circuits DL in which the weight data is stored differ from the latch circuits DL storing the input data.

In accordance with an instruction of the sequencer17, the data register13A performs product operations of stored input data and weight data. The data register13A stores the results of the product operations in latch circuits DL.

The data register13A supplies the results of the product operations to the bit counter13B.

In accordance with an instruction of the sequencer17, the bit counter13B performs a sum operation based on the results of the product operations. This sum operation is performed by a digital operation or analog operation. In this way, the above-mentioned product-sum operation is performed by the data register13A performing product operations of input data and weight data and the bit counter13B performing a sum operation of the product operation results.

The bit counter13B supplies the result of the product-sum operation to the input/output circuit15.

Then, the input/output circuit15supplies the result of the product-sum operation to the memory controller200.

The case where the product-sum operation is performed only once is described here for simplification; however, the embodiment is not limited to this. For example, when multi-stage processing nodes are provided in the hidden layer52, the NAND flash memory100may repeat steps S1005to S1010in accordance with the number of stages.

<1-2-2> Command Set and Waveform Chart

The command set and waveform chart in the operation of the memory system400in the identification step will be described with reference toFIG.11.

As shown inFIG.11, when the NAND flash memory100is in the “ready state (R/Bn signal is at the “H” level)”, the memory controller200issues a product-sum operation command set to the input/output circuit15(S1001). The product-sum operation command set includes a first command (XAH) and second command (XBH) for causing the NAND flash memory100to execute a product-sum operation, and an address (ADD) for designating a memory cell storing weight data, and input data (DATA) used for the product-sum operation.

Upon receipt of the first command (XAH), address (ADD), input data (DATA), and second command (XBH) in instruction, the NAND flash memory100starts a product-sum operation, and transitions from the “ready state (R/Bn signal is at the “H” level)” to the “busy state (R/Bn signal is at the “L” level)”.

Described below are selected word line WL, control signals INV, BLC, BLX, HLL, XXL, and STB, selected bit line BL, and source line SL in step S1005.

At time T1, the sequencer17brings the voltage of control signal INV to the “L” level, raises the voltage of control signal BLC from Vss to Vblc, and raises the voltage of control signal BLX from Vss to Vblc. Accordingly, transistors30,31, and32of the relevant sense amplifier SA are turned on, and the voltage of the bit line BL is raised from Vss to VBL (seeFIG.9). The sequencer17also raises the voltage of the source line SL from Vss to VSL.

At time T2, the sequencer17raises the voltage of the selected word line WL from Vss to AR. Accordingly, when the selected memory cell connected to the selected word line WL is turned on, the voltage of the bit line BL is lowered, whereas when the selected memory cell is not turned on, the voltage of the bit line BL is maintained. The sequencer17also raises the voltage of control signal HLL from the “L” level to the “H” level. Accordingly, transistor34is turned on, and node SEN of the sense amplifier SA is charged (seeFIG.9).

At time T3, the sequencer17lowers the voltage of control signal HLL from the “H” level to the “L” level, and raises the voltage of control signal XXL from the “L” level to the “H” level. Accordingly, transistor35is turned on, and the bit line BL is electrically connected to node SEN via transistors35and32. Therefore, the voltage of node SEN becomes a voltage based on the voltage of the bit line BL (seeFIG.9).

At time T4, the sequencer17raises the voltage of control signal STB from the “L” level to the “H” level while maintaining the voltage of control signal XXL at the “H” level. Accordingly, transistor37is turned on, and information based on the voltage of the gate electrode of transistor36is transferred to the bus LBUS (seeFIG.9). The voltage of the bus LBUS is stored in a latch circuit DL as a result relating to voltage AR.

Specifically, when the selected memory cell is turned on, the voltage of the bit line BL is low, and the voltage of node SEN is consequently low. Therefore, transistor36is turned off, and the voltage of the bus LBUS is maintained. In contrast, when the selected memory cell is turned off, the voltage of the bit line BL is maintained, and the voltage of node SEN is consequently maintained. Therefore, transistor36is turned on, and the bus LBUS is connected to CLK, and the voltage is lowered.

The operation from time T2to time T5as described above is an operation to read the “A” state (“A”-state read).

Next, from time T5to time T6, the sequencer17raises the voltage of the selected word line WL from AR to BR, and performs the same operation as the above-described operation from time T2to time T5, thereby performing an operation to read the “B” state (“B”-state read).

Next, from time T6to time T7, the sequencer17raises the voltage of the selected word line WL from BR to CR, and performs the same operation as the above-described operation from time T2to time T5, thereby performing an operation to read the “C” state (“C”-state read).

By performing the operations from time T1to time T7as described above, weight data are read out to latch circuits DL.

The sequencer17then performs product operations using the latch circuit sets130, and performs a sum operation using the bit counter13B. As a result, the sequencer17outputs the operation result of the bit counter13B to the memory controller200as a product-sum operation result (DATA) (S1012).

This transmissions/receptions of signals DQ will be collectively referred to as a command sequence.

<1-2-3> Example

The difference between the command sequence in the present embodiment and those of a read operation and write operation will be described. The read operation will be described with reference toFIG.12. As shown inFIG.12, in the read operation, the memory controller200first issues a read command set to the NAND flash memory100, whereby data is read from the memory cell array10of the NAND flash memory100out to the data register/bit counter13. The memory controller200then issues a data output command set to the NAND flash memory100, thereby receiving the data read out to the data register/bit counter13.

Next, the write operation will be described with reference toFIG.13. As shown inFIG.13, in the write operation, the memory controller200issues a write command set (including write data) to the NAND flash memory100, whereby write data are written in the memory cell array10of the NAND flash memory100.

As described above, in the read operation, data is output as signal DQ by the memory controller200issuing a data output command set after issuing a read command set (after transitioning to the busy state). In the write operation, write data are written in the memory cell array10by the memory controller200issuing a write command set including write data.

<1-3> Advantageous Effects

In the present embodiment, the memory controller200issues a product-sum operation command set including identification target data and an address of weight data, thereby receiving a product-sum operation result based on the identification target data and weight data from the NAND flash memory100.

In recent years, the size of one page of the NAND flash memory has increased as many as several kilobytes. Therefore, the NAND flash memory includes a large-capacity data register, thereby exhibiting excellent Sequential Write/Read performance. However, there has been no specific report of application of such a technical advantage to AI technology. For example, if memory technology is applied to arithmetic operation methods or algorithms characteristic of AI, a novel technical area may be developed, which may contribute to human life and society.

The present embodiment enables a product-sum operation simply by causing the memory controller200to issue a product-sum operation command set to a NAND flash memory with a large one-page size; therefore, a high-speed AI function is easily realized. Accordingly, mere use of the NAND flash memory makes it possible to easily obtain a high-quality AI function.

<1-4> Specific Example

A specific example of the first embodiment when identification target data is input to the NAND flash memory will be described. In particular, the flow of identification target data, weight data, and operation results will be described.

As shown inFIG.3, when attention is focused on one identification target data item (such as X1), one data item is used for arithmetic operations corresponding to the number of nodes arranged in parallel in the hidden layer52. For example, in the case ofFIG.3, data item X1is used for data items Y1, Y2, and Y3. Namely, data item X1is subjected to a product operation with each of weights W11, W21, and W31. The above-described NAND flash memory performs one product operation with one latch circuit set130. In the case ofFIG.3, three product operations are performed in relation to data X1; therefore, three latch circuit sets130are used. Specifically, as shown inFIG.4, the identification target data items (X1to X4) are assigned to each of the three latch circuit sets130. As described above, the number of required identification target data items changes depending on the number of product operations performed on one identification target data item. In this case, the number of required data items X1to X4is three each. Namely, the identification target data items input to the data register13A need to be X1, X1, X1, X2, X2, X2, X3, X3, X3, X4, X4, and X4. Those identification target data items may be generated by the memory controller200, by the sequencer17, or by another component. Weight data for performing a product operation with each identification target data item is read out from the memory cell array10to latch circuits. Then, the latch circuit set130performs a product operation of the read weight data and the identification target data item, and the product operation result is stored in a latch circuit. Biases (constant terms) B1to B3added to the product-sum operation results are also stored in latch circuits as weight data.

The bit counter13B then reads out a product operation result from each latch circuit set130, performs a sum operation, and outputs a product-sum operation result. The bit counter13B generates data Y of the hidden layer and generates output data.

A specific method for using the latch circuit set130will be described with reference toFIG.15.FIG.15illustrates a case where each of weight data and identification target data is four-valued (multi-valued).

As shown inFIG.15, an AR read result, a BR read result, and a CR read result are required to enable the latch circuit set130to determine four-valued data. InFIG.15, for example, an AR read result (“A” flag) is stored in latch circuit DL(A), a BR read result (“B” flag) is stored in latch circuit DL(B), and a CR read result (“C” flag) is stored in latch circuit DL(C). The latch circuit set130determines weight data based on data stored in DL(A), DL(B), and DL(C). When weight data is not four-valued, as-needed latch circuits DL may be used.

Four-valued identification target data is stored in, for example, two latch circuits DL(D) and DL(E). When identification target data is not four-valued, as-needed latch circuits DL may be used.

The product operation result is stored in, for example, latch circuit DL(F). However, another latch circuit DL may be used for the product operation result.

The sum operation is performed by the bit counter13B, and the product-sum operation result is stored in a storage area which is not shown.

<2> Second Embodiment

Next, the second embodiment will be described. In the first embodiment, data is determined via a bit line. In the second embodiment, the case where data is determined via the source line will be described. Hereinafter, descriptions of portions similar to those of the first embodiment will be omitted.

<2-1> Specific Configuration of Identification Device

<2-1-1> NAND Flash Memory

Here, as a specific hardware configuration for realizing the identification device5, the memory system400will be described as an example.

As shown inFIG.16, the NAND flash memory100included in the memory system400further includes a source line control circuit23. The source line control circuit23controls the voltage of the source line SL.

<2-1-2> Voltage Generator and Source Line Control Circuit

The voltage generator22and source line control circuit23will be described with reference toFIG.17.

FIG.17shows part of the voltage generator22. The voltage generator22includes a constant current source50, NMOS transistors51,52,54, and55, and a resistance element53. InFIG.17, the voltage generator22includes a circuit for generating signal BLC of the sense amplifiers SA and a circuit for charging the source line.

Specifically, the constant current source50generates current Iref1and supplies it as signal BLC. NMOS transistor51has one end and a gate electrode which are connected to the output end of the constant current source50.

NMOS transistor52has one end to which signal Vint is input, a gate electrode to which signal Initialize is input, and the other end connected to the other end of NMOS transistor51.

One end of the resistance element53is connected to the other ends of NMOS transistors51and52.

NMOS transistor54has one end connected to the other end of the resistance element53, a gate electrode to which signal SW to SRC is input, and the other end connected to the source line SL.

NMOS transistor55has one end connected to the other end of the resistance element53, a gate electrode to which signal SW to VSS is input, and the other end connected to the reference voltage VSS.

The source line control circuit23includes a voltage comparator23-1and a detection circuit23-2. The source line control circuit23monitors the total cell current (Icell_total), and convert it into a digital value. Namely, the circuit ofFIG.17is an example of the circuit for determining the cell-source current value (value of the current flowing through the source line) with an analog circuit. InFIG.17, the current value Icell_total corresponding to the product-sum operation result is mirrored by a current mirror circuit, and is compared with a current value (reference value) provided by a regulator.

The voltage comparator23-1compares the voltage of the source line SL with reference voltage VREF_SRC, and provides the source line SL with a voltage. As shown inFIG.17, the voltage comparator23-1includes a PMOS transistor60, a comparator61, and an NMOS transistor62.

PMOS transistor60has a gate to which a precharge signal PRECH is input, one end externally supplied with voltage VCC, and the other end connected to the source line SL. Signal PRECH is brought to the “L” level when the bit line is precharged in a data read operation, thereby turning on PMOS transistor60. As a result, the voltage of the source line SL rises.

The comparator61has a non-inversion input terminal (+) connected to the source line SL and an inversion input terminal (−) to which voltage VREF_SRC is input. Namely, the comparator61compares the voltage of the source line SL with voltage VREF_SRC, and outputs an “H”-level signal when the voltage of the source line SL exceeds voltage VREF_SRC. Voltage VREF_SRC takes a value equal to or larger than the absolute value of the read level V01 for “0” data, of which threshold voltage is the lowest.

NMOS transistor62has a drain connected to the source line SL, a grounded source, and a gate provided with the comparison result of the comparator61. Hereinafter, the gate of NMOS transistor62, i.e., the output node of the comparator61will be referred to as node G_Source. The gate width W of NMOS transistor62will be referred to as gate width Wsource1.

The detection circuit23-2includes PMOS transistors71,74, and75, a comparator72, and NMOS transistors73,76,77,80,81-1,81-2,82-1,82-2,84-1, and84-2.

PMOS transistor70has a source connected to the power-supply voltage VDD, and a gate and drain connected to each other. The node to which the gate and drain of PMOS transistor70are connected will be referred to as node P_GATE. For example, the current supplied by PMOS transistor70is expressed as Iref2.

PMOS transistor71has a source connected to the power-supply voltage VDD, and a gate connected to node P_GATE. For example, the current supplied by PMOS transistor71is expressed as Iref3.

PMOS transistors70and71form a current mirror. Therefore, current Iref2is proportional to current Iref3.

The comparator72has a non-inversion input terminal (+) connected to the drain of PMOS transistor70, and an inversion input terminal (−) connected to the drain of PMOS transistor71. Namely, the comparator72compares the voltage VA of the drain of PMOS transistor70with the voltage VB of the drain of PMOS transistor71, and outputs an “H”-level signal when voltage VA exceeds voltage VB.

NMOS transistor73has a drain connected to node P_GATE, a grounded source, and a gate provided with the comparison result of comparator61. The gate width W of NMOS transistor73will be referred to as gate width Wsource2.

PMOS transistor74has a source connected to the power-supply voltage VDD, and a gate and drain connected to each other.

PMOS transistor75has a source connected to the power-supply voltage VDD, a gate connected to the gate and drain of PMOS transistor74, and a drain connected to node N_GATE.

PMOS transistors74and75form a current mirror.

NMOS transistor76has a drain and gate connected to node N_GATE, and a grounded source.

NMOS transistor77has a drain connected to the drain of PMOS transistor71, a gate connected to node N_GATE, and a grounded source.

NMOS transistors76and77form a current mirror.

NMOS transistor80has a drain and gate supplied with the reference current Iref, and a grounded source.

NMOS transistor81-1has a drain connected to the gate and drain of PMOS transistor74, and a gate supplied with the reference current Iref.

NMOS transistor81-2has a drain connected to the source of NMOS transistor81-1, a gate supplied with signal1bai, and a grounded source.

NMOS transistor82-1includes two parallel NMOS transistors (transistors having the same characteristics as NMOS transistor81-1), each having a drain connected to the gate and drain of PMOS transistor74, and a gate supplied with the reference current Iref.

NMOS transistor82-2includes two parallel NMOS transistors (transistors having the same characteristics as NMOS transistor81-2), each having a drain connected to the source of NMOS transistor82-1, a gate supplied with signal2bai, and a grounded source.

NMOS transistor84-1includes four parallel NMOS transistors (transistors having the same characteristics as NMOS transistor81-1), each having a drain connected to the gate and drain of PMOS transistor74, and a gate supplied with the reference current Iref.

NMOS transistor84-2includes four parallel NMOS transistors (transistors having the same characteristics as NMOS transistor81-2), each having a drain connected to the source of NMOS transistor82-1, a gate supplied with signal4bai, and a grounded source.

The sequencer17brings signals1bai,2bai, and4baito the “H” level as appropriate, thereby controlling the values of the currents flowing through PMOS transistors74and75. Therefore, the sequencer17controls the values of the currents flowing through NMOS transistors76and77; as a result, voltage VB is controlled at will.

<2-2> Operation

As described above, the source line control circuit23causes the current mirror circuit to mirror the current value Icell_total corresponding to the product-sum operation result, and compares the current value Icell_total with the current value (reference value) provided by the regulator. To improve the accuracy of arithmetic operations, it is necessary to reduce the variations of the cell current Icell.

As shown in, for example,FIGS.18and19, even if a read operation is performed by using read voltage AR and read voltage BR, it is not uncommon that, for example, the current Icell when voltage BR is applied varies from 20 nA to 100 nA.

Under the circumstances, in the second embodiment, magnitude relationship determination is performed with the read voltage changed in stages, and thereby the absolute value of the cell-source current is finally detected. This will be described with reference toFIG.20.

FIGS.20and21are diagrams for explaining an example of the read operation in the second embodiment. In the second embodiment, for example, read voltage AR applied to the selected word line (Selected WL) is divided into, for example, N stages for one state, such as A0R, A1R, . . . . As shown inFIG.21, a read is performed by first using read voltage A0R, the current flowing through the source line SL is monitored, and the bit line BL that allows a current to flow therethrogh is locked out. Then, a read is performed by using read voltage A1R, the current flowing through the source line is monitored, and the bit line BL that allows a current to flow therethrogh is locked out. By using the other-stage read voltages, the same operation is repeated. The sequencer17stores a read result in a latch circuit by raising signal STB whenever a read voltage is applied.

As shown inFIG.22, in every read operation in the above-described process, Icell determined as “1” is even up at approximately 20 nA [nanoampere]. Therefore, the accuracy of the product-sum operation is improved.

<2-3> Advantageous Effects

In the second embodiment, the product-sum operation result is detected from the current flowing through the source line in a read operation, as described above. Namely, the selected bit line BL is precharged based on input data, and the bit line BL turned on by AR is locked out. By subsequently applying read voltages AR, BR, and CR, the current flowing through the source line is monitored at each time, and the product-sum operation results are obtained from the current values.

At that time, by incrementing the read voltage in stages for each state, the adverse influence of the variations of the cell current on the accuracy is decreased to such an extent that the influence is ignorable. This enables the product-sum operation result to be detected with sufficient accuracy from the current flowing through the source line in a read operation.

In particular, the sum operations are executed in the memory cell array at once in the second embodiment, which contributes to reduction in the chip size.

In existing semiconductor memory devices, all bit lines are selected in a read operation. Namely, there has been no idea of selecting a bit line in accordance with the logic level of input data. Therefore, it has been impossible to get an idea of implementing a product-sum operation.

In the second embodiment, however, the product-sum operation result is realized by selecting a bit line in accordance with the logic level of input data, raising the threshold voltage in stages, locking out the turned-on bit line, and detecting the currents flowing through the source line in the process of repeating the forgoing steps.

Accordingly, the second embodiment can also provide a semiconductor memory device with an arithmetic operation function.

<3> Others

The present invention is not limited to the above-described first and second embodiments. For example, in the first embodiment, the results of the product operations can be obtained before the result of the product-sum operation is obtained; therefore, the results of the product operations may be taken out to the outside of the NAND flash memory100. Furthermore, information that can be taken out to the outside of the NAND flash memory100may be the result of the product-sum operation, or may be an inference obtained by substituting the result of the product-sum operation into an activation function.

InFIG.10, the NAND flash memory100supplies a product-sum operation result to the memory controller200(step S1012). However, the NAND flash memory100may supply an inference (identification score) to the memory controller200. The “inference” indicates a degree of matching between the input data set (input data) and the label associated with the input data. For example, when the input data is a picture, the NAND flash memory100infers what is in the picture (human, car, tree, etc.) of the input data. The result of the inference is referred to as an inference (identification score).

Here, a modification ofFIG.10will be described with reference toFIGS.23and24.

The operations are the same as those described with reference toFIG.10, and descriptions thereof are omitted.

Upon completion of the product-sum operation, the bit counter13B notifies the completion to the sequencer17.

The operations after step S1013will be described with reference toFIG.24.

Upon receipt of the notice of completion of the product-sum operation, the sequencer17determines whether the arithmetic operations have been performed up to the final layer. Specifically, the sequencer17determines whether or not the processing at the final processing node of a plurality of nodes included in the hidden layer52has been completed.

When determining that the processing at the final processing node has not been completed, the sequencer17performs a product-sum operation using the latest product-sum operation result as input data.

Specifically, the sequencer17performs a calculation by inputting the latest product-sum operation result stored in the data register13A into the activation function, and causes the data register13A to store the operation result of the activation function as input data for the next layer. When the relevant layer is the final layer, an inference is obtained by this step.

The data register13A stores the operation result of the activation function as input data for the next layer. Then, the NAND flash memory100repeats step S1005.

When determining that the processing at the final processing node has not been completed, the sequencer17repeats steps S1015, S1016, S1005to S1010, S1013, and S1014.

When determining that the processing at the final processing node has been completed, the sequencer17causes the NAND flash memory100to output the operation result stored in the data register13A as an inference.

The data register13A supplies the inference to the input/output circuit15in accordance with an instruction of the sequencer17.

Then, the input/output circuit15supplies the inference to the memory controller200. The NAND flash memory100may supply the inference (identification score) to the memory controller200in this manner.

While some embodiments have been described, the embodiments have been presented as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and spirit of the invention, and are included in the scope of the claimed inventions and their equivalents.