Patent ID: 12260803

DETAILED DESCRIPTION OF EMBODIMENTS

FIG.1is a configuration diagram of a display device according to an embodiment.

Referring toFIG.1, the display device100can comprise a display panel120, a data processing device130, a gate driving device140, a data driving device110, etc.

The display panel120can be an LCD panel or a self-light-emitting panel such as an OLED panel.

When the display panel120is an LCD panel, the display panel120can comprise a backlight, liquid crystal, and a common electrode. Each pixel P can comprise a pixel electrode and a driving transistor. When a scan signal is supplied to the gate terminal of the driving transistor, the driving transistor is turned on and a data voltage can be supplied to the pixel electrode. Depending on the data voltage, the alignment direction of the liquid crystal can change as an electric field is formed between the pixel electrode and the common electrode. Accordingly, the brightness of the pixel P can be adjusted by changing the degree of transmission of light supplied from the backlight.

A plurality of data lines DL and a plurality of gate lines GL can be arranged in a matrix form on the display panel120. The data line DL can be connected to the source terminal of the driving transistor of each pixel P, and the gate line GL can be connected to the gate terminal of the driving transistor of each pixel P. When the scan signal SCN is supplied to the gate line GL, the driving transistor is turned on and the data voltage VD supplied through the data line DL can be transmitted to the pixel electrode.

A parasitic capacitor can be formed in the data line DL. The parasitic capacitor can be formed between the data line DL and the common electrode or between the data line DL and the pixel electrode. From the perspective of the data driving device110that supplies the data voltage VD, the parasitic capacitor can be recognized as a load. The larger the capacity of the parasitic capacitor, the more power the data driving device110must supply to the data line DL, which can increase power consumption.

The display panel120can be a self-light-emitting panel such as an OLED panel. In addition to the OLED panel, self-light-emitting panels can also use other types of self-light-emitting devices such as micro-LED panels.

Each pixel P of the OLED panel can comprise a scan transistor, a driving transistor, an OLED, etc. When a scan signal SCN is supplied to the gate of the scan transistor, the scan transistor is turned on and the data voltage VD can be supplied to the driving transistor through the scan transistor. In the OLED panel, the data voltage VD can be supplied to the gate terminal of the driving transistor. The magnitude of the conduction current of the driving transistor can be determined depending on the magnitude of the data voltage VD, and the brightness of the OLED connected to the driving transistor can be adjusted depending on the magnitude of the conduction current of the driving transistor.

A plurality of data lines DL and a plurality of gate lines GL can be arranged in a matrix form on the display panel120. The data line DL can be connected to the source terminal of the scan transistor of each pixel P, and the gate line GL can be connected to the gate terminal of the source transistor of each pixel P. When the scan signal SCN is supplied to the gate line GL, the scan transistor is turned on and the data voltage VD supplied through the data line DL can be transmitted to the driving transistor.

A parasitic capacitor can be formed in the data line DL. The parasitic capacitor can be formed between the data line DL and the cathode electrode of the OLED panel or between the data line DL and the anode electrode of the OLED panel. From the perspective of the data driving device110that supplies the data voltage VD, the parasitic capacitor can be recognized as a load. The larger the capacity of the parasitic capacitor, the more power the data driving device110must supply to the data line.

The data processing device130can receive image data from an external device—for example, a host or a device called an application processor (AP). The data processing device130can convert image data in the format of an external device into image data RGB in a format that the data drive device110can process. The data processing device130can transmit converted image data RGB to the data driving device110.

Image data RGB can comprise pixel data representing grayscale values for the plurality of pixels P, respectively. The pixel data for one pixel P has, for example, 8 bits and can express grayscale values from 0 to 255. The data processing device130can generate pixel data for each pixel P, comprise the pixel data in image data RGB, and transmit the image data RGB to the data driving device110.

The data processing device130can transmit a control signal to devices involved in driving the display panel120—for example, the data driving device110and the gate driving device140. The data processing device130can transmit a data control signal to the data driving device110and a gate control signal GCS to the gate driving device140.

Control signals GCS can comprise setting information for each device. For example, the data processing device130can receive setting information from an external device, check the setting information for each device, and then transmit the setting information by including the setting information in the corresponding control signal GCS.

The control signals GCS can comprise timing signals for controlling each device110and140. The timing signal can comprise, for example, a vertical synchronization signal, a horizontal synchronization signal, etc. The data driving device110or the gate driving device140can distinguish frames and each horizontal time according to the timing signal. In terms of controlling the timing of each device110and140, the data processing device130is also called a timing controller.

The gate driving device140can supply a scan signal SCN to the pixels P of the display panel120. The pixels P to which a scan signal SCN for turn-on is supplied can be selected, and the data voltage VD can be supplied to the selected pixels P.

The gate driving device140can supply a scan signal SCN through the gate line GL. A plurality of gate lines GL can be disposed on the display panel120. Each gate line GL can be connected to pixels P arranged in a row in one direction (e.g., horizontal direction). The gate driving device140can supply a scan signal SCN for turn-on to one of the plurality of gate lines GL, so that the pixels P connected to the gate line GL can be selected. The gate driving device140can supply a scan signal SCN for turn-on while changing the gate line GL at every horizontal time.

The data driving device110can drive the pixels P of the display panel120.

The data driving device110can receive image data RGB from the data processing device130. The data driving device110can check the pixel data for each pixel P comprised in the image data RGB, generate a data voltage VD corresponding to the pixel data, and supply the data voltage VD corresponding to each pixel P.

The pixel data can represent a grayscale value for each pixel P. The data driving device110can generate a data voltage VD corresponding to the grayscale value.

The pixel data can be stored in the latch circuit of the data driving device110and can be output as a digital signal. The data driving device110can convert a digital signal into an analog voltage using reference gamma voltages.

There is a difference between the gradation corresponding to physical brightness and the gradation corresponding to the brightness perceived by humans. Correcting this difference is called gamma conversion. When converting a digital signal to an analog voltage, the data driving device110can also apply gamma conversion at the same time. For example, the data driving device110can simultaneously apply digital-to-analog conversion and gamma conversion by using analog voltages used for digital-to-analog conversion as voltages to which gamma conversion has been applied—reference gamma voltages.

The analog voltage may not be suitable for driving the pixel P due to its low power level. Therefore, the data driving device110can amplify the analog voltage to generate the data voltage VD, and supply the data voltage VD with a relatively high power level to the pixel P.

FIG.2is a configuration diagram of a data driving device according to an embodiment.

Referring toFIGS.1and2, the data driving device110can comprise a first channel circuit210a, a second channel circuit210b, and a reference gamma voltage generation circuit230.

The first channel circuit210acan comprise a first latch circuit211a, a first level shifter212a, a first DAC213a, and a first buffer214a. The first channel circuit210acan receive a first pixel data PXDa corresponding to the grayscale value of the first pixel, generate a first data voltage VDa, and supply the first data voltage VDa to the first data line connected to the first pixel.

The second channel circuit210bcan comprise a second latch circuit211b, a second level shifter212b, a second DAC213b, and a first buffer214b. The second channel circuit210bcan receives the second pixel data PXDb corresponding to the grayscale value of the second pixel, generate a second data voltage VD, and supply the second data voltage VD to the second data line connected to the second pixel.

The first latch circuit211aand the second latch circuit211bcan sequentially store pixel data PXD received through a data bus line.

The first latch circuit211aand the second latch circuit211bcan each comprise two latches therein, that is, a first latch and a second latch, but is not limited thereto. The first latch can store pixel data to be output at the next horizontal time, that is, the second horizontal time, and the second latch can store pixel data to be output at the current horizontal time, that is, the first horizontal time. When the second horizontal time comes, pixel data to be output at the next horizontal time, that is, the third horizontal time, can be stored in the first latch, and the pixel data stored in the first latch can be moved to the second latch and stored.

The output timing of each of the first latch circuit211aand the second latch circuit211bcan be determined according to the latch output signal generated at each horizontal time. The latch output signal can be synchronized with the horizontal synchronization signal. Alternatively, the latch output signal can be a signal that has a different phase from the horizontal synchronization signal but has the same cycle length.

The first latch circuit211acan transfer the first pixel data PXDa stored in the first latch circuit211ato the first level shifter212aaccording to the latch output signal.

The second latch circuit211bcan transfer the second pixel data PXDb stored in the second latch circuit211bto the second level shifter212baccording to the latch output signal.

The first level shifter212acan convert the first pixel data PXDa into a first digital signal DSa, and the second level shifter212bcan convert the second pixel data PXDb into a second digital signal DSb.

The first pixel data PXDa and the second pixel data PXDb can be signals with a low voltage or power level. The first level shifter212acan convert the first pixel data PXDa into a first digital signal DSa with a high voltage or power level. The second level shifter212bcan convert the second pixel data PXDb into a second digital signal DSb with a high voltage or power level.

The first DAC213acan receive the first digital signal DSa and drive the gate terminals of the first switches therein. The first DAC213acan convert the first digital signal DSa into the first analog voltage ASa by driving the gate terminals of the first switches.

The second DAC213bcan receive the second digital signal DSb and drive the gate terminals of the second switches therein. The second DAC213bcan convert the second digital signal DSb into the second analog voltage ASb by driving the gate terminals of the second switches.

The first DAC213acan comprise a plurality of first switches. The first switches can selectively connect one of a plurality of reference gamma voltage lines to which a plurality of reference gamma voltages are supplied to the output terminal according to on the on-off state. The output terminal can be connected to the first buffer214a. The voltage formed on one selected reference gamma voltage line can be the first analog voltage ASa. The first digital signal DSa can change the on-off state of the first switches while being supplied to the gate terminals of the first switches. At this time, the gate load can increase at the switch whose state is changed. For example, the gate load may increase in a switch that changes from an on state to an off state or a switch that changes from an off state to an on state.

The second DAC213bcan comprise a plurality of second switches. The second switches can selectively connect one of a plurality of reference gamma voltage lines to which a plurality of reference gamma voltages are supplied to the output terminal according to the on-off state. The output terminal can be connected to the second buffer214b. The voltage formed on one selected reference gamma voltage line can be the second analog voltage ASb. The second digital signal DSb can change the on-off state of the second switches while being supplied to the gate terminals of the second switches. At this time, the gate load can increase at the switch whose state is changed. For example, the gate load can increase in a switch that changes from an on state to an off state or a switch that changes from an off state to an on state.

The first digital signal DSa can be supplied to drive the gate terminals of the first switches, and the second digital signal DSb can be supplied to drive the gate terminals of the second switches. The first digital signal DSa can be output by the first level shifter212aand the second digital signal DSb can be output by the second level shifter212b. From this perspective, the gate load of the first switches of the first DAC213acan become part of the output load of the first level shifter212a, and the gate load of the second switches of the second DAC213bcan become a part of the output load of the second level shifter212b.

The first DAC213aand the second DAC213bcan have different gate loads for the first digital signal DSa and the second digital signal DSb having the same grayscale value. For example, when the grayscale value is in the range of 0 to 255, the grayscale value indicated by the first digital signal DSa is 0, and the grayscale value indicated by the second digital signal DSb is 0, the gate load of the first DAC213aand the gate load of the second DAC213bcan be different.

From the perspective of the first level shifter212aand the second level shifter212b, the output loads of the first level shifter212aand the second level shifter212bcan be different for the same grayscale value.

When the gate load is proportional to the number of switches that change the state, the first DAC213aand the second DAC213bcan have different numbers of switches that are turned on for the first digital signal DSa and the second digital signal DSb having the same grayscale value. Alternatively, the first DAC213aand the second DAC213bcan have different numbers of switches that are turned off for the first digital signal DSa and the second digital signal DSb having the same grayscale value.

The arrangement structure of the first switches in the first DAC213aand the arrangement structure of the second switches in the second DAC213bcan be different. Alternatively, the structures in which the first switches and the second switches are connected to the plurality of reference gamma voltage lines can be different. At this time, the number of first switches of the first DAC213aand the number of second switches of the second DAC213bcan be the same.

Meanwhile, depending on the grayscale value, the sum of the number of switches that are turned on among the first switches and the number of switches that are turned on among the second switches can be constant. Accordingly, depending on the grayscale value, the sum of the gate loads of the first DAC213aand the second DAC213bcan be substantially the same.

The first grayscale value can be the lowest grayscale value, for example, 0, and the second grayscale value can be the highest grayscale value, for example, 255.

The average gate load of the first DAC213aand the second DAC213bfor the entire grayscale value range—for example, 0 to 255—can be the same. From another perspective, the average number of turn-on switches or the average number of turn-off switches of the first DAC213aand the second DAC213bcan be the same in the entire grayscale value range.

In the entire grayscale value range, the sum of the gate loads of the first DAC213aand the second DAC213bcan be substantially the same. For example, when defining the grayscale value obtained by subtracting the first grayscale value from the highest grayscale value as the second grayscale value, the gate load that combines the gate load of the first DAC213afor the first grayscale value and the gate load of the second DAC for the second grayscale value may be substantially the same over the entire grayscale value range.

The second DAC213bcan have an inverted structure from that of the first DAC213a. Through this, as described above, it is possible to have different gate loads for the same grayscale value and make the sum of the gate loads substantially the same over the entire grayscale value range.

The first DAC213aand the second DAC213beach have a plurality of first switches and a plurality of second switches connecting one of the plurality of reference gamma voltage lines to which the plurality of reference gamma voltages are supplied to the output terminal. Here, the connection relationship between the plurality of reference gamma voltage lines and the first switches can be different from the connection relationship between the plurality of reference gamma voltage lines and the second switches.

The second digital signal DSb can have the form of an inverted signal with respect to the first digital signal DSa. Through this, as described above, it is possible to have different gate loads for the same grayscale value and make the sum of the gate loads substantially the same over the entire grayscale value range.

The first channel circuit210aand the second channel circuit210bcan comprise buffers214aand214bdisposed between the output terminals of the DACs213aand213band the pixel, respectively.

The first buffer214acan amplify the output of the first DAC213aand supply it to the first data line connected to the first pixel. For example, the first buffer214acan amplify the first analog voltage ASa to generate the first data voltage VDa and supply the first data voltage VDa to the first data line.

The second buffer214bcan amplify the output of the second DAC213band supply it to the second data line connected to the second pixel. For example, the second buffer214bcan amplify the second analog voltage ASb to generate the second data voltage VDb and supply the second data voltage VDb to the second data line.

The first data line to which the first channel circuit210asupplies the first data voltage VDa and the second data line to which the second channel circuit210bsupplies the second data voltage VDb can be disposed adjacent to each other in the display panel. Two adjacent pixels, that is, the first pixel and the second pixel, are likely to have the same or similar grayscale values. According to the above-described embodiment, the sum of the gate loads of the DACs213aand213bof the first channel circuit210aand the second channel circuit210bthat drive two adjacent pixels does not have large fluctuations in the entire grayscale value range. Therefore, it is possible to reduce the peak current and minimize the generation of electromagnetic waves or noise due to instantaneous current fluctuations.

The data driving device110according to the embodiment can comprise a plurality of first channel circuits210aand a plurality of second channel circuits210b. The plurality of first channel circuits210aand the plurality of second channel circuits210bcan be disposed alternately in one direction. For example, in one direction, the plurality of first channel circuits210acan be arranged in odd numbers, and the plurality of second channel circuits210bcan be arranged in even numbers.

The data driving device110can comprise a reference gamma voltage generation circuit230that supplies reference gamma voltages VGM to the first DAC213aand the second DAC213b.

FIG.3is a configuration diagram of a reference gamma voltage generation circuit according to an embodiment.

Referring toFIG.3, the reference gamma voltage generation circuit230can divide the voltage between the first gamma driving voltage VH and the second gamma driving voltage VL to generate a plurality of reference gamma voltages VGM. The first gamma driving voltage VH can be greater than the second gamma driving voltage VL. The reference gamma voltage generation circuit230can comprise a programmable gamma circuit310, a voltage dividing circuit320, etc.

The reference gamma voltage generation circuit230can comprise a first reference gamma voltage buffer331for buffering or amplifying the first gamma driving voltage VH and a second reference gamma voltage buffer332for buffering or amplifying the second gamma driving voltage VL.

The programmable gamma circuit310can receive the first gamma driving voltage VH and the second gamma driving voltage VL to generate a plurality of buffer voltages VBF, and supply the buffer voltages VBF to the voltage dividing circuit320.

The programmable gamma circuit310can adjust the level of the buffer voltages VBF according to the level adjustment signal. The level adjustment signal can be generated in the data processing device130, but this is not limited.

The voltage dividing circuit320can comprise resistance string. A plurality of nodes can be formed in the resistance string. The buffer voltages VBF transmitted from the programmable gamma circuit310can be supplied to some nodes among the plurality of nodes. The voltage dividing circuit320can generate voltages having different levels at a plurality of nodes using buffer voltages VBF, and output the voltages generated at the plurality of nodes as a plurality of reference gamma voltages VGM.

FIG.4is a configuration diagram of a programmable gamma circuit according to an embodiment.

Referring toFIG.4, the programmable gamma circuit310can comprise a first resistance string410whose one end is connected to the first gamma driving voltage VH and the other end is connected to the second gamma driving voltage VL.

A plurality of first nodes can be formed in the first resistance string410. The plurality of first nodes can be divided into a plurality of groups.

The programmable gamma circuit310can comprise a plurality of multiplexers420ato420n.

A plurality of multiplexers420ato420ncan be connected to the plurality of first nodes formed in the first resistance string410. The plurality of first nodes comprised in one group can be connected to one multiplexer.

Each multiplexer420ato420ncan output a voltage of one node among the plurality of first nodes belonging to each group according to the level adjustment signal.

In this way, the programmable gamma circuit310can generate N buffer voltages VBFa to VBFn whose levels can be adjusted (N is a natural number).

FIG.5is a configuration diagram of a voltage dividing circuit according to an embodiment.

Referring toFIG.5, the voltage dividing circuit320can comprise a plurality of buffers520ato520nfor buffering or amplifying the buffer voltages VBFa to VBFn. The voltage dividing circuit320can comprise a second resistance string510in which a plurality of nodes are formed.

The buffer voltages VBFa to VBFn can be supplied to at least one node among a plurality of nodes through the buffers520ato520n. Voltages of different levels can be generated in a plurality of nodes by these buffer voltages VBFa to VBFn.

The voltage dividing circuit320can output voltages formed at a plurality of nodes as reference gamma voltages VGM0 to VGM255.

The first DAC and the second DAC according to the embodiment can convert the digital signal corresponding to the grayscale value into an analog voltage using these reference gamma voltages VGM0 to VGM255.

FIG.6is a first example configuration diagram of a first DAC according to an embodiment, andFIG.7is a second example configuration diagram of a second DAC according to an embodiment.

Referring toFIGS.6and7, the first DAC613aand the second DAC613bcan each comprise a plurality of switches.

The plurality of switches can selectively connect one of the plurality of reference gamma voltage lines supplied with the plurality of reference gamma voltages VGM0 to VGM255 to the output terminal.

The first switches arranged in the first DAC613aand the second switches arranged in the second DAC613bcan have different arrangement structures or different connection relationships with the reference gamma voltage lines. Through this, the first DAC613aand the second DAC613bcan have different gate loads for the same grayscale value, and can have the same gate load for different grayscale values.

For example, inFIGS.6and7, a signal for the first bit (DS<0>) of the digital signal can be supplied to the gate terminal of the lowest switch, and a signal for the second bit (DS<1>) of the digital signal can be supplied to the gate terminal of the top switches. In this way, a signal for the 7th bit (DS<7>) of the digital signal can be supplied to the gate terminal of the uppermost switch. A plurality of reference gamma voltages VGM0 to VGM255 can be connected to the lowest switch. In this case, the reference gamma voltage line supplied with the lowest reference gamma voltage VGM0 and the reference gamma voltage line supplied with the highest reference gamma voltage VGM255 can be oppositely connected to each other at the lowest switch in the first DAC613aand the second DAC613b. For example, as shown inFIG.6, in the first DAC613a, the reference gamma voltage line to which the highest reference gamma voltage VGM255 is supplied can be connected to the lowest switch, and the reference gamma voltage line to which the lowest reference gamma voltage VGM0 is supplied can be connected to the uppermost switch. On the contrary, as shown inFIG.7, in the second DAC613b, the reference gamma voltage line to which the highest reference gamma voltage VGM255 is supplied can be connected to the uppermost switch, and the reference gamma voltage line to which the lowest reference gamma voltage VGM0 is supplied can be connected to the lowest switch.

Through this, the gate load of the first DAC613aand the second DAC613bcan be different for the same lowest grayscale value. Additionally, the gate loads of the first DAC613aand the second DAC613bcan be the same for different grayscale values—for example, the lowest grayscale value and the highest grayscale value.

FIG.8is a diagram showing a second example of a first DAC and a second DAC according to an embodiment.

Referring toFIG.8, when the first digital signal DS is supplied to the first DAC813a, the second digital signal DS (bar) having a phase inverted from the first digital signal DScan be supplied to the second DAC813b.

For the same grayscale value, the first DAC813aand the second DAC813bcan generate the same analog voltage. However, unlike the first DAC813a, the second DAC813bcan drive the second switches according to the digital signal of the inverted phase, so that the gate load of the first DAC813aand the second DAC813bcan be different for the same grayscale value.

FIG.9is a diagram showing a third example of a first DAC and a second DAC according to an embodiment.

Referring toFIG.9, the first DAC913acan have the form of a P-DAC, and the second DAC913bcan have the form of an N-DAC.

The P-DAC913acan convert a digital signal for driving a pixel into an analog voltage AS(p) with positive polarity. The P-DAC913acan be supplied with first reference gamma voltages VGM(p) having positive polarity. The P-DAC913acan selectively output one of the first reference gamma voltages VGM(p) as an analog voltage AS(p) having a positive polarity according to the input digital signal.

The N-DAC913bcan convert a digital signal for driving a pixel into an analog voltage AS(n) with negative polarity. The N-DAC913bcan be supplied with second reference gamma voltages VGM(n) having negative polarity. The N-DAC913bcan selectively output one of the second reference gamma voltages VGM(n) as an analog voltage AS(n) having a negative polarity according to the input digital signal.

The P-DAC913aand N-DAC913bcan have different gate loads for the first and second digital signals having the same grayscale value. For example, the P-DAC913aand N-DAC913bcan have different gate loads for the same lowest grayscale value. Additionally, the P-DAC913aand N-DAC913bcan have different gate loads can be present for the same highest grayscale value.

The P-DAC913aand N-DAC913bcan have gate loads of the same size for different grayscale values. For example, the gate load of the P-DAC913afor the lowest grayscale value and the gate load of the N-DAC913bfor the highest grayscale value can be the same. Additionally, the gate load of the P-DAC913afor the highest grayscale value and the gate load of the N-DAC913bfor the lowest grayscale value can be the same. The sum of the gate load of the P-DAC for the lowest grayscale value and the gate load of the N-DAC for the highest grayscale value can be the same according to a grayscale value.

The data driving device can comprise a plurality of P-DACs913aand a plurality of N-DACs913b. The P-DACs913aand N-DACs913bcan be disposed alternately in one direction. The display panel driven by this data driving device can be a liquid crystal display panel.

FIG.10is a graph showing the gate load of a DAC of related technology and the gate load of a DAC according to an embodiment.

FIG.10shows the gate load when one scan line is driven with the same grayscale value.

Referring toFIG.10, the DAC of related technology had a gate load1010that varied greatly depending on the grayscale value. For example, if one scan line has the lowest grayscale value (e.g., the grayscale value corresponding to black) and the next scan line has the highest grayscale value (e.g., the grayscale value corresponding to white), the gate load1010of the DAC fluctuated greatly.

On the other hand, the gate load1020of the DAC according to the embodiment can maintain a constant level in the entire grayscale value range regardless of the change in the grayscale value.

According to the embodiment, the peak current of DACs can be reduced and the current fluctuations in DACs can be alleviated. According to the embodiment, the image quality of the display panel can be improved by minimizing the generation of electromagnetic waves or noise caused by DACs.