Patent ID: 12212339

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, various embodiments are described with reference to the accompanying drawings.

As is traditional in the field, the embodiments are described, and illustrated in the drawings, in terms of functional blocks, units and/or modules. Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units and/or modules being implemented by microprocessors or similar, they may be programmed using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. In embodiments, each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit and/or module of the embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the present scope. Further, the blocks, units and/or modules of the embodiments may be physically combined into more complex blocks, units and/or modules without departing from the present scope.

FIG.1is a block diagram of a memory system20according to embodiments.

Referring toFIG.1, the memory system20may include a memory controller100and a memory module MM. The memory module MM may include a plurality of memory chips. The plurality of memory chips200may include a plurality of data chips200ato200k, a first parity chip200pa, and a second parity chip200pb. Each of the plurality of memory chips200may be referred to as a semiconductor memory device.

The memory controller100may generally control operation of the memory system20and control a general data exchange operation between an external host and memories (or the memory chips200). For example, the memory controller100may control the memory chips200to write data or read data, in response to a request of the host.

Also, the memory controller100may control operations of the memory chips200by applying operation commands for controlling the memory chips200. According to an embodiment, each of the memory chips200may be a dynamic random access memory (DRAM) including volatile memory cells.

According to an embodiment, the number of data chips200ato200kmay be 16, but embodiments are not limited thereto. According to an embodiment, each of the data chips200ato200kmay be referred to as a data memory, and each of the first and second parity chips200paand200pbmay be referred to as an error correction code (ECC) memory or a redundant memory.

The memory controller100may apply a command CMD and an address ADDR to the memory module MM and may exchange a codeword set SCW with the memory module MM.

The memory controller100may include an ECC circuit130, and the ECC circuit130may generate a parity data set by performing ECC encoding on a main data set and metadata by using a parity generation matrix and may provide the codeword set SCW including the main data set, the metadata, and the parity data set to the memory module MM in a write operation. The main data set may be stored in the data chips200ato200k, and the metadata and a portion of the parity data set may be stored in the first parity chip200pa, and the other portion of the parity data set may be stored in the second parity chip200pb.

According to some embodiments, p (where p is a positive integer) bits output by each of the memory chips200may be referred to as a symbol. For example, p may be 16. The ECC circuit130may read a first symbol and a second symbol from each of the memory chips200and may correct an error with respect to the first symbol and the second symbol. The first symbol may denote p bits firstly output by the memory chips200, and the second symbol may denote p bits later output by the memory chips200. The first symbols and the second symbols output by the memory chips200may be included in a codeword.

The ECC circuit130may generate a syndrome with respect to the codeword by using the parity generation matrix. The ECC circuit130may identify a symbol including an error bit based on the syndrome. That is, the ECC circuit130may identify whether an error bit is generated in the first symbol or the second symbol. Also, the ECC circuit130may identify an error pattern of the symbol in which an error is generated, based on the syndrome.

However, when the number of parity data sets is less than the number of bits included in the main data set and the metadata set, it may be difficult to identify a memory chip in which an error is output, based on the syndrome. That is, the ECC circuit130may not identify which memory chip outputs a symbol in which an error is generated, only based on the syndrome.

The ECC circuit130according to an embodiment may generate estimation syndromes with respect to the error pattern by using a plurality of parity check sub-matrices included in a parity check matrix. The plurality of parity check sub-matrices may correspond to symbols output by the memory chips200, respectively. Thus, the plurality of estimation syndromes may correspond to the memory chips200. For example, each estimation syndrome may respectively correspond to a memory chip.

The ECC circuit130may compare the syndrome with the estimation syndrome and may identify a memory chip from which an error pattern is output, based on a result of the comparison. The ECC circuit130may correct an error of the codeword, based on the symbol and the error pattern output by the identified memory chip.

FIG.2is a block diagram of the memory controller100in the memory system20ofFIG.1, according to embodiments.

Referring toFIG.2, the memory controller100may include a central processing unit (CPU)110, a host interface120, a data register125, the ECC circuit130, a command buffer190, and an address buffer195. The ECC circuit130may include an ECC encoder140, an ECC decoder150, and a memory180.

The host interface120may receive a request REQ and main data SDQ provided from an external host, generate metadata MDT related to the main data SDQ, provide the main data SDQ to the data register125, and provide the metadata MDT to the ECC encoder140. The data register125may provide the main data SDQ to the ECC circuit130.

The ECC encoder140may output a codeword set SCW1by performing ECC encoding on the main data SDQ and the metadata MDT by using a parity generation matrix.

The ECC decoder150may output a decoding state flag to the CPU110by using a parity check matrix with respect to a codeword set SCW2and may provide the main data set SDQ or corrected main data set C SDQ to the CPU110. The ECC decoder150may generate a syndrome by performing ECC decoding on the codeword set SCW2by using the parity check matrix. The ECC decoder150may identify an error pattern included in the codeword set SCW2, based on the syndrome.

The ECC decoder150may generate a plurality of estimation syndromes with respect to the error pattern by using a plurality of parity check sub-matrices included in the parity check matrix. The plurality of estimation syndromes may correspond to the plurality of memory chips, respectively.

The ECC decoder150may compare the syndrome with the plurality of estimation syndromes and correct a symbol received from a memory chip corresponding to an estimation syndrome that is the same as the syndrome. That is, based on the syndrome and the estimation syndromes, the ECC decoder150may correct a correctable error of the main data set included in the codeword set SCW2, in a symbol unit.

The memory180may store the parity generation matrix and the parity check matrix.

The CPU110may receive the main data set SDQ or the corrected main data set C SDQ and control the ECC circuit130, the command buffer190, and the address buffer195. The command buffer190may store a command CMD corresponding to a request REQ and transmit the command CMD to the memory module MM, according to control by the CPU110.

The address buffer195may store an address ADDR and transmit the address ADDR to the memory module MM according to control by the CPU110.

FIG.3illustrates data sets corresponding to a plurality of burst lengths provided to each of the data chips and the parity chips or output from each of the data chips and the parity chips in the memory system20ofFIG.1.

Referring toFIG.3, each of the data chips200ato200kand the parity chips200paand200pbmay perform a burst operation.

Here, the burst operation may refer to an operation, in which the data chips200ato200kand the parity chips200paand200pbwrite or read a great amount of data by sequentially decreasing or increasing an address from an initial address received from the memory controller100. A basic unit of the burst operation may be referred to as a burst length BL.

Referring toFIG.3, data sets SDQ1to SDQk may be input to, or output from, the data chips200ato200k, respectively. Each of the data sets SDQ1to SDQk may include data bursts DQ_BL1to DQ_BL8corresponding to a plurality of burst lengths. The data sets SDQ1to SDQk may correspond to the main data set SDQ. InFIG.3, the burst length BL is assumed to be 4. That is, 4 bits received through first to fourth DQ pins DQ1to DQ4may be the data bursts.

Referring toFIG.3, each of the data sets SDQ1to SDQk may include 2 symbols. A symbol may include 4 data bursts and may include 16 bits. The symbol output from each data firstly chip may be referred to as a first symbol, and the subsequent symbol may be referred to as a second symbol. For example, the data set SDQ1may include a first symbol S11and a second symbol S12, and the data set SDQk may include a first symbol Sk1and a second symbol Sk2.

While the burst operation is performed by each of the data chips200ato200k, metadata MDT and first parity data PRTL corresponding to a plurality of burst lengths may be input to, or output from, the first parity chip200pa, and second parity data PRTM corresponding to a plurality of burst lengths may be input/output to/from the second parity chip200pb. The second parity data PRTM may include first sub-parity data PRTM1and second sub-parity data PRTM2.

The first parity data PRTL may be error locator parity data and may be related to a position of error bits included in the main data set SDQ, and the second parity data PRTM may be error size parity data and may be related to the size (or for example the number) of the error bits included in the main data set SDQ.

FIG.4is a block diagram of a component of one of the data chips200aofFIG.1. In embodiments, the block diagram ofFIG.4may also correspond to one or more components of other memory chips200.

Referring toFIG.4, the data chip200amay include a control logic circuit210, an address buffer220, a bank control logic230, a row address multiplexer240, a column address (CA) latch250, a row decoder260, a column decoder270, a memory cell array300, a sense amplifier285, an input and output (I/O) gating circuit290, a data I/O buffer295, and a refresh counter245.

The memory cell array300may include first to fourth bank arrays300ato300d. Also, the row decoder260may include first to fourth bank row decoders260ato260dconnected to the first to fourth bank arrays300ato300d, respectively, the column decoder270may include first to fourth bank column decoders270ato270dconnected to the first to fourth bank arrays300ato300d, respectively, and the sense amplifier285may include first to fourth bank sense amplifiers285ato285dconnected to the first to fourth bank arrays300ato300d, respectively.

The first to fourth bank arrays300ato300d, the first to fourth bank sense amplifiers285ato285d, the first to fourth bank column decoders270ato270d, and the first to fourth bank row decoders260ato260dmay form first to fourth banks, respectively. Each of the first to fourth bank arrays300ato300dmay include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at a point at which the plurality of word lines and the plurality of bit lines cross each other.

The data chip200ais illustrated inFIG.4as including four banks. However, embodiments are not limited thereto, and according to an embodiment, the data chip200amay include an arbitrary number of banks.

The address buffer220may receive an address ADDR including a bank address BANK ADDR, a row address ROW_ADDR, and a column address COL_ADDR, from the memory controller100. The address buffer220may provide the received bank address BANK ADDR to the bank control logic230, provide the received row address ROW_ADDR to the row address multiplexer240, and provide the received column address COL_ADDR to the column address latch250.

The bank control logic230may generate bank control signals in response to the bank address BANK ADDR. In response to the bank control signals, a bank row decoder from among the first to fourth bank row decoders260ato260d, the bank row decoder corresponding to the bank address BANK ADDR, may be activated, and a bank column decoder from among the first to fourth bank column decoders270ato270d, the bank column decoder corresponding to the bank address BANK ADDR, may be activated.

The row address multiplexer240may receive the row address ROW_ADDR from the address buffer220and receive a refresh row address REF ADDR from the refresh counter245. The row address multiplexer240may selectively output the row address ROW_ADDR or the refresh row address REF ADDR as a row address RA. The row address RA output from the row address multiplexer240may be applied to each of the first to fourth bank row decoders260ato260d.

The bank row decoder from among the first to fourth bank row decoders260ato260d, the bank row decoder being activated by the bank control logic230, may decode the row address RA output from the row address multiplexer240and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address RA. The activated bank row decoder may generate the word line driving voltage by using a power voltage VDD and provide the word line driving voltage to the corresponding word line.

The column address latch250may receive the column address COL_ADDR from the address buffer220and may temporarily store the received column address COL_ADDR or a mapped column address MCA. Also, the column address latch250may gradually or sequentially increase the received column address COL_ADDR in a burst mode. The column address latch250may apply the column address COL_ADDR temporarily stored or gradually or sequentially increased to each of the first to fourth bank column decoders270ato270d.

The bank column decoder activated by the bank control logic230from among the first to fourth bank column decoders270ato270dmay activate a sense amplifier corresponding to the bank address BANK ADDR and the column address COL_ADDR through the I/O gating circuit290.

The I/O gating circuit290may include, in addition to circuits for gating input and output data, an input data mask logic, read data latches for storing data output from the first to fourth bank arrays300ato300d, and write drivers for writing data to the first to fourth bank arrays300ato300d.

Data read from a bank array from among the first to fourth bank arrays300ato300dmay be sensed by a sense amplifier corresponding to the bank array and may be stored in the read data latches.

The data stored in the read data latches may be provided to the memory controller100through the data I/O buffer295. The data set SDQ1to be written in one bank array from among the first to fourth bank arrays300ato300dmay be provided to the data I/O buffer295from the memory controller100. The data set SDQ1provided to the data I/O buffer295may be provided to the I/O gating circuit290.

The control logic circuit210may control an operation of the data chip200a. For example, the control logic circuit210may generate control signals for the data chip200ato perform a write operation or a read operation. The control logic circuit210may include a command decoder211configured to decode a command CMD received from the memory controller100and a mode register212configured to configure an operation mode of the data chip200a.

Each of the first and second parity chips200paand200pbofFIG.1may have substantially the same configuration as the data chip200a, for example the configuration illustrated inFIG.4. Each of the first and second parity chips200paand200pbmay input and output corresponding parity data.

FIG.5illustrates the first bank array300ain the data chip200aofFIG.4, according to embodiments.

Referring toFIG.5, the first bank array300amay include a plurality of word lines WL1to WL2m(where m is an integer greater than or equal to 2), a plurality of bit lines BTL1to BTL2n(where n is an integer greater than or equal to 2), and a plurality of memory cells MCs arranged at a crossing point between the plurality of word lines WL1to WL2mand the plurality of bit lines BTL1to BTL2n. Each memory cell MC may have a DRAM cell structure. The word lines WLs to which the memory cells MCs are connected may be defined as rows of the first bank array300a, and the bit lines BLs to which the memory cells MCs are connected may be defined as columns of the first bank array300a.

FIG.6illustrates a parity check matrix PCM stored in a memory in an ECC circuit ofFIG.4.

Referring toFIG.6, the parity check matrix PCM may include a first parity check sub-matrix HS11, a second parity check sub-matrix HS12, and a third parity check sub-matrix HS13.

The first parity check sub-matrix HS11may include partial sub-matrices HSM1.1to HSMk.2corresponding to the data chips200ato200kand two zero sub-matrices ZSMs corresponding to the first and second parity chips200paand200pb. Each of the partial sub-matrices HSM1.1to HSMk.2and each of the zero sub-matrices ZSMs may have a p×p (where p is a natural number greater than or equal to 2) structure. For example, p may be 16.

The partial sub-matrices HSM1.1to HSMk.2may include two partial sub-matrices calculated with symbols output from each memory chip. For example, referring toFIG.3, when generating a syndrome, the partial sub-matrix HSM1.1and the partial sub-matrix HSM1.2may be respectively calculated with the first symbol S11and the second symbol S12output from the data chip200a, and the partial sub-matrix HSMk.1and the partial sub-matrix HSMk.2may be respectively calculated with the first symbol Sk1and the second symbol Sk2output from the memory chip200k.

The second parity check sub-matrix HS12may include a unit sub-matrix ISM having a p×p structure and a zero sub-matrix ZSM having a p×p structure, the unit sub-matrix ISM and the zero sub-matrix ZSM being alternately repeated, and the third parity check sub-matrix HS13may include a zero sub-matrix ZSM and a unit sub-matrix ISM alternately repeated.

The parity check matrix PCM may include column partial matrices CPM1to CPMN. The column partial matrices CPM1to CPMN may correspond to the memory chips200, respectively. N may indicate the number of the memory chips. When generating an estimation syndrome, each of the column partial matrices CPM1to CPMk may be calculated with an error pattern detected based on the syndrome. For example, the column partial matrix CPM1may be calculated with the error pattern to generate the estimation syndrome, and the estimation syndrome and the syndrome may be compared with each other to determine whether or not an error is included in the data set SDQ1of the data chip200a.

FIG.7illustrates the zero sub-matrix ZSM ofFIG.6.

Referring toFIG.7, in the zero-sub matrix ZSM, all of p×p matrix elements may be zero, which may refer to a low level or ‘0’.

FIG.8illustrates the unit sub-matrix ISM ofFIG.6

Referring toFIG.8, in the unit sub-matrix ISM, only p matrix elements in a diagonal direction from among p×p matrix elements may be a high level ‘1,’ and the other matrix elements may be zero.

FIG.9is a diagram for describing a method of calculating an estimation syndrome eSDR.

Referring toFIG.9, the estimation syndrome eSDR may be calculated based on matrix multiplication between the column partial matrix CPMi and an error pattern EP. The error pattern EP may be determined by a syndrome calculated based on matrix multiplication between a parity check matrix and a codeword. The error pattern EP may include a first error e1generated in (or based on) a first symbol and a second error e2generated in (or based on) a second symbol.

The estimation syndrome eSDR may include a first estimation syndrome eSDRi.1, a second estimation syndrome eSDRi.2, and a third estimation syndrome eSDRi.3. Referring toFIGS.5and8, the first estimation syndrome eSDRi.1may be calculated by matrix multiplication between an overlapping portion between the first parity check sub-matrix HS11and the column partial matrix CPMi, and the error pattern EP. In detail, the first estimation syndrome eSDRi.1may be calculated by matrix multiplication between a partial sub-matrix HSMi.1and the first error e1and matrix multiplication between a partial sub-matrix HSMi.2and the second error e2. The second estimation syndrome eSDRi.2may be calculated by matrix multiplication between an overlapping portion between the second parity check sub-matrix HS12and the column partial matrix CPMi, and the error pattern EP. The third estimation syndrome eSDRi.3may be calculated by matrix multiplication between an overlapping portion between the third parity sub-matrix HS13and the column partial matrix CPMi, and the error pattern EP.

When two arbitrary columns of the partial sub-matrix HSMi.1are the same as each other, bits that are multiplied by the same two columns, from among bits included in the first error e1, may not be separately identified, and thus, all columns of the partial sub-matrix HSMi.1may have to be unique. That is, a determinant of the partial sub-matrix HSMi.1must not be 0.

Likewise, a determinant of the partial sub-matrix HSMi.2must not be 0.

FIG.10is a diagram illustrating a relationship between the partial sub-matrices HSMi.1and HSMi.2corresponding to one memory chip.

Referring toFIG.10, the partial sub-matrices HSMi.1and HSMi.2may correspond to a memory chip200i. The partial sub-matrix HSMi.1may be represented by matrix multiplication between a target sub-matrix HD and the partial sub-matrix HSMi.2. The target sub-matrix HD may have a p×p structure.

Referring toFIGS.9and10, the first estimation syndrome eSDRi.1may be calculated by Equation 1 below.
eSDRi.1=HD·e1+e2)·HSMi.2  [Equation 1]

When the first estimation syndrome eSDRi.1is 0, it is impossible to identify an error, and thus, a condition of (HD·e1+e2)·HSMi.2≠0 has to be satisfied. Thus, a condition of HD·e1+e2≠0 has to be satisfied.

In some embodiments, when an error of the data set DQ_BL3and the data set DQ_BL4is a target to be detected in a first symbol, and an error of the data set DQ_BL7and the data set DQ_BL8is a target to be detected in a second symbol, HD·e1+e2≠0 may be represented by Equation 2 below. A target data set in the first symbol to be detected to find the error may not be limited DQ_BL3and BQ_BL4. A target data set in the second symbol to be detected to find the error may not be limited DQ_BL7and BQ_BL8.

(HD⁢11HD⁢12HD⁢13HD⁢14HD⁢21HD⁢22HD⁢23HD⁢24HD⁢31HD⁢32HD⁢33HD⁢34HD⁢41HD⁢42HD⁢43HD⁢44)⁢(00EBL⁢3EBL⁢4)+(00EBL⁢7EBL⁢8)≠0[Equation⁢2]
To develop Equation 2, it is required to satisfy Equation 3

(HD⁢13HD⁢14HD⁢23HD⁢24)⁢(EBL⁢3EBL⁢4)≠0[Equation⁢3]

Thus, in order to detect the errors of the data sets DQ_BL3, DQ_BL4, DQ_BL7, and DQ_BL8, a condition that a determinant of

(HD⁢13HD⁢14HD⁢23HD⁢24),
a sub-matrix of the target sub-matrix HD, is not 0 may be derived.

That is, a value of the target sub-matrix HD may vary according to a location of the error to be detected. Referring toFIG.2, the memory controller100according to an embodiment may store the target sub-matrix HD having various values according to error locations in the memory180.

Because the partial sub-matrices HSMi.1and HSMi.2are determined according to the target sub-matrix HD, the parity check matrix having various values according to error locations may be stored in the memory180.

FIG.11is a diagram for describing a method of generating a syndrome SDR, according to an embodiment.

Referring toFIG.11, the syndrome SDR may be calculated based on matrix multiplication between a parity check matrix PCM and a codeword set SCW. The syndrome SDR may include a first syndrome SDR1, a second syndrome SDR2, and a third syndrome SDR3. The parity check matrix PCM may have a p×2N*p structure, wherein N may be the number of chips, for example the number of memory chips such as memory chips200. The codeword set SCW may include a plurality of symbols S11, S12, . . . , SN1, and SN2.

The first syndrome SDR1may be calculated based on matrix multiplication between the first parity check sub-matrix HS11and the codeword set SCW, the second syndrome SDR2may be calculated based on matrix multiplication between the second parity check sub-matrix HS12and the codeword set SCW, and the third syndrome SDR3may be calculated based on matrix multiplication between the third parity check sub-matrix HS13and the codeword set SCW.

FIG.12is a block diagram of the ECC decoder150according to an embodiment.

Referring toFIG.12, the ECC decoder150may include a syndrome generator151, an error pattern detector152, an estimation syndrome generator153, a comparator154, a counter155, and a data corrector156.

The syndrome generator151may generate the first to third syndromes SDR1to SDR3with respect to the codeword set SCW2by using the parity check matrix PCM. Referring toFIG.10, the codeword set SCW2may include a plurality of symbols S11, S12, . . . , SN1, and SN2.

The error pattern detector152may detect an error pattern EP based on the second syndrome SDR2and the third syndrome SDR3. In detail, the error pattern of a first symbol may be detected based on the second syndrome SDR2, and the error pattern of a second symbol may be detected based on the third syndrome SDR3.

The estimation syndrome generator153may generate first to third estimation syndromes eSDR1to eSDR3with respect to the error pattern EP by using the parity check matrix CPM including first to Nthcolumn partial matrices CPM1to CPMN. In detail, the estimation syndrome generator153may include a first estimation syndrome generator161to an Nthestimation syndrome generator16N. For example, the first estimation syndrome generator161may generate a first estimation syndrome eSDR1.1, a second estimation syndrome eSDR1.2, and a third estimation syndrome eSDR1.3based on matrix multiplication between the first column partial matrix CPM1and the error pattern EP. Likewise, the Nthestimation syndrome generator16N may generate a first estimation syndrome eSDRN.1, a second estimation syndrome eSDRN.2, and a third estimation syndrome eSDRN.3based on matrix multiplication between the Nthcolumn partial matrix CPMN and the error pattern EP.

The comparator154may compare the first to third syndromes SDR1to SDR3with first to third estimation syndromes eSDRi.1to eSDRi.3(i is a natural number greater than or equal to 1 and less than or equal to N). In detail, the comparator154may sequentially compare the estimation syndromes received from the first to Nthestimation syndrome generators161to16N with the syndromes.

When the first to third syndromes SDR1to SDR3and the first to third estimation syndromes eSDRi.1to eSDRi.3are respectively the same, the counter155may increase a count value. For example, when the first to third syndromes SDR1to SDR3are only the same as the first to third estimation syndromes eSDR1.1to eSDR1.3generated by the first estimation syndrome generator161, the count value may be 1.

The data corrector156may identify whether or not it is possible to correct an error, based on the count value. In detail, when the count value is 1, it may be identified that error correction is possible, and when the count value is greater than or equal to 2, it may be identified that error correction is impossible.

FIG.13is a block diagram of the syndrome generator151according to an embodiment.

Referring toFIG.13, the syndrome generator151may include a first syndrome generator171, a second syndrome generator172, and a third syndrome generator173.

The first syndrome generator171may generate the first syndrome SDR1with respect to the codeword set SCW2by using the first parity check sub-matrix HS11.

The second syndrome generator172may generate the second syndrome SDR2with respect to the codeword set SCW2by using the second parity check sub-matrix HS12.

The third syndrome generator173may generate the third syndrome SDR3with respect to the codeword set SCW2by using the third parity check sub-matrix HS13.

FIG.14is a flowchart of an ECC decoding method of the ECC circuit130according to an embodiment. The ECC decoding method may include a plurality of operations S1401to S1410.FIG.14is described below with reference toFIG.12.

In operation S1401, the error pattern detector152may detect an error pattern based on a syndrome. In detail, the syndrome generator151may generate the syndrome with respect to the codeword set SCW2received from the memory chip200by using the parity check matrix, and the error pattern detector152may detect the error pattern based on the generated syndrome.

In operation S1402, the data corrector156may initialize a count value and initialize an index i to 1. The index i may indicate an index of a memory chip.

In operation S1403, the estimation syndrome generator153may generate an estimation syndrome with respect to an ithchip. The estimation syndrome with respect to the ithchip may be generated by performing matrix multiplication between the error pattern and a 2i-1thpartial sub-matrix and a 2ithpartial sub-matrix from among a plurality of partial sub-matrices included in the parity check matrix.

In operation S1404, the comparator154may compare the syndrome with the estimation syndrome. When the syndrome and the estimation syndrome are the same as each other (Y at operation S1404), operation S1405may be performed, and when the syndrome and the estimation syndrome are not the same as each other (N at operation S1404), operation S1406may be performed.

In operation S1405, the counter155may increase the count value.

In operation S1406, when i is the same as the number of memory chips in the memory module MM (Y at operation S1406), operation S1408may be performed, and when i is different from the number of memory chips in the memory module MM (N at operation S1406), i may increase by 1 in operation S1407, and an estimation syndrome with respect to a memory chip of a next order may be generated in operation S1403.

In operation S1408, the data corrector156may determine whether or not the count value is 1. When the count value is 1 (Y at operation S1408), the data corrector156may identify a memory chip with respect to which the corresponding count value is increased and may correct symbols output from the identified memory chip in operation S1409. When the count value is not 1 (N at operation S1408), the data corrector156may identify an error as uncorrectable in operation S1410.

FIG.15is a diagram of a memory module500, which may be applied to a memory system, according to embodiments.

Referring toFIG.15, the memory module500may include a buffer chip590, which may be for example a registering clock driver (RCD) arranged or mounted on a circuit substrate501, a plurality of semiconductor memory devices601ato601e,602ato602e,603ato603d, and604ato604d, module resistors560and570, a serial presence detection (SPD) chip595, and a power management integrated circuit585.

The buffer chip590may control the semiconductor memory devices601ato601e,602ato602e,603ato603d, and604ato604dand the power management integrated circuit (PMIC)585according to control by the memory controller100. For example, the buffer chip590may receive an address ADDR, a command CMD, a main data set SDQ, and metadata MDT from the memory controller100.

The SPD chip595may include a programmable read-only memory device, for example an electrically erasable programmable read-only memory (EEPROM). The SPD chip595may include initial information or device information (DI) of the memory module500. For example, the SPD chip595may include the initial information or the DI of the memory module500, such as a module form, a module configuration, a storage capacity, a module type, an execution environment, etc.

When the memory system including the memory module500is booted, the memory controller100may read the DI from the SPD chip595and recognize the memory module500based on the read DI. The memory controller100may control the memory module500based on the DI from the SPD chip595. For example, the memory controller100may identify types of semiconductor devices included in the memory module500according to the DI from the SPD chip595.

Here, the circuit substrate501is a printed circuit board and may extend in a second direction D2vertical to a first direction D1between a first edge portion503and a second edge portion505in the first direction D1. The buffer chip590may be arranged in a central portion of the circuit substrate501, and the semiconductor memory devices601ato601e,602ato602e,603ato603d, and604ato604dmay be arranged at a plurality of rows between the buffer chip590and the first edge portion503and between the buffer chip590and the second edge portion505.

Here, the semiconductor memory devices601ato601eand602ato602emay be arranged at a plurality of rows between the buffer chip590and the first edge portion503, and the semiconductor memory devices603ato603dand604ato604dmay be arranged at a plurality of rows between the buffer chip590and the second edge portion505. The semiconductor memory devices601ato601d,602ato602d,603ato603d, and604ato604dmay be referred to as data chips, and the semiconductor memory devices601eand602emay be referred to as a first parity chip and a second parity chip.

The buffer chip590may generate first parity data and second parity data based on the main data set SDQ and the metadata MDT, may store the main data set SDQ and the metadata MDT in the data chips, may store first parity data in the first parity chip, and may store second parity data in the second parity chip.

The buffer chip590may provide a command/address signal to the semiconductor memory devices601ato601ethrough a command/address transmission line561and provide a command/address signal to the semiconductor memory devices602ato602ethrough a command/address transmission line563. Also, the buffer chip590may provide a command/address signal to the semiconductor memory devices603ato603dthrough a command/address transmission line571and provide a command/address signal to the semiconductor memory devices604ato604dthrough a command/address transmission line573.

The command/address transmission lines561and563may be commonly connected to the module resistor560arranged to be adjacent to the first edge portion503, and the command/address transmission lines571and573may be commonly connected to the module resistor570arranged to be adjacent to the second edge portion505. Each of the module resistors560and570may include an end resistance Rtt/2 connected to an end voltage Vtt.

Also, each of the semiconductor memory devices601ato601e,602ato602e,603ato603d, and604ato604dmay be a DRAM device.

The SPD chip595may be arranged to be adjacent to the buffer chip590, and the PMIC585may be connected between the semiconductor memory device603dand the second edge portion505. The PMIC585may generate a power voltage VDD based on an input voltage VIN and may provide the power voltage VDD to the semiconductor memory devices601ato601e,602ato602e,603ato603d, and604ato604d.

FIG.16is a diagram of a memory system800having a quad-rank memory module, according to embodiments.

Referring toFIG.16, the memory system800may include a memory controller810and one or more memory modules, that is, a first memory module820and a second memory module830.

The memory controller810may control the first and second memory modules820and830to execute a command applied from a processor or a host. The memory controller810may be realized in the processor or the host or may be realized as an application processor or a system on chip (SoC). Source termination may be realized through a resistor Rtt in a bus80of the memory controller810for signal integrity. The memory controller810may include an ECC circuit815. The ECC circuit815may correspond to the ECC circuit130ofFIG.1.

Thus, the ECC circuit815may include an ECC encoder and an ECC decoder, and the ECC decoder may generate a syndrome by performing, by using a parity check matrix, ECC decoding on a codeword read from the one or more memory modules, that is, the first and second memory modules820and830, may generate an estimation syndrome by using an error pattern detected based on the syndrome and a plurality of partial sub-matrices included in the parity check matrix, and may correct an error by comparing the syndrome with the estimation syndrome.

The first memory module820and the second memory module830may be connected to the memory controller810through a bus840. Each of the first memory module820and the second memory module830may correspond to the memory module MM ofFIG.1. The first memory module820may include one or more memory ranks RK1and RK2, and the second memory module830may include one or more memory ranks RK3and RK4.

The first memory module820and the second memory module830may include a plurality of data chips, a first parity chip, and a second parity chip.

FIG.17is a block diagram of an example in which a memory module is applied to a mobile system900, according to an embodiment.

Referring toFIG.17, the mobile system900may include an application processor (AP)910, a connectivity module920, a user interface930, a nonvolatile memory (NVM) device940, a memory module (MM)950, and a power supply960. The application processor910may include a memory controller (MCT)911. The memory controller911may include the ECC circuit130ofFIG.1.

The application processor910may execute applications providing an Internet browser, a game, a video, etc. The connectivity module920may perform wireless communication or wired communication with an external device.

The memory module950may store data processed by the application processor910or may operate as a working memory. The memory module950may include a plurality of semiconductor memory devices (MD)951to95qand a control device (RCD961. In embodiments, the memory module950may correspond to memory module MM described above.

The plurality of semiconductor memory devices951to95qmay include a plurality of data chips, a first parity chip, and a second parity chip. Thus, the memory controller911may generate a syndrome by performing, by using a parity check matrix, ECC decoding on a codeword read from the memory module950x, generate an estimation syndrome by using an error pattern detected based on the syndrome and a plurality of partial sub-matrices included in the parity check matrix, and correct an error by comparing the syndrome with the estimation syndrome.

The NVM device940may store a boot image for booting the mobile system900. The user interface930may include one or more input devices, such as a keypad, a touch screen, etc., and/or one or more output devices, such as a speaker, a display, etc. The power supply960may supply an operating voltage of the mobile system900.

The mobile system900or the components of the mobile system900may be mounted in various forms of packages.

As described above, embodiments are illustrated in the drawings and the specification. The embodiments herein are described by using specific terms. However, the terms are not used limit the meaning or the scope described in the claims. Therefore, it would be understood by one of ordinary skill in the art that various modifications and equivalent embodiments are possible from the described embodiments. Accordingly, the true technical scope of protection shall be defined by the following claims.