Patent ID: 12224729

The drawing figures do not limit the present invention to the specific embodiments disclosed and described herein. The drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The following detailed description of the invention references the accompanying drawings that illustrate specific embodiments in which the invention can be practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments can be utilized and changes can be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense. The scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

In this description, references to “one embodiment”, “an embodiment”, or “embodiments” mean that the feature or features being referred to are included in at least one embodiment of the technology. Separate references to “one embodiment”, “an embodiment”, or “embodiments” in this description do not necessarily refer to the same embodiment and are also not mutually exclusive unless so stated and/or except as will be readily apparent to those skilled in the art from the description. For example, a feature, structure, act, etc. described in one embodiment may also be included in other embodiments, but is not necessarily included. Thus, the present technology can include a variety of combinations and/or integrations of the embodiments described herein.

Turning toFIG.1, an exemplary digital signal processing (DSP) system10which may implement aspects of the present invention is depicted. The DSP system10is configured to test a radar device12. The radar device12may be any device configured to generate radio signals to measure and/or detect an aspect of its surroundings. While under test, the radar device12generates a radar signal. The DSP system10is configured to receive and modify the radar signal to simulate an environment to test the radar device12and then transmit the modified radar signal back to the radar device12.

The DSP system10may comprise an analog-to-digital converter (ADC)14, a field-programmable gate array (FPGA)16, and a digital-to-analog converter (DAC)17. The ADC14is provided for sampling the radar signal of the radar device12and converting the samples into digital numbers, or digital outputs, representative of the samples for further processing by the FPGA16. The ADC14samples the radar signals at a high frequency for higher resolution and accuracy. For example, in one embodiment, the ADC14may sample the radar signal at a rate of 1 billion samples per second, or 1 Giga samples per second (GS/s), with each sample including 16-bit digital numbers. Thus, the ADC14outputs a high-speed serial data stream.

The FPGA16is provided for various computing functions, including processing the radar signal from the radar device12. The FPGA16is configured to receive the high-speed serial data stream and process the data representative of the radar signal for various DSP system10functions. The FPGA16includes a first transceiver circuit18, a memory element19, a Farrow-structured fractional delay (FD) filter20, and a second transceiver circuit21. The FPGA16may have a clock rate that is a fraction of the sample rate of the ADC14. For example, in one embodiment, the FPGA16may have a clock rate of only 250 MHZ, which is a fourth of the sample rate of the ADC14at 1 GS/s. Applicants have encountered problems implementing some DSP functions such as a finite impulse response (FIR) filter due to the difference between the sample rate of the ADC14and the clock rate of the FPGA16. In some embodiments, the functions and circuits of the FPGA16may be implemented on a different type of processing element, such as a microcontroller, microprocessor, application specific integrated circuits, central processing units, or the like.

The first transceiver circuit18is provided for converting the serial data stream from the ADC14into time-ordered, parallel data streams. For example, as shown inFIG.2, the first transceiver circuit18may be configured to convert serial data stream22into multiple time-ordered, parallel data streams24,26,28,30. The samples of the radar signal from the radar device12may be represented by S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, and S12. The order of the samples is the order in which they were sampled in time, or a time-order. S1is the first sample of the set, and S12is the last. Thus, the parallel data streams24,26,28,30maintain this time-order wherein data stream24conveys S1, data stream26conveys S2, data stream28conveys S3, and data stream30conveys S4. This continues for the next set of samples where data stream24conveys S5, data stream26conveys S6, data stream28conveys S7, data stream30conveys S8, etc.FIG.2depicts the serial data stream22being converted into four parallel data streams24,26,28,30; however, the serial data stream22may be converted into any number of parallel data streams without departing from the scope of the present invention.

In one embodiment, the first transceiver circuit18may convert the serial data stream into parallel streams by first converting the serial data stream22passing 16-bit digital samples into two very high-speed serial data streams operating at 8 billion bits per second, or 8 giga bits per second (Gbps). The first transceiver circuit18may be configured to convert the two very high-speed serial data streams into two streams of 32-bit data words operating at 250 MHZ. Finally, the first transceiver circuit18may concatenate the 32-bit data word streams into a single 64-bit data word stream, wherein each 64-bit data word contains four consecutive samples, such as S1, S2, S3, and S4, each being 16-bit samples. The first transceiver circuit18may output the 64-bit data words at the clock rate of the FPGA16. The FPGA16may be configured to treat the 64-bit data word stream as parallel data streams24,26,28,30. The first transceiver circuit18may include any number of stages and/or transceivers without departing from the scope of the present invention. Further, the first transceiver circuit18may be integral with the FPGA16, external to the FPGA16, or a combination of both.

The memory element19is configured to store digital values from the transceiver circuit18which can be read by the FD filter20after a configurable time delay to simulate distance to target or modified to simulate a moving target. The memory element19may be used to provide static delays which simulate a target that is not moving relative to the radar device12. Additionally or alternatively, the memory element19may be used to provide dynamic delays, which simulate a target moving relative to the radar device12. The memory element19may be integral with the FPGA16, external to the FPGA16, or a combination of both. For example, the memory element19may comprise one or more memory components, including internal or external memory components, such as read-only memory (ROM), programmable ROM, erasable programmable ROM, random-access memory (RAM) such as static RAM (SRAM) or dynamic RAM (DRAM), cache memory, hard disks, floppy disks, optical disks, flash memory, thumb drives, universal serial bus (USB) drives, or the like, or combinations thereof.

The FD filter20is provided for filtering the parallel data streams24,26,28,30, including performing Lagrange interpolation to refine delay resolution in the simulation and to increase the fidelity of the data of the radar signal from the radar device12. The FD filter20may include and/or be represented by one or more Z−1delay elements, one or more FD gain elements, one or more FD adder elements, and one or more finite impulse response (FIR) filters.

The Z−1delay elements are provided for delaying one or more of the parallel data streams24,26,28,30so that all of the most recent and preceding samples required to produce all corresponding data stream outputs are available. The Z−1delay elements are preferably implemented as memory components internal to the FPGA16. However, the Z−1delay elements may comprise one or more other memory elements without departing from the scope of the present invention, including internal or external memory components, such as read-only memory (ROM), programmable ROM, erasable programmable ROM, random-access memory (RAM) such as static RAM (SRAM) or dynamic RAM (DRAM), cache memory, hard disks, floppy disks, optical disks, flash memory, thumb drives, universal serial bus (USB) drives, or the like, or combinations thereof. The Z−1delay elements may be configured to delay one of the data streams24,26,28,30for a clock cycle of the FPGA16. In other words, the Z−1delay elements may be configured to receive one of the digital samples from one of the data streams24,26,28,30, hold it for a clock cycle of the FPGA16, and then output the digital sample during the next clock cycle of the FPGA16. The number of Z−1delay elements may be one less than the number of parallel data streams24,26,28,30.

FIG.3depicts a general topology of an Nth-order FD filter20A. FD filter20A includes a number (N) of FD gain elements36A, N FD adder elements38A, and N FIR filters40A.

The FD gain elements36A provide a value that, at least in part, represents a fractional delay. The fractional delay may be a delay that is a fraction of the clock cycle and/or the sample cycle corresponding to the sample rate. The FD gain elements36A multiply the outputs of the FIR filters40A by the value before the outputs are passed to the FD adder circuits38A. The fractional delay may be predetermined and or modifiable. The FD gain elements36A may be configured to receive an output of one of the FIR filters40A, multiply the output by a value representative of the fractional delay, and then send the output to one of the FD adder circuits38A.

The FD adder circuits38A are configured to add an output of one of the FIR filters40A with outputs of other FIR filters40A. For example, one of the FD adder circuits38A may receive an output from one of the FIR filters40A and add it with an output from one of the FD gain elements36A, which is product of the FD gain and the output of one of the other FIR filters40A. The output of the FD adder circuits38A may be sent to one of the FD gain elements36A.

The FIR filters40A are provided for processing the digital samples and weighting them so that outputs of the FIR filters40A are weighted sums of the most recent digital samples. The number of digital samples to be included in the weighting is determined by the order of the FIR filters40A.FIG.4depicts the general topology of an N-th order FIR filter40A having a plurality of FIR delay elements42A, a plurality of multiplication elements44A, and a plurality of FIR adder elements46A.

The FIR delay elements42A are similar to the Z−1delay elements in that they temporarily store digital samples so that the outputs of the FIR filters40A are based on multiple time-ordered digital samples. The FIR delay elements42A may be configured to receive one of the digital samples, hold it for a clock cycle of the FPGA16, and output the digital sample for the next clock cycle. The FIR delay elements42A are positioned between the multiplication elements44A.

The multiplication elements44A multiply the digital samples by coefficients, A0, A1, A2, A3, A4, A5, A6, A7. . . . AN-1. The coefficients A0, A1, A2, A3, A4, A5, A6, A7. . . . AN-1are based on the order (N) of the FIR filters40A. The multiplication circuits44A are configured to receive a digital sample and multiply the digital sample by their corresponding coefficient A0, A1, A2, A3, A4, A5, A6, A7. . . . AN-1. The outputs of the multiplication elements44A are the product of the digital sample and the corresponding coefficient A0, A1, A2, A3, A4, A5, A6, A7. . . . AN-1. The outputs of the multiplication elements44A are sent to the FIR adder elements46A.

The FIR adder elements46A are provided for adding the outputs of the multiplication elements44A. The FIR adder elements46A enable a current digital sample to be weighted with any preceding digital samples to produce the output of the FIR filter40A. The FIR adder elements46A may be similar to the FD adder elements38A. For example, the FIR adder elements46A may utilize the same components as the FD adder elements38A and/or utilize completely different components. Additionally, the FIR adder elements46A may separately comprise the same or similar components as the FD adder elements38A.

Applicants have discovered that the general topologies of the FD filter20A having the FIR filters40A depicted inFIGS.3and4would not function with parallel data streams24,26,28,30because one of the FIR filters40A would receive, for example, S1, S5, and S9, which would result in an inappropriately weighted output of the FIR filter40A. Applicants have found that the FIR filter40A can be reconfigured as shown in the topology of FIR filter40B shown inFIG.5. FIR filter40B also includes one or more FIR delay elements42B, one or more multiplication elements44B, and one or more FIR adder elements46B.

FIG.5shows an intermediate representation of the FIR filter40A ofFIG.3split into four parallel sub-components24B,26B,28B,30B. The multiplication elements44A of FIR filter40A are split among the four parallel sub-components24B,26B,28B,30B so that the order of each of the four parallel sub-components24B,26B,28B,30B is N/4. The reference numerals of the sub-components24B,26B,28B,30B correspond to the parallel data streams24,26,28,30. However, the output of FIR filter40B is a serial data stream passing outputs at a rate equal to the sample rate, which is higher than the clock rate of the FPGA16. The present invention modifies FIR filter40B to receive parallel data streams24,26,28,30at the clock rate of the FPGA16and output four parallel data streams at the clock rate of the FPGA16, wherein the data samples in the output data streams have been filtered in an identical manner as the FIR filter40A ofFIG.4.

FIGS.6A and6Bdepict an N-th order FIR filter40constructed in accordance with an embodiment of the present invention.FIG.6Ashows that each block45(BN) inFIG.6Brepresents a FIR delay element42, a multiplication element44, and a FIR adder element46, for n>3. The FIR filter40ofFIG.6Bis similar to the FIR filter40A ofFIG.4in that it is also provided for processing the digital samples and weighting them so that the output of the FIR filter40is weighted sums of the most recent digital samples, except that FIR filter40has a plurality of inputs48,50,52,54and a plurality of sub-components56,58,60,62. Given the same input data samples, the output samples of FIR filter40ofFIG.6Bwould be identical to the output samples of FIR filter40A ofFIG.4, except that the input and output data samples to and from the FIR filter40A ofFIG.4are provided in a single data stream of samples at the ADC14/DAC17sample rate while the input and output data samples to and from the FIR filter40ofFIG.6Bare provided in four parallel data streams at the FPGA clock rate which is ¼ of the ADC14/DAC17sample rate.

As depicted inFIG.4, each output sample from a FIR filter40A is a weighted sum of all N previous samples with the weighting provided by the coefficients A0 through AN−1 for a Nth order FIR filter40A.FIG.6Bshows how, in accordance with the present invention, the N coefficients are applied to each of the four input data streams and how each of the four output data streams receives data samples weighted by data received from all four input data streams. This is accomplished by applying the subdivided FIR filter40B ofFIG.5to all four input data streams. The three FIR delay elements42depicted inFIG.6Bare of the FPGA clock rate which is ¼ of the ADC14/DAC17sample rate. Applying this delay is equivalent to four Z−1delays at the ADC14/DAC17sample rate as depicted inFIG.5. Applying this delay is necessary where shown on data streams D1_In54, D2_In52and D3_In50in order to get all four of the most recent and three preceding samples required to produce all four data stream outputs. For data stream D4_In48this is not necessary because the most recent and three preceding samples are all contained within the most recent block of four samples across data streams D1_In54, D2_In52, D3_In50and D4_In48.

Similar to FIR filter40A, FIR filter40includes a plurality of FIR delay elements42, a plurality of multiplication elements44, and a plurality of FIR adder circuits46. Similar to FIR delay elements42A, FIR delay elements42are configured to produce delayed data streams64,66,68. FIR delay elements42are configured to receive a digital sample from one of the data streams26,28,30, hold the digital sample for a clock cycle of the FPGA16, and then output the digital sample, thereby producing delayed data streams64,66,68. The number of FIR delay elements42is one less than the number of inputs48,50,52,54, or data streams24,26,28,30. However, any number of FIR delay elements42may be used without departing from the scope of the present invention.

The multiplication elements44are similar to multiplication elements44A and are provided for multiplying the digital samples by coefficients, A0, A1, A2, A3, A4, A5, A6, A7. . . AN-1. The multiplication elements44are configured so that the sub-components56,58,60,62multiply their corresponding data streams24,26,28,30by coefficients A0, A4. . . AN-4. Further, any preceding digital samples in the data streams24,26,28,30are multiplied by coefficients A1, A5. . . . AN-3; A2, A6. . . . AN-2; or A3, A7. . . AN-1, depending on by how many sample cycles the digital samples preceded the sample in the corresponding data stream24,26,28,30. For example, in sub-component62, S4of data stream30would be multiplied by A0, A4. . . . AN-4; S3which precedes S4and is of data stream28would be multiplied by A1, A5. . . . AN-3; S2which precedes S4and is of data stream26would be multiplied by A2, A6. . . . AN-2; and S1which precedes S4and is of data stream24would be multiplied by A3, A7. . . . AN-.

The plurality of FIR adder elements46are similar to FIR adder elements46A and are provided for summing the outputs of the multiplication elements44thereby resulting in the outputs of the sub-components56,58,60,62.

The plurality of inputs48,50,52,54are provided for receiving the parallel data streams24,26,28,30. Input48receives data stream24, input50receives data stream26, input52receives data stream28, and input54receives data stream30. WhileFIG.6Bdepicts the FIR filter40having four inputs48,50,52,54, the FIR filter40may have any number without departing from the scope of the present invention. The inputs48,50,52,54are connected to and pass the data streams24,26,28,30to corresponding sub-components56,58,60,62. Specifically, sub-component56is connected to input48and corresponds to data stream24, sub-component58is connected to input50and corresponds to data stream26, sub-component60is connected to input52and corresponds to data stream28, and sub-component62is connected to input54and corresponds to data stream30.

The sub-components56,58,60,62are provided for parallel filtration of the data streams24,26,28,30so that the volume of data flowing into the inputs48,50,52,54each clock cycle is equal to the volume of data output by the sub-components56,58,60,62every clock cycle. Each sub-component56,58,60,62is configured to receive its corresponding data stream24,26,28,30from one of the inputs48,50,52,54. Further, each sub-component56,58,60,62is configured to receive any data stream24,26,28,30that precedes its corresponding data stream24,26,28,30. The sub-components56,58,60,62are also configured to receive delayed data streams64,66,68that are subsequent to that sub-component's corresponding data stream26,28,30.

For example, sub-component58is configured to receive data stream26from input50. Because data stream24contains digital samples that precede the digital samples in data stream26in time, sub-component58is configured to receive data stream24by being connected to input48. Further, because data streams28,30are subsequent to data stream26, or contain digital samples that are subsequent in time to the digital samples in data stream26, sub-component58is configured to receive their corresponding delayed data streams66,68.

The FIR filter40may have any number of inputs and FIR sub-components without departing from the scope of the present invention. Additionally, the FIR filter40may be of any order. For example,FIG.7depicts a 4thorder FIR filter40C constructed in accordance with another embodiment of the present invention. The FIR filter40C may comprise substantially similar components as FIR filter40; thus, the components of FIR filter40C that correspond to similar components in FIR filter40have a ‘C’ appended to their reference numerals.

Similar to FIR filter40, 4thorder FIR filter40C includes FIR delay elements42C, multiplication elements44C, FIR adder elements46C, inputs48C,50C,52C,54C, FIR sub-components56C,58C,60C,62C, and delayed data streams64C,66C,68C. The difference between FIR filter40C and FIR filter40is that FIR filter40C is 4thorder. Otherwise it is substantially the same as FIR filter40. Because FIR filter40C is 4thorder, there are only four coefficients A0, A1, A2, A3associated with multiplication elements44C.

FIG.8depicts the topology of a 4thorder, Farrow-structured FD filter20C constructed in accordance with an embodiment of the present invention. The FD filter20C comprises a plurality of 4thorder FIR filters40C ofFIG.7. The FD filter20C may comprise substantially similar components as FD filter20; thus, the components of FD filter20C that correspond to similar components in FD filter20have a ‘C’ appended to their reference numerals.

The FD filter20C includes a plurality of Z−1delay elements34C a plurality of FD gain elements36C, a plurality of FD adder elements38C, a plurality of multiplication elements44C, and a plurality of FIR adder circuits46C. The Z−1delay elements34C are substantially the same as the Z−1delay elements.

The FD gain elements36C are provided for representing a fractional delay before outputs of the FIR filters40C are passed to the FD adder elements38C. The fractional delay may be predetermined and or modifiable. The FD gain elements36C may be configured to receive an output of the FIR filters40C, multiply the output by the value representing the fractional delay, and then send the output to the FD adder elements38C.

The FD adder elements38C are configured to add an output of one of the FIR filters40C with outputs of other FIR filters40C. For example, one of the FD adder elements38C may receive an output from one of the FIR filters40C and add it with an output from one of the FD gain elements36C, which is an output of one of the other FIR filters40C. The output of the FD adder elements38C may be sent to one of the FD gain elements36C.

The multiplication elements44C and FIR adder circuits46are provided for processing the digital samples and weighting them to provide weighted sums of the most recent digital samples. The multiplication elements44C and FIR adder circuits46essentially form sixteen (16) FIR filters. Instead of the FIR filters formed by the multiplication elements44C and FIR adder circuits46having their own FIR delay elements42C, the FD filter20C includes Z−1delay elements34C which are configured to produce delayed data streams64C,66C,68C. Z−1delay elements34C are configured to receive a digital sample in one of the data streams26,28,30, hold the digital sample for a clock cycle of the FPGA16, and then output the digital sample, thereby producing delayed data streams64C,66C,68C. As depicted inFIG.8, the number of Z−1delay elements34C is one less than the number of inputs48C,50C,52C,54C or the number of data streams24,26,28,30. However, any number of Z−1delay elements34C may be used without departing from the scope of the present invention.

The multiplication elements44C are similar to multiplication elements44and are provided for multiplying the digital samples by predetermined coefficients, except that the predetermined coefficients are C0(z), C1(z), C2(z), C3(z), which are defined by equations 1-4 below. The coefficients for Cn(z) can be found using equation 5 with qnbeing the values of an inverse Vandermonde matrix. As shown in equation 1, C0is equal to 1 no matter the value of z; thus, the FIR filter40C having the C0coefficient is not depicted in the topology ofFIG.8. The multiplication elements44C are configured so that the sub-components56C,58C,60C,62C multiply their corresponding data streams24,26,28,30by coefficients C0(0), C1(0), C2(0), C3(0). Further, any preceding digital samples in the data streams24,26,28,30are multiplied by coefficients C0(1), C1(1), C2(1), C3(1); C0(2), C1(2), C2(2), C3(2); C0(3), C1(3), C2(3), C3(3), depending on how many sample cycles the digital samples preceded the sample in the corresponding data stream24,26,28,30. For example, in sub-component62C, S4of data stream30would be multiplied by C0(0), C1(0), C2(0), C3(0). S3precedes S4and is of data stream28, so it would be multiplied by C0(1), C1(1), C2(1), C3(1). S2precedes S4and is of data stream26, so it would be multiplied by C0(2), C1(2), C2(2), C3(2). S1which precedes S4and is of data stream24, so it would be multiplied by C0(3), C1(3), C2(3), C3(3).

C0(z)=1(1)C1(z)=-1.8⁢3⁢3+3⁢z-1-1.5⁢z-2+0.3⁢3⁢3⁢3⁢z-3(2)C2(z)=1-2.5⁢z-1+2⁢z-2-0.5⁢z-3(3)C3(z)=-0.1⁢6⁢6⁢7+0.5⁢z-1-0.5⁢z-2+0.1⁢6⁢6⁢7⁢z-3(4)Cn(z)=∑k=0N⁢qn(k)⁢z-k⁢for⁢n=1,2,…,N(5)

Similar to the plurality of FIR adder elements46, FIR adder elements46C are provided for summing the outputs of the multiplication elements44C thereby resulting in the outputs of the sub-components56C,58C,60C,62C.

Instead of each FIR filter having its own plurality of inputs48,50,52,54, FD filter20C includes a plurality of inputs48C,50C,52C,54C shared among the FIR filters. The inputs48C,50C,52C,54C are provided for receiving the parallel data streams24,26,28,30. Input48C receives data stream24, input50C receives data stream26, input52C receives data stream28, and input54C receives data stream30. WhileFIG.8depicts four inputs48C,50C,52C,54C, any number of inputs may be implemented without departing from the scope of the present invention, i.e., the present invention could be applied to any number of input data streams and any order of Farrow-structured FD filter.

Turning back toFIG.1, the second transceiver circuit21converts the parallel data streams from the FD filter20into a serial data stream. For example, as shown inFIG.9, the second transceiver circuit21may be configured to convert the multiple time-ordered, parallel data streams70,72,74,76received from the outputs (D1_Out, D2_Out, D3_Out, D4_Out) of the FD filter20C into the serial data stream78. The filtered samples from the FD filter20C may be represented by S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, and S12. The order of the samples is the order in which they were sampled in time, or a time-order. S1is the first sample of the set, and S12is the last. The serial data stream78is then passed to the DAC17. The second transceiver circuit21may be integral with the FPGA16, external to the FPGA16, or a combination of both. The DAC17is connected to the FPGA16and is configured to convert the digital serial data stream78to analog samples for processing by the radar device12.

In use, the radar device12emits a radar signal that the ADC14samples at a sample rate. The ADC14converts the analog samples to digital samples at the sample rate and outputs the digital samples creating a serial data stream22. The transceiver18of the FPGA16receives the serial data stream22and converts the serial data stream22into a plurality of parallel data streams24,26,28,30. The memory element19of the FPGA16receives the parallel data streams24,26,28,30. The data is written to the memory element19and read from memory element19after a delay configured to simulate the distance to a target, including a moving or stationary target.

The FD filter20receives the parallel data streams24,26,28,30from the memory element19and filters them via its plurality of FIR filters, FD adder elements, and FD gain elements. The FIR filters receive their corresponding parallel data streams24,26,28,30and any preceding data streams24,26,28,30via inputs48,50,52,54. The FIR filters also receive delayed data streams64,66,68via the Z−1delay elements for any data streams24,26,28,30subsequent to their corresponding data streams24,26,28,30. The FIR filters are configured to weight the digital samples in the data streams24,26,28,30so that the outputs of the FIR filters are weighted sums of recent digital samples. The FIR filters weight the digital samples via their multiplication elements and FIR adder elements.

The FD adder elements add the outputs of the FIR filters with outputs of immediately preceding FIR filters multiplied by the FD gain elements. The outputs of the FD adder elements are then multiplied by the value representing the fractional delay via the FD gain elements before finally being added with a current digital sample from the corresponding data streams24,26,28,30via the FD adder elements. The outputs of the FD adder elements are the outputs of the FD filter20.

The flow chart ofFIG.10depicts the steps of an exemplary method100of filtering time-ordered, parallel data streams24,26,28,30converted from the serial data stream22representative of samples of the radar signal from the radar device12. In some alternative implementations, the functions noted in the various blocks may occur out of the order depicted inFIG.10. For example, two blocks shown in succession inFIG.10may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order depending upon the functionality involved. In addition, some steps may be optional.

The method100is described below, for ease of reference, as being executed by exemplary devices and components introduced with the embodiments illustrated inFIGS.1-2and6-9. For example, the steps of the method100may be performed by the DSP system10, the ADC14, the FPGA16, and the DAC17through the utilization of processors, transceivers, hardware, software, firmware, or combinations thereof. However, a person having ordinary skill will appreciate that responsibility for all or some of such actions may be distributed differently among such devices or other computing devices without departing from the spirit of the present invention. One or more computer-readable medium(s) may also be provided. The computer-readable medium(s) may include one or more executable programs stored thereon, wherein the program(s) instruct one or more processing elements to perform all or certain of the steps outlined herein. The program(s) stored on the computer-readable medium(s) may instruct the processing element(s) to perform additional, fewer, or alternative actions, including those discussed elsewhere herein.

Referring to step101, the serial data stream22is converted into a plurality of time-ordered, parallel data streams24,26,28,30. The serial data stream22may comprise a plurality of digital values that represent samples of a radar signal. The radar signal may be sampled at a sample rate, and the parallel data streams24,26,28,30may operate at a clock rate of the FPGA. The clock rate may be a fraction of the sample rate. The digital values of the serial data stream22may comprise a number of bits, such as 16 bits, and the parallel data streams24,26,28,30may each include a series of data words having a number of bits, such as 16-bit data words. The FD filter may output a same number of bits as the number of bits received from the serial data stream22every clock cycle of the FPGA. As discussed above, in some embodiments the sample rate may be 1 GS/s and the clock rate may be 250 MHz.

Referring to step102, each of the parallel data streams24,26,28,30may be filtered via a Farrow-structured FD filter. The filter may comprise a plurality of FIR filters and FD gain elements. Each of the FIR filters may receive the parallel data streams24,26,28,30. The FIR filters may be configured to receive the corresponding data stream24,26,28,30and filter the corresponding data stream24,26,28,30. As discussed above and depicted inFIG.2, the parallel data streams24,26,28,30have a time-order wherein at each clock cycle the data streams24,26,28,30output digital samples in an order that the samples were taken and converted by the ADC. Values in the data streams24,26,28,30may therefore precede and/or be subsequent to other data streams24,26,28,30. The filtering, via the FIR filters, may comprise receiving a current value from one of the data streams24,26,28,30; receiving a number of values preceding the current value according to the time order; and producing a weighted version of the current value based on the preceding values. The weight given the preceding values for each FIR filter may be predetermined via equations (1)-(4), as discussed above. This step102may also include passing each output of the FIR filters through an FD gain element configured to multiply the output with a value representative of a fractional delay resulting in a delayed output. The delayed output may be added to an output of one of the FIR filters.

Referring to step103, values from one or more of the parallel data streams24,26,28,30may be temporarily stored so that the stored values can be used to filter one or more of the parallel data streams24,26,28,30having values that are, according to the time order, subsequent to the stored values. This step103may include sending the delayed data stream64,66,68to the FIR filters corresponding to any parallel data stream24,26,28,30that precedes the one or more data stream that was delayed26,28,30. This enables the FIR filters to weight current digital samples with preceding samples.

The method100may include additional, less, or alternate steps and/or device(s), including those discussed elsewhere herein.

Although the invention has been described with reference to the embodiments illustrated in the attached drawing figures, it is noted that equivalents may be employed and substitutions made herein without departing from the scope of the invention as recited in the claims.

Having thus described various embodiments of the invention, what is claimed as new and desired to be protected by Letters Patent includes the following: