Patent ID: 12249576

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIGS.1and2are cross-sectional views illustrating intermediate stages of a process for forming a semiconductor device structure100according to a comparative example. In this comparative example, a semiconductor substrate101is provided, a first dielectric layer103and conductive plugs105a,105bsurrounding by the first dielectric layer103are disposed over the semiconductor substrate101, and a second dielectric layer107is disposed over the first dielectric layer103.

Moreover, the structure ofFIG.1has a pattern-loose region A (i.e., array region) and a pattern-dense region B (i.e., peripheral circuit region). An opening110apenetrating through the first dielectric layer103and the second dielectric layer107is located in the pattern-loose region A, and openings110band110cpenetrating through the second dielectric layer107are located in the pattern-dense region B. In order to clarify the disclosure, the dotted line in the middle ofFIG.1is used to indicate the boundary of the pattern-loose region A and the pattern-dense region B.

During the process for forming the openings110a,110band110c, some level of misalignment may occur due to a variety of overlay alignments shift defect in the photolithography process, which leads to the formation of gaps G1, G2and G3around the conductive plugs105aand105b, as shown inFIG.1. Then, as shown inFIG.2, liners113a,113b,113cand conductive plugs115a,115b,115care formed in the openings110a,110b,110c. The gaps G1, G2and G3are small enough such that the gaps G1, G2and G3are sealed in the semiconductor device structure100which can degrade device performance.

FIG.3is a cross-sectional view illustrating a semiconductor device structure200a, andFIG.4is a partial enlargement view illustrating the portion C of the semiconductor device structure200ashown inFIG.3according to various embodiments of the present disclosure. As shown inFIG.3, the semiconductor device structure200aincludes a semiconductor substrate201, a first dielectric layer203disposed over the semiconductor substrate201, and a second dielectric layer231disposed over the first dielectric layer203, in accordance with some embodiments.

In some embodiments, the semiconductor device structure200ahas a pattern-loose region A and a pattern-dense region B. In the pattern loose region A, the semiconductor device structure200aincludes a liner245aand a conductive plug247asurrounded by the first dielectric layer203and the second dielectric layer231. In some embodiments, the conductive plug247ais disposed in the first dielectric layer203and penetrating through the second dielectric layer231. In some embodiments, the bottom surface and the sidewalls of the conductive plug247aare covered by the liner245a, such that the conductive plug247ais separated from the semiconductor substrate201, the first dielectric layer203and the second dielectric layer231by the liner245a.

In the pattern-dense region B, the semiconductor device structure200aincludes conductive plugs227aand227bdisposed in the first dielectric layer203, and liners245b,245cand conductive plugs247b,247cdisposed in the second dielectric layer231. In some embodiments, the liner245band the conductive plug247bare disposed directly over the conductive plug227a, and the liner245cand the conductive plug247care disposed directly over the conductive plug227b. In some embodiments, the bottom surface and the sidewalls of the conductive plug247bare covered by the liner245b, such that the conductive plug247bis separated from the conductive plug227aand the second dielectric layer231by the liner245b.

Moreover, in some embodiments, the bottom surface and the sidewalls of the conductive plug247care covered by the liner245c, such that the conductive plug247cis separated from the conductive plug227band the second dielectric layer231by the liner245c. In some embodiments, the conductive plug247bis electrically connected to the conductive plug227athrough the liner245b, and the conductive plug247cis electrically connected to the conductive plug227bthrough the liner245c.

Each of the conductive plugs227aand227bincludes an upper portion and a lower portion (e.g., the upper portion UP and the lower portion LP of the conductive plug227ainFIG.4), and each of the upper portions of the conductive plugs227aand227bhas lateral extension portions that protrude into the first dielectric layer203, such as the lateral extension portions P1and P2shown inFIG.4in accordance with some embodiments. In some embodiments, the top surface T1of the conductive plug227ais greater than the bottom surface B1of the conductive plug227adue to the existence of the lateral extension portions P1and P2.

In some embodiments, the lateral extension portion P1of the conductive plug227ahas a tapered width W1that is gradually tapered from the second dielectric layer231to the semiconductor substrate201, and the lateral extension portion P2of the conductive plug227ahas a tapered width W2that is gradually tapered from the second dielectric layer231to the semiconductor substrate201. Although the details of the conductive plug227bare not illustrated, it is understood that similar features can be formed in the conductive plug227b.

FIG.5is a cross-sectional view illustrating a semiconductor device structure200b, andFIG.6is a partial enlargement view illustrating the portion D of the semiconductor device structure200bshown inFIG.5according to various embodiments of the present disclosure. The semiconductor device structure200bis similar to the semiconductor device200a. However, in the semiconductor device200b, additional liners225aand225bare disposed in the pattern-dense region B, in accordance with some embodiments.

In some embodiments, the bottom surface and the sidewalls of the conductive plug227aare covered by the liner225a, such that the conductive plug227ais separated from the first dielectric layer203and the semiconductor substrate201by the liner225a. Moreover, in some embodiments, the bottom surface and the sidewalls of the conductive plug227bare covered by the liner225b, such that the conductive plug227bis separated from the first dielectric layer203and the semiconductor substrate201by the liner225b.

Similar to the conductive plugs227aand227bin the semiconductor device structure200a, each of the conductive plugs227aand227bin the semiconductor device structure200bincludes an upper portion and a lower portion (e.g., the upper portion UP and the lower portion LP of the conductive plug227ainFIG.6), and each of the upper portions of the conductive plugs227aand227bhas lateral extension portions that protrude into the first dielectric layer203, such as the lateral extension portions P3and P4shown inFIG.6in accordance with some embodiments. As shown inFIG.6, the top surface T2of the conductive plug227ais greater than the bottom surface B2of the conductive plug227adue to the existence of the lateral extension portions P3and P4, in accordance with some embodiments.

Furthermore, the lateral extension portion P3of the conductive plug227ahas a tapered width W3that is gradually tapered from the second dielectric layer231to the semiconductor substrate201, and the lateral extension portion P4of the conductive plug227ahas a tapered width W4that is gradually tapered from the second dielectric layer231to the semiconductor substrate201, as shown inFIG.6in accordance with some embodiments. Although the details of the conductive plug227bin the semiconductor device structure200bare not illustrated, it is understood that similar features can be formed in the conductive plug227b.

FIG.7is a cross-sectional view illustrating a semiconductor device structure300aaccording to various embodiments of the present disclosure. As shown inFIG.7, the semiconductor device structure300aincludes a semiconductor substrate301, a first dielectric layer303disposed over the semiconductor substrate301, and a second dielectric layer313disposed over the first dielectric layer303, in accordance with some embodiments.

In some embodiments, the semiconductor device structure300ahas a pattern-loose region A and a pattern-dense region B. In the pattern loose region A, the semiconductor device structure300aincludes a liner323aand a conductive plug325asurrounded by the first dielectric layer303and the second dielectric layer313. In some embodiments, the conductive plug325ais disposed in the first dielectric layer303and penetrating through the second dielectric layer313. In some embodiments, the bottom surface and the sidewalls of the conductive plug325aare covered by the liner323a, such that the conductive plug325ais separated from the semiconductor substrate301, the first dielectric layer303and the second dielectric layer313by the liner323a.

In the pattern-dense region B, the semiconductor device structure300aincludes conductive plugs307aand307bdisposed in the first dielectric layer303, and the upper portions of the conductive plugs307aand307bextend into the second dielectric layer313. In some embodiments, the semiconductor device structure300aalso includes silicide layers311aand311bcovering the upper portions of the conductive plugs307aand307b, respectively. It should be noted that the silicide layers311aand311bare disconnected from each other.

In some embodiments, the top surface and the sidewalls of the upper portion of the conductive plug307aabove the top surface303T of the first dielectric layer303(e.g., the top surface T3and the sidewalls SW1, SW2) are covered by the silicide layer311a, and the top surface and the sidewalls of the upper portion of the conductive plug307babove the top surface303T of the first dielectric layer303are covered by the silicide layer311b.

In addition, the semiconductor device structure300aincludes liners323b,323cand conductive plugs325b,325cdisposed in the second dielectric layer313. In some embodiments, the liner323band the conductive plug325bare disposed directly over the conductive plug307aand the silicide layer311a, and the liner323cand the conductive plug325care disposed directly over the conductive plug307band the silicide layer311b. In some embodiments, the bottom surface and the sidewalls of the conductive plug325bare covered by the liner323b, such that the conductive plug325bis separated from the silicide layer311aand the second dielectric layer313by the liner323b.

Moreover, in some embodiments, the bottom surface and the sidewalls of the conductive plug325care covered by the liner323c, such that the conductive plug325cis separated from the silicide layer311band the second dielectric layer313by the liner323c. In some embodiments, the conductive plug325bis electrically connected to the conductive plug307athrough the liner323band the silicide layer311a, and the conductive plug325cis electrically connected to the conductive plug307bthrough the liner323cand the silicide layer311b. In some embodiments, the silicide layers311aand311bare in direct contact with the first dielectric layer303, and the conductive plugs307aand307bare separated from the second dielectric layer313by the silicide layers311aand311b.

FIG.8is a cross-sectional view illustrating a semiconductor device structure300baccording to various embodiments of the present disclosure. The semiconductor device structure300bis similar to the semiconductor device300a. For example, the top surface and the sidewalls of the upper portion of the conductive plug307aabove the top surface303T of the first dielectric layer303(e.g., the top surface T4and the sidewalls SW3, SW4) are covered by the silicide layer311a, and the top surface and the sidewalls of the upper portion of the conductive plug307babove the top surface303T of the first dielectric layer303are covered by the silicide layer311b.

However, in the semiconductor device300b, additional liners305aand305bare disposed in the pattern-dense region B, in accordance with some embodiments. In some embodiments, the bottom surface and the sidewalls of the conductive plug307aare covered by the liner305a, such that the conductive plug307ais separated from the first dielectric layer303and the semiconductor substrate301by the liner305a. Moreover, in some embodiments, the bottom surface and the sidewalls of the conductive plug307bare covered by the liner305b, such that the conductive plug307bis separated from the first dielectric layer303and the semiconductor substrate301by the liner305b.

Furthermore, the liner305aextends between the silicide layer311aand the sidewalls SW3, SW4of the upper portion of the conductive plug307aabove the top surface303T of the first dielectric layer303, and the liner305bextends between the silicide layer311band the sidewalls of the upper portion of the conductive plug307babove the top surface303T of the first dielectric layer303, in accordance with some embodiments.

In some embodiments, the semiconductor device structures200a,200b,300aand300bare dynamic random access memories (DRAM). In these cases, the conductive plugs227a,227b,247a,247b,247c,307a,307b,325a,325band325ccan serve as bit line (BL) contact plugs, capacitor contact plugs and/or interconnect structures which provide vertical electrical conduction pathways in the DRAM structures.

FIG.9is a flow diagram illustrating a method10for preparing a semiconductor device structure (e.g., the semiconductor device structures200aand200b), and the method10includes steps S11, S13, S15, S17, S19, S21and S23, in accordance with some embodiments. The steps S11to S23ofFIG.9are elaborated in connection with the following figures, such asFIGS.11-20.

FIG.10is a flow diagram illustrating a method30for preparing a semiconductor device structure (e.g., the semiconductor device structures300aand300b), and the method30includes steps S31, S33, S35, S37, S39, S41, S43, S45and S47, in accordance with some embodiments. The steps S31to S47ofFIG.10are elaborated in connection with the following figures, such asFIGS.21-26.

FIGS.11-20are cross-sectional views illustrating intermediate stages of forming the semiconductor device structure200a, in accordance with some embodiments. As shown inFIG.11, a semiconductor substrate201is provided. The semiconductor substrate201may be a semiconductor wafer such as a silicon wafer.

Alternatively or additionally, the semiconductor substrate201may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

In some embodiments, the semiconductor substrate201includes an epitaxial layer. For example, the semiconductor substrate201has an epitaxial layer overlying a bulk semiconductor. In some embodiments, the semiconductor substrate201is a semiconductor-on-insulator substrate which may include a substrate, a buried oxide layer over the substrate, and a semiconductor layer over the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

A first dielectric layer203is formed over the semiconductor substrate201, as shown inFIG.11in accordance with some embodiments. The respective step is illustrated as the step S11in the method10shown inFIG.9. In some embodiments, the first dielectric layer203is made of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material or another suitable material. The first dielectric layer203may be formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin-on coating process, or another suitable method.

Subsequently, a patterned mask205with openings210aand210bis formed over the first dielectric layer203, as shown inFIG.12in accordance with some embodiments. In some embodiments, the openings210aand210bare located in the pattern-dense region B, such that the portion of the first dielectric layer203in the pattern-dense region B is partially exposed by the openings210aand210b. In some embodiments, the portion of the first dielectric layer203in the pattern-loose region A is entirely covered by the patterned mask205.

Then, an etching process is performed on the first dielectric layer203using the patterned mask205as a mask, such that openings212aand212bare formed in the first dielectric layer203, as shown inFIG.13in accordance with some embodiments. In some embodiments, the openings212aand212bpenetrate through the first dielectric layer203, such that the semiconductor substrate201is exposed. The respective step is illustrated as the step S13in the method10shown inFIG.9. The etching process may be a wet etching process, a dry etching process, and a combination thereof. After the openings212aand212bare formed, the patterned mask205may be removed.

Next, a patterned mask215with openings220aand220bis formed over the first dielectric layer203, as shown inFIG.14in accordance with some embodiments. In some embodiments, the openings220aand220bof the patterned mask215are located in the pattern-dense region B. In some embodiments, the openings212aand212bin the first dielectric layer203and a top surface203T of the first dielectric layer203around the openings212aand212bare exposed by the openings220aand220bof the patterned mask215.

In some embodiments, the top corners TC of the first dielectric layer203in the openings212aand212bare exposed. In other words, the widths of the openings220aand220bare greater than the widths of the openings212aand212b. In some embodiments, the portion of the first dielectric layer203in the pattern-loose region A is entirely covered by the patterned mask215.

Subsequently, an etching process is performed on the first dielectric layer203using the patterned mask215as a mask, and the etching process removes portions of the first dielectric layer203at the top corners TC of the openings212aand212bto form recesses222a,222b,222cand222d, as shown inFIG.15in accordance with some embodiments. In some embodiments, the top widths of the openings212aand212bare enlarged (i.e., corner rounding). The respective step is illustrated as the step S15in the method10shown inFIG.9.

In some embodiments, the recesses222aand222bare formed on opposite sides of the opening212a, and the recesses222cand222dare formed on opposite sides of the opening212b. The etching process may be a wet etching process, a dry etching process, and a combination thereof. After the recesses222a-222dare formed, the patterned mask215may be removed.

Then, a conductive material227is formed in the openings212a,212band the recesses222a-222d, and over the first dielectric layer203, as shown inFIG.16in accordance with some embodiments. In some embodiments, the conductive material227includes copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), a combination thereof, or another suitable conductive material. The conductive material227may be formed by a deposition process, such as a CVD process, a PVD process, an ALD process, a spin-on coating process, another suitable method, or a combination thereof.

Next, a planarization process is performed on the conductive material227, such that conductive plugs227aand227bare formed in the first dielectric layer203and in the pattern-dense region B, as shown inFIG.17in accordance with some embodiments. In some embodiments, the opening212aand the recesses222a,222bare filled by the conductive plug227a, and the opening212band the recesses222c,222dare filled by the conductive plug227b. The respective step is illustrated as the step S17in the method10shown inFIG.9.

The planarization process may include a chemical mechanical polishing (CMP) process. After the planarization process, the top surfaces of the conductive plugs227aand227bare substantially coplanar with the top surface of the first dielectric layer203. Within the context of this disclosure, the word “substantially” means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

After the conductive plugs227aand227bare formed, a second dielectric layer231is formed over the first dielectric layer203and covering the conductive plugs227aand227b, in accordance with some embodiments. The respective step is illustrated as the step S19in the method10shown inFIG.9. Some materials and processes used to form the second dielectric layer231are similar to, or the same as those used to form the first dielectric layer203, and details thereof are not repeated herein.

Subsequently, a patterned mask233with openings240a,240band240cis formed over the second dielectric layer231, as shown inFIG.18in accordance with some embodiments. In some embodiments, the opening240ais located in the pattern-loose region A, and the openings240band240care located in the pattern-dense region B. In some embodiments, the second dielectric layer231is exposed by the openings240a,240band240c.

Then, an etching process is performed using the patterned mask233as a mask, such that an opening242ais formed penetrating through the first dielectric layer203and the second dielectric layer231, and openings242aand242care formed penetrating through the second dielectric layer231, as shown inFIG.19in accordance with some embodiments. In some embodiments, the portion of the semiconductor substrate201in the pattern-loose region A is partially exposed by the opening242a, and the conductive plugs227aand227bin the pattern-dense region B are partially exposed by the openings242band242c, respectively. The respective step is illustrated as the step S21in the method10shown inFIG.9.

In some embodiments, the conductive plugs227aand227bserve as etch stops during the etching process. The etching process may be a wet etching process, a dry etching process, and a combination thereof. After the openings242a,242band242care formed, the patterned mask233may be removed. In some embodiments, the portion of the second dielectric layer231in the pattern-loose region A is entirely covered by the patterned mask233, and the opening242ais formed in a separate process step than the forming of the openings242band242c.

Next, a lining material245and a conductive material247are sequentially formed in the openings242a,242b,242cand over the second dielectric layer231, as shown inFIG.20in accordance with some embodiments. In some embodiments, the lining material245includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt tungsten (CoW), another applicable material, or a combination thereof, and the lining material245is formed by a deposition process, such as a CVD process, a PVD process, an ALD process, a metal organic chemical vapor deposition (MOCVD) process, a sputtering process, a plating process, or another applicable process.

In some embodiments, the conductive material247includes copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), a combination thereof, or another applicable conductive material. Some processes used to form the conductive material247are similar to, or the same as those used to form the lining material245, and details thereof are not repeated herein.

Subsequently, a planarization process is performed on the lining material245and the conductive material247, such that a liner245aand a conductive plug247aare formed in the pattern-loose region A, and liners245b,245cand conductive plugs247b,247care formed in the pattern-dense region B, as shown inFIG.3in accordance with some embodiments. The respective step is illustrated as the step S23in the method10shown inFIG.9. The planarization process may include a CMP process. After the planarization process is performed, the semiconductor device structure200ais obtained.

The semiconductor device structure200bshown inFIG.5may be formed using similar processes as the semiconductor device structure200a. In some embodiments, a lining material (not shown) is formed lining the openings212a,212band the recesses222a-222dand over the first dielectric layer203before the conductive material227is formed (seeFIGS.15and16), and the lining material is planarized with the conductive material227in order to form the liners225aand225bin the semiconductor device structure200b.

FIGS.21-26are cross-sectional views illustrating intermediate stages of forming the semiconductor device structure300a, in accordance with some embodiments. As shown inFIG.21, a semiconductor substrate301is provided, in accordance with some embodiments. The semiconductor substrate301is similar to, or the same as those of the semiconductor substrate201, and details thereof are not repeated herein.

Still referring toFIG.21, a first dielectric layer303and conductive plugs307a,307bare formed over the semiconductor substrate301, in accordance with some embodiments. In some embodiments, the formation of the first dielectric layer303and the conductive plugs307aand307bincludes forming a first dielectric layer303over the semiconductor substrate301, etching the first dielectric layer303to form openings (not shown) partially exposing the portion of the semiconductor substrate301in the pattern-dense region B, forming a conductive material (not shown) in the openings and over the first dielectric layer303, and performing a planarization process on the conductive material to form the conductive plugs307aand307b. The respective steps are illustrated as the steps S31-35in the method30shown inFIG.10.

After the planarization process, the top surfaces of the first dielectric layer and the conductive plugs307aand307bare substantially coplanar to each other. For example, the top surface T3of the conductive plug307ais substantially coplanar with the top surface303T of the dielectric layer303. Some materials used to form the first dielectric layer303and the conductive plugs307a,307bare similar to, or the same as those used to form the first dielectric layer203and the conductive plugs227aand227b, and details thereof are not repeated herein.

Next, an etching process is performed on the first dielectric layer303such that upper portions of the conductive plugs307aand307bprotrude from the first dielectric layer303, as shown inFIG.22in accordance with some embodiments. The respective step is illustrated as the step S37in the method30shown inFIG.10.

In some embodiments, after the etching process, the top surfaces of the conductive plugs307a,307bare higher than the top surface of the first dielectric layer303. For example, the top surface T3of the conductive plug307ais higher than the top surface303T of the first dielectric layer303. The etching process may be a wet etching process, a dry etching process, and a combination thereof.

Subsequently, a polysilicon layer311is deposited conformally covering the top surface303T of the first dielectric layer303and the upper portions of the conductive plugs307a,307bover the top surface303T of the first dielectric layer303, as shown inFIG.23in accordance with some embodiments. For example, the top surface T3and the sidewalls SW1, SW2of the upper portion of the conductive plug307aare covered by and in direct contact with the polysilicon layer311. The respective step is illustrated as the step S39in the method30shown inFIG.10. In some embodiments, the polysilicon layer311is deposited by a CVD process, a PVD process, an ALD process, a spin-on coating process, another suitable method, or a combination thereof.

Then, a thermal treatment process is performed to transform portions of the polysilicon layer311into silicide layers311aand311bcovering the upper portions of the conductive plugs307aand307b, and a remaining portion (i.e., the unreacted portion) of the polysilicon layer311is removed, as shown inFIG.24in accordance with some embodiments. For example, the top surface T3and the sidewalls SW1, SW2of the upper portion of the conductive plug307aare covered by and in direct contact with the silicide layer311a. The respective step is illustrated as the step S41in the method30shown inFIG.10. In some embodiments, the remaining portion of the polysilicon layer311is removed by an etching process.

Next, a second dielectric layer313is formed over the first dielectric layer303and covering the silicide layers311a,311b, and an etching process is performed on the first dielectric layer303and the second dielectric layer313to form openings320a,320band320c, as shown inFIG.25in accordance with some embodiments. The respective steps are illustrated as the steps S43-S45in the method30shown inFIG.10. In some embodiments, the opening320ais formed penetrating through the first dielectric layer303and the second dielectric layer313, and the openings320band320care formed penetrating through the second dielectric layer313.

In some embodiments, the portion of the semiconductor substrate301in the pattern-loose region A is partially exposed by the opening320a, and the silicide layers311aand311bin the pattern-dense region B are partially exposed by the openings320band320c, respectively. In some embodiments, the silicide layers311aand311bserve as etch stops during the etching process. The etching process may be a wet etching process, a dry etching process, and a combination thereof. In some embodiments, the opening320ais formed in a separate process step than the forming of the openings320band320c.

Subsequently, a lining material323and a conductive material325are sequentially formed in the openings320a,320b,320cand over the second dielectric layer313, as shown inFIG.26in accordance with some embodiments. Some materials and processes used to form the lining material323and the conductive material325are similar to, or the same as those used to form the lining material245and the conductive material247, and details thereof are not repeated herein. It should be noted that the lining material323is separated from the conductive plugs307aand307bby the silicide layers311aand311b, in accordance with some embodiments.

Then, a planarization process is performed on the lining material323and the conductive material325, such that a liner323aand a conductive plug325aare formed in the pattern-loose region A, and liners323b,323cand conductive plugs325b,325care formed in the pattern-dense region B, as shown inFIG.7in accordance with some embodiments. The respective step is illustrated as the step S47in the method30shown inFIG.10. The planarization process may include a CMP process. After the planarization process is performed, the semiconductor device structure300ais obtained.

The semiconductor device structure300bshown inFIG.8may be formed using similar processes as the semiconductor device structure300a. Some processes used to form the liners305aand305bof the semiconductor device structure300bare similar to, or the same as those used to form the liners225aand225bin the semiconductor device structure200b, and details thereof are not repeated herein.

FIG.27is a partial schematic illustration of an exemplary integrated circuit, such as a memory device1000, including an array of memory cells50according to various embodiments of the present disclosure. In some embodiments, the memory device1000includes a DRAM. In some embodiments, the memory device1000includes a number of memory cells50arranged in a grid pattern and including a number of rows and columns. The number of memory cells50may vary depending on system requirements and fabrication technology.

In some embodiments, each of the memory cells50includes an access device and a storage device. The access device is configured to provide controlled access to the storage device. In particular, the access device is a field effect transistor (FET)51and the storage device is a capacitor53, in accordance with some embodiments. In each of the memory cells50, the FET51includes a drain55, a source57and a gate59. One terminal of the capacitor53is electrically connected to the source57of the FET51, and the other terminal of the capacitor53may be electrically connected to the ground. In addition, in each of the memory cells50, the gate59of the FET51is electrically connected to a word line WL, and the drain55of the FET51is electrically connected to a bit line BL.

The above description mentions the terminal of the FET51electrically connected to the capacitor53is the source57, and the terminal of the FET51electrically connected to the bit line BL is the drain55. However, during read and write operations, the terminal of the FET51electrically connected to the capacitor53may be the drain, and the terminal of the FET51electrically connected to the bit line BL may be the source. That is, either terminal of the FET51could be a source or a drain depending on the manner in which the FET51is being controlled by the voltages applied to the source, the drain and the gate.

By controlling the voltage at the gate59via the word line WL, a voltage potential may be created across the FET30such that the electrical charge can flow from the drain55to the capacitor53. Therefore, the electrical charge stored in the capacitor53may be interpreted as a binary data value in the memory cell30. For example, a positive charge above a threshold voltage stored in the capacitor53may be interpreted as binary “1.” If the charge in the capacitor53is below the threshold value, a binary value of “0” is said to be stored in the memory cell30.

The bit lines BL are configured to read and write data to and from the memory cells50. The word lines WL are configured to activate the FET51to access a particular row of the memory cells50. Accordingly, the memory device1000also includes a periphery circuit region which may include an address buffer, a row decoder and a column decoder. The row decoder and the column decoder selectively access the memory cells50in response to address signals that are provided to the address buffer during read, write and refresh operations. The address signals are typically provided by an external controller such as a microprocessor or another type of memory controller.

Referring back toFIGS.3,5,7and8, the conductive plugs247aand325aare formed in the pattern-loose region A, while the conductive plugs247b,247c,325b,325care formed in the pattern-dense region B. The pattern-loose region A may be any of the regions of the address buffer, the row decoder, or the column decoder in the memory device1000, and the pattern-dense region B may be any of the regions of the memory cells50in the memory device1000.

Embodiments of the semiconductor device structures200aand200band method for preparing the same are provided in the disclosure. In some embodiments, each of the semiconductor device structures200aand200bincludes a first conductive plug (e.g., the conductive plug227a) and a second conductive plug (e.g., the conductive plug247b) directly over the first conductive plug, and a top surface of the first conductive plug is greater than a bottom surface of the first conductive plug. The aforementioned stacked conductive plugs can help to eliminate the problems of having overhang resulting from the difficulties in filling a high aspect ratio opening structure.

Moreover, the greater top surface of the first conductive plug increases the landing area for the second conductive plug. Therefore, the possibility of gap formation between the conductive plugs and the surrounding dielectric layers (e.g., the first dielectric layer203and the second dielectric layer231) can be reduced, and the risk of misalignment between the first conductive plug and the second conductive plug can be prevented. As a result, the performance, reliability and yield of the semiconductor device structures200aand200bcan be improved.

Embodiments of the semiconductor device structures300aand300band method for preparing the same are provided in the disclosure. In some embodiments, each of the semiconductor device structures300aand300bincludes a first conductive plug (e.g., the conductive plug307a), a silicide layer (e.g., the silicide layer311a) covering a top surface and sidewalls of an upper portion of the first conductive plug, and a second conductive plug (e.g., the conductive plug325b) directly over the first conductive plug and the silicide layer. The aforementioned stacked conductive plugs can help to eliminate the problems of having overhang resulting from the difficulties in filling a high aspect ratio opening structure.

In addition, the silicide layer disposed over the first conductive plug increases the landing area for the second conductive plug. Therefore, the possibility of gap formation between the conductive plugs and the surrounding dielectric layers (e.g., the first dielectric layer303and the second dielectric layer313) can be reduced, and the risk of misalignment between the first conductive plug and the second conductive plug can be prevented. As a result, the performance, reliability and yield of the semiconductor device structures300aand300bcan be improved.

In one embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. A top surface of the first conductive plug is greater than a bottom surface of the first conductive plug. The semiconductor device structure further includes a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug.

In another embodiment of the present disclosure, a semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. An upper portion of the first conductive plug extends into the second dielectric layer. The semiconductor device structure further includes a silicide layer disposed in the second dielectric layer and covering a top surface and sidewalls of the upper portion of the first conductive plug, and a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug and the silicide layer.

In another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method includes forming a first dielectric layer over a semiconductor substrate, and etching the first dielectric layer to form a first opening exposing the semiconductor substrate. The method also includes forming recesses by removing portions of the first dielectric layer at top corners of the first opening, and forming a first conductive plug in the first opening and the recesses. The method further includes forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a second opening exposing the first conductive plug. In addition, the method includes forming a second conductive plug in the second opening.

In yet another embodiment of the present disclosure, a method for preparing a semiconductor device structure is provided. The method includes forming a first dielectric layer over a semiconductor substrate, and etching the first dielectric layer to form a first opening exposing the semiconductor substrate. The method also includes forming a first conductive plug in the first opening, and etching the first dielectric layer such that an upper portion of the first conductive plug protrudes from a top surface of the first dielectric layer. The method further includes forming a silicide layer covering a top surface and sidewalls of the upper portion of the first conductive plug, and forming a second dielectric layer over the first dielectric layer. In addition, the method includes etching the second dielectric layer to form a second opening exposing the silicide layer, and forming a second conductive plug in the second opening.

The embodiments of the present disclosure have some advantageous features. In some embodiments, the semiconductor device structure includes a first conductive plug and a second conductive plug directly over the first conductive plug, and a top surface of the first conductive plug is greater than a bottom surface of the first conductive plug. The aforementioned stacked conductive plugs can help to eliminate the problems of having overhang resulting from the difficulties in filling a high aspect ratio opening structure. In addition, the greater top surface of the first conductive plug increases the landing area for the second conductive plug. Therefore, the possibility of gap formation between the conductive plugs and the surrounding dielectric layers can be reduced, and the risk of misalignment between the first conductive plug and the second conductive plug can be prevented. As a result, the performance, reliability and yield of the semiconductor device structure can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.