Patent ID: 12249363

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The advantages and features of the present disclosure and methods of achieving the same will be apparent from the exemplary embodiments to be described below in more detail with reference to the accompanying drawings. However, it should be noted that the present disclosure is not limited to the following exemplary embodiments, and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose the present disclosure and to let those skilled in the art know the category of the present disclosure, and the present disclosure is to be defined based only on the claims. The same reference numerals or the same reference designators denote the same elements throughout the specification.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements are not intended to be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element discussed below could be referred to as a second element without departing from the technical spirit of the present disclosure.

The terms used herein are for the purpose of describing particular embodiments only, and are not intended to limit the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,”, “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless differently defined, all terms used herein, including technical or scientific terms, have the same meanings as terms generally understood by those skilled in the art to which the present disclosure pertains. Terms identical to those defined in generally used dictionaries should be interpreted as having meanings identical to contextual meanings of the related art, and are not to be interpreted as having ideal or excessively formal meanings unless they are definitively defined in the present specification.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description of the present disclosure, the same reference numerals are used to designate the same or similar elements throughout the drawings, and repeated descriptions of the same components will be omitted.

FIG.1is a flowchart illustrating a method for controlling a refresh period of an extension memory pool according to an embodiment of the present disclosure.

Referring toFIG.1, the method for controlling a refresh period of an extension memory pool according to an embodiment includes collecting information about each of preset unit DRAM cell sets of an extension memory pool at step S110, setting an initial refresh period for each of the DRAM cell sets at step S120, and adjusting the refresh period based on the information collected from the DRAM cell sets at step S130.

Here, the initial refresh period may be set based on the data retention time of a DRAM cell having the shortest retention time, among DRAM cells in the unit DRAM cell set.

Here, the information about each of the preset unit DRAM cell sets may include information about the address of a weak row including a DRAM cell having a short data retention time and information about the address of a safe row configured with DRAM cells having a long data retention time.

Here, the method for controlling a refresh period may further include remapping memory access to the weak row to the safe row.

Here, remapping the memory access may be performed based on a result of comparison of an accessed memory address with the address of the weak row.

Here, collecting the information about each of the preset unit DRAM cell sets at step S110may comprise collecting the temperatures of the DRAM cell sets and information about whether an error occurs.

Here, collecting the temperatures of the unit DRAM cell sets and information about whether an error occurs may be performed for a unit greater than a unit DRAM cell set, e.g., for each DRAM module unit, and the scope of the present disclosure is not limited to the unit for which temperature is measured.

Here, adjusting the refresh period at step S130may comprise, when an error occurs in a specific DRAM cell, decreasing the refresh period of a unit DRAM cell set including the DRAM cell in which the error occurred.

Here, adjusting the refresh period at step S130may comprise again decreasing the refresh period of the unit DRAM cell set when an error again occurs within a preset time period based on the adjusted refresh period and increasing the refresh period of the unit DRAM cell set when no error occurs within the preset time period.

Here, adjusting the refresh period at step S130may be performed using a count bit value.

Here, adjusting the refresh period at step S130may comprise, when the temperature of a specific section in the DRAM becomes higher than a preset temperature, comparing the refresh period of a unit DRAM cell set including the specific section, in which the temperature becomes higher than the preset temperature, with a preset threshold-temperature-based period and adjusting the refresh period.

FIG.2is a view illustrating a system structure including an extension memory pool according to an embodiment of the present disclosure.

Referring toFIG.2, a system having an extension memory pool is configured with a host100that uses the extension memory pool160by accessing the same and a memory extension device110, which is a device for connecting the extension memory pool160with the host100.

The host100is configured with a CPU120and local DRAM130, and accesses the memory extension device110through a hardware interface, such as PCIe or CCIX, in order to secure an additional memory capacity in addition to the local DRAM130, thereby using the extension memory pool160as if it were the local memory thereof.

The memory extension device110is configured with a device controller140for controlling the memory extension device110, a memory controller150for controlling the extension memory pool160, and the extension memory pool160. Because the memory extension device110is commonly implemented through a Field-Programmable Gate Array (FPGA), it is easy to implement an additional function required by a user, such as the refresh period control method of the present disclosure.

FIG.3is a block diagram illustrating in detail an apparatus for controlling a refresh period according to an embodiment of the present disclosure.

Referring toFIG.3, the apparatus for controlling a refresh period according to the present disclosure may be implemented in a memory extension device110for increasing the memory capacity of a host100.

Here, the apparatus for controlling a refresh period is configured with a profiler200, a refresh table210, an address table220, a refresh controller230, an ECC engine240, an address comparison device250, and a remapping unit260. The refresh controller230, the ECC engine240, and the remapping unit260may be located in a memory controller150.

The profiler200profiles the data retention time of each of preset unit DRAM cell sets for DRAM constituting an extension memory pool160. Here, a unit DRAM cell set indicates a set of DRAM cells on which a refresh operation is performed by the same refresh command. The memory controller150may issue a refresh command to DRAM in any of various methods, such as per-bank refresh for performing a refresh operation for each DRAM bank, a rank-level refresh or all-bank refresh for performing a refresh operation for each DRAM rank, and the like. Therefore, a unit DRAM cell set may be variously defined according to the implementation method of the present disclosure.

The profiler200stores the profiled information in the refresh table210, and the stored information is the address of each unit DRAM cell set and the initial refresh period value of the unit DRAM cell set. The initial refresh period value is set based on a cell having the shortest data retention time, among DRAM cells included in the unit DRAM cell set.

For example, when the data retention time of the cell having the shortest data retention time, among the cells in the unit DRAM cell set, is 70 msec, the initial refresh period value of the unit DRAM cell set may be set to 64 msec.

The profiler200also profiles the address of a weak row, which is a DRAM row including a weak cell, and stores the same in the address table220. Here, the weak cell indicates a DRAM cell having a data retention time shorter than the minimum refresh period set by a user. For example, when a user sets the minimum value of the refresh period to apply to an extension memory pool to 128 msec, a cell having a data retention time shorter than 128 msec is a weak cell, and a DRAM row including the cell is a weak row.

The minimum refresh period is set longer than a value set as the refresh period of existing commercial DRAM (e.g., 64 msec). This is for reducing the amount of power consumed for DRAM by reducing the number of times a refresh operation is performed, compared to the existing DRAM. For example, when the minimum refresh period is set to 128 msec, the number of refresh operations is reduced to half the number of refresh operations performed when the refresh period is 64 msec, which is a commonly used refresh period in DRAM, whereby the power consumption for the refresh operation may be theoretically reduced to half.

The profiler200also profiles the address of a safe row configured with reliable DRAM cells and stores the same in the address table220so as to correspond to the address of the weak row. That is, the address of a safe row corresponding to the address of each weak row is also present in the address table220. All of the DRAM cells included in the safe row have a data retention time longer than the minimum refresh period.

The initial refresh period value for each unit DRAM cell set stored in the above-mentioned refresh table210is set so as not to be less than the minimum refresh period. If a certain unit DRAM cell set includes a weak row, the initial refresh period value of the unit DRAM cell set is set to the minimum refresh period.

The time at which the profiler200performs profiling may be variously defined, such as the time predefined by the host100(e.g., each time the system boots) or the time at which the host100transfers a profile command.

The refresh controller230issues a refresh command at every period set for each unit DRAM cell set by referring to the refresh table210. The initial value of the refresh period of each unit DRAM cell set is the initial refresh period value of each unit DRAM cell set, which is stored in the refresh table210by the profiler200.

The refresh controller230monitors, in real time, the temperature of DRAM included in the extension memory pool160and whether an error occurs, thereby dynamically adjusting a period of issuing a refresh command. When the period of issuing a refresh command is adjusted, the refresh controller230updates the refresh table210with the adjusted period. The method of adjusting a refresh period, performed by the refresh controller230, will be described in detail with reference toFIG.4andFIG.5.

In order to ensure the reliability of DRAM in the extension memory pool160, the ECC engine240generates an Error Correction Code (ECC) of data and stores the same in DRAM along with the data when a write command is executed, and reads the ECC along with the data when a read command is executed, thereby verifying the integrity of the data. If an error occurs in the data in the verification process, the ECC engine240recovers the error and notifies the refresh controller230of the occurrence of the error.

The ECC used by the ECC engine240in the present disclosure is not limited to a specific form of code, and may be implemented in any of various forms, such as a parity code, a hamming code, a Reed-Solomon (RS) code, and the like.

When the host accesses a weak row, the address comparison device250refers to the address table220and notifies the remapping unit260of the access to the weak row through an interrupt signal. The remapping unit260remaps the access to the weak row, which is announced by the address comparison device250, to access to a safe row corresponding to the weak row. The operation methods of the address comparison device250and the remapping unit260will be described in detail later with reference toFIG.6.

FIG.4is a flowchart illustrating a method of adjusting a refresh period depending on whether a real-time error occurs in DRAM.

Here, the step of adjusting a refresh period depending on whether a real-time error occurs in DRAM may be performed by the refresh controller230ofFIG.3. Here, the method of dynamically adjusting a refresh period is applied to each unit DRAM cell set, and may be performed in parallel in all of the unit DRAM cell sets.

First, the refresh controller230initializes a count bit, which gives information about the difference between the current refresh period of a unit DRAM cell set and the initial refresh period value thereof, to 0 at step S200. Subsequently, the refresh controller230monitors whether an error occurs in the unit DRAM cell set through the ECC engine240at step S210. When an error occurs in a certain cell at step S220, the refresh period of the unit DRAM cell set including the cell is decreased by one level, and the value of the count bit is increased by 1 at step S230. The refresh controller230adjusts the refresh period using the value of tREF, which is a parameter indicating the refresh period.

The unit by which the refresh controller230adjusts a refresh period may vary depending on the implementation method of the present disclosure. For example, when a user sets a refresh period adjustment unit to 32 msec and when the previous refresh period was 64 msec, if the refresh period is decreased by one level, the refresh period changes to 32 msec.

Even after it adjusts the refresh period, the refresh controller230continues to monitor whether an error occurs in the corresponding unit DRAM cell set at step S240. If an error occurs again in the corresponding unit DRAM cell set within a certain time period Δt, the process returns to the step (S230) of decreasing the refresh period by one level. If no error occurs in the corresponding unit DRAM cell set within the time period Δt, the refresh period of the corresponding unit DRAM cell set is increased by one level, and the value of the count bit is decreased by 1 at step S260. Subsequently, whether the value of the count bit of the corresponding unit DRAM cell set is 0 is checked at step S270, and when the value is not 0, the process returns to the step (S240) of monitoring whether an error occurs. When the value is 0, the process moves to a termination step. The method of dynamically adjusting a refresh period illustrated inFIG.4is restarted from the initial step immediately after the process is terminated.

FIG.5is a flowchart illustrating a method of adjusting a refresh period depending on the real-time temperature of DRAM.

Here, the step of adjusting a refresh period depending on the real-time temperature of DRAM may be performed by the refresh controller230illustrated inFIG.3. Here, the method of dynamically adjusting a refresh period is applied to each unit DRAM cell set, and may be performed in parallel in all of the unit DRAM cell sets.

Referring toFIG.5, the refresh controller230monitors temperature information of the extension memory pool160by receiving the same from temperature sensors in the extension memory pool160at step S300. If the value of a specific temperature sensor is higher than a threshold temperature thre_temp at step S310, the current refresh period of a unit DRAM cell set included in the corresponding area is compared with a predefined threshold-temperature-based period value T_tREF. When the current refresh period value of the corresponding unit DRAM cell set is greater than the threshold-temperature-based period value at step S320, the refresh period of the corresponding unit DRAM cell set is changed to the threshold-temperature-based period value at step S330. If the refresh period of the corresponding unit DRAM cell set is already decreased as the result of application of the method of dynamically adjusting a refresh period depending on whether an error occurs, illustrated inFIG.4, the process may move to a termination step without adjusting the refresh period. The method of dynamically adjusting a refresh period illustrated inFIG.5is restarted from the initial step immediately after the process is terminated.

FIG.6is a flowchart illustrating a process of remapping memory access to a weak row to a safe row.

When a host100accesses an extension memory pool160, an address comparison device250compares the memory address to which the host100intends to access with an address of a weak row stored in an address table220at step S400. When an address of a weak row that is the same as the memory address to which the host100intends to access is present at step S410, the memory access is remapped to access to a safe row corresponding to the weak row at step S420. That is, the access to the address of the weak row is remapped to access to the address of the safe row. If an address corresponding to the memory address to which the host100intends to access is not present in the weak row list of the address table220, the process moves to a termination step. The address remapping method illustrated inFIG.6is applied to all accesses by the host to the extension memory pool160.

When the address remapping method illustrated inFIG.6is applied, an increase in the number of weak rows causes overhead in terms of the capacity of the extension memory pool160. However, because a very small number of weak cells is present in a DRAM module (generally1000or fewer weak cells are present in a DRAM module having a capacity of 32 GB), even though the address remapping method ofFIG.6is applied, the overhead in terms of the capacity is insignificant.

Even though the above-mentioned minimum refresh period value is set long through the address remapping method ofFIG.6, the reliability of the extension memory pool160may be maintained. Accordingly, the number of times a refresh operation is performed is decreased compared to existing commercial DRAM, whereby the amount of power consumed by the extension memory pool160may be significantly decreased while ensuring the same level of reliability as existing commercial DRAM.

FIG.7is a block diagram illustrating an apparatus for controlling a refresh period of an extension memory pool according to an embodiment of the present disclosure.

Referring toFIG.7, the apparatus for controlling a refresh period of an extension memory pool according to an embodiment includes a storage unit310for collecting information about each of preset unit DRAM cell sets of an extension memory pool and a control unit320for setting the initial refresh period for each of the DRAM cell sets and adjusting the initial refresh period based on the information collected from the DRAM cell sets.

Here, the initial refresh period may be set based on the data retention time of a DRAM cell having the shortest retention time, among DRAM cells in the unit DRAM cell set.

Here, the information about each of the preset unit DRAM cell sets may include information about the address of a weak row including a DRAM cell having a short data retention time and information about the address of a safe row configured with DRAM cells having a long data retention time.

Here, the apparatus for controlling a refresh period may further include a remapping unit330for remapping memory access to the weak row to the safe row.

Here, the remapping unit330may perform remapping based on the result of comparison of the accessed memory address with the address of the weak row.

Here, the storage unit310may collect the temperatures of the unit DRAM cell sets and information about whether an error occurs.

Here, when an error occurs in a specific DRAM cell, the control unit320may decrease the refresh period of the unit DRAM cell set including the DRAM cell in which the error occurs.

Here, when an error occurs again within a preset time period based on the adjusted refresh period, the control unit320may again decrease the refresh period of the unit DRAM cell set, whereas when no error occurs within the preset time period, the control unit320may increase the refresh period of the unit DRAM cell set.

Here, the control unit320may adjust the refresh period using a count bit value.

Here, when the temperature of a specific section in the DRAM is higher than a preset temperature, the control unit320may compare the refresh period of the unit DRAM cell set including the specific section, in which the temperature is higher than the preset temperature, with a preset threshold-temperature-based period and adjust the refresh period.

FIG.8is a view illustrating the configuration of a computer system according to an embodiment.

The apparatus for controlling a refresh period of an extension pool according to an embodiment may be implemented in a computer system1000including a computer-readable recording medium.

The computer system1000may include one or more processors1010, memory1030, a user-interface input device1040, a user-interface output device1050, and storage1060, which communicate with each other via a bus1020. Also, the computer system1000may further include a network interface1070connected to a network1080. The processor1010may be a central processing unit or a semiconductor device for executing a program or processing instructions stored in the memory1030or the storage1060. The memory1030and the storage1060may be storage media including at least one of a volatile medium, a nonvolatile medium, a detachable medium, a non-detachable medium, a communication medium, or an information delivery medium, or a combination thereof. For example, the memory1030may include ROM1031or RAM1032.

According to the present disclosure, a method for efficiently performing a refresh operation may be provided in order to reduce the amount of power consumed for an extension memory pool configured with DRAM.

Also, the present disclosure may significantly reduce power consumption by adjusting a refresh period in consideration of the reliability of memory included in an extension memory pool, the real-time temperature thereof, and whether a real-time error occurs.

Specific implementations described in the present disclosure are embodiments and are not intended to limit the scope of the present disclosure. For conciseness of the specification, descriptions of conventional electronic components, control systems, software, and other functional aspects thereof may be omitted. Also, lines connecting components or connecting members illustrated in the drawings show functional connections and/or physical or circuit connections, and may be represented as various functional connections, physical connections, or circuit connections that are capable of replacing or being added to an actual device. Also, unless specific terms, such as “essential”, “important”, or the like, are used, the corresponding components may not be absolutely necessary.

Accordingly, the spirit of the present disclosure should not be construed as being limited to the above-described embodiments, and the entire scope of the appended claims and their equivalents should be understood as defining the scope and spirit of the present disclosure.