Patent ID: 12260893

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the disclosure will be described in detail so that those skilled in the art may easily understand and reproduce the disclosure through embodiments described with reference to the accompanying drawings. In the description of the disclosure, when it is determined that detailed descriptions of a well-known function or configuration may unnecessarily obscure the principle of the disclosure, the detailed descriptions thereof will be omitted. Terms used throughout the specification of the disclosure are terms defined in consideration of functions in the embodiment of the disclosure, and since the terms may be sufficiently modified according to intentions or customs of users and operators, the definitions of these terms should be made based on the content throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises”, “comprising”, “includes”, and/or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially”, “about”, and other similar terms are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Further, the above-described aspects and additional aspects of the disclosure will become apparent through the embodiments to be described below. It is understood that configurations of the aspects or embodiments optionally disclosed in the specifications can be freely combined with each other even when shown as a single integrated configuration in the drawings unless a technical contradiction is apparent to those skilled in the art, unless otherwise disclosed. Accordingly, since the embodiments disclosed in the specification and the configurations shown in the drawings are merely an embodiment of the disclosure and do not represent all the technical spirit of the disclosure, it should be understood that there may be various equivalents and modifications at the time of filing the application.

The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an ideal or excessively formal sense unless clearly defined in the specification.

FIG.2is a schematic view for describing a semiconductor memory device including a semiconductor memory module including a power management unit, and a semiconductor memory control unit which controls the semiconductor memory module according to an embodiment. As shown in the drawing, a semiconductor memory device3000may include a semiconductor memory control unit2000and a semiconductor memory module1000which receives a source voltage from the semiconductor memory control unit2000to perform electrical operation.

The semiconductor memory control unit2000may include a source voltage supplier2100which supplies a source voltage to the semiconductor memory module, and a voltage regulation commander2200which generates a voltage regulation command signal and provides the voltage regulation command signal to the semiconductor memory module. The voltage regulation commander2200may be configured as a basic input output system (BIOS).

The semiconductor memory module1000may include the dynamic random access memory (DRAM) array100and the power management unit200which supplies a source voltage to the DRAM array. The power management unit200may be implemented as a combination of application software and hardware in a power management integrated circuit (PMIC). The semiconductor memory module1000may receive the source voltage and the voltage regulation command signal from the semiconductor memory control unit to perform electrical operation.

The power management unit200may include a reference voltage generator210, a voltage regulation controller220, an internal voltage generator230, an internal voltage driver240, and a voltage compensation unit250.

The reference voltage generator210may receive a source voltage from the source voltage supplier of the semiconductor memory control unit to generate a reference voltage Vref.

The voltage regulation controller220may receive the voltage regulation command signal from the voltage regulation commander of the semiconductor memory control unit to generate a control signal. The control signal generated by the voltage regulation controller220is a switching control signal, and may be an up/down or on/off signal. The voltage regulation controller220may be implemented in an analog method or may be implemented in a digital method.

The internal voltage generator230may receive a reference voltage from the reference voltage generator and receive the control signal from the voltage regulation controller to generate a cell array reference voltage VrefA.

The internal voltage driver240may receive the cell array reference voltage VrefA from the internal voltage generator and stabilize the cell array reference voltage VrefA to supply a cell array voltage VDDA to the DRAM array,

The voltage driver may serve to constantly maintain an output voltage thereof. For example, when a device using this output voltage is switched from a standby state to an operating state, current consumption (power) increases instantaneously, which causes the voltage to drop, and the voltage driver may serve to increase the output voltage by comparing a difference between the voltage output through an own feedback circuit line and the reference voltage. On the other hand, when the output voltage increases, the voltage driver may serve to lower the voltage.

The voltage compensation unit250may receive the cell array voltage VDDA by feedback ({circle around (1)}) and transmit a compensation command signal to the voltage regulation controller220({circle around (3)}).

The voltage compensation unit250provided in the semiconductor memory module1000may be provided inside or outside the PMIC. Even when the voltage compensation unit250is provided outside the PMIC, the voltage compensation unit250should be regarded as being included in the power management unit (PMU)200.

FIG.3is a schematic view for describing the voltage compensation unit according to an embodiment. As shown in the drawing, the voltage compensation unit250may include a voltage measurer251, a voltage comparator252, and a voltage compensation commander253. Each of the voltage measurer251, the voltage comparator252, and the voltage compensation commander253may be configured as hardware or software.

The voltage measurer251may receive the cell array voltage VDDA by feedback ({circle around (1)}) to measure a voltage value in real time and output a measurement voltage value. A measurement period may be appropriately determined in a range of about 0.1 ms to about 10 ms.

The voltage comparator252may receive the measurement voltage value, and compare the measurement voltage value and a reference voltage value acquired based on the voltage regulation command signal received from the voltage regulation commander ({circle around (2)}) to output a comparison signal. The comparison signal may indicate information on a difference or a ratio of voltage values. For example, the VDDA may indicate information of 1.2 V−2 V=−0.02 V, and may also indicate information of −0.02 V/1.20 V=−1.7%.

The voltage compensation commander253may receive the comparison signal and transmit the compensation command signal to the voltage regulation controller220based on the comparison signal ({circle around (3)}). In the above example, in the case of −0.02 V or −1.7%, a voltage up command to increase by +0.02 V or +1.7% may be given.

According to an embodiment, the voltage compensation commander253may receive the comparison signal and transmit the compensation command signal to the voltage regulation commander2200of the semiconductor memory control unit2000based on the comparison signal ({circle around (3)}′). Whether the voltage compensation commander253will transmit the compensation command signal to the voltage regulation controller220({circle around (3)}) or the voltage compensation commander253will transmit the compensation command signal to the voltage regulation commander2200({circumflex over (3)}′) may depend on information of the comparison signal.

FIG.4is a schematic view for describing operations of the voltage compensation commander253and the semiconductor memory device3000according to information of the comparison signal according to an embodiment. As a result of the voltage compensation commander253inFIG.3analyzing the information of the comparison signal (S100, S200), the voltage compensation commander253transmits the compensation command signal to the voltage regulation controller220({circle around (3)}) to perform voltage compensation (S300) when a difference value between the measurement voltage value and the reference voltage value is smaller than a threshold value (Y). For example, in the above example, when a threshold value is ±25%, ±1.7% is smaller than the threshold value.

However, when the difference value is greater than the threshold value (N), the voltage compensation commander253may transmit the compensation command signal to the voltage regulation commander2200({circumflex over (3)}′) so as to not perform voltage compensation (No voltage Compensation, S400), and further, may provide a defect notice (a failure notification) to a host computer (not shown) (S500). In order to not perform voltage compensation, the voltage regulation commander2200may not transmit the voltage regulation command signal to the voltage regulation controller220. For example, when the threshold value is ±25%, ±30% is greater than the threshold value.

FIG.5is a schematic view for describing a semiconductor memory device including a semiconductor memory module including a power management unit which generates various internal voltages and a semiconductor memory control unit which controls the semiconductor memory module according to another embodiment. As shown in the drawing, a semiconductor memory device3000may include a semiconductor memory control unit2000and a semiconductor memory module1000which receives a source voltage from the semiconductor memory control unit to perform electrical operation.

The semiconductor memory control unit2000includes a source voltage supplier2100which supplies a source voltage to the semiconductor memory module, and a voltage regulation commander2200which generates a voltage regulation command signal and provides the voltage regulation command signal to the semiconductor memory module. The voltage regulation commander2200may be configured as a basic input output system (BIOS).

The semiconductor memory module1000may include a DRAM array100and a power management unit200which supplies a source voltage to the DRAM array. The power management unit200may be implemented as a combination of application software and hardware in a PMIC. The semiconductor memory module1000may receive the source voltage and the voltage regulation command signal from the semiconductor memory control unit to perform electrical operation.

The power management unit200may include a reference voltage generator210, a voltage regulation controller220, an internal voltage generator230, an internal voltage driver240, and a voltage compensation unit250.

The reference voltage generator210may receive a source voltage from the source voltage supplier of the semiconductor memory control unit to generate a reference voltage Vref.

The voltage regulation controller220may receive the voltage regulation command signal from the voltage regulation commander of the semiconductor memory control unit to generate a control signal. The control signal generated by the voltage regulation controller220may be a switching control signal, and may be an up/down or on/off signal. The voltage regulation controller220may be implemented in an analog method or may be implemented in a digital method.

The internal voltage generator230may receive a reference voltage from the reference voltage generator and receive the control signal from the voltage regulation controller to generate a peripheral circuit reference voltage VrefP, a cell array reference voltage VrefA, a data output reference voltage VrefQ, and a word line (WL) reference voltage VrefPP. Like the above, the internal voltage generator230may be configured as sub-internal voltage generators to generate various internal voltages.

The internal voltage driver240may receive and stabilize the peripheral circuit reference voltage VrefP, the cell array reference voltage VrefA, the data output reference voltage VrefQ, and the word line (WL) reference voltage VrefPP from the internal voltage generator to supply a peripheral circuit voltage VDDP, a cell array voltage VDDA, a data output voltage VDDQ, and a word line (WL) voltage VPP to the DRAM array.

The voltage compensation unit250may receive each of the peripheral circuit voltage VDDP, the cell array voltage VDDA, the data output voltage VDDQ, and the word line (WL) voltage VPP by feedback ({circle around (a)}) to transmit a compensation command signal to the voltage regulation controller.

The various internal voltages refer to voltages required for the DRAM chip array100to operate, and may include VDDA, VDDP, VDDQ, and VPP. The VDDA may be used as a power supply for a cell array in a DRAM chip, the VDDP may be used as a power supply for a peripheral circuit in the DRAM chip, the VDDQ may be used as a power supply for data output, and VPP may be used as a power supply for a word line (WL). The internal voltage may include VBB. The VBB refers to a back-bias voltage.

The voltage compensation unit250provided in the semiconductor memory module1000may be provided inside or outside the PMIC. Even when the voltage compensation unit250is provided outside the PMIC, the voltage compensation unit250should be regarded as being included in the power management unit (PMU)200.

FIG.6is a schematic view for describing a voltage compensation unit according to still another embodiment. As shown in the drawing, the voltage compensation unit250may include a voltage measurer251, a voltage comparator252, and a voltage compensation commander253. Each of the voltage measurer251, the voltage comparator252, and the voltage compensation commander253may be configured as hardware or software.

The voltage measurer251may receive each of a peripheral circuit voltage VDDP, a cell array voltage VDDA, a data output voltage VDDQ, and a word line (WL) voltage VPP by feedback ({circle around (a)}) and measure a voltage value of each of the peripheral circuit voltage VDDP, the cell array voltage VDDA, the data output voltage VDDQ, and the word line (WL) voltage VPP to output a measurement voltage value.

The voltage comparator252may receive the measurement voltage value, and compare the measurement voltage value and a reference voltage value acquired based on the voltage regulation command signal received from the voltage regulation commander ({circle around (2)}) to output a comparison signal. The comparison signal may indicate information on a difference or a ratio of voltage values. For example, information of 1.2 V−1.22 V=−0.02 V may be indicated, and information of −0.02 V/1.20 V=−1.7% may also be indicated.

The voltage compensation commander253may receive the comparison signal and transmit the compensation command signal to the voltage regulation controller based on the comparison signal ({circle around (3)}). In the above example, regarding VPP, in the case of −0.02 V or −1.7%, a voltage up command to increase by +0.02 V or +1.7% may be given. Regarding VDDQ, in the case of +0.02 V or +1.7%, a voltage down command to decrease by 0.02 V or 1.7% may be given.

According to an embodiment, the voltage compensation commander253may receive the comparison signal and transmit the compensation command signal to the voltage regulation commander2200of the semiconductor memory control unit2000based on the comparison signal ({circumflex over (3)}′). Whether the voltage compensation commander253will transmit the compensation command signal to the voltage regulation controller220({circle around (3)}) or the voltage compensation commander253will transmit the compensation command signal to the voltage regulation commander2200({circumflex over (3)}′) may depend on information of the comparison signal. A specific operation followsFIG.3and a description thereof. Accordingly, as various internal voltages input to the DRAM chip array through a feedback circuit are individually measured and compensated, the internal voltages may be accurately and stably supplied to the DRAM chip array.

In the disclosure, as a voltage (for example, VDDA) used in a dynamic random access memory (DRAM) array is not generated in the DRAM array, but is generated by an external power management unit and supplied to the DRAM array, voltage regulation is easy, and thus various voltages can be supplied to DRAM arrays for products such as servers, games, and mobile devices, or the like. Accordingly, the application range of products or applications can be expanded.

Further, since the voltage supplied to the DRAM array can be supplied by feedback from an output of the power management unit and sensed to be monitored and compensated, a stable and accurate voltage can be supplied to the DRAM array in real time.

As each of various types of voltages (for example, VDDP, VDDA, VDDQ, and VPP) used in the DRAM array is generated and controlled in the power management unit, it is more advantageous for expanding the application range of products or applications, and a volume of the DRAM array can be reduced.

Since the voltages input to the DRAM array are provided to a semiconductor memory control unit (BIOS) by feedback, it is advantageous for controlling and compensating the voltage.

The above description is an example of technical features of the disclosure, and those skilled in the art to which the disclosure pertains will be able to make various modifications and variations. Thus, the embodiments of the disclosure described above may be implemented separately or in combination with each other.

Therefore, the embodiments disclosed in the disclosure are not intended to limit the technical spirit of the disclosure, but to describe the technical spirit of the disclosure, and the scope of the technical spirit of the disclosure is not limited by these embodiments. The protection scope of the disclosure should be interpreted by the following claims, and it should be interpreted that all technical spirits within the equivalent scope are included in the scope of the disclosure.