Patent ID: 12190828

DESCRIPTION OF EMBODIMENTS

Embodiments will be described below with reference to the accompanying drawings. In a second embodiment and a third embodiment, only points different from those of a first embodiment will be mainly described, and description of points that are the same as those in the first embodiment will be omitted as appropriate. Note that the following description is based on the premise that i and j each represent an integer equal to or greater than 2. Further, in each of the following embodiments, an N-channel thin film transistor is used as a transistor, and thus a high level corresponds to an on level, and a low level corresponds to an off level.

1. First Embodiment

1.1 Overall Configuration

FIG.2is a block diagram illustrating the overall configuration of an organic electroluminescent (EL) display device according to a first embodiment. As illustrated inFIG.2, this organic EL display device includes a display control circuit100, a display portion200, a scanning-side drive circuit300, and a data-side drive circuit400. The scanning-side drive circuit300and the data-side drive circuit400are included in an organic EL display panel5including the display portion200. In the present embodiment, the scanning-side drive circuit300is monolithic. The data-side drive circuit400may be monolithic or may not be monolithic.

In the display portion200, i first scanning signal lines SCAN1(1) to SCAN1(i), i second scanning signal lines SCAN2(1) to SCAN2(i), i first light emission control lines EM1(1) to EM1(i), i second light emission control lines EM2(1) to EM2(i), and j data signal lines D(1) to D(j) are arranged. Each first scanning signal line SCAN1transmits a first scanning signal, each second scanning signal line SCAN2transmits a second scanning signal, each first light emission control line EM1transmits a first light emission control signal, and each second light emission control line EM2transmits a second light emission control signal. The display portion200is also provided with i×j pixel circuits20. Each of the i×j pixel circuits20corresponds to one of the i first scanning signal lines SCAN1(1) to SCAN1(i), one of the i second scanning signal lines SCAN2(1) to SCAN2(i), one of the i first light emission control lines EM1(1) to EM1(i), one of the i second light emission control lines EM2(1) to EM2(i), and one of the j data signal lines D(1) to D(j). The first scanning signal lines SCAN1(1) to SCAN1(i), the second scanning signal lines SCAN2(1) to SCAN2(i), the first light emission control lines EM1(1) to EM1(i), and the second light emission control lines EM2(1) to EM2(i) are typically parallel to each other. The first scanning signal lines SCAN1(1) to SCAN1(i) and the data signal lines D(1) to D(j) are orthogonal to each other. Hereinafter, as necessary, the first scanning signals supplied to the first scanning signal lines SCAN1(1) to SCAN1(i) are also denoted by reference signs SCAN1(1) to SCAN1(i), the second scanning signals supplied to the second scanning signal lines SCAN2(1) to SCAN2(i) are also denoted by reference signs SCAN2(1) to SCAN2(i), the first light emission control signals supplied to the first light emission control lines EM1(1) to EM1(i) are also denoted by reference signs EM1(1) to EM1(i), the second light emission control signals supplied to the second light emission control lines EM2(1) to EM2(i) are also denoted by reference signs EM2(1) to EM2(i), and the data signals supplied to the data signal lines D(1) to D(j) are also denoted by reference signs D(1) to D(j).

Furthermore, in the display portion200, power source lines (not illustrated) common to each of the pixel circuits20are also arranged. To be more specific, a power source line which supplies a high-level power supply voltage ELVDD for driving the organic EL element (hereinafter, referred to as a “high-level power source line”), a power source line which supplies a low-level power supply voltage ELVSS for driving the organic EL element (hereinafter, referred to as a “low-level power source line”), and a power source line which supplies an initialization voltage Vini (hereinafter, referred to as an “initialization power source line”) are disposed. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from a power source circuit (not illustrated). Note that the high-level power source line corresponds to a first power source line, and the low-level power source line corresponds to a second power source line.

Operations of the constituent elements illustrated inFIG.2will be described below. The display control circuit100receives an input image signal DIN and a timing signal group (such as a horizontal synchronization signal and a vertical synchronization signal) TG that are transmitted from the outside, and outputs a digital video signal DV, a control signal SCTL configured to control operations of the scanning-side drive circuit300, and a control signal DCTL configured to control operations of the data-side drive circuit400.

The scanning-side drive circuit300is connected to the first scanning signal lines SCAN1(1) to SCAN1(i), the second scanning signal lines SCAN2(1) to SCAN2(i), the first light emission control lines EM1(1) to EM1(i), and the second light emission control lines EM2(1) to EM2(i). On the basis of the control signal SCTL output from the display control circuit100, the scanning-side drive circuit300applies first scanning signals to the first scanning signal lines SCAN1(1) to SCAN1(i), applies second scanning signals to the second scanning signal lines SCAN2(1) to SCAN2(i), applies first light emission control signals to the first light emission control lines EM1(1) to EM1(i), and applies second light emission control signals to the second light emission control lines EM2(1) to EM2(i). Note that the scanning-side drive circuit300is also supplied with a high-level power supply voltage GVDD and a low-level power supply voltage GVSS for controlling the operations of each unit circuit described below. The detailed configuration and operations of the scanning-side drive circuit300will be described below.

The data-side drive circuit400is connected to the data signal lines D(1) to D(j). The data-side drive circuit400includes a j-bit shift register, a sampling circuit, a latch circuit, and j D/A converters, which are not illustrated. The shift register includes j registers cascade-connected to each other. The shift register sequentially transfers a start pulse included in the control signal DCTL from an input terminal (register of first stage) to an output terminal (register of last stage) on the basis of a clock signal included in the control signal DCTL. As a result, sampling pulses are output from respective stages of the shift register. The sampling circuit stores the digital video signal DV based on the sampling pulses. The latch circuit acquires and holds the digital video signals DV for one row stored in the sampling circuit in accordance with a latch strobe signal included in the control signal DCTL. The D/A converters are provided correspondingly to the respective data signal lines D(1) to D(j). The D/A converters convert the digital video signals DV held in the latch circuit into analog voltages. The converted analog voltages are simultaneously applied, as data signals, to all of the data signal lines D(1) to D(j).

With the data signals being applied to the data signal lines D(1) to D(j), the first scanning signals being applied to the first scanning signal lines SCAN1(1) to SCAN1(i), the second scanning signals being applied to the second scanning signal lines SCAN2(1) to SCAN2(i), the first light emission control signals being applied to the first light emission control lines EM1(1) to EM1(i), and the second light emission control signals being applied to the second light emission control lines EM2(1) to EM2(i) as described above, an image based on the input image signal DIN is displayed on the display portion200.

1.2 Configuration and Operations of Pixel Circuit

Next, a configuration of the pixel circuit20in the display portion200will be described. The pixel circuit20illustrated inFIG.3includes one organic EL element (organic light-emitting diode)21as the display element, six transistors T1to T6(a writing control transistor T1, a drive transistor T2, a threshold voltage compensation transistor T3, a power supply control transistor T4, a light emission control transistor T5, and an initialization transistor T6), and one holding capacitor Cst. In the present embodiment, the transistors T1to T6are thin film transistors including channel regions formed of oxide semiconductors (hereinafter referred to as “oxide TFTs”), and are N-channel transistors. As the oxide TFT, typically, a thin film transistor including a channel region formed of an oxide semiconductor including indium, gallium, zinc, and oxygen is employed. The holding capacitor Cst is a capacitance element including two electrodes (first electrode and second electrode).

In the writing control transistor T1, a control terminal is connected to the second scanning signal line SCAN2, a first conduction terminal is connected to the data signal line D, and a second conduction terminal is connected to a second conduction terminal of the drive transistor T2and a first conduction terminal of the light emission control transistor T5. In the drive transistor T2, a control terminal is connected to a second conduction terminal of the threshold voltage compensation transistor T3and a first electrode of the holding capacitor Cst, a first conduction terminal is connected to a first conduction terminal of the threshold voltage compensation transistor T3and a second conduction terminal of the power supply control transistor T4, and the second conduction terminal is connected to the second conduction terminal of the writing control transistor T1and the first conduction terminal of the light emission control transistor T5. In the threshold voltage compensation transistor T3, a control terminal is connected to the first scanning signal line SCAN1, the first conduction terminal is connected to the second conduction terminal of the power supply control transistor T4and the first conduction terminal of the drive transistor T2, and the second conduction terminal is connected to the control terminal of the drive transistor T2and the first electrode of the holding capacitor Cst.

In the power supply control transistor T4, a control terminal is connected to the second light emission control line EM2, a first conduction terminal is connected to the high-level power source line, and the second conduction terminal is connected to the first conduction terminal of the drive transistor T2and the first conduction terminal of the threshold voltage compensation transistor T3. In the light emission control transistor T5, a control terminal is connected to the first light emission control line EM1, the first conduction terminal is connected to the second conduction terminal of the writing control transistor T1and the second conduction terminal of the drive transistor T2, and a second conduction terminal is connected to a first conduction terminal of the initialization transistor T6, an anode terminal of the organic EL element21, and a second electrode of the holding capacitor Cst. In the initialization transistor T6, a control terminal is connected to the first scanning signal line SCAN1, the first conduction terminal is connected to the second conduction terminal of the light emission control transistor T5, the anode terminal of the organic EL element21, and the second electrode of the holding capacitor Cst, and a second conduction terminal is connected to the initialization power source line.

In the holding capacitor Cst, the first electrode is connected to the control terminal of the drive transistor T2and the second conduction terminal of the threshold voltage compensation transistor T3, and the second electrode is connected to the second conduction terminal of the light emission control transistor T5, the first conduction terminal of the initialization transistor T6, and the anode terminal of the organic EL element21. In the organic EL element21, the anode terminal is connected to the second conduction terminal of the light emission control transistor T5, the first conduction terminal of the initialization transistor T6, and the second electrode of the holding capacitor Cst, and a cathode terminal is connected to the low-level power source line. In the organic EL element21, the anode terminal corresponds to a first terminal, and the cathode terminal corresponds to a second terminal.

Note that, inFIG.3, a node connected to the first conduction terminal of the drive transistor T2, the first conduction terminal of the threshold voltage compensation transistor T3, and the second conduction terminal of the power supply control transistor T4is denoted by reference sign N1, a node connected to the control terminal of the drive transistor T2, the second conduction terminal of the threshold voltage compensation transistor T3, and the first electrode of the holding capacitor Cst is denoted by reference sign N2, and a node connected to the second conduction terminal of the light emission control transistor T5, the first conduction terminal of the initialization transistor T6, the anode terminal of the organic EL element21, and the second electrode of the holding capacitor Cst is denoted by reference sign N3.

In the present embodiment, pause driving (also referred to as intermittent driving or low-frequency driving) is employed to realize low power consumption. Pause driving is a driving method in which a drive period (refresh period) and a pause period (non-refresh period) are provided when the same image is continuously displayed, and a drive circuit is activated in the drive period and operations of the drive circuit are stopped in the pause period. In this way, in the pause period, the writing of the data signals D to all pixel circuits20is stopped throughout a period of one frame period or longer. Pause driving can be applied when the off-leak characteristics of the transistor in the pixel circuit20is favorable (off-leak current is small). Accordingly, as described above, for the transistors T1to T6in the pixel circuit20according to the present embodiment, oxide TFTs are adopted.

Operations of the pixel circuit20illustrated inFIG.3will now be described. As described below, the first scanning signal lines SCAN1(1) to SCAN1(i) are driven one by one, but the second scanning signal lines SCAN2(1) to SCAN2(i), the first light emission control lines EM1(1) to EM1(i), and the second light emission control lines EM2(1) to EM2(i) are driven two by two. Accordingly, herein, n is an even number, and the focus is placed on the pixel circuit20in the (n−1)-th row and the pixel circuit20in the n-th row, which are two pixel circuits20adjacent to each other in an extending direction of the data signal line D. For convenience, the pixel circuit20in the (n−1)-th row is referred to as a “first pixel circuit,” and the pixel circuit20in the n-th row is referred to as a “second pixel circuit.”

First, the operations of the pixel circuit20in the drive period will be described with reference to a timing chart illustrated inFIG.4. Note that, inFIG.4, lengths of the periods during which each signal is maintained at a high level or a low level are not exactly illustrated (the same applies to other drawings illustrating timing charts). Data writing step is realized by the operations in this drive period.

At a time point immediately before time t01, the first scanning signal SCAN1(n−1), the first scanning signal SCAN1(n), the second scanning signal SCAN2(n−1), and the second scanning signal SCAN2(n) are at a low level, and the first light emission control signal EM1(n−1), the first light emission control signal EM1(n), the second light emission control signal EM2(n−1), and the second light emission control signal EM2(n) are at a high level. At this time, in the first pixel circuit and the second pixel circuit, the writing control transistor T1, the threshold voltage compensation transistor T3, and the initialization transistor T6are in an off state, and the power supply control transistor T4and the light emission control transistor T5are in an on state. Accordingly, the organic EL element21emits light in accordance with the magnitude of the drive current.

At time t01, the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) change from a high level to a low level. This places the light emission control transistor T5in the first pixel circuit and the second pixel circuit in an off state. As a result, the supply of current to the organic EL element21is cut off, switching the organic EL element21off.

At time t02, the first scanning signal SCAN1(n−1) changes from a low level to a high level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the first pixel circuit in an on state. At this time, the power supply control transistor T4is maintained in an on state. From the above, in the first pixel circuit, the high-level power supply voltage ELVDD is supplied to the node N2, and the initialization voltage Vini is supplied to the node N3. As a result, in the first pixel circuit, a holding voltage of the holding capacitor Cst and an anode voltage of the organic EL element21are initialized.

At time t03, the first scanning signal SCAN1(n−1) changes from a high level to a low level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the first pixel circuit in an off state.

At time t04, the first scanning signal SCAN1(n) changes from a low level to a high level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the second pixel circuit in an on state. At this time, the power supply control transistor T4is maintained in an on state. From the above, in the second pixel circuit, the high-level power supply voltage ELVDD is supplied to the node N2, and the initialization voltage Vini is supplied to the node N3. As a result, in the second pixel circuit, the holding voltage of the holding capacitor Cst and the anode voltage of the organic EL element21are initialized.

At time t05, the first scanning signal SCAN1(n) changes from a high level to a low level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the second pixel circuit in an off state. Further, at time t05, the second light emission control signal EM2(n−1) and the second light emission control signal EM2(n) change from a high level to a low level. This places the power supply control transistor T4in the first pixel circuit and the second pixel circuit in an off state.

At time t06, the second scanning signal SCAN2(n−1) and the second scanning signal SCAN2(n) change from a low level to a high level. This places the writing control transistor T1in the first pixel circuit and the second pixel circuit in an on state.

At time t07, the first scanning signal SCAN1(n−1) changes from a low level to a high level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the first pixel circuit in an on state. At this time, the power supply control transistor T4and the light emission control transistor T5are in an off state. From the above, in the first pixel circuit, the data signal D is supplied to the node N2via the writing control transistor T1, the drive transistor T2, and the threshold voltage compensation transistor T3, and the initialization voltage Vini is supplied to the node N3via the initialization transistor T6. As a result, in the first pixel circuit, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2. Note that, inFIG.4, a portion in which the data signal D is a voltage for the first pixel circuit is denoted by reference sign61.

At time t08, the first scanning signal SCAN1(n−1) changes from a high level to a low level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the first pixel circuit in an off state.

At time t09, the first scanning signal SCAN1(n) changes from a low level to a high level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the second pixel circuit in an on state. At this time, the power supply control transistor T4and the light emission control transistor T5are in an off state. From the above, in the second pixel circuit, the data signal D is supplied to the node N2via the writing control transistor T1, the drive transistor T2, and the threshold voltage compensation transistor T3, and the initialization voltage Vini is supplied to the node N3via the initialization transistor T6. As a result, in the second pixel circuit, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2. Note that, inFIG.4, a portion in which the data signal D is a voltage for the second pixel circuit is denoted by reference sign62.

At time t10, the first scanning signal SCAN1(n) changes from a high level to a low level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the second pixel circuit in an off state.

At time t11, the second scanning signal SCAN2(n−1) and the second scanning signal SCAN2(n) change from a high level to a low level. This places the writing control transistor T1in the first pixel circuit and the second pixel circuit in an off state.

At time t12, the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) change from a low level to a high level. This places the light emission control transistor T5in the first pixel circuit and the second pixel circuit in an on state. At this time, the power supply control transistor T4is maintained in an off state. Accordingly, in the first pixel circuit and the second pixel circuit, the organic EL element21is maintained in an off state.

At time t13, the second light emission control signal EM2(n−1) and the second light emission control signal EM2(n) change from a low level to a high level. This places the power supply control transistor T4in the first pixel circuit and the second pixel circuit in an on state. As a result, in the first pixel circuit and the second pixel circuit, a drive current corresponding to the charged voltage (holding voltage) of the holding capacitor Cst is supplied to the organic EL element21, and the organic EL element21emits light in accordance with the magnitude of the drive current. Subsequently, in the first pixel circuit and the second pixel circuit, the organic EL element21emits light throughout the period until the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) next change from a high level to a low level.

Next, the operations of the pixel circuit20in the pause period will be described with reference to a timing chart illustrated inFIG.5. Note that, throughout the pause period, an anode reset voltage (voltage for initializing the anode voltage of the organic EL element21) is applied to the data signal line D. In the present embodiment, the low-level power supply voltage ELVSS is applied to the data signal line D as the anode reset voltage. Further, throughout the pause period, the first scanning signal SCAN1(n−1) and the first scanning signal SCAN1(n) are maintained at a low level, and the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) are maintained at a high level. The pause step is realized by the operations in the pause period.

At a time point immediately before time t21, in the first pixel circuit and the second pixel circuit, the organic EL element21emits light in accordance with the magnitude of the drive current similarly to the time point immediately before time t01(refer toFIG.4) in the drive period.

At time t21, the second light emission control signal EM2(n−1) and the second light emission control signal EM2(n) change from a high level to a low level. This places the power supply control transistor T4in the first pixel circuit and the second pixel circuit in an off state. As a result, in the first pixel circuit and the second pixel circuit, the supply of current to the organic EL element21is cut off, switching the organic EL element21off.

At time t22, the second scanning signal SCAN2(n−1) and the second scanning signal SCAN2(n) change from a low level to a high level. This places the writing control transistor T1in the first pixel circuit and the second pixel circuit in an on state. At this time, the light emission control transistor T5is in an on state, and the low-level power supply voltage ELVSS is applied to the data signal line D as described above. From the above, the low-level power supply voltage ELVSS is supplied to the node N3via the writing control transistor T1and the light emission control transistor T5. As a result, in the first pixel circuit and the second pixel circuit, the anode voltage of the organic EL element21is initialized.

At time t23, the second scanning signal SCAN2(n−1) and the second scanning signal SCAN2(n) change from a high level to a low level. This places the writing control transistor T1in the first pixel circuit and the second pixel circuit in an off state.

At time t24, the second light emission control signal EM2(n−1) and the second light emission control signal EM2(n) change from a low level to a high level. This places the power supply control transistor T4in the first pixel circuit and the second pixel circuit in an on state. As a result, in the first pixel circuit and the second pixel circuit, a drive current corresponding to the charged voltage of the holding capacitor Cst is supplied to the organic EL element21, and the organic EL element21emits light in accordance with the magnitude of the drive current. Subsequently, in the first pixel circuit and the second pixel circuit, the organic EL element21emits light throughout the period until the second light emission control signal EM2(n−1) and the second light emission control signal EM2(n) next change from a high level to a low level. In the pause period, the threshold voltage compensation transistor T3is maintained in an off state, and thus the potential of the node N2does not change. Accordingly, the charged voltage of the holding capacitor Cst is equal to the voltage charged in the holding capacitor Cst on the basis of the data signal D in the previous drive period.

1.3 Schematic Configuration of Scanning-Side Drive Circuit

FIG.1is a block diagram illustrating a schematic configuration of the scanning-side drive circuit300in the present embodiment. The scanning-side drive circuit300is constituted by a first scanning signal line drive circuit31, a second scanning signal line drive circuit32, a first light emission control line drive circuit33, and a second light emission control line drive circuit34. The first scanning signal line drive circuit31applies the first scanning signals SCAN1to the first scanning signal lines, the second scanning signal line drive circuit32applies the second scanning signals SCAN2to the second scanning signal lines, the first light emission control line drive circuit33applies the first light emission control signals EM1to the first light emission control lines, and the second light emission control line drive circuit34applies the second light emission control signals EM2to the second light emission control lines.

The first scanning signal line drive circuit31is constituted by a shift register including unit circuits310equal in number to a number of the first scanning signal lines SCAN1. That is, each unit circuit included in the shift register constituting the first scanning signal line drive circuit31corresponds to one first scanning signal line SCAN1. Accordingly, the i first scanning signal lines SCAN1(1) to SCAN1(i) are driven one by one by the first scanning signal line drive circuit31.

The second scanning signal line drive circuit32is constituted by a shift register including unit circuits320equal in number to half a number of the second scanning signal lines SCAN2. That is, each unit circuit included in the shift register constituting the second scanning signal line drive circuit32corresponds to two second scanning signal lines SCAN2. Accordingly, the i second scanning signal lines SCAN2(1) to SCAN2(i) are driven two by two by the second scanning signal line drive circuit32.

The first light emission control line drive circuit33is constituted by a shift register including unit circuits330equal in number to half a number of the first light emission control lines EM1. That is, each unit circuit included in the shift register constituting the first light emission control line drive circuit33corresponds to two first light emission control lines EM1. Accordingly, the i first light emission control lines EM1(1) to EM1(i) are driven two by two by the first light emission control line drive circuit33.

The second light emission control line drive circuit34is constituted by a shift register including unit circuits340equal in number to half a number of the second light emission control lines EM2. That is, each unit circuit included in the shift register constituting the second light emission control line drive circuit34corresponds to two second light emission control lines EM2. Accordingly, the i second light emission control lines EM2(1) to EM2(i) are driven two by two by the second light emission control line drive circuit34.

1.4 First Scanning Signal Line Drive Circuit

1.4.1 Configuration of Shift Register

FIG.6is a block diagram illustrating a configuration of the first scanning signal line drive circuit31. The first scanning signal line drive circuit31is constituted by a shift register including i stages (i unit circuits310) corresponding to the i first scanning signal lines SCAN1(1) to SCAN1(i) on a one-to-one basis. Note thatFIG.6illustrates only the unit circuits310(n−1),310(n),310(n+1), and310(n+2) of the (n−1)th stage, the n-th stage, the (n+1)-th stage, and the (n+2)-th stage, where n is an even number.

The shift register constituting the first scanning signal line drive circuit31is supplied with a clock signal S1CK1, a clock signal S1CK2, a start pulse S1SP (not illustrated inFIG.6), the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS.

Each unit circuit310includes input terminals for respectively receiving a clock signal CKA1, a clock signal CKA2, a set signal SA, the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS, and an output terminal for outputting an output signal OUTA.

The unit circuits310at odd-numbered stages are supplied with the clock signal S1CK1as the clock signal CKA1, and are supplied with the clock signal S1CK2as the clock signal CKA2. The unit circuits310at even-numbered stages are supplied with the clock signal S1CK2as the clock signal CKA1, and are supplied with the clock signal S1CK1as the clock signal CKA2. The high-level power supply voltage GVDD and the low-level power supply voltage GVSS are commonly supplied to all unit circuits310. Further, the unit circuit310at each stage is supplied with the output signal OUTA from the unit circuit310of the preceding stage as the set signal SA. However, a unit circuit310(1) at the first stage is supplied with the start pulse S1SP as the set signal SA. The output signal OUTA from the unit circuit310at each stage is supplied to the corresponding first scanning signal line SCAN1as the first scanning signal and to the unit circuit310of the next stage as the set signal SA.

1.4.2 Configuration of Unit Circuit

FIG.7is a circuit diagram illustrating a configuration of the unit circuit310. As illustrated inFIG.7, the unit circuit310includes eight transistors M11to M18and two capacitors C11, C12. The transistors M11to M18are N-channel type oxide TFTs. Note that, inFIG.7, the output terminal outputting the output signal OUTA is denoted by reference sign319.

InFIG.7, a node connected to a first conduction terminal of the transistor M11, a second conduction terminal of the transistor M12, a control terminal of the transistor M13, and a first conduction terminal of the transistor M16is denoted by reference sign NA1, a node connected to a second conduction terminal of the transistor M11and a first conduction terminal of the transistor M14is denoted by reference sign NA2, a node connected to a second conduction terminal of the transistor M16, a control terminal of the transistor M18, and a first electrode of the capacitor C12is denoted by reference sign NA3, and a node connected to a first conduction terminal of the transistor M13, a control terminal of the transistor M14, a second conduction terminal of the transistor M15, a control terminal of a transistor M17, and a first electrode of the capacitor C11is denoted by the reference sign NA4.

The unit circuit310includes three control circuits311to313and one output circuit314. The control circuit311includes the transistor M12. The control circuit312includes the transistor M13and the transistor M15. The control circuit313includes the transistor M11and the transistor M14. The output circuit314includes the transistor M17, the transistor M18, the capacitor C11, and the capacitor C12.

In the transistor M11, a control terminal is supplied with the clock signal CKA2, the first conduction terminal is connected to the node NA1, and the second conduction terminal is connected to the node NA2. In the transistor M12, a control terminal is supplied with the clock signal CKA1, a first conduction terminal is supplied with the set signal SA, and the second conduction terminal is connected to the node NA1. In the transistor M13, the control terminal is connected to the node NA1, the first conduction terminal is connected to the node NA4, and a second conduction terminal is supplied with the clock signal CKA1. In the transistor M14, a control terminal is connected to the node NA4, the first conduction terminal is connected to the node NA2, and a second conduction terminal is supplied with the low-level power supply voltage GVSS.

In the transistor M15, a control terminal is supplied with the clock signal CKA1, a first conduction terminal is supplied with the high-level power supply voltage GVDD, and the second conduction terminal is connected to the node NA4. In the transistor M16, a control terminal is supplied with the high-level power supply voltage GVDD, the first conduction terminal is connected to the node NA1, and the second conduction terminal is connected to the node NA3. In the transistor M17, the control terminal is connected to the node NA4, a first conduction terminal is connected to the output terminal319, and a second conduction terminal is connected to the low-level power supply voltage GVSS. In the transistor M18, the control terminal is connected to the node NA3, a first conduction terminal is supplied with the clock signal CKA2, and a second conduction terminal is connected to the output terminal319.

In the capacitor C11, the first electrode is connected to the control terminal of the transistor M17and a second electrode is connected to the second conduction terminal of the transistor M17. In the capacitor C12, the first electrode is connected to the control terminal of the transistor M18and a second electrode is connected to the second conduction terminal of the transistor M18.

1.4.3 Operations of Unit Circuit

Operations of the unit circuit310will now be described with reference toFIG.8. At a time point immediately before time t31, potentials of the node NA1, the node NA2, and the node NA3are at a low level, a potential of the node NA4is at a high level, and the output signal OUTA is at a low level.

At time t31, the clock signal CKA1changes from a low level to a high level. This places the transistor M12in an on state. Further, at time t31, the set signal SA changes from a low level to a high level. This increases the potential of the node NA1. At this time, the transistor M16is in an on state and, in association with the rise in the potential of the node NA1, the potential of the node NA3also rises. As a result, the transistor M18is placed in an on state. However, the clock signal CKA2is maintained at a low level, and thus the output signal OUTA is maintained at a low level. Further, although the transistor M13and the transistor M15are placed in an on state, the potential of the node NA4is maintained at a high level because the clock signal CKA1is at a high level.

At time t32, the clock signal CKA1changes from a high level to a low level. This places the transistor M12and the transistor M15in an off state. At this time, the transistor M13is maintained in an on state and the clock signal CKA1is at a low level, and thus the potential of the node NA4changes from a high level to a low level. As a result, the transistor M14and the transistor M17are placed in an off state. Further, at time t32, the set signal SA changes from a high level to a low level.

At time t33, the clock signal CKA2changes from a low level to a high level. At this time, the transistor M18is in an on state, and thus the potential of the output terminal319(potential of the output signal OUTA) rises along with the rise of the potential of the first conduction terminal of the transistor M18. In association, the potential of the third node NA3further rises via the capacitor C12. As a result, a large voltage is applied to the control terminal of the transistor M18, and the potential of the output signal OUTA rises to a level sufficient to place the threshold voltage compensation transistor T3and the initialization transistor T6(refer toFIG.3) being connection destinations of the output terminal319in an on state. Note that, in the period from time t33to time t34, the potential of the node NA3becomes higher than the potential of the high-level power supply voltage GVDD. However, because the transistor M16is placed in an off state, the potential of the node NA1does not change. This prevents a high voltage from being applied to the first conduction terminal or the second conduction terminal of the transistors connected to the node NA1. Further, at time t33, the transistor M11is placed in an on state. At this time, the potential of the node NA1is at a high level, and thus the potential of the node NA2is also placed at a high level.

At time t34, the clock signal CKA2changes from a high level to a low level. At this time, the transistor M18is in an on state, and thus the potential of the output terminal319(potential of the output signal OUTA) decreases along with the decrease of the potential of the first conduction terminal of the transistor M18. When the potential of the output terminal319decreases, the potential of the node NA3also decreases via the capacitor C12.

At time t35, the clock signal CKA1changes from a low level to a high level. This places the transistor M12in an on state. At this time, the set signal SA is at a low level, and thus the potential of the node NA1changes to a low level. In association, the potential of the node NA3is also placed at a low level. With the potential of the node NA1being placed at a low level, the transistor M13changes to an off state. Further, at time t35, the clock signal CKA1is placed at a high level, placing the transistor M15in an on state. As a result, the potential of the node NA4is placed at a high level, and the transistor M14and the transistor M17are placed in an on state. With the transistor M14being placed in an on state, the potential of the node NA2is placed at a low level, and with the transistor M17being placed in an on state, the potential of the output terminal319(potential of the output signal OUTA) is maintained at a low level even if noise occurs.

Note that, in a period before time t31and a period after time t35, the transistor M11is placed in an on state when the clock signal CKA2is placed at a high level. At this time, the transistor M14is maintained in an on state and the potential of the node NA2is maintained at a low level and thus, even if noise occurs, the potential of the node NA1is reliably maintained at a low level. As a result, the occurrence of abnormal operation is suppressed.

1.5 Second Scanning Signal Line Drive Circuit

1.5.1 Configuration of Shift Register

FIG.9is a block diagram illustrating a configuration of the second scanning signal line drive circuit32. Given p=i/2, the second scanning signal line drive circuit32is constituted by a shift register composed of p stages (p unit circuits320). Each stage (each unit circuit320) corresponds to two second scanning signal lines SCAN2adjacent to each other. Note that, given k=n/2 and k is an odd number, only two unit circuits320(k) and320(k+1) corresponding to four second scanning signal lines SCAN2(n−1) to SCAN2(n+2) are illustrated inFIG.9.

A clock signal S2CK1, a clock signal S2CK2, a start pulse S2SP (not illustrated inFIG.9), the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS are supplied to the shift register constituting the second scanning signal line drive circuit32.

Each unit circuit320includes input terminals for respectively receiving a clock signal CKB1, a set signal SB, the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS, and an output terminal for outputting an output signal OUTB.

The unit circuits320at odd-numbered stages are supplied with the clock signal S2CK1as the clock signal CKB1. The unit circuits320at even-numbered stages are supplied with the clock signal S2CK2as the clock signal CKB1. The high-level power supply voltage GVDD and the low-level power supply voltage GVSS are commonly supplied to all unit circuits320. Further, the unit circuit320at each stage is supplied with the output signal OUTB from the unit circuit320of the preceding stage as the set signal SB. However, a unit circuit320(1) at the first stage is supplied with the start pulse S2SP as the set signal SB. The output signal OUTB from the unit circuit320at each stage is supplied to the corresponding two second scanning signal lines SCAN2as the second scanning signal and to the unit circuit320of the next stage as the set signal SB.

As described above, two second scanning signal lines SCAN2adjacent to each other form one pair, and the second scanning signals SCAN2having the same waveform are supplied to the two second scanning signal lines SCAN2forming each pair.

1.5.2 Configuration of Unit Circuit

FIG.10is a circuit diagram illustrating a configuration of the unit circuit320. As illustrated inFIG.10, the unit circuit320includes seven transistors M21to M27and three capacitors C21to C23. The transistors M21to M27are N-channel type oxide TFTs. Note that, inFIG.10, the output terminal outputting the output signal OUTB is denoted by reference sign329.

InFIG.10, a node connected to a second conduction terminal of the transistor M22, a control terminal of the transistor M24, and a first conduction terminal of the transistor M25is denoted by reference sign NB1, a node connected to a control terminal of the transistor M21, a first conduction terminal of the transistor M23, and a first electrode of the capacitor C23is denoted by reference sign NB2, a node connected to a second conduction terminal of the transistor M25, a control terminal of the transistor M27, and a first electrode of the capacitor C22is denoted by reference sign NB3, and a node connected to a second conduction terminal of the transistor M21, a first conduction terminal of the transistor M24, a control terminal of the transistor M26, and a first electrode of the capacitor C21is denoted by reference sign NB4.

The unit circuit320includes two control circuits321,322and one output circuit323. The control circuit321includes the transistor M22. The control circuit322includes the transistor M21, the transistor M23, the transistor M24, and the capacitor C23. The output circuit323includes the transistor M26, the transistor M27, the capacitor C21, and the capacitor C22.

In the transistor M21, the control terminal is connected to the node NB2, a first conduction terminal is supplied with the clock signal CKB1, and the second conduction terminal is connected to the node NB4. In the transistor M22, a control terminal is supplied with the clock signal CKB1, a first conduction terminal is supplied with the set signal SB, and the second conduction terminal is connected to the node NB1. In the transistor M23, a control terminal is supplied with the set signal SB, the first conduction terminal is connected to the node NB2, and a second conduction terminal is supplied with the low-level power supply voltage GVSS. In the transistor M24, the control terminal is connected to the node NB1, the first conduction terminal is connected to the node NB4, and a second conduction terminal is connected to the low-level power supply voltage GVSS.

In the transistor M25, a control terminal is supplied with the high-level power supply voltage GVDD, the first conduction terminal is connected to the node NB1, and the second conduction terminal is connected to the node NB3. In the transistor M26, the control terminal is connected to the node NB4, a first conduction terminal is connected to the output terminal329, and a second conduction terminal is connected to the low-level power supply voltage GVSS. In the transistor M27, the control terminal is connected to the node NB3, a first conduction terminal is supplied with the high-level power supply voltage GVDD, and a second conduction terminal is connected to the output terminal329.

In the capacitor C21, the first electrode is connected to the control terminal of the transistor M26and a second electrode is connected to the second conduction terminal of the transistor M26. In the capacitor C22, the first electrode is connected to the control terminal of the transistor M27and a second electrode is connected to the second conduction terminal of the transistor M27. In the capacitor C23, a first electrode is connected to the control terminal of the transistor M21and a second electrode is connected to the first conduction terminal of the transistor M21. Note that it is assumed that a capacitance of the capacitor C23is sufficiently larger than a parasitic capacitance of the node NB2.

In the present embodiment, a first transistor is realized by the transistor M21, a second transistor is realized by the transistor M22, a third transistor is realized by the transistor M23, a fourth transistor is realized by the transistor M24, a fifth transistor is realized by the transistor M25, a sixth transistor is realized by the transistor M26, a seventh transistor is realized by the transistor M27, a first capacitor is realized by the capacitor C21, a second capacitor is realized by the capacitor C22, a third capacitor is realized by the capacitor C23, a first internal node is realized by the node NB1, a second internal node is realized by the node NB2, a third internal node is realized by the node NB3, a fourth internal node is realized by the node NB4, and a control clock signal is realized by the clock signal CKB1.

1.5.3 Operations of Unit Circuit

Operations of the unit circuit320will now be described with reference toFIG.11. At a time point immediately before time t41, potentials of the node NB1, the node NB2, and the node NB3are at a low level, a potential of the node NB4is at a high level, and the output signal OUTB is at a low level.

At time t41, the set signal SB changes from a low level to a high level. At this time, the clock signal CKB1is maintained at a low level and the transistor M22is in an off state, and thus the potential of the node NB1is maintained at a low level. Note that, during the period in which the set signal SB is maintained at a high level (period from time t41to time t44), the transistor M23is maintained in an on state, and thus the potential of the node NB2is maintained at a low level regardless of the change in the level of the clock signal CKB1.

At time t42, the clock signal CKB1changes from a low level to a high level. This places the transistor M22in an on state. The set signal SB is maintained at a high level, and thus the potential of the node NB1rises. With this, the transistor M24is placed in an on state, and the potential of the node NB4changes from a high level to a low level. This places the transistor M26in an off state. Further, at time t42, the transistor M25is in an on state and, in association with the rise in the potential of the node NB1, the potential of the node NB3also rises. This places the transistor M27in an on state and causes the potential of the output terminal329(potential of the output signal OUTB) to rise. In association, the potential of the third node NB3further rises via the capacitor C22. As a result, a large voltage is applied to the control terminal of the transistor M27, and the potential of the output signal OUTB rises to a level sufficient to place the writing control transistor T1(refer toFIG.3) being a connection destination of the output terminal329to an on state.

At time t43, the clock signal CKB1changes from a high level to a low level. This places the transistor M22in an off state.

At time t44, the set signal SB changes from a high level to a low level. This places the transistor M23in an off state. At this time, the clock signal CKB1is maintained at a low level, and thus the potential of the node NB2is maintained at a low level.

At the time t45, the clock signal CKB1changes from a low level to a high level. This places the transistor M22in an on state. At this time, the set signal SB is at a low level, and thus the potential of the node NB1decreases. This places the transistor M24in an off state. Further, the transistor M23is in an off state, and thus by the clock signal CKB1changing from a low level to a high level, the potential of node NB2changes from a low level to a high level via the capacitor C23. This places the transistor M21in an on state, and changes the potential of the node NB4from a low level to a high level. This places the transistor M26in an on state. Further, in association with the decrease in the potential of the node NB1, the potential of the node NB3also decreases. This places the transistor M27in an off state. With the transistor M27placed in an off state and the transistor M26placed in an on state as described above, the potential of the output terminal329(potential of the output signal OUTB) changes to a low level.

Note that, in a period before time t41and a period after time t45, the transistor M21is placed in an on state each time the clock signal CKB1changes from a low level to a high level, and thus the potential of the node NB4is maintained at a high level. As a result, the transistor M26is maintained in an on state, and thus the output signal OUTB is reliably maintained at a low level even if noise occurs. As a result, the occurrence of abnormal operation is suppressed.

1.6 Light Emission Control Line Drive Circuit

1.6.1 Configuration of Shift Register

FIG.12is a block diagram illustrating a configuration of the first light emission control line drive circuit33. Similarly to the second scanning signal line drive circuit32, given p=i/2, the first light emission control line drive circuit33is constituted by a shift register composed of p stages (p unit circuits330). Each stage (each unit circuit330) corresponds to two first light emission control lines EM1adjacent to each other.

The shift register constituting the first light emission control line drive circuit33is supplied with a clock signal E1CK1, a clock signal E1CK2, a start pulse E1SP (not illustrated inFIG.12), the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS.

Each unit circuit330includes input terminals for respectively receiving a clock signal ECK, a set signal SE, the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS, and an output terminal for outputting an output signal EOUT.

The unit circuits330at odd-numbered stages are supplied with the clock signal E1CK1as the clock signal ECK. The unit circuits330at even-numbered stages are supplied with the clock signal E1CK2as the clock signal ECK. The high-level power supply voltage GVDD and the low-level power supply voltage GVSS are commonly supplied to all unit circuits330. Further, the unit circuit330at each stage is supplied with the output signal EOUT from the unit circuit330of the preceding stage as the set signal SE. However, a unit circuit330(1) at the first stage is supplied with the start pulse E1SP as the set signal SE. The output signal EOUT from the unit circuit330at each stage is supplied to the corresponding two first light emission control lines EM1as the first light emission control signal and to the unit circuit330of the next stage as the set signal SE.

As described above, two first light emission control lines EM1adjacent to each other form one pair, and the first light emission control signals EM1having the same waveform are supplied to the two first light emission control lines EM1forming each pair.

FIG.13is a block diagram illustrating a configuration of the second light emission control line drive circuit34. The shift register constituting the second light emission control line drive circuit34is supplied with a clock signal E2CK1, a clock signal E2CK2, a start pulse E2SP (not illustrated inFIG.13), the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS. Other points are the same as those of the first light emission control line drive circuit33, and thus a detailed description of the second light emission control line drive circuit34will be omitted.

1.6.2 Configuration of Unit Circuit

FIG.14is a circuit diagram illustrating a configuration of the unit circuit330. As illustrated inFIG.14, the unit circuit330includes seven transistors M31to M37and three capacitors C31to C33. As understood fromFIG.10andFIG.14, the unit circuits330included in the shift register constituting the first light emission control line drive circuit33have the same configuration as that of the unit circuits320included in the shift register constituting the second scanning signal line drive circuit32. The transistors M31to M37, the capacitors C31to C33, nodes NC1to NC4, an output terminal339, a control circuit331, a control circuit332, an output circuit333, the set signal SE, the clock signal ECK, and the output signal EOUT inFIG.14correspond to the transistors M21to M27, the capacitors C21to C23, the nodes NB1to NB4, the output terminal329, the control circuit321, the control circuit322, the output circuit323, the set signal SB, the clock signal CKB1, and the output signal OUTB inFIG.10, respectively. Accordingly, a detailed description of the configuration of the unit circuit330will be omitted.

1.6.3 Operations of Unit Circuit

Operations of the unit circuit330will be described with reference toFIG.15. At a time point immediately before time t51, potentials of the node NC1and the node NC3are at a high level, potentials of the node NC2and the node NC4are at a low level, and the output signal EOUT is at a high level.

At time t51, the set signal SE changes from a high level to a low level. This places the transistor M33in an off state. Further, at this time, the clock signal ECK is maintained at a low level and the transistor M32is in an off state, and thus the potential of the node NC1is maintained at a high level.

At time t52, the clock signal ECK changes from a low level to a high level. This places the transistor M32in an on state. At this time, the set signal SE is at a low level, and thus the potential of the node NC1decreases. This places the transistor M34in an off state. Further, the transistor M33is in an off state, and thus by the clock signal ECK changing from a low level to a high level, the potential of node NC2changes from a low level to a high level via the capacitor C33. This places the transistor M31in an on state, and changes the potential of the node NC4from a low level to a high level. This places the transistor M36in an on state. Further, in association with the decrease in the potential of the node NC1, the potential of the node NC3also decreases. This places the transistor M37in an off state. With the transistor M37placed in an off state and the transistor M36placed in an on state as described above, the potential of the output terminal339(potential of the output signal EOUT) changes to a low level.

At time t53, the clock signal ECK changes from a high level to a low level. This places the transistor M32in an off state. Further, the potential of the node NC2changes from a high level to a low level via the capacitor C33.

At time t54, the clock signal ECK changes from a low level to a high level. This places the transistor M32in an on state. At this time, the set signal SE is at a low level, and thus the potential of the node NC1is maintained at a low level. Further, the transistor M33is in an off state, and thus by the clock signal ECK changing from a low level to a high level, the potential of node NC2changes from a low level to a high level via the capacitor C33. With this, the transistor M31is placed in an on state, and the potential of the node NC4is maintained at high level. As a result, the transistor M36is maintained in an on state, and thus the output signal EOUT is reliably maintained at a low level even if noise occurs.

At time t55, the clock signal ECK changes from a high level to a low level. This places the transistor M32in an off state. Further, the potential of the node NC2changes from a high level to a low level via the capacitor C33.

At time t56, the set signal SE changes from a low level to a high level. At this time, the clock signal ECK is maintained at a low level and the transistor M32is in an off state, and thus the potential of the node NC1is maintained at a low level.

At time t57, the clock signal ECK changes from a low level to a high level. This places the transistor M32in an on state. The set signal SE is maintained at a high level, and thus the potential of the node NC1rises. With this, the transistor M34is placed in an on state, and the potential of the node NC4changes from a high level to a low level. This places the transistor M36in an off state. Further, at time t57, the transistor M35is in an on state and, in association with the rise in the potential of the node NC1, the potential of the node NC3also rises. This places the transistor M37in an on state and causes the potential of the output terminal339(potential of the output signal EOUT) to rise. In association, the potential of the third node NC3further rises via the capacitor C32. As a result, a large voltage is applied to the control terminal of the transistor M37, and the potential of the output signal EOUT rises to a level sufficient to cause the light emission control transistor T5(refer toFIG.3) being a connection destination of the output terminal339to change to an on state.

During the period following time t57, the potentials of the node NC1and the node NC3are maintained at a high level, the potentials of the node NC2and the node NC4are maintained at a low level, and the output signal EOUT is maintained at a high level.

1.7 Overall Operations

Overall operations will be described below. However, the operations described hereinafter are merely examples, and no such limitation is intended. Note that, in the following, a length of a period corresponding to z horizontal scanning periods with z as an integer is referred to as “zH.” For example, “8H” represents the length of a period corresponding to eight horizontal scanning periods.

First, overall operations in the drive period will be described with reference to a timing chart illustrated inFIG.16. A pulse width (length of the high-level period) of the start pulses S1SP, S2SP is 2H. For the clock signals S1CK1, S1CK2, the length of the high-level period is 0.5H and the length of the low-level period is 1.5H. For the clock signals S2CK1, S2CK2, the length of the high-level period is 0.5H, and the length of the low-level period is 3.5H. A pulse width (length of the low-level period) of the start pulses E1SP, E2SP is 8H. For the clock signals E1CK1, E1CK2, the length of the high-level period is 1H, and the length of the low-level period is 3H. For the clock signals E2CK1, E2CK2, the length of the high-level period is 1H, and the length of the low-level period is 3H.

The clock signal E1CK1changes from a low level to a high level after the start pulse E1SP changes from a high level to a low level, thereby changing the light emission control signals EM1(1), EM1(2) from a high level to a low level. This places the light emission control transistor T5in an off state, switching the organic EL element21off, in the pixel circuit20of the first row and the pixel circuit20of the second row. Note that, before the start pulse E1SP changes from a high level to a low level, the start pulse S1SP changes from a low level to a high level.

Subsequently, the clock signal S1CK1changes from a low level to a high level, thereby changing the first scanning signal SCAN1(1) from a low level to a high level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in an on state, and the holding voltage of the holding capacitor Cst and the anode voltage of the organic EL element21are initialized in the pixel circuit20of the first row. Furthermore, the clock signal S1CK2changes from a low level to a high level, thereby changing the first scanning signal SCAN1(2) from a low level to a high level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in an on state, and the holding voltage of the holding capacitor Cst and the anode voltage of the organic EL element21are initialized in the pixel circuit20of the second row. Note that, at the timing at which the first scanning signal SCAN1(2) changes from a low level to a high level, the start pulse E2SP changes from a high level to a low level.

Subsequently, the clock signal E2CK1changes from a low level to a high level, thereby changing the second light emission control signals EM2(1), EM2(2) from a high level to a low level. This places the power supply control transistor T4in the pixel circuit20of the first row and the pixel circuit20of the second row in an off state.

Subsequently, after the start pulse S2SP changes from a low level to a high level, the clock signal S2CK1changes from a low level to a high level, thereby changing the second scanning signals SCAN2(1), SCAN2(2) from a low level to a high level. This places the writing control transistor T1in the pixel circuit20of the first row and the pixel circuit20of the second row in an on state.

Subsequently, the start pulse S1SP changes from a low level to a high level again. Then, the clock signal S1CK1changes from a low level to a high level, thereby changing the first scanning signal SCAN1(1) from a low level to a high level. This places the threshold voltage compensation transistor T3and the initialization transistor T6in the pixel circuit20of the first row in an on state. At this time, in the pixel circuit20of the first row, the power supply control transistor T4and the light emission control transistor T5are in an off state. Accordingly, in the pixel circuit20of the first row, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2. Furthermore, the clock signal S1CK2changes from a low level to a high level, thereby changing the first scanning signal SCAN1(2) from a low level to a high level. As a result, in the pixel circuit20in the second row as well, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2.

On the basis of the operations of the clock signals S1CK1, S1CK2, S2CK1, S2CK2, E1CK1, E1CK2, E2CK1, and E2CK2, the same operations are sequentially performed in the pixel circuits20of the third to i-th rows. At this time, as understood fromFIG.16, the first scanning signal lines SCAN1are driven one by one, and the second scanning signal lines SCAN2, the first light emission control lines EM1, and the second light emission control lines EM2are driven two by two. With the first light emission control lines EM1and the second light emission control lines EM2being driven two by two, switching between the lighting state and the non-lighting state of the organic EL element21is performed two rows at a time. Further, the second scanning signal lines SCAN2are driven two by two, but the first scanning signal lines SCAN1are driven one by one, and thus initialization of the state of the pixel circuit20and writing of data to the pixel circuit20are performed one row at a time.

Next, overall operations in the pause period will be described with reference to a timing chart illustrated inFIG.17. The pulse width (length of the high-level period) of the start pulse S2SP is 2H. For the clock signals S2CK1, S2CK2, the length of the high-level period is 0.5H, and the length of the low-level period is 3.5H. For the clock signals E1CK1, E1CK2, the length of the high-level period is 1H, and the length of the low-level period is 3H. The pulse width (length of the low-level period) of the start pulses E2SP is 8H. For the clock signals E2CK1, E2CK2, the length of the high-level period is 1H, and the length of the low-level period is 3H. Note that the start pulse S1SP and the clock signals S1CK1, S1CK2are maintained at a low level throughout the pause period, and the start pulse E1SP is maintained at a high level throughout the pause period. Further, as described above, the anode reset voltage (low-level power supply voltage ELVSS in the present embodiment) is applied to all data signal lines D throughout the pause period.

The clock signal E2CK1changes from a low level to a high level after the start pulse E2SP changes from a high level to a low level, thereby changing the second light emission control signals EM2(1), EM2(2) from a high level to a low level. This places the power supply control transistor T4in an off state, switching the organic EL element21off, in the pixel circuit20of the first row and the pixel circuit20of the second row.

Subsequently, after the start pulse S2SP changes from a low level to a high level, the clock signal S2CK1changes from a low level to a high level, thereby changing the second scanning signals SCAN2(1), SCAN2(2) from a low level to a high level. This places the writing control transistor T1in the pixel circuit20of the first row and the pixel circuit20of the second row in an on state. At this time, in the pixel circuit20of the first row and in the pixel circuit20of the second row, the power supply control transistor T4is in an off state, but the light emission control transistor T5is in an on state. Further, an anode reset voltage is applied to the data signal line D. From the above, in the pixel circuit20of the first row and the pixel circuit20of the second row, the anode voltage of the organic EL element21is initialized.

On the basis of the operations of the clock signals S2CK1, S2CK2, E2CK1, and E2CK2, the same operations are sequentially performed in the pixel circuits20of the third to i-th rows. At this time, with the second scanning signal lines SCAN2and the second light emission control lines EM2being driven two by two, initialization of the anode voltage of the organic EL element21is performed two rows at a time.

1.8 Effect

According to the present embodiment, the second scanning signal line drive circuit32is constituted by the shift register composed of the unit circuits320equal in number to half the number of the second scanning signal lines SCAN2so that the second scanning signal lines SCAN2are driven two by two, the first light emission control line drive circuit33is constituted by the shift register composed of the unit circuits330equal in number to half the number of the first light emission control lines EM1so that the first light emission control lines EM1are driven two by two, and the second light emission control line drive circuit34is constituted by the shift register composed of the unit circuits340equal in number to half the number of the second light emission control lines EM2so that the second light emission control lines EM2are driven two by two. As a result, the area of the circuit region required around the periphery of the display portion200for driving the second scanning signal lines SCAN2, the first light emission control lines EM1, and the second light emission control lines EM2is reduced. That is, it is possible to reduce the area of the frame region of the organic EL display panel5. As described above, according to the present embodiment, frame narrowing of the organic EL display device including the pixel circuit20constituted by one organic EL element21, six N-channel transistors T1to T6, and one holding capacitor Cst as illustrated inFIG.3is realized.

1.9 Modified Examples

In the first embodiment described above, the second scanning signal lines SCAN2, the first light emission control lines EM1, and the second light emission control lines EM2are driven two by two. However, no such limitation is intended, and the second scanning signal lines SCAN2, the first light emission control lines EM1, and the second light emission control lines EM2may be driven three or more at a time. That is, the second scanning signal lines SCAN2, the first light emission control lines EM1, and the second light emission control lines EM2may be driven Q lines at a time, where Q is an integer of 2 or greater. However, it should be noted that as the value of Q increases, the length of a light emission period (period during which the organic EL element21is maintained in a state of emitting light in each pixel circuit20) decreases. Hereinafter, the case of “Q=3” is referred to as a first modified example, and the case of “Q=4” is referred to as a second modified example.

1.9.1 First Modified Example

FIG.18is a block diagram illustrating a schematic configuration of the scanning-side drive circuit300in a first modified example. The first scanning signal line drive circuit31is similar to that in the first embodiment described above. The second scanning signal line drive circuit32is constituted by a shift register including the unit circuits320equal in number to one-third the number of second scanning signal lines SCAN2. However,FIG.18illustrates only one unit circuit320. Each unit circuit included in the shift register constituting the second scanning signal line drive circuit32corresponds to three second scanning signal lines SCAN2. Accordingly, the i second scanning signal lines SCAN2(1) to SCAN2(i) are driven three by three by the second scanning signal line drive circuit32. The first light emission control line drive circuit33is constituted by a shift register including the unit circuits330equal in number to one-third the number of the first light emission control lines EM1. However,FIG.18illustrates only one unit circuit330. Each unit circuit included in the shift register constituting the first light emission control line drive circuit33corresponds to three first light emission control lines EM1. Accordingly, the i first light emission control lines EM1(1) to EM1(i) are driven three by three by the first light emission control line drive circuit33. The second light emission control line drive circuit34is constituted by a shift register including the unit circuits340equal in number to one-third the number of the second light emission control lines EM2. However,FIG.18illustrates only one unit circuit340. Each unit circuit included in the shift register constituting the second light emission control line drive circuit34corresponds to three second light emission control lines EM2. Accordingly, the i second light emission control lines EM2(1) to EM2(i) are driven three by three by the second light emission control line drive circuit34.

In the present modified example, in the drive period, as illustrated inFIG.19, in the period (period indicated by the arrow denoted by reference sign71) during which the first light emission control signals EM1(n−2), EM1(n−1), EM1(n), respectively applied to three first light emission control lines EM1driven collectively, are at a low level, and the second light emission control signals EM2(n−2), EM2(n−1), EM2(n), respectively applied to three second light emission control lines EM2driven collectively, are at a high level, the first scanning signal SCAN1(n−2), the first scanning signal SCAN1(n−1), and the first scanning signal SCAN1(n), respectively applied to three first scanning signal lines SCAN1corresponding to the (n−2)-th to n-th rows, are sequentially placed in an on state for a predetermined period each. As a result, in the pixel circuit20of the (n−2)-th row, the pixel circuit20of the (n−1)-th row, and the pixel circuit20of the n-th row, the holding voltage of the holding capacitor Cst is initialized and the anode voltage of the organic EL element21is initialized. Furthermore, in the drive period, as illustrated inFIG.19, during a part of a period during which the first light emission control signals EM1(n−2), EM1(n−1), and EM1(n) are at a low level, and the second light emission control signals EM2(n−2), EM2(n−1), and EM2(n) are at a low level, the second scanning signal SCAN2(n−2), the second scanning signal SCAN2(n−1), and the second scanning signal SCAN2(n), respectively applied to three second scanning signal lines SCAN2corresponding to the (n−2)-th to n-th rows, are maintained at a high level. In the period (period indicated by the arrow denoted by reference sign72) during which the second scanning signal SCAN2(n−2), the second scanning signal SCAN2(n−1), and the second scanning signal SCAN2(n) are maintained at a high level in this way, the first scanning signal SCAN1(n−2), the first scanning signal SCAN1(n−1), and the first scanning signal SCAN1(n) are sequentially placed in an on state again for a predetermined period each. As a result, in the pixel circuit20in the (n−2)-th row, the pixel circuit20in the (n−1)-th row, and the pixel circuit20in the n-th row, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2.

In the present modified example, in the pause period, as illustrated inFIG.20, during a part of a period during which the second light emission control signals EM2(n−2), EM2(n−1), and EM2(n), respectively applied to three second light emission control lines EM2driven collectively, are at a low level (period indicated by the arrow denoted by reference sign73), the second scanning signal SCAN2(n−2), the second scanning signal SCAN2(n−1), and the second scanning signal SCAN2(n), respectively applied to three second scanning signal lines SCAN2corresponding to the (n−2)-th to n-th rows, are maintained at a high level. As a result, in the pixel circuit20of the (n−2)-th row, the pixel circuit20of the (n−1)-th row, and the pixel circuit20of the n-th row, the anode voltage of the organic EL element21is initialized.

1.9.2 Second Modified Example

FIG.21is a block diagram illustrating a schematic configuration of the scanning-side drive circuit300in a second modified example. The first scanning signal line drive circuit31is similar to that in the first embodiment described above. The second scanning signal line drive circuit32is constituted by a shift register including the unit circuits320equal in number to one-fourth the number of second scanning signal lines SCAN2. However,FIG.21illustrates only one unit circuit320. Each unit circuit included in the shift register constituting the second scanning signal line drive circuit32corresponds to four second scanning signal lines SCAN2. Accordingly, the i second scanning signal lines SCAN2(1) to SCAN2(i) are driven four by four by the second scanning signal line drive circuit32. The first light emission control line drive circuit33is constituted by a shift register including the unit circuits330equal in number to one-fourth the number of the first light emission control lines EM1. However,FIG.21illustrates only one unit circuit330. Each unit circuit included in the shift register constituting the first light emission control line drive circuit33corresponds to four first light emission control lines EM1. Accordingly, the i first light emission control lines EM1(1) to EM1(i) are driven four by four by the first light emission control line drive circuit33. The second light emission control line drive circuit34is constituted by a shift register including the unit circuits340equal in number to one-fourth the number of the second light emission control lines EM2. However,FIG.21illustrates only one unit circuit340. Each unit circuit included in the shift register constituting the second light emission control line drive circuit34corresponds to four second light emission control lines EM2. Accordingly, the i second light emission control lines EM2(1) to EM2(i) are driven four by four by the second light emission control line drive circuit34.

In the present modified example, in the drive period, as illustrated inFIG.22, in the period (period indicated by the arrow denoted by reference sign74) during which the first light emission control signals EM1(n−3), EM1(n−2), EM1(n−1), EM1(n), respectively applied to four first light emission control lines EM1driven collectively, are at a low level, and the second light emission control signals EM2(n−3), EM2(n−2), EM2(n−1), EM2(n), respectively applied to four second light emission control lines EM2driven collectively, are at a high level, the first scanning signal SCAN1(n−3), the first scanning signal SCAN1(n−2), the first scanning signal SCAN1(n−1), and the first scanning signal SCAN1(n), respectively applied to the four first scanning signal lines SCAN1corresponding to the (n−3)-th to n-th rows, are sequentially placed in an on state for a predetermined period each. As a result, in the pixel circuit20of the (n−3)-th row, the pixel circuit20of the (n−2)-th row, the pixel circuit20of the (n−1)-th row, and the pixel circuit20of the n-th row, the holding voltage of the holding capacitor Cst is initialized and the anode voltage of the organic EL element21is initialized. Furthermore, in the drive period, as illustrated inFIG.22, during a part of a period during which the first light emission control signals EM1(n−3), EM1(n−2), EM1(n−1), and EM1(n) are at a low level, and the second light emission control signals EM2(n−3), EM2(n−2), EM2(n-1), and EM2(n) are at a low level, the second scanning signal SCAN2(n−3), the second scanning signal SCAN2(n−2), the second scanning signal SCAN2(n−1), and the second scanning signal SCAN2(n), respectively applied to four second scanning signal lines SCAN2corresponding to the (n−3)-th to n-th rows, are maintained at a high level. In the period during which the second scanning signal SCAN2(n−3), the second scanning signal SCAN2(n−2), the second scanning signal SCAN2(n−1), and the second scanning signal SCAN2(n) are maintained at a high level in this way (period indicated by the arrow denoted by reference sign75), the first scanning signal SCAN1(n−3), the first scanning signal SCAN1(n−2), the first scanning signal SCAN1(n−1), and the first scanning signal SCAN1(n) are sequentially placed in an on state again for a predetermined period each. As a result, in the pixel circuit20in the (n−3)-th row, the pixel circuit20in the (n−2)-th row, the pixel circuit20in the (n−1)-th row, and the pixel circuit20in the n-th row, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2.

In the present modified example, in the pause period, as illustrated inFIG.23, during a part of a period during which the second light emission control signals EM2(n−3), EM2(n−2), EM2(n−1), and EM2(n), respectively applied to four second light emission control lines EM2driven collectively, are at a low level (period indicated by the arrow denoted by reference sign76), the second scanning signal SCAN2(n−3), the second scanning signal SCAN2(n−2), the second scanning signal SCAN2(n−1), and the second scanning signal SCAN2(n), respectively applied to four second scanning signal lines SCAN2corresponding to the (n−3)-th to n-th rows, are maintained at a high level. As a result, in the pixel circuit20of the (n−3)-th row, the pixel circuit20of the (n−2)-th row, the pixel circuit20of the (n−1)-th row, and the pixel circuit20of the n-th row, the anode voltage of the organic EL element21is initialized.

2. Second Embodiment

2.1 Overview

In the first embodiment described above, the first light emission control line drive circuit33for driving the first light emission control lines EM1and the second light emission control line drive circuit34for driving the second light emission control lines EM2are separately provided. However, referring toFIG.16, the waveforms of the first light emission control signals EM1(n+1), EM1(n+2) are the same as the waveforms of the second light emission control signals EM2(n−1) and EM2(n). Herein, in the organic EL display device according to the present embodiment, a configuration is adopted in which the first light emission control lines EM1and the second light emission control lines EM2are driven by one shift register.

The overall configuration and operations of the organic EL display device are similar to those of the first embodiment described above (refer toFIG.2). The configuration and operations of the pixel circuit20are also similar to those of the first embodiment described above (refer toFIG.3). That is, the organic EL display device according to the present embodiment also includes the pixel circuit20constituted by one organic EL element21, six N-channel transistors T1to T6, and one holding capacitor Cst.

2.2 Schematic Configuration of Scanning-Side Drive Circuit

FIG.24is a block diagram illustrating a schematic configuration of the scanning-side drive circuit300in the present embodiment. The scanning-side drive circuit300is constituted by the first scanning signal line drive circuit31, the second scanning signal line drive circuit32, and a light emission control line drive circuit35. The first scanning signal line drive circuit31applies the first scanning signals SCAN1to the first scanning signal lines, the second scanning signal line drive circuit32applies the second scanning signals SCAN2to the second scanning signal lines, and the light emission control line drive circuit35applies the first light emission control signals EM1to the first light emission control lines and the second light emission control signal EM2to the second light emission control lines.

The first scanning signal line drive circuit31and the second scanning signal line drive circuit32have the same configurations as those of the first embodiment described above. Accordingly, the i first scanning signal lines SCAN1(1) to SCAN1(i) are driven one by one by the first scanning signal line drive circuit31, and the i second scanning signal lines SCAN2(1) to SCAN2(i) are driven two by two by the second scanning signal line drive circuit32.

The light emission control line drive circuit35is constituted by a shift register including unit circuits350equal in number to half the number of the first light emission control lines EM1. As illustrated inFIG.24, each unit circuit included in the shift register constituting the light emission control line drive circuit35corresponds to two second light emission control lines EM2and two first light emission control lines EM1. Accordingly, in the present embodiment, the i first light emission control lines EM1(1) to EM1(i) are driven two by two by the light emission control line drive circuit35, and the i second light emission control lines EM2(1) to EM2(i) are driven two by two by the light emission control line drive circuit35. That is, four light emission control lines (two first light emission control lines EM1and two second light emission control lines EM2) are collectively driven by each unit circuit included in the shift register constituting the light emission control line drive circuit35.

2.3 Light Emission Control Line Drive Circuit

FIG.25is a block diagram illustrating a configuration of the light emission control line drive circuit35. Given p=i/2, the light emission control line drive circuit35is constituted by a shift register composed of p stages (p unit circuits350). Each stage (each unit circuit350) corresponds to two second light emission control lines EM2adjacent to each other and two first light emission control lines EM1adjacent to each other. Given k=n/2 and k is an odd number, the unit circuit350(k) of the k-th stage corresponds to the second light emission control line EM2(n−1), the second light emission control line EM2(n), the first light emission control line EM1(n+1), and the first light emission control line EM1(n+2). Note thatFIG.25illustrates only the four unit circuits350(k) to350(k+3) corresponding to the eight second light emission control lines EM2(n−1) to EM2(n+6) and the eight first light emission control lines EM1(n+1) to EM1(n+8). Each unit circuit350has the configuration illustrated inFIG.14.

The shift register constituting the light emission control line drive circuit35is supplied with a clock signal ECK1, a clock signal ECK2, a start pulse ESP (not illustrated inFIG.25), the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS.

As described above, each unit circuit350has the configuration illustrated inFIG.14. That is, each unit circuit350includes input terminals for respectively receiving the clock signal ECK, the set signal SE, the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS, and an output terminal for outputting the output signal EOUT.

The unit circuits350at odd-numbered stages are supplied with the clock signal ECK1as the clock signal ECK. The unit circuits350at even-numbered stages are supplied with the clock signal ECK2as the clock signal ECK. The high-level power supply voltage GVDD and the low-level power supply voltage GVSS are commonly supplied to all unit circuits350. Further, the unit circuit350at each stage is supplied with the output signal EOUT from the unit circuit350of the preceding stage as the set signal SE. However, a unit circuit350(1) at the first stage is supplied with the start pulse ESP as the set signal SE. The output signal EOUT from the unit circuit350at each stage is supplied to the corresponding two second light emission control lines EM2as the second light emission control signal, supplied to the corresponding two first light emission control lines EM1as the first light emission control signal, and supplied to the unit circuit350of the next stage as the set signal SE.

As described above, four light emission control lines (two first light emission control lines EM1and two second light emission control lines EM2) are established as a set, and light emission control signals having the same waveform are supplied to the four first light emission control lines constituting each set. Specifically, given K as an integer, the unit circuit350(K) of the K-th stage included in the shift register constituting the light emission control line drive circuit35supplies the same signal to the (2K−1)-th second light emission control line EM2(2K−1), the 2K-th second light emission control line EM2(2K), the (2K+1)-th first light emission control line EM1(2K+1), and the (2K+2)-th first light emission control line EM1(2K+2), and thus drives the lines collectively.

2.4 Operations

Next, operations of the pixel circuit20according to the present embodiment will be described. However, the operations of the pixel circuit20during the drive period are the same as those of the first embodiment described above, and thus descriptions thereof will be omitted.

The operations of the pixel circuit20in the pause period will now be described with reference to a timing chart illustrated inFIG.26. Herein as well, focus will be placed on the first pixel circuit that is the pixel circuit20in the (n−1)-th row and the second pixel circuit that is the pixel circuit20in the n-th row. Note that, throughout the pause period, the low-level power supply voltage ELVSS is applied to the data signal line D as an anode reset voltage. Further, throughout the pause period, the first scanning signal SCAN1(n−1) and the first scanning signal SCAN1(n) are maintained at a low level.

At a time point immediately before time t61, the first scanning signal SCAN1(n−1), the first scanning signal SCAN1(n), the second scanning signal SCAN2(n−1), and the second scanning signal SCAN2(n) are at a low level, and the first light emission control signal EM1(n−1), the first light emission control signal EM1(n), the second light emission control signal EM2(n−1), and the second light emission control signal EM2(n) are at a high level. At this time, in the first pixel circuit and the second pixel circuit, the writing control transistor T1, the threshold voltage compensation transistor T3, and the initialization transistor T6are in an off state, and the power supply control transistor T4and the light emission control transistor T5are in an on state. Accordingly, the organic EL element21emits light in accordance with the magnitude of the drive current.

At time t61, the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) change from a high level to a low level. This places the light emission control transistor T5in the first pixel circuit and the second pixel circuit in an off state. As a result, the supply of current to the organic EL element21is cut off, switching the organic EL element21off.

At time t62, the second light emission control signal EM2(n−1) and the second light emission control signal EM2(n) change from a high level to a low level. This places the power supply control transistor T4in the first pixel circuit and the second pixel circuit in an off state.

At time t63, the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) change from a low level to a high level. This places the light emission control transistor T5in the first pixel circuit and the second pixel circuit in an on state. At this time, in the first pixel circuit and the second pixel circuit, the power supply control transistor T4is in an OFF state, and thus the organic EL element21is maintained in an OFF state.

At time t64, the second scanning signal SCAN2(n−1) and the second scanning signal SCAN2(n) change from a low level to a high level. This places the writing control transistor T1in the first pixel circuit and the second pixel circuit in an on state. At this time, the light emission control transistor T5is in an on state, and the low-level power supply voltage ELVSS is applied to the data signal line D as described above. From the above, the low-level power supply voltage ELVSS is supplied to the node N3via the writing control transistor T1and the light emission control transistor T5. As a result, in the first pixel circuit and the second pixel circuit, the anode voltage of the organic EL element21is initialized.

At time t65, the second scanning signal SCAN2(n−1) and the second scanning signal SCAN2(n) change from a high level to a low level. This places the writing control transistor T1in the first pixel circuit and the second pixel circuit in an off state.

At time t66, the second light emission control signal EM2(n−1) and the second light emission control signal EM2(n) change from a low level to a high level. This places the power supply control transistor T4in the first pixel circuit and the second pixel circuit in an on state. As a result, in the first pixel circuit and the second pixel circuit, a drive current corresponding to the charged voltage of the holding capacitor Cst is supplied to the organic EL element21, and the organic EL element21emits light in accordance with the magnitude of the drive current. Subsequently, in the first pixel circuit and the second pixel circuit, the organic EL element21emits light throughout the period until the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) next change from a high level to a low level.

In the present embodiment, the first light emission control line EM1and the second light emission control line EM2are driven by one shift register. Therefore, unlike the first embodiment described above, the first light emission control signal EM1cannot be maintained at a high level during the pause period. However, by driving the second scanning signal line SCAN2, the first light emission control line EM1, and the second light emission control line EM2as described above, it is possible to initialize the anode voltage of the organic EL element21in each pixel circuit20in the pause period.

2.5 Effect

According to the present embodiment, the first light emission control lines EM1and the second light emission control lines EM2arrayed in the display portion200are driven by one shift register including unit circuits equal in number to half the number of the first light emission control lines EM1(the number of the second light emission control lines EM2is equal to the number of the first light emission control lines EM1). As a result, the area of the circuit region required around the periphery of the display portion200in order to drive the first light emission control lines EM1and the second light emission control lines EM2is reduced compared with that of the first embodiment described above. From the above, with the organic EL display device including the pixel circuit20constituted by one organic EL element21, six N-channel transistors T1to T6, and one holding capacitor Cst, it is possible to reduce the frame area as compared with that of the first embodiment described above.

2.6 Modified Example

In the second embodiment described above as well, as in the modified example of the first embodiment described above, the second scanning signal lines SCAN2, the first light emission control lines EM1, and the second light emission control lines EM2may be driven Q lines at a time, where Q is an integer of 2 or greater. In this regard, in the present modified example, (Q×2) light emission control lines (Q first light emission control lines EM1and Q second light emission control lines EM2) are driven collectively by each unit circuit included in the shift register constituting the light emission control line drive circuit35.

For example, in the case of “Q=3,” the light emission control line drive circuit35is constituted by a shift register including the unit circuits350equal in number to one-third the number of the first light emission control lines EM1. Then, six light emission control lines (three first light emission control lines EM1and three second light emission control lines EM2) are established as a set, and light emission control signals having the same waveform are supplied to the six light emission control lines constituting each set. Specifically, given K as an integer, the unit circuit350(K) of the K-th stage included in the shift register constituting the light emission control line drive circuit35supplies the same signal to the (3K−2)-th second light emission control line EM2(3K−2), the (3K−1)-th second light emission control line EM2(3K−1), the 3K-th second light emission control line EM2(3K), the (3K+1)-th first light emission control line EM1(3K+1), the (3K+2)-th first light emission control line EM1(3K+2), and the (3K+3)-th first light emission control line EM1(3K+3), and thus drives the lines collectively.

Further, for example, in the case of “Q=4,” the light emission control line drive circuit35is constituted by a shift register including the unit circuits350equal in number to one-fourth the number of the first light emission control lines EM1. Then, eight light emission control lines (four first light emission control lines EM1and four second light emission control lines EM2) are established as a set, and light emission control signals having the same waveform are supplied to the eight light emission control lines constituting each set. Specifically, given K as an integer, the unit circuit350(K) of the K-th stage included in the shift register constituting the light emission control line drive circuit35supplies the same signal to the (4K−3)-th second light emission control line EM2(4K−3), the (4K−2)-th second light emission control line EM2(4K−2), the (4K−1)-th second light emission control line EM2(4K−1), the 4K-th second light emission control line EM2(4K), the (4K+1)-th first light emission control line EM1(4K+1), the (4K+2)-th first light emission control line EM1(4K+2), the (4K+3)-th first light emission control line EM1(4K+3), and the (4K+4)-th first light emission control line EM1(4K+4), and thus drives the lines collectively.

As described above, in the present modified example, the light emission control line drive circuit35is constituted by a shift register including the unit circuits350equal in number to one-Qth the number of the first light emission control lines EM1. Then, given K as an integer, the unit circuit350(K) of the K-th stage included in the shift register constituting the light emission control line drive circuit35collectively drives the (Q×K−(Q−1))-th to the (Q×K)-th second light emission control lines EM2, and the (Q×K+1)-th to the (Q×K+Q)-th first light emission control lines EM1.

3. Third Embodiment

3.1 Overview

In the first embodiment described above and the second embodiment described above, the threshold voltage compensation transistor T3and the initialization transistor T6are controlled by the same signal (first scanning signal SCAN1). However, no such limitation is intended, and a configuration in which the threshold voltage compensation transistor T3and the initialization transistor T6are controlled by different signals (configuration of the present embodiment) can also be employed. This will be described below.

In the present embodiment, the threshold voltage compensation transistor T3is controlled by the first scanning signal SCAN1, and the initialization transistor T6is controlled by the third scanning signal SCAN3. The third scanning signal SCAN3is transmitted by the third scanning signal line.

The overall configuration and operations of the organic EL display device according to the present embodiment are similar to those of the first embodiment described above except that i third scanning signal lines SCAN3(1) to SCAN3(I) are arranged in the display portion200(refer toFIG.2).

3.2. Configuration and Operations of Pixel Circuit

FIG.27is a circuit diagram illustrating a configuration of the pixel circuit20according to the present embodiment. The pixel circuit20according to the present embodiment, as in the first embodiment described above, includes one organic EL element21, six N-channel transistors T1to T6(the writing control transistor T1, the drive transistor T2, the threshold voltage compensation transistor T3, the power supply control transistor T4, the light emission control transistor T5, and the initialization transistor T6), and one holding capacitor Cst. In the present embodiment, a control terminal of the initialization transistor T6is connected to the third scanning signal line SCAN3. Other points are similar to those of the first embodiment described above.

Operations of the pixel circuit20illustrated inFIG.27will now be described. Note that, in the present embodiment as well, pause driving is adopted. Herein as well, focus will be placed on the first pixel circuit that is the pixel circuit20in the (n−1)-th row and the second pixel circuit that is the pixel circuit20in the n-th row.

First, the operations of the pixel circuit20in the drive period will be described with reference to a timing chart illustrated inFIG.28. Data writing step is realized by the operations in this drive period.

At a time point immediately before time t71, the first scanning signal SCAN1(n−1), the first scanning signal SCAN1(n), the second scanning signal SCAN2(n−1), the second scanning signal SCAN2(n), the third scanning signal SCAN3(n−1), and the third scanning signal SCAN3(n) are at a low level, and the first light emission control signal EM1(n−1), the first light emission control signal EM1(n), the second light emission control signal EM2(n−1), and the second light emission control signal EM2(n) are at a high level. At this time, in the first pixel circuit and the second pixel circuit, the writing control transistor T1, the threshold voltage compensation transistor T3, and the initialization transistor T6are in an off state, and the power supply control transistor T4and the light emission control transistor T5are in an on state. Accordingly, the organic EL element21emits light in accordance with the magnitude of the drive current.

At time t71, the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) change from a high level to a low level. This places the light emission control transistor T5in the first pixel circuit and the second pixel circuit in an off state. As a result, the supply of current to the organic EL element21is cut off, switching the organic EL element21off. Further, at time t71, the third scanning signal SCAN3(n−1) and the third scanning signal SCAN3(n) change from a low level to a high level. This places the initialization transistor T6in an on state and supplies the initialization voltage Vini to the node N3in the first pixel circuit and the second pixel circuit. As a result, in the first pixel circuit and the second pixel circuit, the anode voltage of the organic EL element21is initialized.

At time t72, the first scanning signal SCAN1(n−1) changes from a low level to a high level. This places the threshold voltage compensation transistor T3in the first pixel circuit in an on state. At this time, the power supply control transistor T4is maintained in an on state. Further, the initialization transistor T6is in an on state at time t71. From the above, in the first pixel circuit, the high-level power supply voltage ELVDD is supplied to the node N2with the initialization voltage Vini supplied to the node N3. As a result, in the first pixel circuit, the holding voltage of the holding capacitor Cst is initialized.

At time t73, the first scanning signal SCAN1(n−1) changes from a high level to a low level. This places the threshold voltage compensation transistor T3in the first pixel circuit in an off state.

At time t74, the first scanning signal SCAN1(n) changes from a low level to a high level. This places the threshold voltage compensation transistor T3in the second pixel circuit in an on state. At this time, the power supply control transistor T4is maintained in an on state. Further, the initialization transistor T6is in an on state at time t71. From the above, in the second pixel circuit, the high-level power supply voltage ELVDD is supplied to the node N2with the initialization voltage Vini supplied to the node N3. As a result, in the second pixel circuit, the holding voltage of the holding capacitor Cst is initialized.

At time t75, the first scanning signal SCAN1(n) changes from a high level to a low level. This places the threshold voltage compensation transistor T3in the second pixel circuit in an off state. Further, at time t75, the second light emission control signal EM2(n-1) and the second light emission control signal EM2(n) change from a high level to a low level. This places the power supply control transistor T4in the first pixel circuit and the second pixel circuit in an off state.

At time t76, the second scanning signal SCAN2(n−1) and the second scanning signal SCAN2(n) change from a low level to a high level. This places the writing control transistor T1in the first pixel circuit and the second pixel circuit in an on state.

At time t77, the first scanning signal SCAN1(n−1) changes from a low level to a high level. This places the threshold voltage compensation transistor T3in the first pixel circuit in an on state. At this time, the power supply control transistor T4and the light emission control transistor T5are in an off state. Further, the initialization voltage Vini is supplied to the node N3. From the above, in the first pixel circuit, the data signal D is supplied to the node N2via the writing control transistor T1, the drive transistor T2, and the threshold voltage compensation transistor T3. As a result, in the first pixel circuit, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2.

At time t78, the first scanning signal SCAN1(n−1) changes from a high level to a low level. This places the threshold voltage compensation transistor T3in the first pixel circuit in an off state.

At time t79, the first scanning signal SCAN1(n) changes from a low level to a high level. This places the threshold voltage compensation transistor T3in the second pixel circuit in an on state. At this time, the power supply control transistor T4and the light emission control transistor T5are in an off state. Further, the initialization voltage Vini is supplied to the node N3. From the above, in the second pixel circuit, the data signal D is supplied to the node N2via the writing control transistor T1, the drive transistor T2, and the threshold voltage compensation transistor T3. As a result, in the second pixel circuit, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2.

At time t80, the first scanning signal SCAN1(n) changes from a high level to a low level. This places the threshold voltage compensation transistor T3in the second pixel circuit in an off state.

At time t81, the second scanning signal SCAN2(n−1) and the second scanning signal SCAN2(n) change from a high level to a low level. This places the writing control transistor T1in the first pixel circuit and the second pixel circuit in an off state.

At time t82, the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) change from a low level to a high level. This places the light emission control transistor T5in the first pixel circuit and the second pixel circuit in an on state. At this time, the power supply control transistor T4is maintained in an off state. Accordingly, in the first pixel circuit and the second pixel circuit, the organic EL element21is maintained in an off state. Further, at time t82, the third scanning signal SCAN3(n−1) and the third scanning signal SCAN3(n) change from a high level to a low level. This places the initialization transistor T6in the first pixel circuit and the second pixel circuit in an off state.

At time t83, the second light emission control signal EM2(n−1) and the second light emission control signal EM2(n) change from a low level to a high level. This places the power supply control transistor T4in the first pixel circuit and the second pixel circuit in an on state. As a result, in the first pixel circuit and the second pixel circuit, a drive current corresponding to the charged voltage of the holding capacitor Cst is supplied to the organic EL element21, and the organic EL element21emits light in accordance with the magnitude of the drive current. Subsequently, in the first pixel circuit and the second pixel circuit, the organic EL element21emits light throughout the period until the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) next change from a high level to a low level.

Next, the operations of the pixel circuit20in the pause period will be described with reference to a timing chart illustrated inFIG.29. Note that, in the present embodiment, the data signal line D is maintained in a high impedance state throughout the pause period. The pause step is realized by the operations in the pause period.

At a time point immediately before time t91, the organic EL element21emits light in accordance with the magnitude of the drive current in the first pixel circuit and the second pixel circuit, similarly to the time point immediately before time t71(refer toFIG.28) in the drive period.

At time t91, the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) change from a high level to a low level. This places the light emission control transistor T5in the first pixel circuit and the second pixel circuit in an off state. As a result, the supply of current to the organic EL element21is cut off, switching the organic EL element21off. Further, at time t91, the third scanning signal SCAN3(n−1) and the third scanning signal SCAN3(n) change from a low level to a high level. This places the initialization transistor T6in an on state and supplies the initialization voltage Vini to the node N3in the first pixel circuit and the second pixel circuit. As a result, in the first pixel circuit and the second pixel circuit, the anode voltage of the organic EL element21is initialized.

At time t92, the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) change from a low level to a high level. This places the light emission control transistor T5in the first pixel circuit and the second pixel circuit in an on state. Further, at time t92, the third scanning signal SCAN3(n−1) and the third scanning signal SCAN3(n) change from a high level to a low level. This places the initialization transistor T6in the first pixel circuit and the second pixel circuit in an off state. At this time, the power supply control transistor T4is maintained in an on state. Accordingly, in the first pixel circuit and the second pixel circuit, a drive current corresponding to the charged voltage of the holding capacitor Cst is supplied to the organic EL element21, and the organic EL element21emits light in accordance with the magnitude of the drive current. Subsequently, in the first pixel circuit and the second pixel circuit, the organic EL element21emits light throughout the period until the first light emission control signal EM1(n−1) and the first light emission control signal EM1(n) next change from a high level to a low level.

3.3 Schematic Configuration of Scanning-Side Drive Circuit

FIG.30is a block diagram illustrating a schematic configuration of the scanning-side drive circuit300in the present embodiment. The scanning-side drive circuit300is constituted by the first scanning signal line drive circuit31, the second scanning signal line drive circuit32, a third scanning signal line drive circuit36, the first light emission control line drive circuit33, and the second light emission control line drive circuit34. The first scanning signal line drive circuit31applies the first scanning signals SCAN1to the first scanning signal lines, the second scanning signal line drive circuit32applies the second scanning signals SCAN2to the second scanning signal lines, the third scanning signal line drive circuit36applies the third scanning signals SCAN3to the third scanning signal lines, the first light emission control line drive circuit33applies the first light emission control signals EM1to the first light emission control lines, and the second light emission control line drive circuit34applies the second light emission control signals EM2to the second light emission control lines.

The first scanning signal line drive circuit31, the second scanning signal line drive circuit32, the first light emission control line drive circuit33, and the second light emission control line drive circuit34have the same configurations as those of the first embodiment described above. Accordingly, a detailed description of the configurations thereof will be omitted.

The third scanning signal line drive circuit36is constituted by a shift register including unit circuits360equal in number to half the number of the third scanning signal lines SCAN3. That is, each unit circuit included in the shift register constituting the third scanning signal line drive circuit36corresponds to two third scanning signal lines SCAN3. Accordingly, the i third scanning signal lines SCAN3(1) to SCAN3(i) are driven two by two by the third scanning signal line drive circuit36.

3.4 Third Scanning Signal Line Drive Circuit

FIG.31is a block diagram illustrating a configuration of the third scanning signal line drive circuit36. As in the second scanning signal line drive circuit32, given p=i/2, the third scanning signal line drive circuit36is constituted by a shift register composed of p stages (p unit circuits360). Each stage (each unit circuit360) corresponds to two third scanning signal lines SCAN3adjacent to each other.

As illustrated inFIG.31, the shift register constituting the third scanning signal line drive circuit36is supplied with a clock signal S3CK1, a clock signal S3CK2, a start pulse E3SP (not illustrated inFIG.31), the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS. Other points are the same as those of the second scanning signal line drive circuit32, and thus a detailed description of the third scanning signal line drive circuit36will be omitted.

3.5 Overall Operations

Overall operations will be described below. However, the operations described hereinafter are also merely examples, and no such limitation is intended.

First, overall operations in the drive period will be described with reference to a timing chart illustrated inFIG.32. A pulse width (length of the high-level period) of the start pulse S3SP is 5H. For the clock signals S3CK1, S3CK2, the length of the high-level period is 0.5H, and the length of the low-level period is 3.5H. The other signals are similar to those of the first embodiment described above.

The clock signal E1CK1changes from a low level to a high level after the start pulse E1SP changes from a high level to a low level, thereby changing the light emission control signals EM1(1), EM1(2) from a high level to a low level. This places the light emission control transistor T5in an off state, switching the organic EL element21off, in the pixel circuit20of the first row and the pixel circuit20of the second row. Further, after the start pulse S3SP changes from a low level to a high level, the clock signal S3CK1changes from a low level to a high level, thereby changing the third scanning signals SCAN3(1), SCAN3(2) from a low level to a high level. As a result, in the pixel circuit20of the first row and the pixel circuit20of the second row, the initialization transistor T6is placed in an on state and the anode voltage of the organic EL element21is initialized. In this example, the timing at which the light emission control signals EM1(1), EM1(2) change from a high level to a low level is the same as the timing at which the third scanning signals SCAN3(1), SCAN3(2) change from a low level to a high level. Note that, before the start pulse E1SP changes from a high level to a low level, the start pulse S1SP changes from a low level to a high level.

Subsequently, the clock signal S1CK1changes from a low level to a high level, thereby changing the first scanning signal SCAN1(1) from a low level to a high level. This places the threshold voltage compensation transistor T3in an on state, and initializes the holding voltage of the holding capacitor Cst in the pixel circuit20of the first row. Furthermore, the clock signal S1CK2changes from a low level to a high level, thereby changing the first scanning signal SCAN1(2) from a low level to a high level. This places the threshold voltage compensation transistor T3in an on state, and initializes the holding voltage of the holding capacitor Cst in the pixel circuit20of the second row. Note that, at the timing at which the first scanning signal SCAN1(2) changes from a low level to a high level, the start pulse E2SP changes from a high level to a low level.

Subsequently, the clock signal E2CK1changes from a low level to a high level, thereby changing the second light emission control signals EM2(1), EM2(2) from a high level to a low level. This places the power supply control transistor T4in the pixel circuit20of the first row and the pixel circuit20of the second row in an off state.

Subsequently, after the start pulse S2SP changes from a low level to a high level, the clock signal S2CK1changes from a low level to a high level, thereby changing the second scanning signals SCAN2(1), SCAN2(2) from a low level to a high level. This places the writing control transistor T1in the pixel circuit20of the first row and the pixel circuit20of the second row in an on state.

Subsequently, the start pulse S1SP changes from a low level to a high level again. Then, the clock signal S1CK1changes from a low level to a high level, changing the first scanning signal SCAN1(1) from a low level to a high level. This places the threshold voltage compensation transistor T3in an on state in the pixel circuit20of the first row. At this time, in the pixel circuit20in the first row, the power supply control transistor T4and the light emission control transistor T5are in an off state, and the initialization transistor T6is in an on state. Accordingly, in the pixel circuit20of the first row, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for the variation in the threshold voltage of the drive transistor T2. Furthermore, the clock signal S1CK2changes from a low level to a high level, thereby changing the first scanning signal SCAN1(2) from a low level to a high level and, in the pixel circuit20of the second row, charging the holding capacitor Cst with the voltage corresponding to the data signal D so as to compensate for the variation of the threshold voltage of the drive transistor T2.

On the basis of the operations of the clock signals S1CK1, S1CK2, S2CK1, S2CK2, S3CK1, S3CK2, E1CK1, E1CK2, E2CK1, and E2CK2, the same operations are sequentially performed in the pixel circuits20of the third to i-th rows. At this time, as understood fromFIG.32, the first scanning signal lines SCAN1are driven one by one, and the second scanning signal lines SCAN2, the third scanning signal lines SCAN3, the first light emission control lines EM1, and the second light emission control lines EM2are driven two by two. With the third scanning signal lines SCAN3, the first light emission control lines EM1and the second light emission control lines EM2being driven two by two, initialization of the anode voltage of the organic EL element21and switching between the lighting state and the non-lighting state of the organic EL element21are performed two rows at a time. Further, the second scanning signal lines SCAN2and the third scanning signal lines SCAN3are driven two by two, but the first scanning signal lines SCAN1are driven one by one, and thus initialization of the holding voltage of the holding capacitor Cst and writing of data to the pixel circuits20are performed one row at a time.

Next, overall operations in the pause period will be described with reference to the timing chart illustrated inFIG.33. A pulse width (length of the high-level period) of the start pulse S3SP is 5H. For the clock signals S3CK1, S3CK2, the length of the high-level period is 0.5H, and the length of the low-level period is 3.5H. A pulse width (length of the low-level period) of the start pulses E1SP is 8H. The clock signals S2CK1, S2CK2, E1CK1, E1CK2, E2CK1, and E2CK2are similar to those in the first embodiment described above. Note that the start pulses S1SP, S2SP and the clock signals S1CK1, S1CK2are maintained at a low level throughout the pause period, and the start pulse E2SP is maintained at a high level throughout the pause period. Further, as described above, all data signal lines D are maintained in the high-impedance state throughout the pause period.

The clock signal E1CK1changes from a low level to a high level after the start pulse E1SP changes from a high level to a low level, thereby changing the light emission control signals EM1(1), EM1(2) from a high level to a low level. This places the light emission control transistor T5in an off state, switching the organic EL element21off, in the pixel circuit20of the first row and the pixel circuit20of the second row. Further, after the start pulse S3SP changes from a low level to a high level, the clock signal S3CK1changes from a low level to a high level, thereby changing the third scanning signals SCAN3(1), SCAN3(2) from a low level to a high level. As a result, in the pixel circuit20of the first row and the pixel circuit20of the second row, the initialization transistor T6is placed in an on state and the anode voltage of the organic EL element21is initialized.

Subsequently, after the start pulse S3SP changes from a high level to a low level, the clock signal S3CK1changes from a low level to a high level, thereby changing the third scanning signals SCAN3(1), SCAN3(2) from a high level to a low level. This places the initialization transistor T6in the pixel circuit20of the first row and the pixel circuit20of the second row in an off state. Further, after the start pulse E1SP changes from a low level to a high level, the clock signal E1CK1changes from a low level to a high level, thereby changing the light emission control signals EM1(1), EM1(2) from a low level to a high level. This places the light emission control transistor T5in the pixel circuit20of the first row and the pixel circuit20of the second row in an on state. From the above, in the first pixel circuit and the second pixel circuit, a drive current in accordance with the charged voltage of the holding capacitor Cst is supplied to the organic EL element21, and the organic EL element21emits light in accordance with the magnitude of the drive current.

On the basis of the operations of the clock signals S3CK1, S3CK2, E1CK1, and E1CK2, the same operations are sequentially performed in the pixel circuits20of the third to i-th rows. At this time, with the third scanning signal lines SCAN3and the first light emission control lines EM1being driven two by two, initialization of the anode voltage of the organic EL element21is performed two rows at a time.

3.6 Effects

According to the present embodiment, as in the first embodiment described above, frame narrowing of the organic EL display device including the pixel circuit20(refer toFIG.27) constituted by one organic EL element21, six N-channel transistors T1to T6, and one holding capacitor Cst is realized.

3.7 Modified Example

In the third embodiment described above, the first light emission control line drive circuit33for driving the first light emission control lines EM1and the second light emission control line drive circuit34for driving the second light emission control lines EM2are separately provided. However, it is also possible to adopt a configuration in which the first light emission control lines EM1and the second light emission control lines EM2are driven by one shift register as in the second embodiment described above. That is, as illustrated inFIG.34, the light emission control line drive circuit35having the same configuration as that in the second embodiment described above may be provided instead of the first light emission control line drive circuit33and the second light emission control line drive circuit34.

Further, as in the modified example of the first embodiment described above, the second scanning signal lines SCAN2, the third scanning signal lines SCAN3, the first light emission control lines EM1, and the second light emission control lines EM2may be driven three or more at a time.

4. Other

Although the above-described respective embodiments (including the modified examples) have been described with the organic EL display devices having been exemplified, the embodiment is not limited to these devices. The disclosure contents described above can be applied to an inorganic EL display device, a quantum dot light-emitting diode (QLED) display device, or the like as long as the display device includes a display element driven by a current.

REFERENCE SIGNS LIST

5Organic EL display panel20Pixel circuit21Organic EL element31First scanning signal line drive circuit32Second scanning signal line drive circuit33First light emission control line drive circuit34Second light emission control line drive circuit35Light emission control line drive circuit36Third scanning signal line drive circuit100Display control circuit200Display portion300Scanning-side drive circuit310,320,330,340,350,360Unit circuit400Data-side drive circuitSCAN1First scanning signal line, first scanning signalSCAN2Second scanning signal line, second scanning signalSCAN3Third scanning signal line, third scanning signalEM1First light emission control line, first light emission control signalEM2Second light emission control line, second light emission control signalT1Writing control transistorT2Drive transistorT3Threshold voltage compensation transistorT4Power supply control transistorT5Light emission control transistorT6Initialization transistor