Patent ID: 12241931

DETAILED DESCRIPTION

As noted above, in an integrated circuit, toggle rate is a measure of the average number of times a signal changes value, thereby representing how much of a design is transitioning in any given capture clock cycle, the clock cycle representing the amount of time between like edges of two pulses of a signal. Toggles are induced by the changing state of the design, as register capturing new values which propagate through downstream logic.

Automatic test pattern generation (ATPG) testing is a process by which a machine generates a scan chain pattern for testing, with a sequence that will reveal particular errors, rather than having to create the test pattern sequence manually. ATPG helps determine an input sequence which, when applied to a digital circuit, propagates in an expected way—either unchanged or changed in a known way. A fault in the digital circuit design may be indicated if the input sequence emerges from testing with unexpected changes. However, in some cases, ATPG testing may cause a toggle rate in the integrated circuit that exceeds the functional toggle rate that may be expected during actual operation of the integrated circuit. If that excessive toggle rate exceeds the design specifications of the integrated circuit device, the testing may indicate a design failure, even though the failure conditions can never occur during actual operation. For example, too high of a toggle rate may cause a power droop—i.e., a voltage drop at locations in the integrated circuit—that would otherwise not occur during normal operation.

While parameters of the ATPG testing may be adjusted to limit the toggle rate of the integrated circuit design, using such adjustments to prevent false failures is dependent on intervention by the person carrying out the testing. For example, manual partitioning of clock domains is currently utilized to limit the toggle rate during testing of integrated circuit designs. However, such manual action of partitioning clock domains may be insufficient to guarantee that the design activity factor (which defines the limits within which the toggle rate should remain) will not be exceeded during the simulation of the scan chain pattern.

One way to control toggling of logic is to prevent registers from being clocked. A new value is captured every time a register is clocked. Preventing a register from being clocked would prevent the value stored in the register from changing, which in turn would prevent a value change from propagating downstream through the logic and causing additional toggling.

Therefore, in accordance with implementations of the subject matter of this disclosure, an integrated control gate may be added to an integrated circuit design ATPG testing. The integrated control gate determines when to allow clock tree segments to be active, thereby keeping the integrated circuit design within the design activity factor specification during testing by turning off a clock tree segments if keeping the segment active would result in excessive toggling.

The integrated control gate may be added to the actual integrated circuit device, and the actual device may be tested. During testing, the integrated control gate may be used to turn off clock segments as discussed above, and then not used during actual runtime operation of the integrated circuit device. However, ATPG pattern development and testing is frequently carried out as a simulation rather than using real devices, because a parallel testbench simulation can read the states of all registers simultaneously, which for a real device would be possible only if a probe point is provided for each register. With respect to the subject matter of this disclosure, observing the effect of adding and altering integrated control gates can more easily be performed in a simulation, as compared to the lengthy process of preparing a completely new design with added gates, and proceeding through the fabrication process to observe the results of adding those gates.

The subject matter of this disclosure may be better understood by reference toFIGS.1-6.

FIG.1is a flow diagram illustrating implementations of a method in accordance with the subject matter of this disclosure. Although it may theoretically be possible to test an actual fabricated device according to the methods described herein, such actual parallel testing, to test the values of a plurality of registers of the integrated circuit device, would require providing probe points in the device for each register in the scan chain to be read in parallel. Furthermore, providing the necessary probe points for such parallel testing, even if desired, may be difficult to achieve. Therefore, as described above, testing may be performed in software—e.g., as a simulation—to validate the design of integrated circuit device—from both functional and timing perspectives—prior to fabrication.

The testing process100begins at101, by determining the number of integrated clock gate (ICG) cells in the integrated circuit design, to make sure all the ICGs are cycled through during the simulation testing, as described below in further detail. Each ICG may be used for clock gating, to prevent clock propagation through an ICG when a low clock enable signal is applied to the ICG.

Once the number of ICGs is determined, the fanout of the first ICG is compared at102with a threshold number of registers, where the threshold number of registers is based on particular characteristics of the integrated circuit design, and may vary for different integrated circuit designs. If it is determined at102that the ICG fanout is greater than the threshold number of registers, the testing process100moves to103to limit the toggle rate as described below. Alternatively, if it is determined at102that the ICG fanout is less than or equal to the threshold number of registers, then at108, the process100checks to see if the respective fanouts of all ICGs have been compared to the threshold numbers of registers. If it is determined that all the ICGs have not been compared with the threshold number of registers, then at109, the process increments to the next ICG and returns to102to compare the fanout of the next ICG with the threshold number of registers.

As mentioned above, if it is determined at102that the ICG fanout is greater than the threshold number of registers, then at103, it is determined whether the ICG fanout exceeds a maximum number of registers, rendering the fanout too large for one ICG, thereby necessitating a need to clone the ICG—i.e., to add an additional ICG. The particular maximum number of registers that would make the fanout too large is based on particular characteristics of the integrated circuit design being tested and may differ for different integrated circuit designs. The process is handled differently, as described below, for situations where the fanout exceeds the maximum number of registers, as compared to situations where the fanout is between the threshold number of registers and the maximum number of registers.

Following a determination at103that the ICG fanout exceeds the maximum number of registers, the testing process100moves to104to clone the ICG. However, if it determined that the ICG fanout does not exceed the maximum number of registers, the testing process100checks at105whether the function enable path of the ICG is timing-critical. Testing process100provides two different solutions to limit the toggle rate based on the determination made at105regarding whether or not the function enable path of the ICG is timing-critical.

If the function enable path of the ICG is determined to be timing-critical, then at106, testing process100alters the clock input by adding a test-only ICG and a test point to the clock input of the ICG in order to limit the toggle rate. Further details regarding adding a test-only ICG and a test point as a clock input to the ICG are provided with reference toFIG.2below.

However, if, at105, it is determined that the function enable path of the ICG is not timing-critical, then at107, testing process100alters the function-enable input of the ICG, inserting a test point and an AND-gate in the enable path of the ICG. By altering the enable path of the ICG, testing process100effectively adds a control gate to the integrated circuit design which can control when clock tree segments are active, thereby controlling the clock tree activity of the integrated circuit design and keeping the integrated circuit design within the design activity factor specification during testing. Further details regarding inserting the test point and AND-gate in the enable path of the ICG are provided with reference toFIG.3below.

When it is determined that the function-enable path of the ICG is timing-critical, the testing process100is able to limit the toggle rate by adding a test-only ICG204and a test point as a clock signal input to the ICG208.FIG.2depicts an implementation of an ICG208undergoing testing process100, which may be a simulation as noted above, with a test-only ICG204and a test point added as a clock signal input to ICG208, as discussed above with reference toFIG.1at106. As shown inFIG.2, function logic205forms the function-enable input to ICG208. Testing process100introduces the output clock signal of a test-only ICG204as the clock input of the ICG208. Test-only ICG204further incorporates, as its function-enable input, a test point signal based on a processed test-enable signal201.

To achieve the function-enable input at the test-only ICG204, a test-enable signal201is passed through an inverter (NOT-gate)202. The output of the inverter202is then processed through an OR-gate203along with the output from another OR-gate207which processes the circuit206.

The output from OR-gate203serves as the test point which is used as a function-enable input for test-only ICG204. As described above, the output clock signal from test-only ICG204forms the clock input for ICG208, thereby allowing test-only ICG204to control the clocking of registers by ICG208. By preventing registers from being clocked, test-only ICG204may prevent a possible value change, which in turn prevents the downstream toggles caused by a value change in the register.

When it is determined that the function-enable path of the ICG is not timing-critical, testing process100is able to limit the toggle rate by inserting a test point and an AND-gate on the ICG function-enable path input. As shown inFIG.3, instead of adding a test-only ICG204at the clock input of ICG308, testing process100inserts, on the function-enable input to ICG308, a processed test-enable signal301and the function logic303, both of which are processed through an AND-gate307.

To achieve this function-enable input at the ICG308, the test enable signal301is passed through an inverter (NOT-gate)302. The output of the inverter302is then processed through an OR-gate306along with the output from another OR-gate305which processes the circuit304.

The output from the OR-gate306is then processed through an AND-gate307along with the function logic303to form the function-enable input of ICG308, to limit the toggle rate to within a preferred range.

A primary reason for being concerned with excessive toggling is that excessive toggling may cause a device to exceed its design power consumption. Therefore, in some implementations of the subject matter of this disclosure, the testing process may simulate the worst-case power consumption and compare the simulated worst-case power consumption to the designed benchmark, or “estimated,” power consumption, and only if the simulated worst-case power consumption exceeds the design power consumption would clock gating as described above be invoked. Otherwise, if the simulated worst-case power consumption is at or below the design power consumption then there is no reason to be concerned with the toggle rate and the clock gating would not be necessary, as follows.

FIG.4is a flow diagram illustrating implementations of a method400of testing the integrated circuit design including monitoring the power consumption of the design, in accordance with the subject matter of this disclosure. The testing process400depicted inFIG.4incorporates, in a testing process such as that described above with reference toFIG.1, a worst-case power estimation at both the maximum and minimum voltages of the ATPG testing. The process400begins at401where the worst-case power consumption is calculated, via simulation, at both the maximum and minimum voltages of the ATPG testing. Following the power calculation, the testing process400checks at411to see if the calculated power is greater than the estimated benchmark power. If it is determined at411that the calculated power is less than the estimated power, then clock gating is not needed to control toggling to reduce power consumption, and therefore the testing simulation ends.

However, if it is determined at411that the calculated power is greater than the estimated power, the testing process400continues by counting at402the number of ICGs in the integrated circuit design, and that number is eventually used as a limit to make sure all of the ICGs are processed during the simulation testing, as described below in further detail.

Once the number of ICGs is determined, the fanout of the first ICG is compared with the threshold number of registers at403, similar to the simulated testing process100depicted inFIG.1. If it is determined at403that the ICG fanout is greater than the threshold number of registers, the testing process400moves to404to limit the toggle rate. Alternatively, if it is determined at403that the ICG fanout is less than or equal to the threshold number of registers, the testing process moves to410to determine if the respective fanouts of all ICGs have been compared to the threshold numbers of registers. If it is determined at410that fanouts of all of the ICGs have not been compared with the threshold number of registers400, then at409, the process increments to the next ICG and returns to comparing the fanout value of the next ICG with the threshold number of registers at403.

If, however, it is determined at403that the ICG fanout is greater than the threshold number of registers, then at404, it is determined whether the ICG fanout exceeds the maximum number of registers, so as to require cloning the ICG. As described above with reference toFIG.1, a particular maximum number of registers that would make the fanout too large to be handled by one ICG is based on particular characteristics of the integrated circuit design being tested and may differ for different integrated circuit designs. Following this determination404, if the ICG fanout is determined to exceed the maximum number of registers, the testing process400moves to405to clone the ICG. However, if it determined that the ICG fanout does not exceed the maximum number of registers, the testing process400checks at406whether the function-enable path of the ICG is timing-critical.

The testing process400provides two different solutions to limit the toggle rate based on the determination made at406regarding whether or not the function-enable path of the ICG is timing-critical.

If the function enable path of the ICG is determined to be timing-critical, then at407, the testing process400alters the clock input by adding a test-only ICG and a test point as a parent to the ICG to limit the toggle rate at407. Further details regarding adding a test-only ICG and a test point as a parent were provided with reference toFIG.2above.

However, if, at406, it is determined that the function enable path of the ICG is not timing-critical, then at408, the testing process400alters the function-enable input of the ICG by inserting a test point and an AND-gate in the enable path of the ICG. By altering the enable path of the ICG, the testing process400effectively adds a control gate to the integrated circuit design which can control when clock tree segments are active, thereby controlling the clock tree activity of the integrated circuit design and keeping the integrated circuit design within the design activity factor specification during testing. Further details regarding inserting the test point and AND-gate in the enable path of the ICG were provided with reference toFIG.3above.

FIG.5is a flow diagram illustrating implementations of a method in accordance with the subject matter of this disclosure. Method500begins at501where a number of integrated clock gates in the integrated circuit device, each integrated clock gate being disposed in a respective branch of a clock tree of the integrated circuit device to stop clock propagation in the respective branch of the clock tree, is detected. Next, at502, for each detected integrated clock gate, an integrated clock gate fanout is compared with a threshold number of registers, the integrated clock gate fanout being a number of digital inputs that the output of each integrated clock gate can feed. At503, it is determined, when the integrated clock gate fanout is greater than the threshold number of registers, whether a function enable path of an existing integrated clock gate is timing-critical. At504, when it is determined that the function-enable path of the existing integrated clock gate is timing-critical, an additional integrated clock gate and a test point may be inserted as a clock input to the existing integrated clock gate.

Testing methods according to implementations of the subject matter of this disclosure may be carried out using testing apparatus that may be hardwired to perform the testing methods described above. The testing apparatus may also be based on a suitable processor that may be programmed via software or firmware to perform the testing processes described above.

As shown inFIG.6, the testing apparatus600may incorporate a plurality of circuit elements to carry out the testing methods as described above. Although six different circuit elements are shown in the embodiment ofFIG.6, elements that perform the functions of more than one of the various elements shown inFIG.6may be provided, or functions of one of the circuit elements may be implemented using two or more circuit elements, so that the number of circuit elements in the testing apparatus may be smaller or larger than shown inFIG.6while still being within the scope of the present disclosure.

Testing apparatus600may include a test calculation unit601, a comparator unit602, test signal unit603, simulation unit604, cloning unit605and power usage calculation unit606.

Test detection unit601may be configured to detect a number of integrated clock gates in the integrated circuit device. As described above with reference to101inFIG.1, clock propagation through an ICG cell is prevented when a low clock enable signal is applied to the ICG, which may be referred to as clock gating. The test detection unit601determines the number of ICGs in the integrated circuit design, which is eventually used to make sure all the ICGs are processed during the simulation testing.

The comparator unit602may be configured to compare an integrated clock gate fanout with a threshold number of registers, as described in testing process100at102with reference toFIG.1above.

The test signal unit603may be configured to determine, if the integrated clock gate fanout is greater than the threshold number of registers, whether a function enable path of an existing integrated clock gate is timing-critical. As described above at105with reference toFIG.1, the test signal unit603may check whether the function enable path of the ICG is timing-critical. The simulation unit604alters either the clock input, or the function-enable input of the ICG, depending on whether the function-enable path is determined to be timing-critical.

The simulation unit604may be configured to insert an additional integrated clock gate and a test point to the integrated circuit device as a clock input to the existing integrated clock gate, or to replace the enable path of the ICG with a test point and an AND-gate, based on the determinations made by the test signal unit603, as described above.

The cloning unit605may be configured to clone the integrated clock gate if the ICG fanout is too large so as to require a cloning of the ICG. The cloning unit605makes a determination if the ICG fanout exceeds the maximum number of registers, thereby necessitating cloning of the ICG. Following that determination, if the ICG fanout is determined to exceed the maximum number of registers, the cloning unit605proceeds to clone the ICG, as described above.

The power usage calculation unit606may be configured to calculate a worst-case power usage of the integrated circuit device. The power usage calculation unit606checks to see if the calculated power is greater than the estimated power, as described above.

Any one or more of the units described above may be hardwired to perform the specific functions as listed above. Alternatively, any one or more of the units may represent a processor carrying out different portions of the software/firmware testing processes as described.

Testing of integrated circuit devices in accordance with implementations of the subject matter of this disclosure, including controlling clock tree segments to limit register toggling during testing, can prevent a valid design, which would never exceed a design activity factor in actual use, from exceeding the design activity factor during testing. Therefore, the testing methods and apparatus described in this disclosure prevent false test failures, thereby improving the yield of integrated circuit fabrication processes.

As used herein and in the claims which follow, the construction “one of A and B” shall mean “A or B.”

It is noted that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.