Patent ID: 12203894

DETAILED DESCRIPTION

Certain ultrasound devices include ultrasonic transducers, such as capacitive micromachined ultrasonic transducers (CMUTs), that are configured to convert a voltage pulse signal to an ultrasonic wave. To generate an ultrasonic wave of sufficient pressure to penetrate a human body, a pulser circuit may generate a high-voltage pulse signal and input that high-voltage pulse signal to a CMUT.

Certain ultrasound devices also include receive circuitry which may include amplifiers, filters, analog-to-digital converters, and digital processing circuits that are configured to receive, process, and output electronic signals produced by ultrasonic transducers in response to received ultrasonic waves. When there are multiple channels of receive circuitry, it may be helpful for the receive circuitry to operate at low voltages. For example, this may enable receive circuitry to achieve a small physical size in an integrated circuit, and may help to prevent the receive circuitry from generating too much heat. Ultrasound devices may therefore have high-voltage (HV) domains including, for example, pulsers, and a low-voltage (LV) domains including, for example, receive circuitry.

It may be helpful to test pulsers in integrated circuits. For example, testing may include:1. Analyzing whether a pulser is working (e.g., whether it is pulsing)2. When there are multiple pulsers in an ultrasound device, analyzing whether certain pulsers are working and certain pulsers are not working;3. Analyzing what a pulser output waveform looks like, which may be especially helpful for multi-level pulsing and for imaging optimization;4. When there are multiple pulsers in the ultrasound device, analyzing how uniform pulsed waveforms are among different pulsers;5. Analyzing what the actual slew rate of a pulser is with different CMUT loads.

Certain methods of testing pulsers, such as measuring acoustic transmission power from the pulsers using lens reflection, may suffer from lens nonuniformity, and may not be capable of measuring the real pulser output waveform.

The inventors have recognized that one efficient approach for testing a pulser may be to route the output of the pulser to the ultrasound device's receive circuitry, which may already be configured to process electronic signals and output the electronic signals to an external device, where the signals can be analyzed. However, a challenge is that signals output by the pulser may be high-voltage while the receive circuitry may only be capable of handling low-voltage signals. The inventors have recognized that built-in self-test (BIST) integrated circuitry may be integrated onto the same substrate (e.g., a semiconductor substrate) that also includes integrated ultrasound circuitry, such as one or more pulsers, where the BIST circuitry may be configured to receive high-voltage signals from a pulser and attenuate the signal such that the signal may be processed and output by the receive circuitry. One approach, which may be considered a current-mode approach, includes converting the high-voltage pulser output signal to an attenuated current signal using a transconductance amplifier coupled between the pulser and the receive circuitry, and then using a transimpedance amplifier in the receive circuitry to convert the attenuated current signal to a low-voltage signal. Another approach, which may be considered a voltage-mode approach, includes converting the high-voltage pulser output signal to an attenuated voltage signal using one or more capacitor dividers in a capacitor network between the pulser and the receive circuitry.

It should be noted that in some embodiments, a pulser may already include attenuation circuitry (e.g., a capacitor divider) for attenuating the high-voltage pulser output signal to a mid-voltage pulser output. Feedback circuitry in the pulser that operates at a mid-voltage level (i.e., a level between the high-voltage level of the pulser output and the low-voltage levels of the receive circuitry) may then use the attenuated pulser output signal. Thus, the pulser may include both an HV domain and a mid-voltage (MV) domain. In such embodiments, in the current-mode approach, the BIST circuitry may convert the MV version of the pulser output signal to a current signal, and then the transimpedance amplifier may convert the current signal to a LV signal. In voltage mode, the BIST circuitry may convert the MV version of the pulser output signal to a LV signal.

The inventors have also recognized that such circuitry for BIST may also be used for characterizing a CMUT (e.g., characterizing its capacitance, collapse voltage, and/or stiction) and/or testing receive circuitry. For example, a transconductance amplifier in BIST circuitry may be used to generate a constant current and inject that current to an input terminal of a comparator in receive circuitry in the ultrasound device, where the input terminal of the comparator is electrically coupled to the CMUT. The constant current output from the transconductance amplifier may be integrated onto the CMUT to generate a ramp voltage. The comparator may compare the ramp voltage to the reference voltage, and the time it takes from the beginning of the ramp to when the ramp crosses the reference voltage may be used to compute the capacitance of the CMUT. If the capacitance of a CMUT is measured as a function of multiple bias voltage applied to the CMUT, the collapse voltage of the CMUT may be determined, or it may be determined whether the membrane of the CMUT is stuck to the substrate of the CMUT.

Measuring the collapse voltage may be helpful because the collapse voltage of a CMUT may change with time. Applying a bias voltage to the CMUT that is a particular offset voltage greater than the collapse voltage of the CMUTs may help to ensure that, as the collapse voltage of the CMUT changes, the value of the bias voltage applied to the CMUT minus the collapse voltage of the CMUT remains the same. This may help to keep the acoustic efficiency of the CMUT consistently optimized over time. When an ultrasound device includes an array of CMUTs that share one membrane, the collapse voltages of all the CMUTs in the array, or a subset thereof, may be measured and averaged, and a bias voltage may be applied to the CMUTs that is a particular offset voltage greater than the average of the collapse voltages of the CMUTs.

With regards to stiction, a CMUT membrane can get stuck on the substrate due to electrostatic force from charges trapped in the cavity, or from van der Waals forces between the membrane and the bottom of the cavity. Such stiction is detrimental to the operation of the CMUT. By restricting the motion of the membrane, stiction may cause a lower transmission pressure output as well as decreased reception sensitivity, such that resulting ultrasound images may be lower in quality (e.g., in terms of signal-to-noise ratio (SNR)). Also, in an array of CMUTs, stiction may cause non-uniformity in the array, since some CMUTs might be stuck while others may not. The pattern of stuck CMUTs may also not repeat. Asymmetry in the stiction profile may cause undesirable resonant modes. Non-uniformity and non-repeatability in the stiction profile may particularly negatively affect some imaging modes such as Doppler mode by introducing imaging artifacts. It may be helpful to measure how many CMUTs in an array are stuck and generate a notification when the number of stuck CMUTs exceeds a threshold. For example, the notification may notify a user that the ultrasound device should be replaced.

For testing receive circuitry, a pulser may generate a multi-level pulse voltage waveform (e.g., to mimic a sinewave test waveform) and the transconductance amplifier in the BIST circuitry may convert this voltage waveform to a current waveform and output this current waveform to the receive circuitry. This may be an accurate and controllable method for injecting a test waveform to the receive circuitry. Additionally, when multiple blocks of circuitry include transconductance amplifiers, this method may allow for uniformity in generation of waveforms and testing based on the waveforms across the different blocks. In some embodiments, for testing receive circuitry, current sources coupled through switches to a capacitor at the input of receive circuitry may be operated to charge or discharge the capacitor and thereby generate an increasing and/or decreasing ramp voltages at the input of the receive circuitry. This ramp voltage may be injected to the receive circuitry and used for testing the receive circuitry.

As referred to herein in the detailed description and claims, two elements being “coupled” should be understood to mean either directly coupled or that there may be intervening circuitry between the two elements.

Various aspects of the present disclosure may be used alone, in combination, or in a variety of arrangements not specifically described in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

FIG.1is an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.1includes a pulser100, a capacitive micromachined ultrasonic transducer (CMUT)152, a receive switch162, and receive circuitry184. The pulser100is coupled to the CMUT152. The CMUT152is in series with the receive switch162, which is coupled to the receive circuitry184. The CMUT152is couplable to the receive circuitry184by closing the switch162.

In operation, the pulser100may be configured to generate high-voltage pulses that are inputted to the CMUT152(during the “transmit phase”). The high-voltage pulses may cause the CMUT152to output ultrasonic waves. During the transmit phase, to prevent the high-voltage pulses from the pulser100from being inputted to the receive circuitry184, which operates at low voltages, the receive switch162may be configured to be open. The CMUT152may be configured to receive reflected ultrasonic waves and convert these ultrasonic waves to electric currents (during the “receive phase”). The receive circuitry184may be configured to convert these electric currents to voltages that can be further processed by other circuitry in the receive circuitry184. During the receive phase, to allow electric currents converted from received ultrasonic waves to be inputted to the receive circuitry184, the receive switch162may be configured to be closed. The receive circuitry184may include further amplifiers, filters, analog-to-digital converters, and digital processing circuits that may be configured to receive, process, and output the electronic signals produced by the CMUT152in response to received ultrasonic waves.

FIGS.3,4,8,10,14,15,16,17, and21illustrate non-limiting examples of the circuitry ofFIG.1in more detail. The below figures include three types of transistors: high-voltage (HV), mid-voltage (MV), and low-voltage (LV).FIG.2illustrates transistor symbols used for the three different types of transistors, in accordance with certain embodiments described herein. In some embodiments, the maximum operating voltage for HV transistors may be up to 80 V. For example, the maximum operating voltage may be 32 V or 55 V. In some embodiments, the maximum operating voltage for MV transistors may be up to 8 V. For example, the maximum operating voltage may be 8 V or 5 V. In some embodiments, the maximum operating voltage for LV transistors may be up to 3.3 V. For example, the maximum operating voltage may be 1.5 V or 1.1 V. The below figures also include three types of power supplies: HV, MV, and LV, where the voltage of the HV power supplies (or the absolute value of their voltage) is higher than the voltage of the MV power supplies (or the absolute value of their voltage), and the voltage of the MV power supplies (or the absolute value of their voltage) is higher than the voltage of the LV power supplies (or the absolute value of their voltage).

FIG.3is an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.3includes a pulser300(which may be an example of the pulser100), the capacitive micromachined ultrasonic transducer (CMUT)152, the receive switch162, and receive circuitry384(which may be an example of the receive circuitry184). The pulser300includes a comparator302, a controller310, a level shifter316, a HV n-type metal-oxide-semiconductor field effect transistor (nMOS)326, a HV p-type metal-oxide-semiconductor field effect transistor (pMOS)334, and a capacitor divider formed by two capacitors346and348. The receive circuitry384includes an amplifier364and other circuitry not explicitly illustrated. As will be described further below, in some embodiments the amplifier364in the receive circuitry384is configurable as a transimpedance amplifier. In some embodiments, the amplifier364in the receive circuitry384is configurable as a comparator. In some embodiments, the amplifier364in the receive circuitry384is configurable as a unity-gain amplifier.

The comparator302has a positive input terminal304, a negative input terminal306, and an output terminal308. The controller310has an input terminal312, a positive output terminal314, and a negative output terminal315. The level shifter316has a positive input (inp) terminal318, a negative input terminal (inn)320, a positive output terminal (outp)322, and a negative output terminal (outn)324. The HV nMOS326has a gate terminal328, a drain terminal330, and a source terminal332. The HV pMOS334has a gate terminal336, a drain terminal338, and a source terminal340. The amplifier364has a positive input terminal366, a negative input terminal368, and an output terminal370.

The positive input terminal304of the comparator302is coupled to a node Sense. The negative input terminal306of the comparator302is coupled to a node Thres. The output terminal308of the comparator302is coupled to the input terminal312of the controller310. The positive output terminal314of the controller310is coupled to the positive input terminal318of the level shifter316. The negative output terminal315of the controller310is coupled to the negative input terminal320of the level shifter316. The negative output terminal324of the level shifter316is coupled to the gate terminal328of the HV nMOS326. The positive output terminal322of the level shifter316is coupled to the gate terminal336of the HV pMOS334. The drain terminal330of the HV nMOS326is coupled to the node Out. The source terminal332of the HV nMOS326is coupled to a HV negative power supply344. The drain terminal338of the HV pMOS334is coupled to the node Out. The source terminal340of the HV pMOS334is coupled to a HV positive power supply342. The capacitor346extends between the node Out and the node Sense. The capacitor348extends between the node Sense and ground350.

The CMUT152is coupled between the node Out and a bias voltage372. In particular, a bottom electrode of the CMUT152at its substrate may be coupled to the node Out and a membrane of the CMUT152may be coupled to the bias voltage372, which may be referred to as VBIAS. If Out is at a virtual ground, then the voltage applied to the CMUT152(i.e., between the membrane and the bottom electrode of the CMUT152) may be VBIAS. The receive switch162is coupled between the node Out and the negative input terminal368of the amplifier364. The CMUT152is couplable to the input terminal of the receive circuitry384(inFIG.3, to the negative input terminal368of the amplifier364) by closing the receive switch162.

A bias voltage Vref is coupled to the positive input terminal366of the amplifier364. Vref may be generated by bias circuitry, such as a resistor divider in parallel with a bypass capacitor. A resistor380in series with a switch1013is coupled between the negative input terminal368of the amplifier364and the output terminal370of the amplifier364. A switch1031is also coupled between the negative input terminal368of the amplifier364and the output terminal370of the amplifier364. InFIG.3, the switch1013is closed and the switch1031is open. This configuration, in which the resistor380is coupled in feedback configuration between the negative input terminal368of the amplifier364and the output terminal370of the amplifier364is referred to as the TIA365.

In operation, the pulser300may be configured to generate high-voltage pulses at the node Out. The node Out is coupled to the CMUT152, such that the high-voltage pulses at Out may cause the CMUT152to output ultrasonic waves. The pulser300may operate in a feedback configuration to output these high-voltage pulses. In particular, the capacitor divider consisting of the capacitors346and348may be configured to attenuate the output voltage of the pulser300at the node Out to a lower voltage at the node Sense. The capacitor divider may be configured to attenuate the high-voltage pulses in the HV domain to lower-voltage pulses in the MV domain appropriate for processing by the comparator302and the controller310, which may operate at voltages in the MV domain.

The comparator302may be configured to compare the voltage at Sense to the voltage at the node Thres. As will be described further below, the voltage at the node Thres may be a threshold voltage. The comparator302may be configured to output a high voltage if Sense is greater than Thres and output a low voltage if Sense is less than Thres. The controller310may be configured to control the voltages inputted to the level shifter316based on the output voltage received from the comparator302. For example, if the output voltage received from the comparator302is high (i.e., the voltage at Sense is greater than the voltage at Thres), then the controller310may be configured to output signals at the positive output terminal314and/or at the negative output terminal315configured to turn on the HV nMOS326and/or to turn off the HV pMOS334. In this case, an electric current flowing from the node Out to the HV negative power supply344may discharge or negatively charge the node Out until the voltage at Sense is equal to (or within a threshold of) the voltage at Thres. As another example, if the output voltage received from the comparator302is low, then the controller310may be configured to output signals at the positive output terminal314and/or at the negative output terminal315configured to turn off the HV nMOS326and/or to turn on the HV pMOS334. In this case, an electric current flowing from the HV positive power supply342may charge the node Out until the voltage at Sense is equal to (or within a threshold of) the voltage at Thres. As can be seen inFIG.3, the output signals at the positive output terminal314and at the negative output terminal315of the controller310are not directly coupled to the HV nMOS326and the HV pMOS334. This may be because the controller310may operate at voltages in the MV domain and the HV nMOS326and the HV pMOS may operate at voltages in the HV domain. Thus, the level shifter316may be configured to receive these output signals in the MV domain at its positive input terminal318and negative input terminal320, and convert these signals to higher voltage signals in the HV domain at the positive output terminal322and the negative output terminal324appropriate for controlling the gate terminal328of the HV nMOS326and the gate terminal336of the HV pMOS334. If the voltage at Sense equals the voltage at Thres, the comparator302may be turned off (e.g., by control logic not illustrated) until the voltage at Thres changes. For rail-to-rail two-level bipolar or unipolar pulsing, the feedback network formed by the comparator302, the controller310, the level shifter316, and the capacitors346and348may not be used.

In addition to transmitting ultrasonic waves in response to receiving high-voltage pulses from the pulser300(during the “transmit phase”), the CMUT152may be configured to receive reflected ultrasonic waves and convert these ultrasonic waves to electric currents (during the “receive phase”). The TIA365may be configured to convert these electric currents to voltages that can be further processed by other circuitry in the receive circuitry384. During the transmit phase, to prevent the high-voltage pulses from the pulser300from being inputted to the TIA365, the receive switch162may be configured to be open. During the receive phase, to allow electric currents converted from received ultrasonic waves to be inputted to the TIA365(and specifically, to the negative input terminal368of the amplifier364), the receive switch162may be configured to be closed.

With the resistor380coupled in feedback around its amplifier364, the TIA365may be configured to convert the current received at the negative input terminal368of the amplifier364to a voltage at the output terminal370of the amplifier364with a gain equivalent (at least approximately) to the resistance of the resistor380. The voltage at the output terminal370may be output to other circuitry in the receive circuitry384, which may include, for example, circuitry for converting analog voltages to digital codes and for outputting the digital codes to an external device.

FIG.4is an example schematic diagram illustrating further circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.4is the same asFIG.3, but with the addition of a transconductance amplifier (Gm)454coupled between the pulser300and the receive circuitry384. As described above, it may be helpful to analyze the output of the pulser300for testing purposes. While the receive circuitry384may be capable of converting analog voltages to digital codes and outputting the digital codes to an external device where they can be analyzed, it may not be feasible to directly connect the output of the pulser300to the receive circuitry384(e.g., to the TIA365). The output of the pulser300may include pulses that are higher in voltage (e.g., in the HV domain) than the operating voltage of the receive circuitry384(e.g., in the LV domain). The inventors have recognized that, instead, the transconductance amplifier454may be included between the pulser300and the receive circuitry384(in particular, the TIA365) for built-in self-testing (BIST). The transconductance amplifier454may be configured to convert the output of the pulser300(or an attenuated version of the output of the pulser300) to an attenuated current signal that can be converted to a voltage signal by the TIA365. For example, the transconductance amplifier may be configured to convert the HV output of the pulser300, or an attenuated version of the pulser300output in the MV domain, to the LV domain. This LV analog signal may then be output to other circuitry in the receive circuitry384, which may be configured to convert the analog voltage signal to a digital codes and output it to an external device, where it can be analyzed for testing purposes. In other words, the transconductance amplifier may be configured to process the output of the pulser300such that the receive circuitry384may be reused for testing.FIG.4may thus illustrate a configuration for testing of the pulser300. As will be described further below, the transconductance amplifier454may be a linearized transconductance amplifier.

The transconductance amplifier454has a positive input terminal456, a negative input terminal458, and an output terminal460. The positive input terminal456of the transconductance amplifier454is coupled to the node Sense. The negative input terminal458is coupled the node Thres0. The output terminal460of the transconductance amplifier454is coupled to the negative input terminal368of the amplifier364. The amplifier364, as inFIG.3, is in the feedback (current-to-voltage conversion) configuration of the TIA365. The transconductance amplifier454may be configured to receive the voltage pulses from the pulser300(after attenuation by the capacitor divider formed by the capacitors346and348) and convert the difference between these voltage pulses and the voltage Thres0 at the negative input terminal458to a current at the output terminal460. This current may then be input to the TIA365(in particular, to the negative input terminal368of the amplifier364) for conversion to an analog voltage that may be digitally converted and outputted to an external device by the receive circuitry384, and analyzed for testing purposes.

As described above, the transconductance amplifier454may be configured to convert the difference between the voltage pulses at Sense and the voltage Thres0 to a current. As will be described further below, the voltage Thres0 may be the middle voltage of the voltage pulses at Sense, such that subtracting Thres0 from the voltage at Sense may remove the DC component of the voltage pulses. If the DC component of the voltage pulses were not removed, the output current of the transconductance amplifier454may saturate the TIA365.

FIG.5is an example circuit diagram for the transconductance amplifier454, in accordance with certain embodiments described herein. The transconductance amplifier454includes a positive input MV transistor586, a negative input MV transistor588, a current mirror590, a current mirror592, a current mirror594, a resistor596, and a resistor598. The gate of the positive input MV transistor586, which is also the positive input terminal456of the transconductance amplifier454, is coupled to Sense, the drain is coupled to the current mirror590, and the source is coupled to the resistor596. The gate of the negative input MV transistor588, which is also the negative input terminal458of the transconductance amplifier44, is coupled to Thres0, the drain is coupled to the current mirror592, and the source is coupled the resistor598. The current mirror590is coupled between the positive input MV transistor586, the current mirror594, and a MV positive power supply543. The current mirror592is coupled between the negative input MV transistor588, the current mirror594, and the MV positive power supply543. The current mirror594is coupled between the current mirror590, the current mirror592, and ground350. The output terminal460of the transconductance amplifier454is taken from the node between the current mirror590and the current mirror594which, in turn, mirrors the current from current mirror592. The current mirror590and the current mirror592include MV transistors. The current mirror594includes LV transistors. The resistance of the resistors596and598is referred to as Rs. WhileFIG.5illustrates one example circuit for the transconductance amplifier454, it should be appreciated that other circuits may be used.

The transconductance amplifier454ofFIG.5may be considered a source-degenerated linearized transconductance cell. “Linearized” may mean that the transconductance of the transconductance amplifier454is not dominated by the transconductance (gm) of the positive input MV transistor586and the negative input MV transistor588, which may be the normal case for transconductance amplifiers. Rather, the transconductance of the transconductance amplifier454may be dominated by the resistance R s of the degenerated resistors596and598. This may be helpful because gm may not be constant versus different operating voltages/currents, which may introduce non-linearity. In contrast, when the transconductance is dominated by the resistance Rs, the transconductance may be relatively consistent with different voltage/current ranges, thus resulting in better linearity. Such a linearized transconductance amplifier may not be used in other applications because, to obtain a high voltage gain, gm should dominate the transconductance. Here, however, the linearity in conversion between current and voltage may be more important than high gain.

The conversion ratio between the pulser output voltage at the node Out and the transconductance amplifier454output at the output terminal360may be

Acapdiv=RTIAn·Rs,
where Acapdivis the division ratio of the capacitor divider formed by the capacitors346and348, and the current mirror ratio of the current mirrors590and592is n:1. In particular, for every n parallel transistors (not illustrated explicitly) in the current mirrors590and592that have their drains connected to their gates, there may be 1 transistor that does not have its drain connected to its gate. To achieve a desired value for the denominator in the expression

RTIAn·Rs,
the current mirror ratio n:1 may be selected (in other words, the number of parallel transistors may be selected) such that the resistance Rsmay be a sufficiently low value to achieve an acceptably low required physical area for the resistors596and598. In some embodiments, the ratio

RTIAn·Rs
may be approximately equal to or between 1/20 and 1. In some embodiments, Acapdivmay be approximately equal to or between 1/32 and ¼ (e.g., ⅛).

FIG.6is a circuit diagram of a non-limiting example of the transconductance amplifier454, in accordance with certain embodiments described herein. In particular,FIG.6illustrates circuitry, in particular transistors M9, M10, M11, M12, and M13, with which the circuitry illustrated inFIG.5may be augmented to enable turning on and off of the transconductance amplifier454. For example, for testing circuitry in the ultrasound device (e.g., for testing the pulser300or for characterizing the CMUT152), the transconductance amplifier454may be turned on. For using the ultrasound device for normal imaging, the transconductance amplifier454may be turned off while the pulser300and the receive circuitry384remain on.

In operation, to turn off the transconductance amplifier454, the signal en may be switched low and the signal en_b may be switched high. This may cause:1. The transistor M9to turn on, thereby pulling the drain of M9low to the ground350and turning off the transistors M8and M9in the current mirror594;2. The transistor M10to turn off, thereby disabling current flow in its branch of the transconductance amplifier454;3. The transistor M11to turn on, thereby pulling the drain of M11up to the voltage of the MV power supply543, and turning off the transistors M5and M6in the current mirror592;4. The transistor M12to turn off, thereby disabling current flow in its branch of the transconductance amplifier454;5. The transistor M13to turn on, thereby pulling the drain of M13up to the voltage of the MV power supply543, and turning off the transistors M3and M4in the current mirror590.

In operation, to turn on the transconductance amplifier454, the signal en may be switched high and the signal en_b may be switched low. This may cause:1. The transistor M9to turn off;2. The transistor M10to turn on, thereby enabling current flow in its branch of the transconductance amplifier454;3. The transistor M11to turn off;4. The transistor M12to turn on, thereby enabling current flow in its branch of the transconductance amplifier454;5. The transistor M13to turn off.

In some embodiments, the enable signals for M9, M10, and M11may be independent of the enable signals for M12and M13. For example, the enable signals for M9, M10, and M11may be switched low while the enabled signals for M12and M13may be switched high. This may allow conversion of the voltage at Sense to a current without DC subtraction of the voltage at Thres.

FIG.7is an example circuit diagram for further circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.7illustrates a configuration which may be used for testing of the pulser300in conjunction with the configuration illustrated inFIG.4.FIG.7illustrates the comparator302, the transconductance amplifier454, a resistor ladder701, and a multiplexer703. The resistor ladder701includes multiple resistors coupled in a ladder fashion between the HV positive power supply342and ground350such that the resistors form multiple resistor dividers for generating multiple voltages at the nodes Thres+2, Thres+1, Thres0, Thres−1, Thres−2. Both the transconductance amplifier454and the pulser300(in particular, the comparator302) are configured to receive, as inputs, voltages from the resistor ladder701. The multiplexer703may accept these voltages at its input terminals and select, based on a control signal not illustrated, one of the voltages at is output terminal (referred to as the node Thres), which is coupled to the negative input terminal306of the comparator. In some embodiments, the resistor ladder701may include more resistors for generating more voltage options. In some embodiments, the resistor ladder701may include fewer resistors for generating fewer voltage options. The number of voltage options generated may depend on the requirements for the multi-level pulsing (e.g., how many voltage levels are desired).

As described above, the pulser300may operate by using feedback to cause the voltage at the node Sense to be equivalent to, or within a threshold of, the selected threshold voltage at the node Thres. The voltage at Sense is an attenuated version of the voltage at the node Out, which is the output of the pulser300. Thus, in operation, selection of one of the voltages generated by the resistor ladder701may control the output of the pulser30.

The voltage Thres0 is coupled to the negative input terminal458of the transconductance amplifier454. As can be seen inFIG.7, the voltage Thres0 is the middle voltage of the voltages generated by the resistor ladder701, and due to feedback of the pulser300, Thres0 may be middle voltage of the voltage at Sense. As described above, subtracting Thres0 from the voltage at Sense by the transconductance amplifier454may remove the DC component of the voltage pulses at Sense. If the DC component of the voltage pulses were not removed, the output of the transconductance amplifier454may saturate the TIA365(not illustrated inFIG.7).

FIG.8is an example schematic diagram illustrating further circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.8is the same asFIG.4, except that:1. The voltage Thres (i.e., the same voltage inputted to negative input terminal306of the comparator302) is inputted to the positive input terminal456of the transconductance amplifier454;2. The switch1013and the switch1031are open, such that there is an open circuit between the negative input terminal368and the output terminal370of the amplifier364. In other words, the amplifier364is in open-loop configuration and may operate as a comparator (rather than as a TIA);3. The receive switch162is closed.

FIG.8illustrates a non-limiting example of a configuration for characterizing the CMUT152(e.g., characterizing its capacitance, collapse voltage, and/or stiction). In such a configuration, the pulser300may be kept off, such that it does not output any high-voltage signals. The voltage at Thres may be kept constant, such that the voltage difference between Thres and Thres0 that is inputted to the transconductance amplifier454is constant, and the output current from the transconductance amplifier454is constant. The constant current output from the transconductance amplifier454may be integrated onto the CMUT152to generate a ramp voltage at the negative input terminal368of the amplifier364. The amplifier364, operating as a comparator, may compare the ramp voltage to the reference voltage (referred to as Vref) at the positive input terminal366of the amplifier364. When the ramp voltage crosses Vref, the output voltage of the amplifier364may switch from high to low or from low to high. If the ramp begins at the voltage of an LV positive power supply (referred to as VDDA) and proceeds to ground350, or if the ramp begins at ground350and proceeds to VDDA, the configuration ofFIG.8may accordingly be used to time how long it takes from the beginning of the ramp to when the ramp cross Vref. The capacitance of the CMUT152may be computed as

C=Iramp×TrampVDDA-Vref,
where Irampis the constant current outputted by the transconductance amplifier454and Trampis the time it takes from the beginning of the ramp to when the ramp cross Vref. In some embodiments, two ramps may be used, one during current sourcing and one during current sinking, such that one ramp proceeds from VDDA to ground350(during current sinking) and one proceeds from ground350to VDDA (during current sourcing), and the average of the Trampmeasured for each ramp may be used to compute C. In some embodiments, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sourcing, and these multiple measurements of time may be averaged. Additionally, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sinking, and these multiple measurements of time may be averaged. The two averaged results, one result for current sourcing and one for current sinking, may then be averaged together. Alternatively, the multiple measurements from current sourcing and from current sinking may be averaged together. It should be appreciated that in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sourcing may be performed prior to measuring the time for a ramp voltage to cross a reference voltage during current sinking, while in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sinking may be performed prior to measuring the time for a ramp voltage to cross the reference voltage during current sourcing.

In some embodiments, characterizing the CMUT152may include characterizing the collapse voltage of the CMUT152. Characterizing the collapse voltage of the CMUT152may include applying multiple different bias voltage values VBIASto the CMUT152. The bias voltage VBIASapplied to the CMUT may be measured between the membrane of the CMUT152and the bottom electrode at the substrate of the CMUT152. If the bottom electrode at the substrate of the CMUT152is at virtual ground, then applying VBIASto the CMUT may be accomplished by applying VBIASto the membrane. For each value of VBIAS, the capacitance of the CMUT152may be computed as described above to produce a C vs. VBIAScurve. A discontinuity may be observed in this curve when there is contact between the membrane and the substrate of the CMUT152. If the C vs. VBIAScurve was generated by increasing the value of VBIAS, then the value of VBIASat which this contact occurs (i.e., the value of VBIASat which the discontinuity occurs) may be the collapse voltage of the CMUT152. A discontinuity may be detected in the C vs. VBIAScurve by calculating the first and/or second derivative of the curve.

In some embodiments, characterizing the CMUT152may include characterizing whether the membrane of the CMUT152is stuck to the substrate of the CMUT152. In some embodiments, a C vs. VBIAScurve may be generated as described above, and if no discontinuity is detected in this curve, this may mean that the membrane of the CMUT152is stuck to the substrate of the CMUT152. This may be because, for the entire range of VBIASvalues, the membrane is collapsed.

In some embodiments, applying VBIASto the membrane of the CMUT152may include routing the voltage VBIASfrom circuitry in the ultrasound device but external to the substrate on which the CMUT152is disposed, through a routing network, and to the membrane of the CMUT152. It may be helpful to wait for the voltage at the membrane to settle to VBIASafter charging or discharging the routing network.

FIG.9is an example circuit diagram for further circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.9illustrates a non-limiting example of a configuration for characterizing the CMUT152in conjunction with the configuration illustrated inFIG.8.FIG.9is the same asFIG.7, except that inFIG.9, the voltage Thres is inputted to the positive input terminal456of the transconductance amplifier454.

FIG.10is an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.10is the same asFIG.4, except thatFIG.10includes a multiplexer1005. The multiplexer1005includes a first input terminal1007, a second input terminal1009, and an output terminal1011. The first input terminal1007is coupled to the node Sense. The second input terminal1009is coupled to the node Thres. The output terminal1011is coupled to the positive input terminal456of the transconductance amplifier454.

The circuit ofFIG.10may be used either for testing the pulser300, as described with reference toFIG.4, or for characterizing the CMUT152, as described with reference toFIG.8. In operation, for testing the pulser300, a control signal for the multiplexer1005(not illustrated in the figure) may control the multiplexer1005to select the voltage at the first input terminal1007(i.e., the voltage at the node Sense) for outputting at the output terminal1011. Additionally, the switch1013may be closed and the switch1031may be open, such that the amplifier364is in the close-loop, feedback configuration of the TIA365. Thus, the circuit may be equivalent to the circuit ofFIG.4. For characterizing the CMUT152, a control signal for the multiplexer1005(not illustrated in the figure) may control the multiplexer1005to select the voltage at the second input terminal1009(i.e., the voltage at the node Thres) for outputting at the output terminal1011. Additionally, the switch1013and the switch1031may be open, such that the amplifier364is in open-loop, comparator configuration, and the receive switch162may be closed. Thus, the circuit may be equivalent to the circuit ofFIG.8.

FIG.11is an example circuit diagram for further circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.11is the same asFIG.7, except thatFIG.11includes a chopper switch1105. The chopper switch1105includes a first input terminal1107, a second input terminal1109, a first output terminal1111, and a second output terminal1113. The first input terminal1107is coupled to Sense. The second input terminal1109is coupled to Thres. The first output terminal1111is coupled to the positive input terminal456of the transconductance amplifier456. The second output terminal1113is coupled to the positive input terminal304of the comparator302.

The circuit ofFIG.11may be used either for testing the pulser300, as described with reference toFIG.7, or for characterizing the CMUT152, as described with reference toFIG.9. In operation, for testing the pulser300, a control signal for the chopper switch1105(not illustrated in the figure) may control the chopper switch1105to select the voltage at the first input terminal1107(i.e., at the node Sense) for outputting at the first output terminal1111. Thus, the circuit may be equivalent to the circuit ofFIG.7. For characterizing the CMUT152, the control signal for the chopper switch1105(not illustrated in the figure) may control the chopper switch1105to select the voltage at the second input terminal1109(i.e., the voltage at the node Thres) for outputting at the first output terminal1111. Thus, the circuit may be equivalent to the circuit ofFIG.9.

Additionally, in operation, for normal transmission of pulses using the pulser300, a control signal for the chopper switch1105(not illustrated in the figure) may control the chopper switch1105to select the voltage at the first input terminal1107(i.e., the voltage at the node Sense) for outputting at the second output terminal1113and to select the voltage at the second input terminal1109(i.e., the voltage at the node Thres) for outputting at the first output terminal1111. Alternatively, the control signal for the chopper switch1105may control the chopper switch1105to select the voltage at the first input terminal1107(i.e., the voltage at the node Sense) for outputting at the first output terminal1111and to select the voltage at the second input terminal1109(i.e., the voltage at the node Thres) for outputting at the second output terminal1113. Thus, the circuit may control the polarity of pulses generated by the pulser300, and the comparator302may only need to detect crossings in one direction (e.g., rising or falling).

FIG.12is an example circuit diagram for further circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.12is the same asFIG.7, except thatFIG.12includes a multiplexer1205. The multiplexer1205includes a first input terminal1207, a second input terminal1209, and an output terminal1211. The first input terminal1207is coupled to Sense. The second input terminal1209is coupled to Thres. The output terminal1211is coupled to the positive input terminal456of the transconductance amplifier456. Sense is also coupled to the first input terminal304of the comparator302and Thres is also coupled to the second input terminal306of the comparator302.

The circuit ofFIG.12may be used either for testing the pulser300, as described with reference toFIG.7, or for characterizing the CMUT152, as described with reference toFIG.9. In operation, for testing the pulser300, a control signal for the multiplexer1205(not illustrated in the figure) may control the multiplexer1205to select the voltage at the first input terminal1207(i.e., at the node Sense) for outputting at the output terminal1111. Thus, the circuit may be equivalent to the circuit ofFIG.7. For characterizing the CMUT152, the control signal for the multiplexer1205(not illustrated in the figure) may control the multiplexer1205to select the voltage at the second input terminal1209(i.e., the voltage at the node Thres) for outputting at the output terminal1211. Thus, the circuit may be equivalent to the circuit ofFIG.9.

For normal transmission of pulses using the pulser300, the comparator302may be capable of detecting crossings in both directions (e.g., rising and falling) which may enable bipolar operation of the pulser300.

FIG.13is an example circuit diagram for further circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.13is the same asFIG.7, except thatFIG.13includes the chopper switch1105and the multiplexer1205. The first input terminal1107of the chopper switch1105is coupled to Sense, the second input terminal1109is coupled to Thres, and the output terminal1211is coupled to the positive input terminal456of the transconductance amplifier456. The first input terminal1207of the multiplexer1205is coupled to Sense. The second input terminal1209is coupled to Thres. The output terminal1211is coupled to the positive input terminal456of the transconductance amplifier456. Further description of the use of the multiplexer1205for BIST may be found with reference toFIG.12. Further description of the use of the chopper switch1105for controlling polarity of the pulser300may be found with reference toFIG.11.

It should be appreciated from the foregoing discussion that the circuitry illustrated inFIGS.4-13may be used both for built-in self-testing (BIST) of the pulser300and characterizing the CMUT152. Table 1 summarizes configurations for built-in self-testing (BIST) of the pulser300and characterizing of the CMUT152:

TABLE 1Summary of configurations for testing the pulser 300and characterizing the CMUT 152.Input voltage oftransconductanceAmplifier 364Current injectedModeamplifier 454Configurationto amplifier 364Testing Pulser 300VSense− VThres0Closed- Loop (TIA)VS⁢e⁢n⁢s⁢e-VThres⁢0n·RsCharacterizing CMUT 152VThres− VThres0Open-Loop (Comparator)VThres-VThres⁢0n·Rs

FIG.14is an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.14is a simplified version ofFIG.4, except thatFIG.14includes receive circuitry1484instead of the receive circuitry384. The receive circuitry1484(which may be an example of the receive circuitry184) is configurable as a delta-sigma analog-to-digital converter (ADC)1400. Briefly, the delta-sigma ADC1400may be considered a second-order delta-sigma ADC that includes two feedback loops. In operation, during normal imaging, the receive switch162may be closed, and the delta-sigma ADC1400may integrate and then quantize current output from the CMUT152to produce a digital logic level Dout. DOUTmay be a pulse stream in which the frequency of pulses may be proportional to the current inputted to the delta-sigma ADC1400. This frequency may be enforced by the feedback loops of the delta-sigma ADC1400.

The delta-sigma ADC1400includes a transconductance amplifier1480, a capacitor1492, a voltage quantizer1420, a current digital-to-analog converter (DAC)1422, a current digital-to-analog converter (DAC)1486, a switch1487, and a switch1421. The transconductance amplifier1480has an input terminal1482and an output terminal1484. The voltage quantizer1420has an input terminal1428and an output terminal1432. The current DAC1486has an input terminal1488and an output terminal1490. The current DAC1422has an input terminal1434and an output terminal1436.

In the configuration ofFIG.14, the input terminal1482of the transconductance amplifier1480, the output terminal1436of the current DAC1422, and the output terminal460of the transconductance amplifier454are coupled together. (The output terminal1436of the current DAC1422is coupled to this node through the closed switch1421.) The output terminal1484of the transconductance amplifier1480, the output terminal1490of the current DAC1486, a terminal of the capacitor1492, and the input terminal1428of the voltage quantizer1420are coupled together. (The output terminal1490of the current DAC1486is coupled to this node through the closed switch1487.) The other terminal of the capacitor1492is coupled to ground1450. The output terminal1432of the voltage quantizer1420, the input terminal1488of the current DAC1486, and the input terminal1434of the current DAC1422are coupled together. Further aspects of such delta-signal ADCs for converting current output of CMUTs are described in U.S. patent application Ser. No. 16/443,931 titled “APPARATUSES INCLUDING A CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER DIRECTLY COUPLED TO AN ANALOG-TO-DIGITAL CONVERTER,” filed on Jun. 18, 2019, and published on Oct. 3, 2019, as US-2019-0299251-A1 (and assigned to the assignee of the instant application), which is incorporated by reference herein in its entirety.

FIG.14illustrates a non-limiting example of a configuration for testing of the pulser300. In operation, parasitic capacitance at the node at the input terminal1482of the transconductance amplifier1480may integrate the current output from the transconductance amplifier454(which may be a transformed version of the HV output of the pulser300) into a voltage prior to conversion of this voltage back into a current by the transconductance amplifier1480. The capacitor1492may integrate this current into a voltage that may then be quantized by the voltage quantizer1420to produce the digital output Dout. The output Dout of the delta-sigma ADC1400may be output by other circuitry in the receive circuitry1484to an external device for analysis of the operation of the pulser300. The capacitance at the node at the input terminal1482of the transconductance amplifier1480may be lower than when the switch162is closed and the capacitance of the CMUT152is added to the parasitic capacitance at this node. Thus, the stability and linearity of the delta-sigma ADC1400may be degraded. It may be helpful for the transconductance amplifier454's output current to be attenuated further to compensate for the loss in stability and linearity by reducing the signal swing.

FIG.15is an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.15is the same asFIG.14, with the following exceptions:1. The positive input terminal of the transconductance amplifier454is coupled to Thres;2. The switch162is closed;3. The switch1421and the switch1487are open.

FIG.15illustrates a non-limiting example of a configuration for characterizing the CMUT152(e.g., characterizing its capacitance, collapse voltage, and/or stiction). In such a configuration, the pulser300may be kept off, such that it does not output any high-voltage signals. The voltage at Thres may be kept constant, such that the voltage difference between Thres and Thres0 that is inputted to the transconductance amplifier454is constant, and the output current from the transconductance amplifier454is constant. The constant current output from the transconductance amplifier454may be integrated onto the CMUT152to generate a ramp voltage at the input terminal382of the transconductance amplifier1480. The transconductance amplifier1480may convert this voltage to a current. The capacitor1492may integrate this current into a voltage. The quantizer1420, operating as a comparator, may compare the ramp voltage to a reference voltage (referred to as Vref, not illustrated). When the ramp voltage crosses Vref, the output voltage of the amplifier364may switch from high to low or from low to high. If the ramp begins at the voltage of an LV positive power supply (referred to as VDDA) and proceeds to ground350, or if the ramp begins at ground350and proceeds to VDDA, the configuration ofFIG.8may accordingly be used to time how long it takes from the beginning of the ramp to when the ramp cross Vref. The capacitance of the CMUT152may be computed as

C=Iramp×TrampVDDA-Vref,
where Irampramp is the constant current outputted by the transconductance amplifier454and Trampis the time it takes from the beginning of the ramp to when the ramp cross Vref. In some embodiments, two ramps may be used, one during current sourcing and one during current sinking, such that one ramp proceeds from VDDA to ground350(during current sinking) and one proceeds from ground350to VDDA (during current sourcing), and the average of the Trampmeasured for each ramp may be used to compute C. In some embodiments, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sourcing, and these multiple measurements of time may be averaged. Additionally, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sinking, and these multiple measurements of time may be averaged. The two averaged results, one result for current sourcing and one for current sinking, may then be averaged together. Alternatively, the multiple measurements from current sourcing and from current sinking may be averaged together. It should be appreciated that in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sourcing may be performed prior to measuring the time for a ramp voltage to cross a reference voltage during current sinking, while in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sinking may be performed prior to measuring the time for a ramp voltage to cross the reference voltage during current sourcing.

In some embodiments, characterizing the CMUT152may include characterizing the collapse voltage of the CMUT152. Characterizing the collapse voltage of the CMUT152may include applying multiple different bias voltage values VBIASto the CMUT152. The bias voltage VBIASapplied to the CMUT may be measured between the membrane of the CMUT152and the bottom electrode at the substrate of the CMUT152. If the bottom electrode at the substrate of the CMUT152is at virtual ground, then applying VBIASto the CMUT may be accomplished by applying VBIASto the membrane. For each value of VBIAS, the capacitance of the CMUT152may be computed as described above to produce a C vs. VBIAScurve. A discontinuity may be detected in this curve when there is contact between the membrane and the substrate of the CMUT152. If the C vs. VBIAScurve was generated by increasing the value of VBIAS, then the value of VBIASat which this contact occurs (i.e., the value of VBIASat which the discontinuity occurs) may be the collapse voltage of the CMUT152. A discontinuity may be detected in the C vs. VBIAScurve by calculating the first and/or second derivative of the curve.

In some embodiments, characterizing the CMUT152may include characterizing whether the membrane of the CMUT152is stuck to the substrate of the CMUT152. A C vs. VBIAScurve may be generated as described above, and if no discontinuity is detected in the curve, this may mean that the membrane of the CMUT152is stuck to the substrate of the CMUT152. This may be because, for the entire range of VBIASvalues, the membrane is collapsed.

In some embodiments, applying VBIASto the membrane of the CMUT152may include routing the voltage VBIASfrom circuitry in the ultrasound device but external to the substrate on which the CMUT152is disposed, through a routing network, and to the membrane of the CMUT152. It may be helpful to wait for the voltage at the membrane to settle to VBIASafter charging or discharging the routing network.

In some embodiments, the transconductance amplifier454may be used (e.g., using the configuration ofFIG.4or14) to inject a waveform to receive circuitry (e.g., the receive circuitry384or1484or any of the other receive circuitry described herein) for testing of the receive circuitry. In operation, the pulser300may generate a multi-level pulse voltage waveform (e.g., to mimic a sinewave test waveform), an attenuated version of this voltage waveform may be generated at Sense, the transconductance amplifier454may convert this voltage waveform to a current waveform and output this current waveform to the receive circuitry. This may be an accurate and controllable method for injecting a test waveform to the receive circuitry. Additionally, when multiple blocks of circuitry include transconductance amplifiers454, this method may allow for uniformity in generation of waveforms and testing based on the waveforms across the different blocks.

FIG.16Ais an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.16Ais the same asFIG.8, except that the receive switch162is closed, andFIG.16Aincludes a current source1685, a switch1686, a switch1687, and a current source1688and lacks the transconductance amplifier454. The switch1013and the switch1031are open, such that the amplifier364may operate as a comparator. (WhileFIG.16Aillustrates the receive circuitry384, alternatively, the receive circuitry1484may be used.) The current source1685, which it should be appreciated is distinct from the CMUT, is in series with the switch1686and is coupled between a LV power supply382and the negative input terminal368of the amplifier364(which is coupled, through the receive switch162to the node Out). The current source1688is in series with the switch1687and is coupled between the negative input terminal368of the amplifier364and ground350. The current source1685is couplable to the input terminal of the receive circuitry384(in the example ofFIG.16A, to the negative input terminal368of the amplifier364) by closing the switch1686and the current source1688is couplable to the input terminal of the receive circuitry384by closing the switch1687. The current source1685may be configured to supply current to the input terminal of the receive circuitry384and the current source1688may be configured to sink current from the input terminal of the receive circuitry384.

The circuit ofFIG.16Amay be used for characterizing the CMUT152(e.g., characterizing its capacitance, collapse voltage, and/or stiction). In operation, the switch1686may be closed and the switch1687may be opened, such that the current source1685supplies a constant current to the node Out, charging or discharging the CMUT152(depending on the polarity of its membrane voltage) and generating an increasing ramp voltage at the node Out. Alternatively or additionally, the switch1687may be closed and the switch1685may be opened, such that the current source1688sinks a constant current from the node Out, charging or discharging the CMUT152(depending on the polarity of its membrane voltage) and generating a decreasing ramp voltage at the node Out. The amplifier364, operating as a comparator, may compare the ramp voltage to the reference voltage (referred to as Vref) at the positive input terminal366of the amplifier364. When the ramp voltage crosses Vref, the output voltage of the amplifier364may switch from high to low or from low to high. If the ramp begins at the voltage of the LV positive power supply1682(referred to as VDDA) and proceeds to ground350(i.e., the switch1686is closed), or if the ramp begins at ground350and proceeds to VDDA (i.e., the switch1687is closed), the configuration ofFIG.16Amay accordingly be used to measure the time it takes from the beginning of the ramp to when the ramp cross Vref. The capacitance of the CMUT152may be computed as

C=Iramp×TrampVDDA-Vref,
where Irampis the constant current outputted by the current sources1685and/or1688, and Trampis the time it takes from the beginning of the ramp to when the ramp cross Vref. In some embodiments, two ramps may be used, one during current sourcing and one during current sinking, such that one ramp proceeds from VDDA to ground350(during current sinking) and one proceeds from ground350to VDDA (during current sourcing), and the average of the Trampmeasured for each ramp may be used to compute C. In some embodiments, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sourcing, and these multiple measurements of time may be averaged. Additionally, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sinking, and these multiple measurements of time may be averaged. The two averaged results, one result for current sourcing and one for current sinking, may then be averaged together. Alternatively, the multiple measurements from current sourcing and from current sinking may be averaged together. It should be appreciated that in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sourcing may be performed prior to measuring the time for a ramp voltage to cross a reference voltage during current sinking, while in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sinking may be performed prior to measuring the time for a ramp voltage to cross the reference voltage during current sourcing.

In some embodiments, characterizing the CMUT152may include characterizing the collapse voltage of the CMUT152. Characterizing the collapse voltage of the CMUT152may include applying multiple different bias voltage values VBIASto the CMUT152. The bias voltage VBIASapplied to the CMUT may be measured between the membrane of the CMUT152and the bottom electrode at the substrate of the CMUT152. If the bottom electrode at the substrate of the CMUT152is at virtual ground, then applying VBIASto the CMUT may be accomplished by applying VBIASto the membrane. For each value of VBIAS, the capacitance of the CMUT152may be computed as described above to produce a C vs. VBIAScurve. A discontinuity may be detected in this curve when there is contact between the membrane and the substrate of the CMUT152. If the C vs. VBIAScurve was generated by increasing the value of VBIAS, then the value of VBIASat which this contact occurs (i.e., the value of VBIASat which the discontinuity occurs) may be the collapse voltage of the CMUT152. A discontinuity may be detected in the C vs. VBIAScurve by calculating the first and/or second derivative of the curve.

In some embodiments, characterizing the CMUT152may include characterizing whether the membrane of the CMUT152is stuck to the substrate of the CMUT152. A C vs. VBIAScurve may be generated as described above, and if no discontinuity is detected in the curve (e.g., using a first and/or second derivative as described above), this may mean that the membrane of the CMUT152is stuck to the substrate of the CMUT152. This may be because, for the entire range of VBIASvalues, the membrane is collapsed.

In some embodiments, applying VBIASto the membrane of the CMUT152may include routing the voltage VBIASfrom circuitry in the ultrasound device but external to the substrate on which the CMUT152is disposed, through a routing network, and to the membrane of the CMUT152. It may be helpful to wait for the voltage at the membrane to settle to VBIASafter charging or discharging the routing network.

FIG.16Bis an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.16Bis the same asFIG.16A, except that the receive switch162is open, the switch1031is closed such that the amplifier364may be configured as a unity-gain voltage amplifier, the current sources1685and1688are coupled through the switches1686and1687, respectively, to the positive input terminal366of the amplifier364, and a capacitor1689is coupled between the positive input terminal366of the amplifier364and ground350.

In some embodiments, the circuitry ofFIG.16Bmay be used to inject a waveform to the receive circuitry384for testing of the receive circuitry384. In operation, the switch1686may be closed and the switch1687may be opened, such that the current source1685supplies a constant current to the node Vp (i.e., the node at the positive input terminal366of the amplifier364), charging the capacitor1689and generating an increasing ramp voltage at the node Vp. Alternatively or additionally, the switch1687may be closed and the switch1686may be opened, such that the current source1688sinks a constant current from the node Vp, discharging the capacitor1689and generating a decreasing ramp voltage at the node Vp. This ramp voltage may be the waveform injected to the receive circuitry384for testing the receive circuitry384.

FIG.17is an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.17is the same asFIG.3, but with the addition of a capacitor network1717coupled between the pulser300and the receive circuitry384. (WhileFIGS.17and21illustrate the receive circuitry384, alternatively, the receive circuitry1484may be used.) As described above, it may be helpful to analyze the output of the pulser300for testing purposes. While the receive circuitry384may be capable of converting analog voltages to digital codes and outputting the digital codes to an external device where they can be analyzed, it may not be feasible to directly connect the output of the pulser300to the receive circuitry384(e.g., to the TIA365). The output of the pulser300may include pulses that are higher in voltage (e.g., in the HV domain) than the operating voltage of the receive circuitry384(e.g., in the LV domain). The inventors have recognized that, instead, the capacitor network1717may be included between the pulser300and the receive circuitry384for built-in self-testing (BIST). The capacitor network1717may be configured to convert the HV output of the pulser300(or an attenuated version of the output of the pulser300) to an attenuated voltage signal that can be processed and output by the receive circuitry384.

The capacitor network1717includes an input terminal1719and an output terminal1721. The input terminal1719of the capacitor network1717is coupled to the Sense node. The output terminal1721of the capacitor network1717is coupled to the positive input terminal of the amplifier364. The switch1031is closed and the switch1013is open, such that the negative input terminal368of the amplifier364is coupled to the output terminal370of the amplifier364. Thus, the amplifier364may be configured as a unity-gain voltage amplifier. In some embodiments, there may be a voltage buffer between the capacitor network1717and the receive circuitry384.

The capacitor network1717may be used for built-in self-testing (BIST) of circuitry in the ultrasound system.FIG.17illustrates a non-limiting example of a configuration for testing of the pulser300. In operation, the capacitor network1717may be configured to use capacitive division to attenuate the voltage at Sense from the MV domain to the LV domain and to output the LV signal to the receive circuitry384. The capacitor divider consisting of the capacitor346and the parallel combination of the capacitor348and the input capacitance of the capacitor network1717may attenuate the HV signal at Out to the MV signal at Sense, and the capacitor network1717may attenuate the MV signal at Sense to a LV signal at the output terminal1721. In some embodiments, the input capacitance of the capacitor network1717may be such that when the voltage at Out is attenuated by the capacitor divider consisting of the capacitor346and the parallel combination of the capacitor348and the input capacitance of the capacitor network1717, then the attenuation ratio between the voltage at Out and the voltage at Sense is as desired. For example, if the desired attenuation ratio is that the voltage at Sense is 1/N the voltage at Out, then the capacitance of the capacitor346may be C, the capacitance of the capacitor348may be (N−1)C, and the input capacitance of the capacitor network1717may be C.

FIG.18is a circuit diagram of an example capacitor network1817, in accordance with certain embodiments described herein. The capacitor network1817may be used as the capacitor network1717. The capacitor network1817may be configured to attenuate the voltage at Sense by 2 at the node div2, attenuate the voltage at div2 by 2 at the node div4, and attenuate the voltage at div4 by 2 at div8. The capacitor network1817may therefore be configured to provide multiple attenuation options which may be multiplexed to the output of the capacitor network1817(which may be the same as the output terminal1717of the capacitor network1717). The capacitor network1817also includes a node Common that may be at a constant voltage that can be coupled, through switches (not illustrated), to other nodes (e.g., div2, div4, and div8) in the capacitor network1817, in order to reset the voltage across the capacitors.

FIG.19is a circuit diagram of another example capacitor network1917, in accordance with certain embodiments described herein. The capacitor network1917may be used as the capacitor network1717. The capacitor network1917is the same as the capacitor network1817, except that a 2 C and a C capacitor have been removed, such that the capacitor network may not provide the div8 attenuation option.

FIG.20is a circuit diagram of another example capacitor network2017, in accordance with certain embodiments described herein. The capacitor network2017may be used as the capacitor network1717. The capacitor network2017is the same as the capacitor network1817, except that a 2 C and a C capacitor have been added, such that the capacitor network provides an output option for attenuation of div8 by 2 at the node div16. It should be appreciated fromFIGS.18-20that further or fewer attenuation options may be realized by adding or removing a 2 C capacitor and a C capacitor in the manner illustrated.

FIG.21is an example schematic diagram illustrating circuitry in an ultrasound system, in accordance with certain embodiments described herein.FIG.21includes a pulser2100(which may be an example of the pulser100), the capacitive micromachined ultrasonic transducer (CMUT)152, the receive switch162, the receive circuitry384, and a capacitor network217. The capacitor network2117includes an input terminal2119, a first output terminal2121, and a second output terminal2122. The input terminal2119of the capacitor network2117is coupled to the Out node. The second output terminal2122of the capacitor network2117is coupled to the positive input terminal of the amplifier364. The first output terminal2121of the capacitor network2117is coupled to the positive input terminal304of the comparator304. The switch1031is closed and the switch1013is open, such that the negative input terminal368of the amplifier364is coupled to the output terminal370of the amplifier364. Thus, the amplifier364may be connected as a unity-gain voltage amplifier.

The pulser2100is the same as the pulser300, except that the pulser2100lacks the capacitor346and the capacitor348. Instead, the attenuation operation performed by the capacitor346and the capacitor348in the pulser300may be performed by the capacitor network2117. In other words, the capacitor network2117may be configured to receive, as an input, an output signal from the pulser2100and output an attenuated version of the output signal from the pulser2100both to the pulser2100and to the receive circuitry384. In particular, in operation, the capacitor network2117may receive the HV signal at Out at the input terminal2119and output an attenuated, MV pulse signal at the first output terminal2121. In some embodiments, there may be a voltage buffer between the capacitor network2117and the receive circuitry384.

The capacitor network2117may also be used for built-in self-testing (BIST) of circuitry in the ultrasound system.FIG.21illustrates a non-limiting example of a configuration for testing of the pulser2100. In operation, the capacitor network2117may use capacitive division to attenuate the voltage at Out from the HV domain to the LV domain and output the LV signal to the receive circuitry384.

FIG.22is a circuit diagram of an example capacitor network2217, in accordance with certain embodiments described herein. The capacitor network2217may be used as the capacitor network2117. The capacitor network2217may be configured to only output at the node div2 the positive portion of the voltage at Sense such that the attenuation ratio from Out is 2. The capacitor network2217may be configured to output at the node div4 the voltage at div2 attenuated by 2, to output at the node div8 the voltage at div4 attenuated by 2, and to output at the node divX the voltage at div8 attenuated by a factor determined by a capacitor divider consisting of the capacitor coupled to the node divX and the load capacitance (Cload) of the circuit coupled to the node divX (e.g., at the second output terminal2122). For example, the load capacitance may be input capacitance of the amplifier364. In some embodiments, the attenuation ratio from div8 to divX may be approximately equal to C/Cload. In general, the attenuation ratios may depend on Cload being much larger than C. The capacitor network2217may therefore be configured to provide multiple attenuation options which may be multiplexed to the outputs of the capacitor network1817(which may be the same as the first output terminal2121and the second output terminal2122of the capacitor network1717). The voltage at div4 and div8 may be in the MV domain and may therefore be coupled to the positive input terminal304of the comparator302(e.g., through the first output terminal2121). The voltage at divX may be in LV domain and may therefore be coupled to the positive input terminal of the amplifier364(e.g., through the second output terminal2122). The capacitor network2217may also include a node Common at a constant voltage that can be coupled, through switches (not illustrated), to other nodes (e.g., div4, div8, and divX) in the capacitor network2217, in order to reset the voltage across the capacitors. In some embodiments, the capacitor network2217may require fewer units of capacitance than the capacitor network1817in order to perform the same functions.

FIG.23is a circuit diagram of an example capacitor network2317, in accordance with certain embodiments described herein. The capacitor network2317may be used as the capacitor network2117. The capacitor network2317is the same as the capacitor network2217, except that a 2 C and a C capacitor have been removed. The capacitor network2317may therefore provide at attenuation ratio of 2 at div2, an attenuation ratio of 4 at div4, and an attenuation ratio approximately equal to C/Cload at divX.

FIG.24is a circuit diagram of another example capacitor network2417, in accordance with certain embodiments described herein. The capacitor network2417may be used as the capacitor network2117. The capacitor network2417is the same as the capacitor network2217, except that a 2 C and a C capacitor have been added. The capacitor network2217may be configured to output at the node div4 the voltage at div2 attenuated by 2, to output at the node div8 the voltage at div4 attenuated by 2, to output at the node div16 the voltage at div8 attenuated by 2, and to output at the node divX the voltage at div16 attenuated by a factor determined by a capacitor divider consisting of the capacitor coupled to the node divX and the load capacitance (Cload) of the circuit coupled to the node divX (e.g., at the second output terminal2122). For example, the load capacitance may be input capacitance of the amplifier364. In some embodiments, the attenuation ratio from div8 to divX may be approximately equal to C/Cload. In general, the attenuation ratios may depend on Cload being much larger than C. It should be appreciated fromFIGS.22-24that further or fewer attenuation options may be realized by adding or removing a 2 C capacitor and a C capacitor in the manner illustrated.

FIG.25is a circuit diagram of an example capacitor network2517, in accordance with certain embodiments described herein. The capacitor network2517may be used as the capacitor network2117. The capacitor network2517may be configured to only output at the node div2 the positive portion of the voltage at Sense such that the attenuation ratio from Out is 2. The capacitor network2517may be configured to output at the node div4 the voltage at div2 attenuated by 2, to output at the node div8 the voltage at div4 attenuated by 2, and to output at the node divX the voltage at div8 attenuated by a factor determined by a capacitor divider consisting of the capacitor coupled to the node divX and the load capacitance (Cload) of the circuit coupled to the node divX (e.g., at the second input terminal2122). For example, the load capacitance may be input capacitance of the amplifier364. In some embodiments, the attenuation ratio from div8 to divX may be approximately equal to 2 C/Cload. In general, the attenuation ratios may depend on Cload being much larger than C. The capacitor network2517may therefore be configured to provide multiple attenuation options which may be multiplexed to the outputs of the capacitor network1817(which may be the same as the first output terminal2121and the second output terminal2122of the capacitor network1717). The voltage at div4 and div8 may be in the MV domain and may therefore be coupled to the positive input terminal304of the comparator302(e.g., through the first output terminal2121). The voltage at divX may be in LV domain and may therefore be coupled to the positive input terminal of the amplifier364(e.g., through the second output terminal2122). The capacitor network2517may also include a node Common at a constant voltage that can be coupled, through switches (not illustrated), to other nodes (e.g., div4, div8, and divX) in the capacitor network2517, in order to reset the voltage across the capacitors. In some embodiments, to remove an attenuation ratio from the capacitor network2517, the capacitor network2317may be used.

FIG.26is a circuit diagram of another example capacitor network2617, in accordance with certain embodiments described herein. The capacitor network2617may be used as the capacitor network2117. The capacitor network2617is the same as the capacitor network2517, except that a 2 C and a C capacitor have been added. The capacitor network2617may be configured to output at the node div4 the voltage at div2 attenuated by 2, to output at the node div8 the voltage at div4 attenuated by 2, to output at the node div16 the voltage at div8 attenuated by 2, and to output at the node divX the voltage at div16 attenuated by a factor determined by a capacitor divider consisting of the capacitor coupled to the node divX and the load capacitance (Cload) of the circuit coupled to the node divX (e.g., at the second output terminal2122). For example, the load capacitance may be input capacitance of the amplifier364. In some embodiments, the attenuation ratio from div8 to divX may be approximately equal to 2 C/Cload. It should be appreciated fromFIGS.25-26that further or fewer attenuation options may be realized by adding or removing a 2 C capacitor and a C capacitor in the manner illustrated. It should also be appreciated fromFIGS.22-26that the attenuation ratio of the last stage may be modulated by modulating the capacitor at the last stage. Depending of the attenuation ratios desired and the voltage levels involved, one of the capacitor networks inFIGS.22-26and a capacitance for the last stage may be selected.

FIGS.27-34illustrate ultrasound devices and substrates containing circuitry that may be included in the ultrasound devices. As examples, a substrate may include a semiconductor chip, a printed circuit board, a microprocessor, or a field-programmable gate array (FPGA). It should be appreciated that, as illustrated inFIGS.27-34, any of the illustrated circuitry may be integrated circuitry on a substrate (e.g., on a semiconductor chip). Thus, in some embodiments, BIST circuitry may be integrated circuitry that is integrated on the same substrate (e.g., a semiconductor chip) as other integrated ultrasound circuitry such as a pulsers and/or receive circuitry.

FIG.27is a block diagram of an ultrasound circuitry2727, in accordance with certain embodiments described herein. The ultrasound circuitry2727includes a substrate2721. The substrate2721includes the pulser100, the CMUT152, the receive circuitry184, and a built-in self-test (BIST) circuit2719. The BIST circuit2719may be the transconductance amplifier454, the capacitor network1717, the capacitor network2117, the current source1685, the current source1688, and/or the capacitor1689. The output of the pulser100is coupled to the inputs of the CMUT152and the BIST circuit2719. The output of the CMUT152is coupled to the input of the receive circuitry184. The output of the BIST circuit2719is coupled to the input of the receive circuitry184.

FIG.28is a block diagram of another example of ultrasound circuitry2827, in accordance with certain embodiments described herein. The ultrasound circuitry2827is the same as the ultrasound circuitry2727, except that the ultrasound circuitry2827includes a substrate2821and a substrate2823instead of the substrate2721. The pulser100, the BIST circuit2719, and the receive circuitry184are disposed in the substrate2821and the CMUT152is disposed in the substrate2823. In some embodiments, the substrate2821and the substrate2823may be bonded together, and the CMUT152may be electrically coupled to the pulser100and the receive circuitry184through bonding points.

FIG.29is a block diagram of another example of ultrasound circuitry2927, in accordance with certain embodiments described herein. The ultrasound circuitry2927is the same as the ultrasound circuitry2727, except that the ultrasound circuitry2927includes a substrate2921and a substrate2925instead of the substrate2721. The pulser100, the BIST circuit2719, and the CMUT152are disposed in the substrate2921and the receive circuitry184is disposed in the substrate2925. In some embodiments, the substrate2921and the substrate2925may be bonded together, and the receive circuitry184may be electrically coupled to the BIST circuit2719and the CMUT152through bonding points.

FIG.30is a block diagram of another example of ultrasound circuitry3027, in accordance with certain embodiments described herein. The ultrasound circuitry3027is the same as the ultrasound circuitry2927, except that the ultrasound circuitry3027includes a substrate3021instead of the substrate2921and a substrate3025instead of the substrate2925. The pulser100and the CMUT152are disposed in the substrate3021and the BIST circuit2719and the receive circuitry184are disposed in the substrate2925. In some embodiments, the substrate3021and the substrate3025may be bonded together, and the pulser100may be electrically coupled to the BIST circuit2719and the CMUT152may be electrically coupled to the receive circuitry184through bonding points.

FIG.31is a block diagram of another example of ultrasound circuitry3127, in accordance with certain embodiments described herein. The ultrasound circuitry3127includes a substrate3121and a substrate3125. The substrate3121includes the pulser100, the CMUT152, the BIST circuit2719, receive circuitry3129, and receive circuitry3131. The receive circuitry3129and the receive circuitry3131may represent division of the receive circuitry184into two blocks. The output of the pulser100is coupled to the inputs of the CMUT152and the BIST circuit2719. The output of the CMUT152is coupled to the input of the receive circuitry3129. The output of the BIST circuit2719is coupled to the input of the receive circuitry3129. The output of the receive circuitry3129is coupled to the input of the receive circuitry3131. In some embodiments, the substrate3121and the substrate3125may be bonded together, and the receive circuitry3129may be electrically coupled to the receive circuitry3131through bonding points. In some embodiments, the substrate3121and the substrate3125may be electrically coupled through one or more communication links, and the receive circuitry3129may be electrically coupled to the receive circuitry3131through the communication links. In some embodiments, the receive circuitry3129may include a transimpedance amplifier and/or an analog-to-digital converter (ADC) and the receive circuitry3131may include digital processing circuitry (although the receive circuitry3129and the receive circuitry3131may include other circuitry as well). In some embodiments, the receive circuitry3129may include a preamplifier, time-gain compensation (TGC) circuitry, and/or analog beamforming circuitry, and the receive circuitry3131may include a transimpedance amplifier, an analog-to-digital converter (ADC), and/or digital processing circuitry (although the receive circuitry3129and the receive circuitry3131may include other circuitry as well).

FIG.32is a block diagram of another example of ultrasound circuitry3227, in accordance with certain embodiments described herein. The ultrasound circuitry3227includes a substrate3221, the substrate2823, and the substrate2925. The pulser100and the BIST circuit2719are disposed in the substrate3221. In some embodiments, the substrate3221and the substrate2823may be bonded together, and the substrate3221and the substrate2925may be bonded together. In such embodiments, the CMUT152may be electrically coupled to the pulser100and the receive circuitry184through bonding points.

FIG.33is a block diagram of another example of ultrasound circuitry3327, in accordance with certain embodiments described herein. The ultrasound circuitry3327includes a substrate3321, the substrate2823, and the substrate3325. The pulser100is disposed in the substrate AF21 and the BIST circuit2719and the receive circuitry184are disposed in the substrate3325. In some embodiments, the substrate3321and the substrate2823may be bonded together, and the substrate33V21and the substrate3325may be bonded together. In such embodiments, the CMUT152may be electrically coupled to the pulser100and the receive circuitry184through bonding points, and the pulser100may be electrically coupled to the BIST circuit2719through bonding points.

FIG.34is a block diagram of another example of ultrasound circuitry3427, in accordance with certain embodiments described herein. The ultrasound circuitry3427includes a substrate3421, the substrate2823, and the substrate3125. The pulser100, the BIST circuit2719, and the receive circuitry3129are disposed in the substrate3421. In some embodiments, the substrate3421and the substrate2823may be bonded together, and the CMUT152may be electrically coupled to the pulser100and the receive circuitry3129through bonding points. In some embodiments, the substrate3421and the substrate3125may be bonded together, and the receive circuitry3129may be electrically coupled to the receive circuitry3131through bonding points. In some embodiments, the substrate3421and the substrate3125may be electrically coupled through one or more communication links, and the receive circuitry3129may be electrically coupled to the receive circuitry3131through the communication links.

In any of the substrates described herein, the pulser100, the BIST circuit2719, the receive circuitry184, the receive circuitry3129, and/or the receive circuitry3131may be integrated circuitry fabricated in the substrate (e.g., in a semiconductor chip). Additionally, in any of the substrates described herein that include such integrated circuitry and the CMUT152, the CMUT152may be fabricated in the substrate after the integrated circuitry has been fabricated in the substrate.

It should be appreciated that in any of the ultrasound devices described herein that include two or more substrates, any or all of the substrates may be included in a single package. Thus, the BIST circuit2719, the receive circuitry, CMUT152, and the pulser100may be disposed within a single package. The BIST circuit2719may thus be included in the final ultrasound device product, despite potentially not being used once the ultrasound device is in the hands of consumers.

FIG.35Aillustrates a flow diagram for a process3500A for testing a pulser in an ultrasound device, in accordance with certain embodiments described herein. The process3500A may be performed by operating a transconductance amplifier (e.g., the transconductance amplifier454) coupled between a pulser (e.g., the pulser300) and receive circuitry (e.g., the receive circuitry184, the receive circuitry384, or the receive circuitry1484) in an ultrasound device (e.g., the ultrasound device4402described below).

In act3502A, the transconductance amplifier is operated to convert a voltage outputted by the pulser in the ultrasound device to a current. The process3500A proceeds from act3502A to act3504A.

In act3504A, the transconductance amplifier is operated to output the current to the receive circuitry (e.g., to a TIA (e.g., the TIA365) or to a delta-sigma ADC (e.g., the delta-sigma ADC1400) in the receive circuitry) in the ultrasound device. In some embodiments, after testing the pulser, the transconductance amplifier may be shut off while the pulser and the receive circuitry remain on. Further description of circuitry that may be configured to perform the process3500A may be found with reference toFIGS.4-7and10-14. The process3500A may also be used for testing the receive circuitry as described after the description ofFIG.15.

FIG.35Billustrates a flow diagram for a process3500B for testing receive circuitry (e.g., the receive circuitry384) in an ultrasound device, in accordance with certain embodiments described herein. The process3500B may be performed by operating current sources (e.g., the current sources1685and1688) each coupled through a switch (e.g., the switches1686and1687) to a capacitor (e.g., the capacitor1689) and to an input terminal of the receive circuitry (i.e., the positive input terminal366of the amplifier364).

In act3502B, the current sources and switches are operated to generate a current. For example, one of the switches may be closed and the other switch may be opened, such that one of the current sources supplies a constant current to the capacitor and charges the capacitor, generating an increasing ramp voltage at the input terminal of the receive circuitry. Alternatively or additionally, the switch may be opened and the other switch may be closed, such that the other current sources supplies a constant current to the capacitor and discharges the capacitor, generating an decreasing ramp voltage at the input terminal of the receive circuitry.

In act3504B, the ramp voltage generated in act3502B is output to the receive circuitry (e.g., to an amplifier (e.g., the amplifier364) configured as a unity-gain buffer) in the ultrasound device. This ramp voltage may be the waveform injected to the receive circuitry384for testing the receive circuitry384.

FIG.36illustrates a flow diagram for a process3600for testing a pulser in an ultrasound device, in accordance with certain embodiments described herein. The process3600may be performed by operating a capacitor network (e.g., the capacitor network1717or the capacitor network2117) coupled between a pulser (e.g., the pulser300or the pulser2100) and receive circuitry (e.g., the receive circuitry184, the receive circuitry384, or the receive circuitry1484) in an ultrasound device (e.g., the ultrasound device4402described below).

In act3602, the capacitor network is operated to attenuate a voltage outputted by the pulser in the ultrasound device. The process3600proceeds from act3602to act3604.

In act3604, the capacitor network is operated to output the attenuated voltage to the receive circuitry (e.g., to a unity-gain amplifier in the receive circuitry) in the ultrasound device. In some embodiments, the capacitor network may also output an attenuated version of the output of the pulser back to the pulser itself. Further description of circuitry that may be configured to perform the process3600may be found with reference toFIGS.17-26.

FIG.37illustrates a flow diagram for a process3700for characterizing a capacitive micromachined ultrasonic transducer (CMUT) (e.g., the CMUT352), in accordance with certain embodiments described herein. For example, the characterization may be characterization of the CMUT's capacitance. The process3700may be performed by operating a transconductance amplifier (e.g., the transconductance amplifier454) coupled to receive circuitry (e.g., the receive circuitry184, the receive circuitry384, or the receive circuitry1484) in an ultrasound device (e.g., the ultrasound device4402described below). An input terminal of the receive circuitry is electrically coupled to the CMUT. For example, to electrically couple the CMUT to the input terminal of the receive circuitry, a switch (e.g., the receive switch362) between the CMUT and the input terminal of the receive circuitry may be closed.

In act3702, the transconductance amplifier is operated to generate a current. For example, the transconductance amplifier may accept constant voltages at its inputs and output a constant current based on the difference between the two inputted voltages. The process3700proceeds from act3702to act3704.

In act3704, the transconductance amplifier is operated to inject the current to the input terminal of the receive circuitry (e.g., to an amplifier configured as a comparator). The current may charge or discharge the CMUT to generate a ramp voltage. The ramp may begin at the voltage VDDA of a positive power supply and proceed to ground or begin at ground and proceed to VDDA. The receive circuitry (e.g., a comparator in the receive circuitry) may be used to measure the time Trampit takes for the ramp voltage to cross a reference voltage Vref. The capacitance of the CMUT may be computed as

C=Iramp×TrampVDDA-Vref,
where Irampis the constant current generated by the transconductance amplifier and Trampis the time it takes from the beginning of the ramp to when the ramp cross the reference voltage Vref. In some embodiments, after characterizing the CMUT, the transconductance amplifier may be shut off while the pulser and the receive circuitry remain on. Further description of circuitry that may be configured to perform the process3700may be found with reference toFIGS.8-13and15.

In some embodiments, the same transconductance amplifier coupled between the pulser and the receive circuitry may be used to test the pulser and to characterize the CMUT in the ultrasound device.FIG.38illustrates a flow diagram for a process3800for testing a pulser in an ultrasound device, in accordance with certain embodiments described herein. The process3800may be performed by operating a transconductance amplifier (e.g., the transconductance amplifier454) coupled between a pulser (e.g., the pulser300) and receive circuitry (e.g., the receive circuitry184, the receive circuitry384, or the receive circuitry1484) in an ultrasound device (e.g., the ultrasound device4402described below).

In act3802, the transconductance amplifier is operated to convert a first voltage outputted by the pulser in the ultrasound device to a first current. The process3800proceeds from act3802to act3804.

In act3804, the transconductance amplifier is operated to output the first current to the receive circuitry (e.g., to an amplifier configured as a TIA (e.g., the TIA365) in the receive circuitry) in the ultrasound device. Further description of circuitry that may be configured to perform the acts3802-3804may be found with reference toFIGS.4-7and10-14.

In act3806, the transconductance amplifier is operated to generate a second current. For example, the transconductance amplifier may accept constant voltages at its inputs and output a constant current based on the difference between the two inputted voltages. The process3800proceeds from act3806to act3808.

In act3808, the transconductance amplifier is operated to inject the second current to an input terminal of the receive circuitry (e.g., to an amplifier (e.g., the amplifier364) configured as a comparator). The input terminal of the receive circuitry is electrically coupled to the CMUT. For example, to electrically couple the CMUT to the input terminal of the receive circuitry, a switch (e.g., the receive switch362) between the CMUT and the input terminal of the receive circuitry may be closed. The second current may charge or discharge the CMUT to generate a ramp voltage. The ramp may begin at the voltage VDDA of a positive power supply and proceed to ground or begin at ground and proceed to VDDA. The receive circuitry (e.g., a comparator in the receive circuitry) may be used to measure the time Trampit takes for the ramp voltage to cross a reference voltage Vref. The capacitance of the CMUT may be computed as

C=Iramp×TrampVDDA-Vref,
where Irampis the constant current generated by the transconductance amplifier and Trampis the time it takes from the beginning of the ramp to when the ramp cross the reference voltage Vref. Further description of circuitry that may be configured to perform the acts3806-3808may be found with reference toFIGS.8-13and15. In some embodiments, acts3806-3808may be performed before acts3802-3804.

In some embodiments, a process for characterizing a CMUT (e.g., the CMUT352) may include operating a current source (e.g., the current source1685or1688) in the ultrasound device to inject a current to an input terminal of receive circuitry (e.g., to an amplifier (e.g., the amplifier364) configured as a comparator). The input terminal is electrically coupled to the CMUT. For example, to electrically couple the CMUT to the input terminal of the receive circuitry, a switch (e.g., the receive switch362) between the CMUT and the input terminal of the receive circuitry may be closed. The current may charge or discharge the CMUT to generate a ramp voltage. The ramp may begin at the voltage VDDA of a positive power supply and proceed to ground or begin at ground and proceed to VDDA. The receive circuitry (e.g., a comparator in the receive circuitry) may be used to measure the time Trampit takes for the ramp voltage to cross a reference voltage Vref. The capacitance of the CMUT may be computed as

C=Iramp×TrampVDDA-Vref,
where Irampis the constant current generated by the transconductance amplifier and Trampis the time it takes from the beginning of the ramp to when the ramp cross the reference voltage Vref. In some embodiments, one current source may source a first current to the input terminal of the receive circuitry to charge or discharge the CMUT and generate a first ramp voltage. A first time for the first ramp voltage to cross a reference voltage may be measured. A second current source may sink a second current from the input terminal of the receive circuitry to charge or discharge the CMUT and generate a second ramp voltage. A second time for the second ramp voltage to cross the reference voltage may be measured. Both the first and second time may be used to compute the capacitance (e.g., by averaging the first and second times and using the above equation). In some embodiments, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sourcing, and these multiple measurements of time may be averaged. Additionally, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sinking, and these multiple measurements of time may be averaged. The two averaged results, one result for current sourcing and one for current sinking, may then be averaged together. Alternatively, the multiple measurements from current sourcing and from current sinking may be averaged together. It should be appreciated that in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sourcing may be performed prior to measuring the time for a ramp voltage to cross a reference voltage during current sinking, while in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sinking may be performed prior to measuring the time for a ramp voltage to cross the reference voltage during current sourcing. Further description of circuitry that may be configured to perform such a process may be found with reference toFIG.16A.

FIG.39illustrates a process3900for performing measurements in order to determine the collapse voltage of a CMUT (e.g., the CMUT152), in accordance with certain embodiments described herein. The process3900may be performed by an ultrasound device (e.g., the ultrasound device4402described below).

In act3902, the ultrasound device applies a bias voltage VBIASto a CMUT. The bias voltage VBIASapplied to the CMUT may be measured between the membrane of the CMUT and the bottom electrode at the substrate of the CMUT. If the bottom electrode at the substrate of the CMUT is at virtual ground, then applying VBIASto the CMUT may be accomplished by applying VBIASto the membrane. In some embodiments, the ultrasound device may use a DC-DC converter (e.g., the DC-DC converter4339described below) to apply the bias voltage VBIASto the membrane of the CMUT.

In some embodiments, applying VBIASto the membrane of the CMUT may include routing the voltage VBIASfrom circuitry (e.g., the DC-DC converter4339described below) in the ultrasound device but external to the substrate on which the CMUT is disposed, through a routing network, and to the membrane of the CMUT. It may be helpful to wait for the voltage at the membrane to settle to VBIASafter charging or discharging the routing network.

In act3904, the ultrasound device measures a capacitance or a parameter related to the capacitance of the CMUT at the bias voltage applied in act3902. In some embodiments, the ultrasound device may perform act3904by operating a transconductance amplifier (e.g., the transconductance amplifier454) coupled to receive circuitry (e.g., the receive circuitry184, the receive circuitry384, or the receive circuitry1484) in the ultrasound device. An input terminal of the receive circuitry is electrically coupled to the CMUT. For example, to electrically couple the CMUT to the input terminal of the receive circuitry, a switch (e.g., the receive switch362) between the CMUT and the input terminal of the receive circuitry may be closed. The transconductance amplifier may be operated to generate a current. For example, the transconductance amplifier may accept constant voltages at its inputs and output a constant current Trampbased on the difference between the two inputted voltages. The transconductance amplifier may be operated to inject the current to the input terminal of the receive circuitry (e.g., to an amplifier configured as a comparator). The current may charge or discharge the CMUT to generate a ramp voltage. If the ramp begins at the voltage of an LV positive power supply (referred to as VDDA) and proceeds to ground, or if the ramp begins at ground and proceeds to VDDA, the ultrasound device may use the receive circuitry (e.g., a comparator in the receive circuitry) to measure the time Trampthat it takes from the beginning of the ramp to when the ramp crosses a reference voltage Vref. In some embodiments, two ramps may be used, one during current sourcing and one during current sinking, such that one ramp proceeds from VDDA to ground (during current sinking) and one proceeds from ground to VDDA (during current sourcing), and the average of the Trampmeasured for each ramp may be used to compute C. In some embodiments, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sourcing, and these multiple measurements of time may be averaged. Additionally, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sinking, and these multiple measurements of time may be averaged. The two averaged results, one result for current sourcing and one for current sinking, may then be averaged together. Alternatively, the multiple measurements from current sourcing and from current sinking may be averaged together. It should be appreciated that in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sourcing may be performed prior to measuring the time for a ramp voltage to cross a reference voltage during current sinking, while in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sinking may be performed prior to measuring the time for a ramp voltage to cross the reference voltage during current sourcing.

In some embodiments, the ultrasound device may operate a current source (e.g., the current source1685or1688) to inject a current to an input terminal of receive circuitry (e.g., to an amplifier (e.g., the amplifier364) configured as a comparator). The input terminal is electrically coupled to the CMUT. For example, to electrically couple the CMUT to the input terminal of the receive circuitry, a switch (e.g., the receive switch362) between the CMUT and the input terminal of the receive circuitry may be closed. The current may charge or discharge the CMUT to generate a ramp voltage. The receive circuitry (e.g., a comparator in the receive circuitry) may be used to measure the time Trampit takes for the ramp voltage to cross a reference voltage Vref. In some embodiments, one current source may source a first current to the input terminal of the receive circuitry to charge or discharge the CMUT and generate a first ramp voltage. A first time Trampfor the first ramp voltage to cross a reference voltage may be measured. A second current source may sink a second current from the input terminal of the receive circuitry to charge or discharge the CMUT and generate a second ramp voltage. A second time Trampfor the second ramp voltage to cross the reference voltage may be measured. Both the first and second times Trampmay be used to compute the capacitance (e.g., by averaging the Trampvalues). In some embodiments, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sourcing, and these multiple measurements of time may be averaged. Additionally, multiple repeated measurements of the time for ramp voltages to cross the reference voltage may be performed during current sinking, and these multiple measurements of time may be averaged. The two averaged results, one result for current sourcing and one for current sinking, may then be averaged together. Alternatively, the multiple measurements from current sourcing and from current sinking may be averaged together. It should be appreciated that in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sourcing may be performed prior to measuring the time for a ramp voltage to cross a reference voltage during current sinking, while in some embodiments, measuring the time for a ramp voltage to cross the reference voltage during current sinking may be performed prior to measuring the time for a ramp voltage to cross the reference voltage during current sourcing.

The capacitance of the CMUT may be computed based on Trampas

C=Iramp×TrampVDDA-Vref.
In some embodiments, the ultrasound device may measure Trampbut not use Trampto measure C. In some embodiments, the ultrasound device itself may use Trampto measure C. Further description of circuitry that may be configured to perform the act3904may be found with reference toFIGS.8-13and15-16.

The ultrasound device may repeat acts3902and3904by choosing a new bias voltage VBIASto apply to the CMUT at act3902and repeating the measurement at the new bias voltage at act3904. In some embodiments, the ultrasound device may use increasing values of the bias voltage. At act3906, if there is an additional bias voltage to apply, the ultrasound device returns back to act3902and applies the new bias voltage. If there is not an additional bias voltage to apply, the process3900terminates.

In some embodiments, the values of the capacitance C of the CMUT or the values of the parameter (e.g., Tramp) related to the capacitance of the CMUT at each of the bias voltages VBIASmay represent a C vs. VBIAScurve. In some embodiments, the ultrasound device may transmit the measurements of the capacitance or of the parameter (e.g., Tramp) related to the capacitance of the CMUT to a processing device (e.g., the processing device4404described below) which is in operative communication with the ultrasound device. For example, the ultrasound device may transmit the processing device over a wired communication link (e.g., over Ethernet, a Universal Serial Bus (USB) cable or a Lightning cable) or over a wireless communication link (e.g., over a BLUETOOTH, WiFi, or ZIGBEE wireless communication.

FIG.40illustrates a process4000for determining the collapse voltages of one or more CMUTs (e.g., one of which may be the CMUT152) and applying a bias voltage to the CMUTs, in accordance with certain embodiments described herein. The process4000may be performed by a processing device (e.g., the processing device4404described below). The processing device may be in operative communication with an ultrasound device (e.g., the ultrasound device4402described below). For example, the processing device may be a mobile phone, tablet, or laptop. The ultrasound device and the processing device may communicate over a wired communication link (e.g., over Ethernet, a Universal Serial Bus (USB) cable or a Lightning cable) or over a wireless communication link (e.g., over a BLUETOOTH, WiFi, or ZIGBEE wireless communication link). In some embodiments, the process4000may be performed by the ultrasound device.

In act4002, the processing device receive sets of measurements of capacitances or a parameter related to the capacitances of one or more CMUTs at each of multiple bias voltages applied to the CMUTs. Further description of such measurements may be found above with reference to the process3900. As described above, the ultrasound device may measure Tramp, which can be used to compute C. In some embodiments, for each of the multiple CMUTs, the processing device may receive a set of measurements of Trampat multiple bias voltages. In some embodiments, the set of measurements of Trampmay have been collected at increasing bias voltages. In some embodiments, for each of the multiple CMUTs, the processing device may receive a set of measurements of C at multiple increasing bias voltages. The ultrasound device may transmit the sets of measurements to the processing device over a wired communication link (e.g., over Ethernet, a Universal Serial Bus (USB) cable or a Lightning cable) or over a wireless communication link (e.g., over a BLUETOOTH, WiFi, or ZIGBEE wireless communication. In some embodiments, the multiple CMUTs may be all the CMUTs in a CMUT array on the ultrasound device. In some embodiments, the multiple CMUTs may be a subset of the CMUTs in a CMUT array on the ultrasound device.

In act4004, the processing device determines collapse voltages of the one or more CMUTs based on the capacitances of the CMUTs at each of the multiple bias voltages received in act4002. In embodiments in which the processing device receives sets of measurements of Trampat multiple bias voltages, the processing device may compute C at each of the bias voltages for each CMUT using the equation

C=Iramp×TrampVDDA-Vref,
where Irampis the constant current inputted to the CMUT that generates the ramp voltage from ground to the voltage of the positive power supply VDDA or from VDDA to ground and Trampis the time it takes from the beginning of the ramp to when the ramp cross the reference voltage Vref. As described above, in some embodiments, the ultrasound device may measure multiple values for Trampat a single bias voltage for each CMUT; for example, the ultrasound device may measure one value for an increasing ramp voltage and another value for a decreasing ramp voltage. In such embodiments, the processing device may average the multiple values of Trampand use the averaged value to compute C for each CMUT.

The measurements of C at each of the bias voltages VBIASmay constitute a C vs. VBIAScurve for each CMUT. A discontinuity may be observed in this curve when there is contact between the membrane and the substrate of the CMUT. If the C vs. VBIAScurve was generated by increasing the value of VBIAS, then the value of VBIASat which this contact occurs (i.e., the value of VBIASat which the discontinuity occurs) may be the collapse voltage of the CMUT152. The processing device may thus determine the collapse voltage of each CMUT by computing the first or second derivative of the C vs. VBIAScurve and determining where a discontinuity occurs in the curve. The processing device may calculate the first and/or second derivative of the C vs. VBIAScurve in order to determine where the discontinuity occurs.

In act4006, the processing device causes a bias voltage to be applied to the one or more CMUTs based at least in part on the collapse voltages of the one or more CMUTs. The bias voltage applied to the CMUT may be measured between the membranes of the CMUTs and the bottom electrodes at the substrates of the CMUTs. If the desired bias voltage is VBIAS, and the bottom electrodes at the substrates of the CMUTs are at virtual ground, then applying VBIASto the CMUT may be accomplished by applying VBIASto the membrane. In some embodiments, the processing device may compute the average of the collapse voltages of the CMUTs that were computed in act4004and cause a bias voltage to be applied to the CMUTs that is greater than the average of the collapse voltages by a particular offset voltage. Thus, the same bias voltage may be applied to each of the CMUTs. In some embodiments in which the same bias voltage is applied to each of the CMUTs, each of the CMUTs may share one membrane. Alternatively, the processing device may cause different bias voltages to be applied to different CMUTs. For example, if one group of CMUTs shares one membrane and another group of CMUTs shares another membrane, then the processing device may calculate the average collapse voltage for each group and cause a bias voltage to be applied to each group that is greater than that group's average collapse voltage by the particular offset voltage. As another example, if each CMUT has its own membrane, the processing device may cause a bias voltage to be applied to each CMUT that is greater than that CMUT's collapse voltage by the particular offset voltage. In some embodiments, when computing the average of the collapse voltages of multiple CMUTs, the processing device may exclude from the computation those CMUTs having membranes that are stuck to their substrates. The processing device may determine which CMUTs are stuck based on determining that the CMUTs' C vs. VBIAScurves do not have discontinuities.

In some embodiments, the offset voltage may be approximately equal to or between 20-30V. For example, the offset voltage may be approximately equal to 25, 26, 27, 28, 29, or 30V. In some embodiments, the offset voltage may be approximately equal to or between 20-45V. For example, the offset voltage may be approximately equal to 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, or 35V. However, other suitable offset voltages may be used. In some embodiments, a different offset voltage may be used when imaging different anatomical regions. For example, different presets (i.e., where each preset is a predetermined set of imaging parameters optimized for imaging a particular anatomical region) may use different offset voltages. Applying a bias voltage to the CMUTs that is a particular offset voltage greater than the average of the collapse voltages of the CMUTs may help to ensure that, as the collapse voltages of the CMUTs change with time, the value of the bias voltage applied to the CMUTs minus the average of the collapse voltages of the CMUTs remains the same. This may help to increase the acoustic efficiency of the CMUT. The processing device may transmit an instruction to the ultrasound device to apply the bias voltage over a wired communication link (e.g., over Ethernet, a Universal Serial Bus (USB) cable or a Lightning cable) or over a wireless communication link (e.g., over a BLUETOOTH, WiFi, or ZIGBEE wireless communication. In some embodiments, the ultrasound device may use a DC-DC converter (e.g., the DC-DC converter4339described below) to apply the bias voltage VBIASto the membrane of the CMUT.

FIG.41illustrates a process4100for generating a notification based on measurements of capacitance of CMUTs (e.g., one of which may be the CMUT152), in accordance with certain embodiments described herein. The process4100may be performed by a processing device (e.g., the processing device4404described below). The processing device may be in operative communication with an ultrasound device (e.g., the ultrasound device4402described below). For example, the processing device may be a mobile phone, tablet, or laptop. The ultrasound device and the processing device may communicate over a wired communication link (e.g., over Ethernet, a Universal Serial Bus (USB) cable or a Lightning cable) or over a wireless communication link (e.g., over a BLUETOOTH, WiFi, or ZIGBEE wireless communication link). In some embodiments, the process4100may be performed by the ultrasound device.

In act4102, the processing device receive sets of measurements of capacitance or a parameter related to the capacitance of multiple CMUTs at each of multiple bias voltages applied to the multiple CMUTs. The act4102is the same as the act4002. In some embodiments, the multiple CMUTs may be all the CMUTs in a CMUT array on the ultrasound device. In some embodiments, the multiple CMUTs may be a subset of the CMUTs in a CMUT array on the ultrasound device. As described above, in some embodiments, the ultrasound device may measure Tramp, which can be used to compute C, the capacitance of a CMUT at a given bias voltage. In some embodiments, at act4102, the processing device may receive a set of measurements of Trampat multiple bias voltages for each of the multiple CMUTs. In some embodiments, at act4102, the processing device may receive a set of measurements of C at multiple bias voltages for each of the multiple CMUTs.

In embodiments in which the processing device receives sets of measurements of Trampat multiple bias voltages, the processing device may compute C at each of the bias voltages for each CMUT using the equation

C=Iramp×TrampVDDA-Vref,
where Irampis the constant current inputted to the CMUT that generates the ramp voltage from ground to the voltage of the positive power supply VDDA or from VDDA to ground and Trampis the time it takes from the beginning of the ramp to when the ramp cross the reference voltage Vref. As described above, in some embodiments, the ultrasound device may measure multiple values for Trampat a single bias voltage for each CMUT; for example, the ultrasound device may measure one value for an increasing ramp voltage and another value for a decreasing ramp voltage. In such embodiments, the processing device may average the multiple values of Trampand use the averaged value to compute C for each CMUT. The measurements of C at each of the bias voltages VBIASmay constitute a C vs. VBIAScurve for each CMUT.

If the membrane of a CMUT is stuck to its substrate, the CMUT's C vs. VBIAScurve may not have a discontinuity. This may be because, for the entire range of VBIASvalues, the membrane is collapsed. Thus, in some embodiments, the processing device may determine whether the membrane of a CMUT is stuck to its substrate (referred to for simplicity as a CMUT being “stuck”) by determining whether a discontinuity occurs in the C vs. VBIAScurve. The processing device may determine whether a discontinuity occurs by computing the derivative (e.g., first or second derivative) of the C vs. VBIAScurve. The processing device may then count how many CMUTs are stuck. In some embodiments, if this number exceeds a threshold, the processing device may generate a notification as described with reference to act4104. In some embodiments, based on this count, the processing device may then determine what percentage of the CMUTs from which measurements were collected are stuck and/or what percentage of the CMUTs in the CMUT array are stuck. If this percentage exceeds a threshold, the processing device may generate a notification as described with reference to act4104. The threshold percentage may be, for example, approximately equal to or between 0.1%-0.5%, 0.1%-1%, 0.1%-5%, 0.1%-10%, 0.1%-15%, 0.1%-20%, 0.1%-25%, 0.5%-1%, 0.5%-5%, 0.5%-10%, 0.5%-15%, 0.5%-20%, 0.5%-25%, 1-25%, 5-25%, 10-25%, 15-25%, 20-25%, 1-20%, 5-20%, 10-20%, 15-20%, 1-15%, 5-15%, 10-15%, 1-10%, or 1-5%. As specific examples, the threshold percentage may be approximately equal to 1%, 5%, 10%, 15%, 20%, or 25%, although other suitable thresholds may be used.

In act4104, the processing device generates a notification based on the sets of measurements received in act4102. As described above, the processing device may generate the notification if a percentage of stuck CMUTs exceeds a threshold, and the percentage of stuck CMUTs may be determined based on the sets of measurement received in act4102, as described above. The notification may be, for example, that the ultrasound device should be replaced. In some embodiments, the processing device may generate the notification on its own display screen for the user. In some embodiments, the processing device may transmit, over a wireless network, a notification to a supplier of the ultrasound device that the ultrasound device should be replaced.

FIG.42illustrates a schematic diagram of a CMUT4252(which may be the same as the CMUT152), in accordance with certain embodiments described herein. The CMUT4252includes a membrane4233and a substrate4235. The substrate4235includes an electrode4237. InFIG.42, the membrane4233is collapsed onto the substrate4235, such that the membrane4233contacts the substrate4235. The static membrane deflection profile at a DC bias voltage (VBIAS) across the CMUT4252is determined by the applied electrical force and the restoring force of the membrane4233. Without being limited by theory, the capacitance C of the CMUT4252can be calculated by integrating the ring capacitance of the same deflection distance using the following equation:

C⁡(VBIAS)=∫0d⁢2⁢πε0⁢rtg-x⁡(r)⁢dr,
where d is the diameter of the membrane4233and tgis the effective height of the gap between the membrane4233and the substrate4235. It can be appreciated from the above equation that when there is contact between the membrane4233and the substrate, meaning that ∃r:tg=x(r), a discontinuity should be observed in the capacitance C vs. VBIAScurve.

FIG.43illustrates another schematic diagram of the CMUT4252(which may be the same as the CMUT152), in accordance with certain embodiments described herein.FIG.43further illustrates a DC-DC converter4339and ultrasound circuitry4341. The DC-DC converter4339may be, for example, a charge pump. The DC-DC converter4339may be disposed, for example, in an ultrasound device (e.g., the ultrasound device4402described below) but not in the substrate4235. The ultrasound circuitry4341is disposed in the substrate4235of the CMUT4252and is electrically coupled to the electrode4237. The ultrasound circuitry4341may be, for example, integrated circuitry that is integrated in a semiconductor chip. The ultrasound circuitry4341may include, for example, any of the ultrasound circuitry, illustrated inFIG.3-34or43(e.g., the ultrasound circuitry2727,2827,2927,3027,3127,3227,3327,3427, or4310). The DC-DC converter4339may apply a voltage to the membrane4233of the CMUT and the ultrasound circuitry4341may apply a voltage to the electrode4237. If the ultrasound circuitry4341establishes a virtual ground at the electrode4237, and the DC-DC converter4339applies a voltage VBIASto the membrane4233, then the voltage applied to the CMUT4252(i.e., between the membrane4233and the electrode4237of the CMUT152) may be VBIAS.

FIG.44illustrates a schematic block diagram of an example ultrasound system4400upon which various aspects of the technology described herein may be practiced. The ultrasound system4400includes an ultrasound device4402, a processing device4404, a network4406, and one or more servers4408. The processing device4404may be any of the processing devices described herein. The ultrasound device4402may be any of the ultrasound devices described herein.

The ultrasound device4402includes ultrasound circuitry4410. The processing device4404includes a camera4420, a display screen4412, a processor4414, a memory4416, an input device4418, and a speaker4422. The processing device4404is in wired (e.g., through a lightning connector or a mini-USB connector) and/or wireless communication (e.g., using BLUETOOTH, ZIGBEE, and/or WiFi wireless protocols) with the ultrasound device4402. The processing device4404is in wireless communication with the one or more servers4408over the network4406.

The ultrasound device4402may be configured to generate ultrasound data that may be employed to generate an ultrasound image. The ultrasound device4402may be constructed in any of a variety of ways. In some embodiments, the ultrasound device4402includes a transmitter that transmits a signal to a transmit beamformer which in turn drives transducer elements within a transducer array to emit pulsed ultrasonic signals into a structure, such as a patient. The pulsed ultrasonic signals may be back-scattered from structures in the body, such as blood cells or muscular tissue, to produce echoes that return to the transducer elements. These echoes may then be converted into electrical signals by the transducer elements and the electrical signals are received by a receiver. The electrical signals representing the received echoes are sent to a receive beamformer that outputs ultrasound data. The ultrasound circuitry4410may be configured to generate the ultrasound data. The ultrasound circuitry4410may include one or more ultrasonic transducers monolithically integrated onto a single semiconductor die. The ultrasonic transducers may include, for example, one or more capacitive micromachined ultrasonic transducers (CMUTs), one or more CMOS (complementary metal-oxide-semiconductor) ultrasonic transducers (CUTs), one or more piezoelectric micromachined ultrasonic transducers (PMUTs), and/or one or more other suitable ultrasonic transducer cells. In some embodiments, the ultrasonic transducers may be formed on the same chip as other electronic components in the ultrasound circuitry4410(e.g., transmit circuitry, receive circuitry, control circuitry, power management circuitry, and processing circuitry) to form a monolithic ultrasound device. The ultrasound circuitry4410may include any of the ultrasound circuitry illustrated inFIGS.3-34(e.g., the ultrasound circuitry2727,2827,2927,3027,3127,3227,3327,3427, or4341) as well as the DC-DC converter4337. The ultrasound device4402may transmit ultrasound data and/or ultrasound images to the processing device4404over a wired (e.g., through a lightning connector or a mini-USB connector) and/or wireless (e.g., using BLUETOOTH, ZIGBEE, and/or WiFi wireless protocols) communication link. The ultrasound circuitry4410may be configured to perform certain of the processes described herein (e.g., the processes3600,3700,3800, and/or3900).

Referring now to the processing device4404, the processor4414may include specially-programmed and/or special-purpose hardware such as an application-specific integrated circuit (ASIC). For example, the processor4414may include one or more graphics processing units (GPUs) and/or one or more tensor processing units (TPUs). TPUs may be ASICs specifically designed for machine learning (e.g., deep learning). The TPUs may be employed to, for example, accelerate the inference phase of a neural network. The processing device4404may be configured to process the ultrasound data received from the ultrasound device4402to generate ultrasound images for display on the display screen4412. The processing may be performed by, for example, the processor4414. The processor4414may also be adapted to control the acquisition of ultrasound data with the ultrasound device4402. The ultrasound data may be processed in real-time during a scanning session as the echo signals are received. In some embodiments, the displayed ultrasound image may be updated a rate of at least 5 Hz, at least 10 Hz, at least 20 Hz, at a rate between 5 and 60 Hz, at a rate of more than 20 Hz. For example, ultrasound data may be acquired even as images are being generated based on previously acquired data and while a live ultrasound image is being displayed. As additional ultrasound data is acquired, additional frames or images generated from more-recently acquired ultrasound data are sequentially displayed. Additionally, or alternatively, the ultrasound data may be stored temporarily in a buffer during a scanning session and processed in less than real-time.

The processing device4404may be configured to perform certain of the processes (e.g., the processes4000-4100) described herein using the processor4414(e.g., one or more computer hardware processors) and one or more articles of manufacture that include non-transitory computer-readable storage media such as the memory4416. The processor4414may control writing data to and reading data from the memory4416in any suitable manner. To perform certain of the processes described herein, the processor4414may execute one or more processor-executable instructions stored in one or more non-transitory computer-readable storage media (e.g., the memory4416), which may serve as non-transitory computer-readable storage media storing processor-executable instructions for execution by the processor4414. The camera4420may be configured to detect light (e.g., visible light) to form an image. The camera4420may be on the same face of the processing device4404as the display screen4412. The display screen4412may be configured to display images and/or videos, and may be, for example, a liquid crystal display (LCD), a plasma display, and/or an organic light emitting diode (OLED) display on the processing device4404. The input device4418may include one or more devices capable of receiving input from a user and transmitting the input to the processor4414. For example, the input device4418may include a keyboard, a mouse, a microphone, touch-enabled sensors on the display screen4412, and/or a microphone. The display screen4412, the input device4418, the camera4420, and the speaker4422may be communicatively coupled to the processor4414and/or under the control of the processor4414.

It should be appreciated that the processing device4404may be implemented in any of a variety of ways. For example, the processing device4404may be implemented as a handheld device such as a mobile smartphone or a tablet. Thereby, a user of the ultrasound device4402may be able to operate the ultrasound device4402with one hand and hold the processing device4404with another hand. In other examples, the processing device4404may be implemented as a portable device that is not a handheld device, such as a laptop. In yet other examples, the processing device4404may be implemented as a stationary device such as a desktop computer. The processing device4404may be connected to the network4406over a wired connection (e.g., via an Ethernet cable) and/or a wireless connection (e.g., over a WiFi network). The processing device4404may thereby communicate with (e.g., transmit data to or receive data from) the one or more servers4408over the network4406. For example, a party may provide from the server4408to the processing device4404processor-executable instructions for storing in one or more non-transitory computer-readable storage media (e.g., the memory4426) which, when executed, may cause the processing device4404to perform certain of the processes (e.g., the processes4000-4100) described herein. For further description of ultrasound devices and systems, see U.S. patent application Ser. No. 15/415,434 titled “UNIVERSAL ULTRASOUND DEVICE AND RELATED APPARATUS AND METHODS,” filed on Jan. 25, 2017 and published as U.S. Pat. App. Publication No. 2017-0360397 A1 (and assigned to the assignee of the instant application).

FIG.44should be understood to be non-limiting. For example, the ultrasound system4400may include fewer or more components than shown and the processing device4404and ultrasound device4402may include fewer or more components than shown. In some embodiments, the processing device4404may be part of the ultrasound device4402.

FIG.45illustrates an example handheld ultrasound probe4500, in accordance with certain embodiments described herein. The handheld ultrasound probe4500may be the same as the ultrasound device4402and may contain all of the ultrasound circuitry illustrated inFIG.3-34or44(e.g., the ultrasound circuitry2727,2827,2927,3027,3127,3227,3327,3427,4341or4410).

FIG.46illustrates an example wearable ultrasound patch4600, in accordance with certain embodiments described herein. The wearable ultrasound patch4600is coupled to a subject4602. The wearable ultrasound patch4600may be the same as the ultrasound device4402and may contain all of the ultrasound circuitry illustrated inFIG.3-34or44(e.g., the ultrasound circuitry2727,2827,2927,3027,3127,3227,3327,3427,4341or4410).

FIG.47illustrates an example ingestible ultrasound pill4700, in accordance with certain embodiments described herein. The ingestible ultrasound pill4700may be the same as the ultrasound device4402and may contain all of the ultrasound circuitry illustrated inFIG.3-34or44(e.g., the ultrasound circuitry2727,2827,2927,3027,3127,3227,3327,3427,4341, or4410).

Further description of the handheld ultrasound probe4500, the wearable ultrasound patch4600, and the ingestible ultrasound pill4700may be found in U.S. patent application Ser. No. 15/626,711 titled “UNIVERSAL ULTRASOUND IMAGING DEVICE AND RELATED APPARATUS AND METHODS,” filed on Jun. 19, 2017 and published as U.S. Pat. App. Publication No. 2017-0360399 A1 (and assigned to the assignee of the instant application), which is incorporated by reference herein in its entirety.

The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified.

As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified.

Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

As used herein, reference to a numerical value being between two endpoints should be understood to encompass the situation in which the numerical value can assume either of the endpoints. For example, stating that a characteristic has a value between A and B, or between approximately A and B, should be understood to mean that the indicated range is inclusive of the endpoints A and B unless otherwise noted.

The terms “approximately” and “about” may be used to mean within ±20% of a target value in some embodiments, within ±10% of a target value in some embodiments, within ±5% of a target value in some embodiments, and yet within ±2% of a target value in some embodiments. The terms “approximately” and “about” may include the target value.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

Having described above several aspects of at least one embodiment, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be object of this disclosure. Accordingly, the foregoing description and drawings are by way of example only.

It will be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the above description should not be construed as limiting, but merely as exemplifications of various embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the claims appended thereto.