Patent ID: 12219750

DETAILED DESCRIPTION

The memory device described herein includes volatile memory cells in which each of the memory cells can include two transistors (2T). One of the two transistors has a charge storage structure, which can form a memory element of the memory cell to store information. The memory device described herein can have a structure (e.g., a 4F2 cell footprint) that allows the size of the memory device to be relatively smaller than the size of similar conventional memory devices. Further, as mentioned above, some conventional memory devices have multiple access transistors associated with each memory cell and use the same access line (e.g., same word line) to control access to the memory cell in a read or write operation. In such conventional memory devices, the access transistor (e.g., a write access transistor) for a write operation may be required to have a relatively higher threshold voltage to prevent read disturb of the memory cell during a read operation. However, structuring such a write access transistor to have a relatively higher threshold voltage may require careful structure design and material selection for the memory cell in a conventional memory device.

The memory device described herein includes separate access lines (e.g., separate word lines) to separately (e.g., independently) control respective transistors of each memory cell during a read operation or a write operation of the memory device. In comparison with some conventional techniques, using separate access lines as described herein can lessen the requirements associated with having a relatively higher threshold voltage for a write transistor in a memory cell.

Further, the arrangement of the access lines described herein can provide built-in shield structures that can protect or prevent adjacent transistors from disturbance (e.g., in adjacent channel regions of adjacent memory cells) during read and write operation of adjacent memory cells. Moreover, the arrangement of the access lines described herein can provide an opportunity to enlarge the size of a storage charge storage structure of the memory cell for improving (e.g., increasing) storage capacitance of the memory cell. Other improvements and benefits of the described memory device and its variations are discussed below with reference toFIG.1throughFIG.8C.

FIG.1shows a block diagram of an apparatus in the form of a memory device100including volatile memory cells, according to some embodiments described herein. Memory device100includes a memory array101, which can contain memory cells102. Memory device100can include a volatile memory device such that memory cells102can be volatile memory cells. An example of memory device100includes a dynamic random-access memory (DRAM) device. Information stored in memory cells102of memory device100may be lost (e.g., invalid) if supply power (e.g., supply voltage Vcc) is disconnected from memory device100. Hereinafter, supply voltage Vcc is referred to as representing some voltage levels; however, they are not limited to a supply voltage (e.g., Vcc) of the memory device (e.g., memory device100). For example, if the memory device (e.g., memory device100) has an internal voltage generator (not shown inFIG.1) that generates an internal voltage based on supply voltage Vcc, such an internal voltage may be used instead of supply voltage Vcc.

In a physical structure of memory device100, each of memory cells102can include transistors (e.g., two transistors) formed vertically (e.g., stacked on different layers) in different levels over a substrate (e.g., semiconductor substrate) of memory device100. Memory device100can also include multiple levels (e.g., multiple decks) of memory cells where one level (e.g., one deck) of memory cells can be formed over (e.g., stacked on) another level (e.g., another deck) of additional memory cells. The structure of memory array101, including memory cells102, can include the structure of memory arrays and memory cells described below with reference toFIG.2throughFIG.8B.

As shown inFIG.1, memory device100can include access lines104(e.g., “word lines”) and data lines (e.g., bit lines)105. Memory device100can use signals (e.g., word line signals) on access lines104to access memory cells102and data lines105to provide information (e.g., data) to be stored in (e.g., written) or read (e.g., sensed) from memory cells102.

Memory device100can include an address register106to receive address information ADDR (e.g., row address signals and column address signals) on lines (e.g., address lines)107. Memory device100can include row access circuitry (e.g., X-decoder)108and column access circuitry (e.g., Y-decoder)109that can operate to decode address information ADDR from address register106. Based on decoded address information, memory device100can determine which memory cells102are to be accessed during a memory operation. Memory device100can perform a write operation to store information in memory cells102, and a read operation to read (e.g., sense) information (e.g., previously stored information) in memory cells102. Memory device100can also perform an operation (e.g., a refresh operation) to refresh (e.g., to keep valid) the value of information stored in memory cells102. Each of memory cells102can be configured to store information that can represent at most one bit (e.g., a single bit having a binary 0 (“0”) or a binary 1 (“1”)), or more than one bit (e.g., multiple bits having a combination of at least two binary bits).

Memory device100can receive a supply voltage, including supply voltages Vcc and Vss, on lines130and132, respectively. Supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). Supply voltage Vcc can include an external voltage supplied to memory device100from an external power source such as a battery or an alternating current to direct current (AC-DC) converter circuitry.

As shown inFIG.1, memory device100can include a memory control unit118, which includes circuitry (e.g., hardware components) to control memory operations (e.g., read and write operations) of memory device100based on control signals on lines (e.g., control lines)120. Examples of signals on lines120include a row access strobe signal RAS*, a column access strobe signal CAS*, a write-enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock-enable signal CKE. These signals can be part of signals provided to a DRAM device.

As shown inFIG.1, memory device100can include lines (e.g., global data lines)112that can carry signals DQ0through DQN. In a read operation, the value (e.g., “0” or “1”) of information (read from memory cells102) provided to lines112(in the form of signals DQ0through DQN) can be based on the values of the signals on data lines105. In a write operation, the value (e.g., “0” or “1”) of information provided to data lines105(to be stored in memory cells102) can be based on the values of signals DQ0through DQN on lines112.

Memory device100can include sensing circuitry103, select circuitry115, and input/output (I/O) circuitry116. Column access circuitry109can selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Select circuitry115can respond to the signals on lines114to select signals on data lines105. The signals on data lines105can represent the values of information to be stored in memory cells102(e.g., during a write operation) or the values of information read (e.g., sensed) from memory cells102(e.g., during a read operation).

I/O circuitry116can operate to provide information read from memory cells102to lines112(e.g., during a read operation) and to provide information from lines112(e.g., provided by an external device) to data lines105to be stored in memory cells102(e.g., during a write operation). Lines112can include nodes within memory device100or pins (or solder balls) on a package where memory device100can reside. Other devices external to memory device100(e.g., a hardware memory controller or a hardware processor) can communicate with memory device100through lines107,112, and120.

Memory device100may include other components, which are not shown inFIG.1so as not to obscure the example embodiments described herein. At least a portion of memory device100(e.g., a portion of memory array101) can include structures and operations similar to or the same as any of the memory devices described below with reference toFIG.2throughFIG.12C.

FIG.2shows a schematic diagram of a portion of a memory device200including a memory array201, according to some embodiments described herein. Memory device200can correspond to memory device100ofFIG.1. For example, memory array201can form part of memory array101ofFIG.1. As shown inFIG.2, memory device200can include memory cells210through215, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or the same elements among memory cells210through215are given the same labels.

Each of memory cells210through215can include two transistors T1and T2. Thus, each of memory cells210through215can be called a 2T memory cell (e.g., 2T gain cell). Each of transistors T1and T2can include a field-effect transistor (FET). As an example, transistor T1can be a p-channel FET (PFET), and transistor T2can be an n-channel FET (NFET). Part of transistor T1can include a structure of a p-channel metal-oxide semiconductor (PMOS) transistor FET (PFET). Thus, transistor T1can include an operation similar to that of a PMOS transistor. Part of transistor T2can include an n-channel metal-oxide semiconductor (NMOS). Thus, transistor T2can include an operation similar to that of a NMOS transistor.

As shown inFIG.2, transistor T1can have a gate251. Transistor T2can have a gate252. Gates251and252are electrically separated from each other. Transistor T1of memory device200can include a charge-storage based structure (e.g., a floating-gate based). As shown inFIG.2, each of memory cells210through215can include a charge storage structure202, which can include the floating gate of transistor T1. Charge storage structure202can form the memory element of a respective memory cell among memory cells210through215. Charge storage structure202can store charge. The value (e.g., “0” or “1”) of information stored in a particular memory cell among memory cells210through215can be based on the amount of charge in charge storage structure202of that particular memory cell. Each of memory cells210through215can be configured to store at most one bit (e.g., a single-level cell) or multiple bits (e.g., multiple-level cell). For example, the value of information stored in each of memory cells210through215can be “0” or “1” if each memory cell is configured as a single-bit memory cell or “00”, “01”, “10”, or “11” (or other multi-bit values) if each memory cell is configured as a multi-bit memory cell.

As shown inFIG.2, transistor T2(e.g., the channel region of transistor T2) of a particular memory cell among memory cells210through215can be electrically coupled to (e.g., directly coupled to) charge storage structure202of that particular memory cell. Thus, a circuit path (e.g., current path) can be formed directly between transistor T2of a particular memory cell and charge storage structure202of that particular memory cell during an operation (e.g., a write operation) of memory device200. During a write operation of memory device200, a circuit path (e.g., current path) can be formed between a respective data line (e.g., data line271or272) and charge storage structure202of a particular memory cell through transistor T2(e.g., through the channel region of transistor T2) of the particular memory cell.

Memory cells210through215can be arranged in memory cell groups2010and2011.FIG.2shows two memory cell groups (e.g.,2010and2011) as an example. However, memory device200can include more than two memory cell groups. Memory cell groups2010and2011can include the same number of memory cells. For example, memory cell group2010can include memory cells210,212, and214, and memory cell group2011can include memory cells211,213, and215.FIG.2shows three memory cells in each of memory cell groups2010and2011as an example. The number of memory cells in memory cell groups2010and2011can be different from three.

Memory device200can perform a write operation to store information in memory cells210through215, and a read operation to read (e.g., sense) information from memory cells210through215. Memory device200can be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a container for a capacitor, memory device200can store information in the form of charge in charge storage structure202(which can be a floating gate structure). As mentioned above, charge storage structure202can be the floating gate of transistor T1. During an operation (e.g., a read or write operation) of memory device200, two separate access lines (e.g., read access line and write access line) and a data line (e.g., a single data line) can be used to access a selected memory cell (e.g., target memory cell).

As shown inFIG.2, memory device200can include access lines (e.g., word lines)241R,241W,242R,242W,243R, and243W that can carry respective signals (e.g., word line signals) WL1W, WL1R, WL2W, WL2R, WL3W, and WL3R. Access lines241R,241W,242R,242W,243R, and243W are electrically separated from each other. Each memory cell can be associated with two access lines (e.g., read access line and write access line).

The access line (e.g., access line241R,242R, or243R) having label that includes letter “R” can be called a read access line. Access lines241R,242R, and243R can used to selectively turn on a respective transistor T1(e.g., read transistor) of a selected memory cell (or selected memory cells) during a read operation to read information from the selected memory cell (or selected memory cells).

The access line (e.g., access line241W,242W, or243W) having a label that includes letter “W” can be called a write access line. Access lines241W,242W, and243W can used to selectively turn on a respective transistor T2(e.g., write transistor) of a selected memory cell (or selected memory cells) during a write operation to store information in the selected memory cell (or selected memory cells).

Access lines241R,241W,242R,242W,243R, and243W can be used to access both memory cell groups2010and2011. Each of access lines241R,241W,242R,242W,243R, and243W can be structured as a conductive line, which can be driven (e.g., activated) by a separate driver (described below).

Memory device200can include drivers231W,231R,232W,232R,233W, and233R coupled to access lines241W,241R,242W,242R,243W, and243R, respectively. Drivers231R,232R, and233R can be called read drivers and can be used to selectively drive (e.g., activate) access lines241R,242R, and243R, respectively, during a read operation. Drivers231W,232W, and233W can be called write drivers and can be used to selectively drive (e.g., activate) access lines241W,242W, and243W, respectively, during a write operation.

Drivers231W,231R,232W,232R,233W, and233R can be complementary metal oxide semiconductor (CMOS) drivers or other types of drivers that can operate to provide (e.g., drive) signals WL1W, WL1R, WL2W, WL2R, WL3W, and WL3R associated with access lines241W,241R,242W,242R,243W, and243R, respectively. Signals WL1W, WL1R, WL2W, WL2R, WL3W, and WL3R can be provided with different voltages depending on which operation (e.g., read or write operation) memory device200performs.

Drivers231W,231R,232W,232R,233W, and233R can be configured to drive access lines241W,241R,242W,242R,243W, and243R one at a time during an operation (e.g., read or write operation) of memory device200to access a selected memory cell (or selected memory cells) among memory cells210through215. A selected cell can be referred to as a target cell. In a read operation, information can be read from a selected memory cell (or selected memory cells). In a write operation, information can be stored in a selected memory cell (or selected memory cells).

Each of gates251and252of respective transistors T1and T2can be electrically coupled to a respective access line. In the structure of memory device200(seeFIG.5AthroughFIG.6B), each of gates251and252can be formed from a portion (e.g., portion of the material) of a respective access line among access lines241R,241W,242R,242W,243R, and243W. As described above, access lines (e.g., access lines241R and241W) associated with a memory cell (e.g., memory cell210) are electrically separated from each other. Thus, gate251of transistor T1and gate252of transistor T2of a memory cell (e.g., memory cell210) are also electrically separated from each other.

In memory device200ofFIG.2, gates251of different transistors T1of memory cells associated with the same access line (e.g., a read access line) can be formed from different portions of the conductive material that forms that access line. Gates252of different transistors T2of memory cells associated with the same access line (e.g., a write access line) can be formed from different portions of the conductive material that forms that access line

For example, as shown inFIG.2gates251of respective transistors T1of memory cells210and211can be formed from two respective portions of a conductive material (or materials) that forms access line241R. Gates252of respective transistors T2of memory cells210and211can be formed from two respective portions of a conductive material (or materials) that forms access line241W.

Gates251of respective transistors T1of memory cells212and213can be formed from two respective portions of a conductive material (or materials) that forms access line242R. Gates252of respective transistors T2of memory cells212and213can be formed from two respective portions of a conductive material (or materials) that forms access line242W.

Gates251of respective transistors T1of memory cells214and215can be formed from two respective portions of a conductive material (or materials) that forms access line243R. Gates252of respective transistors T2of memory cells214and215can be formed from two respective portions of a conductive material (or materials) that forms access line243W.

Memory device200can include data lines (e.g., bit lines)271and272that can carry respective signals (e.g., bit line signals) BL1and BL2. During a read operation, memory device200can use data line271to obtain information read (e.g., sensed) from a selected memory cell of memory cell group2010, and data line272to read information from a selected memory cell of memory cell group2011. During a write operation, memory device200can use data line271to provide information to be stored in a selected memory cell of memory cell group2010, and data line272to provide information to be stored in a selected memory cell of memory cell group2011.

Memory device200can include a conductive connection297coupled to (e.g., coupled to a terminal of transistor T1) each of memory cells210through215. Conductive connection297can include (or can be part of) a conductive region. As an example, conductive connection297can include a ground connection or can be part of a ground connection. For example, conductive connection297can be structured from a conductive plate (e.g., a layer of conductive material). The conductive plate can be coupled to a ground terminal of memory device200or alternatively coupled to non-ground structure of memory device200.

In the structure of memory device200(FIG.5AthroughFIG.6B), conductive connection297can be part of a common conductive structure (e.g., a common conductive plate) or separate conductive structures that can be formed on a level of memory device200that is under the memory cells (e.g., memory cells210through215) of memory device200. In this example, the elements (e.g., part of transistors T1and T2or the entire transistors T1and T2) of each of the memory cells (e.g., memory cells210through215) of memory device200can be formed (e.g., formed vertically) over the common conductive structure (e.g., a common conductive plate) and electrically coupled to the common conductive structure.

As shown inFIG.2, transistor T1(e.g., the channel region of transistor T1) of a particular memory cell among memory cells210through215can be electrically coupled to (e.g., directly coupled to) conductive connection297and electrically coupled to (e.g., directly coupled to) a respective data line (e.g., data line271or272). Thus, a circuit path (e.g., current path) can be formed between a respective data line (e.g., data line271or272) and conductive connection297through transistor T1(e.g., through a channel region of transistor T1) of a selected memory cell during an operation (e.g., a read operation) performed on the selected memory cell.

Memory device200can include read paths (e.g., circuit paths). Information read from a selected memory cell during a read operation can be obtained through a read path coupled to the selected memory cell. In memory cell group2010, a read path of a particular memory cell (e.g., memory cell210,212, or214) can include a current path (e.g., read current path) through a channel region of transistor T1of that particular memory cell, data line271, and conductive connection297. In memory cell group2011, a read path of a particular memory cell (e.g., memory cell211,213, or215) can include a current path (e.g., read current path) through a channel region of transistor T1of that particular memory cell, data line272, and conductive connection297. In the example where transistor T1is a PFET (e.g., a PMOS), the current in the read path (e.g., during a read operation) can include a hole conduction (e.g., hole conduction in the direction from data line271to conductive connection297through the channel region of transistor T1). Since transistor T1can be used in a read path to read information from the respective memory cell during a read operation, transistor T1can be called a read transistor (or read access transistor) and the channel region of transistor T1can be called a read channel region.

Memory device200can include write paths (e.g., circuit paths). Information to be stored in a selected memory cell during a write operation can be provided to the selected memory cell through a write path coupled to the selected memory cell. In memory cell group2010, a write path of a particular memory cell can include transistor T2(e.g., can include a write current path through a channel region of transistor T2) of that particular memory cell and data line271. In memory cell group2011, a write path of a particular memory cell (e.g., memory cell211,213, or215) can include transistor T2(e.g., can include a write current path through a channel region of transistor T2) of that particular memory cell and data line272. In the example where transistor T2is an NFET (e.g., NMOS), the current in a write path (e.g., during a write operation) can include an electron conduction (e.g., electron conduction in the direction from data line271to charge storage structure202) through the channel region of transistor T2. Since transistor T2can be used in a write path to store information in a respective memory cell during a write operation, transistor T2can be called a write transistor (or write access transistor) and the channel region of transistor T2can be called a write channel region.

Each of transistors T1and T2can have a threshold voltage (Vt). Transistor T1has a threshold voltage Vt1. Transistor T2has a threshold voltage Vt2. The values of threshold voltages Vt1and Vt2can be different (unequal values). For example, the value of threshold voltage Vt2can be greater than the value of threshold voltage Vt1.

As described above, transistors T1and T2of the same memory cell have respective gates251and252that are electrically separated from each other. Thus, transistors T1and T2of the same memory cell can be separately (e.g., individually) controlled. For example, in a memory cell, transistors T1and T2can be separately turned on or turned off during an operation (e.g., read or write operation). Separate drivers (among drivers231R,231W,232R,232W,233R, and233W) can be configured to separately turn on or turn off transistor T1and T2. For example, during a read operation to read (e.g., sense) information stored in charge storage structure202of memory cell210, transistor T1of memory cell210can be turned on and transistor T2of memory cell210can be turned off. Turning off transistor T2can prevent leaking of charge (e.g., during a read operation) from charge storage structure202through transistor T2of the write path during the read operation.

During a read operation of memory device200, only one memory cell of the same memory cell group can be selected one at a time to read information from the selected memory cell. For example, memory cells210,212, and214of memory cell group2010can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells210,212, and214in this example). In another example, memory cells211,213, and215of memory cell group2011can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells211,213, and215in this example).

During a read operation, memory cells of different memory cell groups (e.g., memory cell groups2010and2011) that share the same access line (e.g., access lines241W and241R,242W and242R, or243W and243R) can be concurrently selected (or alternatively can be sequentially selected). For example, memory cells210and211can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells210and211. Memory cells212and213can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells212and213. Memory cells214and215can be concurrently selected during a read operation to read (e.g., concurrently read) information from memory cells214and215.

The value of information read from the selected memory cell of memory cell group2010during a read operation can be determined based on the value of a current detected (e.g., sensed) from a read path (described above) that includes data line271, transistor T1of the selected memory cell (e.g., memory cell210,212, or214), and conductive connection297. The value of information read from the selected memory cell of memory cell group2011during a read operation can be determined based on the value of a current detected (e.g., sensed) from a read path that includes data line272, transistor T1of the selected memory cell (e.g., memory cell211,213, or215), and conductive connection297.

Memory device200can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) a current (e.g., current11, not shown) on a read path that includes data line271, and detect a current (e.g., current12, not shown) on a read path that includes data line272. The value of the detected current can be based on the value of information stored in the selected memory cell. For example, depending on the value of information stored in the selected memory cell of memory cell group2010, the value of the detected current (e.g., the value of current11) on data line271can be zero or greater than zero. Similarly, depending on the value of information stored in the selected memory cell of memory cell group2011, the value of the detected current (e.g., the value of current12) on data line272can be zero or greater than zero. Memory device200can include circuitry (not shown) to translate the value of a detected current into the value (e.g., “0”, “1”, or a combination of multi-bit values) of information stored in the selected memory cell.

During a write operation of memory device200, only one memory cell of the same memory cell group can be selected at a time to store information in the selected memory cell. For example, memory cells210,212, and214of memory cell group2010can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cell210,212, and214in this example). In another example, memory cells211,213, and215of memory cell group2011can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of memory cell211,213, and215in this example).

During a write operation, memory cells of different memory cell groups (e.g., memory cell groups2010and2011) that share the same access line (e.g., access lines241W and241R,242W and242R, or243W and243R) can be concurrently selected. For example, memory cells210and211can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells210and211. Memory cells212and213can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells212and213. Memory cells214and215can be concurrently selected during a write operation to store (e.g., concurrently store) information in memory cells214and215.

Information to be stored in a selected memory cell of memory cell group2010during a write operation can be provided through a write path (described above) that includes data line271and transistor T2of the selected memory cell (e.g., memory cell210,212, or214). Information to be stored in a selected memory cell of memory cell group2011during a write operation can be provided through a write path (described above) that includes data line272and transistor T2of the selected memory cell (e.g., memory cell211,213, or215). As described above, the value (e.g., binary value) of information stored in a particular memory cell among memory cells210through215can be based on the amount of charge in charge storage structure202of that particular memory cell.

In a write operation, the amount of charge in charge storage structure202of a selected memory cell can be changed (to reflect the value of information stored in the selected memory cell) by applying a voltage on a write path that includes transistor T2of that particular memory cell and the data line (e.g., data line271or272) coupled to that particular memory cell. For example, a voltage having one value (e.g., 0V) can be applied on data line271(e.g., provide 0V to signal BL1) if information to be stored in a selected memory cell among memory cells210,212, and214has one value (e.g., “0”). In another example, a voltage having another value (e.g., a positive voltage) can be applied on data line271(e.g., provide a positive voltage to signal BL1) if information to be stored in a selected memory cell among memory cells210,212, and214has another value (e.g., “1”). Thus, information can be stored (e.g., directly stored) in charge storage structure202of a particular memory cell by providing the information to be stored (e.g., in the form of a voltage) on a write path (that includes transistor T2) of that particular memory cell.

Drivers231W,231R,232W,232R,233W, and233R can be configured to apply voltages (in the form of respective signals WL1W, WL1R, WL2W, WL2R, WL3W, and WL3R) to respective access lines241R,241W,242R,242W,243R, and243W in a read operation and a write operation to control (e.g., turn on or turn off) respective transistors T1and T2. The voltages (in the form of signals BL1and BL2) applied to data lines271and272during a read operation and a write operation can be provided by another component (not shown) of memory device200.

FIG.3shows memory device200ofFIG.2including example voltages V1, V2, V3, and V4used during a read operation of memory device200, according to some embodiments described herein. The example ofFIG.3assumes that memory cells210and211are selected memory cells (e.g., target memory cells) during a read operation to read (e.g., to sense) information stored (e.g., previously stored) in memory cells210and211. Memory cells212through215are assumed to be unselected memory cells. This means that memory cells212through215are not accessed, and information stored in memory cells212through215is not read while information is read from memory cells210and211in the example ofFIG.3.

InFIG.3, voltages V1, V2, and V3represent different voltages applied by respective drivers (among drivers231W,231R,232W,232R,233W, and233R) to respective access lines241W,241R,242W,242R,243W, and243R during a read operation of memory device200. Voltage V4represents the voltage applied to each of data lines271and272during the read operation. In the read operation, conductive connection297can be provided with 0V (e.g., coupled to ground).

In the read operation shown inFIG.3, voltage V1can have a value (e.g., −1V) to turn on transistor T1of each of memory cells210and211(selected memory cells in this example). The specific values of voltages used in this description (e.g., used in a read or write operation) are only example values. Different values may be used. For example, voltage V1can have a negative value range (e.g., the value of voltage V1can be from −3V to −1V).

In the read operation associated withFIG.3, voltage V2can have a value (e.g., 0V) to turn off (or keep off) transistor T2of each of memory cells210through215. This allows information to be read from memory cells210and211. Voltage V3can have a value (e.g., 2V), such that transistors T1each of memory cells212through215(unselected memory cells in this example) are turned off (e.g., kept off). Voltage V4can have a value (e.g., 0.5V), such that a current (e.g., read current) may be formed on a read path that includes data line271, transistor T1of memory cell210, and conductive connection297, and a current can be formed on a read path (a separate read path) that includes data line272, transistor T1of memory cell211, and conductive connection297. This allows a detection of current on the read paths coupled to memory cells210and211, respectively. A detection circuitry (not shown) of memory device200can operate to translate the value of the detected current (during reading of information from the selected memory cells) into the value (e.g., “0”, “1”, or a combination of multi-bit values) of information read from the selected memory cell. In the example ofFIG.3, the value of the detected currents on data lines271and272can be translated into the values of information read from memory cells210and211, respectively.

In the read operation shown inFIG.3, the voltages (e.g., V2and V3) applied to respective access lines241W,242R,242W,243R, and243W can cause transistors T1and T2of each of memory cells210through215, except transistor T1of each of memory cells210and211(selected memory cells), to turn off (or to remain turned off). Transistor T1of memory cell210(selected memory cell) may or may not turn on, depending on the value of the threshold voltage Vt1of transistor T1of memory cell210. Transistor T1of memory cell211(selected memory cell) may or may not turn on, depending on the value of the threshold voltage Vt1of transistor T1of memory cell211. For example, if transistor T1of each of memory cells (e.g.,210through215) of memory device200is configured (e.g., structured) such that the threshold voltage of transistor T1is less than zero (e.g., Vt1<−1V) regardless of the value (e.g., the state) of information stored in a respective memory cell210, then transistor T1of memory cell210, in this example, can turn on and conduct a current on data line271(through transistor T1of memory cell210). In this example, transistor T1of memory cell211can also turn on and conduct a current on data line272(through transistor T1of memory cell211). Memory device200can determine the value of information stored in memory cells210and211based on the value of the currents on data lines271and272, respectively. As described above, memory device200can include detection circuitry to measure the value of currents on data lines271and272during a read operation.

FIG.4shows memory device200ofFIG.2including example voltages V5, V6, V7, V8, and V9used during a write operation of memory device200, according to some embodiments described herein. The example ofFIG.4assumes that memory cells210and211are selected memory cells (e.g., target memory cells) during a write operation to store information in memory cells210and211. Memory cells212through215are assumed to be unselected memory cells. This means that memory cells212through215are not accessed and information is not to be stored in memory cells212through215while information is stored in memory cells210and211in the example ofFIG.4.

InFIG.4, voltages V5, V6, and V7represent different voltages applied by respective drivers (among drivers231W,231R,232W,232R,233W, and233R) to respective access lines241W,241R,242W,242R,243W, and243R during a write operation of memory device200. Voltages V8and V9represent the voltages applied to data lines271and272, respectively, during the write operation. In the write operation, conductive connection297can be provided with 0V (e.g., coupled to ground).

The values of voltages V8and V9can be the same or different depending on the value (e.g., “0” or “1”) of information to be stored in memory cells210and211. For example, the values of voltages V8and V9can be the same (e.g., V8=V9) if the memory cells210and211are to store information having the same value. As an example, V8=V9=0V if information to be stored in each of memory cells210and211is “0”, and V8=V9=1V to 3V if information to be stored in each of memory cells210and211is “1”.

In another example, the values of voltages V8and V9can be different (e.g., V8≠V9) if the memory cells210and211are to store information having different values. As an example, V8=0V and V9=1V to 3V if “0” is to be stored in memory cell210and “1” is to be stored in memory cell211. As another example, V8=1V to 3V and V9=0V if “1” is to be stored in memory cell210and “0” is to be stored in memory cell211.

The range of voltage of 1V to 3V is used here as an example. A different range of voltages can be used. Further, instead of applying 0V (e.g., V8=0V or V9=0V) to a particular write data line (e.g., data line271or272) for storing information having a value of “0” to the memory cell (e.g., memory cell210or211) coupled to that particular write data line, a positive voltage (e.g., V8>0V or V9>0V) may be applied to that particular data line.

In the write operation shown inFIG.4, the voltages (e.g., V6and V7) applied to respective access lines241R,242R,242W,243R, and243W can cause transistors T1and T2of each of memory cells210through215, except transistor T1of each of memory cells210and211(selected memory cells), to turn off (or to remain turned off). For example, in a write operation, voltage V6can have a value (e.g., 2V), such that transistor T1each of memory cells210through215are turned off (e.g., kept off). Voltage V7can have a value (e.g., 0V), such that transistor T2each of memory cells212through215are turned off (e.g., kept off).

Voltage V5can have a value (e.g., 3V) to turn on transistor T2of each of memory cells210and211(selected memory cells in this example) and form a write path between charge storage structure202of memory cell210and data line271, and a write path between charge storage structure202of memory cell211and data line272. A current (e.g., write current) may be formed between charge storage structure202of memory cell210(selected memory cell) and data line271. This current can affect (e.g., change) the amount of charge on charge storage structure202of memory cell210to reflect the value of information to be stored in memory cell210. A current (e.g., another write current) may be formed between charge storage structure202of memory cell211(selected memory cell) and data line272. This current can affect (e.g., change) the amount of charge on charge storage structure202of memory cell211to reflect the value of information to be stored in memory cell211.

In the example write operation ofFIG.4, the value of voltage V8may cause charge storage structure202of memory cell210to discharge or to be charged, such that the resulting charge (e.g., charge remaining after the discharge or charge action) on charge storage structure202of memory cell210can reflect the value of information stored in memory cell210. Similarly, the value of voltage V9in this example may cause charge storage structure202of memory cell211to discharge or to be charged, such that the resulting charge (e.g., charge remaining after the discharge or charge action) on charge storage structure202of memory cell211can reflect the value of information stored in memory cell211.

Thus, as described above in the example read and write operations, drivers231W,231R,232W,232R,233W, and233R can be configured to apply different voltages (in the form of respective signals WL1W, WL1R, WL2W, WL2R, WL3W, and WL3R) to respective access lines241W,241R,242W,242R,243W, and243R to selectively turn on or turn off transistors T1and T2of memory cells210through215in a read or write operation. For example, driver231R can be configured to turn on transistor T1of memory cell210during a read operation of reading information from memory cell210, and to turn off transistor T1of memory cell210during a write operation of storing information in memory cell210. Driver231W can be configured to turn off transistor T2of memory cell210during a read operation of reading information from memory cell210, and to turn on transistor T2of memory cell210during a write operation of storing information in memory cell210.

Other pairs of drivers (e.g., drivers232R and232W, and drivers233R and233W) of memory device200can be configured to turn on or turn off respective transistors T1and T2of memory cells212through215in ways similar to those of drivers231R and231W. For example, driver232R can be configured to turn on transistor T1of memory cell212during a read operation of reading information from memory cell212, and to turn off transistor T1of memory cell212during a write operation of storing information in memory cell212. Driver232W can be configured to turn off transistor T2of memory cell212during a read operation of reading information from memory cell212, and to turn on transistor T2of memory cell212during a write operation of storing information in memory cell212. In another example, driver233R can be configured to turn on transistor T1of memory cell214during a read operation of reading information from memory cell214, and to turn off transistor T1of memory cell214during a write operation of storing information in memory cell214. Driver233W can be configured to turn off transistor T2of memory cell214during a read operation of reading information from memory cell214, and to turn on transistor T2of memory cell214during a write operation of storing information in memory cell214.

FIG.5A,FIG.5B,FIG.5C,FIG.5Dshow different views of a structure of memory device200ofFIG.2with respect to the X, Y, and Z directions, according to some embodiments described herein. For simplicity, cross-sectional lines (e.g., hatch lines) are omitted from most of the elements shown inFIG.5AthroughFIG.5Dand other figures in the drawings described herein. Some elements of memory device200(and other memory devices described herein) may be omitted from a particular figure of the drawings so as to not obscure the description of the element (or elements) being described in that particular figure. The dimensions (e.g., physical structures) of the elements shown in the drawings described herein are not scaled.

FIG.5AandFIG.5Bshow different 3-dimensional views (e.g., isometric views) of memory device200including a single memory cell (memory cell210) with respect to the X, Y, and Z directions.FIG.5Cshows memory device200including multiple memory cells (memory cells210,211,212, and213).FIG.5Dshows memory device200ofFIG.5Cincluding separate conductive regions5970and5971.

The following description describes a portion of memory device200including detailed structure of memory cell210. The structures of other memory cells (e.g., memory cells211,212, and213inFIG.5Cand other memory cells schematically shown inFIG.2) of memory device200can be similar to or the same as the structure of memory cell210. InFIG.2andFIG.5AthroughFIG.5D, the same elements are given the same reference numbers. Some portions (e.g., gate oxide and dielectric isolation structures) of memory device200are omitted fromFIG.5AthroughFIG.5Dso as to not obscure the elements of memory device200in the embodiments described herein.

As shown inFIG.5AandFIG.5B, memory device200can include a substrate599over which memory cell210of memory device200can be formed. Transistors T1and T2of memory cell210can be formed vertically with respect to substrate599. Substrate599can be a semiconductor substrate (e.g., silicon-based substrate) or other type of substrate. As shown inFIG.5AandFIG.5B, the Z-direction (e.g., vertical direction) is a direction perpendicular to (e.g., outward from) substrate599. The Z-direction is also perpendicular to (e.g., extended vertically from) the X-direction and the Y-direction (perpendicular to the X-Y plane). The X-direction and Y-direction are perpendicular to each other.

As shown inFIG.5AandFIG.5B, conductive connection297can include a structure (e.g., a piece (e.g., a layer)) of conductive material (e.g., conductive region) located over (formed over) substrate599. Example materials for conductive connection297include metal, conductively doped polysilicon, or other conductive materials. Conductive connection297can be coupled to a ground terminal (not shown) of memory device200.FIG.5AandFIG.5Bshow conductive connection297contacting (e.g., directly coupled to) substrate599as an example. In an alternative structure, memory device200can include a dielectric (e.g., a layer of dielectric material, not shown) between conductive connection297and substrate599.

As shown inFIG.5AandFIG.5B, memory device200can include a semiconductor material596formed over conductive connection297. Semiconductor material596can include a structure (e.g., a piece (e.g., a layer)) of silicon, polysilicon, or other semiconductor material, and can include a doped region (e.g., p-type doped region), or other conductive materials.

Memory device200can include a conductive region597(e.g., a common conductive plate) under memory cell210and under other memory cells (e.g., memory cells211,212, and213inFIG.5C) of memory device200. Conductive region597can include at least one of the materials (e.g., doped polysilicon) of semiconductor material596and the material (e.g., metal or doped polysilicon) of conductive connection297. Thus, conductive region597can include the material of semiconductor material596, the material of conductive connection297, or a combination of the materials of semiconductor material596and conductive connection297.

As shown inFIG.5AandFIG.5B, data line271(associated with signals BL1) can have a length in the Y-direction, a width in the X-direction, and a thickness in the Z-direction. Data line271can include a conductive material (or a combination of materials) that can be structured as a conductive line (e.g., conductive region). Example materials for data line271include metal, conductively doped polysilicon, or other conductive materials. Other data lines (e.g., data lines272inFIG.2) of memory device200can have a similar structure as data line271.

As shown inFIG.5AandFIG.5B, access lines241R and241W can be opposite from each other with respect to the Y-direction. Each of access lines241R and241W can include a conductive material (or a combination of materials) that can be structured as a conductive line (e.g., conductive region). Each of access lines241R and241W can include a structure (e.g., a piece (e.g., a layer)) of conductive material (e.g., metal, conductively doped polysilicon, or other conductive materials). Each access line241R and241W can have a length extending in the X-direction, a width (e.g., a height) in the Z-direction, and a thickness in the Y-direction.

Access line241R and241W are electrically separated from each other. Thus, two different signals (e.g., signals WL1R and WL1W) having different voltages can be applied (e.g., concurrently applied) to access line241R and241W, respectively, in a same operation (e.g., a read or write operation) of memory device200.

Charge storage structure202of memory cell210(and other memory cells of memory device200) can include a charge storage material (or a combination of materials), which can include a piece (e.g., a layer) of semiconductor material (e.g., polysilicon), a piece (e.g., a layer) of metal, or a piece of material (or materials) that can trap charge. The materials of access line241R and241W and charge storage structure202can be the same or can be different. As shown inFIG.5AandFIG.5B, charge storage structure202can include a portion (e.g., bottom portion) that is closer (e.g., extends in the Z-direction closer) to substrate599than the bottom portion of each of access line241R and241W.

Memory device200can include a material520located between and electrically coupled to (e.g., directly contacting) data line271and charge storage structure202. As described above, charge storage structure202of memory cell210can form the memory element of memory cell210. Thus, as shown inFIG.5AandFIG.5B, memory cell210can include a memory element (which is charge storage structure202) located between substrate599and material520with respect to the Z-direction, in which the memory element contacts (e.g., is directly coupled to) material520.

Material520can form a source (e.g., source terminal) of transistor T2, a drain (e.g., drain terminal) of transistor T2, a channel region (e.g., write channel region) between the source and the drain of transistor T2of memory cell210. Thus, as shown inFIG.5AandFIG.5B, the source, channel region, and the drain of transistor T2of memory cell210can be formed from a single structure, for example, a single piece of the same material (or alternatively, a single piece of the same combination of materials), such as material520. Therefore, the source, the drain, and the channel region of transistor T2of memory cell210can be formed from the same material (e.g., material520) of the same conductivity type (e.g., either n-type or p-type). Other memory cells of memory device200can also include material520like memory cell210.

In the example where transistor T2is an NFET (as described above), material520can include n-type semiconductor material (e.g., n-type silicon). In another example, the semiconductor material that forms material520can include a structure (e.g., a piece) of oxide material. Examples of the oxide material used for material520include semiconducting oxide materials, transparent conductive oxide materials, and other oxide materials.

As an example, material520can include at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxide nitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOa), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

Using the materials listed above in memory device200provides improvement and benefits for memory device200. For example, during a read operation, to read information from a selected memory cell (e.g., memory cell210), charge from charge storage structure202of the selected memory cell may leak to transistor T2of the selected memory cell. Using the material listed above for the channel region (e.g., material520) of transistor T2can reduce or prevent such a leakage. This improves the accuracy of information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory device (e.g., memory device200) described herein.

The materials listed above are examples of material520. However, other materials (e.g., a relatively high band-gap material) different from the above-listed materials can be used.

As shown inFIG.5AandFIG.5B, material520and charge storage structure202of memory cell210can be electrically coupled (e.g., directly coupled) to each other, such that material520can contact charge storage structure202of memory cell210without an intermediate material (e.g., without a conductive material) between charge storage structure202of memory cell210and material520. In an alternative structure (not shown), material520can be electrically coupled to charge storage structure202of memory cell210, such that material520is not directly coupled to (not contacting) charge storage structure202of memory cell210, but material520is coupled to (e.g., indirectly contacting) charge storage structure202of memory cell210through an intermediate material (e.g., a conductive material) between charge storage structure202of memory cell210and material520.

As shown inFIG.5AandFIG.5B, memory cell210can include a portion510, which can include a structure (e.g., a piece (e.g., a layer)) of semiconductor material. Example materials for portion510can include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon-germanium, or other semiconductor materials, and semiconducting oxide materials (oxide semiconductors, e.g., SnO, or other oxide semiconductors).

As described above with reference toFIG.2, transistor T1of memory cell210includes a channel region (e.g., read channel region). InFIG.5AandFIG.5B, the channel region of transistor T1of memory cell210can include (e.g., can be formed from) portion510. Portion510can be electrically coupled to data line271and conductive region597. As described above with reference toFIG.2, memory cell210can include a read path. InFIG.5AandFIG.5B, portion510(e.g., the read channel region of transistor T1) can be part of the read path of memory cell210that can carry a current (e.g., read current) during a read operation of reading information from memory cell210. For example, during a read operation to read information from memory cell210, portion510can conduct a current (e.g., read current) between data line271and conductive connection297(through part of semiconductor material596). The direction of the read current can be from data line271to conductive region597(through portion510and part of semiconductor material596and part of conductive connection297). In the example where transistor T1is a PFET and transistor T2is an NFET, the material that forms portion510can have a different conductivity type from material520. For example, portion510can include p-type semiconductor material (e.g., p-type silicon) regions, and material520can include n-type semiconductor material (e.g., n-type gallium phosphide (GaP)) regions.

As shown inFIG.5AandFIG.5B, a portion of access line241R that directly faces (e.g., directly opposes) portion510can form gate251of transistor T1of memory cell210. A portion of access line241W that directly faces (e.g., directly opposes) adjacent material520can form gate252of transistor T2of memory cell210. Since access lines241R and241W are electrically separated from each other, gates251and252are also electrically separated from each other.

As shown inFIG.5AandFIG.5B, access line241R extends lengthwise in the X-direction and is adjacent (e.g., directly facing) portion510(e.g., read channel region of transistor T1). Access line241W is not adjacent (e.g., not directly facing) portion510. Access line241W extends lengthwise in the X-direction and is adjacent (e.g., directly facing) materials520(e.g., write channel region of transistor T2). Access line241W is not adjacent (e.g., not directly facing) materials510. Thus, in memory device200, each access line is adjacent (e.g., directly facing) either portion510(e.g., read channel region of transistor T1) of a memory cell or material520(e.g., write channel region of transistor T2) of a memory cell but not both portion510and material520of a memory cell.

As shown inFIG.5C, other memory cells (e.g., memory cells211,212, and213) and access lines (e.g., access lines242R and242W) of memory device200can have structures similar to (or the same as) the structure of memory cell210and access line241R and241W. The memory cells (e.g., memory cells210through214inFIG.5C) of memory device200can be formed over substrate599and can share conductive region597(which can include any combination of semiconductor material596and conductive connection297). Conductive region597can be a common conductive region for the memory cells of memory device200. Alternatively, conductive region597can be divided (e.g., patterned) into multiple portions (FIG.5D).

As shown inFIG.5D, memory device200can include conductive regions5970and5971that can collectively correspond to conductive region597ofFIG.5C. The memory cells coupled to the same data line in the Y-direction can share (can be electrically coupled to) the same conductive region (one of conductive regions5970and5971). For example, memory cells210and212(which are coupled to data line271) can share conductive region5970. Memory cells211and213(which are coupled to data line272) can share conductive region5971.

FIG.5Dshows an example of conductive region597ofFIG.5Cbeing divided (e.g., patterned) into conductive regions5970and5971that extend lengthwise in the Y-direction. However, in an alternative structure, conductive region597ofFIG.5Ccan be divided (e.g., patterned) into conductive regions that can extend lengthwise in the X-direction. In such an alternative structure, the memory cells (e.g., memory cells210and211, or212and214) sharing the same access line can share (can be electrically coupled to) the same conductive region.

FIG.6Ashows a top view (e.g., plan view) of a portion of memory device200, according to some embodiments described herein.FIG.6Bshows a view (e.g., cross-sectional view) taken along line6B-6B ofFIG.6A. InFIG.6A, it is noted that memory cells216,217,218,219,220, and221and data lines273and274(and associated signals BL3and BL4) are not shown inFIG.2andFIG.5AthroughFIG.5D. For simplicity, only some elements of memory device200are shown inFIG.6A.

FIG.6Ashows relative locations of portions510(e.g., read channel regions) of transistors T1(not labeled) and material520(e.g., write channel regions) of transistors T2(not labeled) of memory cells210through221, access lines241R,241W,242R,242W,243R, and243W, and data lines271,272,273, and274. Charge storage structures202(located under respective materials520) of memory cells210through221are located under respective materials520and are hidden under from the top view ofFIG.6A.

As shownFIG.6A, the memory cells (e.g., memory cells211through221) of memory device200can be arranged in a matrix (or matrix-like) pattern. Access lines241R,241W,242R,242W,243R, and243W can have lengths in the X-direction and are parallel to each other. Access lines241R,242R, and243R are adjacent (e.g., directly facing) respective portions510(e.g., read channel regions of transistors T1) of memory cells210through221. Access lines241W,242W, and243W are adjacent (e.g., directly facing) respective materials520(e.g., write channel regions of transistors T2) of memory cells210through221. For simplicity, dielectric structures618R and618W (inFIG.6B) between the access lines and respective portions510and materials520are not shown inFIG.6A. As shown inFIG.6A, access lines241R,241W,242R,242W,243R, and243W are perpendicular to data lines271,272,273, and274.

Data lines271,272,273, and274(shown in dashed lines), which are located over access lines241R,241W,242R,242W,243R, and243W and memory cells210through221, can have lengths in the Y-direction and are parallel to each other. As shown inFIG.6A, the direction from portion510(e.g., read channel region) to material520(e.g., write channel region) of a respective memory cell among memory cells210,212, and214coupled to a particular data line (e.g., data line271) is also the same as the direction (Y-direction) of the particular data line.

As shown inFIG.6B, each of memory cells210,212, and214can include dielectric structures615A and615B. Dielectric structures615A and615B can be oxide regions that separate charge storage structure202and material520(e.g., write channel region) from portion510(e.g., read channel region) of a respective memory cell. Dielectric structures615A and615B can also electrically separate charge storage structure202of a respective memory cell from conductive region597.

Example materials for dielectric structures615A and615B include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials. In an example structure of memory device200, dielectric structures615A and615B include a high-k dielectric material (e.g., a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide). Using such a high-k dielectric material (instead of silicon dioxide) can improve the performance (e.g., reduce current leakage, increase drive capability of transistor T1, or both) of memory device200.

As shown inFIG.6B, dielectric structure615A has opposing sides611and612in the X-direction. Portion510(read channel region of transistor T1) can be located on side611of dielectric structure615A. Material520(write channel region of transistor T2) can be located on side612of dielectric structure615A.

Memory device200can include dielectric structures655between adjacent memory cells in the X-direction. Dielectric structures655can electrically separate adjacent access lines among the access lines (e.g., access lines241R,241W,242R,242W,243R, and243W) associated with respective memory cells. Dielectric structures655can include an oxide material (e.g., silicon dioxide).

As shown inFIG.6B, access lines241R and241W can form gate251of transistor T1and gate252of transistor T2, respectively, of memory cell210. Access lines242R and242W can form gate251of transistor T1and gate252of transistor T2, respectively, of memory cell212. Access lines243R and243W can form gate251of transistor T1and gate252of transistor T2, respectively, of memory cell214.

As shown inFIG.6B, in memory cell210, gate251is opposite from gate252in the X-direction, which is a direction from the read channel region (included in portion510) of memory cell210to the write channel region (included in material520) of memory cell210. Gates251and252of each of the other memory cells (e.g., each of memory cells212and214) of memory device200can be located opposite from each other in the X-direction in a similar way as gates251and252of memory cell210.

Dielectric structure618R can be a gate oxide region that electrically separates gate251of transistor T1from portion510(e.g., read channel region of transistor T1) of a respective memory cell. Dielectric structure618W can be a gate oxide region that electrically separates gate252of transistor T2from material520(e.g., write channel region of transistor T2) of a respective memory cell. The material (or materials) for dielectric structures618R and618W can be the same as (or alternatively, different from) the material (or materials) of dielectric structures615A and615B. Example materials for dielectric structures618R and618W include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

FIG.6Bshows example locations (e.g., vertical positions) of access lines241R,241W,242R,242W,243R, and243W with respect to Z-direction. However, the locations of access lines241R,241W,242R,242W,243R, and243W with respect to Z-direction can be different from those shown inFIG.6B. For example, access lines241R,241W,242R,242W,243R, and243W can be positioned higher (e.g., can be moved up) in the Z-direction to be closer to data line271than the example locations shown inFIG.6B. In another example, access lines241R,241W,242R,242W,243R, and243W can be positioned lower (e.g., can be moved down) in the Z-direction to be farther from data line271than the example locations shown inFIG.6B. Further, the widths (e.g., height) in the Z-direction of access lines241R,241W,242R,242W,243R, and243W can be different from (e.g., less than or greater than) the widths of access lines241R,241W,242R,242W,243R, and243W shown inFIG.6B.

FIG.7Ashows a top view (e.g., plan view) of a portion of memory device700, according to some embodiments described herein.FIG.7Bshows a side view (e.g., cross-sectional view) taken along line7B-7B ofFIG.7A. Memory device700can be a variation of memory device200ofFIG.6AandFIG.6Band can include elements similar to (or the same as) the elements of memory device200. For simplicity, similar or the same elements between memory device200(FIG.6AandFIG.6B) and memory device700(FIG.7AandFIG.7B) are given the same labels and their descriptions are not repeated.

Differences between memory devices200and700include the arrangements of access lines241R,241W,242R,242W,243R, and243W and the relative locations of read and write channel regions (portions510and materials520) of adjacent memory cells in the Y-direction.

InFIG.6AandFIG.6Bdescribed above, the access lines are arranged in a pattern of read, write, read, write access lines (e.g., access lines241R,241W,242R,242W). Thus, two adjacent access lines (e.g., access lines241W and242R) are different types of access lines (read access line and write access line).

InFIG.7AandFIG.7B, the access lines can be arranged in a pattern such that two adjacent access lines can be the same type of access lines (either read access lines or write access lines). For example, access lines241W and242W (adjacent accesses lines) are write access lines. In another example, access lines242R and243R (adjacent access lines) are read access lines.

InFIG.7AandFIG.7B, the channel regions of adjacent memory cells in the Y-direction can also be the same type of channel regions (e.g., either read channel regions or write channel regions). For example, memory cells210and212(adjacent memory cells in the Y-direction) have adjacent write channel regions (materials520). In another example, memory cells212and214(adjacent memory cells in the Y-direction) have adjacent read channel regions (portions510).

Although not shown inFIG.7AandFIG.7B, memory device700can have separate drivers to separately drive respective access lines241R,241W,242R,242W,243R, and243W like memory device200.

The structures and operations of memory devices200and700described above provide improvements and benefits in the described memory devices in comparison with some conventional memory devices. For example, as described above, memory device200includes separate access lines (e.g., access line241R and241W) that form separate gates (e.g., gates251and252) to control transistors T1and T2, respectively, of a memory cell (e.g., memory cell210or211). Since transistor T2is controlled by a separate gate (e.g., gate252), the threshold voltage of transistor T2may not need to be relatively high (to avoid read disturbance of the memory cell) when transistor T1is turned on (using gate251) in a read operation. Thus, in comparison with a conventional device that uses the same access line to control multiple access transistors in a memory cell, the requirements associated with having a relatively higher threshold voltage for transistor T2in memory device200can be lessened. This can allow more options for forming the structure and selection of the material (e.g., material520) of transistor T2, leading to improving read and write operation of memory device200.

Some conventional memory devices may use multiple data lines to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. In memory device200, a single data line (e.g., data line271or272inFIG.2andFIG.3) can be used to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. This may also simplify the structure, operation, or both of memory device200in comparison with conventional memory devices that use multiple data lines to access a selected memory cell.

Further, the arrangement of the access lines described herein can provide built-in shield structures that can protect or prevent adjacent transistors from disturbance (e.g., channel region to channel region disturbance) during read and write operations of adjacent memory cells. For example, as shown inFIG.6B, access line242R can be a shield structure that shields access line241W from disturbance during a write operation performed on memory cell212(when access line242W is used to access transistor T2of memory cell212). In another example, as shown inFIG.6B, access line241W can be a shield structure that shields access line242R from disturbance during a read operation performed on memory cell210(when access line241R is used to access transistor T1of memory cell210).

Moreover, the arrangement of the access lines described herein (e.g., inFIG.5C) allows an option for the size (e.g., the area) of elements of the memory cell, including charge storage structure202, portion510(e.g., read channel region), and material520(e.g., write channel region), to be proportionally increased in the same direction (e.g., the X-direction). This size increase can improve (e.g., increase) storage capacitance of the memory cell.

FIG.8A,FIG.8B, andFIG.8Cshow different views of a structure of a memory device800including multiple decks of memory cells, according to some embodiments described herein.FIG.8Ashows an exploded view (e.g., in the Z-direction) of memory device800.FIG.8Bshows a side view (e.g., cross-sectional view) in the X-direction and the Z-direction of memory device800.FIG.8Cshows a side view (e.g., cross-sectional view) in the Y-direction and the Z-direction of memory device800.

As shown inFIG.8A, memory device800can include decks (decks of memory cells)8050,8051,8052, and8053that are shown separately from each other in an exploded view to help ease of viewing the deck structure of memory device800. In reality, decks8050,8051,8052, and8053can be attached to each other in an arrangement where one deck can be formed (e.g., stacked) over another deck over a substrate (e.g., a semiconductor (e.g., silicon) substrate)899. For example, as shown inFIG.8A, decks8050,8051,8052, and8053can be formed in the Z-direction perpendicular to substrate899(e.g., formed vertically in the Z-direction with respect to substrate899).

As shown inFIG.8A, each of decks8050,8051,8052, and8053can have memory cells arranged in the X-direction and the Y-direction (e.g., arranged in a matrix-like pattern with rows in the X-direction and in columns in the Y-direction). For example, deck8050can include memory cells8100,8110,8120, and8130(e.g., arranged in a row), memory cells8200,8210,8220, and8230(e.g., arranged in a row), and memory cells8300,8310,8320, and8330(e.g., arranged in a row). Deck8051can include memory cells8101,8111,8121, and8131(e.g., arranged in a row), memory cells8201,8211,8221, and8231(e.g., arranged in a row), and memory cells8301,8311,8321, and8331(e.g., arranged in a row). Deck8052can include memory cells8102,8112,8122, and8132(e.g., arranged in a row), memory cells8202,8212,8222, and8232(e.g., arranged in a row), and memory cells8302,8312,8322, and8332(e.g., arranged in a row). Deck8053can include memory cells8103,8113,8123, and8133(e.g., arranged in a row), memory cells8203,8213,8223, and8233(e.g., arranged in a row), and memory cells8303,8313,8323, and8333(e.g., arranged in a row).

As shown inFIG.8A, decks8050,8051,8052, and8053can be located (e.g., formed vertically in the Z-direction) on levels (e.g., portions)850,851,852, and853, respectively, of memory device800. The arrangement of decks8050,8051,8052, and8053forms a 3-dimensional (3-D) structure of memory cells of memory device800in that different levels of the memory cells of memory device800can be located (e.g., formed) in different levels (e.g., different vertical portions)850,851,852, and853of memory device800.

Decks8050,8051,8052, and8053can be formed one deck at a time. For example, decks8050,8051,8052, and8053can be formed sequentially in the order of decks8050,8051,8052, and8053(e.g., deck8051is formed first and deck8053is formed last). In this example, the memory cells of one deck (e.g., deck8051) can be formed either after formation of the memory cells of another deck (e.g., deck8050) or before formation of the memory cells of another deck (e.g., deck8052). Alternatively, decks8050,8051,8052, and8053can be formed concurrently (e.g., simultaneously), such that the memory cells of decks8050,8051,8052, and8053can be concurrently formed. For example, the memory cells in levels850,851,852, and853of memory device800can be concurrently formed.

The structures of decks8050,8051,8052, and8053can include the structures of memory devices200and700described above with reference toFIG.1throughFIG.7B. For example, the structures of the memory cells of decks8050,8051,8052, and8053can include the structure of the memory cells, access lines, and data lines described above with reference toFIG.1throughFIG.7B.

Memory device800can include data lines (e.g., bit lines) and access lines (e.g., word lines) to access the memory cells of decks8050,8051,8052, and8053. For simplicity, data lines and access lines of memory cells are omitted fromFIG.8A. However, the data lines and access lines of memory device800can be similar to the data lines and access lines, respectively, of the memory devices described above with reference toFIG.1throughFIG.7B.

FIG.8Ashows memory device800including four decks (e.g.,8050,8051,8052, and8053) as an example. However, the number of decks can be different from four.FIG.8Ashows each of decks8050,8051,8052, and8053including one level (e.g., layer) of memory cells as an example. However, at least one of the decks (e.g., one or more of decks8050,8051,8052, and8053) can have two (or more) levels of memory cells.FIG.8Ashows an example where each of decks8050,8051,8052, and8053includes four memory cells (e.g., in a row) in the X-direction and three memory cells (e.g., in a column) in the Y-direction. However, the number of memory cells in a row, in a column, or both, can vary. Since memory device800can include the structures of memory devices200and700, memory device800can also have improvements and benefits like memory devices200and700.

The illustrations of apparatuses (e.g., memory devices100,200,700, and800) and methods (e.g., operations of memory devices100and200) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of apparatuses that might make use of the structures described herein. An apparatus herein refers to, for example, either a device (e.g., any of memory devices100,200,700, and800) or a system (e.g., an electronic item that can include any of memory devices100,200,700, and800).

Any of the components described above with reference toFIG.1throughFIG.8Ccan be implemented in a number of ways, including simulation via software. Thus, apparatuses (e.g., memory devices100,200,700, and800) or part of each of these memory devices described above, may all be characterized as “modules” (or “module”) herein. Such modules may include hardware circuitry, single- and/or multi-processor circuits, memory circuits, software program modules and objects and/or firmware, and combinations thereof, as desired and/or as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and ranges simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.

The memory devices (e.g., memory devices100,200,700, and800) described herein may be included in apparatuses (e.g., electronic circuitry) such as high-speed computers, communication and signal processing circuitry, single- or multi-processor modules, single or multiple embedded processors, multicore processors, message information switches, and application-specific modules including multilayer, multichip modules. Such apparatuses may further be included as subcomponents within a variety of other apparatuses (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.

The embodiments described above with reference toFIG.1throughFIG.8Cinclude apparatuses and methods of operating the apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region. Other embodiments, including additional apparatuses and methods, are described.

In the detailed description and the claims, the term “on” used with respect to two or more elements (e.g., materials), one “on” the other, means at least some contact between the elements (e.g., between the materials). The term “over” means the elements (e.g., materials) are in close proximity, but possibly with one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither “on” nor “over” implies any directionality as used herein unless stated as such.

In the detailed description and the claims, a list of items joined by the term “at least one of” can mean any combination of the listed items. For example, if items A and B are listed, then the phrase “at least one of A and B” means A only; B only; or A and B. In another example, if items A, B, and C are listed, then the phrase “at least one of A, B and C” means A only; B only; C only; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

In the detailed description and the claims, a list of items joined by the term “one of” can mean only one of the list items. For example, if items A and B are listed, then the phrase “one of A and B” means A only (excluding B), or B only (excluding A). In another example, if items A, B, and C are listed, then the phrase “one of A, B and C” means A only; B only; or C only. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

The above description and the drawings illustrate some embodiments of the inventive subject matter to enable those skilled in the art to practice the embodiments of the inventive subject matter. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.