Patent ID: 12199631

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of a comparator and an analog to digital converter will be described with reference to the drawings. Hereinafter, the description will be focused on the main components of the comparator and the analog to digital converter, but there may exist components and functions that are not illustrated or described in the comparator and the analog to digital converter. The following description does not exclude the components and the functions that are not illustrated or described.

First Embodiment

FIG.1is a circuit diagram of a comparator1according to a first embodiment. The comparator1inFIG.1is used in, for example, a successive approximation type ADC as described later, but the application of the comparator1inFIG.1is not necessarily limited to the ADC. A differential input signal pair Vin_p, Vin_n are input to the comparator1inFIG.1. The comparator1outputs a differential output signal pair Vout_p, Vout_n corresponding to a difference signal of the differential input signal pair Vin_p, Vin_n. The comparator1inFIG.1is a kind of double-tail latch-type comparator.

The comparator1inFIG.1includes transistors (first to fourth transistors) Q1to Q4. With respect to the transistor Q1and the transistor Q2, sources thereof are connected to each other, the differential input signal pair Vin_p, Vin_n are input to gates thereof, and a differential output signal pair Vgm_p, Vgm_n are output from drains thereof.

The transistor Q3is connected between both the sources of the transistor Q1and the transistor Q2and a first reference voltage node (for example, a ground node), and is switched on or off in accordance with logic of a first signal. The first signal is, for example, a clock signal Clk having a predetermined frequency. When the clock signal Clk is at a high level, the transistor Q43is turned on, and the comparator1inFIG.1performs a comparison operation. The comparator1inFIG.1is in a stopped state without performing the comparison operation during a period in which the clock signal Clk is at a low level.

The transistor Q4is connected between both the sources of the transistor Q1and the transistor Q2and a second reference voltage node (for example, a power supply voltage node), and is switched on or off in accordance with logic of a second signal having logic different from that of the first signal. The second signal is, for example, an enable signal En. As described later, the enable signal En is turned on in a period in which the comparator1inFIG.1does not perform the comparison operation. When the transistor Q4is turned on, a path (hereinafter, it may be referred to as a tail node) connecting both the sources of the transistor Q1and the transistor Q2is set to a power supply potential. That is, the tail node connecting both the sources of the transistor Q1and the transistor Q2is set to the power supply potential, not to floating during a period in which the comparator1inFIG.1does not perform the comparison operation. Therefore, the voltage level of the tail node connecting both the sources of the transistor Q1and the transistor Q2is fixed to the power supply potential during a period in which the comparator1does not perform the comparison operation, and the voltage dependence of input parasitic capacitances Cin_p and Cin_n of a differential input node pair of the comparator1can be sufficiently reduced.

In the comparator1inFIG.1, the transistors Q1to Q3are N-type MOS transistors, and the transistor Q4is a P-type MOS transistor. As described later, the conductivity types of the transistors Q1to Q4can be reversed from those inFIG.1.

The comparator1inFIG.1includes a pull-up circuit2and a latch circuit3in addition to the transistors Q1to Q4described above.

The pull-up circuit2includes a transistor (fifth transistor) Q5and a transistor (sixth transistor) Q6. The transistor Q5and the transistor Q6are, for example, P-type MOS transistors. A clock signal Clk is input to both gates of the transistor Q5and the transistor Q6. Power supply voltage nodes are connected to both sources of the transistor Q5and the transistor Q6. The differential output signal pair Vout_p, Vout_n are output from respective drains of the transistor Q5and the transistor Q6.

The latch circuit3includes transistors (seventh to thirteenth transistors) Q7to Q13. The transistors Q7to Q10are, for example, N-type MOS transistors, and the transistors Q11to Q13are, for example, P-type MOS transistors. The differential output signal pair Vgm_p, Vgm_n are input to respective gates of the transistor Q7and the transistor Q9. A first output node n1is connected to each gate of the transistor Q10and the transistor Q12, and each drain of the transistor Q7, the transistor Q8, and the transistor Q11, and the Vout_p is output. A second output node n2is connected to each gate of the transistor Q8and the transistor Q11, and each drain of the transistor Q9, the transistor Q10, and the transistor Q12, and the Vout_n is output. A power supply voltage node is connected to a source of the transistor Q13, and each source of the transistor Q11and the transistor Q12is connected to a drain of the transistor Q13. An inversion signal xClk of the clock signal Clk is input to a gate of the transistor Q13.

The comparator1inFIG.1starts a comparison operation when the clock signal Clk transitions from a ground level (low level) to a power supply voltage level (high level). Before the comparator1inFIG.1starts the comparison operation, the clock signal Clk is at a low level, and the differential output signal pair Vgm_p, Vgm_n are pulled up to the power supply level.

When the clock signal Clk transitions to the power supply level, potentials of the differential output signal pair Vgm_p and Vgm_n decrease due to discharging by the transistors Q1, Q2. When “Vin_p>Vin_n”, “discharge rate of Vgm_p>discharge rate of Vgm_n” is obtained. On the other hand, when “Vin_p<Vin_n”, “discharge rate of Vgm_p<discharge rate of Vgm_n” is obtained. In this manner, the difference signal (Vin_p−Vin_n) of the differential input signal pair Vin_p, Vin_n of the comparator1causes a difference in discharge rate between Vgm_p and Vgm_n.

Furthermore, logic of the latch circuit3is determined according to the difference in discharge rate. If “discharge rate of Vgm_p>discharge rate of Vgm_n”, Vout_p=high/Vout_n=low is obtained, and if “discharge rate of Vgm_p<discharge rate of Vgm_n”, Vout_p=low/Vout_n=high is obtained.

FIG.2is a circuit diagram of a comparator1aaccording to a comparative example. InFIG.2, components common to those inFIG.1are denoted by the same reference numerals, and the description will be focused on differences hereinafter.

In the comparator1ainFIG.2, the transistor Q4inFIG.1is omitted. Other circuit configurations are similar to those inFIG.1. In the comparator1ainFIG.2, source potentials of the transistors Q1, Q2are in a floating state during a period in which a comparison operation is not performed. Therefore, an input voltage dependent error occurs in the voltage level of the differential input node pair due to input parasitic capacitances of input nodes of the differential input signal pair Vin_p, Vin_n of the comparator1a.

FIG.3is a graph illustrating the input voltage dependence of input parasitic capacitances of the comparators1,1ainFIGS.1and2.FIG.3illustrates simulation results. In FIG.3, the horizontal axis represents the input voltage [V], and the vertical axis represents the input parasitic capacitance [fF]. InFIG.3, a broken line waveform w1indicates the input voltage dependence of the comparator1inFIG.1, and a solid line waveform w2indicates the input voltage dependence of the comparator1ainFIG.2. The broken line waveform w1inFIG.3is a result of simulation performed in a state in which the enable signal En is set to a low level, and the tail node connecting the sources of the transistors Q1, Q2to each other is pulled up to the power supply voltage in the comparator1inFIG.1. In the comparator1ainFIG.2, the input parasitic capacitance greatly fluctuates according to the input voltage, but in the comparator1inFIG.1, a fluctuation amount of the input parasitic capacitance is greatly suppressed even if the input voltage changes.

FIG.4is a circuit diagram of a successive approximation type ADC4including the comparator1inFIG.1. The successive approximation type ADC4inFIG.4illustrates an example in which the differential input signal pair Vin_p, Vin_n are converted into a 5-bit digital signal. Note that the bit depth of the successive approximation type ADC4is arbitrary. Furthermore, the circuit configuration of the successive approximation type ADC4is not limited to that inFIG.4.

The successive approximation type ADC4inFIG.4includes a first sampling switch5, a second sampling switch6, a first digital to analog converter (hereinafter, first DAC)7, a second digital to analog converter (second DAC)8, the comparator1, and a control circuit (SAR logic)10. In the present specification, the first DAC7and the second DAC8are collectively referred to as a capacitive DAC20.

The first sampling switch5switches whether or not to sample one signal Vin_p of the differential input signal pair Vin_p, Vin_n. The second sampling switch6switches whether or not to sample the other signal Vin_n of the differential input signal pair Vin_p, Vin_n.

The first DAC7converts the one sampled signal Vin_p into a digital signal including a plurality of bits bit by bit in order, and outputs a signal having a voltage level corresponding to unconverted bits.

The first DAC7includes five capacitors C1to C5having different capacitances by powers of two, and three switches (first to third switches) SW1to SW3connected to each of the capacitors C1to C5. The first switches SW1switch whether or not to set one ends of the corresponding capacitors C1to C5to 0 V. The second switches SW2switch whether or not to set one ends of the corresponding capacitors C1to C5to a common voltage Vcom. The third switches SW3switch whether or not to set one ends of the corresponding capacitors C1to C5to a reference voltage Vref. The common voltage Vcom is, for example, a voltage level of ½ of the reference voltage Vref.

The first to third switches SW1to SW3are switched on or off on the basis of a control signal from the control circuit10. The control circuit10turns on the second switch SW2at the start of a comparison operation. Thereafter, the control circuit10turns on the first switch SW1in a case where it is desired to lower the output node voltage Vin_p of the first DAC7, and turns on the third switch SW3in a case where it is desired to increase the output node voltage Vin_p of the first DAC7.

The second DAC8converts the other sampled signal into a digital signal including a plurality of bits bit by bit in order, and outputs a signal having a voltage level corresponding to unconverted bits. The second DAC8is configured similarly to the first DAC7, and switches the first to third switches SW1to SW3on the basis of the control signal from the control circuit10similarly to the first DAC7.

The comparator1has the configuration illustrated inFIG.1. The differential input signal pair Vin_p, Vin_n in which an output signal of the first DAC7and an output signal of the second DAC8form a pair are input to the comparator1. The comparator1outputs signals corresponding to the difference signal of the differential input signal pair Vin_p, Vin_n.

The control circuit10performs switching control of the first to third switches SW1to SW3in the first DAC7and the second DAC8on the basis of the output signals of the comparator1.

A control signal Clk_adc is input to the ADC4. The control signal Clk_adc is inverted by an inverter9ato generate an enable signal En. The enable signal En is input to the gate of the transistor Q4in the comparator1inFIG.1. When the control signal Clk_adc is at a high level, the enable signal En becomes a low level, and the transistor Q4pulls up the tail node connecting the sources of the transistors Q1, Q2to each other.

Furthermore, an inversion signal of the control signal Clk_adc by an inverter9bis input to an AND gate11. When the control signal Clk_adc becomes a low level from a high level, the clock signal Clk becomes a high level. Accordingly, the comparator1performs a comparison operation. The differential output signal pair Vout_p, Vout_n output from the comparator1are input to the control circuit10and input to a NOR gate12. When one signal of the differential output signal pair Vout_p, Vout_n becomes a high level, the output of the NOR gate12becomes a low level. In this case, the output of an AND gate13becomes a low level, and the clock signal Clk is fixed at a low level. Accordingly, the comparator1is reset.

The AND gate11calculates a logical product of the signal obtained by inverting the control signal Clk_adc by the inverter9band the output signal of the NOR gate12. The output of the AND gate11becomes a high level in a case where the control signal Clk_adc is at a low level and both the differential output signal pair Vout_p, Vout_n of the comparator1are at a low level.

The AND gate13calculates a logical product of the output signal of the AND gate11and the signal obtained by inverting a flag signal comp_end of the control circuit10by the inverter14. The output of the AND gate13becomes a high level in a case where the flag signal comp_end of the control circuit10is at a low level, and in a case where the output of the AND gate11is at a high level. When all control in the capacitive DAC20is completed, the control circuit10sets the flag signal comp_end to a high level.

In the ADC4inFIG.4, first, the first sampling switch5and the second sampling switch6are turned on, and the differential input signal pair Vin_p, Vin_n are sampled to the capacitive DAC20. At this time, logic of the control signal Clk_adc is at a high level, and the clock signal Clk input to the comparator1is at a low level.

Thereafter, when the control signal Clk_adc transitions from the high level to the low level, sampling is completed, and the clock signal Clk transitions from the low level to the high level, and the comparator1starts a comparison operation. The control circuit10turns on any of the first to third switches SW1to SW3connected to the capacitor of the most significant bit in the capacitive DAC20on the basis of the comparison result by the comparator1, and controls the output voltage (Vin_p−Vin_n) of the capacitive DAC20. The control circuit10controls switching on or off of the first to third switches SW1to SW3connected to the capacitors C1to C5bit by bit in order from the high-order side bit in the capacitive DAC20. Therefore, the output voltage (Vin_p−Vin_n) of the capacitive DA is gradually approaches zero.

In the control circuit10, the output of the NOR gate12transitions to a low level each time each comparison operation ends. Therefore, the clock signal Clk, which is the output of the AND gate13, becomes a low level, and the transistor Q3in the comparator1is turned off. Therefore, the comparator1is reset each time each comparison operation ends. Thereafter, when the output of the AND gate13transitions to a high level, and the clock signal Clk becomes a high level, switching on or off of the first to third switches SW1to SW3connected to the capacitor C2, which is a second bit from the most significant bit in the capacitive DAC20, is performed.

By repeating the above control, the output voltage of the capacitive DAC20gradually approaches zero. The capacitive DAC20inFIG.4has 5 bits, so that charging and discharging control of the capacitors C1to c5in the capacitive DAC20is performed five times. When the charging and discharging control is completed, the control circuit10outputs the flag signal comp_end, the Clk becomes low, and the comparator1becomes a reset state. Thereafter, when the control signal Clk_adc transitions from low to high, the differential input signal pair Vin_p, Vin_n are sampled again.

Input parasitic capacitances Cin_p, Cin_n exist in a differential input node pair n1, n2of the comparator1inFIG.4. In the embodiment, the tail node connecting the sources of the transistors Q1, Q2to each other is pulled up to the power supply voltage by the transistor Q4during a period in which the comparator1does not perform a comparison operation. Therefore, even if there are input parasitic capacitances in the differential input node pair n1, n2, the input voltage dependence of the parasitic capacitances can be suppressed.

Accordingly, the control amount when controlling the capacitive DAC20is not affected by an input voltage dependent error of the differential input node pair n1, n2, so that deterioration of various characteristics such as distortion of the ADC4can be suppressed.

FIG.5is a waveform diagram of the control signal Clk_adc, the enable signal En, and the clock signal Clk in the comparator1inFIG.4. As illustrated, the logic of the control signal Clk_adc is opposite to that of the enable signal En. The clock signal Clk intermittently becomes a high level a plurality of times during a period in which the enable signal En is at a high level. The comparator1performs a comparison operation during a period in which the clock signal Clk is at a high level. In a case where the capacitive DAC20includes five capacitors C1to C5, the comparator1performs the comparison operation five times, and turns on any of the first to third switches SW1to SW3connected to one ends of the capacitors in order from the capacitor on the high-order side to control charging and discharging of the capacitor.

FIG.6is a circuit diagram of a successive approximation type ADC4a, according to a comparative example, including the comparator1ainFIG.2. The ADC4ainFIG.6has a configuration in which the inverter9bis omitted from the ADC4inFIG.4. The enable signal En is not input to the comparator1ain the ADC4ainFIG.6.

In the ADC4ainFIG.6, during a sampling period of the differential input signal pair Vin_p, Vin_n, the logic of the control signal Clk_adc is at a high level, and the clock signal Clk input to the comparator1ais at a low level. That is, during the sampling period, the tail node connecting the sources of the transistors Q1, Q2in the comparator1inFIG.2to each other is floating, and the potential is undefined.

The input parasitic capacitances Cin_p, Cin_n of the comparator1exist in the output signal paths n1, n2of the capacitive DAC20in the ADC4ainFIG.6. In the state where the tail node connecting the sources of the transistors Q1, Q2in the comparator1to each other is in a floating state, the input parasitic capacitances Cin_p, Cin_n have input voltage dependence. More specifically, when the first sampling switch5and the second sampling switch6are turned on to sample the differential input signal pair Vin_p, Vin_n, the differential input signal pair Vin_p, Vin_n are sampled also in the input parasitic capacitances Cin_p, Cin_n. Charges sampled in the input parasitic capacitances Cin_p, Cin_n are determined according to capacitance values of the input parasitic capacitances Cin_p and Cin_n. However, when the input parasitic capacitances Cin_p and Cin_n have input voltage dependence, charges stored in the input parasitic capacitances Cin_p and Cin_n also have input voltage dependence. This dependence of the charges gives an input voltage dependent error to the control amount when controlling the capacitive DAC20, and also gives an input voltage dependent error to the conversion result of the ADC4a. As a result, there is a possibility that deterioration of various characteristics such as distortion of the ADC4ais caused.

On the other hand, in the comparator1inFIG.1, the tail node connecting the sources of the transistors Q1, Q2in the comparator1to each other is pulled up to the power supply voltage by the transistor Q4at the time of sampling the differential input signal pair Vin_p, Vin_n. Accordingly, there is no possibility that the input parasitic capacitances Cin_p and Cin_n have input voltage dependence, so that the capacitive DAC20can be controlled with high accuracy.

In this manner, in the comparator1according to the first embodiment, the tail node connecting the sources of the transistors Q1, Q2, which generate signals corresponding to the difference signal of the differential input signal pair Vin_p, Vin_n, to each other is pulled up to the power supply voltage level before the comparator1starts the comparison operation. Therefore, the input parasitic capacitances Cin_p, Cin_n of the comparator1do not have input voltage dependence, so that the comparison operation by the comparator1can be performed with high accuracy. Accordingly, AD conversion accuracy of the ADC4incorporating the comparator1can also be improved.

Second Embodiment

A comparator1baccording to a second embodiment is obtained by reversing the conductivity type of each transistor in the comparator1bfrom that in the comparator1inFIG.1.

FIG.7is a circuit diagram of the comparator1baccording to the second embodiment. The comparator1binFIG.7includes transistors Q21to Q24. The transistors Q21to Q23are P-type MOS transistors, and the transistor Q24is an N-type MOS transistor. An inversion signal xEn of the enable signal En inFIG.1is input to a gate of the transistor Q24. An inversion signal of the clock signal Clk inFIG.1is input to a gate of the transistor Q23.

In addition, the comparator1binFIG.7includes a pull-down circuit15and a latch circuit3a. The pull-down circuit15includes a transistor Q45and a transistor Q46connected between respective drains of the first and the transistor Q2and the ground terminals. The inversion signal xClk of the clock signal Clk is input to each gate of the transistor Q45and the transistor Q46. The transistor Q45and the transistor Q46are N-type MOS transistors.

The latch circuit3aincludes transistors Q27to Q33. Among them, the transistors Q27to Q30are P-type MOS transistors, and the transistors Q31to Q33are N-type MOS transistors.

In the comparator1binFIG.7, the conductivity type of each transistor is opposite to that in the comparator1inFIG.1, and connection order of the transistors connected between the power supply voltage node and the ground node is opposite to that in the comparator1inFIG.1, but the comparison operation itself is the same.

When the xClk transitions to a low level, potentials of the differential output voltage pair Vgm_p, Vgm_n increase due to charging by the transistors Q1, Q2. When “Vin_p>Vin_n”, “charge speed of Vgm_p<charge speed of Vgm_n” is obtained. On the other hand, when “Vin_p<Vin_n”, “charge speed of Vgm_p>charge speed of Vgm_n” is obtained. In this manner, the difference signal (Vin_p−Vin_n) of the differential input voltage pair of the comparator1bcauses a difference in charge speed between Vgm_p and Vgm_n.

Moreover, logic of the latch circuit3ain the subsequent stage is determined according to the difference in charge speed. If “charge speed of Vgm_p<charge speed of Vgm_n”, Vout_p=High/Vout_n=Low is obtained, and if “charge speed of Vgm_p>charge speed of Vgm_n”, Vout_p=Low/Vout_n=High is obtained.

The transistor Q24is provided at the tail node connecting sources of the transistors Q1, Q2in the comparator1binFIG.7to each other. The transistor Q24is controlled by the inversion signal xEn of the enable signal En. The transistor Q24is turned on to be pulled down to the ground level while the ADC4performs sampling. In this state, the voltage dependence of the input parasitic capacitances Cin_p and Cin_n of the comparator1bcan be sufficiently reduced. Therefore, deterioration of various characteristics such as distortion of the ADC4can be prevented.

Third Embodiment

In a third embodiment, configurations of a pull-up circuit2and a latch circuit3are different from those inFIG.1.

FIG.8is a circuit diagram of a comparator1caccording to the third embodiment. The comparator1cinFIG.8includes N-type MOS transistors Q1to Q4, Q14to Q15, and P-type MOS transistors Q16to Q19.

The transistors Q16, Q17constitute a pull-up circuit2a. InFIG.1, the pull-up circuit2is connected to the drains of the transistors Q1, Q2, but inFIG.8, the pull-up circuit2ais connected to a first output node and a second output node Vout_p, Vout_n.

A latch circuit3binFIG.8includes the transistors Q14, Q15, Q18, and Q19. Each gate of the transistors Q14, Q18and each drain of the transistors Q15, Q19are connected to the first output node Vout_p. Each gate of the transistors Q15, Q19and each drain of the transistors Q14, Q18are connected to the second output node Vout_n.

Also in the comparator1cinFIG.8, each drain of the transistors Q3, Q4is connected to the tail node connecting the respective sources of the transistors Q1, Q2, and when the enable signal En is at a low level, the transistor Q4is turned on to pull up the tail node to the power supply voltage level. Therefore, the voltage dependence of the input parasitic capacitances Cin_p and Cin_n of the comparator1ccan be sufficiently reduced, so that deterioration of various characteristics such as distortion of the ADC4can be prevented.

Fourth Embodiment

In a fourth embodiment, a differential signal output pair output from the respective drains of the transistors Q1, Q2are waveform-shaped and then input to a latch circuit3.

FIG.9is a circuit diagram of a comparator1daccording to the fourth embodiment. The comparator1dinFIG.9includes inverters16,17connected to the drains of the transistors Q1, Q2. Output signals of the inverters16,17are input to a latch circuit3c. The latch circuit3cincludes N-type MOS transistors Q14to Q17, Q34, and Q35, and P-type MOS transistors Q18, Q19.

The latch circuit3cinFIG.9has a configuration in which the transistors Q34, Q35are added to the latch circuit3binFIG.8. The transistor Q34is connected between the respective drains of the transistors Q14, Q18. The transistor Q35is connected between the respective drains of the transistors Q15, Q19.

Output signals of the inverters16,17are input to the respective gates of the transistors Q34, Q35.

The inverters16,17perform waveform shaping to steepen waveforms of the differential output signal pair Vout_p, Vout_n output from the respective drains of the transistors Q1, Q2. By inputting the differential output signal pair Vout_p, Vout_n to the latch circuit3cvia the inverters16,17, a latch operation of the latch circuit3ccan be speeded up.

Also in the comparator1dinFIG.9, each drain of the transistors Q3, Q4is connected to the tail node connecting the respective sources of the transistors Q1, Q2, and when the enable signal En is at a low level, the transistor Q4is turned on to pull up the tail node to the power supply voltage level. Therefore, the voltage dependence of the input parasitic capacitances Cin_p and Cin_n of the comparator1can be sufficiently reduced, so that deterioration of various characteristics such as distortion of the ADC4can be prevented.

Fifth Embodiment

The comparators1to1dinFIGS.1and7to9described above can be used in the ADC4inFIG.4, but can also be applied to other types of ADCs, and there may be a case where internal configurations of the comparators1to1dneed to be partially changed in accordance with the configuration of the ADC.

FIG.10is a circuit diagram of an ADC4bincluding a filter circuit21in addition to the capacitive DAC20. The filter circuit21inFIG.10samples a differential output signal pair Vin_p, Vin_n output from the capacitive DAC20. The first differential output signal pair Vin_p, Vin_n output from the capacitive DAC20and a second differential output signal pair Vns_p, Vns_n output from the filter circuit21are input to a comparator1ein the ADC4binFIG.10. In this manner, the comparator1einFIG.10includes terminals to which two differential input signal pairs (Vin_p, Vin_n), (Vns_p, Vns_n) are input, and outputs signals corresponding to the difference signals of the respective differential input signal pairs (Vin_p, Vin_n), (Vns_p, Vns_n).

The ADC4binFIG.10includes the filter circuit21. Accordingly, the differential output signals, of the capacitive DAC20, that have not become zero are sampled by the filter circuit21, and are input to the comparator1e. Therefore, accuracy of analog to digital conversion can be further improved.

FIG.11is a circuit diagram illustrating an example of an internal configuration of the comparator1eused in the ADC4binFIG.10. The comparator1einFIG.11includes a first input terminal TL1and a second input terminal TL2to which the first differential input signal pair Vin_p, Vin_n are input, a third input terminal TL3and a fourth input terminal TL4to which the second differential input signal pair Vns_p, Vns_n are input, and a comparison circuit22.

The comparison circuit22outputs signals corresponding to a difference signal of the first differential input signal pair Vin_p, Vin_n input to the first input terminal TL1and the second input terminal TL2and a difference signal of the second differential input signal pair Vns_p, Vns_n input to the third input terminal TL3and the fourth input terminal TL4.

The comparison circuit22outputs, to the first output node n1and the second output node n2, a first differential output signal pair, corresponding to the difference signal of the first differential input signal pair Vin_p, Vin_n, generated by connecting the first input terminal TL1to a positive side and connecting the second input terminal TL2to a negative side. The voltage fluctuation amount of the third input terminal TL3generated according to the voltage fluctuation of the first output node n1is equal to the voltage fluctuation amount of the fourth input terminal TL4generated according to the voltage fluctuation of the second output node n2.

The comparison circuit22includes a first comparison device24and a second comparison device25.

The first comparison device24outputs, to the first output node n1and the second output node n2, the first differential output signal pair, corresponding to the difference signal of the first differential input signal pair Vin_p, Vin_n, generated by connecting the first input terminal TL1to the positive side and connecting the second input terminal TL2to the negative side.

The second comparison device25outputs, from the first output node n1and the first output node n2, the second differential output signal pair, corresponding to the difference signal of the second differential input signal pair, generated by connecting the third input terminal TL3to the positive side and connecting the fourth input terminal TL4to the negative side.

The first comparison device24includes N-type MOS transistors Q41, Q42. The first differential input signal Vin_p is input to a gate of the transistor Q41. The gate of the transistor Q41is the positive side. The first differential input signal Vin_n is input to a gate of the transistor Q42. The gate of the transistor Q42is the negative side.

An N-type MOS transistor Q43is connected between respective sources of the transistors Q41, Q42and a ground node. A clock signal Clk is input to a gate of the transistor Q43. The transistors Q41, Q42perform a comparison operation of the first differential input signal pair Vin_p, Vin_n when the clock signal Clk is at a high level, and stop the comparison operation when the clock signal Clk is at a low level. A drain of the transistor Q41is connected to the first output node n1, and a drain of the transistor Q42is connected to the second output node n2.

Furthermore, a P-type MOS transistor Q68is connected between the sources of the transistors Q41, Q42and a power supply voltage node (second reference voltage node). An enable signal En is input to a gate of the transistor Q68. The transistor Q68performs the same operation as the transistor Q4inFIG.1.

The second comparison device25includes N-type MOS transistors Q44, Q45. The first differential input signal Vns_p is input to a gate of the transistor Q44. The gate of the transistor Q44is the positive side. The second differential input signal Vns_n is input to a gate of the transistor Q45. The gate of the transistor Q45is the negative side.

An N-type MOS transistor Q46is connected between sources of the transistors Q44, Q45and a ground node. A clock signal Clk is input to a gate of the transistor Q46. The transistors Q41, Q42perform a comparison operation of the first differential input signal pair Vin_p, Vin_n when the clock signal Clk is at a high level, and stop the comparison operation when the clock signal Clk is at a low level. Respective drains of the transistors Q44, Q45are connected to the first output node n1and the second output node n2.

Furthermore, a P-type MOS transistor Q69is connected between the sources of the transistors Q44, Q45and a power supply voltage node (second reference voltage node). An enable signal En is input to a gate of the transistor Q69. The transistor Q69performs the same operation as the transistor Q4inFIG.1.

A pull-up circuit (first voltage setting circuit)26is connected to the first output node n1and the second output node n2. The pull-up circuit26pulls up the first output node n1and the second output node n2to a high level when the clock signal Clk is at a low level, that is, during a period in which the comparison circuit22does not perform a comparison operation. The pull-up circuit26includes a P-type MOS transistor Q47connected to the first output node n1, and a P-type MOS transistor Q48connected to the second output node n2. A clock signal Clk is input to gates of the transistors Q47, Q48.

A latch circuit30includes P-type MOS transistors Q57to Q60, and N-type MOS transistors Q61to Q66. The first output node n1is connected to each gate of the transistors Q57, Q61, and Q62. The second output node n2is connected to each gate of the transistors Q58, Q64, and Q65. Each gate of the transistors Q60and Q66and each drain of the transistors Q59, Q63are connected to an output terminal TL5that outputs a differential output voltage Vout_p of the comparator1e. Each gate of the transistors Q59and Q63and each drain of the transistors Q65, Q66are connected to an output terminal TL6that outputs a differential output voltage Vout_n of the comparator1e.

In the comparator1einFIG.11, similar to the comparators1to1daccording to the first to fourth embodiments described above, the tail node in each comparison device is pulled up during a period in which the comparator1edoes not perform a comparison operation. Accordingly, the voltage dependence of the input parasitic capacitances Cin_p and Cin_n of the comparator1ecan be sufficiently reduced, so that deterioration of various characteristics such as distortion of the ADC4bcan be prevented.

Note that the present technology can have the following configurations.

(1) A comparator including: a first transistor and a second transistor that include two sources connected to each other, two gates to which a differential input signal pair are input, and two drains that output a differential output signal pair corresponding to a difference signal of the differential input signal pair;a third transistor that is connected between both the sources of the first transistor and the second transistor and a first reference voltage node, the third transistor being switched on or off in accordance with logic of a first signal; anda fourth transistor that is connected between both the sources of the first transistor and the second transistor and a second reference voltage node, the fourth transistor being switched on or off in accordance with logic of a second signal having logic different from the logic of the first signal.

(2) The comparator described in (1), in which the fourth transistor is turned on in a period in which the first transistor and the second transistor do not perform a comparison operation of the difference signal of the differential input signal pair.

(3) The comparator described in (1) or (2), in which the third transistor is intermittently turned on during a period in which the fourth transistor is off.

(4) The comparator described in any one of (1) to (3), further including a latch circuit that holds the differential output signal pair.

(5) The comparator described in (4), further including a waveform shaping circuit that performs waveform shaping of the differential output signal pair output from both the drains of the first transistor and the second transistor,in which a signal after waveform shaping performed by the waveform shaping circuit is input to the latch circuit.

(6) The comparator described in (5), in which the waveform shaping circuit includes two inverters that invert logic of the differential output signal pair.

(7) The comparator described in any one of (4) to (6)), further including a fifth transistor that switches whether or not to perform a holding operation by the latch circuit in accordance with the logic of the first signal,in which the fifth transistor is intermittently turned on during a period in which the fourth transistor is off.

(8) The comparator described in any one of (1) to (7), in which the fourth transistor has a conductivity type different from a conductivity type of the third transistor.

(9) The comparator described in any one of (1) to (8), in which the first transistor, the second transistor, and the third transistor include N-type MOS transistors, andthe fourth transistor includes a P-type MOS transistor.

(10) The comparator described in any one of (1) to (8), in which the first transistor, the second transistor, and the third transistor include P-type MOS transistors, andthe fourth transistor includes an N-type MOS transistor.

(11) The comparator described in any one of (1) to (10), further including:a first input terminal and a second input terminal to which a first differential input signal pair are input;a third input terminal and a fourth input terminal to which a second differential input signal pair are input; anda comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair input to the first input terminal and the second input terminal and a difference signal of the second differential input signal pair input to the third input terminal and the fourth input terminal,in which the comparison circuit includes:a first comparison device that includes sixth to ninth transistors having a same circuit configuration as a circuit configuration of the first to fourth transistors; anda second comparison device that includes tenth to thirteenth transistors having the same circuit configuration as the circuit configuration of the first to fourth transistors.

(12) An analog to digital converter including: a first sampling switch that switches whether or not to sample one signal of a differential input signal pair;a first digital to analog converter that converts the one signal sampled into a digital signal including a plurality of bits bit by bit in order, and outputs a signal having a voltage level corresponding to an unconverted bit;a second sampling switch that switches whether or not to sample another signal of the differential input signal pair;a second digital to analog converter that converts the another signal sampled into a digital signal including a plurality of bits bit by bit in order, and outputs a signal having a voltage level corresponding to an unconverted bit;a comparator that outputs a signal corresponding to a difference signal of a first differential input signal pair in which an output signal of the first digital to analog converter and an output signal of the second digital to analog converter form a pair; anda control circuit that controls the first digital to analog converter and the second digital to analog converter on the basis of an output signal of the comparator,in which the comparator includes:a first transistor and a second transistor that include two sources connected to each other, two gates to which the first differential input signal pair are input, and two drains that output a differential output signal pair corresponding to the difference signal of the first differential input signal pair;a third transistor that is connected between both the sources of the first transistor and the second transistor and a first reference voltage node, the third transistor being switched on or off in accordance with logic of a first signal; anda fourth transistor that is connected between both the sources of the first transistor and the second transistor and a second reference voltage node, the fourth transistor being switched on or off in accordance with logic of a second signal having logic different from the logic of the first signal.

(13) The analog to digital converter described in (12), further including a filter circuit that samples and outputs the output signal of the first digital to analog converter and the output signal of the second digital to analog converter,in which the comparator outputs a signal corresponding to the difference signal of the first differential input signal pair in which the output signal of the first digital to analog converter and the output signal of the second digital to analog converter form a pair and a difference signal of a second differential input signal pair output from the filter circuit,the comparator includes:a first input terminal and a second input terminal to which the first differential input signal pair are input;a third input terminal and a fourth input terminal to which the second differential input signal pair are input; anda comparison circuit that outputs a signal corresponding to the difference signal of the first differential input signal pair input to the first input terminal and the second input terminal and the difference signal of the second differential input signal pair input to the third input terminal and the fourth input terminal, andthe comparison circuit includes the first to fourth transistors.

Aspects of the present disclosure are not limited to individual embodiments described above, but include various modifications that can be conceived by those skilled in the art, and advantageous effects of the present disclosure are not limited to the contents described above. That is, various additions, modifications, and partial deletions can be made without departing from the conceptual idea and spirit of the present disclosure derived from the contents defined in claims and equivalents thereof.

REFERENCE SIGNS LIST

1,1a,1b,1c,1d,1eComparator2Pull-up circuit3Latch circuit4,4a,4bADC5First sampling switch6Second sampling switch7First DAC8Second DAC9a,9bInverter10Control circuit11AND gate12NOR gate13AND gate14Inverter20Capacitive DAC21Filter circuit22Comparison circuit30Latch circuit