Patent ID: 12218054

DETAILED DESCRIPTION

When metal wires at the same level include both a narrow wire and a wide wire, it may be difficult to form the narrow and wide wires to have low electrical resistances and be structurally stable using the same process. If a damascene process is used to form narrow and wide wires, the narrow wire may move during the process, and defects thus may occur. If an etch process is used to form narrow and wide wires, a number of metal layers included in the narrow and wide wires may be limited, and the wide wire may have high electrical resistance.

According to some embodiments of the present inventive concept, two separate processes may be used to form a narrow wire and a wide wire that are at the same level. In some embodiments, a narrow wire may be formed by an etch process, and a wide wire may be formed by a damascene process.

FIG.1Ais a cross-sectional view of an integrated circuit device taken along the line A-A′ ofFIG.1Baccording to some embodiments of the inventive concept.FIG.1Bis a schematic layout of the integrated circuit device ofFIG.1Aaccording to some embodiments of the inventive concept.

Referring toFIGS.1A and1B, the integrated circuit device may include an upper wire460and lower wires that include first metal wires210and second metal wires310. The first metal wires210and the second metal wires310may be spaced apart from each other in a first direction D1. Multiple first metal wires210(e.g., four first metal wires210) may be provided between two second metal wires310. Each of the first metal wires210and second metal wires310may extend in a second direction D2. The second direction D2may be perpendicular to the first direction D1. As used herein, “an element A extends in a direction X” (or similar language) may mean that the element A extends longitudinally in the direction X. The first direction D1and the second direction D2may be a first horizontal direction and a second horizontal direction, respectively.

A widest width of the first metal wire210in the first direction D1may be narrower than a widest width of the second metal wire310in the first direction D1. For example, a pitch P of the first metal wire210may be about 24 nm.

The lower wires210and310and the upper wire460may be stacked in a third direction D3. The third direction D3may be perpendicular to both the first direction D1and the second direction D2. The third direction D3may be a vertical direction. The upper wire460may extend in the first direction D1. AlthoughFIG.1Ashows a single upper wire460, multiple upper wires460may be provided.

Each of the first metal wires210may be electrically connected to an element of a transistor (e.g., a source/drain region, or a gate). Each of the second metal wires310may be electrically connected to a power source (e.g., Vdd or Vss) of the integrated circuit device. The upper wire460may be electrically connected to at least one of the first metal wires210and the second metal wires310.

Referring toFIG.1A, the integrated circuit device may include a first insulating layer190, a second insulating layer290, and a third insulating layer390sequentially stacked. Each of the first insulating layer190, the second insulating layer290, and the third insulating layer390may include an insulating material (e.g., silicon oxide, or low dielectric material). Lower contacts160may be provided in the first insulating layer190. Each of the lower contacts160may include a conductive material and may electrically connect one of the first metal wires210or one of the second metal wires310to an element of the integrated circuit device.

The first metal wires210and the second metal wires310may be provided on the first insulating layer190and in the second insulating layer290. Each of the lower wires includes a lower surface contacting the first insulating layer190.

In some embodiments, lower surfaces210L of the first metal wires210may be coplanar with lower surfaces310L of the second metal wires310as illustrated inFIG.1A. The first metal wire210may have a first width in the first direction D1monotonically decreasing from the lower surface210L to an upper surface210U thereof. The second metal wires310may have a second width in the first direction D1monotonically increasing from the lower surface310L to an upper surface310U thereof. The first width of the lower surface210L of the first metal wire210may be narrower than the second width of the upper surface310U of the second metal wire310.

AlthoughFIG.1Ashows both the first metal wires210and the second metal wires310have slanted sidewalls, in some embodiments, at least some of the first metal wires210and the second metal wires310may have vertical sidewalls and may have a uniform width in the first direction D1along the third direction D3.

In some embodiments, the upper surface210U of the first metal wire210may be farther from the first insulating layer190than the upper surface310U of the second metal wire310as illustrated inFIG.1A. In some embodiments, the upper surface210U of the first metal wire210may be coplanar with the upper surface310U of the second metal wire310.

The first metal wire210may include a first adhesion layer220and a first metal layer260that are sequentially stacked. The first adhesion layer220may include, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiO), titanium (Ti) and/or tantalum (Ta). The first metal layer260may include, for example, ruthenium (Ru), molybdenum (Mo), cobalt (Co), and/or tungsten (W). As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.

The second metal wire310may include a second adhesion layer320, a first thin metal layer340, and a second metal layer360. The second adhesion layer320may include, for example, TiN, TaN, TiO, Ti, and/or Ta. The first thin metal layer340may include, for example, Ru, Mo, Co, and/or W. The second metal layer360may include, for example, copper (Cu). In some embodiments, both the first metal layer260and the first thin metal layer340may include the same metal element (e.g., Ru). In some embodiments, the first metal layer260may not include a metal element that is included in the second metal layer360.

A first etch stop layer270may extend between the first insulating layer190and the second insulating layer290. The first etch stop layer270may contact both the first insulating layer190and the second insulating layer290. The first etch stop layer270may have a uniform thickness as illustrated inFIG.1A. The first etch stop layer270may extend on a sidewall of the first metal wires210. In some embodiments, the first etch stop layer270may contact an entirety of the sidewall of the first metal wires210as illustrated inFIG.1A. The second metal wires310may extend through the first etch stop layer270and may contact the first insulating layer190as illustrated inFIG.1A.

A second etch stop layer370may extend on the first metal wires210and the second metal wires310. The second etch stop layer370may extend between the second insulating layer290and the third insulating layer390. A lower surface of the second etch stop layer370may contact the upper surface210U of the first metal wire210. The upper surface310U of the second metal wire310may not be higher than the lower surface of the second etch stop layer370. In some embodiments, the upper surface310U of the second metal wire310may contact the lower surface of the second etch stop layer370as illustrated inFIG.1A.

Each of the first etch stop layer270and the second etch stop layer370may include, for example, silicon carbon nitride (SiCN), aluminum oxide (AlO), and/or aluminum nitride (AlN). In some embodiments, the first etch stop layer270and/or the second etch stop layer370may be a SiCN layer.

The upper wire460may include contact portions460cand a liner portion460w. Each of the contact portions460may contact one of the first metal wires210or one of the second metal wires310. The upper wire460may include, for example, Cu. AlthoughFIG.1Ashows that the upper wire460includes three contact portions460c, the upper wire460may include a single contact portion460c, two contact portions460c, or more than three contact portions460c.

A third adhesion layer420and a second thin metal layer440may be provided between the upper wire460and the third insulating layer390. The third adhesion layer420may include, for example, TiN, TaN, TiO, Ti, and/or Ta. The second thin metal layer440may include, for example, Ru, Mo, Co, and/or W.

FIG.2Ais a cross-sectional view of an integrated circuit device taken along the line B-B′ ofFIG.2Baccording to some embodiments of the inventive concept.FIG.2Bis a schematic layout of the integrated circuit device ofFIG.2Aaccording to some embodiments of the inventive concept.

The first metal wires210may include a tall first metal wire210′ that may have an upper surface210′U farther from the first insulating layer190than the upper surfaces210U of remaining first metal layers210and may include a contact portion260cprovided above the upper the upper surfaces210U of remaining first metal layers210. The upper surface210′U of the tall first metal wire210′ may contact the lower surface of the upper etch stop layer370.

In some embodiments, the upper surface310U of the second metal wires may be closer to the first insulating layer190than the upper surface210′U of the tall first metal wire210′, as illustrated inFIG.2A.

FIG.3is a flow chart of a method of forming an integrated circuit device according to some embodiments of the inventive concept.FIGS.5through8are cross-sectional views illustrating a method of forming an integrated circuit device according to some embodiments of the inventive concept.

Referring toFIGS.3and5, the method may include forming first metal wires210(Block120) on a first insulating layer190that may include lower contacts160. The first metal wires210may be formed by depositing a first adhesion layer220and a first metal layer260and then patterning the first adhesion layer220and the first metal layer260. Each of the first adhesion layer220and the first metal layer260may be formed by, for example, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, and/or a plating process (e.g., an electroplating process). The first adhesion layer220and the first metal layer260may be patterned by an etch process (e.g., a dry etch process or a wet etch process).

The first metal wire210may include a lower surface210L facing and/or contacting the first insulating layer190and an upper surface210U opposite the lower surface210L. The lower surface210L of the first metal wire210may contact the lower contact160and may be electrically connected to the lower contact160.

Referring toFIGS.3and6, a second insulating layer290may be formed on the first metal wires210and the first insulating layer190(Block140). In some embodiments, a lower etch stop layer270may be formed before forming the second insulating layer290. The lower etch stop layer270may be conformally formed on underlying elements (e.g., the first metal wire210and the first insulating layer190) and may have a uniform thickness as illustrated inFIG.6. The second insulating layer290may include, for example, a flowable low dielectric material (e.g., SiCOH), and may be formed by a coating process (e.g., a spin coating process).

Openings290omay be formed in the second insulating layer290and the lower etch stop layer270. Each of the openings290omay extend through the second insulating layer290and the lower etch stop layer270. The openings290omay expose upper surfaces of the lower contacts160. The second insulating layer290may be formed to overlap the upper surfaces210U of the first metal wires210.

Referring toFIGS.3and7, second metal wires310may be formed in the second insulating layer290(Block160), specifically, in the openings290o, respectively. The second metal wires310may be formed by, for example, a damascene process.

In some embodiments, a second adhesion layer320and a first thin metal layer340may be sequentially formed on the second insulating layer290. Each of the second adhesion layer320and the first thin metal layer340may be formed conformally on underlying elements and may have a uniform thickness in the openings290oas illustrated inFIG.7. After that, a second metal layer360may be formed on the first thin metal layer340. Each of the second adhesion layer320, the first thin metal layer340, and the second metal layer360may be formed by, for example, a PVD process, an ALD process, a CVD process, and/or a plating process. After the second metal layer360is formed, a planarization process (e.g., a chemical-mechanical polishing (CMP) process or an etch process) may be performed until an upper surface of the second insulating layer290is exposed.

Referring toFIG.8, a first etch process may be performed to remove a portion of the second insulating layer290and a portion of the lower etch stop layer270. The first etch process may be performed until the upper surfaces210U of the first metal wires210are exposed. A second etch process may be performed to remove a portion of the second metal wire310. The second etch process may be performed until the upper surfaces310U of the second metal wires310are recessed toward the first insulating layer190relative to the upper surfaces210U of the first metal wires210. The first etch process and the second etch process may be sequentially performed or concurrently performed.

After performing the first etch process and the second etch process, an upper etch stop layer370may be formed on the first metal wires210, the second metal wires310, and the second insulating layer290. The upper etch stop layer370may be formed conformally on underlying elements and may have a uniform thickness as illustrated inFIG.8.

Referring toFIGS.1A and3, a third insulating layer390and an upper wire460may be formed on the first metal wires210and the second metal wires310(Block180). The upper wire460may be formed by, for example, a damascene process or an etch process.

FIG.4is a flow chart of a method of forming an integrated circuit device according to some embodiments of the inventive concept.FIGS.9through13are cross-sectional views illustrating a method of forming an integrated circuit device according to some embodiments of the inventive concept.

Referring toFIGS.4and9, the method may include forming tall first metal wires210′ on a first insulating layer190(Block120′) and then forming a mask layer265covering at least one of the tall first metal wires210′. The tall first metal wires210′ may be formed by processes similar to the processes of forming the first metal wires210discussed with reference toFIG.5. The mask layer265may include a material different from the first metal layer260and the first adhesion layer220to have an etch selectivity with respect to the first metal layer260and the first adhesion layer220. The mask layer265may include, for example, TiN or metal oxide.

Referring toFIGS.4and10, upper portions of tall first metal wires210′ that are not covered by the mask layer265may be removed (Block130), thereby forming first metal wires210. The upper portions of the tall first metal wires210′ may be removed by a dry etch process and/or a wet etch process.

Referring toFIGS.4and11, the mask layer265may be removed, and then a lower etch stop layer270and a second insulating layer290may be sequentially formed (Block140′) on the first metal wires210and the tall first metal wire210′. Openings290omay be formed in the second insulating layer290and the lower etch stop layer270. Each of the openings290omay extend through the second insulating layer290and the lower etch stop layer270.

Referring toFIGS.3and12, second metal wires310may be formed in the openings290o, respectively, by processes similar to the processes of forming the second metal wires310discussed with reference toFIG.7.

Referring toFIG.13, processes similar to the processes discussed with reference toFIG.8may be performed. A first etch process may be performed to remove a portion of the second insulating layer290and a portion of the lower etch stop layer270. The first etch process may be performed until the upper surface210′U of the tall first metal wire210′ is exposed. A second etch process may be performed to remove a portion of the second metal wire310. The second etch process may be performed until the upper surfaces310U of the second metal wires310become closer to the first insulating layer190than the upper surface210′U of the tall first metal wire210′. The first etch process and the second etch process may be sequentially performed or concurrently performed.

After performing the first etch process and the second etch process, an upper etch stop layer370may be formed on the first metal wires210, the second metal wires310, and second insulating layer290. The upper etch stop layer370may be formed conformally on underlying elements and may have a uniform thickness as illustrated inFIG.13.

Referring toFIGS.2A and3, an upper wire460may be formed on the first metal wires210and the second metal wires310(Block180). The upper wire460may be formed by, for example, a damascene process or an etch process.

Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

Example embodiments of the present inventive concept are described herein with reference to cross-sectional views or plan views that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present inventive concept should not be construed as limited to the particular shapes illustrated herein but include deviations in shapes that result, for example, from manufacturing.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.

It should be noted that in some alternate implementations, the functions/acts noted in flowchart blocks herein may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks that are illustrated, and/or blocks/operations may be omitted without departing from the scope of the present inventive concept.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.