Patent ID: 12205939

DETAILED DESCRIPTION

Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.

FIG.1Ais a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.FIG.1Bis a sectional view taken along a line I-I′ ofFIG.1A.FIG.1Cis an enlarged sectional view of a portion III ofFIG.1B.FIG.1Dis an enlarged sectional view of a portion IV ofFIG.1B.FIG.1Eis a sectional view taken along a line II-II′ ofFIG.1A.

Referring toFIGS.1A to1E, a semiconductor package11may include an interposer structure, solder terminals500, a first semiconductor chip610, and a chip stack60. The interposer structure may include a first redistribution layer110, first redistribution pads115, a second redistribution layer120, second redistribution pads125, a bridge structure200, a passive device300, and conductive structures350.

The first redistribution layer110may include a first insulating layer111, under-bump patterns117, and first redistribution patterns113. The first insulating layer111may be formed of or include at least one of organic materials (e.g., photosensitive polymers). In the present specification, the photosensitive polymer may include at least one of, for example, photo-sensitive polyimide, polybenzoxazole, phenol-based polymer, or benzocyclobutene-based polymer. The first insulating layer111may include a plurality of stacked layers. For example, as shown inFIG.1C, the first insulating layer111may include a first lower insulating layer111A and a first upper insulating layer111B. The first upper insulating layer111B may be disposed on, and in contact with, the first lower insulating layer111A. The first lower insulating layer111A and the first upper insulating layer111B may be provided to have no observable interface therebetween. The first lower insulating layer111A may be the lowermost layer of the first insulating layers111. The first upper insulating layer111B may be the uppermost layer of the first insulating layers111. The number of the stacked layers constituting the first insulating layers111may be variously changed. For example, an additional insulating layer may be further interposed between the first lower insulating layer111A and the first upper insulating layer111B.

The under-bump patterns117may be provided in the first lower insulating layer111A. Bottom surfaces of the under-bump patterns117may not be covered with the first lower insulating layer111A. The under-bump patterns117may serve as pads of the solder terminals500. The under-bump patterns117may be laterally spaced apart from each other and may be electrically disconnected from each other. Here, the expression “two elements are laterally spaced apart from each other” may mean that the elements are horizontally spaced apart from each other. Here, the term “horizontal or horizontally” is used to represent a direction or plane parallel to a bottom surface of the lowermost one of the first insulating layers111. For example, the direction or plane parallel to a bottom surface of the lowermost one of the first insulating layers111may be referred to as a “first direction.” The first lower insulating layer111A may cover top and side surfaces of the under-bump patterns117. The under-bump patterns117may be formed of or include at least one of metallic materials (e.g., copper).

The first redistribution patterns113may be provided on the under-bump patterns117, respectively. The first redistribution patterns113may be laterally spaced apart from each other and may be electrically separated from each other. Referring toFIG.1C, each of the first redistribution patterns113may include a first seed pattern1131and a first conductive pattern1133. The first conductive pattern1133may include two portions, one of which is provided on the top surface of the first lower insulating layer111A, and the other of which is provided in the first lower insulating layer111A. The first conductive pattern1133may include a first via portion1133V and a first wire portion1133W. The first via portion1133V may be disposed in the first lower insulating layer111A. The first via portion1133V may be disposed between the under-bump pattern117and the first wire portion1133W. The first wire portion1133W may be provided on the first via portion1133V and may be directly connected to the first via portion1133V. The first wire portion1133W may be extended to a region on the top surface of the first lower insulating layer111A and may have a long axis extending in the first direction. The first direction may be parallel to a bottom surface of the first lower insulating layer111A. The first wire portion1133W may have a width in the first direction that is larger than a width of the first via portion1133V in the first direction. The first conductive pattern1133may be formed of or include at least one of metallic materials (e.g., copper). In the present specification, the via portion may be an element for vertical interconnection, and the wire portion may be an element for horizontal interconnection. The term “vertical” is used to represent a direction or plane that it is perpendicular to the bottom surface of the lowermost one of the first insulating layers111. For example, the direction or plane that it is perpendicular to the bottom surface of the lowermost one of the first insulating layers111may be referred to as a “second direction.” The via portion may be an element for vertical interconnection in a second direction. The first upper insulating layer111B may cover the side and top surfaces of the first wire portion1133W, on the first lower insulating layer111A. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

The first seed pattern1131may be interposed between the under-bump pattern117and the first conductive pattern1133and between the first lower insulating layer111A and the first conductive pattern1133. The first seed pattern1131may cover bottom and side surfaces of the first via portion1133V and a bottom surface of the first wire portion1133W. The first seed pattern1131may not be extended to a region on a side surface of the first wire portion1133W. The first seed pattern1131may be formed of or include a material that is different from the under-bump pattern117and the first conductive pattern1133. For example, the first seed pattern1131may be formed of or include at least one conductive material (e.g., copper, titanium, and/or alloys thereof).

Although not illustrated in the drawings, lower redistribution patterns (not shown) may be further interposed between the under-bump patterns117and the first redistribution patterns113. The stacking number of the lower redistribution patterns may be variously changed.

The first redistribution layer110may have a first thickness T1. A thickness of an element may be a length of the element measured in a direction that is substantially perpendicular to a bottom surface of the element. For example, a thickness of an element may be a length of the element measured in the second direction. The thickness of the element may correspond to a distance between the bottom and top surfaces of the element. For example, the first thickness T1may correspond to a distance between the bottom surface of the lowermost one of the first insulating layers111and the top surface of the uppermost one of the first insulating layers111. The first thickness T1may have a value selected from a range between 10 μm and 30 μm.

The solder terminals500may be disposed on a bottom surface of the first redistribution layer110. For example, the solder terminals500may be disposed on the bottom surfaces of the under-bump patterns117, respectively, and may be directly coupled to the under-bump patterns117, respectively. The solder terminals500may be electrically connected to the first redistribution patterns113through the under-bump patterns117. The solder terminals500may be electrically disconnected from each other. The solder terminals500may be formed of or include at least one of varying soldering materials. For example, the soldering materials may include tin, bismuth, lead, silver, or alloys thereof. Since the first thickness T1is larger than or equal to 10 μm, the solder terminals500may be stably connected to the first redistribution layer110.

The first redistribution pads115may be disposed on the first upper insulating layer111B. The first redistribution pads115may be laterally spaced apart from each other. The first redistribution pads115may be disposed on and coupled to the first redistribution patterns113, respectively. As illustrated for example inFIG.1B, since the first redistribution patterns113are provided between the first redistribution pads115and the under-bump patterns117, at least one of the first redistribution pads115may not be vertically aligned to the under-bump pattern117that it is electrically connected thereto. Accordingly, the under-bump patterns117or the first redistribution pads115may be designed and disposed with an increased degree of freedom.

Each of the first redistribution pads115may include a first seed pad1151, a first pad pattern1153, and a first bonding pad1155, as shown inFIG.1C. A lower portion of the first pad pattern1153may be provided in the first upper insulating layer111B. An upper portion of the first pad pattern1153may be disposed on a top surface of the first upper insulating layer111B. The upper portion of the first pad pattern1153may have a larger width in the first direction than the lower portion thereof and may be connected to the lower portion thereof. The first pad pattern1153may be formed of or include at least one of metallic materials (e.g., copper). The first seed pad1151may be interposed between the first redistribution pattern113and the first pad pattern1153and between the first upper insulating layer111B and the first pad pattern1153. The first seed pad1151may be formed of or include at least one of conductive materials (e.g., copper, titanium, and/or alloys thereof). The first bonding pad1155may be disposed on the first pad pattern1153. The first bonding pad1155may be formed of or include a metallic material that is different from the first pad pattern1153. For example, the first bonding pad1155may be formed of or include at least one of other metallic materials, such as nickel, gold, and/or alloys thereof. The first bonding pad1155may serve as a protection layer or an adhesive layer.

Referring toFIGS.1B and1D, the bridge structure200may be disposed on the top surface of the first redistribution layer110. The top surface of the first redistribution layer110may correspond to a top surface of the uppermost one of the first insulating layers111. The bridge structure200may include a base substrate210, insulating patterns220, a connection structure250, and connection pads255. The bridge structure200may include integrated circuits, but the inventive concept is not limited to this example. The base substrate210may be a semiconductor substrate, such as a silicon wafer. As another example, the base substrate210may include an organic substrate. The organic substrate may be formed of or include an insulating polymer. The insulating patterns220may be vertically stacked on a top surface of the base substrate210. The insulating patterns220may be formed of or include at least one of silicon-based insulating materials or organic insulating materials. The silicon-based insulating materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, and/or combinations thereof. The organic insulating materials may include insulating polymers.

The connection pads255may be disposed in the uppermost of the insulating patterns220or on the uppermost of the insulating patterns220. The top surfaces of the connection pads255may not be covered with the uppermost of the insulating patterns220. The connection pads255may be laterally spaced apart from each other. The connection pads255may be formed of or include at least one of metallic materials (e.g., copper, aluminum, and/or tungsten). The connection structure250may be provided in the insulating patterns220and may be connected to at least two connection pads255. In an embodiment, a plurality of the connection structures250may be provided to be electrically disconnected from each other. Each of the connection structures250may include conductive vias and a conductive interconnection line. The conductive vias may be respectively interposed between the conductive interconnection line and the connection pads255. The expression “an element is coupled to the bridge structure200” may mean that the element is coupled to the connection structure250. The connection structure250may be formed of or include at least one of metallic materials (e.g., copper, titanium, and/or tungsten).

A height of the bridge structure200in the second direction may have a value selected from a range between 30 μm and 150 μm. A height of an element may correspond to a distance between the bottom and top surfaces of the element. For example, the height of the bridge structure200may be a distance between the bottom surface of the base substrate210and the top surfaces of the connection pads255.

A first adhesive film411may be interposed between the first redistribution layer110and the bridge structure200. The bridge structure200may be stably fastened to the first redistribution layer110by the first adhesive film411. The first adhesive film411may have an insulating property. The first adhesive film411may include a die attach film (DAF). A thickness of the first adhesive film411in the second direction may be smaller than the height of the bridge structure200. The thickness of the first adhesive film411may have a value selected from a range between 3 μm and 25 μm.

The passive device300(e.g., wire, resistor, capacitor, inductor, transformer, diode, etc.) may be disposed on a top surface of the first insulating layer111and may be laterally spaced apart from the bridge structure200. A height of the passive device300may have a value selected from a range between about 30 μm and 150 μm. Terminals315may be provided on a top surface of the passive device300. The terminals315may be formed of or include at least one of conductive materials (e.g., metallic materials).

A second adhesive film413may be interposed between the first redistribution layer110and the passive device300. The passive device300may be attached to the second redistribution layer120through the second adhesive film413. The second adhesive film413may have an insulating property. The second adhesive film413may be a die attach film. A thickness of the second adhesive film413in the second direction may be smaller than the height of the passive device300. The thickness of the second adhesive film413may have a value selected from a range between 3 μm and 25 μm.

The second redistribution layer120may be disposed on the bridge structure200, the passive device300, and the conductive structures350. The second redistribution layer120may be vertically spaced apart from the first redistribution layer110. The second redistribution layer120may include second insulating layers121and second redistribution patterns123. The second insulating layers121may be vertically stacked. However, adjacent ones of the second insulating layers121may be provided to have no observable interface therebetween. In an embodiment, the second insulating layer121may include a second lower insulating layer121A and a second upper insulating layer121B, as shown inFIG.1D. The second upper insulating layer121B may be disposed on the second lower insulating layer121A. The number of the staked second insulating layers121may be variously changed. For example, an additional insulating layer may be further interposed between the second lower insulating layer121A and the second upper insulating layer121B. The second insulating layers121may be formed of or include at least one of organic materials (e.g., photosensitive polymers).

The second redistribution patterns123may be spaced apart from each other and may be electrically disconnected from each other. Each of the second redistribution patterns123may include a second seed pattern1231and a second conductive pattern1233. The second conductive pattern1233may be disposed on the second seed pattern1231. The second conductive pattern1233may include a second via portion1233V and a second wire portion1233W. The second via portion1233V may be disposed in the second insulating layer121. The second wire portion1233W may be provided on the second via portion1233V and may be connected to the second via portion1233V without any interface therebetween. The second wire portion1233W may have a width or length in the first direction that is larger than a width of the second via portion1233V in the first direction. The second wire portion1233W may be extended to a region on a top surface of the second insulating layer121. The second conductive pattern1233may be formed of or include at least one of metallic materials (e.g., copper).

The second seed pattern1231may cover bottom and side surfaces of the second via portion1233V and a bottom surface of the second wire portion1233W. The second seed pattern1231may not be extended to a region on a side surface of the second wire portion1233W. The second seed pattern1231may be formed of or include a material that is different from the second conductive pattern1233. For example, the second seed pattern1231may be formed of or include at least one of metallic materials, such as copper, titanium, and/or alloys thereof.

The second upper insulating layer121B may be provided on the second lower insulating layer121A to cover the side and top surfaces of the second wire portion1233W. Although not illustrated in the drawings, upper redistribution patterns may be further provided on the second redistribution patterns123. The stacking number of the upper redistribution patterns may be variously changed.

The second redistribution layer120may have a second thickness T2in the second direction. The second thickness T2may correspond to a distance between a bottom surface of the lowermost one of the second insulating layers121and a top surface of the uppermost one of the second insulating layers121. Here, the lowermost one of the second insulating layers121may be the second lower insulating layer121A, and the uppermost one of the second insulating layers121may be the second upper insulating layer121B. The second thickness T2may be equal to or smaller than the first thickness T1. The second thickness T2may have a value selected from a range between 3 μm and 20 μm.

A distance A between the bottom surface of the first redistribution layer110and the top surface of the second redistribution layer120may have a value selected from a range between 60 μm and 300 μm. Since the distance A is larger than 60 μm, the passive device300and the bridge structure200may be interposed between the first redistribution layer110and the second redistribution layer120. Since the distance A is smaller than 300 μm, a length of an electric conduction path between the first semiconductor chip610and the solder terminals500may be reduced.

The second redistribution pads125may be disposed on the second upper insulating layer121B. The second redistribution pads125may be laterally spaced apart from each other. The second redistribution pads125may be disposed on and coupled to the second redistribution patterns123, respectively.

Each of the second redistribution pads125may include a second seed pad1251, a second pad pattern1253, and a second bonding pad1255. A lower portion of the second pad pattern1253may be provided in the second upper insulating layer121B. An upper portion of the second pad pattern1253may be disposed on a top surface of the second upper insulating layer121B. The upper portion of the second pad pattern1253may have a larger width than the lower portion thereof and may be connected to the lower portion thereof. The second pad pattern1253may be formed of or include at least one of metallic materials (e.g., copper). The second seed pad1251may be interposed between the second redistribution pattern123and the second pad pattern1253and between the second upper insulating layer121B and the second pad pattern1253. The second seed pad1251may be formed of or include at least one of conductive materials (e.g., copper, titanium, and/or alloys thereof). The second bonding pad1255may be disposed on the second pad pattern1253. The second bonding pad1255may be formed of or include a metallic material that is different from the second pad pattern1253. For example, the second bonding pad1255may be formed of or include at least one of nickel, gold, and/or alloys thereof. The second bonding pad1255may be used as a protection layer or an adhesive layer.

The first semiconductor chip610may be mounted on the top surface of the second redistribution layer120, as shown inFIG.1B. The first semiconductor chip610may be disposed on a center region of the second redistribution layer120, when viewed in a plan view. The first semiconductor chip610may include integrated circuits (not shown) and chip pads615. The integrated circuits of the first semiconductor chip610may be provided in the first semiconductor chip610. The chip pads615may be disposed on a bottom surface of the first semiconductor chip610and may be electrically connected to the integrated circuits. The expression “an element is coupled or connected to the chip pads615” may mean that the element is coupled or connected to the first semiconductor chip610. The first semiconductor chip610may be one of a logic chip, a buffer chip, and a system-on-chip (SOC). In an embodiment, the first semiconductor chip610may be an application specific integrated circuit (ASIC) chip or an application processor (AP) chip. The ASIC chip may include an application specific integrated circuit. In another embodiment, the first semiconductor chip610may include a central processing unit (CPU) or a graphic processing unit (GPU).

First bonding bumps510may be provided between the chip pads615of the first semiconductor chip610and the second redistribution pads125and may be coupled to the chip pads615and the second redistribution patterns123, respectively. Accordingly, the first semiconductor chip610may be coupled to the second redistribution patterns123through the first bonding bumps510. The expression “an element is coupled to the second redistribution layer120” may mean that the element is coupled or connected to at least one of the second redistribution patterns123. Each of the first bonding bumps510may include at least one of a solder ball, a solder pillar, and/or combinations thereof. The first bonding bumps510may be formed of or include at least one of soldering materials or copper.

The chip stack60may be mounted on the top surface of the second redistribution layer120. The chip stack60may be disposed on a top surface of an edge region of the second redistribution layer120. When viewed in a plan view, the edge region of the second redistribution layer120may be provided between a side surface and the center region of the second redistribution layer120. The edge region of the second redistribution layer120may enclose the center region. The chip stack60may be laterally spaced apart from the first semiconductor chip610. In an embodiment, a plurality of the chip stacks60may be provided, and in this case, the first semiconductor chip610may be disposed between the chip stacks60, when viewed in a plan view. The number of the chip stacks60may be variously changed. For example, the semiconductor package11may include just one chip stack60.

Each of the chip stacks60may include a plurality of second semiconductor chips620, which are sequentially stacked in the second direction. The second semiconductor chips620may include integrated circuits provided therein. The second semiconductor chips620may be of a different kind from the first semiconductor chip610. For example, the lowermost one of the second semiconductor chips620may be a logic chip, and the others may be memory chips. The memory chip may include a high bandwidth memory (HBM) chip. The lowermost one of the second semiconductor chips620may be a logic chip which is of a different kind from the first semiconductor chip610. As an example, the lowermost one of the second semiconductor chips620may be a controller chip which is configured to control memory chips. As another example, the lowermost one of the second semiconductor chips620may be a memory chip.

Each of the second semiconductor chips620may include lower pads625, penetration electrodes627, and upper pads626. The lower pads625and the upper pads626may be provided on bottom and top surfaces, respectively, of the second semiconductor chip620. The lower pads625and the upper pads626may be electrically connected to integrated circuits, which are provided in a corresponding one of the second semiconductor chips620. The penetration electrodes627may be disposed in a corresponding one of the second semiconductor chips620and may be coupled to the lower pads625and the upper pads626, respectively. The uppermost one of the second semiconductor chips620may include the lower pads625but may not include the penetration electrodes627and the upper pads626. A thickness of the uppermost one of the second semiconductor chips620in the second direction may be larger than the respective thickness of the remaining ones of the second semiconductor chips620in the second direction.

Each of the chip stacks60may further include interposer bumps550. The interposer bumps550may be interposed between two adjacent ones of the second semiconductor chips620and may be respectively coupled to the lower pads625and the upper pads626. Accordingly, the second semiconductor chips620may be electrically connected to each other. Each of the interposer bumps550may include at least one of a solder ball, a solder pillar, and/or combinations thereof. The interposer bumps550may be formed of or include at least one of soldering materials or copper, but the inventive concept is not limited to this example. As another example, the interposer bumps550may be omitted. In this case, the lower pads625and the upper pads626, which are respectively included in adjacent semiconductor chips and are placed to face each other, may be directly bonded to each other.

Each of the chip stacks60may further include upper under-fill layers433. The upper under-fill layers433may be respectively provided in third gap regions between the second semiconductor chips620to hermetically seal the interposer bumps550. The upper under-fill layer433may be formed of or include an insulating polymer (e.g., epoxy-based polymers).

Second bonding bumps520may be interposed between the lowermost one of the second semiconductor chips620and the second redistribution layer120and may be respectively coupled to corresponding ones of the lower pads625and the second redistribution pads125. Accordingly, the second semiconductor chips620may be coupled to the second redistribution patterns123. Each of the second bonding bumps520may include at least one of a solder ball, a solder pillar, and/or combinations thereof. The second bonding bumps520may be formed of or include at least one of soldering materials or copper, but the inventive concept is not limited to this example.

The semiconductor package11may further include a first under-fill layer431and second under-fill layers432. The first under-fill layer431may be provided in a first gap region between the second redistribution layer120and the first semiconductor chip610to hermetically seal the first bonding bumps510. The first under-fill layer431may be formed of or include an insulating polymer (e.g., epoxy-based polymers). The second under-fill layers432may be respectively provided in second gap regions between the second redistribution layer120and the chip stacks60to seal corresponding ones of the second bonding bumps520. The second under-fill layers432may be formed of or include an insulating polymer (e.g., epoxy-based polymers). Although not illustrated in the drawings, the second under-fill layers432may be omitted, and the first under-fill layer431may be extended into the second gap regions to seal the second bonding bumps520.

First pillar patterns280may be interposed between the bridge structure200and the second redistribution layer120and may be coupled to the connection pads255and the second redistribution patterns123, respectively. For example, the first pillar patterns280may be coupled to bottom surfaces of the second redistribution patterns123, respectively. The first pillar patterns280may be formed of or include at least one of metallic materials (e.g., copper, titanium, and/or alloys thereof). A pitch P10of the first pillar patterns280may be smaller than a pitch P3of the solder terminals500.

The bridge structure200may be overlapped with the first semiconductor chip610and one of the chip stacks60in the second direction, when viewed in a plan view. Each of the chip stacks60may be coupled to a corresponding one of the bridge structures200through the second redistribution layer120and the first pillar patterns280. The expression “an element is electrically connected to the chip stack60” may mean that the element is electrically connected to at least one of the second semiconductor chips620. The second semiconductor chips620may be coupled to the bridge structure200through the second redistribution layer120and the first pillar patterns280. The first semiconductor chip610and the second semiconductor chips620may be electrically connected to each other through the first redistribution pattern113and the connection structure250.

In the case where the bridge structure200is omitted, the first and second semiconductor chips610and620may be electrically connected to each other through the second redistribution layer120, and in this case, it may be necessary to increase the second thickness T2. According to an embodiment of the inventive concept, not only the second redistribution layer120but also the bridge structure200may be used as an electrical connection path between the first and second semiconductor chips610and620. Accordingly, the second thickness T2may be reduced. For example, the second thickness T2may have a value selected from a range between 3 μm and 20 μm.

Since the first pillar patterns280has a relatively small pitch (e.g., the pitch P10), it may be possible to increase an integration density of an electric connection structure between the first and second semiconductor chips610and620or to realize a dense electric connection structure between the first and second semiconductor chips610and620. For example, the pitch P10of the first pillar patterns280may be smaller than a pitch P20of second pillar patterns380, which will be described below, and a distance D between two adjacent ones of the conductive structures350.

In an embodiment, a plurality of the bridge structures200may be provided. The bridge structures200may be spaced apart from each other. At least two ones of the bridge structures200may have different sizes from each other, but the inventive concept is not limited to this example.

As shown inFIG.1E, the semiconductor package11may include a plurality of the first semiconductor chips610. The first semiconductor chips610may be spaced apart from each other. The first semiconductor chips610may be of the same kind. At least one of the bridge structures200may be vertically overlapped with the first semiconductor chips610. The bridge structure200may serve as an electric conduction path between the first semiconductor chips610. For example, the first semiconductor chips610may be electrically connected to each other through the first redistribution patterns113and the connection structure250. Although not illustrated in the drawings, the semiconductor package11may be configured to have just one first semiconductor chip610. Hereinafter, one of the first semiconductor chips610will be mentioned in the following description, for brevity's sake.

According to an embodiment of the inventive concept, since the passive device300is provided at a side of the bridge structure200, the semiconductor package11may have a reduced size and an increased integration density.

The second pillar patterns380may be provided between the passive device300and the second redistribution layer120and may be coupled to the terminals315and the second redistribution patterns123, respectively. For example, the second pillar patterns380may be coupled to the bottom surfaces of the second redistribution patterns123, respectively. The second pillar patterns380may be formed of or include at least one of metallic materials (e.g., copper, titanium, and/or alloys thereof). The pitch P20of the second pillar patterns380may be smaller than the pitch P3of the solder terminals500.

The passive device300may be electrically connected to the first semiconductor chip610through the second pillar patterns380and the second redistribution layer120. According to an embodiment of the inventive concept, since the passive device300is coupled to the first semiconductor chip610through the second redistribution layer120, it may be possible to reduce a length of an electrical conduction path between the passive device300and the first semiconductor chip610. The passive device300may be vertically overlapped with the first semiconductor chip610. Accordingly, the length of the electrical conduction path between the passive device300and the first semiconductor chip610may be further reduced, and this may make it possible to improve the electric characteristics of the semiconductor package11.

In the case where the passive device300is embedded in the first redistribution layer110, the second redistribution layer120, or the first semiconductor chip610, a process of fabricating the first redistribution layer110, the second redistribution layer120, or the first semiconductor chip610may become complex and difficult. By contrast, according to an embodiment of the inventive concept, since the passive device300is provided on the first redistribution layer110, it may be possible to simplify the process of fabricating the first redistribution layer110, the second redistribution layer120, or the first semiconductor chip610. In addition, it may be possible to increase a production yield in the process of fabricating the first redistribution layer110, the second redistribution layer120, or the first semiconductor chip610.

As shown inFIG.1A, the semiconductor package11may include a plurality of the passive devices300. The passive devices300may be laterally spaced apart from each other. The passive devices300may be vertically overlapped with the first semiconductor chip610and may be electrically connected to the first semiconductor chip610. The passive devices300may not be electrically connected to the second semiconductor chips620. Each of the passive devices300may not be overlapped with the second semiconductor chips620, when viewed in a plan view. The number of the passive devices300, which are vertically overlapped with the first semiconductor chip610, may be greater than the number of the passive devices300, which are vertically overlapped with the second semiconductor chips620. Here, the number of the passive devices300, which are vertically overlapped with the second semiconductor chips620, may be zero. The sizes of the passive devices300may be equal to or different from each other.

The conductive structures350may be interposed between the first redistribution layer110and the second redistribution layer120to electrically connect the first redistribution layer110and the second redistribution layer120to each other. The conductive structures350may be laterally spaced apart from the bridge structure200and the passive devices300. The conductive structures350may be laterally spaced apart from each other. The conductive structures350may be disposed on and coupled to the first redistribution pads115, respectively. For example, each of the conductive structures350may be in contact with the first bonding pad1155, as shown inFIG.1C. The conductive structures350may be electrically connected to the solder terminals500through the first redistribution layer110. The expression “an element is electrically connected to the first redistribution layer110” may mean that the element is electrically connected to at least one of the first redistribution patterns113. The conductive structures350may be formed of or include at least one of metallic materials (e.g., copper, tungsten, and/or alloys thereof).

The conductive structures350may include first conductive structures350S and second conductive structures350PG. The first conductive structures350S may be signal structures. The term “signal structure” may indicate a through structure that serves as a path along which data signals propagate and that is electrically connected to a signal source, such as a data, address, or command signal source. For example, the first conductive structures350S may be used to deliver data signals from the first or second semiconductor chips610or620to the solder terminals500.

The second conductive structures350PG may be spaced apart from and electrically disconnected from the first conductive structures350S. The second conductive structures350PG may include at least one of a ground/power structure and a serializer/deserializer (SerDes) structure. The ground/power structure may include at least one of a ground structure and a power structure. The term “ground/power structure” may indicate a through structure that serves as a path along which a ground or power voltage is provided and may be electrically connected to a ground or power source. For example, the second conductive structures350PG may be conduction paths, which are used to supply a ground voltage or a power voltage to the first or second semiconductor chips610or620. The term “SerDes structure” may indicate a through structure that serves as an electric connection path between a pair of blocks that convert data between serial data and parallel interfaces. One of the pair of blocks may be provided in the first semiconductor chip610or second semiconductor chip620.

A width W2of the second conductive structures350PG may be larger than a width W1of the first conductive structures350S. For example, the width W2of the second conductive structures350PG may be 120% to 300% of the width W1of the first conductive structures350S. Since the width W2of the second conductive structures350PG is larger than or equal to 120% of the width W1of the first conductive structures350S, the second conductive structures350PG may be used to deliver a larger amount of current than the first conductive structures350S. Thus, the electric characteristics of the semiconductor package11may be improved. Since the width W1of the first conductive structures350S is smaller than the width W2of the second conductive structures350PG, it may be possible to reduce a size of the semiconductor package11and to increase the number of the first conductive structures350S disposed on the first redistribution layer110. Thus, it may be possible to improve a data signal transmission property of the first or second semiconductor chips610or620. For example, given an increase in the number of the first conductive structures350S, a data signal of the first or second semiconductor chips610or620may be transmitted to an external device through the first conductive structures350S at a faster speed.

Some of the first bonding bumps510may be arranged at a first pitch P1and others may be arranged at a second pitch P2. The first bonding bumps510, which are arranged at the first pitch P1, may be coupled to the bridge structures200. The first bonding bumps510, which are arranged at the second pitch P2, may be coupled to the conductive structures350or the passive device300. The first pitch P1may be smaller than the second pitch P2. Accordingly, it may be possible to increase an integration density of an electric connection structure between the first and second semiconductor chips610and620or between the first semiconductor chips610or to realize a dense electric connection structure. However, in an embodiment, the first pitch P1may be equal to or larger than the second pitch P2.

A lower mold layer410may be provided between the first redistribution layer110and the second redistribution layer120to fill a gap region between the first redistribution layer110and the second redistribution layer120. The lower mold layer410may cover the side and top surfaces of the bridge structure200, the side and top surfaces of the passive device300, and the side surfaces of the conductive structures350. The lower mold layer410may be extended into a gap region between the bridge structure200and the second redistribution layer120to seal the first pillar patterns280. The lower mold layer410may be extended into a gap region between the passive device300and the second redistribution layer120to seal the second pillar patterns380. The lower mold layer410may be formed of or include at least one of insulating polymers (e.g., epoxy molding compound). The lower mold layer410may be formed of or include a material that is different from the first adhesive film411and the second adhesive film413.

A top surface of the lower mold layer410may be located at substantially the same level in the second direction as top surfaces of the first pillar patterns280, the second pillar patterns380, and the conductive structures350. Accordingly, the second redistribution layer120may be easily formed on the lower mold layer410, and the second redistribution patterns123may be well coupled to the first pillar patterns280, the second pillar patterns380, and the conductive structures350. If elements are described to have the same level, thickness, width, or length, the elements may be formed to have levels, thicknesses, widths, or lengths within a specific process tolerance. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes. In the present specification, the term ‘level’ may mean a level in the vertical direction (i.e., the second direction), and the term ‘level difference or different between two levels’ may be a distance between the two levels, which are measured in a direction perpendicular to the bottom surface of the first redistribution layer110. Outer side surfaces of the lower mold layer410may be aligned to outer side surfaces of the first redistribution layer110and outer side surfaces of the second redistribution layer120.

According to an embodiment of the inventive concept, the semiconductor package11may further include an upper mold layer420. The upper mold layer420may be disposed on the top surface of the second redistribution layer120to cover a side surface of the first semiconductor chip610and side surfaces of the second semiconductor chips620. The upper mold layer420may further cover a top surface of the first semiconductor chip610and a top surface of the uppermost one of the second semiconductor chips620. In an embodiment, the upper mold layer420may not cover the top surface of the first semiconductor chip610and the top surface of the uppermost one of the second semiconductor chips620. As another example, the first under-fill layer431and the second under-fill layers432may be omitted, and the upper mold layer420may be extended into the first gap region between the second redistribution layer120and the first semiconductor chip610and the second gap regions between the second redistribution layer120and the chip stacks60.

Outer side surfaces of the upper mold layer420may be aligned to the outer side surfaces of the first redistribution layer110, the outer side surfaces of the lower mold layer410, and the outer side surfaces of the second redistribution layer120.

Although not illustrated in the drawings, the semiconductor package may further include an upper passive device. The upper passive device may be provided in the second redistribution layer120. For example, the upper passive device may be interposed between a corresponding one of the second redistribution patterns123and a corresponding one of the second redistribution pads125. At least one of the solder terminals500may be electrically connected to the first semiconductor chip610through the upper passive device. Alternatively, the first semiconductor chip610may be electrically connected to the passive device300or the bridge structure200through the upper passive device.

FIG.2Ais a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.FIG.2Bis a sectional view taken along a line I-I′ ofFIG.2A.FIG.2Cis an enlarged sectional view of a portion V ofFIG.2B.FIG.2Dis a sectional view taken along a line II-II′ ofFIG.2A. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.

Referring toFIGS.2A,2B,2C, and2D, a semiconductor package12may include the solder terminals500, the interposer structure, the first semiconductor chip610, and the chip stacks60. The interposer structure may include the first redistribution layer110, the first redistribution pads115, the second redistribution layer120, the second redistribution pads125, the bridge structures200, the passive device300, the second adhesive film413, and the conductive structures350. The interposer structure may have substantially the same structure as that described with reference toFIGS.1A to1E. However, the first adhesive film411ofFIG.1Bmay not be provided in the interposer structure in the present embodiment.

Each of the bridge structures200may further include metal patterns260, penetration structures270, and lower connection pads275, in addition to the base substrate210, the insulating patterns220, the connection structure250, and the connection pads255, as shown inFIG.2C. The lower connection pads275may be provided on the bottom surface of the base substrate210. The lower connection pads275may be disposed on an edge region of the bottom surface of the base substrate210. The lower connection pads275may be formed of or include at least one of metallic materials (e.g., copper, aluminum, gold, or nickel).

The penetration structures270may be provided in the base substrate210. The penetration structures270may be disposed on and coupled to the lower connection pads275. In an embodiment, the penetration structures270may be further extended into at least one of the insulating patterns220. The penetration structures270may be formed of or include at least one of conductive materials (e.g., copper, titanium, tungsten, and/or alloys thereof).

The metal patterns260may be provided in or interposed between the insulating patterns220. The metal patterns260may be connected to the connection pads255and the penetration structures270, respectively. The metal patterns260may include a metal via and a metal line. The metal via may be provided to penetrate at least one of the insulating patterns220. The metal line may be interposed between the insulating patterns220. The connection structure250may be disposed between the metal patterns260and may be electrically disconnected from the metal patterns260. Since the metal patterns260are provided, at least one of the penetration structures270may not be aligned in the second direction to the connection pad255that is electrically connected thereto. Accordingly, it may be possible to alleviate technical restrictions on the disposition of the lower connection pads275and the connection pads255. As another example, the metal patterns260may be omitted, and the penetration structures270may be directly coupled to respective corresponding ones of the connection pads255and the lower connection pads275.

First solder patterns580may be respectively interposed between corresponding pairs of the lower connection pads275of the bridge structure200and the first redistribution pads115disposed on the first redistribution layer110. The lower connection pads275may be coupled to the first redistribution layer110through the first solder patterns580. Accordingly, the first semiconductor chip610and the second semiconductor chips620may be electrically connected to the first redistribution layer110through the penetration structures270. In other words, the penetration structures270may be used as electric conduction paths between the first semiconductor chip610and the first redistribution layer110or between the second semiconductor chip620and the first redistribution layer110. The first solder patterns580may include solder balls. The first solder patterns580may be formed of or include at least one of soldering materials.

A first distance A1between the first redistribution layer110and the bridge structure200may have a value selected from a range between 20 μm and 50 μm. The first distance A1may be a distance between the top surface of the uppermost one of the first insulating layers111and the bottom surface of the base substrate210. The first distance A1may be larger than a thickness of the second adhesive film413in the second direction.

As shown inFIG.2B, the height of the bridge structure200may be smaller than the height of the passive device300. A height of a first passive device301may have a value selected from a range between 300 μm and 150 μm. The height of the bridge structure200may have a value selected from a range between 30 μm and 150 μm but may be smaller than the height of the passive device300.

The bridge structures200may have substantially the same size as each other. For example, the bridge structures200may have the same width.

The semiconductor package12may include an under-fill layer430. The under-fill layer430may be provided in the first gap region between the second redistribution layer120and the first semiconductor chip610and may be extended into the second gap regions between the second redistribution layer120and the chip stacks60. For example, the under-fill layer430may be provided to seal or encapsulate the first bonding bumps510and the second bonding bumps520. The under-fill layer430may be formed of or include an insulating polymer (e.g., epoxy-based polymers).

The upper mold layer420may cover the side surface of the first semiconductor chip610and the side surfaces of the second semiconductor chips620. Although not illustrated, the upper mold layer420may be extended to cover the top surface of the first semiconductor chip610and the top surface of the uppermost one of the second semiconductor chips620.

The semiconductor package12may further include a heat-dissipation structure999. The heat-dissipation structure999may be disposed on the top surface of the first semiconductor chip610, the top surfaces of the chip stacks60, and the top surface of the upper mold layer420. Although not illustrated, the heat-dissipation structure999may be extended to a region on the side surface of the upper mold layer420. The heat-dissipation structure999may be formed of or include a material having high thermal conductivity, and in this case, the heat-dissipation structure999may be used as a heat sink, a heat slug, or a heat spreader. For example, heat, which is produced from the first or second semiconductor chips610or620during operations of the semiconductor package12, may be quickly dissipated to the outside through the heat-dissipation structure999. The heat-dissipation structure999may be formed of or include at least one of metallic materials (e.g., copper). In addition, the heat-dissipation structure999may be configured to absorb physical impact from the outside and thereby to protect the first semiconductor chip610and the chip stacks60from the physical impact.

The heat-dissipation structure999may have an electrically conductive property, and in this case, the heat-dissipation structure999may also be used as an electromagnetic wave shielding layer. For example, the heat-dissipation structure999may be used to prevent an electromagnetic interference (EMI) issue from occurring between the first semiconductor chip610and the second semiconductor chips620. In this case, the heat-dissipation structure999may be grounded through the second redistribution layer120to prevent the first or second semiconductor chips610or620from being electrically damaged by an electrostatic discharge (ESD) phenomenon.

FIG.3Ais a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.FIG.3Bis a sectional view taken along a line I-I′ ofFIG.3A.

Referring toFIGS.3A and3B, a semiconductor package13may include the interposer structure, the solder terminals500, the first semiconductor chip610, and the chip stacks60. The interposer structure may include the first redistribution layer110, the first redistribution pads115, the second redistribution layer120, the second redistribution pads125, the bridge structures200, the passive devices300, and the conductive structures350.

The passive devices300may include first passive devices301and second passive devices302. The first passive devices301may be overlapped in the second direction with the first semiconductor chips610, when viewed in a plan view. The first passive devices301may be coupled to the first semiconductor chips610. The second passive devices302may be overlapped in the second direction with the chip stack60, when viewed in a plan view. For example, the second passive devices302may be vertically overlapped in the second direction with the second semiconductor chips620. The second passive devices302may be electrically coupled to the second semiconductor chips620, but the inventive concept is not limited to this example. The number of first passive devices301may be more than the number of second passive devices302. Since each of the first semiconductor chips610is electrically connected to a large number of the first passive devices301, the operation of the first semiconductor chip610may be performed in a reliable manner. Accordingly, the electric characteristics of the semiconductor package13may be improved.

FIG.4Ais a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

Referring toFIG.4A, a semiconductor package14may include the interposer structure, the solder terminals500, the first semiconductor chip610, and the chip stacks60. The interposer structure may include the first redistribution layer110, the first redistribution pads115, the second redistribution layer120, the second redistribution pads125, the bridge structures200, at least one passive device300, the conductive structures350, and an electronic device700.

The electronic device700may be disposed on the top surface of the first redistribution layer110and may be laterally spaced apart from the bridge structures200and the passive device300. The electronic device700may be an active device. For example, the electronic device700may be a semiconductor chip. As an example, the electronic device700may be an input/output chip (I/O chip) or a power management chip. The power management chip may include a power management integrated circuit (PMIC). As another example, the electronic device700may be a chiplet. The chiplet may include a plurality of IP blocks, which are configured to realize different functions. Each of the IP blocks may include integrated circuits. The electronic device700may have conductive pads715. The conductive pads715may be provided on a top surface of the electronic device700. The conductive pads715may be formed of or include at least one of metallic materials (e.g., copper, nickel, gold, and/or aluminum).

The semiconductor package14may include third pillar patterns780. The third pillar patterns780may be provided between the electronic device700and the second redistribution layer120. The third pillar patterns780may be disposed on the conductive pads715, respectively and may be coupled to integrated circuits in the electronic device700. The third pillar patterns780may be coupled to the bottom surfaces of the second redistribution patterns123, respectively. The third pillar patterns780may be formed of or include at least one of metallic materials (e.g., copper, titanium, and/or alloys thereof). A pitch P30of the third pillar patterns780may be smaller than the pitch P3of the solder terminals500.

The semiconductor package14may include a third adhesive film417. The third adhesive film417may be interposed between the electronic device700and the bridge structure200. The electronic device700may be attached to the first redistribution layer110using the third adhesive film417. The third adhesive film417may have an insulating property. The third adhesive film417may include a die attach film. A thickness of the third adhesive film417may have a value selected from a range between 3 μm and 25 μm. The thickness of the third adhesive film417may be smaller than a height of the electronic device700. The height of the electronic device700may have a value selected from a range between 30 μm and 150 μm.

FIG.4Bis a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

Referring toFIG.4B, a semiconductor package15may include the interposer structure, the solder terminals500, the first semiconductor chip610, and the chip stack60. The interposer structure may include the first redistribution layer110, the first redistribution pads115, the second redistribution layer120, the second redistribution pads125, the bridge structures200, the passive device300, the conductive structures350, the first to third pillar patterns280,380, and780, the first solder patterns580, and the electronic device700. The semiconductor package15may not include the third adhesive film417described with reference toFIG.4A.

The electronic device700may include the conductive pads715, penetration vias750, and lower conductive pads725. The conductive pads715may be provided on a top surface of the electronic device700and may be coupled to the second redistribution layer120through the third pillar patterns780. The lower conductive pads725may be provided on a bottom surface of the electronic device700. The lower conductive pads725may be formed of or include at least one of metallic materials (e.g., copper, nickel, gold, and/or aluminum). The penetration vias750may be provided in the electronic device700to penetrate at least a portion of the electronic device700. The penetration vias750may be coupled to the conductive pads715and the lower conductive pads725, respectively. The penetration vias750may be electrically connected to integrated circuits (not shown) of the electronic device700. The penetration vias750may be formed of or include at least one of conductive materials (e.g., copper, titanium, tungsten, and/or alloys thereof).

The semiconductor package15may include second solder patterns570. Each of the second solder patterns570may be interposed between a corresponding pair of the lower conductive pads725and the first redistribution pads115. The lower conductive pads725may be coupled to the first redistribution layer110through the second solder patterns570. The electronic device700may be electrically connected to the first redistribution pattern113through the second solder patterns570. The first or second semiconductor chips610or620may be electrically connected to the first redistribution pattern113through the second redistribution layer120and the penetration structures270. The second solder patterns570may include solder balls. The second solder patterns570may be formed of or include at least one of solder materials.

The afore-described embodiments may be combined to realize the inventive concept. For example, at least two of the embodiments for the semiconductor package11ofFIGS.1A to1E, the semiconductor package12ofFIGS.2A to2D, the semiconductor package13ofFIGS.3A and3B, the semiconductor package14ofFIG.4A, and the semiconductor package15ofFIG.4Bmay be realized in a combined or mixed manner.

FIG.4Cis a sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. For concise description, a previously described element may be identified by the same reference number without repeating an overlapping description thereof.

Referring toFIG.4C, a semiconductor package16may include the interposer structure, the solder terminals500, the first semiconductor chip610, and the chip stack60. The interposer structure may include the first redistribution layer110, the first redistribution pads115, the second redistribution layer120, the second redistribution pads125, the bridge structures200, the passive device300, the conductive structures350, first and second pillar patterns280,380, the lower mold layer410, a third redistribution layer130, lower conductive structures351, the lower passive device300L, a lower electronic device700L, and a molding pattern440.

The lower passive device300L may be disposed on the top surface of the first redistribution layer110. The lower passive device300L may include the lower terminals315L, which are provided on a top surface thereof.

The lower electronic device700L may be disposed on the top surface of the first redistribution layer110and may be laterally spaced apart from the lower passive device300L. The lower electronic device700L may include an active device, a semiconductor chip, or a chiplet. For example, the electronic device700may be an input/output (I/O) chip or a power management chip. The lower electronic device700L may have lower pads715L, which are provided on a top surface thereof. The lower pads715L may be formed of or include at least one of metallic materials.

The interposer structure may further include at least one of a first lower adhesive film413L and a second lower adhesive film417L. The first lower adhesive film413L may be interposed between the first redistribution layer110and the lower passive device300L. The lower passive device300L may be fastened to the first redistribution layer110by the first lower adhesive film413L. The second lower adhesive film417L may be interposed between the first redistribution layer110the lower electronic device700L. The first lower adhesive film413L and the second lower adhesive film417L may have an insulating property and may include die attach films.

The molding pattern440may be disposed on the first redistribution layer110to cover the lower passive device300L and the lower electronic device700L. The molding pattern440may be formed of or include at least one of epoxy-based insulating materials.

The third redistribution layer130may be disposed on the molding pattern440. The third redistribution layer130may be interposed between the first redistribution layer110and the second redistribution layer120. The third redistribution layer130may include third insulating layers131and third redistribution patterns133. The third insulating layers131may be vertically stacked on top of another. Adjacent ones of the third insulating layers131may be provided to have no observable interface therebetween. The third insulating layers131may be formed of or include at least one of organic materials (e.g., photosensitive polymers).

The third redistribution patterns133may be provided in the third insulating layers131or on the third insulating layers131. Each of the third redistribution patterns133may include a third seed pattern and a third conductive pattern. The third conductive pattern and the third seed pattern may be configured to have substantially the same features as the first conductive pattern1133and the first seed pattern1131, respectively, which were previously described with reference toFIGS.1B and1C. The expression “an element is electrically connected to the third redistribution layer130” may mean that the element is electrically connected to at least one of the third redistribution patterns133.

The interposer structure may further include third redistribution pads135. The third redistribution pads135may be interposed between the third redistribution layer130and the conductive structures350. The conductive structures350may be coupled to the third redistribution patterns133through the third redistribution pads135.

The bridge structure200and the passive device300may be disposed on the third redistribution layer130. The first adhesive film411may be interposed between the third redistribution layer130and the bridge structure200. The second adhesive film413may be interposed between the third redistribution layer130and the passive device300.

The lower conductive structures351may be interposed between the first redistribution layer110and the third redistribution layer130and may be coupled to the first redistribution layer110and the third redistribution layer130. The lower conductive structures351may be laterally spaced apart from the lower passive device300L and lower electronic devices700L. The lower conductive structures351may be disposed on and coupled to the first redistribution pads115, respectively. Top surfaces of the lower conductive structures351may be coupled to the third redistribution patterns133, respectively.

The lower conductive structures351may include the first lower conductive structures351S and second lower conductive structures351PG. The first lower conductive structures351S may be signal structures.

The second lower conductive structures351PG may be spaced apart from and disconnected from the first lower conductive structures351S. The second lower conductive structures351PG may include at least one of the ground/power structure and the SerDes structure. A width of the second lower conductive structures351PG in the first direction may be larger than a width of the first lower conductive structures351S in the first direction. For example, the width of the second lower conductive structures351PG may be 120% to 300% of the width of the first lower conductive structures351S.

The interposer structure may further include first lower pillar patterns380L. The first lower pillar patterns380L may be provided between the lower passive device300L and the second redistribution layer120. The first lower pillar patterns380L may be respectively disposed on the lower terminals315L to be coupled to the lower passive device300L. The first lower pillar patterns380L may be coupled to bottom surfaces of the third redistribution patterns133, respectively. A pitch of the first lower pillar patterns380L may be smaller than a pitch of the solder terminals500.

The first semiconductor chip610may be electrically connected to the lower passive device300L through the second redistribution layer120, the second conductive structures350PG, and the third redistribution layer130.

The interposer structure may further include second lower pillar patterns780L. The second lower pillar patterns780L may be provided between the lower electronic device700L and the third redistribution layer130. The second lower pillar patterns780L may be coupled to the lower pads715L and the third redistribution patterns133. The second lower pillar patterns780L may be formed of or include at least one of metallic materials. A pitch of the second lower pillar patterns780L may be smaller than the pitch of the solder terminals500.

The first semiconductor chip610may be electrically connected to the lower electronic device700L through the second redistribution layer120, the first conductive structures350S, and the third redistribution layer130.

In an embodiment, although not illustrated, at least one of the lower passive device300L and the lower electronic device700L may be omitted.

FIGS.5A to5Hare sectional views, which are taken along the line I-I′ ofFIG.1Ato illustrate a method of fabricating a semiconductor package according to an embodiment of the inventive concept.

Referring toFIG.5A, the first redistribution layer110may be formed on a first carrier substrate990. In addition, a carrier adhesive layer980may be interposed between the first carrier substrate990and the first redistribution layer110. The carrier adhesive layer980may attach the first redistribution layer110to the first carrier substrate990. The carrier adhesive layer980may be a release layer. The formation of the first redistribution layer110may be performed in a wafer- or panel-level.

The formation of the first redistribution pattern113may include forming the under-bump patterns117, forming the first lower insulating layer111A on the under-bump patterns117, forming an opening119in the first lower insulating layer111A, forming a seed layer in the opening119and the top surface of the first lower insulating layer111A, forming a resist pattern having a guide opening on the seed layer, performing an electroplating process using a seed layer as an electrode, removing the resist pattern to expose a portion of the seed layer, etching the exposed portion of the seed layer, and forming the first upper insulating layer111B.

The opening119may be formed to expose a corresponding one of the under-bump patterns117. The guide opening may be connected to the opening119. As a result of the electroplating process, the first conductive pattern1133may be formed in the opening119. The first conductive pattern1133may be formed to fill a lower portion of the guide opening. As a result of the etching of the seed layer, the first seed pattern1131may be formed. Accordingly, the first redistribution layer110including the first insulating layer111, the under-bump patterns117, and the first redistribution patterns113may be formed. The first insulating layer111may include the first lower insulating layer111A and the first upper insulating layer111B. Each of the first redistribution patterns113may include the first seed pattern1131and the first conductive pattern1133. The first upper insulating layer111B may cover the first redistribution patterns113, on the first lower insulating layer111A.

The first redistribution pads115may be formed on and coupled to the first redistribution patterns113, respectively.

Referring toFIG.5B, the conductive structures350may be formed on and coupled to the first redistribution pads115, respectively. The conductive structures350may include the first conductive structures350S and the second conductive structures350PG. The width W1of the first conductive structures350S may be smaller than the width W2of the second conductive structures350PG.

Referring toFIG.5C, the bridge structures200and the passive device300may be disposed on the first redistribution layer110. The disposing of the bridge structures200may include attaching the bridge structures200to the first redistribution layer110using a plurality of first adhesive films411. The disposing of the passive device300may include attaching the passive device300to the first redistribution layer110using the second adhesive film413.

The first pillar patterns280may be formed on the connection pads255of the bridge structures200, respectively. The formation of the first pillar patterns280may be performed before or after disposing the bridge structures200on the first redistribution layer110.

The second pillar patterns380may be formed on the terminals315of the passive device300, respectively. The formation of the second pillar patterns380may be performed before or after disposing the passive device300on the first redistribution layer110.

Referring toFIG.5D, a preliminary mold layer410P may be formed on the top surface of the first redistribution layer110to cover the conductive structures350, the bridge structures200, the passive device300, the first pillar patterns280, and the second pillar patterns380. For example, a top surface of the preliminary mold layer410P may be located at a level that is higher than the top surfaces of the conductive structures350, the first pillar patterns280, and the second pillar patterns380.

Referring toFIG.5E, a thinning process may be performed on the preliminary mold layer410P to form the lower mold layer410. The thinning process may be performed using a chemical mechanical polishing (CMP) technology. The thinning process may be performed until the conductive structures350, the first pillar patterns280, and the second pillar patterns380are exposed to the outside. The conductive structures350, the first pillar patterns280, and the second pillar patterns380may be additionally polished during the thinning process. As a result of the thinning process, a top surface410aof the lower mold layer410may be formed at substantially the same level as the top surfaces of the conductive structures350, the top surfaces of the first pillar patterns280, and the top surfaces of the second pillar patterns380.

Referring toFIG.5F, the second redistribution layer120may be formed on the top surface410aof the lower mold layer410. The formation of the second redistribution layer120may include forming the second insulating layers121and forming the second redistribution patterns123. The second insulating layers121and the second redistribution patterns123may be substantially the same as those in the previous embodiment ofFIG.1D. According to an embodiment of the inventive concept, since the top surface410aof the lower mold layer410is located at substantially the same level as the top surfaces of the conductive structures350, the first pillar patterns280, and the second pillar patterns380, the second redistribution layer120may be formed in a desired shape. For example, it may be possible to prevent the second redistribution patterns123from being formed in an undulating shape.

The second redistribution pads125may be formed on and coupled to the second redistribution patterns123, respectively.

Referring toFIG.5G, the first semiconductor chip610and the chip stacks60may be mounted on the second redistribution layer120. The mounting of the first semiconductor chip610may include forming the first bonding bumps510between the chip pads615of the first semiconductor chip610and the corresponding second redistribution pads125. Each of the chip stacks60may include the second semiconductor chips620, the interposer bumps550, and the upper under-fill layers433, which are stacked. The mounting of the chip stacks60may include forming the second bonding bumps520between the lower pads625of the lowermost one of the second semiconductor chips620and the corresponding second redistribution pads125.

The first under-fill layer431may be formed between the second redistribution layer120and the first semiconductor chip610. The second under-fill layers432may be respectively formed between the second redistribution layer120and the chip stacks60. The upper mold layer420may be formed on the second redistribution layer120to cover the first semiconductor chip610and the second semiconductor chips620. A second carrier substrate992may be attached to the top surface of the upper mold layer420.

Referring toFIG.5H, the first carrier substrate990and the carrier adhesive layer980may be removed to expose the bottom surface of the first redistribution layer110. For example, the bottom surface of the lowermost one of the first insulating layers111and the bottom surfaces of the under-bump patterns117may be exposed to the outside.

Referring back toFIG.1B, the solder terminals500may be respectively formed on the bottom surfaces of the under-bump patterns117and thus may be coupled to the under-bump patterns117, respectively. The formation of the solder terminals500may include performing a solder ball attaching process. Thereafter, the second carrier substrate992may be removed. The semiconductor package11may be fabricated through the afore-described process.

FIG.6is a diagram illustrating a process of connecting a bridge structure to a first redistribution layer, according to an embodiment of the inventive concept.

Referring toFIG.6, the first redistribution layer110, the first redistribution pads115, and the conductive structures350may be formed on the first carrier substrate990. The carrier adhesive layer980may be further formed between the first carrier substrate990and the first redistribution layer110. The first redistribution layer110and the first redistribution pads115may be formed in the same manner as the previous embodiment described with reference toFIG.5A. The conductive structures350may be formed in the same manner as the previous embodiment described with reference toFIG.5B.

The bridge structures200may be prepared. Each of the bridge structures200may include the base substrate210, the insulating patterns220, the connection structure250, the connection pads255, the metal patterns260, the penetration structures270, and the lower connection pads275.

The bridge structures200may be connected to the first redistribution layer110. The connecting of the bridge structures200to the first redistribution layer110may include forming the first solder patterns580between the first redistribution pads115and the lower connection pads275. A reflow process on the first solder patterns580may be performed to connect the first solder patterns580to the first redistribution pads115and the lower connection pads275, respectively. Accordingly, the penetration structures270may be electrically connected to the first redistribution layer110.

The disposing of the passive device300may be performed before or after disposing the bridge structures200. The disposing of the passive device300may be performed using the second adhesive film413.

The first pillar patterns280may be formed on the connection pads255of the bridge structures200. The second pillar patterns380may be formed on the terminals315of the passive device300.

Referring toFIGS.6and2B, the lower mold layer410and the second redistribution layer120may be formed on the first redistribution layer110, and the first semiconductor chip610and the chip stacks60may be mounted on the second redistribution layer120. The under-fill layer430and the upper mold layer420may be formed on the second redistribution layer120, and the heat-dissipation structure999may be formed on the upper mold layer420. Thereafter, the first carrier substrate990and the carrier adhesive layer980may be removed, and the solder terminals500may be formed on the bottom surfaces of the under-bump patterns117, respectively. The semiconductor package12may be fabricated through the afore-described process.

FIG.7is a sectional view illustrating a stack-type semiconductor package according to an embodiment of the inventive concept.

Referring toFIG.7, a stack-type semiconductor package1may include outer terminals950, a package substrate900, and the semiconductor package11. The package substrate900may be a printed circuit board (PCB) with a circuit pattern. The package substrate900may include an insulating base layer910, substrate pads920, and internal lines930. The insulating base layer910may include a plurality of stacked layers. As another example, the insulating base layer910may be a single layer. The substrate pads920may be provided on a top surface of the insulating base layer910. The internal lines930may be provided in the insulating base layer910and may be coupled to the substrate pads920, respectively. The expression “an element is coupled or connected to the package substrate900” may mean that the element is coupled or connected to at least one of the internal lines930. The substrate pads920and the internal lines930may be formed of or include at least one of metallic materials (e.g., copper, aluminum, tungsten, and/or titanium).

The outer terminals950may be disposed on a bottom surface of the package substrate900. External electrical signals may be transmitted to and from the package substrate900through the outer terminals950. The outer terminals950may include solder balls, solder pillars, solder bumps, or combinations thereof. The outer terminals950may be formed of or include at least one of metallic materials, such as soldering materials.

The semiconductor package11may include the solder terminals500, the interposer structure, the first semiconductor chip610, the chip stack60, and the upper mold layer420. The interposer structure may include the first redistribution layer110, the first redistribution pads115, the second redistribution layer120, the second redistribution pads125, the bridge structure200, the passive device300, and the conductive structures350.

The semiconductor package11described with reference toFIGS.1A to1Emay be mounted on the package substrate900. The mounting of the semiconductor package11on the package substrate900may include coupling the solder terminals500to the substrate pads920, respectively. Although not illustrated in the drawings, the semiconductor package12ofFIGS.2A to2D, the semiconductor package13ofFIGS.3A and3B, the semiconductor package14ofFIG.4A, or the semiconductor package15ofFIG.4Bmay be mounted on the package substrate900.

According to an embodiment of the inventive concept, a passive device and a bridge structure may be interposed between first and second redistribution layers, and this may make it possible to realize a highly integrated and small size semiconductor package. A first semiconductor chip and chip stacks may be electrically connected to each other through the bridge structure, and thus, a thickness of the second redistribution layer may be reduced. Accordingly, it may be possible to reduce a size of a semiconductor package. The passive device may be electrically connected to a first semiconductor chip through a second redistribution layer, and in this case, a length of an electrical conduction path between the passive device and the first semiconductor chip may be reduced. Accordingly, it may be possible to improve electric characteristics of the semiconductor package.

While example embodiments of the inventive concept have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.