Patent ID: 12223322

DETAILED DESCRIPTION

Overview

In one example, a processor embedded in a PLD can serve some other useful purpose when the customer does not need it as a general purpose processor.

In one example, a processor embedded in a PLD can serve as a configurable fixed function emulator.

In one example, a short, infinite loop program (kernel) is stored in the cache.

In one example, data is streamed in from the fabric and back out to the fabric.

In one example, the data is input/output according to a fixed schedule.

In one example, the embedded processor can serve as a fixed function block implementing various useful functions for the PLD fabric, such as floating-point multiply-add, multiply accumulate, complex multiply, butterfly (for FFT) or matrix-matrix multiply, without limitation.

In one example, the fixed function kernel mode can exchange data with the fabric by aliasing register file registers.

In one example, the fixed function kernel mode exchange of data with the fabric has a deterministic schedule.

In one example, the fixed function kernel mode can be synchronized with the start of the loop with the fabric using a load instruction.

In one example, the embedded processor is one or more scalar processors.

In one example, the embedded processor is a vector processor block (VPB), also referred to as a digital vector processor (DVP).

In one example, the embedded processor is one or more scalar processors and one or more VPBs or DVPs.

FIG.1depicts, generally at100, an example PLD implementation, for example, but not limited to, on a semiconductor die. At102is a PLD. At104is a microprocessor (μP) having a logic unit106which has a general purpose mode108and a fixed function mode110. Via link111the general purpose mode108is operable with a general purpose process112related to the PLD102. Via link119the logic unit106is operable with a memory unit118. At114is fabric which has logic configured into fabric116. Via link115the fixed function mode110is operable with the logic configured into fabric116. Via link113fabric114is operable with memory unit118.

While a single microprocessor (μP)104is shown inFIG.1for explanation, it is to be understood that PLD102can have more than one microprocessor (μP)104, with respective logic units106having respective general purpose modes108and fixed function modes110, without limitation.

FIG.2depicts, generally at200, an example implementation. At204is a microprocessor (μP) having a logic unit206which has a vector processor block (VPB)212, a general purpose mode208, and a fixed function mode210. The VPB212is operable via link209in the general purpose mode208. The VPB212is operable via link211in the fixed function mode210.

FIG.3depicts, generally at300, an example implementation. At312is a VPB having one or more arithmetic logic unit (ALU)320shown respectively as ALU0to ALU N314-0to314-N, with an optional floating point unit (FPU)316. A cache318is coupled via321or323with the one or more ALUs320or the FPU316respectively. It is noted that the cache318can be external of the ALUs314or the FPU316or disposed within the respective ALUs314or the FPU316. The cache318has a Kernel310that is operable via link326in a fixed function mode310. The fixed function mode310, which emulates a fixed function uses data streamed in from the fabric330via link331.

FIG.4depicts, generally at400, an example implementation. At412is a VPB having one or more of an arithmetic logic unit (ALU)420shown as ALU0to ALU N414-0to414-N, or a floating point unit (FPU)416. A cache418is shown coupled via421or423with the one or more ALUs420or the FPU416, respectively. It is noted that the cache418can be external of the ALUs414or the FPU416or disposed within the ALUs414or the FPU416. The cache418has a Kernel410that is operable via link426in a fixed function mode410. The fixed function mode410, which emulates a fixed function, uses data streamed in from the fabric430via link431. Kernel410has an infinite loop program440that receives a start control via link433from a start block432within fabric430. VPB410receives via435a sync control434within fabric430. Optionally, one or more microprocessors450that are connected to the fabric430via437receive a sync via435from sync434within fabric430. This way the optional microprocessors can be synchronized.

FIG.5depicts, generally at500, an example implementation. At512is a VPB having one or more of an arithmetic logic unit (ALU)520shown as ALU0to ALU N514-0to514-N, or a floating point unit (FPU)516. A cache518is shown operable via521or523with the one or more ALUs520or the FPU516respectively. It is noted that the cache518can be external to the ALUs514or the FPU516or disposed within the ALUs514or the FPU516. The cache518has a Kernel510that is operable via link526in fixed function mode510. The fixed function mode510, which emulates a fixed function uses data streamed in from the fabric530via link531. At532is a data interconnect in fabric530. Via link533the data interconnect532transfers data signals between the fabric530and the cache518. At540is a controller which via link533is operable with data interconnect532, and via link535with memory unit542.

FIG.6depicts, generally at600, an example implementation. At602is the PLD. At612is a VPB having one or more of an arithmetic logic unit (ALU)620shown as ALU0to ALU N614-0to614-N, or a floating point unit (FPU)616. A cache618is shown operable via621or623with the one or more ALUs620or the FPU616respectively. It is noted that the cache618can be external of the ALUs614or the FPU616or disposed within the ALUs614or the FPU616. The cache618has a Kernel610that is operable via link626in fixed function mode610. The fixed function mode610, which emulates a fixed function uses data streamed in from the fabric630via link631. At632is a control interconnect which via link633exchanges control signals between the VPB612and a network-on-chip (NoC)640of the PLD602.

FIG.7depicts, generally at700, an example implementation. At704is a microprocessor (μP) having a logic unit706which has a vector processor block712, a general purpose mode708, and a fixed function mode710. The VPB712is operable as an embedded processor720via link709in the general purpose mode708. The VPB712is operable as a floating point math block730via link711in the fixed function mode710. Via link715the fixed function mode710is operable with the logic configured into fabric716which is part of fabric714.

FIG.8depicts, generally at800, an example flow chart of a method. At802is a start of controlling an operation of a microprocessor embedded in a PLD, which proceeds via link803to a decision at804. At804a determination is made if a logic unit in the PLD received a control signal from a fabric of the PLD, and when so (Yes) proceed via link819to block820. If at804a determination is made that the logic unit has not received the control signal from the fabric of the PLD (No) then proceed via link805to block806. At block806execute at least one general purpose process related to an operation of the PLD. At block820emulate a fixed function for use by logic configured into the fabric, then proceed via line821to block822. At block822exchange signals with a memory unit coupled to the logic unit and to the fabric, where the fabric transfers signals with the logic unit in relation to the fixed function.

FIG.9depicts, generally at900, an example flow chart of a method. At902is a start of controlling an operation of a microprocessor embedded in a PLD, which proceeds via link903to a decision at904. At904a determination is made if a logic unit of the PLD received a control signal from a fabric of the PLD, and when so (Yes) proceed via link919to block920. If at904a determination is made that the logic unit has not received the control signal from the fabric of the PLD (No) then proceed via link905to block906. At block906execute at least one general purpose process related to an operation of the PLD. At block920emulate a fixed function for use by logic configured into the fabric of the PLD, then proceed via line921to block922. At block922exchange signals with a memory unit coupled to the logic unit and to the fabric, where the fabric transfers signals with the logic unit in relation to the fixed function. Block924has a logic unit that comprises a VPB operable in at least a first mode corresponding to the emulating, and a second mode corresponding to the executing. Via link925the first mode is operable with emulating block920. Via link927the second mode is operable with executing block906.

FIG.10depicts, generally at1000, an example flow chart of a method. At1002is a start of controlling an operation of a microprocessor embedded in a PLD, which proceeds via link1003to a decision at1004. At1004a determination is made if a logic unit of the PLD received a control signal from a fabric of the PLD, and when so (Yes) proceed via link1019to block1020. If at1004a determination is made that the logic unit has not received the control signal from the fabric of the PLD (No) then proceed via link1005to block1006. At block1006execute at least one general purpose process related to an operation of the PLD. At block1020emulate a fixed function for use by logic configured into the fabric, then proceed via line1021to block1022. At block1022exchange signals with a memory unit coupled to the logic unit and to the fabric, where the fabric transfers signals with the logic unit in relation to the fixed function. Block1028has block1024and block1026. Block1024has a logic unit that comprises a vector processor block (VPB) (more detail in block1026) operable in relation to at least a first mode corresponding to the emulating, and a second mode corresponding to the executing. Via link1025the first mode is operable with emulating block1020. Via link1027the second mode is operable with executing block1006. Block1026details the VPB as comprising one or more of an arithmetic logic unit (ALU) or a floating point unit (FPU), and a cache disposed in or coupled to the ALU/FPU, the cache comprising a kernel stored therewith and operable in relation to the emulated fixed function (via link1025first mode), and wherein the method comprises computing the emulated fixed function using data streamed in from the fabric.

FIG.11depicts, generally at1100, an example flow chart of a method. At1102is a start of controlling an operation of a microprocessor embedded in a PLD, which proceeds via link1103to a decision at1104. At1104a determination is made if a logic unit of the PLD received a control signal from a fabric of the PLD, and when so (Yes) proceed via link1119to block1120. If at1104a determination is made that the logic unit of the PLD has not received the control signal from the fabric of the PLD (No) then proceed via link1105to block1106. At block1106execute at least one general purpose process related to an operation of the PLD. At block1120emulate a fixed function for use by logic configured into the fabric, then proceed via line1121to block1122. At block1122exchange signals with a memory unit coupled to the logic unit and to the fabric, where the fabric transfers signals with the logic unit in relation to the fixed function. Block1128has block1124, block1126, and block1130. Block1124has a logic unit that comprises a VPB (more detail in block1126) operable in at least a first mode corresponding to the emulating, and a second mode corresponding to the executing. Via link1125the first mode is operable with emulating block1120. Via link1127the second mode is operable with executing block1106. Block1126details the VPB as comprising one or more of an arithmetic logic unit (ALU) or a floating point unit (FPU), and a cache (more detail in block1130) disposed in or coupled to the ALU/FPU, the cache comprising a kernel stored therewith and operable in relation to the emulated fixed function (via link1125first mode), and wherein the method comprises computing the emulated fixed function using data streamed in from the fabric. Block1130has additional details where the kernel comprises code relating to an infinite loop program stored in the cache, and comprising triggering a start of the infinite loop program from the fabric, and synchronizing the microprocessor with the fabric.

FIG.12depicts, generally at1200, an example flow chart of a method. At1202is a start of controlling an operation of a microprocessor embedded in a PLD, which proceeds via link1203to a decision at1204. At1204a determination is made if a logic unit of the PLD received a control signal from a fabric of the PLD, and when so (Yes) proceed via link1219to block1220. If at1204a determination is made that the logic unit of the PLD has not received the control signal from the fabric of the PLD (No) then proceed via link1205to block1206. At block1206execute at least one general purpose process related to an operation of the PLD. At block1220emulate a fixed function for use by logic configured into the fabric, then proceed via line1221to block1222. At block1222exchange signals with a memory unit coupled to the logic unit and to the fabric, where the fabric transfers signals with the logic unit in relation to the fixed function. Block1268has block1264, block1266, and block1260. Block1264has a logic unit that comprises a VPB (more detail in block1266) operable in relation to at least a first mode corresponding to the emulating, and a second mode corresponding to the executing. Via link1265the first mode is operable with emulating block1220. Via link1267the second mode is operable with executing block1206. Block1266details the VPB as comprising one or more of an ALU or an FPU, and a cache (more detail in block1260) disposed in or coupled to the ALU/FPU, the cache comprising a kernel stored therewith and operable in relation to the emulated fixed function (via link1265first mode), and wherein the method comprises computing the emulated fixed function using data streamed in from the fabric. Block1260has additional details where the kernel comprises code relating to an infinite loop program stored in the cache, and triggering a start of the infinite loop program from the fabric, and synchronizing the microprocessor with the fabric, and where the synchronizing further comprises synchronizing the microprocessor with one or more other microprocessors of the PLD that are coupled to the fabric as shown via link1261sync to1262having one or more other microprocessors of the PLD that are coupled to the fabric.

FIG.13depicts, generally at1300, an example flow chart of a method. At1302is a start of controlling an operation of a microprocessor embedded in a PLD, which proceeds via link1303to a decision at1304. At1304a determination is made if a logic unit of the PLD received a control signal from a fabric of the PLD, and when so (Yes) proceed via link1319to block1320. If at1304a determination is made that the logic unit has not received the control signal from the fabric of the PLD (No) then proceed via link1305to block1306. At block1306execute at least one general purpose process related to an operation of the PLD. At block1320emulate a fixed function for use by logic configured into the fabric, then proceed via line1321to block1322. At block1322exchange signals with a memory unit coupled to the logic unit and to the fabric, where the fabric transfers signals with the logic unit in relation to the fixed function. Block1328has block1324and block1326. Block1324has a logic unit that comprises a VPB (more detail in block1326) operable in relation to at least a first mode corresponding to the emulating, and a second mode corresponding to the executing. Via link1325the first mode is operable with emulating block1320. Via link1327the second mode is operable with executing block1306. Block1326details the VPB as comprising one or more of an ALU or an FPU, and a cache disposed in or coupled to the ALU/FPU, the cache comprising a kernel stored therewith and operable in relation to the emulated fixed function (via link1325first mode), and wherein the method comprises computing the emulated fixed function using data streamed in from the fabric. Block1330via link1331to block1326transfers data signals between the fabric and the VPB via a data interconnect coupled to the cache and to the fabric, and controls the memory unit in relation to the transferred data signals.

FIG.14depicts, generally at1400, an example flow chart of a method. At1402is a start of controlling an operation of a microprocessor embedded in a PLD, which proceeds via link1403to a decision at1404. At1404a determination is made if a logic unit of the PLD received a control signal from a fabric of the PLD, and when so (Yes) proceed via link1419to block1420. If at1404a determination is made that the logic unit of the PLD has not received the control signal from the fabric of the PLD (No) then proceed via link1405to block1406. At block1406execute at least one general purpose process related to an operation of the PLD. At block1420emulate a fixed function for use by logic configured into the fabric, then proceed via line1421to block1422. At block1422exchange signals with a memory unit coupled to the logic unit and to the fabric, where the fabric is operable to transfer signals with the logic unit in relation to the fixed function. Block1428has block1424and block1426. Block1424has a logic unit that comprises a VPB (more detail in block1426) operable in relation to at least a first mode corresponding to the emulating, and a second mode corresponding to the executing. Via link1425the first mode is operable with emulating block1420. Via link1427the second mode is operable with executing block1406. Block1426details the VPB comprises one or more of an ALU or an FPU, and a cache disposed in or coupled to the ALU/FPU, the cache comprising a kernel stored therewith and operable in relation to the emulated fixed function, and wherein the method comprises computing the emulated fixed function using data streamed in from the fabric, and where the VPB has a control interconnect exchanging control signals between the VPB and a network-on-chip (NoC) of the PLD via link1431control interconnect to block1430having a network-on-chip (NoC) of the PLD.

FIG.15depicts, generally at1500, an example flow chart of a method. At1502is a start of controlling an operation of a microprocessor embedded in a PLD, which proceeds via link1503to a decision at1504. At1504a determination is made if a logic unit of the PLD received a control signal from a fabric of the PLD, and when so (Yes) proceed via link1519to block1520. If at1504a determination is made that the logic unit of the PLD has not received the control signal from the fabric of the PLD (No) then proceed via link1505to block1506. At block1506execute at least one general purpose process related to an operation of the PLD. At block1520emulate a fixed function for use by logic configured into the fabric, then proceed via line1521to block1522. At block1522exchange signals with a memory unit coupled to the logic unit and to the fabric, where the fabric transfers signals with the logic unit in relation to the fixed function. Block1524has a logic unit that comprises a vector processor block (VPB) operable in relation to at least a first mode corresponding to the emulating, and a second mode corresponding to the executing, and where the VPB is operable as an embedded processor in relation to the corresponding second mode, and in relation to the first mode, the method comprises operating the VPB as a floating-point (FP) mathematics (Math) block for use by the configured logic of the fabric, in relation to the first mode. Via link1525the first mode is operable with emulating block1520. Via link1527the second mode is operable with executing block1506.

FIG.16depicts, generally at1600, an example implementation. At1660is an integrated circuit (IC), having a semiconductor die1650with a plurality of components1640including a PLD1602. PLD1602has at1604a microprocessor (μP), a fabric1614and a memory unit1618. The microprocessor1604has a logic unit1606which has a general purpose mode1608and a fixed function mode1610. Via link1611the general purpose mode1608is operable with a general purpose process1612related to the PLD1602. Via link1619the logic unit1606is operable with the memory unit1618. Fabric1614has logic configured into fabric1616. Via link1615the fixed function mode1610is operable with the logic configured into fabric1616. Via link1613fabric1614is operable with memory unit1618. The semiconductor die1650has a conductive matrix1652for coupling the plurality of components1640and one or more components1662external to the semiconductor die1650, and one or more components1670external to the IC1660, via a representative link1680.

FIG.17depicts, generally at1700, an example implementation. At1760is an integrated circuit (IC), having a semiconductor die1750with a plurality of components1740including a PLD1702. The PLD1702has at1704a microprocessor (μP), a fabric1714and a memory unit1718. The microprocessor1704has a logic unit1706which has a vector processor block (VPB)1720, a general purpose mode1708and a fixed function mode1710. The VPB1720is operable via link1721with the general purpose mode1708. The VPB1720is operable via link1723with the fixed function mode1710. Via link1711the general purpose mode1708is operable with a general purpose process1712related to the PLD1702. Via link1719the logic unit1706is operable with the memory unit1718. Fabric1714has logic configured into fabric1716. Via link1715the fixed function mode1710is operable with the logic configured into fabric1716. Via link1713fabric1714is operable with memory unit1718. The semiconductor die1750has a conductive matrix1752for coupling a plurality of components1740and one or more components1762external to the semiconductor die, and one or more components1770external to the IC, via a representative link1780.

FIG.18depicts, generally at1800, an example implementation. At1860is an integrated circuit (IC), having a semiconductor die1850with a plurality of components1840including a PLD1802. The PLD1802has at1804a microprocessor (μP), and at1814fabric. The microprocessor1804has a logic unit1806which has a vector processor block (VPB)1820. The VPB1820has an ALU block1822which has one or more of an arithmetic logic unit (ALU)1824shown as ALU0to ALU N1824-0to1824-N, or a floating point unit (FPU)1826, and a cache1828. Cache1828is shown operable via1829or1831with the one or more ALUs1824or the FPU1826respectively. It is noted that the cache1828can be external to the ALUs1824or the FPU1826or disposed within the ALUs1824or the FPU1826. The cache1828has a Kernel1830that is operable via link1833with fixed function mode1810. The fixed function mode1810, which emulates a fixed function uses data streamed in, via link1817, from the fabric1814from the logic configured into fabric1816.

FIG.19depicts, generally at1900, an example implementation. Not shown, is an integrated circuit (IC), having a semiconductor die, also not shown, with a plurality of components, also not shown, including a PLD1902. The PLD1902has at1904a microprocessor (μP) having a logic unit1906, which logic unit1906has a vector processor block (VPB)1920. The VPB1920has one or more of an arithmetic logic unit (ALU)1922shown as ALU0to ALU N1924-0to1924-N, or a floating point unit (FPU)1926and a cache1928. The cache1928is shown operable via1929or1931with the one or more ALUs1922or the FPU1926respectively. It is noted that the cache1928can be external to the ALUs1922or the FPU1926or disposed within the ALUs1922or the FPU1926. The cache1928has a Kernel1930that is operable via link1933with fixed function mode1910. The fixed function mode1910, which emulates a fixed function uses data streamed in, via link1917, from the fabric1914from the logic configured into fabric1916. Kernel1930has an infinite loop program1932that receives a start control via link1935from a start block1918within fabric1914. VPB1920receives via1937a sync control1940from within fabric1914. Optionally, one or more microprocessors1950that are connected to the fabric1914via1951receive a sync via1937from sync1940within fabric1914. This way the optional microprocessors can be synchronized.

FIG.20depicts, generally at2000, an example implementation. At2060is an integrated circuit (IC), having a semiconductor die2050with a plurality of components2040including a PLD2002. The PLD2002has at2004a microprocessor (μP), at2014a fabric, at2042a controller and at2044a memory unit. The μP2004has a logic unit2006which logic unit2006has a vector processor block (VPB)2020. The VPB2020has one or more of an arithmetic logic unit (ALU)2022shown as ALU0to ALU N2022-0to2022-N, or a floating point unit (FPU)2026. VPB2020has a cache2028, which cache2028is shown operable via2029or2031with the one or more ALUs2022or the FPU2026respectively. It is noted that the cache2028can be external to the ALUs2022or the FPU2026or disposed within the ALUs2022or the FPU2026. The cache2028has a Kernel2030that is operable via link2033in a fixed function mode2010. The fixed function mode2010, which emulates a fixed function uses data streamed in, via link2017, from the fabric2014from the logic configured into fabric2016. At2040is a data interconnect in fabric2014. Via link2041the data interconnect2040is operable with the cache2028of the VPB2020to transfer data signals between the fabric2014and the cache2028. At2042is a controller which via link2041is operable with data interconnect2040, and via link2043with memory unit2044.

FIG.21depicts, generally at2100, an example implementation. At2160is an integrated circuit (IC), having a semiconductor die2150, the semiconductor die2150having a plurality of components2140including a PLD2102. The PLD2102has at2104a microprocessor (μP), at2142a network-on-chip (NoC) and at2114a fabric. The PLD microprocessor2104has a logic unit2106, which logic unit2106has a vector processor block (VPB)2120. The VPB2120has one or more of an arithmetic logic unit (ALU)2122shown as ALU0to ALU N2124-0to2124-N, or a floating point unit (FPU)2126, a cache2128and a control interconnect2140. The cache2128is shown operable via2129or2131with the one or more ALUs2122or the FPU2126respectively. It is noted that the cache2128can be external to the ALUs2122or the FPU2126or disposed within the ALUs2122or the FPU2126. The cache2128has a Kernel2130that is operable via link2133in fixed function mode2110. The fixed function mode2110, which emulates a fixed function uses data streamed in from the fabric2114, via link2117, from the logic configured into fabric2116. Control interconnect2140is operable via link2141to exchange control signals between the VPB2120and NoC2142of the PLD2102.

FIG.22depicts, generally at2200, an example implementation. At2260is an integrated circuit (IC) having a semiconductor die2250and one or components2262external to the semiconductor die2250. Semiconductor die2250has a plurality of components2240including a PLD2202and a conductive matrix2252for coupling a plurality of components2240. The PLD2202has at2204a microprocessor (μP), a memory unit at2218and at2214a fabric. The microprocessor2204has a logic unit2206, which logic unit2206has a vector processor block (VPB)2220having a general purpose mode2208and a fixed function mode2210. The VPB2220is operable as an embedded processor2224via link2221in the general purpose mode2208. The VPB2220is operable as a floating point math block2230via link2223in the fixed function mode2210. Via link2211the general purpose mode2208is operable with a general purpose process2212related to the PLD2202. Via link2219the logic unit2206is operable with the memory unit2218. Fabric2214has logic configured into fabric2216. Via link2215the fixed function mode2210is operable with the logic configured into fabric2216. Via link2213fabric2214is operable with memory unit2218. One or more components external to the IC2270are shown, which may communicate with plurality of components2240, conductive matrix2252, or one or more components external to the semiconductor dies2262via a representative link2280.

FIG.11at1130(and in the associated specification) discusses synchronizing the microprocessor with the fabric, andFIG.12at1260(and in the associated specification) discusses synchronizing multiple microprocessors. Additionally, atFIG.19at1940,1937,1950, and1951(and in the associated specification) discusses synchronizing multiple microprocessors. There are multiple approaches to the syncing mechanism. For example, but not limited to, using the PLD fabric to stall microprocessors, using the PLD fabric to start multiple microprocessors (including VPBs) simultaneously, pausing the respective kernels in the microprocessors until valid data is present, using memory mapped load instructions to stall the microprocessors, or using vector load instructions in VPBs to start execution, without limitation. The reason synchronization is beneficial in some examples, is that predictable results can be achieved at predictable times with multiple microprocessors. In this way scheduling of data and results can be communicated to other microprocessors with predictable behavior. That is, for example, the result from one microprocessor can be communicated in time to other microprocessors without microprocessors having to wait to receive the data and results.

If the IC is using a communications standard for the PLD, for example, but not limited to the ARM LIMITED (ARM) Advanced Microcontroller Bus Architecture (AMBA) AXI4-Streaming Protocol then one example of multiple microprocessor synchronization is illustrated inFIG.23generally at2300. Shown at2302is synchronization shim logic between processors 0 to N (2304-0to2304-N) and fabric logic 0 to N (2306-0to2306-N). The synchronization shim logic2302handles, via the logic illustrated, the AXI4-Streaming READY signals and AXI4-Streaming VALID signals from, and to, the multiple processors2304-0to2304-N and the multiple fabric logic2306-0to2306-N. Note that the data2308-0to2308-N between the respective processor2304and fabric logic2306is not controlled by the2302the synchronization shim logic2302but rather goes directly to/from the respective processor2304to/from the respective fabric logic2306.

InFIG.23a plurality of processors2304is represented by processor 0 to processor N (2304-0to2304-N) respectively. Associated with each of the processors (2304-0to2304-N) is fabric logic2306denoted 0 to N (2306-0to2306-N) respectively. For each of the processors2304there is a respective valid output denoted 0 to N (2310-0to2310-N) and a ready input denoted 0 to N (2312-0to2312-N). Likewise for each fabric logic2306there is a valid input denoted 0 to N (2314-0to2314-N) and ready output denoted 0 to N (2316-0to2316-N). In the synchronization shim logic2302there are 0 to N AND gates2318-0to2318-N which respectively AND the associated processor valid signal (2310-0to2310-N) and the fabric logic ready signal (2316-0to2316-N respectively) yielding (after the ANDing) a plurality of processor-valid-fabric-ready signals which are fed into the AND gate2320. The output of the2320AND gate (after the ANDing) can be considered a global sync signal which is routed to each of the processors 0 to N ready inputs (2312-0to2313-N) and routed to each of the fabric logic 0 to N valid inputs (2314-0to2314-N).

While all of the N+1 (0 to N) processors inFIG.23are shown synchronized, the example is not so limited. For example, on an IC having many microprocessors certain ones may be synchronized and others may not. Also, different groups of microprocessors may be synchronized differently, or synchronized differently depending on their general purpose mode or fixed function mode.

FIG.24depicts, generally at2400, an example implementation showing a die2402having multiple fabric regions as shown by representative fabric region2404and multiple VPBs as shown by representative VPB2406. What is to be appreciated is that VPBs not needed as processors, i.e. operating in general purpose mode, can instead be used by fabric logic as fixed functions, i.e. operating in fixed function mode, such as floating point ALUs, without limitation.

FIG.25depicts, generally at2500, an example implementation showing a VPB2502in a fixed function mode as a floating-point multiply-add (FPMADD) soft intellectual property (IP) block performing the math function D=A+(B*C). The inputs on the left are a clock (clk)2504, reset negative active (resetn)2506, input A2508, input B2510, and input C2512. The inputs A, B, and C are illustrated to be respectively 256 bits wide. The outputs on the right are a ready signal2514, and an output D2516illustrated as 256 bits wide.

FIG.26depicts, generally at2600, an example implementation showing major functional blocks and interconnections. At2602is the VPB, at2604a NoC, at2608the FPGA fabric.

ForFIG.26here are some notations:CSCB—Control, Status, and Configuration BusI and T—Initiator and Target, which are more commonly known as Master and SlaveVPB—Vector Processor Block (which may also be called DVP—Distributed or Digital Vector Processor).NoC—Network-on-ChipVLSRAM—Very-Large Static Random Access Memory. Large on-chip memories that are part of the FPGA SoC.ECC—Error Correction CodeRMW—Read/Modify/WriteVIS7 is a part number from SiFive, Inc. indicating certain features of the processor.L1 I$/D$ is level one instruction cache and data cacheITIM—Instruction Tightly Integrated MemoryDLS—Data Local StoreVecRegFile—Vector Register FileFPGA—Field Programmable Gate Array (a PLD)

Regarding I and T notations it should be noted that I and T are Initiator and Target, which may also be known as Master and Slave respectively. The arrows go from Initiator to Target. The arrow indicates who initiates requests and what target(s) they go to, but the requests themselves can be reads from a target or writes to a target, so there may be data wires going in both directions on all I→T buses.