Patent ID: 12211920

In the drawings, which are not necessarily drawn to scale, like reference symbols may indicate like and/or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols show in one drawing may not be repeated for the same, and/or similar elements in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings, but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of that element are illustrated.

DETAILED DESCRIPTION

This application is directed to devices and processes for forming an Ohmic backside contact for semiconductor devices, such as during semiconductor wafer processing, e.g. back-end wafer processing. The approaches described herein include performing a metallic implant on a backside of a semiconductor wafer, where that metallic implant can facilitate formation of a low-resistance silicon-metal alloy backside ohmic contact, such as by performing the metallic implant at high temperature (e.g., by heating the semiconductor wafer and/or by heating implanted metallic material (e.g., metal ions). Additionally, backside metal layers can then be disposed on (as part of) the backside ohmic contact to produce a low-resistance backside contact that can achieve and/or improve operation of associated circuitry. For instance, such approaches can, as compared to current approaches, improve (reduce) collector-to-emitter saturation voltage (Vcesat) for insulated-gate bipolar transistors (IGBTs), and/or improve (reduce) drain-to-source on resistance (Rdson) for metal-oxide-semiconductor field-effect transistors included in the semiconductor device. In some implementations, the backside contact can be used to couple the semiconductor die to a die attach paddle of a leadframe, a die attach pad of a substrate, etc.

The approaches described herein can also overcome at least some of the drawbacks of current approaches described above. For example, use of such a metallic implant can inhibit oxidation of a corresponding semiconductor wafer (e.g., a silicon wafer), allowing for longer time periods between preparation of the wafer for backside contact formation and application of backside metallization, thus increasing flexibility during semiconductor manufacturing. The approaches described herein can also allow for omitting a wet chemistry etch of the semiconductor wafer prior to formation of the backside contact, which can have process control issues, and for omitting a sputtering operation (initial sputtering operation) for ohmic contact formation. The disclosed approaches can also improve process control of backside contact resistance, as compared to current approaches, through selection of a metallic implant dose and an associated implant energy.

FIG.1is a diagram schematically illustrating an example semiconductor device100. In example implementations, the semiconductor device100can be produced, along with other semiconductor devices, on a semiconductor wafer (e.g., a silicon wafer, a silicon carbide wafer, etc.). As shown inFIG.1, the semiconductor device100includes a semiconductor substrate110(e.g., a portion of a semiconductor wafer), and active circuitry120formed in and/or on a side111of the semiconductor substrate110. The semiconductor device100also includes an ohmic contact130formed in the substrate110, e.g., on a side112, opposite the side111, a metallic layer140disposed on the ohmic contact130.

In the semiconductor device100, the active circuitry120can include one or more individual devices (e.g., transistors, capacitors, resistors, etc.) formed in the semiconductor substrate110, as well as interconnection layers formed on the semiconductor substrate110, where the interconnection layers provide electrical connections to the individual devices. For instance, in some implementations, the active circuitry120can include a power transistor, such as an IGBT or a MOSFET, as well as electrical connections to terminals of the power transistor. For purposes of clarity and brevity, the specifics of such circuitry are not described herein.

In example implementations, the ohmic contact130can be defined using one or more implants. For instance, forming the ohmic contact130can include performing a semiconductor doping impurity implant, such as an implant including one or more of boron, phosphorous, arsenic, etc. The particular impurity or impurities used can depend on the specific implementation. The ohmic contact130can also include a metallic implant, including one or more of aluminum, gold, nickel, platinum, palladium, silver, and/or copper. In some implementations, the metallic implant can form an alloy with the semiconductor substrate110. For instance, in an example implementation of the semiconductor device100, the semiconductor substrate110can be a silicon substrate that is implanted with aluminum. As silicon can dissolve in aluminum, in this example, the ohmic contact130can include a silicon-aluminum alloy. In some implementations, the impurity and metallic implants used to define the ohmic contact130can be blanket implants that are performed over an entire side (surface) of a semiconductor wafer including the semiconductor device100(e.g., performed on the side112of the semiconductor substrate110).

As shown inFIG.1, the semiconductor device100can further include the metallic layer140, which is disposed on (deposited on) the ohmic contact130. The metallic layer140can include one or more metallic materials, formed in one or more layers, that are deposited on the ohmic contact130using metal sputtering. In some implementations, the metallic layer140can include one or more of nickel vanadium, titanium, and/or silver. The ohmic contact130, in combination with the metallic layer140can provide a low-resistance backside contact (ohmic contact) for the semiconductor device100that can achieve both the performance advantages and semiconductor manufacturing process advantages described herein.

FIGS.2A to2Care diagrams schematically illustrating an example process for forming a backside ohmic contact in a semiconductor substrate210(e.g., a semiconductor wafer). In some implementations, the process illustrated byFIGS.2A to2C(as well as the methods illustrated inFIGS.3and4discussed below) can be used to produce an ohmic contact, such as the ohmic contact130of the semiconductor device100inFIG.1. As compared toFIG.1, the orientation of the semiconductor substrate210is inverted from the orientation of the semiconductor substrate110. That is, a side212in which an ohmic contact is formed is the upper side of the semiconductor substrate210inFIG.2, as opposed to the side111of the semiconductor substrate110being illustrated as the lower side inFIG.1.

Referring toFIG.2A, the semiconductor substrate210can include active circuitry220, which can be produced prior to formation of an ohmic contact in the semiconductor substrate210. As shown inFIG.2A, as well as inFIGS.2B and2C. the substrate210can have an irregular (rough, etc.) surface on the side212. This irregular surface can be a result of a grinding operation that is performed to thin the semiconductor substrate210to a desired thickness. In some implementations, a substrate etch can be performed after the grinding operation to remove defects, such as dislocations, in a crystalline structure of the semiconductor substrate210. In this example, the irregular surface of the210on the side212increases an effective surface area, as compared to a planar surface, for ohmic contact formation, which contributed to reducing overall backside contact resistance.

Referring toFIG.2B, an implant layer230acan be formed in the semiconductor substrate210. For instance, the implant layer230acan include a semiconductor impurity implant and a metallic implant, such as described herein. In this example, the implant layer230ais formed using a plurality of implant operations235. That is a first implant operation235can be performed to implant the semiconductor impurity (or impurities), while a second implant can be performed to implant one or more metallic materials (e.g., aluminum, gold, nickel, platinum, palladium, silver, and/or copper). As shown inFIG.2B, the implant layer230acan have an average depth D1. The average depth D1can depend, at least in part, on an energy of an ion beam used to implant the metallic material(s) and an implant dose of the metallic materials. In some implementations an ion beam with an energy between 10 and 500 keV can be used, with an implant metallic material dose between 1×1014/cm2 and 5×1016/cm2. In some implementations, the average depth D1can be in a range of 0.1 um to 10 um.

Referring now toFIG.2C, in this example, the implant layer230aofFIG.2Ccan define an ohmic contact230bin the semiconductor substrate210. For instance, as discussed, above, the implanted portion of the substrate210(e.g., silicon) can form an alloy with at least a portion of the one or more implanted metallic materials (e.g., aluminum), which, along with the semiconductor impurity implant, can define the ohmic contact230b.

In some implementations, heat (e.g., in a temperature range of 250 to 450 degrees Celsius) can be applied either during and/or after performing the metallic implant of the ohmic contact230b. For instance, in some implementations, an anneal operation (e.g., laser anneal, oven anneal, etc.) can be performed after the metallic implants. In other implementations, the semiconductor substrate210and or the implanted metallic material(s) can be heated during the metallic implant. Such application of heat can provide a number of benefits, such as repairing implant damage, forming metallic spikes237, and/or compressively straining the crystalline structure of the semiconductor substrate210. In some implementations, applying heat during the metallic implant can allow for omitting a post implant anneal operation, as resultant implant damage is reduced and/or repaired as a result of the heat applied during performance of the metallic implant.

In this example, the metallic spikes237can be formed as a result of applied heat causing the implanted metallic material to be driven into openings (holes) in the crystalline structure of the210. The metallic spikes237can contribute to reducing resistance of the ohmic contact230b. As shown inFIG.2C, the metallic spikes237can have respective depths, such as depth D2, that are greater than the average depth D1of the implant layer230a, where the average depth D1ofFIG.2Bis shown for reference purposes inFIG.2C. Further, compressively straining the lattice can further reduce resistance of backside contacts and improve performance of devices included in the active circuitry220. For instance, such compressive strain can achieve a twenty percent improvement (reduction) in Vcesatfor an IGBT, or Rdsonfor a MOSFET. While not shown inFIG.2, one or more metallic layers of a backside contact, such as the metallic layer140, can then be formed (deposited, sputtered, etc.) on the ohmic contact230b.

FIG.3is a flowchart illustrating an example method300for forming a backside contact. In some implementations, the method300can be used, in conjunction with other semiconductor processing operations, to produce the semiconductor device100ofFIG.1and/or the ohmic contact230a,230bofFIGS.2A-2C. In some implementations, operations of the method300can be added, omitted and/or replaced with other operations. For instance, as discussed above, applying heat during a metallic implant operation can allow for omitting a post implant anneal operation. As another example, laser anneal operations can be replaced with furnace anneal operations.

The method300, at block310, includes performing a grinding operation to thin a semiconductor wafer (substrate) to a desired thickness. At block320, the method300includes a substrate etch operation (e.g., a plasma etch, dry etch, wet etch, etc.) to remove damage from the grinding operation at block310. At block330, the method300includes performing a semiconductor impurity implant and, at block340, performing a laser anneal operation to repair implant damage from the impurity implant at block330.

At block350, the method300includes performing a metallic material implant for forming an ohmic contact. In this example, heat can be applied during the implant of block350, allowing for an anneal operation after the metallic implant to be omitted. At block360, the method300includes a pre-heat operation for backside metallization application (e.g., heating at 350 degrees Celsius for approximately 30 seconds) and, at block370, depositing (e.g., sputtering) backside metallization layers, such as the metallic layer140ofFIG.1, on the ohmic contact formed at block350.

FIG.4is a flowchart illustrating another example method400for forming a backside contact. As with the method300, in some implementations, the method400can be used, in conjunction with other semiconductor processing operations, to produce the semiconductor device100ofFIG.1and/or the ohmic contact230a,230bofFIGS.2A-2C. In some implementations, operations of the method400can be added, omitted and/or replaced with other operations. For instance, as discussed above, applying heat during a metallic implant operation can allow for omitting a post implant anneal operation. As another example, laser anneal operations can be replaced with furnace anneal operations.

The method400, at block410, includes performing a grinding operation to thin a semiconductor wafer (substrate) to a desired thickness. At block420, the method400includes a substrate etch operation (e.g., a plasma etch, dry etch, wet etch, etc.) to remove damage from the grinding operation at block410.

At block430, the method400includes performing a semiconductor impurity implant and, at block440, performing a metallic material implant for forming an ohmic contact. At block450, the method400includes performing a laser anneal operation to repair implant damage from the impurity implant at block430and the metallic implant at block440. In this example, heat may not be applied during the metallic implant450. At block460, the method400includes a pre-clean operation prior to backside metallization application and, at block470, depositing (e.g., sputtering or evaporating) backside metallization layers, such as the metallic layer140ofFIG.1, on the ohmic contact formed at block440and/or block450.

It will be understood that, in the foregoing description, when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, top, bottom, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Silicon Carbide (SiC), Gallium Arsenide (GaAs), Gallium Nitride (GaN), and/or so forth.

While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.