Patent ID: 12224237

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. In the accompanying drawings, some layers/features may be omitted for simplification.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of” Further, in the following fabrication process, there may be one or more additional operations in/between the described operations, and the order of operations may be changed.

In the back-end-of-line (BEOL) process for forming metal wiring layers, a dual damascene process is used, in which trenches for metal lines (conductive wiring patterns) and holes for vias are fabricated, and then the trenches and the holes are filled with conductive material at the same time. In the dual damascene process, a via and a metal wiring pattern disposed over the via (i.e., the metal wiring layer is upper than the via) are formed at the same time. When the critical dimensions (CDs) of the trenches and/or the holes become smaller, it is more difficult to fill the conductive material into very narrow trenches and holes. Further, an overlay error between the via and the metal layer (formed over the via) in the dual damascene process may cause a high electrical resistance or an electrical short circuit. The via overlay error may also induce a smaller space between the metal wiring patterns on the same level, which may increase the risk of an electrical short circuit. In addition, the via overlay error combined with over-etching during formation of the hole for via may induce a cross layer tunnel and cause an electrical short circuit.

In the present disclosure, a novel process to form metal wiring patterns and vias by using a metal etching process, which can reduce an overlay error is provided. In particular, the present embodiments provide a self-aligned process between a via and a metal wiring pattern disposed below the via. More specifically, the vias are formed by a metal filling process, such as a damascene process, or an etching process; and the metal wiring patterns are formed by an etching process using an etching mask.

FIG.1is a cross sectional view of a semiconductor device including multiple wiring layers in accordance with embodiments of the present disclosure.

In some embodiments, transistors15, such as field effect transistors (FETs), are disposed over a substrate10. In some embodiments, the FET15includes a gate electrode15G, a source15S and a drain15D. In the present disclosure, a source and a drain are interchangeably used and may have the same structure. In some embodiments, the FET is a planar FET, a fin FET (Fin FET) or a gate-all-around (GAA) FET. In some embodiments, one or more interlayer dielectric (ILD) layers30are formed over the FETs.

In some embodiments, the substrate10may be made of a suitable elemental semiconductor, such as silicon, diamond or germanium; a suitable alloy or compound semiconductor, such as Group-IV compound semiconductors (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide, indium phosphide, indium antimonide, gallium arsenic phosphide, or gallium indium phosphide), or the like. The substrate10includes isolation regions in some embodiments, such as a shallow trench isolation (STI), located between active regions and separating one or more electronic elements from other electronic elements.

In some embodiments, multiple wiring layers Lx(x-th wiring layer) are formed over the FETs, where x is 1, 2, 3, . . . , as shown inFIG.1. Each of the wiring layers Lxincludes conductive wiring pattern Mxand vias Vx(via contacts) connected above the wiring patterns Mx, and each of the wiring layers Lx+1((x+1)-th wiring layer) includes conductive wiring pattern Mx+1and vias Vx+1connected above the wiring patterns Mx+1. Similarly, the wiring layers Lx−1includes conductive wiring pattern Mx−1and vias Vx−1connected above the wiring patterns Mx−1.

In some embodiments, when the wiring layers Lxinclude wiring patterns Mxextending in the X direction, the wiring layers Lx+1include wiring patterns Mx+1extending in the Y direction. In other words, X-direction metal wiring patterns and Y-direction metal wiring patterns are alternately stacked in the vertical direction. In some embodiments, x is up to 20. In some embodiments, the wiring layer Li can include the closest wiring patterns M1to the FETs15except for local interconnects. Each of the wiring layers Lxalso includes one or more ILD layers or inter-metal dielectric (IMD) layers. In other embodiments, the wiring layer can include vias formed above the metal wiring patterns.

FIGS.2A and2BtoFIGS.9A and9Bshow various views of the various stages of a sequential manufacturing operation of a semiconductor device in accordance with embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.2A-9B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. InFIGS.2A-9B, the “A” figures are perspective views and the “B” figures are cross sectional views along line X1-X1ofFIG.3A.

As shown inFIGS.2A and2B, a first conductive layer60, as a blanket layer, is formed over a first dielectric (ILD) layer50disposed over the substrate10. The first dielectric layer50includes one or more dielectric layers disposed over the FETs (not shown inFIGS.2A and2B) and include lower vias (via contacts)40. The lower vias40correspond to, for example, the vias Vx−1shown inFIG.1in some embodiments, or local interconnects directly disposed on the source and/or drain of the FETs.

In some embodiments, the first conductive layer60includes one or more layers of conductive material, such as Cu, Al, Ru, W, Co, Ti or Ta or an alloy thereof. In some embodiments, the thickness of the first conductive layer60is in a range from about 20 nm to about 200 nm. When the first conductive layer is made of a single metal element, the purity of the metal element is more than 99% in some embodiments. In some embodiments, the purity is less than 100% and the first conductive layer may include an impurity, such as carbon. In some embodiments, Ru, Co or Cu is used. In some embodiments, the first conductive layer60is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, plating or atomic layer deposition (ALD).

In some embodiments, the first ILD layer50includes one or more layers of silicon oxide, SiON, SiOCN, SiCN, SiOC, silicon nitride, an organic material, a low-k dielectric material, or an extreme low-k dielectric material.

Next, as shown inFIGS.3A and3B, a second ILD layer70is formed over the first conductive layer60. In some embodiments, the second ILD layer70is made of the same material as or different material from the first ILD layer50, and includes one or more layers of silicon oxide, SiON, SiOCN, SiCN, SiOC, silicon nitride, an organic material, a low-k dielectric material, or an extreme low-k dielectric material. In some embodiments, the thickness of the second ILD layer70is in a range from about 20 nm to about 200 nm.

Then, as shown inFIGS.3A and3B, one or more first vias (via contact)80are formed in the second ILD layer70. In some embodiments, the first vias80correspond to the vias Vx.

In some embodiments, a single damascene process is employed to form the first vias80. In the single damascene process, a resist pattern having holes corresponding to the vias80is formed over the second ILD layer70and the second ILD layer70is patterned by using plasma etching to form holes in the second ILD layer70. Then, one or more conductive layers are formed in the holes (a filling process) and over the upper surface of the second ILD layer70, and one or more planarization operation, such as a chemical mechanical polishing (CMP) process, is performed to remove excess portions of the conductive layers.

In some embodiments, the first vias80include one or more layers of a conductive material, such as Cu, Al, Ru, W, Co, Ti or Ta or an alloy thereof. In some embodiments, the first vias80includes one or more barrier or adhesion layers (e.g., Ti, TiN, Ta and/or TaN) and one or more body layers (e.g., Cu, Ru, Co, etc.). In some embodiments, the first vias80, in particular, the body layer, is made of the same material as or different material from the first conductive layer60. In some embodiments, the first conductive layer60includes Ru and the first vias80include Cu. In some embodiments, the first vias80include a body layer and a cap layer disposed on the body layer. In some embodiments, the cap layer is made of the same material as or a different material than a hard mask layer explained inFIGS.4A and4B. When the via, in particular, the body layer, is made of a single metal element, the purity of the metal element is more than 99% in some embodiments. In some embodiments, the purity is less than 100% and the material may include an impurity, such as carbon.

Then, as shown inFIGS.4A and4B, a hard mask layer90is formed over the second ILD layer70and the first vias80. In some embodiments, the hard mask layer90includes one or more dielectric materials (e.g., silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc) different from the second ILD layer70or one or more metal or metal nitride layers, such as Ta, Ti, TaN or TiN. In some embodiments, TiN is used. In some embodiments, the hard mask layer90is formed by CVD, PVD or ALD. In some embodiments, the thickness of the hard mask layer90is in a range from about 5 nm to about 100 nm, depending on the process requirements. In some embodiments, one or more additional ILD layers are formed before forming the hard mask layer90.

Further, as shown inFIGS.5A and5B, by using one or more lithography and etching operations, the hard mask layer90is patterned into a hard mask pattern92. In some embodiments, the hard mask pattern92corresponds to the wiring patterns MxofFIG.1. The hard mask pattern92is designed to align with the lower vias40.

In other embodiments, the hard mask pattern92is formed by using a single damascene process. In such a case, as shown inFIG.5C, a resist pattern having trench openings corresponding to the hard mask pattern92is formed over an additional ILD layer71formed on the second ILD layer70, the additional ILD layer71is patterned by using plasma etching to form trenches in the additional ILD layer71, one or more hard mask materials are formed in the trenches holes and the upper surface of the additional ILD layer71, and then a CMP process is performed. In some embodiments, the additional ILD layer71is made of the same material as or a similar material to the second ILD layer70. In other embodiments, no additional ILD layer is formed and the trenches are formed in the second ILD layer70and filled by the material for the hard mask pattern, as shown inFIG.5D.

As shown inFIGS.5A and5B, the hard mask pattern92does not necessarily fully cover part of the vias80. In some embodiments, two patterns are adjacent to each other along the X direction (pattern extending direction) with an end-to-end space D1. In some embodiments, the space D1is smaller than an end-to-end space D2between adjacent vias80along the X direction. In some embodiments, the space D1is equal or greater than to the space D2in a layout pattern (layout design).

Next, the second ILD layer70is patterned by one or more etching operations using the hard mask pattern92as an etching mask as shown inFIGS.6A and6B. In some embodiments, a plasma etching process is employed. The etching gas in the plasma etching includes one or more selected from the group consisting of carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), and octafluorocyclobutane (C4F8) or any proper reactants. In some embodiments, carbon dioxide (CO2) is further added to the plasma source gas. Other suitable etching gases may be used. In some embodiments, part of the vias80not fully covered by the hard mask pattern92also functions as the etching mask. The plasma dry etching substantially stops on the first conductive layer60.

FIG.6Cshows a cross sectional view after the second ILD layer70is patterned in case of the structure shown inFIG.5D.

Then, as shown inFIGS.7A and7B, the first conductive layer60is patterned by one or more etching operations using the hard mask pattern92, the vias80and the patterned second dielectric layer72as an etching mask. In some embodiments, a part of the upper surface of the vias80is exposed to the plasma (not covered by the hard mask pattern92). By this etching operation, the metal wiring patterns62corresponding to the wiring pattern MxofFIG.1are formed. In some embodiments, the etching gas in the plasma etching includes Cl2and/or O2, or any other suitable etching gas. The plasma dry etching substantially stops on the first ILD layer50.FIG.7Cshows a cross sectional view after the first conductive layer60is patterned in case of the structure shown inFIGS.5D and6C.

As shown inFIGS.7A and7B, when a via80is disposed at a line end of the wiring pattern62along the X direction, the line end of the wiring pattern62is confined by the via80rather than the line end of the hard mask pattern92. Similarly, when a via is laterally mis-aligned with the hard mask pattern92(i.e. overlay error between the hard mask pattern and the via), for example, when a part of the via80protrudes from the side of the hard mask pattern92along the Y direction in plan view, the side of the wiring pattern62after the etching of the first conductive layer60is confined by the via80rather than the side of the hard mask pattern92. In other words, the wiring patterns62are formed in a self-aligned manner with respect to the vias80, which are formed before the wiring patterns62are formed (patterned). Thus, in some embodiments, a protrusion65is formed at the side of the wiring pattern62just below the via80, which is mis-aligned. In some embodiments, the mis-alignment means that the center of the via does not match (or shifts from) the center of the wiring pattern in the width (short side) direction, in plan view.

Then, as shown inFIGS.8A-8D, the hard mask pattern92is removed by using a suitable etching operation.FIGS.8C and8Dare also perspective views from different angles. In some embodiments, a wet etching operation is used to remove the hard mask pattern92.FIG.8Eshow a plan view (a top view) without showing the second ILD layer72andFIG.8Fshows a plan view (a top view) without showing the second ILD layer72and the vias80. D3is an end-to-end space between the wiring patterns.FIG.8Gshows a cross sectional view after the hard mask pattern92is removed in case of the structure shown inFIGS.5D,6C, and7C.

As set forth above, the mis-aligned via80partially protruding from the side of the hard mask pattern92protects the underlying wiring pattern62forming a self-aligned structure. In some embodiments, a side face of the wiring pattern62includes a protrusion or a bump65, over which the via80is disposed.

Further, a third ILD layer100is formed, as shown inFIGS.9A and9B. In some embodiments, a blanket layer of one or more dielectric layers are formed in the trenches between and over the patterned second ILD layers72and the wiring patterns62, and a planarization operation, such as CMP, is performed to expose the upper surface of the vias80. In some embodiments, the third ILD layer100is made of the same material as or different material from the first and/or second ILD layers, and includes one or more layers of silicon oxide, SiON, SiOCN, SiCN, SiOC, silicon nitride, an organic material, a low-k dielectric material, or an extreme low-k dielectric material. As shown inFIGS.9A and9B, the wiring patterns Mxand the vias Vxare formed by the operations fromFIGS.2A and2B to9A and9B.FIG.9Cshows a cross sectional view after the third ILD layer100is formed in case of the structure shown inFIGS.5D,6C,7C and8D.

In some embodiments, the operations explained with respect toFIGS.2A and2B to9A and9Bare repeated to form the wiring structure including the wiring patterns Mx+1and the vias Vx+1.FIGS.10A and10Bshows the structure after the wiring patterns Mx+1and the vias Vx+1are formed. The wiring patterns Mx+1include wiring pattern112similar to the wiring pattern62and extending to a different direction from the wiring pattern62and the vias Vx+1includes vias120similar to the vias80disposed over the wiring patterns112. In some embodiments, a fourth ILD132layer is formed on the wiring patterns112and a fifth ILD layer140fills the spaces between the patterned fourth ILD layers132and the wiring patterns112.FIG.10Cshows a cross sectional view after the wiring patterns112, the vias120, the fourth ILD layer132, and the fifth ILD layer140are formed in case of the structure shown inFIGS.5D,6C,7C,8D and9C.

In some embodiments, a width of the wiring pattern62is in a range from about 5 nm to about 15 nm with a pitch of about 15 nm to 30 nm depending on the design and/or process requirements. In some embodiments, a diameter of the vias80is in a range from about 5 nm to about 15 nm with a minimum pitch of about 12 nm to about 30 nm along the X direction in which the wiring patterns62extend and a pitch of about 15 nm to about 30 nm along the Y direction, depending on the design and/or process requirements.

In some embodiment, the diameter of the via80is about same as the width of the wiring patterns62. The difference is more than 0 nm and less than +/−20% of the width of the wiring pattern62in some embodiments. In some embodiments, the minimum via pitch of the vias80along the Y direction is about the same as the pitch of the wiring patterns62, and the minimum pitch of the vias along the X direction is about the same as the pitch of the upper wiring patterns112(Mx+1).

In some embodiments, instead of repeating the operations explained with respect toFIGS.2A and2B to9A and9B, the wiring pattern114for wiring patterns Mx+1is formed by a single damascene process as shown inFIGS.11A and11B. In some embodiments, the wiring patterns114are embedded in trenches formed in an ILD layer145.

FIGS.12A to12Dshow various views of the various stages of a sequential manufacturing operation in accordance with embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.12A-12D, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

In some embodiments, as shown inFIG.12A, dummy vias80D are formed in the second ILD layer70. In some embodiments, a dielectric material different from the second ILD layer70or a semiconductor material is used for the dummy vias80D. In some embodiments, amorphous or poly silicon is used as the dummy vias80D. Then, by the operations explained with respect toFIGS.4A-9B, the patterned second ILD layer72and the wiring patterns62are formed similar toFIGS.9A and9B, as shown inFIG.12B. Subsequently, the dummy vias80D are removed to leave holes81as shown inFIG.12C. In some embodiments, when the dummy vias80D are made of silicon, the dummy vias80D can be removed by a wet etching operation using, for example, tetramethylammonium hydroxide (TMAH). Then, the holes81are filled with one or more conductive materials to form the vias80as shown inFIG.12D.

FIGS.13A and13Bshow a detailed view of the via80and the wiring pattern62according to an embodiment of the present disclosure. In some embodiments, the via80has a substantially columnar (cylindrical) shape. In some embodiments, the angle θ between the sidewall of the via80and the upper surface of the wiring pattern62is in a range from about 89 degrees to about 91 degrees. In some embodiments, the area and/or shape of the upper face of the via80is substantially the same as the area and/or shape of the bottom of the via80. The difference in area between the upper face and the bottom of the via80is about 1-5% of the upper surface. As shown inFIGS.13A and13B, the wiring pattern62below the via80may be confined or defined by the largest portion of the via80in some embodiments.

FIGS.13C and13Dshow a detailed view of the via80and the wiring pattern62according to an embodiment of the present disclosure. In some embodiments, the via80has a reverse tapered columnar shape. In some embodiments, the angle θ between the sidewall of the via80and the upper surface of the wiring pattern62is in a range from about 80 degrees to about 89 degrees and is in a range from about 82 degrees to about 87 degrees in other embodiments. In some embodiments, the area of the upper face of the via80is greater than the area of the bottom of the via80. The difference in area between the upper face and the bottom of the via80is about 1-20% of the upper surface. As shown inFIGS.13C and13D, the wiring pattern62below the via80may be confined or defined by the largest portion (the upper portion) of the via80in some embodiments.

FIGS.13E and13Fshow a detailed view of the via80and the wiring pattern62according to an embodiment of the present disclosure. In some embodiments, the via80has a tapered columnar shape. In some embodiments, the angle θ between the sidewall of the via80and the upper surface of the wiring pattern62is in a range from about 91 degrees to about 100 degrees and is in a range from about 93 degrees to about 97 degrees in other embodiments. In some embodiments, the area of the upper face of the via80is smaller than the area of the bottom of the via80. The difference in area between the upper face and the bottom of the via80is about 1-20% of the upper surface. As shown inFIGS.13E and13F, the wiring pattern62below the via80may be confined or defined by the largest portion (the bottom) of the via80in some embodiments.

The different shapes of the vias80depend on the etching results for forming holes in the first ILD layer in the single damascene process as explained with respect toFIGS.3A and3B.

FIGS.14A-14Dshow plan views (top views) of the vias80and the hard mask pattern92andFIGS.15A-15Dshow plan views (top views) of the corresponding wiring pattern62, according to embodiments to the present disclosure. As shown inFIGS.14A-15D, the wiring patterns62have the same shape of the combination (as a logical sum) of the hard mask pattern92and the vias80in plan view.

When a single or dual damascene process is used a certain via enclosure budget for CD and overlay error is needed. In some embodiments, the via enclosure budget may be estimated as EB=(D2−D1)/2, where D2is an end-to-end space between adjacent vias80, and D1is an end-to-end space between two patterns of the hard mask pattern92along the X direction. In the damascene process, EB is more than 0 nm.

In some embodiments of the present disclosure, as shown inFIG.14A, the EB is zero or can be negative as shown inFIG.14B. In some embodiments, a left margin D12of the EB is the same as a right margin D21of the EB as shown inFIG.14B. In other embodiments, D12is different (smaller or greater) than D21due to an overlay error between the vias80and the hard mask pattern92, as shown inFIG.14C. As shown inFIGS.14A-14C, the end-to-end space D1can be expanded or greater than the end-to-end space D2of the vias, and the patterning in the lithography operation for the hard mask pattern92(e.g., pattern margins in the layout) can have a greater tolerance.

In some embodiments, as shown inFIG.14D, the overlay error between the vias80and the hard mask pattern92is larger than the case ofFIG.14C. In some embodiments, the end of one of the hard mask patterns overhangs one of the vias80. In such a case, the wiring patterns62also have the same shape of the combination (the logical sum) of the hard mask pattern92and the vias80.

FIGS.16A to16Hshow various views of the various stages of a sequential manufacturing operation of forming the vias80in accordance with embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.16A-16H, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

In the process shown byFIGS.16A-16His substantially the same as a single damascene process. As shown inFIG.16A, the second ILD layer70is formed over the first conductive layer60. Then, in some embodiments, a resist layer, for example, a photo resist layer150is formed over the second ILD layer70as shown inFIG.16B, and then using a lithography operation, the resist layer is patterned into a resist pattern152having holes corresponding to the vias80as shown inFIG.16C. Then, the second ILD layer70is patterned by using plasma etching to form holes in the second ILD layer70as shown inFIG.16D. Then, the resist pattern152is removed as shown inFIG.16E. Then, one or more conductive layers80L are formed in the holes (a filling process) and the upper surface of the second ILD layer70, as shown inFIG.16F, and one or more planarization operation, such as a CMP process, is performed to remove excess portions of the conductive layers-, thereby forming vias80as shown inFIG.16G. In some embodiments, the vias80S and the first conductive layer60are made of the same material as shown inFIG.16H, and there is no significant interface between the vias80S and the first conductive layer60.

FIGS.17A to17Eshow various views of the various stages of a sequential manufacturing operation of forming the vias80in accordance with embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.17A-17E, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

In some embodiments, after the vias80are formed as shown inFIG.17A(the same asFIG.16G), an upper portion of the vias80is partially recessed as shown inFIG.17B. In some embodiments, the recessing amount (depth) is in a range from about 1 nm to about 20 nm. In other embodiments, the recessing amount is about 5% to 30% of the total thickness of the vias80. Then, one or more conductive layers160L are formed over the recessed vias80R and the upper surface of the second ILD layer70, as shown inFIG.17C, and one or more planarization operations, such as CMP process, is performed to remove excess portions of the conductive layers, thereby forming a cap conductive layer160as shown inFIG.17D. In some embodiments, the vias80S and the first conductive layer60are made of the same material as shown inFIG.17E, and there is no significant interface between the vias80S and the first conductive layer60. When the thickness of the cap conductive layer160is too large, a resistance of the vias increases and then the thickness of the cap conductive layer160is too small, a functionality of the cap conductive layer160(e.g., etching barrier) may be reduced. In some embodiments, the cap conductive layer160includes one or more metal or metal nitride layers, such as a Ta, a Ti, a TaN or a TiN layer. In some embodiments, TiN is used. In some embodiments, the conductive layer160L is formed by CVD, PVD, plating or ALD.

The operations explained with respect toFIGS.16E-16Hand/orFIGS.17A-17Ecan be applied to form the vias80in the holes81after the dummy vias80D are removed as shown inFIG.12C.

FIGS.18A and18Bshow cross sectional views of the wiring structure after the upper wiring layers are formed similar toFIGS.10A and10B, with a cap conductive layer160over the vias80R in accordance with embodiments of the present disclosure. In some embodiments, as shown inFIG.18A, the upper wiring pattern112is aligned with the vias80R with the cap conductive layer160and thus the upper wiring pattern112fully covers the cap conductive layer160. In other embodiments, the upper wiring patterns112are mis-aligned with the vias80R with the cap conductive layer160and a part of the cap conductive layer160is exposed from the wiring pattern112. In such a case, when the material of the cap conductive layer160and the material of the hard mask pattern used to form the upper wiring structures are the same, the etching of the conductive layer for the wiring pattern112substantially stops at the cap conductive layer160. Thus, the cap conductive layer160functions as an etching barrier or an etch stop layer. In some embodiments, the cap layer160is removed after planarization operation and before the next layer applied on the vias80R.

In the embodiments of the present disclosure, the wiring pattern is formed (patterned) after a via or a dummy via disposed on the wiring pattern is formed in an interlayer dielectric layer. In such a process, the wiring pattern is confined with the via, and thus even if there is an overlay error between a mask pattern (hard mask pattern and/or resist pattern) and the via, the patterned wiring pattern has a protrusion below the via, which secures the connection between the via and the wiring pattern.

It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages.

In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming patterned second ILD layers and first wiring patterns, after the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layers and the first wiring patterns. In one or more of the foregoing or following embodiments, the first conductive layer includes one of Co, Cu or Ru. In one or more of the foregoing or following embodiments, the via includes one of Co, Cu or Ru. In one or more of the foregoing or following embodiments, the first conductive layer and the via are made of different materials. In one or more of the foregoing or following embodiments, the hard mask pattern is in contact with an upper surface of the via. In one or more of the foregoing or following embodiments, a part of the upper surface of the via is exposed from the hard mask pattern, and the via is also used as the etching mask. In one or more of the foregoing or following embodiments, the hard mask pattern includes TiN. In one or more of the foregoing or following embodiments, the first ILD layer comprises a lower via, and the hard mask pattern includes a pattern aligned with the lower via. In one or more of the foregoing or following embodiments, the via includes a body part and a cap layer disposed on the body part made of a different material than the body part. In one or more of the foregoing or following embodiments, the hard mask pattern is made of a same material as the cap layer.

In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a dummy via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming patterned second ILD layers and first wiring patterns, after the patterning, the hard mask pattern is removed, a third ILD layer is formed between the patterned second ILD layers and the first wiring patterns, and the dummy via is replaced with a conductive via. In one or more of the foregoing or following embodiments, the dummy via includes a different material than the second ILD layer and the first conductive layer. In one or more of the foregoing or following embodiments, the dummy via includes amorphous or poly silicon. In one or more of the foregoing or following embodiments, the dummy via includes a dielectric material. In one or more of the foregoing or following embodiments, the first conductive layer and the conductive via are made of a same material. In one or more of the foregoing or following embodiments, a second wiring pattern is further formed over the conductive via.

In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, the semiconductor device includes a lower wiring pattern, an upper wiring pattern and a via connecting the lower wiring pattern and the upper wiring pattern. In the method, the via is formed in a dielectric layer, and after the via is formed, the lower wiring pattern disposed below the via is formed. In one or more of the foregoing or following embodiments, wherein when the lower wiring pattern is formed, a blanket layer of a conductive material is formed before the dielectric layer is formed, and the blanket layer is patterned by a plasma dry etching. In one or more of the foregoing or following embodiments, the blanket layer is patterned by using a hard mask pattern disposed over the dielectric layer. In one or more of the foregoing or following embodiments, the hard mask pattern is formed by using a damascene process.

In accordance with another aspect of the present disclosure, a semiconductor device includes transistors disposed over a substrate, and a plurality of wiring layers disposed over the transistors. One of the plurality of wiring layers includes a wiring pattern and a via connected to an upper surface of the wiring pattern, and the wiring pattern includes a lateral protrusion protruding from a side face of the wiring pattern. In one or more of the foregoing or following embodiments, a part of the via is disposed on the lateral protrusion. In one or more of the foregoing or following embodiments, the via and the wiring pattern are made of a same material. In one or more of the foregoing or following embodiments, the wiring pattern includes one of Co or Ru. In one or more of the foregoing or following embodiments, the via includes a body layer and a cap layer disposed over the body layer and made of a different material than the body layer. In one or more of the foregoing or following embodiments, the body layer includes at least one of Cu, Al, Ru, W, Co, Ti or Ta, and the cap layer is made of TiN. In one or more of the foregoing or following embodiments, the via has a tapered columnar shape having a top smaller than a bottom. In one or more of the foregoing or following embodiments, an angle between a side face of the via and an upper surface of the wiring pattern is in a range from 91 degrees to 100 degrees. In one or more of the foregoing or following embodiments, the via has a reverse tapered columnar shape having a top larger than a bottom. In one or more of the foregoing or following embodiments, an angle between a side face of the via and an upper surface of the wiring pattern is in a range from 80 degrees to 89 degrees.

In accordance with another aspect of the present disclosure, a semiconductor device includes transistors disposed over a substrate, and a plurality of wiring layers disposed over the transistors. One of the plurality of wiring layers includes a first wiring pattern, a second wiring pattern, a first via connected to an upper surface of the first wiring pattern, and a second via connected to an upper surface of the second wiring pattern. The first and second wiring patterns extend in a first direction and are aligned with each other in the first direction. The first via is disposed at an end of the first wiring pattern and the second via is disposed at an end of the second wiring pattern. An end-to-end space between the first and second vias is equal to an end-to-end space between the first and second wiring patterns in the first direction. In one or more of the foregoing or following embodiments, the end of the first wiring pattern is confined by the first via and the end of the second wiring pattern is confined by the second via. In one or more of the foregoing or following embodiments, the first and second vias are made of a different material than the first and second wiring patterns. In one or more of the foregoing or following embodiments, the via includes a body layer and a cap layer disposed over the body layer and made of a different material than the body layer. In one or more of the foregoing or following embodiments, the body layer includes at least one of Cu, Al, Ru, W, Co, Ti or Ta, and the cap layer is made of TiN.

In accordance with another aspect of the present disclosure, a semiconductor device includes transistors disposed over a substrate, and a plurality of wiring layers disposed over the transistors. The plurality of wiring layers includes an n-th wiring layer and an (n+1)-th wiring layer. The n-th wiring layer includes a first wiring pattern and a first via connected to an upper surface of the first wiring pattern. The (n+1)-th wiring layer includes a second wiring pattern and a second via connected to an upper surface of the second wiring pattern. The first wiring pattern includes a lateral protrusion protruding from a side face of the first wiring pattern below the second via. In one or more of the foregoing or following embodiments, the second via is mis-aligned with the first wiring pattern. In one or more of the foregoing or following embodiments, the second via includes a body layer and a cap layer disposed over the body layer and made of a different material than the body layer. In one or more of the foregoing or following embodiments, the second wiring pattern is mis-aligned with the second via. In one or more of the foregoing or following embodiments, a part of an upper surface of the cap layer is exposed from the second wiring pattern.

The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.