Patent ID: 12231136

It should be noted that the figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments

DETAILED DESCRIPTION OF EMBODIMENTS

As mentioned above, type I PLLs differ from type II PLLs by the absence of a phase-error integration block in the PLL loop, other than the voltage controlled oscillator (VCO). This is axiomatic, since one definition of the “type” of a PLL is that it corresponds to the number of integrators in the loop: for example, there may be just the VCO for a type-I PLL and the VCO plus one other, for a type-II PLL. Thus there can be a variable phase error between the phase detector reference and the output signal—which is returned as the feedback signal. By avoiding a phase-error integration block, the above-mentioned disadvantages associated with using type II PLLs may be reduced or avoided: in particular faster locking times and/or a better trade-off between noise and power may be achievable, and the PLL occupies a small area on a die.

However, there are some applications, such as PDE or narrowband ranging the mentioned above for which a variable phase error is not generally acceptable. For such applications which require “phase coherence” or “phase memory” it would generally be considered that type I PLLs are not appropriate. As a specific example, within PDE it is required to manage a role swap—that is to say the transceiver switching between a receive mode to a transmit mode with associated frequency change—for two-way PDE without introducing a phase error, and similarly for one-way PDE it is required to be able to manage frequency hops again without introducing phase error.

The present inventors have appreciated that it is possible to mitigate or compensate the dynamic frequency error which is introduced when hopping, or role-swapping, between frequencies; thereby it may be possible to reduce or overcome the disadvantages of type-I PLLs, and facilitate their use in a wider range of applications. In particular, it may thereby be possible to benefit from other advantages of type I PLLs, such as speed of convergence and lower noise. The phase error introduced through a frequency hop may be defined as a “transient phase error”, which converges to, and results in a “steady state phase lag” which will be described in more detail hereinbelow, and may be determined or estimated, again as will be detailed hereinbelow.

Considering firstFIG.1, this shows a type I PLL configured for initial phase locking. The PLL100comprises a phase detector (PD)110into which is input a reference signal (REF)105during normal operation. An output VPDfrom the phase detector110is input into a low pass filter (LPF)120. However during the initial phase, this connection is opened—such that the loop is not closed. Instead a pre-charge voltage VPCHis input to the lowpass filter120from a pre-charge unit130. High frequency components are filtered out by the low-pass filter120, which passes a tuning voltage VTUNEto a VCO140. The output from the VCO is both provided as output (OUT)160and fed back as a feedback signal. The feedback signal is divided by a factor (which may be a factor of 10 as shown) in a feedback divider150, and provided as the second, FBK, input to the phase detector110.

During the initial phase, known as an open-loop VCO calibration, the VCO is brought to a self-resonance frequency—which is generally designed to be close or as close as possible to the target PLL frequency. The skilled person will appreciate that how this is achieved is dependent on the specific implementation of hardware used. For instance, there may a capacitor bank controlled by a calibration algorithm. In this phase VTUNE=VPCH; this is typically chosen to be half the PLL supply voltage (VDD-PLL), to maximise the PLL acquisition range. Once the open-loop calibration ends, the loop is closed, and the VCO control voltage VTUNEis set by the PLL to drive the VCO to the correct frequency. In normal operation, the phase detector110produces an output that is proportional to the phase difference between the two inputs signals REF and FBK. Thus VPD=Kϕ·(ϕREF−ϕFBK) where ϕREFand ϕFBKare the phases of the signals REF and FBK respectively and Kϕis the Phase Detector gain (in V/rad).

At the end of the open loop calibration, the frequency of the VCO will differ from the target PLL by a frequency error: FVCO=FPLL+FERR; where FPLLis the target PLL frequency, FERRis the frequency error with respect to the target PLL output frequency and FVCOthe VCO self-resonance frequency. Once the loop is closed, the PLL drives the VCO frequency to the desired value, by acting on the VCO control voltage, until the VCO frequency achieves the locked frequency FVCO-LCK=FPLL. The VCO control voltage then, VTUNE-LCK, will be related to the pre-charge voltage VPCH, through:
VTUNE-LCK=VPCH−FERR/KVCO,
where KVCOis the VCO gain in Hz/V.

Consider the example above in which the pre-charge voltage is half the supply voltage: VPCH=VDD-PLL/2, and assume that the Phase Detector is implemented by a set-reset (SR) latch:
VPD=VDD-PLL/2π·(ϕREF−ϕFBK) andKϕ=VDD-PLL/2π.

If the initial frequency error is null (FERR=0), then VTUNE-LCK=VPCH=VDD-PLL/2 and (ϕREF−ϕFBK)=π. However, is the frequency error is not null, then:
VTUNE-LCK=VPCH−FERR/KVCO=VDD-PLL2−FERR/KVCO.
From which it follows that
(ϕREF−ϕFBK)=π−FERR/(Kϕ·KVCO)=π−Ferr·2π/(VDD-PLL·KVCO).

Since the phase of the feedback signal is equal to the phase of the PLL output signal divided by N, then also the phase of the PLL output signal depends on the VCO frequency error.

Now considering a frequency hop of Δf whilst the PLL is operating—i.e. in closed loop; the resulting relative phase shift (in steady state) at the Phase Detector inputs is:
Δϕ=Δf(Kϕ·KVCO)=Δf·2π/(VDD-PLL·KVCO).

Due to its limited bandwidth, the PLL will take some time to arrive to steady state, but once in steady state a phase shift at the phase detector feedback input is related to a phase shift on the LO (local oscillator—in this example the VCO) signal.

Before returning to a circuit analysis, the reader is directed toFIG.2which is another block diagram depiction of a generic divider-based PLL200, which can be implemented either as an analog or digital circuit, and illustrates two modulation ports for modulation the frequency of the PLL: a low port modulation and a high port modulation. Similar to the PLL shown inFIG.1, the loop comprises a phase detector210, the output of which is input to a loop filter220. The output of the loop filter220is input to an oscillator240, in this instance implemented as an RF oscillator. A frequency counter245counts the oscillator output. There is included between the oscillator and the output260an optional divide-by-x divider250. Feedback is provided from the output, through a divide by N fractional divider255, back to the phase detector210. Along with the feedback, the phase detector has a second input REF-OSC205. The fractional divider250has as an input a (in this case digital) signal output from a Sigma Delta modulator270. The input and Sigma Delta modulator is the sum of a target frequency280and a low port modulation input, if any, as shown at285. The RF oscillator240can be controlled by a course tuning block235; it can be further directly by a high port modulation290provided by a high port modulation input295.

A theoretical analysis of the transfer function of the PLL, over a Laplace domain s can be made, in conjunction withFIG.3, which shows a generic flow graph of a divider-based analog PLL, such as that shown inFIG.2, including a divide-by-N divider in the feedback path, and the option of providing both “low-port injection” and “high-port injection”—which will be explained in more detail hereinbelow. It can be shown that, considering firstly the effect of controlling using VFM1corresponding to a frequency modulation control signal through the Low-Port Modulation path285,270:

ωL⁢OVF⁢M⁢1⁢(s)=1NL⁢O·-G1(s)·K0′·Kϕ·H⁡(s)·Ni⁢n·N·sNi⁢n·N·s+K0′·Kϕ·H⁡(s),
and secondly the effect of controlling using VFM2corresponding to a frequency modulation control signal through the High-Port Modulation path290

ωL⁢OVF⁢M⁢2⁢(s)=1NL⁢O·G2(s)·Km⁢o⁢d⁢0′·Ni⁢n·N·sNi⁢n·N·s+K0′·Kϕ·H⁡(s)
where: s is the Laplace variable; Ninis a fixed division ratio (if any) in front of the feedback divider, and N is the division ratio of the feedback divider. Finally, G is a scaling or gain factor in the Laplace domain.

Since in the present instance VFM1=FFM2=VFM, and G1(s)=G2(s), this results in an all-pass transfer function (i.e. a transfer function allowing for injections signals from both the low pass modulator and the high pass modulator, VFM1and VFM2respectively), for the combination of high port modulation HPM and low port modulation LPM:

fL⁢OVF⁢M⁢(s)=1⇔{LPM⁡(s)=fL⁢OVF⁢M⁢1⁢(s)=K0′·Kϕ·H⁡(s)Nd⁢i⁢v·s+K0′·Kϕ·H⁢(s)=11+Nd⁢i⁢vK0′·Kϕ·H⁡(s)·s→L⁢P⁢FHPM⁡(s)=fL⁢OVF⁢M⁢2⁢(s)=Nd⁢i⁢v·sNd⁢i⁢v·s+K0′·Kϕ·H⁢(s)=Nd⁢i⁢vK0′·Kϕ·H⁡(s)·s1+Nd⁢i⁢vK0′·Kϕ·H⁡(s)·s→H⁢P⁢F

In the above relation, Ndiv=Nin·N, K′0=K0/NLOin, K′mod0=Kmod0/NLOin, and NLoinis the ratio of the (optional) LO divider which is inside the loop between the VCO and the feedback divider, shown as “/x”250inFIG.2and the block “1/NLoin” inFIG.3. It will be appreciated that the above analysis can be broadened to include generic divider-based digital PLL and a generic counter-based digital PLL. In all cases, it results that a similar transfer function exists and a similar dependence on the open-loop gain K′0·Kϕand feedback Ndivloop exists. Thus the above analysis, and hence embodiments of the present disclosure, are not restricted to one single kind or type of type-I PLL.

Considering next a frequency hop (which, as discussed above, may be either for role swap from receive to transmit, or for a channel change), a Δf step will be applied to VFM1leading to Δf/s.

The step response of the LPM in the output frequency and phase domains are:

fL⁢O(s)=Δ⁢fs·11+Nd⁢i⁢vK0′·Kϕ·H⁡(s)·s⁢andϕL⁢O(s)=2⁢πs⁢fL⁢O(s)

Comparing those responses to an ideal PLL, that is to say one in which the transfer function under low port modulation is unity: LPMideal(s)=1, it can be written:

Δ⁢ϕL⁢O(s)=2⁢π·Δ⁢fs2·(11+Nd⁢i⁢vK0′·Kϕ·H⁡(s)·s-1)=-2⁢π·Δ⁢fs·Nd⁢i⁢vK0′·Kϕ·H⁡(s)1+Nd⁢i⁢vK0′·Kϕ·H⁡(s)·s

Applying the Final Value Theorem to obtain the steady state values gives:

Δ⁢ϕLO,steady=limt→+∞Δ⁢ϕL⁢O(t)=lims→0s·ΔϕL⁢O(s)=-2⁢π·Δ⁢f·Nd⁢i⁢vK0′·Kϕ

That is to say, the steady state phase lag, SSPLPLLis a function of Ndiv, and K′0·Kϕ, since the SSPL may be defined as:

S⁢S⁢P⁢LPLL=Δ⁢ϕLO,steady2⁢π·Δ⁢f=-Nd⁢i⁢vK0′·Kϕ

A phase shift, having a value:

-2⁢π·Δ⁢f·NdivK0′·Kϕ
is thus introduced by the frequency hop, and is proportional to the frequency step and inversely proportional to the PLL open loop gain. The present inventors have appreciated that this relationship can be exploited to enable use of a type-I PLL, in application where the phase should be well-controlled.

In the case respectively of a set-reset-latch-based or XOR-gate-based Phase Detector, the above analysis is modified such the phase shift is

-2⁢π·Δ⁢f·NdivKVCO·VD⁢D⁢and-2⁢π·Δ⁢f·Nd⁢i⁢v2·KVCO·VD⁢D,
respectively.

Taking as a specific and non-limiting example, a set-reset-latch-based PD, and a 1 MHz frequency step, for a Ndivof 75.625, KVCO=86 MHz/V, and VDD=0.918 V, a phase shift of −344.85° is obtained. Using these parameters, the PLL SSPL in this case is equal to −957.909 ns.

Turning now toFIGS.4and5,FIG.4shows the response of an example PLL to a 1 MHz frequency step, for an ideal frequency modulator shown at410, that is to say the open-loop VCO response measured as the relative phase to the initial carrier phase, measured in degrees, on the y-axis or ordinate against time in seconds on the x-axis or abscissa. In addition to the open-loop VCO response410, the figure shows a simulated response of a real system at420, and a first order approximation at430.

FIG.5plots, for the same example, the relative phase shift to the same step response, with the relative phase shift in degrees plotted on the y-axis or ordinate, against time on the x-axis or abscissa. The simulated real circuit is shown at520along with the first order approximation at530.

As can be seen inFIG.4, the SSPL PLL for this example is approximately 1 μs, and ΔϕLO,steadycan be seen in bothFIGS.4and5to be approximately 345°.

Returning to the analysis, and now focussing on the digital part of the PLL implementation: in addition to the steady state phase lag from the PLL, the digital data-path latency or delay to apply the frequency step (Digital Sigma Delta modulator+PLL main divider) must be taken into account. This will be implementation dependent, and denoted —NDig·TPLL,Ref, where NDigis a counter value of the digital path latency or in other words, a number of clock cycles for an input sample to be available at the system output, TPLL,Refis the PLL reference clock period and is equal to 1/(Mref·fXO) where fxo is the frequency of the crystal oscillator (in embodiments in which one is used), or another clock at the PLL input, and Mref is the PLL input clock multiplication ratio in case of a frequency multiplier is used in front of the phase detector. (it will be appreciated that this could, alternatively, be a divider or even a cascade of one and/or several multipliers/dividers.

Then due to the type I operation, there is a phase offset in between the PLL reference clock running at Mref·fXOand the feedback clock. Typically, the feedback clock is an image of the clock of the delta-sigma modulator (DSM) in the feedback divider part of the loop, but is NOT directly the DSM clock. The phase offset depends on the initial frequency error in open loop for the pre-charge voltage Vpch, the frequency hop and the nominal phase offset required by the Phase Detector, which is eitherVPCH·π/VDDfor a XOR-based phase detector, orVpch·2π/VDDfor a SR-based phase detector.
which leads to
(FERR−Δf)/(KVCO·Kϕ)−Vpch·(2π/α)/VDD,
where α=1 for a XOR phase detector, and α=2 for a SR-based phase detector.

This phase offset can be converted to a delay:
((FERR−Δf)/(2π/α)·KVCO·Kϕ)−Vpch/VDD)·TPLL,Ref

There is also a time delay in between the DSM clock rising edge and feedback clock edge which is also implementation dependent, and denoted by −Δtclk

The total SSPL is thus:

SSPL=-Ndiv+Δ⁢f-FE⁢R⁢RMr⁢e⁢f·fX⁢Oa⁢π·KVCO·Kϕ-Vpch/VD⁢D+ND⁢i⁢gMr⁢e⁢f·fX⁢O-Δ⁢tc⁢l⁢k

And the total corresponding phase shift is:

Δ⁢ϕL⁢O,s⁢t⁢e⁢a⁢d⁢y=2⁢π·Δ⁢f(-Nd⁢i⁢v+Δ⁢f-FE⁢R⁢RMr⁢e⁢f·fX⁢Oa⁢π·KVCO·Kϕ-Vpch/VD⁢D+ND⁢i⁢gMr⁢e⁢f·fX⁢O-Δ⁢tc⁢l⁢k)

It can be observed that the first term depends on analog variables and the two last terms are constant and deterministic. Thus the two last terms can be known or removed by performing a so-called “zero-metre distance calibration” of PDE-based algorithm, in other words a calibration ofr the case in which there is no separation between the transmitter and receiver. The first term on the other hand requires a way to estimate the unknowns FERR, KVCOand Kϕ

Parameter Estimation

FERRcan be estimated based on the best-achieved, or best achievable, frequency error during VCO coarse tune calibration (that is to say, when using the coarse tuning bank235to adjust the oscillator RFOSC240). Alternatively, it can be estimated based on an acquisition using a ripple counter or similar apparatus which is able to estimate the open-loop VCO frequency.

To estimate the PLL gain (KPLL) several alternatives will be readily appreciated. One is to use a method which directly allows computation of a ratio between a phase delta and a frequency delta, such as 1/(Kϕ·K0)=Δϕ/Δf.

Another is to use a method which exploits gain estimator results such as, for a DPLL, 1/(Kϕ·K0)=1/K̆TDC·1/(2π·K̆DCO).

A specific example for an analog PLL is as follows: choose a pair of VCO pre-charge values equally distributed around default pre-charge voltage but not too far away to avoid seeing varactor non-linearity, e.g. V1=0.4·VDDand V2=0.6·VDDfor a default of 0.5·VDD; measure VCO frequencies through a frequency-calibration (FCAL) or Ripple counter for both pre-charge voltages, which yields f1& f2respectively for V1& V2; and then use the approximate relationship:

KPLL=Kϕ×K0=α⁢VDD/(2⁢π)×2⁢π⁡(f2-f1)/(V2-V1)=α⁢VDD(f2-f1)/(V2-V1)=α⁡(f2-f1)/0.2)
where, α is a constant which depends on the PD implementation: e.g. α=1 for Set-Reset latched-based PD, α=2 for XOR-gate PD)

In digital PLLs: estimators for the PLL gain (Kϕ·K0) parameter are typically directly available: Time-to-Digital Converters (TDC) and DCO gains can be generally estimated using Least-Mean-Square (LMS)-based or similar algorithms, respectively providing 1/K̆TDCand 1/K̆DCO, leading to a direct availability of the loop gain parameter through:
1/(Kφ·K0)=1/K̆TDC·1/(2π·K̆DCO)
Computation of SSPL and Total Phase Shift.

From FERRand KPLLestimation, it is possible to compute SSPL as discussed above:

SSPL=-Ndiv+Δ⁢f-FERRMref·fXOKPLL,

And the total phase shift that needs to be compensated is, correspondingly:

ΔϕLO,steady=2⁢π·Δ⁢f(-Ndiv+Δ⁢f-FERRMref·fXOKPLL),
where Δf is the frequency jump resulting from either the role swap in 2-way PDE, or from a frequency hop for in 1-way PDE.
Compensation Through LPM

According to one or more embodiments of the present disclosure, it is possible to compensate for a phase change in the type-I PLL which re-results from a frequency change, by providing compensation into the low port modulator LPM

The PLL fractional frequency may be written as kfrac*(Mref*fXO).

Applying an offset:

kfrac=ΔϕLO,steady2⁢π·NLO

For a single PLL reference period results in a VCO frequency shift ΔfVCO, where:

Δ⁢fVCO=ΔϕLO,steady2⁢π·NLO·Mref·fXO,

Which is equivalent to a LO frequency shift:

Δ⁢fLO=ΔϕLO,steady2⁢π·Mref·fXO,

Over a single reference period, which corresponds, in the phase domain, to a phase shift of

ΔϕLO,shift=-2⁢π·Δ⁢fLOMref·fXO=-Δ⁢ϕLO,steady.

That is to say, the phase shift is perfectly compensated.

FIG.6illustrates a simulation of the impact of such phase correction by an impulse insertion in the LPM, by plotting phase on the Y-axis alternate against time on the x-axis or abscissa. Plot610shows the change of phase resulting from a frequency step introduced at moment605, without any correction. In contrast by including an impulse at the same moment that the frequency changes, the phase re-settles to the original value, as shown by plot620.

This is shown in more detail inFIG.7.FIG.7shows a simulated response of a PLL to a frequency hop. The top row of graphs (i), (ii) and (iii) show the response without any compensation, at710,740and770respectively. The middle row of graphs (iv), (v) and (vi) show the response when a compensation ΔϕLO,shiftis applied, delayed after the frequency hop, both for an ideal PLL at720,750,780respectively, and for a real PLL at725,755and785respectively. The lower row of graphs (vii), (viii) and (ix) show the response,730,760and790respectively, when the same compensation ΔϕLO,shiftis applied, at the same time as the frequency hop. For each row, the left graph shows the VCO frequency plotted against time. The middle graph shows the normalised phase of an ideal PLL compared with the real PLL, again plotted against time on the same scale, and the right graph shows the normalised phase error, once again plotted against time on the same scale.

Looking first at the frequency response over time (i), (iv) and (vii), the frequency change resulting from the frequency hop is shown at714,744and774respectively. On each plot the phase locking is also shown on the far left at712,742,772, once the open loop calibration discussed above is concluded.

Looking now at the normalised phase response of time, it can be seen that the phase is initially normalised to 0, until the frequency hop is applied. The change in frequency resulting from the frequency hop results in a steadily increasing phase, which is the same for all three plots with respect to the ideal PLL. However, looking at the response of the real PLL with no compensation in plot (ii), it can be seen that the increasing phase lags that of the ideal PLL, shown at725, by a constant amount. In contrast, looking at the middle plot (v) in which the compensation is applied, delayed with respect to the frequency hop, it can be seen that the phase of the real PLL750lags that of the ideal PLL75until the compensation is applied, as shown at A. Thereafter, the compensated phase of the real PLL overlays that of the ideal PLL. Looking now at the lower plot (viii) which shows the normalised phase for a PLL where the conversation is applied at the same time as the frequency hop, here the normalised phase of the real PLL780overlays that of the ideal PLL785for the whole period.

Finally, looking at the right graphs which show the normalised phase error, the top plot at (iii) shows, after the phase settles, zero phase error until the frequency hop is applied at734. Thereafter the phase settles to a steady state phase error (corresponding to the steady state phase lag discussed above). The middle plot (vi) shows the phase error, which again is 0 until the frequency hop is applied, at which moment the phase error becomes negative, and settles to a steady state phase error until the compensation is applied at moment A, at which time the phase error arises, as shown at766, back to a zero phase error. The lower plot (ix) shows the consequence of applying the compensation at the same time as the frequency hop. Again, once the PLL has settled, the phase error790is 0 until the frequency hop is applied. However, in this case the compensation supplied at the same time such that after a short perturbation showed at798, the phase error returns to 0.

The offset applied to the LPM may be provided as an impulse (that is a 1-cycle correction) or the correction may be applied over multiple cycles provided the product of the correction and the number of clock cycles is equal to the desired correction

Compensation Using HPM

According to one or more embodiments of the present disclosure, it is possible to compensate for a phase change in the type-I PLL which re-results from a frequency change, by providing a frequency offset into the high port modulator HPM. In the example of a digital PLL, the oscillator is a digitally controlled oscillator (DCO), and the HPM frequency offset applied needs to be equal and opposite in polarity at the voltage controlled oscillator (VCO) to the frequency change that has been commanded from the PLL (using the programmed fractional division factor). Also note that this offset may be provided as a step-change, or introduced gradually, for instance as a linear or exponential ramp.

The theory underlying this correction will now be considered:

A PLL frequency is typically applied by changing the applied fractional numerator value to the low port modulation LPM Sigma-Delta modulator, for example, for a low IF receiver, transitioning between TX and RX modes at the same channel frequency, the PLL is offset by the value of the IF frequency. This change in frequency results in a constant phase change at the PLL output (assuming that everything else remains constant), as will now be shown, which can be compensated by providing an offset into the HPM.

In the case where two injection points are well matched in gain and delay, and there is no impact from the low pass filter (in other words the anti-aliasing cut-off frequency can be ignored), then:

fLOVF⁢M⁢(s)=1⁢and⁢ϕLOVF⁢M⁢(s)=2⁢πs,
which corresponds to an ideal wideband modulator.

If we apply a step at the HPM after the LPM frequency change step the step response of the HPM transfer function can be studied:

fLO(S)=Δ⁢fs·NdivK0·Kϕ·H⁡(s)·s1+NdivK0·Kϕ·H⁡(s)·s⁢andϕLO(s)=2⁢πs⁢fLO(s).

Applying Final Value Theorem to obtain the steady state phase change results in:

ΔϕLO,shift=limt→+∞ϕLO(t)=lims→0s·ϕLO(s)=2⁢π·Δ⁢f·NdivK0·Kϕ=-ΔϕLO,steady

From this it is seen that the magnitude of the phase change required to be applied via the HPM is proportional to the frequency shift Δf, and inversely dependent on the open-loop gain K0Kϕ. Seen from another viewpoint, this is equivalent to saying that the PLL phase change introduced by the change in the target frequency may be compensated by effectively changing the fixed VCO tank capacitance which causes the PLL loop to settle at the same operating point as it did before the frequency change. In a two-port PLL modulator, the PLL HPM port is a calibrated input that allows for introduction of a calibrated tank capacitance to the VCO core, that can be used to “perfectly” compensate for the phase change resulting from the LPM instituted PLL frequency. Put another way, the introduced HPM frequency offset compensation results in a PLL phase change (which is a function of Δf, Ndiv, K0, Kϕ), which nulls another phase change due to a commanded PLL frequency change. It will be appreciated that compensation using this technique is dependent on the programmable range of the HPM-typically this range is limited to a few megahertz which would normally be adequate to compensate for an IF frequency change resulting from a TX to RX transition. It will also be appreciated that the accuracy of the compensation could be impacted by the HPM resolution and calibration accuracy.

A specific example with typical values, will now be considered. In this instance, a 2.4 GHz Bluetooth-LE (BLE) radio with a receiver IF frequency of, FIFof −1 MHz, and a PLL feedback divider, x, of 2. Then for BLE channel19, the TX LO (or direct launch) frequency is 2.44 GHz, and the (low-IF) RX LO frequency is 2.439 GHz.FIG.8shows, on the left-hand side, case A in which there is no compensation, and case B shown on the left the right-hand side, which includes an impulse modulation on HPM of −2*FIFthat is to say 2*1 MHz.

The upper two traces of case A show the phase810and820of the transmit and receive signals at the PLL output. And the lower two traces830and840show the frequency of the VCO during transmit and receive, without the compensating HPM modulation. On the right-hand part of the figure, B shows the same transmit and receive frequency that the VCO at835and845respectively; however by including the above compensation at the HPM, the transmit and receive phase815and825respectively are seen to overlay each other, showing effectively perfect compensation.

Phase-Correction in PDE Calculation

The above examples have discussed compensating the PLL for the phase difference introduced (either by a phase-domain correction at LPM, or a frequency correction for HPM) by the frequency changes. In other embodiments, the PLL is not compensated, but the knowledge of the phase difference is used in the PDE calculation itself. This can be done for each of one-way PDE and two-way PDE.

Turning first to two-way PDE:

In two-way PDE between two devices A and B separated by a distance r, the estimated “phase distance”, d, can be estimated as:

d=r+c-4⁢π⁢Δ⁢f⁢[(∅TXB⁢2-∅RXB⁢2+∅TXA⁢2-∅RXA⁢2)-(∅TXB⁢1-∅RXB⁢1+∅TXA⁢1-∅RXA⁢1)]

Where:Δf=f2−f1ØTXAnand ØRXAnare the phases of the device A LO at frequency fnin TX and RX mode respectivelyØTXBnand ØRXBnare the phases of the device B LO at frequency fnin TX and RX mode respectively

Since ØTXMn−ØRXMn=−ΔϕLOMn,steadyfor each of M=A, B and

n=1,2=-2⁢π·fIF(-Ndiv+Δ⁢f-ferrorMref·fXOKPLL),ord=r+c4⁢πΔ⁢f[(ΔϕLOB⁢2,steady+ΔϕLOA⁢2,steady)-(ΔϕLOB⁢1,steady+ΔϕLOA⁢1,steady)],
which is of the form:
d=r+errorΔØ,
where the error term errorΔϕ, is expressed in terms of the phase shift, and thus can be estimated using the Steady State Phase Lag concept, discussed above.

A similar analysis applies to one-way PDE. In this case:

d=r+c-2⁢πΔ⁢f⁢(∅TXB⁢2+∅TXB⁢1-∅RXA⁢1-∅RXA⁢2)
Knowing that:

∅TX⁢2+∅TX⁢1=ΔϕLOTX,steady=-2⁢πΔ⁢f(-Ndiv+Δ⁢f-ferrorMref·fXOKPLL)⁢and⁢that∅RX⁢2+∅RX⁢1=ΔϕLORX,steady=-2⁢πΔ⁢f(-Ndiv+Δ⁢f-ferrorMref·fXOKPLL)
Gives:

d=r+c-4⁢π⁢Δ⁢f⁢(ΔϕLOTX,steady-ΔϕLORX,steady)

Once more, this is of the form:
d=r+errorΔØ,
where the error terms errorΔϕ, is expressed in terms of the phase shift, and thus can be estimated suing the Steady State Phase Lag concept.

Thus using the determined total phase shift in a phase-based distance estimation process, PDE, it is possible to convert the total phase shift into a corresponding distance offset, and using the corresponding distance offset, to calculate a distance between a first device comprising the PLL, and a second device, for one-way, or two-way, distance estimation.

From reading the present disclosure, other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known in the art of type I PLLs, and which may be used instead of, or in addition to, features already described herein.

Although the appended claims are directed to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention.

Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. The applicant hereby gives notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

For the sake of completeness it is also stated that the term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality, a single processor or other unit may fulfil the functions of several means recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims.