Patent ID: 12189567

DETAILED DESCRIPTION

FIG.1is a simplified block diagram of a wireless communication system100that includes one or more base station systems (BSS)110, and one or more wireless devices102. Wireless devices102may include, for example, subscriber stations (e.g., hand-held computers, Internet of Things (IoT) devices, cellular telephones, etc.) that wirelessly communicate with the one or more BSS110. BSS110may include any radio access network (RAN) node such as, for example, an evolved Node-B or eNB devices of an LTE (Long Term Evolution) network) or any other type of RAN node in any other type of communication network.

As shown inFIG.1, each wireless device102includes a radio frequency (RF) transceiver106, a digital front end (DFE)105, a baseband processor108, input/output (I/O) devices104, and antenna(s)109. In operation, DFE105communicates data to a radio frequency (RF) transmitter within RF transceiver106. Baseband processor108(e.g., a digital signal processor) is connected through DFE105to the RF transceiver106, which in turn is connected to the one or more antennas109. The baseband processor108and the DFE105may be implemented as one or more integrated circuits to provide the digital processing functionality of the wireless device102. The digital processing components consolidated on the DFE105may include one or more control processors and digital transmit/receive filters, as well as interface peripherals and other I/O for RF subsystem functions. In various embodiments, each RF transceiver106(including an RF transmitter and an RF receiver) is configured to receive or transmit voice, data, or both voice and data using the antenna(s)109, and to provide an interface for signals between the antennas109and the DFE105. More specifically, each RF transceiver106is configured to perform digital-to-analog conversion and amplification of signals from the DFE105, and to amplify and perform analog-to-digital conversion of signals received over the air interface by an antenna109. In addition, each wireless device102may include one or more input/output devices104(e.g., a camera, a keypad, display, etc.), along with other components (not shown).

The BSS110includes a base station controller (BSC)112and one or more base transceiver stations (BTS)114, where each BTS114provides a communication interface between the BSC112and antennas119. The BSC112may, for example, be configured to schedule communications for the wireless devices102. Through antennas109,119, each wireless device102communicates with the BSC112of the BSS110via one of the BTS114.

Essentially, each BTS114is configured to receive or transmit signals that include processed voice, data, or both voice and data through the antenna(s)119, and to provide an interface for signals between the antennas119and the BSC112. The BTS(s)114each include a DFE115which may be implemented as one or more integrated circuits to provide the digital processing functionality of the BTS114. The digital processing components consolidated on the DFE115may include one or more control processors and digital transmit/receive filters, as well as interface peripherals and other I/O for RF subsystem functions. In addition, the BTS(s)114each include an RF transceiver116(including an RF transmitter and an RF receiver), which is configured to perform digital-to-analog conversion and amplification of signals from the DFE115, and to amplify and perform analog-to-digital conversion of signals received over the air interface by an antenna119.

In various embodiments, transceiver116includes one or more power amplifier modules to amplify signals and transmit resulting RF signals using antenna119. In some embodiments, the power amplifier modules include digital control interfaces to allow control of digitally controllable elements that influence or modify the operation of the amplifier. For example, digitally controllable elements may modify a capacitance value of a digitally variable capacitor (DVC) or may control switches that control the presence of circuit elements such as capacitors, inductors and/or resistors in the amplifier circuit. Also for example, a digitally controllable element may modify the operation of circuit elements that bias amplifiers. In general digitally controllable elements may influence or modify the operation of one or more modules within transceiver116in any manner.

Digitally controllable elements may be accessed via one or more interface gateway devices that are coupled to digital control interfaces external to the power amplifier module, (allowing host access) and coupled to one or more groups of digitally controllable elements using a control interface internal to the power amplifier module. For example, in some embodiments, an amplifier module may include an interface gateway device that is coupled to multiple external serial data interfaces that utilize different serial protocols, and that is also coupled in parallel to one or more groups of digitally controllable elements using an internal serial data interface. Registers within the digitally controllable elements may be written to, and read from, by a host controller using any of the external serial data interfaces.

In various embodiments, data presented sequentially on any of the external serial data interfaces may be written to registers in different digitally controllable elements in an interleaved sequence in accordance with an interleaved address map. Registers across multiple digitally accessible elements may be logically organized into “banks” such that one bank of registers (including registers in multiple elements) may be written to using sequential data on the external serial data interface before a second bank of registers (also including registers in the multiple elements) may be written to using sequential data on the same external serial data interface. These and other embodiments are described further below.

As will be appreciated, the digital control of amplifier modules disclosed herein with reference to the base station system110may also be used in connection with a wireless communication device, such as the wireless devices102. To this end, and as mentioned earlier, the transceiver106of each wireless device102may also include multiple digitally controllable elements that present an interleaved register address map to an external serial control interface through an interface gateway device.

FIG.2shows a block diagram of an RF transmit front end, in accordance with an example embodiment. RF transmit front end250may be included as a portion of an RF transceiver such as RF transceiver106within wireless device102or RF transceiver116within BSS110. According to an embodiment, RF transmit front end250includes digital-to-analog converters (DACs)262,263, low pass filters (LPFs), an oscillator, mixers, a signal combiner264, and a power amplifier module265.

Each DAC262,263includes a circuit for converting a digital sampled data stream to an analog signal. Because the analog signals are converted from a complex data stream, each DAC262,263may be defined as a subblock accepting either the real (I) or the imaginary (Q) component of the data stream. For example, DAC262may receive digital samples from a digital front end on node202, and DAC263may receive digital samples from a digital front end on node204. Each DAC262,263performs a digital-to-analog conversion on each received sample, and the resulting analog samples are filtered (e.g., by an LPF). The oscillator produces an RF sinusoidal signal that is used to upconvert (to RF) the analog I and Q sample streams. The filtered, analog I sample stream is mixed with the RF signal, and the filtered, analog Q sample stream is mixed with a 90 degree delayed version of the RF signal in order to re-align the I and Q sample streams. Combiner264then combines the two sample streams and provides a single RF input signal to the power amplifier module265. Power amplifier module265amplifies the RF input signal and produces an amplified RF output signal to be transmitted by antenna253.

As mentioned above, the power amplifier module265may include one or more digitally controllable elements (e.g.,411,421,431,441FIG.5), the operation of which is controlled using a digital interface such as digital control interface240. In the example ofFIG.2, digital control interface240includes serial data interface222or non-serial data interface224.

In some embodiments, serial data interface222may include multiple different serial data interfaces that use different serial protocols. For example, serial data interface222may include, in any number and in any combination, a serial peripheral (SPI) interface, an inter-integrated circuit (I2C) interface, an I3C interface, an RF front end (RFFE) interface, or any other serial data interface. As further described below, power amplifier module265may include an interface gateway device that is coupled to the external serial data interfaces (e.g., serial data interface222) and that may provide an internal serial data interface to communicate with one or more groups of digitally controllable elements within power amplifier module265.

In some embodiments, a first bank of registers that spans multiple digitally controllable elements may be written to using data presented sequentially on serial data interface222, and then a second bank of registers that also spans multiple digitally controllable elements may be written to using additional data presented sequentially on serial data interface222. Further, in some embodiments, non-serial data interface224may then be used to select a bank of registers to influence or modify the operation of the amplifier module265. These and other embodiments are further described below.

FIG.3shows multiple power amplifier modules, in accordance with an example embodiment. Whereas inFIG.2, digital control interface240is shown coupled to a single power amplifier module (PAM), in some embodiments, digital control interface240is coupled to multiple PAMs. For example, as shown inFIG.3, digital control interface240may be coupled to “n” power amplifier modules (n>1), represented as PAM0242, PAM1244, and PAM n246.

In some embodiments, first control values and first address values on the digital control interface240determine which PAM is being communicated with, and second control values and second address values on digital control interface240determine which digitally controllable elements or groups of digitally controllable elements within a PAM are being communicated with. These and other embodiments are further described below.

FIG.4shows a block diagram of a power amplifier module303including a Doherty power amplifier with groups of digitally controllable elements, in accordance with an example embodiment. As shown inFIG.4, Doherty amplifier300(e.g., amplifier module265,FIG.2) includes an RF input terminal301, a power splitter302, a carrier amplifier path304, a peaking amplifier path306, a summing node318, and an RF output terminal303. The power splitter302is coupled both to the carrier amplifier path304and to the peaking amplifier path306, and is configured to divide an input signal (RF-IN) received at RF input terminal301into a carrier RF signal and a peaking RF signal. More specifically, the outputs of power splitter302are connected to carrier amplifier310(also referred to as a main amplifier) and to peaking amplifier312. Impedance matching networks or circuits (not illustrated) may be included along the signal transmission paths between the outputs of power splitter302and the inputs to the carrier and peaking amplifiers310,312. To ensure proper Doherty operation, the carrier amplifier310along the carrier amplifier path304is biased to operate in Class-AB, and the peaking amplifier312along the peaking amplifier path306is biased to operate in Class-C.

In the illustrated embodiment, Doherty amplifier300has a “non-inverted” Doherty configuration, in which an impedance inverter and/or a λ/4 (90 degree) phase shift element314is connected between the output of carrier amplifier310and the summing node318. The output of peaking amplifier312also is connected to the summing node318. The phase shift introduced by element314is, in some implementations, compensated by a 90 degree relative phase shift present on path306introduced by phase shift element316, which is present between the power splitter302and the input to the peaking amplifier312. In an alternate embodiment, amplifier300may have an “inverted” Doherty configuration. In such a configuration, the impedance inverter and/or λ/4 line phase shift element314instead is connected between the output of peaking amplifier312and the summing node318, rather than being connected between the output of carrier amplifier310and the summing node318. In addition, in an inverted Doherty implementation, the phase shift introduced by element314between the output of the peaking amplifier312and the summing node318can be compensated by a 90 degree relative phase shift present on path304(e.g., between power splitter302and the input to the carrier amplifier310), rather than on path306. An impedance transformation network328between summing node318and the amplifier output303functions to present the proper load impedances to each of carrier amplifier310and peaking amplifier312, and outputs the combined signal produced at summing node318to the output terminal303as an output signal (RF-OUT). The output signal, RF-OUT, in turn, may be provided to an antenna (e.g., antenna253,FIG.2), for radiation over the air interface.

Power amplifier module303also includes interface gateway device320coupled to digital control interface240, and also coupled to groups of digitally controllable elements (DCE). For example, interface gateway device320is coupled to group0350, group1352, group2354, and group3356. The various groups350,352,354,356are coupled to interface gateway device320using an internal serial data interface that includes serial data and clock signals340that are common to all groups, and chip select signals CSB0332, CSB1334, CSB2336, CSB3338that are not common to all groups. For example, CSB0is coupled to group0, CSB1is coupled to group1, CSB2is coupled to group2, and CSB3is coupled to group3. Individual groups may include any number of digitally controllable elements.

In various embodiments, interface gateway device320converts serial communications from the external serial protocols (e.g., SPI, I2C, I3C, RFFE, etc.) to a single internal protocol as shown inFIG.4. Converting all of the external protocols in interface gateway device320obviates any need for digitally controllable elements to support a complicated multi-protocol interface.

In the embodiment ofFIG.4, one or more digitally controllable elements within groups0,1,2,3, may be coupled to control circuit elements within Doherty amplifier300. For example, digitally controllable elements within group0350may influence or modify the operation of impedance matching circuits by controlling switches and variable capacitors, and digitally controllable elements within group1352may influence operation of biasing circuits, etc. A more detailed example of digitally controllable elements in a Doherty power amplifier is discussed below with reference toFIG.5.

FIG.5shows a block diagram of a power amplifier module including a Doherty power amplifier with groups of digitally controllable elements, in accordance with an example embodiment. Power amplifier module400receives signals from a digital control interface240at interface gateway device320. In embodiments represented byFIG.5, external serial data interfaces222are converted into an internal serial data interface represented by common serial data and clock340, and chip selects CSB0332and CSB1334. Further, in embodiments represented byFIG.5, interface gateway device320passes non-serial data interface224through as bank select signal402. In the example ofFIG.5, digitally controllable element411represents a controllable element within an impedance matching circuit410at the input to carrier amplifier310(“carrier input match”), digitally controllable element421represents a controllable element within an impedance matching circuit420at the output of carrier amplifier310(“carrier output match”), digitally controllable element431represents a controllable element within an impedance matching circuit430at the input to peaking amplifier312(“peaking input match”), and digitally controllable element441represents a controllable element within an impedance matching circuit440at the output of peaking amplifier312(“peaking output match”).

As an example, and not by way of limitation, one or more of impedance matching circuits410,420,430, and440may include a T network with two inductors in series between the network input/output (e.g., between the splitter and the amp), and a shunt capacitor coupled to a node between the two inductors. In these embodiments, the digitally controllable elements may include a digitally variable shunt capacitor, and/or switches to control which inductors are included within the impedance matching circuit.

As shown inFIG.5, digitally controllable elements411,421,431,441within impedance matching circuits410,420,430, and440are example embodiments of a group of digitally controllable elements (e.g., group0350;FIG.4)). In this example, the entire group is coupled to the common serial data and clock340and chip select CSB0332.

In some embodiments, digitally controllable elements are included to influence the operation of different parts of Doherty amplifier400. For example, in some embodiments, bias voltages of amplifiers310,312may be modified using digitally controllable elements. For example, as shown inFIG.5, amplifiers310,312may be coupled to the common serial data and clock340and chip select CSB1354.

In some embodiments, Doherty amplifier400may support two (or more) tuneable states (e.g., corresponding to two different frequency bands) so that operational state of the amplifier may be quickly switched between the two tuning states using a single input pin (e.g., bank select402). In this example, each of digitally controllable elements within group0(e.g., elements411,421,431,441) includes or accesses two bank registers which are used to set the tuning levels for each tuning state. The first tuning state may correspond to a first configuration for the four impedance matching circuits410,420,430,440, and the second tuning state may correspond to a second configuration for the four impedance matching circuits410,420,430,440. When the amplifier is operating in one tuning state, which utilizes tuning information (“tuning values”) within the first bank registers (“current bank registers”), the second bank registers for the other state can be modified by writing new values to them through the digital control interface. Once the amplifier changes to operation in the other tuning state, the newly modified tuning values will be applied. Alternatively, the current bank registers can be written to through the digital control interface, in which case the change will take effect immediately.

In some embodiments, all of the components illustrated inFIG.5may be mounted on a module substrate401(e.g., a printed circuit board “PCB”), which may then be mounted to a system PCB.

FIG.6shows a block diagram of a power amplifier module interface gateway device, in accordance with an example embodiment. Interface gateway device320is coupled to an external digital control interface (i.e., an interface that is electrically connected to and communicates with circuitry external to the power amplifier module), shown inFIG.6as serial data interface602. and non-serial data interface224.

Serial data interface602includes multiple signal lines that may be coupled to an external serial interface that adheres to one of many different serial protocols. For example, serial data interface602may be coupled to an external SPI serial data interface, an external I2C serial data interface, an external I3C serial data interface, an external RF front end (RFFE) serial data interface, or any other type of external serial data interface. Interface gateway device320is also coupled to an internal serial data interface (i.e., an interface that is electrically connected to and communicates with circuitry internal to the power amplifier module), shown inFIG.6as including INT_DATA610, INT_SCLK612, and chip select signals CSB[0. . .3]614. The interface gateway device translates all the supported external interface protocols to a simpler SPI type format that is passed to the internal devices. The interface gateway device also converts data read from the internal devices back to the external protocol to send back to the host controller. Data packets are translated in real time without buffering, which makes the operation transparent to the external controller, and does not require any additional buffering logic.

In some embodiments, serial data interface602includes a Clock signal, a Data In/Out signal, a Data Out signal, and a Chip Select signal. These external signals may be coupled to either an I2C, I3C, or SPI serial interface as shown in Table 1, below.

TABLE 1External SignalI2CI3CSPIClockSCLSCLSCKData In/OutSDASDASDIData OutSDOChip SelectCSB

In various embodiments, interface gate320is used to bridge SPI transactions from an external host controller (not shown) to internal client devices (e.g., DCE groups). Passing through the interface gateway device320adds additional delay to the SPI signals. When the host controller is writing to the client device this delay applies to both the SCLK and the SDI signal on the external SPI interface. Since both are delayed approximately equally the internal clock and data signals (INT_SCLK and INT_DATA) maintain their timing relationship and the transaction is performed successfully, just slightly delayed.

When the external host controller uses the SPI interface to read data back from the internal device the additional logic within interface gateway device320delays the returning INT_DATA signal, which may delay the signal so much that the serial data signal on the external SPI interface does not reach the controller until after the next SCLK rising edge and no longer matches the SPI protocol. In various embodiments, the INT_DATA signal from the internal client device starts half a clock cycle early by changing on the rising edge of SCLK instead of the falling edge. The SPI timing is reconstructed in the interface gateway device320where the INT_DATA signal passes through a latch before being passed to the SDO signal to the host controller.

FIG.7shows a timing diagram for an example embodiment using an I2C or I3C interface to write data through an interface gateway device. In various embodiments, interface gateway device320is used to translate other protocol transactions from the external host controller to the internal client devices. In the example ofFIG.7, an external (e.g., I2C, I3C, RFFE, etc.) serial write transaction (i.e., a write transaction from an external source) is decoded and translated by the interface gateway device320to a SPI-like internal serial write transaction. In this case the interface gateway device320removes some of the clock pulses from the I2C, I3C or RFFE transaction and converts it into a SPI-like transaction. The additional clock cycles in the original transaction enable the interface gateway device logic to be pipelined if desired to avoid the tighter timing concerns of the SPI bridging mode.

The external serial data interface is represented inFIG.7by serial data SDA and serial clock CLK. The internal serial data interface is represented inFIG.7by CSB signals720,730, internal serial data SDI740, and internal clock SCLK750.

An external serial write transaction may begin at702when a first data unit of serial data (SDA) is presented on a serial data interface (e.g., serial interface602,FIG.6), where the first data unit includes a seven bit address A6-A0, a read/write (R/W) bit, and an acknowledgement (ACK) bit. In some embodiments, the address may specify an address corresponding to a PAM module, where each distinct PAM module has a unique address. For example, address bits A6-A0may specify one of the PAM modules242,244,246shown inFIG.3. Each PAM module includes an interface gateway device320that responds to a unique address, thereby allowing individual PAM modules to be addressed at702.

As part of the serial protocol translation, the first data unit702of the external transaction is masked from (i.e., not conveyed to) the internal serial data interface for all PAMs, including the addressed PAM (i.e., the PAM identified by the address bits A6-A0in data unit702) and the non-addressed PAMs (i.e., all other PAMs). Within non-addressed PAMs, the remainder of the transaction is also masked from the internal serial data interface. The transaction shown inFIG.7represents communication within an addressed PAM (e.g., a PAM that responds to the address specified at702).

When the PAM is being addressed, the interface gateway device320passes the next serial byte including the R/W bit704, group bits S0, S1,706, and register address bits708through to the internal serial data interface610at740. The interface gateway device also asserts all chip select signals614at720within the addressed PAM for the next serial byte to allow each group of digitally controllable elements coupled to the addressed PAM (i.e., the “addressed group”) to decode the R/W bit704, the addressed group specified by group bits S1, S0706, and the register address bits708. The R/W bit704specifies whether the transaction is a read or a write transaction, the group bits706specify which group of DCEs is being addressed, and the register address bits708specify which register(s) within the addressed group are being addressed. As an example, referring back toFIG.5, power amplifier module400includes two groups. Group0includes elements411,421,431,441, and group1includes elements within amplifiers312and310. If, in the transaction ofFIG.7, the group bits706specify group0, then a register in one of elements411,421,431, and441will be addressed by register address bits708. Similarly, if the group bits706specify group1, then a register in one of the elements within amplifiers310,312will be addressed by register address bits708.

The interface gateway device320asserts the chip select for an addressed group at730. For example, if group0is addressed by group bits706, then CSB0will be asserted at730. An acknowledge bit ACK710is masked from the internal serial data, and then one or more data bytes712are passed on to the internal serial data interface610at740. A final ACK714is masked.

FIG.8shows a timing diagram for an example embodiment using an I2C or I3C interface to read data through an interface gateway device. An I2C or I3C read transaction operates in a similar manner to the write transaction described above with referenceFIG.7. The read operation illustrated inFIG.8begins similarly to the write operation inFIG.7. The first data unit702including the PAM address, RAY bit, and ACK bit is received at the interface gateway device. When a PAM is being addressed, the chip selects614for all groups within the PAM are asserted at720for the next serial byte, and R/W bit704, group bits706, and register address bits708are passed through to the internal serial data interface610at840. The interface gateway device then receives a restart and the PAM address and R/W bit again on the external serial data interface at810. In response, the addressed digitally controllable element within the addressed group writes serial data on the internal serial data which is then passed on to the external serial data interface at860. Extraneous data and clock pulses may be presented on the internal serial bus which may be ignored by the interface gateway device.

FIG.9Ashows a block diagram of a digitally controllable element, in accordance with an example embodiment. Digitally controllable element900may be used to implement any of the digitally controllable elements described herein. For example, in some embodiments, digitally controllable element900may be used to implement any of elements within groups350,352,354, or356(FIG.4) or elements411,421,431, or441(FIG.5).

Digitally controllable element900includes serial interface circuit910, control register912, test register914, bank1register916, bank2register918, and multiplexers940and942. In some embodiments, digitally controllable element900also includes one or more digital variable capacitors and/or or passive circuits with switching elements (e.g., transistors) that switch in/out circuit elements (e.g., the switching elements controlled by multiplexers940and942). Serial interface circuit910is coupled to a serial data interface represented inFIG.9as DATA/CTL IN on node902and DATA OUT on node904. The serial data interface may take any form. For example, in some embodiments, the serial data interface may be a three-wire serial data interface and in other embodiments, the serial data interface may be a four-wire serial data interface. In general, the various embodiments are not limited by the type of serial data interface employed.

In the example ofFIG.9A, digitally controllable element900supports two tuneable states of a tuneable element (e.g., a variable component or configurable circuit) in an amplifier. For example, bank1register916may store a first digital word that specifies a first tuneable state, and bank2register918may store a second digital word that specifies a second tuneable state. Each of the first and second digital words may encode, for example, a tuneable element value (or control values corresponding to a tuneable element value) and/or a switch state indicator. The bank select signal on node402may cause multiplexers940,942to configure the tuneable element into either of two tuneable states by passing the contents of either bank1register916or bank2register918to the outputs of the multiplexers940,942. In some embodiments, the output of multiplexer940controls one or more digitally variable capacitors, and the output of multiplexer942controls one or more switches that are coupled to add or remove circuit elements from an amplifier circuit. For example, one or more capacitors, inductors or resistors may be coupled to, or decoupled from, a tuning circuit based on the output of multiplexer942. Control register912and test register914may be used for any purpose, and in some embodiments, they are omitted.

FIG.9Bshows an address map of the registers912,914,916,918within digitally controllable element900ofFIG.9A, in accordance with an example embodiment. For example, data that is presented sequentially by gateway320on the internal serial data interface610is communicated to a serial data interface (e.g., DATA/CTL IN node902) of the digitally controllable element900. This data may be written by element900sequentially to the registers916,918within the digitally controllable element900. Similarly, during a read operation, the digitally controllable element900may present the contents of the registers912,914,916,918sequentially on a serial data interface (e.g., DATA OUT node904) in response to a read command.

FIG.9Cshows a timing diagram of a write operation to the digitally controllable element900ofFIG.9A, in accordance with an example embodiment.FIG.9Cshows a chip select signal CSB, a serial clock signal SCLK, and a serial data input signal SDI, all of which are parts of DATA/CTL IN902(the internal serial data interface). The first byte960represents the RAY bit704, the group bits706, and the register address bits708(FIG.7). In operation, when the CSB signal is asserted (low), the serial interface910will decode the first byte960(or any word size) of serial data as an address. In some embodiments, the first byte960also specifies a command. For example, the first byte960may specify a read or a write command in addition to an address corresponding to a digitally addressable element. When the first byte960includes an address that matches the address assigned to a register912,914,916,918within element900, serial interface910performs an action. For example, when a write command is decoded from the first byte960, and the first byte960also indicates an address that maps to one of the registers912,914,916,918, serial interface910receives additional serial data (e.g., bytes961,962,963,964) presented sequentially on the serial data interface (DATA/CTL IN node902) and writes to the internal registers912,914,916,918, starting at the address encoded in the first byte960. In the example ofFIGS.9B and9C, for example, assuming that the first byte960indicates address0, Data1961is written to address0(control register912), Data2962is written to address1(bank1register916), Data3963is written to address2(bank2register918), and Data4964is written to address3(test register914). The gateway320may than indicate a tuneable state through the bank select signal on node402.

In some embodiments, serial interface910includes additional decoding circuitry to enable interleaving the register address map shown inFIG.9Bwith the register address maps of other digitally controllable devices (e.g., additional instances of device900). For example, when multiple digitally controllable elements are included in an amplifier module and coupled in parallel to the serial data interface, data presented sequentially may be written to registers in multiple digitally controllable elements. These and other embodiments are further described below.

FIG.10Ashows a block diagram of multiple interconnected digitally controllable elements, in accordance with an example embodiment. In the example ofFIG.10A, digitally controllable elements1002,1004,1006,1008(e.g., four instances of digitally controllable element900) are coupled in parallel to a serial data interface that includes signals SDI, SDO, CSB, and SCLK. In some embodiments, the four digitally controllable elements ofFIG.10Amay correspond to four digitally controllable elements in a power amplifier module. For example, element1002may correspond to element411(FIG.5), element1004may correspond to element421(FIG.5), element1006may correspond to element431(FIG.5), and element1008may correspond to element441(FIG.5). Each element1002,1004,1006,1008may include a same type of tuneable element (e.g., a tuneable capacitor or configurable circuit), or elements1002,1004,1006,1008may include different types of tuneable elements.

FIG.10Bshows a block diagram of a digitally controllable element, in accordance with an example embodiment. Digitally controllable element1020may implement any of the digitally controllable elements described herein, including elements411,421,431,441(FIG.5),900(FIG.9A), and1002,1004,1006,1008(FIG.10A). Element1020includes address control logic1022, registers1024, shift register1026, and output buffer1028. Element1020may also include variable circuit elements (e.g., digitally variable capacitors) and passive circuits such as switches as described above.

In operation, serial data present on a serial data in (SDI) line is received at (i.e., clocked into) shift register1026during a write operation, and data from registers1024is presented as serial data on serial data out (SDO) via shift register1026during a read operation. Address control logic1022receives the chip select signal CSB and decodes the address and operation (e.g., read or write) from the first byte (e.g., byte960,FIG.9C) received from the shift register through connection1030. Address control logic1022also receives a device identifier (DEV ID) at input1040. During a write operation, and in response to the address and the DEV ID, address control logic1022may or may not write to registers1024in accordance with an interleaved register accessing sequence wherein the physical registers1024in the various elements (e.g.,1002,1004,1006,1008) are interleaved in a logical register writing sequence. This is illustrated inFIG.11Awhere the bank1registers from different digitally controllable elements are logically grouped together, the bank2registers are grouped together, the control registers are grouped together, and the test registers are grouped together.FIG.11Ais described in more detail below.

In the example ofFIG.10B, the DEV ID is hard coded within digitally controllable element1020, and each of the digitally controllable elements1002,1004,1006,1008has a different DEV ID value. In these embodiments, each of the digitally controllable elements1002,1004,1006,1008(e.g., elements included within an amplifier module) includes a mechanism to store or otherwise specify the DEV ID. In some embodiments, each of the digitally controllable elements may include a slightly different semiconductor device (e.g., silicon) design to accommodate different DEV IDs.

In various embodiments, the address control logic1022may include one or more state machines and digital logic to perform the operations described herein. For example, address control logic1022may include a counter that is loaded with the address value clocked in through the shift register1026, and the counter may be incremented each SCLK cycle. A decoder circuit may then decode the counter state along with the DEV ID to determine which (if any) registers within the current digitally controllable element are being addressed (e.g., written to or read from). This address decoding logic enables each digitally controllable element1002,1004,1006,1008to keep track of which register is being accessed during each clock cycle of the serial transaction. The read/write action of each transaction cycle is gated by the address decoding logic so that although the action is sent to all of the digitally controllable elements1002,1004,1006,1008coupled in parallel to the serial data interface, only the element or elements that use that particular register address perform the action. The use of the DEV ID allows the same address decoding logic to be used in all of the digitally controllable elements1002,1004,1006,1008.

FIG.11Ashows an address map of the multiple interconnected digitally controllable elements1002,1004,1006,1008ofFIG.10A, in accordance with an example embodiment. Register address map1100shows an example interleaved register address map presented by multiple digitally addressable elements that are coupled in parallel to a serial data interface, such as elements1002,1004,1006,1008(FIG.10A). As further explained below, address control logic within each element decodes an element specific device identifier and an address presented on the serial data interface to determine the configuration of the interleaved register address map. For convenience of description and illustration, a first digitally controllable element (e.g., element1002) is designated as device “A,” a second digitally controllable element (e.g., element1004) is designated as device “B,” a third digitally controllable element (e.g., element1006) is designated as device “C,” and a fourth digitally controllable element (e.g., element1008) is designated as device “D.” In the interleaved address map1100, physical writeable registers of the same type or location (e.g., Control, Bank1, Bank2, and Test) in the multiple digitally controllable elements are logically grouped together in a writing sequence such that a serial writing order of each of the writeable registers in an element is interleaved with a serial writing order of writeable registers in other elements.

As an example, bank1registers from four different digitally controllable elements A, B, C, and D (A Bank1, B Bank1, C Bank1, D Bank1) are logically grouped in the register address map and are addressed in sequential order (e.g., as addresses4-7), even though they correspond to physical registers in different devices. Similarly, bank2registers from four different digitally controllable elements A, B, C, and D (A Bank2, B Bank2, C Bank2, D Bank2) are logically grouped in the register address map and are addressed in sequential order (e.g., as addresses8-11). Accordingly, the writing order of bank1registers from different digitally controllable elements are interleaved, and the writing order of bank2registers from different digitally controllable elements are interleaved, in order to create the interleaved register address map1100. This allows a sequential, serial write operation to bank1registers in all of the digitally controllable registers without disturbing (e.g., overwriting) the contents of the other registers within the digitally controlled elements (e.g., bank2, test, and control registers). Similarly, this allows a sequential, serial write operation to bank2registers in all of the digitally controllable registers without disturbing (e.g., overwriting) the contents of the other registers within the digitally controlled elements (e.g., bank1, test, and control registers). An example write operation is illustrated inFIG.11B.

FIG.11Bshows a timing diagram of a write operation to the multiple interconnected digitally controllable elements ofFIG.10A, in accordance with an example embodiment. The write operation1140illustrated inFIG.11Bdemonstrates writing to bank1registers in elements1002,1004,1006,1008(FIG.10A) according to the interleaved register address map1100(FIG.11A). A write operation to address4“write4” is presented as the first byte1160on the serial data input SDI line of the serial data interface. This is received (at shift register1026) and decoded (by address control logic1022) by all four digitally controllable elements1002,1004,1006,1008. The address control logic within each element decodes the write4along with the element specific DEV ID, and the element that includes the register mapped in the register address map1100to address4(element1002, DEVICE A) performs the first write. Accordingly, when presented as the second byte1162on the serial data input SDI line of the serial data interface, the serial data in byte1162is written to the bank1register of device A (element1002). Then the address within each element is incremented by the address control logic (in this example to address “5”). The address control logic within each element then decodes the incremented address value of 5 along with the element specific DEV ID, and, according to the register address map1100, the element that includes the register at address5(element1004, DEVICE B) performs the next write into its bank1register. Accordingly, the serial data in byte1164is written to the bank1register of device B (element1004). In a similar manner, the serial data in subsequently received byte1166is written to the bank1register of device C (element1006), and the serial data in subsequently received byte1168is written to the bank1register of device D (element1008).

As illustrated inFIGS.11A and11B, multiple digitally controllable elements coupled in parallel to a serial data interface are configured to present an interleaved register address map to the serial data interface in response to a unique device identifier assigned to each of the multiple digitally controllable elements. AlthoughFIG.11Billustrates a write operation to a single bank of interleaved registers, the various embodiments described herein are not limited in this respect. For example, in some embodiments, write operations span banks such that multiple banks are written in a single write operation. Also for example, in some embodiments, test and control registers are contiguous in the interleaved register address map, and single write operation may update the contents of all test and control registers in all digitally controllable elements without disturbing the contents of any of the bank1registers or bank2registers.

Read operations may be performed in a similar manner. For example, during a read operation, the write4in byte1160may instead be a “read9” (or a read of another register address), and each digitally controllable register will decode the address along with the element's specific DEV ID to determine which register contents are to be presented on the SDO output, in this instance resulting in the bank2register contents being read from multiple digitally controllable elements in a sequence according to the interleaved register map shown at1100(FIG.11A).

FIG.12Ashows a block diagram of multiple interconnected digitally controllable elements, in accordance with an example embodiment. In the example ofFIG.12A, digitally controllable elements1202,1204,1206,1208(e.g., four instances of digitally controllable element900) are coupled in parallel to a serial data interface that includes signals SDI, SDO, CSB, and SCLK. In some embodiments, the four digitally controllable elements ofFIG.12Amay correspond to four digitally controllable elements in a power amplifier module. For example, element1202may correspond to element411(FIG.5), element1204may correspond to element421(FIG.5), element1206may correspond to element431(FIG.5), and element1208may correspond to element441(FIG.5). Each element1202,1204,1206,1208may include a same type of tuneable element (e.g., a tuneable capacitor or configurable circuit), or elements1202,1204,1206,1208may include different types of tuneable elements

In embodiments represented byFIG.12A, each of the digitally controllable elements also receives an element specific DEV ID. For example, element1202receives a DEV ID having a value of DEV A, element1204receives a DEV ID having a value of DEV B, element1206receives a DEV ID having a value of DEV C, and element1208receives a DEV ID having a value of DEV D. The element specific DEV ID values may be any values that the address control logic within the addressable elements can decode to determine the interleaved register address map. For example, the DEV A value may be zero, the DEV B value may be four, the DEV C value may be eight, and the DEV C value may be twelve.

FIG.12Bshows a block diagram of a digitally controllable element, in accordance with an example embodiment. Digitally controllable element1220may implement any of the digitally controllable elements described herein, including elements411,421,431,441(FIG.5),900(FIG.9A), and1002,1004,1006,1008(FIG.10A). Element1220includes address control logic1022, registers1024, shift register1026, and output buffer1028, all of which are described above with reference toFIG.10B. Element1220may also include variable circuit elements (e.g., digitally variable capacitors) and passive circuits such as switches as described above.

In the example ofFIG.12B, the DEV ID is not hard coded within digitally controllable element1220. In these embodiments, each of the digitally controllable elements included within an amplifier module includes an additional DEV ID input, through which each element receives the element's specific DEV ID from an external node1240. In these embodiments, each of the digitally controllable elements may be implemented using identical semiconductor device (e.g., silicon) designs, allowing any number of identical parts to be utilized within an amplifier module. In some embodiments, the element specific DEV IDs are specified by coupling multiple individual circuit traces within node1240to logic levels when a digitally controllable element is placed in an amplifier module. For example, in some embodiments, node1240may include four individual circuit traces, allowing for 16 different DEV ID values. DEV A may be set to zero (0001), DEV B may be set to four (0100), DEV C may be set to eight (1000), and DEV D may set to twelve (1100). As another example, in some embodiments, node1240may include only two individual circuit traces, allowing for 4 different DEV ID values. DEV A may be set to zero (00), DEV B may be set to one (01), DEV C may be set to two (10), and DEV D may set to three (11). These DEV ID values are presented as examples only, and the various embodiments are not limited in this respect.

FIG.13is a flowchart illustrating methods, in accordance with various embodiments. In block1310, an interface gateway device receives, on a first serial data interface (e.g., serial interface602,FIG.6), using a first serial protocol, a first command to write to a first bank of registers in a first group of digitally controllable elements, wherein the first command includes a first group value, a first register address value, and first data values (collectively referred to as “data values”) sequentially on the first serial data interface. The first serial data interface may be one of many different types of serial data interfaces coupled to the interface gateway device and accessible outside a power amplifier module. For example, the first serial data interface may be any of the serial data interfaces described above. Further, the first serial protocol may be any of the serial protocols described above (e.g., SPI, I2C, I3C, RFFE, etc.). An example of the operations of block1310is illustrated inFIG.7in which a first command (including bits702,704,706,708) is received including group value (e.g., group bits706), a register address value (e.g., address bits708), and sequential data values (e.g., data bits712).

In block1320, the first data values are written by the interface gateway device320to the first bank of registers (e.g., corresponding to addresses4-7,FIG.11A). The interface gateway device performs the write operation by translating the first serial protocol on the external serial data interface (e.g., serial interface602,FIG.6) to a second serial protocol on an internal serial data interface (e.g., interface610,FIG.6) coupled to the groups of digitally controllable elements. For example, as illustrated inFIG.7, the interface gateway device produces chip select signals720,730, data740, and clock750on the internal serial data interface to perform the write operation that was received in the first command on the external serial data interface at1310.

In various embodiments, during the write operation at1320, the first register address value and an element specific ID within each of the group-addressed digitally controllable elements (or provided from an external source) are decoded to write the multiple data values to registers in the multiple elements (or to read multiple data values from the registers, depending on whether the operation is write or read) according to an interleaved register address map. In one example of the operations of block1320(e.g., when the first register address specifies a write to register address4,FIG.11A), each of the digitally controllable elements may decode the write operation starting at register address4and write to the bank1registers at addresses4,5,6, and7in interleaved register map1100in sequential order even though the physical registers corresponding to these addresses are physically located in different digitally addressable elements. In another example of the operations of block1320, multiple banks of registers within the multiple elements may be written. For example, the first register address value may be followed by eight sequential data values, in which case both bank1registers and bank2registers will be written according to the interleaved register map1100.

In block1330, the interface gateway device receives, on the first serial data interface, using the first serial protocol, a second command to write to a second bank of registers in the first group of digitally controllable elements, wherein the second command includes the first group value, a second register address value, and second data values sequentially on the first serial data interface. As described above, the first serial data interface may be one of many different types of serial data interfaces coupled to the interface gateway device and accessible outside a power amplifier module. For example, the serial data interface may be any of the serial data interfaces described above (e.g., serial interface602,FIG.6), and the first serial protocol may be any of the serial protocols described above (e.g., SPI, I2C, I3C, RFFE, etc.). An example of the operations of block1330is illustrated inFIG.7in which a first command (including bits702,704,706,708) is received including group value (e.g., bits706), a register address value (e.g., bits708), and sequential data values (e.g., bits712).

In block1340, the second data values are written by the interface gateway device320to the second bank of registers (e.g., corresponding to addresses8-11,FIG.11A). The interface gateway device performs the write operation by translating the first serial protocol on the external serial data interface to the second serial protocol on the internal serial data interface coupled to the groups of digitally controllable elements. For example, as illustrated inFIG.7, the interface gateway device produces chip select signals720,730, data740, and clock750on the internal serial data interface to perform the write operation that was received in the first command on the external serial data interface at1310.

In block1350, a selection is made between multiple (e.g., first and second) logically contiguous banks of registers (e.g., bank1and bank2) to influence or modify the operation of an amplifier module (e.g., to set the values of tunable elements or circuit configurations according to the values in the bank1registers or the bank2registers). The multiple logically contiguous banks of registers may be spread across multiple digitally controllable elements. In an example of the operations of block1350, a bank select signal (e.g., bank select402,FIG.9A) may select one of bank1registers or bank2registers to select a tunable state of a power amplifier module (e.g., power amplifier module265,FIG.2). In some embodiments, the operations of blocks1310and1320are repeated to effect a write operation in one bank of registers while a different bank of registers is selected in block1350. For example, a typical sequence may include 1) write both banks of registers in a single write operation (blocks1310,1320), 2) select bank1to put a power amplifier module in a first tunable state associated with bank1(block1350), 3) while the power amplifier module is operating in the first tunable state, write to bank2(repeat blocks1310,1320) without disturbing bank1and without disturbing the amplifier operation in the first tunable state, and 4) subsequently selecting bank2to put the power amplifier module in a second tunable state (repeat block1350). The aforementioned sequence is provided as an example only, and the various embodiments described herein support a myriad of different writing and selecting sequences.

In an alternate embodiment, the operations of blocks1310and1320may be repeated to effect a write operation in one bank of registers while that same bank of registers is selected in block1350. For example, a typical sequence may include 1) write both banks of registers in a single write operation (blocks1310,1320), 2) select bank1to put an amplifier module in a first tunable state associated with bank1(block1350), and 3) while the amplifier module is operating in the first tunable state, overwrite the registers of bank1(repeat blocks1310,1320).

The above-described embodiments relate to a system that is configurable into two states (e.g., an amplifier that is configurable to operate in two different frequency bands), where “Bank1” pertains to settings associated with a first state, and “Bank2” pertains to settings associated with a second state. In other embodiments, the system may be configurable into more than two states, and accordingly, additional registers associated with additional states may be interleaved and grouped together in the address map (e.g., Bank3, Bank4, and so on).

An embodiment of system includes an interface gateway device coupled to communicate with one or more host controllers using one or more first serial data interfaces using one or more first serial protocols, the interface gateway device configured to convert the one or more first serial protocols to a second serial protocol to communicate on a second serial data interface. The system further includes a first group of digitally controllable elements communicatively coupled in parallel to the interface gateway device, wherein each digitally controllable element of the first group of digitally controllable elements includes a plurality of writeable registers, and further includes an address control circuit. The address control circuit is configured to receive a first byte including an address value from the serial data interface, receive a plurality of data values from the serial data interface, and write at least one of the plurality of data values to at least one of the plurality of writeable registers in accordance with an interleaved register accessing sequence in which a serial writing order of the plurality of writeable registers is interleaved with a serial writing order of writeable registers in other digitally controllable elements of the plurality of digitally controllable elements.

According to a further embodiment of the system, the first group of digitally controllable elements are coupled to be responsive a common chip select signal within the serial data interface. According to a further embodiment, the address control circuit is configured to determine the interleaved register accessing sequence responsive to a unique device identifier assigned to each digitally controllable element of the plurality of digitally controllable elements. According to yet another further embodiment of the system, the unique device identifier is hard-coded within each digitally controllable element of the plurality of digitally controllable elements. According to yet another further embodiment of the system, each digitally controllable element of the plurality of digitally controllable elements includes an input node to receive the unique device identifier. According to a further embodiment, the address value specifies a write operation, and the address control circuit is configured to decode the write operation from the address value. According to another further embodiment, the address control circuit is further configured to receive a second address value from the serial data interface and present contents of at least one of the plurality of writeable registers on the serial data interface in accordance with the interleaved register accessing sequence. According to another further embodiment, the plurality of writeable registers within each digitally controllable element are organized into a plurality of banks, and wherein each digitally controllable element is responsive to a bank select signal to select one of the plurality of banks. According to a further embodiment, contents of a selected bank of the plurality of writeable registers are coupled to control at least one digitally variable capacitor. According to a further embodiment, contents of a selected bank of the plurality of writeable registers are coupled to control at least one variable impedance circuit within an amplifier module.

According to another further embodiment the amplifier module includes a Doherty power amplifier with a carrier amplifier path and a peaking amplifier path, the Doherty power amplifier includes a power splitter configured to divide the RF input signal into a carrier RF signal and a peaking RF signal, the digitally controllable elements include one or more variable capacitors and/or switches coupled to inductors coupled to either or both of the carrier amplifier path and the peaking amplifier path, and the digitally controllable elements are configured to modify operation of the amplifier by modifying impedances within the amplifier module.

An embodiment of a power amplifier module includes an RF input node, an RF output node, a plurality of first serial data interfaces accessible outside the power amplifier module, an interface gateway device coupled to the plurality of first serial data interfaces, and to provide a second serial data interface internal to the power amplifier module, at least one amplifier to amplify an input signal on the RF input node and produce an output signal on the RF output node, and a first group of digitally controllable elements coupled to modify operation of the at least one amplifier, the plurality of digitally controllable elements being coupled in parallel to the second serial data interface, wherein the first group of digitally controllable elements are configured to present an interleaved register address map to the second serial data interface in response to a unique device identifier assigned to each of the plurality of digitally controllable elements.

According to a further embodiment of the system, the at least one amplifier includes a Doherty power amplifier with a carrier amplifier path and a peaking amplifier path, and the plurality of digitally controllable elements include one or more variable impedance circuits coupled to either or both of the carrier amplifier path and the peaking amplifier path. According to a further embodiment, each of the plurality of digitally controllable elements includes physical registers, and the interleaved register address map includes a plurality of logically contiguous banks of registers, wherein each logically contiguous bank of registers of the plurality of logically contiguous banks of registers includes physical registers in each of the plurality of digitally controllable elements. According to yet another further embodiment of the system, the amplifier module includes a bank select input node coupled to select one of the logically contiguous banks of registers to modify operation of the at least one amplifier. According to yet another further embodiment of the system, the plurality of digitally controllable elements include programmable impedance circuits.

An embodiment of a method performed by a communication system includes receiving, on first serial data interface, using a first serial protocol, a first command to write to a first bank of registers in a first group of digitally controllable elements in a power amplifier module, wherein the first command includes a first group value, a first address value, and first data values sequentially on the first serial data interface; writing the first data values to the first bank of registers; receiving, on the first serial data interface, using the first serial protocol, a second command to write to a second bank of registers in a first group of digitally controllable elements in a power amplifier module, wherein the first command includes the first group value, a second address value, and second data values sequentially on the first serial data interface; writing the second data values to the second bank of registers; and selecting between the first bank of registers and the second bank of registers to modify operation of the power amplifier module.

According to a further embodiment, the method may further include writing to the first bank of registers when the second bank of registers are selected. The method may further include amplifying the RF input signal, by a power amplifier that includes a sub-circuit that is controllable based on the control signal produced by the control circuit. The method may further include writing to the second bank of registers when the first bank of registers are selected. According to another further embodiment of the method, selecting between the first bank of registers and the second bank of registers to modify operation of the power amplifier module includes selecting between two states of impedance matching circuits.

The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first”, “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.

As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, or the like, at which a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes may be realized by one physical element (and two or more signals can be multiplexed, modulated, or otherwise distinguished even though received or output at a common node).

The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted subject matter.

While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.