Patent ID: 12199770

DETAILED DESCRIPTION

The present implementations will now be described in detail with reference to the drawings, which are provided as illustrative examples of the implementations so as to enable those skilled in the art to practice the implementations and alternatives apparent to those skilled in the art. Notably, the figures and examples below are not meant to limit the scope of the present implementations to a single implementation, but other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the present implementations can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present implementations will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the present implementations. Implementations described as being implemented in software should not be limited thereto, but can include implementations implemented in hardware, or combinations of software and hardware, and vice-versa, as will be apparent to those skilled in the art, unless otherwise specified herein. In the present specification, an implementation showing a singular component should not be considered limiting. Rather, the present disclosure is intended to encompass other implementations including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the present implementations encompass present and future known equivalents to the known components referred to herein by way of illustration.

Time synchronization can be a crucial parameter for time-aware networks like telecommunication, industrial automation, and connected cars. Time-aware networks can include 5G telecom networks, and other network architectures demanding latency below the nanosecond level. For example, with 5G being a low timestamping error-tolerant network, the timestamping error performance parameter values are quite stringent for it. Thus, the need for high accuracy timestamping has become even more important, and to meet timestamping accuracy and error performance numbers for 5G and other networks having stringent latency and error-tolerance requirements. A technical solution can include a serial high-speed Ethernet stack, with a special frame marker Start of Frame Delimiter (SFD) for timestamping. Timestamping at the SFD can achieve timing synchronization between Ethernet time-aware nodes.

Timestamps can be used for assessing network latency and synchronization-related measurements in modern communication networks. Accuracy can include a quality of being near to a true value. Timestamping error can include deviation in timestamped values of an event from its actual occurrence. Maximizing accuracy of timestamping in a network interface can be dependent on various factors. First, timestamping and identification of an SFD should be done as nearest to the physical medium as possible, to maximize timestamping accuracy. Second, an SFD field can be restricted to processing at a Medium Access Control (MAC) level on both transmit and receive portions of an Ethernet stack.

In various approaches for operations at a transmit side, an SFD can be timestamped at a MAC layer or logical layer. Then, the value of the SFD can be propagated through all the frame processing blocks of PHY or a physical layer until the value of the SFD reaches the serial data line on the medium. Such operation can introduce timestamping error due to timestamps at a layer different from a layer to which the time stamp corresponds. In various approaches for operations at a receive side, the SFD timestamping value is not directly available at PHY, because the physical line is serial and identification of sampled bits as SFD is prevented due to an encoded and scrambled state of the received data. To accommodate this restriction, a timestamping value can be estimated by subtracting latency of the receive side of the PHY stack from the time at which the SFD is first identified at the MAC layer. The estimation process introduces error into the timestamp, reducing the reliability of the timestamping process for application areas requiring high accuracy. Further, timestamping inaccuracies can be introduced in the receive path, due to the timestamping of each serial bit from the medium and then propagate its value through all frame processing layers of the PHY or physical layer of the receive side.

Present implementations provide a technical improvement that minimizes timestamping errors on the transmit and receive sides of network communication devices and interfaces, including an Ethernet stack. For example, the encoded value of SFD can be predetermined on the transmit side. The SFD value can be set to or associated with, for example, a 64/66 bit encoding of Spec IEEE 802.3-2018. Thus, a scrambler on a transmit side can advantageously be bypassed. The network communication interface or device can include a pattern detection logic to detect encoded SFD values, or any predetermined marker in network traffic, where the serial data is passes through the physical medium. For example, after the SFD is detected on a transmit side at the physical medium, the SFD can be timestamped and the network communication device or interface can issue an interrupt or callback. High accuracy can include, for example, the elimination of error corresponding to timestamps. This process provides the technical improvement of avoiding the scope of any timestamping error introduction, because propagation of timestamping value through the whole network communication stack is eliminated.

On the receive side, present implementations can include SFD pattern detection logic, to sample a serial data stream from the physical medium. For example, after the pattern detection logic detects the SFD detected, the SFD is timestamped and the network communication device or interface can issue an interrupt or callback. Present implementations can thus provide a technical improvement eliminating calculation of timestamp propagation estimation and any error introduced by that estimation, and eliminating timestamping each serial bit and propagating each bit to a MAC or logical layer to identify an SFD.

FIG.1illustrates a device, in accordance with present implementations. According to aspects of the present disclosure, the device can apply a timestamp to a packet of a device at a hardware layer and/or detect such a timestamp applied to a packet. As set forth above, applying a timestamp at a hardware layer can provide at least the technical improvement of eliminating timestamp error by eliminating a timestamp offset based on an estimation of propagation delay through a network architecture from a hardware layer where a packet is received, to a logical layer where timestamping occurs

As illustrated by way of example inFIG.1, a device100can include a transmit stack102, a receive stack104, an output node106, and an input node108. The transmit stack102and receive stack104can each include a plurality of layers. Each of the layers can correspond to various communication processing components of a network communication device or network communication interface. For example, the transmit stack102can include communication processing components corresponding to communication to send a transmission by the output node106, according at least partially to one or more Ethernet protocols. For example, the receive stack104can include communication processing components corresponding to communication to receive a transmission by the input node108, according at least partially to one or more Ethernet protocols. One or more of the input node106and the output node108can be operatively coupled with one or more external network communication devices, electronic or electrical devices, or any combination thereof.

The device100can include a physical or logical device, and can be integrated into a physical communication device or a verification device. A physical communication device can include one or more hardware elements to perform an electronic communication. For example, a physical communication device can include one or more of a portion of a solid state electronic device, a portion of an integrated circuit, and a chipset including one or more integrated circuit devices, or any combination thereof. For example, the physical communication device can be integrated into a handset, mobile computer, smartphone, or the like. A verification device can include a physical or virtual device, and can perform one or more testing operations during or in connection with operation of the device100. For example, the verification device can be configured to monitor one or more aspects of operation of the physical communication device.

The transmit stack102can include a physical communication layer110, a logical communication layer130, and a control layer150. The transmit stack102can perform a communication from the control layer150to the physical communication layer110. The receive stack104can include a physical communication layer112, a logical communication layer132, and a control layer152. The receive stack104can perform a communication from the physical communication layer112to the control layer152.

The physical communication layers110and112can include one or more electrical or electronic components to transmit or translate communication from the network communication device or interface to or from an external device or interface. For example, the control layer150can include one or more buffers, interrupt controllers, serializers, deserializers, or any combination thereof. For example, the physical communication layers110and112can include a Physical Medium Attachment (PMA) layer in accordance with an Ethernet communication protocol.

The physical communication layer110can include a pattern detector120. The pattern detector120can detect one or more predetermined patterns corresponding to one or more aspects of an input received at the pattern detector. For example, the pattern detector120can include one or more logical or physical components to detect a match between a particular predetermined sequence of bits and an input sequence of bits. For example, a sequence of bits can be received in binary or hexadecimal format. The pattern detector can include, for example a comparator device to determine whether a particular portion of an input to the pattern detector110matches a particular target sequence. The physical communication layer112can include a pattern detector122. The pattern detector122can correspond at least partially in one or more of structure and operation to the physical communication layer110. For example, the pattern detector122can detect one or more patterns detectable by the pattern detector120. The pattern detectors120and122can detect patterns compatible with an Ethernet protocol, and can identify a particular packet or particular portion of data based on the detected pattern.

The logical communication layer130can include one or more electrical or electronic components to transmit or translate communication across layers of the network communication device or interface. For example, the logical communication layer130can include a Physical Coding Sublayer (PCS) layer in accordance with an Ethernet communication protocol. A PHY physical layer can include a PCS layer and a PMA layer.

The logical communication layer130can include an encoder140. The encoder140can transform at least a portion of a data packet into a format compatible with the physical communication layer110. For example, the encoder140can generate an encoded block compatible with an Ethernet protocol. The logical communication layer132can include a decoder142. The decoder142can correspond at least partially in one or more of structure and operation to the encoder140. For example, the decoder142can perform a reverse, inverse, or converse of one or more encoding operations performable by the encoder140. For example, a sequential operation of the encoder and the decoder on a particular data packet or data object can return the original input data packet or data object.

The control layer150can include one or more electrical or electronic components to execute logical decision flows. For example, the control layer150can include one or more message handlers, authentication processors, data integrity validation components, or any combination thereof. For example, the control layer150can include a MAC layer in accordance with an Ethernet communication protocol.

FIG.2illustrates a system, in accordance with present implementations. As illustrated by way of example inFIG.2, a system200can include a first network device202, a second network device204, an input packet path210, a timestamped packet path212, a timestamped packet path214, and an output packet path220. The first network device202and the second network device204can each correspond to the device100. The first network device202can include the output node106, the input node108, the physical communication layer110, the logical communication layer130, the control layer150, the physical communication layer112, the logical communication layer132, and the control layer152. The second network device204can include a physical communication layer230, the logical communication layer250, the control layer260, the physical communication layer232, the logical communication layer252, and the control layer262, corresponding at least partially in one or more of structure and operation respectively to elements110,130,150,112,132and152. An input108of the first network device202can be operatively coupled with an output of the second network device204. An output106of the first network device202can be operatively coupled with an input of the second network device204. Thus, the first network device202and the second network device204can be operatively coupled to allow bidirectional communication there between.

The input packet path210can indicate a transmission path of a packet by the physical communication layer230of the second network device204to the physical communication layer112of the first network device202. The physical communication layer112can timestamp a packet at the physical communication layer112before transmission of the packet along the timestamped packet path. The timestamped packet path212can indicate a transmission path of a packet from the physical communication layer112of the first network device202to the control layer152of the first network device202. Thus, the packet traveling by the timestamped packet path212can include a timestamp usable by the first network device202or any external device coupled therewith that eliminates any introduction of error due to latency of travel of the packet by the timestamped packet path212.

The timestamped packet path214can indicate a transmission path of a packet from the control layer150of the first network device202to the physical communication layer110of the first network device202. Thus, the packet traveling by the timestamped packet path214can include a timestamp usable by the first network device202or any external device coupled therewith that eliminates any introduction of error due to latency of travel of the packet by the timestamped packet path212. The output packet220can indicate a transmission path of a packet by the physical communication layer110of the first network device202to the physical communication layer232of the second network device204. The physical communication layer232can timestamp a packet at the physical communication layer232before transmission of the packet along a timestamped packet path of the second network device204.

FIG.3Aillustrates a system, in accordance with present implementations. As illustrated by way of example inFIG.3A, a system300A can include the device100, a transmission310A with the logical layer, a transmission320A with the physical layer, and a transmission330with a pattern detector. The device100can include the output node106, the input node108, the physical communication layers110and112, the logical communication layers130and132, and the control layers150and152.

The control layer150can obtain an SFD block302from a data packet. For example, one or more of the data packet and the SFD block302can have a structure corresponding to a particular lane of a communication compatible with an Ethernet protocol. For example, the lane can be or include Lane 0. For example, the communication can be compatible with a 10 gigabit media-independent interface (XGMII) protocol. The SFD block302can include one or more hexadecimal characters. The control layer150can transmit the SFD block302to the logical communication layer130by transmission310A.

The logical communication layer130can transmit the SFD block302to the encoder140. The encoder140can transform the SFD block302into an encoded block304corresponding to a particular data structure, format, or any combination thereof. For example, the encoder140can encode the SFD block302according to a 49-7 64 bit/66 bit block format. For example, the encoder140can transform the SFD block302into an encoded SFD block304having a block post encoding. The logical communication layer130can transmit the encoded SFD block304to the physical communication layer110by transmission320B.

The physical communication layer110can transmit the encoded block304to the pattern detector120by transmission330. The pattern detector120can identify a pattern within the encoded SFD block304corresponding to a particular data sequence. The pattern detector120can transform the encoded SFD block304into a pattern block306. The pattern detector120can transform the encoded SFD block304by moving, shifting, reversing, or the like, bit positions of one or more bits of the encoded SFD block304. For example, the pattern detector120can transfer bit positions from the most significant bit position to the least significant bit position to generate the pattern block306. For example, the pattern detector120can transform hexadecimal 78 into hexadecimal 1E by reversing the binary bits from 0111_1000 to 0001_1110. For example, the pattern detector120can transform hexadecimal CC into hexadecimal 33 by reversing the binary bits from 1100_1100 to 0011_0011.

FIG.3Billustrates a system, in accordance with present implementations. As illustrated by way of example inFIG.3B, a system300B can include the device100, a transmission310B with the logical layer, a conversion transmission320B with the physical layer, and the transmission330with a pattern detector. The device100can include the output node106, the input node108, the physical communication layers110and112, the logical communication layers130and132, and the control layers150and152.

The control layer150can generate a split SFD block312from an SFD block302obtained from a data packet. For example, one or more of the data packet and the SFD block302can have a structure corresponding to a particular lane of a communication compatible with an Ethernet protocol. For example, the lane can be or include Lane 4. For example, the communication can be compatible with a 10 gigabit media-independent interface (XGMII) protocol. The split SFD block312can include one or more hexadecimal characters. The control layer150can split the SFD block302obtained having a Lane 4 structure at one or more points in the SFD block302. For example, the control layer150can split the SFD block302after an eight byte from the most significant byte of the SFD block302and transmit one or more splits to generate or obtain one or more split SFD blocks312. The control layer150can discard or ignore one or more byte addresses, including one or more bytes indicating a destination address for the SFD block302to generate or obtain the split SFD block312. The control layer150can transmit the split SFD block312to the logical communication layer130by transmission310B.

The logical communication layer130can transmit the split SFD block312to the encoder140. The encoder140can transform the split SFD block312into an encoded split SFD block314corresponding to a particular data structure, format, or any combination thereof. For example, the encoder140can encode the split SFD block312according to a 49-7 64 bit/66 bit block format. For example, the encoder140can transform the split SFD block312into an encoded split SFD block314having a block post encoding. For example, the encoder140can add two bits corresponding to a sync header to the least significant bits of the encoded split SFD block314. Further, the encoder140can encode a second portion of the SFD block302split from the SFD block302after the sync header bits, to generate or obtain a converted encoded block322. The logical communication layer130can transmit the converted encoded block322to the physical communication layer110by transmission330.

The physical communication layer110can transmit the converted encoded block322to the pattern detector120by transmission330. The pattern detector120can identify a pattern within the converted encoded block322corresponding to a particular data sequence. The pattern detector120can transform the converted encoded block322into a pattern block306. The pattern detector120can transform the converted encoded block322by moving, shifting, reversing, or the like, bit positions of one or more bits of the encoded SFD block304. For example, the pattern detector120can transfer bit positions from the most significant bit position to the least significant bit position to generate the pattern block306. For example, the pattern detector120can transform hexadecimal 78 into hexadecimal 1E by reversing the binary bits from 0111_1000 to 0001_1110. For example, the pattern detector120can transform hexadecimal CC into hexadecimal 33 by reversing the binary bits from 1100_1100 to 0011_0011. The transmissions310A,310B,320A,320B and330can be performed bidirectionally at either the transmit or receive stacks, through either of the layers110,130and150, or112,132and152.

FIG.4illustrates a packet architecture, in accordance with present implementations. As illustrated by way of example inFIG.4, a data packet400can include a preamble410, an SFD420, a destination MAC address430, a source MAC address432, an ethertype434, a payload440, and an FCS450. The structure of the data packet400can correspond to a data packet compatible with an Ethernet protocol, for example.

FIG.5illustrates a pattern architecture, in accordance with present implementations. As illustrated by way of example inFIG.5, a pattern architecture500can include a first pattern architecture510, and a split pattern architecture520.

Present implementations can include a Start of Frame Delimiter (SFD) pattern detector120to perform accurate and error-free timestamping. A scrambler device of a network communication device or interface can be bypassed and detection can be performed on an encoded value of SFD determined based on an encoding architecture. An encoding architecture can correspond to an encoding table compatible with an Ethernet protocol. For example, an SFD block can be detected based on a pattern of a data packet detected matching or corresponding to a first pattern architecture510. The first pattern architecture510can correspond to a Lane 0 pattern as discussed herein. For example, an SFD block can be detected based on a pattern of a data packet detected matching or corresponding to a second pattern architecture520. The second pattern architecture520can correspond to a Lane 4 pattern as discussed herein.

This technical solution can thus provide multiple technical improvements, including at least the below. For example, this technical solution can minimize timestamping errors on transmit and receive sides of Ethernet stacks. For example, this technical solution can eliminate overhead caused by propagating a timestamp value through a network communication device or interface stack. For example, this technical solution can eliminate hardware or logic to timestamp each serial data on receive side, including eliminating calculation on the receive side to retrieve a timestamp value. For example, this technical solution can be scaled to detect any special marker in a data packet or data communication, and is not limited to pattern detection based on a Start of Frame Delimiter (SFD) for packet timestamping purposes. Present implementations can advantageously be applied at least in Ethernet design and verification systems and devices.

FIG.6illustrates a method600of high accuracy timestamping of transmissions at a physical layer, in accordance with present implementations. The device or system100,200,300A or300B can perform method600according to present implementations. The method600can begin at610.

At610, the method600can obtain a data packet at the physical communication layer.610can include at least one of612,614,616, and618. At612, the method600can obtain a data packet at a physical communication layer integrated with the network communication interface. At614, the method600can obtain a data packet including one or more of a frame and a marker. At616, the method600can obtain a data packet from a logical communication layer of the network communication interface in a transmit operation. At618, the method600can obtain a data packet from a second physical communication layer integrated with the external network communication interface, in a receive operation. The method600can then continue to620.

At620, the method600can split at least a portion of the data packet.620can include at least one of622,624, and626. For example, the control layer or the logical communication layer can split an SFD block at a particular bit or byte address location into two or more split SFD blocks. The control layer or the logical communication layer can then transmit one or more of the splits to another components of a network communication device or interface. At622, the method600can split the data packet by the logical communication layer of network communication interface. At624, the method600can split the data packet in response to the determination that the SFD of the data packet has a particular lane type. For example, the control layer or the logical communication layer can split the packet upon a determination that the packet corresponds to an Ethernet communication compatible with a Lane 4 data structure, and can block or limit a split of the SFD block upon a determination that the packet corresponds to an Ethernet communication compatible with a Lane O data structure At626, the method600can split the data packet into a first block and second block. The method600can then continue to702.

FIG.7illustrates a method700of high accuracy timestamping of transmissions at a physical layer further to the method ofFIG.6. The device or system100,200,300A or300B can perform method700according to present implementations. The method700can begin at702. The method700can then continue to710.

At710, the method700can detect a marker from the portion of data in the data packet.710can include at least one of712,714,716, and718. At712, the method700can detect a marker by the detection circuit integrated with the physical communication layer. The marker can include, but is not limited to, an SFD block compatible with an Ethernet protocol. At714, the method700can detect a marker identifying the data packet. At716, the method700can detect the marker based on the digital pattern matching the marker. At718, the method700can detect the marker within the first block or the second block. The method700can then continue to720.

At720, the method700can trigger an interrupt in response to detecting a marker.720can include722. At722, the method700can generate an interrupt by the physical communication layer. The interrupt can trigger a timestamp operation to write a timestamp to a portion of the packet or to read a timestamp from the packet. The method700can then continue to802.

FIG.8illustrates a method800of high accuracy timestamping of transmissions at physical layer further to the method ofFIG.7. The device or system100,200,300A or300B can perform method800according to present implementations. The method800can begin at802. The method800can then continue to810.

At810, the method800can link a timestamp with the data packet using the physical communication layer.810can include at least one of812and814. At812, the method800can embed a timestamp at the start frame delimiter of the data packet. At814, the method800can link a timestamp with the data packet in response to detecting an interrupt. The method800can then continue to820.

At820, the method800can transmit the data packet with a timestamp using the physical communication layer.820can include at least one of822and824. At822, the method800can transmit the data packet from the physical communication layer to the logical communication layer of the network communication interface. At824, the method800can transmit the data packet from the physical communication layer to a second physical communication layer integrated with an external network communication interface. The method800can end at820.

The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are illustrative, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable,” to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

With respect to the use of plural and/or singular terms herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. The various singular/plural permutations may be expressly set forth herein for sake of clarity.

It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.).

Although the figures and description may illustrate a specific order of method steps, the order of such steps may differ from what is depicted and described, unless specified differently above. Also, two or more steps may be performed concurrently or with partial concurrence, unless specified differently above. Such variation may depend, for example, on the software and hardware systems chosen and on designer choice. All such variations are within the scope of the disclosure. Likewise, software implementations of the described methods could be accomplished with standard programming techniques with rule-based logic and other logic to accomplish the various connection steps, processing steps, comparison steps, and decision steps.

It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should typically be interpreted to mean “at least one” or “one or more”). The same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, typically means at least two recitations, or two or more recitations).

Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general, such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B.”

Further, unless otherwise noted, the use of the words “approximate,” “about,” “around,” “substantially,” etc., mean plus or minus ten percent.

The foregoing description of illustrative implementations has been presented for purposes of illustration and of description. It is not intended to be exhaustive or limiting with respect to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the disclosed implementations. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.