Patent ID: 12211701

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments are described below with respect to a semiconductor manufacturing process node such as a 20 nm process node, a 9 nm process node, a 7 nm process node, or the like, in which a metal gate may be fabricated using an implantation process in order to enhance the metal gate and channel performance. However, the embodiments described may be utilized in a wide variety of processes and devices, and are not limited to the embodiments listed above.

With reference now toFIGS.1A-1B, there is illustrated a semiconductor device100which includes a substrate101with fins103(denoted as separate from the rest of the substrate101by dashed line102) located between first trenches105formed within the substrate101, and first isolation regions107within the first trenches105. In an embodiment the substrate101may comprise, for example, bulk silicon, doped or undoped, germanium, a III-V material (such as gallium arsenide, indium arsenide, or the like), or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used.

The fins103and the first trenches105may be formed from the substrate101. In an embodiment the fins103may be formed from the substrate101by initially forming a patterned mask (not separately illustrated inFIGS.1A-1B) over the substrate101. The material of the patterned mask, such as silicon nitride, silicon oxide, combinations of these, or the like, is subsequently patterned using, for example, photolithography techniques. Generally, photolithography techniques involve depositing a photoresist material and irradiating the photoresist material in accordance with a pattern. Thereafter, the photoresist material is developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material during subsequent processing steps, such as etching. In this case, the photoresist material is utilized to create the patterned mask to define the fins103and the first trenches105.

Once the patterned mask has been formed, the fins103may be formed using a subtractive etching process along with the patterned mask106in order to form a raised portion with sidewalls, wherein the sidewalls may comprise a (001) surface. For example, exposed portions of the substrate101may be etched to form the fins103and the first trenches105from the substrate101. In an embodiment the substrate101may be etched by, for example, HBr/O2, HBr/Cl2/O2, or SF6/C12plasma. In an embodiment the fins103may be patterned such that it will eventually be used for a channel in a semiconductor device such as a fin field effect transistor (FinFET).

However, as one of ordinary skill in the art will recognize, the subtractive process described above to form the fins103is intended to be illustrative and is not intended to limit the embodiments. Rather, any suitable process, such as an epitaxial growth process using the substrate101and a mask, may be utilized to form the fins103. Any suitable process for forming the fins103from the substrate101may be utilized, and all such processes are fully intended to be included within the scope of the embodiments.

Once the first trenches105and the fins103have been formed, the first trenches105may be filled with a dielectric material and the dielectric material may be recessed within the first trenches105to form the first isolation regions107. The dielectric material may be an oxide material, a high-density plasma (HDP) oxide, or the like. The dielectric material may be formed, after an optional cleaning and lining of the first trenches105, using either a chemical vapor deposition (CVD) method (e.g., the HARP process), a high density plasma CVD method, or other suitable method of formation as is known in the art.

The first trenches105may be filled by overfilling the first trenches105and the substrate101with the dielectric material and then removing the excess material outside of the first trenches105and the fins103through a suitable process such as chemical mechanical polishing (CMP), an etch, a combination of these, or the like. In an embodiment, the removal process removes any dielectric material that is located over the fins103as well, so that the removal of the dielectric material will expose the surface of the fins103to further processing steps.

Once the first trenches105have been filled with the dielectric material, the dielectric material may then be recessed away from the surface of the fins103. The recessing may be performed to expose at least a portion of the sidewalls of the fins103adjacent to the top surface of the fins103. The dielectric material may be recessed using a wet etch by dipping the top surface of the fins103into an etchant such as HF, although other etchants, such as H2, and other methods, such as a reactive ion etch, a dry etch with etchants such as NH3/NF3, chemical oxide removal, or dry chemical clean may be used. The dielectric material may be recessed to a distance from the surface of the fins103of between about 50 Å and about 500 Å, such as about 400 Å. Additionally, the recessing may also remove any leftover dielectric material located over the fins103to ensure that the fins103are exposed for further processing.

As one of ordinary skill in the art will recognize, however, the steps described above may be only part of the overall process flow used to fill and recess the dielectric material. For example, lining steps, cleaning steps, annealing steps, gap filling steps, combinations of these, and the like may also be utilized to form and fill the first trenches105with the dielectric material. All of the potential process steps are fully intended to be included within the scope of the present embodiment.

FIG.2illustrates a placement of an interfacial layer201, a high-k dielectric layer203, and a first metal layer205over the fins103. In an embodiment the interfacial layer201is utilized to reduce damage between the fins103and, e.g., the high-k dielectric layer203(described further below). In an embodiment the interfacial layer201comprises a buffer material such as silicon oxide, although any suitable material may be utilized. The interfacial layer201may be formed using a process such as CVD, PVD, or even oxidation of the fins103to a thickness of between about 1 Å and about 20 Å, such as about 9 Å. However, any suitable process or thicknesses may be utilized.

Once the interfacial layer201has been formed, the high-k dielectric layer203may be formed over the interfacial layer201. In an embodiment the high-k dielectric layer203is a high-k material such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations of these, or the like, deposited through a process such as atomic layer deposition, chemical vapor deposition, or the like. The high-k dielectric layer203may be deposited to a thickness of between about 5 Å and about 200 Å, such as about 16 Å, although any suitable material and thickness may be utilized.

The first metal layer205may be formed adjacent to the high-k dielectric layer203and may be formed from a metallic material such as TiN, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, Ti, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. The first metal layer205may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like, to a thickness of between about 5 Å and about 200 Å, such as about 16 Å, although any suitable deposition process or thickness may be used.

FIG.3illustrates that, after the first metal material205has been formed, a first anneal process (represented inFIG.3by the wavy lines labeled301) may be performed. In an embodiment the first anneal process301may be a thermal anneal wherein the substrate101is heated within, e.g., a furnace, within an inert atmosphere. The first anneal process301may be performed at a temperature of between about 600° C. and about 900° C., such as about 850° C., and may be continued for a time of between about 1 s and about 1 min, such as about 0.5 min.

FIG.4illustrates that, once the first anneal process301has been completed, a capping layer401is formed over the first metal layer205in order to protect the underlying first metal layer205from being damaged in subsequent processing. In an embodiment the capping layer401is silicon, although other suitable materials, such as SiN, SiCN, SiON, SiC, Si-rich oxide, combinations thereof, or the like, may be utilized, and the capping layer401may be formed by CVD, spin-on-glass process, flow-able CVD, atomic layer deposition (ALD), molecular layer deposition (MLD), or the like. The capping layer401may be formed to a thickness of between about 5 Å and about 40 Å, such as about 30 Å. However, any other suitable materials, processes, and thicknesses may be utilized.

FIGS.5A-5Billustrate an implantation process (represented inFIG.5Aby the lines labeled501) that is utilized to help incorporate a first dopant into the fins103, the interfacial layer201, the high-k dielectric layer203, and the first metal layer205by initially implanting the first dopant into the capping layer401. In an embodiment the first dopant is a material which can help to reduce the number of oxygen vacancies, reduce the number of silicon dangling bonds, or help to mitigate weak silicon-hydrogen bonding, each of which can degrade the overall performance of the semiconductor device100. For example, in embodiments in which the fins103, the first metal layer205is titanium nitride, the high-k dielectric layer203is hafnium oxide, and the interfacial layer201is silicon oxide, the first dopant to be implanted may be fluorine, although any other suitable dopants, such as carbon and nitrogen, may be utilized.

FIG.5Billustrates an ion implanter500which may be utilized during the ion implantation process501to implant the first dopant into the capping layer401. In an embodiment the ion implanter500may include an ion source516a mass analysis magnet503, a linear accelerator505, a convergence unit502, an aperture517, an end station507, a wafer handling unit509and a controller511to control the operation of the ion implanter500. Each of these pieces will be discussed in the following paragraphs.

The ion source516produces an ion beam513. However, as the ion source516produces ions having a range of charge-to-mass ratio, and only a certain range of ions are suitable for implantation, the ion beam513is directed towards the mass analysis magnet503in order to electromagnetically separate those ions having a desired charge-to-mass ratio for implantation from those ions having an undesired charge-to-mass ratio. Once a coherent ion beam515of suitable charge-to-mass ratio is obtained, the coherent ion beam515is sent to the linear accelerator505.

The linear accelerator505is used to impart additional energy to the coherent ion beam515as it passes through the linear accelerator505. The linear accelerator505imparts this additional energy using a series of electrodes (not shown) that generate an electromagnetic field which, when the coherent ion beam515passes through the field, works to accelerate the coherent ion beam515. The linear accelerator505may vary the electromagnetic fields periodically with time or may adjust the phase of the electromagnetic fields to accommodate ions with different atomic numbers as well as ions having different initial speeds.

After the coherent ion beam515is passed through the linear accelerator505, the coherent ion beam515is passed through the converging unit502, which is utilized to modify the convergence and divergence of the coherent ion beam515(which arrives from the linear accelerator505as a substantially parallel beam). In an embodiment the converging unit502comprises one or more (such as three) multipole lenses, such as a uniformity multipole lens and a collimator multipole lens. However, any suitable number and type of lenses may be utilized.

In a particular embodiment the converging unit502comprises one or more quadrupole lenses. For example, the converging unit502may comprise three quadrupole lenses, such as a first quadrupole lens504, a second quadrupole lens506, and a third quadrupole lens508. Each of the first quadrupole lens504, the second quadrupole lens506, and the third quadrupole lens508may separately be a magnetic field lens or an electric field lens. However, any suitable unit which can modify the convergence and divergence of the coherent ion beam515may be utilized.

In a particular embodiment in which the first quadrupole lens504is an electric field lens, the first quadrupole lens504comprises a first pair of electrodes510opposite each other in a first direction and a second pair of electrodes512opposite each other in a second direction perpendicular to the first direction. As such, by varying the electrical potential to the first pair of electrodes510, a first repulsive or attractive force can be applied to the individual ions within the coherent ion beam515in the first direction. Additionally, by varying the electrical potential to the second pair of electrodes512, a second repulsive or attractive force can be applied to the individual ions within the coherent ion beam515in the second direction. As such, the control and application of the first quadrupole lens504helps to control the convergence and divergence of the ions within the coherent ion beam515.

Additionally, the second quadrupole lens506may be similar to the first quadrupole lens504(e.g., may have a first pair of electrodes and a second pair of electrodes), but may be controlled to apply electrical potentials that are opposite than the electrical potentials applied to the first pair of electrodes510and the second pair of electrodes512(within the first quadrupole lens504). As such, the second quadrupole lens506can help to modify the coherent ion beam in the first direction and the second direction opposite the first quadrupole lens504.

Finally, in an embodiment in which the converging unit502utilizes the third quadrupole lens508, the third quadrupole lens508may be similar to the first quadrupole lens504. For example, the third quadrupole lens508may have a first pair of electrodes and a second pair of electrodes, and may be controlled by applying electrical potentials that are similar, if not the same, as the electrical potentials applied to the first pair of electrodes510and the second pair of electrodes512(within the first quadrupole lens504). However, in other embodiments the third quadrupole lens508may be different from the first quadrupole lens504.

After the coherent ion beam515has passed through the converging unit502, the coherent ion beam515passes through an aperture517in order to further enhance and control the divergence of the coherent ion beam515. In an embodiment the aperture517is an aperture with an adjustable width that can adjust the magnitude of the coherent ion beam515. For example, the aperture517may comprise adjustable and movable plates such that a spacing between the plates can be adjusted, thereby allowing for an adjustment of the beam current magnitude.

Additionally, if desired, a chicane (not separately illustrated inFIG.5B) may be utilized between the converging unit502and the end station507. In an embodiment the chicane is utilized to direct and bend the path of the coherent ion beam515to the desired finalized location (e.g., onto the substrate101). However, any suitable device may be utilized.

Once the coherent ion beam515has been accelerated (through the linear accelerator505) and the divergence of the coherent ion beam515has been modified (through the convergence unit502), the coherent ion beam515is directed towards the end station507. The end station507may house the wafer handling unit509, which handles the substrate101which will be implanted with ions from the coherent ion beam515. The wafer handling unit509is utilized to move the substrate101in relation to the coherent ion beam515so as to illuminate different sections of the substrate101with the coherent ion beam515. For example, the wafer handling unit509may comprise two motors (not shown) which may be used to control the position of the substrate101in at least two directions, such as an x-direction and a y-direction, relative to the coherent ion beam515.

However, as one of ordinary skill in the art will recognize, moving the substrate101in relation to the coherent ion beam515is merely one exemplary method of illuminating different sections of the substrate101with the coherent ion beam515. Other suitable methods, such as the use of deflection electrodes along the path of the coherent ion beam515to shift the direction of the coherent ion beam515in relation to the substrate101instead of shifting the substrate101in relation to the coherent ion beam515, using a multiple wafer rotating system to illuminate multiple wafers in order, or using angular implantation methods, may also be utilized. These methods, and any other suitable method for illuminating different portions of the substrate101with the coherent ion beam515, are fully intended to be included within the scope of the present disclosure.

The controller511is used to control the operating parameters of the ion implanter500during operation. The controller511may be implemented in either hardware or software, and the parameters may be hardcoded or fed into the controller511through an input port. The controller511may be used to store and control parameters associated with the operation of the ion implanter500, such as the desired ion beam current, the current to the accelerator electrodes, and the like. Additionally, the controller511may also be used to control the wafer handling unit509and, more specifically, the velocity of the motors of the wafer handling unit509, which, in turn, control the velocity of the substrate101with respect to the coherent ion beam515.

With reference now to bothFIGS.5A-5B, in order to implant the first dopant (e.g., fluorine ions) into the capping layer401, the substrate101is placed on the wafer handling unit509and the coherent ion beam515is generated. Additionally, as the coherent ion beam515passes through the convergence unit502and the aperture517, the coherent ion beam515is turned into a divergent ion beam519. In an embodiment the divergent ion beam519has an intensity divergence from parallel of between about ±0.1° to about ±20°, such as about ±10°. However, any suitable divergence that is greater than 0° may be utilized.

Additionally, the ion implantation process501may be performed at an energy level that allows for an implantation of the first dopants into the capping layer401, but helps to minimize or prohibit damage being done to the underlying layers (e.g., the first metal layer205, the high-k dielectric layer203, the interfacial layer201, and the fins103). For example, in an embodiment the ion implantation process501may be performed with a sub-keV implantation, such as about 300 eV. However, any suitable implantation power may be utilized.

By utilizing the divergent ion beam519(instead of a parallel ion beam), a better conformality of the first dopants may be achieved within the capping layer401. For example, in an embodiment the first dopants may be implanted within the capping layer401at an area concentration of the ion implanter at a tilt of zero degrees of between about 5×1013atoms/cm2and about 5×1015atoms/cm2, such as about 8×1014atoms/cm2.

FIG.6illustrates that, after the first implantation process501has been formed, a second anneal process (represented inFIG.6by the wavy lines labeled601) may be performed in order to drive the first dopants from the capping layer401and into one or more of the first metal layer205, the high-k dielectric layer203, the interfacial layer201, and the fins103. In an embodiment the second anneal process601may be a spike anneal wherein the substrate101is heated within, e.g., a furnace, within an inert atmosphere. The second anneal process601may be performed at a temperature of between about 800° C. and about 1000° C., such as about 903° C., and may be continued for a time of between about 0.5 s and about 1 min, such as about 1 sec.

By using the second anneal process601the first dopants that were previously implanted into the capping layer401may be driven from their location (wherein they were implanted) within the capping layer401and into one or more of the first metal layer205, the high-k dielectric layer203, the interfacial layer201, and the fins103. As such, by utilizing a diffusion process to place the first dopants into the first metal layer205, the high-k dielectric layer203, the interfacial layer201, and the fins103, a different non-zero concentration gradient is formed within each of the first metal layer205, the high-k dielectric layer203, the interfacial layer201, and the fins103.

For example, in an embodiment in which the first metal layer205is titanium nitride and the first dopant is fluorine, the first metal layer205may have a first surface (facing towards the capping layer401) that has a first concentration of between about 1×1020/cm3and about 1×1022/cm3, such as about 1×1021/cm3. Additionally, the first metal layer205has a second surface (e.g., facing away from the capping layer401and towards the high-k dielectric layer203) which has a second concentration that is lower than the first concentration, such as having a second concentration of between about 1×1019/cm3and about 1×1021/cm3, such as about 1×1020/cm3, for a concentration gradient through the first metal layer205that has a minimum concentration of about 1×1021/cm3and a maximum concentration of about 1×1020/cm3, such as about 5×1020/cm3. However, any suitable concentration may be utilized.

Also, in embodiments in which the first dopants extend into the high-k dielectric layer203, a concentration gradient may also be seen in the high-k dielectric layer203. For example, in an embodiment in which the first dopant is fluorine and the high-k dielectric layer203is hafnium oxide, the high-k dielectric layer203has a third surface (facing towards the first metal layer205) that has a third concentration of between about 1×1019/cm3and about 1×1021/cm3, such as about 1×1020/cm3. Additionally, the high-k dielectric layer203has a fourth surface (e.g., facing away from the first metal layer205) which has a fourth concentration that is lower than the third concentration, such as having a fourth concentration of between about 1×1019/cm3and about 1×1020/cm3, such as about 5×1019/cm3, for a concentration gradient through the high-k dielectric layer203of between about 1×1020/cm3and about 5×1019/cm3, such as about 7×1019/cm3. However, any suitable concentration may be utilized.

Additionally, in embodiments in which the first dopants extend into the interfacial layer201, a concentration gradient may also be seen in the interfacial layer201. For example, in an embodiment in which the first dopant is fluorine and the interfacial layer201is silicon dioxide, the interfacial layer201has a fifth surface (facing towards the high-k dielectric layer203) that has a fifth concentration of between about 1×1018/cm3and about 1×1019/cm3, such as about 5×1018/cm3. Additionally, the interfacial layer201has a sixth surface (e.g., facing away from the high-k dielectric layer203) which has a sixth concentration that is lower than the fifth concentration, such as having a sixth concentration of between about 1×1018/cm3and about 1×1019/cm3, such as about 3×1018/cm3, for a concentration gradient through the interfacial layer201of between about 5×1018/cm3and about 3×1018/cm3, such as about 4×1018/cm3. However, any suitable concentration may be utilized.

Finally, in embodiments in which the first dopants extend into the fins103, a concentration gradient may also be seen in the fins103. For example, in an embodiment in which the first dopant is fluorine and the fins103are silicon, the fins103have a seventh surface (facing towards the interfacial layer201) that has a seventh concentration of between about 1×1018/cm3and about 1×1019/cm3, such as about 3×1018/cm3. Additionally, the concentration of the first dopants within the fins103will continue to decrease in a direction away from the seventh surface until the concentration reaches zero. In a particular embodiment the first dopants will diffuse into the fins103a distance of between about 1 nm and about 5 nm, such as about 2 nm, for a concentration gradient through the fins103of between about 3×1018/cm3and about 5×1017/cm3, such as about 1×1018/cm3. However, any suitable concentration and depth may be utilized.

By implanting the fluorine into each of the different layers, multiple issues may be resolved simultaneously. For example, with respect to embodiments in which the interfacial layer201is silicon dioxide and the fins103are silicon, the interface between the silicon dioxide and the silicon can be strengthened. For example, by replacing bonds such as a silicon-hydrogen bond (which may have a bond strength of about 3.18 eV) with bonds that are stronger, such as a silicon-fluorine bond (which may have a bond strength of about 5.73 eV), the bonding between the fins103and the interfacial layer201may be strengthened. As such, the overall interface passivation will also be strengthened.

Additionally, by diffusing the first dopant (e.g., fluorine) into the high-k dielectric layer203, the first dopant will also spontaneously passivate oxygen vacancies Vowhich can occur within the high-k dielectric layer203. For example, in an embodiment in which the high-k dielectric layer203is hafnium oxide, by spontaneously reacting fluorine that is diffusing through the high-k dielectric layer203with oxygen vacancies Vowhich are already present, the fluorine will be substituted for the oxygen vacancies Voin an exothermic reaction that releases 2.5 eV. As such, the number of oxygen vacancies Vowill be reduced or eliminated within the high-k dielectric layer203, thereby also reducing or eliminating any remaining gap states within the high-k dielectric layer203.

Finally, by using the divergent ion beam519to produce a more conformal implantation into the capping layer401, and then driving the first dopant into the fins103, the concentration of the first dopant within the first sidewalls of the fins103will see an increase in the concentration of the first dopants. For example, by using the divergent ion beam519and processes described above, the concentration of the first dopants along the sidewalls of the fins103may be increased between about 3% and about 4% from the sidewall concentration that would be obtained without the divergent ion beam519. As such, a more conformal doping of the fins103(e.g., between the top and sidewalls of the fins103) may be obtained, such as a conformality of less than about 3×1020/cm3.

By utilizing the first dopant, all of these issues may be resolved or mitigated. As such, the channel resistance (Rch) of devices formed from the fins103may see an improvement. For example, in an n-type ultra-low voltage threshold device the channel resistance Rch may be improved from 1.42 kΩ/fin to about 1.32 kΩ/fin. Additionally, in a p-type ultra-low voltage threshold device, the channel resistance Rch may be improved from about 2.3 kΩ/fin to about 1.98 kΩ/fin.

FIG.7illustrates that, after the second anneal601has been performed, the capping layer401may be removed. In an embodiment the removal of the capping layer401may be performed using, e.g., an etching process such as a wet etching process or dry etching process, which utilizes etchants that are selective to the material of the capping layer401. For example, in an embodiment in which the capping layer401is silicon, the capping layer401may be removed using a wet etching process with an etchant such as dilute-HF. However, any suitable removal process may be utilized.

By utilizing the capping layer401to receive the implantation of the first dopants and then removing the capping layer401, damage from the ion implantation process501may be avoided within the first metal layer205, the high-k dielectric layer203, the interfacial layer201, and the fins103within the final structure of the semiconductor device100. In particular, any damage from the ion implantation process501will be mostly limited to within the capping layer401, which is subsequently removed after the transference of the first dopants from the capping layer401.

Optionally, after the diffusion of the first dopants, the fins103may be doped in order to form source/drain regions. In an embodiment an n-type dopant or p-type dopant (depending upon the desired device) may be implanted into the fins103. Additionally, once the n-type dopants or p-type dopants have been implanted, an activation anneal may be performed to activate the p-type and/or n-type dopants that were implanted. In an embodiment the activation anneal may be performed at a temperature of between about 700° C. and about 1000° C., such as about 850° C. However, any suitable temperature may be utilized.

Additionally, once the capping layer401has been removed, additional steps may be performed in order to incorporate the structure comprising the fins103into a functional, fully connected integrated circuit. For example, metallization layers (not illustrated) may be formed over the fins103while contacts (not illustrated) may be dropped down to make electrical connection with the fins103and the first metal layer205, and the overall structure may be utilized to form more complex devices, such as a ring oscillator (RO) or a pulse controlled modulator (PCM). In embodiments in which the fins103are incorporated into a ring oscillator, the ring oscillator may see a benefit in DC performance, like Ioncurrent, from a base target as measured through an electrical test key of between about 1% (from 70% to about 71%) and about 2%, such as about 1.6% because of the better passivation and higher mobility which reduces the channel resistance of the fins103.

In an embodiment, a method includes implanting dopants into a capping layer, the capping layer located over a first metal layer, a first dielectric layer, and a semiconductor fin, wherein the implanting the dopants is performed with a divergent ion beam; and driving the dopants from the capping layer into the first dielectric layer through the first metal layer. In an embodiment the driving the dopants further comprises driving the dopants into an interfacial layer located between the first dielectric layer and the semiconductor fin. In an embodiment the dopants comprise fluorine. In an embodiment the divergent ion beam has a beam intensity that is greatest at ±10°. In an embodiment the method further includes removing the capping layer after the driving the dopants from the capping layer into the first dielectric layer. In an embodiment the capping layer comprises silicon. In an embodiment the first dielectric layer comprises hafnium oxide.

In another embodiment, a method of manufacturing a semiconductor device includes forming a fin over a semiconductor substrate; applying a first dielectric layer over the fin; applying a first metal layer over the first dielectric layer; applying a capping layer over the first metal layer; implanting dopants into the capping layer using a divergent ion beam; driving the dopants into the first metal layer; and removing the capping layer. In an embodiment the driving the dopants into the first metal layer is performed at least in part with an anneal. In another embodiment the anneal is a spike anneal. In an embodiment the implanting the dopants into the capping layer damages the capping layer without damaging the first metal layer. In an embodiment the divergent ion beam has a beam intensity that is greatest at ±10°. In an embodiment the first metal layer has a first concentration gradient of the dopants. In an embodiment the first dielectric layer has a second concentration gradient of the dopants different from the first concentration gradient.

In another embodiment, a semiconductor device includes a semiconductor fin over a substrate; an interfacial layer over the semiconductor fin, the interfacial layer having a first non-zero concentration gradient of a first dopant; a high-k dielectric layer over the interfacial layer, the high-k dielectric layer having a second non-zero concentration gradient of the first dopant; and a first metal layer over the high-k dielectric layer, the first metal layer having a third non-zero concentration gradient of the first dopant. In an embodiment the first dopant is fluorine. In an embodiment the interfacial layer comprises silicon oxide. In an embodiment the high-k dielectric layer comprises hafnium oxide. In an embodiment the first metal layer comprises titanium nitride. In an embodiment the high-k dielectric layer is free from implantation damage.

In another embodiment, a method of manufacturing a semiconductor device includes generating an ion beam; modifying a convergence of the ion beam to generate a divergent ion beam; implanting ions from the divergent ion beam into a capping layer, the capping layer being located over a first metal layer and a first dielectric layer; and driving ions from the capping layer into the first metal layer and the first dielectric layer. In an embodiment the divergent ion beam has a beam intensity that is greatest at ±10°. In an embodiment the divergent ion beam comprises fluorine ions. In an embodiment the method further includes removing the capping layer after the driving the ions from the capping layer into the first metal layer.

In another embodiment, a method of manufacturing a semiconductor device includes forming a capping layer over a first metal layer, the first metal layer being over a semiconductor fin; implanting a dopant into the capping layer, wherein after the implanting the dopant into the capping layer, wherein a conformality of a dopant concentration after the implanting the dopant into the capping layer is less than about 3×1020/cm3; and annealing the capping layer after the implanting the dopant into the capping layer, wherein the annealing the capping layer drives the dopants through the first metal layer. In an embodiment, during the annealing the capping layer an exothermic reaction occurs in a dielectric layer located between the capping layer and the semiconductor fin. In an embodiment the implanting the dopant is performed with a divergent ion beam.

In another embodiment, a semiconductor device includes a semiconductor fin over a substrate, the semiconductor fin comprising a first element; an interfacial layer over the semiconductor fin, the interfacial layer comprising a second element and a first dopant, the first dopant having a silicon bond strength greater than a bond strength between the first element and the second element; a high-k dielectric layer over the interfacial layer, the high-k dielectric layer having a first concentration gradient of the first dopant; and a first metal layer over the high-k dielectric layer, the first metal layer having a second concentration gradient of the first dopant. In an embodiment the first dopant is fluorine. In an embodiment the high-k dielectric layer is hafnium oxide.

In another embodiment, a semiconductor device includes a semiconductor fin over a substrate; an interfacial layer extending along sidewalls and a top surface of the semiconductor fin, the interfacial layer having a first concentration of a first dopant; a dielectric layer over the interfacial layer, the dielectric layer having a second concentration of the first dopant; and a first metal layer over the dielectric layer, the first metal layer having a third concentration of the first dopant.

In another embodiment, a semiconductor device includes isolation regions over a substrate; a semiconductor fin between adjacent isolation regions; an interfacial layer in physical contact with sidewalls and a topmost surface of the semiconductor fin; a high-k dielectric layer over the interfacial layer; a first metal layer over the high-k dielectric layer; and a first dopant in the semiconductor fin, the interfacial layer, the high-k dielectric layer, and the first metal layer, a concentration of the first dopant in the first metal layer decreasing along a first direction, the first direction extending from a topmost surface of the first metal layer toward the topmost surface of the semiconductor fin.

In another embodiment, a semiconductor device includes: a semiconductor fin over a substrate; and a gate structure over the semiconductor fin, wherein the gate structure includes: a gate dielectric layer extending along sidewalls and a top surface of the semiconductor fin, the gate dielectric layer having a first concentration of a first dopant; and a metal layer over the gate dielectric layer, the metal layer having a second concentration of the first dopant, wherein the second concentration is different from the first concentration.

In another embodiment, a semiconductor device includes: isolation regions over a substrate; a semiconductor fin between adjacent isolation regions; and a gate structure over the semiconductor fin, wherein the gate structure includes: a gate dielectric layer extending along sidewalls and a top surface of the semiconductor fin; a metal layer over the gate dielectric layer; and a first dopant in the gate dielectric layer and the metal layer, where a concentration of the first dopant in the metal layer decreases along a first direction, and where the first direction extends from a top surface of the metal layer toward the top surface of the semiconductor fin.

In another embodiment, a method includes: forming a semiconductor fin over a substrate; and forming a gate structure over the semiconductor fin, wherein forming the gate structure includes: forming a gate dielectric layer along sidewalls and a top surface of the semiconductor fin; forming a metal layer over the gate dielectric layer; forming a capping layer over the metal layer; implanting first dopants into the capping layer; and performing an annealing process to drive the first dopants from the capping layer into the gate dielectric layer through the metal layer, where a concentration of the first dopants in the metal layer decreases along a first direction, and where the first direction extends from a top surface of the metal layer toward the top surface of the semiconductor fin.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.