Patent ID: 12237027

DESCRIPTION OF THE EMBODIMENTS

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For the sake of easy understanding, the same elements in the following description will be denoted by the same reference numerals.

In the text, the terms mentioned in the text, such as “comprising”, “including”, “containing” and “having” are all open-ended terms, i.e., meaning “including but not limited to”.

When using terms such as “first” and “second” to describe elements, it is only used to distinguish the elements from each other, and does not limit the order or importance of the devices. Therefore, in some cases, the first element may also be called the second element, the second element may also be called the first element, and this is not beyond the scope of the present invention.

In addition, the directional terms, such as “on”, “above”, “under” and “below” mentioned in the text are only used to refer to the direction of the drawings, and are not used to limit the present invention

FIG.1Ais a schematic cross-sectional view of an anti-fuse memory cell in an anti-fuse memory of the first embodiment of the present invention.FIG.1Bis a layout diagram of the anti-fuse memory cell inFIG.1A.

Referring toFIGS.1A and1B, in the present embodiment, an anti-fuse memory includes an anti-fuse memory cell10. The anti-fuse memory cell10includes a substrate100, an isolation structure102, a select gate104, a first gate insulating layer106a, an anti-fuse gate108, a second gate insulating layer106b, a first doped region110, a second doped region112and a third doped region114.

In the present embodiment, the substrate100may be a silicon substrate having a first conductive type. When the first conductive type is p-type, the second conductive type is n-type. Conversely, when the first conductive type is n-type, the second conductive type is p-type. The isolation structure102is disposed in the substrate100to define an active area (AA). As known to a person skilled in the art, the isolation structure102may be a shallow trench isolation (STI) structure or a field oxide (FOX) layer. The select gate104is disposed on the substrate100. The select gate104may be a polysilicon gate. The anti-fuse gate108is disposed on the substrate100and is partially overlapped with the isolation structure102. That is, in the present embodiment, a part of the anti-fuse gate108is located above the substrate100, and another part of the anti-fuse gate108is located above the isolation structure102. The anti-fuse gate108may be a polysilicon gate.

In the present embodiment, the dielectric layer106is continuously disposed on the substrate100and the isolation structure102. The dielectric layer106may be a silicon oxide layer or other dielectric layers with high dielectric constant, such as a HfO2layer, an Al2O3layer, and the like. The dielectric layer106located between the select gate104and the substrate100may be used as the gate insulating layer of the select gate104, that is, the first gate insulating layer106a. The dielectric layer106located between the anti-fuse gate108and the substrate100may be used as the gate insulating layer of the anti-fuse gate108, that is, the second gate insulating layer106b. That is, in the present embodiment, the first gate insulating layer106aand the second gate insulating layer106bare the same dielectric layer, but the present invention is not limited thereto. In other embodiments, the first gate insulating layer106aand the second gate insulating layer106bmay be different dielectric layers according to actual needs. For example, the first gate insulating layer106aand the second gate insulating layer106bmay be different in material, or the first gate insulating layer106aand the second gate insulating layer106bmay be different in thickness. In addition, in the present embodiment, spacers105are disposed on the sidewalls of the select gate104, and spacers109are disposed on the sidewalls of the anti-fuse gate108, but the present invention is not limited thereto.

The first doped region110and the second doped region112are respectively disposed in the substrate100at opposite sides of the select gate104. The first doped region110and the second doped region112have an opposite conductive type to that of the substrate100, that is, the first doped region110and the second doped region112have a second conductive type. The first doped region110is located between the select gate104and the anti-fuse gate108. In addition, in the present embodiment, the anti-fuse memory cell10further includes a contact113disposed on the second doped region112and connected to the second doped region112penetrating through the dielectric layer106. The contact113is used to electrically connect the anti-fuse memory cell10with a bit line (not shown) in the anti-fuse memory. Therefore, in the present embodiment, the first doped region110may be used as a source, and the second doped region112may be used as a drain.

The third doped region114is disposed in the substrate100between the first doped region110and the isolation structure102. The third doped region114is partially overlapped with the anti-fuse gate108. The third doped region114has an opposite conductive type to that of the substrate100, that is, the third doped region114has the second conductive type. In addition, in the present embodiment, the third doped region114is used as a lightly doped drain region. Therefore, the doping concentration of the third doped region114is less than the doping concentration of the first doped region110and less than the doping concentration of the second doped region112.

In addition, in the present embodiment, the anti-fuse memory cell10further includes a fourth doped region116and a fifth doped region118. The fourth doped region116is disposed in the substrate100below the select gate104and connected to the first doped region110. The fifth doped region118is disposed in the substrate100below the select gate104and connected to the second doped region112. The fourth doped region116and the fifth doped region118have an opposite conductive type to that of the substrate100, that is, the fourth doped region116and the fifth doped region118have the second conductive type. The region between the fourth doped region116and the fifth doped region118is the channel region of the select transistor including the select gate104. In addition, in the present embodiment, the fourth doped region116and the fifth doped region118are lightly doped drain regions. Therefore, the doping concentration of the fourth doped region116and the doping concentration of the fifth doped region118are less than the doping concentration of the first doped region110and less than the doping concentration of the second doped region112.

In addition, in the present embodiment, the third doped region114is in contact with the isolation structure102. That is, in the transistor including the anti-fuse gate108, there is no channel region, such as the region between the fourth doped region116and the fifth doped region118, or other regions such as the halo implant region or the pocket implant region well known to a person skilled in the art.

In the anti-fuse memory cell10of the present embodiment, since the third doped region114is in contact with the isolation structure102, there is no channel region or other regions between the third doped region114and the isolation structure102. In addition, the anti-fuse gate108and the second gate insulating layer106bconstitute an anti-fuse structure. In this way, during the programming operation of the anti-fuse memory cell10, a break down region (conductive path) is formed by causing the second gate insulating layer106bunder the anti-fuse gate108to break down (burn out at a high temperature), and thus the leakage current may be effectively avoided. In other words, in the present embodiment, current only flows from the anti-fuse gate108to the third doped region114through the break down region. In addition, since there is no channel region or other regions between the third doped region114and the isolation structure102, the increase of threshold voltage caused by the formation of parasitic diode at the channel region during the programming operation may be avoided, and the increase of threshold voltage caused by the halo implant region or the pocket implant region may also be avoided.

In addition, in order to further enhance the effects brought by the third doped region114, in the present embodiment, the overlapping width between the third doped region114and the anti-fuse gate108is greater than the overlapping width between the fourth doped region116and the select gate104, and greater than the overlapping width between the fifth doped region118and the select gate104, but the present invention is not limited thereto. In other embodiments, depending on actual needs, the overlapping width between the third doped region114and the anti-fuse gate108may be the same as the overlapping width between the fourth doped region116and the select gate104and the overlapping width between the fifth doped region118and the select gate104.

In addition, in the present embodiment, the select gate104and the anti-fuse gate108have the same width, but the present invention is not limited thereto. In other embodiments, the select gate104and the anti-fuse gate108may have different widths. For example, in an embodiment, the width of the anti-fuse gate108may preferably be greater than the width of the select gate104.

The programming operation and the reading operation of the anti-fuse memory cell10of the present embodiment are exemplarily described below, but the present invention is not limited thereto.

A voltage of about 7.0 V is applied to the anti-fuse gate108and a voltage of about 3.0 V is applied to the select gate104to perform a programming operation on the anti-fuse memory cell10. At this time, the second gate insulating layer106bbetween the anti-fuse gate108and the third doped region114is broken down (burned out at a high temperature) to form a conductive path with a resistance value of 0. After the programming operation, a reading operation may be performed on the anti-fuse memory cell10. As shown inFIGS.6A and6B, a voltage V1of about 2.5 V is applied to the anti-fuse gate108of the anti-fuse transistor600, and a voltage V2of about 1.4 V is applied to the select gate104of the select transistor602. In addition, the contact113may be connected to the external read circuit604through the bit line BL. The readout circuit604includes various devices that are well known and are not limited by the present invention. For example, in the present embodiment, the read circuit604may include a device for processing column select signals Y and YB; a device for pre-charging to half of the supply voltage VCC according to the pre-charge signal PCHB and the reference voltage VREF, wherein the reference current IREF is generated; a sense amplifier buffer SABUF for generating the data line signal DL; an output buffer OUTBUF for generating the data output signal DOUT. At this time, a voltage of about 1.4 V may be applied to the bit line BL (the contact113) via the external reading circuit604for pre-charging. Therefore, as shown inFIG.6A, when the anti-fuse memory cell10has been programmed, the current I flowing through the select gate104is greater than 0, the voltage at the bit line BL may be pulled up to about 0.8 V, and the data of “1” may be read. In addition, as shown inFIG.6B, when the anti-fuse memory cell10is not programmed, the current I flowing through the select gate104is 0, the voltage at the bit line BL may be pulled down to about 0 V, and the data of “0” may be read. In this way, the electrical signal of the anti-fuse memory cell10may be read.

FIG.2is a layout diagram of an anti-fuse memory of the second embodiment of the present invention. In the present embodiment, the same devices as those inFIGS.1A and1Bwill be denoted by the same reference numbers and will not be described again.

Referring toFIG.2, an anti-fuse memory20of the present embodiment includes two anti-fuse memory cells10and a bit line200. In detail, in the anti-fuse memory20, two anti-fuse memory cells10share one second doped region112and one contact113. The two anti-fuse memory cells10are arranged in a mirrored manner with respect to the contact113. In addition, the bit line200is disposed on the two anti-fuse memory cells10and connected with the contact113. In this way, a voltage may be simultaneously applied to the second doped regions112in the two anti-fuse memory cells10through the bit line200. In addition, in the present embodiment, the extending direction of the bit line200is the same as the connection direction of the two anti-fuse memory cells10, so the layout area of the anti-fuse memory20may be effectively reduced.

FIG.3is a layout diagram of an anti-fuse memory of the third embodiment of the present invention. In the present embodiment, the same devices as those inFIGS.1A,1B and2will be denoted by the same reference numbers and will not be described again.

Referring toFIG.3, an anti-fuse memory30of the present embodiment includes a first pair32-1of the anti-fuse memory cells10, a second pair32-2of the anti-fuse memory cells10and a bit line300. In detail, in the anti-fuse memory30, the first pair32-1of the anti-fuse memory cells10and the second pair32-2of the anti-fuse memory cells10each have a configuration as shown inFIG.2. That is, in the first pair32-1of the anti-fuse memory cells10, the two anti-fuse memory cells10share one second doped region112and one contact113, and the two anti-fuse memory cells10are arranged in a mirrored manner with respect to the contact113; in the second pair32-2of the anti-fuse memory cells10, the two anti-fuse memory cells10share one second doped region112and one contact113, and the two anti-fuse memory cells10are arranged in a mirrored manner with respect to the contact113. In addition, in the present embodiment, the first pair32-1of the anti-fuse memory cells10is not connected to the second pair32-2of the anti-fuse memory cells10.

In addition, the bit line300is disposed on the first pair32-1of the anti-fuse memory cells10of and the second pair32-2of the anti-fuse memory cells10, and is connected with both the contact113corresponding to the first pair32-1and the contact113corresponding to the second pair32-2. In the extending direction of the bit line300, one anti-fuse gate108in the first pair32-1is adjacent to one anti-fuse gate108in the second pair32-2. In this way, a voltage may be applied simultaneously to the second doped regions112in the first pair32-1of the anti-fuse memory cells10and the second pair32-2of the anti-fuse memory cells10through the bit line300. In addition, in the present embodiment, the extending direction of the bit line300is the same as the arrangement direction of the first pair32-1of the anti-fuse memory cells and the second pair32-2of the anti-fuse memory cells10, so the layout area of the anti-fuse fuse memory30may be effectively reduced.

In the present embodiment, the anti-fuse memory30includes two pairs of anti-fuse memory cells10, but the present invention is not limited thereto. In other embodiments, depending on the actual needs, the same method may be used to set the bit lines on more pairs of anti-fuse memory cells10, and connect the bit lines to the contacts corresponding to each pair at the same time.

FIG.4is a layout diagram of the anti-fuse memory of the fourth embodiment of the present invention. In the present embodiment, the same devices as those inFIGS.1A,1B and2will be denoted by the same reference numbers and will not be described again.

Referring toFIG.4, an anti-fuse memory40of the present embodiment includes a first pair42-1of the anti-fuse memory cells10, a second pair42-2of the anti-fuse memory cells10, a first bit line400-1and a second bit line400-2. In the anti-fuse memory40, the first pair42-1of the anti-fuse memory cells10and the second pair42-2of the anti-fuse memory cells10each have a configuration as shown inFIG.2. That is, in the first pair42-1of the anti-fuse memory cells10, the two anti-fuse memory cells10share one second doped region112and one contact113, and the two anti-fuse memory cells10are arranged in a mirrored manner with respect to the contact113; in the second pair42-2of the anti-fuse memory cells10, the two anti-fuse memory cells10share one second doped region112and one contact113, and the two anti-fuse memory cells10are arranged in a mirrored manner with respect to the contact113. In addition, the first pair of42-1of the anti-fuse memory cells10and the second pair of42-2of the anti-fuse memory cells10share one anti-fuse gate108, that is, the first pair of42-1of the anti-fuse memory cells10and the second pair of42-2of the anti-fuse memory cells10are connected with each other.

In addition, in the present embodiment, the first bit line400-1and the second bit line400-2are disposed on the first pair of42-1of the anti-fuse memory cells10and the second pair of42-2of the anti-fuse memory cells10. The first bit line400-1is connected with the contact113corresponding to the first pair42-1, and the second bit line400-2is connected with the contact113corresponding to the second pair42-2. That is, in the present embodiment, a voltage may be applied independently to the second doped region112in the first pair of42-1of the anti-fuse memory cells10through the first bit line400-1, and a voltage may be applied independently to the second pair of42-2of the anti-fuse memory cells10through the second bit line400-2to operate the two pairs of anti-fuse memory cells10independently.

In addition, in the present embodiment, from the top view, the first bit line400-1and the second bit line400-2are extended in parallel at opposite sides of the anti-fuse memory cells10respectively, so the first bit line400-1and the second bit line400-2may be arranged at the same level, that is, the first bit line400-1and the second bit line400-2may be disposed in the same layer, but the present invention is not limited thereto. In other embodiments, the first bit line400-1and the second bit line400-2may be disposed at different levels according to actual needs.

FIG.5is a layout diagram of the anti-fuse memory of the fifth embodiment of the present invention. In the present embodiment, the same devices as those inFIG.4will be denoted by the same reference numbers and will not be described again.

Referring toFIG.5, the difference between an anti-fuse memory50of the present embodiment and the anti-fuse memory40is that: in the anti-fuse memory50, the second bit line400-2is disposed at a higher level than the first bit line400-1, that is, the first bit line400-1and the second bit line400-2are disposed in different layers. In this way, the layout area of the anti-fuse memory may be effectively reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.