Patent ID: 12219830

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are illustrated in block diagram form in order to avoid unnecessarily obscuring various embodiments. Further, various embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concepts.

Unless otherwise specified, the illustrated embodiments are to be understood as providing features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements.

When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening element(s) or layer(s) may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z-axes, and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.

Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.

In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.” As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present disclosure described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the illustrative embodiments of the present disclosure.

Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

FIG.1is a plan view illustrating a display device according to an embodiment.FIG.2is a block diagram illustrating the display device ofFIG.1.FIG.3is a circuit diagram illustrating a pixel circuit and an organic light emitting diode included in the display device ofFIG.2.

Referring toFIGS.1,2, and3, a display device10according to an embodiment may be divided into a display area DA, a non-display area NDA, and a fingerprint recognition area FA. For example, the display area DA may have a rectangular shape having a short side extending in a first direction D1(i.e., latitudinal direction) and a long side extending in a second direction D2(i.e., longitudinal direction) crossing the first direction D1. The non-display area NDA may be positioned to be around (e.g., to surround) the display area DA, and the display area DA may be positioned to be around (e.g., to surround) the fingerprint recognition area FA. A display panel100may be disposed in the display area DA and the fingerprint recognition area FA to display an image. A data driver200, a gate driver300, an emission control driver400, and a timing controller500may be disposed in the non-display area NDA.

A first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and a fourth sub-pixel SPX4may be disposed in the display panel100. Each of the first to fourth sub-pixels SPX1, SPX2, SPX3, and SPX4may be electrically connected to a data line DL, a gate line GL, and an emission control line EML. In some embodiments, the first to fourth sub-pixels SPX1, SPX2, SPX3, and SPX4may constitute a first pixel PX1.

The data line DL may be electrically connected to the data driver200and may extend in the second direction D2. The data line DL may transmit a data voltage DATA.

The gate line GL may be connected to the gate driver300and may extend in the first direction D1. The gate line GL may transmit a gate signal GW, GC, GI, and GB.

The emission control line EML may be connected to the emission control driver400and may extend in the first direction D1. The emission control line EML may transmit an emission control signal EM. For example, an activation period of the emission control signal EM may be an emission period of the display device10, and an inactivation period of the emission control signal EM may be a non-emission period of the display device10.

The gate driver300may receive a gate control signal GCTRL from the timing controller500and may generate the gate signal. For example, the gate signal may include a first gate signal GW, a second gate signal GC, a third gate signal GI, and a fourth gate signal GB.

The data driver200may receive an output image data ODAT and a data control signal DCTRL from the timing controller500to generate the data voltage DATA. The emission control driver400may receive an emission drive control signal ECTRL from the timing controller500and may generate the emission control signal EM. The timing controller500may receive a control signal CTRL and an input image data DAT from an external device to control the data driver200, the gate driver300, and the emission control driver400.

For example, the data driver200and the timing controller500may be disposed on a flexible printed circuit board, the gate driver300may be mounted in the non-display area NDA adjacent to a left side of the display area DA, and the emission control driver400may be mounted in the non-display area NDA adjacent to a right side of the display area DA. However, a structure in which the data driver200, the gate driver300, the emission control driver400, and the timing controller500are disposed according to the present disclosure is not limited thereto.

The first sub-pixel SPX1may include a first pixel circuit PC1and a first organic light emitting diode OLED1. The first pixel circuit PC1may provide a driving current to the first organic light emitting diode OLED1, and the first organic light emitting diode OLED1may generate light based on the driving current. The second to fourth sub-pixels SPX2, SPX3, and SPX4may have substantially the same circuit structure as that of the first sub-pixel SPX1.

The first pixel circuit PC1may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST.

The first organic light emitting diode OLED1may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal), the first terminal of the first organic light emitting diode OLED1may be connected to the sixth transistor T6and the seventh transistor T7, and the second terminal may receive a common voltage ELVSS. The first organic light emitting diode OLED1may generate light having a luminance corresponding to the driving current.

The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may be connected to the first transistor T1, and the second terminal of the storage capacitor CST may receive a power voltage ELVDD. The storage capacitor CST may maintain a voltage level of a gate terminal of the first transistor T1during an inactive period of the first gate signal GW.

The first transistor T1may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the first transistor T1may be connected to the first terminal of the storage capacitor CST. The first terminal of the first transistor T1may be connected to the second transistor T2to receive the data voltage DATA. The second terminal of the first transistor T1may be connected to the sixth transistor T6. The first transistor T1may generate the driving current based on a voltage difference between the gate terminal and the first terminal. For example, the first transistor T1may be referred to as a driving transistor.

The second transistor T2may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the second transistor T2may receive the first gate signal GW through the gate line GL.

The second transistor T2may be turned on or off in response to the first gate signal GW. For example, when the second transistor T2is a P-channel metal-oxide-semiconductor (“PMOS”) transistor, the second transistor T2may be turned off when the first gate signal GW has a positive voltage level, and may be turned on when the first gate signal GW has a negative voltage level. The first terminal of the second transistor T2may receive the data voltage DATA through the data line DL. The second terminal of the second transistor T2may provide the data voltage DATA to the first terminal of the first transistor T1while the second transistor T2is turned on. For example, the second transistor T2may be referred to as a switching transistor.

The third transistor T3may include a gate terminal, a back gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal and the back gate terminal of the third transistor T3may receive the second gate signal GC. The first terminal of the third transistor T3may be connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3may be connected to the gate terminal of the first transistor T1.

The third transistor T3may be turned on or off in response to the second gate signal GC. For example, when the third transistor T3is an N-channel metal-oxide-semiconductor (“NMOS”) transistor, the third transistor T3may be turned on when the second gate signal GC has a positive voltage level, and may be turned off when the second gate signal GC has zero (ground) or a negative voltage level.

During a period in which the third transistor T3is turned on in response to the second gate signal GC, the third transistor T3may diode-connect the first transistor T1. The third transistor T3may compensate for a threshold voltage of the first transistor T1. For example, the third transistor T3may be referred to as a compensation transistor.

The fourth transistor T4may include a gate terminal, a back gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal and the back gate terminal of the fourth transistor T4may receive the third gate signal GI. The first terminal of the fourth transistor T4may be connected to the gate terminal of the first transistor T1. The second terminal of the fourth transistor T4may receive a gate initialization voltage VINT.

The fourth transistor T4may be turned on or off in response to the third gate signal GI. For example, when the fourth transistor T4is the NMOS transistor, the fourth transistor T4may be turned on when the third gate signal GI has a positive voltage level, and may be turned off when the third gate signal GI has zero or a negative voltage level,

While the fourth transistor T4is turned on in response to the third gate signal GI, the gate initialization voltage VINT may be provided to the gate terminal of the first transistor T1. Accordingly, the fourth transistor T4may initialize the gate terminal of the first transistor T1to the gate initialization voltage VINT. For example, the fourth transistor T4may be referred to as a gate initialization transistor.

The fifth transistor T5may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fifth transistor T5may receive the emission control signal EM. The first terminal of the fifth transistor T5may receive the power voltage ELVDD. The second terminal of the fifth transistor T5may be connected to the first terminal of the first transistor T1. When the fifth transistor T5is turned on in response to the emission control signal EM, the fifth transistor T5may provide the power voltage ELVDD to the first transistor T1.

The sixth transistor T6may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the sixth transistor T6may receive the emission control signal EM. The first terminal of the sixth transistor T6may be connected to the first transistor T1. The second terminal of the sixth transistor T6may be connected to the first organic light emitting diode OLED1. When the sixth transistor T6is turned on in response to the emission control signal EM, the sixth transistor T6may provide the driving current to the first organic light emitting diode OLED1.

The seventh transistor T7may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the seventh transistor T7may receive the fourth gate signal GB. The first terminal of the seventh transistor T7may be connected to the first terminal of the first organic light emitting diode OLED1. The second terminal of the seventh transistor T7may receive an anode initialization voltage AINT.

When the seventh transistor T7is turned on in response to the fourth gate signal GB, the seventh transistor T7may provide the anode initialization voltage AINT to the first organic light emitting diode OLED1. Accordingly, the seventh transistor T7may initialize the first terminal of the first organic light emitting diode OLED1to the anode initialization voltage AINT. For example, the seventh transistor T7may be referred to as an initialization transistor.

In some embodiments, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7may be the PMOS transistors, and the third and fourth transistors T3and T4may be the NMOS transistors. Accordingly, active patterns of the PMOS transistors may include a silicon thin film doped with cations, and active patterns of the NMOS transistors may include an oxide semiconductor. In addition, the first gate signal GW, the emission control signal EM, and the fourth gate signal GB for turning on the second, fifth, sixth, and seventh transistors T2, T5, T6, and T7may have negative voltage levels. The second gate signal GC and the third gate signal GI for turning on the third and fourth transistors T3and T4may have positive voltage levels.

A connection structure of the first pixel circuit PC1shown inFIG.3is illustrative and may be variously changed.

FIG.4is a cross-sectional view of an embodiment taken along line I-I′ ofFIG.1.FIG.5is a cross-sectional view illustrating an embodiment of a display panel included in the display device ofFIG.1.FIG.6is a perspective view illustrating an embodiment of a display panel included in the display device ofFIG.4.

Referring toFIGS.1and4, the display device10may include the display panel100, an optical sensor module LSM, and various functional layers disposed above or below the display panel100. For example, the functional layers may include a cushion layer CSL, a protective film PFL, an air layer ARL, a polarizing plate POL, and a window WIN. In addition, an adhesive layer may be disposed between the functional layers CSL, PFL, ARL, POL, and WIN, and the adhesive layer may be an optically clear adhesive (“OCA”).

The display panel100may overlap the display area DA and the fingerprint recognition area FA in a plan view. As described above, the display panel100may include the first to fourth sub-pixels SPX1, SPX2, SPX3, and SPX4. For example, the first to fourth sub-pixels SPX1, SPX2, SPX3, and SPX4may overlap the fingerprint recognition area FA.

The protective film PFL may be disposed under the display panel100. The protective film PFL may overlap the display area DA and may not overlap the fingerprint recognition area FA in a plan view. In other words, an opening overlapping the fingerprint recognition area FA in a plan view may be defined by the protective film PFL. The protective film PFL may include a plastic material and may support the display panel100.

The air layer ARL may be disposed under the display panel100. The air layer ARL may be filled with air. The air layer ARL may overlap the fingerprint recognition area FA and may not overlap the display area DA in a plan view. For example, the air layer ARL may be defined by the opening. Light may be smoothly transmitted to the optical sensor module LSM through the air layer ARL.

The cushion layer CSL may be disposed under the protective film PFL. The cushion layer CSL may overlap the display area DA and may not overlap the fingerprint recognition area FA in a plan view. In other words, an opening overlapping the fingerprint recognition area FA may be defined by the cushion layer CSL. The cushion layer CSL may include an elastic body and may protect the display panel100from external impact.

The optical sensor module LSM may be disposed under the protective film PFL. The optical sensor module LSM may overlap the fingerprint recognition area FA in a plan view. In other words, the optical sensor module LSM may be disposed in the opening defined by the cushion layer CSL. The optical sensor module LSM may recognize a user's fingerprint. For example, light emitted from the display panel100may be reflected by the user's finger on the window WIN, and the optical sensor module LSM may detect the light reflected from the finger. In order for the optical sensor module LSM to detect light, the optical sensor module LSM may be exposed by the air layer ARL.

The polarization layer POL may be disposed on the display panel100. The polarizing layer POL may reduce reflection of external light.

The window WIN may be disposed on the polarizing layer POL. The window WIN may be made of glass, plastic, or the like, and may protect the display panel100from external impact.

As the air layer ARL is defined under the display panel100, light reflected from the fingerprint recognition area FA may be incident on the display panel100. For example, a light11incident from the outside and reflected from the optical sensor module LSM and/or a light12emitted from the display panel100and reflected from the optical sensor module LSM may be incident to the display panel100.

Referring toFIGS.5and6, the display panel100may include first to fourth pixel circuit parts PCP1, PCP2, PCP3, and PCP4, and first to fourth emitting diodes ED1, ED2, ED3, and ED4.

In some embodiments, the first pixel circuit part PCP1and the first emitting diode ED1may constitute the first sub-pixel SPX1. For example, the first pixel circuit part PCP1may correspond to the first pixel circuit PC1, and the first emitting diode ED1may correspond to the first organic light emitting diode OLED1. In other words, the transistors may be formed in the first pixel circuit part PCP1, and the driving current may be provided to the first emitting diode ED1.

In addition, the second pixel circuit part PCP2and the second emitting diode ED2may constitute the second sub-pixel SPX2, the third pixel circuit part PCP3and the third emitting diode ED3may constitute the third sub-pixel SPX3, and the fourth pixel circuit part PCP4and the fourth emitting diode ED4may constitute the fourth sub-pixel SPX4. Accordingly, the first to fourth pixel circuit parts PCP1, PCP2, PCP3and PCP4and the first to fourth emitting diodes ED1, ED2, ED3, and ED4may constitute the first pixel PX1.

The first emitting diode ED1may include a first pixel electrode ADE1, a first emission layer EL1, and a common electrode CTE. For example, the first emission layer EL1may generate red light. The second emitting diode ED2may include a second pixel electrode ADE2, a second emission layer EL2, and the common electrode CTE. For example, the second emission layer EL2may generate green light. The third emitting diode ED3may include a third pixel electrode ADE3, a third emission layer EL3, and the common electrode CTE. For example, the third emission layer EL3may generate blue light. The fourth emitting diode ED4may include a fourth pixel electrode ADE4, a fourth emission layer EL4, and the common electrode CTE. For example, the fourth emission layer EL4may generate green light.

The first pixel circuit part PCP1may include a first organic film layer PI1, a first barrier layer BRR1, a second organic film layer PI2, a second barrier layer BRR2, a lower pattern SDP, a third barrier layer BRR3, a first active pattern1100, a first conductive pattern1200, a second conductive pattern1300, a second active pattern1400, a third conductive pattern1500, a fourth conductive pattern1600, and a fifth conductive pattern1700. For example, each of the first and second organic film layers PI1and PI2may be referred to as a substrate of the display panel100. Insulation layers may be disposed between the first active pattern1100to the fifth conductive pattern1700. In addition, a second via insulating layer VIA2may be disposed on the fifth conductive pattern1700, and the first to fourth pixel electrodes ADE1, ADE2, ADE3, and ADE4may be respectively connected to the fifth conductive pattern1700through contact holes passing through the second via insulating layer VIA2.

A related art display device includes a display panel and transistors including active patterns that are disposed in the display panel. An electric field may be generated inside the display panel due to signals and voltages provided to the display panel. Organic materials included in an organic film layer of the display panel may be polarized by the electric field. The polarized organic materials may have an electrical effect on the active patterns of the display panel. Accordingly, electrical characteristics of the transistors may be changed. In addition, a polarization phenomenon may be further accelerated by light incident on the display panel. Therefore, a display quality of the related art display device may be deteriorated.

However, the display device10may include the lower pattern SDP disposed inside the display panel100. The lower pattern SDP may prevent or protect the polarization from having an electrical effect on the first and second active patterns1100and1400. Accordingly, electrical characteristics of the transistors may not be changed. Accordingly, display quality of the display device10may be improved, and will be described in more detail below.

FIG.7toFIG.18are layout diagrams illustrating an embodiment of the display device ofFIG.1.FIG.19is a cross-sectional view illustrating an example taken along line II-II′ ofFIG.18.FIG.20is a cross-sectional view illustrating an example taken along line III-III′ ofFIG.18.

Referring toFIG.7, the display device10may include a plurality of pixel circuit parts arranged in a matrix shape. For example, the display device10may include the first to fourth pixel circuit parts PCP1, PCP2, PCP3, and PCP4arranged with each other in the first direction D1. In some embodiments, the second pixel circuit part PCP2may have a shape symmetrical with a shape of the first pixel circuit part PCP1. In addition, the third pixel circuit part PCP3may have the same shape as the first pixel circuit part PCP1, and the fourth pixel circuit part PCP4may have a shape symmetrical with the shape of the third pixel circuit part PCP3.

Referring toFIGS.8,9,10,11, and19, the first pixel circuit part PCP1may include the first organic film layer PI1, the first barrier layer BRR1, the second organic film layer PI2, the second barrier layer BRR2, the lower pattern SDP, and the third barrier layer BRR3, as shown inFIG.5.

The first organic film layer PI1may include an organic material. For example, the first organic film layer PI1may include polyimide.

The first barrier layer BRR1may be disposed on the first organic film layer PI1. The first barrier layer BRR1may include an inorganic material. For example, the first barrier layer BRR1may include silicon oxide, silicon nitride, amorphous silicon, and/or one or more other suitable materials.

The second organic film layer PI2may be disposed on the first barrier layer BRR1. For example, the second organic film layer PI2may include the same material as the first organic film layer PI1.

The second barrier layer BRR2may be disposed on the second organic film layer PI2. The second barrier layer BRR2may include the same material as the first barrier layer BRR1. The second barrier layer BRR2may protect the second organic film layer PI2, which may be damaged in the process of forming the lower pattern SDP.

In some embodiments, the lower pattern SDP may be disposed between the second organic film layer PI2and the first active pattern1100. For example, the lower pattern SDP may be disposed on the second barrier layer BRR2.

In some embodiments, the lower pattern SDP may include metal. For example, the lower pattern SDP may include the same metal as the first conductive pattern1200(e.g., the lower pattern and the gate electrode are composed of the same metal or are the same in metal.

In other embodiments, the lower pattern SDP may include a silicon semiconductor. For example, the lower pattern SDP may include amorphous silicon and/or polycrystalline silicon. In addition, the lower pattern SDP may be doped with positive (cation) and/or negative (anion) ions. For example, the cation may be a group III element (e.g., boron and/or the like). The anion may be a group V element (e.g., phosphorus and/or the like).

In some embodiments, the lower pattern SDP may be electrically floating. In another embodiment, a constant voltage may be provided to the lower pattern SDP. In another embodiment, an AC voltage may be provided to the lower pattern SDP.

In some embodiments, for example, as shown inFIG.10, the lower pattern SDP may have a mesh shape defining a disconnection area DCA.

In some embodiments, the lower pattern SDP may include a first pattern PTN1and a second pattern PTN2. The first pattern PTN1may extend in the second direction D2. The second pattern PTN2may extend in the second direction D2and may be spaced apart from the first pattern PTN1in the first direction D1. For example, a shape of the first pattern PTN1and a shape of the second pattern PTN2may be the same.

In some embodiments, the first pattern PTN1and the second pattern PTN2may not be connected to each other. In other words, the first pattern PTN1and the second pattern PTN2may be disconnected from each other. For example, the disconnection area DCA may be positioned between the first pattern PTN1and the second pattern PTN2.

In more detail, the disconnection area DCA may be an area in which the first pattern PTN1and the second pattern PTN2are disconnected from each other. In other words, the lower pattern SDP may be partially removed from the disconnection area DCA. Accordingly, the second barrier layer BRR2may contact the third barrier layer BRR3in the disconnection area DCA.

In some embodiments, the first pattern PTN1may include a first auxiliary pattern PTN11, a second auxiliary pattern PTN12, a third auxiliary pattern PTN13, and a fourth auxiliary pattern PTN14.

The first auxiliary pattern PTN11may include a first portion PRT1overlapping a first gate electrode (e.g., a first gate electrode1221shown inFIG.13) and a second portion PRT2extending in the second direction D2.

A second shape of the second auxiliary pattern PTN12may be symmetrical with a first shape of the first auxiliary pattern PTN11in the first direction D1. The first auxiliary pattern PTN11and the second auxiliary pattern PTN12may be connected to each other through a first bridge BRD1extending in the first direction D1.

A third shape of the third auxiliary pattern PTN13may be the same as the first shape. The second auxiliary pattern PTN12and the third auxiliary pattern PTN13may be connected to each other through a second bridge BRD2extending in the first direction D1.

A fourth shape of the fourth auxiliary pattern PTN14may be the same as the second shape and may be symmetrical with the third shape in the first direction D1. The third auxiliary pattern PTN13and the fourth auxiliary pattern PTN14may be connected to each other through the first bridge BRD1. In other words, the first to fourth auxiliary patterns PTN11, PTN12, PTN13, and PTN14may be connected to each other through the first and second bridges BRD1and BRD2.

The first portion PRT1of the first auxiliary pattern PTN11may completely overlap the first gate electrode1221(e.g., in a plan view). For example, a shape of the first portion PRT1may be substantially the same as a shape of the first gate electrode1221, and a size of the first portion PRT1may be greater than or equal to a size of the first gate electrode1221.

The second portion PRT2of the first auxiliary pattern PTN11may overlap a power voltage line (e.g., a power voltage line1720ofFIG.18) to be described later in more detail. For example, the second portion PRT2may be disposed along the power voltage line1720.

The first portion PRT1of the second auxiliary pattern PTN12may completely overlap a second gate electrode (e.g., a second gate electrode1222shown inFIG.13). For example, a shape of the first portion PRT1may be substantially the same as a shape of the second gate electrode1222, and a size of the first portion PRT1may be greater than or equal to a size of the second gate electrode1222.

The second portion PRT2of the second auxiliary pattern PTN12may overlap the power voltage line. For example, the second portion PRT2may be disposed along the power voltage line1720.

The third barrier layer BRR3may cover the lower pattern SDP and may be disposed on the second barrier layer BRR2. The third barrier layer BRR3may include the same material as the first barrier layer BRR1. In addition, as described above, the third barrier layer BRR3may contact the second barrier layer BRR2in the disconnection area DCA.

A buffer layer BFR may be disposed on the third barrier layer BRR3, as shown inFIG.12. The buffer layer BFR may prevent or reduce diffusion of metal atoms and/or impurities into the first active pattern1100. In addition, the buffer layer BFR may help the first active pattern1100to be uniformly formed by controlling a heat supply rate during a crystallization process for forming the first active pattern1100.

Referring toFIGS.12and19, the first active pattern1100may be disposed on the buffer layer BFR. The first active pattern1100may overlap the lower pattern SDP. In some embodiments, the first active pattern1100may include a silicon semiconductor. For example, the first active pattern1100may include amorphous silicon, polycrystalline silicon, and/or one or more other suitable materials.

In some embodiments, cations and/or anions may be selectively doped to the first active pattern1100. For example, when the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7are the PMOS transistors, the first active pattern1100may include a source region having a high cation concentration, a drain region having a high cation concentration, and a channel region having a low cation concentration.

A first gate insulating layer GI1may cover the first active pattern1100and may be disposed on the buffer layer BFR. The first gate insulating layer GI1may include an insulating material. For example, the first gate insulating layer GI1may include silicon oxide, silicon nitride, titanium oxide, tantalum oxide, and/or one or more other suitable materials.

Referring toFIGS.13and19, a first conductive pattern1200may be disposed on the first gate insulating layer GI1. The first conductive pattern1200may include a first gate line1210, a first gate electrode1221, a second gate electrode1222, and a third gate line1230.

The first gate line1210may be disposed on the first active pattern1100and may extend in the first direction D1. In some embodiments, the first gate line1210may be adjacent to a first side of the first gate electrode1221on a plane (e.g., in a plan view). The first gate line1210may constitute the fifth and sixth transistors T5and T6together with the first active pattern1100. The emission control signal EM may be provided to the first gate line1210. For example, the first gate line1210may be referred to as an emission control line.

The first gate electrode1221and the second gate electrode1222may be arranged in the first direction D1. In addition, as shown inFIG.6, the first to fourth pixel circuit parts PCP1, PCP2, PCP3, and PCP4may be arranged in the first direction D1. Accordingly, the first gate electrode1221, the second gate electrode1222, the third gate electrode included in the third pixel circuit part PCP3, and the fourth gate electrode included in the fourth circuit part PCP4may be arranged in the first direction D1.

The first gate electrode1221may overlap the first portion PRT1of the first pattern PTN1and the first active pattern1100. The first gate electrode1221may constitute the first transistor T1of the first sub-pixel SPX1together with the first active pattern1100.

The second gate electrode1222may be spaced apart from the first gate electrode1221in the first direction D1. The second gate electrode1222may overlap the second pattern PTN2and the first active pattern1100. The second gate electrode1222may form the first transistor T1of the second sub-pixel SPX2together with the first active pattern1100.

The third gate line1230may be disposed on the first active pattern1100and may extend in the first direction D1. For example, the third gate line1230may form the second transistor T2together with the first active pattern1100. The first gate signal GW may be provided to the third gate line1230.

In addition, the third gate line1230may constitute the seventh transistor T7together with the first active pattern1100. The fourth gate signal GB may be provided to the third gate line1230. For example, the first gate signal GW and the fourth gate signal GB may have substantially the same waveform with a time difference.

In some embodiments, the first conductive pattern1200may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and/or one or more other suitable materials. For example, the first conductive pattern1200may include silver (“Ag”), an alloy containing silver, molybdenum (“Mo”), an alloy containing molybdenum, aluminum (“Al”), an alloy containing aluminum, aluminum nitride (“AlN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), and/or the like.

A second gate insulating layer GI2may cover the first conductive pattern1200and may be disposed on the first gate insulating layer GI1. The second gate insulating layer Gi2may include an insulating material.

The first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7may be substantially the same as the first, second, fifth, sixth and seventh transistors T1, T2, T5, T6, and T7described with reference toFIG.3. For example, the gate electrode1221may correspond to the gate terminal of the first transistor T1described with reference toFIG.3. However, this correspondence relationship will not be described in detail, and may be apparent to those skilled in the art to which the present disclosure pertains.

Referring toFIGS.14and19, a second conductive pattern1300may be disposed on the second gate insulating layer GI2. The second conductive pattern1300may include a storage capacitor electrode1310, a fourth gate line1320, a fifth gate line1330, and a gate initialization voltage line1340.

The storage capacitor electrode1310may extend in the first direction D1. In some embodiments, the storage capacitor electrode1310may constitute the storage capacitor CST included in the first pixel circuit part PCP1together with the first gate electrode1221. For example, the storage capacitor electrode1310may overlap the first gate electrode1221, and the power voltage ELVDD may be provided to the storage capacitor electrode1310. In addition, the storage capacitor electrode1310may form the storage capacitor CST included in the second pixel circuit part PCP2together with the second gate electrode1222. For example, the storage capacitor electrode1310may overlap the second gate electrode1222.

In some embodiments, openings exposing top surfaces of the first and second gate electrodes1221and1222may be formed in the storage capacitor electrode1310.

The fourth gate line1320may extend in the first direction D1. In some embodiments, the fourth gate line1320may be adjacent to a second side opposite to the first side of the first gate electrode1221on a plane. In some embodiments, the fourth gate line1320may provide the second gate signal GC to the third transistor T3. For example, the fourth gate line1320may correspond to the back gate terminal of the third transistor T3. The fourth gate line1320may be referred to as a lower compensation control line.

The fifth gate line1330may extend in the first direction D1. In some embodiments, the fifth gate line1330may provide the third gate signal GI to the fourth transistor T4. For example, the fifth gate line1330may correspond to the back gate terminal of the fourth transistor T4.

The gate initialization voltage line1340may extend in the first direction D1. In some embodiments, the gate initialization voltage line1340may provide the gate initialization voltage VINT to the fourth transistor T4. For example, the gate initialization voltage line1340may be electrically connected to the second active pattern1400.

For example, the second conductive pattern1300may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and/or one or more other suitable materials.

A first interlayer insulating layer ILD1may cover the second conductive pattern1300and may be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1may include an insulating material.

Referring toFIGS.15and19, the second active pattern1400may be disposed on the first interlayer insulating layer ILD1. For example, the second active pattern1400may overlap the fourth gate line1320, the fifth gate line1330, and the gate initialization line1340.

In some embodiments, the second active pattern1400may be disposed on a different layer from the first active pattern1100and may not overlap the first active pattern1100. In other words, the second active pattern1400may be formed separately from the first active pattern1100. For example, the first active pattern1100may include the silicon semiconductor, and the second active pattern1400may include an oxide semiconductor.

In some embodiments, the first pixel circuit part PCP1may include the first, second, fifth, sixth and seventh transistors T1, T2, T5, T6, and T7which are silicon-based semiconductor transistors, and the third and fourth transistors T3and T4which are oxide-based semiconductor transistors. For example, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7are the PMOS transistors and the third and fourth transistors T3and T4may be the NMOS transistors.

A third gate insulating layer GI3may cover the second active pattern1400and may be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3may include an insulating material.

Referring toFIGS.16and19, a third conductive pattern1500may be disposed on the third gate insulating layer GI3. The third conductive pattern1500may include a second gate line1510and a sixth gate line1520.

The second gate line1510may extend in the first direction D1. In some embodiments, the second gate line1510may overlap the third gate line1320in a plan view and may be electrically connected to the third gate line1320. In some embodiments, the second gate line1510may provide the second gate signal GC to the third transistor T3. For example, the second gate line1510may correspond to the gate terminal of the third transistor T3. For example, the second gate line1510may be referred to as an upper compensation control line.

The sixth gate line1520may extend in the first direction D1. In some embodiments, the sixth gate line1520may overlap the fifth gate line1330in a plan view and may be electrically connected to the fifth gate line1330. In some embodiments, the sixth gate line1520may provide the third gate signal GI to the fourth transistor T4. For example, the sixth gate line1520may correspond to the gate terminal of the fourth transistor T4.

A second interlayer insulating layer ILD2may cover the third conductive pattern1500and may be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2may include an insulating material.

A fourth conductive pattern1600may include a first power voltage pattern1611, a second power voltage pattern1612, a first anode pattern1621, a second anode pattern1622, a first compensation connection pattern1631, a second compensation connection pattern1632, a first initialization connection pattern1641, a second initialization connection pattern1642, an anode initialization voltage line1650, a first data pattern1661, a second data pattern1662, and a gate initialization voltage pattern1670.

The first and second power voltage patterns1611and1612may transmit the power voltage ELVDD to the first active pattern1100. In some embodiments, the first and second power voltage patterns1611and1612may electrically connect a power voltage line (e.g., the power voltage line1720ofFIG.18) and the first active pattern1100. For example, the first and second power voltage patterns1611and1612may contact the power voltage line1720and the first active pattern1100.

The first anode pattern1621may provide the anode initialization voltage AINT or the driving current to the first emitting diode ED1connected to the first pixel circuit part PCP1. For example, the first anode pattern1621may contact the first active pattern1100and a third anode pattern (e.g., a third anode pattern1731ofFIG.18).

The second anode pattern1622may provide the anode initialization voltage AINT or the driving current to the second emitting diode ED2connected to the second pixel circuit part PCP2. For example, the second anode pattern1622may contact the first active pattern1100and a fourth anode pattern (e.g., a fourth anode pattern1732ofFIG.18).

The first compensation connection pattern1631may electrically connect the second terminal of the first transistor T1included in the first pixel circuit part PCP1and the second terminal of the third transistor T3included in the first pixel circuit part PCP1. For example, the first compensation connection pattern1631may contact the first active pattern1100and the second active pattern1400.

The second compensation connection pattern1632may electrically connect the second terminal of the first transistor T1included in the second pixel circuit part PCP2and the second terminal of the third transistor T3included in the second pixel circuit part PCP2. For example, the second compensation connection pattern1632may contact the first active pattern1100and the second active pattern1400.

The first initialization connection pattern1641may electrically connect the gate terminal of the first transistor T1included in the first pixel circuit part PCP1and the second terminal of the fourth transistor T4included in the first pixel circuit part PCP1. For example, the first initialization connection pattern1641may contact the second active pattern1400and the first gate electrode1221.

The second initialization connection pattern1642may electrically connect the gate terminal of the first transistor T1included in the second pixel circuit part PCP2and the second terminal of the fourth transistor T4included in the second pixel circuit part PCP2. For example, the second initialization connection pattern1642may contact the second active pattern1400and the second gate electrode1222.

The anode initialization voltage line1650may provide the anode initialization voltage AINT to the seventh transistor T7. For example, the anode initialization voltage line1650may contact the first active pattern1100.

The first data pattern1661may provide the data voltage DATA to the second transistor T2included in the first pixel circuit part PCP1. For example, the first data pattern1661may contact the first active pattern1100and a first data line (e.g., a first data line1711ofFIG.18).

The second data pattern1662may provide the data voltage DATA to the second transistor T2included in the second pixel circuit part PCP2. For example, the second data pattern1662may contact the first active pattern1100and a second data line (e.g., a second data line1712ofFIG.18).

The gate initialization voltage pattern1670may provide the gate initialization voltage VINT to the fourth transistor T4. For example, the gate initialization voltage pattern1670may provide the gate initialization voltage VINT to the second active pattern1400. The gate initialization voltage pattern1670may contact the gate initialization voltage line1340and the second active pattern1400.

A first via insulating layer VIA1may cover the fourth conductive pattern1600and may be disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1may include an organic insulating material. For example, the first via insulating layer VIA1may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, and/or the one or more other suitable materials.

Referring toFIGS.18and19, a fifth conductive pattern1700may be disposed on the first via insulating layer VIA1. The fifth conductive pattern1700may include the first data line1711, the second data line1712, the power voltage line1720, the third anode pattern1731, and the fourth anode pattern1732.

The first data line1711may extend in the second direction D2. In some embodiments, the first data line1711may provide the data voltage DATA to the second transistor T2included in the first pixel circuit part PCP1. For example, the first data line1711may contact the first data pattern1661.

The second data line1712may extend in the second direction D2. In some embodiments, the second data line1712may provide the data voltage DATA to the second transistor T2included in the second pixel circuit part PCP2. For example, the second data line1712may contact the second data pattern1662.

The power voltage line1720may extend in the second direction D2. In some embodiments, the power voltage line1720may provide the power voltage ELVDD to the first and second power voltage patterns1611and1612. For example, the power voltage line1720may contact the first and second power voltage patterns1611and1612.

The third anode pattern1731may provide the anode initialization voltage AINT or the driving current to the first emitting diode ED1connected to the first pixel circuit part PCP1. For example, the third anode pattern1731may contact the first anode pattern1621.

The fourth anode pattern1732may provide the anode initialization voltage AINT or the driving current to the second emitting diode ED2connected to the second pixel circuit part PCP2. For example, the fourth anode pattern1732may contact the second anode pattern1622.

A second via insulating layer VIA2may cover the fifth conductive pattern1700and may be disposed on the first via insulating layer VIA1. The second via insulating layer VIA2may include an organic insulating material. For example, the second via insulating layer VIA2may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, and/or one or more other suitable materials.

As shown inFIG.19, the lower pattern SDP may overlap the first active pattern1100, the first gate electrode1221, and the power voltage line1720(e.g., in a thickness direction or in a plan view). In a plan view, the first gate line1210may be adjacent (e.g., closer) to the first side (e.g., the left side) of the first gate electrode1221, and the fourth gate line1320and the second gate line1510may be adjacent to the second side (e.g., the right side) of the first gate electrode1221.

As described above, the emission control signal EM may be provided to the first gate line1210, and the second gate signal GC may be provided to the fourth gate line1320and the second gate line1510. In order to turn on the fifth and sixth transistors T5and T6, the emission control signal EM may have a negative voltage level. At the same time, in order to turn off the third transistor T3, the second gate signal GC may have a negative voltage level.

In a related art display device, when the emission control signal EM and the second gate signal GC have the same negative voltage level at the same time, an electric field may be formed in the second organic film layer PI2. Accordingly, organic materials in the second organic film layer PI2may be polarized. A back channel may be formed in the first active pattern1100by the polarized organic materials. Accordingly, electrical characteristics (e.g., threshold voltage, electron mobility, etc.) of the first transistor T1may be changed. Accordingly, the pixel including the first transistor T1whose electrical characteristics have been changed may emit luminance not corresponding to the data voltage DATA, and display quality of the display device may be deteriorated.

However, the display device10may include the lower pattern SDP disposed between the second organic film layer PI2and the first active pattern1100. The lower pattern SDP may shield the first active pattern1100from the polarized organic materials. Accordingly, the back channel may not be formed in the first active pattern1100and electrical characteristics of the first transistor T1may not be changed. Accordingly, display quality of the display device10may be improved.

The lower pattern SDP may have a mesh shape. For example, the lower pattern SDP may be connected to each other, and may be repeatedly arranged in a certain unit. As the lower pattern SDP has the mesh shape, the lower pattern SDP can effectively suppress the polarization of the organic materials.

In addition, as shown inFIGS.8,18, and20, the lower pattern SDP may have a mesh shape defining the disconnection area DCA. The lower pattern SDP may not be formed in the disconnection area DCA. Accordingly, the lower pattern SDP may include the first pattern PTN1and the second pattern PTN2that are not connected to each other. In other words, the second barrier layer BRR2and the third barrier layer BRR3may contact each other in the disconnection area DCA.

As the lower pattern SDP is removed from the disconnection area DCA, a unit area of the lower pattern SDP may be reduced. Accordingly, resistance of the lower pattern SDP may be increased, and a crosstalk between the lower pattern SDP and the first data line1711(or the second data line1712) may be improved (e.g., reduced). In other words, even if the data voltage DATA transmitted to the first data line1711is fluctuated, the potential of the lower pattern SDP may fluctuate relatively little. Accordingly, a crosstalk between the lower pattern SDP and the first gate electrode1221(or the second gate electrode1222) may be improved (e.g., reduced). In other words, since the potential of the lower pattern SDP fluctuates relatively little, an electrical influence of the potential of the lower pattern SDP on the first gate electrode1221may be reduced.

Meanwhile, the polarization of the organic materials may be further accelerated by the light incident on the display panel100described with reference toFIG.4(e.g.,11or12ofFIG.4). Accordingly, in some embodiments, the lower pattern SDP may overlap with the fingerprint recognition area FA and may not overlap with the display area DA. In other words, the lower pattern SDP may be formed in the display panel100overlapping the fingerprint recognition area FA, and may not be formed in the display panel100overlapping the display area DA.

FIG.21toFIG.25are layout diagrams illustrating a display device according to another embodiment. For example,FIGS.21and22are layout diagrams illustrating a lower pattern,FIG.23is a layout diagram illustrating the lower pattern and a first active pattern,FIG.24is a layout diagram illustrating the lower pattern, the first active pattern, and a first conductive pattern, andFIG.25is a layout diagram illustrating the lower pattern, the first active pattern, the first conductive pattern, and a fifth conductive pattern.

Referring toFIGS.21to25, a display device20according to another embodiment may include a first pixel circuit part PCP1and a second pixel circuit part PCP2adjacent to the first pixel circuit part PCP1. In some embodiments, the second pixel circuit part PCP2may have a shape symmetrical with a shape of the first pixel circuit part PCP1.

However, the display device20may be substantially the same as the display device10except for the shape of the lower pattern SDP. For example, the display device20may include the first organic film layer PI1, the first barrier layer BRR1, the second organic film layer PI2, the second barrier layer BRR2, the third barrier layer BRR3, the buffer layer BFR, the first active pattern1100, the first gate insulating layer GI1, the first conductive pattern1200, the second gate insulating layer GI2, the second conductive pattern1300, the first interlayer insulating layer ILD1, the second active pattern1400, the third gate insulating layer GI3, the third conductive pattern1500, the second interlayer insulating layer ILD2, the fourth conductive pattern1600, the first via insulating layer VIA1, the fifth conductive pattern1700, and the second via insulating layer VIA2. Hereinafter, the shape of the lower pattern SDP will be mainly described.

As shown inFIGS.21and22, the lower pattern SDP included in the display device20may be disposed on the second barrier layer BRR2. In some embodiments, the lower pattern SDP may have a mesh shape defining a disconnection area DCA.

In some embodiments, the lower pattern SDP may include a first pattern PTN1and a second pattern PTN2. The first pattern PTN1may extend in the second direction D2. The second pattern PTN2may extend in the second direction D2and may be spaced apart from the first pattern PTN1in the first direction D1. For example, a second shape of the second pattern PTN2may be symmetrical with a first shape of the first pattern PTN1in the first direction D1.

In some embodiments, the first pattern PTN1and the second pattern PTN2may not be connected to each other. In other words, the first pattern PTN1and the second pattern PTN2may be disconnected from each other. For example, the disconnection area DCA may be positioned between the first pattern PTN1and the second pattern PTN2.

In more detail, the disconnection area DCA may be an area in which the first pattern PTN1and the second pattern PTN2are disconnected from each other. In other words, the lower pattern SDP may be partially removed from the disconnection area DCA. Accordingly, the second barrier layer BRR2may contact the third barrier layer BRR3in the disconnection area DCA.

The first pattern PTN1may include a first portion PRT1overlapping the first gate electrode1221and a second portion PRT2extending in the second direction D2. The second pattern PTN2may include a first portion PRT1overlapping the second gate electrode1222and a second portion PRT2extending in the second direction D2. The second shape of the second pattern PTN2may be symmetrical with the first shape of the first pattern PTN1in the first direction D1.

As shown inFIGS.21and24, the first portion PRT1of the first pattern PTN1may completely overlap the first gate electrode1221. For example, a shape of the first portion PRT1of the first pattern PTN1may be substantially the same as a shape of the first gate electrode1221, and a size of the first portion PRT1of the first pattern PTN1may be greater than or equal to a size of the first gate electrode1221.

As shown inFIGS.21and25, the second portion PRT2of the first pattern PTN1may overlap the power voltage line1720. For example, the second portion PRT2of the first pattern PTN1may be disposed along the power voltage line1720.

As shown inFIGS.21and24, the first portion PRT1of the second pattern PTN2may completely overlap the second gate electrode1222. For example, a shape of the first portion PRT1of the second pattern PTN2may be substantially the same as a shape of the second gate electrode1222, and a size of the first portion PRT1of the second pattern PTN2may be greater than or equal to a size of the second gate electrode1222.

As shown inFIGS.21and25, the second portion PRT2of the second pattern PTN2may overlap the power voltage line1720. For example, the second portion PRT2of the second pattern PTN2may be disposed along the power voltage line1720.

The first pattern PTN1and the second pattern PTN2may be disconnected from each other. In other words, the lower pattern SDP may not include the first and second bridges BRD1and BRD2described with reference toFIG.9. Accordingly, the unit area of the lower pattern SDP may be reduced.

FIG.26toFIG.30are layout diagrams illustrating a display device according to still another embodiment. For example,FIGS.26and27are layout diagrams illustrating a lower pattern,FIG.28is a layout diagram illustrating the lower pattern and a first active pattern,FIG.29is a layout diagram illustrating the lower pattern, the first active pattern, and a first conductive pattern, andFIG.30is a layout diagram illustrating the lower pattern and a gate electrode.

Referring toFIGS.26to30, a display device30according to another embodiment may include a first pixel circuit part PCP1and a second pixel circuit part PCP2adjacent to the first pixel circuit part PCP1. In some embodiments, the second pixel circuit part PCP2may have a shape symmetrical to a shape of the first pixel circuit part PCP1.

However, the display device30may be substantially the same as the display device10except for the shape of the lower pattern SDP. For example, the display device30may include the first organic film layer PI1, the first barrier layer BRR1, the second organic film layer PI2, the second barrier layer BRR2, the third barrier layer BRR3, the buffer layer BFR, the first active pattern1100, the first gate insulating layer GI1, the first conductive pattern1200, the second gate insulating layer GI2, the second conductive pattern1300, the first interlayer insulating layer ILD1, the second active pattern1400, the third gate insulating layer GI3, the third conductive pattern1500, the second interlayer insulating layer ILD2, the fourth conductive pattern1600, the first via insulating layer VIA1, the fifth conductive pattern1700, and the second via insulating layer VIA2. Hereinafter, the shape of the lower pattern SDP will be mainly described.

As shown inFIGS.26and27, the lower pattern SDP included in the display device30may be disposed on the second barrier layer BRR2. In some embodiments, the lower pattern SDP may have a mesh shape defining a disconnection area DCA.

In some embodiments, the lower pattern SDP may include a first pattern PTN1and a second pattern PTN2. The first pattern PTN1may extend in the first direction D1. The second pattern PTN2may extend in the first direction D1and may be spaced apart from the first pattern PTN1in the second direction D2. For example, a shape of the first pattern PTN1and a shape of the second pattern PTN2may be the same.

In some embodiments, the first pattern PTN1and the second pattern PTN2may not be connected to each other. In other words, the first pattern PTN1and the second pattern PTN2may be disconnected from each other. For example, the disconnection area DCA may be positioned between the first pattern PTN1and the second pattern PTN2. In other words, the lower pattern SDP may not include the second part PRT2described with reference toFIG.9.

In more detail, the disconnection area DCA may be an area in which the first pattern PTN1and the second pattern PTN2are disconnected from each other. In other words, the lower pattern SDP may be partially removed from the disconnection area DCA. Accordingly, the second barrier layer BRR2may contact the third barrier layer BRR3in the disconnection area DCA.

In some embodiments, as shown inFIG.30, the display device30may include a first gate electrode1221and a second gate electrode1241arranged in the second direction D2. The first pattern PTN1may overlap the first gate electrode1221, and the second pattern PTN2may overlap the second gate electrode1241.

The first pattern PTN1and the second pattern PTN2may be disconnected from each other. In other words, the lower pattern SDP may not include the second portion PRT2described with reference toFIG.9. Accordingly, the unit area of the lower pattern SDP may be reduced.

FIG.31andFIG.32are layout diagrams illustrating a display device according to still another embodiment.

Referring toFIGS.31and32, the display device40according to still another embodiment may include a lower pattern SDP.

However, the display device40may be substantially the same as the display device10except for the shape of the lower pattern SDP. For example, the display device40may include the first organic film layer PI1, the first barrier layer BRR1, the second organic film layer PI2, the second barrier layer BRR2, the third barrier layer BRR3, the buffer layer BFR, the first active pattern1100, the first gate insulating layer GI1, the first conductive pattern1200, the second gate insulating layer GI2, the second conductive pattern1300, the first interlayer insulating layer ILD1, the second active pattern1400, the third gate insulating layer GI3, the third conductive pattern1500, the second interlayer insulating layer ILD2, the fourth conductive pattern1600, the first via insulating layer VIA1, the fifth conductive pattern1700, and the second via insulating layer VIA2. Hereinafter, the shape of the lower pattern SDP will be mainly described.

The lower pattern SDP included in the display device40may be disposed on the second barrier layer BRR2. In some embodiments, the lower pattern SDP may have an island shape.

In some embodiments, the lower pattern SDP may include a first pattern PTN1and a second pattern PTN2. The second pattern PTN2may have the same shape as the first pattern PTN1, and may not be connected to the first pattern PTN1.

In some embodiments, the first pattern PTN1may have a mesh shape. In addition, the gate electrodes1221may be arranged in a matrix shape. Accordingly, the first pattern PTN1may overlap the plurality of gate electrodes1221. For example, as shown inFIG.32, the first pattern PTN1may overlap the eight gate electrodes1221. In other words, the first pattern PTN1may correspond to the eight sub-pixels (i.e., two pixels). However, the number of the sub-pixels corresponding to the first pattern PTN1is not limited thereto. For example, the first pattern PTN1may correspond to four sub-pixels (i.e., one pixel). Alternatively, it may correspond to 12 sub-pixels (i.e., three pixels).

FIG.33andFIG.34are layout diagrams illustrating a display device according to still another embodiment.

Referring toFIGS.33and34, the display device50according to still another embodiment may include a lower pattern SDP.

However, the display device50may be substantially the same as the display device10except for the shape of the lower pattern SDP. For example, the display device50may include the first organic film layer PI1, the first barrier layer BRR1, the second organic film layer PI2, the second barrier layer BRR2, the third barrier layer BRR3, the buffer layer BFR, the first active pattern1100, the first gate insulating layer GI1, the first conductive pattern1200, the second gate insulating layer GI2, the second conductive pattern1300, the first interlayer insulating layer ILD1, the second active pattern1400, the third gate insulating layer GI3, the third conductive pattern1500, the second interlayer insulating layer ILD2, the fourth conductive pattern1600, the first via insulating layer VIA1, the fifth conductive pattern1700, and the second via insulating layer VIA2. Hereinafter, the shape of the lower pattern SDP will be mainly described.

The lower pattern SDP included in the display device50may be disposed on the second barrier layer BRR2. In some embodiments, the lower pattern SDP may have a mesh shape defining the disconnection area DCA, and may overlap the gate electrodes1221disposed in a matrix shape. In some embodiments, as shown inFIG.33, the disconnection area DCA may be randomly located. Accordingly, the lower pattern SDP may be randomly disconnected. Accordingly, the unit area of the lower pattern SDP may be reduced.

Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art.