Patent ID: 12211896

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Integrated chips often comprise transistors that are designed to operate at a number of different voltages. High voltage transistors are design to operate at a high breakdown voltage (e.g., a breakdown voltage of greater than approximately 20V, greater than approximately 50V, or other suitable values). One type of commonly used high voltage transistor is a laterally diffused MOSFET (LDMOS) device. An LDMOS device has a gate structure that is disposed over a substrate between a source region and a drain region. The gate structure is separated from the drain region by way of a drift region. The drift region comprises a lightly doped region of the substrate (e.g., a region of the substrate having a doping concentration that is less than that of the source region and/or the drain region).

During operation, a bias voltage may be applied to the gate structure to form an electric field that causes a channel region to extend below the gate structure and through the drift region. A breakdown voltage of the LDMOS device is typically proportional to a size and doping concentration of the drift region (e.g., a larger drift region will result in a larger breakdown voltage). However, if an electric field within the device is not uniform the breakdown voltage of the transistor device may be negatively affected. For example, the breakdown voltage of a LDMOS can be negatively affected due to spikes in the electric field that can occur at a p-n junction between the drift region and the substrate.

The present disclosure, in some embodiments, relates to an integrated chip comprising a transistor device having a gate electrode with a plurality of gate extensions that are configured to provide the transistor device with a high breakdown voltage. The gate electrode is disposed within a substrate between a source region and a drain region. A drift region is located between the gate electrode and the drain region. The plurality of gate extensions laterally protrude outward from a sidewall of the gate electrode and to over the drift region. The plurality of gate extensions are configured to generate an electric field within the drift region, which can laterally spread charges along a p-n junction of the device. By laterally spreading the charges, an electric field along a surface of the substrate can be spread out, thereby reducing spikes in the electric field and increasing a breakdown voltage of the transistor device.

FIG.1illustrates a three-dimensional view of some embodiments of an integrated chip100having a high voltage transistor device comprising a gate electrode with gate extensions.

The integrated chip100comprises a gate structure106disposed within a substrate102. In some embodiments, the gate structure106is recessed within the substrate102. In some such embodiments, the gate structure106extends from below an upper surface102uof the substrate102to the upper surface102uof the substrate102. A source region104is disposed on a first side of the gate structure106and a drain region108is disposed on a second side of the gate structure106opposite the first side. The source region104and the drain region108are separated by the gate structure106along a first direction114.

A drift region110is arranged between the gate structure106and the drain region108along the first direction114. In some embodiments, a well region109may be disposed within the substrate102below the gate structure106and laterally contacting the drift region110. One or more isolation structures112are disposed within the drift region110. The one or more isolation structures112extend in the first direction114between the gate structure106and the drain region108along the upper surface of the substrate102. The one or more isolation structures112are separated from one another by the drift region110along a second direction116that is perpendicular to the first direction114. In some embodiments, sidewalls of the one or more isolation structures112extend along the first direction114in parallel with one another. In some embodiments, the one or more isolation structures112comprise one or more dielectric materials disposed within trenches in the substrate102. In some embodiments, the one or more isolation structures112may comprise shallow trench isolation (STI) structures.

The gate structure106comprises a gate dielectric105and a gate electrode107over the gate dielectric105. The gate electrode107comprises a base region107band one or more gate extensions107e. The base region107bis separated from the drift region110by the gate dielectric105. In some embodiments, the gate dielectric105continuously extends from a first side of the base region107bto an opposing second side of the base region107b. The one or more gate extensions107eprotrude laterally outward from a sidewall of the base region107bof the gate electrode107to within the one or more isolation structures112. The one or more isolation structures112laterally and vertically separate the one or more gate extensions107efrom the drift region110. In some embodiments, the one or more gate extensions107eextend through a sidewall of the gate dielectric105.

During operation, a bias voltage may be applied to the gate electrode107. The bias voltage causes charges (e.g., positive or negative charges) within the gate electrode107to form an electric field in the underlying substrate102. Typically, the maximum breakdown voltage of the transistor device may be limited by junction edge breakdown effects due to surface field crowding at a junction of the drift region110and the well region109. However, the electric field generated by the one or more gate extensions107elaterally spreads the electric field along the surface of the substrate102(e.g., along the second direction116). By spreading the electric field, the one or more gate extensions107ereduce an electric field strength along a surface of the substrate102, thereby allowing for a higher breakdown voltage to be achieved by the transistor device.

FIGS.2A-2Cillustrate some additional embodiments of an integrated chip having a high voltage transistor device comprising a recessed gate electrode with gate extensions.

As shown in cross-sectional view200ofFIG.2A, the integrated chip comprises a source region104and a drain region108disposed within a substrate102. A drift region110is arranged between the source region104and the drain region108. In some embodiments, a well region109may surround the source region104, the drain region108, and the drift region110. In some embodiments, the substrate102and the well region109may have a first doping type (e.g., p-type), while the source region104, the drain region108, and the drift region110may have a second doping type (e.g., n-type). In some embodiments, the drift region110may have the second doping type (e.g., n-type), but with a lower doping concentration than the source region104and/or the drain region108.

A gate electrode107is disposed within the substrate102between the source region104and the drain region108. The gate electrode107is separated from the drain region108by the drift region110. The gate electrode107comprises a base region107band one or more gate extensions107e. The one or more gate extensions107eextend outward from the base region107balong a first direction114to directly over the drift region110. The base region107bis surrounded by a gate dielectric105. The one or more gate extensions107eare surrounded by one or more isolation structures112arranged within the drift region110. In some embodiments, the one or more gate extensions107emay extend directly over upper surfaces of the one or more isolation structures112and the gate dielectric105. In some embodiments, the one or more gate extensions107emay have a bottom surface that is in contact with both an upper surface of the gate dielectric105and an upper surface of the one or more isolation structures112.

In some embodiments, the gate electrode107may comprise a conductive material, such as a metal (e.g., tungsten, aluminum, or the like), doped polysilicon, or the like. In some embodiments, the gate dielectric105and the one or more isolation structures112may comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or the like.

In some embodiments, the base region107bmay have a first thickness204and the one or more gate extensions107emay have a second thickness206. In some embodiments, the second thickness206may less than to the first thickness204. For example, in some embodiments, the second thickness206may be between 50% and approximately 90% of the first thickness204. In some embodiments, the first thickness204may be in a range of between approximately 900 Angstroms (Å) and approximately 600 Å, between approximately 650 Å and approximately 750 Å, or other similar values. In other embodiments (not shown), the second thickness206may approximately equal to the first thickness204.

A plurality of conductive interconnects210-212are disposed within an inter-level dielectric (ILD) structure208over the substrate102. In some embodiments, the plurality of conductive interconnects210-212may comprise one or more conductive contacts210coupled to interconnect wires212. In some embodiments, the one or more conductive contacts210are electrically coupled to the source region104, the drain region108, and the gate electrode107. In some embodiments, the plurality of conductive interconnects210-212may comprise one or more of copper, tungsten, aluminum, or the like. In some embodiments, the ILD structure208may comprise one or more of silicon dioxide, doped silicon dioxide (e.g., carbon doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or the like.

FIG.2Billustrates a top-view202of the integrated chip ofFIG.2A. The cross-sectional view200ofFIG.2Ais taken along cross-sectional line A-A′ ofFIG.2B.

As shown in top-view202ofFIG.2B, the one or more gate extensions107eprotrude outward from a sidewall of the base region107balong the first direction114, while the base region107bextends in a second direction116past the one or more gate extensions107e. Adjacent ones of the one or more gate extensions107eare separated along the second direction116by both the drift region110and parts of at least two of the one or more isolation structures112.

In some embodiments, the one or more isolation structures112continuously extend along the first direction114from a first end contacting the gate dielectric105to a second end contacting the drain region108. In some embodiments, the one or more gate extensions107eare separated from the drain region108by the one or more isolation structures112. In such embodiments, the one or more gate extensions107eare separated from an end of the one or more isolation structures112by a non-zero distance d. In various embodiments, the non-zero distance d may be in a range of between approximately 400 μm and approximately 1,000 μm, between approximately 400 μm and approximately 750 μm, between approximately 250 μm and approximately 500 μm, or other suitable values.

FIG.2Cillustrates a cross-sectional view216of the integrated chip taken along cross-sectional line B-B′ ofFIG.2B.

As shown in the cross-sectional view216, the one or more isolation structures112are disposed within trenches218formed by interior surfaces102iof the substrate102. The gate extensions107eare disposed within additional trenches220that are formed by interior surfaces112iof the one or more isolation structures112. This allows the one or more gate extensions107eto be separated from one another by the drift region110and the one or more isolation structures112along the second direction116.

As shown in cross-sectional view200ofFIG.2Aand cross-sectional view216ofFIG.2C, a depletion region214is present along a p-n junction between the drift region110and the well region109and/or the substrate102. The depletion region214causes an electric field to form along the p-n junction. The electric field increases during operation of the transistor device due to bias voltages applied to the source region104, the drain region108, and/or the gate electrode107. However, the one or more gate extensions107eare able to generate electric fields that spread out charges along the p-n junction.

For example,FIG.2Dillustrates a cross-sectional view222of the integrated chip, taken along cross-sectional line B-B′ ofFIG.2B, during operation of the high voltage transistor device.

As shown in cross-sectional view222ofFIG.2D, during operation a bias voltage may be applied to the one or more gate extensions107e. The bias voltage causes the one or more gate extensions107eto form an electric field that extends into the well region109and the drift region110. The electric field causes charges,224and226, having opposite polarities to accumulate within the well region109and within the drift region110due to the doping types of the well region109and the drift region110. For example, in some embodiments, negative charges224may accumulate within the well region109and positive charges226may accumulate within the drift region110. The one or more gate extensions107emay spread out the charges,224and226, along the second direction116and past outermost ones of the one or more gate extensions107e. Spreading out the charges,224and226, may increase a width of the depletion region214along the second direction116and mitigate spikes the electric field along a surface of the substrate102(e.g., so that a surface electric field above the p-n junction is less than a critical electric field corresponding to a breakdown voltage of the device). By decreasing spikes in the electric field along the surface of the substrate102a breakdown voltage of the high voltage transistor device is increased.

FIG.3illustrates a cross-sectional view of some additional embodiments of an integrated chip300having a high voltage transistor device comprising a recessed gate electrode with gate extensions.

The integrated chip300comprises a gate electrode107recessed below an upper surface of a substrate102. The gate electrode107is separated from the substrate102by a gate dielectric105and by one or more isolation structures112. The gate electrode107comprises a base region107bdisposed over the gate dielectric105and one or more gate extensions107eprotruding outward from the base region107bto over the one or more isolation structures112. The gate dielectric105extends along sidewalls and a lower surface of the base region107b. The one or more isolation structures112extend along sidewalls and a lower surface of the one or more gate extensions107e.

In some embodiments, the one or more isolation structures112may have a different thickness (e.g., a greater thickness) along bottoms of the one or more gate extensions107ethan along sidewalls of the one or more gate extensions107e. In some embodiments, the one or more isolation structures112may vertically extend from bottoms of the one or more gate extensions107eto below a bottommost surface of the gate dielectric105. In some additional embodiments, the one or more isolation structures112may vertically extend from a horizontal plane extending along a top of the gate dielectric105to below the bottommost surface of the gate dielectric105.

In some embodiments, the gate dielectric105may laterally extend directly over parts, but not all, of the one or more isolation structures112. In some such embodiments, the gate dielectric105may line an upper surface and an interior sidewall of the one or more isolation structures112. In some additional embodiments, the gate dielectric105may extend to a non-zero distance302below the upper surface of the one or more isolation structures112. In such embodiments, the gate dielectric105may also line an outermost sidewall of the one or more isolation structures112.

In some embodiments, the gate dielectric105may comprise a protrusion304that extends outward from an upper surface of the gate dielectric105between the base region107band the one or more gate extensions107e. In some embodiments, the protrusion304extends to above a bottom surface of the one or more gate extensions107e. In some embodiments, the protrusion304may have tapered sidewalls that cause a width of the protrusion304to decrease as a height over the upper surface increases. The protrusion304may be a result of an etching process used to form the one or more gate extensions107e. For example, during fabrication the gate dielectric105may be formed along an angled sidewall of the one or more isolation structures112. The one or more isolation structures112may be subsequently etched to form gate extension trenches extending from within the one or more isolation structures112to the angled sidewall. Over-etching of the gate dielectric105will cause the gate dielectric105to be recessed below a top of the angled sidewall, resulting in the protrusion304. In other embodiments (not shown), the etching process may etch the gate dielectric105past the angled sidewall, so that the gate dielectric105the angled sidewall is completely removed and the resulting gate dielectric105has an outer sidewall that is separated from a sidewall of the isolation structures112by a non-zero distance that is over an upper surface of the one or more isolation structures112.

In some embodiments, one or more dielectric structures306are disposed over opposing outer edges of the gate electrode107. In some embodiments, the one or more dielectric structures306continuously extend from a first outer edge that is directly over the base region107bto a second outer edge that is directly over a source region104. In some embodiments, the one or more dielectric structures306continuously extend from a third outer edge that is directly over the one or more gate extensions107eof the gate electrode107to a fourth outer edge that is directly over a drain region108. In some embodiments, the one or more dielectric structures306may extend a non-zero distance310over opposing edges of the gate electrode107. In some embodiments, the non-zero distance310may be in a range of between approximately 200 Å and approximately 600 Å, between approximately 350 Å and approximately 500 Å, or other suitable values. In some embodiments, the one or more dielectric structures306may comprise one or more dielectric materials, such as an oxide, a nitride, or the like.

A silicide308is arranged along upper surfaces of the source region104, the drain region108, and the gate electrode107. The silicide308is configured to provide for a low resistance connection with conductive interconnects210-212. In various embodiments, the silicide308may comprise a nickel silicide, a titanium silicide, or the like. In some embodiments, outer edges of the silicide308are laterally separated from outer edges of the source region104, the drain region108, and the gate electrode107, so that parts of the source region104, the drain region108, and the gate electrode107that are directly below the one or more dielectric structures306may be free of the silicide308.

A contact etch stop layer (CESL)312vertically separates the substrate102and the one or more dielectric structures306from a first inter-level dielectric (ILD) layer208a. In some embodiments, the CESL312and/or the first ILD layer208aextend from directly over the one or more dielectric structures306to along sidewalls of the one or more dielectric structures306. A second ILD layer208bis disposed on the first ILD layer208a.

FIG.4illustrates a top-view of some additional embodiments of an integrated chip400having a high voltage transistor device comprising a gate electrode with gate extensions.

The integrated chip400comprises a gate electrode107having a base region107band one or more gate extensions107e. The one or more gate extensions107eprotrude outward from the base region107balong a first direction114to within one or more isolation structures112. The one or more gate extensions107eare separated from one another along a second direction116that is perpendicular to the first direction114.

In some embodiments, the one or more isolation structures112may be arranged along the second direction116at a pitch402, while closest ones of the one or more gate extensions107eare separated by a distance404that is larger than the pitch402. In such embodiments, closest ones of the one or more gate extensions107eare separated by an isolation structure that does not contain a gate extension. For example, in some embodiments, the one or more gate extensions107emay comprise a first gate extension107e1and a second gate extension107e2, which is a closest gate extension to the first gate extension107e1. The first gate extension107e1is disposed within a first isolation structure112aand the second gate extension107e2is disposed within a second isolation structure112b. A third isolation structure112c, which does not surround a gate extension, separates the first gate extension107e1from the second gate extension107e2.

FIGS.5A-5Billustrate some additional embodiments of an integrated chip having a high voltage transistor device comprising a recessed gate electrode with gate extensions.

As shown in cross-sectional view500ofFIG.5A(taken along cross-sectional line A-A′ ofFIG.5B), the integrated chip comprises a gate electrode107disposed over a substrate102. The gate electrode107comprises a base region107band one or more gate extensions107eprotruding outward from the base region107bto over one or more isolation structures112. A gate dielectric105continuously extends along sidewalls and a lower surface of the base region107band the one or more gate extensions107e. The gate dielectric105vertically and laterally separates the one or more gate extensions107efrom the one or more isolation structures112.

As shown in top-view502ofFIG.5B, the gate dielectric105extends around an outer perimeter of the gate electrode107in a closed and unbroken loop. By surrounding both the base region107band the one or more gate extensions107ewith the gate dielectric105, one or more processing steps (e.g., one or more lithography and/or etch processes) can be eliminated from a fabrication process used to form the transistor device. By eliminating one or more processing steps from a fabrication process used to form the transistor device, a cost of forming the integrated chip can be reduced.

FIGS.6A-6Billustrate some additional embodiments of an integrated chip having a high voltage transistor device comprising a gate electrode with gate extensions.

As shown in cross-sectional view600ofFIG.6A(taken along cross-sectional line A-A′ ofFIG.6B), the integrated chip comprises a gate electrode107having a base region107band one or more gate extensions107e. A gate dielectric105extends along sidewalls and a lower surface of the base region107b. The base region107bprotrudes outward from an upper surface102uof the substrate102. The one or more gate extensions107eprotrude outward from a sidewall of the base region107bthat is over the upper surface102uof the substrate102to directly over one or more isolation structures112.

As shown in top-view602ofFIG.6B(taken along line B-B′ ofFIG.6A), the gate dielectric105extends around an outer perimeter of the base region107bin a closed and unbroken loop. By having the one or more gate extensions107eprotrude outward from a sidewall of the base region107bthat is over the upper surface102uof the substrate102, one or more processing steps (e.g., one or more lithography and/or etch processes) can be eliminated from a fabrication process used to form the transistor device. By eliminating one or more processing steps from a fabrication process used to form the transistor device, a cost of forming the integrated chip can be reduced.

FIG.7illustrates a cross-sectional view of some embodiments of an integrated chip700having a high voltage transistor device region and a peripheral logic region.

The high voltage transistor device region702comprises a high-voltage transistor device that includes a gate electrode107disposed between a source region104and a drain region108. The gate electrode107has a base region107band one or more gate extensions107eextending outward from the base region107b.

One or more dielectric structures306are disposed over opposing edges of the gate electrode107. The one or more dielectric structures306respectively comprise a first dielectric material706and a second dielectric material708over the first dielectric material706. In some embodiments, a third dielectric material710may extend along outermost sidewalls of the first dielectric material706and the second dielectric material708. In some embodiments, the first dielectric material706and the second dielectric material708may comprise different dielectric materials, while the third dielectric material710may be a same dielectric material as the first dielectric material706or the second dielectric material708. In various embodiments, the first dielectric material706, the second dielectric material708, and the third dielectric material710may comprise one or more of an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

The peripheral logic region704comprises one or more additional transistor devices. The one or more additional transistor devices comprise a gate structure712that is arranged between a source region714and a drain region716and that is laterally surrounded by one or more sidewall spacers728. The gate structure712comprises a gate dielectric structure717separating a gate electrode722from the substrate102. One or more overlying dielectric layers724-726may be disposed over the gate electrode722. In some embodiments, the gate dielectric structure717may comprise a first gate dielectric material718and a second gate dielectric material720over the first gate dielectric material718. In some embodiments, the first gate dielectric material718may be a same material as first dielectric material706, the second gate dielectric material720may be a same material as the second dielectric material708, and the one or more sidewall spacers728may be a same material as the third dielectric material710. In some embodiments, the first gate dielectric material718may have a substantially same thickness as the first dielectric material706and the second gate dielectric material720may have a substantially same thickness as the second dielectric material708.

FIG.8illustrates a top-view of some additional embodiments of an integrated chip800having a high voltage transistor device comprising a recessed gate electrode with gate extensions.

The integrated chip800comprises a drain region108that is surrounded on opposing sides by source regions104a-104b. Gate structures106a-106bare also disposed along opposing sides of the drain region108and separate the drain region108from the source regions104a-104b, respectively. The gate structures106a-106brespectively comprise a base region107band one or more gate extensions107ethat extend outward from the base region107btowards the drain region108. In some embodiments, body regions802a-802bmay be separated from the gate structures106a-106bby the source regions104a-104b.

In some embodiments, the source regions104a-104bare electrically coupled together and the gate structures106a-106bare electrically coupled together. In some additional embodiments, the gate structures106a-106b, the source regions104a-104b, and the body regions802a-802bare substantially symmetric about a line804that bisects the drain region108.

During operation, charges within the drift region110and charges within the gate extensions107eare separated by both the gate dielectric105and the one or more STI regions112. Because the gate extensions107elaterally spread out the charges within the drift region110, the gate extensions107eincrease a capacitance between the drift region110and the gate electrodes107.

FIGS.9A-9Billustrate some additional embodiments of an integrated chip having a high voltage transistor device comprising a recessed gate electrode with gate extensions.

As shown in cross-sectional view900ofFIG.9A, a gate electrode107is disposed within a substrate102between a source region104and a drain region108. The gate electrode107comprises a base region107bsurrounded by a gate dielectric105and one or more gate extensions107ethat are surrounded by one or more isolation structures112. In some embodiments, the gate electrode107extends into the substrate102to a first depth902. In some embodiments, the first depth902may be in a range of between approximately 200 Å and approximately 800 Å, between approximately 500 Å and approximately 700 Å, or other suitable values. In some embodiments, the gate dielectric105may have a thickness904that is in a range of between approximately 700 Å and approximately 1,000 Å, between approximately 800 Å and approximately 900 Å, or other suitable values.

In some embodiments, the source region104and the drain region108are laterally surrounded by one or more additional isolation structures906. The one or more additional isolation structures906are separated from the one or more isolation structures112by way of the source region104and the drain region108. In some embodiments, the one or more isolation structures112extend into the substrate102to a second depth908that is substantially the same as the one or more additional isolation structures906. In some embodiments, the second depth908may be in a range of between approximately 2,000 Å and approximately 3,000 Å, between approximately 2,000 Å and approximately 2,500 Å, or other suitable values. As shown in top-view910ofFIG.9B, in some embodiments, the one or more additional isolation structures906may wrap around the transistor device in a closed loop.

FIGS.10A-24illustrate some embodiments of method of forming an integrated chip having a high voltage transistor device comprising a recessed gate electrode with gate extensions. AlthoughFIGS.10A-24are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.10A-24are not limited to such a method, but instead may stand alone as structures independent of the method.

As shown in cross-sectional view1000ofFIG.10A, a substrate102is patterned to form one or more isolation trenches1002. In various embodiments, the substrate102may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers, associated therewith. The one or more isolation trenches1002are formed by sidewalls and a horizontally extending surface of the substrate102. As shown in top-view1012ofFIG.10B, in some embodiments the one or more isolation trenches1002comprise rectangular shaped trenches that extend in parallel to each other along a first direction114and that are separated from one another along a second direction116that is perpendicular to the first direction114.

In some embodiments, the one or more isolation trenches1002may be formed by selectively exposing the substrate102to a first etchant1004according to a first masking layer1006. In some embodiments, the first masking layer1006may comprise a hard mask comprising a first hard mask layer1008and a second hard mask layer1010over the first hard mask layer1008. In some embodiments, the first hard mask layer1008comprises a first dielectric material (e.g., an oxide, a nitride, or the like) and the second hard mask layer1010comprises a second dielectric material (e.g., an oxide a nitride, or the like) that is different than the first dielectric material. In some embodiments, the first etchant1004may comprise a dry etchant. For example, in some embodiments, the first etchant1004may comprise an oxygen plasma etchant.

As shown in cross-sectional view1100ofFIG.11A, isolation structures112are formed within the one or more isolation trenches1002. As shown in top view1102ofFIG.11B, the one or more isolation structures112are separated from one another along the second direction116. In some embodiments, the one or more isolation structures112may be formed by forming one or more dielectric materials within the one or more isolation trenches1002. In some embodiments, the one or more dielectric materials may comprise an oxide, a nitride, or the like. In some embodiments, the one or more dielectric materials may be formed by way of a deposition process (e.g., a chemical vapor deposition (CVD) process, a plasma enhanced CVD process, or the like). In some embodiments, the one or more dielectric materials may be formed within the one or more isolation trenches1002prior to removal of an entirety of the first masking layer (1006ofFIG.10A). A planarization process (e.g., a chemical mechanical planarization process) may be subsequently performed to remove excess of the dielectric material from laterally outside of the one or more isolation trenches1002. In some embodiments, the one or more isolation structures112may be formed concurrent with the formation of additional isolation structures (not shown) that provide isolation between adjacent transistor devices (e.g., as shown inFIGS.9A-9B).

As shown in cross-sectional view1200ofFIG.12A, a gate base recess1202is formed within the substrate102. In some embodiments, the gate base recess1202may also extend to within the one or more isolation structures112. In some embodiments, the gate base recess1202extends into the substrate102to a first depth1208that is less than a second depth1210of the one or more isolation structures112. The gate base recess1202is formed by one or more sidewalls1202s1and a horizontally extending surface1202h1of the substrate102. In some embodiments, the gate base recess1202may be further formed by one or more sidewalls1202s2and a horizontally extending surface1202h2of the one or more isolation structures112. As shown in top-view1212ofFIG.12B, the gate base recess1202continuously extends in the second direction116past opposing sidewalls of the one or more isolation structures112.

In some embodiments, the gate base recess1202may be formed by selectively exposing the substrate102to a second etchant1204according to a second masking layer1206. In various embodiments, the second masking layer1206may comprise a hard mask layer, a photosensitive material (e.g., photoresist), or the like. In some embodiments, the second etchant1204may comprise a dry etchant. For example, in some embodiments, the second etchant1204may comprise an oxygen plasma etchant.

As shown in cross-sectional view1300ofFIG.13Aand top-view1306ofFIG.13B, a well region109and a drift region110are formed within the substrate102. The drift region110laterally surrounds the one or more isolation structures112and vertically extends to below the one or more isolation structures112. The well region109vertically and/or laterally abuts the drift region110. In some embodiments, the well region109may be formed by implanting a first dopant species into the substrate102and the drift region110may be formed by subsequently implanting a second dopant species1302into the substrate102according to a third masking layer1304. In various embodiments, the first dopant species may comprise a first doping type (e.g., formed by p-type dopants such as boron, aluminum, or the like) and the second dopant species1302may comprise a second doping type (e.g., formed by n-type dopants such as phosphorus, arsenic, or the like). In some embodiments, the third masking layer1304may comprise a photosensitive material (e.g., a photoresist). In some alternative embodiments, the well region109and/or the drift region110may be formed prior to forming the one or more isolation structures112.

As shown in cross-sectional view1400ofFIG.14Aand top-view1402ofFIG.14B, a gate dielectric105is formed over the substrate102. In some embodiments, the gate dielectric105is formed within the gate base recess1202, and over the substrate102and the one or more isolation structures112. In some embodiments, the gate dielectric105may comprise an oxide, a nitride, or the like. In some embodiments, the gate dielectric105may be formed by way of a deposition process (e.g., a CVD process, a PE-CVD process, or the like).

As shown in cross-sectional view1500ofFIG.15A, one or more gate extension trenches1502are formed within the one or more isolation structures112. The one or more gate extension trenches1502extend into the one or more isolation structures112to a third depth1504that is less than the second depth1210. In some embodiments, the third depth1504may also be less than the first depth1208of the gate base recess1202. In some embodiments, the one or more isolation structures112extend a distance d past the one or more gate extension trenches1502, so that the one or more gate extension trenches1502are formed by sidewalls and horizontally extending surfaces of the one or more isolation structures112.FIG.15Billustrates a top-view1510of the cross-sectional view1500ofFIG.15A. As shown in top-view1510, the one or more gate extension trenches1502extend outward from different positions of the gate base recess1202.

In some embodiments, the one or more gate extension trenches1502may be formed by selectively exposing the gate dielectric105and the one or more isolation structures112to a third etchant1506according to a fourth masking layer1508. In various embodiments, the fourth masking layer1508may comprise a hard mask layer, a photosensitive material (e.g., photoresist), or the like. In some embodiments, the third etchant1506may comprise a dry etchant. In some alternative embodiments (not shown), the gate extension trenches1502may be formed concurrent with the gate base recess1202. In some such embodiments, an etchant (e.g., a dry etchant comprising CF4) having a relatively low etching selectivity between silicon and silicon oxide may be used.FIG.15Cillustrates a three-dimensional view1512of the cross-sectional view ofFIG.15Aand the top-view1510ofFIG.15Bafter removal of the fourth masking layer1508.

As shown in cross-sectional view1600ofFIG.16Aand top-view1604ofFIG.16B, a gate material1602is formed within the gate base recess1202and within the one or more gate extension trenches1502. In some embodiments, the gate material1602may be formed to extend from within the gate base recess1202and the one or more gate extension trenches1502to directly over an upper surface of the substrate102. In some embodiments, the gate material1602may comprise polysilicon, a metal, or the like. In some embodiments, the gate material1602may be formed by way of a deposition process (e.g., a CVD process, a PE-CVD process, or the like) and/or a plating process (e.g., an electroplating process, an electroless plating process, or the like).

As shown in cross-sectional view1700ofFIG.17A, a planarization process is performed along line1702to form a gate electrode107by removing an excess of the gate material (1602ofFIG.16) and the gate dielectric105from over the substrate102. As shown in top-view1704ofFIG.17B, the gate electrode107comprises a base region107band one or more gate extensions107eprotruding laterally outward from a sidewall of the gate electrode107forming the base region107bto directly over the one or more isolation structures112. In some embodiments, the planarization process may comprise a chemical mechanical planarization (CMP) process.

As shown in cross-sectional view1800ofFIG.18, a gate stack1802is formed over the substrate102. The gate stack1802extends past opposing sides of the gate electrode107. In some embodiments, the gate stack1802may comprise a first dielectric material706, a second dielectric material708over the first dielectric material706, a gate electrode material1804over the second dielectric material708, a third dielectric material1806over the gate electrode material1804, and a fourth dielectric material1808over the third dielectric material1806.

As shown in cross-sectional view1900ofFIG.19, the gate stack (1802ofFIG.18) is patterned to form a patterned gate stack1902. In some embodiments, after patterning the gate stack (1802ofFIG.18) one or more sidewall spacers1904are formed along opposing sides of the patterned gate stack1902. The patterned gate stack1902exposes a source area1906and a drain area1908of the substrate102on opposing sides of the gate electrode107. In some embodiments (not shown), the gate stack may be patterned to form an additional gate stack in a peripheral logic region on another part of the substrate (e.g., as shown inFIG.7).

As shown in cross-sectional view2000ofFIG.20, one or more dopant species2002are implanted into the substrate102to form a source region104and a drain region108on opposing sides of the gate electrode107. In some embodiments, the one or more dopant species2002may be selectively implanted into the substrate102according to the patterned gate stack1902. In such embodiments, the source region104is formed within the source area1906and the drain region108is formed within the drain area1908. In various embodiments, the one or more dopant species2002may comprise n-type dopants (e.g., phosphorus, arsenic, etc.) or p-type dopants (e.g., boron, aluminum, etc.). In some embodiments, an anneal may be performed after the one or more dopant species2002are implanted into the substrate102to drive the dopants further into the substrate102.

As shown in cross-sectional view2100ofFIG.21, a planarization process is performed (along line2102) on the patterned gate stack (1902ofFIG.20) to remove one or more layers of the patterned gate stack and to form a dielectric stack2104. In some embodiments, the planarization process removes the gate electrode material (1804ofFIG.18), the third dielectric material (1806ofFIG.18), and the fourth dielectric material (1808ofFIG.18). In some embodiments, the planarization process may comprise a chemical mechanical polishing (CMP) process.

As shown in cross-sectional view2200ofFIG.22, the dielectric stack (2104ofFIG.21) may be selectively etched to remove parts of the dielectric stack. In some embodiments, the dielectric stack is not removed from over the gate dielectric105so as to prevent damage to the gate dielectric105. In such embodiments, etching the dielectric stack forms one or more dielectric structures306that cover at least one uppermost surface of the gate dielectric105and have sidewalls forming an opening2204that extends through the one or more dielectric structures306to expose an upper surface of the gate electrode107. In some embodiments, the dielectric stack (2104ofFIG.21) may be selectively etched by forming a fifth masking layer2202over the dielectric stack and subsequently exposing unmasked parts of the dielectric stack to an etchant2206that removes unmasked parts of the dielectric stack.

As shown in cross-sectional view2300ofFIG.23, a salicide process is performed. The salicide process forms a silicide308along upper surfaces of the source region104, the drain region108, and the gate electrode107. In some embodiments, the silicide308is laterally set back from edges of the source region104, the drain region108, and the gate electrode107that are covered by the one or more dielectric structures306. In some embodiments, the salicide process may be performed by depositing a metal (e.g., aluminum) onto the source region104, the drain region108, and the gate electrode107, followed by a high temperature anneal.

As shown in cross-sectional view2400ofFIG.24, an inter-level dielectric (ILD) structure208is formed over the substrate102and a plurality of conductive interconnects210-212are formed within the ILD structure208. In some embodiments, the ILD structure208may comprise a plurality of stacked ILD layers formed over the substrate102. In some embodiments (not shown), the plurality of stacked ILD layers are separated by etch stop layers (not shown). In some embodiments, the plurality of conductive interconnects210-212may comprise conductive contacts210and interconnect wires212. In some embodiments, the plurality of conductive interconnects210-212may be formed by forming one of the one or more ILD layers (e.g., an oxide, a low-k dielectric, or an ultra low-k dielectric) over the substrate102, selectively etching the ILD layer to form a via hole and/or a trench within the ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the via hole and/or the trench, and performing a planarization process (e.g., a chemical mechanical planarization process).

FIG.25illustrates a flow diagram of some embodiments of a method2500of forming an integrated chip having a high voltage transistor device comprising a recessed gate electrode with gate extensions.

While the disclosed method2500is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At2502, one or more isolation structures are formed within a substrate.FIGS.10A-11Billustrate cross-sectional views,1000and1100, and top-views,1012and1102, of some embodiments corresponding to act2502.

At2504, the substrate is selectively etched to form a gate base recess within the substrate.FIGS.12A-12Billustrate a cross-sectional view1200and a top-view1212of some embodiments corresponding to act2504.

At2506, a well region and a drift region are formed within the substrate.FIGS.13A-13Billustrate a cross-sectional view1300and a top-view1306of some embodiments corresponding to act2506.

At2508, a gate dielectric is formed within the gate base recess and over the one or more isolation structures.FIGS.14A-14Billustrate a cross-sectional view1400and a top-view1402of some embodiments corresponding to act2508.

At2510, one or more gate extension trenches are formed to extend outward from the gate base recess to within the one or more isolation structures.FIGS.15A-15Cillustrate a cross-sectional view1500, a top-view1510, and a three-dimensional view1512of some embodiments corresponding to act2510.

At2512, a gate electrode is formed within the gate base recess and the one or more gate extension trenches.FIGS.16A-17Billustrate cross-sectional views,1600and1700, and top-views,1604and1704, of some embodiments corresponding to act2512.

At2514, a gate stack is formed over the gate electrode.FIG.18illustrates a cross-sectional view1800of some embodiments corresponding to act2514.

At2516, the gate stack is patterned to form a patterned gate stack over the gate electrode.FIG.19illustrates a cross-sectional view1900of some embodiments corresponding to act2516.

At2518, the substrate is implanted according to the patterned gate stack to form source and drain regions on opposing sides of the gate electrode.FIG.20illustrates a cross-sectional view2000of some embodiments corresponding to act2518.

At2520, one or more layers are removed from the patterned gate stack to form a dielectric stack.FIG.21illustrates a cross-sectional view2100of some embodiments corresponding to act2520.

At2522, the dielectric stack is patterned to form one or more dielectric structures covering the gate dielectric.FIG.22illustrates a cross-sectional view2200of some embodiments corresponding to act2522.

At2524, a salicide process is performed.FIG.23illustrates a cross-sectional view2300of some embodiments corresponding to act2524.

At2526, one or more conductive contacts are formed within an inter-level dielectric (ILD) layer formed over the gate electrode.FIG.24illustrates a cross-sectional view2400of some embodiments corresponding to act2526.

Accordingly, in some embodiments, the present disclosure relates to an integrated chip comprising a transistor device having a gate structure with gate extensions that are configured to provide the transistor device with a high breakdown voltage.

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate; a drain region disposed within the substrate and separated from the source region along a first direction; a drift region disposed within the substrate between the source region and the drain region; a plurality of isolation structures disposed within the drift region; and a gate electrode disposed within the substrate, the gate electrode having a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures. In some embodiments, the plurality of isolation structures have outer sidewalls that are separated by the drift region along a second direction that is perpendicular to the first direction. In some embodiments, the plurality of isolation structures respectively extend past opposing sides of respective ones of the plurality of gate extensions along a second direction that is perpendicular to the first direction. In some embodiments, the plurality of gate extensions are separated from one another by the plurality of isolation structures and by the drift region along a second direction that is perpendicular to the first direction. In some embodiments, the plurality of isolation structures are between the plurality of gate extensions and the drain region. In some embodiments, the integrated chip further includes a gate dielectric disposed along sidewalls and a lower surface of the base region of the gate electrode, the plurality of isolation structures having sidewalls that directly contact a sidewall of the gate dielectric. In some embodiments, the integrated chip further includes a gate dielectric disposed along sidewalls and a lower surface of the base region of the gate electrode, the plurality of isolation structures continuously extending along an upper surface of the substrate from the gate dielectric to the drain region. In some embodiments, the plurality of isolation structures include one or more dielectric material disposed within trenches in the substrate; and the plurality of gate extensions are disposed within additional trenches formed by interior surfaces of the plurality of isolation structures. In some embodiments, the integrated chip further includes a gate dielectric disposed along sidewalls and a lower surface of the base region of the gate electrode; one or more dielectric structures disposed over opposing outer edges of the gate electrode and over the gate dielectric; and an inter-level dielectric (ILD) disposed over and along sidewalls of the one or more dielectric structures.

In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate; a drain region disposed within the substrate; a gate dielectric lining interior surfaces of the substrate; a gate electrode disposed between the source region and the drain region and having a base region over the gate dielectric and a plurality of gate extensions, the plurality of gate extensions protruding outward from a sidewall of the base region of the gate electrode forming the drain region; and a plurality of isolation structures continuously extending between the gate dielectric and the drain region, the plurality of isolation structures respectively surrounding one of the plurality of gate extensions. In some embodiments, the integrated chip further includes a drift region disposed within the substrate between the base region and the drain region, the plurality of isolation structures are separated from one another by the drift region. In some embodiments, the drift region extends past opposing sides of the plurality of isolation structures along a first direction and along a second direction that is perpendicular to the first direction. In some embodiments, the integrated chip further includes one or more dielectric structures disposed over opposing outer edges of the gate electrode; an inter-level dielectric (ILD) disposed over and along sidewalls of the one or more dielectric structures; and a silicide arranged along an upper surface of the gate electrode, the one or more dielectric structures covering one or more parts of the gate electrode that are outside of the silicide. In some embodiments, the one or more dielectric structures respectively include a first dielectric material, a second dielectric material over the first dielectric material, and a third dielectric material along sidewalls of the first dielectric material and the second dielectric material. In some embodiments, the base region extends to a first depth below an upper surface of the substrate and the plurality of gate extensions extend to a second depth below the upper surface of the substrate, the second depth being less than the first depth. In some embodiments, the plurality of isolation structures extend to a greater depth within the substrate than the gate dielectric. In some embodiments, the gate dielectric includes a protrusion arranged between the base region and a gate extension of the plurality of gate extensions, the protrusion extending outward from an upper surface of the base region to above a bottom of the gate extension. In some embodiments, a bottom surface of a gate extension of the plurality of gate extensions is in contact with both an upper surface of the gate dielectric and an upper surface of an isolation structure of the plurality of isolation structures.

In yet other embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate; selectively etching the substrate to form a gate base recess within the substrate; selectively etching the plurality of isolation structures to form a plurality of gate extension trenches extending outward from the gate base recess; forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and forming a source region and a drain region on opposing sides of the gate electrode. In some embodiments, the method further includes forming a gate dielectric within the gate base recess prior to selectively etching the plurality of isolation structures to form the plurality of gate extension trenches.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.