Patent ID: 12237253

DETAILED DESCRIPTION

FIG.1is an exemplary layout diagram of a semiconductor package according to some embodiments.FIG.2is a cross-sectional view along line A-A ofFIG.1.FIG.3is an enlarged view of region R1ofFIG.2.FIG.4is an enlarged view of region R2ofFIG.3.FIGS.5A to5Dare various layout diagrams of region R1ofFIG.2.

Referring toFIGS.1to5A, a semiconductor packages according to some embodiments may include a package substrate100, an interposer200, a first semiconductor chip310, a second semiconductor chip320, and a molding member400.

The package substrate100may be a substrate for a semiconductor package. As an example, the package substrate100may be a printed circuit board (PCB). The package substrate100may include a lower side and an upper side that are opposite to each other.

The package substrate100may include an insulating core101, a first substrate pad102and a second substrate pad104. The first substrate pad102and the second substrate pad104may be used to electrically connect the package substrate100to other components, respectively. For example, the first substrate pad102may be exposed from a lower surface of the insulating core101, and the second substrate pad104may be exposed from an upper surface of the insulating core101. For example, the first substrate pad102and the second substrate pad104may include metallic substances, e.g., copper (Cu) or aluminum (Al).

Wiring patterns for electrically connecting the first substrate pad102and the second substrate pad104may be formed inside the insulating core101. Although the insulating core101is shown as a single layer, this is only for convenience of explanation. For example, the insulating core101may include multiple layers, and multi-layered wiring patterns may be formed inside the insulating core101.

The package substrate100may be mounted on a motherboard or the like of an electronic device. For example, a substrate bump190connected to the first substrate pad102may be formed. The package substrate100may be mounted on the motherboard or the like of the electronic device through the substrate bump190. The package substrate100may be, e.g., a BGA (Ball Grid Array substrate).

The substrate bump190may be, e.g., a solder bump. The substrate bump190may have various shapes, e.g., a land, a ball, a pin, and a pillar. The number, interval, arrangement form, and the like of the substrate bump190are not limited to those shown in the drawings, and may be formed depending on the various designs.

The interposer200may be placed on the upper side of the package substrate100. The interposer200may be, e.g., a silicon interposer or an organic interposer. The interposer200may include an upper surface and a lower surface that are opposite to each other. The lower surface of the interposer200may face the upper surface of the package substrate100. The interposer200may be used to facilitate the connection between the package substrate100and the semiconductor chips310and320to be described later and to reduce the warpage of the package substrate100.

The interposer200may include a redistribution structure210, a first lower pad230, a second lower pad220, and an upper pad270. The first lower pad230, the second lower pad220, and the upper pad270may each be used to electrically connect the interposer200to other components. For example, as shown inFIG.2, the first lower pad230and the second lower pad220may each be exposed from the lower surface of the redistribution structure210, and the upper pad270may be exposed from the upper surface of the redistribution structure210. For example, the first lower pad230, the second lower pad220, and the upper pad270may include metallic substances e.g., copper (Cu) or aluminum (Al).

The interposer200may be mounted on the upper side of the package substrate100. For example, a first interposer bump292and a second interposer bump290may be formed between the package substrate100and the interposer200. The first interposer bump292may connect some of the plurality of second substrate pads104to the first lower pad230, and the second interposer bump290may connect some others of the plurality of the second substrate pads104to the second lower pad220. The package substrate100and the interposer200may be electrically connected accordingly.

In some embodiments, the first lower pad230and the second lower pad220may be formed at the same level. As used herein, the term “same level” means formation by the same fabricating process. For example, the first lower pad230and the second lower pad220may have the same material composition as each other. In some embodiments, the first interposer bump292and the second interposer bump290may be formed at the same level.

The first interposer bump292and the second interposer bump290may each be solder bumps including a low melting point metal, e.g., tin (Sn), tin (Sn) alloys or the like. The first interposer bump292and the second interposer bump290may each have various shapes, e.g., a land, a ball, a pin, and a pillar. The first interposer bump292and the second interposer bump290may be formed of a single layer or multiple layers, respectively. As an example, if each of the first interposer bump292and the second interposer bump290is formed of a single layer, the single layer may include tin-silver (Sn—Ag) solder or copper (Cu). As another example, when each of the first interposer bumps292and the second interposer bumps290is formed of multiple layers, the multiple layers are made of a copper pillar (Cu pillar) and a solder. The number, interval, arrangement form, and the like of the first interposer bumps292and the second interposer bumps290are not limited to those shown in the drawings and may depend on various designs.

In some embodiments, a first underfill280may be formed between the package substrate100and the interposer200. The first underfill280may fill a space between the package substrate100and the interposer200. Further, the first underfill280may cover the first interposer bump292and the second interposer bump290. The first underfill280may prevent a breakage or the like of the interposer200, by fixing the interposer200onto the package substrate100. For example, the first underfill280may include an insulating polymeric material, e.g., an EMC (epoxy molding compound).

As shown inFIG.3, the redistribution structure210may include a plurality of sequentially stacked redistribution layers (e.g., first to fourth redistribution layers). The redistribution structure210may electrically connect the first lower pad230and/or the second lower pad220and the upper pad270through the plurality of redistribution layers.

In detail, each redistribution layer may include redistribution insulating films210ato210d, redistribution patterns212ato212d, and redistribution plugs214ato214d. The redistribution insulating films210ato210dmay cover the redistribution patterns212ato212d. For example, a first redistribution pattern212amay be formed on the first lower pad230and the second lower pad220. The first redistribution insulating film210amay cover the first redistribution pattern212a. The redistribution plugs214ato214dmay interconnect the redistribution patterns212ato212dplaced at different levels from each other. For example, a second redistribution pattern212bextending along the upper surface of the first redistribution insulating film210amay be formed. The second redistribution plug214bmay penetrate the first redistribution insulating film210ato connect the first redistribution pattern212aand the second redistribution pattern212b.

Each redistribution layer may perform various functions depending on the design of the layer. For example, the redistribution patterns212ato212dmay include signal patterns, ground patterns, power patterns, and the like. Here, the ground patterns may transmit and receive a ground signal GND, and the power patterns may transmit and receive a power signal PWR. The signal patterns may transmit and receive various signals (e.g., data signals) except the ground signal and the power signal.

The second lower pad220may be connected to the redistribution patterns212ato212d. For example, the first redistribution plug214amay penetrate a pad insulating film202to connect the second lower pad220and the first redistribution pattern212a. Therefore, the second lower pad220may be electrically connected to the redistribution structure210and may transmit and receive data signals, ground signals or power signals. In an embodiment, the second lower pad220may be a signal pad that transmits and receives data signals, ground signals or power signals.

In some embodiments, the first lower pad230may not be connected to the redistribution patterns212ato212d. For example, the first lower pad230may not be connected to the first redistribution plug214a, e.g., the first lower pad230may be completely covered by the pad insulating film202. That is, the first lower pad230may not be electrically connected to the redistribution structure210. In an embodiment, the first lower pad230may be a dummy pad that does not transmit or receive data signals, ground signals or power signals. In another embodiment, the first lower pad230may be a ground pad that transmits and receives the ground signals.

In some embodiments, the pad insulating film202may be formed on the lower surface of the redistribution structure210. For example, as shown inFIG.3, the first redistribution pattern212amay extend along the upper surface of the pad insulating film202. The first lower pad230and the second lower pad220may be formed inside the pad insulating film202, respectively. Further, the first lower pad230and the second lower pad220may be exposed from the lower surface of the pad insulating film202, respectively. For example, the pad insulating film202may include a photosensitive insulating material, e.g., a PID (photoimageable dielectric).

In some embodiments, a passivation film260may be formed on the lower surface of the pad insulating film202. The passivation film260may expose at least a part of the first lower pad230and/or at least a part of the second lower pad220. For example, the passivation film260may include an opening265that exposes at least a part of the first lower pad230and/or at least a part of the second lower pad220. Through the opening265, the first interposer bump292may be connected to the first lower pad230and the second interposer bump290may be connected to the second lower pad220. For example, the passivation film260may include a thermosetting resin, e.g., an epoxy resin, a thermoplastic resin, e.g., polyimide, or a photosensitive insulating material, e.g., a PID.

In some embodiments, each of the first lower pad230and the second lower pad220may include first seed patterns224and234and first metal patterns222and232. The first seed patterns224and234and the first metal patterns222and232may be sequentially stacked on the passivation film260.

The first metal patterns222and232may include conductive materials, e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof. For example, the first metal patterns222and232may include copper (Cu). The first seed patterns224and234may serve as a seed for the formation of the first metal patterns222and232. For example, the first seed patterns224and234may include copper (Cu). In some embodiments, the first seed patterns224and234may be formed of multiple layers. As an example, the first seed patterns224and234may be formed of a double layer of titanium (Ti)/copper (Cu).

In some embodiments, each of the redistribution patterns212ato212dmay include a second seed pattern215and a second metal pattern217. The second seed pattern215and the second metal pattern217may be sequentially stacked on the redistribution insulating films210ato210d. For example, as shown inFIG.4, the first redistribution pattern212amay include a second seed pattern215and a second metal pattern217that are sequentially stacked on the first redistribution insulating film210a.

The second metal pattern217may include conductive materials, e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof. For example, the second metal pattern217may include copper (Cu). The second seed pattern215may serve as a seed for the formation of the second metal pattern217. For example, the second seed pattern215may include copper (Cu).

In some embodiments, the thickness of each of the first lower pad230and the second lower pad220may be greater than the thickness of the first redistribution pattern212a, e.g., the thicknesses of the first lower pad230and the second lower pad220may be equal to each other. For example, as illustrated inFIG.4, a thickness TH1of the first metal patterns232may be greater than a thickness TH3of the second metal pattern217, e.g., along a direction normal to a bottom of the package substrate100. This may be attributed to the fact that a part of the first lower pad230may be lost in the process of forming the first interposer bump292and the second interposer bump290. The thickness TH1of the first metal patterns222and232, e.g., thicknesses of the first metal patterns222and232may be equal to each other, may be about 5 μm or more, e.g., the thickness TH1may be about 8 μm to about 10 μm. For example, as further illustrated inFIG.4, a thickness TH2of the pad insulating film202may be larger than the thickness TH1of the first metal patterns222and232to extend above and completely cover tops of the first metal patterns222and232.

The plurality of second lower pads220may be spaced apart from each other and exposed from the lower surface of the interposer200. A second interposer bump290may be placed on each second lower pad220. That is, the plurality of second interposer bumps290may be placed to correspond to the second lower pad220. The second interposer bump290may electrically connect the second substrate pad104and the second lower pad220accordingly. In some embodiments, the second lower pad220may include copper (Cu).

The first lower pad230may be formed in a bent line shape (e.g., a snake shape) from a planar viewpoint. For example, as shown inFIG.5A, the first lower pad230may include a plurality of extensions (e.g., first to fourth extensions232a,232b,232cand232d) and a plurality of connections (e.g., first to third connections234a,234band234c) connected to define the bent line shape (e.g., a snake shape).

In detail, referring toFIG.5A, the first to fourth extensions232a,232b,232cand232dmay be spaced apart from each other and extend side by side in a first direction Y. In other words, the first to fourth extensions232a,232b,232cand232dmay extend in the first direction Y, and may be spaced apart from each other in a second direction X. The first to third connections234a,234band234cmay each extend in the second direction X, which intersects the first direction Y, and may interconnect the first to fourth extensions232a,232b,232cand232d. Here, the first direction Y and the second direction X are directions parallel to the lower surface of the interposer200, respectively. As an example, the first connection234amay connect the first extension232aand the second extension232b, and the second connection234bmay connect the second extension232band the third extension232c.

In some embodiments, the first connection234amay extend from one end of the second extension232b, and the second connection234bmay extend from the other end of the second extension232b. Accordingly, the first lower pad230may continuously extend in the bent line shape (e.g., a snake shape).

In some embodiments, the first connection234aand the second connection234bmay not overlap in the second direction X. In some embodiments, the second connection234band the third connection234cmay overlap in the second direction X. For example, the lengths of the first to fourth extensions232a,232b,232cand232dextending in the first direction Y may be the same as each other. As used herein, the term “same” means not only exactly the same, but also minute differences that may occur due to process margins and the like.

As further illustrated inFIGS.3and5A, the lower surface of the interposer200may include a plurality of pad regions230S that are spaced apart from each other (e.g., dashed square regions spaced apart from each other over the first lower pad230inFIG.5A). Each pad region230S may refer to a region in which the first interposer bump292is placed. That is, the plurality of first interposer bumps292may be placed to correspond to the pad region230S, e.g., one-to-one correspondence. At least a part of the first lower pad230may overlap each pad region230S. Here, the overlap means an overlap in a direction that intersects the first direction Y and the second direction X (e.g., a vertical direction that intersects the lower surface of the interposer200). The first interposer bump292may electrically connect the second substrate pad104and the first lower pad230accordingly. In some embodiments, the first lower pad230may include copper (Cu).

In some embodiments, the width W2, e.g., along the second direction X, of each pad region230S may be the same as the width W1, e.g., along the second direction X, of each second lower pad220. Here, the width means a width in a direction parallel to the lower surface of the interposer200(e.g., the second direction X). The width W1of each second lower pad220and the width W2of each pad region230S may be, e.g., about 5 μm or more. As an example, the width W1of each second lower pad220and the width W2of each pad region230S may be about 10 μm to about 30 μm.

In some embodiments, a spaced distance D2between the pad regions230S, e.g., along the second direction X, may be greater than a spaced distance D1between the second lower pads220, e.g., along the second direction D1. The spaced distance D2between the pad regions230S may be, e.g., about 5 μm or more. As an example, the spaced distance D2between the pad regions230S may be about 10 μm to about 30 μm.

In some embodiments, a distance D3of the pad regions230S spaced apart from the second lower pad220may be smaller than the spaced distance D2between adjacent ones of the pad regions230S, e.g., the distance D3may be a distance along the second direction X between outermost facing edges of the pad regions230S and the corresponding second lower pads220. Although the distance D3of the pad regions230S spaced apart from the second lower pad220is shown as being greater than the spaced distance D1between adjacent ones of the second lower pads220, this is only an example.

In some embodiments, each pad region230S may overlap a plurality of extensions among the extensions (e.g., first to fourth extensions232a,232b,232cand232d). For example, one of the pad regions230S (e.g., a pad region230S placed on the left side inFIG.5A) may overlap a part of the first extension232a, a part of the second extension232b, and a part of the third extension232c. Accordingly, each first interposer bump292may be connected to a plurality of extensions among the extensions (e.g., the first to fourth extensions232a,232b,232cand232d). For example, each first interposer bump292may be connected to three extensions (e.g., first to third extensions232a,232band232c).

In some embodiments, at least a part of the pad regions230S may overlap at least a part of the connections (e.g., first to third connections234a,234band234c). For example, one of the pad regions230S (e.g., a pad region230S located on the left upper end inFIG.5A) may overlap the first connection234a.

In some embodiments, some of the extensions (e.g., first to fourth extensions232a,232b,232cand232d) and the connections (e.g., first to third connections234a,234band234c) may not overlap the pad regions230S. For example, the fourth extension232dand the third connection234cmay not overlap the pad regions230S.

In some embodiments, a widths W31of each extension (e.g., first to fourth extensions232a,232b,232cand232d) may be identical to each other. Here, the width W31refers to a width in a direction (e.g., the second direction X) which intersects a length direction (e.g., the first direction Y) of each extension. The width W31of each of the first to fourth extensions232a,232b,232cand232dmay be, e.g., about 5 μm or less. As an example, the width W31of each of the first to fourth extensions232a,232b,232cand232dmay be about 2 μm to about 5 μm.

In some embodiments, a spaced distance D4between the respective extensions (e.g., first to fourth extensions232a,232b,232cand232d) may be identical to each other. The spaced distance D4between the first to fourth extensions232a,232b,232cand232dmay be, e.g., about 5 μm or less. As an example, the spaced distance D4between the first to fourth extensions232a,232b,232cand232dmay be about 2 μm to about 5 μm. In some embodiments, the spaced distance D4between the respective extensions (e.g., first to fourth extensions232a,232b,232cand232d) may be the same as the width W31of the respective extensions (e.g., first to fourth extensions232a,232b,232cand232d).

In some embodiments, a width W32of each connection (e.g., first to third connections234a,234band234c) may be the same as the width W31of each extension (e.g., first to fourth extensions232a,232b,232cand232d). Here, the width W32refers to a width in a direction (e.g., the first direction Y) that intersects the length direction (e.g., the second direction X) of each connection.

In some embodiments, a width W4of the first redistribution pattern212amay be smaller than the width W31of each extension (e.g., first to fourth extensions232a,232b,232cand232d). The width W4of the first redistribution pattern212amay be, e.g., about 2 μm or less. As an example, the width W4of the first redistribution pattern212amay be about 1 μm to about 2 μm.

In some embodiments, a spaced distance D5between the first redistribution patterns212amay be smaller than the spaced distance D4between the respective extensions (e.g., first to fourth extensions232a,232b,232cand232d). The spaced distance D5between the first redistribution patterns212amay be, e.g., about 2 μm or less. As an example, the spaced distance D5between the first redistribution patterns212amay be about 1 μm to about 2 μm.

The first semiconductor chip310and the second semiconductor chip320may be spaced apart from each other and placed on the upper surface of the interposer200. The first semiconductor chip310and the second semiconductor chip320may be integrated circuits (IC) in which hundreds to millions or more of semiconductor elements are integrated in a single chip, respectively.

In some embodiments, the first semiconductor chip310may be a logic semiconductor chip. For example, the first semiconductor chip310may be an application processor (AP), e.g., a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), a FPGA (Field-Programmable Gate Array), a digital signal processor, an encryption processor, a microprocessor, a microprocessor, and/or an ASIC (Application-Specific IC).

In some embodiments, the second semiconductor chip320may be a memory semiconductor chip. For example, the second semiconductor chip320may be a volatile memory, e.g., a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory), or may be a non-volatile memory, e.g., a flash memory, a PRAM (Phase-change Random Access Memory), a MRAM (Magnetoresistive Random Access Memory), a FeRAM (Ferroelectric Random Access Memory) or a RRAM (Resistive Random Access Memory).

As an example, the first semiconductor chip310may be an ASIC, e.g., a GPU, and the second semiconductor chip320may be a stack memory, e.g., a high bandwidth memory (HBM). Such a stack memory may have a form in which a plurality of ICs are stacked. The stacked ICs may be electrically connected to each other through a TSV (Through Silicon Via) or the like.

In some embodiments, a larger number of second semiconductor chips320may be placed than the first semiconductor chip310. For example, a plurality of second semiconductor chips320may be placed around a single first semiconductor chip310. As an example, as shown inFIG.1, two second semiconductor chips320may be placed on each of two opposite sides of the first semiconductor chip310.

The first semiconductor chip310may include a first chip pad312. The first chip pad312may be used to electrically connect the first semiconductor chip310to other components. For example, the first chip pad312may be exposed from the lower surface of the first semiconductor chip310.

The second semiconductor chip320may include a second chip pad322. The second chip pad322may be used to electrically connect the second semiconductor chip320to other components. For example, the second chip pad322may be exposed from the lower surface of the second semiconductor chip320. For example, the first chip pad312and the second chip pad322may include metallic materials, e.g., copper (Cu) or aluminum (Al), respectively.

The first semiconductor chip310and the second semiconductor chip320may be mounted on the upper surface of the interposer200. In some embodiments, a first chip bump390may be formed between the interposer200and the first semiconductor chip310, and a second chip bump392may be formed between the interposer200and the second semiconductor chip320. The first chip bump390may connect some of the plurality of upper pads270to the first chip pad312. The second chip bump392may connect some other of the plurality of upper pads270to the second chip pad322. The first semiconductor chip310and the second semiconductor chip320may each be electrically connected to the interposer200accordingly.

For example, the first chip bump390and the second chip bump392may be micro bumps including low melting point metals, e.g., tin (Sn) and tin (Sn) alloys. The first chip bump390and the second chip bump392may have various shapes, e.g., a land, a ball, a pin, and a pillar, respectively. The first chip bump390and the second chip bump392may include, e.g., a UBM (Under Bump Metallurgy), respectively. In some embodiments, the first chip bump390and the second chip bump392may be formed at the same level.

In some embodiments, the upper pad270may include a pad layer271, a pad plug272, and a surface treatment layer275. The pad plug272may penetrate a fourth redistribution insulating film210dand connect the fourth redistribution pattern212dand the pad layer271. The surface treatment layer275may be interposed between the pad layer271and the first chip bump390, and between the pad layer271and the second chip bump392. The surface treatment layer275may prevent formation of an intermetallic compound between the pad layer271, the first chip bump390, and the second chip bump392. In some embodiments, the surface treatment layer275may be formed of multiple layers. As an example, the surface treatment layer275may be formed of a double layer of gold (Au)/nickel (Ni).

In some embodiments, the redistribution structure210may electrically connect the first semiconductor chip310and the second semiconductor chip320. For example, a part of the fourth redistribution pattern212dmay connect the upper pad270connected to the first chip bump390and the upper pad270connected to the second chip bump392. The first semiconductor chip310and the second semiconductor chip320may be electrically connected to each other accordingly.

In some embodiments, a second underfill318may be formed between the interposer200and the first semiconductor chip310, and a third underfill328may be formed between the interposer200and the second semiconductor chip320. The second underfill318may fill a space between the interposer200and the first semiconductor chip310, and the third underfill328may fill a space between the interposer200and the second semiconductor chip320. Further, the second underfill318may cover the first chip bump390, and the third underfill328may cover the second chip bump392. The second underfill318and the third underfill328may prevent breakage or the like of the semiconductor chips310and320, by fixing the semiconductor chips310and320onto the interposer200. For example, the second underfill318and the third underfill328may each include an insulating polymeric material, e.g., EMC.

The molding member400may be formed on the upper surface of the interposer200. The molding member400may be formed to cover at least a part of the semiconductor chips310and320. For example, the molding member400may cover the side surfaces of the first semiconductor chip310, the side surfaces of the second semiconductor chip320, the second underfill318, and the third underfill328. Although the molding member400is shown to expose the upper surface of the first semiconductor chip310and the upper surface of the second semiconductor chip320, the molding member400may also cover the upper surface of the first semiconductor chip310and the upper surface of the second semiconductor chip320.

For example, the molding member400may include an insulating polymeric material, e.g., EMC. In some embodiments, the first underfill280, the second underfill318, and the third underfill328may include a substance different from the molding member400. For example, the first underfill280, the second underfill318, and the third underfill328may each include an insulating substance having a fluidity superior to the molding member400. Accordingly, the first underfill280, the second underfill318, and the third underfill328may be efficiently fill the narrow space between the package substrate100and the interposer200, or between the interposer200and the semiconductor the chips310and320.

Referring toFIGS.1to4and5B, in the semiconductor package according to some embodiments, the first lower pad230may include a plurality of first pad patterns230A that are spaced apart, e.g., completely separated, from each other. The plurality of first pad patterns230A may be placed to correspond to the pad regions230S, e.g., in a one-to-one correspondence.

In detail, at least a part of the first pad pattern230A may be placed inside each pad region230S. As described above with reference toFIGS.1to5A, the plurality of first interposer bumps292may be placed to correspond to the pad regions230S. The plurality of first interposer bumps292may be connected to correspond to the first pad patterns230A accordingly.

Referring toFIG.5B, in some embodiments, each first pad pattern230A may include a plurality of extensions (e.g., first to fourth extensions232a,232b,232cand232d) and a plurality of connections (e.g., first to third connections234a,234band234c). For example, as illustrated inFIG.5B, the first pad patterns230A may be spaced apart from each other in two direction, and the plurality of extensions (e.g., first to fourth extensions232a,232b,232cand232d) in each of the first pad patterns230A may be separated from respective extensions (e.g., first to fourth extensions232a,232b,232cand232d) of adjacent ones of the first pad patterns230A. Because the first to fourth extensions232a,232b,232cand232dand the first to third connections234a,234band234care similar to those described above usingFIGS.1to5A, detailed description thereof will not be provided below.

Referring toFIGS.1to4and5C, in the semiconductor package according to some embodiments, the first lower pad230includes a plurality of second pad patterns230B that are spaced apart, e.g., completely separated, from each other. Each second pad pattern230B may be formed in a vortex-shaped bent line shape (e.g., a snake shape).

For example, referring toFIG.5C, each second pad pattern230B may include a plurality of extensions (e.g., first to fourth extensions232a,232b,232cand232d) and a plurality of connections (e.g., first to third connections234a,234band234c). As an example, the first extension232amay be interposed between the second extension232band the third extension232c, and the second extension232bmay be interposed between the first extension232aand the fourth extension232d. At this time, the length of the first to fourth extensions232a,232b,232cand232dextending in the first direction Y may sequentially increase.

In some embodiments, the plurality of second pad patterns230B may be placed to correspond to the pad regions230S, e.g., in a one-to-one correspondence. That is, at least a part of the second pad patterns230B may be placed inside each pad region230S. As described above usingFIGS.1to5A, the plurality of first interposer bumps292may be placed to correspond to the pad regions230S. Therefore, the plurality of first interposer bumps292may be connected to correspond to the second pad patterns230B.

Referring toFIGS.1to4and5D, in the semiconductor package according to some embodiments, the width W1of each second lower pad220is larger than the width W2of each pad region230S. For example, the width W2of each pad region230S may be about 5 μm or less, e.g., about 2 μm to about 5 μm, while the width W1of each second lower pad220may be larger than 5 μm, e.g., about 10 μm to about 30 μm.

In some embodiments, the spaced distance D2between the pad regions230S may be greater than the spaced distance D1between the second lower pads220. For example, the spaced distance D2between the pad regions230S may be about 5 μm or more, e.g., about 10 μm to about 30 μm.

In some embodiments, the distance D3of the pad regions230S spaced apart from the second lower pads220may be smaller than the spaced distance D2between the pad regions230S. Although the distance D3of the pad regions230S spaced apart from the second lower pad220is shown as being greater than the spaced distance D1between the second lower pads220, this is only an example.

FIG.6is another enlarged view of region R1inFIG.2. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5Dwill be only briefly explained or omitted

Referring toFIG.6, in the semiconductor package according to some embodiments, the first lower pad230is connected to the redistribution patterns212ato212d. For example, a part of the first redistribution plug214amay penetrate the pad insulating film202to connect the first lower pad230to the first redistribution pattern212a. Accordingly, the first lower pad230may be electrically connected to the redistribution structure210, and may transmit and receive data signals, ground signals or power signals. In some embodiments, the first lower pad230may be a ground pad that transmits and receives the ground signals.

FIG.7is an exemplary layout diagram of a semiconductor package according to some embodiments.FIGS.8and9are various schematic cross-sectional views taken along line B-B ofFIG.7. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to6will be only briefly explained or omitted.

Referring toFIGS.7and8, in the semiconductor package according to some embodiments, the second semiconductor chip320is stacked on the first semiconductor chip310. The second semiconductor chip320may be placed on the upper surface of the first semiconductor chip310. The second semiconductor chip320may be mounted on the upper surface of the first semiconductor chip310.

For example, a third chip pad314exposed from the upper surface of the second semiconductor chip320may be formed. Further, the second chip bump392may be formed between the first semiconductor chip310and the second semiconductor chip320. The second chip bump392may connect the third chip pad314and the second chip pad322. The first semiconductor chip310and the second semiconductor chip320may be electrically connected to each other accordingly.

In some embodiments, the second semiconductor chip320may include a chip through via315. The chip through via315may penetrate a base substrate (e.g., a semiconductor substrate) of the second semiconductor chip320to electrically connect the first chip pad312and the third chip pad314. The first semiconductor chip310may be electrically connected to the interposer200accordingly.

In some embodiments, the interposer200may include an interposer through via250. The interposer through via250may penetrate the redistribution structure210to electrically connect the second lower pad220and the upper pad270. The interposer200may be electrically connected to the first semiconductor chip310and/or the second semiconductor chip320accordingly.

Referring toFIGS.7and9, in the semiconductor package according to some embodiments, at least some of the plurality of interposer through vias250are connected to the first lower pad230. For example, some of the plurality of interposer through vias250may penetrate the redistribution structure210to electrically connect the second lower pad220and the upper pad270. Some other of the plurality of interposer through vias250may penetrate the redistribution structure210to electrically connect the first lower pad230and the upper pad270.

Hereinafter, a method for fabricating a semiconductor package according to an exemplary embodiment will be described referring toFIGS.10to23.FIGS.10to23illustrate cross-sectional views of stages in the method for fabricating the semiconductor package according to some embodiments.FIGS.11-19are enlarged views of region R1inFIG.10, andFIGS.21-23are enlarged views of region R1inFIG.20. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to9will be only briefly explained or omitted.

Referring toFIGS.10-11, a carrier substrate500may be provided. For example, the carrier substrate500may be a pre-preg including, e.g., glass or insulating resin, an inorganic filler, and a glass fiber. The carrier substrate500may be a glass carrier or a normal detach core.

Referring toFIG.12, a passivation film260, a first seed film225L, and a first sacrificial film220P may be sequentially formed on the carrier substrate500.

For example, the passivation film260may include a thermosetting resin, e.g., an epoxy resin, a thermoplastic resin, e.g., polyimide, or a photosensitive insulating material, e.g., a PID.

The first seed film225L may function as a seed for formation of first metal patterns222and232to be described below. In some embodiments, the first seed film225L may be formed of multiple layers. As an example, the first seed film225L may be formed of a double layer of titanium (Ti)/copper (Cu).

The first sacrificial film220P may include, e.g., a photoresist layer or a dry film.

Referring toFIG.13, the first sacrificial film220P may be patterned to form first sacrificial patterns220PP. For example, a photolithography process of patterning the first sacrificial film220P may be performed. The first sacrificial patterns220PP that expose a part of the upper surface of the first seed film225L may be formed accordingly.

Referring toFIG.14, first metal patterns222and232may be formed. For example, an electroplating process which uses the first seed film225L exposed by the first sacrificial patterns220PP as a seed may be performed. The first metal patterns222and232that fill the region between the first sacrificial patterns220PP may be formed accordingly. After the first metal patterns222and232are formed, the first sacrificial film220P may be removed.

The first metal patterns222and232may include a conductive material, e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. Preferably, the first metal patterns222and232may include copper (Cu).

In some embodiments, the first seed film225L may be patterned to form the first seed patterns224and234. For example, an etching process which uses the first metal patterns222and232as an etching mask may be performed. Accordingly, the first lower pad230and the second lower pad220each including the first seed patterns224and234and the first metal patterns222and232may be formed.

Referring toFIG.15, the pad insulating film202and a second sacrificial film212P may be formed on the passivation film260, the first lower pad230, and the second lower pad220.

The pad insulating film202may cover the passivation film260, the first lower pad230, and the second lower pad220. The pad insulating film202may expose a part of the second lower pad220. For example, the pad insulating film202may include a trench that exposes a part of the upper surface of the second lower pad220. In some embodiments, the pad insulating film202may not expose the first lower pad230.

The second sacrificial film212P may cover the pad insulating film202. Further, the second sacrificial film212P may fill the trench of the pad insulating film202. The second sacrificial film212P may include, e.g., a photoresist layer or a dry film.

In some embodiments, a second seed film which covers the pad insulating film202may be formed before the second sacrificial film212P is formed. The second seed film may function as a seed for forming the first redistribution pattern212ato be described later.

Referring toFIG.16, the second sacrificial film212P is patterned to form the second sacrificial patterns212PP. A photolithography process of patterning the second sacrificial film212P may be performed. Accordingly, the second sacrificial pattern212PP that exposes a part of the upper surface of the pad insulating film202(or a part of the upper surface of the second seed film) may be formed.

Referring toFIG.17, the first redistribution pattern212aand the first redistribution plug214aare formed. For example, an electroplating process which uses the second seed film exposed by the second sacrificial patterns212PP as a seed may be performed. Accordingly, the first redistribution pattern212athat fills the region between the second sacrificial patterns212PP may be formed. Also, the first redistribution plug214athat fills the trench of the pad insulating film202may be formed.

Referring toFIG.18, the redistribution structure210and the upper pad270are formed.

For example, the first redistribution insulating film210athat covers the first redistribution pattern212amay be formed. The first redistribution pattern212a, the first redistribution plug214a, and the first redistribution insulating film210amay form the first redistribution layer. Subsequently, a plurality of redistribution layers (e.g., second to fourth redistribution layers) may be formed on the first redistribution layer. Because formation of each of the second to fourth redistribution layers is similar to formation of the first redistribution layer (e.g., redistribution insulating films210ato210d), detailed description thereof will not be provided below.

Subsequently, the upper pad270may be exposed from the upper surface of the redistribution structure210(e.g., the fourth redistribution insulating film210d). In some embodiments, the upper pad270may include the pad plug272, the pad layer271, and the surface treatment layer275. The interposer200that includes the redistribution structure210, the first lower pad230, the second lower pad220, and the upper pad270may be formed accordingly.

Referring toFIG.19, the first semiconductor chip310and the second semiconductor chip320may be formed on the interposer200. The first semiconductor chip310and the second semiconductor chip320may be mounted on an upper surface of the interposer200.

For example, the first chip bump390which connects some of the plurality of upper pads270and the first chip pad312may be formed, and the second chip bump392which connects some others of the plurality of upper pads270and the second chip pad322may be formed. The first chip bump390and the second chip bump392may each be micro bumps that include low melting point metals, e.g., tin (Sn) and tin (Sn) alloys.

Referring toFIGS.20and21, the carrier substrate500is removed. The carrier substrate500may be separated from the passivation film260. A lower surface of the passivation film260may be exposed accordingly.

Referring toFIG.22, at least a part of the first lower pad230and/or at least a part of the second lower pad220is exposed. For example, the opening265that exposes at least a part of the first lower pad230and/or at least a part of the second lower pad220is formed inside the passivation film260. At least a part of the lower surface of the first lower pad230and/or at least a part of the lower surface of the second lower pad220may be exposed through the opening265.

Referring toFIG.23, the first interposer bump292and the second interposer bump290are formed. For example, through the opening265, the first interposer bump292may be connected to the first lower pad230, and the second interposer bump290may be connected to the second lower pad220. The first interposer bump292and the second interposer bump290may each be, but are not limited to, solder bumps including low melting point metals, e.g., tin (Sn) and tin (Sn) alloys.

Subsequently, referring toFIGS.2and3, the interposer200is stacked on the package substrate100. The interposer200may be mounted on the upper side of the package substrate100. For example, the first interposer bump292may connect some of the plurality of second substrate pads104to the first lower pad230, and the second interposer bump290may connect some others of the plurality of second substrate pads104to the second lower pad220. The package substrate100and the interposer200may be electrically connected accordingly.

In general, as semiconductor chips gradually become highly integrated, an interposer having a redistribution layer with a fine pattern is required for signal transmission between the semiconductor chips. However, a redistribution layer with a fine pattern may be damaged during manufacturing, e.g., due to warpage or steps, thereby causing low yield.

For example, if the first lower pads were to be formed without interconnected extensions that are spaced apart from each other, the larger spaced distance D2between such first lower pads (functioning as dummy pads or ground pads) relative to the spaced distance D1between second lower pads, would have reduced the flatness of the subsequent process to cause defects. That is, the pad insulating film that fills the gap between the first lower pads would have included undulations between adjacent first lower pads due to the relatively larger distance D2. Such undulation202CS would have reduced the flatness of the second sacrificial film formed on the pad insulating film, which in turn, would have caused a defect of the first redistribution pattern formed by the use of the second sacrificial film, e.g., delamination or lift of the first redistribution pattern which is a fine pattern.

Further, in another example, if the width W2of the first lower pad230were to be formed to be greater than the width W1of the second lower pad, the relatively larger width W2of the first lower pad would have also reduced the flatness of the subsequent process to cause defects. That is, the pad insulating film that covers the upper surface of the first lower pad would have included additional undulations due to the relatively large width W2. The additional undulations would have reduced the flatness of the second sacrificial film formed on the pad insulating film, which in turn, would have caused a defect of the first redistribution pattern formed by the use of the second sacrificial film, e.g., delamination or lift of the first redistribution pattern which is a fine pattern.

In contrast, the first lower pad230of the semiconductor package according to example embodiments is formed to have a plurality of interconnected extensions spaced apart from each other (e.g., first to fourth extensions232a,232b,232cand232d), thereby improving the flatness of the subsequent process. That is, as described above usingFIGS.1to5D, the first lower pad230, e.g., only the first lower pad230among the first and second lower pads220and230, may be formed at a relatively small width (e.g., W31) and distance (e.g., D4). Accordingly, it is possible to provide a semiconductor package and a method for fabricating the same, in which the flatness of the subsequent process is improved, e.g., due to the plurality of spaced extensions, and the yield is improved.

On the other hand, a pad formed with a relatively small width may also be vulnerable to twisting, steps, or the like. However, since the first lower pad230of the semiconductor package according to example embodiments is formed in a bent line shape (e.g., a snake shape) from a planar viewpoint, it is possible to prevent a lift from the passivation film260. Specifically, as described above usingFIGS.1to5D, the first lower pad230may include a plurality of extensions (for example, first to fourth extensions232a,232b,232cand232d) and a plurality of connections (e.g., first to third connections234a,234band234c). Accordingly, even though the first lower pad230is formed with a relatively small width (e.g., W31), by improving the contact area with the passivation film260, the degree of adhesion with the passivation film260may be improved.

By way of summation and review, as semiconductor chips gradually become highly integrated, an interposer having a redistribution layer with a fine pattern may be required for signal transmission between the semiconductor chips. However, the redistribution layer of the fine pattern may be vulnerable to warpage or steps and a low yield.

In contrast, aspects of embodiments provide a semiconductor package having an improved yield. Aspects of embodiments also provide a method for fabricating a semiconductor package having an improved yield.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.