Patent ID: 12219841

Use of the same reference numbers in different figures indicate similar or identical elements.

While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

In this description, the term “device” and “microdevice” are used interchangeably. However, it is clear to one skilled in the art that the embodiments described here are independent of the device size.

In this description, the term “system substrate”, “receiver substrate” and “backplane” are used interchangeably. However, it is clear to one skilled in the art that the embodiments described here are independent of the substrate type.

According to one embodiment, one or more stages may be created after the transfer of a first microdevice to a system (temporary) substrate for the subsequent microdevice transfer to the first (or the second) microdevice transfer. The stage improves the surface profile of the system (temporary) substrate so that next microdevice can be transferred without the first microdevice on the substrate get damaged by or interfere with the surface of the donor or transfer head.

According to another embodiment, the stage can be a planarization layer that is formed on the substrate after the transfer of the first microdevice. In one case, the stage is a pillar that is formed on the substrate. In another case, the stage is a pillar that is formed on the microdevice surface.

According to one embodiment, the stage can be a combination of the abovementioned methods.

According to another embodiment, the stage can be conductive and can connect the microdevice to a signal. In one case, vias can be opened through the stage to couple the microdevice to a signal. In another case, pads can be formed in the vias for connections.

According to one embodiment, the first microdevice can be a part of the stage.

According to another embodiment, a conductive layer can connect the common electrode to first and second (or other stacked) microdevices. In one case, the conductive layer is part of the stage.

According to one embodiment, the second microdevice may have a slight overlap with the first device, but not completely cover the device. After the second electrode is deposited and etched, a bonding layer may be added to the electrode and then the second device is integrated. This process may be repeated for all further device integrations.

In one embodiment, a reflective layer may be added to the individual devices in these embodiments or a complete set of devices for each pixel. The conductive electrode may be used as a reflective layer as well.

In another embodiment, the top electrode may have two parts: a reflective part at a vertical side and a transparent electrode at the top side.

In one embodiment, one electrode is connected to two different microdevice contacts. Here, switches are used to couple the electrode to different signals depending on the function of different microdevices.

In one case, the staging pads profile in all structures mentioned herein may be either higher or lower than the system substrate surface. In another case, the staging pads profile may be made of a few different layers. In one embodiment, the staging pads may be higher than the system substrate surface to offer more selectivity.

In one embodiment, the staging pads may be conductive and create electrical connection between the system substrate and microdevices.

In another embodiment, one or more planarization layers may be formed to level the system substrate surface. In one case, an opening through the planarization layer(s) may be provided to create contact between the microdevices and system substrate. In another case, the staging pads and the planarization layer may be the same. In another case, the staging pads may be formed separately.

In one case, the microdevices may have more than one connection at each side.

In one embodiment, a backplane may be formed on top, bottom or in between the planarization layer.

In another embodiment, a buffer layer or a release layer may be formed before the microdevices on the system substrate. The buffer layer and the release layer may be the same or different layers.

In another case, a bonding layer may be added to the electrode and the microdevices.

In one embodiment, a reflective layer may be added to individual devices. In one case, the conductive electrode may be used as a reflective layer as well. In this case, the top electrode may have two parts: a reflective part at a vertical side and a transparent electrode at the top side.

In another embodiment, where the devices are sharing an electrode, the devices may be driven in a combination method.

In one embodiment, pixel structures with shared electrodes between different microdevices may be provided.

In another embodiment, programmable switches may be provided to change the pixel configuration.

In one embodiment, one may perform time multiplexing. Here, the driver is shared between the devices and may be allocated to each device for a given time during the frame time.

Various embodiments in accordance with the present structures and processes provided are described below in detail.

Many microdevices, including light emitting diodes (LEDs), organic LEDs, sensors, solid state devices, integrated circuits, microelectromechanical systems (MEMS) and other electronic components, are typically fabricated in batches, often on planar substrates. To form an operational system, microdevices from at least one donor substrate need to be transferred to a receiver substrate.

With reference toFIG.1A, a block diagram of an example of transferring and integrating a plurality of microdevices into a system substrate is provided. In one embodiment, one or more microdevices may be fabricated on a donor substrate. The one or more microdevices may be transferred and integrated to a system substrate or a temporary substrate. The microdevices may be transferred from different donor substrates. The block diagram100may include one or more donor substrates (104,106) with one or more microdevices fabricated on them. There may be a plurality of donor substrates. A transfer mechanism108may be applied to transfer one or more microdevices from the one or more donor substrates to landing areas on a system substrate110.

FIG.1Billustrates an example method of processing steps for integrating multi devices into the system substrate. In the first step110, at least one microdevice can be transferred into the system substrate. At step120, after the first microdevice is transferred, a stage is formed at the system substrate for at least one second microdevice, wherein a top of second microdevice is higher than a top of the first microdevice. The stage can also have adhesive property to assist in the transfer of the microdevice. In another case, extra bonding layer may form on top of the stage. Further at step114, the at least one second microdevice is transferred onto the stage and the substrate surface is planarized at step116. In some cases, the planarization layer can be eliminated, and at step118, the post processing steps can be performed. The post processing can include, electrode deposition, forming vias/opening for accessing the microdevices, optical layers deposition and etc.

FIG.1Cillustrates an example method of processing steps for integrating multi devices into the system substrate. In the first step110-1, at least one microdevice can be transferred into the system substrate. At step120-1, after the first microdevice is transferred, a stage is formed at the system substrate for at least one second microdevice, wherein the stage is taller than or equal to a distance from the surface of the substrate where the second microdevice will land to the top of the first microdevice. The stage can also have adhesive property to assist in the transfer of the microdevice. In another case, extra bonding layer may form on top of the stage. Further at step114-1, the at least one second microdevice is transferred onto the stage and the substrate surface is planarized at step116-1. In some cases, the planarization layer can be eliminated, and at step118-1, the post processing steps can be performed. The post processing can include, electrode deposition, forming vias/opening for accessing the microdevices, optical layers deposition and etc.

FIG.2Ashows a system substrate with a first integrated microdevice, in accordance with an embodiment of the invention. Here, a system or temporary substrate200can be provided with landing area (or landing surface) (202,206) formed on a surface of the system substrate200. There can be pads as part of the landing area (202,206) for microdevices. The pads can be only for assisting in the transfer (e.g. bonding layer or adhesion layers) or can be coupling the microdevice to a signal. A first microdevice204is transferred from a donor substrate and integrated to a corresponding landing area202on the system substrate200.

In one embodiment, a stage can be formed on the system substrate surface where the second micro device will be transferred (landing area) for enabling integration of the second microdevices and improving the surface profile of receiver substrate. The stage can be on top of a pad or directly on another surface. The height of the stage is equal or higher than the combined height of the first microdevice plus the first landing area minus the height of the landing area of the second microdevice.

In one case, the staging pads may be deposited and etched on the substrate. In another case, the staging pad is transferred, printed, or deposited on the substrate.

FIG.2B-1shows a system substrate with integrated first microdevice and stage for enabling integration of a second microdevice, in accordance with an embodiment of the invention. Here, a stage207may be provided to facilitate the integration of the second microdevice. The stage207may be formed on a top surface of the corresponding landing area206where the second microdevice will be transferred next. The stage207is used to ready the system substrate surface for the second microdevice integration. Here, after a first microdevice204is integrated into the system substrate, the location of the second (or more) microdevice integration may be raised by adding stages/staging pads that facilitate the integration of second and other microdevices. This process may continue for several other microdevice series integration. The stage207can be on top of a pad or directly on another surface. The height of the stage250is equal or higher than the combined height252of the first microdevice204plus the first landing area202minus the height of the landing area206of the second microdevice208.

In one embodiment, a stage can be formed on the temporary substrate before transferring the second microdevice the system substrate.

FIG.2B-2shows a donor substrate with integrated microdevices and stage pad for enabling integration of second microdevice, in accordance with an embodiment of the invention. Here, the donor substrate100may be provided with the stage207formed on the microdevice(s)208before getting transferred to the system substrate. In one case, one or more staging pads may be used for each microdevice. In another case, the staging pads may only be added to the device areas that are being integrated next.

In one embodiment, a microdevice donor substrate with at least one stage microdevice may be ready for being integrated into system substrate which include at least one another microdevice.

FIG.2Cshows integration of at least one another microdevice with stage on the receiver substrate, in accordance with an embodiment of the invention. Here, the second microdevice208with stage207on the donor substrate may be transferred to the corresponding landing area206on the system substrate200which include at least one another microdevice. The stage207may be conductive and create an electrical connection between the system substrate200and the second microdevice207. The stage may be transferred to the system substrate by any means described in this disclosure or other methods, or it may be deposited or etched.

In case more than two devices are integrated into the system substrate, the second staging pad may be transferred into the second and third device areas. Then, after the integration of the second device, another staging pad is transferred into the position where a third device may be integrated. This process may also be followed for more than three devices.

In one embodiment, the staging pads may be higher than the system substrate surface to offer more selectivity when transferring. After all devices are transferred, the surface may be leveled using a planarization layer. If a common electrode is needed, an opening need to be created in the planarization layer to deposit the common electrode.

In one case, the staging pads and the planarization layer may be the same. In another case, the staging pads may be formed separately.

FIG.3A-3Cshows a system (or temporary) substrate where the microdevice different from the first microdevice is transferred on a different level from the first microdevice, in accordance with an embodiment of the invention. With reference toFIGS.3A-3C, a staggered structure may be provided to integrate the microdevices to the system substrate.FIG.3Ashows a system (or temporary) substrate where a second microdevice different from the first microdevice is transferred on a level different from the first microdevice. The system substrate includes the integration of a first microdevice304and a second microdevice308as discussed above (inFIGS.2B-1and2C). A first microdevice304is transferred to a corresponding landing area302on the system substrate. A second microdevice308may be transferred on a different level from the first microdevice304. After the integration of the first microdevice304, the surface of the system substrate is leveled with a planarization layer305. Then, an opening320may be made through the planarization layer305to create a connection between the second microdevice308and the system substrate300. An electrode307may be provided to the second microdevice308to make a connection with the system substrate200.

FIG.3Bshows that a system (or temporary) substrate300, wherein the second microdevice different from the first microdevice304is transferred on a different level from the first microdevice304. After the integration of the first microdevice304, the surface of the system substrate is leveled with a planarization layer305. Then, an opening320may be made through the planarization layer305to create a connection between the second microdevice308and the system substrate300. An electrode307may be provided to the second microdevice308to make a connection with the system substrate200which can be a common electrode for the first microdevice too.

FIG.3Cshows a system (or temporary) substrate where there are two microdevices (304,308) sharing a common electrode307. The planarization layer305may be extended to a surface of the second microdevice308. There can be another electrode312for the second microdevice308through a second opening in the planarization layer305.

FIG.4shows stacked microdevices with staging pads while at least one electrode and pad is shared, in accordance with an embodiment of the invention. Here, a temporary substrate/cartridge substrate300may be provided. A buffer layer/release layer316may be deposited on the cartridge substrate300to facilitate release of microdevices. The buffer layer316may be formed before the microdevices. The release layer may be a separate layer formed on top of the substrate. The release layer may be the same as the buffer layer. Here, two microdevices304and308may be provided. The two microdevices may share at least one common electrode307and a common staging pad312. A separate stage314may be provided for the first microdevice304on a landing area302and a separate stage310may be provided for the second microdevice308.

FIG.5shows a top view of stacked microdevices as shown inFIG.4, in accordance with an embodiment of the invention. Here, a microdevice304is having a staging pad shared staging pad312. A planarization layer305may be deposited covering the microdevice and the staging pad. A buffer layer/release layer316may be deposited on the cartridge substrate to facilitate release of microdevices. A separate staging pad314may be provided for the first microdevice304.

FIG.6shows stacked microdevices with pads with separate electrode and pad for each device. Here, a cartridge substrate300is provided. A buffer layer/release layer316may be deposited on the cartridge substrate300to facilitate the release of microdevices. Here, two microdevices304and308may be provided. The two microdevices may be stacked together with separate electrodes and staging pads. Here, the first microdevice304may be provided with an electrode302and stages (314and312-B). The second microdevice308may be provided with another electrode307and stages (310and312-A).

FIG.7shows stacked microdevices with pads on a system substrate, in accordance with an embodiment of the invention. Here, a stack of a plurality of microdevices with staging pads on a system substrate may be provided. Here, for example, three microdevices702,704and706are provided. A first microdevice702may be integrated to the system substrate700. In one case, there can be a staging pad for the first microdevice702for integration to the system substrate. In another case, the first microdevice702may be integrated directly to the system substrate. For the integration of a second microdevice. E.g.,704, a staging pad704-2may be provided to facilitate the integration of the second microdevice704to the system substrate. The staging pad704-2is used to ready the system substrate surface for the second microdevice704integration.

In one embodiment, after the integration of the first microdevice702into the system substrate, the location of integration for the second (or subsequent) microdevices, may be raised by adding staging pads that facilitate the integration of second and other microdevices. This process may continue for several other microdevice series integration. For example, a third microdevice706may be integrated to the system substrate with a raised staging pad706-2.

In one embodiment, the staging pads may be conductive for connecting the microdevices to a signal. In another embodiment, a planarization layer705may be formed on and over the microdevices and staging pads. Vias (712,714,716) may be made through the planarization layer705for providing electrode (720,724,726) to each microdevice for connecting the microdevices to the signal. In one case, the microdevices may have more than one connection at each side. In this case, more than one via may be needed for each microdevice. The stage can be the same as planarization layer (after each device a planarization layer can be deposited).

In another embodiment, a backplane may be formed on top of the planarization layer. In one case, the backplane may be at the bottom or in between the planarization layer.

In one embodiment, a buffer layer may be formed before the microdevices are formed or transferred. In one case, a release layer may be formed on top of the substrate. The release layer and the buffer layer may be the same or different layer.

FIG.8A-8Eshows different arrangements of placing the microdevices with stages, in accordance with an embodiment of the invention. Here, a system (or temporary) substrate where the microdevice different from the first microdevice is transferred on a different level from the first microdevice in different arrangements may be provided.

With reference toFIG.8A, here, microdevices overlapped and connected through a common electrode. In one case, microdevices (802,804and806) can have overlap (stage can be used to support the other side of the device). The overlap can be used to connect the common electrode820. In one case, the common electrode820can be connected to both bottom and top side of the device. Stacking microdevices on top of each other enables the connection between the microdevices. Each microdevice can have one or more other connection as well. A first microdevice802may be transferred into the substrate800. A second microdevice804different from the first microdevice802may be transferred to the substrate at a different level from the first microdevice. A planarization layer805may be formed on the substrate after the transfer of the first microdevice. A stage can be planarization layer805. The stage is conductive and can connect the microdevices to a signal. Further, a via/opening is opened through the stage to couple the microdevice to a signal. An electrode814for first microdevice may be provided through the opening. A common connection810may be provided between the first microdevice802and the second microdevice804. This process may continue for the third and more device series integration. After integration of second microdevice, another stage is transferred. A third microdevice806may be transferred to substrate. The second and third microdevices may share a connection812. A common electrode820may be provided for all the transferred microdevices.

FIG.8Bshows a top view ofFIG.8A, in accordance with an embodiment of the invention. Here, microdevices overlapped and connected through a common electrode. In one case, the microdevices (802,804and806) can have overlap (stage can be used to support the other side of the device). The overlap can be used to connect the common electrode820. In one case, the common electrode820can be connected to both bottom and top side of the device. Stacking microdevices on top of each other enables the connection between the microdevices. Each microdevice can have one or more other connection as well e.g, the first microdevice802may be provided with an electrode/contact822-1, the second microdevice may be provided with an electrode/contact822-2and the third microdevice806may be provided with an electrode/contact822.

FIG.8Cshows different arrangements of placing the microdevices with stages, in accordance with an embodiment of the invention. Here, the microdevices802,804and806may be provided. Each microdevice may be provided with a corresponding electrode and a contact to make a connection with the system substrate. For example, the microdevice806may be provided with an individual electrode822and a contact828-3. Further, a common electrode820may be formed on the provide connections to microdevices.

FIG.8Dshows different arrangements of placing the microdevices with stages, in accordance with an embodiment of the invention. Here, the three microdevices802,804and806may be provided. The microdevices may be provided with common connections. There may be a common connection810-1between the first microdevice802and the second microdevice804and a common connection810-2between the second microdevice804and a third microdevice806. In one case, each microdevice may be provided with a corresponding electrode to make a connection with the system substrate800. In another case, there may be common electrode820-1between the microdevices. Further, a planarization layer805may be formed on the substrate after the transfer of the first microdevice. A stage can be planarization layer805. The stage is conductive and can connect the microdevices to a signal.

FIG.8Eshows a top view ofFIG.8D, in accordance with an embodiment of the invention. Here, microdevices are connected through a common electrode. In one case, the common electrode820can be connected to both bottom and top side of the device. Stacking microdevices on top of each other enables the connection between the microdevices. Each microdevice can have one or more other connection as well e.g, the first microdevice802may be provided with an electrode822-3and a contact822-4.

According to one embodiment, a solid state array device may be provided. The solid state array device may comprising one or more pixel circuits, each pixel circuit has two or more microdevices and at least one of the two microdevices coupled to one pixel circuit and each microdevice is coupled to a bias voltage through a switch.

According to another embodiment, the one of the microdevices is decoupled from the shared pixel circuits from the switch and coupled to the bias voltage which turns off the microdevice.

FIG.9shows a pixel structure with shared electrodes between different microdevices.FIG.9A-9Bshow a driving scheme for microdevices, according to one embodiment of the present invention. Here, the embodiment shows a combination driving method of the devices with a shared electrode. Three microdevices912,916, and920may be provided with corresponding pixel circuits910,914, and918. In a case where the devices are sharing an electrode, one may drive the devices in a combination method.FIGS.9A-9Bshows an embodiment of such a driving scheme. InFIG.9A, a voltage source VBmay be applied to each microdevice. I1defines the driving force of first device912, I1+I2defines the driving force of second device916and, I1+I2+I3defines the driving force of third device920. This daisy chain may be extended to more devices as well.FIG.9Bshows an alternate arrangement for microdevices912,916, and920, where I3defines the driving force of third device918, I2+I3defines the driving force of second device916and, I1+I2+I3defines the driving force of third device912. This daisy chain may be extended to more devices as well. In one case, each of the voltage sources may be replaced with a current source.

FIGS.10A-10Eshow a time multiplexing driving scheme, according to one embodiment of the present invention. In one case, time multiplexing may be provided between the devices. Here, the driver is shared between the devices and may be allocated to each device for a given time during a frame time.

FIGS.10A and10Bshow exemplary pixel structures with shared electrodes between different microdevices and switches to change the pixel configuration. With reference toFIGS.10A and10B, three microdevices1012,1016and1020may be provided with corresponding pixel circuits1010,1014, and1018. There may be provided a switch configuration1022,1032,1034,1042,1044to each device to either connect the device to a pixel circuit1010,1014,1018or to a bias voltage VB1, VB2, VB3. For example, switch1022is provided to device1012, a voltage source VB2coupled to switches1032,1034is provided to device1016, and a voltage source VB3is coupled to switches1042,1044and may be provided to device1020.

In another embodiment, the pixel circuit1010,1014, and1018can be one pixel circuit and shared between the devices1012,1016and1020and may be allocated to each device1012,1016and1020for a given time during a frame time.

FIG.10Cshows an example of switch operation during different operation periods. Each device is connected to a pixel circuit and is in operation mode during at least a subframe of the frame time. During the operation mode, the switch connecting the device to the pixel circuit is ON and the switch biasing the other side of the device to a bias voltage is OFF. During other times in the frame, the device is not connected to the pixel circuit and unoperational. For unoperational mode, the device can be disconnected from the pixel circuit and both sides are either connected to a bias voltage or to at least one side is floating. The bias voltages are set to make sure the device is off.

Referring toFIG.10C, during the first sub frame, the switches1022,1034,1044are ON and other switches1032,1042are OFF. As a result, device1012is coupled to the pixel circuit1010and other devices1016,1020are uncoupled from the pixel circuits1014,1018. Therefore, the device1012is operational and controlled by the pixel circuit1010and other devices1016,1020are unoperational.

Referring toFIG.10C, during the second sub frame, the switches1032,1044are ON and other switches1022,1034,1042are OFF. As a result, device1016is coupled to the pixel circuit1014and other devices1012,1020are uncoupled from the pixel circuits1010,1018. Therefore, the device1016is operational and controlled by the pixel circuit1014and other devices1012,1020are unoperational.

Referring toFIG.10C, during the third sub frame, the switches1042,1034are ON and other switches1022,1044,1032are OFF. As a result, device1020is coupled to the pixel circuit1018and other devices1012,1016are uncoupled from the pixel circuits1010,1018. Therefore, the device1020is operational and controlled by the pixel circuit1018and other devices1012,1016are unoperational.

Referring toFIG.10D, the ON time of each device is extended and at least two devices are operational during one sub frame. During the first and third sub frame, devices1012and1020are operational and controlled by pixel circuit1010,1018and device1016is unoperational. During the second and fourth subframe, device1016is coupled to1020and other devices1012,1020are unoperational. One can combine the first and third subframes and combine the second and the fourth subframes.

FIG.10Eshows another embodiment which performs similar toFIGS.10A and10B. However, the two-pixel circuits1010,1014are connected to the same point shared between two devices1012and1016. Here, one can merge the two circuits1010,1014and can eliminate the switches1022,1032. The operation of this pixel and device arrangement can be similar to that ofFIGS.10C, and10D.

FIGS.11A-11Bshow other embodiments where more than two microdevices share the same contact/electrode, according to one embodiment of the present invention. With reference toFIGS.11A and11B, three microdevices1112,1116,1120may be provided with corresponding pixel circuits1110,1118,1114. There may be provided a switch configuration1142,1144,1132,1122to either connect the device1112,1116,1120to pixel circuits1110,1118,1114, or to a bias voltage VB3, VB2, VB4, VB5. For example, switch1142is provided to device1120and pixel circuit1118, a voltage VB3is coupled to switch1144, switch1132is provided to device1116and pixel circuit1114, a voltage source VB2is coupled to switch1134, and switch1122is provided to device1112and pixel circuit1110. Here, the two-pixel circuits1118,1114are connected to the same point shared between two devices1118and1116.

In some embodiments, the pixel circuit can be one-pixel circuit and shared between the devices and may be allocated to each device for a given time during a frame time.

With reference toFIGS.12A and12B, a pixel structure shared between different microdevices may be provided. In these embodiments, three micro devices1212,1216, and1220share a common pixel1210. There may be provided a switch configuration1222,1232,1234,1242,1244to either connect the devices1212,1216,1220to the common pixel circuit1210or to a bias voltage VB3, VB2. Here, the common pixel circuit1210may be allocated to each microdevice for a given time during a frame time.

With reference toFIGS.13A and13B, a pixel structure shared between different microdevices may be provided. In these embodiments, three micro devices1312,1316, and1320may share a common pixel circuit1310. There may be provided a switch configuration1322,1332,1334to connect the devices1312,1316, and1320to the common pixel circuit1310and to a bias voltage VB1, VB3, VB2. Here, the common pixel circuit1310may be allocated to each microdevice for a given time during a frame time.

With reference toFIGS.14A and14B, a pixel structure shared between different microdevices may be provided. In these embodiments, three micro devices1412,1416, and1420share a common pixel circuit1410. There may be provided a switch configuration1422,1432,1434connected between the common pixel circuit1410and the devices1412,1416, and1420connected to a bias voltage VB1, VB3, VB2.

With reference toFIG.15A, a pixel diagram with shared drive and separated storage element for different microdevices may be provided. With reference toFIG.15A, three storage element1510-B1,1510-B2and1510-B3may be provided with a common pixel element1510-A. There may be provided a switch configuration1550,1560and1570to each storage element to either connect with common pixel element1510-A or to a common bias voltage VBC through another switch1580. There may be provided another switch configuration1572,1574,1562,1564,1552,1554to connect storage elements1510-B1,1510-B2and1510-B3with individual bias voltage VB4, VB5and VB6. The common pixel drive element1510-A may be connected to microdevices1512,1516,1520which are connected to corresponding bias voltages VB1, VB2and VB3.

With reference toFIG.15B, the switching configuration during different operation periods may be provided. Each storage element is connected to a common pixel driver and is in operation mode during at least a subframe of the frame time. During operation mode, the switch connecting the storage element to the pixel driver element is ON and the switch biasing the other side of the storage element to a bias voltage is ON. During other times in the frame, the storage element is not connected to the pixel driver element and is unoperational. For unoperational mode, the storage element can be disconnected from the pixel driver element and both sides are either connected to a bias voltage or at least one side is floating. The bias voltages are set to make sure the storage element is OFF.

InFIG.15B, during the first subframe, the switches1570,1560,1550,1574,1564,1580and1554are ON, whereas the switches1572,1562, and1552, are OFF. As a result, all the storage elements1510-B1,1510-B2and1510-B3are operational. During the second subframe ofFIG.15B, the switches1580,1560,1550,1574,1562,1564,1552and1554are OFF, whereas the switches1570and1572are ON. As a result, only the first storage element1510-B1is in operation and coupled to pixel driver element, whereas other storage elements1510-B2and1510-B3are uncoupled from pixel driver elements and are unoperational.

During the third subframe ofFIG.15B, the switches1580,1570,1550,1574,1572,1564,1552and1554are OFF, whereas the switches1560and1562are ON. As a result, only the second storage element1510-B2is in operation and coupled to pixel driver element1510-A, whereas other storage elements1510-B1and1510-B3are uncoupled from pixel driver elements and are unoperational.

During the fourth subframe ofFIG.15B, the switches1580,1570,1560,1574,1572,1564,1562and1554are OFF, whereas the switches1550and1552are ON. As a result, only the third storage element1510-B3is in operation and coupled to pixel driver element1510-A, whereas other storage elements1510-B1and1510-B2are uncoupled from pixel driver elements and are unoperational.

Subframes two to four (FIG.15B) can be repeated during different operation periods so that different switches are ON for each subframe, and therefore storage elements are in operation during each subframe.

With reference toFIG.16A, a pixel diagram with shared drive and separated storage element for different microdevices may be provided. With reference toFIG.16A, three storage element1610-B1,1610-B2and1610-B3may be provided with a common pixel element1610-A. There may be provided a switch configuration1680to either connect each storage element1610-B1,1610-B2and1610-B3to with common pixel element1610-A or to a common bias voltage VBC. The storage element may comprise capacitors. There may be provided another switch configuration1672,1674,1662,1664,1652,1654to connect storage elements1610-B1,1610-B2and1610-B3with individual bias voltage VB4, VB5and VB6. The common pixel drive element1610-A may be connected to microdevices1612,1616,1620which are connected to corresponding bias voltages VB1, VB2and VB3.

InFIG.16B, during the first subframe, the switches1680,1674,1664, and1654ON, whereas the switches1672,1662, and1652, are OFF. As a result, all the storage elements1610-B1,1610-B2and1610-B3are operational. During the second subframe ofFIG.16B, the switches1680,1674,1664,1654,1662and1652are OFF, whereas the switch1672is ON. As a result, only the first storage element1610-B1is in operation and coupled to pixel driver element, whereas other storage elements1610-B2and1610-B3are uncoupled from pixel driver elements and are unoperational.

During the third subframe ofFIG.16B, the switches1680,1674,1664,1654,1672,1652are OFF, whereas the switch1662is ON. As a result, only the second storage element1610-B2is in operation and coupled to pixel driver element1610-A, whereas other storage elements1610-B1and1610-B3are uncoupled from pixel driver elements and are unoperational.

During the fourth subframe ofFIG.16B, the switches1680,1674,1664,1654,1672and1672are OFF, whereas the switches1652is ON. As a result, only the third storage element1610-B3is in operation and coupled to pixel driver element1610-A, whereas other storage elements1610-B1and1610-B2are uncoupled from pixel driver elements and are unoperational.

Subframes two to four (FIG.16B) can be repeated during different operation periods so that different switches, and therefore storage element, are in operation for each subframe.

Tile Stacking for Optoelectronic System

Some embodiments of the present disclosure relate to tiled display device and more particularly, to stacking tiles to a backplane to form the tiled display device.

Here, different color microLEDs are used to explain the invention. However, different microdevices can be used instead of colored microLEDs.

According to one embodiment, there is provided a method of stacking tile structure layers to a substrate, each tile structure layer comprising plurality of microdevices, the method comprising: releasing a first tile structure layer on the substrate, providing and aligning a second tile structure layer with the first tile structure layer on the substrate; and bonding the first tile structure layer and the second tile structure layer on the substrate, wherein the first tile structure and the second tile structure are physically separated from each other.

In one embodiment, a tile structure may comprise one or more microdevices transferred onto a carrier substrate.

In another embodiment, a buffer layer may be formed on the carrier substrate before transferring the microdevices to the substrate. The buffer layer can be a release layer, a supporting substrate, or a backplane layer.

In another embodiment, the microdevices are planarized. The planarization layer is patterned or etch backed to open a connection to the microdevices.

In another embodiment, a first tile structure layer is released from the carrier substrate. Extra processing steps can be performed after the first tile structure layer transfer. For example, traces or bumps can be formed.

In another embodiment, a second tile structure layer is aligned with the first tile structure layer either through alignment mark or through the other structure in the first and the second tile structures layers.

In one embodiment, the second tile structure layer is then bonded to the first tile structure layer through the means of adhesive layer or bonding pads.

In another embodiment, vias can be formed through the tile structure layers to connect them together or provide connection to connect different layers to a backplane.

In one embodiment, the system substrate is bonded at the top of the tile structure. In one case, the substrate may be bonded at a bottom side of the tile structure.

In another embodiment, the backplane and substrate may be prepared separately from the tiles and then bond together. In another embodiment, the backplane is flexible between the tiles.

To improve surface profile, in one embodiment, the planarization layer is patterned at some areas to provide dents for bonding microdevices from the other tile layer structures.

In another embodiment, driving circuitry may form on the substrate prior to stacking of the tile layers. Here, vias/openings can be used to connect the tiles to the driving circuitry. The driving circuitry can be pixel circuits. Planarization and protection layer may be formed after the driving circuitry for preparing the surface for integration of stacked tile structure. The driving circuitry can be also a tile structure transferred to the substrate.

In one embodiment, there can be common electrode between each tile connecting one terminal of the devices together. The common electrode can be at multiple tiles or at the final common metalization layer.

In one case, the bonding layers may be formed between the tile layers for enabling integration of microdevices. The bonding layers can be adhesive or bonding pads. The adhesive can be different materials such as SU8, Polyamide, UV or thermal curable epoxy. The bonding pads can be Au/In or Au/Au or other materials compatible with compression, thermal compression, eutectic and bonding methods.

Each tile structure can be tested prior to stacking and the tile structure that meets some threshold in terms of performance and yield will be stacked.

FIG.17shows an embodiment of single-color tile structure with top metalization. To prepare a tile structure, one or more microdevices1708are transferred onto a carrier substrate1702. These microdevices may be of same color. The color may be one of red, green or blue. A buffer layer may be formed on the substrate1702before transferring the microdevices to the substrate1702. The buffer layer can be a release layer, a supporting substrate, or a backplane layer. It can include some optical layer as well. Each of the microdevices may be provided with contact pads or ohmic contacts1710over a surface of the microdevices. The microdevices1708are planarized. Other processing step can be performed after the planarization layer. For example, the planarization layer1706is patterned or etch backed to open a connection to the microdevices108. In another case, the planarization layer1706is etched back to expose the top of the microdevices1708. The openings/vias may be made through the planarization layer1706to provide metalization1704for traces and bridges. One of the traces can be a common electrode.

FIG.18shows a stacked tile bonded to a system (or temporary) substrate. Here, a tile structure layer is prepared where microdevices are transferred into a carrier substrate. The tile structure layer may be covered with planarization layers and other metalization layers. Other layers can be used such as support substrate layer or release layer. The first tile structure layer is bonded to the substrate through application of adhesive layer or bonding pads between the tile and the substrate. Then, the first tile structure layer is released from the carrier substrate. Extra processing steps can be performed after the first tile structure layer transfer. For example, traces or bumps can be formed. Then the second tile structure layer is aligned with the first tile structure layer either through alignment mark or through the other structure in the first and the second tile structures layers. The second tile structure layer is then bonded to the first tile structure layer through the means of adhesive layer or bonding pads. The process of stacking can continue for adding more functional microdevice tile structure layers into the substrate. Via can be formed through the tile structure layers to connect them together or provide connection to connect different layers to a backplane.

The substrate1802may be one of: a stacking substrate, a system substrate, a temporary substrate or a backplane. Here, the first tile layer structure having microdevices e.g.1820,1808-1released from the carrier substrate to the substrate1802. Extra processing steps can be performed after the first tile structure layer transfer. For example, traces or bumps can be formed. Then, a second tile layer structure having microdevices e.g.,1808-2released from other carrier substrate and aligned with the first tile layer structure through alignment mark (1810,1810-2) or through the other structure in the first and the second tile structures layers. The second tile structure layer is then bonded to the first tile structure layer through the means of adhesive layer or bonding pads. Further, a third tile structure having microdevices e.g.,1808-3released from other carrier substrate and aligned with bonded the first tile layer structure and the second tile layer structure through alignment mark (1810,1810-2and1810-3) or through the other structure in the first, second or third tile structures layers. The third tile structure layer is then bonded to the first and second tile structure layer through the means of adhesive layer or bonding pads. The process of stacking can continue for adding more functional microdevice tiles into the substrate. Vias can be formed through the tiles to connect them together. In one embodiment, the first microdevice tile and the second microdevice tile and subsequent tiles are physically separated from one another.

Here, the substrate is bonded at the top of the tile structure. In one case, the substrate may be bonded at a bottom side of the tile structure.

In one embodiment, the backplane and substrate may be prepared separately from the tiles and then bond together. In another embodiment, the backplane is flexible between the tiles.

FIG.19Ashows cross section of transferring of a first tile layer structure to a system substrate. Here, a first tile layer structure is bonded to a system (or temporary) substrate1902. The first tile structure layer is released from the carrier substrate. The first tile structure layer is prepared where microdevices are transferred into the carrier substrate. The transferred tile structure layer may be covered with planarization layers1912and other metalization layers1904. The first tile structure layer is bonded to the system substrate1902through application of adhesive layer or bonding pads between the tile and the substrate. Traces or bumps can also be formed. An alignment mark1910may be provided in the tile structure for the purpose of aligning with subsequent tiles with the first tile structure.

FIG.19Bshows cross section of patterning of the first tile layer structure on the system substrate and a second tile layer structure. The first tile layer structure may be patterned. The planarization layer1916around the microdevices1908is patterned or etch backed to remove excess material on or around the microdevices to ease the bonding process.

A second tile layer structure1920may be provided on a carrier substrate1922. A buffer layer may be formed on the substrate1922before transferring the microdevices1924to the substrate1922. The buffer layer can be a release layer, a supporting substrate, or a backplane layer. It can include some optical layer as well. Each of the microdevices may be provided with contact pads or ohmic contacts1926over a surface of the microdevices. The microdevices1924are planarized. The planarization layer1916-2is patterned or etch backed to open a connection to the microdevices1924. The openings/vias may be made through the planarization layer1916-2to provide metalization for traces and bridges.

To improve surface profile, in one embodiment, the planarization layer is patterned at some areas to provide dents1918for bonding microdevices from the other tile layer structures. An alignment mark1910-2may be provided in the second tile layer structure for the purpose of aligning with the first tile layer structure.

FIG.19Cshows a cross section of bonding between the second tile and the first tile structure on the system substrate1902. Here, the second tile layer structure is aligned with the first tile layer either through alignment marks (1910,1910-2) or through the other structure in the first and second tile structure. The second tile is then bonded to the first tile through the means of adhesive or bonding pads. The process of stacking can continue for adding more functional microdevice tiles into the substrate. In one case, Via can be formed through the tiles to connect them together.

In one embodiment, there can be common electrode between each tile connecting one terminal of the devices together. The common electrode can be at multiple tiles or at the final common metalization layer. Optical structure can form on top of each microdevice at different tiles to allow better light coupling to outside or from outside world to the device. In one case, the optical structure can be vias with metal around the area over the microdevice to confine the light.

FIG.19Dshows cross section of patterning the second tile layer structure and a third tile layer structure. The bonded first and second tile layer structures may be patterned to remove excess material on and around the microdevices to ease the bonding process.

A third tile layer structure1930may be provided on a carrier substrate. Each of the microdevices may be provided with contact pads or ohmic contacts over a surface of the microdevices. The microdevices are planarized. The planarization layer1916-3is patterned or etch backed to open a connection to the microdevices1924. The excessive planarization layer around the microdevices may be removed. An alignment mark1910-3may be provided in the third tile layer structure for the purpose of aligning with the bonded first and second tile layer structure.

FIG.19Eshows cross section of bonding of the third layer structure to the system substrate. Here, the bonded first and second tile layer structure is aligned with the third tile layer either through alignment marks (1910,1910-2,1910-3) or through the other structure in the tile structures. The third tile is then bonded to the second and first tile through the means of adhesive or bonding pads. The process of stacking can continue for adding more functional microdevice tiles into the substrate. Via can be formed through the tiles to connect them together.

In one embodiment, driving circuitry may form on the substrate prior to stacking of the tile layers. Here, via/opening can be used to connect the tiles to the driving circuitry. The driving circuitry can be pixel circuits. Planarization and protection layer may be formed after the driving circuitry for preparing the surface for integration of stacked tile structure. The driving circuitry can be also a tile structure transferred to the substrate.

FIG.20Ashows cross section of transferring of a first tile layer structure without metallization to a substrate and vias formed through the tiles and the backplane mounted to the top of the layers through via. Here, a first tile layer structure is bonded to a system (or temporary) substrate2002. The first tile structure layer is released from the carrier substrate. The tile structure layer is prepared where microdevices are transferred into the carrier substrate. The transferred tile structure layer may be covered with planarization layers2012. In this case, Vias may also be formed through the tiles and the backplane2002may be mounted to the top of the layers through vias. The first tile structure layer is bonded to the system substrate through application of adhesive layer or bonding pads between the tile and the substrate. Traces or bumps can also be formed. An alignment mark2010may be provided in the tile structure for the purpose of aligning with subsequent tiles.

FIG.20Bshows cross section of patterning of the first tile layer structure on the system substrate and a second tile layer structure. The first tile layer structure may be patterned. The planarization layer2012around the microdevices is patterned or etch backed to remove excess material on or around the microdevices to ease the bonding process.

A second tile layer structure2020may be provided on a carrier substrate2022. A buffer layer may be formed on the substrate2022before transferring the microdevices2024to the substrate2022. The buffer layer can be a release layer, a supporting substrate, or a backplane layer. It can include some optical layer as well. Each of the microdevices may be provided with contact pads or ohmic contacts over a surface of the microdevices. The microdevices2024are planarized. In one embodiment, the planarization layer is patterned at some areas to provide dents2018for bonding microdevices from the other tile layer structures. An alignment mark2010-2may be provided in the second tile layer structure for the purpose of aligning with the first tile layer structure.

FIG.20Cshows a cross section of bonding between the second tile and the first tile structure on the system substrate2002. Here, the second tile layer structure is aligned with the first tile layer either through alignment marks (2010,2010-2) or through the other structure in the first and second tile structure. The second tile is then bonded to the first tile through the means of adhesive or bonding pads. The process of stacking can continue for adding more functional microdevice tiles into the substrate. In one case, Via can be formed through the tiles to connect them together.

In one embodiment, there can be common electrode between each tile connecting one terminal of the devices together. The common electrode can be at multiple tiles or at the final common metalization layer. Optical structure can form on top of each microdevice at different tiles to allow better light coupling to outside or from outside world to the device. In one case, the optical structure can be vias with metal around the area over the microdevice to confine the light.

FIG.20Dshows cross section of patterning the second tile layer structure and a third tile layer structure. The bonded first and second tile layer structures may be patterned to remove excess material on and around the microdevices to ease the bonding process.

A third tile layer structure2030may be provided on a carrier substrate. Each of the microdevices may be provided with contact pads or ohmic contacts over a surface of the microdevices. The microdevices are planarized. The excessive planarization layer around the microdevices may be removed. An alignment mark2010-3may be provided in the third tile layer structure for the purpose of aligning with the bonded first and second tile layer structure.

FIG.20Eshows cross section of bonding of the third layer structure to the system or temporary (carrier) substrate. Here, the bonded first and second tile layer structure is aligned with the third tile layer either through alignment marks (2010,2010-2,2010-3) or through the other structure in the tile structures. The third tile is then bonded to the second and first tile through the means of adhesive or bonding pads. The process of stacking can continue for adding more functional microdevice tiles into the substrate. Via can be formed through the tiles to connect them together.

In another embodiment, driving circuitry may form on the substrate prior to stacking of the tile layers. Here, via/opening can be used to connect the tiles to the driving circuitry. The driving circuitry can be pixel circuits. Planarization and protection layer may be formed after the driving circuitry for preparing the surface for integration of stacked tile structure. The driving circuitry can be also a tile structure transferred to the substrate.

Each tile structure can be tested prior to stacking and the one that meet some threshold in terms of performance and yield will be stacked.

FIG.21Ashows a cross section of color tile with bonding pads2120formed on top of the stacked layers. Here, the substrate2102may be at bottom side. The bonding layers (2106-1,2006-2) may be formed between the tile layers2112for enabling integration of microdevices. The substrate2102may be one of a stacking substrate, a system substrate, a temporary substrate or a backplane. Here, a tile structure is a full color tile that includes a plurality of microdevices (e.g, R, G, B as shown inFIG.19). The microdevices may be bonded to the substrate in different tile layers2112. There can be common electrode2104between each tile connecting one terminal of the devices together. The common electrode can be at multiple tiles or at the final common metalization layer. Optical structure2122can form on top of each microdevice at different tiles to allow better light coupling to outside or from outside world to the device. In one case, the optical structure can be vias with metal around the area over the microdevice to confine the light.

A bonding layer2106-1may be formed on a surface where the second microdevice tile (e.g. G) will be bonded. The bonding layer can be adhesive or bonding pads. The adhesive can be different materials such as SUB, Polyamide, UV or thermal curable epoxy. The bonding pads can be Au/In or Au/Au or other materials compatible with compression, thermal compression, eutectic and bonding methods.

In one embodiment, a backplane may be formed on top, bottom or in between the tile layers.

In one embodiment, one or more planarization layers may be formed to level the substrate surface. In one case, an opening through the planarization layer(s) may be provided to create contact between the microdevices and substrate. In another case, the bonding layers and the planarization layer may be the same. In another case, the bonding layers may be formed separately.

FIG.21Bshows vias can be formed through the tiles to connect them together and the backplane may be mounted to the top of the stacked layers through vias.

FIG.21Cshows driving circuitry2120may form on the substrate prior to stacking of the tile layers. Here, via opening can be used to connect the tiles to the driving circuitry. The driving circuitry can be pixel circuits. Planarization and protection layer may be formed after the driving circuitry for preparing the surface for integration of stacked tile structure. The driving circuitry can be also a tile structure transferred to the substrate.

FIG.22shows another cross section of full color tile bonded to a system (or temporary) substrate. In one embodiment, the contact pads (2212-1,2212-2) or ohmic contacts may be formed on opposite sides of the microdevice between the tile layers. Here, the microdevice have bonding pads at top and bottom surface of the device. The metallization on the contact pads may be provided through openings in the planarization layers provided between the tile layers.

FIG.23Ashows a cross-sectional view of a single-color tile structure, in accordance with an embodiment of the invention. Here, a carrier substrate2302is provided with one or more microdevices2304. These microdevices2304can be fabricated directly on the carrier substrate or transferred to the carrier substrate from a growth substrate. The microdevices can be of the same type. In one example, the microdevices are microLED and can be the same color. The color can be one of red, green or blue. A buffer layer2306can be formed on the substrate2302before transferring the microdevices2304-1to the carrier substrate2302. The buffer layer can be a release layer, a supporting substrate, or a backplane layer. It can include some optical layer as well.

FIG.23Bshows a cross-sectional view of a single-color tile structure with planarization layer and top electrodes, in accordance with an embodiment of the invention. Here, a planarization layer2308-1is formed around the microdevice. Other processing steps can be performed after the formation of planarization layer2308-1. For example, the planarization layer2308-1is patterned or etch backed to open a connection to the microdevices2304-1. Each of the microdevices may be provided with an electrode2310-1over a top surface of microdevices2304-1.

FIG.23Cshows a cross-sectional view of a first single color tile structure bonded to a system (or temporary) substrate, in accordance with an embodiment of the invention. The substrate2312may be one of a stacking substrate, a system substrate, a temporary substrate or a backplane. Here, a first tile layer structure (as shown inFIGS.23A &23B) having microdevices e.g.2304-1released from the carrier substrate and bonded or transferred to a substrate2312. The substrate2312can be a temporary substrate. The first tile structure is bonded to the temporary substrate2312through an application of adhesive layer or bonding layer2314between microdevices2304-1and the temporary substrate2312. Then, the carrier substrate can be removed after bonding with the temporary substrate. In one case, the buffer layer can also be removed.

FIG.23Dshows a cross-sectional view of a first single color tile structure bonded to a system (or temporary) substrate having bottom connections, in accordance with an embodiment of the invention. The connections can be provided to the microdevices on a surface opposite to the microdevices. Here, after the removal of buffer layers, bottom electrodes2316-1may be formed on a surface opposite to a first surface of microdevices2304-1to extend the connection of the microdevices if there is one at the bottom side.

The process of stacking can continue for adding more functional microdevice tile structure layers into the temporary substrate. In one embodiment, the first microdevice tile and the second microdevice tile and subsequent tiles are physically separated from one another.

In one embodiment, the temporary substrate is bonded at the top of the tile structure. In another embodiment, the temporary substrate may be bonded at a bottom side of the tile structure.

FIG.23Eshows a cross-sectional view of a second single color tile structure bonded to the temporary substrate, in accordance with an embodiment of the invention. Here, a second tile layer structure having microdevices e.g.,2304-2, a second planarization layer2308-2, top electrodes2310-2and bottom electrodes2316-2may be formed separately on another carrier substrate. The microdevices2304-2can be released from other carrier substrate and aligned with the first tile layer structure. The second tile structure layer is then bonded to the first tile structure layer through the means of adhesive layer or bonding pads2314-2. Each of the second microdevices2304-2can be provided with top electrodes2310-2over a top surface of the microdevices and bottom electrode2316-2on a surface opposite to a first surface of microdevices2304-2to extend the connection of the microdevices2304-2if there is one at the bottom side.

FIG.23Fshows a cross-sectional view of vias formed through the tile structures, in accordance with an embodiment of the invention. Here, vias2324can be formed through the tile structure layers to connect them together or provide connection to connect different layers to the temporary substrate2312.

FIG.23Gshows a cross-sectional view of vias connected with pads and electrodes, in accordance with an embodiment of the invention. Here, vias2324corresponding to top electrodes (2310-1,2310-2) can be filed with conductive materials and some can be connected together to form a common electrode2330. The common electrode between each tile connecting one terminal of the devices together. The common electrode can be at multiple tiles or at the final common metalization layer. Pads2332can be formed on part of the bottom electrodes (2316-1,2316-2) for bonding or some can be connected together to form a common pad.

FIG.23Hshows a cross-sectional view of bonding between the temporary substrate and a backplane, in accordance with an embodiment of the invention. In one embodiment, the backplane and temporary substrate may be prepared separately from the tiles and then can be bonded together. In another embodiment, the backplane is flexible between the tiles structures. The backplane2340may include driving circuitry2334. The driving circuitry may include pixels circuits and electrodes. The driving circuitry can include a common electrode or a patterned electrode for each microdevice. The backplane2340can have pads corresponding to the pads2332of stacked microdevices. The microdevices can get bonded or connected to the backplane2340through the pads2336or other adhesive layers.

FIG.23Ishows a cross-sectional view of an optical layer on the temporary substrate, in accordance with an embodiment of the invention. Here, an optical layer2342can be provided on the temporary substrate2312prior to stacking tile layer structures. The optical layer2342can confine the light output of the microdevices or the input light to the microdevices. Furthermore, the optical layer2342can also reduce the viewing angle effect as the light of different layers will be combined and push out through the optical layer2342.

FIG.23Jshows a cross-sectional view of an optical layer on the temporary substrate bonded to the backplane, in accordance with an embodiment of the invention. Here, an optical layer2342can be provided on the temporary substrate2312prior to stacking microdevice layers. In one case, optical layer can form on top of each microdevice at different tiles to allow better light coupling. The optical layer can confine the light output of the microdevices or the input light to the microdevices. It can also reduce the viewing angle effect as the light of different layers will be combined and push out through the optical layer2342. Then, the temporary substrate and the backplane can be bonded together. The backplane2340may include driving circuitry2334. The driving circuitry may include pixels circuits and electrodes. The driving circuitry can include a common electrode or a patterned electrode for each microdevice. The backplane2340can have pads corresponding to the pads2332of stacked microdevices. The microdevices can get bonded or connected to the backplane2340through the pads2336or other adhesive layers.

FIG.23Kshows a cross-sectional view of patterned stacked tiles layer structure on a temporary substrate, in accordance with an embodiment of the invention. Here, the stacked tiles layer structure can be patterned to create isolated areas including a plurality of microdevices. The isolated areas or islands can represent pixel areas. The patterning can happen at the temporary substrate or after bonding to the backplane.

FIG.23Lshows a cross-sectional view a reflective layer formed around the islands, in accordance with an embodiment of the invention. Here, a reflective layer2346can be formed around the islands to further reduce the viewing angle effect by directing the light from different layers to one surface.

FIG.23Mshows a cross-sectional view of patterned stacked tiles layer structure on a backplane, in accordance with an embodiment of the invention. Here, the stacked tiles layer structure can be patterned to create isolated area including a plurality of microdevices after bonding to the backplane. The isolated areas or islands can represent pixel areas. The patterning happened after bonding the temporary substrate to the backplane.

FIG.23Nshows a cross-sectional view of removal of the temporary substrate, in accordance with an embodiment of the invention. Here, after bonding with the backplane, the temporary substrate can be removed. The space between pixels can be filed by fillers. The fillers can be black matrix. In one case, the fillers can be filled between the pixels prior to transfer to the temporary substrate.

FIG.24shows a schematic top view of a tiled stacked display as shown inFIG.23N, in accordance with an embodiment of the invention. Here, in top view of a tile stacked display, the stacked layer structure is patterned into isolates area of islands including plurality of microdevices. The islands can be formed with some random positioning to reduce the visual artifact in case few different tiles are bonded in one backplane. Each island may include common pads2402, common electrode2412, vias2410, microdevice pads2404, planarization layers2306and reflector layers2408around the islands to further reduce the viewing angle effect by directing the light from different layers to one surface.

According to one embodiment, a method of integrating microdevices may be provided. The method may comprising: providing one or more microdevices on a donor substrate, integrating a first set of microdevices from the donor substrate to a system substrate, providing one or more staging pads to a second set of devices on the donor substrate; and integrating the second set of microdevices to the system substrate.

According to another embodiment, the one or more staging pads are one of: a conductive layer, a planarization layer, or a pillar formed on a substrate or microdevice surface and the one or more staging pads create a connection between the microdevices and the system substrate.

According to one embodiment, the method may further comprising providing one or more planarization layers over integrated microdevices to the system substrate, wherein an opening is created in the planarization layer to couple the microdevices to a signal.

According to another embodiment, the method may further comprising depositing an electrode over the microdevices through the opening in the planarization layer, adding a bonding layer to the electrode and a reflective layer is provided to each microdevice.

According to some embodiments, the first microdevice and the second microdevice are overlapped and connected through a common electrode.

According to one embodiment, a solid state array device comprising one or more pixels, each pixel has two or more microdevices and at least one of the two microdevices coupled to a pixel circuit and each microdevice is coupled to a bias voltage through a corresponding switch.

According to another embodiment, the pixel circuit is one of: a pixel circuit corresponding to each microdevice and a shared pixel circuit between the microdevices and wherein the shared pixel circuit is allocated to each microdevice for a given time during a frame time.

According to some embodiments, the one of the microdevices is coupled to the shared pixel circuit through the switch and decoupled to the bias voltage, to turn on the microdevice during an operational mode and the one of the microdevices is decoupled from the shared pixel circuit through the switch and coupled to the bias voltage, to turn off the microdevice during an unoperational mode.

According to one embodiment, an on time of each microdevice is extended and at least two microdevices are operational during one sub frame of the frame time. Each microdevice is provided with a corresponding storage element coupled to the shared pixel circuit through corresponding switches, wherein the storage element comprises a capacitor.

According to another embodiment, a method of stacking tile structure layers to a substrate may be provided. Each tile structure layer comprising plurality of microdevices. The method may comprising: releasing a first tile structure layer on the substrate, providing and aligning a second tile structure layer with the first tile structure layer on the substrate; and bonding the first tile structure layer and the second tile structure layer on the substrate, wherein the first tile structure and the second tile structure are physically separated from each other.

According to a further embodiment, the second tile structure layer aligned with the first tile structure layer through alignment marks, the second tile structure layer bonded to the first tile structure layer through means of an adhesive layer or bonding pads, wherein the bonding pads formed on either side of the microdevices between tile structures layers and the first tile structure layer and second tile structure layer is covered with planarization layers and metalization layers.

According to another embodiment, the method may further comprising providing vias through the planarization layers to connect first tile structure layer and second tile structure layer together or provide connection to connect different tile structure layers to the substrate, providing vias through first tile structure layer and second tile structure layer to couple the tile layers to controlling and biasing signals, wherein the substrate is one of: a temporary substrate, a system substrate or a backplane and is affixed to either a bottom surface, a top surface or in between the tile layer structures. The microdevices are of the same or different colors.

According to one embodiment, the method may further comprising providing driving circuitry on the substrate prior to stacking the tile layer structures, testing each tile structure layer prior to stacking, providing bonding layers between the tile structures layers for enabling integration of microdevices, providing common electrode between each tile structure layer for connecting one terminal of the microdevices together and forming an optical structure on each microdevice at different tile structure layers.

According to another embodiment, the bonding layers is one of adhesive or bonding pads, wherein the adhesive is one of: SU8, Polyamide, UV or thermal curable epoxy, The bonding pads is one of: Au/In, Au/Au or other materials compatible with compression, thermal compression, and eutectic bonding methods and formed on either side of the microdevice between the tile structures layers. The second tile structure layer has dents in the planarization layer to receive microdevices from the first tile layer structure, wherein an excess of planarization layer around the microdevices in the first layer structure is removed to ease the bonding.

According to one embodiment, a display device may be provided. The display device may comprising a plurality of tile structures stacked with each other, each of the tile structure including: a substrate; an array of microdevices disposed on the substrate; top electrodes disposed on a first surface of each microdevice; and bottom electrodes disposed on a surface opposite to the first surface of the microdevices; and a backplane bonded to the plurality of the tile structures.

According to one embodiment, the plurality of tile structures transferred to a temporary substrate before bonding with the backplane and the plurality of tile structures are bonded with each other through a bonding layer in between.

According to another embodiment, a planarization layer is formed between the array of microdevices for each tile structure and provides openings for the top electrodes and the bottom electrodes to make connections with microdevices. A common electrode is provided between each tile structures for connecting the microdevices together.

According to some embodiments, the bottom electrodes comprises bonding pads for the microdevices to bond with the backplane. The backplane comprises driving circuitry and contact pads corresponding to the bonding pads of the microdevices. An optical layer is provided on the temporary substrate prior to stacking tile structures to the temporary substrate, wherein the stacked tiles structures are patterned to create islands at the temporary substrate or after bonding to the backplane.

According to another embodiment, a reflective layer is provided around the islands to reduce viewing angle effect by directing the light from different tile structures to one surface.

According to a further embodiment, the temporary substrate is removed after bonding with the backplane and a space between the microdevices is filled by a filling material before or after bonding with the backplane.

In summary, the present disclosure discloses structures and methods to integrate microdevices into system or receiver substrates. The integration of microdevices is facilitated by adding staging pads to microdevices before or after transferring. Creating stages after the transfer of a first microdevice to a substrate for the subsequent microdevice transfer to the first (or the second) microdevice transfer. The stage improves the surface profile of the substrate so that next microdevice can be transferred without the first microdevice on the substrate get damaged by or interfere with the surface of the donor or transfer head. Some embodiments further relate to tiled display device and more particularly, to stacking tiles to a backplane to form the tiled display device.

While particular embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations can be apparent from the foregoing descriptions without departing from the spirit and scope of the invention as defined in the appended claims.