Patent ID: 12236996

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following detailed description, only certain embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. The sequence of operations or steps is not limited to the order presented in the claims or figures unless specifically indicated otherwise. The order of operations or steps may be changed, several operations or steps may be merged, a certain operation or step may be divided, and a specific operation or step may not be performed.

As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Although the terms first, second, and the like may be used herein to describe various elements, components, steps and/or operations, these terms are only used to distinguish one element, component, step or operation from another element, component, step, or operation.

FIG.1is a block diagram of an example of a memory system according to an embodiment.

Referring toFIG.1, a memory system100may include a memory device110and a memory controller120. In some embodiments, the memory device110and the memory controller120may be connected through a memory interface to send and receive signals through the memory interface.

The memory device110may include a memory cell array111and a refresh control circuit112. The memory cell array111may include a plurality of memory cells defined by a plurality of rows and a plurality of columns. In some embodiments, the rows may be defined by word lines and the columns may be defined by bit lines. The refresh control circuit112may detect an aggressor row from among the rows, determine a row address (referred to as a “victim row address”) of a victim row to be refreshed based on a row address (referred to as an “aggressor row address”) of the aggressor row, and output the victim row address. In some embodiments, the aggressor row may be a rowhammer aggressor row, and the victim row may be a row for rohammer care.

The memory controller120may control a memory operation of the memory device110by providing a signal to the memory device110. The signal may include a command CMD and an address ADDR. In some embodiments, the memory controller120may provide the command CMD and the address ADDR to the memory device110to access the memory cell array111and control a memory operation such as read or write. Data may be transferred from the memory cell array111to the memory controller120according to a read operation, and data may be transferred from the memory controller120to the memory cell array111according to a write operation.

The command CMD may include an activate command, a read/write command, and a refresh command. In some embodiments, the command CMD may further include a precharge command. The activate command may be a command for activating a target row of the memory cell array111in order to write data to or read data from the target row the memory cell array111. The read/write command may be a command for performing the read or write operation on a target memory cell of the activated row. The refresh command may be a command for performing a refresh operation in the memory cell array111. In some embodiments, the refresh control circuit112may output a normal refresh command or a targeted refresh command in response to the refresh command. The targeted refresh command may be a refresh command that instructs an operation to refresh a victim row. Since the targeted refresh targets the victim row, it may be referred to as a “target row refresh” or a “forced refresh”. The normal refresh command may be a refresh command that instructs a normal refresh operation, for example, an operation for sequentially refreshing rows of the memory cell array111. The normal refresh may include, for example, an auto-refresh performed when the memory device200is in use and a self-refresh performed when the memory device200is in an idle state.

In some embodiments, the memory controller120may access the memory device110in response to a request from a host external to the memory system100. The memory controller120may communicate with the host using various protocols.

The memory device110may be a storage device based on a semiconductor device. In some embodiments, the memory device110may include a DRAM device. In some embodiments, the memory device110may include other volatile or non-volatile memory devices for which the refresh operation is used.

FIG.2is a block diagram of an example of a memory device according to an embodiment.

Referring toFIG.2, a memory device200may include a memory cell array210, a sense amplifier211, a command decoder220, an address buffer230, a row decoder250, a column decoder260, an input/output (I/O) gating circuit270, a data I/O buffer280, and a refresh control circuit290.

The memory cell array210may include a plurality of memory cells MC. In some embodiments, the memory cell array210may include a plurality of memory banks210ato210h. AlthoughFIG.2shows eight memory banks210ato210h(Bank0to Bank7), the number of memory banks is not limited thereto. Each of the memory banks210ato210hmay include a plurality of rows, a plurality of columns, and a plurality of memory cells MC arranged at intersections of the plurality of rows and the plurality of columns. In some embodiments, the rows may be defined by a plurality of wordlines WL, and the columns may be defined by a plurality of bitlines BL.

The command decoder220may generate a control signal so that the memory device200may perform a read operation, a write operation, or a refresh operation. The command decoder221may generate a refresh command REF by decoding a command CMD received from a memory controller (e.g.,120inFIG.1).

The address buffer230may receive an address ADDR provided by the memory controller120. The address ADDR may include a row address RA indicating a row of the memory cell array210and a column address CA indicating a column of the memory cell array210. The row address RA may be provided to the row decoder250, and the column address CA may be provided to the column decoder260. The row address RA may be provided to the refresh control circuit290through the command decoder220or may be provided directly to the refresh control circuit290. In some embodiments, the row address RA may be provided to the row decoder250via a row address multiplexer251. In some embodiments, the address ADDR may further include a bank address BA indicating a memory bank.

In some embodiments, the memory device200may further include the row address multiplexer251. The row address multiplexer251may receive the row address RA from the address buffer230, and a refresh row address REF RA to be refreshed from the refresh control circuit290. The row address multiplexer251may selectively output the row address RA received from the address buffer230and the refresh row address REF RA received from the refresh control circuit290to the row decoder250.

The row decoder250may select a row to be activated from among the rows of the memory cell array210based on the row address RA or the refresh row address REF RA. The row decoder250may apply a driving voltage to a wordline corresponding to the row to be activated. In some embodiments, a plurality of bank row decoders250ato250hrespectively corresponding to the memory banks210ato210hmay be provided.

The column decoder260may select a column to be activated from among the columns of the memory cell array210based on the column address CA. The column decoder260may activate the sense amplifier211corresponding to the column address CA through the I/O gating circuit270. In some embodiments, a plurality of bank column decoders260ato260hrespectively corresponding to the memory banks210ato210hmay be provided. In some embodiments, the I/O gating circuit270may gate I/O data, and may include a data latch that stores data read from the memory cell array210and a write driver that writes data to the memory cell array210. The data read from the memory cell array210may be sensed by the sense amplifier211and stored in the I/O gating circuit270(e.g., the data latch). In some embodiments, a plurality of sense amplifiers211ato211hrespectively corresponding to the memory banks210ato210hmay be provided.

In some embodiments, the memory device200may further include a bank control logic circuit240that generates a bank control signal in response to the bank address BA. In response to the bank control signal, a bank row decoder corresponding to the bank address BA among the bank row decoders250ato250hmay be activated, and a bank column decoder corresponding to the bank address BA among the bank column decoders260ato260hmay be activated.

In some embodiments, the data read from the memory cell array210(e.g., the data stored in the data latch) may be provided to the memory controller120via the data I/O buffer280. The data to be written to the memory cell array210may be provided from the memory controller120to the data I/O buffer280, and the data provided to the data I/O buffer280may be provided to the I/O gating circuit270.

The refresh control circuit290may transfer the refresh row address REF RA to be refreshed to the row decoder250in response to the refresh command REF. In some embodiments, the refresh control circuit290may include a targeted refresh control circuit291, a normal refresh control circuit292, and a refresh row address selector293. The target refresh control circuit291may calculate a victim row address VRA based on the number of accesses of each row address, and may output the victim row address VRA in response to a targeted refresh command. The targeted refresh command may be a rowhammer refresh command. The normal refresh control circuit292may calculate a row address NRA on which a normal refresh operation is to be performed, and may output the row address NRA in response to a normal refresh command. The refresh row address selector293may selectively output the victim row address VRA from the targeted refresh control circuit291or the row address NRA from the normal refresh control circuit292. In some embodiments, the refresh row address selector293may output the row address NRA from the normal refresh control circuit292as the refresh row address REF RA in response to the normal refresh command, and may output the victim row address VRA from the targeted refresh control circuit291as the refresh row address REF RA in response to the targeted refresh command.

FIG.3is a block diagram showing an example of a memory device according to an embodiment, andFIG.4is a diagram showing an example of a refresh period in a memory device according to an embodiment.

Referring toFIG.3, a memory device300may include a refresh control circuit310, a plurality of counters320, a plurality of flags330, and a queue340. In some embodiments, the refresh control circuit310ofFIG.3may correspond to the targeted refresh control circuit (e.g.,291ofFIG.2).

The counters320may correspond to a plurality of rows of a memory cell array (e.g.,111inFIG.1or210inFIG.2), respectively. Each counter320may count the number of accesses to a corresponding row and store a count value, and may have a plurality of bits. Each time a row address (hereinafter referred to as “incoming row address”) RA of a row to be activated in the memory cell array (111or210) is received from a memory controller (e.g.,120inFIG.1), the count value of the counter320corresponding to the incoming row address RA may be updated (e.g., increased). The flags330may correspond to the rows of the memory cell array, respectively. Each flag330may store a flag value of a corresponding row, and may have a plurality of bits.

The queue340may store an aggressor row address ARA. In some embodiments, the queue340may output a predetermined number (e.g., one) of the aggressor row addresses ARA from among stored aggressor row addresses ARA in response to a targeted refresh command. The queue340may be implemented as, for example, a flip-flop, a latch, a buffer circuit, or a static random-access memory (SRAM), but is not limited thereto. For example, the queue340may store a plurality of addresses.

Referring toFIG.4, the memory device300may manage a normal refresh so that each memory cell of a corresponding bank is refreshed every refresh period tREFW. In some embodiments, the refresh period tREFW may correspond to a normal refresh period, and may be, for example, a refresh window. The refresh control circuit310may set a refresh flag R_Flag in the refresh period tREFW and update the refresh flag R_Flag each time the refresh period tREFW changes. When the refresh flag R_Flag has a plurality of bits, the refresh control circuit310may update the refresh flag R_Flag by changing (for example, increasing) the refresh flag R_Flag by one each time the refresh period tREFW changes. In some embodiments, the number of bits in the refresh flag R_Flag may be equal to the number of bits in the flag330. For example, when the refresh flag R_Flag has two bits, the refresh control circuit310may sequentially update the refresh flag R_Flag to “00”, “01”, “10”, “11”, and “00” each time the refresh period tREFW change.

Referring toFIG.3again, the refresh control circuit310may receive a count value of a counter (referred to as a “target counter”)320corresponding to the incoming row address RA among the counters320, and receive a flag value of a flag (referred to as a “target flag”)330corresponding to the incoming row address RA among the flags330, in response to a row operation command. In some embodiments, the row operation command may be an activation command ACT or a precharge command PRE. The refresh control circuit310may determine whether to put the incoming row address RA into the queue340as the aggressor row address ARA based on the count value, the flag value, and a flag value of a refresh flag (referred to as a “current refresh flag”)311set in a current refresh period. In some embodiments, the refresh control circuit310may store the current refresh flag311in a device, which can store an updated value, for example, such as a counter or a register.

When the count value of the incoming row address RA, the flag value of the incoming row address RA, and the flag value of the current refresh flag311satisfy a predetermined condition, the refresh control circuit310may put the incoming row address RA into the queue340as the aggressor row address ARA. In some embodiments, the predetermined condition may include a condition in which the count value of the incoming row address RA reaches a first threshold and a difference between the flag value of the incoming row address RA and the flag value of the current refresh flag311is less than or equal to a predetermined value. In some embodiments, when the predetermined condition is satisfied, the refresh control circuit310may update the flag value of the incoming row address RA. In some embodiments, the refresh control circuit may update the flag value of the incoming row address RA by setting the flag value of the incoming row address RA to be equal to the flag value of the current refresh flag311. Accordingly, the flag value of the target flag330corresponding to the incoming row address RA may be updated.

In some embodiments, the refresh control circuit310may maintain the flag value of the incoming row address RA without putting the incoming row address RA into the queue340, when the count value of the incoming row address RA reaches the first threshold but the difference between the flag value of the incoming row address RA and the flag value of the current refresh flag311is greater than the predetermined value.

In some embodiments, the refresh control circuit310may update the flag value of the incoming row address RA without putting the incoming row address RA into the queue340when the count value of the incoming row address RA is less than or equal to a second threshold that is less than the first threshold.

In some embodiments, the refresh control circuit310may maintain the flag value of the incoming row address RA without putting the incoming row address RA into the queue340when the count value of the incoming row address RA is greater than the second threshold but does not reach the first threshold.

The refresh control circuit310may extract a predetermined number (e.g., one) of row addresses from the queue340when a targeted refresh command is received, and determine a victim row address based on the extracted row address. Accordingly, the memory device may refresh a victim row indicated by the victim row address. The refresh control circuit310may determine a row adjacent to an aggressor row indicated by the aggressor row address as the victim row. In some embodiments, the victim row may include a predetermined number of rows physically adjacent to the aggressor row. For example, when the aggressor row is an mthrow and the predetermined number is two, the victim row may include an (m+1)throw and an (m−1)throw. Alternatively, when the aggressor row is an mthrow and the predetermined number is four, the victim row may include an (m+2)throw, an (m+1)throw, an (m−1)throw, and an (m−2)throw.

As described above, the refresh control circuit310may prevent the queue340from overflowing by not putting a row address that has managed by the normal refresh into the queue340even if the number of accesses to the row is large. In particular, when the number of accesses for all rows of the memory cell array is managed, the queue340may be highly likely to overflow due to a large number of rows. However, by not putting the row addresses managed by the normal refresh into the queue340, the queue340may be prevented from overflowing. Accordingly, the memory device300may efficiently perform the targeted refresh by preventing a warning due to the overflow of the queue340from occurring and by not putting row addresses of rows, on which the targeted refresh does not need to be performed due to the normal refresh, into the queue.

Next, a refresh method of a memory device according to an embodiment is described with reference toFIG.5andFIG.6.

FIG.5is a flowchart showing an example of a refresh method of a memory device according to an embodiment, andFIG.6is a diagram showing an example of row addresses used in a refresh method shown inFIG.5.

For convenience, four example rows (i.e., row addresses RA1, RA2, RA3, and RA4), and counters and flags to them are shown inFIG.6. It is assumed that a count value611of “101111111111” and a flag value621of “11” are stored in the counter and the flag corresponding to the row address RA1, respectively; a count value612of “001000011011” and a flag value622of “01” are stored in the counter and the flag corresponding to the row address RA2, respectively; a count value613of “000111111001” and a flag value623of “01” are stored in the counter and the flag corresponding to the row address RA3, respectively; and a count value614of “100111111111” and a flag value624of “01” are stored in the counter and the flag corresponding to the row address RA4, respectively. Further, it is assumed that a first threshold is 512 and a second threshold is 460, which is approximately (9/10) of the first threshold. Furthermore, it is assumed that a flag value (referred to as a “current refresh flag value”)630of a refresh flag in a current refresh period is “11”.

Referring toFIG.5, a memory device, for example, a refresh control circuit may receive a count value and a flag value of an incoming row address in response to a row operation command in S510. In some embodiments, the row operation command may be an activation command or a precharge command. The refresh control circuit may compare the count value of the incoming row address with a threshold in S520and S530. The threshold may include a first threshold and a second threshold less than the first threshold.

When the count value of the incoming row address does not exceed the second threshold in S520(No), the refresh control circuit may update the flag value of the incoming row address to be equal to the current refresh flag value in S560, and update (e.g., increase) the count value of the incoming row address without putting the incoming row address RA into the queue340in S570. In some embodiments, the refresh control circuit may determine whether the count value exceeds the second threshold by comparing a predetermined number of least significant bits in the count value with the second threshold in S520. The refresh control circuit may determine that the count value does not exceed the second threshold when the count value is equal to or less than the second threshold. A case in which the count value is equal to or less than the second threshold may be interpreted as a case in which the count value is less than a threshold obtained by adding one to the second threshold. In some embodiments, since the number of accesses of the incoming row address is increased by reception of the incoming row address, the refresh control circuit may compare the increased count value (i.e., the increased number of accesses) with the second threshold. In some embodiments, the refresh control circuit may compare the count value before being increased with the second threshold. In this case, the second threshold may be set to a threshold obtained by subtracting one from the second threshold compared with the increased count value. For example, as shown inFIG.6, the count value612of the incoming row address RA2does not exceed the second threshold of 460 because the lowest nine bits of “001000011011” are “000011011”. Accordingly, the refresh control circuit may update the flag value622of the incoming row address RA2to “11”, which is the current refresh flag value. In addition, the refresh control circuit may increase the count value612of the counter of the incoming row address RA2to “001000011100”. As such, when the count value is less than the second threshold, the corresponding row address may be in a low level of disturbance. Accordingly, the refresh control circuit may update the flag value622to the current refresh flag value630, so that the corresponding row address RA2may be treated as being refreshed by a normal refresh in the current refresh cycle.

When the count value of the incoming row address exceeds the second threshold in S520(Yes) but does not reach the first threshold in S530(No), the refresh control circuit may update the count value of the incoming row address without updating the flag value of the incoming row address without putting the incoming row address RA into the queue340in S570. Although not shown, in some embodiments, when the count value of the incoming row address exceeds the second threshold in S520(Yes) but does not reach the first threshold in S530(No), the refresh control circuit may update the flag value of the incoming row address RA without putting the incoming row address RA into the queue340in S560. In some embodiments, the refresh control circuit may determine whether the count value reaches the first threshold by comparing a predetermined number of least significant bits in the count value with the first threshold in S530. The refresh control circuit may determine that the count value reaches the first threshold when the count value is equal to the first threshold. A case in which the count value is equal to the first threshold may be interpreted as a case in which the count value exceeds a threshold obtained by subtracting one from the first threshold. In some embodiments, since the number of accesses of the incoming row address is increased by reception of the incoming row address, the refresh control circuit may compare the increased count value (i.e., the increased number of accesses) with the first threshold. In some embodiments, the refresh control circuit may compare the count value before being increased with the first threshold. In this case, the first threshold may be set to a threshold obtained by subtracting one from the first threshold compared with the increased count value. For example, as shown inFIG.6, the count value613of the incoming row address RA3exceeds the second threshold of 460 but does not reach the first threshold of 512 because the lowest nine bits of “000111111001” are “111111001”. Accordingly, the refresh control circuit may increase the count value613of the counter of the incoming row address RA3to “000111111010” without updating the flag value623of the incoming row address RA3. In this way, the refresh control circuit may determine that the incoming row address RA3is being accessed continuously in the same refresh period by not updating the flag value623.

When the count value of the incoming row address reaches the first threshold in S530, the refresh control circuit may compare the flag value of the incoming row address with the current refresh flag value in S540. When a difference between the flag value of the incoming row address and the current refresh flag value is greater than a predetermined value in S540(No), the refresh control circuit may update the count value of the incoming row address without updating the flag value of the incoming row address in S570. Further, the refresh control circuit may not put the incoming row address into a queue. A case where the difference between the flag value of the incoming row address and the current refresh flag value is greater than the predetermined value may be interpreted as a case in which the difference between the flag value of the incoming row address and the current refresh flag value is greater than or equal to a value obtained by adding one to the predetermined value. For example, as shown inFIG.6, because the lowest nine bits of the count value (“100111111111”)614of the incoming row address RA4are “111111111”, the 10thbit of the count value614may be flipped, so the count value614of the incoming row address RA4may reach the first threshold. In this case, the difference between “01”, which is the flag value624of the incoming row address RA4, and “11”, which is the current refresh flag value630, is two, which is greater than a predetermined value (e.g., one). Accordingly, the refresh control circuit may increase the count value614of the counter of the incoming row address RA4to “101000000000” without updating the flag value624of the incoming row address RA4. As such, when the difference between the flag values624and630is greater than the predetermined value (e.g., one), an additional refresh period may exist between a refresh period (flag value of “01”) in which intensive accesses have been occurred and the current refresh period (flag value of “11”). Accordingly, the refresh control circuit may determine that the row indicated by the incoming row address RA4is a row that has been previously managed by the normal refresh, and may not put the incoming row address RA4into the queue.

On the other hand, since an attack may occur at an end of the previous refresh cycle, the refresh control circuit may not determine whether the flag value of the incoming row address and the current refresh flag value are the same, but may determine whether the difference between the flag value of the incoming row address and the current refresh flag value is less than or equal to the predetermined value. In some embodiments, when two bits are used as the flag, the predetermined value may be set to one. In some embodiments, when three or more bits are used as the flag, the predetermined value may be set to a value of one or more.

When the count value of the incoming row address reaches the first threshold in S530and the difference between the flag value of the incoming row address and the current refresh flag value is less than or equal to the predetermined value in S540, the refresh control circuit may put the incoming row address into the queue in S550. Further, the refresh control circuit may update the flag value of the incoming row address in S560and update the count value of the incoming row address in S570. For example, as shown inFIG.6, since the lowest nine bits of the count value (“101111111111”)611of the incoming row address RA1are “111111111”, the 10th bit of the count value611may be flipped, so the count value611of the incoming row address RA1may reach the first threshold. In this case, the flag value621of “11” of the incoming row address RA1may be equal to the current refresh flag value630of “11” (i.e., may be less than or equal to the predetermined value of one). Accordingly, the refresh control circuit may put the incoming row address RA1into the queue and increase the count value611of the counter of the incoming row address RA1to “110000000000”. In this way, when the difference between the flag values621and630is less than or equal to the predetermined value (for example, one), the refresh control circuit may determine that the row indicated by the incoming row address RA1is a row which has not been previously managed by the normal refresh, and may put the incoming row address RA1into the queue.

When receiving a target refresh command in S580, the refresh control circuit may determine a row address to be refreshed based on address information stored in the queue (i.e., addresses stored in queue) in S590. The refresh control circuit may extract the row address from the queue, and determine a victim row address based on the extracted row address at S590.

FIG.7is a block diagram showing an example of a memory device according to example embodiments.

Referring toFIG.7, a memory device700may include a refresh control circuit710, a plurality of counters720, a plurality of flags730, and a queue740. In some embodiments, the refresh control circuit710ofFIG.7may correspond to a targeted refresh control circuit (e.g.,291ofFIG.2).

The counters720may correspond to a plurality of rows of a memory cell array, respectively. Each counter720may count the number of accesses to a corresponding row and store a count value, and may have a plurality of bits. The flags730may correspond to the rows of the memory cell array, respectively. Each flag730may store a flag value of a corresponding row, and may have a plurality of bits.

The refresh control circuit710may include comparing circuits711,712, and713, and a control logic circuit714. In response to a row operation command such as an activation command ACT or a precharge command PRE, the refresh control circuit710may receive a counter value from a target counter720corresponding to a target row indicated by an incoming row address RA among the counters720, and receive a flag value from a target flag730corresponding to the target row among the flags730, under a control of the memory device700.

The comparing circuit711may compare the count value of the target counter720with a first threshold TH1, and the comparing circuit712may compare the count value of the target counter720with a second threshold TH2. The second threshold TH2may be smaller than the first threshold TH1. The comparing circuit713may compare the flag value of the target flag730with a flag value of a refresh flag715set in a current refresh period. The control logic circuit714may determine whether to put the incoming row address RA into the queue740based on comparison results of the comparing circuits711,712, and713. The control logic circuit714may change the flag value of the refresh flag715every refresh period. The memory device700may update (i.e., increase) the count value of the target counter720when the incoming row address RA is received.

The control logic circuit714may perform an operation of putting the incoming row address into the queue740, an operation of updating the flag value of the target flag730, or an operation of maintaining the flag value of the target flag730without updating it, based on a condition satisfied by the comparison results of the comparing circuits711,712, and713among a plurality of conditions. When updating the flag value of the target flag730, the control logic circuit714may update the flag value of the target flag730to be equal to the flag value of the refresh flag715set in the current refresh period.

When the comparison results of the comparing circuits711,712, and713satisfy a first condition, the control logic circuit714may put the incoming row address RA into the queue740and may update the flag value of the target flag730. When the comparison results of the comparing circuits711,712, and713satisfy a second condition, the control logic circuit714may not put the incoming row address RA into the queue740and may update the flag value of the target flag730. When the comparison results of the comparing circuits711,712, and713satisfy a third condition, the control logic circuit714may not put the incoming row address RA into the queue740and may maintain the flag value of the target flag730.

In some embodiments, the first condition may include a condition in which the comparison result of the comparing circuit711indicates that the count value is equal to the first threshold TH1, and the comparison result of the comparing circuit713indicates that a difference between the flag value of the target flag730and the flag value of the refresh flag715is less than or equal to a predetermined value. The second condition may include a condition in which the comparison result of the comparing circuit712indicates that the count value is equal to or less than the second threshold TH2. The third condition may include a condition in which the comparison result of the comparing circuit711indicates that the count value is less than the first threshold TH1, and the comparison result of the comparing circuit712indicates that the count value is greater than the second threshold TH2, or a condition in which the comparison result of the comparing circuit711indicates that the count value is equal to the first threshold TH1, and the comparison result of the comparing circuit713indicates that the difference between the flag value of the target flag730and the flag value of the refresh flag715is greater than the predetermined value.

In some embodiments, the comparing circuits711and712may compare predetermined bits of the count value with the first threshold TH1or the second threshold TH2. The predetermined bits may be, for example, a predetermined number of least significant bits.

FIG.8is a diagram showing an example of a memory cell array of a memory device according to an embodiment.

Referring toFIG.8, a memory cell array800may include a plurality of rows RL1, RL2, . . . , and RLn, and each row RLimay include a plurality of memory cells MC. Here, n indicates the number of rows, n is an integer greater than 1, and i is an integer between 1 and n. In each row RLi, the memory cells MC may include a first group of memory cells810i, a second group of memory cells820i, and a third group of memory cells830i. The first group of memory cells810imay be used to store data. The second group of memory cells820imay be used as a counter of the corresponding row RLi, and the third group of memory cells830imay be used as a flag of the corresponding row RLi. The number of memory cells belonging to the second group of memory cells820imay be determined based on a maximum count value of the counter, and the number of memory cells belonging to the third group of memory cells830imay be determined based on the number of bits of the flag. For example, as in an example shown inFIG.6, when twelve bits are used as the count value and two bits are used as the flag, the second group of memory cells820imay include twelve memory cells MC, and the third group of memory cells830imay include two memory cells MC.

Accordingly, a memory device may manage the number of accesses for all rows RL1to RLnof the memory cell array800through the counter8201formed in each row RLi, and the flag values of all rows RL1to RLnthrough the flag8301formed in each row RLi.

FIG.9is a block diagram showing an example of a computing device according to an embodiment.

Referring toFIG.9, a computing device900may include a processor910, a memory920, a memory controller930, a storage device940, a communication interface950, and a bus960. The computing device900may further include other components.

The processor910may control an overall operation of each component of the computing device900. The processor910may be implemented with at least one of various processing units such as a central processing unit (CPU), an application processor (AP), and a graphic processing unit (GPU).

The memory920may store various data and instructions. The memory920may be implemented with the memory device described with reference toFIG.1toFIG.8. The memory controller930may control transfers of data or instructions to and from the memory920. The memory controller930may be implemented with the memory controller described with reference toFIG.1toFIG.8. In some embodiments, the memory controller930may be provided as a separate chip from the processor910. In some embodiments, the memory controller930may be provided as an internal component of the processor910.

The storage device940may non-temporarily store programs and data. In some embodiments, the storage device940may be implemented as a non-volatile memory. The communication interface950may support wired or wireless Internet communication of the computing device900. In addition, the communication interface950may support various communication methods other than Internet communication. The bus960may provide a communication function between the components of the computing device1400. The bus960may include at least one type of bus according to a communication protocol between the components.

In some embodiments, each of the components, elements, modules, or units represented by a block as illustrated inFIG.1toFIG.8may be implemented as various numbers of hardware, software, and/or firmware structures that execute respective functions described above, according to embodiments. For example, at least one of these components, elements, modules, or units may include various hardware components including a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or other circuitry using a digital circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc., that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Further, at least one of these components, elements, modules, or units may include a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Furthermore, at least one of these components, elements, modules, or units may further include or may be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Functional aspects of embodiments may be implemented in algorithms that execute on one or more processors.

While this invention has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.