Patent ID: 12189256

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present disclosure.

Referring toFIG.2andFIG.3,FIG.2shows a schematic diagram of a pixel according to a first embodiment of the present disclosure, andFIG.3shows an equivalent circuit diagram of the pixel ofFIG.2. The pixel100is arranged at an intersection of a data line111and a scan line120. The data line111is arranged along a vertical direction, and the scan line120is arranged along a horizontal direction. The pixel100includes a first sub-pixel101and a second sub-pixel102arranged along the horizontal direction. The first sub-pixel101and the second sub-pixel102are connected to the same data line110and the same scan line120. Furthermore, the first sub-pixel101is connected to the first common electrode line131, and the second sub-pixel102is connected to the second common electrode line132. The first common electrode line131and the second common electrode line132are arranged along the horizontal direction and are arranged on opposite sides of the scan line120.

As shown inFIG.2andFIG.3, the first sub-pixel101includes a first driving transistor1011, a first pixel electrode1012, a first storage capacitor1013, and a first liquid crystal capacitor1014. A gate of the first driving transistor1011is connected to the scan line120. One of a source and a drain of the first driving transistor1011is connected to the data line110. Another one of the source and the drain of the first driving transistor1011is connected to the first pixel electrode1012, and is connected to the first common electrode line131through the first storage capacitor1013. That is, one end of the first storage capacitor1013is connected to the first common electrode line131, and another end of the first storage capacitor1013is connected to the another one of the source and the drain of the first driving transistor1011. One end of the first liquid crystal capacitor1014is connected to an opposite electrode107of an opposite substrate, and another end of the first liquid crystal capacitor1014is connected to the another one of the source and the drain of the first driving transistor1011.

As shown inFIG.2andFIG.3, the second sub-pixel102includes a second driving transistor1021, a second pixel electrode1022, a second storage capacitor1023, and a second liquid crystal capacitor1024. A gate of the second driving transistor1021is connected to the scan line120. One of a source and a drain of the second driving transistor1021is connected to the data line110. Another one of the source and the drain of the second driving transistor1021is connected to the second pixel electrode1022, and is connected to the second common electrode line132through the second storage capacitor1023. That is, one end of the second storage capacitor1023is connected to the second common electrode line132, and another end of the second storage capacitor1023is connected to the another one of source and the drain of the second driving transistor1021. One end of the second liquid crystal capacitor1024is connected to the opposite electrode107of the opposite substrate, and another end of the second liquid crystal capacitor1024is connected to the another one of the source and the drain of the second driving transistor1021.

As shown inFIG.2andFIG.3, the pixel100also includes a common transistor103. A gate of the common transistor103is connected to the scan line120. One of a source and a drain of the common transistor103is connected to the first common electrode line131. Another one of the source and the drain of the common transistor103is connected to the second common electrode line132. Specifically, the pixel100further includes a first connecting electrode1051, a second connecting electrode1052, a first via hole1061, and a second via hole1062. The first connecting electrode1051is disposed on the scan line120and extends to overlap with the first common electrode line131. The second connecting electrode1052is disposed on the scan line120and extends to overlap with the second common electrode line132. The first via hole1061is formed at an overlap portion of the first connecting electrode1051and the first common electrode line131, and exposes the first common electrode line131. The first connecting electrode1051is connected to the first common electrode line131through the first via hole1061. The second via hole1062is formed at an overlap portion of the second connecting electrode1052and the second common electrode line132, and exposes the second common electrode line132. The second connecting electrode1052is connected to the second common electrode line132through the second via hole1062. The first connection electrode1051and the second connection electrode1052are separated from each other where they overlap with the scan line120, and together form the common transistor103.

As shown inFIG.2andFIG.3, in this embodiment, when a positive signal is applied to the scan line120, the common transistor103is turned on, and the first common electrode line131and the second common electrode line132are electrically connected, thereby ensuring the stability of a common voltage. In addition, when a signal detection process is performed, a negative signal is applied to the scan line120, and a positive signal is applied to other lines. At this time, the common transistor103is turned off, and the first common electrode line131and the second common electrode line132are electrically separated from each other. If a short circuit occurs between the common electrode line and the data line110or a shared electrode line140, the lines in the horizontal direction can be located according to an acquired short circuit signal, and the defect lines can be further repaired.

As shown inFIG.2andFIG.3, the pixel100further includes a shared transistor104. A gate of the shared transistor104is connected to the scan line120. One of a source and a drain of the shared transistor104is connected to the another one of the source and the drain of the second driving transistor1021. Another of the source and the drain of the shared transistor104is connected to the shared electrode line140. The shared electrode line140is arranged between two adjacent data lines110. The shared electrode line140extends from the first sub-pixel101to the second sub-pixel102along the vertical direction. The first driving transistor1011is configured to drive the first sub-pixel101. The second driving transistor1021is configured to drive the second sub-pixel102. The shared transistor104is configured to release the charge in the second sub-pixel102. Specifically, when the shared transistor104is turned on, part of the charge in the second sub-pixel102is released into the shared transistor104. As a result, there is a potential difference between the first sub-pixel101and the second sub-pixel102, and tilt angles of liquid crystal molecules are different, thereby reducing a color shift.

Referring toFIG.4, which shows an equivalent circuit diagram of a pixel according to a second embodiment of the present disclosure. A pixel200is arranged at an intersection of a data line211and a scan line220. The data line211is arranged along a vertical direction, and the scan line220is arranged along a horizontal direction. The pixel200includes a first sub-pixel and a second sub-pixel arranged along the horizontal direction. The first sub-pixel and the second sub-pixel are connected to the same data line210and the same scan line220. Furthermore, the first sub-pixel is connected to a first common electrode line231, and the second sub-pixel is connected to a second common electrode line232. The first common electrode line231and the second common electrode line232are arranged along the horizontal direction, and are arranged on opposite sides of the scan line220.

As shown inFIG.4, the first sub-pixel includes a first driving transistor2011, a first pixel electrode, a first storage capacitor2013, and a first liquid crystal capacitor2014. The second sub-pixel includes a second driving transistor2021, a second pixel electrode, a second storage capacitor2023, and a second liquid crystal capacitor2024. One ends of the first liquid crystal capacitor2014and the second liquid crystal capacitor2024are connected to an opposite electrode207of an opposite substrate. The pixel200also includes a common transistor203and a shared transistor204. One of a source and a drain of the shared transistor204is connected to a shared electrode line240. The pixel200of the second embodiment is substantially the same as the pixel100of the first embodiment. A difference between the two is that a gate of the common transistor203of the pixel200of the second embodiment is connected to the second common electrode line232. In some embodiments, the gate of the common transistor can also be connected to the first common electrode line.

As shown inFIG.4, in this embodiment, when a positive signal is applied to the first common electrode line231and the second common electrode line232, the common transistor203is turned on, and the first common electrode line231and the second common electrode line232are electrically connected, thereby ensuring the stability of a common voltage. In addition, when a signal detection process is performed, a negative signal is applied to the first common electrode line231and the second common electrode line232, and a positive signal is applied to other lines. At this time, the common transistor203is turned off, and the first common electrode line231and the second common electrode line232are electrically separated from each other. If a short circuit occurs between the common electrode line and the data line210or the shared electrode line240, the lines in the horizontal direction can be located according to an acquired short circuit signal, and the defect lines can be further repaired. On the other hand, the design of other elements in the pixel200of the second embodiment is the same as that of the first embodiment, and will not be repeated here.

Referring toFIG.5, which shows a schematic diagram of an array substrate according to an embodiment of the present disclosure. An array substrate50includes a plurality of data lines511, a plurality of scan lines521, a plurality of common electrode lines541, a plurality of shared electrode lines551, and a plurality of pixels. The plurality of data lines511and the plurality of shared electrode lines551extend along a vertical direction. The plurality of scan lines521and the plurality of common electrode lines541extend along the horizontal direction. The plurality of data lines511and the plurality of scan lines521intersect with each other and define a plurality of pixel regions53. The plurality of pixels are arranged in an array and disposed in the pixel regions53. The pixel in this embodiment can be any of the above-mentioned pixels, and will not be repeated here.

As shown inFIG.5, the array substrate50also includes a data driver51, a scan driver52, a common electrode bus line54, and a shared electrode bus line55. The plurality of data lines511are connected to the data driver51. The plurality of scan lines521are connected to the scan driver52. The plurality of common electrode lines541are connected to the common electrode bus line54. The plurality of shared electrode lines551are connected to the shared electrode bus line55.

Referring toFIG.6, which shows a schematic diagram of a display device according to an embodiment of the present disclosure. The display device60includes an array substrate61, an opposite substrate62, and a liquid crystal layer63. The array substrate61includes any of the above-mentioned array substrates and pixels, and details are not described herein. The opposite substrate62is opposite to the array substrate61and includes an opposite electrode621. The liquid crystal layer63is disposed between the array substrate61and the opposite substrate62.

In the present disclosure, the first common electrode line and the adjacent second common electrode line are connected through the common transistor. When the common transistor is turned on, the first common electrode line and the second common electrode line are electrically connected, thereby ensuring the stability of the common voltage. In addition, when a signal detection process is performed, the common transistor is turned off, so that the lines in the horizontal direction can be located according to the acquired short-circuit signal, and the defect lines can be further repaired.

The pixel, the array substrate, and the display device of the embodiments of the present disclosure are described in detail above. Specific embodiments are used in this document to describe the principle and implementations of the present disclosure. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present disclosure. Those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or equivalently replace some of the technical features. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.