Patent ID: 12191373

DETAILED DESCRIPTION

Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. The same reference numerals or the same reference designators may denote the same elements or components throughout the specification.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being “on”, “attached” to, “connected” to, “coupled” with, “contacting”, etc., another element, it can be directly on, attached to, connected to, coupled with or contacting the other element or intervening elements may also be present. In contrast, when an element is referred to as being, for example, “directly on”, “directly attached” to, “directly connected” to, “directly coupled” with or “directly contacting” another element, there are no intervening elements present. It is noted that aspects described with respect to one embodiment may be incorporated in different embodiments although not specifically described relative thereto. That is, all embodiments and/or features of any embodiments can be combined in any way and/or combination.

FIG.1is a plan diagram illustrating a semiconductor device according to an example embodiment.

FIG.2Ais a cross-sectional diagram illustrating a semiconductor device taken along lines I-I′ and II-II′ ofFIG.1according to an example embodiment.FIG.2Bis an enlarged diagram illustrating region A inFIG.2A.

Referring toFIGS.1to2B, a semiconductor device100A may include a substrate101, an active region105on the substrate101, source/drain regions150on the active region105, a gate structure160intersecting the active region105and extending thereacross, and contact patterns180connected to the source/drain regions150. The semiconductor device100A may further include device separation layers110, a first insulating layer172, a second insulating layer176, and a third insulating layer178. The gate structure160may include a gate dielectric layer164, a gate electrode165, a gate capping layer166, and a plurality of spacers.

A fin-type transistor (FinFET) including a fin-type channel region is illustrated as an example embodiment of the inventive concept, but example embodiments thereof are not limited thereto. Semiconductor devices in the example embodiments may include, but are not limited to, a tunneling field effect transistor (tunneling FET), a transistor including a nanowire, a transistor including a nanosheet (multi bridge channel FET, (MBCFET™)) or a three-dimensional (3D) transistor.

The substrate101may have an upper surface extending in an x direction and a y direction. The substrate101may include, for example, a group IV semiconductor, a group III-V compound semiconductor, and/or a group II-VI compound semiconductor. For example, a group IV semiconductor may include one or more of silicon, germanium, silicon-gallium, or the like. The substrate101may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator layer (SOI), or a semiconductor on insulator layer (SeOI), or the like.

The device separation layer110may define the active region105on the substrate101. For example, the device separation layer110may be formed by using a shallow trench isolation (STI) process. In example embodiments, the device separation layer110may further include a region having a stepped portion and extending to a lower portion of the substrate101. The device separation layer110may partially expose an upper portion of the active region105. In example embodiments, the device separation layer110may have a curved upper surface having a higher level (relative to the substrate101being a base reference level) towards the active region105. The device separation layer110may be formed of an insulating material. For example, the device separation layer110may be formed of an oxide, a nitride, or a combination thereof.

The active region105may be defined by the device separation layers110in the substrate101, and may extend in a first direction, the x direction, for example. The active region105may be configured to protrude from the substrate101. An upper end of the active region105may be configured to protrude at a defined height from an upper surface of the device separation layers110. The active region105may be configured as a portion of the substrate101, or may include an epitaxial layer grown from the substrate101. A portion of the active region105on the substrate101may be recessed on both sides of the gate structure160, and the source/drain regions150may be disposed on the recessed active region105. The active region105may include impurities or doping regions including impurities.

The source/drain regions150may be disposed on the active region105on both sides of the gate structure160. The source/drain regions150may be provided as a source region or a drain region of the semiconductor device100A. A height of an upper surface of each of the source/drain regions150(relative to the substrate101being a base reference level) may be the same as a height of an uppermost end of the active region105(relative to the substrate101being a base reference level), but example embodiments thereof are not limited thereto. A height of an upper surface of each of the source/drain regions150(relative to the substrate101being a base reference level) may vary in example embodiments. In another example embodiment, each of the source/drain regions150may have an elevated form in which an upper surface thereof is disposed on a level higher than a lower surface of the gate electrode165(relative to the substrate101being a base reference level), but example embodiments thereof are not limited thereto. In an example embodiment, each of the source/drain regions150may have a width decreasing from an upper portion to a lower portion, and a lower surface of each of the source/drain regions150may have a “U”-shape. However, example embodiments thereof are not limited thereto, and the source/drain regions150may have various other shapes. For example, each of the source/drain regions150may have a polygonal shape or a circular shape.

The source/drain regions150may include silicon or silicon germanium (SiGe). The source/drain regions150may be formed of epitaxial layers. For example, when the source/drain regions150include silicon-gallium (SiGe), the source/drain regions150may apply stress to a channel region of the semiconductor device100A, one region of the active region105formed of silicon (Si), such that mobility of a hole may improve. In example embodiments, the source/drain regions150may include a plurality of regions including elements and/or doped elements having different concentrations.

The gate structure160may intersect the active region105and may extend in one direction, the y direction, for example, in an upper portion of the active region105. Channel regions of transistors may be formed in the active region105intersecting the gate structure160. The gate structure160may include a gate dielectric layer164, a gate electrode165on the gate dielectric layer164, a gate capping layer166on the gate electrode165, and a plurality of spacers on a side surface of the gate electrode165. The plurality of spacers may include a first spacer161on each side surface of the gate electrode165, an air-gap spacer169on an external side surface of the first spacer161, a second spacer162on an external side surface of the air-gap spacer169, and a third spacer163on an external side surface of the second spacer162.

The gate dielectric layer164may be disposed between the active region105and the gate electrode165. In an example embodiment, the gate dielectric layer164may only be disposed on a lower surface of the gate electrode165with other surface areas of the gate electrode165being free of the gate dielectric layer164, but example embodiments thereof are not limited thereto. The gate dielectric layer164may be on and at least partially cover a lower surface and both side surfaces of the gate electrode165. The gate dielectric layer164may include an oxide, a nitride, and/or a high-k material. The high-k material may refer to a dielectric material having a dielectric constant higher than a silicon oxide film (SiO2). Examples of high-k materials may include, but are not limited to, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3), for example.

The gate electrode165may be disposed in an upper portion of the active region105, and may have a line form extending in the y direction. The gate electrode165may have a first height H1(seeFIG.2B) from the gate dielectric layer164to the gate capping layer166. The first height H1may be configured to be lower than or not to extend to a point at which the second spacer162is bent. The gate electrode165may include a conductive material. For example, the gate electrode165may include one or more metal nitride materials, such as, but not limited to, a titanium nitride film (TiN), a tantalum nitride film (TaN), and a tungsten nitride film (WN), and/or one or more metal materials such as, but not limited to, aluminum (Al), tungsten (W), molybdenum (Mo), and the like, and/or one or more semiconductor materials, such as, but not limited to, a doped polysilicon. The gate electrode165may include multiple layers, i.e., two or more layers. The gate electrodes165may be separated from each other by a separation portion between at least some of adjacent transistors in accordance with the example configuration of the semiconductor device100A.

The gate capping layer166may be disposed in an upper portion of the gate electrode165, and a lower surface and side surfaces thereof may be surrounded by the gate electrode165and the plurality of spacers161,162,163, and169. The gate capping layer166may include a material having tensile stress. Tensile stress of the gate capping layer166will be described below with reference toFIG.2C.

The plurality of spacers161,162,163, and169may be disposed on both side surfaces of the gate electrode165. The plurality of spacers161,162,163, and169may insulate the source/drain regions150and the gate electrode165from each other. In example embodiments, the plurality of spacers161,162,163, and169may further include one or more other spacers in addition to the first spacer161, the second spacer162, the third spacer163, and the air-gap spacer169.

The first spacer161may be disposed between the gate electrode165and the air-gap spacer169, the second spacer162may be disposed between the air-gap spacer169and the third spacer163, and the third spacer163may be disposed between the second spacer162and the first insulating layer172. Each of the first to third spacers161,162, and163may have a line form extending in the y direction. In an example embodiment, each of the first to third spacers161,162, and163may have a width increasing from an upper portion to a lower portion. A width of each of the first to third spacers161,162, and163may be 100 Å or less, but example embodiments thereof are not limited thereto.

The first to third spacers161,162, and163may be formed of an oxide, a nitride, and/or an oxide nitride, and may be configured as a multilayer film. The first to third spacers161,162, and163may include a low-k material. For example, the first to third spacers161,162, and163may include SiC, SiN, SiO, SiCN, SiOC, and/or SiOCN. In another example embodiment, at least one of the first to third spacers161,162, and163may include one or more of a polyimide, a polyarylene ether (PAE), SiLK™, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), Black Diamond™, fluorine-doped silicate glass (FSG), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and the like. As the first to third spacers161,162, and163may include a low-k material, capacitance between the gate electrode165and contact plugs185may decrease.

The air-gap spacer169may be defined as an empty space surrounded by the first spacer161, the second spacer162, and the active region105. The air-gap spacer169may have a spacer shape. The air-gap spacer169may be disposed between the first spacer161and the second spacer162, and may have a line form extending in the y direction. In example embodiments, the air-gap spacer169may be defined as an empty space surrounded by the first spacer161, the second spacer162, and the substrate101.

An upper portion of the second spacer162may be bent towards an upper portion of the first spacer161to cap and seal the air-gap spacer169. An upper portion of the third spacer163may be bent towards the upper portion of the first spacer161to conform to a shape of the upper portion of the second spacer162. The upper portion of the second spacer162may be in physical contact with the upper portion of the first spacer161on a contact surface S. A lowermost end of the contact surface S may be disposed on a level higher than an upper surface of the gate electrode165(relative to the substrate101being a base reference level). In an example embodiment, the contact surface S may include a first contact surface and a second contact surface on both sides of the gate electrode165, for example, and the first and second contact surfaces may be disposed on different levels from a lower surface of the gate electrode165(relative to the substrate101being a base reference level).

A first width W1of an upper portion169U of the air-gap spacer169may be less than a second width W2of a lower portion169L, and a width of the air-gap spacer169may have a value within a range of approximately 40 Å to 60 Å. The upper portion169U of the air-gap spacer169may have a shape bent towards the gate electrode165. In an example embodiment, a shape of the air-gap spacer169is not limited to the example illustrated in the diagram, and when the upper portion169U of the air-gap spacer169is capped by the first and second spacers161and162, a shape of the air-gap spacer169below the capped region may vary. For example, the air-gap spacer169may have a width increasing from an upper portion to a lower portion, or may have a minimum width in an upper portion and a maximum width in a middle portion, but example embodiments thereof are not limited thereto.

In example embodiments, as the semiconductor device100A includes the air-gap spacer169between the first spacer161and the second spacer162, electrical insulating properties of the gate structure160may improve. Particularly, parasitic capacitance may be reduced, and, accordingly, operation speed of the semiconductor device may increase.

The first insulating layer172may be on and at least partially cover the source/drain regions150, and may be on and at least partially cover the device separation layer110in a region not illustrated. The first insulating layer172may be disposed on at least one side of the gate structure160, and may be in physical contact with an outermost spacer of the plurality of spacers. The first insulating layer172may include an oxide, a nitride, and/or an oxide nitride, and may include a low-k material.

The second insulating layer176may be disposed on the first insulating layer172, may be disposed on at least one side of the gate structure160, and may be in physical contact with an outermost space of the plurality of spacers. An upper surface of the second insulating layer176may be disposed on a level substantially the same as that of upper surfaces of the plurality of spacers (relative to the substrate101being a base reference level). An upper surface of the second insulating layer176may be coplanar with an upper surface of the first spacer161, an upper surface of the second spacer162, an upper surface of the third spacer163, and an upper surface of the gate capping layer166. The second insulating layer176may include an oxide, a nitride, and/or an oxide nitride, and may include a low-k material.

The first and second insulating layers172and176may have different properties. In an example embodiment, the second insulating layer176may have a density greater than that of the first insulating layer172. For example, the second insulating layer176may include a silicon oxide having a density greater than a density of the first insulating layer172. In an example embodiment, the first and second insulating layers172and176may include a silicon oxide, and the first insulating layer172may also include one or more of SiH, SiC, or the like, such that the first insulating layer172may have an oxygen atomic fraction less than that of the second insulating layer176.

The third insulating layer178may be on and at least partially cover the first to third spacers161,162, and163, the gate capping layer166, and the second insulating layer176. The third insulating layer178may include an oxide, a nitride, and/or an oxide nitride, and may include a low-k material.

The contact patterns180may include a metal semiconductor film182and contact plugs185. The metal semiconductor film182may be disposed between the source/drain regions150and the contact plugs185. The metal semiconductor film182may include a metal silicide, a metal germanide, and/or a metal silicide-germanide, and the metal may comprise titanium (Ti), nickel (Ni), tantalum (Ta), cobalt (Co), and/or tungsten (W). The contact plugs185may penetrate the first to third insulating layers172,176, and178, may be connected to the source/drain regions150, and may apply an electrical signal to the source/drain regions150. The contact plugs185may be disposed on the source/drain regions150as illustrated inFIG.1, and in example embodiments, the contact plugs185may have a length longer than a length of each of the source/drain regions150in the y direction. The contact plugs185may have inclined side surfaces, a width of a lower portion of which is narrower than a width of an upper portion, in accordance with an aspect ratio, but example embodiments thereof are not limited thereto. The contact plugs185may be in contact with the source/drain regions150by recessing a portion of the source/drain regions150, and a depth of the recessed portion may vary in example embodiments. In example embodiments, a lower surface of each of the contact plugs185may extend downwardly farther than an upper surface of the active region105. Alternatively, in example embodiments, the contact plugs185may be in physical contact with an upper surface of the source/drain region150without recessing the source/drain region150. The contact plugs185may include one or more metal nitride materials, such as, but not limited to, a titanium nitride film (TiN), a tantalum nitride film (TaN), and/or a tungsten nitride fiml (WN), and/or a metal material, such as, but not limited to, aluminum (Al), tungsten (W), and/or molybdenum (Mo).

FIG.2Cis an enlarged diagram illustrating a portion of a semiconductor device, denoted as region B inFIG.2A, according to an example embodiment.FIG.2Cis a diagram illustrating stress applied to a plurality of spacers161,162,163, and169between a gate capping layer166and a second insulating layer176.

Referring toFIG.2C, the plurality of spacers161,162,163, and169may form a capping region R between the gate capping layer166and the second insulating layer176. The gate capping layer166and the second insulating layer176may have tensile stress to apply compressive stress to the plurality of spacers161,162,163, and169. The “tensile stress” may refer to stress pushing the plurality of spacers161,162,163, and169in a first force F1direction by the gate capping layer166or stress pushing the plurality of spacers161,162,163, and169in a second force F2direction by the second insulating layer176. For example, the gate capping layer166may include nitride having tensile stress, and may push the first spacer161in the direction of the first force F1. The second insulating layer176may include silicon oxide having high density and tensile stress, and may push the third spacer136in the direction of the second force F2. Due to the second insulating layer176, the second and third spacers162and163may maintain a bent structure, which is bent towards the first spacer161.

In example embodiments, due to the stress relationship, shapes of the plurality of spacers161,162,163, and169or the shape of the gate capping layer166may partially change in a capping region R. For example, one surface of the first spacer161in contact with the gate capping layer166may have a rounded shape, curved inwardly towards the air-gap spacer169, but example embodiments thereof are not limited thereto.

Through the first force F1of the gate capping layer166and the second force F2of the second insulating layer176, compressive stress may be applied to the plurality of spacers161,162,163, and169. In example embodiments, compressive stress may be applied to the first to third spacers161,162, and163so as not to externally expose an upper portion169U of the air-gap spacer169capped by the first to third spacers161,162, and163, such that capping stability of the air-gap spacer169may improve. Accordingly, a structure of the capping region R of the air-gap spacer169may be maintained, such that insulating properties of the spacers may improve, and a semiconductor device having improved electrical properties may be provided.

FIG.3is a cross-sectional diagram illustrating a semiconductor device taken along line I-I′ ofFIG.1according to an example embodiment.

Referring toFIG.3, a semiconductor device100B may further include a liner layer174abetween a first insulating layer172and a second insulating layer176a. The liner layer174amay be disposed on at least one side of a gate structure160, and may be in physical contact with an outermost spacer of the plurality of spacers. The liner layer174amay also be disposed adjacent to a region in which an air-gap spacer169is capped by second and third spacers162and163. An uppermost portion of the liner layer174amay be disposed on a level substantially the same as that of an upper portion of the plurality of spacers (relative to the substrate101being a base reference level). An uppermost surface of the liner layer174amay be substantially coplanar with an upper surface of the first spacer161, an upper surface of the second spacer162, an upper surface of the third spacer163, an upper surface of the gate capping layer166, and an upper surface of the second insulating layer176a.

The liner layer174amay include a horizontal portion174aH in parallel to an upper surface of a substrate101, and an extended portion174aE connected to the horizontal portion174aH and bent towards the gate electrode165. Contact plugs185may penetrate the second insulating layer176a, the horizontal portion174aH of the liner layer174a, and the first insulating layer172and may be in physical contact with the source/drain regions150. The extended portion174aE may be in physical contact with an external side surface of the third spacer163.

The liner layer174amay apply compressive stress to the first to third spacers161,162, and163along with the second insulating layer176and may maintain a structure of the air-gap spacer169, such that the liner layer174amay improve capping stability. The liner layer174amay be comprise an oxide, a nitride, and/or an oxide nitride, and may include a low-k material. For example, the liner layer174amay include SiC, SiN, SiO, SiCN, SiOC, and/or SiOCN. The liner layer174amay not be limited to these example embodiments, but may also be implemented and/or used in other example embodiments.

FIG.4is a cross-sectional diagram illustrating a semiconductor device taken along line I-I′ ofFIG.1according to an example embodiment.

Referring toFIG.4, second and third spacers162aand163aof a semiconductor device100C may cap an air-gap spacer169and may have a shape extending farther in a z direction, and the semiconductor device100C may include a liner layer174bbetween a first insulating layer172and a second insulating layer176b. The air-gap spacer169may be disposed on a relatively lower level with reference to the second insulating layer176bin the cross-sectional view ofFIG.4, differently from some other example embodiments. A second spacer162amay further extend in a z direction along an external side surface of the first spacer161from a portion in which the second spacer162ais in contact with the first spacer161. A third spacer163amay further extend in the z direction along an external side surface of the second spacer162a. As a contact area between the second spacer162aand the first spacer161is greater than in some other example embodiments, and as a contact area between the third spacer163aand the liner layer174bis greater than in some other example embodiments, capping stability of the air-gap spacer169by compressive stress may improve.

A relative height of each of the second spacer162a, the third spacer163a, and the air-gap spacer169may vary in example embodiments. For example, a ratio between a length of one surface on which the second spacer162ais in contact with the first spacer161ain the z direction and a height of the air-gap spacer169may vary in example embodiments.

The liner layer174bmay include a horizontal portion174bH in parallel to an upper surface of the substrate101, and an extended portion174bE connected to the horizontal portion174bH and bent towards the gate electrode165. The extended portion174bE may further extend along an external side surface of the third spacer163afrom a portion in which the extended portion174bE is in contact with the third spacer163a. Further description of the liner layer174bmay be omitted in view of the above description of the liner layer174awith reference toFIG.3.

FIG.5is a cross-sectional diagram illustrating a semiconductor device taken along line I-I′ ofFIG.1according to an example embodiment.

Referring toFIG.5, second and third spacers162aand163aof a semiconductor device100D may cap an air-gap spacer169and may have a shape further extending in the z direction. The second spacer162amay further extend in the z direction along an external side surface of the first spacer161from a portion in which the second spacer162ais in contact with the first spacer161. The third spacer163amay further extend in the z direction along an external side surface of the second spacer162a. As the second and third spacers162aand163afurther extend in the z direction, the second insulating layer176cmay have a greater thickness in the z direction, in contrast with the example illustrated inFIG.2A. The second insulating layer176cmay apply compressive stress to the first to third spacers161,162, and163and may maintain a structure of the air-gap spacer169, such that capping stability may improve. As a contact area between the second spacer162aand the first spacer161may be greater than in some other example embodiments, and as a contact area between the third spacer163aand the second insulating layer176cmay be greater than in some other example embodiments, capping stability of the air-gap spacer169may improve.

FIG.6is a cross-sectional diagram illustrating a semiconductor device taken along line I-I′ ofFIG.1according to an example embodiment.

Referring toFIG.6, in a semiconductor device100E, a plurality of spacers may include a first spacer161, a second spacer162b, and an air-gap spacer169a, and an outermost spacer of the plurality of spacers may be the second spacer162b. Thus, in contrast with the example embodiments ofFIG.2A, the plurality of spacers may not include a third spacer163. The air-gap spacer169amay have a relatively wide width, and insulating properties of the spacer may improve, such that a semiconductor device having improved electrical properties may be provided.

In another example embodiment, liner layers174aand174bmay also be disposed between the first insulating layer172and the second insulating layer176, similar to the example embodiments ofFIGS.3and4, such that capping stability of the air-gap spacer169amay improve.

FIG.7is a cross-sectional diagram illustrating a semiconductor device taken along line I-I′ ofFIG.1according to an example embodiment.

Referring toFIG.7, a semiconductor device100F may further include a lower sacrificial spacer layer168disposed in a lower portion of an air-gap spacer169b. The lower sacrificial spacer layer168of a sacrificial spacer268(seeFIG.9) may not be etched by an etching process, which will be described with reference toFIG.10B, and may remain. The air-gap spacer169bmay be configured as an empty space surrounded by the first and second spacers161and162and the lower sacrificial spacer layer168. The lower sacrificial spacer layer168may be in physical contact with a lower portion of the first spacer161and a lower portion of the second spacer162, and a central portion of the lower sacrificial spacer layer168may have a rounded shape, curved inwardly towards a substrate101, but example embodiments thereof are not limited thereto.

In the example embodiment, the lower sacrificial spacer layer168may be disposed on a level lower than the first insulating layer172(relative to the substrate101being a base reference level), but example embodiments thereof are not limited thereto. In example embodiments, an uppermost end of the lower sacrificial spacer layer168in physical contact with the first spacer161or the second spacer162bmay be disposed on a level higher than a lower surface of the first insulating layer172(relative to the substrate101being a base reference level).

The lower sacrificial spacer layer168is illustrated inFIG.7, but example embodiments thereof are not limited thereto. In some other example embodiments, the lower sacrificial spacer layer168may be disposed in a lower portion of the air-gap spacer169.

FIG.8is a cross-sectional diagram illustrating a semiconductor device taken along lines I-I′ and II-II′ ofFIG.1according to an example embodiment.

Referring toFIG.8, a semiconductor device100G may include channel structures140including a plurality of channel layers141,142, and143vertically disposed on an active region105and spaced apart from each other. In the semiconductor device100G, the active region105may have a fin structure, and the gate electrode165may be disposed between the active region105and the channel structure140and among a plurality of channel layers141,142, and143of the channel structures140, and may be disposed in an upper portion of the channel structure140. Accordingly, the semiconductor device100G may be configured as a multi bridge channel FET (MBCFET™) formed by the channel structures140, source/drain regions150, and gate structures160.

The gate structure160may intersect the active region105and the channel structures140and may extend in the y direction in the active region105and on upper portions of the channel structures140. Channel regions of transistors may be formed in the active region105and the channel structures140intersecting the gate structure160. The gate structure160may include a gate electrode165, a gate dielectric layer164abetween the gate electrode165and the plurality of channel layers141,142, and143, a plurality of spacers161,162,163, and169on side surfaces of the gate electrode165, and a gate capping layer166on an upper surface of the gate electrode165. The gate electrode165may be in and at least partially fill a region among the plurality of channel layers141,142, and143and may extend to an upper portion of the channel structure140on an upper portion of the active region105. The gate electrode165may surround the plurality of channel layers141,142, and143. The gate electrode165may be spaced apart from the plurality of channel layers141,142, and143by the gate dielectric layer164a.

Internal spacers130may be disposed side by side with the gate electrode165between the channel structures140. The gate electrode165may be spaced apart from and electrically separated from the source/drain regions150by the internal spacers130in a lower portion of the third channel layer143. A side surface of the internal spacers130in physical contact with the gate electrode165may have a rounded shape, curved inwardly towards the gate electrode165, but example embodiments thereof are not limited thereto. The internal spacers130may comprise an oxide, a nitride, and/or an oxide nitride, and may be formed of a low-k film.

The channel structure140may include first to third channel layers141,142, and143, two or more channel layers spaced apart from one another in a direction perpendicular to an upper surface of the active region105, in the z direction, for example, on the active region105. The first to third channel layers141,142, and143may be connected to the source/drain region150and may be spaced apart from an upper surface of the active region105. Each of the first to third channel layers141,142, and143may have a width the same as or similar to a width of the active region105in the y direction, and may have a width the same as or similar to a width of the gate structure160in the x direction. In example embodiments, each of the first to third channel layers141,142, and143may have a reduced width, such that side surfaces thereof may be disposed in a lower portion of the gate structure160in the x direction.

The first to third channel layers141,142, and143may comprise a semiconductor material. For example, the first to third channel layers141,142, and143may include silicon (Si), silicon-gallium (SiGe), and/or germanium (Ge). The first to third channel layers141,142, and143may comprise the same material as that of the substrate101. In example embodiments, the first to third channel layers141,142, and143may include an impurity region disposed adjacent to the source/drain regions150. The number and shapes of the first to third channel layers141,142, and143included in a single channel structure140may vary in example embodiments. For example, in example embodiments, the channel structure140may further include a channel layer disposed on an upper surface of the active region105.

FIGS.9to15are diagrams illustrating processes of methods of manufacturing a semiconductor device according to example embodiments.

Among example processes for manufacturing a fin-type transistor (FinFET), example processes before forming an air-gap spacer will now be described. A trench, which defines the active region105, may be formed by patterning the substrate101. A process for configuring the active region105to protrude on the substrate101by burying the trench using an insulating material and partially removing a portion of the insulating material may be performed, thereby forming a device separation layer110. First and second sacrificial layers264and265, first to third preliminary spacers261,262, and263, and a sacrificial spacer268, intersecting the active region105and extending thereacross, may be formed. A recess may be formed by selectively removing the active region105on both sides of the third preliminary spacer263, and source/drain regions150may be formed on the recessed active region105.

Referring toFIGS.9and10A, a first preliminary insulating layer272may be formed on the source/drain regions150and a planarization process may be performed thereon. Upper portions of the first to third preliminary spacers261,262, and263, the second sacrificial layer265, the sacrificial spacer268, and the first preliminary insulating layer272may be substantially coplanar with one another. The sacrificial spacer268may include a material layer having a density lower than a density of the first preliminary insulating layer272, and may be formed of a material having etching selectivity with respect to the first to third preliminary spacers261,262, and263.

A recess having a designed depth may be formed by removing portions of the sacrificial spacer268and the first preliminary insulating layer272.

The sacrificial spacer268may be removed through selective etching using a wet etching process with respect to the first to third preliminary spacers261,262, and263. As the sacrificial spacer268is removed, a preliminary air-gap269may be formed between the first preliminary spacer261and the second preliminary spacer262. The sacrificial spacer268may include a material layer having a density lower than a density of the first preliminary insulating layer272, such that an etching speed of the sacrificial spacer268may be greater than that of the first preliminary insulating layer272, and, accordingly, etched depths thereof may be different.

The first preliminary insulating layer272may also be selectively etched with respect to the first to third preliminary spacers261,262, and263by using a wet-etching process, such that the first preliminary insulating layer272may be removed in greater amounts in a downward direction than an upper surface of the second sacrificial layer265by a designed depth. As the first preliminary insulating layer272is removed by a recess height RH, a first insulating layer172may be formed. In a subsequent process, the recess height RH may be configured based on a desired height of the gate electrode. A height of the air-gap spacer may also be configured based on the recess height RH.

Referring toFIG.10B, a lower portion of the sacrificial spacer268may not be removed by the etching process and may remain, thereby forming a lower sacrificial spacer layer168. A central portion of the lower sacrificial spacer layer168may be etched further than portions of the lower sacrificial spacer layer168adjacent to side surfaces of each of the first and second preliminary spacers261and262. The lower sacrificial spacer layer168may have a rounded shape, curved inwardly towards the substrate101.

Referring toFIG.11, a preliminary liner layer274may be formed to cap an air-gap spacer169by bending a second preliminary spacer262aand a third preliminary spacer263atowards a first preliminary spacer261.

The preliminary liner layer274may be on and at least partially cover a first insulating layer172, first to third preliminary spacers261,262, and263, and a second sacrificial layer265, and may be formed conformally. The second and third preliminary spacers262aand263amay be bent towards the first preliminary spacer261from a level the same as an upper surface of the first insulating layer172. The second preliminary spacer262amay be in physical contact with one region of the first preliminary spacer261sdisposed at a first gate height GH1from an upper surface of the first sacrificial layer264. The preliminary liner layer274may be configured as a compressive layer formed based on one or more process variations, such as, but not limited to, a deposition temperature, a deposition time, a deposition method, a material, a density of a material, and the like.

In some example embodiments, as the air-gap spacer169may be capped by the preliminary liner layer274without an additional deposition process for forming a capping layer for capping the air-gap spacer169, fabrication process complexity and costs may be reduced. When the air-gap spacer169is capped through an additional deposition process for forming the capping layer, it may be difficult to maintain a constant or consistent shape of the air-gap spacer169, but in some example embodiments, as the preliminary liner layer274is formed generally uniformly, the air-gap spacer169may have a generally uniform structure. When the preliminary liner layer274is a compressive layer, a device structure may be maintained so as to not externally expose the air-gap spacer169, and capping stability may improve.

In some other example embodiments, the air-gap spacer169may be capped by forming a second insulating layer without performing the process for forming the preliminary liner layer274, and the second insulating layer may be formed by forming the preliminary liner layer274and removing the preliminary liner layer274, but example embodiments thereof are not limited thereto.

Referring toFIG.12, the second preliminary insulating layer276may be formed and a planarization process may be performed, and thereafter, the first and second sacrificial layers264and265may be removed, thereby forming a first opening OP1.

The second preliminary insulating layer276may be formed on and may at least partially cover the first insulating layer172and the second sacrificial layer265, and a planarization process may be performed. The planarization process may be performed until an upper surface of the second sacrificial layer265is exposed or free of the preliminary liner layer274. In some example embodiments, before forming the second preliminary insulating layer276, the preliminary liner layer274may be removed.

The first and second sacrificial layers264and265, sacrificial gate structures, may be removed. The first and second sacrificial layers264and265may be selectively removed with respect to device separation layers110and the active region105, disposed in a lower portion, thereby forming the first opening OP1exposing the device separation layers110and the active region105so that they are at least partially free of layers thereon. The process for removing the first and second sacrificial layers264and265may include a dry etching process and/or a wet etching process.

In other example embodiments, the second preliminary insulating layer276may be on and at least partially cover the preliminary liner layer274. The second preliminary insulating layer276may be formed on and to at least partially cover an upper portion of the preliminary liner layer274disposed on the second sacrificial layer265, and a planarization process may be performed until an upper surface of the second sacrificial layer265is exposed, such that a portion thereof may be removed.

Referring toFIG.13, a gate dielectric layer164and a preliminary gate electrode165amay be formed in the first opening OP1.

The gate dielectric layer164may be formed conformally along a lower surface of the first opening OP1. The gate dielectric layer164may include an oxide, a nitride, an oxide nitride, and/or a high-k material. The preliminary gate electrode165ais in and may completely fill an internal space of the first opening OP1on the gate dielectric layer164. The preliminary gate electrode165amay include a metal and/or a semiconductor material.

After forming the gate dielectric layer164and the preliminary gate electrode165a, the preliminary gate electrode165amay be planarized so as to have a second gate height GH2in the z direction from the gate dielectric layer164. The second preliminary insulating layer276may also be planarized, and the second insulating layer176may be formed. An upper surface of the second insulating layer176may be substantially coplanar with an upper surface of the preliminary gate electrode165a. An upper surface of the second insulating layer176may be substantially coplanar with an upper surface of the first spacer161, an upper surface of the second spacer162, and an upper surface of the third spacer163. An upper surface of the preliminary gate electrode165amay be disposed on a level higher than at least a region in which the air-gap spacer169bis capped (relative to the substrate101being a base reference level). Referring toFIG.11, the second gate height GH2may be higher than the first gate height GH1(relative to the substrate101being a base reference level).

Referring toFIG.14, an upper portion of the preliminary gate electrode165amay be removed down to a designed depth, such that a gate electrode165may be formed. A gate capping layer166may be formed in a region from which the preliminary gate electrode165awas removed.

The gate electrode165may have a third gate height GH3. The third gate height GH3may vary based on a recess height RH (seeFIG.10A), and a height of the gate electrode165may be configured to be lower than the first gate height GH1of the gate electrode in which the air-gap spacer169is capped by adjusting the recess height RH (relative to the substrate101being a base reference level).

As described in the above described example embodiments with reference toFIG.2C, the gate capping layer166may have tensile stress and may apply compressive stress to the plurality of spacers161,162,163, and169. For example, the gate capping layer166may comprise a nitride having tensile stress.

Referring toFIG.15, the third insulating layer178may be formed on and to at least partially cover the gate capping layer166and the second insulating layer176, and a second opening OP2penetrating the first to third insulating layers172,176, and178may be formed. Referring back toFIG.2A, contact plugs185may be formed.

The second opening OP2may be formed by patterning the third insulating layer178, and the contact plugs185may be formed by at least partially filling the second opening OP2with a conductive material. A lower surface of the second opening OP2may be recessed into the source/drain regions150, or may have a curved portion along an upper surface of each of the source/drain regions150. In different example embodiments, the shape and the dispositional form of the contact plugs185may be varied.

According to the above described example embodiments, by controlling the structures of a spacer and an air-gap spacer of a gate structure, a semiconductor device having improved electrical properties may be provided.

While the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.