Patent ID: 12262549

DETAILED DESCRIPTION

Embodiments of the present invention provide a comb-shaped transistor device that combine aspects of a fin field effect transistor and nanosheet transistor to increase the effective drive current, while maintaining the device size.

Embodiments of the present invention provide a method of fabricating a comb-shaped transistor device by forming channel sidewalls on semiconductor nanosheet layers.

Exemplary applications/uses to which the present invention can be applied include, but are not limited to: semiconductor transistors, electrical circuits, and semiconductor chips.

It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG.1, a series of alternating sacrificial spacer layers and channel layers on an insulating layer of a substrate is shown, in accordance with an embodiment of the present invention.

In one or more or more embodiments, a series of alternating sacrificial spacer layers130and channel layers140can be formed on a semiconductor-on-insulator substrate101, where the semiconductor-on-insulator substrate101can include a support layer110, an insulating layer120, and an active semiconductor layer that can be the bottom-most sacrificial spacer layer130. In various embodiments, the sacrificial spacer layers130and channel layers140can be formed by epitaxial growth or heteroepitaxial growth on an underlying layer, where the underlying layer can be a single crystal. In various embodiments, the support layer110can be a semiconductor material, where the semiconductor material can be single crystal, polycrystalline, microcrystalline, and/or amorphous, where the support layer110can provide physical support for the insulating layer120and active semiconductor layer. The insulating layer120can be an insulating dielectric material, for example, silicon oxide (SiO) or silicon nitride (SiN), where the insulating layer120can be a buried oxide layer (BOX) between the active semiconductor layer and the support layer110.

In one or more embodiments, the active semiconductor layer can be a type IV semiconductor material (e.g., silicon (Si), germanium (Ge)), a type IV-IV semiconductor material (e.g., silicon carbide (SiC), silicon germanium (SiGe), or a III-V semiconductor material (e.g., gallium arsenide (GaAs), indium phosphide (InP)), where the material of the active semiconductor layer can be selectively removable relative to an overlying channel layer140.

In one or more embodiments, the channel layers140can be a type IV semiconductor material (e.g., silicon (Si), germanium (Ge)), a type IV-IV semiconductor material (e.g., silicon carbide (SiC), silicon germanium (SiGe), or a III-V semiconductor material (e.g., gallium arsenide (GaAs), indium phosphide (InP)). The channel layers140can be single crystal to provide for epitaxial or heteroepitaxial growth.

In one or more embodiments, the sacrificial spacer layers130can be a type IV semiconductor material (e.g., silicon (Si), germanium (Ge)), a type IV-IV semiconductor material (e.g., silicon carbide (SiC), silicon germanium (SiGe), or a III-V semiconductor material (e.g., gallium arsenide (GaAs), indium phosphide (InP)), where the material of the sacrificial spacer layers130is different from the material of the channel layers140to allow selective removal, while providing for epitaxial or heteroepitaxial growth on the alternating layers. Alternatively, the alternating sacrificial spacer layers and channel layers can formed on a bulk substrate.

In one or more embodiments, the sacrificial spacer layers130can have a thickness in a range of about 6 nanometers (nm) to about 30 nm, or about 8 nm to about 15 nm, to provide sufficient distance between the channel layers140to form a gate-all-around (GAA) structure.

In one or more embodiments, the channel layers140can have a thickness in a range of about 4 nanometers (nm) to about 12 nm, or about 6 nm to about 9 nm, although other thicknesses are also contemplated.

In a non-limiting exemplary embodiment, the semiconductor-on-insulator substrate101can be a silicon-germanium-on-insulator (SGOI) substrate, where the active semiconductor layer is silicon-germanium, and the active semiconductor layer forms the bottom-most sacrificial spacer layer130used for epitaxial or heteroepitaxial growth of the subsequent alternating layers.

In various embodiments, the topmost layer of the alternating sacrificial spacer layers130and channel layers140can be a sacrificial spacer layer130to provide space for a gate-all-around (GAA) structure on a topmost channel layer140.

FIG.2is a cross-sectional side view showing a masking template and a segment template on a patterned stack of alternating sacrificial spacer layers and channel layers, in accordance with an embodiment of the present invention.

In one or more embodiments, a hardmask layer can be formed on the stack of alternating sacrificial spacer layers130and channel layers140, where the hardmask layer can be formed by a deposition (e.g., chemical vapor deposition (CVD), plasma enhanced CVD (PECVD)). In various embodiments, the hardmask layer can be a dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxy carbonitride (SiOCN), silicon boro carbonitride (SiBCN), and combinations thereof.

In one or more embodiments, a masking layer can be formed on the hardmask layer. In various embodiments, the masking layer can be a softmask layer that can be a lithography resist material that can be patterned and developed using lithographic processes. The masking layer can be a polymer resist material. In various embodiments, the masking layer can be patterned and developed to form masking templates162on the hardmask layer. The pattern can be transferred from the masking templates162to the hardmask layer by etching, for example, a directional etch (e.g., reactive ion etch (RIE)) to form segment templates152. In various embodiments, the masking template162can also be a hardmask. For example, the masking templates162can be formed by using lithography followed by etching. Other suitable techniques, such as sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned multiple patterning (SAMP), self-aligned quadruple patterning (SAQP) can be used to form the masking templates162.

In one or more embodiments, portions of the sacrificial spacer layers130and channel layers140exposed by the segment templates152can be removed using a directional etch (e.g., RIE) to form a stack105of alternating sacrificial spacer segments132and channel segments142on the insulating layer120.

FIG.3is a cross-sectional side view showing the masking templates removed and channel sidewalls formed on opposite sides of the stack of alternating sacrificial spacer segments and channel segments, in accordance with an embodiment of the present invention.

In one or more embodiments, the masking templates162can be removed to expose the underlying segment templates152, where the masking templates162can be removed by etching, chemical stripping, and/or ashing.

In one or more embodiments, channel sidewalls170can be formed on opposite sides of the stack105of alternating sacrificial spacer segments132and channel segments142, where the channel sidewalls170can be formed by lateral epitaxial growth on the exposed surfaces.

In various embodiments, the channel sidewalls170can about the same width as the thickness of the channel segments142. The channel sidewalls170can have a width in a range of about 4 nanometers (nm) to about 12 nm, or about 6 nm to about 9 nm, although other thicknesses are also contemplated.

FIG.4is a cross-sectional side view showing a sacrificial fill layer on the channel sidewalls and segment templates, in accordance with an embodiment of the present invention.

In one or more embodiments, a sacrificial fill layer180can be formed on the channel sidewalls170and segment templates152, where the sacrificial fill layer180can be formed by a blanket deposition, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), a spin-on process, or a combination thereof. Excess sacrificial fill layer material can be removed using, for example, chemical-mechanical polishing (CMP), wet chemical etching, or a combination thereof. The sacrificial fill layer180can cover the channel sidewalls170.

In various embodiments, the sacrificial fill layer180can be an insulating dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a low-k dielectric material, amorphous carbon (a-C), or a combination thereof. A low-k dielectric material can be, for example, fluorine-doped silicon oxide (SiO:F), carbon-doped silicon oxide (SiO:C), a polymeric material, for example, tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ), organo-silicon compounds (SiCOH), and combinations thereof. The sacrificial fill layer180can be a dielectric material that can be selectively removed from the channel sidewalls170and/or insulating layer120.

FIG.5is a cross-sectional side view showing the segment templates removed from the stack to expose a topmost sacrificial spacer segment and inner sidewalls of the sacrificial fill layer, in accordance with an embodiment of the present invention.

In one or more embodiments, the segment templates152can be removed from the stack105to expose a topmost sacrificial spacer segment132and inner sidewalls of the sacrificial fill layer180. The segment templates152can be removed using a selective isotropic etch, for example, a wet chemical etch or dry plasma etch. The sacrificial fill layer180can remain on the top surfaces of the channel sidewalls170.

FIG.6is a cross-sectional side view showing partition templates formed on the exposed topmost sacrificial spacer segment and inner sidewalls of the sacrificial fill layer, in accordance with an embodiment of the present invention.

In one or more embodiments, partition templates190can be formed on the exposed topmost sacrificial spacer segment132and inner sidewalls of the sacrificial fill layer180, where the partition templates190can be formed by blanket depositing a hardmask material in the opening(s)185formed by removing the segment templates152and planarizing the hardmask material using CMP. The hardmask material in the opening(s)185can be patterned and partially removed using lithographic and etching processes to form the partition templates190in the opening(s)185. A pair of partition templates190can be formed on the exposed surface of a topmost sacrificial spacer segment132. A center portion of the topmost sacrificial spacer segment132can be exposed between the pair of partition templates190.

FIG.7is a cross-sectional side view showing the central portions of the sacrificial spacer segments and channel segments exposed between the partition templates removed to form a pair of free-standing partial stacks, in accordance with an embodiment of the present invention.

In one or more embodiments, the central portions of the sacrificial spacer segment132and channel segments142exposed between the partition templates190can be removed to form a trench between a pair of free-standing partial stacks107. The exposed portions of the sacrificial spacer segment132and channel segments142can be removed using a sequence of selective directional etches (e.g., RIE) to divide the sacrificial spacer segment132and channel segments142into alternating sacrificial spacer slabs134and channel slabs144of two adjacent free-standing partial stacks107.

FIG.8is a cross-sectional side view showing the partition templates removed and sacrificial fill layer removed from the channel sidewalls, in accordance with an embodiment of the present invention.

In one or more embodiments, the partition templates190can be removed from the free-standing partial stacks107, where the partition templates190can be removed using a selective isotropic etch (e.g., wet chemical etch) or a selective directional etch (e.g., RIE). The partition templates190can be selectively removed relative to the insulating layer120, which can be exposed between the pair of free-standing partial stacks107, where the insulating layer120is a different dielectric material from the partition templates190.

In one or more embodiments, the sacrificial fill layer180can be removed using a selective isotropic etch to expose the insulating layer120and channel sidewalls170. The two adjacent free-standing partial stacks107can remain on the insulating layer120separated by the a distance equal to the gap between the partition templates190. The channel sidewalls170can be on opposite facing sides of the sacrificial spacer slabs134and channel slabs144forming an adjacent pair of comb-like structures.

FIG.9is a cross-sectional side view showing a dummy gate structure formed across the pair of free-standing partial stacks, in accordance with an embodiment of the present invention.

In one or more embodiments, a dummy gate structure can be formed across the pair of free-standing partial stacks107, where the dummy gate structure can be formed by blanket depositing a dummy gate layer on the partial stacks107, and patterning the dummy gate layer to form the dummy gate200. Gate spacers210can be formed on the sidewalls of the dummy gate200by a conformal deposition, for example, atomic layer deposition (ALD) or plasma enhanced ALD (PEALD), and removing the portion of the gate spacer material from the top surface of the dummy gate200.

In various embodiments, the dummy gate200can be amorphous silicon (a-Si), amorphous carbon (a-C), germanium (Ge), silicon-germanium (SiGe), or other easily etchable materials that can be selectively removed from the sacrificial spacer segments132and channel segments142on the insulating layer120. Although shown as one piece, the dummy gate may include a dummy gate dielectric (e.g., silicon oxide) and a dummy gate fill (e.g., a-Si).

FIG.10is a cross-sectional side view perpendicular toFIG.9showing a portion of the dummy gate structure on the topmost sacrificial spacer segment, in accordance with an embodiment of the present invention.

In one or more embodiments, the dummy gate200and gate spacers210can cover a center portion of each of the free-standing partial stacks107, including the alternating sacrificial spacer slabs134and channel slabs144. In various embodiments, the dummy gate200can be a different material from the sacrificial spacer slabs134and channel slabs144, so exposed portions of the sacrificial spacer slabs134and channel slabs144can be selectively removed using the dummy gate200and gate spacers210as a mask.

FIG.11is a top view showing a dummy gate structure formed across the pair of free-standing partial stacks, in accordance with an embodiment of the present invention.

In one or more embodiments, the dummy gate structure can be across a center portion of the pair of free-standing partial stacks107, such that a portion of the channel sidewalls170, sacrificial spacer slabs134, and channel slabs144extend beyond the gate spacers210on opposite sides. The gate spacer210can surround the dummy gate200on four sides.

FIG.12is a cross-sectional side view along the A-A cross-section ofFIG.11showing the partial stacks of sacrificial spacer slabs and channel slabs trimmed back to form a nanosheet column of sacrificial plates and channel plates below the dummy gate structure, in accordance with an embodiment of the present invention.

In one or more embodiments, the partial stacks107of sacrificial spacer slabs134, and channel slabs144can be trimmed back to form a nanosheet column109of sacrificial plates136and channel plates146below the gate spacers210and dummy gate200of the dummy gate structure. The channel plates146can be in physical and electrical contact with the channel sidewall170to form a comb-like structure having both horizontal and vertical components, where the channel plates146extend outward from a side face of the channel sidewall170. The width of the channel plates146can determine the gate length of a resulting comb-shaped nanosheet device, and the channel sidewall170can increase the effective width of the gate by adding to the charge carrying capacity and effective drive current of the channel, while maintaining the size and chip area of the transistor device.

FIG.13is a cross-sectional side view showing opposite sides of the sacrificial plates of the nanosheet column recessed, in accordance with an embodiment of the present invention.

In one or more embodiments, opposite sides of the sacrificial plates136of the nanosheet column109can be recessed using an isotropic etch. The recesses formed in the sacrificial plates136can be sufficiently deep to allow an insulating dielectric material to cover the entire sidewall of the sacrificial plate136. In various embodiments, the recesses can be about as deep as the gate spacers210are thick.

FIG.14is a cross-sectional side view showing inner spacers formed in the recesses on opposite sides of the sacrificial plates, in accordance with an embodiment of the present invention.

In one or more embodiments, inner spacers220can be formed in the recesses on opposite sides of the sacrificial plates136, where the inner spacers220can be formed by a conformal deposition (e.g., ALD, PEALD) and etched back using an isotropic etch or a directional etch (e.g., RIE). In various embodiments, the inner spacers220can be an insulating dielectric material.

FIG.15is a cross-sectional side view showing source/drains formed on the exposed surfaces of the channel plates of the nanosheet column, in accordance with an embodiment of the present invention.

In one or more embodiments, source/drains230can be formed on the exposed surfaces of the channel plates146, where the source/drains230can be formed by a lateral epitaxial growth. The source/drains230can be doped to form n-type transistor devices or p-type transistor devices.

FIG.16is a top view showing the source/drains exposes on opposite sides of each of the nanosheet columns below the dummy gate structure, in accordance with an embodiment of the present invention.

In one or more embodiments, source/drains230can be formed on adjacent nanosheet column109, where the source/drains230can be separate or merged.

FIG.17is a cross-sectional side view showing a dielectric fill layer formed on the source/drains and dummy gate structure, in accordance with an embodiment of the present invention.

In one or more embodiments, a dielectric fill layer240can be formed on the source/drains230and dummy gate structure, where the dielectric fill layer240can be formed by a blanket deposition. The dielectric fill layer240can be an insulating dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiON), silicon oxynitride (SiON), a low-k dielectric material, or a combination thereof.

FIG.18is a cross-sectional side view showing the dummy gate removed from within the gate spacer, and the sacrificial plates removed from between the inner spacers and channel plates, in accordance with an embodiment of the present invention.

In one or more embodiments, the dummy gate200can be removed from within the gate spacer210, where the dummy gate200can be removed using a selective, isotropic etch. Removal of the dummy gate200can expose the sacrificial plates136and channel plates146, where the sidewalls of the sacrificial plates136and channel plates146can be exposed.

In one or more embodiments, the sacrificial plates136can be removed from between the inner spacers220and channel plates146, where the sacrificial plates136can be removed using a selective, isotropic etch. Removal of the sacrificial plates136can form spaces between the channel plates146.

FIG.19is a cross-sectional side view showing a gate dielectric layer and a conductive gate electrode formed on the channel plates, inner spacers, and gate spacers, in accordance with an embodiment of the present invention.

In one or more embodiments, a gate dielectric layer250can be formed on the channel plates146, inner spacers220, and gate spacers, where the gate dielectric layer250can be formed by a conformal deposition (e.g., ALD, PEALD).

In various embodiments, the gate dielectric layer250can be a dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon boronitride (SiBN), silicon boro carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), a high-k dielectric, and combinations thereof. Examples of high-k materials include but are not limited to metal oxides, such as, hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalum oxide (PbScTaO), and lead zinc niobate (PbZnNbO). The high-k material may further include dopants such as lanthanum, aluminum, magnesium, or combinations thereof.

In various embodiments, the gate dielectric layer250can have a thickness in a range of about 1 nm to about 3 nm, or about 2 nm, although other thicknesses are also contemplated.

In one or more embodiments, a work function layer can be formed on the gate dielectric layer190, where the work function layer can be formed by a conformal deposition.

In various embodiments, the work function layer can be a conducting transition metallic nitride or carbide compound material, for example, tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and combinations thereof.

In one or more embodiments, a conductive gate electrode260can be formed in the open spaces on the gate dielectric layer250, where the conductive gate electrode260can be formed by a conformal deposition (e.g., ALD, PEALD).

In various embodiments, the conductive gate electrode260can be a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au), a conducting metallic compound material (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide (CoSi), nickel silicide (NiSi)), transition metal aluminides (e.g. Ti3Al, ZrAl), TaC, TaMgC, or any suitable combination of these materials.

FIG.20is a cross-sectional side view perpendicular toFIG.19showing the gate dielectric layer and the conductive gate electrode of the gate structure on the channel plates, in accordance with an embodiment of the present invention.

In various embodiments, the channel sidewalls170and channel plates146can form a comb-like channel structure for the field effect transistor device, where the channel sidewalls170and channel plates146combine the device width to increase the drive current capacity of the transistor device. The channel sidewall and the plurality of channel plates increase the channel width and increase the drive current capacity of the field effect transistor device relative to a fin field effect transistor or nanosheet field effect transistor alone having similar feature dimensions.

The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-xwhere x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as dwell, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative: terms are intended to encompass different orientations of the device in use or operation addition of the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Having described preferred embodiments of a system and method (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.