Patent ID: 12243820

DETAILED DESCRIPTION OF THE EMBODIMENTS

The embodiments described herein are all example embodiments, and thus, the inventive concept is not limited thereto, and may be realized in various other forms. Each of the embodiments provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if matters described in a specific example or embodiment are not described in a different example or embodiment thereto, the matters may be understood as being related to or combined with the different example or embodiment, unless otherwise mentioned in descriptions thereof. In addition, it should be understood that all descriptions of principles, aspects, examples, and embodiments of the inventive concept are intended to encompass structural and functional equivalents thereof. In addition, these equivalents should be understood as including not only currently well-known equivalents but also equivalents to be developed in the future, that is, all devices invented to perform the same functions regardless of the structures thereof. For example, a MOSFET described herein may take a different type or form of a transistor as long as the inventive concept can be applied thereto.

It will be understood that when an element, component, layer, pattern, structure, region, or so on (hereinafter collectively “element”) of a semiconductor device is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element the semiconductor device, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or an intervening element(s) may be present.

In contrast, when an element of a semiconductor device is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element of the semiconductor device, there are no intervening elements present. Like numerals refer to like elements throughout this disclosure.

Spatially relative terms, such as “over,” “above,” “on,” “upper,” “below,” “under,” “beneath,” “lower,” and the like, may be used herein for ease of description to describe one element's relationship to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of a semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. Thus, the term “below” can encompass both an orientation of above and below. The semiconductor device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, terms such as a “row” and a “column” of an array, in which a plurality of semiconductor structures are arranged, may be interpreted as a “column” and a “row” when the array is rotated 90 degrees.

As used herein, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression, “at least one of a, b, and c,” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when a term “same” is used to compare a dimension of two or more elements, the term may cover a “substantially same” dimension.

It will be understood that, although the terms 1st, 2nd, 3rd, 4th, etc. may be used herein to describe various elements (or layers), these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a 1stelement described in a portion the specification could be termed a 2ndelement in another portion of the specification or claims without departing from the teachings of the inventive concept.

It will be also understood that, although in an embodiment of manufacturing an inventive apparatus or structure, a step or operation is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

Many embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of the embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concept. Further, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

For the sake of brevity, conventional elements to a semiconductor device including a fin field-effect transistor (finFET) may or may not be described in detail herein when those elements are not related to the inventive concept. Further, even if those conventional elements are described, their specific structures or materials forming thereof may not be described herein when those structures or materials are not related to the inventive concept.

Herebelow, when a width of a certain layer or structure is mentioned, the width may refer to a horizontal width of the layer or structure.

FIGS.2A-2Killustrate a method of forming a plurality of fine metal lines and wide metal lines of a BEOL structure in a semiconductor device, according to some embodiments. This method is also described in reference to a flowchart shown inFIG.3. It is understood here that a plurality of operations of the method described herebelow and a plurality of sub-operations in each of the operations may not be limited to the order presented herein.

Referring toFIG.2A, a 1stmetal layer210is formed on a semiconductor device stack200with a base layer201interposed therebetween, according to an embodiment (operation S10).

The 1stmetal layer210may include at least one of ruthenium (Ru), molybdenum (Mo), tungsten (W) and cobalt (Co), not being limited thereto. The formation of the 1stmetal layer210on the semiconductor device stack200and the base layer201may be performed by, for example, physical vapor deposition (PVD), not being limited thereto.

In a later operation, the 1stmetal layer210is to be patterned to form a plurality of wide metal lines of a back-end-of-line (BEOL) structure of the semiconductor device stack200that may also include a front-end-of-line (FEOL) structure and/or a middle-of-line (MOL) structure of one or more transistors. The FEOL structure may include source/drain regions and gate structures of the transistors, and the MOL structures may include source/drain contacts, gate contacts, via structures, etc. of the transistors. The one or more transistors may be planar transistors, finFETs, nanosheet transistors, and a combination thereof. However, the FEOL structure and the MOL structure of the semiconductor device stack200are not depicted in detail inFIGS.2A to2Kas those structures are not necessary for understanding the embodiment disclosed herein.

The base layer201may include at least one of an insulation layer, an adhesive layer and an etch stop layer. The insulation layer may be formed of an oxide material such as silicon dioxide (SiO2), the adhesive layer may be formed of amorphous silicon (a-Si), titanium nitride (TiN) or tantalum nitride (TaN), and the etch stop layer may be formed of aluminum nitride (AlN) and oxide doped carbide (ODC), not being limited thereto. The base layer201may be provided here for the purpose of adhesion of the 1stmetal layer210to the semiconductor device stack200, nucleation of the 1stmetal layer210and/or etch stop of an etching process to be performed on the 1stmetal layer210in later operations.

Referring toFIG.2B, a 1sthardmask layer220is formed on the 1stmetal layer210, and a plurality photoresist patterns PR1and PR2are formed on the 1sthardmask layer20, according to an embodiment (operation S20).

In the present operation, the 1sthardmask layer220may be formed first on the 1stmetal layer210and planarized, after which a 1stphotoresist230may be formed on the 1sthardmask layer220and patterned to obtain a plurality of patterns shown as 1stpattern PR1and 2ndpattern PR2on the 1sthardmask layer220. The formation of the 1sthardmask layer220and the 1stphotoresist230may be performed by at least one of PVD, chemical vapor deposition (CVD) and plasma-enhanced chemical vapor deposition (PECVD), not being limited thereto. The planarization of the 1sthardmask layer220may be performed by chemical-mechanical polishing (CMP), not being limited thereto, and the 1stpatterns PR1and the 2ndpatterns PR2may be obtained through applying a 1stphotolithography process to the 1stphotoresist230. AlthoughFIG.2Bshows only three 1stpatterns PR1and one 2ndpattern PR2are formed, the number of these patterns obtained through the 1stphotolithography process is not limited thereto.

The 1sthardmask layer220may be formed of silicon oxynitride (SiON) or silicon dioxide (SiO2), not being limited thereto, and the 1stphotoresist230may include an organic polymer resin containing a photoactive (light sensitive) material.

According to an embodiment, the 1stphotoresist230may be patterned such that the 1stpatterns PR1having a same size are arranged in a row with a predetermined pitch PI therebetween. The predetermined pitch PI may be set to four times a sum of a width F of a fine metal line to be obtained in a later operation and a thickness S of a spacer layer to be used to pattern the fine metal line in a later operation, according to an embodiment. That is, the predetermined pitch PI may be represented by 4×(F+S), as shown inFIG.2B. Here, the fine metal line is one of a plurality of fine metal lines that will form the BEOL structure for the semiconductor device stack200along with the wide metal lines to be patterned from the 1stmetal layer210in a later operation. It is noted that the thickness S of the spacer layer will define and be equal to a width S of a space between two adjacent fine metal lines among three or more fine metal lines to be arranged in a row at a uniform pitch to be described later. These three or more fine metal lines are included in the plurality of fine metal lines of the BEOL structure for the semiconductor device stack200.

According to an embodiment, the 1stphotoresist230may also be patterned such that the 1stpatterns PR1, a space (or trench) therebetween, and the 2ndpattern PR2can have predetermined widths, respectively. For example, a width of each of the 1stpatterns PR1may be set to a sum of two times the width F of the fine metal line and the thickness S of the spacer layer, that is, 2F+S, as shown inFIG.2B. Further, a width of a space between the two adjacent 1stpatterns PR1may be set to a sum of two times the width F of the fine metal line and three times the thickness S of the spacer layer, that is, 2F+3S. In addition, a width W of the 2ndpattern PR2may be set to be greater than the width of each of the 1stpatterns PR1(which is 2F+S), and a width of a space between the 2ndpattern PR2and the closest 1stpattern PR1may be set to be greater than 2F+3S, not being limited thereto.

Here, it is noted that the width 2F+S of each of the 1stpatterns PR1may define a width of each of 1stwide metal lines that will be formed along with the fine metal lines as the BEOL structure for the semiconductor device stack200in a later operation. It is further noted that the width W of the 2ndpattern PR2may define a width of a 2ndwide metal line that will also be formed along with the fine metal lines as the BEOL structure for the semiconductor device stack200in a later operation. Thus, according to design needs for the fine metal lines, the 1stwide metal lines and the 2ndwide metal line, the 1stphotoresist230may be differently patterned so that the width 2F+S of each of the 1stpatterns PR1and the width W of the 2ndpattern PR2are different from the dimensions shown inFIG.2B. For example, the width W of the 2ndpattern PR2may be set to be smaller than the width 2F+S of each of the 1stpatterns PR1as long as the width W is set to be greater than the width F of the fine metal line.

Referring toFIG.2C, subtractive etching is performed on the 1sthardmask layer220and the 1stmetal layer210using the patterns PR1and PR2shown inFIG.2Bto obtain a plurality of metal patterns therebelow, and the patterns PR1and PR2and the 1sthardmask layer220are removed after the subtractive etching operation, according to an embodiment (operation S30).

The subtractive etching may be performed, for example, by dry etching and/or reactive ion etching (RIE) to obtain a plurality of metal patterns respectively corresponding to the 1stpatterns PR1and the 2ndpattern PR2as shown inFIG.2B. The subtractive etching also exposes a top surface of the base layer201between the plurality of metal patterns. Accordingly,FIG.2Cshows three 1stmetal patterns MP1and one 2ndmetal pattern MP2corresponding to the three 1stpatterns PR1and one 2ndpattern PR2, respectively, are formed on the base layer201, and a top surface of the base layer201is exposed between the plurality of metal patterns.

It is noted here that the shapes of the 1stpatterns PR1and the 2ndpattern PR2are transferred to the 1stmetal patterns MP1and the 2ndmetal pattern MP2through the above-described 1stphotolithography process and dry etching and/or wet etching operation. Thus, the 1stmetal patterns MP1and the 2ndmetal pattern MP2may have the same widths as the 1stpatterns PR1and the 2ndpattern PR2, respectively, and a space (or trench) formed between two adjacent 1stmetal patterns MP1may have the same width as the space between two adjacent 1stpatterns PR1. Accordingly, the width of each of the 1stmetal patterns MP1may be equal to the width 2F+S of each of the 1stpatterns, and the width of the space between the two adjacent 1stmetal patterns MP1may be equal to the width 2F+3S of the space between the two adjacent 1stpatterns PR1. Further, the width of the 2ndmetal pattern MP2may be equal to the width W of the 2ndpattern PR2.

It is also noted that two of the three 1stmetal patterns MP1and the one 2ndmetal pattern MP2are provided here to form two 1stwide metal lines and one 2ndwide metal line of the BEOL structure for the semiconductor device stack200, respectively, in a later operation to be described in reference toFIG.2J. Thus, the width 2F+S of each of the 1stmetal patterns MP1is to be the width of each of the 1stwide metal lines, and the width W of the 2ndmetal pattern MP2is to be the width of the 2ndwide metal line.

Referring toFIG.2D, a spacer layer240is conformally deposited on outer surfaces of the 1stmetal patterns MP1and the 2ndmetal pattern MP2, and the exposed top surface of the base layer201, according to an embodiment (operation S40).

In this conformal deposition operation, the spacer layer240may be deposited using a thin film deposition technique such as atomic layer deposition (ALD) so that the spacer layer140can have the thickness S which is uniform along the outer surfaces of the 1stmetal patterns MP1and the 2ndmetal pattern MP2, and the exposed top surface of the base layer201, according to an embodiment. As noted above, the thickness S of the spacer layer140may be set to be equal to the width S of the space between two adjacent fine metal lines among three or more fine metal lines to be arranged in a row at a uniform pitch to be described later.

Further, in the present operation, the spacer layer240may be conformally deposited on the outer surfaces of the 1stmetal patterns MP1and the 2ndmetal pattern MP2, and the exposed top surface of the base layer201, without being disconnected, as shown inFIG.2D,

The spacer layer240may be formed of a material including silicon oxide (SiO) and/or silicon dioxide (SiO2), not being limited thereto, as long as the material has etch selectivity against a material or layer deposited above the spacer layer240in later operations.

Referring toFIG.2E, the spacer layer240is etched back by, for example, dry etching, at top surfaces of the 1stmetal patterns MP1and the 2ndmetal pattern MP2, and at the top surface of the exposed base layer201, according to an embodiment (operation S50).

However, after this etch-back operation performed on the spacer layer240, the spacer layer240may still remain on side surfaces of the metal patterns MP1and MP2to expose the top surfaces thereof upward to the outside. The remaining spacer layer240includes spacers SL1to SL6formed on the side surfaces of the 1stmetal patterns MP1, and spacers SL7and SL8formed on the side surfaces of the 2ndmetal pattern MP2. A width S of each of these spacers SL7and SL8is equal to the thickness S of the spacer layer240.

Further, by this etch-back operation, the top surfaces of the metal patterns MP1and MP2and top surfaces of the spacer layer240remaining on the side surfaces of the metal patterns MP1and MP2may become coplanar with each other.

Referring toFIG.2F, a 2ndhardmask250is formed on the metal patterns MP1and MP2with the spacers SL1to SL8on their side surfaces, and the base layer201therebetween, and a 2ndphotoresist260is formed on the 2ndhardmask250except a 1sttarget space (or trench) TSP1where a top surface of the 2ndhardmask250is exposed upward to the outside, according to an embodiment (operation S60).

The 2ndhardmask250formed on the metal patterns MP1and MP2may be a spin-on carbon (SOC) hardmask or a spin-on glass (SOG) hardmask, and the 2ndphotoresist260may be formed of the same material forming the 1stphotoresist230as describe in reference toFIG.2B, according to embodiments.

Although not shown inFIG.2F, the 2ndhardmask250may be planarized at a top thereof after being formed on the metal patterns MP1and MP2with the spacers SL1to SL8on their side surfaces and the base layer201therebetween, according to an embodiment. The planarization may be performed by, for example, CMP, not being limited thereto. Subsequently, the 2ndphotoresist260may be formed on the planarized 2ndhardmask250, and a 2ndphotolithography process may be applied to the 2ndphotoresist260in a manner similar to the 1stphotolithography process applied to the 1stphotoresist230as shown inFIG.2B. The 2ndphotolithography process may remove a portion of the 2ndphotoresist260to form the 1sttarget space TSP1corresponding to a target metal pattern TMP, among the 1stmetal patterns MP1, according to an embodiment. Here, the target metal pattern TMP is a metal pattern which is selected among the 1stmetal patterns MP1to be removed in a subsequent operation while the other metal patterns among the 1stmetal patterns MP1and the 2ndmetal pattern MP2are to become the wide metal lines of the BEOL structure. Thus, the 2ndphotolithography process may be performed such that the 1sttarget space TSP1is formed vertically above the target metal pattern TMP, according to an embodiment.

Referring toFIG.2G, a portion of the 2ndhardmask250, vertically below the 1sttarget space TSP1, and the target metal pattern TMP therebelow are removed using the spacers SL3and SL4, hereafter referred to as target spacers, formed on the side surfaces of the target metal pattern TMP, according to an embodiment (operation S70).

In the present operation, the target spacers SL3and SL4may be used as a mask to remove the target metal pattern TMP between the target spacers SL3and SL4by, for example, dry etching and/or wet etching. In order to remove the target metal pattern TMP by dry etching and/or wet etching, the 1sttarget space TSP1may have been formed in a previous operation to have a width greater than the width 2F+S of the target metal pattern TMP, which is the same as the width of each of the 1stmetal patterns MP1, according to an embodiment.

With the target metal pattern TMP being removed, a 2ndtarget space (or trench) TSP2having a width 2F+S equal to the width of the target metal pattern is formed between the target spacers SL3and SL4. Further, the 2ndphotoresist260and the 2ndhardmask250are removed by wet etching and/or ashing such as plasma ashing, not being limited thereto. As the 2ndhardmask250is removed, additional 2ndtarget spaces TSP2having the same width 2F+S are formed at positions where the 2ndhardmask250is removed. The 2ndtarget spaces TSP2refer to positions in which the fine metal lines are to be formed by conformal deposition of a metal layer in a later operation. It is noted here that a width of the 2ndtarget space TSP2may be set to be greater than twice the width F of the fine metal line so that the metal layer forming the fine metal line can be conformally deposited inside the 2ndtarget space TSP2obtained by removing the target metal pattern TMP without being overlapped in a later operation.

Referring toFIG.2H, a 2ndmetal layer270is conformally deposited along outer surfaces of various patterns remaining after the etching and/or ashing operations described in reference toFIGS.2F and2G, and on the top surface of the exposed base layer201between the various patterns, according to an embodiment (operation S80).

Here, the various patterns include the 1stmetal patterns MP1with the spacers SL1, SL2, SL5and SL6formed on their side surfaces, the 2ndmetal pattern with the spacers SL7and SL8formed on its side surfaces, the target spacers SL3and SL4. These various patterns take a form of a plurality of protrusions from the base layer201as shown inFIG.2G. Hereafter, the 1stmetal patterns MP1remaining after the target metal pattern TMP is removed are referred to as remaining 1stmetal patterns MP1.

According to an embodiment, the 2ndmetal layer270may be conformally deposited by, for example, ALD or CVD, along outer surfaces of the various patterns so that a thickness of the 2ndmetal layer270can be uniform along the outer surfaces of the various patterns to have a uniform thickness T. As will be described later, the conformally deposited 2ndmetal layer270is to become the fine metal lines to be obtained to form the BEOL structure for the semiconductor device stack200. Thus, the uniform thickness T of the 2ndmetal layer270may define to be equal to the width F of the fine metal line.

When the 2ndmetal layer270is conformally deposited along the outer surfaces of the various patterns in the present operation, the 2ndmetal layer270may also be conformally deposited along the side surfaces of the target spacers SL3and SL4inside the 2ndtarget spaces TSP2without filling the 2ndtarget space TSP2as shown inFIGS.2G and2H. This conformal deposition can be enabled because the width of the 2ndtarget space TSP2is set to be greater than twice the thickness T of the 2ndmetal layer270, as described earlier. Thus, two portions P1and P2of the 2ndmetal layer270formed at the side surfaces of the target spacers SL3and SL4to face each other inside the 2ndtarget space TSP2may not contact or overlap each other. Here, it is noted that the two portions P1and P2deposited on the side surfaces of the target spacers SL3and SL4inside the 2ndtarget space TSP2along with portions P3and P4deposited on the other side surfaces of the target spacers SL3and SL4are to form a plurality of fine metal lines in a later operation.

It is also noted that a space between these two portions P1and P2of the 2ndmetal layer270inside the 2ndtarget space TSP2is defined by the thickness S of the spacer layer240. In other words, if the thickness of the spacer layer240is set to be greater than S, which defines the widths of the patterns PR1, the target metal pattern TMP and the 2ndtarget space TSP2as shown inFIGS.2B to2G, the two portions P1and P2of the 2ndmetal layer270may contact or overlap each other when the 2ndmetal layer270is deposited inside the 2ndtarget space TSP2, thereby preventing the conformal deposition inside the 2ndtarget space TSP2. Thus, the thickness S may be the minimum thickness that the spacer layer240may have so that the 2ndmetal layer270may be conformally deposited inside the 2ndtarget space TSP2, according to an embodiment.

Moreover, the width F of the fine metal line, which is equal to the thickness T of the metal layer270, also defines the widths of the patterns PR1, the target metal pattern TMP and the 2ndtarget space TSP2. If the thickness of the metal layer270is set to be greater than T when the thickness of the spacer layer240is set to S, the two portions P1and P2of the 2ndmetal layer270may contact or overlap each other when the 2ndmetal layer270is deposited inside the 2ndtarget space TSP2. In this case, the conformal deposition of the metal layer270inside the 2ndtarget space TSP2may not be achieved, thereby to prevent obtaining a plurality of fine metal lines having a uniform width. Further, if the thickness of the metal layer270is set to be smaller than T when the thickness of the spacer layer240is set to S, a width of a space between the two portions P1and P2of the 2ndmetal layer270may become greater than the thickness S of the spacer layer240which is equal to the width S of the space between two adjacent fine metal lines described above. In this case, spaces having a uniform width between the plurality of fine metal lines may not be achieved. Thus, the thickness T may be an optimal thickness that the 2ndmetal layer270may have to achieve a uniform thickness and a uniform-width space for the plurality of fine metal lines, according to embodiments.

The 2ndmetal layer270may be formed of at least one of ruthenium (Ru), molybdenum (Mo), tungsten (W) and cobalt (Co), not being limited thereto, that forms the 1stmetal layer210. However, according to an embodiment, the material forming the 2ndmetal layer270may be different from that of the 2ndmetal layer210. For example, when the 1st metal layer210is formed of Ru, the 2ndmetal layer270may be formed of Mo. Why differ?

Referring toFIG.2I, the 2ndmetal layer270shown inFIG.2His removed at top surfaces of the various patterns described in the previous operation, and at the top surface of the exposed base layer201, according to an embodiment (operation S90).

In the present operation, the 2ndmetal layer270formed on the top surfaces of the various patterns and the base layer201may be etched back by, for example, dry etching, to expose the top surfaces of the various patterns and the base layer201upward to the outside. However, after the etch back operation, the 2ndmetal layer270may still remain on the side surfaces of the target spacers SL3and SL4, and on side surfaces of the spacers SL1, SL2and SL5to SL8deposited on side surfaces of the remaining 1stmetal patterns MP1and the 2ndmetal pattern MP2.

Referring toFIG.2J, the spacers SL1to SL8including the target spacers SL3and SL4are removed to form a plurality of fine metal lines and wide metal lines, according to an embodiment (operation S100).

The spacers SL1to SL8including the target spacers SL3and SL4may be removed by, for example, dry etching and/or wet etching. By removing the spacers SL1to SL8including the target spacers SL3and SL4in the present operation, the 2ndmetal layer270remaining on the side surfaces of the removed target spacers SL3and SL4may form four 1stfine metal lines270F-1, which correspond to the three or more fine metal lines arranged in a row with a uniform pitch as described earlier. Also, the 2ndmetal layer270remaining on the side surfaces of the removed spacers SL2and SL5facing the target spacers SL3and SL4may form additional two 1stfine metal lines270F-1, while the 2ndmetal layer270remaining on the side surfaces of the removed spacers SL1and SL6may form two 2ndfine metal lines270F-2. Further, the 2ndmetal layer270remaining on the side surfaces of the removed spacers SL7and SL8may form two 3rdfine metal lines270F-3. Further, the remaining 1stmetal patterns MP1form a plurality of 1stwide metal lines, and the 2ndmetal pattern MP2form a 2ndwide meal line210W-2.

Thus, the width F of each of the fine metal lines270F-1,270F-2and270F-3may be equal to the thickness T of the 2ndmetal layer270. Further, the width of each of the 1stwide metal lines210W-2may be equal to the width 2F+S of each of the remaining 1stmetal patterns MP1, and the width of the 2ndwide metal line210W-2may be equal to the width W of the 2ndmetal pattern MP2. This is because, as described earlier, the remaining 1stmetal patterns MP1became the 1stwide metal lines210W-1, and the 2ndmetal pattern MP2became the 2ndwide metal line210W-2.

In addition, a width S of a space between any two adjacent fine metal lines among the 1stfine metal lines270F-1may be equal to the thickness S of the spacer layer240. Further, a width of a space between each of the 1stwide metal lines210W-1and the closest 1stfine metal line among the 1stfine metal lines270F-1may also be equal to S. This is because each of the 1stwide metal lines210W-1and the closest 1stfine metal line are both formed in the additional 2ndtarget space TSP2having the same width as the 2ndtarget space TSP2in which two of the 1stfine metal lines270F-1are formed, as shown inFIGS.2H to2J. It is noted that a width of a space between each of the 1stwide metal lines210W-1and the closest 1stfine metal line among the 1stfine metal lines270F-1may also be equal to S, because this space is formed by removing the spacer SL2or SL3having the width S. Further, a width of a space between each of the 3rdfine metal lines270F-3and the 2ndwide metal line210W-2may also be equal to S, because this space is formed by removing the spacer SL7or SL8having the width S.

Thus, as shown inFIG.2J, the 1stfine metal lines270F-1are arranged in a row with a uniform pitch, which is equal to F+S. Further, all of the fine metal lines270F-1to270F-3have a uniform width F, and the space between any two adjacent fine metal lines among the 1stfine metal lines270F-1has the uniform width S. However, a space between a 2ndfine metal line270F-2and a 3rdfine metal line270F-3adjacent to each other may have a greater width than the uniform width S.

Referring toFIG.2K, the base layer201is removed to finish formation of the fine metal lines270F-1to270F-3, the 1stwide metal lines210W-1and the 2ndwide metal line210W-2of the BEOL structure for the semiconductor device stack200, according to an embodiment (operation S110).

The base layer201may be removed at the spaces between the fine metal lines270F-1,270F-2,270F-3, and the wide metal lines210W-1and210W-2by selective wet etching and cleaning, or dry etching, not being limited thereto, as shown inFIG.2Kaccording to an embodiment. However, the base layer201may still remain below the fine metal lines270F-1,270F-2,270F-3, and the wide metal lines210W-1and210W-2for connection with the MOL structure of the semiconductor device stack200as will be described later in reference toFIG.4.

In the above embodiments, the 1stmetal layer210, the 1sthardmask layer220and the plurality photoresist patterns PR1and PR2are formed on the semiconductor device stack200(FIGS.2A and2B) to pattern the BEOL structure of the semiconductor device stack200. However, according to another embodiment, the 1stmetal layer210, the 1sthardmask layer220and the plurality photoresist patterns PR1and PR2may be formed separately, not on the semiconductor device stack200, to pattern the BEOL structure, and the patterned BEOL structure may be bonded to the semiconductor device stack200later to form a semiconductor device.

As described above in reference toFIGS.2A to2K, the fine metal lines270F and the wide metal lines210W-1and210W-2obtained through the operations shown inFIGS.2A-2Kmay form the BEOL structure for the semiconductor device stack200which may include one or more of a planar transistor, a finFET, a nanosheet transistor, and a combination thereof. Thus, a following embodiment provides a schematic diagram of a semiconductor device in which the above-described BEOL structure including the fine metal lines270F-1,270F-2,270F-3, and the wide metal lines210W-1and210W-2are interconnected to an MOL structure of the semiconductor device.

FIG.4illustrates a semiconductor device including a semiconductor device stack and a plurality of metal lines formed above the semiconductor device stack, according to an embodiment.

Referring toFIG.4, a semiconductor device40includes the semiconductor device stack200and the plurality of metal lines shown inFIG.2K.

According to an embodiment, the plurality of fine metal lines270F-1,270F-2and270F-3arranged in a row with the predetermined same pitch are connected to an n-type finFET, which may be an n-type metal oxide semiconductor (NMOS), and a p-type finFET, which may be a p-type metal oxide semiconductor (PMOS) through an MOL structure. Specifically, the fine metal lines210F arranged in a row with the predetermined same pitch are connected two source/drain regions and a gate structure of each of the NMOS and the PMOS through an MOL structure including corresponding source/drain contact structures and gate structures. According to an embodiment, the 1stwide metal lines210W-1and210W-2may be respectively connected to a voltage source and a ground source through corresponding power lines (not shown).

FIG.4further shows that the other fine metal lines210F and the 2ndwide metal line are reserved for connection to another circuit element of the semiconductor device40or another semiconductor device.

As described above, a plurality of fine metal lines and a plurality of wide metal lines are obtained by a method different from the relate art etching operation. According to the embodiments, the fine metal lines are formed by performing conformal deposition, such as conformal CVD or ALD, of a metal layer along various patterns as shown inFIG.2H, while the wide metal lines are formed by patterning a different metal layer though a photolithography process followed by dry etching and/or wet etching. Thus, unlike the related art fine metal line patterning that uses direct etching on a metal layer using a hardmask or layer that may cause a clogging problem, the above embodiments provide forming fine metal lines by simple conformal deposition that may avoid the clogging problem. Thus, the fine metal lines obtained according to embodiments may have a uniform thickness and a uniform space between a plurality of fine metal lines arranged in a row.

FIG.5illustrates a schematic plan view of an integrated chip (IC) according to an embodiment.

Referring toFIG.5, an IC500according to an embodiment may include a processor520and semiconductor devices530that are mounted on a module substrate510. The processor520and/or the semiconductor devices530may include the plurality of fine metal lines and at least one wide metal line described in the above embodiments.

FIG.6illustrates a schematic block diagram of an electronic system according to an embodiment.

Referring toFIG.6, an electronic system600in accordance with an embodiment may include a microprocessor610, a memory620, and a user interface630that perform data communication using a bus640. The microprocessor610may include a central processing unit (CPU) or an application processor (AP). The electronic system600may further include a random access memory (RAM)650in direct communication with the microprocessor610. The microprocessor610and/or the RAM650may be implemented in a single module or package. The user interface630may be used to input data to the electronic system600, or output data from the electronic system600. For example, the user interface630may include a keyboard, a touch pad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light-emitting device (LED), an organic light-emitting diode (OLED) device, an active-matrix light-emitting diode (AMOLED) device, a printer, a lighting, or various other input/output devices without limitation. The memory620may store operational codes of the microprocessor610, data processed by the microprocessor610, or data received from an external device. The memory620may include a memory controller, a hard disk, or a solid state drive (SSD).

At least one of the microprocessor610, the memory620and/or the RAM650in the electronic system600may include one or more of the multi-stack semiconductor devices described in at least one the above embodiments.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a number of example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above embodiments without materially departing from the inventive concept.