Patent ID: 12230662

DESCRIPTION OF EMBODIMENTS

Hereinafter, suitable embodiments of the present disclosure are explained in detail with reference to the attached drawings. Note that constituent elements that have substantially the same functional configurations are given the same reference signs in the present specification and the drawings, and overlapping explanations are omitted thereby.

In addition, explanations are given in the following order.1. Overview of Present Disclosure2. First Embodiment3. Second Embodiment4. Application Example of Second Embodiment5. Third Embodiment6. Fourth Embodiment7. Fifth Embodiment8. Sixth Embodiment9. Seventh Embodiment10. Eighth Embodiment11. Ninth Embodiment12. Application Example of Ninth Embodiment13. Tenth Embodiment14. First Application Example of Tenth Embodiment15. Second Application Example of Tenth Embodiment16. Examples of Application to Electronic Equipment17. Use Examples of Solid-State Image Pickup Apparatus18. Examples of Application to Endoscopic Surgery System19. Examples of Application to Mobile Body

1. Overview of Present Disclosure

The present disclosure is to reduce the manufacturing cost of solid-state image pickup apparatuses.

Here, before an explanation of the present disclosure, WoW (Wafer on Wafer) disclosed in PTL 1 is explained.

WoW is a technology of joining and stacking a solid-state image pickup apparatus, and a circuit including an IC such as a signal processing circuit or a memory circuit in the states of wafers, as depicted inFIG.1, for example.

FIG.1schematically represents WoW in which a wafer W1having plural solid-state image pickup elements11formed thereon, a wafer W2having plural memory circuits12formed thereon, and a wafer W3having plural logic circuits13formed thereon are joined and stacked in a state in which the wafer W1, the wafer W2, and the wafer W3are finely aligned.

By dicing the thus-stacked configuration, a solid-state image pickup apparatus like the one depicted inFIG.2is formed, for example.

A solid-state image pickup apparatus1inFIG.2includes pixels131(e.g., on-chip lenses10and on-chip color filters), a solid-state image pickup element11, a memory circuit12, a logic circuit13, and a support board14that are stacked in this order from above.

Here, by applying the WoW technology, wires21-1that electrically connect the solid-state image pickup element11and the memory circuit12, and wires21-2that electrically connect the memory circuit12and the logic circuit13can form connections at fine pitches.

As a result, the number of wires can be increased. Accordingly, the transfer speed of each signal line can be reduced, and so it becomes possible to attempt to save electric power.

However, because the area sizes considered to be required for the stacked solid-state image pickup element11, the memory circuit12, and the logic circuit13are different from each other, spaces Z1where none of circuits and wires is formed occur on the left and right, in the figure, of the memory circuit12having an area size smaller than the largest solid-state image pickup element11. In addition, spaces Z2where none of circuits and wires is formed occur on the left and right, in the figure, of the logic circuit13having an area size smaller than the memory circuit12.

That is, the spaces Z1and Z2occur because the area sizes considered to be required for the solid-state image pickup element11, the memory circuit12, and the logic circuit13are different from each other, and occur because the stack is formed with the solid-state image pickup element11considered to be required to have the largest area size as the reference element inFIG.2.

Thereby, the theoretical yield related to the manufacturing of the solid-state image pickup apparatus1decreases; as a result, the costs related to the manufacturing increases.

In addition, inFIG.1, configurations that are in the solid-state image pickup elements11, the memory circuits12, and the logic circuits13formed on the wafers W1to W3, and are to be bad elements are represented by colored squares. That is, it is depicted inFIG.1that two bad elements have occurred in each of the wafers W1to W3.

Bad elements that are generated in the solid-state image pickup elements11, the memory circuits12, and the logic circuits13formed on the wafers W1to W3, respectively, do not necessarily occur at the same positions, as depicted inFIG.1. Because of this, as depicted inFIG.1, as solid-state image pickup apparatuses1are formed by stacking, six bad solid-state image pickup apparatuses1occur as indicated by crosses on the wafer W1of the solid-state image pickup elements11.

Thereby, despite the fact that at least two parts in three parts, which are a solid-state image pickup element11, a memory circuit12, and a logic circuit13, are not bad elements in each of the six bad solid-state image pickup apparatuses1, the six solid-state image pickup apparatuses1are treated as being bad, and the yield of each part becomes six, which corresponds to the product of multiplication by the number of wafers, while otherwise the yield really could be two.

As a result, the yield of solid-state image pickup apparatuses1is lowered, and the manufacturing cost increases.

In addition, as depicted inFIG.3, as one possible solution, after solid-state image pickup elements11, memory circuits12, and logic circuits13with different chip sizes are diced, only good elements are arranged selectively, and are connected by forming small-sized bumps.

In the solid-state image pickup apparatus1inFIG.3, the on-chip lenses and on-chip color filters10, and the solid-state image pickup element11are stacked from above, the memory circuit12and the logic circuit13are stacked thereunder on a single layer, and the support board14is provided and stacked thereunder. In addition, the solid-state image pickup element11, and the memory circuit12and logic circuit13arranged on the single layer are electrically connected via small-sized bumps31.

In the solid-state image pickup apparatus1inFIG.3, chips with different sizes that are selected as good chips are connected via the bumps31, and additionally the influences of the theoretical yield of each wafer, and the yield of each chip are reduced.

However, it is difficult to form the small-sized bumps31, and, as depicted inFIG.3, there is a limitation on the size-reduction of a connection pitch d2, which make it impossible to make the connection pitch d2smaller than a connection pitch d1inFIG.2depicting the case that WoW is used.

Because of this, the solid-state image pickup apparatus1inFIG.3, which is a stack formed by using bumps, cannot have a large number of connection terminals compared with the solid-state image pickup apparatus1inFIG.2, which is a stack formed by using WoW. In addition, if the number of connection terminals increases in the case of the connection by using bumps as in the solid-state image pickup apparatus1inFIG.3, the connection terminals are joined in an implementation process, and so deterioration of the yield related to the joining occurs, undesirably increasing the cost. Further, the connection of the bumps in the implementation process requires work which is performed for each bump. Accordingly, each process takes a long time, and the process cost also increases.

On the basis of the above, an image pickup element of the present disclosure is to reduce costs related to manufacturing, in terms of theoretical yield, implementation cost and process cost.

2. First Embodiment

FIG.4is a figure for explaining a structure that is to be applied at the time of the manufacturing of a solid-state image pickup apparatus of the present disclosure, and is a stack of plural wafers formed by using a combination of the CoW (Chip on Wafer) technology and the WoW technology.

In the manufacturing of the solid-state image pickup apparatus of the present disclosure, two wafers are stacked in a state in which wires are finely aligned. One of the two wafers is a wafer101in which plural solid-state image pickup elements (CMOS (Complementary Metal Oxide Semiconductor) image sensors or CCDs (Charge Coupled Devices)120are formed, and the other of the two wafers is a wafer102in which memory circuits121and logic circuits122are re-arranged. Note that, in explanations hereinafter, solid-state image pickup elements120are represented as being CMOS image sensors (CMOS Image Sensors) in figures, and are also referred to as CIS120simply.

The wafer101has plural solid-state image pickup elements120formed therein by a semiconductor process.

The wafer102has plural memory circuits121re-arranged therein. The plural memory circuits121are formed on a wafer103by a semiconductor process, and diced, and thereafter are each subjected to an electrical inspection, and confirmed to be good chips.

In addition, the wafer102has plural logic circuits122re-arranged therein. The plural logic circuits122are formed on a wafer104by a semiconductor process, and diced, and thereafter are each subjected to an electrical inspection, and confirmed to be good chips.

<Configuration Example of Solid-State Image Pickup Apparatus Formed with Wafers Stacked by Using WoW Technology inFIG.4>

After plural wafers are stacked by using the WoW technology as depicted inFIG.4, the plural wafers are diced, and thereby a solid-state image pickup apparatus111(FIG.5) of the present disclosure is formed.

The solid-state image pickup apparatus of the present disclosure has a configuration as depicted inFIG.5, for example. Note thatFIG.5includes a side cross-sectional view on the upper half, and a figure, on the lower half, depicting a horizontal arrangement relation among a solid-state image pickup element120, a memory circuit121, and a logic circuit122as seen from above.

In the solid-state image pickup apparatus111on the upper half ofFIG.5, color filters and on-chip lenses pixels131, and the solid-state image pickup element120are stacked from above in the figure. Thereunder, the memory circuit121and the logic circuit122are stacked being arranged on the left and right on a single layer. Thereunder, a support board132is formed. That is, as depicted on the upper half ofFIG.5, the solid-state image pickup apparatus111inFIG.5includes a semiconductor element layer E1including the solid-state image pickup element120formed on the wafer101, and a semiconductor element layer E2including the memory circuit121and the logic circuit122formed on the wafer102.

Wires120athat are in wires120aof the solid-state image pickup element120, and are on the memory circuit121are electrically connected with wires121aof the memory circuit121by wires134connected by CuCu-connection.

In addition, wires120athat are in the wires120aof the solid-state image pickup element120, and are on the logic circuit122are electrically connected with wires122aof the logic circuit122by wires134connected by CuCu-connection.

The space that is in the semiconductor element layer E2on which the memory circuit121and the logic circuit122are formed, and surrounds the memory circuit121and the logic circuit122becomes filled with an oxide film133. Thereby, in the semiconductor element layer E2, the memory circuit121and the logic circuit122become embedded in the oxide film133.

If the oxide film133is an inorganic film, it is desirably a Si-based oxide film such as a SiO2 film, a SiO film, or a SRO film in terms of heat resistance and the warp amount after film formation. In addition, it is also possible to replace the oxide film133with an organic film. The organic film in that case is preferably a polyimide-based (PI, PBO, etc.) film, a polyamide-based film or the like that can easily ensure high heat resistance.

In addition, the semiconductor element layer E1on which the solid-state image pickup element120is formed, and the semiconductor element layer E2on which the memory circuit121and the logic circuit122are formed are joined at their boundary by an oxide film junction layer135formed by oxide-film joining. Further, the semiconductor element layer E2including the memory circuit121and the logic circuit122, and the support board132are joined by an oxide film junction layer135formed by oxide-film joining.

In addition, as depicted on the lower half ofFIG.5, when seen from above, the memory circuit121and the logic circuit122are arranged to be enclosed in an area where the solid-state image pickup element120is on the uppermost layer. With such an arrangement, the empty space not occupied by the memory circuit121and the logic circuit122decreases on the layer including the memory circuit121and the logic circuit122, and so it becomes possible to enhance the theoretical yield.

On the wafer102inFIG.4, memory circuits121and logic circuits122are re-arranged being adjusted finely such that, when individual solid-state image pickup apparatuses111are formed by dicing, the memory circuits121and the logic circuits122are arranged in areas of solid-state image pickup elements120when seen from above.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.5>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.5is explained with reference toFIG.6toFIG.9. Note that side cross-sectional views6A to6L inFIG.6toFIG.9depict side cross-sectional views of the solid-state image pickup apparatus111.

In a first process, as depicted in the side cross-sectional view6A inFIG.6, the memory circuit121and the logic circuit122confirmed to be good elements after an electrical inspection is performed are re-arranged on a re-arrangement board151in the layout as depicted on the lower half ofFIG.5. An adhesive152is applied onto the re-arrangement board151, and the memory circuit121and the logic circuit122re-arranged on the re-arrangement board151, and fixed by the adhesive152.

In a second process, as depicted in the side cross-sectional view6B inFIG.6, the memory circuit121and the logic circuit122are reversed such that their top surfaces depicted in the side cross-sectional view6A become the lower surfaces, an oxide film is formed, and oxide-film joining is performed by forming the oxide film junction layer135on a flattened support board161.

In a third process, as depicted in the side cross-sectional view6C inFIG.6, the re-arrangement board151is debonded together with the adhesive152, and peeled and eliminated.

In a fourth process, as depicted in the side cross-sectional view6D inFIG.7, silicon layers at top surface sections, in the figure, of the memory circuit121and the logic circuit122are made thin such the height of the memory circuit121and the logic circuit122becomes a height A which does not influence the characteristics of the device.

In a fifth process, as depicted in the side cross-sectional view6E inFIG.7, the oxide film133to function as an insulating film is formed, and a chip including the re-arranged memory circuit121and logic circuit122is embedded therein. At this time, the surface of the oxide film133is flattened at the height corresponding to the height of the memory circuit121and the logic circuit122.

In a sixth process, as depicted in the side cross-sectional view6F inFIG.7, a support board171is joined on the flattened oxide film133by the oxide film junction layer135formed by oxide-film joining.

In a seventh process, as depicted in the side cross-sectional view6G inFIG.8, the support board171is eliminated by being debonded or by being etched. By the processes from the first process to the seventh process, the memory circuit121and the logic circuit122are re-arranged in the layout depicted on the lower half ofFIG.5, and are embedded in the insulating film including the oxide film133, and in this state the wafer102having the oxide film junction layer135formed on the flattened uppermost surface becomes completed state.

In an eighth process, as depicted in the side cross-sectional view6H inFIG.8, wires134are formed for the wires121aof the memory circuit121, and the wires122aof the logic circuit122for electrical connection with the solid-state image pickup element120.

In a ninth process, as depicted in the side cross-sectional view6I inFIG.8, the wires134from the wires121aof the memory circuit121, and the wires122aof the logic circuit122on the wafer102, and the wires134from the wires120aof the solid-state image pickup element (CIS)120on the wafer101are aligned such that they are at appropriately facing positions.

In a tenth process, as depicted in the side cross-sectional view6J inFIG.9, the wafers101and102are bonded by WoW such that the wires134from the wires121aof the memory circuit121, and the wires122aof the logic circuit122on the wafer102, and the wires134from the wires120aof the solid-state image pickup element120on the wafer101are connected by CuCu-joining. By this process, each of the memory circuit121and the logic circuit122on the wafer102becomes electrically connected with each solid-state image pickup element120on the wafer101.

In an eleventh process, as depicted in the side cross-sectional view6K inFIG.9, a silicon layer which is an upper layer, in the figure, of the solid-state image pickup element120is made thin.

In a twelfth process, as depicted in the side cross-sectional view6L inFIG.9, the color filters and on-chip lenses pixels131are provided on the solid-state image pickup element120, and diced. Thereby, the solid-state image pickup apparatus111is completed.

With processes like the ones above, the solid-state image pickup apparatus111including a first layer on which the solid-state image pickup element120is formed, and a second layer on which the memory circuit121and the logic circuit122are formed is manufactured.

With such a configuration, the inter-circuit connection between the solid-state image pickup element120, and the memory circuit121and the logic circuit122can be formed by forming terminals at a wire density of very thin wires by the semiconductor lithography technology as in WoW. Accordingly, the number of connection terminals can be increased, the signal processing speed at each wire can be reduced, and so it becomes possible to attempt to reduce the power consumption.

In addition, only those confirmed to be good chips are connected as the memory circuit121and the logic circuit122. Accordingly, bad chips of each wafer, which is a drawback of WoW, decrease, and so the occurrence of yield loss can be reduced.

Further, unlike WoW, the memory circuit121and the logic circuit122to be connected can be arranged in an independent island-like manner as depicted on the lower half ofFIG.5by reducing their sizes as much as possible regardless of the chip size of the solid-state image pickup element120. Accordingly, it becomes possible to enhance the theoretical yield of the memory circuit121and the logic circuit122to be connected.

This means that the solid-state image pickup element120requires a minimum necessary pixel size for reacting to optical light, and so the process cost can be reduced because the process of manufacturing the solid-state image pickup element120does not necessarily require fine wiring processes. In addition, it becomes possible to reduce the power consumption by using a state-of-the-art fine wiring process for the process of manufacturing the logic circuit122. Further, it becomes possible to enhance the theoretical yield of the memory circuit121and the logic circuit122. As a result, it becomes possible to reduce the cost related to the manufacturing of the solid-state image pickup apparatus111.

In addition, because it is a structure in which chips can be re-arrayed and joined on a wafer, it becomes possible to stack on one chip even in the case of processes involving different types in which case it is difficult to fabricate, in the same wafer, an analog circuit such as a power supply IC or a clock, and a logic circuit122which are configured by totally different processes, or even in a case where there are differences of wafer sizes.

In addition, while the memory circuit121and the logic circuit122are used as circuits to be connected to the solid-state image pickup element120in the example explained above, circuits that are used may be other than the memory circuit121and the logic circuit122, like circuits related to the control of the solid-state image pickup element120, circuits related to the processing of pixel signals generated by image-capturing, and the like as long as those circuits are signal processing circuits considered to be required for the operation of the solid-state image pickup element120. Examples of the signal processing circuits considered to be required for the operation of the solid-state image pickup element120may include, for example, a power supply circuit, an image signal compression circuit, a clock circuit, an optical communication conversion circuit and the like.

3. Second Embodiment

The solid-state image pickup apparatus111explained above has a two-layer configuration including stacked layers, which are layer on which the solid-state image pickup element120is formed, and a layer on which the memory circuit121and the logic circuit122are re-arranged.

However, in a CoC (Chip On Chip) in which plural chips are mounted on one chip (a CoC on which two chips, which are the memory circuit121and the logic circuit122, are mounted on a chip of the one solid-state image pickup element120) as mentioned above, as depicted inFIG.10, it is necessary to form, on a surface of a semiconductor element (solid-state image pickup element120) with a large size, wires (hereinafter, also referred to as communication wires) for connecting two chips, which are the memory circuit121and the logic circuit122, that are arranged being arrayed on a plane.

FIG.10is a side cross-sectional view of the solid-state image pickup apparatus111more specifically representing internal terminals and wires of each of the solid-state image pickup element (CIS)120, the memory circuit121and the logic circuit122included in the solid-state image pickup apparatus111depicted inFIG.5. Note that hereinafter, for convenience of explanations, the oxide film junction layer135is omitted from illustrations, but is present.

As depicted inFIG.10, along a junction surface F1on which the solid-state image pickup element120and the memory circuit121face each other, pads120band121belectrically connected with the wires120aand121a, respectively, are mutually CuCu-joined. Similarly, along the junction surface F1on which the solid-state image pickup element120and the logic circuit122face each other, pads120band122belectrically connected with wires120aand122a, respectively, are mutually CuCu-connected.

In addition, each pad120bof the solid-state image pickup element120is connected to various types of circuit, a wire120aor another pad120bvia a wire120c. In addition, each pad121bof the memory circuit121is connected to a wire121avia a wire121c. Further, each pad122bof the logic circuit122is connected to a wire122avia a wire122c.

Note that each wire134inFIG.5has a configuration which is an aggregation of wires120c, pads120band121b, and wires121c.

In addition, configurations that are in each of the wires120a,121a, and122a, the pads120b,121b, and122band the wires120c,121c, and122c, and need to be particularly distinguished from one another are given separate reference signs each with “-” at the end of its reference character.

That is, pads122b-1and122b-2of the logic circuit122are CuCu-joined with pads120b-1and120b-2of the solid-state image pickup element120, and pads121b-2and121b-1of the memory circuit121are CuCu-joined with pads120b-3and120b-4of the solid-state image pickup element120.

In addition, the pad120b-1of the solid-state image pickup element120is connected with a wire120c-1. In addition, the pads120b-2and120b-3are interconnected via a wire120c-2. Further, a pad120c-4is connected with a wire120c-3.

With such a configuration, the solid-state image pickup element120and the memory circuit121are electrically connected via the wire120c-2.

The memory circuit121and the logic circuit122are connected via the wire120c-2in the solid-state image pickup element120with the largest chip area size.

That is, inFIG.10, the wire120c-2functions as a communication wire between the memory circuit121and the logic circuit122.

Here, with reference toFIG.11, the configuration of wires is explained by referring to a configuration which has the wire120c-2to be the communication wire as the center of the configuration, and includes selected pads and wires which are the pad120b-1to120b-4and the wires120c-1to120c-3of the solid-state image pickup element120, the wires121a-1and121a-2, the pads121b-1and121b-2, and the wires121c-1and121c-2of the memory circuit121, and the wires122a-1and122a-2, the pads122b-1and122b-2, and the wires122c-1and122c-2of the logic circuit122.

As depicted inFIG.11, in a case where the wire120c-2functions as the communication wire of the memory circuit121and the logic circuit122, the memory circuit121and the logic circuit122are electrically connected via the wire (pad)121a-2, the wire121c-2, the pads121b-2and120b-3, the wire120c-2, the pads120b-2and122b-2, the wire122c-2, and the wire (pad)122a-2.

If such a wire configuration is adopted, processes for forming the communication wire increase in a process of manufacturing the solid-state image pickup element120, the yield loss according to the process increase occurs. In addition, because the memory circuit121and the logic circuit122are connected via the wire120c-2of the solid-state image pickup element120, the signal line distance increases due to restrictions in terms of layout, or the power consumption increases by forming aggregated wires.

In view of this, in the solid-state image pickup apparatus111in a configuration example of a second embodiment of the present disclosure, as depicted inFIG.12, a communication wire connecting the memory circuit121and the logic circuit122is formed in the semiconductor element layer E2on which the memory circuit121and the logic circuit122are formed, and the pads121band122bare mutually electrically connected.

That is, the solid-state image pickup apparatus111inFIG.12is different from the solid-state image pickup apparatus111inFIG.10in terms of the configuration of the semiconductor element layer E2.

It should be noted however that pads120b-11to120b-14and wires120c-11and120c-14of the solid-state image pickup element120in the configuration inFIG.12correspond to the pads120b-1to120b-4and the wires120c-1and120c-3of the solid-state image pickup element120inFIG.10, respectively.

In addition, wires121a-11and121a-12, pads121b-11and121b-12, and wires121c-11and121c-12of the memory circuit121inFIG.12correspond to the wires121a-1and121a-2, the pads121b-1and121b-2, and the wires121c-1and121c-2of the memory circuit121inFIG.10, respectively.

Further, wires122a-11and122a-12, pads122b-11and122b-12, and wires122c-11and122c-12of the logic circuit122inFIG.12correspond to the wires122a-1and122a-2, the pads122b-1and122b-2, and the wires122c-1and122c-2of the logic circuit122inFIG.10, respectively.

That is, in the semiconductor element layer E2inFIG.12, a wiring layer is formed between the memory circuit121and the logic circuit122, and the pads121band122b, and wires121c′-1and122c′-1which are extensions of the wires121cand122care formed.

Further, in the same wiring layer where the wires121c′-1and122c′-1are formed, a communication wire T that connects a wire121c-12of the memory circuit121, and a wire122c-12of the logic circuit122is formed.

In addition, as depicted inFIG.13, it becomes possible to electrically connect the memory circuit121and the logic circuit122directly by the communication wire T, without connecting them via the wires120cof the solid-state image pickup element120.

That is, as depicted in an area Z1indicated by a dotted line inFIG.13, it becomes unnecessary to form a communication wire or aggregate other wires for forming a communication wire in the solid-state image pickup element120. Accordingly, it becomes possible to suppress a process increase of the solid-state image pickup element120, and it becomes possible to enhance the yield.

In addition, because it is possible to suppress an increase of the distances of wiring paths, it becomes possible to suppress an increase of power consumption.

Further, the total area size of the memory circuit121and the logic circuit122is smaller than that of the solid-state image pickup element120, and so it becomes possible to expand the wire pitch of121c′-1and122c′-1to the extent as allowed by the area size of the solid-state image pickup element120as depicted inFIG.12, for example, by using unoccupied areas.

Thereby, by expanding the wire pitch in an area Z2indicated by a dotted line inFIG.13, the influence of defects is reduced. Accordingly, it becomes possible to enhance the yield, and it becomes possible to reduce the power consumption.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.12>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.12is explained with reference to a flowchart inFIG.14, and side cross-sectional views inFIG.15toFIG.22.

First, a method of manufacturing a logic circuit122is explained.

In a process in Step S11(Logic_FEOL), a wiring pattern is formed on a board of each logic circuit122by FEOL (Front-End-Of-Line: board process) on the wafer104inFIG.4, for example.

In a process in Step S12(Logic_BEOL), wires are formed with a metal such as AL or Cu along the wiring pattern on the board of the logic circuit122by BEOL (Back-End-Of-Line: wiring process).

In a process in Step S13(Logic_Inspection (KGD)), as depicted in a side cross-sectional view15A inFIG.15, a measurement terminal C is used to perform an inspection of the wires (pads)122cof the logic circuit122, and on the basis of results of the inspection, a logic circuit122to be a good element is selected.

In a process in Step S14(embed pad), as depicted in a side cross-sectional view15B inFIG.15, the wires (pads)122cof the logic circuit122are embedded in a Si oxide film122L by plasma CVD (Chemical Vapor Deposition).

In a process in Step S15(flatten embedment), as depicted in a side cross-sectional view15C inFIG.15, embedment steps LD (see the side cross-sectional view15B) formed with the Si oxide film122L of the logic circuit122are polished and flattened by CMP (Chemical Mechanical Polishing).

In a process in Step S16(Logic Dicing), logic circuits122on the wafer104are separated into pieces by dicing, and good elements are extracted.

As mentioned above, by the processes in Steps S11to S16, the logic circuit122is manufactured.

Next, a method of manufacturing a memory circuit121is explained.

In a process in Step S21(Memory_FEOL), a wiring pattern is formed on a board of each memory circuit121by FEOL (Front-End-Of-Line: board process) on the wafer103inFIG.4, for example.

In a process in Step S22(Memory_BEOL), wires are formed with a metal such as AL or Cu along the wiring pattern on the board of the memory circuit121by BEOL (Back-End-Of-Line: wiring process).

In a process in Step S23(Memory_Inspection (KGD: Known Good Die)), as depicted in a side cross-sectional view16A inFIG.16, the measurement terminal C is used to perform an inspection of the wires (pads)121cof the memory circuit121, and on the basis of results of the inspection, a memory circuit121to be a good element is selected.

In a process in Step S24(embed pad), as depicted in a side cross-sectional view16B inFIG.16, the wires (pads)121cof the memory circuit121are embedded in a Si oxide film121M by plasma CVD (Chemical Vapor Deposition).

In a process in Step S25(flatten embedment), as depicted in a side cross-sectional view16C inFIG.16, embedment steps MD (see the side cross-sectional view16B) formed with the Si oxide film121M of the memory circuit121are polished and flattened by CMP (Chemical Mechanical Polishing).

In a process in Step S26(Memory_Dicing), logic circuits122on the wafer103are separated into pieces by dicing, and good elements are extracted.

As mentioned above, by the processes in Steps S21to S26, the memory circuit121is manufactured.

Next, a process of re-arranging a manufactured memory circuit121and logic circuit122on the re-arrangement board151is explained.

In a process in Step S31(Memory_die CoW), as depicted in a side cross-sectional view17A inFIG.17, a junction Si oxide film is formed on the re-arrangement board151by CVD, and the memory circuit121is temporarily connected such that a surface thereof provided with wires (pads)121cabuts against the junction Si oxide film (Face down). Examples of the connection method for the temporary connection include oxide-film joining such as plasma joining.

In addition, for the temporary connection, a method other than oxide-film joining such as plasma joining may be used, and, for example, a commercially available temporary joint tape or the like may be used. Note that it becomes possible to enhance the connection quality by forming an alignment mark for each CoW in advance on the side of the re-arrangement board151.

In a process in Step S32(Logic_die CoW), as depicted in a side cross-sectional view17B inFIG.17, the logic circuit122is temporarily connected such that a surface thereof provided with wires (pads)122cabuts against the re-arrangement board151(Face down).

In a process in Step S33(embed die), as depicted in a side cross-sectional view17C inFIG.17, a gap between the memory circuit121and the logic circuit122is filled (partially) with the oxide film133by plasma CVD, and the diced memory circuit121and logic circuit122are fixed to the re-arrangement board151.

In a process in Step S34(make die thin), as depicted in a side cross-sectional view18A inFIG.18, Si boards of the diced memory circuit121and logic circuit122are made thin. More specifically, grinding is performed at high speed by a grinder, and CMP is performed for a surface quality improvement.

In a process in Step S35(embed dei), as depicted in a side cross-sectional view18B inFIG.18, the oxide film133is formed until steps are filled again by plasma CVD or the like for the purpose of filling the gap between the memory circuit121and logic circuit122having been made thin.

In a process in Step S36(embedment surface CMP), as depicted in a side cross-sectional view18C inFIG.18, a step KD formed on the surfaces of the memory circuit121and the logic circuit122is flattened by CMP. At this time, the memory circuit121and the logic circuit122are finished such that their Si film thicknesses are within the range approximately of 1 to 10 um.

By the processes up to this point, the memory circuit121and the logic circuit122are re-arranged on the re-arrangement board151and are embedded in the oxide film133.

Next, a process in which the memory circuit121and the logic circuit122re-arranged on the re-arrangement board151are formed on the support board132is explained.

In a process in Step S41(permanently join WoW), as depicted in a side cross-sectional view19A inFIG.19, the support board132on which a Si oxide film is formed is permanently joined by plasma joining on the memory circuit121and the logic circuit122re-arranged on the re-arrangement board151.

In a process in Step S42(debond re-arrangement board), as depicted in a side cross-sectional view19B inFIG.19, the re-arrangement board151is debonded and peeled.

In a process in Step S43(form communication wire), as depicted in a side cross-sectional view20B inFIG.20, the oxide film133is further accumulated additionally. Then, as depicted in a side cross-sectional view20C inFIG.20, the communication wire T to connect the memory circuit121and the logic circuit122is formed.

In a process in Step S44(form Cu—Cu connection wire (etc.)), as depicted in a side cross-sectional view20C inFIG.20, pads121band122bfor electrical connection with the solid-state image pickup element120are formed.

Note that the communication wire T may include plural wires depending on the pitches of the pads121band122bas represented by communication wires T1to T5as depicted inFIG.21. In addition, as represented by the communication wires T3to T5, the communication wires may be formed in an area outside the arrangement area of the memory circuit121and the logic circuit122.

Further, the pads121band122bmay be formed on a grid in the area of the solid-state image pickup element120to be stacked thereafter. In addition, the communication wires may be connected to another circuit or the like other than the memory circuit121and the logic circuit122as represented by a communication wire T6such that the memory circuit121or the logic circuit122is individually connected with another circuit.

Note thatFIG.21includes a top view of the support board132on the upper half, and a side view of the support board132on the lower half. In addition, an area surrounded by a dotted line in the top view inFIG.21is an area on which the solid-state image pickup element120is to be stacked.

By the processes above, after the wafer on which the memory circuit121and the logic circuit122are re-arranged is formed, the memory circuit121and the logic circuit122are connected by the communication wire T, and further the pads121band122bfor connection with the solid-state image pickup element120are formed.

Next, the manufacturing of a solid-state image pickup element120is explained.

In a process in Step S51(CIS_FEOL), a wiring pattern is formed on a board of each solid-state image pickup element120by FEOL (Front-End-Of-Line: board process) on the wafer101inFIG.4, for example.

In a process in Step S52(Logic_BEOL), wires are formed with a metal such as AL or Cu along the wiring pattern on the board of the solid-state image pickup element120by BEOL (Back-End-Of-Line: wiring process).

In a process in Step S53(flatten embedment), although an illustration is omitted, the pads120bof the solid-state image pickup element120are embedded in a Si oxide film by plasma CVD (Chemical Vapor Deposition), and embedment steps including the Si oxide film are polished and flattened by CMP (Chemical Mechanical Polishing).

In a process in Step S54(form Cu—Cu connection wire (etc.)), as depicted in a side cross-sectional view22A inFIG.22, the pads120bfor electrical connection with the solid-state image pickup element120are formed, and the wafer101of the solid-state image pickup element120is completed.

As mentioned above, the solid-state image pickup element120is manufactured by the processes in Steps S51to S54.

Next, a process in which the wafer102on which the memory circuit121and the logic circuit122are re-arranged, and in which the mutual communication wire T is formed, and the wafer101of the solid-state image pickup element120are joined to manufacture the solid-state image pickup apparatuses111is explained.

In a process in Step S61(permanent (Cu—Cu joining WoW)), as depicted in a side cross-sectional view22B inFIG.22, the pads120bof the solid-state image pickup element120, and the pads121bof the memory circuit and the pads122bof the logic circuit122are CuCu-joined (direct joining).

In a process in Step S62(backside CIS process), as depicted in a side cross-sectional view22C inFIG.22, the solid-state image pickup element120is made thin, and a protective film is formed. Thereafter, as depicted in a side cross-sectional view22D ofFIG.22, the color filters and on-chip lenses pixels131are formed.

With the series of processes above, the solid-state image pickup apparatus111inFIG.12formed with the communication wire of the memory circuit121and the logic circuit122not going through the solid-state image pickup element120is manufactured.

Because, as a result, it becomes unnecessary to form a communication wire that goes through the solid-state image pickup element120, it becomes possible to suppress a process increase in the manufacturing of the solid-state image pickup element120, and it becomes possible to enhance the yield.

In addition, because the degree of freedom of the placement of wires is enhanced, it becomes possible to make wire lengths short and to increase wires, and it becomes possible to stabilize power supplies, and to reduce power consumption.

Further, the degree of freedom of the formation of light-blocking films for measures against hot carrier is improved.

In addition, because it becomes possible to place communication wires around in an area as larger as or larger than the area size of the solid-state image pickup element120, it becomes possible to expand wire pitches, and it becomes possible to suppress the deterioration of the yield.

Further, it becomes unnecessary to aggregate wires, and the wire density is reduced. Accordingly, the electrical resistance can be lowered, and so it becomes possible to attempt to reduce the power consumption.

4. Application Example of Second Embodiment

While in the example explained above, the communication wire T of the memory circuit121and the logic circuit122is formed in the semiconductor element layer E2, and on a side of the boundary with the solid-state image pickup element120, it may be formed in another area as long as it is possible to join the memory circuit121and the logic circuit122.

For example, the communication wire may be formed in the semiconductor element layer E2, and on a side of the boundary with the support board132.

FIG.23depicts the solid-state image pickup apparatus111in which a communication wire T′ is formed in the semiconductor element layer E2, and on a side of the boundary with the support board132.

In the case of the solid-state image pickup apparatus111inFIG.23also, it becomes possible to attain effects similar to the effects attained with the solid-state image pickup apparatus111inFIG.12having the communication wire T formed therein.

Note that the solid-state image pickup apparatus111inFIG.23is similar to the solid-state image pickup apparatus111inFIG.12in other respects than that the communication wire T′ is formed in the memory circuit121and the logic circuit122, and on a side of the boundary with the support board132, and so an explanation regarding a method of manufacturing the solid-state image pickup apparatus111inFIG.23is omitted.

5. Third Embodiment

In the explanation above, the connections between the solid-state image pickup element120, and the memory circuit121and the logic circuit122are formed between wires CuCu-joined with the pads120band the pads121band122bconnected at a junction surface F2.

However, because it is sufficient as long as the solid-state image pickup element120, and the memory circuit121and the logic circuit122are electrically connected, they may be connected by another method.

Electrical connections between the solid-state image pickup element120, and the memory circuit121and the logic circuit122may go through through-electrodes TCV (Through Chip Via), for example.

That is, in the solid-state image pickup apparatus111inFIG.24, the solid-state image pickup element120, and the memory circuit121are connected by a through-electrode TCV1, and the solid-state image pickup element120and the logic circuit122are connected by a through-electrode TCV2. The through-electrodes TCV1and TCV2include Cu, and insulating films are formed on surfaces thereof.

More specifically, the memory circuit121is provided with a pad121bto be connected with the through-electrode TCV1, and the logic circuit122is provided with a pad122bto be connected with the through-electrode TCV2.

In addition, the pad121bof the memory circuit121, and the pad122bof the logic circuit122are formed when the communication wire T is formed.

With such a configuration, processes of forming the pad120bin the solid-state image pickup element120, the pad121bof the memory circuit121and the pad122bof the logic circuit122can be omitted, and so it becomes possible to reduce the yield.

In addition, because wires can be placed in spaces in which the pad120bin the solid-state image pickup element120, the pad121bof the memory circuit121and the pad122bof the logic circuit122are provided, it becomes possible to reduce the resistance of wires, and to reduce the power consumption.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.24>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.24is explained with reference to a flowchart inFIG.25.

Note that the processes of manufacturing the memory circuit121, the logic circuit122, and the re-arrangement board151are similar to those in the flowchart inFIG.14, and so are omitted in the flowchart inFIG.25.

In addition, the processes in Steps S71, S72, S81to S83, S91, and S93inFIG.25are similar to the processes in Steps S41, S42, S51to S53, S61, and S62explained with reference toFIG.14, and so explanations thereof are omitted.

That is, in the flowchart inFIG.25, the communication wire T is formed in a process in Step S73(form communication wire (etc.)). At this time, the pad121bof the memory circuit121, and the pad122bof the logic circuit122for the connection with the through-electrodes TCV1and TCV2are formed at positions corresponding to the through-electrodes TCV1and TCV2.

Then, in a process in Step S92(connect vertical die (TCV)), through-holes are formed at the positions of the through-electrodes TCV1and TCV2inFIG.24through the Si board of the solid-state image pickup element120, and thereafter the through-holes are filled with Cu, and formed as electrodes.

With such a process, the solid-state image pickup apparatus111inFIG.24is manufactured.

In addition, because wires can be placed in spaces in which the pad120bin the solid-state image pickup element120, the pad121bof the memory circuit121, and the pad122bof the logic circuit122are provided, it becomes possible to reduce the resistance of wires, and to reduce the power consumption.

6. Fourth Embodiment

While in the example explained above, the junction surface F2is formed in a state in which the wiring layer side of the memory circuit121and the logic circuit122, and the wiring layer side of the solid-state image pickup element120are facing each other, through-electrodes may be formed on a surface (a surface on the side of the Si board) opposite to the wiring layers of the memory circuit121and the logic circuit122, and joined with the solid-state image pickup element120.

FIG.26depicts the solid-state image pickup apparatus111in which through-electrodes TSV (Through Silicon Via) are formed on a surface opposite to the wiring layers of the memory circuit121and the logic circuit122, and joined with the solid-state image pickup element120.

That is, the solid-state image pickup apparatus111inFIG.26is different from the solid-state image pickup apparatus111inFIG.12in that the memory circuit121and the logic circuit122are vertically reversed in the figure, and have through-electrodes121dand122dformed on the backsides thereof (the Si-board sides thereof to be the top surfaces inFIG.26), and wires121c′ and122c′ are connected to the pads121band122bvia through-electrodes (TSV).

With such a configuration, it becomes possible to attain effects similar to the effects attained with the solid-state image pickup apparatus111in the first embodiment.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.26>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.26is explained with reference to a flowchart inFIG.27, and side cross-sectional views inFIG.28toFIG.32.

Note that, in the flowchart inFIG.27, the processes of manufacturing the memory circuit121and the logic circuit122are similar to Steps S11to S16, and Steps S21to S26in the flowchart inFIG.14, and so explanations thereof are omitted.

In addition, the processes in Steps S111to S114which are the processes of manufacturing the solid-state image pickup element120are similar to the processes in Steps S51to S54inFIG.14, and so explanations thereof are omitted.

Further, because the re-arrangement board151is not used as described below, there are no processes related to the re-arrangement board151.

That is, in a process in Step S101(Memory_die CoW), as depicted in a side cross-sectional view28A inFIG.28, a junction Si oxide film is formed on the support board132by CVD, and the memory circuit121is connected such that a surface thereof provided with wires (pads)121cabuts against the junction Si oxide film (Face down). Examples of the connection method include oxide-film joining such as plasma joining.

In addition, for the connection, a method other than oxide-film joining such as plasma joining may be used, and, for example, a commercially available temporary joint tape or the like may be used. Note that it becomes possible to enhance the connection quality by forming an alignment mark for each CoW in advance on the side of the re-arrangement board151.

In a process in Step S102(Logic_die CoW), as depicted in a side cross-sectional view28B inFIG.28, the logic circuit122is connected such that a surface thereof provided with wires122cabuts against the support board132(Face down).

In a process in Step S103(make die thin), as depicted in a side cross-sectional view28C inFIG.28, a gap between the memory circuit121and the logic circuit122is filled (partially) with the oxide film133by plasma CVD, and the diced memory circuit121and logic circuit122are fixed to the support board132.

Further, as depicted in a side cross-sectional view29A inFIG.29, Si boards of the diced memory circuit121and logic circuit122are made thin. More specifically, grinding is performed at high speed by a grinder, and CMP is performed for a surface quality improvement.

In a process in Step S104(embed dei), as depicted in a side cross-sectional view29B inFIG.29, the oxide film133is formed until steps are filled again by plasma CVD or the like for the purpose of filling the gap between the memory circuit121and logic circuit122having been made thin.

Further, as depicted in a side cross-sectional view29C inFIG.29, a step KD formed on the surfaces of the memory circuit121and the logic circuit122is flattened by CMP. At this time, the memory circuit121and the logic circuit122are finished such that their Si film thicknesses are within the range approximately of 1 to 10 um.

By the processes up to this point, the memory circuit121and the logic circuit122are re-arranged on the support board132and are embedded in the oxide film133.

In a process in Step S105(rewire & form pad), plasma SiO2 is formed such that the thickness becomes approximately 100 to 1500 nm for the purpose of insulating the Si films of the memory circuit121and the logic circuit122after CMP.

Subsequently, as depicted in a side cross-sectional view30A inFIG.30, groove sections121e,122e, and Te corresponding to wires to connect the memory circuit121and the logic circuit122are formed by resist patterning and oxide film dry etching.

At this time, the groove sections121e,122e, and Te are formed down to depths that do not reach Si of the memory circuit121and the logic circuit122.

Further, as depicted in a side cross-sectional view30A inFIG.30, through-holes121fand122fare formed as openings to reach depths immediately before reaching copper wires of the lowermost layer in the multi-layer wiring layer, or as openings to reach depths immediately before reaching Al pads at the uppermost layer, such that the through-holes121fand122fpenetrate Si of the memory circuit121and the logic circuit122from the areas of the groove sections121eand122eformed in the manner described above. The diameters of the through-holes121fand122fare approximately 1 to 5 um, for example.

In addition, insulating films including SiO2 are formed on the side walls of Si exposed as a result of the processing described above, and thereafter an etch-back process is performed to thereby eliminate SiO2 formed as protective films of bottom sections of the through-holes121fand122f, and make the wiring layers of the memory circuit121and the logic circuit122exposed.

Then, as depicted in a side cross-sectional view30B inFIG.30, after a barrier metal is formed, a metal such as Cu is embedded in the through-holes121fand122f, the surfaces are polished by CMP (Chemical Mechanical Polishing), and only the conductive materials of the groove sections121e,122e, and Te and the through-holes121fand122fare left.

Thereby, the communication wire T that connects the memory circuit121and the logic circuit122, and lead wires121c′ and122c′ from the through-electrodes121dand122dof the memory circuit121and the logic circuit122are formed in areas in the insulating spacer layer.

Further, as depicted in a side cross-sectional view30C inFIG.30, the pads121band122bfor CuCu-joining (hybrid joining) with the solid-state image pickup element120are formed.

Note that the communication wire T may include plural wires depending on the pitches of the pads121band122bas represented by the communication wires T1to T5inFIG.31. In addition, as represented by the communication wires T3to T5, the communication wires may be formed in an area that is in the arrangement area of the solid-state image pickup element120, and outside the arrangement area of the memory circuit121and the logic circuit122.

Further, the pads121band122bmay be formed on a grid in the area of the solid-state image pickup element120to be stacked thereafter. In addition, the communication wires may be connected to another circuit or the like other than the memory circuit121and the logic circuit122as represented by the communication wire T6such that the memory circuit121or the logic circuit122is individually connected with another circuit.

Note thatFIG.31includes a top view of the support board132on the upper half, and a side view of the support board132on the lower half. In addition, an area surrounded by a dotted line in the top view inFIG.31is an area on which the solid-state image pickup element120is to be stacked.

By the processes above, after the wafer on which the memory circuit121and the logic circuit122are re-arranged is formed, the memory circuit121and the logic circuit122are connected by the communication wire T, and further the pads121band122bfor connection with the solid-state image pickup element120are formed.

In addition, in processes in Step S111to Step S114(form Cu—Cu connection wire (etc.)), as depicted in a side cross-sectional view32A inFIG.32, the pads120bfor electrical connection with the pads121band122bof the memory circuit121and the logic circuit122are formed, and the wafer101of the solid-state image pickup element120is completed.

Then, in a process in Step S115(permanent (Cu—Cu joining WoW)), as depicted in a side cross-sectional view32B inFIG.32, the pads120bof the solid-state image pickup element120, and the pads121bof the memory circuit and the pads122bof the logic circuit122are CuCu-joined (direct joining).

In a process in Step S116(backside CIS process), as depicted in a side cross-sectional view32C inFIG.32, the solid-state image pickup element120is made thin, and a protective film is formed. Thereafter, as depicted in a side cross-sectional view32D ofFIG.32, the color filters and on-chip lenses130are formed.

With the series of processes above, the solid-state image pickup apparatus111inFIG.12formed with the communication wire of the memory circuit121and the logic circuit122not going through the solid-state image pickup element120is manufactured.

Because, as a result, it becomes unnecessary to form a communication wire that goes through the solid-state image pickup element120, it becomes possible to suppress a process increase in the manufacturing of the solid-state image pickup element120, and it becomes possible to reduce the occurrence of the yield.

In addition, because the degree of freedom of the placement of wires is enhanced, it becomes possible to make wire lengths short and to increase wires, and it becomes possible to stabilize power supplies, and to reduce power consumption.

Further, the degree of freedom of the formation of light-blocking films for measures against hot carrier is improved.

In addition, because it becomes possible to place communication wires around in an area as large as or larger than the area size of the solid-state image pickup element120, it becomes possible to expand wire pitches, and it becomes possible to suppress the deterioration of the yield.

Further, it becomes unnecessary to aggregate wires, and the wire density is reduced. Accordingly, the electrical resistance can be lowered, and so it becomes possible to attempt to reduce the power consumption.

7. Fifth Embodiment

While in the example explained above, a wiring layer is formed in each of the memory circuit121, the logic circuit122, and the solid-state image pickup element120, and the junction surface F2is formed in a state in which the memory circuit121, the logic circuit122, and the solid-state image pickup element120are facing one another, further a wiring layer may be formed also on the support board132, and a communication wire between the memory circuit121and the logic circuit122may be formed on the wiring layer on the support board132.

FIG.33depicts a configuration example of the solid-state image pickup apparatus111in which a wiring layer is formed also on the support board132, and a communication wire between the memory circuit121and the logic circuit122is formed via the wiring layer on the support board132.

That is, the solid-state image pickup apparatus111inFIG.33has a configuration that is different from the configuration of the solid-state image pickup apparatus111inFIG.26in that the solid-state image pickup element120, and the memory circuit121and the logic circuit122are electrically connected at a junction surface F4-1, and the memory circuit121and the logic circuit122, and the support board are electrically connected at a junction surface F4-2.

The memory circuit121and the logic circuit122have pads121b′ and122b′ formed therein on surfaces thereof that face the support board132, and at positions corresponding to pads132bforming the wiring layer of the support board132.

In addition, the support board132has the pads132bformed at positions facing the memory circuit121and the logic circuit122, and further wires132a, and a communication wire T″ between the memory circuit121and the logic circuit122are formed at a lower section inFIG.33.

The wires132acan be used for electrical connection and can also be used for positioning by being used as alignment marks.

The pads132bof the support board132, the pads121b′ of the memory circuit121, and the pads122b′ of the logic circuit122are CuCu-connected.

In the example depicted, in the solid-state image pickup apparatus111inFIG.33, communication wires between the memory circuit121and the logic circuit122include the two communication wires T and T″, but only any one of them may be provided.

With a configuration like the one above, it becomes unnecessary to form communication wires that go through the solid-state image pickup element120, and so a process increase is suppressed. Additionally, it becomes unnecessary to aggregate wires in the solid-state image pickup element120, and the wire density is reduced. Accordingly, it becomes possible to reduce the occurrence of the yield. In addition, for a similar reason, it is possible to reduce the electrical resistance, and so it becomes possible to attempt to reduce the power consumption.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.33>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.33is explained with reference to a flowchart inFIG.34, and side cross-sectional views inFIG.35toFIG.38.

Note that, in the flowchart inFIG.34, the processes of manufacturing the memory circuit121and the logic circuit122are similar to Steps S11to S16, and Steps S21to S26in the flowchart inFIG.14except for the processes in Steps S126and S136, and so explanations thereof are omitted.

In addition, the processes in Steps S142to S147which are the processes related to the support board132are similar to the processes in Steps S101to S106inFIG.27, and so explanations thereof are omitted.

Further, the processes in Steps S151to S154which are the processes of manufacturing the solid-state image pickup element120are similar to the processes in Steps S51to S54inFIG.14, and so explanations thereof are omitted.

That is, in a process in Step S126(form Cu—Cu connection pad), in the logic circuit122manufactured on the wafer104as depicted in a side cross-sectional view35A inFIG.35, the pads122b′ for CuCu-joining with the pads132bof the support board132are formed as depicted in a side cross-sectional view35B inFIG.35.

In addition, the pads122b′ are formed by a technique that is similar to the technique used in the case the through-electrodes122d, the wire122c′, and the pads122b′ in the solid-state image pickup apparatus111inFIG.26are formed in the process in Step S106explained with reference to the flowchart inFIG.27. After the pads121b′ are formed, the logic circuit122on the wafer104is diced, and a good element is extracted.

Note that, in Step S136, the pads121b′ are formed in the memory circuit121also by a similar technique, the memory circuit121is diced, and a good element is extracted.

In addition, in a process in Step S141(form communication wire (etc.)), as depicted inFIG.36, the wires132a, the communication wire T″, and the pads132bare formed on the support board132.

More specifically, a thermal oxide film, LP-SiN or the like is formed on the support board (bare Si)132not having a device structure, and is insulated from Si.

Subsequently, plasma SiO2 is formed to have a thickness of approximately 100 to 1500 nm, a wiring pattern for inter-chip connection with the line pitch width of 0.5 to 5 um is formed by resist-patterning depending on the layout of the pads121b′ and122b′ of the memory circuit121and the logic circuit122, and a groove section with the depth of 100 to 1000 nm is formed by dry etching.

After a Ta-based or Ti-based barrier metal is formed in the groove section, copper is embedded therein by electroplating, and excess copper at field sections is eliminated by CMP to thereby form inter-chip connections, and a wire132afrom each chip.

Subsequently, the pads132bfor CuCu-connection are formed by a technique similar to the technique used in the case where the through-electrodes122d, the wire122c′, and the pads122bare formed.

Note that, at this time, alignment marks for chip connection are formed simultaneously because the wires132aare used therefor, and so the alignment precision at the time of the formation of the communication wire T″ in the support board132can be increased.

In processes in Steps S142and S143(Memory_die CoW, Logic_die CoW), as depicted in a side cross-sectional view37A inFIG.37, on the support board132where the communication wire T″, the pads132b, and the wires132aas alignment marks are formed, the pads121b′ and122b′ of the memory circuit121and the logic circuit122are CuCu-joined (direct joining), and electrically connected such that the pads121b′ and122b′ of the memory circuit121and the logic circuit122are at positions corresponding to the positions of the pads132b.

In a process in Step S144(make die thin), a gap between the memory circuit121and the logic circuit122is filled (partially) with the oxide film133by plasma CVD, and the diced memory circuit121and logic circuit122are fixed to the support board132.

Further, Si boards of the diced memory circuit121and logic circuit122are made thin. More specifically, grinding is performed at high speed by a grinder, and CMP is performed for a surface quality improvement.

In a process in Step S145(embed dei), as depicted in a side cross-sectional view37B inFIG.37, the oxide film133is formed until steps are filled again by plasma CVD or the like for the purpose of filling the gap between the memory circuit121and logic circuit122having been made thin.

Further, a step formed on the surfaces of the memory circuit121and the logic circuit122is flattened by CMP. At this time, the memory circuit121and the logic circuit122are finished such that their Si film thicknesses are within the range approximately of 1 to 10 um.

In a process in Step S146(form TSV), plasma SiO2 is formed such that the thickness becomes approximately 100 to 1500 nm for the purpose of insulating the Si films of the memory circuit121and the logic circuit122after CMP.

Subsequently, as depicted in a side cross-sectional view37C inFIG.37, the groove sections121e,122e, and Te corresponding to wires to connect the memory circuit121and the logic circuit122are formed by resist patterning and oxide film dry etching.

At this time, the groove sections121e,122e, and Te are formed down to depths that do not reach Si of the memory circuit121and the logic circuit122.

Further, subsequently, the through-holes121fand122fare formed as openings to reach depths immediately before reaching copper wires of the lowermost layer in the multi-layer wiring layer, or as openings to reach depths immediately before reaching Al pads at the uppermost layer, such that the through-holes121fand122fpenetrate Si of the memory circuit121and the logic circuit122from the areas of the groove sections121eand122eformed in the manner described above. The diameters of the through-holes121fand122fare approximately 1 to 5 um, for example.

In a process in Step S147(rewire & form pad), as depicted in a side cross-sectional view37D inFIG.37, insulating films including SiO2 are formed on the side walls of Si exposed as a result of the processing described above, and thereafter an etch-back process is performed to thereby eliminate SiO2 formed as protective films of bottom sections of the through-holes121fand122f, and make the wiring layers of the memory circuit121and the logic circuit122exposed.

Then, after a barrier metal is formed, a metal such as Cu is embedded in the through-holes121fand122f, the surfaces are polished by CMP (Chemical Mechanical Polishing), and only the conductive materials of the groove sections121e,122e, and Te and the through-holes121fand122fare left.

Thereby, the communication wire T that connects the memory circuit121and the logic circuit122, and lead wires121c′ and122c′ from the through-electrodes121dand122dof the memory circuit121and the logic circuit122are formed in areas in the insulating spacer layer.

Further, the pads121band122bfor hybrid (Cu—Cu) connection with the solid-state image pickup element120are formed.

By the processes above, after the wafer on which the memory circuit121and the logic circuit122are re-arranged is formed, the memory circuit121and the logic circuit122are connected by the communication wires T and T″, and further the pads121band122bfor connection with the solid-state image pickup element120are formed.

In addition, in a process in Step S151to Step S154(form Cu—Cu connection wire (etc.)), the pads120bare formed, and the wafer101of the solid-state image pickup element120is completed.

Then, in a process in Step S155(permanent (Cu—Cu joining WoW)), as depicted in a side cross-sectional view38A inFIG.38, the pads120bof the solid-state image pickup element120, and the pads121bof the memory circuit and the pads122bof the logic circuit122are CuCu-joined.

In a process in Step S156(backside CIS process), as depicted in a side cross-sectional view32B inFIG.38, the solid-state image pickup element120is made thin, and a protective film is formed. Thereafter, as depicted in a side cross-sectional view38C ofFIG.38, the color filters and on-chip lenses130are formed.

With the series of processes above, the solid-state image pickup apparatus111inFIG.33formed with the communication wires T and T″ of the memory circuit121and the logic circuit122not going through the solid-state image pickup element120is manufactured.

Because, as a result, it becomes unnecessary to form a communication wire that goes through the solid-state image pickup element120, it becomes possible to suppress a process increase in the manufacturing of the solid-state image pickup element120, and it becomes possible to enhance the yield.

In addition, because the degree of freedom of the placement of wires is enhanced, it becomes possible to make wire lengths short and to increase wires, and it becomes possible to stabilize power supplies, and to reduce power consumption.

Further, the degree of freedom of the formation of light-blocking films for measures against hot carrier is improved.

In addition, because it becomes possible to place communication wires around in an area as large as or larger than the area size of the solid-state image pickup element120, it becomes possible to expand wire pitches, and it becomes possible to suppress the deterioration of the yield.

Further, it becomes unnecessary to aggregate wires, and the wire density is reduced. Accordingly, the electrical resistance can be lowered, and so it becomes possible to attempt to reduce the power consumption.

8. Sixth Embodiment

The memory circuit121and the logic circuit122are re-arranged on the support board132including the communication wires, and the solid-state image pickup element120is stacked in the solid-state image pickup apparatus111in the explanation above; however, in another possible configuration, the logic circuit122may be stacked on a memory device board having the function of the memory circuit121instead of the support board132, and the solid-state image pickup element120may be stacked on the logic circuit122.

FIG.39depicts a configuration example of the solid-state image pickup apparatus111in which the logic circuit122is stacked on a memory device board having the function of the memory circuit121instead of the support board132, and the solid-state image pickup element120is stacked on the logic circuit122.

In the configuration of the solid-state image pickup apparatus111inFIG.39, instead of the support board132, a memory device board201having the function of the memory circuit121is provided, the logic circuit122is stacked on the memory device board201such that the logic circuit122is embedded in the oxide film133, and further the solid-state image pickup element120is stacked on the logic circuit122.

In addition, the solid-state image pickup element120, and the logic circuit122and the memory device board201are CuCu-joined and electrically connected at a junction surface F5-1through the pads120b, and the pads201b′ and122b.

More specifically, in the oxide film133in which the logic circuit122is embedded, the pads201b′, wires201c, and through-electrodes201dare formed in a state in which the pads201b′, the wires201c, and the through-electrodes201dare connected with each other, and the pads201bof the memory device board201, and the through-electrodes201dare connected at a junction surface F5-2.

Thereby, the memory device201and the solid-state image pickup element120are electrically connected via the pads201b′, the wires201cand the through-electrodes201d, and the pads201b.

Further, the logic circuit122and the memory device board201are CuCu-joined and electrically connected at the junction surface F5-2through the pads201band122b. Stated differently, the CuCu-joined pads201band122bsubstantially function as communication wires.

With such a configuration, communication wires become unnecessary by stacking the memory circuit121and the logic circuit122. Accordingly, it becomes unnecessary to form communication wires to go through the solid-state image pickup element120, and it becomes possible to suppress a process increase.

In addition, it becomes unnecessary to aggregate wires in the solid-state image pickup element120, and the wire density is reduced. Accordingly, it becomes possible to enhance the yield, and additionally the electrical resistance can be lowered; as a result, it becomes possible to attempt to reduce the power consumption.

Note that, in the configuration example of the solid-state image pickup apparatus111depicted inFIG.39, instead of the support board132, the memory device board201having the function of the memory circuit121is provided, and is stacked such that the logic circuit122is sandwiched between the memory device board201and the solid-state image pickup element120. However, instead of the support board132, a logic device board having the function of the logic circuit122may be provided, and stacked such that the memory circuit121is sandwiched between the logic device board and the solid-state image pickup element120, in another possible configuration.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.39>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.39is explained with reference to a flowchart inFIG.40, and side cross-sectional views inFIG.41toFIG.43.

Note that, in the flowchart inFIG.39, the processes of manufacturing the logic circuit122are similar to Steps S121to S127in the flowchart inFIG.34, and so explanations thereof are omitted. In addition, the processes in Steps S191to S194which are the processes of manufacturing the solid-state image pickup element120are similar to the processes in Steps S51to S54in the flowchart inFIG.14, and so explanations thereof are omitted.

Similarly to the processes in Steps S21and S22inFIG.14, in processes in Steps S171and S172(Memory_FEOL, Memory_BEOL), a wiring pattern for realizing the function as the memory circuit121is formed on the memory device board201, and wires are formed with a metal such as AL or Cu.

Note that an inspection may be performed after the process in Step S172(Memory_BEOL), and good dies and bad dies may be clearly identified in advance.

In a process in Step S173(rewire & form Cu—Cu connection pad), wires201aand the pads201bare formed. Here, alignment marks for connection are formed also.

In a process in Step S174(Logic_die CoW), as depicted in a side cross-sectional view41A inFIG.41, the pads201bof the memory device board201, and the pads122b′ of the logic circuit122are CuCu-joined. Note that, while an example in which only the logic circuit122is connected is explained with reference toFIG.41, plural circuit chips may be connected depending on functions.

In a process in Step S175(make die thin), the space around the logic circuit122on the memory device board201is filled with the oxide film133to thereby fix the logic circuit122onto the memory device board201, and thereafter the logic circuit122is made thin.

In a process in Step S176(embed die), as depicted in a side cross-sectional view41B inFIG.41, by repeating the process in Step S175, the logic circuit122is embedded in the oxide film133.

In processes in Steps S177and S178(form TSV, form memory connection via), as depicted in side cross-sectional views42A to42C inFIG.42, the through-electrodes122dthat penetrate Si of the logic circuit122, and the through-electrodes201dfor connection with the memory device board201are formed.

More specifically, as depicted in the side cross-sectional view42A inFIG.42, an insulating film221including plasma SiO2 is formed such that the thickness becomes 100 to 1500 nm, for the purpose of insulating Si after CMP. Then, an area where the pads201b′, the wires201cand the through-electrodes201dto connect the memory device board201and the solid-state image pickup element120are formed, and groove sections222that are corresponding to intra-stack connecting wires to be used when the solid-state image pickup element120and the logic circuit122are connected are formed by resist patterning and oxide film dry etching. At this time, the groove sections222are formed with depths that do not reach Si of the logic circuit122and the memory device201.

Next, after resists for processing of the groove sections222are eliminated, as depicted in a side cross-sectional view42B inFIG.42, vias223for connection with the memory device board201, and vias224for connection with the logic circuit122are formed by patterning, and dry etching of the oxide film133is performed first.

Because the oxide film133on the logic circuit122is thin, the vias224reach Si while the vias223of the memory device board201are being formed, but because the selection ratio of SiO2 and Si is high, Si is not processed, and the vias223and224with different depths are formed.

Note that, at this time, the SiO2 processing of the vias224is stopped before the vias223reach the pads201bon the memory device board201.

Thereafter, the etching condition is changed, and the vias223and224are processed. That is, after the processing resists are eliminated, the insulating film221including plasma SiO2 for insulating Si is formed, and thereafter an etch-back process performed. Thereby, vias223′ and254′ are formed simultaneously as depicted in a side cross-sectional view42C inFIG.42.

In a process in Step S179(rewire & form pad), as depicted in a side cross-sectional view43A inFIG.43, after a barrier metal is formed, a metal such as Cu is embedded in the vias223′ and224′, and the surfaces are polished by CMP (Chemical Mechanical Polishing).

By this process, only the conductive materials of the wires122c′ and201c, and the through-electrodes122dand201dare left. Thereby, the wires122c′ and201c, and the through-electrodes122dand201dwhich are lead wires from the memory device board201and the logic circuit122are formed.

Further, the pads201band122bfor CuCu-connection with the solid-state image pickup element120are formed.

In a process in Step S195(permanently (Cu—Cu) join WoW), as depicted in a side cross-sectional view43B inFIG.43, the pads120bof the solid-state image pickup element120, and the pads201band122b′ of the memory device board201and the logic circuit122are CuCu-joined.

In a process in Step S196(backside CIS process), as depicted in a side cross-sectional view43C inFIG.43, the solid-state image pickup element120is made thin, and a protective film is formed. Thereafter, as depicted in a side cross-sectional view43D ofFIG.43, the color filters and on-chip lenses pixels131are formed.

According to the solid-state image pickup apparatus111manufactured by the processes above, it becomes possible to reduce the number of processes before the solid-state image pickup element120with a large area size is joined, and it is possible to enhance the yield according to the reduction of processes.

In addition, because it becomes possible to form wires of the memory device board201and the logic circuit122without using wires of the solid-state image pickup element120, it becomes possible to enhance the degree of freedom of the placement of wires.

As a result, it becomes possible to make wire lengths short and to increase wires, and it becomes possible to stabilize power supplies, and to reduce power consumption. In addition, it becomes possible to enhance the degree of freedom of the formation of light-blocking films for measures against hot carrier.

Note that because it becomes possible to join at least any one of the memory circuit121and the logic circuit122after an inspection, it becomes possible to enhance the yield of the backside-illumination solid-state image pickup apparatus111to be finished.

9. Seventh Embodiment

<Manufacturing Method in which Memory Circuit and Logic Circuit are Stacked on Solid-State Image Pickup Element>

In the example explained above, the memory circuit121and the logic circuit122are stacked on the re-arrangement board151or the support board132and are embedded in the oxide film133, and the solid-state image pickup element120is stacked on the memory circuit121and the logic circuit122, to thereby manufacture the solid-state image pickup apparatus111.

However, the memory circuit121and the logic circuit122may be stacked on the solid-state image pickup element120and be embedded in the oxide film133, and the support board132may be stacked on the memory circuit121and the logic circuit122.

The configuration of the completed solid-state image pickup apparatus111is basically similar to that inFIG.10. In view of this, in the method of manufacturing the solid-state image pickup apparatus111explained here with reference to side cross-sectional views inFIG.44toFIG.46, the memory circuit121and the logic circuit122are stacked on the solid-state image pickup element120and are embedded in the oxide film133, and the support board132is stacked on the memory circuit121and the logic circuit122.

Note that it is assumed that the solid-state image pickup element120, the memory circuit121and the logic circuit122have been manufactured, and the memory circuit121and the logic circuit122have been diced, and selected as good elements as a result of an inspection.

In a first process, as depicted in a side cross-sectional view44A inFIG.44, the wires120aand the pads120bare formed in the solid-state image pickup element120.

In a second process, as depicted in a side cross-sectional view44B inFIG.44, the memory circuit121and the logic circuit122are stacked on the solid-state image pickup element120, and the pads120b, and the pads121band122bare CuCu-joined. At this time, because oxide-film connection is performed after a hydrophilic treatment, connection at the normal temperature is possible at the time of the CuCu-connection, and it becomes possible to highly precisely ensure the alignment between the solid-state image pickup element120, and the memory circuit121and the logic circuit122.

For example, the alignment precision is at a level that can satisfy 1 um<3σ. In addition, as depicted in the side cross-sectional view44B inFIG.44, after the alignment, the memory circuit121is tilted, and is caused to partially abut against the solid-state image pickup element120. In this state, the whole is joined. By this implementation, it becomes possible to suppress generation of voids due to entrainment, and enhance the reliability of the operation of the solid-state image pickup element120, the memory circuit121, and the logic circuit122. Further, it is possible to easily cope with even a case where the heights of the memory circuit121and the logic circuit122to be implemented are different. Note that, while the side cross-sectional view44B inFIG.44depicts a state where only the memory circuit121is tilted, and is caused to partially abut against the solid-state image pickup element120, the logic circuit122is also implemented by a similar technique.

In a third process, as depicted in a side cross-sectional view44C inFIG.44, Si of the memory circuit121and the logic circuit122is made thin. Considering the embeddability by the oxide film133, it is better if the memory circuit121and the logic circuit122are made as thin as possible before the embedment process using the oxide film133, or the like. In terms of ensuring the properties of the oxide film133and the like that allow embedment flattening, and in terms of an increase of the warp amount, the thicknesses of the memory circuit121and the logic circuit122are preferably made equal to or thinner than approximately 20 um, for example.

In a fourth process, as depicted in a side cross-sectional view45A inFIG.45, the memory circuit121and the logic circuit122are embedded in the oxide film133. If the oxide film133is an inorganic film, it is desirably a Si-based oxide film such as a SiO2 film, a SiO film, or a SRO film in terms of heat resistance and the warp amount after film formation. In addition, in a case where the oxide film133is an organic film, the oxide film133is preferably a polyimide-based (PI, PBO, etc.) oxide film, a polyamide-based oxide film or the like that can easily ensure high heat resistance.

In a fifth process, as depicted in a side cross-sectional view45B inFIG.45, groove sections121e′,122e′, and Te′ corresponding to wires to connect the memory circuit121and the logic circuit122are formed by resist patterning and oxide film dry etching.

At this time, the groove sections121e′,122e′, and Te′ are formed down to depths that do not reach Si of the memory circuit121and the logic circuit122.

Further, subsequently, through-holes121fand122fare formed as openings to reach depths immediately before reaching copper wires of the lowermost layer in the multi-layer wiring layer, or as openings to reach depths immediately before reaching Al pads at the uppermost layer, such that the through-holes121fand122fpenetrate Si of the memory circuit121and the logic circuit122from the areas of the groove sections121e′ and122e′ formed in the manner described above. The diameters of the through-holes121fand122fare approximately 1 to 5 um, for example.

In a sixth process, as depicted in a side cross-sectional view45C inFIG.45, insulating films including SiO2 are formed on the side walls of Si exposed as a result of the processing described above, and thereafter an etch-back process is performed to thereby eliminate SiO2 formed as protective films of bottom sections of the through-holes121fand122f, and make the wiring layers of the memory circuit121and the logic circuit122exposed.

Then, after a barrier metal is formed, a metal such as Cu is embedded in the through-holes121fand122f, the surfaces are polished by CMP (Chemical Mechanical Polishing), and only the conductive materials of the groove sections121e′,122e′, and Te′ and the through-holes121fand122fare left.

Thereby, a communication wire T′″ that connects the memory circuit121and the logic circuit122, and through-electrodes121d′ and122d′ of the memory circuit121and the logic circuit122are formed in areas in the insulating spacer layer.

In a seventh process, as depicted in a side cross-sectional view46A inFIG.46, the solid-state image pickup element120, the memory circuit121, and the logic circuit122in the state depicted in the side cross-sectional view45C inFIG.45are reversed vertically, and are connected onto the support board132.

Then, in an eighth process, as depicted in a side cross-sectional view46B inFIG.46, the Si board of the solid-state image pickup element120is made thin, and thereafter the color filters and on-chip lenses pixels131are formed.

By the processes above, it becomes possible to increase the theoretical yield, and it becomes possible to reduce the cost.

In addition, in a case where the configuration of the solid-state image pickup element120uses an organic photoelectric conversion film, in the eighth process, as depicted in a side cross-sectional view46C inFIG.46, in addition to the on-chip lenses10(color filters are not included inFIG.46), an organic photoelectric conversion film241may be formed between the on-chip lenses10and the solid-state image pickup element120.

In the case of the solid-state image pickup element120that uses the organic photoelectric conversion film241which has been proposed for the enhancement of pixel characteristics in recent years, the heat proof temperature of the organic photoelectric conversion film241is low, and cannot endure a solder connection temperature which requires heating at 200° C. or higher.

However, in the seventh embodiment of the present disclosure, it is possible to form the less heat-resistant organic photoelectric conversion film241after the stacking of chips, and a technology of fine CuCu joining can be applied. Accordingly, it becomes possible to realize the solid-state image pickup apparatus111including the solid-state image pickup element120having low dark current characteristics, while maintaining a high external quantum efficiency.

10. Eighth Embodiment

<Manufacturing Method in which Memory Circuit and Logic Circuit are Stacked on Solid-State Image Pickup Element>

In the example explained above, the memory circuit121and the logic circuit122are arrayed and stacked on the solid-state image pickup element120, and are embedded in the oxide film133, and the support board132is stacked on the memory circuit121and the logic circuit122, to thereby manufacture the solid-state image pickup apparatus111.

However, the solid-state image pickup apparatus111may be manufactured by stacking and arranging the memory circuit121and the logic circuit122on the solid-state image pickup element120, embedding the memory circuit121and the logic circuit122in the oxide film133, and stacking the support board132on the stacked memory circuit121and logic circuit122.

FIG.47depicts a configuration example of the solid-state image pickup apparatus111manufactured by stacking and arranging the memory circuit121and the logic circuit122on the solid-state image pickup element120, embedding the memory circuit121and the logic circuit122in the oxide film133, and stacking the support board132on the memory circuit121and logic circuit122.

That is, the logic circuit122is stacked on the support board132, further two memory circuits121-1and121-2are arrayed in the horizontal direction and stacked on the logic circuit122, and then the solid-state image pickup element120is stacked on the memory circuits121-1and121-2.

In addition, through-electrodes (TSV)231and232are formed in the memory circuits121-1and121-2, the solid-state image pickup element120and the logic circuit122are electrically connected via the through-electrodes231, and the memory circuit121and the logic circuit122are electrically connected via the through-electrodes232. That is, the through-electrodes232function as communication wires.

Note that the order in which the memory circuit121and the logic circuit122are stacked may be reversed, and, for example, the memory circuit121and the logic circuit122inFIG.47may be vertically reversed, in one possible configuration.

Because the solid-state image pickup apparatus111can be manufactured by stacking the good memory circuit121and logic circuit122in such a configuration also, it is possible to enhance the theoretical yield, and it becomes possible to reduce the cost.

In addition, for example, plural layers of memory circuits121and logic circuits122may be stacked further by a similar technique, and so it becomes possible to realize a capacity increase of a memory.

In particular, in a case where the solid-state image pickup element120that uses the organic photoelectric conversion film241(FIG.46) is used, there is a pixel signal for each wavelength of RGB. Accordingly, a large capacity memory that stores data once before performing signal processing is required. Because of this, by forming a structure in which memory circuits121are stacked at many stages, it becomes possible to increase the memory capacity effectively, and it becomes possible to effectively use the organic photoelectric conversion film241.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.47>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.47is explained with reference toFIGS.48and49.

Note that it is assumed that the solid-state image pickup element120, the memory device board201and the logic circuit122have been manufactured similarly to the memory circuit121and the logic circuit122, and the logic circuit122has been diced, and selected as a good element as a result of an inspection.

In a first process, as depicted in a side cross-sectional view48A inFIG.48, the wires120aand the pads120bare formed in the solid-state image pickup element120.

In a second process, as depicted in a side cross-sectional view48B inFIG.48, the logic circuit122is stacked on the solid-state image pickup element120, and the pads120band the pads122bare CuCu-joined.

In a third process, as depicted in a side cross-sectional view48C inFIG.48, Si of the logic circuit122is made thin, and the through-electrodes231and232are formed. The through-electrodes231are connected with the pads120bof the solid-state image pickup element120, and the through-electrodes232are connected with the pads122bof the logic circuit.

In a fourth process, as depicted in a side cross-sectional view48D inFIG.48, the memory circuits121-1and121-2are arranged being arrayed on the logic circuit122, and the through-electrodes231and232, and the pads121b-1and121b-2of the memory circuits121-1and121-2are CuCu-connected.

In a fifth process, as depicted in a side cross-sectional view49A inFIG.49, the memory circuits121-1and121-2are formed being embedded in the oxide film133, and further surfaces of the memory circuits121-1and121-2are flattened by CMP.

In a sixth process, as depicted in a side cross-sectional view49B inFIG.49, the state in the side cross-sectional view49A is reversed vertically, and the memory circuits121-1and121-2are connected and fixed onto the support board132.

In a seventh process, as depicted in a side cross-sectional view49C inFIG.49, the Si board of the solid-state image pickup element120is made thin, and thereafter the color filters and on-chip lenses pixels131are formed.

Note that, in a case where memory circuits121are stacked further, the memory circuits121are stacked at a necessary number of stages by repeating the fourth and fifth processes explained with reference to the side cross-sectional view48D inFIG.48, and the side cross-sectional view49A inFIG.49.

Because the solid-state image pickup apparatus111manufactured by the processes above also can be manufactured by stacking the good memory circuit121and logic circuit122, it is possible to enhance the theoretical yield, and it becomes possible to reduce the cost.

In addition, by stacking many stages of memory circuits121further, it becomes possible to realize a large capacity of a memory, and it becomes possible to stably realize signal processing in the solid-state image pickup element120like the one that uses the organic photoelectric conversion film241.

11. Ninth Embodiment

<Configuration Example of Solid-State Image Pickup Apparatus in which Wiring Layer is Formed on Side of Support Board, and Terminals of Wire Bonding are Formed>

While in the example explained above, the good memory circuit121and logic circuit122are stacked on the solid-state image pickup element120to manufacture the solid-state image pickup apparatus111, a wiring layer may be formed on the side of the support board, and terminals of wire bonding may be formed.

FIG.50depicts a configuration example of the solid-state image pickup apparatus111in which a wiring layer is formed on the side of the support board, and terminals of wire bonding are formed.

The solid-state image pickup apparatus111inFIG.50has a configuration in which wires261aare formed in a support board261and are electrically connected with terminals261bat left and right end sections. The wires261aare connected with the wires121aand122avia through-electrodes251and252that penetrate the Si boards of the memory circuit121and the logic circuit122. In addition, because the pads121band122bof the memory circuit121and the logic circuit122are CuCu-joined with the wires120aof the solid-state image pickup element120, the wires261aare electrically connected also with the solid-state image pickup element120via the memory circuit121and the logic circuit122.

The terminals261bare provided with bonding sections271to which wires272are connected, and the solid-state image pickup apparatus111has a configuration that can transmit and receive signals to and from an external apparatus via the wires272via the bonding sections271.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.50>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.50is explained with reference toFIG.51andFIG.52. Note that it is assumed that the solid-state image pickup element120, the memory circuit121, and the logic circuit122have been manufactured, and the memory circuit121and the logic circuit122have been diced, and selected as good elements as a result of an inspection.

In addition, an explanation is given below assuming that the wires120aand the pads120bhave been formed on the solid-state image pickup element120, the memory circuit121, and the logic circuit122have been stacked on the solid-state image pickup element120, the pads120b, and the pads121band122bhave been CuCu-joined and embedded in the oxide film133, and Si of the memory circuit121and the logic circuit122have been made thin, and flattened.

In a first process, as depicted in a side cross-sectional view51A inFIG.51, the through-electrodes251and252are formed to the wires121aand122ain the Si boards of the memory circuit121and the logic circuit122.

In a second process, as depicted in a side cross-sectional view51B inFIG.51, the configuration in the side cross-sectional view51A inFIG.51is vertically reversed, and is joined to the support board261in which the wires261aand the terminals261bare formed. At this time, the through-electrodes251and252are joined with the wires261aof the support board261.

In a third process, as depicted in a side cross-sectional view51C inFIG.51, the Si board of the solid-state image pickup element120is made thin.

In a fourth process, as depicted in a side cross-sectional view52A inFIG.52, the color filters and on-chip lenses pixels131are formed on the solid-state image pickup element120.

In a fifth process, as depicted in a side cross-sectional view52B inFIG.52, the oxide film133and the solid-state image pickup element120that are in upper sections of the terminals261bsurrounded by dotted lines in the figure are partially cut out, and the terminals261bare made exposed.

In a sixth process, as depicted in a side cross-sectional view52C inFIG.52, the wires272are connected with the terminals261bvia the bonding sections271, and the solid-state image pickup apparatus111is completed.

In such a manufacturing method also, it becomes possible to enhance the theoretical yield, and so it becomes possible to reduce the cost.

In addition, by manufacturing by such processes, for example, if the wires272are to be connected by the bonding sections271by providing through-holes282on the terminals261bas depicted in an upper left section inFIG.53, it becomes necessary to keep a distance to a lens281, and accordingly this becomes a hindrance to a reduction of the height of the solid-state image pickup apparatus111.

That is, in a case where the wires272are placed around via the through-holes282as depicted in the upper left section inFIG.53, the space required for handling in order to cope with the bending of the wires272increases, and so the distance to the lens281needs to be a distance A.

In contrast to this, in the case of the solid-state image pickup apparatus111manufactured by the manufacturing method of the present disclosure, the space required for handling of the wires272can be made small as depicted in an upper right section inFIG.53, and so the distance between the solid-state image pickup element120and the lens281can be made a distance B shorter than the distance A.

As a result, it becomes possible to realize a reduction of the height of the solid-state image pickup apparatus111.

In addition, in a case where the solid-state image pickup element120is arranged directly on the support board261as depicted in a lower left section inFIG.53, there is a fear that a ghost or a flare occurs due to incident light reflected off the wires272as represented by dotted arrows.

In contrast to this, in the case of the solid-state image pickup apparatus111manufactured by the manufacturing method of the present disclosure, as depicted in a lower right section inFIG.53, incident light reflected off the wires272enters a side-surface section of the solid-state image pickup element120, and side-surface sections of the memory circuit121and logic circuit122, and so it becomes possible to suppress the occurrence of a ghost and a flare.

12. Application Example of Ninth Embodiment

First Application Example of Ninth Embodiment

In the example explained above, the through-electrodes251and252are formed from the memory circuit121and the logic circuit122, respectively, and signals from the solid-state image pickup element120are output to the outside via the wires272connected to the bonding sections271via the memory circuit121and the logic circuit122, and the wires261aand the terminals261bof the support board261.

However, for example, as depicted in a side cross-sectional view54A inFIG.54, through-electrodes291that penetrate the oxide film133without penetrating the memory circuit121and the logic circuit122, and connect the pads120bof the solid-state image pickup element120, and the wires261aof the support board261may be formed.

In this case, the solid-state image pickup element120, and the wires261aof the support board261are connected directly via the through-electrodes291. It should be noted however that, in this case, the memory circuit121and the logic circuit122become not electrically connected with the support board261, but output to the outside is possible via wires in the solid-state image pickup element120, and the through-electrodes291.

Second Application Example of Ninth Embodiment

While in the examples explained above, either the through-electrodes251and252or the through-electrodes291are provided, all of them may be provided in one possible configuration.

That is, as depicted in a side cross-sectional view54B inFIG.54, the through-electrodes291that connect the pads120bof the solid-state image pickup element120, and the wires261aof the support board261, the through-electrodes251that connect the wires121aof the memory circuit121, and the wires261a, and the through-electrodes251that connect the wires122aof the logic circuit122, and the wires261amay be provided.

In this case, the solid-state image pickup element120, the memory circuit121, and the logic circuit122are individually independently electrically connected with the support board261, and so it becomes unnecessary to provide communication wires and the like.

Third Application Example of Ninth Embodiment

While in the examples explained above, at least any one of the through-electrodes251and252, and the through-electrodes291are provided, output to the outside may not be performed via the support board261via the through-electrodes251,252, and271, and terminals may be provided in the electrically connected state in a wiring layer in the memory circuit121and the logic circuit122on which the pads121band122bare provided.

That is, in the solid-state image pickup apparatus111in a side cross-sectional view54C inFIG.54, terminals261b′ in the electrically connected state are provided in the wiring layer in the memory circuit121and the logic circuit122on which the pads121band122bare provided.

By adopting such a configuration, it becomes possible to form the terminals261b′ and the bonding sections271at positions in a latter stage in terms of the direction of incidence than the incidence surface of the solid-state image pickup element120, and it becomes possible to suppress the space required for handling by the wires272, without providing through-electrodes. Thereby, as explained with reference to the upper half ofFIG.53, it becomes possible to make the distance to a lens short, and to realize a reduction of the height, without providing through-electrodes in the solid-state image pickup apparatus111.

13. Tenth Embodiment

While in the example explained above, wires are led out from bonding sections at the top surfaces of end sections of the support board, and signals are output to the outside therethrough, it may be made possible to output signals of the solid-state image pickup element120directly from the backside of the support board.

FIG.55depicts a configuration example of the solid-state image pickup apparatus111that can output signals directly from through-electrodes301connected to the solid-state image pickup element120from the backside of the support board132, without going through the memory circuit121and the logic circuit122.

With a configuration like the solid-state image pickup apparatus111inFIG.55, it becomes possible to enhance the theoretical yield to thereby reduce the cost, and additionally to lead out signals from the solid-state image pickup element120from the backside of the support board132.

Thereby, it becomes possible to configure signal processing circuits and the like by stacking them on the backside of the solid-state image pickup apparatus111.

<Method of Manufacturing Solid-State Image Pickup Apparatus inFIG.55>

Next, a method of manufacturing the solid-state image pickup apparatus111inFIG.55is explained with reference toFIG.56andFIG.57. Note that a side cross-sectional view56A inFIG.56depicts a state where the solid-state image pickup apparatus111inFIG.12has been manufactured. An explanation is given regarding the solid-state image pickup apparatus111inFIG.55assuming that it is generated by processing the solid-state image pickup apparatus111inFIG.12.

In a first process, as depicted in a side cross-sectional view56B inFIG.56, the configuration in the side cross-sectional view56A inFIG.56is vertically reversed, and is placed on a backing board311via an interference section312which includes a resin that can protect the color filters and on-chip lenses pixels131on the solid-state image pickup element120, and is resistant to heat that is equal to or higher than 250° C., or the like.

In a second process, as depicted in a side cross-sectional view56C inFIG.56, the support board132is made thin.

In a third process, as depicted in a side cross-sectional view57A inFIG.57, the through-electrodes301are formed such that they penetrate the oxide film133from above the support board132, and reach the wires120aof the solid-state image pickup element120.

In a fourth process, as depicted in a side cross-sectional view57B inFIG.57, the surface of the solid-state image pickup element120including the color filters and on-chip lenses pixels131is peeled off from the interference section312, and the configuration is reversed vertically as depicted in a side cross-sectional view57C to thereby complete the solid-state image pickup apparatus111inFIG.55.

By a manufacturing method like the one above, it becomes possible to manufacture the solid-state image pickup apparatus111that can directly lead out signals of the solid-state image pickup element120from the backside of the support board132of the solid-state image pickup apparatus111.

14. First Application Example of Tenth Embodiment

While in the example explained above, it is made possible to output signals of the solid-state image pickup element120directly from the backside of the support board by forming the through-electrodes301, dug sections of the through-electrodes undesirably become thicker as the through-electrodes reach deeper positions, due to tapering. In view of this, it may be made possible to make the thicknesses of the through-electrodes thin by forming through-holes that are each formed separately in layers, and eventually stacking the through-holes to form the through-electrodes, not by forming the through-electrodes at once.

Here, in a method of manufacturing the solid-state image pickup apparatus111explained with reference toFIG.58toFIG.60, through-electrodes are each formed separately in layers, and stacked.

Note that an explanation is given here on the premise that a memory circuit121and a logic circuit122extracted as good circuits have been placed on the re-arrangement board151.

In a first process, through-electrodes371with predetermined depths are formed in advance on the support board132at positions corresponding to the through-electrodes301inFIG.55. Then, as depicted in a side cross-sectional view58A inFIG.58, in a state in which the support board132is vertically reversed, the support board132is fixed onto the memory circuit121and the logic circuit122placed on the re-arrangement board151.

In a second process, as depicted in a side cross-sectional view58B inFIG.58, after the state of the side cross-sectional view58A inFIG.58is vertically reversed, the re-arrangement board151is removed.

In a third process, as depicted in a side cross-sectional view58C inFIG.58, the memory circuit121and the logic circuit122are embedded in the oxide film133, and flattened.

In a fourth process, as depicted in a side cross-sectional view59A inFIG.59, after the communication wire T, and the pads121band122bare formed, through-electrodes381are formed in the oxide film133at positions corresponding to the through-electrodes301inFIG.55. That is, the through-electrodes381become electrically connected with the through-electrodes371.

In a fifth process, after through-electrodes391are formed at positions corresponding to the through-electrodes301inFIG.55of the solid-state image pickup element120, as depicted in a side cross-sectional view59B inFIG.59, the state is vertically reversed, and the through-electrodes391are joined onto the memory circuit121and the logic circuit122. That is, the through-electrodes391become electrically connected with the through-electrodes381. That is, by the processes up to this point, the through-electrodes371,381, and391are configured as integrated through-electrodes.

In a sixth process, as depicted in a side cross-sectional view59C inFIG.59, the solid-state image pickup element120is made thin, and thereafter the color filters and on-chip lenses pixels131are formed on the image pickup surface.

In a seventh process, as depicted in a side cross-sectional view60A inFIG.60, the configuration in the side cross-sectional view59C inFIG.59in the vertically reversed state is placed on the backing board311via the interference section312which includes a resin that can protect the color filters and on-chip lenses pixels131on the solid-state image pickup element120, and is resistant to heat that is equal to or higher than 250° C., or the like.

In an eighth process, as depicted in a side cross-sectional view60B inFIG.60, the support board132is made thin, and top sections of the through-electrodes371are exposed.

In a ninth process, as depicted in a side cross-sectional view60C inFIG.60, the interference section312is peeled off from the surface of the solid-state image pickup element120including the color filters and on-chip pixels131, and the configuration is reversed vertically to thereby complete the solid-state image pickup apparatus111inFIG.55.

By a manufacturing method like the one above, when through-electrodes to directly lead out signals of the solid-state image pickup element120to the backside of the support board132are formed, it becomes possible, by forming the through-electrodes371,381, and391in the individual layers, to form through-electrodes thinner than through-electrode formed at once.

15. Second Application Example of Tenth Embodiment

While in the example explained above, through-electrodes are formed, and through-electrodes that directly lead out signals of the solid-state image pickup element120from the backside of the support board132to be the backside of the solid-state image pickup apparatus111are formed, it may be made possible to lead out signals directly from the backside of the support board132by forming through-electrodes through each of the memory circuit121and the logic circuit122.

That is, as depicted inFIG.61, through-electrodes401and402may be formed from the backside of the support board132such that they are connected to the wires121aand122aof the memory circuit121and the logic circuit122, respectively, included in the solid-state image pickup apparatus111.

Note that the method of manufacturing the solid-state image pickup apparatus111inFIG.61is similar to that in a case where the through-electrodes301or the through-electrodes371,381, and391are formed in the method of manufacturing the solid-state image pickup apparatus111inFIG.55, and so an explanation thereof is omitted.

16. Examples of Application to Electronic Equipment

For example, the image pickup element mentioned above can be applied to various types of electronic equipment like image pickup apparatuses such as a digital still camera or a digital video camera, mobile phones having the image pickup function, or other equipment having the image pickup function.

FIG.62is a block diagram depicting a configuration example of an image pickup apparatus as electronic equipment to which the present technology is applied.

An image pickup apparatus501depicted inFIG.62includes an optical system502, a shutter apparatus503, a solid-state image pickup element504, a drive circuit505, a signal processing circuit506, a monitor507, and a memory508, and can capture still image images and moving images.

The optical system502includes one lens or plural lenses, guides light from a subject (incident light) to the solid-state image pickup element504, and causes an image to be formed on the light-receiving surface of the solid-state image pickup element504.

The shutter apparatus503is arranged between the optical system502and the solid-state image pickup element504, and, under the control of the drive circuit505, controls the light emission period and light blocking period of light into the solid-state image pickup element504.

The solid-state image pickup element504includes a package including the solid-state image pickup element mentioned above. The solid-state image pickup element504accumulates a signal charge for a predetermined period according to light to form an image on the light-receiving surface after going through the optical system502and the shutter apparatus503. The signal charge accumulated in the solid-state image pickup element504is transferred according to a drive signal (timing signal) supplied from the drive circuit505.

The drive circuit505outputs drive signals to control the transfer operation of the solid-state image pickup element504, and the shutter operation of the shutter apparatus503, and drives the solid-state image pickup element504and the shutter apparatus503.

The signal processing circuit506performs various types of signal processing on a signal charge output from the solid-state image pickup element504. An image (image data) obtained by the signal processing performed by the signal processing circuit506is supplied to and displayed on the monitor507, or is supplied to and stored (recorded) on the memory508, for example.

In the thus-configured image pickup apparatus501also, by applying the solid-state image pickup apparatus111mentioned above to the optical system502and the solid-state image pickup element204, it becomes possible to enhance the yield, and reduce the cost related to manufacturing.

17. Use Examples of Solid-State Image Pickup Apparatus

FIG.63is a figure depicting use examples in which the solid-state image pickup apparatus111mentioned above is used.

The solid-state image pickup apparatus mentioned above can be used in various cases in which light such as visible light, infrared light, ultraviolet light, or X-ray is sensed, like the following ones, for example.Apparatuses such as digital cameras or mobile equipment having the camera function that capture images provided for appreciationApparatuses provided for transportation such as vehicle-mounted sensors that capture images of spaces in front of, behind, around, inside and the like of an automobile, monitor cameras that monitor travelling vehicles and roads, or distance measurement sensors that perform measurement of the distances between vehicles and the like, for safe driving by automatic stop and the like, recognition of the state of a driver, and the likeApparatuses provided for home electric appliances such as TVs, refrigerators, or air conditioners for capturing images of gestures of a user, and performing equipment operation according to the gesturesApparatuses provided for medical care or healthcare such as endoscopes or apparatuses for capturing images of blood vessels by receiving infrared lightApparatuses provided for security such as monitor cameras for crime prevention uses, or cameras for human authentication usesApparatuses provided for cosmetic purposes such as skin measurement devices that capture images of skin, or microscopes that capture images of scalpsApparatus provided for sports such as action cameras for sports uses and the like, or wearable camerasApparatuses provided for agriculture such as cameras for monitoring the states of fields and crops

18. Examples of Application to Endoscopic Surgery System

The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to endoscopic surgery systems.

FIG.64is a view depicting an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (present technology) can be applied.

InFIG.64, a state is illustrated in which a surgeon (medical doctor)11131is using an endoscopic surgery system11000to perform surgery for a patient11132on a patient bed11133. As depicted, the endoscopic surgery system11000includes an endoscope11100, other surgical tools11110such as a pneumoperitoneum tube11111and an energy device11112, a supporting arm apparatus11120which supports the endoscope11100thereon, and a cart11200on which various apparatus for endoscopic surgery are mounted.

The endoscope11100includes a lens barrel11101having a region of a predetermined length from a distal end thereof to be inserted into a body cavity of the patient11132, and a camera head11102connected to a proximal end of the lens barrel11101. In the example depicted, the endoscope11100is depicted which includes as a rigid endoscope having the lens barrel11101of the hard type. However, the endoscope11100may otherwise be included as a flexible endoscope having the lens barrel11101of the flexible type.

The lens barrel11101has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus11203is connected to the endoscope11100such that light generated by the light source apparatus11203is introduced to a distal end of the lens barrel11101by a light guide extending in the inside of the lens barrel11101and is irradiated toward an observation target in a body cavity of the patient11132through the objective lens. It is to be noted that the endoscope11100may be a forward-viewing endoscope or may be an oblique-viewing endoscope or a side-viewing endoscope.

An optical system and an image pickup element are provided in the inside of the camera head11102such that reflected light (observation light) from the observation target is condensed on the image pickup element by the optical system. The observation light is photo-electrically converted by the image pickup element to generate an electric signal corresponding to the observation light, namely, an image signal corresponding to an observation image. The image signal is transmitted as RAW data to a CCU11201.

The CCU11201includes a central processing unit (CPU), a graphics processing unit (GPU) or the like and integrally controls operation of the endoscope11100and a display apparatus11202. Further, the CCU11201receives an image signal from the camera head11102and performs, for the image signal, various image processes for displaying an image based on the image signal such as, for example, a development process (demosaic process).

The display apparatus11202displays thereon an image based on an image signal, for which the image processes have been performed by the CCU11201, under the control of the CCU11201.

The light source apparatus11203includes a light source such as, for example, a light emitting diode (LED) and supplies irradiation light upon imaging of a surgical region to the endoscope11100.

An inputting apparatus11204is an input interface for the endoscopic surgery system11000. A user can perform inputting of various kinds of information or instruction inputting to the endoscopic surgery system11000through the inputting apparatus11204. For example, the user would input an instruction or a like to change an image pickup condition (type of irradiation light, magnification, focal distance or the like) by the endoscope11100.

A treatment tool controlling apparatus11205controls driving of the energy device11112for cautery or incision of a tissue, sealing of a blood vessel or the like. A pneumoperitoneum apparatus11206feeds gas into a body cavity of the patient11132through the pneumoperitoneum tube11111to inflate the body cavity in order to secure the field of view of the endoscope11100and secure the working space for the surgeon. A recorder11207is an apparatus capable of recording various kinds of information relating to surgery. A printer11208is an apparatus capable of printing various kinds of information relating to surgery in various forms such as a text, an image or a graph.

It is to be noted that the light source apparatus11203which supplies irradiation light when a surgical region is to be imaged to the endoscope11100may include a white light source which includes, for example, an LED, a laser light source or a combination of them. Where a white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and the output timing can be controlled with a high degree of accuracy for each color (each wavelength), adjustment of the white balance of a picked up image can be performed by the light source apparatus11203. Further, in this case, if laser beams from the respective RGB laser light sources are irradiated time-divisionally on an observation target and driving of the image pickup elements of the camera head11102are controlled in synchronism with the irradiation timings. Then images individually corresponding to the R, G and B colors can be also picked up time-divisionally. According to this method, a color image can be obtained even if color filters are not provided for the image pickup element.

Further, the light source apparatus11203may be controlled such that the intensity of light to be outputted is changed for each predetermined time. By controlling driving of the image pickup element of the camera head11102in synchronism with the timing of the change of the intensity of light to acquire images time-divisionally and synthesizing the images, an image of a high dynamic range free from underexposed blocked up shadows and overexposed highlights can be created.

Further, the light source apparatus11203may be configured to supply light of a predetermined wavelength band ready for special light observation. In special light observation, for example, by utilizing the wavelength dependency of absorption of light in a body tissue to irradiate light of a narrow band in comparison with irradiation light upon ordinary observation (namely, white light), narrow band observation (narrow band imaging) of imaging a predetermined tissue such as a blood vessel of a superficial portion of the mucous membrane or the like in a high contrast is performed. Alternatively, in special light observation, fluorescent observation for obtaining an image from fluorescent light generated by irradiation of excitation light may be performed. In fluorescent observation, it is possible to perform observation of fluorescent light from a body tissue by irradiating excitation light on the body tissue (autofluorescence observation) or to obtain a fluorescent light image by locally injecting a reagent such as indocyanine green (ICG) into a body tissue and irradiating excitation light corresponding to a fluorescent light wavelength of the reagent upon the body tissue. The light source apparatus11203can be configured to supply such narrow-band light and/or excitation light suitable for special light observation as described above.

FIG.65is a block diagram depicting an example of a functional configuration of the camera head11102and the CCU11201depicted inFIG.64.

The camera head11102includes a lens unit11401, an image pickup unit11402, a driving unit11403, a communication unit11404and a camera head controlling unit11405. The CCU11201includes a communication unit11411, an image processing unit11412and a control unit11413. The camera head11102and the CCU11201are connected for communication to each other by a transmission cable11400.

The lens unit11401is an optical system, provided at a connecting location to the lens barrel11101. Observation light taken in from a distal end of the lens barrel11101is guided to the camera head11102and introduced into the lens unit11401. The lens unit11401includes a combination of a plurality of lenses including a zoom lens and a focusing lens.

The number of image pickup elements which is included by the image pickup unit11402may be one (single-plate type) or a plural number (multi-plate type). Where the image pickup unit11402is configured as that of the multi-plate type, for example, image signals corresponding to respective R, G and B are generated by the image pickup elements, and the image signals may be synthesized to obtain a color image. The image pickup unit11402may also be configured so as to have a pair of image pickup elements for acquiring respective image signals for the right eye and the left eye ready for three dimensional (3D) display. If 3D display is performed, then the depth of a living body tissue in a surgical region can be comprehended more accurately by the surgeon11131. It is to be noted that, where the image pickup unit11402is configured as that of stereoscopic type, a plurality of systems of lens units11401are provided corresponding to the individual image pickup elements.

Further, the image pickup unit11402may not necessarily be provided on the camera head11102. For example, the image pickup unit11402may be provided immediately behind the objective lens in the inside of the lens barrel11101.

The driving unit11403includes an actuator and moves the zoom lens and the focusing lens of the lens unit11401by a predetermined distance along an optical axis under the control of the camera head controlling unit11405. Consequently, the magnification and the focal point of a picked up image by the image pickup unit11402can be adjusted suitably.

The communication unit11404includes a communication apparatus for transmitting and receiving various kinds of information to and from the CCU11201. The communication unit11404transmits an image signal acquired from the image pickup unit11402as RAW data to the CCU11201through the transmission cable11400.

In addition, the communication unit11404receives a control signal for controlling driving of the camera head11102from the CCU11201and supplies the control signal to the camera head controlling unit11405. The control signal includes information relating to image pickup conditions such as, for example, information that a frame rate of a picked up image is designated, information that an exposure value upon image picking up is designated and/or information that a magnification and a focal point of a picked up image are designated.

It is to be noted that the image pickup conditions such as the frame rate, exposure value, magnification or focal point may be designated by the user or may be set automatically by the control unit11413of the CCU11201on the basis of an acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function and an auto white balance (AWB) function are incorporated in the endoscope11100.

The camera head controlling unit11405controls driving of the camera head11102on the basis of a control signal from the CCU11201received through the communication unit11404.

The communication unit11411includes a communication apparatus for transmitting and receiving various kinds of information to and from the camera head11102. The communication unit11411receives an image signal transmitted thereto from the camera head11102through the transmission cable11400.

Further, the communication unit11411transmits a control signal for controlling driving of the camera head11102to the camera head11102. The image signal and the control signal can be transmitted by electrical communication, optical communication or the like.

The image processing unit11412performs various image processes for an image signal in the form of RAW data transmitted thereto from the camera head11102.

The control unit11413performs various kinds of control relating to image picking up of a surgical region or the like by the endoscope11100and display of a picked up image obtained by image picking up of the surgical region or the like. For example, the control unit11413creates a control signal for controlling driving of the camera head11102.

Further, the control unit11413controls, on the basis of an image signal for which image processes have been performed by the image processing unit11412, the display apparatus11202to display a picked up image in which the surgical region or the like is imaged. Thereupon, the control unit11413may recognize various objects in the picked up image using various image recognition technologies. For example, the control unit11413can recognize a surgical tool such as forceps, a particular living body region, bleeding, mist when the energy device11112is used and so forth by detecting the shape, color and so forth of edges of objects included in a picked up image. The control unit11413may cause, when it controls the display apparatus11202to display a picked up image, various kinds of surgery supporting information to be displayed in an overlapping manner with an image of the surgical region using a result of the recognition. Where surgery supporting information is displayed in an overlapping manner and presented to the surgeon11131, the burden on the surgeon11131can be reduced and the surgeon11131can proceed with the surgery with certainty.

The transmission cable11400which connects the camera head11102and the CCU11201to each other is an electric signal cable ready for communication of an electric signal, an optical fiber ready for optical communication or a composite cable ready for both of electrical and optical communications.

Here, while, in the example depicted, communication is performed by wired communication using the transmission cable11400, the communication between the camera head11102and the CCU11201may be performed by wireless communication.

One example of the endoscopic surgery system to which the technology according to the present disclosure can be applied is explained above. The technology according to the present disclosure can be applied to the endoscope11100, (the image pickup unit11402of) the camera head11102and the like in the configurations explained above. Specifically, the solid-state image pickup apparatus111of the present disclosure can be applied to the image pickup unit10402. By applying the technology according to the present disclosure to the endoscope11100, (the image pickup unit11402of) the camera head11102and the like, it becomes possible to enhance the yield, and reduce the cost related to manufacturing.

Note that, while the endoscopic surgery system is explained as one example here, the technology according to the present disclosure may be applied to others, for example, microscopic surgery systems and the like.

19. Examples of Application to Mobile Body

The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as an apparatus to be mounted on any type of mobile body such as an automobile, an electric automobile, a hybrid electric automobile, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, or a robot.

FIG.66is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

The vehicle control system12000includes a plurality of electronic control units connected to each other via a communication network12001. In the example depicted inFIG.66, the vehicle control system12000includes a driving system control unit12010, a body system control unit12020, an outside-vehicle information detecting unit12030, an in-vehicle information detecting unit12040, and an integrated control unit12050. In addition, a microcomputer12051, a sound/image output section12052, and a vehicle-mounted network interface (I/F)12053are illustrated as a functional configuration of the integrated control unit12050.

The driving system control unit12010controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit12010functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

The body system control unit12020controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit12020functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit12020. The body system control unit12020receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

The outside-vehicle information detecting unit12030detects information about the outside of the vehicle including the vehicle control system12000. For example, the outside-vehicle information detecting unit12030is connected with an imaging section12031. The outside-vehicle information detecting unit12030makes the imaging section12031image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit12030may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

The imaging section12031is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section12031can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section12031may be visible light, or may be invisible light such as infrared rays or the like.

The in-vehicle information detecting unit12040detects information about the inside of the vehicle. The in-vehicle information detecting unit12040is, for example, connected with a driver state detecting section12041that detects the state of a driver. The driver state detecting section12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section12041, the in-vehicle information detecting unit12040may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

The microcomputer12051can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040, and output a control command to the driving system control unit12010. For example, the microcomputer12051can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

In addition, the microcomputer12051can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030or the in-vehicle information detecting unit12040.

In addition, the microcomputer12051can output a control command to the body system control unit12020on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit12030. For example, the microcomputer12051can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit12030.

The sound/image output section12052transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example ofFIG.66, an audio speaker12061, a display section12062, and an instrument panel12063are illustrated as the output device. The display section12062may, for example, include at least one of an on-board display and a head-up display.

FIG.67is a diagram depicting an example of the installation position of the imaging section12031.

InFIG.67, the imaging section12031includes imaging sections12101,12102,12103,12104, and12105.

The imaging sections12101,12102,12103,12104, and12105are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle12100as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section12101provided to the front nose and the imaging section12105provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle12100. The imaging sections12102and12103provided to the sideview mirrors obtain mainly an image of the sides of the vehicle12100. The imaging section12104provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle12100. The imaging section12105provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

Incidentally,FIG.67depicts an example of photographing ranges of the imaging sections12101to12104. An imaging range12111represents the imaging range of the imaging section12101provided to the front nose. Imaging ranges12112and12113respectively represent the imaging ranges of the imaging sections12102and12103provided to the sideview mirrors. An imaging range12114represents the imaging range of the imaging section12104provided to the rear bumper or the back door. A bird's-eye image of the vehicle12100as viewed from above is obtained by superimposing image data imaged by the imaging sections12101to12104, for example.

At least one of the imaging sections12101to12104may have a function of obtaining distance information. For example, at least one of the imaging sections12101to12104may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, the microcomputer12051can determine a distance to each three-dimensional object within the imaging ranges12111to12114and a temporal change in the distance (relative speed with respect to the vehicle12100) on the basis of the distance information obtained from the imaging sections12101to12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle12100and which travels in substantially the same direction as the vehicle12100at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer12051can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

For example, the microcomputer12051can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections12101to12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer12051identifies obstacles around the vehicle12100as obstacles that the driver of the vehicle12100can recognize visually and obstacles that are difficult for the driver of the vehicle12100to recognize visually. Then, the microcomputer12051determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer12051outputs a warning to the driver via the audio speaker12061or the display section12062, and performs forced deceleration or avoidance steering via the driving system control unit12010. The microcomputer12051can thereby assist in driving to avoid collision.

At least one of the imaging sections12101to12104may be an infrared camera that detects infrared rays. The microcomputer12051can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections12101to12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections12101to12104as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer12051determines that there is a pedestrian in the imaged images of the imaging sections12101to12104, and thus recognizes the pedestrian, the sound/image output section12052controls the display section12062so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section12052may also control the display section12062so that an icon or the like representing the pedestrian is displayed at a desired position.

One example of the vehicle control system to which the technology according to the present disclosure can be applied is explained above. The technology according to the present disclosure can be applied, for example, to the imaging section12031and the like in the configuration explained above. Specifically, the solid-state image pickup apparatus111of the present disclosure can be applied to the imaging section12031. By applying the technology according to the present disclosure to the imaging section12031, it becomes possible to enhance the yield, and reduce the cost related to manufacturing.

The technology according to the present disclosure can be applied to a solid-state image pickup apparatus like the one above.

Note that the present disclosure can have configurations like the ones below.

<1>

A backside-illumination solid-state image pickup apparatus including:

a first semiconductor element having an image pickup element that generates a pixel signal of each pixel;

a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, the second semiconductor element and the third semiconductor element having signal processing circuits that are embedded therein by using embedment members and that are necessary for signal processing of the pixel signal; and

a communication wire that electrically connects the second semiconductor element and the third semiconductor element.

<2>

The backside-illumination solid-state image pickup apparatus according to <1>, in which

the communication wire is formed in a single layer.

<3>

The backside-illumination solid-state image pickup apparatus according to <1> or <2>, in which

the second semiconductor element and the third semiconductor element are stacked on a backside of the first semiconductor element in terms of a direction of incidence of incident light, and

the communication wire is formed on a side of the first semiconductor element relative to a boundary between the first semiconductor element, and the second semiconductor element and the third semiconductor element.

<4>

The backside-illumination solid-state image pickup apparatus according to <1> or <2>, in which

the second semiconductor element and the third semiconductor element are stacked on a backside of the first semiconductor element in terms of a direction of incidence of incident light, and

the communication wire is formed on a side of the second semiconductor element and the third semiconductor element relative to a boundary between the first semiconductor element, and the second semiconductor element and the third semiconductor element.

<5>

The backside-illumination solid-state image pickup apparatus according to <4>, in which

the communication wire is formed on surfaces of the second semiconductor element and the third semiconductor element that face the direction of incidence of the incident light.

<6>

The backside-illumination solid-state image pickup apparatus according to <5>, in which

surfaces of the second semiconductor element and the third semiconductor element on which a wire is formed are formed on surfaces that face the direction of incidence of the incident light.

<7>

The backside-illumination solid-state image pickup apparatus according to <5>, in which

surfaces of the second semiconductor element and the third semiconductor element on which a wire is formed are formed on backsides in terms of the direction of incidence of the incident light.

<8>

The backside-illumination solid-state image pickup apparatus according to <7>, in which

the surfaces of the second semiconductor element and the third semiconductor element on which the wire is formed are formed on the backsides in terms of the direction of incidence of the incident light, and the communication wire is formed via a through-electrode formed through each board.

<9>

The backside-illumination solid-state image pickup apparatus according to <5>, in which

a support board is connected on a side of backsides of the second semiconductor element and the third semiconductor element in terms of the incident light, and

the communication wire is formed in the support board.

<10>

The backside-illumination solid-state image pickup apparatus according to <4>, in which

the communication wire is formed on backsides of the second semiconductor element and the third semiconductor element in terms of the direction of incidence of the incident light.

<11>

The backside-illumination solid-state image pickup apparatus according to <10>, in which

the communication wire is formed on a front side of a support board on a side of the backsides of the second semiconductor element and the third semiconductor element in terms of the direction of incidence of the incident light.

<12>

The backside-illumination solid-state image pickup apparatus according to <4>, in which

the second semiconductor element and the third semiconductor element are electrically connected with the first semiconductor element by a through-electrode that penetrates the first semiconductor element.

<13>

The backside-illumination solid-state image pickup apparatus according to <4>, in which

the first semiconductor element, the second semiconductor element, and the third semiconductor element are stacked in an order of the first semiconductor element, the second semiconductor element, and the third semiconductor element when seen in the direction of incidence of the incident light, and pads that are formed on junction surfaces of the second semiconductor element and the third semiconductor element such that the pads face each other are electrically connected to function as the communication wire.

<14>

The backside-illumination solid-state image pickup apparatus according to <1>, in which

the first semiconductor element, the second semiconductor element, and the third semiconductor element are stacked in an order of the first semiconductor element, the second semiconductor element, and the third semiconductor element when seen in a direction of incidence of incident light, and the first semiconductor element and the third semiconductor element are electrically connected by a through-electrode formed penetrating the second semiconductor element.

<15>

The backside-illumination solid-state image pickup apparatus according to <4>, in which

a support board is connected on a side of backsides of the second semiconductor element and the third semiconductor element in terms of the incident light, and

a wire of at least any one of the first semiconductor element, the second semiconductor element, and the third semiconductor element is connected by a through-electrode and is led out to a side of a backside of the support board in terms of the direction of incidence of the incident light.

<16>

The backside-illumination solid-state image pickup apparatus according to <4>, in which

the communication wire is placed in a vertical range occupied by the first semiconductor element in terms of the incident light.

<17>

The backside-illumination solid-state image pickup apparatus according to <3>, in which

a support board is connected on a side of backsides of the second semiconductor element and the third semiconductor element in terms of the incident light, and

a wire is formed in the support board, the wire of the support board and the wire of at least any one of the first semiconductor element, the second semiconductor element, and the third semiconductor element are connected by a through-electrode, and a terminal to lead out a signal line is formed on the support board at a portion outside an area where the second semiconductor element and the third semiconductor element are formed.

<18>

An image pickup apparatus including:a backside-illumination solid-state image pickup apparatus includinga first semiconductor element having an image pickup element that generates a pixel signal of each pixel,a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, the second semiconductor element and the third semiconductor element having signal processing circuits that are embedded therein by using embedment members and that are necessary for signal processing of the pixel signal, anda communication wire that electrically connects the second semiconductor element and the third semiconductor element.
<19>

Electronic equipment including:a backside-illumination solid-state image pickup apparatus includinga first semiconductor element having an image pickup element that generates a pixel signal of each pixel,a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, the second semiconductor element and the third semiconductor element having signal processing circuits that are embedded therein by using embedment members and that are necessary for signal processing of the pixel signal, anda communication wire that electrically connects the second semiconductor element and the third semiconductor element.
<20>

A method of manufacturing a backside-illumination solid-state image pickup apparatus, the backside-illumination solid-state image pickup apparatus includinga first semiconductor element having an image pickup element that generates a pixel signal of each pixel,a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, the second semiconductor element and the third semiconductor element having signal processing circuits that are embedded therein by using embedment members and that are necessary for signal processing of the pixel signal, anda communication wire that electrically connects the second semiconductor element and the third semiconductor element, in whichthe second semiconductor element and the third semiconductor element with the signal processing circuits that are included in the second semiconductor element and the third semiconductor element formed by a semiconductor process, the second semiconductor element and the third semiconductor element being determined as good elements by an electrical inspection, are re-arranged on a wafer having the image pickup element formed by a semiconductor process and embedded by using the embedment members,a communication wire that electrically connects the second semiconductor element and the third semiconductor element is formed, andthe first semiconductor element, the second semiconductor element, and the third semiconductor element are stacked by oxide-film joining such that wires are electrically connected between the first semiconductor element, and the second semiconductor element and the third semiconductor element, and then are diced.
<21>

A backside-illumination solid-state image pickup apparatus including:a first semiconductor element layer having an image pickup element that generates a pixel signal of each pixel;a second semiconductor element layer having a second semiconductor element and a third semiconductor element that are smaller than the first semiconductor element, the second semiconductor element and the third semiconductor element having signal processing circuits that are embedded therein by using embedment members and that are necessary for signal processing of the pixel signal; anda support board, in whichthe second semiconductor element layer is provided between the first semiconductor element layer and the support board, andthe first semiconductor element layer and the second semiconductor element layer are joined by direct joining.
<22>

The backside-illumination solid-state image pickup apparatus according to <21>, in whicha communication wire that electrically connects the second semiconductor element and the third semiconductor element is provided in the second semiconductor element layer or the support board.
<23>

The backside-illumination solid-state image pickup apparatus according to <22>, in whichthe communication wire is provided on a side of the second semiconductor element layer which is closer to the first semiconductor element layer.
<24>

The backside-illumination solid-state image pickup apparatus according to <22>, in whichthe communication wire is provided on a side of the second semiconductor element layer which is closer to the support board.
<25>

The backside-illumination solid-state image pickup apparatus according to <22> or <23>, in whichthe support board further has a wiring layer on a side closer to the second semiconductor element layer, andthe communication wire is provided in the wiring layer of the support board.
<26>

The backside-illumination solid-state image pickup apparatus according to <22>, in whichthe second semiconductor element and the third semiconductor element are stacked on a backside of the first semiconductor element in terms of a direction of incidence of incident light, andthe communication wire is formed on a side of the second semiconductor element and the third semiconductor element relative to a boundary between the first semiconductor element, and the second semiconductor element and the third semiconductor element.
<27>

The backside-illumination solid-state image pickup apparatus according to <26>, in whichthe communication wire is formed on surfaces of the second semiconductor element and the third semiconductor element that face the direction of incidence of the incident light.
<28>

The backside-illumination solid-state image pickup apparatus according to <27>, in whichsurfaces of the second semiconductor element and the third semiconductor element on which a wire is formed are formed on surfaces that face the direction of incidence of the incident light.
<29>

The backside-illumination solid-state image pickup apparatus according to <27>, in whichsurfaces of the second semiconductor element and the third semiconductor element on which a wire is formed are formed on backsides in terms of the direction of incidence of the incident light.
<30>

The backside-illumination solid-state image pickup apparatus according to <29>, in whichthe surfaces of the second semiconductor element and the third semiconductor element on which the wire is formed are formed on the backsides in terms of the direction of incidence of the incident light, and the communication wire is formed via a through-electrode formed through each board.
<31>

The backside-illumination solid-state image pickup apparatus according to <27>, in whicha support board is connected on a side of backsides of the second semiconductor element and the third semiconductor element in terms of the incident light, andthe communication wire is formed in the support board.
<32>The backside-illumination solid-state image pickup apparatus according to <26>, in whichthe communication wire is formed on backsides of the second semiconductor element and the third semiconductor element in terms of the direction of incidence of the incident light.
<33>

The backside-illumination solid-state image pickup apparatus according to <32>, in whichthe communication wire is formed on a front side of a support board on a side of the backsides of the second semiconductor element and the third semiconductor element in terms of the direction of incidence of the incident light.

REFERENCE SIGNS LIST

101to104: Wafer111: Solid-state image pickup apparatus120: Solid-state image pickup element120a: Wire120b: Pad121: Memory circuit121a,121a-1to121a-4,121a-11to121a-14: Wire121b,121b-1to121b-4,121b-11to121b-14,121b′: Pad121c,121c-1to121c-4,121c-11to121c-14: Wire122: Logic circuit122a,122a-1to122a-4,122a-11to122a-14: Wire122b,122b-1to122b-4,122b-11to122b-14,122b′: Pad122d: Through-electrode131: Pixel (e.g., On-chip lens and on-chip color filter)132: Support board132a: Wire132b: Pad133: Oxide film134,134-1,134-2,134A to134H: Wire135: Oxide film junction layer151: Re-arrangement board152: Adhesive201: Memory device board201a: Wire201b: Pad201c: Wire201d: Through-electrode231: Through-electrode241: Organic photoelectric conversion film251,252: Through-electrode261: Support board261a: Wire261b: Terminal281: Lens282: Through-hole301: Through-electrode311: Backing board312: Interference section371,381,391: Through-electrodeT, T″, T″, T1to T6: Communication wireTCV1, TCV2: Through-electrode