Patent ID: 12212678

DETAILED DESCRIPTION

Specific structural and functional description is provided herein only to describe embodiments of the invention. However, the invention may be configured and/or carried out in various other ways, as those skilled in the art will understand from the present disclosure. Thus, the invention is not limited to any of disclosed embodiments nor to any specific detail described in this specification. Also, throughout the specification, reference to “an embodiment,” “another embodiment” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). The term “embodiments” when used herein does not necessarily refer to all embodiments.

FIG.1is a diagram illustrating a computing system400according to an embodiment of the present disclosure.

Referring toFIG.1, the computing system400may include a storage device50and a host300.

The storage device50may include a memory device100and a memory controller200controlling operations of the memory device100. The storage device50may store data in response to control of the host300. Examples of the storage device50include a cellular phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game player, a TV, a tablet PC, and an in-vehicle infotainment system.

The storage device50may be configured as any of various types of storage devices depending on a host interface which is a communication method with the host300. For example, the storage device50may be configured as a solid state drive (SSD), a multimedia card in the form of a multimedia card (MMC), an eMMC, an RS-MMC, and a micro-MMC, a secure digital card in the form of an SD, a mini-SD, and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI express (PCI-e or PCIe) card type storage device, a compact flash (CF) card, a smart media card, or a memory stick.

The storage device50may be manufactured as any of various types of packages. For example, the storage device50may be manufactured as a package-on-package (POP), a system-in-package (SIP), a system-on-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabricated package (WFP), or a wafer-level stack package (WSP).

The memory device100may store data. The memory device100may operate in response to control of the memory controller200. The memory device100may include a memory cell array including a plurality of memory cells storing data.

Each of the memory cells may be a Single-Level Cell (SLC) storing one bit of data, a Multi-Level Cell (MLC) storing two bits of data, a Triple-Level Cell (TLC) storing three bits of data, or a Quad-Level Cell (QLC) storing four bits of data.

The memory cell array may include a plurality of memory blocks, each of which may include a plurality of memory cells. Each memory block may include a plurality of pages. According to an embodiment, a page may be a unit for storing data in the memory device100or reading data stored in the memory device100.

The memory block may be a unit for erasing data. According to an embodiment, the memory device100may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin-transfer torque random access memory (STT-RAM). By way of example, it is assumed that the memory device100is NAND flash memory in the context of the following description.

The memory device100may receive a command and an address from the memory controller200, and access an area selected by the address in the memory cell array. That is, the memory device100may perform an operation that the command instructs on the area selected by the address. For example, the memory device100may perform a write operation (or a program operation), a read operation, and an erase operation. During the program operation, the memory device100may program the area selected by the address with data. During the read operation, the memory device100may read data from the area selected by the address. During the erase operation, the memory device100may erase data stored in the area selected by the address.

According to an embodiment, the memory device100may include a write protection area. Write data that has verified integrity may be stored in the write protection area. Integrity may refer to a state in which write data received from the host300is not distorted or modulated.

The memory controller200may control general operation of the storage device50.

When power is applied to the storage device50, the memory controller200may execute firmware (FW). When the memory device100is a flash memory device, the memory controller200may execute firmware such as a flash translation layer (FTL) for controlling communication between the host300and the memory device100.

According to an embodiment, the memory controller200may receive data and a logical block address (LBA) from the host300and translate the LBA into a physical block address (PBA) indicating an address of memory cells in which data is to be stored in the memory device100.

For example, the memory controller200may control the memory device100to perform a program operation, a read operation or an erase operation in response to a request from the host300. During the program operation, the memory controller200may provide the memory device100with a write command, a PBA, and data. During the read operation, the memory controller200may provide the memory device100with a read command and a PBA. During the erase operation, the memory controller200may provide the memory device100with an erase command and a PBA.

According to an embodiment, the memory controller200may generate and transfer a command, an address, and data to the memory device100regardless of a request from the host300. For example, the memory controller200may provide the memory device100with a command, an address, and data to perform background operations, such as a program operation for wear leveling and a program operation for garbage collection.

According to an embodiment, the memory controller200may control at least two memory devices100. The memory controller200may control the memory devices100according to an interleaving scheme so as to improve operation performance. In the interleaving scheme operating periods of two or more memory devices100may at least partially overlap.

According to an embodiment, the memory controller200may generate a device authentication code using the write data received from the host300and a key shared with the host300. The memory controller200may verify integrity of the write data based on a result of comparing the device authentication code with a host authentication code received from the host300. The memory controller200may control the memory device100to store write data that has verified integrity in the write protection area in response to the request from the host300. The memory controller200may provide the host300with a result of a program operation on the write data in response to the request from the host300. The result of the program operation may include information as to whether the write data has integrity and information as to whether the program operation has passed or failed.

The host300may communicate with the storage device50using at least one of various communication methods such as a Universal Serial Bus (USB), Serial AT Attachment (SATA), a Serial Attached SCSI (SAS), a High Speed Interchip (HSIC), a Small Computer System Interface (SCSI), a Peripheral Component Interconnection (PCI), PCI express (PCIe), NonVolatile Memory express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), a MultiMedia Card (MMC), an embedded MMC (eMMC), a Dual In-line Memory Module (DIMM), a Registered DIMM (RDIMM), and/or a Load Reduced DIMM (LRDIMM).

Communication regarding security write between the host300and the storage device50is described later with reference toFIGS.2and3.

FIG.2is a diagram illustrating security write according to an embodiment.

Referring toFIG.2, at step S201, the host300may generate a host authentication code based on a key shared with the storage device50and write data. The host300may generate the host authentication code by using a message authentication code (MAC) algorithm. The host authentication code may be used for verifying integrity of the write data. In other words, the host authentication code may be used for verifying whether the write data is distorted or modulated during the transmission of the write data from the host300to the storage device50.

The host300may provide the storage device50with a series of requests, e.g., first to third requests, for security write.

At step S203, the host300may provide the storage device50with the first request. The first request may be for programming the write data into a write protection area of the storage device50. The host300may provide the storage device50with the first request, the write data, and the host authentication code.

At step S205, the storage device50may provide the host300with a first response indicating whether the first request has been received.

At step S207, the host300may provide the storage device50with the second request in response to the first response. The second request may be for checking whether a result of a program operation on the write data is available, i.e., ready to be collected.

At step S209, the storage device50may provide the host300with a second response indicating whether the second request has been received.

At step S211, the host300may provide the storage device50with the third request in response to the second response. The third request may be for the result of the program operation on the write data.

At step S213, the storage device50may provide the host300with a third response including the result of the program operation on the write data, in response to the third request. The result of the program operation may include information indicating whether the program operation has passed or failed, and also may include information indicating whether the write data has integrity.

At step S215, the storage device50may receive the write data and the host authentication code, together with the first request from the host300.

At step S217, the storage device50may generate a device authentication code based on a key shared with the host300and the received write data. The storage device50may generate the device authentication code by using a message authentication code (MAC) algorithm.

At step S219, the storage device50may verify whether the write data has integrity. According to a result of verification, when it is determined that the write data has integrity, the process flow may proceed to step S221. Alternatively, when it is determined that the write data does not have integrity, the process flow may proceed to step S213.

At step S221, the storage device50may perform a program operation of storing the write data in the write protection area. After the program operation is performed, the storage device50may generate information indicating whether the program operation has passed or failed. After performing step S221, the process flow may proceed to step S213.

FIG.3is a diagram illustrating security write according to an embodiment.

Referring toFIG.3, the host300may provide the storage device50with a series of first to third requests for security write.

At step S301, the host300may provide the storage device50with the first request. The first request may be for programming write data into a write protection area of the storage device50. The host300may provide the storage device50with the first request and the write data.

At step S303, the host300may generate a host authentication code after providing the storage device50with the first request. The host300may generate the host authentication code based on a key shared with the storage device50and the write data. The host300may generate the host authentication code by using a message authentication code (MAC) algorithm. The host300may provide the write data to the storage device50in parallel with the generation of the host authentication code. In other words, the host300may initiate the generation of the host authentication code when the write data is transmitted to the storage device50.

According to various embodiments, the storage device50may generate a device authentication code at step S317when the host300generates the host authentication code at step S303. In other words, the generation of the host authentication code may be performed in parallel with the generation of the device authentication code.

At step S305, the storage device50may provide the host300with a first response indicating whether the first request has been received.

At step S307, the host300may provide the storage device50with the second request in response to the first response when the generation of the host authentication code is completed. The second request may be for checking whether a result of a program operation on the write data is ready to be collected. The host300may provide the storage device50with the second request and the host authentication code.

At step S309, the storage device50may provide the host300with a second response indicating whether the second request has been received.

At step S311, the host300may provide the storage device50with the third request in response to the second response. The third request may be for the result of the program operation on the write data.

At step S313, the storage device50may provide the host300with a third response including the result of the program operation on the write data. The result of the program operation may include information indicating whether the program operation has passed or failed, and also may include information indicating whether the write data has integrity.

At step S315, the storage device50may receive the write data, together with the first request from the host300.

At step S317, the storage device50may generate a device authentication code based on a key shared with the host300and the received write data. The storage device50may generate the device authentication code by using a message authentication code (MAC) algorithm.

At step S319, the storage device50may determine whether the host authentication code has been received from the host300. When it is determined that the host authentication code has been received, the process flow may proceed to step S321. Alternatively, when it is determined that the host authentication code has not been received, the process flow may proceed to step S325.

At step S321, the storage device50may verify whether the write data has integrity. According to a result of verification, when it is determined that the write data has integrity, the process flow may proceed to step S323. Alternatively, when it is determined that the write data does not have integrity, the process flow may proceed to step S313.

At step S323, the storage device50may perform a program operation of storing the write data in the write protection area. After the program operation is performed, the storage device50may generate information indicating whether the program operation has passed or failed. After performing step S323, the process flow may proceed to step S313.

At step S325, the storage device50may wait until the host authentication code is received together with the second request from the host300. After performing step S325, the process flow may proceed to step S319.

In the embodiment illustrated inFIG.3, the generation of the host authentication code may be performed in parallel with the transmission of the write data from the host300to the storage device50. Accordingly, the time required to perform a security write operation may be reduced by the time during which the generation of the host authentication code overlaps the transmission of the write data.

According to another embodiment, the generation of the host authentication code may be performed in parallel with the generation of the device authentication code of the storage device50. Accordingly, the time required to perform the security write operation may be reduced by the time during which the generation of the host authentication code overlaps the generation of the device authentication code.

FIG.4is a diagram illustrating a configuration and operations of the computing system400shown inFIG.1according to an embodiment.

Referring toFIG.4, the computing system400may include the storage device50and the host300.

According to an embodiment, the memory device100may include a write protection area110.

The write protection area110may be a region in which write data W_DATA that has verified integrity is stored. Integrity may refer to a state in which the write data W_DATA received from the host300is not distorted or modulated.

The memory device100may perform a program operation of storing the write data W_DATA that has the verified integrity in the write protection area110in response to a program command received from the memory controller200. The memory device100may provide the memory controller200with a state read response STA_RES including information that indicates whether the program operation has passed or failed, in response to a state read command received from the memory controller200.

According to an embodiment, the memory controller200may include an authenticated write controller210and a data verification component220.

The authenticated write controller210may provide the host300with responses RES to a series of requests REQ regarding security write which are received from the host300. The series of requests REQ regarding the security write may include the first to third requests described with reference toFIGS.2and3.

For example, the authenticated write controller210may receive the first request and the write data W_DATA from the host300. The authenticated write controller210may provide the host300with a first response indicating whether the first request has been received, in response to the first request received from the host300. The first request may be for programming the write data W_DATA into the write protection area110of the memory device100.

The authenticated write controller210may receive the second request and a host authentication code HA_CODE from the host300. The authenticated write controller210may provide the host300with a second response indicating whether the second request has been received, in response to the second request received from the host300. The second request may be for checking whether a result of the program operation on the write data W_DATA is ready to be collected.

The authenticated write controller210may receive the third request to request the result of the program operation on the write data W_DATA from the host300. The authenticated write controller210may provide the host300with a third response including the result of the program operation on the write data W_DATA, in response to the third request received from the host300.

The authenticated write controller210may control the memory device100to store the write data W_DATA in the write protection area110. For example, the authenticated write controller210may determine whether the write data W_DATA has integrity based on authentication information AUT_INF received from the data verification component220. The authenticated write controller210may provide the memory device100with a program command about the write data W_DATA that has the verified integrity.

After providing the memory device100with the program command, the authenticated write controller210may provide the memory device100with the state read command to receive the result of the program operation. The authenticated write controller210may receive the state read response STA_RES indicating the result of the program operation from the memory device100. The state read response STA_RES may include information indicating whether the program operation has passed or failed.

The authenticated write controller210may provide the host300with a response including the result of the program operation of storing the write data W_DATA in the write protection area110. The result of the program operation may include information as to whether the write data W_DATA has the integrity and as to whether the program operation has passed or failed.

The data verification component220may generate the authentication information AUT_INF indicating the integrity of the write data W_DATA received from the host300. The data verification component220may provide the authenticated write controller210with the authentication information AUT_INF.

More specifically, the data verification component220may generate a device authentication code by using the write data W_DATA received from the host300and a key shared with the host300. The data verification component220may generate the authentication information AUT_INF indicating the integrity of the write data W_DATA based on a result of comparing the host authentication code HA_CODE received from the host300with the device authentication code. The host authentication code HA_CODE may be received when the authenticated write controller210receives the second request from the host300.

According to an embodiment, the host300may include a host processor310and host memory320.

The host processor310may provide the memory controller200with the series of requests REQ regarding security write. The series of requests REQ may include first to third requests as described with reference toFIGS.2and3.

The host processor310may provide the memory controller200with the write data W_DATA stored in the host memory320and the first request.

After providing the memory controller200with the first request, the host processor310may generate the host authentication code HA_CODE based on a key shared with the storage device50and the write data W_DATA.

The host processor310may provide the write data W_DATA to the memory controller200in parallel with the generation of the host authentication code HA_CODE. In other words, the generation of the host authentication code HA_CODE may be performed in parallel with the transmission of the write data W_DATA.

When the generation of the host authentication code HA_CODE is completed, the host processor310may provide the memory controller200with the second request and the host authentication code HA_CODE in response to the first response received from the memory controller200.

The host processor310may provide the memory controller200with the third request regarding the result of the program operation on the write data W_DATA, in response to the second response received from the memory controller200.

The host memory320may store the write data W_DATA to be provided to the memory controller200.

According to an embodiment described with reference toFIG.4, the generation of the host authentication code HA_CODE by the host processor310may be performed in parallel with the transmission of the write data W_DATA to the storage device50. Accordingly, a time required to perform a security write operation may be reduced by a time when the generation of the host authentication code HA_CODE overlaps the transmission of the write data W_DATA.

According to an embodiment described with reference toFIG.4, the generation of the host authentication code HA_CODE by the host processor310may be performed in parallel with the generation of the device authentication code by the data verification component220. Accordingly, the time required to perform the security write operation may be reduced by a time during which the generation of the host authentication code HA_CODE overlaps the generation of the device authentication code.

FIG.5is a diagram illustrating the data verification component220shown inFIG.4.

Referring toFIG.5, the data verification component220may include an authentication code generator221and an authentication code comparator222. The data verification component220may further include an encryption key storage223.

The authentication code generator221may generate a device authentication code DA_CODE based on the write data W_DATA received from the host and a shared key KEY received from the encryption key storage223. The authentication code generator221may generate the device authentication code DA_CODE by using a message authentication code (MAC) algorithm. The authentication code generator221may provide the authentication code comparator222with the device authentication code DA_CODE.

The authentication code comparator222may generate the authentication information AUT_INF indicating integrity of the write data W_DATA based on the comparison between the host authentication code HA_CODE received from the host and the device authentication code DA_CODE. The authentication code comparator222may determine whether the write data W_DATA has integrity according to whether the host authentication code HA_CODE is the same as the device authentication code DA_CODE.

The encryption key storage223may store the shared key KEY between the host and the storage device. The shared key KEY may be used for generating an authentication code. The shared key KEY may be previously stored in the encryption key storage223. The shared key KEY may be changed in response to a request of the host.

FIG.6is a diagram illustrating another embodiment of a memory controller shown inFIG.1.

Referring toFIG.6, a memory controller1000may be coupled to a host and a memory device. The memory controller1000may access the memory device in response to a request from the host. For example, the memory controller1000may control write, read, erase, and background operations of the memory device. The memory controller1000may provide an interface between the memory device and the host. The memory controller1000may be configured to drive firmware for controlling the memory device.

The memory controller1000may include a processor1010, a memory buffer1020, an error correction code (ECC) block1030, a host interface1040, a buffer controller1050, a memory interface1060, and a bus1070.

The bus1070may provide a channel between components of the memory controller1000.

The processor1010may control overall operation of the memory controller1000and may perform a logical operation. The processor1010may communicate with an external host through the host interface1040and communicate with the memory device through the memory interface1060. Further, the processor1010may communicate with the memory buffer1020through the buffer controller1050. The processor1010may control operations of a storage device by using the memory buffer1020as operational memory, cache memory or buffer memory.

The processor1010may perform the function of a flash translation layer (FTL). The processor1010may translate a logical block address (LBA), which is provided by the host, to a physical block address (PBA) through the FTL. The FTL may receive the LBA and translate the LBA to the PBA by using a mapping table. There may be various address mapping methods for the FTL depending on a mapping unit. Typical address mapping methods may include a page mapping method, a block mapping method and a hybrid mapping method.

The processor1010may be configured to randomize data received from the host. For example, the processor1010may randomize the data received from the host using a randomizing seed. The randomized data may be provided to the memory device as data to be stored and may be programmed into a memory cell array.

The processor1010may be configured to derandomize data received from the memory device during a read operation. For example, the processor1010may derandomize the data received from the memory device using a derandomizing seed. The derandomized data may be output to the host.

According to an embodiment, the processor1010may run software or firmware to perform randomizing and derandomizing operations.

The memory buffer1020may serve as operational memory, cache memory, or buffer memory of the processor1010. The memory buffer1020may store codes and commands executed by the processor1010. The memory buffer1020may store data processed by the processor1010. The memory buffer1020may include Static RAM (SRAM) or Dynamic RAM (DRAM).

The ECC block1030may perform error correction. The ECC block1030may perform ECC encoding based on data to be written to the memory device through the memory interface1060. The ECC-encoded data may be transmitted to the memory device through the memory interface1060. The ECC block1030may perform ECC decoding on data received from the memory device through the memory interface1060. For example, the ECC block1030may be included as a component of, and disposed in, the memory interface1060.

The host interface1040may be configured to communicate with the external host under the control of the processor1010. The host interface1040may perform communication using at least one of various communication methods such as a Universal Serial Bus (USB), Serial AT Attachment (SATA), a Serial Attached SCSI (SAS), a High Speed Interchip (HSIC), a Small Computer System Interface (SCSI), a Peripheral Component Interconnection (PCI), PCI express (PCIe), NonVolatile Memory express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), a MultiMedia Card (MMC), an embedded MMC (eMMC), a Dual In-line Memory Module (DIMM), a Registered DIMM (RDIMM), and a Load Reduced DIMM (LRDIMM).

The buffer controller1050may be configured to control the memory buffer1020under the control of the processor1010.

The memory interface1060may be configured to communicate with the memory device under the control of the processor1010. The memory interface1060may exchange commands, addresses, and data with the memory device through channels.

In an embodiment, the memory controller1000does not include the memory buffer1020and the buffer controller1050. Instead, one or both of these components may be provided separately, and/or the functionality of one or both such components may be distributed within the memory controller1000.

For example, the processor1010may control the operations of the memory controller1000using codes. The processor1010may load codes from a nonvolatile memory device provided in the memory controller1000(for example, Read Only Memory (ROM)). In another example, the processor1010may load codes from the memory device through the memory interface1060.

For example, the bus1070of the memory controller1000may be divided into a control bus and a data bus. The data bus may be configured to transmit data in the memory controller1000, and the control bus may be configured to transmit control information such as commands and addresses in the memory controller1000. The data bus and the control bus may be isolated from each other so as not to interfere with, nor influence, each other. The data bus may be coupled to the host interface1040, the buffer controller1050, the ECC block1030, and the memory interface1060. The control bus may be coupled to the host interface1040, the processor1010, the buffer controller1050, the memory buffer1020, and the memory interface1060.

According to an embodiment, the authenticated write controller210and the data verification component220may be included in the processor1010.

FIG.7is a block diagram illustrating a memory card system2000to which a storage device is applied according to an embodiment of the present disclosure.

Referring toFIG.7, the memory card system2000may include a memory controller2100, a memory device2200, and a connector2300.

The memory controller2100may be coupled to the memory device2200. The memory controller2100may access the memory device2200. For example, the memory controller2100may be configured to control read, write, erase and background operations of the memory device2200. The memory controller2100may be configured to provide an interface between the memory device2200and the host. The memory controller2100may be configured to drive firmware for controlling the memory device2200. The memory controller2100may be configured in the same manner as the memory controller200described above with reference toFIG.1.

For example, the memory controller2100may include components, such as Random Access Memory (RAM), a processing unit, a host interface, a memory interface, and an ECC block.

The memory controller2100may communicate with an external device through the connector2300. The memory controller2100may communicate with the external device (for example, a host) based on a specific communication protocol. For example, the memory controller2100may communicate with the external device through at least one of various communication protocols such as a Universal Serial Bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnection (PCI), PCI-express (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial-ATA (SATA), Parallel-ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth, and/or nonvolatile memory express (NVMe). For example, the connector2300may be defined by at least one of the above-described various communication protocols.

For example, the memory device2200may be implemented as any of various nonvolatile memory devices, such as Electrically Erasable and Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase-change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and/or Spin-Transfer Torque Magnetic RAM (STT-MRAM).

The memory controller2100and the memory device2200may be integrated into a single semiconductor device to form a memory card. For example, the memory controller2100and the memory device2200may be integrated into a single semiconductor device and form a memory card, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), a smart media card (e.g., SM or SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro, or eMMC), a secure digital (SD) card (e.g., SD, miniSD, microSD, or SDHC), and universal flash storage (UFS).

FIG.8is a block diagram illustrating a solid state drive (SSD) system3000to which a storage device is applied according to an embodiment of the present disclosure.

Referring toFIG.8, the SSD system3000may include a host3100and an SSD3200. The SSD3200may exchange signals with the host3100through a signal connector3001and may receive power through a power connector3002. The SSD3200may include an SSD controller3210, a plurality of flash memory3221to322n, an auxiliary power supply3230, and a buffer memory3240.

According to an embodiment, the SSD controller3210may perform the function of the memory controller200described above with reference toFIG.1.

The SSD controller3210may control the plurality of flash memory3221to322nin response to the signals received from the host3100. For example, the signals may be based on the interfaces of the host3100and the SSD3200. For example, the signals may be defined by at least one of various interfaces such as a Universal Serial Bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnection (PCI), PCI-express (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial-ATA (SATA), Parallel-ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth, and/or nonvolatile memory express (NVMe).

The auxiliary power supply3230may be coupled to the host3100through the power connector3002. The auxiliary power supply3230may be charged with power supplied from the host3100. The auxiliary power supply3230may supply power of the SSD3200when power is not smoothly supplied from the host3100. For example, the auxiliary power supply3230may be disposed within or external to the SSD3200. For example, the auxiliary power supply3230may be disposed on a main board and may supply auxiliary power to the SSD3200.

The buffer memory3240may function as buffer memory of the SSD3200. For example, the buffer memory3240may temporarily store data received from the host3100or data received from the plurality of flash memory3221to322n, or may temporarily store metadata (for example, mapping tables) of the flash memory3221to322n. The buffer memory3240may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or GRAM or nonvolatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

According to an embodiment, the host3100may operate in the same manner as the host300described with reference toFIG.4.

FIG.9is a block diagram illustrating a user system4000to which a storage device is applied according to an embodiment of the present disclosure.

Referring toFIG.9, the user system4000may include an application processor4100, a memory module4200, a network module4300, a storage module4400, and a user interface4500.

The application processor4100may operate components included in the user system4000, an Operating System (OS), or a user program. For example, the application processor4100may include controllers, interfaces, graphic engines, and the like, for controlling the components included in the user system4000. The application processor4100may be provided as a System-on-Chip (SoC).

The memory module4200may function as main memory, operational memory, buffer memory, or cache memory of the user system4000. The memory module4200may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM or nonvolatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor4100and the memory module4200may be packaged based on Package-on-Package (POP) and may then be provided as a single semiconductor package.

The network module4300may communicate with external devices. For example, the network module4300may support wireless communication, such as Code Division Multiple Access (CDMA), Global System for Mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), Wimax, WLAN, UWB, Bluetooth, or Wi-Fi. For example, the network module4300may be included in the application processor4100.

The storage module4400may store data. For example, the storage module4400may store data received from the application processor4100. Alternatively, the storage module4400may transmit the data stored in the storage module4400to the application processor4100. According to an embodiment, the storage module4400may be implemented as a nonvolatile semiconductor memory device, such as Phase-change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory having a three-dimensional (3D) structure. For example, the storage module4400may be provided as a removable storage medium (i.e., removable drive), such as a memory card or an external drive of the user system4000.

According to an embodiment, the storage module4400may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may operate in the same manner as the memory device as described above with reference toFIG.1. The storage module4400may operate in the same manner as the storage device50described above with reference toFIG.1.

The user interface4500may include interfaces which input data or commands to the application processor4100or output data to an external device. For example, the user interface4500may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, or a piezoelectric device. The user interface4500may further include user output interfaces such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display device, an Active Matrix OLED (AMOLED) display device, an LED, a speaker, or a monitor.

According to embodiments of the present disclosure, a computing system having improved write performance and an operating method of the computing system are provided.

While the present invention has been illustrated and described in connection with various embodiments, those skilled in the art will understand in light of this disclosure that various changes in form and operation may be made without departing from the spirit and scope of the present invention. The present invention encompasses all such changes that fall within the scope of the claims.