Patent ID: 12190949

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In some embodiments, a memory circuit uses a feedback configuration to generate a bias voltage whereby loading is reduced and the speed of a read operation is increased compared to other approaches. The memory circuit includes a current path with a resistance-based memory device and a replica resistive device that mimics resistance characteristics of at least a portion of the current path including the resistance-based memory device. In some embodiments, a local buffer circuit is provided to generate the bias voltage that is used by a voltage clamp device to drive a drive voltage to the current path during a read operation, and the feedback is provided by another buffer circuit configured to generate another bias voltage that is provided to the replica resistive device. In some embodiments, the bias voltage is provided using the feedback configuration including a reference current conducted through the replica resistive device to generate a reference voltage.

Compared to approaches that do not include such feedback arrangements, standby power of the bias voltage generator is decreased and the amount of charge that can be delivered dynamically is increased, thereby reducing power consumption and increasing the speed of the memory circuit.

FIGS.1A and1Bare diagrams of a memory circuit100, in accordance with some embodiments.FIG.1Ais a top-level diagram including a bias voltage generator110coupled to multiple instances of a voltage clamp device120coupled in series between corresponding instances of a sense amplifier SA and a current path111.FIG.1Bis a diagram of a single instance of the current path111, sense amplifier SA, and voltage clamp device120coupled to the bias voltage generator110in the memory circuit100.

FIG.1Adepicts details of the bias voltage generator110that are discussed below, andFIG.1Bdepicts details of the current path111including an instance of a resistance-based memory device150.

For the purpose of illustration,FIG.1Bdepicts each resistance-based memory device150coupled between conduction lines L1 and L2. In some embodiments, memory circuit100is a subset of a memory macro (not shown) that includes one or more additional components, e.g., at least one control or logic circuit in addition to the array of resistance-based memory devices150depicted inFIGS.1A and1B.FIG.1Aalso depicts power source voltage/nodes VDD, and each ofFIGS.1A and1Balso depicts power reference voltage/nodes, e.g., a ground, designated by ground symbols.

Each resistance-based memory device150is a memory storage device capable of having either a high resistance state (HRS) or a low resistance state (LRS) indicative of a logical state. In some embodiments, each resistance-based memory device150includes a terminal152coupled to its respective conduction line L1 and a terminal153coupled to its respective conduction line L2. Resistance-based memory device150includes a resistive layer (not shown) capable of having either largely insulating properties corresponding to the HRS or largely conductive properties corresponding to the LRS, e.g., based on the respective absence or presence of one or more filaments, also referred to as conduction paths. In operation, filaments are formed, e.g., thereby setting resistance-based memory devices150to the LRS, based on one or more of various mechanisms, e.g., vacancy or defect migration or another suitable mechanism, and broken, thereby resetting resistance-based memory devices150to the HRS, based on heating or one or more other suitable mechanisms.

Resistance-based memory device150includes a selection transistor (not shown) coupled in series with the resistive layer and having a gate coupled to an input terminal (not shown), and is thereby configured to couple resistance-based memory device150to its respective conduction line pair L1/L2 in response to an activation voltage. In some embodiments, the resistance-based memory device150includes an RRAM device, a magnetic tunnel junction (MTJ) device, a phase change memory (PCM) device, and/or the like. In some embodiments ofFIGS.1A and1B, each resistance-based memory device150includes an RRAM device.

In some embodiments, the resistance-based memory device150has a resistance value in the LRS ranging from 1 kilo-ohm (kΩ) to 4 kΩ and/or a resistance value in the HRS ranging from 15 kΩ to 30 kΩ. Other resistance values/ranges are within the scope of the present disclosure.

Resistance-based memory device150is thereby readable based on a memory cell voltage V12 equal to a difference between a voltage V1 at terminal152and a voltage V2 at terminal153, as reduced by the level of a drain-source voltage across the selection transistor.

Memory circuit100, or a memory macro including memory circuit100, is configured such that memory cell voltage V12 has a read voltage level corresponding to detecting the LRS or HRS of resistance-based memory device150in a read operation. In order to program resistance-based memory device150, the memory cell voltage V12 is set at a first programming voltage level to set resistance-based memory device150at the LRS and at a second programming voltage level to set resistance-based memory device150at the HRS. In some embodiments, each of the first programming voltage level and the second programming voltage level is higher in magnitude than the read voltage level.

In various embodiments, each of the first and second write operations and the read operation has a same polarity, or one of the first or second write operations or the read operation has a polarity different from that of the other two of the first or second write operations or the read operation. In each of the first and second write operations and the read operation, memory cell voltage V12 applied to resistance-based memory device150causes a current Id to flow between terminals152and153in a direction determined by the polarity of the memory cell voltage.

During a read operation, the memory cell voltage V12 is set at the read voltage level so that the current Id is generated. The current Id has a first current level when the resistance-based memory device150is in the HRS and a second current level when the resistance-based memory device150is in the LRS. Because a resistance level of the HRS is higher than the resistance level of the LRS, the first current level is lower than the second current level. Each sense amplifier SA is configured to detect whether the current Id has the first current level or the second current level and thus detect whether its corresponding resistance-based memory device150is in the HRS or in the LRS.

Each resistance-based memory device150is provided in a current path111. A voltage clamp device120is configured to generate a drive voltage VD and apply the drive voltage VD to the current path111in order to generate the current Id. InFIGS.1A and1B, each sense amplifier SA is depicted as being coupled to a single respective resistance-based memory device150and a single pair of conduction lines L1, L2. This configuration is a non-limiting example provided to simplify the explanation. In some embodiments, each sense amplifier SA and each voltage clamp device120is coupled to a set of resistance-based memory devices150, wherein each resistance-based memory device150in the set is coupled to a different pair of conduction lines.

Two or more circuit elements are considered to be coupled based on one or more direct electrical connections and/or one or more indirect electrical connections that include one or more logic devices, e.g., an inverter or logic gate, between the two or more circuit elements. In some embodiments, electrical communications between the two or more coupled circuit elements are capable of being modified, e.g., inverted or made conditional, by the one or more logic devices.

As shown inFIG.1B, each current path111is coupled between a corresponding voltage clamp device120and power reference node. A voltage clamp device, e.g., voltage clamp device120, is a switching device, e.g., an NMOS device, configured to limit a voltage at a conduction path terminal, e.g. a source terminal, based on a voltage received at a control terminal, e.g., a gate terminal.

Current path111includes path segments130and140, conduction lines L1 and L2 coupled between path segments130and140, and resistance-based memory device150coupled between conduction lines L1 and L2. In some embodiments, path segment130is a multiplexer that is configured to select conduction line L1. In this case, path segment140is a multiplexer that is configured to select conduction line L2. In other embodiments, path segment130is a multiplexer that is configured to select conduction line L2. In this case, path segment140is a multiplexer that is configured to select conduction line L1.

In operation, when multiple resistance-based memory devices150(coupled between their individual pairs of conduction lines) are coupled to each of the sense amplifiers SA and each of the voltage clamp devices120, the path segments130,140are used to select among the various resistance-based memory devices150(by selecting among the pairs of conduction lines). When a resistance-based memory device150is selected by the path segments130,140, the current Id flows through the resistance-based memory device150(and thus through the corresponding individual pair of conduction lines) but does not flow to the other resistance-based memory devices150(and the other corresponding pairs of conduction lines) that are also coupled to the individual sense amplifier SA and voltage clamp device120.

In order for the sense amplifier SA to detect whether the selected resistance-based memory device150is in the HRS or the LRS in a read operation, the drive voltage VD applied to the current path111is maintained at the appropriate drive voltage level. However, changes in the operation of the voltage clamp device120due to temperature variations can result in variations in the drive voltage level.

To control the drive voltage level of the drive voltages VD generated by the voltage clamp devices120, the memory circuit100includes the bias voltage generator110coupled to each voltage clamp device120. The bias voltage generator110is configured to generate and control a bias voltage VGB for each voltage clamp device120. More specifically, the bias voltage generator110is configured to maintain the drive voltage level of the drive voltages VD generated by each of the voltage clamp devices120near constant voltage regardless of a resistance, e.g., based on a resistive state, coupled between the voltage clamp device120and the power reference node. The bias voltage generator110is configured to adjust the voltage level of the bias voltage VGB to maintain the drive voltage VD at the drive voltage level required in order for the sense amplifier SA to detect whether the respective resistance-based memory device150is in the LRS or the HRS.

The bias voltage generator110includes a global control circuit139and local buffers144. In the embodiment depicted inFIG.1A, the bias voltage generator110includes thirty-two local buffers144, one for each of the voltage clamp devices120. In other embodiments, the bias voltage generator110includes more than thirty-two or fewer than thirty-two local buffers144. Each of the local buffers144is configured to generate the bias voltage VGB, which is received at a corresponding one of the voltage clamp devices120. In some embodiments, the local buffers144are not loaded by the components of the buffer141, which includes components to mimic the resistive behavior of the voltage clamp devices120and current paths111with the resistance-based memory devices150. By providing the local buffers144, the size of the bias voltage generator110can be reduced and thereby save power and area.

InFIGS.1A and1B, each of the voltage clamp devices120includes an NMOS device. A gate of the NMOS device is configured to receive the bias voltage VGB from a respective one of the local buffers144to which it is coupled. A drain of the NMOS device is coupled to a respective one of the sense amplifiers (SA) while a source of the NMOS device is coupled to the current path111. The NMOS device is configured to generate the current Id from the current path.

InFIG.1A, the global control circuit139is configured to generate a bias voltage VG. In operation, the bias voltage VG is received by each of the local buffers144, and each of the local buffers144is configured to adjust the bias voltage VGB based on the bias voltage VG. As discussed below, the global control circuit139is configured to adjust the bias voltage level of the bias voltage VG in order to adjust the bias voltage level of the bias voltage VGB and maintain the drive voltage level of the drive voltage VD as required by the sense amplifier SA. By separating the global control circuit139from the local buffers144, the global control circuit139is not loaded by the voltage clamp devices120and the current paths111and is thereby capable of consuming less power and taking up a smaller area compared to approaches in which a control circuit is loaded by voltage clamp device circuits.

The global control circuit139includes an operational amplifier143, a buffer141, and a replica circuit145. The replica circuit145is configured to mimic a resistance of at least a portion of the current path111having resistance-based memory device150. The replica circuit145is configured to provide a path resistance having a predetermined resistance value based on the resistance of the current path111. In other words, the replica circuit145is configured to mimic the resistive behavior of the first current path111as the operating conditions (e.g., temperature, physical, voltage conditions) of the first current path111vary. In various embodiments, the replica circuit145includes a polycrystalline silicon material (poly), a compound material including silicon, a semiconductor material or compound, or other material suitable to mimic the resistive behavior of the first current path111. In some embodiments, the predetermined resistance value is based on a resistance value of a resistance-based memory device, e.g., resistance-based memory device150or at least some portion of the current path111including resistance-based memory device150.

In various embodiments, the predetermined resistance value corresponds to the resistance value of the resistance-based memory device in the HRS or the LRS, a resistance value above the resistance value of the resistance-based memory device in the HRS, a resistance value below the resistance value of the resistance-based memory device in the LRS, or a resistance value between the resistance values of the resistance-based memory device in the HRS and the LRS. In some embodiments, the replica circuit145is configured to mimic the resistive behavior of the voltage clamp device120and the entire current path111.

In various embodiments, the replica circuit145is configured to have the predetermined resistance value equal to the resistance-based memory device resistance value or to another value derived from the resistance-based memory device resistance value, e.g., a multiple or fraction of the resistance-based memory device resistance value.

The replica circuit145does not receive the bias voltage VGB that is received by the voltage clamp device120. Instead, the buffer141is configured to generate a bias voltage VGB′ and the replica circuit145is configured to receive the bias voltage VGB′ from the buffer141. The buffer141is configured to receive the bias voltage VG from the operational amplifier143and adjust the bias voltage VGB′ based on the bias voltage VG.

In operation, the operational amplifier143and replica circuit145are used to imitate the resistive behavior of the current path111and ensure that the drive voltage VD is maintained at the appropriate drive voltage level. The operational amplifier143is configured to generate the bias voltage VG and adjust the bias voltage VG based on feedback from the replica circuit145. More specifically, the replica circuit145is configured to generate a drive voltage VRBL. The replica circuit145is configured to adjust the drive voltage VRBL based on the bias voltage VGB′. In operation, because the replica circuit145mimics the resistive behavior of the current path111, the drive voltage level of the drive voltage VRBL mimics the drive voltage level of the drive voltage VD.

The bias voltage generator110is configured to adjust the bias voltage VG based on a voltage difference between a reference voltage Vref and the drive voltage VRBL. InFIG.1A, the operational amplifier143has a non-inverting input terminal NIT configured to receive the reference voltage Vref, an inverting terminal IT configured to receive the drive voltage VRBL, and an output terminal OT configured to output the bias voltage VG. The reference voltage Vref is set to a nearly constant reference voltage level. The reference voltage Vref has a predetermined reference voltage level configured to, in operation, cause the operational amplifier143to adjust the bias voltage VG such that the drive voltage levels of the drive voltages VD maintain the current levels of the currents Id at an appropriate reading level magnitude despite variations in the resistive behavior of the current paths111due to operational and environmental variations.

FIG.2is a diagram of a memory circuit100A, in accordance with some embodiments.

Memory circuit100A is one embodiment of the memory circuit100. Components in memory circuit100A that the same as the components in memory circuit100are labeled with the same component numbers inFIG.2as inFIGS.1A and1Band are not described again for the sake of brevity.

The memory circuit100A includes a bias voltage generator110A that includes a global control circuit139A and a local buffer144A. In this embodiment, a single buffer is shown as the local buffer144A. In some embodiments, all of the local buffers144are identical to local buffer144A. In some embodiments, the other local buffers144have a different configuration than the local buffer144A, such as the configurations discussed below with respect toFIGS.4and5. In some embodiments, one or more of the other local buffers144are provided in the same manner as local buffer144A while one or more other of the other local buffers144are provided in a different configuration.

The bias voltage generator110A includes a global control circuit139A, which is one embodiment of the global control circuit139shown inFIG.1A. The global control circuit139A includes the operational amplifier143described above along with a buffer141A and a replica circuit145A. The buffer141A is an embodiment of the buffer141, described above with respect toFIG.1Aand the replica circuit145A is an embodiment of the replica circuit145, also described above with respect toFIG.1A.

In the embodiment depicted inFIG.2, the bias voltage generator110A includes a capacitive device C1 coupled between the output terminal OT of the operational amplifier143and the power reference node. In some embodiments, a capacitive device, e.g., the capacitive device C1, includes a capacitor or an NMOS or PMOS device configured as a capacitor. In operation, the capacitive device C1 acts to stabilize the bias voltage VG, e.g., by decoupling noise from the local buffer144and/or144A. In some embodiments, the bias voltage generator110A does include the capacitive device C1.

The local buffer144A includes a current source200and an NMOS device202coupled to the current source200in a source follower configuration. In this embodiment, a drain of the NMOS device202is configured to receive power source voltage VDD, a gate of the NMOS device202is configured to receive the bias voltage VG from the output terminal OT of the operational amplifier143, and the source of the NMOS device202is coupled to a node BN1. The node BN1 is coupled to the gate of the voltage clamp device120and to an anode of the current source200. A cathode of the current source200is coupled to the power reference node. As such, the NMOS device202is configured to operate in the triode region. The current source200is configured to generate a current IB1. The NMOS device202is configured to generate the bias voltage VGB at node BN1 from the source of the NMOS device202. Accordingly, the NMOS device202is configured to, in operation, conduct the current IB1 of the current source200and thereby adjust the bias voltage level of the bias voltage VGB such that the conducted current matches current IB1 generated by the current source200. The NMOS device202is thereby configured to adjust the bias voltage level of the bias voltage VGB in accordance with a change in the bias voltage level of the bias voltage VG in order to ensure that the current IB1 is conducted as generated by the current source200. An advantage of the local buffer144A is that the NMOS device202draws very little current at the gate and presents a low impedance to the voltage clamp device120.

The current source200is configured to operate in an active state and in a standby state. In the active state, the local buffer144A is actively operating to perform the read operation. In the standby state, the local buffer144A is on but is not actively operating to perform a read operation. Thus, the current source200is configured to generate the current IB1 having a first current level in the active state and a second current level in the standby state, the first current level being of a higher magnitude than the second current level.

In some embodiments, the current source200is configured to generate the current IB1 having the first current level ranging from 100 microamperes (μA) to 10 milliamperes (mA). In some embodiments, the current source200is configured to generate the current IB1 having the first current level ranging from 900 μA to 1.1 mA, e.g., at or near 1 mA. Other first current levels/ranges are within the scope of the present disclosure.

In some embodiments, the current source200is configured to generate the current IB1 having the second current level ranging from 1 μA to 100 μA. In some embodiments, the current source200is configured to generate the current IB1 having the second current level ranging from 8 μA to 12 μA, e.g., at or near 10 μA. Other second current levels/ranges are within the scope of the present disclosure.

The buffer141A includes a current source204and an NMOS device206coupled to the current source204in a source follower configuration. In this embodiment, a drain of the NMOS device206is configured to receive power source voltage VDD, a gate of the NMOS device206is configured to receive the bias voltage VG from the output terminal OT of the operational amplifier143, and a source of the NMOS device206is coupled to a node BN2. The node BN2 is coupled to a gate of a voltage clamp device120R in the replica circuit145A and to an anode of the current source204. A cathode of the current source204is coupled to the power reference node. As such, the NMOS device206is configured to operate in the triode region. The current source204is configured to generate a current IB2. The NMOS device206is configured to generate the bias voltage VGB′ at node BN2 from the source of the NMOS device206. Accordingly, the NMOS device206is configured to, in operation, conduct the current IB2 of the current source204and thereby adjust the bias voltage level of the bias voltage VGB′ such that the conducted current matches current IB2 generated by the current source204. The NMOS device206is thereby configured to adjust the bias voltage level of the bias voltage VGB′ in accordance with a change in the bias voltage level of the bias voltage VG in order to ensure that the current IB2 is conducted as generated by the current source204. An advantage of the buffer141A is that the NMOS device206draws very little current at the gate and presents a low impedance to the voltage clamp device120R.

In this embodiment, the current level of the current IB2 is approximately equal to the second current level of the current IB1 when the current source200is in the standby mode. In operation, the local buffer141A also maintains the feedback to generate the bias voltage VGB by the local buffer144A during the standby state, thereby significantly reducing the amount of power consumed by the memory circuit100A during the standby state compared to other approaches. Furthermore, the local buffer144A is capable of delivering a dynamic change in charge to the gate of its respective voltage clamp device120and thereby stabilize the bias voltage VGB during a disturbance or a transition.

The replica circuit145A is configured to mimic the resistive behavior of the voltage clamp device120and the current path111. The replica circuit145A includes the voltage clamp device120R, a replica path segment130R, a replica resistance-based memory device150R, and a replica path segment140R. The voltage clamp device120R is configured to mimic the operation of the voltage clamp device120, the replica path segment130R is configured to mimic the resistive behavior of the path segment130, the replica resistance-based memory device150R is configured to mimic the resistive behavior of the resistance-based memory device150, and the replica path segment140R is configured to mimic the resistive behavior of the path segment140. The replica path segment130R, the replica resistance-based memory device150R, and the replica path segment140R make up a replica current path111R. The replica current path111R is thereby configured to mimic the resistive behavior of the current path111.

In this embodiment, the voltage clamp device120R is an NMOS device having a drain configured to receive the power supply voltage VDD, a gate configured to receive the bias voltage VGB′ from the node BN2 and a source that is coupled to a feedback node FBN. The voltage clamp device120R is configured to generate the drive voltage VRBL from the source such that, in operation, the drive voltage VRBL is applied to the replica current path111R at the feedback node FBN, thereby generating a replica current IR that propagates through the replica current path111R. The replica path segment130R includes three FETs coupled in series to mimic the resistance of one of the path segments130, which in some embodiments are multiplexers. The replica path segment140R includes two FETs coupled in series to mimic the resistance of one of the path segments140, which in some embodiments are multiplexers.

The replica resistance-based memory device150R includes a replica selection transistor151R and a replica resistive device RP1. The replica selection transistor151R is configured to mimic the resistive behavior of the selection transistor in the resistance-based memory device150. In some embodiments, transistor151R has dimensions that match those of the selection transistor of resistance-based memory device150such that, for a given transistor bias defined by the current level of replica current IR and the output voltage of amplifier143, transistor151R has a voltage drop equal to a value of the drain-source voltage of the selection transistor in the resistance-based memory device150having the same transistor bias. In various embodiments, transistor151R has dimensions related to those of the selection transistor such that, for the given transistor bias, transistor151generates voltage drop having a value derived from the drain-source voltage value, e.g., a multiple or fraction of the drain-source voltage value.

Resistive device RP1 is one or more conductive segments configured to provide a path resistance. The one or more conductive segments have dimensions configured to provide the path resistance having a predetermined resistance value. In various embodiments, the one or more conductive segments include a polycrystalline silicon material (poly), a compound material including silicon, a semiconductor material or compound, or other material suitable for having the predetermined resistance value. In some embodiments, the predetermined resistance value is based on a resistance value of a resistance-based memory device, e.g., resistance-based memory device150.

In various embodiments, the predetermined resistance value corresponds to the resistance value of the resistance-based memory device150in the HRS or the LRS. In some embodiments, a resistance value is above the resistance value of the resistance-based memory device150in the HRS, a resistance value is below the resistance value of the resistance-based memory device150in the LRS, or a resistance value is between the resistance values of the resistance-based memory device150in the HRS and the LRS.

In various embodiments, resistive device RP1 is configured to have the predetermined resistance value equal to the resistance-based memory device150resistance value or to another value derived from the resistance-based memory device150resistance value, e.g., a multiple or fraction of the resistance-based memory device150resistance value. In some embodiments, in addition to the resistance value of the resistance-based memory device150, the predetermined resistance value of the resistive device RP1 includes the resistance value of the appropriate portions of one pair of the conduction lines L1, L2. Thus, in these embodiments, the predetermined resistance value is set in accordance with a resistive value of the resistance-based memory device150plus the resistance value of the appropriate portions of one pair of the conduction lines L1, L2.

In some embodiments, resistive device RP1 is configured to have the predetermined resistance value ranging from 1 kΩ to 50 kΩ. In some embodiments, resistive device RP1 is configured to have the predetermined resistance value ranging from 2 kΩ to 5 kΩ. Other predetermined resistance values/ranges are within the scope of the present disclosure.

In operation, the drive voltage level of the drive voltage VRBL is thereby applied to the replica current path111R that mimics the resistive behavior of one of the current paths111including an instance of the resistance-based memory device150. The drive voltage VRBL is fed back to the inverting terminal IT of the operational amplifier143, and the operational amplifier143is configured to adjust the bias voltage level of the bias voltage VG until the drive voltage level of the drive voltage VRBL and the reference voltage level of the reference voltage Vref are approximately equal. The bias voltage level of the bias voltage VGB′ received at the gate of the replica voltage clamp device120R is thereby adjusted by the buffer141A. In response, the local buffer144A is configured to provide a corresponding adjustment in the bias voltage level of the bias voltage VGB received at the gate of the voltage clamp device120. As a result, the voltage clamp device120is configured to adjust the drive voltage level of the drive voltage VD in response to the corresponding adjustment in the bias voltage level of the bias voltage VGB. In this manner, the drive voltage level of the drive voltage VD is maintained at the appropriate voltage level in accordance with the reference voltage level of the reference voltage Vref.

In some embodiments, the replica circuit145A is configured to generate replica current IR having a current level corresponding to the second current level generated by current source200in the standby state as discussed above. In some embodiments, the current source204is configured to generate the current IB2 having a current level corresponding to the second current level generated by current source200in the standby state. In some embodiments, the operational amplifier143is configured to draw a current on the same order of magnitude as the second current level generated by current source200in the standby state.

Memory circuit100A is thereby configured to have a total standby current less than that of a memory circuit based on an approach that does not include the operational amplifier143, the buffer141A, the replica circuit145A, and the instances of local buffers144and/or144A.

In a non-limiting example, in the standby state, the operational amplifier143draws 40 μA, the buffer141A draws 10 μA, the replica circuit145A draws 10 μA, and each of 32 instances of the local buffer144and/or144A draws 10 μA such that the bias voltage generator110A of the memory circuit100A draws a total of 380 μA in the standby state. Other current levels/ranges are within the scope of the present disclosure.

FIG.3is a graph that illustrates the bias voltage VGB during a read operation in accordance with some embodiments.

FIG.3depicts a non-limiting example in which an instance of the bias voltage VGB generated by the bias voltage generator110A of the memory circuit100A shown inFIG.2is plotted over time. A control signal C1 is configured to switch between a low voltage state to a high voltage state at a time t1 corresponding to the memory circuit100A being switched from an off state to the standby state. At a time t2, a control signal C2 is switched from the low voltage state to the high voltage state corresponding to the memory circuit100A being switched from the standby state to the active state, during which the memory circuit100A performs a read operation. At a time t3, the read operation ends, the control signal C2 is switched from the high voltage state to the low voltage state, and the memory circuit100A is switched from the active state back to the standby state.

In the non-limiting example ofFIG.3, the bias voltage VGB has an initial voltage level of approximately 300 millivolts (mV) for a period prior to time t1 through time t2. Between times t2 and t3, the bias voltage VGB exhibits a voltage drop during the read operation of approximately 30 mV followed by a return to the initial voltage level of approximately 300 mV, a performance level comparable to that of other approaches in which a bias voltage is generated without using the operational amplifier143, the buffer141A, the replica circuit145A, and the instances of local buffers144and/or144A. Other initial voltage levels and/or voltage drop levels are within the scope of the present disclosure.

FIG.4is a diagram of a memory circuit100B, in accordance with some embodiments.

Memory circuit100B is one embodiment of the memory circuit100. Components in memory circuit100B that are the same as the components in memory circuit100A and the memory circuit100are labeled with the same component numbers inFIG.4as inFIGS.1A-2and are not described again for the sake of brevity.

The memory circuit100B includes a bias voltage generator110B that includes the global control circuit139A and a local buffer144B. In this embodiment, only the buffer1is shown as the local buffer144B. In some embodiments, all of the local buffers144are identical to local buffer144B. In some embodiments, the other local buffers144have a different configuration than the local buffer144B, such as the local buffer144A discussed above and/or the configurations discussed herein with respect toFIGS.2,3, and5. In some embodiments, one or more of the other local buffers144are provided in the same manner as local buffer144B while one or more other of the other local buffers144are provided in a different configuration.

The local buffer144B includes a current source400and an NMOS device402coupled to the current source400in a source follower configuration. In this embodiment, a drain of the NMOS device402is configured to receive the power source voltage VDD, a gate of the NMOS device402is configured to receive the bias voltage VG from the output terminal OT of the operational amplifier143, and the source of the NMOS device402is coupled to the node BN1. The node BN1 is coupled to the gate of the voltage clamp device120and to an anode of the current source400. A cathode of the current source400is coupled to the power reference node. As such, the NMOS device402is configured to operate in the triode region. The current source400is configured to generate the current IB1. In this embodiment, the current source400is configured to generate the current IB1 at the second current level both in the standby state and in the active state. Thus, unlike the current source200discussed above with respect toFIG.2, the current source400does not operate at two different current levels depending on whether the memory circuit100B is in the standby state or in the active state.

The local buffer144B also includes a current source404and an NMOS device406. The current source404and the NMOS device406are configured to be deactivated in the standby state and activated in the active state. The NMOS device406has a gate configured to receive the bias voltage VG. A node408is configured to receive the power supply voltage VDD. A switch410is coupled between the node408and the drain of the NMOS device406. The switch410is configured to be open in the standby state and closed in the active state. Accordingly, in the active state, the NMOS device406receives the power supply voltage VDD at the drain of the NMOS device406. In the standby state, the NMOS device406does not receive the power supply voltage VDD at the drain and thus is inactive. A source of the NMOS device is coupled to a node BN3. The node BN3 is coupled to the node BN1 and to the gate of the voltage clamp device120. A switch412is coupled between the node BN3 and an anode of the current source404. The switch412is configured to be open in the standby state and closed in the active state. Accordingly, the current source404is activated in the active state and deactivated in the standby state. When the current source404is activated, the current source404is configured to generate a current IB3 having a third current level. In some embodiments, the first current level discussed above with respect toFIG.2is approximately equal to the second current level plus the third current level. As such, when the local buffer144B is in the active state during a read operation, the current source400and the current source404are configured to generate a total current having the first current level. When in the standby state, the current source404is inactive and thus the current IB3 is not generated, and the total current is equal to the current IB1 having the second current level.

During the standby state, the NMOS device402at node BN1 is configured to generate the bias voltage VGB from the source of the NMOS device402. Accordingly, the NMOS device402is configured to, in operation, conduct the current IB1 of the current source400and thus the NMOS device402is configured to adjust the bias voltage level of the bias voltage VGB such that the conducted current matches the current IB1 generated by the current source400. The NMOS device402is thereby configured to adjust the bias voltage level of the bias voltage VGB in accordance with a change in the bias voltage level of the bias voltage VG in order to ensure that the current IB1 is conducted as generated by the current source400. The NMOS device406is inactive in the standby state and thus does not help regulate the bias voltage VG or contribute significantly to power consumption.

In the active state, the NMOS device406is activated. The NMOS device402at node BN1 and the NMOS device406at node BN3 are configured to collectively generate the bias voltage VGB from the source of the NMOS device402and the source of the NMOS device406. Accordingly, the NMOS device402and the NMOS device406are configured to, in operation, conduct a current that is equal to a sum of the current IB1 of the current source400and the current IB3 of the current source404. The NMOS device402and the NMOS device406are thereby configured to adjust the bias voltage level of the bias voltage VGB such that the conducted current matches the current IB1+IB3 generated by the respective current sources400and404. The NMOS devices402and406are thereby configured to adjust the bias voltage level of the bias voltage VGB in accordance with a change in the bias voltage level of the bias voltage VG in order to ensure that the current IB1+IB3 is conducted as generated by the current source400and the current source404. The local buffer144B including the NMOS device402and the NMOS device406is thereby configured to provide a dynamic current that delivers a charge that can quickly handle adjustments to the bias voltage VGB in the active state and operates at low current and power levels in the standby state.

FIG.5is a diagram of a memory circuit100C, in accordance with some embodiments.

Memory circuit100C is one embodiment of the memory circuit100. Components in memory circuit100C that are the same as the components in memory circuit100are labeled with the same component numbers inFIG.5as inFIGS.1A and1Band are not described again for the sake of brevity.

The memory circuit100C includes a bias voltage generator110C that includes a global control circuit139B and a local buffer144C. In this embodiment, only the buffer1is shown as the local buffer144C. In some embodiments, all of the local buffers144are identical to local buffer144C. In other embodiments, the other local buffers144have a different configuration than the local buffer144C, such as the local buffer144A above and/or the configurations explained above forFIGS.2and4. In still other embodiments, one or more of the other local buffers144are provided in the same manner as local buffer144C while one or more other of the other local buffers144are provided in a different configuration.

The local buffer144C includes a current source500and a PMOS device502coupled to the current source500in a source follower configuration. In this embodiment, a drain of the PMOS device502is configured to receive the power reference voltage, a gate of the PMOS device502is configured to receive the bias voltage VG from the output terminal OT of the operational amplifier143and a source of the PMOS device502is coupled to the node BN1. The node BN1 is coupled to the gate of the voltage clamp device120and to a cathode of the current source500. An anode of the current source500is configured to receive the power source voltage VDD. As such, the PMOS device502is configured to operate in the triode region. In this embodiment, the current source500is configured to generate the current IB1 at the second current level both in the standby state and in the active state. Thus, unlike the current source200inFIG.2, the current source500does not operate at two different current levels depending on whether the memory circuit100C is in the standby state or in the active state.

The local buffer144C also includes a current source504and a PMOS device506. The current source504and the PMOS device506are configured to be deactivated in the standby state and activated in the active state. The PMOS device506has a gate configured to receive the bias voltage VG. A drain of the PMOS device506is configured to receive the power reference voltage. A switch512is coupled between the power reference node and the drain of the PMOS device506. The switch512is configured to be open in the standby state and closed in active state. Accordingly, in the active state, the PMOS device506receives the power reference voltage at the drain of the PMOS device506. In the standby state, the PMOS device506does not receive the power reference voltage at the drain and thus is inactive. A source of the PMOS device506is coupled to the node BN3. The node BN3 is coupled to the node BN1 and to the gate of the voltage clamp device120. A node508is configured to receive the power supply voltage VDD. A switch510is coupled between the node508and an anode of the current source504. A cathode of the current source504is coupled to the node BN3. The source of the PMOS device506is also coupled to the node BN3. The switch510is configured to be open in the standby state and closed in the active state. Accordingly, the current source504is activated in the active state and deactivated in the standby state. When the current source504is activated, the current source504is configured to generate the current IB3 having the third current level. In some embodiments, the first current level discussed above with respect toFIG.2is at or is approximately equal to the second current level plus the third current level. As such, when the local buffer144C is in the active state during a read operation, the current source500and the current source504are configured to generate a total current having the first current level. When in the standby state, the current source504is inactive and thus the current IB3 is not generated, and the total current is equal to the current IB1 having the second current level.

During the standby state, the PMOS device502at node BN1 is configured to generate the bias voltage VGB from the source of the PMOS device502. Accordingly, the PMOS device402is configured to, in operation, conduct the current IB1 of the current source500and thus the PMOS device502is configured to adjust the bias voltage level of the bias voltage VGB such that the conducted current matches the current IB1 generated by the current source. Accordingly, the PMOS device502is configured to adjust the bias voltage level of the bias voltage VGB in accordance with a change in the bias voltage level of the bias voltage VG in order to ensure that the current IB1 is conducted as generated by the current source500. The PMOS device506is inactive in the standby state and thus does not help regulate the bias voltage VG or contribute significantly to power consumption.

In the active state, the PMOS device506is activated. The PMOS device502at node BN1 and the PMOS device506at node BN3 are configured to collectively generate the bias voltage VGB from the source of the PMOS device502and the source of the PMOS device506. Accordingly, the PMOS device502and the PMOS device506are configured to, in operation, conduct a current that is equal to a sum of the current IB1 of the current source500and the current IB3 of the current source504. The PMOS device502and the PMOS device506are thereby configured to adjust the bias voltage level of the bias voltage VGB such that the conducted current matches the current IB1+IB3 generated by the respective current sources500and504. The PMOS devices502and506are thereby configured to adjust the bias voltage level of the bias voltage VGB in accordance with a change in the bias voltage level of the bias voltage VG in order to ensure that the current IB1+IB3 is conducted as generated by the current source500and the current source504. The local buffer144C including the PMOS device502and the PMOS device506is thereby configured to provide a dynamic current that delivers a charge that can quickly handle adjustments to the bias voltage VGB in the active state and operates at low current and power levels in the standby state.

The global control circuit139B is one embodiment of the global control circuit139shown inFIG.1A. The global control circuit139B includes the operational amplifier143and the replica circuit145A discussed above with respect toFIGS.1A and2, and also includes a buffer141B.

The buffer141B includes a current source514and a PMOS device516coupled to the current source514in a source follower configuration. In this embodiment, a drain of the PMOS device516is coupled to the power reference node, a gate of the PMOS device516is configured to receive the bias voltage VG from the output terminal OT of the operational amplifier143, and a source of the PMOS device516is coupled to a node BN2. The node BN2 is coupled to the gate of the voltage clamp device120R in the replica circuit145A and to a cathode of the current source514. An anode of the current source514is configured to receive the power source voltage VDD. As such, the PMOS device516is configured to operate in the triode region. The current source514is configured to generate the current IB2. The PMOS device516at node BN2 is configured to generate the bias voltage VGB′ from the source of the PMOS device516. Accordingly, the PMOS device516is configured to, in operation, conduct the current IB2 of the current source514and thereby adjust the bias voltage level of the bias voltage VGB′ such that the conducted current matches the current IB2 generated by the current source514. The PMOS device516is thereby configured to adjust the bias voltage level of the bias voltage VGB′ in accordance with a change in the bias voltage level of the bias voltage VG in order to ensure that the current IB2 is conducted as generated by the current source514. An advantage of the buffer141B is that the PMOS device516draws very little current at the gate and presents a low impedance to the voltage clamp device120R. The buffer141B also maintains the feedback to generate the bias voltage VGB by the local buffer144C during the standby state, thereby significantly reducing the amount of power consumed by the memory circuit100C during the standby state compared to other approaches.

FIG.6is a diagram of a memory circuit600, in accordance with some embodiments.

The memory circuit600includes a reference stage602, a voltage sensing stage604, a gain stage606, a buffer608, voltage clamp devices610, and current paths612. As discussed below, the reference stage602, voltage sensing stage604, gain stage606, and buffer608collectively correspond to a bias voltage generator configured to generate the bias voltage VGB discussed above with respect toFIGS.1A-5.

Each of the current paths612includes a multiplexing switch613and a resistance-based memory device614. The multiplexing switch613is coupled in series between a corresponding one of the voltage clamp devices610and the resistance-based memory device614. Each of the multiplexing switches613is configured to be closed when the corresponding current path612is selected and open when the corresponding current path612is not selected. Each of the resistance-based memory devices614includes a selection transistor616coupled in series with a variable resistance device618and having a gate coupled to an input terminal (not shown), and is thereby configured to couple the resistance-based memory device614to a corresponding conduction line (not labeled) in response to an activation voltage. In some embodiments, each of variable resistance devices618includes an RRAM device, an MTJ device, a PCM device, or the like.

In this embodiment, each of the voltage clamp devices610is an NMOS device having a drain coupled to a sense amplifier (not shown), a source coupled to a corresponding one of the current paths612, and a gate coupled to a node NTS configured to have the bias voltage VGB. In operation, when a given selection transistor616is on and the selection transistor616is closed, the bias voltage VGB causes the voltage clamp device610to apply a drive voltage Vmtj to the corresponding current path612, thereby generating a read current Imtj.

The reference stage602is configured to generate a reference voltage VGB_ref. In this embodiment, the reference stage602includes a current source620, an NMOS device M1, a resistive device622, and a capacitive device626. The current source620is configured to receive the power source voltage VDD at an anode of the current source620, and a cathode of the current source620is coupled to a drain of the NMOS device M1. The current source620is configured to generate a current624having a current level Iref. The drain of the NMOS device M1 is coupled to a gate of the NMOS device M1. The resistive device622is coupled between a source of the NMOS device M1 and the power reference node. The capacitive device626is coupled between the gate of the NMOS device M1 and the power reference node. The resistive device622has a resistance of Rref configured to replicate a resistance of the current paths612in the manner discussed above with respect to replica resistive device RP1 andFIG.2. The NMOS device M1 has a channel size 1X such that a voltage Vgs (not labeled) of the NMOS device M1 is a function of the channel size 1X and the current level Iref.

The reference stage602is thereby configured to, in operation, generate the reference voltage VGB_ref having a voltage level equal to the voltage Vgs of the NMOS device M1 plus a voltage across the resistive device622, each generated based on the current level Iref. In some embodiments, the current level Iref corresponds to a predetermined activation current of the variable resistance devices618.

The voltage sensing stage604is configured to generate a voltage Vs on a node NRS responsive to the bias voltage VGB. The voltage sensing stage604includes an NMOS device M3 and a resistive device628. A drain and a gate of the NMOS device M3 are both coupled to the node NTS and are thereby coupled to one another and configured to receive the bias voltage VGB. A source of the NMOS device M3 is coupled to the node NRS. The resistive device628is coupled between the node NRS and the power reference node. The resistive device628has a resistance Rref/n and the NMOS device M3 has a channel size n*X, n being a positive number greater than or equal to one.

The NMOS device M3 and the resistive device628are thereby arranged as a voltage divider configured to, in operation, generate the voltage Vs on the node NRS by dividing the bias voltage VGB on the node NTS. The voltage Vs has a voltage level based on a ratio of a voltage Vgs (not labeled) of the NMOS device M3 and a voltage across the resistive device628. A value of the ratio is based on the channel size n*X and the resistance Rref/n and is thereby substantially constant for varying values of the number n. As the number n increases, a response time of the voltage sensing stage604decreases and a standby current increases.

In some embodiments, the number n has a value ranging from one to eight. In some embodiments, the number n has a value ranging from two to six, e.g., four. Other values/ranges of the number n are within the scope of the present disclosure.

The gain stage606is configured to amplify an offset between the reference voltage VGB_ref and the bias voltage VGB based on the voltage Vs received on a node NSS coupled to node NRS of the voltage sensing stage604. The gain stage606includes a current source630, an NMOS device M2, and a resistive device632. An anode of the current source630is configured to receive the power source voltage VDD and a cathode of the current source630is coupled to a node NDS. A drain of the NMOS device M2 is coupled to the node NDS, a source of the NMOS device M2 is coupled to the node NSS, and a gate of the NMOS device M2 is coupled to the gate of the NMOS device M1 of the reference stage602. The resistive device632is coupled between the node NSS and the power reference node.

The current source630is configured to generate a current634having a current level m*Iref, the resistive device632has a resistance Rref/m and the NMOS device M2 has a channel size m*X, m being a positive number greater than or equal to one.

The gain stage606is thereby arranged as a common gate amplifier configured to, in operation, generate a bias voltage Vb on the node NDS responsive to the reference voltage VGB_ref received at the gate of the NMOS device M2 and the voltage Vs received on the node NSS. A gain of the gain stage606is thereby configured to have a value that is substantially constant for varying values of the number m. As the number m increases, a response time of the gain stage606decreases and a standby current increases.

In some embodiments, the number m has a value ranging from one to eight. In some embodiments, the number m has a value ranging from two to six, e.g., four. Other values/ranges of the number m are within the scope of the present disclosure.

The buffer608is configured to generate the bias voltage VGB on the node NTS based on the bias voltage Vb received on the node NDS. In this embodiment, the buffer608includes a PMOS device Mp. The PMOS device Mp has a drain configured to receive the power source voltage VDD, a gate coupled to the node NDS, and a source coupled to the node NTS.

The buffer608is thereby arranged as a common source amplifier configured to, in operation, generate the bias voltage VGB on the node NTS having a voltage level controlled by the relative voltage levels of the reference voltage VGB_ref generated by the reference stage602and the bias voltage Vb generated by the gain stage606responsive to the voltage Vs generated by the voltage sensing stage604.

The memory circuit600thereby includes the reference stage602, the voltage sensing stage604, the gain stage606, and the buffer608having a feedback arrangement configured to generate the bias voltage VGB. A total current used to generate the bias voltage VGB is the sum of the current624generated by current source620, the current634generated by current source630, and the current Ivgb controlled by the PMOS device Mp.

In both the standby and active states, the current624has the predetermined current level Iref and the current634has the predetermined current level m*Iref. In the standby state, the current Ivgb has a current level controlled by the voltage level of the bias voltage VGB and the configuration of the PMOS device Mp and the resistive device628. In the active state, selection activity causes the current Ivgb to have one or more high transient current levels triggered by capacitive coupling to current paths612through voltage clamp devices610. Based on the feedback arrangement of memory circuit600, the PMOS device Mp is configured to supply the current Ivgb having a low current level in the standby state and having the one or more high current levels in the active state.

Compared to other approaches, memory circuit600is thereby capable of generating the bias voltage VGB using a decreased standby power and having an increased amount of charge able to be delivered dynamically such that power consumption is reduced and memory circuit speed is increased.

FIG.7is a flowchart of a method700of performing a read operation, in accordance with some embodiments. Method700is usable with a memory circuit, e.g., memory circuit100discussed above with respect toFIGS.1A and1B, memory circuit100A discussed above with respect toFIG.2, memory circuit100B discussed above with respect toFIG.4, memory circuit100C discussed above with respect toFIG.5, or memory circuit600discussed above with respect toFIG.6.

The sequence in which the operations of method700are depicted inFIG.7is for illustration only; the operations of method700are capable of being executed in sequences that differ from that depicted inFIG.7. In some embodiments, operations in addition to those depicted inFIG.7are performed before, between, during, and/or after the operations depicted inFIG.7. In some embodiments, the operations of method700are a subset of operations of a method of operating a memory macro.

At operation702, a first bias voltage is generated based on a reference voltage and a feedback voltage. In some embodiments, generating the first bias voltage based on the reference voltage and the feedback voltage includes generating the bias voltage VG based on the reference voltage Vref and the drive voltage VRBL as discussed above with respect toFIGS.1A,2,4, and5.

In some embodiments, generating the first bias voltage based on the feedback voltage includes using a first voltage clamp device to generate the feedback voltage based on the first bias voltage. In some embodiments, using the first voltage clamp device to generate the feedback voltage based on the first bias voltage includes using the voltage clamp device120R to generate the drive voltage VRBL based on the bias voltage VG as discussed above with respect toFIGS.2,4, and5.

In some embodiments, using the first voltage clamp device to generate the feedback voltage includes applying the feedback voltage to a replica circuit. In some embodiments, applying the feedback voltage to the replica circuit includes applying the drive voltage VRBL to the replica circuit145A as discussed above with respect toFIGS.2,4, and5.

In some embodiments, using the first voltage clamp device to generate the feedback voltage based on the first bias voltage includes using a first buffer to generate a second bias voltage received by the first voltage clamp device. In some embodiments, using the first buffer to generate the second bias voltage includes using buffer141,141A, or141B to generate the bias voltage VGB′ as discussed above with respect toFIGS.1A,2,4, and5.

In some embodiments, generating the first bias voltage based on the reference voltage and the feedback voltage includes generating the bias voltage Vb based on the reference voltage VGB_ref and the voltage Vs as discussed above with respect toFIG.6.

In some embodiments, generating the first bias voltage based on the reference voltage and the feedback voltage includes generating the reference voltage based on a reference current. In some embodiments, generating the reference voltage based on the reference current includes generating the reference voltage VGB_ref based on the reference current Iref as discussed above with respect toFIG.6.

In some embodiments, generating the reference voltage based on the reference current includes conducting the reference current with a replica resistive device. In some embodiments, conducting the reference current with the replica resistive device includes conducting the reference current Iref with resistive device622as discussed above with respect toFIG.6.

At operation704, a first buffer is used to generate a second bias voltage from the first bias voltage. In some embodiments, generating the second bias voltage includes generating the bias voltage VGB as discussed above with respect toFIGS.1A-6.

In some embodiments, using the first buffer to generate the second bias voltage includes using a local buffer. In some embodiment, the local buffer is one local buffer of a plurality of local buffers, the second bias voltage is one second bias voltage of a plurality of second bias voltages, and using the first buffer to generate the second bias voltage includes using the plurality of local buffers to generate the plurality of second bias voltages.

In some embodiments, using the first buffer to generate the second bias voltage includes using one or more of the buffers144,144A,144B, and/or144C to generate one or more instances of the bias voltage VGB as discussed above with respect toFIGS.1A,2,4, and5.

In some embodiments, using the first buffer to generate the second bias voltage from the first bias voltage includes using a buffer included in the feedback configuration. In some embodiments, using the first buffer to generate the second bias voltage from the first bias voltage includes using the buffer608to generate the bias voltage VGB from the voltage Vs received by the gain stage606and used to generate the voltage Vb as discussed above with respect toFIG.6.

At operation706, a first drive voltage is generated with a local voltage clamp device based on the second bias voltage. In some embodiments, generating the first drive voltage with the local voltage clamp device based on the second bias voltage includes generating the drive voltage VD with the voltage clamp device120based on the bias voltage VGB as discussed above with respect toFIGS.1A-2,4, and5.

In some embodiments, generating the first drive voltage with the local voltage clamp device based on the second bias voltage includes generating the drive voltage Vmtj with the voltage clamp device610based on the bias voltage VGB as discussed above with respect toFIG.6.

At operation708, the first drive voltage is applied to a current path including a resistance-based memory device. In some embodiments, applying the first drive voltage to the current path including the resistance-based memory device includes the current path including an RRAM device or an MTJ device.

In some embodiments, applying the first drive voltage to the current path including the resistance-based memory device includes applying the drive voltage VD to the current path111including the resistance-based memory device150as discussed above with respect toFIGS.1A-2,4, and5.

In some embodiments, applying the first drive voltage to the current path including the resistance-based memory device includes applying the drive voltage Vmtj to the current path612including the resistance-based memory device614as discussed above with respect toFIG.6.

By executing some or all of the operations of method700, a bias voltage is provided to a voltage clamp device based on a feedback configuration of a memory circuit, thereby realizing the benefits discussed above with respect to memory circuits100,100A,100B,100C, and600.

In some embodiments, a memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage, and a plurality of voltage clamp devices coupled to the plurality of second buffers, wherein each voltage clamp device of the plurality of voltage clamp devices is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages. In some embodiments, the first buffer is configured to generate a third bias voltage based on the first bias voltage, and the bias voltage generator includes another voltage clamp device coupled to a replica path segment and configured to generate a feedback voltage based on the third bias voltage and an operational amplifier including an output terminal configured to output the first bias voltage based on the feedback voltage and the reference voltage. In some embodiments, the bias voltage generator includes a capacitive device coupled between the output terminal and a power reference node. In some embodiments, each second buffer of the plurality of second buffers includes a first NMOS device, a first node, and a first current source coupled in series between a power source node and a power reference node, each first NMOS device includes a gate coupled to the first buffer and is thereby configured to receive the first bias voltage, and each voltage clamp of the plurality of voltage clamps includes a control terminal coupled to the first node of a corresponding second buffer of the plurality of second buffers. In some embodiments, each first current source of a corresponding second buffer of the plurality of second buffers is configured to generate a first current having first and second current levels, and the first current level has a magnitude higher than a magnitude of the second current level. In some embodiments, the first buffer includes a second NMOS device, a second node, and a second current source coupled in series between the power source node and the power reference node, and the second current source is configured to generate a second current having a current level approximately equal to the second current level of the first current. In some embodiments, each resistance-based memory device of the plurality of resistance-based memory devices includes an RRAM device.

In some embodiments, a memory circuit includes a bias voltage generator including an operational amplifier and a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage, and a plurality of voltage clamp devices coupled to the plurality of second buffers, wherein each second buffer of the plurality of second buffers includes a first parallel arrangement of a first current source and a second current source in series with a first switch, and each voltage clamp device of the plurality of voltage clamp devices is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages. In some embodiments, the first buffer is configured to generate a third bias voltage based on the first bias voltage, the bias voltage generator includes a voltage clamp device coupled to a replica path segment and configured to generate a feedback voltage based on the third bias voltage, and the operational amplifier includes an output terminal configured to output the first bias voltage based on the feedback voltage and the reference voltage. In some embodiments, for each second buffer of the plurality of second buffers, the first parallel arrangement is coupled between a node and a power reference node, the second buffer includes a second parallel arrangement of a first NMOS device and a second NMOS device in series with a second switch, the second parallel arrangement is coupled between a power source node and the node, each of the first and second NMOS devices includes a gate coupled to the output terminal, and each voltage clamp of the plurality of voltage clamps includes a control terminal coupled to the node of a corresponding second buffer of the plurality of second buffers. In some embodiments, the first buffer includes a third NMOS device and a third current source coupled between the power source node and the power reference node, and the third current source and each first current source of each second buffer of the plurality of second buffers are configured to generate respective third and first currents having a same first current level. In some embodiments, each second current source of each second buffer of the plurality of second buffers is configured to generate a second current having a second current level higher in magnitude than the first current level. In some embodiments, for each second buffer of the plurality of second buffers, the first parallel arrangement is coupled between a power source node and a node, the second buffer includes a second parallel arrangement of a first PMOS device and a second PMOS device in series with a second switch, the second parallel arrangement is coupled between the node and a power reference node, each of the first and second PMOS devices includes a gate coupled to the output terminal, and each voltage clamp of the plurality of voltage clamps includes a control terminal coupled to the node of a corresponding second buffer of the plurality of second buffers. In some embodiments, the first buffer includes a third current source and a third PMOS device coupled between the power source node and the power reference node, and the third current source and each first current source of each second buffer of the plurality of second buffers are configured to generate currents having a same current level. In some embodiments, each second current source of each second buffer of the plurality of second buffers is configured to generate a second current having a second current level higher in magnitude than the first current level.

In some embodiments, a method of operating a memory circuit includes using a first buffer to generate a first bias voltage based on a reference voltage, using a plurality of second buffers to generate a plurality of second bias voltages based on the first bias voltage, and using each voltage clamp device of a plurality of voltage clamp devices to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on a corresponding second bias voltage of the plurality of second bias voltages. In some embodiments, using the first buffer to generate the first bias voltage includes using the first buffer to generate a third bias voltage based on the first bias voltage, using another voltage clamp device coupled to a replica path segment to generate a feedback voltage based on the third bias voltage, receiving the reference and feedback voltages at input terminals of an operational amplifier, and outputting the first bias voltage at an output terminal of the operational amplifier. In some embodiments, using the plurality of second buffers to generate the plurality of second bias voltages based on the first bias voltage includes, for each second buffer of the plurality of second buffers, receiving the first bias voltage at a gate of first transistor coupled in series with a first current source, and generating the corresponding second bias voltage at a node between the first transistor and the first current source. In some embodiments, using the plurality of second buffers to generate the plurality of second bias voltages based on the first bias voltage includes, for each second buffer of the plurality of second buffers, receiving the first bias voltage at a gate of second transistor coupled in series with the node and a second current source. In some embodiments, applying the drive voltage to the corresponding resistance-based memory device of the plurality of resistance-based memory devices includes applying the drive voltage to an RRAM device.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.