Patent ID: 12249991

DETAILED DESCRIPTION

FIG.1illustrates a near field communication device DIS. The near field communication device DIS comprises a phase-locked loop PLL. The phase-locked loop PLL includes an oscillator circuit OC configured to provide a clock signal having a desired frequency.

The near field communication device DIS is configured to receive a first carrier signal CLK_REF having a frequency of 13.56 MHz. This frequency is a reference frequency to which the device DIS aims to synchronize using the phase-locked loop PLL, when communicating from said device to the reader. This first carrier signal CLK_REF is extracted from an electromagnetic field transmitted by the reader and received by said antenna. The extraction of the first carrier signal CLK_REF is performed by a carrier signal extraction circuit (not represented) well known to the skilled person.

The phase-locked loop PLL includes a clock generator circuit CGH including the oscillator OC controlled by a digital word. The oscillator circuit OC is supplied with a low-dropout regulator REG.

The oscillator circuit OC is configured to generate a signal having a frequency which is a multiple of a desired frequency (that is synchronous with the reference frequency signal, for example 13.56 MHz) of an output signal CLK_TX. For example, the oscillator circuit OC may be configured to generate a frequency in the order of 868 MHz (64*13.56 MHz).

The phase-locked loop further includes a divider-counter CNTD for counting a number of rising edges of the signal generated by the oscillator circuit OC. The divider-counter CNTD is configured to divide the frequency of the signal generated by the oscillator circuit OC so as to provide the output signal CLK_TX at the desired frequency via the output O1.

The digital output O2of the counter-divider CNTD is connected to an inverting input of a comparator CMP. The comparator CMP also includes an input receiving an output from an accumulator ACC. The accumulator ACC has an input receiving a value equal to the value multiplying the desired frequency of the oscillator circuit OC, for example sixty-four. The accumulator ACC also has an input connected to its output. The accumulator ACC takes the reference frequency signal CLK_REF as its clock. The accumulator ACC thus makes it possible to obtain a value equal to the reference phase multiplied by sixty-four.

The output of the comparator CMP corresponds to an error between the phase of the signal generated by the oscillator circuit OC (equal to the frequency of the signal at the output of the phase-locked loop multiplied by sixty-four) and the reference phase multiplied by sixty-four.

The output of the comparator CMP is connected to a loop filter PLL_f configured to generate the digital word to control the clock generator circuit.

FIG.2illustrates a clock generator circuit CGH. The clock generator circuit CGH is supplied with a supply source ALIM, especially a battery, of the near field communication device DIS. The supply source ALIM is configured to generate a voltage VBAT. More particularly, the near field communication device DIS includes a low-dropout regulator REG.

The regulator REG is configured to adapt the voltage VBAT provided by the supply source ALIM in order to obtain a voltage adapted to supply the clock generator circuit CGH. For example, the regulator REG is configured to receive the voltage VBAT, which may vary between 2.6 Volts (V) and 5.5V, and to provide a voltage V1at 2.4V to the clock generator circuit CGH.

The regulator REG includes a transistor P0, for example of the PMOS type (that is a P-type metal-oxide-semiconductor field effect transistor). Transistor P0has a source connected to the supply source ALIM, a drain connected to a supply input of the clock generator circuit CGH, and a gate controlled by an operational amplifier AMP.

The operational amplifier AMP has an input, for example a non-inverting input, configured to receive a reference voltage VREF corresponding to the voltage to be applied to the input of the clock generator circuit CGH. This reference voltage VREF can be obtained by a reference voltage generation circuit. The reference voltage generation circuit may be a bandgap voltage reference circuit, well known to the skilled person.

The operational amplifier AMP also has an input, for example an inverting input, connected to the drain of transistor P0.

The operational amplifier has an output connected to the gate of transistor P0.

The operational amplifier AMP is thus configured to control transistor P0according to a comparison between the supply voltage V1of the clock generator circuit CGH and the reference voltage VREF so as to obtain a supply voltage V1of the clock generator circuit equal to the reference voltage VREF.

The clock generator circuit CGH includes a plurality of MOS transistors (that is a field effect transistor with a metal-oxide-semiconductor structure). These MOS transistors have their gates made in varying thicknesses of oxide, referred to as GO1and GO2in the following. The difference between the thicknesses of the gate oxides makes it possible to make high-voltage MOS transistors and low-voltage MOS transistors (relatively to each other). The difference in gate oxide thickness between the MOS transistors allows a threshold voltage Vt of these MOS transistors to be changed so as to also change their gate-source voltage VGS. As discussed below, the gate oxide of the transistor GO2can be about three times greater the gate thickness of the transistor GO1.

In the illustrated embodiment, the MOS transistors GO1at 1.2V have a gate oxide thickness Tox in the order of 17 Å (ångström), and the MOS transistors GO2at 2.4V have a gate thickness Tox in the order of 50 Å. In this embodiment, the MOS transistors GO2have a gate oxide thickness that is about three times greater than the gate thickness of the MOS transistors GO1.

The clock generator circuit CGH includes the oscillator circuit OC and a bias circuit BC for controlling the oscillator circuit OC from a digital word DCTRL.

The oscillator circuit OC includes an odd number of inverter circuits INV arranged in a closed loop. Each inverter circuit INV has a supply input configured to receive a voltage VDDint.FIG.3illustrates an example of an inverter circuit INV. The inverter circuit includes a PMOS type transistor PO1and an NMOS type transistor NO1(that is field effect transistor with an N-type metal-oxide-semiconductor structure). Transistor PO1has a source configured to receive the voltage VDDint, a drain connected to an output OG1of the inverter circuit INV, and a gate connected to an input IG1of the inverter circuit INV. transistor NO1has a source connected to a cold point, especially to a ground GND, a drain connected to the output of the inverter circuit, and a gate connected to the input of the inverter circuit INV. Transistors PO1and NO1are of the GO2type at 2.4V.

The output OG1of each INV inverter circuit is connected to the input IG1of an inverter circuit INV placed downstream in the closed loop of the oscillator circuit OC.

The oscillator circuit OC is configured to generate an oscillating signal whose frequency depends on the voltage VDDint applied to the supply inputs of the inverter circuits INV.

The supply input of each inverter circuit INV is connected to the supply input of the frequency generator circuit CGH via a transistor P1, for example of the PMOS type.

Transistor P1thus has a source connected to the supply input of the clock generator circuit CGH so as to receive the voltage V1, and a drain connected to the oscillator circuit OC. Transistor P1also has a gate connected to the bias circuit. Transistor P1is of the GO2type at 2.4V.

The bias circuit BC controls transistor P1in order obtain the voltage VDDint as a function of the value of a digital word DCTRL.

In particular, the bias circuit BC comprises an input configured to receive a digital word DCTRL. The digital word DCTRL is provided by the phase-locked loop.

As illustrated inFIG.4, the bias circuit BC includes a current source SC.

The bias circuit BC also includes a programmable current mirror MC configured to receive the current provided by the current source SC, and to generate as an output a current I whose ratio to the current of the current source SC is programmable. In particular, the current mirror MC includes a transistor N1, for example of the NMOS type, and a programmable transistor N2, for example of the NMOS type. Transistor N1has a drain connected to the current source SC, a source connected to a cold point, especially to the ground GND, and a gate connected to the current source SC and to a gate of the programmable transistor N2.

The programmable transistor N2has a source connected to a cold spot, especially to the ground GND, and a drain for generating the current at the output of the current mirror.

The transistor N2is programmable as a function of the digital word received as an input of the bias circuit. For this purpose, the programmable transistor N2can be formed by a plurality of transistors in parallel, each transistor having a gate that can be connected via a switch either to the gate of transistor N1or to a cold point, especially to the ground GND.

The current generated by the current source SC is defined in such a way as to bias transistor N1correctly for all variations in the process, voltage, and temperature (“PVT”).

Transistors N1and N2are of the GO1type at 1.2V.

The bias circuit BC also includes a transistor N3, for example of the NMOS type. Transistor N3has a source connected to a cold point, especially to the ground GND, a drain, and a gate connected to its drain. Transistor N3is a GO1type transistor at 1.2V.

The transistor N3has dimensions (width and length) adapted so that the current range does not saturate transistor N3in any variation of process, voltage and temperature.

The bias circuit BC also includes a transistor N4, for example of the NMOS type. Transistor N4has a source connected to the drain and the gate of transistor N3, a drain, and a gate connected to its drain.

The bias circuit BC further includes a cascode transistor N5, for example of the NMOS type. The cascode transistor N5has a source connected to the drain of the programmable transistor N2, a drain and a gate connected to the gate and the drain of transistor N4.

Transistors N4and N5are of the GO2type at 2.4V. In addition, transistors N4and N5are identical to within one ratio. Thus, transistors N4and N5have the same gate-source voltage VGS.

Transistors N4and N5are automatically biased to copy the gate-source voltage VGS of transistor N3to the drain-source voltage VDS of transistor N2. This reduces or even avoids saturation of transistor N2.

The bias circuit BC also includes a transistor P2, for example of the PMOS type. Transistor P2has a source connected to the supply input of the clock generator circuit CGH so as to apply the voltage V1thereto. Transistor P2also has a drain connected to the drain of the cascode transistor N5, and a gate connected to the drain of transistor P2and the drain of the cascode transistor N5.

The bias circuit BC also includes a transistor P3, for example of the PMOS type. Transistor P3has a source connected to the supply input of the clock generator circuit CGH so as to apply the voltage V1thereto. Transistor P3also has a drain connected to the drain of transistor N4, and a gate connected to the gate of transistor P2, the drain of transistor P2and the drain of the cascode transistor N5.

Transistors P2, P3are of the GO2type at 2.4V.

The gates of transistors P2and P3are also connected to the gate of transistor P1. In particular, transistors P2and P3can be connected to the gate of transistor P1via a filter circuit. The filter circuit FT may comprise a variable resistor R1and a capacitor C1. Variable resistor R1then has a first terminal connected to the gates of transistors P2and P3and a second terminal connected to the gate of transistor P1. Capacitor C1has a first terminal connected to the supply input of the clock generator circuit and a second terminal connected to the second terminal of resistor R1and to the gate of transistor P1.

The bias circuit BC provides robust control of the oscillator circuit OC by means of the self-regulating cascode transistor N5.

The use of a current mirror including GO1type low-voltage transistors N1and N2allows proper operation of the clock generator circuit CGH over a sufficiently large supply voltage range, for example between 2 Volts and 2.7 Volts. This reduces the minimum voltage VBAT for proper operation of the clock generator circuit.

The use of GO2type transistors for the oscillator circuit OC allows the clock generator circuit CGH to operate over a wide frequency range in a more robust manner.

Thus, the clock generator circuit CGH can generate a reliable clock in a phase-locked loop PLL. A same phase-locked loop PLL can be used to operate the near field communication device DIS in reader mode or in card emulator mode.