Patent ID: 12237300

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.

The terms “over”, “to”, “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.

The term “package” generally refers to a self-contained carrier of one or more dice, where the dice are attached to the package substrate, and may be encapsulated for protection, with integrated or wire-bonded interconnects between the dice and leads, pins or bumps located on the external portions of the package substrate. The package may contain a single die, or multiple dice, providing a specific function. The package is usually mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components, forming a larger circuit.

Here, the term “cored” generally refers to a substrate of an integrated circuit package built upon a board, card or wafer comprising a non-flexible stiff material. Typically, a small printed circuit board is used as a core, upon which integrated circuit device and discrete passive components may be soldered. Typically, the core has vias extending from one side to the other, allowing circuitry on one side of the core to be coupled directly to circuitry on the opposite side of the core. The core may also serve as a platform for building up layers of conductors and dielectric materials.

Here, the term “coreless” generally refers to a substrate of an integrated circuit package having no core. The lack of a core allows for higher-density package architectures, as the through-vias have relatively large dimensions and pitch compared to high-density interconnects.

Here, the term “land side”, if used herein, generally refers to the side of the substrate of the integrated circuit package closest to the plane of attachment to a printed circuit board, motherboard, or other package. This is in contrast to the term “die side”, which is the side of the substrate of the integrated circuit package to which the die or dice are attached.

Here, the term “dielectric” generally refers to any number of non-electrically conductive materials that make up the structure of a package substrate. For purposes of this disclosure, dielectric material may be incorporated into an integrated circuit package as layers of laminate film or as a resin molded over integrated circuit dice mounted on the substrate.

Here, the term “metallization” generally refers to metal layers formed over and through the dielectric material of the package substrate. The metal layers are generally patterned to form metal structures such as traces and bond pads. The metallization of a package substrate may be confined to a single layer or in multiple layers separated by layers of dielectric.

Here, the term “bond pad” generally refers to metallization structures that terminate integrated traces and vias in integrated circuit packages and dies. The term “solder pad” may be occasionally substituted for “bond pad” and carries the same meaning.

Here, the term “solder bump” generally refers to a solder layer formed on a bond pad. The solder layer typically has a round shape, hence the term “solder bump”.

Here, the term “printed circuit board” generally refers to a planar platform comprising dielectric and metallization structures. The substrate mechanically supports and electrically couples one or more IC dies on a single platform, with encapsulation of the one or more IC dies by a moldable dielectric material. The substrate generally comprises solder bumps as bonding interconnects on both sides. One side of the substrate, generally referred to as the “die side”, comprises solder bumps for chip or die bonding. The opposite side of the substrate, generally referred to as the “land side”, comprises solder bumps for bonding the package to a printed circuit board.

Here, the term “assembly” generally refers to a grouping of parts into a single functional unit. The parts may be separate and are mechanically assembled into a functional unit, where the parts may be removable. In another instance, the parts may be permanently bonded together. In some instances, the parts are integrated together.

Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.

The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, magnetic or fluidic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.

The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The vertical orientation is in the z-direction and it is understood that recitations of “top”, “bottom”, “above” and “below” refer to relative positions in the z-dimension with the usual meaning. However, it is understood that embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.

The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

Views labeled “cross-sectional”, “profile” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.

As will be understood to those skilled in the art, integrated circuit assemblies may contain various mold, fill, and/or underfill materials. As these integrated circuit assemblies become ever smaller, it becomes challenging to prevent voids from forming within these materials, which may affect the reliability of the integrated circuit assemblies. Since integrated circuit assemblies are generally formed by electrically attaching integrated circuit dice on electronic substrates, the embodiments of the present description relate to injecting the mold, fill, and/or underfill materials through openings formed in the electronic substrate to fill voids that may form and/or to prevent the formation of the voids altogether.

FIG.1illustrates an integrated circuit assembly100having at least one integrated circuit die (illustrated as at least two first level integrated circuit dice1201attached to an electronic substrate110and at least one second level integrated circuit die1202attached to the at least two first level integrated circuit dice1201, according to an embodiment of the present description.

The electronic substrate110may be any appropriate device, including, but not limited to, a passive substrate (such as a package substrate or interposer, a printed circuit board, and the like) or a combination of an active device (not shown), such as, a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, combinations thereof, stacks thereof, or the like, embedded in the passive electronic substrate.

The electronic substrate110may comprise a plurality of dielectric material layers (not shown), which may include build-up films and/or solder resist layers, and may be composed of an appropriate dielectric material, including, but not limited to, bismaleimide triazine resin, fire retardant grade4material, polyimide material, silica filled epoxy material, glass reinforced epoxy material, and the like, as well as low-k and ultra low-k dielectrics (dielectric constants less than about 3.6), including, but not limited to, carbon doped dielectrics, fluorine doped dielectrics, porous dielectrics, organic polymeric dielectrics, and the like. The electronic substrate110may further include conductive routes118or “metallization” (shown in dashed lines) extending through the electronic substrate110. The bond pads116on the first surface112of the electronic substrate110may be in electrical contact with the conductive routes118, and the conductive routes118may extend through the electronic substrate110and be electrically connected to external components (not shown).

As will be understood to those skilled in the art, the conductive routes118may be a combination of conductive traces (not shown) and conductive vias (not shown) extending through the plurality of dielectric material layers (not shown). These conductive traces and conductive vias are well known in the art and are not shown inFIG.1for purposes of clarity. The conductive traces and the conductive vias may be made of any appropriate conductive material, including but not limited to, metals, such as copper, silver, nickel, gold, aluminum, alloys thereof, and the like. As will be understood to those skilled in the art, the electronic substrate110may be a cored substrate or a coreless substrate.

The integrated circuit dice1201,1202may be any appropriate active devices, including, but not limited to, microprocessors, chipsets, graphics devices, wireless devices, memory devices, application specific integrated circuits, or the like, an may be any appropriate passive device, including, but not limited to capacitors, resistors, inductors, and the like.

Each of the integrated circuit dice1201,1202may include a first surface122, an opposing second surface124, and at least one side126extending between the first surface122and the second surface124. Each of the integrated circuit dice1201,1202may further include at least one bond pad128on the first surfaces122thereof. As illustrated, the second surfaces124of the at least two first level integrated circuit dice1201may be attached to the first surface112of the electronic substrate110, and the second surface124of the second level integrated circuit die1202. It is understood that the second level integrated circuit die1202is positioned to avoid interference with the bond pads128on the first level integrated circuit dice1201. In an embodiment of the present description shown inFIG.1, the first level integrated circuit dice1201and the second level integrated circuit die1202may be electrically attached to the electronic substrate110through at least one bond wire130extending between the bond pads128of the first level integrated circuit dice1201and the bond pads116of the electronic substrate110and between the bond pads128of the second level integrated circuit die1202and the bond pads116of the electronic substrate110, respectively. Additionally, the first level integrated circuit dice1201and the second level integrated circuit die1202may be electrically attached to one another through at least one bond wire130extending between the bond pads128of the first level integrated circuit dice1201and the bond pads128of the second level integrated circuit dice1202.

An electrically-insulating mold material140, such as an epoxy material, may be disposed over the integrated circuit dice1201,1202and the electronic substrate110, and may substantially surround each bond wire130. The mold material140may provide structural integrity and may prevent contamination, as will be understood to those skilled in the art.

As shown inFIG.1, the stack configuration of the first level integrated circuit dice1201and the second level integrated circuit die1202can result in at least one void150forming in areas where the mold material140does not flow, such as tunnels and blind cavities. In one embodiment shown inFIG.1, the at least one void150may be defined by the first surface112of the electronic substrate110, the sides126of the first level integrated circuit dice1201, and the second surface124of the second level integrated circuit die1202. The mold material140itself may additionally define the at least one void150, as will be understood.

As shown inFIG.1, the electronic substrate110may include at least one inlet opening170extending from the first surface112to an opposing second surface114of the electronic substrate110. The inlet opening170may be used to introduce a fill material160, such as an epoxy material, into the at least one void150, and, thus, at least a portion of the fill material160will extend into the inlet opening170. In one embodiment, the fill material160may be dispensed into the void150as a viscous liquid and then hardened with a curing process. It may be advantageous to form at least one vent opening180extending from the first surface112to the second surface114of the electronic substrate110, such that the assembly can be flipped over and the fill material160dispensed into the void150, such that ambient atmosphere may be vented out of the vent opening180as the fill material160fills the void150. In one embodiment of the present description, the fill material160may be substantially the same material as the mold material140. In an embodiment of the present description, the fill material160may be injected under positive pressure into the inlet opening170from the second surface114of the electronic substrate110. In an embodiment of the present description, the at least one inlet opening170and/or the at least one vent opening180may be made by any known process, including, but not limited to, laser drilling, ion ablation, etching, and the like. In a specific embodiment, the at least one inlet opening170and/or the at least one vent opening180may be formed as a plated through hole, as known in the art.

As shown inFIG.2, the integrated circuit assembly100may comprise two first level integrated circuit dice1201, one second level integrated circuit die1202, one inlet opening170, and four vent openings180. It is noted that the mold material140(seeFIG.1) is not shown and the second level integrated circuit die1202and associated components are shown in shadow for clarity.

As shown inFIG.3, the integrated circuit assembly100may have any appropriate number of integrated circuit dice. In one embodiment, the integrated circuit assembly100may comprise four first level integrated circuit dice1201, one second level integrated circuit die1202, one inlet opening170, and four vent openings180. It is noted that the mold material140(seeFIG.1), the bond wires130, and associated bond pads are not shown for clarity.

AlthoughFIG.1illustrates two levels of integrated circuit dice, the embodiments of the present description are not so limited and can include any number of levels. In one example, an embodiment of the present description has four levels of integrated circuit dice, i.e. first level dice1201, second level dice1202, third level dice1203, and fourth level die1204, as shown inFIG.4.

FIG.5is a flow chart of a process200of fabricating an integrated circuit assembly. As set forth in block210, an electronic substrate having a first surface and an opposing second surface may be formed. An opening may be formed in the electronic substrate, wherein the opening extends from the first surface to the second surface of the electronic substrate, as set forth in block220. As set forth in block230, at least two first level integrated circuit dice may be formed having a first surface and a second surface. The second surface of each of the at least two first level integrated circuit dice may be attached to the first surface of the electronic substrate, as set forth in block240. As set forth in block250, at least one second level integrated circuit die may be formed having a first surface and a second surface. The second surface of the at least one second level integrated circuit die may be attached to the first surface of at least one of the first level integrated circuit dice, wherein at least one void is defined by the electronic substrate, the at least two first level integrated circuit dice, and the second level integrated circuit die, as set forth in block260. As set forth in block270, the electronic substrate may be oriented with the second surface gravitationally higher than the first surface thereof. A fill material may be dispensed from the second surface of the electronic substrate through the opening and into the at least one void, as set forth in block280. As set forth in block290, the fill material may be cured.

FIG.6illustrates a further embodiment of the present description comprising an integrated circuit assembly300having at least one integrated circuit device310attached to the electronic substrate110in a configuration generally known as a flip-chip or controlled collapse chip connection (“C4”) configuration, according to an embodiment of the present description. The integrated circuit device310may be any appropriate active device, as described with regard to integrated circuit dice1201,1202ofFIG.1.

In an embodiment of the present description shown inFIG.6, the integrated circuit device310may be attached to the electronic substrate110with a plurality of device-to-substrate interconnects320. In one embodiment of the present description, the device-to-substrate interconnects320may extend between the bond pads116on the first surface112of the electronic substrate110and bond pads318on a first surface312of the integrated circuit device310.

In one embodiment, the device-to-substrate interconnects320may be solder balls formed from tin, lead/tin alloys (for example, 63% tin/37% lead solder), and high tin content alloys (e.g. 90% or more tin—such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys). The device-to-substrate interconnects320may be in electrical communication with integrated circuitry (not shown) within the integrated circuit device310.

An electrically-insulating underfill material330, such as an epoxy material, may be disposed between the integrated circuit device310and the electronic substrate110to substantially surround each device-to-substrate interconnect of the plurality of device-to-substrate interconnects320. The underfill material330may provide structural integrity and may prevent contamination, as will be understood to those skilled in the art. As discussed with regard toFIG.1, the electronic substrate110may include at least one inlet opening170extending from the first surface112to the second surface114of the electronic substrate110, as previously discussed. The inlet opening170is used to introduce the underfill material330between the integrated circuit device310and the electronic substrate110, and, thus, at least a portion of the underfill material330will extend into the inlet opening170. In one embodiment, the underfill material330may be dispensed between the first surface312of the integrated circuit device310and the first surface112of the electronic substrate110as a viscous liquid and then hardened with a curing process. In an embodiment of the present description, the underfill material330may be injected under positive pressure into the inlet opening170from the second surface114of the electronic substrate110, which reduces or eliminates capillary action as the driving force for the distribution of the underfill material330.

FIG.7illustrates a view along line7-7ofFIG.6. As shown, the inlet opening170may be substantially centrally located within a substantially symmetrical array of bond pads116of the electronic substrate110. However, it is understood that the inlet opening170may be located in any position to achieve the shortest flow time of the underfill material330, particularly when the bond pads116(and hence the device-to-substrate interconnects320(seeFIG.6)) have a non-symmetrical arrangement.

FIG.8illustrates an electronic or computing device400in accordance with one implementation of the present description. The computing device400may include a housing401having a board402disposed therein. The computing device400may include a number of integrated circuit components, including but not limited to a processor404, at least one communication chip406A,406B, volatile memory408(e.g., DRAM), non-volatile memory410(e.g., ROM), flash memory412, a graphics processor or CPU414, a digital signal processor (not shown), a crypto processor (not shown), a chipset416, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the integrated circuit components may be physically and electrically coupled to the board402. In some implementations, at least one of the integrated circuit components may be a part of the processor404.

The communication chip enables wireless communications for the transfer of data to and from the computing device. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In one embodiment, at least one of the integrated circuit components may include an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one inlet opening extending from the first surface to the second surface, at least one integrated circuit die attached to the electronic substrate; at least one void defined by the electronic substrate and the integrated circuit die; and a fill material within the at least one void, wherein a portion of the fill material extends into the opening in the electronic substrate.

In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.

It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated inFIGS.1-8. The subject matter may be applied to other integrated circuit devices and assembly applications, as well as any appropriate electronic application, as will be understood to those skilled in the art.

The following examples pertain to further embodiments and specifics in the examples may be used anywhere in one or more embodiments, wherein Example 1 is an integrated circuit assembly comprising an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one inlet opening extending from the first surface to the second surface, at least one integrated circuit die attached to the electronic substrate; at least one void defined by the electronic substrate and the integrated circuit die; and a fill material within the at least one void, wherein a portion of the fill material extends into the opening in the electronic substrate.

In Example 2, the subject matter of Example 1 can optionally include a mold material on the electronic substrate and the at least one of the integrated circuit dice.

In Example 3, the subject matter of Example 2 can optionally include the at least one void being further defined by the mold material.

In Example 4, the subject matter of any of Examples 1 to 3 can optionally include at least one vent opening extending from the first surface of the electronic substrate to the second surface of the electronic substrate.

In Example 5, the subject matter of any of Examples 1 to 4 can optionally include a portion of the fill material extending into the vent opening.

Example 6 is an electronic system, comprising an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one opening extending from the first surface to the second surface; at least two first level integrated circuit dice having a first surface and an opposing second surface, wherein the second surface of each at least two integrated first level integrated circuit attached to the electronic substrate; at least one second level integrated circuit die having a first surface and an opposing second surface, wherein the second surface of second level integrated circuit die is attached to the first surface of at least one of the first level integrated circuit dice; at least one void defined by the electronic substrate, the at least two first level integrated circuit dice, and the second level integrated circuit die; and a fill material within the at least one void, wherein a portion of the fill material extends into the inlet opening in the electronic substrate.

In Example 7, the subject matter of Example 6 can optionally include the electronic substrate further comprises at least one vent opening extending from the first surface of the electronic substrate to the second surface of the electronic substrate.

In Example 8, the subject matter of Example 7 can optionally include a portion of the fill material extending into the vent opening.

In Example 9, the subject matter of any of Examples 6 to 8 can optionally include a mold material on the electronic substrate, the at least two first level integrated circuit dice, and the second level integrated circuit die.

In Example 10, the subject matter of Example 9 can optionally include the at least one void being further defined by the mold material.

In Example 11, the subject matter of Example 9 can optionally include the fill material being substantially the same as the mold material.

In Example 12, the subject matter of any of Examples 6 to 11 can optionally include at least one of the at least two first level integrated circuit dice and the at least one second level integrated circuit die being electrically attached to the electronic substrate with at least one bond wire.

In Example 13, the subject matter of any of Examples 6 to 12 can optionally include at least one of the at least two first level integrated circuit dice being electrically attached to the at least one second level integrated circuit die with at least one bond wire.

Example 14 is a method of fabricating an integrated circuit assembly comprising forming an electronic substrate having a first surface and an opposing second surface; forming an opening in the electronic substrate, wherein the opening extends from the first surface of the electronic substrate to the second surface of the electronic substrate; forming at least two first level integrated circuit dice having a first surface and an opposing second surface; attaching the second surface of each at least two integrated first level integrated circuit to the first surface of the electronic substrate; forming at least one second level integrated circuit die having a first surface and an opposing second surface; attaching the second surface of the at least one second level integrated circuit die to the first surface of at least one of the first level integrated circuit dice, wherein at least one void is defined by the electronic substrate, the at least two first level integrated circuit dice, and the second level integrated circuit die; orienting the electronic substrate with the second surface gravitationally higher than the first surface thereof; dispensing a fill material from the second surface of the electronic substrate through the inlet opening and into the at least one void; and curing the fill material.

In Example 15, the subject matter of Example 14 can optionally include a portion of the fill material extending into the inlet opening.

In Example 16, the subject matter of any of Examples 14 and 15 can optionally include forming at least one vent opening extending from the first surface of the electronic substrate to the second surface of the electronic substrate.

In Example 17, the subject matter of Example 16 can optionally include a portion of the fill material extending into the at least one vent opening.

In Example 18, the subject matter of Example 14 to 17 can optionally include forming a mold material on the electronic substrate, the at least two first level integrated circuit dice, and the second level integrated circuit die.

In Example 19, the subject matter of Example 18 can optionally include the at least one void being further defined by the mold material.

In Example 20, the subject matter of any of Examples 18 to 19 can optionally include the fill material is substantially the same as the mold material.

In Example 21, the subject matter of any of Examples 14 to 21 can optionally include electrically attaching at least one of the at least two first level integrated circuit dice and the at least one second level integrated circuit die to the electronic substrate with at least one bond wire.

In Example 22, the subject matter of any of Examples 14 to 21 can optionally include electrically attaching at least one of the at least two first level integrated circuit dice to the at least one second level integrated circuit die with at least one bond wire.

Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.