Patent ID: 12261047

DETAILED DESCRIPTION

Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

As used in this specification and the appended claims, the term “substrate” refers to a surface, or portion of a surface, upon which a process acts. It will also be understood by those skilled in the art that reference to a substrate can also refer to only a portion of the substrate, unless the context clearly indicates otherwise. Additionally, reference to depositing on a substrate can mean both a bare substrate and a substrate with one or more films or features deposited or formed thereon.

A “substrate surface” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such underlayer as the context indicates. Thus for example, where a film/layer or partial film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

Embodiments of the present disclosure relate to methods of forming an electronic device with a method comprising a conformal and selective doping process. Some embodiments of this disclosure advantageously provide methods of conformally doping a semiconductor material. Some embodiments of this disclosure advantageously provide methods for doping semiconductor materials preferentially over oxide materials. Some embodiments of this disclosure advantageously provide methods of doping non-line of sight surfaces.

As used in this specification and the appended claims, the term “selectively depositing a film on one surface over another surface”, and the like, means that a first amount of the film is deposited on the first surface and a second amount of film is deposited on the second surface, where the second amount of film is less than the first amount of film, or no film is deposited on the second surface. The term “over” used in this regard does not imply a physical orientation of one surface on top of another surface, rather a relationship of the thermodynamic or kinetic properties of the chemical reaction with one surface relative to the other surface. For example, selectively depositing a cobalt film onto a copper surface over a dielectric surface means that the cobalt film deposits on the copper surface and less or no cobalt film deposits on the dielectric surface; or that the formation of the cobalt film on the copper surface is thermodynamically or kinetically favorable relative to the formation of a cobalt film on the dielectric surface.

Referring toFIG.1, some embodiments relate to a method100of forming an electronic device.FIG.1illustrates a cross-sectional view of an exemplary substrate for processing by the method100. The substrate10comprises a first surface20comprising a semiconductor material25and a second surface30comprising an oxide material35. In some embodiments, the semiconductor material25comprises or consists essentially of silicon.

In some embodiments, the semiconductor material25is a source/drain extension region of a transistor. In some embodiments, the electronic device comprises a3D NAND device comprising a plurality of alternating first surfaces20and second surfaces30.

As used in this specification and the appended claims, the term “consists essentially of”, and the like, means that the subject film or composition is greater than or equal to about 95%, 98%, 99% or 99.5% of the stated active material. For gaseous compositions (e.g., reactive gases) the term “consists essentially of” refers to the active component of the composition, not including diluent, carrier or inert gases.

In some embodiments, the method100begins by selectively depositing a substantially conformal dopant film40on the first surface20over the second surface30. As used herein, a film which is “substantially conformal” refers to a film where the thickness is about the same throughout (e.g., on the top, middle and bottom of sidewalls and on the bottom of the gap). A film which is substantially conformal varies in thickness by less than or equal to about 10%, 5%, 2%, 1% or 0.5%.

In some embodiments, the dopant film40has a thickness in the range of about 2 to about 10 monolayers.

In some embodiments, selectively depositing the conformal film40is performed using a non-line of sight deposition process. Accordingly, in some embodiments, the dopant film40deposits conformally on all exposed first surfaces regardless of their “visibility”. As shown inFIG.1, the underside of the diamond fins would typically be difficult to dope as these surfaces are not “visible” to line of sight processes.

In some embodiments, selectively depositing the dopant film40comprises a thermal decomposition process. In some embodiments, the thermal decomposition process comprises exposing the first surface and the second surface to a dopant precursor at a temperature in a range of about 600° C. to about 900° C. or in a range of about 700° C. to about 800° C.

In some embodiments, the dopant precursor is a boron precursor and the dopant film comprises boron. In some embodiments, the boron precursor comprises or consists essentially of one or more of borane (BH3), diborane (B2H6), triborane (B3H5, B3H7), tetraborane (B4H6, B4H10), pentaborane (B5H9, B5H11) or a cyclic triborane (B3H6) or a cyclic tetraborane (B4H8). Additional examples of suitable boron precursors include boron halides such as BCl3, or alkyl substituted boron compounds having the formula BHxR3−x, wherein each R is an independently selected C1-C6 alkyl group and x is 0, 1 or 2. Specific examples of alkyl substituted boron compounds include trimethylboron and triethylboron.

In some embodiments, the dopant precursor is a phosphorous precursor and the dopant film comprises phosphorous. In some embodiments, the phosphorous precursor comprises or consists essentially of phosphine (PH3). In some embodiments, the dopant precursor is an arsenic precursor and the dopant film comprises arsenic. In some embodiments, the arsenic precursor comprises or consists essentially of arsine (AsH3).

In some embodiments, the method100continues by annealing the electronic device to drive dopant atoms from the dopant film40into the semiconductor material25so that the semiconductor material25is conformally doped and there is substantially no dopant atoms driven into the oxide material35. As illustrated inFIG.1, the conformal doping of the semiconductor material25is shown by a bold line on the doped surfaces. As used herein, “substantially no dopant atoms” means that the subject material surface comprises fewer than 5%, 2%, 1%, or 0.5% dopant atoms.

In some embodiments, annealing the electronic device comprises one or more of a spike anneal, laser anneal, rapid thermal anneal, millisecond anneal or a combination thereof. In some embodiments, annealing occurs at a temperature in the range of about 1000° C. to about 1300° C. or in the range of about 1150° C. to about 1200° C.

In some embodiments, the dopant atoms are driven into the semiconductor material25to a depth greater than or equal to about 1 nm, greater than or equal to about 2 nm, or greater than or equal to about 5 nm. In some embodiments, the conformally doped semiconductor material has a dopant concentration greater than or equal to about 120atoms B/cm3, greater than or equal to about 220atoms B/cm3, or greater than or equal to about 520atoms B/cm3at the surface of the semiconductor material.

Referring toFIG.2, some embodiments relate to a method200of forming an electronic device.FIG.2illustrates a cross-sectional view of an exemplary substrate for processing by the method200. The substrate210comprises a crystalline semiconductor material220.

In some embodiments, the method200begins by forming an amorphous boron layer230on the crystalline semiconductor material220. Forming the amorphous boron layer may be performed by any suitable process, including but not limited to the processes outlined above for depositing a dopant film40.

In some embodiments, the method200continues by depositing additional semiconductor material240on the amorphous boron layer230. In some embodiments, the additional semiconductor material240is substantially amorphous.

In some embodiments, the method200continues by annealing the substrate210to crystallize the additional semiconductor material240and melt the amorphous boron layer230and form a boron doped crystalline semiconductor material250. In some embodiments, the anneal process comprises a laser anneal. In some embodiments, the boron doped crystalline semiconductor material250has the same stoichiometry as the crystalline semiconductor material220. In some embodiments, not shown, the method continues by forming a silicide from the boron doped crystalline semiconductor material250.

In some embodiments, the crystalline semiconductor material220and the additional semiconductor material are comprised of the same material. In some embodiments, the semiconductor material comprises silicon. In some embodiments, the semiconductor material comprises silicon and germanium.

With reference toFIG.3, additional embodiments of the disclosure are directed to processing tools900for executing the methods described herein.FIG.3illustrates a system900that can be used to process a substrate according to one or more embodiment of the disclosure. The system900can be referred to as a cluster tool. The system900includes a central transfer station910with a robot912therein. The robot912is illustrated as a single blade robot; however, those skilled in the art will recognize that other robot912configurations are within the scope of the disclosure. The robot912is configured to move one or more substrate between chambers connected to the central transfer station910.

At least one pre-clean/buffer chamber920is connected to the central transfer station910. The pre-clean/buffer chamber920can include one or more of a heater, a radical source or plasma source. The pre-clean/buffer chamber920can be used as a holding area for an individual semiconductor substrate or for a cassette of wafers for processing. The pre-clean/buffer chamber920can perform pre-cleaning processes or can pre-heat the substrate for processing or can simply be a staging area for the process sequence. In some embodiments, there are two pre-clean/buffer chambers920connected to the central transfer station910.

In the embodiment shown inFIG.3, the pre-clean chambers920can act as pass through chambers between the factory interface905and the central transfer station910. The factory interface905can include one or more robot906to move substrate from a cassette to the pre-clean/buffer chamber920. The robot912can then move the substrate from the pre-clean/buffer chamber920to other chambers within the system900.

A first processing chamber930can be connected to the central transfer station910. The first processing chamber930can be configured as an anisotropic etching chamber and may be in fluid communication with one or more reactive gas sources to provide one or more flows of reactive gases to the first processing chamber930. The substrate can be moved to and from the deposition chamber930by the robot912passing through isolation valve914.

Processing chamber940can also be connected to the central transfer station910. In some embodiments, processing chamber940comprises an isotropic etching chamber and is fluid communication with one or more reactive gas sources to provide flows of reactive gas to the processing chamber940to perform the isotropic etch process. The substrate can be moved to and from the deposition chamber940by robot912passing through isolation valve914.

Processing chamber945can also be connected to the central transfer station910. In some embodiments, the processing chamber945is the same type of processing chamber940configured to perform the same process as processing chamber940. This arrangement might be useful where the process occurring in processing chamber940takes much longer than the process in processing chamber930.

In some embodiments, processing chamber960is connected to the central transfer station910and is configured to act as a selective epitaxial growth chamber. The processing chamber960can be configured to perform one or more different epitaxial growth processes.

In some embodiments, the anisotropic etch process occurs in the same processing chamber as the isotropic etch process. In embodiments of this sort, the processing chamber930and processing chamber960can be configured to perform the etch processes on two substrates at the same time and processing chamber940and processing chamber945can be configured to perform the selective epitaxial growth processes.

In some embodiments, each of the processing chambers930,940,945and960are configured to perform different portions of the processing method. For example, processing chamber930may be configured to perform the anisotropic etch process, processing chamber940may be configured to perform the isotropic etch process, processing chamber945may be configured as a metrology station or to perform a first selective epitaxial growth process and processing chamber960may be configured to perform a second epitaxial growth process. The skilled artisan will recognize that the number and arrangement of individual processing chamber on the tool can be varied and that the embodiment illustrated inFIG.3is merely representative of one possible configuration.

In some embodiments, the processing system900includes one or more metrology stations. For example metrology stations can be located within pre-clean/buffer chamber920, within the central transfer station910or within any of the individual processing chambers. The metrology station can be any position within the system900that allows the distance of the recess to be measured without exposing the substrate to an oxidizing environment.

At least one controller950is coupled to one or more of the central transfer station910, the pre-clean/buffer chamber920, processing chambers930,940,945, or960. In some embodiments, there are more than one controller950connected to the individual chambers or stations and a primary control processor is coupled to each of the separate processors to control the system900. The controller950may be one of any form of general-purpose computer processor, microcontroller, microprocessor, etc., that can be used in an industrial setting for controlling various chambers and sub-processors.

The at least one controller950can have a processor952, a memory954coupled to the processor952, input/output devices956coupled to the processor952, and support circuits958to communication between the different electronic components. The memory954can include one or more of transitory memory (e.g., random access memory) and non-transitory memory (e.g., storage).

The memory954, or computer-readable medium, of the processor may be one or more of readily available memory such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The memory954can retain an instruction set that is operable by the processor952to control parameters and components of the system900. The support circuits958are coupled to the processor952for supporting the processor in a conventional manner. Circuits may include, for example, cache, power supplies, clock circuits, input/output circuitry, subsystems, and the like.

Processes may generally be stored in the memory as a software routine that, when executed by the processor, causes the process chamber to perform processes of the present disclosure. The software routine may also be stored and/or executed by a second processor (not shown) that is remotely located from the hardware being controlled by the processor. Some or all of the method of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed using a computer system, in hardware as, e.g., an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routine, when executed by the processor, transforms the general purpose computer into a specific purpose computer (controller) that controls the chamber operation such that the processes are performed.

In some embodiments, the controller950has one or more configurations to execute individual processes or sub-processes to perform the method. The controller950can be connected to and configured to operate intermediate components to perform the functions of the methods. For example, the controller950can be connected to and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum control, etc.

The controller950of some embodiments has one or more configurations selected from: a configuration to move a substrate on the robot between the plurality of processing chambers and metrology station; a configuration to load and/or unload substrates from the system; a configuration to deposit a dopant film; a configuration to anneal the substrate; and a configuration to deposit semiconductor material.

Reference throughout this specification to “one embodiment,” “certain embodiments,” “one or more embodiments” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as “in one or more embodiments,” “in certain embodiments,” “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, the present disclosure can include modifications and variations that are within the scope of the appended claims and their equivalents.