Patent ID: 12245460

DETAILED DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, embodiments are merely described below, by referring to the figures, to explain aspects of the description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

As the disclosure allows for various changes and numerous embodiments, embodiments will be illustrated in the drawings and described in detail in the written description. The effects and features of the disclosure, and ways to achieve them will become apparent by referring to embodiments that will be described later in detail with reference to the drawings. However, the disclosure is not limited to the following embodiments but may be embodied in various forms.

Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, like reference numerals refer to like elements and redundant descriptions thereof will be omitted.

It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

In embodiments below, the singular forms include the plural forms unless the context clearly indicates otherwise.

The terms “overlap” or “overlapped” mean that a first object may be above or below or to a side of a second object, and vice versa. Additionally, the term “overlap” may include layer, stack, face or facing, extending over, covering, or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art.

When an element is described as ‘not overlapping’ or ‘to not overlap’ another element, this may include that the elements are spaced apart from each other, offset from each other, or set aside from each other or any other suitable term as would be appreciated and understood by those of ordinary skill in the art.

The terms “face” and “facing” mean that a first element may directly or indirectly oppose a second element. In a case in which a third element intervenes between the first and second element, the first and second element may be understood as being indirectly opposed to one another, although still facing each other.

In embodiments below, it is to be understood that the terms such as ““comprises,” “comprising,” “includes,” and/or “including,”, “has,” “have,” and/or “having,” and variations thereof when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. In embodiments below, it will be understood that when a portion such as a layer, an area, or an element is referred to as being “on” or “above” another portion, it can be directly on or above the other portion, or intervening portion may also be present.

Also, in the drawings, for convenience of description, sizes of elements may be exaggerated or contracted. For example, since sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

When an embodiment is implementable in another manner, a process order may be different from a described one. For example, two processes that are consecutively described may be substantially simultaneously performed or may be performed in an opposite order to the described order.

In the specification, “A and/or B” refers to A, B, or A and B. In addition, “at least one of A and B” refers to A, B, or A and B.

In an embodiments below, it will be understood that when a portion such as a layer, an area, or an element is referred to as being “connected” to another portion, it can be directly connected to the other portion, or/and an intervening portion may also be present. For example, throughout the specification, it will be understood when a portion such as a layer, an area, or an element is referred to as being “electrically connected” to another portion, it can be directly electrically connected to the other portion, and/or it can be indirectly electrically connected with an intervening portion therebetween.

The phrase “in a plan view” means viewing the object from the top, and the phrase “in a schematic cross-sectional view” means viewing a cross-section of which the object is vertically cut from the side.

“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

An x-axis, a y-axis, and a z-axis are not limited to three axes on a rectangular coordinates system but may be construed as including these axes. For example, an-x axis, a y-axis, and a z-axis may be at right angles or may also indicate different directions from one another, which are not at right angles.

FIG.1is a schematic perspective view of a display apparatus according to an embodiment.

Referring toFIG.1, a display apparatus1may include a display area DA and a peripheral area PA outside of the display area DA. The display area DA may include a component area CA and a main display area MDA at least partially surrounding or adjacent to the component area CA. The component area CA and the main display area MDA may display an image individually or jointly. The peripheral area PA may be a type of non-display area where no display element is arranged or disposed. The display area DA may be entirely surrounded by the peripheral area PA.

FIG.1illustrates that a single component area CA is located or disposed in the main display area MDA. According to an embodiment, the display apparatus1may include two or more component areas CA, and a shape and size of component areas CA may be different from one another. When viewed from a direction approximately perpendicular to an upper surface of the display apparatus1, the component area CA may have various shapes such as substantially a circle, substantially an ellipse, a polygon including substantially a quadrangle, substantially a star shape, or substantially a diamond shape. Also, inFIG.1, the component area CA arranged or disposed in an upper middle portion of the main display area MDA (+y direction) having an approximately quadrangular shape when viewed from the direction approximately perpendicular to the upper surface of the display apparatus1is illustrated. However, the component area CA may also be arranged or disposed at a side of the main display area MDA, for example, at a right upper side or a left upper side thereof.

The display apparatus1may provide an image by using pixels PX arranged or disposed in the display area DA. The display apparatus1may provide an image by using main pixels PXm arranged or disposed in the main display area MDA and auxiliary pixels PXa arranged or disposed in the component area CA. Each of the main pixels PXm and each of the auxiliary pixels PXa may include a display element. Each of the main pixels PXm and each of the auxiliary pixels PXa may include a display element such as an organic light-emitting diode OLED. Each pixel PX may emit light of, for example, red, green, blue or white light through the organic light-emitting diode OLED. Herein, each pixel PX refers to a sub-pixel emitting light of different colors, and each pixel PX may be one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

As will be described later with reference toFIG.2, a component40, which is an electronic element, may be arranged or disposed in the component area CA under or below a display panel, to correspond to the component area CA. The component40may include a camera using an infrared ray or visible light or the like, and may include an imaging device. By way of example, the component40may include a solar cell, a flash, an illuminance sensor, a proximity sensor, or an iris sensor. By way of example, the component40may have a function of receiving sound. To minimize limitation of functions of the component40, the component area CA may include a transmission area TA through which light or/and sound or the like that is output from the component40to the outside or proceeds from the outside to the component40may transmit. In a display panel according to an embodiment and a display apparatus including the display panel, in case that the component area CA transmits light, light transmittance may be about 10% or higher, about 40% or higher, about 25% or higher, about 50% or higher, about 85% or higher, or about 90% or higher.

The auxiliary pixels PXa may be arranged or disposed in the component area CA. The component area CA may include an auxiliary display area ADA as illustrated inFIG.2which will be described later, and the auxiliary pixels PXa may be arranged or disposed in the auxiliary display area ADA.

The auxiliary pixels PXa may emit light to provide an image. An image displayed in the component area CA may be an auxiliary image, and may have a lower resolution than an image displayed in the main display area MDA. For example, the component area CA may include the transmission area TA through which light and sound may transmit, and in case that no pixel is arranged or disposed in the transmission area TA, the number of auxiliary pixels PXa to be arranged or disposed in the component area CA per unit area may be less than the number of main pixels PXm arranged or disposed in the main display area MDA per unit area. This will be described in further detail with reference toFIG.3.

FIG.2is a schematic cross-sectional view schematically illustrating a display apparatus1according to an embodiment.

Referring toFIG.2, the display apparatus1may include a display panel10and a component40overlapping the display panel10. A cover window (not shown) protecting the display panel10may be further arranged or disposed above the display panel10.

The display panel10may include the component area CA overlapping the component40and the main display area MDA on which a main image is displayed. As the display panel10may include a substrate100as will be described later, it may also be said that the substrate100may include the component area CA and the main display area MDA. In other words, the component area CA and the main display area MDA may be defined in the substrate100.

The display panel10may include the substrate100, a display layer DISL, a touch screen layer TSL, and an optical functional layer OFL on the substrate100, and a panel protection member PB arranged or disposed under or below the substrate100.

The display layer DISL may include a circuit layer PCL including a pixel circuit PC including a transistor (for example, a thin-film transistor), a display element layer DEL including main and auxiliary display elements DEm and DEa, and an encapsulation member ENCM such as a thin-film encapsulation layer or an encapsulation substrate (not shown). Insulating layers IL and IL′ may be between the substrate100and the display layer DISL and in the display layer DISL.

The substrate100may include an insulating material such as glass, quartz, or a polymer resin. The substrate100may include a rigid substrate or a flexible substrate that is bendable, foldable, rollable, or the like within the spirit and the scope of the disclosure.

The main pixel PXm may be arranged or disposed in the main display area MDA of the display panel10. The main pixel PXm may include a main pixel circuit PCm and a main display element DEm electrically connected to the main pixel circuit PCm. The main pixel circuit PCm may include at least one transistor and control emission of the main display element DEm. The main pixel PXm may be implemented by using light emission of the main display element DEm.

The auxiliary pixel PXa may be arranged or disposed in the component area CA of the display panel10. The auxiliary pixel PXa may include an auxiliary pixel circuit PCa and the auxiliary display element DEa electrically connected to the auxiliary pixel circuit PCa. The auxiliary pixel circuit PCa may include at least one transistor and control emission of the auxiliary display element DEa. The auxiliary pixel PXa may be implemented by using light emission of the auxiliary display element DEa.

An area of the component area CA where the auxiliary pixel PXa is arranged or disposed may be referred to as the auxiliary display area ADA. Also, an area of the component area CA where the auxiliary pixel PXa is not arranged or disposed may be referred to as the transmission area TA. The transmission area TA may include an area through which light or a signal emitted from the component40arranged or disposed to correspond to the component area CA or light or a signal incident to the component40are transmitted. The auxiliary display area ADA and the transmission area TA may be alternately arranged or disposed in the component area CA. The transmission area TA may surround the auxiliary display area ADA.

According to an embodiment, the main pixel circuit PCm and the auxiliary pixel circuit PCa may be electrically connected to each other via a connection line CL. For example, a main conductive line of the main pixel circuit PCm and an auxiliary conductive line of the auxiliary pixel circuit PCa may be electrically connected to each other via the connection line CL. The main conductive line may include a main gate line, and the auxiliary conductive line may include an auxiliary gate line. By way of example, the main conductive line may include a main data line, and the auxiliary conductive line may include an auxiliary data line. Thus, a gate signal and/or a data voltage supplied to the main pixel circuit PCm may also be supplied to the auxiliary pixel circuit PCa.

Also, the auxiliary pixel circuits PCa may be electrically connected to each other via a connection line CL′. For example, auxiliary conductive lines of the auxiliary pixel circuits PCa may be electrically connected to each other via the connection line CL′. Thus, the auxiliary pixel circuits PCa may share with one another a gate signal and/or a data voltage received from the main pixel circuit PCm.

Thus, the auxiliary pixel circuits PCa may receive a gate signal and/or a data voltage from an adjacent main pixel circuit PCm. Thus, the auxiliary pixel circuits PCa may control the auxiliary display elements DEa in the same manner as the main pixel circuit PCm does.

According to an embodiment, the connection lines CL and CL′ may at least partially overlap the transmission area TA. The connection lines CL and CL′ may include a transparent conductive material having high transmittance, and thus, even in case that the connection lines CL and CL′ are arranged or disposed to at least partially overlap the transmission area TA, transmittance of the transmission area TA may be ensured.

The display element layer DEL may be covered or overlapped using the thin-film encapsulation layer TFEL or an encapsulation substrate. In an embodiment, the thin-film encapsulation layer TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer as illustrated inFIG.2. According to an embodiment, the thin-film encapsulation layer TFEL may include a first inorganic encapsulation layer131and a second inorganic encapsulation layer133and an organic encapsulation layer132therebetween.

The first inorganic encapsulation layer131and the second inorganic encapsulation layer133may include at least one inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiNx) silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), and may be formed using, for example, a chemical vapor deposition (CVD) method. The organic encapsulation layer132may include a polymer-based material. Examples of the polymer-based material may include a silicon resin, an acrylic resin, an epoxy resin, polyimide (PI), and polyethylene.

The first inorganic encapsulation layer131, the organic encapsulation layer132, and the second inorganic encapsulation layer133may be integral with each other as a single body to cover or overlap the main display area MDA and the component area CA.

In case that the display element layer DEL is encapsulated using an encapsulation substrate (not shown), the encapsulation substrate may be arranged or disposed to face the substrate100with the display element layer DEL therebetween. There may be a gap between the encapsulation substrate and the display element layer DEL. The encapsulation substrate may include glass. A sealant including a frit or the like may be arranged or disposed between the substrate100and the encapsulation substrate, and the sealant may be arranged in the peripheral area PA illustrated inFIG.1. The sealant arranged or disposed in the peripheral area PA may surround the display area DA and prevent lateral penetration of moisture.

The touch screen layer TSL may acquire coordinate information according to an external input, for example, a touch event. The touch screen layer TSL may include a touch electrode and touch wirings electrically connected to the touch electrode. The touch screen layer TSL may sense an external input by using a self-capacitance method or a mutual capacitance method.

The touch screen layer TSL may be formed or disposed on the thin-film encapsulation layer TFEL. By way of example, the touch screen layer TSL may be separately formed or disposed on a touch substrate and coupled or connected onto the thin-film encapsulation layer TFEL by using an adhesive layer such as an optically clear adhesive (OCA). According to an embodiment, the touch screen layer TSL may be formed or disposed on or may be directly formed or disposed on the thin-film encapsulation layer TFEL, and, the adhesive layer may not be between the touch screen layer TSL and the thin-film encapsulation layer TFEL.

The optical functional layer OFL may include an anti-reflection layer. The anti-reflection layer may reduce reflectance of light incident from the outside to the display apparatus1(external light).

In an embodiment, the optical functional layer OFL may include a polarization film. The optical functional layer OFL may include an opening OFL_OP corresponding to the transmission area TA. Accordingly, light transmittance of the transmission area TA may be significantly improved. The opening OFL_OP of the optical functional layer OFL may be filled with a transparent material such as an optically clear resin (OCR).

In an embodiment, the optical functional layer OFL may include a filter plate including a black matrix and color filters.

The panel protection member PB may be attached under or below the substrate100to support and protect the substrate100. The panel protection member PB may include an opening PB_OP corresponding to the component area CA. As the panel protection member PB may include the opening PB_OP, the light transmittance of the component area CA may be improved. The panel protection member PB may include polyethylene terephthalate (PET) or PI.

The component area CA may have a larger area than an area where the component40is arranged or disposed. Accordingly, an area of the opening PB_OP included in the panel protection member PB may not be equal to the area of the component area CA.

Also, components40may be arranged or disposed in the component area CA. The components40may have different functions from each other. For example, the components40may include at least two of a camera (imaging device), a solar cell, a flash, a proximity sensor, an illuminance sensor, and an iris sensor.

Although not illustrated inFIG.2, a bottom metal layer may be arranged or disposed below the auxiliary pixel PXa of the component area CA. The bottom metal layer may be arranged or disposed below the auxiliary display element DEa constituting the auxiliary pixel PXa. For example, the display apparatus1may include the bottom metal layer.

The bottom metal layer may be arranged or disposed to overlap the auxiliary display element DEa between the substrate100and the auxiliary display element DEa. The bottom metal layer may block external light from reaching the auxiliary display element DEa. The bottom metal layer may be formed to correspond to the entire component area CA, and may include a bottom hole corresponding to the transmission area TA. The bottom hole may have various shapes such as substantially a polygon, substantially a circle, or an amorphous shape to adjust diffraction characteristics of external light.

FIG.3is a schematic enlarged plan view of a portion of a display apparatus according to an embodiment.

Referring toFIG.3, main pixel units PXum may be arranged or disposed in the main display area MDA. Each of the main pixel units PXum may include a first main pixel PXm1, a second main pixel PXm2, and a third main pixel PXm3. The first main pixel PXm1, the second main pixel PXm2, and the third main pixel PXm3may emit light of different colors from each other. For example, the first main pixel PXm1may emit red light, the second main pixel PXm2may emit green light, and the third main pixel PXm3may emit blue light.

According to an embodiment, the first main pixel PXm1, the second main pixel PXm2, and the third main pixel PXm3may be arranged or disposed in a PenTile® type arrangement.

For example, from among vertices of a virtual square VS having a center point of the second main pixel PXm2as a center point of the square, the first main pixel PXm1may be placed at first and third vertices of the virtual square VS, and the third main pixel PXm3may be placed at second and fourth vertices of the virtual square VS. The virtual square VS may be modified to various shapes such as substantially a rectangle, substantially a rhombus, or substantially a square.

The above-described pixel arrangement is referred to as a PenTile® matrix structure or a PenTile® structure, and a high resolution may be obtained using a small number of pixels by applying rendering driving whereby colors are expressed by sharing adjacent pixels.

The main pixel units PXum arranged or disposed in the main display area MDA in a PenTile® matrix structure are illustrated inFIG.3, but the disclosure is not limited thereto.

According to an embodiment, the main pixel units PXum, for example, the first main pixel PXm1, the second main pixel PXm2, and the third main pixel PXm3may be arranged or disposed in a stripe arrangement, a mosaic arrangement, a delta arrangement or the like within the spirit and the scope of the disclosure.

According to an embodiment, as illustrated inFIG.3, the third main pixel PXm3and the first main pixel PXm1may have a greater size (or width) than a size (or width) of the second main pixel PXm2.

The auxiliary pixels PXa may be respectively arranged or disposed in the auxiliary display areas ADA of the component area CA. The auxiliary pixels PXa may emit light of different colors. For example, the auxiliary pixels PXa may respectively emit light of any one of red, green, and blue colors.

The component area CA may include the transmission area TA. The transmission area TA may be arranged or disposed to surround each of the auxiliary display areas ADA. As the auxiliary pixels PXa may be respectively arranged or disposed in the auxiliary display areas ADA, the transmission area TA may be arranged or disposed to surround each auxiliary pixel PXa. By way of example, the transmission area TA may be arranged or disposed in a lattice form with respect to the auxiliary pixels PXa.

As the component area CA has the transmission area TA, a resolution of the component area CA may be lower than a resolution of the main display area MDA. For example, the resolution of the component area CA may be about ½, ⅜, ⅓, ¼, 2/9, ⅛, 1/9, 1/12.25, or 1/16 of the resolution of the main display area MDA. The resolution of the main display area MDA may be equal to or higher than about 400 ppi, and the resolution of the component area CA may be about 200 ppi or about 100 ppi.

In other words, the number of auxiliary pixels PXa arranged or disposed in the component area CA per unit area may be less than the number of main pixels PXm arranged or disposed in the main display area MDA per unit area. For example, the number of auxiliary pixels PXa and the number of the main pixels PXm, each arranged or disposed in an equal area, may be provided in a ratio of, for example, about 1:2, about 1:4, about 1:8, about 1:9, or about 1:12.25. As the main pixel PXm may include the main display element DEm (FIG.2), and the auxiliary pixel PXa may include the auxiliary display element DEa (FIG.2), the number of auxiliary pixels PXa per unit area may be regarded to be less than the number of the main display elements DEm per unit area.

The auxiliary pixels PXa arranged or disposed in the component area CA may be arranged or disposed in various forms.

According to an embodiment, some or a part of the auxiliary pixels PXa may be grouped into a pixel group, and the auxiliary pixels PXa may be arranged or disposed in various forms such as a PenTile® structure, a stripe arrangement, a mosaic arrangement, a delta arrangement or the like, in each pixel group. A distance between the auxiliary pixels PXa arranged or disposed in a pixel group may be equal to a distance between the main pixels PXm.

By way of example, according to an embodiment, the auxiliary pixels PXa may be distributed within the component area CA as illustrated inFIG.3.

FIG.4is a schematic enlarged plan view of a region of a display apparatus according to an embodiment.

Referring toFIG.4, main pixel circuits PCm and first main conductive lines MCL1respectively constituting the main pixels PXm (FIG.3) may be arranged or disposed in the main display area MDA.

The main pixel circuits PCm may be arranged or disposed in a first direction (for example, ±x direction) and a second direction (for example, ±y direction). The main pixel circuits PCm may be respectively electrically connected to outer circuits arranged or disposed in the peripheral area PA.

Gate driving circuits GDC may be arranged or disposed in the peripheral area PA. The gate driving circuits GDC may be arranged or disposed in the second direction (for example, ±y direction) in the peripheral area PA as illustrated inFIG.4. The gate driving circuits GDC may be electrically connected to the first main conductive lines MCL1respectively extending in the first direction (for example, ±x direction).

The first main conductive lines MCL1may be respectively electrically connected to the main pixel circuits PCm located or disposed in same rows. The first main conductive lines MCL1may respectively transfer an electrical signal to the main pixel circuits PCm located or disposed in same rows.

For example, as illustrated inFIG.4, a first main pixel circuit PCm1which is one of the main pixel circuits PCm may be electrically connected to the first main conductive line MCL1extending in the first direction (for example, ±x direction).

While each of the first main conductive lines MCL1is illustrated as a single wiring inFIG.4, the first main conductive lines MCL1may each include wirings. For example, each of the first main conductive lines MCL1may include a main scan line, a main emission control line, or the like within the spirit and the scope of the disclosure. This will be described in further detail later with reference toFIG.11.

The auxiliary pixel circuits PCa, first auxiliary conductive lines ACL1, and first connection lines CL1respectively constituting the auxiliary pixels PXa (FIG.3) may be arranged or disposed in the component area CA.

The first auxiliary conductive lines ACL1may respectively extend in the first direction (for example, ±x direction) to be electrically connected to the auxiliary pixel circuits PCa.

For example, as illustrated inFIG.4, a first auxiliary pixel circuit PCa1, which is one of the auxiliary pixel circuits PCa, may be electrically connected to a 1-1stauxiliary conductive line ACL1aextending in the first direction (for example, ±x direction), and a second auxiliary pixel circuit PCa2, which is another one of the auxiliary pixel circuits PCa, may be electrically connected to a 1-2ndauxiliary conductive line ACL1bextending in the first direction (for example, ±x direction), and a third auxiliary pixel circuit PCa3, which is another one of the auxiliary pixel circuits PCa, may be electrically connected to a 1-3rdauxiliary conductive line ACL1cextending in the first direction (for example, ±x direction).

Here, the auxiliary display area ADA, in which the first auxiliary pixel circuit PCa1is arranged or disposed, from among the auxiliary display areas ADA, may be referred to as a first auxiliary display area ADA1; the auxiliary display area ADA, in which the second auxiliary pixel circuit PCa2is arranged or disposed, from among the auxiliary display areas ADA, may be referred to as a second auxiliary display area ADA2; and the auxiliary display area ADA, in which the third auxiliary pixel circuit PCa3is arranged or disposed, from among the auxiliary display areas ADA, may be referred to as a third auxiliary display area ADA3.

While each of the first auxiliary conductive lines ACL1is illustrated as a single wiring inFIG.4, each of the first auxiliary conductive lines ACL1may include wirings. For example, each of the first auxiliary conductive lines ACL1may include an auxiliary scan line, an auxiliary emission control line, or the like within the spirit and the scope of the disclosure. As each of the first auxiliary conductive lines ACL1may include wirings, each of the first connection lines CL1may also include wirings. This will be described in further detail later with reference toFIG.11.

Each of the first connection lines CL1may extend in the first direction (for example, ±x direction) to electrically connect the first main conductive line MCL1to the first auxiliary conductive line ACL1or electrically connect the first auxiliary conductive lines ACL1electrically connected to different auxiliary pixel circuits PCa to one another.

In other words, some or a part of the first connection lines CL1may electrically connect the first main conductive line MCL1to the first auxiliary conductive line ACL1. Some others of the first connection lines CL1may electrically connect the first auxiliary conductive lines ACL1electrically connected to different auxiliary pixel circuits PCa, to one another.

For example, as illustrated inFIG.4, a 1-1stconnection line CL1a, which is one of the first connection lines CL1, may electrically connect the first main conductive line MCL1to the 1-1stauxiliary conductive line ACL1a. A 1-2ndconnection line CL1b, which is another one of the first connection lines CL1, may electrically connect the 1-1stauxiliary conductive line ACL1ato the 1-2ndauxiliary conductive line ACL1b. A 1-3rdconnection line CL1c, which is another one of the first connection lines CL1, may electrically connect the 1-2ndauxiliary conductive line ACL1bto the 1-3rdauxiliary conductive line ACL1c.

The first main conductive line MCL1and the first auxiliary conductive line ACL1that are electrically connected to each other via the first connection line CL1, from among the first main conductive lines MCL1and the first auxiliary conductive lines ACL1, may be apart from each other in the first direction (for example, ±x direction). The first auxiliary conductive lines ACL1electrically connected to each other via the first connection line CL1, from among the first auxiliary conductive lines ACL1, may be apart from each other in the first direction (for example, ±x direction). The transmission area TA may be between the first main conductive line MCL1and the first auxiliary conductive line ACL1that are apart from each other in the first direction (for example, ±x direction). The transmission area TA may be arranged or disposed between the first auxiliary conductive lines ACL1that are apart from each other in the first direction (for example, ±x direction).

For example, as illustrated inFIG.4, the first main conductive line MCL1and the 1-1stauxiliary conductive line ACL1a, the 1-1stauxiliary conductive line ACL1aand the 1-2ndauxiliary conductive line ACL1b, and the 1-2ndauxiliary conductive line ACL1band the 1-3rdauxiliary conductive line ACL1cmay be respectively apart from each other in the first direction (for example, ±x direction). The transmission area TA may be arranged or disposed between the first main conductive line MCL1and the 1-1stauxiliary conductive line ACL1a, between the 1-1stauxiliary conductive line ACL1aand the 1-2ndauxiliary conductive line ACL1b, and between the 1-2ndauxiliary conductive line ACL1band the 1-3rdauxiliary conductive line ACL1c.

As described above, in case that the first main conductive line MCL1and the first auxiliary conductive line ACL1that are apart from each other in the first direction (for example, ±x direction) are electrically connected to each other via the first connection line CL1, and the first auxiliary conductive lines ACL1that are apart from each other in the first direction (for example, ±x direction) are electrically connected to each other via the first connection line CL, an electrical signal supplied from the gate driving circuit GDC may be transferred to each of the main pixel circuits PCm and the auxiliary pixel circuits PCa arranged or disposed in the first direction (for example, ±x direction).

As illustrated inFIG.1, the main display area MDA may surround the component area CA. The first main conductive lines MCL1that are apart from each other in the first direction (for example, ±x direction) by the component area CA may be electrically connected to each other via the first connection lines CL1and the first auxiliary conductive lines ACL1.

According to an embodiment, the first connection line CL1and the first main conductive line MCL1may be electrically connected to each other via a first contact plug CP1. The first connection line CL1and the first auxiliary conductive line ACL1may be electrically connected to each other via the first contact plug CP1.

For example, as illustrated inFIG.4, the 1-1stconnection line CL1aand the first main conductive line MCL1may be electrically connected to each other via a 1-1stcontact plug CP1a, and the 1-1stconnection line CL1aand the 1-1stauxiliary conductive line ACL1amay be electrically connected to each other via a 1-2ndcontact plug CP1b. The 1-2ndconnection line CL1band the 1-1stauxiliary conductive line ACL1amay be electrically connected to each other via a 1-3rdcontact plug CP1c, and the 1-2ndconnection line CL1band the 1-2ndauxiliary conductive line ACL1bmay be electrically connected to each other via a 1-4thcontact plug CP1d. The 1-3rdconnection line CL1cand the 1-2ndauxiliary conductive line ACL1bmay be electrically connected to each other via a 1-5thcontact plug CP1e, and the 1-3rdconnection line CL1cand the 1-3rdauxiliary conductive line ACL1cmay be electrically connected to each other via a 1-6thcontact plug CP1f.

As illustrated inFIGS.5and6to be described later, some or a part of the first connection lines CL1may be buried in a contact hole formed in an insulating layer. A portion of the first connection line CL1buried in the contact hole may be referred to as the first contact plug CP1. In other words, the first connection line CL1and the first contact plug CP1may be a single body.

According to an embodiment, the first connection line CL1may have higher light transmittance than the first main conductive line MCL1and the first auxiliary conductive line ACL1. The first connection line CL1may include a transparent conducting oxide (TCO). For example, the first connection line CL1may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

According to an embodiment, as illustrated inFIG.4, each of the first connection lines CL1may at least partially overlap the transmission area TA. As described above, the first connection line CL1may include a transparent conductive material having high transmittance, and thus, even in case that the first connection line CL1is arranged or disposed to at least partially overlap the transmission area TA, transmittance of the transmission area TA may be ensured.

FIGS.5and6are schematic cross-sectional views of a portion ofFIG.4taken along line I-I′ and line II-II′.

FIGS.5and6illustrate cross-sections of a pixel circuit PC including at least one transistor TFT, the first main conductive line MCL1, the first connection line CL1(FIG.4), and the first auxiliary conductive line ACL1(FIG.4). The pixel circuit PC may be the main pixel circuit PCm (FIG.4) arranged or disposed in the main display area MDA or the auxiliary pixel circuit PCa (FIG.4) arranged or disposed in the auxiliary display area ADA (FIG.4).

Hereinafter, a configuration included in the display apparatus will be described in detail according to a stack structure thereof by referring toFIGS.5and6, and positional relationships of the first main conductive line MCL1, the first connection line CL1, and the first auxiliary conductive line ACL1will be described.

The substrate100may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate. The substrate100including the polymer resin may be flexible, rollable, or bendable. The substrate100may have a multi-layer structure including a layer including the above-described polymer resin and an inorganic layer (not shown).

The buffer layer111may reduce or block penetration of foreign substances, moisture, or outside air from below the substrate100, and may provide a flat surface on the substrate100. The buffer layer111may include an inorganic material such as oxide or nitride, an organic material, or an organic-inorganic complex material, and may have a single-layer or multi-layer structure including an inorganic material and an organic material.

A barrier layer (not shown) may be further included between the substrate100and the buffer layer111. The barrier layer may prevent or minimize penetration of impurities from the substrate100or the like into a semiconductor layer A. The barrier layer may include an inorganic material such as oxide or nitride, an organic material, or an organic-inorganic complex material, and may have a single-layer or multi-layer structure including an inorganic material and an organic material.

The semiconductor layer A may be arranged or disposed on the buffer layer111. The semiconductor layer A may include amorphous silicon or polysilicon. According to an embodiment, the semiconductor layer A may include an oxide of at least one material from among indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

The semiconductor layer A may include a channel region C and a source region S and a drain region D arranged or disposed on both sides of the channel region C. The semiconductor layer A may include a single layer or multiple layers.

A first gate insulating layer113and a second gate insulating layer115may be stacked each other and arranged or disposed above the substrate100to cover or overlap the semiconductor layer A. For example, the first gate insulating layer113and the second gate insulating layer115may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

A first conductive layer may be arranged or disposed above the first gate insulating layer113. The first conductive layer may have a single-layer or multi-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like within the spirit and the scope of the disclosure. For example, the first conductive layer may include a single layer of Mo.

A second conductive layer may be arranged or disposed above the second gate insulating layer115. The second conductive layer may have a single-layer or multi-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like within the spirit and the scope of the disclosure. For example, the second conductive layer may include a single layer of Mo.

The first conductive layer may include a gate electrode G. The gate electrode G may be arranged or disposed to at least partially overlap the semiconductor layer A.

The second conductive layer may include an upper electrode CE2of a storage capacitor Cst.

According to an embodiment, the storage capacitor Cst may include a lower electrode CE1and the upper electrode CE2, and may overlap the transistor TFT as illustrated inFIGS.5and6. For example, the gate electrode G of the transistor TFT may function as the lower electrode CE1of the storage capacitor Cst. By way of example, the storage capacitor Cst may not overlap the transistor TFT, but may exist separately therefrom.

The upper electrode CE2of the storage capacitor Cst may overlap the lower electrode CE1with the second gate insulating layer115therebetween, and form capacitance. The second gate insulating layer115may function as a dielectric layer of the storage capacitor Cst.

According to an embodiment, as illustrated inFIG.5, the first conductive layer may include the first main conductive line MCL1and the first auxiliary conductive line ACL1. In other words, the first main conductive line MCL1and the first auxiliary conductive line ACL1may be arranged or disposed on an upper surface of the first gate insulating layer113.FIG.5illustrates, as an example, the 1-1stauxiliary conductive line ACL1aand the 1-2ndauxiliary conductive line ACL1bfrom among the first auxiliary conductive lines ACL1.

According to an embodiment, as illustrated inFIG.6, the second conductive layer may include the first main conductive line MCL1and the first auxiliary conductive line ACL1. In other words, the first main conductive line MCL1and the first auxiliary conductive line ACL1may be arranged or disposed on an upper surface of the second gate insulating layer115. FIG.6illustrates, as an example, the 1-1stauxiliary conductive line ACL1aand the 1-2ndauxiliary conductive line ACL1bfrom among the first auxiliary conductive lines ACL1.

An interlayer insulating layer117may be provided or disposed on the second gate insulating layer115to cover or overlap the upper electrode CE2of the storage capacitor Cst. The interlayer insulating layer117may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

A third conductive layer may be arranged or disposed on the interlayer insulating layer117. The third conductive layer may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multi-layer or single-layer structure including the above material. For example, the third conductive layer may have a Ti/Al/Ti multi-layer structure.

The third conductive layer may include a first electrode E1. The first electrode E1may be electrically connected to the drain region D of the semiconductor layer A via a contact hole formed in the first gate insulating layer113, the second gate insulating layer115, and the interlayer insulating layer117. While the first electrode E1is illustrated as being electrically connected to the drain region D of the semiconductor layer A inFIGS.5and6, according to an embodiment, the first electrode E1may be electrically connected to the source region S of the semiconductor layer A.

The third conductive layer may be covered or overlapped by an inorganic protective layer (not shown). The inorganic protective layer may include a single layer or multiple layers including silicon nitride (SiNX) or silicon oxide (SiOX). The inorganic protective layer may be introduced to cover or overlap and protect some or a part of wirings arranged or disposed on the inter layer insulating layer117.

A planarization layer119is arranged or disposed to cover or overlap the third conductive layer, and the planarization layer119may include contact holes used to electrically connect the transistor TFT and a pixel electrode210to each other.

The planarization layer119may include an organic material layer provided as a single layer or multiple layers, and provide a flat upper surface. The planarization layer119may include a general-purpose polymer such as benzocyclobutene (BCB), PI, hexamethyldisiloxane (HMIDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymers, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and blends thereof.

According to an embodiment, as illustrated inFIGS.5and6, the planarization layer119may include a first planarization layer119a, a second planarization layer119b, and a third planarization layer119c.

A fourth conductive layer may be arranged or disposed on the first planarization layer119a. The fourth conductive layer may include a TCO. For example, the fourth conductive layer may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

The fourth conductive layer may include the first connection line CL1.FIGS.5and6illustrate, as an example, the 1-1stconnection line CL1aand the 1-2ndconnection line CL1bfrom among the first connection lines CL1.

According to an embodiment, as illustrated inFIG.5, the first connection line CL1may be electrically connected to the first main conductive line MCL1and/or the first auxiliary conductive line ACL1via first contact holes formed in the second gate insulating layer115, the interlayer insulating layer117, and the first planarization layer119a. Portions of the first connection line CL1may be respectively buried in the first contact holes, and the portions of the first connection line CL1respectively buried in the first contact holes may be referred to as the first contact plugs CP1(FIG.4). In other words, the first connection line CL1and the first contact plug CP1may be integrated.

For example, a 1-1stcontact hole CNT1a, a 1-2ndcontact hole CNT1b, a 1-3rdcontact hole CNT1c, and a 1-4thcontact hole CNT1dmay be formed in the second gate insulating layer115, the interlayer insulating layer117, and the first planarization layer119a.

Portions of the 1-1stconnection line CL1amay be respectively buried in the 1-1stcontact hole CNT1aand the 1-2ndcontact hole CNT1b. The portion of the 1-1stconnection line CL1aburied in the 1-1stcontact hole CNT1amay be referred to as the 1-1stcontact plug CP1a, and the portion of the 1-1stconnection line CL1aburied in the 1-2ndcontact hole CNT1bmay be referred to as the 1-2ndcontact plug CP1b. The 1-1stconnection line CL1a, the 1-1stcontact plug CP1a, and the 1-2ndcontact plug CP1bmay be integrated.

Portions of the 1-2ndconnection line CL1bmay be respectively buried in the 1-3rdcontact hole CNT1cand the 1-4thcontact hole CNT1d. A portion of the 1-2ndconnection line CL1bburied in the 1-3rdcontact hole CNT1cmay be referred to as the 1-3rdcontact plug CP1c, and a portion of the 1-2ndconnection line CL1bburied in the 1-4thcontact hole CNT1dmay be referred to as the 1-4thcontact plug CP1d. The 1-2ndconnection line CL1b, the 1-3rdcontact plug CP1c, and the 1-4thcontact plug CP1dmay be integrated.

As a result, the 1-1stconnection line CL1amay be electrically connected to the first main conductive line MCL1via the 1-1stcontact plug CP1a, and electrically connected to the 1-1stauxiliary conductive line ACL1avia the 1-2ndcontact plug CP1b. The 1-2ndconnection line CL1bmay be electrically connected to the 1-1stauxiliary conductive line ACL1avia the 1-3rdcontact plug CP1c, and electrically connected to the 1-2ndauxiliary conductive line ACL1bvia the 1-4thcontact plug CP1d.

As illustrated inFIG.6, in case that the first main conductive line MCL1and the first auxiliary conductive line ACL1are arranged or disposed on the second gate insulating layer115, the first contact holes may be formed in the interlayer insulating layer117and the first planarization layer119a.

A fifth conductive layer may be arranged or disposed on the second planarization layer119b. The fifth conductive layer may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multi-layer or single-layer structure including the above material.

The fifth conductive layer may include a second electrode E2. The second electrode E2may be electrically connected to the first electrode E1via a contact hole formed in the first planarization layer119aand the second planarization layer119b.

A display element DE may be arranged or disposed on the planarization layer119. The display element DE may include the pixel electrode210, an intermediate layer220including an organic emission layer, and an opposite electrode230. For example, the display element DE may include an organic light-emitting diode.

The display element DE may be electrically connected to the transistor TFT via the contact holes formed in the planarization layer119and the second electrode E2. Accordingly, the display element DE may be electrically connected to the pixel circuit PC.

The pixel electrode210may include a (semi)transmissive electrode or a reflective electrode. In an embodiment, the pixel electrode210may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or semitransparent electrode layer formed on the reflective layer. The transparent or semitransparent electrode layer may include at least one from among indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In an embodiment, the pixel electrode210may have an ITO/Ag/ITO structure.

In a display area of the substrate100, a pixel defining layer121may be arranged or disposed on the planarization layer119. The pixel defining layer121may cover or overlap edges of the pixel electrode210and have an opening exposing a center portion of the pixel electrode210. A light-emitting area of the display element DE may be defined by the opening.

The pixel defining layer121may increase a distance between the edges of the pixel electrode210and the opposite electrode230above the pixel electrode210to thereby perform a function of preventing an arc or the like at the edges of the pixel electrode210.

The pixel defining layer121may include at least one organic insulating material from among PI, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed using a method such as spin coating.

The intermediate layer220may be arranged or disposed in the opening formed by the pixel defining layer121and may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material emitting red, green, blue, or white light. The organic emission layer may be a low molecular weight organic material or a polymer organic material, and a functional layer such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be selectively further arranged or disposed below and above the organic emission layer.

The opposite electrode230may include a transmissive electrode or a reflective electrode. In an embodiment, the opposite electrode230may include a transparent or semitransparent electrode, and may include a metal thin-film including Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, or a compound thereof and having a small work function. Also, a TCO layer such as ITO, IZO, ZnO or In2O3may be further arranged or disposed on the metal thin-film. The opposite electrode230may be arranged or disposed over the display area, and arranged or disposed on the intermediate layer220and the pixel defining layer121. The opposite electrode230may be integral with respect to display elements DE to correspond to pixel electrodes210.

The display element DE as described above may be easily damaged by external moisture or oxygen, and thus may be covered or overlapped using an encapsulation layer (not shown) to be protected. The encapsulation layer may cover or overlap the display area and extend to at least a portion of a peripheral area. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

FIG.7is a schematic enlarged plan view of a region of a display apparatus according to an embodiment.

Referring toFIG.7, the main pixel circuits PCm and the second main conductive lines MCL2respectively constituting the main pixels PXm (FIG.3) may be arranged or disposed in the main display area MDA.

The second main conductive lines MCL2may be respectively electrically connected to the main pixel circuits PCm located or disposed in same columns. The second main conductive lines MCL2may be electrically connected to a pad or a voltage wiring arranged or disposed in the peripheral area PA (FIG.1). The second main conductive lines MCL2may respectively transfer an electrical signal to the main pixel circuits PCm located or disposed in same columns.

For example, as illustrated inFIG.7, a second main pixel circuit PCm2which is one of the main pixel circuits PCm may be electrically connected to the second main conductive line MCL2extending in the second direction (for example, ±y direction).

While each of the second main conductive lines MCL2is illustrated as a single wiring inFIG.7, the second main conductive lines MCL2may each include wirings. For example, each of the second main conductive lines MCL2may include a main data line, a main driving voltage line, or the like within the spirit and the scope of the disclosure. This will be described in further detail later with reference toFIG.11.

The auxiliary pixel circuits PCa, second auxiliary conductive lines ACL2, and second connection lines CL2respectively constituting the auxiliary pixels PXa (FIG.3) may be arranged or disposed in the component area CA.

The second auxiliary conductive lines ACL2may respectively extend in the second direction (for example, ±y direction) to be electrically connected to the auxiliary pixel circuits PCa.

For example, as illustrated inFIG.7, a fourth auxiliary pixel circuit PCa4, which is one of the auxiliary pixel circuits PCa, may be electrically connected to a 2-1stauxiliary conductive line ACL2aextending in the second direction (for example, ±y direction), and a fifth auxiliary pixel circuit PCa5, which another one of the auxiliary pixel circuits PCa, may be electrically connected to a 2-2ndauxiliary conductive line ACL2bextending in the second direction (for example, ±y direction).

The auxiliary display area ADA, in which the fourth auxiliary pixel circuit PCa4is arranged or disposed, from among the auxiliary display areas ADA, may be referred to as a fourth auxiliary display area ADA4, and the auxiliary display areas ADA, in which the fifth auxiliary pixel circuit PCa5is arranged or disposed, from among the auxiliary display areas ADA, may be referred to as a fifth auxiliary display area ADA5.

While each of the second auxiliary conductive lines ACL2is illustrated as a single wiring inFIG.7, each of the second auxiliary conductive lines ACL2may include wirings. For example, each of the second auxiliary conductive lines ACL2may include an auxiliary data line, an auxiliary driving voltage line, or the like within the spirit and the scope of the disclosure. As each of the second auxiliary conductive lines ACL2may include wirings, each of the second connection lines CL2may also include wirings. This will be described in further detail later with reference toFIG.11.

Each of the second connection lines CL2may extend in the second direction (for example, ±y direction) to electrically connect the second main conductive line MCL2to the second auxiliary conductive line ACL2or electrically connect the second auxiliary conductive lines ACL2electrically connected to different auxiliary pixel circuits PCa to one another.

In other words, some or a part of the second connection lines CL2may electrically connect the second main conductive line MCL2to the second auxiliary conductive line ACL2. Some others of the second connection lines CL2may electrically connect the second auxiliary conductive lines ACL2electrically connected to different auxiliary pixel circuits PCa, to one another.

For example, as illustrated inFIG.7, a 2-1stconnection line CL2a, which is one of the second connection lines CL2, may electrically connect the second main conductive line MCL2to the 2-1stauxiliary conductive line ACL2a. A 2-2ndconnection line CL2b, which is another one of the second connection lines CL2, may electrically connect the 2-1stauxiliary conductive line ACL2ato the 2-2ndauxiliary conductive line ACL2b.

The second main conductive line MCL2and the second auxiliary conductive line ACL2that are electrically connected to each other via the second connection line CL2, from among the second main conductive lines MCL2and the second auxiliary conductive lines ACL2, may be apart from each other in the second direction (for example, ±y direction). The second auxiliary conductive lines ACL2electrically connected to each other via the second connection line CL2, from among the second auxiliary conductive lines ACL2, may be apart from each other in the second direction (for example, ±y direction). The transmission area TA may be between the second main conductive line MCL2and the second auxiliary conductive line ACL2that are apart from each other in the second direction (for example, ±y direction). The transmission area TA may be arranged or disposed between the second auxiliary conductive lines ACL2that are apart from each other in the second direction (for example, ±y direction).

For example, as shown inFIG.7, the second main conductive line MCL2and the 2-1stauxiliary conductive line ACL2a, and the 2-1stauxiliary conductive line ACL2aand the 2-2ndauxiliary conductive line ACL2bmay be each spaced apart from each other in the second direction (for example, ±y direction). The transmission area TA may be between the second main conductive line MCL2and the 2-1stauxiliary conductive line ACL2aand between the 2-1stauxiliary conductive line ACL2athe 2-2ndauxiliary conductive line ACL2b.

As described above, in case that the second main conductive line MCL2and the second auxiliary conductive line ACL2that are apart from each other in the second direction (for example, ±y direction) are electrically connected to each other via the second connection line CL2, and the second auxiliary conductive lines ACL2that are apart from each other in the second direction (for example, ±y direction) are electrically connected to each other via the second connection line CL, an electrical signal supplied a pad or a voltage wiring may be transferred to each of the main pixel circuits PCm and the auxiliary pixel circuits PCa arranged or disposed in the second direction (for example, ±y direction).

As illustrated inFIG.1, the main display area MDA may surround the component area CA. The second main conductive lines MCL2that are apart from each other by the component area CA in the second direction (for example, ±y direction) may be electrically connected to each other via the second connection lines CL2and the second auxiliary conductive lines ACL2.

According to an embodiment, the second connection line CL2and the second main conductive line MCL2may be electrically connected to each other via a second contact plug CP2. The second connection line CL2and the second auxiliary conductive line ACL2may be electrically connected to each other via the second contact plug CP2.

For example, as illustrated inFIG.7, the 2-1stconnection line CL2aand the second main conductive line MCL2may be electrically connected to each other via a 2-1stcontact plug CP2a, and the 2-1stconnection line CL2aand the 2-1stauxiliary conductive line ACL2amay be electrically connected to each other via a 2-2ndcontact plug CP2b. The 2-2ndconnection line CL2band the 2-1stauxiliary conductive line ACL2amay be electrically connected to each other via a 2-3rdcontact plug CP2c, and the 2-2ndconnection line CL2band the 2-2ndauxiliary conductive line ACL2bmay be electrically connected to each other via a 2-4thcontact plug CP2d.

As illustrated inFIG.8to be described later, a portion of the second connection line CL2may be buried in a contact hole formed in an insulating layer. The portion of the second connection line CL2buried in the contact hole may be referred to as the second contact plug CP2. In other words, the second connection line CL2and the second contact plug CP2may be a single body.

As illustrated inFIG.9to be described later, in case that the second main conductive line MCL2, the second auxiliary conductive line ACL2, and the second connection line CL2are arranged or disposed in a same layer, the second contact plug CP2may be omitted.

According to an embodiment, the second connection line CL2may include a TCO. For example, the second connection line CL2may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

According to an embodiment, as illustrated inFIG.7, each of the second connection lines CL2may at least partially overlap the transmission area TA. As described above, the second connection line CL2may include a transparent conductive material having high transmittance, and thus, even in case that the second connection line CL2is arranged or disposed to at least partially overlap the transmission area TA, transmittance of the transmission area TA may be ensured.

FIG.8is a schematic cross-sectional view of a portion ofFIG.7taken along line III-III′ and line IV-IV′. InFIG.8, like reference numerals as those ofFIGS.5and6denote like elements, and thus, repeated description thereof will be omitted.

Referring toFIG.8, the third conductive layer may include the first electrode E1, the second main conductive line MCL2, and the second auxiliary conductive line ACL2(FIG.7). In other words, the first electrode E1, the second main conductive line MCL2, and the second auxiliary conductive line ACL2may be arranged or disposed on an upper surface of the interlayer insulating layer117.FIG.8illustrates, as an example, the 2-1stauxiliary conductive line ACL2aand the 2-2ndauxiliary conductive line ACL2bfrom among the second auxiliary conductive lines ACL2.

A sixth conductive layer may be further arranged or disposed on the second planarization layer119b. The sixth conductive layer may include a TCO. For example, the sixth conductive layer may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

The sixth conductive layer may include the second connection line CL2.FIG.8illustrates, as an example, the 2-1stconnection line CL2aand the 2-2ndconnection line CL2bfrom among the second connection lines CL2.

The second connection line CL2may be electrically connected to the second main conductive line MCL2and/or the second auxiliary conductive line ACL2via second contact holes formed in the first planarization layer119aand the second planarization layer119b. Portions of the second connection line CL2may be respectively buried in the second contact holes, and the portions of the second connection line CL2respectively buried in the second contact holes may be referred to as the second contact plugs CP2(FIG.7). In other words, the second connection line CL2and the second contact plug CP2may be integrated.

For example, a 2-1stcontact hole CNT2a, a 2-2ndcontact hole CNT2b, a 2-3rdcontact hole CNT2c, and a 2-4thcontact hole CNT2dmay be formed in the first planarization layer119aand the second planarization layer119b.

Portions of the 2-1stconnection line CL2amay be respectively buried in the 2-1stcontact hole CNT2aand the 2-2ndcontact hole CNT2b. A portion of the 2-1stconnection line CL2aburied in the 2-1stcontact hole CNT2amay be referred to as the 2-1stcontact plug CP2a, and a portion of the 2-1stconnection line CL2aburied in the 2-2ndcontact hole CNT2bmay be referred to as the 2-2ndcontact plug CP2b. The 2-1stconnection line CL2a, the 2-1stcontact plug CP2a, and the 2-2ndcontact plug CP2bmay be integrated.

A portion of the 2-2ndconnection line CL2bmay be buried in each of the 2-3rdcontact hole CNT2cand the 2-4thcontact hole CNT2d. The portion of the 2-2ndconnection line CL2bburied in the 2-3rdcontact hole CNT2cmay be referred to as the 2-3rdcontact plug CP2c, and the portion of the 2-2ndconnection line CL2bburied in the 2-4thcontact hole CNT2dmay be referred to as the 2-4thcontact plug CP2d. The 2-2ndconnection line CL2b, the 2-3rdcontact plug CP2c, and the 2-4thcontact plug CP2dmay be integrated.

As a result, the 2-1stconnection line CL2amay be electrically connected to the second main conductive line MCL2via the 2-1stcontact plug CP2a, and electrically connected to the 2-1stauxiliary conductive line ACL2avia the 2-2ndcontact plug CP2b. The 2-2ndconnection line CL2bmay be electrically connected to the 2-1stauxiliary conductive line ACL2avia the 2-3rdcontact plug CP2c, and electrically connected to the 2-2ndauxiliary conductive line ACL2bvia the 2-4thcontact plug CP2d.

FIG.9is a schematic cross-sectional view of a portion ofFIG.7taken along line III-III′ and line IV-IV′.FIG.9is a modified embodiment ofFIG.8, and is different in structures of the second main conductive line MCL2and the second auxiliary conductive line ACL2. Hereinafter, repeated details may be referred to the description with reference toFIG.8, and description will focus on the difference.

Referring toFIG.9, unlikeFIG.8, the second main conductive lines MCL2and the second auxiliary conductive line ACL (FIG.7) may be arranged or disposed in a same layer as the second connection line CL2(FIG.7). However, a material included in the second connection line CL2may be different from materials respectively included in the second main conductive line MCL2and the second auxiliary conductive line ACL2.

As described above with reference toFIG.5, the fifth conductive layer may be arranged or disposed on the second planarization layer119b, and the fifth conductive layer may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the above material. The fifth conductive layer may include the second main conductive line MCL2and the second auxiliary conductive line ACL2.

As described above with reference toFIG.8, the sixth conductive layer may be further arranged or disposed on the second planarization layer119b. The sixth conductive layer may include a TCO. For example, the sixth conductive layer may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The sixth conductive layer may include the second connection line CL2.

According to an embodiment, an end of the second connection line CL2may cover or overlap an end of the second main conductive line MCL2, and the other end of the second connection line CL2may cover or overlap an end of the second auxiliary conductive line ACL2.

For example, as illustrated inFIG.9, an end of the 2-1stconnection line CL2amay cover or overlap the end of the second main conductive line MCL2, and the other end of the 2-1stconnection line CL2amay cover or overlap an end of the 2-1stauxiliary conductive line ACL2a. An end of the 2-2ndconnection line CL2bmay cover or overlap the end of the 2-1stauxiliary conductive line ACL2a, and the other end of the 2-2ndconnection line CL2bmay cover or overlap an end of the 2-2ndauxiliary conductive line ACL2b.

As described above, in case that the second main conductive line MCL2and the second auxiliary conductive line ACL2are arranged or disposed in a same layer as the second connection line CL2, the second contact plugs CP2illustrated inFIGS.7and8may be omitted.

FIG.10is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

Referring toFIG.10, a pixel PX may include a pixel circuit PC and an organic light-emitting diode OLED electrically connected to the pixel circuit PC.

For example, as illustrated inFIG.10, the pixel circuit PC may include first through seventh transistors T1through T7and a storage capacitor Cst. The first to seventh transistors T1through T7and the storage capacitor Cst may be electrically connected to first through third scan lines SL, SL−1, and SL+1 respectively that transmit first through third scan signals Sn, Sn−1, and Sn+1, a data line DL to transmit a data voltage Dm, an emission control line EL to transmit an emission control signal En, and a driving voltage line PL to transmit a driving voltage ELVDD, an initialization voltage line VL to transmit an initialization voltage Vint, and a common electrode to which a common voltage ELVSS may be applied.

The first transistor T1may include a driving transistor having a drain current, the amplitude of which is determined according to a gate-source voltage, and the second through seventh transistors T2through T7may include switching transistors turned on or off according to a gate-source voltage, substantially, a gate voltage. The first through seventh transistors T1through T7may include thin-film transistors.

The first transistor T1may be referred to as a driving transistor, the second transistor T2may be referred to as a scan transistor, the third transistor T3may be referred to as a compensation transistor, and the fourth transistor T4may be referred to as a gate initialization transistor, and the fifth transistor T5may be referred to as a first emission control transistor, the sixth transistor T6may be referred to as a second emission control transistor, and the seventh transistor T7may be referred to as an anode initialization transistor.

The storage capacitor Cst may be electrically connected between the driving voltage line PL and a gate of the driving transistor T1. The storage capacitor Cst may have the upper electrode CE2electrically connected to the driving voltage line PL and the lower electrode CE1electrically connected to the gate of the driving transistor T1.

The driving transistor T1may control amplitude of the driving current IOLEDflowing from the driving voltage line PL to the organic light-emitting diode OLED according to a gate-source voltage. The driving transistor T1may include the gate electrically connected to the lower electrode CE1of the storage capacitor Cst, a source electrically connected to the driving voltage line PL via the first emission control transistor T5, and a drain electrically connected to the organic light-emitting diode OLED via the second emission control transistor T6.

The driving transistor T1may output the driving current IOLEDto the organic light-emitting diode OLED according to the gate-source voltage. The amplitude of the driving current IOLEDmay be determined based on a difference between the gate-source voltage and a threshold voltage of the driving transistor T1. The organic light-emitting diode OLED may receive the driving current IOLEDfrom the driving transistor T1and emit light at a brightness according to the amplitude of the driving current IOLED.

The scan transistor T2may transfer the data voltage Dm to the source of the driving transistor T1in response to the first scan signal Sn. The scan transistor T2may have a gate electrically connected to the first scan line SL, a source electrically connected to the data line DL, and a drain electrically connected to the source of the driving transistor T1.

The compensation transistor T3may be electrically connected in series between the drain and the gate of the driving transistor T1, and electrically connect the drain and the gate of the driving transistor T1to each other in response to the first scan signal Sn. The compensation transistor T3may have a gate electrically connected to the first scan line SL, a source electrically connected to the drain of the driving transistor T1, and a drain electrically connected to the gate of the driving transistor T1.FIG.10illustrates that the compensation transistor T3may include a single transistor, but the compensation transistor T3may include two transistors electrically connected in series with each other.

The gate initialization transistor T4may apply an initialization voltage Vint to the gate of the driving transistor T1in response to the second scan signal Sn−1. The gate initialization transistor T4may have a gate electrically connected to the second scan line SL−1, a source electrically connected to the gate of the driving transistor T1, and a drain electrically connected to the initialization voltage line VL. InFIG.10, the gate initialization transistor T4is illustrated to include a single transistor, but the gate initialization transistor T4may include two transistors electrically connected in series with each other.

The anode initialization transistor T7may apply the initialization voltage Vint to an anode of the organic light-emitting diode OLED in response to the third scan signal Sn+1. The anode initialization transistor T7may have a gate electrically connected to the third scan line SL+1, a source electrically connected to the anode of the organic light-emitting diode OLED, and a drain electrically connected to the initialization voltage line VL.

The first emission control transistor T5may electrically connect the driving voltage line PL and the source of the driving transistor T1to each other in response to the emission control signal En. The first emission control transistor T5may have a gate electrically connected to the emission control line EL, a source electrically connected to the driving voltage line PL, and a drain electrically connected to the source of the driving transistor T1.

The second emission control transistor T6may electrically connect the drain of the driving transistor T1and the anode of the organic light-emitting diode OLED to each other in response to the emission control signal En. The second emission control transistor T6may have a gate electrically connected to the emission control line EL, a source electrically connected to the drain of the driving transistor T1, and a drain electrically connected to the anode of the organic light-emitting diode OLED.

The second scan signal Sn−1 may be substantially synchronized with the first scan signal Sn of a previous row. The third scan signal Sn+1 may be substantially synchronized with the first scan signal Sn. According to another example, the third scan signal Sn+1 may be substantially synchronized with the first scan signal Sn of a next row.

In an embodiment, the first through seventh transistors T1through T7may include a semiconductor layer including silicon. For example, the first through seventh transistors T1through T7may include a semiconductor layer including low-temperature polysilicon (LTPS). Polysilicon materials have high electron mobility (more than about 100 cm2/Vs), and thus low energy consumption and excellent reliability. As another example, the semiconductor layers of the first through seventh transistors T1through T7may include an oxide of at least one material from among indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer A may include an InSnZnO (ITZO) semiconductor layer, an InGaZnO (IGZO) semiconductor layer, or the like within the spirit and the scope of the disclosure. As another example, some or a part of the semiconductor layers of the first through seventh transistors T1through T7may include LTPS, and some or a part of the semiconductor layers may include an oxide semiconductor (IGZO, etc.).

Hereinafter, a detailed operation process of a pixel PX of a display apparatus according to an embodiment will be described in detail. As illustrated inFIG.5, it is assumed that the first through seventh transistors T1through T7are p-type metal-oxide-semiconductor field effect transistors (MOSFETs).

First, in case that an emission control signal En of a high level is received, the first emission control transistor T5and the second emission control transistor T6are turned off, and the driving transistor T1stops outputting of a driving current IOLED, and the organic light-emitting diode OLED stops emitting light.

Thereafter, during a gate initialization period in which the second scan signal Sn−1 of a low level is received, the gate initialization transistor T4is turned on, and the initialization voltage Vint is applied to the gate of the driving transistor T1, for example, the lower electrode CE1of the storage capacitor Cst. A difference between the driving voltage ELVDD and the initialization voltage Vint (ELVDD-Vint) may be stored in the storage capacitor Cst.

During a data write period in which the first scan signal Sn of a low level is received, the scan transistor T2and the compensation transistor T3are turned on, and the data voltage Dm is received by the source of the driving transistor T1. Here, the driving transistor T1is diode-connected by the compensation transistor T3, and is biased in a forward direction. A gate voltage of the driving transistor T1rises at the initialization voltage Vint. In case that the gate voltage of the driving transistor T1is equal to a data compensation voltage Dm−|Vth| obtained by subtracting a threshold voltage Vth of the driving transistor T1from the data voltage Dm, the driving transistor T1is turned off, and the increase in the gate voltage of the driving transistor T1is stopped. Accordingly, the difference between the driving voltage ELVDD and the data compensation voltage (Dm−|Vth|) (ELVDD−Dm+|Vth|) is stored in the storage capacitor Cst.

During an anode initialization period in which the third scan signal Sn+1 of a low level is received, the anode initialization transistor T7is turned on, and the initialization voltage Vint is applied to the anode of the organic light-emitting diode OLED. By completely preventing light emission from the organic light-emitting diode OLED by applying the initialization voltage Vint to the anode of the organic light-emitting diode OLED, slight light emission from the organic light-emitting diode OLED occurring despite receiving the data voltage Dm corresponding to black gradation in a next frame may be prevented.

The first scan signal Sn and the third scan signal Sn+1 may be substantially synchronized with each other, and, the data write period and the anode initialization period may be the same period.

In case that the emission control signal En of a low level is received, the first emission control transistor T5and the second emission control transistor T6may be turned on, and the driving transistor T1may output a driving current IOLEDcorresponding to a voltage obtained by subtracting the threshold voltage |Vth| of the driving transistor T1from a source-gate voltage (ELVDD−Dm+|Vth|) of the driving transistor T1stored in the storage capacitor Cst, and the organic light-emitting diode OLED may emit light at a luminance corresponding to the amplitude of the driving current IOLED.

WhileFIG.10describes the pixel circuit PC including seven thin-film transistors and one storage capacitor, the disclosure is not limited thereto. For example, the pixel circuit PC may include two or more transistors and/or two or more storage capacitors. According to an embodiment, the pixel circuit PC may include two transistors and one storage capacitor.

FIG.11is a schematic enlarged plan view of a portion of a display apparatus according to an embodiment.FIG.12is a schematic plan view of a first connection line and a second connection line according to an embodiment.FIG.13is a schematic cross-sectional view of a portion ofFIG.11taken along line V-V′ and line VI-VI′.FIG.11is a modified embodiment ofFIGS.4and7, and may be different from embodiments ofFIGS.4and7in structures of a first main conductive line, a first connection line, a first auxiliary conductive line, a second main conductive line, a second connection line, and a second auxiliary conductive line. Hereinafter, repeated details may be referred to the description provided with reference toFIGS.4and7, and description will focus on the difference.

Referring toFIG.11, the main pixel circuit PCm arranged or disposed in the main display area MDA and the auxiliary pixel circuit PCa arranged or disposed in the auxiliary display area ADA may include the pixel circuit PC illustrated inFIG.10.

Accordingly, the first main conductive line MCL1illustrated inFIG.4may include a first main scan line SL-1m, a second main scan line SLm, and a main emission control line ELm. As a third main scan line may correspond to the first main scan line SL-1mor the first main scan line SL-1min a next row, the third main scan line is omitted inFIG.11. Each of the first main scan line SL-1m, the second main scan line SLm, and the main emission control line ELm may respectively extend in the first direction (for example, ±x direction) and be electrically connected to the main pixel circuits PCm located or disposed in a same row.

The first auxiliary conductive line ACL1illustrated inFIG.4may include a first auxiliary scan line SL-1a, a second auxiliary scan line SLa, and an auxiliary emission control line ELa. As a third auxiliary scan line may correspond to the first auxiliary scan line SL-1aor the first auxiliary scan line SL-1ain a next row, the third auxiliary scan line is omitted inFIG.11. The first auxiliary scan line SL-1a, the second auxiliary scan line SLa, and the auxiliary emission control line ELa may respectively extend in the first direction (for example, ±x direction) and be electrically connected to the auxiliary pixel circuit PCa.

The first connection line CL1illustrated inFIG.4may include a 1-1stconnection line CL1-1, a 1-2ndconnection line CL1-2, and a 1-3rdconnection line CL1-3. Each of the 1-1stconnection lines CL1-1may extend in the first direction (for example, ±x direction) to electrically connect the first main scan line SL-1mto the first auxiliary scan line SL-1aor electrically connect the first auxiliary scan lines SL-1aelectrically connected to different auxiliary pixel circuits PCa, to one another. Each of the 1-2ndelectrically connection lines CL1-2may extend in the first direction (for example, ±x direction) to electrically connect the second main scan line SLm to the second auxiliary scan line SLa or electrically connect the second auxiliary scan lines SLa electrically connected to different auxiliary pixel circuits PCa, to one another. Each of the 1-3rdconnection lines CL1-3may extend in the first direction (for example, ±x direction) to electrically connect the main emission control line ELm to the auxiliary emission control line ELa, and electrically connect the auxiliary emission control lines ELa electrically connected to different auxiliary pixel circuits PCa, to one another.

According to an embodiment, as illustrated inFIG.12, the first connection lines CL1may be apart from each other in the first direction (for example, ±x direction). In other words, a substantially planar shape of each of the first connection lines CL1may be an island shape. The 1-1stconnection lines CL1-1may be apart from each other in the first direction (for example, ±x direction), and the 1-2ndconnection lines CL1-2may be apart from each other in the first direction (for example, ±x direction), and the 1-3rdconnection lines CL1-3may be apart from each other in the first direction (for example, ±x direction). In other words, a substantially planar shape of each of the 1-1stconnection lines CL1-1, the 1-2ndconnection lines CL1-2, and the 1-3rdconnection lines CL1-3be an island shape.

InFIG.12, the first connection lines CL1that are apart from each other in the first direction (for example, ±x direction) are illustrated, but in an embodiment, the first connection lines CL1may continuously extend in the first direction (for example, ±x direction) in the component area CA. This will be described later inFIGS.14and15.

According to an embodiment, the 1-1stconnection line CL1-1and the first main scan line SL-1mmay be electrically connected to each other via the first contact plug CP1, and the 1-1stconnection line CL-1and the first auxiliary scan line SL-1amay be electrically connected to each other via the first contact plug CP1. The 1-2ndconnection line CL1-2and the second main scan line SLm may be electrically connected to each other via the first contact plug CP1, and the 1-2ndconnection line CL1-2and the second auxiliary scan line SLa may be electrically connected to each other via the first contact plug CP1. The 1-3rdconnection line CL1-3and the main emission control line ELm may be electrically connected to each other via the first contact plug CP1, and the 1-3rdconnection line CL1-3and the auxiliary emission control line ELa may be electrically connected to each other via the first contact plug CP1.

As illustrated inFIG.13, first contact holes CNT1may be formed in the second gate insulating layer115, the interlayer insulating layer117, and the first planarization layer119a. Portions of the first connection line CL1may be respectively buried in the first contact holes CNT1. The portions of the first connection lines CL1respectively buried in the first contact holes CNT1may be referred to as the first contact plugs CP1. The first connection line CL1and the first contact plugs CP1may be integrated.

The second main conductive line MCL2illustrated inFIG.7may include a main data line DLm and a main driving voltage line PLm. The main data line DLm and the main driving voltage line PLm may respectively extend in the second direction (for example, ±y direction) to be electrically connected to the main pixel circuits PCm located or disposed in a same column.

The second auxiliary conductive line ACL2illustrated inFIG.7may include an auxiliary data line DLa and an auxiliary driving voltage line PLa. The auxiliary data line DLa and the auxiliary driving voltage line PLa may respectively extend in the second direction (for example, ±y direction) to be electrically connected to the auxiliary pixel circuit PCa.

The second connection line CL2illustrated inFIG.7may include a 2-1stconnection line CL2-1and a 2-2ndconnection line CL2-2. The 2-1stconnection lines CL2-1may respectively extend in the second direction (for example, ±y direction) to electrically connect the main data line DLm to the auxiliary data line DLa, and connect the auxiliary data lines DLa electrically connected to different auxiliary pixel circuits PCa to one another. The 2-2ndconnection lines CL2-2may respectively extend in the second direction (for example, ±y direction) to electrically connect the main driving voltage line PLm to the auxiliary driving voltage line PLa, and electrically connect the auxiliary driving voltage lines PLa electrically connected to different auxiliary pixel circuits PCa to one another.

According to an embodiment, as illustrated inFIG.12, the second connection lines CL2may be apart from each other in the second direction (for example, ±y direction). In other words, a substantially planar shape of each of the second connection lines CL2may be an island shape. The 2-1stconnection lines CL2-1may be apart from each other in the second direction (for example, ±y direction), and the 2-2ndconnection line CL2-2may be apart from each other in the second direction (for example, ±y direction). In other words, a substantially planar shape of each of the 2-1stconnection lines CL2-1and the 2-2ndconnection lines CL2-2may be an island shape.

InFIG.12, the second connection lines CL2that are apart from each other in the second direction (for example, ±y direction) are illustrated, but in an embodiment, the second connection lines CL2may continuously extend in the second direction (for example, ±y direction) in the component area CA. This will be described later inFIGS.16and17.

According to an embodiment, the 2-1stconnection line CL2-1and the main data line DLm may be electrically connected to each other via the second contact plug CP2, and the 2-1stconnection line CL2-1and the auxiliary data line DLa may be electrically connected to each other via the second contact plug CP2. The 2-2ndconnection line CL2-2and the main driving voltage line PLm may be electrically connected to each other via the second contact plug CP2, and the 2-2ndconnection line CL2-2and the auxiliary driving voltage line PLa may be electrically connected to each other via the second contact plug CP2.

As illustrated inFIG.13, second contact holes CNT2may be formed in the first planarization layer119aand the second planarization layer119b. Portions of the second connection line CL2may be respectively buried in the second contact holes CNT2. The portions of the second connection lines CL2respectively buried in the second contact holes CNT2may be referred to as the second contact plugs CP2. The second connection line CL2and the second contact plugs CP2may be a single body.

FIG.14is a schematic enlarged plan view of a region of a display apparatus according to an embodiment.FIG.15is a schematic cross-sectional view of a portion ofFIG.14taken along line VII-VII′.FIGS.14and15are respectively a modified embodiment ofFIGS.4and5, and may be different from embodiment ofFIGS.4and5in a structure of a first connection line. Hereinafter, repeated details may be referred to the description provided with reference toFIGS.4and5, and description will focus on the difference.

Referring toFIGS.14and15, unlike the first connection line CL1illustrated inFIGS.4and5, a first connection line CL1′ may extend and be arranged or disposed in the first direction (for example, ±x direction) in the component area CA.

A portion of the first connection line CL1′ may overlap the transmission area TA, and another portion of the first connection line CL1′ may overlap the auxiliary display area ADA. In other words, a portion of the first connection line CL1′ may overlap the transmission area TA, and another portion of the first connection line CL1′ may overlap the auxiliary pixel circuit PCa. A portion of the first connection line CL1′ may overlap the transmission area TA, and another portion of the first connection line CL1′ may overlap the first auxiliary conductive line ACL1.

As the first connection line CL1′ may extend in the first direction (for example, ±x direction) in the component area CA, the first connection line CL1′ may electrically connect the first main conductive line MCL1to the first auxiliary conductive lines ACL1arranged or disposed in the first direction (for example, ±x direction).

For example, as illustrated inFIG.14, the first connection line CL1′ may electrically connect the first main conductive line MCL1, the 1-1stauxiliary conductive line ACL1a, the 1-2ndauxiliary conductive line ACL1b, and the 1-3rdauxiliary conductive line ACL1cto one another.

According to an embodiment, the first connection line CL1′ and the first main conductive line MCL1may be electrically connected to each other via a first contact plug CP1′. The first connection line CL1′ and the first auxiliary conductive line ACL1may be electrically connected to each other via the first contact plug CP1′.

For example, as illustrated inFIG.14, the first connection line CL1′ and the first main conductive line MCL1may be electrically connected to each other via a 1-1stcontact plug CP1′a, and the first connection line CL1′ and the 1-1stauxiliary conductive line ACL1amay be electrically connected to each other via a 1-2ndcontact plug CP1′b, and the first connection line CL1′ and the 1-2ndauxiliary conductive line ACL1bmay be electrically connected to each other via a 1-3thcontact plug CP1′c, and the first connection line CL1′ and the 1-3thauxiliary conductive line ACL1cmay be electrically connected to each other via a 1-4thcontact plug CP1′d.

As such, in case that the first connection line CL1′ extends in the component area CA in the first direction (for example, ±x direction), at least one first contact plug CP1′ needs to be arranged or disposed per first main conductive line MCL1or first auxiliary conductive line ACL1, and thus, the number of first contact plugs CP1′ may be less than the number of the first contact plugs CP1′ illustrated inFIG.4.

Portions of the first connection line CL1′ may be respectively buried in first contact holes formed in an insulating layer. The portions of the first connection lines CL1respectively buried in the first contact holes may be respectively referred to as the first contact plugs CP1′. For example, the first connection line CL1′ and the first contact plugs CP1′ may be a single body.

For example, as illustrated inFIG.15, a 1-1stcontact hole CNT1′a, a 1-2ndcontact hole CNT1′b′, and a 1-3rdcontact hole CNT1′cmay be formed in the second gate insulating layer115, the interlayer insulating layer117, and the first planarization layer119a. Portions of the first connection line CL1′ may be respectively buried in the 1-1Stcontact hole CNT1′a, the 1-2ndcontact hole CNT1′b, and the 1-3rdcontact hole CNT1′c. A portion of the first connection line CL1′ buried in the 1-1stcontact hole CNT1′amay be referred to as the 1-1stcontact plug CP1′a, a portion of the first connection line CL1′ buried in the 1-2ndcontact hole CNT1′bmay be referred to as the 1-2ndcontact plug CP1′b, and a portion of the first connection line CL1′ buried in the 1-3rdcontact hole CNT1′cmay be referred to as a 1-3rdcontact plug CP1′c. The first connection line CL1′, the 1-1stcontact plug CP1′a, the 1-2ndcontact plug CP1′b, and the 1-3rdcontact plug CP1′cmay be integrated.

FIG.16is a schematic enlarged plan view of a region of a display apparatus according to an embodiment.FIG.17is a schematic cross-sectional view of a portion ofFIG.16taken along line VIII-VIII′.FIGS.16and17are respectively a modified embodiment ofFIGS.7and8, and may be different from embodiment ofFIGS.7and8in a structure of a second connection line. Hereinafter, repeated details may be referred to the description provided with reference toFIGS.7and8, and description will focus on the difference.

Referring toFIGS.16and17, unlike the second connection line CL2illustrated inFIGS.7and8, the second connection line CL2′ may extend and be arranged or disposed in the component area CA in the second direction (for example, ±y direction).

A portion of the second connection line CL2′ may overlap the transmission area TA, and another portion of the second connection line CL2′ may overlap the auxiliary display area ADA. In other words, a portion of the second connection line CL2′ may overlap the transmission area TA, and another portion of the second connection line CL2′ may overlap the auxiliary pixel circuit PCa. A portion of the second connection line CL2′ may overlap the transmission area TA, and another portion of the second connection line CL2′ may overlap the second auxiliary conductive line ACL2.

As the second connection line CL2′ may extend in the component area CA in the second direction (for example, ±y direction), the second connection line CL2′ may electrically connect the second main conductive line MCL2and the second auxiliary conductive lines ACL2that are arranged or disposed in the second direction (for example, ±y direction).

For example, as illustrated inFIG.16, the second connection line CL2′ may electrically connect the second main conductive line MCL2, the 2-1stauxiliary conductive line ACL2a, and the 2-2ndauxiliary conductive line ACL2bto one another.

According to an embodiment, the second connection line CL2′ and the second main conductive line MCL2may be electrically connected to each other via a second contact plug CP2′. The second connection line CL2′ and the second auxiliary conductive line ACL2may be electrically connected to each other via the second contact plug CP2′.

For example, as shown inFIG.16, the second connection line CL2′ and the second main conductive line MCL2may be electrically connected to each other via a 2-1stcontact plug CP2′a, and the second connection line CL2′ and the 2-1stauxiliary conductive line ACL2amay be electrically connected to each other via a 2-2ndcontact plug CP2′b, and the second connection line CL2′ and the 2-2ndauxiliary conductive line ACL2bmay be electrically connected to each other via a 2-3thcontact plug CP2′c.

As described above, in case that the second connection line CL2′ extends in the component area CA in the second direction (for example, ±y direction), at least one second contact plug CP2′ needs to be arranged or disposed per second main conductive line MCL2or second auxiliary conductive line ACL2, and thus, the number of the second contact plugs CP2′ may be less than the number of second contact plugs CP2illustrated inFIG.7.

Portions of the second connection line CL2′ may be respectively buried in second contact holes formed in an insulating layer. The portions of the second connection lines CL2respectively buried in the second contact holes may be respectively referred to as the second contact plugs CP2′. For example, the second connection line CL2′ and the second contact plugs CP2′ may be a single body.

For example, as illustrated inFIG.17, 2-1stcontact holes CNT2′a,2-2ndcontact holes CNT2′b, and 2-3rdcontact holes CNT2′cmay be formed in the first planarization layer119aand the second planarization layer119b. Portions of the second connection line CL2′ may be respectively buried in the 2-1stcontact hole CNT2′a, the 2-2ndcontact hole CNT2′b, and the 2-3rdcontact holes CNT2′c. A portion of the second connection line CL2′ buried in the 2-1stcontact hole CNT2′amay be referred to as the 2-1stcontact plug CP2′a, and a portion of the second connection line CL2′ buried in the 2-2ndcontact hole CNT2′bmay be referred to as the 2-2ndcontact plug CP2′b, and a portion of the second connection line CL2′ buried in the 2-3rdcontact hole CNT2′cmay be referred to as the 2-3rdcontact plug CP2′c. The second connection line CL2′, the 2-1st contact plug CP2′a, the 2-2nd contact plug CP2′b, and the 2-3rd contact plug CP2′cmay be integrated.

FIG.18is a schematic plan view of an auxiliary pixel circuit according to an embodiment.FIG.19is a schematic cross-sectional view of the auxiliary pixel circuit ofFIG.18.

Referring toFIG.18, as described above with reference toFIG.11, the first auxiliary scan line SL-1amay be electrically connected to the first connection line CL1via the first contact plug CP1. The second auxiliary scan line SLa may be electrically connected to the first connection line CL1via the first contact plug CP1. The auxiliary emission control line ELa may be electrically connected to the first connection line CL1via the first contact plug CP1.

Also, the auxiliary data line DLa may be electrically connected to the second connection line CL2via the second contact plug CP2. The auxiliary driving voltage line PLa may be electrically connected to the second connection line CL2via the second contact plug CP2.

The auxiliary display element DEa including the pixel electrode210and the intermediate layer220may be arranged or disposed on the auxiliary pixel circuit PCa. The intermediate layer220may be arranged or disposed in an opening OP formed in the pixel defining layer121to expose at least a portion of the pixel electrode210.

According to an embodiment, the auxiliary display element DEa may overlap at least one of the first contact plug CP1and the second contact plug CP2. In detail, the pixel electrode210of the auxiliary display element DEa may overlap at least one of the first contact plug CP1and the second contact plug CP2. For example, as illustrated inFIG.18, the pixel electrode210may overlap six first contact plugs CP1and four second contact plugs CP2.

As described above, as the pixel electrode210covers or overlaps at least one of the first contact plug CP1and the second contact plug CP2, a change in white angle dependence (WAD) according to a viewing angle may be reduced.

InFIG.18, a substantially planar shape of the pixel electrode210is shown as substantially a square, but the substantially planar shape of the pixel electrode210may have various shapes such as substantially a circle, substantially an ellipse, substantially a polygon, substantially a star shape, or substantially a diamond shape.

Referring toFIG.19, the auxiliary pixel circuit PCa may include a first transistor TFT1, a second transistor TFT2, and a storage capacitor Cst. The auxiliary display element DEa may overlap the first transistor TFT1, the second transistor TFT2, and the storage capacitor Cst. In detail, the pixel electrode210of the auxiliary display element DEa may overlap the first transistor TFT1, the second transistor TFT2, and the storage capacitor Cst. For example, as the pixel electrode210overlaps at least one of the first contact plug CP1and the second contact plug CP2arranged or disposed outside of the auxiliary pixel circuit PCa, the pixel electrode210may also overlap the first transistor TFT1, the second transistor TFT2, and the storage capacitor Cst in the auxiliary pixel circuit PCa.

While a display apparatus has been described above, the disclosure is not limited thereto. For example, a method of manufacturing the display apparatus is also included in the scope of the disclosure.

According to the various embodiments, a display apparatus having an extended display area to display an image also in an area in which a component, which is an electronic element, is arranged or disposed may be provided. However, the scope of the disclosure is not limited by the above-described effects.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.