Patent ID: 12243938

DETAILED DESCRIPTION

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG.1Ais a layout of a semiconductor device100A according to some embodiments of the present disclosure. The layout shows a relationship among electrodes120and122, gate electrodes132and136, and a conductive layer150over a nitride-based semiconductor layer112of the semiconductor device100A. These elements can constitute parts of transistors in the semiconductor device100A. The layout reflects a top view of the semiconductor device100A, which means the layout reflects the electrodes120and122, the gate electrodes132and136, and the conductive layer150are formed as layers over the nitride-based semiconductor layer112and viewed along a direction normal to these layers. More structural details of the semiconductor device100A are provided as follows.

To illustrate,FIG.1BandFIG.1Care cross-sectional views across a line1B-1B′ and a line1C-1C′ of the semiconductor device100A inFIG.1A. The semiconductor device100A further includes a substrate102, a nitride-based semiconductor layer110, p-type doped III-V compound semiconductor layers130,134, passivation layers140,160,164, contact vias170,174, patterned conductive layers172,176, and a protection layer178.

The substrate102may be a semiconductor substrate. The exemplary materials of the substrate102can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI), or other suitable semiconductor materials. In some embodiments, the substrate102can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the substrate102can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The nitride-based semiconductor layer110is disposed over the substrate102. The exemplary materials of the nitride-based semiconductor layer110can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(1-x-y)N where x+y≤1, AlyGa(1-y)N where y≤1. The nitride-based semiconductor layer112is disposed on the nitride-based semiconductor layer110. The exemplary materials of the nitride-based semiconductor layer112can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(1-x-y)N where x+y≤1, AlyGa(1-y)N where y≤1.

The exemplary materials of the nitride-based semiconductor layers110and112are selected such that the nitride-based semiconductor layer112has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer110, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer110is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer112can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers110and112can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device100A is available to include at least one GaN-based high-electron-mobility transistor (HEMT).

In some embodiments, the semiconductor device100A may further include a buffer layer, a nucleation layer, or a combination thereof (not illustrated). The buffer layer can be disposed between the substrate102and the nitride-based semiconductor layer110. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate102and the nitride-based semiconductor layer110, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. The nucleation layer may be formed between the substrate102and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate102and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The p-type doped III-V compound semiconductor layers130and134and the gate electrodes132and136are stacked on the nitride-based semiconductor layer112. The p-type doped III-V compound semiconductor layer130is between the nitride-based semiconductor layer112and the gate electrode132. The p-type doped III-V compound semiconductor layer134is between the nitride-based semiconductor layer112and the gate electrode136. In some embodiments, the semiconductor device100A may further include an optional dielectric layer (not illustrated) between the p-type doped III-V compound semiconductor layers130and134and the gate electrodes132and136.

In the exemplary illustration ofFIGS.1B and1C, the semiconductor device100A is an enhancement mode device, which is in a normally-off state when the gate electrodes132and136are at approximately zero bias. Specifically, the p-type doped III-V compound semiconductor layers130and134may create at least one p-n junction with the nitride-based semiconductor layer112to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding p-type doped III-V compound semiconductor layer130or134has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the semiconductor device100A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrodes132and136or a voltage applied to the gate electrodes132and136is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrodes132and136), the zone of the 2DEG region below the p-type doped III-V compound semiconductor layer130or134is kept blocked, and thus no current flows therethrough. Moreover, by providing the p-type doped III-V compound semiconductor layers130and134, gate leakage current is reduced and an increase in the threshold voltage during the off-state is achieved.

In some embodiments, the p-type doped III-V compound semiconductor layers130and134can be omitted, such that the semiconductor device100A is a depletion-mode device, which means the semiconductor device100A in a normally-on state at zero gate-source voltage.

The exemplary materials of the p-type doped III-V compound semiconductor layers130and134can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer110includes undoped GaN and the nitride-based semiconductor layer112includes AlGaN, and the p-type doped III-V compound semiconductor layers112are p-type GaN layers which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device100A into an off-state condition. In some embodiments, the gate electrodes132and136may include metals or metal compounds. The gate electrodes132and136may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the gate electrodes132and136may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof. In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiOx layer, a SiNx layer, a high-k dielectric material (e.g., HfO2, Al2O3, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, etc), or combinations thereof.

The passivation layer140is disposed over the nitride-based semiconductor layer112. The passivation layer140can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements). The passivation layer140covers a top surface of the nitride-based semiconductor layer112. The passivation layer140covers the p-type doped III-V compound semiconductor layers130and134. The passivation layer140covers the gate electrodes132and136. The exemplary materials of the passivation layer140can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma-enhanced oxide (PEOX), tetraethoxysilane normal abbreviation (TEOS), or combinations thereof. In some embodiments, the passivation layer140can be a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

In some embodiments, the electrode120can serve as a source electrode. In some embodiments, the electrode120can serve as a drain electrode. In some embodiments, the electrode122can serve as a source electrode. In some embodiments, the electrode122can serve as a drain electrode. In some embodiments, each of the electrodes120and122can be called a source/drain (S/D) electrode, which means they can serve as a source electrode or a drain electrode, depending on the device design.

The electrodes120and122are disposed on/over/above the nitride-based semiconductor layer112. The electrodes120and122can be located at two opposite sides of the gate electrodes132and136although other configurations may be used, particularly when plural source, drain, or gate electrodes are employed in the device. The gate electrodes132and136are located between the electrodes120and122. In the exemplary illustration ofFIG.1BandFIG.1C, the electrodes120and122are symmetrical about the gate electrodes132and136therebetween. In some embodiments, the electrodes120and122can be optionally asymmetrical about the gate electrodes132and136therebetween. That is, one of the electrodes120and122may be closer to a middle position of the gate electrodes132and136than another one of the electrodes120and122. The electrodes120and122can penetrate/pass through the passivation layer140to contact the nitride-based semiconductor layer112.

In some embodiments, the electrodes120and122can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the electrodes120and122can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The electrodes120and122may be a single layer, or plural layers of the same or different composition. In some embodiments, the electrodes120and122form ohmic contact with the nitride-based semiconductor layer112. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the electrodes120and122. In some embodiments, each of the electrodes120and122is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The conductive layer150is disposed over the nitride-based semiconductor layer112and the passivation layer140. The conductive layer150includes an electrode portion152and a field plate portion154. The electrode portion152is directly connected to the field plate portion154. The electrode portion152is located between the gate electrodes132and136. The electrode portion152can penetrate/pass through the passivation layer140to make contact with the nitride-based semiconductor layer112. The gate electrodes132and136, the electrodes120and122, and the electrode portion152of the conductive layer150can collectively act as at least one nitride-based/GaN-based HEMT with the 2DEG region, which can be called a nitride-based/GaN-based semiconductor device.

In the exemplary illustration ofFIG.1BandFIG.1C, the gate electrodes132and136are symmetrical about the electrode portion152of the conductive layer150therebetween. In some embodiments, the gate electrodes132and136can be optionally asymmetrical about the electrode portion152of the conductive layer150therebetween. That is, one of the gate electrodes132and136may be closer to the electrode portion152of the conductive layer150than another one of the gate electrodes132and136.

The field plate portion154of the conductive layer150is located over the gate electrodes132and136. The field plate portion154of the conductive layer150can change an electric field distribution of source or drain regions and affect breakdown voltage of the semiconductor device100A. In other words, the field plate portion154can suppress the electric field distribution in desired regions and to reduce its peak value.

The electrode portion152and the field plate portion154are arranged to directly connect to each other such that the manufacturing process of the semiconductor device100A can be simplified. For example, the electrode portion152and the field plate portion154can be formed from the same single conductive layer so the number of the stages of the manufacturing process of the semiconductor device100A decreases.

However, since such a single conductive layer may have large area during a manufacturing stage of a semiconductor device, it would result in a significant stress which induces cracks at underlying element layers or peeling. The cracks as such will negatively affect the electrical properties and reliability of the device. Accordingly, an oversized area issue may occur at such a single conductive layer.

With respect to the oversized area issue, the conductive layer150can be designed as a discontinuous conductive layer for the purpose of avoiding accumulation of stress. Such a configuration can alleviate the afore-mentioned negative effects due to stress. Herein, the phrase “discontinuous conductive layer” means that, the conductive layer150can have at least one aperture/opening such that the conductive layer150has at least one inner boundary/border between the two opposite edges thereof in at least one vertical cross-sectional view of the conductive layer150(e.g., as shown inFIG.1C).

More specifically, as shown inFIG.1A, the conductive layer150can have at least one aperture/opening155. As compared with a continuous conductive layer, the area of the conductive layer150can be reduced by creating the apertures/openings155. As such, the accumulation of the stress in the conductive layer150can be lowered, thereby improving the reliability of the semiconductor device100A.

With creating the apertures/openings155, the conductive layer150can at least have inner sidewalls SW1and SW2. The locations of the inner sidewalls SW1and SW2depend on the locations of the apertures/openings155. For example, the apertures/openings155are located directly over at least one of the gate electrodes132and134, which results in that the inner sidewalls SW1can be located directly over at least one of the gate electrodes132and134. The electrode portion152is formed with the inner sidewall SW2. The field plate portion154is formed with the inner sidewall SW1. The inner sidewalls SW2and SW1of the electrode and field plate portions152and154can face each other.

The inner sidewalls SW1and SW2of the conductive layer150can form a closed loop inner boundary for the conductive layer150. Accordingly, each of the apertures/openings155can serve a closed loop pattern collectively formed by the inner sidewalls SW1and SW2of the conductive layer150. The closed loop apertures/openings155can overlap with the gate electrodes132and136from the top view of the semiconductor device100A. The electrode portion152and the field plate portion154are spaced apart from the closed loop inner boundary. The conductive layer150can further include at least one connection portion156connecting the electrode and field plate portions152and154. The connection portions156are located between the electrode and field plate portions152and154. The connection portions156are located at edges of the electrode and field plate portions152and154. With the connection portions156, the electrode and field plate portions152and154can have substantially the same electric potential when a voltage is applied to the conductive layer150.

With respective the gate electrode132, a vertical projection of at least one portion of a right edge of the gate electrode132on the nitride-based semiconductor layer112is out of a vertical projection of the conductive layer150on the nitride-based semiconductor layer112. A right sidewall of the gate electrode132is located between the inner sidewall SW1of the field plate portion154and the sidewall SW2of the electrode portion152, at least from a top view thereof.

With respective the gate electrode136, a vertical projection of at least one portion of a right edge of the gate electrode136on the nitride-based semiconductor layer112is out of a vertical projection of the conductive layer150on the nitride-based semiconductor layer112. A right sidewall of the gate electrode136is located between the inner sidewall SW1of the field plate portion154and the sidewall SW2of the electrode portion152, at least from a top view thereof.

For each of the gate electrodes132and136, still one edge thereof near the electrode120or122is covered by the field plate portion154of the conductive layer150. The reason is to change the electric field distribution of the corresponding source or drain region. Therefore, lowering the accumulation of the stress in the conductive layer150with the modulation to the electric field distribution remained is achieved.

Each of the apertures/openings155can be formed in a shape of a rectangle. The electrode portion152and the field plate portion154can be regarded as a plurality of strips of the conductive layer150parallel with each other. The strips of the conductive layer150are parallel with the gate electrodes132and134. The strips of the conductive layer150are parallel with the electrodes120and122.

Moreover, as shown inFIG.1C, the inner sidewall SW1of the field plate portion154extends upward at a position directly above the gate electrode132or136. The sidewall SW2of the electrode portion152is spaced apart from the gate electrode132or136. Therefore, the edge of the gate electrode132or136facing the electrode120or122is located directly beneath the field plate portion154of the conductive layer150. Such a configuration is to keep the modulation of the electric field distribution of the corresponding source or drain region.

The exemplary materials of the source and the conductive layer150can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), other suitable conductor materials, or combinations thereof. In some embodiments, the exemplary materials of the conductive layer150can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, the conductive layer150and the electrodes include the same material.

The passivation layer160is disposed on the passivation layer140and the conductive layer150. The passivation layer160covers the electrodes120and122and the conductive layer150. Since the conductive layer150is formed to have the apertures/openings155, the passivation layer160can have at least one portion162penetrating the conductive layer150to make contact with the passivation layer140. The portion162of the passivation layer160is located within the apertures/openings155. The portion162of the passivation layer160is located between the electrode portion152and the field plate portion154of the conductive layer150. In some embodiment, the portion162of the passivation layer160is entirely enclosed/surrounded by the conductive layer150. In some embodiment, the portion162of the passivation layer160is entirely enclosed/surrounded by the electrode portion152, the field plate portion154, and the connection portions156of the conductive layer150. In some embodiments, each of the apertures/openings155is filled with the corresponding portion162. By the configuration, the conductive layer150can be positioned firmly to avoid peeling from the passivation layer140.

The passivation layer160can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the passivation layer160can be formed as being thicker, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer160to remove the excess portions, thereby forming a level top surface. The exemplary materials of the passivation layer160can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, PEOX, TEOS, or combinations thereof. In some embodiments, the passivation layer160is a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

The contact vias170are disposed within the passivation layer160. The contact vias170penetrate the passivation layer160. The contact vias170can extend longitudinally to at least electrically couple with the electrodes120and122and the electrode portion152and the field plate154of the conductive layer150. At least one of the contact vias170can be formed to make contact with the electrode portion152of the conductive layer150and this is electrically couple with the field plate154through the connection portion156. At least one of the contact vias170can form an interface with the electrode portion152, which is higher than a bottom of the inner sidewall SW1of the field plate portion154and is lower than a top of the inner sidewall SW1of the field plate portion154. The exemplary materials of the contact vias170can include, for example but are not limited to, conductive materials, such as metals or alloys.

The patterned conductive layer172is disposed on the passivation layer160and the contact vias170. The patterned conductive layer172is in contact with the contact vias170. The patterned conductive layer172may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer172can form at least one circuit. The exemplary materials of the patterned conductive layer172can include, for example but are not limited to, conductive materials. The patterned conductive layer172may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The passivation layer164is disposed above the passivation layer130and the patterned conductive layer172. The passivation layer164covers the passivation layer160and the patterned conductive layer172. The exemplary materials of the passivation layer164can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof. In some embodiments, the passivation layer164is a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

The contact vias174are disposed within the passivation layer164. The contact vias174penetrate the passivation layer164. The contact vias174can extend longitudinally to at least electrically couple with the patterned conductive layer172. The exemplary materials of the contact vias174can include, for example but are not limited to, conductive materials, such as metals or alloys.

The patterned conductive layer176is disposed on the passivation layer164and the contact vias174. The patterned conductive layer176is in contact with the contact vias174. The patterned conductive layer176may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer176can form at least one circuit. The exemplary materials of the patterned conductive layer176can include, for example but are not limited to, conductive materials. The patterned conductive layer176may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The protection layer178is disposed above the passivation layer164and the patterned conductive layer176. The protection layer178covers the passivation layer164and the patterned conductive layer176. The protection layer178can prevent the patterned conductive layer176from oxidizing. Some portions of the patterned conductive layer176can be exposed through openings in the protection layer178, which are configured to electrically connect to external elements (e.g., an external circuit).

Different stages of a method for manufacturing the semiconductor device100A are shown inFIG.2A,FIG.2B, andFIG.2C, described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring toFIG.2A, a substrate102is provided. Nitride-based semiconductor layers110and112can be formed over the substrate102in sequence by using the above-mentioned deposition techniques. P-type doped III-V compound semiconductor layers130and134and gate electrodes132and136can be formed above the nitride-based semiconductor layer112in sequence by using the deposition techniques and a series of patterning process. In some embodiments, the patterning process can include photolithography, exposure and development, etching, other suitable processes, or combinations thereof. A passivation layer140is formed to cover the p-type doped III-V compound semiconductor layers130and134and the gate electrodes132and136. A portion of the passivation layer140can be removed to expose the nitride-based semiconductor layer112.

Referring toFIG.2B, a blanket conductive layer150′ is formed on the passivation layer140. The blanket conductive layer150′ can span the gate electrodes132and136. The blanket conductive layer150′ can be formed to make contact with the exposed portions of the nitride-based semiconductor layer112.

Referring toFIG.2C, the blanket conductive layer150′ is patterned to form a conductive layer150. The conductive layer150includes an electrode portion152and a field plate portion154connected to each other, as afore-mentioned. The conductive layer150is patterned to have at least one aperture/opening155between the electrode and field plate portions152and154. The apertures/openings155can overlap with a sidewall of the gate electrodes132and136, such that the gate electrodes132and136at least have portions free from coverage of the conductive layer150. Moreover, electrodes120and122can be formed by patterning the blanket conductive layer150′ as well. The formed electrodes120and122are in contact with the nitride-based semiconductor layer112and are separated from the conductive layer150. In some embodiments, patterning the blanket conductive layer150can include a dry etching process, which is advantageous to apply to a thick layer such as the blanket conductive layer150.

In some embodiments, patterning the blanket conductive layer150′ can be performed twice. As shown inFIG.3A, patterning the blanket conductive layer150′ can be performed to form electrodes120and122contact with the nitride-based semiconductor layer112and separated from the conductive layer150. At this stage, the conductive layer150is a solid layer without any aperture/opening. Thereafter, as shown inFIG.3B, the conductive layer150is patterned to form an electrode portion152and a field plate portion154connected to each other, as afore-mentioned. Such a manner can improve the accuracy of formed position of the aperture/opening of the conductive layer150.

FIG.4is a cross-sectional view of a semiconductor device100B according to some embodiments of the present disclosure. In the present embodiment, as shown in the exemplary illustration ofFIG.4, the conductive layer150has oblique sidewalls. More specifically, the electrode portion152and the field plate portion154respectively have inner sidewalls SW1and SW2facing each other. The inner sidewalls SW1and SW2of the electrode portion152and the field plate portion154tilt in opposite directions. The profile of the inner sidewalls SW1and SW2can be achieved by turning the process parameters. The oblique inner sidewalls SW1and SW2can receive more force components from the passivation layer160, which will be advantageous to be positioned firmly and avoid peeling from the passivation layer140. Furthermore, the electrodes120and122can have oblique sidewalls.

FIG.5is a cross-sectional view of a semiconductor device100C according to some embodiments of the present disclosure. In the present embodiment, as shown in the exemplary illustration ofFIG.5, each of the closed loop apertures/openings155of the conductive layer150has a curved boundary. Since the closed loop apertures/openings155can receive a portion of a passivation layer (e.g., the passivation layer160ofFIG.1B), the curved boundary thereof can be advantageous to disperse the stress from the passivation layer.

The above embodiments are provided with respect to the pattern of the conductive layer, and the described manner can be further applied to make the semiconductor device performance improved.

FIG.6Ais a top view of a semiconductor device200A according to some embodiments of the present disclosure. In order to make the description clear, directions D1and D2are labeled inFIG.6A, which are different than each other. For example, the direction D1is perpendicular to the direction D2.

The layout shows a relationship among electrodes226,227, and228, gate electrodes224A and224B, and field plates250A and250B disposed over a nitride-based semiconductor layer212of the semiconductor device200A. These elements can constitute parts of transistors in the semiconductor device200A. The layout reflects a top view of the semiconductor device200A, which means the layout reflects the electrodes226,227, and228, gate electrodes224A and224B, and field plates250A and250B are formed as layers over the nitride-based semiconductor layer212and viewed along a direction normal to these layers. More structural details of the semiconductor device200A are provided as follows.

To illustrate,FIG.6BandFIG.6Care cross-sectional views across a line6B-6B′ and a line6C-6C′ of the semiconductor device200A inFIG.6A. The semiconductor device200A further includes a substrate202, a nitride-based semiconductor layer210, p-type doped III-V compound semiconductor layers222A,222B, passivation layers230,240,242,248, contact vias260,264, patterned conductive layers262,266, and a protection layer268.

The substrate202can applies the configuration identical with or similar to that of the substrate102as afore-mentioned.

The nitride-based semiconductor layers210and212can applies the configuration identical with or similar to that of the substrate102as afore-mentioned. The nitride-based semiconductor layers210and212can collectively have an active portion114and an electrically isolating portion116, as shown inFIG.6A. The electrically isolating portion216is non-semi-conducting. Herein, the term “non-semi-conducting” means the electrically isolating portion216can still provide an electrical isolation property even it is biased. The electrically isolating portion216can enclose/surround the active portion. The active portion214and the electrically isolating portion216form two interfaces I1and I2. The two interfaces I1and I2extend along the direction D1. The two interfaces I1and I2are opposite and thus spaced apart from each other by the active portion214.

In some embodiments, the electrically isolating portion216of the nitride-based semiconductor layers210and212can be doped with ions to achieve the electrically isolating purpose. The ions can include, for example but are not limited to, nitrogen ion, fluorine ion, oxygen ion, argon atom, aluminum atom, or combinations thereof. These dopants can make the electrically isolating portion216have a high resistivity and thus act as an electrically isolating region. The active portion214and the electrically isolating portion216are configured to define a device boundary. Accordingly, the semiconductor device100A is available to include at least one GaN-based HEMT located within the active portion214and surrounded by the electrically isolating portion216.

The p-type doped III-V compound semiconductor layers222A,222B are disposed above the nitride-based semiconductor layer212. The p-type doped III-V compound semiconductor layers222A,222B are located within the active portion214. The p-type doped III-V compound semiconductor layers222A,222B extend along the direction D2. The p-type doped III-V compound semiconductor layers222A,222B are configured to bring the semiconductor device200A into an enhancement mode, as afore-mentioned.

The gate electrodes224A and224B are disposed above the nitride-based semiconductor layer212. The gate electrodes224A and224B are disposed above the p-type doped III-V compound semiconductor layers222A,222B. The gate electrodes224A and224B are located within the active portion214. The gate electrodes224A and224B extend along the direction D2. The gate electrodes224A and224B extend across the interfaces I1and I2such that the gate electrodes224A and224B can extend to the electrically isolating portion216.

The electrodes226,227, and228are disposed above the nitride-based semiconductor layer212. The electrodes226,227, and228are located within the active portion214. The electrodes226,227, and228extend along the direction D2. The electrodes226,227, and228are arranged to be parallel with the gate electrodes224A and224B. Each of the electrodes226,227, and228can serve as a source electrode or a drain electrode, depending on the device design. In some embodiments, at least one of the226,227, and228can serve as a source electrode. In some embodiments, at least one of the226,227, and228can serve as a drain electrode.

The relationship among the electrodes226,227, and228and the gate electrodes224A and224B disposed over the nitride-based semiconductor layer212can applies the relationship identical with or similar to that of embodiments as afore-mentioned. The gate electrodes224A and224B and the electrodes226,227, and228can collectively act as at least one nitride-based/GaN-based HEMT with the 2DEG region, which can be called a nitride-based/GaN-based semiconductor device.

The field plates250A and250B are disposed above the nitride-based semiconductor layer212. The field plates250A and250B are disposed gate electrodes224A and224B. The field plates250A and250B extends along the direction D2. The field plates250A and250B extend across the interfaces I1and I2such that the field plates250A and250B extend to the electrically isolating portion216. The field plates250A and250B can overlap with the gate electrodes224A and224B near the interfaces I1and I2. More specifically, the gate electrodes224A and224B and the field plates250A and250B can horizontally overlap with the interfaces I1and I2. Herein, the “horizontally overlapping” means that: the interface I1or I2can go through the gate electrodes224A and224B and the field plates250A and250along a horizontal direction in the layout of the semiconductor device200A (e.g., the direction D1inFIG.6A). In some embodiments, the overlapped areas among the gate electrodes224A and224B, the field plates250A and250, and the interfaces I1and I2extend along the direction D1. As such, the gate electrode224A has portions near and across the interfaces I1and I2is covered with the field plate250A. The gate electrode224B has portions near and across the interfaces I1and I2is covered with the field plate250B.

Such a configuration is to protect those portions of the gate electrodes224A and224B from damage. The reason is that the formation of the electrically isolating portion216involves an ion implantation process, which might damage those portions of the gate electrodes224A and224B. Specifically, during the ion implantation process, a photoresist layer is formed to cover the gate electrodes224A and224B. The photoresist layer has an edge/a boundary to define the area of the active portion214. Due to process variation, the edge/boundary of the photoresist layer may have the non-uniform thickness which may let the portions of the gate electrodes224A and224B damaged by ion bombardment. Once the portions of the gate electrodes224A and224B are damaged, at least one leakage current flow would tend to occur at there, reducing the performance of the semiconductor device100A.

Therefore, since the portions of the gate electrodes224A and224B near and across the interfaces I1and I2are covered with the field plates250A and250B, the field plates250A and250B can protect the gate electrodes224A and224B from damage of ion bombardment. Accordingly, the occurrence of the leakage current is avoided, improving the performance of the semiconductor device100A.

To further protect the gate electrodes224A and224B, the field plates250A and250B extend to the electrically isolating portion216. In this regard, each of the field plates250A and250B has two opposite end portions to achieve it. For example, the field plate250A has two opposite end portions252A and254A. The end portions252A and254A are directly over the gate electrode224A. The end portions252A and254A can overlap with the electrically isolating portion216, such that the end portions252A and254A are spaced apart by a distance L1greater than a distance L2from the interface I1to the interface12. The interfaces I1and I2are located between two opposite side surfaces of the field plate250A.

The profile of the field plates250A and250B still can keep the modulation to the electric field distribution. For example, the field plate250A has a central portion256A. The central portion256A is located between the end portions252A and254A. The central portion256A is located within the active portion214. The central portion256A of the field plate250A vertically overlaps with the gate electrode224A. Herein, the “vertically overlapping” means that: the central portion256A of the field plate250A is located directly above the gate electrode224A. The coverage of the central portion256A can provide the gate electrode224A with the modulation to the electric field distribution.

Moreover, the gate electrode224A has a portion within the active portion214and is free from coverage of the central portion256A of the field plate250A. The end portions252A and254A can be wider than the central portion256A. Since the central portion256A is narrower than the end portions252A and254A, the end portions252A and254A can be regarded as extending along the direction D1with respect to the central portion256A. The profile of the field plate250A can decrease the area of the field plate250A so as to lower the accumulation of the stress in the field plate250A as afore-described.

In some embodiments, the central portion256A of the field plate250A covers one of the two edges of the gate electrode224A, and each of the end portions252A and254A covers both of the two edges of the gate electrode224A. With the configuration, three technical effects are achieved, including, the protection of the ion bombardment, the modulation to the electric field distribution, and the lowering accumulation of the stress in the field plate.

The field plate250B can apply a profile/configuration the same as the field plate250A, so the relationship between the gate electrode224B and the field plate250B can be identical with or similar to the relationship between the gate electrode224A and the field plate250A. In some embodiments, the field plates250A and250B are symmetrical. For example, the field plates250A and250B can be symmetrical about the electrode227.

Different stages of a method for manufacturing the semiconductor device200A are shown inFIG.7A,FIG.7B,FIG.7C,FIG.7D,FIG.7E, andFIG.7F, described below.

Referring toFIG.7A, a substrate202is provided. Nitride-based semiconductor layers210and212can be formed over the substrate202in sequence by using the above-mentioned deposition techniques. P-type doped III-V compound semiconductor layers222A and222B and gate electrodes224A and224B can be formed above the nitride-based semiconductor layer212in sequence by using the deposition techniques and a series of patterning process. A passivation layer230is formed to cover the p-type doped III-V compound semiconductor layers222A and222B and the gate electrodes224A and224B.

Referring toFIG.7B, a blanket conductive layer270is formed over the passivation layer230. A mask layer272is formed over the blanket conductive layer270. A patterning process can be performed on the blanket conductive layer270using the mask layer272.

Referring toFIG.7C, the blanket conductive layer270is patterned to form field plates250A and250B above the gate electrodes224A and224B. As afore-described, the formed field plates250A and250B can span the gate electrodes224A and224B, respectively, so as to protect the gate electrodes224A and224B from ion bombardment. Thereafter, the mask layer272is removed.

Referring toFIG.7D, a passivation layer240is formed to cover the field plates250A and250B and the passivation layer230. Portions of the passivation layers230and240can be removed to expose the nitride-based semiconductor layer212. Thereafter, electrodes226,227, and228can be formed from a blanket conductive layer by using the deposition techniques and a series of patterning process.

Referring toFIG.7EandFIG.7F, in whichFIG.7Fis a top view corresponding toFIG.7E, a mask layer280is formed over the field plates250A and250B. The mask layer280has opposite edges spaced apart from each other by a distance282less than a length284of each of the field plates250A and250B. In this regard, the distance282and the length284are in a direction that the gate electrodes224A and224B extend along the same. Accordingly, there would be some of the nitride-based semiconductor layers210and212free from coverage of the mask layer280. After the formation of the mask layer280, an ion implantation process is performed on the nitride-based semiconductor layers210and212such that the nitride-based semiconductor layers210and212collectively have an electrically isolating portion216exposed from the mask layer280. As afore-described, even though the mask layer280may have the non-uniform thickness at the edges due to the process variation, the field plate250A and250B can protect gate electrodes224A and224B from unexpected damage of the ion bombardment.

FIG.8is a top view of a semiconductor device200B according to some embodiments of the present disclosure. In the present embodiment, as shown in the exemplary illustration ofFIG.8, a field plate290is formed to replace the field plates250A and250B. The field plate290is formed to have a ring shape by patterning a blanket conductive layer. The field plate290and the gate electrode224A and224B horizontally overlap with the interfaces I1and I2for the purpose of protection of ion bombardment.

Since the field plate290is ring-shaped, some of the gate electrode224A and224B are exposed. The electrode227has a portion free from coverage from the first field plate. The portion of the electrode227is enclosed/surrounded by the ring shape of the field plate290. With this configuration, the field plate290can still provide the modulation to the electric field distribution with the area thereof reduced, so as to lower accumulation of the stress therein.

FIG.9Ais a top view of a semiconductor device200C according to some embodiments of the present disclosure.FIG.9Bis a cross-sectional view across a line9B-9B′ the semiconductor device200C inFIG.9A. In the present embodiment, as shown in the exemplary illustration ofFIGS.9A and9B, a conductive layer292is formed to have an electrode portion294and a field plate portion296, as afore-describe (e.g.,FIG.1A). The electrode portion294can serve as a source or a drain in contact with the nitride-based semiconductor layer212. The field plate portion296can be divided into two portions to cover the gate electrodes224A and224B, respectively.

The electrode portion294and the field plate portion296can be made from the same blanket conductive material by a single patterning process. The electrode portion294and the field plate portion296are physically connected to each other. The conductive layer292can be formed to extend across the interfaces I1and I2to protect the gate electrodes224A and224B. The present embodiment shows the protection to the gate electrode by the field plate is high compatible to the different semiconductor device configurations.

FIG.10is a top view of a semiconductor device200D according to some embodiments of the present disclosure. In the present embodiment, as shown in the exemplary illustration ofFIG.10, the conductive layer292has at least one aperture/opening to decrease the area, so as to lower accumulation of the stress therein. The conductive layer292is formed to extend across the interfaces I1and I2to protect the gate electrode224A and224B. The conductive layer292has a connection portion298between the electrode portion294and the field plate portion296. The connection portion298of the conductive layer292aligns with the interfaces I1and I2. The field plate portion296can be divided into two portions to cover the gate electrodes224A and224B, respectively.

FIG.11is a top view of a semiconductor device200E according to some embodiments of the present disclosure. In the present embodiment, as shown in the exemplary illustration ofFIG.11, the conductive layer292has the electrode portion294. The electrode portion294have top and bottom edges extending toward the gate electrodes224A and224B. The top and bottom edges of the electrode portion294horizontally overlap with the interfaces I1and I2. The top and bottom edges of the electrode portion294extend to cover the gate electrodes224A and224B so as to protect them from ion bombardment. In some embodiments, the semiconductor device200E can further include one or more field plate disposed on the conductive layer292.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms “substantially,” “substantial,” “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to +10% of that numerical value, such as less than or equal to +5%, less than or equal to +4%, less than or equal to +3%, less than or equal to +2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to +0.1%, or less than or equal to +0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.