Patent ID: 12232377

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments. Further, various embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concepts.

Unless otherwise specified, the illustrated embodiments are to be understood as providing illustrative features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements.

When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z-axes, and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Various embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

FIG.1is a plan view showing a display device according to embodiments of the present invention;FIG.2is a plan view for describing circuit boards included in the display device ofFIG.1; andFIG.3is a block diagram for describing an external device electrically connected to the display device ofFIG.1.

Referring toFIGS.1,2, and3, a display device100may include first pad electrodes471, second pad electrodes472, first power circuit boards841, second power circuit boards941, driving circuit boards900, and the like.

The display device100may include: a display area10; a peripheral area20substantially surrounding the display area10; a first pad area61located in one side of the peripheral area20; and a second pad area62located in an opposite side of the peripheral area20. In this case, the peripheral area20may include a first peripheral area21and a second peripheral area22. For example, when viewed in a plan view of the display device100, the first pad area61may be located on an upper portion of the display area10, and the first peripheral area21may be interposed between the display area10and the first pad area61. In addition, the second pad area62may be located on a lower portion of the display area10, and the second peripheral area22may be interposed between the display area10and the second pad area62.

A plurality of sub-pixel areas30may be arranged over the whole display area10in a first direction D1, which is parallel to a top surface of the display device100, and a second direction D2 that is orthogonal to the first direction D1. A sub-pixel SP ofFIG.4may be disposed in each of the sub-pixel areas30, and the sub-pixel SP may include transistors, organic light emitting diodes, and the like. An image may be displayed in the display area10through the sub-pixel SP.

For example, sub-pixels SP may include first, second, and third sub-pixels. The first sub-pixel may include a first organic light emitting diode for emitting a red light, the second sub-pixel may include a second organic light emitting diode for emitting a green light, and the third sub-pixel may include a third organic light emitting diode for emitting a blue light.

The first organic light emitting diode may overlap transistors included in the first sub-pixel, the second organic light emitting diode may overlap transistors included in the second sub-pixel, and the third organic light emitting diode may overlap transistors included in the third sub-pixel. In some embodiments, the first organic light emitting diode may overlap a portion of the transistors included in the first sub-pixel and a portion of transistors included in a sub-pixel that is different from the first sub-pixel, the second organic light emitting diode may overlap a portion of the transistors included in the second sub-pixel and a portion of transistors included in a sub-pixel that is different from the second sub-pixel, and the third organic light emitting diode may overlap a portion of the transistors included in the third sub-pixel and a portion of transistors included in a sub-pixel that is different from the third sub-pixel. For example, the first to third organic light emitting diodes may be arranged by using an RGB stripe scheme in which rectangles having the same size are sequentially arranged, an S-stripe scheme including a blue organic light emitting diode having a relatively large area, a WRGB scheme further including a white organic light emitting diode, a PenTile™ scheme in which RG-GB patterns are repeatedly arranged, or the like.

In addition, the sub-pixel SP may include at least one driving transistor, at least one switching transistor, at least one capacitor, and the like. In the embodiments, the sub-pixel SP may include one driving transistor (e.g., a first transistor TR1ofFIG.4), six switching transistors (e.g., second to seventh transistors TR2, TR3, TR4, TR5, TR6, and TR7ofFIG.4), one storage capacitor (e.g., a storage capacitor CST ofFIG.4), and the like.

However, although the display device100according to the present invention has been described as having a rectangular shape when viewed in a plan view, the shape of the display device100is not limited thereto. For example, the display device100may have a triangular shape, a rhombic shape, a polygonal shape, a circular shape, an elliptical shape, or a track shape when viewed in a plan view.

A plurality of lines may be disposed in the peripheral area20. For example, the lines may include a data signal line, a gate signal line, an emission control signal line, a gate initialization signal line, an initialization voltage line, a first power line, a second power line, and the like. The lines may extend from the peripheral area20to the display area10so as to be electrically connected to the sub-pixels SP. Moreover, a gate driver, a data driver, and the like may be disposed in the peripheral area20.

In the embodiments, a conductive member (e.g., a first extension part of a conductive member360ofFIG.5) may be disposed in the first peripheral area21, and as shown inFIG.1, a first contact hole361formed in a protective insulating layer and a planarization layer, which will be described below, may be located on the conductive member. In other words, the first contact hole361may be located to correspond to the conductive member, and may have a bar shape when viewed in a plan view. In addition, a length of the first contact hole361in the first direction D1 may be substantially equal to a length of the conductive member in the first direction D1. In other words, a portion of a top surface of the conductive member may be exposed through the first contact hole361.

Referring again toFIGS.1to3, the first pad electrodes471may be disposed in the first pad area61, and the second pad electrodes472may be disposed in the second pad area62. Only the first power circuit board841and the second power circuit board941may be electrically connected to the first pad electrodes471, and the first power circuit board841, the second power circuit board941, and the driving circuit board900may be electrically connected to the second pad electrodes472. In other words, the driving circuit board900may not be disposed in the first pad area61, and the first pad electrodes471and the driving circuit board900may not make direct contact with each other. For example, the first power circuit boards841and the second power circuit boards941may be alternately arranged in the first pad area61, and the second power circuit board941, the first power circuit board841, and the driving circuit board900may be alternately arranged in the second pad area62.

An external device101may be electrically connected to the display device100through the first power circuit board841, the second power circuit board941, and the driving circuit board900. For example, one side of each of the first power circuit board841, the second power circuit board941, and the driving circuit board900may make direct contact with the first and second pad electrodes471and472, and an opposite side of each of the first power circuit board841, the second power circuit board941, and the driving circuit board900may make direct contact with the external device101.

In addition, the external device101may generate a data signal, a gate signal, an emission control signal, a gate initialization signal, an initialization voltage, a first power, a second power, and the like. In the embodiments, the data signal, the gate signal, the emission control signal, the gate initialization signal, and the initialization voltage generated from the external device101may be provided to the display device100through the driving circuit board900. The first power generated from the external device101may be provided to the display device100through the first power circuit board841, and the second power generated from the external device101may be provided to the display device100through the second power circuit board941. For example, a voltage level of the first power (e.g., a low power voltage ELVSS ofFIG.4) may be lower than a voltage level of the second power (e.g., a high power voltage ELVDD ofFIG.4).

A driving integrated circuit may be mounted on each of the first power circuit board841, the second power circuit board941, and the driving circuit board900. In other embodiments, the driving integrated circuit may be mounted on the display device100while being adjacent to the first and second pad electrodes471and472, or each of the first power circuit board841, the second power circuit board941, and the driving circuit board900may not include the driving integrated circuit.

FIG.4is a circuit diagram showing a sub-pixel disposed in a sub-pixel area ofFIG.1.

Referring toFIG.4, the display device100may include sub-pixels SP disposed in the sub-pixel areas30, respectively, and the sub-pixel SP may include an organic light emitting diode OLED (e.g., a sub-pixel structure200ofFIG.6), first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7(e.g., a semiconductor element250ofFIG.6), a storage capacitor CST, a high power voltage (ELVDD) line (e.g., a second upper power line740ofFIG.5and a second lower power line950ofFIG.9), a low power voltage (ELVSS) line (e.g., a first upper power line640ofFIG.5and a first lower power line840ofFIG.9), an initialization voltage (VINT) line, a data signal (DATA) line, a gate signal (GW) line, a gate initialization signal (GI) line, an emission control signal (EM) line, a diode initialization signal (GB) line, and the like. As described above, the first transistor TR1may correspond to a driving transistor, and the second to seventh transistors TR2, TR3, TR4, TR5, TR6, and TR7may correspond to switching transistors. Each of the first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7may include a first terminal, a second terminal, a channel, and a gate terminal. In the embodiments, the first terminal may be a source terminal, and the second terminal may be a drain terminal. In some embodiments, the first terminal may be a drain terminal, and the second terminal may be a source terminal.

The organic light emitting diode OLED may output a light based on a driving current ID. The organic light emitting diode OLED may include a first terminal and a second terminal. In the embodiments, the second terminal of the organic light emitting diode OLED may receive a low power voltage ELVSS (e.g., the first power), and the first terminal of the organic light emitting diode OLED may receive a high power voltage ELVDD (e.g., the second power). For example, the first terminal of the organic light emitting diode OLED may be an anode terminal, and the second terminal of the organic light emitting diode OLED may be a cathode terminal. In some embodiments, the first terminal of the organic light emitting diode OLED may be a cathode terminal, and the second terminal of the organic light emitting diode OLED may be an anode terminal. In the embodiments, the anode terminal of the organic light emitting diode OLED may correspond to a lower electrode290ofFIG.6, and the cathode terminal of the organic light emitting diode OLED may correspond to an upper electrode340ofFIG.6.

The first transistor TR1may generate the driving current ID. In the embodiments, the first transistor TR1may operate in a saturation region. In this case, the first transistor TR1may generate the driving current ID based on a voltage difference between the gate terminal and the source terminal of the first transistor TR1. In addition, gray levels may be expressed based on a magnitude of the driving current ID supplied to the organic light emitting diode OLED. In some embodiments, the first transistor TR1may operate in a linear region. In this case, the gray levels may be expressed based on a sum of a time during which the driving current is supplied to the organic light emitting diode OLED within one frame.

The gate terminal of the second transistor TR2may receive a gate signal GW. The first terminal of the second transistor TR2may receive a data signal DATA. The second terminal of the second transistor TR2may be connected to the first terminal of the first transistor TR1. For example, the gate signal GW may be provided from the gate driver, and the gate signal GW may be applied to the gate terminal of the second transistor TR2through the gate signal (GW) line. The second transistor TR2may supply the data signal DATA to the first terminal of the first transistor TR1during an activation period of the gate signal GW. In this case, the second transistor TR2may operate in a linear region.

The gate terminal of the third transistor TR3may receive the gate signal GW. The first terminal of the third transistor TR3may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3may be connected to the second terminal of the first transistor TR1. For example, the gate signal GW may be provided from the gate driver, and the gate signal GW may be applied to the gate terminal of the third transistor TR3through the gate signal (GW) line. The third transistor TR3may connect the gate terminal of the first transistor TR1and the second terminal of the first transistor TR1during the activation period of the gate signal GW.

An input terminal of the initialization voltage line to which an initialization voltage VINT is provided may be connected to the first terminal of the fourth transistor TR4and the first terminal of the seventh transistor TR7, and an output terminal of the initialization voltage line may be connected to the second terminal of the fourth transistor TR4and a first terminal of the storage capacitor CST.

The gate terminal of the fourth transistor TR4may receive a gate initialization signal GI. The first terminal of the fourth transistor TR4may receive the initialization voltage VINT. The second terminal of the fourth transistor TR4may be connected to the gate terminal of the first transistor TR1. The fourth transistor TR4may supply the initialization voltage VINT to the gate terminal of the first transistor TR1during an activation period of the gate initialization signal GI. In this case, the fourth transistor TR4may operate in a linear region. In other words, the fourth transistor TR4may initialize the gate terminal of the first transistor TR1to the initialization voltage VINT during the activation period of the gate initialization signal GI. In the embodiments, the initialization voltage VINT may have a voltage level that is sufficiently lower than a voltage level of the data signal DATA maintained by the storage capacitor CST in a previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1. In other embodiments, the initialization voltage may have a voltage level that is sufficiently higher than the voltage level of the data signal maintained by the storage capacitor in the previous frame, and the initialization voltage may be applied to the gate terminal of the first transistor. In the embodiments, the gate initialization signal GI may be substantially the same as the gate signal GW of one horizontal time before.

The gate terminal of the fifth transistor TR5may receive an emission control signal EM. The first terminal of the fifth transistor TR5may be connected to the high power voltage (ELVDD) line. The second terminal of the fifth transistor TR5may be connected to the first terminal of the first transistor TR1. For example, the emission control signal EM may be provided from an emission control driver, and the emission control signal EM may be applied to the gate terminal of the fifth transistor TR5through the emission control signal (EM) line. The fifth transistor TR5may supply the high power voltage ELVDD to the first terminal of the first transistor TR1during an activation period of the emission control signal EM. On the contrary, the fifth transistor TR5may cut off the supply of the high power voltage ELVDD during an inactivation period of the emission control signal EM. In this case, the fifth transistor TR5may operate in a linear region. Since the fifth transistor TR5supplies the high power voltage ELVDD to the first terminal of the first transistor TR1during the activation period of the emission control signal EM, the first transistor TR1may generate the driving current ID. In addition, since the fifth transistor TR5cuts off the supply of the high power voltage ELVDD during the inactivation period of the emission control signal EM, the data signal DATA supplied to the first terminal of the first transistor TR1may be supplied to the gate terminal of the first transistor TR1.

The gate terminal of the sixth transistor TR6(e.g., the semiconductor element250ofFIG.6) may receive the emission control signal EM. The first terminal of the sixth transistor TR6may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6may be connected to the first terminal of the organic light emitting diode OLED. The sixth transistor TR6may supply the driving current ID generated by the first transistor TR1to the organic light emitting diode OLED during the activation period of the emission control signal EM. In this case, the sixth transistor TR6may operate in a linear region. In other words, since the sixth transistor TR6supplies the driving current ID generated by the first transistor TR1to the organic light emitting diode OLED during the activation period of the emission control signal EM, the organic light emitting diode OLED may output the light. In addition, since the sixth transistor TR6electrically separates the first transistor TR1and the organic light emitting diode OLED from each other during the inactivation period of the emission control signal EM, the data signal DATA supplied to the second terminal of the first transistor TR1(precisely, a data signal that has been subject to threshold voltage compensation) may be supplied to the gate terminal of the first transistor TR1.

The gate terminal of the seventh transistor TR7may receive a diode initialization signal GB. The first terminal of the seventh transistor TR7may receive the initialization voltage VINT. The second terminal of the seventh transistor TR7may be connected to the first terminal of the organic light emitting diode OLED. The seventh transistor TR7may supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during an activation period of the diode initialization signal GB. In this case, the seventh transistor TR7may operate in a linear region. In other words, the seventh transistor TR7may initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB. In some embodiments, the gate initialization signal GI and the diode initialization signal GB may be substantially the same signal.

The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between the high power voltage (ELVDD) line and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power voltage (ELVDD) line. The storage capacitor CST may maintain a voltage level of the gate terminal of the first transistor TR1during an inactivation period of the gate signal GW. The inactivation period of the gate signal GW may include the activation period of the emission control signal EM, and the driving current ID generated by the first transistor TR1may be supplied to the organic light emitting diode OLED during the activation period of the emission control signal EM. Therefore, the driving current ID generated by the first transistor TR1may be supplied to the organic light emitting diode OLED based on the voltage level maintained by the storage capacitor CST.

However, although the sub-pixel SP according to the present invention has been described as including seven transistors and one storage capacitor, the configuration of the present invention is not limited thereto. For example, the sub-pixel SP may have a configuration including at least one transistor and at least one storage capacitor.

FIG.5is a partially enlarged plan view showing a region A ofFIG.1,FIG.6is a cross-sectional view taken along line I-I′ ofFIG.5;FIG.7is a cross-sectional view taken along line II-II′ ofFIG.5; andFIG.8is a cross-sectional view taken along line III-III′ ofFIG.5.

Referring toFIGS.5,6,7, and8, the display device100may further include a substrate110, a buffer layer115, a semiconductor element250, a protective insulating layer400, a first upper power line640, a second upper power line740, upper inspection pads660, a conductive member360, a conductive pattern510, a first connection pattern365, a second connection pattern645, a third connection pattern235, a fourth connection pattern655, a first sub-power line650, a second sub-power line750, a signal line610, a sub-pixel structure200, an upper connection member295, a first electrode pattern305, a pixel defining layer310, an encapsulation substrate450, and the like. In this case, the semiconductor element250may include an active layer130, a gate insulating layer150, a gate electrode170, an interlayer insulating layer190, a source electrode210, and a drain electrode230, and the sub-pixel structure200may include a lower electrode290, a light emitting layer330, and an upper electrode340.

The substrate110including transparent or opaque materials may be provided. The substrate110may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda lime glass substrate, a non-alkali glass substrate, and the like. In some embodiments, the substrate110may be configured as a transparent resin substrate having flexibility. In the embodiments, the substrate110may have a configuration in which a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer are sequentially stacked. The first barrier layer and the second barrier layer may include an inorganic material such as silicon oxide, and may block water and/or moisture penetrating through the first and second organic layers. In addition, the first organic layer an d the second organic layer may include an organic material having flexibility, such as a polyimide-based resin.

Since the display device100includes a display area10in which a plurality of sub-pixel areas30are arranged, a peripheral area20including a first peripheral area21and a second peripheral area22, a first pad area61, and a second pad area62, as shown inFIGS.6,7, and8, the substrate110may also be divided into a display area10in which a plurality of sub-pixel areas30are arranged, a peripheral area20including a first peripheral area21and a second peripheral area22, a first pad area61, and a second pad area62(seeFIG.1).

The buffer layer115may be disposed on the substrate110. The buffer layer115may be dis posed over the whole of the display area10, the peripheral area20, the first pad area61, and the second pad area62on the substrate110. For example, the buffer layer115may prevent metal atoms or impurities from diffusing from the substrate110to the semiconductor element250, and may control a heat transfer rate during a crystallization process for forming the active layer130to obtain a substantially uniform active layer130. In addition, when a surface of the substrate110is not uniform, the buffer layer115may serve to improve flatness of the surface of the substrate110. Depending on a type of the substrate110, at least two buffer layers115may be provided on the substrate110, or the buffer layer115may not be provided. The buffer layer115may include a silicon compound, metal oxide, and the like. The buffer layer115may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), and the like.

The active layer130may be disposed in the sub-pixel area30on the buffer layer115. The active layer130may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon or polysilicon), an organic semiconductor, or the like. The active layer130may include a source region, a drain region, and a channel region located between the source region and the drain region.

The gate insulating layer150may be disposed on the active layer130. The gate insulating layer150may be disposed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the buffer layer115. For example, the gate insulating layer150may sufficiently cover the active layer130on the buffer layer115, and may have a substantially flat top surface without creating a step around the active layer130. In some embodiments, the gate insulating layer150may be disposed along a prof ile of the active layer130with a uniform thickness to cover the active layer130on the buffer layer115. The gate insulating layer150may include a silicon compound, metal oxide, and the like. In other embodiments, the gate insulating layer150may have a multilayer structure having a plurality of insulating layers including mutually different materials, and the insulating layers may have mutually different thicknesses.

The gate electrode170may be disposed in the sub-pixel area30on the gate insulating layer150. The gate electrode170may be disposed on a portion of the gate insulating layer150under which the active layer130is located (e.g., to overlap the channel region of the active layer130). The gate electrode170may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, the gate electrode170may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The second upper power line740may be disposed in the first pad area61and the first peripheral area21on the gate insulating layer150. In the embodiments, the second upper power line740may be located at a lower level than the first upper power line640and the conductive member360, and may be electrically connected to the second power circuit board941disposed in the first pad area61ofFIG.2through the first pad electrodes471. In addition, the second upper power line740may include a first line extension part741, a second line extension part742, and a third line extension part743. For example, the first line extension part741may be located in the first peripheral area21, and may extend in the first direction D1. In other words, the first line extension part741may overlap the first peripheral area21. The second line extension part742may extend from one side of the first line extension part741in a third direction D3 that is a direction from the first peripheral area21to the first pad area61(e.g., a direction opposite to the second direction D2) so as to be located in the first pad area61. In other words, the second line extension part742may protrude from the one side of the first line extension part741in the third direction D3, and may extend in the third direction D3 so as to be electrically connected to the second power circuit board941through the first pad electrodes471. The third line extension part743may extend from an opposite side of the first line extension part741in the second direction D2 that is a direction from the first peripheral area21to the display area10, and may intersect the conductive member360. In other words, the third line extension part743may protrude from the opposite side of the first line extension part741in the second direction D2, and may be located under the conductive member360. Moreover, the first line extension part741, the second line extension part742, and the third line extension part743may be formed integrally with each other.

The second power (e.g., the high power voltage ELVDD ofFIG.4) may be provided to the second upper power line740. The second power may be provided to the lower electrode290through the second upper power line740and the second sub-power line750. The second sub-power line750may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In some embodiments, the second upper power lines740may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

However, although one third line extension part743has been described as protruding from the first line extension part741in the second direction D2 for convenience, the second upper power line740may include one first line extension part741and a plurality of third line extension parts743as shown inFIG.5. In addition, each of the third line extension parts743may be electrically connected to the second sub-power line750in the first peripheral area21, and the second sub-power line750may extend in the second direction D2 and may be disposed in the sub-pixel area30.

The conductive pattern510may be disposed in parallel with the third line extension part743in the first peripheral area21on the gate insulating layer150. In other words, the conductive pattern510may be disposed under the conductive member360, and may intersect the conductive member360. The conductive pattern510may electrically connect the upper inspection pad660and the signal line610through contact holes511and512. The conductive pattern510may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, the conductive pattern510may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses. In the embodiments, the gate electrode170, the conductive pattern510, and the second upper power line740may be located on the same layer.

The interlayer insulating layer190may be disposed on the gate electrode170, the conductive pattern510, and the second upper power line740. The interlayer insulating layer190may be disposed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the gate insulating layer150. In the embodiments, the interlayer insulating layer190may include: a contact hole511that exposes one side of the conductive pattern510; a contact hole512that exposes an opposite side of the conductive pattern510; and a contact hole751that exposes a portion of the third line extension part743that is adjacent to the display area10. For example, the interlayer insulating layer190may sufficiently cover the gate electrode170, the conductive pattern510, and the second upper power line740on the gate insulating layer150, and may have a substantially flat top surface without creating a step around the gate electrode170and the second upper power line740. In some embodiments, the interlayer insulating layer190may be disposed along a profile of the gate electrode170, the conductive pattern510, and the second upper power line740with a uniform thickness to cover the gate electrode170, the conductive pattern510, and the second upper power line740on the gate insulating layer150. The interlayer insulating layer190may include a silicon compound, metal oxide, and the like. In other embodiments, the interlayer insulating layer190may have a multilayer structure having a plurality of insulating layers including mutually different materials, and the insulating layers may have mutually different thicknesses.

The source electrode210and the drain electrode230may be disposed in the sub-pixel area30on the interlayer insulating layer190. The source electrode210may be connected to the source region of the active layer130through a contact hole formed by removing first portions of the gate insulating layer150and the interlayer insulating layer190, and the drain electrode230may be connected to the drain region of the active layer130through a contact hole formed by removing second portions of the gate insulating layer150and the interlayer insulating layer190. Each of the source electrode210and the drain electrode230may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, each of the source electrode210and the drain electrode230may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

Accordingly, the semiconductor element250including the active layer130, the gate insulating layer150, the gate electrode170, the interlayer insulating layer190, the source electrode210, and the drain electrode230may be provided.

However, although the semiconductor element250has been described as having a top gate structure, the inventive concepts are not limited thereto. For example, the semiconductor element250may have a bottom gate structure.

In addition, although the display device100has been described as including one semiconductor element, the inventive concepts are not limited thereto. For example, the display device100may include at least one semiconductor element and at least one storage capacitor.

The conductive member360may be disposed in the first peripheral area21and the display area10on the interlayer insulating layer190. For example, the conductive member360may include a first extension part and a second extension part. In this case, the first extension part may extend in the first direction D1 in the first peripheral area21, and may be located in parallel with the first line extension part741. For example, the first line extension part741may be located close to the first pad area61in the first peripheral area21, and the first extension part may be located close to the display area10in the first peripheral area21. As described above, the first contact hole361may be located on the first extension part of the conductive member360, and the first contact hole361may be located to correspond to the first extension part. In other words, the first contact hole361may extend in the first direction D1, and may expose a portion of a top surface of the first extension part. The second extension part may extend from one side of the first extension part in the second direction D2, and may be located in a portion of the first peripheral area21and the display area10. In addition, the second extension part may be disposed in the sub-pixel area30, and a third contact hole651may be located on the second extension part in the sub-pixel area30. The second extension part may be defined as the first sub-power line650. The first extension part and the second extension part may be forme d integrally with each other.

In embodiments, the conductive member360may receive the first power (e.g., the low power voltage ELVSS ofFIG.4) applied to the first upper power line640through the upper connection member295, and the first power may be provided to the upper electrode340through the first sub-power line650. The conductive member360may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. For example, the conductive member360may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an aluminum-containing alloy, aluminum nitride (AlNx), a silver-containing alloy, tungsten nitride (WNx), a copper-containing alloy, a molybdenum-containing alloy, titanium nitride (TiNx), chromium nitride (CrNx), tantalum nitride (TaNx), strontium ruthenium oxide (SrRuxOy), zinc oxide (ZnOx), indium tin oxide (ITO), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium zinc oxide (IZO), and the like. These may be used alone or in combination with each other. In some embodiments, the conductive member360may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

However, although one second extension part has been described as extending from the first extension part in the second direction D2 in the display area10for convenience, the conductive member360may include one first extension part and a plurality of second extension parts as shown inFIG.5. In addition, each of the second extension parts may be disposed in the sub-pixel area30.

The upper inspection pads660may be disposed in the first peripheral area21on the interlayer insulating layer190to overlap the first line extension part741of the second upper power line740. The upper inspection pads660may be located on the same layer as the first upper power line640and the conductive member360, and may be arranged in the first direction D1 in the first peripheral area21. Each of the upper inspection pads660may further include an extension part extending in the second direction D2, in which one side of the extension part may be connected to the upper inspection pad660, and an opposite side of the extension part may be adjacent to the conductive member360. The opposite side of the extension part may be electrically connected to the signal line610through the conductive pattern510. For example, the upper inspection pads660may function as OS pads configured to inspect an open state and a short of a data line (e.g., the signal line610). In some embodiments, for accurate inspection, an opening may be formed in the second upper power line740located under each of the upper inspection pads660. Each of the upper inspection pads660may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, each of the upper inspection pads660may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The first upper power line640may be disposed in the first pad area61on the interlayer insulating layer190. In the embodiments, the first upper power line640may be located at a higher level than the second upper power line740, and may be electrically connected to the first power circuit board841disposed in the first pad area61ofFIG.2. In other words, one side of the first upper power line640may be electrically connected to the first power circuit board841through the first pad electrodes471, and an opposite side of the first upper power line640may be electrically connected to the upper connection member295. In this case, a second contact hole641may be located on the opposite side of the first upper power line640so that the opposite side of the first upper power line640may be electrically connected to the upper connection member295, and the second contact hole641may expose a portion of a top surface of the first upper power line640. In addition, the first upper power line640may be disposed in parallel with the second line extension part742.

The first power (e.g., the low power voltage ELVSS ofFIG.4) may be provided to the first upper power line640. The first power may be provided to the upper electrode340through the first upper power line640, the upper connection member295, the conductive member360, and the first sub-power line650. The first upper power line640may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In some embodiments, the first upper power line640may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The signal line610may be disposed in a portion of the first peripheral area21and the display area10on the interlayer insulating layer190, and may extend in the second direction D2. The data signal DATA ofFIG.5may be applied to the signal line610, and the signal line610may correspond to the data signal (DATA) line ofFIG.5. In other words, the signal line610may be electrically connected to the semiconductor element250and another semiconductor element (e.g., the second transistor TR2ofFIG.4) disposed in the sub-pixel area30, and may provide the data signal DATA to the semiconductor element. The signal line610may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, the signal line610may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The second sub-power line750may be disposed in parallel with the signal line610in a portion of the first peripheral area21and the display area10on the interlayer insulating layer190, and may extend in the second direction D2. The second sub-power line750may be electrically connected to the second upper power line740through the contact hole751in the first peripheral area21, and the second power may be applied to the second sub-power line750. For example, the second sub-power line750may correspond to the high power voltage (ELVDD) line ofFIG.4. In other words, in another sectional view of the display device100, the second sub-power line750may be electrically connected to the lower electrode290disposed in the sub-pixel area30, and may provide the second power (e.g., the high power voltage ELVDD ofFIG.4) to the lower electrode290. The second sub-power line750may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, the second sub-power line750may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The first sub-power line650may be disposed in parallel with the signal line610and the second sub-power line750in a portion of the first peripheral area21and the display area10on the interlayer insulating layer190, and may extend in the second direction D2. As described above, the first sub-power line650may extend from the first extension part of the conductive member360in the first peripheral area21, and the first power may be applied to the first sub-power line650. For example, the first sub-power line650may correspond to the low power voltage (ELVSS) line ofFIG.4. As shown inFIG.6, the first sub-power line650may be electrically connected to the upper electrode340through the third contact hole651, and may provide the first power (e.g., the low power voltage ELVSS ofFIG.4) to the upper electrode340. In the embodiments, the conductive member360, the first upper power line640, the upper inspection pads660, the signal line610, the second sub-power line750, and the first sub-power line650may be located on the same layer.

The protective insulating layer400may be disposed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the source and drain electrodes210and230, the signal line610, the second sub-power line750, the first sub-power line650, the conductive member360, the upper inspection pads660, and the first upper power line640. In the embodiments, the protective insulating layer400may include: a contact hole that exposes a portion of a top surface of the drain electrode230; a contact hole that exposes a portion of a top surface of the first sub-power line650; a contact hole that exposes a portion of a top surface of the conductive member360; a contact hole that exposes a portion of a top surface of the first upper power line640; and the like.

The protective insulating layer400may sufficiently cover the source and drain electrodes210and230, the signal line610, the second sub-power line750, the first sub-power line650, the conductive member360, the upper inspection pads660, and the first upper power line640on the interlayer insulating layer190, and may have a substantially flat top surface without creating a step around the source and drain electrodes210and230, the signal line610, the second sub-power line750, the first sub-power line650, the conductive member360, the upper inspection pads660, and the first upper power line640. In some embodiments, the protective insulating layer400may be disposed along a profile of the source and drain electrodes210and230, the signal line610, the second sub-power line750, the first sub-power line650, the conductive member360, the upper inspection pads660, and the first upper power line640with a substantially uniform thickness to cover the source and drain electrodes210and230, the signal line610, the second sub-power line750, the first sub-power line650, the conductive member360, the upper inspection pads660, and the first upper power line640on the interlayer insulating layer190. The protective insulating layer400may include a silicon compound, metal oxide, and the like. In other embodiments, the protective insulating layer400may have a multilayer structure having a plurality of insulating layers including mutually different materials, and the insulating layers may have mutually different thicknesses.

The first connection pattern365may be disposed in the contact hole that exposes the portion of the top surface of the conductive member360, the second connection pattern645may be disposed in the contact hole that exposes the portion of the first upper power line640, the third connection pattern235may be disposed in the contact hole that exposes the portion of the top surface of the drain electrode230, and the fourth connection pattern655may be disposed in the contact hole that exposes the portion of the top surface of the first sub-power line650. In other words, at least a portion of each of the first to fourth connection patterns365,645,235, and655may be interposed between the protective insulating layer400and a planarization layer270. The first connection pattern365may completely cover the conductive member360exposed by the contact hole, the second connection pattern645may completely cover the first upper power line640exposed by the contact hole, the third connection pattern235may completely cover the drain electrode230exposed by the contact hole, and the fourth connection pattern655may completely cover the first sub-power line650exposed by the contact hole. For example, in a method of manufacturing the display device100, the conductive member360, the second connection pattern645, the first upper power line640, and the drain electrode230may be formed by using copper, and each of the first to fourth connection patterns365,645,235, and655may be formed by using indium tin oxide. After the planarization layer270is formed on the protective insulating layer400, an etching process for forming contact holes of the planarization layer270overlapping the contact holes formed in the protective insulating layer400may be performed. The first to fourth connection patterns365,645,235, and655may be provided to protect the conductive member360, the second connection pattern645, the first upper power line640, and the drain electrode230while the etching process is performed. In some embodiments, each of the first to fourth connection patterns365,645,235, and655may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, each of the first to fourth connection patterns365,645,235, and655may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The planarization layer270may be disposed on the first to fourth connection patterns365,645,235, and655. The planarization layer270may be disposed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the protective insulating layer400. The planarization layer270may have a contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the top surface of the conductive member360, and the contact holes may be defined as the first contact hole361. In addition, the planarization layer270may have a contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the first upper power line640, and the contact holes may be defined as the second contact hole641. Moreover, the planarization layer270may have a contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the top surface of the first sub-power line650, and the contact holes may be defined as the third contact hole651. Meanwhile, the planarization layer270may have a contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the top surface of the drain electrode230, and the lower electrode290may be electrically connected to the semiconductor element250through the contact holes.

For example, the planarization layer270may have a relatively large thickness. In this case, the planarization layer270may have a substantially flat top surface. In order to implement such a flat top surface of the planarization layer270, a planarization process may be additionally performed on the planarization layer270. In some embodiments, the planarization layer270may be disposed along a profile of the first to fourth connection patterns365,645,235, and655with a uniform thickness on the protective insulating layer400. The first planarization layer270may be formed of an organic material or an inorganic material. In the embodiments, the planarization layer270may include an organic material. For example, the planarization layer270may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acryl-based resin, an epoxy-based resin, and the like.

The lower electrode290may be disposed in the sub-pixel area30on the planarization layer270. The lower electrode290may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, the lower electrode290may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The upper connection member295may be disposed in the first peripheral area21and the first pad area61on the planarization layer270. The upper connection member295may extend in the first direction D1 in the first peripheral area21, and may overlap a portion of the first upper power line640and the conductive member360. The upper connection member295may electrically connect the conductive member360and the first upper power line640through the first contact hole361and the second contact hole641. In other words, the first power applied to the first upper power line640may be provided to the conductive member360through the upper connection member295. The upper connection member295may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In some embodiments, the upper connection member295may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The first electrode pattern305may be disposed in the third contact hole651. The first electrode pattern305may be disposed between the upper electrode340and the fourth connection pattern655, and may completely cover the fourth connection pattern655exposed by the third contact hole651. For example, in the method of manufacturing the display device100, after the light emitting layer330is formed, a laser drilling process for removing the light emitting layer330, which is formed on the first electrode pattern305to overlap the third contact hole651, may be performed. The light emitting layer330formed on the first electrode pattern305may be removed through the laser drilling process. While the laser drilling process is performed, the first electrode pattern305may protect the fourth connection pattern655. The first electrode pattern305may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, the first electrode pattern305may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The pixel defining layer310may be disposed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the planarization layer270. The pixel defining layer310may cover both side portions of the lower electrode290, and may expose a portion of a top surface of the lower electrode290. In addition, the pixel defining layer310may cover both side portions of the first electrode pattern305, and may expose a portion of a top surface of the first electrode pattern305. Moreover, the pixel defining layer310may cover the upper connection member295in the first peripheral area21and the first pad area61. The pixel defining layer310may be formed of an organic material or an inorganic material. In the embodiments, the pixel defining layer310may include an organic material.

The light emitting layer330may be disposed in the display area10on the pixel defining layer310, the lower electrode290, and a portion of the first electrode pattern305. As described above, the light emitting layer330may expose the portion of the top surface of the first electrode pattern305through the laser drilling process. In other words, the light emitting layer330may not be disposed in a portion in which the third contact hole651is formed. The light emitting layer330may have a multilayer structure including an organic light emission layer EML, a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, an electron injection layer EIL, and the like. The organic light emission layer EML of the light emitting layer330may be formed by using at least one of light emitting materials for emitting different color lights (i.e., a red light, a green light, a blue light, etc.) according to sub-pixels. Alternatively, the organic light emission layer EML of the light emitting layer330may be formed by stacking a plurality of light emitting materials for generating different color lights such as a red light, a green light, and a blue light to emit a white light as a whole. In this case, a color filter may be disposed on the light emitting layer330disposed on the lower electrode290. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. In some embodiments, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin or a color photoresist.

The upper electrode340may be disposed in the display area10on the substrate110. For example, the upper electrode340may be disposed on the light emitting layer330in the display area10, and may make direct contact with the first electrode pattern305exposed by the light emitting layer330. In other words, the upper electrode340may be disposed along a profile of the light emitting layer330and the first electrode pattern305. As described above, the first power applied to the first upper power line640may be transmitted to the upper electrode340through the second connection pattern645, the upper connection member295, the first connection pattern365, the conductive member360, the first sub-power line650, the fourth connection pattern655, and the first electrode pattern305. The upper electrode340may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, the upper electrode340may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

Accordingly, the sub-pixel structure200including the lower electrode290, the light emitting layer330, and the upper electrode340may be provided.

The encapsulation substrate450may be disposed in the display area10on the upper electrode340. The encapsulation substrate450may face the substrate110, and may not be disposed in the first pad area61and the second pad area62. The encapsulation substrate450may include substantially the same material as the substrate110. For example, the encapsulation substrate450may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, a non-alkali glass substrate, and the like. In other embodiments, the encapsulation substrate450may include a transparent inorganic material or flexible plastic. For example, the encapsulation substrate450may include a transparent resin substrate having flexibility. In this case, in order improve flexibility of the display device100, the encapsulation substrate450may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. The stacked structure may include a first inorganic layer, an organic layer, and a second inorganic layer.

For example, a conventional display device may have an enlarged size and a high resolution. When the display device is driven with a high luminance, a current may be concentrated in the first upper power line640disposed in the first peripheral area21and the first pad area61so that a temperature may be increased (e.g., a heat generation phenomenon). In this case, the heat generation phenomenon may cause a short of the first upper power line640or deformation of an insulating layer located around the first upper power line640. In addition, as the display area10is widened, a voltage drop (IR drop) phenomenon may occur. In addition, a defect of the conventional display device may be caused by the heat generation phenomenon of the first upper power line640occurring in the second peripheral area22and the voltage drop phenomenon occurring in the display area10.

In embodiments, since the display device100includes the conductive member360, and the first contact hole361formed on the conductive member360has a relatively wide area, a contact area between the upper connection member295and the conductive member360may be relatively increased. In addition, since the upper electrode340is electrically connected to the first upper power line640through the third contact hole651, the upper electrode340may receive the first power. Accordingly, according to the display device100, both the heat generation phenomenon and the voltage drop phenomenon may be reduced.

FIG.9is a partially enlarged plan view showing a region B ofFIG.1;FIG.10is a cross-sectional view taken along line IV-IV′ ofFIG.9;FIG.11is a cross-sectional view taken along line V-V′ ofFIG.9; andFIG.12is a cross-sectional view taken along line VI-VI′ ofFIG.9.

Referring toFIGS.9,10,11, and12, the display device100may further include a fan-out line420, a first lower power line840, a second lower power line950, lower inspection pads760, a fifth connection pattern385, a sixth connection pattern845, a seventh connection pattern665, a sub-pixel structure200, a lower connection member395, a second electrode pattern315, and the like.

Although the sub-pixel structure200ofFIG.10has been assumed as having the same reference numeral as the sub-pixel structure200ofFIG.6for convenience of description, the sub-pixel structure200ofFIG.10and the sub-pixel structure200ofFIG.6may be mutually different sub-pixel structures. In other words, the sub-pixel structure200ofFIG.10may be a sub-pixel structure disposed in the display area10that is adjacent to the second peripheral area22, and the sub-pixel structure200ofFIG.6may be a sub-pixel structure disposed in the display area10that is adjacent to the first peripheral area21. However, the light emitting layer330and the upper electrode340shown inFIG.10may be the same as the light emitting layer330and the upper electrode340shown inFIG.6, respectively.

The fan-out line420may be disposed in the second pad area62and the second peripheral area22on the gate insulating layer150. In the embodiments, the fan-out line420may be located between the substrate110and the first and second lower power lines840and940. One side of the fan-out line420may be electrically connected to the driving circuit board900through the second pad electrodes472ofFIG.2, and an opposite side of the fan-out line420may be electrically connected to the lower inspection pads760. The data signal DATA ofFIG.4may be provided to the fan-out line420from the driving circuit board900. The data signal DATA may be provided to the second transistor TR2ofFIG.4through the lower inspection pads760and the signal line610. The fan-out line420may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In some embodiments, the fan-out line420may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses. In the embodiments, the fan-out line420may be located on the same layer as the gate electrode170and the second upper power line740.

The first lower power line840may be disposed in the second pad area62on the interlayer insulating layer190. In the embodiments, the first lower power line840may be located at a higher level than the fan-out line420, and may be electrically connected to the first power circuit board841disposed in the second pad area62ofFIG.2. In other words, one side of the first lower power line840may extend in the second direction D2 so as to be electrically connected to the first power circuit board841through the second pad electrodes472, and an opposite side of the first lower power line840may be electrically connected to the lower connection member395. In this case, a fifth contact hole842may be located on the opposite side of the first lower power line840so that the opposite side of the first lower power line840may be electrically connected to the lower connection member395, and the fifth contact hole842may expose a portion of a top surface of the first lower power line840.

The first power (e.g., the low power voltage ELVSS ofFIG.4) may be provided to the first lower power line840. The first power may be provided to the upper electrode340through the first lower power line840, the lower connection member395, and the first sub-power line650. The first lower power line840may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In some embodiments, the first lower power line840may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The second lower power line950may be disposed in the second pad area62on the interlayer insulating layer190. In the embodiments, the second lower power line950may be located at a higher level than the fan-out line420, and may be located on the same layer as the first lower power line840. In addition, the second lower power line950may be electrically connected to the second power circuit board941disposed in the second pad area62ofFIG.2through the second pad electrodes472. Moreover, the second lower power line950may include a first line extension part951and a second line extension part952. For example, the first line extension part951may be located in the second peripheral area22, and may extend in the first direction D1. In other words, the first line extension part951may overlap the second peripheral area22. The second line extension part952may extend from one side of the first line extension part951in the second direction D2 so as to be located in the second pad area62. In other words, the second line extension part952may protrude from first and second portions of the first line extension part951in the second direction D2, and may extend in the second direction D2 so as to be electrically connected to the second power circuit board941through the second pad electrodes472.

The second power (e.g., the high power voltage ELVDD ofFIG.4) may be provided to the second lower power line950. The second power may be provided to the lower electrode290through the second lower power line950and the second sub-power line750. The second lower power line950may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In some embodiments, the second lower power line950may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The lower inspection pads760may be disposed in the second peripheral area22on the interlayer insulating layer190while being spaced apart from the second lower power line950. For example, the second lower power line950may be located close to the second pad area62in the second peripheral area22, and the lower inspection pads760may be located close to the display area10of the second peripheral area22. The lower inspection pads760may be located on the same layer as the first lower power line840and the second lower power line950, and may be arranged in the first direction D1 in the second peripheral area22. Each of the lower inspection pads760may further include an extension part extending in the third direction D3, and the extension part may correspond to the signal line610. In the embodiments, the interlayer insulating layer190may cover the fan-out line420, and may have a contact hole761that exposes a portion of the fan-out line420in the second peripheral area22. Each of the lower inspection pads760may be electrically connected to the fan-out line420through the contact hole761. For example, the lower inspection pads760may function as OS pads configured to inspect an open state and a short of the data line (e.g., the signal line610). Each of the lower inspection pads760may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, each of the lower inspection pads760may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

In the embodiments, the protective insulating layer400may include: a contact hole that exposes a first portion of a top surface of the first sub-power line650; a contact hole that exposes a portion of a top surface of the first lower power line840; a contact hole that exposes a second portion of the top surface of the first sub-power line650; and the like.

The fifth connection pattern385may be disposed in the contact hole that exposes the first portion of the top surface of the first sub-power line650, the sixth connection pattern845may be disposed in the contact hole that exposes the portion of the top surface of the first lower power line840, and the seventh connection pattern665may be disposed in the contact hole that exposes the second portion of the top surface of the first sub-power line650. In other words, at least a portion of each of the fifth to seventh connection patterns385,845, and665may be interposed between the protective insulating layer400and the planarization layer270. The fifth connection pattern385may completely cover the first portion of the first sub-power line650exposed by the contact hole, the sixth connection pattern845may completely cover the first lower power line840exposed by the contact hole, and the seventh connection pattern665may completely cover the second portion of the first sub-power line650exposed by the contact hole. For example, in the method of manufacturing the display device100, the first sub-power line650and the first lower power line840may be formed by using copper, and each of the fifth to seventh connection patterns385,845, and665may be formed by using indium tin oxide. After the planarization layer270is formed on the protective insulating layer400, an etching process for forming contact holes of the planarization layer270overlapping the contact holes formed in the protective insulating layer400may be performed. The fifth to seventh connection patterns385,845, and665may be provided to protect the first sub-power line650and the first lower power line840while the etching process is performed. In some embodiments, each of the fifth to seventh connection patterns385,845, and665may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, each of the fifth to seventh connection patterns385,845, and665may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

In the embodiments, the planarization layer270may have a contact hole overlapping the contact hole of the protective insulating layer400that exposes the first portion of the top surface of the first sub-power line650, and the contact holes may be defined as a fourth contact hole391. In addition, the planarization layer270may have a contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the top surface of the first lower power line840, and the contact holes may be defined as the fifth contact hole842. Moreover, the planarization layer270may have a contact hole overlapping the contact hole of the protective insulating layer400that exposes the second portion of the top surface of the first sub-power line650, and the contact holes may be defined as a sixth contact hole652.

The lower connection member395may be disposed in the second peripheral area22and the second pad area62on the planarization layer270. The lower connection member395may extend in the first direction D1 in the second peripheral area22, and may overlap a portion of the first lower power line840and the first sub-power line650. The lower connection member395may electrically connect the first sub-power line650and the first lower power line840through the fourth contact hole391and the fifth contact hole842. In other words, the first power applied to the first lower power line840may be provided to the first sub-power line650through the lower connection member395. In some embodiments, a conductive member such as the conductive member360ofFIG.5may be formed in the second peripheral area22. For example, the conductive member may overlap one side of the lower connection member395that is adjacent to a boundary between the second peripheral area22and the display area10, and may be disposed on the same layer as the gate electrode170. The lower connection member395may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In some embodiments, the lower connection member395may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

The second electrode pattern315may be disposed in the sixth contact hole652. The second electrode pattern315may be disposed between the upper electrode340and the seventh connection pattern665, and may completely cover the seventh connection pattern665exposed by the sixth contact hole652. For example, in the method of manufacturing the display device100, after the light emitting layer330is formed, a laser drilling process for remove the light emitting layer330, which is formed on the second electrode pattern315to overlap the sixth contact hole652, may be performed. The light emitting layer330formed on the second electrode pattern315may be removed through the laser drilling process. While the laser drilling process is performed, the second electrode pattern315may protect the seventh connection pattern665. The second electrode pattern315may include a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. In other embodiments, the second electrode pattern315may have a multilayer structure including a plurality of metal layers formed of mutually different materials, and the metal layers may have mutually different thicknesses.

As described above, the display device100shown inFIGS.1to12may be provided.

Since the display device100according to the embodiments of the present invention includes the conductive member360, and the first contact hole361formed on the conductive member360has a relatively wide area, the heat generation phenomenon that may occur in the first peripheral area21may be reduced. In addition, since the display device100includes the third contact hole651, and the upper electrode340receives the first power from the first sub-power line650in each of the sub-pixel areas30, the voltage drop phenomenon that may occur in the display area10may be reduced. Accordingly, according to the display device100, both the heat generation phenomenon that may occur in the first peripheral area21and the voltage drop phenomenon that may occur in the display area10may be reduced.

However, although the display device100according to the present invention has been described as specifically being an organic light emitting diode display device, the inventive concepts are not limited thereto. In other embodiments, the display device100may include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP), or an electrophoretic image display device (EPD).

FIGS.13to26are views showing a method of manufacturing a display device according to embodiments of the present invention. For example,FIGS.13,14,18, and19are plan views showing the method of manufacturing the display device, andFIGS.15to17and20to26are sectional views showing the method of manufacturing the display device.

Referring toFIGS.13,14,15,16, and17, as shown inFIGS.15,16, and17, a substrate110including transparent or opaque materials may be provided. The substrate110may be formed by using a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, a non-alkali glass substrate, and the like. The substrate110may include a display area10in which a plurality of sub-pixel areas30are arranged, a peripheral area20including a first peripheral area21and a second peripheral area22, a first pad area61, and a second pad area62(seeFIG.1).

As shown inFIGS.15,16, and17, a buffer layer115may be formed on the substrate110. The buffer layer115may be formed over the whole of the display area10, the peripheral area20, the first pad area61, and the second pad area62on the substrate110. Depending on a type of the substrate110, at least two buffer layers115may be provided on the substrate110, or the buffer layer115may not be formed. The buffer layer115may be formed by using a silicon compound, metal oxide, and the like. The buffer layer115may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, aluminum oxide, aluminum nitride, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and the like.

As shown inFIG.15, an active layer130may be formed in the sub-pixel area30on the buffer layer115. The active layer130may be formed by using a metal oxide semiconductor, an inorganic semiconductor, an organic semiconductor, or the like. The active layer130may include a source region, a drain region, and a channel region located between the source region and the drain region.

As shown inFIGS.15,16, and17, a gate insulating layer150may be formed on the active layer130. The gate insulating layer150may be formed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the buffer layer115. The gate insulating layer150may cover the active layer130in the sub-pixel area30on the buffer layer115, and may extend in a direction from the sub-pixel area30to the peripheral area20. For example, the gate insulating layer150may sufficiently cover the active layer130on the buffer layer115, and may have a substantially flat top surface without creating a step around the active layer130. In some embodiments, the gate insulating layer150may be formed along a profile of the active layer130with a uniform thickness to cover the active layer130on the buffer layer115. The gate insulating layer150may be formed by using a silicon compound, metal oxide, and the like.

As shown inFIG.15, a gate electrode170may be formed in the sub-pixel area30on the gate insulating layer150. The gate electrode170may be formed on a portion of the gate insulating layer150under which the active layer130is located. The gate electrode170may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.13and16, a second upper power line740may be formed in the first pad area61and the first peripheral area21on the gate insulating layer150. The second upper power line740may include a first line extension part741, a second line extension part742, and a third line extension part743. For example, the first line extension part741may be located in the first peripheral area21, and may extend in the first direction D1. The second line extension part742may extend from one side of the first line extension part741in the third direction D3 so as to be located in the first pad area61. The third line extension part743may extend from an opposite side of the first line extension part741in the second direction D2. The first line extension part741, the second line extension part742, and the third line extension part743may be formed integrally with each other. The second upper power line740may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.14and17, a fan-out line420may be formed in the second pad area62and the second peripheral area22on the gate insulating layer150. The fan-out line420may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIG.13, a conductive pattern510may be formed in parallel with the third line extension part743in the first peripheral area21on the gate insulating layer150. The conductive pattern510may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

In embodiments, the gate electrode170, the conductive pattern510, the second upper power line740, and the fan-out line420may be simultaneously formed by using the same material.

As shown inFIGS.13,15,16, and17, an interlayer insulating layer190may be formed on the gate electrode170, the conductive pattern510, the second upper power line740, and the fan-out line420. The interlayer insulating layer190may be formed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the gate insulating layer150. The interlayer insulating layer190may include: a contact hole511that exposes one side of the conductive pattern510in the first peripheral area21; a contact hole512that exposes an opposite side of the conductive pattern510; and a contact hole751that exposes a portion of the third line extension part743that is adjacent to the display area10, and may include a contact hole761that exposes a portion of the fan-out line420in the second peripheral area22. For example, the interlayer insulating layer190may sufficiently cover the gate electrode170, the conductive pattern510, the second upper power line740, and the fan-out line420on the gate insulating layer150, and may have a substantially flat top surface without creating a step around the gate electrode170, the conductive pattern510, the second upper power line740, and the fan-out line420. In some embodiments, the interlayer insulating layer190may be formed along a profile of the gate electrode170, the conductive pattern510, the second upper power line740, and the fan-out line420with a uniform thickness to cover the gate electrode170, the conductive pattern510, the second upper power line740, and the fan-out line420on the gate insulating layer150. The interlayer insulating layer190may be formed by using a silicon compound, metal oxide, and the like.

Referring toFIGS.18,19,20,21, and22, as shown inFIG.20, a source electrode210and a drain electrode230may be formed in the sub-pixel area30on the interlayer insulating layer190. The source electrode210may be connected to the source region of the active layer130through a contact hole formed by removing first portions of the gate insulating layer150and the interlayer insulating layer190, and the drain electrode230may be connected to the drain region of the active layer130through a contact hole formed by removing second portions of the gate insulating layer150and the interlayer insulating layer190. Each of the source electrode210and the drain electrode230may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

Accordingly, the semiconductor element250including the active layer130, the gate insulating layer150, the gate electrode170, the interlayer insulating layer190, the source electrode210, and the drain electrode230may be formed.

As shown inFIGS.18and21, a conductive member360may be formed in the first peripheral area21and the display area10on the interlayer insulating layer190. For example, the conductive member360may include a first extension part and a second extension part. In this case, the first extension part may extend in the first direction D1 in the first peripheral area21, and may be located in parallel with the first line extension part741. In addition, the second extension part may be formed in the sub-pixel area30. The second extension part may be defined as a first sub-power line650. The first extension part and the second extension part may be formed integrally with each other. The conductive member360may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. For example, the conductive member360may include gold, silver, aluminum, platinum, nickel, titanium, palladium, magnesium, calcium, lithium, chromium, tantalum, tungsten, copper, molybdenum, scandium, neodymium, iridium, an aluminum-containing alloy, aluminum nitride, a silver-containing alloy, tungsten nitride, a copper-containing alloy, a molybdenum-containing alloy, titanium nitride, chromium nitride, tantalum nitride, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, and the like. These may be used alone or in combination with each other.

As shown inFIGS.18and21, a first upper power line640may be formed in the first pad area61on the interlayer insulating layer190. The first upper power line640may be formed in parallel with the second line extension part742. The first upper power line640may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.18,20, and21, a signal line610may be formed in a portion of the first peripheral area21and the display area10on the interlayer insulating layer190, and may extend in the second direction D2. One side of the signal line610may overlap the contact hole512of the interlayer insulating layer190, and may be connected to the conductive pattern510through the contact hole512. The signal line610may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.18and21, a second sub-power line750may be formed in parallel with the signal line610and the first sub-power line650in a portion of the first peripheral area21and the display area10on the interlayer insulating layer190, and may extend in the second direction D2. The second sub-power line750may be connected to the second upper power line740through the contact hole751in the first peripheral area21. The second sub-power line750may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.18and21, upper inspection pads660may be formed in the first peripheral area21on the interlayer insulating layer190to overlap the first line extension part741of the second upper power line740. The upper inspection pads660may be arranged in the first direction D1 in the first peripheral area21. Each of the upper inspection pads660may further include an extension part extending in the second direction D2, in which one side of the extension part may be connected to the upper inspection pad660, and an opposite side of the extension part may overlap the contact hole511of the interlayer insulating layer190, and may be connected to the conductive pattern510through the contact hole511. Each of the upper inspection pads660may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.19and22, a first lower power line840may be formed in the second pad area62on the interlayer insulating layer190. The first lower power line840may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.19and22, a second lower power line950may be formed in the second pad area62on the interlayer insulating layer190. The second lower power line950may include a first line extension part951and a second line extension part952. For example, the first line extension part951may be located in the second peripheral area22, and may extend in the first direction D1. The second line extension part952may extend from one side of the first line extension part951in the second direction D2 so as to be located in the second pad area62. The second lower power line950may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.19and22, lower inspection pads760may be formed in the second peripheral area22on the interlayer insulating layer190while being spaced apart from the second lower power line950. For example, the second lower power line950may be formed close to the second pad area62in the second peripheral area22, and the lower inspection pads760may be formed close to the display area10in the second peripheral area22. The lower inspection pads760may be arranged in the first direction D1 in the second peripheral area22. Each of the lower inspection pads760may further include an extension part extending in the third direction D3, and the extension part may correspond to the signal line610. Each of the lower inspection pads760may be connected to the fan-out line420through the contact hole761of the interlayer insulating layer190. Each of the lower inspection pads760may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

In the embodiments, the source electrode210, the drain electrode230, the conductive member360, the first upper power line640, the signal line610, the second sub-power line750, the upper inspection pads660, the first lower power line840, the second lower power line950, and the lower inspection pads760may be simultaneously formed by using the same material.

Referring toFIG.1, first pad electrodes471may be formed in the first pad area61on the substrate110, and second pad electrodes472may be formed in the second pad area62on the substrate110. For example, the first pad electrodes471and the second pad electrodes472may be formed simultaneously with the source electrode210, the drain electrode230, the conductive member360, the first upper power line640, the signal line610, the second sub-power line750, the upper inspection pads660, the first lower power line840, the second lower power line950, and the lower inspection pads760by using the same material as the source electrode210, the drain electrode230, the conductive member360, the first upper power line640, the signal line610, the second sub-power line750, the upper inspection pads660, the first lower power line840, the second lower power line950, and the lower inspection pads760.

As shown inFIGS.18to22, a protective insulating layer400may be formed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the source electrode210, the drain electrode230, the conductive member360, the first upper power line640, the signal line610, the second sub-power line750, the upper inspection pads660, the first lower power line840, the second lower power line950, and the lower inspection pads760. The protective insulating layer400may sufficiently cover the source electrode210, the drain electrode230, the conductive member360, the first upper power line640, the signal line610, the second sub-power line750, the upper inspection pads660, the first lower power line840, the second lower power line950, and the lower inspection pads760on the interlayer insulating layer190, and may have a substantially flat top surface without creating a step around the source electrode210, the drain electrode230, the conductive member360, the first upper power line640, the signal line610, the second sub-power line750, the upper inspection pads660, the first lower power line840, the second lower power line950, and the lower inspection pads760. In some embodiments, the protective insulating layer400may be formed along a profile of the source electrode210, the drain electrode230, the conductive member360, the first upper power line640, the signal line610, the second sub-power line750, the upper inspection pads660, the first lower power line840, the second lower power line950, and the lower inspection pads760with a substantially uniform thickness to cover the source electrode210, the drain electrode230, the conductive member360, the first upper power line640, the signal line610, the second sub-power line750, the upper inspection pads660, the first lower power line840, the second lower power line950, and the lower inspection pads760on the interlayer insulating layer190. The protective insulating layer400may be formed by using a silicon compound, metal oxide, and the like.

After the protective insulating layer400is formed, a contact hole that exposes a portion of a top surface of the drain electrode230, a contact hole that exposes a portion of a top surface of the first sub-power line650, a contact hole that exposes a portion of a top surface of the conductive member360, a contact hole that exposes a portion of a top surface of the first upper power line640, a contact hole that exposes a first portion of the top surface of the first sub-power line650, a contact hole that exposes a portion of a top surface of the first lower power line840, and a contact hole that exposes a second portion of the top surface of the first sub-power line650may be formed in the protective insulating layer400.

A first connection pattern365may be formed in the contact hole that exposes the portion of the top surface of the conductive member360, a second connection pattern645may be formed in the contact hole that exposes the portion of the first upper power line640, a third connection pattern235may be formed in the contact hole that exposes the portion of the top surface of the drain electrode230, a fourth connection pattern655may be formed in the contact hole that exposes the portion of the top surface of the first sub-power line650, a fifth connection pattern385may be formed in the contact hole that exposes the first portion of the top surface of the first sub-power line650, a sixth connection pattern845may be formed in the contact hole that exposes the portion of the top surface of the first lower power line840, and a seventh connection pattern665may be formed in the contact hole that exposes the second portion of the top surface of the first sub-power line650. The first to seventh connection patterns365,645,235,655,385,845, and665may be formed to protect the conductive member360, the second connection pattern645, the first upper power line640, the drain electrode230, the first sub-power line650, and the first lower power line840. Each of the first to seventh connection patterns365,645,235,655,385,845, and665may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

A planarization layer270may be formed on the first to seventh connection patterns365,645,235,655,385,845, and665. The planarization layer270may be formed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the protective insulating layer400. For example, the planarization layer270may have a relatively large thickness. In this case, the planarization layer270may have a substantially flat top surface. In order to implement such a flat top surface of the planarization layer270, a planarization process may be additionally performed on the planarization layer270. In some embodiments, the planarization layer270may be formed along a profile of the first to seventh connection patterns365,645,235,655,385,845, and665with a uniform thickness on the protective insulating layer400. The planarization layer270may be formed by using an organic material. For example, the planarization layer270may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acryl-based resin, an epoxy-based resin, and the like.

After the planarization layer270is formed, a contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the top surface of the conductive member360may be formed in the planarization layer270, and the contact holes may be defined as a first contact hole361. A contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the first upper power line640may be formed in the planarization layer270, and the contact holes may be defined as a second contact hole641. A contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the top surface of the first sub-power line650may be formed in the planarization layer270, and the contact holes may be defined as a third contact hole651. A contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the top surface of the drain electrode230may be formed in the planarization layer270. A contact hole overlapping the contact hole of the protective insulating layer400that exposes the first portion of the top surface of the first sub-power line650may be formed in the planarization layer270, and the contact holes may be defined as a fourth contact hole391. A contact hole overlapping the contact hole of the protective insulating layer400that exposes the portion of the top surface of the first lower power line840may be formed in the planarization layer270, and the contact holes may be defined as a fifth contact hole842. A contact hole overlapping the contact hole of the protective insulating layer400that exposes the second portion of the top surface of the first sub-power line650may be formed in the planarization layer270, and the contact holes may be defined as a sixth contact hole652.

Referring toFIGS.5,9,23,24, and25, as shown inFIG.23, a lower electrode290may be formed in the sub-pixel area30on the planarization layer270. The lower electrode290may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.5and24, an upper connection member295may be formed in the first peripheral area21and the first pad area61on the planarization layer270. The upper connection member295may extend in the first direction D1 in the first peripheral area21, and may overlap a portion of the first upper power line640and the conductive member360. The upper connection member295may be connected to the conductive member360and the first upper power line640through the first contact hole361and the second contact hole641, respectively. The upper connection member295may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.5and23, a first electrode pattern305may be formed in the third contact hole651. The first electrode pattern305may completely cover the fourth connection pattern655exposed by the third contact hole651. The first electrode pattern305may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.9,23, and24, a lower connection member395may be formed in the second peripheral area22and the second pad area62on the planarization layer270. The lower connection member395may extend in the first direction D1 in the second peripheral area22, and may overlap a portion of the first lower power line840and the first sub-power line650. The lower connection member395may be connected to the first sub-power line650and the first lower power line840through the fourth contact hole391and the fifth contact hole842, respectively. In some embodiments, a conductive member such as the conductive member360ofFIG.5may be formed in the second peripheral area22. For example, the conductive member may overlap one side of the lower connection member395that is adjacent to a boundary between the second peripheral area22and the display area10, and may be formed on the same layer as the gate electrode170. The lower connection member395may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

As shown inFIGS.9and10, a second electrode pattern315may be formed in the sixth contact hole652. The second electrode pattern315may completely cover the seventh connection pattern665exposed by the sixth contact hole652. The second electrode pattern315may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

In the embodiments, the lower electrode290, the upper connection member295, the first electrode pattern305, the lower connection member395, and the second electrode pattern315may be simultaneously formed by using the same material.

As shown inFIGS.23,24, and25, a pixel defining layer310may be formed in the display area10, the peripheral area20, the first pad area61, and the second pad area62on the planarization layer270. The pixel defining layer310may cover both side portions of the lower electrode290, both side portions of the first electrode pattern305, both side portions of the second electrode pattern315, the upper connection member295, and the lower connection member395. The pixel defining layer310may be formed by using an organic material.

Referring toFIGS.5,9, and26, a light emitting layer330may be formed in the display area10on the pixel defining layer310, the lower electrode290, the first electrode pattern305, and the second electrode pattern315. The light emitting layer330may have a multilayer structure including an organic light emission layer, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like. The organic light emission layer of the light emitting layer330may be formed by using at least one of light emitting materials for emitting different color lights (i.e., a red light, a green light, a blue light, etc.) according to sub-pixels. Alternatively, the organic light emission layer of the light emitting layer330may be formed by stacking a plurality of light emitting materials for generating different color lights such as a red light, a green light, and a blue light to emit a white light as a whole.

After the light emitting layer330is formed, a portion of a top surface of the first electrode pattern305and a portion of a top surface of the second electrode pattern315may be exposed through a laser drilling process.

An upper electrode340may be formed in the display area10on the substrate110. For example, the upper electrode340may be formed in the display area10on the light emitting layer330, and may make direct contact with the first electrode pattern305and the second electrode pattern315exposed by the light emitting layer330. In other words, the upper electrode340may be formed along a profile of the light emitting layer330, the first electrode pattern305, and the second electrode pattern315. The upper electrode340may be formed by using a metal, an alloy, metal nitride, conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other.

Accordingly, the sub-pixel structure200including the lower electrode290, the light emitting layer330, and the upper electrode340may be formed.

An encapsulation substrate450may be formed in the display area10on the upper electrode340. The encapsulation substrate450may face the substrate110, and may not be formed in the first pad area61and the second pad area62. The encapsulation substrate450may include substantially the same material as the substrate110. For example, the encapsulation substrate450may be formed by using a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, a non-alkali glass substrate, and the like.

Referring toFIG.2, a first power circuit board841and a second power circuit board941may be formed on the first pad electrodes471, and a first power circuit board841, a second power circuit board941, and a driving circuit board900may be formed on the second pad electrodes472.

Accordingly, the display device100shown inFIGS.1to12may be manufactured.

The present invention may be applied to various electronic devices including a display device. For example, the present invention may be applied to a number of the electronic devices such as vehicle-display devices, ship-display devices, aircraft-display devices, portable communication devices, display devices for display or for information transfer, medical-display devices, etc.

Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art.