Patent ID: 12211903

The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schematically and not to scale. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.

DETAILED DESCRIPTION

FIG.2shows a top plane view of the first exemplary embodiment of a semiconductor transistor cell1. In a full transistor device, a multitude of transistor cells1are arranged on the emitter side31, adjacent with each other.FIGS.3A-Cshow more specific details in cross sections at different cut lines as depicted inFIG.2, in form of a punch through insulated gate bipolar transistor (IGBT) with a four-layer structure (pnpn). The layers are arranged between an emitter electrode3on an emitter side31and a collector electrode2on a collector side21, which is arranged opposite of the emitter side31in a first direction X, also identified as the vertical orientation. The IGBT transistor cell comprises an (n-) doped drift layer4, which is arranged between the emitter side31and the collector side21, and a p doped first base layer9arranged on the emitter side31of the drift layer4, and extending into the drift layer4in the X direction. The transistor cell1also comprises an n doped source region7, which is arranged at the emitter side31embedded into the first base layer9, and directly contacting the emitter electrode3. The source region7has a higher doping concentration than the drift layer4. Both the source region7and the first base layer9are shaped as elongated rectangles in a top plane view defined by the Y-Z directions, which are orthogonal to the X direction and together they define the horizontal orientation.

The innovative power semiconductor transistor cell1further comprises a p doped second base layer8, which is arranged between the first base layer9and the emitter electrode3, which second base layer8is in direct electrical contact to the emitter electrode3. The second base layer8has a higher doping concentration than the doping of the first base layer9. The second base layer8extends in the X direction deeper than the source region, but shallower than the first base layer9. In the same top plane view, the second base layer8is shaped as a rectangle substantially centered on the rectangle of the source region7. In the direction Y, the position of the edge of the second base layer8is spaced apart by a separation region60from the position of the edge of the source region7, when referring to the furthest edges with respect to the position of the contact opening14. The separation region60has a length that can be substantially 0 as represented inFIG.3A, can be larger than 0 as represented inFIG.9, or can be negative (not shown).

Furthermore, a plurality of first gate electrodes11are embedded in corresponding trench recesses, each electrode11being electrically insulated from the surrounding first base layer9, the second base layer8, the source region7and the drift layer4by a first insulating layer12′. The first gate electrodes11extend longitudinally in the Y direction, and are arranged at an angle of 90 degrees with respect to the Z direction, when observed in the top plane view. The trench recesses intersect both the source region7and the second base layer8, i.e., the first end trench wall90of the first gate electrodes is arranged in the source region7.

A second insulation layer12is arranged on the emitter side31, protecting the surface of the drift layer4, of the first base layer9and of the source region7. The layer12can also be used as a masking layer for the implantation of ions forming the source region7and the first base layer9.

The power semiconductor device according to the first exemplary embodiment further comprises a p-doped collector layer6arranged between a buffer layer5and the collector electrode2, which collector layer6is in direct electrical contact to the collector electrode2. An n-doped buffer layer5is arranged between the collector layer6, and the drift region4. A third insulation layer13is arranged between the emitter electrode3, the first gate electrodes11, and the gate runners11′.

The emitter electrode3and the insulating layer13are omitted in most of the Figures showing top plane views, in order to better facilitate the visualisation of the underlaying structures.

With respect to theFIGS.2A,3B and3C, the critical design aspects are the distance Wtor mesa between the trenches of the first gate electrodes11in the Z direction, as well as the dimension W′prepresenting the distance from a trench end wall90of a first gate electrode11to a trench end wall90of the adjacent first gate electrode in the Y direction. Improved carrier storage/reduced hole drainage is expected as the dimensions Wtand W′pare reduced. The value of Wtmay be in a range from about 5 μm to below 0.1 μm, more preferably from 1 μm to 0.1 μm—which is achievable with the proposed design because no additional structures have to be lithographically defined in between the trench recesses of the first gate electrodes11. Also, improved carrier storage/reduced hole drainage is expected by reducing the distance W′p. More specifically, W′pcould extend approximately in a range from about 20 μm to about 0.1 μm, preferably from 5 μm to 0.1 μm, and more preferably from 2 μm to 0.1 μm. In order to enable a proper electrical contact between the source region7, the second base layer8and the emitter electrode3, the distance W′pis increased in certain regions of the semiconductor, in order to allow a contact opening14to be formed. The new distance Wpin these regions could extend approximately in a range from about 2 μm to 0.5 μm, depending on the resolution of the lithography system used during the manufacturing process.

The number of first gate electrodes11shown inFIG.2is indicative only, and used for clarification purposes, and do not define the exact number of gate electrodes that must be used when designing a real semiconductor transistor1. The number of first gate electrodes11as well as their specific arrangement into groups having a separation distance W′pand groups having a separation distance Wpwill depend on the selected target performance criteria as well as the overall geometrical dimensions of the full semiconductor device. The plurality of first gate electrodes11are interconnected using gate runners, a concept known to those experts in the field.

In the first exemplary embodiment depicted inFIG.2, and cross sectionsFIG.3A-C, a voltage applied on the first gate electrodes11initiates the formation of an inversion layer in the first base layer9. If a positive voltage is applied, with a value above a threshold value, the inversion channel is formed only on the lateral trench walls, except in the regions abutting the highly doped second base layer8, which has higher dopant concentration than the first base layer9. No surface inversion layer is formed on the emitter side31of the first base layer9.

Due to the plurality of first gate electrodes11arranged, according to the first exemplary embodiment, orthogonally to the extension direction of the source region7in a top plane view, the Miller capacitance will be increased and will impact especially the turnoff that changes the IGBT from the ON-state or Conductive-state to the OFF-state. When the IGBT is in Conductive-state before the turnoff, a voltage as high as the collector-emitter saturation voltage is applied between the collector electrode2and the emitter electrode3and many charge carriers are accumulated in the vicinity of the first insulating layer12′. Therefore, the Miller capacitance is the capacitance of the first insulating layer12′. As soon as the IGBT turnoff process starts, depletion starts from the vicinity of the pn-junction between the first base layer9and the drift layer4. Immediately after a depletion layer starts expanding, the area of the depletion layer edge is large and the depletion layer width is extremely small. Remaining charge carriers prevent the depletion layer from expanding. Therefore, the Miller capacitance is the largest in the turnoff that changes the IGBT from the ON-state to the OFF-state. Due to the largest Miller capacitance, the turnoff time increases and the collector-emitter voltage rises slowly. Therefore, the switching loss of the transistor increases.

The Miller capacitance increases also in the turn-on that changes the IGBT from the OFF-state to the ON-state. In the blocking state before the turn-on, a sufficiently high voltage is applied between the collector electrode2and the emitter electrode3and the charge carries are not in the vicinity of the first insulating layer12′ due to a depletion layer formed at the pn junction between the first base layer9and the drift layer4. The depletion layer abuts the buffer layer5in the X direction; thus, the width of the depletion layer is substantially the same as a thickness of the drift layer4. Therefore, the Miller capacitance is small. However, as soon as the turn-on process starts, the depletion layer width is reduced and carriers are injected from the source region7. Especially as the collector-emitter voltage decreases, the area of the depletion layer increases, and the depletion layer width becomes small. Therefore, the Miller capacitance increases. As a result, the fall (starting point of the decrease) of the collector-emitter voltage is delayed and the switching loss of the transistor is increased. For reducing the switching loss of the transistor by reducing the Miller capacitance, it is thus necessary to include a fortifying p-type region9′ in a wide range. The fortifying regions9′ can be electrically floating, or can be connected to the emitter electrode3(or other electrical potentials) through contact regions spaced apart from each other (not shown in Figures).

In the first exemplary embodiment, the fortified region9′ is formed such that the second end walls90′ of the trench recesses of the first gate electrodes11abut this region. In the case of Silicon based transistors, where the drift layer4is formed of Silicon crystal, the region9′ must extend along X direction to a distance from the side31of 2 μm and even more than 3 μm. Such a dopant profile can be achieved through different means, for example by tilted ion implantation through the lateral wall90′. The fortified region9′ can also be created by ion implantation from the emitter side31.

When the drift layer4is formed of a material of wide bandgap such as Silicon Carbide, Gallium Nitride, Gallium Oxide, etc. the depth of the trench recesses can be smaller than 2 μm or even smaller than 1 μm. In this case, it may be possible to form the region9′ by deep ion implantation such that the highest dopant concentration in this region is located entirely below the surface31.

The presence of the fortified layer9′ has three major effects on the performance of the semiconductor transistor1. The first effect is to protect the corner of the trench recesses from the damaging effects of high electric fields that develop in the OFF-state of the transistor. The second effect is to reduce the parasitic capacitance associated with the overlap between the first gate electrodes11and the drift layer4. Thus, the semiconductor device has an overall improved performance when turning on and off between the ON-state and the OFF-state, and the power requirements of the gate driver (directly related to the Miller capacitance) are reduced. The third effect is related to the ease of removal of charge carriers accumulated in the ON-state in the fortifying layer9′. Unlike today's trench gate semiconductors, the fortifying layer9′ is not isolated from the emitter electrode3by trench gates that prevent the flow of charge carriers to the emitter electrode3during the transition from the ON-state to the OFF-state, thus increasing the switching losses. In the first exemplary embodiment, there is a direct path to quickly deplete the fortifying layer9′ because the trench gate electrodes11are allowing a direct path through the drift layer4for the charge carriers to reach the emitter electrode3.

In a second exemplary embodiment shown inFIG.4, both trench walls90and90′ are abutting corresponding fortifying regions9′. One of the benefits of this approach is to protect all corners at the bottom of trench recesses, against high electric fields. The oppositely arranged regions9′ are separated by a portion of the drift region4to allow the electrons to flow in ON-state from the source region7, through the inversion layer formed on the lateral walls of the trench recesses of the first gate electrodes11, and to enter the drift region4.

In a third exemplary embodiment shown inFIG.5, a second gate electrode10is formed on the emitter side31of the drift layer4, separated from the drift layer4, the first base layer9, and the source region7by a second insulating layer12. The second gate electrode10can then ensure the electrical connectivity between the first gate electrodes11, so that no additional gate runners are required. The advantage of this second exemplary embodiment resides in the formation of an additional planar MOS channel15in the transistor cell, at the emitter side31in the first base region9overlapped by the second gate electrode10as shown in the cross-section fromFIG.6A. However, it may be that in certain designs it is desirable to electrically disconnect some of the first gate electrodes11from portions of the second gate electrodes10, in order to optimize certain static or dynamic functional parameters. Another advantage of the third exemplary embodiment resides in simplifying the manufacturing process, in particular reducing the number of masks needed to structure the source region7and the first base layer9. This is because the second gate electrode10can also be used as a mask for ion implantation.

In a fourth exemplary embodiment depicted inFIG.7, the first insulated layer covering the walls of the trench recesses of the first gate electrodes11will have a substantially different thickness in regions that do not abut the first base layer9. In such an arrangement, the thickness of the first insulated layer12′ is kept at a standard value in the portions of the first insulated layer wherein an inversion layer is formed in the first base layer9, when a voltage is applied on the first gate electrodes11. The standard value thickness is dependent on the voltage threshold requirements of the semiconductor device and on the material of the drift layer4. However, in other portions12″ of the first insulated layer, which are further away from and not abutting the first base layer9, the thickness of the insulating layer can be increased. In these regions, the parasitic capacitance associated with the first gate electrodes11overlapping the drift layer4through the first insulated layer12′ will be significantly reduced, as the thickness of the portions12″ is increased. This is better understood in the cross-section depicted inFIG.8A. The thickness of the insulated layer covering the bottom of the trench recesses can also be made thicker (as shown in theFIG.8B), in order to further decrease the parasitic capacitances and protect the corners of the trench recesses from the damaging effects of high electric fields.

The first edges of the doped regions defining the source region7and the second base layer8, are defined as being positioned in the Y direction furthermost from the contact opening14, and closer to the first wall90of the first gate electrodes11. In the above-described embodiments, the first edges of the source region7and of the second base layer8were substantially formed at the same position in the Y direction and a MOS channel was only formed on the lateral walls of the first gate electrodes11. However,FIG.9depicts a cross section through a fifth exemplary embodiment of the invention, wherein a separation region60with a length greater than zero spaces apart, in the Y direction, the first edge of the source region7and the first edge of the second base layer8. The second base layer8does not fully protect the bottom side of the source region7as indicated in theFIG.9. In this fifth embodiment, the trench recesses of the first gate electrodes11abut the source region7, but not the second base layer8. In a similar manner to the first exemplary embodiment, an inversion layer can be formed on the lateral trench walls of the first gate electrodes11, and additionally a vertical MOS channel16is formed on the first end wall90of the trench recesses, in regions where the trench recesses abut the first base layer9. This significantly increases the width of the total MOS channel of the semiconductor device. However, when the length of the separation region60is greater than 0, the highly doped second base layer8does not fully protect the bottom side of the source region7, which may impact the Reverse Blocking Safe Operating Area (RB-SOA), i.e., the source region7may become forward biased, and may inject electron charge carriers in the drift layer4, leading to a latch up phenomena. Therefore, a proper optimization of the separation distance60must be considering for each semiconductor transistor cell taking into account the trade-offs between electrical performance criteria.

In a sixth exemplary embodiment depicted inFIG.10, the fortifying layer9′ is formed such that its highest dopant concentration is localized at a depth in the drift layer4comparable to the depth of the trench recesses of the first gate electrodes11. Such an arrangement can be obtained by using high energy implantation of dopant atoms, and has the advantage of not requiring dopant diffusion/activation of dopants for extended times, in order to obtain a dopant profile extending all the way from the emitter side31to the depth of the trench recesses.

In a further embodiment, the extension direction of the first gate electrodes11can form other angles different than 90° with respect to the Z direction. This may provide certain benefits if the drift layer4is formed of materials with strong dependence between their electrical properties and their crystallographic directions, such as Silicon Carbide.

As described previously, multiple active cells must be arranged on a semiconductor wafer of a starting material to form a fully functional semiconductor device. In addition to the active cells, the fully functional semiconductor device may comprise other regions, such as a junction termination region required for achieving voltage blocking capabilities. In terms of arranging multiple active cells, various layouts can be considered. For example, in addition to the stripe layouts depicted inFIG.2,5, or7, it can be possible to arrange the layers in other shapes, such as squares, hexagons, octagons, etc.

In order to address possible short circuit operating conditions, it can also be possible to structure the transistor active cells1in such a manner, that the source region7is omitted in between multiple adjacent trench regions of first gate electrodes11.

The second gate electrode10can be electrically grounded or left floating. Consequently, no inversion layer can be formed at the emitter side31of the first base layer9, under the second gate electrode10. Because there is no electrical connection to the first gate electrodes11, the operation of the first gate electrodes11remains independent from second gate electrodes10, and follows the same phenomenon as a described previously, with the electrons flowing along the lateral walls40of the trench regions when the voltage applied to the gate electrodes11is greater than a threshold value.

A further embodiment is a reverse conducting type of power semiconductor, wherein the collector layer2can be formed of alternating regions of p doped6and n doped18material. In this case, there will be a diode formed in parallel with the transistor in the same cell. The performance of the diode part will be heavily influenced by the emitter side structure of the transistor cell. With the embodiments disclosed in this patent application, it will be possible to better control the trade-off performance curves for the diode part, without negatively affecting the transistor part.

In a further embodiment, the drift region4can consist of pillars of alternating p-type and n-type doping conductivity, or a so called “charge-compensated” or “superjunction” semiconductor device. Such a semiconductor device, although more difficult to manufacture, can show improvement in the ON-state losses as well as switching losses as the thickness of the drift region4can be minimized, and its doping concentration can be increased.

In a further embodiment, a charge carrier enhancement layer can be arranged between the drift layer4and the first base layer9, with the purpose of further enhancing the electron-hole plasma concentration at the emitter side31. To achieve this effect, the doping of the enhancement layer may be larger than the doping of the drift layer4.

In other embodiments, the material of the drift layer can be different than Silicon, for example it may be made of Silicon Carbide, Gallium Nitride, Gallium Oxide, Zinc Oxide or the like. In this case, the same embodiments as described above can be applied, however the specific dimensions and dopant profiles have to be adjusted accordingly by means known to experts in the field. More specifically, if the drift layer4is made of Silicon material, the trench recesses of the first gate electrodes11may extend vertically to a depth approximately in a range from about 2 μm to about 7 μm. The trench width may range from about 3 μm to about 0.5 μm. However, if the drift layer4comprises wide band gap materials such as Silicon Carbide or Gallium Nitride or Gallium Oxide or Zinc Oxide, the depth and width of the trench recesses have different dimensions than above, for example the depth can be also smaller than 2 μm.

In addition, for some of the additional embodiments comprising wide bandgap materials, the buffer layer5and the collector layer6may be omitted, in particular if the power semiconductor device is a MOSFET device with unipolar conduction i.e. majority charge carriers only.

Furthermore, in other embodiments, it can be possible that the power semiconductor is made of a multitude of different transistor cells, but not all cells may be of the same design. For example, the power semiconductor device may be formed with some transistor cells having the first exemplary embodiment, and with some transistor cells having a different design covered in the previous embodiments, or in the prior art.

It is also possible to apply the invention to power semiconductor devices, in which the conductivity type of all layers is reversed, i.e. with a lightly p doped drift layer etc.

In most applications, power semiconductors are not used in bare die form. Therefore, in a further embodiment to this patent application, multiple power semiconductors of any of the previous embodiments may be mounted as single or parallel connected chips on a substrate using techniques such as soldering or sintering. An additional enclosure, protective layers, sensors, and internal/external metal connectors are usually added to form the basis for a power module, with the role of protecting the power semiconductors from damaging environmental factors (mechanical pressure, humidity, high temperatures, electrical discharges etc).

The power modules may be subsequently used in power converters that control the flow of electrical current between a source and a load. The source may be a DC type battery for example, and the load may be an electrical motor. Typical converter topologies that could make use of semiconductor devices with transistor cells according to any previous exemplary embodiments are two-, three- or other multi-level converters, H-bridge or resonant switching.

REFERENCE LIST

1: inventive transistor cell layout for semiconductor devices3: emitter metallization (electrode)31: emitter side2: collector metallization (electrode)21: collector side4: drift layer, substrate5: buffer layer6: collector layer7: n source layer8: p second base layer9: p first base layer10: second gate electrode, electrically conductive layer11: first gate electrode, electrically conductive layer12: second insulating layer12′: first insulating layer12″: regions of the first insulating layer with increased dielectric thickness13: third insulating layer14: emitter contact opening15: horizontal channel for planar gate16: vertical channel for trench gate17: enhancement layer18: collector shorts60: separation region between the first edge of the source region, and the first edge of the second base layer (in the Y dimension)90: first end trench wall90′: second end trench wall301: trench MOS cell power semiconductor device (prior art)