Patent ID: 12199124

DETAILED DESCRIPTION

(Overview of the Present Disclosure)

Non-limiting and exemplary embodiments of the present disclosure provides the followings.

An imaging device according to one aspect of the present disclosure includes a semiconductor substrate and pixels. Each of the pixels includes a first capacitive element including a first electrode provided above the semiconductor substrate, a second electrode provided above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one selected from the group consisting of the first electrode and the second electrode has a first electrical contact point electrically connected to a first electrical element and a second electrical contact point electrically connected to a second electrical element different from the first electrical element. The first capacitive element includes at least one trench portion having a trench shape.

Thus, since the first capacitive element is provided with two or more electrical contact points, it is possible to increase the degree of freedom of a layout of wires that provide electrical connection between the first capacitive element and the electrical elements. Thus, for example, since wires can be provided so that a parasitic capacitance between wires becomes less likely to occur even in a small pixel region, noise can be reduced. Thus, it is possible to realize an imaging device that can further reduce noise. Also, since an increase in the degree of freedom of the layout of the wires can reduce the pixel area, the imaging device is miniaturized.

For example, at least one selected from the group consisting of the first electrical contact point and the second electrical contact point may be provided at the at least one trench portion. For example, the at least one selected from the group consisting of the first electrical contact point and the second electrical contact point may be provided at a bottom surface of the at least one trench portion. For example, the first electrical contact point may be provided at the at least one trench portion, and the second electrical contact point may be provided at a portion other than the at least one trench portion.

As described above, the bottom surface or a side surface of the trench portion can be used to establish electrical connection with the electrical elements. That is, since the electrical contact points can be provided not only at a planar portion of the first capacitive element but also at a portion other than the planar portion, it is possible to enhance the degree of freedom of the wire layout.

For example, the at least one trench portion may include a plurality of trench portions, and the plurality of trench portions may include a trench portion where the first electrical contact point and the second electrical contact point are not provided.

This makes it possible to increase the capacitance value of the first capacitive element, while suppressing an increase in the area occupied by the first capacitive element in a plan view. That is, the first capacitive element having a large capacitance value can be provided in a small pixel area.

For example, the first electrode may be closer to the semiconductor substrate than the second electrode and may have the first electrical contact point and the second electrical contact point.

With this arrangement, for example, vias or exposed portions of wiring portions can be exposed to plasma during formation of trenches, and the exposed portions can be activated. When the exposed portions and the first electrode of the first capacitive element are connected at the contact points, it is possible to reduce the contact resistance between the vias or the wiring portions and the first electrode. A reduction in the contact resistance can reduce variations in contact resistances among the pixels, thus making it possible to suppress roughness in an image generated by the imaging device. Thus, it is possible to realize an imaging device that can further reduce noise.

For example, the second electrode may be farther from the semiconductor substrate than the first electrode and may have the first electrical contact point and the second electrical contact point.

With this arrangement, since the electrode provided with the electrical contact points is not limited to the first electrode, it is possible to further enhance the degree of freedom of the wire layout.

For example, the first electrode and the second electrode may contain titanium nitride (TiN) or tantalum nitride (TaN).

This makes it possible to form a first electrode and a second electrode having low surface roughness. Accordingly, since variations in the distance between the first electrode and the second electrode are suppressed, it is also possible to suppress variations in the capacitance value of the first capacitive element.

For example, the imaging device according to one aspect of the present disclosure may further include a plurality of wiring layers provided at an upper side of the semiconductor substrate. Of the plurality of wiring layers, the number of wiring layers located at an upper side of the first capacitive element may be larger than the number of wiring layers located at a lower side of the first capacitive element.

In many cases, impurity regions that serve as parts of photoelectric converters for accumulating signal charge generated by charge accumulation portions are formed at a semiconductor substrate. Since the number of wiring layers that are close to the semiconductor substrate can be reduced, it is possible to suppress variations in the potentials of the charge accumulation portions, the variations being caused by parasitic capacitance components in the wiring layers. Accordingly, it is possible to realize an imaging device that can further reduce noise.

For example, the imaging device may further include vias, and each of the first electrical contact point and the second electrical contact point may be connected to a corresponding one of the vias.

With this arrangement, for example, when upper ends of the vias are exposed to plasma during formation of the trenches, the upper ends of the vias are activated. This facilitates metal coupling between the upper ends of the vias and the electrodes of the first capacitive element, thus making it possible to reduce contact resistances between the vies and the electrodes of the first capacitive element.

For example, each of the pixels may further include: a photoelectric converter that converts light into charge; and an impurity region that is provided in the semiconductor substrate, the impurity region being electrically connected to the photoelectric converter. The charge may be accumulated in the impurity region. In a plan view, the first capacitive element may overlap the entire impurity region.

With this arrangement, when the first electrode or the second electrode is formed using material having a light-shielding property, the first capacitive element can suppress light incident on the imaging device reaching the impurity region. Thus, it is possible to suppress generation of unwanted charge in the impurity region, thus making it possible to further reduce noise.

For example, each of the pixels may further include: a photoelectric converter that converts light into charge; an impurity region that is provided in the semiconductor substrate, the impurity region being electrically connected to the photoelectric converter; a transistor electrically connected to the impurity region; and a second capacitive element. The charge may be accumulated in the impurity region. The transistor may be one of the first electrical contact point and the second electrical contact point, and the second capacitive element may be the other of the first electrical contact point and the second electrical contact point. For example, the transistor may be a reset transistor that resets the charge.

Thus, the first electrode or the second electrode can be made to have the same potential as the potential of one electrode of the second capacitive element and the potential of a source region or a drain region of the transistor. For example, the first electrode or the second electrode;one electrode of the second capacitive element, and the source region or the drain region of the transistor can be utilized as reset drain nodes.

For example, the second capacitive element may be electrically connected to the impurity region via the first electrode or the second electrode.

Thus, the first electrode or the second electrode of the first capacitive element can be utilized as a part of a wire. Thus, since a dedicated wire that is needed for electrical connection can be reduced, the space in each pixel can be increased, thus making it possible to further increase the degree of freedom of layout of other wires.

For example, each of the pixels may further include: a photoelectric converter that converts light into charge; and an impurity region that is provided in the semiconductor substrate, the impurity region being electrically connected to the photoelectric converter. The charge may be accumulated in the impurity region. The first electrode may be closer to the semiconductor substrate than the second electrode and may be electrically connected to the impurity region. The second electrode may be electrically connected to a pad to which a predetermined voltage value is applied.

This allows the potential of the first capacitive element to be adjusted with the voltage applied to the pad.

For example, the imaging device may further include a sensitivity adjustment line for adjusting sensitivity of the imaging device, the sensitivity adjustment line being electrically connected to the pad and the second electrode.

This allows the sensitivity to be adjusted according to the amount of light that is incident on the imaging device, and thus the dynamic range of the imaging device can be increased ranging from dark scenes to bright scenes.

For example, the imaging device may further include a signal line that is connected to the pixels. A potential of the signal line may vary with time. Each of the pixels may further include an impurity region that is provided in the semiconductor substrate. Charge generated by photoelectric conversion may be accumulated in the impurity region. The at least one trench portion may be located between the impurity region and the signal line and on a line that connects the impurity region and at least a part of the signal line. For example, the imaging device may further include a signal line that is connected to the pixels. A potential of the signal line may vary with time. Each of the pixels may further includea photoelectric converter that converts light into charge,a first via that connects the semiconductor substrate and the photoelectric converter, anda second via that connects the signal line and the semiconductor substrate. The at least one trench portion may be located between the first via and the second via and on a line that connects the first via and the second via. For example, the imaging device may further include a signal line that is connected to the pixels. A potential of the signal line may vary with time. Each of the pixels may further include a second via that connects the signal line and the semiconductor substrate. In a plan view, the first capacitive element does not necessarily have to overlap the second via.

For example, each of the pixels may further includea photoelectric converter that converts light into charge, anda first via that connects the semiconductor substrate and the photoelectric. The at least one trench portion may include a first trench portion and a second trench portion. In a sectional view, the first via is located between the first trench portion and the second trench portion. Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and/or advantages may be individually obtained by the various embodiments and features of the specification and drawings, which need not all be provided in order to obtain one or more of such benefits and/or advantages.

Embodiments will be described below in detail with reference to the accompanying drawings.

The embodiments described below each present a general or specific example. Numerical values, shapes, materials, constituent elements, the arrangement positions and connection forms of constituent elements, steps, the order of steps, and so on described in the embodiments below are merely examples and are not intended to limit the present disclosure. Also, of the constituent elements in the embodiments below, constituent elements not set h in the independent claim will be described as optional constituent elements.

Also, the drawings are schematic diagrams and are not necessarily strictly illustrated. Accordingly, for example, scales and so on do not necessarily match in each drawing. In the individual drawings, substantially the same constituent elements are denoted by the same reference numerals, and redundant descriptions are omitted or are briefly given.

Also, herein, the terms “parallel”, “orthogonal”, and so on representing relationships between elements, terms representing element shapes, and the ranges of numerical values are not expressions representing only exact meanings and are expressions representing substantially equivalent ranges, for example, expressions meaning that they include differences of about several percent.

Also, herein, the terms “upper side”, “top”, and “upper” and the terms “lower side”, “bottom”, and “lower” do not refer to an upper direction (a vertically upper side) and a lower direction (a vertically lower side) in absolute spatial recognition and are used as terms defined by relative positional relationships based on the order of laminated layers in a laminate configuration. Also, the terms “upper side” and “lower side” apply not only to cases in which two constituent elements are arranged with a gap therebetween and a constituent element exists between the two constituent elements but also to cases in which two constituent elements are arranged to adhere to each other and contact each other.

Also, herein, the “plan view” refers to a view in a direction orthogonal to a major surface of a semiconductor substrate.

First Embodiment

[1. Circuit Configuration]

FIG.1is a diagram showing an exemplary circuit configuration of an imaging device100according to a first embodiment. As illustrated inFIG.1, the imaging device100includes a plurality of pixels10and peripheral circuitry. The pixels10are, for example, two-dimensionally arrayed to form a pixel region RA. For simplicity, inFIG.1, four pixels10of the plurality of pixels10are illustrated, and the other pixels10are not illustrated.

For example, when the imaging device100complies with a video graphics array (VGA) standard, the imaging device100includes about three-hundred thousand pixels10arrayed in a matrix. Also, when the imaging device100complies with an 8K standard, the imaging device100includes about 36 million pixels10arrayed in a matrix. The above-described peripheral circuitry is arranged in a peripheral region outside the pixel region RA.

Needless to say, the number of pixels10and the arrangement thereof are not limited to this example. The array of the pixels10may be one-dimensional. In this case, the imaging device100can be used as a line sensor.

The pixels10are connected to power-supply wires22. During operation of the imaging device100, a predetermined power-supply voltage ANDD is applied to the pixels10through the power-supply wires22. Accumulation control lines17are connected to the pixels10. As will be described later in detail, each of the pixels10includes a photoelectric converter that photoelectrically converts incident light and a signal detection circuit that detects a signal generated by the photoelectric converter. In a typical embodiment, the accumulation control lines17apply a predetermined voltage to all the photoelectric converters in the pixels10.

In the configuration illustrated inFIG.1, the peripheral circuitry of the imaging device100includes a vertical scanning circuit16, a plurality of load circuits19, a plurality of column signal processing circuits20, a plurality of inverting amplifiers24, and a horizontal signal readout circuit21. The load circuit19, the column signal processing circuit20, and the inverting amplifier24are arranged for each column of the pixels10that are arrayed two-dimensionally. The vertical scanning circuit is also called a row scanning circuit. The column signal processing circuits are also called row signal accumulation circuits. The horizontal signal readout circuit is also called a column scanning circuit.

Address signal lines30and reset signal lines26are connected to the vertical scanning circuit16. The vertical scanning circuit16applies a predetermined voltage to the address signal lines30to thereby select, for each row, the pixels10arranged in the row, As a result of selecting the pixels10for each row, readout of signal voltages of the selected pixels10and reset of signal charge described below are executed.

In the illustrated example, feedback control lines28and sensitivity adjustment lines32are further connected to the vertical scanning circuit16. The vertical scanning circuit16applies a predetermined voltage to the feedback control lines28to thereby form feedback loops for negatively feeding back outputs of the pixels10. Also, the vertical scanning circuit16can supply a predetermined voltage to the pixels10via the sensitivity adjustment lines32.

The imaging device100has vertical signal lines18provided for the respective columns of the pixels10. The load circuits19are electrically connected to the vertical signal lines18, respectively. The pixels10are electrically connected to the column signal processing circuits20through the corresponding vertical signal lines18.

The column signal processing circuits20perform noise suppression signal processing typified by correlated double sampling, analog-to-digital conversion, and so on. The horizontal signal readout circuit21is electrically connected to the column signal processing circuits20provided corresponding to the respective columns of the pixels10. The horizontal signal readout circuit21sequentially reads out signals from the column signal processing circuits20to a horizontal common signal line23.

As illustrated inFIG.1, the power-supply wires22, feedback lines25, and the vertical signal lines18extend in upper and lower directions inFIG.1, that is, in column directions of the pixels10. Each of the feedback lines25and each of the vertical signal lines18, the feedback lines25and the vertical signal lines18being provided for the corresponding columns of the pixels10, have connections with corresponding two or more pixels10that are arranged along the column directions. Meanwhile, the accumulation control lines17, the reset signal lines26, the feedback control lines28, the address signal lines30, and the sensitivity adjustment lines32extend, for example, in row directions of the pixels10. These signal lines are connected to each of the pixels10arranged in the row directions, The accumulation control lines17and the sensitivity adjustment lines32may extend in the column directions of the pixels10. The accumulation control lines17and the sensitivity adjustment lines32may be connected to the pixels10arranged in the column directions.

In the configuration illustrated inFIG.1, the inverting amplifiers24are provided corresponding to the respective columns of the pixels10. A negative-side input terminal of each inverting amplifier24is connected to the corresponding vertical signal line18, and a predetermined voltage Vref is supplied to a positive-side input terminal of each inverting amplifier24. The voltage Vref is, for example, a positive voltage of 1 V or around 1 V. An output terminal of each inverting amplifier24is connected to the pixels10having connections with the negative-side input terminal of the inverting amplifier24through one of the feedback lines25provided corresponding to the columns of the pixels10. Each inverting amplifier24constitutes a part of the feedback circuit for negatively feeding back outputs from the pixels10. The inverting amplifiers24may be called feedback amplifiers.

FIG.2is a diagram showing one example of the circuit configuration of each of the pixels10included in the imaging device100according to the present embodiment. In the present embodiment, the pixels10included in the imaging device100have substantially the same configuration.

As illustrated inFIG.2, each pixel10includes a photoelectric converter15and a signal detection circuit SC. In the configuration illustrated inFIG.2, the imaging device100includes a feedback circuit FC for negatively feeding back outputs of the signal detection circuit SC.

The photoelectric converter15has a first electrode15a, a photoelectric conversion layer15b, and a second electrode15c, which serves as a pixel electrode. The first electrode15aof the photoelectric converter15is connected to the corresponding accumulation control line17. The second electrode15cof the photoelectric converter15is connected to a charge accumulation node44. Controlling the potential of the first electrode15athrough the accumulation control line17allows the second electrode15cto collect charge having one of the polarities of positive (specifically, holes) charge and negative charge (specifically, electrons) generated in the photoelectric conversion layer15bby photoelectric conversion. For example, when holes are used as the signal charge, it is sufficient that the potential of the first electrode15abe made higher than the potential of the second electrode15c.A case in which holes are used as the signal charge will be described below by way of example. For example, a voltage of about 10 V is applied to the first electrode15athrough the accumulation control line17. As a result, signal charge is accumulated at the charge accumulation node44. Electrons may also be used as the signal charge.

The signal detection circuit SC includes a signal detection transistor34and a first capacitive element41. The signal detection transistor34amplifies a signal generated by the photoelectric converter15and outputs the signal. In the illustrated example, the signal detection circuit SC further includes a reset transistor36, a feedback transistor38, a second capacitive element42having a capacitance value smaller than that of the first capacitive element41, and an address transistor40. As described above, in the present embodiment, each of the pixels10has one or more capacitive elements therein. Since the first capacitive element41has a relatively large capacitance value, for example, kTC noise can be effectively reduced, as will be described later in detail. An example in which N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are used as transistors, such as the signal detection transistor34, will be described below.

A gate of the signal detection transistor34is connected to the charge accumulation node44. In other words, a gate of the signal detection transistor34is connected to the second electrode15c.A drain of the signal detection transistor34is connected to the power-supply wire22, which serves as a source-follower power supply, and a source of the signal detection transistor34is connected to the vertical signal line18via the address transistor40. The signal detection transistor34and the load circuit19(seeFIG.1), which is not illustrated inFIG.2, constitute a source follower circuit.

In the example illustrated inFIG.2, the address transistor40is connected between the source of the signal detection transistor34and the vertical signal line18. A gate of the address transistor40is connected to the address signal line30. When signal charge is accumulated in the charge accumulation node44, a voltage corresponding to the amount of the accumulated signal charge is applied to the gate of the signal detection transistor34. The signal detection transistor34amplifies the voltage applied to the gate thereof. When the address transistor40is turned on, the voltage amplified by the signal detection transistor34is selectively read out as a signal voltage. The address transistor40may be connected between the drain of the signal detection transistor34and the power-supply wire22. That is, the drain of the signal detection transistor34may be connected to the power-supply wire22via the address transistor40,

In the configuration illustrated inFIG.2, one of a pair of electrodes of the first capacitive element41is connected to the sensitivity adjustment line32. A pad is connected to the sensitivity adjustment line32, and the potential of the sensitivity adjustment lines32is adjusted with a voltage applied to the pad. For example, during operation of the imaging device100, the potential of the sensitivity adjustment line32is fixed to a certain potential, such as 0 V. The sensitivity adjustment line32can be used to control the potential of the charge accumulation node44. The other of the pair of electrodes of the first capacitive element41is connected to one of a pair of electrodes of the second capacitive element42. A node including a connection point of the first capacitive element41and the second capacitive element42may hereinafter be referred to as a “reset drain node46”.

The other of the pair of electrodes of the second capacitive element42is connected to the charge accumulation node44. That is, of the pair of electrodes of the second capacitive element42, the electrode that is not connected to the reset drain node46has electrical connection with the second electrode15cof the photoelectric converter15. In the example illustrated inFIG.2, the reset transistor36is connected in parallel with the second capacitive element42. A gate of the reset transistor36is connected to the reset signal line26.

In the configuration illustrated in Fig,2, the pixel10includes the feedback transistor38. As illustrated inFIG.2, one of a source and a drain of the feedback transistor38is connected to the reset drain node46. The other of the source and the drain of the feedback transistor38is connected to the feedback line25. A gate of the feedback transistor38is connected to the feedback control line28.

[2. Device Structure of Pixels]

Next, one example of the device structure of each pixel10will be described with reference toFIGS.3to5.

FIG.3is a schematic sectional view of each pixel10included in the imaging device100according to the present embodiment.FIG.4is a schematic plan view showing one example of a layout of elements included in each pixel10included in the imaging device100according to the present embodiment,FIG.3schematically illustrates a cross section along line111-111illustrated inFIG.4.

InFIG.3, hatching indicating a cross section is not applied to insulating layers4a,4b,4c,4d,4e, and4fincluded in an interlayer insulating layer4. The same applies toFIGS.6A to6I,FIGS.7and8, andFIGS.12to15, which are described below.

As illustrated inFIG.4, the imaging device100has a semiconductor substrate2. For example, a silicon substrate can be used as the semiconductor substrate2. The semiconductor substrate2is not limited to a substrate that is entirely made of semiconductor material. For example, the semiconductor substrate2may be an insulating substrate having a semiconductor layer on its surface. In this case, a p-type silicon substrate will be described as the semiconductor substrate2by way of example.

The pixels10are formed at the semiconductor substrate2. An element isolation region2tformed in the semiconductor substrate2electrically isolate each of the pixels10from the other pixels10. The element isolation region2tis formed, for example, by acceptor ion-implantation under a predetermined implantation condition.

In the example illustrated inFIG.3, the interlayer insulating layer4that covers the semiconductor substrate2is arranged between the semiconductor substrate2and the photoelectric converter15. The interlayer insulating layer4has a laminated structure of the insulating layers4a,4b,4c,4d,4e, and4f.Each of the insulating layers4a,4b,4c,4d,4e, and4fis formed of, for example, silicon dioxide, In this example, the photoelectric converter15is located on the insulating layer4fthat is located farthest from the semiconductor substrate2.

Impurity regions2a,2b, and2care formed in the semiconductor substrate2. All the impurity regions2a,2b, and2care, for example, regions where N-type dopants are diffused. A gate insulating layer36gand a gate electrode36eof the reset transistor36are provided in that order in a region located on a major surface of the semiconductor substrate2and between the impurity regions2aand2b. Also, a gate insulating layer38gand a gate electrode38eof the feedback transistor38are provided in that order in a region located on the major surface of the semiconductor substrate2and between the impurity regions2band2c.The major surface of the semiconductor substrate2is a surface that is included in a plurality of surfaces of the semiconductor substrate2and at which the interlayer insulating layer4and the photoelectric converter15are provided. The major surface of the semiconductor substrate2is covered by the insulating layer4ain the interlayer insulating layer4.

The impurity region2afunctions as one of a drain region and a source region of the reset transistor36. The impurity region2bfunctions as the other of the drain region and the source region of the reset transistor36. In the example illustrated inFIG.3, the reset transistor36and the feedback transistor38share the impurity region2band are thereby electrically connected to each other. That is, the impurity region2balso functions as one of a drain region and a source region of the feedback transistor38.

The impurity region2cfunctions as the other of the drain region and the source region of the feedback transistor38. The impurity region2cis connected to the feedback line25, which extends across two or more of the pixels10, through a plug, a via, and a wiring layer arranged in the interlayer insulating layer4. As illustrated inFIG.1, the feedback line25is a signal line that extends to outside of the pixel region RA.

In the configuration illustrated inFIG.3, a portion included in the feedback line25and located in one pixel10of interest is included in a wiring layer51located between the second electrode15cof the photoelectric converter15and the semiconductor substrate2. Also, a wiring layer52located in the same layer as the wiring layer51also includes a portion included in the vertical signal line18and located in the pixel10of interest. That is, in this example, in the pixel10, the vertical signal line18and the feedback line25are located in the same layer, Similarly to the feedback line25, the vertical signal line18is also a signal line that extends to outside of the pixel region RA.

The “same layer” means being located in a common insulating layer. In this case, when the common insulating layer is a planarization film, heights from the major surface of the semiconductor substrate2become substantially equal to each other.

Also, the signal lines that extend to outside of the pixel region RA include not only the vertical signal line18and the feedback line25but also the reset signal line26, the feedback control line28, the address signal line30, and the sensitivity adjustment line32. At least one of the wiring layer51or the wiring layer52may include parts of the reset signal line26, the feedback control line28, the address signal line30, or the sensitivity adjustment line32, each of which being a control line for driving two or more pixels.

A gate insulating layer34gand a gate electrode34eof the signal detection transistor34are further provided on the major surface of the semiconductor substrate2in that order. As can be understood with reference toFIG.4, a drain region and a source region of the signal detection transistor34are located at the front side and the back side, respectively, of the plane ofFIG.3. In the example illustrated inFIG.3, a pair of the reset transistor36and the feedback transistor38and a pair of the signal detection transistor34and the address transistor40(not illustrated inFIG.3) are isolated by an element isolation region2u.Similarly to the element isolation region2t,the element isolation region2ucan be formed, for example, by acceptor ion-implantation under a predetermined implantation condition. Each of the element isolation regions2tand2umay be an insulation region formed by a shallow trench isolation (STI) process. The element isolation regions2tand2uare integrally formed in the pixel region RA.

As illustrated inFIG.3, each pixel10has, in the interlayer insulating layer4, a connection portion50that electrically connects the impurity region2ain the semiconductor substrate2to the second electrode15cof the photoelectric converter15. The impurity region2ais one example of an impurity region electrically connected to the photoelectric converter15. The impurity region2afunctions as at least one part of a charge accumulation region in which signal charge generated by the photoelectric converter15is accumulated.

The connection portion50includes plugs P1and P2and a wiring portion50a.A lower end of the plug P1is connected to the impurity region2ain the semiconductor substrate2, and an upper end of the plug P1is connection to the wiring portion50a. A lower end of the plug P2is connected to the gate electrode34eof the signal detection transistor34, and an upper end of the plug P2is connected to the wiring portion50a. The wiring portion50aprovides mutual connection between the plug P1and the plug P2. The plugs P1and P2and the wiring portion50aprovide electrical interconnection between the impurity region2aand the gate electrode34e.That is, the impurity region2a, which functions as the drain region or the source region of the reset transistor36, and the gate electrode34eof the signal detection transistor34are electrically connected to the second electrode15cof the photoelectric converter15via the connection portion50.

The plugs P1and P2and the wiring portion50aare formed using electrically conductive material. For example, the plugs P1and P2and the wiring portion50aare formed using polysilicon given electrical conductivity by impurity doping. At least one of the plug P1, the plug P2, or the wiring portion50amay be formed using metal material, such as copper.

The connection portion50further includes wiring layers50band50cand vias50d,50e, and50f.The via50d, the wiring layer50b,the via50e, the wiring layer50c, and the via50fare provided between the wiring portion50aand the second electrode15cin that order from the semiconductor substrate2. The wiring layers50band50cand the vias50d,50e, and50fare formed, for example, using metal material, such as copper. Alternatively, the wiring layers50band50cand the vias50d,50e, and50fmay be formed using electrically conductive material, such as polysilicon given electrical conductivity, other than metal material.

As illustrated inFIG.3, the wiring layer50bis located in the same layer as the wiring layers51and52. For example, the wiring layer50b,the wiring layer51, and the wiring layer52can be formed at the same time. In this case, the wiring layer50b,the wiring layer51, and the wiring layer52are the same in thickness and material. Accordingly, the wiring layers51and52may also be formed of metal, such as copper.

The number of wiring layers arranged in the interlayer insulating layer4and the number of insulating layers in the interlayer insulating layer4are not limited to the example illustrated inFIG.3and ca be set arbitrarily.

The photoelectric converter15supported by the semiconductor substrate2includes the first electrode15a, the photoelectric conversion layer15b, and the second electrode15c. The photoelectric converter15has a structure in which the photoelectric conversion layer15bis sandwiched between the first electrode15aand the second electrode15c.

The first electrode15aof the photoelectric converter15is provided at a side on which light from a subject is incident. The first electrode15ais formed of transparent electrically conductive material, such as indium tin oxide (ITO). The first electrode15amay be formed directly on the photoelectric conversion layer15bor another layer may be arranged between the first electrode15aand the photoelectric conversion layer15b.

In response to incidence of light, the photoelectric conversion layer15bcauses positive and negative charge, specifically, hole-electron pairs, to be generated. The photoelectric conversion layer15bis formed of organic material or inorganic material, such as amorphous silicon. The photoelectric conversion layer15bmay include a layer composed of organic material and a layer composed of inorganic material.

The second electrode15cis located closer to the semiconductor substrate2than the first electrode15aand the photoelectric conversion layer15b. The second electrodes15care provided separately for the respective pixels10. Specifically, each second electrode15cis spatially isolated from the second electrodes15cin other adjacent pixels10, so that the second electrode15cis electrically isolated therefrom. The second electrode15ccollects charge generated by photoelectric conversion in the photoelectric conversion layer15b. The second electrode15cis formed of, for example, metal such as aluminum or copper, metal nitride, polysilicon, or the like given electrical conductivity by impurity doping.

The first electrode15aand the photoelectric conversion layer15bare formed, for example, through two or more pixels10. Alternatively, similarly to the second electrode15c, at least one of the first electrode15aor the photoelectric conversion layer15bin one pixel10may be spatially isolated from the at least one electrode in another pixel10.

In the present embodiment, the first capacitive element41is provided in the interlayer insulating layer4between the photoelectric converter15and the semiconductor substrate2. Specifically, the first capacitive element41is located between the wiring layers51and52, which include at least parts of signal lines connected to two or more pixels10, and the semiconductor substrate2. In the configuration illustrated inFIG.3, the first capacitive element41is located between the wiring layers52and51, which respectively include a part of the vertical signal line18and a part of the feedback line25, and the semiconductor substrate2. In other words, in the present embodiment, the first capacitive element41has an arrangement such that it is located closer to the semiconductor substrate2than the wiring layers including parts of the signal lines connected to two or more pixels10. That is, in the present embodiment, of the wiring layers included in the imaging device100, the number of wiring layers located at an upper side of the first capacitive elements41is larger than the number of wiring layers located at a lower side of the first capacitive elements41. A wiring layer does not necessarily have to be provided at the lower side of the first capacitive elements41.

Each first capacitive element41has a top electrode41a, a bottom electrode41c, and a dielectric layer41barranged between the top electrode41aand the bottom electrode41c.The top electrode41ais one example of a second electrode and is located between the wiring layer52and the semiconductor substrate2in the sectional view inFIG.3. The bottom electrode41cis one example of a first electrode and is located between the top electrode41aand the semiconductor substrate2.

The bottom electrode41c, the dielectric layer41b, and the top electrode41aare laminated in that order from the semiconductor substrate2. The dielectric layer41bis in contact with the bottom electrode41cto cover the entire bottom electrode41c.The bottom electrode41cis covered by the dielectric layer41band is thus not exposed to outside. The top electrode41ais in contact with the dielectric layer41bto cover the dielectric layer41b. The top electrode41aand the bottom electrode41care not in contact with each other, since the dielectric layer41bis arranged therebetween.

The first capacitive element41is a trench capacitor. Specifically, the first capacitive element41includes at least one trench portion. In the example illustrated inFIG.3, the first capacitive element41includes a planar portion41dand two trench portions41eand41f. The two trench portions41eand41fare provided so as to sandwich the connection portion50therebetween in sectional view.

The planar portion41dis a portion that is included in the first capacitive element41and that is located on an upper surface of the insulating layer4c.The trench portion41eis a portion that is included in the first capacitive element41and that is located in a trench4tprovided in the insulating layer4c. The trench portion41fis a portion that is included in the first capacitive element41and that is located in a trench4uprovided in the insulating layer4c. In each of the planar portion41dand the trench portions41eand41f, the bottom electrode41cand the dielectric layer41bare formed with a generally uniform film thickness. The top electrode41ais provided so as to fill insides of the trenches4tand4u. Alternatively, the top electrode41amay also be formed with a generally uniform film thickness.

With this configuration, not only the planar portion41dbut also the trench portions41eand41fcontribute to a capacitance value of the first capacitive element41. Compared with a parallel flat plate capacitor that does not have the trench portions41eand41f, the first capacitive element41has a capacitance value increased by an amount corresponding to the surface areas of wall surfaces of the trenches4tand4u.Thus, since the first capacitive element41includes the trench portions41eand41f, it is possible to increase the capacitance value, while suppressing an increase in the area occupied in plan view. The first capacitive element41may have only one of the trench portions41eand41f.

In the present embodiment, at least one of the bottom electrode41cor the top electrode41ahas two or more electrical contact points. The two or more electrical contact points are electrically connected to different electrical elements, respectively. In the example illustrated inFIG.3, the bottom electrode41chas two contact points41gand41h.The two contact points41gand41hare provided at the trench portions41eand41f, respectively.

Specifically, the contact point41gis provided at a bottom surface of the trench portion41e.The bottom surface refers to a surface (specifically, a lower surface) of the trench portion41e,the surface being adjacent to the semiconductor substrate2. The contact point41gis a point of contact with a via v1at the bottom surface of the trench portion41e.The via v1is coupled to the impurity region2bvia a plug P3. That is, the contact point41gis electrically connected to the reset transistor36and the feedback transistor38. Each of the reset transistor36and the feedback transistor38is one example of an electrical element to which the contact point41gis electrically connected. As described above, one contact point included in the first capacitive element may be connected to a plurality of electrical elements.

The contact point41his provided at a bottom surface of the trench portion41f. The contact point41his a point of contact with a via v2at the bottom surface of the trench portion41f. The via v2is coupled to an electrode42a.The electrode42aoverlaps the gate electrode34ewith an insulating film42bbeing interposed therebetween. That is, the electrode42aand the gate electrode34eare included in the second capacitive element42. The second capacitive element42is one example of an electrical element to which the contact point41his electrically connected. As described above, the contact point41gand the contact point41hare respectively connected to the electrical elements that are different from each other.

A desired capacitance value can be realized for a capacitance value of the second capacitive element42by adjusting the material or the thickness of the insulating film42bor the area where the electrode42aand the gate electrode34eoverlap each other.

Although a method for forming the first capacitive element41is described later, providing the contact points41gand41hof the bottom electrode41cat the bottom surfaces of the trench portions41eand41fmakes it possible to reduce the value of contact resistance between the bottom electrode41cand the vias v1and v2. This makes it possible to suppress variations in the value of the contact resistance in each pixel10.

The bottom electrode41cof the first capacitive element41, the via v1, the plug P3, the via v2, and the electrode42aconstitute parts of the reset drain node46. As illustrated inFIG.2, the charge accumulation node44is electrically coupled with the reset drain node46via the second capacitive element42. Thus, the potential of the charge accumulation node44can vary upon a potential variation in the reset drain node46.

That is, even when the contact resistance between the bottom electrode41cand the vias v1and v2vary among the pixels10, this variation leads to a fluctuation of the potential of the reset drain node46. For example, even when light with the same amount of light is incident on the individual pixels10, and the same amounts of charge are generated by the photoelectric converters15, the potentials of the charge accumulation nodes44do not become the same among the pixels10when the potentials of the reset drain nodes46vary. Thus, an image that is acquired looks like noise (also called roughness) is occurring.

In the present embodiment, reducing the resistance values of the reset drain nodes46makes it possible to bring the potentials of the reset drain nodes46in all the pixels10close to a constant potential.

The top electrode41aof the first capacitive element41can be a part of the wiring layers located between the second electrode15cof the photoelectric converter15and the gate electrode34eof the signal detection transistor34. The top electrode41ais electrically connected to a pad not illustrated inFIG.3. The pad is, for example, a portion to which a predetermined voltage is applied. For example, the pad is connected to the top electrode41athrough the sensitivity adjustment line32. As illustrated inFIG.5, the top electrode41aextends in a plane that is parallel to the major surface of the semiconductor substrate2. The same applies to the bottom electrode41cand the dielectric layer41b.

Each of the top electrode41aand the bottom electrode41cis formed using electrically conductive material, such as metal or a metal compound. A metal simple substance, such as titanium (Ti), aluminum (Al), gold (Au), or platinum (Pt), or a metal alloy of two or more types thereof is used as the electrically conductive material, Alternatively, electrically conductive metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or hafnium nitride (HfN), may be used as the electrically conductive material. The top electrode41aand the bottom electrode41cmay be formed using the same type of material or may be formed using types of material that are different from each other.

The dielectric layer41bis formed using a so-called high-k material having a higher dielectric constant than silicon oxide. Specifically, the dielectric layer41bcontains hafnium (Hf) or zirconium (Zr) oxide of as a main component.

As described above, the first capacitive element41has a metal-insulator-metal (UM) structure in which a dielectric body is sandwiched between two electrodes formed of metal or a metal compound. In this case, in order to equalize the potentials of the reset drain nodes46in the pixels10, it is desirable that leakage current that flows between the top electrode41aand the bottom electrode41cbe reduced as much as possible. This is because, when leakage current is large, the charge of the reset drain node46flows through the sensitivity adjustment line32connected to the top electrode41a.

In theory, there should be no leakage current that flows via the dielectric layer41blocated between the top electrode41aand the bottom electrode41c. However, in the present embodiment, a high-k material having a high refractive index is used for the dielectric layer41bin order to increase the capacitance value of the first capacitive element41. Thus, the bandgap of the dielectric layer41bis reduced. Also, for the same purpose, the film thickness of the dielectric layer41bis reduced in a range of about 5 nm or more and about 40 nm or less. For these reasons, in practice, the leakage current tends to increase.

In order to suppress the leakage current, surface roughness of the top electrode41aand the bottom electrode41cmay be reduced. The leakage current and the surface roughness of each electrode have a relationship in which the leakage current increases as the surface roughness increases. For example, when the surface roughness of the top electrode41aand the bottom electrode41cis high, the thickness of the dielectric layer41bbecomes uneven. Since an electric field tends to be concentrated at a portion where the dielectric layer41bis thin, the leakage current is likely to increase.

In contrast, in the present embodiment, for example, TiN or TaN is used as the electrically conductive material of which the top electrode41aand the bottom electrode41care formed. Thus, since TiN or TaN allows the surface roughness to be reduced when it is deposited, the leakage current of the first capacitive element41can be suppressed. Also, making the surface roughness of the bottom electrode41cof the top electrode41auniform can also contribute to suppressing variations in the capacitance value of the first capacitive element41in each pixel10. Also, since TiN or TaN has a low sheet resistance, it is possible to reduce resistance components that occur at the reset drain node46.

FIG.5is a schematic plan view showing one example of the shapes and the arrangements of the first capacitive element41and the trench portions41eand41fincluded in each pixel10included in the imaging device100according to the present embodiment. Specifically,FIG.5illustrates one example of positional relationships of the top electrode41a, the trench portions41eand41f, the vias v1and v2, the impurity regions2band2c,and the second capacitive element42, excluding the photoelectric converter15from the pixel10, when viewed in a normal direction of the major surface of the semiconductor substrate2.

In the example illustrated inFIG.5, the vias v1and v2are formed at approximately centers of the respective trench portions41eand41f. The outer shapes of the trench portions41eand41fare denoted by thick solid lines. The via v1is located immediately above the impurity region2bto which it is connected. The via v2is located immediately above the electrode42a.The arrangements and the shapes of the trench portions41eand41fare not particularly limited.

As illustrated inFIG.5, according to the present embodiment, the first capacitive element41in one pixel10has two or more trench portions41eand41f. As illustrated inFIG.3, the contact points41gand41hare provided at respective bottom surfaces of the trench portions41eand41f, Since the contact points41gand41hobtain electrical connections with the respective different electrical elements, the reset drain node46can be designed with a shortest path and in accordance with a circuit diagram. Also, the reset drain node46is formed in a layer at a lower side of the wiring layer51including the feedback line25provided through two or more pixels10and the wiring layer52including the vertical signal line18. Thus, the reset drain node46has a structure that is less vulnerable to influences of noise, thus making it possible to reduce influences of parasitic capacitance.

As illustrated inFIG.5, the first capacitive element41is provided so as to occupy a majority portion of the pixels10in plan view. The plan-view shape of the first capacitive element41is generally rectangle, and an opening AP is provided at a center thereof. The plan-view shape of the first capacitive element41is substantially the same as the plan-view shape of the top electrode41a. The opening AP is a through-hole for passage of the connection portion50. The position where the opening AP is provided is not particularly limited.

Also, in the present embodiment, as can be understood with reference toFIG.3, the first capacitive element41overlaps at least a part of the impurity region2ain plan view. Specifically, at least one of the top electrode41aor the bottom electrode41coverlaps the impurity region2a, For example, both the top electrode41aand the bottom electrode41ccover the entire impurity region2a.That is, in plan view, the entire impurity region2ais located inside the top electrode41aand the bottom electrode41a.

Each of the top electrode41aand the bottom electrode41chas a light-shielding property. Thus, light that is incident on the imaging device100and that travels in the interlayer insulating layer4without being photoelectrically converted by the photoelectric converter15is shielded by the top electrode41aor the bottom electrode41c. This makes it possible to suppress light that reaches the impurity region2a. When light is incident on the impurity region2a, charge is generated, which can cause noise. Suppression of light that reaches the impurity region2amakes it possible to reduce noise.

[3. Manufacturing Method]

Subsequently, a manufacturing method for the imaging device100according to the present embodiment, particularly, a process for manufacturing the first capacitive element41, will be described with reference toFIGS.6A to6I.FIGS.6A to6Iare sectional views for describing a plurality of processes included in a process for manufacturing the first capacitive element41. Although a description will be given below while paying attention to one trench portion41e,the same description also applies to the trench portion41f.

First, as illustrated inFIG.6A, the vias v1and v3are formed in the insulating layer4bdeposited at an upper side of the semiconductor substrate2(not illustrated). In this case, although not illustrated inFIG.6A, the via v2is formed at the same time. Specifically, first, a plasma chemical vapor deposition (CVD) method or the Ike is used to form a silicon oxide film as the insulating layer4b.Thereafter, the deposited insulating layer4bis patterned by photolithography and etching to thereby form contact holes h1and h3. Next, a vapor deposition method, a sputtering method, a CVD method, plating, or the Ike is used to fill the contact holes h1and h3with metal material, such as tungsten (W) or copper (Cu), to thereby form the vias v1and v3.

The via vi is, for example, an electrically conductive via connected to the bottom electrode41cof the first capacitive element41. In the example illustrated inFIG.6A, the via v3, in addition to the via v1, is formed at the same time. The via v3is a part of the via50dincluded in the connection portion50connected to the second electrode15cof the photoelectric converter15.

Next, as illustrated inFIG.6B, an insulating layer71and the insulating layer4care sequentially formed on an entire surface of the insulating layer4bby a plasma CVD method. The insulating layer71is, for example, a silicon carbon nitride film (SiCN film). The insulating layer4cis, for example, a silicon oxide film. The silicon carbon nitride film makes it possible to suppress diffusion of metal included in the vias v1and v3. InFIG.3, the insulating layer71is not illustrated. Also, the formation of the insulating layer71is not essential and may be omitted.

Next, as illustrated inFIG.6C, the trench4tthat penetrates the insulating layer71and the insulating layer4cis formed by dry etching. The trench4tis a through-hole for exposing the via v1. When the first capacitive element41includes two or more trench portions, the trenches are formed at the same time. For example, the trenches4tand4uare formed at the same time.

Next, as illustrated inFIG.6D, the bottom electrode41cis formed. Specifically, first, an electrically conductive thin film, such as a titanium nitride film, is deposited. The titanium nitride film is formed, for example, by an atomic layer deposition (ALD) method or a plasma CVD method. Next, after a resist mask is formed on the deposited electrically conductive thin film, for example, a part of the electrically conductive thin film is removed by dry etching using chlorine (Cl2) gas, and the resist mask is removed by oxygen ashing processing. As a result, the bottom electrode41cpatterned to have a predetermined shape is formed, as illustrated inFIG.6D.

Continuously performing the formation process of the trench4tand the deposition process of the electrically conductive thin film that constitutes the bottom electrode410makes it possible to reduce a contact resistance between the bottom electrode41cand the via v1. In the process of forming the trench4t, since a surface of the via v1needs to be exposed to plasma, the state of the surface at which the via v1is exposed is activated. In addition, forming the electrically conductive thin film facilitates that metal coupling is formed between the electrically conductive thin film and the via v1, thus making it possible to suppress the contact resistance.

Next, as illustrated inFIG.6E, the dielectric layer41bis formed. Specifically, first, a dielectric film is deposited on an entire surface of the insulating layer4cso as to cover the bottom electrode41c.The dielectric film is, for example, a hafnium oxide film. The hafnium oxide film is formed, for example, by an ALD method or a plasma CVD method. Next, after a resist mask is formed on the deposited dielectric film, for example, a part of the dielectric film is removed by dry etching using chlorine gas, and the resist mask is removed by oxygen ashing processing. As a result, as illustrated inFIG.6E, the dielectric layer41bpatterned to have a predetermined shape is formed. At this point in time, leaving the dielectric layer41blarger than the bottom electrode41callows the dielectric layer41bto entirely cover the bottom electrode41cso that an end portion of the bottom electrode41cis not exposed.

Next, as illustrated inFIG.6F, the top electrode41ais formed. Specifically, first, an electrically conductive thin film, such as a titanium nitride film, is deposited on an entire surface of the insulating layer4cso as to cover the dielectric layer41b. The titanium nitride film is formed, for example, by an ALD method or a plasma CVD method. Next, after a resist mask is formed on the deposited electrically conductive thin film, for example, a part of the electrically conductive thin film is removed by dry etching using chlorine gas. As a result, as illustrated inFIG.6F, the top electrode41apatterned to have a predetermined shape is formed. At this point in time, leaving the top electrode41alarger than the dielectric layer41ballows the top electrode41ato entirely cover the dielectric layer41bso that an end portion of the dielectric layer41bis not exposed.

After the bottom electrode41cis formed, the dielectric film and the electrically conductive thin film may be deposited continuously. After the dielectric film and the electrically conductive thin film are deposited continuously, the electrically conductive thin film, and the dielectric film may be sequentially patterned to thereby form the top electrode41aand the dielectric layer41bhaving predetermined shapes. In this case, an end portion of the top electrode41aand an end portion of the dielectric layer41bare generally flush with each other, so that the plan-view shape of the top electrode41aand the plan-view shape of the dielectric layer41bbecome generally the same.

Through the above-described processes, the first capacitive element41including the planar portion41dand the trench portion41eis formed.

Next, as illustrated inFIG.6G, the insulating layer4d is deposited on an entire surface so as to cover the top electrode41aof the first capacitive element41. The insulating layer4dis, for example, a silicon oxide film.

Next, as illustrated inFIG.6H, vias v4and v5, the wiring layer50b,and a wiring layer53are formed. The formation of the vias v4and v5is performed in the same manner as the vies v1and v3. That is, after contact holes are formed by photolithography and etching, the formed contact holes are filled with metal material to thereby form the vies v4and v5.

The via v4is a part of the via50dincluded in the connection portion50. Although not illustrated inFIG.3, the via v5and the wiring layer53are portions that provide electrical connection between the top electrode41aof the first capacitive element41and the sensitivity adjustment line32. InFIG.6H, although the via v5is provided so as to penetrate the top electrode41a, the via v5may be in contact with an upper surface of the top electrode41a.

In addition, the insulating layer4eis formed, and the via50e, a via v6, the wiring layer50c, and a wiring layer54are formed, as illustrated inFIG.6I, Specific formation methods are analogous to the formation method of the insulating layer4dand the formation method of the vias v4and v5and the wiring layers50band53.

Repeating the formation of the insulating layer, the vias, and the wiring layer makes it possible to form the interlayer insulating layer4having a desired number of laminated layers. This allows various signal lines including the sensitivity adjustment lines32to be drawn out of the pixel region.

[4. Modification]

Now, a modification of the first embodiment will be described with reference toFIG.7.

FIG.7is a schematic sectional view of each pixel11included in an imaging device according to this modification. As illustrated inFIG.7, an electrical contact point41iis provided at a side surface of the trench portion41fin the first capacitive element41. Specifically, the bottom electrode41cof the first capacitive element41has the electrical contact point41i.The electrical contact point41iis a coupling portion of the bottom electrode41cand a wiring layer55.

In this modification, the trench portion41fis provided so as to penetrate the insulating layer4cand an insulating layer4g.The insulating layer4gis located between the insulating layer4band the insulating layer4c. Since the trench portion41fis provided so as to penetrate the plurality of insulating layers4cand4g,the wiring layer55can be provided between the insulating layer4cand the insulating layer4g.Thus, the contact point41ican be formed at the side surface of the trench portion41f.

The number of insulating layers penetrated by the trench portion41fis not limited to two and may be three or more. This allows a plurality of electrical contact points to be provided at different heights at the side surface of the trench portion41f.

The wiring layer55is electrically connected to an upper end of the via v2. The wiring layer55is formed so as to be exposed at a side surface of the trench4uprovided in the insulating layers4cand4g.Thus, forming the bottom electrode41calong the side surface of the trench4uallows the wiring layer55and the bottom electrode41cto be electrically connected to each other. The first capacitive element41is connected to the electrode42aof the second capacitive element42through the electrical the contact point41iof the bottom electrode41c, the wiring layer55, and the via v2.

As described above, the electrical contact point of the bottom electrode410of the first capacitive element41does not necessarily have to be provided at a bottom portion of the trench portion41fand may be provided at the side surface of the trench portion41f. Also, an electrical contact point of the bottom electrode41cmay be provided at the planar portion41dof the first capacitive element41.

Second Embodiment

Subsequently, a second embodiment will be described.

Compared with the imaging device according to the first embodiment, an imaging device according to the second embodiment differs in the number of trench portions included in a first capacitive element. Hereinafter, points that differ from the first embodiment will be mainly described, and descriptions of common points will be omitted or briefly given.

FIG.8is a schematic sectional view of each pixel110included in the imaging device according to the present embodiment.FIG.9is a schematic plan view showing one example of the shapes and the arrangements of a first capacitive element141and trench portions included in each pixel110included in the imaging device according to the present embodiment.

Compared with the pixel10according to the first embodiment, the pixel110differs in that it includes the first capacitive element141instead of the first capacitive element41, as illustrated inFIG.8. The first capacitive element141includes three or more trench portions. Specifically, as illustrated inFIG.9, the first capacitive element141includes six trench portions41e,41f,141a,141b,141c, and141d.

As illustrated inFIG.8, the trench portions41eand41fare provided with electrical contact points41gand41h,as in the first embodiment. The trench portions141a,141b,141c, and141dare not provided with electrical contact points. A bottom surface and a side surface of the trench portion141aare respectively in contact with the insulating layers4band4cand are covered thereby. As illustrated inFIG.9, a vias that overlaps the trench portion141ain plan view is not provided. The same also applies to the trench portions141b,141c, and141d.

Thus, in the present embodiment, since the first capacitive element141includes a large number of trench portions, the capacitance value can be increased. A specification value of the capacitance value of the first capacitive element141, in many cases, varies depending on the type of image sensor. For example, when a bright scene is shot, the reset transistor36is put into an on state, and not only the charge accumulation node44but also the reset drain node46can be used as a charge accumulation portion. In this case, the larger the capacitance value of the first capacitive element141is, the less likely a gate potential of the signal detection transistor34increases, even when a large amount of charge is accumulated. Thus, a conversion gain can be switched, so that an image in which highlight clipping does not occur can be provided even for a bright scene.

The number of trench portions that are not provided with electrical contact points is not limited to four. The number of trench portions that are not provided with electrical contact points may be only one, may be two or three, or may be five or more. Also, the number of trench portions that are provided with electrical contact points is not limited to two, may be only one, or may be three or more.

In the present embodiment, as illustrated inFIGS.8and9, the wiring layers51and52are provided at an upper side of the first capacitive element141. As described above, in one example, the wiring layers51and52include the vertical signal line18, the feedback line25, and so on.

In this case, parasitic capacitances occur between the top electrode41a of the first capacitive element141and the wiring layers51and52. In particular, the potentials of the vertical signal line18and the feedback line25vary with time in accordance with the corresponding pixel10. Thus, parasitic capacitance components are detected as noise components in the vertical signal line18and the feedback line25.

A parasitic capacitance value is proportional to a dielectric constant of an insulating film between the wiring layers51and52and the top electrode41aand to a difference voltage that occurs therebetween. In contrast, in order to reduce the parasitic capacitance value, the top electrode41aof the first capacitive element141and the wiring layers51and52may be arranged so as not to overlap each other, as illustrated inFIG.10. This makes it possible to suppress noise components based on the parasitic capacitance.FIG.10is a schematic plan view showing one example of the shapes and the arrangements of the first capacitive element141and trench portions included in each pixel111included in an imaging device according to a modification of the second embodiment.

In this modification, as can be understood from comparison betweenFIGS.8and10, the area that the first capacitive element141occupies in the pixel in plan view is reduced. Thus, the capacitance value of the planar portion41dof the first capacitive element141decreases.

Meanwhile, in order for the first capacitive element141to achieve a desired capacitance value, the first capacitive element141needs to ensure a certain electrode area in plan view. Ensuring the electrode area and suppressing overlap with the wiring layers are in a trade-off relationship. That is, when the electrode area is increased, it is difficult to avoid overlap with the wiring layers.

In contrast, in the first capacitive element141according to this modification, providing the plurality of trench portions41e,41f,141a,141b,141c, and141dwhile avoiding overlap with the wiring layers in plan view makes it possible to obtain an electrode area by utilizing the sidewalls of the trench portions. This makes it possible to increase the capacitance value of the first capacitive element141while suppressing noise components caused by parasitic capacitance.

Third Embodiment

Subsequently, a third embodiment will be described.

In an imaging device according to the third embodiment, the circuit configuration thereof differs from the imaging devices according to the first and second embodiments. Hereinafter, points that differ from the first and second embodiments will be mainly described, and descriptions of common points will be omitted or briefly given.

FIG.11is a diagram showing one example of a circuit configuration of each pixel210included in the imaging device according to the present embodiment. As illustrated inFIG.11, compared with the pixel10according to the first embodiment, the pixel210differs in that it does not include the second capacitive element42and the feedback transistor38. In the pixel210, the reset drain node46is not provided. Also, in the pixel210, the reset transistor36is provided between one of a pair of electrodes of the first capacitive element41and the feedback line25. That is, the reset transistor36is provided at the same position as the feedback transistor38according to the first embodiment.

As illustrated inFIG.11, the charge accumulation node44is connected to one of the pair of electrodes of the first capacitive element41. Thus, the first capacitive element41functions as a charge accumulation portion. That is, signal charge generated in the photoelectric converter15is also accumulated in the first capacitive element41. This makes it possible to increase the amount of signal charge accumulated in the pixel210, thus making it possible to suppress occurrence of highlight clipping even in a bright scene.

FIG.12is a schematic sectional view of the pixel210included in the imaging device according to the present embodiment. As illustrated inFIG.12, the reset transistor36, instead of the feedback transistor38illustrated inFIG.3, is provided at the same position as the feedback transistor38. That is, the impurity region2bis one of a source region and a drain region of the reset transistor36. The impurity region2cis the other of the source region and the drain region of the reset transistor36.

Also, as illustrated inFIG.12, the pixel210includes a connection portion250instead of the connection portion50. The connection portion250does not include the plug P1and the wiring portion50aillustrated inFIG.3. The connection portion250provides electrical connection between the second electrode15cof the photoelectric converter15and the gate electrode34eof the signal detection transistor34.

The gate electrode34eis connected to the via v2through a plug P4and a wiring portion250a.The via v2is connected to the bottom electrode41cof the first capacitive element41, as in the first embodiment. With this configuration, as illustrated inFIG.12, the second electrode15cof the photoelectric converter15is connected to the impurity region2bthrough the connection portion250, the gate electrode34e, the plug P4, the wiring portion250a,the via v2, the bottom electrode41cof the first capacitive element41, the via v1, and the plug P3. That is, the second electrode15c, the connection portion250, the gate electrode34e, the plug P4, the wiring portion250a, the via v2, the bottom electrode41cof the first capacitive element41, the via v1, the plug P3, and the impurity region2bserve as the charge accumulation node44.

As described above, in the present embodiment, since the capacity of the charge accumulation portion in which the signal charge generated by the photoelectric converter15is accumulated can be increased, it is possible to suppress occurrence of highlight clipping even in a bright scene.

Fourth Embodiment

Subsequently, a fourth embodiment will be described,

Compared with the imaging device according to each of the first to third embodiments, an imaging device according to the fourth embodiment differs in that an electrical contact point is provided at the top electrode. Hereinafter, points that differ from the first to third embodiments will be mainly described, and descriptions of common points will be omitted or briefly given.

FIG.13is a schematic sectional view of each pixel310included in the imaging device according to the present embodiment. As illustrated inFIG.13, compared with the pixel10according to the first embodiment, the pixel310includes a connection portion350instead of the connection portion50,

The connection portion350includes a plug P5, a wiring portion350a, an electrode342a, vias v7,350d,50e, and50f, and the wiring layers50band50c. The connection portion350provides electrical connection between the second electrode15cof the photoelectric converter15and the gate electrode34eof the signal detection transistor34. Also, the gate electrode34eis electrically connected to the impurity region2a, the connection of which is not illustrated inFIG.13.

Also, as illustrated inFIG.13, the pixel310includes a first capacitive element341and a second capacitive element342, instead of the first capacitive element41and the second capacitive element42, compared with the pixel10according to the first embodiment, The first capacitive element341has a top electrode341a, the dielectric layer41b, and the bottom electrode41c.

The top electrode341aof the first capacitive element341has an electrode portion342b. The electrode portion342bis a portion provided so as to extend from the top electrode341aonto the upper surface of the insulating layer4c. Specifically, in plan view, the electrode portion342boverlaps a part of the electrode342aincluded in the connection portion350. Thus, the electrode portion342band the part of the electrode342aform the second capacitive element342.

Also, the top electrode341aof the first capacitive element341has contact points341gand341h.The contact points341gand341hare provided at portions that are included in the top electrode341aand that extend onto the insulating layer4c.

The contact point341gis provided at a bottom surface of the top electrode341a.The contact point341gis connected to a via v8and is connected to the impurity region2bthrough the via v8and the plug P3. That is, the contact point341gis connected to the reset transistor36and the feedback transistor38. In the present embodiment, each of the reset transistor36and the feedback transistor38is one example of an electrical element to which the contact point341gis electrically connected, as in the first embodiment.

The contact point341his a connection portion of the top electrode341aand the electrode portion342b. That is, the contact point341his connected to the second capacitive element342. In the present embodiment, the second capacitive element342is one example of an electrical element to which the contact point341his electrically connected.

In the example illustrated inFIG.13, the bottom electrode41cis also provided with the contact point41g.The contact point41gis connected to the via v1. Although not illustrated inFIG.13, the contact point41gis connected to the sensitivity adjustment line32through the via v1.

As described above, in the imaging device according to the present embodiment, two contact points341gand341hare provided at the top electrode341aof the first capacitive element341. Also, the contact points341gand341hare provided at portions other than the trench portion41ein the first capacitive element341. Also, the contact points341gand341hmay be provided at an upper surface of the top electrode341a.That is, the via provided on the first capacitive element341and the top electrode341amay be electrically connected to each other.

Also, at least one contact point may be provided at the top electrode341aof the trench portion41e.For example, although, inFIG.13, the top electrode341ais provided so as to fill the trench4t,the top electrode341amay also be configured with a uniform film thickness in the trench4tand may have a shape that is curved along a bottom surface and a side surface of the trench4t, similarly to the dielectric layer41band the bottom electrode41c. In this case, a contact point may be provided at an inner bottom surface of the top electrode341ain the trench portion41e. Alternatively, the contact point may be provided at an inner side surface of the top electrode341ain the trench portion41e.

Fifth Embodiment

Subsequently, a fifth embodiment will be described.

Compared with the imaging device according to each of the first to fourth embodiments, an imaging device according to the fifth embodiment differs in that the photoelectric converter is provided in the semiconductor substrate. Hereinafter, points that differ from the first to fourth embodiments will be mainly described, and descriptions of common points will be omitted or briefly given.

FIG.14is a schematic sectional view of each pixel410included in the imaging device according to the present embodiment.

As illustrated inFIG.14, the pixel410includes a photodiode PD instead of the photoelectric converter15. The photodiode PD is one example of a photoelectric converter and is, for example, a photodiode having a P-N junction. The photodiode PD is formed by an impurity region or the like formed in the semiconductor substrate2.

The imaging device according to the present embodiment is a backside-illuminated CMOS image sensor. The “backside” refers to one of two major surfaces of the semiconductor substrate2and is a surface opposite to the major surface at which the interlayer insulating layer4is provided. In the imaging device according to the present embodiment, light is incident from the backside of the semiconductor substrate2, that is, from an upper side in the plane ofFIG.14.

Also, the imaging device according to the present embodiment has a chip-stack structure. Specifically, the imaging device includes a first chip410aand a second chip410b.The first chip410aand the second chip410bare arranged one on another, that is, are stacked, in vertical directions.

As illustrated inFIG.14, the first chip410aincludes the semiconductor substrate2and the interlayer insulating layer4. The second chip410bincludes a semiconductor substrate402and an interlayer insulating layer404. After the first chip410aand the second chip410bare respectively manufactured, they are arranged one on another to thereby form the imaging device including the pixels410. Specifically, the interlayer insulating layer4formed on a major surface of the semiconductor substrate2and the interlayer insulating layer404formed on the major surface of the semiconductor substrate402are bonded to each other. InFIG.14, the bonding plane is schematically denoted by a dashed-and-dotted line. In the present embodiment, the interlayer insulating layer4includes five insulating layers4a,4b,4c,4d, and4e.The interlayer insulating layer404includes two insulating layers404aand404b. The numbers of layers in the interlayer insulating layer4and the interlayer insulating layer404are not limited to those numbers.

In the example illustrated inFIG.14, the first chip410ais provided with the reset transistor36, the feedback transistor38, and the first capacitive element141. The second chip410bis provided with the signal detection transistor34and the address transistor40. The second capacitive element42may be provided in the interlayer insulating layer4or may be provided in the interlayer insulating layer404. The elements included in the signal detection circuit SC in the pixel410may be provided in any of the first chip410aand the second chip410b.

As illustrated inFIG.14, the insulating layer4e, which is the uppermost layer (the layer at a lower side in the plane of the figure) in the interlayer insulating layer4, is provided with an electrically conductive terminal portion60. Similarly, the insulating layer404b, which is the uppermost layer in the interlayer insulating layer404, is provided with an electrically conductive terminal portion460. Since the terminal portion60and the terminal portion460are connected in contact with each other, the elements provided at the semiconductor substrate2and the elements provided at the semiconductor substrate402can be electrically connected to each other.

In the present embodiment, the contact point41gis provided at the bottom surface of the trench portion41ein the first capacitive element141. The contact point41gis connected to the reset transistor36through the via v1.

Also, the contact point41his provided at the bottom surface of the trench portion41fin the first capacitive element141. Although not illustrated inFIG.14, the contact point41his electrically connected to the second capacitive element42. The second capacitive element42is provided, for example, in the first chip410a.As described above, two or more electrical elements to which two or more electrical contact points of the first capacitive element141are connected are provided in the first chip410ain which the first capacitive element141is provided.

The two or more electrical elements to which the two or more electrical contact points of the first capacitive element141are connected do not necessarily have to be provided in the first chip410a.At least one electrical element or all electrical elements may be connected to the second chip410b.

FIG.15is a schematic sectional view of each pixel411included in the imaging device according to this modification. In the pixel411illustrated inFIG.15, the reset transistor36and the first capacitive element341are provided in the first chip410a.The feedback transistor38is provided in the second chip410b. The signal detection transistor34, the address transistor40, and the second capacitive element42may be provided in the first chip410aor may be provided in the second chip410b.

As illustrated inFIG.15, the pixel411includes the first capacitive element341. The top electrode341aof the first capacitive element341includes the contact points341gand341i.The contact point341gis electrically connected to the reset transistor36. That is, the reset transistor36is one example of an electrical element. The contact point341iis electrically connected to the feedback transistor38. That is, the feedback transistor38is one example of an electrical element.

Two or more electrical elements to which two or more contact points of the first capacitive element341are connected may be respectively provided in the first chip410aand the second chip410b. That is, the first chip410aand the second chip410bmay be stacked to thereby cause the contact points and the electrical elements to be electrically connected to each other.

Other Embodiments

Although the imaging devices according to one or more aspects have been described based on the embodiments, the present disclosure is not limited to those embodiments. Modes obtained by making various modifications conceived by those skilled in the art to the embodiments and modes constructed by combining the constituent elements in different embodiments are also encompassed by the scope of the present disclosure, as long as such modes do not depart from the spirit of the present disclosure.

FIG.16is a schematic sectional view of each pixel12included in an imaging device according to another modification of the first embodiment. As illustrated inFIG.16, in the pixel12, the top electrode41aof the first capacitive element41is electrically connected to the sensitivity adjustment line32through a via. The sensitivity adjustment line32extends from inside of the pixel region to outside of the pixel region. In a region outside the pixel region, the sensitivity adjustment line32is electrically connected to a pad70through a via. Accordingly, the top electrode41ais electrically connected to the pad70through the sensitivity adjustment line32.

For example, in the embodiments described above, the numbers of insulating layers and wiring layers included in the interlayer insulating layer in the imaging device are not particularly limited. Also, the position of the capacitive element in the interlayer insulating layer is not particularly limited.

For example, the number of trench portions included in the first capacitive element may be only one. No electrical contact point may be provided in any of the trench portion included in the first capacitive element. In this case, two or more electrical contact points may be provided at the top electrode at the planar portion of the first capacitive element or may be provided at the bottom electrode at the planar portion. The electrical contact points may be provided at any of the upper surface and the lower surface of the top electrode or the bottom electrode.

For example, the dielectric layer41bmay be an insulating film, such as a silicon oxide film or a silicon nitride film, not a thin film using a high-k material.

For example, each transistor included in the signal detection circuit SC in the imaging device may be a P-channel MOSFET. Also, each transistor may be a bipolar transistor, not an FET.

Also, various changes, replacements, additions, omissions, and so on within the scope recited in the claims and a scope equivalent thereto can be made to each embodiment described above,

The imaging device according to one aspect of the present disclosure is useful for, for example, image sensors and digital cameras. For example, the imaging device according to one aspect of the present disclosure can be used for medical cameras, cameras for robots, security cameras, camera mounted on vehicles, and so on.