Patent ID: 12206368

DETAILED DESCRIPTION

Hereinafter, detailed contents for embodying the present invention will be described in detail with reference to the accompanying drawings.

FIG.1is a diagram illustrating a high-gain amplifier based on double-gain boosting according to an embodiment of the present invention.

Referring toFIG.1, a high-gain amplification unit100based on double-gain boosting includes a first gain amplification unit110and a second gain amplification unit120.

The first gain amplification unit110includes a first amplifier111, a second amplifier112, and an interstage matching network113.

Each of the first and second amplifiers111and112includes a first transmission line Z1, a transistor M1, a second transmission line Z2, and a third transmission line Z3.

The first transmission line Z1is connected to an input terminal, and may have a first reactance value capable of obtaining a maximum achievable gain at a set first frequency and a second reactance value capable of obtaining a maximum achievable gain at a second frequency.

The transistor120may be connected to a rear end of the first transmission line Z1.

The second transmission line Z2is connected to a rear end and an output terminal of the transistor, and may have a third reactance value capable of obtaining a maximum achievable gain at a set first frequency and a fourth reactance value capable of obtaining a maximum achievable gain at a second frequency.

The third transmission line Z3may be connected between the input terminal and the output terminal.

The third transmission line Z3may be connected in parallel with the first transmission line Z1, the transistor120, and the second transmission line Z2.

The third transmission line140is connected to an input terminal, and may have a fifth reactance value capable of obtaining a maximum achievable gain at set first frequency and a sixth reactance value capable of obtaining a maximum achievable gain at a second frequency.

The interstage matching network113may be connected between the first amplifier111and the second amplifier112, and match both amplifiers.

The second gain amplification unit120is connected in parallel with the first gain amplification unit110and may perform secondary amplification.

The second gain amplification unit120may include a fourth transmission line Z4connected between a front end of the first amplifier111and an input terminal, a fifth transmission line Z5connected between a rear end of the second amplifier112and an output terminal, and a sixth transmission line Z6connected between a front end Z4of the fourth transmission line Z4and a rear end Z5of the fifth transmission line.

In addition, the high-gain amplifier100based on double-gain boosting may further include a second matching unit (not illustrated) connected to the rear end of the second amplifier112, and a third amplifier (not illustrated) connected between the rear end of the second matching unit (not illustrated) and the second gain amplification unit. In this way, in the high-gain amplifier100based on double-gain boosting, N amplifiers and matching units may be arranged in cascade, and N may be variously selected according to circumstance.

FIG.2is a schematic of n-stage cascaded Gmax cores with matching networks.

Referring toFIG.2,FIG.2shows the schematic of n-stage cascaded Gmax cores with matching networks, where all the transistors are identical and embedded into a linear, lossless, reciprocal (LLR) networks to achieve Gmax at the target frequency, that is, the transfer parameter ratio (As) of each Gmax core is given by [18], [21], [31]

As=Y21⁢sY12s=-Gmax_tr,(1)θ2=phase(Az)=π(2)ks=1.(3)

InFIG.2, Ys, Ycas_n, ks, kcas_n,θs, andθcas n represent Y-parameter, Rollet stability factor, and the phase of A for the Gmax core and the n-stage cascaded Gmax cores, respectively, and Gmax_tr represents the Gmax value of a transistor. Assuming that all passive components for the embedding and interstage matching networks are linear, lossless and reciprocal, Acas_n,θcas_n, and kcas_n of the n-stage Gmax cores are given by

Aces⁢_⁢n=Y21⁢cas⁢_⁢nY12⁢cas⁢_⁢n=(Y21⁢sY12⁢s)n=(-Gmax_tr)n=(-1)n×Gmax_trn(4)θcas⁢_⁢n=θs×n=π×n(5)kcas⁢_⁢n=1.(6)

respectively. By substituting Acas_n, kcas_n, andθcas_n into Gma and U equation [21], the maximum available gain

(Gma_cas_n) and unilateral gain (Ucas_n) of the n-stage cascaded Gmax cores can be given by

Gma⁢_⁢cas⁢_⁢n=❘"\[LeftBracketingBar]"Y21⁢sY12⁢s❘"\[RightBracketingBar]"n⁢(ks-kz2-1)n=❘"\[LeftBracketingBar]"-Gmax_tr❘"\[RightBracketingBar]"n=Gmax_trn,(7)Ucas⁢_⁢n=❘"\[LeftBracketingBar]"Acas⁢_⁢n-1❘"\[RightBracketingBar]"22⁢kcas⁢_⁢n⁢❘"\[LeftBracketingBar]"Acas⁢_⁢n❘"\[RightBracketingBar]"-2⁢Re⁡(Acas⁢_⁢n)=Acas⁢_⁢n2-2⁢Acasn+12⁢kcas⁢_⁢n⁢❘"\[LeftBracketingBar]"Acas⁢_⁢n❘"\[RightBracketingBar]"-2⁢❘"\[LeftBracketingBar]"Acas⁢_⁢n❘"\[RightBracketingBar]"⁢cos⁢(θcas⁢_⁢n)(8)

which leads to the maximum achievable gain (Gmax_cas_n) of the n-stage cascaded Gmax cores given by
Gmax_cas_n=(2Ucasn−1)+2√{square root over (Ucas_n(Ucas_n−1))}.  (9)

Note that, as can be seen in (7), the overall gain of n-stage cascaded Gmax cores, Gma_cas_n, is limited to Gmax trn. To achieve Ucas_n and Gmax_cas_n, additional embedding networks have to be applied to the n-stage cascaded Gmax cores. As follows, the characteristics of Ucas_n and Gmax_cas_n show uniquely different behavior depends on whether the numbers of stages are odd or even.

In the case of odd number of cascaded Gmax cores, Ucas_n is given by

Ucas⁢_⁢n=❘"\[LeftBracketingBar]"-Gmax_trn-1❘"\[RightBracketingBar]"22⁢kcas⁢_⁢n⁢❘"\[LeftBracketingBar]"-Gmax_trn❘"\[RightBracketingBar]"-2⁢Re⁡(-Gmax_trn)=Gmax_tr2⁢n+2⁢Gmax_trn+14⁢Gmax_trn.(10)

By substituting (10) into (9), Gmax_cas_n is given by
Gmax_cas_n=Gmax_trn.  (11)

From (11), maximum achievable gain which is applied to an odd number of cascaded Gmax cores (Gmax_cas_n) is the same as the maximum available gain of the cascaded Gmax cores (Gmax_trn) as in (7). This means that the gain higher than Gmax trn cannot be achieved even with additional embedding network for Gmax, that is, double-Gmax.

However, in the case of even number of cascaded Gmax cores, Ucas_n is given by

Ucas⁢_⁢n=❘"\[LeftBracketingBar]"Gmax_trn-1❘"\[RightBracketingBar]"22⁢kcas⁢_⁢n⁢❘"\[LeftBracketingBar]"Gmax_trn❘"\[RightBracketingBar]"-2⁢Re⁡(Gmax_trn)=Gmax_tr2⁢n-2⁢Gmax_trn+12×1×Gmax_trn-2⁢Gmax_trn=∞.(12)which leads to
Gmax_cas_n=∞.  (13)

As can be seen in (12) and (13), in principle, the unilateral (Ucas_n) and maximum achievable (Gmax_cas_n) gains,

implemented with an even number of cascaded Gmax cores can approach infinity. Note that, (12) and (13) are valid at fo<fmax since the Gmax of the single transistor is defined at fo<fmax.

Even though both Ucas_n and Gmax_cas_n in (12) and (13) can approach infinity at the target frequencies, Gmax_cas_n is

more realistic to be adopted for the amplifier design since achieving zero reverse gain for Ucas_n at high operating frequencies is not practical mainly due to the substrate coupling. The implementation of Gmax_cas_n is much easier and straightforward. It is to be noted, however, that (12) and (13) represents, by definition, the boundary condition for oscillation. However, the oscillation can be easily avoided by adjustingθcas_n while satisfying the unconditional stability. Therefore, by adopting the double-Gmax core, the amplifier can achieve much higher gain per stage than Gmax_tr with unconditional stability.

FIG.3a,FIG.3b,FIG.3candFIG.3dare design procedure of two-stage double-Gmax core. Transistor, single-transistor Gmax core, cascade of two single-transistor Gmax cores, and double-Gmax core.

Referring toFIG.3a,FIG.3b,FIG.3candFIG.3d, any even number of cascaded Gmax cores can satisfy (12) and (13), but a cascade of two single-transistor Gmax cores is chosen for the implementation of high gain amplifier as it requires minimum chip area and dc power consumption.

A step-by-step procedure which leads to double-Gmax core where all the passive components are assumed linear, lossless and reciprocal. InFIG.3a, the characteristic of the transistor is represented by Atr, ktr, θtr, Gma_tr/Gms_trand Gmax_tr. The transistor are satisfied the condition Gma_tr/Gms_tr<Gmax_trGmaxis equal to Gmax_tr
Atr
ktr,θtr
Gma_tr/Gms_tr<Gmax_tr
Gmax=Gmax_tr

The single-transistor Gmax core can be realized by embedding the transistor into an LLR network, as shown inFIG.3b, that satisfies the condition As=−Gmax_tr, ks=1, θs=π, such that Gma_s=Gmax_tr. Due to the linear, lossless, and reciprocal nature of the embedding network, the Mason's Invariant Us of the single-transistor Gmaxcore is the same as that of the transistor, Utr. Hence, the Gmaxof the single-transistor Gmaxcore is the same as Gmax_trsince Gmax_tris only a function of Utras in (9).
As=−Gmax_tr
ks=1, θs=π
Gma_s=Gmax_tr
Gmax=Gmax_s=Gmax_tr

For a cascade of two single-transistor Gmax cores with interstage matching network, shown inFIG.3c, A_cas_2is equal to Gmax_tr2, Gma_cas_2is equal to Gmax_tr2, kcas_2=1, θcas_2=2 π and Gmax, i.e., Gmax_cas_2approaches 1 following (12) and (13), Gmaxis equal to Gmax_cas_2, Gmaxapproaches infinity.
Acas_2=Gmax_tr2
kcas_2=1, θcas_2=2π
Gma_cas_2=Gmax_tr2
Gmax=Gmax_cas_2=∞

FIG.3dshows the schematic of the double-Gmaxcore where an additional LLR is adopted onto the cascade of two single-transistor Gmaxcores and satisfies the condition of Ad=−Gmax_cas_2, kd=1, θd=π, i.e., the values of kdand θdof double-Gmaxcore are 1 and, respectively, such that the gain (Gma_d) approaches infinity.
Ad=−Gmax_cas_2
kd=1, θd=π
Gma_d=Gmax_cas_2=∞

FIG.4is final general structure of the proposed two-stage double-Gmax core.

Referring toFIG.4, the final general structure of the proposed two-stage double-Gmaxcore. The reactive components Z1, Z2and Z3are for the single-transistor Gmaxcore, and Z4, Z5and Z6are for the implementation of Gmaxonto the cascade of two single-transistor Gmaxcores.

The gain of double-Gmaxcore can be controlled by varying the values of ksand θs. This section describes the behaviors of double-Gmaxcore as a function of ksand θs.

For the cascade of two single-transistor Gmaxcores shown inFIG.3c, the kcas 2and θcas 2can be given by
kcas_2=2k22−1,  (14)
and
θcas_2=2θ2(15)which become equal to 1 and 2π, respectively, when ks=1 and θs=π. The derivation details of (14) is shown in Appendix A. Then, from (4) and the expression for Gmain [21], Acas_2can be given by

Aces⁢_⁢n=Y21⁢cas⁢_⁢nY12⁢cas⁢_⁢n=(Y21⁢sY12⁢s)n=(Gmax_trks-ks2-1)2.(16)

Substituting (14), (15) and (16) into the expression for the unilateral gain [21], the unilateral gain for the cascade of two single-transistor Gmaxcores can be given by

Ucas⁢_⁢z=❘"\[LeftBracketingBar]"Acas⁢_⁢2-1❘"\[RightBracketingBar]"22⁢kcas⁢_⁢2⁢❘"\[LeftBracketingBar]"Acas⁢_⁢2❘"\[RightBracketingBar]"-2⁢Re⁡(Acas⁢_⁢2)=(Gma⁢sks-ks2-1)4-2⁢(Gmasks-ks2-1)2+1(4⁢kz2-2)(Gmaskz-kz2-1)2-2⁢(Gmasks-ks2-1)2⁢cos⁡(2⁢θs)(17)and the maximum achievable gain of the cascade of two single transistor Gmaxcores is given by
Gmax_cas_2=(2Ucas_2−1)+2√{square root over (Ucas_2(Ucas_2−1))}.  (18)

FIG.5is behavior of Gmax cas 2 as a function of ks and _s, from (17) and (18), in comparison with Gmax_tr2.

Referring toFIG.5, the behavior of Gmax_cas_2as a function of ksand θs, from (17) and (18), in comparison with Gmax_tr2. Only ks>1 region is shown considering unconditional stability. The plane parallel to ksand θs-axis (in pink) represents the theoretical maximum available gain (Gmax_tr2) that can be obtained from a cascade of two single-transistor Gmaxcores. As can be seen inFIG.5,1) Gmax_cas_2approaches infinity when ks=1 and θs=π,2) Gmax_cas_2can have much higher values of gain than Gmax_tr2as ksand θsapproach 1 and π, respectively.3) Contrary to the common perception, it is possible to obtain a gain higher than Gmax_trper transistor stage while satisfying the unconditional stability.

Based on the analysis described in Section III, this section presents a practical implementation example of a 250 GHz two-stage double-Gmaxcore. An n-MOSFET having a channel length of 60 nm and a total width of 12 um with 20 fingers, same as the one in [21], is adopted for the design, which is biased at VGS=VDS=1 V with IDS=10.75 mA. The simulated fmaxof the given transistor with optimized layout is 395 GHz, where the interconnect metals and contacts up to the top signal metal line are included in the transistor layout, and Gmax_trat 250 GHz is 9.95 dB.

FIG.6aandFIG.6bis design of a single-transistor Gmax core with three passive elements.

Referring toFIG.6aandFIG.6b, to design a cascade of two single-transistor Gmaxcores, a single-transistor Gmaxcore should be designed in advance, which is shown inFIG.6aandFIG.6b, where a three passive elements based embedding network is chosen as it allows infinite combinations of embedding network for gain-boosting [18], [21], [22]. InFIG.5(a), Yinand Youtrepresent input and output admittances of the Gmaxcore, respectively. The single-transistor Gmaxcore is designed in terms of minimizing the chip area and passive component loss as in [18] except that the θsvalue has been shifted to 195° which makes the gain (Gmax_cas_2) to be less susceptible to the PVT variations by reducing the gain, considering the sharp increase in Gmax_cas_2at the values of ksand θs's near 1 and π as shown inFIG.5. The target power gain of the double-Gmaxcore is set to be around 10 dB higher than that of the cascade of two single-transistor Gmaxcores. The ksof implemented single-transistor Gmaxcore will increase slightly higher than 1 due to the passive component losses even though the design point of ksis set to 1. Under this condition, Gmax_cas_2shows around 10 dB higher gain than that of the cascade of two single-transistor Gmaxcores (Gmax_tr2) when θs=195°. Therefore, ks=1 and θs=195° are chosen as a design point considering both target power gain and abrupt PVT variation.FIG.5(b)shows the values of X3, X1, Real (Yin) and Real (Yout) as a function of X2that satisfies ks=1 and θs=195° conditions at 250 GHz. As shown inFIG.6b, the input (Real (Yin)) and output (Real (Yout)) conductances of the single-transistor Gmaxcore vary over the X1, X2and X3combinations. Utilizing this property, the loss and chip area of the interstage matching network can be minimized [18] as follows.

FIG.7aandFIG.7bis design of single-transistor Gmax core considering the size of series connected transmission line TLISML for the interstage matching.

Referring toFIG.7aandFIG.7b,FIG.6shows the details of how the values of LLR embedding network for the single-transistor Gmaxcore are determined considering the size of series connected transmission line TLISMLfor the interstage matching. As shown inFIG.7a, transmission lines (TLs) with characteristic impedance (Zo) of 50 are used for Z1, Z2and Z3and the wavelength (λ) of the TLs at 250 GHz is assumed 653 um.FIG.7bshows the physical length of the TL1, TL3and TLISMLas a function of the length of TL2that satisfies the Gmaxcondition. Generally, a shorter interstage series matching element is advantageous in terms of the insertion loss [32]. Even though the interstage matching for the real part between the two Gmaxcores can be achieved by adjusting the value of embedding network without TLISML, the adoption of TLISML, 30 um as a minimum, not only minimizes the insertion loss of interstage matching network but also helps prevent the unwanted coupling between the two Gmaxcores as explained in [18], [33].

FIG.8is simulated Gma_s, ks andθs of the single-transistor Gmax core as a function of frequency.

Referring toFIG.8, The final values of TL1, TL2, and TL3for the single-transistor Gmaxcore are 24, 18, and 117 um, respectively, which leads to TLISML=30 um.FIG.8shows the simulated Gma_s, ksand θsof the single-transistor Gmaxcore as a function of frequency, where their values at 250 GHz are 9.5 dB, 1.02 and 195°, respectively. Due to the loss of embedding network and the offset in θs(1950), Gma_sis slightly reduced from the theoretical value of Gmax_tr(9.95 dB).

FIG.9a,FIG.9bandFIG.9cis cascade of two single-transistor Gmax cores.

Referring toFIG.9a,FIG.9bandFIG.9c, The cascade of two single-transistor Gmax cores can be implemented with two single-transistor Gmax cores and the interstage matching network.FIG.9a,FIG.9bandFIG.9cshows the schematic of the cascade of two single-transistor Gmax cores and its simulated kcas_2 and θcas_2, as well as the comparison of Gma_cas_2, Ucas_2 and Gmax_cas_2. InFIG.9a, the two single-transistor Gmax cores are matched by the 30 um TLISML1 in combination with a shunted TLISML2. As shown inFIG.9b, the values of kcas_2 and θcas_2 are 1.02 and 30° (=195°+195°), respectively. Note that, the interstage matching network does not affect the kcas2since it introduces the same amount of phase shifts in both forward and reverse directions, which compensate each other. The insertion losses of the embedding and interstage matching components lead to kcas_2 slightly higher than 1, which leads to Gma_cas_2, Ucas_2 and Gmax_cas_2 of 17.2, 22.2 and 28.3 dB, respectively, as shown inFIG.9c.

FIG.10aandFIG.10bshows the design of double-Gmaxcore which is implemented with three passive elements as in single-transistor Gmaxcore.FIG.10aandFIG.10bshows the required reactance values of X6and X4as a function of X5at 250 GHz, to meet kd=1 and θd=180° of Gmax. As shown inFIG.10aandFIG.10b, the lowest required reactance value of X6is chosen for the design considering the limited implementable value caused by minimum metal width and the resulting insertion loss of the TL6. For the design simplicity, Zoof 50Ω is adopted for the TLs implementing Z4, Z5and Z6.

FIG.11is reactance of TL6as a function of physical length in degree.

Referring toFIG.11, shows the reactance of TL6as a function of physical length in degree. As shown inFIG.11, the reactance value of TL shows the periodic characteristic since the equivalent TL reactance value is Zosin(β1), where β and l represent propagation constant and physical length of TL, respectively. The TL length of 84°, 96°, 444° and 456° meet the required reactance value of j49.7Ω in a one and half period. A long TL length of 444° is adopted for TL6, even though short line has advantage in terms of loss, to avoid the coupling between the outer and inner passive elements of the Gmaxcores as well as the convenience of the measurement. A proper amount of spacing is required between the input and output pads of an amplifier for the on-wafer probing, therefore, mandates longer TL length than the minimum required size. The final sizes of TL4, TL5, and TL6are 35, 92, and 805 um, respectively. If the double-Gmaxcore is implemented as a component of a bigger circuit, more compact layout would be feasible.

FIG.12a,FIG.12bandFIG.12cis Proposed 250 GHz two-stage double-Gmax core.

Referring toFIG.12a,FIG.12bandFIG.12c, shows the final details of the proposed double-Gmaxcore and its simulated maximum available gain in comparison with those of the cascade of two single-transistor Gmaxcores (Gma_cas_2) and the theoretical Gmax_tr2, and k-factor and |Δ|=1 S11S22-S12S21| as a function of frequency. InFIG.12b, the values of gain for double-Gmaxcore (Gma_d), Gma_cas_2and Gmax_tr2are 26.5, 16.5 and 20 dB, respectively, at 250 GHz. Note that, Gma_cas_2inFIG.12bis lower than the ideal Gmax_tr2by 3.5 dB due to the losses of the embedding and matching networks. InFIG.12b, Gma_dshows a higher gain than Gma_cas_2and Gmax_tr2by 10 and 6.5 dB, respectively. As shown inFIG.12c, the double-Gmaxcore shows unconditional stability (kd>1 and |Δ|<1). The embedding network loss increases the kdslightly higher than 1, which makes simultaneous conjugate input and output matching networks design possible. The simulated value of kdis 1.02 at 250 GHz. Due to the losses from TL4, TL5, and TL6, and overall kdof 1.02, the maximum available gain of double-Gmaxcore (26.5 dB) is lower than Gmax_cas_2(28.3 dB) inFIG.9cby 1.8 dB.

FIG.13shows the circuit schematics of the 250 GHz amplifier that adopts the double-Gmax core by adding the input and output matching networks.

Referring toFIG.13, To demonstrate the feasibility of the proposed double-Gmax gain boosting technique, two-stage 250 GHz amplifiers are designed in a 65 nm CMOS process.FIG.13the circuit schematics of the 250 GHz amplifier that adopts the double-Gmax core described in Section IV by adding the input and output matching networks. The input and output admittances of the 250 GHz double-Gmax core for simultaneous conjugate matching were 0.022-j0.024 S and 0.028-j0.027 S, respectively. The input and output real part matching can be achieved by relatively short series TLs as shown inFIG.13since the input and output conductances are quite close to 0.02 S (= 1/50). Then, the input and output susceptances can be canceled by using open stub TLs. The simulated insertion losses of the input and output matching networks of the 250 GHz amplifier were 0.9 and 1.5 dB, respectively.

All or some of the respective exemplary embodiments may be selectively combined with each other so that the above-mentioned exemplary embodiments may be variously modified.

According to the disclosed invention, gain boosting is primarily performed, and then secondarily performed to obtain a greater gain than the existing maximum achievable gain Gmax.

In addition, it is to be noted that the exemplary embodiments are provided in order to describe the present invention rather than limiting the present invention. Further, it may be understood by those skilled in the art to which the present invention pertains that various exemplary embodiments are possible without departing from the spirit and scope of the present invention.