Patent ID: 12193222

DETAILED DESCRIPTION

Exemplary implementation modes of the application will be described below more comprehensively with reference to the drawings. Although the exemplary implementation modes of the application are shown in the drawings, it should be understood that, the application may be implemented in various forms and should not be limited by the specific implementation modes elaborated herein. On the contrary, these implementation modes are provided to enable a more thorough understanding of the application and to fully convey the scope of the disclosure of the application to those skilled in the art.

In the following description, a large number of specific details are given in order to provide a more thorough understanding of the application. However, it will be apparent to those skilled in the art that the application may be implemented without one or more of these details. In other examples, in order to avoid confusion with the application, some technical features known in the art are not described. That is, all the features of the actual embodiments are not described here, and the known functions and structures are not described in detail.

In the drawings, the dimensions of layers, areas and elements and their relative dimensions may be exaggerated for clarity. Throughout, the same reference numerals represent the same elements.

It is to be understood that description that an element or layer is “above”, “adjacent to”, “connected to”, or “coupled to” another element or layer may refer to that the element or layer is directly above, adjacent to, connected to or coupled to the other element or layer, or there may be an intermediate element or layer. On the contrary, description that an element is “directly on”, “directly adjacent to”, “directly connected to” or “directly coupled to” another element or layer refers to that there is no intermediate element or layer. It is to be understood that, although various elements, components, areas, layers and/or parts may be described with terms first, second, third, etc., these elements, components, areas, layers and/or parts should not be limited to these terms. These terms are used only to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, a first element, component, area, layer or part discussed below may be represented as a second element, component, area, layer or part without departing from the teaching of the application. However, when the second element, component, area, layer or part is discussed, it does not mean that the first element, component, area, layer or part must exist in the application.

The terms used herein are intended only to describe specific embodiments and are not a limitation of the application. As used herein, singular forms “a/an”, “one”, and “the” may also be intended to include the plural forms, unless otherwise specified types in the context. It is also to be understood that, when terms “composed of” and/or “including” are used in this specification, the presence of the features, integers, steps, operations, elements, and/or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups is also possible. As used herein, term “and/or” includes any and all combinations of the related listed items.

In a DRAM process technology, it is more and more difficult to increase the process integration of a semiconductor process and reduce the component size. Especially, in an array process of a DRAM, the process flow of each device needs to overcome a series of process problems and some problems that may be avoided in the connection of the process flow. However, in the manufacturing process of the DRAM, simply increasing the height of a capacitor will greatly increase the difficulty of capacitor etching.

The embodiment of the application provides a semiconductor structure and a method for forming a semiconductor structure. A semiconductor structure with relatively large charge capacity may be manufactured through the method for forming a semiconductor device provided in the embodiment of the application.

FIG.1is an optional schematic diagram of a method for forming a semiconductor structure provided in the embodiment of the application. As shown inFIG.1, the method may include the following operations.

At S101, a substrate structure is provided, in which the substrate structure at least includes bit line structures and a plurality of landing pads, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap is formed between each two adjacent landing pads of the plurality of landing pads.

In some embodiments, the substrate structure may also include a semiconductor substrate, the bit line structures are formed on a surface of the semiconductor substrate. In an embodiment of the application, the substrate structure may include a plurality of bit line structures arranged in parallel. Herein, the semiconductor substrate may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP) or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or a combination thereof.

The semiconductor substrate may include a top surface on the front and a bottom surface on the back opposite to the front. In the case of ignoring the flatness of the top surface and the bottom surface, a direction perpendicular to the top surface and the bottom surface of the semiconductor substrate is defined as a first direction. A second direction and a third direction intersecting with each other (e.g., perpendicular to each other) are defined with respect to the direction of the top surface and the bottom surface of the semiconductor substrate (i.e., the plane where the semiconductor substrate is located). For example, the arrangement direction of a plurality of bit line structures may be defined as the second direction, the extension direction of the bit line structures may be defined as the third direction, and the direction of the plane where the semiconductor substrate is located may be determined based on the second direction and the third direction. Here, any two of the first direction, the second direction and the third direction are perpendicular to each other. In the embodiment of the application, the first direction is defined as the Z-axis direction, the second direction is defined as the X-axis direction, and the third direction is defined as the Y-axis direction.

In the embodiment of the application, the landing pads are configured to be electrically connected to capacitive structures formed later, and a gap is formed between two adjacent landing pads. Here, the two adjacent landing pads refer to the two adjacent landing pads along the arrangement direction (i.e., the second direction) of the bit line structures.

At S102, capacitive structures are formed on top surfaces of the plurality of the landing pads and in the gaps.

In the embodiment of the application, each capacitive structure may be a capacitor with a cup-shape.

In the embodiment of the application, since the capacitive structures may be not only formed on the upper surfaces of the landing pads, but also formed in the gaps between adjacent landing pads. In this way, a semiconductor structure with relatively large charge capacity may be manufactured.

FIG.2AtoFIG.2Kare schematic flowchart diagrams illustrating the formation of a semiconductor substrate according to an embodiment of the application. The method for forming the semiconductor structure provided in the embodiment of the application will be further described in detail below with reference toFIG.2AtoFIG.2K.

At first, with reference toFIG.2AandFIG.2B, S101is executed. A substrate structure is provided, in which the substrate structure at least includes bit line structures and a plurality of landing pads, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap is formed between each two adjacent landing pads of the plurality of landing pads.

As shown inFIG.2AtoFIG.2B, the substrate structure includes a semiconductor substrate101and a plurality of bit line structures102formed on a surface of the semiconductor substrate101. Herein, the semiconductor substrate101includes a plurality of active areas1011in array pattern and a shallow trench isolation structure1012configured to isolate the active areas1011from each other. The bit line structures102are formed on the surfaces of the active areas1011and are in contact with the active areas1011through bit line contact structures. The substrate structure also includes a plurality of landing pads (LP)103, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap V1is formed between each two adjacent landing pads103of the plurality of landing pads along the X-axis direction.

Each bit line structure102may include a bit line contact layer1021, a bit line metal layer1022and a bit line mask layer1023which are sequentially arranged onto one another from bottom to top along the Z-axis direction. The material of the bit line contact layer1021may be polysilicon. The material of the bit line metal layer1022may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof. The material of the bit line mask layer may be silicon nitride.

In some embodiments, the substrate structure also includes a word line structure (not shown in the figure) buried in the semiconductor substrate101and a first spacer layer, a sacrificial spacer layer102aand a second spacer layer102bsequentially formed on the side wall of each bit line structure102. The dimensions of the first spacer layer, the sacrificial spacer layer102aand the second spacer layer102bare sequentially reduced along the Z-axis direction.

In some embodiments, the substrate structure also includes a storage Node Contact (NC)104, and each of the storage node contacts is formed around a respective one of the bit line structures102and is in contact with a respective one of the plurality of landing pads103. The plurality of landing pads and the gaps may be formed by the following operations.

At S1011, a conductive layer covering the bit line structures is formed on a surface of each storage node contact, in which a top surface of the conductive layer exceeds a top surface of each bit line structure.

As shown inFIG.2A, a conductive layer103acovering the bit line structures102is formed on the surface of each storage node contact104, in which the top surface of the conductive layer103aexceeds the top surface of each bit line structure102.

In the embodiment of the application, the conductive layer may be formed by any suitable deposition process, such as a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a spin coating process or a coating process.

At S1012, a patterned second mask layer is formed on a surface of the conductive layer.

Please with reference toFIG.2A, a patterned second mask layer105is formed on the surface of the conductive layer103a. The patterned second mask layer105is provided with a plurality of openings, and each opening exposes the top surface of a part of the conductive layer103a.

In some embodiments, the second mask layer may be an Amorphous Carbon Layer (ACL), a Spin-on Hard mask (SOH), a polysilicon layer or a silicon oxynitride layer.

At S1013, a part of the conductive layer and a part of the first spacer layer are etched through the patterned second mask layer until the sacrificial spacer layer is exposed, to form the plurality of landing pads on surfaces of the storage node contacts and the gaps between adjacent landing pads.

As shown inFIG.2B, a part of the conductive layer103aand a part of the first spacer layer are etched through the openings of the patterned second mask layer105until the sacrificial spacer layer102ais exposed, to form the plurality of landing pads103on the surfaces of the storage node contacts104and the gaps V1located between adjacent landing pads.

The gap V1located between adjacent landing pads formed in the embodiment of the application has a stepped cross section along the XZ direction, herein, the Z-axis direction (i.e., the first direction) is perpendicular to the extension direction (i.e., the third direction) of the bit line structures and the arrangement direction (i.e., the second direction) of the bit line structures.

Next, with reference toFIG.2CtoFIG.2K, S102is executed. The capacitive structures are formed on the top surfaces of the plurality of landing pads and in the gaps.

In some embodiments, S102may include the following operations.

At S1021, first insulating layers are formed in the gaps, in which the first insulating layers are flush with surfaces of the landing pads.

As shown inFIG.2CandFIG.2D, firstly, the gaps V1are filled with an insulating material to form an initial insulating layer106a. Due to the influence of a process, the initial insulating layer106ausually covers the surfaces of the landing pads103. Secondly, the initial insulating layer106ais processed through dry etching or Chemical Mechanical Polishing (CMP) to expose the surfaces of the landing pads103. In this way, the first insulating layers106are formed in the gaps V1. In the embodiment of the application, the first insulating layers may be a silicon oxide layer.

At S1022, a stack structure is formed on the surfaces of the plurality of landing pads and surfaces of the first insulating layers.

In the embodiment of the application, the stack structure includes a sacrificial layer and a supporting layer, herein, the sacrificial layer and the supporting layer are alternately stacked onto one another along the Z-axis direction. The sacrificial layer may be an oxide layer, such as a silicon oxide layer. The supporting layer may be a nitride layer, such as a silicon nitride layer. Here, the stack structure may be formed by any suitable deposition process.

As shown inFIG.2E, a stack structure107is formed on the surfaces of the landing pads103and the surfaces of the first insulating layers106. In the embodiment of the application, the stack structure107may include a first sacrificial layer1071, a first supporting layer1072, a second sacrificial layer1073and a second supporting layer1074sequentially stacked onto one another from bottom to top along the Z-axis direction.

At S1023, the stack structure and the first insulating layers are processed to form the capacitive structures.

In some embodiments, S1023may be achieved through the following operations.

At S1, the stack structure is patterned to form capacitive holes in the stack structure on the surfaces of the plurality of landing pads.

In some embodiments, before S1is executed, the method for forming the semiconductor structure also includes the following operation. A first mask layer is formed on a surface of the second supporting layer.

Please with reference toFIG.2E, a first mask layer108is formed on the surface of the second supporting layer1074. The material of the first mask layer108may be the same as or different from the material of the patterned second mask layer105.

In some embodiments, S1may be achieved through the following operations.

At S11, the first mask layer is patterned.

At S12, the second supporting layer, the second sacrificial layer, the first supporting layer and the first sacrificial layer on the surfaces of the plurality of landing pads are etched by using the patterned first mask layer as a mask to form a plurality of capacitive holes.

As shown inFIG.2F, the second supporting layer1074, the second sacrificial layer1073, the first supporting layer1072and the first sacrificial layer1071located on the surfaces of the plurality of landing pads103are etched through the patterned first mask layer to form a plurality of capacitive holes109.

At S2, first electrode layers are formed on inner walls of the capacitive holes and on a surface of the patterned stack structure.

Please with reference toFIG.2F, first electrode layers110are formed on the inner walls of the capacitive holes109and on the surface of the patterned stack structure. In the embodiment of the application, the first electrode layer110may be a titanium nitride layer.

At S3, the supporting layer is patterned to form openings between adjacent capacitive holes.

At S4, the sacrificial layer and the first insulating layers are etched through the openings.

In some embodiments, the patterned stack structure includes the first sacrificial layer, the first supporting layer, the second sacrificial layer and the second supporting layer stacked onto one another, and the first mask layer and the first electrode layers are formed on the surface of the patterned stack structure. S3and S4may be achieved through the following operations.

A first opening is formed in the first mask layer and the second supporting layer.

The second sacrificial layer is removed through the first opening.

As shown inFIG.2G, a first opening111ais formed in the first mask layer108and the second supporting layer1074by using a conventional etching process, and the second sacrificial layer1073is removed through the first opening111a. In the embodiment of the application, the second sacrificial layer1073may be removed by using a wet etching solution through a wet etching process. In the embodiment of the application, when the first opening111ais formed, the first electrode layers located on the top surface of the first mask layer108are removed.

A second opening is formed in the first supporting layer.

The first sacrificial layer and the first insulating layer are removed through the second opening.

As shown inFIG.2HandFIG.2I, a second opening111bis formed in the second supporting layer1074by using the conventional etching process, and the first sacrificial layer1071and the first insulating layer106are removed through the second opening111b. In the embodiment of the application, the first sacrificial layer1071and the first insulating layer106are removed by using the wet etching solution through the wet etching process.

In some embodiments, the second sacrificial layer1073and the first insulating layer106may be made of the same material or different materials.

In the embodiment of the application, the first opening111aand the second opening111bmay be formed by dry etching process, such as a plasma etching process.

In some embodiments, a side wall of each bit line structure102is formed with a first spacer layer, a second spacer layer102aand a sacrificial spacer layer102blocated between the first spacer layer and the second spacer layer, and the first insulating layer106is connected with the sacrificial spacer layer102a. The method for forming the semiconductor structure also includes the following operation. The sacrificial spacer layer is removed when the first sacrificial layer and the first insulating layer are removed through the second opening. The first sacrificial layer and the sacrificial spacer layer are formed of the same material.

Please with reference toFIG.2I, a sacrificial spacer layer102aon the side wall of each bit line structure102is removed when the first sacrificial layer1071and the first insulating layer106are removed, to form an air gap G located on the side wall of each bit line structure. The air gap G communicates with the gap V1, and the air gap G may reduce the electric leakage of the semiconductor structure.

In some embodiments, the second sacrificial layer, the first sacrificial layer, the first insulating layer and the first spacer layer may be removed through etching solutions, such as sulfuric acid, hydrofluoric acid and nitric acid, by a wet etching process.

At S5, the capacitive structures are formed in the patterned supporting layer.

In some embodiments, S5may be achieved through the following operations.

Dielectric layers and second electrode layers are sequentially deposited on surfaces of the first electrode layers.

As shown inFIG.2J, dielectric layers112and second electrode layers113are formed on the surfaces of the first electrode layers, and the dielectric layers112and the second electrode layers113are also configured to seal the air gap G. In the embodiment of the application, the dielectric layer112may be a zirconium oxide layer and/or an aluminum oxide layer, or other material layers with a high dielectric constant. The second electrode layer113may be the same as or different from the first electrode layer110.

A conductive material that fills a clearance between the second electrode layers and covers an upper surface of the stack structure is deposited. The first electrode layers, the dielectric layers, the second electrode layers and the conductive material form the capacitive structures.

As shown inFIG.2K, a conductive material114is deposited in a clearance between the second electrode layers to form complete capacitive structures. The capacitive structures may include the first electrode layers110, the dielectric layers112, the second electrode layers113and the conductive material114.

In the embodiment of the application, the conductive material may be polysilicon or any other suitable conductive material, such as tungsten, cobalt or doped polysilicon.

In the method for forming the semiconductor structure provided in the embodiment of the application, since the capacitive structures are also formed in the gaps between adjacent landing pads, the semiconductor structure with relatively large charge capacity may be manufactured. Moreover, when the capacitive structures are formed in the semiconductor structure in the embodiment of the application, air gaps located on the side walls of the bit line structures are formed, so that the electric leakage performance of the semiconductor structure may be improved.

In the embodiment of the application, by using an NON structure of two devices including a bit line (BL) and a bit line contact (BLC), a manufacturing process of increasing capacitance and an air gap to reduce electric leakage is designed. Through the over etching of the landing pads, the insulating material (such as SiO2) is filled around the landing pads, On the basis of the traditional capacitor, a BL/BLC/LP air gap structure formed integrally is formed by acid pickling (such as hydrofluoric acid), and TIN/ZrO is deposited in the gaps between the landing pads to increase the charge capacity of the capacitor.

FIG.3AtoFIG.3Iare other schematic flowchart diagrams illustrating the formation of the semiconductor substrate according to an embodiment of the application. The method for forming the semiconductor structure provided in the embodiment of the application will be further described in detail below with reference toFIG.3AtoFIG.3I.

At first, with reference toFIG.3AandFIG.3B, S101is executed. A substrate structure is provided, in which the substrate structure at least includes bit line structures and a plurality of landing pads, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap is formed between each two adjacent landing pads of the plurality of landing pads.

As shown inFIG.3A, the substrate structure includes a semiconductor substrate101and a plurality of bit line structures102formed on a surface of the semiconductor substrate101. Herein, the semiconductor substrate101includes a plurality of active areas1011and shallow trench isolation structures1012alternately arranged along the X-axis direction. Each bit line structure102includes a bit line contact layer1021, a bit line metal layer1022and a bit line mask layer1023sequentially stacked onto one another from bottom to top along the Z-axis direction. The substrate structure also includes a first spacer layer, a sacrificial spacer layer102aand a second spacer layer102bsequentially formed on the side wall of each bit line structure102. The dimensions of the first spacer layer, the sacrificial spacer layer102aand the second spacer layer102bare sequentially reduced along the Z-axis direction. The substrate structure also include a plurality of landing pads103, each of the plurality of landing pads is formed around a respective one of the bit line structures102and covers a part of the respective one of the bit line structures102.

In some embodiments, the gaps between adjacent landing pads may be formed through the following operations.

At S301, a second insulating layer is formed between each two adjacent landing pads of the plurality of landing pads, in which the second insulating layer is flush with the surfaces of the plurality of landing pads.

Please with reference toFIG.3A, a second insulating layer301is formed between each two adjacent landing pads103, in which the surface of the second insulating layer301is flush with the surfaces of the plurality of landing pads103. Herein, the second insulating layer may be a silicon oxide layer or other insulating layers.

At S302, the second insulating layer and a part of the bit line mask layer are etched to form the gaps, in which the section of each gap along the first direction is U-shaped.

Herein, the second insulating layer and the bit line mask layer may be etched by a dry etching process or a wet etching process. As shown inFIG.3B, the second insulating layer301and a part of the bit line mask layer1023are etched and removed along the Z-axis direction to form a gap V2between each two adjacent landing pads103along the Z-axis direction, and the section of each gap V2along the XZ direction is U-shaped.

Next, with reference toFIG.3CtoFIG.3I, S102is executed. Capacitive structures are formed on the top surfaces of the plurality of landing pads and in the gaps.

In some embodiments, S102may include the following operations.

At S1021, first insulating layers are formed in the gaps, in which the first insulating layers are flush with the surfaces of the landing pads.

As shown inFIG.3C, the gaps V2are filled with an insulating material to form first insulating layers302, in which the surface of each first insulating layer302is flush with the surfaces of the landing pads103. The material of the first insulating layers302may be the same as or different from the material of the second insulating layer301.

It is to be noted that, the process of forming the first insulating layers302in the embodiment of the application is the same as the process of forming the first insulating layer106in the above embodiment.

At S1022, a stack structure is formed on the surfaces of the plurality of landing pads and surfaces of the first insulating layers.

In the embodiment of the application, the stack structure may include a sacrificial layer and a supporting layer. As shown inFIG.3D, a stack structure107is formed on the surfaces of the landing pads103and the surfaces of the first insulating layers302. In the embodiment of the application, the stack structure107includes a first sacrificial layer1071, a first supporting layer1072, a second sacrificial layer1073and a second supporting layer1074sequentially stacked onto one another from bottom to top along the Z-axis direction.

At S1023, the stack structure and the first insulating layers are processed to form the capacitive structures.

In some embodiments, S1023may be achieved through the following operations.

At S1, the stack structure is patterned to form capacitive holes in the stack structure on the surfaces of the plurality of landing pads.

In some embodiments, before S1is executed, the method for forming the semiconductor structure also includes the following operation. A first mask layer is formed on a surface of the second supporting layer.

Please with reference toFIG.3D, a first mask layer108is formed on the surface of the second supporting layer1074.

In some embodiments, S1may be achieved through the following operations.

At S11, the first mask layer is patterned.

At S12, the second supporting layer, the second sacrificial layer, the first supporting layer and the first sacrificial layer on the surfaces of the plurality of landing pads are etched by using the patterned first mask layer as a mask to form a plurality of capacitive holes.

As shown inFIG.3E, the second supporting layer1074, the second sacrificial layer1073, the first supporting layer1072and the first sacrificial layer1071located on the surfaces of the plurality of landing pads103are sequentially etched through the patterned first mask layer to form a plurality of capacitive holes109.

At S2, first electrode layers are formed on inner walls of the capacitive holes and on a surface of the patterned stack structure.

Please with reference toFIG.3E, first electrode layers110are formed on the inner walls of the capacitive holes109and on the surface of the patterned stack structure.

At S3, the supporting layer is patterned to form openings between adjacent capacitive holes.

At S4, the sacrificial layer and the first insulating layers are etched through the openings.

In some embodiments, the patterned stack structure includes the first sacrificial layer, the first supporting layer, the second sacrificial layer and the second supporting layer stacked onto one another, and the first mask layer and the first electrode layers are formed on the surface of the patterned stack structure. S3and S4may be achieved through the following operations.

A first opening is formed in the first mask layer and the second supporting layer.

The second sacrificial layer is removed through the first opening.

As shown inFIG.3F, a first opening111ais formed in the first mask layer108and the second supporting layer1074by using a conventional etching process, and the second sacrificial layer1073is removed through the first opening111a.

A second opening is formed in the first supporting layer.

The first sacrificial layer and the first insulating layer are removed through the second opening.

As shown inFIG.3G, a second opening111bis formed in the second supporting layer1074by using the conventional etching process, and the first sacrificial layer1071and the first insulating layer302are removed through the second opening111b.

In the embodiment of the application, the first opening111aand the second opening111bmay be formed by dry etching process, such as a plasma etching process.

In some embodiments, the sacrificial spacer layer102ais connected with the first insulating layer302, and the sacrificial spacer layer is removed when the first sacrificial layer and the first insulating layer are removed through the second opening.

Please with reference toFIG.3G, a sacrificial spacer layer102bon the side wall of each bit line structure102is removed when the first sacrificial layer1071and the first insulating layer302are removed, to form an air gap G located on each bit line structure or each bit line contact layer. The air gap communicates with the gap V2, and the air gap G may reduce the electric leakage of the semiconductor structure. In the embodiment of the application, the first sacrificial layer and the sacrificial spacer layer may be made of the same material or different materials.

At S5, the capacitive structures are formed in the patterned supporting layer.

In some embodiments, S5may be achieved through the following operations.

At S51, dielectric layers and second electrode layers are sequentially deposited on surfaces of the first electrode layers.

At S52, a conductive material that fills a clearance between the second electrode layers and covers an upper surface of the stack structure is deposited. The first electrode layers, the dielectric layers, the second electrode layers and the conductive material form the capacitive structures.

As shown inFIG.3H, dielectric layers112and second electrode layers113are formed on the surfaces of the first electrode layers, and the dielectric layers112and the second electrode layers113are also configured to seal the air gaps G. As shown inFIG.3J, a conductive material114is deposited in a clearance between the second electrode layers to form complete capacitive structures. The capacitive structures may include the first electrode layers110, the dielectric layers112, the second electrode layers113and the conductive material114.

The method for forming the semiconductor structure in the embodiment of the application is similar to the method for forming the semiconductor structure in the above embodiment. The technical features not disclosed in detail in the embodiment of the application refer to the above embodiment for understanding, and will not be elaborated here.

In the method for forming the semiconductor structure provided in the embodiment of the application, since the capacitive structures are also formed in the gaps between adjacent landing pads, the semiconductor structure with relatively large charge capacity may be manufactured. Moreover, when the capacitive structures are formed in the semiconductor structure in the embodiment of the application, air gaps located on the side walls of the bit line structures are formed, so that the electric leakage performance of the semiconductor structure may be improved.

In addition, the embodiment of the application also provides a semiconductor structure. As shown inFIG.4AandFIG.4B, the semiconductor structure40includes a substrate structure and capacitive structures401.

The substrate structure includes a plurality of bit line structures102arranged in parallel along the X-axis direction and a plurality of landing pads103, and each of the plurality of landing pads is formed around a respective one of the bit line structures102and covers a part of the respective one of the bit line structures. A gap V1or gap V2is formed between each two adjacent landing pads103. As shown inFIG.4A, the section of each gap V1along the XZ direction is stepped, and the Z-axis direction is perpendicular to the extension direction of the bit line structures102and the arrangement direction of the bit line structures102(i.e. the X-axis direction). Each of the bit line structures102includes a bit line contact layer1021, a bit line metal layer1022and a bit line mask layer1023sequentially stacked onto one another from bottom to top along the Z-axis direction. As shown inFIG.4B, the section of each gap V2along the XZ direction is U-shaped. Each of the bit line structures102includes the bit line contact layer1021, the bit line metal layer1022and a part of the bit line mask layer1023sequentially stacked onto one another from bottom to top along the Z-axis direction.

In some embodiments, the substrate structure also includes a semiconductor substrate101. The semiconductor substrate101includes a plurality of active areas1011in array pattern and shallow trench isolation structures1012configured to isolate the active areas1011from each other. The bit line structures102are formed on the surfaces of the active areas1011and are in contact with the active areas1011through bit line contact structures. The substrate structure also includes storage node contacts104, and each of the storage node contacts is formed around a respective one of the bit line structures102and in contact with a respective one of the landing pads103.

In some embodiments, the substrate structure also includes a word line structure (not shown in the figure) buried in the semiconductor substrate101.

The capacitive structures401are located on the top surfaces of the landing pads103and in the gaps V1or gaps V2.

In some embodiments, the capacitive structures401include first electrode layers110, dielectric layers112and second electrode layers113sequentially stacked onto one another, and a conductive material114is filled between adjacent second electrode layers113.

In the embodiment of the application, the capacitive structures401have a cup shape, and the extension direction (Z-axis direction) of the capacitive structures is perpendicular to the top surfaces of the landing pads103. A first supporting layer1072and a second supporting layer1074parallel to each other are also arranged between the capacitive structures401. The first supporting layer1072is arranged on the middle periphery of the capacitive structures401, the second supporting layer1074is arranged on the top periphery of the capacitive structures401, and the first supporting layer1072and the second supporting layer1074are configured to support the capacitive structures401.

In some embodiments, the thickness h1of the second supporting layer1074is greater than the thickness h2of the first supporting layer1072, so that a better supporting effect may be achieved.

In some embodiments, the side wall of each bit line structure102is formed with a first spacer layer, a second spacer layer102aand an air gap G between the first spacer layer and the second spacer layer102b, herein, the air gap G is connected with a respective one of the dielectric layers112.

The method for forming the semiconductor structure in the embodiment of the application is similar to method for forming the semiconductor structure in the above embodiment. The technical features not disclosed in detail in the embodiment of the application refer to the above embodiment for understanding and will not be elaborated here.

In the semiconductor structure provided in the embodiment of the application, the capacitive structures are not only located on the top surfaces of the landing pads, but also in the gaps between adjacent landing pads. In this way, the manufactured semiconductor structure may have relatively large charge capacity. Moreover, the semiconductor structure in the embodiment of the application is provided with an air gap located on the side wall of each bit line structure, so that the electric leakage performance of the formed semiconductor structure may be improved.

In several embodiments provided in the application, it should be understood that, the disclosed devices and methods may be realized in a non-target manner. The device embodiments described above are only schematic. For example, the division of the unit is only a logical function division, and there may be another division mode in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the components shown or discussed are coupled to each other, or directly coupled.

The features disclosed in several methods or device embodiments provided by the disclosure may be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only some implementation mode of the embodiment of the disclosure and not intended to limit the scope of protection of the embodiment of the disclosure. Modifications or replacements are apparent to those skilled in the art within the technical scope disclosed by the embodiment of the disclosure, and these modifications or replacements shall fall within the scope of protection of the embodiment of the disclosure. Therefore, the scope of protection of the embodiment of the disclosure should be subject to the appended claims.