Patent ID: 12193223

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A one-time-programmable (OTP) memory device generally includes an array of memory cells. In some embodiments, a one-bit memory cell includes an anti-fuse structure and a read transistor. The anti-fuse structure has a dielectric layer overlying a semiconductor region that is conductively connected to a first semiconductor terminal of the read transistor, while a second semiconductor terminal of the read transistor is conductively connected to a bit conducting line. The gate of the anti-fuse structure is conductively connected to a word programming line, and the gate terminal of the read transistor is conductively connected to a word read line. After the memory device is programmed, the resistive value of the dielectric layer between the semiconductor region and the gate of the anti-fuse structure corresponds to the stored logic value in the one-bit memory cell.

During the read operation, when the read transistor is turned on and a reading voltage is applied to the word programming line, a current passing through the dielectric layer of the anti-fuse structure is induced. The induced current, after passing through the semiconductor channel of the read transistor and through the bit conducting line, is detected by a sense amplifier. The induced current detected by the sense amplifier is used to determine the stored logic value in the one-bit memory cell. In some embodiments, improving the conductive connection between the word programming line and the gate of the anti-fuse structure improves the sensitivity and the reliability for the sense amplifier to detect the current passing through the dielectric layer of the anti-fuse structure. In some embodiments, improving the conductive connection between the second semiconductor terminal of the read transistor and the bit conducting line also improves the sensitivity and the reliability for the sense amplifier to detect the current passing through the dielectric layer of the anti-fuse structure.

FIG.1is a flowchart of a method100of generating a layout design of a memory device in accordance with some embodiments.FIGS.2-3,FIG.4AandFIG.5Aare partial layout diagrams of memory devices at various stages of layout design processes, in accordance with some embodiments.

In operation110of the method100inFIG.1, an array of active zone patterns is generated. Each active zone pattern specifies a corresponding active zone in the memory device. In operation120, programming gate-strip patterns and read gate-strip patterns are generated intersecting the active zone patterns. Each programming gate-strip pattern specifies a corresponding programming gate-strip in the memory device. Each read gate-strip pattern specifies a corresponding read gate-strip in the memory device. In operation130, terminal conductor patterns intersecting the active zone patterns are generated. Each terminal conductor pattern specifies a corresponding terminal conductor in the memory device. In some embodiments, the partial layout diagram of the memory device generated after operation130is show inFIG.2.

As specified by the partial layout diagram ofFIG.2, the memory device includes an array of active zones251-254extending in the X-direction, programming gate-strips220A and220B extending in the Y-direction, and read gate-strips240A and240B extending in the Y-direction. The Y-direction is perpendicular to the X-direction. The memory device also includes terminal conductors261,262,263, and264extending in the Y-direction. The terminal conductors261,262,263, and264provides the source terminals or drain terminals of the transistors in the active zone.

The programming gate-strips220A and220B are configured to program anti-fuse structures. The programming gate-strip220A intersects each of the active zones251-254over a semiconductor region of an anti-fuse structure programmable by the programming gate-strips220A, while the conductive coupling between the programming gate-strips220A and the semiconductor region depends upon the isolation properties of a dielectric layer overlying the semiconductor region. The programming gate-strip220B intersects each of the active zones251-254over a semiconductor region of an anti-fuse structure programmable by the programming gate-strips220B, while the conductive coupling between the programming gate-strips220B and the semiconductor region depends upon the isolation properties of a dielectric layer overlying the semiconductor region. The read gate-strips240A and240B are configured to control channel conductivities of read transistors. The read gate-strip240A intersects each of the active zones251-254over a channel region of a read transistor having the gate electrode connected to the read gate-strip240A. The read gate-strip240B intersects each of the active zones251-254over a channel region of a read transistor having the gate electrode connected to the read gate-strip240B. Each of the terminal conductors261,262,263, and264intersects correspondingly the active zones251,252,253, or254over a terminal region of a first read transistor and a second read transistor, while the gate electrodes of the first read transistor and the second read transistor are correspondingly connected to the read gate-strip240A and the read gate-strip240B. A terminal region of a transistor is either a source region of the transistor or a drain region of the transistor.

InFIG.1, after operation130, more layout patterns are generated. In operation140, programming conducting line patterns, read conducting line patterns, and bit connector patterns are generated. Each programming conducting line pattern specifies a corresponding programming conducting line in the memory device, each read conducting line pattern specifies a corresponding read conducting line in the memory device, and each bit connector pattern specifies a corresponding bit connector in the memory device. In operation145, gate via-connector patterns and terminal via-connector patterns are positioned at various locations. Each gate via-connector pattern specifies a corresponding gate via-connector in the memory device, and each terminal via-connector pattern specifies a corresponding terminal via-connector in the memory device. The gate via-connector patterns are positioned at intersections between the programming gate-strip patterns and the programming conducting line patterns and at intersections between the programming gate-strip patterns and the read conducting line patterns. The terminal via-connector patterns are positioned at the overlapped areas formed by the bit connector patterns and the terminal conductor patterns. In some embodiments, the partial layout diagram of the memory device generated after operation145is show inFIG.3.

The partial layout diagram ofFIG.3includes additional drawing patterns superimposed on the partial layout diagram ofFIG.2. As specified by the partial layout diagram ofFIG.3, the memory device also includes programming conducting lines arranged in groups (391A,392A,393A,394A) for the programming gate-strip220A and programming conducting lines arranged in groups (391B,392B,393B,394B) for the programming gate-strip220B. Each programming conducting line extends in the X-direction. The programming conducting lines in the group391A and in the group391B are associated with the active zone251. The programming conducting lines in the group392A and in the group392B are associated with the active zone252. The programming conducting lines in the group393A and in the group393B are associated with the active zone253. The programming conducting lines in the group394A and in the group394B are associated with the active zone254. Each of the programming conducting lines in the groups391A,392A,393A, and394A is conductively connected to the programming gate-strip220A through the gate via-connector VG. Each of the programming conducting lines in the groups391B,392B,393B, and394B is conductively connected to the programming gate-strip220B through the gate via-connector VG.

As specified by the partial layout diagram ofFIG.3, the memory device further includes bit connectors361,362,363, and364. Each of the bit connectors361,362,363, and364is conductively connected to one of the corresponding terminal conductors261,262,263, and264through a terminal via-connector VD.

As specified by the partial layout diagram ofFIG.3, the memory device also includes read conducting lines312and334for the read gate-strip240A and read conducting lines323and345for the read gate-strip240B. The read conducting lines312extending in the X-direction is parallelly positioned between the active zones251and the active zones252. The read conducting lines334extending in the X-direction is parallelly positioned between the active zones253and the active zones254. The read conducting lines323extending in the X-direction is parallelly positioned between the active zones252and the active zones253. The read conducting lines345extending in the X-direction is parallelly positioned between the active zones254and another adjacent active zone (not shown in the figure). Each of the read conducting lines312and334is conductively connected to the read gate-strip240A through the gate via-connector VG. Each of the read conducting lines323and345is conductively connected to the read gate-strip240B through the gate via-connector VG.

InFIG.1, after operation145, more layout patterns are generated. In operation150, word programming line patterns, word read line patterns, and bit electrode patterns are generated. Each word programming line pattern specifies a corresponding word programming line in the memory device. Each word read line pattern specifies a corresponding word read line in the memory device. Each bit electrode pattern specifies a corresponding bit electrode in the memory device. In operation155, via-connector VIA0patterns are positioned at various locations. Each via-connector VIA0pattern specifies a corresponding via-connector VIA0in the memory device. Some of the via-connector VIA0patterns are positioned at intersections between the programming conducting line patterns and the word programming line patterns. Some of the via-connector VIA0patterns are positioned at intersections between the read conducting line patterns and the word read line patterns. Some of the via-connector VIA0patterns are positioned at the overlapped areas formed by the bit electrode patterns and the bit connector patterns. In some embodiments, the partial layout diagram of the memory device generated after operation155is show inFIG.4A.

The partial layout diagram ofFIG.4Aincludes additional drawing patterns superimposed on the partial layout diagram ofFIG.3. As specified by the partial layout diagram ofFIG.4A, the memory device further includes bit electrodes461,462,463, and464. Each of the bit electrodes461,462,463, and464is conductively connected to one of the corresponding bit connectors361,362,363, and364through a via-connector VIA0. As specified by the partial layout diagram ofFIG.4A, the memory device also includes word programming lines420A and420B extending in the Y-direction and word read lines440A and440B extending in the Y-direction. The word programming line420A is conductively connected to the programming conducting lines in the groups391A,392A,393A, and394A through the via-connectors VIA0at the intersections between the word programming lines420A and the programming conducting lines. The word programming line420B is conductively connected to the programming conducting lines in the groups391B,392B,393B, and394B through the via-connectors VIA0at the intersections between the word programming lines420B and the programming conducting lines. The word read line440A is conductively connected to the read conducting lines312and334through the via-connectors VIA0at the intersections between the word read lines440A and the read conducting lines. The word read line440B is conductively connected to the read conducting lines323and345through the via-connectors VIA0at the intersections between the word read lines440B and the read conducting lines.

FIG.4Bis a cross-sectional view of the memory device in a cutting plane as specified by the line P-P′ inFIG.4A, in accordance with some embodiments. InFIG.4B, the word programming line420A is conductively connected to the programming gate-strip220A through the programming conducting lines in the group392A. The programming conducting lines in the group392A overlie an insulation layer ILD1of inter-layer-dielectric materials. The insulation layer ILD1covers the programming gate-strip220A and the semiconductor materials in the active zone252. In some embodiments, the semiconductor materials in the active zone252as shown inFIG.4Bis a cross-section of a fin structure. The programming gate-strip220A forms a gate electrode of an anti-fuse structure. The anti-fuse structure has a dielectric layer456between the programming gate-strip220A and a semiconductor region458in the active zone252. The gate via-connector VG, which passes though the insulation layer ILD1, conductively connects the programming conducting line in the group392A to the programming gate-strip220A. InFIG.4B, the word programming line420A and the word read line440A overlie an insulation layer ILD2of inter-layer-dielectric materials. The insulation layer ILD2covers the programming conducting lines in the group392A and the insulation layer ILD1. The via-connector VIA0, which passes though the insulation layer ILD2, conductively connects the word programming line420A to the programming conducting line in the group392A.

FIG.4Cis a cross-sectional view of the memory device in a cutting plane as specified by the line Q-Q′ inFIG.4A, in accordance with some embodiments. InFIG.4C, the bit electrode462is conductively connected to the terminal conductor262through the bit connector362. The bit electrode462overlies the insulation layer ILD2which covers the bit connector362and the insulation layer ILD1. The bit connector362overlies the insulation layer ILD1which covers the terminal conductor262. The terminal conductor262overlaps the source/drain regions of two read transistors in the active zone252. One of the two read transistors (as specified inFIG.4A) has the channel region at the intersection (inFIG.4A) between the read gate-strips240A and the active zone252. Another one of the two read transistors (as specified inFIG.4A) has the channel region at the intersection (inFIG.4A) between the read gate-strips240B and the active zone252. In some embodiments, the read transistors are formed with fin structures. In the non-limiting example ofFIG.4C, the read transistors are formed with three fin structures within the active zone252, and the terminal conductor262forms conductive contact with the source/drain regions in the three fin structures. In alternative embodiments, the read transistors are formed as planar transistors, and the terminal conductor262forms conductive contact with the source/drain regions in the heavily doped diffusion regions of the active zone252. In still alternative embodiments, the read transistors are formed as nano transistors, and the terminal conductor262forms conductive contact with the source/drain regions in the nano-wires or the nano-sheets of the nano transistors. InFIG.4C, the via-connector VIA0, which passes though the insulation layer ILD2, conductively connects the bit electrode462with the bit connector362. The terminal via-connector VD, which passes though the insulation layer ILD1, conductively connects the bit connector362with the terminal conductor262.

InFIG.1, after operation155, more layout patterns are generated. In operation160, bit conducting line patterns are generated. Each bit conducting line pattern specifies a corresponding bit conducting line in the memory device. In operation165, via-connector VIA1patterns are positioned at various locations. Each via-connector VIA1pattern specifies a corresponding via-connector VIA1in the memory device. The via-connector VIA1patterns are positioned at the overlapped areas formed by the bit electrode patterns and the bit conducting line patterns. In some embodiments, the partial layout diagram of the memory device generated after operation165is show inFIG.5A.

The partial layout diagram ofFIG.5Aincludes additional drawing patterns superimposed on the partial layout diagram ofFIG.4A. As specified by the partial layout diagram ofFIG.5A, the memory device includes bit conducting lines510,520,530, and540extending in the X-direction. Each of the bit conducting lines (510,520,530, and540) is conductively connected to a corresponding bit electrode (461,462,463, or464) through a via-connector VIAL

FIG.5Bis a cross-sectional view of the memory device in a cutting plane as specified by the line P-P′ inFIG.5A, in accordance with some embodiments.FIG.5Cis a cross-sectional view of the memory device in a cutting plane as specified by the line Q-Q′ inFIG.5A, in accordance with some embodiments. InFIG.5BandFIG.5C, the bit conducting line520overlies the insulation layer ILD3. InFIG.5B, the insulation layer ILD3covers the word programming line420A and the word read line440A. InFIG.5C, the insulation layer ILD3covers the bit electrode462. The via-connector VIA1, which passes though the insulation layer ILD3, conductively connects the bit conducting line520to the bit electrode462.

In the partial layout diagram ofFIG.4A, the area of a via-connector VIA0is larger than the area of a gate via-connector VG, and the boundary of a gate via-connector VG is within the boundary of a via-connector VIA0. In alternative embodiments, the area of a via-connector VIA0is smaller than the area of a gate via-connector VG, the boundary of a via-connector VIA0is within the boundary of a gate via-connector VG. In some embodiments, the area of a via-connector VIA0is equal to the area of a gate via-connector VG, and a via-connector VIA0and a gate via-connector VG occupy the same area in a layout diagram.

In the partial layout diagram ofFIG.5A, the area of a via-connector VIA1is larger than the area of a via-connector VIA0and the area of the terminal via-connector VD. In alternative embodiments, the area of a via-connector VIA1is smaller than the area of a via-connector VIA0and/or the area of the terminal via-connector VD. In some embodiments, the area of a via-connector VIA1is equal to the area of a via-connector VIA0and/or the area of the terminal via-connector VD. In some embodiments, as shown inFIGS.6A-6CandFIGS.7A-7C, some of the via-connector VIA1, the via-connector VIA0, the gate via-connector VG, and the terminal via-connector VD do not have overlapped area.

FIG.6Ais a partial layout diagram of a memory device at an intermediate stage of layout design processes, in accordance with some embodiments.FIG.6Bis a cross-sectional view of the memory device in a cutting plane as specified by the line P-P′ inFIG.6A, in accordance with some embodiments.FIG.6Cis a cross-sectional view of the memory device in a cutting plane as specified by the line Q-Q′ inFIG.6A, in accordance with some embodiments. With the exception of the via-connector VIA0patterns, the layout design inFIG.6Ais identical to the layout design inFIG.4A. As a comparison, a via-connector VIA0pattern inFIG.4Aoverlaps with a gate via-connector VG pattern or a terminal via-connector VD pattern. InFIG.6A, however, a via-connector VIA0pattern does not overlap with a gate via-connector VG or with a terminal via-connector VD. For example, inFIG.6AandFIG.6B, the via-connector VIA0for connecting the word programming line420A with the programming conducting line (e.g., in the group392A) is shifted in the X-direction relative to the gate via-connector VG for connecting the programming gate-strip220A with the programming conducting line (e.g., in the group392A). InFIG.6AandFIG.6C, the via-connector VIA0for connecting the bit electrode (e.g.,462) with the bit connector (e.g.,362) is shifted in the Y-direction relative to the terminal via-connector VD for connecting the terminal conductor (e.g.,262) with the bit connector (e.g.,362).

FIG.7Ais partial layout diagram of a memory device at an intermediate stage of layout design processes, in accordance with some embodiments.FIG.7Bis a cross-sectional view of the memory device in a cutting plane as specified by the line P-P′ inFIG.7A, in accordance with some embodiments.FIG.7Cis a cross-sectional view of the memory device in a cutting plane as specified by the line Q-Q′ inFIG.7A, in accordance with some embodiments. With the exception of the via-connector VIAL patterns and the via-connector VIA0patterns, the layout design inFIG.7Ais identical to the layout design inFIG.5A. As a comparison, a via-connector VIAL inFIG.5Aoverlaps with a via-connector VIA0and a terminal via-connector VD. InFIG.7A, however, a via-connector VIAL does not overlap with a via-connector VIA0or a terminal via-connector VD. For example, inFIG.7AandFIG.7C, the via-connector VIAL for connecting the bit conducting line520with the bit electrode462is shifted in the Y-direction relative to the via-connector VIA0for connecting the bit electrode462with the bit connector362. InFIG.7AandFIG.7C, the via-connector VIAL for connecting the bit conducting line520with the bit electrode462is also shifted in the Y-direction relative to the terminal via-connector VD for connecting the terminal conductor262with the bit connector362.

FIG.8Ais an equivalent circuit of the memory device as specified by one of the partial layout diagrams inFIG.5Aand inFIG.7A, in accordance with some embodiments. InFIG.8A, the gate terminals of the anti-fuse structures S1A, S2A, S3A, and S4A are connected by the programming gate-strip220A, and the gate terminals of the anti-fuse structures S1B, S2B, S3B, and S4B are connected by the programming gate-strip220B. Each of the gate terminals of the anti-fuse structures S1A, S2A, S3A, and S4A is connected to the word programming line420A correspondingly through the programming conducting lines in the groups391A,392A,393A, and394A. Each of the gate terminals of the anti-fuse structures S1B, S2B, S3B, and S4B is connected to the word programming line420B correspondingly through the programming conducting lines in the groups391B,392B,393B, and394B. InFIG.8A, each group of the programming conducting lines (e.g., each of the groups391A-394A and391B-394B) has three programming conducting lines. In other embodiments, each group of the programming conducting lines has more three programming conducting lines. The number of the programming conducting lines matches the number of connections from the gate terminal of an anti-fuse structure to a corresponding word programming line. Each connection from the gate terminal of an anti-fuse structure to a corresponding word programming line is equivalent to a resistive element inFIG.8A. The number of the programming conducting lines is selected to minimize the electric resistance of the parallel connections from the gate terminal of an anti-fuse structure to a corresponding word programming line while the areas of the programming conducting lines are maintained within the upper limit of the allocated area for the parallel connections.

InFIG.8A, the gate terminals of the read transistors T1A, T2A, T3A, and T4A are connected by the read gate-strip240A, and the gate terminals of the read transistors T1B, T2B, T3B, and T4B are connected by the read gate-strip240B. The semiconductor terminals of the read transistors T1A and T1B at the terminal conductor261are jointly connected to the bit conducting lines510. The semiconductor terminals of the read transistors T2A and T2B at the terminal conductor262are jointly connected to the bit conducting lines520. The semiconductor terminals of the read transistors T3A and T3B at the terminal conductor263are jointly connected to the bit conducting lines530. The semiconductor terminals of the read transistors T4A and T4B at the terminal conductor264are jointly connected to the bit conducting lines540. The read gate-strip240A is conductively connected to the word read line440A through read conducting lines312and334. The read gate-strip240B is conductively connected to the word read line440B through read conducting lines323and345.

InFIG.8A, the memory device includes two one-bit memory cells B11and B12in a first row, two one-bit memory cells B21and B22in a second row, two one-bit memory cells B31and B32in a third row, and two one-bit memory cells B41and B42in a fourth row. In each row of the memory device, the two anti-fuse structures, the two read transistors, and the two groups of programming conducting lines are connected as a two-bit memory cell. The two-bit memory cell in each row includes a first one-bit memory cell and a second one-bit memory cell. The first one-bit memory cell includes a first anti-fuse structure controlled by the word programming line420A, and a first read transistor controlled by the word read line440A. The first one-bit memory cell also includes the group of the programming conducting lines directly connected to the gate of the first anti-fuse structure. The second one-bit memory cell includes a second anti-fuse structure controlled by the word programming line420B, and a second read transistor controlled by the word read line440B. The second one-bit memory cell also includes the group of the programming conducting lines directly connected to the gate of the second anti-fuse structure. As an example, in the second row of the memory device, a two-bit memory cell includes two anti-fuse structures S2A and S2B, two read transistors T2A and T2B, and two groups (392A and392B) of programming conducting lines. The first one-bit memory cell B21in the second row includes the anti-fuse structures S2A, the read transistors T2A, and the group392A of programming conducting lines. The second one-bit memory cell B22in the second row includes the anti-fuse structures S2B, the read transistors T2B, and the group392B of programming conducting lines.

InFIG.8A, a column of one-bit memory cells B11, B21, B31, and B41forms an array of first one-bit memory cells, and a column of one-bit memory cells B12, B22, B32, and B42forms an array of second one-bit memory cells. The array of the first one-bit memory cells is controlled by the word programming line420A and the word read line440A. The array of the second one-bit memory cells is controlled by the word programming line420B and the word read line440B. Each one-bit memory cell in the memory device is configured to store a logic “1” or a logic “0” based on the resistance of the anti-fuse structure in the one-bit memory cell. In general, the anti-fuse structure and the read transistor in a one-bit memory cell can be based on either NMOS devices or PMOS devices.

During the programming operation, in some embodiments, one column of the one-bit memory cells is selected for programming during each allocated time period by setting the one-bit memory cells in the selected column to the programming mode, while the one-bit memory cells in other column are set to the non-programming mode. For example, the first column of one-bit memory cells B11, B21, B31, and B41is selected for programming during a first allocated time period, and the second column of one-bit memory cells B12, B22, B32, and B44is selected for programming during a second allocated time period after the first allocated time period.

During the first allocated time period, to set each of the one-bit memory cells B11, B21, B31, and B41in the first column to the programming mode, the read transistor in each of the one-bit memory cells in the first column is tuned on by a voltage applied to the word read line440A, and the gate terminal of the anti-fuse structure in each of the one-bit memory cells in the first column is maintained at a programming voltage supplied by the word programming line420A. When the one-bit memory cells in the first column are in the programming mode, the voltage level on each of the bit conducting lines510,520,530, and540correspondingly determines whether each of the one-bit memory cells B11, B21, B31, and B41is stored with a logic “1” or with a logic “0”.

When a one-bit memory cell is in the programming mode, the residual resistivity of the dielectric layer in the anti-fuse structure after the programming is determined by the voltage difference between the programming voltage applied to the gate of the anti-fuse structure and the voltage applied to the semiconductor region of the one-bit memory cell. The stored logic state (either logic “1” or a logic “0”) of the one-bit memory cell is determined by the residual resistivity of the dielectric layer in the anti-fuse structure of the one-bit memory cell after the one-bit memory cell is programed.

For example, after a programming voltage VPis applied to the word programming line420A to select the one-bit memory cells B11, B21, B31, and B41for programming, the residual resistivity of the dielectric layer in the anti-fuse structure of the one-bit memory cell B21depends upon a bit voltage v[2,1] applied to the bit conducting line520. The voltage difference VP−V[2,1] determines the residual resistivity of the dielectric layer (e.g.,456, inFIG.5BorFIG.7B) in the anti-fuse structure S2A of the one-bit memory cell B21. In some embodiments, when the anti-fuse structure S2A and the read transistor T2A are based on NMOS devices, if the voltage difference VP−V[2,1] is larger than a threshold voltage, the dielectric layer456in the anti-fuse structure S2A breaks down. As a consequence, the resistance between the gate of the anti-fuse structure S2A and the semiconductor terminal n2A of the anti-fuse structure S2A changes from a HIGH resistive value to a LOW resistive value. On the other hand, if the voltage difference VP−V[2,1] is smaller than the threshold voltage, the resistance between the gate of the anti-fuse structure S2A and the semiconductor terminal n2A of the anti-fuse structure S2A maintains at a HIGH resistive value. The range of the HIGH resistive value and the range of the LOW resistive value depend upon the thickness, the area, and the material type of the dielectric layer in the anti-fuse structure. The range of the HIGH resistive value and the range of the LOW resistive value also depend upon other design factors in the anti-fuse structure.

During the programming operation, the one-bit memory cells in the memory device are programed column by column. After the programming operation, logic values are stored in the memory device as resistive values in a matrix of residual resistors each depending upon the condition of the dielectric layer in the anti-fuse structure of a corresponding one-bit memory cell.FIG.8Bis an equivalent circuit of the memory device after the memory circuit is programed with the programming operation, in accordance with some embodiments. Each anti-fuse structure is equivalent to a residual resistor which is set to either the HIGH resistive value or the LOW resistive value during the programming operation. The resistive values of the residual resistors are read out during the read operation. InFIG.8B, each of the residual resistors R11, R21, R31, and R41is serially connected to a corresponding read transistor (T11, T21, T31, or T41) in one of the one-bit memory cells (B11, B21, B31, and B41) in the first column. Each of the residual resistors R12, R22, R32, and R42is serially connected to a corresponding read transistor (T12, T22, T32, or T42) in one of the one-bit memory cells (B12, B22, B32, and B42) in the second column.

During the read operation, in some embodiments, one column of the one-bit memory cells is selected for reading during each allocated time period by setting the one-bit memory cells in the selected column to the reading mode, while the one-bit memory cells in other column are set to the non-reading mode. For example, the first column of one-bit memory cells B11, B21, B31, and B41is selected for reading during a first reading time period, and the second column of one-bit memory cells B12, B22, B32, and B44is selected for reading during a second reading time period after the first reading time period.

In some embodiments, during the first reading time period, to set each of the one-bit memory cells B11, B21, B31, and B41in the first column to the reading mode, a selection voltage is applied to the word read line440A and a reading voltage VRis applied to the word programming line420A. The read transistor in each of the one-bit memory cells in the first column is tuned on by the applied selection voltage. When the one-bit memory cells B11, B21, B31, and B41in the first column are set to the reading mode, the induced current in each of the bit conducting lines510,520,530, or540is correspondingly related to the resistive value of the residual resistor (R11, R21, R31, or R41) in one of the one-bit memory cells in the first column. The induced current in each of the bit conducting lines510,520,530, and540is detected by a sense amplifier (not shown) and converted into one of the discrete values. The discrete values are related to the HIGH resistive value or the LOW resistive value of a corresponding residual resistor.

FIG.9Ais a three-dimensional representation of the conductive connections of the column of bit cells900in the equivalent circuit ofFIG.8A, in accordance with some embodiments. InFIG.9A, the resistivity of the programming gate-strip220A between the gate terminals of two adjacent anti-fuse structures is explicitly represented by a resistor RMG. Each connection from the word programming line420A to a gate terminal of an anti-fuse structure (e.g., S1A, S2A, S3A, or S4A) through a corresponding group of programming conducting lines (e.g.,391A,392A,393A, and394A) is represented by an equivalent resistor RM0/VG. The connections from the word programming line420A to a gate terminal of the anti-fuse structures (not shown inFIG.8A) in other one-bit memory cells adjacent to one-bit memory cells B11or B41are correspondingly represented by resistors390A and399A. When one column of the one-bit memory cells connecting to the programming gate-strip220A is selected for programming or for reading, the bit conducting lines510,520,530, and540are functioning correspondingly as the bit line BL1for the one-bit memory cell B11, the bit line BL2for the one-bit memory cell B21, the bit line BL3for the one-bit memory cell B31, and the bit line BL4for the one-bit memory cell B41. The total equivalent resistivity in the conductive path for sensing each one-bit memory cell B21is equal to RM0/VG+RMG+Rcell+RBL. Here, Rcellis the equivalent cell resistor (such as one of the residual resistors R11, R21, R31, and R41during the reading mode), and RBLis the equivalent resistance of the bit line (such as one the bit lines BL1, BL2, BL3, and BL4).

FIG.9Bis an equivalent circuit of the one-bit memory cell B21in the reading mode while the one-bit memory cell B21is in connection with the word programming line420A and the bit conducting line520, in accordance with some embodiments. In the non-limiting example ofFIG.9B, the read transistor T2A is an NMOS transistor. The gate terminal of the read transistor T2A is conductively connected to the word read line440A through an equivalent resistor RWRGbetween the word read line and the gate of the read transistor T2A. The resistive value of the equivalent resistor RWRGdepends upon the resistive values of read conducting lines312and334, the conductivity of the read gate-strip240A, the resistivity of the via-connectors VIA0(e.g., inFIGS.6A-6C) between the word read line440A and read conducting lines312and334, and the resistivity of the via-connectors VG (e.g., inFIGS.6A-6C) between the read gate-strip240A and read conducting lines312and334. The source terminal of the read transistor T2A is conductively connected to the sense amplifier SA through the bit conducting line520. The resistive value of the equivalent resistor RBLbetween the source terminal of the read transistor T2A and the input of the sense amplifier SA depends upon the resistive value of the bit conducting line510and the resistivity of the via-connectors (e.g., VD, VIA0, and VIA1inFIG.7C) for connecting the source terminal of the read transistor T2A to the bit conducting line520.

InFIG.9B, one terminal of the residual resistors R21is connected to the drain terminal of the read transistor T2A, and the other terminal of the residual resistors R21is connected to the word programming line420A through an equivalent resistor RWPGbetween the word programming line and the gate of the anti-fuse structures S2A. The resistive value of the equivalent resistor RWPGdepends upon the resistive value of each programming conducting line in the group392A, the number of programming conducting lines in the group392A, the resistivity of the via-connectors VIA0(e.g., inFIGS.6A-6C) between the word programming line420A and the programming conducting lines, and the resistivity of the via-connectors VG (e.g., inFIGS.6A-6C) between the programming gate-strip220A and the programming conducting lines. While the resistive value of the equivalent resistor RWPGmay also depends upon the resistivity of the programming gate-strip220A, the contribution to the resistive value of the equivalent resistor RWPGby the resistivity of the programming gate-strip220A is negligible in some embodiments. For example, when the layout pattern of each programming conducting line in the group392B overlaps with the layout pattern of the active zones252in the partial layout patternFIG.3, in some embodiments, the resistivity of the programming gate-strip220A in a fabricated device does not significantly impact the resistive value of the equivalent resistor RWPG.

When the reading voltage VRis applied to the word programming line420A, the induced current Ireadflowing through the residual resistor R21is detected by the sense amplifier SA. The induced current Ireadinversely proportional to the total resistive value due to the equivalent resistor RWPG(between the word programming line420A and the gate of the anti-fuse structures S2A), the equivalent resistor RBL(between the source terminal of the read transistor T2A and the sense amplifier SA), and the residual resistor R21of the anti-fuse structures S2A. The sensitivity and the reliability for the sense amplifier SA to discriminate between the HIGH resistive value and the LOW resistive value of the residual resistor R21depends upon the resistive value of the equivalent resistor RWPGand the resistive value of the equivalent resistor RBL. Lowering the resistive value of the equivalent resistor RWPGand/or the resistive value of the equivalent resistor RBLimproves the sensitivity and the reliability of the sense amplifier SA for determining a discrete value of the residual resistor R21.

While increasing the number of programming conducting lines in the group392A reduces the resistive value of the equivalent resistor RWPG, increasing the number of programming conducting lines in some circumstances may also increase the size of the one-bit memory cell B21in certain circumstances. In some embodiments (such as the embodiments inFIGS.10A-10B,FIGS.11A-11B, andFIGS.12A-12B), multiple programming conducting lines are implemented for each one-bit memory cell to connect the gate of an anti-fuse structure (e.g., S2A) to a word programming line (e.g.,420A) while the size of the one-bit memory cell is not significantly increased.

FIG.10Ais a partial layout diagram of a part of a memory circuit having programming conducting lines, bit connectors, and via connectors positioned along with active zones, in accordance with some embodiments. The layout designs of various elements inFIG.10Aare identical to the layout designs of the corresponding elements inFIG.3. For example, both the programming gate-strip220A and read gate-strips240A extends in the Y-direction and intersect each of the active zones251and252. Each of the terminal conductors261and262extending in the Y-direction correspondingly intersects one of the active zones251and252. Each of the bit connectors361and362is conductively connected to one of the corresponding terminal conductors261and262through a terminal via-connector VD. Each of the programming conducting lines in group391A overlaps with the active zone251and is conductively connected to the programming gate-strip220A through the gate via-connector VG. Each of the programming conducting lines in group391B overlaps with the active zone251and is conductively connected to the programming gate-strip220B through the gate via-connector VG. Each of the programming conducting lines in group392A overlaps with the active zone252and is conductively connected to the programming gate-strip220A through the gate via-connector VG. Each of the programming conducting lines in group392B overlaps with the active zone252and is conductively connected to the programming gate-strip220B through the gate via-connector VG. InFIG.10A, each group of programming conducting lines includes three programming conducting lines. For example, the group392A includes programming conducting lines392A[1],392A[2], and392A[3].

In some embodiments, the width of the active zones251and252as designed is larger than the total width of three or more programming conducting lines if each of the programming conducting line is implemented with a minimal width based on design rule requirements. For example, in some embodiments, the width of the active zones251and252are optimized based upon performance requirements, such as, speeds and power consumptions. If the outer edge-to-edge distance of each group of programming conducting lines is less than the width of the active zones, the size of the one-bit memory cell is not impacted by the multiple programming conducting lines in the group. For example, inFIG.10A, if the distance WC between392A[1] and392A[3] measured from outer edge to outer edge is not larger than the width WA of the active zone252, the mere implementation of three programming conducting lines in the group392A does not increase the size of the one-bit memory cell (which is B21inFIG.8A). In some circumstances, even if the distance WC between392A[1] and392A[3] is larger than the width WA of the active zone252, some embodiments of the programming conducting lines are considered to be acceptable in terms of the impacts to the size of the one-bit memory cell. In some embodiments, even if the distance WC is larger than the width WA, each of the programming conducting lines in the group392A still overlaps with the active zone252. In some embodiments, even if the distance WC is larger than the width WA, each of the gate via-connector VG for connecting the programming gate-strip220A with one of the programming conducting lines in the group392A is still within the active zone252.

While each of the programming conducting lines inFIG.10Ais connected to a programming gate-strip through a corresponding gate via-connector VG, the connection between each group of programming conducting lines and the programming gate-strip, in alternative embodiments, may include at least one extended via-connector.FIG.10Bis a partial layout diagram of a part of a memory circuit having extended via-connectors, based on a modification of the partial layout diagram inFIG.10A, in accordance with some embodiments. The layout designs inFIG.10Bare similar to that inFIG.10A, except that the multiple gate via-connectors VG for connecting each group of programming conducting lines to a programming gate-strip are substituted with one extended via-connector. The extended via-connectors1051A and1052A correspondingly connect the programming conducting lines in the group391A and the group392A to the programming gate-strip220A. The extended via-connectors1051B and1052B correspondingly connect the programming conducting lines in the group391B and the group392B to the programming gate-strip220B. In some embodiments, the length of an extended via-connector along the Y-direction is selected to be sufficiently large to connect all programming conducting lines in one group for a one-bit memory cell to a programming gate-strip. For example, the length of the extended via-connector1052A is designed to connect all programming conducting lines392A[1],392A[2], and392A[3] in the group392A to the programming gate-strip220A. In some embodiments, the width of an extended via-connector along the X-direction is selected to be maximized without violations of the design rules.

In contrast to the embodiments inFIG.10Ain which multiple programming conducting lines are used for connecting a programming gate-strip to a word programming line (e.g.,420A inFIG.6A), in alternative embodiments, a merged programming conducting line is used for connecting a programming gate-strip to a word programming line.FIG.10Cis a partial layout diagram of a part of a memory circuit having merged programming conducting lines, based on a modification of the partial layout diagram inFIG.10A, in accordance with some embodiments. The layout designs inFIG.10Care similar to that inFIG.10A, except that each group of programming conducting lines inFIG.10Ais substituted with a merged programming conducting line. Each of the merged programming conducting lines1091A,1092A,1091B, and1092B inFIG.10Ccorrespondingly replaces one of the groups391A,392A,391B,392B of programming conducting lines inFIG.10A. In some embodiments, the width WM of a merged programming conducting line is less than or equal to the width WA of the active zone. In some embodiments, while the width WM of a merged programming conducting line is larger than the width WA of the active zone, the width WM of a merged programming conducting line is selected to be maximized within the limit constrained by the design rules. If two merged programming conducting lines are adjacent to each other and the width WM of each of the two merged programming conducting lines is too large, then, in certain circumstances, the edge-to-edge distance between the two adjacent lines may violate the design rules. Consequently, the possible width WM of a merged programming conducting line has a maximum limit.

In still alternative embodiments, the layout designs ofFIG.10Dinclude both the extended via-connectors and the merged programming conducting lines.FIG.10Dis a partial layout diagram of a part of a memory circuit based on a modification of the partial layout diagram in FIG. having merged programming conducting lines, in accordance with some embodiments. InFIG.10D, each of the merged programming conducting lines1091A and1092A is correspondingly connected to the programming gate-strip220A though one of the extended via-connectors1051A and1052A. Each of the merged programming conducting lines1091B and1092B is correspondingly connected to the programming gate-strip220B though one of the extended via-connectors1051B and1052B.

In addition to reducing the resistive value of the equivalent resistor RWPGbetween a word programming line and the gate of an anti-fuse structure, reducing the equivalent resistor RBLbetween the source terminal of the read transistor and the sense amplifier may further improve the sensitivity and the reliability for the sense amplifier to determine a discrete value of the residual resistor in a one-bit memory cell. In some embodiments, each of the bit connectors in a memory device is conductively connected to one corresponding terminal conductor through multiple terminal via-connectors VD. In some embodiments, each of the bit connectors in a memory device is conductively connected to one corresponding terminal conductor through an extended terminal via-connector.

FIGS.11A-11Dare partial layout diagrams based on modifications of the partial layout diagram inFIGS.10A-10D, in accordance with some embodiments. Each of the partial layout diagrams inFIGS.11A-11Dspecifies a part of a memory circuit having multiple terminal via-connectors between each bit connector and a corresponding terminal conductor. The layout designs in each ofFIGS.11A-11Dare correspondingly similar to that inFIGS.10A-10D, except that each terminal via-connector inFIGS.10A-10Dis substituted with multiple terminal via-connectors VD. In some embodiments, the number of the terminal via-connectors VD between each bit connector and the corresponding terminal conductor is maximized within the limit constrained by the design rules.

FIGS.12A-12Dare partial layout diagrams based on modifications of the partial layout diagram inFIGS.10A-10D, in accordance with some embodiments. Each of the partial layout diagrams inFIGS.12A-12Dspecifies a part of a memory circuit having an extended terminal via-connector between each bit connector and a corresponding terminal conductor. The layout designs inFIGS.12A-12Dare correspondingly similar to that inFIGS.10A-10D, except that each terminal via-connector inFIGS.10A-10Dis substituted with an extended terminal via-connector. The extended terminal via-connector1261inFIGS.12A-12Dreplaces the terminal via-connector VD between the bit connector361and the terminal conductor261inFIGS.10A-10D. The extended terminal via-connector1262inFIGS.12A-12Dreplaces the terminal via-connector VD between the bit connector362and the terminal conductor262inFIGS.10A-10D. An extended terminal via-connectors has an aspect ratio that is the ratio between the length of the extended terminal via-connector extending in the Y-direction and the width of the extended terminal via-connector extending in the X-direction. Generally, the aspect ratio of each of the extended terminal via-connectors1261and1262is larger than or equal to 2.0. In some embodiments, the aspect ratio of each of the extended terminal via-connectors1261and1262is maximized to the extent permitted by the design rules. In some embodiments, the length of each extended terminal via-connector (1261or1262) is larger than or equal to the width WA of the corresponding active zone (251or252). In some embodiments, the length of each extended terminal via-connector (1261or1262) is larger than or equal to the width WA but smaller than the length of the terminal conductor (261or262) extending in the Y-direction.

InFIGS.10A-10D,11A-11D, and12A-12D, the layout designs are modified for at least some of the programming conducting lines, the gate via-connectors, the terminal via-connectors in the partial layout diagrams ofFIG.5AorFIG.7A. In alternative embodiments, layout modifications of other elements are possible. For example, in some embodiments, the layout designs of the read conducting lines are modified.FIG.13is a partial layout diagram based on a modification of the partial layout diagram inFIG.5A, in accordance with some embodiments. The layout designs inFIG.13are similar to that inFIG.5A, except that the positions of the read conducting lines are shifted along the Y-direction. The read conducting line334inFIG.5Ais substituted with the read conducting line323A inFIG.13. The read conducting line323inFIG.5A(orFIG.7A) is substituted with the read conducting line334B inFIG.13.

FIG.14is a block diagram of an electronic design automation (EDA) system1400in accordance with some embodiments.

In some embodiments, EDA system1400includes an APR system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system1400, in accordance with some embodiments.

In some embodiments, EDA system1400is a general purpose computing device including a hardware processor1402and a non-transitory, computer-readable storage medium1404. Storage medium1404, amongst other things, is encoded with, i.e., stores, computer program code1406, i.e., a set of executable instructions. Execution of instructions1406by hardware processor1402represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods).

Processor1402is electrically coupled to computer-readable storage medium1404via a bus1408. Processor1402is also electrically coupled to an I/O interface1410by bus1408. A network interface1412is also electrically connected to processor1402via bus1408. Network interface1412is connected to a network1414, so that processor1402and computer-readable storage medium1404are capable of connecting to external elements via network1414. Processor1402is configured to execute computer program code1406encoded in computer-readable storage medium1404in order to cause system1400to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor1402is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium1404is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium1404includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium1404includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).

In one or more embodiments, storage medium1404stores computer program code1406configured to cause system1400(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1404also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1404stores library1407of standard cells including such standard cells as disclosed herein. In one or more embodiments, storage medium1404stores one or more layout diagrams1409corresponding to one or more layouts disclosed herein.

EDA system1400includes I/O interface1410. I/O interface1410is coupled to external circuitry. In one or more embodiments, I/O interface1410includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor1402.

EDA system1400also includes network interface1412coupled to processor1402. Network interface1412allows system1400to communicate with network1414, to which one or more other computer systems are connected. Network interface1412includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems1400.

System1400is configured to receive information through I/O interface1410. The information received through I/O interface1410includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor1402. The information is transferred to processor1402via bus1408. EDA system1400is configured to receive information related to a UI through I/O interface1410. The information is stored in computer-readable medium1404as user interface (UI)1442.

In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system1400. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.

In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.

FIG.15is a block diagram of an integrated circuit (IC) manufacturing system1500, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system1500.

InFIG.15, IC manufacturing system1500includes entities, such as a design house1520, a mask house1530, and an IC manufacturer/fabricator (“fab”)1550, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1560. The entities in system1500are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1520, mask house1530, and IC fab1550is owned by a single larger company. In some embodiments, two or more of design house1520, mask house1530, and IC fab1550coexist in a common facility and use common resources.

Design house (or design team)1520generates an IC design layout diagram1522. IC design layout diagram1522includes various geometrical patterns designed for an IC device1560. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1560to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1522includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1520implements a proper design procedure to form IC design layout diagram1522. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1522is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1522can be expressed in a GDSII file format or DFII file format.

Mask house1530includes data preparation1532and mask fabrication1544. Mask house1530uses IC design layout diagram1522to manufacture one or more masks1545to be used for fabricating the various layers of IC device1560according to IC design layout diagram1522. Mask house1530performs mask data preparation1532, where IC design layout diagram1522is translated into a representative data file (“RDF”). Mask data preparation1532provides the RDF to mask fabrication1544. Mask fabrication1544includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1545or a semiconductor wafer1553. The design layout diagram1522is manipulated by mask data preparation1532to comply with particular characteristics of the mask writer and/or requirements of IC fab1550. InFIG.15, mask data preparation1532and mask fabrication1544are illustrated as separate elements. In some embodiments, mask data preparation1532and mask fabrication1544can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation1532includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram1522. In some embodiments, mask data preparation1532includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation1532includes a mask rule checker (MRC) that checks the IC design layout diagram1522that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1522to compensate for limitations during mask fabrication1544, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation1532includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1550to fabricate IC device1560. LPC simulates this processing based on IC design layout diagram1522to create a simulated manufactured device, such as IC device1560. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1522.

It should be understood that the above description of mask data preparation1532has been simplified for the purposes of clarity. In some embodiments, data preparation1532includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1522according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1522during data preparation1532may be executed in a variety of different orders.

After mask data preparation1532and during mask fabrication1544, a mask1545or a group of masks1545are fabricated based on the modified IC design layout diagram1522. In some embodiments, mask fabrication1544includes performing one or more lithographic exposures based on IC design layout diagram1522. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1545based on the modified IC design layout diagram1522. Mask1545can be formed in various technologies. In some embodiments, mask1545is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1545includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask1545is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1545, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1544is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1553, in an etching process to form various etching regions in semiconductor wafer1553, and/or in other suitable processes.

IC fab1550is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1550is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

IC fab1550includes fabrication tools1552configured to execute various manufacturing operations on semiconductor wafer1553such that IC device1560is fabricated in accordance with the mask(s), e.g., mask1545. In various embodiments, fabrication tools1552include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

IC fab1550uses mask(s)1545fabricated by mask house1530to fabricate IC device1560. Thus, IC fab1550at least indirectly uses IC design layout diagram1522to fabricate IC device1560. In some embodiments, semiconductor wafer1553is fabricated by IC fab1550using mask(s)1545to form IC device1560. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram1522. Semiconductor wafer1553includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer1553further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g., system1500ofFIG.15), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference.

An aspect of the present disclosure relates to a memory device. The memory device includes a first programming gate-strip and a second programming gate-strip both extending in a second direction perpendicular to a first direction, a first anti-fuse structure having a first dielectric layer overlying a first semiconductor region in an active zone at an intersection of the first programming gate-strip and the active zone extending in the first direction, and a second anti-fuse structure having a second dielectric layer overlying a second semiconductor region in the active zone at an intersection of the second programming gate-strip and the active zone. The memory device also includes a first transistor having a first channel region in the active zone, a second transistor having a second channel region in the active zone, and a terminal conductor overlying a terminal region in the active zone between the first channel region of the first transistor and the second channel region of the second transistor. The memory device further includes a group of first programming conducting lines extending in the first direction, and a group of second programming conducting lines extending in the first direction. The first programming conducting lines are conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors. The second programming conducting lines are conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors.

Another aspect of the present disclosure also relates to a memory device. The memory device includes a first programming gate-strip and a second programming gate-strip both extending in a second direction perpendicular to a first direction, and includes also a first read gate-strip and a second read gate-strip, both extending in the second direction, positioned between the first programming gate-strip and the second programming gate-strip. The memory device further includes a first anti-fuse structure, a first transistor, a second anti-fuse structure, a second transistor, a terminal conductor, a group of first programming conducting lines, a group of second programming conducting lines, and a bit connector. The first anti-fuse structure has a first dielectric layer overlying a first semiconductor region in an active zone at an intersection of the first programming gate-strip and the active zone extending in the first direction. The first transistor has a first channel region in the active zone at an intersection of the first read gate-strip and the active zone. The second anti-fuse structure has a second dielectric layer overlying a second semiconductor region in the active zone at an intersection of the second programming gate-strip and the active zone. The second transistor has a second channel region in the active zone at an intersection of the second read gate-strip and the active zone. The terminal conductor overlies a terminal region in the active zone between the first channel region of the first transistor and the second channel region of the second transistor. The group of first programming conducting lines, extending in the first direction, is conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors. The group of second programming conducting lines, extending in the first direction, is conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors. The bit connector is conductively connected to the terminal conductor through one or more terminal via-connectors.

Another aspect of the present disclosure still relates to a memory device. The memory device includes a first programming gate-strip and a second programming gate-strip both extending in a second direction perpendicular to a first direction, and the memory device includes a first read gate-strip and a second read gate-strip, both extending in the second direction, positioned between the first programming gate-strip and the second programming gate-strip. The memory device also includes a first anti-fuse structure having a first dielectric layer overlying a first semiconductor region in an active zone at an intersection of the first programming gate-strip and the active zone extending in the first direction, and a second anti-fuse structure having a second dielectric layer overlying a second semiconductor region in the active zone at an intersection of the second programming gate-strip and the active zone. The memory device further includes a first transistor having a first channel region in the active zone at an intersection of the first read gate-strip and the active zone, a second transistor having a second channel region in the active zone at an intersection of the second read gate-strip and the active zone, and a terminal conductor overlying a terminal region in the active zone between the first channel region of the first transistor and the second channel region of the second transistor. The memory device further includes a group of first programming conducting lines extending in the first direction, a group of second programming conducting lines, extending in the first direction, a first word programming line, extending in the second direction, and a second word programming line, extending in the second direction. The first programming conducting lines are conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors. The second programming conducting lines are conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors. The first word programming line is conductively connected to the group of first programming conducting lines. The second word programming line is conductively connected to the group of second programming conducting lines.

It will be readily seen by one of ordinary skill in the art that one or more of the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.