Patent ID: 12210189

DETAILED DESCRIPTION

A photonic integrated circuit (PIC) device is formed by stamping photonic elements into a nanoimprint functional resist disposed on a substrate (e.g., wafer, film, plate). The resultant PIC device with photonic elements stamped into a nanoimprint functional resist encapsulates a plurality of optical elements (e.g., waveguides, tapers, transitions, couplers, filters) having both larger features (e.g., centimeters, millimeters) and smaller features (e.g., microns, nanometers) in a three-dimensional arrangement (e.g., multiple heights lengths and widths). The optical elements can be linear, tortuous, and/or dendritic with tailored transitions among the various length scales. The substrate can be formed of a material (e.g., glass) that has a lower refractive index (e.g., 2% to 50% lower) than the nanoimprint resist. The nanoimprint resist can be a sol-gel resist such as silica, titanium oxide (TiO2), or a loaded sol-gel such as titanium oxide particles or semiconductor particles embedded in a nanoimprint resist (e.g., Amonil UV nanoimprint resist, titanium oxide resist). The nanoimprint resist has a relatively high refractive index (e.g., greater than 1.7 and less than 4.0) with a low optical loss.

A fabrication methodology of forming a silicon ‘master’ photonic circuit can be employed using traditional techniques to generate a master stamp that is an inverted version of the master photonic circuit. The photonic circuit is then reproduced by placement of the master stamp in a high-index nanoimprint functional resist. This single-step imprint technique allows the fabrication of photonic integrated circuits with reduced cost and improved reproducibility. By using nanoimprint functional resists fabricated of IR transparent materials, it is possible to use this technique for mid-wave infrared (MWIR) PICs. The nanoimprinted resist can be self-curing or formed of a photo-curable or thermally-curable resist.

Traditional techniques require multiple expensive tools for fabricating large and small scale devices into a single PIC. Traditional techniques also require using different layers and calibration of etches of these layers for multiple chips. Calibration over many devices is very difficult and may result in the scrapping or degradation of many PICs over a fabrication lot. A single master stamp allows for the repeatability of similar quality PICs over a fabrication lot with the formation of both large features and small features of multiple dimensions in a single process. The master stamp can be replicated and distributed to simpler facilities that can stamp wafers under ambient conditions without the expensive equipment found in a high performance semiconductor foundry.

Stamps can be made from hard (e.g., semiconductor, metal, or glass) or soft materials (e.g., elastomeric). In one example, a single nanoimprint stamp encompasses nanopatterns to pattern features that form each of the plurality of optical elements. In another example, the single nanoimprint stamp is an elastomeric stamp. The elastomeric stamp can be made by a trilayer of materials with a high Young's modulus (E=10-100 MPa) top polymer layer that encompasses the plurality of optical elements (nanopatterns), followed by a lower Young's modulus (E=2-10 MPa) intermediate polymer layer disposed on a glass plate. For example, the nanoimprint stamp can be a specially prepared tri-layer system comprised of a hard polydimethylsiloxane (PDMS) layer which holds the nanopatterns, a soft PDMS layer to enable conformality to the imprint substrate, and a flexible glass backing layer to both facilitate handling and ensure long-range dimensional stability. Stamp lifetimes can be on the order of 700-1000 wafers prior to replacement and can be produced inexpensively since an original master wafer can be reused without degradation.

The nanoimprint resist in this approach serves as a functional optical component of the final photonic circuit rather than a sacrificial masking layer as in traditional lithographies. The process also allows the transfer of structures across a wide range of length scales and dimensions into the resist, enabling structures where both nano-, micro-, and macro-scale features are simultaneously replicated. The nanoimprinted photonic base layer is compatible with standard fabrication processes. It can stand alone or be planarized and overlaid with other electrical and/or electro-optical layers.

FIG.1illustrates an example of a PIC device10having nanofeatures that form a plurality of optical elements formed in a single nanoimprint resist structure14. The plurality of optical elements can form optical devices such as waveguides, splitters, combiners, bragg reflectors, lenses and other optical devices. The single nanoimprint resist structure14is disposed on a substrate12(e.g., wafer, film, plate). The substrate12can be formed of a material (e.g., glass, quartz, silicon, sapphire) having a refractive index (e.g., less than or equal to about 1.5) that is lower than the refractive index of the nanoimprint resist structure14(e.g., from about 1.7 to about 4.0). The single nanoimprint resist structure14can be a sol-gel resist such as silica, titanium oxide (TiO2), or a loaded sol-gel such as titanium oxide particles or semiconductor particles embedded in a nanoimprint resist (e.g., Amonil UV nanoimprint resist). The single nanoimprint resist structure14has a relatively high refractive index with a low optical loss. The nanoimprinted resist can be self-curing or formed of a photo-curable or thermally-curable resist.

The plurality of optical elements are formed from nanofeatures embedded into the nanoimprint resist structure14. The nanofeatures are a result of a stamping process employing a stamp that includes nanopatterns that are inverted versions of the nanofeatures. The features can include large scale or micro-scale features (e.g., millimeters or micrometers)18and24and small scale or nano-scale features20and22(e.g., nanometers). As illustrated inFIG.1, nano-scale features20have varying heights that are different than nano-scale features22and micro-scale features18and24. Therefore, the nanopatterns can provide for a three-dimensional arrangement of nanofeatures of varying widths, lengths and heights. This three-dimensional arrangement is provided in a single stamping process as opposed to multiple lithography processes of different layers required in the fabrication of conventional PIC devices. An encapsulation layer16overlies the nanofeatures of the nanoimprint resist structure14. The encapsulation layer16can be a lower-index sol-gel layer to provide both mechanical or environmental protection and planarization for subsequent device layers.

Nanoimprint lithography can be performed with either a hard (semiconductor, metal, or glass) stamp or a soft polymeric stamp. While hard stamps have been used to demonstrate the highest resolution patterning, they are accompanied by significant disadvantages: challenging removal from the imprinted substrate, fragility during handling, susceptibility to irreversible damage from dust contamination, processing at elevated temperatures and/or pressures, and difficulties in scaling due to the requirement of highly planar substrates.

Soft stamps address these challenges presented by hard stamps, while supporting sub-30 nm resolutions exceeding the requirements of even visible-light PICs. Soft stamps support room temperature application and curing which can be accelerated using flood UV illumination. The polymeric stamp material also supports sufficient out-of-plane deformation to bend over dust contamination, significantly improving stamp lifetime by reducing degradation as a function of number of imprints performed. These stamps also resist damage from handling, and can be reproduced inexpensively.

FIG.2illustrates an example of a master pattern stamp40having a plurality of nanopatterns. The plurality of nanopatterns are inverted versions of nanofeatures to be stamped into a nanoimprint functional resist to form a plurality of optical elements from the nanofeatures. In one example, the single nanoimprint stamp40is an elastomeric stamp. The elastomeric stamp includes soft or low modulus polymer layer44overlying a substrate layer42and a hard or high modulus polymer layer46overlying the low modulus polymer layer44. The substrate layer42can be a flexible glass backing layer to both facilitate handling and ensure long-range dimensional stability. The low modulus polymer layer44can be a soft PDMS layer to enable conformality to the imprint substrate. The high modulus layer46can be a hard PDMS layer that holds the nanopatterns and overlies the soft PDMS layer44. Stamp lifetimes can be on the order of 700-1000 imprints prior to replacement and can be produced inexpensively since an original master wafer can be reused without degradation to form a number of stamps.

The patterns can include large scale or micro-scale patterns (e.g., centimeters, millimeters)48and54and small scale or nano-scale patterns50and52(e.g., nanometers) to form large scale or micro-scale features (e.g., centimeters, millimeters) and small scale or nano-scale features (e.g., nanometers) in a stamped nanoimprint resist structure. As illustrated inFIG.2, nanopatterns52have varying heights that are different than nano-scale patterns50and micro-scale patterns48and54to provide features of varying heights, lengths and widths on the stamped nanoimprint resist structure.

Turning now toFIGS.3-5, fabrication is discussed in connection with formation of the PIC device10ofFIG.1.FIG.3illustrates a cross-sectional view of a PIC device in its early stages of fabrication. A nanoimprint resist material layer64overlies a substrate62. The nanoimprint resist material layer64may be formed over the substrate62via spin-coating or spin casting deposition techniques similar to a photoresist material resist deposition process. However, the nanoimprint resist material layer64is a high-index functional nanoimprint resist applied as a liquid that when stamped and cured can provide functional optical elements. The nanoimprint resist material layer64can have a thickness of about 100 nm to about 250 nm. The substrate62can be formed of a material (e.g., glass) that has a lower refractive index (e.g., 2% to 50% lower) than the nanoimprint resist material layer62. The nanoimprint resist material layer62can be a sol-gel resist such as silica, titanium oxide (TiO2), or a loaded sol-gel such as titanium oxide particles or semiconductor particles embedded in a nanoimprint resist material (e.g., Amonil UV nanoimprint resist, titanium oxide resist). The nanoimprint resist material layer has a relatively high refractive index (e.g., greater than 1.7 and less than 4.0) with a low optical loss.

FIG.4illustrates a cross-sectional view of the stamp40ofFIG.2disposed on the nanoimprint resist material layer64ofFIG.3. After the stamp40is disposed on the nanoimprint resist material layer64, pressure is placed on the back of the stamp40to submerge the pattern of the stamp40into the nanoimprint resist material layer64. The liquid nanoimprint resist material pulls the stamp down by capillary forces causing the liquid nanoimprint resist material to flow (e.g., about 5-10 microns) filling the openings in the pattern of the stamp40. The nanoimprint resist material layer64can cure at room temperature. Alternatively, the nanoimprint resist material layer64can be cured faster by subjecting the nanoimprint resist material layer64to elevated temperatures. Furthermore, the nanoimprint resist material layer64can be photocured by subjecting the nanoimprint resist material layer64to ultra-violet (UV) light through the stamp40. The nanoimprint resist material layer64can take anywhere from about 20 seconds to about 20 minutes to cure based on the selected process.

Once the nanoimprint resist material layer64is cured, the stamp can be removed to provide the resultant structure ofFIG.5. The stamp40is self-cleaning such that the solvent from the nanoimprint resist evaporated into the air and not into the stamp40. The resultant structure ofFIG.5provides a plurality of optical elements formed from nanofeatures embedded into the nanoimprint resist structure64. The nanofeatures include large scale or micro-scale features (e.g., centimeters, millimeters or micrometers)72and78and small scale or nano-scale features74and76(e.g., nanometers). The nano-scale features74have varying heights that are different than nano-scale features76and micro-scale features72and78. Therefore, the nanopatterns can provide for a three-dimensional arrangement of nanofeatures of varying widths, lengths and heights. The nanoimprinted resist structure can be formed of a photo-curable or thermally-curable resist. A resultant resist top layer80resides over the substrate around the nanopatterns as a result of the stamping process that can be removed or utilized for other features and/or connections.

After imprinting, the functional resist layer can be either used as-is or modified through postprocessing. Processes known to improve either mechanical or optical properties include calcination, vacuum annealing, or atomic layer deposition. Postprocessing can also include superstrate deposition or encapsulation with a lower-index sol-gel layer to both provide mechanical or environmental protection and planarization for subsequent device layers to provide a structure similar to the structure illustrated inFIG.1. Integration can be accomplished using established techniques for patterning and connecting readout integrated circuitry (ROIC), detectors, and other required components.

What have been described above are examples of the invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the invention are possible. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims.