Patent ID: 12230595

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

An integrated circuit structure and the method of forming the same are provided in accordance with some embodiments. The intermediate stages in the formation of the integrated circuit structure are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In accordance with some embodiments of the present disclosure, a metal bump, which includes a via portion and an overlying bump portion, is formed. The via portion extends into a polymer layer to connect to an underlying conductive feature such as a metal pad. The profile including the width, the height, the tilt angle, and the R-angle of via portion is adjusted in order to reduce the stress applied on the underlying low-k dielectric layers. The material of the polymer layer is also adjusted to achieve the desirable profile of the via portion.

FIGS.1through10illustrate the cross-sectional views of intermediate stages in the formation of an integrated circuit structure including the metal bump in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow200as shown inFIG.19.

FIG.1illustrates a cross-sectional view of package component20. In accordance with some embodiments of the present disclosure, package component20is a device wafer including active devices and possibly passive devices, which are represented as integrated circuit devices26. Device wafer20may include a plurality of chips22therein, with one of chips22illustrated schematically. In accordance with alternative embodiments of the present disclosure, package component20is an interposer wafer, which does not include active devices, and may or may not include passive devices such as inductors, resistors, capacitors, etc. In accordance with yet alternative embodiments of the present disclosure, package component20is a package substrate strip, which includes core-less package substrates or the package substrates with cores therein. In subsequent discussion, a device wafer is discussed as an example of package component20. The embodiments of the present disclosure may also be applied on interposer wafers, package substrates, packages, etc.

In accordance with some embodiments of the present disclosure, wafer20includes semiconductor substrate24and the features formed at a top surface of semiconductor substrate24. Semiconductor substrate24may be formed of crystalline silicon, crystalline germanium, silicon germanium, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. Semiconductor substrate24may also be a bulk semiconductor substrate or a Semiconductor-On-Insulator (SOI) substrate. Shallow Trench Isolation (STI) regions (not shown) may be formed in semiconductor substrate24to isolate the active regions in semiconductor substrate24. Although not shown, through-vias may be formed to extend into semiconductor substrate24, wherein the through-vias are used to electrically inter-couple the features on the opposite sides of wafer20.

In accordance with some embodiments of the present disclosure, wafer20includes integrated circuit devices26, which are formed on the top surface of semiconductor substrate24. Integrated circuit devices26may include Complementary Metal-Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, and the like in accordance with some embodiments. The details of integrated circuit devices26are not illustrated herein. In accordance with alternative embodiments, wafer20is used for forming interposers, and substrate24may be a semiconductor substrate or a dielectric substrate.

Inter-Layer Dielectric (ILD)28is formed over semiconductor substrate24and fills the space between the gate stacks of transistors (not shown) in integrated circuit devices26. In accordance with some embodiments of the present disclosure, ILD28is formed of Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-doped Phospho Silicate Glass (BPSG), Fluorine-doped Silicate Glass (FSG), Tetra Ethyl Ortho Silicate (TEOS), or the like. ILD28may be formed using spin coating, Flowable Chemical Vapor Deposition (FCVD), or the like. In accordance with some embodiments of the present disclosure, ILD28is formed using a deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), or the like.

Contact plugs30are formed in ILD28, and are used to electrically connect integrated circuit devices26to overlying metal lines and vias. In accordance with some embodiments of the present disclosure, contact plugs30are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multi-layers thereof. The formation of contact plugs30may include forming contact openings in ILD28, filling a conductive material(s) into the contact openings, and performing a planarization process (such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process) to level the top surfaces of contact plugs30with the top surface of ILD28.

Over ILD28and contact plugs30may reside interconnect structure32. Interconnect structure32includes metal lines34and vias36, which are formed in dielectric layers38(also referred to as Inter-metal Dielectrics (IMDs)). The metal lines at a same level are collectively referred to as a metal layer hereinafter. In accordance with some embodiments of the present disclosure, interconnect structure32includes a plurality of metal layers including metal lines34that are interconnected through vias36. Metal lines34and vias36may be formed of copper or copper alloys, and they can also be formed of other metals. In accordance with some embodiments of the present disclosure, dielectric layers38are formed of low-k dielectric materials. The dielectric constants (k values) of the low-k dielectric materials may be lower than about 3.0, for example. Dielectric layers38may be formed a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In accordance with some embodiments of the present disclosure, the formation of dielectric layers38includes depositing a porogen-containing dielectric material and then performing a curing process to drive out the porogen, and hence the remaining dielectric layers38are porous.

The formation processes of metal lines34, vias36, and dielectric layers38may include single damascene processes and/or dual damascene processes. In a single damascene process, a trench is first formed in one of dielectric layers38, followed by filling the trench with a conductive material. A planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process is then performed to remove the excess portions of the conductive material higher than the top surface of the respective IMD layer, leaving a metal line in the trench. In a dual damascene process, both a trench and a via opening are formed in an IMD layer, with the via opening underlying and connected to the trench. The conductive material is then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

Wafer20further includes top conductive (metal) features such as metal lines, metal pads, or vias (denoted as37) in a top dielectric layer39. In accordance with some embodiments of the present disclosure, dielectric layer39is formed of a low-k dielectric material similar to the material of lower ones of dielectric layers38. In accordance with other embodiments, dielectric layer39is formed of a non-low-k dielectric material, which may include silicon nitride, Undoped Silicate Glass (USG), silicon oxide, or the like. Dielectric layer39may also have a multi-layer structure including, for example, two USG layers and a silicon nitride layer in between. Dielectric layer39is sometimes referred to as a passivation layer. Top metal features37may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

Metal pad42is formed over and contacting metal feature37. The respective process is illustrated as process202in the process flow200as shown inFIG.19. The illustrated metal pad42represents a plurality of metal pads at the same level. Metal pad42may be electrically coupled to integrated circuit devices26through conductive features such as metal lines34and vias36. In accordance with some embodiments of the present disclosure, metal pad42is an aluminum pad or an aluminum-copper pad, and other metallic materials may be used. In accordance with some embodiments of the present disclosure, metal pad42has an aluminum percentage greater than about 95 percent.

A patterned passivation layer44is formed on metal pad42. The respective process is illustrated as process204in the process flow200as shown inFIG.19. Some portions of passivation layer44may cover the edge portions of metal pad42, and the central portion of the top surface of metal pad42is exposed through opening46. In accordance with some embodiments of the present disclosure, opening46is formed by etching passivation layer44in an etching process. Passivation layer44may be a single layer or a composite layer, and may be formed of a non-porous material. In accordance with some embodiments of the present disclosure, passivation layer44is a composite layer including a silicon oxide layer and a silicon nitride layer over the silicon oxide layer.

FIG.2illustrates the application of dielectric layer48. The respective process is illustrated as process206in the process flow200as shown inFIG.19. In accordance with some embodiments of the present disclosure, dielectric layer48is formed of polymer diluted in a solvent. The formation of dielectric layer48may include spin-coating polymer layer48and pre-baking polymer layer48, so that it may maintain its shape in the subsequent light-exposure process and development process. In accordance with some embodiments of the present disclosure, the pre-baking is performed at a temperature in the range between about 100 degrees and about 180 degrees. The pre-baking duration may be in the range between about 2 minutes and about 10 minutes.

In accordance with some embodiments of the present disclosure, N-Methyl-2-pyrrolidone (NMP), which was conventional used as the solvent, is replaced by aliphatic amide, so that the desirable profile (FIGS.3and11) may be generated when openings are formed in dielectric layer48. In accordance with some embodiments of the present disclosure, the coated dielectric layer48(when and after it is coated but before baking) is free from NMP. In accordance with alternative embodiments of the present disclosure, the coated dielectric layer48(when and after it is coated but before baking), is substantially free from NMP, for example, including NMP with a weight percentage smaller than about 0.3 percent, or smaller than about 0.1 percent. It is appreciated that some analyzing equipment for detecting the composition of the polymer may detect the concentration of some chemicals such as NMP with concentrations higher than certain value such as 0.3 percent, but does not have the accuracy of detecting the NMP having concentrations lower than about 0.3 percent.

In addition, to suit to the use of aliphatic amide as solvent, the coated polymer 48 may also include other additives such as alkoxy decane. Alkoxy decane is also a polymer. As a result, the resulting polymer may include silicon alkoxide (with the formula Si(OR)n), which may be detected using Fourier transform Infrared (FTIR) and Gas Chromatography Mass Spectrometry (GCMS). In accordance with some embodiments of the present disclosure, the alkoxy decane in the coated dielectric layer48has a weight percentage greater than about 0.1 percent (excluding the solvent). The weight percentage of silicon alkoxide is detectable, and may be in the range between about 0.1 percent and about 10 percent.

FIG.2also illustrates the light-exposure process of dielectric layer48, which is performed using lithography mask50. The respective process is illustrated as process208in the process flow200as shown inFIG.19. Lithography mask50includes opaque portions50A for blocking the light used in the light-exposure, and transparent portion50B allowing the light to pass through, so that selected portions of dielectric layer48are exposed.

After the light exposure, a development process is performed, so that opening52is formed in dielectric layer48, as shown inFIG.3. The respective process is also illustrated as process208in the process flow200as shown inFIG.19. The top surface of metal pad42is exposed to opening52.

After the development process, a main baking process, which is also a curing process, is performed to cure dielectric layer48. The respective process is illustrated as process210in the process flow200as shown inFIG.19. In accordance with some embodiments of the present disclosure, the main baking process is performed at a temperature in the range between about 200 degrees (° C.) and about 400 degrees. The main baking duration may be in the range between about 1 hour and about 12 hours. It is observed that the tilt angle θ (FIG.11) is related to the baking temperature, and higher temperature results in greater tilt angle θ, and vice versa. Accordingly, the baking temperature is adjusted in order to adjust tilt angle θ. For example, tilt angle θ may be in the range greater than about 45 degrees and lower than about 90 degrees, which may be achieved through a pre-baking temperature in the range between about 120 degrees and about 210 degrees. Tilt angle θ may also be in the range between about 70 degrees and about 80 degrees, which may be achieved through a pre-baking temperature in the range between about 140 degrees and about 160 degrees. In addition, the tilt angle θ may be increased by increasing the exposure focus of the tool for the light-exposure process of dielectric layer48in accordance with some embodiments. The desirable tilt angle θ may be achieved by adjusting the exposure focus to an appropriate value, which may be discovered through experiments.

During the baking process, dielectric layer48shrinks, and its thickness is reduced.FIG.11illustrates a magnified view of opening52, which is filled with via portion58A of metal bump58in a subsequent process. As shown inFIG.11, after the main baking process, dielectric layer48has a thickness H1, which is the thickness of a portion of dielectric layer48directly over metal pad42and passivation layer44. In accordance with some embodiments of the present disclosure, thickness H1is equal to or greater than about 5 μm, and may be in the range between about 5 μm and about 15 μm. As discussed in subsequent paragraphs, adjusting thickness H1to be equal to or greater than about 5 μm is critical in reducing the stress in low-k dielectric layers38to a level that no cracks are generated in low-k dielectric layers38(FIG.3). Via portion58A of metal bump58contacts metal pad42to form an interface, which has width W1. Width W1is also the bottom width of opening52as shown inFIG.3. In accordance with some embodiments of the present disclosure, width W1is equal to or smaller than about 20 μm, and may be in the range between about 8 μm and about 20 μm. As discussed in subsequent paragraphs, making width W1to be equal to or smaller than about 20 μm is critical in reducing the stress in low-k dielectric layers38to a level that no cracks are generated in low-k dielectric layers38.

In a cross-sectional view, as shown inFIG.11, dielectric layer48has straight sidewalls48A, and round sidewalls48B connected to straight sidewalls48A. The round sidewalls48B are also connected to the top surface42A of metal pad42, which top surface also forms the bottom surface of opening52inFIG.3. The round sidewalls48B form parts of circles that have an R-angle, which is the diameter R of the respective circles to which round sidewalls48B fit. In accordance with some embodiments of the present disclosure, the R-angle is smaller than about 4 μm. Furthermore, the R-angle is greater than 0 μm, and may be greater than about 1 μm. In accordance with some embodiments of the present disclosure, the R-angle is in the range between about 1 μm and about 3 μm. As will be discussed in subsequent paragraphs, making the R-angle to be equal to or smaller than about 4 μm is critical in reducing the stress in low-k dielectric layers38to a level that no cracks are generated in low-k dielectric layers38.

As shown inFIGS.3,4, and11, the top surface of passivation layer44includes a first portion (the illustrated lower portion or lower part, also referred to as a first top surface or a second top surface) that is located beyond an edge of the metal pad42, and a second portion (the illustrated higher portion or a higher part, also referred to as a second top surface or a first top surface) that overlaps metal pad42. The straight sidewalls48A may have a tilt angle θ, which is the sharp angle formed between straight sidewalls48A and a horizontal plane (which is parallel to a top surface and a bottom surface of package component22). In accordance with some embodiments of the present disclosure, tilt angle θ is in the range between about 45 degrees and about 90 degrees. As will be discussed in subsequent paragraphs, making the tilt angle θ to be in the range between about 45 degrees and about 90 degrees is critical in reducing the stress in low-k dielectric layers38to a level that no cracks are generated in low-k dielectric layers38.

In accordance with some embodiments, as shown inFIG.4, due to the adoption of solvent aliphatic amide and alkoxy decane, the top surface48C of dielectric layer48may rise in the region where the top surface of dielectric layer48joins sidewalls48A. In the regions farther away from opening52, the top surfaces48C of dielectric layer48are planar. In accordance with some embodiments of the present disclosure, the rising-up height H2(also referred to as crown height) is smaller than 1.5 μm, and may be in the range between about 0.5 μm and about 1.5 μm. The rising surface48C is illustrated using dashed lines. In accordance with some embodiments, a part (portion) of the top surface of passivation layer44overlapping metal pad42is flat. When top surface48C includes the rising-up portion (as shown inFIG.4), the rising-up portion, which overlaps the flat part of the top surface of the passivation layer44and overlaps metal pad42, is curved. Accordingly, the rising-up part is more curved than the flat part of the top surface of the passivation layer44. Furthermore, there are rising-up parts on opposite sides of the opening52and have same shape and a same rising-up height H2. The top surface of dielectric layer48also has the possibility of being planar in the region where the top surface of dielectric layer48joins sidewalls48A, as shown by solid lines inFIG.4(also shown inFIG.3). The rising-up of the top surface is not shown inFIGS.5through10, although the top surfaces in these figures may also rise.

FIGS.5through9illustrate the formation of a metal bump. In accordance with some embodiments of the present disclosure, the metal bump is formed to be in contact with metal pad42. In accordance with alternative embodiments of the present disclosure, additional conductive lines and possibly dielectric layers are formed over metal pad42and underlying the metal bump. For example, there may be Redistribution Lines (RDLs, sometimes referred to Post-Passivation Interconnects (PPIs)) and polymer layers formed, with the PPIs in the polymer layers interconnecting metal pad42to the overlying metal bump.

Referring toFIG.5, seed layer54is deposited over dielectric layer48. Seed layer54is a conductive seed layer, and may be a metal seed layer in accordance with some embodiments. The respective process is illustrated as process212in the process flow200as shown inFIG.19. In accordance with some embodiments of the present disclosure, seed layer54is a composite layer comprising two or more layers. For example, seed layer54may include a lower layer and an upper layer, wherein the lower layer may include a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, or the like. The materials of the upper layer may include copper or a copper alloy. In accordance with alternative embodiments, seed layer54is a single layer, which may be a copper layer, for example. Seed layer54may be formed using Physical Vapor Deposition (PVD), Plasma Enhanced CVD (PECVD), atomic layer deposition, etc., while other applicable methods may also be used. Seed layer54is a conformal layer that extends into opening52.

FIG.6illustrates the formation of a patterned plating mask56. The respective process is illustrated as process214in the process flow200as shown inFIG.19. In accordance with some embodiments of the present disclosure, plating mask56is formed of a photo resist. Plating mask56is patterned to form opening58, through which a portion of the seed layer54is exposed. The patterning of plating mask56may include a light-exposure process and a development process.

Next, referring toFIG.7, a plating process(es) is performed to form metal bump58. The respective process is illustrated as process216in the process flow200as shown inFIG.19. Metal bump58may include one or a plurality of non-solder metal layers. For example, metal bump58may include copper-containing layer60including copper or a copper alloy. Metal bump58may also include metal cap layer62over copper-containing layer60. Metal cap layer62may be a nickel-containing layer, a palladium-containing layer, a gold layer, and/or the like, or a composite layer comprising the aforementioned layers.

On top of metal bump58, solder region64is formed, for example, by plating. The respective process is also illustrated as process216in the process flow200as shown inFIG.19. Solder region64may be formed of a Sn—Ag alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free or lead-containing. In a subsequent process, plating mask56is removed in a stripping process, and the underlying portions of seed layer54are exposed. The respective process is illustrated as process218in the process flow200as shown inFIG.19. For example, when plating mask56is formed of a photo resist, plating mask56may be ashed using oxygen. Next, the exposed portions of seed layer54that were previously covered by plating mask56are removed through etching, for example, using sub-atmospheric-pressure pure hydrogen glow plasma to etch copper. The mixture of N2and H2or the mixture of Cl2and Ar may be used as the process gas. Titanium, if included in the seed layer, may be etched using a fluorine-containing gas such as SF6, or CF4, or NF3. The portions of seed layer54covered by metal bump58remain un-removed. The respective process is also illustrated as process218in the process flow200as shown inFIG.19. The resulting structure is shown inFIG.8. Throughout the description, the remaining portions of seed layer54are considered as being a part of the metal bump58. Metal bump58includes via portion58A extending into dielectric layer48, and bump portion58B higher than the top surface of dielectric layer48. The sidewalls of the bump portion58B of metal bump58may be substantially vertical and straight. The details of the profile of via portion58A may be found referring to the profile shown inFIG.11. For example, as shown in the magnifiedFIG.11, the corner formed between the sidewall of passivation layer44and the top surface of metal pad42is sharper than the rounded bottom corner of the via portion58A.

Referring toFIG.9, solder region64is reflowed in a reflow process, for example, in a convection reflow process, laser reflow process, or the like. The respective process is illustrated as process220in the process flow200as shown inFIG.19. Solder region64thus has a rounded surface.

FIG.12illustrates a top view of metal bump58. In accordance with some embodiments of the present disclosure, via portion58A and bump portion58B both have elongated shapes. In which case, the width W1(also refer toFIGS.4and11) is the smaller width (in the widthwise direction) of via portion58A. In accordance with alternative embodiments of the present disclosure, metal bump58may have a non-elongated top view shape without a significant difference between the longer axis and shorter axis. For example, the top-view shape may be a circular shape, and width W1is the diameter of the circular shape. The top-view shape via portion58A and bump portion58B of may also be hexagons, and width W1is the distance between two parallel edges of the corresponding hexagon. The shape of opening46(FIG.1) is also illustrated inFIG.12.

Referring back toFIG.9, wafer20is singulated in a die-saw process. The singulation is performed along scribe lines66. The respective process is illustrated as process222in the process flow200as shown inFIG.19. Package components22(which may be device dies, package substrate, interposers, packages, or the like) are thus separated from each other to form discrete package components.

Next, Referring toFIG.10, one of package components22is bonded to package component68, which may be an interposer, a package substrate, a package, a device die, a printed circuit board, or the like. The respective process is illustrated as process224in the process flow200as shown inFIG.19. The bonding may be through solder region65, which includes the material of solder region64(FIG.9). Solder region65may or may not include additional solder from the solder region pre-formed on conductive feature70in package component68. Underfill71may be disposed into the gap between package component22and package component68. Underfill71may be in contact with the top surface of dielectric layer48, and may contact the sidewalls of bump portion58B. Furthermore, Underfill71may encircle, and may be in contact with, metal bump58. Package72is thus formed.

It has been found that when the stresses in low-k dielectric layers38increase to about 150 MPa, low-k dielectric layers38may crack. When the stress in low-k dielectric layers38is lower than about 150 MPa, low-k dielectric layers38will not crack. Accordingly, a plurality of simulations have been performed to determine the effect of some factors on the stress in low-k dielectric layers38. The simulation results are illustrated inFIGS.13,14,15,16, and17.

FIG.13illustrates the simulation results, in which the stress in low-k dielectric layers38(FIG.10) is illustrated as a function of the width W1(FIG.11) of the via portion58A of the metal bump58. The X-axis represents the width W1, and the Y-axis represents the stress in low-k dielectric layers38.FIG.13reveals that with the increase in the width W1, the stress in low-k dielectric layers38increases. When the width W1reaches about 20 μm or greater, the stress increases to the critical value of 150 MPa or higher. This means that low-k dielectric layers38will not crack when width W1is smaller than 20 μm, and has the possibility of cracking when width W1is greater than about 20 μm. Accordingly, reducing the width W1results in the desirable reduction in the stress in low-k dielectric layers38, and the width W1is designed to be smaller than about 20 μm.

FIG.14illustrates the simulation results, wherein the normalized stress in low-k dielectric layers38(FIG.10) is illustrated as a function of the width W1(FIG.11) of the via portion58A. The X-axis represents the width W1, and the Y-axis represents the normalized stress in low-k dielectric layers38, with the normalized stress being a ratio of the stress in dielectric layers38to the critical value of 150 MPa. Similar toFIG.13,FIG.14reveals that with the increase in the width W1, the stress in low-k dielectric layers38increases. When the width W1reaches about 20 μm, the normalized stress increases to 1.0.FIG.14also reveals that reducing the width W1results in the desirable reduction in the stress in low-k dielectric layers38, and the width W1is designed to be smaller than about 20 μm.

FIG.15illustrates the simulation results, wherein the stress in low-k dielectric layers38(FIG.10) is illustrated as a function of the height H1(FIG.11) of the via portion58A of the metal bump58. The X-axis represents the height H1in microns, and the Y-axis represents the normalized stress in low-k dielectric layers38.FIG.15reveals that with the increase in the height H1, the stress in low-k dielectric layers38reduces. When the height H1increases to about 5 μm or higher, the normalized stress reduces to the critical value of 1.0 or lower, which means that low-k dielectric layers38are unlikely to crack. Accordingly, increasing the height H1results in the desirable reduction in the stress in low-k dielectric layers38, and the height H1is designed to be greater than about 5 μm.

FIG.16illustrates the simulation results, wherein the stress in low-k dielectric layers38(FIG.10) is illustrated as a function of the tilt angle θ of the sidewalls48A (FIG.11) of the via portion58A. The X-axis represents the tilt angle θ, and the Y-axis represents the normalized stress in low-k dielectric layers38, which is normalized to the critical value of 150 MPa.FIG.16reveals that with the increase in the tilt angle θ, the stress in low-k dielectric layers38reduces. When the tilt angle θ is greater than about 45 degrees, the normalized stress reduces to the critical value of 1.0, which means that low-k dielectric layers38will not crack. Accordingly, increasing the tilt angle θ results in the desirable reduction in the stress in low-k dielectric layers38, and the tilt angle θ is designed to be greater than about 45 degrees. On the other hand, the tilt angle θ cannot be greater than 90 degrees since this will cause difficulty in forming a conformal seed layer54(FIG.5), which causes problems (such as voids) in the subsequent plating of metal bump58. In accordance with some embodiments of the present disclosure, tilt angle θ is in the range between about 70 degrees and about 80 degrees.

FIG.17illustrates the correlation of the R-angle and the tilt angle θ. The X-axis represents the tilt angle θ, and the Y-axis represents the R-angle. It is found that with the increase in the tilt angle θ, the R-angle reduces. As is aforementioned, reducing the tilt angle θ and/or reducing the R-angle may reduce the stress in low-k dielectric layers38, and vice versa. Accordingly,FIG.17reveals that increasing the tilt angle θ has similar effect as increasing the R-angle, and vice versa. The correlation as shown inFIG.17may also be reflected as:
R-angle=0.0152θ2−0.5863θ+4.3865  [Eq. 1]

As shown inFIGS.13,14,15,16, and17, the reduction of the stress in low-k dielectric layers38may be achieved through reducing the R-angle, reducing the width W1of the via portion of metal bump58, increasing the thickness H1of dielectric layer48, and increasing the tilt angle θ. Simulation results have revealed that when the width W1(FIG.11) is smaller than about 20 μm, the height H1is greater than about 5 μm, and the tilt angle is greater than about 45 degrees (and smaller than 90 degrees), no crack will be resulted in the low-k dielectric layers by the stress applied by the metal bump58and dielectric layer48.

FIG.18illustrates a relationship between tilt angle θ and the exposure focus for performing the light exposure on dielectric layer48(when dielectric layer48is a light-sensitive layer) in the process shown inFIG.2. It is appreciated thatFIG.18illustrates an example, and the relationship may be different when different exposure tool is used. As shown inFIG.18, the profile angle may be increased by increasing the exposure focus in accordance with some embodiments.

The embodiments of the present disclosure have some advantageous features. By adjusting the composition of the applied polymer, the profile of the via portion of the metal bump, which profile includes the bottom width W1of the via portion of the metal bump, the thickness of the polymer, and the tilt angle θ of the sidewall of the via portion of the metal bump, is adjusted to the desired profile, so that the stress in the underlying low-k dielectric layers is reduced, and the cracking in the low-k dielectric layers is avoided.

In accordance with some embodiments of the present disclosure, a method of forming an integrated circuit structure comprises forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer; applying a polymer layer over the patterned passivation layer, wherein the polymer layer is substantially free from NMP, and wherein the polymer layer comprises aliphatic amide as a solvent; performing a light-exposure process on the polymer layer; performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening; baking the polymer; and forming a conductive region comprising a via portion extending into the second opening. In an embodiment, the polymer layer comprises alkoxy decane. In an embodiment, the via portion comprise a straight sidewall; a straight bottom surface; and a round corner comprising a top end connecting to the straight sidewall, and a bottom end connecting to the straight bottom surface, wherein the round corner has an R-angle smaller than about 4 μm. In an embodiment, the straight sidewall has a tilt angle in a range between about 45 degrees and about 90 degrees. In an embodiment, the straight sidewall has a tilt angle in a range between about 70 degrees and about 80 degrees. In an embodiment, after the baking process, the polymer layer has a thickness greater than about 5 μm. In an embodiment, when the polymer layer is applied, the NMP has a weight percentage smaller than about 0.3 percent in the polymer layer. In an embodiment, when the polymer layer is applied, the polymer layer is free from NMP.

In accordance with some embodiments of the present disclosure, a method of forming an integrated circuit structure comprises applying a polymer layer over a metal pad; patterning the polymer layer to form an opening in the polymer layer, wherein a top surface of the metal pad is revealed to the opening, and the polymer layer comprises: a straight sidewall facing the opening; and a round corner surface comprising a top end connecting to the straight sidewall, and a bottom end joining to the top surface of the metal pad, wherein the round corner surface has an R-angle smaller than about 4 μm; and forming a conductive region comprising: a via portion extending into the opening; and a bump portion over the polymer layer. In an embodiment, the polymer layer, when applied, comprises aliphatic amide as a solvent. In an embodiment, the polymer layer, when applied, is free from NMP. In an embodiment, the polymer layer comprises silicon alkoxide. In an embodiment, the method further includes baking the polymer layer after the polymer layer is patterned.

In accordance with some embodiments of the present disclosure, an integrated circuit structure comprises a metal pad; a polymer layer over and contacting the metal pad; and a metal bump comprising a via portion in the polymer layer, wherein the via portion comprises: a straight sidewall; a straight bottom surface; and a round bottom corner comprising a top end connecting to the straight sidewall, and a bottom end connecting to the straight bottom surface, wherein the round bottom corner has an R-angle smaller than about 4 μm; and a bump portion over the polymer layer and joining to the via portion. In an embodiment, the straight sidewall has a tilt angle in a range between about 45 degrees and about 90 degrees. In an embodiment, the tilt angle is in a range between about 70 degrees and about 80 degrees. In an embodiment, the polymer layer comprises silicon alkoxide. In an embodiment, a portion of the polymer layer directly over the metal pad has a thickness greater than about 5 μm. In an embodiment, the via portion contacts a top surface of the metal pad to form an interface, and the interface has a width smaller than about 20 μm.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.