Patent ID: 12199511

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional, and material properties.

For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.

In the following disclosure, unless indicated otherwise, when reference is made to absolute positional qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or to relative positional qualifiers, such as the terms “above”, “below”, “higher”, “lower”, etc., or to qualifiers of orientation, such as “horizontal”, “vertical”, etc., reference is made to the orientation shown in the figures, or to a . . . as orientated during normal use.

Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%.

FIG.1represents schematically an embodiment of a voltage converter1. The converter1is a DC/DC converter, of the switching power supply type, which converts a DC supply voltage to a DC output voltage.

The converter1is configured to provide a DC output voltage Vout. The converter comprises an output node2, at which the voltage Vout is available.

The converter1is supplied with a DC supply voltage Vbat. The converter1is then connected between a first conductor rail, or node, 3 connected to the voltage Vbat, and a second conductor rail, or node, 5 connected to a reference potential GND.

The converter1is configured to provide the voltage Vout at a value equal to a setpoint value. For this purpose, the converter1receives, at an input node7, a DC setpoint voltage Vref referenced to the potential GND, the value of which is shown to be representative of the setpoint value of the voltage Vout, preferably equal to the setpoint value of the voltage Vout. The voltage Vref is preferably substantially constant during operation of the converter.

In this example, the voltages Vout, Vbat and Vref are positive. In this example, the voltages Vout, Vbat, and Vref are referenced to the potential GND, such as ground.

In this example, the converter1is of the step-down or buck type, i.e., the set value of the voltage Vout is lower than the value of the voltage Vbat. In other words, the value of the voltage Vout is lower than the value of the voltage Vbat.

The converter1comprises a power stage20. The power stage20comprises a first MOS (“metal oxide semiconductor”) transistor9, preferably a PMOS (P-channel MOS transistor). The MOS transistor9is coupled, preferably connected, between the rail3and an internal node11. In other words, a first conduction terminal of the transistor9, for example, its source, is coupled, preferably connected, to the rail3, with a second conduction terminal of the transistor9, for example, its drain, being coupled, preferably connected, to the node11.

The stage20further comprises a second MOS transistor13, preferably an NMOS (N-channel MOS transistor) transistor. The transistor13is coupled, preferably connected, between the node11and the rail5. In other words, a first conduction terminal of the transistor13, for example, its source, is coupled, preferably connected, to the rail5, with a second conduction terminal of the transistor13, for example, its drain, being coupled, preferably connected, to the node11. Alternatively, the NMOS transistor may be replaced by a diode or a Schottky diode.

Thus, the transistors9and13are connected in series between the rails3and5and are connected to each other at the internal node11.

Each of the transistors9and13comprises an intrinsic diode not represented. The intrinsic diodes not represented are, for example, connected in series between the rails3and5. More specifically, a first terminal, anode or cathode, of the intrinsic diode of the transistor13is coupled, preferably connected, to rail5and a second terminal, cathode or anode, of the said diode is coupled, preferably connected, to the node11. A first terminal, anode or cathode, of the intrinsic diode of the transistor9is coupled, preferably connected, to node11and a second terminal, cathode or anode, of the said diode is coupled, preferably connected, to rail3. The first terminals of the intrinsic diodes are for example the anodes and the second terminals of the intrinsic diodes are for example the cathodes. The node11is thus connected to the anode of one of the diodes and to the cathode of the other diode.

The stage20comprises an inductive element or inductor15. The inductor15is connected between the node11and the node2. The converter1comprises an output capacitive element or capacitor16connected between the node2and the rail5. As an example, the capacitance of the capacitor is greater than 2 μF, preferably between 2.2 μF to 20 μF or even more. This output capacitor16acts as a filter. In other words, this output capacitor of the converter smooths the current present on the node2and stores energy supplied to the node2by the converter.

In operation, a load not represented, is connected between the node2and rail5so as to be supplied by the voltage Vout.

The converter1comprises a control circuit17. The circuit17is configured to implement, or control, the cycles of operation of the converter1, so as to regulate the voltage Vout so that its value is equal to the setpoint value Vref. The circuit17comprises a circuit172, for example a state machine configured to generate the control signals for the transistors9and13. Thus, an output of the circuit172is coupled, preferably connected, to a control terminal of the transistor9and provides a GP signal for controlling the transistor9. Similarly, an output of the circuit172is coupled, preferably connected, to a control terminal of the transistor13and provides a GN signal for controlling the transistor13.

The converter1is for example configured to operate in pulse frequency modulation (discontinuous conduction mode). The circuit17is then configured to start a cycle of operation of the converter1when the value of the voltage Vout is lower than the setpoint value Vref and the two transistors9and13are in the off state.

For this purpose, the circuit17comprises, for example, a comparator171configured to compare the voltage Vout and the setpoint voltage Vref. The comparator171comprises an input, such as an inverting input, coupled, preferably connected, to the node2. The comparator171comprises another input, for example, a non-inverting input, coupled, preferably connected, to the node7. An output of the comparator171is coupled, preferably connected, to the circuit172, and provides a signal representing the difference between the voltage Vref and the voltage Vout.

More particularly, at the beginning of each operating cycle, signified by the output signal of the comparator171, the circuit17is configured to control the beginning of an energy accumulation phase, i.e., switching the transistor9to the on state, the transistor13being left in the off state. Energy is then accumulated in the inductor15and in the capacitor16, during a first duration TPon, a current Ic flowing in the inductor15. At the end of the duration TPon, the circuit17is configured to control the switching to the off state the transistor9and switching to the on state the transistor13. Energy is then restituted by the inductor15and the capacitor16, to the load connected at the output of the converter, during a second duration TNon, the current Ic in the inductor decreasing. At the end of the duration TNon, the circuit17is configured to control the switching to the off state the transistor13.

The durations TPon and TNon are determined by comparing the voltage ramps to a reference value, for example the setpoint voltage Vref. Thus, circuit17comprises a voltage ramp generation circuit174. The circuit174is configured to generate a voltage ramp RAMP1 and a voltage ramp RAMP2.

The voltage ramp RAMP1 is, for example, an increasing ramp, starting at a low value less than the voltage Vref. The voltage ramp RAMP2 is for example a decreasing ramp, starting at a high value, greater than the Vref value.

The circuit17comprises a comparator176. The comparator176comprises an input, preferably a non-inverting input, coupled, preferably connected, to the node7. The comparator176comprises another input, preferably an inverting input, coupled, preferably connected, to an output of circuit174on which the voltage ramp RAMP1 is provided. The comparator176comprises an output on which is provided a CMDP signal, for example a binary signal, representative of the difference between the voltage Vref and the ramp RAMP1. Specifically, the CMDP signal indicates that the ramp RAMP1 reaches the value of the voltage Vref.

The circuit17comprises a comparator178. The comparator178comprises an input, preferably an inverting input, coupled, preferably connected, to node7. The comparator178comprises another input, preferably a non-inverting input, coupled, preferably connected, to an output of circuit174at which the voltage ramp RAMP2 is provided. The comparator178comprises an output on which is provided a CMDN signal, for example a binary signal, representative of the difference between the voltage Vref and the ramp RAMP2. Specifically, the CMDN signal indicates that the ramp RAMP2 reaches the value of the voltage Vref.

Thus, during operation of the converter1, at a start of cycle, for example determined by the comparator171, the energy accumulation phase begins and the ramp RAMP1 begins to increase from the low value. When the ramp RAMP1 reaches the value Vref, the CMDP signal changes from a first value to a second value, indicating the end of the energy accumulation phase. Thus, the duration TPon corresponds to the duration of the increase of the ramp RAMP1 between the low value and the value Vref. At the end of the energy accumulation phase, the energy restitution phase begins, i.e. the states of the transistors are reversed, with the transistor9switching to an off state and the transistor13switching to an on state. Moreover, the ramp RAMP2 starts to decrease from the high value. When the ramp RAMP2 reaches the value Vref, the CMDN signal changes from a first value to a second value, indicating the end of the energy restitution phase. Thus, the duration TNo corresponds to the duration of the decrease of the ramp RAMP2 between the high value and the value Vref. The end of the energy restitution phase corresponds to the end of the cycle. The transistors9and13are then switched to an off state and the node11is in a high impedance state until the voltage Vout drops below the value of the voltage Vref again.

The circuit174is configured to allow the slope of at least one of the voltage ramps, for example the ramp RAMP2, to be changed or adjusted. In this way, the duration of at least one of the phases, for example the energy restitution phase, can be changed. The circuit174is configured so that the slope of at least one of the voltage ramps, for example the ramp RAMP2, is varied so as to achieve a zero current in the inductor at the end of the operating cycles.

The converter1comprises a circuit19configured to determine whether the current through the inductor15is positive or negative. In particular, the circuit19is configured to determine the sign, positive or negative, of the current through the inductor15at the end of each operating cycle, i.e., at the end of each energy restitution phase.

In the embodiment ofFIG.1, the circuit19comprises an input coupled, preferably connected, to the node11. The circuit19comprises, for example, an output19aon which is provided a POS signal indicating that the current in the inductor15is positive and an input19bon which is provided a NEG signal indicating that the current in the inductor15is negative.

The converter1further comprises a circuit21configured to determine, from the POS and NEG signals, the change to be made in the slope(s) of the voltage ramps. The circuit21comprises two inputs, one input coupled, preferably connected, to the output19aof the circuit19on which the POS signal is received and one input coupled, preferably connected, to the output19bof the circuit19on which the NEG signal is provided. The circuit21comprises an output on which is provided a TRIM signal representing the changes to be made on at least one voltage ramp slope. The output of circuit21is coupled, preferably connected, to an input of the circuit174.

According to one embodiment, the voltage ramp slope RAMP1 is not changed from one cycle to the next. Thus, the slope of the voltage ramp RAMP1 is substantially constant from one cycle to the next. The slope of the ramp RAMP2 can be modified from one cycle to the next, according to the sign of the current flowing through the inductor15at the end of the cycle. For example, the circuit174is configured for a finite number of ramp RAMP2 slope values. The ramp RAMP2 may be generated by the circuit174with a slope having one of N separate possible slope values. The different possible slopes range from, for example, a slope value V1 to a slope value VN, with the V1 value being, for example, the least sloping and the VN value being, for example, the most sloping.

For example, if the current in the inductor15is positive at the end of a cycle, not all of the energy has been restituted. The slope of the ramp RAMP2 is therefore, in the next cycle, modified so as to be less steep, i.e., to have a smaller inclination. For example, it passes from a value Vi of slope, to a value Vi−1. In other words, the slope is decreased to the nearest lower value. The energy restitution phase is thus longer.

Similarly, if the current in inductor15is negative at the end of a cycle, too much energy has been restituted. The slope of the ramp RAMP2 is therefore, in the next cycle, modified so as to be steeper, i.e., to have a greater inclination. For example, it passes from a value Vi, of the slope, to a value Vi+1. In other words, the slope is increased to the nearest higher value. This results in a shorter energy accumulation phase.

Preferably, when the converter starts, the value of the slope has a central, or median, value, i.e., there are as many lower values as there are higher values. Preferably, this central value is equal to or substantially equal to the value of the slope of the ramp RAMP1.

According to another embodiment, the slope of the ramp RAMP2 is not changed from one cycle to the next, and the slope of the ramp RAMP1 is changed from one cycle to the next. The operation is then similar to the operation described above, except that the slope of the ramp RAMP1 becomes steeper if the current in the inductor15is positive and becomes lower if the current in inductor15is negative at the end of the cycle.

FIG.2is a set of timing diagrams illustrating the operation of the circuit ofFIG.1.FIG.2comprises a timing diagram illustrating current (I) versus time (t). More specifically, the timing diagram illustrates the current Ic in the inductor15by a curve23and illustrates the current drawn by the unrepresented load by a curve25.FIG.2further comprises a timing diagram illustrating voltage (V) versus time (t). More specifically, the timing diagram illustrates the output voltage Vout by a curve27and the setpoint voltage Vref by a curve29.FIG.2further comprises timing diagrams illustrating the TRIM, POS and NEG signals.

The values of the TRIM signal are, in this example, related to slope values. Thus, if the TRIM signal has a value of 8, the slope has a value of V8.

It can be observed that at the end of each operating cycle, which corresponds to a minimum of the curve29, a pulse, i.e. a switching of the signal to the high value for a duration of a few nanoseconds, occurs on the POS signal if the current Ic is positive and a pulse occurs on the NEG signal if the signal Ic is negative.

In the example ofFIG.2, the value of the TRIM signal is modified if two successive pulses occur on the NEG signal, or on the POS signal. More generally, the value of the TRIM signal can be modified at each cycle, or every N cycles, where N is an integer, for example, at least equal to 2.

Thus, in a phase P1, the current Ic is less than 0 at the end of the operating cycles, which leads to the formation of a pulse on the NEG signal. For every two pulses of the NEG signal, in the example ofFIG.2, the value of the TRIM signal decreases by a constant value, for example the step of a counter, for example 1. It can then be observed that the maximum negative value of the current Ic at the end of the cycle approaches 0 during phase P1 with the changes in the value of TRIM and thus the change in the slope of the ramp RAMP2. Thus, at the end of the phase P1, the value of the current Ic at the end of the cycle is substantially equal to 0.

Similarly, in a phase P2, subsequent to phase P1, the current Ic is greater than 0 at the end of the operating cycles, which leads to the formation of a pulse on the POS signal. The transition from phase P1 to phase P2 is caused, for example, by an increase in the current drawn by the load, illustrated by the curve25. This increase is caused, for example, by a change in the supply voltage. For every second pulse of the POS signal, the value of the TRIM signal increases by a constant value, for example 1. It can then be observed that the positive value of the current Ic at the end of the cycle decreases during the phase P1 with the changes in the TRIM value and thus the change in the slope of the ramp RAMP2.

FIG.2shows a phase P3 similar to phase P1.

FIG.3represents in greater detail an example implementation of a portion of the embodiment ofFIG.1. Specifically,FIG.3represents the circuits19and20in greater detail. The circuit19is configured to determine whether an input voltage is within a range of voltages. In other words, circuit19is configured to compare the said input voltage to first and second voltage thresholds, different from each other.

The circuit20is identical to circuit20represented inFIG.1, except that circuit20comprises, inFIG.3, two diodes218and220that were not represented inFIG.1. The diodes218and220are connected in series between rail3and rail5. Specifically, a first terminal, anode or cathode, of diode220is coupled, preferably connected, to the rail5and a second terminal, cathode or anode, of diode220is coupled, preferably connected, to the node11. A first terminal, anode or cathode, of the diode218is coupled, preferably connected, to the node11and a second terminal, cathode or anode, of the diode218is coupled, preferably connected, to the rail3. In the example ofFIG.3, the first terminals of the diodes218and220are anodes and the second terminals of the diodes218and220are cathodes. Thus, the node11is connected to the anode of one of the diodes and to the cathode of the other diode.

In other words, each diode is coupled, preferably connected, in parallel with one of the transistors9and13. For example, the anode of the diode218is coupled, preferably connected, to the source of the transistor9and the cathode of the diode218is coupled, preferably connected, to the drain of the transistor9. Similarly, the anode of the diode220is coupled, preferably connected, to the source of transistor13and the cathode of the diode220is coupled, preferably connected, to the drain of the transistor13. For example, the cathode of the diode218is also coupled, preferably connected, to the substrate of the transistor9. The anode of the diode220is also, for example, coupled, preferably connected, to the substrate of the transistor13. Preferably, the diodes218and220are the intrinsic diodes of the transistors9and13, respectively.

The circuit10comprises an input102coupled, preferably connected, to the node11and the two outputs19aand19b. The input102receives a voltage VLX, which is desired to be compared to the voltage range, and more specifically, desired to be compared to the first and second voltage thresholds. In the example ofFIG.3, the first and second thresholds are respectively the positive supply voltage Vbat of the converter1and a reference voltage GND, preferably ground. The output19aprovides a POS signal, preferably binary, and the output19bprovides a NEG signal, preferably binary. When the circuit10determines that the input voltage is greater than, for example by a value substantially equal to a diode threshold, the first threshold Vbat of the range, the NEG signal takes a first value, for example a high value. If the input voltage is less than the first threshold Vbat, the NEG voltage takes on a second value, for example, a low value. When the circuit10determines that the input voltage is less than, for example by a value substantially equal to a diode threshold, the second threshold of the range, the POS signal takes a first value, for example a high value. If the input voltage is greater than the second threshold, the POS voltage takes on a second value, for example a low value.

Thus, if both the POS and NEG signals have a low value, it means that the input voltage is between the first and second thresholds. If the NEG signal has a high value and the POS signal has a low value, the input voltage has a value greater than the first threshold. If the NEG signal has a low value and the POS signal has a high value, the input voltage has a value less than the second threshold.

The circuit10comprises two transistors108and no connected in series between the rails3and5. More specifically, one of the conduction terminals, source or drain, of the transistor108is coupled, preferably connected, to a node112. The other conduction terminal of the transistor108, drain or source, is coupled, preferably connected, to the input node102. One conduction terminal of the transistor no, source or drain, is coupled, preferably connected, to the node102. The other conduction terminal of transistor no, drain or source, is coupled, preferably connected, to a node114.

Preferably, the transistor no is a P-type, or PMOS field effect transistor, and the transistor108is an N-type, or NMOS field effect transistor. Preferably, transistors108and no are coupled, preferably connected, to the node102through their respective sources.

The transistor108is controlled by a voltage whose value is substantially equal to, preferably equal to, the second voltage threshold, here the reference voltage GND. In other words, the control terminal, or gate, of the transistor108is connected to the rail5for applying the voltage GND. The transistor no is controlled by a voltage whose value is substantially equal, preferably equal, to the first voltage threshold, here the supply voltage Vbat. In other words, the control terminal, or gate, of the transistor no is connected to the voltage Vbat application rail3.

The node112is connected to the rail3, preferably through a resistive element, or resistor,116. The node112is also connected to the output node19a, preferably by a circuit, or inverter,117configured to invert the binary signals. Thus, when the circuit117receives a low value at the input, it provides a high value at the output and vice versa.

The node114is connected to rail5, preferably by a resistive element, or resistor,118. The node114is also connected to the output node19b, preferably by two circuits, or inverters,120and122in series configured to invert the binary signals.

The resistor116, transistor108, transistor no, and resistor118are thus connected in series in this order between the rails3and5.

The circuits117,120and122ensure that the POS and NEG signals are binary signals with recognizable high and low values.

FIG.4is a set of timing diagrams illustrating the operation of the circuit inFIG.3. Specifically,FIG.4represents the behavior of the control signals GN, GP, of the current Ic, the voltage VLX on node11, and the POS and NEG signals, during one cycle of the operation of the circuit20ofFIG.1and during a portion (E) of a subsequent cycle. The cycle of operation includes, for example, four phases: an energy accumulation phase (A) in the inductor15, not shown inFIG.4, an intermediate phase (B), an energy restitution phase (C), and a compensation phase (D).

During the energy accumulation phase (A), transistor9is in an on state and transistor13is in an off state. This corresponds, in the embodiment ofFIG.1, to the control signal GN having a low value and the control signal GP having a low value. The voltage VLX thus has a positive value V1, less than the value Vbat. Thus, during the phase (A), the current Ic through the inductor, not shown inFIG.1, increases.

Since the voltage VLX is lower than the control voltage of transistor no, i.e., the supply voltage Vbat, the gate-source voltage of transistor no is positive. The transistor no thus remains in an off state during the phase (A). Thus, the voltage on the node114has a low value, for example substantially equal to the reference voltage GND. The NEG signal, at the output of inverters120and122thus has a low value.

Similarly, the voltage VLX is higher than the control voltage of the transistor108, i.e. the reference voltage GND, the gate-source voltage of the transistor108is negative. The transistor108therefore remains in an off state during phase (A). Thus, the voltage on the node112has a high value, for example substantially equal to the voltage Vbat. The POS signal, at the output of the inverter117, therefore has a low value.

During the phase (B), the transistors13and9are in an off state. This corresponds, in the embodiment ofFIG.1, to the control signal GN having a low value and the control signal GP having a high value. The phase (B) is an intermediate phase to ensure that the transistors9and13are not simultaneously switched to an on state. During the phase (B), the node11is no longer supplied by rail3. The current Ic therefore decreases. The current Ic is positive and transistors9and13are in an off state. The current IC flows through the diode220. The voltage VLX takes a negative value V3.

Since the voltage VLX is lower than the control voltage of transistor no, i.e. the supply voltage Vbat, the gate-source voltage of transistor no is positive. The transistor no thus remains in an off state during the phase (B). Thus, the voltage on the node114is a low value, for example substantially equal to the reference voltage GND. The NEG signal, at the output of inverters120and122thus has a low value.

The voltage VLX is negative. In other words, the voltage VLX is lower than the control voltage of the transistor108, i.e., the reference voltage GND. Therefore, the gate-to-source voltage of transistor108is positive. The transistor108is therefore in an on state during the phase (B). Thus, the voltage on the node112has a low value, for example substantially equal to the voltage V3. The POS signal, at the output of the inverter117, is however maintained at the low value. Preferably, the POS signal and the NEG signal are maintained at the low value until the end of the energy restitution phase, for example until a falling edge of the GN signal. For example, the holding of the NEG and POS signals at the low value during the phases A, B and C is performed by elements not represented. For example, holding the NEG and POS signals at a low value during the phases A, B and C is performed by the circuit21.

During the phase (C), i.e. the energy restitution phase, the transistor13is in an on state and the transistor9is in an off state. This corresponds, in the embodiment ofFIG.3, to the control signal GN having a high value and the control signal GP having a high value. The voltage VLX increases but remains negative. During the phase (C), the current Ic decreases, as the node11is no longer supplied by the rail3.

Since the voltage VLX is lower than the control voltage of transistor no, i.e. the supply voltage Vbat, the gate-source voltage of transistor no is positive. The transistor no thus remains in an off state during the phase (C). Thus, the voltage on the node114has a low value, for example substantially equal to the reference voltage GND. The NEG signal at the output of the inverters120and122therefore has a low value.

The voltage VLX is negative. In other words, the voltage VLX is lower than the control voltage of the transistor108, i.e., the reference voltage GND. The gate-to-source voltage of the transistor108is therefore positive. The transistor108is therefore in an on state during the phase (B). Thus, the voltage on the node112has a low value, for example substantially equal to the voltage V3. The POS signal, at the output of the inverter117, is however maintained at the low value during the phase (C).

During the phase (D), the transistor13is switched to an off state and the transistor9is switched to an off state. This corresponds, in the embodiment ofFIG.1, to the control signal GN having a low value and the control signal GP having a high value.

As in the phase (B), the current Ic is positive and the transistors9and13are in an off state. The current Ic therefore flows through the diode220. The voltage VLX takes the negative value V3.

The voltage VLX being, as in the phase (B), lower than the control voltage of the transistor no, i.e. the supply voltage Vbat, the gate-source voltage of the transistor no is positive. The transistor no thus remains in an off state during the phase (B). Thus, the voltage on the node114has a low value, for example substantially equal to the reference voltage GND. The NEG signal, at the output of the inverters120and122thus has a low value.

As in the phase (B), the voltage VLX is negative. In other words, the voltage VLX is lower than the control voltage of the transistor108, i.e., the reference voltage GND. The gate-to-source voltage of the transistor108is therefore positive. The transistor108is therefore in an on state during the phase (B). Thus, the voltage on the node112has a low value, for example substantially equal to the voltage V3. The POS signal, at the output of the inverter117, is however maintained at the low value, for example until the falling edge of the GN signal.

During the phase (D), the current Ic continues to decrease. The phase (D) ends when the current Ic reaches the value zero. During the phase (D), the POS and NEG signals are no longer held at the low value. Thus, the POS signal takes the high value. The NEG signal still has the low value.

The phase (D) is followed by a phase (E) corresponding to, for example, the phase (A) of a subsequent operating cycle or a phase at standstill.

FIG.5is a set of timing diagrams illustrating the operation of the circuit ofFIG.3. More specifically,FIG.5represents the behavior of the control signals GN, GP, the current Ic, the voltage VLX on the node206, and the POS and NEG signals, during an operating cycle of the circuit20ofFIG.1. The operating cycle includes, as inFIG.2, four phases: a phase (A) of energy accumulation in the inductive element, an intermediate phase (B), an energy restitution phase (C), and a compensation phase (D).

The phases (A) and (B) are identical to phases (A) and (B) inFIG.4and will not be described again.

During the energy restitution phase (C), the transistor13is in an on state and transistor9is in an off state. This corresponds, in the embodiment ofFIG.1, to the control signal GN having a high value and the control signal GP having a high value.

The voltage VLX increases during the phase (C). At an instant tz of phase (C), the voltage VLX reaches the value zero, and then continues to increase. The current Ic decreases during the phase (C). At the instant tz, the current Ic reaches the value zero. During phase (C), the current Ic is positive before instant tz and negative after instant tz and the voltage VLX is negative before instant tz, and positive after instant tz.

During the phase (C), the voltage VLX is lower than the first voltage threshold Vbat. Thus, the NEG signal maintains the low value. In addition, the voltage VLX is lower than the second voltage threshold GND before instant tz, and above the second threshold after instant tz. During the phase (C), the POS signal is kept low.

During the phase (D), the transistor13is in an off state and the transistor9is in an off state. This corresponds, in the embodiment ofFIG.3, to the control signal GN having a low value and the control signal GP having a high value.

With transistors9and13being in an off state, and with the current Ic negative, the diode218becomes active. The voltage VLX thus becomes higher than the voltage Vbat, for example substantially equal to the voltage Vbat plus the threshold voltage of the diode218. Thus, the current Ic increases until it reaches zero. When the current reaches zero, the phase (D) is complete.

Since the voltage VLX is higher, for example by a value substantially equal to a diode threshold, than the control voltage of the transistor no, i.e., the supply voltage Vbat, the NEG signal has a high value. In addition, the voltage VLX is higher than the control voltage of the transistor108, i.e. the reference voltage GND, the POS signal has a low value.

The phase (D) is followed by a phase (E), in which the device behaves similarly to its behavior in the phase (A). Alternatively, the phase (E) corresponds to a phase at standstill.

FIG.6represents in greater detail another part of the embodiment ofFIG.1.FIG.6represents in greater detail a portion of the voltage ramp generation circuit174. More specifically,FIG.6represents the portion of the circuit174generating the voltage ramp whose slope depends on the TRIM signal, i.e., the ramp RAMP2 in the example whose operation is described in relation toFIG.1.

The circuit174comprises a resistor302and a transistor304connected in series between the node3for applying the supply voltage Vbat and the node5for applying a reference voltage GND. More specifically, one terminal of the resistor302is coupled, preferably connected, to the node3and another terminal of the resistor302is coupled, preferably connected, to a node303. One conduction terminal, for example, the drain, of transistor304is coupled, preferably connected, to the node303and another conduction terminal, for example, the source of the transistor304is coupled, preferably connected, to the node5.

The circuit174further comprises the switches306and308in series with a transistor310. More specifically, one terminal of the switch306is coupled, preferably connected, to the node3and another terminal of the switch306is coupled, preferably connected, to a node312. One terminal of the switch308is coupled, preferably connected, to the node312and another terminal of the switch308is coupled, preferably connected, to a node314. One conduction terminal, for example, the drain, of the transistor310is coupled, preferably connected, to the node314and another conduction terminal, for example, the source, of the transistor310is coupled, preferably connected, to the node5.

Thus, the set comprising the resistor302and the transistor304is in parallel with the set comprising the switches306,308and the transistor310.

Preferably, the transistors304and310are of the same type, for example N-channel MOS transistors. For example, the transistors304and310are identical. The control terminals of the transistors304and310are coupled, preferably connected, to each other.

The circuit174further comprises an operational amplifier316. The operational amplifier316receives on one input the voltage Vout and on another input the voltage on the node303. In other words, the operational amplifier316comprises one input coupled, preferably connected, to the node2(FIG.1) and another input coupled, preferably connected, to the node303. The operational amplifier supplies on output the control signal for the transistors304and310. Thus, the operational amplifier comprises an output coupled, preferably connected, to the control terminals of the transistors304and310.

The circuit174further comprises a capacitor, or capacitive circuit with variable capacitance. That is, the circuit174includes at least two capacitors connected between the nodes312and5. More specifically, the circuit174comprises a transistor318connected between the nodes312and5. One terminal of the capacitor318is coupled, preferably connected, to the node312and another terminal of the capacitor318is coupled, preferably connected, to the node5. Thus, the capacitor318is charged whenever the circuit174generates a voltage ramp.

The circuit174comprises at least one set320. Each set320comprises a capacitor322and a switch324connected in series between the nodes312and5. More specifically, in each set320, one terminal of capacitor322is coupled, preferably connected, to the node5and another terminal of the capacitor is coupled, preferably connected, to one terminal of the switch324, with the other terminal of the switch324being coupled, preferably connected, to the node312. Preferably, the capacitors322are identical to each other and identical to the capacitor318.

When generating the voltage ramp RAMP2, the switch306is in an on state and the switch308is in an off state, so as to charge the capacitor318and the capacitors322of the set whose switch324is in an on state. The overall capacitance value of the charged capacitors determines the slope of the voltage ramp RAMP2. Thus, the greater the number of switches in an on state, the greater the overall capacitance, and the lower the slope of the ramp RAMP2.

The states of the switches324are determined by the TRIM signal. Thus, the TRIM signal determines the number of switches in an off state (open) and the number in an on state (closed). Thus, the TRIM signal determines the slope of the ramp RAMP2. For example, if the value of the TRIM signal increases, the number of open switches324increases, or conversely, as the value of the TRIM signal increases, the number of open switches324decreases. For example, if the TRIM signal value increases by one step, for example 1, a switch324is open and if the TRIM signal value decreases by one step, for example 1, a switch324is closed. Preferably, only one switch324may be closed or open from one cycle to the next. Preferably, when the converter1is started, one half of the switches324are open and the other half of the switches are closed.

For example, the circuit174comprises a circuit, not represented, configured to convert the TRIM signal, into a binary word, comprising for example one bit for each switch324.

Alternatively, the capacitor318may be replaced with a set320.

FIG.7represents in greater detail a portion of the embodiment ofFIG.1. More specifically,FIG.7represents an example of the implementation of the circuit21.

The circuit21receives at inputs400and402respectively the POS and NEG signals. The circuit21additionally receives the CMDP signal at an input404. The circuit21further receives an ENA signal at an input406. The ENA signal is a binary start-up signal for the converter1. In other words, when the ENA signal is at a first binary value, preferably the value 0, the converter is in an off state, and when the ENA signal has a second binary value, preferably the value 1, the converter1is in an on state. Thus, during the operation of the circuit21, the ENA signal has a constant value equal to 1.

The circuit21comprises two D flip-flops408and410. The circuit21further comprises two NAND logic gates412and414, and two OR logic gates416and418.

The flip-flop408comprises a data input D1at which the reference voltage GND is provided. In other words, the D1input of the flip-flop408is coupled, preferably connected, to the node5. In other words, the D1input receives, consistently during the operation of the circuit21, as an input, the binary value 0.

The flip-flop408comprises a clock input CLK1. The CLK1input is coupled, preferably connected, to a node420on which the complementary signal of the CMDP control signal is provided. Thus, the node404is connected to node420by an inverter circuit422. An input of the circuit422is coupled, preferably connected, to the node404and an output of the circuit422is coupled, preferably connected, to the node420.

The flip-flop408comprises an output Q1coupled, preferably connected, to a node424.

Similarly, the flip-flop410comprises a data input D2at which the reference voltage GND is provided. In other words, the D2input of the flip-flop410is coupled, preferably connected, to the node5. In other words, the D2input receives, consistently during the operation of the circuit21, as an input the binary value 0.

The flip-flop410comprises a clock input CLK2. The CLK2input is coupled, preferably connected, to the node420on which the complementary signal of the CMDP control signal is provided.

The flip-flop410comprises an output Q2coupled, preferably connected, to a node426.

The flip-flops408and410further comprise set1 and set2 active inputs which are set to 1 and zero respectively, i.e., the Q1or Q2output is set to 1 if the signal on the respective input is zero. The set1 input is coupled, preferably connected, to an output of the OR gate416. One input of the gate416is coupled, preferably connected, to the node426and another input of the OR gate416is coupled, preferably connected, to an output of the NOT AND gate412. One input of the NOT AND gate412is coupled, preferably connected, to the node400and another input of the NOT AND gate412is coupled, preferably connected, to the node406.

The set2 input is coupled, preferably connected, to an output of the OR gate418. One input of the gate418is coupled, preferably connected, to node424and another input of the OR gate418is coupled, preferably connected, to an output of the NOT AND gate414. One input of the NOT AND gate414is coupled, preferably connected, to the node402and another input of the NOT AND gate414is coupled, preferably connected, to the node406.

Thus, at each rising edge of the CMDP signal, i.e., at the beginning of each energy accumulation phase, i.e., at the end of each cycle:the binary value on the node424, i.e., an ipos_det signal, assumes the value of 1 if the POS signal has the value of 1, the ENA signal has the value of 1, and if the binary value on the node426is equal to 0, i.e., if the circuit19determines that the current in the inductor15is positive, if the circuit21is operating, and if the circuit19has not determined that the current in the inductor is negative.the binary value at the node424, i.e., an ipos_det signal, assumes the value 0 if the POS signal or the ENA signal is 0, or if the binary value at the node426is 1, i.e., if the circuit19does not determine that the current in the inductor15is positive, or if the circuit21is not operating or if the circuit19determines that the current in the inductor is negativethe binary value at the node426, i.e., an ineg_det signal, assumes the value of 1 if the NEG signal has the value of 1, the ENA signal has the value of 1, and the binary value at the node424is 0, i.e., if the circuit19determines that the current in the inductor15is negative, if the circuit21is operating, and if the circuit19has not determined that the current in the inductor is positive; andthe binary value at node426, i.e., an ineg_det signal, takes on the value 0 if the NEG signal or the ENA signal is 0, or if the binary value at the node424is 1, i.e., if the circuit19does not determine that the current in the inductor15is negative, or if the circuit21is not operating or if the circuit19determines that the current in the inductor is positive.

Preferably, the ipos_det and ineg_det signals cannot be equal to 1 at the same instant. If the ipos_det and ineg_det signals are equal to 1 at the same instant, this information is ignored by the circuit430. If the POS signal is set to 1 when the ineg_det signal is already set to 1, an input of the OR gate416is already set to 1, so setting the POS signal to 1 does not change the output value of416and the ipos_det signal cannot be set to 1. Similarly, if the NEG signal is set to 1 when the ipos_det signal is already set to 1, an input of the OR gate418is already set to 1 and therefore setting the NEG signal to 1 does not change the output value of418and the ineg_det signal cannot change to 1.

The circuit21further comprises a circuit430. The circuit430receives as input the ipos_det, ineg_det signals. In other words, the circuit430comprises an input coupled, preferably connected, to the node424and an input coupled, preferably connected, to the node426. In addition, the circuit430comprises a clock input CLK at which the circuit430receives the complementary signal of the CMDP signal. In other words, the CLK input of the circuit430is coupled, preferably connected, to the node420. The circuit430further comprises an output on which the TRIM signal is provided. The TRIM signal is, for example, provided on a multi-bit data bus, such as a 5-bit data bus.

The circuit430is configured to change the value of the TRIM signal according to the values of the ipos_det and ineg_det signals. For example, the circuit430is a counter configured to, at each falling edge of the complementary signal of the CMDP signal, i.e., at each rising edge of the CMDP signal, i.e., at the beginning of each cycle, decrease the value of the TRIM signal by one step, preferably by 1, if the ipos_det signal has the value of 1 and increase the value of the TRIM signal if the ineg_det signal has the value of 1. Preferably, if the TRIM signal value reaches the minimum value, for example 0, and the ipos_det signal has the value 1, the TRIM signal value is not changed. Similarly, if the TRIM signal value reaches the maximum value, and the ineg_det signal has the value 1, the TRIM signal value is not changed. Furthermore, if the ipos_det and ineg_det signals are simultaneously1, the TRIM signal value is not changed.

More generally, the circuit21is configured to detect at a given instant, for example the beginning of a cycle corresponding for example to a rising edge of the control signal of the transistor9, the state of the POS and NEG signals so as to modify the TRIM signal. This is done by means of D flip-flops, and in particular by supplying the POS and NEG signals, set to 1, to the asynchronous (SET) inputs of the flip-flops, the flip-flops being reset to 0 on the falling edge of the CMDP signal of each cycle.

Preferably, the device1is configured so that a rising edge of the CMDP signal does not occur at the same time that the POS and NEG signals have a high value, i.e., a value of 1.

An advantage of the described embodiments is that it allows a current through the inductor to be zero at the end of the cycle.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art.

Finally, the practical implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art based on the functional description provided hereinabove.