Patent ID: 12243500

DETAILED DESCRIPTION

Technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to accompanying drawings. Obviously, the described embodiments are merely some but not all embodiments of the present disclosure. All other embodiments obtained on a basis of the embodiments of the present disclosure by a person of ordinary skill in the art shall be included in the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term “comprise” and other forms thereof such as the third-person singular form “comprises” and the present participle form “comprising” are construed as an open and inclusive meaning, i.e., “including, but not limited to.” In the description of the specification, the terms such as “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to indicate that specific features, structures, materials or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s). In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner.

Below, the terms “first” and “second” are used for descriptive purposes only, and are not to be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, “a plurality of”, “the plurality of” or “multiple” means two or more unless otherwise specified.

In the description of some embodiments, the expressions “coupled” and “connected” and their derivatives may be used. For example, the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. For another example, the term “coupled” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

The phrase “at least one of A, B and C” has a same meaning as the phrase “at least one of A, B or C”, and they both include the following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C.

The phrase “A and/or B” includes the following three combinations: only A, only B, and a combination of A and B.

In the related art, for a display apparatus with a large size and a narrow bezel, such as a high aperture advanced super dimensional switching (HADS) display apparatus, the bezel thereof is relatively narrow (e.g., a width of the bezel is 3.5 mm), so that a width of a signal line is small, a resistance of the signal line increases, and a recovery capability of the signal line decreases. In addition, high resolution of the display apparatus (e.g., the resolution is (2560×1440)) and a large coupling capacitance (e.g., a coupling capacitance formed between a data line and a common electrode) in the display apparatus may result in signal distortion in a signal transmission process and potential drift, which affects normal charging and discharging of pixels, so that line image sticking may appear and are difficult to eliminate in a display period of the display apparatus. An image sticking is an image retention, in which a static picture remains on a screen for a long time. This phenomenon will change with a passage of time and a change of the picture, and finally disappear. For example, there may be accumulation of charges in a pixel electrode of the display apparatus due to the coupling capacitance and other reasons. In a case where the charges accumulate to a certain extent, a potential difference and an electric field may be formed between the pixel electrode and a common electrode, which causes liquid crystals to continue to deflect. The charges will appear as image sticking in a process of slowly disappearing, thereby affecting a display effect.

The embodiments of the present disclosure provide an array substrate100. As shown inFIG.1, the array substrate100has a display area (also referred to as an active area) AA and a bonding region B (the bonding region B corresponding to a first region101of the array substrate100inFIG.10, which can be understood as that the bonding region B is located in the first region101, or the bonding region B is the first region101) located at a side of the display area. Referring toFIG.10, the array substrate100further has a second region102, a third region103and a fourth region104. The first region101and the second region102both extend in the first direction X. The first region101and the second region102are opposite in the second direction Y, and the third region103and the fourth region104are opposite in the first direction X. The display area AA is located between the first region101and the second region102and between the third region103and the fourth region104. The display area includes a distal region F away from the bonding region B.

The array substrate100includes a base10, a common electrode20, a first common signal line30, and a feedback signal line40.

The common electrode20is disposed on the base10and located in the display area.

For example, a material of the common electrode20may be a transparent conductive material including indium tin oxide (ITO).

The first common signal line30and the feedback signal line40are disposed on the base10. The first common signal line30is disposed in the third region103or the fourth region104.

The first common signal line30and the feedback signal line40are coupled to a portion of the common electrode20located in the distal region F. The first common signal line30and the feedback signal line40extend to the bonding region B to be coupled to a circuit board.

The feedback signal line40is configured to transmit a common voltage signal of the portion of the common electrode20located in the distal region F to the circuit board.

The first common signal line30is configured to transmit a first compensation common voltage signal to the portion of the common electrode20located in the distal region F.

The first compensation common voltage signal is a signal obtained by the circuit board compensating for the common voltage signal according to the common voltage signal.

For example, an area of the distal region F accounts for ⅛ to ⅕ of an area of the display area, e.g., the area of the distal region F accounts for ⅙ of the area of the display area.

In this case, the feedback signal line40transmits the common voltage signal of the portion of the common electrode20located in the distal region F to the circuit board; the circuit board obtains the first compensation common voltage signal according to the common voltage signal; and transmits the first compensation common voltage signal to the portion of the common electrode20located in the distal region F through the first common signal line30, so as to compensate for the common voltage signal of the portion of the common electrode20located in the distal region F, which may avoid delay in the common voltage signal of the portion of the common electrode20located in the distal region F, thereby improving the display effect.

Therefore, the array substrate100provided by the embodiments of the present disclosure includes the first common signal line30and the feedback signal line40, and the first common signal line30and the feedback signal line40are coupled to the portion of the common electrode20located in the distal region F. The feedback signal line40transmits the common voltage signal of the portion of the common electrode20located in the distal region F to the circuit board, so as to generate the first compensation common voltage signal. The first common signal line30transmits the first compensation common voltage signal to the portion of the common electrode20located in the distal region F, so as to compensate for the common voltage signal of the portion of the common electrode20located in the distal region F. As a result, the delay in the common voltage signal of the portion of the common electrode20located in the distal region F may be avoided, and the image sticking appearing during display caused by the potential drift of the common voltage signal may also be avoided, thereby improving the display effect.

In some embodiments, as shown inFIG.2, the array substrate100includes two feedback signal lines40, and the two feedback signal lines40are disposed on two opposite sides of the display area. That is, the first common signal lines30are disposed in the third region103and the fourth region104.

In this case, in a process where the feedback signal line40transmits the common voltage signal of the portion of the common electrode20located in the distal region F to the circuit board, transmission time of the common voltage signal may be shortened, and the common voltage signal may be quickly transmitted to the circuit board, so that an efficiency of compensating for the common voltage signal may be improved.

In some embodiments, as shown inFIG.3, the array substrate100includes two first common signal lines30, and the two first common signal lines30are disposed on the two opposite sides of the display area. Positions where the first common signal lines30are coupled to the common electrode20are located on a side of the common electrode20away from the bonding region B.

The positions where the first common signal lines30are coupled to the common electrode20are the positions, in the portion of the common electrode20located in the distal region F, that are farthest away from the bonding region B.

Since there is a large gap between the portion of the common electrode20located in the distal region F and the circuit board, signals are greatly affected by the coupling capacitance in the array substrate100in a process where the circuit board transmits the signals to the portion of the common electrode20located in the distal region F. Therefore, the first common signal line30transmits the first compensation common voltage signal to a side of the portion of the common electrode20located in the distal region F away from the bonding region B, so as to compensate for the common voltage signal of the portion of the common electrode20located in the distal region F. As a result, it may be possible to improve a problem of serious delay in the common voltage signal of the portion of the common electrode20located in the distal region F, and avoid a distortion of the common voltage signal. In addition, the two first common signal lines30may shorten time for compensating for the common voltage signal of the portion of the common electrode20located in the distal region F, and improve the efficiency of compensating for the common voltage signal of the common electrode20.

For example, part (a) inFIG.4is waveform diagrams before the common voltage signal in the array substrate100is compensated, and part (b) inFIG.4is waveform diagrams after the common voltage signal in the array substrate100is compensated, wherein a horizontal axis represents time (μs), and a vertical axis represents a voltage (V) of the common voltage signal. According to a common voltage signal Vleft on one of the two first common signal lines30located on one of the two opposite sides of the display area (e.g., a left side of the array substrate100inFIG.3), and a common voltage signal Vright on another of the two first common signal lines30located on another of the two opposite sides of the display area (e.g., a right side of the array substrate100inFIG.3), it may be seen that a signal delay degree of the waveforms of the common voltage signals in part (a) inFIG.4is relatively large, and a potential drift degree of the waveforms of the common voltage signals in part (b) inFIG.4is obviously weakened compared with a potential drift degree of the waveforms of the common voltage signals in part (a) inFIG.4, which may avoid the distortion of the common voltage signal and improve a recovery capability of the first common signal line30.

In some embodiments, as shown inFIG.5, the display area further includes a proximal region N proximate to the bonding region B. The array substrate100further includes a second common signal line50. The second common signal line50is coupled to a portion of the common electrode20located in the proximal region N, and the second common signal line50extends to the bonding region B to be coupled to the circuit board. The second common signal line50is disposed in the third region103or the fourth region104.

The second common signal line50is configured to transmit the common voltage signal or a second compensation common voltage signal to the portion of the common electrode20located in the proximal region N.

For example, an area of the proximal region N accounts for ⅛ to ⅕ of the area of the display area, e.g., the area of the proximal region N accounts for ⅙ of the area of the display area.

In this case, the feedback signal line40transmits the common voltage signal of the portion of the common electrode20located in the distal region F to the circuit board; the circuit board obtains the second compensation common voltage signal according to the common voltage signal; and transmits the second compensation common voltage signal to the portion of the common electrode20located in the proximal region N through the second common signal line50, so as to compensate for a common voltage signal of the portion of the common electrode20located in the proximal region N, which may avoid delay in the common voltage signal of the portion of the common electrode20located in the proximal region N, thereby improving the display effect.

In some embodiments, as shown inFIG.6, the array substrate100includes two second common signal lines50, and the two second common signal lines50are disposed at two opposite ends of a side of the proximal region N proximate to the bonding region B. That is, the second common signal lines50are disposed in the third region103and the fourth region104.

In this case, in a process where the second common signal line50transmits the second compensation common voltage signal to the portion of the common electrode20located in the proximal region N, the two second common signal lines50may shorten the transmission time of the second compensation common voltage signal, so that the common voltage signal of the portion of the common electrode20located in the proximal region N may be compensated quickly, thereby improving the efficiency of compensating for the common voltage signal of the common electrode20.

In some embodiments, as shown inFIG.7, the display area further includes a middle region M located between the distal region F and the proximal region N. The array substrate100further includes a third common signal line60disposed on the base10. The third common signal line60is disposed in the third region103or the fourth region104.

The third common signal line60extends to the bonding region B to be coupled to the circuit board. The third common signal line60is coupled to a portion of the common electrode20located in the middle region M.

The third common signal line60is configured to transmit a third compensation common voltage signal to the portion of the common electrode20located in the middle region M.

For example, the third common signal line60may be disposed between the first common signal line30and the display area AA, and the feedback signal line40may be disposed between the first common signal line30and the third common signal line60.

For example, an area of the middle region M accounts for ⅛ to ⅕ of the area of the display area, e.g., the area of the middle region M accounts for ⅙ of the area of the display area.

In this case, the feedback signal line40transmits the common voltage signal of the portion of the common electrode20located in the distal region F to the circuit board; the circuit board compensates for the common voltage signal according to the common voltage signal, so as to obtain the third compensation common voltage signal; and the third common signal line60transmits the third compensation common voltage signal to the portion of the common electrode20located in the middle region M, so as to compensate for a common voltage signal of the portion of the common electrode20located in the middle region M, which may avoid delay in the common voltage signal of the portion of the common electrode20located in the middle region M, thereby improving the display effect.

In some embodiments, as shown inFIG.8, the array substrate100includes two third common signal lines60, and the two third common signal lines60are disposed on the two opposite sides of the display area. That is, the third common signal lines60are disposed in the third region103and the fourth region104.

In this case, in a process where the third common signal lines60transmit the third compensation common voltage signal to the portion of the common electrode20located in the middle region M, the two third common signal lines60may shorten the transmission time of the third compensation common voltage signal, so that the common voltage signal of the portion of the common electrode20located in the middle region M may be compensated quickly, thereby improving the efficiency of compensating for the common voltage signal of the common electrode20.

In some embodiments, as shown inFIG.9, the array substrate100includes two first common signal lines30, two second common signal lines50, two third common signal lines60, and two feedback signal lines40, and beneficial effects are similar to the above, which will not be repeated here.

In some embodiments, the feedback signal line(s)40and the first common signal line(s)30are made of a same material and disposed in a same layer.

For example, the material of the feedback signal line(s)40and the first common signal line(s)30may include a metal material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), and tungsten (W).

In this case, the feedback signal line(s)40and the first common signal line(s)30may be formed synchronously, so that production processes may be simplified in terms of process.

In some embodiments, in a case where the array substrate100includes the second common signal line(s)50, the second common signal line(s)50and the first common signal line(s)30are made of a same material and disposed in a same layer.

In this case, the second common signal line(s)50and the first common signal line(s)30may be formed synchronously, so that the production processes may be simplified in terms of process.

In some embodiments, in a case where the array substrate100includes the third common signal line(s)60, the third common signal line(s)60and the first common signal line(s)30are made of a same material and disposed in a same layer.

In this case, the third common signal line(s)60and the first common signal line(s)30may be formed synchronously, so that the production processes may be simplified in terms of process.

In some embodiments, as shown inFIG.10, the array substrate100further includes a connecting lead70and a conductive frame80.

The connecting lead70is disposed outside the distal region F of the display area (corresponding to the second region102of the array substrate100inFIG.10), and the first common signal line(s)30are coupled to the connecting lead70.

The conductive frame80surrounds the display area, the feedback signal line(s)40, the connecting lead70and the portion of the common electrode20located in the distal region F are coupled to the conductive frame80, so that the first common signal line(s)30are coupled to the portion of the common electrode20located in the distal region F through the connecting lead70and the conductive frame80, and the feedback signal line(s)40are coupled to the portion of the common electrode20located in the distal region F through the conductive frame80.

In some embodiments, as shown inFIG.10, the connecting lead70includes at least two connecting lines700, and the at least two connecting lines700are coupled to the conductive frame80.

For example, the conductive frame80may be made of a metal material, such as copper, aluminum, or molybdenum.

Since the material of the common electrode20is different from the material of the first common signal line(s)30, the first common signal line(s)30are coupled to the portion of the common electrode20located in the distal region F through the connecting lead70and the conductive frame80, and the feedback signal line(s)40are coupled to the portion of the common electrode20located in the distal region F through the conductive frame80, which may reduce a contact resistance between the first common signal line30and the common electrode20and a contact resistance between the feedback signal line40and the common electrode20, and may reduce a loss of signal transmission between the first common signal line30and the common electrode20and a loss of signal transmission between the feedback signal line40and the common electrode20.

In some embodiments, as shown inFIG.10, in a case where the array substrate100includes the second common signal line(s)50and the third common signal line(s)60, the second common signal line(s)50and the third common signal line(s)60are coupled to the common electrode20through the conductive frame80. In this case, a contact resistance between the second common signal line50and the common electrode20and a contact resistance between the third common signal line60and the common electrode20may be reduced, and a loss of signal transmission between the second common signal line50and the common electrode20and a loss of signal transmission between the third common signal line60and the common electrode20may be reduced.

In some embodiments, the first common signal line(s)30, the connecting lead70and the conductive frame80are made of a same material and disposed in a same layer.

In this case, the first common signal line(s)30, the connecting lead70and the conductive frame80may be formed synchronously, so that the production processes may be simplified in terms of process.

In some embodiments, in a case where the array substrate100further includes the second common signal line(s)50and the third common signal line(s)60, a resistance of the first common signal line30, a resistance of the second common signal line50, and a resistance of the third common signal line60are all less than or equal to 300Ω. A resistance of the feedback signal line40is less than or equal to 1000Ω.

It will be noted that in a case where the array substrate100is applied to a display apparatus, specific values of the resistances of the first common signal line30, the second common signal line50, the third common signal line60, and the feedback signal line40may be set by a person skilled in the art according to actual conditions (e.g., different resolution and other factors) of the display apparatus.

For example, the resistance (RV1) of the first common signal line30, the resistance (RV2) of the second common signal line50, the resistance (RV3) of the third common signal line60, and the resistance (RVF) of the feedback signal line40satisfy RV1:RV2:RV3:RVF=2:1:2:5. For example, the resistance of the first common signal line30is 200Ω, the resistance of the second common signal line50is 100Ω, the resistance of the third common signal line60is 200Ω, and the resistance of the feedback signal line40is 500Ω.

In some embodiments, as shown inFIG.11, the array substrate100has a plurality of sub-pixel regions P. The common electrode20includes a plurality of sub-electrodes202and a plurality of first conductive patterns201.

A sub-electrode202is located in at least one sub-pixel region P. Adjacent sub-electrodes202are coupled through at least one first conductive pattern201.

In this case, the sub-electrodes202in all the sub-pixel regions P may be connected as a whole through the first conductive patterns201. Therefore, when the first common signal line30transmits the compensated common voltage signal to the sub-electrodes202located in the distal region F, the compensated common voltage signal may be transmitted to all the sub-electrodes202, and common voltage signals of all the sub-electrodes202may be compensated, thereby preventing the common voltage signals of the sub-electrodes202from being delayed.

In some embodiments, as shown inFIG.11, the array substrate100further includes data lines90disposed on the base10.

As shown inFIG.12, the data lines90are arranged closer to the base10than the common electrode20in a direction perpendicular to the base10. Orthogonal projections of the data lines90on the base10at least partially overlap with an orthogonal projection of the common electrode20on the base10.

In some embodiments, in a case where the array substrate100is applied to the display apparatus, as shown inFIG.13, a display apparatus300includes an opposite substrate400disposed opposite to the array substrate100, a liquid crystal layer500disposed between the array substrate100and the opposite substrate400, and a backlight module600disposed on a side of the array substrate100away from the opposite substrate400. The opposite substrate400includes a black matrix (BM).

On this basis, since the orthogonal projection of the data line90on the base10at least partially overlaps with the orthogonal projection of the common electrode20on the base10, an electric field will be formed between the data line90and the common electrode20upon application of power, so that liquid crystal molecules in the liquid crystal layer500rotates under an action of the electric field, which may prevent light emitted from the backlight module600from leaking at a position of the data line90, so as to reduce an area of the black matrix at the position of the data line90, thereby increasing an aperture ratio and facilitating a realization of the narrow bezel of the display apparatus300.

In some embodiments, as shown inFIGS.11and12, the array substrate100further includes a thin film transistor (TFT) disposed in the sub-pixel region P.

As shown inFIG.11, the plurality of sub-pixel regions P may be arranged in an array. Sub-pixel regions P arranged in a row direction X are referred to as sub-pixel regions in a same row, and sub-pixel regions P arranged in a column direction Y are referred to as sub-pixel regions in a same column. The TFTs in the sub-pixel regions in the same row may be electrically connected to a gate line91. The TFTs in the sub-pixel regions in the same column may be electrically connected to the data line90. In this case, a sub-electrode202may correspond to the sub-pixel regions in the same row, and sub-electrodes202in two adjacent rows are coupled through the first conductive pattern201.

In some embodiments, the first common signal line(s)30and the gate line(s)91are made of a same material and disposed in a same layer. Therefore, the first common signal line(s)30and the gate line(s)91may be formed synchronously in terms of process.

In addition, in some embodiments, as shown inFIGS.11and12, the array substrate100further includes pixel electrodes21disposed on a side of the common electrode20proximate to the base10. The TFT includes a gate12, an active layer16, and a source13and a drain14that are disposed on the base10in sequence. A pixel electrode21is coupled to the drain14of the TFT through a second conductive pattern17, and the second conductive pattern17and the common electrode20are made of a same material and disposed in a same layer. The array substrate100further includes a semiconductor pattern22, the semiconductor pattern22is located on a side of the data line90proximate to the base10, and the semiconductor pattern22and the active layer16of the TFT are made of a same material and disposed in a same layer.

In terms of process, referring toFIGS.11and12, the pixel electrode21is formed on the base10; the gate12and the active layer16of the TFT are sequentially formed on a side of the pixel electrode21away from the base; the source13and the drain14are formed on a side of the active layer16away from the base10by using a single slit mask (SSM); a passivation layer11is formed on a side of the TFT away from the base10; and the common electrode20is formed on a side of the passivation layer11away from the base10.

The embodiments of the present disclosure further provide the display apparatus300. As shown inFIG.14, the display apparatus300includes the array substrate100in any of the above embodiments and a circuit board200.

The circuit board200is bonded to the bonding region B in the array substrate100.

The circuit board200includes a control circuit210, and the control circuit210is coupled to the first common signal line30and the feedback signal line40in the array substrate100.

The control circuit210is configured to generate a first compensation common voltage signal according to the common voltage signal transmitted by the feedback signal line40, and transmit the first compensation common voltage signal to the first common signal line30.

It will be understood that the first compensation common voltage signal is obtained after the control circuit210compensates for the common voltage signal according to the common voltage signal.

The feedback signal line40and the first common signal line30are coupled to the portion of the common electrode20located in the distal region F.

For example, the circuit board200may be a printed circuit board (PCB) or a flexible printed circuit (FPC) board or the like.

Therefore, the first compensation common voltage signal generated by the control circuit210according to the common voltage signal transmitted by the feedback signal line40is transmitted to the portion of the common electrode20located in the distal region F through the first common signal line30, so as to compensate for the common voltage signal of the portion of the common electrode20located in the distal region F. As a result, the delay in the common voltage signal of the portion of the common electrode20located in the distal region F may be avoided, thereby improving the display effect.

In some embodiments, as shown inFIG.15, the control circuit210includes an inverter211and a first operational amplifier212.

The inverter211is coupled to the feedback signal line40.

The first operational amplifier212is coupled to the inverter211and the first common signal line30.

The inverter211is configured to invert the common voltage signal transmitted by the feedback signal line40.

The first operational amplifier212is configured to amplify an inverted signal from the inverter211to generate the first compensation common voltage signal, and transmit the first compensation common voltage signal to the first common signal line30.

On this basis, the common voltage signal transmitted by the feedback signal line40(i.e., the common voltage signal of the portion of the common electrode20located in the distal region F) is distorted and potential drift occurs. After the common voltage signal is inverted by the inverter211and amplified by the first operational amplifier212, the generated first compensation common voltage signal may compensate for the distorted common voltage signal of the portion of the common electrode20located in the distal region F, thereby avoiding the delay in the common voltage signal of the portion of the common electrode20located in the distal region F.

For example, as shown inFIG.16, the inverter211includes an N-type transistor TNand a P-type transistor TP. A control electrode of the N-type transistor TNis coupled to a first input terminal IN1, a first electrode of the N-type transistor TNis coupled to a first voltage terminal VSS, and a second electrode of the N-type transistor TNis coupled to a first output terminal Out1. A control electrode of the P-type transistor TPis coupled to the first input terminal IN1, a first electrode of the P-type transistor TPis coupled to a second voltage terminal VDD, and a second electrode of the P-type transistor TPis coupled to the first output terminal Out1.

The first input terminal IN1is coupled to the feedback signal line40, and the first output terminal Out1is coupled to the first operational amplifier212.

A voltage of the first voltage terminal VSS and a voltage of the second voltage terminal VDD are each an operating voltage of the inverter211. When the inverter211is operating, the voltage of the first voltage terminal VSS is at a direct current low level and may be used as a negative electrode of a power supply, and the voltage of the second voltage terminal VDD is at a direct current high level and may be used as a positive electrode of the power supply.

In this case, when a voltage of the common voltage signal transmitted by the feedback signal line40makes the N-type transistor TNturned on, the P-type transistor TPis turned off, the common voltage signal is a high-level signal, the N-type transistor TNtransmits a first voltage signal received from the first voltage terminal VSS to the first output terminal Out1, and a signal of the first output terminal Out1is a low-level signal, which realizes an inversion of the common voltage signal. Similarly, when the voltage of the common voltage signal transmitted by the feedback signal line40makes the P-type transistor TPturned on, the N-type transistor TNis turned off, the common voltage signal is a low-level signal, the P-type transistor TPtransmits a second voltage signal received from the second voltage terminal VDD to the first output terminal Out1, and the signal of the first output terminal Out1is a high-level signal, which realizes an inversion of the common voltage signal.

For example, as shown inFIG.16, the first operational amplifier212includes a first amplifier OP1, a first resistor R1, a second resistor R2, and a third transistor R3.

A positive input terminal of the first amplifier OP1is coupled to a second end of the third resistor R3, a negative input terminal of the first amplifier OP1is coupled to a first end of the first resistor R1and a first end of the second resistor R2, and an output terminal of the first amplifier OP1is coupled to a first compensation common voltage signal output terminal Outf1.

A second end of the first resistor R1is grounded.

A second end of the second resistor R2is coupled to the first compensation common voltage signal output terminal Outf1.

A first end of the third resistor R3is coupled to a second input terminal IN2.

The second input terminal IN2is coupled to the first output terminal Out1of the inverter211, and the first compensation common voltage signal output terminal Outf1is coupled to the first common signal line20.

The third resistor R3is a balance resistor, and the resistance of R3is the resistance of R1and R2in parallel, i.e., R3=R1//R2, which may avoid an influence of an input bias current of the first operational amplifier212on an output.

It will be understood that a signal VIN2received at the second input terminal IN2is an inverted signal from the inverter211, and the inverted signal is an inversion of the common voltage signal. In this case, a first compensation common voltage signal Vf1generated by the first operational amplifier212is equal to (1+R2/R1) by VIN2, i.e., Vf1=(1+R2/R1)×VIN2, and an amplification factor of the first operational amplifier212is (1+R2/R1).

It will be noted that those skilled in the art may set the amplification factor of the first operational amplifier212according to actual conditions (e.g., different resolution, etc.), and select the first resistor R1and the second resistor R2with suitable resistance values according to a required amplification factor.

In some embodiments, as shown inFIG.17, in a case where the array substrate100further includes the second common signal line(s)50, the control circuit210further includes a second operational amplifier213.

The second operational amplifier213is coupled to the inverter211and the second common signal line50. The second operational amplifier213is configured to amplify the inverted signal from the inverter211to generate a second compensation common voltage signal, and transmit the second compensation common voltage signal to the second common signal line50.

An amplification factor of the second operational amplifier213is less than the amplification factor of the first operational amplifier212.

On this basis, the common voltage signal transmitted by the feedback signal line40(i.e., the common voltage signal of the portion of the common electrode20located in the distal region F) is distorted and potential drift occurs. Since a delay degree of the common voltage signal of the portion of the common electrode20located in the proximal region N is less than a delay degree of the common voltage signal of the portion of the common electrode20located in the distal region F, the second compensation common voltage signal generated by the second operational amplifier213amplifying the inverted signal may compensate for the distorted common voltage signal of the portion of the common electrode20located in the proximal region N, thereby avoiding the delay in the common voltage signal of the portion of the common electrode20located in the proximal region N.

For example, as shown inFIG.18, the second operational amplifier213includes a second amplifier OP2, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.

A positive input terminal of the second amplifier OP2is coupled to a second end of the sixth resistor R6, a negative input terminal of the second amplifier OP2is coupled to a first end of the fourth resistor R4and a first end of the fifth resistor R5, and an output terminal of the second amplifier OP2is coupled to a second compensation common voltage signal output terminal Outf2.

A second end of the fourth resistor R4is grounded.

A second end of the fifth resistor R5is coupled to the second compensation common voltage signal output terminal Outf2.

A first end of the sixth resistor R6is coupled to the second input terminal IN2. The second compensation common voltage signal output terminal Outf2is coupled to the second common signal line50.

The sixth resistor R6is a balance resistor, and the resistance of R6is the resistance of R4and R5in parallel, i.e., R6=R4//R5, which may avoid an influence of an input bias current of the second operational amplifier213on an output.

In this case, a second compensation common voltage signal Vf2generated by the second operational amplifier213is equal to (1+R5/R4) by VIN2, i.e., Vf2=(1+R5/R4)×VIN2, and the amplification factor of the second operational amplifier213is (1+R5/R4).

It will be noted that those skilled in the art may set the amplification factor of the second operational amplifier213according to actual conditions (e.g., different resolution, etc.), and select the fourth resistor R4and the fifth resistor R5with suitable resistance values according to a required amplification factor.

In some embodiments, as shown inFIG.19, in a case where the array substrate100further includes the third common signal line(s)60, the control circuit210further includes a third operational amplifier214.

The third operational amplifier214is coupled to the inverter211and the third common signal line60. The third operational amplifier214is configured to amplify the inverted signal from the inverter211to generate a third compensation common voltage signal, and transmit the third compensation common voltage signal to the third common signal line60.

An amplification factor of the third operational amplifier214is less than the amplification factor of the first operational amplifier212.

In a case where the control circuit210further includes the second operational amplifier213, the amplification factor of the third operational amplifier214is greater than the amplification factor of the second operational amplifier213.

On this basis, the common voltage signal transmitted by the feedback signal line40(i.e., the common voltage signal of the portion of the common electrode20located in the distal region F) is distorted and potential drift occurs. Since a delay degree of the common voltage signal of the portion of the common electrode20located in the middle region M is less than the delay degree of the common voltage signal of the portion of the common electrode20located in the distal region F, and is greater than the delay degree of the common voltage signal of the portion of the common electrode20located in the proximal region N, the third compensation common voltage signal generated by the third operational amplifier214amplifying the inverted signal may compensate for the distorted common voltage signal of the portion of the common electrode20located in the middle region M, thereby avoiding the delay in the common voltage signal of the portion of the common electrode20located in the middle region M.

For example, as shown inFIG.20, the third operational amplifier214includes a third amplifier OP3, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.

A positive input terminal of the third amplifier OP3is coupled to a second end of the ninth resistor R9, a negative input terminal of the third amplifier OP3is coupled to a first end of the seventh resistor R7and a first end of the eighth resistor R8, and an output terminal of the third amplifier OP3is coupled to a third compensation common voltage signal output terminal Outf3.

A second end of the seventh resistor R7is grounded.

A second end of the eighth resistor R8is coupled to the third compensation common voltage signal output terminal Outf3.

A first end of the ninth resistor R9is coupled to the second input terminal IN2.

The third compensation common voltage signal output terminal Outf3is coupled to the third common signal line60.

The ninth resistor R9is a balance resistor, and the resistance of R9is the resistance of R7and R8in parallel, i.e., R9=R7//R8, which may avoid an influence of an input bias current of the third operational amplifier214on an output.

In this case, a third compensation common voltage signal Vf3generated by the third operational amplifier214is equal to (1+R8/R7) by VIN2, i.e., Vf3=(1+R8/R7)×VIN2. The amplification factor of the third operational amplifier214is (1+R8/R7).

It will be noted that relationships among the amplification factors of the first operational amplifier212, the second operational amplifier213, and the third operational amplifier214in different display apparatuses are all different. Ranges of the amplification factor of the first operational amplifier212, the amplification factor of the second operational amplifier213, and the amplification factor of the third operational amplifier214may be determined according to actual conditions of the display apparatus, such as the resolution and pixel structures. In addition, resistance values of the first resistor R1and the second resistor R2in the first operational amplifier212, resistance values of the fourth resistor R4and the fifth resistor R5in the second operational amplifier213, and resistance values of the seventh resistor R7and the eighth resistor R8in the third operational amplifier214are set in advance through multiple experiments and tests on the display apparatus before delivery.

In addition, the display apparatus300may be any apparatus that can display images whether in motion (e.g., a video) or stationary (e.g., a static image), and regardless of text or image. More specifically, it is anticipated that the described embodiments may be implemented in or associated with a variety of electronic devices. The variety of electronic devices may be (but not limited to), e.g., a mobile phone, a wireless device, a personal data assistant (PDA), a hand-held or portable computer, a global positioning system (GPS) receiver/navigator, a camera, an MPEG-4 Part 14 (MP4) video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, a car display (e.g., an odometer display), a navigator, a cockpit controller and/or display, a display of camera view (e.g., a display of a rear view camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a building structure, and a packaging and an aesthetic structure (e.g., a display for an image of a piece of jewelry).

On the basis of the above, the embodiments of the present disclosure further provide a control method of the display apparatus300as described in any of the above embodiments, including:transmitting, by the feedback signal line40, the common voltage signal of the portion of the common electrode20located in the distal region F to the control circuit210in the circuit board200; andgenerating, by the control circuit210, the first compensation common voltage signal according to the common voltage signal transmitted by the feedback signal line40, and transmitting, by the control circuit210, the first compensation common voltage signal to the first common signal line30, so as to compensate for the common voltage signal of the portion of the common electrode20located in the distal region F.

In some embodiments, the control method of the display apparatus300further includes:generating, by the control circuit210, the second compensation common voltage signal according to the common voltage signal transmitted by the feedback signal line, and transmitting, by the control circuit210, the second compensation common voltage signal to the second common signal line50, so as to compensate for the common voltage signal of the portion of the common electrode20located in the proximal region N.

In some embodiments, the control method of the display apparatus300further includes:generating, by the control circuit210, the third compensation common voltage signal according to the common voltage signal transmitted by the feedback signal line40, and transmitting, by the control circuit210, the third compensation common voltage signal to the third common signal line60, so as to compensate for the common voltage signal of the portion of the common electrode20located in the middle region M.

Beneficial effects that may be achieved by the control method of the display apparatus300provided by the embodiments of the present disclosure are the same as beneficial effects of the above display apparatus300, and will not be repeated here.

The foregoing descriptions are merely specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or replacements that a person skilled in the art could conceive of within the technical scope of the present disclosure shall be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.