Patent ID: 12256551

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when it is powered, while non-volatile memory (NVM) generally refers to any memory or storage that can retain stored data even when no power is applied. Example NVM includes flash memory, and flash memory includes two main types: NAND-type memory and NOR-type memory. The NAND-type memory has an advantage of a high-density structure including a number of storage transistors series-connected to form strings. However, reading and writing the content of any of the series-connected storage transistor requires activation of all series-connected storage transistors in one string, results in slow read/write access speed. Therefore, a memory structure complying with high-speed requirement in AI and high bandwidth memory, and high density requirements is needed. Existing 3D NAND-type memory bases on charge-trapping memory (CTM), which uses traps in insulating layers to store charge, instead of floating gates. Consequently, charge number needed for programming and erasing is reduced, resulting faster write speed and less write power consumption.

In some embodiments, a ferroelectric FET (FeFET), which provides a field-switching based storage instead of a charge-based storage, can be used in the 3D NAND-type memory. Further, FeFET is more scalable. The FeFET includes a ferroelectric layer, where dipoles, which are bonded, immobile “charges”, are formed. The dipoles flip under electric field generated by potential difference, which refers to voltage drop across the channel and the gate stack. In some embodiments, positive voltage is applied on the gate of the FeFET for programming, and negative voltage is applied on the gate of the FeFET for erasing.

In some embodiments, when the FeFET includes a channel layer that including materials such as intrinsically strong N type material or intrinsically strong P type material, the FeFET has difficulty in erasing or programming. In other words, memory wind (MW) is decreased. In some comparative approaches, voltages for programming and erasing are increase to overcome the small MW issue. However, it raises reliability issue: The gate of Fe FET may breakdown in cycles fewer than expected.

The present disclosure therefore provides a semiconductor memory structure and a method for forming the same that is able to improve erasing operation efficiency and thus mitigate the small MW issue. In some embodiments, doped regions are formed in the substrate on which the 3D memory array is stacked. Accordingly, NPN junctions or PNP junctions are formed by the substrate and the doped region. The NPN junctions or PNP junctions are able to provide charge carriers (hereinafter referred to as carriers) into the channel layer. Further, the carriers are injected into the channel layer, and thus an inversion layer may be formed in the channel layer. In some embodiments, the inversion layer helps to screen electric field toward the channel layer. Therefore, the electric fields generated to flip dipoles can be concentrated in the ferroelectric layer. Thus erasing and programming operation efficiency can be improved.

FIG.1is a flowchart representing a method10for forming a semiconductor memory structure according to aspects of the present disclosure. In some embodiments, the method10includes a number of operations (101,102,103,104,105,106,107and108) and is further described below according to one or more embodiments. It should be noted that the operations of the method10may be omitted, rearranged, or otherwise modified within the scope of the various aspects. It should further be noted that additional operations may be provided before, during, and after the method10, and that some other operations may just be briefly described herein.

Referring toFIG.2AandFIG.2B, in operation101, the method10forms a plurality of doped regions204in a semiconductor substrate202(hereinafter referred to as substrate202). In some embodiments, the substrate202is a silicon substrate. In some embodiments, the substrate202includes germanium, an alloy semiconductor (for example, SiGe), another suitable semiconductor material, or combinations thereof. In other embodiments, the substrate202is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. In some embodiments, the substrate202can include various devices, such as CMOS devices, though not shown.

In some embodiments, the substrate202includes dopants of first conductivity type. For example, the substrate202may include p-type dopants such as boron, indium, another p-type dopant, or a combination thereof. Alternatively, the substrate202may include n-type dopants such as phosphorus, arsenic, another n-type dopant, or a combination thereof. In some embodiments, a concentration of the dopants of the first conductivity type in the substrate202may be between approximately 1E15 ions/cm3and approximately 1E17 ions/cm3, but the disclosure is not limited thereto.

Still referring toFIGS.2A and2B, in some embodiments, the doped regions204may be formed in the substrate202by ion implantation and anneal. Each of the doped regions204includes dopants of a second conductivity type, which is complementary to the first conductivity type. For example, when the substrate202includes the p-type dopants, the doped regions204include the n-type dopants. Alternatively, when the substrate202includes the n-type dopants, the doped regions204include the p-type dopants. In some embodiments, a concentration of the dopants of the second conductivity type in the doped regions204is greater than the concentration of the dopants of the first conductivity type in the substrate202. In some embodiments, the concentration of the dopants of the second conductivity type in each of the doped regions204is between approximately 1E18 ions/cm3and approximately 1E20 ions/cm3, but the disclosure is not limited thereto.

As shown inFIGS.2A and2B, the doped regions204are formed in the substrate202, and sidewalls and a bottom surface of each doped region204may be in contact with the substrate202. In other words, the doped regions204can be referred to as island-like features separated from each other in the substrate202. In some embodiments, the doped regions204are arranged in an array pattern. In some embodiments, the doped regions204are arranged in a staggered array pattern, as shown inFIG.2A, but the disclosure is not limited thereto. In some embodiments, the doped regions204are formed in a cell array region CA where a memory cell array is to be formed, but the disclosure is not limited thereto.

Referring toFIGS.3A and3B, in operation102, the method10forms a stack210over the substrate202. In some embodiments, the stack210includes a plurality of first insulating layers212and a plurality of second insulating layers214. Further, the first insulating layers212and the second insulating layers214are alternately arranged. The number of the alternating layers212and214included in the stack210can be made as high as the number of layers needed for the semiconductor memory device. Further, in some embodiments, the topmost layer and the bottommost layer may both be the first insulating layers212, as shown inFIGS.3A and3B, but the disclosure is not limited thereto. Thicknesses of the first insulating layers212and thicknesses of the second insulating layers214may be similar or different, depending on different product requirements. In some embodiments, the first insulating layers212and the second insulating layers214include different materials. Fox example, the first insulating layers212may include silicon oxide, and the second insulating layers214may include silicon nitride, but the disclosure is not limited thereto.

Referring toFIGS.4A and4B, portions of the first insulating layers212and portions of the second insulating layers214are removed, such that remaining first insulating layers212and remaining second insulating layers214over the substrate202form a staircase configuration. In some embodiments, portions of the second insulating layers214are exposed, and areas of the exposed second insulating layers214may be similar. In some embodiments, the remaining topmost first insulating layer212can be used to define a location and a dimension of a cell array region CA, which will be described below.

Referring toFIGS.5A and5B, in some embodiments, a dielectric structure220may be formed over the substrate202. Further, a top surface of the dielectric structure220can be aligned with a top surface of the topmost first insulating layer212, as shown inFIG.5A. Consequently, an even and flush surface can be obtained.

Referring toFIGS.6A and6B, in operation103, the method10forms a trench221in the dielectric structure220and the stack210. In some embodiments, the trench221extends along a first direction D1. In some embodiments, a plurality of trenches221may be formed in the dielectric structure220and the stack210. As shown inFIG.6A, the trenches221extend along the first direction D1, and are arranged along a second direction D2, which is different from the first direction D1. In some embodiments, the first direction D1and the second direction D2are perpendicular with each other. Each of the trenches221may penetrate the dielectric structure220and the stack210(i.e., the remaining first and second insulating layers212and214in the staircase configuration). Further, depths of the trenches221are similar with each other. In some embodiments, the trenches221are formed offset from the doped regions204. Further, a width of the trenches221may be less than a distance between adjacent two doped regions204. Thus, the substrate202may be exposed through a bottom of each trench221, as shown inFIGS.6A and6B, but the disclosure is not limited thereto. In some embodiments, the first insulating layer layers212and the second insulating layers214may be exposed through two opposite sidewalls of each trench221.

Referring toFIGS.7A and7B, in some embodiments, in operation104, the method10replaces the second insulating layers214with a plurality of conductive layers216. In some embodiments, portions of the second insulating layers214may be removed to form a plurality of recesses (not shown), which extend along the second direction D2into the stack210. In some embodiments, an etchant which has a higher selectivity for the second insulating layers214than the first insulating layers212may be introduced into the trenches221. Accordingly, the portions of the second insulating layers214are removed to form the recesses between the first insulating layers212, though not shown. A conductive material can be formed to fill the recesses and to form the conductive layer216. In some embodiments, the conductive material may include, for example but not limited thereto, titanium nitride and tungsten (TiN/W), titanium nitride and copper (TiN/Cu), tantalum nitride and copper (TaN/Cu), cobalt and tungsten (Co/W), ruthenium (Ru), or other suitable conductive materials. In some embodiments, a barrier layer and/or an adhesive layer218may be formed prior to the forming of the conductive material, as shown inFIGS.7A and7B, but the disclosure is not limited thereto. In some embodiments, the conductive layer216may fill each of the recesses and cover sidewalls of each trench221, as shown inFIG.7B. Further, after the forming of the conductive layers216, a sacrificial layer219may be formed to fill the trenches221. The sacrificial layer219may include insulating materials different from the second insulating layers214, but the disclosure is not limited thereto. In some embodiments, a planarization operation such as a chemical-mechanical polishing (CMP) operation can be performed to remove superfluous barrier layer218, conductive layers216and sacrificial layer219. Consequently, a top surface of the conductive layers216, a top surface of the sacrificial layer219and a top surface of the topmost first insulating layer212are aligned with each other (i.e., substantially co-planar), as shown inFIG.7B.

Referring toFIGS.8A,8B,9A and9B, in some embodiments, the operations103and104can be repeatedly performed to replace the second insulating layers214with the conductive layers216, which may serve as gate layers for the semiconductor memory structure to be formed. For example, a plurality of trenches223may be formed in the dielectric structure220and the stack210. As shown inFIG.8A, the trenches223extend along the first direction D1, and are arranged along the second direction D2. Further, depths of the trenches223are similar with each other. Similar to the trenches221, each of the trenches223may penetrate the dielectric structure220and the stack210(i.e., the remaining first and second insulating layers212and214in staircase configuration). Further, dimensions of the trenches223are similar to that of the trenches221. It should be noted that the trenches223and the trenches221(now filled with the barrier layer218, the conductive layer216and the sacrificial layer219) are alternately arranged. In some embodiments, the trenches223are formed offset from the doped regions204. Further, a width of the trenches223may be less than the distance between adjacent two doped regions204. Thus, the substrate202may be exposed through a bottom of each trench223, as shown inFIGS.8A and8B, but the disclosure is not limited thereto. In some embodiments, the first insulating layer layers212and the second insulating layers214may be exposed through two opposite sidewalls of each trench223.

Referring toFIGS.9A and9B, in some embodiments, in operation104, the method10replaces the second insulating layers214, which are exposed through sidewalls of the trenches223, with a plurality of conductive layers216. As mentioned above, portions of the second insulating layers214may be removed to form a plurality of recesses (not shown), which extend along the second direction D2into the stack210. In some embodiments, an etchant which has a higher selectivity for the second insulating layers214than the first insulating layers212can be introduced into the first trenches212. Accordingly, the portions of the second insulating layers214are removed to form the recesses between the first insulating layers212, though not shown. The conductive material may be formed to fill the recesses and to form the conductive layer216. In some embodiments, a barrier layer and/or an adhesive layer218may be formed prior to the forming of the conductive material, as shown inFIGS.9A and9B, but the disclosure is not limited thereto. In some embodiments, the conductive layer216may fill each of the recesses and cover sidewalls of each trench223, as shown inFIG.9B. Further, after the forming of the conductive layers216, a sacrificial layer219may be formed to fill the trenches223. In some embodiments, a planarization operation such as a CMP operation may be performed to remove superfluous barrier layer218, conductive layers216and sacrificial layer219. Consequently, a top surface of the conductive layers216, a top surface of the sacrificial layer219and a top surface of topmost the first insulating layer212are aligned with each other (i.e., substantially co-planar), as shown inFIG.9B.

Referring toFIGS.10A and10B, in operation105, the method10forms another trench225. In some embodiments, a plurality of trenches225can be formed, the trenches225can extend along the first direction D1and arranged along the second direction D2, but the disclosure is not limited thereto. In some embodiments, the sacrificial layer219and portions of the conductive layers216may be removed to form the trenches225. For example, the sacrificial layer219may be entirely removed, and portions of the conductive layers216are removed to expose the substrate202through bottoms of the trenches225, as shown inFIGS.10A and10B, but the disclosure is not limited thereto. Further, depths of the trenches225are similar with each other. In some embodiments, the trenches225are formed offset from the doped regions204. Further, a width of the trenches225may be less than a distance between two adjacent doped regions204. In some embodiments, remaining conductive layers216may be exposed through sidewalls of the trenches225.

Referring toFIGS.11A and11B, in operation106, the method10forms a charge-trapping layer242and a channel layer244in each trench225. In some embodiments, the charge-trapping layer242can be referred to as a memory layer. The charge-trapping layer242may be conformally formed in each trench225by, for example but not limited thereto, a deposition. Therefore, the charge-trapping layer242covers the sidewalls and the bottom of each trench225. Further, a bottom surface of the charge-trapping layer242is in contact with the substrate202but separated from the doped regions204. In some embodiments, the charge-trapping layer242includes ferroelectric material, such as hafnium silicates (HfSiO), hafnium zirconium oxide (HfZrO, also referred to as HZO), and the like.

Still referring toFIGS.11A and11B, in some embodiments, the channel layer244is formed on the charge-trapping layer242. In some embodiments, the channel layer224exposes the charge-trapping layer242over the bottoms of the trenches225but covers the charge-trapping layer242over the sidewalls of the trenches225. Additionally, the channel layer244is separated from the substrate202by the charge-trapping layer242. In some embodiments, the channel layer244may include semiconductor materials.

Referring toFIGS.12A and12B, in operation107, the method10forms an isolation structure252in each trench225after the forming of the charge-trapping layer242and the channel layer244. In some embodiments, the isolation structure252may be formed by filling each second trench223with a dielectric material, such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, and the like. The dielectric material may be used to fill up the trenches225and covers top surface of the stack210and dielectric structure220. A planarization operation such as a CMP may be performed to remove superfluous dielectric material to form the isolations structure252. Accordingly, a top surface of the isolation structure252, the top surface of the dielectric structure220, the top surface of the topmost first insulating layer212, a topmost surface of the charge-trapping layer242, and a topmost surface of the channel layer244may be aligned with each other.

Referring toFIGS.13A,13B,14A and14B, in operation108, the method10forms a source structure254S and a drain structure254D at two sides of the isolation structure252. In some embodiments, portions of the isolation structure252and portions of the channel layer244are removed. Accordingly, a plurality of recesses251are formed in the cell array region CA. In some embodiments, dimensions and depth of the recesses251are the same. Further, the channel layer244may be exposed through two opposite sidewalls of each recess251, while the charge-trapping layer242may be exposed through a bottom of each recess251. In the cell array region CA, the recesses251may be arranged to form a staggered pattern, but the disclosure is not limited thereto. In some embodiments, the recesses251are formed offset from the doped regions204. Further, a width of each recess251is less than the distance between adjacent two doped regions204.

Referring toFIGS.14A and14B, the source structure254S and the drain structure254D are respectively formed in the recesses251. In some embodiments, a barrier layer (not shown) can be formed to cover sidewalls and a bottom of each recess251, and then the recesses251are filled with a conductive material. A planarization operation such as a CMP operation is performed to remove superfluous barrier layer and conductive material. Consequently, the source structure254S and the drain structure254D are formed at the two sides of the isolation structure252. In some embodiments, the conductive material can include doped polysilicon, doped amorphous silicon, tungsten, copper, and the like. In some embodiments, a plurality of stacked memory cells Mc may be formed in the cell array region CA after the forming the of source structure254S and the drain structure254D.

Still referring toFIGS.14A and14B, accordingly, a semiconductor memory structure200is obtained. The semiconductor memory structure200includes the substrate202, the doped regions204in the substrate202and separated from each other by the substrate202, and the plurality of conductive layers216and the first insulating layers212alternately stacked over the substrate202. The semiconductor memory structure200further includes a plurality of columns250disposed over the substrate202. As shown inFIGS.14A and14B, the columns250penetrate the stack210including the alternating conductive layers216and first insulating layers212. Further, each of the columns250includes an isolation structure252, a source structure254S and a drain structure254D. As shown inFIG.14A, the source structure254S and the drain structure254D are disposed at two opposite sides of the isolation structure252. The semiconductor memory structure200further includes a charge-trapping layer242disposed at two sides of each column250, and a channel layer244between the charge trapping layer242and each column250.

In some embodiments, the columns250are arranged to form an array pattern. In some embodiments, the columns250are arranged to form a staggered array pattern, as shown inFIG.14A, but the disclosure is not limited thereto. Each of the columns250is offset from the doped regions204. Further, a width of each column250is less than the distance between adjacent two doped regions204. Further, as shown inFIG.14B, the columns250are separated from the substrate202by the charge-trapping layer242. Additionally, the channel layer244is also separated from the substrate202by the charge-trapping layer242.

Referring toFIG.15, which is an enlarged view of a portion of the semiconductor memory structure200, each of the columns250includes a plurality of memory cells Mc. Further, each of the memory cells Mc includes a conductive layer216(serving as a gate layer), a portion of the charge-trapping layer242, a portion of the channel layer244, a portion of the source structure254S and a portion of the drain structure254D.

As mentioned above, the doped regions204include dopants of the second conductivity type, which is complementary to the dopants of the first conductivity type in the substrate202, therefore, an NPN junction or a PNP junction may be formed by the doped regions204and the substrate202. In some embodiments, an NPN junction or a PNP junction may be formed by the doped regions204and the substrate202.

Referring toFIGS.16and17, which are schematic drawings illustrating the memory cell Mc in the programming operation and the erasing operation, respectively. Referring toFIG.16, during the programming operation, positive voltage is applied to the conductive layer216(i.e., VWL>0), electrons are accumulated in the channel layer244, and the memory cell Mc is in On state. Referring toFIG.17, during the erasing operation, negative voltage is applied to the conductive layer216(i.e., VWL<0), electrons are depleted, and the memory cell Mc is in Off state. In some embodiments, when the doped regions204and the substrate202form the NPN or N+PN+ junction, the NPN junction or the N+PN+ junction helps to inject the carriers, such as holes into the channel layer244. Further, an inversion layer may be formed in the channel layer244due to the carrier injection. In some embodiments, the inversion layer helps to screen electric field toward the channel layer242. Therefore, the electric fields generated to flip dipoles can be concentrated in the ferroelectric layer242. Thus, at least the erasing operation efficiency can be improved. Additionally, when the doped regions204and the substrate202form PNP junction, the PNP junction helps to inject charge carriers, such as electrons into the channel layer244.

Accordingly, the present disclosure provides a semiconductor memory structure and a method for forming the same that is able to improve erasing operation efficiency and thus mitigate the small MW issue. In some embodiments, the doped regions are formed in the substrate on which the 3D memory array is stacked. Accordingly, NPN junctions or PNP junctions are formed by the substrate and the doped region. The NPN junctions or PNP junctions are able to provide carriers. As mentioned above, the carriers are injected into the channel layer, thereby an inversion layer that is able to help to screen electric field toward the channel layer may be formed. Accordingly, the electric fields generated to flip dipoles can be concentrated in the ferroelectric layer. Thus erasing and programming operation efficiency can be improved, and the small MW issue can be mitigated.

In some embodiments, a method for forming a semiconductor memory structure is provided. The method includes following operations. A plurality of doped regions are formed in a semiconductor substrate. The doped regions are separated from each other. A stack including a plurality of first insulating layers and a plurality of second insulating layers alternately arranged is formed over the semiconductor substrate. A first trench is formed in the stack. The second insulating layers are replaced with a plurality of conductive layers. A second trench is formed. A charge-trapping layer and a channel layer are formed in the second trench. An isolation structure is formed to fill the second trench. A source structure and a drain structure are formed at two sides of the isolation structure.

In some embodiments, a method for forming a semiconductor memory structure is provided. The method includes following operations. A semiconductor substrate is received. The semiconductor substrate includes a plurality of doped regions separated from each other. A stack including a plurality of first insulating layers and a plurality of conductive layers are formed over the semiconductor substrate. The first insulating layers and the second insulating layers are alternately arranged. A trench is formed in the stack. A charge-trapping layer and a channel layer are formed in the trench. An isolation structure is formed to fill the trench. A source structure and a drain structures are formed at two sides of the isolation structure.

In some embodiments, a method for forming a semiconductor memory structure is provided. The method includes following operations. A semiconductor substrate is received. The semiconductor substrate includes at least a doped region. A stack is formed over the semiconductor substrate. The stack includes a plurality of first insulating layers and a plurality of conductive layers alternately arranged. A first trench is formed in the stack. A charge-trapping layer and a channel layer are formed in the first trench. The charge-trapping layer is in contact with the semiconductor substrate and separated from the doped region. An isolation structure is formed to fill the first trench. A first recess and a second recess separated from each other are formed in the isolation structure. A source structure is formed in the first recess, and a drain structure is formed in the second recess.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.