Patent ID: 12211949

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, “around,” “about,” “approximately,” or “substantially” shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated. One of ordinary skill in the art will appreciate that the dimensions may be varied according to different technology nodes. One of ordinary skill in the art will recognize that the dimensions depend upon the specific device type, technology generation, minimum feature size, and the like. It is intended, therefore, that the term be interpreted in light of the technology being evaluated.

The advanced lithography process, method, and materials described in the current disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs can be processed according to the above disclosure.

The present disclosure is related to semiconductor detectors, methods of forming the same, and methods of using the same. More particularly, some embodiments of the present disclosure are related to high-density and powerless semiconductor detectors for detecting e-beam lights. In some embodiments, the semiconductor detectors may be realized on the device including planar devices, multi-gate devices, FinFETs, nanosheet-gate FETs, and gate-all-around FETs.

FIG.1is a perspective view of a semiconductor detector in accordance with some embodiments, andFIG.2is a schematic circuit diagram illustrating the semiconductor detector ofFIG.1according to some embodiments of the present disclosure. The semiconductor detector inFIGS.1and2may include a single cell unit100. The (cell unit100of the) semiconductor detector includes a substrate110, at least one active region, an isolation structure130, a gate structure140, a first source/drain structure150, a second source/drain structure155, at least one reading contact160, at least one sensing contact170, and a sensing pad structure180. The active region may be a semiconductor fin120protruding from the substrate110. It is noted that although there are four semiconductor fins120inFIG.1, the claimed scope of the present disclosure is not limited in this respect. In some other embodiments, a person having ordinary skill in the art can manufacture suitable number of the semiconductor fins120of the semiconductor detector according to actual situations.

The isolation structure130is over the substrate110and laterally surrounds the semiconductor fins120. That is, bottom portions of the semiconductor fins120are embedded in the isolation structure130. The isolation structure130may be shallow trench isolation (STI) regions.

The gate structure140is over the isolation structure130and crosses the semiconductor fins120. Portions of the semiconductor fins120covered by the gate structure140are referred to as channel portions of the semiconductor fins120. In some embodiments, there is no electrically conductive element physically connected to the gate structure140, such that the gate structure140can be referred to as a floating gate.

The first source/drain structure150and the second source/drain structure155are over the semiconductor fins120and are on opposite sides of the gate structure140. As such, one of the first source/drain structure150and the second source/drain structure155serves as a source terminal and another one of the first source/drain structure150and the second source/drain structure155serves as a drain terminal. Portions of the semiconductor fins120under the first source/drain structure150and portions of the semiconductor fins120under the second source/drain structure155are referred to as source/drain portions of the semiconductor fins120.

Two reading contacts160are adjacent to the gate structure140and directly on the isolation structure130, such that the two reading contacts160are spaced apart from the semiconductor fins120. The reading contacts160are on opposite sides of the gate structure140and are further spaced apart from the first source/drain structure150and the second source/drain structure155. The reading contacts160are separated from the gate structure140by a dielectric material (e.g., the gate spacers550, the CESL560, and/or the ILD layer565inFIG.15A). As such, the gate structure140, the reading contact160, and the dielectric material therebetween form a capacitance. A distance D1is formed between the reading contact160and the gate structure140, and each of the reading contacts160has an inner surface161facing the gate structure140. A coupling ratio between the gate structure140and the reading contact160is determined at least by the distance D1and an area of the inner surface161of the reading contact160. In some embodiments, the coupling ratio between the gate structure140and the reading contact160is in a range of about 10% to about 50%. Further, the distance D1may be smaller than a width W of the first source/drain structure150. In some embodiments, (the cell unit100of) the semiconductor detector includes a single reading contact160on one side of the gate structure140.

Two sensing contacts170are adjacent to the gate structure140and directly on the isolation structure130, such that the two sensing contacts170are spaced apart from the semiconductor fins120. The sensing contacts170are on opposite sides of the gate structure140and are further spaced apart from the first source/drain structure150and the second source/drain structure155. In some embodiments, the sensing contact170and the reading contact160are on opposite sides of the first source/drain structure150(or the second source/drain structure155), such that the first source/drain structure150is between the sensing contact170and the reading contact160. The sensing contacts170are separated from the gate structure140by a dielectric material (e.g., the gate spacers550, the CESL560, and/or the ILD layer565inFIG.15A). As such, the gate structure140, the sensing contact170, and the dielectric material therebetween form a capacitance. A distance D2is formed between the sensing contact170and the gate structure140, and each of the sensing contact170has an inner surface171facing the gate structure140. A coupling ratio between the gate structure140and the sensing contact170is determined at least by the distance D2and an area of the inner surface171of the sensing contact170. In some embodiments, the coupling ratio between the gate structure140and the sensing contact170is in a range of about 10% to about 50%. Further, the distance D2may be smaller than the width W of the first source/drain structure150. In some embodiments, (the cell unit100of) the semiconductor detector includes a single sensing contact170on one side of the gate structure140. Moreover, the isolation structure130is in contact with the reading contacts160, the sensing contacts170, and the semiconductor fins120.

The sensing pad structure180is electrically connected to the sensing contacts170. In some embodiments, the sensing pad structure180is disposed over the sensing contacts170and the gate structure140. In some embodiments, the sensing pad structure180includes a plurality of sensing pads182and sensing vias184between adjacent sensing pads182. Some of the sensing vias184interconnect adjacent sensing pads182, and some of the sensing vias184interconnect the bottommost sensing pad182and the sensing contacts170. The sensing pads182and the sensing vias184are conductive materials, such that electrons can flow from the sensing pads182to the sensing contacts170. Further, a capacitance can be formed between the bottommost sensing pad182and the gate structure140if the bottommost sensing pad182is close enough to the gate structure140.

In some embodiments, the sensing pad structure180includes a single sensing pad182, which is connected to the sensing contacts170through the sensing vias184. The single sensing pad182may be at the lowest level (e.g., M0 level) of the sensing pad structure180. In some other embodiments, the single sensing pad182may at the middle level (e.g., M1, M2, . . . level) or the topmost level (e.g., Mn level) of the sensing pad structure180according to various requirements.

The (cell unit100of the) semiconductor detector further includes a word line WL and a bit line BL. The word line WL is electrically connected to the reading contact160, and the bit line BL is electrically connected to the second source/drain structure155(i.e., the drain of the cell unit100). For example, the bit line BL is connected to the second source/drain structure155through a source/drain contact195. Further, the word line WL is electrically isolated from the gate structure140. In some embodiments, the first source/drain structure150is electrically connected to a ground (line) GND, which provides a reference electrical potential (e.g., about 0V) to the semiconductor detector during programming, erasing, and/or reading processes, through a source/drain contact190.

The (cell unit100of the) semiconductor detector has four different states it can be in: programming, erasing, sensing, and reading. The semiconductor detector performs the four different states (program, erase, sense, and read) as follows:

Programming—FIG.3is a schematic circuit diagram illustrating the semiconductor detector ofFIG.2at a programming operation according to some embodiments of the present disclosure. The start of a program cycle of the semiconductor detector begins by applying a positive voltage +V1 (e.g., about 8 V to about 10 V) to the word line WL and applying a negative voltage −V2 (e.g., about 0.6 V to about 0.7 V) to the bit line BL. Further, the first source/drain structure150is connected to the ground GND. As such, the gate structure140is floating and an electric field is formed in the gate structure140, driving electrons to flow from the substrate110to the gate structure140through tunneling effect, and the electrons can be stored in the gate structure140.

Erasing—FIG.4is a schematic circuit diagram illustrating the semiconductor detector ofFIG.2at an erasing operation according to some embodiments of the present disclosure. The start of an erase cycle of the semiconductor detector begins by applying a negative voltage −V1 (e.g., about 8 V to about 10 V) to the word line WL and applying a positive voltage +V2 (e.g., about 0.6 V to about 0.7 V) to the bit line BL. Further, the first source/drain structure150is connected to the ground GND. As such, the gate structure140is floating and an electric field is formed in the gate structure140, driving electrons to flow from the gate structure140to the substrate110through tunneling effect, and the gate structure140is supposed to be free of electrons.

Sensing—During the sense cycle of the semiconductor detector, no power is applied to the word line WL, the bit line BL, and the first source/drain structure150as shown inFIG.2. In other word, the semiconductor detector is powerless in the sensing mode. When e-beam light is incident on the sensing pad structure180, electrons of the e-beam light enter the sensing pad structure180and flow to the sensing contact(s)170. An electrical coupling is formed between the sensing contact(s)170and the gate structure140, and the voltage in the gate structure140is changed.

Reading—FIG.5is a schematic circuit diagram illustrating the semiconductor detector ofFIG.2at a reading operation according to some embodiments of the present disclosure. The start of a read cycle of the semiconductor detector begins by applying a varied positive voltage +V3 (e.g., from about 0 V to about 6 V) to the word line WL, applying ground GND to the first source/drain structure150, and the gate structure140is floating, such that a corresponding current under the varied positive voltage +V3 is read from the bit line BL. From the results of experiments, this configuration is read disturb free with the positive voltage +V3.

FIG.6is a plot of I-V characteristics of a bit line in an exemplary detector cell unit100before and after the sensing operation for E-beam light. Before the sensing operation, the gate structure140is substantially free of electrons, and the line12inFIG.6shows the I-V curve of the cell unit100before the sensing operation. The lines14,16, and18show I-V curves of the cell unit100after the sensing operation under first, second, and third intensities of E-beam light, respectively. The third intensity is higher than the second intensity, which is higher than the first intensity.

FIG.7is a perspective view of a semiconductor detector200in accordance with some embodiments, andFIG.8is a schematic circuit diagram illustrating the semiconductor detector200ofFIG.7according to some embodiments of the present disclosure. In some embodiments, the semiconductor detector200includes a plurality of cell units100. In greater detail, the cell unit100inFIG.1can be arranged as an array. That is, a plurality of the cell units100can be arranged in an X-direction and/or a Y-direction. The semiconductor detector200further includes a plurality of word lines (e.g., word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8). Each of the word lines interconnects reading contacts160of the cell units100of the same row (i.e., arranged in the X-direction). The semiconductor detector200further includes a plurality of bit lines (e.g., bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, and BL8). Each of the bit lines interconnects the second source/drain structures155of the cell units100of the same column (i.e., arranged in the Y-direction). For clarity, the word lines and the bit lines are shown inFIG.8and are omitted inFIG.7. With such configuration, the semiconductor detector200can collect the electron distribution of the e-beam light in the XY-directions simultaneously. In some other embodiments, the sensing pad structure180of each of the cell units100inFIG.7includes a single sensing pad182(which may be at an arbitrary height of the corresponding sensing pad structure180). Other relevant structural details of the cell units100of the semiconductor detector200are substantially the same as or similar to the cell unit100of the semiconductor detector inFIG.1, and, therefore, a description in this regard will not be repeated hereinafter.

FIG.9is a perspective view of a semiconductor detector300in accordance with some embodiments. The semiconductor detector300includes a plurality of cell units100a,100b,100c,100d,100e,100f,100g, and100h. Each of the cell units100a-100hhas a similar configuration to the cell unit100inFIG.1except the sensing pad structures. InFIG.9, each of the cell units100a-100hhas a sensing pad structure including single sensing pad. In greater detail, the cell unit100aincludes a sensing pad182aconnected to sensing contacts170athrough sensing vias184a; the cell unit100bincludes a sensing pad182bconnected to sensing contacts170bthrough sensing vias184b; the cell unit100cincludes a sensing pad182cconnected to sensing contacts170cthrough sensing vias184c; the cell unit100dincludes a sensing pad182dconnected to sensing contacts170dthrough sensing vias184d. The cell units100a,100b,100c, and100dare arranged as a two-dimensional array, such that the cell units100a,100b,100c, and100dcan collect the electron distribution of the e-beam light in the XY-directions simultaneously.

Further, the cell unit100eincludes a sensing pad182econnected to sensing contacts170ethrough sensing vias184e; the cell unit100fincludes a sensing pad182fconnected to sensing contacts170fthrough sensing vias184f; the cell unit100gincludes a sensing pad182gconnected to sensing contacts170gthrough sensing vias184g; the cell unit100hincludes a sensing pad182hconnected to sensing contacts170hthrough sensing vias184h. The sensing pad182eis directly above and covers the sensing pad182a, but there is no conductive via between the sensing pad182eand the sensing pad182a. That is, the sensing pad182eis electrically isolated from the sensing pad182a. The sensing pad182fis directly above and covers the sensing pad182b, but there is no conductive via between the sensing pad182fand the sensing pad182b. That is, the sensing pad182fis electrically isolated from the sensing pad182b. The sensing pad182gis directly above and covers the sensing pad182c, but there is no conductive via between the sensing pad182gand the sensing pad182c. That is, the sensing pad182gis electrically isolated from the sensing pad182c. The sensing pad182his directly above and covers the sensing pad182d, but there is no conductive via between the sensing pad182hand the sensing pad182d. That is, the sensing pad182his electrically isolated from the sensing pad182d. With such configuration, the semiconductor detector300can collect the electron distribution of the e-beam light in the XYZ-directions simultaneously. In some embodiments, the semiconductor detector300includes more cell units for detecting different X, Y, and/or Z positions. Other relevant structural details of the cell units100a-100hof the semiconductor detector300are substantially the same as or similar to the cell unit100of the semiconductor detector inFIG.1, and, therefore, a description in this regard will not be repeated hereinafter.

FIGS.10-17Cillustrate a method for manufacturing a semiconductor detector at various stages in accordance with some embodiments of the present disclosure. In addition to the semiconductor detector,FIGS.10-15A,16A, and17Adepict X-axis, Y-axis, and Z-axis directions.FIGS.10-15A,16A, and17Aare perspective views of some embodiments of the semiconductor detector at intermediate stages during fabrication.FIGS.15B,16B, and17Bare cross-sectional views of some embodiments of the semiconductor detector at intermediate stages during fabrication along a first cut (e.g., cut I-I), which is along a lengthwise direction of the reading contact460(or the sensing contact470).FIGS.15C,16C, and17Care cross-sectional views of some embodiments of the semiconductor detector at intermediate stages during fabrication along a second cut (e.g., cut II-II), which is along a lengthwise direction of a channel (i.e., the semiconductor fin420).

Reference is made toFIG.10. A substrate410is provided. In some embodiments, the substrate410is made of a suitable elemental semiconductor, such as silicon, diamond or germanium; a suitable alloy or compound semiconductor, such as Group-IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide InGaAs, indium arsenide, indium phosphide, indium antimonide, gallium arsenic phosphide, or gallium indium phosphide), or the like. Further, the substrate410may include an epitaxial layer (epi-layer), which may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure.

One or more semiconductor fins420are formed on the substrate410. The semiconductor fins420may be P-type. That is, each of the semiconductor fins420may include a P-well region412(seeFIG.15C). The semiconductor fins420may be formed using, for example, a patterning process to form trenches such that trenches are formed between adjacent semiconductor fins420. As discussed in greater detail below, the semiconductor fins420will be used to form FinFETs. It is understood that four semiconductor fins420are illustrated for purposes of illustration, but other embodiments may include any number of semiconductor fins. In some embodiments, one or more dummy semiconductor fins are formed adjacent to the semiconductor fins420.

The semiconductor fins420may be formed by performing an etching process to the substrate410. Specifically, a patterned hard mask structure is formed over the substrate410. In some embodiments, the patterned hard mask structure is formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon-nitride, or the like. For example, the patterned hard mask structure includes an oxide pad layer and a nitride mask layer over the oxide pad layer. The patterned hard mask structure covers a portion of the substrate410while leaves another portion of the substrate410uncovered. The substrate410is then patterned using the patterned hard mask structure as a mask to form trenches402. Accordingly, the semiconductor fins420are formed.

Isolation structures430, such as shallow trench isolations (STI), are disposed in the trenches402and over the substrate410. The isolation structures430can be equivalently referred to as an isolation insulating layer in some embodiments. The isolation structures430may be made of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. In some embodiments, the isolation structures430are formed through a process such as CVD, flowable CVD (FCVD), or a spin-on-glass process, although any acceptable process may be utilized. Subsequently, portions of the isolation structures430extending over the top surfaces of the semiconductor fins420, are removed using, for example, an etching back process, chemical mechanical polishing (CMP), or the like.

The isolation structures430are then recessed to expose an upper portion of the semiconductor fin420. In some embodiments, the isolation structures430are recessed using a single etch processes, or multiple etch processes. In some embodiments in which the isolation structures430is made of silicon oxide, the etch process may be, for example, a dry etch, a chemical etch, or a wet cleaning process. For example, the chemical etch may employ fluorine-containing chemical such as dilute hydrofluoric (dHF) acid.

Reference is made toFIG.11. After the semiconductor fins420and the isolation structures430are formed, at least one dummy gate structure540is formed over the substrate410and at least partially disposed over the semiconductor fins420. The portions of the semiconductor fins420underlying the dummy gate structure540may be referred to as the channel regions C (seeFIGS.17C and18C), and the semiconductor fins420may be referred to as channel layers. The dummy gate structure540may also define source/drain regions S/D (seeFIGS.17C and18C) of the semiconductor fins420, for example, the regions of the semiconductor fins420adjacent and on opposing sides of the channel regions C.

Dummy gate formation operation first forms a dummy gate dielectric layer over the semiconductor fins420. Subsequently, a dummy gate electrode layer and a hard mask which may include multiple layers (e.g., an oxide layer and a nitride layer) are formed over the dummy gate dielectric layer. The hard mask is then patterned to be a nitride mask layer548and an oxide mask layer546, followed by patterning the dummy gate electrode layer to be a dummy gate electrode544by using the nitride mask layer548and the oxide mask layer546as etch masks. In some embodiments, after patterning the dummy gate electrode layer, the dummy gate dielectric layer is removed from the S/D regions of the semiconductor fins420and to be a dummy gate dielectric layer542. The etch process may include a wet etch, a dry etch, and/or combinations thereof. The etch process is chosen to selectively etch the dummy gate dielectric layer without substantially etching the semiconductor fins420, the dummy gate electrode layer544, the oxide mask layer546, and the nitride mask layer548.

In some embodiments, lightly-doped-drain (LDD) source/drain regions414and416(seeFIG.15C) are formed in the source/drain portions of the semiconductor fins420. For example, at least one implantation process is performed, such that dopants are implanted in the source/drain portions of the semiconductor fins420to form the LDD source/drain regions414and416. The dummy gate structure540act as a mask for the ion implantation.

After formation of the dummy gate structure540(or formation of the LDD source/drain regions414and416) is completed, gate spacers550are formed on sidewalls of the dummy gate structure540. In some embodiments of the gate spacer formation operations, a spacer material layer is deposited on the substrate410. The spacer material layer may be a conformal layer that is subsequently etched back to form the gate spacers550. In some embodiments, the spacer material layer includes multiple layers, such as a first spacer layer552and a second spacer layer554(seeFIG.15C) formed over the first spacer layer552. The first and second spacer layers552and554each are made of a suitable material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. By way of example and not limitation, the first and second spacer layers552and554may be formed by depositing in sequence two different dielectric materials over the dummy gate structure540using processes such as, an ALD process, a PEALD (plasma enhanced ALD) process, a PECVD process, a subatmospheric CVD (SACVD) process, or other suitable process. An anisotropic etching process is then performed on the first and second spacer layers552and554to expose portions of the semiconductor fins420not covered by the dummy gate structure540(e.g., in the source/drain regions of the semiconductor fins420). Portions of the first and second spacer layers552and554directly above the dummy gate structure540may be removed by this anisotropic etching process. Portions of the first and second spacer layers552and554on sidewalls of the dummy gate structure540may remain, forming gate sidewall spacers, which are denoted as the gate spacers550, for the sake of simplicity. In some embodiments, the first spacer layer552is formed of silicon oxide that has a lower dielectric constant than silicon nitride, and the second spacer layer554is formed of silicon nitride that has a higher etch resistance against subsequent etching processing (e.g., etching source/drain recesses in the semiconductor fins420) than silicon oxide. In some embodiments, the gate spacers550may be used to offset subsequently formed doped regions, such as source/drain regions. The gate spacers550may further be used for designing or modifying the source/drain region profile.

Reference is made toFIG.12. After the formation of the gate spacers550is completed, source/drain epitaxial structures450and455are formed on source/drain regions of the semiconductor fins420that are not covered by the dummy gate structures540and the gate spacers550. In some embodiments, formation of the source/drain epitaxial structures450and455includes recessing source/drain regions of the semiconductor fins420, followed by epitaxially growing semiconductor materials in the recessed source/drain regions of the semiconductor fins420.

The source/drain regions of the semiconductor fins420can be recessed using suitable selective etching processing that attacks the semiconductor fins420, but barely attacks the gate spacers550and the mask layer548of the dummy gate structure540. For example, recessing the semiconductor fins420may be performed by a dry chemical etch with a plasma source and an etchant gas. The plasma source may be inductively coupled plasma (ICP) etch, transformer coupled plasma (TCP) etch, electron cyclotron resonance (ECR) etch, reactive ion etch (RIE), or the like and the etchant gas may be fluorine, chlorine, bromine, combinations thereof, or the like, which etches the semiconductor fins420at a faster etch rate than it etches the gate spacers550and the mask layer548of the dummy gate structure540. In some other embodiments, recessing the semiconductor fin420may be performed by a wet chemical etch, such as ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, which etches the semiconductor fins420at a faster etch rate than it etches the gate spacers550and the mask layer548of the dummy gate structure540. In some other embodiments, recessing the semiconductor fins420may be performed by a combination of a dry chemical etch and a wet chemical etch.

Once recesses are created in the source/drain regions of the semiconductor fins420, the source/drain epitaxial structures450and455are formed in the source/drain recesses in the semiconductor fins420by using one or more epitaxy or epitaxial (epi) processes that provides one or more epitaxial materials on the semiconductor fins420. During the epitaxial growth process, the gate spacers550limit the one or more epitaxial materials to source/drain regions in the semiconductor fins420. In some embodiments, the lattice constants of the source/drain epitaxial structures450and455are different from the lattice constant of the semiconductor fins420, so that the channel region in the semiconductor fins420and between the source/drain epitaxial structures450and455can be strained or stressed by the source/drain epitaxial structures450and455to improve carrier mobility of the semiconductor device and enhance the device performance. The epitaxy processes include CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the semiconductor fins420.

In some embodiments, the source/drain epitaxial structures450and455include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain epitaxial structures450and455may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain epitaxial structures450and455are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the source/drain epitaxial structures450and455. In some exemplary embodiments, the source/drain epitaxial structures450and455in an n-type transistor include SiP.

Once the source/drain epitaxial structures450and455are formed, an annealing process can be performed to activate the n-type dopants in the source/drain epitaxial structures450and455. The annealing process may be, for example, a rapid thermal anneal (RTA), a laser anneal, a millisecond thermal annealing (MSA) process or the like.

Reference is made toFIG.13. An interlayer dielectric (ILD) layer565is formed on the substrate410. In some embodiments, a contact etch stop layer (CESL) 560 is also formed prior to forming the ILD layer565. In some embodiments, the CESL560includes a silicon nitride layer, a silicon oxynitride layer, and/or other suitable materials having a different etch selectivity than the ILD layer565. The CESL560may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the ILD layer565includes materials such as tetraethylorthosilicate (TEOS)-formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials having a different etch selectivity than the CESL560. The ILD layer565may be deposited by a subatmospheric CVD (SACVD) process, a flowable CVD process, or other suitable deposition technique. In some embodiments, after formation of the ILD layer565, the wafer may be subject to a high thermal budget process to anneal the ILD layer565.

In some examples, after forming the ILD layer565, a planarization process may be performed to remove excessive materials of the ILD layer565. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer565(and the CESL560, if present) overlying the dummy gate structure540. In some embodiments, the CMP process also removes the oxide mask layer546and the nitride mask layer548(as shown inFIG.12) and exposes the dummy gate electrode544.

Reference is made toFIG.14. The dummy gate electrode544and the dummy gate dielectric layer542(seeFIG.13) are removed, resulting in a gate trench between the gate spacers550. The dummy gate electrode544and the dummy gate dielectric layer542are removed using a selective etching process (e.g., selective dry etching, selective wet etching, or combinations thereof) that etches materials in the dummy gate electrode544and the dummy gate dielectric layer542at a faster etch rate than it etches other materials (e.g., the gate spacers550, the CESL560, and/or the ILD layer565).

Thereafter, a replacement gate structure440is formed in the gate trench. The gate structure440may be the final gates of FinFETs. The final gate structure may be a high-k/metal gate stack, however other compositions are possible. In some embodiments, the gate structure440forms the gate associated with the three-sides of the channel region provided by the semiconductor fins420. Stated another way, the gate structure440wraps around the semiconductor fins420on three sides. In various embodiments, the (high-k/metal) gate structure440includes a gate dielectric layer442lining the gate trench and a gate electrode over the gate dielectric layer442. The gate electrode may include a work function metal layer444formed over the gate dielectric layer442and a fill metal446formed over the work function metal layer444and filling a remainder of gate trenches. The gate dielectric layer442includes an interfacial layer (e.g., silicon oxide layer) and a high-k gate dielectric layer over the interfacial layer. High-k gate dielectrics, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The work function metal layer444and/or fill metal446used within the high-k/metal gate structure440may include a metal, metal alloy, or metal silicide. Formation of the high-k/metal gate structure440may include multiple deposition processes to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials.

In some embodiments, the interfacial layer of the gate dielectric layer442may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-k dielectric layer of the gate dielectric layer442may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer442may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations thereof.

The work function metal layer444may include work function metals to provide a suitable work function for the high-k/metal gate structure440. For an n-type FinFET, the work function metal layer444may include one or more n-type work function metals (N-metal). The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. In some embodiments, the fill metal446may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

Reference is then made toFIGS.15A-15C, whereFIG.15Bis a cross-sectional view taken along line I-I ofFIG.15A, andFIG.15Cis a cross-sectional view taken along line II-II ofFIG.15A. One or more etching processes are performed to form contact openings O1, O2, O3, and O4 extending though the ILD layer565to expose the source/drain epitaxial structures450,455, or the isolation structures430. For example, the contact openings O1 and O3 expose the isolation structures430as shown inFIG.15B, and the contact openings O2 and O4 respectively expose the source/drain epitaxial structures450and455as shown inFIG.15C. That is, the depths of the contact openings O1 and O3 are greater than the depths of the contact openings O2 and O4.

Reference is then made toFIGS.16A-16C, whereFIG.16Bis a cross-sectional view taken along line I-I ofFIG.16A, andFIG.16Cis a cross-sectional view taken along line II-II ofFIG.16A. Reading contacts460are respectively formed in the contact openings O1, sensing contacts470are respectively formed in the contact openings O3, and source/drain contacts490and495are respectively formed in the contact openings O2 and O4. Formation of the contacts includes, by way of example and not limitation, depositing one or more conductive materials overfilling the contact openings O1, O2, O3, and O4 such that the conductive materials are in contact with the isolation structure430, and then performing a CMP process to remove excessive conductive materials outside the contact openings O1, O2, O3, and O4. As shown inFIG.16B, a top surface462of the reading contact460, a top surface472of the sensing contact470, and a top surface492of the source/drain contact490are substantially coplanar.

In some embodiments, metal alloy layers492and497are respectively formed above the source/drain epitaxial structures450and455prior to forming the source/drain contacts490and495. The metal alloy layers492and497, which may be silicide layers, are respectively formed in the contact openings O2 and O4 and over the exposed source/drain epitaxial structures450and455by a self-aligned silicide (salicide) process. The silicide process converts the surface portions of the source/drain epitaxial structures450and455into the silicide contacts. Silicide processing involves deposition of a metal that undergoes a silicidation reaction with silicon (Si). In order to form silicide contacts on the source/drain epitaxial structures450and455, a metal material is blanket deposited on the source/drain epitaxial structures450and455. After heating the wafer to a temperature at which the metal reacts with the silicon of the source/drain epitaxial structures450and455to form contacts, unreacted metal is removed. The silicide contacts remain over the source/drain epitaxial structures450and455, while unreacted metal is removed from other areas. The silicide layer may include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel platinum silicide, erbium silicide, palladium silicide, combinations thereof, or other suitable materials. In some embodiments, the metal alloy layer492and497may include germanium.

Reference is then made toFIGS.17A-17C, whereFIG.17Bis a cross-sectional view taken along line I-I ofFIG.17A, andFIG.17Cis a cross-sectional view taken along line II-II ofFIG.17A. A multilayer interconnection (MLI) structure570is formed over the structure ofFIG.16A. The MLI structure570may include a plurality of metallization layers572. The number of metallization layers572may vary according to design specifications of the semiconductor device. Eight metallization layers572are illustrated inFIGS.17B and17Cfor the sake of simplicity. The metallization layers572each includes an inter-metal dielectric (IMD) layer573and an etch stop layer574. For clarity, the IMD layers573and the etch stop layers574are shown inFIGS.17B and17Cand are omitted inFIG.17A. The metallization layers572include one or more horizontal interconnects, such as a word line WL, a bit line BL, a ground line GND, and sensing pads482, respectively extending horizontally or laterally in the IMD layers573and vertical interconnects, such as sensing vias484and conductive vias486, respectively extending vertically in the IMD layers573and pass through the etch stop layers574. As mentioned above, the sensing pads482and the sensing vias484form a sensing pad structure480.

The word line WL, the bit line BL, the ground line GND, the sensing pads482, the sensing vias484, and the conductive vias486can be formed using, for example, a single damascene process, a dual damascene process, the like, or combinations thereof. In some embodiments, the IMD layers573may include low-k dielectric materials having k values, for example, lower than about 4.0 or even 2.0 disposed between such conductive features. In some embodiments, the IMD layers573may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon oxide, silicon oxynitride, combinations thereof, or the like, formed by any suitable method, such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or the like. In some embodiments, the etch stop layers574may be formed of SiNx, SiCN, SiO2, CN, AlOxNy, combinations thereof, or the like, deposited by CVD or PECVD techniques. The word line WL, the bit line BL, the ground line GND, the sensing pads482, the sensing vias484, and the conductive vias486may include metal materials such as copper, aluminum, tungsten, combinations thereof, or the like. In some embodiments, the word line WL, the bit line BL, the ground line GND, the sensing pads482, the sensing vias484, and the conductive vias486may further include one or more barrier/adhesion layers (not shown) to protect the respective IMD layers573from metal diffusion (e.g., copper diffusion) and metallic poisoning. The one or more barrier/adhesion layers may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using physical vapor deposition (PVD), CVD, ALD, or the like. As shown inFIG.17C, there is no via interconnecting the horizontal interconnects and/or vertical interconnects of the MLI structure570and the gate structure440.

FIG.18Ais a perspective view of a semiconductor detector in accordance with some embodiments,FIG.18Bis a cross-sectional view taken along line I-I ofFIG.18A, andFIG.18Cis a cross-sectional view taken along line II-II ofFIG.18A. The difference between the semiconductor detectors inFIGS.18A-18CandFIGS.17A-17Cpertains to the conductivity type of the semiconductor detectors. For example, the semiconductor detector inFIGS.17A-17Cuses an NMOS configuration, and the semiconductor detector inFIGS.18A-18Cuses a PMOS configuration. Specifically, inFIG.18C, a P-well412is formed in the substrate410, and an N-well413is formed in the P-well412. The source/drain epitaxial structures450and455are P-type and formed in the N-well413.

In some embodiments, the source/drain epitaxial structures450and455include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain epitaxial structures450and455may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2and/or other suitable dopants including combinations thereof. If the source/drain epitaxial structures450and455are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the source/drain epitaxial structures450and455. In some exemplary embodiments, the source/drain epitaxial structures450and455in a p-type include GeSnB and/or SiGeSnB.

The work function metal layer444may include work function metals to provide a suitable work function for the high-k/metal gate structures442. For a p-type FinFET, the work function metal layer444may include one or more p-type work function metals (P-metal). The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. Other relevant structural details of the semiconductor detector inFIGS.18A-18Care the same as or similar to the semiconductor detector inFIGS.17A-17C, and, therefore, a description in this regard will not be repeated hereinafter.

FIG.19is a schematic diagram of an electron beam system700for implementing one or more embodiments of the present disclosure. The electron beam lithography system includes a chamber710, an electron source720, an electron optical module730, a wafer stage740, a pump unit750, and a modulator760according to one or more embodiments of the present disclosure. However, other configurations and inclusion or omission of devices may be possible. In some embodiments, the electron beam system700is an electron beam writer or a scanning electron microscope. The electron source720is disposed in the chamber710and provides electrons (i.e., the electron beam722) emitted from a conducting material by heating conducting materials to a very high temperature, where the electrons have sufficient energy to overcome the work function barrier and escape from the conducting material (thermionic sources), or by applying an electric field sufficiently strong that the electron tunnel through the barrier (field emission sources). The electron optical module730is disposed in the chamber710and includes electromagnetic apertures732, electrostatic (and/or electromagnetic) lenses734, shaping deflector, and/or cell selection deflector; and provides a plurality of Gaussian spot electron beams, variable shaped electron beams and cell projection electron beams. The chamber710includes a wafer loading and unloading unit, and provides the wafer transportation without interrupting the vacuum of the system. The pump unit750includes one or more pumps and provides a high vacuum environment for the electron beam system700. The wafer stage740is disposed in the chamber710and includes motors, roller guides, and/or tables, and provides an accurate position and movement for a wafer W, secured on the wafer stage740by vacuum, in X, Y and Z directions during focus, leveling, exposure process of the wafer in the electron beam system700. The modulator760is configured to blank, pulse, or modulating the electron beam722.

FIG.20is a flowchart of a method M10 for detecting light uniformity of e-beam according to aspects of the present disclosure in various embodiments. The method M10 is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method M10, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the process. For clarity and ease of explanation, some elements of the figures have been simplified.

Various operations of the method M10 are discussed in association with cross-section diagramsFIGS.2-5. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In operation S12ofFIG.20, the detector units of the semiconductor detector are initialized. For example, each of the gate structures of the detector units is performed with the programming process (FIG.3). That is, the electrons are injected into the gate structures of the detector units. With the programming process, the electrons in the gate structures of the detector units may be in saturation states after the initialization process. The programming process of the detector units is described inFIG.3. Alternatively, each of the gate structures of the detector units is performed with the erasing process (FIG.4). That is, the electrons are extracted out of the gate structures of the detector units. With the erasing process, the gate structures of the detector units may be substantially free of electrons after the initialization (erasing) process. The erasing process of the detector units is described inFIG.4.

In operation S14ofFIG.20, a pre-exposure reading operation is performed. For example, a wafer acceptance test (WAT) is performed on product wafers which are going to carry on exposure processes. The wafer acceptance test includes numerous testing items and is a part of IC fabrication process. The wafer acceptance test is used to determine product quality. During the wafer acceptance test, the semiconductor detector (e.g., the semiconductor detector100inFIG.1, the semiconductor detector200inFIG.7, or the semiconductor detector300inFIG.9) is initialized and then the data of the gate structures of the detector units of the semiconductor detector is read by performing the process described inFIG.5. In some embodiments, the line12inFIG.6is the data obtained from the pre-exposure reading operation.

In operation S16ofFIG.20, a sensing operation is performed to the semiconductor detector. In some embodiments, the semiconductor detector is positioned on a wafer stage of an exposure apparatus (e.g., the wafer stage740of the electron beam system700shown inFIG.19). The electron source720of the electron beam system700is turned on, and the electron beam722is incident or impinges or illuminates or projects on the semiconductor detector. The sensing pad structure of the detector units of the semiconductor detector sense the e-beam, and amounts of the electrons in the gate structures are changed. The sensing operation is described inFIG.2.

In operation S18ofFIG.20, a post-exposure reading operation is performed. For example, another wafer acceptance test (WAT) is performed on the semiconductor detector. During the wafer acceptance test, the data of the gate structure of each of the detector units of the semiconductor detector is read again by performing the process described inFIG.5. InFIG.6, the lines14,16, and18shows the I-V curve of the gate structure (under different e-beam intensities) after the e-beam sensing operation.

In operation S20ofFIG.20, data of the pre-exposure reading operation and the post-exposure reading operation are compared to obtain intensity. Specifically, by comparison the I-V curves of the pre- and post-exposure reading operations, the electron variation of each gate can be determined, and the corresponding spatial e-beam intensity can be obtained.

In operation S22ofFIG.20, the e-beam distribution of the electron beam system700is adjusted based on the compared data. Specifically, the spatial distribution of the e-beam of the semiconductor detector is obtained in the operation S20. If the spatial distribution is not desired (such as non-uniform), parameters of the electron beam system700are tuned to form an e-beam having more uniform spatial distribution. For example, the parameters are e-beam dosage.

In operation S24ofFIG.20, product wafers are processed by using the adjusted e-beam. For example, the product wafers can be disposed on the wafer stage740of the electron beam system700shown inFIG.19. The product wafers each include a photoresist, which can be exposed by the adjusted e-beam. The photoresist can then be developed and a patterned photoresist is formed. With the embodiments of the method M10, the patterning quality of the photoresists is improved.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the semiconductor detector is powerless during the sensing mode. Another advantage is that the sensing and recording of the e-beam intensity are in the same element (i.e., the floating gates), and an additional recorder can be omitted to save the layout area. In addition, there are only one transistor in a cell unit to achieve high density and high spatial resolution. Further, the manufacturing of the semiconductor detector is compatibility to semiconductor device (e.g., CMOS) process. For example, the semiconductor detector can be formed on a semiconductor wafer, such that the semiconductor detector can reflect the intensity distribution of the e-beam on a product wafer. Also, the data in the floating gate can be readout with (in-line) wafer acceptance tests, and the data can be timely feedback to adjust the e-beam intensity.

According to some embodiments, a device includes a semiconductor fin, an isolation structure, a gate structure, source/drain structures, a sensing contact, a sensing pad structure, and a reading contact. The semiconductor fin includes a channel region and source/drain regions on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is over the channel region of the semiconductor fin. The source/drain structures are respectively over the source/drain regions of the semiconductor fin. The sensing contact is directly on the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The reading contact is directly on the isolation structure and adjacent to the gate structure.

According to some embodiments, a method includes forming an isolation structure over a substrate to define an active region in the substrate. A gate structure is formed over the active region. Source/drain structures are formed on the active region and on opposite sides of the gate structure. An interlayer dielectric (ILD) layer is deposited over the substrate and surrounding the gate structure. A first opening, a second opening, and a third opening are formed in the ILD layer, such that the first opening exposes the active region, and the second and third openings expose the isolation structure. A source/drain contact is formed in the first opening, a reading contact is formed in the second opening, and a sensing contact is formed in the third opening. An interconnect structure is formed over the gate structure and the sensing contact. The interconnect structure includes a sensing pad connected to the sensing contact.

According to some embodiments, a method includes initializing an electrical potential of a gate structure of a semiconductor detector. The semiconductor detector includes the gate structure, an isolation structure, a reading contact, a sensing contact, and a sensing pad. The gate structure is over a semiconductor fin. The isolation structure surrounds the semiconductor fin. The reading contact is over the isolation structure and adjacent to the gate structure. The sensing contact is over the isolation structure and adjacent to the gate structure. The sensing pad is over and connected to the sensing contact. A pre-exposure reading operation is performed on the semiconductor detector. An e-beam light is projected to the sensing pad of the semiconductor detector after initializing the electrical potential of the gate structure of the semiconductor detector. A post-exposure reading operation is performed on the semiconductor detector. The data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the e-beam light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.