Patent ID: 12261091

Throughout this description, elements appearing in figures are assigned three-digit or four-digit reference designators, where the two least significant digits are specific to the element and the one or two most significant digit may be the figure number where the element is first introduced or fabricated. An element that is not described in conjunction with a figure may be presumed to have the same characteristics and function as a previously-described or subsequently-described element having the same reference designator.

DETAILED DESCRIPTION

Description of Apparatus

The following describes improved wafers, die, chips and fabrication techniques thereof for electronic assemblies having in-substrate chip (e.g., chiplet) integration into wafer cavities of a host wafer using lateral dielectric material. The host wafer can have pre-fabricated interconnects and integrated circuitry, such as passive components, that connect to a chiplet level microelectronics transistor chip integrated in a through-wafer cavity of the wafer. This may form an assembly for integrated circuit devices where the chips contain active circuits from at least one semiconductor technology and the wafers contain passive (or active) circuits from another semiconductor technology (often a cheaper and larger scale technology). Using a low-cost large-diameter integration platform for the chips with active devices allows for much faster manufacturing of the assembled circuits, at larger scale and lower cost.

The electronic assembled circuit may integrate chiplets having one type of components into a carrier wafer having a different type of components. The electronic assembled circuit may integrate chiplets having high-performance integrated circuits, such as Gallium Nitride (GaN) radio frequency (RF) integrated circuits (ICs) into host wafers having other integrated circuits, such as silicon-based integrated circuits, in a manner that is inexpensive and has high manufacturing yields and short manufacturing cycles. The high performance RF ICs, chips (or chiplets) can have type III-V transistors or other types of transistors and passives, and can be integrated together with resistors, inductors, capacitors and matching networks, as well as active devices from another semiconductor technology into the host wafer. For example, the RF ICs can be one type of semiconductor technology that is integrated together with resistors, inductors, capacitors, matching networks, active devices from another semiconductor technology that are part of the host wafer. A chiplet may be a chip including the circuitry, material, and/or devices noted above in this paragraph. It may also be a chip or small chip having active microelectronic (i.e., transistor) devices, CMOS devices, microwave IC devices and/or radio frequency (RF) IC devices. It may also be a chip or small chip having a SAW, BAW or other acoustic wave device. A chiplet may have a footprint or top surface area that is half, a third a fifth or less than a fifth of that of a computer processor chip (e.g., 8086, P3, P4, etc.).

FIG.1Ais a schematic top view100of a host wafer110having cavities120for in-substrate chiplet integration into the wafer cavities120of a host wafer110using lateral dielectric material. Host wafer110has back surface112and front surface114as shown inFIG.2. Host wafer110and/or each cavity120has side surfaces116, such as a vertical or sidewall surfaces between the back surface112and front surface114. There may be 3, 4 or more side surface116. Typically, there are 4 side surfaces.

Wafer110may be or include (e.g., as a mixture of materials or as material layers) silicon, silicon germanium, silicon on insulator, gallium arsenide, indium phosphide, aluminum nitride, diamond, silicon carbide, quartz, alumina. If the wafer only contains interconnections and passive components, it can be a dielectric such as glass, quartz, alumina, or another ceramic. The host wafer110may have layers of one or more of these materials in the form of an oxide material, crystalline material and polycrystalline material and/or amorphous material. Wafer110may include at least one of resistors, capacitors, inductors, through substrate vias, dielectric layers, metal layers (e.g., signal traces or signal planes). Wafer110may include at least one layer of silicon, silicon carbide (SiC), quartz, or another semiconductor wafer material.

Wafer110may include areas to be diced into integrated circuits, each having passive integrated components (e.g., signal traces, interconnects and conductive vias, resistors, inductors and/or capacitors), a single transistor and/or a plurality of transistors. Silicon is an advantageous choice for wafer110, because it takes advantage of having a lower expense than other materials; and/or of known microelectronics fabrication processes and of scaling and manufacturing capabilities.

FIG.1Bis a schematic top view102of chiplets130for in-substrate chiplet integration into wafer cavities120of a host wafer110using lateral dielectric material. Chiplets130have frontside132(e.g., a frontside surface) and backside134(e.g., a backside surface) as shown inFIG.2. Each chiplet130has side surfaces136, such as a vertical or sidewall surfaces between the frontside surface132and backside134. There may be 3, 4 or more side surface136. Sometimes there are 4 side surfaces. The number of side surfaces136of each chiplet130may be the same as the number of surfaces116.

Chiplets130may each be or include (e.g., as a mixture of materials or as material layers) silicon, silicon germanium, silicon-on-insulator, gallium arsenide, indium phosphide, aluminum nitride, quartz, alumina, gallium nitride, silicon carbide. The chiplets130may have layers of one or more of these materials in the form of an oxide material, crystalline material and polycrystalline material and/or amorphous material. There may be different electrical component ones or types of chiplets130that are manufactured separately from each other. Chiplets130can include a GaN, InP or GaAs or any other industry-known electrical component and can be fabricated on a substrate such as Si, SiGe, InP, GaAs, SiC, Alumina, or diamond, or any other substrate known in the industry.

Chiplets130or types of chiplets130may include RF switches, transmit and/or receive circuits; power switches, amplifiers and circuits such as using GaAs, InP, GaN; and/or transistors such as Si CMOS transistors. They may have smaller and more expensive electrical components than those of wafer110. There may be hundreds, thousands or hundreds of thousands of chiplets130embedded in one wafer110. Wafer110may have more passive components, lower cost components, routing (e.g., traces, conductive vias and interconnections) than those of chiplets130. Wafer110may be fabricated using different microelectronic fabrication techniques or processes than used to fabricate chiplets130.

Chiplets130and wafer110can be made of different materials. For example, wafer110can be a silicon wafer while chiplets130can be a type III-Nitride material component chip. Chiplets130may each be or include an integrated circuit having passive integrated components (e.g., signal traces, interconnects and conductive vias, resistors, inductors and/or capacitors), a single transistor and/or a plurality of transistors.

The chiplets130, each include at least one of transistor circuitry and interconnects to contact pads on a frontside132of the chiplets130. The chiplets130may be high-end pre-fabricated active device chiplets that are integrated into wafer110through pick and place assembly on temporary wafer with an adhesive laminate or simply on an adhesive laminate340(seeFIG.3B).

FIG.2is a schematic cross-sectional view of a device200having in-substrate chiplet130integration into wafer cavities120of a host wafer110using lateral dielectric material360. Device200may include the devices ofFIGS.1A and1B.

Device200may be an electronic assembly having a backside capping layer370having a top surface372and a back surface374. Device200has a host wafer110having back surface112and front surface114, with the back surface112of the wafer bonded to the top surface372of a backside capping layer370except for cavities120in the wafer110formed over a plurality of areas376of the top surface372. The cavities may extend from back surface112, through the wafer and to front surface114. The cavities have side surfaces116. The back surface112of the wafer may be directly attached to and touching the top surface372. The bond between the back surface112and the top surface372may be a covalent, chemical or atomic bond.

Chiplets130or a plurality of chips have a backside134and a frontside132, with the backsides134of the chiplets130bonded directly to at least portion378of the plurality of areas376of the top surface372of the backside capping layer. Portion378may be the footprint of the chiplet130on top surface372within the cavity120. A gap350between side surfaces116and136may be the difference between area376and portion378. The backside134may be directly attached to and touching the top surface372. The bond between the backside134and the top surface372may be a covalent, chemical or atomic bond.

The cavities120may be through-substrate holes or through substrate holes etched in the wafer at the areas376. The, chiplets130may be embedded into the wafer110at the substrate holes or at cavities120.

A lateral dielectric material360extends between side surfaces136of the chiplets130and the side surfaces116of the wafer or cavities. The lateral dielectric material360may mechano-chemically bond the side surfaces136of the chiplets130to the side surfaces116of the wafer. The lateral dielectric material360may form a mechanical and/or a chemical bond to the side surfaces136and to the side surfaces116. In some cases, the lateral dielectric material360is a molded material and the bonding is a mechano-chemical bond.

Dielectric material360is not a metal and is an electrical insulator. Dielectric material360may be or include material that is not conductive, is not a semiconductor, is a plastic, is not an alloy, is a bio-material. Material360may be an epoxy. It may be epoxy with a silica particles. It may be epoxy with a SiO2 particles.

Material360may have dielectric characteristics such that when placed in an electric field, the electric charges do not flow through the material. Electric charges slightly shift from their average equilibrium positions, causing dielectric polarization that causes positive charges to flow in the direction of the field and negative charges to shift in the opposite direction of the field. This phenomenon yields an internal electric field, which in turn reduces the overall electric field within the dielectric material.

In some cases, material360may have no current flow through it when a voltage is applied. However, certain changes do happen at the atomic scale. When a voltage is applied across a dielectric object, it becomes polarized. Since atoms are made of a positively charged nucleus and negatively charged electrons, polarization is an effect which slightly shifts electrons towards the positive voltage. They do not travel far enough to create a current flow through the material—the shift is microscopic, but has a very important effect. Once the voltage source is removed from the material, it either returns to its original non-polarized state, or stays polarized if the molecular bonds in the material are weak. The dielectric materials may be an insulators, but one that is easily polarized.

In some cases, the dielectric material360has a coefficient of thermal expansion between or equal to one of those of the wafer110and of the chiplets130.

The lateral dielectric material360is disposed in gaps350between the side surfaces136of each of the chiplets130and the side surfaces116of the corresponding wafer cavity that each chiplet130is disposed in. The gap350has a width gw of between ⅕ (one fifth) and 10 times a thickness tw of the wafer110or chiplets130.

The thickness tw of the wafer may be between 20 and 200 microns. It may be between 50 and 125 um. It may be 75 um. The thickness of one, many or all of the chiplets may be that same as that of the wafer.

A thickness te of the backside capping layer may be between 3 and 300 microns. It may be between 5 and 100 microns. It may be between 10 and 50 microns. It may be 15 um.

Each of the chiplets130have between 3 and 6 sides. They may have 4 sides. The sides may be straight, curved or wavy in profile as viewed from a top perspective. The cavities120may have the same number of and sides corresponding to the shapes of the sides of the chiplets130.

The backside capping layer370may be is a high-thermal-conductivity backside metallization layer that improves heat transfer from the chiplets130to the wafer110. Layer370may be a thermal plane that improves heat conduction away from the chiplets by increasing thermal conduction from the chiplets130and to layer370and/or wafer110. Layer370be a material in direct contact with the chiplets130to increase thermal conduction between the materials of the chiplets130and that of layer370. In some cases, the backside capping layer370has a coefficient of thermal expansion between those of or equal to one of those of the wafer110and of the chiplets130.

Interconnects510may be formed directly on the lateral dielectric material360and connect electrical (e.g., power, ground and/or signal) contacts138of the chiplets130to contacts118of the wafer110. Interconnects510may include direct interconnect routing or traces that is formed directly on the lateral dielectric material (e.g., without any dielectric/air gap), and that extends from the chiplets to wafer electrical routing. The interconnect routing may include low loss high-performance DC, RF, and mm-wave routing from the chiplets130, directly on the lateral dielectric material, and to wafer electrical routing. Interconnects510may be directly on material360by being bonded to and/or directly attached to (e.g., touching) the top surface of the lateral dielectric material360.

In some cases, wafer110includes an electronic integrated circuit (not shown), at least one integrated circuit contact118(e.g., contact pad) formed on the front wafer surface114, and at least one through-wafer cavity120having side surface116that join back surface112to front surface114. In some cases, a chiplet130is held in the through-wafer cavity120by a lateral dielectric material360that attaches at least one side surface116of the through-wafer cavity120to at least one side surface136of the chiplet130. In some cases, lateral dielectric material360fills gap350of the cavity, thus attaching most of the side surfaces136of chiplet130to the side surfaces116of through-wafer cavity120; however material360does not attach the backside134of chiplet130to top surface372of layer370.

A passivation layer (not shown) can be arranged on most of the front surface114of wafer110. Conducting vias (e.g., TWVs) arranged through the passivation layer can connect the active and/or passive circuitry of wafer110to contacts118(e.g., contact pads) on front surface114. Wafer110can be a silicon wafer or substrate, which allows taking advantage of known fabrication processes and manufacturability on large wafer diameters.

It is noted that wafer110can include any integrated circuit, active or passive, made possible by a chosen manufacturing process; for example, a CMOS manufacturing process. In some cases, the thickness of the one or more integrated circuit layers can for example be only a fraction of the thickness tw of wafer110(for example between 1/10 and 1/1000 of the thickness of wafer110; for example 50 nm thick with a wafer 50 μm thick). In some cases, the thickness of wafer110can be reduced after fabrication of integrated circuits of the wafer and for example before etching the through-wafer cavity120or after filling gap350with lateral dielectric material360.

Chiplet130may include one or more transistors (not shown) having its terminals connected to at least one integrated circuit contact138(e.g., contact pad), such as by a conductive via (not shown). Chiplet130can comprise a substrate and integrated circuit layers formed on top of its substrate, the thickness of the integrated circuit layers being for example only a fraction of the thickness of the substrate (for example between 1/10 and 1/1000 of the thickness of the substrate). In some cases, the total thickness of chiplet130is smaller than the total thickness of host wafer110. In some cases, lateral dielectric material360contacts the side surfaces136of chiplet130along most of their height (at least 50% of the height, starting from close to the top surface of chiplet130). Preferably, lateral dielectric material360contacts essentially all of the side surfaces136of chiplet130. Preferably, lateral dielectric material360fills completely gap350, up to a level essentially flush with the front surface114of host wafer110.

In some cases, lateral dielectric material360holds the chiplet130such that the chiplet frontside132is flush with the front surface114. Being “flush” may be understood as meaning that the two surfaces are in a same plane, or have, with respect to each other, a small or negligible height difference. The two surfaces may be flush, such as resulting from the process of material360permanently attaching chiplet130to the side surfaces116of through wafer cavity120while both the chiplet frontside132and the front surface114are attached temporarily to an adhesive laminate340(seeFIGS.3A-3F), for example according to a process as illustrated herein. The frontside132and the front surface114may be flush, such as resulting from polishing or CMP of those surfaces after removing the temporarily adhesive laminate340.

In some cases, layer370has flat planar, continuous surface and a constant thickness te, such as where the back surfaces112of the chiplets and backside surface134of the wafer are all at the same vertical, planar level. In other cases, layer370has a non-flat surface and a non-constant thickness, such as where the back surfaces112of the chiplets and/or backside surface134of the wafer vary in height and are not planar. In one case, the thickness te of layer370varies between the chiplets and wafer by being a certain thickness for the wafer and having another thickness for one or more chips. in other words, the wafer and some of the chiplets have different thicknesses. In this case, some of the chiplets may have different thicknesses than other chiplets.

It is considered that the host wafer110can be vertically diced at dicing lines (shown by the vertical bars inFIG.2) along a perimeter386of the wafer around at least one chiplet to form a chip having the at least one chiplet and an area of the wafer surrounding the at least one chiplet.

Description of Methods

FIGS.3A-3Fare a flow diagram showing a process of steps301-306for fabrication of a device200having in-substrate chiplet integration into wafer cavities of a host wafer using lateral dielectric material. The process may form device200using the devices ofFIGS.1A and1B. The process starts with device311and ends with device200. The process may be a method of forming or assembling an electronic assembly or device. The process may be a lateral chiplet dielectric bonding process. The flow chart ofFIGS.3A-3Fincludes only major process steps. Various conventional process steps (e.g. surface preparation, chemical mechanical processing (CMP), cleaning, inspection, deposition, photolithography, baking, annealing, monitoring, testing, etc.) may be performed before, between, after, and during the steps shown inFIGS.3A-3F.

FIG.3Ashows step301for forming device311, which includes a host wafer110bonded to an adhesive laminate340. Step301may include forming cavities120through a host wafer110having back surface112and front surface114, the cavities having side surfaces116. Forming the cavities120may include etching through-substrate holes in the back surface112of the wafer.

Step301then includes bonding a front surface114of the wafer to a top surface342of an adhesive laminate340having the top surface342and a bottom surface344such that the cavities120are disposed over a plurality of areas376of the top surface342of the adhesive laminate. Bonding at step301may include directly attaching the front surface114of the wafer to the top surface342such that front surface114is bonded to and touching top surface342, except for the cavities120or areas376. The bond between the front surface114and the top surface342may be a covalent, chemical or atomic bond. In some cases, cavities120may be formed after bonding wafer110to laminate340.

Laminate340may include at least one of an adhesive, an epoxy, a sacrificial layer on a wafer, a water-soluble adhesive, a solvent-dissolvable adhesive, a UV-releasable adhesive, or a heat-releasable adhesive.

Step301may include the placement of the host wafer110with through-substrate holes120, such as placement onto laminate340, or lamination of laminate340onto the surface of wafer110to form device311. The holes120may have a minimum of one sides (e.g., may be a circle) and up to an infinite number of sides, but preferably have 4 sides. The wafer thickness tw may be from 10 to 2,000 microns, but preferably 75 um.

FIG.3Bshows step302for forming device312, which includes chiplets130bonded to top surface342within cavities120. Step302may include bonding a frontside132of a plurality of chiplets130having the backside134and a frontside132to a portion378of the plurality of areas376of the top surface342of the adhesive laminate340. Bonding at step302may include directly attaching the frontsides132of the chiplets130to the portions378of the of areas376such that frontside132is bonded to and touching top surface342within the cavities120. The bond between the frontside132and the top surface342may be a covalent, chemical or atomic bond.

The chiplets130, typically have 4 sides, but could have anywhere between 0 and an infinite number of sides that are then aligned with and bonded into the through-substrate holes120of device311, face down (e.g., flip chip bonding) onto the adhesive laminate material340. The chiplets130can be of the same thickness tw or thicker or thinner than the thickness tw of wafer110.

Bonding at step302may include pick and place assembling a high-end pre-fabricated chiplet130into the cavities120of the top surface342of the adhesive laminate340.

Each chiplet130may include at least one of active device circuitry and interconnects to contact pads on a front surface of the chiplet. Each chiplet130may be a pre-fabricated transistor chiplet.

FIG.3Cshows step303for forming device313, which includes lateral dielectric material360molded between chiplets130and wafer110within cavities120. Step303may include molding a lateral dielectric material360between side surfaces236of the chiplets130and the side surfaces116of the wafer110within the cavities120. The lateral dielectric material360may mechano-chemically bond the side surfaces136of the chiplets130to the side surfaces116of the wafer. The lateral dielectric material360may fill gaps150between the chiplets130and the wafer110. The lateral dielectric material360may completely fill gap width gw and thickness tw of gaps150.

Molding at step303may include directly attaching the material360to side surfaces136of the chiplets130, top surface342of the adhesive340, and side surfaces116of the wafer110such that material360is touching side surfaces136, top surface342and side surfaces116. The bond between the material360, side surfaces136, top surface342and side surfaces116may be an a covalent, chemical or atomic bond. It may be an adhesive bond formed by pressure forming the material360into gaps350.

Step303may be performing a lateral chip bonding process that bonds chiplets130to wafer110of device312(e.g., seeFIGS.4A-4Cfor details). The aspect ratio, as defined by ratio of the thickness tw of the wafer (or chip) to the width gw of the gap150(e.g., the minimum distance between the vertical side of the chip236and the side of the through-hole116) can be on the order of 100:1, but typically would be 10:1. In some cases, thickness tw is 1000 um and width gw is 10 um.

FIGS.4A and4Bare flow diagrams showing two processes for the step303forming device313ofFIG.3Calso shown atFIG.4C. TheFIGS.4A and4Bprocesses may form device313by molding a lateral dielectric material360into gaps350. The flow chart ofFIGS.4A-4Cincludes only major process steps. Various conventional process steps (e.g. surface preparation, chemical mechanical processing (CMP), cleaning, inspection, deposition, photolithography, baking, annealing, monitoring, testing, etc.) may be performed before, between, after, and during the steps shown inFIGS.4A-4C.

FIG.4Ashows step401for forming device411, which includes a bump480of the lateral dielectric material360printed onto a chiplet backside134or a wafer back surface112. Step401may include using a printing process to print the bump480of the lateral dielectric material360into gaps350between the side surfaces136of the chiplets and the side surfaces116of the wafer110using a permanent screen, such as using the wafer with cavity as a screen to be printed on by the printer.

Step401may include a screen-printing process, where484may be a squeegee that spreads a ball480of bonding material over the surfaces134and112, and into the gaps350as shown inFIG.4C. Thus,FIG.4Ais a step of the process priorFIG.4Cwhere a bump of adhesive480no longer exists.

Step401may include using a printer482with printhead484that prints a bump480of the material360on the back surface and into the gaps350.

FIG.4Bshows step402for forming device412, which includes the bump480of the lateral dielectric material360pressured onto the backside134of device411. Step402may include using a molding process to mold the bump480of the lateral dielectric material360into gaps350between the side surfaces136of the chiplets and the side surfaces116of the wafer110using a vacuum and pressure. The molding may be done using a liquid compression molding technique such as liquid composite molding (LCM).

Printing at401and/or molding at402may us a squeegee or a squeegee process to print the bump480and/or mold the bump480into gaps350.

After either of step401or402,FIG.4Cshows step403for forming device313ofFIG.3C. Either of step401or402, may include mechano-chemically bonding bump480between side surfaces236of the chiplets130and the side surfaces116of the wafer110within the cavities120to form the lateral dielectric material360. Step403may include heating and/or curing of the molding of step401or402.

After step303,FIG.3Dshows step304for forming device314, which includes a backside capping370encapsulating the backside134of the chiplets, the back surface112of the wafer110and the top surfaces of the lateral dielectric material360. Step304may include encapsulating the backside134, the back surface112and on the top surfaces of the lateral dielectric material360with a backside capping layer370having a top surface372and a back surface374, such that the areas of cavities120are disposed over areas376of the top surface372of the backside capping layer370. As shown, portions376and areas378may be vertically aligned with respect to laminate340and layer370.

Encapsulating at step304may include directly attaching the backside134, the back surface112and on the top surfaces of the lateral dielectric material360to backside capping layer370such that layer370is touching backside134, back surface112and the top surfaces of material360. Encapsulating at step304may include embedding the chiplets130into the wafer110at the holes or at cavities120.

Encapsulating at step304may include encapsulating the restructured wafer/panel device313with a metallic version of layer370acting as a thermal plane, preferably having thickness te in the order of 5-25 microns thick, and making direct contact with the backside face134and front surface114of the chips130and of the wafer110.

The backside capping layer370may be a high-thermal-conductivity backside metallization layer that improves heat transfer away from the chiplet, such as to the wafers. It may form a “thermal plane” to conduct heat away from the chiplets. The backside capping layer370may have a coefficient of thermal conductivity greater than those of the wafer and of the chiplets. The backside capping layer370may have a coefficient of thermal expansion between those of the wafer and of the chiplets.

FIG.3Eshows step305for forming device315, which does not include adhesive laminate340, but does include layer370on the chiplets130, on the wafer110and on the lateral dielectric material360.FIG.3Eshows device314inverted and without laminate340, Step305may include removing or detaching the adhesive laminate340from the surfaces of the chiplets130, wafer110and lateral dielectric material360using a bath, liquid and/or heat. Step305may be the removal of the adhesive laminate340from device314.

Because chiplet130is then attached inside cavity120by material360, chiplet130is maintained in cavity120in the position it had relative to wafer110when they were attached to laminate340.

The chiplets130and wafer exposed bottom surfaces may be polished such as by chemical mechanical polishing (CMP) after laminate340is removed. In other cases, they are not polished. The exposed surfaces132may be surfaces with the electrical components that are then interconnected with the conductors510added inFIG.3F. In some cases, chiplet130can be arranged such that a surface fabricated as a side surface is arranged and maintained parallel to the front surface of wafer110. This capability can be used to increase the number of component chiplets130embedded in wafer110, and/or when the side surface of chiplet130maintained parallel to the front surface of wafer110has a specific function. This might be the case, for example, when chiplet130is a semiconductor laser chip and its side surface is a laser emitting side.

FIG.3Fshows step306for forming device316, which includes interconnects510connecting contacts118of the chiplets to contacts138of the wafer. Step306may include forming interconnects510directly on the lateral dielectric material360and connecting the contacts of the chiplets to contacts of the wafer. Interconnects510may be formed by electroplating a pattern of interconnects510through a photoresist and then dissolving the photoresist. Interconnects510may be formed by deposition of, masking over the pattern of interconnects510and etching away non-patterned parts of a conductive material such as a metal.

Beneficially, interconnects510can be formed without the cost, processing or material height of using solder or contact bumps on contacts of either the chiplets130or the wafer110.

Forming at step306may include directly attaching the interconnects510to the material360such that the interconnects510are touching the top surface of material360. Forming at step306may include forming direct interconnect510routs or traces from the contacts138of chiplets130, directly on (e.g., bonded to, directly attached to, touching and/or with no air gap between the interconnect and the dielectric) the lateral dielectric material360, and to wafer electrical routing or contacts118.

It is considered that the host wafer110can be vertically diced at dicing lines (shown by the vertical bars inFIG.3F) along a perimeter386of the wafer around at least one chiplet to form a chip having the at least one chiplet and an area of the wafer surrounding the at least one chiplet.

FIGS.2and3Fmay shows how the interconnect structure510directly sits on top of the dielectric bonding material360between the chiplets130and wafer110.

Beneficially, the step303lateral mechano-chemical chiplet bonding and/or use of the dielectric360: (1) is low cost such as by using low cost processes of step303and materials such as dielectric360; and (2) is volume-scalable such as by allowing the size and number of chiplets130to be easily changed. Beneficially, the step303lateral mechano-chemical chiplet bonding and/or use of the dielectric360mitigates coefficient of thermal expansion mismatch between the silicon wafer frame110and the chiplets130, such as by the dielectric360having a coefficient of thermal expansion close to one of, or between that of, wafer110and the chiplets130. Beneficially, the step303lateral mechano-chemical chiplet bonding and/or use of the dielectric360allows: (1) direct interconnect routing from the chiplets130to the wafer110electrical routing (e.g., with no dielectric/air gap); and (2) low loss high-performance DC, RF, and mm-wave signal transfer between the chiplets130and the wafer110electrical routing, where (1) and (2) can use interconnects510between contacts of the chiplets130and wafer110that can be formed on the surface of dielectric360.

Beneficially, the step303lateral mechano-chemical chiplet bonding and/or use of the dielectric360, as compared to using a semiconductor or conductor material in place of dielectric360, reduces noise and changes in frequency in interconnect routing from the chiplets130to the wafer110electrical routing. Beneficially, the step303lateral mechano-chemical chiplet bonding and/or use of the dielectric360, as compared to using a semiconductor or conductor material in place of dielectric360, reduces capacitance in high frequency signals and has lower signal loss in interconnect routing from the chiplets130to the wafer110electrical routing. Beneficially, the step303lateral mechano-chemical chiplet bonding and/or use of the dielectric360, as compared to using a semiconductor or conductor material in place of dielectric360, reduces the cost of the material of and processing for forming the lateral bonding material between the chiplets130and the wafer110.

In addition to those benefits, that lateral mechano-chemical dielectric bonding process is augmented by benefits of steps304-304and/or use of backside capping layer370which provide: a high-thermal-conductivity backside metallization370of the restructured wafer314or200to improve heat transfer from the chiplets130to the wafer110and layer370which may be a “thermal plane” for the device200.

According to the process301-306, a plurality of electronic assemblies can be manufactured simultaneously, in which case pluralities of component chiplets130are provided and attached to a plurality of predetermined locations (e.g., of areas378) on laminate340. The chiplet130can actually comprise a plurality of identical or distinct component chips, each having each their frontside132attached temporarily to the predetermined locations of top surface342. In some cases, the various component chips can have different thicknesses, subject to the constraint that they be no thicker than wafer110.

Chiplets130are preferably pre-tested to verify their functionality. As a result, the yield of the final device200or diced devices is much improved over integration of component chips, in which the functionality of the component chips is not verified until after integration.

Embedding of a chiplet130(comprising a single chip or a plurality of component chips, etc.) in a dielectric360filled cavity120allows a desirable increase in the drain of any chip-produced heat to the wafer110during use of the chiplet. The increased drain significantly beneficially limits any change in size of the chiplet due to a temperature change and allows any mechanical strain due to such size change to beneficially remain moderate. Another advantage is that the dielectric360may be resilient and pliable to better absorb the size change. This heat drain is improved by connecting the bottom of the chiplet130to a metal backside capping layer370, such as a metal plate, formed on a portion of the bottom surface of wafer110. As illustrated inFIG.3, backside capping layer370of metal (for example, gold) can be formed on the bottom of chiplet130and wafer110. Doing so improves the thermal conductivity and interface between chiplet130, material360and wafer110, thus further increasing the desirable drain of any chip-produced heat from the chiplet and to the layer370during use of the chiplet.

Advantageously, by allowing different electrical component ones of chiplets130to be manufactured separately from each other and from wafer110, electronic components of those all chiplets130and wafer110can be tested separately before assembling them. In case one of the components of a certain electrical component chiplet130or of wafer110has poor fabrication yields, it is possible to separately spend time and money to improve the fabrication yield of that electrical component separately to produce a completed product device200or die thereof, having the chiplets130together in the cavities of the wafer110. For example, If an electrical component of a certain chiplet type of the chiplets130has poor fabrication yield, it is possible to separately spend time and money to improve the fabrication yield of that electrical component chiplet type without spending time and money to improve the components of the other types of chiplets130or of wafer110, to produce a completed product device200or die thereof, having the chiplets130and wafer110.

Further, because embodiments allow fabricating different electrical component ones of chiplets130separately from each other and from wafer110, all of the component types of chiplets130and wafer110do not need to be exposed to steps in the fabrication of all the different electrical component ones of chiplets130that could potentially damage other ones of chiplets130or damage wafer110.

Thus, embodiments can reduce manufacturing costs by using small component chips in chiplets130having specific features and made of exotic expensive materials, in combination with integrated circuits of other chiplets130and/or wafer110having more common features and made of cheaper common materials.

According to embodiments, chiplets130can include a GaN, InP or GaAs electrical component and can be fabricated on a substrate such as Si, SiGe, InP, GaAs, Alumina, or diamond. In some cases, electrical components or integrated circuits of host wafer110can comprise metal routing and passive components fabricated at the wafer scale. In some cases, interconnection510can be made using conductors made out of thin films, thick, plated interconnects, multi-layers, etc. The interconnections can for example be made using the back-end steps of a manufacturing process.

Closing Comments

Throughout this description, the embodiments and examples shown should be considered as exemplars, rather than limitations on the apparatus and procedures disclosed or claimed. Although many of the examples presented herein involve specific combinations of method acts or system elements, it should be understood that those acts and those elements may be combined in other ways to accomplish the same objectives. With regard to flowcharts, additional and fewer steps may be taken, and the steps as shown may be combined or further refined to achieve the methods described herein. Acts, elements and features discussed only in connection with one embodiment are not intended to be excluded from a similar role in other embodiments.

As used herein, “plurality” means two or more. As used herein, a “set” of items may include one or more of such items. As used herein, whether in the written description or the claims, the terms “comprising”, “including”, “carrying”, “having”, “containing”, “involving”, and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of”, respectively, are closed or semi-closed transitional phrases with respect to claims. Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements. As used herein, “and/or” means that the listed items are alternatives, but the alternatives also include any combination of the listed items.