Patent ID: 12248022

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

FIG.1illustrates a schematic view of an apparatus100for testing a device under test (DUT), in accordance with some embodiments of the present disclosure. The apparatus100can also be referred to as a system or equipment. The apparatus100includes a testing device10and a load board20. The testing device10includes a power supply device12, a clock device14, a data generating device16and a comparison device18. The testing device10can be electrically connected to the load board20. Data, power, commands or signals can be communicated between the testing device10and the load board20.

The power supply device12, the clock device14, the data generating device16and the comparison device18can be electrically connected to each other. Data, power, commands or signals can be communicated between the power supply device12, the clock device14, the data generating device16and/or the comparison device18.

Although the power supply device12, the clock device14, the data generating device16and the comparison device18shown inFIG.1are included in the testing device10, it can be contemplated that they may be disposed apart from each other. Although the power supply device12, the clock device14, the data generating device16and the comparison device18shown inFIG.1are individual devices, it can be contemplated that some of them can be integrated into a single device. In some embodiments, the power supply device12, the clock device14, the data generating device16and the comparison device18can be implemented by software or instruction codes stored in the hardware.

The power supply device12can be configured to provide power to the load board20. The power supply device12can be configured to provide current to the load board20. The power supply device12can be configured to provide voltages to the load board20. The power supply device12can be configured to provide direct current (DC) to the load board20. The power supply device12can be configured to provide alternating current (AC) to the load board20.

The clock device14can be configured to provide clock signals to the load board20. The data generating device16can be configured to provide data to the load board20. In some embodiments, the data generating device16may provide analog signals to the load board20. In some embodiments, the data generating device16may provide digital signals to the load board20. In some embodiments, the data generating device16may provide data streams to the load board20. In some embodiments, the data generating device16may provide bit streams to the load board20.

The comparison device18can be configured to compare two data streams. The comparison device18can be configured to compare two bit streams. The comparison device18can be configured to compare a data stream provided by the data generating device16and a data stream received from the load board20. The comparison device18can provide the comparison results to, for example, a processing unit (not shown) of the apparatus100for determining whether defects exist within the DUT.

One or several DUTs30can be mounted on the load board20. The pins or connection pads of the DUTs30can be electrically connected to the pins or connection pads of the load board20. Data, power, commands or signals can be communicated between the DUTs30and the load board20. Data, power, commands or signals from the testing device10can be transmitted to the DUTs30mounted on the load board20.

In some embodiments, the apparatus100can be configured to test only one DUT30. In some embodiments, the apparatus100can be configured to test several DUTs30in parallel. In some embodiments, the apparatus100can be configured to test several DUTs30simultaneously.

In some embodiments, the testing device10may include a display screen (not shown). The comparison results provided by the comparison device18can be displayed on the display screen. In some embodiments, the comparison results provided by the comparison device18can be displayed to a user for he or she to determine whether any defects are found in the DUT30. In some embodiments, the testing device10can determine whether defects are found in the DUT30based on the results provided by the comparison device18. In some embodiments, the testing device10may issue visual or acoustic alerts when defects are found in the DUT30.

FIG.2illustrates a schematic view of a DUT, in accordance with some embodiments of the present disclosure.FIG.2shows a schematic view of a DUT30. In some embodiments, the DUT30may be a semiconductor device. In some embodiments, the DUT30may be a semiconductor chip.

The DUT30may include several input/output (I/O) ports. The DUT30includes ports30A,30B,30C and30D. In some embodiments, the DUT30may include more I/O ports. In some embodiments, the DUT30may include fewer I/O ports. The DUT30may receive data, power, commands or signals from the ports30A,30B,30C and30D. The DUT30may output data, power, commands or signals through the ports30A,30B,30C and30D.

The DUT30may include several logic units. Referring toFIG.2, the DUT30includes logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fi. The index “i” is a positive integer. The logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fican be connected in series. The logic unit30F1may receive data from the port30A. The logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fimay be merely a portion of the DUT30. The DUT30may include additional units/circuits other than the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fi.

The logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fican be the portion that is used for data storage for the DUT30. In some embodiments, logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fimay occupy more than 20% of the area of the DUT30. If defects exist in any of the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fi, the performance of the DUT30can be adversely affected. If defects exist in any of the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fithe DUT30may not work properly.

The data received from the port30A can be transmitted, unit by unit, from the logic units30F1to the logic units30Fi. For example, the logic unit30F1may forward the data received from the port30A to the logic unit30F2. The logic30F2may forward the data received from the logic unit30F1to the logic unit in the next stage (i.e.,30F3), and so on. The logic unit30Fimay output data through the port30B. The data streams provided through the port30A, after transmission through the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fi, can be outputted by the port30B. In other embodiments, the data can be transmitted to the port30A in parallel. For example, a data stream can be inputted to the logic units30F1to the logic units30Fisimultaneously.

In some embodiments, power can be provided to the DUT30through the port30C. In some embodiments, current/voltage can be provided to the DUT30through the port30C. The current/voltage received from the port30C can be provided to each of the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fi. In some embodiments, signals can be provided to the DUT30through the port30D. In some embodiments, clock signals can be provided to the DUT30through the port30D. The clock signals received from the port30D can be provided to each of the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fi.

In some embodiments, the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fican be flip flops. In some embodiments, the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fican be flip flops that include data storage capability.

FIG.3Aillustrates a schematic view of an operation for testing a DUT, in accordance with some embodiments of the present disclosure.FIG.3shows an operation for testing a DUT30′. For simplicity of illustration, the DUT30′ includes only five logic units30F1,30F2,30F3,30F4and30F5. It can be contemplated that the operation shown inFIG.3Acan also be applied to the DUT30which includes logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fi.

For simplicity of illustration, only the power supply device12and the clock device14are depicted together with the DUT30′ inFIG.3A. It can be contemplated that the DUT30′ is mounted on the load board20, and is able to receive signals/data from the testing device10or to transmit signals/data to the testing device10. For simplicity of illustration, I/O ports of the DUT30′ are omitted inFIG.3A. It can be contemplated that the DUT30′ includes I/O ports similar to the ports30A,30B,30C and30D shown inFIG.2.

The operation shown inFIG.3Ais conducted during time duration T1. During the time duration T1, the power supply device12is configured to provide a voltage V1to the logic units30F1,30F2,30F3,30F4and30F5. During the time duration T1, data ds1is provided, for example, by the data generating device16, to the DUT30′. The data ds1may include several bits. The number of bits of the data ds1can be identical to the number of the logic units. InFIG.3A, the data ds1including five bits of “1” is provided to the DUT30′ for testing the logic units30F1,30F2,30F3,30F4and30F5. In some embodiments, a number i of bits should be provided to the DUT30shown inFIG.2if the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fineed to be tested.

The clock device14is configured to provide a clock signal to the DUT30′ during the time duration T1. The clock signal provided by the clock device14may include several signal edges. Some of the signal edges of the clock signal may include a rising edge (or positive edge), which is a low-to-high transition of the clock signal. Some of the signal edges of the clock signal may include a falling edge (or negative edge), which is the high-to-low transition of the clock signal.

A signal edge of the clock signal may trigger a logic unit to capture a bit transmitted from its previous stage. A signal edge of the clock signal may trigger a logic unit to shift a bit to its next stage. For example, a signal edge of the clock signal can trigger the logic unit30F1to capture a bit transmitted from the data generating device16. Another signal edge of the clock signal can trigger the logic unit30F1to shift a bit to the logic unit30F2. Similarly, a signal edge of the clock signal can trigger the logic unit30F2to capture a bit transmitted from the logic unit30F1. Another signal edge of the clock signal can trigger the logic unit30F2to shift a bit to the logic unit30F3.

In the example shown inFIG.3A, the data ds1can be transmitted to and stored in the logic units30F1,30F2,30F3,30F4and30F5after five signal edges of the clock signal.

FIG.3Billustrates a schematic view of an operation for testing a DUT, in accordance with some embodiments of the present disclosure. The operation shown inFIG.3Bcan be conducted during time duration T2after the time duration T1. During the time duration T2, the clock device14is configured to stop providing clock signals to the DUT30′. In some embodiments, the clock device14is configured to provide a clock signal that does not include signal edges to the DUT30′.

During the time duration T2, the power supply device12is configured to provide a voltage V2to the DUT30′. The voltage V2includes a level different from that of the voltage V1. The voltage V2includes a level lower than that of the voltage V1. The level of the voltage V2can be adjusted in accordance with the characteristics of the DUT30′. The characteristics of the DUT30′ may include, for example, but are not limited to, the technologies of manufacturing the DUT30′, the application field of the DUT30′, the operation conditions of the DUT30′, or the functions of the DUT30′.

In some embodiments, the voltage V2can be 20% less than the voltage V1. In some embodiments, the voltage V2can be 50% less than the voltage V1. In some embodiments, the voltage V2can be 80% less than the voltage V1. In some embodiments, a ratio of the voltage V2to the voltage V1ranges from 80% to 20%.

The time duration T2can last for more than 50 milliseconds (ms). The time duration T2can last for more than 80 ms. The time duration T2can last for more than 100 ms. The voltage V2can be applied to the DUT30′ for more than 100 ms. The time duration T2can be adjusted in accordance with the characteristics of the DUT30′. The characteristics of the DUT30′ may include, for example, but are not limited to, the technologies of manufacturing the DUT30′, the application field of the DUT30′, the operation conditions of the DUT30′, or the functions of the DUT30′.

If defects exist in some of the logic units30F1,30F2,30F3,30F4and30F5, current leakage may occur during the time duration T2. The current leakage may affect or change the bit stored in the logic units.FIG.3Bshows an example of defects existing within the logic unit30F3, and the bit stored in the logic unit30F3changes from “1” to “0” during the time duration T2. In some embodiments, defects may exist in a logic unit different from the logic unit30F3.

FIG.3Cillustrates a schematic view of an operation for testing a DUT, in accordance with some embodiments of the present disclosure. The operation shown inFIG.3Ccan be conducted during time duration T3after the time duration T2. During the time duration T3, the power supply device12is configured to provide a voltage V1to the DUT30′. During the time duration T3, the clock device14is configured to provide a clock signal to the DUT30′.

During the time duration T3, data ds2is provided, for example, by the data generating device16, to the DUT30′. The data ds2can have an identical number of bits to that of the data ds1. The data ds2can have an identical number of digits to that of the data ds1. The data ds2may include bits b1, b2, b3, b4and b5. Bits b1, b2, b3, b4and b5can be fed into the logic units30F1,30F2,30F3,30F4and30F5in sequence. Bits b1, b2, b3, b4and b5can be fed into the logic units30F1,30F2,30F3,30F4and30F5sequentially, triggered by the signal edges of the clock signal provided by the clock device14.

The purpose of feeding the data ds2into the DUT30′ is to have the data ds1′ outputted by the DUT30′. Therefore, the data ds2can include arbitrary combinations of bits “0” or “1.” After the bits b1, b2, b3, b4and b5are fed into the DUT30′, data ds1′ can be outputted from the DUT30′. The data ds1′ can include the bits that are stored in the logic units30F1,30F2,30F3,30F4and30F5, at the end of the time duration T2.

The data ds1′ shown inFIG.3Ccan be compared with the data ds1shown inFIG.3A, for example, by the comparison device18. If some of the bits of the data ds1′ are different from those of the data ds1, it can be determined, for example, by the testing device10, that defects exist in the DUT30′. In some embodiments, the testing device10may issue visual or acoustic alerts when defects are found in the DUT30′.

FIG.4Aillustrates a schematic view of an operation for testing a DUT, in accordance with some embodiments of the present disclosure. The operation shown inFIG.4Acan be conducted during time duration T4. In some embodiments, the operation shown inFIG.4Acan be conducted after the operation shown inFIG.3C, and the time duration T4can be after the time duration T3. In some embodiments, the operation shown inFIG.4Acan be conducted independent of the operations shown inFIGS.3A,3B and3C.

During the time duration T4, the power supply device12is configured to provide a voltage V1to the DUT30′. During the time duration T4, the clock device14is configured to provide a clock signal to the DUT30′.

During the time duration T4, data ds3is provided, for example, by the data generating device16, to the DUT30′. The data ds3may include several bits. The number of bits of the data ds3can be identical to the number of the logic units. The data ds3can have an identical number of bits/digits to that of the data ds1. The data ds3can be different from the data ds1shown inFIG.3A. InFIG.4A, the data ds3including five bits of “0” is provided to the DUT30′ for testing the logic units30F1,30F2,30F3,30F4and30F5. In some embodiments, a number i of bits should be provided to the DUT30shown inFIG.2if the logic units30F1,30F2, . . . ,30Fi-1,30Fi-2and30Fineed to be tested.

In the example shown inFIG.4A, the data ds3can be transmitted to and stored in the logic units30F1,30F2,30F3,30F4and30F5after five signal edges of the clock signal provided by the clock device14.

FIG.4Billustrates a schematic view of an operation for testing a DUT, in accordance with some embodiments of the present disclosure. The operation shown inFIG.4Bcan be conducted during time duration T5after the time duration T4. During the time duration T5, the clock device14is configured to stop providing clock signals to the DUT30′. In some embodiments, the clock device14is configured to provide a clock signal that does not include signal edges to the DUT30′.

During the time duration T5, the power supply device12is configured to provide a voltage V2to the DUT30′. The voltage V2includes a level different from that of the voltage V1. The voltage V2includes a level lower than that of the voltage V1. The level of the voltage V2can be adjusted in accordance with the characteristics of the DUT30′. The characteristics of the DUT30′ may include, for example, but are not limited to, the technologies of manufacturing the DUT30′, the application field of the DUT30′, the operation conditions of the DUT30′, or the functions of the DUT30′.

In some embodiments, the voltage V2can be 20% less than the voltage V1. In some embodiments, the voltage V2can be 50% less than the voltage V1. In some embodiments, the voltage V2can be 80% less than the voltage V1. In some embodiments, a ratio of the voltage V2to the voltage V1ranges from 80% to 20%.

The time duration T5can last for more than 50 milliseconds (ms). The time duration T5can last for more than 80 ms. The time duration T5can last for more than 100 ms. The voltage V2can be applied to the DUT30′ for more than 100 ms. The time duration T5can be adjusted in accordance with the characteristics of the DUT30′. The characteristics of the DUT30′ may include, for example, but are not limited to, the technologies of manufacturing the DUT30′, the application field of the DUT30′, the operation conditions of the DUT30′, or the functions of the DUT30′.

If defects exist in some of the logic units30F1,30F2,30F3,30F4and30F5, current leakage may occur during the time duration T5. The current leakage may affect or change the bit stored in the logic units.FIG.4Bshows an example of defects existing within the logic unit30F3, and the bit stored in the logic unit30F3changes from “0” to “1” during the time duration T5. In some embodiments, defects may exist in a logic unit different from the logic unit30F3.

FIG.4Cillustrates a schematic view of an operation for testing a DUT, in accordance with some embodiments of the present disclosure. The operation shown inFIG.4Ccan be conducted during time duration T6after the time duration T5. During the time duration T6, the power supply device12is configured to provide a voltage V1to the DUT30′. During the time duration T6, the clock device14is configured to provide a clock signal to the DUT30′.

During the time duration T6, data ds2is provided, for example, by the data generating device16, to the DUT30′. The data ds2may include bits b1, b2, b3, b4and b5. Bits b1, b2, b3, b4and b5can be fed into the logic units30F1,30F2,30F3,30F4and30F5in sequence. Bits b1, b2, b3, b4and b5can be fed into the logic units30F1,30F2,30F3,30F4and30F5sequentially, triggered by the signal edges of the clock signal provided by the clock device14.

The purpose of feeding the data ds2into the DUT30′ is to have the data ds1′ outputted by the DUT30′. Therefore, the data ds2can include arbitrary combinations of bits “0” or “1.” After the bits b1, b2, b3, b4and b5are fed into the DUT30′, data ds3′ can be outputted from the DUT30′. The data ds3′ can include the bits that stored in the logic units30F1,30F2,30F3,30F4and30F5, at the end of the time duration T5.

The data ds3′ shown inFIG.4Ccan be compared with the data ds3shown inFIG.4A, for example, by the comparison device18. If some of the bits of the data ds3′ are different from those of the data ds3, it can be determined, for example, by the testing device10, that defects exist in the DUT30′. In some embodiments, the testing device10may issue visual or acoustic alerts when defects are found in the DUT30′.

FIG.5Aillustrates a schematic view of a logic unit, in accordance with some embodiments of the present disclosure.FIG.5Ashows a logic unit30F1. The logic unit30F1includes a multiplexer32, a flip flop34, a flip flop36and an inverter38. The multiplexer32can be electrically connected to the flip flop34. The flip flop34can be electrically connected to the flip flop36. The inverter38can be connected between the flip flop34and the flip flop36.

The multiplexer32includes input ports32i1,32i2and32i3. The multiplexer32includes an output port32o1. The flip flop34includes input ports34i1and34i2. The flip flop34includes output ports34o1and34o2. The flip flop36includes input ports36i1and36i2. The flip flop36includes output ports36o1and36o2. The output port32o1of the multiplexer32can be connected to the input port34i1of the flip flop34. The output port34o1of the flip flop34can be connected to the input port36i1of the flip flop36. The inverter38can be connected between the input port34i2of the flip flop34and the input port36i2of the flip flop36.

In some embodiments, the input port32i2of the multiplexer32may receive the test data (for example, the data ds1, ds2and ds3shown inFIGS.3A-4C) provided by the data generating device16. In some embodiments, the input port34i2of the flip flop34may receive a clock signal CLK provided by the clock device14. The clock signal CLK provided by the clock device14can be inverted by the inverter38to beCLK, before it is received by the input port36i2of the flip flop36.

The flip flop34can be a scan D flip flop. The flip flop36can be a scan D flip flop. The flip flop34can be a master flip flop. The flip flop36can be a slave flip flop. The flip flops34and36can be configured as a latch for data storage.

The data outputted by the output port34o1of the flip flop34can be an inversion of the data outputted by the output port34o2of the flip flop34. For example, if the data outputted by output port34o1of the flip flop34is a logic “0,” then the data outputted by output port34o2of the flip flop34will be a logic “1,” and vice versa. The data outputted by the output port36o1of the flip flop36can be an inversion of the data outputted by the output port36o2of the flip flop36. For example, if the data outputted by output port36o1of the flip flop36is a logic “0,” then the data outputted by output port36o2of the flip flop36will be a logic “1,” and vice versa.

FIG.5Billustrates a schematic view of a logic unit, in accordance with some embodiments of the present disclosure.FIG.5Bshows one of the possible implementations of the flip flop34. The flip flop36can be implemented in a manner similar to that shown inFIG.5B.

Referring toFIG.5B, the flip flop34includes an inverter341, AND gates342and343, and NOR gates344and345. The input port34i1of the flip flop34can receive data provided by another circuit (for example, the multiplexer32). The input port34i2of the flip flop34can receive signals provided by another circuit (for example, the clock device14).

The data outputted by the output port34o1of the flip flop34can be an inversion of the data outputted by the output port34o2of the flip flop34. For example, if the data outputted by output port34o1of the flip flop34is a logic “0,” then the data outputted by output port34o2of the flip flop34will be a logic “1,” and vice versa.

FIG.6illustrates a flowchart including various operations of a method for testing a DUT, in accordance with some embodiments of the present disclosure.

In operation82, data is provided to a DUT. For example, the data ds1can be provided to the DUT30′. In operation84, the power provided to the DUT is reduced, and the reduced power is provided to the DUT for a time duration. For example, the power provided to the DUT30′ is reduced from the voltage V1to the voltage V2, and the voltage V2is provided to the DUT30′ for the time duration T2. In operation86, the data of the DUT is shifted out. For example, the data stored in the DUT30′ can be shifted out as the data ds1′.

FIG.7Aillustrates a flowchart including various operations of a method for testing a DUT, in accordance with some embodiments of the present disclosure.FIG.7Ashows operations102to112. The operations102to112can be performed by the apparatus100shown inFIG.1. Although the operations102to112are depicted in a sequential manner, it does not mean that the operations102to112must be conducted according to the order shown inFIG.7A.

In operation102, a voltage V1is provided to a DUT during a time duration T1. The voltage V1can be provided, for example, by the power supply device12to a DUT30mounted on the load board20. In operation104, data ds1is provided to the DUT during the time duration T1. The data ds1can be provided, for example, by the data generating device16to a DUT30mounted on the load board20. Although inFIG.7A, the operation102is depicted as being followed by the operation104, it can be contemplated that the operations102and104may be conducted in parallel.

In operation106, a voltage V2is provided to a DUT during a time duration T2after the time duration T1. The voltage V2can be provided, for example, by the power supply device12to a DUT30mounted on the load board20. The voltage V2can be different from the voltage V1. The voltage V2can be lower than the voltage V1. In some embodiments, the level of the voltage V2ranges from 20% to 80% of the level of the voltage V1. In some embodiments, the duration T2may last, for example, greater than 100 ms.

In operation108, a voltage V1is provided to a DUT during a time duration T3after the time duration T2. The voltage V1can be provided, for example, by the power supply device12to a DUT30mounted on the load board20. In operation110, data ds2is provided to the DUT during the time duration T3. The data ds2can be provided, for example, by the data generating device16to a DUT30mounted on the load board20. Although inFIG.7A, the operation108is depicted as being followed by the operation110, it can be contemplated that the operations108and110may be conducted in parallel. The purpose of feeding the data ds2into the DUT30is to have the data stored in the DUT to be output by the DUT30. Therefore, the data ds2can include arbitrary combinations of bits “0” or “1.”

In operation112, the data ds1′ outputted by the DUT30can be compared with the data ds1provided during the time duration T1. The operation112can be conducted by, for example, the comparison device18. The apparatus100can determine whether defects exist in the DUT30based on results provided by the comparison device18. The apparatus100can determine whether defects exist in the DUT30based on the comparison between the data ds1and the data ds1′.

FIG.7Billustrates a flowchart including various operations of a method for testing a DUT, in accordance with some embodiments of the present disclosure.FIG.7Bshows operations114to124. The operations114to124can be performed by the apparatus100shown inFIG.1. Although the operations114to124are depicted in a sequential manner, it does not mean that the operations114to124must be conducted according to the order shown inFIG.7B.

The operation114shown inFIG.7Bcan be conducted after the operation112ofFIG.7A. In operation114, a voltage V1is provided to a DUT during a time duration T4after the time duration T3. The voltage V1can be provided, for example, by the power supply device12to a DUT30mounted on the load board20.

In operation116, data ds3is provided to the DUT during the time duration T4. The data ds3can be provided, for example, by the data generating device16to a DUT30mounted on the load board20. The data ds3can be different from the data ds1provided in the time duration T1. The data ds3can have an identical number of bits to that of the data ds1. The data ds3can have an identical number of digits to that of the data ds1. Although inFIG.7B, the operation114is depicted as being followed by the operation116, it can be contemplated that the operations114and116may be conducted in parallel.

In operation118, a voltage V2is provided to a DUT during a time duration T5after the time duration T4. The voltage V2can be provided, for example, by the power supply device12to a DUT30mounted on the load board20. The voltage V2can be different from the voltage V1. The voltage V2can be lower than the voltage V1. In some embodiments, the level of the voltage V2ranges from 20% to 80% of the level of the voltage V1. In some embodiments, the duration T2may last, for example, greater than 100 ms.

In operation120, a voltage V1is provided to a DUT during a time duration T6after the time duration T5. The voltage V1can be provided, for example, by the power supply device12to a DUT30mounted on the load board20. In operation122, data ds2is provided to the DUT during the time duration T6. The data ds2can be provided, for example, by the data generating device16to a DUT30mounted on the load board20. Although inFIG.7B, the operation120is depicted as being followed by the operation122, it can be contemplated that the operations120and122may be conducted in parallel. The purpose of feeding the data ds2into the DUT30is to have the data stored in the DUT to be output by the DUT30. Therefore, the data ds2can include arbitrary combinations of bits “0” or “1.”

In operation124, the data ds3′ outputted by the DUT30can be compared with the data ds3provided during the time duration T4. The operation124can be conducted by, for example, the comparison device18. The apparatus100can determine whether defects exist in the DUT30based on results provided by the comparison device18. The apparatus100can determine whether defects exist in the DUT30based on the comparison between the data ds3and the data ds3′.

The operations shown inFIGS.6,7A and7Bcan also be referred to a power cycling screen method for detecting weak flip flops.

The operations shown inFIGS.6,7A and7Bcan be used to check the data storage function of a DUT. The operations shown inFIGS.6,7A and7Bcan be used to check the data storage function of a logic circuit. The operations shown inFIGS.6,7A and7Bcan be used to detect tiny current leakage that exists in the flip flops. The operations shown inFIGS.6,7A and7Bcan be used to detect tiny defects that exists in the flip flops.

The tiny current leakage may not be easily detected if no “power cycling” operation is involved. That is, the tiny current leakage may not be easily detected if a lower power (for example, the voltage V2) is provided to the DUT for a predetermined time duration (for example, the time duration T2).

Some embodiments of the present disclosure provide an apparatus for testing a device under test (DUT). The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.

Some embodiments of the present disclosure provide a method for testing a logic device. The method includes providing a first voltage to the logic device in a first time duration. The method includes providing first data to the logic device in the first time duration. The method includes providing a second voltage to the logic device in a second time duration after the first time duration. In some embodiments, the second voltage is different from the first voltage.

Some embodiments of the present disclosure provide a method for testing a semiconductor device. The method includes providing a first voltage and first data to the semiconductor device. The method includes providing a second voltage different from the first voltage to the semiconductor device for a first time duration. The method includes providing the first voltage and second data to the semiconductor device. The method includes comparing the data outputted by the semiconductor device with the first data.

The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.