Patent ID: 12211891

DETAILED DESCRIPTION

Drawings of a semiconductor device according to some embodiments show capacitors and electrode supports included in a dynamic random access memory (DRAM).

FIG.1is a schematic plan view for explaining the semiconductor device according to some embodiments.FIG.2is an enlarged plan view of a portion P ofFIG.1.FIGS.3and4are example diagrams taken along A-A and B-B ofFIG.2.FIG.5is an enlarged plan view of a portion Q ofFIG.1.FIG.6is an example diagram taken along C-C ofFIG.5.FIG.7is a diagram for explaining shapes of a first lower electrode ofFIG.2and a second lower electrode ofFIG.5.

For simplicity of illustration, a lower electrode210, a capacitor insulating (e.g., dielectric) film211, and an upper electrode212are not shown inFIG.1. In addition, the capacitor insulating film211and the upper electrode212are not shown inFIGS.2and5. When cuttingFIG.5in the same manner as in B-B ofFIG.2, it may be similar toFIG.4except that the lower electrode210bends.

Referring toFIGS.1to7, the semiconductor device according to some embodiments may include a first capacitor block CAP_ST1.

The first capacitor block CAP_ST1may be disposed on the substrate100. The first capacitor block CAP_ST1may include a plurality of lower electrodes210, a capacitor dielectric film211, an upper electrode212, a first electrode support50, and a second electrode support60.

The substrate100may be bulk silicon or silicon on insulator (SOI). Moreover, the substrate100may be a silicon substrate or may include other materials, for example, but are not limited to, silicon germanium, silicon germanium on-insulator (SGOI), indium antimonide, lead tellurium compounds, indium arsenide, indium phosphate, gallium arsenide or gallium antimonide.

The substrate100may be formed with unit elements necessary for forming a semiconductor element such as various types of active elements or passive elements. The unit elements may be, for example, cell transistors such as a DRAM (Dynamic Random Access Memory) or a flash memory.

A plurality of lower electrodes210may be disposed on the substrate100. Each lower electrode210may extend long (i.e., longitudinally) in a fourth direction DR4.

The lower electrode210may have, for example, a pillar shape. The lower electrode210may have a solid pillar shape.

The plurality of lower electrodes210may be repeatedly arranged/aligned with each other along a first direction DR1and a second direction DR2. For example, each lower electrode210may be aligned with first ones of the lower electrodes210in the first direction DR1and may be aligned with second ones of the lower electrodes210in the second direction DR2. The first direction DR1and the second direction DR2may be orthogonal to each other, but are not limited thereto. The first direction DR1and the second direction DR2may each be orthogonal (i.e., perpendicular) to a fourth direction DR4.

The plurality of lower electrodes210may be repeatedly arranged/aligned in the first direction DR1. The lower electrodes210arranged/aligned in the first direction DR1may be disposed to be spaced apart by a first distance/pitch. The first distance/pitch may be a shortest distance between the side walls of ones of the lower electrodes210adjacent to each other in the first direction DR1.

In a center region of the first capacitor block CAP_ST1, the first distance/pitch between the lower electrodes210arranged/aligned in the first direction DR1may different from the first distance/pitch between the lower electrodes210arranged/aligned in the first direction DR1in an edge region of the first capacitor block CAP_ST1. A description thereof will be provided later.

The lower electrodes210repeatedly arranged/aligned in the first direction DR1may also be repeatedly arranged/aligned in the second direction DR2. The lower electrodes210repeatedly arranged/aligned in the second direction DR2may not all be linearly arranged along the second direction DR2.

The lower electrodes210arranged/aligned in the second direction DR2may be arranged in a zigzag manner. More specifically, the plurality of lower electrodes210may include a first group of the lower electrodes210and a second group of the lower electrodes210that are repeatedly arranged/aligned in the first direction DR1. The first group of the lower electrodes210and the second group of the lower electrodes210may be adjacent to each other in the second direction DR2. No additional group of lower electrodes210repeatedly arranged/aligned in the first direction DR1is disposed between the first group of the lower electrodes210and the second group of the lower electrodes210.

As shown inFIG.2, a first center of each lower electrode210included in the first group of the lower electrodes210and a second center of each lower electrode210included in the second group of the lower electrodes210are not aligned along the second direction DR2.

In other words, an extension line passing through the center of each lower electrode210included in the first group of the lower electrodes210and extending in the second direction DR2does not pass through the center of each lower electrode210included in the second group of the lower electrodes210.

The plurality of lower electrodes210may be repeatedly arranged/aligned to be closest to each other in the first direction DR1and the third direction DR3. For example, the first distance/pitch between the lower electrodes210adjacent to each other in the first direction DR1may be substantially the same as the second distance/pitch between the lower electrodes210adjacent to each other in the third direction DR3. The third direction DR3may intersect the first direction DR1and the second direction DR2. The third direction DR3may be orthogonal to the fourth direction DR4. The first to third directions DR1, DR2and DR3may be different directions disposed on a single plane.

In other words, the plurality of lower electrodes210may be repeatedly arranged/aligned so as to be closest to each other in the first direction DR1and the third direction DR3.

Alternatively, the plurality of lower electrodes210may be repeatedly arranged/aligned so as to be located at a hexagonal structure and a center of the hexagonal structure.

The lower electrode210may include, for example, but not limited to, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium or tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.).

The first electrode support50may be disposed on the substrate100. The first electrode support50may have a plate-like shape extending in a direction aligned/parallel with an upper surface of the substrate100. For example, the first electrode support50may be an electrode support disposed at the uppermost part in the electrode supports included in the first capacitor block CAP_ST1.

The first electrode support50may come into contact with the side walls of the lower electrode210. The first electrode support50may support a plurality of lower electrodes210.

The first electrode support50may inhibit/prevent the lower electrode210extending long in the fourth direction DR4from tilting and falling. The lower electrode210extends in a thickness direction of the first electrode support50.

For example, an upper surface50_US of the first electrode support50may be coplanar with an upper surface210_US of the lower electrode210. That is, the lower electrode210may not protrude upward from/beyond the upper surface50_US of the first electrode support50.

The first electrode support50may include an insulating material. The first electrode support50may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxyarbonitride (SiOCN).

The first electrode support50may include outer walls that define a boundary of the first electrode support50. The outer walls of the first electrode support50may define the boundary of the upper surface50_US of the first electrode support50.

The outer walls of the first electrode support50may include a first side wall50_SA extending in the first direction DR1, and a second side wall50_SB extending in the second direction DR2. The first side wall50_SA of the first electrode support50may be connected to the second side wall50_SB of the first electrode support50.

Although the first side wall50_SA of the first electrode support is shown to be directly connected to the second side wall50_SB of the first electrode support, the present invention is not limited thereto. Unlike the shown example, the outer walls of the first electrode support50may further include connecting (i.e., intervening) side walls that connect the first side wall50_SA of the first electrode support and the second side wall50_SB of the first electrode support.

For example, in a plan view, the connecting side walls of the first electrode support50may include various shapes such as a straight line, a curved line, a stepped shape, and a wavy shape.

The first electrode support50may include a center region50_CEN and an edge region50_EDGE. The edge region50_EDGE of the first electrode support50may be defined along the periphery of the center region50_CEN of the first electrode support50.

The center region50_CEN of the first electrode support50is included in the center region of the first capacitor block CAP_ST1described above. The edge region50_EDGE of the first electrode support50is included in the edge region of the first capacitor block CAP_ST1.

The edge region50_EDGE of the first electrode support50includes the first side wall50_SA of the first electrode support50and the second side wall50_SB of the first electrode support50.

The first electrode support50may include a plurality of first penetration patterns50_H1and50_H2that penetrate the first electrode support50. The plurality of first penetration patterns50_H1and50_H2may include a plurality of first center penetration patterns50_H1and a plurality of first edge penetration patterns50_H2.

The center region50_CEN of the first electrode support50includes a plurality of first center penetration patterns50_H1. The edge region50_EDGE of the first electrode support50includes a plurality of first edge penetration patterns50_H2.

For example, the center region50_CEN of the first electrode support50includes two or more first center penetration patterns50_H1. The edge region50_EDGE of the first electrode support50includes two or more first edge penetration patterns50_H2. The first electrode support50may include four or more first penetration patterns50_H1and50_H2.

For example, each of a first center penetration pattern50_H1and a first edge penetration pattern50_H2may be formed over four lower electrodes210. Each of the first center penetration pattern50_H1and the first edge penetration pattern50_H2may intersect the four lower electrodes210.

In the center region50_CEN of the first electrode support50, a plurality of first center penetration patterns50_H1may be repeatedly disposed along the first direction DR1and the second direction DR2. The center region50_CEN of the first electrode support50may include first center penetration patterns50_H1arranged/aligned in the first direction DR1. The center region50_CEN of the first electrode support50may include first center penetration patterns50_H1arranged/aligned in the second direction DR2.

In the center region50_CEN of the first electrode support, the first center penetration patterns50_H1adjacent to each other in the first direction DR1may be spaced apart from each other by a first interval P11. The first center penetration patterns50_H1adjacent to each other in the second direction DR2may be spaced apart from each other by a second interval P12. For example, the first interval P11may be the shortest distance between the first center penetration patterns50_H1spaced apart from each other in the first direction DR1.

In the edge region50_EDGE of the first electrode support50, a plurality of first edge penetration patterns50_H2may be repeatedly disposed along the first direction DR1and the second direction DR2. The edge region50_EDGE of the first electrode support50may include first edge penetration patterns50_H2arranged/aligned in the first direction DR1. The edge region50_EDGE of the first electrode support50may include the first edge penetration patterns50_H2arranged/aligned in the second direction DR2.

In the edge region50_EDGE of the first electrode support50, the first edge penetration patterns50_H2adjacent to each other in the first direction DR1may be spaced apart from each other by a third interval P21. The first edge penetration patterns50_H2adjacent to each other in the second direction DR2may be spaced apart from each other by a fourth interval P22.

In the semiconductor device according to some embodiments, a spaced interval of the first center penetration patterns50_H1adjacent to each other in the center region50_CEN of the first electrode support50differs from a spaced interval of the first edge penetration patterns50_H2adjacent to each other at the edge region50_EDGE of the first electrode support50. For example, the spaced interval of the first center penetration patterns50_H1adjacent to each other in the center region50_CEN of the first electrode support50may be greater than the spaced interval of the first edge penetration patterns50_H2adjacent to each other at the edge region50_EDGE of the first electrode support50.

As an example, the first interval P11by which the adjacent first center penetration patterns50_H1are spaced apart in the first direction DR1may be greater than the third interval P21by which the adjacent first edge penetration patterns50_H2are spaced apart in the first direction DR1. The second interval P12by which the adjacent first center penetration patterns50_H1are spaced apart in the second direction DR2may be greater than the fourth interval P22by which the adjacent first edge penetration patterns50_H2are spaced apart in the second direction DR2.

As another example, the first interval P11by which the adjacent first center penetration patterns50_H1are spaced apart in the first direction DR1may be greater than the third interval P21by which the adjacent first edge penetration patterns50_H2are spaced apart in the first direction DR1. The second interval P12by which the adjacent first center penetration patterns50_H1are spaced apart in the second direction DR2may be the same the fourth interval P22by which the adjacent first edge penetration patterns50_H2are spaced apart in the second direction DR2.

As still another example, the first interval P11by which the adjacent first center penetration patterns50_H1are spaced apart in the first direction DR1may be the same as the third interval P21by which the adjacent first edge penetration patterns50_H2are spaced apart in the first direction DR1. The second interval P12by which the adjacent first center penetration pattern50_H1are spaced apart in the second direction DR2may be greater than the fourth interval P22by which the adjacent first edge penetration pattern50_H2are spaced apart in the second direction DR2.

Although not shown, moving toward the center of the first electrode support50, the third interval P21between the first edge penetration patterns50_H2adjacent to each other in the first direction DR1may increase. Moving toward the center of the first electrode support50, the third interval P21between the first edge penetration patterns50_H2adjacent to each other in the first direction DR1may converge with (e.g., increase to/be equal to) the first interval P11between the first center penetration patterns50_H1adjacent to each other in the first direction DR1.

Also, moving toward the center of the first electrode support50, the fourth interval P22between the first edge penetration patterns50_H2adjacent to each other in the second direction DR2may increase. Moving toward the center of the first electrode support50, the fourth interval P22between the first edge penetration patterns50_H2adjacent to each other in the second direction DR2may converge with (e.g., increase to/be equal to) the second interval P12between the first center penetration patterns50_H1adjacent to each other in the second direction DR2.

When the first interval P11and the second interval P12are measured in the vicinity of the center of the first electrode support50, and the third interval P21and the fourth interval P22are measured in the vicinity adjacent to the first side wall50_SA of the first electrode support and/or the second side wall50_SB of the first electrode support, it is possible to clearly confirm that the spaced intervals P11and P12of the first center penetration patterns50_H1are greater than the spaced intervals P21and P22of the first edge penetration pattern50_H2.

The plurality of lower electrodes210may include a plurality of first lower electrodes210_1and a plurality of second lower electrodes210_2. The plurality of first lower electrodes210_1may come into contact with the center region50_CEN of the first electrode support50. The plurality of second lower electrodes210_2may come into contact with the edge region50_EDGE of the first electrode support50.

For example, each first center penetration pattern50_H1may be formed over four first lower electrodes210_1. The first edge penetration pattern50_H2may be formed over four second lower electrodes210_2. Since the center region50_CEN of the first electrode support50may include two or more first center penetration patterns50_H1, the lower electrode210may include at least eight or more first lower electrodes210_1. Since the edge region50_EDGE of the first electrode support50may include two or more first edge penetration patterns50_H2, the lower electrode210may include at least eight or more second lower electrodes210_2. The first electrode support50may come into contact with at least sixteen or more lower electrodes210.

A part of the lower electrode210may have a chamfered shape, in the portion in which the first center penetration pattern50_H1and the first edge penetration pattern50_H2are formed. In other words, a part of the lower electrode210may be recessed, in the portion in which the first center penetration pattern50_H1and the first edge penetration pattern50_H2are formed. In such a case, the upper surface210_US of the lower electrode210may not include the chamfered portion.

Unlike the shown example, the lower electrode210may not have a chamfered shape in the portion in which the first center penetration pattern50_H1and the first edge penetration pattern50_H2are formed.

InFIGS.3,6and7, the first lower electrode210_1may include an upper portion210UP_1and a lower portion210BP_1. The second lower electrode210_2may include an upper portion210UP_2and a lower portion210BP_2.

Each of the upper portion210UP_1of the first lower electrode210_1and the upper portion210UP_2of the second lower electrode210_2may be portions that come into contact with the first electrode support50. Each of the upper portion210UP_1of the first lower electrode210_1and the upper portion210UP_2of the second lower electrode210_2may include the upper surface210_US of the lower electrode210.

Each of the lower portion210BP_1of the first lower electrode210_1and the lower portion210BP_2of the second lower electrode210_2may be portions that come into contact with an etching stop film165, which will be described later. Each of the lower portion210BP_1of the first lower electrode210_1and the lower portion210BP_2of the second lower electrode210_2may include a lower surface of the lower electrode210that comes into contact with (and is electrically connected to) a respective landing pad160.

In the first lower electrode210_1, a horizontal center210UP_CL1of the upper portion210UP_1of the first lower electrode210_1may be aligned with a horizontal center210BP_CL1of the lower portion210BP_1of the first lower electrode210_1. That is, the center210UP_CL1of the upper portion210UP_1of the first lower electrode210_1and the center210BP_CL1of the lower portion210BP_1of the first lower electrode210_1may be aligned in the fourth direction DR4. The center210UP_CL1of the upper portion210UP_1of the first lower electrode210_1and the center210BP_CL1of the lower portion210BP_1of the first lower electrode210_1may lie on a single straight line (i.e., may be collinear).

In the second lower electrode210_2, a center210UP_CL2of the upper portion210UP_2of the second lower electrode210_2may be misaligned with a center210BP_CL2of the lower portion210BP_2of the second lower electrode210_2. That is, the center210UP_CL2of the upper portion210UP_2of the second lower electrode210_2may be spaced apart from the center210BP_CL2of the lower portion210BP_2of the second lower electrode210_2in a horizontal direction orthogonal to the fourth direction DR4. The center210UP_CL2of the upper portion210UP_2of the second lower electrode210_2and the center210BP_CL2of the lower portion210BP_2of the second lower electrode210_2do not lie on the single straight line (i.e., are not collinear).

The second lower electrode210_2may bend toward the center region50_CEN of the first electrode support50. In the single second lower electrode210_2, at least a part of the second lower electrode210_2(e.g., an upper portion of the second lower electrode210_2that is in contact with the edge region50_EDGE) may bend toward the center of the first electrode support50. For example, the degree to which the second lower electrode210_2bends may decrease, as it moves toward the center of the first electrode support50. That is, when a portion of the second lower electrode210_2adjacent to the first side wall50_SA of the first electrode support50and/or the second side wall50_SB of the first electrode support50bends by a first size, a portion of the second lower electrode210_2adjacent to the center of the first electrode support50may bend by a second size smaller than the first size.

The second lower electrode210_2is affected by the surrounding environment of the first capacitor block CAP_ST1(e.g., a substance, an interval between patterns, etc.), and may bend toward the vicinity of the center of the first electrode support50. However, the influence of the surrounding environment of the first capacitor block CAP_ST1decreases, going away from the first side wall50_SA of the first electrode support50and/or the second side wall50_SB of the first electrode support50.

A portion of the first lower electrode210_1that comes into contact with the center region50_CEN of the first electrode support50may not be affected (or may be affected to only a small extent) by the surrounding environment of the first capacitor block CAP_ST1. As a result, the center210UP_CL1of the upper portion210UP_1of the first lower electrode210_1may be aligned with the center210BP_CL1of the lower portion210BP_1of the first lower electrode210_1.

Since a portion of the second lower electrode210_2that comes into contact with the edge region50_EDGE of the first electrode support50bends toward the vicinity of the center of the first electrode support50, it may be beneficial to adjust the third interval P21and the fourth interval P22differently from the first interval P11and the second interval P12.

One first edge penetration pattern50_H2and four lower electrodes210around the first edge penetration pattern50_H2will be described as an example. If the third interval P21and the fourth interval P22are the same as the first interval P11and the second interval P12, the first edge penetration pattern50_H2may be formed to be biased toward at least one of the four lower electrodes210. In such a case, an electric field may be concentrated on at least one of the four lower electrodes210, while the first capacitor block CAP_ST1is operating. In the vicinity of the lower electrode210on which the electric field is concentrated, a defect may occur in the first capacitor block CAP_ST1. Such a defective capacitor block may reduce the performance and reliability of the semiconductor device.

The second electrode support60may be disposed between the substrate100and the first electrode support50. The second electrode support60may have a plate-like shape extending in a direction parallel to the upper surface of the substrate100.

The second electrode support60may come into contact with the side walls of the lower electrode210. The second electrode support60may support a plurality of lower electrodes210.

The second electrode support60may include a plurality of second penetration patterns60_H1and60_H2that penetrate the second electrode support60. The second penetration patterns60_H1and60_H2may include a plurality of second center penetration patterns60_H1and a plurality of second edge penetration patterns60_H2.

The second penetration patterns60_H1and60_H2may be formed at positions corresponding to the first penetration patterns50_H1and50_H2. The second penetration patterns60_H1and60_H2may be overlapped by (i.e., may underlie) and/or connected to the first penetration patterns50_H1and50_H2in the fourth direction DR4.

The second electrode support60may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxyarbonitride (SiOCN).

Unlike the shown example, in an example, the first capacitor block CAP_ST1may not include the second electrode support60. As another example, the first capacitor block CAP_ST1may further include an additional electrode support between the substrate100and the first electrode support50.

The capacitor dielectric film211may be formed on the plurality of lower electrodes210, the first electrode support50, and the second electrode support60. The capacitor dielectric film211may extend along the profile of the lower electrode210, the upper surface50_US of the first electrode support50and the lower surface of the first electrode support50, and the upper surface of the second electrode support60and the lower surface of the second electrode support60. The capacitor dielectric film211may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof. Although the capacitor dielectric film211is shown as a single film, this is only for convenience of explanation, and the present invention is not limited thereto.

In the semiconductor device according to some embodiments, the capacitor dielectric film211may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked.

In the semiconductor device according to some embodiments, the capacitor dielectric film211may include a dielectric film including hafnium (Hf). In the semiconductor device according to some embodiments, the capacitor dielectric film211may have a stacked film structure of a ferroelectric material film and a paraelectric material film.

The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may have a thickness to such an extent that it has ferroelectric properties. A thickness range of the ferroelectric material film having the ferroelectric properties may vary depending on the ferroelectric material.

For example, the ferroelectric material film may include a monometal oxide. The ferroelectric material film may include a monometal oxide film. Here, the monometal oxide may be a binary compound made up of one metal and oxygen. The ferroelectric material film including the monometal oxide may have an orthorhombic crystal structure.

As an example, the metal included in the monometal oxide film may be hafnium (Hf). The monometal oxide film may be a hafnium oxide (HfO) film. Here, the hafnium oxide film may have a chemical formula suitable for stoichiometry, or may have a chemical formula that is not suitable for stoichiometry.

As another example, the metal included in the monometal oxide film may be a rare earth metal belonging to lanthanoids. The monometal oxide film may be a rare earth metal oxide film belonging to the lanthanoids. Here, the rare earth metal oxide film belonging to the lanthanoids may have a chemical formula suitable for stoichiometry or may have a chemical formula that is not suitable for stoichiometry. When the ferroelectric material film includes the monometal oxide film, the ferroelectric material film may have a thickness of, for example, 1 nanometer (nm) or more and 10 nm or less.

For example, the ferroelectric material film may include a bimetal oxide. The ferroelectric material film may include a bimetal oxide film. Here, the bimetal oxide may be a ternary compound made up of two metals and oxygen. The ferroelectric material film including the bimetal oxide may have an orthorhombic crystal structure.

The metal included in the bimetal oxide film may be, for example, hafnium (Hf) and zirconium (Zr). The bimetal oxide film may be a hafnium zirconium oxide film (HfxZr(1−x)O). In the bimetal oxide film, x may be 0.2 or more and 0.8 or less. Here, the hafnium zirconium oxide film (HfxZr(1−x)O) may have a chemical formula suitable for stoichiometry, or may have a chemical formula not suitable for stoichiometry.

When the ferroelectric material film includes a bimetal oxide film, the ferroelectric material film may have a thickness of, for example, 1 nm or more and 20 nm or less.

For example, the paraelectric material film may be, but is not limited to, a dielectric film including zirconium (Zr) or a stacked film including zirconium (Zr). Even if the chemical formula is the same, the ferroelectric properties may be exhibited or the paraelectric properties may be exhibited, depending on the crystal structure of the dielectric substance.

The paraelectric material has a positive dielectric constant, and the ferroelectric material may have a negative dielectric constant in a fixed interval. That is, the paraelectric material may have a positive capacitance, and the ferroelectric material may have a negative capacitance.

In general, when two or more capacitors having positive capacitance are connected in series, the sum of the capacitances decreases. However, when a negative capacitor having a negative capacitance and a positive capacitor having a positive capacitance are connected in series, the sum of capacitances increases.

The upper electrode212may be formed on the capacitor dielectric film211. The upper electrode212may include, for example, but is not limited to, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, or tantalum, etc.), or a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.). The upper electrode212is shown as a single film, this is only for convenience of explanation, and the present invention is not limited thereto.

Hereinafter, a lower structure connected to the first capacitor block CAP_ST1will be described.

The substrate100may include a cell region, and a core/peri region located around the cell region.

A cell element separation film105may be formed inside the substrate100of the cell region. The cell element separation film105may have an STI (shallow trench isolation) structure having excellent element separation characteristics. The cell element separation film105may define a cell active region inside the cell region.

The cell element separation film105may include, for example, but is not limited to, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. InFIGS.3,4, and6, although the cell element separation film105is shown to be formed of a single insulating film, this is only for convenience of explanation, and the present invention is not limited thereto. Depending on the width of the cell element separation film105, the cell element separation film105may be formed of a single insulating film or may be formed of a plurality of insulating films.

Although the upper surface of the cell element separation film105and the upper surface of the substrate100are shown as being disposed on the same plane, this is only for convenience of explanation, and the present invention is not limited thereto.

A cell gate structure110may be formed inside the substrate100and the cell element separation film105. The cell gate structure110may be formed across the cell element separation film105and the cell active region defined by the cell element separation film105. The cell gate structure110may include a cell gate trench115, a cell gate insulating film111, a cell gate electrode112, a cell gate capping pattern113, and a cell gate capping conductive film114that are formed inside the substrate100and the cell element separation film105. For example, when the semiconductor device includes a DRAM, the cell gate electrode112may correspond to a word line. Unlike the shown example, the cell gate structure110may not include the cell gate capping conductive film114.

The cell gate insulating film111may extend along the side walls and the bottom surface of the cell gate trench115. The cell gate insulating film111may extend along a profile of at least a part of the cell gate trench115. The cell gate insulating film111may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

The cell gate electrode112may be formed on the cell gate insulating film111. The cell gate electrode112may extend long in the first direction DR1. The cell gate electrode112may fill a part of the cell gate trench115. The cell gate capping conductive film114may extend along the upper surface of the cell gate electrode112.

The cell gate electrode112may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The cell gate electrode112may include, for example, but is not limited to, at least one of TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC—N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni—Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrOx, RuOx and combinations thereof. The cell gate capping conductive film114may include, but is not limited to, for example, polysilicon or polysilicon-germanium.

The cell gate capping pattern113may be disposed on the cell gate electrode112and the cell gate capping conductive film114. The cell gate capping pattern113may fill the cell gate trench115that remains after the cell gate electrode112and the cell gate capping conductive film114are formed. Although the cell gate insulating film111is shown to extend along the side walls of the cell gate capping pattern113, the present invention is not limited thereto. The cell gate capping pattern113may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and a combination thereof.

Although not shown, an impurity doping region may be formed on at least one side of the cell gate structure110. The impurity doping region may be a source/drain region of the transistor.

A bit line structure140ST may include a cell conductive line140and a cell line capping film144. The cell conductive line140may be formed on the substrate100and the cell element separation film105on which the cell gate structure110is formed. The cell conductive line140may intersect the cell element separation film105and the cell active region defined by the cell element separation film105. The cell conductive line140may be formed to intersect the cell gate structure110. The cell conductive line140may extend long (i.e., longitudinally) in the second direction DR2. For example, when the semiconductor device includes a DRAM, the cell conductive line140may correspond to a bit line.

The cell conductive line140may be multiple films. The cell conductive line140may include, for example, a first cell conductive film141, a second cell conductive film142, and a third cell conductive film143. The first to third cell conductive films141,142, and143may be sequentially stacked on the substrate100and the cell element separation film105. Although the cell conductive line140is shown as a triple film, the present invention is not limited thereto.

The first to third cell conductive films141,142, and143may each include at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride metal, and a metal alloy. For example, although the first cell conductive film141may include a doped semiconductor material, the second cell conductive film142may include at least one of a conductive silicide compound and a conductive metal nitride, and the third cell conductive film143may include at least one of metal and metal alloy, the present invention is not limited thereto.

A bit line contact146may be formed between the cell conductive line140and the substrate100. That is, the cell conductive line140may be formed on the bit line contact146. The bit line contact146may be formed between the cell active region and the cell conductive line140.

The bit line contact146may electrically connect the cell conductive line140and the substrate100. Here, the bit line contact146may correspond to the direct contact of the DRAM. The bit line contact146may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal.

InFIGS.3and6, in a region in which it overlaps the upper surface of the bit line contact146, the cell conductive line140may include a second cell conductive film142and a third cell conductive film143. In a region in which it does not overlap the upper surface of the bit line contact146, the cell conductive line140may include the first to third cell conductive films141,142and143.

The cell line capping film144may be disposed on the cell conductive line140. The cell line capping film144may extend in the second direction D2along the upper surface of the cell conductive line140. In some embodiments, the cell line capping film144may include, for example, at least one of a silicon nitride film, a silicon oxynitride, a silicon carbonitride, and a silicon oxycarbonitride. Although the cell line capping film144is shown as a single film, the present invention is not limited thereto. Unlike the shown example, as an example, the cell line capping film144may have a double film structure. As another example, the cell line capping film144may have a triple film structure. As still another example, the cell line capping film144may have a structure of a quadruple film or more.

The cell insulating film130may be formed on the substrate100and the cell element separation film105. More specifically, the cell insulating film130may be formed on a portion of the substrate100and the cell element separation film105on which the bit line contact146and the storage contact120are not formed. The cell insulating film130may be formed between the substrate100and the cell conductive line140, and between the cell element separation film105and the cell conductive line140.

Although the cell insulating film130may be a single film, as shown, the cell insulating film130may be a multiple film including the first cell insulating film131and the second cell insulating film132. For example, although the first cell insulating film131may include a silicon oxide film, and the second cell insulating film132may include a silicon nitride film, the present invention is not limited thereto. Unlike the shown example, the cell insulating film130may be, but is not limited to, a triple film including a silicon oxide film, a silicon nitride film and a silicon oxide film.

The cell line spacer150may be disposed on the side walls of the cell conductive line140and the cell line capping film144. In a portion of the cell conductive line140in which the bit line contact146is formed, the cell line spacer150may be formed on the substrate100and the cell element separation film105. The cell line spacer150may be disposed on the side walls of the cell conductive line140, the cell line capping film144, and the bit line contact146.

However, in a remaining portion of the cell conductive line140in which the bit line contact146is not formed, the cell line spacer150may be disposed on the cell insulating film130. The cell line spacer150may be disposed on the side walls of the cell conductive line140and the cell line capping film144.

Although the cell line spacer150may be a single film, as shown, the cell line spacer150may be multiple films including the first to fourth cell line spacers151,152,153, and154. For example, the first to fourth cell line spacers151,152,153, and154may include, but are not limited to, one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), air, and combinations thereof. For example, the second cell line spacer152is not disposed on the cell insulating film130, but may be disposed on the side walls of the bit line contact146.

A fence pattern170may be disposed on the substrate100and the cell element separation film105. The fence pattern170may be formed to overlap the cell gate structure110formed inside the substrate100and the cell element separation film105. The fence pattern170may be disposed between the bit line structures140ST extending in the second direction D2. The fence pattern170may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

The storage contact120may be disposed between the cell conductive lines140adjacent to each other in the first direction D1. The storage contacts120may be disposed between the fence patterns170adjacent to each other in the second direction D2. The storage contact120may overlap the substrate100and the cell element separation film105between the adjacent cell conductive lines140. The storage contact120may be connected to the cell active region. Here, the storage contact120may correspond to the buried contact of the DRAM.

The storage contact120may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal.

The landing pad160may be formed on the storage contact120. The landing pad160may be electrically connected to the storage contact120. The landing pad160may be connected to the cell active region.

The landing pad160may overlap a part of the upper surface of the bit line structure140ST. The landing pad160may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

A pad separation insulating film180may be formed on the landing pad160and the bit line structure140ST. For example, the pad separation insulating film180may be disposed on the cell line capping film144. The pad separation insulating film180may define the landing pad160that forms a plurality of isolation regions. The pad separation insulating film180may not cover the upper surface of the landing pad160. For example, a height of the upper surface160US of the landing pad160may be the same as a height of the upper surface of the pad separation insulating film180, relative to the upper surface of the substrate100.

The pad separation insulating film180includes an insulating material, and may electrically separate a plurality of landing pads160from each other. For example, the pad separation insulating film180may include, for example, at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbonitirde film, and a silicon carbonitride film.

The etching stop film165may be disposed on the upper surface160US of the landing pad and the upper surface of the pad separation insulating film180. The etching stop film165may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), and silicon boronitride (SiBN).

InFIGS.3,4and6, the landing pad160may include, for example, a first landing pad and a second landing pad that are spaced apart from each other. The first landing pad and the second landing pad are not electrically connected to each other, but may be electrically connected to a first lower electrode210_1and a second lower electrode210_2, respectively, without being electrically connected to the second lower electrode210_2and the first lower electrode210_1, respectively.

The lower electrode210may include a first sub-lower electrode and a second sub-lower electrode that are spaced apart from each other. The first sub-lower electrode and the second sub-lower electrode may each extend long (i.e., longitudinally) in the fourth direction DR4. The first sub-lower electrode and the second sub-lower electrode are not electrically connected to each other. The first sub-lower electrode and the second sub-lower electrode penetrate the etching stop film165and are connected to the landing pad160.

In the semiconductor device according to some embodiments, the first landing pad is connected to the first sub-lower electrode, but is not connected to the second sub-lower electrode. The second landing pad is connected to the second sub-lower electrode, but is not connected to the first sub-lower electrode.

For example, the first capacitor block CAP_ST1may be a capacitor disposed in the memory cell region of the memory element. The first capacitor block CAP_ST1includes a plurality of capacitors, each of which operates separately. The capacitor including the first sub-lower electrode may operate separately from the capacitor including the second sub-lower electrode.

FIGS.8and9are diagrams for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from those described usingFIGS.1to7will be mainly described.

For reference,FIG.8may be an example cross-sectional view taken along A-A ofFIG.2, andFIG.9may be an example cross-sectional view taken along C-C ofFIG.5.

Referring toFIGS.8and9, the semiconductor device according to some embodiments may further include a plate lower electrode190disposed between the substrate100and the plurality of lower electrodes210.

A peri interlayer insulating film195may be disposed on the substrate100. The peri interlayer insulating film195may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boronitride (SiBN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxide (SiO), silicon oxyarbonitride (SiOCN) and combinations thereof. For example, silicon oxycarbide (SiCO) includes silicon (Si), carbon (C) and oxygen (O), but does not require a particular ratio between silicon (Si), carbon (C) and oxygen (O).

The plate lower electrode190may be disposed on the peri interlayer insulating film195. The plate lower electrode190may have a plate-like shape extending in a direction parallel to the upper surface of the substrate100.

A plurality of lower electrodes210may be disposed on the plate lower electrode190. Each lower electrode210may be connected to the plate lower electrode190. For example, each lower electrode210may be electrically connected to the plate lower electrode190.

Each first lower electrode210_1that comes into contact with the center region50_CEN of the first electrode support50may be connected to the plate lower electrode190. Moreover, each second lower electrode210_2that comes into contact with the edge region50_EDGE of the first electrode support50may be connected to the plate lower electrode190. In some embodiments, a part of the second lower electrode210_2that comes into contact with the edge region50_EDGE of the first electrode support50may be connected to the plate lower electrode190. The rest of the second lower electrode210_2is not connected to the plate lower electrode190.

The plate lower electrode190may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal.

When the first capacitor block CAP_ST1is included in the memory device, the first capacitor block CAP_ST1may be, for example, a capacitor disposed in the core/peri region. The first capacitor block CAP_ST1may be a single capacitor. Alternatively, the plurality of lower electrodes210connected to the plate lower electrode190may operate like a single electrode.

FIG.10is a diagram for explaining a semiconductor device according to some embodiments.FIG.11is a diagram for explaining the semiconductor device according to some embodiments. For convenience of explanation, points different from those described usingFIGS.1to7will be mainly described.

Referring toFIG.10, in the semiconductor device according to some embodiments, a part of the lower electrode210may protrude upward from/beyond the upper surface50_US of the first electrode support50.

The upper surface50_US of the first electrode support50is not located on the same plane as the upper surface210_US of the lower electrode. Relative to the upper surface of the substrate100, the upper surface50_US of the first electrode support50is lower than the upper surface210_US of the lower electrode210inFIG.10.

Referring toFIG.11, in the semiconductor device according to some embodiments, the lower electrode210may have a cylinder form.

The lower electrode210may include a bottom portion extending along the upper surface of the landing pad160, and side wall parts extending from the bottom portion in the fourth direction DR4.

FIG.12is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from those described usingFIGS.1to7will be mainly described.

Referring toFIG.12, the semiconductor device according to some embodiments may further include a node pad125.

The bit line contact146includes an upper surface connected to the cell conductive line140, and a lower surface connected to the cell active region of the substrate100. A width of the upper surface of the bit line contact146in the first direction DR1may be smaller than the width of the lower surface of the bit line contact146in the first direction DR1. The width of the bit line contact146may gradually increase as it goes away from the cell conductive line140. That is, the bit line contact146may have a gradually wider width from the upper portion to the lower portion.

The node pad125may be disposed on the substrate100. The node pad125may be disposed on the cell active region. The node pad125may be disposed between the storage contact120and the substrate100.

The upper surface of the node pad125may be lower than the upper surface of the bit line contact146relative to the upper surface of the cell element separation film105. The upper surface of the node pad125may be lower than the lower surface of the cell conductive line140relative to the upper surface of the cell element separation film105.

A contact separation pattern141rmay be interposed between the bit line contact146and the node pad125adjacent thereto. The contact separation pattern141rmay include an insulating material.

The node separation pattern145may be interposed between adjacent node pads125. The node separation pattern145is disposed on the substrate100. The node separation pattern145may separate the adjacent node pads125in the first direction DR1. The node separation pattern145may cover the upper surface of the node pads125adjacent to each other in the first direction DR1. In the cross-sectional view, the node separation pattern145may have a “T” shape.

The upper surface of the node separation pattern145may be coplanar with the upper surface of the bit line contact146. The upper surface of the node separation pattern145may be located at the same height as the upper surface of the bit line contact146relative to the upper surface of the cell element separation film105. The upper surface of the node separation pattern145may be located at the same height as the lower surface of the cell conductive line140relative to the upper surface of the cell element separation film105.

The node separation pattern145may include, for example, an insulating material. The lower surface of the node separation pattern145may be located at the same height as the upper surface of the cell element separation film105, but is not limited thereto. The lower surface of the node separation pattern145may be lower than the upper surface of the cell element separation film105.

The stacked structure of the cell conductive line140in the region in which it overlaps the upper surface of the bit line contact146may be the same as the stacked structure of the cell conductive line140in the region in which it does not overlap the upper surface of the bit line contact146.

The storage contact120is connected to the node pad125. The storage contact120connects the node pad125and the landing pad160.

FIG.13is a diagram for explaining the semiconductor device according to some embodiments.FIG.14is a diagram for explaining the semiconductor device according to some embodiments.FIG.15is a diagram for explaining the semiconductor device according to some embodiments. For convenience of explanation, points different from those described usingFIGS.1to7will be mainly described.

For reference,FIGS.13to15are enlarged views of a portion P ofFIG.1, respectively.

Referring toFIG.13, in a semiconductor device according to some embodiments, the first center penetration pattern50_H1may be formed between three adjacent first lower electrodes210_1. The first center penetration pattern50_H1may expose the three adjacent first lower electrodes210_1.

Three first lower electrodes210_1that intersect one first center penetration pattern50_H1may be disposed at apex positions of a triangle. A fourth first lower electrode210_1is not disposed in the first center penetration pattern50_H1.

Although not shown, an enlarged plan view of the portion Q ofFIG.1may be similar to that ofFIG.13.

The adjacent first center penetration patterns50_H1may be spaced apart by a fifth interval P13. The first edge penetration patterns50_H2included in the edge region of the first electrode support (50_EDGE ofFIG.1) are spaced apart by an interval smaller than the fifth interval P13.

Referring toFIG.14, in the semiconductor device according to some embodiments, the first center penetration pattern50_H1may have the form of a bar extending long in the first direction DR1.

Although the first center penetration pattern50_H1is shown to be formed over three first lower electrodes210adjacent to each other in a first row in the first direction DR1and four first lower electrodes210adjacent to each other in a second row in the first direction DR1, this is only for convenience of explanation, and the present invention is not limited thereto.

Although not shown, an enlarged plan view of a portion Q ofFIG.1may also be similar to that ofFIG.14.

As described usingFIGS.1to7, the intervals P11and P12by which the first center penetration patterns50_H1adjacent to each other are spaced apart from each other in the center region50_CEN of the first electrode support50are greater than the intervals P21and P22by which the first edge penetration patterns50_H2adjacent to each other are spaced apart from each other in the edge region50_EDGE of the first electrode support50.

Referring toFIG.15, in the semiconductor device according to some embodiments, the first lower electrodes210_1repeatedly arranged/aligned in the second direction DR2may be linearly arranged along the second direction DR2.

The first lower electrodes210_1repeatedly arranged/aligned in the first direction DR1may be arranged along the first direction DR1. Further, the first lower electrodes210_1repeatedly arranged/aligned in the second direction DR2may be arranged along the second direction DR2.

Although not shown, an enlarged plan view of the portion Q ofFIG.1may also be similar to that ofFIG.15.

As described usingFIGS.1to7, the intervals P11and P12by which the first center penetration patterns50_H1adjacent to each other are spaced apart from each other in the center region50_CEN of the first electrode support50are greater than the intervals P21and P22by which the first edge penetration patterns50_H2adjacent to each other are spaced apart from each other in the edge region50_EDGE of the first electrode support50.

FIG.16is a schematic plan view for explaining the semiconductor device according to some embodiments.FIG.17is an enlarged plan view of a portion R ofFIG.16.FIG.18is an enlarged plan view of a portion S ofFIG.16.

Since the enlarged plan view of the P portion ofFIG.16is the same as that ofFIG.2, the description will be centered onFIGS.17and18in which the edge region50_EDGE of the first electrode support50is enlarged.

Referring toFIGS.2, and16to18, the semiconductor device according to some embodiments may include first to ninth capacitor blocks CAP_ST1, CAP_ST2, CAP_ST3, CAP_ST4, CAP_ST5, CAP_ST6, CAP_ST7, CAP_ST8, and CAP_ST9.

The second to ninth capacitor blocks CAP_ST2, CAP_ST3, CAP_ST4, CAP_ST5, CAP_ST6, CAP_ST7, CAP_ST8, and CAP_ST9may be disposed around the first capacitor block CAP_ST1. Although the eight capacitor blocks are shown as being disposed around the first capacitor block CAP_ST1, the present invention is not limited thereto.

The second to ninth capacitor blocks CAP_ST2, CAP_ST3, CAP_ST4, CAP_ST5, CAP_ST6, CAP_ST7, CAP_ST8, and CAP_ST9may have the same structure as that of the first capacitor block CAP_ST1. However, the lower structures connected to the second to ninth capacitor blocks CAP_ST2, CAP_ST3, CAP_ST4, CAP_ST5, CAP_ST6, CAP_ST7, CAP_ST8, and CAP_ST9may be different from each other. As an example, the second to ninth capacitor blocks CAP_ST2, CAP_ST3, CAP_ST4, CAP_ST5, CAP_ST6, CAP_ST7, CAP_ST8, and CAP_ST9may be connected to the landing pad160described inFIGS.2to4and12. As another example, the second to ninth capacitor blocks CAP_ST2, CAP_ST3, CAP_ST4, CAP_ST5, CAP_ST6, CAP_ST7, CAP_ST8, and CAP_ST9may be connected to the plate lower electrode190described inFIGS.8and9. As yet another example, some of the second to ninth capacitor blocks CAP_ST2, CAP_ST3, CAP_ST4, CAP_ST5, CAP_ST6, CAP_ST7, CAP_ST8, and CAP_ST9may be connected to the landing pad160described inFIGS.2,4and12, and the rest may be connected to the plate lower electrode190described inFIGS.8and9.

A second capacitor block CAP_ST2and a third capacitor block CAP_ST3will be described as an example.

The second capacitor block CAP_ST2and the third capacitor block CAP_ST3may be disposed separately from the first capacitor block CAP_ST1in the first direction DR1, respectively.

The second capacitor block CAP_ST2may be spaced apart from the first capacitor block CAP_ST1in the first direction D1by a first distance L1. The third capacitor block CAP_ST3may be spaced apart from the first capacitor block CAP_ST1in the first direction D1by a second distance L2.

In the semiconductor device according to some embodiments, the first distance L1by which the first capacitor block CAP_ST1and the second capacitor block CAP_ST2are spaced apart is different from the second distance L2by which the first capacitor block CAP_ST1and the third capacitor block CAP_ST3are spaced apart. For example, the second distance L2may be greater than the first distance L1.

A stress received by the lower electrode210that comes into contact with the edge region50_EDGE of the first electrode support may vary depending on the distance between the first capacitor block CAP_ST1and the surrounding capacitor blocks. That is, the degree of bending of the second lower electrode (210_2ofFIG.6) may vary depending on the distance between the first capacitor block CAP_ST1and the surrounding capacitor blocks.

The edge region50_EDGE of the first electrode support50may include, for example, a first sub-edge region50_EDGE1, a second sub-edge region50_EDGE2, a third sub-edge region50_EDGE3, and a fourth sub-edge region50_EDGE4.

The first sub-edge region50_EDGE1of the first electrode support50may be a portion of the edge region50_EDGE of the first electrode support50that overlaps the second capacitor block CAP_ST2in the first direction DR1. The second sub-edge region50_EDGE2of the first electrode support50may be a portion of the edge region50_EDGE of the first electrode support50that overlaps the third capacitor block CAP_ST3in the first direction DR1. The third sub-edge region50_EDGE3of the first electrode support50may be a portion of the edge region50_EDGE of the first electrode support that overlaps the fifth capacitor block CAP_ST5in the second direction DR2. The fourth sub-edge region50_EDGE4of the first electrode support50may be a portion of the edge region50_EDGE of the first electrode support that overlaps the fourth capacitor block CAP_ST4in the second direction DR2.

For example, a part of the edge region50_EDGE of the first electrode support50that overlaps the second capacitor block CAP_ST2in the first direction DR1may overlap the fifth capacitor block CAP_ST5in the second direction DR2. Hereinafter, it will be described that the first sub-edge region50_EDGE1of the first electrode support50does not include a portion that overlaps the fifth capacitor block CAP_ST5in the second direction DR2, in the edge region50_EDGE of the first electrode support50that overlaps the second capacitor block CAP_ST2in the first direction DR1.

The edge region50_EDGE of the first electrode support includes a plurality of first sub-edge penetration patterns50_H21and second sub-edge penetration patterns50_H22. The first sub-edge region50_EDGE1of the first electrode support50includes a plurality of first sub-edge penetration patterns50_H21. The second sub-edge region50_EDGE2of the first electrode support50includes a plurality of second sub-edge penetration patterns50_H22.

The plurality of lower electrodes210may include a plurality of first sub-lower electrodes210_2A and a plurality of second sub-lower electrodes210_2B. The plurality of first sub-lower electrodes210_2A may come into contact with the first sub-edge region50_EDGE1of the first electrode support50. The plurality of second sub-lower electrodes210_2B may come into contact with the second sub-edge region50_EDGE2of the first electrode support50.

In the first sub-edge region50_EDGE1of the first electrode support50, a plurality of first sub-edge penetration patterns50_H21may be repeatedly disposed along the first direction DR1and the second direction DR2. The first sub-edge region50_EDGE1of the first electrode support50may include first sub-edge penetration patterns50_H21arranged/aligned in the first direction DR1. The first sub-edge region50_EDGE1of the first electrode support50may include first sub-edge penetration patterns50_H21arranged/aligned in the second direction DR2.

In the first sub-edge region50_EDGE1of the first electrode support50, the first sub-edge penetration patterns50_H21adjacent to each other in the first direction DR1may be spaced apart by a sixth interval P211. The first sub-edge penetration patterns50_H21adjacent to each other in the second direction DR2may be spaced apart by a seventh interval P221.

In the second sub-edge region50_EDGE2of the first electrode support50, a plurality of second sub-edge penetration patterns50_H22may be repeatedly disposed along the first direction DR1and the second direction DR2. The second sub-edge region50_EDGE2of the first electrode support50may include second sub-edge penetration patterns50_H22arranged/aligned in the first direction DR1. The second sub-edge region50_EDGE2of the first electrode support50may include second sub-edge penetration patterns50_H22arranged/aligned in the second direction DR2.

In the second sub-edge region50_EDGE2of the first electrode support50, the second sub-edge penetration patterns50_H22adjacent to each other in the first direction DR1may be spaced apart by an eighth interval P212. The second sub-edge penetration patterns50_H22adjacent to each other in the second direction DR2may be spaced apart by a ninth interval P222.

In the semiconductor device according to some embodiments, the interval by which the first sub-edge penetration patterns50_H21adjacent to each other are spaced apart in the first sub-edge region50_EDGE1of the first electrode support50is different from the interval by which the second sub-edge penetration patterns50_H22adjacent to each other are spaced apart in the second sub-edge region50_EDGE2of the first electrode support50. For example, the interval by which the first sub-edge penetration patterns50_H21adjacent to each other are spaced apart in the first sub-edge region50_EDGE1of the first electrode support50is greater than the interval by which the second sub-edge penetration patterns50_H22adjacent to each other are spaced apart in the second sub-edge region50_EDGE2of the first electrode support50.

As an example, more specifically, the sixth interval P211by which the adjacent first sub-edge penetration patterns50_H21are spaced apart in the first direction DR1is greater than the eighth interval P212by which the adjacent second sub-edge penetration patterns50_H22are spaced apart in the first direction. The seventh interval P221by which the adjacent first sub-edge penetration patterns50_H21are spaced apart in the second direction DR2is greater than the ninth interval P222by which the adjacent second sub-edge penetration patterns50_H22are spaced apart in the second direction DR2.

As another example, more specifically, the sixth interval P211by which the adjacent first sub-edge penetration patterns50_H21are spaced apart in the first direction DR1is greater than the eighth interval P212by which the adjacent second sub-edge penetration patterns50_H22are spaced apart in the first direction DR1. The seventh interval P221by which the adjacent first sub-edge penetration patterns50_H21are spaced apart in the second direction DR2may be the same as the ninth interval P222by which the adjacent second sub-edge penetration patterns50_H22are spaced apart in the second direction DR2.

As still another example, more specifically, the sixth interval P211by which the adjacent first sub-edge penetration patterns50_H21are spaced apart in the first direction DR1may be the same as the eighth interval P212by which the adjacent second sub-edge penetration patterns50_H22are spaced apart in the first direction DR1. The seventh interval P221by which the adjacent first sub-edge penetration patterns50_H21are spaced apart in the second direction DR2is greater than the ninth interval P222by which the adjacent second sub-edge penetration patterns50_H22are spaced apart in the second direction DR2.

For example, the intervals P11and P12by which the first center penetration patterns50_H1adjacent to each other are spaced apart in the center region50_CEN of the first electrode support are greater than the intervals P211and P221by which the first sub-edge penetration patterns50_H21adjacent to each other are spaced apart in the first sub-edge region50_EDGE1of the first electrode support50. The intervals P11and P12by which the first center penetration patterns50_H1adjacent to each other are spaced apart in the center region50_CEN of the first electrode support are greater than the intervals P212and P222by which the second sub-edge penetration patterns50_H22adjacent to each other are spaced apart in the second sub-edge region50_EDGE2of the first electrode support50.

Although the second capacitor block CAP_ST2and the third capacitor block CAP_ST3are described as being adjacent to the first capacitor block CAP_ST1in the first direction DR1, the present invention is not limited thereto.

The description about the spaced interval of the first penetration patterns50_H21and50_H22may be applied as it is, even in a case where the second capacitor block CAP_ST2is adjacent to the first capacitor block CAP_ST1in the first direction DR1, and the third capacitor block CAP_ST3is adjacent to the first capacitor block CAP_ST1in the second direction DR2.

FIG.19is a layout diagram for explaining a semiconductor memory device according to some embodiments.FIG.20is a perspective view for explaining the semiconductor memory device according to some embodiments.FIG.21is a cross-sectional view taken along lines D-D and E-E ofFIG.19.

For reference,FIG.19may be an enlarged view of a region P and a region Q ofFIG.1.

Referring toFIGS.19to21, the semiconductor device according to some embodiments may include a substrate100, a plurality of first conductive lines420, a channel layer430, a gate electrode440, a gate insulating film450, and a first capacitor block CAP_ST1. The semiconductor device according to some embodiments may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which a channel length of the channel layer430extends from the substrate100along a vertical direction.

A lower insulating layer412may be disposed on the substrate100. A plurality of first conductive lines420may be spaced apart from each other in the first direction DR1and extend in the second direction DR2on the lower insulating layer412. A plurality of first insulating patterns422may be disposed on the lower insulating layer412to fill the space between the plurality of first conductive lines420. The plurality of first insulating patterns422may extend in the second direction DR2. The upper surfaces of the plurality of first insulating patterns422may be disposed at the same level as (i.e., may be coplanar with) the upper surfaces of the plurality of first conductive lines420. The plurality of first conductive lines420may function as bit lines.

The plurality of first conductive lines420may include a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the plurality of first conductive lines420may be made up of, but are not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx or a combination thereof. The plurality of first conductive lines420may include a single layer or multiple layers of the above-mentioned materials. In example embodiments, the plurality of first conductive lines420may include graphene, carbon nanotube or a combination thereof.

The channel layers430may be arranged in the form of a matrix in which they are disposed apart from each other in the first direction DR1and the second direction DR2on the plurality of first conductive lines420. The channel layer430may have a first width along the first direction DR1and a first height along the fourth direction DR4, and the first height may be greater than the first width. For example, the first height may be, but is not limited to, about 2 to 10 times the first width. Although not shown, a bottom portion of the channel layer430may function as a third source/drain region, an upper portion of the channel layer430may function as a fourth source/drain region, and a part of the channel layer430between the third and second source/drain regions may function as a channel region.

In the example embodiments, the channel layer430may include an oxide semiconductor, and the oxide semiconductor may include, for example, InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, InxGayO or combinations thereof. The channel layer430may include a single layer or multiple layers of the oxide semiconductor. In some embodiments, the channel layer430may have a bandgap energy that is greater than the bandgap energy of silicon. For example, the channel layer430may have bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer430may have optimum channel performance when having the bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer430may be, but is not limited to, polycrystalline or amorphous. In the example embodiments, the channel layer430may include graphene, carbon nanotube or a combination thereof.

The gate electrode440may extend in the first direction DR1on opposite side walls of the channel layer430. The gate electrode440may include a first sub-gate electrode440P1facing the first side wall of the channel layer430, and a second sub-gate electrode440P2facing the second side wall opposite to the first side wall of the channel layer430. Since one channel layer430is disposed between the first sub-gate electrode440P1and the second sub-gate electrode440P2, the semiconductor device may have a dual gate transistor structure. However, the present disclosure is not limited thereto, and the second sub-gate electrode440P2may be omitted, and only the first sub-gate electrode440P1facing the first side wall of the channel layer430may be formed to implement a single gate transistor structure. The material included in the gate electrode440may be the same as that described with respect to the cell gate electrode112.

The gate insulating film450surrounds the side walls of the channel layer430and may be interposed between the channel layer430and the gate electrode440. For example, as shown inFIG.19, the entire side walls of the channel layer430may be surrounded by the gate insulating film450, and a part of the side walls of the gate electrode440may come into contact with the gate insulating film450. In other embodiments, the gate insulating film450extends in an extension direction of the gate electrode440(that is, the first direction DR1), and among the side walls of the channel layer430, only the two side walls that face the gate electrode440may come into contact with the gate insulating film450. In the example embodiments, the gate insulating film450may be made up of a silicon oxide film, a silicon oxynitride film, a high dielectric constant material having a higher dielectric constant than that of silicon oxide film or a combination thereof.

A plurality of second insulating patterns432may extend along the second direction DR2on the plurality of first insulating patterns422. The channel layer430may be disposed between two adjacent second insulating patterns432among the plurality of second insulating patterns432. In addition, a first buried layer434and a second buried layer436may be disposed in the space between the two adjacent channel layers430, between the two adjacent second insulating patterns432. The first buried layer434may be disposed at the bottom portion of the space between the two adjacent channel layers430. The second buried layer436may be formed to fill the rest of the space between the two adjacent channel layers430on the first buried layer434. The upper surface of the second buried layer436is coplanar with the upper surface of the channel layer430, and the second buried layer436may cover the upper surface of the second gate electrode440. Unlike this, a plurality of second insulating patterns432may be formed by a material layer that is continuous with a plurality of first insulating patterns422, or the second buried layer436may also be formed of a material layer that is continuous with the first buried layer434.

Capacitor contacts460may be disposed on the channel layer430. The capacitor contacts460are disposed to vertically overlap the channel layer430, and may be arranged in the form of a matrix in which they are spaced apart in the first direction DR1and the second direction DR2. The capacitor contact460may be made up of, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx or a combination thereof. The upper insulating film462may surround the side walls of the capacitor contact460on the plurality of second insulating patterns432and the second buried layer436.

A cell etching stop film470may be disposed on the upper insulating layer462. The first capacitor block CAP_ST1may be disposed on the cell etching stop film470. The cell etching stop film470may correspond to the etching stop film165ofFIG.3.

The first capacitor block CAP_ST1includes a plurality of lower electrodes210, a capacitor dielectric film211, an upper electrode212, a first electrode support50, and a second electrode support60. The description about the first capacitor block CAP_ST1may be substantially the same as that described usingFIGS.1to7.

The lower electrode210penetrates the cell etching stop film470and may be electrically connected to the upper surface of the capacitor contact460. In some example embodiments, the lower electrodes210are disposed to vertically overlap the capacitor contact460, and may be arranged in the form of a matrix in which they are spaced apart from each other in the first direction DR1and the second direction DR2. Unlike the shown example, a landing pad may be further disposed between the capacitor contact460and the lower electrode210, and the lower electrode210may be disposed in a hexagonal shape.

FIG.22is a layout diagram for explaining the semiconductor device according to some embodiments.FIG.23is a perspective view for explaining the semiconductor device according to some embodiments.

Referring toFIGS.22and23, the semiconductor device according to some embodiments may include a substrate100, a plurality of first conductive lines420A, a channel structure430A, a contact gate electrode440A, a plurality of second conductive lines442A, and a first capacitor block CAP_ST1. The semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor VCT.

A plurality of active regions AC may be defined on the substrate100by the first element separation pattern412A and the second element separation pattern414A. The channel structure430A may be disposed inside each active region AC. The channel structure430A may include a first active pillar430A1and a second active pillar430A2each extending in the vertical direction, and a connecting portion430L connected to the bottom portion of the first active pillar430A1and the bottom portion of the second active pillar430A2. A first source/drain region SD1may be disposed inside the connecting portion430L. A second source/drain region SD2may be disposed above the first and second active pillars430A1and430A2. The first active pillar430A1and the second active pillar430A2may each form an independent unit memory cell.

The plurality of first conductive line420A may extend in a direction that intersects each of the plurality of active regions AC, and may extend, for example, in the second direction DR2. A single first conductive line420A among the plurality of first conductive lines420A may be disposed on the connecting portion430L between the first active pillar430A1and the second active pillar430A2. Further, the single first conductive line420A may be disposed on the first source/drain region SD1. The other first conductive line420A adjacent to the single first conductive line420A may be disposed between the two channel structures430A. The single first conductive line420A among the plurality of first conductive lines420A may function as a common bit line included in two unit memory cells formed by the first active pillar430A1and the second active pillar430A2disposed on opposite sides of the single first conductive line420A.

A single contact gate electrode440A may be disposed between two channel structures430A adjacent to each other in the second direction DR2. For example, the contact gate electrode440A may be disposed between the first active pillar430A1included in the single channel structure430A and the second active pillar430A2of the channel structure430A adjacent thereto. The single contact gate electrode440A may be shared by the first active pillar430A1and the second active pillar430A2disposed on opposite side walls thereof. A gate insulating film450A may be disposed between the contact gate electrode440A and the first active pillar430A1, and between the contact gate electrode440A and the second active pillar430A2. The plurality of second conductive lines442A may extend in the first direction DR1on the upper surface of the contact gate electrode440A. The plurality of second conductive lines442A may function as word lines of the semiconductor device.

A capacitor contact460A may be disposed on the channel structure430A. The capacitor contact460A may be disposed on the second source/drain region SD2, and the first capacitor block CAP_ST1may be disposed on the capacitor contact460A.

FIG.24is a diagram for explaining the semiconductor device according to some embodiments.

For reference,FIG.24may be a diagram relating to the formation of the cell active region of the cell region.

Referring toFIG.24, the semiconductor device according to some embodiments may include a cell region20, a cell separation region22, and a core/peri region24.

The cell region20may be a region in which the memory cell for storing information is formed. The core/peri region24may be a region in which a peripheral circuit for driving the memory cell is formed. The cell separation region22may be a region that separates the cell region20and the core/peri region24.

The cell region20may include a center cell region20_CEN, and an edge cell region20_EDGE defined along the periphery of the center cell region20_CEN. The edge cell region20_EDGE may form a boundary with the cell separation region22.

The cell region20may include a plurality of cell active regions ACT_CEN and ACT_EDGE. The cell active regions ACT_CEN and ACT_EDGE may be disposed in the form of a bar of a diagonal line (or an oblique line). For example, the cell active regions ACT_CEN and ACT_EDGE may extend in a fifth direction DR5. The fifth direction DR5may be a direction that is different from the third direction DR3ofFIG.3.

The cell active region may include a center cell active region ACT_CEN and an edge cell active region ACT_EDGE. The center cell active region ACT_CEN is formed in the center cell region20_CEN, and the edge cell active region ACT_EDGE may be formed in the edge cell region20_EDGE.

For example, the distance by which the adjacent center cell active regions ACT_CEN are spaced apart in the first direction DR1may be the same as the distance by which the adjacent edge cell active regions ACT_EDGE are spaced apart in the first direction DR1.

The center cell active region ACT_CEN may be formed using a first mask pattern ACT_MASK1. The edge cell active region ACT_EDGE may be formed using a second mask pattern ACT_MASK2. The first mask pattern ACT_MASK1and the second mask pattern ACT_MASK2may be included in a photomask used to form the cell active regions ACT_CEN and ACT_EDGE.

In the semiconductor device according to some embodiments, the distance by which the first mask patterns ACT_MASK1are spaced apart in the first direction DR1may be smaller than the distance by which the second mask patterns ACT_MASK2are spaced apart in the first direction DR1.

The distance by which the first mask patterns ACT_MASK1are spaced apart in the first direction DR1is assumed to be the same as the distance by which the second mask patterns ACT_MASK2are spaced apart in the first direction DR1. The center cell active region ACT_CEN may be regularly formed around the center cell active region ACT_CEN.

Since the center cell region20_CEN is located on one side of the edge cell region20_EDGE, the edge cell active region ACT_EDGE may be regularly formed on one side of the edge cell active region ACT_EDGE. However, since the core/peri region24is located on the other side of the edge cell region20_EDGE, the edge cell active region ACT_EDGE is not formed on another (e.g., an opposite) side of the edge cell active region ACT_EDGE. That is, since a difference in the surrounding environment between one side and the other side of the edge cell region20_EDGE occurs, the edge cell active region ACT_EDGE may bend to the center cell active region ACT_CEN. That is, the distance by which the adjacent edge cell active regions ACT_EDGE are spaced apart in the first direction DR1may be smaller than the distance by which the adjacent center cell active regions ACT_CEN are spaced apart in the first direction DR1.

If the interval between the cell active regions ACT_CEN and ACT_EDGE changes depending on the position of the cell region20, process defects such as contact defects or an increase in contact resistance may occur in the subsequent manufacturing process.

Considering that the edge cell active region ACT_EDGE bends toward the center of the cell region20, the photomask used for forming the cell active regions ACT_CEN and ACT_EDGE may be fabricated such that the spaced distance of the second mask patterns ACT_MASK2in the first direction DR1is greater than the spaced distance of the first mask patterns ACT_MASK1in the first direction DR1.

FIG.25is a diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, points different from those described usingFIG.24will be mainly described.

For reference,FIG.25is a schematic layout diagram of a semiconductor memory device.

Referring toFIG.25, the distance by which the adjacent center cell active regions ACT_CEN are spaced apart in the first direction DR1is greater than the distance by which the adjacent edge cell active regions ACT_EDGE are spaced apart in the first direction DR1.

In the photomask used for forming the cell active regions ACT_CEN and ACT_EDGE ofFIG.24, the spaced distance of the second mask patterns ACT_MASK2in the first direction DR1may be the same as the spaced distance of the first mask patterns ACT_MASK1in the first direction DR1.

The word line WL may extend in the first direction DR1across the cell active regions ACT_CEN and ACT_EDGE.

The bit lines BL_CEN and BL_EDGE are disposed on the word line WL and may be disposed in the second direction DR2. The bit lines BL_CEN and BL_EDGE may intersect the cell active regions ACT_CEN and ACT_EDGE.

The bit line may include a center bit line BL_CEN and an edge bit line BL_EDGE. The center bit line BL_CEN may be formed in the center cell region20_CEN. The edge bit line BL_EDGE may be formed in the edge cell region20_EDGE.

A boundary bit line BL_IF may extend in the second direction DR2alongside the bit lines BL_CEN and BL_EDGE. At least a part of the boundary bit line BL_IF may be disposed to overlap the cell separation region22in the first direction DR1. Unlike the shown example, the semiconductor device according to some embodiments may not include the boundary bit line BL_IF.

The distance between the center bit lines BL_CEN adjacent to each other in the first direction DR1may be a third distance L3. The distance between the edge bit lines BL_EDGE adjacent to each other in the first direction DR1may be a fourth distance L4.

Since the distance by which the adjacent center cell active regions ACT_CEN are spaced apart in the first direction DR1may be greater than the distance by which the adjacent edge cell active regions ACT_EDGE are spaced apart in the first direction DR1, the third distance L3may be greater than the fourth distance L4.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the example embodiments without substantially departing from the scope of the present invention. Therefore, the disclosed example embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation.