Patent ID: 12199032

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor memory device includes a first conductor layer, a plurality of second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first conductor layer is provided via a first insulator layer above a substrate. The second conductor layers are stacked above the first conductor layer and apart from each other in a first direction. The first pillar is passing through the second conductor layers along the first direction. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The second insulator layer is provided between the first semiconductor layer and the second conductor layers. An intersections with the second conductor layers function as memory cell transistors. The first contact is passing through the second conductor layers along the first direction. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The third insulator layer is provided between the third conductor layer and the second conductor layers. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.

Hereinafter, embodiments will be described with reference to the accompanying drawings. Each of the embodiments is an example of a device and a method to embody a technical idea of the invention. The drawings are schematic or conceptual, and the dimensions and ratios, etc. in the drawings are not always the same as the actual ones. Furthermore, the technical concept of the invention is not limited by the form, structure, arrangement or the like of the structural components.

In the description that follows, components having substantially the same functions and configurations will be denoted by the same reference symbols. The numbers after the letters constituting the reference symbols are used to discriminate between components that are denoted by the reference symbols sharing letters in common and that have similar configurations. If there is no need to discriminate between components that are denoted by the reference symbols sharing letters in common, such components are denoted by reference symbols that include the letters only.

Embodiment

Hereinafter, a semiconductor memory device1according to an embodiment will be described.

[1] Configuration of Semiconductor Memory Device1

[1-1] Overall Configuration of Semiconductor Memory Device1

FIG.1shows a configuration example of the semiconductor memory device1according to the embodiment. The semiconductor memory device1is a NAND-type flash memory which can store data in a non-volatile manner, and is controlled by an external memory controller2. Communications between the semiconductor memory device1and the memory controller2support the NAND interface standard, for example.

As shown inFIG.1, the semiconductor memory device1includes, for example, a memory cell array10, a command register11, an address register12, a sequencer13, a driver module14, a row decoder module15, and a sense amplifier module16.

The memory cell array10includes a plurality of blocks BLK0to BLKn (n is an integer greater than or equal to 1). A block BLK is a group of memory cells capable of storing data in a nonvolatile manner, and is, for example, a unit of erasing data. The memory cell array10is provided with a plurality of bit lines and word lines. Each memory cell is, for example, associated with one bit line and one word line. The memory cell array10will be described in detail later.

The command register11retains a command CMD received by the semiconductor memory device1from the memory controller2. The command CMD includes instructions to cause the sequencer13to execute, for example, a read operation, a write operation, an erase operation, etc.

The address register12retains address information ADD received by the semiconductor memory device1from the memory controller2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used to select a block BLK, a word line, and a bit line, respectively.

The sequencer13controls the operation of the entire semiconductor memory device1. For example, the sequencer13controls the driver module14, the row decoder module15, the sense amplifier module16, etc., based on the command CMD held in the command register11, and executes a read operation, a write operation, an erase operation, etc.

The driver module14generates voltages used for a read operation, a write operation, an erase operation, etc. The driver module14applies the generated voltage to a signal line corresponding to the selected word line based on, for example, the page address PAd held in the address register12. Furthermore, the driver module14may apply the voltage to the source line SL. Namely, the driver module14is also a circuit that drives the source line SL.

The row decoder module15selects one block BLK in the corresponding memory cell array10based on a block address BAd held in the address register12. The row decoder module15transfers, for example, the voltage applied to the signal line corresponding to the selected word line, to the selected word line in the selected block BLK.

In a write operation, the sense amplifier module16applies a desired voltage to each bit line in accordance with write data DAT received from the memory controller2. Namely, the sense amplifier module16is also a circuit that drives the bit line BL. In a read operation, the sense amplifier module16determines the data stored in a memory cell based on the voltage of the bit line, and transfers the determination result as read data DAT to the memory controller2.

The above mentioned semiconductor memory device1and memory controller2may be combined into a single semiconductor memory device. Such a semiconductor device may be a memory card, such as an SD™ card, and a solid state drive (SSD), for example.

[1-2] Circuit Configuration of Memory Cell Array10

FIG.2shows an example of the circuit configuration of the memory cell array10included in the semiconductor memory device1according to the embodiment, focusing on one block BLK among a plurality of blocks BLK included in the memory cell array10. As shown inFIG.2, the block BLK includes, for example, four string units SU0to SU3.

Each string unit SU includes a plurality of NAND strings NS that are respectively associated with bit lines BL0to BLm (m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0to MT15, and select transistors ST1and ST2. Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the select transistors ST1and ST2is used to select a string unit SU at the time of performing various operations.

In each NAND string NS, the memory cell transistors MT0to MT15are coupled in series. The select transistor ST1includes a drain coupled to the associated bit line BL, and a source coupled to one end of each of the memory cell transistors MT0to MT15coupled in series. The select transistor ST2includes a drain coupled to the other end of each of the memory cell transistors MT0to MT15coupled in series. The select transistor ST2includes a source coupled to the source line SL.

In the same block BLK, control gates of the memory cell transistors MT0to MT15are coupled in common to respective word lines WL0to WL15. In the string units SU0to SU3, the gates of the select transistors ST1are coupled in common to respective select gate lines SGD0to SGD3. The gates of the select transistors ST2are coupled in common to select gate line SGS.

In the above-described circuit configuration of the memory cell array10, the word lines WL0to WL7intersect with a portion formed in a memory hole LMH described later, while the word lines WL8to WL15intersect with a portion formed in a memory hole UMH described later. The bit line BL is shared by the NAND string NS to which the same column address is assigned in each string unit SU. The source line SL is shared by a plurality of blocks BLK, for example.

A group of memory cell transistors MT coupled to a common word line WL in a string unit SU is referred to as, for example, a cell unit CU. For example, the storage capacity of the cell unit CU including the memory cell transistors MT each holding 1-bit data is defined as “1-page data”. The cell unit CU may have a storage capacity of data of two or more pages in accordance with the number of bits of data stored in the memory cell transistor MT.

The circuit configuration of the memory cell array10included in the semiconductor memory device1according to the embodiment is not limited to the above described configuration. For example, the number of memory cell transistors MT and select transistors ST1and ST2included in each NAND string NS may be determined as appropriate. The number of string units SU included in each block BLK may be determined as appropriate.

[1-3] Configuration of Memory Cell Array10

An example of the configuration of the memory cell array10according to the embodiment will be described.

In the drawings referred to in the following description, the X direction corresponds to the extending direction of word lines WL, the Y direction corresponds to the extending direction of bit lines BL, and the Z direction corresponds to the direction vertical to the surface of the semiconductor substrate20on which the semiconductor memory device1is formed. In the plan view, shading lines are provided as appropriate for viewability. The shading lines provided in the plan view are not necessarily related to materials or characteristics of elements with the shading lines. In the cross-sectional view, elements such as an insulation film (interlayer insulation film), an interconnect, a contact, etc. are omitted as appropriate for viewability.

FIG.3is an example of the planar layout of the memory cell array10included in the semiconductor memory device1according to the embodiment, focusing on a region including a structure corresponding to one block BLK (i.e., string units SU0to SU3). As shown inFIG.3, the memory cell array10includes a plurality of slits SLT.

The slits SLT each extend in the X direction and are arranged in the Y direction. The slits SLT include insulators to, for example, divide the interconnect layers corresponding to the word lines WL, the interconnect layer corresponding to the select gate line SGD, and the interconnect layer corresponding to the select gate line SGS. In this example, a region divided by the slits SLT corresponds to one string unit SU. That is, the string units SU0to SU3each extending in the X direction are arranged in the Y direction. In the memory cell array10, the layout shown inFIG.3, for example, is repeatedly arranged in the Y direction.

In the planar layout of the memory cell array10described above, a cell area CA and a contact area C4tapare arranged to extend in the Y direction. For example, the cell area CA and the contact area C4tapare alternately arranged in the X direction. The cell area CA is an area where the NAND string NS is formed. The contact area C4tapis an area where a contact is formed for electrically coupling the source line SL coupled to the NAND string NS and the circuit formed between the semiconductor substrate and the memory cell array10. The cell area CA and the contact area C4tapof the memory cell array10will be described below in this order.

(Configuration in Cell Area CA)

FIG.4shows an example of a detailed planar layout of the memory cell array10in the cell area CA of the semiconductor memory device1according to the embodiment. As shown inFIG.4, in the cell area CA, the memory cell array10includes a plurality of memory pillars MP and a plurality of bit lines BL.

The memory pillars MP are, for example, staggered in four lines in a region between neighboring slits SLT. The number or the arrangement of the memory pillars MP between the neighboring slits SLT is not limited to this, and may be changed as appropriate. Each of the memory pillars MP functions as one NAND string NS, for example.

The bit lines BL each extend in the Y direction, and are arranged in the X direction. Each bit line BL is arranged to overlap with at least one memory pillar MP in each string unit SU. In this example, each memory pillar MP overlaps with two bit lines BL. A contact MPC is provided between the memory pillar MP and one bit line BL of the plurality of bit lines BL overlapping with the memory pillar MP. Each memory pillar MP is electrically coupled to the corresponding bit line BL via the contact MPC.

FIG.5is a cross-sectional view taken along line V-V ofFIG.4, and shows an example of a cross-section structure in the cell area CA of the memory cell array10included in the semiconductor memory device1according to the embodiment. As shown inFIG.5, the memory cell array10further includes conductor layers21to26. The conductor layers21to26are provided above the semiconductor substrate20.

Specifically, the conductor layer21is provided via an insulator layer above the semiconductor substrate20. Although illustration is omitted, the insulator layer between the semiconductor substrate20and the conductor layer21is provided with a circuit such as a sense amplifier module16. The conductor layer21is formed in a plate-like shape expanding along the XY plane, for example, and is used as the source line SL. The conductor layer21contains, for example, silicon (Si).

The conductor layer22is provided via the insulator layer above the conductor layer21. The conductor layer22is formed in a plate-like shape expanding along the XY plane, for example, and is used as the select gate line SGS. The conductor layer22contains, for example, silicon (Si).

The insulator layer and the conductor layer23are alternately arranged above the conductor layer22. The conductor layer23is formed in a plate-like shape expanding along the XY plane, for example. For example, the stacked conductor layers23are respectively used as the word lines WL0to WL7in the order from the semiconductor substrate20side. The conductor layer23contains, for example, tungsten (W).

The insulator layer and the conductor layer24are alternately arranged above the uppermost conductor layer23. The conductor layer24is formed, for example, in a plate-like shape expanding along the XY plane. For example, the stacked conductor layers24are respectively used as word lines WL8to WL15in the order from the semiconductor substrate20side. The conductor layer24contains, for example, tungsten.

The insulator layer between the uppermost conductor layer23and the lowermost conductor layer24is thicker than that between the adjacent conductor layers23, and thicker than that between the adjacent conductor layers24. In other words, the space in the Z direction between the uppermost conductor layer23and the lowermost conductor layer24is larger than that in the Z direction between the adjacent conductor layers23, and larger than that in the Z direction between the adjacent conductor layers24.

The conductor layer25is provided via the insulator layer above the uppermost conductor layer24. The conductor layer25is formed in a plate-like shape expanding along the XY plane, for example, and is used as the select gate line SGD. The conductor layer25contains, for example, tungsten.

The conductor layer26is provided via the insulator layer above the conductor layer25. The conductor layer26is formed in a shape of a line extending along the Y direction, for example, and is used as the bit line BL. Namely, a plurality of conductor layers26are arranged along the X direction in a region not shown. The conductor layer26contains, for example, copper (Cu).

The memory pillar MP is provided to extend along the Z direction, and passes through the conductor layers22to25. Each memory pillar MP includes a first portion formed in a lower memory hole LMH, and a second portion formed in an upper memory hole UMH.

Specifically, the first portion corresponding to the memory hole LMH passes through the conductor layers22and23. The first portion corresponding to the memory hole LMH includes a bottom that is located inside the layer in which the conductor layer21is provided. In other words, the bottom of the first portion corresponding to the memory hole LMH is terminated without passing through the conductor layer21. The second portion corresponding to the memory hole UMH is provided above the first portion corresponding to the memory hole LMH, and passes through the conductor layers24and25.

The memory pillar MP includes, for example, a core member30, a semiconductor layer31, a tunnel insulation film32, an insulation film33, a block insulation film34, and a semiconductor portion35. The core member30, the semiconductor layer31, the tunnel insulation film32, the insulation film33, and the block insulation film34are continuously provided between the first portion and the second portion of the memory pillar MP.

Specifically, the core member30is provided to extend along the Z direction. For example, the upper end of the core member30is included in the layer higher than the layer in which the conductor layer25is provided, while the lower end of the core member30is included in the layer in which the conductor layer21is provided. The core member30includes an insulator of silicon oxide (SiO2), etc.

The semiconductor layer31covers the side and bottom surfaces of the core member30. The semiconductor layer31includes a side contact portion SC1. The side contact portion SC1is included in the layer in which the conductor layer21is provided. At the side contact portion SC1, the semiconductor layer31is in contact with the conductor layer21, and electrically coupled to the conductor layer21. The semiconductor layer31contains, for example, silicon.

The tunnel insulation film32covers the side and bottom surfaces of the semiconductor layer31except for the side contact portion SC1. The insulation film33covers the side and bottom surfaces of the tunnel insulation film32except for the side contact portion SC1. The block insulation film34covers the side and bottom surfaces of the insulation film33except for the side contact portion SC1. The tunnel insulation film32and the block insulation film34each contain, for example, silicon oxide. The insulation film33contains, for example, silicon nitride (SiN).

The semiconductor portion35is included in the layer higher than the conductor layer25, and the side surface is in contact with the inner wall of the semiconductor layer31while the bottom surface is in contact with the core member30, for example. The semiconductor portion35and the semiconductor layer31are electrically coupled. The semiconductor portion35is, for example, formed of a material similar to that of the semiconductor layer31.

A column-like contact MPC is provided on the top surfaces of the semiconductor layer31and the semiconductor portion35in the memory pillar MP. In the region illustrated, the contact MPC of one memory pillar MP out of two memory pillars MP is shown. To the memory pillar MP to which the contact MPC is not coupled in this region, a contact MPC is coupled in a region not shown. One conductor layer26, i.e., one bit line BL, is in contact with the top surface of the contact MPC. One contact MPC is coupled to one bit line BL in the space partitioned by the slits SLT.

The slit SLT is formed in a plate-like shape expanding along the XZ plane, for example, and divides the conductor layers22to25. The upper end of the slit SLT is included in the layer between the conductor layers25and26. The lower end of the slit SLT is included in the layer in which the conductor layer21is provided, for example. The slit SLT includes an insulator of silicon oxide, for example.

FIG.6is a cross-sectional view taken along line VI-VI ofFIG.5, and shows an example of the cross-section structure of the memory pillar MP in the semiconductor memory device according to the embodiment. More specifically,FIG.6shows the cross-section structure of the memory pillar MP and its peripheral portion in the layer parallel to the surface of the semiconductor substrate20and including the conductor layer23.

As shown inFIG.6, in the layer including the conductor layer23, the core member30is provided at the center of the memory pillar MP, for example. The semiconductor layer31surrounds the side surface of the core member30. The tunnel insulation film32surrounds the side surface of the semiconductor layer31. The insulation film33surrounds the side surface of the tunnel insulation film32. The block insulation film34surrounds the side surface of the insulation film33. The conductor layer23surrounds the side surface of the block insulation film34.

In the above-described structure of the memory pillar MP, the portion where the memory pillar MP and the conductor layer22intersect with each other functions as the select transistor ST2. The portion where the memory pillar MP and the conductor layer23intersect with each other and the portion where the memory pillar MP and the conductor layer24intersect with each other function as the memory cell transistors MT. The portion where the memory pillar MP and the conductor layer25intersect with each other functions as the select transistor ST1.

Namely, the semiconductor layer31is used as a channel of each of the memory cell transistors MT and the select transistors ST1and ST2. The insulation film33is used as a charge storage layer in the memory cell transistor MT. Therefore, each of the memory pillars MP may function as one NAND string NS.

(Configuration in Contact Area C4tap)

FIG.7shows an example of the detailed planar layout of the memory cell array10in the contact area C4tapof the semiconductor memory device1according to the embodiment. The region shown inFIG.7includes an end region of the cell area CA. As shown inFIG.7, the memory cell array10includes, in the contact area C4tap, a plurality of support pillars HR, contacts C4, and interconnects IC.

In the contact area C4tap, regions CR and PR are provided to each extend in the Y direction. The region CR is provided to be adjacent to the cell area CA. The region PR is provided to be adjacent to the region CR and away from the cell area CA. The region CR includes a plurality of support pillars HR. The region PR includes a plurality of contacts C4. The support pillars HR may be included in the region PR.

Although illustration is omitted, the source line SL in the region CR and the source line SL in the cell area CA are continuously provided, and electrically coupled. In the region PR, the source line SL may or may not be divided. The source line SL in the region PR may be provided to have a different layer structure from the cell area CA and the region CR. The following description is based on the case where the source line SL is divided in the region PR.

Each of the support pillars HR includes a lower end that is electrically coupled to the source line SL. For example, the support pillars HR are arranged between the neighboring slits SLT in the region CR. Each of the contacts C4includes a lower end that is electrically coupled to the interconnect below the memory cell array10. For example, the contact C4is arranged between the neighboring slits SLT in the region PR. The plurality of interconnects IC are arranged to overlap with at least two support pillars HR and at least one contact C4.

The plurality of support pillars HR include those overlapping with the interconnect IC and those not overlapping with the interconnect IC. A contact HRC is provided, as an upper contact, between the support pillar HR and the interconnect IC on the support pillar HR overlapping with the interconnect IC. An upper contact is not provided on the support pillar HR that does not overlap with the interconnect IC. The support pillar HR overlapping with the interconnect IC is electrically coupled to the corresponding interconnect IC via the contact HRC. A contact C4C is provided between the contact C4and the interconnect IC overlapping with the contact C4. The contact C4is electrically coupled to the corresponding interconnect IC via the contact C4C.

In the example ofFIG.7, in each string unit SU region, the interconnect IC is provided to overlap with two support pillars HR and one contact C4. The contacts HRC are provided to correspond to the two support pillars HR, and the contact C4C is provided to correspond to the contact C4. That is, two support pillars HR coupled in parallel to the source line SL and one contact C4are electrically coupled via the interconnect IC.

The planar layout of the memory cell array10in the contact area C4tapcan be modified in various manners, and is not limited to the example ofFIG.7. For example, the interconnect IC may be provided to overlap with three or more support pillars HR. The plurality of support pillars HR overlapping with the interconnect IC may include those provided with the contacts HRC and coupled to the interconnect IC, and those not provided with the contacts HRC and not coupled to the interconnect IC. The support pillar HR, the contact C4, and the interconnect IC do not have to be provided independently for each string unit SU.

FIG.8is a cross-sectional view taken along line VIII-VIII ofFIG.7, and shows an example of the cross-section structure in the contact area C4tapof the memory cell array10included in the semiconductor memory device1according to the embodiment. The region shown inFIG.8includes one memory pillar MP in the cell area CA. As shown inFIG.8, the memory cell array10further includes a conductor layer D2, insulator layers27, and a conductor layer28, in the contact area C4tap.

The conductor layer D2is, for example, an interconnect coupled to the driver module14, and is provided between the semiconductor substrate20and the conductor layer21. The insulator layers27divide the conductor layer21(source line SL), for example. The region where the insulator layers27is provided corresponds to the region PR. The insulator layers27do not necessarily have to be provided, and a conductor layer having a different structure from that of the conductor layer21may be provided in the region where the insulator layer27is provided. In this case, the conductor layer21(source line SL) in the neighboring cell area CA is electrically coupled via the conductor layer of a different structure. The conductor layer28is, for example, provided above the conductor layer26, and used as an interconnect IC.

The support pillar HR is provided to extend along the Z direction, and passes through the conductor layers22to25. The layer including the upper end of the support pillar HR is included in the layer higher than the layer including the upper end of the memory pillar MP. Each support pillar HR includes a first portion formed in a lower hole LHR, and a second portion formed in an upper hole UHR.

Specifically, the first portion corresponding to the hole LHR passes through the conductor layers22and23. The first portion corresponding to the hole LHR includes a bottom that is located inside the layer in which the conductor layer21is provided. In other words, the bottom of the first portion corresponding to the hole LHR is terminated without passing through the conductor layer21. The second portion corresponding to the hole UHR is provided above the first portion corresponding to the hole LHR, and passes through the conductor layers24and25. The upper end of the first portion of the support pillar HR, i.e., the upper end of the first portion formed in the hole LHR, has a height nearly equal to that of the upper end of the first portion of the memory pillar MP, i.e., the upper end of the first portion formed in the memory hole LMH.

The support pillar HR includes, for example, a conductor layer40and an insulation film41. For example, the conductor layer40and the insulation film41are continuously provided between the first and second portions of the support pillar HR.

Specifically, the conductor layer40is provided to extend along the Z direction. For example, the upper end of the conductor layer40is included in the layer higher than the upper end of the semiconductor layer31in the memory pillar MP, while the lower end of the conductor layer40is included in the layer in which the conductor layer21is provided. The conductor layer40is in contact with the conductor layer21at the side contact portion SC2included in the layer in which the conductor layer21is provided, and is electrically coupled to the conductor layer21. The conductor layer40may be a metal or a semiconductor. For example, the conductor layer40may contain tungsten or silicon.

The insulation film41covers the side and bottom surfaces of the conductor layer40except for the side contact portion SC2of the conductor layer40. The insulation film41contains, for example, silicon oxide.

A column-like contact HRC is provided on the support pillar HR coupled to the interconnect IC. Specifically, the contact HRC is provided on the conductor layer40. In the region illustrated, the contact HRC is provided on the top surface of each of two support pillars HR, and one conductor layer28is in contact with the tops of the contacts HRC.

The contact C4is provided to extend along the Z direction, and passes through the conductor layers22to25and the insulator layer27. The upper end of the contact C4is included in the layer higher than the upper end of the support pillar HR. The bottom of the contact C4is in contact with the conductor layer D2. The contact C4has an outer diameter larger than that of the support pillar HR.

The contact C4includes, for example, a conductor layer50and an insulation film51.

Specifically, the conductor layer50is provided to extend in the Z direction. For example, the upper end of the conductor layer50is included in the layer higher than the upper end of the conductor layer40in the support pillar HR, while the lower end of the conductor layer50is in contact with the conductor layer D2. The conductor layer50contains, for example, tungsten.

The insulation film51covers the side surface of the conductor layer50. The insulation film51contains, for example, silicon oxide.

A column-like contact C4C is provided on the contact C4. The top surface of the contact C4C is in contact with the conductor layer28.

FIG.9is a cross-sectional view taken along line IX-IX ofFIG.8, and shows an example of the cross-section structure of the support pillar HR in the semiconductor memory device according to the embodiment. More specifically,FIG.9shows the cross-section structure of the support pillar HR and its peripheral portion in the layer parallel to the surface of the semiconductor substrate20and including the conductor layer23.

As shown inFIG.9, in the layer including the conductor layer23, the conductor layer40is provided at the center of the support pillar HR, for example. The insulation film41surrounds the side surface of the conductor layer40. The conductor layer23surrounds the side surface of the insulation film41.

FIG.10is a cross-sectional view taken along line X-X ofFIG.8, and shows an example of the cross-section structure of the contact C4in the semiconductor memory device according to the embodiment. More specifically,FIG.10shows the cross-section structure of the contact C4and its peripheral portion in the layer parallel to the surface of the semiconductor substrate20and including the conductor layer23.

As shown inFIG.10, in the layer including the conductor layer23, the conductor layer50is provided at the center of the contact C4, for example. The insulation film51surrounds the side surface of the conductor layer50. The conductor layer23surrounds the side surface of the insulation film51.

In the above-described structure of the support pillar HR and the contact C4, the conductor layers40and50function as a current path between the source line SL and the conductor layer D2. Namely, the conductor layer21used as the source line SL is electrically coupled to the conductor layer D2via the conductor layer40, the contact HRC, the interconnect IC, the contact C4C, and the conductor layer50.

The configuration of the memory cell array10has been described as an example above, and the memory cell array10may have other configurations. For example, the number of the conductor layers23or the conductor layers24is determined based on the number of word lines WL. A plurality of conductor layers22provided in a plurality of layers may be allocated to the select gate line SGS. If the select gate line SGS is provided in a plurality of layers, a conductor layer different from the conductor layer22may be used. A plurality of conductor layers25provided in a plurality of layers may be allocated to the select gate line SGD.

The memory pillar MP and the conductor layer26may be electrically coupled via two or more contacts, and may be electrically coupled via other interconnect. Similarly, the support pillar HR and the interconnect IC, and the contact C4and the interconnect IC, may be electrically coupled via two or more contacts, or other interconnect. The inside of the slit SLT may be made of various types of insulators. For example, silicon nitride (SiN) may be formed as a side wall of the slit SLT before silicon oxide is filled in the slit SLT.

[2] Manufacturing Method of Semiconductor Memory Device1

Next, a description will be given of an example of a series of manufacturing processes relating to formation of the stacked interconnect structure inside the memory cell array10in the semiconductor memory device1according to the embodiment.FIGS.11to28each show an example of the cross-section structure including the structure corresponding to the memory cell array10in the process of manufacturing the semiconductor memory device1according to the embodiment. The area shown in the cross-sectional view of each manufacturing process referred to in the following description includes a region where the memory pillar MP, the support pillar HR, the contact C4, and the slit SLT are formed.

First, as shown inFIG.11, a source line portion is formed. The source line portion refers to a stacked structure of the interconnect layer corresponding to the conductor layer21used as the source line SL. In this process, first, an insulator layer60including the conductor layer D2, a conductor layer61, a sacrifice member62, and a conductor layer63are formed in this order on the semiconductor substrate20. Then, a part of each of the conductor layer61, the sacrifice member62and the conductor layer63is removed, and the insulator layer27is formed in the space obtained by removal.

A part of the conductor layer D2and the insulator layer27overlap with the region PR described with reference toFIG.7. Although illustration is omitted, circuits corresponding to the driver module14, the sense amplifier module16, etc. are formed between the semiconductor substrate20and the conductor layer61. The conductor layers61and63each contain, for example, polysilicon with phosphorus doped therein. For the sacrifice member62, a material capable of increasing the etching selection ratio to each of the conductor layers61and63is selected. The insulator layer27contains, for example, silicon oxide (SiO2).

Next, as shown inFIG.12, an insulator layer64is formed on the conductor layer63and the insulator layer27. A conductor layer22is formed on the insulator layer64. An insulator layer65and a sacrifice member66are alternatively arranged on the conductor layer22. An insulator layer67is formed on the uppermost sacrifice member66. The conductor layer22corresponds to the select gate line SGS. The insulator layers64,65, and67each contain silicon oxide, for example. The sacrifice member66corresponds to the word line WL intersecting with the first portion of the memory pillar MP. The sacrifice member66contains, for example, silicon nitride (SiN).

Next, as shown inFIG.13, the memory hole LMH and the hole LHR are formed. Specifically, first, a mask is formed by photolithography, etc. in which areas corresponding to the memory hole LMH and the hole LHR are opened. Then, by anisotropic etching using the formed mask, the memory hole LMH and the hole LHR are formed.

The memory hole LMH and the hole LHR formed in this process pass through the insulator layers64,65and67, the sacrifice members62and66, and the conductor layers22and63, and the memory hole LMH and the hole LHR each include the bottom that is terminated inside the conductor layer61. The anisotropic etching in this process is, for example, reactive ion etching (RIE).

Next, as shown inFIG.14, the sacrifice member68is formed in each of the memory hole LMH and the hole LHR. Specifically, first, the sacrifice members68are formed to fill in the memory hole LMH and the hole LHR. Then, the sacrifice members68formed outside the memory hole LMH and the hole LHR are removed by, for example, chemical mechanical polishing (CMP). The sacrifice member68is, for example, amorphous silicon.

Next, as shown inFIG.15, the insulator layer70is formed on the insulator layer67and the sacrifice members68. The sacrifice member71and the insulator layer72are alternatively arranged on the insulator layer70. The insulator layer73is formed on the uppermost sacrifice member71. The insulator layers70,72, and73each contain, for example, silicon oxide. The sacrifice members71correspond to the word lines WL and the select gate line SGD intersecting with the second portion of the memory pillar MP. The sacrifice member71contains, for example, silicon nitride.

Next, as shown inFIG.16, the memory hole UMH is formed. Specifically, first, a mask is formed by photolithography, etc., in which an area corresponding to the memory hole UMH, i.e., an area overlapping with the memory hole LMH, is opened. Then, by anisotropic etching using the formed mask, the memory hole UMH is formed.

The memory hole UMH formed in this process is provided on the sacrifice member68filled in the memory hole LMH. The memory hole UMH passes through the insulator layers70,72and73, and the sacrifice members71, and at the bottom of the memory hole UMH, a part of the sacrifice member68in the memory hole LMH is exposed. The anisotropic etching in this process is, for example, RIE.

Next, as shown inFIG.17, the memory pillars MP is formed. Specifically, first, the sacrifice member68formed in the memory hole LMH is removed by wet etching, etc. through the memory hole UMH. Next, the block insulation film34, the insulation film33, the tunnel insulation film32, the semiconductor layer31, and the core member30are formed in this order in the memory holes LMH and UMH. Then, the block insulation film34, the insulation film33, the tunnel insulation film32, the semiconductor layer31, and the core member30formed above the top surface of the insulator layer73are removed by, for example, CMP. Then, the upper end of the core member30is etched back up to the inside of the layer in which the insulator layer73is formed, thereby forming a semiconductor portion35in the area where the core member30is removed. As a result, the structure corresponding to the memory pillar MP is formed in each of the memory holes LMH and UMH.

Next, as shown inFIG.18, the hole UHR is formed. Specifically, the insulator layer74is formed on the top surfaces of the insulator layer73and the memory pillar MP. Then, a mask is formed by photolithography, etc., in which an area corresponding to the hole UHR, i.e., an area overlapping with the hole LHR, is opened. Then, by anisotropic etching using the formed mask, the hole UHR is formed.

The hole UHR formed in this process is provided on the sacrifice member68filled in the hole LHR. The hole UHR passes through the insulator layers70,72,73and74, and the sacrifice members71, and at the bottom of the hole UHR, a part of the sacrifice member68in the hole LHR is exposed. The anisotropic etching in this process is, for example, RIE. The insulator layer74contains, for example, silicon oxide.

Next, as shown inFIG.19, the support pillar HR is formed. Specifically, first, the sacrifice member68formed in the hole LHR is removed by wet etching, etc. Thereafter, the insulation film41and the conductor layer40are formed in the holes LHR and UHR. Then, the insulation film41and the conductor layer40formed above the top surface of the insulator layer74are removed by, for example, CMP.

Next, as shown inFIG.20, the contact hole C4H is formed. Specifically, first, the insulator layer75is formed on the top surfaces of the insulator layer74and the support pillar HR. Next, a mask is formed by photolithography, etc. in which an area corresponding to the contact hole C4H is opened. Then, by anisotropic etching using the formed mask, the contact hole C4H is formed.

The contact hole C4H formed in this process passes through the insulator layers27,64,65,67,70,72,73,74and75, the sacrifice members66and71, and the conductor layer22, and at the bottom of the contact hole C4H, a part of the conductor layer D2in the insulator layer60is exposed. The anisotropic etching in this process is, for example, RIE. The insulator layer75contains, for example, silicon oxide.

Next, as shown inFIG.21, the contact C4is formed. Specifically, first, the insulation film51is formed in the contact hole C4H. The insulation film51formed at the bottom of the contact hole C4H is removed so as to expose the conductor layer D2. Then, the conductor layer50is filled in the contact hole C4H, and the insulation film51and the conductor layer50formed above the top surface of the insulator layer75are removed by, for example, CMP.

Next, the replacement process for the source line portion is performed. In the replacement process for the source line portion, the insulator layer76is formed on the top surfaces of the insulator layer75and the contact C4. Next, a mask is formed by photolithography, etc. in which an area corresponding to the slit SLT is opened. Then, by anisotropic etching using the formed mask, the slit SLT is formed as shown inFIG.22.

The slit SLT formed in this process passes through the insulator layers65,67,70,72,73,74,75and76, the sacrifice members66and71, and the conductor layer22, and has the bottom that is terminated inside the insulator layer64. The anisotropic etching in this process is, for example, RIE. The insulator layer76contains, for example, silicon oxide.

The spacer77is formed on the top surface of the insulator layer76and the inner wall of the slit SLT by chemical vapor deposition (CVD), for example. For the spacer77, silicon nitride is formed, for example. By RIE, for example, as shown inFIG.23, the spacer77formed on the top surface of the insulator layer76and the spacer77formed at the bottom of the slit SLT are removed. Thereby, a side wall of silicon nitride is formed on the side surface of the slit SLT.

Etching to remove the spacer77formed at the bottom of the slit SLT is continued after the removal of the spacer77formed at the bottom of the slit SLT. As a result, by the etching, the bottom of the slit SLT reaches the layer in which the sacrifice member62is formed, for example. The slit SLT in this process may pass through the sacrifice member62, or the bottom of the slit SLT may reach the inside layer in which the conductor layer61is formed. The slit SLT in this process may reach at least the sacrifice member62.

By performing etching through the slit SLT, the sacrifice member62is selectively removed. As a result, at the lower end of the memory pillar MP, the side surface of the block insulation film34is exposed, and at the lower end of the support pillar HR, the side surface of the insulation film41is exposed. Next, etching is performed through the space obtained by removing the sacrifice member62to thereby remove a part of each of the block insulation film34, the insulation film33and the tunnel insulation film32as well as a part of the insulation film41exposed in the space. As a result, as shown inFIG.24, at the lower end of the memory pillar MP, a part of the side surface of the semiconductor layer31is exposed, and at the lower end of the support pillar HR, a part of the side surface of the conductor layer40is exposed.

Thereafter, the conductor layer78is formed in the space obtained by removal of the sacrifice member62, a part of each of the block insulation film34, the insulation film33and the tunnel insulation film32, and a part of the insulation film41, and etching back is performed subsequently. As a result, as shown inFIG.25, the semiconductor layer31of the memory pillar MP, the conductor layer40of the support pillar HR, and the source line portion (a group of the conductor layers61,78and63) are electrically coupled. For the conductor layer78, polysilicon with phosphorus doped therein is formed.

Next, the replacement process for the stacked interconnect portion is performed. In the replacement process for the stacked interconnect portion, first, the surfaces of the conductor layers61,78and63(polysilicon film) exposed in the slit SLT are oxidized to form an oxide protective film (not shown). Thereafter, the spacer77and the sacrifice members66and71are removed, as shown inFIG.26, by wet etching using thermal phosphoric acid. In the structure in which the sacrifice members66and71are removed, the three-dimensional configuration thereof is maintained by the memory pillar MP and the support pillar HR, for example. If the oxide protective film is formed on the surface of the polysilicon film, the oxide protective film is not formed on the surface of the spacer77. That is, when the oxide protective film is formed in this process, selective oxidation is performed, for example.

Then, conductors corresponding to the conductor layers23,24and25are formed by, for example, CVD, in the space obtained by removal of the sacrifice members66and71. For the conductors corresponding to the conductor layers23,24and25, for example, a metallic film of tungsten or the like may be filled after a block film of aluminum oxide (Al2O3) is formed.

Then, the conductors formed in the slit SLT are removed by, for example, wet etching, and the plurality of conductor layers23,24and25provided in different layers are separated from one another. As a result, as shown inFIG.27, for example, the conductor layers23corresponding respectively to the word lines WL0to WL7, the conductor layers24corresponding respectively to the word lines WL8to WL15, and the conductor layer25corresponding to the select gate line SGD are formed.

Thereafter, as shown inFIG.28, the insulator79is formed in the slit SLT. In this process, silicon nitride, etc. may be formed as a side wall of the slit SLT before the insulator79is filled in the slit SLT.

In the manufacturing process described above, the NAND string NS, the source line SL coupled to the NAND string NS, the select gate lines SGS and SGD, the word lines WL, the support pillar HR, and the contact C4are formed. It should be noted that the manufacturing process has been described as an example, and other processes may be inserted between processes described.

[3] Advantages of Embodiment

The semiconductor memory device1according to the embodiment described above makes it possible to improve the yield of the semiconductor memory device1. The following is a detailed description of the advantages of the semiconductor memory device1according to the embodiment.

The semiconductor memory device with three-dimensionally stacked memory cells is provided with the stacked interconnects including, for example, the source line SL, the select gate line SGS, the word lines WL, and the select gate line SGD, above the semiconductor substrate. The memory pillar MP is provided to pass through the stacked interconnects above the source line SL, and is electrically coupled to the source line SL arranged in the lowermost layer. As described, in the semiconductor memory device in which the memory cell array is provided above the semiconductor substrate, the interconnect for applying the voltage to the source line SL may be provided below the memory cell array, i.e., between the semiconductor substrate and the source line SL.

In the process of manufacturing the memory cell array having the stacked interconnects, the replacement process for the stacked interconnects is performed, for example. In the replacement process for the stacked interconnects, first, the sacrifice member and the insulator layer are alternatively arranged. Next, for example, after formation of the memory pillar MP, the support pillar HR and the contact C4in the stacked structure, the sacrifice members are removed, and the conductors are formed in the space obtained by removal of the sacrifice members. The three-dimensional configuration in the cell area CA when the sacrifice members are removed is maintained by the plurality of memory pillars MP, while the three-dimensional configuration in the contact area C4tapis maintained by the plurality of support pillars HR and the plurality of contacts C4.

Moreover, for electrically coupling the source line SL and the interconnect below the memory cell array, the semiconductor memory device including the interconnect below the memory cell array uses the contact that is coupled to the source line SL and passes through the stacked interconnects above the source line SL, and the contact C4that is coupled to the interconnect below the memory cell array and has the upper end higher than the uppermost interconnect (select gate line SGD) in the stacked interconnects including the source line SL. The source line SL is electrically coupled to the interconnect below the memory cell array by passing through these two types of contacts and the interconnect above the memory cell array.

The two types of contacts for coupling the source line SL and the interconnect below the memory cell array are provided in such a manner that one is provided on the source line SL while the other is provided on the interconnect below the memory cell array. The two types of contacts are each formed in a hole having a depth corresponding to the height of the stacked interconnect, and preferably formed by the same process for reducing the manufacturing costs. That is, when the two types of contacts are formed by the same process, two types of contact holes having different target bottom positions are formed at the same time. However, etching to form such two types of contact holes is difficult, and there may be variations in bottom positions of the contact holes. There is a concern that a failure may occur resulting from the source line SL due to the variations and the yield of the semiconductor memory device is lowered.

In contrast, the semiconductor memory device1according to the embodiment uses the plurality of support pillars HR provided in the contact area C4tapas the contacts for electrically coupling the source line SL and the interconnect below the memory cell array. Specifically, in the semiconductor memory device1according to the embodiment, the plurality of support pillars HR are provided to overlap with the source line SL, and each of the support pillars HR includes the conductor layer40provided to pass through the stacked interconnects. Each of the conductor layers40is electrically coupled to the source line SL via the side surface, in a manner similar to the memory pillar MP, in the layer in which the source line SL (conductor layer21) is provided.

In addition, the support pillars HR include one to which the contact HRC is coupled at the top and one to which an upper contact is not coupled. The support pillar HR to which the contact HRC is coupled is electrically coupled to the contact C4that passes through the stacked interconnects and that is coupled to the interconnect below the memory cell array. Namely, in the semiconductor memory device1according to the embodiment, the source line SL (conductor layer21) is electrically coupled to the source line drive circuit (e.g., driver module14) via the contact C4and the support pillar HR to which the contact HRC is coupled.

As a result, the semiconductor memory device1according to the embodiment can drive the source line SL via the support pillar HR. In addition, the method of manufacturing the semiconductor memory device1according to the embodiment uses the support pillars HR as the contacts for the source line SL, and therefore the target position of the bottom of the contact hole C4H can be one type in the process of forming the contact hole C4H corresponding to the contact C4. Thus, the method of manufacturing the semiconductor memory device1according to the embodiment can reduce the difficulty in processing the contact hole C4H and can improve the yield.

The conductor layer40included in the support pillar HR is electrically coupled to the source line SL via the side surface in the layer in which the source line SL is provided. This is similar to the coupling between the semiconductor layer31included in the memory pillar MP and the source line SL. That is, the process for coupling the conductor layer40included in the support pillar HR to the source line SL and the process for coupling the semiconductor layer31included in the memory pillar MP to the source line SL can be performed by the same process. Thus, the method of manufacturing the semiconductor memory device1according to the embodiment can reduce the manufacturing processes and can suppress the manufacturing costs.

If the semiconductor memory device1has the memory pillar MP in which two or more pillars are connected, i.e., the first portion formed in the lower memory hole LMH and the second portion formed in the upper memory hole UMH, for example, the support pillar HR is formed in a manner similar to the memory pillar MP to have the structure in which two or more pillars are connected. In this case, the process for the hole LHR passing through the lower stacked interconnects and corresponding to the support pillar HR and the process for the memory hole LMH may be collectively performed. Since the method of manufacturing the semiconductor memory device1according to the embodiment shares some processes of formation of the support pillar HR and the memory pillar MP in common, it is possible to reduce the manufacturing processes and to suppress the manufacturing costs.

In addition, in the semiconductor memory device1according to the embodiment, the plurality of support pillars HR electrically coupled to the source line SL are electrically coupled to one interconnect IC via the contacts HRC provided on the respective support pillars HR, and are electrically coupled to the contact C4via the interconnect IC. That is, in the electric coupling between the source line SL and the contact C4, the plurality of support pillars HR are coupled in parallel to the common interconnect IC. For example, if some processes of formation of the support pillar HR and the memory pillar MP are shared, in general, the outer diameter of the support pillar HR is set to be smaller than the outer diameter of the contact C4; since the plurality of support pillars HR used as the contacts for the source line SL are coupled in parallel, the electrical resistance in the current path between the source line SL and the contact C4is suppressed. Moreover, by electrically coupling the conductor layer40included in the support pillar HR to the source line SL via the side surface of the conductor layer40, it is possible to ensure the contact area in the Z direction between the conductor layer40and the source line SL regardless of the outer diameter of the support pillar HR, and to reduce the contact resistance in the contact surface with the source line SL of each support pillar HR.

The plurality of support pillars HR described above are members used as pillars to maintain the three-dimensional configuration when the replacement process of the stacked interconnects is carried out. The semiconductor memory device1according to the embodiment uses a part of the plurality of support pillars HR as contacts for electrically coupling the source line drive circuit and the source line SL. That is, the semiconductor memory device1according to the embodiment can be realized by the minimum design change, and can suppress the increase in the area of the memory cell array10as well as the manufacturing costs.

[4] Other Modifications

In the above-described embodiment, the memory cell array10may have other configurations. For example, the memory pillar MP may be formed of a single pillar with no connection, or may be formed of three or more pillars connected in the Z direction. Moreover, the memory pillar MP may have a structure in which a pillar corresponding to the select gate line SGD and a pillar corresponding to the word line WL are connected. The inside of the slit SLT may be made of various types of insulators. The number of bit lines BL overlapping with each memory pillar MP may be determined as appropriate.

FIG.29is an example of a cross-sectional structure in a cell CA area and a contact area C4tapof a semiconductor memory device according to a first modification of the embodiment, and corresponds to a region similar to the region shown inFIG.8. As shown inFIG.29, the memory pillar MP and the support pillars HR each may be in contact with the conductor layer21at the bottom.

Specifically, in the embodiment described above, the semiconductor layer31and the conductor layer21are electrically coupled via the side contact portion SC1provided on the side surface of the memory pillar MP; however, the semiconductor layer31and the conductor layer21may be electrically coupled via the bottom of the memory pillar MP. In this case, a part of each of the tunnel insulation film32, the insulation film33and the block insulation film34formed at the bottom of the memory pillar MP is removed, and via this portion, the semiconductor layer31and the conductor layer21are in contact with each other.

For the support pillars HR, a similar modification can be made. In the embodiment described above, the conductor layers40and21are electrically coupled via the side contact portion SC2provided on the side surface of the support pillar HR; however, the conductor layers40and21may be electrically coupled via the bottom of the support pillar HR. In this case, a part of the insulation film41formed at the bottom of the support pillar HR is removed, and via this portion, the conductor layers40and21are in contact with each other.

FIG.30is an example of a cross-sectional structure in a cell area CA and a contact area C4tapof a semiconductor memory device1according to a second modification of the embodiment. As shown inFIG.30, the second modification has a different cross-sectional structure in the region PR including the contact area C4described with reference toFIG.7from the structure of the contact area C4tapshown in the embodiment.

Specifically, the slit80filled with an insulator, for example, is provided around the contact C4. The slit80locally divides the interconnect layers at least provided with the conductor layers23to25in the region PR including the contact C4between the slits SLT adjacent in the Y direction. In each of the interconnect layers provided with the conductor layers23to25, the portion surrounded by the slit80is provided with an insulator layer82. The insulator layer82is, for example, the sacrifice member66or71that is removed by the replacement process of the stacked interconnects described in the embodiment, and corresponds to the sacrifice member66or71remaining in the portion surrounded by the slit80by causing the insulator in the slit80to function as a stopper at the time of the replacement process of the stacked interconnects. The embodiment is not limited to this, and the insulator layer82may be another insulation member (e.g., oxide film) filled in the space obtained by removal of the sacrifice members66and71. In the conductor layer22, the region overlapping with the insulator layer27in the plane view may be replaced with the insulator layer81. Furthermore, the insulation film51may be omitted.

As described above, the contact C4may not directly pass through the conductor layers22to25as in the embodiment, and may be provided to pass through the insulator layers81and82. In the embodiment described above, the structure around the contact C4can be changed as appropriate.

In the manufacturing method described in the embodiment, the support pillar HR is formed after the memory pillar MP is formed; however, the method is not limited to this. The memory pillar MP may be formed after the support pillar HR is formed. In this case, the memory pillar MP may be higher than the support pillar HR.

In the embodiment described above, circuits such as the sense amplifier module16are provided below the memory cell array10of the semiconductor memory device1; however, the configuration is not limited to this. For example, the semiconductor memory device1may have a structure in which a chip provided with the sense amplifier module16, etc. and a chip provided with the memory cell array10are bonded to each other.

In the embodiment described above, the word line WL and the select gate line SGS are adjacent while the word line WL and the select gate line SGD are adjacent; however, the configuration is not limited to this. For example, a dummy word line corresponding to a dummy transistor may be provided between the uppermost word line WL and the select gate line SGD. Similarly, a dummy word line may be provided between the lowermost word line WL and the select gate line SGS. Furthermore, a conductor layer at the vicinity of the contact portion of the memory pillars MP connected in the Z direction may be used as a dummy word line.

In the drawings referred to in the description of the above embodiment, the support pillar HR or the contact C4has a tapered shape, but the embodiment is not limited to this. For example, the support pillar HR or the contact C4may have a reversed tapered shape or a shape having a fat middle part. Similarly, the memory pillar MP or the slit SLT may have a reversed tapered shape or a shape having a fat middle part. Moreover, in the embodiment described above, the support pillar HR, the contact C4, and the memory pillar MP each have a circular cross-section; however, the cross-section thereof may be oval, and may be determined as appropriate.

The term “outer diameter” described in this specification indicates, for example, the outer diameter of the block insulation film34of the memory pillar MP, the outer diameter of the insulation film41of the support pillar HR, or the outer diameter of the insulation film51of the contact C4. The outer diameter of one member being larger or smaller than that of the other member indicates the size relation between the outer diameters in the same layer. In other words, the outer diameters of the first and second members in the same cross section parallel to the surface of the semiconductor substrate20are used for the comparison of the outer diameters between the first and second members.

The term “height” described in this specification indicates the interval between the surface of the semiconductor substrate20and the target portion in the direction vertical to the surface of the semiconductor substrate20. As a criterion of “height”, a structure other than the semiconductor substrate20may be used. For example, if the semiconductor memory device1has a structure in which the chip provided with the memory cell array10and the chip provided with a peripheral circuit such as the sense amplifier module16are bonded to each other, the source line SL (conductor layer21) or the like may be used instead of the semiconductor substrate20as a criterion of “height”.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.