Patent ID: 12261533

Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the teachings herein. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments presented herein.

DETAILED DESCRIPTION

The detailed description set forth below discloses various embodiments to provide a thorough understanding of the present disclosure. It is understood that these exemplary embodiments are intended to illustrate rather than limit the present disclosure. Other embodiments within the scope of the present disclosure will become readily apparent to those skilled in the art from the following detailed description. The exemplary embodiments described herein may be implemented in other and different forms, and its several details are capable of modification in various other respects. In some instances, the specific details of the various embodiments need not be employed to practice the teachings herein. In other instances, well-known structures, components, materials or methods may not be described, or shown in block diagram form, in order to avoid obscuring the present disclosure.

Reference throughout this specification to “one embodiment”, “an embodiment”, “an exemplary embodiment”, “one example” or “an example” means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other examples presented in this disclosure. A particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “in an exemplary embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

Any reference to an element herein using a designation such as “first,” “second,” and so forth does not limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element. As used herein, references to the plural include the singular, and references to the singular include the plural.

The term “switch” as used in the present disclosure includes any for making or breaking a connection in an electric circuit including without limitation, mechanical and electrical switches, bipolar transistors, field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), logic gates, or any other suitable device that performs a switching function.

In the context of the present disclosure, when a transistor is in an “off-state” or “off” the transistor blocks current and/or does not substantially conduct current. Conversely, when a transistor is in an “on-state” or “on” the transistor is able to substantially conduct current. By way of example, in one embodiment, a high-voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) with the high-voltage being supported between the first terminal, a drain, and the second terminal, a source. In some embodiments an integrated controller circuit may be used to drive a power switch when regulating energy provided to a load. Also, for purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured. Additionally, according to power electronics theory (i.e., power is related to the rate of change of energy), “power” transfer may be implied by “energy” transfer; conversely, “energy” transfer may be implied by “power” transfer.

A power converter and/or a power converter stage (e.g. a flyback converter) according to the present disclosure may include primary and secondary controllers that are galvanically isolated (e.g., isolated by a communication link). Additionally, the primary controller and the secondary controller may be galvanically isolated from one another; and the secondary controller may transmit signals to the primary controller to control how the primary controller switches the primary power switch to control the transfer of energy from an energy transfer element (e.g., a transformer) to a load (e.g., to a universal serial bus, a power drawing device, etc.). For example, the secondary controller may transmit signals to the primary controller in response to a sensed output quantity of the power converter.

The primary and secondary controllers may operate to regulate an output quantity (e.g., voltage and/or current) of the power converter that is delivered to the load. For example, the primary and secondary controllers may operate to regulate the output voltage of the power converter to a desired output voltage value in response to a sensed output voltage. Although the primary and secondary controllers may regulate the output voltage in response to a sensed output voltage, in some examples, the primary and secondary controllers may regulate the output voltage and/or the output current of the power converter in response to a sensed output voltage and/or a sensed output current.

Power converters, including multi-stage power converters, are often specified to deliver power from low power levels to a maximum power level; and efficiency is often specified as a figure of merit in terms of input power and output power. For instance, efficiency may be quantified as a percentage (e.g., a ratio) of an input power that is delivered to a load (e.g., output power). Additionally, efficiency may be specified as a ratio of output power (e.g., load power) to input power (e.g., ac mains power).

Efficiency of a multi-stage power converter may be degraded as input power is decreased below its maximum. For instance, at input power levels less than seventy-five percent of maximum, efficiency may be degraded, at least in part, due to the power necessitated by individual stages (e.g., by a power factor correction stage and/or a flyback converter stage). Accordingly, there is a need to reduce supply power (e.g., bias supply power) to one or more of the stages in a multi-stage power converter operating at input power levels less than maximum.

As the load power changes, similar issues with the efficiency of the multi-stage power converter exist. At some load power levels, multiple stages may be used to deliver power. However, at other power levels, the multi-stage power converter would be more efficient if one or more of the stages of the multi-stage power converter were turned off or bypassed by the power delivery from input to load.

Various techniques for a power detection circuit will now be described. These techniques will be presented in the context of multi-stage power converters that use power detection to selectively power or bypass one or more stages. While these techniques may be well suited for these applications, those skilled in the art will realize that such techniques may be extended to other applications. Accordingly, any reference to a multi-stage power converter is intended only to illustrate various aspects of the present disclosure, with the understanding that such aspects may have a wide range of applications.

In an exemplary embodiment of a power converter, an energy transfer element of one stage is used to transfer energy to the load. The energy transfer element may be a transformer or other suitable device. The energy transfer element can be employed in a feedback loop to selectively provide power to another stage in the multi-stage power converter. By way of example, a first stage may be a power factor correction circuit and a second stage may be a flyback converter that uses the energy transfer element to deliver the power to the load. However, the first and second stages, as well as additional stages in some embodiments may be implemented in different ways. Those skilled in the art will readily be able to determine the manner in which the various states based on the present disclosure depending on the particular application and the overall design parameters.

A sensor may be employed to respond to an output of the energy transfer element in the first stage. The output may be provided to the sensor by a bias winding associated with the energy transfer element or by any other suitable means. The sensor may be configured to selectively provide power to the second stage, or cause the second stage to be bypassed, based on the response. In at least one embodiment, the sensor may be implemented with two circuits, each which responds differently to the output of the energy transfer element. Each circuit may include a diode and/or other components that together, or individually, cause the different responses to the output from the energy transfer element. For example, one circuit may include a diode having a reverse recovery time different from the reverse recovery time of the diode in the other circuit. Those skilled in the art will readily understand how to determine the manner in which the various states depend on the particular application and the overall design parameters.

FIG.1Aillustrates a multi-stage power converter100aaccording to an exemplary embodiment of the present disclosure.

The multi-stage power converter100aincludes two stages: a power factor correction (PFC) stage102and a flyback converter stage104. Additional stages may be included without departing from the scope of the present disclosure. The multi-stage power converter100aalso includes an auxiliary bias circuit88that selectively provides power to the PFC stage102based on feedback from the flyback converter stage104.

Output power POUT is delivered to a load106. The output power POUT may be determined, at least in part, by the load current Io and load voltage Vo. Load current Io and load voltage Vo may also be referred to as output current Io and output voltage Vo, respectively, without departing from the scope of the present disclosure.

Alternating current (ac) input power PIN (i.e., ac voltage Vac, ac current Iac) is provided to the full bridge rectifier110between input terminals112,114. The full bridge rectifier110includes four diodes D10, D20, D30, D40and provides rectified dc voltage VRECT to the input of the PFC stage102.

In turn the PFC stage102receives dc voltage VRECT and provides input voltage VIN to the flyback converter stage104. The PFC stage102may include a PFC controller122, a boost inductor126, a boost diode127, a power switch123connected to point125between boost inductor126and boost diode127, and a bypass diode124. As illustrated, the boost inductor126, boost diode127, and power switch123may be configured to boost the rectified dc voltage VRECT.

In accordance with switch mode power supply theory, when enabled the PFC controller122may provide gate signal VGATE to control switch123according to a switching cycle. In this manner the voltage VIN, provided to the flyback converter stage104, may be greater than the rectified dc voltage VRECT. Alternatively, and additionally, the bypass diode124may transfer power to the flyback converter stage104when the PFC controller122is disabled. According to the teachings herein, the auxiliary bias circuit88may enable and disable (i.e., selectively provide power to) the PFC controller122.

The flyback converter stage104includes an energy transfer element139(e.g., a transformer), an output capacitor Co, a primary switch133, a clamp136, and a flyback controller132. The energy transfer element139includes a primary winding135, a core137, a secondary winding134, and an auxiliary winding99. The auxiliary winding99may also be referred to as a bias winding99and/or an auxiliary bias winding99without departing from the scope of the present disclosure. As illustrated, the input voltage VIN may be provided to the primary winding135.

The flyback controller132may provide a gate signal VCS to the primary switch133. When the primary switch133is on (i.e., closed), the primary winding135becomes energized. When the primary switch133turns off (i.e., opens), energy is transferred to the secondary winding134and to the auxiliary winding99. The auxiliary winding99produces a bias winding voltage VBW that is provided to the auxiliary bias circuit88. For emphasis,FIG.1Bshows an example waveform89of the bias winding voltage VBW provided by the auxiliary winding99.

In accordance with power supply theory, clamp136may protect primary switch133by limiting the switch node voltage VSW during operation. Output capacitor Co may reduce ripple (i.e., variation) by filtering the output voltage Vo; and diode138may rectify current in the secondary winding134.

The auxiliary bias circuit88may generate a first bias voltage VBIAS1and a second bias voltage VBIAS2from the bias winding voltage VBW. The first bias voltage VBIAS1may be configured to have a different circuit response than that of the second bias voltage VBIAS2. For instance, the first bias voltage VBIAS1exhibit a “fast” response to changes in the example waveform89; while second bias voltage VBIAS2may exhibit a “slow” response to changes in the example waveform89. Possible differences in characteristics of the circuit responses of the first and second bias voltages VBIAS1, VBIAS2are described hereinbelow.

Because of the difference in circuit response characteristics between the first bias voltage VBIAS1and the second bias voltage VBIAS2, a voltage difference (VBIAS1−VBIAS2) can be obtained. This voltage difference may represent a change in load current Io. The voltage difference may also be a function of load current Io, which is related to input power PIN. Accordingly, the voltage difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2may be related to input power PIN and may be calibrated against input power PIN.

Further, the voltage difference may be related to power drawn by the load, as the change in load current Io is shown by the voltage difference. As such, the voltage difference may also be related to output (load) power POUT; and the voltage difference may be used, via auxiliary bias circuit88, to selectively provide power to the PFC stage102of the multi-stage power converter100aas described herein.

The auxiliary bias circuit88includes a first circuit path141(which may be referred to as a “fast” circuit path141), a second circuit path142(which may be referred to as a “slow” circuit path142), an input power level detection circuit150, filter capacitors143-144, and a pass transistor Q3.

The first circuit path141is electrically coupled to a filter capacitor143, to an input BIAS1of the input power level detection circuit150, and to a supply input VCC1of the flyback controller132. The second circuit path142is electrically coupled to a filter capacitor144and to an input BIAS2of the input power level detection circuit150.

As described above, the auxiliary winding99produces bias winding voltage VBW that is provided to the auxiliary bias circuit88. The bias winding voltage VBW is an ac voltage that is rectified by second circuit path142to produce a positive cycle of the ac voltage and filtered by capacitor144to produce a dc source voltage. The dc source voltage is applied to the flyback controller132via the supply input VCC1. Other circuits (not shown) may be used to further process the dc source voltage, including without limitation, a voltage regulator. Since the dc source voltage to the flyback controller132is generated from the auxiliary winding99, which requires an operational flyback controller, start-up circuitry (not shown) will be required to power the flyback controller132. Those skilled in the art will readily understand how best to implement the start-up circuitry and regulate the dc source voltage generated by the auxiliary winding99based on the specific application and the overall design parameters.

First bias voltage VBIAS1and second bias voltage VBIAS2, or the difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2, and/or the absolute value thereof, may be used as a feedback signal to generate pass signal VPASS. When pass signal VPASS turns on pass transistor Q3, the dc source voltage is supplied to PFC controller122via supply input VCC2. When pass transistor Q3is off, PFC controller122is turned off (i.e., disabled), as supply input VCC2is not supplied. Because the first bias voltage VBIAS1and the second bias voltage VBIAS2vary (i.e., as bias winding voltage VBW varies based on the signals passing through primary winding135and/or secondary winding134vary), the auxiliary bias circuit88will selectively control power application to PFC controller122.

As primary winding135is energized, bias winding99is also energized, and waveform89is produced in bias winding99. As load106draws power POUT, this changes the load current Io through secondary winding134, which also changes the voltage and current through primary winding135and bias winding99. These changes, along with changes created by PFC controller122, may be represented as changes in waveform89of the bias winding voltage VBW. As such, auxiliary bias circuit88, vis-à-vis bias winding99and bias winding voltage VBW, may convey the load conditions, (e.g., the load current Io) when a load106is connected to multi-stage power converter100a.

The input power level detection circuit150passes (i.e., provides) the first bias voltage VBIAS1and/or the second bias voltage VBIAS2to the supply input VCC2of the PFC controller122when the voltage difference (VBIAS1−VBIAS2) exceeds a threshold. The threshold may be based, at least in part, on empirical data, load parameters, circuit or component responses, or other parameters. Further, the threshold may be calibrated against a standard or desired value.

FIG.1Cillustrates a multi-stage power converter100caccording to another exemplary embodiment of the present disclosure.

The multi-stage power converter100cis similar to that of multi-stage power converter100aas described with respect toFIG.1A, except pass transistor Q3has been replaced with a load switch162.

FIG.1Dillustrates a multi-stage power converter100daccording to another exemplary embodiment of the present disclosure.

The multi-stage power converter100dis similar to that of multi-stage power converter100aas described with respect toFIG.1Aexcept the second circuit path142is electrically coupled to a separate auxiliary winding98. In this embodiment the second bias voltage VBIAS2is generated from bias winding voltage VBW2.

FIG.2Aillustrates a flyback converter stage104and load106according to an exemplary embodiment of the present disclosure.

The flyback converter stage104may include a primary switch133, a flyback controller209, a clamp136, energy transfer element139, a synchronous rectifier SR226, and an output capacitor Co. The energy transfer element139includes a primary winding135, a core137, a secondary winding134, and an auxiliary winding99. The auxiliary winding99may also be referred to as a bias winding99and/or an auxiliary bias winding99without departing from the scope of the present disclosure.

The flyback controller209may include a primary controller211connected to primary ground GND and a secondary controller213connected to secondary ground RTN. To communicate across the isolation barrier between the primary controller211and the secondary controller213, signal FL may be transmitted via magnetic coupling (e.g., FluxLink™), optical coupling, or any other suitable means. FluxLink™ is a trademark of Power Integrations, Inc., 5245 Hellyer Ave, San Jose, CA 95138.

The forward pin node223provides a forward pin voltage VFWD indicative of the switching state. Resistor Rw may act as a current limiter to limit current into secondary controller213. Accordingly, the secondary controller213may monitor a forward pin signal FW via forward pin node223to determine when to turn on (and off) the synchronous rectifier SR226. The SR226is controlled by a voltage signal Vcr output from the secondary controller. As illustrated, the synchronous rectifier may be realized with an NFET, although other circuit components may be employed as a synchronous rectifier without departing from the scope of the present disclosure.

During operation, the secondary controller213communicates with the primary controller211to regulate output power (i.e., load current Io and output voltage Vo) delivered to the load106. For instance, when a feedback signal FB1from the load106droops, then the secondary controller213may send a demand pulse via signal FL. In response to a demand pulse via signal FL, the primary controller211may turn on the primary switch133with gate drive signal VCS. The primary controller211may also limit a peak current of the primary switch current Isw by turning off the primary switch133when the switch current Isw exceeds a peak current limit. Feedback signal FB1and the peak current limit may both be set at various values as desired.

In response to a signal SENS from current sense element254, the primary controller211may turn off the primary switch133with gate drive signal VCS. For emphasis,FIG.2Bshows an example waveform83of primary switch current Isw.

FIG.2Cillustrates a flyback converter stage104and load106according to an exemplary embodiment of the present disclosure.

The flyback converter stage104is similar to that ofFIG.2A, except the primary switch133is realized with an NFET233. Other realizations and embodiments for primary switch133are possible without departing from the scope of the present disclosure. For instance, the primary switch133may be realized with a gallium nitride (GaN) cascode and/or a bipolar junction transistor (BJT).

FIG.2Dillustrates a flyback converter stage104and load106according to an exemplary embodiment of the present disclosure.

The flyback converter stage104ofFIG.2Dis similar to that ofFIG.2A, except the load106comprises a universal serial bus (USB)219. Additionally, the flyback converter stage104includes a USB power delivery (PD) controller224which may communicate the state of the USB219to the secondary controller213via PD signals229. Signals235may act as another form of feedback between the USB219and the secondary controller213, such that the USB219can deliver variable load current Io to USB219.

FIG.3illustrates waveforms301-304according to an exemplary embodiment of the present disclosure.

With reference toFIGS.1A-1D(for bias winding voltage VBW) andFIGS.2A-2D(secondary current Isc), waveforms301and302correspond with secondary current Isc under different load conditions, while waveforms303and304correspond with bias winding voltage VBW. For instance, waveforms301and303may respectively correspond to secondary current Isc (i.e., the current in secondary winding134) and bias winding voltage VBW when the load current Io is less than three amperes (3 A); while waveforms302and304may respectively correspond to secondary current Isc and bias winding voltage VBW when the load current Io is greater than twenty amperes (20 A).

Waveforms301and302of the secondary current Isc and waveforms303and304of the bias winding voltage VBW exhibit load dependent ringing. According to switch mode power converter theory, the ringing at times311and313may be due, at least in part, to a leakage inductance of the primary winding135and to capacitance at node NSW. Times312and314indicate the falling edges of bias winding voltage VBW and secondary current Isc.

Additionally, the peak excursions of waveforms301-304are load dependent. For instance, the peak voltage VP2of waveform304is greater and more pronounced than that of waveform303. Similarly, peak current IP2of waveform302is greater than that of peak current IP1.

In one exemplary embodiment, the load dependence of the bias winding voltage VBW may indicate input power level. As the load current Io changes, the currents and voltages in bias winding99(or bias windings98and99as shown inFIG.1D) will change. As bias winding voltages VBW and VBW2change, the response to these changes are reflected in the response differences in the first bias voltage VBIAS1and the second bias voltage VBIAS2. Since the current in bias winding99is related to the current in primary winding135and also related to the current in secondary winding134, the current in bias winding99may indicate input power level to energy transfer element139as well as output power level from energy transfer element139. This embodiment may be used when the flyback converter stage104uses a secondary controller213and when the primary controller211does not directly sample the load current Io.

FIG.4Aillustrates an auxiliary bias circuit88according to an exemplary embodiment of the present disclosure.

As shown in the auxiliary bias circuit88, the first circuit path141may include a recovery diode Dfast (e.g., a “fast” recovery diode), and the second circuit path142may include a recovery diode Dslow (e.g., a “slow” recovery diode). Although “fast” and “slow” may be used as descriptors, so long as the response to the bias winding voltage VBW is different between the first circuit path141and the second circuit path142, a voltage difference may be obtained between the voltages of the first circuit path141and the second circuit path142. For instance, in one exemplary embodiment, the recovery diode Dfast may be realized using component US1DWF-7, manufactured by Diodes Incorporated; while the recovery diode Dslow may be realized using component S1MLHRVG, manufactured by Taiwan Semiconductor Corporation.

Recovery diode Dfast rectifies the bias winding voltage VBW from the auxiliary winding99in the flyback converter stage104(seeFIG.1A) and provides the first bias voltage VBIAS1to input BIAS1. Loading due to additional components may be modeled by impedance403connected in parallel with filter capacitor143. To reduce switching related overvoltage spikes, the first circuit path141also includes a snubber circuit402electrically coupled in parallel with the recovery diode Dfast. The snubber circuit402may be implemented with a series capacitor410and resistor412. The first circuit path141and second circuit path142may also be modified, as desired, to operate with the dual bias windings98and99shown inFIG.1D.

Recovery diode Dslow rectifies the bias winding voltage VBW and provides the second bias winding voltage VBIAS2to input BIAS2. Loading due to additional components may be modeled by impedance404connected in parallel with filter capacitor144.

FIG.4Billustrates an auxiliary bias circuit88according to another exemplary embodiment of the present disclosure.

The auxiliary bias circuit88ofFIG.4Bis like that ofFIG.4Aexcept the collector of pass transistor Q3is electrically coupled to the first circuit path141instead of the second circuit path142. Accordingly, the input power level detection circuit150ofFIG.4Bmay pass the first bias voltage VBIAS1instead of the second bias voltage VBIAS2.

FIG.4Cillustrates an auxiliary bias circuit88according to another exemplary embodiment of the present disclosure.

The auxiliary bias circuit88ofFIG.4Cis similar to that ofFIG.4Aexcept the second circuit path142includes a recovery diode Dfast2electrically coupled in series with a choke LF (e.g., an inductor LF).

The recovery diodes Dfast and Dfast2may have similar characteristics. For instance, recovery diode Dfast and recovery diode Dfast2may both be realized using component US1DWF-7, manufactured by Diodes Incorporated. However, choke LF in series with fast recovery diode Dfast2may functionally operate like recovery diode Dslow. As one may appreciate, other realizations of a first circuit path141and second circuit path142are possible without departing from the scope of the present disclosure.

FIG.5Aillustrates graphs503-509of measured voltage versus load current Io according to an exemplary embodiment of the present disclosure.

Graphs502and504may respectively correspond to first bias voltage VBIAS1and second bias voltage VBIAS2when ac voltage Vac is two hundred sixty five volts ac (265 VAC) and output voltage Vo is twenty volts (20V); graphs503and505may respectively correspond to first bias voltage VBIAS1and second bias voltage VBIAS2when ac voltage Vac is ninety volts ac (90 VAC) and output voltage Vo is twenty volts (20V).

Graphs506and508may respectively correspond to first bias voltage VBIAS1and second bias voltage VBIAS2when ac voltage Vac is two hundred sixty five volts ac (265 VAC) and output voltage Vo is fifteen volts (15V); and graphs507and509may respectively correspond to first bias voltage VBIAS1and second bias voltage VBIAS2when ac voltage Vac is ninety volts ac (90 VAC) and output voltage Vo is fifteen volts (15V).

FIG.5Billustrates graphs512,513,516,517of measured voltage versus load current Io according to an exemplary embodiment of the present disclosure.

Graph512may correspond with the difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2when ac voltage Vac is two hundred sixty five volts ac (265 VAC) and output voltage Vo is twenty volts (20V). Graph513may correspond with the difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2when ac voltage Vac is ninety volts ac (90 VAC) and output voltage Vo is twenty volts (20V). Graph516may correspond with the difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2when ac voltage Vac is two hundred sixty-five volts ac (265 VAC) and output voltage Vo is fifteen volts (15V). Graph517may correspond with the difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2when ac voltage Vac is ninety volts ac (90 VAC) and output voltage Vo is twenty volts (15V).

FIG.5Cillustrates graphs522-525of measured voltage versus load current Io according to an exemplary embodiment of the present disclosure.

Graphs522,523,524, and525may correspond with the difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2at forty-five degrees Celsius, twenty-five degrees Celsius, ten degrees Celsius, and zero degrees Celsius, respectively. Additionally, the ac voltage Vac may be two hundred sixty-five volts ac (265 VAC) and the output voltage Vo may be fifteen volts (15V).

FIG.5Dillustrates graphs532of measured voltage versus load current Io according to an exemplary embodiment of the present disclosure.

The graphs532may correspond with the difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2sampled from nine different boards (e.g., nine different circuit boards of a multi-stage power converter100a). Additionally, the ac voltage Vac may be two hundred sixty-five volts ac (265 VAC) and the output voltage Vo may be twenty volts (20V).

The data presented by graphs502-509,512-513,516-517,522-525, and532, may provide guidance to the skilled artisan in the design of an input power level detection circuit150(see, e.g.,FIG.1A). For instance, by analyzing variation like that presented by the graphs ofFIG.5AthroughFIG.5D, an input power level detection circuit150may be tailored to meet specification, calibrated against a standard or desired value, or other parameters as desired.

FIG.6illustrates an input power level detection circuit150according to an exemplary embodiment of the present disclosure. Input power level detection circuit150includes shunt regulator U3, resistor divider601, capacitor C11, resistor R15, resistor R16, bipolar junction transistor Q1, circuit path602, shunt regulator U4, resistor divider603, circuit path604, Zener diode D5, resistors R20-R22, and a p-type field effect transistor (PFET) Q2.

The shunt regulator U3may be configured to operate as a comparator and may be realized using a component LMV431 (manufactured by Texas Instruments) or any other suitable device. Resistor divider601, implemented by series resistors R12and R13, may provide a voltage VX1proportional to the difference of the first bias voltage VBIAS1and the second bias voltage VBIAS2. When the voltage VX1exceeds a reference value (e.g., 1.24V) of shunt regulator U3, then shunt regulator U3may turn on and provide voltage to the voltage divider implemented by resistors R15and R16. In response to the shunt regulator U3turning on, a voltage VX2may be provided at the base of bipolar junction transistor (BJT) Q1.

Capacitor C11may provide filtering (e.g., low pass filtering) to improve the response of shunt regulator U3; and circuit path602, including diode D3and resistor R14, may introduce hysteresis by providing positive feedback to the resistor divider601.

Shunt regulator U4, realized with component ATL431BQDBZR (manufactured by Texas Instruments) or any other suitable device, may also be configured as a comparator. Resistor divider603, implemented by series resistors R17and R18, may provide voltage VX3proportional to the collector current from BJT Q1; and circuit path604, including diode D4and resistor R18, may introduce hysteresis by providing positive feedback to the resistor divider603.

Accordingly, when BJT Q1turns on and voltage VX3exceeds an internal reference of shunt regulator U4, the shunt regulator U4may drive the gate of PFET Q2via resistors R20and R21. For instance, in response to shunt regulator U4turning on, voltage VX4may decrease sufficiently to drive the gate of PFET Q2.

As illustrated, pass transistor Q3may be switched on in response to PFET Q2turning on; and current flowing through limiting resistor R22may drive the base of pass transistor Q3. In turn, pass transistor Q3may provide regulated voltage VP. In accordance with the theory of linear regulators, voltage VP may be regulated, at least in part, by a voltage of the Zener diode D5less a base-to-emitter voltage of pass transistor Q3.

As described in connection withFIGS.1A-1D, the regulated voltage VP may be provided to the supply input VCC2of the PFC controller122. Accordingly, the pass transistor Q3allows the second bias voltage VBIAS2to pass to the supply input VCC2of the PFC controller122.

Also, the input power level detection circuit150passes (i.e., provides) the second bias voltage VBIAS2to the supply input VCC2of the PFC controller122when the voltage difference (VBIAS1−VBIAS2) exceeds a calibrated threshold. The calibrated threshold may be based, at least in part, on empirical data like that presented inFIG.5A-5D. Additionally, in some embodiments, the first bias voltage VBIAS1can be passed (i.e., provided) instead of second bias voltage VBIAS2.

With reference toFIG.6, the resistor divider601may be adjusted to calibrate the threshold. For instance, it may be determined empirically that a calibrated threshold of input power may be sixty five percent of the maximum. Using a mapping of output current to measured input power, data like that presented inFIG.5A-5Dmay be used to determine a corresponding voltage difference between the first bias voltage VBIAS1and the second bias voltage VBIAS2.

CONCLUSION

The above description of illustrated examples of the present disclosure, including what is described in the Abstract are not intended to be exhaustive or to be limiting to the precise forms disclosed. While specific embodiments of, and examples for, a power detection circuit for a power converter are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings herein.

The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding whether these features, elements and/or states are included or are to be performed in any particular embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present disclosure is defined only by reference to the appended claims.