Patent ID: 12199096

DETAILED DESCRIPTION

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments will be described with reference to the accompanying drawings.

FIG.1Aschematically illustrates a layout of a partial region of a semiconductor device according to an embodiment.FIG.1Bshows a perspective view illustrating a vertical cross-section taken along lines A-A′ and B-B′ ofFIG.1A.FIG.1Cshows vertical cross-sectional views taken along lines I-I′ and II-II′ ofFIG.1A.FIG.1Dshows vertical cross-sectional views taken along lines III-III′ and IV-IV′ ofFIG.1A. For brevity, the illustration of active regions and an interlayer insulating layer is omitted inFIG.1A, and the illustration of components at a level above a top end of a gate line is omitted inFIG.1B.

Referring toFIGS.1A to1D, a semiconductor device100amay include a substrate101, active regions AR1and AR2, active fins F1and F2, device isolation layers STI and DTI, a first field insulating layer SDB, a second field insulating layer IFR, gate lines GL and GLB, a gate isolation layer IG, gate spacers114, source and drain regions120, and interlayer insulating layers130and135.

The substrate101may include a first region P and a second region N. For example, the first region P may be a P-type metal-oxide-semiconductor (PMOS) region, and the second region N may be an N-type MOS (NMOS) region. The substrate101may include a semiconductor material, such as silicon and germanium. For example, the substrate101may be formed of at least one material selected out of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium phosphide (GaP), gallium arsenide (GaAs), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), and indium phosphide (InP). However, the substrate101may be a silicon on insulator (SOI) substrate.

The active regions AR1and AR2may include a first active region AR1and a second active region AR2. The first active region AR1may be in the first region P, and the second active region AR2may be in the second region N. The active regions AR1and AR2may extend in a first direction. The active regions AR1and AR2may be spaced to be apart from each other in a second direction intersecting the first direction. The active regions AR1and AR2may protrude in a third direction, intersecting the first and second directions, which is vertical to, e.g. orthogonal to, a surface of the substrate101. Top ends of the first active region AR1and the second active region AR2may be at a relatively high level LV_AR1. In an embodiment, a top end of a portion of the second active region AR2may be at a relatively low level LV_AR2.

The active fins F1and F2may include a first active fin F1in the first region P and a second active fin F2in the second region N. The first active fin F1may be on the first active region AR1, and the second active fin F2may be on the second active region AR2. The active fins F1and F2may extend in the first direction. Each of the active fins F1and F2may include long-axial sidewalls L, which extend in the first direction, and short-axial sidewalls S, which extend in the second direction. The long-axial sidewalls L are longer than the short-axial sidewalls S. The active fins F1and F2may be spaced to be apart from each other in the first direction so that the short-axial sidewalls S of the active fins F1and F2may face each other. The active fins F1and F2may be spaced apart from each other in the second direction so that the long-axial sidewalls L of the active fins F1and F2may face each other. The active fins F1and F2may protrude in the third direction from the active region AR1and AR2. Although two active fins F1and F2are illustrated as being on one of the active regions AR1and AR2, one or at least three active fins may be on one of the active regions AR1and AR2.

The active regions AR1and AR2and the active fins F1and F2may be portions of the substrate101, and may include epitaxial layers grown from the substrate101. In an embodiment, the active regions AR1and AR2and the active fins F1and F2may include a semiconductor material. For example, the active regions AR1and AR2and the active fins F1and F2may include silicon (Si), silicon germanium (SiGe), or the like. The active regions AR1and AR2and the active fins F1and F2may include the same material as the substrate101. For example, when the substrate101includes Si, the active regions AR1and AR2and the active fins F1and F2may also include Si. However, the substrate101may include a different material from the active regions AR1and AR2and the active fins F1and F2.

The device isolation layers STI and DTI may include a shallow device isolation layer STI and a deep device isolation layer DTI. The device isolation layers STI and DTI may define the active regions AR1and AR2and the active fins F1and F2. For example, the device isolation layers STI and DTI may cover sidewalls of the active regions AR1and AR2on the substrate101. The device isolation layers STI and DTI may cover lower sidewalls of the active fins F1and F2, but may not cover upper portions thereof. In an embodiment, the shallow device isolation layer STI may be in the first region P and the second region N, and the deep device isolation layer DTI may be in the first region P and the second region N. A bottom surface of the deep device isolation layer DTI may be at a lower level, e.g., closer to the substrate101along the third direction, than a bottom surface of the shallow device isolation layer STI. The device isolation layers STI and DTI may include any one of oxide, oxynitride, nitride, or the like.

The first field insulating layer SDB may be in contact with the short-axial sidewalls S of the first active fins F1in the first region P and extend in the second direction. The first field insulating layer SDB may be on the device isolation layers STI and DTI, and a partial region of the first field insulating layer SDB may extend downward, e.g., along the third direction towards the substrate101, and be between the first active fins F1. A partial region of the first field insulating layer SDB may be between the first active regions AR1. That is, the partial region of the first field insulating layer SDB may extend downward, e.g., along the third direction towards the substrate101, so that a level LV1of a bottom end of the extended portion of the first field insulating layer SDB may be lower than a level LV_F of top ends of the active fins F1and F2and higher than a level LV_AR1of a top end of the first active region AR1. Alternatively, the partial region of the first field insulating layer SDB may extend further downward, e.g., along the third direction towards the substrate101, so that the level LV1of the bottom end of the extended portion of the first field insulating layer SDB is lower than the level LV_AR1of the top end of the first active region AR1. A level of a top surface of the first field insulating layer SDB may be higher, further from the substrate101along the third direction, than the level LV_F of the top ends of the active fins F1and F2and higher than a level of top ends of the source and drain regions120.

In an embodiment, two first field insulating layers SDB may be adjacent to each other in the first direction, e.g., no other components that extend along the second direction are therebetween, and may be parallel to each other and extend in the second direction. One source or drain region120may be between the two first field insulating layers SDB.

In an embodiment, the first field insulating layer SDB may include a compressive stress material and/or a tensile stress material. For example, the compressive stress material may be a material capable of applying compressive stress to an active region, and the tensile stress material may be a material capable of applying tensile stress to the active region. For instance, the first field insulating layer SDB may include silicon nitride.

The second field insulating layer IFR may be in contact with the short-axial sidewalls S of the second active fins F2in the second region N and extend in the second direction. The second field insulating layer IFR may be in contact with the device isolation layers STI and DTI. A bottom surface of the second field insulating layer IFR may be in contact with a portion of the second active region AR2which has a top end having a relatively low level LV_AR2, e.g., closer to the substrate101along the third direction than that of the first active region AR1. A width of the second field insulating layer IFR in the first direction may be greater than a width of the first field insulating layer SDB. In an embodiment, a level LV2of the bottom surface of the second field insulating layer IFR may be different from the level LV1of the bottom end of the first field insulating layer SDB. A level LV3of a top surface of the second field insulating layer IFR may be lower than the level LV_F of the top ends of the active fins F1and F2and higher than top surfaces of the device isolation layers STI and DTI. However, the level LV3of the top surface of the second field insulating layer IFR may be higher than the level LV_F of the top ends of the active fins F1and F2or may be lower than or equal to the level of the top surfaces of the device isolation layers STI and DTI.

In an embodiment, the second field insulating layer IFR may be formed of the same material as the device isolation layers STI and DTI. Although a boundary between the second field insulating layer IFR and the device isolation layers STI and DTI is clearly illustrated, the second field insulating layer IFR may be integrally formed with the device isolation layers STI and DTI. That is, the second field insulating layer IFR may be a portion of the device isolation layers STI and DTI. In an embodiment, the second field insulating layer IFR may include a tensile stress material and/or a compressive stress material. For example, the second field insulating layer IFR may include an oxide, e.g., tetraethyl orthosilicate (TEOS).

The gate lines GL may intersect the active fins F1and F2on the device isolation layers STI and DTI, and extend in the second direction. The gate lines GL may be spaced apart from the first field insulating layer SDB in the first direction and parallel to the first field insulating layer SDB. The gate lines GLB may be spaced apart from the first field insulating layer SDB in the second direction and spaced apart from the gate lines GL in the first direction. A width of the gate lines GL and GLB in the first direction may be substantially equal to a width of a top end of the first field insulating layer SDB in the first direction.

Any two (e.g., GLB) of the gate lines GL and GLB may be in contact with the top surface of the second field insulating layer IFR and intersect the second field insulating layer IFR. For example, as shown inFIGS.1A,1C, and1D, a first gate line GLB may cover a first end portion of the second active fin F2and a portion of the top surface of the second field insulating layer IFR, while a second gate line GLB may cover a second end portion of the second active fin F2, opposite the first end portion across the second field insulating layer IFR, and another portion of the top surface of the second field insulating layer IFR. Thus, from among the first field insulating layer SDB and the second field insulating layer IFR, a field insulating layer having a width corresponding to the gate lines GL and GLB may be called a “single diffusion break region.” Further, from among the first field insulating layer SDB and the second field insulating layer IFR, a field insulating layer having a width in the first direction greater than a shortest distance between the gate lines GL and GLB in the first direction may be called a “double diffusion break region.” That is, the first field insulating layer SDB shown inFIG.1Cmay be a single diffusion break region, and the second field insulating layer IFR may be a double diffusion break region.

The gate lines GL and GLB may include gate electrodes115and115b, gate insulating layers116and116b, and gate capping layers117and117b, respectively. Each of the gate electrodes115and115bmay include at least two stacked layers. In an embodiment, each of the gate electrodes115and115bmay include a first gate metal layer and a second gate metal layer. The first gate metal layer may control a work function and the second gate metal layer may fill a space in the first gate metal layer. The first gate metal layer may include, e.g., at least one of titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), a combination thereof, or the like. In addition, the second gate metal layer may include, e.g., at least one of tungsten (W), aluminum (Al), cobalt (Co), titanium (Ti), tantalum (Ta), polysilicon (poly-Si), silicon germanium (SiGe), a metal alloy, or the like.

The gate insulating layers116and116bmay be between the gate electrodes115and115band the active fins F1and F2, respectively. Further, the gate insulating layers116and116bmay be between the gate electrodes115and115band the device isolation layers DTI and STI, respectively. In an embodiment, the gate insulating layer116may extend in the second direction along profiles of the active fins F1and F2protruding from the device isolation layers DTI and STI. The gate insulating layers116and116bmay extend in the third direction along a side surface of the gate electrode115. The gate insulating layers116and116bmay include a high-k dielectric material having a higher dielectric constant than silicon oxide. For example, the gate insulating layers116and116bmay include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (LaO), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), or the like. For example, the gate electrodes115and115band the gate insulating layers116and116bmay be formed using a replacement process (or a gate last process).

The gate capping layers117and117bmay be on the gate electrodes115and115band the gate insulating layers116and116b. For example, the gate capping layers117and117bmay include at least one of a silicon nitride film and a silicon oxynitride film.

In an embodiment, the gate line GLB and the first field insulating layer SDB may be form a line in the second direction, e.g., the first field insulating layer SDB may be in the first region P and the gate line GLB may be in the second region N. The gate line GLB may be spaced to be apart from the first field insulating layer SDB in the second direction, e.g., by a gate isolation layer IG. A short-axial sidewall Sg of the gate line GLB, which extends in the first direction, may face a short-axial sidewall Ss of the first field insulating layer SDB. The gate line GLB may overlap a portion of the second field insulating layer IFR from viewed from above, e.g., in plan view and along the third direction.

In an embodiment, the gate electrode115band the first field insulating layer SDB may form a line in the second direction, e.g., may overlap along the second direction. The gate electrode115bmay be spaced to be apart from the first field insulating layer SDB in the second direction. A first side surface (i.e., a short-axial sidewall), which extends in the first direction, of the gate electrode115bmay face the short-axial sidewall Ss of the first field insulating layer SDB.

The gate insulating layer116bmay cover a bottom surface of the gate electrode115b, a short-axial side surface of the gate electrode115bwhich extends in the first direction, and a long-axial side surface of the gate electrode115bwhich extends in the second direction. The gate insulating layer116bmay be between the second field insulating layer IFR and the gate electrode115b, between the second active fins F2and the gate electrode115b, and between the device isolation layers STI and DTI and the gate electrode115b. That is, the gate insulating layer116may extend in the second direction along profiles of the device isolation layers STI and DTI, the second field insulating layer IFR, and the second active fins F2. The gate insulating layer116bmay extend in the third direction along side surfaces of the gate electrode115b. In other words, the gate insulating layer116bmay separate the gate electrode115bfrom other components immediately adjacent thereto.

The gate isolation layer IG may be on the device isolation layers STI and DTI between the first field insulating layer SDB and the gate line GLB. A first side surface Sig1of the gate isolation layer IG may be in contact with the short-axial sidewall Ss of the first field insulating layer SDB. A second side surface Sig2of the gate isolation layer IG may be in contact with the short-axial sidewall Sg of the gate line GLB. That is, the second side surface Sig2of the gate isolation layer IG may be in contact, e.g., direct contact, with the gate insulating layer116band the gate capping layer117b. The gate isolation layer IG may be in contact with a portion of the gate insulating layer116b, that extends in the third direction between the gate electrode115band the gate isolation layer IG. In an embodiment, the gate isolation layer IG may be formed of a single insulating material or a plurality of insulating materials. For instance, the gate isolation layer IG may be formed of silicon oxide, silicon nitride, air spaces, a combination thereof, or the like.

The gate spacers114and114bmay be on both sidewalls of the gate lines GL and GLB, respectively. That is, the gate spacers114and114bmay extend in the second direction and be in contact with both side surfaces, e.g., sides surfaces spaced apart along the first direction, of the gate insulating layers116and116b, and of the gate capping layer117and117b, respectively. Further, the gate spacers114may extend in the second direction and may also be on both sidewalls of the gate isolation layer IG and both sidewalls of the first field insulating layer SDB.

In an embodiment, the gate spacers114may include first gate spacers114a, second gate spacers114b, and third gate spacers114c. The first gate spacers114amay be on both sidewalls of the first field insulating layer SDB. The second gate spacers114bmay be on both sidewalls of the gate line GLB, which may overlap the first field insulating layer SDB along the second direction. The third gate spacers114cmay be on both sidewalls of the gate isolation layer IG between the first gate spacers114aand the second gate spacers114bin the second direction. The first gate spacers114amay be connected to the third gate spacers114c, and the second gate spacers114bmay be connected to the third gate spacers114cso that the first to third gate spacers114a,114b, and114cmay integrally form the gate spacers114. In an embodiment, the gate spacers114may include nitride. A level of top ends of the gate spacers114may be equal to a level of top surfaces of the gate capping layers117and117band a level of the top surface of the first field insulating layer SDB. For example, the gate spacers114may include at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, a combination thereof, or the like.

The source and drain regions120may be on both sides of the gate spacers114and the gate lines GL and GLB. The source and drain regions120may be in the active fins F1and F2. That is, the source and drain regions120may be formed in partially etched regions of the active fins F1and F2. Although the source and drain regions120are illustrated as being in contact with each other in the second direction inFIG.1B, the source and drain regions120may be spaced to be apart from each other along the second direction. In an embodiment, the source and drain regions120may be elevated source and drain regions. Thus, the top ends of the source and drain regions120may be at a higher level than the top ends of the active fins F1and F2.

In an embodiment, the source and drain regions120in the first region P may include a compressive stress material. For example, the compressive stress material may be a material (e.g., SiGe) having a higher lattice constant than silicon. The compressive stress material may apply compressive stress to the active fins F1and F2(i.e., channel regions) under the gate lines GL and GLB and improve the mobility of carriers in the channel regions. Meanwhile, the source and drain regions120in the second region N may include the same material as the substrate101or a tensile stress material. For instance, when the substrate101includes silicon, the source and drain regions120may include silicon or a material (e.g., silicon carbide (SiC) and silicon phosphide (SiP)) having a lower lattice constant than silicon. The tensile stress material may apply tensile stress to the active fins F1and F2(i.e., the channel regions) under the gate lines GL and GLB and improve the mobility of carriers in the channel regions.

In an embodiment, the source and drain regions120may be formed using an epitaxial growth process. A silicide layer may be formed on the source and drain regions120. The silicide layer may be formed along top surfaces of the source and drain regions120. The silicide layer may serve to reduce a sheet resistance, a contact resistance, or the like when the source and drain regions120are in contact with a first contact CA1. The silicide layer may include a conductive material, for example, platinum (Pt), nickel (Ni), cobalt (Co), or the like. The silicide layer may be a layer formed by siliciding the source and drain regions120that are in contact with the first contact CA1.

A first interlayer insulating layer130may cover the source and drain regions120, the gate lines GL and GLB, the gate spacers114, the first field insulating layer SDB, and the device isolation layers STI and DTI. A second interlayer insulating layer135may cover the first interlayer insulating layer130. The first interlayer insulating layer130and the second interlayer insulating layer135may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or the like.

The first contact CA1may pass through, e.g., extend along the third direction, the first interlayer insulating layer130to contact the source or drain region120. The first contact CA1may electrically connect the source or drain region120with a first interconnection M1. For example, the first contact CA1may have an elongated shape, e.g., that extends along the second direction, when viewed from above, e.g., in plan view. The first contact CA1may include a conductive material. The first contact CA1may include, for example, tungsten (W), aluminum (Al), copper (Cu), or the like. The first contact CA1may include a barrier layer and a conductive layer.

A first via V1may extend along the third direction through the second interlayer insulating layer135to contact the first contact CA1. The first via V1may electrically connect the first contact CA1with the first interconnection M1. The first interconnection M1may be on the second interlayer insulating layer135. The first interconnection M1may be electrically connected to the first via V1.

A second contact CA2may be on the gate line GL. The second contact CA2may extend along the third direction through the first interlayer insulating layer130and the gate capping layer117to be in contact with the gate electrode115. The second contact may extend along the first direction. The second via V2may extend along the third direction through the second interlayer insulating layer135to contact the second contact CA2. The second via V2may electrically connect the second contact CA2with the second interconnection M2. The second interconnection M2may be on the second interlayer insulating layer135. The second interconnection M2may be electrically connected to the second via V2.

FIGS.1E and1Fshow vertical cross-sectional views taken along a line IV-IV′ ofFIG.1A, according to embodiments. Hereinafter, the same descriptions as inFIGS.1A to1Dwill be omitted for brevity.

Referring toFIG.1E, the second field insulating layer IFR may extend along a second direction and be in contact with the gate isolation layer IG, e.g., may have an upper portion of a sidewall of the second field insulating layer IFR in contact with a lower portion of the gate isolation layer IG. Although a portion of one side surface of the gate isolation layer IG is illustrated as being in contact with a portion of another side surface of the second field insulating layer IFR, the second field insulating layer IFR may further extend in the second direction so that a bottom surface of the gate isolation layer IG may be in contact with an upper surface of the second field insulating layer IFR. A level LV3of a bottom surface of a gate line GLB may be higher than a level of the bottom surface of the gate isolation layer IG and higher than a level LV_TI of top surfaces of device isolation layers STI and DTI.

Referring toFIG.1F, each of a gate electrode115band a gate capping layer117bmay be in contact with the gate isolation layer IG. That is, unlike that which is shown inFIGS.1D and1E, the gate insulting layer116bmay be only under the gate line GLB and may not extend in a third direction between the gate isolation layer IG and the gate electrode115b.

FIG.2Aillustrates a layout of a partial region of a semiconductor device according to an embodiment.FIG.2Bis a perspective view illustrating a vertical cross-section taken along lines A-A′ and B-B′ ofFIG.2A.FIG.2Cshows vertical cross-sectional views taken along lines I-I′ and II-II′ ofFIG.2A.FIG.2Dshows vertical cross-sectional views taken along lines III-III′ and IV-IV′ ofFIG.2A.FIG.2Eshows a vertical cross-sectional view taken along lines I-I′ ofFIG.2A, according to an embodiment. Hereinafter, the same descriptions as inFIGS.1to1Fwill be omitted for brevity.

Referring toFIGS.2A to2D, the semiconductor device100bmay include a first field insulating layer DB, pairs of outer gate spacers114a,114b, and114c, and pairs of inner gate spacers114a′,114b′, and114c′.

The first field insulating layer DB may be in contact with short-axial sidewalls S of fin active fins F1in a first region P and extend in a second direction. In an embodiment, a width of a top surface of the first field insulating layer DB in the second direction may be at least twice of a width of the top surface of the above-described first field insulating layer SDB in the second direction. A width of the top surface of the first field insulating layer DB in the first direction may be greater than a shortest distance between gate lines GL in the first direction. Thus, the first field insulating layer DB may be called a “double diffusion break region.” Thus, while the diffusion break regions in both the first region P and the second region N may both be double diffusion break regions, they have different structures.

In an embodiment, the first field insulating layer DB may include a first portion DB1, a second portion DB2, and a third portion DB3. Portions of the first portion DB1and the second portion DB2may extend downward, e.g., along the third direction towards the substrate101, and be between the first active fin F1and device isolation layers STI and DTI. Alternatively, the portions of the first portion DB1and the second portion DB2may extend further downward and be between the first active fin F1, the first active region AR1, and the device isolation layers STI and DTI. The third portion DB3may be between the first portion DB1and the second portion DB2, e.g., may extend therebetween along the first direction. The third portion DB3may be formed by extending an upper portion of the second portion DB2in a direction toward the second portion DB2and extending an upper portion of the second portion DB2in a direction toward the first portion DB1. In an embodiment, a bottom surface of the third portion DB3may be at a higher level than a top end of the first active fin F1. The first active fin F1, source and drain regions120, and a first interlayer insulating layer130may be between the first portion DB1and the second portion DB2, and under the third portion DB3. As an example, the bottom surface of the third portion DB3may have a convex or U shape.

In an embodiment, each of two gate lines GLB may be spaced to be apart from the first field insulating layer DB in the second direction and in a second region N. The two gate lines GLB may be spaced apart from each other and parallel to each other in the first direction. Short-axial sidewalls Sg of the two gate lines GLB, which extend in the first direction, may face short-axial sidewalls Sd of the first field insulating layer DB. For example, a first of the two gate lines GLB may extend linearly from the first portion DB1of the first field insulating layer DB, and a second of the two gate lines GLB may extend linearly from the second portion DB2of the first field insulating layer DB.

The gate isolation layer IG may be in the second direction on the device isolation layers STI and DTI between the first field insulating layer DB and the gate line GLB. The gate isolation layer IG may be between the first portion DB1of the first field insulating layer DB and the gate line GLB, and may form a line with the first portion DB1, e.g., may overlap along the second direction. Further, the gate isolation layer IG may be between the second portion DB2of the first field insulating layer DB and the gate line GLB in a straight line along with the second portion DB2e.g., may overlap along the second direction. One side surface Sig1of the gate isolation layer IG may be in contact with the first portion DB1, and another side surface Sig2of the gate isolation layer IG may be in contact with the gate line GLB.

The side surface Sig1of the gate isolation layer IG may be in contact with the first portion DB1and the second portion DB2of the first field insulating layer DB. The side surface Sig2of the gate isolation layer IG may be in contact with a gate insulating layer116band a gate capping layer117b.

Gate spacers114may include the pairs of outer gate spacers114a,114b, and114cand pairs of gate inner gate spacers114a′,114b′, and114c′. The pairs of outer gate spacers114a,114b, and114cmay extend in the second direction over the first region P and the second region N. The pairs of outer gate spacers114a,114b, and114cmay include first outer gate spacers114a, second outer gate spacers114b, and third outer gate spacers114c. The first outer gate spacers114amay be cover both outer sidewalls, which may extend in the second direction, of the first field insulating layer DB. That is, the first outer gate spacers114amay cover outer sidewalls of the first portion DB1and outer sidewalls of the second portion DB2of the first field insulating layer DB. When viewed from above, e.g., in plan view, the first field insulating layer DB may be between the first outer gate spacers114a.

The second outer gates spacers114bmay cover outer sidewalls of the gate line GLB. The third outer gate spacers114cmay cover outer sidewalls of the gate isolation layer IG. The first outer gate spacers114amay be connected to the third outer gate spacers114c, and the second outer gate spacers114bmay be connected to the third outer gate spacers114cso that the first to third outer gate spacers114a,114b, and114cmay integrally form outer gate spacers.

The pairs of inner gate spacers114a′,114b′, and114c′ may extend in the second direction over the first region P and the second region N. The pairs of inner gate spacers114a′,114b′, and114c′ may include first inner gate spacers114a′, second inner gate spacers114b′, and third inner gate spacers114c′. The first inner gate spacers114amay cover inner side surfaces of the first field insulating layer DB. That is, the first inner gate spacers114amay cover an inner side surface of the first portion DB1and an inner side surface of the second portion DB2of the first field insulating layer DB, and the first portion DB1may be between the first outer gate spacer114aand the first inner gate spacer114a′. A top end of the first inner gate spacer114a′ may be in contact with the bottom surface of the third portion DB3of the first field insulating layer DB. The top end of the first inner gate spacer114a′ may be at a lower level than a top end of the first outer gate spacer114a.

The second inner gate spacers114b′ may cover inner sidewalls of the gate line GLB, and the gate line GLB may be between the second outer gate spacer114band the second inner gate spacer114b′. A top end of the second inner gate spacer114b′ may be at a higher level than the top end of the first inner gate spacer114a′.

The third inner gate spacers114c′ may cover inner sidewalls of the gate isolation layer IG, and the gate isolation layer IG may be between the third outer gate spacer114cand the third inner gate spacer114c′. A top end of the third inner gate spacer114c′ may be at the same level as top ends of the outer gate spacers114a,114b, and114c. The top end of the third inner gate spacer114c′ may be at the same level as the top end of the second inner gate spacer114b′. The first inner gate spacers114a′ may be connected to third inner gate spacers114c′, and the second inner gate spacers114b′ may be connected to the third inner gate spacers114c′ so that the first to third inner gate spacers114a′,114b′, and114c′ may integrally form inner gate spacers.

In an embodiment, one end of the third inner gate spacer114c′ may be in contact with a portion of a side surface of the first field insulating layer DB, which extends in the second direction. For example, the one end of the third inner gate spacer114c′ may be in contact with a portion of one side surface of the third portion DB3of the first field insulating layer DB.

Referring toFIG.2E, a semiconductor device100bmay include a first field insulating layer DB and a pair of outer gate spacers114ain a first region P. The first field insulating layer DB may include a first portion DB1, a second portion DB2, and a third portion DB3. In an embodiment, a level LV_DB3of a highest part of a bottom surface of the third portion DB3may be lower than or equal to a level LV_F of a top end of a first active fin F1. The first active fin F1and portions of the source and drain regions120may be between the first portion DB1and the second portion DB2and under the third portion DB3. As an example, the bottom surface of the third portion DB3may have a concave or inverted U shape.

The pair of outer gate spacers114amay be respectively on outer sidewalls of the first portion DB1and the second portion DB2. Unlike that which is shown inFIG.2C, a pair of inner gate spacers may be only on inner sidewalls of a gate isolation layer and a gate line, e.g., may not be on inner sidewalls of the first field insulating layer DB.

FIG.3Aschematically illustrates a layout of a partial region of a semiconductor device according to an embodiment.FIG.3Bshows vertical cross-sectional views taken along lines I-I′ and II-II′ ofFIG.3A.FIGS.3C and3Dshow vertical cross-sectional views taken along the line I-I′ ofFIG.3A, according to embodiments. Hereinafter, the same descriptions as inFIGS.1A to2Ewill be omitted for brevity.

Referring toFIGS.3A and3B, a semiconductor device100cmay include a first field insulating layer DB and a pair of inner gate spacers114dand114e. In an embodiment, the first field insulating layer DB may have a relatively large width in a first direction in a first region P. For instance, a width of a top surface of the first field insulating layer DB in the first direction may be at least twice of a width of a gate line GL. In an embodiment, a bottom surface of the first field insulating layer DB may have a curved shape. For example, a middle portion of the bottom surface of the first field insulating layer DB may have a concavely indented shape upward. Thus, the middle portion of the bottom surface of the first field insulating layer DB may be at a level LV_DB3higher than a level LV1of a lowermost end of the first field insulating layer DB. The bottom surface of the first field insulating layer DB may be formed by further extending the third portion DB3ofFIG.2Efurther downward.

The pair of inner gate spacers114dand114emay extend in the second direction in a second region N, and portions of the pair of inner gate spacers114dand114emay be in the first region P. The pair of inner gate spacers114dand114emay include a first inner gate spacer114dand a second inner gate spacer114e. The first inner gate spacer114dmay be in contact with an inner side surface of the gate line GLB in the second region N. The second inner gate spacer114emay be in contact with an inner side surface of the gate isolation layer IG in the first region P and the second region N. The first inner gate spacer114dmay be connected to the second inner gate spacer114eto integrally form a spacer. In an embodiment, one ends of the pair of inner gate spacers114dand114emay be in contact with a first side surface of the first field insulating layer DB. That is, a first end of the second inner gate spacer114emay be in contact with one side surface of the first field insulating layer DB.

Referring toFIG.3C, the bottom surface of the first field insulating layer DB may have a curved shape. For example, a middle portion of the bottom surface of the first field insulating layer DB may have a convexly protruding shape downward. Thus, the middle portion of the bottom surface of the first field insulating layer DB may be at the level LV_DB3lower than the level LV1of the lowermost end of the first field insulating layer DB.

Referring toFIG.3D, the bottom surface of the first field insulating layer DB may be a curved surface, e.g., a continuously convex surface having a base at the level LV_DB3, or may be a flat planar surface.

FIGS.4A to10Bare diagrams illustrating stages in a method of manufacturing a semiconductor device according to an embodiment. In particular,FIGS.4A,5A,6A,7A,8A, and9Aillustrate a layout of a partial region of a semiconductor device according to an embodiment.FIGS.4B,5B,6B,7B,8B,9B, and10Aillustrate vertical cross-sectional views taken along lines I-I′ and II-II′.FIGS.4C,5C,6C,7C,8C,9C, and10B illustrate vertical cross-sectional views taken along lines III-III′ and IV-IV′. InFIGS.1A to10B, like numbers refer to like elements. Hereinafter, the same descriptions as inFIGS.1A to3Dwill be omitted for brevity.

Referring toFIGS.4A to4C, a substrate101may be partially etched to form active regions AR1and AR2and active fins F1and F2. Along the second direction, widths of the active regions AR1and AR2and the active fins F1and F2may be gradually reduced upward, e.g., along the third direction away from the substrate101, while the widths of a bottom surface of the active fins F1and F2may be stepwise smaller than widths of an upper surface of the active regions AR1and AR2. An insulating film may be formed on the substrate101to cover the active regions AR1and AR2and the active fins F1and F2. The insulating film may then be partially removed to form device isolation layers STI and DTI. In an embodiment, an etchback process for partially removing the insulating film may be performed to leave the device isolation layers STI and DTI. After the device isolation layers STI and DTI are formed, the active fins F1and F2may protrude along the third direction from top surfaces of the device isolation layers STI and DTI to be exposed. As an example, the device isolation layers STI and DTI may be formed of silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or the like.

Thereafter, the device isolation layers STI and DTI, the active fins F1and F2, and the second active region AR2may be partially etched in the second region N, thereby forming a lower trench LT. The lower trench LT may be formed by performing an etching process using a mask layer that covers the device isolation layers STI and DTI and the first active fins F1in the first region P, and partially exposes the device isolation layers STI and DTI and the second active fins F2in the second region N. Thus, the lower trench LT is only in the second region N. The second field insulating layer IFR may be formed inside the lower trench LT. After the lower trench LT is filled with a second field insulating layer IFR, the mask layer may be removed.

A dummy gate structure DG may be formed on the active fins F1and F2and the device isolation layers STI and DTI and extend across the active fins F1and F2. A portion of the dummy gate structure DG may also extend across the second field insulating layer IFR in the second region N. For example, the dummy gate structure DG may extend to completely cover the second field insulating layer IFR along the second direction, while, along the first direction, the dummy gate structure DG may overlap a portion of the second field insulating layer IFR and the second active fins F2.

The dummy gate structure DG may include dummy gate lines111,112, and113, and gate spacers114. The dummy gate lines111,112, and113may include a dummy gate insulating layer111, a dummy gate electrode112, and a dummy gate capping layer113, which are sequentially stacked. The dummy gate insulating layer111may include silicon oxide and may be formed using a method such as a CVD process or an ALD process. The dummy gate electrode112may include polysilicon. The dummy gate capping layer113may be formed of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. The gate spacers114may be on both sidewalls of the dummy gate structure DG. That is, the gate spacers114may be on both sidewalls of the dummy gate insulating layer111, the dummy gate electrode112, and the dummy gate capping layer113. The gate spacers114may be formed of silicon nitride, silicon oxynitride, a combination thereof, or the like.

Referring toFIGS.5A to5C, source and drain regions120may be formed on the active fins F1and F2on both sides of the dummy gate structure DG. Exposed portions of the active fins F1and F2, which are not covered by the dummy gate structure DG, may be removed to form recesses. Thereafter, the source and drain regions120may be formed in the recesses by using an epitaxial growth process.

Subsequently, a first interlayer insulating layer130may be formed to cover the active fins F1and F2, the device isolation layers STI and DTI, the second field insulating layer IFR, and the dummy gate structure DG. A planarization process, e.g. a chemical mechanical polishing (CMP) process, an etchback process, or the like, may be performed so that a top surface of the first interlayer insulating layer130may be at the same level as a top surface of the dummy gate structure DG, e.g., along the third direction from the substrate101. A mask layer140may be formed to cover the planarized first interlayer insulating layer130and the planarized dummy gate structure DG. A portion of the mask layer140may be etched to form an open region OP1exposing top surfaces of at least two adjacent dummy gate structures DG, e.g., at a center of an interface of the first region P and the second region N. The open region OP1may extend in the first direction. The top surface of the first interlayer insulating layer130may also be exposed through the open region OP1.

An etching process may be performed using the mask layer140, the first interlayer insulating layer130, and the gate spacers114as etch masks. The dummy gate insulating layer111, the dummy gate electrode112, and the dummy gate capping layer113of which top surfaces are exposed by the open region OP1may be partially removed due to the etching process. Thus, adjacent dummy gate line111,112, and113exposed by the open region OP1may be separated into a first dummy gate line111a,112a, and113a, and a second dummy gate line111b,112b, and113b. The gate spacer114may be divided into a first gate spacer114ain contact with the first dummy gate line111a,112a, and113a, a second gate spacer114bin contact with the second dummy gate line111b,112b, and113b, and a third gate spacer114chaving inner side surfaces exposed between the first gate spacer114aand the second gate spacer114b. Further, the dummy gate structure DG, which is partially removed due to the etching process, may be divided into a first dummy gate structure DGa and a second dummy gate structure DGb. In particular, the first dummy gate structure DGa extends along the second direction from the open region OP1towards an outer edge of the first region P, while the second dummy gate structure DGb extends along the second direction from the open region OP1towards an outer edge of the second region N.

A gate recess region GR exposing a portion of the top surface of the device isolation layers STI and DTI may be formed between the third gate spacers114cin the first direction, and between the first dummy gate lines111a,112a, and113a, and the second dummy gate lines111b,112b, and113bin the second direction. A first side surface of the first dummy gate insulating layer111a, a first side surface of the first dummy gate electrode112a, and a first side surface of the first dummy gate capping layer113amay be exposed by the gate recess region GR. In addition, a second side surface of the second dummy gate insulating layer111b, a second side surface of the second dummy gate electrode112b, and a second side surface of the second dummy gate capping layer113bmay be exposed by the gate recess region GR. Furthermore, inner side surfaces of the third gate spacers114cmay be exposed by the gate recess region GR.

Referring toFIGS.6A to6C, the mask layer140may be removed to expose the top surface of the dummy gate structure DG, DGa, and DGb, and the top surface of the first interlayer insulating layer130. A gate isolation layer IG may be formed to fill the gate recess region GR. The formation of the gate isolations layer IG may include depositing an insulating material to such a sufficient thickness for filling the gate recess region GR to cover a top surface of the first interlayer insulating layer130, and etching back or planarizing the insulating material until the top surface of the first interlayer insulating layer130is exposed. In an embodiment, the gate isolation layer IG may be formed of silicon oxide, silicon nitride, air spaces, a combination thereof, or the like. The gate isolation layer IG may be in contact with the inner side surfaces of the third gate spacers114c, the first sidewalls of the first dummy gate line111a,112a, and113a, second sidewalls of the second dummy gate line111b,112b, and113b, and the top surfaces of the device isolation layers STI and DTI.

Referring toFIGS.7A to7C, the dummy gate lines111,112, and113may be removed to form dummy gate trenches GT. The first dummy gate lines111a,112a, and113amay be removed to form first dummy gate trenches GTa, and the second dummy gate lines111b,112b, and113bmay be removed to form second dummy gate trenches GTb. Inner side surfaces of the first gate spacers114a, inner side surfaces of the second gate spacers114b, upper portions of the active fins F1and F2, a portion of the top surfaces of the device isolation layers STI and DTI, and a part of an upper portion of the second field insulating layer IFR may be exposed by the dummy gate trench GTa and GTb. Further, both side surfaces of the gate isolation layer IG may be exposed by the dummy gate trench GTa and GTb.

Referring toFIGS.8A to8C, a gate line GL may be formed inside the dummy gate trench GT. The gate electrode115, the gate insulating layer116, and the gate capping layer117may fill the dummy gate trench GT and cover the first interlayer insulating layer130, and, then, an etchback process and a planarization process may be performed to expose top surfaces of the first interlayer insulating layer130, the gate spacers114and114c, and the gate isolation layer IG. Similarly, e.g., simultaneously, the gate electrode115a, the gate insulating layer116a, and the gate capping layer117amay fill the dummy gate trench GTa, and the gate electrode115b, the gate insulating layer116b, and the gate capping layer117bmay fill the dummy gate trench GTb, and, the gate spacers114aand114bmay be exposed. Thus, the first gate line GLa filling the first dummy gate trench GTa and the second gate line GLb filling the second dummy gate trench GTb may be formed with the gate isolation layer IG therebetween, e.g., along the second direction.

Referring toFIGS.9A to9C, an etching process may be performed using a mask layer145, the first gate spacer114a, and the first interlayer insulating layer130as etch masks to remove the first gate line GLa. The mask layer145may cover the first region P and the second region N, and may have an open region OP2in the first region P. A portion of the top surface of the first interlayer insulating layer130and top surfaces of the first gate line GLa and the first gate spacer114amay be exposed by the open region OP2.

The first gate electrode115a, the first gate insulating layer116a, and the first gate capping layer117aof the first gate line GLa may be removed to form a gate line trench GLT in the first region P. An upper portion of the first active fin F1, portions of the top surfaces of the device isolation layers STI and DTI, and a first side surface of the gate isolation layer IG may be exposed by the gate line trench GLT.

Referring toFIGS.10A and10B, upper portions of the first active fins F1exposed by the gate line trench GLT may be etched in the first region P to form fin recesses FR. That is, the fin recesses FR may be formed by extending portions of the gate line trench GLT downward. The fin recesses FR may be connected to the gate line trench GLT to integrally form a space. The device isolation layers STI and DTI in the first region P may be partially etched during the formation of the fin recesses FR so that the portions of the top surfaces of the device isolation layers STI and DTI exposed by the gate line trench GLT may be at a lower level than unexposed portions of the top surfaces of the device isolation layers STI and DTI. In an embodiment, during the formation of the fin recesses FR, the first interlayer insulating layer130, of which the top surface is exposed by the open region OP2, and a gate spacer114a′ may be partially etched by the open region OP2. Thereafter, as shown inFIG.2C, the first field insulating layer DB may fill the fin recesses FR and the gate line trench GLT.

Referring back toFIGS.10A and10B, a first interlayer insulating layer130′, the gate spacer114a′, source and drain regions120, and the first active fin F1may be etched through the open region OP2, thereby forming fin recesses having a large width and a gate line trench having a large width. Thereafter, as shown inFIGS.3B to3D, the first field insulating layer DB may be formed to fill the fin recesses having the large width and the gate line trench having the large width.

According to the example embodiments, a semiconductor device having different diffusion break regions, e.g., different structures and/or different types, in a PMOS region and an NMOS region can be provided to improve performance of each of the PMOS region and the NMOS region. Further, in a process of manufacturing the semiconductor device having different diffusion break regions in the PMOS region and the NMOS region, a gate line of the NMOS region can be prevented from being lost using a gate isolation layer so that the cause of deterioration of characteristics of a transistor can be fundamentally eliminated.

The example embodiments are directed to providing a semiconductor device, of which performance is improved by providing an optimized diffusion break region to each of a P-type metal-oxide-semiconductor (PMOS) region and an N-type MOS (NMOS) region.

In addition, the example embodiments are directed to providing a method of manufacturing a semiconductor device in which an optimized diffusion break region is provided to each of a PMOS region and an NMOS region so that problems caused in the vicinity of a gate line and a diffusion break region can be solved.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated.

Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.