Patent ID: 12243772

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

An interconnect structure interconnecting two stacked dies and the method of forming the same are provided in accordance with various embodiments. The intermediate stages of forming the interconnect structure are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS.1through12illustrate the cross-sectional views of intermediate stages in the formation of stacked wafers (and the corresponding stacked dies) in accordance with some embodiments of the present disclosure. The steps shown inFIGS.1through12are also reflected schematically in the process flow300shown inFIG.15.

FIG.1illustrates the cross-sectional view in the formation of wafer110. The respective process is illustrated as process302in the process flow shown inFIG.15. In accordance with some embodiments of the present disclosure, wafer no is a device wafer including active devices122such as transistors and/or diodes, and possibly passive devices such as capacitors, inductors, resistors, or the like. Wafer no may include a plurality of identical chips124therein, with one of chips124illustrated. Chips124are alternatively referred to as (device) dies hereinafter. The subsequent discussion of the wafers thus also applies to the corresponding device dies. In accordance with some embodiments of the present disclosure, wafer no is an image sensor wafer, which may further be a backside illuminated image sensor wafer, and active devices122may include image sensors, which may be photo diodes, for example. In accordance with some embodiments of the present disclosure, some of integrated circuit devices122are formed on the top surface of semiconductor substrate120. The details of integrated circuit devices122are not illustrated herein. In accordance with alternative embodiments of the present disclosure, wafer no includes passive device dies and is free from active devices.

In accordance with some embodiments of the present disclosure, wafer no includes logic devices and circuits therein, which may include Application Specific Integrated Circuit (ASIC) circuits. In accordance with alternative embodiments of the present disclosure, wafer110is a logic wafer, which may include Central Processing Unit (CPU) dies, Micro Control Unit (MCU) dies, input-output (IO) dies, BaseBand (BB) dies, Application processor (AP) dies, or the like. Wafer no may also include memory dies such as Dynamic Random Access Memory (DRAM) dies or Static Random Access Memory (SRAM) dies.

In accordance with some embodiments of the present disclosure, wafer no includes semiconductor substrate120and the features (such as transistors) formed at a top surface of semiconductor substrate120. Semiconductor substrate120may be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, and/or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and the like. Semiconductor substrate120may also be a bulk silicon substrate or a Semiconductor-On-Insulator (SOI) substrate. Shallow Trench Isolation (STI) regions (not shown) may be formed in semiconductor substrate120to isolate the active regions in semiconductor substrate120. Although not shown, through-vias may be formed to extend into semiconductor substrate120, and the through-vias are used to electrically inter-couple the features on opposite sides of wafer110.

Inter-Layer Dielectric (ILD)126is formed over semiconductor substrate120, and fills the space between the gate stacks of transistors (not shown) in integrated circuit devices122. In accordance with some embodiments of the present disclosure, ILD126is formed of Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-Doped Phospho Silicate Glass (BPSG), Fluorine-Doped Silicate Glass (FSG), Tetra Ethyl Ortho Silicate (TEOS), or the like. ILD126may be formed using spin coating, Flowable Chemical Vapor Deposition (FCVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), or the like. Although not shown, a Contact Etch Stop Layer (CESL) may be formed between ILD126and integrated circuit devices122, with contact plugs128penetrating through the CESL.

Contact plugs128are formed in ILD126, and are used to electrically connect integrated circuit devices122to overlying metal lines134and vias136. In accordance with some embodiments of the present disclosure, contact plugs128are formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys therefore, and/or multi-layers thereof. The formation of contact plugs128may include forming contact openings in ILD126(and the underlying CESL), filling a conductive material(s) into the contact openings, and performing a planarization process (such as a Chemical Mechanical Polish (CMP) process) to level the top surfaces of contact plugs128with the top surface of ILD126.

Over ILD126and contact plugs128resides interconnect structure130. Interconnect structure130includes dielectric layers132, and metal lines134and vias136formed in dielectric layers132. Dielectric layers132are sometimes referred to as Inter-Metal Dielectric (IMD) layers132hereinafter. In accordance with some embodiments of the present disclosure, some of the lower dielectric layers132are formed of a low-k dielectric material having a dielectric constant (k-value) lower than about 3.0 or about 2.5. Dielectric layers132may be formed of Black Diamond (a registered trademark of Applied Materials), a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In accordance with alternative embodiments of the present disclosure, some or all of dielectric layers132are formed of non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbo-nitride (SiCN), silicon oxy-carbo-nitride (SiOCN), or the like. In accordance with some embodiments of the present disclosure, the formation of dielectric layers132includes depositing a porogen-containing dielectric material, and then performing a curing process to drive out the porogen, and hence the remaining dielectric layers132become porous. Etch stop layers133, which may be formed of silicon carbide, silicon nitride, or the like, are formed between IMD layers132.

Metal lines134and vias136are formed in dielectric layers132and etch stop layers133. The metal lines134at a same level are collectively referred to as a metal layer hereinafter. In accordance with some embodiments of the present disclosure, interconnect structure130includes a plurality of metal layers that are interconnected through vias136. Metal lines134and vias136may be formed of copper or copper alloys, and can also be formed of other metals. The formation process may include single damascene and dual damascene processes. In a single damascene process, a trench is first formed in one of dielectric layers132, followed by filling the trench with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portions of the conductive material higher than the top surface of the IMD layer, leaving a metal line in the trench. In a dual damascene process, both a trench and a via opening are formed in an IMD layer, with the via opening underlying and connected to the trench. The conductive material is then filled into both the trench and the via opening to form a metal line and a via, respectively. The conductive material may include a diffusion barrier and a copper-containing metallic material over the diffusion barrier. The diffusion barrier may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

Metal lines134include metal lines134A, which are sometimes referred to as top metal lines. Top metal lines134A are also collectively referred to as being a top metal layer. The respective dielectric layer132A may be formed of a non-low-k dielectric material such as Undoped Silicate Glass (USG), silicon oxide, silicon nitride, or the like. Dielectric layer132A may also be formed of a low-k dielectric material, which may be selected from the similar materials of the underlying IMD layers132.

In accordance with some embodiments of the present disclosure, passivation layer138is formed over the top metal layer. Passivation layer138is a surface dielectric layer of wafer no. Passivation layer138is formed of a non-low-k dielectric material, which has the function of blocking moisture and detrimental chemicals from reaching devices122and interconnect structure130. Furthermore, passivation layer138may be formed of a material that can be used for fusion bonding, and may include silicon oxide. In accordance with some embodiments of the present disclosure, no etch stop layer is formed between top metal layer134and passivation layer138. Accordingly, the bottom surface of passivation layer138is in direct contact with the top surfaces of metal lines134A. Passivation layer138may be formed of a homogenous material, with all portions of the passivation layer138formed of the same material such as silicon oxide.

Wafer no (die124) includes a plurality of metal pipes140, with one metal pipe140illustrated. Metal pipes140may be formed of metals and metal alloys such as copper, titanium, aluminum, aluminum copper (AlCu), tantalum, tungsten, or the like. In accordance with some embodiments, each of metal pipes140includes a diffusion barrier and a metallic material on the diffusion barrier. The diffusion barrier may be formed of titanium, tantalum, titanium nitride, tantalum nitride, or the like. The metallic material may be copper, aluminum, or the like.FIG.1schematically illustrates diffusion barrier layers35and the metallic material in some of the metal pipes140, while other metal pipes and metal lines and vias may have similar structures. Metal pipe140includes a plurality of metal-line portions134B-1,134B-2,134B-3, and134B-4, as shown in the illustrated example, with each being in one of the metal-line layers. That is, the metal-line portion (such as134B-1,134B-2,134B-3,134B-4) and one of the metal lines134are in the same level. Metal pipe140further includes a plurality of via portions136B-1,136B-2, and136B-3as shown in the illustrated example, with each being in one of the metal-via layers. That is, the via portion (such as136B-1,136B-2,136B-3) and one of the vias136are in the same level. The metal-line portions134B-1,134B-2,134B-3, and134B-4and the via portions136B-1,136B-2, and136B-3are alternately arranged. It is appreciated that wafer no may include more or fewer metal layers and via layers than illustrated. Accordingly, the total number of the via portions and metal line portions in a metal pipe140will vary correspondingly. Metal pipe140is formed in the same processes as the formation of the metal lines134and vias136in the same metal layer. Each of the metal-line portions134B-1,134B-2,134B-3, and134B-4and each of the via portions136B-1,136B-2, and136B-3may be a solid ring. The resulting metal pipe140is also a solid metal pipe. Metal pipe140is electrically coupled to active devices122through some metal lines134and vias136, as illustrated in accordance with some embodiments.

Metal pipe140encircle dielectric region142therein, and dielectric region142includes the portions of dielectric layers132encircled by metal pipe140. In accordance with some embodiments of the present disclosure, dielectric region142has gradually increased lateral dimensions, which may be diameters, from the top of dielectric region142to the bottom of dielectric region142. For example, in the illustrated embodiments, each of the dielectric portions encircled by a corresponding via portion of metal pipe140has a greater lateral dimension than the dielectric portion encircled by the corresponding overlying metal-line portion of metal pipe140. Each of the dielectric portion encircled by the corresponding metal-line portion of metal pipe140also has a greater lateral dimension than the dielectric portion encircled by the corresponding overlying via portion. Accordingly, the sidewalls and top surfaces of dielectric region142form a plurality of steps. Alternatively stated, in each of the dual damascene structures of metal pipe140, the inner sidewalls of the via portion of metal pipe140are recessed relative to the inner sidewalls of the respective overlying metal-line portion. The inner sidewalls of the via portions and metal-line portions are the sidewalls contacting the sidewalls of dielectric region142.

In accordance with alternative embodiments of the present disclosure, in each (or some but not all) of the dual damascene structures of metal pipe140, the inner sidewalls of the via portion136B-1/136B-2/136B-3of metal pipe140are flush with the inner sidewalls of the respective overlying metal-line portion134B-2/134B-3/134B-4. Alternatively stated, each of the via portions of metal pipe140may have an inner sidewall flush with the inner sidewall of the overlying metal line portion in the same dual damascene structure. For example, via portion136B-1and metal-line portion134B-2are in the same dual damascene structure, and may have inner sidewalls flush with each other. Via portion136B-2and metal-line portion134B-3are in the same dual damascene structure, and may have inner sidewalls flush with each other. Via portion136B-3and metal-line portion134B-4are in the same dual damascene structure, and may have inner sidewalls flush with each other. Accordingly, the corresponding dielectric region142has fewer steps than illustrated since no step is formed inside some dual damascene structures. Rather, the steps are formed between dual damascene structures.

In accordance with some embodiments of the present disclosure, the outer sidewall of metal pipe140is substantially straight and vertical. This means that the outer sidewalls of the via portions and metal-line portions of metal pipe140are flush with each other. In accordance with some embodiments of the present disclosure, the outer sidewalls of the via portions and metal-line portions of metal pipe140are not flush with each other. For example, when metal-line portions134B-1,134B-2,134B-3, and134B-4and via portions136B-1,136B-2, and136B-3have a same thickness (measured in a horizontal direction), the outer sidewalls of lower ones of the via portions and metal-line portions are farther away from the center line141of metal pipe140than outer sidewalls of the corresponding upper ones of the via portions and metal-line portions. Alternatively stated, the outer sidewalls of the via portions and metal line portions of metal pipe140also form a plurality of steps.

FIG.13Aillustrates the bottom view of a first dual damascene structure formed of via portion136B-3and metal line portion134B-4(FIG.1) having inner sidewalls136B-3′ and134B-4′, respectively. The diameters of inner sidewalls134B-4′ and136B-3′ are D1and D2, respectively, with diameter D2being greater than (or equal to) diameter D1.FIG.13Billustrates the bottom view of a second dual damascene structure formed of via portion136B-2and metal line portion134B-3(FIG.1) having inner sidewalls136B-2′ and134B-3′, respectively. The diameters of inner sidewalls134B-3′ and136B-2′ are D3and D4, respectively, with diameter D4being greater than (or equal to) diameter D3, which is further greater than D2.FIG.13Cillustrates the bottom view of a third dual damascene structure formed of via portion136B-1and metal-line portion134B-2(FIG.1), which have inner sidewalls136B-1′ and134B-2′, respectively. The diameters of inner sidewalls134B-2′ and136B-1′ are D5and D6, respectively, with diameter D6being greater than (or equal to) D5, which is further greater than diameter D4. Metal-line portion134B-1(FIG.1) may have a similar bottom-view shape as metal-line portion134B-2(FIG.13C), with the diameter of the inner sidewall being greater than D6.

Throughout the description, dimensions D1through D7are referred to as inner lateral dimensions of metal pipe140. In accordance with some embodiments of the present disclosure, as illustrated inFIGS.13A,13B, and13C, the relationship may exist that D7>D6≥D5>D4≥D3>D2≥D1.

In the examples as shown inFIGS.13A,13B, and13C, the inner sidewalls and outer sidewalls of the dual damascene structures have circular bottom-view shapes. It is appreciated that the bottom views of the inner sidewalls and the outer sidewalls of the dual damascene structures (and single-damascene structures) may adopt shapes other than circles, which may include, and not limited to, squares, hexagons, rectangles, ellipse, or the like. For example,FIG.14Aillustrates a metal portion in metal pipe140having an inner sidewall having a bottom-view shape of a square, and an outer sidewall having a bottom-view shape of a circle.FIG.14Billustrates a metal portion having inner sidewalls having a bottom-view shape of a circle, and an outer sidewall having a bottom-view shape of a square.

FIG.2illustrates the cross-sectional view in the formation of wafer210. In accordance with some embodiments of the present disclosure, wafer210is a device wafer including active devices222such as transistors and/or diodes, and possibly passive devices such as capacitors, inductors, resistors, or the like. Wafer210may include a plurality of identical chips/dies224therein, with the details of one of chips224illustrated. In accordance with some embodiments of the present disclosure, device die224is a logic die, which may be an ASIC die including ASIC circuits therein. In accordance with some embodiments of the present disclosure, device die224is a logic die, which may be a CPU die, a MCU die, an IO die, a BB die, an AP die, or the like. Device die224may also be a memory die such as a DRAM die or a SRAM die. In accordance with alternative embodiments of the present disclosure, wafer210includes passive devices (with no active devices therein).

In accordance with some embodiments of the present disclosure, wafer210includes semiconductor substrate220and the features (such as transistors) formed at a top surface of semiconductor substrate220. Semiconductor substrate220may be formed of a material selected from the same group of candidate materials for forming semiconductor substrate120(FIG.1), and may have a structure selected from the same group of candidate structures of semiconductor substrate120. Although not shown, through-vias may be formed to extend into semiconductor substrate220, and the through-vias are used to electrically inter-couple the features on opposite sides of wafer210.

ILD226is formed over semiconductor substrate220, and fills the space between the gate stacks of transistors (not shown) in integrated circuit devices222. In accordance with some embodiments of the present disclosure, ILD226is formed of a material selected from the same group of candidate materials of ILD126(FIG.1). ILD226may also be formed using spin coating, FCVD, CVD, PECVD, LPCVD, or the like.

Contact plugs228are formed in ILD226. Over ILD226and contact plugs228resides interconnect structure230. Interconnect structure230includes dielectric layers232, and metal lines234and vias236formed in dielectric layers232. Dielectric layers232are alternatively referred to as IMD layers232hereinafter. Etch stop layers233may also be formed. In accordance with some embodiments of the present disclosure, some of dielectric layers232are formed of a low-k dielectric material(s) having a dielectric constant (k-value) lower than about 3.0 or about 2.5. In accordance with alternative embodiments of the present disclosure, some or all of dielectric layers232are formed of non-low-k dielectric materials such as silicon oxide, silicon carbide, silicon carbo-nitride, silicon oxy-carbo-nitride, or the like.

Metal lines234and vias236are formed in dielectric layers232and etch stop layers233. In accordance with some embodiments of the present disclosure, interconnect structure230includes a plurality of metal layers that are interconnected through vias236. Metal lines234and vias236may be formed of copper or copper alloys, and can also be formed of other metals. The formation process may include single damascene and dual damascene processes. Metal lines234include metal lines234A, which are sometimes referred to as top metal lines. One of the top metal lines is illustrated, and is referred to as metal pad234A hereinafter. The other metal lines in the same layer as metal pad234A are not illustrated, and may also exist. The respective dielectric layer232A may be formed of a non-low-k dielectric material such as USG, silicon oxide, silicon nitride, or the like, or may be formed of a low-k dielectric material.

In accordance with some embodiments of the present disclosure, passivation layer238is formed over the top metal layer. Passivation layer238is a surface dielectric layer of wafer210. Passivation layer238may be formed of a non-low-k dielectric material, which has the function of blocking moisture and detrimental chemicals from reaching the devices222and interconnect structure230. Furthermore, passivation layer238may be formed of a material that can be used for fusion bonding, and may include silicon oxide. In accordance with some embodiments of the present disclosure, etch stop layer239is formed between top metal layer234and passivation layer238. Etch stop layer239is formed of a material different from the material of passivation layer238. The material of etch stop layer239may be selected from copper oxide, hafnium oxide, aluminum oxide, tungsten oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxy-carbo-nitride, or the like.

As shown inFIG.3, semiconductor wafer no is bonded to semiconductor wafer210. The respective process is illustrated as process304in the process flow shown inFIG.15. Semiconductor wafer no and semiconductor wafer210are bonded together through suitable bonding techniques such as direct bonding, which may include oxide-to-oxide bonding (also referred to as fusion bonding), for example. In accordance with some embodiments of the present disclosure, in a direct bonding process, passivation layers138and238are oxide layers (for example, formed of silicon oxide), which are bonded to each other through fusion bonding, with Si—O—Si bonds formed, for example.

FIG.3further illustrates a cross-sectional view of the semiconductor device shown inFIG.3after one or more dielectric layer is formed on the stacked wafers. The respective process is illustrated as process306in the process flow shown inFIG.15. In accordance with some embodiments of the present disclosure, the dielectric layers include pad oxide layer22and hard mask layer24over pad oxide layer22. Pad oxide layer22may be formed of silicon oxide, and hard mask layer24may be formed of silicon nitride. The dielectric layer(s) may also act as a Bottom Anti-Reflection Coating (BARC) layer. Layers22may be formed using, for example, thermal oxidation, with a top surface layer of substrate120being oxidized. Layer24may be formed using a deposition method such as Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), or the like. Layers22and24may also be formed of other dielectric materials.

Next, a patterned mask such as a photo resist (not shown) is formed over dielectric layers22and24using suitable deposition and photolithography techniques. A suitable etching process, such as a Reactive Ion Etch (RIE) process or other dry etch process may be performed on substrate120of semiconductor wafer110and dielectric layers22and24. As a result, as shown inFIG.4, opening26is formed in dielectric layers22and24and substrate120. The respective process is illustrated as process308in the process flow shown inFIG.15. Opening26penetrates through semiconductor substrate120, and stops on an underlying dielectric layer. For example, opening26may be stopped on the top surface of a Contact Etch Stop Layer (CESL, not shown), which is formed over ILD126, with the top surface of the CESL exposed to opening26. In accordance with alternative embodiments of the present disclosure, opening26penetrates through the CESL and stops on the top of ILD126, with the top surface of ILD126exposed to opening26. In accordance with alternative embodiments of the present disclosure, opening26may penetrate through ILD126and stop on a top surface of an underlying dielectric layer.

Referring toFIG.5, dielectric layer28is deposited. The respective process is illustrated as process310in the process flow shown inFIG.15. Dielectric layer28may be formed at the bottom and on the sidewalls of opening26. In addition, dielectric layer28has a portion overlapping dielectric layers22and24. Dielectric layer28may be formed of various dielectric materials that can be used in integrated circuit fabrication. For example, dielectric layer28may be formed of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, or the like. In addition, a combination of the aforementioned dielectric materials may also be used to form dielectric layer28. In accordance with some embodiments of the present disclosure, dielectric layer28is formed using a conformal deposition method such as CVD or ALD, and hence dielectric layer28is a conformal layer, for example, with different parts of dielectric layer28having thickness variation being smaller than about 20 percent.

Referring toFIG.6, patterned mask layer30is formed. Patterned mask30may extend into opening26, so that the portions of dielectric layer28on the sidewalls of substrate120are protected. In accordance with some embodiments of the present disclosure, patterned mask30is a photo resist.

Referring toFIG.7, patterned mask30is used as an etching mask to etch the underlying portions of wafers110and210. The respective process is illustrated as process312in the process flow shown inFIG.15. The etching is anisotropic, and may be performed using dry etching. Since the underlying etched structure includes different materials, the etching may also include a plurality of etching processes using different etching gases. As a result, opening32is formed as an extension of opening26. With the proceeding of the etching process, the inner surfaces of metal pipe140are exposed. The etching gases are selected so that the exposed portions of metal pipe140are not etched, while dielectric region142(FIG.6) is etched. For example, the etching gas may include a mixed gas of NF3and NH3, or a mixed gas of HF and NH3, depending on the material of the etched portions.

In the etching of dielectric region142as shown inFIG.6, although metal pipe140is not intended to be etched, since the etching selectivity between the etching rates of dielectric region142and metal pipe140is not infinite, the corners of the exposed metal pipe140may be rounded. Overall, the inner sidewalls of metal pipe140facing opening32will have a slanted profile, with the inner sidewalls being slanted with a plurality of ripples. Accordingly, the sidewalls of each of the metal-line portions134B-1,134B-2,134B-3, and134B-4and via portions136B-1,136B-2, and136B-3may have continuously slanted sidewalls from top to bottom.

After the removal of dielectric region142, the underlying portions of passivation layers138and238are etched, and opening32extends to the top surface of etch stop layer239. In accordance with some embodiments of the present disclosure, etch stop layer239is used to determine when the etching should be stopped. The determination is performed by detecting the presentation of the elements in etch stop layer239, and the finding of the elements (such as nitrogen, if the overlying passivation layers138and238do not include nitride) in etch stop layer239indicates that etch stop layer239has been exposed. Upon the exposure of etch stop layer239, the etching of the regions above etch stop layer239is stopped. By forming etch stop layer239in wafer210, the process is better controlled, and no excess etching is needed. For example, the etching rates of the edge portions and center portions of wafers110/210are different. To ensure the etching is stopped after the exposure of all metal pads234A in wafer210, the etching time is prolonged. The prolonged etching causes damage to the exposed joint between passivation layers138and238, and voids may be generated to extend into the interface. These voids cause difficulty in the subsequent filling of openings26and32with metal, and may cause voids in the resulting conductive plug. The formation of the etch stop layer239improves the process control, and results in the desirable reduction in the over-etching. As a comparison, wafer no may not include an etch stop layer between passivation layer138and the top metal134A.

In accordance with some embodiments, the portion of opening32in passivation layers138and238are made steep. For example, when passivation layers138and238are formed of silicon oxide, in the etching of passivation layers138and238, a fluorine-containing etching gas such as CF4, C4F8, CHF3, or the like, or combinations thereof may be used as the etching gas. Oxygen (O2) may be added. The adoption of carbon-and-fluorine-containing etching gas results in the formation of polymer, which covers the sidewalls of the formed opening in passivation layers138and238. The amount of the polymer affects how vertical the sidewall of the opening is, and with a proper thickness of the polymer, the opening in passivation layers138and238may be substantially vertical. The thickness of the polymer may be adjusted by adjusting the flow rate of oxygen, and with more oxygen provided, the polymer is thinner, and vice versa. In accordance with some embodiments of the present disclosure, the tilt angle α is greater than about 85 degrees, and may be in the range between about 85 degrees and about 90 degrees, or in the range between about 88 degrees and about 90 degrees.

FIG.8illustrates the etching of etch stop layer239, hence exposing metal pad234A. The respective process is illustrated as process314in the process flow shown inFIG.15. The process conditions for etching passivation layers138and238are different from the process conditions for etching etch stop layer239. For example, the etching gas for etching passivation layers138and238may be different from the etching gas used for etching etch stop layer239.

Next, referring toFIG.9, protection layer36is formed. The respective process is illustrated as process316in the process flow shown inFIG.15. Protection layer36extends to the bottom and the sidewalls of openings26and32, and may extend on dielectric layer28. Protection layer36is formed of a dielectric material, which may be selected from silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, or the like. In addition, a combination of the aforementioned dielectric materials may also be used to form protection layer36. In accordance with some embodiments of the present disclosure, protection layer36is formed using a conformal deposition method such as ALD or CVD. Accordingly, the thickness of protection layer36is uniform or substantially uniform, for example, with different parts having thickness variations smaller than about 20 percent. The thickness of protection layer36may be in the range between about 30 Å and about 300 Å. Dielectric layer28and protection layer36may be formed of the same dielectric material, or different dielectric materials.

Referring toFIG.10, an anisotropic etching is performed to etch protection layer36, wherein the etching is shown by arrows37. The anisotropic etching may be performed without forming an etching mask. Accordingly, an entirety of the opening as shown inFIG.10may be exposed to the etching. The respective process is illustrated as process318in the process flow shown inFIG.15. The etching may include a dry etching process. In the etching, the horizontal portions of protection layer36are removed, and the horizontal portions include the portions on the top of dielectric layers22and24, and the portion at the bottom of opening32. Due to the formation of the steps of metal pipe140, the inner sidewalls of metal pipe140overall have a slanted profile. Furthermore, the corners of the exposed metal pipe140are rounded and the inner sidewalls of metal pipe140may be slant. This makes the removal of some vertical portions of dielectric protection layer36easy. In accordance with some embodiments, there is no remaining portion of the protection layer36in contact with the sidewalls of metal pipe140. Alternatively stated, the portions of dielectric protection layer36on the sidewalls of metal pipe140are removed. Also, there may not be any remaining portion of the protection layer36at the same level as metal pipe140, such as at the corners of the steps.

Due to the vertical profile of the portion of opening32in passivation layers138and238, and further because the portions of protection layer36on the sidewalls of passivation layers138and238are deep inside opening32, the portions of protection layer36on the sidewalls of passivation layers138and238and etch stop layer239have at least some portions, and possibly majority portions, remaining. Protection layer36may have some portions left in opening26(at the same level as substrate120), which portions may be thinned. The portion of protection layer36at the same level as substrate120may also be removed during the anisotropic etching. However, since dielectric layer24protects the sidewalls of substrate120, the thickness of the remaining portion of protect layer36in opening26may be greater or smaller without affecting the performance of the resulting structure. Since substrate120and passivation layers138and238are thicker than each layer of the via portions and metal line portions of metal pipe140, further because the sidewalls of passivation layers138and238are made to be substantially vertical, protection layer36may be removed from metal pipe140, but may remain on the sidewalls of passivation layers138and238. Protection layer36thus protects the interface between passivation layers138and238, which is the bonded interface. Also, the interface may be damaged in the preceding formation of opening32, causing voids extending into the interface. Protection layer36has the function of filling the voids at least partially. The remaining portions of protection layer36form two rings, one at the level of semiconductor substrate120, and the other one at the level of passivation layers138and238.

Conductive materials are then filled into openings26and32in accordance with some embodiments of the present disclosure. The resulting structure is shown inFIG.11. In accordance with some embodiments of the present disclosure, conductive barrier layer38is deposited lining the sidewalls and the bottoms of openings26and32. The formation of the protection layer36on the sidewalls of passivation layers138and238improves the adhesion of conductive barrier layer38. The respective process is illustrated as process320in the process flow shown inFIG.15. Conductive barrier layer38may be formed of titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, or composite layers thereof. In accordance with some embodiments of the present disclosure, conductive barrier layer38has a substantially uniform thickness. Conductive barrier layer38may be formed using a conformal deposition method such as ALD or CVD.

In addition, a seed layer (a part of conductive material40, not shown separately) may be deposited over conductive barrier layer38. The seed layer may be formed of copper or a copper alloy. The seed layer may be formed by a suitable deposition technique such as PVD. Once conductive barrier layer38and the seed layer have been deposited, conductive material40is filled into the remaining openings26and32. The respective process is illustrated as process322in the process flow shown inFIG.15. Conductive material40may also be formed of copper or a copper alloy. In accordance with some embodiments of the present disclosure, conductive material40is filled in the openings through an electroplating process.

After the filling of conductive material, a planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process is performed to remove excess portions of conductive material40and conductive barrier layer38. The respective process is illustrated as process324in the process flow shown inFIG.15. The resulting structure is shown inFIG.11. During the planarization, the horizontal portions of protection layer36may be used as a CMP stop layer. In accordance with some embodiments of the present disclosure, the horizontal portions of dielectric layer24or22may be used as the CMP stop layer, and the overlying portions of dielectric layers are removed. As shown inFIG.11, conductive plug42is formed, and includes the remaining portions of conductive barrier layer38and conductive material40. Conductive plug42is electrically connected to metal pipe140, which is further connected to active devices122in wafer no. Furthermore, conductive plug42is electrically connected to metal pad234A, which is further connected to active devices222in wafer210. Accordingly, conductive plug42acts as an interconnection for electrically coupling/connecting to active devices122and222. It is appreciated that protection layer36includes a first portion in semiconductor substrate120, and a second portion in passivation layers138and238. Each of the first portion and the second portion of protection layer36forms a full ring encircling conductive plug42.

Referring toFIG.12, dielectric layer44is formed. Dielectric layer44is formed of a dielectric material, which may be selected from silicon nitride, silicon oxynitride, silicon oxy-carbide, silicon carbide, combinations thereof, and multi-layers thereof. Dielectric layer44may be deposited through suitable deposition techniques such as a CVD method, ALD, PECVD, etc.. In subsequent steps, the bonded wafers110and210are sawed into a plurality of packages46along scribe lines48, with each of the packages including device die124and device die224. In accordance with some embodiment in which device die124is a backside illumination image sensor, light may be projected from the top of device die124onto the image sensors in device die124.

It should be noted that whileFIG.11illustrates two semiconductor wafers stacked together, one skilled in the art will recognize that the stacked semiconductor device shown inFIG.12is merely an example. There may be many alternatives, variations, and modifications. For example, the stacked semiconductor device may accommodate more than two semiconductor wafers.

In above-illustrated embodiments, some processes and features are discussed in accordance with some embodiments of the present disclosure. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

The embodiments of the present disclosure have some advantageous features. By forming the protection layer, the bonded interface between two wafers is protected, and the corresponding voids are filled. The subsequently formed conductive plug is less likely to have voids. Furthermore, the formation of the etch stop layer between the passivation layer and the top metal pad further reduces the damage to the interface.

In accordance with some embodiments of the present disclosure, a method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening. In an embodiment, the method further comprises after the metal pad in the second wafer is revealed, depositing a dielectric protection layer extending into the opening; and performing an anisotropic etch to remove portions of the dielectric protection layer in the metal pipe. In an embodiment, after the anisotropic etch, the dielectric protection layer has a sidewall portion left to cover sidewalls of a first surface dielectric layer in the first wafer and a second surface dielectric layer in the second wafer, wherein the first surface dielectric layer is bonded to the second surface dielectric layer. In an embodiment, the method further comprises forming the metal pipe, wherein the dielectric region in the metal pipe has gradually reduced lateral dimensions from a top surface of the dielectric region to a bottom surface of the dielectric region. In an embodiment, the metal pipe comprises a plurality of metal line portions, each in one of the plurality of dielectric layers; and a plurality of via portions interpolated with the plurality of metal line portions, wherein the plurality of metal line portions and the plurality of via portions form a plurality of rings, and each of the plurality of rings has an inner lateral dimension equal to or greater than inner lateral dimensions of all respective lower rings. In an embodiment, each of the plurality of rings has a lateral dimension greater than inner lateral dimensions of all respective lower rings. In an embodiment, the second wafer comprises an etch stop layer over and contacting the metal pad, and the extending the opening into the second wafer comprises etching a dielectric layer over the etch stop layer, and the etching stops on the etch stop layer; and etching through the etch stop layer, wherein the dielectric layer and the etch stop layer are etched using different etching gases.

In accordance with some embodiments of the present disclosure, a method comprises forming a first wafer comprising forming a plurality of dielectric layers; and forming a metal pipe penetrating through the plurality of dielectric layers, with portions of the plurality of dielectric layers encircled by the metal pipe forming a dielectric region; forming a second wafer comprising forming a metal pad; and forming an etch stop layer over and contacting the metal pad; bonding the first wafer to the second wafer, wherein the metal pipe overlaps the metal pad; etching the first wafer and the second wafer to form an opening, wherein the dielectric region is removed in the etching to leave an opening, and the etching is stopped on a top surface of the etch stop layer; etching the etch stop layer; and forming a conductive plug in the opening. In an embodiment, the etching the first wafer and the second wafer comprises etching a dielectric layer over and contacting the etch stop layer using an etching gas different from an etching gas for etching the etch stop layer. In an embodiment, the forming the metal pipe comprises forming a plurality of metal-line portions and a plurality of via portions having different inner lateral dimensions. In an embodiment, the metal pipe comprises a first surface facing toward a semiconductor substrate in the first wafer; and a second surface facing away from the semiconductor substrate, and in a direction from the first surface to the second surface, the inner lateral dimensions of the metal pipe continuously reduce. In an embodiment, each of the plurality of metal-line portions has an inner lateral dimension different from inner lateral dimensions of immediate overlying and underlying metal via portions. In an embodiment, the etching the first wafer comprises etching-through a semiconductor substrate of the first wafer to form a through-opening; forming a dielectric liner lining the through-opening; and etching the dielectric liner and portions of the first wafer underlying a bottom portion of the dielectric liner. In and embodiment, the method further comprises, after the etching the etch stop layer and before the forming the conductive plug, forming a dielectric protection layer; and removing portions of the dielectric protection layer on inner sidewalls of the metal pipe, wherein the dielectric protection layer comprises an upper portion on a sidewall of a semiconductor substrate of the first wafer and a lower portion extending from the first wafer into the second wafer.

In accordance with some embodiments of the present disclosure, a structure comprises a first die comprising a first semiconductor substrate; a plurality of dielectric layers underlying the first semiconductor substrate; a plurality of metal rings, each in one of the plurality of dielectric layers, wherein inner lateral dimensions of the plurality of metal rings are different from each other, and wherein the plurality of metal rings are stacked to form a metal pipe; and a first surface dielectric layer underlying the plurality of metal rings and the plurality of dielectric layers; a second die comprising a second semiconductor substrate; a metal pad over the second semiconductor substrate; a second surface dielectric layer overlying the metal pad, wherein the first surface dielectric layer is bonded to the second surface dielectric layer; and a conductive plug penetrating through the first die to contact a top surface of the metal pad. In and embodiment, the structure further comprises a dielectric protection layer comprising a first portion encircling the conductive plug, wherein the first portion of the dielectric protection layer contacts sidewalls of the first surface dielectric layer and the second surface dielectric layer. In and embodiment, the dielectric protection layer further comprises a second portion encircling the conductive plug, wherein the second portion of the dielectric protection layer contacts sidewalls of the first semiconductor substrate. In and embodiment, the conductive plug has a portion in the metal pipe, and from a top to a bottom of the portion of the conductive plug, the, inner lateral diameters of the portion of the conductive plug gradually decrease. In and embodiment, the plurality of metal rings comprise a plurality of damascene structures, with each having a metal-line portion and a via portion overlying the metal-line portion, and the via portion has a first inner lateral dimension smaller than a second inner lateral dimension of the metal-line portion. In and embodiment, the structure further comprises an etch stop layer over and contacting the metal pad, with the conductive plug penetrating through the etch stop layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.