Patent ID: 12236093

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Note that the following description and drawings are examples for describing the present invention, and are omitted and simplified as appropriate for the sake of clarity of description, and the present invention can be implemented in other various forms, and each component may be singular or plural unless otherwise limited.

In addition, the embodiments described below do not limit the invention according to the claims, and all combinations of elements described in the embodiments are not necessarily essential to the method for solving the problems of the invention.

The terminology in the following description is provided below.

First, I/O with a peripheral device with a cache mechanism may be referred to as directly requesting I/O from the device. In such a case, it is assumed that the cache mechanism operates appropriately and I/O from the cache is executed appropriately. However, the present invention is not limited thereto in a case where intervening/non-intervening of the cache function is clearly indicated.

Second, processing of releasing a region on a memory or a storage device may be mentioned; however, depending on a structure of the device or implementation of control software of the device, for example in a case where the storage device is configured by a solid-state drive (SSD), actual release processing may be suspended, and the region may only be recorded as being logically released.

Third, in the description of the processing procedure, there is a case where it is defined to terminate the processing without releasing the memory area used in the processing, but the release of the used memory area is appropriately processed by a mechanism such as a garbage collection (GC).

Fourth, processing may be described with a “program” as a subject. In such a case, a processor that executes the program appropriately issues I/O to a peripheral device such as a storage according to processing contents defined in the program. When a processor that executes a program is not specified, an appropriate processor is assumed to execute the program according to the execution environment.

An FTP (fingerprint table) search for deduplication in the storage system will be described below. An increase in the CPU processing load in the controller due to the FTP search may cause I/O performance degradation. The load on the CPU can be reduced by installing search-dedicated hardware in the controller separately from the CPU and offloading high-load processing to the search-dedicated hardware. For example, a coprocessor or an FPGA for exclusively executing the FPT search is mounted, and the FPT search is offloaded to the coprocessor or the FPGA.

Mounting dedicated hardware inside the controller only for offloading the FPT search may cause problems in terms of cost, mounting area, power capacity, heat generation, and the like. An embodiment herein focuses on a surplus resource of a coprocessor mounted on a controller for a purpose different from the FPT search, and proposes offloading at least a part of the FPT search processing to the surplus resource.

Examples of the coprocessor mounted on a controller for a purpose other than FPT search include a coprocessor mounted on a controller for the purpose of offloading a processing load of a network protocol from a CPU along with support of a high-speed network standard such as 100 gigabit Ethernet (hereinafter 100 GbE) in a storage area network (SAN). Such a coprocessor is referred to as an I/O processing unit (IPU).

The IPU is equipped with a processor for network protocol processing, a memory serving as a buffer for protocol data, and a DMA engine for reading and writing the memory of the controller. It is considered that these resources are not sufficiently utilized depending on the load of the host interface to which the IPU is connected, and a surplus is generated.

As an example, in a configuration in which a plurality of IPUs supporting a high-speed network standard such as 100 GbE are mounted on the same controller, it is sufficiently possible for a single IPU to saturate the I/O band of the whole controller by a migration operation or the like, and in such a case, other IPUs become surplus resources.

By offloading the FPT search by utilizing such IPU surplus resources, it is possible to improve the performance of the storage device without mounting dedicated hardware.

However, the IPU is originally a coprocessor for handling I/O processing with the host, and it is required to avoid an influence on the I/O processing performance due to a processing load of the offloaded FPT search. In addition, since the I/O processing load with the host varies one by one depending on the operation of the host application, the amount of resources that can be used for the FPT search also varies. Therefore, instead of constantly offloading the FPT search, the controller may monitor the I/O processing load of the IPU one by one and determine whether or not offloading is possible as appropriate.

In addition, in a case where a plurality of IPUs are mounted, load distribution among the plurality of IPUs may also be a problem. It is unlikely that the I/O loads are equalized between the IPUs. For example, in a case where the load distribution is implemented by changing the offload destination by the round robin method for each FPK, the influence on the I/O performance may increase in the IPU having a high I/O load. Therefore, it is conceivable to intensively offload the FPT search to the IPU having a low I/O load among the plurality of mounted IPUs.

In the embodiments of the present specification, FPK-based load balancing is proposed to solve the problem caused by FPT search offloading. In one embodiment herein, it is not assumed that a particular hash function is used for the FPK calculation, but it is assumed that the hash function used for the same purpose has sufficient uniformity and randomness. This means that even if the input data is biased to a specific pattern, the FPK output by the hash function can be regarded as a uniform random number.

Therefore, in an implementation in which a specific FPK value range is allocated to each IPU and the search for only the FPK within the allocation range is requested to each IPU, the search load of each IPU can be adjusted by adjusting the FPK allocation range.

In the embodiment herein, the processor load, the memory load, and the DMA load of each IPU are aggregated at regular time intervals, and the FPK value allocation range to each IPU is determined based on the loads.

According to the embodiment herein, the duplication data detection processing in the storage device can be offloaded to the surplus resource of the IPU, and the performance of the storage device can be improved without mounting the dedicated hardware. Note that at least a part of the FPT search can be offloaded to an IPU that performs protocol processing for communication with a network different from the SAN or a device different from the host.

FIG.1is a block diagram illustrating a configuration example of an information processing system according to an embodiment herein.

An information processing system according to an embodiment herein includes a storage system34and a host computer37, which are connected by a SAN111.

The host computer37is a computer device including a peripheral device necessary for executing the application40in addition to a central processing unit (CPU)70and a memory73. The host computer37issues a write command and a read command of data to the connected storage system34in response to a request from the application40.

The storage system34includes a CPU64and a main memory76. The main memory76includes a CPU program area47, a working area45, and an I/O area108. The CPU64executes various programs arranged in the CPU program area47. The CPU64provides a storage service to the host computer37and controls the whole storage system34by controlling reading and writing (read processing and write processing) of data of the volume49based on various programs in the CPU program area47. The physical storage area of the volume is provided by one or more storage drives (not illustrated).

In addition, the storage system34includes an IPU package (IPPK)104on which an I/O processing unit (IPU)55and an IPU memory79are mounted. The IPU package104is connected to the CPU64via a bus117such as PCI Express, for example, to enable mutual communication. The IPU memory79includes an IPU program area92, an IPU working area95, and an IPU I/O area84. The IPU55has a main role of relaying communication between the host computer37and the CPU64based on various programs arranged in the IPU program area92.

A direct memory access (DMA) controller114(DMA114) is mounted on the IPU55, and the IPU55can read and write a space of the main memory76by the DMA114.

FIG.2Aillustrates a block diagram of the inside of the IPU program area92according to the present embodiment.FIG.2Billustrates a block diagram of the inside of the CPU program area43.

The IPU program area92stores a finger print table directory (VFPTD) search routine18, a VFPTD update routine24, and an IPU load acquisition routine30. The VFPTD search routine18and the VFPTD update routine24are regular execution routines that each stand by for a command from the CPU64. The IPU load acquisition routine30is a periodic execution routine that acquires load information of the IPU at a constant cycle.

In addition, a finger print match queue (FPMQ) search routine21is stored in the IPU program area92as a subroutine of the routine. This routine is not directly called by anything other than the above-described routine.

The CPU program area47includes an FPT search routine42, an FPT update routine48, an FPRDT update routine54, and a virtual fingerprint block list (VFPBL) release routine62. The FPT search routine42is called to search for matching data at a timing when data is written from the host computer37and deduplication is executed.

The FPT update routine48is called when the deduplication processing is completed and an entry of new data is registered in the FPT, when data is deleted, or the like. The FPRDT update routine54is a constant execution routine based on an infinite loop. The VFPBL release routine62is called when the VFPBL and FPMQ need to be released due to depletion of the capacity of the CPU working area45or the like.

In addition, the CPU program area47includes an FPT search request routine44and a VFPTD update request routine60as subroutines of the above-described routines. These routines are not directly called by anything other than the above routines.

FIG.3Aillustrates a block diagram of the inside of an IPU working area95. The IPU working area95stores a VFPTD63.FIG.3Bis a block diagram of the inside of a CPU working area45. The CPU working area45stores a VFPBL43and a FPMQ46. The IPU I/O area84does not particularly include a data structure.

FIG.4illustrates a block diagram of the inside of the CPU I/O area108. In the CPU I/O area108, a pair of a submission queue (SQ)20and a completion queue (CQ)23for exchanging command/response with each IPU55are stored per IPU55.

FIG.5illustrates a configuration example of the whole FPT according to the present embodiment. In the present embodiment, the FPT includes three types of tables: the VFPTD63, the VFPBL43, and the FPMQ46.

The VFPTD63is always located in the IPU working area95and gives the address of the corresponding VFPBL43using the high-order bits of the FPK as an index.FIG.5illustrates an example of the VFPTD63that gives a 32-bit VFPBL address from the high-order 12 bits of the FPK; however, the number of bits of the FPK that are used as an index of the VFPTD63is not limited, and the bit width of the VFPBL address is not limited.

The capacity of the IPU memory79is generally smaller than the capacity of the main memory76. The size of the VFPTD63may increase depending on the number of bits of the FPK used as the index, to place a burden on the IPU working area95. Therefore, VFPTD63may also be implemented by a sparse data structure such as a trie instead of a linear array. A trie implementation method of VFPTD63is described inFIG.6.

VFPTD63may take a special value as an invalid VFPBL address to indicate that VFPBL43corresponding to the index FPK does not exist in the CPU working area45.FIG.5illustrates an example in which −1 is reserved as the invalid address, but another value may be set as the invalid address depending on the memory address system of the system.

When the valid VFPBL address is obtained as a result of the IPU55referring to the VFPTD63from the FPK based on the FPT search request from the CPU64, the IPU55reads the corresponding VFPBL43from the CPU working area45to the IPU working area95by using the DMA114. By reading only the required VFPBL43, the burden on the IPU working area95can be reduced.

On the other hand, when the address obtained from the VFPTD63is an invalid VFPBL address, the IPU55requests the CPU64to secure the VFPBL43. The CPU64reads the FPMQ46from the volume49, creates the VFPBL43from the address of the read the FPMQ46, and requests the IPU55to update and re-search the VFPTD63using the address of the newly created VFPBL43.

When the CPU working area45is depleted due to an increase in data cache or the like, it may be necessary to release the VFPBL43and the FPMQ46to secure an area. At that time, all the IPUs55are requested to delete the address to the corresponding VFPBL43from the VFPTD63of each IPU working area95and replace the address with the invalid address. Thereafter, the VFPBL43and the FPMQ46are released.

The VFPBL43is an array of FPMQ addresses arranged in the CPU working area45. The addresses of all the FPMQs46corresponding to the same entry on the VFPTD63are stored in one VFPBL43, and the IPU55can acquire the address to each FPMQ46on the CPU working area45with reference to the VFPBL43on the CPU working area45by the DMA114.

AlthoughFIG.5illustrates an example in which a 32-bit FPMQ address is stored, the bit width of the FPMQ address is not limited to 32 bits.

The FPMQ46is an array arranged in the CPU working area45, and each entry of the FPMQ46includes a set of FPK and LA. The IPU55reads the FPMQ46from the CPU working area45to the IPU working area95based on the FPMQ address obtained with reference to the VFPBL43, and searches for the FPMQ entry including the FPK matching the search target FPK. When the FPK match is detected, the IPU55notifies the CPU64of the LA stored in the entry in which the match is detected. Note that the match may be detected for a plurality of entries in one search, and in this case, the CPU64is notified of LA of all the entries for which the match is detected.

As described above, the FPMQ46may be released from the main memory76when the capacity of the CPU working area45is exhausted. Thereafter, in a case where the access to the FPMQ46is requested again, the CPU64re-ensures the access in the main memory76by the read access from the volume49.

AlthoughFIG.5illustrates an example in which 32-bit values are used as the FPK and the LA, the bit width of these values is not limited to 32 bits.

FIG.6illustrates a configuration example using a trie of the VFPTD63according to the present embodiment.

As described above, when the VFPTD63is configured as a linear array or the like, the capacity of the IPU working area95may become tight. As such, the VFPTD63may be configured as a trie composed of at least one root node53, any number of intermediate nodes52, and any number of leaf nodes55. At this time, each node of the VFPTD63has a child node address corresponding to each value of the corresponding digit, as a table61.

The table61of the leaf nodes55points to the VFPBL43instead of nodes in the VFPTD63.

For example, inFIG.6, when the high-order 12 bits of the FPK (the first 3 digits in the hex trie) are 245, the intermediate node52is first read with reference to the child node address corresponding to the value 2 of the most significant digit in the root node53. Next, the leaf node55is read with reference to the child node address 0x5B74E72B corresponding to the value 4 of the second digit in the table61of the read intermediate node52. Finally, the VFPBL43corresponding to 245 is read with reference to the VFPBL43address 0x1C34062C corresponding to the value 5 of the third digit. Note that the addresses stored in the leaf nodes55refer to memory locations on the CPU working area45, instead of the IPU working area95.

Note that, inFIG.6, an example is illustrated in which the VFPTD63is configured as a hex trie with a maximum depth of 3; however, the cardinal number of the trie may not be 16, and the depth of the trie may not be 3.

FIG.7Aillustrates a configuration example of the SQ20according to the present embodiment.FIG.7Billustrates a configuration example of the CQ23according to the present embodiment.

The SQ20is arranged in the CPU I/O area108and functions as an area for delivering the command23from the CPU64to the IPU55.

The SQ20is implemented as a FIFO ring buffer, a command23transmitted from the CPU64to the IPU55is prepended to the SQ20, and a P-index32indicating the head position of the SQ is incremented. The IPU55retrieves the command23from the tail of the SQ20and increments the C-index29indicating the tail position of the SQ, thereby notifying the CPU64of the reception of the command23.

The CQ23is arranged in the CPU I/O area108and functions as an area for delivering the response59from the IPU55to the CPU64.

Similarly to the SQ20, the CQ23is implemented as a FIFO ring buffer. The response59transmitted from the IPU55to the CPU64is prepended to the CQ23, and the P-index32indicating the head position of the CQ is incremented. The CPU64retrieves the response59from the tail of the CQ, increments the C-index29indicating the tail position of the CQ, and notifies the IPU55of the reception of the response59.

FIG.8illustrates a configuration example of a fingerprint range dispatch table (FPRDT)15according to the present embodiment.

The FPRDT15is a table including two columns: an FPK range9and an allocation destination ID12. A section of the FPK is registered in the FPK range9, and an allocation destination IPU number of the FPT search for the FPK in each FPK section is registered in the allocation destination ID12.

For example, inFIG.8, in a case where the high-order 4 bits of the FPK are 0x2456, the FPK is in the section from 0x2000 to 0x2FFF, and thus the search request destination is the IPU of No. 0.

In addition, in the column of the allocation destination ID12, −1 is registered as a special value, so that the search by the CPU64is designated without requesting the search to any IPU. Load distribution including the CPU64is thus enabled. The CPU64can execute the FPT search processing by the same method as the FPT search processing by the IPU55described herein.

AlthoughFIG.8illustrates an example in which the 16-bit FPK is equally divided into 16 sections, the size of the FPK is not limited to 16 bits, and the number of divisions of the FPK is not limited to 16. In addition, the section division of the FPK does not need to be equal.

By determining the allocation amount of the FTP search processing by the section division of the FPK, the probability of reusability of the reference data for the search processing cached in the IPU package104increases, and the overall efficiency of the FTP search processing can be improved.

FIGS.9A to9Cillustrate examples of load balancing based on the FPRDT15according to the present embodiment.

In the present embodiment, for example, the load information of each IPU55at each time is registered in the IPU load information table31.FIG.9Aillustrates a configuration example of the IPU load information table31. The IPU load information table31indicates a maximum processing capability, a current IPU load factor, a current memory load factor, and a current DMA load factor for each of the plurality of IPUs. The load factor indicates a utilization rate of performance of each component. For example, the IPU load factor may be determined based on the amount of computation per hour, the memory load factor may be determined based on the amount of access per hour, and the DMA load factor may be determined based on the amount of data transfer per hour.

The processing capability of the IPU, the processing capability of the component, and the load factor are in the following relationship. The maximum processing capability of the CPU, the memory, and the DMA matches the maximum processing capability of the IPU. In the example ofFIG.9A, the maximum processing capability of all the IPUs is 5, and the maximum processing capability of each component thereof is also5. The processing capability exhibited (used) by each component is a product of the load factor and the maximum processing capability. The excess processing performance is a value obtained by subtracting the current use processing performance from the maximum processing performance. Note that the maximum processing capability may be different between the IPUs.

The CPU64acquires an IPU load factor, a memory load factor, and a DMA load factor of each IPU55based on information of a response transmitted by an IPU load acquisition routine30to be described later, and registers the IPU load factor, the memory load factor, and the DMA load factor in corresponding columns of the IPU load information table31. The IPU load information table31may be stored in the CPU working area45.

On the other hand, the CPU64acquires the FPT search load at each time and registers the acquired FPT search load in the FPT search load information table28.FIG.9Billustrates a configuration example of the FPT search load information table28. The FPT search load information table28may be stored in the CPU working area45.

The FPT search load information table28indicates the load of the FPT search process to be performed from these at each time and the load ratios of the CPU, the memory, and the DMA in the FPT search process. In the example ofFIG.9B, the FPT search processing load to be executed from now at the current time is 10. The IPU processing capability required for this processing is 10. Furthermore, in the FPT search process, the load ratio related to the CPU, the memory, and the DMA is 100:150:75. That is, the load of the memory is the highest and the load of the DMA is the lowest. In this example, the load ratios are common to all the IPUs; however, the load ratios may be different between the IPUs.

The CPU64updates the FPRDT15so as to maximize the use efficiency of the IPU resource at each time by collating the information in the IPU load information table31with the information in the FPT search load information table28.FIG.9Cillustrates a configuration example of the updated FPRDT15.

For example, in the examples illustrated inFIGS.9A to9C, the IPU of No. 0 has the maximum processing capability of 5, the IPU load factor at the present time is 60%, the memory load factor is 70%, and the DMA load factor is 50%. Therefore, the surplus processing capacity available for the FPT search is 2 (5*0.4) for the CPU, 1.5 (5*0.3) for the memory, and 2.5 (5*0.5) for the DMA.

In this example, as shown inFIG.9B, the load of the memory is the heaviest in the FPT search. Therefore, the FPT search processing amount offloadable to the IPU of No. 0 is one out of ten in total. Note that the FPT search processing amount is offloaded by one. At this time, in the FPRDT15, a processing amount of 1/10 or less of the entire FPT search processing is allocated to the IPU of No. 0.

Similarly, the CPU64determines the offload amount to the IPUs of No. 1 to No. 3. For the remaining processing, −1 or the like is set as an invalid IPU number in the FPRDT15, and the processing is performed by the CPU64, so that the I/O processing performance of the IPU55is not affected, and at the same time, the surplus resources of the IPU55can be effectively utilized to improve the FPT search performance.

FIG.10illustrates an FPT search flow according to the present embodiment.

In step S0101, the FPT search routine42calls an FPT search request routine44.

In step S0102, the FPT search routine42receives a search result of the FPT search request routine44from the CQ23.

In step S0103, the FPT search routine42checks whether the search result of the FPT search request routine44received in step S0102is a read request response of the VFPBL43due to an invalid address being set in the VFPTD63.

In step S0103, when the received search result of the FPT search request routine44is a request response of the VFPBL, in step S0105, the FPT search routine42calls the VFPBL update routine56, loads the VFPBL43and the whole FPMQ46instructed by the VFPBL from the volume49into the CPU working area45, and notifies the IPU55of the result. Thereafter, the process returns to step S0101, and the FPT search is requested to the IPU55.

In step S0104, the FPT search routine42determines whether an FPK match has been detected in the search result received from the IPU55in step S0102.

In a case where an FPK match is detected in step S0104, in step S0106, the FPT search routine42calls a deduplication processing or the like, passes at least one LA received from the IPU55, and causes the process to be performed. An arbitrary method can be adopted as the content of the deduplication processing, and details thereof are omitted herein.

FIG.11illustrates an FPT search request flow according to the present embodiment.

In step S0201, the FPT search request routine44calculates the FPK of the FPT search target data. The FPK is calculated by applying a hash function to the data. The type of the hash function used here is not specified in the present embodiment, and any hash function having sufficient uniformity and randomness for correctly distributing the load can be used.

When a hash function is applied to the FPK to calculate the FPK, an accelerator mounted on the CPU64or the IPU55may be used.

In step S0202, the FPT search request routine44reads the FPT allocation range table15into the memory.

In step S0203, the FPT search request routine44uses the value of the FPK calculated in step S0101to look up in the FPT allocation range table15read in step S0202, and determines an IPU number as a search request target.

In step S0204, the FPT search request routine44determines an FPT search request destination based on the IPU search request destination ID read from the FPT allocation range table15in step S0203.

In a case where the FPT search request destination ID corresponds to any IPU in step S0204, the FPT search request routine44creates a command for requesting the FPT search to the IPU55in step S0205.

In step S0206, the FPT search request routine44stores the FPT search request command created in step S0205in the SQ20of the request destination IPU, thereby transmitting the command. The IPU55that has received the FPT search request command starts the VFPTD search routine18.

On the other hand, in a case where the FPT search request destination ID does not correspond to any IPU in step S0204, the FPT search request routine44calls a routine for executing the FPT search in the CPU64in step S0207instead of requesting the FPT search to the IPU55. Details of the routine will be omitted herein.

FIG.12illustrates a VFPTD search flow according to the present embodiment.

In step S0300, the VFPTD search routine18receives an FPT search request command from the CPU64.

In step S0301, the VFPTD search routine18refers to the VFPTD63using the high-order bits of the FPK to obtain the VFPBL address.

In step S0302, the VFPTD search routine18determines whether the VFPBL address read in step S0301is a valid address that points to a memory location in the CPU working area45. In this example, when the VFPBL address is “−1”, the address is an invalid address.

When the determination result is not the valid VFPBL address in step S0302, it is necessary for the CPU64to secure the VFPBL43. Therefore, in step S0303, the VFPTD search routine18creates a VFPBL request response for requesting the CPU64to secure the VFPBL43.

In step S0304, the VFPTD search routine18stores the VFPBL request response created in step S0303in the CQ23, and transmits the response to the CPU64. Thereafter, the process returns to step S0300and stands by for the next command.

When the determination result is a valid VFPBL address in step S0302, the VFPTD search routine18calls the FPMQ search routine21using the address as a parameter in step S0305. Thereafter, the process returns to step S0300and stands by for the next command.

FIG.13illustrates an FPMQ search flow according to the present embodiment.

In step S0400, the FPMQ search routine21reads the VFPBL43arranged in the CPU working area45into the IPU working area by the DMA114.

In step S0401, the FPMQ search routine21reads the FPMQ46arranged in the CPU working area45into the IPU working area by the DMA114based on the content of the VFPBL43read in step S0400. For example, the FPMQs46of all addresses indicated by the VFPBL43are read. Note that the FPMQ46indicated by the VFPBL43may be sequentially read, and the processing described below may be executed for each FPMQ46.

When the FPMQ46is divided into a plurality of discontinuous regions and arranged in the CPU working area45, all the regions are treated as one FPMQ46. When the FPMQ46in the CPU working area45dispersed in these discontinuous areas is read into the IPU working area95by the DMA114, a function of speeding up transfer of the data divided into a plurality of areas, such as a gathering function of the DMA, may be used.

In step S0402, the FPMQ search routine21retrieves the leading entry of the FPMQ46read into the IPU working area95in step S0401.

In step S0403, the FPMQ search routine21compares the FPK of the retrieved FPMQ entry with the search target FPK.

In step S0403, when the FPK of the FPMQ entry and the search target FPK do not match, in step S0404, the FPMQ search routine21determines whether the current FPMQ entry is the last entry in the FPMQ. In a case where it is the last entry, the processing of the routine is terminated.

If the current FPMQ entry is not the last entry in the FPMQ in step S0404, the FPMQ search routine21reads the next FPMQ entry in FPMQ46in step S0405and returns to step S0403.

In a case where the FPK in the FPMQ entry matches the search target FPK in step S0403, the FPMQ search routine21creates an FPK match detection response for notifying the CPU64of the FPK detection in step S0406. The FPK match detection response includes the LA associated with each of the at least one matching FPK.

In step S0, the FPMQ search routine21stores the FPK match detection response created in step S0406in the CQ23and transmits the same to the CPU64. Thereafter, the process proceeds to step S0404. For example, the VFPTD search may be offloaded to the IPU55, and the FPMQ search may be executed by the CPU64. The searched VFPBL address is passed from the IPU55to the CPU64.

FIG.14illustrates a VFPBL update flow according to the present embodiment.

In step S0501, the VFPBL update routine56reads the VFPBL43from the volume49(drive) to the CPU working area45based on the FPK specified by the caller. When the VFPBL43is dispersedly stored in a plurality of discontinuous regions on the volume49, all the regions are collectively treated as one VFPBL43.

In step S0502, the VFPBL update routine56reads the FPMQ46into the CPU working area45based on the VFPBL43read into the CPU working area45in step S0501.

In step S0503, the VFPBL update routine56calls the VFPTD update request routine60, and requests each IPU55to add the address of the VFPBL43read into the CPU working area45in step S0501to the VFPTD63.

FIG.15illustrates a VFPTD update request flow according to the present embodiment.

In step S0601, the VFPTD update request routine60calculates the FPK of the FPT update target data. For the FPK calculation, a method similar to that of the FPT search request routine44is used.

In step S0602, the VFPTD update request routine60creates an FPT update request command using the FPK calculated in step S0601.

In step S0603, the VFPTD update request routine60resets the IPU ID counter to 0.

In step S0604, the VFPTD update request routine60determines whether the value of the IPU ID counter exceeds the maximum value of the IPU ID.

When the value of the IPU ID counter does not exceed the maximum value of the IPU ID in step S0604, the VFPTD update request routine60transmits a VFPTD update request command to the IPU55indicated by the value of the IPU ID counter in step S0605. Upon receiving the VFPTD update request command, the IPU55sets the address of the target VFPBL43in the entry corresponding to the FPK in the VFPTD63in the IPU working area95.

In step S0606, the VFPTD update request routine60increments the value of the IPU ID counter, and returns to step S0604.

When the value of the IPU ID counter exceeds the maximum value of the IPU ID in step S0604, the VFPTD update request routine terminates the process.

FIG.16illustrates an FPT update flow according to the present embodiment.

In step S0701, the FPT update routine48calculates the FPK of the FPT update target data. The calculation of the FPK is similar to that of the FPT search routine42.

In step S0702, the FPT update routine48calls the VFPTD update request routine60, and requests each IPU55to invalidate the VFPTD entry corresponding to the FPK calculated in step S0701. This is a measure to prevent the IPU55from referring to these data structures and reading invalid data to the IPU55during subsequent update operations of the FPMQ46and the VFPBL43.

In step S0703, the FPT update routine48updates the FPMQ46based on the FPK calculated in step S0701. Note that the update of the FPMQ46refers to, for example, a table independently managed by the CPU64, and details are omitted herein.

In step S0704, the FPT update routine48updates the VFPBL43based on the FPK calculated in step S0701.

In step S0705, the FPT update routine48calls the VFPTD update request routine60again using the updated VFPBL address, and reflects the updated VFPBL address on the VFPTD63held in the working area95by each IPU55.

FIG.17illustrates an IPU load acquisition flow according to the present embodiment.

In step S0801, the IPU load acquisition routine30acquires the processor load of the IPU55.

In step S0802, the IPU load acquisition routine30acquires the memory load of the IPU55.

In step S0803, the IPU load acquisition routine30acquires the DMA load of the IPU55.

In step S0804, the IPU load acquisition routine30creates an IPU load notification response for notifying the CPU64of the IPU load based on the load information acquired in steps S0801, S0802, and S0803.

In step S0805, the IPU load acquisition routine30stores the IPU load notification response created in step S0804in the CQ23and transmits the response to the CPU64.

In step S0806, the IPU load acquisition routine30stands by for a certain period, and returns to step S0801.

FIG.18illustrates an FPRDT update flow according to the present embodiment.

In step S0901, the FPRDT update routine54receives an IPU load notification response from any of the IPUs55. This response includes information on the processor load, the memory load, and the DMA load acquired in the IPU load acquisition routine30.

In step S0902, the FPRDT update routine54updates the FPRDT15based on the information of the response received from the IPU55in step S0901. The update of the FPRDT15is as described with reference toFIGS.9A to9C. Thereafter, the FPRDT update routine returns to step S0901and waits for the next response.

FIG.19illustrates a VFPBL release flow according to the present embodiment.

In step S1001, the VFPBL release routine62calls the VFPTD update request routine60, and requests each IPU55to delete the reference to the VFPBL43corresponding to the FPK in the FPTD and replace the VFPBL with the invalid address.

In step S1002, the VFPBL release routine62releases VFPBL43from the CPU working area45.

In step S1003, the VFPBL release routine62releases the FPMQ46from the CPU working area45.

FIG.20illustrates a VFPTD update flow according to the present embodiment.

In step S1101, the VFPTD update routine24receives a VFPTD update request command from the CPU64.

In step S1102, the VFPTD update routine24updates the VFPTD63arranged in the IPU working area95based on the FPK included in the VFPTD update request command received from the CPU64in step S1101and the corresponding VFPBL address. Thereafter, the process returns to step S1101to wait for the next VFPTD update request command.

The present invention is not limited to the above-described embodiments, and encompasses various modifications. For example, the above-described embodiments have been described in detail for the sake of comprehensible explanation of the present invention, and are not necessarily limited to those provided with all the described configurations. Furthermore, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. In addition, with regard to a part of the configuration of each embodiment, addition of other configurations, deletion, and replacement are possible.

In addition, some or all of the above-described configurations, functions, processing units, and the like may be embodied by hardware, for example, by designing on an integrated circuit. In addition, each of the above-described configurations, functions, and the like may be embodied by software by a processor interpreting and executing a program realizing each function. Information such as a program, a table, and a file for realizing each function can be stored in a storage device such as a memory, a hard disk, and a solid-state drive (SSD), or a recording medium such as an IC card and an SD card.

In addition, only the control lines and the information lines considered to be necessary for the description are shown, and not necessarily all the control lines and the information lines in the product are shown. In practice, it may be considered that almost all the configurations are connected to each other.