Patent ID: 12225714

DETAILED DESCRIPTION

Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. In a direction perpendicular to an extension direction of the WLs, a first height difference is formed between active regions and isolation structures contacting the WLs, so the semiconductor structure increases the contact area between the active regions and the WLs, thereby helping the WLs better control the conductivity of channels in the active regions.

The embodiments of the present application are described in detail below with reference to the drawings. Those of ordinary skill in the art should understand that many technical details are proposed in each embodiment of the present application to help the reader better understand the present application. However, even without these technical details and various changes and modifications made based on the following embodiments, the technical solutions claimed in the present application may still be realized.

FIG.1is a schematic structural view of a semiconductor structure according to the present application.FIG.2is a partially enlarged view along a circular dotted box inFIG.1.FIG.3is another partially enlarged view along a circular dotted box inFIG.1.FIG.4is a sectional view along an AA1direction inFIG.1.

Referring toFIG.1toFIG.4, the semiconductor structure includes: a substrate10, including active regions100arranged at intervals and isolation structures110located between the active regions100; WL trenches120, penetrating through the active regions100and the isolation structures110along a first direction X; and WLs130, located in the WL trenches120. On a section in a second direction Y, a first height difference is formed between the active regions100and the isolation structures110, and the second direction Y is parallel to the substrate10and perpendicular to the first direction X.

The semiconductor structure includes the WL trenches120penetrating through the active regions100and the isolation structures110along the first direction X and the WLs130filling the WL trenches120. In a direction parallel to the second direction Y, the first height difference is formed between active regions100and isolation structures110contacting the WLs130. Therefore, the semiconductor structure increases the contact area between the active regions100and the WLs130, thereby helping the WLs130better control the conductivity of channels in the active regions100.

In some embodiments, the active regions100may be made of silicon, germanium or gallium arsenide. It will be understood that the active regions100may be made of a corresponding material as required. Regions of the active regions100close to the WLs130are provided with channels. When the semiconductor structure is an N-channel metal oxide semiconductor (NMOS) transistor, N-type ions are doped in the channels. When the semiconductor structure is a P-channel metal oxide semiconductor (PMOS) transistor, P-type ions are doped in the channels.

The isolation structures110may be made of silicon oxide, silicon nitride or silicon oxynitride. It will be understood that the isolation structures110may be made of a corresponding material as required.

In some embodiments, the active regions100each includes a protrusion140. Aside of the protrusion140contacts each of the WLs130. Along the second direction Y, a width of the WL130which contacting the protrusion140is smaller than a width of the WL130which contacting each of the isolation structures110. The active regions100each having the protrusion140contacts the WLs130, such that the contact area between the active regions100and the WLs130is increased, and the WLs130better control the conductivity of the channels in the active regions100.

The protrusion140extends toward each of the WLs130. Interfaces wherein the active regions100contact the sidewalls of the WLs130are considered as interfaces wherein the protrusion140contacts the WLs130. It will be understood that a distance from a vertex of the protrusion140to a bottom edge of the protrusion140is the first height difference, and the larger the first height difference, the larger area of the protrusion140and the larger contact area with the WLs130.

In some embodiments, orthographic projection, of a side of each of the WLs130contacting the sides of the active regions100, on a surface of the substrate10is of a stepped shape. The first height difference is controlled based on the number of steps and the height of the step. In some embodiments, the orthographic projection, of the side of each of the WLs130contacting the sides of the active regions100, on the surface of the substrate10may also be of an arc shape, that is, the protrusion140has arc-shaped orthographic projection on the surface of the substrate10. The arc-shaped protrusion140can reduce the point discharge of the protrusion140and malfunction of the semiconductor structure.

In some embodiments, the WLs130each may be of a laminated structure including a semiconductor conductive layer and a metal layer. The semiconductor conductive layer may be made of polycrystalline silicon, and the metal layer may be made of tungsten. In other embodiments, the WLs130each may also be of a single structure only including a semiconductor conductive layer or a metal layer.

The semiconductor structure may further include: a protective layer150on top surfaces of the WLs130. A side of the protective layer150contacts sides of the active regions100and sides of the isolation structures110. In a direction perpendicular to a surface of the substrate10, a length of the protrusion140is greater than a length of each of the WLs130.

It will be understood that, in the direction perpendicular to the surface of the substrate10, the protrusion140contacts a sidewall of each of the WLs130, and the protrusion140further contacts a sidewall of the protective layer150by at least a certain thickness. The protective layer150is configured to protect the WLs130to ensure normal work of the semiconductor structure.

In an embodiment, in the direction perpendicular to the surface of the substrate10, a length of the protrusion140is the same as a sum for a length of each of the WLs130and a length of the protective layer150, that is, the protrusion140contacts the sidewall of each of the WLs130, and the protrusion140further contacts the sidewall of the whole protective layer150. Accordingly, orthographic projection of a sidewall of the protective layer150, contacting the sides of the active regions100, on the surface of the substrate10may also be of a stepped shape.

In other embodiments, the protrusion140may only contact the sidewall of each of the WLs130, that is, in the direction perpendicular to the surface of the substrate10, a length of the protrusion140is less than or equal to a length of each of the WLs130, and orthographic projection, of each of the active regions100and isolation structures110contacting the protective layer150, on the surface of the substrate10is of a straight line. More specifically, in the direction perpendicular to the surface of the substrate10, if the protrusion140is shorter than the WL130, a part of the WL130contacts the protrusion140, and orthographic projection of a contact surface between a remaining part of the WL130and each of the active regions100and the isolation structures110on the surface of the substrate10is of a straight line.

In some embodiments, the protective layer150may be made of silicon oxide or silicon nitride or the like.

It is to be noted that in the direction perpendicular to the surface of the substrate10, each step on the side of the protective layer150contacting the sides of the active regions100has the small length and width, so contact surfaces between the active regions100and the protective layer150inFIG.1appear arc-shaped.

In some embodiments, the stepped shape may be a symmetric pattern, and may be symmetric with respect to a plane perpendicular to the second direction Y. In some embodiments, a ratio of a height of the stepped shape in a direction perpendicular to the first direction X to a width of each of the active regions100between adjacent isolation structures110in a direction parallel to the first direction X is ½-1. When the ratio of the height of the stepped shape to the width of each of the active regions100between adjacent isolation structures110is less than ½, the contact area between the active regions100and the WLs130is small, with the undesirable effect.

In some embodiments, top surfaces of the isolation structures110exposed by the WLs130may further be lower than top surfaces of the active regions100exposed by the WLs130. Besides the top surfaces of the WLs130, the protective layer150may further be located on the top surfaces of the isolation structures110exposed by the WLs130. In some embodiments, the first height difference is also formed between active regions100and isolation structures110exposed by bottom surfaces of the WL trenches120, and orthographic projection of the active regions100within a plane in the first direction X is also of a stepped shape. In some embodiments, the projection of the active regions100exposed by the bottom surfaces of the WL trenches120within the plane in the first direction X and the projection of the active regions100exposed by the sidewalls of the WL trenches120on the surface of the substrate10may be of a same type.

By forming the stepped active regions100on the bottom surfaces of the WL trenches120, the contact area between the bottom surfaces of the WLs130and the active regions100is increased, and the WLs130better control the conductivity of the channels in the active regions100.

The semiconductor structure provided by the embodiment of the present application includes WL trenches120penetrating through active regions100and isolation structures110along a first direction X, and WLs130filling the WL trenches120. A first height difference is formed in a second direction Y between the active regions100and the isolation structures110, and the second direction Y is parallel to a substrate10and perpendicular to the first direction X. By providing the semiconductor structure having the first height difference in the second direction Y between the active regions100and the isolation structures110in the WL trenches120, the present application increases the contact area between the active regions100and the WLs130and the flow area of the current, thereby helping the WLs130better control the conductivity of channels in the active regions100, and improving the working efficiency of the semiconductor structure.

Another embodiment of the present application further provides a semiconductor structure. The semiconductor structure is approximately the same as that described in the above embodiment, with the following main differences: Portions of the active regions contacting the WLs each are referred to as a recess, and a width of the WL which contacting the recess is greater than a width of the WL which contacting each of the isolation structures.

FIG.5is a schematic structural view of a semiconductor structure according to another embodiment of the present application.FIG.6is a partially enlarged schematic view along a dotted line inFIG.5.

Referring toFIG.5andFIG.6, the semiconductor structure includes: a substrate20, including active regions200arranged at intervals and isolation structures210located between the active regions200; WL trenches220, penetrating through the active regions200and the isolation structures210along a first direction X; and WLs230, located in the WL trenches220. On a section parallel to a second direction Y, a first height difference is formed between the active regions200and the isolation structures210, and the second direction Y is parallel to the substrate20and perpendicular to the first direction X.

In some embodiments, the active regions200each include a recess240. A side of the recess240contacts each of the WLs230. Along the first direction X, the width of the WL230which contacting the recess240is greater than the width of the WL230which contacting each of the isolation structures210. The recess240extends toward a direction away from each of the WLs230. By forming the active regions200each having the recess240, the contact area between the active regions200and the WLs230is increased, and the WLs230better control the conductivity of channels in the active regions200.

In some embodiments, orthographic projection, of a side of each of the WLs230contacting sides of the active regions200, on a surface of the substrate20may be of a stepped shape, namely orthographic projection of the recess240on the surface of the substrate20may be of a stepped shape. In some embodiments, if the number of steps in the stepped shape is sufficient, the orthographic projection of the recess240on the surface of the substrate20is of an arc shape.

Specifically, the stepped shape may be a symmetric pattern, and may be symmetric with respect to a plane perpendicular to the second direction Y. In addition, a ratio of a height of the stepped shape in a direction perpendicular to the first direction X to a width of each of the active regions200between adjacent isolation structures210in a direction parallel to the first direction X is ½-1.

It is to be noted that the contact area between the active regions200and the WLs230is increased regardless of the stepped recess240or the arc-shaped recess240, thereby helping the WLs230better control the conductivity of channels in the active regions200, and improving the working efficiency of the semiconductor structure.

In some embodiments, the semiconductor structure further includes: a protective layer250on top surfaces of the WLs230. A side of the protective layer250contacts sides of the active regions200and a side of the protective layer250contacts sides of the isolation structures210. In a direction perpendicular to a surface of the substrate20, a length of the recess240is greater than a length of the each of the WLs230.

It will be understood that in the direction perpendicular to the surface of the substrate20, the length of the recess240may be greater than the length of the each of the WLs230, namely the recess240further contacts a sidewall of the protective layer250besides a sidewall of each of the WLs230. In this way, orthographic projection of a side of the protective layer250contacting the sides of the active regions200on the surface of the substrate20is also of the stepped shape. The active regions200each are provided with the recess240, and the recess240contacts each of the WLs230, so the semiconductor structure provided by the embodiment increases the contact area between the active regions200and the WLs230and the flow area of the current through the recess240, thereby helping the WLs230better control the turn-on speed of channels in the active regions200, and improving the working efficiency of the semiconductor structure.

An embodiment of the present application further provides a method of manufacturing a semiconductor structure, which may be used to manufacture the semiconductor structure in the above embodiment. The method of manufacturing a semiconductor structure provided by the embodiment of the present application will be described below with reference to the accompanying drawings. Contents the same as or corresponding to those mentioned in the semiconductor structure may be referred to the corresponding descriptions and will not be repeated herein.

FIG.7toFIG.15are schematic structural diagrams corresponding to various steps in a method of manufacturing a semiconductor structure according to an embodiment of the present application.

Referring toFIG.7, a substrate10is provided. The substrate10includes active regions100arranged at intervals and isolation structures110located between the active regions100.

Referring toFIG.8andFIG.9,FIG.9is a sectional view along a dotted line AA1inFIG.8. The active regions100and the isolation structures110are patterned to form WL trenches120. The WL trenches120extend along a first direction X. Sidewalls of the WL trenches120expose the active regions100and the isolation structures110.

In some embodiments, the WL trenches120are formed with dry etching. In some embodiments, there are different etching rates for the active regions100and the isolation structures110in the dry etching, such that the WL trenches120each have an uneven bottom surface. For example, if an etching rate for the active regions100is greater than that for the isolation structures110in the etching, top surfaces of isolation structures110are higher than top surfaces of active regions100on bottom surfaces of the WL trenches120. If an etching rate for the active regions100is less than that for the isolation structures110in the etching, the top surfaces of the isolation structures110are lower than the top surfaces of the active regions100on the bottom surfaces of the WL trenches120.

In some embodiments, the top surfaces of the active regions100may also be as high as the top surfaces of the isolation structures110on the bottom surfaces of the WL trenches120, and sides of the active regions100and sides of the isolation structures110exposed by the sidewalls of the WL trenches120may be flush.

Referring toFIG.10toFIG.15, corner rounding is performed at least once on the active regions100and isolation structures110exposed by the sidewalls of the WL trenches120(referring toFIG.9), such that a first height difference is formed in a second direction Y between the active regions100and isolation structures110exposed by the sidewalls of the WL trenches120(referring toFIG.9).

The corner rounding will be described below in detail with reference to the drawings. Referring toFIG.10andFIG.11,FIG.10is a sectional view along an AA2direction inFIG.9, andFIG.11is a partially enlarged schematic view along a circular dotted line inFIG.10. The isolation structures110exposed by the sidewalls of the WL trenches120(referring toFIG.9) are etched, such that the active regions100are partially exposed by the isolation structures110in the second direction Y.

In some embodiments, wet etching may be used to etch the isolation structures110, namely the isolation structures110exposed by the sidewalls of the WL trenches120(referring toFIG.9).

When the isolation structures110are made of silicon oxide, a hydrofluoric acid solution having a molar concentration of 40-60%, such as a hydrofluoric acid solution having a molar concentration of 49%, serves as an etching reagent in the wet etching.

In some embodiments, the wet etching lasts for 10-30 s, such as 15 s, 17 s or 20 s. It will be understood that the etching depth may be controlled by adjusting the mole of the solvent and the etching time in the wet etching.

Referring toFIG.12, exposed active regions100are etched. In the exposed active regions100, an etching rate for corner regions is greater than that for regions out of the corner regions.

In some embodiments, the wet etching is used to etch the exposed active regions100. The wet etching includes that the active regions100are etched for 10-30 s with a nitric acid solution having a molar concentration of 20-50%.

In some embodiments, the active regions100are etched by a thickness of 1-3 nm in a direction parallel to the second direction. The smaller the etched thickness of the active regions100, the greater the corresponding number of times for performing the corner rounding. If the etched thickness of the active regions100is large, the active regions100will be removed excessively to affect the ion carrying capability of the active regions100.

It will be understood that the etched thickness of the active regions100may be controlled by adjusting the molar concentration of the etching reagent and the etching time.

Referring toFIG.13andFIG.14, next corner rounding is performed.

Specifically, referring toFIG.13, isolation structures110exposed by a sidewall of at least one of the WL trenches120(referring toFIG.9) are etched.

Referring toFIG.14, the wet etching is used to etch the active regions100exposed by the sidewalls of the WL trenches120(referring toFIG.9).

It will be understood that whenever the corner rounding is performed again, there is one step more formed on orthographic projection of each of the active regions100exposed by the WL trenches120(referring toFIG.9) on the surface of the substrate10, and a height difference from the top surfaces of the active regions100exposed by the sidewalls of the WL trenches120(referring toFIG.9) to the isolation structures110exposed by the sidewalls of the WL trenches120(referring toFIG.9) is increased. By controlling the number of times for performing the corner rounding, the first height difference is formed between the active regions100and isolation structures110exposed by the sidewalls of the WL trenches120(referring toFIG.9).

Referring toFIG.15, upon completion of the corner rounding, the first height difference is formed between the active regions100and isolation structures110exposed by the sidewalls of the WL trenches120(referring toFIG.9).

The corner rounding may be performed for 2-10 times. It will be understood that the number of times for performing the corner rounding may be adjusted according to the required first height difference.

After the corner rounding, the active regions100each have arc-shaped orthographic projection on the surface of the substrate10(referring toFIG.1). It will be understood that, as the step formed by each corner rounding is small, the active regions100after repeated corner rounding each are of an arc shape. Actually, the arc shape is the step shape composed of a plurality of steps.

Referring toFIG.1, upon completion of the corner rounding, WLs130filling the WL trenches120are formed.

In some embodiments, when the isolation structures110exposed by the sidewalls of the WL trenches120are etched, top surfaces of the isolation structures110may further be etched. Top surfaces of remaining isolation structures110enclose recessed regions with adjacent active regions100. Accordingly, after the WLs130are formed, the method of manufacturing a semiconductor structure may further include: A protective layer150is formed. The protective layer150is located on surfaces of the WLs130and fills the WL trenches120. The protective layer150further fills the recessed regions.

According to the method of manufacturing a semiconductor structure provided by the embodiment of the present application, after the active regions100and the isolation structures110on the substrate10are patterned to form the WL trenches120extending along the first direction X, the corner rounding is performed at least once on the active regions100and isolation structures110exposed by the sidewalls of the WL trenches120to form the first height difference in the second direction Y between the active regions100and isolation structures110exposed by the sidewalls of the WL trenches120. By forming the protrusion140on each of the active regions100, the contact area between the active regions100and the WLs130and the flow area of the current are increased, thereby helping the WLs130better control turn-on speeds of channels in the active regions100, and improving the working efficiency of the semiconductor structure.

Another embodiment of the present application further provides a method of manufacturing a semiconductor structure, which may be used to manufacture the semiconductor structure in the above embodiment. It is to be noted that the manufacturing method in the embodiment of the present application differs from the manufacturing method in the above embodiment mainly in: The active regions on the sidewalls of the WL trenches have different shapes. Contents same as or corresponding to the above embodiment may refer to the corresponding descriptions in the above embodiment and will not be repeated hereinafter.

Referring toFIG.16,FIG.16is a partially enlarged view along a circular dotted line inFIG.10. The active regions200exposed by the sidewalls of the WL trenches220(referring toFIG.5) are etched.

Referring toFIG.17, an oxide layer260is formed on top surfaces of the active regions200exposed by the sidewalls of the WL trenches220(referring toFIG.5) and sidewalls of isolation structures210exposed after the active regions200are etched.

In some embodiments, atomic layer deposition (ALD) is used to form the oxide layer260on the top surfaces of the active regions200exposed by the sidewalls of the WL trenches220(referring toFIG.5) and the sidewalls of the isolation structures210. The ALD is helpful to form the oxide layer260with good uniformity and compactness and better control the thickness of the oxide layer260.

In some embodiments, the oxide layer260may be made of silicon oxide.

Referring toFIG.18andFIG.19,FIG.18is a sectional view along an AA3direction inFIG.17. Dry etching is used to etch the oxide layer260.

It will be understood that tilting angles of ions in the dry etching are usually increased to completely etch the oxide layer260on bottom surfaces of the WL trenches220(referring toFIG.5). By adjusting incident angles of the ions, the oxide layer260on the surfaces of the active regions200exposed by the sidewalls of the WL trenches220(referring toFIG.5) is removed completely.

In some embodiments, the oxide layer260on the sidewalls of the isolation structures210may further be retained to lay the foundation for subsequent etching of the active regions200.

Referring toFIG.20, wet etching is used to etch the active regions200exposed by the sidewalls of the WL trenches220(referring toFIG.5).

Because of isotropy of the wet etching, etched active regions200each have arc-shaped projection on the surface of the substrate20.

In some embodiments, the active regions200are made of silicon, and a solution mixed by nitric acid having a molar concentration of 20-50% and water may serve as a reagent in the wet etching to etch the active regions200.

Referring toFIG.21, the oxide layer260(referring toFIG.19) and at least one of the isolation structures210exposed by the sidewalls of the WL trenches220(referring toFIG.5) are removed to expose surfaces of the active regions200.

In some embodiments, both the oxide layer260(referring toFIG.19) and the isolation structures210are made of silicon oxide. While the wet etching is used to etch the oxide layer260(referring toFIG.19), at least one of the isolation structures210exposed by the sidewalls of the WL trenches220(referring toFIG.5) is removed synchronously.

Referring toFIG.22, the wet etching is used to etch the active regions200exposed by the sidewalls of the WL trenches220(referring toFIG.5) to expand radii of curvature of etched portions of the active regions200, thereby increasing the contact area between the active regions200and the subsequently formed WLs230.

In some embodiments, the oxide layer may also not be formed, but the active regions are directly etched. The contact area between the active regions and the WLs in the scheme in which the oxide layer is not formed, but the active regions are directly etched is less than that between the active regions and the WLs in the scheme in which the oxide layer is formed and the active regions are etched.

It will be understood that a recess240may be formed in each of the active regions200by repeating the above steps. The subsequently formed WLs230each contact the side of the recess240.

The manufacturing method further includes: WLs230filling the WL trenches220are formed, a side of the recess240contacting each of the WLs230. A protective layer250is formed, the protective layer250covering surfaces of the WLs230and filling the WL trenches220. For the method and step for forming the WLs230and the protective layer250, refer to the detailed descriptions in the above embodiment.

In the embodiment, the active regions200each having the recess240are formed, and the recess240contacts each of the WLs230, such that the contact area between the active regions200and the WLs230and the flow area of the current are increased, thereby helping the WLs230better control the turn-on speed of channels in the active regions200, and improving the working efficiency of the semiconductor structure.

Those of ordinary skill in the art should understand that the above implementations are specific embodiments for implementing the present application. In practical applications, various changes may be made to the above implementations in terms of form and details without departing from the spirit and scope of the present application.

Those skilled in the art may make changes and modifications to the implementations without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.