Patent ID: 12204366

DETAILED DESCRIPTION

Hereinafter, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.

FIG.1is a diagram illustrating a construction of a semiconductor system100according to an embodiment of the present technology. InFIG.1, the semiconductor system100may include a first semiconductor device110and a second semiconductor device120. The first semiconductor device110may be a master device for controlling an operation of the second semiconductor device110. The second semiconductor device120may be a slave device capable of performing various operations under the control of the first semiconductor device110. The first semiconductor device110may provide various control signals that are necessary for the second semiconductor device120to operate. The first semiconductor device110may include various types of host devices. For example, the first semiconductor device110may be a host device, such as a central processing unit (CPU), a graphic processing unit (GPU), a multi-media processor (MMP), a digital signal processor, an application processor (AP), a memory controller, and the like. For example, the second semiconductor device120may be a memory device. The memory device may include volatile memory and nonvolatile memory. The volatile memory may include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. The nonvolatile memory may include read only memory (ROM), programmable ROM (PROM), electrically erasable PROM (EEPROM), electrically programmable ROM (EPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like.

The second semiconductor device120may be coupled to the first semiconductor device110through a plurality of buses. The plurality of buses may be a signal transmission path, link, or channel for transmitting a signal. The plurality of buses may include a clock bus101, a command address bus102, and a data bus103. The clock bus101and the command address bus102may be unidirectional buses from the first semiconductor device110to the second semiconductor device120. The data bus103may be a bidirectional bus. The second semiconductor device120may be coupled to the first semiconductor device110through the clock bus101and may receive a system clock signal SCK from the first semiconductor device110. The system clock signal SCK may be a differential signal along with a complementary signal SCKB and may be transmitted through the clock bus101. The second semiconductor device120may be coupled to the first semiconductor device110through the command address bus102and may receive a command address signal CA from the first semiconductor device110. The command address signal CA may include a plurality of signal sets including a plurality of bits. The second semiconductor device120may receive the command address signal CA based on the system clock signal SCK. The second semiconductor device120may be coupled to the first semiconductor device110through the data bus103, and the second semiconductor device120may receive data DQ from the first semiconductor device110or may transmit the data DQ to the first semiconductor device110.

The first semiconductor device110may include a system clock generation circuit111, a command address generation circuit112, and a data input/output circuit113. The system clock generation circuit111may generate the system clock signal SCK and the complementary signal SCKB. The system clock generation circuit111may include any clock generator for generating the system clock signal SCK. For example, the system clock generation circuit may include an oscillator, a phase-locked loop circuit, or a delay-locked loop circuit. The system clock generation circuit111may generate the system clock signal SCK having a frequency that is suitable for the first and second semiconductor devices110and120to communicate with each other. The system clock generation circuit111may transmit the system clock signal SCK and the complementary signal SCKB to the second semiconductor device120through the clock bus101. The system clock generation circuit111may provide the system clock signal SCK and the complementary signal SCKB to at least one of the command address generation circuit112and the data input/output circuit113.

The command address generation circuit112may generate the command address signal CA based on a request REQ. The command address generation circuit112may generate the command address signal CA that instructs the second semiconductor device120to perform various operations according to the request REQ. The command address generation circuit112may transmit the command address signal CA to the second semiconductor device120through the command address bus102. The command address generation circuit112may receive the system clock signal SCK and may transmit the command address signal CA to the command address bus102in synchronization with the system clock signal SCK.

The data input/output circuit113may be coupled to the second semiconductor device120through the data bus103, and the data input/output circuit113may transmit the data DQ to the second semiconductor device120through the data bus103or may receive the data DQ that is transmitted by the second semiconductor device120through the data bus103. The data input/output circuit113may receive the system clock signal SCK and may perform a data input/output operation in synchronization with the system clock signal SCK. The data input/output circuit113may transmit internal data IND1 of the first semiconductor device110as the data DQ in synchronization with the system clock signal SCK. The second semiconductor device120may transmit the data DQ to the data input/output circuit113in synchronization with the system clock signal SCK, and the data input/output circuit113may generate the internal data IND1 of the first semiconductor device110based on the received data.

The second semiconductor device120may include a clock reception circuit121, a clock distribution network122, a command address reception circuit123, and a data input/output circuit124. The clock reception circuit121may be coupled to the clock bus101and may receive the system clock signal SCK that is transmitted by the first semiconductor device110through the clock bus101. The clock reception circuit121may receive the system clock signal SCK by differentially amplifying the system clock signal SCK and the complementary signal SCKB. The clock reception circuit121may generate a reference clock signal pair CK and CKB by receiving the system clock signal SCK and the complementary signal SCKB. The reference clock signal pair CK and CKB may be provided to the clock distribution network122.

The clock distribution network122may be coupled to the clock reception circuit121and may receive the reference clock signal pair CK and CKB from the clock reception circuit121. In an embodiment, the clock reception circuit121may be integrated into the clock distribution network122. The clock distribution network122may generate a plurality of internal clock signals based on the reference clock signal pair CK and CKB. The plurality of internal clock signals may include a command clock signal CCK and a data clock signal DCK. The clock distribution network122may distribute the plurality of internal clock signals to the internal circuits of the second semiconductor device120. The clock distribution network122may provide the command clock signal CCK to the command address reception circuit123and may provide the data clock signal DCK to the data input/output circuit124. The data clock signal DCK may have a higher frequency than the command clock signal CCK. The clock distribution network122may include a frequency divider, such as a clock divider, in order to generate the plurality of internal clock signals having different frequencies from the system clock signal pair SCK and SCKB and/or the reference clock signal pair CK and CKB. The clock distribution network122may include a plurality of clock trees for distributing the plurality of internal clock signals.

The command address reception circuit123may be coupled to the command address bus102and may receive the command address signal CA that is transmitted by the first semiconductor device110through the command address bus120. The command address reception circuit123may receive a reference voltage VREF and may receive the command address signal CA by differentially amplifying the command address signal CA and the reference voltage VREF. The command address reception circuit123may receive the command clock signal CCK from the clock distribution network122. The command address reception circuit123may synchronize the received command address signal with the command clock signal CCK by latching the received command address signal CA in synchronization with the command clock signal CCK.

The data input/output circuit124may be coupled to the first semiconductor device110through the data bus103, and the data input/output circuit124may transmit the data DQ to the first semiconductor device110through the data bus103or may receive the data DQ that is transmitted by the first semiconductor device110through the data bus103. The data input/output circuit124may receive the data clock signal DCK from the clock distribution network122and may perform a data input/output operation in synchronization with the data clock signal DCK. The data input/output circuit124may transmit internal data IND2 of the second semiconductor device120as the data DQ in synchronization with the data clock signal DCK. The data input/output circuit124may receive the data DQ that is transmitted by the first semiconductor device110in synchronization with the data clock signal DCK and may generate the internal data IND2 of the second semiconductor device120based on the received data.

FIG.2is a diagram illustrating a construction of a clock distribution network200according to an embodiment of the present technology. The clock distribution network200may be applied as the clock distribution network122, illustrated inFIG.1. Referring toFIG.2, the clock distribution network200may receive a first input clock signal CKI and a second input clock signal CKIB and may generate a first output clock signal CKO and a second output clock signal CKOB. The first and second input clock signals CKI and CKIB may be signals that swing at a current mode logic (CML) level and may be a differential clock signal pair. The first and second output clock signals CKO and CKOB may be signals that swing at a complementary metal-oxide-semiconductor (CMOS) level and may be a differential clock signal pair. The clock distribution network200may generate the first and second output clock signals CKO and CKOB by converting the swing range of the first and second input clock signals CKI and CKIB from the CML level to the CMOS level. When the clock distribution network200is applied as the clock distribution network122as illustrated inFIG.1, the first and second input clock signals CKI and CKIB may correspond to the reference clock signal pair CK and CKB or a division clock signal pair that is generated by dividing the reference clock signal pair CK and CKB. The first and second output clock signals CKO and CKOB may correspond to at least one of the command clock signal CCK and the data clock signal DCK.

The clock distribution network200may include a global clock tree210, a local clock tree220, and a wake-up control circuit230. The global clock tree210may generate a first global clock signal GCK and a second global clock signal GCKB by receiving the first and second input clock signals CKI and CKIB. The global clock tree210may buffer the first and second input clock signals CKI and CKIB and may generate the first and second global clock signals GCK and GCKB. The first and second global clock signals GCK and GCKB may be a differential signal pair. The global clock tree210may generate the first and second global clock signals GCK and GCKB by buffering the first and second input clock signals CKI and CKIB to the CML level. The first and second global clock signals GCK and GCKB may be signals that swing at the CML level. The global clock tree210may receive a global enable signal GEN and may be selectively activated based on the global enable signal GEN. When the global enable signal GEN is enabled, the global clock tree210may be activated and may generate the first and second global clock signals GCK and GCKB based on the first and second input clock signals CKI and CKIB. When the global enable signal GEN is disabled, the global clock tree210may be deactivated and might not generate the first and second global clock signals GCK and GCKB. The first global clock signal GCK may be transmitted through a first clock transmission line201and distributed to the local clock tree220. The second global clock signal GCKB may be transmitted through a second clock transmission line202and distributed to a local clock tree220. The first and second clock transmission lines201and202may be internal signal transmission lines that are disposed within a single semiconductor device. In an embodiment, the first and second clock transmission lines201and202may be signal transmission lines that enable one semiconductor device to be coupled to another semiconductor device within a single package.

The local clock tree220may be coupled to the first and second clock transmission lines201and202and may receive the first and second global clock signals GCK and GCKB through the first and second clock transmission lines201and202. The local clock tree220may generate the first output clock signal CKO and the second output clock signal CKOB from the first and second global clock signals GCK and GCKB. The local clock tree220may generate the first and second output clock signals CKO and CKOB that swing at the CMOS level by converting the first and second global clock signals GCK and GCKB that swing at the CML level. The local clock tree220may generate the first output clock signal CKO by converting the swing range of the first global clock signal GCK to the CMOS level and may generate the second output clock signal CKOB by converting the swing range of the second global clock signal GCKB to the CMOS level. The local clock tree220may receive a local enable signal LEN and may be selectively activated based on the local enable signal LEN. When the local enable signal LEN is enabled, the local clock tree220may be activated and may generate the first and second output clock signals CKO and CKOB from the first and second global clock signals GCK and GCKB. When the local enable signal LEN is disabled, the local clock tree220may be deactivated or partially activated and may set the voltage levels of the first and second output clock signals CKO and CKOB as predetermined voltage levels.

The wake-up control circuit230may receive a clock enable signal CKEN and may generate the global enable signal GEN and the local enable signal LEN based on the clock enable signal CKEN. The clock enable signal CKEN may be a signal that determines an operation mode of a semiconductor device including the clock distribution network200. For example, when the semiconductor device operates in a low power mode or a standby mode, the clock enable signal CKEN may be disabled. When the semiconductor device operates in another mode other than the low power mode or the standby mode (e.g., when the semiconductor device performs a data input/output operation), the clock enable signal CKEN may be enabled. The clock enable signal CKEN may be one of the control signals that are provided from the first semiconductor device110to the second semiconductor device120as illustrated inFIG.1. When the clock enable signal CKEN is disabled, the wake-up control circuit230may disable both the global enable signal GEN and the local enable signal LEN. When the clock enable signal CKEN is enabled, the wake-up control circuit230may enable the local enable signal LEN and the global enable signal GEN. The wake-up control circuit230may sequentially enable the local enable signal LEN and the global enable signal GEN. When the clock enable signal CKEN is enabled, the wake-up control circuit230may enable the global enable signal GEN after enabling the local enable signal LEN. A time at which the local enable signal LEN is enabled to a time at which the global enable signal GEN is enabled may be arbitrarily set. The wake-up control circuit230may further generate a common mode enable signal CEN. The wake-up control circuit230may be enabled when the clock enable signal CKEN and/or the local enable signal LEN is enabled, and may be disabled when the global enable signal GEN is enabled.

FIG.3is a timing diagram illustrating an operation of the wake-up control circuit230as illustrated inFIG.2. Referring toFIG.3, when the clock enable signal CKEN is in a disable state, the wake-up control circuit230may maintain all of the global enable signal GNE, the local enable signal LEN, and the common mode enable signal CEN in the disable state. When the clock enable signal CKEN is enabled, the wake-up control circuit230may maintain the disable state of the global enable signal GEN but may enable the local enable signal LEN and the common mode enable signal CEN. When a predetermined time “t1” elapses, the wake-up control circuit230may enable the global enable signal GEN and may disable the common mode enable signal CEN. The common mode enable signal CEN may have a pulse width corresponding to the predetermined time “t1”. In an embodiment, the common mode enable signal CEN may have a pulse width corresponding to a time that is shorter or longer than the predetermined time “t1”.

Referring back toFIG.2, the local clock tree220may perform various operations by being controlled by the wake-up control circuit230. The local clock tree220may set the voltage levels of a first output node N1 and a second output node N2 as a common mode voltage level based on the local enable signal LEN and the global enable signal GEN. The first output clock signal CKO may be output through the first output node N1, and the second output clock signal CKOB may be output through the second output node N2. The common mode voltage level may be a middle voltage level between a first voltage V1 and a second voltage V2. For example, the common mode voltage level may be a voltage level corresponding to half of the sum of the first and second voltages ((V1+V2)/2). The first voltage V1 may have a higher voltage level than the second voltage V2. For example, the first voltage V1 may be a power supply voltage, and the second voltage V2 may be a ground voltage. The global clock tree210and the local clock tree220may receive the first and second voltages V1 and V2 as an operating voltage. The local clock tree220may receive the common mode enable signal CEN and may set the voltage levels of the first and second output nodes N1 and N2 as the common mode voltage level based on the common mode enable signal CEN. When the common mode enable signal CEN is enabled (i.e., when the local enable signal LEN is enabled and the global enable signal GEN is disabled), the local clock tree220may set the voltage levels of the first and second output nodes N1 and N2 as the common mode voltage level. When the common mode enable signal CEN is disabled (i.e., when the global enable signal GEN is enabled after the local enable signal LEN is enabled), the local clock tree220may release the state in which the voltage levels of the first and second output clock signals CKO and CKOB have been set as the common mode voltage level and may generate the first and second output clock signals CKO and CKOB by receiving the first and second global clock signals GCK and GCKB from the global clock tree210. When the clock enable signal CKEN is disabled, the local clock tree220may precharge the first and second output nodes N1 and N2. When the clock enable signal CKEN and/or the local enable signal LEN is disabled, the local clock tree220may perform a precharge operation of setting the voltage levels of the first and second output nodes N1 and N2 as opposite logic levels. For example, the local clock tree220may set the voltage level of the first output node N1 as the voltage level of the second voltage V2 and may precharge the voltage level of the second output node N2 to the voltage level of the first voltage V1.

The global clock tree210may include a first global buffer211and a second global buffer212. The first global buffer211may receive the global enable signal GEN and the first input clock signal CKI and may generate the first global clock signal GCK by buffering the first input clock signal CKI based on the global enable signal GEN. When the global enable signal GEN is enabled, the first global buffer211may generate the first global clock signal GCK by buffering the first input clock signal CKI to the CML level. When the global enable signal GEN is disabled, the first global buffer211might not generate the first global clock signal GCK. The first global buffer211may include a plurality of CML buffers that are sequentially coupled in series. The plurality of CML buffers may generate the first global clock signal GCK by sequentially buffering the first input clock signal CKI. The plurality of CML buffers may be selectively activated based on the global enable signal GEN. InFIG.2, the first global buffer211may include two CML buffers, but the disclosure is not limited thereto. For example, the first global buffer211may include any even number of CML buffers.

The second global buffer212may receive the global enable signal GEN and the second input clock signal CKIB and may generate the second global clock signal GCKB by buffering the second input clock signal CKIB based on the global enable signal GEN. When the global enable signal GEN is enabled, the second global buffer212may generate the second global clock signal GCKB by buffering the second input clock signal CKIB to the CML level. When the global enable signal GEN is disabled, the second global buffer212might not generate the second global clock signal GCKB. The second global buffer212may include a plurality of CML buffers that are sequentially coupled in series. The plurality of CML buffers may generate the second global clock signal GCKB by sequentially buffering the second input clock signal CKIB. The plurality of CML buffers may be selectively activated based on the global enable signal GEN. InFIG.2, the second global buffer212may include two CML buffers, but the disclosure is not limited thereto. For example, the number of CML buffers that are included in the second global buffer212may be any even number of CML buffers. The number of CML buffers that are included in the second global buffer212may be substantially the same as the number of CML buffers that are included in the first global buffer212.

The local clock tree220may include a first converter221, a second converter222, and a common mode setting circuit223. The first converter221may receive the local enable signal LEN and the first global clock signal GCK and may generate the first output clock signal CKO from the first global clock signal GCK based on the local enable signal LEN. The first converter221may be a CML to CMOS converter. The first converter221may convert the first global clock signal GCK that swings at the CML level to the first output clock signal CKO that swings at the CMOS level. When the local enable signal LEN is enabled, the first converter221may generate the first output clock signal CKO by converting the first global clock signal GCK. When the local enable signal LEN is disabled, the first converter221might not generate the first output clock signal CKO from the first global clock signal GCK.

The first converter221may include a first inverter221-1, a first resistor221-2, and a first pass gate221-3. An input terminal of the first inverter221-1may be an input terminal A1 of the first converter221and may receive the first global clock signal GCK. The first inverter221-1may invert and drive a signal that is input to the input terminal A1. One end of the first resistor221-2may be coupled to the input terminal of the first inverter221-1. The first pass gate221-3may be coupled between the other end of the first resistor221-2and an output terminal of the first inverter221-1. The output terminal of the first inverter221-1may be an output terminal B1 of the first converter221. The first pass gate221-3may receive the local enable signal LEN. When the local enable signal LEN is enabled to a high logic level and a complementary signal LENB is disabled to a low logic level, the first pass gate221-3may activate a feedback loop that sequentially couples the output terminal of the first inverter221-1, the first resistor221-2, and the input terminal of the first inverter221-1, by coupling the output terminal of the first inverter221-1to the other end of the first resistor221-2. When the local enable signal LEN is disabled to a low logic level and the complementary signal LENB is enabled to a high logic level, the first pass gate221-3may deactivate the feedback loop by electrically separating the output terminal of the first inverter221-1from the other end of the first resistor221-2. The components of the first converter221are merely an example. Any CML to CMOS converter may be modified to be selectively activated based on the local enable signal LEN and may be applied and/or adopted as the first converter221.

The second converter222may receive the local enable signal LEN and the second global clock signal GCKB and may generate the second output clock signal CKO from the second global clock signal GCKB based on the local enable signal LEN. The second converter222may be a CML to CMOS converter. The second converter222may convert the second global clock signal GCKB that swing at the CML level to the second output clock signal CKOB that swings at the CMOS level. When the local enable signal LEN is enabled, the second converter222may generate the second output clock signal CKOB by converting the second global clock signal GCKB. When the local enable signal LEN is disabled, the second converter222might not generate the second output clock signal CKOB from the second global clock signal GCKB.

The second converter222may include a second inverter222-1, a second resistor222-2, and a second pass gate222-3. An input terminal of the second inverter222-1may be an input terminal A2 of the second converter222and may receive the second global clock signal GCKB. The second inverter222-1may invert and drive the second global clock signal GCKB. One end of the second resistor222-2may be coupled to the input terminal of the second inverter222-1. The second pass gate222-3may be coupled between the other end of the second resistor222-2and an output terminal of the second inverter222-1. The output terminal of the second inverter222-1may be an output terminal B2 of the second converter222. The second pass gate222-3may receive the local enable signal LEN. When the local enable signal LEN is enabled to a high logic level and the complementary signal LENB is disabled to a low logic level, the second pass gate222-3may activate a feedback loop that sequentially couples the output terminal of the second inverter222-1, the second resistor222-2, and the input terminal of the second inverter222-1, by coupling the output terminal of the second inverter222-1to the other end of the second resistor222-2. When the local enable signal LEN is disabled to a low logic level and the complementary signal LENB is enabled to a high logic level, the second pass gate222-3may deactivate the feedback loop by electrically separating the output terminal of the second inverter222-1from the other end of the second resistor222-2. The second converter222may have substantially the same construction as the first converter221and may perform substantially the same function as the first converter221.

The common mode setting circuit223may set the voltage levels of the first and second output nodes N1 and N2 as the common mode voltage level by receiving the common mode enable signal CEN. The common mode setting circuit223may selectively couple the input terminal A1 and output terminal B1 of the first converter221based on the common mode enable signal CEN. The common mode setting circuit223may selectively couple the input terminal A2 and output terminal B2 of the second converter222based on the common mode enable signal CEN. When the common mode enable signal CEN is enabled, the common mode setting circuit223may equalize the voltage levels of the input terminal A1 and output terminal B1 of the first converter221by coupling the input terminal A1 and output terminal B1 of the first converter221and may set the voltage level of the first output node N1 as the common mode voltage level. Furthermore, the common mode setting circuit223may equalize the voltage levels of the input terminal A2 and output terminal B2 of the second converter222by coupling the input terminal A2 and output terminal B2 of the second converter222and may set the voltage level of the second output node N2 as the common mode voltage level. When the common mode enable signal CEN is disabled, the common mode setting circuit223may electrically separate the input terminal A1 and output terminal B1 of the first converter221and may electrically separate the input terminal A2 and output terminal B2 of the second converter222.

The common mode setting circuit223may include a first transistor223-1and a second transistor223-2. The first and second transistors223-1and223-2may be N channel MOS transistors. The first transistor223-1may be coupled between the input terminal A1 and output terminal B1 of the first converter221. A gate of the first transistor223-1may receive the common mode enable signal CEN. When the common mode enable signal CEN is enabled to a high logic level, the first transistor223-1may couple the input terminal A1 to output terminal B1 of the first converter221. The second transistor223-2may be coupled between the input terminal A2 and output terminal B2 of the second converter222. A gate of the second transistor223-2may receive the common mode enable signal CEN. When the common mode enable signal CEN is enabled to a high logic level, the second transistor223-2may couple the input terminal A2 to output terminal B2 of the second converter222.

The local clock tree220may further include a precharge circuit224. The precharge circuit224may receive the local enable signal LEN and may precharge the voltage levels of the input terminals A1 and A2 of the first and second converters221and222to opposite logic levels based on the local enable signal LEN. When the local enable signal LEN is disabled, the precharge circuit224may precharge the voltage levels of the input terminal A1 of the first converter221and the input terminal A2 of the second converter222to opposite logic levels. When the local enable signal LEN is enabled, the precharge circuit224may stop the precharge operation and might not drive the input terminals A1 and A2 of the first and second converters221and222. For example, the precharge circuit224may precharge the voltage level of the input terminal A1 of the first converter221to the first voltage V1 and may precharge the voltage level of the input terminal A2 of the second converter222to the second voltage V2. In an embodiment, the precharge circuit224may precharge the voltage level of the input terminal A1 of the first converter221to the second voltage V2 and may also precharge the voltage level of the input terminal A2 of the second converter222to the first voltage V1.

The precharge circuit224may include a first transistor224-1and a second transistor224-2. The first transistor224-1may be a P channel MOS transistor. A gate of the first transistor224-1may receive the local enable signal LEN. A source of the first transistor224-1may receive the first voltage V1. A drain of the first transistor224-1may be coupled to the input terminal A1 of the first converter221. When the local enable signal LEN is disabled to a low logic level, the first transistor224-1may precharge the voltage level of the input terminal A1 of the first converter221to the voltage level of the first voltage V1 by providing the first voltage V1 to the input terminal A1 of the first converter221. The second transistor224-2may be an N channel MOS transistor. A gate of the second transistor224-2may receive the complementary signal LENB of the local enable signal. A source of the second transistor224-2may receive the second voltage V2. A drain of the second transistor224-2may be coupled to the input terminal A2 of the second converter222. When the complementary signal LENB is enabled to a high logic level, the second transistor224-2may precharge the voltage level of the input terminal A2 of the second converter222to the voltage level of the second voltage V2 by providing the second voltage V2 to the input terminal A2 of the second converter222.

The precharge circuit224may further include a third transistor224-3and a fourth transistor224-4. The third transistor224-3may be an N channel MOS transistor. A gate and source of the third transistor224-3may receive the second voltage V2. A drain of the third transistor224-3may be coupled to the input terminal A1 of the first converter221. The fourth transistor224-4may be a P channel MOS transistor. A gate and source of the fourth transistor224-4may receive the first voltage V1. A drain of the fourth transistor224-4may be coupled to the input terminal A2 of the second converter222. Because the gate of the third transistor224-3receives the second voltage V2 and the gate of the fourth transistor224-4receives the first voltage V1, the third and fourth transistors224-3and224-4may continue to maintain an OFF state. The third and fourth transistors224-3and224-4may be provided in order to compensate for a mismatch between the first transistor224-1that precharges the voltage level of the input terminal A1 of the first converter221and the second transistor224-2that precharges the voltage level of the input terminal A2 of the second converter222, and the third and fourth transistors224-3and224-4may be components that may be selectively added.

The local clock tree220may further include a first CML buffer225-1, a second CML buffer225-2, a third inverter226-1, and a fourth inverter226-2. The first CML buffer225-1may be coupled between the first clock transmission line201and the first converter221. The first CML buffer225-1may buffer the first global clock signal GCK having the CML level and may provide a buffered signal LIN to the input terminal A1 of the first converter221. The first CML buffer225-1may receive the local enable signal LEN and may be selectively activated based on the local enable signal LEN. When the local enable signal LEN is enabled, the first CML buffer225-1may be activated and may provide the buffered signal LIN to the first converter221by buffering the first global clock signal GCK. When the local enable signal LEN is disabled, the first CML buffer225-1may be deactivated and may block the first global clock signal GCK from being provided to the first converter221.

The second CML buffer225-2may be coupled between the second clock transmission line202and the second converter222. The second CML buffer225-2may buffer the second global clock signal GCKB having the CML level and may provide a buffered signal LINB to the input terminal A2 of the second converter222. The second CML buffer225-2may receive the local enable signal LEN and may be selectively activated based on the local enable signal LEN. When the local enable signal LEN is enabled, the second CML buffer225-2may be activated and may provide the buffered signal LINB to the second converter222by buffering the second global clock signal GCKB. When the local enable signal LEN is disabled, the second CML buffer225-2may be deactivated and may block the second global clock signal GCKB from being provided to the second converter222.

The third inverter226-1may be coupled to the first output node N1 and/or output terminal B1 of the first converter221and may output the first output clock signal CKO by inverting and driving the output signal of the first converter221. The fourth inverter226-2may be coupled to the second output node N2 and/or output terminal B2 of the second converter222and may output the second output clock signal CKOB by inverting and driving the output signal of the second converter222. The local clock tree220may further include a first capacitor227-1and a second capacitor227-2. The first capacitor227-1may be coupled between an output terminal of the first CML buffer225-1and the input terminal A1 of the first converter221. The second capacitor227-2may be coupled between an output terminal of the second CML buffer225-2and the input terminal A2 of the second converter222.

FIGS.4A,4B, and4Care diagrams illustrating an operation of the clock distribution network200according to an embodiment of the present technology. An operation of the clock distribution network200according to an embodiment of the present technology will be described as follows with reference toFIGS.2to4C.FIG.4Amay illustrate an operation of the clock distribution network200in the interval in which the clock enable signal CKEN has been disabled. The interval in which the clock enable signal CKEN has been disabled may be a deactivation interval or a partial enable interval of the clock distribution network200. When the clock enable signal CKEN is disabled, all of the global enable signal GEN, the local enable signal LEN, and the common mode enable signal CEN may be disabled. Both the first and second global buffers221and222of the global clock tree210may be OFF, and the first CML buffer225-1, second CML buffer225-2, first pass gate221-3, and second pass gate222-3of the local clock tree220may also be OFF. The first and second transistors223-1and223-2of the common mode setting circuit223may also be OFF. The first and second transistors224-1and224-2of the precharge circuit224may be ON. The first transistor224-1may precharge the voltage level of the input terminal A1 of the first converter221to the first voltage V1, and the second transistor224-2may precharge the voltage level of the input terminal A2 of the second converter222to the second voltage V2. The first inverter221-1may precharge the voltage level of the output terminal B1 of the first converter221and/or the first output node N1 to the second voltage V2 according to the voltage level of the input terminal A1 of the first converter221. The second inverter221-2may precharge the voltage level of the output terminal B2 of the second converter222and/or the second output node N2 to the first voltage V1 according to the voltage level of the input terminal A2 of the second converter222. Accordingly, the voltage levels of each of the input terminals A1 and A2 of the first and second converters221and222, the first and second output nodes N1 and N2, and the first and second output clock signals CKO and CKOB may be maintained at opposite logic levels.

FIG.4Bmay illustrate an operation of the clock distribution network200in the interval in which the clock enable signal CKEN has been enabled and the local enable signal LEN and the common mode enable signal CEN have been enabled, but the global enable signal GEN has been disabled. The interval in which the local enable signal LEN and the common mode enable signal CEN have been enabled and the global enable signal GEN has been disabled may be a wake-up interval and/or partial activation interval of the clock distribution network200. In the wake-up interval, both the first and second global buffers211and212of the global clock tree210may maintain the OFF state. The first and second transistors224-1and224-2of the precharge circuit224of the local clock tree220may be OFF, and the precharge states of the input terminals A1 and A2 of the first and second converters221and222may be released. All of the first CML buffer225-1, the second CML buffer225-2, the first pass gate221-3, the second pass gate222-3, and the first and second transistors223-1and223-2of the common mode setting circuit223may be ON. As the first and second transistors223-1and223-2be ON, the first transistor223-1may couple the input terminal A1 to output terminal B1 of the first converter221, and the second transistor223-2may couple the input terminal A2 to output terminal B2 of the second converter222. Because the input terminal A1 of the first converter221is in the state in which the input terminal A1 has been precharged to the first voltage V1 and the output terminal B2 of the second converter222is in the state in which the output terminal B2 has been precharged to the second voltage V2, the input terminal A1 and output terminal B1 of the first converter221may be coupled, and the voltage levels of the input terminal A1 and output terminal B1 of the first converter221may be equalized at the common mode voltage level VCM. Likewise, because the input terminal A2 of the second converter222is in the state in which the input terminal A2 has been precharged to the second voltage V2 and the output terminal B2 of the second converter222is in the state in which the output terminal B2 has been precharged to the first voltage V1, the input terminal A2 and output terminal B2 of the second converter222may be coupled, and the voltage levels of the input terminal A2 and output terminal B2 of the second converter222may be equalized at the common mode voltage level VCM. Furthermore, the voltage levels of the first and second output clock signals CKO and CKOB may also be equalized at the common mode voltage level VCM.

FIG.4Cmay illustrate an operation of the clock distribution network200in the interval in which the local enable signal LEN and the global enable signal GEN have been enabled and the common mode enable signal CEN has been disabled. The interval in which the global enable signal GEN has been enabled and the common mode enable signal CEN has been disabled may be a full activation interval of the clock distribution network200. When the global enable signal GEN is enabled, both the first and second global buffers211and212of the global clock tree210may be ON, the first global buffer211may generate the first global clock signal GCK, and the second global buffer212may generate the second global clock signal GCKB. The first CML buffer225-1of the local clock tree220may buffer the first global clock signal GCK and may provide the buffered signal LIN to the first converter221. The second CML buffer225-2of the local clock tree220may buffer the second global clock signal GCKB and may provide the buffered signal LINB to the second converter222. Because the input terminals A1 and A2 of the first and second converters221and222are in the state in which the voltage levels of the input terminals A1 and A2 have been set as the common mode voltage level, the voltage levels of the input terminals A1 and A2 of the first and second converters221and222may be rapidly changed to opposite logic levels according to the logic levels of the buffered signals LIN and LINB. The first converter221may convert the voltage level of the buffered first global clock signal to the CMOS level, and the second converter222may convert the voltage level of the buffered second global clock signal to the CMOS level. At this time, because the output terminals B1 and B2 of the first and second converters221and222are also in the state in which the voltage levels of the output terminals B1 and B2 have been set as the common mode voltage level, the voltage levels of the output terminals B1 and B2 of the first and second converters221and222may also be rapidly changed to different logic levels. The third inverter226-1may generate the first output clock signal CKO by inverting and driving a signal that is output by the output terminal B1 of the first converter221. The fourth inverter226-2may generate the second output clock signal CKOB by inverting and driving a signal that is output by the output terminal B2 of the second converter222.

FIG.5Ais a waveform diagram illustrating an operation of a common clock distribution network.FIG.5Bis a waveform diagram illustrating an operation of the clock distribution network200according to an embodiment of the present technology. Referring toFIG.5A, in the common clock distribution network, when a global clock tree and a local clock tree are deactivated, first and second global clock signals GCK′ and GCKB′ may be maintained at a high logic level, and the voltage levels of input terminals A1′ and A2′ of converters of the local clock tree might not be defined. In the common clock distribution network, the global clock tree and the local clock tree may be simultaneously enabled and the first and second global clock signals GCK′ and GCKB′ may be generated. However, it may take a long time for the amplitudes of the input terminals A1′ and A2′ of the converters to converge. Accordingly, while the amplitudes of the input terminals A1′ and A2′ are converging, output clock signals CKO′ and CKOB′ might not toggle according to the first and second global clock signals GCK′ and GCKB′ but may be fixed at opposite levels. When the amplitudes of the input terminals A1′ and A2′ of the converters have converged, the output clock signals CKO′ and CKOB′ may toggle in a normal state in a similar manner as the first and second global clock signals GCK′ and GCKB′. Accordingly, the common clock distribution network may require a long wake-up time tWU′, and operational reliability of a semiconductor device including the common clock distribution network may be degraded.

Referring toFIG.5B, in the clock distribution network200according to an embodiment of the present technology, when the global clock tree210is deactivated and the local clock tree220is deactivated or partially activated, the precharge circuit224may precharge the voltage levels of the input terminals A1 and A2 of the first and second converters221and222to opposite logic levels. When the clock enable signal CKEN is enabled, the local enable signal LEN may be enabled before the global enable signal GEN is enabled. When the local enable signal LEN is enabled, the voltage levels of the input terminals A1 and A2 of the first and second converters221and222and the output terminals B1 and B2 of the first and second converters221and222may be set as the common mode voltage level. The first and second CML buffers225-1and225-2may be activated based on the local enable signal LEN, but the first and second global clock signals GCK and GCKB might not be toggled. Accordingly, the voltage levels of the buffered signals LIN and LINB may be set as the common mode voltage level according to the voltage levels of the input terminals A1 and A2 of the first and second converters221and222.

Thereafter, when the global enable signal GEN is enabled, the first and second global clock signals GCK and GCKB may be generated, and the voltage levels of the buffered signals LIN and LINB and the input terminals A1 and A2 of the first and second converters221and222may be changed from the common mode voltage level to a high logic level or a low logic level so that the amplitudes of the input terminals A1 and A2 of the first and second converters221and222may be rapidly converged. Accordingly, the first and second output clock signals CKO and CKOB that have been balanced between a high logic level and a low logic level can be rapidly generated from the output terminals B1 and B2 of the first and second converters221and222. The clock distribution network200according to an embodiment of the present technology may have a very short wake-up time tWU, and performance of a semiconductor device including the clock distribution network200can be improved.

FIG.6is a diagram illustrating a construction of a clock distribution network300according to an embodiment of the present technology. The clock distribution network300may be applied as the clock distribution network122as illustrated inFIG.1. Referring toFIG.6, the clock distribution network300may include a global clock tree310, a local clock tree320, and a wake-up control circuit330. The global clock tree310may include first and second global buffers311and312and may generate first and second global clock signals GCK and GCKB by receiving first and second input clock signals CKI and CKIB. The local clock tree320may receive the first and second global clock signals GCK and GCKB and may generate first and second output clock signals CKO and CKOB. The local clock tree320may include a first converter321, a second converter322, a common mode setting circuit323, a precharge circuit324, a first CML buffer325-1, and a second CML buffer325-2. The clock distribution network300may have substantially the same construction as the clock distribution network200, illustrated inFIG.2, except for the common mode setting circuit323of the local clock tree320. The same components as those of the clock distribution network200inFIG.2are assigned reference numerals similar to those of the clock distribution network200inFIG.2, and a description of the same components has been omitted.

The common mode setting circuit323may receive a common mode enable signal CEN and may set the voltage levels of input terminals A1 and A2 of the first and second converters321and322as a common mode voltage level based on the common mode enable signal CEN. When the common mode setting circuit323sets the voltage levels of the input terminals A1 and A2 of the first and second converters321and322as the common mode voltage level, the voltage levels of the first and second output nodes N1 and N2 may also be set as the common mode voltage level by the first and second converters321and322. When the common mode enable signal CEN is enabled, the common mode setting circuit323may set each of the voltage level of the input terminal A1 of the first converter321and the voltage level of the input terminal A2 of the second converter322as the common mode voltage level. When the common mode enable signal CEN is disabled, the common mode setting circuit323may stop setting the voltage levels of the input terminals A1 and A2 of the first and second converters321and322as the common mode voltage level.

The common mode setting circuit323may include a first three-state inverter323-1and a second three-state inverter323-2. The first three-state inverter323-1may receive the common mode enable signal CEN and a complementary signal CENB as a control signal. An input terminal and output terminal of the first three-state inverter323-1may be coupled to the input terminal A1 of the first converter321in common. When the common mode enable signal CEN is enabled to a high logic level and the complementary signal CENB is disabled to a low logic level, the first three-state inverter323-1may set the voltage level of the input terminal A1 of the first converter321as the common mode voltage level by equalizing the voltage level of the input terminal A1 of the first converter321. The second three-state inverter323-2may receive the common mode enable signal CEN and the complementary signal CENB as a control signal. An input terminal and output terminal of the second three-state inverter323-2may be coupled to the input terminal A2 of the second converter322in common. When the common mode enable signal CEN is enabled to a high logic level and the complementary signal CENB is disabled to a low logic level, the second three-state inverter323-2may set the voltage level of the input terminal A2 of the second converter322as the common mode voltage level by equalizing the voltage level of the input terminal A2 of the second converter322.

FIG.7is a diagram illustrating a construction of a semiconductor device400according to an embodiment of the present technology. The semiconductor device400may be applied as the second semiconductor device120as illustrated inFIG.1. Referring toFIG.7, the semiconductor device400may include a clock reception circuit410, a first global clock generation circuit421, a second global clock generation circuit422, a plurality of local clock generation circuits431,432, and433, a plurality of data input/output circuits441and442, a strobe transmission circuit450, and a command address reception circuit460. The first and second global clock generation circuits421and422may constitute a global clock tree. The plurality of local clock generation circuits431,432, and433may constitute a local clock tree. The clock reception circuit410, the first and second global clock generation circuits421and422, and the plurality of local clock generation circuits431,432, and433may constitute a clock distribution network. The clock reception circuit410may receive the system clock signal SCK and the complementary signal SCKB. The clock reception circuit410may generate a reference clock signal pair CK and CKB by differentially amplifying the system clock signal SCK and the complementary signal SCKB. The reference clock signal pair CK and CKB may be provided to the first and second global clock generation circuits421and422, respectively.

The first global clock generation circuit421may receive the reference clock signal pair CK and CKB from the clock reception circuit410and may generate a first global clock signal pair DCK and DCKB by buffering the reference clock signal pair CK and CKB. Through a first clock transmission line401, the first global clock generation circuit421may distribute and transmit the first global clock signal pair DCK and DCKB to the plurality of local clock generation circuits431,432, and433that are coupled to the data input/output circuits441and442and the strobe transmission circuit450. The first global clock signal pair DCK and DCKB may be signals that swing at the CML level and may be a data clock signal pair.

The second global clock generation circuit422may receive the reference clock signal pair CK and CKB from the clock reception circuit410and may generate a second global clock signal pair CCK and CCKB by buffering the reference clock signal pair CK and CKB. The second global clock generation circuit422may distribute and transmit the second global clock signal pair CCK and CCKB to the command address reception circuit460through a second clock transmission line402. The second global clock signal pair CCK and CCKB may be signals that swing at the CML level or the CMOS level and may be a command clock signal pair. In an embodiment, the second global clock generation circuit422may generate the second global clock signal pair CCK and CCKB by dividing the reference clock signal pair CK and CKB. The second global clock signal pair CCK and CCKB may have a lower frequency than the first global clock signal pair DCK and DCKB.

The local clock generation circuit431may be coupled to the data input/output circuit441. The local clock generation circuit431may receive the first global clock signal pair DCK and DCKB that is transmitted through the first clock transmission line401. The local clock generation circuit431may generate the local clock signal pair CKO1 and CKO1B by converting the first global clock signal pair DCK and DCKB that swings at the CML level to a signal that swings at the CMOS level. The local clock generation circuit431may provide the local clock signal pair CKO1 and CKO1B to the data input/output circuit441. The semiconductor device400may further include a buffer471in order to buffer the local clock signal pair CKO1 and CKO1B that is transmitted from the local clock generation circuit431to the data input/output circuit441. The data input/output circuit441may include a data receiver RX and a data transmitter TX. The data receiver RX and the data transmitter TX may receive the local clock signal pair CKO1 and CKO1B, respectively, from the local clock generation circuit431. The data receiver RX and the data transmitter TX may be coupled in common to a data bus through which data DQ1 is transmitted. The data receiver RX may receive the data DQ1 that is transmitted through the data bus, in synchronization with the local clock signal pair CKO1 and CKO1B. The data transmitter TX may transmit the data DQ1 through the data bus in synchronization with the local clock signal pair CKO1 and CKO1B.

The local clock generation circuit432may be coupled to the data input/output circuit442. The local clock generation circuit432may receive the first global clock signal pair DCK and DCKB that is transmitted through the first clock transmission line401. The local clock generation circuit432may generate a local clock signal pair CKO2 and CKO2B by converting the first global clock signal pair DCK and DCKB that swings at the CML level to a signal that swings at the CMOS level. The local clock generation circuit432may provide the local clock signal pair CKO2 and CKO2B to the data input/output circuit442. The semiconductor device400may further include a buffer472in order to buffer the local clock signal pair CKO2 and CKO2B that is transmitted from the local clock generation circuit432to the data input/output circuit442. The data input/output circuit442may include a data receiver RX and a data transmitter TX. The data receiver RX and the data transmitter TX may receive the local clock signal pair CKO2 and CKO2B, respectively, from the local clock generation circuit432. The data receiver RX and the data transmitter TX may be coupled, in common, to a data bus through which data DQ2 is transmitted. The data receiver RX may receive the data DQ2 that is transmitted through the data bus, in synchronization with the local clock signal pair CKO2 and CKO2B. The data transmitter TX may transmit the data DQ2 through the data bus in synchronization with the local clock signal pair CKO2 and CKO2B. In an embodiment, the data input/output circuit442may be an extension data input/output circuit. Bandwidth extension data DQE or DQX may be transmitted and received through the extension data input/output circuit. The bandwidth extension data DQE or DQX may be added, or a different type of a data signal may be added in order to extend the data bandwidth of the semiconductor device400.

The local clock generation circuit433may be coupled to the strobe transmission circuit450. The local clock generation circuit433may receive the first global clock signal pair DCK and DCKB that is transmitted through the first clock transmission line401. The local clock generation circuit433may generate a local clock signal pair CKO3 and CKO3B by converting the first global clock signal pair DCK and DCKB that swings at the CML level to a signal that swings at the CMOS level. The local clock generation circuit433may provide the local clock signal pair CKO3 and CKO3B to the strobe transmission circuit450. The semiconductor device400may further include a buffer473in order to buffer the local clock signal pair CKO3 and CKO3B that is transmitted from the local clock generation circuit433to the strobe transmission circuit450. The strobe transmission circuit450may include a strobe transmitter TX. The strobe transmitter TX may receive the local clock signal pair CKO3 and CKO3B from the local clock generation circuit433. The strobe transmitter TX may be coupled to a strobe bus through which data strobe signals RCK and RCKB are transmitted. The data strobe signals RCK and RCKB may be synchronized with the data DQ1, DQ2, DQE, or DQX that are transmitted through the data transmitters TX. The strobe transmitter TX may generate the data strobe signals RCK and RCKB from the local clock signal pair CKO3 and CKO3B and may transmit the data strobe signals RCK and RCKB through the strobe bus.

The command address reception circuit460may receive the second global clock signal pair CCK and CCKB from the second global clock generation circuit422through the second clock transmission line402. The command address reception circuit460may be coupled to a command address bus through which the command address signal CA is transmitted. The command address reception circuit460may receive the command address signal CA and may latch the command address signal CA in synchronization with the second global clock signal pair CCK and CCKB. The semiconductor device400may further include a buffer474in order to buffer the second global clock signal pair CCK and CCKB that is provided from the second global clock generation circuit422to the command address reception circuit460.

The data input/output circuit441and442and the strobe transmission circuit450may be circuits that operate at a high speed. Accordingly, although the semiconductor device400operates in the low power mode or a standby mode in which a data input/output operation is not performed, the clock distribution network having a relatively long wake-up time needs to maintain an activation state without being deactivated. Accordingly, in the low power mode or the standby mode of the semiconductor device400, the data input/output circuits441and442, the strobe transmission circuit450, and the buffers471,472, and473may be OFF, but the first global clock generation circuit421and the plurality of local clock generation circuits431,432, and433need to maintain an ON state. Accordingly, power consumption of the semiconductor device400may be increased due to the components that maintain the ON state. However, the clock distribution network having a reduced wake-up time may be deactivated in the low power mode or standby mode of the semiconductor device400. In the low power mode or standby mode of the semiconductor device400, the first global clock generation circuit421and the plurality of local clock generation circuits431,432, and433may also be OFF. Accordingly, components that maintain the ON state can be greatly reduced, and power consumption of the semiconductor device400can be dramatically reduced.

A person skilled in the art to which the present disclosure pertains can understand that the present disclosure may be carried out in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all aspects, not limitative. The scope of the present disclosure is defined by the claims to be described below rather than the detailed description, and it should be construed that the meaning and scope of the claims and all changes or modified forms derived from the equivalent concept thereof are included in the scope of the present disclosure.