Patent ID: 12261617

DETAILED DESCRIPTION

The present disclosure relates to an analog-to-digital converter (ADC) system that can be calibrated without requiring an external reference, such as can include using one or more internal references.

An ADC system may receive an analog input signal, such as a current or voltage signal. The ADC system can generate a digital output signal corresponding to or representing the analog input signal. The resulting digital output signal value may be used in a variety of calculations or operations in the digital domain. It may be desirable for an ADC system to be calibrated, such as to an absolute standard. With calibration, for a given digital output signal value, the corresponding absolute analog input signal value can be determined. It may be desirable for an ADC system to be calibrated to a relative standard. When calibrated to a relative standard, for a given analog input signal value, the digital output signal value is consistent across multiple measurements over time. Absolute calibration or relative calibration can help improve the accuracy or precision of a measurement. Such improved accuracy may be desired to better understand past events or better predict future events.

A relative calibration may use a consistent calibration reference having a consistent or substantially consistent analog signal value. The consistent calibration reference may not have a specified, measured, or calibrated absolute value, but may be consistent or vary only within an acceptable range over time. In this way, through periodic or other repeated measurements of the consistent calibration reference, an ADC system can adjust to generate the same digital output signal value for the consistent calibration reference value. In an example, a bandgap reference circuit may be used to provide a consistent calibration reference, due to the bandgap reference's stability over time and at various operating conditions, such as temperature.

An absolute calibration may use an absolute calibration reference of a specified, measured, or calibrated absolute analog signal value, or within a certain tolerance of an absolute analog signal value. The absolute calibration reference may be generated by a system that is capable of producing a specified absolute analog signal value of a given tolerance. The absolute calibration reference may be generated by measuring the absolute value of a given analog signal contemporaneously or near in time with the calibration measurement of the given analog signal value by the ADC system. Following the absolute measurement and calibration measurement, the absolute measurement value can be used to calibrate the ADC system. The absolute calibration reference may also be generated by measuring the absolute value of an analog signal that is believed to be consistent over time, such as a consistent calibration reference. Then, the consistent calibration reference can be considered to be an absolute calibration reference having the measured absolute value.

An ADC system may include one or more consistent calibration references, such as bandgap references, that are generally or substantially consistent over time, over temperature, and over other variations. The calibration reference may provide a relative calibration due to its consistency. Or, the calibration reference may be configured to have a specific signal value and may therefore provide an absolute calibration or quasi-absolute calibration. The ADC system may undergo a factory characterization while the ADC system is in a factory characterization mode, such as during manufacturing or after manufacturing. The factory characterization mode can be used to determine an absolute value of the calibration references, and to allow for absolute calibration of the ADC system. The factory characterization mode may be completed once in the life of the ADC system, or multiple times. The factory characterization may improve the accuracy of the ADC system. For example, the factory characterization may provide an accuracy greater than an ADC system that has not undergone a factory characterization to measure the absolute value of the ADC system's internal references.

During the factory characterization mode, the ADC system may supply the calibration references for measuring by a precision external measurement device. The calibration references may be provided through temporarily borrowed pins or multi-purpose test pins such as to decrease the number of pins on the ADC system100.

FIG.1is a schematic drawing of an example of portions of an ADC system100. In the example ofFIG.1, the ADC system100may include a bandgap voltage generation circuit120, an internal ADC130, a processor160, a memory170, a first multiplexer140, and a second multiplexer142. The ADC system100may include a number of external pins such as a voltage input pin102, test pin104, ADC input pin106, communication bus connections108, digital output pin110, and ground pin112.

The bandgap voltage generation circuit120may include as outputs a first reference voltage122and a second reference voltage124. The first reference voltage122and the second reference voltage124may be connected to the first multiplexer140and the second multiplexer142. The bandgap voltage generation circuit120may generate the first reference voltage122and the second reference voltage124using bandgap voltage generation circuitry.

The internal ADC130may include an analog signal input132and a digital signal output134. The internal ADC130may convert the analog signal input132into the digital signal output134using analog-to-digital conversion circuitry employing a conversion technique such as delta-sigma, successive approximation, flash, or integration. The analog signal input132may be selected by the second multiplexer142from a number of options such as the first reference voltage122, the second reference voltage124, or the ADC input pin106. The digital signal output134may include a number of bits for providing a given resolution, such as 8, 10, 12, 14, 16, or 32 bits. The digital signal output134may have a precision equaling the bit resolution of the internal ADC130, or the digital signal output134may have a precision that is less than the bit resolution of the internal ADC130. In an example, the internal ADC130may be a differential ADC that compares the analog signal input132to a reference voltage. The reference voltage may be provided by a ground or neutral voltage, a supply voltage, or a dedicated ADC reference voltage. The input range of the analog signal input132may start at 0V, or may be offset to start above 0V, such as at 5V. The internal ADC130may be designed so that the upper range of the analog signal input132may take on any value, such as 5V, 10V, 20V, or 100V. The input range of the ADC may be 0V to 3.63V.

The processor160may be connected to the digital signal output134of the internal ADC130and may be connected to the communication bus connections108. The processor160may receive the digital signal output134for further processing such as filtering, smoothing, calibrating, or adjusting. The processor160may send the raw value or a processed value of the digital signal output134using the communication bus connections108.

The memory170may include one or more storage mediums such as random access memory (RAM) or direct access memory. The one or more storage mediums may be volatile, losing their stored data when power is lost, or non-volatile, maintaining their stored data when power is lost. The one or more storage mediums may be read-only or writable. The memory170may be connected to the processor160for use in various processor operations, such as storing and retrieving information or data.

The processor160may also control the first multiplexer140and the second multiplexer142. The processor160may perform a number of other operations related to the analog-to-digital conversion of signals as well as operations unrelated to the analog-to-digital conversions, such as controlling the digital output pin110.

The first multiplexer140may have inputs including the first reference voltage122and the second reference voltage124. The first multiplexer140may provide a single selected input as the test voltage output150. The test voltage output150may be connected to the test pin104. The test voltage output150may be connected to the test pin104through a hardwire or permanent connection, or the test voltage output150may be connected to the test pin104temporarily using one or more multiplexers or switching devices. The first multiplexer140may be controlled by the processor160, hardwire internal circuitry, or an external device, such as through the communication bus connections108.

The second multiplexer142may have inputs including the first reference voltage122the second reference voltage124and the ADC input pin106. The second multiplexer142may provide a single selected output as the analog signal input132to the internal ADC130. The second multiplexer142may be controlled by the processor160, hardwire internal circuitry, or an external device, such as through the communication bus connections108.

The voltage input pin102may provide the operating voltage for one or more components of the ADC system100. The voltage input pin may accept a direct current (DC) voltage or an alternating current (AC) voltage. The voltage input pin102may accept a single voltage or a range of voltages. Internal circuitry of the ADC system100may convert the voltage from the voltage input pin102to one or more other voltages for use by the ADC system100. In an example, the voltage input pin102accepts a voltage range of 3-24V DC and converts this voltage to 3.3V DC and 5V DC.

The ground pin112may be connected to a ground or neutral of a power supply used to provide power to the voltage input pin102. The ground pin112may be connected to an earth ground, or the ground pin112may be floated or isolated from earth ground. The ground pin112may provide a reference value for various voltages in the ADC system100. The ground pin112may provide a return path for current entering the voltage input pin102.

The test pin104may be connected to an external measurement or test device, such as during a factory characterization mode, a factory calibration, or a test. The test pin104may be connected to the test voltage output150and may output various internal values, such as first reference voltage122and second reference voltage124, using internal switching and multiplexing devices. The test pin104may not be a physical pin, but rather one or more pins that are repurposed during calibration for testing purposes. In an example, the ADC input pin106or the digital output pin110may be repurposed as the test pin104during calibration or testing. The test pin104may provide the first reference voltage122and the second reference voltage124to an external voltage measurement device during a factory characterization mode to determine the absolute value of the first reference voltage122and the second reference voltage124to allow for absolute calibration of the ADC system100.

The ADC input pin106may be connected to an input of the second multiplexer142for routing to the analog signal input132of the internal ADC130when selected. The ADC input pin106may carry an analog signal of interest. The analog signal of interest may have a signal value, and the ADC system100may operate to measure and return a digital representation of the signal value of the analog signal of interest.

The communication bus connections108may include one or more pins for carrying an analog or digital communication signal. The communication may be according to a standardized communication format or may utilize a proprietary communication format. The communication bus connections108may utilize a serial form of digital communication. The communication bus connections108may be connected to another chip, circuit, or device.

FIG.2is a schematic drawing200of an example of portions of an ADC system100and an example of a portion of an external system260connected to the ADC system100. In the example ofFIG.2, the ADC system100may include a bandgap voltage generation circuit120, a first multiplexer140a test bond wire resistance252, a test bond wire inductance254, a ground bond wire resistance256, a ground bond wire inductance258, a test pin104, and a ground pin112. The ADC system100may be the same ADC system100depicted in part inFIG.1, or it may differ from the ADC system100ofFIG.1in one or more ways.

The external system260may be a measurement instrument or device, such as a voltage measurement device or a current measurement device. In an example, the external system260may be a precision voltage ADC or a precision voltmeter. The external system260may receive the first reference voltage122or the second reference voltage124through the first multiplexer140connected to the test pin104. The external system260may measure the voltage value on the test pin104and provide a digital representation of the voltage value on the test pin104. The digital representation of the voltage value may be stored in the memory170for retrieval during calibration. The external system260may have a precision or resolution that exceeds the precision or resolution desired from the ADC system100. The external system260having a precision exceeding the precision of the ADC system100may allow the ADC system100to be calibrated within the bit resolution of the internal ADC130. The external system260may have an ADC with a larger number of bits than the internal ADC130. The external system260may have a finer accuracy or resolution than the internal ADC130. A desired accuracy of the internal ADC130may be within 20 mV of the measured signal value, and the accuracy of the external system260may be within this accuracy, such as within 10 mV of the measured signal value.

The bandgap voltage generation circuit120may include a first bandgap current source222, a second bandgap current source224, a first bandgap voltage generation resistor226, and a second bandgap voltage generation resistor228.

The first bandgap current source222may be generated by the same bandgap voltage reference or different references. The low side of the first bandgap voltage generation resistor226and the second bandgap voltage generation resistor228may be connected to the ground pin112

The first bandgap current source222may be passed through the first bandgap voltage generation resistor226, and thereby generate a first reference voltage122on the high side of the first bandgap voltage generation resistor226. The first reference voltage122may be equal to the multiplication of the value of the first bandgap current source222and the value of the first bandgap voltage generation resistor226(V_Ref_1=R1*I_bg1).

The second bandgap current source224may be passed through the second bandgap voltage generation resistor228and thereby generate a second reference voltage124on the high side of the second bandgap voltage generation resistor228. The second reference voltage124may be equal to the multiplication of the value of the second bandgap current source224and the value of the second bandgap voltage generation resistor228(V_Ref_2=R2*I_bg2).

The first bandgap current source222, second bandgap current source224, first bandgap voltage generation resistor226, and second bandgap voltage generation resistor228, may be selected or tuned so that the first reference voltage122and the second reference voltage124have a selected value, or a value very close to a selected value. The first reference voltage122and the second reference voltage124may have the same or a similar value, or they may be selected to be of a different value. The first reference voltage122and the second reference voltage124can be selected to span a portion of the full-scale range of the internal ADC130, such as 10% to 90%, 50% to 80%, at least 20%, at least 40%, at least 60%, at least 80% or at least 90% of the full-scale range. In an example, the full-scale range of the internal ADC130is 0V to 3.63V and the first reference voltage122has a value of 0.5V and the second reference voltage124has a value of 2.0V.

In an example, the bandgap voltage generation circuit120may only generate a single voltage. In an example, the bandgap voltage generation circuit120may generate 3 or more voltages. The schematic drawing200ofFIG.2shows a method of generating the first reference voltage122and the second reference voltage124using bandgap voltage sources and resistors, but there may be a number of other ways of generating reference voltages. In an example, the bandgap voltage generation circuit120may be substituted for by another voltage generation circuit that can be configured to generate one or more references without using a bandgap reference.

The test bond wire resistance252and test bond wire inductance254may represent a resistance and an inductance respectively of the test pin104and the circuitry connecting the test pin104to the first multiplexer140. The ground bond wire resistance256, and ground bond wire inductance258may represent a resistance and an inductance respectively of the ground pin112and the circuitry connecting the ground pin112to the low sides of the first bandgap voltage generation resistor226and the second bandgap voltage generation resistor228.

The external system260may receive a value of or measure one or more of the test bond wire resistance252, test bond wire inductance254, ground bond wire resistance256, and ground bond wire inductance258and may adjust the digital representation of the voltage value on the test pin104to account for one or more of the inductance or resistance values. The external system260may adjust for one or more of a resistance or an inductance of test leads connecting the external system260to the ADC system100.

FIG.3is a schematic drawing300of an example of portions of an ADC system100. In the example ofFIG.3, the ADC system100may include a second multiplexer142, an ADC signal chain330, and an internal ADC130. The ADC signal chain330may include a first stage310, and one or more additional stages320.

The first stage310may act as an input stage for the internal ADC130. The first stage310may include a first input resistor312, and a first ground resistor314. The first input resistor312may be connected between the output of the second multiplexer142and an input of the one or more additional stages320. The first ground resistor314may be connected between ground on one end and between the first input resistor312and an input to the one or more additional stages320on the other end.

The first input resistor312may provide an input impedance for the ADC signal chain330to one or more of reduce a maximum current, reduce inrush current, provide a given resistor-capacitor time constant, or fulfill another design objective. The first ground resistor314may provide a resistive path to ground to one or more of provide a filtering effect, provide a drain path for voltage or charge, or fulfill another design objective.

The one or more additional stages320may be selected to include one or more isolation stages, one or more amplification stages, or one or more filtering stages. In an example, the one or more additional stages320may include capacitors that are charged through the first stage310during an ADC input cycle, and switches to isolate the one or more additional stages320from the first stage310after the ADC input cycle.

FIG.4is a schematic drawing of an example of portions of an ADC system100and an example of a portion of an external system260connected to the ADC system. In the example ofFIG.4, the ADC system100may include a first stage310of an ADC signal chain330, a second multiplexer142, a first multiplexer140, and portions of a bandgap voltage generation circuit120.

When the second multiplexer142selects the first reference voltage122to output to the first stage310, the value of the first reference voltage122may change. For example, the value of the first reference voltage122may change due to the first input resistor312and the first ground resistor314providing an additional path to ground for the first bandgap current source222. In an example, this additional path to ground may lower the total resistance to ground seen by the first bandgap current source222and therefore may lower the first reference voltage122. When the second multiplexer142selects the first reference voltage122, the first input resistor312and the first ground resistor314are connected in series with each other to ground, and as a group in parallel with the first bandgap voltage generation resistor226to ground. This may change the total resistance to ground seen by the first bandgap current source222from R1 to:

R⁢1⁢❘"\[LeftBracketingBar]"❘"\[RightBracketingBar]"⁢(R⁢3+R⁢4)=R⁢1*(R⁢3+R⁢4)R⁢1+R⁢3+R⁢4
The total resistance may decrease, and as a result, the value of the first reference voltage122may decrease, which may result in the value of the first reference voltage122measured by the internal ADC130being lower than an open circuit value of the first reference voltage122.

The factory characterization mode may compensate or adjust for this decrease in the value measured by the internal ADC130by connecting the internal ADC130to the first reference voltage122in parallel with the external system260. This may result in the value of the first reference voltage122measured by the external system260matching or more closely matching the value of the first reference voltage122measured by the internal ADC130. This may allow the ADC system100to achieve a calibration that is closer to an absolute calibration than would be achieved by measuring the first reference voltage122without connecting the first stage310of the internal ADC130in parallel with the external system260. The factory characterization mode may account for the variability in the construction of the reference voltages which may lead to varying values of the first reference voltage122and the second reference voltage124. The factory characterization mode may account for variability in the construction of the internal ADC130, which may lead to varying values of the first input resistor312and the first ground resistor314. The input impedance of the external system260may be large and therefore only have a minimal effect on the measured voltage.

FIG.5is an example of a graph500showing conversion of an analog voltage level to a digital representation, including an example of a theoretical measured curve and an example of a calculated ideal curve. In the example ofFIG.5, the internal ADC130may have a full-scale analog signal input132voltage range of 0V to 3V, and may be a 12-bit ADC having a digital signal output134range from 0 to 4095 bits, for a total of 2{circumflex over ( )}12 possible output values.

The ideal curve may represent a desired function of an ADC, may be linear or substantially linear, and may span the entire range of both analog signal input132and the digital signal output134. The ideal curve may convert an analog signal input132value of 0 volts to a digital signal output134value of 0 bits. The ideal curve may convert an analog signal input132value of 3 volts to a digital signal output134of 4095 bits. The ideal curve may convert analog signal input132value to digital signal output134according to the following ideal ADC curve equation:

Digital⁢Output⁢(Bits)=(2N-1)*(VinVfs)=4⁢0⁢9⁢5⁢(Vin3)
where N is the number of bits of the ADC, V_in is the input voltage, and V_fs is the full-scale resolution of the ADC. Because the digital signal output134value may be limited to integer values, the internal ADC130may one or more of round to the nearest number, take a floor value by discarding any remainder, or take a ceiling value by rounding up any remainder.

The measured may represent the output function of an ADC, such as the internal ADC130. The measured curve may be linear or substantially linear, or it may be non-linear due to one or more of an ADC design decision, an ADC design defect, an ADC manufacturing error, an ADC operating condition, or one or more other reasons. The measured curve may convert an analog signal input132value of 0 volts to a digital signal output134value that is not equal to 0 bits, such as approximately 400 bits in the example ofFIG.5. In an example, the internal ADC130may produce a digital signal output134value of 0 bits when the analog signal input132value is still greater than 0V but at the low-level saturation value of the internal ADC130, which may result in the internal ADC130not being able to measure values between 0V and the low-level saturation value. The measured curve may convert an analog signal input132value or 3 voltages to a digital signal output134value that is not equal to 4095 bits, such as approximately 3850 bits in the example ofFIG.5. In an example, the internal ADC130may produce a digital signal output134value of 4095 bits when the analog signal input132is less than 3V but at a high-level saturation value of the internal ADC130, which may result in the internal ADC130not being able to measure values between the high-level saturation value and 3V.

The resolution of the internal ADC130may be reduced due to a non-ideal nature of the measured curve. In the example ofFIG.5, the resolution may be reduced from 4096 different bit values to about 3450 different bit values (3850-400). In an example, the resolution of the internal ADC130may be increased due to a non-ideal nature of the measured curve, but the full-scale range may be decreased.

It may be desirable to correct or calibrate the measured ADC curve toward the ideal ADC curve. For example, it may be desirable to adjust a digital signal output134value of the internal ADC130for a given analog signal input132value towards the digital signal output134value that would have been given by an ideal ADC for the same digital signal output134value. In order to calibrate an ADC, it may be desirable to have one or more reference voltage values having a specified, measured, or calibrated value, or a value within a degree of error of a specified, measured, or calibrated value. If the ideal curve and the measured curve are linear or substantially linear, a first reference value and a second reference value may allow for a calibration of the measured curve towards the ideal curve. Each point on the measured line may be converted or mapped to a point on the ideal line to provide the corrected or calibrated output value.

A first internal reference voltage may be provided by the first reference voltage122and a second internal reference voltage may be provided by the second reference voltage124. The first reference voltage122may have a specified, measured, or calibrated first reference value V_Ref_1, which may be converted to a digital representation, D_Ref_1, according to the ideal ADC curve equation. The ideal ADC curve may pass through or transect D_Ref_1 and V_Ref_1 at point512. The second reference voltage124may have a specified, measured, or calibrated second reference value V_Ref_2 which may be converted to a digital representation, D_Ref_2, according to the ideal ADC curve equation. The ideal ADC curve may pass through or transect D_Ref_2 and V_Ref_2 at point514. The first reference voltage122may be applied to an analog signal input132of the internal ADC130to generate a first digital calibration value D_Cal_1 where the measured curve meets V_Ref_1 at point502. The second reference voltage124may be applied to an analog signal input132of the internal ADC130to generate a second digital calibration value D_Cal_2 where the measured curve meets V_Ref_2 at point504. An analog signal of interest provided to the ADC input pin106may be applied to an analog signal input132of the internal ADC130to generate a digital measured signal value D_Meas where the measured curve meats the signal value at point506. The measured ADC curve may pass through or transect502,504, and506and may be generally or substantially linear.

The digital measured signal value, D_Meas, may be converted to a corrected or calibrated digital signal value, D_Cor, such as by mapping D_Meas from the measured ADC curve at point506to the ideal ADC curve at point516. The correction may be performed by calculating at least one of an intercept correction or a slope correction between the measured ADC curve and the ideal ADC curve. The slope or gain correction, M, may be calculated according to the following equation:

M=DRef2-DRef1DCal2-DCal1
The intercept or offset correction, B, may be calculated according to the following equation:
B=DRef1−M*Dcal1
The corrected digital signal value, D_Cor, may be calculated according to the following equation:
Dcor=M*DMeas+B
The corrected digital signal value, D_Cor may be converted to an analog value of the measured signal of interest, V_Meas, using the following equation:

VMeas=VFS*DCor2N-1

The first reference voltage122and the second reference voltage124may have a specified, measured, or calibrated value that was measured during a factory characterization mode using the external system260. The specified, measured, or calibrated values may be stored in memory170for retrieval during the end-user operational mode during which the first digital calibration value and second digital calibration value are measured. In an example, the reference values are measured once during the life of the ADC system100during a factory characterization mode, and the calibration values are also measured once during the factory characterization mode. In an example, the calibration values are measured periodically during a post-manufacturing end-user operational mode to periodically calibrate the ADC. In an example, the calibration values are measured at least once every 1 microsecond, 5 microseconds, 10 microseconds, 50 microseconds, 100 microseconds, 200 microseconds, 500 microseconds, 1 millisecond, or 10 milliseconds. In an example the measuring of the calibration values occurs at least once for every time an analog signal of interest is measured. In an example, the measuring of the calibration values occurs at least once for every 10, 100, 1000, 5000, 10,000, or 100,000 times an analog signal of interest is measured. The calibration may be able to correct or cancel part or all of the 1/f noise of the internal ADC130. The calibration may be able to correct or cancel at least one of offset or gain drift over time. In an example, the internal ADC130may be adjusted in response to a calibration measurement to move the measured curve closer to the ideal curve.

The calibration calculations may be performed using software in a software-based processor. The calibration calculations may be performed, at least in part, in hardware-based calibration circuitry. In an example, the values measured during the factory characterization mode may be stored as floating point numbers and converted to digital values during calibration. In an example, the values measured during the factory characterization mode may be stored as digital numbers corresponding to the digital output values of the ideal ADC curve for the first reference voltage122and the second reference voltage124.

The calibration calculations may be performed in a bit resolution that is equal to the bit resolution of the internal ADC130. The calibration calculations may be performed in a bit resolution that is less than the bit resolution of the internal ADC130. Performing the calibration calculations in a lower bit resolution may one or more of conserve power or conserve hardware resources. In an example, the internal ADC130may have 12 bits of resolution, and the calibration calculations may be performed, at least in part, using one or more of 8-bit or 10-bit logic. The internal ADC130may have a lower effective bit resolution than the true bit resolution of the internal ADC130, such as may be due to the nonlinearity of a portion of the internal ADC130. In an example, the effective bit resolution of the internal ADC130may be bits and the true bit resolution may be 12 bits. The difference in effective bit resolution and true bit resolution may affect the bit resolution of the calibration calculations, such as by allowing for a lower bit resolution of calibration calculations without losing accuracy.

In an example, the ADC calibration may be performed with a single reference voltage, such as a first reference voltage122, and may result in one of an intercept or offset correction. In an example, the ADC calibration may be performed with more than two reference voltages, such as 2, 3, 4, 5, 6, or N voltages, where N represents an integer greater than 6. The ADC calibration performed with more than two reference voltages may use a regression technique, such as a linear regression to determine a measured line from the three or more calibration points. An ADC calibration performed with three or more reference voltages may not map a measured line to an ideal line, but may determine a measured curve and an ideal curve, where the measured curve and ideal curve may not be linear. The measured curve may transect each of the measured calibration points. In an example, the calibration may map a non-linear measured curve to a linear or substantially linear ideal curve. Calibration may be able to correct or adjust for a non-linearity in the internal ADC130.

FIGS.6A and6Bshow a laboratory-measured example of an uncalibrated ADC measurement600A inFIG.6Aand a measurement600B from an ADC calibrated using a calibration method of the present disclosure inFIG.6B. In the example ofFIGS.6A and6B, the analog signal input132of the internal ADC130from 0V to the full-scale voltage is shown on the horizontal axis, and the error in the measurement is shown on the vertical axis. The error in the measurement is calculated by subtracting the value of the input voltage from measured value returned by the internal ADC130.

In the uncorrected example ofFIG.6A, the error ranges from approximately 5 mV to 30 mV across the measurement range. In the corrected example ofFIG.6B, the error ranges from approximately −100 μV to 250 μV.FIG.6Bmay show measurement artifacts, such as aliasing, possibly due to the error value being below the measurement range of the laboratory instruments used.

FIG.7is a flow chart700showing an example of a method for operating portions of an ADC system, such as the ADC system100shown inFIG.1. At702—a measured first reference value can be received, such as corresponding to a first internal reference voltage of an ADC system measured by an external voltage measurement device. At704—a measured second reference value can be received, such as corresponding to a first internal reference voltage of an ADC system measured by an external voltage measurement device. At706—a first internal reference voltage can be applied to an input of an internal ADC to generate a resulting first calibration value. At708—a second internal reference voltage can be applied to an input of an internal ADC to generate a resulting second calibration value. At710—a measured signal value of an analog signal of interest can be applied to the input of the internal ADC. At712—a corrected value can be provided, such as corresponding to the measured signal value, using the first reference value, the second reference value, the first calibration value, the second calibration value, and the measured signal value. The shown order of steps is not intended to be a limitation on the order the steps are performed in. In an example, two or more steps may be performed simultaneously or at least partially concurrently.

702and704may involve receiving reference values that were measured by an external voltage measurement device such as during a factory characterization mode. The reference values may be stored in memory170within the ADC system100, and the values may be stored in a format corresponding to a voltage value, such as a floating point number, or a value corresponding to an ADC digital output value, such as an integer number of bits.

706,708, and710may occur during a post-manufacturing end-user operational mode, such as during a calibration of the ADC system100.712may be performed using software, or may be performed partially or completely on hardwire digital logic.712may involve mapping the mapping the measured signal value from a measured ADC curve towards an ideal ADC curve to obtain the corrected value.

FIG.8is a flow chart800showing an example of a method for operating portions of an ADC system, such as the ADC system100shown inFIG.1. At802—a reference data set can be obtained, wherein the reference data set includes a digital representation of one or more internal reference voltages as measured by a voltage measurement device during the factory characterization mode. At804—a measured signal value can be obtained, wherein the measured signal value is a digital representation of an analog signal of interest obtained by applying the analog signal of interest to an input of an ADC in the ADC system. At806—a calibration data set can be obtained, wherein the calibration data set includes a digital representation of the one or more internal reference voltages obtained by applying the one or more internal reference voltages to the input of the ADC. At808—the measured signal value can be mapped from a curve transecting the calibration data set to a curve transecting the reference data set to obtain a corrected value. The shown order of steps is not intended to be a limitation on the order the steps are performed in. In an example, two or more steps may be performed simultaneously or at least partially concurrently.

The reference data set obtained at802may be from values stored in memory170during a factory characterization mode. The calibration data set obtained at806and measured signal value obtained at804may be obtained during a post-manufacturing end-user operational mode. The reference data set obtained at802may have the same number of values as the calibration data set obtained at806, or the data sets may differ in size. In an example, the reference data set and the calibration data set may both contain two points, and the mapping at808may involve mapping the measured signal value from a substantially linear measured ADC curve transecting the two points in the calibration data set to a corresponding point on a substantially linear ideal ADC curve transecting the two points in the reference data set. The mapping may include calculating one or more of a slope or intercept difference between the measured ADC curve and the ideal ADC curve.

The systems, techniques, and methods described herein are believed to apply, at least in part, to a variety of ADC systems, such as voltage ADCs and current ADCs.

Each of the non-limiting aspects above can stand on its own or can be combined in various permutations or combinations with one or more of the other aspects or other subject matter described in this document.

The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to generally as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.

In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc., are used merely as labels, and are not intended to impose numerical requirements on their objects.

Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Such instructions can be read and executed by one or more processors to enable performance of operations comprising a method, for example. The instructions are in any suitable form, such as but not limited to source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like.

Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.