Patent ID: 12248360

DETAILED DESCRIPTION

FIG.1is a block diagram illustrating a storage system according to example embodiments.

Referring toFIG.1, a storage system1according to example embodiments may include a host100and a storage device200.

The storage device200may include storage media for storing data according to a request from the host100. As one example, the storage device200may include any one or any combination of a solid state drive (SSD), an embedded memory, or a removable external memory. When the SSD is provided in the storage device200, the storage device200may be a device conforming to a standard such as non-volatile memory express (NVMe), SATA, or SAS. When the embedded memory or the external memory is provided in the storage device200, the storage device200may be a device conforming to a standard such as universal flash storage (UFS), embedded multi-media card (eMMC), security digital (SD), or other protocol. The host100and the storage device200may each generate and transmit a packet according to an adopted standard protocol.

When a nonvolatile memory220of the storage device200includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device200may include various other types of nonvolatile memories. For example, a magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive memory (resistive RAM), or various other types of memories may be applied to the storage device200.

According to example embodiments, the host100may include host controller110, host memory120, and host interface111.

According to an example embodiment, the host controller110and the host memory120may be implemented as separate semiconductor chips. Alternatively, in example embodiments, the host controller110and the host memory120may be integrated in the same semiconductor chip. As one example, the host controller110may be any one of a plurality of modules provided in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory120may be an embedded memory provided in the application processor, or a nonvolatile memory or a memory module disposed outside the application processor.

The host controller110may have an operating system (OS) installed, and may control the overall operation of the host100by the operating system (OS). The operating system (OS) may be, for example, any one of Windows series, Unix series, Linux series, and the like. The host controller110may manage an operation of storing data (e.g., write data) of a buffer area121into the nonvolatile memory220or storing data (e.g., read data) of the nonvolatile memory220into the buffer area121.

The host interface111may provide a physical connection between the host100and the storage device200. The host interface21may be implemented with various types of interfaces, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), IEEE 1394, universal serial bus (USB), secure digital (SD) card, multi-media card (MMC), embedded multi-media card (eMMC), and compact flash (CF) card.

The host memory120may be used as a buffer memory, a working memory, or the like for temporarily storing data to be transmitted to the storage device200or data transmitted from the storage device200. For example, the host memory120may be implemented as a volatile memory such as DRAM or SRAM, or a nonvolatile memory such as PRAM or flash memory.

An application122and a storage driver124may be implemented in firmware or software, and may be loaded into the host memory120. Alternatively, the application122and/or the storage driver124may be implemented in hardware.

The application122may correspond to various types of applications installed on the host100and capable of accessing the storage device200. The application122may be an application that provides a retention mode activation request to the storage device200so that the storage device200performs a retention operation. The application122may provide the retention mode activation request including a retention level to the storage device200. For example, the application122may receive an input from a user and provide the retention mode activation request including a retention level to the storage device200. The retention level may be set by the user.

The storage driver124may access the storage device200at the request of the operating system or the application122. The storage driver124may convert the request of the application122into a command corresponding to the storage device200to access the storage device200.

The storage driver124may provide a retention mode command R_M_CMD including the retention level to the storage device200at the retention mode activation request provided from the application122. The retention mode command R_M_CMD may be a command conforming to the host interface111and a device interface211. The retention mode command R_M_CMD may be, for example, one of input/output commands such as a read command and a write command. The retention mode command R_M_CMD may be, for another example, one of vendor specific commands through which a manufacturer can define an operation. The retention mode command R_M_CMD according to example embodiments may be a vendor command which defines the retention operation based on the retention level.

The storage device200may include a storage controller210and the nonvolatile memory220.

The storage controller210may include the device interface211, a memory interface212, and a central processing unit (CPU)213. In addition, the storage controller210may further include the working memory214, a packet manager215, a buffer memory216, an error correction code (ECC) engine217, and an advanced encryption standard (AES) engine218.

The device interface211may transmit and receive a packet to and from the host100. A packet transmitted from the host100to the device interface211may include a command, data to be written to the nonvolatile memory220, and the like. A packet transmitted from the device interface211to the host100may include a response to the command, data read from the nonvolatile memory220, and the like. The memory interface212may transmit data to be written to the nonvolatile memory220to the nonvolatile memory220or may receive data read from the nonvolatile memory220. The memory interface212may be implemented to conform to standard conventions such as Toggle or ONFI.

The working memory214may operate under the control of the CPU213and may be used as a working memory, a buffer memory, a cache memory, or the like. For example, the working memory214may be implemented as a volatile memory such as DRAM or SRAM, or a nonvolatile memory such as PRAM or flash memory.

A flash transition layer (FTL)214amay be loaded into the working memory214. Data write and read operations for the nonvolatile memory220may be controlled by the CPU213executing the flash transition layer214a. The flash transition layer214amay perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation of converting a logical address received from the host into a physical address used to actually store data in the nonvolatile memory220. The wear-leveling function is a technique for preventing excessive deterioration of a specific block by allowing blocks in the nonvolatile memory220to be uniformly used. For example, the wear-leveling may be implemented through firmware technology that balances erase counts of physical blocks. The garbage collection function is a technique for securing usable capacity in the nonvolatile memory220by copying valid data of a block to a new block and erasing the existing block.

A retention module214bmay be implemented in firmware or software, and may be loaded into the working memory214. Alternatively, the retention module214bmay be implemented in hardware. The retention module214bmay perform the retention operation in response to the retention mode command R_M_CMD. The retention module214bmay perform the retention operation based on the retention level included in the retention mode command R_M_CMD. Accordingly, the retention module214bmay control the width of the threshold voltage distribution corresponding to data.

That is, in the storage system according to example embodiments, the retention operation may be performed by the user's request. The user may request the retention operation. For example, the retention operation may be requested based on the retention level or according to a situation of the storage system, such as a situation in which the storage system is left unattended for a long time.

The packet manager215may generate a packet according to a protocol of an interface negotiated with the host100or may parse various types of information from a packet received from the host100. In addition, the buffer memory216may temporarily store data to be written to the nonvolatile memory220or data read from the nonvolatile memory220. The buffer memory216may be provided inside the storage controller210, or alternatively, may be provided outside the storage controller210.

The ECC engine217may perform an error detection and correction function for read data read from the nonvolatile memory220. More specifically, the ECC engine217may generate parity bits for write data to be written to the nonvolatile memory220, and the generated parity bits may be stored in the nonvolatile memory220together with the write data. When data is read from the nonvolatile memory220, the ECC engine217may correct an error in the read data using parity bits read from the nonvolatile memory220together with the read data, and may output the read data in which the error has been corrected.

The AES engine218may perform, using a symmetric-key algorithm, any one or any combination of an encryption operation or a decryption operation for data inputted to the storage controller210.

FIG.2is an exemplary block diagram illustrating a nonvolatile memory according to example embodiments.

Referring toFIG.2, the nonvolatile memory220may include a controller222, a memory cell array223, a page buffer unit224, a voltage generator225, and a row decoder226. The nonvolatile memory220may further include the memory interface212shown inFIG.1, and may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

The controller222may control various operations of the nonvolatile memory220. The controller222may output various control signals in response to a command CMD and/or an address ADDR from the memory interface212. For example, the controller222may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array223may include a plurality of memory blocks BLK1to BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1to BLKz may include a plurality of memory cells. The memory cell array223may be connected to the page buffer unit224through bit lines BL, and may be connected to the row decoder226through word lines WL, string select lines SSL, and ground select lines GSL.

In an example embodiment, the memory cell array223may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference. In an example embodiment, the memory cell array223may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged along row and column directions.

The page buffer unit224may include a plurality of page buffers PB1to PBn (where n is an integer equal to or greater than 3), and the plurality of page buffers PB1to PBn may be connected respectively to the memory cells through the plurality of bit lines BL. The page buffer unit224may select at least one of the bit lines BL based on the column address Y-ADDR. The page buffer unit224may operate as a write driver or a sense amplifier depending on an operation mode. For example, during a program operation, the page buffer unit224may apply, to the selected bit line, a bit line voltage corresponding to data to be programmed. During a read operation, the page buffer unit224may sense data stored in the memory cell by sensing a current or voltage of the selected bit line.

The voltage generator225may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator225may generate a program voltage, a read voltage, a program verification voltage, an erase voltage, and the like as a word line voltage VWL.

The row decoder226may select one of the plurality of word lines WL and one of the plurality of string select lines SSL, based on the row address X-ADDR. For example, during a program operation, the row decoder226may apply a program voltage and a program verification voltage to the selected word line, and during a read operation, the row decoder226may apply a read voltage to the selected word line.

FIG.3is a diagram illustrating a 3D V-NAND structure according to example embodiments. When the nonvolatile memory220ofFIG.1is implemented as a 3D V-NAND type flash memory, a plurality of memory blocks BLK1to BLKz constituting the memory cell array223(seeFIG.2) of the nonvolatile memory220may each be represented by an equivalent circuit as shown inFIG.3.

The memory block BLK1shown inFIG.3represents a 3D memory block formed in a 3D structure on the substrate. For example, a plurality of memory NAND strings included in the memory block BLK1may be formed in a direction perpendicular to the substrate.

Referring toFIG.3, the memory block BLK1may include a plurality of memory NAND strings NS11to NS33connected between a common source line CSL and bit lines BL1, BL2, and BL3. The plurality of memory NAND strings NS11to NS33may each include a string select transistor SST, a plurality of memory cells MC1to MC8, and a ground select transistor GST. InFIG.3, it is illustrated that each of the plurality of memory NAND strings NS11to NS33includes eight memory cells MC1to MC8, but the present disclosure is not necessarily limited thereto.

The string select transistor SST may be connected to a string select line SSL1, SSL2, SSL3corresponding thereto. The plurality of memory cells MC1to MC8may be connected to corresponding gate lines GTL1to GTL8, respectively. The gate lines GTL1to GTL8may correspond to the word lines, and some of the gate lines GTL1to GTL8may correspond to dummy word lines. The ground select transistor GST may be connected to a ground select line GSL1, GSL2, GSL3corresponding thereto. The string select transistor SST may be connected to the bit line BL1, BL2, BL3corresponding thereto, and the ground select transistor GST may be connected to the common source line CSL.

The word line (e.g., WL1) at the same height may be connected in common, and the ground select lines GSL1, GSL2, and GSL3and the string select lines SSL1, SSL2, and SSL3may be separated from each other. InFIG.3, the memory block BLK1is shown to be connected to eight gate lines GTL1to GTL8and three bit lines BL1, BL2, BL3, but is not necessarily limited thereto.

FIG.4is a flowchart illustrating operation of a storage system according to example embodiments.

Referring toFIGS.1and4, the storage driver124may receive the retention mode activation request including a retention level (operation S110). The retention mode activation request including a retention level may be provided from the application122. The retention level may be a period in which data stored in the nonvolatile memory220is guaranteed. For example, a first retention level may indicate a first period, and a second retention level may indicate a second period longer than the first period. The period in which data is guaranteed may vary depending on the width of the threshold voltage distribution of valid data. In other words, the width of the threshold voltage distribution of valid data may vary depending on the retention level.

The storage driver124may issue the retention mode command R_M_CMD including the retention level in response to the retention mode activation request (operation S120). The storage driver124may provide the retention mode command R_M_CMD to the storage device200.

The storage device200may perform the retention operation in response to the retention mode command R_M_CMD (operation S130). The retention operation may be performed based on the retention level.

FIG.5is a flowchart illustrating a retention operation according to example embodiments. For example, the retention operation S130ofFIG.4may include the operations shown inFIG.5.

Referring toFIGS.1and5, the nonvolatile memory220may include at least one valid page and at least one free page. The retention module214bmay perform the retention operation in response to the retention mode command R_M_CMD.

The retention module214bmay read valid data from the valid page of the nonvolatile memory220(operation S132).

The retention module214bmay store the valid data read from the valid page of the nonvolatile memory220in the buffer memory216(operation S134).

The retention module214bmay program the valid data in the free page of the nonvolatile memory220based on the retention level included in the retention mode command R_M_CMD (operation S136). For example, the valid data read from the valid page of a first memory block may be written to the free page of a free block different from the first memory block.

When the number of the free pages is smaller than the number of the valid pages in the nonvolatile memory220, the retention module214bmay generate a free block by performing an erase operation on at least one memory block, and may program the valid data into the free page. Accordingly, invalid pages may be erased, resulting in a garbage collection effect.

In the nonvolatile memory220, as the program time increases, the width of the threshold voltage distribution may decrease and the retention performance may be improved. Accordingly, the retention module214bmay control the width of the threshold voltage distribution by, for example, controlling the program time based on the retention level, thereby improving the retention performance.

The retention module214bmay determine whether the valid page in operation S132is the last valid page (operation S138). If the valid page in operation S132is the last valid page, the retention operation may be terminated. On the other hand, if the valid page in operation S132is not the last valid page, the retention module214bmay perform operation S132on the next valid page (operation S139).

FIGS.6to8are diagrams illustrating a retention operation according to example embodiments.FIG.6is a diagram illustrating threshold voltage distribution of memory cells before a retention operation is performed.FIG.7is a diagram illustrating threshold voltage distribution of memory cells in which a retention operation has been performed based on a second retention level.FIG.8is a diagram illustrating threshold voltage distribution of memory cells in which a retention operation has been performed based on a first retention level. InFIGS.6to8, a horizontal axis represents the threshold voltage of memory cells, and a vertical axis represents the number of memory cells.

Referring toFIG.6, the memory cells included in the nonvolatile memory220(seeFIG.1) may be multi-level cells (MLC) that store 2 bits. However, example embodiments are not limited thereto, and the memory cells may be triple-level cells (TLC) or single-level cells (SLC). InFIG.6, a dotted line10represents an initial program threshold voltage distribution of the memory cells, and a solid line20represents a threshold voltage distribution that has changed over time.

The memory cells may have four states E, P1, P2, and P3. The four states may each be defined as a range of a threshold voltage Vth. According to two bits written to each memory cell, each memory cell may be programmed to have the threshold voltage Vth belonging to one of the four states E, P1, P2, and P3. The four states E, P1, P2, and P3may be identified using, for example, three read voltages having levels between four threshold voltage Vth ranges.

As time passes after the memory cells are programmed, the threshold voltage distribution of the memory cells may be changed due to physical characteristics of the memory cells or external factors. In particular, as time passes after the memory cells are programmed, a charge loss in which electrons trapped in a floating gate or tunnel oxide are emitted may occur, resulting in a change in the threshold voltage distribution. In addition, while repeating operations such as programming and erasing for the memory cells, the tunnel oxide may be deteriorated, so that the charge loss may further increase. The charge loss may reduce the threshold voltage. Accordingly, the threshold voltage distribution20may be shifted to the left compared to the initial program threshold voltage distribution10.

Referring toFIGS.7and8, threshold voltage distributions30and40of the memory cells in which the retention operation has been performed may be shifted to the right compared to the threshold voltage distribution20of the memory cells before the retention operation is performed.

The width of the threshold voltage distributions30and40of memory cells in which the retention operation has been performed may be smaller than the width of the threshold voltage distribution20of the memory cells before the retention operation is performed. Specifically, when the retention operation is performed based on the first retention level, as shown inFIG.8, the width of the threshold voltage distribution of the memory cells may be controlled to a second width W2. In addition, when the retention operation is performed based on the second retention level, as shown inFIG.7, the width of the threshold voltage distribution of the memory cells may be controlled to a first width W1.

The retention level may indicate a period in which the user wants the reliability of data stored in the nonvolatile memory to be guaranteed. The first retention level may be a first period, and the second retention level may be a second period longer than the first period. The second width W2of the threshold voltage distribution40of the memory cells in which the retention operation has been performed based on the first retention level may be greater than the first width W1of the threshold voltage distribution30of the memory cells in which the retention operation has been performed based on the second retention level. Accordingly, the valid data may be guaranteed for a longer period in the memory cells in which the retention operation has been performed based on the second retention level than in the memory cells in which the retention operation has been performed based on the first retention level.

That is, as the retention level increases, the width of the threshold voltage distribution of the memory cells in which the retention operation has been performed based on the retention level may decrease. As the retention level increases, the threshold voltage distribution of the memory cells in which the retention operation has been performed based on the retention level may become sharper.

FIGS.9and10are diagrams illustrating operation S136ofFIG.5.FIG.9is a diagram illustrating a method of programming valid data in a free page based on a second retention level.FIG.10is a diagram illustrating a method of programming valid data in a free page based on a first retention level. InFIGS.9and10, a horizontal axis represents time, and a vertical axis represents a program voltage used during the retention operation.

Referring toFIGS.1,9, and10, the retention module214bmay program valid data in a free page using, for example, the program voltage whose voltage level is changed in a stepwise manner based on the retention level. For example, the program voltage may be an incremental step pulse programming (ISPP) voltage whose voltage level increases in a stepwise manner.

Referring toFIGS.1and9, the retention module214bmay program valid data in a free page using a plurality of first program voltages Vpgm1to VpgmN. Each increment of the voltage level of the first program voltage Vpgm1to VpgmN may be changed by a first voltage level ΔVpgm1. The retention module214bmay apply each of the first program voltages Vpgm1to VpgmN and a verification voltage Vvfy1.

Referring toFIGS.1and10, the retention module214bmay program valid data in a free page using a plurality of second program voltages Vpgm1to VpgmM. Each increment of the voltage level of the second program voltage Vpgm1to VpgmM may be changed by a second voltage level ΔVpgm2The retention module214bmay apply each of the second program voltages Vpgm1to VpgmM and the verification voltage Vvfy2.

The first retention level may be a first period, and the second retention level may be a second period longer than the first period. For example, the second voltage level ΔVpgm2may be greater than the first voltage level ΔVpgm1, and the number of the second program voltages Vpgm1to VpgmM may be same as the number of the first program voltages Vpgm1to VpgmN. M may be same as N. For example, the second voltage level ΔVpgm2may be same as the first voltage level ΔVpgm1, and the number of the second program voltages Vpgm1to VpgmM may be smaller than the number of the first program voltages Vpgm1to VpgmN. M may be smaller than N.

Accordingly, memory cells in which the retention operation has been performed based on the first retention level may have, for example, the threshold voltage distribution40ofFIG.8, and the memory cells in which the retention operation has been performed based on the second retention level may have, for example, the threshold voltage distribution30ofFIG.7. That is, the first width W1(seeFIG.7) of the threshold voltage distribution of the memory cells in which the retention operation has been performed based on the second retention level may be smaller than the second width W2(seeFIG.8) of the threshold voltage distribution of the memory cells in which the retention operation has been performed based on the first retention level. Accordingly, the retention performance of the memory cells in which the retention operation has been performed based on the second retention level may be higher than that of the memory cells in which the retention operation has been performed based on the first retention level.

FIG.11is a block diagram illustrating a storage system according to example embodiments. For simplicity of description, differences fromFIG.1will be mainly described.

Referring toFIG.11, in a storage system2according to example embodiments, the storage controller210may further include a DRAM interface241. The storage controller210may exchange data with a DRAM240through the DRAM interface241.

The retention module214bmay perform the retention operation in response to the retention mode command R_M_CMD. Specifically, the retention module214bmay read valid data from the valid page of the nonvolatile memory220. The retention module214bmay store the valid data read from the valid page of the nonvolatile memory220in the DRAM240. The retention module214bmay program the valid data stored in the DRAM240into the free page of the nonvolatile memory220based on the retention level included in the retention mode command R_M_CMD. Accordingly, the retention module214bmay control the width of the threshold voltage distribution corresponding to an effective data value.

FIG.12is a block diagram illustrating a storage system according to example embodiments. For simplicity of description, differences fromFIG.1will be mainly described.FIGS.13,15, and17are flowcharts illustrating operation of the storage system ofFIG.12according to example embodiments.FIGS.14and16are block diagrams illustrating a register provided in the storage system ofFIG.12according to example embodiments.

Referring toFIGS.12and13, a storage system3according to example embodiments may further include a patrol read module214c, a register219, and a temperature sensor230.

The temperature sensor230may sense a temperature T of the nonvolatile memory220, the patrol read module214cmay periodically perform a patrol read operation, and the retention module214bmay count the number of errors occurred in the patrol read operation (operation S210).

The temperature sensor230may be connected to the nonvolatile memory220to sense the temperature T of the nonvolatile memory220. The temperature sensor230may provide the sensed temperature T to the retention module214b.

The patrol read module214cmay be implemented in firmware or software, and may be loaded into the working memory214. Alternatively, the patrol read module214cmay be implemented in hardware. The patrol read module214cmay perform the patrol read operation according to a set period. The set period may be, for example, a period set by a setting command provided from the host100.

The patrol read operation may indicate that the patrol read module214creads the valid data from all valid pages of the nonvolatile memory120by itself without receiving a read command from the host100. The patrol read module214cmay itself issue a read command and address, and according to the read command and address, may read the valid data from all valid pages of the nonvolatile memory120. At this time, the ECC engine217may perform an error detection and correction function on the valid data read from the valid page by the patrol read module214c. The retention module214bmay count the number of errors detected in the patrol read operation.

The retention module214bmay determine whether the temperature T of the nonvolatile memory220is greater than or equal to a set temperature Tth during a set time Pth or whether the number NOE of errors counted is greater than or equal to a set value Eth (operation S220). The set time Pth and the set value Eth may be, for example, a time and a value set by the setting command provided from the host100.

When the temperature T of the nonvolatile memory220is lower than the set temperature Tth during the set time Pth and the number NOE of errors counted is less than the set value Eth, the retention module214bmay go back to operation S210.

When it is determined that the temperature T of the nonvolatile memory220is greater than or equal to the set temperature Tth during the set time Pth or the number NOE of errors counted is greater than or equal to the set value Eth, the retention module214bmay determine the retention level (operation S230). The retention module214bmay determine the retention level based on the temperature T of the nonvolatile memory220maintained for the set time Pth or the number NOE of errors counted.

Referring toFIG.14, a plurality of tables219aand219bmay be stored in the register219. The plurality of tables219aand219bmay be, for example, tables stored by the setting command provided from the host100.

A first table219amay indicate retention levels Lr respectively corresponding to temperatures T of the nonvolatile memory220. A second table219bmay indicate the retention levels Lr respectively corresponding to the number NOE of errors that have occurred in the patrol read operation.

The retention module214bmay read the retention level depending on the temperature T of the nonvolatile memory220from the first table219a. The retention module214bmay read the retention level based on, for example, the average temperature of the temperature T of the nonvolatile memory220during the set time Pth. The retention module214bmay read the retention level depending on the number NOE of errors occurred in the patrol read operation from the second table219bto determine the retention level.

The retention module214bmay perform the retention operation based on the determined retention level (operation S240). The higher the temperature T of the nonvolatile memory220and the greater the number NOE of errors occurred in the patrol read operation, the more deterioration that may occur in the memory cells. Accordingly, the retention module214bmay control the width of the threshold voltage distribution corresponding to the valid data to be smaller as the temperature T of the nonvolatile memory220increases and the number NOE of errors occurred in the patrol read operation increases. The retention module214bmay control the width of the threshold voltage distribution corresponding to the valid data to be smaller by controlling the number of program voltages used in the retention operation, the program time, and/or the like. The retention module214bmay perform the retention operation described with reference toFIGS.6to10.

For example,FIG.7illustrates the threshold voltage distribution of the memory cells in which the retention operation has been performed based on a first retention level L1when the temperature T of the nonvolatile memory220is a first temperature T1, or the threshold voltage distribution of the memory cells in which the retention operation has been performed based on a first retention level L1′ when the number NOE of errors that have occurred in the patrol read operation is a first value NOE1. In this case,FIG.9shows a method in which the retention module214bprograms the valid data in the free page based on the first retention levels L1and L1′.FIG.7illustrates the threshold voltage distribution of the memory cells in which the retention operation has been performed based on a second retention level L2when the temperature T of the nonvolatile memory220is a second temperature T2, or the threshold voltage distribution of the memory cells in which the retention operation has been performed based on a second retention level L2′ when the number NOE of errors occurred in the patrol read operation is a second value NOE2. In this case,FIG.9shows a method in which the retention module214bprograms the valid data in the free page according to the second retention levels L2and L2′.

Referring toFIGS.7and8, the first temperature T1may be lower than the second temperature T2, and the first value NOE1may be less than the second value NOE2. The width W1of the threshold voltage distribution40of the memory cells in which the retention operation has been performed based on the second retention levels L2and L2′ may be smaller than the width W2of the threshold voltage distribution30of the memory cells in which the retention operation has been performed based on the first retention levels L1and L1′.

In addition, referring toFIGS.9and10, the retention module214bmay program the valid data into the free page using more program voltages as the temperature T of the nonvolatile memory220increases and/or the number NOE of errors occurred in the patrol read operation increases.

FIG.15is a block diagram illustrating an operation of a storage system according to example embodiments.

Referring toFIGS.12and15, the storage device200may be powered by received power (operation S310). The storage device200may receive a power-off period Pp from the host100(operation S320). That is, while the storage device200is powered on, the host100may receive the power-off period Pp during which the storage device200maintains a power-off state. The retention module214bmay determine whether the power-off period Pp of the storage device200is greater than or equal to a set power-off period Pp_th (operation S330). When the power-off period Pp of the storage device200is less than the set power-off period Pp_th, the flow may return to operation S310.

When it is determined that the power-off period Pp of the storage device200is greater than or equal to the set power-off period Pp_th, the retention module214bmay determine the retention level (operation S340). The retention module214bmay determine the retention level based on the power-off period Pp of the storage device200. For example, if the power-off period Pp is greater than or equal to first power-off period Ppf1, the retention level may be determined as a first retention level L1″. For example, if the power-off period Pp is greater than or equal to second power-off period Ppf2, the retention level may be determined as a second retention level L2″.

Referring toFIG.16, the register219may further include a third table219c. The third table219cmay be, for example, a table stored by the setting command provided from the host100.

The third table219cmay include the retention level Lr depending on the power-off period Pp of the storage device200. The retention module214bmay read the retention level depending on the power-off period Pp of the storage device200to determine the retention level.

The retention module214bmay perform the retention operation based on the determined retention level (operation S350). The longer the power-off period Pp of the storage device200, the more deterioration that may occur in the memory cells. Accordingly, as the power-off period Pp of the storage device200increases, the retention module214bmay control the width of the threshold voltage distribution corresponding to the valid data to be smaller. The retention module214bmay control the width of the threshold voltage distribution corresponding to the valid data to be smaller by controlling the number of program voltages used in the retention operation, the program time, and/or the like. The retention module214bmay perform the retention operation described with reference toFIGS.6to10.

For example,FIG.8illustrates the threshold voltage distribution of the memory cells in which the retention operation has been performed based on a first retention level L1″ when the power-off period Pp of the storage device200is a first power-off period Ppf1. In this case,FIG.10shows a method in which the retention module214bprograms the valid data in the free page based on the first retention level L1″.FIG.7illustrates the threshold voltage distribution of the memory cells in which the retention operation has been performed based on a second retention level L2″ when the power-off period Pp of the storage device200is a second power-off period Ppf2. In this case,FIG.9shows a method in which the retention module214bprograms the valid data in the free page based on the second retention level L2″.

Referring toFIGS.7and8, the width W1of the threshold voltage distribution40of the memory cells in which the retention operation has been performed based on the second retention level L2″ may be smaller than the width W2of the threshold voltage distribution30of the memory cells in which the retention operation has been performed based on the first retention level L1″.

In addition, referring toFIGS.9and10, the retention module214bmay program the valid data into the free page using more program voltages as the power-off period Pp of the storage device200increases.

FIG.17is a flowchart illustrating operation of a storage system according to still other example embodiments. For simplicity of description, the following description will focus on differences from the description with reference toFIG.15.

Referring toFIGS.12and17, the storage device200may be powered by received power (operation S310), and may receive a power-off period of the storage device200and a power-off period INF_P from the host100(operation S320).

The storage device200may calculate the power-off period Pp during which the storage device200maintains the power-off state by using the power-off period of the storage device200and the power-off period INF_P (operation S325).

The storage device200may compare the power-off period Pp with a set power-off period Pp_th (operation S330). If the power-off period Pp of the storage device200is less than the set power-off period Pp_th, the flow may return to operation S310.

When it is determined that the power-off period Pp of the storage device200is greater than or equal to the set power-off period Pp_th, the retention module214bmay determine the retention level (operation S340). The retention module214bmay perform the retention operation based on the determined retention level (operation S350).

When it is determined that the retention performance is deteriorated, the storage device200according to example embodiments may rewrite the valid data by itself to enhance or improve the retention performance.

FIG.18is a block diagram illustrating a storage system according to example embodiments.FIGS.19and20are flowcharts illustrating the operation ofFIG.18.

Referring toFIG.18, a storage system4according to example embodiments may be a vehicle. The storage system4may include a storage device310, a temperature sensor315, a controller320, one or more sensors330, a communication interface340, a user interface350, a first function block360, a second function block370, and a power supply device380.

The storage device310may be one of the storage devices200described above with reference toFIGS.1to17.

The temperature sensor315may sense the temperature of the storage device310. The temperature of the storage device310sensed by the temperature sensor315may be provided to the controller320.

The controller320may control the overall operation of the storage system4. The controller320may control the power supply device380to supply power to the storage device310, the temperature sensor315, the controller320, the one or more sensors330, the communication interface340, the user interface350, the first function block360, the second function block370, and the power supply device380. The controller320may provide a retention mode command to the storage device310based on the temperature of the storage device310sensed by the temperature sensor315or a power-off period during which the storage device310maintains a power-off state.

The sensor330may include one or more camera devices, one or more LiDAR sensors, one or more active scanning devices such as ultrasonic sensors, and one or more geospatial positioning devices, and the like. The sensor1150may generate a sensing signal by monitoring at least a part of an external environment surrounding the vehicle.

The communication interface340may include a wireless transceiver and/or a global positioning system (GPS).

The user interface350may include a display unit indicating a dashboard of a vehicle. The display unit may display the application122described above with reference toFIGS.1to11. As described with reference toFIGS.1to11, the user may provide a retention mode activation request including a retention level through the displayed application122so that the storage device310performs a retention operation. Accordingly, the controller320may provide the retention mode command including the retention level to the storage device310.

The first function block360may perform a first process. The second function block370may perform a second process. The first process and the second process may be different from each other. The first and second processes may refer to, for example, operations of a vehicle steering device configured to control the direction of the vehicle, a throttle device configured to control acceleration and/or deceleration by controlling a motor or engine of the vehicle, a brake device configured to control the braking of the vehicle, an external lighting device, and the like.

Referring toFIGS.18and19, the temperature sensor315may sense a temperature T of the storage device310(operation S410). The controller320may determine whether the temperature T of the storage device310is higher than or equal to the set temperature Tth during the set time Pth (operation S420). When the temperature T of the storage device310is less than the set temperature Tth during the set time Pth, the flow may return to operation S410.

When it is determined that the temperature T of the storage device310is higher than or equal to the set temperature Tth during the set time Pth, the controller320may determine the retention level (operation S430). The controller320may include a register in which the retention level depending on the temperature T of the storage device310has been stored. The controller320may read the retention level depending on the temperature T of the storage device200from the register to determine the retention level. The controller320may issue the retention mode command including the retention level (operation S440). The storage device310may receive the retention mode command and perform the retention operation (operation S450). Example embodiments are not limited thereto, and the controller320may issue the retention mode command by receiving the temperature T of the storage device310from the temperature sensor in the storage device310.

Referring toFIGS.18and20, the controller320may sense the power-off period Pp during which the storage device310maintains the power-off state (operation S510). If the power-off period Pp of the storage device310is less than the set power-off period Pp_th, the flow may return to operation S510.

When it is determined that the power-off period Pp of the storage device310is greater than or equal to the set power-off period Pp_th, the controller320may power on the storage device310(operation S525). The controller320may control the power supply device380to supply power to the storage device310. The controller320may determine the retention level based on the power-off period Pp (operation S530). The controller320may include a register in which the retention level depending on the power-off period Pp of the storage device310has been stored. The controller320may read the retention level depending on the power-off period Pp of the storage device310from the register to determine the retention level. The controller320may issue the retention mode command including the retention level (operation S540). The storage device310may receive the retention mode command and perform the retention operation (operation S550).

When the vehicle is parked for a long time, the storage device310may be in a power-off state for a long time. Accordingly, deterioration of the retention performance of the storage device310may occur. In addition, the temperature of the storage device310may increase due to the environment of the vehicle, and accordingly, the retention performance of the storage device310may be deteriorated.

However, in the storage system according to example embodiments, the retention operation may be performed based on the temperature of the storage device310and/or the power-off period of the storage device310. In addition, the retention operation may be performed at the request of the user. Accordingly, the retention performance of the storage device310may be improved or enhanced.

FIG.21is a diagram illustrating a system to which a storage system according to example embodiments is applied.

A system1000ofFIG.21may be a mobile system such as a portable communication terminal (mobile phone), a smart phone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, example embodiments are not necessarily limited to a mobile system, and the system1000ofFIG.21may also be a personal computer, a laptop computer, a server, a media player, an automotive device such as a navigation system, or the like.

Referring toFIG.21, the system1000may include a main processor1100, memories1200aand1200b, and storage devices1300aand1300b, and additionally, may include one or more of an image capturing device1410, a user input device1420, a sensor1430, a communication device1440, a display1450, a speaker1460, a power supply device1470, and a connection interface1480.

The main processor1100may control the overall operation of the system1000, more specifically, the operations of other components constituting the system1000. The main processor1100may be implemented as a general-purpose processor, a dedicated processor, an application processor, or the like.

The main processor1100may include one or more CPU cores1110, and may further include a controller1120for controlling the memories1200aand1200band/or the storage devices1300aand1300b. According to an example embodiment, the main processor1100may further include an accelerator block1130, which is a dedicated circuit for high-speed data operation such as artificial intelligence (AI) data operation. The accelerator block1130may include a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), and/or the like, and may be implemented as a separate chip physically independent of other components of the main processor1100.

The memories1200aand1200bmay be used as main memory devices of the system1000, and may include a volatile memory such as SRAM and/or DRAM, or may include a nonvolatile memory such as a flash memory, PRAM and/or RRAM. The memories1200aand1200bmay be implemented in the same package as the main processor1100.

The storage devices1300aand1300bmay be the storage device200described above with reference toFIGS.1to17.

The storage devices1300aand1300bmay function as nonvolatile storage devices that store data regardless of whether power is supplied or not, and may have a relatively larger storage capacity than the memories1200aand1200b. The storage devices1300aand1300bmay be the storage device200described with reference toFIGS.1to17.

The image capturing device1410may capture a still image or a moving picture (e.g., a series of still images), and may be a camera, a camcorder, a webcam, and/or the like.

The user input device1420may receive various types of data inputted from a user of the system1000, and may be a touch pad, a keypad, a keyboard, a mouse, a microphone, and/or the like.

The sensor1430may sense various types of physical quantities that can be obtained from the outside of the system1000and may convert the sensed physical quantities into electric signals. The sensor1430may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, a gyroscope, and/or the like.

The communication device1440may transmit and receive signals to and from other devices outside the system1000according to various communication protocols. The communication device1440may be implemented by including an antenna, a transceiver, a modem (MODEM), and/or the like.

The display1450and the speaker1460may function as output devices that output visual information and auditory information to the user of the system1000, respectively.

The power supply device1470may appropriately convert power supplied from a battery built in the system1000and/or an external power source to supply the power to each component of the system1000.

The connection interface1480may provide a connection between the system1000and an external device connected to the system1000and capable of exchanging data with the system1000.

FIG.22is a diagram illustrating a UFS system according to example embodiments. A UFS system2000is a system conforming to the UFS standard announced by the Joint Electron Device Engineering Council (JEDEC), and may include a UFS host2100, a UFS device2200, and a UFS interface2300. The above description of the system1000ofFIG.21may also be applied to the UFS system2000ofFIG.22within a range that does not conflict with the following description ofFIG.22.

Referring toFIG.22, the UFS host2100and the UFS device2200may be interconnected through the UFS interface2300. When the main processor1100ofFIG.21is an application processor, the UFS host2100may be implemented as part of the corresponding application processor. A UFS host controller2110and a host memory2140may correspond to the controller1120and the memories1200aand1200bof the main processor1100ofFIG.21, respectively. The UFS device2200may correspond to the storage devices1300aand1300bofFIG.21, and a UFS device controller2210and a nonvolatile memory2220may correspond to the storage controllers1310aand1310band the nonvolatile memories1320aand1320bofFIG.21, respectively.

The UFS host2100may include the UFS host controller2110, an application2120, a UFS driver2130, the host memory2140, and a UFS interconnect (UIC) layer2150. The UFS device2200may include a UFS device controller2210, the nonvolatile memory2220, a storage interface2230, a device memory2240, a UIC layer2250, and a regulator2260. The nonvolatile memory2220may be composed of a plurality of memory units2221, and the memory unit2221may be the nonvolatile memory220described with reference toFIGS.2and3. The UFS device controller2210and the nonvolatile memory2220may be connected to each other through the storage interface2230.

The application2120may refer to a program that desires communication with the UFS device2200in order to use the functions of the UFS device2200. The application2120may transmit an input-output request (IOR) to the UFS driver2130for input/output to the UFS device2200.

The UFS driver2130may manage the UFS host controller2110through a UFS-HCI (host controller interface). The UFS driver2130may convert the input/output request generated by the application2120into a UFS command defined by the UFS standard, and transmit the converted UFS command to the UFS host controller2110. One input/output request may be converted into a plurality of UFS commands. The UFS command may be a command defined by the SCSI standard, but may also be a UFS standard-only command.

The UFS host controller2110may transmit the UFS command converted by the UFS driver2130to the UIC layer2250of the UFS device2200through the UIC layer2150and the UFS interface2300. In this process, a UFS host register2111of the UFS host controller2110may serve as a command queue (CQ).

The UIC layer2150of the UFS host2100may include a MIPI M-PHY2151and a MIPI UniPro2152, and the UIC layer2250of the UFS device2200may include a MIPI M-PHY2251and a MIPI UniPro2252.

The UFS interface2300may include a line that transmits a reference clock REF_CLK, a line that transmits a hardware reset signal RESET_n for the UFS device2200, a pair of lines that transmit a differential input signal pair DIN_t and DIN_c, and a pair of lines that transmit a differential output signal pair DOUT_t and DOUT_c.

The UFS device controller2210of the UFS device2200may control the overall operation of the UFS device2200. The UFS device controller2210may manage the nonvolatile memory2220through a logical unit (LU)2211that is a logical data storage unit. The number of the LUs2211may be eight, but is not limited thereto.

The UFS device controller2210may include a working memory2212in which a retention module2212ais driven. The retention module2212aand the nonvolatile memory2220may be the retention module214aand the nonvolatile memory220described above with reference toFIGS.1to17.

The UFS host2100may sequentially store commands to be transmitted to the UFS device2200in the UFS host register2111which may function as a command queue, and transmit the commands to the UFS device2200in the above order. At this time, even when a previously transmitted command is still being processed by the UFS device2200, that is, even before receiving a notification that the previously transmitted command has been processed by the UFS device2200, the UFS host2100may transmit a next command waiting in a command queue to the UFS device2200. Accordingly, the UFS device2200may receive the next command from the UFS host2100even while processing the previously transmitted command. The plurality of memory units2221may be the nonvolatile memory220described above with reference toFIGS.2and3.

FIG.23is a diagram illustrating a data center to which a storage system according to example embodiments is applied.

Referring toFIG.23, a data center3000is a facility that collects various types of data and provides services, and may be referred to as a data storage center. The data center3000may be a system for operating a search engine and a database, or may be a computing system used in a government institution or a company such as a bank. The data center3000may include application servers3100to3100n, storage servers3200to3200m, and an archive storage server3300. The number of the application servers3100to3100n, the number of the storage servers3200to3200m, and the archive storage server3300may be variously selected according to example embodiments, and the number of the application servers3100to3100n, the number of the storage servers3200to3200m, and the number of the archive storage server3300may be different from each other.

The application server3100, the storage server3200, and the archive storage server3300may include at least one of a processor3110,3210,3310or a memory3120,3220,3320. When describing the storage server3200as an example, the processor3210may control the overall operation of the storage server3200, and access the memory3220to execute instructions and/or data loaded in the memory3220. The memory3220may be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a nonvolatile DIMM (NVMDIMM). According to an example embodiment, the number of the processors3210and the number of the memories3220included in the storage server3200may be variously selected. In an example embodiment, the processor3210and the memory3220may be provided as a processor-memory pair. In an example embodiment, the number of processors3210and the number of memories3220may be different. The processor3210may include a single core processor or a multiple core processor. The above description of the storage server3200may be similarly applied to the application server3100. According to an example embodiment, the application server3100may not include the storage device3150. The storage server3200may include at least one storage device3250. The number of storage devices3250included in the storage server3200may be variously selected according to example embodiments. A controller3251,3351, a NAND3252,3352, a DRAM3253,3353, and an interface3254,3354may be the storage controller210, the nonvolatile memory220, the buffer memory216, and the device interface211described above with reference toFIGS.1to17, respectively.

The application servers3100to3100n, the storage servers3200to3200m, and the archive storage server3300may communicate with each other through a network1300. The network1300may be implemented using a Fibre Channel (FC), Ethernet, or the like. In this case, the FC may be a medium used for relatively high-speed data transmission, and an optical switch providing high performance/high availability may be used. The storage servers3200to3200mmay be provided as file storage, block storage, or object storage according to an access method of the network1300.

In an example embodiment, the network1300may be a storage-only network, such as a storage area network (SAN). As one example, the SAN may an FC-SAN that uses an FC network and is implemented according to FC Protocol (FCP). As another example, the SAN may be an IP-SAN that uses a TCP/IP network and is implemented according to an iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In another example embodiment, the network1300may be a general network such as the TCP/IP network. For example, the network1300may be implemented according to a protocol such as FC over Ethernet (FCoE), network attached storage (NAS), NVMe over Fabrics (NVMe-oF), or the like.

Hereinafter, a description will be given focusing on the application server3100and the storage server3200. The description of the application server3100may also be applied to another application server3100n, and the description of the storage server3200may also be applied to another storage server3200m.

The application server3100may store data requested to be stored by a user or a client in one of the storage servers3200to3200mthrough the network1300. In addition, the application server3100may acquire data requested to be read by a user or a client from one of the storage servers3200to3200mthrough the network1300. For example, the application server3100may be implemented as a web server, a database management system (DBMS), or the like.

The application server3100may access a memory3120nor a storage device3150nincluded in another application server3100nthrough the network1300, or may access the memories3220to3220mor the storage devices3250to3250mincluded in the storage servers3200to3200mthrough the network1300. Accordingly, the application server3100may perform various operations on data stored in the application servers3100to3100nand/or the storage servers3200to3200m. For example, the application server3100may execute a command for moving or copying data between the application servers3100to3100nand/or the storage servers3200to3200m. At this time, the data may be transferred from the storage devices3250to3250mof the storage servers3200to3200mto the memories3120to3120nof the application servers3100-3100ndirectly or through the memories3220to3220mof the storage servers3200to3200m. Data moving through the network1300may be encrypted data for security or privacy.

The archive storage server3300may be used as a secondary storage server for cold storage. Therefore, an access frequency may be lower and a power-off period may be longer, compared to the storage servers3200to3200m.

Switches3230and3330may selectively connect the processor3210,3310to the storage device3250,3350, or may selectively connect the NIC3240,3340to the storage device3250,3350, under the control of the processor3210,3310.

A power supply device3400may supply power to the application servers3100to3100n, the storage servers3200to3200m, and the archive storage server3300.

The data center3000may further include the archive storage server3300and the power supply device3400. The archive storage server3300may be used as a secondary storage server for cold storage. In addition, the archive storage server3300may store therein data requiring permanent or long-term storage, such as original data.

In the data center3000according to example embodiments, the archive storage server3300may perform the retention operation as described above with reference toFIGS.1to17. Accordingly, the retention performance of the archive storage server3300may be enhanced or improved.

At least one of the components, elements, modules or units (collectively “components” in this paragraph) represented by a block in the drawings may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an example embodiment. These components may include, for example, the FTL214a, the retention module214b, the patrol read module214c, the packet manager215, the ECC217, the AES218, the controller222, the controller320, the first function block360, and the second function block370shown inFIGS.2,12and18, not being limited thereto. At least one of these components may use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Further, at least one of these components may include or may be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Two or more of these components may be combined into one single component which performs all operations or functions of the combined two or more components. Also, at least part of functions of at least one of these components may be performed by another of these components.

It will be also understood that, although in example embodiments related to methods or flowcharts, a step or operation is described later than another step or operation, the step or operation may be performed earlier than the other step or operation unless the other step or operation is described as being performed after the step or operation.

While example embodiments have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure.