Patent ID: 12249954

DETAILED DESCRIPTION

FIG.1is a circuit diagram of a prior art NMOS-based constant-gmcurrent source2for use with a Pierce oscillator, and in particular to supply the inverter4of the Pierce oscillator. The details of the Pierce oscillator are not described in detail as the structure and function of a Pierce oscillator are well known in the art per se.

The constant-gmcurrent source2provides a dynamically-adjusted supply current IPIERCEto the inverter4of the Pierce oscillator, i.e. to the ‘Pierce inverter’. This supply current IPIERCEis adjusted during operation to keep the transconductance gmof the current source substantially constant across corners and temperatures. However, this only works within certain limits.

The dynamically-adjusted supply current IPIERCEto the Pierce inverter4is achieved with the ‘NMOS-based’ topology shown inFIG.1. Note that the terms ‘NMOS-based’ and ‘PMOS-based’ as used herein do not mean that the associated current source only uses NMOS or PMOS devices respectively, but instead refers to which device type is used for which purpose.

The two PMOS transistors P1, P2have substantially equal W/L ratios, i.e. there is a 1:1 relationship between the W/L ratios of P1and P2. However, the two NMOS transistors N1, N2are scaled such that the W/L ratio of N2is four times greater than the W/L ratio of N1, i.e. there is a 1:4 relationship between the W/L ratios of N1and N2. It will be appreciated, however, that other factors between the W/L ratios of N1and N2, and thus in general the W/L of N2is a factor ‘m’ greater than the W/L of N1.

The constant-gmcurrent source2is constructed from a pair of PMOS transistors P1, P2and a pair of NMOS transistors N1, N2. The first PMOS transistor P1and the first NMOS transistor N1form a ‘first branch’ and the second PMOS transistor P2and the second NMOS transistor N2form a ‘second branch’.

The first branch is arranged such that the source terminal of N1is connected to ground, and the source terminal of P1is connected to the positive supply rail AVDD. The drain terminals of P1and N1are connected to each other and to the gate terminal of N1.

The gate terminals of P1and P2are connected to each other. Similarly, the gate terminals of N1and N2are also connected to each other.

The second branch is arranged such that the source terminal of N2is connected to ground via a fixed resistor R1, and the source terminal of P2is connected to the positive supply rail AVDD. The drain terminals of P2and N2are connected to each other and to the gate terminal of P2.

A PMOS output transistor P3is arranged such that its gate terminal is connected to the drain terminals of P2and N2. Thus the voltage at the gate terminal of the output transistor P3varies the drain-source current through the output transistor P3, which is provided as the supply current IPIERCEto the Pierce inverter4, i.e. the drain terminal of P3is connected to the Pierce inverter4. The source terminal of P3is connected to the positive supply rail AVDD.

Generally, the current through N2is equal to the magnitude of the difference between the gate-source voltages of the N1and N2divided by the resistance of R1in accordance with Equation 1:

The⁢current⁢through⁢the⁢first⁢and⁢third⁢transistorsEquation⁢1I2=❘"\[LeftBracketingBar]"Vg⁢s⁢1-Vg⁢s⁢2❘"\[RightBracketingBar]"R1=Δ⁢Vg⁢sR1=Δ⁢VodR1=I1=I
where: I is the current, I1is the current through N1, I2is the current through N2, Vgs1is the gate-source voltage of N1, Vgs2is the gate-source voltage of N2, ΔVgsis the difference in these gate-source voltages, Vodis the difference between the gate-source voltage Vgsand the threshold voltage Vthfor a given transistor (as outlined further below below) and thus ΔVodis the difference between this value for the two transistors N1, N2.

The transconductance gmis given as per Equation 2 below:

The⁢transconductance⁢of⁢the⁢current⁢source⁢2Equation⁢2gm⁢1=2×IVod⁢1=2⁢(Δ⁢Vod)(R⁢1×Vod⁢1)=(2×R⁢1)×(1-Vod⁢2Vod⁢1)=2R⁢1⁢(1-1m)
where: gm1is the transconductance of N1, Vod1is the difference between the respective gate-source voltage Vgsand the threshold voltage Vthof N1, Vod2is the difference between the respective gate-source voltage Vgsand the threshold voltage Vthof N2, and m is the factor by which the aspect ratio W/L of N2is greater than the aspect ratio W/L of N1.

By using Equation 3 below:

Relationship⁢between⁢the⁢output⁢voltages⁢and⁢the⁢factor⁢mEquation⁢3Vod⁢2Vod⁢1=W⁢1W⁢2=1√(m)
and setting m to 4, then the transconductance of N1

gm⁢1=1R⁢1,
and thus the transconductance gm1depends only on the value of R1, thereby providing the constant-gmfunction of the current source2.

By simulating the negative resistance RNEGgenerated by the Pierce inverter4for a given supply current IPIERCE, the ratio between the maximum and minimum negative resistances seen—i.e. Max(RNEG)/Min(RNEG)—is 1.64. Reducing this ratio would be preferable because this would indicate less fluctuation in the negative resistance RNEGgenerated by the Pierce inverter4across these corners and temperatures.

As will be appreciated by those skilled in the art, the Pierce inverter4would typically have a crystal (e.g. a quartz crystal) connected across its terminals XC1, XC2. However, there are many possible options when choosing commercial crystals. For examples, different Q-factors, different package types, and different model parameters even with the same package size, all influence the need to have sufficient negative resistance RNEGgenerated by the Pierce inverter4in order to drive the crystal and to sustain the oscillation. With the conventional arrangement ofFIG.1(and that ofFIG.2as outlined below), the supply current IPIERCEneeds to be adjusted manually for different crystals, which is cumbersome.

FIG.2is a circuit diagram of a prior art PMOS-based constant-gmcurrent source2′, which supplies the inverter4of a Pierce oscillator. As before, the Pierce inverter4would typically have a crystal (e.g. a quartz crystal) connected across its terminals XC1, XC2.

The PMOS-based constant-gmcurrent source2′ provides the dynamically-adjusted supply current IPIERCEto the inverter4of the Pierce oscillator, and this supply current IPIERCEis adjusted during operation to keep the transconductance gmof the current source substantially constant across corners and temperatures. However, as with the arrangement ofFIG.1, this only works within certain limits.

In this arrangement, the two NMOS transistors N1, N2have substantially equal W/L ratios, i.e. there is a 1:1 relationship between the W/L ratios of N1and N2. However, the two PMOS transistors P1, P2are scaled such that the W/L ratio of P2is four times greater than the W/L ratio of P1, i.e. there is a 1:4 relationship between the W/L ratios of P1and P2. As before, the 1:4 relationship is only given as an example, and in practice there may be a 1:m relationship between the W/L ratios of P1and P2.

The constant-gmcurrent source2′ is constructed from a pair of PMOS transistors P1, P2and a pair of NMOS transistors N1, N2. The first PMOS transistor P1and the first NMOS transistor N1form a ‘first branch’ and the second PMOS transistor P2and the second NMOS transistor N2form a ‘second branch’.

The first branch is arranged such that the source terminal of N1is connected to ground, and the source terminal of P1is connected to the positive supply rail AVDD. The drain terminals of P1and N1are connected to each other and to the gate terminal of P1.

The second branch is arranged such that the source terminal of N2is connected to ground, and the source terminal of P2is connected to the positive supply rail AVDD via a fixed resistor R1. The drain terminals of P2and N2are connected to each other and to the gate terminal of N2. The gate terminals of P1and P2are connected to each other. Similarly, the gate terminals of N1and N2are also connected to each other.

An NMOS output transistor N3is arranged such that its gate terminal is connected to the drain terminals of P2and N2. Thus, the voltage at the gate terminal of the output transistor P3varies the drain-source current through the output transistor N3.

The drain terminal of the output transistor N3is connected to a current mirror formed from a pair of PMOS transistors P4, P5. These transistors P4, P5are arranged in a current mirror arrangement such that the first mirror transistor P4is arranged in a ‘diode-connected’ arrangement, such that its source terminal is connected to AVDD, and its gate and drain terminals are both connected to the drain terminal of the NMOS output transistor N3. The second mirror transistor P5is arranged such that its source terminal is connected to AVDD, its gate terminal is connected to the gate and drain terminals of P4(and thus to the drain terminal of N3), and its drain terminal is connected to the Pierce inverter4.

The drain-source current flowing through the output transistor N3, and thus the drain-source current through the first mirror transistor P4is ‘mirrored’ through the second mirror transistor P5. The mirrored current through P5is provided as the supply current IPIERCEto the Pierce inverter4, i.e. the drain terminal of P3is connected to the Pierce inverter4.

Like the NMOS-based arrangement ofFIG.1, in the PMOS-based arrangement ofFIG.2, the supply current IPIERCEneeds to be adjusted manually for different crystals, which is cumbersome. Additionally, the PMOS-based arrangement ofFIG.2suffers from wide variation in the ratio between the maximum and minimum negative resistances seen—i.e. Max(RNEG)/Min(RNEG).

In order to find this value, operation of the arrangement ofFIG.2across5corners was simulated. These five corners are:1) Typical operation=Room temperature; AVDD at its nominal value2) Fast 0=High temperature; Nominal AVDD3) Fast_1=Low temperature; Nominal AVDD4) Slow_0=High temperature; Nominal AVDD5) Slow_1=Low temperature; Nominal AVDD

It will be appreciated that ‘Nominal AVDD’ means that the value of AVDD is simulated as its nominal ‘design’ value.

The results of this simulation can be seen in the table ofFIG.5, which relates to a simulation of a typical ‘FA128’ crystal. The metric Max(RNEG)/Min(RNEG) has been found by simulation to be 1.64 (to two decimal places).

FIG.3is a circuit diagram of a constant-gmcurrent source in accordance with an embodiment of the present invention. The overall topology of the arrangement ofFIG.3resembles that of the NMOS-based topology ofFIG.2, and elements having like reference numerals to the arrangement ofFIG.2are alike in structure and function.

However, unlike the arrangement ofFIG.2, the constant-gmcurrent source102ofFIG.3replaces the fixed resistor between the source terminal of P2and AVDD with a ‘trim’ resistor R1′. This resistor R1′ provides a ‘reference’ resistive element. In order to provide the trimmable behaviour, the ‘resistor R1’ is typically not a single fixed resistor, but instead a matrix (i.e. an array) of resistors and associated switches—such as the matrix shown inFIG.4—that allow for a given selection of the resistors in the matrix to be ‘switched in’, thereby setting the resistance of R1′. Other mechanisms suitable for varying the resistance of R1′ could be used instead, however.

As can be seen inFIG.4, the resistance R1′ in this embodiment is controlled by varying a four-bit control word TRIM<0-3>. Depending on the value of each bit TRIM<0-3>, the associated resistor is either ‘switched in’ or bypassed by the associated switch. In this particular embodiment, the resistors within R1′ have increasing resistance, from 1 ‘unit’ resistance, to 2 units, to 4 units, and then 8 units. With all resistors switched in, the total resistance of R1′ can be set up to 31 units of resistance. Of course, the resistances do not need to step in this way, or at all (these could all be the same value, for example), and any suitable selection may be made for a particular implementation.

In this case the switches are PMOS transistors but other suitable switches such as NMOS transistors could be used with suitable modification to the circuit and which value of the bits TRIM<0-3> enables and disables the associated resistor.

Referring back toFIG.3, an additional ‘auto-calibration’ resistor R2is provided between the source terminal of P1and AVDD. In practice, R2is constructed from a PMOS transistor P6, arranged such that its source terminal is connected to AVDD, and its drain terminal is connected to the source terminal of P1.

While the voltage vgp at the gate terminals of P1and P2depends on the process, supply voltage, and temperature (PVT) variations of the device, the auto-calibration transistor P6is also subject to these same PVT variations.

The gate terminal of P6(i.e. the auto-calibration resistor R2) is arranged to receive the same voltage vgp that is applied to the gate terminals of P1and P2. This may be achieved by physically connecting the gates of P1and P2to one another, or by supplying the same voltage to both (without a direct connection between them). As the gate terminal of P6is supplied with the same voltage vgp as the gates of P1and P2, this auto-calibration transistor P6operates in its triode region. This means that the transistor P6has resistor-like behaviour, i.e. there is a relatively linear, Ohmic like relationship between its drain-source voltage and drain-source current.

Like the arrangement ofFIG.2, an NMOS output transistor N3is arranged such that its gate terminal is connected to the drain terminals of P2and N2. Thus, the voltage at the gate terminal of the output transistor P3varies the drain-source current through the output transistor N3. A current mirror formed from a pair of PMOS transistors P4, P5mirrors the current through this output transistor N3, and supplies the mirrored current IPIERCE to the Pierce inverter4.

The resistance of R1′, i.e. the trimmable resistor, determines the voltage vgp at the gate terminals of P1and P2, and at the gate terminal of the auto-calibration transistor P6. For a given selected crystal (i.e. to be connected between the XC1and XC2terminals of the Pierce inverter4), the resistance of R1′ can be trimmed to a value appropriate for ‘normal’ operation of the circuit, i.e. with AVDD at its nominal value and room temperature conditions.

Compared to the arrangements ofFIGS.1and2, the arrangement ofFIG.3in accordance with an embodiment of the present invention has a far more consistent the ratio between the maximum and minimum negative resistances seen. As before, the simulated corners are:1) Typical operation=Room temperature; AVDD at its nominal value2) Fast_0=High temperature; Nominal AVDD3) Fast_1=Low temperature; Nominal AVDD4) Slow_0=High temperature; Nominal AVDD5) Slow_1=Low temperature; Nominal AVDD

The results of this simulation can be seen in the table ofFIG.6. A direct comparison of the typical FA128 crystal (FA128_TYPICAL) to the simulation results associated with the prior art arrangement ofFIG.2shown in the table ofFIG.5shows a significant improvement in the ratio of the maximum to minimum negative resistance seen. Specifically, through this simulation, the ratio Max(RNEG)/Min(RNEG) for the arrangement ofFIG.3has been found to be 1.12.

The simulation results in the table ofFIG.6also show the values found for several other commercially available crystals: NX1210AB; NX1612AA; FA20H; and TSX3225. The ‘_TYPICAL’ and ‘_WORST’ suffixes indicate typical and worst-case simulation results. As can be seen from the results, the ratio Max(RNEG)/Min(RNEG) for the arrangement ofFIG.3has been found to be consistently 1.12 (to two decimal places) for all simulated crystals and scenarios.

Thus, the metric Max(RNEG)/Min(RNEG) is significantly lower for the topology ofFIG.3compared to the prior art arrangements ofFIGS.1and2. In other words, the arrangement ofFIG.3is more consistent across the simulated corners when compared to the described prior art arrangements.

To illustrate the impact of the auto-calibration transistor P6as an ‘automatic’ resistance,FIG.7provides a further table of simulation results in which R1is ‘trimmed’ as above, but no R2(i.e. no P6) is provided. The ratio Max(RNEG)/Min(RNEG) is consistently between 1.29 and 1.30 (to two decimal places) for the same crystals and scenarios as in the table ofFIG.6. While the ratio Max(RNEG)/Min(RNEG) is improved compared to the prior art arrangement, the results are not as consistent as they are for the arrangement ofFIG.3with an auto-configuration resistor R2, as evidenced in the table ofFIG.6.

It can be seen, therefore, that embodiments of the present invention provide an improved constant-gmcurrent source for use with a Pierce oscillator, suitable for a variety of different crystals, that is more resilient to PVT variations. The constant-gmcurrent source of the present invention advantageously results in more consistent negative resistance exhibited by a Pierce oscillator supplied by the constant-gmcurrent source across different corners.

Those skilled in the art will appreciate that the specific embodiments described herein are merely exemplary and that many variants within the scope of the invention are envisaged.