Patent ID: 12238920

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a layout illustrating a semiconductor device according to embodiments.

Referring toFIG.1, a semiconductor device1includes a plurality of active regions ACT. In some embodiments, each of the plurality of active regions ACT has an elliptical shape with a long axis extending in a diagonal direction with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction).

A plurality of word lines WL are parallel to each other and extend across the plurality of active regions ACT in the first horizontal direction (X direction). Above the plurality of word lines WL, a plurality of bit lines BL are parallel to each other and extend in the second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). The plurality of bit lines BL may be connected to the plurality of active regions ACT via direct contact DC.

In some embodiments, a plurality of buried contacts BC are formed between the two neighboring bit lines BL of the plurality of bit lines BL. In some embodiments, the plurality of buried contacts BC are arranged in a matrix form in which the buried contacts BC are arrayed in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

Above the plurality of buried contacts BC, a plurality of landing pads LP may be formed. The plurality of landing pads LP overlap the buried contacts BC. In some embodiment, each landing pad LP partially overlaps a corresponding buried contact BC. In some embodiments, each of the plurality of landing pads LP may extend above one bit line BL of the two neighboring bit lines BL. For example, each landing pad LP may partially overlap a corresponding bit line BL.

The plurality of landing pads LP are arranged in a hexagonal array pattern in a plan view. For example, the plurality of landing pads LP are arranged in a honeycomb shape in which the landing pads LP are arrayed in a row in the first horizontal direction (X direction) and arrayed in a zigzag manner in the second horizontal direction (Y direction) in the plan view. A top surface of each of the plurality of landing pads LP may have a circular, disc shape. The present invention is not limited thereto. In some embodiments, a top surface of each landing pad LP may be elliptical.

Above the plurality of landing pads LP, a plurality of storage nodes SN may be formed. The plurality of storage nodes SN may be formed above the plurality of bit lines BL. The plurality of storage nodes SN are arranged in a hexagonal array pattern in a plan view. For example, the plurality of storage nodes SN are arranged in a honeycomb shape in which the storage nodes SN are arrayed in a row in the first horizontal direction (X direction) and arrayed in a zigzag manner in the second horizontal direction (Y direction) in the plan view. Each of the plurality of storage node SN may be a lower electrode of a corresponding capacitor of a plurality of capacitors. The storage nodes SN may be connected to the active regions ACT via the landing pads LP and the buried contacts BC.

In some embodiments, the semiconductor device1may be a dynamic random access memory (DRMA) device.

FIGS.2A and2B,FIGS.3A and3B,FIGS.4A and4B,FIGS.5A and5B,FIGS.6A and6B,FIGS.7A and7B,FIGS.8A to8C, andFIGS.10A and10Bare cross-sectional views sequentially illustrating a manufacturing method of a semiconductor device according to embodiments. For example,FIG.2A,FIG.3A,FIG.4A,FIG.5A,FIG.6A,FIG.7A,FIG.8A, andFIG.10Aare cross-sectional views taken along line A-A′ ofFIG.1,FIG.2B,FIG.3B,FIG.4B,FIG.5B,FIG.6B,FIG.7B,FIG.8B, andFIG.10Bare cross-sectional views taken along line B-B′ ofFIG.1, andFIG.8Cis an enlarged cross-sectional view of region XIIIc ofFIG.8A.

Referring toFIG.2AandFIG.2Btogether, element separation trenches116T are formed in a substrate110, and element separation films116for filling the element separation trenches116T are formed.

The substrate110may include, for example, silicon (Si), such as, crystalline Si, polycrystalline Si, and amorphous Si. Also, the substrate110may include at least one compound semiconductor selected from a semiconductor element such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Also, the substrate110may be have a silicon on insulator (SOI) structure. For example, the substrate110may include a buried oxide (BOX) layer. The substrate110may include a conductive region, for example, a well doped with impurities or a structure doped with impurities.

Each of the element separation films116may be made of a material including, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The element separation film116may include a single layer including one type of insulating film, a double layer including two types of insulating films, or a multi layer including at least three types of insulating films. For example, the element separation film116may have a dual layer or a multi layer, which includes an oxide film and a nitride film. However, according to the inventive concept, the configuration of the element separation film116is not limited thereto. A plurality of active regions118may be defined in the substrate110by the element separation films116.

Each of the active regions118may have an island, elliptical shape with a short axis and a long axis in a plan view, as in the active region ACT illustrated inFIG.1. For example, the long axis of each active region118may be parallel to the diagonal direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction).

A plurality of word line trenches120T are formed in the substrate110. Each of the plurality of word line trenches120T may have a line shape. The word line trenches120T are parallel to each other and extend in the first horizontal direction (X direction), and pass through the active regions118. The word line trenches120T are spaced apart from each other at a substantially constant distance in the second horizontal direction (Y direction). The term “substantially constant distance” does not necessarily mean an identical distance, but is intended to encompass nearly identical distance within acceptable variations that may occur, for example, due to manufacturing processes. In some embodiments, a stepped portion may be formed on the bottom surfaces of the plurality of word line trenches120T. In some embodiments, in a process of forming the plurality of word line trenches120T, the element separation film116and the substrate110may be etched by separate etching processes, and thus, an etching depth of the element separation film116may be different from an etching depth of the substrate110. In some embodiments, in a process of forming the plurality of word line trenches120T, the element separation film116and the substrate110may be etched together, but due to difference in etch rates of the element separation film160and the substrate110, an etching depth of the element separation film116may be different from an etching depth of the substrate110. In some embodiments, each word line trench120T may extend along the first horizontal direction (X direction) and have a first portion formed in the substrate110and a second portion formed in the element separation film116. When the element separation film116and the substrate110are etched together or separately, an etching depth of the first portion in the substrate110may be different from an etching depth of the second portion in the element separation film116. In some embodiments, the etching depth of the first portion in the substrate110may be smaller than the etching depth of the second portion in the element separation film116. Such difference in the etching depths may form the step portion at the bottom of each word line trench120T. In some embodiments, the first portion of each word line trench120T and the second portion thereof may be alternately arranged along the first horizontal direction with a step portion at a boundary between the first portion and the second portion.

After the formation of the plurality of the word line trenches120T, a cleaning process may be performed and then, a plurality of gate dielectric films122, a plurality of word lines120, and a plurality of buried insulating films124may be sequentially formed inside the plurality of word line trenches120T. The plurality of word lines120may constitute the plurality of word lines WL as illustrated inFIG.1. Each of the plurality of word lines120may have a line shape extending in the first horizontal direction (X direction). The word lines120that are parallel to each other and extend in the first horizontal direction (X direction) pass through the active regions118, and are spaced apart from each other at a substantially constant distance in the second horizontal direction (Y direction). A top surface of each of the plurality of word lines120is positioned at a lower level than a top surface of the substrate110. A bottom surface of each of the plurality of word lines120may have an uneven shape due to the steps at the bottoms of the word line trenches120T, and transistors having a saddle fin (saddle fin-type field effect transistors (FinFETs)) may be formed in the plurality of the active regions118.

In this specification, a level may refer to a height in a vertical direction (Z direction) with respect to a main surface or a top surface of the substrate110. For example, being at the same level or at a constant level may refer to being at the same height or being at a constant height in the vertical direction (Z direction) with respect to the main surface or the top surface of the substrate110. Being at lower/upper level may refer to being at a lower/higher height in the vertical direction (Z direction) with respect to the main surface of the substrate110.

In some embodiments, each of the plurality of word lines120is a laminated structure of a lower word line layer120aand an upper word line layer120b. In some embodiments, the lower word line layer120amay include a metal material, a conductive metal nitride, or a combination thereof. For example, the lower word line layer120amay include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. In some embodiments, the upper word line layer120bmay include doped polysilicon. In some embodiments, the lower word line layer120amay include a core layer and a barrier layer between the core layer and a gate dielectric film122. For example, the core layer may include a metal material or a conductive metal nitride such as W, WN, TiSiN, or WSiN, and the barrier layer may include a metal material or a conductive metal nitride such as Ti, TiN, Ta, or TaN.

In some embodiments, after or before the plurality of word lines120are formed, impurity ions may be implanted into portions of the active regions118of the substrate110on opposite sides of the plurality of word lines120, and thus, source regions and drain regions may be formed inside the plurality of active regions118.

The gate dielectric film122may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, oxide/nitride/oxide (ONO), and high-k dielectric film having a higher dielectric constant than the silicon oxide film. For example, the gate dielectric film122may have a dielectric constant between about 10 and about 25. In some embodiment, the gate dielectric film122may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric film122may include HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

A top surface of the each of the plurality of buried insulating films124may be at substantially the same level as the top surface of the substrate110. The buried insulating films124may include at least one material film selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and combination thereof.

Referring toFIGS.3A and3Btogether, first and second insulating film patterns112and114, which cover the element separation films116, the plurality of active regions118, and the plurality of buried insulating films124, are formed. For example, each of the first and second insulating film patterns112and114may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metallic dielectric film, or a combination thereof. In some embodiments, the first and second insulating film patterns112and114may be formed by laminating a plurality of insulating films including the first insulating film pattern112and the second insulating film pattern114. In some embodiments, the first insulating film pattern112may include a silicon oxide film, and the second insulating film pattern114may include a silicon oxynitride film.

In some embodiments, the first insulating film pattern112may include a non-metallic dielectric film, and the second insulating film pattern114may include a metallic dielectric film. For example, the first insulating film pattern112may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. For example, the second insulating film pattern114may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

Subsequently, a conductive semiconductor layer132P is formed above the first and second insulating film patterns112and114. Then, a direct contact hole134H, which passes through the conductive semiconductor layer132P and the first and second insulating film patterns112and114and exposes a source region inside the active region118, is formed. A direct contact conductive layer134P, which fills the direct contact hole134H, is formed. In some embodiments, the direct contact hole134H may extend into the active region118, for example, into the source region.

The conductive semiconductor layer132P may include, for example, doped polysilicon. The direct contact conductive layer134P may include silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof. In some embodiments, the direct contact conductive layer134P may include an epitaxial silicon layer. In some embodiments, the direct contact conductive layer134P may include a doped polysilicon.

In some embodiments, the direct contact hole134H, which passes through the first and second insulating film patterns112and114and exposes the source region inside the active region118, is firstly formed, and then the direct contact hole134H is filled with the direct contact conductive layer134P. The conductive semiconductor layer132P, which covers the first and second insulating film patterns112and114, and the direct contact conductive layer134P may be formed together. In an exemplary embodiment, the conductive semiconductor layer132P and the direct contact conductive layer134P may be formed of the same material such as a doped polysilicon. For the clarity of drawing,FIG.3Amarks a boundary between the conductive semiconductor layer132P and the direct contact conductive layer134P.

Referring toFIGS.4A and4Btogether, a metallic conductive layer and an insulating capping layer, which cover the conductive semiconductor layer132P and the direct contact conductive layer134P, are sequentially formed to form a bit line structure140.

In some embodiments, the metallic conductive layer may be a laminated structure of a first metallic conductive layer and a second metallic conductive layer. The metallic conductive layer may have a double layered structure such as a laminated conductive layer structure, but this is merely an example. The inventive concept is not limited to the example. For example, the metallic conductive layer may have a single layer or a multi laminated structure including three or more layers.

In some embodiments, the insulating capping layer may have a laminated structure of a first insulating capping layer, a second insulating capping layer, and a third insulating capping layer. The insulating capping layer may have a laminated insulating layer structure including three or more layers, but this is merely an example. The inventive concept is not limited to the example. For example, the insulating capping layer may have a single layer, a double layer, or a multi laminated structure including four or more layers.

The first metallic conductive layer, the second metallic conductive layer, and the insulating capping layer may be etched to form a plurality of bit lines147and a plurality of insulating capping lines148. Each of the plurality of bit lines147has a laminated structure of a first metallic conductive pattern145and a second metallic conductive pattern146. Each bit line147may have a line shape extending along the second horizontal direction (Y axis). Each insulating capping line148is disposed on a corresponding bit line, extending along the second horizontal direction (Y axis).

In some embodiments, the first metallic conductive pattern145may include titanium nitride (TiN) or TSN (Ti—Si—N), and the second metallic conductive pattern146may include tungsten (W), or tungsten and tungsten silicide (WSix). In some embodiments, the first metallic conductive pattern145may serve as a diffusion barrier. In some embodiments, each of the plurality insulating capping lines148may have a laminated structure of a first insulating capping line148a, a second insulating capping line148b, and a third insulating capping line148c. In some embodiments, each of the first insulating capping line148a, the second insulating capping line148b, and the third insulating capping line148cmay include a silicon nitride film.

One bit line147and one insulating capping line148that covers the one bit line147may constitute one bit line structure140. The plurality of bit line structures140, constituted by the plurality of bit lines147and the plurality of insulating capping lines148, are parallel to each other. Each bit line structure140may extend in the second horizontal direction (Y direction) that is parallel to the main surface of the substrate110. The plurality of bit lines147may constitute the plurality of bit lines BL illustrated inFIG.1. In some embodiments, the bit line structure140may further include a conductive semiconductor pattern132, which is a portion of the conductive semiconductor layer132P (FIGS.3A and3B) disposed between the first metallic conductive pattern145and a combined structure of the first and second insulating film patterns112and114.

In an etching process for forming the plurality of bit lines147, a portion of the direct contact conductive layer134P (FIGS.3A and3B) not vertically overlapping the bit line147is removed. Thus, a plurality of direct contact conductive patterns134may be formed. Here, each of the first and second insulating film patterns112and114may serve as an etch stop film during the etching process for forming the plurality of bit lines147and the plurality of direct contact conductive patterns134. The plurality of direct contact conductive patterns134may constitute the plurality of direct contacts DC illustrated inFIG.1. The plurality of bit lines147may be electrically connected to the plurality of active regions118via the plurality of direct contact conductive patterns134.

In some embodiments, during a process of etching the portion of the direct contact conductive layer134P to form the direct contact conductive pattern134, the conductive semiconductor pattern132may be formed together. For example, the conductive semiconductor pattern132may be a portion of the conductive semiconductor layer132P, which does not vertically overlap the direct contact hole134H and is positioned above the first and second insulating film patterns112and114. The portion of the conductive semiconductor layer132P vertically overlaps the bit line147. In some embodiment, the bit line147may serve as an etching mask to form the conductive semiconductor pattern132. The direct contact conductive pattern134is a portion which vertically overlaps the direct contact hole134H and is in contact with the active region118. The term “contact,” as used herein, refers to a direct connection (i.e., touching) unless the context indicates otherwise.

After the bit line structure140is formed, a buried insulating pattern136may be formed. The buried insulating pattern136fills a portion of the direct contact hole134H from which the portion of the direct contact conductive layer134P is removed during the process of forming the direct contact conductive pattern134. The buried insulating pattern136may include, for example, a silicon nitride film.

Opposite sidewalls of each of the bit line structures140are covered with a preliminary insulating spacer structure150P. Each of the plurality of preliminary insulating spacer structures150P includes a first insulating spacer152, a second insulating spacer154, a third insulating spacer156, and a fourth insulating spacer158. In some embodiments, each of the plurality of preliminary insulating spacer structures150P does not include one of the third insulating spacer156and the fourth insulating spacer158. In some embodiments, each of the plurality of preliminary insulating spacer structures150P may include the first insulating spacer152, the second insulating spacer154, and the third insulating spacer156. In some embodiments, each of the plurality of preliminary insulating spacer structures150P may include the first insulating spacer152, the second insulating spacer154, and the fourth insulating spacer158.

In some embodiments, each of the first insulating spacer152, the third insulating spacer156, and the fourth insulating spacer158may include a nitride film. The second insulating spacer154may include a material having etch selectivity with respect to the first insulating spacer152, the third insulating spacer156, and the fourth insulating spacer158. For example, when each of the first insulating spacer152, the third insulating spacer156, and the fourth insulating spacer158include a silicon nitride film, the second insulating spacer154may include an oxide film and may be removed in a subsequent process to form an air spacer.

A plurality of buried contact holes170H are formed between the plurality of bit lines147. An inner space of each of the plurality of buried contact holes170H may be defined by the active region118, the insulating spacer structure150that covers a sidewall of a first bit line of the two neighboring bit lines147and the insulating spacer structure150that covers a sidewall of a second bit line of the two neighboring bit lines147.

The plurality of buried contact holes170H may be formed by removing portions of the first and second insulating film patterns112and114and portions of the active region118. In some embodiments, the plurality of insulating capping lines148and the preliminary insulating spacer structures150P covering the opposite sidewalls of each of the plurality of bit line structures140may be used as etch masks. In some embodiments, the plurality of buried contact holes170H may be formed by firstly performing an anisotropic etch process in which portions of the first and second insulating film patterns112and114and portions of the active region118may be removed by using, as the etch masks, the plurality of insulating capping lines148and the preliminary insulating spacer structures150P covering the opposite sidewalls of each of the plurality of bit line structures140. Then, an isotropic etch process of further removing another portion of the active region118may be performed, and thus, the space defined by the active region118may extend. For example, an undercut below the preliminary insulating spacer structures150P may be formed using the isotropic etch process so that the space defined by the active region118may extend in the first horizontal direction (X direction).

Referring toFIGS.5A and5Btogether, a plurality of buried contacts170and a plurality of insulating fences180are formed in spaces between the plurality of preliminary insulating spacer structures150P covering the opposite sidewalls of each of the plurality of bit line structures140. The plurality of buried contacts170and the plurality of insulating fences180may be alternately arranged, along a space between a facing pair of the preliminary insulating spacer structures150P of the plurality of preliminary insulating spacer structures150P covering the opposite sidewalls of the plurality of bit line structures140. For example, the plurality of buried contacts170and the plurality of insulating fences180may be alternately arranged along the second horizontal direction (Y direction). For example, each of the plurality of buried contacts170may include polysilicon. For example, each of the plurality of insulating fences180may include a silicon nitride film.

In some embodiments, the plurality of buried contacts170may be arrayed in the first horizontal direction (X direction) and the second horizontal direction (Y direction). In some embodiments, the plurality of insulating fences180may be arrayed in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

Each of the buried contacts170extends from above the active region118in the vertical direction (Z direction) perpendicular to the substrate110. The plurality of buried contacts170may constitute the plurality of buried contacts BC illustrated inFIG.1.

The plurality of buried contacts170are positioned in spaces defined by the plurality of insulating fences180and the plurality of preliminary insulating spacer structures150P covering opposite sidewalls of the plurality of bit line structures140. The plurality of buried contacts170fill some of lower portions of the spaces between the plurality of preliminary insulating spacer structures150P covering opposite sidewalls of the plurality of bit line structures140. For example, each buried contact170fills a lower portion of a space between the facing pair of preliminary insulating spacer structures150P in the first horizontal direction (X direction) and between two neighboring insulating fences180in the second horizontal direction (Y direction).

Levels of top surfaces of the plurality of buried contacts170are lower than levels of top surfaces of the plurality of insulating capping lines148with respect to the vertical direction (Z direction). Top surfaces of the plurality of insulating fences180may be at the same level as the top surfaces of the plurality of insulating capping lines148with respect to the vertical direction (Z direction).

A plurality of landing pad holes190H are defined by the plurality of insulating spacer structures150and the plurality of insulating fences180. The plurality of buried contacts170are exposed at bottom surfaces of the plurality of landing pad holes190H.

During a process of forming the plurality of buried contacts170and/or the plurality of insulating fences180, the insulating capping line148included in the bit line structure140and a portion of an upper side of the preliminary insulating spacer structure150P may be partially removed, and thus, a level of a top surface of the bit line structure140may be lowered.

Referring toFIGS.6A and6B, a landing pad material layer190P is formed, which fills the plurality of landing pad holes190H and covers the plurality of bit line structures140.

In some embodiments, the landing pad material layer190P includes a conductive barrier layer192P and a conductive pad material layer194P on the conductive barrier layer192P. For example, the conductive barrier layer192P may include metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier layer192P may include a Ti/TiN laminated structure or TiN. In some embodiments, the conductive pad material layer194P may include tungsten (W).

In some embodiments, before the landing pad material layer190P is formed, a metal silicide film may be formed on the plurality of buried contacts170. The metal silicide film may be disposed between the plurality of buried contacts170and the landing pad material layer190P. The metal silicide film may include cobalt silicide (CoSix), nickel silicide (NiSix), or manganese silicide (MnSix), but is not limited thereto.

A plurality of hard mask patterns HMK are formed on the landing pad material layer190P. In some embodiment, the plurality of hard mask patterns HMK may be formed through an ArF lithography process or an extreme ultraviolet (EUV) lithography process.

Referring toFIGS.7A and7Btogether, a first etching process, in which a portion of the landing pad material layer190P is removed by using the plurality of hard mask patterns HMK as etch masks, may be performed to form preliminary recess portions190RP. Each of the preliminary recess portions190RP may be formed by removing a portion of the conductive pad material layer194P so that the conductive barrier layer192P is exposed or by removing a portion of the conductive pad material layer194P and a portion of the conductive barrier layer192P so that the preliminary insulating spacer structure150P is exposed.

For example, the first etching process may be performed by a plasma etching method in which CF4or SF6is used as an etchant. For example, the first etching process may have high selectivity with respect to conductive materials such as metal and a metal nitride.

In some embodiments, during a time when the first etching process is performed, a portion of the landing pad material layer190P and a portion of the preliminary insulating spacer structure150P may be removed together with the etch masks (e.g., the hard mask patterns HMK).

Referring toFIGS.8A to8Ctogether, a second etching process and a third etching process may be performed alternately several times using the plurality of hard mask patterns HMK as the etch masks to form recess portions190R. Each of the recess portions190R may be formed by removing a portion of the conductive barrier layer192P, another portion of the conductive pad material layer194P, a portion of the fourth insulating spacer158, and a portion of the third insulating spacer156, so that the second insulating spacer154is exposed.

For example, the second etching process may be performed by a plasma etching method in which Cl2, NF3, SF6, or a mixture thereof is used as an etchant. For example, the second etching process may have high selectivity with respect to conductive materials or semiconductor materials such as metal, a metal nitride, and silicon.

For example, the third etching process may be performed by a plasma etching method in which CxFy, CxHy, CHxFy, or a mixture thereof is used as an etchant. For example, the third etching process may have high selectivity with respect to insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

The landing pad material layers190P (FIGS.7A and7B) are divided into a plurality of segments by the recess portions190R and formed into a plurality of landing pads190which fill at least some of the plurality of landing pad holes190H. The landing pads190are disposed on upper surfaces of the buried contacts170, extending above the plurality of bit line structures140. For example, the landing pads190are disposed on both the upper surfaces of the buried contacts170and the upper surfaces of the bit line structures140. The plurality of landing pads190may be spaced apart from each other with the recess portion190R therebetween.

The plurality of landing pads190are positioned above the plurality of buried contacts170and may extend above the plurality of bit line structures140. In some embodiments, the plurality of landing pads190may extend above the plurality of bit lines147. The plurality of landing pads190are positioned above the plurality of buried contacts170. Thus, the plurality of buried contacts170and the plurality of landing pads190, which correspond to each other, may be electrically connected to each other. The plurality of landing pads190may be electrically connected to the active regions118via the plurality of buried contacts170. The plurality of landing pads190may constitute the plurality of landing pads LP illustrated inFIG.1. Each of the plurality of landing pads190may include a conductive barrier pattern192and a conductive pad pattern194on the conductive barrier pattern192. In some embodiments, the conductive barrier pattern192may include a Ti/TiN laminated structure or TiN. In some embodiments, the conductive pad pattern194may include tungsten (W).

Each of the buried contacts170may be positioned between two bit line structures140adjacent to each other, and each of landing pads190may extend above one bit line structure140from between the two bit line structures140which are adjacent to each other with the buried contact170therebetween. Referring toFIGS.8A and8B, andFIG.1, each landing pad190(inFIG.1, LP) overlaps two neighboring active regions118(inFIG.1, the active regions ACT). For example, each landing pad190overlaps a buried contact170(inFIG.1, the buried contact BC) on a first active region of the two neighboring active regions and a direct contact conductive pattern134(inFIG.1, the direct contact DC) on a second active region of the two neighboring active region. The buried contact170of the first active region does not overlap the second active region. The direct contact conductive pattern134that is disposed on the second active region does not overlap the first active region. The landing pad190may be electrically connected to the buried contact170that is disposed on the first active region without being electrically connected to the direct contact conductive pattern134that is disposed on the second active region. The direct contact conductive pattern134is disposed on a bit line structure140(inFIG.1, the bit line BL) on the second active region118-2and is electrically connected thereto. The landing pad190overlaps the bit line structure140on the second active region118-2without being electrically connected to the bit line structure140.

In some embodiments, the insulating fence180and the insulating capping line148may have similar etch characteristics to the third insulating spacer156and the fourth insulating spacer158, and during a time when the recess portion190R is formed, a portion of the insulating fence180and a portion of the insulating capping line148may also be removed together.

The recess portion190R may be formed by alternately performing the second etching process and the third etching process. Thus, the recess portion190R may be bent from an upper side of the recess portion190R to a lower side of the recess portion190R, so that the recess portion190R extends, along between the landing pad190and the preliminary insulating spacer structure150P, with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the recess portion190R may be bent from the landing pad190toward the insulating capping line148of the bit line structure140, so that the recess portion190R extends with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the recess portion190R has a sidewall extending along a sidewall of the landing pad190toward the substrate110. As extending toward the substrate110, the sidewall of the recess portion190R is closer to a sidewall of the bit line structure140. The recess portion190R is defined by the sidewall of the landing pad190and the sidewall of the bit line structure140.

Referring toFIG.8C, a first vertical line UCL that extends along a center of an upper end of the recess portion190R with respect to the first horizontal direction (X direction) and a second vertical line LCL that extends along a center of a lower end of the recess portion190R with respect to the first horizontal direction (X direction) may be offset by a center shift distance CL from each other in the first horizontal direction (X direction). In some embodiment, the recess portion190R extends from an upper end of the recess portion190R toward a lower end of the recess portion190R. The recess portion190R has the center shift distance CL in the first horizontal direction (X direction) from the landing pad190toward the bit line structure140, and may be bent with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the recess portion190R may have a sidewall extending along a sidewall of the landing pad190toward the substrate110. As extending toward the substrate110, the sidewall of the recess portion190R is closer to a sidewall of the bit line structure140. The recess portion190R is defined by the sidewall of the landing pad190and the sidewall of the bit line structure140.

In some embodiments, the center of the lower end of the recess portion190R and a center of an upper end of the second insulating spacer154may be aligned with each other in the vertical direction (Z direction).

Referring toFIG.8B, the recess portion190R may have a bottom surface of which at least a portion is substantially flat in the second horizontal direction (Y direction). Between the two landing pads190spaced apart from each other in the second horizontal direction (Y direction) with the recess portion190R therebetween, the recess portion190R may have the bottom surface of which at least a portion is substantially flat in the second horizontal direction (Y direction). In some embodiments, the recess portion190R between the two landing pads190may have a substantially flat bottom surface. Because the second etching process and the third etching process are performed alternately several times during the process of forming the recess portion190R, a portion of the insulating fence180and a portion of the landing pad190exposed by the bottom surface of the preliminary recess portions190RP ofFIG.7Bmay be etched at a substantially similar rate so that the bottom surface of the recess portion190R may be substantially flat in the second horizontal direction (Y direction). For example, at least a portion of a top surface of a portion of the insulating fence180exposed at the bottom surface of the recess portion190R may be at substantially the same level as a top surface of a portion of the landing pad material layer190P along the second horizontal direction (Y direction) with respect to the vertical direction (Z direction). The portion of the landing pad material layer190P may be left between two insulating fences180after the landing pad190is formed from the landing pad material layer190P ofFIG.7B. In some embodiments, a lower portion of a side surface of the conductive pad pattern194, which is positioned below the hard mask pattern HMK, may be covered with a portion of the insulating fence180.

FIG.9is a flow chart of a manufacturing method of a semiconductor device according to embodiments.

Referring toFIGS.6A to9together, the landing pad material layer190P is formed, which fills the plurality of landing pad holes190H and covers the plurality of bit line structures140(S10). The landing pad material layer190P includes the conductive barrier layer192P and the conductive pad material layer194P on the conductive barrier layer192P. For example, the conductive barrier layer192P may include metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier layer192P may include a Ti/TiN laminated structure or TiN. In some embodiments, the conductive pad material layer194P may include tungsten (W).

The plurality of hard mask patterns HMK are formed on the landing pad material layer190P (S20). In some embodiment, the plurality of hard mask patterns HMK may be formed through an ArF lithography process or an EUV lithography process.

A first etching process (S100), in which a portion of the landing pad material layer190P is removed by using the plurality of hard mask patterns HMK as etch masks, is performed to form the preliminary recess portions190RP. Each of the preliminary recess portions190RP may be formed by removing a portion of the conductive pad material layer194P so that the conductive barrier layer192P is exposed or by removing a portion of the conductive pad material layer194P and a portion of the conductive barrier layer192P so that the preliminary insulating spacer structure150P is exposed.

For example, the first etching process (S100) may be performed by a plasma etching method in which CF4or SF6is used as an etchant. For example, the first etching process (S100) may have high selectivity with respect to conductive materials such as metal and a metal nitride. In some embodiments, the first etching process may have highest selectivity with respect to tungsten (W).

After the preliminary recess portions190RP are formed, a second etching process (S200) and a third etching process (S300) are performed alternately several times using the plurality of hard mask patterns HMK as the etch masks, and thus, the recess portions190R and the plurality of landing pads190, which are spaced apart from each other with the recess portions190R therebetween, are formed (S1000). Each of the recess portions190R may be formed by removing another portion of the landing pad material layer190P, a portion of the fourth insulating spacer158, and a portion of the third insulating spacer156, so that the second insulating spacer154is exposed.

For example, the second etching process (S200) may be performed by a plasma etching method in which Cl2, NF3, SF6, or a mixture thereof may be used as an etchant. In some embodiments, the second etching process (S200) may be performed by a plasma etching method in which a mixture of Cl2and NF3may be used as an etchant. For example, the second etching process (S200) may have high selectivity with respect to conductive materials or semiconductor materials such as metal, a metal nitride, and silicon. In some embodiments, the second etching process (S200) may have highest selectivity with respect to Ti/TiN.

For example, the third etching process (S300) may be performed by a plasma etching method in which CxFy, CxHy, CHxFy, or a mixture thereof may be used as an etchant. In some embodiments, the third etching process (S300) may be performed by an etching method in which a mixture of CHF3and Ar is used as an etchant. For example, the third etching process (S300) may have high selectivity with respect to insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. In some embodiments, the third etching process (S300) may have highest selectivity with respect to silicon nitride.

In some embodiments, the recess portion190R may be formed by alternately performing the second etching process (S200) and the third etching process (S300). For example, the number of times of performing the second etching process (S200) may be equal to the number of times of performing the third etching process (S300). For example, the second etching process (S200) may be performed first, and then the third etching process (S300) may be performed. Additionally, the second etching process (S200) and the third etching process (S300) may be repeatedly performed to form the recess portion190R.

In other embodiments, the recess portion190R may be formed by alternately performing the second etching process (S200) and the third etching process (S300) such that the number of times of performing the second etching process (S200) may be greater by one than the number of times of performing the third etching process (S300). For example, the second etching process (S200) may be performed first, and then the third etching process (S300) may be performed. Additionally, the second etching process (S200) and the third etching process (S300) may be repeatedly performed, and finally, the second etching process (S200) may be performed more. As a result, the recess portion190R may be formed.

In other embodiments, the recess portion190R may be formed by alternately performing the third etching process (S300) and the second etching process (S200) such that the number of times of performing the third etching process (S300) may be greater by one than the number of times of performing the second etching process (S200). For example, the third etching process (S300) may be performed first, and then the second etching process (S200) may be performed. Additionally, the third etching process (S300) and the second etching process (S200) may be repeatedly performed, and finally, the third etching process (S300) may be performed more. As a result, the recess portion190R may be formed.

In some embodiments, an execution time of the second etching process (S200), which is performed first in the second etching processes (S200) performed several times, may be longer than an execution time of the second etching process (S200), which is performed subsequently. In other embodiments, an execution time of the third etching process (S300), which is performed first in the third etching processes (S300) performed several times, may be longer than an execution time of the third etching process (S300), which is performed subsequently.

An upper portion of the recess portion190R may be mainly formed by performing the first etching process (S100), and a lower portion of the recess portion190R may be mainly formed by alternately performing the second etching process (S200) and the third etching process (S300) several times. In this specification, the upper portion of the recess portion190R may refer to a portion between the two neighboring landing pads190, and the lower portion of the recess portion190R may refer to a portion between one landing pad190and the bit line structure140, which is spaced apart from and adjacent to the one landing pad190.

When the first etching process (S100) is performed, a portion of the landing pad material layer190P is mainly removed toward the substrate110in the vertical direction (Z direction) along spaces between the plurality of hard mask patterns HMK, and the upper portion of the recess portion190R, which corresponds to the preliminary recess portion190RP, is formed. When the second etching process (S200) and the third etching process (S300) are alternately performed several times, another portion of the landing pad material layer190P and a portion of the preliminary insulating spacer structure150P are removed along a boundary surface between the landing pad material layer190P and the preliminary insulating spacer structure150P, and thus, the lower portion of the recess portion190R is formed.

A width, in the first horizontal direction (X direction), of the lower portion of the recess portion190R is smaller than a width, in the first horizontal direction (X direction), of the upper portion of the recess portion190R. The width of the recess portion190R with respect to the first horizontal direction (X direction) may decrease from an upper end of the recess portion190R toward a lower end of the recess portion190R. For example, the width of the upper portion of the recess portion190R may be constant along the vertical direction (Z direction), and the width of the lower portion of the recess portion190R may decrease toward the substrate110along the vertical direction.

The upper portion of the recess portion190R, which is the portion between the two neighboring landing pads190, extends toward the substrate110in the vertical direction (Z direction). The lower portion of the recess portion190R, which is the portion between one landing pad190and the bit line structure140and which is spaced apart from and adjacent to the one landing pad190, may be bent from the one landing pad190toward the bit line structure140, which is spaced apart from and adjacent to the one landing pad190, so that the lower portion of the recess portion190R extends toward the substrate110with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the lower portion of the recess portion190R has a sidewall extending along a sidewall of the landing pad190toward the substrate110. In a direction extending toward the substrate110, the sidewall of the recess portion190R gets closer to a sidewall of the bit line structure140. The recess portion190R is defined by the sidewall of the landing pad190and the sidewall of the bit line structure140.

The center, with respect to the first horizontal direction (X direction), of the upper end of the recess portion190R formed by performing the first etching process (S100) and the center of the upper end of the second insulating spacer154are not aligned with each other in the vertical direction (Z direction) but may be shifted a center shift distance CL from each other. For example, the center, in the first horizontal direction (X direction), of the upper end of the recess portion190R and the center, in the first horizontal direction (X direction), of the upper end of the second insulating spacer154, when viewed in a top down view, are spaced apart from each other in the first horizontal direction (X direction). The center, with respect to the first horizontal direction (X direction), of the lower end of the recess portion190R formed by alternately performing the second etching process (S200) and the third etching process (S300) several times and the center of the upper end of the second insulating spacer154may be aligned with each other in the vertical direction (Z direction).

The center shift distance CL may be determined according to a ratio of the sum of execution times of the third etching processes (S300) performed several times to the sum of execution times of the second etching processes (S200) performed several times. As the sum of execution times of the third etching processes (S300) performed several times increases, the center shift distance CL may increase. As the sum of execution times of the third etching processes (S300) performed several times decreases, the center shift distance CL may decrease. By adjusting the ratio of the sum of execution times of the third etching processes (S300) performed several times to the sum of execution times of the second etching processes (S200) performed several times, the center of the lower end of the recess portion190R with respect to the first horizontal direction (X direction) and the center of the upper end of the second insulating spacer154may be aligned with each other in the vertical direction (Z direction).

The plurality of landing pads190may be spaced apart from each other with the recess portions190R therebetween. The lower portion of the recess portion190R, which is the portion between one landing pad190and the bit line structure140and which is spaced apart from and adjacent to the one landing pad190, may be bent from the one landing pad190toward the bit line structure140, which is spaced apart from and adjacent to the one landing pad190, so that the lower portion of the recess portion190R extends toward the substrate110with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the lower portion of the recess portion190R has a sidewall extending along a sidewall of the landing pad190toward the substrate110. In a direction extending toward the substrate110, the sidewall of the recess portion190R gets closer to a sidewall of the bit line structure140. The recess portion190R is defined by the sidewall of the landing pad190and the sidewall of the bit line structure140. Thus, even though the width of the lower portion of the landing pad190covering the sidewall of the bit line structure140, that is, the width of a neck of the landing pad190with respect to the first horizontal direction (X direction) increases, a gap between the two neighboring landing pads190may be secured.

Referring toFIGS.8A,8B,10A, and10Btogether, second insulating spacers154are removed through the recess portions190R, and thus, a plurality of insulating spacer structures150respectively having air spacers AS are formed.

Before the second insulating spacers154are removed or after the second insulating spacers154are removed, the plurality of hard mask patterns HMK may be removed.

The recess portion190R extends, toward the substrate110, from the upper end of the recess portion190R to the lower end of the recess portion190R. The recess portion190R has the center shift distance CL in the first horizontal direction (X direction) from the landing pad190toward the bit line structure140, and is bent so that the recess portion190R extends with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the recess portion190R may have a sidewall extending along a sidewall of the landing pad190toward the substrate110. As extending toward the substrate110, the sidewall of the recess portion190R is closer to a sidewall of the bit line structure140. The recess portion190R is defined by the sidewall of the landing pad190and the sidewall of the bit line structure140. Thus, the center of the lower end of the recess portion190R may be aligned with the center of the upper end of the second insulating spacer154in the vertical direction (Z direction).

For example, the second insulating spacer154is exposed at the bottom surface of the recess portion190R, and the center of the bottom surface of the recess portion190R and the center of the upper end of the second insulating spacer154are aligned with each other in the vertical direction (Z direction). Thus, the second insulating spacer154may be smoothly removed through the recess portion190R. As a result, an air spacer AS may be formed to reduce parasitic capacitance between a bit line147and a buried contact170, for example, spaced apart from each other in the first horizontal direction (X direction).

Each of the plurality of insulating spacer structures150includes the first insulating spacer152, the third insulating spacer156, and the fourth insulating spacer158. The air spacer AS is positioned between the first insulating spacer152and the third insulating spacer156. In some embodiments, each of the plurality of insulating spacer structures150does not include one of the third insulating spacer156and the fourth insulating spacer158. For example, each of the plurality of insulating spacer structures150may include the first insulating spacer152and the third insulating spacer156. The air spacer AS may be positioned between the first insulating spacer152and the third insulating spacer156. Alternatively, for example, each of the plurality of insulating spacer structures150may include the first insulating spacer152and the fourth insulating spacer158. The air spacer AS may be positioned between the first insulating spacer152and the fourth insulating spacer158.

FIGS.11A to11Dare cross-sectional views showing a semiconductor device according to embodiments.FIG.11Ais a cross-sectional view taken along line A-A′ ofFIG.1, andFIG.11Bis a cross-sectional view taken along line B-B′ ofFIG.1.FIG.11Cis an enlarged cross-sectional view of XIc ofFIG.11A, andFIG.11Dis an enlarged cross-sectional view of Xid ofFIG.11B.

Referring toFIGS.11A to11Dtogether, an insulating structure195, which fills the recess portion190R, is formed, and then, a plurality of lower electrodes210, a capacitor dielectric film220, and an upper electrode230are sequentially formed on the plurality of landing pads190. As a result, a semiconductor device1including a plurality of capacitor structures200may be formed.

In some embodiments, the insulating structure195may serve as an interlayer insulating layer and an etch stop film. For example, the interlayer insulating layer may include an oxide film, and the etch stop film may include a nitride film.

The plurality of the lower electrodes210are disposed on the plurality of landing pads190, respectively, and are electrically connected thereto, respectively. The capacitor dielectric film220conformally covers the plurality of the lower electrodes210. The upper electrode230covers the capacitor dielectric film220. The upper electrode230is spaced apart from the lower electrodes210with the capacitor dielectric film220therebetween. The capacitor dielectric film220and the upper electrode230may be integrated with each other to cover the plurality of lower electrodes210in a certain region, for example, in one memory cell region CR. The plurality of lower electrodes210may constitute the plurality of storage nodes SN illustrated inFIG.1.

Each of the plurality of lower electrodes210may have a solid column shape of a pillar shape with a circular horizontal cross-section, but is not limited thereto. In some embodiments, each of the plurality of lower electrodes210may have a cylindrical shape with a closed lower portion. In some embodiments, the plurality of lower electrodes210may be arranged in a honeycomb shape in which the lower electrodes210are arrayed in a zigzag manner in the first horizontal direction (X direction) or the second horizontal direction (Y direction). In other embodiments, the plurality of lower electrodes210may be arranged in a matrix form in which the lower electrodes210are arrayed in the first horizontal direction (X direction) and the second horizontal direction (Y direction). The lower electrode210may include, for example, silicon doped with impurities, metal such as tungsten or copper, or a conductive metal compound such as titanium nitride. Although not separately illustrated, the semiconductor device1may further include at least one support pattern that is in contact with sidewalls of the plurality of the lower electrodes210.

The capacitor dielectric film220may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or a combination thereof.

The upper electrode230may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO SRO(SrRuO), BSRO((Ba,Sr)RuO), CRO(CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof.

FIGS.11A to11Dillustrate that a top surface of the insulating structure195and a bottom surface of each of the lower electrodes210are positioned at the same level, but the embodiment is not limited thereto. For example, the level of the top surface of the insulating structure195may be positioned higher than the level of the bottom surface of the lower electrode210, and the lower electrode210may extend into the insulating structure195toward the substrate110.

The semiconductor device1includes the substrate110in which the plurality of active regions118are defined, the plurality of gate dielectric films122, the plurality of word lines120, and the plurality of buried insulating films124which are sequentially formed inside the plurality of word line trenches120T that pass through the plurality of active regions118inside the substrate110. The semiconductor device1further includes the first and second insulating film patterns112and114covering the element separation films116, the plurality of active regions118, the plurality of buried insulating films124, the plurality of bit line structures140above the first and second insulating film patterns112and114, the plurality of insulating spacer structures150covering both the sidewalls of the plurality of bit line structures140, the plurality of buried contacts170which fill the lower portions of the spaces defined by the plurality of insulating fences180and the plurality of insulating spacer structures150and which are connected to the plurality of the active regions118, the plurality of landing pads which fill the upper portions thereof, extend above the bit line structures140, and are spaced apart from each other with the insulating structure195therebetween, and the plurality of capacitor structures200including the plurality of lower electrodes210connected to the plurality of landing pad190, the capacitor dielectric film220, and the upper electrode230.

The plurality of insulating fences180may be spaced apart from each other in the second horizontal direction (Y direction) and disposed along a space between a pair of the facing insulating spacer structures150of the plurality of insulating spacer structures150covering the opposite sidewalls of the plurality of bit line structures140. Each of the plurality of insulating fences180may extend from between the plurality of buried contacts170to between the plurality of landing pads190in the vertical direction (Z direction).

Each of the plurality of insulating spacer structures150includes the first insulating spacer152, the third insulating spacer156, and the fourth insulating spacer158. The air spacer AS is positioned between the first insulating spacer152and the third insulating spacer156. In some embodiments, each of the plurality of insulating spacer structures150does not include one of the third insulating spacer156and the fourth insulating spacer158. In some embodiments, each of the plurality of insulating spacer structures150may include the first insulating spacer152and the third insulating spacer156. The air spacer AS may be positioned between the first insulating spacer152and the third insulating spacer156. In some embodiments, each of the plurality of insulating spacer structures150may include the first insulating spacer152and the fourth insulating spacer158. The air spacer AS may be positioned between the first insulating spacer152and the fourth insulating spacer158.

The insulating structure195may be bent from an upper side of the insulating structure195toward a lower side of the insulating structure195, so that the insulating structure195extends along the spaces between the landing pad190and the preliminary insulating spacer structure150P. For example, the insulating structure195may be bent from the landing pad190toward the insulating capping line148of the bit line structure140, so that the recess portion190R extends with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the insulating structure195may have a sidewall extending along a sidewall of the landing pad190toward the substrate110. As extending toward the substrate110, the sidewall of the insulating structure195is closer to a sidewall of the bit line structure140.

In some embodiments, the first vertical line UCL that extends along the center of the upper end of the insulating structure195with respect to the first horizontal direction (X direction) and the second vertical line LCL that extends along the center of the lower end of the insulating structure195with respect to the first horizontal direction (X direction) may be offset by the center shift distance CL from each other in the first horizontal direction (X direction). For example, the insulating structure195extends from the upper end of the insulating structure195toward the lower end of the insulating structure195. The insulating structure195has the center shift distance CL in the first horizontal direction (X direction) from the landing pad190toward the bit line structure140, and may be bent to extend with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction).

In some embodiments, the center of the lower end of the insulating structure195and the center of the upper end of the air spacer AS may be aligned with each other in the vertical direction (Z direction).

Also, the insulating structure195may have a bottom surface of which at least a portion is substantially flat in the second horizontal direction (Y direction). That is, at least a portion of the top surface of the portion of the insulating fence180that is in contact with the bottom surface of the insulating structure195and the top surface of the portion of the landing pad190may be positioned substantially at the same level along the second horizontal direction (Y direction) with respect to the vertical direction (Z direction).

In this specification, an upper portion of the insulating structure195may refer to a portion between the two neighboring landing pads190, and a lower portion of the insulating structure195may refer to a portion between one landing pad190and the bit line structure140which is spaced apart from and adjacent to the one landing pad190.

A width of the lower portion of the insulating structure195with respect to the first horizontal direction (X direction) may be less than a width of the upper portion of the insulating structure195with respect to the first horizontal direction (X direction). The width of the insulating structure195with respect to the first horizontal direction (X direction) may substantially decrease from the upper end of the insulating structure195toward the lower end of the insulating structure195.

The upper portion of the insulating structure195, which is the portion between the two neighboring landing pads190, extends substantially toward the substrate110in the vertical direction (Z direction). The lower portion of the insulating structure195, which is the portion between one landing pad190and the bit line structure140which is spaced apart from and adjacent to the one landing pad190, is bent from the one landing pad190toward the bit line structure140, which is spaced apart from and adjacent to the one landing pad190, so that the lower portion of the insulating structure195extends toward the substrate110with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the insulating structure195may have a sidewall extending along a sidewall of the landing pad190toward the substrate110. In a direction extending toward the substrate110, the sidewall of the insulating structure195gets closer to a sidewall of the bit line structure140.

The center of the upper end of the insulating structure195with respect to the first horizontal direction (X direction) and the center of the upper end of the air spacer AS are not aligned with each other in the vertical direction (Z direction) but may be shifted a center shift distance CL from each other. For example, the center, in the first horizontal direction (X direction), of the upper end of the insulating structure195and the center, in the first horizontal direction (X direction), of the upper end of the air spacer AS, when viewed in a top down view, are spaced apart from each other by the center shift distance CL in the first horizontal direction (X direction). The center of the lower end of the insulating structure195with respect to the first horizontal direction (X direction) and the center of the upper end of the air spacer AS may be aligned with each other in the vertical direction (Z direction).

In the semiconductor device1according to the inventive concept, the insulating structure195is positioned between the plurality of landing pads190so that the plurality of landing pads190are spaced apart from each other. The insulating structure195, between one landing pad190and the bit line structure140which is spaced apart from and adjacent to the one landing pad190, may be bent from the one landing pad190toward the bit line structure140, which is spaced apart from and adjacent to the one landing pad190, so that the lower portion of the insulating structure195extends toward the substrate110with a slope relative to the first horizontal direction (X direction) and the vertical direction (Z direction). For example, the insulating structure195may have a sidewall extending along a sidewall of the landing pad190toward the substrate110. In a direction extending toward the substrate110, the sidewall of the insulating structure195gets closer to a sidewall of the bit line structure140. The insulating structure195is disposed between the sidewall of the landing pad190and the sidewall of the bit line structure140.

Also, in an embodiment, the width of the lower portion of the insulating structure195with respect to the first horizontal direction (X direction) is smaller than the width of the upper portion of the insulating structure195with respect to the first horizontal direction (X direction). For example, the width of the insulating structure195with respect to the first horizontal direction (X direction) decreases from the upper end of the insulating structure195toward the lower end of the insulating structure195.

Thus, even though the width of the lower portion of the landing pad190covering the sidewall of the bit line structure140, that is, the width of a neck of the landing pad190with respect to the first horizontal direction (X direction) increases, a gap between the two neighboring landing pads190may be secured.

Also, the center of the lower end of the insulating structure195with respect to the first horizontal direction (X direction), which corresponds to the center of the bottom surface of the recess portion190R, may be aligned with the center of the upper end of the air spacer AS in the vertical direction (Z direction). Therefore, before the insulating structure195is formed, the second insulating spacer154(FIGS.8A and8C) may be smoothly removed through the recess portion190R. Thus, the air spacer AS may reduce parasitic capacitance between the plurality of bit lines147. Therefore, the semiconductor device1according to the inventive concept may have improved operation speed and operation reliability.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.