Patent ID: 12192024

DETAILED DESCRIPTION

FIG.1depicts a data center in which disaggregated resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers) includes multiple pods110,120,130,140, a pod being or including one or more rows of racks. Of course, although data center100is shown with multiple pods, in some embodiments, the data center100may be embodied as a single pod. As described in more detail herein, each rack houses multiple sleds, each of which may be primarily equipped with a particular type of resource (e.g., memory devices, data storage devices, accelerator devices, general purpose processors), e.g., resources that can be logically coupled to form a composed node, which can act as, for example, a server. In the illustrative embodiment, the sleds in each pod110,120,130,140are connected to multiple pod switches (e.g., switches that route data communications to and from sleds within the pod). The pod switches, in turn, connect with spine switches150that switch communications among pods (e.g., the pods110,120,130,140) in the data center100. In some embodiments, the sleds may be connected with a fabric using Intel® Omni-Path technology. In other embodiments, the sleds may be connected with other fabrics, such as InfiniBand or Ethernet. As described in more detail herein, resources within sleds in the data center100may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more sleds to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same sled. The resources in a managed node may belong to sleds belonging to different racks, and even to different pods110,120,130,140. As such, some resources of a single sled may be allocated to one managed node while other resources of the same sled are allocated to a different managed node (e.g., one processor assigned to one managed node and another processor of the same sled assigned to a different managed node).

A data center comprising disaggregated resources, such as data center100, can be used in a wide variety of contexts, such as enterprise, government, cloud service provider, and communications service provider (e.g., Telco's), as well in a wide variety of sizes, from cloud service provider mega-data centers that consume over 100,000 sq. ft. to single- or multi-rack installations for use in base stations.

The disaggregation of resources to sleds comprised predominantly of a single type of resource (e.g., compute sleds comprising primarily compute resources, memory sleds containing primarily memory resources), and the selective allocation and deallocation of the disaggregated resources to form a managed node assigned to execute a workload improves the operation and resource usage of the data center100relative to typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources in a single chassis. For example, because sleds predominantly contain resources of a particular type, resources of a given type can be upgraded independently of other resources. Additionally, because different resources types (processors, storage, accelerators, etc.) typically have different refresh rates, greater resource utilization and reduced total cost of ownership may be achieved. For example, a data center operator can upgrade the processors throughout their facility by only swapping out the compute sleds. In such a case, accelerator and storage resources may not be contemporaneously upgraded and, rather, may be allowed to continue operating until those resources are scheduled for their own refresh. Resource utilization may also increase. For example, if managed nodes are composed based on requirements of the workloads that will be running on them, resources within a node are more likely to be fully utilized. Such utilization may allow for more managed nodes to run in a data center with a given set of resources, or for a data center expected to run a given set of workloads, to be built using fewer resources.

FIG.2depicts a pod. A pod can include a set of rows200,210,220,230of racks240. Each rack240may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative embodiment, the racks in each row200,210,220,230are connected to multiple pod switches250,260. The pod switch250includes a set of ports252to which the sleds of the racks of the pod110are connected and another set of ports254that connect the pod110to the spine switches150to provide connectivity to other pods in the data center100. Similarly, the pod switch260includes a set of ports262to which the sleds of the racks of the pod110are connected and a set of ports264that connect the pod110to the spine switches150. As such, the use of the pair of switches250,260provides an amount of redundancy to the pod110. For example, if either of the switches250,260fails, the sleds in the pod110may still maintain data communication with the remainder of the data center100(e.g., sleds of other pods) through the other switch250,260. Furthermore, in the illustrative embodiment, the switches150,250,260may be embodied as dual-mode optical switches, capable of routing both Ethernet protocol communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance link-layer protocol (e.g., PCI Express) via optical signaling media of an optical fabric.

It should be appreciated that each of the other pods120,130,140(as well as any additional pods of the data center100) may be similarly structured as, and have components similar to, the pod110shown in and described in regard toFIG.2(e.g., each pod may have rows of racks housing multiple sleds as described above). Additionally, while two pod switches250,260are shown, it should be understood that in other embodiments, each pod110,120,130,140may be connected to a different number of pod switches, providing even more failover capacity. Of course, in other embodiments, pods may be arranged differently than the rows-of-racks configuration shown inFIGS.1-2. For example, a pod may be embodied as multiple sets of racks in which each set of racks is arranged radially, e.g., the racks are equidistant from a center switch.

Referring now toFIGS.3-5, each illustrative rack240of the data center100includes two elongated support posts302,304, which are arranged vertically. For example, the elongated support posts302,304may extend upwardly from a floor of the data center100when deployed. The rack240also includes one or more horizontal pairs310of elongated support arms312(identified inFIG.3via a dashed ellipse) configured to support a sled of the data center100as discussed below. One elongated support arm312of the pair of elongated support arms312extends outwardly from the elongated support post302and the other elongated support arm312extends outwardly from the elongated support post304.

In the illustrative embodiments, each sled of the data center100is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack240is configured to receive the chassis-less sleds. For example, each pair310of elongated support arms312defines a sled slot320of the rack240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm312includes a circuit board guide330configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide330is secured to, or otherwise mounted to, a top side332of the corresponding elongated support arm312. For example, in the illustrative embodiment, each circuit board guide330is mounted at a distal end of the corresponding elongated support arm312relative to the corresponding elongated support post302,304. For clarity of the Figures, not every circuit board guide330may be referenced in each Figure.

Each circuit board guide330includes an inner wall that defines a circuit board slot380configured to receive the chassis-less circuit board substrate of a sled400when the sled400is received in the corresponding sled slot320of the rack240. To do so, as shown inFIG.4, a user (or robot) aligns the chassis-less circuit board substrate of an illustrative chassis-less sled400to a sled slot320. The user, or robot, may then slide the chassis-less circuit board substrate forward into the sled slot320such that each side edge414of the chassis-less circuit board substrate is received in a corresponding circuit board slot380of the circuit board guides330of the pair310of elongated support arms312that define the corresponding sled slot320as shown inFIG.4. By having robotically accessible and robotically manipulatable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate. Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack240, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. As such, in some embodiments, the data center100may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human may facilitate one or more maintenance or upgrade operations in the data center100.

It should be appreciated that each circuit board guide330is dual sided. That is, each circuit board guide330includes an inner wall that defines a circuit board slot380on each side of the circuit board guide330. In this way, each circuit board guide330can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack240to turn the rack240into a two-rack solution that can hold twice as many sled slots320as shown inFIG.3. The illustrative rack240includes seven pairs310of elongated support arms312that define a corresponding seven sled slots320, each configured to receive and support a corresponding sled400as discussed above. Of course, in other embodiments, the rack240may include additional or fewer pairs310of elongated support arms312(e.g., additional or fewer sled slots320). It should be appreciated that because the sled400is chassis-less, the sled400may have an overall height that is different than typical servers. As such, in some embodiments, the height of each sled slot320may be shorter than the height of a typical server (e.g., shorter than a single rank unit, “1U”). That is, the vertical distance between each pair310of elongated support arms312may be less than a standard rack unit “1U.” Additionally, due to the relative decrease in height of the sled slots320, the overall height of the rack240in some embodiments may be shorter than the height of traditional rack enclosures. For example, in some embodiments, each of the elongated support posts302,304may have a length of six feet or less. Again, in other embodiments, the rack240may have different dimensions. For example, in some embodiments, the vertical distance between each pair310of elongated support arms312may be greater than a standard rack until “1U”. In such embodiments, the increased vertical distance between the sleds allows for larger heat sinks to be attached to the physical resources and for larger fans to be used (e.g., in the fan array370described below) for cooling each sled, which in turn can allow the physical resources to operate at increased power levels. Further, it should be appreciated that the rack240does not include any walls, enclosures, or the like. Rather, the rack240is an enclosure-less rack that is opened to the local environment. Of course, in some cases, an end plate may be attached to one of the elongated support posts302,304in those situations in which the rack240forms an end-of-row rack in the data center100.

In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts302,304. To facilitate such routing, each elongated support post302,304includes an inner wall that defines an inner chamber in which interconnects may be located. The interconnects routed through the elongated support posts302,304may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot320, power interconnects to provide power to each sled slot320, and/or other types of interconnects.

The rack240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot320and is configured to mate with an optical data connector of a corresponding sled400when the sled400is received in the corresponding sled slot320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center100are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable approaches or enters the connector mechanism. Subsequently, the optical fiber inside the cable may enter a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.

The illustrative rack240also includes a fan array370coupled to the cross-support arms of the rack240. The fan array370includes one or more rows of cooling fans372, which are aligned in a horizontal line between the elongated support posts302,304. In the illustrative embodiment, the fan array370includes a row of cooling fans372for each sled slot320of the rack240. As discussed above, each sled400does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array370provides cooling for each sled400received in the rack240. Each rack240, in the illustrative embodiment, also includes a power supply associated with each sled slot320. Each power supply is secured to one of the elongated support arms312of the pair310of elongated support arms312that define the corresponding sled slot320. For example, the rack240may include a power supply coupled or secured to each elongated support arm312extending from the elongated support post302. Each power supply includes a power connector configured to mate with a power connector of the sled400when the sled400is received in the corresponding sled slot320. In the illustrative embodiment, the sled400does not include any on-board power supply and, as such, the power supplies provided in the rack240supply power to corresponding sleds400when mounted to the rack240. Each power supply is configured to satisfy the power requirements for its associated sled, which can vary from sled to sled. Additionally, the power supplies provided in the rack240can operate independent of each other. That is, within a single rack, a first power supply providing power to a compute sled can provide power levels that are different than power levels supplied by a second power supply providing power to an accelerator sled. The power supplies may be controllable at the sled level or rack level, and may be controlled locally by components on the associated sled or remotely, such as by another sled or an orchestrator.

Referring now toFIG.6, the sled400, in the illustrative embodiment, is configured to be mounted in a corresponding rack240of the data center100as discussed above. In some embodiments, each sled400may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, the sled400may be embodied as a compute sled800as discussed below in regard toFIGS.8-9, an accelerator sled1000as discussed below in regard toFIGS.10-11, a storage sled1200as discussed below in regard toFIGS.12-13, or as a sled optimized or otherwise configured to perform other specialized tasks, such as a memory sled1400, discussed below in regard toFIG.14.

As discussed above, the illustrative sled400includes a chassis-less circuit board substrate602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate602is “chassis-less” in that the sled400does not include a housing or enclosure. Rather, the chassis-less circuit board substrate602is open to the local environment. The chassis-less circuit board substrate602may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate602is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate602in other embodiments.

As discussed in more detail below, the chassis-less circuit board substrate602includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate602. As discussed, the chassis-less circuit board substrate602does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled400by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate602is not positioned in an individual housing or enclosure, there is no vertically-arranged backplane (e.g., a backplate of the chassis) attached to the chassis-less circuit board substrate602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate602has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate602. For example, the illustrative chassis-less circuit board substrate602has a width604that is greater than a depth606of the chassis-less circuit board substrate602. In one particular embodiment, for example, the chassis-less circuit board substrate602has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path608that extends from a front edge610of the chassis-less circuit board substrate602toward a rear edge612has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled400. Furthermore, although not illustrated inFIG.6, the various physical resources mounted to the chassis-less circuit board substrate602are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below. That is, no two electrical components, which produce appreciable heat during operation (e.g., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-less circuit board substrate602linearly in-line with each other along the direction of the airflow path608(e.g., along a direction extending from the front edge610toward the rear edge612of the chassis-less circuit board substrate602).

As discussed above, the illustrative sled400includes one or more physical resources620mounted to a top side650of the chassis-less circuit board substrate602. Although two physical resources620are shown inFIG.6, it should be appreciated that the sled400may include one, two, or more physical resources620in other embodiments. The physical resources620may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of the sled400depending on, for example, the type or intended functionality of the sled400. For example, as discussed in more detail below, the physical resources620may be embodied as high-performance processors in embodiments in which the sled400is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which the sled400is embodied as an accelerator sled, storage controllers in embodiments in which the sled400is embodied as a storage sled, or a set of memory devices in embodiments in which the sled400is embodied as a memory sled.

The sled400also includes one or more additional physical resources630mounted to the top side650of the chassis-less circuit board substrate602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled400, the physical resources630may include additional or other electrical components, circuits, and/or devices in other embodiments.

The physical resources620are communicatively coupled to the physical resources630via an input/output (I/O) subsystem622. The I/O subsystem622may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources620, the physical resources630, and/or other components of the sled400. For example, the I/O subsystem622may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, waveguides, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem622is embodied as, or otherwise includes, a double data rate4(DDR4) data bus or a DDR5 data bus.

In some embodiments, the sled400may also include a resource-to-resource interconnect624. The resource-to-resource interconnect624may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect624is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the resource-to-resource interconnect624may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), PCI express (PCIe), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.

The sled400also includes a power connector640configured to mate with a corresponding power connector of the rack240when the sled400is mounted in the corresponding rack240. The sled400receives power from a power supply of the rack240via the power connector640to supply power to the various electrical components of the sled400. That is, the sled400does not include any local power supply (e.g., an on-board power supply) to provide power to the electrical components of the sled400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate602as discussed above. In some embodiments, voltage regulators are placed on a bottom side750(seeFIG.7) of the chassis-less circuit board substrate602directly opposite of the processors820(seeFIG.8), and power is routed from the voltage regulators to the processors820by vias extending through the circuit board substrate602. Such a configuration provides an increased thermal budget, additional current and/or voltage, and better voltage control relative to typical printed circuit boards in which processor power is delivered from a voltage regulator, in part, by printed circuit traces.

In some embodiments, the sled400may also include mounting features642configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled600in a rack240by the robot. The mounting features642may be embodied as any type of physical structures that allow the robot to grasp the sled400without damaging the chassis-less circuit board substrate602or the electrical components mounted thereto. For example, in some embodiments, the mounting features642may be embodied as non-conductive pads attached to the chassis-less circuit board substrate602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate602. The particular number, shape, size, and/or make-up of the mounting feature642may depend on the design of the robot configured to manage the sled400.

Referring now toFIG.7, in addition to the physical resources630mounted on the top side650of the chassis-less circuit board substrate602, the sled400also includes one or more memory devices720mounted to a bottom side750of the chassis-less circuit board substrate602. That is, the chassis-less circuit board substrate602is embodied as a double-sided circuit board. The physical resources620are communicatively coupled to the memory devices720via the I/O subsystem622. For example, the physical resources620and the memory devices720may be communicatively coupled by one or more vias extending through the chassis-less circuit board substrate602. Each physical resource620may be communicatively coupled to a different set of one or more memory devices720in some embodiments. Alternatively, in other embodiments, each physical resource620may be communicatively coupled to each memory device720.

The memory devices720may be embodied as any type of memory device capable of storing data for the physical resources620during operation of the sled400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4. Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A block can be any size such as but not limited to 2 KB, 4 KB, 8 KB, and so forth. A memory device may also include next-generation nonvolatile devices, such as Intel Optane® memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.

Referring now toFIG.8, in some embodiments, the sled400may be embodied as a compute sled800. The compute sled800is optimized, or otherwise configured, to perform compute tasks. Of course, as discussed above, the compute sled800may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks. The compute sled800includes various physical resources (e.g., electrical components) similar to the physical resources of the sled400, which have been identified inFIG.8using the same reference numbers. The description of such components provided above in regard toFIGS.6and7applies to the corresponding components of the compute sled800and is not repeated herein for clarity of the description of the compute sled800.

In the illustrative compute sled800, the physical resources620are embodied as processors820. Although only two processors820are shown inFIG.8, it should be appreciated that the compute sled800may include additional processors820in other embodiments. Illustratively, the processors820are embodied as high-performance processors820and may be configured to operate at a relatively high power rating. Although the processors820generate additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-less circuit board substrate602discussed above facilitate the higher power operation. For example, in the illustrative embodiment, the processors820are configured to operate at a power rating of at least 250 W. In some embodiments, the processors820may be configured to operate at a power rating of at least 350 W.

In some embodiments, the compute sled800may also include a processor-to-processor interconnect842. Similar to the resource-to-resource interconnect624of the sled400discussed above, the processor-to-processor interconnect842may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect842communications. In the illustrative embodiment, the processor-to-processor interconnect842is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the processor-to-processor interconnect842may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications (e.g., PCIe).

The compute sled800also includes a communication circuit830. The illustrative communication circuit830includes a network interface controller (NIC)832, which may also be referred to as a host fabric interface (HFI). The NIC832may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, or other devices that may be used by the compute sled800to connect with another compute device (e.g., with other sleds400). In some embodiments, the NIC832may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC832may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC832. In such embodiments, the local processor of the NIC832may be capable of performing one or more of the functions of the processors820. Additionally or alternatively, in such embodiments, the local memory of the NIC832may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels. In some examples, a network interface includes a network interface controller or a network interface card. In some examples, a network interface can include one or more of a network interface controller (NIC)832, a host fabric interface (HFI), a host bus adapter (HBA), network interface connected to a bus or connection (e.g., PCIe, CXL, DDR, and so forth). In some examples, a network interface can be part of a switch or a system-on-chip (SoC).

The communication circuit830is communicatively coupled to an optical data connector834. The optical data connector834is configured to mate with a corresponding optical data connector of the rack240when the compute sled800is mounted in the rack240. Illustratively, the optical data connector834includes a plurality of optical fibers which lead from a mating surface of the optical data connector834to an optical transceiver836. The optical transceiver836is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector834in the illustrative embodiment, the optical transceiver836may form a portion of the communication circuit830in other embodiments.

In some embodiments, the compute sled800may also include an expansion connector840. In such embodiments, the expansion connector840is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled800. The additional physical resources may be used, for example, by the processors820during operation of the compute sled800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate602discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.

Referring now toFIG.9, an illustrative embodiment of the compute sled800is shown. As shown, the processors820, communication circuit830, and optical data connector834are mounted to the top side650of the chassis-less circuit board substrate602. Any suitable attachment or mounting technology may be used to mount the physical resources of the compute sled800to the chassis-less circuit board substrate602. For example, the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets. In some cases, some of the electrical components may be directly mounted to the chassis-less circuit board substrate602via soldering or similar techniques.

As discussed above, the individual processors820and communication circuit830are mounted to the top side650of the chassis-less circuit board substrate602such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors820and communication circuit830are mounted in corresponding locations on the top side650of the chassis-less circuit board substrate602such that no two of those physical resources are linearly in-line with others along the direction of the airflow path608. It should be appreciated that, although the optical data connector834is in-line with the communication circuit830, the optical data connector834produces no or nominal heat during operation.

The memory devices720of the compute sled800are mounted to the bottom side750of the of the chassis-less circuit board substrate602as discussed above in regard to the sled400. Although mounted to the bottom side750, the memory devices720are communicatively coupled to the processors820located on the top side650via the I/O subsystem622. Because the chassis-less circuit board substrate602is embodied as a double-sided circuit board, the memory devices720and the processors820may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate602. Of course, each processor820may be communicatively coupled to a different set of one or more memory devices720in some embodiments. Alternatively, in other embodiments, each processor820may be communicatively coupled to each memory device720. In some embodiments, the memory devices720may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate602and may interconnect with a corresponding processor820through a ball-grid array.

Each of the processors820includes a heatsink850secured thereto. Due to the mounting of the memory devices720to the bottom side750of the chassis-less circuit board substrate602(as well as the vertical spacing of the sleds400in the corresponding rack240), the top side650of the chassis-less circuit board substrate602includes additional “free” area or space that facilitates the use of heatsinks850having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate602, none of the processor heatsinks850include cooling fans attached thereto. That is, each of the heatsinks850is embodied as a fan-less heatsink. In some embodiments, the heat sinks850mounted atop the processors820may overlap with the heat sink attached to the communication circuit830in the direction of the airflow path608due to their increased size, as illustratively suggested byFIG.9.

Referring now toFIG.10, in some embodiments, the sled400may be embodied as an accelerator sled1000. The accelerator sled1000is configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task. In some embodiments, for example, a compute sled800may offload tasks to the accelerator sled1000during operation. The accelerator sled1000includes various components similar to components of the sled400and/or compute sled800, which have been identified inFIG.10using the same reference numbers. The description of such components provided above in regard toFIGS.6,7, and8apply to the corresponding components of the accelerator sled1000and is not repeated herein for clarity of the description of the accelerator sled1000.

In the illustrative accelerator sled1000, the physical resources620are embodied as accelerator circuits1020. Although only two accelerator circuits1020are shown inFIG.10, it should be appreciated that the accelerator sled1000may include additional accelerator circuits1020in other embodiments. For example, as shown inFIG.11, the accelerator sled1000may include four accelerator circuits1020in some embodiments. The accelerator circuits1020may be embodied as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations. For example, the accelerator circuits1020may be embodied as, for example, central processing units, cores, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), programmable control logic (PCL), security co-processors, graphics processing units (GPUs), neuromorphic processor units, quantum computers, machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.

In some embodiments, the accelerator sled1000may also include an accelerator-to-accelerator interconnect1042. Similar to the resource-to-resource interconnect624of the sled600discussed above, the accelerator-to-accelerator interconnect1042may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect1042is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the accelerator-to-accelerator interconnect1042may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits1020may be daisy-chained with a primary accelerator circuit1020connected to the NIC832and memory720through the I/O subsystem622and a secondary accelerator circuit1020connected to the NIC832and memory720through a primary accelerator circuit1020.

Referring now toFIG.11, an illustrative embodiment of the accelerator sled1000is shown. As discussed above, the accelerator circuits1020, communication circuit830, and optical data connector834are mounted to the top side650of the chassis-less circuit board substrate602. Again, the individual accelerator circuits1020and communication circuit830are mounted to the top side650of the chassis-less circuit board substrate602such that no two heat-producing, electrical components shadow each other as discussed above. The memory devices720of the accelerator sled1000are mounted to the bottom side750of the of the chassis-less circuit board substrate602as discussed above in regard to the sled600. Although mounted to the bottom side750, the memory devices720are communicatively coupled to the accelerator circuits1020located on the top side650via the I/O subsystem622(e.g., through vias). Further, each of the accelerator circuits1020may include a heatsink1070that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks870, the heatsinks1070may be larger than traditional heatsinks because of the “free” area provided by the memory resources720being located on the bottom side750of the chassis-less circuit board substrate602rather than on the top side650.

Referring now toFIG.12, in some embodiments, the sled400may be embodied as a storage sled1200. The storage sled1200is configured, to store data in a data storage1250local to the storage sled1200. For example, during operation, a compute sled800or an accelerator sled1000may store and retrieve data from the data storage1250of the storage sled1200. The storage sled1200includes various components similar to components of the sled400and/or the compute sled800, which have been identified inFIG.12using the same reference numbers. The description of such components provided above with regard toFIGS.6,7, and8apply to the corresponding components of the storage sled1200and is not repeated herein for clarity of the description of the storage sled1200.

In the illustrative storage sled1200, the physical resources620are embodied as storage controllers1220. Although only two storage controllers1220are shown inFIG.12, it should be appreciated that the storage sled1200may include additional storage controllers1220in other embodiments. The storage controllers1220may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into the data storage1250based on requests received via the communication circuit830. In the illustrative embodiment, the storage controllers1220are embodied as relatively low-power processors or controllers. For example, in some embodiments, the storage controllers1220may be configured to operate at a power rating of about 75 watts.

In some embodiments, the storage sled1200may also include a controller-to-controller interconnect1242. Similar to the resource-to-resource interconnect624of the sled400discussed above, the controller-to-controller interconnect1242may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect1242is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the controller-to-controller interconnect1242may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.

Referring now toFIG.13, an illustrative embodiment of the storage sled1200is shown. In the illustrative embodiment, the data storage1250is embodied as, or otherwise includes, a storage cage1252configured to house one or more solid state drives (SSDs)1254. To do so, the storage cage1252includes a number of mounting slots1256, each of which is configured to receive a corresponding solid state drive1254. Each of the mounting slots1256includes a number of drive guides1258that cooperate to define an access opening1260of the corresponding mounting slot1256. The storage cage1252is secured to the chassis-less circuit board substrate602such that the access openings face away from (e.g., toward the front of) the chassis-less circuit board substrate602. As such, solid state drives1254are accessible while the storage sled1200is mounted in a corresponding rack204. For example, a solid state drive1254may be swapped out of a rack240(e.g., via a robot) while the storage sled1200remains mounted in the corresponding rack240.

The storage cage1252illustratively includes sixteen mounting slots1256and is capable of mounting and storing sixteen solid state drives1254. Of course, the storage cage1252may be configured to store additional or fewer solid state drives1254in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage1252, but may be mounted in the storage cage1252in a different orientation in other embodiments. Each solid state drive1254may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives1254may include volatile and non-volatile memory devices discussed above.

As shown inFIG.13, the storage controllers1220, the communication circuit830, and the optical data connector834are illustratively mounted to the top side650of the chassis-less circuit board substrate602. Again, as discussed above, any suitable attachment or mounting technology may be used to mount the electrical components of the storage sled1200to the chassis-less circuit board substrate602including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques.

As discussed above, the individual storage controllers1220and the communication circuit830are mounted to the top side650of the chassis-less circuit board substrate602such that no two heat-producing, electrical components shadow each other. For example, the storage controllers1220and the communication circuit830are mounted in corresponding locations on the top side650of the chassis-less circuit board substrate602such that no two of those electrical components are linearly in-line with each other along the direction of the airflow path608.

The memory devices720of the storage sled1200are mounted to the bottom side750of the of the chassis-less circuit board substrate602as discussed above in regard to the sled400. Although mounted to the bottom side750, the memory devices720are communicatively coupled to the storage controllers1220located on the top side650via the I/O subsystem622. Again, because the chassis-less circuit board substrate602is embodied as a double-sided circuit board, the memory devices720and the storage controllers1220may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate602. Each of the storage controllers1220includes a heatsink1270secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate602of the storage sled1200, none of the heatsinks1270include cooling fans attached thereto. That is, each of the heatsinks1270is embodied as a fan-less heatsink.

Referring now toFIG.14, in some embodiments, the sled400may be embodied as a memory sled1400. The storage sled1400is optimized, or otherwise configured, to provide other sleds400(e.g., compute sleds800, accelerator sleds1000, etc.) with access to a pool of memory (e.g., in two or more sets1430,1432of memory devices720) local to the memory sled1200. For example, during operation, a compute sled800or an accelerator sled1000may remotely write to and/or read from one or more of the memory sets1430,1432of the memory sled1200using a logical address space that maps to physical addresses in the memory sets1430,1432. The memory sled1400includes various components similar to components of the sled400and/or the compute sled800, which have been identified inFIG.14using the same reference numbers. The description of such components provided above in regard toFIGS.6,7, and8apply to the corresponding components of the memory sled1400and is not repeated herein for clarity of the description of the memory sled1400.

In the illustrative memory sled1400, the physical resources620are embodied as memory controllers1420. Although only two memory controllers1420are shown inFIG.14, it should be appreciated that the memory sled1400may include additional memory controllers1420in other embodiments. The memory controllers1420may be embodied as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets1430,1432based on requests received via the communication circuit830. In the illustrative embodiment, each memory controller1420is connected to a corresponding memory set1430,1432to write to and read from memory devices720within the corresponding memory set1430,1432and enforce any permissions (e.g., read, write, etc.) associated with sled400that has sent a request to the memory sled1400to perform a memory access operation (e.g., read or write).

In some embodiments, the memory sled1400may also include a controller-to-controller interconnect1442. Similar to the resource-to-resource interconnect624of the sled400discussed above, the controller-to-controller interconnect1442may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect1442is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem622). For example, the controller-to-controller interconnect1442may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller1420may access, through the controller-to-controller interconnect1442, memory that is within the memory set1432associated with another memory controller1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers1420may implement a memory interleave (e.g., one memory address is mapped to the memory set1430, the next memory address is mapped to the memory set1432, and the third address is mapped to the memory set1430, etc.). The interleaving may be managed within the memory controllers1420, or from CPU sockets (e.g., of the compute sled800) across network links to the memory sets1430,1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.

Further, in some embodiments, the memory sled1400may be connected to one or more other sleds400(e.g., in the same rack240or an adjacent rack240) through a waveguide, using the waveguide connector1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (e.g., receive) lanes and 16 Tx (e.g., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 GHz or 32 GHz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets1430,1432) to another sled (e.g., a sled400in the same rack240or an adjacent rack240as the memory sled1400) without adding to the load on the optical data connector834.

Referring now toFIG.15, a system for executing one or more workloads (e.g., applications) may be implemented in accordance with the data center100. In the illustrative embodiment, the system1510includes an orchestrator server1520, which may be embodied as a managed node comprising a compute device (e.g., a processor820on a compute sled800) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled to multiple sleds400including a large number of compute sleds1530(e.g., each similar to the compute sled800), memory sleds1540(e.g., each similar to the memory sled1400), accelerator sleds1550(e.g., each similar to the memory sled1000), and storage sleds1560(e.g., each similar to the storage sled1200). One or more of the sleds1530,1540,1550,1560may be grouped into a managed node1570, such as by the orchestrator server1520, to collectively perform a workload (e.g., an application1532executed in a virtual machine or in a container). The managed node1570may be embodied as an assembly of physical resources620, such as processors820, memory resources720, accelerator circuits1020, or data storage1250, from the same or different sleds400. Further, the managed node may be established, defined, or “spun up” by the orchestrator server1520at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. In the illustrative embodiment, the orchestrator server1520may selectively allocate and/or deallocate physical resources620from the sleds400and/or add or remove one or more sleds400from the managed node1570as a function of quality of service (QoS) targets (e.g., a target throughput, a target latency, a target number instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application1532). In doing so, the orchestrator server1520may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in each sled400of the managed node1570and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. The orchestrator server1520may additionally determine whether one or more physical resources may be deallocated from the managed node1570while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, the orchestrator server1520may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application1532) while the workload is executing. Similarly, the orchestrator server1520may determine to dynamically deallocate physical resources from a managed node if the orchestrator server1520determines that deallocating the physical resource would result in QoS targets still being met.

Additionally, in some embodiments, the orchestrator server1520may identify trends in the resource utilization of the workload (e.g., the application1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application1532) and pre-emptively identifying available resources in the data center100and allocating them to the managed node1570(e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server1520may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center100. For example, the orchestrator server1520may utilize a model that accounts for the performance of resources on the sleds400(e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server1520may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center100(e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled400on which the resource is located).

In some embodiments, the orchestrator server1520may generate a map of heat generation in the data center100using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds400and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center100. Additionally or alternatively, in some embodiments, the orchestrator server1520may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center100and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server1520may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center100. In some embodiments, the orchestrator server1520may identify patterns in resource utilization phases of the workloads and use the patterns to predict future resource utilization of the workloads.

To reduce the computational load on the orchestrator server1520and the data transfer load on the network, in some embodiments, the orchestrator server1520may send self-test information to the sleds400to enable each sled400to locally (e.g., on the sled400) determine whether telemetry data generated by the sled400satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled400may then report back a simplified result (e.g., yes or no) to the orchestrator server1520, which the orchestrator server1520may utilize in determining the allocation of resources to managed nodes.

DMA Engine

In a distributed memory architecture, hyperconverged shared memory solutions provide sharing of memory that is directly attached to a central processing unit (CPU). This architecture can create a dependence between the memory that is allocated to the local host and the memory allocated to a remote host and may not enable the host to have its own memory space that is completely isolated from access by devices other than the host. This architecture may not provide isolation of use of the local memory between a local node and remote nodes.

In a cloud environment, the performance of a local host's application can be impacted by the remote hosts accessing the memory used by the application. For example, a noisy neighbor problem can arise in a virtualized environment as the host's memory is shared by tenants on the host as well as tenants from remote hosts and any of the tenants may utilize memory to the detriment of unavailability of memory for use by other tenants.

In a bare metal hosted environment, where a CPU is entirely rented to a tenant, a trusted hypervisor may not run on the CPU to enforce security isolation between the local host accessing the CPU's direct attached memory and a remote host accessing the same. Security and confidentiality of data available to a tenant may be compromised as the data may be accessed by another tenant.

Various embodiments provide sharing of a local memory as part of a distributed memory pool across a network or fabric by use of a smart controller or network interface controller (NIC) to manage use of the local memory. Various embodiments provide for sharing of local memory to a local host or a remote host using the smart controller or NIC. Various embodiments provide a network or fabric-attached smart controller to access host physical memory using a high speed interface and the physical memory can be allocated, by the smart controller or NIC, to the host and devices connected to a network or fabric. The smart controller or NIC can be within an infrastructure provider's trust and management domain and can attempt to provide both performance and security isolation between local and remote hosts by providing address translation and quality of service (QoS) specific to the tenants (or hosts).

FIG.16depicts an example of memory pools accessible by a computing node. A system topology can include N compute nodes connected to M memory pool nodes, where N and M are integers and can be the same or different values. Memory pool nodes can provide some of the memory used by the N compute nodes and a remainder of the compute node's memory needs may be met by local memory. Partitioning of memory in memory pool nodes between or assigned to the N compute nodes can be managed by system software (e.g., OS, hypervisor (e.g., Linux, VMware ESX, Windows Hyper-V), orchestrator (e.g., Kubernetes, OpenStack, Slurm (High Performance Computing (HPC)), Open Source NFV Management and Orchestration (MANO) from European Telecommunications Standards Institute (ETSI)'s Open Source Mano (OSM) group), pod manager, or traffic manager on a same or different host node, fabric manager (e.g., CXL fabric manager).

Compute node1600can be coupled to any memory pool node1650using a network or fabric. Memory pool node1650can include a network or fabric interface, compute resources (e.g., CPUs or accelerators), and memory resources (e.g., memory, storage, or cache). Although this example shows merely one compute node coupled to multiple memory pool nodes, multiple compute nodes can be coupled to multiple memory pool nodes.

Compute node1600can include a network or fabric interface (e.g., network interface1604), compute resources (e.g., CPUs or accelerators), and memory resources (e.g., memory1608, storage, or cache). For example, compute node1600can execute workloads or applications. For example, compute node1600can be implemented as a server, rack of servers, computing platform, or others. In some examples, a host node can include one or more of: CPUs1606, a core, graphics processing unit (GPU), field programmable gate array (FPGA), or application specific integrated circuit (ASIC). In some examples, a core can be sold or designed by Intel®, ARM®, AMD®, Qualcomm®, IBM®, Texas Instruments®, among others. Any processor can execute an operating system, driver, applications, and/or a virtualized execution environment (VEE) (e.g., virtual machine or container). In some examples, an operating system (OS) can be Linux®, Windows®, FreeBSD®, Android®, MacOS®, iOS®, or any other operating system.

Memory1608can include one or more of: one or more registers, one or more cache devices (e.g., level 1 cache (L1), level 2 cache (L2), level 3 cache (L3), lower level cache (LLC)), volatile memory device, non-volatile memory device, or persistent memory device. For example, memory1608can include static random access memory (SRAM) memory technology or memory technology consistent with high bandwidth memory (HBM), or double data rate (DDRx, where x is an integer), among others. Memory1608can be connected to network interface1604using a high speed interface (e.g., DDR, CXL (e.g., Compute Express Link Specification revision 2.0, version 0.9 (2020), as well as earlier versions, revisions or variations thereof), Peripheral Component Interconnect express (PCIe) (e.g., PCI Express Base Specification 1.0 (2002), as well as earlier versions, revisions or variations thereof).

In some examples, memory1608can be accessed by CPUs1606and/or network interface1604using a device interface (e.g., PCIe) or memory interface (e.g., DDR, CXL). In some examples, memory1608are coupled to CPUs1606and/or network interface1604using conductive leads of one or more circuit boards. In some examples, memory1608is part of a same system on chip (SoC) as CPUs1606and/or network interface1604.

According to various embodiments, network interface1604can include one or more cores, graphics processing unit (GPU), field programmable gate array (FPGA), or application specific integrated circuit (ASIC). Network interface1604can provide network interface capabilities to generate or decode packets transmitted or received from a network or fabric. According to various embodiments, network interface1604can be configured to manage access to memory1608or portions of any of memory pools1650-0to1650-M−1 by software executing on CPUs1606and CPUs1654-0to1654-M−1 or other devices (e.g., accelerators, GPUs, and so forth). For example, network interface1604can partition memory1608dynamically and allocate those partitions to both local attached host(s) and/or fabric attached hosts (e.g., one or more compute nodes such as compute node1600).

Network interface1604or one or more of network interfaces1652-0to1652-M−1 can be part of different Infrastructure Processing Units (IPUs) or data processing units (DPUs). An IPU or DPU can include a SmartNlC with one or more programmable or fixed function processors to perform offload of operations that could have been performed by a CPU. The IPU or DPU can include one or more memory devices. In some examples, the IPU or DPU can perform virtual switch operations, manage storage transactions (e.g., compression, cryptography, virtualization), and manage operations performed on other IPUs or DPUs, servers, or devices.

In some examples, network interface1604or one or more of network interfaces1652-0to1652-M−1 can be within a domain of trust whereby a memory access request issued by one of network interface1604or one or more of network interfaces1652-0to1652-M−1 can be permitted to access data in a memory device managed by another of network interface1604or one or more of network interfaces1652-0to1652-M−1. In some examples, some, but not all, of network interface1604or one or more of network interfaces1652-0to1652-M−1 are within a domain of trust. In some examples, where network interfaces are within a domain of trust, a network interface that receives a memory access request can forward the memory access request to another network interface to perform if the memory access request is associated with memory managed by the memory access request. In some examples, where network interfaces are within a domain of trust, a network interface can allocate memory within a memory device locally connected to another network interface within the domain of trust.

For example, network interface1604can authenticate hosts using fabric specific mechanisms and ensure security for communications between any host and network interface1604such as IP security (IPSec), Transport Layer Security (TLS), link encryption, or access control list (ACL). In some examples, network interface1604can use fabric-specific protocols to expose access to memory1608via a network fabric to other hosts or memory pool nodes (e.g., nodes1650-0to1650-M−1) such as remote direct memory access (RDMA), CXL-over-Ethernet, or a custom protocol. For example, network interface1604can have at least one core or processor to be able to run a management stack to provision, manage and monitor memory1608and the controller's operation (e.g., network operations on the fabric, telemetry, etc.). For example, network interface1604can enforce per host Quality-of-Service and access right enforcement so that priority can be granted to access memory1608to some hosts or applications executed thereon over other hosts or applications executed thereon. In some examples, network interface1604can operate in stand-alone mode (e.g., node1650-1) where it is not attached to a host but contains or is connected to memory1608that is made available on the fabric for other hosts or memory pool nodes.

In a similar manner, where allocated, any of network interfaces1652-0to1652-M−1 can provide access to respective memory pools1656-0to1656-M−1 to its node or other nodes. In other words, any network interface can be provisioned to provide access to locally attached memory to any other requester including a requester on its own platform. Any of memory pools1656-0to1656-M−1 can include one or more of: one or more registers, one or more cache devices (e.g., level 1 cache (L1), level 2 cache (L2), level 3 cache (L3), lower level cache (LLC)), volatile memory device, non-volatile memory device, or persistent memory device.

Any of memory pool nodes1650-0to1650-M−1 can include respective network interfaces1652-0to1652-M−1 to communicate with any other memory pool node or compute node1600as a remote device through one or more routers or switches. In this example, memory pool node1650-0can include a network interface1652-0coupled to memory pool1656-0using a high speed interface (e.g., DDRx, CXL, PCIe). Network interface1652-0can manage use of memory pool1656-0by CPUs1654-0of the same memory pool node or a different memory pool node or compute node1600. In this example, memory pool node1650-M−1 can include a network interface1652-M−1 coupled to CPUs1654-M−1. CPUs1654-M−1 can be coupled to memory pool1656-M−1 using a high speed interface (e.g., DDRx, CXL, PCIe).

A memory access request (e.g., read, write, read-modify-write) can be issued by an application, virtualized execution environment (VEE) (e.g., virtual machine or container), operating system (OS) or other software executed by CPUs1606, CPUs1654-0to1654-M−1, or other device such as an accelerator device. Content stored in any memory device can include data, metadata, and/or executable instructions. Network interface1604can direct the memory access request to the applicable memory device (e.g., memory1608or any of memory pools1656-0to1656-M−1). Network interface1604can receive memory access requests from any host and determine where to route the memory request. Network interface1604can arbitrate requests for data from hosts (inbound and outbound).

Some examples of network interface1604or network interfaces1652-0to1652-M−1 can include a DMA engine that provides data mover and transformation operations. For example, a DMA engine can validate CRC or checksum values in connection with storage and networking applications. For example, the DMA engine can perform memory compare and delta generation or merge to support VM or container migration, VM or container check-pointing (e.g., to revert a VM or container to a previous state) and software managed memory deduplication usages.

DMA is a technology that allows an input/output (I/O) device to bypass a central processing unit (CPU) or core, and to send or receive data directly to or from a system memory. Because DMA allows the CPU or core to not manage a copy operation when sending or receiving data to or from the system memory, the CPU or core can be available to perform other operations. Without DMA, when the CPU or core is using programmed input/output, the CPU or core is typically occupied for the entire duration of a read or write operation and is unavailable to perform other work. With DMA, the CPU or core can, for example, initiate a data transfer, and then perform other operations while the data transfer is in progress. The CPU or core can receive an interrupt from a DMA controller when the data transfer is finished.

High speed interconnects can be used to couple a compute node1600and memory pool nodes1650-0to1650-M−1 such as one or more of: Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect express (PCIe), Intel QuickPath Interconnect (QPI), Intel® Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omnipath, Compute Express Link (CXL), HyperTransport, high-speed fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), Infinity Fabric (IF), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof. In some examples, data can be copied or stored to virtualized storage nodes using protocols such as Non-Volatile Memory Express (NVMe) or NVMe over fabrics (NVMe-oF) (or iSCSI storage command generation). For example, NVMe-oF is described at least in NVM Express, Inc., “NVM Express Over Fabrics,” Revision 1.0, Jun. 5, 2016, and specifications referenced therein and variations and revisions thereof.

FIG.17shows a system of pooled memory and local memory shared with a cluster of hosts using distributed physical memory behind network interfaces1702-0to1702-N (e.g., smart controllers) (where N is an integer). In some examples, any of network interfaces1702-0to1702-N can be attached to a different host clusters (e.g., a host cluster includes one or more of hosts 0 an X) (e.g., servers) using a high speed interface (e.g., CXL, DDRx, PCIe). For example, a host can issue a memory access request using a device interface (e.g., PCIe) or memory interface (e.g., CXL or DDRx). Host clusters can be attached to fabric attached memories (FAMs) via a fabric (e.g., CXL.mem compatible, Ethernet, or others) to allow for memory to be pooled or shared among host clusters. In some examples, network interfaces1702-0to1702-N can contain or provide access to one or more physical memory devices (shown as mem) (e.g., DDRx DRAM, DDR-T Optane or CXL Optane) that can be exposed to one or more of the fabric attached host clusters, or subsets thereof.

Fabric Attached Memory (FAM) can refer to a network interface that exists in stand-alone mode that is not attached to a host but is attached to one or more memory devices. Memory in a FAM can be made available via the fabric to other host clusters. In some examples, memory technology and devices in FAM can be higher latency and/or cheaper than memory technology and devices in memory locally attached to a smart controller and hosts so that a memory hierarchy provides near memory in the memory devices and the far memory in the FAMs. For example, latency of access to a FAM can include packet formation and packet decoding for communication over a fabric or network as well as fabric or network media latency. For example, a central management entity (e.g., orchestrator) can allocate memory and storage devices that a smart controller can configure and allocate to use. Various embodiments provide composable memory devices with different tiers and capacities of memory such as composable fast memory and composable high capacity low cost memory that is fabric attached.

Various embodiments provide a scalable but performant architecture for pooled memory deployments. Various embodiments provide memory available to a host that can be dynamically provisioned with high performance near memory and lower cost high capacity memory (e.g., FAM) via a fabric. In some examples, if a smart controller is modular, it can be upgraded independent of the server that it is attached to. In some examples, more memory (e.g., FAM) can be added to any pool by adding FAMs without needing to add servers.

In some examples, a memory address range can correspond with a particular latency level. For example, memory address range x0000 0000 to x0000 1000 can correspond to lower latency fast memory attached to a smart controller whereas address range x1000 0000 to x1000 1000 can correspond to higher latency FAM memory devices. Note that a FAM may appear as higher latency to a host because of latency arising from transmission across a fabric and receipt of responses (e.g., fabric communication-related latency).

The following provides examples of memory allocations. For example, an application developer, hypervisor, or operating system (OS) can choose which memory device to use to store data. An application can tag data with a priority tag to hint at whether to choose fast local memory or higher latency pooled memory where pooled memory and fast memory are available for use by application. For example, a database application can utilize pooled memory or artificial intelligence (AI) applications can utilize fast local memory. Some virtual machines (VMs) have time sensitive requirements for access to data.

Non-uniform memory access (NUMA) techniques can be used by an application whereby the application can specify priority of data with NUMA tags. NUMA tags can be available in NUMA aware libraries such as from Windows, Linux, iOS, VMWare, etc.

FIG.18depicts an example smart controller. In this example, various circuitry within a smart controller are shown. For example, memory address partitioning1802can allocate one or more memory addresses in a local memory attached to memory interface1850or a memory device attached to fabric interface1852for use by one or more requesters. A requester can be any of an application, virtual machine, container, CPU, GPU, accelerator, or any device. The requester can be associated with a processing identifier (PASID) to identify unique requesters. The requester can be executed on a server connected via host interface1856or a server connected via a fabric through fabric interface1852.

Authentication and security circuitry1804can authenticate a requester to determine if the requester is permitted to access a region of memory managed by smart controller1800. Smart controller1800can deny any memory access request or memory allocation request from any requester that is not permitted to access a requested region of memory. In some examples, authentication and security circuitry1804can negotiate and establish a secure connection with a requester so that memory access requests and data can be transferred using a secure connection such as TLS, IPSec, or link encryption.

Quality of service enforcement circuitry1806can regulate quality of service among multiple requesters so that more memory and/or more memory bandwidth can be allocated to higher priority level requesters than to lower priority level requesters. Quality of service enforcement circuitry1806can regulate quality of service among multiple requesters so that higher priority level requesters can receive responses to their memory access requests sooner than lower priority level requesters. In some examples, quality of service enforcement circuitry1806can regulate data transfer rates to be no more or no less than levels assigned to a particular priority level.

Management controller1808can provision, manage and monitor operation of smart controller and various memory devices. Some examples are memory allocation and assignment to one or more hosts, physical memory attribute enumeration (e.g., capacity, latency etc.), fabric-specific node configuration (e.g., IP addresses of nodes), etc.

In some examples, memory can be allocated to applications at boot time. For example, when a system powers on, an orchestrator or CXL fabric manager can configure smart controller1800to map a host to memory regions. The host can be allocated certain amount of addressable memory locations in local memory and FAM by a Basic Input/Output System (BIOS) or other firmware reading registers.

In some examples, a data center orchestrator can allocate virtual machines (VMs) or containers to execute on hosts. An orchestrator can distribute memory to hosts based on knowledge of memory utilized by deployed VMs. The orchestrator can increase or decrease available local memory and FAM based on deployed VMs.

In some examples, more memory can be added for access by one or more hosts. An orchestrator or CXL fabric memory can request smart controller for memory and smart controller1800can make more memory available for use by one or more hosts. An Orchestrator or CXL fabric manager can allocate more to the host. In some examples, memory can be removed and smart controller1800can reduce an amount of memory (e.g., bytes) allocated to one or more host devices.

FIG.19depicts an example process. The process can be performed at least by a network interface or smart controller. At1902, a network interface controller can be configured with permitted requesters and allocated memory devices and addresses. For example, an orchestrator or data center administrator can configure the network interface controller with available memory addresses and permitted requesters that are able to allocate use of memory addresses or an amount of memory and access memory (e.g., read, write).

At1904, a determination can be made if a memory request is received. For example, a memory request can include a request to allocate an amount of memory from a requester or a request to access memory from a requester. If a memory request is not received, the process can repeat1904. If a memory request is received, the process can proceed to1906. At1906, a determination can be made if a memory configuration change is received in the memory request from an entity permitted to change or set the memory configuration. If a memory configuration change is received, the process proceeds to1902to update or re-configure available memory (e.g., increase or decrease or add or remove memory devices) and/or permitted requesters (e.g., add or remove) in accordance with the memory configuration change. If a memory configuration request is not received in the memory request, the process can proceed to1910.

At1910, a determination can be made if a requester is permitted to make a memory request. For example, if the memory request is a memory access request, a determination can be made if the memory access request to a memory address is permitted. For example, if the memory request is a memory allocation request, a determination can be made if the memory allocation request to allocate a region of memory addresses is permitted. For example, if the memory access request or memory allocation request from the requester is permitted for the memory requested to be accessed or an amount of memory requested to be allocated or type of memory (e.g., lower latency versus higher latency) to allocate are permitted, the request can be permitted. If the memory request is permitted, the process can proceed to1912. If the memory request is not permitted, the process can proceed to1920.

At1912, the network interface can perform the memory request. In a case where the memory request is a memory access request (e.g., read, write, or read-modify-write), the network interface controller can transfer the memory access request to the applicable memory device. For example, if the memory device is a locally attached device, the network interface can provide the memory access request to the memory device through a memory or device interface. Examples of memory interfaces include DDRx, CXL, PCIe and so forth. For example, if the memory device is a device accessible through a network, the network interface can transmit the memory access request to the memory device using one or more packets through a fabric or network.

If the memory request is a request to allocate memory, the network interface can allocate the requested memory up to applicable limits such as configured limitations on amount of memory, latency level of memory, and others. In some examples, the memory can be thinly provisioned. Under memory thin provisioning, physical storage resources initially allocated to application programs are less than virtual storage resources allocated to application programs or other software. Under provisioning or thin provisioning can be a memory allocation allocated to a processor (e.g., an executed a virtual execution environment or executed application) being greater than an actual amount of physical addressable memory allocated among the memory and/or the memory pool to the processor. When the physical storage resources allocated to the application programs cannot meet needs of application programs, physical storage resources are gradually added until the physical storage resources reach the virtual storage resources. An application program only needs to manage the declared virtual storage resources. Accordingly, a smaller physical storage resource may be used to support a larger virtual storage resource, thereby improving use efficiency of the physical storage resources.

At1914, the network interface can provide a response to the memory request. If the memory request is a memory access request to a local memory device, the network interface can provide a response such as data, for a read request, or an acknowledgement of completion, for a write request. If the memory request is a memory access request to a remote memory device, the network interface can provide a response (e.g., data or acknowledgement of write completion). In cases of redirection of a memory access request received by a memory node to another memory node (such as when the receiver memory node does not include the target memory device), the network interface that received the memory request can respond to the requester (host) but wait for the response from the remote node that received the re-directed or forwarded request. For example, if A=host, B=IPU, and C=IPU, then if A sends a memory access request to B but the request can be served by C, B forwards the memory access request to C, C responds to B and B responds to A. In some examples, C could respond to A if A, B, and C are connected to the same fabric and A-C are in same trust group.

At1920, the memory request can be denied. In some examples, an administrator or orchestrator can be informed of the declined request and the request made.

FIG.20depicts a network interface that can use embodiments or be used by embodiments. In some embodiments, network interface an include capability to allocate memory and forward memory requests to target memory devices in accordance with embodiments described herein. In some examples, network interface2000can be implemented as a network interface controller, network interface card, a host fabric interface (HFI), or host bus adapter (HBA), and such examples can be interchangeable. Network interface2000can be coupled to one or more servers using a bus, PCIe, CXL, or DDR. Network interface2000may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors.

Network interface2000can include transceiver2002, processors2004, transmit queue2006, receive queue2008, memory2010, and bus interface2012, and DMA engine2052. Transceiver2002can be capable of receiving and transmitting packets in conformance with the applicable protocols such as Ethernet as described in IEEE 802.3, although other protocols may be used. Transceiver2002can receive and transmit packets from and to a network via a network medium (not depicted). Transceiver2002can include PHY circuitry2014and media access control (MAC) circuitry2016. PHY circuitry2014can include encoding and decoding circuitry (not shown) to encode and decode data packets according to applicable physical layer specifications or standards. MAC circuitry2016can be configured to perform MAC address filtering on received packets, process MAC headers of received packets by verifying data integrity, remove preambles and padding, and provide packet content for processing by higher layers. MAC circuitry2016can be configured to assemble data to be transmitted into packets, that include destination and source addresses along with network control information and error detection hash values.

Processors2004can be any a combination of a: processor, core, graphics processing unit (GPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), or other programmable hardware device that allow programming of network interface2000. For example, a “smart network interface” or SmartNIC can provide packet processing capabilities in the network interface using processors2004. In some examples, processors2004can be implemented as a processor component for a SmartNIC.

Packet allocator2024can provide distribution of received packets for processing by multiple CPUs or cores using timeslot allocation described herein or RSS. When packet allocator2024uses RSS, packet allocator2024can calculate a hash or make another determination based on contents of a received packet to determine which CPU or core is to process a packet.

Interrupt coalesce2022can perform interrupt moderation whereby network interface interrupt coalesce2022waits for multiple packets to arrive, or for a time-out to expire, before generating an interrupt to host system to process received packet(s). Receive Segment Coalescing (RSC) can be performed by network interface2000whereby portions of incoming packets are combined into segments of a packet. Network interface2000provides this coalesced packet to an application.

Direct memory access (DMA) engine2052can copy a packet header, packet payload, and/or descriptor directly from host memory to the network interface or vice versa, instead of copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the destination buffer. In some embodiments, multiple DMA engines are available for transfer of contents of packets to a destination memory associated with a host device or a destination memory associated with an accelerator device.

Memory2010can be any type of volatile or non-volatile memory device and can store any queue or instructions used to program network interface2000. Transmit queue2006can include data or references to data for transmission by network interface. Receive queue2008can include data or references to data that was received by network interface from a network. Descriptor queues2020can include descriptors that reference data or packets in transmit queue2006or receive queue2008and corresponding destination memory regions. Bus interface2012can provide an interface with host device (not depicted). For example, bus interface2012can be compatible with PCI, PCI Express, PCI-x, Serial ATA, and/or USB compatible interface (although other interconnection standards may be used).

FIG.21depicts a system. The system can use embodiments described herein for processing NVMe commands. System2100includes processor2110, which provides processing, operation management, and execution of instructions for system2100. Processor2110can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware to provide processing for system2100, or a combination of processors. Processor2110controls the overall operation of system2100, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.

In one example, system2100includes interface2112coupled to processor2110, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem2120, graphics interface components2140, or accelerators2142. Interface2112represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface2140interfaces to graphics components for providing a visual display to a user of system2100. In one example, graphics interface2140can drive a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately 100 PPI (pixels per inch) or greater and can include formats such as full HD (e.g., 1080p), retina displays, 4K (ultra-high definition or UHD), or others. In one example, the display can include a touchscreen display. In one example, graphics interface2140generates a display based on data stored in memory2130or based on operations executed by processor2110or both. In one example, graphics interface2140generates a display based on data stored in memory2130or based on operations executed by processor2110or both.

Accelerators2142can be a programmable or fixed function offload engine that can be accessed or used by a processor2110. For example, an accelerator among accelerators2142can provide compression (DC) capability, cryptography services such as public key encryption (PKE), cipher, hash/authentication capabilities, decryption, or other capabilities or services. In some embodiments, in addition or alternatively, an accelerator among accelerators2142provides field select controller capabilities as described herein. In some cases, accelerators2142can be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that includes a CPU and provides an electrical interface with the CPU). For example, accelerators2142can include a single or multi-core processor, graphics processing unit, logical execution unit single or multi-level cache, functional units usable to independently execute programs or threads, application specific integrated circuits (ASICs), neural network processors (NNPs), programmable control logic, and programmable processing elements such as field programmable gate arrays (FPGAs). Accelerators2142can provide multiple neural networks, processor cores, or graphics processing units can be made available for use by artificial intelligence (AI) or machine learning (ML) models. For example, the AI model can use or include any or a combination of: a reinforcement learning scheme, Q-learning scheme, deep-Q learning, or Asynchronous Advantage Actor-Critic (A3C), combinatorial neural network, recurrent combinatorial neural network, or other AI or ML model. Multiple neural networks, processor cores, or graphics processing units can be made available for use by AI or ML models.

Memory subsystem2120represents the main memory of system2100and provides storage for code to be executed by processor2110, or data values to be used in executing a routine. Memory subsystem2120can include one or more memory devices2130such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as DRAM, or other memory devices, or a combination of such devices. Memory2130stores and hosts, among other things, operating system (OS)2132to provide a software platform for execution of instructions in system2100. Additionally, applications2134can execute on the software platform of OS2132from memory2130. Applications2134represent programs that have their own operational logic to perform execution of one or more functions. Processes2136represent agents or routines that provide auxiliary functions to OS2132or one or more applications2134or a combination. OS2132, applications2134, and processes2136provide software logic to provide functions for system2100. In one example, memory subsystem2120includes memory controller2122, which is a memory controller to generate and issue commands to memory2130. It will be understood that memory controller2122could be a physical part of processor2110or a physical part of interface2112. For example, memory controller2122can be an integrated memory controller, integrated onto a circuit with processor2110.

In some examples, OS2132can determine a capability of a device associated with a device driver. For example, OS2132can receive an indication of a capability of a device (e.g., NIC2150or a storage configuration interface) to configure a NIC2150to perform memory allocation in one or more host devices or requesters in local or remote memory in accordance with embodiments described herein. OS2132can request a driver to enable or disable NIC2150to perform any of the capabilities described herein. In some examples, OS2132, itself, can enable or disable NIC2150to perform any of the capabilities described herein. OS2132can provide requests (e.g., from an application or VM) to NIC2150to utilize one or more capabilities of NIC2150. For example, any application can request use or non-use of any of capabilities described herein by NIC2150.

While not specifically illustrated, it will be understood that system2100can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus.

In one example, system2100includes interface2114, which can be coupled to interface2112. In one example, interface2114represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface2114. Network interface2150provides system2100the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface2150can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface2150can transmit data to a remote device, which can include sending data stored in memory. Network interface2150can receive data from a remote device, which can include storing received data into memory. Various embodiments can be used in connection with network interface2150, processor2110, and memory subsystem2120.

In one example, system2100includes one or more input/output (I/O) interface(s)2160. I/O interface2160can include one or more interface components through which a user interacts with system2100(e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface2170can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system2100. A dependent connection is one where system2100provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.

In one example, system2100includes storage subsystem2180to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage2180can overlap with components of memory subsystem2120. Storage subsystem2180includes storage device(s)2184, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage2184holds code or instructions and data2186in a persistent state (e.g., the value is retained despite interruption of power to system2100). Storage2184can be generically considered to be a “memory,” although memory2130is typically the executing or operating memory to provide instructions to processor2110. Whereas storage2184is nonvolatile, memory2130can include volatile memory (e.g., the value or state of the data is indeterminate if power is interrupted to system2100). In one example, storage subsystem2180includes controller2182to interface with storage2184. In one example controller2182is a physical part of interface2114or processor2110or can include circuits or logic in both processor2110and interface2114.

A volatile memory is memory whose state (and therefore the data stored in it) is indeterminate if power is interrupted to the device. Dynamic volatile memory requires refreshing the data stored in the device to maintain state. One example of dynamic volatile memory incudes DRAM (Dynamic Random Access Memory), or some variant such as Synchronous DRAM (SDRAM). Another example of volatile memory includes cache or static random access memory (SRAM). A memory subsystem as described herein may be compatible with a number of memory technologies, such as DDR3 (Double Data Rate version 3, original release by JEDEC (Joint Electronic Device Engineering Council) on Jun. 27, 2007). DDR4 (DDR version 4, initial specification published in September 2012 by JEDEC), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version3, JESD209-3B, August 2013 by JEDEC), LPDDR4) LPDDR version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide Input/output version 2, JESD229-2 originally published by JEDEC in August 2014, HBM (High Bandwidth Memory, JESD325, originally published by JEDEC in October 2013, LPDDR5 (currently in discussion by JEDEC), HBM2 (HBM version 2), currently in discussion by JEDEC, or others or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications. The JEDEC standards are available at www.jedec.org.

A non-volatile memory (NVM) device is a memory whose state is determinate even if power is interrupted to the device. In one embodiment, the NVM device can comprise a block addressable memory device, such as NAND technologies, or more specifically, multi-threshold level NAND flash memory (for example, Single-Level Cell (“SLC”), Multi-Level Cell (“MLC”), Quad-Level Cell (“QLC”), Tri-Level Cell (“TLC”), or some other NAND). A NVM device can also comprise a byte-addressable write-in-place three dimensional cross point memory device, or other byte addressable write-in-place NVM device (also referred to as persistent memory), such as single or multi-level Phase Change Memory (PCM) or phase change memory with a switch (PCMS), Intel® Optane™ memory, NVM devices that use chalcogenide phase change material (for example, chalcogenide glass), resistive memory including metal oxide base, oxygen vacancy base and Conductive Bridge Random Access Memory (CB-RAM), nanowire memory, ferroelectric random access memory (FeRAM, FRAM), magneto resistive random access memory (MRAM) that incorporates memristor technology, spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory.

A power source (not depicted) provides power to the components of system2100. More specifically, power source typically interfaces to one or multiple power supplies in system2100to provide power to the components of system2100. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source. In one example, power source includes a DC power source, such as an external AC to DC converter. In one example, power source or power supply includes wireless charging hardware to charge via proximity to a charging field. In one example, power source can include an internal battery, alternating current supply, motion-based power supply, solar power supply, or fuel cell source.

In an example, system2100can be implemented using interconnected compute sleds of processors, memories, storages, network interfaces, and other components. High speed connections can be used such as: Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect express (PCIe), Intel® QuickPath Interconnect (QPI), Intel® Ultra Path Interconnect (UPI), Intel® On-Chip System Fabric (IOSF), Omnipath, Compute Express Link (CXL), HyperTransport, high-speed fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, DisplayPort, embedded DisplayPort, MIPI, HDMI, Infinity Fabric (IF), and successors or variations thereof.

Embodiments herein may be implemented in various types of computing and networking equipment, such as switches, routers, racks, and blade servers such as those employed in a data center and/or server farm environment. The servers used in data centers and server farms comprise arrayed server configurations such as rack-based servers or blade servers. These servers are interconnected in communication via various network provisions, such as partitioning sets of servers into Local Area Networks (LANs) with appropriate switching and routing facilities between the LANs to form a private Intranet. For example, cloud hosting facilities may typically employ large data centers with a multitude of servers. A blade comprises a separate computing platform that is configured to perform server-type functions, that is, a “server on a card.” Accordingly, each blade includes components common to conventional servers, including a main printed circuit board (main board) providing internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted to the board.

In some examples, network interface and other embodiments described herein can be used in connection with a base station (e.g., 3G, 4G, 5G and so forth), macro base station (e.g., 5G networks), picostation (e.g., an IEEE 802.11 compatible access point), nanostation (e.g., for Point-to-MultiPoint (PtMP) applications), on-premises data centers, off-premises data centers, edge network elements, fog network elements, and/or hybrid data centers (e.g., data center that use virtualization, cloud and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation. A processor can be one or more combination of a hardware state machine, digital control logic, central processing unit, or any hardware, firmware and/or software elements.

Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations in accordance with the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predefined computer language, manner or syntax, for instructing a machine, computing device or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium which represents various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

The appearances of the phrase “one example” or “an example” are not necessarily all referring to the same example or embodiment. Any aspect described herein can be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with respect to the same figure or element. Division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would necessarily be divided, omitted, or included in embodiments.

Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The terms “first,” “second,” and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term “asserted” used herein with reference to a signal denote a state of the signal, in which the signal is active, and which can be achieved by applying any logic level either logic 0 or logic 1 to the signal. The terms “follow” or “after” can refer to immediately following or following after some other event or events. Other sequences of steps may also be performed according to alternative embodiments. Furthermore, additional steps may be added or removed depending on the particular applications. Any combination of changes can be used and one of ordinary skill in the art with the benefit of this disclosure would understand the many variations, modifications, and alternative embodiments thereof.

Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is otherwise understood within the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present. Additionally, conjunctive language such as the phrase “at least one of X, Y, and Z,” unless specifically stated otherwise, should also be understood to mean X, Y, Z, or any combination thereof, including “X, Y, and/or Z.”

Example 1 can include an apparatus comprising: a network interface controller comprising a memory interface and a network interface, the network interface controller configurable to provide access to local memory or and remote memory to a requester, wherein the network interface controller is configured with an amount of memory of different memory access speeds for allocation to one or more requesters.

Example 2 includes any example, wherein the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester.

Example 3 includes any example, wherein the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester.

Example 4 includes any example, wherein the network interface controller is to regulate quality of service of memory access requests from requesters.

Example 5 includes any example, wherein the local memory comprises a lower latency memory technology and the remote memory comprises a higher latency memory technology.

Example 6 includes any example, wherein the local memory comprises a local memory connected to the network interface controller using a memory interface.

Example 7 includes any example, wherein the remote memory comprises a memory connected to the network interface controller using a fabric.

Example 8 includes any example, wherein the network interface controller is configured to permit memory allocation to one or more servers within a trust group.

Example 9 includes any example, comprising one or more of a server, rack, or data center and wherein the one or more of a server, rack, or data center is coupled to the network interface controller and the one or more of a server, rack, or data center is to execute a requester to request allocation of an amount of memory.

Example 10 includes any example, and includes a computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: enable or disable a network interface to: manage access to local memory or remote memory granted to a requester, wherein the network interface is configured with an amount of memory of different memory access speeds for allocation to one or more requesters.

Example 11 includes any example, and include instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester.

Example 12 includes any example, and include instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: enable or disable the network interface to regulate quality of service of memory access requests from one or more requesters.

Example 13 includes any example, wherein: the local memory comprises a local memory connected to the network interface using a memory interface and the remote memory comprises a memory connected to the network interface using a fabric.

Example 14 includes any example, and includes a method comprising: providing access to local memory or remote memory, by a network interface, to one or mor requesters, based on a configured amount of memory of different memory access speeds allocated to one or more requesters.

Example 15 includes any example, and includes granting or denying, by the network interface, a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester.

Example 16 includes any example, and includes granting or denying, by the network interface, a memory access request from a requester based on a configuration of memory allocated to the requester.

Example 17 includes any example, and includes regulating quality of service of memory access requests from requesters.

Example 18 includes any example, wherein the local memory comprises a lower latency memory technology and the remote memory comprises a higher latency memory technology.

Example 19 includes any example, wherein the local memory comprises a memory connected to the network interface using a memory interface.

Example 20 includes any example, wherein the remote memory comprises a memory connected to the network interface using a fabric.