Patent ID: 12224752

DETAILED DESCRIPTION

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

FIG.1illustrates a block diagram of an example data processing circuit100in accordance with an aspect of the disclosure. The data processing circuit100may be implemented in an integrated circuit (IC), such as a system on chip (SOC). It shall be understood that the data processing circuit100is merely an example, and many variations with same and/or different components are contemplated.

In particular, the data processing circuit100includes a clock generator (e.g., phase locked loop (PLL))105, a first (e.g., hierarchical level) clock gating circuit (CGC-1)110, a set of one or more cascaded buffers115, and a functional circuit120(e.g., a processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a memory (e.g., dynamic random access memory (DRAM)), etc.). The functional circuit120, in turn, includes a second (e.g., hierarchical level) clock gating circuit (CGC-2)125, a set of input buffers130-1to130-N, and a set of single-edge-triggered (SET) flip-flops (FFs)135-1to135-N.

The clock generator105is configured to generate a root clock signal clk_root. A clock signal, as defined herein, is a substantially periodic voltage waveform (e.g., substantially square wave) used to sequentially control the movement of data within a functional circuit, such as the functional circuit120. The first clock gating circuit (CGC-1)110is configured to gate/pass the root clock signal clk_root based on a first enable signal (EN1). For example, if the first enable signal (EN1) is asserted (e.g., a logic one (1) or high voltage level), the first clock gating circuit (CGC-1)110allows the root clock signal clk_root to pass therethrough as an output clock signal clk. If the first enable signal (EN1) is not asserted (e.g., a logic zero (0) or low voltage level), the first clock gating circuit (CGC-1)110gates the root clock signal clk_root from passing therethrough.

The set of one or more cascaded buffers115provides some isolation between the first clock gating circuit (CGC-1)110and the functional circuit120to maintain the integrity of the output clock signal clk. The output clock signal clk may be provided to clock inputs of the set of SET FFs135-1to135-N−1 via the set of input buffers130-1to130-N−1, respectively. In this example, the second clock gating circuit (CGC-2)125is configured to gate/pass the output clock signal clk based on a second enable signal (EN2) in a similar manner as the first clock gating circuit (CGC-1)110(e.g., pass if EN2=1, and gate if EN2=0). The second gated output clock signal clk2is provided to the clock input of the SET FF135-N via the input buffer130-N. Each of the set of SET FFs135-1to135-N, which may include parallel SET FFs or a network of SET FFs, may pertain to a set of data pipelines for moving/routing input data (D) and output data (Q) to and/or from functional blocks (e.g., combinational logic, arithmetic logic units (ALUs), registers, etc.) as part of the functional circuit120.

As discussed, in this example, the data processing circuit100uses SET FFs that capture or move data on one of the edges or transitions (e.g., rising or falling transition) per period of the clock signal clk. The other edge or transition (e.g., falling or rising transition) of the clock period merely sets up the SET FF for the next capture interval. Accordingly, from a power efficient perspective, the data processing circuit100may not be optimal as one of the edges per clock period may be considered wasted energy as it does not effectuate data propagation or movement. This is explained further herein with reference to more detail descriptions of a SET FF.

FIG.2illustrates a block diagram of an example single-edge-triggered (SET) flip-flop (FF)200in accordance with another aspect of the disclosure. The SET FF200may be an example detailed implementation of any of the set of SET FFs135-1to135-N of data processing circuit100.

In particular, the SET FF200includes a master latch (M-latch)210cascaded with a slave latch (S-latch)230along a data path. The master latch210includes a data input (IN) configured to receive a data (D) signal, a complementary (e.g., inverting) clock input (CK) configured to receive a clock signal CLK, and a data output (OUT). Similarly, the slave latch230includes a data input (IN) coupled to the data output (OUT) of the master latch210, a non-complementary clock input (CK) configured to receive the clock signal CLK, and a data output (OUT) configured to generate an output data signal (Q).

In operation, when the clock signal CLK is a logic zero (0) or low, the master latch210is transparent and the slave latch230is opaque. The master latch210being transparent accepts the current data D(t) at its data input (IN) and provides it to its data output (OUT). The slave latch230being opaque latches the previous data D(t−1) while blocking or preventing the current data (D(t) from affecting the latched previous data D(t−1). When the clock signal CLK transitions to a logic one (1) or high, the master latch210becomes opaque and the slave latch230becomes transparent. The master latch210being opaque latches the current data D(t) while blocking or preventing the next data D(t+1) from affecting the latched current data D(t). The slave latch230being transparent receives and outputs the current data D(t) as the output data signal Q(t).

Note that two clock transitions are needed to propagate data from the data input of the master latch210to the data output of the slave latch230. For instance, in this example, the falling edge or transition of the clock signal causes the master latch210to merely accept the current data D(t). Then, the rising edge or transition causes the current data D(t) to propagate from the master latch210to the slave latch230to output the current data Q(t). Thus, the falling edge or transition of the clock signal may be considered wasted energy as it does not effectuate data movement from the input to the output of the SET FF200.

FIG.3illustrates a block diagram of another example single-edge-triggered (SET) flip-flop (FF)300in accordance with another aspect of the disclosure. The SET FF300may be a more detailed implementation of the SET FF200previously discussed. Similarly, the SET FF300includes a master latch310cascaded with a slave latch330along a data path. Additionally, the SET FF300includes a pair of cascaded inverters360and365configured to generate a complementary clock signal (CKB) and a non-complementary clock signal (CKI) based on an input clock signal (CLK), respectively.

The master latch310, in turn, includes a tristate inverter315, and a latch circuit including a latch inverter320and a latch tristate inverter325. The tristate inverter315includes a data input, which serves as the data input of the SET FF300, to receive an input data signal D. The tristate inverter315further includes complementary and non-complementary control inputs configured to receive the non-complementary clock signal CKI and the complementary clock signal CKB, respectively. The tristate inverter315includes an output coupled to an input of the latch inverter320and an output of the latch tristate inverter325. The latch inverter320includes an output coupled to an input of the latch tristate inverter325. The latch tristate inverter325further includes complementary and non-complementary control inputs configured to receive the complementary clock signal CKB and the non-complementary clock signal CKI, respectively.

The slave latch330, in turn, includes a transmission gate335, a latch circuit including a latch inverter340and a latch tristate inverter345, and an output inverter350. The transmission gate335includes a data input coupled to an output (e.g., the output of the latch inverter320) of the master latch310. The transmission gate335further includes complementary and non-complementary control inputs configured to receive the complementary clock signal CKB and the non-complementary clock signal CKI, respectively. The transmission gate335includes an output coupled to an input of the latch inverter340and an output of the latch tristate inverter345. The latch inverter340includes an output coupled to respective inputs of the latch tristate inverter345and the output inverter350. The latch tristate inverter345further includes complementary and non-complementary control inputs configured to receive the non-complementary clock signal CKI and the complementary clock signal CKB, respectively. The output inverter350includes an output configured to generate an output data signal (Q).

In operation, when the input clock signal CLK transitions to a logic zero (0), the inverter360generates the complementary clock signal CKB as a logic one (1), and the inverter365generates the non-complementary clock signal CKI as a logic zero (0). Based on such states of the clock signals CKI and CKB, the master latch310is transparent and the slave latch330is opaque. That is, with regard to the master latch310, the tristate inverter315is enabled to receive the current data D(t), and the cascaded inverters315and320reproduces the current data D(t) at the input of the slave latch330, while the latch tristate inverter325is disabled. With regard to the slave latch330, the transmission gate335is gated to prevent the current data D(t) from affecting the latched inverted previous dataD(t−1) held by the latch inverter340and enabled latch tristate inverter345. The output inverter350inverts the latched inverted previous dataD(t−1) to generate the previous output data Q(t−1).

When the input clock signal CLK transitions to a logic one (1), the inverter360generates the complementary clock signal CKB as a logic zero (0), and the inverter365generates the non-complementary clock signal CKI as a logic one (1). Based on these states of the clock signals CKI and CKB, the master latch310becomes opaque and the slave latch330becomes transparent. That is, with regard to the master latch310, the tristate inverter315is disabled to block or prevent the next data D(t+1) from affecting the latched current data D(t) by the latch inverter320and the enabled latch tristate inverter325. With regard to the slave latch330, the transmission gate335is not gated to pass the current data D(t) from the output of the master latch310to the output of the slave latch330via inverters340and350to generate the current output data Q(t) while the latch tristate inverter345is disabled.

Similarly, as discussed above with SET FF200, a rising edge or transition of the clock signal CLK causes the current data D(t) to propagate from the master latch310to the output of the slave latch330, i.e., the output of the SET FF300. The falling edge of the clock signal CLK merely prepares the SET FF300to accept the current data D(t) by propagating it to the master latch310. Similarly, the falling clock edge in this example may be regarded as wasted power because it does not cause a movement of the data from the input to the output of the SET FF300.

FIG.4Aillustrates a block diagram of an example clock gating circuit (CGC)400for a set of single-edge-triggered (SET) flip-flops (FFs)430in accordance with another aspect of the disclosure. The CGC400may be an example detailed implementation of any of the CGCs110and125of data processing circuit100. The CGC400includes a latch410and an AND gate420. The latch410includes an input (IN) to receive an enable signal EN, a complementary (e.g., inverting) clock input (CK) configured to receive an input clock signal CLKIN, and an output (OUT) configured to generate a latched enable signal ENL. The AND gate420includes a first input coupled the output (OUT) of the latch410to receive the latched enable signal ENL therefrom, and a second input configured to receive the input clock signal CLKIN. The AND gate420generates an output clock signal CLKOUTat an output coupled to clock inputs of the set of SET FFs430. The operation of the CGC400is discussed further herein with reference toFIG.4B.

FIG.4Billustrates a timing diagram of example signals associated with the CGC400in accordance with another aspect of the disclosure. The horizontal axis of the timing diagram represents time. From top to bottom, the vertical axis represents logic states of the enable signal EN, the input clock signal CLKIN, the output clock signal CLKOUT, and the output data (Q) of the set of SET FFs430.

When the enable signal EN is asserted (e.g., a logic one (1) or high) during time interval t0to t3, the latch410generates an asserted latched enable signal ENL (e.g., a logic one (1) or high), which causes the AND gate420to pass the input clock signal CLKINto produce the output clock signal CLKOUT. Accordingly, the rising edges or transitions of the output clock signal CLKOUTat times t1, t2, and t3causes the set of SET FFs430to output data Q(t), Q(t+1), and Q(t+2), respectively. At time t3, the enable signal EN becomes deasserted (e.g., a logic zero (0) or low). In response to the following falling edge or transition of the input clock signal CLKINat time t4, the latch410deasserts the latched enable signal ENL (e.g., a logic zero (0) or low).

In response, the AND gate420maintains the output clock signal CLKOUTat a fixed logic zero (0) or low until the latched enable signal ENL becomes a logic one (1) or high at time t6. During time interval t6to t8, the AND gate420passes the input clock signal CLKINto produce the output clock signal CLKOUT. Accordingly, at time t7, the output clock signal CLKOUTexperiences a rising edge or transition. In response, the set of SET FFs430outputs the next data Q(t+3) at time t7. Note that because the enable signal EN was deasserted between times t3and t5, the output clock signal CLKOUTdid not experience a rising edge at time t5, as did the input clock signal CLKIN. Thus, the set of SET FFs maintain its output data at Q(t+2) for two periods of the input clock signal CLKIN.

FIG.5illustrates a block diagram of another example data processing circuit500in accordance with another aspect of the disclosure. In contrast to data processing circuit100, the data processing circuit500includes dual-edge-triggered (DET) flip-flops (FFs) that capture/propagate/move data on both edges or transitions (e.g., rising and falling) of a clock signal. Thus, the frequency of the clock signal may be halved to save power, while still maintaining the same data throughput as the SET-based data processing circuit100. Alternatively, the frequency of the clock signal may remain the same while achieving double the data throughput as the SET-based data processing circuit100. It shall be understood that the data processing circuit500is merely an example, and many variations with same and/or different components are contemplated.

In particular, the data processing circuit500includes a clock generator (e.g., phase locked loop (PLL))505, a duty cycle controller (DCC)510, a first (e.g., hierarchical level) clock gating circuit (CGC-1)515, a set of one or more cascaded buffers520, and a functional circuit530(e.g., a processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a memory (e.g., dynamic random access memory (DRAM)), etc.). The functional circuit530, in turn, includes a second (e.g., hierarchical level) clock gating circuit (CGC-2)535, a set of input buffers540-1to540-N, and a set of dual-edge-triggered (DET) flip-flops (FFs)545-1to545-N.

The clock generator (e.g., PLL)505is configured to generate a source clock signal clk_pll. The DCC510is configured to control/adjust the duty cycle of the source clock signal clk_pll to generate a root clock signal clk_root having substantially 50 percent (%) duty cycle. As the set of DET FFs545-1to545-N move data on both the rising and falling edges of a clock signal, duty cycle distortion in the clock signal substantially affects performance of DET sequential circuits. This is because the timing of all the clock edges should comply with setup and hold time margins. Whereas, in the case of the SET FF where data propagates in response to, for example, the rising edge of a clock signal, the timing of the falling edge is not that critical. Accordingly, duty cycle distortion in the clock signal does not significantly affect the performance of SET sequential circuits.

The first clock gating circuit (CGC-1)515is configured to gate/pass the root clock signal clk_root based on a first enable signal (EN1). Similarly, if the first enable signal (EN1) is asserted (e.g., a logic one (1) or high voltage level), the first clock gating circuit (CGC-1)515allows the root clock signal clk_root to pass therethrough as an output clock signal clk. If the first enable signal (EN1) is not asserted (e.g., a logic zero (0) or low voltage level), the first clock gating circuit (CGC-1)515gates the root clock signal clk_root from passing therethrough.

The set of one or more cascaded buffers520provides some isolation between the first clock gating circuit (CGC-1)515and the functional circuit530to maintain the integrity of the output clock signal clk. The output clock signal clk may be provided to clock inputs of the set of DET FFs545-1to545-N−1 via a set of input buffers540-1to540-N−1, respectively. In this example, the second clock gating circuit (CGC-2)535is configured to gate/pass the output clock signal clk based on a second enable signal (EN2) in a similar manner as the first clock gating circuit (CGC-1)515(e.g., pass if EN2=1, and gate if EN2=0). The second gated output clock signal clk2is provided to the clock input of the DET FF545-N via the input buffer540-N. Each of the set of DET FFs545-1to545-N, which may include parallel DET FFs or a network of DET FFs, may pertain to a set of data pipelines for moving/routing input data (D) and output data (Q) to and/or from functional blocks (e.g., combinational logic, arithmetic logic units (ALUs), registers, etc.) as part of the functional circuit530.

FIG.6illustrates a block diagram of an example dual-edge-triggered (DET) flip-flop (FF)600in accordance with another aspect of the disclosure. The DET FF600may be an example detailed implementation of any of the set of DET FFs545-1to545-N of data processing circuit500.

In particular, the DET FF600includes a first latch620, a second latch640, and a multiplexer660. The first latch620includes a data input (IN) configured to receive an input data signal (D), a complementary (e.g., inverting) clock input (CK) configured to receive a clock signal CLK, and a data output (OUT) coupled to a first input “1” of the multiplexer660. Similarly, the second latch640includes a data input (IN) configured to receive the input data signal (D), a non-complementary clock input (CK) configured to receive the clock signal CLK, and a data output (OUT) coupled to a second input “0” of the multiplexer660. The multiplexer660further includes a select input configured to receive the clock signal CLK, and an output configured to produce an output data signal (Q).

In operation, when the clock signal CLK has a falling transition to a logic zero (0) or low, the first latch620becomes transparent and the second latch640becomes opaque. The first latch620being transparent accepts the current data D(t). The second latch640being opaque latches the previous data D(t−1) while blocking or preventing the current data D(t) from affecting the latched previous data D(t−1). The clock signal CLK being at a logic zero (0) or low causes the multiplexer660to select the latched previous data D(t−1) as the previous output data Q(t−1). When the clock signal CLK has a rising transition to a logic one (1) or high, the first latch620becomes opaque and the second latch640becomes transparent. The second latch640being transparent accepts the next data D(t+1). The first latch620being opaque latches the current data D(t) while blocking or preventing the next data D(t+1) from affecting the latched current data D(t). The clock signal CLK being at a logic one (1) or high causes the multiplexer660to select the latched current data D(t) as the current output data Q(t). Thus, the DET FF600effectuates data movement on both the rising and falling edges of the clock signal CLK.

FIG.7illustrates a block diagram of another example dual-edge-triggered (DET) flip-flop (FF)700in accordance with another aspect of the disclosure. The DET FF700may be a more detailed implementation of the DET FF600previously discussed.

The DET FF700includes an input pair of cascaded inverters710and715, a first latch720, a second latch740, a multiplexer760, and an output inverter780. Additionally, the DET FF700includes a pair of cascaded inverters790and795configured to generate a complementary clock signal (CKB) and a non-complementary clock signal (CKI) based on an input clock signal (CLK), respectively. The input pair of cascaded inverters710and715serve as a buffer configured to receive an input data signal D and regenerate the data signal D at the inputs of the first and second latches720and740.

The first latch720includes a transmission gate725, and a latch circuit including latch inverter730and latch tristate inverter735. The transmission gate725includes an input coupled to the output of the inverter715to receive the data signal D therefrom. The transmission gate725further includes complementary and non-complementary control inputs configured to receive the non-complementary clock signal CKI and the complementary clock signal CKB, respectively. The transmission gate725includes an output coupled to an input of the latch inverter730and an output of the latch tristate inverter735. The latch inverter730includes an output coupled to an input of the latch tristate inverter735. The latch tristate inverter735further includes complementary and non-complementary control inputs configured to receive the complementary clock signal CKB and the non-complementary clock signal CKI, respectively.

The second latch740includes a transmission gate745, and a latch circuit including latch inverter750and latch tristate inverter755. The transmission gate745includes an input coupled to the output of the inverter715to receive the data signal D therefrom. The transmission gate745further includes complementary and non-complementary control inputs configured to receive the complementary clock signal CKB and the non-complementary clock signal CKI, respectively. The transmission gate745includes an output coupled to an input of the latch inverter750and an output of the latch tristate inverter755. The latch inverter750includes an output coupled to an input of the latch tristate inverter755. The latch tristate inverter755further includes complementary and non-complementary control inputs configured to receive the non-complementary clock signal CKI and the complementary clock signal CKB, respectively.

The multiplexer760includes a first transmission gate765and a second transmission gate770. The first transmission gate765includes an input, serving as the first input “1” of the multiplexer760, coupled to an output of the first latch720(e.g., to the output of the latch inverter730). The first transmission gate765further includes complementary and non-complementary control inputs configured to receive the complementary clock signal CKB and the non-complementary clock signal CKI, respectively. The second transmission gate770includes an input, serving as the second input “0” of the multiplexer760, coupled to an output of the second latch740(e.g., to the output of the latch inverter750). The second transmission gate770further includes complementary and non-complementary control inputs configured to receive the non-complementary clock signal CKI and the complementary clock signal CKB, respectively. The first and second transmission gates765and770include outputs coupled together, and to an input of the output inverter780. The output inverter780includes an output configured to produce an output data signal Q.

In operation, when the clock signal CLK has a falling transition to a logic zero (0) or low, the inverter790generates the complementary clock signal CKB as a logic one (1) or high, and the inverter795generates the non-complementary clock signal CKI as a logic zero (0) or low. In response, the first latch720becomes transparent to accept the current data D(t) from the input pair of cascaded inverters710and715, the second latch740becomes opaque to latch the complementary previous dataD(t−1) and block the current data D(t) from affecting the latched complementary previous dataD(t−1), the multiplexer760outputs the latched complementary previous dataD(t−1) from the second latch740, and the output inverter780inverts the complementary previous dataD(t−1) to generate the previous output data Q(t−1).

More specifically, based on CKI=0 and CKB=1, the first latch720becomes transparent because the transmission gate725is not gated and passes the current data D(t) to the open latch circuit730/735due to the disabled tristate inverter735. The second latch740becomes opaque because the transmission gate745is gated and prevents the current data D(t) from affecting the latching of the complementary previous dataD(t−1) by the latch circuit750/755due to the enabled tristate inverter755. The first transmission gate765of the multiplexer760is gated and the second transmission gate770is not gated to pass the latched complementary previous dataD(t−1) to the output inverter780to generate the previous output data Q(t−1).

When the clock signal CLK has a rising transition to a logic one (1) or high, the inverter790generates the complementary clock signal CKB as a logic zero (0) or low, and the inverter795generates the non-complementary clock signal CKI as a logic one (1) or high. In response, the first latch720becomes opaque to latch the complementary current dataD(t) and block the next data D(t+1) from affecting the latched complementary current dataD(t), the second latch740becomes transparent to accept the next data D(t+1) from the input pair of cascaded inverters710and715, the multiplexer760outputs the latched complementary current dataD(t) from the first latch720, and the output inverter780inverts the complementary current dataD(t) to generate the current output data Q(t).

More specifically, based on CKI=1 and CKB=0, the first latch720becomes opaque because the transmission gate725is gated and prevents the next data D(t+1) from affecting the latching of the complementary current dataD(t) by the latch circuit730/735due to the enabled tristate inverter735. The second latch740becomes transparent because the transmission gate745is not gated and passes the next data D(t+1) to the open latch circuit750/755due to the disabled tristate inverter755. The first transmission gate765of the multiplexer760is not gated to pass the latched complementary current dataD(t) to the output inverter780to generate the current output data Q(t), and the second transmission gate770is gated.

FIG.8Aillustrates a block diagram of an example clock gating circuit (CGC)800for dual-edge-triggered (DET) flip-flops (FFs) in accordance with another aspect of the disclosure. The CGC800may be an example detailed implementation of any of the CGCs515and535of data processing circuit500.

The CGC800includes a dual-edge-triggered (DET) flip-flop (FF)810and an exclusive-OR gate820. The DET FF810includes an input (IN) coupled to an output of the exclusive-OR gate820, a clock input configured to receive an input clock signal CLKIN, and an output (OUT) configured to generate an output clock signal CLKOUTat an output coupled to the clock inputs of the set of DET FFs830. The exclusive-OR gate820includes a first input coupled to the output of the DET FF810. The exclusive-OR gate820includes a second input configured to receive an enable signal (EN). The operation of the CGC800is discussed further herein with reference toFIG.8B.

FIG.8Billustrates a timing diagram of example signals associated with DET CGCs, such as CGC800(and others) in accordance with another aspect of the disclosure. The horizontal axis of the timing diagram represents time. From top to bottom, the vertical axis represents logic states of the enable signal EN, the input clock signal CLKIN, the output clock signal CLKOUT, and the output data (Q) of the set of DET FFs830. As discussed below, a difference between the SET CGC400and the DET CGC800is that when the enable signal EN is deasserted (e.g., EN=0), the output clock signal CGC generated by the SET CGC400goes to a logic zero (0) or low, whereas the output clock signal CGC generated by the DET CGC800stays at the level at the time the enable signal EN is deasserted.

For example, when the enable signal is asserted (e.g., a logic one (1) or high) during time interval t0to t3, the exclusive-OR gate820operates as an inverter to feedback the inverted output clock signal CLKOUTback to the input (IN) of the DET FF810(e.g., the exclusive-OR gate output Xo=CLKBOUT). Thus, for every edge or transition of the input clock signal CLKIN, the DET FF810concurrently generates a corresponding edge or transition of the output clock signal CLKOUT, although the output clock signal CLKOUTmay be in-phase or 180 degrees out-of-phase with the input clock signal CLKIN, as discussed further herein. In this example, during time interval t0to t3, the output clock signal CLKOUTis in-phase with the input clock signal CLKIN. As the output clock signal CLKOUTexhibits edges or transitions at times t1, t2, and t3, the set of DET flip-flops830clocks out the output data Q(t), Q(t+1), and Q(t+2), respectively.

At time t3, the enable signal EN is deasserted (e.g., EN=0) when the output clock signal CLKOUTis at a high logic level. In response, the exclusive-OR gate820operates as a buffer to maintain its output signal Xo at the last logic state of the output clock signal CLKOUT(e.g., a high logic state). Accordingly, when the following edge or transition of the input clock signal CLKINoccurs at time t4, the output clock signal CLKOUTremains fixed at the last logic level (e.g., a high logic state).

Also, in accordance with this example, the enable signal EN becomes asserted (e.g., EN=1) at time t4, where the exclusive-OR gate820is configured again as an inverter to output the inverted output clock signal CLKOUTto the input of the DET FF810. Accordingly, at time t5when the input clock signal CLKINexperiences another edge or transition, the output clock signal CLKOUTexperiences a falling edge or transition. Note that at such time t5, the output clock signal CLKOUTis 180 degrees out-of-phase with the input clock signal CLKIN. The falling edge or transition of the output clock signal CLKOUTat time t5causes the set of DET FFs830to clock out the next output data Q(t+3).

An issue with the DET CGC800is that it generally introduces or adds duty cycle distortion (DCD) to the output clock signal CLKOUT. As previously discussed, a DET sequential circuit is more susceptible to DCD compared to a SET sequential circuit. This is because DCD also affects the timing of the “falling” clock edge or transition, which effectuates data movement in a DET sequential circuit, but does not in a SET sequential circuit. A root cause of the DCD is that the DET FF810operates under the control of the complementary and non-complementary versions of the input clock signal CLKIN. Within the DET FF810, the skew and/or delay associated with the rising and falling edges of internally-generated clock signals CKI and CKB may be significantly different (e.g., often referred to as clock imbalance), as well as the skew and/or delay associated with the rising and falling edges of the exclusive-OR gate820output signal Xo and the output clock signal CLKOUT. Such skew and/or delay differences typically manifest as DCD in the output clock signal CLKOUT.

FIG.9illustrates a block diagram of another example clock gating circuit (CGC)900for a set of dual-edge-triggered (DET) flip-flops (FFs)940in accordance with another aspect of the disclosure. The CGC900may be an example detailed implementation of any of the CGCs515and535of data processing circuit500. The CGC900does not generally suffer from clock imbalance issues as the control of the clock gating device is based on the enable signal not complementary clock signals. Accordingly, the CGC900substantially minimizes duty cycle distortion (DCD) that it adds to the output clock signal.

In particular, the CGC900includes a multiplexer910, a clock gating device920, and a clock selection circuit930. The multiplexer910includes a first input “0” configured to receive a non-complementary clock signal CLK and a second input “1” configured to receive a complementary clock signal CKB. Additionally, the multiplexer910includes a select input coupled to an output of the clock selection circuit930to receive a select signal therefrom. The multiplexer910is configured to output either the non-complementary clock signal CLK and the complementary clock signal CKB as a selected clock signal CLKSELbased on the state of the select signal.

The clock gating device920includes a clock input coupled to an output of the multiplexer910to receive the selected clock signal CLKSELtherefrom. Further, the clock gating device920includes a control input configured to receive an enable signal EN. Additionally, the clock gating device920includes an output configured to generate an output clock signal CLKOUTby selectively gating/outputting the selected clock signal CLKSELbased on a state of the enable signal EN. As previously discussed, the clock gating device920maintains the output clock signal CLKOUTat the fixed logic level when the enable signal EN is deasserted. When the enable signal EN is asserted, the clock gating device920passes the selected clock signal CLKSELas the output clock signal CLKOUT. The output of the clock gating device920is coupled to clock inputs of the set of DET FFs940.

The clock selection circuit930includes a first input coupled to the output of the clock gating device920to receive the output clock signal CLKOUTtherefrom, and a second input configured to receive the non-complementary clock signal CLK or the complementary clock signal CKB. Additionally, the clock selection circuit930includes a control input to receive the enable signal EN. The clock selection circuit930is configured to generate the select signal so that the multiplexer910outputs the non-complementary clock signal CLK or the complementary clock signal CKB to generate a transition (e.g., rising or falling) on the output clock signal CLKOUTwhen the enable signal EN becomes asserted. That is, if the output clock signal CLKOUTis at a low logic level, the selected clock signal CLK or CKB generates a rising transition on the output clock signal CLKOUT. Conversely, if the output clock signal CLKOUTis at a high logic level, the selected clock signal CLK or CKB generates a falling transition on the output clock signal CLKOUT.

For example, with reference to bothFIGS.8B and9, during time interval t0to t3, the output clock signal CLKOUTis in phase with the input clock signal CLKIN, which may be referred to as the non-complementary clock signal CLK. In such case, the clock selection circuit930generates the select signal (e.g., as a logic zero (0)) to cause the multiplexer910to output the non-complementary clock signal CLK as the selected clock signal CLKSEL. When the enable signal EN becomes deasserted at time t3and then becomes asserted again at time t4, the output clock signal CLKOUTis at a high logic level whereas the input clock signal CLKINis at a low logic level, i.e., the output clock signal CLKOUTis 180 degrees out-of-phase with the input clock signal CLKIN. In such case, the clock selection circuit930generates the select signal (e.g., as a logic one (1)) to cause the multiplexer910to output the complementary clock signal CKB as the selected clock signal CLKSEL.

FIG.10illustrates a block diagram of another example clock gating circuit (CGC)1000for a set of dual-edge-triggered (DET) flip-flops (FFs)1070in accordance with another aspect of the disclosure. The CGC1000may be an example more detailed implementation of the CGC900previously discussed. Additionally, the CGC1000may be an example detailed implementation of any of the CGCs515and535of data processing circuit500.

In particular, the CGC1000includes a multiplexer1010, a first latch1020, a logic level comparator1030, and a second latch1040. With reference to CGC900, the multiplexer1010corresponds to the multiplexer910, the first latch1020corresponds to the clock gating device920, and the logic level comparator1030and second latch1040collectively corresponds to the clock selection circuit930.

More specifically, the multiplexer1010includes a non-inverting input “0” and an inverting input “1”, both configured to receive an input clock signal CLKIN. Additionally, the multiplexer1010includes a select input coupled to an output of the second latch1040to receive a select signal therefrom. The multiplexer1010is configured to output a selected clock signal CLKSELbeing either the non-inverted or inverted input clock signal CLKINbased on the state of the select signal.

The first latch1020includes a “data” input coupled to an output of the multiplexer1010to receive the selected clock signal CLKSELtherefrom. Further, the first latch1020includes a “clock” input configured to receive an enable signal EN. Additionally, the first latch1020includes an output configured to generate an output clock signal CLKOUTby selectively gating/outputting the selected clock signal CLKSELbased on a state of the enable signal EN. For example, the first latch1020maintains the output clock signal CLKOUTfixed at the same logic level when the enable signal EN is deasserted (e.g., EN=0). When the enable signal EN is asserted (e.g., EN=1), the first latch1020passes the selected clock signal CLKSELas the output clock signal CLKOUT. The output of the first latch1020is coupled to clock inputs of the set of DET FFs1070.

The logic level comparator1030includes an input “A” coupled to the output of the first latch1020to receive the output clock signal CLKOUTtherefrom. The logic level comparator1030further includes a second input “B” configured to receive the input clock signal CLKIN. The logic level comparator1030is configured to generate a logic level difference signal ΔL based on a comparison of the output clock signal CLKOUTand the input clock signal CLKIN. For example, if the output clock signal CLKOUTis at the same logic level as the input clock signal CLKIN, the logic level comparator1030generates the logic level difference signal ΔL at a first logic value (e.g., a logic zero (0)). If the output clock signal CLKOUTis at an opposite logic level as the input clock signal CLKIN, the logic level comparator1030generates the logic level difference signal ΔL at a second logic value (e.g., a logic one (1)).

The second latch1040includes a “data” input coupled to an output of the logic level comparator1030to receive the logic level difference signal ΔL therefrom. The second latch1040includes an inverting input configured to receive the enable signal EN. Further, the second latch1040includes a “data” output configured to generate the select signal, which is the logic level difference signal ΔL latched in response to the enable signal EN being asserted (e.g., EN=1).

In operation, with reference to bothFIGS.8B and10, during time interval t0to t3, the enable signal EN is asserted (e.g., EN=1). In response, the first latch1020is transparent and the second latch1040is opaque. Also, during this time interval t0to t3, the output clock signal CLKOUTis at the same logic level as (e.g., in-phase with) the input clock signal CLKIN. Accordingly, the logic level comparator1030generates the logic level difference signal ΔL as a logic zero (0), which has been latched by the opaque second latch1040to generate the select signal as a logic zero (0). In response to the select signal being a logic zero (0), the multiplexer1010outputs the input clock signal CLKINas the selected clock signal CLKSEL.

When the enable signal EN becomes deasserted (e.g., EN=0) at time t3until time t4, the first latch1020becomes opaque and holds the output clock signal CLKOUTat the last state or level, which in this example is a high logic level state. During time interval t3to time t4while the enable signal EN is deasserted, the second latch1040is transparent to cause the select signal to follow the logic level difference signal ΔL. At time t4, the enable signal EN becomes asserted again, and the first and second latches1020and1040responsively become transparent and opaque, respectively. At such time t4, the output clock signal CLKOUTis at an opposite logic level as (e.g., 180 degrees out-of-phase with) the input clock signal CLKIN, and the logic level comparator1030responsively generates the logic level difference signal ΔL at a logic one (1). The opaque second latch1040latches the logic level difference signal ΔL to generate the select signal at a logic one (1), which causes the multiplexer1010to output the inverted input clock signal CLKINas the selected clock signal CLKSEL.

FIG.11illustrates a block/schematic diagram of another example clock gating circuit (CGC)1100for a set of dual-edge-triggered (DET) flip-flops (FFs)1170in accordance with another aspect of the disclosure. The CGC1100may be an example more detailed implementation of the CGC1000previously discussed. Additionally, the CGC1100may be an example detailed implementation of any of the CGCs515and535of data processing circuit500.

In particular, the CGC1100includes an input inverter1105, an exclusive-NOR gate1110, a first latch including a transmission gate1115, a latch inverter1120, a latch tristate inverter1125, and an output inverter1130, an exclusive-OR gate1135, and a second latch including a transmission gate1140, a latch inverter1145, and a latch tristate inverter1150. Additionally, the CGC1100includes a pair of cascaded inverters1155and1160configured to generate a complementary enable signal ENB and a non-complementary enable signal ENI based on an input enable signal EN, respectively.

With reference to CGC1000, the input inverter1105and the exclusive-NOR gate1110correspond to the multiplexer1010, the first latch including the transmission gate1115, latch inverter1020, latch tristate inverter1125, and output inverter1130corresponds to the first latch1020, the exclusive-OR gate1135corresponds to the logic level comparator1030, and the second latch including the transmission gate1140, latch inverter1145, and latch tristate inverter1150corresponds to the second latch1040.

More specifically, the input inverter1105includes an input configured to receive an input clock signal CLKIN, and an output to generate a complementary input clock signal CKB. The exclusive-NOR gate1110includes a first input coupled to the output of the input inverter1105to receive the complementary input clock signal CKB therefrom, a second input coupled to an output of the latch inverter1145to receive a select signal therefrom, and an output configured to generate a selected clock signal CLKSELbased on the state of the select signal.

The transmission gate1115includes a “data” input coupled to the output of the exclusive-NOR gate1110to receive the selected clock signal CLKSELtherefrom. The transmission gate1115further includes a complementary control input configured to receive the complementary enable signal ENB, and a non-complementary control input configured to receive the non-complementary enable signal ENI. The transmission gate1115includes an output coupled to an input of the latch inverter1120and an output of the latch tristate inverter1125. The latch inverter1120includes an output coupled to respective inputs of the latch tristate inverter1125and the output inverter1130. The latch tristate inverter1125includes a complementary control input configured to receive the non-complementary enable signal ENI, and a non-complementary control input configured to receive the complementary enable signal ENB. The output inverter1130includes an output at which an output clock signal CLKOUTis generated. The output of the output inverter1130is coupled to clock inputs of the set of DET FFs1170to provide the output clock signal CLKOUTthereto.

The exclusive-OR gate1135includes a first input coupled to the output of the output inverter1130to receive the output clock signal CLKOUTtherefrom. The exclusive-OR gate1135further includes a second input configured to receive the complementary input clock signal CKB. The exclusive-OR gate1135is configured to generate a logic level difference signal ΔL based on a logic level difference between the output clock signal CLKOUTand the complementary input clock signal CKB.

The transmission gate1140includes a “data” input coupled to the output of the exclusive-OR gate1135to receive the logic level difference signal ΔL therefrom. The transmission gate1140further includes a complementary control input configured to receive the non-complementary enable signal ENI, and a non-complementary control input configured to receive the complementary enable signal ENB. The transmission gate1140includes an output coupled to an input of the latch inverter1145and an output of the latch tristate inverter1150. The latch inverter1145includes an output coupled to the input of the latch tristate inverter1150. The latch tristate inverter1150includes a complementary control input configured to receive the complementary enable signal ENB, and a non-complementary control input configured to receive the non-complementary enable signal ENI.

In operation, with reference to bothFIGS.8B and11, during time interval t0to t3, the enable signal EN is asserted (e.g., EN=1). In response, the cascaded inverters1155and1160responsively generate the complementary enable signal ENB as a logic zero (0) and the non-complementary enable signal ENI as a logic one (1). As a result, the first latch1115/1120/1125is transparent and the second latch1140/1145/1150is opaque. That is, the signals ENB=0 and ENI=1 enable the transmission gate1115and disable the latch tristate inverter1125. In such state, the selected clock signal CLKSELpropagates to form the output clock signal CLKOUTvia the transmission gate1115, latch inverter1120, and output inverter1130.

Also, during time interval t0to t3, the output clock signal CLKOUTis at an opposite logic level as (e.g., 180 degrees out-of-phase with) the complementary input clock signal CKB. Accordingly, the exclusive-OR gate1135generates the logic level difference signal ΔL as a logic one (1). The second latch1140/1145/1150being opaque latches the inverted logic level difference signal ΔL to generate the select signal as a logic zero (0). That is, the signals ENB=0 and ENI=1 disables the transmission gate1140and enables the latch tristate inverter1150. In such state, the logic level difference signal ΔL=1 is latched and inverted to generate the select signal as a logic zero (0). The logic zero (0) at the second input of the exclusive-NOR gate1110causes the exclusive-NOR gate1110to invert the complementary input clock signal CKB to generate the selected clock signal CLKSELas the input clock signal CLKIN.

When the enable signal EN becomes deasserted (e.g., EN=0) at time t3until time t4, the first latch1115/1120/125becomes opaque and holds the output clock signal CLKOUTfixed at the last state or level, which in this example is a high logic level state. That is, the signals ENB=1 and ENI=0 disable the transmission gate1115and enable the latch tristate inverter1125. In such state, the last state of the output clock signal CLKOUTis maintained by the opaque first latch. During time interval t3to time t4while the enable signal EN is deasserted, the second latch1140/1145/1150is transparent to cause the select signal to inversely follow the logic level difference signal ΔL. That is, the signals ENB=1 and ENI=0 enables the transmission gate1140and disables the latch tristate inverter1150. In such state, the logic level difference signal ΔL propagates via the latch inverter1145to the select signal.

At time t4, the enable signal EN becomes asserted again, and the first and second latches responsively become transparent and opaque, respectively. At such time t4, the output clock signal CLKOUTis at the same logic level as (e.g., in-phase with) the complementary input clock signal CKB, and the exclusive-OR gate1135responsively generates the logic level difference signal ΔL at a logic zero (0). The opaque second latch latches the logic level difference signal ΔL to generate the select signal at a logic one (1), which configures the exclusive-NOR gate1110as a buffer to output the complementary input clock signal CKBINas the selected clock signal CLKSEL.

FIG.12illustrates a flow diagram of an example method1200of gating a clock signal in accordance with another aspect of the disclosure. The method1200includes generating a logic level difference signal based on a comparison of a logic level of an output clock signal with a logic level of a non-complementary clock signal (block1210). Examples of means for generating a logic level difference signal based on a comparison of a logic level of an output clock signal with a logic level of a non-complementary clock signal include the clock selection circuit930, logic level comparator1030, and exclusive-OR gate1135of CGCs900,1000, and1100, respectively.

The method1200further includes selecting the non-complementary clock signal or a complementary clock signal based on the logic level difference signal and an asserted enable signal (block1220). Examples of means for selecting the non-complementary clock signal or a complementary clock signal based on the logic level difference signal and an asserted enable signal include the multiplexers910and1010of CGCs900and1000, respectively, and the exclusive-NOR gate1110of CGC1100.

Additionally, the method1200includes outputting the selected one of the non-complementary clock signal or the complementary clock signal as the output clock signal in response to the asserted enable signal (block1230). Examples of means for outputting the selected one of the non-complementary clock signal or the complementary clock signal as the output clock signal in response to the asserted enable signal include clock gating device920, the latch1020, and the transmission gate1115/latch inverter1120/latch tristate inverter1125/output inverter1130of CGCs900,1000, and1100, respectively.

The selecting of the non-complementary clock signal or the complementary clock signal may include: selecting the non-complementary clock signal if the logic level difference signal is at a first logic value; and selecting the complementary clock signal if the logic level difference signal is at a second logic value. The method1200may further include maintaining the output clock signal at a fixed logic state in response to the enable signal becoming deasserted. Examples of means for maintaining the output clock signal at a fixed logic state and in response to the enable signal becoming deasserted include the clock gating device920, latch1020, and latch circuit including transmission gate1115, latch inverter1120, latch tristate inverter1125, and output inverter1130.

FIG.13illustrates a block diagram of an example wireless communication device1300in accordance with another aspect of the disclosure. The wireless communication device1300may be a smart phone, a desktop computer, laptop computer, tablet device, Internet of Things (IoT), wearable wireless device (e.g., wireless watch), and other types of wireless device.

In particular, the wireless communication device1300includes an integrated circuit (IC), which may be implemented as a system on chip (SOC)1310. The SOC1310includes one or more signal processing cores1320, and one or more clock gating circuits (CGCs)1330. The one or more CGCs1330may each be implemented per any of the CGCs900,1000, and1100described herein. The one or more signal processing cores1320may be configured to generate a transmit baseband (BB) signal and process a received baseband (BB) signal based on one or more clock signals received from the one or more CGCs1330.

The wireless communication device1300may further include a transceiver1350and at least one antenna1360(e.g., an antenna array). The transceiver1350is coupled to the one or more signal processing cores1320to receive therefrom the transmit BB signal and provide thereto the received BB signal. The transceiver1350is configured to convert the transmit BB signal into a transmit radio frequency (RF) signal, and convert a received RF signal into the received BB signal. The transceiver1350is coupled to the at least one antenna1360to provide thereto the transmit RF signal for electromagnetic radiation into a wireless medium for wireless transmission, and receive the received RF signal electromagnetically picked up from the wireless medium by the at least one antenna1360.

The following provides an overview of aspects of the present disclosure:

Aspect 1: An apparatus, comprising: a clock gating circuit (CGC), comprising: a clock gating circuit configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

Aspect 2: The apparatus of aspect 1, wherein the clock gating device is configured to pass the selected clock signal based on the enable signal being asserted.

Aspect 3: The apparatus of aspect 1 or 2, wherein the clock gating device is configured to generate the output clock signal at a fixed logic level based on the enable signal being deasserted.

Aspect 4: The apparatus of aspect 3, wherein the fixed logic level is a logic level of the output clock signal at substantially a time when the enable signal becomes deasserted.

Aspect 5: The apparatus of any one of aspects 1-4, wherein the clock selection circuit is configured to select the non-complementary clock signal or the complementary clock in response to the enable signal becoming asserted.

Aspect 6: The apparatus of any one of aspects 1-5, wherein the CGC further comprises a multiplexer including a first input configured to receive the non-complementary clock signal, a second input configured to receive the complementary clock signal, a select input configured to receive a select signal from the clock selection circuit, and an output configured to output the selected clock signal.

Aspect 7: The apparatus of any one of aspects 1-5, wherein the CGC further comprises a multiplexer including a non-inverting input configured to receive the non-complementary clock signal, an inverting input configured to receive and invert the non-complementary clock signal to generate the complementary clock signal, a select input configured to receive a select signal from the clock selection circuit, and an output configured to output the selected clock signal.

Aspect 8: The apparatus of any one of aspects 1-5, wherein the CGC further comprises a logic gate including a first input configured to receive the complementary clock signal, a second input configured to receive the select signal from the clock selection circuit, and an output configured to output the selected clock signal based on the select signal.

Aspect 9: The apparatus of aspect 8, wherein the logic gate comprises an exclusive-NOR gate.

Aspect 10: The apparatus of any one of aspects 1-9, wherein the clock gating device comprises a latch including a data input configured to receive the selected clock signal, a clock input configured to receive the enable signal, and a data output configured to output the output clock signal.

Aspect 11: The apparatus of any one of aspects 1-10, wherein the clock gating device comprises: a transmission gate including an input configured to receive the selected clock signal, a complementary control input configured to receive a complementary enable signal, and a non-complementary control input configured to receive a non-complementary enable signal; a latch inverter including an input coupled to an output of the transmission gate; and a latch tristate inverter including an input coupled to an output of the latch inverter, an output coupled to an input of the latch inverter, a complementary control signal configured to receive the non-complementary enable signal, and a non-complementary control signal configured to receive the complementary enable signal.

Aspect 12: The apparatus of aspect 11, wherein the CGC further comprises: a first inverter configured to generate the complementary enable signal based on the enable signal; and a second inverter configured to generate the non-complementary enable signal based on the complementary enable signal.

Aspect 13: The apparatus of aspect 11 or 12, wherein the clock gating device further comprises an output inverter coupled to an output of the latch inverter.

Aspect 14: The apparatus of any one of aspects 1-13, wherein the clock selection circuit comprises a logic level comparator including a first input configured to receive the output clock signal, a second input configured to receive the non-complementary clock signal or the complementary clock signal, and an output configured to output a logic level difference signal, wherein the selection of the non-complementary clock signal or the complementary clock is based on the logic level difference signal.

Aspect 15: The apparatus of aspect 14, wherein the logic level comparator comprises an exclusive-OR gate.

Aspect 16: The apparatus of aspect 14 or 15, wherein the clock selection circuit further comprises a latch including a data input coupled to an output of the logic level comparator, a clock input configured to receive the enable signal, and an output configured to generate a select signal to effectuate the selection of the non-complementary clock signal or the complementary clock signal.

Aspect 17: The apparatus of any one of aspects 14-16, wherein the clock selection circuit comprises: a transmission gate including an input coupled to an output of the logic level comparator, a complementary control input configured to receive a non-complementary enable signal, and a non-complementary control input configured to receive a complementary enable signal; a latch inverter including an input coupled to an output of the transmission gate; and a latch tristate inverter including an input coupled to an output of the latch inverter, an output coupled to an input of the latch inverter, a complementary control signal configured to receive the complementary enable signal, and a non-complementary control signal configured to receive the non-complementary enable signal.

Aspect 18: The apparatus of aspect 17, wherein the CGC further comprises: a first inverter configured to generate the complementary enable signal based on the enable signal; and a second inverter configured to generate the non-complementary enable signal based on the complementary enable signal.

Aspect 19: The apparatus of any one of aspects 1-18, further comprising a set of one or more dual-edge-triggered flip-flops including a set of one or more clock inputs configured to receive the output clock signal.

Aspect 20: An apparatus, comprising: a clock gating circuit (CGC), comprising: a multiplexer including a first input configured to receive a non-complementary clock signal and a second input configured to receive a complementary clock signal; a clock gating device including a first input coupled to an output of the multiplexer and a second input configured to receive an enable signal; and a clock selection circuit including a first input coupled to an output of the clock gating device, a second input configured to receive the non-complementary or complementary clock signal, a third input configured to receive the enable signal, and an output coupled to a select input of the multiplexer.

Aspect 21: The apparatus of aspect 20, wherein the clock gating device comprises a latch.

Aspect 22: The apparatus of aspect 20 or 21, wherein the clock gating circuit comprises: a transmission gate including an input coupled to the output of the multiplexer, a complementary control input configured to receive a complementary enable signal, and a non-complementary control input configured to receive a non-complementary enable signal; a latch inverter including an input coupled to an output of the transmission gate; and a latch tristate inverter including an input coupled to an output of the latch inverter, an output coupled to the input of the latch inverter, a complementary control signal configured to receive the non-complementary enable signal, and a non-complementary control signal configured to receive the complementary enable signal.

Aspect 23: The apparatus of any one of aspects 20-22, wherein the clock selection device comprises: a logic level comparator including a first input coupled to an output of the clock gating device and a second input configured to receive the non-complementary or complementary clock signal; and a latch including a first input coupled to the output of the logic level comparator, a second input configured to receive the enable signal, and the output coupled to the select input of the multiplexer.

Aspect 24: The apparatus of aspect 23, wherein the logic level comparator comprises a logic gate including the first input coupled to the output of the clock gating device, a second input configured to receive the non-complementary or complementary clock signal, and the output coupled to the first input of the latch.

Aspect 25: The apparatus of aspect 23 or 24, wherein the latch comprises: a transmission gate including the first input coupled to the output of the logic level comparator, the second input including a complementary control input configured to receive the enable signal, and a non-complementary control input configured to receive a complementary of the enable signal; a latch inverter including an input coupled to an output of the transmission gate; and a latch tristate inverter including an input coupled to an output of the latch inverter, an output coupled to the input of the latch inverter, a complementary control signal configured to receive the complementary enable signal, and a non-complementary control signal configured to receive the enable signal.

Aspect 26: The apparatus of any one of aspects 20-25, wherein the multiplexer comprises an inverter including the first input configured to receive the non-complementary clock signal, a logic gate including the second input coupled to an output of the inverter, the select input coupled to the output of the clock selection circuit, and the output coupled to the clock gating device.

Aspect 27: The apparatus of aspect 26, wherein the logic gate comprises an exclusive-NOR gate.

Aspect 28: A method, comprising: generating a logic level difference signal based on a comparison of a logic level of an output clock signal with a logic level of a non-complementary clock signal; selecting the non-complementary clock signal or a complementary clock signal based on the logic level difference signal and an asserted enable signal; and outputting the selected one of the non-complementary clock signal or the complementary clock signal as the output clock signal in response to the asserted enable signal.

Aspect 29: The method of aspect 28, wherein selecting the non-complementary clock signal or the complementary clock signal comprises: selecting the non-complementary clock signal if the logic level difference signal is at a first logic value; and selecting the complementary clock signal if the logic level difference signal is at a second logic value.

Aspect 30: The method of aspect 28 or 29, further comprising maintaining the output clock signal at a fixed logic state and in response to the enable signal becoming deasserted.

Aspect 31: An apparatus, comprising: means for generating a logic level difference signal based on a comparison of a logic level of an output clock signal with a logic level of a non-complementary clock signal; means for selecting the non-complementary clock signal or a complementary clock signal based on the logic level difference signal and an asserted enable signal; and means for outputting the selected one of the non-complementary clock signal or the complementary clock signal as the output clock signal in response to the asserted enable signal.

Aspect 32: The apparatus of aspect 31, wherein the means for selecting the non-complementary clock signal or the complementary clock signal comprises: means for selecting the non-complementary clock signal if the logic level difference signal is at a first logic value; and means for selecting the complementary clock signal if the logic level difference signal is at a second logic value.

Aspect 33: The apparatus of aspect 31 or 32, further comprising means for maintaining the output clock signal at a fixed logic state in response to the enable signal becoming deasserted.

Aspect 34: A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver, wherein the one or more signal processing cores comprises one or more clock gating circuits each comprising: a clock gating circuit configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.