Patent ID: 12216943

DETAILED DESCRIPTION

Some memory systems may use a different addressing scheme than an associated host system. For example, a host system may identify data using logical addresses (e.g., logical block addresses (LBAs), virtual addresses, system addresses, or other logical addresses) and the memory system may store the data at physical addresses that are independent of the logical addresses used by the host system. A physical address may identify a physical location of a corresponding memory cell (e.g., or a page of memory cells) within a memory device. The physical location of data within the memory device may change over time due to the memory device accommodating the writing of additional data, maintenance operations performed by the memory device (e.g., garbage collection operations), or for other reasons. A host system coupled with the memory system may reference data (e.g., if issuing read, write, or other commands associated with the data) using the logical addresses, and the memory system may generate and maintain a logical-to-physical (L2P) mapping between the logical addresses used in the communications with the host system and the physical addresses of the memory cells at which the data is stored.

A memory system may use a hierarchical L2P mapping that is divided into multiple subsets (or levels) to map a logical address to a corresponding physical address. The memory system may use the hierarchical L2P mapping to progressively translate a logical block address into the corresponding physical address. For example, a three-level L2P mapping may be divided into a relatively small first subset (e.g., or level) that may include entries that point to different locations of a second subset (e.g., or level). Entries of the second subset may point to different locations of a third subset (e.g., or level), and entries of the third subset may point to physical addresses of pages of data stored in a memory device of the memory system. Thus, to access data stored in the memory device, the memory system may navigate through the three subsets to identify the location of a requested page of data. Such an approach may allow for the relatively small first subset to be stored in a volatile memory device of the memory system for fast accesses and updates, but may increase read latency by introducing additional operations, such as two additional reads (e.g., for reading entries in the different subsets of the mapping) to identify the physical address of the data.

Techniques, systems, and devices are described herein for increasing performance and reducing latency associated with using L2P mappings by embedding a pivot table in entries of a second subset of L2P mappings to identify physical addresses of data, thereby bypassing the reading of an entry of a third subset of the L2P mapping. For example, a memory system receive a write command for a set of addresses and determine whether the set of addresses are consecutively indexed. The memory system may set a flag in a pivot table in the entry of the second subset based on the set of addresses being consecutively indexed and write data to the set of addresses in response to setting the flag. The flag may be set in the entry of the second subset to indicate that the entry of the second subset indicates a starting physical address.

In response to receiving a read command that includes an LBA corresponding to the data, the memory system may traverse a first subset of the L2P mapping and the second subset to locate and read the data without accessing a third subset. For example, the memory system may read an entry of a first subset corresponding to the LBA and may identify an entry of the second subset based on the first subset and the LBA. The memory system may read the entry of the second subset, which may include the pivot table. Using the pivot table, the memory system may identify a physical address associated with the LBA and access the data stored at that physical address. The memory system may then transmit the data to a host system coupled with the memory system. In this way, the memory system may reduce latency associated with using L2P mappings to locate data stored at consecutively indexed physical addresses by including the pivot table in the second subset and eliminating the reading of third subset to locate the data.

Features of the disclosure are initially described in the context of systems with reference toFIG.1. Features of the disclosure are described in the context of diagrams and structures with reference toFIGS.2-6. These and other features of the disclosure are further illustrated by and described in the context of an apparatus diagram and flowcharts that relate to integrated pivot table in a logical-to-physical mapping with reference toFIGS.7-9.

FIG.1illustrates an example of a system100that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The system100includes a host system105coupled with a memory system110.

A memory system110may be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, a memory system110may be or include a Universal Flash Storage (UFS) device, an embedded Multi-Media Controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

The system100may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), an Internet of Things (IOT) enabled device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

The system100may include a host system105, which may be coupled with the memory system110. In some examples, this coupling may include an interface with a host system controller106, which may be an example of a controller or control component configured to cause the host system105to perform various operations in accordance with examples as described herein. The host system105may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system105may include an application configured for communicating with the memory system110or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system105), a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., peripheral component interconnect express (PCIe) controller, serial advanced technology attachment (SATA) controller). The host system105may use the memory system110, for example, to write data to the memory system110and read data from the memory system110. Although one memory system110is shown inFIG.1, the host system105may be coupled with any quantity of memory systems110.

The host system105may be coupled with the memory system110via at least one physical host interface. The host system105and the memory system110may in some cases be configured to communicate via a physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system110and the host system105). Examples of a physical host interface may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fiber Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., DIMM socket interface that supports DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller106of the host system105and a memory system controller115of the memory system110. In some examples, the host system105may be coupled with the memory system110(e.g., the host system controller106may be coupled with the memory system controller115) via a respective physical host interface for each memory device130included in the memory system110, or via a respective physical host interface for each type of memory device130included in the memory system110.

The memory system110may include a memory system controller115and one or more memory devices130. A memory device130may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices130-aand130-bare shown in the example ofFIG.1, the memory system110may include any quantity of memory devices130. Further, if the memory system110includes more than one memory device130, different memory devices130within the memory system110may include the same or different types of memory cells.

The memory system controller115may be coupled with and communicate with the host system105(e.g., via the physical host interface) and may be an example of a controller or control component configured to cause the memory system110to perform various operations in accordance with examples as described herein. The memory system controller115may also be coupled with and communicate with memory devices130to perform operations such as reading data, writing data, erasing data, or refreshing data at a memory device130—among other such operations—which may generically be referred to as access operations. In some cases, the memory system controller115may receive commands from the host system105and communicate with one or more memory devices130to execute such commands (e.g., at memory arrays within the one or more memory devices130). For example, the memory system controller115may receive commands or operations from the host system105and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices130. In some cases, the memory system controller115may exchange data with the host system105and with one or more memory devices130(e.g., in response to or otherwise in association with commands from the host system105). For example, the memory system controller115may convert responses (e.g., data packets or other signals) associated with the memory devices130into corresponding signals for the host system105.

The memory system controller115may be configured for other operations associated with the memory devices130. For example, the memory system controller115may execute or manage operations such as wear-leveling operations, garbage collection operations, error control operations such as error-detecting operations or error-correcting operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system105and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices130.

The memory system controller115may include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations ascribed herein to the memory system controller115. The memory system controller115may be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

The memory system controller115may also include a local memory120. In some cases, the local memory120may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by the memory system controller115to perform functions ascribed herein to the memory system controller115. In some cases, the local memory120may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller115for internal storage or calculations, for example, related to the functions ascribed herein to the memory system controller115. Additionally or alternatively, the local memory120may serve as a cache for the memory system controller115. For example, data may be stored in the local memory120if read from or written to a memory device130, and the data may be available within the local memory120for subsequent retrieval for or manipulation (e.g., updating) by the host system105(e.g., with reduced latency relative to a memory device130) in accordance with a cache policy.

Although the example of the memory system110inFIG.1has been illustrated as including the memory system controller115, in some cases, a memory system110may not include a memory system controller115. For example, the memory system110may additionally or alternatively rely upon an external controller (e.g., implemented by the host system105) or one or more local controllers135, which may be internal to memory devices130, respectively, to perform the functions ascribed herein to the memory system controller115. In general, one or more functions ascribed herein to the memory system controller115may in some cases instead be performed by the host system105, a local controller135, or any combination thereof. In some cases, a memory device130that is managed at least in part by a memory system controller115may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

A memory device130may include one or more arrays of non-volatile memory cells. For example, a memory device130may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magneto RAM (MRAM), NOR (e.g., NOR flash) memory, Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, a memory device130may include one or more arrays of volatile memory cells. For example, a memory device130may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

In some examples, a memory device130may include (e.g., on a same die or within a same package) a local controller135, which may execute operations on one or more memory cells of the respective memory device130. A local controller135may operate in conjunction with a memory system controller115or may perform one or more functions ascribed herein to the memory system controller115. For example, as illustrated inFIG.1, a memory device130-amay include a local controller135-aand a memory device130-bmay include a local controller135-b.

In some cases, a memory device130may be or include a NAND device (e.g., NAND flash device). A memory device130may be or include a memory die160. For example, in some cases, a memory device130may be a package that includes one or more dies160. A die160may, in some examples, be a piece of electronics-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die160may include one or more planes165, and each plane165may include a respective set of blocks170, where each block170may include a respective set of pages175, and each page175may include a set of memory cells.

In some cases, a NAND memory device130may include memory cells configured to each store one bit of information, which may be referred to as single level cells (SLCs). Additionally or alternatively, a NAND memory device130may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLCs) if configured to each store two bits of information, as tri-level cells (TLCs) if configured to each store three bits of information, as quad-level cells (QLCs) if configured to each store four bits of information, or more generically as multiple-level memory cells. Multiple-level memory cells may provide greater density of storage relative to SLC memory cells but may, in some cases, involve narrower read or write margins or greater complexities for supporting circuitry.

In some cases, planes165may refer to groups of blocks170, and in some cases, concurrent operations may take place within different planes165. For example, concurrent operations may be performed on memory cells within different blocks170so long as the different blocks170are in different planes165. In some cases, performing concurrent operations in different planes165may be subject to one or more restrictions, such as identical operations being performed on memory cells within different pages175that have the same page address within their respective planes165(e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes165).

In some cases, a block170may include memory cells organized into rows (pages175) and columns (e.g., strings, not shown). For example, memory cells in a same page175may share (e.g., be coupled with) a common word line, and memory cells in a same string may share (e.g., be coupled with) a common digit line (which may alternatively be referred to as a bit line).

For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first level of granularity (e.g., at the page level of granularity) but may be erased at a second level of granularity (e.g., at the block level of granularity). That is, a page175may be the smallest unit of memory (e.g., set of memory cells) that may be independently programmed or read (e.g., programed or read concurrently as part of a single program or read operation), and a block170may be the smallest unit of memory (e.g., set of memory cells) that may be independently erased (e.g., erased concurrently as part of a single erase operation). Further, in some cases, NAND memory cells may be erased before they can be re-written with new data. Thus, for example, a used page175may in some cases not be updated until the entire block170that includes the page175has been erased.

In some cases, to update some data within a block170while retaining other data within the block170, the memory device130may copy the data to be retained to a new block170and write the updated data to one or more remaining pages of the new block170. The memory device130(e.g., the local controller135) or the memory system controller115may mark or otherwise designate the data that remains in the old block170as invalid or obsolete and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) for the data with the new, valid block170rather than the old, invalid block170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block170due to latency or wearout considerations, for example. In some cases, one or more copies of an L2P mapping table may be stored within the memory cells of the memory device130(e.g., within one or more blocks170or planes165) for use (e.g., reference and updating) by the local controller135or memory system controller115.

In some cases, L2P mapping tables may be maintained and data may be marked as valid or invalid at the page level of granularity, and a page175may contain valid data, invalid data, or no data. Invalid data may be data that is outdated due to a more recent or updated version of the data being stored in a different page175of the memory device130. Invalid data may have been previously programmed to the invalid page175but may no longer be associated with a valid logical address, such as a logical address referenced by the host system105. Valid data may be the most recent version of such data being stored on the memory device130. A page175that includes no data may be a page175that has never been written to or that has been erased.

In some cases, a memory system controller115or a local controller135may perform operations (e.g., as part of one or more media management algorithms) for a memory device130, such as wear leveling, background refresh, garbage collection, scrub, block scans, health monitoring, or others, or any combination thereof. For example, within a memory device130, a block170may have some pages175containing valid data and some pages175containing invalid data. To avoid waiting for all of the pages175in the block170to have invalid data in order to erase and reuse the block170, an algorithm referred to as “garbage collection” may be invoked to allow the block170to be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block170that contains valid and invalid data, selecting pages175in the block that contain valid data, copying the valid data from the selected pages175to new locations (e.g., free pages175in another block170), marking the data in the previously selected pages175as invalid, and erasing the selected block170. As a result, the quantity of blocks170that have been erased may be increased such that more blocks170are available to store subsequent data (e.g., data subsequently received from the host system105).

The system100may include any quantity of non-transitory computer readable media that support integrated pivot table in a logical-to-physical mapping. For example, the host system105, the memory system controller115, or a memory device130may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware) for performing the functions ascribed herein to the host system105, memory system controller115, or memory device130. For example, such instructions, if executed by the host system105(e.g., by the host system controller106), by the memory system controller115, or by a memory device130(e.g., by a local controller135), may cause the host system105, memory system controller115, or memory device130to perform one or more associated functions as described herein.

In some cases, a memory system110may utilize a memory system controller115to provide a managed memory system that may include, for example, one or more memory arrays and related circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller135). An example of a managed memory system is a managed NAND (MNAND) system.

In some cases, during a read operation, the memory system110may receive a read command, read an entry of a first subset of a mapping (e.g., a root map of the logical-to-physical mapping), read an entry of a second subset of the mapping (e.g., a global map of the logical-to-physical mapping), and transmit data the host system105. In such cases, the memory system110may read from a pivot table included in the entry of the second subset of the mapping. In some examples, during a write operation, the memory system110may receive a write command to write data to continuous physical addresses, write the data to the physical addresses, and set a continuous flag in an entry of the pivot table included in the second subset of the mapping (e.g., global map).

FIG.2illustrates an example of an entry diagram200that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The entry diagram200may implement aspects of a system100, as described with reference toFIG.1. For example, the entry diagram200may be implemented by a controller, such as a memory system controller115or a local controller135, or a memory device, such as a memory device130, or both, as described with reference toFIG.1. The entry diagram200may be implemented to reduce latency and power consumption and increase performance of a memory system, among other benefits.

The entry diagram200depicts a mapping205that may correspond to an L2P mapping as described herein. For example, the mapping205may be an example of a hierarchical L2P mapping that is divided into multiple subsets210. The mapping205may include at least a subset210-a, a subset210-b, and a subset210-c. The controller may maintain the mapping205to map LBAs generated by a host system coupled with the memory system to physical addresses235(e.g., page addresses) of a non-volatile memory device215(e.g., a memory device130that includes non-volatile memory cells, a NAND device) of the memory system.

The subset210-amay be an example of a root level or root mapping (e.g., first subset of the mapping205). The subset210-amay include entries220-aup to220-w, where w is some positive integer. In some cases, the subset210-amay include a relatively small quantity of entries220(e.g., w may be a relatively small positive integer) such that the controller may store the subset210-ain a volatile memory device (e.g., local memory120, a memory device130that includes volatile memory cells, an SRAM device) of the memory system to allow for faster accesses and updates.

The subset210-bmay be an example of global level or global mapping (e.g., second subset of the mapping205). The subset210-bmay include entries225-aup to225-x, where x is some positive integer. In some examples, the subset210-bmay include a relatively large quantity of entries225(e.g., x may be a relatively large positive integer) such that the controller may store the subset210-bin the non-volatile memory device215(e.g., at physical addresses235not shown). Accordingly, in order to read an entry225of the subset210-b, the controller may transfer a portion of the subset210-bthat includes the entry225from the non-volatile memory device215to the volatile memory device. After reading the entry225, the controller may transfer the portion of the subset210-bback to non-volatile memory device215.

The subset210-cmay be an example of L2P level or L2P mapping (e.g., third subset of the mapping205). In some examples, the subset210-cmay be an example of physical page table (PPT) level or PPT mapping. The subset210-cmay include entries230-aup to230-y, where y is some positive integer. In some examples, the subset210-cmay include a relatively large quantity of entries230(e.g., y may be a relatively large positive integer) such that the controller may store the subset210-cin the non-volatile memory device215(e.g., at physical addresses235not shown). Accordingly, in order to read an entry230of the subset210-c, the controller may transfer a portion of the subset210-cthat includes the entry230from the non-volatile memory device215to the volatile memory device. After reading the entry230the controller may transfer the portion of the subset210-cback to the non-volatile memory device215.

In some examples, each subset210may be an individual L2P mapping table stored in the memory system. For example, the subset210-amay be a first level L2P mapping table that is stored in the volatile memory device. Here, each entry220may point to a different second level L2P table. For example, the subset210-bmay include multiple second level L2P tables that each include a corresponding set of entries225. Here, the controller may use an entry220and an offset (e.g., indicated by an LBA) to determine the corresponding entry225within the second level L2P table pointed to by the entry220. Additionally, in some cases, each entry225may point to a different third level L2P table. For example, the subset210-cmay include multiple third level L2P tables that each include a corresponding set of entries230. Here, the controller may use the entry225and a second offset (e.g., indicated by the LBA) to determine the corresponding entry230within the third level L2P table pointed to by the entry225.

For example, the controller may use an LBA to identify an entry220of the subset210-a, the entry220to identify an entry225of the subset210-b, the entry225to identify an entry230of the subset210-c, and the entry230to identify a physical address235corresponding to the LBA. That is, to identify the corresponding physical address235, the controller may, in some cases, traverse the first level, second level, and third level of the mapping205. However, traversing the three levels of the mapping205may include transferring portions of the subsets210-a,210-b, and210-cto the volatile memory device to read various entries. Each entry of the mapping205that is read and portion of a subset210that is transferred may increase a latency associated with using the mapping205(e.g., to identify the corresponding physical address235). Accordingly, techniques to reduce a quantity of entries of the mapping205that are read and portions of subsets210that are transferred may reduce the latency associated with the using the mapping205.

The controller may reduce a quantity of entries of the mapping205that are read and, by extension, a quantity of portions of subsets210that are transferred to the volatile memory device by setting an entry225to indicate a physical address235rather than an entry230. For example, if data stored in a set of physical addresses235are consecutively indexed, the controller may set an entry225to indicate a starting physical address235of the set of consecutively indexed physical addresses235. For example, data corresponding to a first LBA may be stored at a set of consecutively indexed physical addresses235that includes at least a physical address235-a, a physical address235-b, and a physical address235-c, where the physical address235-ais a starting physical address of the set of consecutively indexed physical addresses235.

The controller may set an entry225-ato indicate the physical address235-a. For example, the entry225-amay include a flag240and at least a portion of a pivot table250. The flag240may indicate whether the entry225is associated with an entry230of the subset210-cor is associated with a starting physical address235of a set of consecutively indexed physical addresses235. The pivot table250may include a plurality of entries where an entry of the plurality of entries represents a plurality of logical block addresses that are consecutively indexed and the instructions to identify a starting physical address235of a plurality of physical addresses235that are consecutively indexed. To address an increased quantity of data associated with the host system (e.g., user data) able to fit within the mapping205(e.g., in 1 MB), the controller may determine whether the data includes sequential data. For example, the controller may determine whether the blocks may be written logically and physically in sequential order (e.g., consecutively indexed).

Based on the flag240and the pivot table250, the physical address of entry225-amay correspond to either a physical address of the entry230or the starting physical address235-a. Accordingly, in the example ofFIG.2, the controller may set the flag240of the entry225-ato indicate that the entry225-acorresponds to the set of consecutively indexed physical addresses235. Additionally, the controller may read of the entry225-a(e.g., including the entry of the pivot table250) to indicate the starting physical address235-a. In this way, the controller may set the entry225-ato refrain from (e.g., skip) reading and transferring a portion of the subset210-cthat includes an entry230. For example, controller may receive a read command that includes the first LBA (e.g., from the host system). The controller may use the first LBA to identify and read the entry220-a, which the controller may use to identify and read the entry225-a. The controller may determine that the pivot table250indicates the starting physical address235-abased on the flag240and may read the data corresponding to the first LBA starting at the physical address235-a. The controller may then transmit the data to the host system.

In some cases, the LBA used to identify an entry220of the subset210-a(e.g., and subsequently an entry225of the subset210-b) may not correspond to the physical addresses in the pivot table250. In such cases, the pivot table250may indicate a starting physical address235that corresponds to a starting LBA. For example, the controller may determine a difference between the LBA in the command and the starting LBA. The controller may then use the determined difference between the LBA and the starting LBA to identify the physical address235. For example, the controller may combine the difference between the LBAs with the starting physical address stored in the pivot table to determine the desired physical address. In some examples, the controller may use an entry220and an offset (e.g., a difference between the LBA and the starting LBA) to determine the corresponding entry225within the second level L2P table pointed to by the entry220. The controller may use the entry225and a second offset (e.g., a difference between the LBA and the starting LBA) to determine the corresponding entry230within the third level L2P table pointed to by the entry225.

To increase the range of LBAs that may be addressed by the mapping205, the system may integrate a pivot table250into the mapping205. For example, the pivot table250may be generated and integrated into subset210-bof the mapping205. In such cases, by embedding the pivot table250into subset210-b, the range of LBAs that may be addressed by the controller without accessing the NAND may increase, thereby improving the overall performance of the system and decreasing latencies. In some examples, a pivot table may be an example of a data structure or mapping that summarizes or compresses information associated with a more extensive data structure or mapping. In some cases, the pivot table may be an example of a condensed version of the physical addresses associated with the memory system.

Alternatively, data may be stored at a set of physical addresses235that includes one or more physical addresses235that are non-consecutive with other physical addresses235of the set. For example, data corresponding to a second LBA may be stored at a set of physical addresses235that includes at least a non-consecutive physical address235-d. Accordingly, the controller may identify the pointer245to indicate that the entry225-bis associated with (indicates the physical address of) an entry230(e.g., an entry230-a). Additionally, the controller may identify the pointer245of the entry225-bto indicate (e.g., to include the physical address of) the entry230-aand may set the entry230-ato indicate the physical address235-d. In such cases, the controller may refrain from setting the flag240. The controller may read a second entry (e.g., entry225-b) that includes the pointer245and represents the logical block address that is non-consecutively indexed with other logical block addresses.

Accordingly, in response to receiving a read command that includes the second LBA, the controller may use the second LBA to identify and read the entry220-bwhich the controller may use to identify and read the entry225-b. The controller may determine that the pointer245indicates the physical address of the entry230-a. Accordingly, the controller may identify and read the entry230-ato identify the physical address235-dand read the data corresponding to the second LBA stored at the physical address235-d. The controller may then transmit the data to the host system.

In some cases, the range of LBA's that may be addressed from the controller without having to fetch (e.g., retrieve) the L2P map from NAND to determine where data may be stored may be increased. In some systems, one (1) GB addressing range may utilize one (1) MB of embedded SRAM to store a quantity of L2P maps (e.g., 1024 KB divided by 4 B multiplied by 4 KB). To expand (e.g., increase the addressing range), the system may increase the mapped data size from 4 KB to 512 KB.

In some examples, an entry230of the subset210-cmay be 4 B size and managed as 4 KB units on a 2048 GB device, as illustrated in Table 1.

TABLE 1PhysicalMappingTableCacheRecordMappingSubsetSizeSizeTypeSizeRegionSubset2 KB2KBStatic4 B4 GB210-aSubset2 MB8-32KBStatic4 B4 MB210-bSubset2 GB256-1024KBDynamic4 B4 KB210-c

The physical table size to support a 2048 GB drive may include 2 KB of subset210-a(e.g., 512 entries (e.g., entries220) multiplied by 4 B (e.g., the record size)). The physical table size to support a 2048 GB drive may include 2 MB of subset210-b(e.g., 512 entries multiplied by 1024 entries (e.g., entries225) multiplied by 4 B). The physical table size to support a 2048 GB drive may include 2 GB of subset210-c(e.g., 512 entries multiplied by 1024 entries multiplied by 1024 entries (e.g., entries230) multiplied by 4 B). The L2P cache (e.g., subset210-c) addressing range may be 1 GB (e.g., 1024 KB divided by 4 B entries multiplied by 4 KB). In other examples, an entry230of the subset210-cmay be 4 B size and managed as 4 KB units on a 2048 GB device, as illustrated in Table 2.

TABLE 2MappingPhysicalRecordSubsetTable SizeCache SizeTypeSizeMapping RegionSubset 210-a16 KB16KBStatic4 B0.5GBSubset 210-b16 MB8-32KBStatic4 B0.5MBSubset 210-c2048 MB256-1024KBDynamic4 B4KB

In some examples, the size of the subset210-cmay be 1024 KB (e.g., LBAs), the range of the pivot table250included in the subset210-bmay be 128 (e.g., LBAs), and the pivot per PPT may be 8 (e.g., 1024 entries (size of the subset210-c) divided by 128 pivot range (e.g., the range of the pivot table250)). The physical table size to support a 2048 GB drive may include 16 KB of subset210-a(e.g., 512 entries220multiplied by 8 (e.g., the pivot per table) multiplied by 4 B (e.g., the record size)). The physical table size to support a 2048 GB drive may include 16 MB of subset210-b(e.g., 512 entries220multiplied by 8 (e.g., pivot per table) multiplied by 1024 entries225multiplied 4B (e.g., the record size)). The physical table size to support a 2048 GB drive may include 2048 MB of subset210-c(e.g., 512 entries220multiplied by 1024 entries225multiplied by 1024 entries230multiplied by 4 B (e.g., the record size)). The global cache (e.g., subset210-b) addressing range (e.g., of direct data) may be 128 GB (e.g., 1 MB divided by 4 B entries225multiplied by the 128 (e.g., range of the pivot table250) multiplied by 4 KB). The L2P cache (e.g., subset210-c) addressing range may be 1 GB (e.g., 1 MB divided by 4 B entries225multiplied by 4 KB).

By integrating the pivot table250into the subset210-b, the size of the mapping may increase from 2 MB to 16 MB for subset210-b. In such cases, the subset210-bmay store an increased quantity of pointers. The mapping region granularity of subset210-bmay be updated from 4 MB to 0.5 MB (e.g., 512 KB). By increasing the size of subset210-b, the system may address an increased quantity of data. Instead of addressing 1 GB of address space, if the controller determines that the physical address are sequential (e.g., consecutively indexed), the controller may address 128 GB of address space.

FIG.3illustrates an example of pivot table structures300that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The pivot table structures300may implement aspects of a system100and entry diagram200, as described with reference toFIGS.1and2. For example, the pivot table structures300may be implemented by a controller, such as a memory system controller115or a local controller135, or a memory device, such as a memory device130, or both, as described with reference toFIG.1. The pivot table structures300may be implemented to reduce latency and power consumption and increase performance of a memory system, among other benefits.

The pivot table structures300may include L2P table305and pivot table310. The L2P table305may include entries315-aup to 315-w, where w is some positive integer. For example, w may be 1024 where the L2P table305may include 1024 entries315. Each entry315of the L2P table305may include physical addresses and point to 4 K entries. The L2P table305may include intervals325where each interval325includes a quantity of entries315. For example, each interval325may include 128 entries315. In such cases, the entries315(e.g., sampled physical address values) may be selected at 128 intervals325. The quantity of entries315in the interval325(e.g., 128) may be an example of a pivot range. In some cases, the L2P table305may be an example of a PPT.

In some cases, the physical addresses in each of the 128 chunks (e.g., intervals325) may include sequential data and may be either invalid or valid data. For example, the entry315-aof interval325-amay include sequential, valid data. The entry315-bof interval325-bmay include sequential, invalid data. The memory system may store the first entry315(e.g., physical address) for each interval325in the pivot table310which may enable the memory system to retrieve the relevant information from the mapping.

The pivot table310may include a plurality of entries320up to320-x, where x is some positive integer. For example, x may be 8 where the pivot table310may include 8 entries320. The quantity of entries320in the pivot table310may be an example of a pivot per physical page table. To generate the pivot table310, the memory system may include a first entry315from each interval325of the L2P table305. For example, the pivot table310may include at least the first entry315-aof the first interval325-a, the first entry315-bof the second interval325-b, and the first entry315-cof the third interval325-c. In such cases, the pivot table310may include the first entry315of each of the eight intervals325of the L2P table305. In some cases, the memory system may include a pivot table310for each L2P table305or a segment of the L2P table305.

In some cases, the entry320-a(e.g., including the first entry315-aof the first interval325-a) may represent a plurality of logical block addresses that are consecutively indexed and the instructions to identify a starting physical address of a plurality of physical addresses that are consecutively indexed. The physical addresses may correspond to the logical block addresses. In some examples, the entry320-b(e.g., including the first entry315-bof the second interval325-b) may represent a plurality of logical block addresses that include invalid data. The pivot table310may summarize information about physical addresses in 128 entry chunks (e.g., intervals325).

The memory system may receive a request to perform a read or write operation and generate the pivot table310. To generate the pivot table310, the memory system may replace an entry of the second subset of mapping (e.g., global level or global mapping) with the pivot table310. In some systems, the first entry of the second subset of mapping may include a pointer. In such cases, the memory system may replace the pointer with the at least a portion of the pivot table310. The memory system may store the pivot table in the entry of the second subset of the mapping in response to receiving write commands.

For example, the pivot table310may be embedded within the second subset of the mapping. In such cases, the memory system may receive a read command associated with a first logical block address. The memory system may read an entry (e.g., entry320-a) of the pivot table310included in the second subset of the mapping, and the entry320-amay indicate whether the address is a starting physical address of a plurality of physical addresses that are consecutively indexed or associated with a third subset of the mapping. The memory system may retrieve and transmit data based on the entry320-aof the pivot table310.

The memory system may convert logical block addresses to physical addresses using the L2P table305. The size of the L2P table305may be greater than a size that may be maintained in the system on chip (SoC) memory. In such cases, a subset of the L2P table305may be stored in the memory and the remaining subsets of the L2P table305may be stored in the NAND. The subsets of the L2P table305may include sequentially written LBAs. In such cases, the memory system may generate a compressed representation of the L2P table305based on the sequentially written data. The pivot table310may include the compressed subset of the L2P table305and may be stored in SoC memory. In some cases, a bitmap pivot table may be used to verify that the logical block address has been written in a continuous sequence of physical addresses or whether it has been written out of sequence by random writes.

The bitmap pivot table may be generated by starting with the value of the pivot table310as a base of “expected physical addresses” and use that to compare with the range of corresponding values in the L2P table305. If the value from the L2P table305may be in line with the sequence of “expected physical addresses” by the pivot table310, the associated bit in the bitmap pivot table may be set. If the L2P table305value fails to follow the sequence, the bitmap pivot table may be cleared to 0. In some cases, the pivot table310entry320-bmay include invalid data. In such cases, the bitmap pivot table for the 128 logical block address sequence (e.g., interval325-b) may be cleared to 0. The bitmap pivot table may include a bit for each of the 128 logical block addresses represented by an entry320of the pivot table310.

Each entry320of the pivot table310may represent a group of 128 logical block addresses where the value of the first physical address (e.g., entry315-a) may be recorded as the entry320-aof the pivot table310. The first entry320-aof the pivot table310may include a consecutively written set of physical addresses. In such cases, the bitmap pivot table may be written with 1's. The second entry320-bof the pivot table310may include invalid data. In such cases, the bitmap pivot table may be written with 0's. The third entry320-cmay include a combination of sequentially written physical addresses and random physical addresses. In such cases, the bitmap pivot table may be written with a combination of 1's and 0's.

In some examples, the memory system may identify an entry320(e.g., PBA(n)) from LBA(n) by using a starting LBA (e.g., LBA(0)) and the starting physical address (e.g., entry320-a) stored in the pivot table310. The entry320-amay be an example of PBA(0). For example, the memory system may determine a difference between the LBA(n) and the starting LBA (e.g., LBA(0)). The difference may be used to identify the entry320(e.g., PBA(n)). In such cases, by compressing the data, the memory system may perform an algorithm to determine the physical address of entry320.

FIG.4illustrates an example of a read diagram400that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The read diagram400may implement aspects of the systems, as described with reference toFIGS.1-3. For example, the read diagram400may be implemented by a controller, such as a memory system controller115or a local controller135, or a memory device, such as a memory device130, or both, as described with reference toFIG.1.

The read diagram400depicts an operation which may correspond to a read operation as described hereon. The read diagram400may include at least a subset410-a, subset410-b, and non-volatile memory device415, which may be examples of subset210-b, subset210-c, and non-volatile memory device215as described with reference toFIG.2. The subset410-amay be an example of pivot table310as described with reference toFIG.3.

The subset410-amay be an example of global level or global mapping (e.g., second subset of the mapping). The subset410-amay include entries425-aup to425-x, where x is some positive integer. For example, the subset410-amay include 8 entries425. The subset410-bmay be an example of L2P/PPT level or mapping (e.g., third subset of the mapping). The subset410-bmay include entries430-aup to430-y, where y is some positive integer. The non-volatile memory device415may include physical addresses435-aup to435-z, where z is some positive integer.

In some cases, each entry425may point to subset410-bor the non-volatile memory device415. For example, the entry425may point to the non-volatile memory device415. Data corresponding to a first LBA may be stored at a set of consecutively indexed physical addresses435that includes at least a physical address435-aand a physical address435-b, where the physical address435-ais a starting physical address of the set of consecutively indexed physical addresses435. The memory system may set an entry425-ato indicate the physical address435-a. For example, the entry425-amay indicate a starting physical address435of a set of consecutively indexed physical addresses435. In such cases, the entry425-amay correspond to the set of consecutively indexed physical addresses435.

The memory system may perform sequential read405to read the entry425-a(e.g., including the entry of the pivot table) to indicate the starting physical address435-a. In this way, the memory system may set the entry425-ato refrain from (e.g., skip) reading and transferring a portion of the subset410-bthat includes an entry430. For example, the memory system may receive a read command that includes the first LBA (e.g., from the host system). The memory system may use the first LBA to identify (e.g., read) the entry425-a. The memory system may determine that the entry425-aindicates the starting physical address435-aand may read the data corresponding to the first LBA starting at the physical address435-a. The memory system may then transmit the data to the host system.

In other examples, the memory system may use the LBA to identify (e.g., read) the entry425where the entry425may not be a starting physical address (e.g., may not indicate the starting physical address435-a). For example, if the LBA in the read command is LBA(n) where n is greater than zero (0) (e.g., not the starting LBA), then the memory system may identify PBA(n) using PBA(0) and the LBA(n). The memory system may read the data corresponding to the LBA starting at the physical address435(e.g., PBA(n)). In such cases, the physical address may correspond to the logical block address.

In some examples, the entry425may point to the non-volatile memory device415. In such cases, data may be stored at a set of physical addresses435that includes one or more physical addresses435that are non-consecutive with other physical addresses435of the set. For example, data corresponding to a second LBA may be stored at a set of physical addresses435that includes at least a non-consecutive physical address435-z. The memory system may identify that the entry425-bis associated with (indicates the physical address of) an entry430(e.g., an entry430-a). The memory system may set the entry430-ato indicate the physical address435-z.

In some examples, the memory system may use the entry425-band an offset (e.g., indicated by the LBA) to determine the corresponding entry230within the subset410-bpointed to by the entry425-b. In such cases, the memory system may use the entry425-bto identify an entry430of the subset410-b, and the entry430to identify a physical address435corresponding to the LBA. The physical address of entry425-bmay correspond to a physical address of the entry430(e.g., entry430-a). The memory system may read a second entry (e.g., entry425-b) that represents the logical block address that is non-consecutively indexed with other logical block addresses. The memory system may identify and perform random read420to read the entry430-ato identify the physical address435-zand then perform read440to read the data corresponding to the second LBA stored at the physical address235-z. The memory system may then transmit the data to the host system.

In some system, subset410-amay include a single pointer. By embedding the pivot table within the subset410-aquantity of pointers may be increased from a single pointer to 8 pointers (e.g., 8 entries425). For example, the entry425-amay point to non-volatile memory device415and the entry425-bmay point to subset410-b. In such cases, the subset410-amay include a hybrid of pointers that may point to subset410-bor non-volatile memory device415. The granularity of the subset410-amay be reduced from each entry425pointing to 4 MB to each entry425pointing to 512 KB, thereby increasing the overall performance of the memory system. In such cases, each of the 8 entries425points to 512 KB which equals a total of 4 MB that the subset410-apoints to.

To expand the addressable range of logical block addresses, each 4 MB pointer of the subset410-amay be replaced with a pivot table segment. The pivot table entries defined by the pivot table range may divide each 4 MB physical address of the subset410-ainto multiple entries425that may point directly to sequential data in the NAND or to L2P mapping stage (e.g., subset410-b) if the data is random. For example, the size of the PPT (e.g., 1024 entries) divided by the pivot range (e.g., 128 entries within each interval) equals a quantity of entries425(e.g., 8 entries425) in the subset410-a.

The data may be compressed by each 4 B entry in the subset410-apointing directly to sequential data in the NAND (e.g., non-volatile memory device415) while the analogous L2P map entries may be unused. For example, if each entry425in the subset410-arepresents 512 KB, then the compression ratio is 128:1. The data compression may be expressed by a quantity of mapped logical block addresses in 1 MB of controller SRAM buffer. A lower limit of a size of mapped logical block addresses may be equal to 1 MB divided by 4 B physical addresses multiplied by the pivot range (e.g., 128) multiplied by 4 KB. In such cases, the lower limit of the size of mapped logical block addresses may be 128 GB. For example, each 4 B physical address may point to 512 KB of sequential data. The quantity of mapped logical block addresses may be data dependent.

If the sequence of logical block addresses may not be sequentially written into the NAND, the entry425of subset410-amay point to the subset410-b, and the memory system may fetch the L2P from the NAND (e.g., non-volatile memory device415). In some cases, a 512 KB pivot range may be used for the tracking of sequential data.

The read command associated with the sequential read405may directly address the NAND, and the sequential physical address stored in the subset410-amay be incremented by one to read the associated data. The read command associated with the random read420may be associated with non-sequential physical addresses, and the memory system may fetch (e.g., retrieve) the associated L2P level map (e.g., subset410-b) to directly address the data of non-volatile memory device415associated with a host system.

FIG.5illustrates an example of a flow diagram500that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The operations of flow diagram500may be implemented by any device or its components as described herein. For example, the operations of flow diagram500may be performed by a memory system as described with reference toFIG.1. Alternative examples of the following may be implemented, where some steps are performed in a different order or not at all. Some steps may additionally include additional features not mentioned below. The flow diagram500illustrates techniques where a memory system may use integrated pivot table in a logical-to-physical mapping for a read operation.

Aspects of the flow diagram500may be implemented by a controller, among other components. Additionally or alternatively, aspects of the flow diagram500may be implemented as instructions stored in a controller (e.g., controller coupled with the memory system). For example, the instructions, when executed by a controller (e.g., the memory system controller115), may cause the controller to perform the operations of the flow diagram500.

At505, a read command may be received. For example, the memory system may receive a read command. The read command may include a logical block address of a non-volatile memory device. At510, a first entry may be read. For example, the memory system may read, based at least in part on the logical block address, a first entry of a first subset of a mapping. In some cases, the first entry may define a relationship between the logical block address and a physical address. The first subset of the mapping may be an example of a root mapping or root level.

At515, a second entry may be read. For example, the memory system may read, based at least in part on reading the first entry of the first subset, a second entry of a second subset of the mapping. In some cases, the second entry may include at least a portion of a pivot table associated with physical addresses of the non-volatile memory device. The second subset of the mapping may be an example of a global mapping or global level.

In some examples, the second entry of the second subset may include a flag that indicates whether the second entry is associated with a third subset of the mapping or is associated with a starting physical address of a set of physical addresses associated with the read command. The third subset of the mapping may be an example of a L2P mapping or L2P level. In other examples, the third subset of the mapping may be an example of a PPT mapping or PPT level. In some cases, the pivot table of the second subset of the mapping may include a flag that indicates whether the physical addresses are consecutively indexed (e.g., continuous).

The pivot table may include a plurality of entries where an entry of the plurality of entries may represent a plurality of logical block addresses that are consecutively indexed. In such cases, an entry of the pivot table may identify a starting physical address of a plurality of physical addresses that are consecutively indexed. The plurality of physical addresses may correspond to the plurality of logical block addresses. In some examples, the memory system may read the second entry of the second subset of the mapping by reading the entry of the plurality of entries. For example, the memory system may read a first entry (e.g., segment of the pivot table). In some cases, the entry in the pivot table may point to the third level of the mapping (e.g., L2P table or PPT).

At520, a determination may be made. For example, the memory system may determine whether the physical addresses of the set of physical addresses are consecutively indexed in response to reading the second entry of the second subset of the mapping. In such cases, the memory system may determine whether the physical addresses associated with the read command are continuous and determine whether the flag is set based on the physical addresses being continuous. In some examples, the memory system may determine that the physical addresses are consecutively indexed.

At525, user data may be retrieved. For example, the memory system may retrieve, from the non-volatile memory device, the data from the physical address identified using the pivot table of the second entry in direct response to determining that the physical addresses are consecutively indexed. The data may be retrieved from the physical address without reading a third subset of the mapping. In some examples, the data may correspond to user data from the non-volatile memory device.

In some cases, the memory system may refrain from reading a third entry of a third subset of the mapping based on a flag indicating that the second entry of the second subset of the mapping is associated with the physical addresses of the non-volatile memory device. The memory system may refrain from transferring, from the non-volatile memory device to a volatile memory device, at least a portion of a third subset of the mapping based on a flag indicating that the second entry of the second subset of the mapping is associated with the physical addresses of the non-volatile memory device. In such cases, the memory system may refrain from reading the third subset of the mapping or refrain from loading the third subset of the mapping in response to determining that the physical addresses are consecutively indexed or both.

At530, a starting physical address may be identified. For example, the memory system may identify a starting physical address of a plurality of physical addresses that are consecutively indexed using the pivot table of the second entry. The memory system may identify the physical address to access based on a starting logical block address and a difference between the starting logical block address and the logical block address. In such cases, the memory system may identify a starting address and determine an offset.

At535, data may be transmitted. For example, the memory system may transmit, to a host system, data retrieved from the physical address identified in the pivot table of the second subset of the mapping in response to reading the second entry of the second subset of the mapping. In some cases, transmitting the data may be in direct response to determining that the physical addresses are consecutively indexed and retrieving the data.

In some examples, the memory system may determine that the physical addresses are not consecutively indexed (e.g., random). In such case, at540, a portion of the third subset may be transferred. For example, the memory system may transfer, from the non-volatile memory device to a volatile memory device, at least a portion of a third subset of the mapping based on a flag indicating that the second entry of the second subset of the mapping is associated with the physical addresses of the non-volatile memory device. In such cases, the memory system may transfer, to a volatile memory device, at least the portion of the third subset of the mapping in direct response to determining that the physical addresses are not consecutively indexed.

At545, a third entry may be read. For example, the memory system may read a third entry of a third subset of the mapping based on a flag indicating that the second entry of the second subset of the mapping is associated with the physical addresses of the non-volatile memory device. The memory system may read the third entry of the third subset in response to transferring the portion of the third subset of the mapping.

At550, data may be transmitted. For example, the memory system may transmit, to a host system, data retrieved from the physical address identified in the pivot table of the second subset of the mapping in response to reading the third entry of the third subset of the mapping.

FIG.6illustrates an example of a flow diagram600that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The operations of flow diagram600may be implemented by any device or its components as described herein. For example, the operations of flow diagram600may be performed by a memory system as described with reference toFIG.1. Alternative examples of the following may be implemented, where some steps are performed in a different order or not at all. Some steps may additionally include additional features not mentioned below. The flow diagram600illustrates techniques where a memory system may use integrated pivot table in a logical-to-physical mapping for a write operation.

Aspects of the flow diagram600may be implemented by a controller, among other components. Additionally or alternatively, aspects of the flow diagram600may be implemented as instructions stored in a controller (e.g., controller coupled with the memory system). For example, the instructions, when executed by a controller (e.g., the memory system controller115), may cause the controller to perform the operations of the flow diagram600.

At605, write commands may be received. For example, the memory system may receive a plurality of write commands for a set of physical addresses of a non-volatile memory device. At610, a pivot table may be identified. For example, the memory system may identify that the pivot table is included in the second subset of the mapping in response to receiving the plurality of write commands. In such cases, the pivot table may be identified in the global map or global level. The memory system may generate the pivot table to be included in the second subset of the mapping in direct response to receiving the plurality of write commands. In some cases, the memory system may replace the entry of the second subset of the mapping that includes a pointer with at least the portion of the pivot table. For example, the pointer of the second subset of the mapping may be replaced with the pivot table.

The pivot table may include a plurality of entries where a first entry of the plurality of entries may represent a plurality of logical block addresses that are consecutively indexed. The pivot table may identify a starting physical address of a plurality of physical addresses that are consecutively indexed where the plurality of physical addresses correspond to the plurality of logical block addresses.

At615, the pivot table may be stored. For example, the memory system may store at least the portion of the pivot table in the entry of the second subset of the mapping in response to receiving the plurality of write commands. In some examples, the memory system may store the portion of the pivot table in response to generating the pivot table, identifying the pivot table, replacing the pointer with the pivot table, or a combination thereof.

At620, a determination may be made. For example, the memory system may determine whether the set of physical addresses are consecutively indexed in response to receiving the plurality of write commands. In some cases, the memory system may determine that the set of physical addresses are consecutively indexed.

At625, a flag may be set. For example, the memory system may set, based on the set of physical addresses being consecutively indexed, a flag in an entry of a second subset of a mapping. The mapping may include a first subset (e.g., root mapping or root level), the second subset, and a third subset (e.g. L2P table or L2P level). The memory system may set the flag in the entry in direct response to determining that the physical addresses are consecutively indexed. The entry of the second subset includes at least a portion of a pivot table associated with the set of physical addresses. In some case, the flag may indicate that the entry is associated with a starting physical address of the set of physical addresses associated with the plurality of write commands. The memory system may set the flag in response to identifying the pivot table, generating the pivot table, replacing the entry, storing at least the portion of the pivot table, or a combination thereof.

At630, an entry may be set. For example, the memory system may set the entry of the second subset of the mapping to indicate a starting physical address in response to determining that the set of physical addresses are consecutively indexed. In such cases, the memory system may set the entry of the second subset of the mapping to include the starting physical address of the data located in the NAND. At635, data may be written. For example, the memory system may write data to the set of physical addresses in response to setting the flag.

The memory system may determine that the set of physical addresses are not consecutively indexed (e.g., random). In such cases, at640, a flag may be set. For example, the memory system may set, based on the set of physical addresses failing to be consecutively indexed, a flag in an entry of a third subset of a mapping. The flag may indicate that the entry is associated with the third subset of the mapping. In such cases, the memory system may determine that the physical addresses are randomly indexed and set the flag in direct response to the determination.

At645, an entry may be set. For example, the memory system may set the entry of the third subset of the mapping in response to determining that the set of physical addresses are not consecutively indexed. In such cases, the memory system may determine that the physical addresses are randomly indexed and set the entry in direct response to the determination. At650, data may be written. For example, the memory system may write data to the set of physical addresses in response to setting the flag.

FIG.7shows a block diagram700of a memory system720that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The memory system720may be an example of aspects of a memory system as described with reference toFIGS.1through6. The memory system720, or various components thereof, may be an example of means for performing various aspects of integrated pivot table in a logical-to-physical mapping as described herein. For example, the memory system720may include a command receiver725, a root component730, a global component735, a data transmitter740, an index component745, a flag component750, a write component755, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The command receiver725may be configured as or otherwise support a means for receiving a read command including a logical block address of a non-volatile memory device. The root component730may be configured as or otherwise support a means for reading, based at least in part on the logical block address, a first entry of a first subset of a mapping that defines a relationship between the logical block address and a physical address. The global component735may be configured as or otherwise support a means for reading, based at least in part on reading the first entry of the first subset, a second entry of a second subset of the mapping, the second entry including at least a portion of a pivot table associated with physical addresses of the non-volatile memory device. The data transmitter740may be configured as or otherwise support a means for transmitting, to a host system, data retrieved from a physical address identified in the pivot table of the second subset of the mapping based at least in part on reading the second entry of the second subset of the mapping.

In some examples, the data transmitter740may be configured as or otherwise support a means for retrieving, from the non-volatile memory device, the data from the physical address identified using the pivot table of the second entry, where transmitting the data is based at least in part on retrieving the data.

In some examples, the data is retrieved from the physical address without reading a third subset of the mapping.

In some examples, the second entry of the second subset includes a flag that indicates whether the second entry is associated with a third subset of the mapping or is associated with a starting physical address of a set of physical addresses associated with the read command.

In some examples, the global component735may be configured as or otherwise support a means for determining whether the physical addresses of the set of physical addresses are consecutively indexed based at least in part on reading the second entry of the second subset of the mapping, where transmitting the data is based at least in part on determining that the physical addresses are consecutively indexed.

In some examples, the global component735may be configured as or otherwise support a means for identifying a starting physical address of a plurality of physical addresses that are consecutively indexed using the pivot table of the second entry. In some examples, the global component735may be configured as or otherwise support a means for identifying the physical address to access based at least in part on a starting logical block address and a difference between the starting logical block address and the logical block address.

In some examples, the flag component750may be configured as or otherwise support a means for refraining from reading a third entry of a third subset of the mapping based at least in part on a flag indicating that the second entry of the second subset of the mapping is associated with the physical addresses of the non-volatile memory device.

In some examples, the flag component750may be configured as or otherwise support a means for refraining from transferring, from the non-volatile memory device to a volatile memory device, at least a portion of a third subset of the mapping based at least in part on a flag indicating that the second entry of the second subset of the mapping is associated with the physical addresses of the non-volatile memory device.

In some examples, the pivot table includes a plurality of entries, an entry of the plurality of entries represents a plurality of logical block addresses that are consecutively indexed and, to support identifies a starting physical address of a plurality of physical addresses that are consecutively indexed, the plurality of physical addresses corresponding to the plurality of logical block addresses, and where reading the second entry of the second subset of the mapping, the global component735may be configured as or otherwise support a means for reading the entry of the plurality of entries, where transmitting, to the host system, the data is based at least in part on reading the entry.

In some examples, a third entry of the plurality of entries represents the logical block address that is non-consecutively indexed with other logical block addresses and identifies a fourth entry of a third subset of the mapping, the fourth entry of the third subset including the physical address associated with the logical block address.

In some examples, the command receiver725may be configured as or otherwise support a means for receiving a plurality of write commands for a set of physical addresses of a non-volatile memory device. The index component745may be configured as or otherwise support a means for determining whether the set of physical addresses are consecutively indexed based at least on receiving the plurality of write commands. The flag component750may be configured as or otherwise support a means for setting, based at least in part on the set of physical addresses being consecutively indexed, a flag in an entry of a second subset of a mapping that includes a first subset, the second subset, and a third subset, the entry of the second subset including at least a portion of a pivot table associated with the set of physical addresses. The write component755may be configured as or otherwise support a means for writing data to the set of physical addresses based at least in part on setting the flag.

In some examples, the flag that indicates whether the entry is associated with the third subset of the mapping or is associated with a starting physical address of the set of physical addresses associated with the plurality of write commands.

In some examples, the index component745may be configured as or otherwise support a means for setting the entry of the second subset of the mapping to indicate a starting physical address based at least in part on determining that the set of physical addresses are consecutively indexed.

In some examples, the global component735may be configured as or otherwise support a means for identifying that the pivot table is included in the second subset of the mapping based at least in part on receiving the plurality of write commands, where setting the flag is based at least in part on identifying the pivot table.

In some examples, the global component735may be configured as or otherwise support a means for generating the pivot table to be included in the second subset of the mapping based at least in part on receiving the plurality of write commands, where setting the flag is based at least in part on generating the pivot table.

In some examples, the global component735may be configured as or otherwise support a means for replacing the entry of the second subset of the mapping including a pointer with at least the portion of the pivot table, where setting the flag is based at least in part on replacing the entry.

In some examples, the global component735may be configured as or otherwise support a means for storing at least the portion of the pivot table in the entry of the second subset of the mapping based at least in part on receiving the plurality of write commands, where setting the flag is based at least in part on storing at least the portion of the pivot table.

In some examples, the pivot table includes a plurality of entries, a first entry of the plurality of entries represents a plurality of logical block addresses that are consecutively indexed and identifies a starting physical address of a plurality of physical addresses that are consecutively indexed, the plurality of physical addresses corresponding to the plurality of logical block addresses.

FIG.8shows a flowchart illustrating a method800that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The operations of method800may be implemented by a memory system or its components as described herein. For example, the operations of method800may be performed by a memory system as described with reference toFIGS.1through7. In some examples, a memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may perform aspects of the described functions using special-purpose hardware.

At805, a read command may be received. For example, the method may include receiving a read command including a logical block address of a non-volatile memory device. The operations of805may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of805may be performed by a command receiver725as described with reference toFIG.7.

At810, a first entry may be read. For example, the method may include reading, based at least in part on the logical block address, a first entry of a first subset of a mapping that defines a relationship between the logical block address and a physical address. The operations of810may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of810may be performed by a root component730as described with reference toFIG.7.

At815, a second entry may be read. For example, the method may include reading, based at least in part on reading the first entry of the first subset, a second entry of a second subset of the mapping, the second entry including at least a portion of a pivot table associated with physical addresses of the non-volatile memory device. The operations of815may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of815may be performed by a global component735as described with reference toFIG.7.

At820, data may be transmitted. For example, the method may include transmitting, to a host system, data retrieved from a physical address identified in the pivot table of the second subset of the mapping based at least in part on reading the second entry of the second subset of the mapping. The operations of820may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of820may be performed by a data transmitter740as described with reference toFIG.7.

In some examples, an apparatus as described herein may perform a method or methods, such as the method800. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a read command including a logical block address of a non-volatile memory device, reading, based at least in part on the logical block address, a first entry of a first subset of a mapping that defines a relationship between the logical block address and a physical address, reading, based at least in part on reading the first entry of the first subset, a second entry of a second subset of the mapping, the second entry including at least a portion of a pivot table associated with physical addresses of the non-volatile memory device, and transmitting, to a host system, data retrieved from a physical address identified in the pivot table of the second subset of the mapping based at least in part on reading the second entry of the second subset of the mapping.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for retrieving, from the non-volatile memory device, the data from the physical address identified using the pivot table of the second entry, where transmitting the data may be based at least in part on retrieving the data.

In some examples of the method800and the apparatus described herein, the data may be retrieved from the physical address without reading a third subset of the mapping.

In some examples of the method800and the apparatus described herein, the second entry of the second subset includes a flag that indicates whether the second entry may be associated with a third subset of the mapping or may be associated with a starting physical address of a set of physical addresses associated with the read command.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for determining whether the physical addresses of the set of physical addresses may be consecutively indexed based at least in part on reading the second entry of the second subset of the mapping, where transmitting the data may be based at least in part on determining that the physical addresses may be consecutively indexed.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying a starting physical address of a plurality of physical addresses that may be consecutively indexed using the pivot table of the second entry and identifying the physical address to access based at least in part on a starting logical block address and a difference between the starting logical block address and the logical block address.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for refraining from reading a third entry of a third subset of the mapping based at least in part on a flag indicating that the second entry of the second subset of the mapping may be associated with the physical addresses of the non-volatile memory device.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for refraining from transferring, from the non-volatile memory device to a volatile memory device, at least a portion of a third subset of the mapping based at least in part on a flag indicating that the second entry of the second subset of the mapping may be associated with the physical addresses of the non-volatile memory device.

In some examples of the method800and the apparatus described herein, the pivot table includes a plurality of entries, an entry of the plurality of entries represents a plurality of logical block addresses that may be consecutively indexed, and identifies a starting physical address of a plurality of physical addresses that may be consecutively indexed, the plurality of physical addresses corresponding to the plurality of logical block addresses, and where reading the second entry of the second subset of the mapping may include operations, features, circuitry, logic, means, or instructions for reading the entry of the plurality of entries, where transmitting, to the host system, the data may be based at least in part on reading the entry.

In some examples of the method800and the apparatus described herein, a third entry of the plurality of entries represents the logical block address that may be non-consecutively indexed with other logical block addresses and identifies a fourth entry of a third subset of the mapping, the fourth entry of the third subset including the physical address associated with the logical block address.

FIG.9shows a flowchart illustrating a method900that supports integrated pivot table in a logical-to-physical mapping in accordance with examples as disclosed herein. The operations of method900may be implemented by a memory system or its components as described herein. For example, the operations of method900may be performed by a memory system as described with reference toFIGS.1through7. In some examples, a memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may perform aspects of the described functions using special-purpose hardware.

At905, a plurality of commands may be received. For example, the method may include receiving a plurality of write commands for a set of physical addresses of a non-volatile memory device. The operations of905may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of905may be performed by a command receiver725as described with reference toFIG.7.

At910, a determination may be made. For example, the method may include determining whether the set of physical addresses are consecutively indexed based at least on receiving the plurality of write commands. The operations of910may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of910may be performed by an index component745as described with reference toFIG.7.

At915, a flag may be set. For example, the method may include setting, based at least in part on the set of physical addresses being consecutively indexed, a flag in an entry of a second subset of a mapping that includes a first subset, the second subset, and a third subset, the entry of the second subset including at least a portion of a pivot table associated with the set of physical addresses. The operations of915may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of915may be performed by a flag component750as described with reference toFIG.7.

At920, data may be written. For example, the method may include writing data to the set of physical addresses based at least in part on setting the flag. The operations of920may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of920may be performed by a write component755as described with reference toFIG.7.

In some examples, an apparatus as described herein may perform a method or methods, such as the method900. The apparatus may include, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a plurality of write commands for a set of physical addresses of a non-volatile memory device, determining whether the set of physical addresses are consecutively indexed based at least on receiving the plurality of write commands, setting, based at least in part on the set of physical addresses being consecutively indexed, a flag in an entry of a second subset of a mapping that includes a first subset, the second subset, and a third subset, the entry of the second subset including at least a portion of a pivot table associated with the set of physical addresses, and writing data to the set of physical addresses based at least in part on setting the flag.

In some examples of the method900and the apparatus described herein, the flag that indicates whether the entry may be associated with the third subset of the mapping or may be associated with a starting physical address of the set of physical addresses associated with the plurality of write commands.

Some examples of the method900and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for setting the entry of the second subset of the mapping to indicate a starting physical address based at least in part on determining that the set of physical addresses may be consecutively indexed.

Some examples of the method900and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for identifying that the pivot table may be included in the second subset of the mapping based at least in part on receiving the plurality of write commands, where setting the flag may be based at least in part on identifying the pivot table.

Some examples of the method900and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for generating the pivot table to be included in the second subset of the mapping based at least in part on receiving the plurality of write commands, where setting the flag may be based at least in part on generating the pivot table.

Some examples of the method900and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for replacing the entry of the second subset of the mapping including a pointer with at least the portion of the pivot table, where setting the flag may be based at least in part on replacing the entry.

Some examples of the method900and the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for storing at least the portion of the pivot table in the entry of the second subset of the mapping based at least in part on receiving the plurality of write commands, where setting the flag may be based at least in part on storing at least the portion of the pivot table.

In some examples of the method900and the apparatus described herein, the pivot table includes a plurality of entries, a first entry of the plurality of entries represents a plurality of logical block addresses that may be consecutively indexed and identifies a starting physical address of a plurality of physical addresses that may be consecutively indexed, the plurality of physical addresses corresponding to the plurality of logical block addresses.

It should be noted that the methods described above describe possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

The term “coupling” refers to a condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other if the switch is open. If a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

The terms “if,” “when,” “based on,” or “based at least in part on” may be used interchangeably. In some examples, if the terms “if,” “when,” “based on,” or “based at least in part on” are used to describe a conditional action, a conditional process, or connection between portions of a process, the terms may be interchangeable.

The term “in response to” may refer to one condition or action occurring at least partially, if not fully, as a result of a previous condition or action. For example, a first condition or action may be performed and second condition or action may at least partially occur as a result of the previous condition or action occurring (whether directly after or after one or more other intermediate conditions or actions occurring after the first condition or action).

Additionally, the terms “directly in response to” or “in direct response to” may refer to one condition or action occurring as a direct result of a previous condition or action. In some examples, a first condition or action may be performed and second condition or action may occur directly as a result of the previous condition or action occurring independent of whether other conditions or actions occur. In some examples, a first condition or action may be performed and second condition or action may occur directly as a result of the previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action or a limited quantity of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Any condition or action described herein as being performed “based on,” “based at least in part on,” or “in response to” some other step, action, event, or condition may additionally or alternatively (e.g., in an alternative example) be performed “in direct response to” or “directly in response to” such other condition or action unless otherwise specified.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” if a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” if a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to providing an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a hyphen and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over, as one or more instructions or code, a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.