Patent ID: 12188973

DESCRIPTIONS FOR REFERENCE NUMERALS IN THE ACCOMPANYING DRAWINGS

10, power conversion circuit;11, processor;12, fault arc signal processing circuit;13, current signal input circuit;14, crystal oscillator debugging interface circuit;15, communication networking circuit;16, sound alarming circuit;17, key indication circuit;18, alarming trip circuit;19, communication interface circuit;101, voltage sampling circuit;102, first voltage conversion circuit;103, second voltage conversion circuit;104, third voltage conversion circuit;105, fourth voltage conversion circuit;121, voltage signal processing circuit;122, current signal processing circuit;123, square shoulder pulse signal extraction circuit;124, high-frequency pulse signal extraction circuit;1231, current differential amplification circuit;1232, automatic gain amplification circuit;1233, current positive square wave generation circuit;1234, current negative square wave generation circuit;1235, square shoulder pulse generation circuit;1236, first current shaping circuit;1211, voltage differential amplification circuit;1212, voltage shaping circuit;1241, high-pass filter circuit;1242, low-pass filter circuit; and1243, second current shaping circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present disclosure will be described in detail below in combination with the accompanying drawings, however, the present disclosure may be implemented in various different manners limited and covered as follows.

As shown inFIG.1, a preferred embodiment of the present disclosure provides a single phase fault arc detector used to detect a single-phase fault arc, including:a power conversion circuit10connected to the live wire and neutral wire of a mains supply and configured to provide various power voltages and voltage sampling signals;a current signal input circuit13connected to a current transformer and configured to provide current sampling signals;a fault are signal processing circuit12respectively connected to the power conversion circuit10and the current signal input circuit13and configured to process the voltage sampling signals and the current sampling signals anti then output a voltage square wave signal, a voltage sine wave signal, a current sine wave signal, a current square wave signal, a current square shoulder pulse signal, and a current high-frequency pulse signal; anda processor11respectively connected to the power conversion circuit10and the fault arc signal processing circuit12and configured to determine, on the basis of the plurality of current signals and voltage signals output by the fault arc signal processing circuit12and in combination with a preset operation rule, whether there is a single-phase fault arc.

It can be understood that, as shown inFIG.2andFIG.3,FIG.2is a normal current waveform,FIG.3is a fault arc current waveform. It can be seen from the contrast of the waveforms inFIG.2andFIG.3, a fault arc current generally has the following characteristics: 1, there is a “zero current” phenomenon in the fault arc current every half a cycle, that is, there are square shoulder parts in the fault arc current waveform; 2, the rise rate of the fault arc current is generally higher than dial of a normal current, and the current may be abruptly changed every half a cycle, wherein the abrupt change is random, etc. The fault arc detection standard is clearly recorded in the national standard “GB14287.4-2014”, effective detection may be achieved if only at most 9 or fewer fault arcs having half a cycle or 14 or more fault arcs having half a cycle are generated every second during detection, and microarcs of which the durations do not exceed 0.42 ms or the current values do not exceed 5% of a rated current value are not used as arcs for statistics. Therefore, accurate extraction for the square shoulder parts in the fault arc current waveform is of great importance to the detection of fault arcs.

It can be understood that, according to the single-phase fault arc detector in the present embodiment, the fault are signal processing circuit12processes the voltage sampling signals and the current sampling signals to obtain the voltage square wave signal, the voltage sine wave signal the current sine wave signal, the current square wave signal, the current square shoulder pulse signal, and the current high-frequency pulse signal, and thus, the processor11may accurately determine, on the basis of the plurality of obtained current signals and voltage signals and in combination with a preset operation rule, whether there is a single-phase fault arc in a power utilization line. The current square shoulder pulse signal corresponds to square shoulder parts in the fault arc current waveform, correlated characteristics of the square shoulder parts may be accurately recognized by accurately extracting the current square shoulder pulse signal from the current sampling signals; then, characteristics such as the number and durations of the square shoulder pans as well as a current value may be comprehensively recognized on the basis of the current square shoulder pulse signal and the current high-frequency pulse signal; and when it is recognized that the number of the square shoulder parts exceeds14, the duration of each square shoulder exceeds 420 us, and the current value exceeds a rated current value by 5%, it is determined that there is the single-phase fault arc in the power utilization line, or else, it is determined that there is no single-phase fault arc in the power utilization line. At most time, the voltage square wave signal, the current square wave signal, the voltage sine wave signal and the current sine wave signal are used as triggering signals, and when it is recognized by the processor11that these signals are abnormal, a fault arc detection function is started, that is, the current square shoulder pulse signal and the current high-frequency pulse signal are started to be sampled, and thus, the accuracy of the detector is improved to reduce the false alarm rate while the flexibility of the detector is guaranteed. It can be understood that a specific determination rule is carried in the processor in advance by a program, and the processor may automatically determine whether there is the single-phase fault arc by only acquiring the above-mentioned current signals and voltage signals.

It can be understood that, as shown inFIG.4, the power conversion circuit10includes a fuse F1, a voltage sampling circuit101, a first voltage conversion circuit102, a second voltage conversion circuit103, a third voltage conversion circuit104, and a fourth voltage conversion circuit105; the voltage sampling circuit101and the first voltage conversion circuit102are respectively connected to the live w ire and neutral wire of the mains supply; the fuse F1is located between the first voltage conversion circuit102and the live wire of the mains supply and is configured to play a role in overload protection; the voltage sampling circuit101is configured to sample a voltage signal of the mains supply; the first voltage conversion circuit102is configured to convert a 220 V alternating current voltage of the mains supply into a +12 V direct current voltage; the second voltage conversion circuit103is connected to the output end of the first voltage conversion circuit102and is configured to convert the +12 V direct current voltage into a +5 V direct current voltage; the third voltage conversion circuit104is connected to the output end of the second voltage conversion circuit103and is configured to convert the +5 V direct current voltage into a ±5.5 V direct current voltage; and the fourth voltage conversion circuit105is connected to the output end of the second voltage conversion circuit103and is configured to convert the +5 V direct current voltage into a +3.3 V direct current voltage. It can be understood that the power conversion circuit10may be provided with more voltage conversion circuits as actually required to provide different power voltages.

Specifically, the voltage sampling circuit101includes a resistor R1, a resistor R2, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a resistor R9; the first end of the resistor R1is connected to the live wire of the mains supply by the fuse F1, and the second end of the resistor R1is connected to the first end of the resistor R4; the second end of the resistor R4is connected to the first end of the resistor R5; the first end of the resistor R3is connected to the neutral wire of the mains supply, and the second end of the resistor R3is connected to the first end of the resistor R6; the second end of the resistor R6is connected to the first end of the resistor R7; the second end of the resistor R7is respectively connected to the first end of the resistor R8and the fault arc signal processing circuit12; the second end of the resistor R8and the first end of the resistor R9are grounded; and the second end of the resistor R9and the second end of the resistor R5are both connected to the fault arc signal processing circuit12. The voltage sampling circuit101may provide a voltage sampling signal to the fault arc signal processing circuit12in a resistive subdivision sampling manner, thereby facilitating subsequent voltage signal analysis.

The first voltage conversion circuit102includes a capacitor C3, a first voltage conversion module DY2, a filter inductor T1, a capacitor C7, a capacitor C12, and a capacitor C16; the first end of the capacitor C3is connected to the live wire of the mains supply by the fuse F1, and the second thereof is connected to the neutral wire of the mains supply; two input ends of the first voltage conversion module DY2are respectively connected to the live wire and neutral wire of the mains supply, and two output ends of the first voltage conversion module DY2are respectively connected to the input end of the filter inductor T1; the first output end of the filter inductor T1is respectively connected to the first end of the capacitor C7and the second voltage conversion circuit103, and the second output end thereof is grounded; the second end of the capacitor C12is connected to the second end of the resistor R5; the second end of the capacitor C7, the first end of the capacitor C16and the first end of the capacitor C12are all grounded; and the second end of the capacitor C16is connected to the second end of the resistor R7. The first voltage conversion module DY2is an EMC power conversion module for converting an alternating current to a direct current; and by using the first voltage conversion module DY2, a 220 V alternating current power voltage of the mains supply is converted into a 12 V direct current power voltage.

The second voltage conversion circuit103includes a polar capacitor C8, a second voltage conversion module TM1, a capacitor C4, and a polar capacitor C5; the anode end of the polar capacitor C8and fie input end of the second voltage conversion module TM1are both connected to the first output end of the filter inductor T1; the output end of the second voltage conversion module TM1is respectively connected to the first end of the capacitor C4, the anode end of the polar inductor C5, the fault arc signal processing circuit12, and the third voltage conversion circuit104; and the second end of the capacitor C4, the cathode end of the polar capacitor C5and the cathode end of the polar capacitor C8are all grounded. By using the second voltage conversion module TM1, a 12 V direct current voltage may be converted into a 5 V direct current voltage.

The third voltage conversion circuit104includes a third voltage conversion module DY1, a capacitor C1, a capacitor C2, and a polar capacitor C9; a first pin of the third voltage conversion module DY1is connected to the output end of the second voltage conversion module TM1, a second pin thereof is grounded, a fifth pin thereof is used as the output end of a −5.5 V voltage, a sixth pin thereof is grounded, and a seventh pin thereof is respectively connected to the first end of the capacitor C1and the anode end of the polar capacitor C2and is used as the output end of a +5.5 V voltage; the second end of the capacitor C1, the cathode end of the polar capacitor C2, the first end of the capacitor C10and the anode end of the polar capacitor C9are all grounded; and the second end of the capacitor C10and the cathode end of the polar capacitor C9are both connected to the fifth pin of the third voltage conversion module DY1.

The fourth voltage conversion circuit105includes a capacitor C13, a polar capacity C17, a fourth voltage conversion module U1, a capacitor C14, and a polar capacitor C15; the first end of the capacitor C13, the anode end of the polar capacitor C17, the anode end of the polar capacity C7and the input end of the fourth voltage conversion module U1are all connected to the output end of the second voltage conversion module TM1; the output end of the fourth voltage conversion module U1is respectively connected to the first end of the capacitor C14and the anode end of the polar capacitor C15; and the second end of the capacitor C13, the cathode end of the polar capacitor C17, the second end of the capacitor C14and the cathode end of the polar capacitor C15are all grounded. By using the fourth voltage conversion module U1, a 5 V direct current voltage may be converted into a 3.3 V voltage by which the processor11may be powered.

It can be understood that, as shown inFIG.1andFIG.5, the fault arc signal processing circuit12includes a voltage signal processing circuit121and a current signal processing circuit122; the voltage signal processing circuit121is respectively connected to the power conversion circuit10and the processor11and is configured to respectively convert the voltage sampling signals into the voltage sine wave signal and the voltage square wave signal and then output the voltage sine wave signal and the voltage square wave signal to the processor11; and the current signal processing circuit122is respectively connected to the current signal input circuit13and the processor11and is configured to respectively convert the current sampling signals into the current sine wave signal, the current square wave signal, the current square shoulder pulse signal and the current high-frequency pulse signal and then output the current sine wave signal, the current square wave signal, the current square shoulder pulse signal and the current high-frequency pulse signal to the processor11.

Specifically, the voltage signal processing circuit121includes a voltage differential amplification circuit1211and a voltage shaping circuit1212; the voltage differential amplification circuit1211is respectively connected to the power conversion circuit10, the voltage shaping circuit1212and the processor11and is configured to perform primary amplification processing on the voltage sampling signals and respectively output the voltage sine wave signal subjected to the amplification process to the voltage shaping circuit1212and the processor11; and the voltage shaping circuit1212is respectively connected to the voltage differential amplification circuit1211and the processor11and is configured to sequentially perform secondary amplification processing and shaping processing on the voltage sine wave signal subjected to the primary amplification processing to convert the voltage sine wave signal into a 3.3 V voltage square wave signal and then output the 3.3 V voltage square wave signal to the processor11. The processor11may recognize the correlated characteristics of the fault arc voltage signal according to the voltage sine wave signal and the voltage square wave signal, for example, when the single-phase fault arc occurs, a line voltage sags, the waveform is approximately rectangular, and therefore, the processor11may preliminarily determine, according to the voltage sine wave signal and the voltage square wave signal, whether there is the single-phase fault arc.

Specifically, the voltage differential amplification circuit1211includes a resistor R14, a resistor R16, a resistor R13, a capacitor C20, a resistor R22, a differential amplifier U1D, a resistor R19, a resistor R20, and a capacitor C19; the first ends of the resistor R14and the resistor R16are connected to the power conversion circuit10so that the voltage sampling signals are accessed, that is, they are connected to the output end of the voltage sampling circuit101; the first end of the capacitor C20is connected to the power conversion circuit10so that a 5 V power voltage is accessed; the second end of the resistor R14is respectively connected to the first end of the resistor R13and the reversed-phase input end of the differential amplifier U1D; the second end of the capacitor C20is connected to the first end of the resistor R22; the second end of tire resistor R16is respectively connected to the second end of the resistor R22and the forward-phase input end of the differential amplifier U1D; the output end of the differential amplifier U1D is respectively connected to the second end of the resistor R13, the first end of the capacitor C19, and the voltage shaping circuit1212; the second end of the capacitor C19is respectively connected to the second end of the resistor R19, the first end of the resistor R20, and the processor11; the first end of the resistor R19is grounded; and the second end of the resistor R20is connected to the power conversion circuit10so that a 3.3 V power voltage is accessed.

The voltage shaping circuit1212includes a resistor R18, a differential amplifier U1C, a resistor R17, a capacitor C18, a NAND gate U3A, and a resistor R12; the first end of the resistor R18is connected to the output end of the voltage differential amplification circuit1211, i.e. the output end of the differential amplifier U1D, and the second end of the resistor R18is connected to the forward-phase input end of the differential amplifier U1C; the reverse-phase input end of the differential amplifier U1C is grounded, and the output end thereof is connected to the first end of the resistor R17; the second end of the resistor R17is respectively connected to the first end of the capacitor C18and two input ends of the NAND gate U3A; the second end of the capacitor C18is grounded; the output end of the NAND gate U3A is respectively connected to the first end of the resistor R12and the processor11; and the second end of the resistor R12is connected to the power conversion circuit10. The secondary amplification is performed on the voltage sine wave signal by the differential amplifier U1C, and then, the voltage sine wave signal subjected to the secondary amplification is shaped by using the NAND gate U3A so as to be converted into a 3.3 V voltage square wave signal to be conveniently recognized and processed by the processor11.

The current signal processing circuit122includes a square shoulder pulse signal extraction circuit123and a high-frequency pulse signal extraction circuit124; the square shoulder pulse signal extraction circuit123is respectively connected to the current signal input circuit13and the processor11and is configured to respectively convert the current sampling signals into the current sine wave signal, the current square wave signal and the current square shoulder pulse signal and then output the current sine wave signal, the current square wave signal and the current square shoulder pulse signal to the processor11; and the high-frequency pulse signal extraction circuit124is respectively connected to the square shoulder pulse signal extraction circuit123and the processor11and is configured to convert the current sine wave signal into tire current high-frequency pulse signal and then output the current high-frequency pulse signal to the processor11.

Specifically, the square shoulder pulse signal extraction circuit123includes a current differential amplification circuit1231, an automatic gain amplification circuit1232, a current positive square wave generation circuit1233, a current negative square wave generation circuit1234, a square shoulder pulse generation circuit1235, and a first current shaping circuit1236; the current differential amplification circuit1231is respectively connected to the current signal input circuit13, the processor11and the automatic gain amplification circuit1232and is configured to perform primary amplification processing on the current sampling signals and respectively output the current sine wave signal subjected to amplification processing to the processor11and the automatic gain amplification circuit1232; the automatic gain amplification circuit1232is respectively connected to the processor11, the current positive square wave generation circuit1233and the current negative square wave generation circuit1234and is configured to perform, under the control of the processor11, secondary amplification processing on the current sine wave signal subjected to the primary amplification processing and output the current sine wave signal subjected to the secondary amplification processing, the current positive square wave generation circuit1233is configured to convert the current sine wave signal subjected to the secondary amplification processing into a 5.5 V current positive square wave signal; the current negative square wave generation circuit1234is configured to convert the current sine wave signal subjected to the secondary amplification processing into a current negative square wave signal; the square shoulder pulse generation circuit1235is respectively connected to the current positive square wave generation circuit1233, the current negative square wave generation circuit1234and the processor11and is configured to superpose the current positive square wave signal and the current negative square wave signal, extract the current square shoulder pulse signal and then output the current square shoulder pulse signal to the processor11, and the first current shaping circuit1236is connected to the current positive square wave generation circuit1233and is configured to convert the 5.5 V current positive square wave signal output by the current positive square wave generation circuit1233into a 3.3 V current positive square wave signal and then output the 3.3 V current positive square wave signal to the processor11.

The current differential amplification circuit1231includes a resistor R30, a resistor R41, a resistor R42, a differential amplifier U1D, a resistor R31, a resistor R36, a resistor R37, a capacitor C22, and a resistor R44; the first end of the resistor R41and the first end of the resistor R30are both connected to the current signal input circuit13, and the second end of the resistor R30is respectively connected to the first end of the resistor R31and the reversed-phase input end of the differential amplifier U1D; the second end of the resistor R41and the second end of the resistor R42are both connected to the in-phase input end of the differential amplifier U1D; the first end of the resistor R42is grounded; the output end of the differential amplifier U1D is respectively connected to the second end of the resistor R31, the first end of the capacitor C22, the second end of the resistor R36, and the high-frequency pulse signal extraction circuit124; the first end of the resistor R36is connected to the automatic gain amplification circuit1232; the second end of the capacitor C22is respectively connected to the second end of the resistor R37, the first end of the resistor R44, and the processor11; the first end of the resistor R37is connected to the power conversion circuit10so that a 3.3 V power voltage is accessed; and the second end of the resistor R44is grounded.

The automatic gam amplification circuit1232includes a resistor R28, a resistor R23, a resistor29, an in-phase amplifier U1A, a resistor R43, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R38, a resistor R39, a resistor R40, a resistor R45, a resistor R46, a resistor R47, a triode Q1, a triode Q2, and a triode Q3; the first end of the resistor R28is grounded, and the second end of the resistor R28and the first end of the resistor R23are connected to the reversed-phase input end of the in-phase amplifier U1A; the first end of the resistor R29is connected to the forward-phase input end of the in-phase amplifier U1A; the output end of the in-phase amplifier U1A is respectively connected to the second end of the resistor R23and the first end of the resistor R43; and the second end of the resistor R43is respectively connected to the current positive square wave generation circuit1233and the current negative square wave generation circuit1234. The second end of the resistor R29is respectively connected to the first end of the resistor R36, the first end of the resistor R32, the first end of the resistor R33, the first end of the resistor R34, and the first end of the resistor R35; the second end of the resistor R33is connected to the collector of the triode Q1, and the base of the triode Q1is respectively connected to the second end of the resistor R38and the first end of the resistor R45; the first end of the resistor R38, the first end of the resistor R39and the first end of the resistor R40are all connected to the processor11; the collector of the triode Q2is connected to the second end of the resistor R34, and the base thereof is respectively connected to the second end of the resistor R39and the first end of the resistor R46; the collector of the triode Q3is connected to the first end of the resistor R35, and the base thereof is respectively connected to the second end of the resistor R40and the first end of the resistor R47; and the second end of the resistor R32, the emitter of the triode Q1, the emitter of the triode Q2, the emitter of the triode Q3, the second end of the resistor R45, the second end of the resistor R46and the second end of the resistor R47are all grounded. The processor11controls, by controlling electric levels applied to the resistor R38, the resistor R39and the resistor R40, whether the triode Q1, the triode Q2and the triode Q3are turned on, thereby controlling the number of the resistors connected to the circuit and a connecting structure among the plurality of resistors to change the attenuation intensity of an input signal of the in-phase amplifier U1A and then achieve control on 8-level attenuation.

The current positive square wave generation circuit1233includes a capacitor C25, a resistor R48, a resistor R59, a positive square wave generator U2B, a resistor R55, and a resistor R56; the first end of the capacitor C25and the forward-phase input end of the positive square wave generator U2B are both connected to the automatic gain amplification circuit1232, i.e. The second end of the resistor R43, so that the current sine wave signal subjected to the amplification processing is accessed; the second end of the resistor R48is connected to the power conversion circuit10so that a −5.5 V power voltage is accessed, and the first end of the resistor R48is respectively connected to the first end of the resistor R59and the reversed-phase input end of the positive square wave generator U2B, the output end of the positive square wave generator U2B is respectively connected to the first end of the resistor R55, the first end of the resistor R56, and the first current shaping circuit1236; the second end of the resistor R59, the second end of the capacitor C25and the second end of the resistor R55are all grounded; and the second end of the resistor R56is connected to the square shoulder pulse generation circuit1235. A fault arc current positive square wave signal generated by the current positive square wave generation circuit1233is shown asFIG.6.

The current negative square wave generation circuit1234includes a resistor R49, a resistor R60, a negative square wave generator U2C, a capacitor C23, a capacitor C27, and a resistor R58; the reversed-phase input end of the negative square wave generator U2C is connected to the automatic gain amplification circuit1232, i.e. the second end of the resistor R43, and the forward-phase input end thereof is respectively connected to the first end of the resistor R49and the first end of the resistor R60; the second end of the resistor R49, the first end of the capacitor C23and a fourth pin of the negative square wave generator U2C are all connected to the power conversion circuit10so that a +5.5 V power voltage is accessed; an eleventh pin of the negative square wave generator U2C and the first end of the capacitor C27are connected to the power conversion circuit10so that a −5.5 V power voltage is accessed; the output end of the negative square wave generator U2C is respectively connected to the first end of the resistor R58and the first current shaping circuit1236; and the second end of the resistor R58, the second end of the capacitor C23, the second end of the capacitor C27and the second end of the resistor R60are all grounded. By using the current negative square wave generation circuit1234. A fault arc current negative square wave signal generated by the current negative square wave generation circuit1234is shown asFIG.7.

The square shoulder pulse generation circuit1235includes a resistor R53, a capacitor C24, a capacitor C26, a NAND gate U3D, and a resistor R50; the first end of the resistor R53is connected to the output end of the negative square wave generator U2C, and the second end of the resistor R53is respectively connected to the first end of the capacitor C24and the first input end of the NAND gate U3D; the second input end of the NAND gate U3D is respectively connected to the first end of the capacitor C26and the output end of the current positive square wave generation circuit (i.e. the second end of the resistor R56); the output end of the NAND gate U3D is respectively connected to the processor (11) and the second end of the resistor R50; the first end of the resistor R50is connected to the power conversion circuit10so that a 3.3 V power voltage is accessed; and the second end of the capacitor C24and the second end of the capacitor C26are grounded. As shown inFIG.8andFIG.9, by using the NAND gate U3D, the fault arc current positive square wave signal and the fault arc current negative square wave signal are superposed, and a square shoulder pulse reverse waveform, i.e. the current square shoulder pulse signal, is extracted.FIG.8is a schematic view showing that the fault arc current positive square wave signal and the fault arc current negative square wave signal are superposed by the NAND gate U3D; andFIG.9is a schematic view showing a waveform of the square shoulder pulse reverse signal synthesized by the NAND gate U3D.

The first current shaping circuit1236includes a resistor R24, a capacitor C21, a NAND gate U3B, and a resistor R21; the first end of the first resistor R24is connected to the output end of the positive square wave generator U2B, and the second end of the first resistor R24is connected to connected to the first end of the capacitor C21and the input end of the NAND gate U3B; the second end of the capacitor C21is grounded; the output end of the NAND gate U3B is respectively connected to the processor11and the second end of the resistor R21; and the first end of the resistor R21is connected to the power conversion circuit10so that a 3.3 V power voltage is accessed. By using the NAND gate U3B, a 5.5 V current positive square wave signal is converted into a 3.3 V current positive square wave signal, and then, the 3.3 V current positive square wave signal is output to the processor11so as to be conveniently recognized and processed by the processor11. It can be understood that a current square wave signal output by the first current shaping circuit1236is a current positive square wave signal, i.e. a half-wave signal.

The high-frequency pulse signal extraction circuit124includes a high-pass filter circuit1241, a low-pass filter circuit1242and a second current shaping circuit1243; the high-pass filter circuit1241is connected to the current differential amplification circuit1231; the low-pass filter circuit1242is respectively connected to the high-pass filter circuit1241and the second current shaping circuit1243; the high-pass filter circuit1241is configured to filter a low-frequency interference signal in the current sine wave signal subjected to the amplification processing; the low-pass filter circuit1242is configured to filter a high-frequency interference signal in the current sine wave signal; a medium-frequency current sine wave signal may only enter the second current shaping circuit1243after being subjected to two-time band-pass filtering; and the second current shaping circuit1243is configured to shape the current sine wave signal into a 3.3 V current square wave signal and then output the 3.3 V current square wave signal to the processor11. It can be understood that the current square wave signal output by the second current shaping circuit1243is a complete square wave signal. In a preferred embodiment of the present disclosure, the allowable critical signal frequency of the high-pass filter circuit1241is 700 kHz, that is, signals of which the frequencies exceed 700 kHz are only allowed to pass; the allowable critical signal frequency of the low-pass filter circuit1242is 900 kHz, that is, signals of which the frequencies are smaller than 900 kHz are only allowed to pass; and the frequency of the current sine wave signal is about 800 kHz.

Specifically, the high-pass filter circuit1241includes a capacitor C29, a resistor R77, a capacitor C30, a resistor R64, an operational amplifier U2A, a resistor R79, and a resistor R68; the first end of the capacitor129is connected to the output end of the current differential amplification circuit1231, i.e. the output end of the differential amplifier U1D, and the second end of the capacitor C29is respectively connected to the first end of the capacitor C30and the first end of the resistor R77; the second end of the capacitor C30is respectively connected to the first end of the resistor R79and the forward-phase input end of the operational amplifier U2A; the second end of the resistor R79and the first end of the resistor R64arc grounded; the reversed-phase input end of the operational amplifier U2A is respectively connected to the second end of the resistor R64and the first end of the resistor R68; and the output end of the operational amplifier U2A is respectively connected to the second end of the resistor R68, the second end of the resistor R77, and the low-pass filter circuit1242.

The low-pass filter circuit1242includes a resistor R71, a capacitor C33, a resistor R72, a capacitor C31, an operational amplifier U2B, a resistor R63, and a resistor R65; the first end of the resistor R71is connected to the output end of the high-pass filter circuit1241, i.e. the output end of the operational amplifier U2A, and the second end of the resistor R71is respectively connected to the first end of the capacitor C33and the first end of the resistor R72; the second end of the resistor R72is respectively connected to the first end of the capacitor C31and the forward-phase input end of the operational amplifier U2B; the reversed-phase input end of the operational amplifier U2B is respectively connected to the second end of the resistor R63and the first end of the resistor R65; the first end of the resistor R63and the second end of the capacitor C31are grounded; and the output end of the operational amplifier U2B is respectively connected to the second end of the capacitor C33, the second end of the resistor R65, and the second current shaping circuit1243.

The second current shaping circuit1243includes a resistor R69, a capacitor C32, a NAND gate U3C, and a resistor R66; the first end of the resistor R69is connected to the output end of the low-pass filter circuit1242, i.e. the output end of the operational amplifier U2B, and the second end of the resistor R69is respectively connected to the first end of the capacitor C32and the input end of the NAND gate U3C; the second end of the capacitor C32is grounded; the output end of the NAND gate U3C is respectively connected to the second end of the resistor R66and the processor11; and the first end of the resistor R66is connected to the power conversion circuit10so that a 3.3 V power voltage may be accessed. By using the NAND gate U3C, a current sine wave signal subjected to second-level band-pass filtering is shaped to form a 3.3 V complete current square wave signal to be conveniently recognized and processed by the processor11. In addition, a circuit pin view of the processor11is shown asFIG.10, and there are 48 pins in total.

It can be understood that, as a preference, as shown inFIG.1andFIG.11, the single-phase fault arc detector further includes a sound alarming circuit16connected to the processor11and configured to give a sound alarming caution. When determining that there is a single-phase fault arc in a power utilization line, the processor11controls the sound alarming circuit16to give an alarming caution. Specifically, the sound alarming circuit16includes a buzzer BE1, a diode D2, a capacitor C28, a resistor R73, a resistor R76, and a triode Q5; the first end of the resistor R73is connected to the processor11so that a control signal is accessed, and the second end of the resistor R73is respectively connected to the first end of the resistor R76and the base of the triode Q5; the second end of the resistor R76and the emitter of the triode Q5are grounded; the collector of the triode Q5is respectively connected to the buzzer BE1, the anode end of the diode D2, and the second end of the capacitor C28; and the buzzer BE1, the cathode end of the diode D2and the first end of the capacitor C28are all connected to the power conversion circuit10so that a +12 V power voltage is accessed. The overall circuit is relatively simple in structure, adopts relatively common electronic elements in the market and lower in manufacturing cost.

It can be understood that, as a preference, as shown inFIG.1andFIG.12, the single-phase fault arc detector further includes a crystal oscillator debugging interface circuit14connected to the processor11. Specifically, the crystal oscillator debugging interface circuit14includes an interface PZ1, a resistor R2, a capacitor C6, a capacitor C11, and a crystal oscillator Y1; the interface PZ1, the first end of the resistor R2, the first end of the capacitor C6, two ends of the crystal oscillator Y1and the second end of the capacitor C11are all connected to the processor11, and the second end of the resistor R2, the second end of the capacitor C6and the first end of the capacitor C11are all grounded. By connecting the PZ1to external crystal oscillator debugging equipment, the working parameter of the crystal oscillator Y1may be debugged.

It can be understood that, as a preference, as shown inFIG.1andFIG.13, the single-phase fault arc defector further includes a communication networking circuit15connected to the processor11. Specifically, the communication networking circuit15includes a Wifi interface module and a RS485 communication circuit respectively connected to the processor11; the Wifi interface module is configured to perform communication on a Wifi signal; and the RS485 communication circuit is configured to perform communication on a 485 signal. The RS485 communication circuit includes a resistor R61, a resistor R54, a resistor R62, and a RS485 communication module U4; the first ends of the resistor R61, the resistor R54and the resistor R62are all connected to the power conversion circuit10so that a 5 V power voltage is accessed; the second end of the resistor R61, the second end of the resistor R54, the second end of the resistor R62and the output end of the RS485 communication module U4are all connected to the processor11; and the input end of the RS485 communication module U4is connected to external communication equipment by an interface.

It can be understood that, as a preference, as shown inFIG.1andFIG.14, the single-phase fault arc detector further includes a key indication circuit17connected to the processor11. Specifically, the key indication circuit17includes a resistor R67, a resistor R70, a resistor R74, a resistor R75, a resistor R78, a key switch S1, a key switch S2, a light emitting diode D3, a light emitting diode D4, and a light emitting diode D5; the first end of the resistor R67and the first end of the resistor R70are both connected to the power conversion circuit10so that a 3.3 V power voltage is accessed; the second end of the resistor R67is respectively connected to the processor11and the first end of the key switch S1; the second end of the resistor R70is respectively connected to the processor11and the first end of the key switch S2; the first end of the resistor R74, the first end of the resistor R75and the first end of the resistor R78are all connected to the processor11; the second end of the resistor R74is connected to the first end of the light emitting diode D3; the second end of the resistor R75is connected to the first end of the light emitting diode D4; the second end of the resistor R78is connected to the first end of the light entitling diode D5; and the second end of the light emitting diode D3, the second end of the light emitting diode D4, the second end of the light emitting diode D5, the second end of the key switch S1and the second end of the key switch S2are all grounded.

It can be understood that, as a preference, as shown inFIG.1andFIG.15, the single-phase fault arc detector further includes an alarming trip circuit18connected to the processor11and configured to control the turn off of a safety switch in the power utilization line under the control of the processor11so as to play a role in safely protection. Specifically, the alarming trip circuit18includes a resistor R57, a resistor R51, a resistor R52, a triode Q4, a diode D1, and a relay K1; the first end of the resistor R57is connected to the processor11, and the second end of the resistor R57is connected to the power conversion circuit10so that a 3.3 V power voltage is accessed; the second end of the resistor R51is connected to the processor11; the first end of the resistor R51and the first end of the resistor R52are both connected to the base of the triode Q4; the second end of the resistor R52and the emitter of the triode Q4are both grounded; the emitter of the triode Q4is respectively connected to the anode end of the diode D1and the relay K1; the relay K1and the cathode end of the diode D1are both connected to the power conversion circuit10so that a +5 V power voltage is accessed; and a normally-closed contact of the relay K1is connected to the safety switch in the power utilization line. The processor11sends a control signal to control the triode Q4to be turned on, thereby controlling the relay K1to be electrified; and then, the relay K1acts, thereby controlling the safety switch to be turned off.

It can be understood that, as a preference, as shown inFIG.1andFIG.16, the single-phase fault arc detector further includes a communication interface circuit19connected to the communication networking circuit15. The communication interface circuit19includes a resistor R10, a resistor R15, and a resistor R11; the first end of the resistor R10is grounded; the second end of the resistor R10and the first end of the resistor R11are connected to the communication networking circuit15; the second end of the resistor R11and the first end of the resistor R15are both connected to the communication networking circuit15; and the second end of the resistor R15is connected to the power conversion circuit10so that a 5 V power voltage is accessed.

As shown inFIG.17, the current signal input circuit13includes a resistor R25, a resistor R26, a resistor R27, and a filter inductor T2; two ends of the resistor R25, two ends of the resistor R26, two ends of the resistor R27and two input ends of the filter inductor T2are all connected to two ends of the a transformer; and two output ends of the filter inductor T2are both connected to the fault arc signal processing circuit12and are specifically connected to the first end of the resistor R30and the first end of the resistor R41in the current differential amplification circuit1231. By disposing the filter inductor T2, a common-mode filtering effect may be achieved.

The above descriptions are not intended to limit the present disclosure, but merely as preferred embodiments thereof. Any alterations and variations of the present disclosure may be made by the skilled in the art. Any modifications, equivalent replacements, improvements, etc. made with the spirit and principle of the present disclosure should fall within the protection scope of the present disclosure.