Patent ID: 12218044

DETAILED DESCRIPTION

(Descriptions of Form, Basic Term, and Usage in Present Application)

In the present application, the description of the embodiment will be divided into a plurality of sections or the like as required for convenience, but unless expressly stated otherwise, these are not independent of each other, and each part of a single example, one of which is a partial detail or a part or all of the other, whether before or after the description, or the like, is modified example or the like. In principle, descriptions of similar parts are omitted. Also, each component in an embodiment is not essential, unless expressly stated otherwise, theoretically limited to that number, and obviously otherwise from the context.

Similarly, in the description of the embodiment and the like, “X consisting of A” or the like with respect to the material, composition, and the like does not exclude elements other than A, except when it is clearly indicated that this is not the case and when it is obvious from the context that this is not the case. For example, regarding a component, it means “X including A as a main component” or the like. For example, the term “silicon member” or the like is not limited to pure silicon, and it is needless to say that it also includes a member containing a SiGe (silicon-germanium) alloy, a multi-element alloy containing silicon as its main component, other additives, or the like. In addition, the term gold plating, Cu layer, nickel plating, or the like includes not only pure components, but also members containing gold, Cu, nickel, or the like as main components, except when it is clearly stated that this is not the case.

In addition, reference to a specific numerical value or quantity may be greater than or less than that specific numerical value, unless expressly stated otherwise, theoretically limited to that number, and obviously not so from the context.

In the drawings of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and the description will not be repeated in principle.

In addition, in the attached drawings, hatching and the like may be omitted even in a cross-section when it becomes complicated or when it is clearly distinguished from a gap. In this connection, even if the hole is closed in plan, the outline of the background may be omitted when it is obvious from the description or the like. In addition, hatching or dot patterns may be added to indicate that the region is not a void even if it is not a cross-section or to indicate the boundary of the area.

<Electronic Device>

First, with reference toFIGS.1and2, an example of usage of a semiconductor device of the present embodiment described below will be explained.FIG.1is an explanatory view showing a configuration example of an electronic device including a semiconductor device according to the present embodiment. Further,FIG.2is an explanatory view showing a configuration example of a circuit of the electronic device shown inFIG.1. Incidentally, inFIG.1, in order to explicitly indicate that semiconductor device PKG1and semiconductor device PKG2are electrically connected, schematically showing the signal transmission path SGP shown inFIG.2by a thick line.

The electronic device (electronics) EDV1shown inFIG.1has a wiring substrate (motherboard, mounting substrate) MB1and semiconductor device PKG1and semiconductor device PKG2mounted on the wiring substrate MB1. Semiconductor device PKG1and semiconductor device PKG2, via the signal transmission path SGP formed in the wire substrate MB1, are connected to each other, and electrically. The signal transmitted through the signal transmission path SGP includes a signal SGT output from semiconductor device PKG1and a signal SGR input to semiconductor device PKG1. Further, the signal transmission path SGP includes a signal transmission path SGPT signal SGT is transmitted, and a signal transmission path SGPR signal SGR is transmitted.

In the exemplary embodiment shown inFIG.1, the signal SGT is output from semiconductor device PKG1, and is input to semiconductor device PKG2. The signal SGR is outputted from semiconductor device PKG2, and the signal SGR is inputted to semiconductor device PKG1. However, the output destination of the signal SGT and the output source of the signal SGR is not limited to the example shown inFIG.1, there are various modified example. Since semiconductor device PKG1and semiconductor device PKG2shown inFIG.1have the same structures, semiconductor device PKG1will be described below as a typical example.

As shown inFIG.2, the electronic device EDV1has a plurality of signal transmission paths SGP. Signal transmission path SGP, for example, a signal is transmitted at a transmission rate above 15 Gbps (Gigabit per second), a high-speed transmission path (high-speed signal transmission path). Incidentally, when realizing the transmission rate of 15 Gbps by one signal transmission path, for example, the frequency of the electric signal flowing through the signal transmission path SGP is required to be 30 GHz (gigahertz) or more. Further, in the present embodiment, as an example of a signal transmission path SGP is a high-speed transmission path, different signals are transmitted to each of the plurality of signal transmission path SGP, so-called, will be described taking a transmission path of the single-ended structure. However, the technique described below transmits one signal via a pair of signal transmission paths constituting the differential pair, it can also be applied to the transmission path of the differential system.

As shown inFIG.2, the semiconductor chip semiconductor device PKG1has (semiconductor component, electronic component) CHP1includes a plurality of electrodes (electrode terminals). A plurality of electrodes semiconductor chip CHP1has a signal SOT is an output signal (transmission signal) (seeFIG.1) includes a signal electrode to be transmitted (signal electrode terminal) Tx. Further, a plurality of electrodes semiconductor chip CHP1has includes a signal electrode (signal electrode terminal) Rx signal SGR (refer toFIG.1) is an input signal (received signal) is transmitted. In the following, as a generic name of the signal electrode Tx or the signal electrode Rx, may be described as a signal electrode Sx.

InFIG.2, among the plurality of signal transmission path SGP semiconductor device PKG1is provided, typically shows two output signal transmission path SGPT and two input signal transmission path SGPR. However, the number of signaling paths SGPs included in semiconductor device PKG1is larger than the number shown inFIG.2.

Further, a plurality of electrodes having the semiconductor chip CHP1includes an electrode reference potential (first potential) VSS is supplied (reference potential electrode, the first potential electrode) Vs, an electrode power supply potential (second potential) VDD is supplied (power supply potential electrode, the second potential electrode) Vd, a. The electrode Vs constitutes a part of the reference potential supply path VSP. Electrode Vd constitutes a portion of the power supply potential supply path VDP. The semiconductor chip CHP1(specifically, the circuit provided by the semiconductor chip CHP1), the power supply potential VDD is supplied via the electrode Vd. Further, the semiconductor chip CHP1(specifically, the circuit provided by the semiconductor chip CHP1), the reference potential VSS is supplied via the electrode Vs. At least a portion of the plurality of circuits semiconductor chip CHP1is provided is driven by a driving voltage generated by the potential difference between the power supply potential VDD and the reference potential VSS. The reference potential VSS is, for example, a ground potential, the power supply potential VDD is higher than the reference potential VSS.

<Semiconductor Device>

FIG.3is an upper surface view of one of two semiconductor devices shown inFIG.1. Also,FIG.4is a lower surface view of the semiconductor device shown inFIG.3. Also,FIG.5is a plan view of the semiconductor device removing a cover member shown inFIG.3. Further,FIG.6is a cross-sectional view along line A-A inFIG.3.

The semiconductor device PKG1of the present embodiment has a wiring substrate SUB1, a semiconductor-chip CHP1mounted on the wiring substrate SUB1(seeFIG.5), Semiconductor device PKG1also has a heat dissipation sheet TIM disposed on the semiconductor chip CHP1, the entire semiconductor chip CHP1, the entire heat dissipation sheet TIM, and a cover member LID covering a portion of the wiring substrate SUB1. Although not shown, the technique described below can also be applied to a semiconductor device having no heat dissipating sheet TIM and the cover member LID.

As shown inFIG.6, the wiring substrate SUB1has a upper surface semiconductor chip CHP1is mounted (surface, main surface, chip mounting surface)2t, the lower surface opposite to upper surface2t(surface, main surface, mounting surface)2b. Further, the wiring substrate SUB1has a plurality of side surfaces2s(seeFIGS.3to5) continuous to the respective outer edges of upper surface2tand the lower surface2b. For the present embodiment, upper surface2tof the wiring substrate SUB1(seeFIG.3) and the lower surface2b(seeFIG.4) are each square. Upper surface2tis a chip mounting surface facing the surface3tof the semiconductor chip CHP1.

The wiring substrate SUB1has a plurality of wiring layers (6 layers in the example shown inFIG.6) WL1, WL2, WL3, WL4, WL5, and a WL6for electrically connecting the terminal (pad2PD) formed on the upper surface2t, which is a chip mounting surface, and the terminal (land2LD) formed the lower surface2b, which is a mounting surface. Each wiring layer is located between the upper surface2tand the lower surface2b. Each wiring layer has a conductive pattern such as a wiring that is a path for supplying an electrical signal or power. Also, the insulating layer2eis disposed between each wiring layer. Each the wiring layer is electrically connected to each other by way of a via wiring2vor a through-hole wiring2THW, that are an interlayer conductive path penetrating through the insulating layer2e. In the present embodiment, the wiring substrate having a wiring layer of eight layers is exemplified as an example of the wiring substrate SUB1, the number of wiring layers provided by the wiring substrate SUB1is not limited to eight layers. For example, a wiring substrate having five or less layers or seven or more layers of wiring layers can be used as modified example.

Further, among the plurality of wiring layers, the wiring layer WL1disposed on the most upper surface2tside is covered with the organic insulating film SR1. The organic insulating film SR1, an opening is provided, a plurality of pad WL1provided a plurality of pad2PD is exposed from the organic insulating film SR1in the opening. Further, among the plurality of wiring layers, the wiring layer WL6disposed at a position closest to the lower surface2bside of the wiring substrate SUB1, a plurality of land2LD is provided, the wiring layer WL6is covered with the organic insulating film SR2. Each of the organic insulating film SR1and the organic insulating film SR2is a solder resist film. The plurality of pads2PD provided in the wiring layer WL1and the plurality of lands2LD provided in the wiring layer WL6are electrically connected with each other by way of the conductive pattern (wiring2dor conductive pattern of large area) formed in the respective wiring layer of the wiring substrate SUB1, the via wiring2vand the through-hole wiring2THW.

Each of the wiring2d, the pad2PD, the via wiring2v, the via land2vL (refer toFIG.9to be described later), the through-hole wiring2THW, the land2LD, and the conductive pattern2CP is made of copper or a metallic material mainly composed of, for example, copper.

Further, the wiring substrate SUB1is formed by laminating a plurality of wiring layers on the upper surface2Ct and the lower surface2Cb, respectively, of the insulating layer (core material, core insulating layer)2CR, which is made of, for example, prepreg impregnated with a resin to a glass fiber, by using a build-up method. Further, the wiring layer WL3formed on the upper surface2Ct of the insulating layer2CR and the wiring layer WL4formed on the lower surface2Cb of the insulating layer2CR are electrically connected with each other by way of a plurality of through-hole wiring2THW that are embedded in a plurality of through-holes provided so as to reach from one of the upper surface2Ct and the lower surface2Cb to the other.

In the exemplary shown inFIG.6, the wiring substrate SUB1shows a wiring2CR in which a plurality of wiring layers are laminated on upper surface2Ct side and the lower surface2Cb side of the insulating layer2Cb which is a core material, respectively. However, as modified example with respect toFIG.6, without an insulating layer2CR made of a hard material such as preg material, formed by laminating a conductive pattern such as an insulating layer2eand the wiring2din order, so-called, coreless substrate it may be used. When using a coreless substrate, the through-hole wiring2THW is not formed, the wiring layers are electrically connected via the via wiring2v.

Further, in the example shown inFIG.6, each of the plurality of land2LD, the solder balls (solder material, external terminals, electrodes, external electrodes) SB are connected. Solder balls SB, when mounting semiconductor device PKG1on the motherboard (not shown), electrically connecting a plurality of terminals of the motherboard side (not shown) and a plurality of land2LD, a conductive member. Solder balls SB, for example, lead (Pb) containing Sn—Pb solder material, or substantially free of Pb, so-called, a solder material made of lead-free solder. Examples of lead-free solders include, for example, tin (Sn), tin-bismuth (Sn—Bi), tin-copper-silver (Sn—Cu—Ag), tin-copper (Sn—Cu), and the like. Here, the lead-free solder means a solder in which the content of lead (Pb) is 0.1 wt % or less, and this content is determined as a standard of RoHS (Restriction of Hazardous Substances) instruction.

As shown inFIG.4, the plurality of balls SBs are arranged in a matrix. Although not shown inFIG.4, a plurality of lands2LD (seeFIG.6) to which a plurality of solder balls SB are bonded are also arranged in a matrix form. Thus, on the mounting surface side of the wiring substrate SUB1, a semiconductor device for arranging a plurality of external terminals (solder balls SB, land2LD) in a matrix, referred to as an area-array type semiconductor device. Area array type semiconductor device, the mounting surface of the wiring substrate SUB1(lower surface2b) side, it is possible to effectively utilize as the arrangement space of the external terminals, the mounting area of semiconductor device even if the number of external terminals is increased it is preferable in that it is possible to suppress an increase. In other words, a semiconductor device in which the number of external terminals increases as the function and integration become higher can be mounted in a space-saving manner.

Further, semiconductor device PKG1includes a semiconductor-chip CHP1mounted on the wiring substrate SUB1. As shown inFIG.6, each of the semiconductor chip CHP1includes a plurality of protruding electrode3BP are arranged surface (main surface, upper surface)3t, the back surface opposite to the surface3t(main surface, the lower surface)3b. The semiconductor chip CHP1includes a plurality of side surfaces3sintersecting the front surface3tand the back surface3b. Semiconductor chip CHP1forms a square outer shape having a smaller planar area than the wiring substrate SUB1in plan view as shown inFIG.1nthe example shown inFIG.5, the semiconductor chip CHP1is mounted on the central portion of substrate SUB1of upper surface2t, and, each of the four side surfaces3sof the semiconductor chip CHP1extends along each of the four side surfaces2sof the wiring substrate SUB1.

Further, on the front surface3tside of the semiconductor chip CHP1, a plurality of electrodes (pads, electrode pads, bonding pads)3PD are formed. In the example shown inFIG.6, the semiconductor chip CHP1, while the surface3tis opposed to upper surface2tof the wiring substrate SUB1is mounted on the wiring substrate SUB1. Such a mounting method is called a face-down mounting method or a flip-chip connection method.

Although not shown, the main surface of the semiconductor chip CHP1(specifically, the semiconductor element forming region provided on the element forming surface of semiconductor substrate is a substrate of the semiconductor chip CHP1), a plurality of semiconductor elements (circuit elements) are formed. A plurality of electrode3PD, the inside of the semiconductor chip CHP1(specifically, between the surface3tand the semiconductor element forming region (not shown) via a wiring formed in the wiring layer disposed in, and the plurality of semiconductor elements, respectively electrically connected.

The semiconductor chip CHP1(specifically, the substrate of the semiconductor chip CHP1) is made of, for example, silicon (Si). Further, the surface3t, an insulating film covering the substrate and the wiring of the semiconductor chip CHP1(passivation film3PF shown inFIG.9to be described later) is formed, a portion of each of the plurality of electrode3PD, in the opening formed in the passivation film, it is exposed from the passivation film. Each of the plurality of electrodes3PD is made of a metal, and in the present embodiment, aluminum (Al), for example, is made of aluminum (Al).

Further, as shown inFIG.6, each of the protruding electrode3PD to the plurality of electrode3BP is connected, a plurality of electrode3PD of the semiconductor chip CHP1, the plurality of pad substrate SUB1through a plurality of protruding electrode3BP, are electrically connected, respectively. Projecting electrode (bump electrode)3BP is a metal member formed so as to protrude on the surface3tof the semiconductor chip CHP1(conductive member). In the present embodiment, a pillar electrode made of copper, for example, is formed on an electrode3PD, and a solder material is laminated on the end of the columnar electrode to form a protruding electrode3BP. As the solder material laminated on the tip of the columnar electrode, a solder material containing lead or a lead-free solder can be used, similarly to the above-described solder ball SB.

When mounting the semiconductor chip CHP1to the wiring substrate SUB1, good bonding material bonding between the solder to a plurality of pad2PD (e.g., base metal film or solder paste) is formed in advance. By performing heat treatment (reflow process) while contacting the solder material at the end of the columnar electrode and the bonding material on the pad2PD, the solder is integrated, the protruding electrode3BP is formed. Further, as modified example for the present embodiment, columnar electrodes made of nickel (Ni), or micro-solder balls are formed through the underlayer metal film on the electrode3PD, the so-called solder bumps may be used as the protruding electrode3BP.

Further, between the semiconductor chip CHP1and the wiring substrate SUB1as shown inFIG.6, underfill resin (insulating resin) UF is disposed. The underfill resin UF is disposed so as to close the space between upper surface2tof the surface3tand the wiring substrate SUB1of the semiconductor chip CHP1. Each of the plurality of protrusion electrodes3BP is sealed with the underfill resin UF. Further, the underfill resin UF is made of an insulating (non-conductive) material (e.g., a resin material), is disposed so as to seal the electrical connecting portion of the semiconductor chip CHP1and the wiring substrate SUB1(junction of the plurality of protruding electrode3BP). Thus, by covering the junction between the plurality of protruding electrode3BP and the plurality of pad2PD with an underfill resin UF, it is possible to alleviate the stresses occurring in the electrically connecting portion of the semiconductor chip CHP1and the wiring substrate SUB1. Further, it is possible to alleviate the stresses occurring at the junction between the plurality of electrode3PD and the plurality of protruding electrode3BP of the semiconductor chip CHP1. Furthermore, it is also possible to protect the main surface of the semiconductor device of the semiconductor chip CHP1(circuit elements) is formed.

Further, on the back surface3bof the semiconductor chip CHP1, the cover member (lid, heat spreader, heat radiating member) LID is disposed. Cover member LID, for example, a metal plate having a higher thermal conductivity than the wiring substrate SUB1, and a function of discharging heat generated in the semiconductor chip CHP1to the outside. Further, the cover member LID is thermally connected to the semiconductor chip CHP1through the heat radiating sheet TIM. Radiating sheet TIM is in contact with each of the semiconductor chip CHP1and the cover member LID.

<Peripheral Structure of Pads of Wiring Board>

Next, the detailed structures around the connecting portions of the protruding electrodes3BP shown inFIG.6will be described.FIG.7is an enlarged plan view of an upper surface of the wire substrate shown inFIG.6.FIG.8is an enlarged cross-sectional view along line B-B inFIG.7.FIG.9is an enlarged cross-sectional view along line C-C inFIG.7.FIG.10is an enlarged plan view, which is corresponding to the enlarged plan view shown inFIG.7, showing a configuration example of a metal pattern disposed in a second wiring layer shown inFIG.9. InFIGS.8and9, in order to show the positional relation between the projection electrode3BP and the pad2PD, the projection electrode3BP connected to each of the plurality of pads2PD is shown.

The upper surface2tof the wiring substrate SUB1shown inFIG.7, and each of the plurality of wiring layers shown inFIG.6, in a plan view viewed from the semiconductor chip CHP1, overlapping the semiconductor chip CHP1region CHR1(refer toFIG.7), and does not overlap with the semiconductor chip CHP1, and a region CHR2in the periphery of the region CHR1(seeFIG.7). Further, each of the plurality of wiring layers, a boundary between the region CHR1and the region CHR2, and a boundary line CBLI overlapping with any one of the side surfaces3sof the semiconductor chip CHP1(refer toFIG.5) in plan view (seeFIG.7). In the following description, the text described with reference to the boundary line CBLI, the portion of the “boundary line CBLI” can be read as “one of the side surface3sof the semiconductor chip CHP1in a plan view as viewed from the semiconductor chip CHP1”.

A plurality of pad2PD as shown inFIG.7, in the area CHR1overlapping the semiconductor chip CHP1(refer toFIG.6), are arranged in a matrix (array-like, matrix-like). Although not shown by plan view, as shown inFIG.8, each of the plurality of protruding electrode3BP and a plurality of pad2PD which are arranged on the surface3tof the semiconductor chip CHP1is disposed at a position facing each other. Similarly, each of the plurality of electrode3PD and a plurality of pad2PD arranged on the surface3tof the semiconductor chip CHP1is disposed at a position facing each other.

Each of the plurality of pads2PD shown inFIG.7has a central portion (portion) PDe facing the protrusion electrode3BP (refer toFIG.8) and a peripheral portion (portion) PDp located around the central portion PDc. The peripheral portion PDp of each of the plurality of pad2PD is covered with the organic insulating film SR1, and the central portion PDe of each of the plurality of pad2PD is exposed from the organic insulating film SR1in the opening portion SRh formed in the organic insulating film SR1. As shown inFIG.9, the portion of the pad2PD exposed from the opening portion SRh is bonded to the protruding electrode3BP. The wiring substrate SUB1has a plurality of pad2PD, the transmission path of the electric signal (e.g., signal transmission path SGP shown inFIG.2), the reference potential supply path VSP (seeFIG.2), or the power supply potential supply path VSD (seeFIG.2) It is included in.

As shown inFIG.8, the surface3tside of the semiconductor chip3, the passivation film3PF is formed. Passivation film3PF is an indefinite insulating film having a surface3t. An opening PFh is formed in the passivation film3PF, and the electrodes3PD are exposed from the passivation film3PF in the opening PFh. One end portion of the protruding electrode3BP is in contact with the electrode3PD. The other end of the protruding electrodes3BP is in contact with the bonding material3BM made of solders.

On the upper surface2tside of the wiring substrate SUB1, the organic insulating film SR1is formed. The organic insulating film is a solder resist film having a characteristic of suppressing the wetting and spreading of solder. The organic insulating film SR1has upper surface2t. A plurality of opening portions SRh is formed in the organic insulating film SR1, and the pad2PD is exposed from the organic insulating film SR1in the opening portion SRh. A metal film2UBM is formed on the exposed surface of the pads2PD. The metal film2UBM is called an under-bump metal, and is a film provided to improve electric connecting characteristics between the protruding electrodes3BP and the pads2PD. Projection electrode3BP and the metal film2UBM is electrically connected via a solder (bonding material3BM).

As described with reference toFIGS.1and2, since the high-frequency signal is transmitted to the signal transmission path SGP, the signal transmission path SGP, noise countermeasures are necessary. For example, in the example shown inFIG.9, the wiring2dconstituting a part of the signal transmission path SGP (seeFIG.2) is disposed in the wiring layer WL2(seeFIG.6). In the thickness direction of the wiring substrate SUB1, the wiring2dis disposed between the conductive pattern2CP formed on the wiring layer WL1, the conductive pattern2CP formed on the wiring layer WL3(seeFIG.6). Reference potential is supplied to the conductive pattern2CP. The conductive pattern to which the reference potential is supplied is referred to as a ground plane. Wiring structure illustrated inFIG.9is referred to as a stripline structure, the ground plane disposed so as to sandwich the wiring2d, electromagnetic waves generated by the high-frequency signal is transmitted to the wiring2dfunctions as an electromagnetic shield to prevent diffusing around.

Further, when semiconductor device PKG1used for signal transmission applications at high speeds, in addition to the high frequency of one signal transmission path SGP, there is also a request to widen the bus width by increasing the number of signal transmission path SGP. In order to increase the number of signaling paths SGPs, the number of pads2PD needs to be increased. However, due to the need for miniaturization for semiconductor device, the overall sizing of semiconductor device PKG1needs to be suppressed even when the padding2PD is increased. As a result, the arrangement densities of the plurality of pads2PD are increased. In the exemplary embodiment shown inFIG.7, the diameter2PDD of each of the plurality of pad2PD is, for example, about 90 μm to 150 μm, whereas the smallest value of the center-to-center distance2PDP of adjacent pad2PD is about 110% to 130% relative to the diameter2PDD.

As shown inFIG.7, when the arrangement densities of a plurality of pads2PD are increased, a technique for preventing short-circuiting between adjacent pads2PD is required. For example, in the example shown inFIG.8, when the adhesion interface between the organic insulating film SR1and the pad2PD is peeled off, there is a case where the solder penetrates into the gap generated by the peeling. When the peeling progresses in the planar directions, the mutually adjacent pads2PD may communicate with each other by a gap generated by the peeling, depending on the extent of the peeling. When solder penetrates into this communicating gap, there is a fear that adjacent pad2PD is short-circuited through the solder.

From the viewpoint of preventing the short circuit as described above, it is preferable to improve the adhesion between the pads2PD and the organic insulating film SR1. Therefore, the inventor of the present application, among the pad2PD, by roughening the surface in contact with the organic insulating film SR1, was examined to suppress the peeling between the pad2PD and the organic insulating film SR1.

Incidentally, it is preferable to improve the adhesion between the metal pattern and the insulating layer containing an organic material such as a resin from the viewpoint of protecting the damage of the metal pattern. If it is possible to prevent peeling between the metal pattern and the insulating layer, the external force caused by the development of peeling, it is possible to prevent the metal pattern is broken. From this point of view, the roughened metal pattern, not only the pad2PD shown inFIG.8, the contact interface between the respective and the insulating layer2e2of the plurality of wires2dformed in the wiring layer WL2(seeFIG.6) is also preferably roughened.

However, according to the studies of the present inventors, the signal transmission path, particularly when roughening the surface roughness of the wiring2dconstituting the transmission path of the high-frequency signal, it was found that the transmission loss is increased. Further, for high density, there is a tendency that the wiring width of the wiring2dbecomes narrower. In a state where the wiring width of the wiring2dis narrow, when roughening the surface roughness, it causes a decrease in accuracy when molding the pattern. If the shape accuracy of the wiring pattern in the signal transmission path is reduced, variations in the signal transmission characteristics occur.

Based on the above examination results, the construction of semiconductor device PKG1of the present embodiment will be described with reference toFIG.9. In the following description, the metal pattern formed on the wiring layer WL1(seeFIG.6) will be described as a metal pattern2MP2. The metal pattern2MP2corresponds to any one of the plurality of pads2PD. Further, a metal pattern formed in the wiring layer WL2(seeFIG.6) will be described as a metal pattern2MP1. The metal pattern2MP1corresponds to a pattern having the via land2vL and the wiring2dthat are integrally formed with each other, the conductive pattern2CP (seeFIG.6), etc. Further, although detailed will be described later, the metal pattern formed in the wiring layer WL3(seeFIG.6) will be described as a metal pattern2MP3. The metal pattern2MP3, a plurality of conducive pattern2CP power supply potential or reference potential is supplied, through-hole lands connected to the through-hole wiring2THW shown inFIG.6(reference numeral is omitted) and the like corresponds.

As shown inFIG.9, the semiconductor device PKG1has a semiconductor chip CHP1, and a wiring substrate SUB1having a upper surface2tfacing the surface3tof the semiconductor chip CHP1. Wiring substrate SUB1includes an insulating layer2e1, and a metal pattern2MP1formed on the insulating layer2e1. The wiring substrate SUB1is in contact with the metal pattern2MP1, and includes an insulating layer2e2formed on the insulating layer2e1so as to cover the metal pattern2MP1, and a metal pattern2MP2formed on the insulating layer2e2. The metal pattern2MP2is provided with a first portion (central portion PDc shown inFIG.7) facing the protruding electrode3BP and a second portion (surrounding portion PDp shown inFIG.7) around first portion. The wiring substrate SUB1is in contact with second portion of the metal pattern2MP2, and includes an organic insulating film formed on the insulating layer2e2so that first portion of the metal pattern2MP2is exposed. The metal pattern2MP1has a lower surface MP1bin contact with the insulating layer2e1, located on the opposite side of the lower surface MP1b, and a upper surface MP1tin contact with the insulating layer2e2. The Metal pattern2MP2has a lower surface MP2bin contact with the insulating layer2e2, and a upper surface MP2tin contact with the organic insulating film in second portion. The surface roughness of2MP2of the metal pattern upper surface MP2tis larger than that of the lower surface MP2bof the metal pattern, upper surface MP1tof the metal pattern2MP1, and the lower surface MP1b, respectively.

For example, when the index of the surface roughness is expressed using Ra, which is an arithmetic average roughness, the following range is preferable. The surface roughness (Ra) of upper surface MP2tof the metal pattern2MP2is preferably 0.3 μm or more. On the other hand, the lower surface MP2bof the metal pattern2MP2, upper surface MP1tof the metal pattern2MP1, and the lower surface MP1b, the respective surface roughness Ra is preferable less than 0.3 μm.

The above-mentioned arithmetic average roughness Ra is calculated as follows. First, extracting the reference length L in the direction of the average line from the roughness curve of the surface. Next, the X-axis in the direction of the average line of the extracted portion, taking the Y-axis in a direction perpendicular to the average line, represents the roughness curve by y=f(x). At this time, Ra, which is the arithmetic average roughness, is calculated by the following equation.

Ra=1L⁢∫0L❘"\[LeftBracketingBar]"f⁡(x)❘"\[RightBracketingBar]"⁢dx[EQUATION⁢1]

For the configuration described above, first, the peeling of the organic insulating film SR1, the surface roughening of the pad2PD of the wiring layer WL1short circuit of adjacent pad2PD is most likely to occur (seeFIG.6). On the other hand, the lower surface MP2bof the metal pattern2MP2not in contact with the organic insulating film SR1, upper surface MP1tof the metal pattern2MP1, and the surface roughness of each of the lower surface MP1bis smaller than the surface roughness of the pad2PD. Therefore, for example, even when the high-frequency signal is transmitted to the wiring2dshown inFIG.9, it is possible to reduce the transmission loss.

An example of the method for roughening the surface roughness of the pad2PD (i.e., metal pattern2MP2) includes a sandblasting process. This is a method of roughening the surface roughness of a target by causing a group of fine particles made of an inorganic material to collide with the target.

It is preferable that the surface on which the process for roughening the surface roughness (hereinafter, referred to as the roughening treatment) is performed contains at least upper surface MP2tof the pad2PD. Upper surface MP2tis a surface easily become a starting point of peeling of the organic insulating film SR1. Further, if it is possible to prevent peeling in upper surface MP2t, it is possible to prevent the penetration of the bonding material3BM made of solder.

Further, in the example shown inFIG.9, the metal pattern2MP2has a side surface MP2swhich is connected to the upper surface MP2tand is in contact with the organic insulating film SR1. The surface roughness of the side surface2sof the metal pattern2MP2is larger than the respective surface roughness of the lower surface MP2bof the metal pattern2MP2, upper surface MP1tof the metal pattern2MP1, and the lower surface MP1b. Surface roughness of the side surface2sof the metal pattern2MP2is comparable to the surface roughness of upper surface MP2t, Ra is arithmetic mean roughness is preferably 0.3 μm or more. By the surface roughness of the side MP2sto the same extent as the surface roughness of upper surface MP2t, it is possible to prevent the peeling mode peeling generated in the side MP2sis developed to upper surface MP2tside. However, although illustration is omitted, as a modified example with respect toFIG.9, the side surface MP2sis not subjected to the roughening treatment, and upper surface MP2tis selectively subjected to the roughening treatment in some cases. Even in this modified example, peeling from upper surface MP2tas a starting point can be prevented.

Further, the wiring layer WL1(seeFIG.6), in addition to the pad2PD, a metal pattern such as a conductive pattern2CP is formed. Only a plurality of pad2PD formed on the wiring layer upper surface MP2tof the pad WL1, or may be selectively roughened to some of the plurality of pad2PD. However, from the viewpoint of suppressing the peeling between the metal pattern formed on the organic insulating film SR1and the wiring layer WL1, including upper surface of the conductive pattern2CP, it is particularly preferable to perform the roughening treatment for all of the plurality of metal patterns formed on the wiring layer WL1. In this case, the surface roughness of upper surface of all the metal patterns formed on the wiring layer WL1is greater than the lower surface MP2bof the metal pattern2MP2, upper surface MP1tof the metal pattern2MP1, and the lower surface MP1b, respectively of the surface roughness.

Further, as shown inFIG.9, the metal film2UBM is formed on the central portion of the metal pattern2MP2(portion), and the protruding electrode3BP and the metal film2UBM is electrically connected via a solder (bonding material3BM). In this case, when peeling (interfacial peeling) occurs at the interface between upper surface MP2tand the organic insulating film SR1of the metal pattern2MP2, peeling propagates (progresses) into the organic insulating film SR1, the organic insulating film SR1there is a possibility that solder penetrates into the gap propagated to.

Further, in the transmission path of the high-frequency signal described above, reducing the transmission loss by reducing the surface roughness is more effective for the pattern extending long like the wiring pattern. In case ofFIG.9, the protruding electrode3BP is electrically connected to the metal pattern2MP1. The metal pattern2MP1is electrically connected to the metal pattern2MP2by way of the via wiring2vformed so as to penetrate through the insulating layer2e2. The metal pattern2MP1includes a via land (via land portion)2vL to which the via wiring2vis connected, and a wiring (wiring portion)2dformed integrally with the via land2vL and extending along the X direction.

Further, as shown inFIG.7, the pad2PD corresponding to the metal pattern2MP2(seeFIG.9), in a plan view, are disposed in the area CHR1overlapping the semiconductor chip CHP1. As shown inFIG.10, the wires2dof the metal pattern2MP1, in plan view, extend from the region CHR1toward the region CHR2that is around the region CHR1. In other words, the interconnection2dstraddles the border line CBLI between the region CHR1and the region CHR2. In other words, in plan view, the pad2PD does not overlap the side surface3sof the semiconductor chip CHP1(refer toFIG.9) (seeFIG.9), and the wiring2doverlaps with one of the side surfaces3sof the semiconductor chip CHP1.

The length of the wiring2dshown inFIG.9is longer than the respective lengths of the metal pattern2MP2, the via wiring2v, and the via land2vL. In the above, the length of the wiring2d, of the wiring2d, from the connection portion between the via lands2vL shown inFIG.9, is defined as the length to the connection portion between the via wiring2vconnecting the wiring layer WL2and the wiring layer WL3shown in FIG. The length of the metal pattern2MP2is defined as the length from the connection portion between the protruding electrode2BP shown inFIG.9to the connection portion between the via wiring2vconnecting the wiring layer WL1and the wiring layer WL2. The length of the via wiring2vis defined as the length of the via wiring2vin the Z direction shown inFIG.9. The length of the via land2vL is defined as the length from the connecting portion of the via lands2vL, which is connected to the via wiring2vconnecting between the wiring layer WL1and the wiring layer WL2, to the connecting portion of the via lands2vL, which is connected to the wiring2d. Further, the metal pattern2MP1and the metal pattern2MP2, an electric signal (e.g., signal SGT or signal SGR shown inFIG.1) is transmitted. In other words, the metal pattern2MP1and the metal pattern2MP2are included in the signal transmission path SGP (seeFIG.2). Further, in the present embodiment, the electric signal flowing through the signal transmission path SGP is a high-frequency signal of 30 GHz (gigahertz) or more. Therefore, of the transmission path of the high-frequency signal of more than 30 GHZ, the portion extending longer than the other portion of the transmission path (portion corresponding to the wiring2d), when increasing the roughness of the surface, the insulating layer2e1and the insulating layer2e2in contact with this portion (wiring2d) adhesion is improved, but susceptible to transmission loss due to this roughening. That is, the skin effect of the high-frequency signal (the higher the frequency signal, the scattering loss due to the phenomenon that the current only flows on the surface of the wiring) is increased. On the other hand, according to the present embodiment, the surface roughness of the wire2dconstituting the signal transmission path, for example, since small than the surface roughness of upper surface MP2tof the metal pattern2MP2, it is possible to reduce the transmission loss.

Peeling of the metal pattern and the insulating film is generated due to the difference in linear expansion coefficient caused by the material constituting each member. Therefore, when the difference in the linear expansion coefficient between the metal pattern and the insulating film is small, peeling hardly occurs, if the difference in the linear expansion coefficient is large, peeling is likely to occur. For example, in the example shown inFIG.9, the thermal expansion coefficient of the organic insulating film SR1(specifically, the linear expansion coefficient) is greater than the thermal expansion coefficient of the insulating layer2e2(specifically, the linear expansion coefficient). Also, the storage modulus of the organic insulating film SR1is softer than the storage modulus of the insulating layer2e2. In addition to the electric insulating properties, the organic insulating film SR1is required to function as a solder resist film as described above. In addition, since the organic insulating film SR1is a film located on the outermost surface of the materials constituting the interconnection substrate SUB1, it is also required to function as a protective film. On the other hand, the insulating layer2e1and the insulating layer2e2located in the inner layer of the wiring substrate SUB1than the organic insulating film SR1, in addition to the electrically insulating properties, so that the warpage and deformation of the wiring substrate SUB1can be suppressed, high stiffness is required. Therefore, by selecting the material so that the thermal expansion coefficient of the insulating layer2e2is reduced, it is preferable to approach the thermal expansion coefficient of the metal pattern2MP1. Thus, it is possible to reduce the generation of peeling at the interface between the metal pattern2MP1and the insulating layer2e2. On the other hand, the interface between the organic insulating film SR1and the metal pattern2MP2, it is possible to suppress the generation of peeling by increasing the surface roughness of upper surface MP2tas described above.

Further, as an example shown inFIG.6, when the metal pattern formed on the wiring layer WL3(metal pattern2MP3shown inFIG.9) is formed on the insulating layer2CR is a core insulating layer, peeling at the interface between the insulating layer2CR and the metal pattern2MP3is difficult to occur. As described above, the insulating layer2CR is an insulating layer made of a prepreg obtained by impregnating glass fibers with a resin. In this case, it is possible to reduce the linear expansion coefficient of the insulating layer2CR. On the other hand, the organic insulating film SR1, the insulating layer2e1, and the insulating layer2e2do not contain fiberglass. Therefore, the organic insulating film SR1, the respective linear expansion coefficients of the insulating layer2e1and the insulating layer2e2is larger than the linear expansion coefficient of the insulating layer2CR.

Further, as shown inFIG.9, the thickness TSR of the organic insulating film SR1is thinner than the thickness Te2of the insulating layer2e2. The organic insulating film SR1, which is relatively thinner than the insulating layer2e2, tends to expand or contract in accordance with environmental temperatures more easily than the insulating layer2e2. Therefore, the adhesion interface between the organic insulating film SR1and the metal pattern2MP2, it is particularly essential to take peeling countermeasures by roughening treatment.

FIG.11is an enlarged cross-sectional view showing a modified example with respect toFIG.9. The semiconductor device PKG3shown inFIG.11is the same as2MP3PKG1shown inFIG.9except that upper surface MP3tof the metal pattern2MP3is subjected to roughening treatment as described below. Therefore, duplicate descriptions are omitted. Semiconductor device PKG3shown inFIG.11further includes a core insulating layer2CR (seeFIG.6) and a metal pattern2MP3formed on the insulating layer2CR. The metal pattern2MP3is a conductive pattern2CP formed on the wiring layer WL3(seeFIG.6). The conductive pattern2CP, although the reference potential or power supply potential is supplied, the reference potential is supplied to the conductive pattern2CP shown in FIG. The metal pattern2MP3has an insulating layer2CR (seeFIG.6) abutting lower surface MP3b, and located on the opposite side of the lower surface MP3b, and the upper surface MP3tin contact with the insulating layer2e1. The surface roughness of2MP3of the metal pattern upper surface MP3tis larger than that of the lower surface2MP2of the metal pattern MP2b, upper surface MP It of the metal pattern2MP1, and the lower surface MP1b, respectively. For example, the metal pattern2MP3is subjected to the roughening treatment similar to that of the metal pattern2MP2, and the surface roughness (Ra) of upper surface MP3tis preferably 0.3 μm or more. As for the supply path of the reference potential, it is less susceptible to transmission loss due to roughening compared with the signal transmission path. On the other hand, the metal pattern2MP3, when compared with the wire2d, is a pattern of a large area having an area of three times or more. Large-area metal pattern2MP3have large stresses generated when they are thermally shrunk or thermally expanded. Therefore, peeling is likely to occur at the adhesion interface between the metal pattern2MP3and the insulating layer2e1due to stresses. Therefore, it is preferable that the metal pattern2MP3is subjected to a roughening treatment in the same manner as the metal pattern2MP2.

However, even when peeling occurs between the metal-pattern2MP3and the insulating layer2e1, it is not immediately insulation failure or the like occurs. Therefore, the order of precedence of the roughening treatment is higher in the metal pattern2MP1than in the metal pattern2MP3. Therefore, as in semiconductor device PKG1shown inFIG.9, the surface roughness of upper surface MP3tof the metal pattern2MP3may be comparable to the surface roughness of upper surface MP It of the metal pattern2MP1.

Incidentally, inFIG.9, upper surface MP2tof the metal pattern2MP2, the side MP2s, and the surface of the metal pattern other than upper surface MP3tof the metal pattern2MP3is illustrated as a flat surface. However, when a step called a desmear process is performed in the process of manufacturing the interconnection substrate SUB1, the other surface may not be a flat surface.FIG.12is an enlarged cross-sectional view showing a modified example with respect toFIG.11. Incidentally, semiconductor device PKG4shown inFIG.12is the same as semiconductor device PKG3shown inFIG.11except that it includes an uneven surface caused by the desmear process described below. Therefore, duplicate descriptions are omitted.

In the manufacturing process of the wiring substrate SUB1, for example, when adopting a build-up method, after forming an insulating layer on the wiring layer of the lower layer, subjected to drilling for providing the via wiring2v. At this time, in order to remove the residue of the insulating layer remaining after the drilling process, for example, the non-treated surface is irradiated with plasma. This process is referred to as desmear processing (sometimes referred to as plasma desmear processing). By performing the desmear treatment, the adhesiveness between the metal film and the insulating layer can be improved. On the other hand, since the plasma is irradiated to the insulating layer in the desmear process, the surface roughness of the insulating layer is an underlayer of the metal pattern is larger when compared with the case without the desmear process. When a metal pattern is formed after the desmear treatment, the lower surface of the metal pattern becomes uneven surface following the unevenness of the desmear processed insulating layer.

As shown inFIG.12, each of the lower surface MP1bof the metal pattern2MP1and the lower surface MP2bof the metal pattern2MP2has an uneven surface due to desmear treatment rather than a flat surface. However, in the case of the uneven surface caused by the desmear process, it is possible to suppress the surface roughness from becoming extremely large as compared with the roughening treatment such as the sand blasting treatment described above. Therefore, even in modified example shown inFIG.12, the following can be said. That is, the surface roughness of2MP2of the metal pattern upper surface MP2tis larger than the lower surface MP2bof the metal pattern, upper surface MP1tof the metal pattern2MP1, and the lower surface MP1b, respectively. Also, the surface roughness of the side surface2sof the metal pattern2MP2, the lower surface MP2bof the metal pattern2MP2, upper surface MP1tof the metal pattern2MP1, and the lower surface MP1b, greater than the respective surface roughness of. Also, the surface roughness of2MP3of the metal pattern upper surface MP3tis larger than the respective surface roughness of the lower surface MP2bof the metal pattern2MP2, upper surface MP1tof the metal pattern2MP1, and the lower surface MP1b.

Further, in semiconductor device PKG4of modified example shown inFIG.12, in that it does not perform the roughening treatment on the metal-pattern2MP1is the same as semiconductor device PKG1shown in FIG. Therefore, the surface roughness and the surface roughness of the lower surface MP1bof upper surface MP1tof the metal pattern2MP1the following relations hold. That is, the surface roughness of upper surface MP1tof the metal pattern2MP1is smaller than the surface roughness of the lower surface MP1bof the metal pattern2MP1. Also, the surface roughness of upper surface MP1tof the metal pattern2MP1is smaller than the respective surface roughness of upper surface MP2t, the lower surface MP2b, and the side MP2sof the metal pattern2MP2.

Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and it is needless to say that various modifications can be made without departing from the gist thereof.