Patent ID: 12232307

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range.

The present disclosure is directed to semiconductor devices, and particularly to uniform application of an underfill material in semiconductor die packaging. Generally, the methods and structures of the present disclosure may be used to provide a chip package structure such as a fan-out wafer level package (FOWLP) or a fan-out panel level package (FOPLP). While the present disclosure is described using an FOWLP configuration, the methods and structures of the present disclosure may be implemented in an FOPLP configuration or any other fan-out or fan-in package configuration.

Metal bonding structures on semiconductor dies and redistribution structures may increase the capillary force during application of an underfill material. The increased capillary force may be advantageously used to enhance uniformity of the underfill material distribution around the metal bonding structures in a die-to-die gap or in a die-to-package gap (such as a die-to-chip-scale-package gap). According to an aspect of the present disclosure, the flow uniformity of an underfill material may be enhanced using dummy metal bonding structures and/or dummy solder material portions. Void formation within an underfill material portion within a die-to-die gap or a die-to-package gap may be avoided or reduced through use of the dummy structures of the present disclosure that enhance the capillary force in inter-die regions.

For example, a high performance computing (HPC) package may comprise multiple semiconductor dies including at least one system-on-chip (SoC) die and at least one high bandwidth memory (HBM) die within a chiplet, such as a fan-out wafer level package. Die-to-die gaps and/or die-to-chip-scale-package gaps increase the complexity of an underfill material dispensation step. In instances in which the underfill material flows non-uniformly, voids may be formed within the underfill material portion in gap regions. Such voids in the underfill material may cause solder bridging or a “popcorn” phenomenon in which solder material portions are securely attached to metal bonding structures. The dummy structures of embodiments of the present disclosure may be used to avoid or reduce formation voids in the underfill material. The various aspects and embodiments of the methods and structures of the present disclosure are described with reference to accompanying drawings.

Referring toFIG.1, an exemplary structure according to an embodiment of the present disclosure includes a first carrier substrate300and redistribution structures920formed on a front side surface of the first carrier substrate300. The first carrier substrate300may include an optically transparent substrate such as a glass substrate or a sapphire substrate. The diameter of the first carrier substrate300may be in a range from 150 mm to 290 mm, and the thickness of the first carrier substrate300may be in a range from 500 microns to 2,000 microns, although lesser and greater thicknesses may also be used. Alternatively, the first carrier substrate300may be provided in a rectangular panel format.

A first adhesive layer301may be applied to the front-side surface of the first carrier substrate300. In one embodiment, the first adhesive layer301may be a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer may convert ultraviolet light to heat, which may cause the material of the LTHC layer to lose adhesion. Alternatively, the first adhesive layer301may include a thermally decomposing adhesive material. For example, the first adhesive layer301may include an acrylic pressure-sensitive adhesive that decomposes at an elevated temperature. The debonding temperature of the thermally decomposing adhesive material may be in a range from 150 degrees to 200 degrees Celsius.

Redistribution structures920may be formed over the first adhesive layer301. Specifically, a redistribution structure920may be formed within each unit area UA, which is the area of a repetition unit that is repeated in a two-dimensional array over the first carrier substrate300. Each redistribution structure920may include redistribution dielectric layers922and redistribution wiring interconnects924. The redistribution dielectric layers922include a respective dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable materials may be within the contemplated scope of disclosure. Each redistribution dielectric layer922may be formed by spin coating and drying of the respective dielectric polymer material. The thickness of each redistribution dielectric layer922may be in a range from 2 microns to 40 microns, such as from 4 microns to 20 microns. Each redistribution dielectric layer922may be patterned, for example, by applying and patterning a respective photoresist layer thereabove, and by transferring the pattern in the photoresist layer into the redistribution dielectric layer922using an etch process such as an anisotropic etch process. The photoresist layer may be subsequently removed, for example, by ashing.

Each of the redistribution wiring interconnects924may be formed by depositing a metallic seed layer by sputtering, by applying and patterning a photoresist layer over the metallic seed layer to form a pattern of openings through the photoresist layer, by electroplating a metallic fill material (such as copper, nickel, or a stack of copper and nickel), by removing the photoresist layer (for example, by ashing), and by etching portions of the metallic seed layer located between the electroplated metallic fill material portions. The metallic seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have thickness in a range from 50 nm to 400 nm, and the copper seed layer may have a thickness in a range from 100 nm to 500 nm. The metallic fill material for the redistribution wiring interconnects924may include copper, nickel, or copper and nickel. The thickness of the metallic fill material that is deposited for each redistribution wiring interconnect924may be in a range from 2 microns to 40 microns, such as from 4 microns to 10 microns, although lesser or greater thicknesses may also be used. The total number of levels of wiring in each redistribution structure920(i.e., the levels of the redistribution wiring interconnects924) may be in a range from 1 to 10. Other suitable materials are within the contemplated scope of disclosure. A periodic two-dimensional array (such as a rectangular array) of redistribution structures920may be formed over the first carrier substrate300. The layer including all redistribution structures920is herein referred to as a redistribution structure layer. The redistribution structure layer includes a two-dimensional array of redistribution structures920.

Referring toFIGS.2A and2B, at least one metallic material and a first material may be sequentially deposited over the front-side surface of the redistribution structures920. The at least one metallic material comprises a material that may be used for metallic bumps, such as copper. The thickness of the at least one metallic material may be in a range from 5 microns to 60 microns, such as from 10 microns to 30 microns, although lesser and greater thicknesses may also be used. The first material may comprise a first material suitable for C2 bonding, i.e., for microbump bonding. The thickness of the first material may be in a range from 2 microns to 30 microns, such as from 4 microns to 15 microns, although lesser and greater thicknesses may also be used.

The first material and the at least one metallic material may be patterned into discrete arrays of first solder material portions940and arrays of metal bonding structures, which are herein referred to as arrays of redistribution-side bonding structures938. Each array of redistribution-side bonding structures938is formed within a respective unit area UA. Each array of first solder material portions940is formed within a respective unit area UA. Each first solder material portion940may have a same horizontal cross-sectional shape as an underlying redistribution-side bonding structures938.

In one embodiment, the redistribution-side bonding structures938may include, and/or may consist essentially of, copper or a copper-containing alloy. Other suitable materials are within the contemplated scope of disclosure. The thickness of the redistribution-side bonding structures938may be in a range from 5 microns to 60 microns, although lesser or greater thicknesses may also be used. The redistribution-side bonding structures938may have horizontal cross-sectional shapes of rectangles, rounded rectangles, circles, regular polygons, irregular polygons, or any other two-dimensional curvilinear shape having a closed periphery. In one embodiment, redistribution-side bonding structures938may be configured for microbump bonding (i.e., C2 bonding), and may have a thickness in a range from 10 microns to 30 microns, although lesser or greater thicknesses may also be used. In this embodiment, each array of redistribution-side bonding structures938may be formed as an array of microbumps (such as copper pillars) having a lateral dimension in a range from 10 microns to 25 microns, and having a pitch in a range from 20 microns to 50 microns.

Referring toFIGS.3A and3B, a set of at least one semiconductor die (700,800) may be bonded to each redistribution structure920. In one embodiment, the redistribution structures920may be arranged as a two-dimensional periodic array, and multiple sets of at least one semiconductor die (700,800) may be bonded to the redistribution structures920as a two-dimensional periodic rectangular array of sets of the at least one semiconductor die (700,800). Each set of at least one semiconductor die (700,800) includes at least one semiconductor die. Each set of at least one semiconductor die (700,800) may include any set of at least one semiconductor die known in the art. In one embodiment, each set of at least one semiconductor die (700,800) may comprise a plurality of semiconductor dies (700,800). For example, each set of at least one semiconductor die (700,800) may include at least one system-on-chip (SoC) die700and/or at least one memory die800. Each SoC die700may comprise an application processor die, a central processing unit die, or a graphic processing unit die. In one embodiment, the at least one memory die800may comprise a high bandwidth memory (HBM) die that includes a vertical stack of static random access memory dies. In one embodiment, the at least one semiconductor die (700,800) may include at least one system-on-chip (SoC) die and a high bandwidth memory (HBM) die including a vertical stack of static random access memory (SRAM) dies that are interconnected to one another through microbumps and are laterally surrounded by an epoxy molding material enclosure frame.

Referring toFIGS.3A and3B, each of the semiconductor dies (700,800) may include a respective array of die-side bonding structures (780,880). For example, each SoC die700may include an array of SoC metal bonding structures780, and each memory die800may include an array of memory-die metal bonding structures880. Each of the semiconductor dies (700,800) may be positioned in a face-down position such that die-side bonding structures (780,880) face the first solder material portions940. Each set of a plurality of semiconductor dies (700,800) may be placed within a respective unit area UA. Placement of the semiconductor dies (700,800) may be performed using a pick and place apparatus so that each of the die-side bonding structures (780,880) is placed on a top surface of a respective one of the first solder material portions940.

Generally, a redistribution structure920including redistribution-side bonding structures938thereupon may be provided, and a plurality of semiconductor dies (700,800) including a respective set of die-side bonding structures (780,880) may be provided. The plurality of semiconductor dies (700,800) may be bonded to the redistribution structure920using first solder material portions940that are bonded to a respective redistribution-side bonding structure938within a first subset of the redistribution-side bonding structures938and to a respective one of the die-side bonding structures (780,880). A second subset of the redistribution-side bonding structures938is not bonded to any of the plurality of semiconductor dies (700,800).

The first subset of the redistribution-side bonding structures938may be bonded to a first subset of the first solder material portions940, and the second subset of the redistribution-side bonding structures938may be bonded to a second subset of the first solder material portions940. The second subset of the redistribution-side bonding structures938is herein referred to as dummy redistribution-side bonding structures938D. The second subset of the first solder material portions940is herein referred to as dummy solder material portions940D. The second subset of the redistribution-side bonding structures938(including the dummy redistribution-side bonding structure938D) is devoid of any bonds to any of the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800). Put another way, the second subset of the redistribution-side bonding structures938(including the dummy redistribution-side bonding structure938D) is not bonded to any of the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800).

Each redistribution-side bonding structure938within the first subset of the redistribution-side bonding structures938may have an areal overlap with a respective one of the plurality of semiconductor dies (700,800) in a plan view (such as a top-down view), and may be located entirely within the area of the respective one of the plurality of semiconductor dies (700,800) in the plan view. Each dummy redistribution-side bonding structure938D does not have any areal overlap with the plurality of semiconductor dies (700,800) in the plan view, and may be located entirely between areas of a neighboring pair of semiconductor dies (700,800) within the plurality of semiconductor dies (700,800) in the plan view.

Each first solder material portion940within the first subset of the first solder material portions940may have an areal overlap with a respective one of the plurality of semiconductor dies (700,800) in the plan view, and may be located entirely within the area of the respective one of the plurality of semiconductor dies (700,800) in the plan view. Each dummy solder material portion940D does not have any areal overlap with the plurality of semiconductor dies (700,800) in the plan view, and may be located entirely between areas of a neighboring pair of semiconductor dies (700,800) within the plurality of semiconductor dies (700,800) in the plan view.

Generally, first solder material portions940(such as the first subset of the first solder material portions940) may be formed on the first subset of the redistribution-side bonding structures938, and additional first solder material portions940(such as the dummy solder material portions940D) may be formed on the second subset of the redistribution-side bonding structures938(i.e., on the dummy redistribution-side bonding structures938D). The additional first solder material portions (such as the dummy solder material portions940D) are not bonded to any of the die-side bonding structures (780,880). The additional first solder material portions (such as the dummy solder material portions940D) are devoid of any bonds to any of the die-side bonding structures (780,880).

In one embodiment, the dummy solder material portions940D may be located on a respective dummy redistribution-side bonding structure938D selected from the second subset of the redistribution-side bonding structures938, and do not contact any of the plurality of semiconductor dies (700,800). In one embodiment, the dummy solder material portions940D comprises at least one row of dummy solder material portions940D arranged along a direction that is parallel to, and is located between, a pair of sidewalls of a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700,800). Each of the dummy solder material portions940D has a same material composition as the sets of solder material portions940that are bonded to a respective pair of a redistribution-side bonding structure938and a die-side bonding structure (780,880).

Generally, the dummy redistribution-side bonding structures938D and the dummy solder material portions940D do not have any areal overlap with the plurality of semiconductor dies (700,800) in the plan view (such as the top-down view ofFIG.3B) within each unit area UA. In one embodiment, a row of dummy redistribution-side bonding structures938D and a row of dummy solder material portions940D may be located between areas of a neighboring pair of semiconductor dies (700,800) within the plurality of semiconductor dies (700,800) in the plan view. The arrangement of the dummy redistribution-side bonding structures938D and the dummy solder material portions940D may vary depending on the arrangement of the plurality of semiconductor dies (700,800) within each unit area UA.

FIGS.4A-4Cillustrate alternative configurations of the exemplary structure that may be derived from the exemplary structure ofFIGS.3A and3Bby varying the arrangement of the semiconductor dies (700,800) and/or the total number of semiconductor dies (700,800) and/or the type(s) of the semiconductor dies (700,800). The semiconductor dies (701,702,703,704) within the alternative configurations of the exemplary structure inFIGS.4A-4Cinclude a first semiconductor die701, a second semiconductor die702, and optionally a third semiconductor die703and/or a fourth semiconductor die704. Each of the semiconductor dies (701,702,703,704) may comprise an SoC die700or a memory die800. The pattern of the dummy redistribution-side bonding structures938D and the dummy solder material portions940D may include a single-row pattern illustrated inFIG.4A, a multiple-row pattern illustrated inFIG.4B, and/or a cross pattern illustrated inFIG.4C. Generally, any pattern may be used for arrangement of the dummy redistribution-side bonding structures938D and the dummy solder material portions940D provided that at least one dummy redistribution-side bonding structure938D and at least one dummy solder material portion940D is placed between a neighboring pair of semiconductor dies {(700,800) or (701,702,703,704)}.

WhileFIGS.3A,3B, and4A-4Cillustrate configurations in which the dummy solder material portions940D and the dummy redistribution-side bonding structures938D have horizontal cross-sectional shapes of a respective rectangle. Generally, the dummy solder material portions940D and the dummy redistribution-side bonding structures938D may have a horizontal cross-sectional shape of any two-dimensional curvilinear shape having a closed periphery.

Referring toFIG.5A, alternative shapes for the dummy solder material portions940D (and for the dummy redistribution-side bonding structures938) are shown, which may comprise a regular polygon having equal sides.

Referring toFIG.5B, additional alternative shapes for the dummy solder material portions940D (and for the dummy redistribution-side bonding structures938) are shown, which may comprise an irregular polygon.

Yet alternatively, the dummy solder material portions940D (and for the dummy redistribution-side bonding structures938) may have horizontal cross-sectional shapes of a circle, an ellipse, an oval, or a curved two-dimensional shape having a closed periphery.

Referring toFIG.6, a high bandwidth memory (HBM) die810is illustrated, which may be used as a memory die800within the exemplary structures ofFIGS.3A and3B,4A,4B, and/or4C. The HBM die810includes a vertical stack of static random access memory dies (811,812,813,814,815) that are interconnected to one another through microbumps820and are laterally surrounded by an epoxy molding material enclosure frame816. The gaps between vertically neighboring pairs of the random access memory dies (811,812,813,814,815) may be filled with a HBM underfill material portions822that laterally surrounds a respective set of microbumps820. The HBM die810may comprise an array of memory-die metal bonding structures880configured to be bonded to a subset of an array of redistribution-side bonding structures938within a unit area UA. The HBM die810may be configured to provide a high bandwidth as defined under JEDEC standards, i.e., standards defined by The JEDEC Solid State Technology Association.

Referring toFIGS.7A and7B, a first underfill material may be applied into each gap between the redistribution structures920and sets of a plurality of semiconductor dies (700,800) that are bonded to the redistribution structures920. The first underfill material may comprise any underfill material known in the art. A first underfill material portion950may be formed within each unit area UA between a redistribution structure920and an overlying set of a plurality of semiconductor dies (700,800). The first underfill material portions950may be formed by injecting the first underfill material around a respective array of first solder material portions940in a respective unit area UA. Any known underfill material application method may be used, which may be, for example, the capillary underfill method, the molded underfill method, or the printed underfill method.

Within each unit area UA, a first underfill material portion950laterally surrounds, and contacts, each of the first solder material portions940within the unit area UA, which include a first subset of the first solder material portions940that may be bonded to a respective pair of a redistribution-side bonding structure938and a die-side bonding structure (780or880), and a second subset of the first solder material portions940(i.e., the dummy solder material portions940D) that are not bonded to any of the die-side bonding structures (780or880). The first underfill material portion950may be formed around, and may contact, the first solder material portions940, the redistribution-side bonding structures938, and the die-side bonding structures (780,880) in the unit area UA. Within each unit area UA, the dummy redistribution-side bonding structures938D (i.e., the subset of the redistribution-side bonding structures938that is not bonded (i.e., devoid of any bonds) to any of the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800), may be laterally surrounded by, and may contact, the first underfill material portion950.

Each redistribution structure920in a unit area UA may include redistribution-side bonding structures938. A plurality of semiconductor dies (700,800) comprising a respective set of die-side bonding structures (780,880) may be attached to a respective subset of the redistribution-side bonding structures938through a respective set of first solder material portions940(which include the first subset of the first solder material portions940). Within each unit area UA, a first underfill material portion950laterally surrounds the redistribution-side bonding structures938and the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800). A subset of the redistribution-side bonding structures938(i.e., the dummy redistribution-side bonding structures938D) is not bonded to any of the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800), and may be laterally surrounded by the first underfill material portion950.

Referring toFIGS.8A and8B, an epoxy molding compound (EMC) may be applied to the gaps between contiguous assemblies of a respective set of semiconductor dies (700,800) and a first underfill material portion950. The EMC may include an epoxy-containing compound that may be hardened (i.e., cured) to provide a dielectric material portion having sufficient stiffness and mechanical strength. The EMC may include epoxy resin, hardener, silica (as a filler material), and other additives. The EMC may be provided in a liquid form or in a solid form depending on the viscosity and flowability. Liquid EMC provides better handling, good flowability, less voids, better fill, and less flow marks. Solid EMC provides less cure shrinkage, better stand-off, and less die drift. A high filler content (such as 85% in weight) within an EMC may shorten the time in mold, lower the mold shrinkage, and reduce the mold warpage. Uniform filler size distribution in the EMC may reduce flow marks, and may enhance flow ability. The curing temperature of the EMC may be lower than the release (debonding) temperature of the first adhesive layer301if the adhesive layer includes a thermally debonding material. For example, the curing temperature of the EMC may be in a range from 125° C. to 150° C.

The EMC may be cured at a curing temperature to form an EMC matrix910M that laterally surrounds and embeds each assembly of a set of semiconductor dies (700,800) and a first underfill material portion950. The EMC matrix910M may include a plurality of epoxy molding compound (EMC) die frames that may be laterally adjoined to one another. Each EMC die frame may be a portion of the EMC matrix910M that is located within a respective unit area UA. Thus, each EMC die frame may laterally surround and embed a respective a set of semiconductor dies (700,800) and a respective first underfill material portion950.

Portions of the EMC matrix910M that overlies the horizontal plane including the top surfaces of the semiconductor dies (700,800) may be removed by a planarization process. For example, the portions of the EMC matrix910M that overlies the horizontal plane may be removed using a chemical mechanical planarization. The combination of the remaining portion of the EMC matrix910M, the semiconductor dies (700,800), the first underfill material portions950, and the two-dimensional array of redistribution structures920comprises a reconstituted wafer900W. Each portion of the EMC matrix910M located within a unit area UA constitutes an EMC die frame.

Referring toFIG.9, a second adhesive layer401may be applied to the physically exposed planar surface of the reconstituted wafer900W, i.e., the physically exposed surfaces of the EMC matrix910M, the semiconductor dies (700,800), and the first underfill material portions950. In one embodiment, the second adhesive layer401may comprise a same material as, or may comprise a different material from, the material of the first adhesive layer301. If the first adhesive layer301comprises a thermally decomposing adhesive material, the second adhesive layer401comprises another thermally decomposing adhesive material that decomposes at a higher temperature, or may comprise a light-to-heat conversion material.

A second carrier substrate400may be attached to the second adhesive layer401. The second carrier substrate400may be attached to the opposite side of the reconstituted wafer900W relative to the first carrier substrate300. Generally, the second carrier substrate400may comprise any material that may be used for the first carrier substrate300. The thickness of the second carrier substrate400may be in a range from 500 microns to 2,000 microns, although lesser and greater thicknesses may also be used.

The first adhesive layer301may be decomposed by ultraviolet radiation or by a thermal anneal at a debonding temperature. In embodiments in which the first carrier substrate300includes an optically transparent material and the first adhesive layer301includes an LTHC layer, the first adhesive layer301may be decomposed by irradiating ultraviolet light through the transparent carrier substrate. The LTHC layer may be absorb the ultraviolet radiation and generate heat, which decomposes the material of the LTHC layer and cause the transparent first carrier substrate300to be detached from the reconstituted wafer900W. In embodiments in which the first adhesive layer301includes a thermally decomposing adhesive material, a thermal anneal process at a debonding temperature may be performed to detach the first carrier substrate300from the reconstituted wafer900W.

Referring toFIG.10, fan-out bonding pads928and second solder material portions290may be formed by depositing and patterning a stack of at least one metallic material that may function as metallic bumps and a solder material layer. The metallic fill material for the fan-out bonding pads928may include copper. Other suitable materials are within the contemplated scope of disclosure. The thickness of the fan-out bonding pads928may be in a range from 5 microns to 100 microns, although lesser or greater thicknesses may also be used. The fan-out bonding pads928and the second solder material portions290may have horizontal cross-sectional shapes of rectangles, rounded rectangles, or circles. Other suitable shapes are within the contemplated scope of disclosure. In embodiments in which the fan-out bonding pads928are formed as C4 (controlled collapse chip connection) pads, the thickness of the fan-out bonding pads928may be in a range from 5 microns to 50 microns, although lesser or greater thicknesses may also be used. In some embodiments, the fan-out bonding pads928may be, or include, under bump metallurgy (UBM) structures. The configurations of the fan-out bonding pads928are not limited to be fan-out structures. Alternatively, the fan-out bonding pads928may be configured for microbump bonding (i.e., C2 bonding), and may have a thickness in a range from 30 microns to 100 microns, although lesser or greater thicknesses may also be used. In such an embodiment, the fan-out bonding pads928may be formed as an array of microbumps (such as copper pillars) having a lateral dimension in a range from 10 microns to 25 microns, and having a pitch in a range from 20 microns to 50 microns. In some embodiments, the second solder material portions290may be, or include, copper pillars.

The fan-out bonding pads928and the second solder material portions290may be formed on the opposite side of the EMC matrix910M and the two-dimensional array of sets of semiconductor dies (700,800) relative to the redistribution structure layer. The redistribution structure layer includes a three-dimensional array of redistribution structures920. Each redistribution structure920may be located within a respective unit area UA. Each redistribution structure920may comprise redistribution dielectric layers922, redistribution wiring interconnects924embedded in the redistribution dielectric layers922, and fan-out bonding pads928. The fan-out bonding pads928may be located on an opposite side of the redistribution-side bonding structures938relative to the redistribution dielectric layers922, and may be electrically connected to a respective one of the redistribution-side bonding structures938.

Referring toFIG.11, the second adhesive layer401may be decomposed by ultraviolet radiation or by a thermal anneal at a debonding temperature. In embodiments in which the second carrier substrate400includes an optically transparent material and the second adhesive layer401includes an LTHC layer, the second adhesive layer401may be decomposed by irradiating ultraviolet light through the transparent carrier substrate. In embodiments in which the second adhesive layer401includes a thermally decomposing adhesive material, a thermal anneal process at a debonding temperature may be performed to detach the second carrier substrate400from the reconstituted wafer900W.

Referring toFIG.12, the reconstituted wafer900W including the fan-out bonding pads928may be subsequently diced along dicing channels by performing a dicing process. The dicing channels correspond to the boundaries between neighboring pairs of unit areas UA. Each diced unit from the reconstituted wafer900W comprises a fan-out package900. In other words, each diced portion of the assembly of the two-dimensional array of sets of semiconductor dies (700,800), the two-dimensional array of first underfill material portions950, the EMC matrix910M, and the two-dimensional array of redistribution structures920constitutes a fan-out package900. Each diced portion of the EMC matrix910M constitutes a molding compound die frame910. Each diced portion of the redistribution structure layer (which includes the two-dimensional array of redistribution structures920) constitutes a redistribution structure920.

Referring toFIG.13, a fan-out package900obtained by dicing the exemplary structure at the processing steps ofFIG.12is illustrated. The fan-out package900comprises a redistribution structure920including redistribution-side bonding structures938, a plurality of semiconductor dies (700,800) comprising a respective set of die-side bonding structures (780,880) that is attached to a respective subset of the redistribution-side bonding structures938through a respective set of first solder material portions940, a first underfill material portion950laterally surrounding the redistribution-side bonding structures938and the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800), wherein a subset of the redistribution-side bonding structures938is located between a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700,800) in a plan view, i.e., a view along a direction that is perpendicular to an interface between the redistribution structure920and the first underfill material portion950. The fan-out package900may comprise a molding compound die frame910laterally surrounding the plurality of semiconductor dies (700,800) and comprising a molding compound material. In one embodiment, the molding compound die frame910may include sidewalls that are vertically coincident with sidewalls of the redistribution structure920, i.e., located within same vertical planes as the sidewalls of the redistribution structure920. Generally, the molding compound die frame910may be formed around the plurality of semiconductor dies (700,800) after formation of the first underfill material portion950within each fan-out package900. The molding compound material contacts a peripheral portion of a planar surface of the redistribution structure920.

Referring toFIG.14, a package substrate200may be bonded to the fan-out package900through the second solder material portions290. The package substrate200may be a cored package substrate including a core substrate210, or a coreless package substrate that does not include a package core. Alternatively, the package substrate200may include a system-on-integrated package substrate (SoIS) including redistribution layers and/or dielectric interlayers, at least one embedded interposer (such as a silicon interposer). Such a system-integrated package substrate may include layer-to-layer interconnections using solder material portions, microbumps, underfill material portions (such as molded underfill material portions), and/or an adhesion film. While the present disclosure is described using an exemplary substrate package, it is understood that the scope of the present disclosure is not limited by any particular type of substrate package and may include an SoIS. The core substrate210may include a glass epoxy plate including an array of through-plate holes. An array of through-core via structures214including a metallic material may be provided in the through-plate holes. Each through-core via structure214may, or may not, include a cylindrical hollow therein. Optionally, dielectric liners212may be used to electrically isolate the through-core via structures214from the core substrate210.

The package substrate200may include board-side surface laminar circuit (SLC)240and a chip-side surface laminar circuit (SLC)260. The board-side SLC240may include board-side insulating layers242embedding board-side wiring interconnects244. The chip-side SLC260may include chip-side insulating layers262embedding chip-side wiring interconnects264. The board-side insulating layers242and the chip-side insulating layers262may include a photosensitive epoxy material that may be lithographically patterned and subsequently cured. The board-side wiring interconnects244and the chip-side wiring interconnects264may include copper that may be deposited by electroplating within patterns in the board-side insulating layers242or the chip-side insulating layers262.

In one embodiment, the package substrate200includes a chip-side surface laminar circuit260comprising chip-side wiring interconnects264connected to an array of chip-side bonding pads268that is bonded to the array of second solder material portions290, and a board-side surface laminar circuit240including board-side wiring interconnects244connected to an array of board-side bonding pads248. The array of board-side bonding pads248is configured to allow bonding through solder balls. The array of chip-side bonding pads268is configured to allow bonding through C4 solder balls. Generally, any type of package substrate200may be used. While the present disclosure is described using an embodiment in which the package substrate200includes a chip-side surface laminar circuit260and a board-side surface laminar circuit240, embodiments are expressly contemplated herein in which one of the chip-side surface laminar circuit260and the board-side surface laminar circuit240is omitted, or is replaced with an array of bonding structures such as microbumps. In an illustrative example, the chip-side surface laminar circuit260may be replaced with an array of microbumps or any other array of bonding structures.

The second solder material portions290attached to the fan-out bonding pads928of the fan-out package900may be disposed on the array of the chip-side bonding pads268of the package substrate200. A reflow process may be performed to reflow the second solder material portions290, thereby inducing bonding between the fan-out package900and the package substrate200. In one embodiment, the second solder material portions290may include C4 solder balls, and the fan-out package900may be attached to the package substrate200using an array of C4 solder balls.

Referring toFIG.15, a second underfill material portion292may be formed around the second solder material portions290by applying and shaping a second underfill material. The second underfill material portion292may be formed by injecting the second underfill material around the array of second solder material portions290after the second solder material portions290are reflowed. Any known underfill material application method may be used, which may be, for example, the capillary underfill method, the molded underfill method, or the printed underfill method.

The second underfill material portion292may contact each of the second solder material portions290(which may be C4 solder balls or C2 solder caps), and may contact vertical sidewalls of the fan-out package900. The second underfill material portion292is formed between the redistribution structure920and the package substrate200. The second underfill material portion laterally surrounds, and contacts, the array of second solder material portions290and the fan-out package900.

Optionally, a stabilization structure294, such as a cap structure or a ring structure, may be attached to the assembly of the fan-out package900and the package substrate200to reduce deformation of the assembly during subsequent processing steps and/or during usage of the assembly.

Referring toFIG.16, a printed circuit board (PCB)100including a PCB substrate110and PCB bonding pads180may be provided. The PCB100includes a printed circuitry (not shown) at least on one side of the PCB substrate110. An array of solder joints190may be formed to bond the array of board-side bonding pads248to the array of PCB bonding pads180. The solder joints190may be formed by disposing an array of solder balls between the array of board-side bonding pads248and the array of PCB bonding pads180, and by reflowing the array of solder balls. An underfill material portion192may be formed around the solder joints190by applying and shaping an underfill material. The package substrate200is attached to the PCB100through the array of solder joints190.

Referring toFIG.17, a flowchart illustrates steps for forming an exemplary structure according to an embodiment of the present disclosure.

Referring step1710andFIGS.1,2A, and2B, a redistribution structure920including redistribution-side bonding structures938thereupon may be provided.

Referring to step1720andFIGS.3A-6, a plurality of semiconductor dies (700,800) including a respective set of die-side bonding structures (780,880) may be provided.

Referring to step1730andFIGS.3A-6, the plurality of semiconductor dies (700,800) may be bonded to the redistribution structure920using first solder material portions940that are bonded to a respective redistribution-side bonding structure938within a first subset of the redistribution-side bonding structures938and to a respective one of the die-side bonding structures (780,880). A second subset of the redistribution-side bonding structures938(such as the dummy redistribution-side bonding structures938D) is not bonded to any of the plurality of semiconductor dies (700,800).

Referring to step1740andFIGS.7A and7B, a first underfill material portion950may be formed around the first solder material portions940, the redistribution-side bonding structures938, and the die-side bonding structures (780,880).

Referring to all drawings and according to various embodiments of the present disclosure, a fan-out package is provided, which comprises: a redistribution structure920comprising a plurality of first metal bonding structures (such as redistribution-side bonding structures938) on a side; a plurality of semiconductor dies (700,800) comprising a plurality of second metal bonding structures (such as the die-side bonding structures (780,880)) that are attached to the first metal bonding structures938through bump portions (such as the first solder material portions940); and an underfill material portion (such as the first underfill material portion950) laterally surrounding the first metal bonding structures938and the second metal bonding structures (780,880) of the plurality of semiconductor dies (700,800), wherein a subset of the first metal bonding structures938comprises at least one dummy metal bonding structure938D that is surrounded by the underfill material portion950and is electrically isolated from the semiconductor dies (700,800) and the second metal bonding structures (780,880) by the underfill material portion950. Generally, the first metal bonding structures and the second metal bonding structures may comprise any type of bonding structures such as C4 bonding pads or C2 bonding pillars or any other type of metal structures to which a solder material can be bonded.

In one embodiment, at least one dummy metal bonding structure938D is located between a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700,800) in a plan view. In one embodiment, the at least one dummy metal bonding structure938D does not have an areal overlap with any of the plurality of semiconductor dies (700,800) in the plan view.

In one embodiment, the fan-out package comprises at least one dummy bump portion (such as at least one dummy solder material portion940D) located on a respective one of the at least one dummy metal bonding structure938D and not contacting any of the second metal bonding structures (780,880). In one embodiment, all surfaces of the at least one dummy bump portion938D are in contact with the underfill material portion950or the at least one dummy metal bonding structure938D.

In one embodiment, the at least one dummy bump portion938D comprises at least one row of dummy bump portions938D arranged along a direction that is parallel to, and is located between, a pair of sidewalls of a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700,800). In one embodiment, each of the at least one dummy bump portion938D has a same material composition as the bump portions938.

In one embodiment, the fan-out package900may include a molding compound die frame910laterally surrounding the plurality of semiconductor dies (700,800) and comprising a molding compound material. In one embodiment, the molding compound die frame910may include sidewalls that are vertically coincident with sidewalls of the redistribution structure920.

In one embodiment, the redistribution structure920may include: redistribution wiring interconnects924embedded in redistribution dielectric layers922and electrically connected to a respective one of the redistribution-side bonding structures938; and fan-out bonding pads928located on an opposite side of the redistribution-side bonding structures938and electrically connected to a respective one of the redistribution-side bonding structures938.

In one embodiment, the plurality of semiconductor dies (700,800) at least one system-on-chip (SoC) die700; and a memory die800such as a high bandwidth memory (HBM) die810including a vertical stack of static random access memory (SRAM) dies (811,812,813,814,815) that are interconnected to one another through microbumps820and may be laterally surrounded by an epoxy molding material enclosure frame816.

According to an aspect of the present disclosure, a structure including a fan-out package900may be provided, which may include: a redistribution structure920may include redistribution-side bonding structures938; a plurality of semiconductor dies (700,800) which may include a respective set of die-side bonding structures (780,880) that is attached to a respective subset of the redistribution-side bonding structures938through a respective set of solder material portions940; and an underfill material portion950laterally surrounding the redistribution-side bonding structures938and the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800), wherein a subset of the redistribution-side bonding structures938(such as the dummy redistribution-side bonding structures938D) is not bonded to any of the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800) and is laterally surrounded by the first underfill material portion950.

In one embodiment, the subset of the redistribution-side bonding structures938(such as the dummy redistribution-side bonding structures938D) is located between a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700,800) in a plan view. In one embodiment, the subset of the redistribution-side bonding structures938(such as the dummy redistribution-side bonding structures938D) does not have an areal overlap with any of the plurality of semiconductor dies (700,800) in the plan view.

In one embodiment, the fan-out package may include dummy solder material portions940D located on a respective redistribution-side bonding structure938(such as a dummy redistribution-side bonding structure938D) selected from the subset of the redistribution-side bonding structures938. In some embodiments, the dummy solder material portions940D and the dummy redistribution-side bonding structures938D may not contact and/or be electrically connected to any of the plurality of semiconductor dies (700,800).

In one embodiment, all surfaces of the dummy solder material portions940D may be in contact with the first underfill material portion950or the subset of the redistribution-side bonding structures938(such as the dummy redistribution-side bonding structures938D). In one embodiment, the dummy solder material portions940D may include at least one row of dummy solder material portions940D arranged along a direction that is parallel to, and may be located between, a pair of sidewalls of a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700,800). In one embodiment, each of the dummy solder material portions940D may have a same material composition as the sets of solder material portions940.

According to an aspect of the present disclosure, a chip package structure is provided, which may include: a fan-out package900including a redistribution structure920comprising redistribution-side bonding structures938, a plurality of semiconductor dies (700,800) may include a respective set of die-side bonding structures (780,880) that may be attached to a respective subset of the redistribution-side bonding structures938through a respective set of first solder material portions940, a first underfill material portion950laterally surrounding the redistribution-side bonding structures938and the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800), wherein a subset of the redistribution-side bonding structures938(such as the dummy redistribution-side bonding structures938D) may be located between a neighboring pair of semiconductor dies (700,800) selected from the plurality of semiconductor dies (700,800) in a plan view; and a package substrate200that is attached to the fan-out package900via an array of second solder material portions290.

In one embodiment, the chip package structure may include a molding compound die frame910laterally surrounding the plurality of semiconductor dies (700,800) and may include a molding compound material that contacts a peripheral portion of a planar surface of the redistribution structure920.

In one embodiment, the chip package structure may include a second underfill material portion292laterally surrounding the array of second solder material portions290and the fan-out package900.

In one embodiment, the subset of the redistribution-side bonding structures938(such as the dummy redistribution-side bonding structures938) is not bonded to any of the die-side bonding structures (780,880) of the plurality of semiconductor dies (700,800), and may be laterally surrounded by, and contacts, the first underfill material portion950.

The various structures and methods of the present disclosure may be used to provide a chip package structure including a fan-out package900including dummy redistribution-side bonding structures938D and dummy solder material portions940D that modify the pattern of conduits for an underfill material and increases the capillary force for the underfill material. The various methods and structures of the present disclosure may be used to reduce or eliminate voids in the first underfill material portion950and to increase the reliability of the fan-out package900.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.