Patent ID: 12229558

DETAILED DESCRIPTION

The following description describes an instruction and processing logic for tracking performance bottlenecks in association with a processor, virtual processor, package, computer system, or other processing apparatus. In one embodiment, such bottlenecks may be associated with the fetching of instructions. In the following description, numerous specific details such as processing logic, processor types, micro-architectural conditions, events, enablement mechanisms, and the like are set forth in order to provide a more thorough understanding of embodiments of the present disclosure. It will be appreciated, however, by one skilled in the art that the embodiments may be practiced without such specific details. Additionally, some well-known structures, circuits, and the like have not been shown in detail to avoid unnecessarily obscuring embodiments of the present disclosure.

Although the following embodiments are described with reference to a processor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments of the present disclosure may be applied to other types of circuits or semiconductor devices that may benefit from higher pipeline throughput and improved performance. The teachings of embodiments of the present disclosure are applicable to any processor or machine that performs data manipulations. However, the embodiments are not limited to processors or machines that perform 512-bit, 256-bit, 128-bit, 64-bit, 32-bit, or 16-bit data operations and may be applied to any processor and machine in which manipulation or management of data may be performed. In addition, the following description provides examples, and the accompanying drawings show various examples for the purposes of illustration. However, these examples should not be construed in a limiting sense as they are merely intended to provide examples of embodiments of the present disclosure rather than to provide an exhaustive list of all possible implementations of embodiments of the present disclosure.

Although the below examples describe instruction handling and distribution in the context of execution units and logic circuits, other embodiments of the present disclosure may be accomplished by way of a data or instructions stored on a machine-readable, tangible medium, which when performed by a machine cause the machine to perform functions consistent with at least one embodiment of the disclosure. In one embodiment, functions associated with embodiments of the present disclosure are embodied in machine-executable instructions. The instructions may be used to cause a general-purpose or special-purpose processor that may be programmed with the instructions to perform the steps of the present disclosure. Embodiments of the present disclosure may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform one or more operations according to embodiments of the present disclosure. Furthermore, steps of embodiments of the present disclosure might be performed by specific hardware components that contain fixed-function logic for performing the steps, or by any combination of programmed computer components and fixed-function hardware components.

Instructions used to program logic to perform embodiments of the present disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions may be distributed via a network or by way of other computer-readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Discs, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium may include any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as may be useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, designs, at some stage, may reach a level of data representing the physical placement of various devices in the hardware model. In cases wherein some semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine-readable medium. A memory or a magnetic or optical storage such as a disc may be the machine-readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or retransmission of the electrical signal is performed, a new copy may be made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

In modem processors, a number of different execution units may be used to process and execute a variety of code and instructions. Some instructions may be quicker to complete while others may take a number of clock cycles to complete. The faster the throughput of instructions, the better the overall performance of the processor. Thus it would be advantageous to have as many instructions execute as fast as possible. However, there may be certain instructions that have greater complexity and require more in terms of execution time and processor resources, such as floating point instructions, load/store operations, data moves, etc.

As more computer systems are used in internet, text, and multimedia applications, additional processor support has been introduced over time. In one embodiment, an instruction set may be associated with one or more computer architectures, including data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O).

In one embodiment, the instruction set architecture (ISA) may be implemented by one or more micro-architectures, which may include processor logic and circuits used to implement one or more instruction sets. Accordingly, processors with different micro-architectures may share at least a portion of a common instruction set. For example, Intel® Pentium 4 processors, Intel® Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale CA implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. Similarly, processors designed by other processor development companies, such as ARM Holdings, Ltd., MIPS, or their licensees or adopters, may share at least a portion a common instruction set, but may include different processor designs. For example, the same register architecture of the ISA may be implemented in different ways in different micro-architectures using new or well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file. In one embodiment, registers may include one or more registers, register architectures, register files, or other register sets that may or may not be addressable by a software programmer.

An instruction may include one or more instruction formats. In one embodiment, an instruction format may indicate various fields (number of bits, location of bits, etc.) to specify, among other things, the operation to be performed and the operands on which that operation will be performed. In a further embodiment, some instruction formats may be further defined by instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields and/or defined to have a given field interpreted differently. In one embodiment, an instruction may be expressed using an instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and specifies or indicates the operation and the operands upon which the operation will operate.

Scientific, financial, auto-vectorized general purpose, RMS (recognition, mining, and synthesis), and visual and multimedia applications (e.g., 2D/3D graphics, image processing, video compression/decompression, voice recognition algorithms and audio manipulation) may require the same operation to be performed on a large number of data items. In one embodiment, Single Instruction Multiple Data (SIMD) refers to a type of instruction that causes a processor to perform an operation on multiple data elements. SIMD technology may be used in processors that may logically divide the bits in a register into a number of fixed-sized or variable-sized data elements, each of which represents a separate value. For example, in one embodiment, the bits in a 64-bit register may be organized as a source operand containing four separate 16-bit data elements, each of which represents a separate 16-bit value. This type of data may be referred to as ‘packed’ data type or ‘vector’ data type, and operands of this data type may be referred to as packed data operands or vector operands. In one embodiment, a packed data item or vector may be a sequence of packed data elements stored within a single register, and a packed data operand or a vector operand may a source or destination operand of a SIMD instruction (or ‘packed data instruction’ or a ‘vector instruction’). In one embodiment, a SIMD instruction specifies a single vector operation to be performed on two source vector operands to generate a destination vector operand (also referred to as a result vector operand) of the same or different size, with the same or different number of data elements, and in the same or different data element order.

SIMD technology, such as that employed by the Intel® Core™ processors having an instruction set including x86, MMX™, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSE4.1, and SSE4.2 instructions, ARM processors, such as the ARM Cortex® family of processors having an instruction set including the Vector Floating Point (VFP) and/or NEON instructions, and MIPS processors, such as the Loongson family of processors developed by the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences, has enabled a significant improvement in application performance (Core™ and MMX™ are registered trademarks or trademarks of Intel Corporation of Santa Clara, Calif.).

In one embodiment, destination and source registers/data may be generic terms to represent the source and destination of the corresponding data or operation. In some embodiments, they may be implemented by registers, memory, or other storage areas having other names or functions than those depicted. For example, in one embodiment, “DEST1” may be a temporary storage register or other storage area, whereas “SRC1” and “SRC2” may be a first and second source storage register or other storage area, and so forth. In other embodiments, two or more of the SRC and DEST storage areas may correspond to different data storage elements within the same storage area (e.g., a SIMD register). In one embodiment, one of the source registers may also act as a destination register by, for example, writing back the result of an operation performed on the first and second source data to one of the two source registers serving as a destination registers.

FIG.1Ais a block diagram of an exemplary computer system formed with a processor that may include execution units to execute an instruction, in accordance with embodiments of the present disclosure. System100may include a component, such as a processor102to employ execution units including logic to perform algorithms for process data, in accordance with the present disclosure, such as in the embodiment described herein. System100may be representative of processing systems based on the PENTIUM® III, PENTIUM® 4, Xeon™, Itanium®, XScale™ and/or StrongARM™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and the like) may also be used. In one embodiment, sample system100may execute a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used. Thus, embodiments of the present disclosure are not limited to any specific combination of hardware circuitry and software.

Embodiments are not limited to computer systems. Embodiments of the present disclosure may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include a micro controller, a digital signal processor (DSP), system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment.

Computer system100may include a processor102that may include one or more execution units108to perform an algorithm to perform at least one instruction in accordance with one embodiment of the present disclosure. One embodiment may be described in the context of a single processor desktop or server system, but other embodiments may be included in a multiprocessor system. System100may be an example of a ‘hub’ system architecture. System100may include a processor102for processing data signals. Processor102may include a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In one embodiment, processor102may be coupled to a processor bus110that may transmit data signals between processor102and other components in system100. The elements of system100may perform conventional functions that are well known to those familiar with the art.

In one embodiment, processor102may include a Level 1 (L1) internal cache memory104. Depending on the architecture, the processor102may have a single internal cache or multiple levels of internal cache. In another embodiment, the cache memory may reside external to processor102. Other embodiments may also include a combination of both internal and external caches depending on the particular implementation and needs. Register file106may store different types of data in various registers including integer registers, floating point registers, status registers, and instruction pointer register.

Execution unit108, including logic to perform integer and floating point operations, also resides in processor102. Processor102may also include a microcode (ucode) ROM that stores microcode for certain macroinstructions. In one embodiment, execution unit108may include logic to handle a packed instruction set109. By including the packed instruction set109in the instruction set of a general-purpose processor102, along with associated circuitry to execute the instructions, the operations used by many multimedia applications may be performed using packed data in a general-purpose processor102. Thus, many multimedia applications may be accelerated and executed more efficiently by using the full width of a processor's data bus for performing operations on packed data. This may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

Embodiments of an execution unit108may also be used in micro controllers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System100may include a memory120. Memory120may be implemented as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, flash memory device, or other memory device. Memory120may store instructions and/or data represented by data signals that may be executed by processor102.

A system logic chip116may be coupled to processor bus110and memory120. System logic chip116may include a memory controller hub (MCH). Processor102may communicate with MCH116via a processor bus110. MCH116may provide a high bandwidth memory path118to memory120for instruction and data storage and for storage of graphics commands, data and textures. MCH116may direct data signals between processor102, memory120, and other components in system100and to bridge the data signals between processor bus110, memory120, and system I/O122. In some embodiments, the system logic chip116may provide a graphics port for coupling to a graphics controller112. MCH116may be coupled to memory120through a memory interface118. Graphics card112may be coupled to MCH116through an Accelerated Graphics Port (AGP) interconnect114.

System100may use a proprietary hub interface bus122to couple MCH116to I/O controller hub (ICH)130. In one embodiment, ICH130may provide direct connections to some I/O devices via a local I/O bus. The local I/O bus may include a high-speed I/O bus for connecting peripherals to memory120, chipset, and processor102. Examples may include the audio controller, firmware hub (flash BIOS)128, wireless transceiver126, data storage124, legacy I/O controller containing user input and keyboard interfaces, a serial expansion port such as Universal Serial Bus (USB), and a network controller134. Data storage device124may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

For another embodiment of a system, an instruction in accordance with one embodiment may be used with a system on a chip. One embodiment of a system on a chip comprises of a processor and a memory. The memory for one such system may include a flash memory. The flash memory may be located on the same die as the processor and other system components. Additionally, other logic blocks such as a memory controller or graphics controller may also be located on a system on a chip.

FIG.1Billustrates a data processing system140which implements the principles of embodiments of the present disclosure. It will be readily appreciated by one of skill in the art that the embodiments described herein may operate with alternative processing systems without departure from the scope of embodiments of the disclosure.

Computer system140comprises a processing core159for performing at least one instruction in accordance with one embodiment. In one embodiment, processing core159represents a processing unit of any type of architecture, including but not limited to a CISC, a RISC or a VLIW-type architecture. Processing core159may also be suitable for manufacture in one or more process technologies and by being represented on a machine-readable media in sufficient detail, may be suitable to facilitate said manufacture.

Processing core159comprises an execution unit142, a set of register files145, and a decoder144. Processing core159may also include additional circuitry (not shown) which may be unnecessary to the understanding of embodiments of the present disclosure. Execution unit142may execute instructions received by processing core159. In addition to performing typical processor instructions, execution unit142may perform instructions in packed instruction set143for performing operations on packed data formats. Packed instruction set143may include instructions for performing embodiments of the disclosure and other packed instructions. Execution unit142may be coupled to register file145by an internal bus. Register file145may represent a storage area on processing core159for storing information, including data. As previously mentioned, it is understood that the storage area may store the packed data might not be critical. Execution unit142may be coupled to decoder144. Decoder144may decode instructions received by processing core159into control signals and/or microcode entry points. In response to these control signals and/or microcode entry points, execution unit142performs the appropriate operations. In one embodiment, the decoder may interpret the opcode of the instruction, which will indicate what operation should be performed on the corresponding data indicated within the instruction.

Processing core159may be coupled with bus141for communicating with various other system devices, which may include but are not limited to, for example, Synchronous Dynamic Random Access Memory (SDRAM) control146, Static Random Access Memory (SRAM) control147, burst flash memory interface148, Personal Computer Memory Card International Association (PCMCIA)/Compact Flash (CF) card control149, Liquid Crystal Display (LCD) control150, Direct Memory Access (DMA) controller151, and alternative bus master interface152. In one embodiment, data processing system140may also comprise an I/O bridge154for communicating with various I/O devices via an I/O bus153. Such I/O devices may include but are not limited to, for example, Universal Asynchronous Receiver/Transmitter (UART)155, Universal Serial Bus (USB)156, Bluetooth wireless UART157and I/O expansion interface158.

One embodiment of data processing system140provides for mobile, network and/or wireless communications and a processing core159that may perform SIMD operations including a text string comparison operation. Processing core159may be programmed with various audio, video, imaging and communications algorithms including discrete transformations such as a Walsh-Hadamard transform, a fast Fourier transform (FFT), a discrete cosine transform (DCT), and their respective inverse transforms; compression/decompression techniques such as color space transformation, video encode motion estimation or video decode motion compensation; and modulation/demodulation (MODEM) functions such as pulse coded modulation (PCM).

FIG.1Cillustrates other embodiments of a data processing system that performs SIMD text string comparison operations. In one embodiment, data processing system160may include a main processor166, a SIMD coprocessor161, a cache memory167, and an input/output system168. Input/output system168may optionally be coupled to a wireless interface169. SIMD coprocessor161may perform operations including instructions in accordance with one embodiment. In one embodiment, processing core170may be suitable for manufacture in one or more process technologies and by being represented on a machine-readable media in sufficient detail, may be suitable to facilitate the manufacture of all or part of data processing system160including processing core170.

In one embodiment, SIMD coprocessor161comprises an execution unit162and a set of register files164. One embodiment of main processor165comprises a decoder165to recognize instructions of instruction set163including instructions in accordance with one embodiment for execution by execution unit162. In other embodiments, SIMD coprocessor161also comprises at least part of decoder165to decode instructions of instruction set163. Processing core170may also include additional circuitry (not shown) which may be unnecessary to the understanding of embodiments of the present disclosure.

In operation, main processor166executes a stream of data processing instructions that control data processing operations of a general type including interactions with cache memory167, and input/output system168. Embedded within the stream of data processing instructions may be SIMD coprocessor instructions. Decoder165of main processor166recognizes these SIMD coprocessor instructions as being of a type that should be executed by an attached SIMD coprocessor161. Accordingly, main processor166issues these SIMD coprocessor instructions (or control signals representing SIMD coprocessor instructions) on the coprocessor bus166. From coprocessor bus166, these instructions may be received by any attached SIMD coprocessors. In this case, SIMD coprocessor161may accept and execute any received SIMD coprocessor instructions intended for it.

Data may be received via wireless interface169for processing by the SIMD coprocessor instructions. For one example, voice communication may be received in the form of a digital signal, which may be processed by the SIMD coprocessor instructions to regenerate digital audio samples representative of the voice communications. For another example, compressed audio and/or video may be received in the form of a digital bit stream, which may be processed by the SIMD coprocessor instructions to regenerate digital audio samples and/or motion video frames. In one embodiment of processing core170, main processor166, and a SIMD coprocessor161may be integrated into a single processing core170comprising an execution unit162, a set of register files164, and a decoder165to recognize instructions of instruction set163including instructions in accordance with one embodiment.

FIG.2is a block diagram of the micro-architecture for a processor200that may include logic circuits to perform instructions, in accordance with embodiments of the present disclosure. In some embodiments, an instruction in accordance with one embodiment may be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as datatypes, such as single and double precision integer and floating point datatypes. In one embodiment, in-order front end201may implement a part of processor200that may fetch instructions to be executed and prepares the instructions to be used later in the processor pipeline. Front end201may include several units. In one embodiment, instruction prefetcher226fetches instructions from memory and feeds the instructions to an instruction decoder228which in turn decodes or interprets the instructions. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine may execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, trace cache230may assemble decoded uops into program ordered sequences or traces in uop queue234for execution. When trace cache230encounters a complex instruction, microcode ROM232provides the uops needed to complete the operation.

Some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, decoder228may access microcode ROM232to perform the instruction. In one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder228. In another embodiment, an instruction may be stored within microcode ROM232should a number of micro-ops be needed to accomplish the operation. Trace cache230refers to an entry point programmable logic array (PLA) to determine a correct micro-instruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from micro-code ROM232. After microcode ROM232finishes sequencing micro-ops for an instruction, front end201of the machine may resume fetching micro-ops from trace cache230.

Out-of-order execution engine203may prepare instructions for execution. The out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler202, slow/general floating point scheduler204, and simple floating point scheduler206. Uop schedulers202,204,206, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation. Fast scheduler202of one embodiment may schedule on each half of the main clock cycle while the other schedulers may only schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

Register files208,210may be arranged between schedulers202,204,206, and execution units212,214,216,218,220,222,224in execution block211. Each of register files208,210perform integer and floating point operations, respectively. Each register file208,210, may include a bypass network that may bypass or forward just completed results that have not yet been written into the register file to new dependent uops. Integer register file208and floating point register file210may communicate data with the other. In one embodiment, integer register file208may be split into two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. Floating point register file210may include 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

Execution block211may contain execution units212,214,216,218,220,222,224. Execution units212,214,216,218,220,222,224may execute the instructions. Execution block211may include register files208,210that store the integer and floating point data operand values that the micro-instructions need to execute. In one embodiment, processor200may comprise a number of execution units: address generation unit (AGU)212, AGU214, fast Arithmetic Logic Unit (ALU)216, fast ALU218, slow ALU220, floating point ALU222, floating point move unit224. In another embodiment, floating point execution blocks222,224, may execute floating point, MMX, SIMD, and SSE, or other operations. In yet another embodiment, floating point ALU222may include a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro-ops. In various embodiments, instructions involving a floating point value may be handled with the floating point hardware. In one embodiment, ALU operations may be passed to high-speed ALU execution units216,218. High-speed ALUs216,218may execute fast operations with an effective latency of half a clock cycle. In one embodiment, most complex integer operations go to slow ALU220as slow ALU220may include integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. Memory load/store operations may be executed by AGUs212,214. In one embodiment, integer ALUs216,218,220may perform integer operations on 64-bit data operands. In other embodiments, ALUs216,218,220may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. Similarly, floating point units222,224may be implemented to support a range of operands having bits of various widths. In one embodiment, floating point units222,224, may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, uops schedulers202,204,206, dispatch dependent operations before the parent load has finished executing. As uops may be speculatively scheduled and executed in processor200, processor200may also include logic to handle memory misses. If a data load misses in the data cache, there may be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations might need to be replayed and the independent ones may be allowed to complete. The schedulers and replay mechanism of one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations.

The term “registers” may refer to the on-board processor storage locations that may be used as part of instructions to identify operands. In other words, registers may be those that may be usable from the outside of the processor (from a programmer's perspective). However, in some embodiments registers might not be limited to a particular type of circuit. Rather, a register may store data, provide data, and perform the functions described herein. The registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store 32-bit integer data. A register file of one embodiment also contains eight multimedia SIMD registers for packed data. For the discussions below, the registers may be understood to be data registers designed to hold packed data, such as 64-bit wide MMX™ registers (also referred to as ‘mm’ registers in some instances) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. These MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not need to differentiate between the two data types. In one embodiment, integer and floating point may be contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

In the examples of the following figures, a number of data operands may be described.FIG.3Aillustrates various packed data type representations in multimedia registers, in accordance with embodiments of the present disclosure.FIG.3Aillustrates data types for a packed byte310, a packed word320, and a packed doubleword (dword)330for 128-bit wide operands. Packed byte format310of this example may be 128 bits long and contains sixteen packed byte data elements. A byte may be defined, for example, as eight bits of data. Information for each byte data element may be stored in bit 7 through bit 0 for byte 0, bit 15 through bit 8 for byte 1, bit 23 through bit 16 for byte 2, and finally bit 120 through bit 127 for byte 15. Thus, all available bits may be used in the register. This storage arrangement increases the storage efficiency of the processor. As well, with sixteen data elements accessed, one operation may now be performed on sixteen data elements in parallel.

Generally, a data element may include an individual piece of data that is stored in a single register or memory location with other data elements of the same length. In packed data sequences relating to SSEx technology, the number of data elements stored in a XMM register may be 128 bits divided by the length in bits of an individual data element. Similarly, in packed data sequences relating to MMX and SSE technology, the number of data elements stored in an MMX register may be 64 bits divided by the length in bits of an individual data element. Although the data types illustrated inFIG.3Amay be 128 bits long, embodiments of the present disclosure may also operate with 64-bit wide or other sized operands. Packed word format320of this example may be 128 bits long and contains eight packed word data elements. Each packed word contains sixteen bits of information. Packed doubleword format330ofFIG.3Amay be 128 bits long and contains four packed doubleword data elements. Each packed doubleword data element contains thirty-two bits of information. A packed quadword may be 128 bits long and contain two packed quad-word data elements.

FIG.3Billustrates possible in-register data storage formats, in accordance with embodiments of the present disclosure. Each packed data may include more than one independent data element. Three packed data formats are illustrated; packed half341, packed single342, and packed double343. One embodiment of packed half341, packed single342, and packed double343contain fixed-point data elements. For another embodiment one or more of packed half341, packed single342, and packed double343may contain floating-point data elements. One embodiment of packed half341may be 128 bits long containing eight 16-bit data elements. One embodiment of packed single342may be 128 bits long and contains four 32-bit data elements. One embodiment of packed double343may be 128 bits long and contains two 64-bit data elements. It will be appreciated that such packed data formats may be further extended to other register lengths, for example, to 96-bits, 160-bits, 192-bits, 224-bits, 256-bits or more.

FIG.3Cillustrates various signed and unsigned packed data type representations in multimedia registers, in accordance with embodiments of the present disclosure. Unsigned packed byte representation344illustrates the storage of an unsigned packed byte in a SIMD register. Information for each byte data element may be stored in bit 7 through bit 0 for byte 0, bit 15 through bit 8 for byte 1, bit 23 through bit 16 for byte 2, and finally bit 120 through bit 127 for byte 15. Thus, all available bits may be used in the register. This storage arrangement may increase the storage efficiency of the processor. As well, with sixteen data elements accessed, one operation may now be performed on sixteen data elements in a parallel fashion. Signed packed byte representation345illustrates the storage of a signed packed byte. Note that the eighth bit of every byte data element may be the sign indicator. Unsigned packed word representation346illustrates how word seven through word zero may be stored in a SIMD register. Signed packed word representation347may be similar to the unsigned packed word in-register representation346. Note that the sixteenth bit of each word data element may be the sign indicator. Unsigned packed doubleword representation348shows how doubleword data elements are stored. Signed packed doubleword representation349may be similar to unsigned packed doubleword in-register representation348. Note that the necessary sign bit may be the thirty-second bit of each doubleword data element.

FIG.3Dillustrates an embodiment of an operation encoding (opcode). Furthermore, format360may include register/memory operand addressing modes corresponding with a type of opcode format described in the “IA-32 Intel Architecture Software Developer's Manual Volume 2: Instruction Set Reference,” which is available from Intel Corporation, Santa Clara, CA on the world-wide-web (www) at intel.com/design/litcentr. In one embodiment, an instruction may be encoded by one or more of fields361and362. Up to two operand locations per instruction may be identified, including up to two source operand identifiers364and365. In one embodiment, destination operand identifier366may be the same as source operand identifier364, whereas in other embodiments they may be different. In another embodiment, destination operand identifier366may be the same as source operand identifier365, whereas in other embodiments they may be different. In one embodiment, one of the source operands identified by source operand identifiers364and365may be overwritten by the results of the text string comparison operations, whereas in other embodiments identifier364corresponds to a source register element and identifier365corresponds to a destination register element. In one embodiment, operand identifiers364and365may identify 32-bit or 64-bit source and destination operands.

FIG.3Eillustrates another possible operation encoding (opcode) format370, having forty or more bits, in accordance with embodiments of the present disclosure. Opcode format370corresponds with opcode format360and comprises an optional prefix byte378. An instruction according to one embodiment may be encoded by one or more of fields378,371, and372. Up to two operand locations per instruction may be identified by source operand identifiers374and375and by prefix byte378. In one embodiment, prefix byte378may be used to identify 32-bit or 64-bit source and destination operands. In one embodiment, destination operand identifier376may be the same as source operand identifier374, whereas in other embodiments they may be different. For another embodiment, destination operand identifier376may be the same as source operand identifier375, whereas in other embodiments they may be different. In one embodiment, an instruction operates on one or more of the operands identified by operand identifiers374and375and one or more operands identified by operand identifiers374and375may be overwritten by the results of the instruction, whereas in other embodiments, operands identified by identifiers374and375may be written to another data element in another register. Opcode formats360and370allow register to register, memory to register, register by memory, register by register, register by immediate, register to memory addressing specified in part by MOD fields363and373and by optional scale-index-base and displacement bytes.

FIG.3Fillustrates yet another possible operation encoding (opcode) format, in accordance with embodiments of the present disclosure. 64-bit single instruction multiple data (SIMD) arithmetic operations may be performed through a coprocessor data processing (CDP) instruction. Operation encoding (opcode) format380depicts one such CDP instruction having CDP opcode fields382-389. The type of CDP instruction, for another embodiment, operations may be encoded by one or more of fields383,384,387, and388. Up to three operand locations per instruction may be identified, including up to two source operand identifiers385and390and one destination operand identifier386. One embodiment of the coprocessor may operate on eight, sixteen, thirty-two, and 64-bit values. In one embodiment, an instruction may be performed on integer data elements. In some embodiments, an instruction may be executed conditionally, using condition field381. For some embodiments, source data sizes may be encoded by field383. In some embodiments, Zero (Z), negative (N), carry (C), and overflow (V) detection may be done on SIMD fields. For some instructions, the type of saturation may be encoded by field384.

FIG.4Ais a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline, in accordance with embodiments of the present disclosure.FIG.4Bis a block diagram illustrating an in-order architecture core and a register renaming logic, out-of-order issue/execution logic to be included in a processor, in accordance with embodiments of the present disclosure. The solid lined boxes inFIG.4Aillustrate the in-order pipeline, while the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline. Similarly, the solid lined boxes inFIG.4Billustrate the in-order architecture logic, while the dashed lined boxes illustrates the register renaming logic and out-of-order issue/execution logic.

InFIG.4A, a processor pipeline400may include a fetch stage402, a length decode stage404, a decode stage406, an allocation stage408, a renaming stage410, a scheduling (also known as a dispatch or issue) stage412, a register read/memory read stage414, an execute stage416, a write-back/memory-write stage418, an exception handling stage422, and a commit stage424.

InFIG.4B, arrows denote a coupling between two or more units and the direction of the arrow indicates a direction of data flow between those units.FIG.4Bshows processor core490including a front end unit430coupled to an execution engine unit450, and both may be coupled to a memory unit470.

Core490may be a Reduced Instruction Set Computing (RISC) core, a Complex Instruction Set Computing (CISC) core, a Very Long Instruction Word (VLIW) core, or a hybrid or alternative core type. In one embodiment, core490may be a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like.

Front end unit430may include a branch prediction unit432coupled to an instruction cache unit434. Instruction cache unit434may be coupled to an instruction Translation Lookaside Buffer (TLB)436. TLB436may be coupled to an instruction fetch unit438, which is coupled to a decode unit440. Decode unit440may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which may be decoded from, or which otherwise reflect, or may be derived from, the original instructions. The decoder may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one embodiment, instruction cache unit434may be further coupled to a level 2 (L2) cache unit476in memory unit470. Decode unit440may be coupled to a rename/allocator unit452in execution engine unit450.

Execution engine unit450may include rename/allocator unit452coupled to a retirement unit454and a set of one or more scheduler units456. Scheduler units456represent any number of different schedulers, including reservations stations, central instruction window, etc. Scheduler units456may be coupled to physical register file units458. Each of physical register file units458represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. Physical register file units458may be overlapped by retirement unit154to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using one or more reorder buffers and one or more retirement register files, using one or more future files, one or more history buffers, and one or more retirement register files; using register maps and a pool of registers; etc.). Generally, the architectural registers may be visible from the outside of the processor or from a programmer's perspective. The registers might not be limited to any known particular type of circuit. Various different types of registers may be suitable as long as they store and provide data as described herein. Examples of suitable registers include, but might not be limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. Retirement unit454and physical register file units458may be coupled to execution clusters460. Execution clusters460may include a set of one or more execution units162and a set of one or more memory access units464. Execution units462may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scheduler units456, physical register file units458, and execution clusters460are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments may be implemented in which only the execution cluster of this pipeline has memory access units464). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units464may be coupled to memory unit470, which may include a data TLB unit472coupled to a data cache unit474coupled to a level 2 (L2) cache unit476. In one exemplary embodiment, memory access units464may include a load unit, a store address unit, and a store data unit, each of which may be coupled to data TLB unit472in memory unit470. L2 cache unit476may be coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement pipeline400as follows: 1) instruction fetch438may perform fetch and length decoding stages402and404; 2) decode unit440may perform decode stage406; 3) rename/allocator unit452may perform allocation stage408and renaming stage410; 4) scheduler units456may perform schedule stage412; 5) physical register file units458and memory unit470may perform register read/memory read stage414; execution cluster460may perform execute stage416; 6) memory unit470and physical register file units458may perform write-back/memory-write stage418; 7) various units may be involved in the performance of exception handling stage422; and 8) retirement unit454and physical register file units458may perform commit stage424.

Core490may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA).

It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads) in a variety of manners. Multithreading support may be performed by, for example, including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof. Such a combination may include, for example, time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology.

While register renaming may be described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor may also include a separate instruction and data cache units434/474and a shared L2 cache unit476, other embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that may be external to the core and/or the processor. In other embodiments, all of the cache may be external to the core and/or the processor.

FIG.5Ais a block diagram of a processor500, in accordance with embodiments of the present disclosure. In one embodiment, processor500may include a multicore processor. Processor500may include a system agent510communicatively coupled to one or more cores502. Furthermore, cores502and system agent510may be communicatively coupled to one or more caches506. Cores502, system agent510, and caches506may be communicatively coupled via one or more memory control units552. Furthermore, cores502, system agent510, and caches506may be communicatively coupled to a graphics module560via memory control units552.

Processor500may include any suitable mechanism for interconnecting cores502, system agent510, and caches506, and graphics module560. In one embodiment, processor500may include a ring-based interconnect unit508to interconnect cores502, system agent510, and caches506, and graphics module560. In other embodiments, processor500may include any number of well-known techniques for interconnecting such units. Ring-based interconnect unit508may utilize memory control units552to facilitate interconnections.

Processor500may include a memory hierarchy comprising one or more levels of caches within the cores, one or more shared cache units such as caches506, or external memory (not shown) coupled to the set of integrated memory controller units552. Caches506may include any suitable cache. In one embodiment, caches506may include one or more mid-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

In various embodiments, one or more of cores502may perform multi-threading. System agent510may include components for coordinating and operating cores502. System agent unit510may include for example a Power Control Unit (PCU). The PCU may be or include logic and components needed for regulating the power state of cores502. System agent510may include a display engine512for driving one or more externally connected displays or graphics module560. System agent510may include an interface1214for communications busses for graphics. In one embodiment, interface1214may be implemented by PCI Express (PCIe). In a further embodiment, interface1214may be implemented by PCI Express Graphics (PEG). System agent510may include a direct media interface (DMI)516. DMI516may provide links between different bridges on a motherboard or other portion of a computer system. System agent510may include a PCIe bridge1218for providing PCIe links to other elements of a computing system. PCIe bridge1218may be implemented using a memory controller1220and coherence logic1222.

Cores502may be implemented in any suitable manner. Cores502may be homogenous or heterogeneous in terms of architecture and/or instruction set. In one embodiment, some of cores502may be in-order while others may be out-of-order. In another embodiment, two or more of cores502may execute the same instruction set, while others may execute only a subset of that instruction set or a different instruction set.

Processor500may include a general-purpose processor, such as a Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, XScale™ or StrongARM™ processor, which may be available from Intel Corporation, of Santa Clara, Calif. Processor500may be provided from another company, such as ARM Holdings, Ltd, MIPS, etc. Processor500may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. Processor500may be implemented on one or more chips. Processor500may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

In one embodiment, a given one of caches506may be shared by multiple ones of cores502. In another embodiment, a given one of caches506may be dedicated to one of cores502. The assignment of caches506to cores502may be handled by a cache controller or other suitable mechanism. A given one of caches506may be shared by two or more cores502by implementing time-slices of a given cache506.

Graphics module560may implement an integrated graphics processing subsystem. In one embodiment, graphics module560may include a graphics processor. Furthermore, graphics module560may include a media engine565. Media engine565may provide media encoding and video decoding.

FIG.5Bis a block diagram of an example implementation of a core502, in accordance with embodiments of the present disclosure. Core502may include a front end570communicatively coupled to an out-of-order engine580. Core502may be communicatively coupled to other portions of processor500through cache hierarchy503.

Front end570may be implemented in any suitable manner, such as fully or in part by front end201as described above. In one embodiment, front end570may communicate with other portions of processor500through cache hierarchy503. In a further embodiment, front end570may fetch instructions from portions of processor500and prepare the instructions to be used later in the processor pipeline as they are passed to out-of-order execution engine580.

Out-of-order execution engine580may be implemented in any suitable manner, such as fully or in part by out-of-order execution engine203as described above. Out-of-order execution engine580may prepare instructions received from front end570for execution. Out-of-order execution engine580may include an allocate module1282. In one embodiment, allocate module1282may allocate resources of processor500or other resources, such as registers or buffers, to execute a given instruction. Allocate module1282may make allocations in schedulers, such as a memory scheduler, fast scheduler, or floating point scheduler. Such schedulers may be represented inFIG.5Bby resource schedulers584. Allocate module1282may be implemented fully or in part by the allocation logic described in conjunction withFIG.2. Resource schedulers584may determine when an instruction is ready to execute based on the readiness of a given resource's sources and the availability of execution resources needed to execute an instruction. Resource schedulers584may be implemented by, for example, schedulers202,204,206as discussed above. Resource schedulers584may schedule the execution of instructions upon one or more resources. In one embodiment, such resources may be internal to core502, and may be illustrated, for example, as resources586. In another embodiment, such resources may be external to core502and may be accessible by, for example, cache hierarchy503. Resources may include, for example, memory, caches, register files, or registers. Resources internal to core502may be represented by resources586inFIG.5B. As necessary, values written to or read from resources586may be coordinated with other portions of processor500through, for example, cache hierarchy503. As instructions are assigned resources, they may be placed into a reorder buffer588. Reorder buffer588may track instructions as they are executed and may selectively reorder their execution based upon any suitable criteria of processor500. In one embodiment, reorder buffer588may identify instructions or a series of instructions that may be executed independently. Such instructions or a series of instructions may be executed in parallel from other such instructions. Parallel execution in core502may be performed by any suitable number of separate execution blocks or virtual processors. In one embodiment, shared resources—such as memory, registers, and caches—may be accessible to multiple virtual processors within a given core502. In other embodiments, shared resources may be accessible to multiple processing entities within processor500.

Cache hierarchy503may be implemented in any suitable manner. For example, cache hierarchy503may include one or more lower or mid-level caches, such as caches572,574. In one embodiment, cache hierarchy503may include an LLC595communicatively coupled to caches572,574. In another embodiment, LLC595may be implemented in a module590accessible to all processing entities of processor500. In a further embodiment, module590may be implemented in an uncore module of processors from Intel, Inc. Module590may include portions or subsystems of processor500necessary for the execution of core502but might not be implemented within core502. Besides LLC595, Module590may include, for example, hardware interfaces, memory coherency coordinators, interprocessor interconnects, instruction pipelines, or memory controllers. Access to RAM599available to processor500may be made through module590and, more specifically, LLC595. Furthermore, other instances of core502may similarly access module590. Coordination of the instances of core502may be facilitated in part through module590.

FIGS.6-8may illustrate exemplary systems suitable for including processor500, whileFIG.9may illustrate an exemplary System on a Chip (SoC) that may include one or more of cores502. Other system designs and implementations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, DSPs, graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, may also be suitable. In general, a huge variety of systems or electronic devices that incorporate a processor and/or other execution logic as disclosed herein may be generally suitable.

FIG.6illustrates a block diagram of a system600, in accordance with embodiments of the present disclosure. System600may include one or more processors610,615, which may be coupled to Graphics Memory Controller Hub (GMCH)620. The optional nature of additional processors615is denoted inFIG.6with broken lines.

Each processor610,615may be some version of processor500. However, it should be noted that integrated graphics logic and integrated memory control units might not exist in processors610,615.FIG.6illustrates that GMCH620may be coupled to a memory640that may be, for example, a dynamic random access memory (DRAM). The DRAM may, for at least one embodiment, be associated with a non-volatile cache.

GMCH620may be a chipset, or a portion of a chipset. GMCH620may communicate with processors610,615and control interaction between processors610,615and memory640. GMCH620may also act as an accelerated bus interface between the processors610,615and other elements of system600. In one embodiment, GMCH620communicates with processors610,615via a multi-drop bus, such as a frontside bus (FSB)695.

Furthermore, GMCH620may be coupled to a display645(such as a flat panel display). In one embodiment, GMCH620may include an integrated graphics accelerator. GMCH620may be further coupled to an input/output (I/O) controller hub (ICH)650, which may be used to couple various peripheral devices to system600. External graphics device660may include be a discrete graphics device coupled to ICH650along with another peripheral device670.

In other embodiments, additional or different processors may also be present in system600. For example, additional processors610,615may include additional processors that may be the same as processor610, additional processors that may be heterogeneous or asymmetric to processor610, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor. There may be a variety of differences between the physical resources610,615in terms of a spectrum of metrics of merit including architectural, micro-architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst processors610,615. For at least one embodiment, various processors610,615may reside in the same die package.

FIG.7illustrates a block diagram of a second system700, in accordance with embodiments of the present disclosure. As shown inFIG.7, multiprocessor system700may include a point-to-point interconnect system, and may include a first processor770and a second processor780coupled via a point-to-point interconnect750. Each of processors770and780may be some version of processor500as one or more of processors610,615.

WhileFIG.7may illustrate two processors770,780, it is to be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

Processors770and780are shown including integrated memory controller units772and782, respectively. Processor770may also include as part of its bus controller units point-to-point (P-P) interfaces776and778; similarly, second processor780may include P-P interfaces786and788. Processors770,780may exchange information via a point-to-point (P-P) interface750using P-P interface circuits778,788. As shown inFIG.7, IMCs772and782may couple the processors to respective memories, namely a memory732and a memory734, which in one embodiment may be portions of main memory locally attached to the respective processors.

Processors770,780may each exchange information with a chipset790via individual P-P interfaces752,754using point to point interface circuits776,794,786,798. In one embodiment, chipset790may also exchange information with a high-performance graphics circuit738via a high-performance graphics interface739.

A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset790may be coupled to a first bus716via an interface796. In one embodiment, first bus716may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown inFIG.7, various I/O devices714may be coupled to first bus716, along with a bus bridge718which couples first bus716to a second bus720. In one embodiment, second bus720may be a Low Pin Count (LPC) bus. Various devices may be coupled to second bus720including, for example, a keyboard and/or mouse722, communication devices727and a storage unit728such as a disk drive or other mass storage device which may include instructions/code and data730, in one embodiment. Further, an audio I/O724may be coupled to second bus720. Note that other architectures may be possible. For example, instead of the point-to-point architecture ofFIG.7, a system may implement a multi-drop bus or other such architecture.

FIG.8illustrates a block diagram of a third system800in accordance with embodiments of the present disclosure. Like elements inFIGS.7and8bear like reference numerals, and certain aspects ofFIG.7have been omitted fromFIG.8in order to avoid obscuring other aspects ofFIG.8.

FIG.8illustrates that processors870,880may include integrated memory and I/O Control Logic (“CL”)872and882, respectively. For at least one embodiment, CL872,882may include integrated memory controller units such as that described above in connection withFIGS.5and7. In addition. CL872,882may also include I/O control logic.FIG.8illustrates that not only memories832,834may be coupled to CL872,882, but also that I/O devices814may also be coupled to control logic872,882. Legacy I/O devices815may be coupled to chipset890.

FIG.9illustrates a block diagram of a SoC900, in accordance with embodiments of the present disclosure. Similar elements inFIG.5bear like reference numerals. Also, dashed lined boxes may represent optional features on more advanced SoCs. An interconnect units902may be coupled to: an application processor910which may include a set of one or more cores902A-N and shared cache units906; a system agent unit910; a bus controller units916; an integrated memory controller units914; a set or one or more media processors920which may include integrated graphics logic908, an image processor924for providing still and/or video camera functionality, an audio processor926for providing hardware audio acceleration, and a video processor928for providing video encode/decode acceleration; an SRAM unit930; a DMA unit932; and a display unit940for coupling to one or more external displays.

FIG.10illustrates a processor containing a Central Processing Unit (CPU) and a graphics processing unit (GPU), which may perform at least one instruction, in accordance with embodiments of the present disclosure. In one embodiment, an instruction to perform operations according to at least one embodiment could be performed by the CPU. In another embodiment, the instruction could be performed by the GPU. In still another embodiment, the instruction may be performed through a combination of operations performed by the GPU and the CPU. For example, in one embodiment, an instruction in accordance with one embodiment may be received and decoded for execution on the GPU. However, one or more operations within the decoded instruction may be performed by a CPU and the result returned to the GPU for final retirement of the instruction. Conversely, in some embodiments, the CPU may act as the primary processor and the GPU as the co-processor.

In some embodiments, instructions that benefit from highly parallel, throughput processors may be performed by the GPU, while instructions that benefit from the performance of processors that benefit from deeply pipelined architectures may be performed by the CPU. For example, graphics, scientific applications, financial applications and other parallel workloads may benefit from the performance of the GPU and be executed accordingly, whereas more sequential applications, such as operating system kernel or application code may be better suited for the CPU.

InFIG.10, processor1000includes a CPU1005, GPU1010, image processor1015, video processor1020, USB controller1025, UART controller1030, SPI/SDIO controller1035, display device1040, memory interface controller1045, MIPI controller1050, flash memory controller1055, Dual Data Rate (DDR) controller1060, security engine1065, and I2S/I2C controller1070. Other logic and circuits may be included in the processor ofFIG.10, including more CPUs or GPUs and other peripheral interface controllers.

One or more aspects of at least one embodiment may be implemented by representative data stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores,” may be stored on a tangible, machine-readable medium (“tape”) and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor. For example, IP cores, such as the Cortex™ family of processors developed by ARM Holdings, Ltd. and Loongson IP cores developed the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences may be licensed or sold to various customers or licensees, such as Texas Instruments, Qualcomm, Apple, or Samsung and implemented in processors produced by these customers or licensees.

FIG.11illustrates a block diagram illustrating the development of IP cores, in accordance with embodiments of the present disclosure. Storage1130may include simulation software1120and/or hardware or software model1110. In one embodiment, the data representing the IP core design may be provided to storage1130via memory1140(e.g., hard disk), wired connection (e.g., internet)1150or wireless connection1160. The IP core information generated by the simulation tool and model may then be transmitted to a fabrication facility where it may be fabricated by a third party to perform at least one instruction in accordance with at least one embodiment.

In some embodiments, one or more instructions may correspond to a first type or architecture (e.g., x86) and be translated or emulated on a processor of a different type or architecture (e.g., ARM). An instruction, according to one embodiment, may therefore be performed on any processor or processor type, including ARM, x86, MIPS, a GPU, or other processor type or architecture.

FIG.12illustrates how an instruction of a first type may be emulated by a processor of a different type, in accordance with embodiments of the present disclosure. InFIG.12, program1205contains some instructions that may perform the same or substantially the same function as an instruction according to one embodiment. However the instructions of program1205may be of a type and/or format that is different from or incompatible with processor1215, meaning the instructions of the type in program1205may not be able to execute natively by the processor1215. However, with the help of emulation logic,1210, the instructions of program1205may be translated into instructions that may be natively executed by the processor1215. In one embodiment, the emulation logic may be embodied in hardware. In another embodiment, the emulation logic may be embodied in a tangible, machine-readable medium containing software to translate instructions of the type in program1205into the type natively executable by processor1215. In other embodiments, emulation logic may be a combination of fixed-function or programmable hardware and a program stored on a tangible, machine-readable medium. In one embodiment, the processor contains the emulation logic, whereas in other embodiments, the emulation logic exists outside of the processor and may be provided by a third party. In one embodiment, the processor may load the emulation logic embodied in a tangible, machine-readable medium containing software by executing microcode or firmware contained in or associated with the processor.

FIG.13illustrates a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set, in accordance with embodiments of the present disclosure. In the illustrated embodiment, the instruction converter may be a software instruction converter, although the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.FIG.13shows a program in a high level language1302may be compiled using an x86 compiler1304to generate x86 binary code1306that may be natively executed by a processor with at least one x86 instruction set core1316. The processor with at least one x86 instruction set core1316represents any processor that may perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. x86 compiler1304represents a compiler that may be operable to generate x86 binary code1306(e.g., object code) that may, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core1316. Similarly,FIG.13shows the program in high level language1302may be compiled using an alternative instruction set compiler1308to generate alternative instruction set binary code1310that may be natively executed by a processor without at least one x86 instruction set core1314(e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA). Instruction converter1312may be used to convert x86 binary code1306into code that may be natively executed by the processor without an x86 instruction set core1314. This converted code might not be the same as alternative instruction set binary code1310; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, instruction converter1312represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute x86 binary code1306.

FIG.14is a block diagram of an instruction set architecture1400of a processor, in accordance with embodiments of the present disclosure. Instruction set architecture1400may include any suitable number or kind of components.

For example, instruction set architecture1400may include processing entities such as one or more cores1406,1407and a graphics processing unit1415. Cores1406,1407may be communicatively coupled to the rest of instruction set architecture1400through any suitable mechanism, such as through a bus or cache. In one embodiment, cores1406,1407may be communicatively coupled through an L2 cache control1408, which may include a bus interface unit1409and an L2 cache1410. Cores1406,1407and graphics processing unit1415may be communicatively coupled to each other and to the remainder of instruction set architecture1400through interconnect1410. In one embodiment, graphics processing unit1415may use a video code1420defining the manner in which particular video signals will be encoded and decoded for output.

Instruction set architecture1400may also include any number or kind of interfaces, controllers, or other mechanisms for interfacing or communicating with other portions of an electronic device or system. Such mechanisms may facilitate interaction with, for example, peripherals, communications devices, other processors, or memory. In the example ofFIG.14, instruction set architecture1400may include an LCD video interface1425, a Subscriber Interface Module (SIM) interface1430, a boot ROM interface1435, an SDRAM controller1440, a flash controller1445, and a Serial Peripheral Interface (SPI) master unit1450. LCD video interface1425may provide output of video signals from, for example, GPU1415and through, for example, a Mobile Industry Processor Interface (MIPI)1490or a High-Definition Multimedia Interface (HDMI)1495to a display. Such a display may include, for example, an LCD. SIM interface1430may provide access to or from a SIM card or device. SDRAM controller1440may provide access to or from memory such as an SDRAM chip or module. Flash controller1445may provide access to or from memory such as flash memory or other instances of RAM. SPI master unit1450may provide access to or from communications modules, such as a Bluetooth module1470, high-speed 3G modem1475, global positioning system module1480, or wireless module1485implementing a communications standard such as 802.11.

FIG.15is a more detailed block diagram of an instruction set architecture1500of a processor, in accordance with embodiments of the present disclosure. Instruction architecture1500may implement one or more aspects of instruction set architecture1400. Furthermore, instruction set architecture1500may illustrate modules and mechanisms for the execution of instructions within a processor.

Instruction architecture1500may include a memory system1540communicatively coupled to one or more execution entities1565. Furthermore, instruction architecture1500may include a caching and bus interface unit such as unit1510communicatively coupled to execution entities1565and memory system1540. In one embodiment, loading of instructions into execution entities1564may be performed by one or more stages of execution. Such stages may include, for example, instruction prefetch stage1530, dual instruction decode stage1550, register rename stage155, issue stage1560, and writeback stage1570.

In one embodiment, memory system1540may include an executed instruction pointer1580. Executed instruction pointer1580may store a value identifying the oldest, undispatched instruction within a batch of instructions. The oldest instruction may correspond to the lowest Program Order (PO) value. A PO may include a unique number of an instruction. Such an instruction may be a single instruction within a thread represented by multiple strands. A PO may be used in ordering instructions to ensure correct execution semantics of code. A PO may be reconstructed by mechanisms such as evaluating increments to PO encoded in the instruction rather than an absolute value. Such a reconstructed PO may be known as an “RPO.” Although a PO may be referenced herein, such a PO may be used interchangeably with an RPO. A strand may include a sequence of instructions that are data dependent upon each other. The strand may be arranged by a binary translator at compilation time. Hardware executing a strand may execute the instructions of a given strand in order according to PO of the various instructions. A thread may include multiple strands such that instructions of different strands may depend upon each other. A PO of a given strand may be the PO of the oldest instruction in the strand which has not yet been dispatched to execution from an issue stage. Accordingly, given a thread of multiple strands, each strand including instructions ordered by PO, executed instruction pointer1580may store the oldest illustrated by the lowest number-PO in the thread.

In another embodiment, memory system1540may include a retirement pointer1582. Retirement pointer1582may store a value identifying the PO of the last retired instruction. Retirement pointer1582may be set by, for example, retirement unit454. If no instructions have yet been retired, retirement pointer1582may include a null value.

Execution entities1565may include any suitable number and kind of mechanisms by which a processor may execute instructions. In the example ofFIG.15, execution entities1565may include ALU/Multiplication Units (MUL)1566, ALUs1567, and Floating Point Units (FPU)1568. In one embodiment, such entities may make use of information contained within a given address1569. Execution entities1565in combination with stages1530,1550,1555,1560,1570may collectively form an execution unit.

Unit1510may be implemented in any suitable manner. In one embodiment, unit1510may perform cache control. In such an embodiment, unit1510may thus include a cache1525. Cache1525may be implemented, in a further embodiment, as an L2 unified cache with any suitable size, such as zero, 128 k, 256 k, 512 k, 1M, or 2M bytes of memory. In another, further embodiment, cache1525may be implemented in error-correcting code memory. In another embodiment, unit1510may perform bus interfacing to other portions of a processor or electronic device. In such an embodiment, unit1510may thus include a bus interface unit1520for communicating over an interconnect, intraprocessor bus, interprocessor bus, or other communication bus, port, or line. Bus interface unit1520may provide interfacing in order to perform, for example, generation of the memory and input/output addresses for the transfer of data between execution entities1565and the portions of a system external to instruction architecture1500.

To further facilitate its functions, bus interface unit1520may include an interrupt control and distribution unit1511for generating interrupts and other communications to other portions of a processor or electronic device. In one embodiment, bus interface unit1520may include a snoop control unit1512that handles cache access and coherency for multiple processing cores. In a further embodiment, to provide such functionality, snoop control unit1512may include a cache-to-cache transfer unit that handles information exchanges between different caches. In another, further embodiment, snoop control unit1512may include one or more snoop filters1514that monitors the coherency of other caches (not shown) so that a cache controller, such as unit1510, does not have to perform such monitoring directly. Unit1510may include any suitable number of timers1515for synchronizing the actions of instruction architecture1500. Also, unit1510may include an AC port1516.

Memory system1540may include any suitable number and kind of mechanisms for storing information for the processing needs of instruction architecture1500. In one embodiment, memory system1504may include a load store unit1530for storing information such as buffers written to or read back from memory or registers. In another embodiment, memory system1504may include a translation lookaside buffer (TLB)1545that provides look-up of address values between physical and virtual addresses. In yet another embodiment, bus interface unit1520may include a Memory Management Unit (MMU)1544for facilitating access to virtual memory. In still yet another embodiment, memory system1504may include a prefetcher1543for requesting instructions from memory before such instructions are actually needed to be executed, in order to reduce latency.

The operation of instruction architecture1500to execute an instruction may be performed through different stages. For example, using unit1510instruction prefetch stage1530may access an instruction through prefetcher1543. Instructions retrieved may be stored in instruction cache1532. Prefetch stage1530may enable an option1531for fast-loop mode, wherein a series of instructions forming a loop that is small enough to fit within a given cache are executed. In one embodiment, such an execution may be performed without needing to access additional instructions from, for example, instruction cache1532. Determination of what instructions to prefetch may be made by, for example, branch prediction unit1535, which may access indications of execution in global history1536, indications of target addresses1537, or contents of a return stack1538to determine which of branches1557of code will be executed next. Such branches may be possibly prefetched as a result. Branches1557may be produced through other stages of operation as described below. Instruction prefetch stage1530may provide instructions as well as any predictions about future instructions to dual instruction decode stage.

Dual instruction decode stage1550may translate a received instruction into microcode-based instructions that may be executed. Dual instruction decode stage1550may simultaneously decode two instructions per clock cycle. Furthermore, dual instruction decode stage1550may pass its results to register rename stage1555. In addition, dual instruction decode stage1550may determine any resulting branches from its decoding and eventual execution of the microcode. Such results may be input into branches1557.

Register rename stage1555may translate references to virtual registers or other resources into references to physical registers or resources. Register rename stage1555may include indications of such mapping in a register pool1556. Register rename stage1555may alter the instructions as received and send the result to issue stage1560.

Issue stage1560may issue or dispatch commands to execution entities1565. Such issuance may be performed in an out-of-order fashion. In one embodiment, multiple instructions may be held at issue stage1560before being executed. Issue stage1560may include an instruction queue1561for holding such multiple commands. Instructions may be issued by issue stage1560to a particular processing entity1565based upon any acceptable criteria, such as availability or suitability of resources for execution of a given instruction. In one embodiment, issue stage1560may reorder the instructions within instruction queue1561such that the first instructions received might not be the first instructions executed. Based upon the ordering of instruction queue1561, additional branching information may be provided to branches1557. Issue stage1560may pass instructions to executing entities1565for execution.

Upon execution, writeback stage1570may write data into registers, queues, or other structures of instruction set architecture1500to communicate the completion of a given command. Depending upon the order of instructions arranged in issue stage1560, the operation of writeback stage1570may enable additional instructions to be executed. Performance of instruction set architecture1500may be monitored or debugged by trace unit1575.

FIG.16is a block diagram of an execution pipeline1600for an instruction set architecture of a processor, in accordance with embodiments of the present disclosure. Execution pipeline1600may illustrate operation of, for example, instruction architecture1500ofFIG.15.

Execution pipeline1600may include any suitable combination of steps or operations. In1605, predictions of the branch that is to be executed next may be made. In one embodiment, such predictions may be based upon previous executions of instructions and the results thereof. In1610, instructions corresponding to the predicted branch of execution may be loaded into an instruction cache. In1615, one or more such instructions in the instruction cache may be fetched for execution. In1620, the instructions that have been fetched may be decoded into microcode or more specific machine language. In one embodiment, multiple instructions may be simultaneously decoded. In1625, references to registers or other resources within the decoded instructions may be reassigned. For example, references to virtual registers may be replaced with references to corresponding physical registers. In1630, the instructions may be dispatched to queues for execution. In1640, the instructions may be executed. Such execution may be performed in any suitable manner. In1650, the instructions may be issued to a suitable execution entity. The manner in which the instruction is executed may depend upon the specific entity executing the instruction. For example, at1655, an ALU may perform arithmetic functions. The ALU may utilize a single clock cycle for its operation, as well as two shifters. In one embodiment, two ALUs may be employed, and thus two instructions may be executed at1655. At1660, a determination of a resulting branch may be made. A program counter may be used to designate the destination to which the branch will be made.1660may be executed within a single clock cycle. At1665, floating point arithmetic may be performed by one or more FPUs. The floating point operation may require multiple clock cycles to execute, such as two to ten cycles. At1670, multiplication and division operations may be performed. Such operations may be performed in four clock cycles. At1675, loading and storing operations to registers or other portions of pipeline1600may be performed. The operations may include loading and storing addresses. Such operations may be performed in four clock cycles. At1680, write-back operations may be performed as required by the resulting operations of1655-1675.

FIG.17is a block diagram of an electronic device1700for utilizing a processor1710, in accordance with embodiments of the present disclosure. Electronic device1700may include, for example, a notebook, an ultrabook, a computer, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

Electronic device1700may include processor1710communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. Such coupling may be accomplished by any suitable kind of bus or interface, such as I2C bus, System Management Bus (SMBus), Low Pin Count (LPC) bus, SPI, High Definition Audio (HDA) bus, Serial Advance Technology Attachment (SATA) bus, USB bus (versions 1, 2, 3), or Universal Asynchronous Receiver/Transmitter (UART) bus.

Such components may include, for example, a display1724, a touch screen1725, a touch pad1730, a Near Field Communications (NFC) unit1745, a sensor hub1740, a thermal sensor1746, an Express Chipset (EC)1735, a Trusted Platform Module (TPM)1738, BIOS/firmware/flash memory1722, a DSP1760, a drive1720such as a Solid State Disk (SSD) or a Hard Disk Drive (HDD), a wireless local area network (WLAN) unit1750, a Bluetooth unit1752, a Wireless Wide Area Network (WWAN) unit1756, a Global Positioning System (GPS), a camera1754such as a USB 3.0 camera, or a Low Power Double Data Rate (LPDDR) memory unit1715implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

Furthermore, in various embodiments other components may be communicatively coupled to processor1710through the components discussed above. For example, an accelerometer1741, Ambient Light Sensor (ALS)1742, compass1743, and gyroscope1744may be communicatively coupled to sensor hub1740. A thermal sensor1739, fan1737, keyboard1746, and touch pad1730may be communicatively coupled to EC1735. Speaker1763, headphones1764, and a microphone1765may be communicatively coupled to an audio unit1764, which may in turn be communicatively coupled to DSP1760. Audio unit1764may include, for example, an audio codec and a class D amplifier. A SIM card1757may be communicatively coupled to WWAN unit1756. Components such as WLAN unit1750and Bluetooth unit1752, as well as WWAN unit1756may be implemented in a Next Generation Form Factor (NGFF).

FIG.18is a block diagram of a portion of a system1800for tracking and supervising performance bottlenecks, according to embodiments of the present disclosure. In one embodiment, such bottlenecks may include bottlenecks associated with instruction fetching. In another embodiment, system1800may execute instructions that cause portions of the system to track bottlenecks in fetching. System1800may include any suitable number and kind of elements for executing these instructions. Moreover, in various embodiments system1800may include any suitable number and kind of elements for support of tracking bottlenecks in fetching. In one embodiment, system1800may include an interface for users to specify, through instructions accessing the interface, events that are of interest for performance bottleneck tracking of fetches. Such an interface may include a model-specific register. In another embodiment, system1800may include mechanisms for defining performance management events that identify issues with fetching or front ends. In yet another embodiment, system1800may include a programmable circuit to count when front-end delays meet latency or bandwidth conditions specified by users through instructions. Such delays may be counted regardless of source event. In yet another embodiment, system1800may include a sampling mechanism to create event samples or interrupts when a delayed front-end event retires. Although various elements of system1800may be described herein as performing particularly functionality, the functionality described herein may be performed by any suitable portion of system1800.

Identification of where instruction fetch problems arise may be difficult in an out-of-order processor, such as processor1804. Fetch latency issues may arise due to large code footprints, spread of virtualized and consolidated systems for execution, and object-oriented frameworks with fragmented code. Furthermore, some workloads are naturally more intensive with respect to fetch bandwidth requirements. Fetch issues may be difficult to identify in performance analysis because the fetch issues arise at an early stage of the processor pipeline. The pipeline, as described above, may include multiple stages, large buffers, and instruction speculation that make it difficult to track issues from where they arose. Furthermore, some fetch issues might not even execute, as they may be a part of a speculative branch.

In one embodiment, system1800may include a mechanism to specify that bottlenecks in fetching are to be tracked. Any suitable mechanism may be used, such as function calls, registers, or configuration settings. For example, system1800may include a frontend model-specific-register (FE MSR)1830to specify how bottlenecks in fetching are to be tracked. Instructions to access FE MSR1830may include, for example, SET_FE_EVENT to specify what events will be tracked; SET_FE_CRITICAL to specify that critical events or events for critical operations will be tracked; SET_FE_LATENCY to set parameters about fetch latency for events to be tracked; and SET_FE_THRESHOLD to set parameters about how many fetch bottlenecks to be tracked.

In another embodiment, system1800may include a performance monitoring unit (PMU)1826to track markers associated with fetch bottlenecks and counters of events. PMU1826may be implemented by any suitable combination of analog circuitry, digital circuitry, and microcode for reconfigurable logic. In a further embodiment, PMU1826may respond to retired instructions marked as associated with front-end events. The front-end events may be marked in any suitable manner. In various embodiments, the front-end events may be marked according to a source of the event. For example, if an attempted loading of an instruction from a cache generates a miss, the instruction, when loaded, may be marked with a bit identifying that the load was associated with a fetch miss. In a further embodiment, when the instruction retires, counters associated with the fetch miss may be incremented by observing the set bit. The miss, alone or with other data, may be reported by PMU1826through interrupts or other suitable mechanisms. PMU1826may be implemented by combinations of digital circuitry, analog circuitry, and execution of microcode in reconfigurable logic. PMU1826may operate according to specified values in FE MSR1830.

In another embodiment, system1800may include mechanism for precise event based sampling (PEBS)1828. A call stack, PerfMon framework, instruction pointer, architectural state of processor1804, and register values may be included in PEBS1828. PEBS1828may be implemented by combinations of digital circuitry, analog circuitry, and execution of microcode in reconfigurable logic. PEBS1828may operate according to specified values in FE MSR1830.

In yet another embodiment, system1800may include a mechanism for tracking latency and bandwidth associated with designated frontend events. For example, system1800may include latency counter1834. Latency counter1834may be implemented by combinations of digital circuitry, analog circuitry, and execution of microcode in reconfigurable logic. Latency counter1834may operate according to specified values in FE MSR1830.

System1800may include processor1804. Processor1804may be implemented in part by any suitable combination of the elements ofFIGS.1-17. Processor1804may include a front end1806, which may receive and decode instructions from instruction stream1802using a decoder1818to implement a decode pipeline stage. The decoded instructions may be dispatched, allocated, and scheduled for execution by an allocation stage1810of a pipeline and allocated to specific execution units1812or cores1814. After execution, instructions may be retired by a writeback stage or retirement stage1816. Although various operations are described herein as performed by specific components of processor1804, the functionality may be performed by any suitable portion of processor1804. In various embodiments, processor1804may receive, decode, schedule, execute, and retire execute instructions that enable or disable tracking of fetch bottlenecks. Furthermore, processor1804may receive, decode, schedule, execute, and retire other instructions that are to be tracked.

Fetch stage1803may encounter delays from, for example, fetching instructions or data from a memory subsystem1824. Memory subsystem1824may include, for example, a cache hierarchy connected to registers or physical memory. Furthermore, fetch stage1803may encounter delays when accessing instruction cache1820. If an instruction is unavailable in instruction cache1820(resulting in a miss), then the instruction might need to be retrieved from memory subsystem1824. If the instruction is not located on any cache, then access from physical memory may be required, which may be relatively slow. Furthermore, fetch stage1803may encounter delays when accessing instruction translation lookaside buffer (iTLB)1822. If a requested page information is unavailable in iTLB1822, a miss may occur. Furthermore, fetch stage1803may encounter delays from still other actions, bugs, conflicts, or errors.

FE MSR1830may be set by execution of instructions to track one or more possible delays in front end1806or fetch stand1804. FE MSR1830may specifically identify that certain kinds of delays from the front end or fetching are to be tracked. Moreover, FE MSR1830may specify that latency and bandwidth are to be tracked for any sort of delays from the front end or fetching. Once a delay is encountered, such as a miss from instruction cache1820or iTLB1822, a NOP may be issued for execution as execution stages of processor1804may require input for all cycles. In one embodiment, the NOP or the subsequent instruction may be tagged with an identifier of the front end or fetch delay. The identifier may be specific to the type of delay. The identifier is associated with the instruction as it propagates through the execution pipeline of processor1804. In another embodiment, the front end or fetch delay may be counted in PMU1826or PEBS1828after the marked instruction is retired. Information about the instruction subsequent to the NOP may be recorded or reported so that the source of the delays may be identified. By waiting until the marked instruction is retired, mispredicted delays and other information may be removed from consideration. Furthermore, by waiting until the marked instruction is retired, the counts of delay events may be non-speculative. PMU1826or PEBS may issue interrupts based upon collected data from retired, marked instructions.

In some embodiments, critical events may be filtered such that only such critical events contribute to the counts of delay events. Such critical events may include a subset of possible retired events that are likely to cause performance slowdown.

FIG.19is an illustration of an example model-specific register for front end event tracking, according to embodiments of the present disclosure. In one embodiment,FIG.19may illustrate an embodiment of FE MSR1830. Counters may be programmed with an event denoting usage of FE MSR1830, such as FRONTEND_RETIRED. The actual events to be tracked are identified within FE MSR1830, as discussed below.

In one embodiment, FE MSR1830may include a field1902for a front-end event threshold, above which reporting may occur. This field may be, for example, three bits wide. This field may be used when bubble-counting and tracking is to be performed in an instruction decode queue. This field may control the minimum number of allocation slots that should contain a bubble in order for system1800to consider the bubble a potentially problematic event and have a latency counter increment. The instruction setting this field may identify a particular instance of FE MSR, if more than one is available on system1800. Furthermore, the instruction may include a value to set this field, as well as any other necessary operands, fields, flags, or parameters.

In another embodiment, FE MSR1830may include a field1904for a front-end latency value, above which reporting may occur. This field may be used when bubble-counting and tracking is to be performed in an instruction decode queue. It specifies the minimum number of consecutive cycles that a bubble (or unarrived instruction) must occur in order for system1800to consider the bubble a potentially problematic event. As this field is set by users, it may be configurable and tunable to be more or less tolerant of bubbles in the instruction decode queue. By default, this value may be set to eight. This field may be, for example, twelve bits wide. The instruction may identify a particular instance of FE MSR, if more than one is available on system1800. Furthermore, the instruction may include a value to set this field, as well as any other necessary operands, fields, flags, or parameters.

In yet another embodiment, FE MSR1830may include a field1906for denoting whether tracking or reporting will be filtered on critical events. Such critical events may be defined by a design of system1800. Furthermore, these events are those front-end or fetch delays that are more likely to cause delays in processing further down the pipeline. In a further embodiment, field1906may be a bit wide. In another, further embodiment, field1906may be multiple bits wide, wherein each bit is associated with a different type of critical aspect, or the bits together form a code or identifier of a critical condition. This field may be set by the instruction SET_FE_CRITICAL. The instruction may identify a particular instance of FE MSR, if more than one is available on system1800. Furthermore, the instruction may include a value to set this field, as well as any other necessary operands, fields, flags, or parameters.

In still yet another embodiment, FE MSR1830may include a field1908to identify what events are to be tracked. Field1908may be three bits wide, eight bits wide, or any other size necessary to illustrate a sufficient number of types of events that need to be identified. This field may be set by the instruction SET_FE_EVENT. The instruction may identify a particular instance of FE MSR, if more than one is available on system1800. Furthermore, the instruction may include a value to set this field, as well as any other necessary operands, fields, flags, or parameters.

Furthermore, FE MSR1830may include other reserved fields or spaces.

Any suitable number or kind of events may be tracked by system1800. The following are provided as examples. In one embodiment, field1908may designate that a decoded stream buffer (DSB), which may also be a decoded micro-op cache, miss may be tracked. This may be denoted as DSB_MISS.

In another embodiment, field1908may designate that an instruction cache miss in of a first level may be tracked. This may be denoted as an event known as L1I_MISS. This may require a true miss. Additional requests to the same cache line while the miss is in-flight might not be counted. Furthermore, field1908may designate that an instruction cache miss in a second level of a cache hierarchy may be tracked. This may be denoted as an event known as L2I_MISS or MLC_MISS. This may also require a true miss and might not increment while the miss is in-flight. Furthermore, field1908may designate that an instruction cache miss in a third level of a cache hierarchy may be tracked. This may be denoted as an L3I_MISS event. More events may be defined per the memory subsystem and cache organization in system1800.

In yet another embodiment, field1908may designate that an instruction TLB miss is to be tracked. This may be denoted as ITLB_MISS. In still yet another embodiment, field1908may designate that data TLB misses are to be tracked. For example, a second-level data TLB in a hierarchy may have been missed. This may be denoted as STLB_MISS. These may be required to be true misses, and updated values might not occur while the misses are in-flight.

In still yet another embodiment, field1908may designate that overall delays are to be tracked. This may include invocation of a function or instruction to read the number of bubbles, or NOPs or gaps, within an execution pipeline due to fetch delays. This may be denoted as IDQ_READ_BUBBLES. Such returned data may be used in conjunction with latency counter1834, as further explained below. An IDQ read bubble may include any allocation slot in an instruction decode queue that is not filled by the front-end on any cycle where there is no back end stall. Using threshold and latency fields associated with this event allows counting of IDQ read bubbles of various magnitudes and durations. Latency may control the number of cycles and threshold may control the number of allocation slots that contain bubbles. An event is generated, or counts, if and only if a sequence of at least [latency] consecutive cycles contains at least [threshold] number of bubbles each.

Once one or more events are set to be tracked, the events might be tagged as they are encountered in a front end. The events may be tagged in any suitable manner. In one embodiment, the events may be tagged by setting a bit on the responsible instruction, line, or micro operation. Multiple possible bits may be available for defining the type of event. The bit may be propagated through the execution pipeline until the instruction is retired. Upon such retirement, the event may be logged or issued by, for example, PMU1826or PEBS1828.

FIG.20is an illustration of example operation of system1800to track front end bottlenecks, according to embodiments of the present disclosure.

The portions of processor1804propagating event information shown inFIG.20are provided as examples. Other portions of processor1804may similarly propagate tags or other information denoting the existence of the front end events.

Taking an instruction cache1820miss as an example event, the front end of processor1804may attempt to load a cacheline from instruction cache1820but the cacheline might not be available. The load may have originated from a branch predict unit2002. The miss may cause a front end event tag1832to be set within the cacheline.

In one embodiment, as fetch unit1804reads the cacheline from the queue of branch predict unit1804, it may mark or identify the instructions contained within the fetched cacheline. Furthermore, fetch unit1804may associate any instructions that in turn use the marked cacheline (such as a case where the instruction as fetched was incomplete). Fetch unit1804may set an entry for the instruction with a bit in instruction queue2006when the instruction is written to the queue. When instruction decoder2008reads the instruction from instruction queue2006, it may observe that the entry includes the tag. Decoder2008may create microoperations for the instruction. Decoder2008may set the tag in the first resulting microoperation produced for the instruction, such as the first microporation. The microoperation, including the tag, may be written to the instructions decoded queue2010. When a register alias table or allocator2012read the entry from instructions decoded queue2010, allocator2012may pass on the tag which may be stored with the microoperation in a reorder buffer2014or other out-of-order execution tracking mechanism. Upon retirement, retirement unit2016may read the value from reorder buffer2014and increment counters or other information. Actions to report the value may be handled by PMU1826, if thresholds are reached. The values of the counters may be read through an interrupt. If the event was enabled for handling by PEBS1828, a PEBS event may be signaled.

The value may be reported via an event within an event framework for system1800. For example, the event may be reported as a FRONTEND_RETIRED event. Users of system1800, when receiving notice of the event, may be able identify the instructions that caused fetching and front end issues. In one embodiment, this event may inly count retired, non-speculative front end or fetch events. Only events from true program execution path are counted. In another embodiment, the event will count once per attempted cacheline access. If a cacheline contains multiple instructions or accesses for which misses were created, the additional instances might not be counted. In yet another embodiment, if a multiple-uop instruction multiple events, these might be counted as a single event for the entire instruction. In another embodiment, if two instructions are fused using, for example, macro-fusion, and either or both cause a front end miss or fetch event, only one event will be counted for the combination. In yet another embodiment, if a miss occurs outside of an instruction boundary (for example, due to processor handling of an architectural event), the event might be reported for the next instruction to retire.

FIG.21is an illustration of a latency counter, according to embodiments of the present disclosure.FIG.21may illustrate an example embodiment of latency counter1834. Latency counter1834may be provided for a given entity such as an application, denoted Tx.

In one embodiment, latency counter1834may be enabled through setting of an associated field in FE MSR1830. In particular, setting the event field for IDQ_Read_Bubbles may cause invocation of an instruction to read the number of bubbles, or NOPs, in the pipeline created as a result of delays in the front end or fetching. These may arise in an instruction decode queue, such as element2010inFIG.20. Thus, such bubbles may be counted in the instruction decode queue.

A function call to IDQ_Read_Bubbles may return a count of the number of bubbles generated. In one embodiment, a multiplexer2102may issue the count if an identifier of the queue matches the entity for which front end and fetch event tracking is to be performed.

In one embodiment, a comparator2104may compare the count against the threshold value stored in FE MSR1830. If the count is greater than the threshold, then the count may be forwarded for possible further consideration. Comparator2104may be implemented by a comparator circuit and multiplexer that compares the two values but outputs a set value only when the count is greater. In another embodiment, the output of comparator2104may be routed to an OR gate2106, which may determine if either comparator2104has found a count exceeding the threshold, or if a sticky bit reset has been issued by a decision block2112, discussed in further detail below. The sticky bit may be cleared after it is read. In yet another embodiment, the output of gate2106may be routed to a latency counter2108for the entity. Latency counter2108may increment upon receiving a new input. Latency counter2108may be 12 bits wide. Furthermore, latency counter2108may be implemented with circuitry as an adder with a “one” as an input, a loopback as the other input, and latching input. The output may be routed to a comparator2110.

In one embodiment, comparator2110may compare the current latency counter2108value with the latency threshold defined in FE MSR1830. Comparator2110may be implemented by a comparator circuit and multiplexer that compares the two values but outputs a set value only when the two are equal. The output may be made to a decision block2112implemented by a circuit to set the sticky bit reset, if the event code from FE MSR1830specifies IDQ_Read_Bubbles. Moreover, a specific event tag, denoted PRECISE_FIT_TAG, may be set for microoperations that follow a determination that latency counter2108has reached latency settings from FE MSR1830.

For example, if the threshold of the bubble count threshold is four and the latency threshold is three, the PRECISE_FIT_TAG may be set for microoperations that follow an allocation window that has had no micro-operations (that is, it has had bubbles instead of actual instructions arrive) for at least three cycles. If the threshold of the bubble count is two and the latency threshold is two, then a resulting event will tag uops allocated following a window of a least two cycles wherein at least two bubbles were found.

FIG.22is a flowchart of a method2200for tracking entry and exit to monitored regions of memory, according to embodiments of the present disclosure. Method2200may begin at any suitable point and may execute in any suitable order. In one embodiment, method2200may begin at2205. In various embodiments, method2200may be performed during the execution of a processor such as processor1804or elements such as front end1806, fetch stage1803, PMU1826, or PEBS1828. Moreover, method2200may be performed by any suitable combination of the elements of processor1804or other elements.

At2205, it may be determined whether an instruction for enabling or disabling tracking of front end or fetch bottlenecks has been received, executed, and retired. If such an instruction has been received, method2200may proceed to2210. Otherwise, method2200may proceed to2215. In one embodiment, at2210, if such an instruction has been received, tracking may be enabled or disabled as appropriate. Moreover, parameters of such tracking may be applied to, for example, an MSR. Such parameters may include, for example, parameters: bubble count thresholds, latency thresholds, critical filter identifiers, and event identifiers. Method2200may proceed to2215.

At2215, it may be determined whether another instruction, which may be candidate for tracking, has been received. If not, method2200may proceed to2240. If a candidate for tracking has been received, method2200may proceed to2220.

At2220, in one embodiment it may be determined whether a fetch or front end event, such as an instruction cache miss, has occurred that matches an event code enabled in the MSR. Such matching may be performed by counters enabled by performance monitoring schemes. If so, method2200may proceed to2225. Otherwise, method2200may proceed to2240.

At2225, in one embodiment a tag identifying fetch events, front end events, or the particular event encountered by the instruction may be attached to the instruction. The tag may be propagated through translation, transformation, decoding, allocation, and execution of the instruction through the pipeline. At2230, in another embodiment it may be determined whether the instruction has been retired. An instruction might not have been retired, for example, because of a branch misprediction or other out-of-order execution error. If the instruction will not be retired, the event tag may be discarded or ignored and method2200may proceed to2240. If the instruction has retired, method2200may proceed to2235. In yet another embodiment, at2235an event for the event code and identifying the instruction may be issued. Method2220may proceed to2240.

At2240, in one embodiment it may be determined whether bubble tracking has been enabled. Such bubble tracking may be designated by the MSR. The bubble tracking may be initiated in an instruction decode queue. If such tracking has not been enabled, method2200may proceed to2260. Otherwise method2200may proceed to2245.

At2245, in one embodiment it may be determined whether the count of bubbles in the instruction decode queue is greater than a threshold designated by the MSR. If not, method2200may proceed to2260. If the count is greater than the threshold, then in another embodiment at2250it may be determined whether a number of cycles for which the bubbles have exceeded the count threshold is greater than a latency setting. A latency or cycle counter may be incremented. If the determined number of cycles is not greater than the latency setting, method2200may proceed to2260. If the determined number of cycles is greater than the latency setting, in yet another embodiment at2255a tag identifying the bubble condition may be generated. The tag may be generated for a first instruction after a present allocation window with NOPs ends. Method2200may return to2225to attach the tag to the instruction.

At2260, it may be determined whether method2200is to repeat. If not, method2200may terminate.

Method2200may be initiated by any suitable criteria. Furthermore, although method2200describes an operation of particular elements, method2200may be performed by any suitable combination or type of elements. For example, method2200may be implemented by the elements illustrated inFIGS.1-21or any other system operable to implement method2200. As such, the preferred initialization point for method2200and the order of the elements comprising method2200may depend on the implementation chosen. In some embodiments, some elements may be optionally omitted, reorganized, repeated, or combined.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the disclosure may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system may include any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores,” may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, Compact Disk Read-Only Memories (CD-ROMs), Compact Disk Rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as Read-Only Memories (ROMs), Random Access Memories (RAMs) such as Dynamic Random Access Memories (DRAMs), Static Random Access Memories (SRAMs), Erasable Programmable Read-Only Memories (EPROMs), flash memories, Electrically Erasable Programmable Read-Only Memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Accordingly, embodiments of the disclosure may also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part-on and part-off processor.

Thus, techniques for performing one or more instructions according to at least one embodiment are disclosed. While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on other embodiments, and that such embodiments not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art upon studying this disclosure. In an area of technology such as this, where growth is fast and further advancements are not easily foreseen, the disclosed embodiments may be readily modifiable in arrangement and detail as facilitated by enabling technological advancements without departing from the principles of the present disclosure or the scope of the accompanying claims.

Embodiments of the present disclosure may include a processor. In various embodiments, the processor may include a front end with circuitry and logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions, an execution unit with circuitry and logic to execute the event instruction and set a register with parameters for supervision of the front end event, a retirement stage with circuitry and logic to retire the event instruction, a counter, and a performance monitoring unit. In any of the above embodiments, the front end further may include logic and circuitry to receive a candidate instruction and match the candidate instruction to the front end event. In any of the above embodiments, the counter may include logic and circuitry to generate the front end event upon retirement of the candidate instruction. In any of the above embodiments, the front end may include logic and circuitry to mark the candidate instruction to indicate the front end event. In any of the above embodiments, the instruction may retain the mark until retirement. In any of the above embodiments, the front end may include logic and circuitry to ignore the front end event when the candidate instruction is never retired. In any of the above embodiments, the performance monitoring unit includes logic to report an address of the candidate instruction based upon the front end event and retirement of the candidate instruction. In any of the above embodiments, an instruction decode queue may be included, and may itself include logic and circuitry to report a number and position of bubbles. In any of the above embodiments, the counter may include logic and circuitry to generate the front end event further based upon the number of bubbles reported. In any of the above embodiments, a latency counter may be included, and may itself include logic and circuitry to assign an event tag to a subsequent instruction based upon a number of cycles for which the instruction decode queue includes bubbles. In any of the above embodiments, the subsequent instruction may be a first instruction after an allocation window including bubbles. In any of the above embodiments, the instruction decode queue may include logic and circuitry to report a number and position of bubbles. In any of the above embodiments, the latency counter may include logic and circuitry to assign an event tag to a subsequent instruction based upon the number of bubbles and upon a number of cycles for which the number of bubbles are within the instruction decode queue. In any of the above embodiments, the counter further includes logic to filter the front end event based upon a critical filter. The critical filter may indicate a likelihood that the front end event will cause execution delays.

Embodiments of the present disclosure may include a system. In various embodiments, the system may include a front end with circuitry and logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions, an execution unit with circuitry and logic to execute the event instruction and set a register with parameters for supervision of the front end event, a retirement stage with circuitry and logic to retire the event instruction, a counter, and a performance monitoring unit. In any of the above embodiments, the front end further may include logic and circuitry to receive a candidate instruction and match the candidate instruction to the front end event. In any of the above embodiments, the counter may include logic and circuitry to generate the front end event upon retirement of the candidate instruction. In any of the above embodiments, the front end may include logic and circuitry to mark the candidate instruction to indicate the front end event. In any of the above embodiments, the instruction may retain the mark until retirement. In any of the above embodiments, the front end may include logic and circuitry to ignore the front end event when the candidate instruction is never retired. In any of the above embodiments, the performance monitoring unit includes logic to report an address of the candidate instruction based upon the front end event and retirement of the candidate instruction. In any of the above embodiments, an instruction decode queue may be included, and may itself include logic and circuitry to report a number and position of bubbles. In any of the above embodiments, the counter may include logic and circuitry to generate the front end event further based upon the number of bubbles reported. In any of the above embodiments, a latency counter may be included, and may itself include logic and circuitry to assign an event tag to a subsequent instruction based upon a number of cycles for which the instruction decode queue includes bubbles. In any of the above embodiments, the subsequent instruction may be a first instruction after an allocation window including bubbles. In any of the above embodiments, the instruction decode queue may include logic and circuitry to report a number and position of bubbles. In any of the above embodiments, the latency counter may include logic and circuitry to assign an event tag to a subsequent instruction based upon the number of bubbles and upon a number of cycles for which the number of bubbles are within the instruction decode queue. In any of the above embodiments, the counter further includes logic to filter the front end event based upon a critical filter. The critical filter may be to indicate a likelihood that the front end event will cause execution delays.

Embodiments of the present disclosure may include an apparatus. In various embodiments, the apparatus may include means for receiving an event instruction to enable supervision of a front end event that will delay execution of instructions, means for executing the event instruction and setting a register with parameters for supervision of the front end event, and means for retiring the event instruction. In any of the above embodiments, the apparatus may further include means for receiving a candidate instruction and matching the candidate instruction to the front end event. In any of the above embodiments, the apparatus may further include means for generating the front end event upon retirement of the candidate instruction. In any of the above embodiments, the apparatus may further include means for marking the candidate instruction to indicate the front end event. In any of the above embodiments, the instruction may retain the mark until retirement. In any of the above embodiments, the apparatus may further include means for ignoring the front end event when the candidate instruction is never retired. In any of the above embodiments, the apparatus may further include means for reporting an address of the candidate instruction based upon the front end event and retirement of the candidate instruction. In any of the above embodiments, the apparatus may further include means for reporting a number and position of bubbles. In any of the above embodiments, the apparatus may further include means for generating the front end event further based upon the number of bubbles reported. In any of the above embodiments, the apparatus may further include means for assigning an event tag to a subsequent instruction based upon a number of cycles for which the instruction decode queue includes bubbles. In any of the above embodiments, the subsequent instruction may be a first instruction after an allocation window including bubbles. In any of the above embodiments, the apparatus may further include means for reporting a number and position of bubbles. In any of the above embodiments the apparatus may further include means for assigning an event tag to a subsequent instruction based upon the number of bubbles and upon a number of cycles for which the number of bubbles are within the instruction decode queue. In any of the above embodiments, the apparatus may further include means for filtering the front end event based upon a critical filter. The critical filter may indicate a likelihood that the front end event will cause execution delays.

Embodiments of the present disclosure may include a method. In various embodiments, the method may include receiving an event instruction to enable supervision of a front end event that will delay execution of instructions, executing the event instruction and setting a register with parameters for supervision of the front end event, and retiring the event instruction. In any of the above embodiments, the method may further include receiving a candidate instruction and matching the candidate instruction to the front end event. In any of the above embodiments, the method may further include generating the front end event upon retirement of the candidate instruction. In any of the above embodiments, the method may further include marking the candidate instruction to indicate the front end event. In any of the above embodiments, the instruction may retain the mark until retirement. In any of the above embodiments, the method may further include ignoring the front end event when the candidate instruction is never retired. In any of the above embodiments, the method may further include reporting an address of the candidate instruction based upon the front end event and retirement of the candidate instruction. In any of the above embodiments, the method may further include reporting a number and position of bubbles. In any of the above embodiments, t the method may further include generating the front end event further based upon the number of bubbles reported. In any of the above embodiments, the method may further include assigning an event tag to a subsequent instruction based upon a number of cycles for which the instruction decode queue includes bubbles. In any of the above embodiments, the subsequent instruction may be a first instruction after an allocation window including bubbles. In any of the above embodiments, the method may further include reporting a number and position of bubbles. In any of the above embodiments the method may further include assigning an event tag to a subsequent instruction based upon the number of bubbles and upon a number of cycles for which the number of bubbles are within the instruction decode queue. In any of the above embodiments, the method may further include filtering the front end event based upon a critical filter. The critical filter may indicate a likelihood that the front end event will cause execution delays.