Patent ID: 12230314

MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are described below. Note that any of the embodiments described in this specification can be combined as appropriate. In the case where a plurality of structure examples (including operation examples, usage examples, manufacturing method examples, and the like) are described in one embodiment, structure examples can be combined with each other as appropriate. Furthermore, the present invention can be implemented in many different modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope thereof. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments.

The size, the layer thickness, the region, and the like in the drawings are exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. The drawings schematically show ideal examples, and embodiments of the present invention are not limited to shapes, values, and the like shown in the drawings. For example, variation in signal, voltage, or current due to noise or variation in signal, voltage, or current due to difference in timing can be included.

In this specification, terms for describing arrangement, such as “over” and “under” are used for convenience to describe the positional relation between components with reference to drawings in some cases. The positional relation between components is changed as appropriate in accordance with a direction in which components are described. Thus, terms for the description are not limited to those used in this specification, and the description can be changed appropriately depending on the situation.

The positions of circuit blocks in a block diagram shown in a drawing specifies their positional relations just for description, and the positions of circuit blocks of one embodiment of the present invention are not limited thereto. Even when different circuit blocks are illustrated to achieve individual functions in a block diagram, one circuit block may be actually configured to achieve different functions. Functions of circuit blocks are specified for description, and actual circuit blocks may be provided such that processing performed in one circuit block in an illustration is performed in the plurality of circuit blocks.

Embodiment 1

In this embodiment, a DOSRAM (registered trademark) is described as an example of an oxide semiconductor memory device. Note that “DOSRAM” stands for Dynamic Oxide Semiconductor Random Access Memory. A “DOSRAM” is a memory device whose memory cell is a 1T1C (one-transistor one-capacitor) memory cell and has an OS transistor as a write transistor.

Configuration Example of DOSRAM

FIG.1is a functional block diagram showing a configuration example of a DOSRAM. A DOSRAM100inFIG.1includes a control circuit102, a row circuit104, a column circuit105, and a memory cell (MC) and sense amplifier (SA) array120. The row circuit104includes a decoder111, a word line driver112, a column selector113, and a sense amplifier driver114. The column circuit105includes a global sense amplifier block115and an input/output (I/O) circuit116.

Voltages VDDD, VDH, VSSS, and Vbg1, a clock signal CLK, an address signal ADDR, and signals CE, GW, and BW are input to the DOSRAM100. Circuits, signals, and voltages for the DOSRAM100can be selected as appropriate. Another circuit or another signal may be added. Structures (e.g., bit length) of input and output signals to/from the DOSRAM100are set on the basis of the operation, circuit configuration, and the like of the DOSRAM100.

The control circuit102is a logic circuit having a function of controlling the entire operation of the DOSRAM100. The control circuit102has a function of performing a logical operation on the signals CE, GW, and BW to determine an operation and a function of generating control signals for the row circuit104and the column circuit105to make the determined operation executed. Note that the signals CE, GW, and BW are a chip enable signal, a global write enable signal, and a bite write enable signal, respectively.

The DOSRAM100has a hierarchical bit-line architecture. The MC and SA array120includes a plurality of blocks130and a plurality of global bit lines. The block130includes a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. Here, the number of blocks130is No (No is an integer of 1 or greater). Note that when one of the blocks130needs to be specified, a reference numeral130<0> or the like is used; the reference numeral130denotes an arbitrary cell block. The same can be applied to other components, and a reference numeral such as <1> is used to distinguish a plurality of components.

The configurations of the MC and SA array120and the block130are described with reference toFIG.1B. The MC and SA array120has a structure in which a memory cell array125is stacked over a sense amplifier array121. The sense amplifier array121includes N0sense amplifier blocks131, and the memory cell array125includes N0local cell arrays135. The block130has a structure in which the local cell array135is stacked over the sense amplifier block131.

The local cell array135includes a plurality of memory cells20. As illustrated inFIG.1C, the memory cell20includes a transistor Tw1and a capacitor C1, and is electrically connected to a word line WL, a bit line BL (or BLB), a wiring BGL, and a power supply line for the voltage VSSS. The transistor Tw1is an OS transistor having a back gate. The back gate is electrically connected to the wiring BGL. The voltage Vbg1is input to the wiring BGL, for example. The threshold voltage of the transistor Tw1can be changed with the voltage Vbg1. In the local cell array135, the word lines WL, the bit lines BL and BLB, and the wirings BGL are provided in accordance with the arrangement of the memory cells20.

A metal oxide has a band gap of 2.5 eV or wider; thus, an OS transistor has an extremely small off-state current. For example, the off-state current per micrometer in channel width at a source-drain voltage of 3.5 V and room temperature (25° C.) can be lower than 1×10−20A, lower than 1×10−22A, or lower than 1×10−24A. That is, the on/off ratio of drain current can be greater than or equal to 20 digits and less than or equal to 150 digits. Thus, the amount of charge leaking from the retention node through the transistor Tw1is extremely small in the memory cell20. Thus, the DOSRAM100can be used as a nonvolatile memory device.

A metal oxide used for an OS transistor is a Zn oxide, a Zn—Sn oxide, a Ga—Sn oxide, an In—Ga oxide, an In—Zn oxide, an In—M—Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), or the like. In addition, an oxide containing indium and zinc may further contain one or more kinds of elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

For the purpose of improving the reliability and electrical characteristics of the OS transistor, it is preferable that a metal oxide having a crystal part such as a CAAC-OS, a CAC-OS, an nc-OS, or the like be used for the metal oxide used in the semiconductor layer. CAAC-OS stands for c-axis-aligned crystalline metal oxide semiconductor. CAC-OS stands for Cloud-Aligned Composite metal oxide semiconductor. In addition, nc-OS stands for nanocrystalline metal oxide semiconductor.

The CAAC-OS has c-axis alignment, a plurality of nanocrystals thereof are connected in the a-b plane direction, and its crystal structure has distortion. Note that the distortion refers to a portion where the direction of a lattice arrangement changes between a region with a regular lattice arrangement and another region with a regular lattice arrangement in a region where the plurality of nanocrystals are connected.

The CAC-OS has a function of allowing electrons (or holes) serving as carriers to flow and a function of not allowing electrons serving as carriers to flow. The function of allowing electrons to flow and the function of not allowing electrons to flow are separated, whereby both functions can be heightened at the maximum. In other words, when the CAC-OS is used for a channel formation region of an OS transistor, a high on-state current and an extremely low off-state current can be both achieved. Thus, an OS transistor is very suitable for the write transistor of the memory cell.

The sense amplifier block131is provided with a plurality of sense amplifiers132. The sense amplifier132has a function of comparing the voltage of the bit line BL and that of the bit line BLB, and a function of amplifying a voltage difference between the bit line BL and the bit line BLB. Note that two bit lines which are compared concurrently by the sense amplifier132are referred to as a bit line pair. In the example ofFIG.1B, BL and BLB serve as a bit line pair. In this specification, the bit line pair is referred to as the bit line pair (BL, BLB) in some cases.

Since the transistor Tw1is an OS transistor, the local cell array135can be stacked over the sense amplifier block131. With such a stacked structure, the bit line can be shortened. Hereinafter, bit line shortening is described with reference toFIGS.2A to2D.FIG.2Aillustrates a configuration example of the bit line according to one embodiment of the present invention, andFIGS.2B to2Dillustrate comparison examples.

In the comparison example ofFIG.2D, a sense amplifier array and a memory cell array do not have a stacked structure, and the sense amplifier is provided in the column circuit. Thus, in the comparison example ofFIG.2D, a bit line has almost the same length as a memory cell array.

In the comparison example ofFIG.2C, a memory cell array is divided into a plurality of local cell arrays and the local cell arrays are stacked over the sense amplifier block. Thus, the length of the bit line provided in the local cell array can be shortened to a length almost the same as that of the sense amplifier block. In this comparison example, the number of memory cells per bit line (also referred to as CPB) is small. A smaller CPB can shorten the bit line, which reduces the capacitance accompanying to the bit line (also referred to as bit line capacitance).

As in a DRAM including Si transistors, the capacitance Cs of the capacitor C1in the memory cell20is preferably small in light of the operation speed, power consumption, production yield, and the like of the DOSRAM100. A reduction in the bit line capacitance leads to a reduction in the capacitance Cs of the capacitor. When the capacitance Cs is small, the structure of the capacitor C1and the manufacturing process thereof can be simplified. Furthermore, the DOSRAM100can be downsized or can have an increased memory capacity.

FIG.2Bis an enlarged view of part of the local cell array and the sense amplifier block ofFIG.2C. As illustrated inFIG.2B, the local cell array is stacked over the sense amplifier block, whereby the bit line pair (BL, BLB) for connecting the sense amplifier and the memory cell is led both in the local cell array and the sense amplifier block. In this embodiment, a structure example for further reducing the bit line capacitance is disclosed. Specifically, as illustrated inFIG.2A, a bit line is not led in the local cell array. A main conduction portion for the memory cell and the sense amplifier is formed by a conductor provided in a via hole. That is, a bit line in the sense amplifier and a bit line in the local cell array are integrated.

First, a circuit configuration example of the sense amplifier block131and the local cell array135is described with reference toFIG.4. In the example ofFIG.4, the CPB of the local cell array135is 8 and two bit line pairs (BL, BLB) are provided with respect to a global bit line pair (GBL, GBLB).

Signals EQ, EQB, SEN, SENB, and CSEL[3:0] and a voltage Vpre are input to the sense amplifier blocks131. The signals EQB and SENB are inverted signals of the signals EQ and SEN, respectively.

The sense amplifier132includes an equalizer31, a sense amplifier32, and a selector33. The signals EQ and EQB are signals for activating the equalizer31, and the signals SEN and SENB are signals for activating the sense amplifier32. The signals EQ, EQB, SEN, and SENB are generated by the sense amplifier driver114. In the case where a local cell array135<j> is to be accessed (j is an integer of 0 to N0-1), the sense amplifier driver114generates the signals EQ, EQB, SEN, and SENB that make the sense amplifier block131<j> active and the other sense amplifier blocks131inactive. With such control, power consumption of the DOSRAM100can be reduced.

The signal CSEL[3:0] is generated by the column selector113. In response to the signal CSEL[3:0], any one of the four bit line pairs (BL, BLB) is brought into conduction with the global bit line pair (GBL, GBLB).

In the sense amplifier block115, a global sense amplifier140is provided for each global bit line pair (GBL, GBLB). In the input/output circuit116, a write circuit142and a read circuit143are provided for each global bit line pair (GBL, GBLB). The write circuit142has a function of writing data to the global bit line pair (GBL, GBLB). The read circuit143has a function of holding data input to the global bit line pair (GBL, GBLB) and outputting the held data.

The circuit diagram ofFIG.4illustrates that the bit line BL is led in the sense amplifier block131and the local cell array135; however, as shown inFIG.3A, the leading portion for the bit line BL can be provided only in the local cell array135when the sense amplifier block131and the local cell array135are stacked. Note thatFIG.3Acorresponds to the circuit diagram ofFIG.2A.FIG.3Billustrates the circuit diagram ofFIG.2Bas a comparison example.

In the comparison example ofFIG.3B, the leading portion for the bit line BL is provided over the transistor Tw1in the local cell array135. In contrast, in the configuration example ofFIG.3A, this leading portion is not provided in the local cell array135. InFIG.3A, a portion indicated by a dotted line indicates a portion in which the bit line BL is omitted. The length of the bit line BL inFIG.3Ais approximately ½ of that inFIG.3B. A connection structure example of the bit line BL and the memory cell20will be specifically described in Embodiment 3.

The bit line capacitance can be reduced because of the shortened bit line. An index that affects reading performance is the ratio of the bit line capacitance (Cbit) to the capacitance Cs. With a larger Cs/Cbit, a greater potential difference of the bit line pair can be obtained when data is read from the memory cell20. Therefore, a larger Cs/Cbit enables higher-speed or more stable reading operation. Under the condition where the reading performance is constant, a reduction in the bit line capacitance Cbit enables a reduction in the capacitance Cs of the capacitor C. Therefore, the DOSRAM100has excellent reading performance as compared to a conventional DRAM with Si transistors if both of them have the same capacitance Cs of the capacitor C1.

Since the transistor Tw1is an OS transistor with an extremely low off-state current, the DOSRAM100has excellent retention characteristics as compared to a conventional DRAM even when its capacitance Cs is smaller than that of the DRAM. Therefore, the DOSRAM100is preferable because it can have the capacitor C1with smaller capacitance Cs.

In the DOSRAM100, the local cell array135can have a multilayer structure.FIG.5illustrates an example in which the local cell array135is formed with three layers of cell arrays135ato135c. In this configuration example, a leading portion for the bit line BL is provided in the cell array135b, and the transistor Tw1of the cell array135cis electrically connected to this leading portion.

Although the sense amplifier132is formed with a Si transistor in this example, the sense amplifier132may be formed with an OS transistor.

The structure of the bit line disclosed in this embodiment can be used in other oxide semiconductor memory devices. For example, this structure can be used in a NOSRAM (registered trademark). A NOSRAM stands for Nonvolatile Oxide Semiconductor RAM. The NOSRAM is an oxide semiconductor memory device in which its memory cell is composed of a 2T or 3T gain cell and the transistors in the memory cell are OS transistors. For example, the memory cell22illustrated inFIG.6includes three transistors Tw2, Tr2, and Ts2. The transistors Tw2, Tr2, and Ts2are each an OS transistor having a back gate. A capacitor for holding the gate voltage of the transistor Tr2may be provided in the memory cell22. The memory cell22is electrically connected to a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and a source line SL. The write bit line WBL and the read bit line RBL are electrically connected to a sense amplifier. For one or both of the write bit line WBL and the read bit line RBL, the structure of the bit line of this embodiment can be used.

The bit line structure disclosed in this embodiment can be used in a semiconductor device composed of stacked transistors. Shortening the length of the wiring reduces the parasitic capacitance of the wiring, leading to improvement in the performance of the semiconductor device.

Embodiment 2

In this embodiment, an electronic component, an electronic device, and the like including the above-mentioned oxide semiconductor memory device are described.

The above-mentioned oxide semiconductor memory device can be incorporated into a variety of processor chips such as a CPU chip, a GPU chip, an FPGA chip, or an application processor (AP) chip. Here, a configuration example of an AP chip is shown as an example.

An AP chip600illustrated inFIG.7includes a CPU (central processing unit)610, a GPU (graphics processing unit)612, a memory device614, a bus615, an interface unit616, a memory control unit621, an audio processing unit622, a video processing unit623, and a display control unit624. These integrated circuits are provided in one die. Note that circuits provided in the AP chip600are selected as appropriate in accordance with the intended use and the like. The above-mentioned oxide semiconductor memory device is used as the memory device614.

Various kinds of peripheral devices can be controlled with the AP chip600in which a variety of functional circuits are provided. For example, the memory control unit621includes a memory controller, a DRAM controller, and a flash memory controller. The audio processing unit622processes audio data and the like. The video processing unit623includes a video decoder, a video encoder, an image processing circuit for a camera, and the like. A display controller and a multi-monitor controller are provided in the display control unit624.

A memory chip630including the above-mentioned oxide semiconductor memory device and a processor chip640including the above-mentioned oxide semiconductor memory device can be incorporated in a variety of electronic devices. For example, in the electronic device, the memory chip630can be used as a replacement for a DRAM chip or a flash memory chip.FIG.8illustrates some examples of electronic devices in each of which the memory chip630and/or the processor chip640are incorporated.

A robot7100includes an illuminance sensor, a microphone, a camera, a speaker, a display, various kinds of sensors (e.g., an infrared ray sensor, an ultrasonic wave sensor, an acceleration sensor, a piezoelectric sensor, an optical sensor, and a gyro sensor), a moving mechanism, and the like. The processor chip640controls these peripheral devices. The memory chip630stores data obtained by the sensors, for example.

A microphone has a function of detecting acoustic signals of a speaking voice of a user, an environmental sound, and the like. A speaker has a function of outputting audio signals such as a voice and a warning beep. The robot7100can analyze an audio signal input via the microphone and can output a necessary audio signal from the speaker. The robot7100can communicate with a user with the use of the microphone and the speaker.

A camera has a function of taking images of the surroundings of the robot7100. Furthermore, the robot7100has a function of moving with the use of a moving mechanism. The robot7100can take images of the surroundings with the use of the camera, and can analyze the images to sense whether there is an obstacle in the way of the movement.

A flying object7120includes propellers, a camera, a battery, and the like and has a function of flying autonomously. The processor chip640controls these peripheral devices.

For example, image data taken by the camera is stored in the memory chip630. The processor chip640can analyze image data to sense whether there is an obstacle in the way of the movement. Remaining battery power can be estimated with the processor chip640on the basis of the amount of change in the power storage capacity of the battery.

A cleaning robot7140includes a display provided on the top surface, a plurality of cameras provided on the side surface, a brush, an operation button, various kinds of sensors, and the like. Although not illustrated, the cleaning robot7140is provided with a tire, an inlet, and the like. The cleaning robot7140can run autonomously, detect dust, and vacuum the dust through the inlet provided on the bottom surface.

For example, the processor chip640can judge whether there is an obstacle such as a wall, furniture, or a step by analyzing an image taken by the cameras. In the case where an object that is likely to be caught in the brush such as a wiring is detected by image analysis, the rotation of the brush can be stopped.

An automobile7160includes an engine, tires, a brake, a steering gear, a camera, and the like. For example, the processor chip640performs control for optimizing the running state of the automobile7160on the basis of navigation information, the speed, the state of the engine, the gearshift state, the use frequency of the brake, and other data. For example, image data taken by the camera is stored in the memory chip630.

The memory chip630and/or the processor chip640can be incorporated in a TV (television receiving) device7200, a smartphone7210, PCs (personal computers)7220and7230, game consoles7240and7260, and the like.

For example, the processor chip640incorporated in the TV device7200can function as an image processing engine. The processor chip640performs, for example, image processing such as noise removal and resolution up-conversion.

The smartphone7210is an example of a portable information terminal. The smartphone7210includes a microphone, a camera, a speaker, various kinds of sensors, and a display unit. The processor chip640controls these peripheral devices.

The PCs7220and7230are respectively examples of a notebook PC and a desktop PC. To the PC7230, a keyboard7232and a monitor device7233can be connected with or without a wire. The game console7240is an example of a portable game console. The game console7260is an example of a stationary game console. To the game console7260, a controller7262is connected with or without a wire. The memory chip630and/or the processor chip640can be incorporated into the controller7262.

Embodiment 3

In this embodiment, an example of a stacked structure of the DOSRAM100will be described.FIG.9illustrates a cross section of the typical block130. As described above, the local cell array135is stacked over the sense amplifier block131in the block130. Note thatFIG.9corresponds to the cross-sectional view of the circuit diagram inFIG.3A.

As illustrated inFIG.9, the bit line BL and Si transistors Ta10and Ta11are provided in the sense amplifier block131. The Si transistors Ta10and Ta11have a semiconductor layer in a single crystal silicon wafer. The Si transistors Ta10and Ta1constitute the sense amplifier132and are electrically connected to the bit line BL.

In the local cell array135, the two transistors Tw1share a semiconductor layer. A plurality of conductors are stacked between the semiconductor layer and the bit line BL. Through these conductors, the transistor Tw1has electrical continuity with the bit line BL. With such a connection structure, the sense amplifier block131and the local cell array135can share the bit line BL in the local cell array135.

Accordingly, the length of the bit line BL is shortened and the bit line BL does not have a portion intersecting with the word line WL, so that the bit line parasitic capacitance Cbit can be reduced. Accordingly, the memory cell20can be formed with the capacitor C1with small capacitance Cs. For example, the capacitor C1may have a structure illustrated inFIG.10. The area of the capacitor C1is reduced, whereby the area of the memory cell20can be reduced and the DOSRAM100can be downsized.

The connection structures between the semiconductor layer and the wiring illustrated inFIG.9andFIG.10can be used in a variety of semiconductor devices formed by stacking a plurality of circuits including a transistor group.

Metal oxides, insulators, conductors, and the like inFIG.9andFIG.10may each be a single layer or a stack of layers. They can be formed by a variety of deposition methods such as a sputtering method, a molecular beam epitaxy method (MBE method), a pulsed laser ablation method (PLA method), a CVD method, and an atomic layer deposition method (ALD method). Note that examples of a CVD method include a plasma CVD method, a thermal CVD method, and a metal organic CVD method.

In the example illustrated here, the semiconductor layer of the transistor Tw1is formed using three metal oxide layers. These metal oxide layers are formed preferably with the above-mentioned metal oxides, and more preferably with a metal oxide containing In, Ga, and Zn.

Note that when an element that can form an oxygen vacancy or an element that can be bonded to an oxygen vacancy is added to a metal oxide, the carrier density is increased and the resistance is reduced in some cases. For example, when a semiconductor layer with a metal oxide is selectively reduced in resistance, a source region and a drain region can be provided in the semiconductor layer.

Typical examples of an element that reduces the resistance of a metal oxide include boron and phosphorus. Moreover, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas, or the like may be used. Typical examples of the rare gas element include helium, neon, argon, krypton, and xenon.

For example, when a dummy gate is used, the resistance of the semiconductor layer can be selectively reduced. Specifically, the dummy gate is provided over the semiconductor layer with an insulating layer therebetween, and the above-described element is added to the semiconductor layer using the dummy gate as a mask. Thus, the element is added to a region of the semiconductor layer that does not overlap with the dummy gate, so that the resistance of the region is reduced. As methods for adding a dopant, an ion implantation method in which an ionized source gas is subjected to mass separation and then added, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, and the like can be given.

Examples of conductive materials used for the conductors include a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus; silicide such as nickel silicide; a metal such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium; a metal nitride containing the above metal as its component (tantalum nitride, titanium nitride, molybdenum nitride, or tungsten nitride); and the like. Moreover, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

Examples of insulating materials used for the insulators include aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate. In this specification and the like, an oxynitride refers to a compound whose oxygen content is higher than nitrogen content, and a nitride oxide refers to a compound whose nitrogen content is higher than oxygen content.

REFERENCE NUMERALS

20,22: memory cell,31: equalizer,32: sense amplifier,33: selector,100: DOSRAM,102: control circuit,104: row circuit,105: column circuit,111: decoder,112: word line driver,113: column selector,114: sense amplifier driver,115: global sense amplifier block,116: input/output circuit,120: memory cell and sense amplifier (MC and SA) array,121: sense amplifier array,125: memory cell array,130: block,131: sense amplifier block,132: sense amplifier,135: local cell array,135a,135b,135c: cell array,140: global sense amplifier,142,143: circuit,600: AP (application processor) chip,614: memory device,615: bus,616: interface unit,621: memory control unit,622: audio processing unit,623: video processing unit,624: display control unit,630: memory chip,640: processor chip,7100: robot,7120: flying object,7140: cleaning robot,7160: automobile,7200: TV device,7200: device,7210: smartphone,7220,7230: PC,7232: keyboard,7233: monitor device,7240: game console,7260: game console,7262: controller