Patent ID: 12223249

DETAILED DESCRIPTION OF SOME EXAMPLE EMBODIMENTS

Hereinafter, some example embodiments according to the technical spirit of inventive concepts will be described with reference to the accompanying drawings. In the descriptions ofFIGS.1to18, substantially the same elements are denoted by the same reference numerals, and overlapping descriptions of the elements will be omitted. Throughout several drawings of inventive concepts, like reference numerals are used for like elements.

As used herein, the term “module” and/or “system” may include a unit implemented in hardware, software, or firmware and may be used interchangeably with other terms such as “logic,” “logic block,” “part,” and “circuitry.” A module may be a single integral element or a minimum unit or a part thereof adapted to perform one or more functions. For example, according to an embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

FIG.1is a block diagram illustrating an etch-modeling system according to some example embodiments of inventive concepts.FIG.2is a block diagram illustrating a sample select module according to some example embodiments of inventive concepts.

Referring toFIGS.1and2, an etch-modeling system1may include an observing apparatus100and a modeling apparatus200.

The observing apparatus100may image a substrate on which a pattern is formed. The observing apparatus100according to some example embodiments of inventive concepts may image a semiconductor substrate or an etched semiconductor substrate. An image I of a semiconductor substrate captured by the observing apparatus100may be a scanning electron microscope (SEM), such as a critical-dimension SEM (CDSEM), image or an intensity map image, and for convenience of description, the image I of the semiconductor substrate is referred to as an “SEM image.” However, example embodiments according to the technical spirit of inventive concepts are not limited thereto.

The observing apparatus100may be in the same facility, e.g. a cleanroom, wherein the pattern is formed; alternatively the observing apparatus100may be in another facility, e.g. a laboratory, in a location different from where the pattern is formed. Still further the modeling apparatus200may be in the same facility, e.g. the cleanroom, wherein the pattern is formed; alternative the modeling apparatus200may be in another facility, e.g. in a location different from where the pattern is formed.

According to a subject to be imaged by the observing apparatus100, the SEM image I may be, or correspond to, an after cleaning inspection (ACI) image and/or an after development inspection (ADI) image. When the observing apparatus100provides the SEM image I to the modeling apparatus200for an etch-modeling operation, the SEM image I may be an ACI SEM image ACI_I. When an imaging operation is performed, a pattern formed on the substrate may be a photoresist pattern and/or a target pattern (e.g. a hardmask target pattern) formed with a photoresist pattern.

The observing apparatus100according to some example embodiments may include an electron gun to capture the ACI SEM image ACI_I. The electron gun may be implemented as at least one of a thermionic electron gun, a field emission electron gun, or the like, and the ACI SEM image ACI_I may be or include features of between 2 nm to 10 nm. The ACI SEM image ACI_I may be in an appropriate format, such as but not limited to a JPEG format, and/or a TIFF format, and/or a bitmap format. However, the technical spirit of inventive concepts is not limited to the above example embodiments.

The modeling apparatus200may include a layout processing system210, a sample select module220, an edge placement (EP) extract module230, an etch-modeling module240, and a validation module250.

The layout processing system210may provide layout data LD of a plurality of target patterns that are formed on the substrate, which is or will be a subject of etch modeling, and/or layout data LD of mask patterns for forming the plurality of target patterns to the sample select module220. According to an example embodiment, the layout data LD may be data reflecting optical proximity correction. The layout data LD may be formatted in an appropriate format, such as but not limited to a graphic design system (GDSII) and/or another appropriate format. The technical spirit of inventive concepts is not limited to the form of layout data.

The layout processing system210may be disposed in the modeling apparatus200to provide the layout data LD to the sample select module220. According to some example embodiments, however, the layout processing system210may be disposed outside the modeling apparatus200to provide the layout data LD to the sample select module220through a direct (e.g., wired) communication channel and/or a wireless communication channel.

The sample select module220may include a unique pattern extraction unit221, a density calculation unit222, a population calculation unit223, and a sampling unit224.

The unique pattern extraction unit221may extract a plurality of unique patterns, e.g. uniquely shaped and/or uniquely sized and/or uniquely oriented patterns, for implementing a plurality of patterns in the layout data LD from the layout data LD, and may extract a plurality of pieces of unique pattern data regarding the plurality of unique patterns.

Each of the unique patterns may be or corresponds to a pattern set which has a unique form (such as at least one of a unique shape, a unique size, or a unique orientation) and includes a single short pattern or a plurality of short patterns. The plurality of patterns representing the layout data LD may be implemented as a plurality of unique patterns UP extracted by the unique pattern extraction unit221.

Some unique patterns UP may have a unique form, such as an align mark, and/or a unique form in which a plurality of short patterns are gathered.

Accordingly, the unique pattern extraction unit221according to some example embodiments may extract unique pattern data on the unique patterns UP and may provide the unique pattern data to the density calculation unit222and the population calculation unit223.

The density calculation unit222may calculate a density value UP_d of each of the unique patterns UP. The density values UP_d are indicators representing characteristics of the unique patterns UP, and each of the density values UP_d is or corresponds to a ratio, e.g. an area actually occupied by all patterns in each of the unique patterns UP compared to the area of a region including all patterns in each of the unique patterns UP. The density value UP_d may not have a unit and may be represented as a percentage, or a ratio, or a percentile, according to some example embodiments.

The density calculation unit222may provide data of a plurality of density values UP_d for the plurality of unique patterns UP to the sampling unit224.

The population calculation unit223may calculate a population UP_p of each of the unique patterns UP (e.g. may calculate a count or a number of instances of each of the unique patterns UP), calculate a population (e.g. a count or a number of instances) of each of the unique patterns UP in the layout data LD, and provide data of the plurality of populations UP_p of the plurality of unique patterns UP to the sampling unit224.

The sampling unit224may receive the data of the density values UP_d and the populations UP_p of the plurality of unique patterns UP for implementing the layout data LD and may classify the plurality of unique patterns UP into a plurality of groups by grouping the plurality of unique patterns UP on the basis of the data of the density values UP_d.

In each group, the sampling unit224may perform sampling by selecting some unique patterns, e.g. a subset of the unique patterns and not all of the unique patterns, on the basis of certain rules for the density values UP_d and the populations UP_p. The sampling unit224may sample a plurality of patterns SP corresponding to the selected unique patterns from the layout data LD, and may provide data of the sampled patterns SP to the EP extract module230.

The sampling unit224may perform a random sampling procedure to select some unique patterns. For example, the sampling unit224may sample unique patterns based on a random-number generated, and/or based on a hash function. However, example embodiments are not limited thereto.

The EP extract module230may receive the ACI SEM image ACI_I from the observing apparatus100, receive sampled pattern data SP_D from the sample select module220, and extract an SEM image of the sampled patterns SP from the ACI SEM image ACI_I.

The EP extract module230may extract EP data EP_D, which is or corresponds to contour data representing the edge of the sampled patterns SP, from the SEM image of the sampled patterns SP, and the EP data EP_D may be represented as coordinate data. The EP extract module230may provide the EP data EP_D to the etch-modeling module240.

The etch-modeling module240may receive the EP data EP_D from the EP extract module230, receive ADI EP data EP_ADI of the ADI SEM image, which is an SEM image before etching is performed and may include an image of photoresist, and perform etch modeling on the basis of the EP data EP_D and the ADI EP data EP_ADI to generate and provide modeling data M_D to the validation module250and/or to a semiconductor manufacturing equipment (not shown) including etching equipment.

The modeling data M_D may indicate an open ratio which represents an average density value of the plurality of patterns in the layout data LD and/or interval data between the plurality of patterns in the layout data LD.

The validation module250may receive arbitrary ADI EP data EP_ADI and the modeling data M_D to perform an etching simulation, and may compare a result of the etching simulation with an ACI SEM image ACI_I, which is a result of an etching operation, to generate an effective validation value. The effective valuation value may be a value such as a root mean square (RMS), for example a value representing the square root of the squared difference between the ACI SEM image ACI_I and the etching simulation, and may validate a modeling operation of the etch-modeling module240.

FIG.3is a flowchart illustrating a method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.FIG.4is a flowchart illustrating a sampling operation of the sample select module according to some example embodiments of inventive concepts.FIGS.5to8are diagrams and graphs illustrating a sampling operation of the sample select module according to some example embodiments of inventive concepts.

Referring toFIGS.1,3, and4, the layout processing system210may provide layout data LD to the sample select module220, and the sample select module220may receive the layout data LD including pattern data on a plurality of patterns (S110).

The sample select module220performs sampling on the plurality of patterns in the layout data LD (S120). The unique pattern extraction unit221extracts a plurality of unique patterns on the basis of the layout data LD (S121).

Referring toFIGS.5and6further, the sample select module220may perform a sampling operation on a plurality of patterns to be disposed in a layout region R on a semiconductor substrate10. The semiconductor substrate100may be a wafer, for example may be a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer; however, example embodiments are not limited thereto. The semiconductor substrate100may be a silicon substrate or a silicon-on-insulator (SOI) substrate or a gallium-arsenide substrate or another commonly used substrate; however, example embodiments are not limited thereto. For convenience of description, the layout region R is shown as a partial region of the semiconductor substrate10. However, considering that an etching operation may be performed in units of a wafer, the layout region R may indicate the entire semiconductor substrate10. Furthermore, although the layout region R only includes a plurality of die (not labeled) and does not extend to the edge of the substrate100, this is for illustrative purposes only, and example embodiments are not limited thereto. Furthermore, the die may or may not be square-shaped.

Within the layout region R, for example within a region of one of the plurality of dies in the layout region R, the layout data LD may include first to nthpatterns P_1to P_n (n is a natural number greater than or equal to two), and the first to nthpatterns P_1to P_n may be implemented as first to Nthunique patterns UP_1to UP_N (N is a natural number greater than or equal to two). According to an example embodiment, n and N may be different natural numbers.

In the following process, the first to nthpatterns P_1to P_n may be formed using an extreme ultraviolet (EUV) patterning technology. Accordingly, a critical dimension (CD) of the first patterns P_1among the first to nthpatterns P_1to P_n in the layout data LD may be 3 nm to 4 nm, and a pitch between the first patterns P1may also be designed to be 3 nm to 4 nm. However, example embodiments are not limited thereto, and the first to nth patterns P_1to P_n may be formed using another patterning technology such as a deep ultraviolet (DUV) patterning technology.

The unique pattern extraction unit221may extract N unique patterns, for example, the first to Nthunique patterns UP_1to UP_N from the first to nthpatterns P_1to P_n in the layout data LD.

The first unique pattern UP_1may include the plurality of first patterns P_1, the second unique pattern UP_2may include the second pattern P_2and the third pattern P_3, the third unique pattern UP_3may include the third pattern P_3, and the Nthunique pattern UP_N may include the plurality of nthpatterns P_n. The inclusion relation is illustrative and intended to facilitate description, and the technical spirit of inventive concepts is not limited to the inclusion relation.

Different unique patterns may have a difference in at least one of a structure, a size, an orientation, and a contour profile; however, example embodiments are not limited thereto. For example, different unique patterns may be dissimilar and/or may not be congruent; however, example embodiments are not limited thereto.

The unique pattern extraction unit221may provide data of the extracted first to Nthunique patterns UP_1to UP_N to the density calculation unit222and the population calculation unit223.

FIG.7is a graph showing density values UP_d and populations UP_p of the first to Nthunique patterns UP_1to UP_N. Referring toFIG.7further, the density calculation unit222calculates first to Nthdensity values UP_d1 to UP_dN (e.g. a ratio of open areas to pattern areas) of the extracted first to Nthunique patterns UP_1to UP_N, and the population calculation unit223calculates first to Nthpopulations UP_p1 to UP_pN of the first to Nthunique patterns UP_1to UP_N (S122).

The density calculation unit222may provide data of the first to Nthdensity values UP_d1 to UP_dN to the sampling unit224, and the population calculation unit223may provide data of the first to Nthpopulations UP_p1 to UP_pN to the sampling unit224.

The sampling unit224may classify the first to Nthunique patterns UP_1to UP_N into first to tenth density groups D1to D10on the basis of the first to Nthdensity values UP_d1 to UP_dN (S123). The patterns may be classified into ten groups by means of example, and the number of groups may vary depending on example embodiments. The number of groups is a natural number greater than or equal to two.

As an example, the first unique pattern UP_1may be classified into the eighth density group D8, the second unique pattern UP_2may be classified into the second density group D2, the third unique pattern UP_3may be classified into the third density group D3, and the fourth unique pattern UP_4may be classified into the first density group D1.

Since density values may be indicators representing characteristics of unique patterns, the etch-modeling system1can increase the reliability of etch modeling by grouping unique patterns having similar pattern characteristics through a grouping and/or classification operation based on the density values, and then sampling a combination of unique patterns similar to actual patterns.

The sampling unit224may perform a sampling operation on the basis of the first to Nthdensity values UP_d1 to UP_dN and the first to Nthpopulations UP_p1 to UP_pN (S124).

Referring toFIG.8, the sampling unit224according to some example embodiments may select the same number of unique patterns from the first to tenth density groups D1to D10as a plurality of sampled patterns. As an example, two unique patterns may be selected from each of the density groups D1to D10such that first to twentieth sampled patterns SP_1to SP_20may be sampled, and sampled pattern data SP_D may be provided to the EP extract module230.

For example, the second sampled pattern SP_2may correspond to the fourth unique pattern UP_4, the third sampled pattern SP_3may correspond to the third unique pattern UP_3, and the fifteenth sampled pattern SP_15may correspond to the first unique pattern UP_1. However, example embodiments are not limited thereto.

Alternatively or additionally, the total number of the sampled patterns SP_1to SP_20sampled by the sampling unit224is required to be larger than a number A. The number A may be predetermined, and/or may be provided to the sampling unit224, and/or may be determined dynamically by the sampling unit224. Under this condition, the etch-modeling system1may ensure the reliability of a modeling operation. When the sampled patterns SP_1to SP_20do not satisfy the condition related to the total number, the sampling unit224may repeat sampling.

FIG.9is a graph illustrating a sampling operation of a sample select module according to some other example embodiments of inventive concepts. Operations of the sample select module according to some other example embodiments of inventive concepts will be described below with reference toFIGS.7and9. Differences from the operations of the sample select module shown inFIG.8will be mainly described.

Unlike the sampling unit ofFIG.8, the sampling unit224ofFIG.9may perform sampling by selecting a unique pattern having the largest population count in each of the density groups D1to D10. Accordingly, first to tenth sampled patterns SP_1′ to SP_10′ having the largest population count in the first to tenth density groups D1to D10may be selected in a sampling operation.

FIGS.10to15are diagrams illustrating an etch-modeling operation of the method of manufacturing or fabricating a semiconductor device according to some example embodiments of inventive concepts.

Referring toFIGS.10to15, the observing apparatus100may emit electron beams E to the semiconductor substrate10, on which a pattern P is formed, on a stage300to image the pattern P. Accordingly, the observing apparatus100acquires an ACI SEM image ACI_I of the pattern P and provides the acquired ACI SEM image ACI_I to the modeling apparatus200.

The pattern P on the semiconductor substrate10may be or may include a wafer pattern formed of a photoresist pattern, and thus the SEM image I may be an ACI image. However, the technical spirit of inventive concepts is not limited to the image example. For example, the SEM image I may be an image based on an optical model.

The EP extract module230receives the ACI SEM image ACI_I from the observing apparatus100, receives the sampled pattern data SP_D from the sample select module220, and extracts the EP data EP_D of the sampled pattern SP on the basis of the ACI SEM image ACI_I and the sampled pattern data SP_D (S130).

FIG.11is a diagram only showing the sampled patterns SP in the ACI SEM image ACI_I, andFIG.12is an enlarged view of a fifteenth region R15ofFIG.11.FIG.13is a diagram obtained by extracting EP data from the ACI SEM image ACI_I ofFIG.11, andFIG.14is an enlarged view of the fifteenth region R15ofFIG.13.

Referring toFIGS.11to14, the fifteenth sampled pattern SP_15corresponds to the first unique pattern UP_1, and corresponds to the plurality of first patterns P_1ofFIG.6. All patterns in the fifteenth sampled pattern SP_15may be included in the fifteenth region R15, and a density value SP_d15 of the fifteenth sampled pattern SP_15may be a percentage or a ratio of an actual area occupied by the fifteenth sampled pattern SP_15in the fifteenth region R15to the area of the fifteenth region R15.

In the ACI SEM image ACI_I, the fifteenth sampled pattern SP_15represents the edge of the fifteenth sampled pattern SP_15and may include a white band WB15that is a region in which contrast is changed. The EP extract module230may extract EP data EP_D of the fifteenth sampled pattern SP_15through the fifteenth white band WB15.

In some example embodiments, the EP extract module230may represent and store the EP data EP_D of the fifteenth sampled pattern SP_15in two dimensions, for example, in the form of (x coordinate, y coordinate), and provide the EP data EP_D to the etch-modeling module240.

Since the extraction operation is applied to other sampled patterns in the same way, descriptions of other sampled patterns are replaced with the extraction operation for the fifteenth sampled patterns SP_15.

FIG.15is a diagram illustrating ADI EP data EP_ADI corresponding to the fifteenth sampled pattern SP_15and EP data of the fifteenth sampled pattern SP_15.

The etch-modeling module240performs etch modeling on the basis of the EP data EP_D (S140). Referring toFIG.15, the etch-modeling module240may perform etch modeling by causing contour data of the fifteenth sampled pattern SP_15and contour data of a fifteenth developed pattern DP_15in the ADI EP data EP_ADI corresponding to the fifteenth sampled pattern SP_15to correspond to each other, e.g. on a one-to-one basis.

Modeling may be performed on the basis of the EP data EP_D and displacement differences Δr between the pieces of contour data corresponding to the EP data such that the modeling data M_d including an average density value, an average open ratio, or the like, which is a parameter input from the semiconductor manufacturing equipment, may be generated.

Referring back toFIG.3, a semiconductor device may be fabricated on the basis of the etch modeling generated by the etch-modeling model2450(S150).

FIG.16is a flowchart illustrating an etching model validation operation of the method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.FIGS.17and18are a diagram and graphs illustrating the etching model validation operation of the method of manufacturing a semiconductor device according to some example embodiments of inventive concepts.

Referring toFIGS.16to18, the validation module250may receive arbitrary ADI EP data EP_ADI and the modeling data M_D and perform an etching simulation (S310).

The validation module250may be set to an average density value or an average open ratio to perform an etching simulation operation on the arbitrary ADI EP data EP_ADI and generate simulation data SD.

The validation module250receives an ACI SEM image ACI_I corresponding to the arbitrary ADI EP data EP_ADI and compares the ACI SEM image ACI_I with first simulation data SD1included in the simulation data SD (S320).

The validation module250causes contour data of an arbitrary first point P1in the first simulation data SD1and contour data of a first ACI point P1′, which corresponds to the first point P1, in a first ACI pattern ACI_P_1of the ACI SEM image ACI_I to correspond to each other, e.g. on a one-to-one basis, generates displacement differences Δr1′ between the pieces of contour data, and calculates a value such as an RMS value on the basis of the plurality of generated displacement difference values (S330). The smaller the RMS value, the more consistent the ACI SEM image ACI_I and the simulation result.

An RMS generated by an EP gauge base model, which is generated by the etch-modeling system1of inventive concepts, is 0.49. An RMS generated by a CD gauge base model, which does not have the technical characteristics of inventive concepts, that is, which does not perform the sampling operation, is 1.02. Thus, it may be possible to see that modeling data generated by the etch-modeling system1of inventive concepts has high or improved reliability.

The etch-modeling system1of inventive concepts performs modeling to reflect an etching environment of actual patterns by sampling target patterns to be actually fabricated in consideration of a density value, which is a pattern characteristic, and the total number of patterns, thereby increasing the reliability. Also, the etch-modeling system1can increase the reliability by performing modeling on the basis of EP data.

Alternatively or additionally, when etch modeling is performed through the etch-modeling system1of inventive concepts, it may be unnecessary to separately form a pattern for modeling. Since it is unnecessary to fabricate a modeling mask, it may be more efficient in terms of cost.

As used herein, the term “module” or “system” may include a unit implemented in hardware, software, or firmware and may be interchangeably used with other terms such as “logic,” “logic block,” “part,” or “circuitry.” A module may be a single integral element or a minimum unit or a part thereof adapted to perform one or more functions. For example, according to an embodiment, a module may be implemented in the form of an ASIC.

The method of inventive concepts may be included and provided in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a universal serial bus (USB) medium) or distributed (downloaded or uploaded) online or between two user devices (e.g., smart phones) directly. When distributed online, at least a part of the computer program product may be temporarily generated or at least temporarily stored in the machine-readable storage medium such as memory of the manufacturer's server, a server of the application storage, or a relay server.

Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

Some example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art, features, characteristics, and/or elements described in connection with a particular example embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Furthermore example embodiments described herein are not necessarily mutually exclusive. For example, some example embodiments may include features associated with a first figure, and also may include features associated with another figure. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of example embodiments as set forth in the following claims.