Patent ID: 12200857

DETAILED DESCRIPTION

Hereinafter, package devices of embodiments of the present disclosure are detailed in the following description. It should be understood that many different embodiments provided below are implemented to different aspects. The following specific components and arrangements describe some embodiments just for simplicity and clarity. Of course, these are just for example and not for limitation. In addition, similar components may be labeled with similar and/or corresponding reference numerals in different embodiments for clarity of description. However, these similar reference numbers just describe some embodiments simply and clearly, and do not mean that there is any relationship between different embodiments and/or structures discussed herein.

When a first layer is located on or above a second layer, the first layer may be in direct contact with the second layer. Alternatively, one or more other layers may be spaced between them, and in such case, the first layer may not be in direct contact with the second layer.

The contents of the present disclosure will be described in detail with reference to specific embodiments and drawings. In order to make the contents clearer and easier to understand, the following drawings may be simplified schematic diagrams, and components therein may not be drawn to scale. The numbers and sizes of the components in the drawings are just illustrative, and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the specification and the appended claims of the present disclosure to refer to specific components. Those skilled in the art should understand that electronic equipment manufacturers may refer to a component by different names, and this document does not intend to distinguish between components that differ in name but not function. In the following description and claims, the terms “comprise”, “include” and “have” are open-ended fashion, so they should be interpreted as “including but not limited to . . . ”. It should also be understood that when a component is said to be “coupled” to another component (or a variant thereof), it may be directly connected to another component or indirectly connected (e.g., electrically connected) to another component through one or more components.

When ordinal numbers, such as “first” and “second”, used in the specification and claims are used to modify components in the claims, they do not mean and represent that the claimed components have any previous ordinal numbers, nor do they represent the order of a claimed component and another claimed component, or the order of manufacturing methods. These ordinal numbers are just used to distinguish a claimed component with a certain name from another claimed component with the same name.

When a component (e.g., film or region) is called “on another component”, it may be directly on the another component, or there may be other components in between. On the other hand, when a component is called “directly on another component”, there is no component between them. In addition, when a component is called “on another component”, there is an upper and lower relationship between the two components in a top view direction, and this component may be above or below the other component, and this upper and lower relationship depends on the orientation of the device.

In this document, the terms “about”, “substantially” and “approximately” usually mean within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range. The quantity given here is about the quantity, that is, without specifying “about”, “substantially” and “approximately”, the meanings of “about”, “substantially” and “approximately” may still be implied. In addition, the term “range from a first value to a second value” means that the range includes the first value, the second value and other values between them.

It should be understood that according to the following embodiments, features of different embodiments may be replaced, recombined or mixed to constitute other embodiments without departing from the spirit of the present disclosure. As long as the features of the embodiments do not violate the inventive spirit or conflict with each other, they can be mixed and used at will.

In the present disclosure, the thicknesses, lengths and widths may be measured by optical microscope, in which the thicknesses may be measured from cross-sectional image obtained by electron microscope, but the present disclosure is not limited to this. In addition, any two values or directions used for comparison may have certain errors. If a first value is equal to a second value, it implies that there may be about 10% error between the first value and the second value; if a first direction is perpendicular to a second direction, an angle between the first direction and the second direction may range from 80 degrees to 100 degrees; and if the first direction is parallel to the second direction, the angle between the first direction and the second direction may range from 0 to 10 degrees.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as those commonly understood by those skilled in the art to which the present disclosure belongs. It can be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as meanings consistent with the background or context of related technologies and the present disclosure, and should not be interpreted in an idealized or overly formal way, unless it is specifically defined in the embodiments of the present disclosure.

FIG.1schematically illustrates a top view of a test mark according to a first embodiment of the present disclosure, andFIG.2schematically illustrates a cross-sectional view of a package device according to the first embodiment of the present disclosure, in which a right part ofFIG.2schematically illustrates a cross-section view taken along a line A-A′ shown inFIG.1. For clearly illustrating the package device1of this embodiment,FIG.2shows a part of the cross-sectional structure, but the present disclosure is not limited thereto. As shown inFIG.2, the package device1may include a redistribution layer14, in which the redistribution layer14may have a test mark12for inspecting the warpage degree or warpage tendency of a carrier (e.g., a carrier16shown inFIG.3) and layers of the redistribution layer14during processes for manufacturing the redistribution layer14. In some embodiments, the package device1may include an electronic component CE disposed on the redistribution layer14. For example, the electronic component CE may include a chip, a passive component, or other suitable components, and is not limited herein. In some embodiments, the redistribution layer14may be a fan-out circuit structure formed on a wafer, for instance.

In the embodiment ofFIG.2, the redistribution layer14may include a first dielectric layer141, a conductive layer142, and a second dielectric layer143, and the conductive layer142may be disposed between the first dielectric layer141and the second dielectric layer143. For example, the conductive layer142may include a metal material, such as including copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), nickel (Ni), other suitable materials or any combination thereof, but the present disclosure is not limited thereto. A thickness T1 of the conductive layer142may, for example, range from 4 microns (μm) to 5 μm (4 μm≤the thickness T1≤5 μm), but not limited thereto. The first dielectric layer141and/or the second dielectric layer143may include photosensitive polyimide or other suitable dielectric materials, for example, but the present disclosure is not limited herein. A thickness T2 of the first dielectric layer141and/or a thickness T3 of the second dielectric layer143may, for example, range from 4 μm to 7 μm (4 μm≤the thickness T2≤7 μm; 4 μm≤the thickness T3≤7 μm), but not limited thereto. The thickness T1 of the conductive layer142may refer to as a maximum thickness of a part of the conductive layer142that does not extend into a through hole (e.g., a through hole141aas mentioned in following contents) in a top view direction TD. The thickness T2 of the first dielectric layer141or the thickness T3 of the second dielectric layer143may refer to as a maximum thickness of a part of the dielectric layer which does not overlap the conductive layer covered by this dielectric layer in the top view direction TD, as shown inFIG.1.

As shown inFIG.1andFIG.2, the redistribution layer14may further include at least one trace142a, in which the trace142ais formed of the conductive layer142, the test mark12may include a plurality of conductive patterns121formed of the conductive layer142, and the plurality of conductive patterns121are arranged in a ring shape. The phrase of “the conductive patterns121are arranged in a ring shape” means that as viewed along the top view direction TD of the package device1, the test mark12may have a center121c(substantially corresponding to a center of the test mark12), and these conductive patterns circle the center121cand are arranged in the ring shape. In some embodiments, shapes of the conductive patterns may be substantially the same. In some embodiments, the trace142amay be electrically connected to the electronic component CE disposed on the redistribution layer14, for example, the trace142amay be electrically connected to the electronic component CE through other conductive layers or conductive components. In some embodiments, the trace142amay be electrically isolated from the test mark12, but not limited thereto. In some embodiments, the conductive patterns121may, for example, be arranged outwardly in a radial shape with the center121cas a center. For example, the conductive patterns121may include a conductive pattern1211, a conductive pattern1212, and a conductive pattern123, and/or other conductive patterns (not labeled), which are arranged in the ring shape substantially around the center121cin sequence. In some embodiments, the conductive patterns121may extend along different extending directions. For example, the conductive pattern1211may extend along an extending direction RD1, the conductive pattern1212may extend along an extending direction RD2, and the conductive pattern1213may extend along an extending direction RD3. The extending direction RD1, the extending direction RD2, and the extending direction RD3 may be different from each other, for example.

InFIG.1, an angle θA may be between the extending directions of any two adjacent conductive patterns121of the conductive patterns121, for example, and these angles θA may substantially the same, but not limited thereto. For example, an angle θA may be between the extending direction RD1 of the conductive pattern1211and the extending direction RD2 of the conductive pattern1212, another angle θA may be between the extending direction RD2 of the conductive pattern1212and the extending direction RD3 of the conductive pattern1213, and the angle θA may be substantially equal to the another angle θA, but not limited to this. In some embodiments, these angles θA may be, for example, range from 10 degrees to 45 degrees (10 degrees≤the angles θA≤45 degrees) or other suitable angle ranges, and the ranges of the angles θA may be adjusted according to the number of the conductive patterns121of one test mark12, but not limited thereto. In other embodiments (not shown), the angle θA between the extending direction RD1 of the conductive pattern1211and the extending direction RD2 of the conductive pattern1212may be different from the angle θA between the extending direction RD2 of the conductive pattern1212and the extending direction RD3 of the conductive pattern1213.

In the embodiment ofFIG.1, the conductive patterns121(e.g., the conductive pattern1211, the conductive pattern1212and the conductive pattern1213) are strip-shaped and have substantially the same width W1. The width W1 is defined as a maximum width of the conductive pattern121in a direction perpendicular to the extending direction of the conductive pattern121(e.g., the extending direction RD1, the extending direction RD2 or the extending direction RD3), but not limited thereto. In some embodiments, each of the conductive patterns121(e.g., the conductive pattern1211, the conductive pattern1212and the conductive pattern1213) may have a maximum width and a minimum width in a direction perpendicular to its extending direction, respectively, and a ratio of the maximum width to the minimum width may be range from 0.8 to 1.2 (0.8≤the ratio≤1.2). When the ratio of the maximum width to the minimum width is within the above range, it may consider that the conductive pattern with this ratio has substantially the same width W1, but not limited thereto. In the embodiment ofFIG.1, each of the conductive patterns (e.g., the conductive pattern1211, the conductive pattern1212and the conductive pattern1213) may have a length L1, which is defined as a maximum length of this conductive pattern121along the extending direction (e.g., extending direction RD1, extending direction RD2 or extending direction RD3) of this conductive pattern121. In some embodiments, the lengths L1 of the conductive patterns121may optionally be designed to be the same or different, but not limited thereto.

In this embodiment, when the conductive layer142warps, the widths W1 of some of the conductive patterns121may have obvious changes or differences in different parts. For example, the ratio of the maximum width to the minimum width of one of the conductive patterns121may not be within the above range, so that the warping direction or warpage position may be determined by comparing the ratio of the maximum widths to the minimum widths of the conductive patterns121or comparing the maximum widths (or minimum widths) of different conductive patterns121. Accordingly, the warpage degree or warpage tendency may be determined. The present disclosure is not limited herein. In this way, the process conditions may be improved or monitored in real time so as to improve the process yield.

In some embodiments, the conductive patterns (e.g., the conductive pattern1211, the conductive pattern1212, and the conductive pattern1213) may have substantially the same shape and size, but not limited thereto. In some embodiments (not shown), the conductive patterns (the conductive pattern1211, the conductive pattern1212, and the conductive pattern1213) may extend to the center121cto be connected to each other, but not limited thereto. In other embodiments, the conductive patterns (the conductive pattern1211, the conductive pattern1212, and the conductive pattern1213) may be adjusted to be wavy or other suitable shapes according to requirements, but not limited thereto.

In the embodiment ofFIG.1, a varying or uneven distance may be between adjacent two conductive patterns121(e.g., the conductive pattern1211, the conductive pattern1212, and the conductive pattern1213). The distance may be defined as a distance (spacing) spaced between adjacent two conductive patterns. For example, in the embodiment ofFIG.1, the test mark12may have a center121c, and the center121cmay optionally correspond to or not correspond to the conductive patterns121. For example, the center121cofFIG.1may not correspond to the conductive patterns121. In some embodiments, the distance between two adjacent conductive patterns121may increase, for example, in a direction away from the center121c, but not limited thereto. In some embodiments (not shown), the distance between two adjacent conductive patterns121may decrease, for example, in the direction away from the center121c. The above increase or decrease may not be limited to be increased or decreased proportionally. For example, a first distance d1A and a second distance d2A may be between adjacent two conductive patterns (e.g., the conductive pattern1211, the conductive pattern1212, and the conductive pattern1213). The first distance d1A may be defined as a distance (spacing) between adjacent two conductive patterns located on a dotted line C1 closest to the center121c, the second distance d2A may be defined as a distance (spacing) between adjacent two conductive patterns located on a dotted line C2 farthest from the center121c, and the first distance d1A is greater than the second distance d2A, but not limited thereto. As shown inFIG.1, the above-mentioned dotted line C1 is, for example, defined by short sides (not labeled) of the conductive patterns121(e.g., the conductive pattern1211, the conductive pattern1212, and the conductive pattern1213, but not limited thereto) adjacent to the center121c. The dotted line C2 is, for example, defined by other short sides of the conductive patterns121(e.g., the conductive pattern1211, the conductive pattern1212, and the conductive pattern1213, but not limited thereto) away from the center121c.

In some embodiments (as shown inFIG.1), the test mark12may optionally include a plurality of sequence patterns122(including a number pattern, a letter pattern, a Roman numeral pattern or other sequence patterns) to mark orientations of the conductive patterns121, but not limited thereto. For example, the sequence patterns122may be Roman numeral patterns I to XII, and each of these sequence patterns122may correspond to one conductive pattern, but not limited thereto. The arrangement of the sequence patterns122may, for example, be arranged in a clockwise or counterclockwise arrangement, but not limited thereto. In some embodiments, the number of the plural sequence patterns122may be adjusted according to the number of the plural conductive patterns121. For example, the number of the plural conductive patterns121may be N1 times the number of the plural sequence patterns122, and N1 is, for example, a positive integer.

It should be noted that, in the embodiment ofFIG.1, the conductive patterns121are designed to have substantially the same pattern with each other. For example, the conductive patterns121may have substantially the same shape, size, width, and/or length, and/or the adjacent conductive patterns121may have substantially the same angles θA, the same first distances d1A, and/or the same second distances d2A, but not limited thereto. In addition, when warpage of the conductive layer142occurs, at least a part of the conductive patterns121may be deformed. Since a plurality of conductive patterns121may be arranged in the ring shape, through identifying variation and/or position of the deformed conductive pattern121, the warping direction and/or warpage position may be determined, thereby determining the warpage degree or warpage tendency of the conductive layer142. For example, by comparing shapes, sizes, widths and/or lengths of different conductive patterns121with each other, and/or comparing the angles θA and/or distances between adjacent conductive patterns121(e.g., the first distance d1A and/or the second distance d2A) with each other, whether different parts of the conductive layer142are warped may be determined, or their warpage degree may be obtained, but not limited to thereto.

It should be noted that the redistribution layer14may include other layers according to requirements. In the embodiment ofFIG.2, the redistribution layer14may include a conductive layer144and/or a conductive layer145. The conductive layer144is disposed under the first dielectric layer141, and the conductive layer145is disposed on the second dielectric layer143. For example, the conductive layer144may include at least one lower pad144adisposed on a lower surface of the redistribution layer14. The first dielectric layer141may have at least one through hole141a, so that the trace142amay be electrically connected to the lower pad144athrough the through hole141a. The conductive layer145may include at least one upper pad145adisposed on an upper surface of the redistribution layer14, and the upper pad145amay be used for electrical connection with external electronic components CE or other suitable components. The upper pad145amay be electrically connected to the trace142athrough the through hole143aof the second dielectric layer143, and the trace142amay be electrically connected to the lower pad144athrough the through hole141aof the first dielectric layer141. In some embodiments (not shown), the conductive layer144and/or the conductive layer145of the redistribution layer14may include at least one test mark to inspect the warpage degree while forming the conductive layer144and/or the conductive layer145in real time. The test mark of the conductive layer144and/or the conductive layer145may be applied to the test mark12ofFIG.1and/or at least one of the test marks of the following embodiments and variant embodiments. In some embodiments, another conductive layer and/or another dielectric layer may be optionally disposed between the second dielectric layer143and the conductive layer145including the upper pad145a. In some embodiments, other conductive layers and/or other dielectric layers may optionally be disposed between the first dielectric layer141and the conductive layer144including the lower pad144a, but not limited thereto. In this case, the redistribution layer14may include other test marks formed of other conductive layers. In some embodiments, the test marks formed of different conductive layers may overlap or not overlap in the top view direction TD. In some embodiments, the number of the test marks12corresponding to one conductive layer may not be limited to one shown inFIG.1, but may also be plural.

In some embodiments, as shown inFIG.2, the conductive layer142, the conductive layer144and/or the conductive layer145may be, for example, a single-layer structure or a multi-layer structure. For example, the multi-layer structure may include a seed layer SL and a metal layer ML stacked in sequence, but not limited thereto. In this case, the conductive pattern121, the lower pad144a, the trace142a, and the upper pad145amay respectively include a seed block SLa and/or a metal block MLa, but not limited thereto. In some embodiments, the conductive layer142, the conductive layer144, and the conductive layer145may, for example, include copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), nickel (Ni), other metal materials, or any combination thereof, but not limited thereto. Each of the thickness (not labeled) of the conductive layer144and the thickness (not labeled) of the conductive layer145may, for example, be equal to or different from the thickness T1 of the conductive layer142described above.

The following description further details the manufacturing method of the package device of this embodiment. The manufacturing method of the package device of some embodiments of the present disclosure may include providing the carrier16, and forming the redistribution layer14on the carrier16, in which the redistribution layer14may include the first dielectric layer141, the conductive layer142, and the second dielectric layer143. The conductive layer142is disposed between the first dielectric layer141and the second dielectric layer143, in which the redistribution layer14may have the test mark12, and the test mark12may include a plurality of or at least one conductive pattern121, and the conductive pattern121may be formed of the conductive layer142. In some embodiments, the plurality of conductive patterns121may be arranged in the ring shape, but not limited thereto. For details, refer toFIG.3in combination withFIG.2.FIG.3schematically illustrates the manufacturing method of the package device according to the first embodiment of the present disclosure.

First, as shown inFIG.3, the carrier16is provided. Then, the conductive layer144including the lower pad144ais formed on the carrier16, and the first dielectric layer141is formed on the conductive layer144and the carrier16. Subsequently, the through hole141ais formed in the first dielectric layer141to expose at least a part of the lower pad144a. Next, the seed layer SL is formed on the first dielectric layer141, and the seed layer SL may extend into the through hole141a. Thereafter, through an exposure and development process, a photoresist pattern18may be formed on the seed layer SL. The photoresist pattern18may have a plurality of through holes18ato expose parts of the seed layer SL, and the metal block MLa may be subsequently disposed or filled in these through holes18a; that is, the regions of the through holes18amay substantially define positions of parts of the conductive layer142. The formed metal layer ML may include a plurality of metal blocks MLa. For example, the method of forming the metal layer ML may include forming the metal layer ML on the exposed parts of the seed layer SL through an electroplating process, a chemical plating process, a physical vapor deposition process or other suitable processes.

As shown inFIG.2, after the metal layer ML is formed, the photoresist pattern18may be removed to expose parts of the seed layer SL. Then, through an etching process, the parts of the seed layer SL that are uncovered by the metal layer ML may be removed to form a plurality of seed blocks SLa, thereby forming the conductive layer142on the first dielectric layer141, but not limited thereto. After the test mark12is formed, an inspection step may be performed to obtain a top view image of the test mark12so as to determine whether the warpage occurs or whether the warpage degree exceed standard. The top view image of the test mark12may be obtained by, for example, an optical microscope, but not limited thereto. Through inspecting the conductive layer142in real time, the warpage degree and warpage tendency may be found in real time, so as to improve the process conditions in real time and/or increase the process yield.

As shown inFIG.2, after the conductive layer142is formed, the second dielectric layer143may be formed on the conductive layer142and the first dielectric layer141. In some embodiments, the second dielectric layer143may be optionally disposed on the test mark12, but not limited thereto.

As shown inFIG.2, after the second dielectric layer143is formed, the conductive layer145may be formed on the second dielectric layer143, thereby forming the redistribution layer14on the carrier16. Then, the carrier16may be optionally removed to form the package device1of this embodiment. In some embodiments, a plurality of package devices1may be formed on the carrier16, so that before or after the carrier16is removed, a cutting process may be performed to separate the package devices1from each other, but not limited thereto. In some embodiments, the method of forming at least one of the conductive layer144and the conductive layer145may be similar to the method of forming the conductive layer142, but not limited thereto. In some embodiments, after the conductive layer144and/or the conductive layer145is formed, another inspection step may be performed to inspect the warpage degrees during the formation of the conductive layer144and/or the conductive layer145, but not limited thereto.

The test mark of the present disclosure is not limited to the above-mentioned embodiment and may include different embodiments or variant embodiments. In order to simplify the description, different embodiments and variant embodiments described below will refer to components identical to those in the first embodiment using the same labels. For clearly describing different embodiments and variant embodiments, the following contents will describe differences between the first embodiment and different embodiments or variant embodiments, and will no longer repeat descriptions regarding the same components in detail.

FIG.4schematically illustrates a test mark according to a variant embodiment of the first embodiment of the present disclosure. As shown inFIG.4, the test mark12amay have a plurality of conductive patterns121, and a uniform distance may be between two adjacent conductive patterns121. In some embodiments, a first distance d1B and a second distance d2B may be between adjacent two conductive patterns121. The first distance d1B may be defined as a distance (spacing) between adjacent two conductive patterns121on the dotted line C1 closest to the center121c, the second distance d2B may be defined as a distance (spacing) between adjacent two conductive patterns121on the dotted line C2 furthest away from the center121c, and the first distance d1B is substantially equal to the second distance d2B, but not limited thereto. As shown inFIG.4, the above-mentioned dotted line C1 may be, for example, defined by the short sides (not labeled) of the conductive patterns121adjacent to the center121c, and the above-mentioned dotted line C2 may be, for example, defined by other short sides (not labeled) of the conductive patterns121away from the center121c. The test mark12amay have the center121c, and the center121cmay optionally correspond to or not correspond to the conductive patterns121. For example, the center121cof the embodiment ofFIG.4may not correspond to the conductive patterns121. In this variant embodiment, the warpage degree or the warpage tendency of the conductive layer may be determined by comparing the first distances d1B and/or the second distances d2B between adjacent conductive patterns121or comparing the first distances d1B and/or the second distances d2B with design standards. In some embodiments (as shown inFIG.7), the top-view shape of each of the conductive patterns121of the test mark12amay be an annular sector pattern or other patterns whose width increases along its extending direction, but not limited thereto. For example, the width W1 of the conductive pattern121may gradually increase along a direction away from the center121c, and the width W1 of the conductive pattern121may be, for example, a width measured in a direction perpendicular to the extending direction RD of the conductive pattern121. In some embodiments (not shown), the width W1 of the conductive pattern121may also gradually decrease along a direction away from the center121c. The increase or decrease mentioned above may not be limited to be increased or decreased proportionally. Other parts of the test mark12aand the manufacturing method of the test mark12aof this variant embodiment may be the same as or similar to the above-mentioned embodiment and will not be repeated in detail.

FIG.5schematically illustrates a top view of a test mark according to another variant embodiment of the first embodiment of the present disclosure. As shown inFIG.5, the test mark12bmay have a plurality of conductive patterns121. The width W1 of each of the conductive patterns121may gradually decrease along a direction away from the center121c. The width W1 may be, for example, a width measured in a direction perpendicular to the extension direction RD of the conductive pattern121, and the conductive patterns121may have substantially the same size, but not limited thereto. In some embodiments, the test mark12bmay have a center121c, and the center121cmay or may not correspond to the conductive patterns121. In the embodiment ofFIG.5, the center121cmay, for example, correspond to the conductive patterns121. For example, at least one of the plurality of conductive patterns121may be triangular (e.g., isosceles triangle) or other suitable shapes, but is not limited thereto. In this variant embodiment, the warpage degree or the warpage tendency of the conductive layer may be determined by comparing the sizes of these conductive patterns121or comparing the sizes of the detected conductive patterns121with the design standards. In some embodiments, the test mark12bmay include a plurality of conductive patterns121and another conductive pattern123. The plurality of conductive patterns121are arranged around the another conductive pattern123, and the conductive patterns121and the other conductive pattern123may, for example, be formed of the same conductive layer (e.g., the conductive layer142). In some embodiments, a shape of the another conductive pattern123may include circle or other suitable shapes. In some embodiments, minimum distances from these conductive patterns121to the another conductive pattern123may be substantially the same, so that the warpage degree or warpage tendency of the conductive layer may be determined by comparing the minimum distances between the conductive patterns121and the conductive pattern123with each other or comparing these minimum distances with the design standards. The other parts of the test mark12band the manufacturing method of the test mark12bof this variant embodiment may be the same as or similar to the above-mentioned embodiment and may refer to the description of the above-mentioned embodiment, so that they will not be repeated.

FIG.6schematically illustrates a top view of a test mark according to another variant embodiment of the first embodiment of the present disclosure. As shown inFIG.6, the test mark12cmay include a conductive pattern121formed of the conductive layer124as described above. The conductive pattern121may include a center portion121P1and a plurality of extension portions121P2, and the plurality of extension portions121P2may be respectively connected to the center portion121P1. For example, the extension portions121P2may be separated from each other and connected to each other by the center portion121P1. In some embodiments, the plurality of extension portions121P2may extend outwardly in the radial shape with the center portion121P1substantially as a center, but not limited thereto. For example, the extension portions121P2extend outwardly in the radial shape with a center point P1C of the center portion121P1substantially as the center. As viewed along the top view direction TD, an angle θ may be between the extension directions ED of any two adjacent extension portions121P2, and these angles θ may be substantially the same. In some embodiments, these angles θ may range from 10 degrees to 45 degrees (10 degrees≤the angles θ≤45 degrees), but not limited thereto. The angles θ may be adjusted according to the number or width W2 of the extension portions121P2. In some variant embodiments, the warpage degree or warpage tendency of the conductive layer may be determined by comparing the angles θ between the conductive patterns121or comparing the detected angles θ with the design standards. In the embodiment ofFIG.6, the extension portions121P2may respectively have the extension directions ED, and each of the extension portions121P2may have a uniform width W2 in a direction perpendicular to its extension direction ED, but not limited thereto. In some embodiments, a distance L2 may be between the short side of each of the extension portions121P2away from the center portion121P1and the center point P1C in the extension direction ED of the extension portion121P2, and the distances L2 may be substantially the same or at least two of the distance L2 may be different. Alternatively, the widths W2 of at least two extension portions121P2may be different. The other parts of the test mark12cand the manufacturing method of the test mark12cof this variant embodiment may be the same as or similar to the above-mentioned embodiment and will not be repeated.

FIG.7schematically illustrates a top view of the test mark of a second embodiment of the present disclosure. As shown inFIG.7, the test mark22may include a plurality of conductive patterns221, and these conductive patterns221may have substantially similar top-view shapes. The conductive patterns221may be arranged along at least one direction or arranged along multiple directions, for example, along the direction D1 and/or the direction D2. The direction D1 may be different from the direction D2, and the direction D1 may be, for example, perpendicular to the direction D2, but not limited thereto. In some embodiments, the sizes of the plurality of conductive patterns221may sequentially increases or decreases, for example, along the at least one direction. It should be noted that the above-mentioned sequential increase or decrease may not mean that the sizes need to be changed proportionally. In some embodiments, the top-view shapes of the conductive patterns121may be, for example, an E-shape, a C-shape, or other suitable shapes with notches.

For example, in the embodiment ofFIG.7, the conductive patterns221may include a conductive pattern2211, a plurality of conductive patterns2212, and a plurality of conductive patterns2213. In some embodiments, the conductive patterns221may include a conductive pattern2211and a plurality of conductive patterns2212, or a conductive pattern2211and a plurality of conductive patterns2213. As shown inFIG.7, the conductive pattern2211and the plurality of conductive patterns2212may be arranged, for example, along the direction D1, and the sizes of the conductive pattern2211and the plurality of conductive patterns2212may be sequentially increased or decreased along the direction D1, in which a distance d3A may be between any two adjacent conductive patterns221arranged in sequence, and the distances d3A may be substantially the same, but not limited thereto. The conductive pattern2211and the plurality of conductive patterns2213may be arranged, for example, along the direction D2, and the sizes of the conductive pattern2211and the plurality of conductive patterns2213may be sequentially increased or decreased along the direction D2, in which a distance d3B may be between any two adjacent conductive patterns sequentially arranged along the direction D2, and the distances d3B may be substantially the same, but not limited thereto. In this case, the distance d3A between two adjacent conductive patterns221sequentially arranged along the direction D1 may be substantially equal to the distance d3B between two adjacent conductive patterns221sequentially arranged along the direction D2, but not limited thereto. It may be determined whether the warpage of the conductive layer occurs or the warpage degree of the conductive layer may be obtained by inspecting the distances, sizes, or pattern shape of the conductive patterns221. For example, the test mark22may have a center (e.g., substantially corresponding to the conductive pattern2211), and a plurality of virtual circles20(FIG.7just shows one of the virtual circles for illustration) may be illustrated from the center (e.g., substantially corresponding to the conductive pattern2211). The virtual circles may cross both one of the conductive patterns2212and one of the conductive patterns2213. By inspecting the size of the conductive pattern2212and the size of the conductive pattern2213corresponding to the same virtual circle20, and/or the distance d3A between this conductive pattern2212and the conductive pattern2211and the distance d3B between this conductive pattern2213and the conductive pattern2211corresponding to the same virtual circle20, it may be determined whether the warpage occurs or how much the warpage degree is. In some embodiments, the center may not correspond to the conductive patterns221. In some embodiments, at least two distances d3A of the conductive patterns221sequentially arranged along the direction D1 may not be the same, and/or at least two pitches d3B of the conductive patterns221sequentially arranged along the direction D2 may also not be the same.

In the embodiment shown inFIG.7, each of the conductive patterns221may include at least one notch221b. Since the sizes of the conductive patterns221(e.g., widths of the notches221b) may increase or decrease along the direction D1 and/or the direction D2, For example, sizes of the notches221bof the conductive pattern2211and the conductive pattern2212may sequentially increase or decrease along the direction D1, and sizes of the notches221bof the conductive pattern2211and the conductive pattern2213may sequentially increase or decrease along the direction D2, but not limited thereto. The warpage of the conductive layer may also be determined by inspecting the sizes of the notches221bof different conductive patterns221.

FIG.8schematically illustrates a top view of a test mark according to a variant embodiment of the second embodiment of the disclosure. As shown inFIG.8, in this variant embodiment, the test mark22amay have a plurality of conductive patterns221, and the plurality of conductive patterns221may be arranged in a ring shape. In some embodiments, the plurality of conductive patterns221may be arranged in a radial shape, but not limited thereto. In the embodiment ofFIG.8, top-view shapes of the conductive patterns221may be C-shaped as an example, but not limited thereto. The top-view shapes of the conductive patterns221may also be E-shaped or other suitable shapes. The conductive patterns221may be arranged in a star shape or other suitable shapes, for example. In some embodiments (not shown), the test mark22amay not include the conductive pattern2211substantially located at the center of the virtual circle20, or the center of the test mark22amay not correspond to any conductive pattern221. Through inspecting the sizes of the conductive patterns221substantially corresponding to the same virtual circle20(FIG.8just shows one the virtual circle20for illustration) and/or the distances (e.g., the distance d3A and the distance d3B) from the conductive patterns221substantially located on the same virtual circle20to the center of the same virtual circle20, it may be determined whether the warpage of the conductive layer occurs or how much the warpage degree of the conductive layer is. The conductive patterns221substantially corresponding to the same virtual circle20may, for example, mean that the conductive patterns221crossing the virtual circle20or substantially adjacent to the virtual circle20.

FIG.9schematically illustrates positions of the test marks according to an embodiment of the present disclosure. As shown inFIG.9, the carrier16may have a plurality of device regions16aand a peripheral region16bsurrounding the plurality of device regions16a, and one of the device regions16amay correspond to one package device1, but not limited thereto. The package device1of this embodiment may be, for example, the package device of any of the above-mentioned embodiments or variant embodiments, and the test mark32may be, for example, the test mark of any of the above-mentioned embodiments or variant embodiments. The redistribution layer14(not shown, may refer toFIG.2andFIG.3) may be formed on the carrier16and may include a plurality of test marks32, and at least one test mark32may be disposed on the carrier16in at least one of the device regions16aand the peripheral region16b. In some embodiments, when the test mark32is disposed on the carrier16in the peripheral region16b, the test mark32may be located at a corner, a side, a center, and/or other portions of the peripheral region16b, but not limited thereto. In some embodiments, when the test mark32is disposed on the carrier16in one of the device regions16a, the test mark32may be located at a corner, a side and/or other portions of the device region16a, but not limited thereto. By installing the test marks32on the carrier16in different regions, the warpage degree in different regions may be inspected.

In some embodiments, after the plural package devices1are completed, for example, after the redistribution layer14is completed in the device regions16a, the peripheral region16bmay, for example, be removed, and the test marks32located on the carrier16in the peripheral region16bmay also be removed.

FIG.10schematically illustrates positions of test marks in the package device according to another embodiment of the present disclosure. As shown inFIG.10, the test marks32may be dispersed at different positions of the package device1. For example, at least one of the test marks32may be adjacent to one of the upper pads145aand/or disposed at the corner of the package device1. In some embodiments, the size of one of the test marks32may be less than or equal to that of one of the upper pads145a, but not limited thereto. In other embodiments, the relationship between the sizes of the test marks32and sizes of the upper pads145amay be designed according to requirements.

In summary, in the manufacturing method of the package device of the present disclosure, since the test marks are formed at the same time during the process of manufacturing the package device, the test marks may be identified to determine whether the warpage occurs or whether the warpage degree exceeds the standards in real time, thereby increasing the process yield.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.