Patent ID: 12237376

DETAILED DESCRIPTION

Techniques in accordance with embodiments described herein are directed to new vertical tunnel field-effect transistors (“TFET”) with III-V compound semiconductor materials “III-V materials”. In one or more embodiments of the current disclosure, a source layer of a first III-V material is stacked over a substrate. A channel layer of a second III-V material is stacked over the source layer. A drain layer is stacked over the channel layer (“first channel layer”) with an interlayer (“second channel layer”) stacked therebetween. The drain layer and the interlayer overlap a first surface portion of the channel layer. A first gate structure is positioned over the channel layer by a second surface portion of the channel layer. The second surface portion is adjacent to and separated from the first surface portion. The first gate structure is also adjacent to the interlayer layer by a first sidewall of the interlayer layer. The first gate structure may also be adjacent to the drain layer by a first sidewall of the drain layer. That is, the first gate structure is substantially “L-shaped” with respect to the interlayer and the channel layer. In an embodiment where two drain layers are coupled to a same source layer and a same channel layer, the first gate structure is substantially “U-shaped” between the two drain layers.

In an embodiment, a second gate structure (“band aligner structure”) is positioned adjacent to a second sidewall of the second channel layer and/or a second sidewall of the drain layer. The second sidewalls of the second channel layer and the drain layer are opposite to the first sidewalls thereof.

In an embodiment, the second channel layer and the first channel layer are intrinsic or unintentionally doped, e.g., intrinsically doped. The second channel layer may include a same material as the first channel layer, but with a larger thickness. The larger thickness of the second channel layer reduces tunnel current in the OFF state and improves the turn-off characteristic of the TFET.

In another embodiment, the second channel layer includes a different semiconductor material than the first channel layers such that the second channel layer enables a smaller off-state tunnel current than the first channel layer. The second channel layer may include the same III and V elements as the first channel layer but with different element ratios.

The first gate structure is configured to apply an electrical field on the first channel layer in a vertical direction, e.g., the direction of band-to-band tunnel (“BTBT”) through the first channel layer. The first gate structure is configured to apply an electric field on the second channel layer by the first sidewall of the second channel layer, e.g., orthogonal to the tunnel current, which is a weaker gate control because the direction of the electrical field intersects the direction of the charge carrier movement orthogonally.

In operation, at the ON state, the ON current flows vertically from the source layer to the first channel layer via BTBT effect and is collected by the drain layer through the second channel layer. At the ON state, the main BTBT occurs under the first gate structure, and its direction is in parallel to the gate electric field, which provides greater gate control.

At the OFF state, while the main BTBT under the first gate structure is suppressed, the source-to-drain tunnel current (“SDT”) dominates since the gate control over the source to first channel junction that is not right below the first gate is weaker. However, the SDT current needs to tunnel through not only the first channel layer but also the second channel layer to be collected by the drain layer. Therefore, the SDT current (or “leakage”) is suppressed by engineering or controlling the second channel layer and its tunneling barrier without affecting the ON state BTBT current that travels through the first channel layer under the first gate structure.

Therefore, a large ON state current and a small OFF state leakage current can be separately achieved owing to the effective control over different tunneling paths for the ON and the OFF state currents.

The disclosure herein provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present description. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”

The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

Tunneling field effect transistor (“TFET”) structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the TFET structure.

The following description refers to a transistor as an example of a semiconductor structure to which the present description applies; however, the present description is not limited in applicability to transistors. For example, the following description applies to other types of semiconductor structures that are not transistors where the improved tunneling effects of the intrinsic channel region are desirable in a vertical device using GaN. Further, the disclosure also includes a vertical device using other III-V materials, which include a pyramid type upper profile, e.g., a sloped surface.

FIGS.1A and1Bshow a top view and a cross-sectional view of an example tunnel field-effect transistor (“TFET”) structure100.FIG.1Ais a top view of the structure100andFIG.1Bis a cross-sectional view of the structure100from cutting plane II-II. With reference toFIGS.1A and1Btogether, the structure100includes, in a vertical stack, a substrate110, a first semiconductor layer120, a second semiconductor layer130, a third semiconductor layer140, and a fourth semiconductor layer150. The third semiconductor layer140and the fourth semiconductor layer150each include a plurality of discrete portions140A,140B,150A,150B, respectively. The discrete portions in each of the layers140,150are separated from one another. For example, the portion140A and the portion140B of the third semiconductor layer140are separated from one another. Portions140A,150A form a vertical stack and portions140B,150B form a separate vertical stack. In a non-limiting embodiment, the layers150A (or150B) and the layer140A (or140B) in a vertical stack include sidewalls150S,140S that are plumb with one another. Each of the vertical stacks of the discrete portions140A,150A,140B,150B covers or overlaps a smaller area than the second semiconductor layer130. Specifically, the vertical stack of140A,150A overlaps portion130(1) of the second semiconductor layer130, and the vertical stack of140B,150B overlaps portion130(3) of the second semiconductor layer130.

A gate structure160(first gate structure) is formed over the second semiconductor layer130and between the portions140A and140B of the third semiconductor layer140. Specifically, the first gate structure160contacts portion130(2) of the second semiconductor layer130and is adjacent to the sidewall140S of each of the third semiconductor portions140A,140B. The portion130(2) separates the portion130(1) and the portion130(3). The first gate structure160may also be at least partially adjacent to the portions150A,150B of the fourth semiconductor layer150. The first gate structure160includes a gate electrode162and a gate dielectric164. The gate electrode162is a metal material or other suitable electrically conductive material. The gate dielectric164is a high-K dielectric material. Because the gate dielectric164contacts surface132of the second semiconductor layer130, specifically that of the portion130(2), and the sidewalls140S of the separate portions140A,140B of the third semiconductor layer140, the gate dielectric164is essentially U-shaped, indicating a U-shaped interface between the first gate structure160and the portion140A, the surface132and the portion140B. The gate dielectric164is essentially L-shaped with respect to the surface132and a sidewall of one of the portions140A,140B.

In an embodiment, the structure100also includes a second gate structure170(shown as170A,170B). The second gate structure170contacts a sidewall130S of the second semiconductor layer130and a sidewall140S′ of the portion140A of the third semiconductor layer140. The sidewall140S′ is a different sidewall (or a different sidewall portion) from the sidewall140S that is adjacent to the first gate structure160. The second gate structure170(170A,170B) includes a gate electrode172(172A shown) and a gate dielectric174(174A shown), which may include the same materials as the gate electrode162and the gate dielectric164of the first gate structure160.

FIGS.1A and1Bshow, as an embodiment, that the first gate structure160and the second gate structure170overlap surfaces of the portions150A,150B of the fourth semiconductor layer150. The disclosure is not limited by this specific embodiment. For example, one or more of the first gate structure160or the second gate structure170may be substantially at a same level as the fourth semiconductor layer150or be lower than an upper surface of the fourth semiconductor layer150(150A,150B).

In an embodiment, the structure100is a tunnel field-effect transistor (“TFET”). The first semiconductor layer120is configured as a source of the TFET. The source layer120is, for example, P-doped. The second semiconductor layer130is configured as a first channel layer. The first channel layer130is intrinsic or lightly N-doped (“N−”). Depending on the material and the formation process, an intended intrinsic (e.g., undoped) first channel layer130might be unintentionally doped (“UID”) (also referred to as “intrinsically doped”). The third semiconductor layer140(140A,140B) is an interlayer semiconductor layer or “second channel layer.” The interlayer140is intrinsic, unintentionally N doped or lightly N-doped.

The fourth semiconductor layer150(150A,150B) is configured as a drain layer and is N-doped with a higher doping concentration than the lightly or unintentionally doped interlayer/second channel layer140or first channel layer130. In an embodiment, a material of the interlayer140includes a higher tunneling barrier than a material of the first channel layer130.

In an example embodiment, the substrate110is indium phosphide “InP”, doped as P-type. The source layer120is gallium arsenide antimonide (“GaAsSb”). The first channel layer130is indium gallium arsenide (“InGaAs”) and has a composition of InxGa1-xAs. The interlayer140is indium gallium arsenide (“InGaAs”) and has a composition of InyGa1-yAs. In an embodiment, the interlayer140includes a higher ratio of Ga atoms and a lower ratio of In atoms than the channel layer, e.g., x>y. The higher ratio of Ga atoms and the lower ratio of In causes the interlayer140to include a higher tunneling barrier than the channel layer130. In an example, x=0.87 and y=0.75.

The drain layer150includes N-doped InGaAs. The doping concentration of the drain layer150is much higher than the doping concentration of the lightly N-doped or unintentionally N-doped channel layer130and interlayer140. In an example, the doping concentration of the drain layer150is more than 2 times that of the doping concentration of the lightly N-doped or unintentionally N-doped channel layer130and interlayer140. In an embodiment, the doping concentration of the drain layer150is more than 3 times that of the doping concentration of the lightly N-doped or unintentionally N-doped channel layer130and interlayer140.

FIG.1Ashows, as an embodiment, that the semiconductor stack of140A,150A and the semiconductor stack of140B,150B are fin type structures separated from one another, and the second gate structures170A,170B are separated from one another. In another embodiment, as shown inFIG.1C, a top view of an alternative example structure1000, the third semiconductor layer140(not shown) and the fourth semiconductor layer150are each an integrated pattern and have a continuous shape, e.g., a ring shape. The second gate structure170is also an integrated pattern and has a continuous shape. The description ofFIG.1Balso applies to the example structure1000ofFIG.1C.

FIGS.2A and2Bschematically show the operation of the TFET100ofFIG.1.FIG.2Ashow an ON state of the TFET100. An ON voltage Von is applied on the gate electrode162of the first gate structure160. Through the tunneling effect, the ON state current flows vertically from the source layer120to the first channel layer130via a band-to-band tunneling (“BTBT”) effect and is collected by the drain150through the second channel layer140. An arrow210illustrates the charge carrier movement direction. As shown by the arrow210, at the ON state, the main BTBT occurs under the first gate structure160. For this main BTBT, the ON voltage Von creates an electrical field in a direction that is in parallel with the charge carrier movement210, which provides greater gate control. After the main BTBT, the tunnel current moves through the second channel layer140(140A,140B) through the sidewall140S area that is controlled by the ON voltage Von in an orthogonal intersect direction. Because the main BTBT has already passed through the greater gate control on the first channel layer120, the second channel layer140(140A,140B) does not substantially affect the ON state current.

At the OFF state, as shown inFIG.2B, an OFF voltage Voff is applied on the gate electrode162of the first gate structure160. While the main BTBT under the first gate160is much suppressed by the Voff, the source-drain tunnel (“SDT”) current, shown as arrow220, dominates due to the weaker gate control over the source/channel junction that is not right below the first gate structure160. The SDT current needs to tunnel through not only the first channel130, but also the second channel140. Therefore, the existence of the second channel layer/interlayer140substantially lowers the SDT current, e.g., the leakage current, at the OFF state. The SDT leakage is suppressed by engineering or controlling the thickness of the interlayer140and its tunneling barrier. As described herein, the thickness and the tunneling barrier of the second layer140do not affect the ON state of the BTBT current that is mainly controlled by a parallel gate electrical field under the first gate structure160, as shown inFIG.2A.

Therefore, both a large ON current and a low OFF leakage can be achieved owing to the effective control over different tunneling paths separately for the ON and OFF state currents.

The second gate structure170functions to further suppress the BTBT current through the interface region adjacent to the sidewall130S of the channel130and the sidewall140S′ of the interlayer140. Specifically, the second gate structure170functions to provide extra control over the SDT channel, e.g., the first channel130plus the second channel140, to misalign the bands for the SDT leakage. As such, the second gate structure170may also be referred to as a “band aligner.” The voltage applied onto the second gate structure170can be the same as or different from the voltage applied onto the first gate structure160, depending on the operational requirements. In an embodiment, to maximize the band aligning function, the second gate structure170is controlled by a separate control voltage signal from that of the first gate160. The second gate structure170has a less significant effect on the ON state BTBT current because its gate electric field is orthogonal to the main BTBT current from the source120through the channel130, as shown inFIG.2A.

FIGS.3-6show alternative and/or additional embodiments with respect to the TFET100ofFIG.1. Referring toFIG.3, in example TFET structure300, a first gate structure360and a second gate structure370each include a gate electrode362,372over a respective gate dielectric364,374and follow the profile of the gate dielectric364,374. That is, the gate electrode362also includes a U-shaped profile.

Further, the TFET300also includes an additional interlayer semiconductor layer440(440A,440B) stacked under the drain150and the interlayer140and adjacent to the channel layer130. In an embodiment, the additional interlayer440(second interlayer) includes a semiconductor material having a tunneling barrier higher than that of the first channel layer130and lower than that of the interlayer140(first interlayer or second channel layer). In an example, the first channel layer130is InxGa1-xAs, the first interlayer140is InyGa1-yAs, and the second interlayer440is InzGa1-zAs and x>z>y. In an example, x=0.87, z=0.80 and y=0.75. The second interlayer440is also referred to as a “third channel layer.” The third channel layer440is laterally adjacent to the first channel layer130and substantially at a same level as the first channel layer130. The third channel layer440is below the second channel layer140.

Because the ON state BTBT current travels through the first channel layer130below the first gate360and through the interface region adjacent to the sidewall140S of the first interlayer/second channel layer140, the second interlayer/third channel layer440(440A,440B) does not substantially affect the ON state BTBT current. At the OFF state, as the tunneling barrier of the second interlayer (or third channel layer)440is higher than that of the first channel layer130, the leakage current is further reduced as compared to the TFET100ofFIG.1.

FIG.4shows another example TFET400. The TFET400includes a first gate structure460and a second gate structure470. Each of the gate structures460,470contact a surface portion430(1),430(2) of the first channel layer130and contact a sidewall140S,140S′ of the interlayer140. The gate structures460,470may also contact a sidewall150S,150S′ of the drain layer150. The sidewalls140S,150S are opposite to the respective sidewalls140S′,150S′. The drain layer150and the interlayer140overlap a portion430(3) of the first channel layer130. The portion430(3) is positioned between the portions430(1) and430(2).

In an embodiment, the gate structures460,470are portions of a single gate structure that wraps around the interlayer140and wraps at least partially around the drain layer150.

In an embodiment, the TFET300includes only one stack of the drain layer150and the interlayer140over the channel layer130.

FIG.5shows another example TFET500. The TFET500is similar to the TFET400ofFIG.4, except that the TFET500includes a second interlayer/third channel layer540vertically below the interlayer140(first interlayer) and laterally between or within the first channel layer130. The second interlayer/third channel layer540includes a semiconductor material that has a higher tunneling barrier than the first channel layer130. In an example, the first channel layer130is InxGa1-xAs, the first interlayer140is InyGa1-yAs, and the second interlayer540is InzGa1-zAs and x>z>y. In an example, x=0.87, z=0.80 and y=0.75.

FIG.6shows another example TFET600. The TFET600is similar to the TFET100ofFIG.1, except that the second gate structure170does not contact the first channel layer130. An insulation layer630, e.g., of dielectric, is positioned laterally adjacent to the first channel layer130and vertically between the second gate structure170and the source layer120.

The example TFETS100,1000,300,400,500,600and the portions thereof may be combined and/or replaced among one another in various ways, which are all included in the disclosure.

In all the embodiment TFETS100,1000,300,400,500,600, the thickness of the first channel layer130is controlled to be relatively thin to achieve a high ON state current. In an embodiment, the first channel layer130is thinner than 10 nm. In an embodiment, the first channel layer130has a thickness ranging from 4 nm to about 10 nm.

A thickness of the first interlayer (or second channel layer)140is relatively thick, as compared to the first channel layer130, to increase the tunneling barrier so that the OFF leakage current is low. In an embodiment, the first interlayer140has a thickness ranging between 20 to 50 nm.

The second interlayer (or third channel layer)440,540is substantially coplanar with the respective channel layer130and has a similar thickness as the respective channel layer130.

The first gate structure160,360include a length (L1inFIG.1) larger than about 5 nm to ensure sufficient BTBT tunneling for the ON current. In an embodiment, the first gate structure160,360includes a gate length ranging from about 6 nm to about 15 nm. The first gate structure460and the second gate structure470include a length (L3inFIG.5) larger than 3 nm. In an embodiment, the gate length L3ranges from about 3 nm to about 10 nm.

The interlayer140and the drain layer150each include a length (L2inFIG.1) larger than about 10 nm.

The gate structures160,170,460,470are metal gates. The following description lists examples of materials for the gate structure160,170,460,470. The gate electrode162,172,462,472of the gate structure160,170,460,470includes a conductive material, e.g., a metal or a metal compound. Suitable metal materials for the gate electrode162,462of the gate structure160,170,460,470include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides and other suitable P-type metal materials and include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), and other suitable materials for N-type metal materials. In some examples, the gate electrode162,172,462,472of the gate structures160,170,460,470includes a work function layer tuned to have a proper work function for enhanced performance of the field effect transistor devices. For example, suitable N-type work function metals include Ta, TiAl, TiAlN, TaCN, other N-type work function metals, or a combination thereof, and suitable P-type work function metal materials include TiN, TaN, other P-type work function metals, or combination thereof. In some examples, a conductive layer, such as an aluminum layer, a copper layer, a cobalt layer or a tungsten layer is formed over the work function layer such that the gate electrode162,172,462,472of gate structure160,170,460,470includes a work function layer disposed over the dielectric layer164,174,464,474and a conductive layer disposed over the work function layer and below a gate cap (not shown for simplicity). In an example, the gate electrode162,172,462,472of the gate structure160,170,460,470has a thickness ranging from about 5 nm to about 40 nm depending on design requirements.

In example embodiments, the dielectric layer164,174,464,474includes an interfacial silicon oxide layer (not separately shown for simplicity), e.g., a thermal or chemical oxide having a thickness ranging from about 5 to about 10 angstrom (Å). In example embodiments, the dielectric layer144further includes a high dielectric constant (high-K) dielectric material selected from one or more of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfArO), combinations thereof, and/or other suitable materials. A high K dielectric material, in some applications, includes a dielectric constant (K) value larger than 6. Depending on design requirements, a dielectric material of a dielectric contact (K) value of 7 or higher is used. The high-K dielectric layer may be formed by atomic layer deposition (ALD) or other suitable technique. In accordance with embodiments described herein, the high-K dielectric layer of the gate dielectric layer includes a thickness ranging from about 10 to about 30 angstrom (Å) or other suitable thickness. Other dielectric materials can also be used for the dielectric layer164,174,464,474, e.g., MgCaO or Al2O3.

In example embodiments, the insulation layer630(FIG.6) is silicon oxide or a low-K dielectric material. A low-K dielectric material includes as silicon oxynitride, silicon nitride (Si3N4), silicon monoxide (SiO), silicon oxycarbide (SiOC), vacuum, and other dielectrics or other suitable materials.

FIG.7shows an example fabrication process700.FIGS.8A to8Hshow a wafer800in various stages of the fabrication process700in making a transistor device, e.g., TFET devices100,300,400,500,600of the disclosure. The example TFET100ofFIG.1is used as an example to illustrate the example fabrication process700.

Referring toFIG.7, with reference also toFIG.8A, in example operation710, a wafer800is received. The wafer800includes a substrate810. The substrate810is an indium phosphide (“InP”) substrate or a silicon substrate having an InP layer thereover. The substrate810may also include other element semiconductors, such as germanium, or other compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and/or sapphire. Further, the substrate810may also include a silicon-on-insulator (SOI) structure. The substrate810may include an epitaxial layer and/or may be strained for performance enhancement. The substrate810may also include various doping configurations depending on design requirements as is known in the art, such as P-type substrate and/or N-type substrate and various doped regions such as P-wells and/or N-wells. As an illustrative example, the substrate810is a P-doped InP substrate.

In example operation720, with reference also toFIG.8B, a first semiconductor layer820of a P-doped III-V compound semiconductor material, e.g., GaAsSb, is formed over the InP substrate810. The GaAsSB layer820is formed using an epitaxy process, e.g., metalorganic chemical vapor deposition (“MOCVD”) or molecular beam epitaxy (“MBE”). For example, the MOCVD process uses one or more of TMGa, TEGa or TTBGa as the Ga source precursor, one or more of TBAs, TMAs, DETBAs as the As source precursor and one or more of TMSb or TESb as the Sb source precursor. In an embodiment, the GaAsSb layer820is doped as P-type by the supply of additional Si, Mg, C or Zn containing precursors, e.g., CBr4for C source, Si2H6for Si source or DEZn for Zn source. Other suitable doping procedures, e.g., ion implantation of Si, Mg, C or Zn impurities for P-type doping, are also possible and included in the disclosure. The MOCVD growth temperature for the GaASSb layer820ranges between about 500° C. and about 600° C.

In example operation730, with reference also toFIG.8C, a second semiconductor layer830of a second compound semiconductor material, e.g., InGaAs, is formed over the GaAsSb layer820. The InGaAs layer830is formed using an epitaxy process, e.g., metalorganic chemical vapor deposition (“MOCVD”) or molecular beam epitaxy (“MBE”). For example, the MOCVD process uses one or more of TMIn or DADI as the In source precursor, one or more of TMGa, TEGa or TTBGa as the Ga source precursor, one or more of TBAs, TMAs, DETBAs as the As source precursor. In an embodiment, the InGaAs layer830is intrinsic or unintentionally lightly doped as N-type. In other embodiments, the InGaAs layer830is intentionally doped lightly as N-type (“N−”) using an impurity gas of dopant precursors of DETe as the Te source or Si2H6as the Si source. The MOCVD growth temperature for the InGaAs layer830ranges between about 500° C. and about 700° C. In an embodiment, the InGaAs alloy has a composition of InxGa1-xAs, with 0<x<1, where x indicates the atom ratio of In as compared to the atom ratio of Ga in the alloy. Note that the InGaAs alloy includes InAs and GaAs. If x=0.3, it means that 30 percent of the alloy composition is InAs and 70% of the alloy composition is GaAs. In some embodiment, 0.2≤x≤0.9.

In an embodiment, the thickness of the InGaAS layer830is controlled to be less than 10 nm.

In example operation740, with reference also toFIG.8D, a third semiconductor layer840of III-V compound semiconductor material is formed over the second semiconductor layer830. The third semiconductor layer840may include an InGaAs alloy having composition of InyGa1-yAs, where y indicate the atom ratio of In as compared to the atom ratio of Ga in the alloy and where y≤x. In some embodiment, y<x. That is, the InGaAs alloy in the third semiconductor layer840includes a higher ratio of Ga with respect to In as compared to the second semiconductor layer830. As such, the InyGa1-yAs layer840includes a higher tunneling barrier than the InxGa1-xAs layer830. In an embodiment, the InGaAS layer840is intrinsic or unintentionally lightly doped as N-type. In other embodiments, the InGaAs layer830is intentionally doped lightly as N-type (“N−”) using an impurity gas of dopant precursors of DETe as the Te source or Si2H6as the Si source.

In example operation750, with reference also toFIG.8E, a fourth semiconductor layer850of III-V compound semiconductor material is formed over the third semiconductor layer840. The fourth semiconductor layer850may include an InGaAs alloy doped as N-type. For example, the InGaAs layer850is formed with an additional impurity gas supply of dopant precursors of DETe as the Te source or Si2H6as the Si source. The doping concentration of the InGaAs layer850(N+) is higher than that of the unintentionally doped or lightly doped InGaAs layers830,840. The unintentionally doped InGaAs layers830,840may include an average impurity/carrier concentration of about (5±1.3)*1011cm−3. In an embodiment, the doping concentration of the InGaAs layer850is more than 2 times higher than that of the unintentionally doped or lightly doped InGaAs layers830,840. In another embodiment, the doping concentration of the InGaAs layer850is more than 3 times higher than that of the unintentionally doped or lightly doped InGaAs layers830,840.

In example operation760, with reference also toFIG.8F, the InGaAs layers840,850are patterned to form pattern stacks852A,852B. The pattern stack852A includes a first pattern portion850A of the InGaAs layer850over a first pattern portion840A of the InGaAs layer840. The pattern stack852B includes a second pattern portion850B of the InGaAs layer850over a second pattern portion840B of the InGaAs layer840. The pattern stacks852A,852B overlap or cover a surface portion830A,830B of the InGaAs layer830, respectively, and are spaced apart from one another. A surface portion830G of the InGaAS layer830is positioned between the surface portions830A and830B.

In an embodiment, the InGaAs layer830is also patterned to remove edge portions830E (shown in dotted lines) that laterally extend outward beyond the surface portions830A,830B.

The processes740-760show a top-down approach of forming the pattern stacks852A,852B. In another embodiment, the pattern stacks852A,852B may also be formed using a bottom-up approach. For example, as shown inFIG.8F(1), a mask layer854is formed and patterned over the InGaAs layer830to have apertures856A,856B exposing the surface portions830A,830B. The pattern stacks852A,852B are formed within the apertures856A,856B using selective area growth (“SAG”) approaches using MOCVD, vapor-phase epitaxy and/or crystal facet-controlled epitaxial lateral overgrowth (“FACELO”) techniques or other suitable growth mechanisms.

Within each of the pattern stack852A,852B, the layers840A,850A,840B,850B may be formed through controlling the precursor components and ratios and other growth conditions, or other suitable approaches, which are all included in the disclosure. Subsequently, the remaining mask layer854may be removed using selective etching and the InGaAS layer830may be patterned to obtain the wafer800stage as shown inFIG.8F.

In example operation770, with reference also toFIG.8G, a high-K gate dielectric layer864, e.g., HfO2, and a conductive layer862are formed over the surface of the wafer800. The high-K dielectric material may be selected from one or more of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfArO), combinations thereof, and/or other suitable materials ZrO2, Al2O3, LaO, TiO, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO. The high-K dielectric layer864may be formed by atomic layer deposition (“ALD”) or other suitable technique. In accordance with embodiments described herein, high-K dielectric layer864includes a thickness ranging from about 5 to about 20 angstrom (A) or other suitable thickness.

The conductive layer862is tungsten (W) or titanium nitride (TiN). Other suitable materials for conductive layer862may include ruthenium, palladium, platinum, tungsten, cobalt, nickel, and/or conductive metal oxides, hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), and other suitable conductive materials.

The conductive layer862may be formed through sputtering or atomic layer deposition (“ALD”).

In example operation780, with reference also toFIG.8H, the conductive layer862and the dielectric layer864are patterned to form first gate structure860and second gate structures870. The first gate structure860and the second gate structures870are separated from one another. The first gate structure860is positioned between the pattern stacks852A,852B and is adjacent to the sidewalls850S,840S of the layers850(850A,850B),840(840A,840B). The first gate860is also adjacent to the surface portion830G of the second semiconductor layer830.

The second gate structures870are each adjacent to the sidewalls850S′,840S′ of the layers850(850A,850B),840(840A,840B). The sidewalls850S′,840S′ are different from, e.g., opposite to, the sidewalls840S,850S. The second gate structures870are also adjacent to sidewalls830S of the second semiconductor layer830and are adjacent to the first semiconductor layer820.

In an embodiment, the first semiconductor layer820(P+type) is configured as a source of a N-type TFET, the second semiconductor layer830(N−type or intrinsic) is configured as a first channel layer, the third semiconductor layer840((N−type or intrinsic840A,840B) is configured as a second channel layer (or an interlayer), and the fourth semiconductor layer850(P+type850A,850B) is configured as a drain layer. The two pattern stacks852A,852B each covers or overlaps a surface portion830A,830B, respectively, of the channel layer830. The surface portions830A,830B are separated by the surface portion830G that is in contact with the first gate structure860.

Although illustrated with the example TFET100, the example process700may be used, with slight modifications/variations, to make other TFET structures or other transistor structures.FIG.9shows three example TFET structures900A,900B and900C, which can be made by the example process700and are included in the structure embodiments of the disclosure. The three examples900A,900B and900C are not shown to include a second gate structure for simplicity purposes. A second gate structure may be added to one or more of the structures900A,900B or900C. The three examples900A,900B and900C show that different materials may be used for the source, first channel, interlayer (second channel) and/or drain layers of a TFET of the disclosure. The process and structures are also applicable to a P-type TFET with a P-doped drain layer.

The second channel layer vertically stacked between the first channel and the drain improves the OFF state characteristic of the disclosed TFETs because the source to drain leakage tunneling is substantially blocked by the second channel. The U-shaped or L-shaped first gate applies a gate electrical field in parallel to the main BTBT current moving from the source to the first channel, which ensures a high ON state BTBT current. The second gate structure further enhances the OFF state characteristic by adding additional gate control of the first channel and second channel to misalign the conductivity bands.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present description. Those skilled in the art should appreciate that they may readily use the present description as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present description, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present description.

In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

The present disclosure may be further appreciated with the description of the following embodiments:

In a tunnel field-effect transistor embodiment, a tunnel field-effect transistor includes a substrate, a source layer over the substrate, a first channel layer over the source layer, the first channel layer including a first portion and a second portion, a second channel layer over the first portion of the first channel layer, a first drain layer over the second channel layer, and a first gate structure over the second portion of the first channel layer and adjacent to a first sidewall of the second channel layer.

In another semiconductor structure embodiment, a structure includes: a substrate, a first semiconductor layer of a first III-V compound semiconductor material and doped as a first conductivity type over the substrate, a second semiconductor layer of a second III-V compound semiconductor material over the first semiconductor layer, a gate structure positioned over and contacting a first upper surface portion of the second semiconductor layer, and two vertical semiconductor stacks adjacent to the gate structure from two opposite sides of the gate structure. Each of the two vertical semiconductor stacks includes a third semiconductor layer and a fourth semiconductor layer. The third semiconductor layer has a same second III-V compound semiconductor material as the second semiconductor layer but with a different material composition. The fourth semiconductor layer is doped as a second conductivity type different from the first conductivity type.

A method embodiment forms a first semiconductor layer of a first III-V compound semiconductor material and a first conductivity type over a substrate. A second semiconductor layer is formed over the first semiconductor layer. The second semiconductor layer has a first portion and a second portion adjacent to the first surface portion. The second portion has a second III-V compound semiconductor material. A vertical stack of semiconductor layers are formed over the first portion of the second semiconductor layer. The vertical stack includes a third semiconductor layer and a fourth semiconductor layer stacked over the third semiconductor layer. The third semiconductor layer has a same second III-V compound semiconductor material as the second portion of the second semiconductor layer but with a different material composition. The fourth semiconductor layer has a second conductivity type. A gate structure is formed over the second portion of the second semiconductor layer. The gate structure contacts a sidewall of the third semiconductor layer.