Patent ID: 12192659

DESCRIPTION OF EMBODIMENTS

Modes for carrying out the present technique (hereinafter also referred to as “embodiments”) will be described below. The description will be given in the following order.1. First embodiment (an example of transferring a charge to a pair of charge holding regions)2. Second embodiment (an example of sharing a floating diffusion region and transferring a charge to a pair of charge holding regions)3. Third embodiment (an example of adjusting a height of a potential barrier and transferring a charge to a pair of charge holding regions)4. Example of application to mobile object

1. First Embodiment

[Configuration Example of Imaging Device]

FIG.1is a block diagram showing a configuration example of an imaging device100according to a first embodiment of the present technique. The imaging device100is a device that captures image data and includes an imaging lens110, a solid-state imaging element200, a recording unit120, and an imaging control unit130. As the imaging device100, for example, a digital camera or an electronic device having an imaging function (a smartphone, a personal computer, or the like) is assumed.

The solid-state imaging element200captures image data under the control of the imaging control unit130. The solid-state imaging element200supplies the image data to the recording unit120via a signal line209.

The imaging lens110collects light and guides it to the solid-state imaging element200. The imaging control unit130controls the solid-state imaging element200to capture the image data. The imaging control unit130supplies, for example, an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging element200via a signal line139. The recording unit120records the image data.

Here, the vertical synchronization signal VSYNC is a signal indicating timing of imaging, and a periodic signal having a constant frequency (60 hertz, etc.) is used for the vertical synchronization signal VSYNC.

Also, although the imaging device100records the image data, the image data may be transmitted to the outside of the imaging device100. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging device100may further display the image data. In this case, a display unit is further provided.

[Configuration Example of Solid-State Imaging Element]

FIG.2is a block diagram showing a configuration example of the solid-state imaging element200according to the first embodiment of the present technique. The solid-state imaging element200includes a vertical scanning circuit211, a pixel array unit212, a timing control circuit213, a digital to analog converter (DAC)214, a load MOS circuit block250, and a column signal processing circuit260. A plurality of pixels220are arranged in a two-dimensional grid pattern in the pixel array unit212.

Hereinafter, a set of pixels220arranged in a horizontal direction will be referred to as a “row,” and a set of pixels220arranged in a direction perpendicular to the row will be referred to as a “column.”

The timing control circuit213controls operation timing of the vertical scanning circuit211, the DAC214, and the column signal processing circuit260in synchronization with the vertical synchronization signal VSYNC from the imaging control unit130.

The DAC214generates an analog reference signal that fluctuates with a lapse of time through digital to analog (DA) conversion. For example, a sawtooth wave shape ramp signal is used for the reference signal. The DAC214supplies the generated reference signal to the column signal processing circuit260.

The vertical scanning circuit211selects and drives rows in order and outputs analog pixel signals. The pixels220photoelectrically convert incident light to generate the analog pixel signals. The pixels220supply the pixel signals to the column signal processing circuit260via the load MOS circuit block250.

The load MOS circuit block250is provided with MOS transistors that supply a constant current for each column.

The column signal processing circuit260executes signal processing such as AD conversion processing and high-dynamic-range (HDR) combination on the pixel signals for each column. The column signal processing circuit260supplies image data including the processed signals to the recording unit120. Also, the column signal processing circuit260is an example of the signal processing circuit described in the claims.

[Configuration Example of Pixel]

FIG.3is a circuit diagram showing a configuration example of the pixel220according to the first embodiment of the present technique. The pixel220includes a charge discharge transistor221, a photoelectric conversion element222, transfer transistors223,225and227, charge holding regions224and226, and a floating diffusion region228. Further, the pixel220includes a reset transistor231, an amplification transistor232and a selection transistor233.

Capacities of the charge holding regions224and226are different from each other. For example, the capacity of the charge holding region224is larger than that of the charge holding region226. The charge holding region224is an example of the front-stage charge holding region described in the claims, and the charge holding region226is an example of the rear-stage charge holding region described in the claims.

The transfer transistors223,225and227are connected in series between the photoelectric conversion element222and the floating diffusion region228. Also, the charge holding region224is inserted between a connection node of the transfer transistors223and225and a ground node, and the charge holding region226is inserted between a connection node of the transfer transistors225and227and a ground node.

The charge discharge transistor221discharges a charge from the photoelectric conversion element222in accordance with a control signal OFG from the vertical scanning circuit211. This operation is hereinafter referred to as “photo diode (PD) reset.”

Here, for all pixels, the vertical scanning circuit211turns the transfer transistor223off when exposure starts and turns the transfer transistors225and227and the reset transistor231on when the exposure ends. Thus, the charge holding regions224and226and the floating diffusion region228are initialized. This operation is hereinafter referred to as “storage (ST) reset.” Immediately after the ST reset, the vertical scanning circuit211turns the transfer transistor227and the reset transistor231off and turns the transfer transistors223and225on. Thus, the charge is transferred from the photoelectric conversion element222to the charge holding regions224and226.

Immediately after the charge is transferred from the photoelectric conversion element222to the charge holding regions224and226, the vertical scanning circuit211turns the transfer transistors223and225off. Thus, the charge holding region224and the charge holding region226are separated from each other. After this separation, the vertical scanning circuit211turns the transfer transistor227on.

Thus, the charge is transferred from the charge holding region226to the floating diffusion region228, and an analog pixel signal corresponding to an amount of charge in the charge holding region226is AD-converted. Then, the vertical scanning circuit211turns the transfer transistors225and227on. Thus, an analog pixel signal corresponding to an amount of charge in the charge holding regions224and226is AD-converted.

The photoelectric conversion element222generates a charge (electrons, etc.) through photoelectric conversion for incident light.

The transfer transistor223transfers the charge from the photoelectric conversion element222to the charge holding regions224and226in accordance with a transfer signal TX1from the vertical scanning circuit211. Also, the transfer transistor223is an example of the front-stage transfer transistor described in the claims.

The transfer transistor225transfers the charge from the charge holding region224to the charge holding region226in accordance with a transfer signal TX2from the vertical scanning circuit211. As described above, the vertical scanning circuit211turns the transfer transistors225and227on after the charge is transferred from the charge holding region226to the floating diffusion region228. For this reason, the charge that remains in the charge holding region224is transferred to the floating diffusion region228via the charge holding region226and the turned-on transfer transistor227. Also, the transfer transistor225is an example of the intermediate transfer transistor described in the claims.

The transfer transistor227transfers the charge from the charge holding region226to the floating diffusion region228in accordance with a transfer signal TG from the vertical scanning circuit211. Also, the transfer transistor227is an example of the rear-stage transfer transistor described in the claims.

The reset transistor231extracts the charge from the floating diffusion region228to initialize it in accordance with a reset signal RST from the vertical scanning circuit211. The vertical scanning circuit211turns the reset transistor231on while turning the transfer transistors225and227off, so that it can initialize the floating diffusion region228only. This operation is hereinafter referred to as “floating diffusion (FD) reset.”

The amplification transistor232amplifies the analog signal corresponding to the amount of charge in the floating diffusion region228. The selection transistor233outputs the amplified analog signal as a pixel signal to a vertical signal line239in accordance with a selection signal SEL from the vertical scanning circuit211.

FIG.4is an example of a cross-sectional view of the pixel220according to the first embodiment of the present technique. A p-type semiconductor substrate320in which p-type impurities are diffused is laminated on a n-type semiconductor substrate310. On a front surface of the p-type semiconductor substrate320, n+ layers331,335, and336and p+ layers337,338, and339are formed. Further, n layers332,333, and334, which are diffusion regions of n-type impurities, are formed below the p+ layers337,338, and339. These p+ layers337,338, and339function as pinning layers and serve to fill incomplete bonds between atoms at a silicon interface with holes to improve dark current and fix an interface potential.

Further, on the front surface of the p-type semiconductor substrate320, a gate electrode341is provided in a region straddling between the n+ layer331and the p+layer337via an oxide film. A gate electrode342is provided in a region straddling between the p+layer337and the p+layer338via an oxide film. A gate electrode343is provided in a region straddling between the p+layer338and the p+layer339via an oxide film. A gate electrode344is provided in a region straddling between the p+layer339and the n+layer335via an oxide film. A gate electrode345is provided in a region straddling between the n+layer335and the n+layer336via an oxide film.

The control signal OFG, the transfer signal TX1, the transfer signal TX2, the transfer signal TG, and the reset signal RST are input to the gate electrodes341,342,343,344, and345, respectively. Further, the n+layers331and336are connected to nodes of a power supply voltage VDD.

The n+layer331, the p-type semiconductor substrate320, the p+layer337, and the gate electrode341function as the charge discharge transistor221. Similarly, the gate electrodes342,343,344, and345functions as the transfer transistor223, the transfer transistor225, the transfer transistor227, and the reset transistor231, respectively, together with semiconductor regions below them.

The n layer332functions as the photoelectric conversion element222. The n layers333and334function as the charge holding regions224and226. As illustrated in the figure, a region321between the n layer333(charge holding region224) and the n layer334(charge holding region226) is a diffusion region of p-type impurities (in other words, the p-type semiconductor substrate320) having a polarity different from those of them.

An applied voltage level to a gate of each transistor of the charge discharge transistor221and the like and its control timing can be set independently. In a case in which a particular transistor is turned on, the vertical scanning circuit211applies a positive voltage to a gate of that transistor to lower a potential under the gate. Further, when a transistor is turned off, the vertical scanning circuit211applies a ground or a negative voltage to the transistor. In a case in which a voltage applied to a gate is negative, holes are attracted to an electric field under the gate and gather at a silicon interface, and the same effect as the above-mentioned pinning layer can be obtained.

FIG.5is an example of a potential diagram of the pixel220according to the first embodiment of the present technique. A solid line in the figure shows potentials when the charge discharge transistor221, the transfer transistors223,225and227, and the reset transistor231are turned off. Also, fine dotted lines indicate potentials when each of the charge discharge transistor221and the transfer transistor223is turned on. An alternate long and short dash line indicates a potential when the transfer transistor225is turned on. A rough dotted line indicates a potential when the transfer transistor227is turned on. Further, reference sign ST1in the figure shows the charge holding region224, and reference sign ST2in the figure shows the charge holding region226. Reference sign FD indicates the floating diffusion region228.

As illustrated in the figure, when the transfer transistor223is turned off, a potential barrier is generated between the photoelectric conversion element222and the charge holding region224. Further, when the transfer transistor225is turned off, a potential barrier is generated between the charge holding region224and the charge holding region226, and when the transfer transistor227is turned off, a potential barrier is generated between the charge holding region226and the floating diffusion region228. As illustrated inFIG.4, there is the p-type region321between the n-type charge holding region224and the n-type charge holding region226, and thus, due to this n-p-n structure, as illustrated inFIG.5, the potential barrier is formed between the charge holding region224and the charge holding region226.

Further, potentials of the charge holding region224(ST1) and the charge holding region226(ST2) are designed to satisfy the following two conditions. A first condition is that the potential of ST2when the charge is transferred from the photoelectric conversion element222to ST1and ST2is lower than that of ST1. A second condition is that there is a potential barrier between ST1and ST2during charge holding after the charge is transferred from the photoelectric conversion element222to ST1and ST2. These two conditions can be satisfied by adjusting impurity concentrations of wells that form the potentials of ST1and ST2at the time of manufacturing. Alternatively, the two conditions can be satisfied by adjusting voltage levels and timing applied to gates of transistors and polysilicon disposed on or around ST1and ST2. Alternatively, these conditions can be satisfied by both adjusting the impurity concentrations and adjusting the voltage levels and timing.

Further, when an amount of charge that can be held by ST2alone is defined as Qh, this Qh is a value proportional to a product of a height of the potential barrier under the second condition and a capacity of ST2.

In a case in which illuminance is so low that the amount of charge transferred from the photoelectric conversion element222to ST1and ST2is Qh or less, all the charge at the time of transfer passes through ST1and moves to ST2due to the first condition. For this reason, ST1becomes empty. Then, due to the second condition, the charge that has entered ST2remains and is held in ST2by the potential barrier. Further, even if there is photoelectric conversion due to light leakage generated in ST1during charge holding, the charge of ST1remains in ST1and does not enter ST2due to the potential barrier. On the other hand, in a case in which illuminance is so high that the amount of charge transferred from the photoelectric conversion element222to ST1and ST2becomes larger than Qh, the charge is distributed and held in both ST1and ST2.

FIG.6is a plan view showing an example of a layout of elements in the pixel220according to the first embodiment of the present technique. Hereinafter, the optical axis is defined as the Z axis, and a predetermined axis perpendicular to the Z axis is defined as the X axis. The axis perpendicular to both the X axis and the Z axis is defined as the Y axis.” The figure shows a layout seen from the optical axis (Z axis) direction.

As illustrated in the figure, the charge discharge transistor221, the transfer transistors223,225, and227, and a transistor arrangement region230are disposed around the photoelectric conversion element222. The reset transistor231, the amplification transistor232, and the selection transistor233are disposed in the transistor arrangement region230.

FIG.7is an example of a cross-sectional view cut along line A-B inFIG.6according to the first embodiment of the present technique. A surface of both surfaces of the p-type semiconductor substrate320, on which a wiring layer414is formed, is defined as a front surface, and the photoelectric conversion element222and the charge holding region224(ST1) are formed on the front surface. The solid-state imaging element200having the photoelectric conversion element222formed on the front surface in this way is generally called a surface-illuminated solid-state imaging element.

An upper portion of the photoelectric conversion element222is open, and an upper portion of the charge holding region224(ST1) is plane-shielded form light by a metal of the wiring layer414. Light-shielding walls411and412are formed around the pixel220by deep trench isolation (DTI). Further, since it is necessary to form a charge transfer channel413between the photoelectric conversion element222and ST1, a light-shielding wall cannot be placed, and light rays such as incident light415may leak into ST1. This leaked light causes an undesired image artifact.

Resistance to this phenomenon is called PLS resistance.

FIG.8is an example of a cross-sectional view cut along line C-D inFIG.6according to the first embodiment of the present technique. An upper portion of the charge holding region226(ST2) is also shielded from light by a metal. Further, unlike the charge holding region224(ST1), a light-shielding wall416is formed between the photoelectric conversion element222and ST2. Thus, it is possible to prevent the charge from leaking from the photoelectric conversion element222to ST2, and the PLS resistance of ST2can be made stronger than that of ST1.

FIG.9is an example of a cross-sectional view cut along line E-F inFIG.6according to the first embodiment of the present technique. A light-shielding wall417is formed around the pixel220, and the upper portions of the charge holding region224(ST1) and the charge holding region226(ST2) are shielded from light by the metal of the wiring layer414.

Also, inFIGS.7to9, for convenience of description, a color filter and an on-chip lens on the upper portion of the photoelectric conversion element222are omitted.

[Configuration Example of Column Signal Processing Circuit]

FIG.10is a block diagram showing a configuration example of a load MOS circuit block250and a column signal processing circuit260according to the first embodiment of the present technique.

The vertical signal line239is wired for each column in the load MOS circuit block250. When the number of columns is set to I (I is an integer), I vertical signal lines239are wired. Further, a load MOS transistor251that supplies a constant current is connected to each of the vertical signal lines239.

A plurality of ADCs261and a digital signal processing unit262are disposed in the column signal processing circuit260. The ADCs261are disposed for each column. When the number of columns is set to I, I ADCs261are disposed.

The ADC261uses a reference signal (a ramp signal Rmp, etc.) from the DAC214to convert an analog pixel signal from a corresponding column into a digital signal. The ADC261supplies the digital signal to the digital signal processing unit262.

The digital signal processing unit262performs predetermined signal processing such as correlated double sampling (CDS) processing and HDR combination processing for each of digital signals of each column. The digital signal processing unit262supplies image data including the processed digital signals to the recording unit120.

[Operation Example of Solid-State Imaging Element]

FIG.11is a timing chart showing an example of a global shutter operation of the solid-state imaging element200according to the first embodiment of the present technique. The vertical scanning circuit211supplies the control signal OFG to all the pixels from timing TO immediately before start of exposure to timing T1of the start of exposure, turns the charge discharge transistor221on, and performs PD reset. Hereinafter, the number of rows is set to N (N is an integer), and a control signal to a pixel in an n-th (n is an integer of 1 to N) row is set to OFG_[n]. The same applies to the reset signal RST and the transfer signals TX1, TX2, and TG.

During an exposure period of timings T1and T2, the photoelectric conversion elements222of all pixels perform photoelectric conversion. Such control of exposing all pixels at the same time is called a global shutter method. An amount of charge generated varies depending on illuminance of incident light. At the timing T2of end of the exposure, the vertical scanning circuit211turns the reset transistors231and the transfer transistors225and227of all the pixels on in accordance with the reset signal RST, the transfer signals TX2, and the TG signal. Thus, the charge holding regions224and226and the floating diffusion regions228of all the pixels are reset (ST reset).

Then, at timing T3, the vertical scanning circuit211turns the transfer transistors225of all pixels off in accordance with the transfer signal TX2, and at timing T4immediately after T3, turns the transfer transistors227of all pixels off in accordance with the transfer signal TG. At timing T5immediately after the timing T4, the vertical scanning circuit211turns the reset transistors231of all pixels off in accordance with the reset signal RST. In this way, the vertical scanning circuit211turns the transfer transistor225, the transfer transistor227, and the reset transistor231off in order. This control makes it possible to maintain a state in which the potential decreases from the charge holding region224(ST1) toward the floating diffusion region228, and completely reset ST1and ST2of all the pixels.

At timing T6immediately after the ST reset, the vertical scanning circuit211turns the transfer transistors223and225of all pixels on in accordance with the transfer signals TX1and TX2to transfer the charge of the photoelectric conversion element222to the charge holding regions224and226. At this time, the potential of the photoelectric conversion element222is higher than that of the charge holding region224(ST1) and the potential of ST1is higher than that of the charge holding region226(ST2). This magnitude relationship in potential is realized by adjusting implantation concentrations at the time of manufacturing and adjusting on-voltage levels applied to gates of the transfer transistors223and225.

Then, at timing T7, the vertical scanning circuit211turns the transfer transistors223of all pixels off in accordance with the transfer signal TX1, and at timing T8immediately after T7, turns the transfer transistors225of all pixels off in accordance with the transfer signal TX2. In this way, by turning the transfer transistor223and the transfer transistor225off in order, a low illuminance charge in ST2does not flow back to ST1. In the case of low illuminance, the charge is held only in ST2. On the other hand, in the case of high illuminance, the charge is held in both ST1and ST2.

FIGS.12A,12B, and12Can are examples of a potential diagram showing the first embodiment of the present technique until the ST reset when illuminance is low.FIG.12Ais an example of the potential diagram at the time of the PD reset, andFIG.12Bis an example of the potential diagram during exposure accumulation.FIG.12Cis an example of the potential diagram at the time of the ST reset.

As illustrated in a in the figureFIG.12A, the vertical scanning circuit211turns the transfer transistors223,225, and227and the reset transistor231off while turning only the charge discharge transistor221on, thereby performing the PD reset. Then, as illustrated inFIG.12B, the vertical scanning circuit211turns the charge discharge transistor221off, thereby executing the exposure accumulation. Subsequently, as illustrated inFIG.12C, the vertical scanning circuit211turns the transfer transistors225and227and the reset transistor231on to perform the ST reset.

FIGS.13A and13Bare examples of a potential diagram showing the first embodiment of the present technique until the separation of the charge holding regions when illuminance is low.FIG.13Ais an example of a potential diagram at the time of the charge transfer to the charge holding regions224and226.FIG.13Bis an example of a potential diagram when the charge holding region224is separated from the charge holding region226.

As illustrated inFIG.13A, the vertical scanning circuit211turns the transfer transistors223and225on while the transfer transistor227and the reset transistor231are turned off. Thus, the charge is transferred from the photoelectric conversion element222to the charge holding regions224and226. In the case of low illuminance, the charge is held only in ST2.

Then, as illustrated inFIG.13B, the vertical scanning circuit211turns the transfer transistors223and225off, thereby separating the charge holding region224from the charge holding region226.

FIGS.14A,14B, and14Care examples of a potential diagram showing the first embodiment of the present technique until the ST reset when illuminance is high.FIG.14Ais an example of a potential diagram at the time of the PD reset, andFIG.14Bis an example of a potential diagram during the exposure accumulation.FIG.14Cis an example of a potential diagram at the time of the ST reset. These potential diagrams are the same as those illustrated inFIGS.12A,12B, and12C, except that the amount of charge is different.

FIGS.15A and15Bare examples of a potential diagram showing the first embodiment of the present technique until the separation of the charge holding regions when illuminance is high.FIG.15Ais an example of a potential diagram at the time of the charge transfer to the charge holding regions224and226.FIG.15Bis an example of a potential diagram when the charge holding region224is separated from the charge holding region226. These potential diagrams are the same as those illustrated inFIGS.13A and13B, except that the amount of charge is different. As illustrated inFIGS.15A and15B, in the case of high illuminance, the charge is held in both ST1and ST2.

FIG.16is a timing chart showing an example of an operation of reading out a row when illuminance is low according to the first embodiment of the present technique. A readout operation in the figure is executed row by row in order after the global shutter illustrated inFIG.11.

For example, at timings T11and T16, a horizontal synchronization signal XHS is supplied to the column signal processing circuit260by the timing control circuit213. The vertical scanning circuit211supplies a selection signal SEL in synchronization with the horizontal synchronization signal XHS. For example, when a first row is selected within the period from the timing T11to T16, a selection signal SEL_[1] is supplied.

At the timing T11, the vertical scanning circuit211supplies the reset signal RST over a pulse period to turn the reset transistor231on, thereby performing FD reset. In a period until timing T12, a reset level at the time of the FD reset is output to the vertical signal line239via the amplification transistor232and the selection transistor233and is AD-converted by the column signal processing circuit260. This reset level is also called a P phase level. The P phase level after the AD conversion is defined as Vp.

Then, at the timing T12, the vertical scanning circuit211supplies the transfer signal TG over the pulse period to turn the transfer transistor227on and transfers the charge in the charge holding region226(ST2) to the floating diffusion region228. The charge in the charge holding region224(ST1) and the charge holding region226(ST2) is a signal charge generated through photoelectric conversion, and a signal level corresponding to an amount of charge of the signal is called a D phase level. In a period until timing T13, this D phase level is AD-converted by the column signal processing circuit260. The D phase level after the first AD conversion is defined as Vd1.

Subsequently, at timing T13, the vertical scanning circuit211supplies the transfer signals TG and TX2to turn the transfer transistors225and227on and transfers the charge in the charge holding region224(ST1) to the floating diffusion region228. Further, at timing T14, the vertical scanning circuit211turns the transfer transistor225off and at timing T15immediately after T14, turns the transfer transistor227off. By turning the transfer transistors225and227off in order, the potential of ST2can be maintained higher than that of the floating diffusion region228, so that the signal charge of ST1can be completely transferred to the floating diffusion region228.

In a period until the timing T13, the D phase level is AD-converted by the column signal processing circuit260. The D phase level after the second AD conversion is defined as Vd2. In the second time, the charge transferred from the charge holding region224to the floating diffusion region228is added to the charge transferred from the charge holding region226in the first time. For this reason, the second D phase level becomes a level corresponding to a value obtained by adding the amount of charge held in each of the charge holding regions224and226.

The column signal processing circuit260performs the following calculation in the CDS processing. By the CDS processing, reset noise of the floating diffusion region228and a noise offset of the circuit can be canceled.
Δ1=Vd1−Vp
Δ2=Vd2−Vp

The column signal processing circuit260compares a difference Δ1with a predetermined threshold Δth and determines whether or not the difference Δ1is equal to or less than the threshold Δth. Here, the threshold Δth is an amount of charge that ST2can safely hold alone and is proportional to a product of the capacity of ST2, the potential barrier between ST1and ST2, and a charge-voltage conversion efficiency of the floating diffusion region228.

As illustrated in the figure, in a case in which the difference Δ1is equal to or less than the threshold Δth, the column signal processing circuit260determines that illuminance is relatively low and outputs the difference Δ1as a final pixel signal. On the other hand, in a case in which the difference Δ1is larger than the threshold Δth, the column signal processing circuit260determines that illuminance is relatively high and outputs a difference Δ2as the final pixel signal.

In this way, the low illuminance pixel outputs the difference Δ1, and the high illuminance pixel outputs the difference Δ2, so that the PLS of the low illuminance signal can be reduced.

In addition, since ST2can secure a wider distance from the open photoelectric conversion element222than ST1, it is difficult for leaked light to reach it. Further, since ST2only needs to receive a part of the signal charge in the full range, the capacity of ST2remains small. Due to both of these effects, the light leakage generated in ST2can be effectively inhibited.

Here, in the image data, in particular, an artifact that generally occurs in a low illuminance signal is easily noticeable. The reason for this may be that a large amount of optical shot noise is included along with a high illuminance signal, and even if there is an artifact, it is buried in the optical shot noise and is not noticeable.

In the solid-state imaging element200, as described above, a low illuminance charge signal in which an artifact is noticeable is held in ST2that is less susceptible to light leakage, and thus influence of light leakage is reduced.

FIG.17is an example of a potential diagram at the time of reading out when illuminance is low according to the first embodiment of the present technique. In the case of low illuminance, no signal charge remains in ST1when the first D phase level is read out, as illustrated in the figure. The potential diagram at the time of reading out the second D phase level is the same as that of the first D phase level.

FIG.18is a timing chart showing an example of an operation of reading out a row when illuminance is high according to the first embodiment of the present technique. Readout control in the figure is the same as the control illustrated inFIG.16As illustrated in the figure, in a case in which illuminance is high, the difference Δ1becomes larger than the threshold Δth. In this case, the column signal processing circuit260outputs the difference Δ2as the final pixel signal.

FIGS.19A and19Bare examples of a potential diagram at the time of reading out when illuminance is high according to the first embodiment of the present technique.FIG.19Ais an example of the potential diagram at the time of reading out the first D phase level, andFIG.19Bexample of the potential diagram at the time of reading out the second D phase level.

As illustrated inFIG.19A, in the case in which illuminance is high, the signal level remains in ST1when the first D phase level is read out. As illustrated inFIG.19B, the signal charge remaining in ST1is transferred to the floating diffusion region228, added to the amount of charge of the first time, and read out as the second D phase level.

FIG.20is a flowchart showing an example of an operation of the solid-state imaging element200according to the first embodiment of the present technique. This operation is started, for example, when a predetermined application for generating an HDR image is executed.

The vertical scanning circuit211in the solid-state imaging element200performs the PD reset for all pixels (step S901) and executes the exposure accumulation (step S902). After the exposure ends, the vertical scanning circuit211performs the ST reset for all the pixels (step S903) and transfers the charge to the charge holding regions224and226(step S904). The vertical scanning circuit211separates the charge holding regions224and226(step S905).

The vertical scanning circuit211selects a row, and the column signal processing circuit260calculates the differences Δ1and Δ2for each column by CDS processing (step S906). The column signal processing circuit260determines whether or not the difference Δ1is equal to or less than the threshold for each column (step S907). In a case in which the difference Δ1is equal to or less than the threshold (step S907: Yes), the column signal processing circuit260selects the difference Δ1and outputs it as the pixel signal (step S908). On the other hand, in a case in which the difference Δ1is larger than the threshold (step S907: No), the column signal processing circuit260selects the difference Δ2and outputs it as the pixel signal (step S909). Also, processes of steps S906to S909are executed for each column in the selected row, but in the figure, for convenience of description, the processes except for one column are omitted.

After step S908or S909, the solid-state imaging element200determines whether or not readout of all rows is completed (step S910). In a case in which the readout of all rows is not completed (step S910: No), the solid-state imaging element200repeatedly executes step S906and subsequent steps. In a case in which the readout of all rows is completed (step S910: Yes), the solid-state imaging element200ends the operation for generating the HDR image.

Also, in a case in which a plurality of HDR images are continuously generated, the processes of steps S901to S910are repeatedly executed in synchronization with the vertical synchronization signal.

As described above, in the first embodiment of the present technique, the leakage of charge from the photoelectric conversion element222to the rear-stage charge holding region226is prevented by the light-shielding wall, and thus the PLS resistance is improved. Further, the transfer transistor223transfers the charge to the charge holding regions224and226, and the transfer transistors225and227sequentially transfer the charge held in each of them to the floating diffusion region228. Thus, the column signal processing circuit260can output either a low illuminance signal or a high illuminance signal for each pixel, reduce the PLS of the low illuminance signal, and improve image quality.

First Modified Example

In the first embodiment described above, the surface-illuminated solid-state imaging element200has been used, but in the surface-illuminated type, it is required to guide the incident light to the photoelectric conversion element222while avoiding the wiring layer414, which may result in insufficient sensitivity. A solid-state imaging element200of a first modified example of the first embodiment is different from that of the first embodiment in that it is a back-illuminated type.

A layout of the solid-state imaging element200of the first modified example of the first embodiment when viewed from the Z axis direction is the same as that of the first embodiment illustrated inFIG.6.

FIG.21is an example of a cross-sectional view cut along line A-B according to the first modified example of the first embodiment of the present technique. As illustrated in the figure, the surface of both surfaces of the p-type semiconductor substrate320on which the wiring layer414is formed is used for the front surface, and the photoelectric conversion element222is formed on the back surface of the front surface. On the back surface, the upper portion of the charge holding region224(ST1) is shielded from light by a metal421. Further, the light-shielding walls411and412are formed around the pixel220through DTI. As illustrated in the figure, the solid-state imaging element200having the photoelectric conversion element222formed on the back surface is called a back-illuminated solid-state imaging element.

FIG.22is an example of a cross-sectional view cut along line C-D according to the first modified example of the first embodiment of the present technique. On the back surface, the upper portion of the charge holding region226(ST2) is shielded from light by the metal421. Further, the light-shielding wall416is formed between the photoelectric conversion element222and ST2. The light-shielding walls416and412around ST2extend from the wiring layer414along the Z axis direction, penetrate the p-type semiconductor substrate320, and are connected to the metal421. This makes it possible to increase light-shielding resistance of ST2.

FIG.23is an example of a cross-sectional view cut along line E-F according to the first modified example of the first embodiment of the present technique. The light-shielding wall417is formed around the pixel220, and the upper portions of the charge holding region224(ST1) and the charge holding region226(ST2) are shielded from light by the metal421on the back surface.

As described above, in the modified example of the first embodiment of the present technique, the photoelectric conversion element222is formed on the back surface of the front surface on which the wiring layer414on the substrate is formed, and thus it is not necessary to guide the incident light to avoid the wiring layer414, so that the sensitivity can be improved as compared with a surface-illuminated type.

Second Modified Example

In the first embodiment described above, the floating diffusion region228has been disposed for each pixel, but in this configuration, it is difficult to reduce a circuit scale of the pixel array unit212. A solid-state imaging element200of a second modified example of the first embodiment is different from that of the first embodiment in that a plurality of pixels share the floating diffusion region228.

FIG.24is a circuit showing a configuration example of a pixel block240according to the second modified example of the first embodiment of the present technique. In the second modified example of the first embodiment, a plurality of pixel blocks240are arranged in the pixel array unit212. Each of the pixel blocks240includes charge discharge transistors221and241, photoelectric conversion elements222and242, and transfer transistors223,225,227,243,245, and247. Further, the pixel block240includes charge holding regions224,226,244, and246, the floating diffusion region228, the reset transistor231, the amplification transistor232, and the selection transistor233.

In the second embodiment, a configuration for connecting the charge discharge transistor221, the photoelectric conversion element222, the transfer transistors223,225, and227, the charge holding regions224and226, and the floating diffusion region228is the same as that of the first embodiment. A configuration for connecting the charge discharge transistor241and the photoelectric conversion element242, the transfer transistors243,245, and247, and the charge holding regions244and246is the same as the corresponding element of the first embodiment. A configuration for connecting the reset transistor231, the amplification transistor232, and the selection transistor233is the same as that of the first embodiment.

Also, the transfer transistors243,245, and247of the second embodiment are connected in series between a connection node of the charge discharge transistor241and the photoelectric conversion element242, and the floating diffusion region228. According to the configuration exemplified in the figure, the pixel block240functions as two pixels, and these pixels share one floating diffusion region228.

Since the plurality of pixels share one floating diffusion region228in this way, the number of elements per pixel is reduced as compared with the first embodiment in which the plurality of pixels do not share one, so that the circuit scale of the pixel array unit212can be reduced.

In addition, the photoelectric conversion elements221and241are examples of the first and second photoelectric conversion elements described in the claims. The transfer transistors223and243are examples of the first and second front-stage transfer transistors described in the claims. The transfer transistors225and245are examples of the first and second intermediate transfer transistors described in the claims. The transfer transistors227and247are examples of the first and second rear-stage transfer transistors described in the claims. The charge holding regions224and244are examples of the first and second front-stage charge holding regions described in the claims. The charge holding regions226and246are examples of the first and second rear-stage charge holding regions described in the claims.

FIG.25is a diagram showing an example of a layout of elements in the pixel block240according to the second modified example of the first embodiment of the present technique. As illustrated in the figure, the charge discharge transistor221, the photoelectric conversion element222, and the transfer transistors223,225, and227are disposed on the left side in the same layout as in the first embodiment. The charge discharge transistor241, the photoelectric conversion element242, and the transfer transistors243,245, and247are disposed on the right side in a symmetrical layout with the left side. The floating diffusion region228is disposed between the transfer transistors227and247, and the transistor arrangement region230is disposed between the photoelectric conversion elements222and242.

Also, inFIGS.24and25, the number of pixels sharing the floating diffusion region228is set to 2, but a plurality of pixels having 3 or more pixels may share the floating diffusion region228. Further, the first modified example of the first embodiment can be applied to the second modified example of the first embodiment.

As described above, in the second modified example of the first embodiment of the present technique, since a plurality of pixels share one floating diffusion region228, the number of elements per pixel can be reduced as compared with the case of not sharing.

2. Second Embodiment

In the first embodiment described above, two independent n layers are provided as the charge holding regions224and226, but since two n layers are required for each pixel, an area of the pixel220increases, which makes it difficult to obtain a finer pixel. A solid-state imaging element200of a second embodiment is different from the first embodiment in that the charge holding regions224and226are formed in one n-layer.

FIG.26is a circuit diagram showing a configuration example of the pixel220according to the second embodiment of the present technique. The pixel220of the second embodiment is different from the first embodiment in that the transfer transistors223and225share the same n-layer. The charge holding regions224and226are formed in the n-layer.

FIG.27is an example of a cross-sectional view of the pixel220according to the second embodiment of the present technique. In the pixel220of the second embodiment, the n layer334and the p+layer339are not formed, and the gate electrodes342and343are formed on the n layer333and the p+layer338. In the n layer333, a left side of the region321below a gap between the gate electrodes342and343is used for the charge holding region224(ST1), and a right side thereof is used for the charge holding region226(ST2). In this way, ST1and ST2are formed in the same n layer333. Thus, as compared with the case in which two independent n layers are provided for ST1and ST2, one n layer is not required, and thus the area of the pixel220can be reduced.

The region321has weaker electrolysis from a gate electrode than the region directly below each of the gate electrodes342and343. For this reason, when the transfer transistors223and225are turned off, the potential of the region321becomes higher than of the region directly under the gate electrode, and a potential barrier is generated in the region321between ST1and ST2.

Further, it is also possible to adjust the potential barrier by adjusting an implantation concentration of impurities in the region321at the time of manufacturing. In this case, for example, an impurity concentration of the region321is adjusted to be lower than that around it

FIG.28is an example of a potential diagram of the pixel220according to the second embodiment of the present technique. The figure shows the potential when the charge discharge transistor221, the transfer transistors223,225, and227, and the reset transistor231are turned off. As illustrated in the figure, since ST1and ST2are formed in the same n layer333, the potential barrier between them when they are turned off is lower than that in the first embodiment.

Also, the first modified example and the second modified example of the first embodiment can be applied to the second embodiment.

As described above, in the second embodiment of the present technique, since the charge holding region224and the charge holding region226are formed in the same n layer333, the n layers can be reduced as compared with the case in which two independent n layers are provided.

3. Third Embodiment

In the second embodiment described above, the charge holding region224and the charge holding region226have been formed in the same n layer333, but in this configuration, the height of the potential barrier between them may be insufficient.

A solid-state imaging element200of a third embodiment is different from the second embodiment in that a transistor for adjusting the height of the potential barrier is provided.

FIG.29is a circuit diagram showing a configuration example of the pixel220according to the third embodiment of the present technique. The pixel220of the third embodiment is different from the second embodiment in that it further includes an adjustment transistor229.

The adjustment transistor229adjusts the potential barrier between the charge holding region224and the charge holding region226in accordance with a control signal TXc from the vertical scanning circuit211.

FIG.30is an example of a cross-sectional view of the pixel220according to the third embodiment of the present technique. The pixel220of the third embodiment is different from the second embodiment in that a gate electrode346is further provided.

In addition, as in the second embodiment, the region of the n layer333immediately below the gate electrode342is used for the charge holding region224(ST1), and the region directly below the gate electrode343is used for the charge holding region226(ST2).

The gate electrode346is disposed between the gate electrode342and the gate electrode343(in other words, directly above the potential barrier), and the control signal TXc is input thereto. The gate electrode346and the semiconductor region below the gate electrode346function as the adjustment transistor229.

The vertical scanning circuit211applies a positive voltage to a gate of the adjustment transistor229and lowers a potential under the gate. Further, when it is turned off, the vertical scanning circuit211applies a ground or a negative voltage to the adjustment transistor229. The vertical scanning circuit211can adjust the potential barrier by adjusting the voltage applied to the gate of the adjustment transistor229. When the voltage applied to the gate of the adjustment transistor229when it is off (when the charge is held in ST1or the like) is set lower than those of the transfer transistors223and225on both sides thereof, the potential barrier immediately below it becomes higher than that around it.

FIG.31is an example of a potential diagram of the pixel220according to the second embodiment of the present technique. The figure shows the potential when the charge discharge transistor221, the transfer transistors223,225, and227, the adjustment transistor229, and the reset transistor231are turned off. As illustrated in the figure, the potential barrier can be raised as compared with the second embodiment by adding the adjustment transistor229.

FIG.32is a timing chart showing an example of a global shutter operation of the solid-state imaging element according to the third embodiment of the present technique. In the third embodiment, control of the PD reset and the exposure accumulation is the same as in the first and second embodiments. At the timing T2, the vertical scanning circuit211turns the reset transistor231, the transfer transistors225and227, and the adjustment transistor229of all pixels on in accordance with the reset signal RST, the transfer signal TX2, the TG signal, and the control signal TXc. Thus, the ST reset is performed.

Further, at the timing T3, the vertical scanning circuit211turns the adjustment transistor229off in accordance with the control signal TXc, and at the timing T4, turns the transfer transistor225off in accordance with the transfer signal TX2.

Then, at the timing T5, the vertical scanning circuit211turns the transfer transistor227off in accordance with the transfer signal TG, and at the timing T6, turns the reset transistor231off in accordance with the reset signal RST.

Subsequently, at the timing T7immediately after the ST reset, the vertical scanning circuit211turns the transfer transistors223and227and the adjustment transistor229of all the pixels on in accordance with the transfer signals TX1and TX2and the control signal TXc to transfer the charge.

Then, at the timing T8, the vertical scanning circuit211turns the transfer transistor223off in accordance with the transfer signal TX1, and at the timing T9immediately after T8, turns the adjustment transistor229off in accordance with the control signal TXc. At the timing T10immediately after T9, the vertical scanning circuit211turns the transfer transistor225off in accordance with the transfer signal TX2.

FIG.33is a timing chart showing an example of an operation of reading out a row when illuminance is low according to the third embodiment of the present technique. The control up to immediately before timing T23is the same as in the first and second embodiments.

At the timing T23, the vertical scanning circuit211supplies the transfer signals TG and TX2and the control signal TXc to turn the transfer transistors225and227and the adjustment transistor229on and transfers the charge to the floating diffusion region228. Further, at timing T24, the vertical scanning circuit211turns the adjustment transistor229off in accordance with the control signal TXc, and at timing T25immediately after T24, turns the transfer transistor225off in accordance with the transfer signal TX2. At timing T26immediately after T25, the vertical scanning circuit211turns the transfer transistor227off in accordance with the transfer signal TG.

FIG.34is an example of a potential diagram at the time of reading out when illuminance is low according to the third embodiment of the present technique. In a case in which illuminance is low, no signal charge remains in ST1as illustrated in the figure when the first D phase level is read out. The potential diagram at the time of reading out the second D phase level is the same as that of the first D phase level.

FIG.35is a timing chart showing an example of an operation of reading out a row when illuminance is high according to the third embodiment of the present technique. The readout control in the figure is the same as the control illustrated inFIG.33.

FIGS.36A and36Bare examples of a potential diagram at the time of reading out when illuminance is high according to the third embodiment of the present technique.FIG.36Ais an example of the potential diagram at the time of reading out the first D phase level, andFIG.36Bis an example of the potential diagram at the time of reading out the second D phase level.

In addition, the first modified example and the second modified example of the first embodiment can be applied to the third embodiment.

As described above, according to the third embodiment of the present technique, since the transistor for adjusting the height of the potential barrier is provided, it is possible to solve shortage of the height of the potential barrier.

4. Example of Application to Mobile Object

The technique according to the present disclosure (the present technique) can be applied to various products. For example, the technique according to the present disclosure may be realized as a device mounted in any type of mobile objects such as automobiles, electric vehicles, hybrid electric vehicles, motorbikes, bicycles, personal mobility, airplanes, drones, ships, and robots.

FIG.37is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile object control system to which the technique according to the present disclosure can be applied.

A vehicle control system12000includes a plurality of electronic control units connected to each other via a communication network12001. In the example illustrated inFIG.37, the vehicle control system12000includes a drive system control unit12010, a body system control unit12020, a vehicle external information detection unit12030, a vehicle internal information detection unit12040, and an integrated control unit12050. In addition, as functional configurations of the integrated control unit12050, a microcomputer12051, a sound image output unit12052, and an in-vehicle network interface (I/F)12053are illustrated.

The drive system control unit12010controls operations of devices related to a drive system of a vehicle in accordance with various programs. For example, the drive system control unit12010functions as a control device of a driving force generation device for generating a driving force of, for example, an internal combustion engine or a driving motor of a vehicle, a driving force transmission mechanism for transmitting a driving force to wheels, a steering mechanism for adjusting a steering angle of a vehicle, a braking device that generates a braking force of a vehicle, and the like.

The body system control unit12020controls operations of various devices equipped in a vehicle body in accordance with various programs. For example, the body system control unit12020functions as a control device of, for example, a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device that substitutes for a key or signals of various switches may be input to the body system control unit12020. The body system control unit12020receives inputs of the radio waves or signals and controls a door lock device, a power window device, a lamp, and the like of a vehicle.

The vehicle external information detection unit12030detects information outside the vehicle in which the vehicle control system12000is mounted. For example, an imaging unit12031is connected to the vehicle external information detection unit12030. The vehicle external information detection unit12030causes the imaging unit12031to capture an image outside the vehicle and receives the captured image.

The vehicle external information detection unit12030may perform object detection processing or distance detection processing for peoples, cars, obstacles, signs, and letters on the road based on the received image.

The imaging unit12031is an optical sensor that receives light and outputs an electrical signal in accordance with an amount of received light. The imaging unit12031can also output the electrical signal as an image or as ranging information. In addition, the light received by the imaging unit12031may be visible light or invisible light such as infrared light.

The vehicle internal information detection unit12040detects information on the inside of the vehicle. For example, a driver state detection unit12041that detects a driver's state is connected to the vehicle internal information detection unit12040. The driver state detection unit12041includes, for example, a camera that captures an image of the driver, and the vehicle internal information detection unit12040may calculate a degree of fatigue or concentration of the driver or may determine whether or not the driver is dozing on the basis of detection information input from the driver state detection unit12041.

The microcomputer12051can calculate a control target value of the driving force generation device, the steering mechanism, or the braking device on the basis of the information inside and outside the vehicle acquired by the vehicle external information detection unit12030or the vehicle internal information detection unit12040, and output a control command to the drive system control unit12010. For example, the microcomputer12051can perform cooperative control for the purpose of realizing functions of an advanced driver assistance system (ADAS) including vehicle collision avoidance, impact mitigation, following traveling based on an inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like.

Further, by controlling the driving force generation device, the steering mechanism, the braking device, and the like on the basis of information regarding the vicinity of the vehicle acquired by the vehicle external information detection unit12030or the vehicle internal information detection unit12040, the microcomputer12051can perform cooperative control for the purpose of automated driving or the like in which autonomous travel is performed without depending on an operation of the driver.

In addition, the microcomputer12051can output a control command to the body system control unit12020on the basis of the information outside the vehicle acquired by the vehicle external information detection unit12030. For example, the microcomputer12051can perform cooperative control for the purpose of controlling headlamps in accordance with a position of a preceding vehicle or an oncoming vehicle detected by the vehicle external information detection unit12030and achieving antiglare by switching a high beam to a low beam, or the like.

The sound image output unit12052transmits an output signal of at least one of sound and an image to an output device capable of visually or audibly notifying an occupant of a vehicle or the outside of the vehicle of information. In the example shown inFIG.37, an audio speaker12061, a display unit12062, and an instrument panel12063are exemplified as output devices. The display unit12062may include, for example, at least one of an onboard display and a head-up display.

FIG.38is a diagram showing an example of an installation position of the imaging unit12031.

InFIG.38, imaging units12101,12102,12103,12104, and12105are provided as the imaging unit12031.

The imaging units12101,12102,12103,12104, and12105are provided at positions such as a front nose, side-view mirrors, a rear bumper, a back door, and an upper portion of a windshield in a vehicle interior of a vehicle12100, for example. The imaging unit12101provided on the front nose and the imaging unit12105provided in the upper portion of the windshield in the vehicle interior mainly acquire images in front of the vehicle12100. The imaging units12102and12103provided on the side mirrors mainly acquire images on a lateral side of the vehicle12100. The imaging unit12104provided on the rear bumper or the back door mainly acquires images behind the vehicle12100. The imaging unit12105provided in the upper portion of the windshield in the vehicle interior is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

Also,FIG.38shows an example of imaging ranges of the imaging units12101to12104. An imaging range12111indicates an imaging range of the imaging unit12101provided at the front nose, imaging ranges12112and12113respectively indicate imaging ranges of the imaging units12102and12103provided at the side mirrors, and an imaging range12114indicates an imaging range of the imaging unit12104provided at the rear bumper or the back door. For example, a bird's-eye view image of the vehicle12100as viewed from above can be obtained by superimposing image data captured by the imaging units12101to12104.

At least one of the imaging units12101to12104may have a function of acquiring distance information. For example, at least one of the imaging units12101to12104may be a stereo camera configured of a plurality of imaging elements or may be an imaging element having pixels for phase difference detection.

For example, by obtaining distances to each three-dimensional object within the imaging range12111to12114and changes of the distances over time (relative velocity with respect to the vehicle12100) on the basis of distance information obtained from the imaging units12101to12104, the microcomputer12051can extract, particularly, the closest three-dimensional object on a traveling path of the vehicle12100, which is a three-dimensional object traveling at a predetermined speed (for example, 0 km/h or higher) in the substantially same direction as the vehicle12100, as a preceding vehicle. Further, the microcomputer12051can set an inter-vehicle distance to be secured in advance from the preceding vehicle and can perform automated braking control (also including following stop control) or automated acceleration control (also including following start control). In this way, it is possible to perform cooperative control for the purpose of automated driving or the like in which autonomous travel is performed without depending on an operation of the driver.

For example, the microcomputer12051can classify and extract three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles on the basis of the distance information obtained from the imaging units12101to12104and use the three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer12051identifies obstacles in the vicinity of the vehicle12100into obstacles that can be visually recognized by the driver of the vehicle12100and obstacles that are difficult to be visually recognized. In addition, the microcomputer12051determines a collision risk indicating a degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and there is a possibility of collision, outputs a warning to the driver via the audio speaker12061or the display unit12062and performs forced deceleration or avoidance steering via the drive system control unit12010, so that it can perform driving assistance for collision avoidance.

At least one of the imaging units12101to12104may be an infrared camera that detects infrared light. For example, the microcomputer12051can recognize a pedestrian by determining whether or not a pedestrian is present in captured images of the imaging units12101to12104. Such recognition of a pedestrian is performed through, for example, a procedure of extracting feature points in the captured images of the imaging units12101to12104serving as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points indicating a contour of an object to determine whether or not the object is a pedestrian. When the microcomputer12051determines that a pedestrian is present in the captured images of the imaging units12101to12104and recognizes the pedestrian, the sound image output unit12052controls the display unit12062such that a square contour line for emphasis is superimposed on the recognized pedestrian and is displayed. In addition, the sound image output unit12052may control the display unit12062so that an icon or the like indicating a pedestrian is displayed at a desired position.

An example of the vehicle control system to which the technique according to the present disclosure may be applied has been described above. The technique according to the present disclosure may be applied to the imaging unit12031and the like among the configurations described above. Specifically, the imaging device100ofFIG.1can be applied to the imaging unit12031. By applying the technique according to the present disclosure to the imaging unit12031, PLS resistance is improved, a clearer captured image can be obtained, and thus it is possible to reduce a driver's fatigue.

Also, the above-described embodiments show examples for embodying the present technique, and matters in the embodiments and matters specifying the inventions in the claims have a corresponding relationship with each other. Similarly, the matters specifying the inventions in the claims and the matters in the embodiments of the present technique having the same name have a corresponding relationship with each other. However, the present technique is not limited to the embodiments and can be embodied by applying various modifications to the embodiments without departing from the gist thereof.

In addition, the effects described in the present specification are merely examples and are not intended as limiting, and other effects may be obtained.

The present technique can also have the following configurations.

(1) A solid-state imaging element including:a photoelectric conversion element;a front-stage charge holding region;a rear-stage charge holding region having a different capacity from the front-stage charge holding region;a front-stage transfer transistor that transfers a charge from the photoelectric conversion element to the front-stage charge holding region and the rear-stage charge holding region;a rear-stage transfer transistor that transfers the charge from the rear-stage charge holding region to a floating diffusion region;an intermediate transfer transistor that transfers a charge, which remains in the front-stage charge holding region after the charge has been transferred from the rear-stage charge holding region to the floating diffusion region, to the floating diffusion region via the front-stage charge holding region; anda light-shielding wall that prevents the charge from leaking from the photoelectric conversion element to the rear-stage charge holding region.

(2) The solid-state imaging element according to the above (1),wherein the front-stage charge holding region and the rear-stage charge holding region are impurity diffusion regions having the same polarity, anda predetermined impurity diffusion region having a different polarity from those of both the front-stage charge holding region and the rear-stage charge holding region is disposed between the front-stage charge holding region and the rear-stage charge holding region.

(3) The solid-state imaging element according to the above (1),wherein the front-stage charge holding region and the rear-stage charge holding region are formed in the same impurity diffusion region.

(4) The solid-state imaging element according to the above (3),wherein an impurity concentration in a region between the front-stage charge holding region and the rear-stage charge holding region in the impurity diffusion region is different from that around the region.

(5) The solid-state imaging element according to the above (3), further including an adjustment transistor that adjusts a height of the potential barrier between the front-stage charge holding region and the rear-stage charge holding region.

(6) The solid-state imaging element according to any one of the above (1) to (5), further includinga vertical scanning circuit that controls each of the front-stage transfer transistor, the rear-stage transfer transistor, and the intermediate transfer transistor to be turned either on or off,wherein the vertical scanning circuit turns the front-stage transfer transistor and the intermediate transfer transistor on while turning the rear-stage transfer transistor off to transfer the charge to the front-stage charge holding region and the rear-stage charge holding region, turns the rear-stage transfer transistor on while turning the front-stage transfer transistor and the intermediate transfer transistor off to transfer the charge from the rear-stage charge holding region to the floating diffusion region, and turns the intermediate transfer transistor and the rear-stage transfer transistor on to transfer the charge from the front-stage charge holding region to the floating diffusion region.

(7) The solid-state imaging element according to any one of the above (1) to (6), further includinga signal processing circuit that compares, between a first pixel signal corresponding to an amount of charge of the rear-stage charge holding region and a second pixel signal corresponding to an amount of charge of the front-stage charge holding region, the first pixel signal with a predetermined threshold and performs processing of selecting one of the first and second pixel signals on the basis of a comparison result.

(8) The solid-state imaging element according to any one of the above (1) to (7), wherein the photoelectric conversion element is formed on a wired front surface of both surfaces of a predetermined semiconductor substrate.

(9) The solid-state imaging element according to any one of the above (1) to (7), wherein the photoelectric conversion element is formed on a back surface of a wired front surface of both surfaces of a predetermined semiconductor substrate.

(10) The solid-state imaging element according to any one of the above (1) to (9),wherein the photoelectric conversion element includes first and second photoelectric conversion elements,the front-stage charge holding region includes first and second front-stage charge holding regions,the rear-stage charge holding region includes first and second rear-stage charge holding regions,the front-stage transfer transistor includes first and second front-stage transfer transistors,the intermediate transfer transistor includes first and second intermediate transfer transistors, andthe rear-stage transfer transistor includes first and second rear-stage transfer transistors.

(11) The solid-state imaging element according to any one of the above (1) to (10), further comprising:a charge discharge transistor that discharges the charge from the photoelectric conversion element,a reset transistor that initializes the floating diffusion region,an amplification transistor that amplifies the signal corresponding to the amount of charge transferred to the floating diffusion region, anda selection transistor that outputs the amplified signal as a pixel signal in accordance with a predetermined selection signal.

(12) An imaging device including:a photoelectric conversion element;a front-stage charge holding region;a rear-stage charge holding region having a different capacity from the front-stage charge holding region;a front-stage transfer transistor that transfers a charge from the photoelectric conversion element to the front-stage charge holding region and the rear-stage charge holding region;a rear-stage transfer transistor that transfers the charge from the rear-stage charge holding region to a floating diffusion region;an intermediate transfer transistor that transfers a charge, which remains in the front-stage charge holding region after the charge has been transferred from the rear-stage charge holding region to the floating diffusion region, to the floating diffusion region via the front-stage charge holding region;a light-shielding wall that prevents the charge from leaking from the photoelectric conversion element to the rear-stage charge holding region; anda signal processing circuit that processes a pixel signal in accordance with an amount of charge transferred to the floating diffusion region.

(13) A method for controlling a solid-state imaging element comprising:a front-stage transfer procedure of transferring a charge from a photoelectric conversion element to a front-stage charge holding region and a rear-stage charge holding region which have different capacities;a rear-stage transfer procedure of transferring the charge from the rear-stage charge holding region in which leakage of charge to the photoelectric conversion element is prevented by a light-shielding wall to a floating diffusion region; andan intermediate transfer procedure of transferring a charge, which remains in the front-stage charge holding region after the charge has been transferred from the rear-stage charge holding region to the floating diffusion region, to the floating diffusion region via the front-stage charge holding region.

REFERENCE SIGNS LIST

100Imaging device110Imaging lens120Recording unit130Imaging control unit200Solid-state imaging element211Vertical scanning circuit212Pixel array unit213Timing control circuit214DAC220Pixel221,241Charge discharge transistor222,242Photoelectric conversion element223,225,227,243,245,247Transfer transistor224,226,244,246Charge holding region228Floating diffusion region229Adjustment transistor230Transistor arrangement region231Reset transistor232Amplification transistor233Selection transistor240Pixel block250Load MOS circuit block251Load MOS transistor260Column signal processing circuit261ADC262Digital signal processing unit310n-type semiconductor substrate320p-type semiconductor substrate331,335,336n+layer332,333,334n layer337to339p+layer341to346Gate electrode411,412,416,417Light-shielding wall413Charge transfer channel414Wiring layer421Metal12031Imaging unit