Patent ID: 12245454

DETAILED DESCRIPTION

Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the accompanying drawings.

It will be understood that the terms “first,” “second,” “third,” etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an embodiment may be described as a “second” element in another embodiment.

The singular forms “a”, “an”, and “the” used herein are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that when a component, such as a film, a region, a layer, or an element, is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another component, it can be directly on, connected, coupled, or adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being “between” two components, it can be the only component between the two components, or one or more intervening components may also be present. It will also be understood that when a component is referred to as “covering” another component, it can be the only component covering the other component, or one or more intervening components may also be covering the other component. Other words use to describe the relationship between elements should be interpreted in a like fashion.

When an embodiment may be implemented differently, a certain process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.

When layers, regions, or components are “connected”, the layers, regions, or components may not only be “directly connected” but may also be “indirectly connected” via another layer, region, or component. For example, when layers, regions, or components are electrically connected, the layers, regions, or components may not only be directly electrically connected but may also be indirectly electrically connected via another layer, region, or component.

When two or more elements or values are described as being substantially the same as or about equal to each other, it is to be understood that the elements or values are identical to each other, indistinguishable from each other, or distinguishable from each other but functionally the same as each other as would be understood by a person having ordinary skill in the art. For example, when two or more elements or values are substantially the same as or about equal to each other but are not identical to each other, it is to be understood that the two or more elements or values are approximately the same as or equal to each other within a measurement error as would be understood by a person having ordinary skill in the art.

FIG.1is a schematic perspective view of a display apparatus1according to an embodiment.

Referring toFIG.1, the display apparatus1includes a first area OA (an opening area) and a second area DA (a display area). The second area DA at least partially surrounds the first area OA.

The display apparatus1may provide an image by using light emitted from a plurality of pixels disposed in the second area DA. The first area OA may be entirely surrounded by the second area DA. The first area OA may be an area in which a component20(refer toFIG.2) is disposed.

A third area MA (a middle area) may be disposed between the first area OA and the second area DA, and the second area DA may be surrounded by a fourth area PA (a peripheral area).

The third area MA and the fourth area PA may be non-display areas in which no pixels are disposed. The third area MA may be entirely surrounded by the second area DA, and the second area DA may be entirely surrounded by the fourth area PA.

Although the display apparatus1is described herein as being an organic light-emitting display apparatus, embodiments are not limited thereto. For example, according to embodiments, the display apparatus1may be a liquid crystal display apparatus, an inorganic light-emitting display apparatus, or a quantum dot light-emitting display apparatus.

AlthoughFIG.1shows one first area OA that is substantially circular, the number and shape of the first area OA is not limited thereto. For example, according to One or more embodiments, the number of first areas OA may be two or more, and each first area OA may be variously changed to have, for example, a circular shape, an oval shape, a polygonal shape such as a triangular or tetragonal shape, a star shape, a diamond shape, or an atypical shape, on the plane (or in a direction vertical to a main surface of a substrate).

The display apparatus1may be implemented in various electronic devices such as, for example, a mobile phone, a notebook computer, or a smartwatch.

FIG.2is a schematic cross-sectional view of the display apparatus1ofFIG.1taken along line II-II′, according to an embodiment.

Referring toFIG.2, the display apparatus1may include a display panel10, an input sensing layer40, an optical function layer50, and a window60.

The display panel10may display an image. The display panel10includes pixels disposed in the second area DA (the display area). The pixels may include a display element and a pixel circuit connected thereto. The display element may include, for example, an organic light-emitting diode. Alternatively, the display element may include an inorganic light-emitting diode, a quantum dot light-emitting diode, etc.

The input sensing layer40obtains coordinate information according to an external input such as, for example, a touch event. The input sensing layer40may include a sensing electrode or touch electrode, and trace lines connected to the sensing electrode or touch electrode. The input sensing layer40may be disposed on the display panel10. The input sensing layer40may sense an external input using, for example, a mutual-capacitance method and/or a self-capacitance method.

The input sensing layer40may be directly disposed on the display panel10. The input sensing layer40may be formed with the display panel10in the same process, or may be formed through a separate process and be combined with the display panel10via an adhesive layer such as, for example, an optical clear adhesive (OCA). For example, after manufacturing processes of the display panel10are completed, the input sensing layer40may be formed by consecutively implementing a direct deposition process and/or an extra patterning process on the display panel10. In this case, there may be no adhesive layer between the input sensing layer40and the display panel10.

AlthoughFIG.2shows the input sensing layer40disposed between the display panel10and the optical function layer50, embodiments are not limited thereto. For example, in an embodiment, the input sensing layer40may be disposed on the optical function layer50.

The optical function layer50may include a reflection-preventing layer. The reflection-preventing layer may decrease reflectance of incident light (external light) moving from the outside toward the display panel10through the window60.

The reflection-preventing layer may include a retarder and a polarizer. The retarder may be of a film type or a liquid crystal coating type, and may include a λ/2 retarder and/or a λ/4 retarder. The polarizer may be of a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include liquid crystals in a predetermined arrangement.

The retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or the protective film may be defined as a base layer of the reflection-preventing layer.

In an embodiment, the reflection-preventing layer may include a black matrix and color filters. The color filters may be disposed by taking into account a color of light emitted from each pixel of the display panel10.

In an embodiment, the reflection-preventing layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers from each other. First reflected light and second reflected light respectively reflected from the first reflective layer and the second reflective layer may experience destructive interference, and thus, reflectance of external light may decrease.

The optical function layer50may include a lens layer. The lens layer may increase light output efficiency of light emitted from the display panel10or may decrease color deviation. The lens layer may include a layer having a concave or convex lens shape and/or may include a plurality of layers having different refractive indexes from each other. The optical function layer50may include both of the above-described reflection-preventing layer and the lens layer, or may include one of the above-described reflection-preventing layer and the lens layer.

The display panel10, the input sensing layer40, and the optical function layer50may include an opening. In this regard,FIG.2shows the display panel10, the input sensing layer40, and the optical function layer50respectively including first to third openings10H,40H, and50H overlapping one another.

The first to third openings10H,40H, and50H may correspond to the first area OA (an opening area). For example, the first area OA may be formed by the first to third openings10H,40H, and50H. Sizes (or diameters) of the first to third openings10H,40H, and50H may be the same as or different from one another.

In an embodiment, at least one of the display panel10, the input sensing layer40and/or the optical function layer50may include no opening. For example, one or two components selected from among the display panel10, the input sensing layer40, and the optical function layer50may include no opening. Thus, the first area OA may be formed by some, but not all, of the first to third openings10H,40H, and50H.

The first area OA may be a component area (e.g. a sensor area, a camera area, a speaker area, etc.) in which a component20such as, for example, a sensor, a camera, a speaker, etc. for adding various functions to the display apparatus1is located.

As denoted by a solid line inFIG.2, the component20may be disposed in the first to third openings10H,40H, and50H. Alternatively, as denoted by a dashed line, the component20may be disposed below the display panel10, and thus, not within any of the first to third openings10H,40H, and50H. In this case, one or more from among the display panel10, the input sensing layer40, and the optical function layer50may include no opening. That is, in this case, at least one of the first to third openings10H,40H, and50H may not be included.

The component20may include an electronic element. For example, the component20may be an electronic element using light or sound.

For example, the electronic element may include a sensor, such as an infrared sensor, using light, a camera receiving light to capture an image, a sensor outputting and sensing light or sound to measure a distance or recognize a fingerprint, etc., a small lamp outputting light, a speaker outputting sound, etc. The electronic element using light may use light within various wavelength ranges, such as visible light, infrared light, ultraviolet light, etc. In some embodiments, the first area OA may be a transmission area capable of transmitting light and/or sound output from the component20to the outside or travelling from the outside toward the electronic element.

In an embodiment, when the display apparatus1is used to implement, for example, a smartwatch or a vehicle-use dashboard, the component20may be a member including clock hands, a needle indicating predetermined information (e.g. a vehicle speed, etc.), etc. When the display apparatus1includes the component20such as clock hands or a vehicle-use dashboard, the component20may be externally exposed through the window60, and the window60may include an opening corresponding to the first area OA. Alternatively, even when the display apparatus1includes the component20that does not include clock hands or a vehicle-use dashboard (e.g., when the component is a speaker), the window60may include an opening corresponding to the first area OA.

The component20may include a component (components) related to a function of the display panel10as described above, or may include a component such as an accessory increasing an aesthetic sense of the display panel10.

A layer including an adhesive layer such as, for example, an OCA, may be disposed between the window60and the optical function layer50.

FIG.3is a schematic plan view of the display panel10ofFIG.2, according to an embodiment.FIG.4is an equivalent circuit diagram schematically illustrating a pixel P of the display panel10, according to an embodiment.

Referring toFIG.3, the display panel10includes the first area OA (an opening area), the second area DA (a display area), the third area MA (a middle area), and the fourth area PA (a peripheral area). FIG. illustrates a substrate100of the display panel10. For example, the substrate100includes the first area OA, the second area DA, the third area MA, and the fourth area PA.

The display panel10includes a plurality of pixels P disposed in the second area DA. As shown inFIG.4, each pixel P includes a pixel circuit PC and an organic light-emitting diode OLED, which is a display element connected to the pixel circuit PC.

The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red, green, blue, or white light through the organic light-emitting diode OLED.

The second thin film transistor T2, which is a switching thin film transistor, may be connected to a scan line SL and a data line DL, and may deliver a data voltage input from the data line DL to the first thin film transistor T1according to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2and a driving voltage line PL, and may store a voltage corresponding to a difference between a voltage received from the second thin film transistor T2and a first power voltage ELVDD supplied to the driving voltage line PL.

The first thin film transistor T1, which is a driving thin film transistor, may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL through the organic light-emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The driving current may allow the organic light-emitting diode OLED to emit light having a predetermined brightness. An opposite electrode (e.g. a cathode) of the organic light-emitting diode OLED may receive a second power voltage ELVSS.

Although the pixel circuit PC illustrated inFIG.4includes two thin film transistors and one storage capacitor, embodiments are not limited thereto. For example, the number of thin film transistors and the number of storage capacitors may variously change according to design of the pixel circuit PC.

Referring again toFIG.3, the third area MA may surround the first area OA. The third area MA is an area in which a display element such as an organic light-emitting diode emitting light is not disposed, and signal lines for providing signals to the pixels P disposed around the first area OA may pass the third area MA.

A scan driver1100providing a scan signal to each pixel P, a data driver1200providing a data signal to each pixel P, a main power line for providing first and second power voltages, etc. may be disposed in the fourth area PA (a peripheral area). Although the data driver1200is disposed adjacent to a lateral side of the substrate100inFIG.3, embodiments are not limited thereto. For example, in an embodiment, the data driver1200may be disposed on a flexible printed circuit board (FPCB) electrically connected to a pad disposed on a side of the display panel10.

FIG.5is a plan view of a portion of a display panel according to an embodiment, and illustrates signal lines in the third area MA (a middle area).

Referring toFIG.5, the pixels P are disposed in the second area DA, and the third area MA (a middle area) is disposed between the first area OA and the second area DA. The pixels P adjacent to the first area OA may be mutually spaced apart with respect to the first area OA on the plane. The pixels P may be spaced apart vertically with respect to the first area OA or may be spaced apart horizontally with respect to the first area OA.

From among signal lines for supplying signals to the pixels P, signal lines adjacent to the first area OA may detour around the first area OA. Some data lines DL from among data lines passing the second area DA may extend in the y direction to provide data signals to the pixels P respectively disposed above and below the first area OA (with the first area OA disposed therebetween), and may take a detour along the edge of the first area OA over the third area MA.

Some scan lines SL from among scan lines passing the second area DA may extend in the x direction to provide scan signals to the pixels P respectively disposed to the left and right of the first area OA (with the first area OA disposed therebetween), and may take a detour along the edge of the first area OA over the third area MA.

FIG.6is a plan view of a portion of a display panel according to an embodiment, and illustrates a groove G in the third area MA.

Referring toFIG.6, one or more grooves G may be disposed between the first area OA and the second area DA. AlthoughFIG.6shows three grooves G disposed between the first area OA and the second area DA, embodiments are not limited thereto. For example, one, two, or four or more grooves may be disposed in the third area MA according to embodiments.

On the plane, the grooves G may be disposed in the third area MA (a middle area) and may have a ring shape entirely surrounding the first area OA. On the plane, a radius of each of the grooves G to a center C of the first area OA may be greater than a radius of the first area OA. The grooves G may be spaced apart from one another.

Referring toFIGS.5and6, the grooves G may be disposed between the first area OA and the detour portions of the data line DL and/or the scan line SL taking a detour along the edge of the first area OA, and the grooves G may be more adjacent to the first area OA than detour portions of the data line DL and/or the scan line SL taking a detour along the edge of the first area OA.

FIG.7is a cross-sectional view of the display panel10ofFIG.6taken along line VII-VII′, according to an embodiment.

Referring toFIG.7, the pixel circuit PC and the organic light-emitting diode OLED electrically connected to the pixel circuit PC may be disposed in the second area DA (a display area).

The pixel circuit PC may be disposed on the substrate100, and the organic light-emitting diode OLED may be disposed on the pixel circuit PC. The pixel circuit PC includes a thin film transistor TFT and the storage capacitor Cst disposed on the substrate100, and a pixel electrode221is electrically connected thereto.

The substrate100may include, for example, polymer resin or glass. In an embodiment, the substrate100may include polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate and/or cellulose acetate propionate, and may have a flexible nature.

In an embodiment, the substrate100may include glass including primarily SiO2or resin such as reinforced plastics, and may have a rigid nature.

The substrate100may have a stack structure of a layer including the above-described polymer resin and a barrier layer located on the above-described polymer resin layer. For example, the substrate100may have a structure in which a first polymer resin layer, a first barrier layer, a second polymer resin layer, and a second barrier layer are stacked. The substrate100including polymer resin may increase flexibility. The barrier layer may include, for example, silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOx), etc.

A buffer layer201, which may prevent permeation of impurities into a semiconductor layer Act of the thin film transistor TFT, may be disposed on the substrate100. The buffer layer201may include an inorganic insulating material such as, for example, silicon nitride, silicon oxynitride, and silicon oxide, and may have a single-layer or multilayer structure including the above-described inorganic insulating material.

The pixel circuit PC may be disposed on the buffer layer201. The pixel circuit PC includes the thin film transistor TFT and the storage capacitor Cst. The thin film transistor TFT may include the semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. The thin film transistor TFT shown inFIG.7may be a driving thin film transistor, as described above with reference toFIG.4. AlthoughFIG.7illustrates a top-gate type thin film transistor in which the gate electrode GE is disposed on the semiconductor layer Act with a gate insulating layer203disposed therebetween, embodiments are not limited thereto. For example, the thin film transistor TFT may be a bottom-gate type thin film transistor in an embodiment.

The semiconductor layer Act may include, for example, polysilicon. Alternatively, the semiconductor layer Act may include, for example, amorphous silicon, may include an oxide semiconductor, or may include an organic semiconductor. The gate electrode GE may include, for example, a low-resistance metal material. The gate electrode GE may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer or multilayer structure including the above-described material.

The gate insulating layer203disposed between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer203may have a single-layer or multilayer structure including the above-described material.

The source electrode SE and the drain electrode DE may include a highly conductive material. The source electrode SE and the drain electrode DE may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer or single-layer structure including the above-described material. In an embodiment, the source electrode SE and the drain electrode DE may include multiple layers of Ti/Al/Ti.

The storage capacitor Cst includes a lower electrode CE1and an upper electrode CE2overlapping each other with a first interlayer insulating layer205disposed therebetween. In an embodiment, the storage capacitor Cst may overlap the thin film transistor TFT. In this regard, in an embodiment, the gate electrode GE of the thin film transistor TFT may be the lower electrode CE1of the storage capacitor Cst. In an embodiment, the storage capacitor Cst may not overlap the thin film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer207.

The first and second interlayer insulating layers205and207may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first and second interlayer insulating layers205and207may have a single-layer or multilayer structure including the above-described material.

The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by a planarization insulating layer209. The planarization insulating layer209may include a side having a substantially flat upper surface. The planarization insulating layer209may include an organic insulating material such as a general-purpose polymer such as, for example, poly(methyl methacrylate) (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof. In an embodiment, the planarization insulating layer209may include PI. Alternatively, the planarization insulating layer209may include an inorganic insulating material, or may include inorganic and organic insulating materials.

The pixel electrode221may be disposed on the planarization insulating layer209. The pixel electrode221may include a conductive oxide such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In an embodiment, the pixel electrode221may include a reflective film including, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In an embodiment, the pixel electrode221may further include a film disposed on and/or under the above-described reflective film, the film including ITO, IZO, ZnO, or In2O3.

A pixel-defining film211may be disposed on the pixel electrode221. The pixel-defining film211may include an opening that exposes an upper surface of the pixel electrode221, and may cover the edge of the pixel electrode221. The pixel-defining film211may include an organic insulating material. Alternatively, the pixel-defining film211may include an inorganic insulating material such as, for example, silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxide (SiOx). Alternatively, the pixel-defining film211may include an organic insulating material and an inorganic insulating material.

An intermediate layer222includes an emission layer222b. The intermediate layer222may further include a first function layer222adisposed under the emission layer222b, and/or a second function layer222cdisposed on the emission layer222b. The emission layer222bmay include a polymer or low-molecular organic material emitting light having a predetermined color.

The first function layer222amay have a single-layer or multilayer structure. For example, when the first function layer222aincludes a polymer material, the first function layer222amay be a hole transport layer (HTL) having a single-layer structure and may include poly-(3,4)-ethylene-dihydroxy thiophene (PEDOT) or polyaniline (PANI). When the first function layer222aincludes a low-molecular material, the first function layer222amay include a hole injection layer (HIL) and an HTL.

The second function layer222cmay be omitted in embodiments. In an embodiment, when the first function layer222aand the emission layer222binclude a polymer material, the second function layer222cmay be provided. The second function layer222cmay have a single-layer or multilayer structure. The second function layer222cmay include an electron transport layer (ETL) and/or an electron injection layer (EIL).

The emission layer222bof the intermediate layer222may be disposed for each pixel in the second area DA. The emission layer222bmay contact the upper surface of the pixel electrode221exposed via the opening in the pixel-defining film211. Unlike the emission layer222b, the first and second function layers222aand222cof the intermediate layer222may be present not only in the second area DA (a display area) ofFIG.7, but also in the third area MA (refer toFIG.12). For example, in an embodiment, the emission layer222bis disposed in the second area DA (a display area) and is not disposed in the third area MA, and the first and second function layers222aand222care disposed in the second area DA (a display area) and the third area MA.

An opposite electrode223may include a conductive material having a low work function. For example, the opposite electrode223may include a (semi)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), an alloy thereof, etc. Alternatively, the opposite electrode223may further include a layer, such as ITO, IZO, ZnO, or In2O3, disposed on the (semi)transparent layer including the above-described material. The opposite electrode223may be disposed over not only the second area DA, but also the third area MA (a middle area). The intermediate layer222and the opposite electrode223may be formed, for example, by thermal deposition.

A capping layer230may be disposed on the opposite electrode223. The capping layer230may include, for example, lithium fluoride (LiF), and may be formed, for example, by thermal deposition. Alternatively, the capping layer230may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. Alternatively, the capping layer230may include an organic insulating material. Alternatively, the capping layer230may be omitted.

A spacer213may be disposed on the pixel-defining film211. The spacer213may include an organic insulating material such as, for example, PI. Alternatively, the spacer213may include an inorganic insulating material such as, for example, silicon nitride or silicon oxide, or may include an organic insulating material and an inorganic insulating material.

The spacer213may include a different material than the pixel-defining film211. Alternatively, the spacer213may include the same material as the pixel-defining film211, and in this case, the pixel-defining film211and the spacer213may be formed together during a mask process using, for example, a halftone mask. In an embodiment, the pixel-defining film211and the spacer213may include PI.

The organic light-emitting diode OLED is covered by a thin film encapsulation layer300. For example, the thin film encapsulation layer300is disposed on the organic light-emitting diode OLED. The thin film encapsulation layer300may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In an embodiment, the thin film encapsulation layer300includes first and second inorganic encapsulation layers310and330, as well as an organic encapsulation layer320disposed between the first and second inorganic encapsulation layers310and330, as shown inFIG.7. The number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order thereof may be changed according to embodiments.

The first and second inorganic encapsulation layers310and330may include one or more inorganic insulating materials such as, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride, and may be formed by, for example, chemical vapor deposition (CVD).

The organic encapsulation layer320may include, for example, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane (HMDSO), acrylic resin (e.g. PMMA, poly(acrylic acid), etc.), or any combination thereof.

The input sensing layer40may be disposed on the display panel10. In an embodiment, the input sensing layer40is directly formed on the display panel10such that it contacts the thin film encapsulation layer300, as shown inFIG.7.

FIG.8is a schematic plan view of the input sensing layer40, according to an embodiment.FIG.8shows a portion of the input sensing layer40corresponding to the second area DA as shown inFIG.7.

Referring toFIG.8, the input sensing layer40includes a first sensing electrode SP1and a second sensing electrode SP2located in the second area DA. In an embodiment, a plurality of first sensing electrodes SP1are arranged and connected to each other in the x direction, and a plurality of second sensing electrodes SP2are arranged and connected to one another in the y direction across the first sensing electrodes SP1. The first sensing electrodes SP1and the second sensing electrodes SP2may vertically cross each other.

Corners of the first sensing electrodes SP1and the second sensing electrodes SP2may be adjacent to each other. Neighboring first sensing electrodes SP1may be electrically connected to each other in the x direction via a first connection electrode CP1, and neighboring second sensing electrodes SP2may be electrically connected to each other in the y direction via a second connection electrode CP2.

FIGS.9A and9Bare respective plan views of a first conductive layer410and a second conductive layer420of an input sensing layer (e.g., the input sensing layer40ofFIG.8), according to an embodiment.FIG.9Cis a cross-sectional view of the input sensing layer40ofFIGS.9A and9Btaken along line VIII-VIII′ ofFIG.8, according to an embodiment.

Referring toFIGS.9A and9B, the first sensing electrode SP1and the second sensing electrode SP2may be disposed on the same layer as each other. For example, the first conductive layer410may include the first connection electrode CP1(refer toFIG.9A), and the second conductive layer420may include the first sensing electrode SP1, the second sensing electrode SP2, and the second connection electrode CP2(refer toFIG.9B).

The second sensing electrodes SP2may be connected to each other by the second connection electrode CP2, which is disposed on the same layer. For example, the second sensing electrodes SP2and the second connection electrode CP2may be disposed on the second conductive layer420(refer toFIG.9B). The first sensing electrodes SP1may be disposed in the x direction, and may be connected to each other by the first connection electrode CP1, which is disposed on a different layer. For example, the first sensing electrodes SP1may be disposed on the second conductive layer420(refer toFIG.9B), and the first connection electrode CP1may be disposed on the first conductive layer410(refer toFIG.9A).

Referring toFIG.9C, a middle insulating layer403may be disposed between the first conductive layer410and the second conductive layer420. The first sensing electrodes SP1disposed in the second conductive layer420may be connected to the first connection electrode CP1disposed in the first conductive layer410via a contact hole CNT in the middle insulating layer403.

The second conductive layer420may be covered by an upper insulating layer405, and a lower insulating layer401may be disposed under the first conductive layer410. The lower and middle insulating layers401and403may be inorganic insulating layers such as, for example, silicon nitride, or organic insulating layers.

The upper insulating layer405may be an organic insulating layer or an inorganic insulating layer. The first and second conductive layers410and420may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum (Mo), mendelevium (Mb), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and an alloy thereof. The transparent conductive layer may include transparent conductive oxide such as, for example, ITO, IZO, ZnO, indium tin zinc oxide (ITZO), etc. In addition, the transparent conductive layer may include a conductive polymer such as, for example, PEDOT, metal nanowire, carbon nanotube, graphene, etc.

In the embodiment ofFIG.9C, the lower insulating layer401is disposed between the thin film encapsulation layer300and the first conductive layer410. In an embodiment, the lower insulating layer401may be omitted, and the first conductive layer410may be directly disposed on the thin film encapsulation layer300.

FIGS.10A and10Bare respective plan views of the first conductive layer410and the second conductive layer420of an input sensing layer (e.g., the input sensing layer40ofFIG.8), according to an embodiment.FIG.10Cis a cross-sectional view of the input sensing layer40ofFIGS.10A and10Btaken along line VIII-VIII′ ofFIG.8, according to an embodiment.

Referring toFIGS.10A and10B, the first conductive layer410includes the first sensing electrodes SP1and the first connection electrode CP1connecting the first sensing electrodes SP1, and the second conductive layer420includes the second sensing electrodes SP2and the second connection electrode CP2connecting the second sensing electrodes SP2. The first conductive layer410may further include a second auxiliary sensing electrode S-SP2, which is connected to the second sensing electrode SP2, and the second conductive layer420may further include a first auxiliary sensing electrode S-SP1, which is connected to the first sensing electrode SP1.

Referring toFIG.10A, each of the first sensing electrodes SP1may have a mesh structure including a plurality of holes H. A hole H may overlap an emission area P-E of a pixel. The second sensing electrode SP2, the first auxiliary sensing electrode S-SP1, and the second auxiliary sensing electrode S-SP2may also have a mesh structure including a plurality of holes corresponding to the emission area P-E of the pixel, as shown inFIG.10A.

Referring toFIG.10C, the first auxiliary sensing electrode S-SP1may be connected to the first sensing electrode SP1via the contact hole CNT in the middle insulating layer403. Such a structure may decrease resistance of the first sensing electrode SP1. Similarly, the second sensing electrode SP2may be connected to the second auxiliary sensing electrode S-SP2via the contact hole CNT in the middle insulating layer403.

The lower and middle insulating layers401and403may be inorganic insulating layers such as, for example, silicon nitride, or organic insulating layers, and the upper insulating layer405may be an organic insulating layer or an inorganic insulating layer.

The first and second conductive layers410and420may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum (Mo), mendelevium (Mb), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and an alloy thereof, and may have a single-layer or multilayer structure including the above-described metal. For example, the first and second conductive layers410and420may be metal layers including three sub-layers of Ti/Al/Ti. The transparent conductive layer may include, for example, a transparent conductive oxide, a conductive polymer, a metal nanowire, graphene, etc., as described above.

FIGS.11A and11Bare respective plan views of the first conductive layer410and the second conductive layer420of an input sensing layer (e.g., the input sensing layer40ofFIG.8), according to an embodiment.FIG.11Cis a cross-sectional view of the input sensing layer40ofFIGS.11A and11Btaken along line VIII-VIII′ ofFIG.8, according to an embodiment.

Referring toFIGS.11A and11B, the first conductive layer410includes the first sensing electrodes SP1and the first connection electrode CP1connecting the first sensing electrodes SP1, and the second conductive layer420includes the second sensing electrodes SP2and the second connection electrode CP2connecting the second sensing electrodes SP2.

Referring toFIG.11C, the middle insulating layer403may be disposed between the first conductive layer410and the second conductive layer420. The middle insulating layer403does not include a contact hole, and the first and second sensing electrodes SP1and SP2may be electrically insulated from each other with the middle insulating layer403disposed therebetween.

The second conductive layer420may be covered by the upper insulating layer405. The lower insulating layer401including an inorganic material or an organic material may be further included under the first conductive layer410. The middle and upper insulating layers403and405may be organic insulating layers or inorganic insulating layers.

The first and second conductive layers410and420may include a metal layer or a transparent conductive layer. The metal layer may include, for example, molybdenum (Mo), mendelevium (Mb), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as, for example, ITO, IZO, ZnO, ITZO, etc. In addition, the transparent conductive layer may include a conductive polymer such as, for example, PEDOT, metal nanowire, graphene, etc.

FIG.12is a cross-sectional view of a display apparatus according to an embodiment, taken along line XII-XII′ ofFIG.6.FIG.13is a cross-sectional view of portion XIII ofFIG.12, according to an embodiment.FIG.14is a cross-sectional view of a display apparatus according to an embodiment, and illustrates portion XIV ofFIG.12.FIGS.15and16are cross-sectional views of display apparatuses according to embodiments, and illustrate a periphery of a cover layer730.FIG.17is a cross-sectional view of a display apparatus, according to an embodiment.

Referring toFIG.12, the display panel10may include the first opening10H corresponding to the first area OA.

The second area DA includes the pixel circuit PC disposed on the substrate100, the pixel electrode221connected to the pixel circuit PC, and the intermediate layer222and the opposite electrode223sequentially stacked on the pixel electrode221.

The substrate100may include multiple layers. For example, the substrate100may include a first base layer101, a first barrier layer102, a second base layer103, and a second barrier layer104, which are sequentially stacked.

Each of the first and second base layers101and103may include polymer resin. For example, the first and second base layers101and103may include polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate and/or cellulose acetate propionate. The above-described polymer resin may be transparent.

Each of the first and second barrier layers102and104, which is a barrier layer that may prevent permeation of an external foreign material, may have a single-layer or multilayer structure including an inorganic material such as, for example, silicon nitride (SiNx) and/or silicon oxide (SiOx).

The pixel circuit PC is on the substrate100and includes, for example, a thin film transistor and a storage capacitor. An organic light-emitting diode including the pixel electrode221, an emission layer of the intermediate layer222, and the opposite electrode223emits predetermined light and is covered by the thin film encapsulation layer300. Components disposed in the second area DA are the same as those described above with reference toFIG.7, and for convenience of description, a further description thereof is omitted.

Referring toFIG.12, the third area MA may include a first sub-middle area SMA1relatively adjacent to the second area DA, and a second sub-middle area SMA2relatively adjacent to the first area OA or the first opening10H. For example, the first sub-middle area SMA1is closer to the second area DA than it is to the first area OA, and the second sub-middle area SMA2is closer to the first area OA than it is to the second area DA.

The first sub-middle area SMA1may be an area in which signal lines such as, for example, the data lines DL described above with reference toFIG.5, pass through. The data lines DL shown inFIG.12may correspond to data lines detouring around the first area OA. The first sub-middle area SMA1may be a line area or a detour area in which the data lines DL pass through. In an embodiment, a width of the first sub-middle area SMA1may be less than or greater than that of the second sub-middle area SMA2. In an embodiment, the width of the first sub-middle area SMA1may be substantially the same as that of the second sub-middle area SMA2.

As shown inFIG.12, the data lines DL may be alternately disposed with an insulating layer disposed therebetween. For example, a first group of data lines DL may be disposed on the first interlayer insulating layer205, the second interlayer insulating layer207may be disposed on top of the first group of data lines DL, and a second group of data lines DL may be disposed on top of the second interlayer insulating layer207. Data lines DL of the first and second groups may be disposed in an alternating fashion. When neighboring data lines DL are respectively disposed above and below with the insulating layer (e.g. the second interlayer insulating layer207) disposed therebetween, a gap (pitch) between the neighboring data lines DL may decrease, and a width of the third area MA may decrease.

In an embodiment, the data lines DL may be disposed on the same insulating layer (e.g. the second interlayer insulating layer207). AlthoughFIG.12shows the data lines DL disposed in the first sub-middle area SMA1, scan lines detouring the first area OA, as described above with reference toFIG.5, may also be disposed in the first sub-middle area SMA1.

A shield layer80may be disposed on the data lines DL and/or the scan lines located in the first sub-middle area SMA1. The shield layer80may overlap the data lines DL and/or the scan lines, thus preventing the data lines DL and/or the scan lines from being visible to the user. In an embodiment, the shield layer80may include metal.

The second sub-middle area SMA2is a groove area including a plurality of grooves G. AlthoughFIG.12shows five grooves G disposed in the second sub-middle area SMA2, embodiments are not limited thereto, and the number of grooves G may variously change.

Each of the grooves G may be in a multilayer film including a first layer and a second layer including different from materials from each other. For example, in an embodiment, the groove G may be disposed in sub-layers of the substrate100, as shown inFIG.12.

Referring toFIGS.12and13, the groove G may be formed by removing a portion of the second barrier layer104and a portion of the second base layer103. A hole H2formed through the second barrier layer104and a recess R1formed in the second base layer103may be spatially connected to form the groove G. The second base layer103may correspond to the first layer of the multilayer film described above, and the second barrier layer104may correspond to the second layer of the multilayer film.

During a process of forming the groove G, a portion of the buffer layer201disposed on the second barrier layer104may be removed together with the second barrier layer104to form the hole H2. Although the buffer layer201and the second barrier layer104are described herein as separate components, in an embodiment, the buffer layer201disposed on the substrate100may be a sub-layer of the second barrier layer104having a multilayer structure.

A width of a portion of the groove G passing the second barrier layer104, for example, the hole H2, may be less than that of a portion of the groove G passing the second base layer103, for example, the recess R1. A width W2(or a diameter) of the hole H2may be less than a width W1(or a diameter) of the recess R1, and the groove G may have an undercut cross-section.

A side surface of the second barrier layer104defining the hole H2may protrude toward a center of the groove G more than a side surface of the second base layer103defining the recess R1. For example, as shown inFIG.13, a distance from the side surface of the second barrier layer104adjacent to the groove G to the center of the groove G may be less than a distance from the side surface of the second base layer103adjacent to the groove G to the center of the groove G. Portions of the second barrier layer104protruding toward the center of the groove G may constitute a pair of eaves (or a pair of protruding tips or tips PT). Along with the second barrier layer104, the buffer layer201may also constitute the pair of eaves.

The groove G may be formed before a process of forming the intermediate layer222. A portion222′ of the intermediate layer222, for example, the first function layer222aand/or the second function layer222cextending to the third area MA, is discontinuous around the groove G. For example, the groove G may create a break (or a disconnection) in the intermediate layer222. Similarly, the opposite electrode223and the capping layer230including, for example, LiF, may be discontinuous around the groove G. For example, the groove G may create a break (or a disconnection) in the opposite electrode223and the capping layer230. A length l of each of the pair of tips PT may be less than about 2.0 μm. For example, in an embodiment, the length l may be about 1.0 μm to about 1.8 μm.

AlthoughFIGS.12and13show a bottom surface of the groove G located on an imaginary plane between a bottom surface and an upper surface of the second base layer103, embodiments are not limited thereto. For example, in an embodiment, the bottom surface of the groove G may be located on the same plane as the bottom surface of the second base layer103. For example, during an etching process for forming the groove G, a depth dp of the recess R1may be substantially the same as a thickness t of the second base layer103, and in this case, the bottom surface of the groove G may lie on the same plane as the bottom surface of the second base layer103. The depth dp of the recess R1may be about 2.0 μm or greater. When the depth dp of the recess R1is substantially the same as the thickness t of the second base layer103, the recess R1may form a hole through the second base layer103.

As shown inFIG.12, the thin film encapsulation layer300covering display elements in the second area DA (a display area) may extend to cover the third area MA. For example, the first and second inorganic encapsulation layers310and330may extend to the third area MA.

The first and second inorganic encapsulation layers310and330may be formed, for example, by CVD, and may have relatively good step coverage compared to the portion222′ of the intermediate layer222or the opposite electrode223. Accordingly, the first and second inorganic encapsulation layers310and330may each be continuous rather than discontinuous around the groove G.

The first inorganic encapsulation layer310may cover an inner surface of the groove G. The first and second inorganic encapsulation layers310and330may have different thicknesses from each other. For example, the first inorganic encapsulation layer310may have a thickness of about 1 μm, and the second inorganic encapsulation layer330may have a smaller thickness of about 0.7 μm. Alternatively, a thickness of the first inorganic encapsulation layer310and that of the second inorganic encapsulation layer330may be substantially the same as each other, or a thickness of the first inorganic encapsulation layer310may be greater than that of the second inorganic encapsulation layer330.

AlthoughFIGS.12and13show a structure in which the capping layer230including LiF is discontinuous around the groove G, embodiments are not limited thereto. For example, in an embodiment, when the capping layer230includes an inorganic material, like the first inorganic encapsulation layer310, the capping layer230may continuously cover an inner surface of the groove G instead of being discontinuous around the groove G. That is, in this case, the groove G does not create a break (or a disconnection) in the capping layer230.

As shown inFIG.12, the organic encapsulation layer320may cover the second area DA and may have an end320E disposed on a side of a first partition wall510. The end320E of the organic encapsulation layer320may contact the first partition wall510.

The organic encapsulation layer320may be formed, for example, by spreading and curing monomers. The flow of monomers may be controlled by the first partition wall510, and a thickness of the organic encapsulation layer320may be controlled by the first partition wall510.

The organic encapsulation layer320, for example, the end320E of the organic encapsulation layer320, may be spaced apart from the first area OA. As a result, external moisture permeating through the first opening10H may be prevented from travelling to an organic light-emitting diode of the second area DA (a display area) via the organic encapsulation layer320.

The first partition wall510may include a plurality of layers (e.g., a plurality of insulating layers). In this regard,FIG.12shows the first partition wall510having a stack structure of layers including the same material as the gate insulating layer203, the first interlayer insulating layer205, and the second interlayer insulating layer207, and layers including the same material as the planarization insulating layer209and the pixel-defining film211. However, embodiments are not limited thereto. For example, in an embodiment, the number of layers constituting the first partition wall510may be greater or less than the number of layers shown inFIG.12.

An organic material layer320A is adjacent to the first area OA, and is spaced apart from the organic encapsulation layer320by a predetermined distance. The organic material layer320A may be formed during the same process as the organic encapsulation layer320and may include the same material as the organic encapsulation layer320. As the flow of monomers is adjusted by the first partition wall510during a formation process of the organic encapsulation layer320, the organic material layer320A may be adjusted by a second partition wall520, and an end320AE of the organic material layer320A may be disposed on a side of the second partition wall520.

As shown inFIG.12, the first inorganic encapsulation layer310and the second inorganic encapsulation layer330may be located over the third area MA while contacting each other.

When a contact area between the first inorganic encapsulation layer310and the second inorganic encapsulation layer330is about equal to or greater than a certain value, the first and second inorganic encapsulation layers310and330or a surrounding layer, for example, a planarization layer720described below, may be lifted due to stresses of the first inorganic encapsulation layer310and the second inorganic encapsulation layer330. However, the contact area between the first and second inorganic encapsulation layers310and330may be decreased by arranging the organic material layer320A as shown inFIG.12, thus, preventing or reducing such lifting.

When the organic material layer320A spaced apart from the organic encapsulation layer320is disposed, the first and second inorganic encapsulation layers310and330may contact each other between the end320E of the organic encapsulation layer320and the end320AE of the organic material layer320A.

The planarization layer720may be disposed in the third area MA.

The planarization layer720may be an organic insulating layer. The planarization layer720may include a polymer-based material. The planarization layer720may include, for example, silicone-based resin, acrylic resin, epoxy-based resin, PI, polyethylene, etc. The above-described polymer-based material may be transparent.

In an embodiment, the planarization layer720may include a different material from the organic encapsulation layer320. For example, in an embodiment, the organic encapsulation layer320may include silicone-based resin, and the planarization layer720may include acrylic resin. In an embodiment, the organic encapsulation layer320and the planarization layer720may include the same material as each other.

The planarization layer720may cover at least one groove G in the third area MA. The planarization layer720may increase flatness of the display panel10around the first area OA by covering at least an area that is not covered by the organic encapsulation layer320in the third area MA. Accordingly, problems such as separation or detachment of the input sensing layer40(ofFIG.2) and/or the optical function layer50(ofFIG.2) disposed on the display panel10may be prevented or reduced. A portion of the planarization layer720may overlap the organic encapsulation layer320. An end of the planarization layer720, for example, a first end720E1adjacent to the second area DA, may be disposed on the organic encapsulation layer320. For example, the first end720E1of the planarization layer may overlap the thin film encapsulation layer300.

The planarization layer720may be formed over the third area MA through, for example, exposure and development processes. During some of formation processes (e.g., a washing process) of the planarization layer720, when an external foreign material, for example, moisture, travels in a side direction of the display panel10(e.g. a direction parallel to the xy plane), an organic light-emitting diode of the second area DA may be damaged. However, according to embodiments, the above-described problem caused by permeation of moisture during and after the formation processes of the planarization layer720and/or lifting of a surrounding film may be prevented or reduced by arranging insulating layers, for example, a first insulating layer710and a second insulating layer740, under and on the planarization layer720, respectively.

The first insulating layer710may be disposed directly under the planarization layer720. For example, the first insulating layer710may contact the planarization layer720, and no other layers may be present between the first insulating layer710and the planarization layer720. The first insulating layer710may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The first insulating layer710may directly contact the thin film encapsulation layer300. For example, the first insulating layer710may directly contact an upper surface of the second inorganic encapsulation layer330.

The first insulating layer710may include the same material as the second inorganic encapsulation layer330or may include a different material from the second inorganic encapsulation layer330. Even though the first insulating layer710includes the same material as the second inorganic encapsulation layer330, for example, silicon nitride, a detailed composition ratio (e.g. the content ratio of silicon and nitrogen) may be different, and there may be an interface between the first insulating layer710and the second inorganic encapsulation layer330. A thickness of the first insulating layer710may be less than that of the second inorganic encapsulation layer330. Alternatively, the thickness of the first insulating layer710may be substantially the same as or greater than that of the second inorganic encapsulation layer330.

The second insulating layer740may be disposed on the planarization layer720, for example, directly on the planarization layer720. The second insulating layer740may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The first insulating layer710and the second insulating layer740may include the same material as each other or may include different materials from each other. A thickness of the second insulating layer740may be greater than that of the first insulating layer710. Alternatively, the thickness of the second insulating layer740may be less than or substantially the same as that of the first insulating layer710.

The planarization layer720may have a step with respect to a lower layer thereof. Referring toFIG.14, the first end720E1of the planarization layer720may have a step with respect to a lower layer thereof, for example, an upper surface of the first insulating layer710. During an operation of manufacturing the display panel10and/or an operation of using the display panel10after manufacturing, to prevent the first end720E1of the planarization layer720from being separated from a lower layer thereof or being lifted due to the above step, the first end720E1of the planarization layer720may be covered by the second insulating layer740and/or the cover layer730.

In an embodiment, the cover layer730may entirely overlap the first end720E1of the planarization layer720, and may partially overlap the first insulating layer710and the second insulating layer740, as shown inFIG.14.

The cover layer730may include a different material from the first and second insulating layers710and740. For example, the cover layer730may include the same material as the first conductive layer410and/or the second conductive layer420of the input sensing layer40located in the second area DA. In an embodiment, the cover layer730may include a conductive material such as metal.

A third width W3of the cover layer730may be tens of μm to hundreds of μm. For example, the third width W3of the cover layer730may be about 50 μm to about 500 μm, about 50 μm to about 400 μm, about 50 μm to about 300 μm, about 50 μm to about 200 μm, about 50 μm to about 100 μm, or about 60 μm to about 100 μm.

The cover layer730may be disposed on the planarization layer720. For example, the cover layer730may be disposed directly on the second insulating layer740covering the planarization layer720.

To prevent the first end720E1of the planarization layer720from being separated from a lower layer thereof or being lifted due to the above step, an upper portion of the planarization layer720is covered by the second insulating layer740, and the cover layer730is formed close to the first end720E1of the planarization layer720. However, gas components generated in the planarization layer720may accumulate and cause lifting of the cover layer730.

By forming a plurality of through holes740H in the second insulating layer740directly contacting the planarization layer720, according to embodiments, outgassing of the planarization layer720may be facilitated, and thus, lifting of the cover layer730may be prevented or reduced.

For example, according to embodiments, each of the through holes740H is not filled with another material. As a result, outgassing of the planarization layer720may be facilitated through the through holes740H, and lifting of the cover layer730may be prevented or reduced. For example, although some of the material used to form the layer disposed directly above the through holes740H may enter the through holes740H, the through holes740H are not entirely filled, and remain at least partially open, if not entirely open. As a result, gas released by the planarization layer720may be released into the through holes740H, which may decrease pressure, and thus, prevent or reduce lifting of the cover layer730that would otherwise be caused if the through holes740H were not present.

In an embodiment, a first end730E1of the cover layer730is not disposed above the planarization layer720in a first portion of the cover layer730further extending beyond the first end720E1of the planarization layer720in a direction toward the second area DA, as shown inFIG.14. A second end730E2of the cover layer730may be disposed above the planarization layer720in a second portion of the cover layer730extending over the planarization layer720in a direction toward the first area OA.

A width W31of the first portion of the cover layer730may be less than a width W32of the second portion of the cover layer730. For example, the width W31of the first portion of the cover layer730may be about 20 and the width W32of the second portion of the cover layer730may be about 60 μm.

As shown inFIG.14, in an embodiment, the first portion of the cover layer730having the width W31does not cover the planarization layer720, and the second portion of the cover layer730having the width W32covers the planarization layer. Thus, in an embodiment, the width W31of the first portion of the cover layer730that does not cover the planarization layer720is less than the width W32of the second portion of the cover layer730that covers the planarization layer720.

A third insulating layer750and a fourth insulating layer760may be disposed on the cover layer730. The third insulating layer750may include an inorganic insulating material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. Alternatively, the third insulating layer750may include an organic insulating material. The fourth insulating layer760may include an inorganic insulating material or may include an organic insulating material. The fourth insulating layer760including an organic insulating material may have a substantially flat upper surface. The organic insulating material may be a photoresist (negative or positive), or may include a polymer-based organic material.

At least one of the first insulating layer710, the second insulating layer740, the third insulating layer750, and the fourth insulating layer760may include the same material as an insulating layer included in the input sensing layer40described above with reference toFIGS.8to11C.

In an embodiment, each of the first insulating layer710, the second insulating layer740, the third insulating layer750, and the fourth insulating layer760may be formed together during the same process as at least one insulating layer of the input sensing layer40described above with reference toFIGS.8to11C. For example, as shown inFIG.12, the first insulating layer710may include the same material as a first sub-lower insulating layer401a, which is a portion of the lower insulating layer401of the input sensing layer40, and may be integrally formed with the first sub-lower insulating layer401aof the input sensing layer40. The second insulating layer740may include the same material as a second sub-lower insulating layer401b, which is a portion of the lower insulating layer401, and may be integrally formed with the second sub-lower insulating layer401b. The third insulating layer750may include the same material as the middle insulating layer403of the input sensing layer40and may be integrally formed with the middle insulating layer403. The fourth insulating layer760may include the same material as the upper insulating layer405of the input sensing layer40and may be integrally formed with the upper insulating layer405. In an embodiment, the first insulating layer710, the second insulating layer740, and the third insulating layer750may include an inorganic insulating material, and the fourth insulating layer760may include an organic insulating material.

The first and second openings10H and40H of the display apparatus1may be formed, for example, by performing a cutting or scribing process after forming the above-described component and layers on the substrate100.

In this regard, the cross-sectional structure ofFIG.12may be understood as a cross-section of the display panel10manufactured by performing a cutting or scribing process along a first line SCL1. Ends of the layers disposed on the substrate100around the first area OA may be on the same vertical line as an end100E of the substrate100defining the first opening10H. For example, an end710E of the first insulating layer710, a second end720E2of the planarization layer720, and an end740E of the second insulating layer740may be on the same vertical line as the end100E defining an opening100H of the substrate100. Similarly, ends of the first and second inorganic encapsulation layers310and330, the organic material layer320A, and the third and fourth insulating layers750and760may also be on the same vertical line as the end100E of the substrate100.

An area from the first line SCL1to an nthline SCLn shown inFIG.12may be an area CA through which laser may pass during a cutting or scribing process of manufacturing processes of a display panel. That is, a cutting or scribing process may be performed along one of the first to nthlines SCL1to SCLn, and a resulting cross-sectional structure may correspond to a structure of a display apparatus according to one or more embodiments.

Referring toFIGS.15and16, according to embodiments, the cover layer730may include a second through hole730H. The width of the second through hole730H may be varied. In an embodiment, the second through hole730H may overlap the first through hole740H, as shown inFIG.15. The second through hole730H may entirely overlap the first through hole740H (e.g., the second through hole730H may be aligned with the first through hole740H) as shown inFIG.15, or the second through hole730H may at least partially overlap the first through hole740H. The second through hole730H may have substantially the same size as the first through hole740H. In an embodiment, the second through hole730H does not overlap the first through hole740H, as shown inFIG.16.

According to embodiments, the through holes730H and740H are not filled with another material. As a result, outgassing of the planarization layer720may be facilitated through the through holes730H and740H. For example, although some of the material used to form the layer disposed directly above the through holes730H and740H may enter the through holes730H and740H, the through holes730H and740H are not entirely filled, and remain at least partially open, if not entirely open. As a result, gas released by the planarization layer720may be released into the through holes730H and740H, which may decrease pressure, and thus, prevent or reduce lifting of the cover layer730that would otherwise be caused if the through holes730H and740H were not present.

FIG.17shows a cross-sectional structure of the display panel10having a cutting or scribing process performed along the nthline SCLn. The cross-sectional structure(s) of a display panel having a cutting or scribing process performed along one of the first to nthlines SCL1to SCLn shown inFIG.12may correspond to embodiments of the present application.

The cross-sectional structure shown inFIGS.12and17may be understood as a structure surrounding the first area OA. For example, as described above with reference toFIG.6, the grooves G disposed between the first area OA and the second area DA may have a ring shape surrounding the first opening10H and the first area OA. Similarly, on the plane, the planarization layer720ofFIG.12may have a ring shape surrounding the first opening10H and the first area OA, and in this regard,FIG.18shows the planarization layer720.

FIG.18is a plan view of the first area OA and a periphery thereof in a display apparatus according to an embodiment, which is excerpted from the planarization layer720and the cover layer730for convenience of description.

Referring toFIG.18, the planarization layer720may have a ring shape surrounding the first area OA. The planarization layer720may be disposed in the third area MA, and on the plane, the second end720E2of the planarization layer720may be substantially the same as an outline of the first area OA.

The cover layer730may at least partially cover the first end720E1of the planarization layer720. In this regard,FIG.18shows the cover layer730having a ring shape surrounding the first area OA and entirely covering the first end720E1of the planarization layer720. However, embodiments are not limited thereto. For example, in an embodiment, the cover layer730may partially cover the first end720E1of the planarization layer720, may have a shape partially surrounding the first area OA on the plane.

As described above, the cover layer730may include the same material as one of the conductive layers included in the input sensing layer40(ofFIG.12), and may be on the same layer as one of the conductive layers included in the input sensing layer40(ofFIG.12). For example, the cover layer730may include the same material as the first conductive layer410of the input sensing layer40or the second conductive layer420of the input sensing layer40, and may be disposed on the same layer as the first conductive layer410of the input sensing layer40or the second conductive layer420of the input sensing layer40.

The cover layer730may include a metal layer. For example, the cover layer730may have a metal multilayer structure in which, for example, a titanium layer, an aluminum layer, and a titanium layer are sequentially stacked.

FIGS.19A to19Dshow various arrangements of through holes in the second insulating layer740and the cover layer730, according to embodiments.

FIGS.19A and19Bshow embodiments in which only the second insulating layer740includes first through holes740H.FIG.19Ashows the first through holes740H disposed in columns in which the first through holes740H are aligned with each other in adjacent columns.FIG.19Bshows the first through holes740H disposed in columns in which the first through holes740H are not aligned with each other in adjacent columns. InFIG.19B, the first through holes740H in alternating columns may be aligned with each other.

FIGS.19B and19Cshow embodiments in which the second insulating layer740includes the first through holes740H and the cover layer730includes second through holes730H.FIG.19Cshows some of the second through holes730H overlapping the first through holes740H, and some of the second through holes730H not overlapping the first through holes740H.FIG.19Dshows the second through holes730H and the first through holes740H entirely overlapping each other.

AlthoughFIGS.19A to19Dshow through holes in a tetragonal shape, embodiments are not limited thereto. For example, in embodiments, the through holes may be variously modified to have, for example, a circular shape, an oval shape, a polygonal shape such as a triangular or tetragonal shape, a star shape, a diamond shape, an atypical shape, etc.

According to one or more embodiments, faults such as lifting or exfoliation of a film around an opening area may be prevented or reduced.

While one or more embodiments have been described herein with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure, as defined by the following claims.