Patent ID: 12222626

It should be noted that, for clarity, in the drawings used to describe the embodiments of the present disclosure, sizes of layers, structures, or regions may be enlarged or reduced, that is, the drawings are not drawn according to actual scale.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following description, for purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is obvious that the various exemplary embodiments may be implemented without the specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagrams to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, without departing from the inventive concept, specific shapes, configurations and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

In the drawings, sizes and relative sizes of elements may be enlarged for clarity and/or description purposes. In this way, a size and a relative size of each element are not necessarily to be limited to a size and a relative size shown in the drawing. When the exemplary embodiment may be implemented differently, a specific process sequence may be performed differently from a sequence described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals indicate the same elements.

When an element is described as being “on”, “connected to” or “coupled to” another element, the element may be directly on the another element, directly connected to the another element or directly coupled to the another element, or there may be an intermediate element. However, when an element is described as being “directly on”, “directly connected to” or “directly coupled to” another element, there is no intermediate element. Other terms and/or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, “between” and “directly between”, “adjacent” and “directly adjacent”, “above” and “directly above” etc. In addition, the term “connect” may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection. In addition, X axis, Y axis, and Z axis are not limited to three axes of a Cartesian coordinate system, which may be interpreted in broader meaning. For example, the X axis, the Y axis, and the Z axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, “at least one of X, Y, and Z” and “at least one selected from a group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As shown in the present disclosure, the term “and/or” includes any and all combinations of one or more of the related items.

It should be understood that, although terms “first”, “second”, etc. may be used herein to describe various elements, the elements should not be limited by the terms. The terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be named as a second element, and similarly, a second element may be named as a first element.

In the present disclosure, unless otherwise specified, an expression “patterning process” generally includes steps of photoresist coating, exposure, development, etching and photoresist stripping, and the like. The expression “one patterning process” refers to a process of forming patterned layers, elements, components and the like by using one mask.

It should be noted that, an expression “same layer” refers to a layer structure formed by using a same film forming process to form a film layer for forming specific patterns, and then using a same mask to pattern the film layer through a patterning process. Depending on different specific patterns, the patterning process may include a plurality of exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. The specific patterns may also be located at different heights or have different thicknesses.

It should be noted that, in order to clearly illustrate a stacking relationship between various elements, components, members or patterns, in the drawings of the present disclosure, unless otherwise specified, elements, components, members or patterns located in the same layer are generally shown using a same cross-sectional line.

It should be noted that since a source electrode and a drain electrode of a thin film transistor may generally be used interchangeably, in the present disclosure, expressions such as first electrode and second electrode of thin film transistor are used. It should be understood that, a “first electrode” of the thin film transistor may refer to one of the source electrode and the drain electrode of the thin film transistor, and a “second electrode” of the thin film transistor may refer to the other one of the source electrode and the drain electrode of the thin film transistor.

In the present disclosure, unless otherwise specified, expressions “disposed continuously” and “extending continuously” refer to that two regions, parts or components extend, connect or dispose continuously and without interruption, that is, the two regions, parts or components form an integral structure, and there is no disconnection between the two regions, parts or components.

The embodiments of the present disclosure provide a display substrate, including: a base substrate; a plurality of gate lines and a plurality of data lines on the base substrate, each gate line extends in a row direction, each data line extends in a column direction, and the plurality of gate lines and the plurality of data lines intersect to surround a plurality of pixels; a first thin film transistor and a second thin film transistor in each pixel on the base substrate, each of the first thin film transistor and the second thin film transistor includes a first electrode and a second electrode; and a pixel electrode in each pixel on the base substrate, the pixel electrode includes a pixel conductive layer, the first electrode is located in a layer different from a layer where the pixel conductive layer is located, and the second electrode is located in a layer different from the layer where the pixel conductive layer is located, wherein the first electrode of the first thin film transistor is electrically connected to the pixel conductive layer of the pixel electrode, the second electrode of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor, and the second electrode of the second thin film transistor is electrically connected to the data line; and wherein an orthographic projection of a combination of the second electrode of the first thin film transistor and the first electrode of the second thin film transistor on the base substrate at least partially overlaps with an orthographic projection of the pixel conductive layer of the pixel electrode on the base substrate. With such the display substrate, the pixel electrode covers an area where the thin film transistor is located, and a coverage area of the pixel electrode is increased. In this way, at least an opening ratio of the pixel may be increased, thereby improving the display performance.

FIG.1is a schematic plan view of a display substrate in the prior art, which schematically illustrates a plurality of (for example, 4) pixels included in the display substrate.FIG.2is a schematic plan view of a pixel included in the display substrate inFIG.1.FIG.3Ais a cross-sectional view of the display substrate in the prior art taken along line AA′ inFIG.2.FIG.3Bis a cross-sectional view of a display device in the prior art.

For example, the display substrate may be a display substrate of an electronic paper display device, and the display substrate may be an array substrate of the electronic paper display device.

Referring toFIGS.1to3Ain combination, the display substrate may include a plurality of pixels P. InFIG.1, the plurality of (for example, 4) pixels P are exemplarily shown. It should be understood that, the display substrate may include more pixels P. Specifically, the display substrate includes: a base substrate1; and a plurality of gate lines GL, a plurality of data lines (or referred to as source lines) DL and a plurality of common electrode lines CL on the base substrate1. The plurality of gate lines GL extend in parallel in a row direction X, the plurality of data lines DL extend in parallel in a column direction Y, the plurality of common electrode lines CL extend in parallel in the column direction Y, and each common electrode line CL is located between two adjacent data lines DL. The plurality of gate lines GL and the plurality of data lines DL are intersected to surround the plurality of pixels P.

The display substrate may include two thin film transistors in one pixel P. For ease of description, the two thin film transistors are referred to as a first thin film transistor T1and a second thin film transistor T2, respectively, and the first thin film transistor T1is farther away from a data line DL than the second thin film transistor T2. That is, inFIGS.1to3A, the first thin film transistor T1is located on a right side of the second thin film transistor T2.

Referring toFIGS.2and3A, the first thin film transistor T1includes a first source electrode T1S, a first gate electrode T1G and a first drain electrode T1D, and the second thin film transistor T2includes a second source electrode T2S, a second gate electrode T2G and a second drain electrode T2D. The first drain electrode T1D of the first thin film transistor T1is electrically connected to a pixel electrode. The first source electrode T1S of the first thin film transistor T1and the second drain electrode T2D of the second thin film transistor T2are an integral structure. A gate line GL is electrically connected to the first gate electrode T1G of the first thin film transistor T1and the second gate electrode T2G of the second thin film transistor T2. For example, the gate line GL, the first gate electrode T1G and the second gate electrode T2G are an integral structure, that is, the gate line GL, the first gate electrode T1G and the second gate electrode T2G are a continuously extending integral structure. The second source electrode T2S of the second thin film transistor T2is electrically connected to the data line DL.

It should be understood that the source electrode and the drain electrode of the thin film transistor may be interchanged. For example, the first source electrode of the first thin film transistor may be electrically connected to the pixel electrode, and the second drain electrode of the second thin film transistor may be electrically connected to the data line.

An electronic ink is controlled by two thin film transistors connected in series to achieve display, and the two thin film transistors connected in series may reduce a drain current and improve a display quality.

Continuing to refer toFIGS.1to3A, the display substrate may include a first conductive layer2, a gate insulating layer3, an active layer4, a second conductive layer5, a passivation layer6and a pixel conductive layer7that are disposed on the base substrate1.

The first conductive layer2may include the first gate electrode T1G of the first thin film transistor T1, the second gate electrode T2G of the second thin film transistor T2and the gate line GL.

The gate insulating layer3is located on a side of the first conductive layer2away from the base substrate1.

The active layer4is located on a side of the gate insulating layer3away from the base substrate1. The active layer4may include a semiconductor material, such as amorphous silicon, polysilicon or metal oxide, and the like.

The second conductive layer5is located on a side of the active layer4away from the base substrate1. The second conductive layer5may include: the first source electrode T1S and the first drain electrode T1D of the first thin film transistor T1, the second source electrode T2S and the second drain electrode T2D of the second thin film transistor T2, the data line DL, the common electrode Line CL and a common electrode8.

The passivation layer6is located on a side of the second conductive layer5away from the base substrate1. An orthographic projection of the passivation layer6on the base substrate1covers an orthographic projection of the second conductive layer5on the base substrate1. The passivation layer6is made of an insulating material.

The pixel conductive layer7is located on a side of the passivation layer6away from the base substrate1.

Referring toFIGS.2and3A, the display substrate may further include a via hole62penetrating the passivation layer6, the via hole62exposes a part of the first drain electrode T1D of the first thin film transistor T1. A part of the pixel conductive layer7may be filled in the via hole62. In this way, the pixel conductive layer7is electrically connected to the first drain electrode T1D of the first thin film transistor T1. In this way, the pixel conductive layer7constitutes a part of the pixel electrode. In this way, an electrical connection between the pixel electrode and the first drain electrode T1D of the first thin film transistor T1is achieved.

In this way, under a control of a gate line signal supplied by the gate line GL, a signal (for example, voltage) supplied by the data line DL may be transmitted to the pixel electrode.

Further, referring toFIGS.1and2, the common electrode line CL may be electrically connected to the common electrode8. For example, common electrodes8of the plurality of pixels P adjacent to each other in the column direction Y may be electrically connected by the common electrode line CL. In this way, a signal (for example, voltage) supplied by the common electrode line CL may be transmitted to the common electrode8. Therefore, a storage capacitor may be formed between the pixel electrode (i.e, the pixel conductive layer7) and the common electrode8.

Referring toFIG.3B, an electronic ink layer9is disposed on a side of a pixel conductive layer7away from a base substrate1, for example, the electronic ink layer9may be disposed on a counter substrate11. It should be understood that, an upper electrode is also disposed on the counter substrate11. The electronic ink layer9may include a plurality of microcapsules, and a microcapsule may include charged particles. By controlling an electric field between the pixel electrode and the upper electrode, the charged particles may be driven to move in the microcapsules. In this way, by adjusting colors of the charged particles in the microcapsules, the electronic ink may display patterns and colors.

In the exemplary embodiments ofFIG.1toFIG.3AandFIG.3B, except for the first drain electrode T1D of the first thin film transistor T1, an orthographic projection of the pixel conductive layer7on the base substrate1does not overlap with other parts of the first thin film transistor T1and the second thin film transistor T2(including the first gate electrode T1G and the first source electrode T1S of the first thin film transistor T1, and the second gate electrode T2G, the second source electrode T2S and the second drain electrode T2D of the second thin film transistor T2). That is, the orthographic projection of the pixel conductive layer7on the base substrate1does not cover most of an orthographic projections of the first thin film transistor T1and the second thin film transistor T2on the base substrate1.

In this way, as shown inFIG.2, a shape of the pixel P is rectangular or approximately rectangular (for example, a rounded rectangle). However, the orthographic projection of the pixel conductive layer7on the base substrate1is not a complete rectangle and has a gap in an area where the two thin film transistors are located. For example, in one example, an area of the gap occupies about 13% of an area of the entire pixel P. Due to the existence of the gap, it is not conducive to increasing the opening ratio of pixel.

Further, referring toFIGS.2,3A and3Bin combination, since there is no pixel electrode above the area where the two thin film transistors are located, there is no electric field to drive the charged particles of the electronic ink layer in the area. Or, even if there is an electric field, the electric field is also a fringe electric field generated at an edge of the pixel electrode. A driving ability of the fringe electric field is weak, so that a dispersion degree of the charged particles in the electronic ink layer is poor. Under low temperature conditions, the charged particles in the electronic ink layer are particularly sensitive to the gap, which may easily lead to undesirable phenomena such as blurred handwriting on the display screen of the electronic paper.

Hereinafter, some exemplary embodiments of the present disclosure will be described with reference to the drawings.

FIG.4is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure, which schematically illustrates a plurality of (for example, 4) pixels included in the display substrate.FIG.5is a schematic plan view of a pixel included in the display substrate inFIG.4.FIG.6Ais a cross-sectional view of the display substrate taken along line AA′ inFIG.5according to some exemplary embodiments of the present disclosure.FIG.6Bis a cross-sectional view of a display device according to some exemplary embodiments of the present disclosure;

For example, the display substrate may be a display substrate of an electronic paper display device, and the display substrate may be an array substrate of an electronic paper display device. Correspondingly, the display device may be an electronic paper display device.

Referring toFIGS.4to6Ain combination, the display substrate may include a plurality of pixels P. InFIG.4, the plurality of (for example, 4) pixels P are exemplarily shown. It should be understood that, the display substrate may include more pixels P. Specifically, the display substrate includes: a base substrate10; a plurality of gate lines GL, a plurality of data lines (or referred to as source lines) DL and a plurality of common electrode lines CL on the base substrate10. The plurality of gate lines GL extend in parallel in the row direction X, the plurality of data lines DL extend in parallel in the column direction Y, the plurality of common electrode lines CL extend in parallel in the column direction Y, and each common electrode line CL is located between two adjacent data lines DL. The plurality of gate lines GL and the plurality of data lines DL are intersected to surround the plurality of pixels P.

It should be noted that, in the illustrated embodiment, the row direction X and the column direction Y are perpendicular to each other. However, the embodiments of the present disclosure are not limited to this, and the row direction X and the column direction Y may be any two directions that intersect at other angles in a plane on which the pixel is arranged.

In the exemplary embodiment of the present disclosure, the display substrate may include two thin film transistors in one pixel P, that is, a driving circuit of each pixel may include two thin film transistors. For ease of description, the two thin film transistors are referred to as a first thin film transistor T1and a second thin film transistor T2, respectively, and the first thin film transistor T1is farther away from a data line DL than the second thin film transistor T2. That is, inFIGS.5and6A, the first thin film transistor T1is located on a right side of the second thin film transistor T2.

Referring toFIGS.5and6A, the first thin film transistor T1includes a first source electrode T1S, a first gate electrode T1G and a first drain electrode T1D, and the second thin film transistor T2includes a second source electrode T2S, a second gate electrode T2G and a second drain electrode T2D. The first drain electrode T1D of the first thin film transistor T1is electrically connected to a pixel electrode. The first source electrode T1S of the first thin film transistor T1and the second drain electrode T2D of the second thin film transistor T2are an integral structure. A gate line GL is electrically connected to the first gate electrode T1G of the first thin film transistor T1and the second gate electrode T2G of the second thin film transistor T2. For example, the gate line GL, the first gate electrode T1G and the second gate electrode T2G are an integral structure, that is, the gate line GL, the first gate electrode T1G and the second gate electrode T2G are a continuously extending integral structure. The second source electrode T2S of the second thin film transistor T2is electrically connected to the data line DL.

It should be understood that, the source electrode and the drain electrode of the thin film transistor may be interchanged. For example, the first source electrode of the first thin film transistor may be electrically connected to the pixel electrode, and the second drain electrode of the second thin film transistor may be electrically connected to the data line.

In the exemplary embodiments of the present disclosure, an electronic ink is controlled by two thin film transistors connected in series to achieve display, and the two thin film transistors connected in series may reduce a drain current and improve a display quality.

The base substrate10may be a rigid substrate, such as a glass substrate; or, the base substrate10may be a flexible substrate, such as a polyimide (PI) substrate.

Continuing to refer toFIGS.4to6A, the display substrate may include a first conductive layer20, a gate insulating layer30, an active layer40, a second conductive layer50, a passivation layer60and a pixel conductive layer70that are disposed on the base substrate10.

The first conductive layer20may include the first gate electrode T1G of the first thin film transistor T1, the second gate electrode T2G of the second thin film transistor T2, the gate line GL and a gate conductive layer24. That is, the first gate electrode T1G of the first thin film transistor T1, the second gate electrode T2G of the second thin film transistor T2, the gate line GL and the gate conductive layer24are located in a same layer made of a gate metal material. For example, the gate electrodes T1G, T2G and the gate line GL are a continuously extending structure, the gate conductive layer24and the continuously extending structure are disposed at an interval and insulated from each other.

The gate insulating layer30is located on a side of the first conductive layer20away from the base substrate10. An orthographic projection of gate insulating layer30on base substrate10covers an orthographic projection of each of the first gate electrode T1G of the first thin film transistor T1, the second gate electrode T2G of the second thin film transistor T2, the gate line GL and the gate conductive layer24on the base substrate10.

The active layer40is located on a side of the gate insulating layer30away from the base substrate1. The active layer4may include a semiconductor material, such as amorphous silicon, polysilicon or metal oxide, and the like.

The second conductive layer50is located on a side of the active layer40away from the base substrate1. The second conductive layer5may include: the first source electrode T1S and the first drain electrode T1D of the first thin film transistor T1, the second source electrode T2S and the second drain electrode T2D of the second thin film transistor T2, the data line DL, the common electrode Line CL and a common electrode80. That is, the first source electrode T1S and the first drain electrode T1D of the first thin film transistor T1, the second source electrode T2S and the second drain electrode T2D of the second thin film transistor T2, the data line DL, the common electrode line CL and the common electrode80are all located in a same layer made of a source and drain metal material. In some examples, an orthographic projection of a combination of all the components (for example, the first source electrode T1S and the first drain electrode T1D of the first thin film transistor T1, the second source electrode T2S and the second drain electrode T2D of the second thin film transistor T2, the data line DL, the common electrode line CL and the common electrode80) in the second conductive layer50on the base substrate10falls within an orthographic projection of the active layer40on the base substrate10.

The passivation layer60is located on a side of the second conductive layer50away from the base substrate10. An orthographic projection of the passivation layer60on the base substrate10covers an orthographic projection of the second conductive layer50on the base substrate10. The passivation layer60is made of an insulating material.

The pixel conductive layer70is located on a side of the passivation layer6away from the base substrate10. The pixel conductive layer70is made of a transparent conductive material (for example, ITO).

Referring toFIGS.5and6A, the display substrate may further include a via hole602penetrating the passivation layer60, the via hole602exposes a part of the first drain electrode T1D of the first thin film transistor T1. For example, two via holes602are disposed in each pixel P. A part of the pixel conductive layer7may be filled in the via hole62. In this way, the pixel conductive layer7is electrically connected to the first drain electrode T1D of the first thin film transistor T1. Since two via holes602are disposed in each pixel P, it may be ensured that there is a reliable electrical connection between the pixel conductive layer70and the first drain electrode T1D of the first thin film transistor T1. In this way, an electrical connection between a pixel electrode90and the first drain electrode T1D of the first thin film transistor T1is achieved.

Continuing to refer toFIGS.5and6A, the display substrate may further include a via hole601penetrating both the gate insulating layer30and the passivation layer60, the via hole601exposes a part of the gate conductive layer24. For example, two via holes601are disposed in each pixel P. A part of the pixel conductive layer70may be filled in the via hole601, In this way, the pixel conductive layer70and the gate conductive layer24are electrically connected. Since two via holes601are disposed in each pixel P, it may be ensured that there is a reliable electrical connection between the pixel conductive layer70and the gate conductive layer24. In this way, the pixel conductive layer70made of the transparent conductive material and the gate conductive layer24made of the gate metal material are electrically connected to form the pixel electrode90of the display substrate.

In this way, under a control of a gate line signal supplied by the gate line GL, a signal (for example, voltage) supplied by the data line DL may be transmitted to the pixel electrode90.

Further, referring toFIGS.4and5, the common electrode line CL may be electrically connected to the common electrode80. For example, common electrodes80of the plurality of pixels P adjacent to each other in the column direction Y may be electrically connected by the common electrode line CL. In this way, a signal (for example, voltage) supplied by the common electrode line CL may be transmitted to the common electrode80. Therefore, a storage capacitor may be formed between the pixel electrode90and the common electrode80.

Referring toFIG.6B, an electronic ink layer100is disposed on a side of a pixel conductive layer70away from a base substrate10, for example, the electronic ink layer100may be disposed on a counter substrate110. It should be understood that an upper electrode is also disposed on the counter substrate110. The electronic ink layer100may include a plurality of microcapsules, and a microcapsule may include charged particles. By controlling an electric field between the pixel electrode90and the upper electrode, the charged particles may be driven to move in the microcapsules. In this way, by adjusting colors of the charged particles in the microcapsules, the electronic ink may display patterns and colors.

In the exemplary embodiments ofFIG.4toFIG.6AandFIG.6B, an orthographic projection of the pixel conductive layer70on the base substrate10covers an orthographic projection of the gate conductive layer24on the base substrate10, and the orthographic projection of the pixel conductive layer70on the base substrate10covers an orthographic projection of the common electrode80on the base substrate10. That is, a coverage area of the pixel conductive layer70is set to be relatively large to increase the opening ratio of each pixel, so that the display performance may be improved.

In the exemplary embodiments ofFIGS.4to6A and6B, the orthographic projection of the pixel conductive layer70on the base substrate10at least partially overlaps with an orthographic projection of the first drain electrode T1D of the first thin film transistor T1on the base substrate10. In this way, an electrical connection between the pixel conductive layer70and the drain electrode of the thin film transistor may be achieved.

An orthographic projection of a combination of the first source electrode T1S of the first thin film transistor T1and the second drain electrode T2D of the second thin film transistor T2on the base substrate10at least partially overlaps with the orthographic projection of the pixel conductive layer70on the base substrate10. In other words, the pixel conductive layer70includes a protrusion702. The orthographic projection of the combination of the first source electrode T1S of the first thin film transistor T1and the second drain electrode T2D of the second thin film transistor T2on the base substrate10at least partially overlaps with an orthographic projection of the protrusion702on the base substrate10. In some embodiments, the first source electrode T1S of the first thin film transistor T1and the second drain electrode T2D of the second thin film transistor T2are a continuously extending integral structure, and the orthographic projection of the protrusion702on the base substrate10at least partially overlaps with the orthographic projection of the continuously extending integral structure on the base substrate10.

Specifically, the first gate electrode T1G of the first thin film transistor T1and the second gate electrode T2G of the second thin film transistor T2are disposed at an interval in the row direction X. The orthographic projection of the protrusion702on the base substrate10falls with an orthographic projection of a gap between the first gate electrode T1G of the first thin film transistor T1and the second gate electrode T2G of the second thin film transistor T2on the base substrate10.

Referring toFIGS.5and6A, the orthographic projection of the pixel conductive layer70on the base substrate10does not overlap with the first gate electrode T1G of the first thin film transistor T1and the second gate electrode T2G of the second thin film transistor T2.

Specifically, the orthographic projection of the protrusion702on the base substrate10does not overlap with the first gate electrode T1G of the first thin film transistor T1and the second gate electrode T2G of the second thin film transistor T2. As shown inFIGS.5and6A, the orthographic projection of the protrusion702on the base substrate10and the first gate electrode T1G of the first thin film transistor T1are disposed at a predetermined distance in the row direction X. For ease of description, the predetermined distance is referred to as a first predetermined distance, as shown by d1inFIG.6A. The orthographic projection of the protrusion702on the base substrate10and the second gate electrode T2G of the second thin film transistor T2are disposed at a predetermined distance in the row direction X. For ease of description, the predetermined distance is referred to as a second predetermined distance, as shown in d2inFIG.6A. For example, the first predetermined distance d1may be equal to the second predetermined distance d2.

For example, the orthographic projection of the protrusion702on the base substrate10may have a rectangular or approximately rectangular shape (for example, a rounded rectangle), and a width of the orthographic projection of the protrusion702on the base substrate10in the row direction X is indicated as w1.

In some exemplary embodiments, considering factors such as process fluctuations, the width w1is set to be 3.4 to 6.5 micrometers. Correspondingly, the first predetermined distance d1and the second predetermined distance d2may be set to 1.75 to 3.3 micrometers. For example, when the width w1is 3.4 micrometers, both the first predetermined distance d1and the second predetermined distance d2are 3.3 micrometers; when the width w1is 6.5 micrometers, both the first predetermined distance d1and the second predetermined distance d2are 1.75 micrometers. That is, by disposing the protrusion702and the gate electrodes of the two thin film transistors at an interval and setting the first predetermined distance d1and the second predetermined distance d2to be 1.75 to 3.3 micrometers, an area of the protrusion covering the gap between the gate electrodes of the two thin film transistors may be made as large as possible, while even if the factor of process fluctuation is considered, the protrusion still does not overlap with the gate electrode.

In this way, the coverage area of the pixel conductive layer70may be increased. That is, the coverage area of the pixel electrode90is increased to further increase the opening ratio of each pixel, so that the display performance may be improved. Moreover, since the pixel conductive layer70does not overlap with the gate electrodes of the two thin film transistors, the thin film transistor may maintain a small drain current, and an influence of a gate line voltage change on the pixel electrode may be reduced, so that the electronic paper keeps pulling the pixel electrode while the electronic paper keeps display.

Further, referring toFIG.6B, since a part of the pixel electrode overlaps with the area where the two thin film transistors are located, an electric field between the pixel electrode and the common electrode may act on the area where the two thin film transistors are located. As shown inFIG.6B, there are also an electric field and a fringe electric field in the area, the electric field may drive the charged particles in the electronic ink layer located in the area. In this way, undesirable phenomena such as blurred handwriting in the area may be solved, and the display quality may be improved.

It should be noted that referring back toFIGS.5and6A, the orthographic projection of the pixel conductive layer70on the base substrate10does not overlap with an orthographic projection of the second source electrode T2S of the second thin film transistor T2on the base substrate10, and the orthographic projection of the pixel conductive layer70on the base substrate10does not overlap with an orthographic projection of the data line DL on the base substrate10. In addition, the orthographic projection of the pixel conductive layer70on the base substrate10does not overlap with an orthographic projection of the gate line GL on the base substrate10.

For example, in the embodiments shown inFIGS.1to6A, a width of a channel region of each of the first thin film transistor T1and the second thin film transistor T2may be 40 micrometers and a length of thereof may be 4.5 micrometers. The first thin film transistor T1and the second thin film transistor T2connected in series may be regarded as a thin film transistor with a double gate structure. An aspect ratio of the channel of the thin film transistor with the double gate structure may be 40/(4.5+4.5). Under conditions of a same pixel size and a same thin film transistor size, the display substrate according to the embodiment shown inFIGS.1to3Aand the embodiment shown inFIGS.4to6Amay have following performance parameters.

TABLE 1Comparison table of performance parameters of display substrateEmbodiment shown inEmbodiment shown inFIG. 1 to 3AFIG. 4 to 6AOpening radio71.77%77%On-state current3.22 μA3.23 μAIonOff-state current0.41 pA0.83 pAIoff

Through comparison, it is found that in the embodiment shown inFIGS.4to6A, the coverage area of the pixel electrode is increased by adding the protrusion702, thereby greatly increasing the opening ratio of the pixel. While the on-state current Ion of the thin film transistor remains basically unchanged, and the off-state current Ioff is slightly increased, but the off-state current Ioff is still within a standard range of electronic paper display products. That is, the display substrate provided by the embodiments of the present disclosure may greatly increase the opening ratio while maintaining the driving performance, thereby improving the display quality.

FIG.7is a schematic plan view of a pixel included in a display substrate according to some exemplary embodiments of the present disclosure.FIG.8is a cross-sectional view of the display substrate taken along line AA′ inFIG.7according to some exemplary embodiments of the present disclosure. The following will mainly describe differences between the embodiment shown inFIG.7andFIG.8with respect to the embodiment shown inFIG.5andFIG.6A, and other similarities may refer to the above descriptions.

Referring toFIGS.7and8, an orthographic projection of a pixel conductive layer70on a base substrate10at least partially overlaps with an orthographic projection of a first drain electrode T1D of a first thin film transistor T1on the base substrate10.

An orthographic projection of a combination of a first source electrode T1S of the first thin film transistor T1and a second drain electrode T2D of a second thin film transistor T2on the base substrate10at least partially overlaps with the orthographic projection of the pixel conductive layer70on the base substrate10. In other words, the pixel conductive layer70includes a protrusion702, the orthographic projection of the combination of the first source electrode T1S of the first thin film transistor T1and the second drain electrode T2D of the second thin film transistor T2on the base substrate10at least partially overlaps with an orthographic projection of the protrusion702on the base substrate10. Specifically, a first gate electrode T1G of the first thin film transistor T1and a second gate electrode T2G of the second thin film transistor T2are disposed at an interval in a row direction X, and the orthographic projection of the protrusion702on the base substrate10falls within an orthographic projection of a gap between the first gate electrode T1G of the first thin film transistor T1and the second gate electrode T2G of the second thin film transistor T2on the base substrate10.

The orthographic projection of the pixel conductive layer70on the base substrate10at least partially overlaps with an orthographic projection of a second source electrode T2S of the second thin film transistor T1on the base substrate10. In other words, the pixel conductive layer70includes a protrusion704, an orthographic projection of the protrusion704on the base substrate10at least partially overlaps with an orthographic projection of the second source electrode T2S of the second thin film transistor T1on the base substrate10. Specifically, the second gate electrode T2G of the second thin film transistor T2and the data line DL are disposed at an interval in the row direction X, and the orthographic projection of the protrusion704on the base substrate10falls within an orthographic projection of a gap between the second gate electrode T2G of the second thin film transistor T2and the data line DL on the base substrate10.

The orthographic projection of the pixel conductive layer70on the base substrate10does not overlap with the first gate layer T1G of the first layer T1and the second gate layer T2G of the second layer T2. Specifically, the orthographic projection of any one of the protrusion702and the protrusion704on the base substrate10does not overlap with the orthographic projections of any one of the first gate electrode T1G of the first thin film transistor T1and the second gate electrode T2G of the second thin film transistor T2on the base substrate10. As shown inFIG.7, the orthographic projection of the protrusion702on the base substrate10and the first gate electrode T1G of the first thin film transistor T1are disposed at a predetermined distance in the row direction X. For ease of description, the predetermined distance is referred to as a first predetermined distance, as shown by d1inFIG.8. The orthographic projection of the protrusion702on the base substrate10and the second gate electrode T2G of the second thin film transistor T2are disposed at a predetermined distance in the row direction X. For ease of description, the predetermined distance is referred to as a second predetermined distance, as shown in d2inFIG.8. For example, the first predetermined distance d1may be equal to the second predetermined distance d2. The orthographic projection of the protrusion704on the base substrate10and the second gate electrode T2G of the second thin film transistor T2are disposed at a predetermined distance in the row direction X. For ease of description, the predetermined distance is referred to as a third predetermined distance, as shown in d3inFIG.8.

For example, the orthographic projection of the protrusion702on the base substrate10may have a rectangular or approximately rectangular shape (for example, a rounded rectangle), and a width of the orthographic projection of the protrusion702on the base substrate10in the row direction X is indicated as a first width w1. The orthographic projection of the protrusion704on the base substrate10may have a rectangular shape, and a width of the orthographic projection of the protrusion704on the base substrate10in the row direction X is indicated as a second width w2.

In some exemplary embodiments, considering factors such as process fluctuations, the first width w1is set to be 3.4 to 6.5 micrometers. Correspondingly, both the first predetermined distance d1and the second predetermined distance d2may be set to 1.75 to 3.3 micrometers. For example, when the first width w1is 3.4 micrometers, both the first predetermined distance d1and the second predetermined distance d2are 3.3 micrometers; when the first width w1is 4.5 micrometers, both the first predetermined distance d1and the second predetermined distance d2are 2.75 micrometers; when the first width w1is 6.5 micrometers, both the first predetermined distance d1and the second predetermined distance d2are 1.75 micrometers.

In some exemplary embodiments, considering factors such as process fluctuations, the second width w2is set to be 3.4 to 4.4 micrometers. Correspondingly, the third predetermined distance d3may be set to 1.75 to 2.75 micrometers. For example, when the second width w2is 3.4 micrometers, the third predetermined distance d3is 2.75 micrometers; when the second width w2is 4.4 micrometers, the third predetermined distance d3is 1.75 micrometers.

In this embodiment, by disposing the protrusion702and the protrusion704and the gate electrodes of two thin film transistors at an interval, and the first predetermined distance d1and the second predetermined distance d2are set to 1.75 to 3.3 micrometers and the third predetermined distance d3is set to 1.75 to 2.75 micrometers, so as to make an area of the two protrusions covering the two thin film transistors excluding the gate electrodes as large as possible, while even if the factor of process fluctuation is considered, the two protrusions still do not overlap with the gate electrodes.

In this way, the coverage area of the pixel conductive layer70may be further increased. That is, the coverage area of the pixel electrode90is further increased to further increase the opening ratio of each pixel, so that the display performance may be improved. Moreover, since the pixel conductive layer70does not overlap with the gate electrodes of the two thin film transistors, the thin film transistor may maintain a small drain current, and an influence of a gate line voltage change on the pixel electrode may be reduced, so that the electronic paper keeps pulling the pixel electrode while the electronic paper keeps display.

For example, in the embodiments shown inFIGS.7to8, a width of a channel region of each of the first thin film transistor T1and the second thin film transistor T2may be 40 micrometers and a length of thereof may be 4.5 micrometers. The first thin film transistor T1and the second thin film transistor T2connected in series may be regarded as a thin film transistor with a double gate structure. An aspect ratio of the channel of the thin film transistor with the double gate structure may be 40/(4.5+4.5). Under conditions of a same pixel size and a same thin film transistor size, the opening ratio of the pixel may be increased to 78%. It may be seen that the opening ratio may be further improved.

It should be noted that in this embodiment, an on-state current Ion of the thin film transistor is slightly increased compared to the on-state current Ion of the thin film transistor in the embodiments shown inFIGS.4to6A; an off-state current Ioff of the thin film transistor in this embodiment increases significantly compared to the off-state current Ioff of the thin film transistor in the embodiment shown inFIGS.4to6A.

FIG.9is a schematic plan view of a pixel included in a display substrate according to some exemplary embodiments of the present disclosure.FIG.10is a cross-sectional view of the display substrate taken along line AA′ inFIG.9according to some exemplary embodiments of the present disclosure. The following will mainly describe differences between the embodiment shown inFIG.9andFIG.10with respect to the above embodiments, and other similarities may refer to the above descriptions.

Referring toFIGS.9and10, an orthographic projection of a pixel conductive layer70on a base substrate10substantially covers an orthographic projection of both a first thin film transistor T1and a second thin film transistor T2on the base substrate10. That is, the orthographic projection of the pixel conductive layer70on the base substrate10covers an orthographic projection of a first drain electrode T1D of the first thin film transistor T1on the base substrate10, the orthographic projection of the pixel conductive layer70on the base substrate10also covers an orthographic projection of a combination of a first source electrode T1S of the first thin film transistor T1and a second drain electrode T2D of the second thin film transistor T2on the base substrate10, the orthographic projection of the pixel conductive layer70on the base substrate10also covers an orthographic projection of each of a first gate electrode T1G of the first thin film transistor T1and a second gate electrode T2G of the second thin film transistor T2on the base substrate10, and the orthographic projection of the pixel conductive layer70on the base substrate10also covers an orthographic projection of a second source electrode T2S of the second thin film transistor T2on the base substrate10.

Referring toFIG.9, the orthographic projection of the pixel conductive layer70on the base substrate10has a rectangular or approximately rectangular shape. For example, the approximate rectangle may include a rectangle with rounded corners, and the rectangle or the approximate rectangle has a no gap design.

In this way, a coverage area of the pixel conductive layer70may be further increased, that is, a coverage area of a pixel electrode90may be further increased, so as to further increase an opening ratio of each pixel, thereby the display performance may be improved.

For example, in the embodiment shown inFIGS.9to10, a width of a channel region of each of the first thin film transistor T1and the second thin film transistor T2may be 40 micrometers and a length of thereof may be 4.5 micrometers. The first thin film transistor T1and the second thin film transistor T2connected in series may be regarded as a thin film transistor with a double gate structure. An aspect ratio of the channel of the thin film transistor with the double gate structure may be 40/(4.5+4.5). Under conditions of a same pixel size and a same thin film transistor size, the opening ratio of the pixel may be increased to 84.46%. It may be seen that the opening ratio may be further improved significantly.

It should be noted that, in this embodiment, an on-state current Ion of the thin film transistor is slightly increased compared to the on-state current Ion of the thin film transistor in the embodiment shown inFIGS.4to6A; an off-state current Ioff of the thin film transistor in this embodiment increases significantly compared to the off-state current Ioff of the thin film transistor in the embodiment shown inFIGS.4to6A.

FIG.11is a cross-sectional view taken along line BB′ inFIG.4according to some exemplary embodiments of the present disclosure, andFIG.12is a cross-sectional view taken along line CC′ inFIG.4according to some exemplary embodiments of the present disclosure. It should be noted that, in order to clearly illustrate a relative positional relationship between the first conductive layer, the active layer, the second conductive layer and the pixel conductive layer, some other layers are omitted inFIGS.11and12.

With reference toFIGS.4to6AandFIGS.11and12, the pixel electrode90and the common electrode80are disposed in each pixel P, wherein the pixel electrode90includes the gate conductive layer24and the pixel conductive layer70.

In a Z direction perpendicular to the base substrate10, the common electrode80is disposed between the gate conductive layer24and the pixel conductive layer70. In this way, a capacitance is formed between the pixel conductive layer70and the common electrode80, and between the gate conductive layer24and the common electrode80, so that a capacitance value of a storage capacitor Cst may be increased. In this way, a holding time of the electronic paper display device during display may be increased. It should be understood that, for the electronic paper display device, a display time is relatively long, so it is required to have a relatively long holding time during display. In the embodiments of the present disclosure, by disposing such the structure, the display device may have a relatively long holding time, which is beneficial to improve the display performance.

In each pixel P, the area of the pixel conductive layer70is set to be the largest. That is, the orthographic projection of the pixel conductive layer70on the base substrate10covers the orthographic projection of each of the gate conductive layer24and the common electrode80on the base substrate10. Because the coverage area of the pixel conductive layer70determines the opening ratio of pixel, the opening ratio of pixel may be increased in this way.

In each pixel P, an area of the gate conductive layer24is smaller than the area of the pixel conductive layer70and is greater than an area of the common electrode80. That is, the orthographic projection of the gate conductive layer24on the base substrate10falls within the orthographic projection of the pixel conductive layer70on the base substrate10, and covers the orthographic projection of the common electrode80on the base substrate10. The area of the gate conductive layer24is associated with the capacitance value of the storage capacitor Cst. Through such arrangement, a designed value of the capacitance value of the storage capacitor Cst may be better matched. In addition, by setting the area of the gate conductive layer24to be greater than the area of the common electrode80, ESD (ie, electrostatic discharging) may be avoided, thereby product yield may be improved.

In the exemplary embodiments, in each pixel P, a side surface of the common electrode80is retracted inwardly in the X direction (that is, in a direction away from the data line DL) relative to a side surface of the pixel conductive layer70by a distance d5. For example, the d5may be about 12.5 micrometers. A side surface of the common electrode80is retracted inwardly in the X direction (that is, in a direction away from the data line DL) relative to a side surface of the gate conductive layer24by a distance d4. For example, the d4may be about 5.35 micrometers. Another side surface of the common electrode80is retracted inwardly in the Y direction (that is, in a direction away from the gate line GL) relative to another side surface of the pixel conductive layer70by a distance d8. For example, the d8may be about 12.6 micrometers. Another side surface of the common electrode80is retracted inwardly in the Y direction (that is, in a direction away from the gate line GL) relative to another side surface of the gate conductive layer24by a distance d7, and the d7may be about 5.35 micrometers.

In two adjacent pixels P, pixel conductive layers70of the pixel electrodes90are disposed at an interval with each other, and a distance between the pixel conductive layers70is set as small as possible, as long as a crosstalk between adjacent pixels may be avoided. For example, in the exemplary embodiments, pixel conductive layers70in two adjacent pixels P are disposed at a distance d6in the row direction X and are disposed at a distance d9in the column direction Y. For example, each of the d6and d9may be about 14 micrometers. Through such arrangement, under a premise of avoiding crosstalk between adjacent pixels, the coverage area of each pixel electrode may be made as large as possible, so that the opening ratio of pixel may be increased as much as possible. In addition, through such arrangement, the d6may be made larger than a width of the data line DL in the row direction X, and the d9may be made larger than a width of the gate line GL in the row direction X.

In two adjacent pixels P, common electrodes80are electrically connected to each other by the common electrode line CL extending in the Y direction.

FIG.13is a schematic plan view of a pixel included in a display substrate according to some exemplary embodiments of the present disclosure.FIG.14is a schematic plan view of a pixel conductive layer included in the display substrate inFIG.13.FIG.15is a partial enlarged view of part I inFIG.13. The following will mainly describe differences between the embodiment shown inFIG.13,FIG.14, andFIG.15relative to the above-mentioned various embodiments, and other similarities may refer to the above descriptions.

Referring toFIGS.13-15in combination, a pixel conductive layer70may include a body portion701, a first protrusion portion702extending from the body portion701and a second protrusion portion705extending from the body portion. The first protrusion701extends in a column direction Y, the second protrusion705extends in a row direction X, the first protrusion702and the second protrusion705are connected to each other, so that the pixel conductive layer70includes a first opening71and a second opening72. A first thin film transistor T1and a second thin film transistor T2respectively includes channel regions CH1, CH2in an active layer40, the first opening71exposes the channel region CH1of the first thin film transistor T1, and the second opening72exposes the channel region CH2of the second thin film transistor T2.

For example, the display substrate may include a first gate protrusion G1and a second gate protrusion G2extending from a gate line GL, an overlapping area between the first gate protrusion G1and the active layer40of the first thin film transistor forms a gate electrode T1G of the first thin film transistor, and an overlapping area between the second gate protrusion G2and the active layer40of the second thin film transistor forms a gate electrode T2G of the second thin film transistor.

For example, an orthographic projection of a combination of a second electrode (such as a source electrode T1S) of the first thin film transistor and a first electrode (such as a drain electrode T2D) of the second thin film transistor on the base substrate at least partially overlaps with an orthographic projection of the first gate protrusion G1on the base substrate, an orthographic projection of the first protrusion702on the base substrate and an orthographic projection of the channel region CH1of the first thin film transistor T1on the base substrate are disposed at an interval, and the orthographic projection of the first protrusion702on the base substrate and an orthographic projection of the channel region CH2of the second thin film transistor T2on the base substrate are disposed at an interval.

For example, the orthographic projection of the first gate protrusion G1on the base substrate at least partially overlaps with an orthographic projection of the second protrusion705on the base substrate. For example, the orthographic projection of the first gate protrusion G1on the base substrate intersects with the orthographic projection of the second protrusion705on the base substrate.

For example, an orthographic projection of the second gate protrusion G2on the base substrate at least partially overlaps with the orthographic projection of the second protrusion705on the base substrate. For example, the orthographic projection of the second gate protrusion G2on the base substrate intersects with the orthographic projection of the second protrusion705on the base substrate.

FIG.16is a schematic plan view of a pixel included in a display substrate according to some exemplary embodiments of the present disclosure.FIG.17is a schematic plan view of the pixel conductive layer included in the display substrate inFIG.16. Optionally, referring toFIGS.16and17, an orthographic projection of a second gate protrusion G2on the base substrate does not overlap with an orthographic projection of a second protrusion705on the base substrate. That is, the second protrusion705does not extend to a position overlapping the second gate protrusion G2.

Referring toFIGS.13to17, the orthographic projection of the second protrusion705on the base substrate and an orthographic projection of a channel region CH1of a first thin film transistor on the base substrate are disposed at an interval, and the orthographic projection of the second protrusion705on the base substrate and an orthographic projection of a channel region CH2of a second thin film transistor on the base substrate are disposed at an interval.

For example, an orthographic projection of a pixel conductive layer70of a pixel electrode on the base substrate and an orthographic projection of a second electrode of the second thin film transistor (for example, T2S) on the base substrate are disposed at an interval.

For example, the orthographic projection of the pixel conductive layer70of the pixel electrode on the base substrate and an orthographic projection of each of gate line GL and data line DL on the base substrate are disposed at an interval.

In the above embodiment, by designing a digging pixel conductive layer70, an opening ratio of the pixel may be effectively increased, while the digging pixel conductive layer70does not overlap with the channel region and gate electrode of the thin film transistor, which may avoid adverse effects on the performance of the thin film transistor.

For example, a distance (for example, as shown in d11inFIG.15) between the orthographic projection of the first protrusion702on the base substrate and an orthographic projection of each of the channel regions CH1and CH2of the first thin film transistor and the second thin film transistor on the base substrate in the row direction X is 1 to 3 micrometers.

For example, a distance (for example, as shown in d12inFIG.15) between the orthographic projection of the second protrusion705on the base substrate and the orthographic projection of the gate line GL on the base substrate in the column direction Y is 0.01 to 3 micrometers.

For example, a distance (for example, as shown in d13inFIG.15) between an orthographic projection of the body portion701on the base substrate and the orthographic projection of the data line DL on the base substrate in the row direction X is 0.01 to 3 micrometers. In the embodiments of the present disclosure, the orthographic projection of the pixel conductive layer70of the pixel electrode on the base substrate and the orthographic projection of data line DL on the base substrate are disposed at an interval, that is, the pixel conductive layer70of the pixel electrode does not overlap with the data line DL, so as to prevent generation of a coupling capacitor between the pixel conductive layer70and the data line DL. In this way, it is possible to prevent an on-state current Ion of the thin film transistor from being reduced, thereby facilitating charging of the pixel.

In the above embodiments, the orthographic projection of the pixel conductive layer70of the pixel electrode on the base substrate and the orthographic projection of each of the gate line GL and the data line DL on the base substrate are disposed at an interval, and the interval is set to be relatively small. In this way, on one hand, the coverage area of the pixel conductive layer70may be effectively increased, thereby helping to increase the opening ratio of pixel; on the other hand, the generation of the coupling capacitance may be avoided, and the adverse effect on the performance of the device may be reduced.

Some exemplary embodiments of the present disclosure also provide a display device. Referring toFIG.6B, the display device may include the above-mentioned display substrate. The display device may also include the electronic ink layer100, the electronic ink layer100may be disposed on the side of the pixel conductive layer70away from the base substrate10. For example, the electronic ink layer100may be disposed on the counter substrate110. For example, the electronic ink layer100and the counter substrate110may adopt a paper film structure known in the art, which will not be repeated here.

It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and the advantages of the above-mentioned display substrate, and these features and advantages may be referred to the above descriptions of the display substrate, which will not be repeated here.

FIG.18is a flowchart of a method for manufacturing a display substrate according to some exemplary embodiments of the present disclosure. Referring toFIG.18, the method for manufacturing the display substrate may include five patterning processes. For example, the method may include following steps S101to S106.

In step S101, a first conductive layer20is formed on a base substrate10. For example, a gate metal material layer may be formed on the base substrate10, and the first conductive layer20including a first gate electrode T1G of a first thin film transistor T1, a second gate electrode T2G of a second thin film transistor T2, a gate line GL and a gate conductive layer24is formed through a first patterning process.

In step S102, a gate insulating layer30is formed on a side of the first conductive layer20away from the base substrate10. The gate insulating layer30may cover the base substrate. Specifically, an orthographic projection of the gate insulating layer30on the base substrate10covers an orthographic projection of each of the first gate electrode T1G of the first thin film transistor T1, the second gate electrode T2G of the second thin film transistor T2, the gate line GL and the gate conductive layer24on the base substrate10.

In step S103, an active layer40is formed on a side of the gate insulating layer30away from the base substrate10. For example, a semiconductor material layer may be formed on the side of the gate insulating layer30away from the base substrate10, and then the active layer40may be formed through a second patterning process.

In step S104, a second conductive layer50is formed on a side of the active layer40away from the base substrate10. For example, a source and drain metal material layer may be formed on the side of the active layer40away from the base substrate10, and the second conductive layer50including a first source electrode T1S and a first drain electrode T1D of the first thin film transistor T1, a second source electrode T2S and a second drain electrode T2D of the second thin film transistor T2, a data line DL, a common electrode line CL and a common electrode80is formed through a third patterning process.

In step S105, a passivation layer60is formed on a side of the second conductive layer50away from the base substrate10. For example, an insulating material layer may be formed on the side of the second conductive layer50away from the base substrate10, and the passivation layer60including via holes601and602is formed through a fourth patterning process.

In step S106, a pixel conductive layer70is formed on a side of the passivation layer60away from the base substrate10. For example, a transparent conductive material (such as ITO) layer may be formed on the side of the passivation layer60away from the base substrate10, and the pixel conductive layer70is formed through a fifth patterning process.

The pattern of the pixel conductive layer70may refer toFIG.5,FIG.7,FIG.9,FIG.15andFIG.17.

FIG.19is a flowchart of a method for manufacturing a display substrate according to some exemplary embodiments of the present disclosure. Referring toFIG.19, the method for manufacturing the display substrate may include 4 patterning processes. For example, the method may include following steps S201to S205.

In step S201, a first conductive layer20is formed on a base substrate10. For example, a gate metal material layer may be formed on the base substrate10, and the first conductive layer20including a first gate electrode T1G of a first thin film transistor T1, a second gate electrode T2G of a second thin film transistor T2, a gate line GL and a gate conductive layer24is formed through a first patterning process.

In step S202, a gate insulating layer30is formed on a side of the first conductive layer20away from the base substrate10. The gate insulating layer30may cover the base substrate. Specifically, an orthographic projection of the gate insulating layer30on the base substrate10covers an orthographic projection of each of the first gate electrode T1G of the first thin film transistor T1, the second gate electrode T2G of the second thin film transistor T2, the gate line GL and the gate conductive layer24on the base substrate10.

In step S203, an active layer40and a second conductive layer50are formed on a side of the gate insulating layer30away from the base substrate10through a patterning process (that is, a second patterning process).

Specifically, step S203may be performed according to following steps.

As shown inFIG.20A, a semiconductor material layer40′ and a source and drain metal material layer50′ may be sequentially formed on the side of the gate insulating layer30away from the base substrate10, and a photoresist50″ is coated on the source and drain metal material layer50′.

As shown inFIG.20B, the photoresist50″ is exposed through a halftone mask150to form an unexposed area P1, a semi-exposed area P2and a fully exposed area P3. The unexposed area P1corresponds to the second conductive layer50to be formed including a first source electrode T1S and a first drain electrode T1D of the first thin film transistor T1, a second source electrode T2S and a second drain electrode T2D of the second thin film transistor T2, a data line DL, a common electrode line CL and a common electrode80, The semi-exposed area P2corresponds to a part of the active layer40to be formed which does not overlap with the second conductive layer50, and the fully exposed area P3corresponds to the rest of the base substrate10. In other words, an orthographic projection of the unexposed area P1on the base substrate10overlaps with an orthographic projection of the second conductive layer50to be formed on the base substrate10; an orthographic projection of the semi-exposed area P2on the base substrate10falls within an orthographic projection of the active layer40to be formed on the base substrate10, and the orthographic projection of the semi-exposed area P2on the base substrate10does not overlap with the orthographic projection of the second conductive layer50to be formed on the base substrate10; an orthographic projection of the fully exposed area P3on the base substrate10does not overlap with orthographic projections of the active layer40to be formed and the second conductive layer50to be formed on the base substrate10.

As shown inFIG.20C, the photoresist50″ is developed, the photoresist in the unexposed area P1is completely retained, the photoresist in the semi-exposed area P2is partially removed, and a photoresist in the fully exposed area P3is completely removed.

As shown inFIG.20D, a part of the semiconductor material layer40′ and the source and drain metal material layer50′ that are located in the fully exposed area P3are removed thorough an etching process.

As shown inFIG.20E, the photoresist50″ is ashed to remove all the photoresist in the semi-exposed area P2and part of the photoresist in the unexposed area P1, and the part of the source and drain metal material layer50′ located in the semi-exposed area P2is removed through an etching process.

As shown inFIG.20F, the photoresist in the unexposed area P1is completely removed.

In this way, by using the halftone mask, the active layer40and the second conductive layer50may be formed by a patterning process, so that a patterning process may be saved.

In step S204, a passivation layer60is formed on a side of the second conductive layer50away from the base substrate10. For example, an insulating material layer may be formed on the side of the second conductive layer50away from the base substrate10, and the passivation layer60including via holes601and602may be formed through a third patterning process.

In step S205, a pixel conductive layer70is formed on a side of the passivation layer60away from the base substrate10. For example, a transparent conductive material (such as ITO) layer may be formed on the side of the passivation layer60away from the base substrate10, and the pixel conductive layer70may be formed through a fourth patterning process.

The pattern of the pixel conductive layer70may refer toFIG.5,FIG.7,FIG.9,FIG.15andFIG.17.

It should be noted that some steps of the above manufacturing method may be performed individually or in combination, and may be performed in parallel or sequentially, and are not limited to the specific operation sequence shown in the drawings.

It should be understood that the method for manufacturing the display substrate according to some exemplary embodiments of the present disclosure has all the characteristics and the advantages of the above-mentioned display substrate, and these characteristics and advantages may be referred to the above descriptions of the display substrate, which will not be repeated here.

As used herein, the terms “substantially”, “about”, “approximately” and other similar terms are used as approximate terms rather than as terms of degree, and the terms are intended to explain an inherent deviation of measured or calculated values recognized by those skilled in the art. Taking into account factors such as process fluctuations, measurement problems and errors associated with the measurement of specific quantities (i.e, limitations of the measurement system), the terms “about” or “approximately” used herein includes the stated value, and means that a specific value determined by those skilled in the art is within an acceptable range of deviation. For example, “about” may refer to be within one or more standard deviations, or may be within ±10% or ±5% of the stated value.

Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, those skilled in the art will understand that, changes may be made to the embodiments without departing from the principle and spirit of the general inventive concept of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.