Patent ID: 12243581

DETAILED DESCRIPTION

Aspects of the present disclosure relate to an output driver level-shifting latch circuit for dual-rail memory.

Embodiments described herein enable a Q output level-shifting circuit with integrated latch function for dual-rail design that operates over two logic stages as a two stage system. The integrated level-shifting and latch design uses parallel output driver and hold transistor paths to bypass a serial level-shifting delay associated with dual-rail memories. This solution overall provides a four-stage delay from sense amplifier enable (SAE) to output Q, which is equal to that of single-rail designs.

Dual-rail memory systems introduce additional stage delays relative to a single-rail memory system that uses four stages. To have all memories in a SoC functioning the same, it is desirable to reduce the stage delays of the dual-rail system to match the single-rail system in all memories provided on a SoC.

Embodiments herein describe a dual-rail memory system that has four stages like a single-rail memory. To accomplish providing a four-stage system the dual-rail memory system described herein introduces a level-shifter and hold circuit to transition between the higher VDDA power rail of the memory system to the lower VDDP power rail used for the remaining circuit. The bit-cell read sense amplifier used in the dual-rail memory can substantially the same as a sense amplifier of a single rail system. However, an inverter circuit connects the sense amplifier to provide complementary outputs QT and QB that pulsed and provided to the level shifter and hold circuit to enable the level shifter and hold circuit to function to provide the system output Q based on the complementary signals QT and QB in only two additional stages.

Advantages of the level shifter and hold circuitry enable the dual-rail memory system to operate at the four-stage delay of a single-rail memory. Internal components of the level shifter and hold circuit include latches to hold the state of the complementary signals QT and QB after one of them pulses to change the state of the output Q, as well as to hold the state of Q. Pull-up and pull-down transistors function to transition the voltage levels from VDDA to VDDP quickly without suffering a level shifting and hold delay that might cause the system to provide a delay of more than 4 stages.

FIG.1shows a block diagram of components making up a dual-rail memory instance in a System on a Chip (SoC). The SoC100shown includes logic102operating at a voltage rail VDDP. The SoC also includes a dual-rail memory104which operates at a higher voltage rail VDDA to enable writing to the dual-rail memory104. In one example, the VDDP voltage is 0.4 Volts while VDDA is 1.2 Volts. The memory104is therefore a dual-rail memory with instance circuitry that transitions from the higher VDDA voltage of the memory to a lower voltage VDDP of the logic circuitry102when providing the memory state to the logic circuitry102. The dual-rail memory104also translates voltages from other circuitry of the SoC100, such as the clock which operates at the lower VDDP voltage, to the higher VDDA voltage of the memory104. A level shifter112provides a circuit to convert the system clock of the SoC which operates at VDDP to a clock signal that operates at the higher voltage VDDA of the memory circuitry.

The dual-rail memory104shown inFIG.1, therefore includes first circuitry operating at a voltage VDDA including the memory bit cells106(bitcell array) and sense amplifiers108that detect the state of the bit cells106. Further circuitry operating at VDDA includes the input clock buffer110(input CLK buffer) that clocks operations to read and write from the bit cells106and to operate the sense amplifiers108.

The dual-rail memory104also includes circuitry to translate between the voltage VDDP of the SoC100and the higher VDDA voltage of memory104. First, the level-shifter112includes circuitry to translate the clock of the SoC100operating at VDDP to the higher VDDA voltage of memory104. Further, another level-shifter circuit114(level-shifter) is included in the memory104to translate the sense amplifiers108which operate at VDDA to the lower voltage VDDP of the logic102on the SoC100. Embodiments described herein provide circuitry for such a sense amplifier with a goal to reduce stage delays of dual-rail systems so that all memory systems in a SoC operate with a common number of stages.

FIG.2shows circuitry for a single-rail memory design200that includes four stages. The single-rail system ofFIG.2is shown and described to illustrate that a single-rail system operates with four stages, and includes some components that are carried over to similar circuit components in a dual-rail system. The goal of embodiments of a dual-rail system described herein is to provide similar stage delays in all memories of a SoC, so it is desirable to maintain four stages in dual-rail memory systems to match the single-rail four stage delay. The single rail design shown inFIG.2operates with both the memory and other components of the circuit all operating at a lower voltage VDDP.FIG.2provides a reference to show a desired number of stages that are used to sense the state of a bit cell and provide the output to components of a SoC. The symbol #followed by a number denotes the separate stages of the single rail design200.

InFIG.2, the first stage is a sense amplifier202. The sense amplifier includes two PMOS pull-up transistors connected in a latch configuration to the rail voltage VDDP and two NMOS pull-down transistors connecting to the system supply (VSS) also connected in a latch configuration. The connection to VSS is through an enabling transistor connected to the sense amplifier enable (SAE) signal.

A second stage inFIG.2is provided by inverter204. The inverter204receives the sense amplifier output (XB). Inverter204has power provided from the VDDP rail voltage.

A third stage inFIG.2is another logic stage206. The logic stage206includes two stacked PMOS transistors for connecting to the rail voltage VDDP. The upper PMOS transistor has a gate controlled by the inverse of the SAE signal, which is SAEB. The lower PMOS transistor has a gate controlled by the output (XT) of the sense amplifier202. The third stage also includes an NMOS pull-down transistor connected to VSS and a gate input driven by the output of the stage two inverter204.

A fourth stage inFIG.2is another inverter208that has power provided from the VDDP voltage rail. The output of the fourth stage is the overall output (Q) of the system. The four stages provided inFIG.2are provided in a single rail design.

FIG.3shows circuitry for a dual-rail memory design that uses six stages, or two additional stages relative to the single rail design ofFIG.2. Specifically,FIG.3includes the dual-rail memory300that includes a first stage having the sense amplifier302that includes similar circuitry to the sense amplifier202of the single rail design. The second stage304is an inverter buffer similar to the inverter204of the single rail design. The third stage is another logic stage306similar to the second logic stage206of the single rail design ofFIG.2, except the logic stage306of dual-rail design connects to the higher voltage rail VDDA of the memory instead of the lower rail VDDP used in a single rail design ofFIG.2. The dual-rail design ofFIG.3next introduces a level-shifter308for shifting from the higher voltage rail VDDA of the memory to a lower voltage VDDA for other SoC circuitry separate from the memory. The level shifter308that provides two stages of latency or delay. The dual-rail circuit ofFIG.3next includes an inverter310in stage6, which is similar to single rail inverter308ofFIG.2.

The dual-rail high speed register ofFIG.3requires an additional 2-stage delays of the level shifter308relative to the four stage delay of the single-rail system ofFIG.2to change the LQB output signal at the output of the inverter306operating at the VDDA power rail to provide an input to the final inverter310which operates at the VDDP power rail. It is noted that the total number of logic stages from SAE to Q changes from 4 to 6. Further the full clock to Q path increases from 10 stage delays to 12 stage delays in the dual-rail design due to the number of stages of system that require proper operation. A problem with the dual-rail design ofFIG.3is these added stages which do not match with a single-rail system like that shown inFIG.2.

FIG.4shows circuitry400for an improved dual-rail memory design with four stages according to embodiments. The first stage of the dual-rail circuitry400ofFIG.4includes a sense amplifier402. The circuitry of the sense amplifier is similar to the dual-rail sense amplifier302ofFIG.3and operates at the higher rail voltage VDDA associated with a memory bit cell.

Outputs of the sense amplifier402, XT and the inverse XB, are provided to a second stage inversion circuit404that has circuitry that is different than the dual-rail memory design ofFIG.3. The inversion circuit404includes a PMOS transistor406connecting to the higher VDDA power rail with control received from the sense amplifier enable SAE. The PMOS transistor406provides power to two inverters408and410that (i) receive the outputs XB and XT from the sense amplifier402and (ii) provide outputs QB and QT.

The final two stages ofFIG.4are provided by the level-shifting latch circuit412. The level-shifting latch412converts from the higher memory VDDA power rail to the VDDP power rail. The level-shifting latch412receives the inputs QB and QT from the inversion circuit404and provides an output Q from the dual-rail circuit400.

FIG.5shows specific circuitry for the level-shifting latch412ofFIG.4. The circuit first includes parallel connected stacked PMOS pull-up transistors502,504and506,508. The upper PMOS pull-up transistors502and506connect the lower VDDP voltage rail to the top end of lower PMOS pull-up transistors504and508and have gates connected in a latch configuration to respective ones of the bottom of lower PMOS pull-up transistors504and508. The gate of lower PMOS pull-up transistor504receives the QT output from the inverter circuit404operating at the voltage rail VDDA. The gate of lower PMOS pull-up transistor508receives the QB output from the inverter circuit404.

The circuit ofFIG.5further includes parallel NMOS pull-down transistors510and512that connect to LQ and LQB, respectively. Gates of the parallel NMOS pull-down transistors510and512are connected to the respective outputs QT and QB of the inverter circuit404.

A combination of the stacked PMOS transistors502,504and506,508along with the NMOS pull-down transistors510and512functionally form a level shifter circuit. QT and QB which drive the level shifter circuit are pulsed signals that have voltages at the VDDA level. Because QT and QB are pulsed, a latch circuitry is implemented to hold the outputs LQ and LQB signal state of the level shifter circuit after the QT and QB signals are pulsed so that the output Q will maintain the same state after the QT and QB signal returns to 0 after pulsing. The output LQ is provided at the junction of lower PMOS transistor508and NMOS transistor512. The output LQB is provided at the junction of lower PMOS transistor504and NMOS transistor510.

The NMOS pull-down transistors514and516form the latch to hold the state of LQB and LQ after QT and QB are pulsed. The NMOS pull-down transistors514and516have gates cross connected in a latch configuration. The NMOS pull-down transistor514connects LQ to VSS and NMOS transistor516connects LQB to VSS.

The output Q of the level-shifting latch406is driven by stacked PMOS pull-up transistors518and520, NMOS driver532and NMOS hold transistor530. The upper PMOS pull-up transistor518connects VDDP to the output Q through lower PMOS transistor520, and the upper PMOS transistor518and has a gate driven by QT. The lower PMOS transistor has a gate driven by LQB. The NMOS hold transistor530connects the output Q to VSS and has a gate driven by LQB. The NMOS driver transistor532connects the output Q to VSS and has a gate connected to QT.

In operation, first a read one operation is considered when QB pulses high to a 1 to transition Q to 1. Initially after QB pulses to a 1, LQB is driven low and Q then transitions to 1. LQ transitions to VDDP to break feedback from the LQB output. LQB is kept at 0 when QB returns to 0 after pulsing as latched by the NMOS latch connected transistors514and516. In summary for the read one operation, QB rises to a 1 which forces LQB low, and this in turn drives Q to 1.

In operation with a read zero operation QT pulses high to a 1, the level shifter circuit delay is bypassed, and the output Q is transitioned to 0. First, with QT pulsing high, the NMOS driver transistor532forces Q to 0. The upper PMOS pull-up transistor518with an input of QT breaks the path to VDDP to allow the NMOS driver transistor to pull Q to 0. LQB transitions to VDDP after two gate delays to enable hold transistor530to keep Q at 0. After QT pulsing is complete, QT returns to 0, but Q is held at 0 by NMOS hold transistor532.

In summary for the read zero operation, the QT rising edge forces Q to 0 and level-shifter delay is bypassed. LQB rises after level-shifter delay to hold a 0 value on Q before the QT pulse resets.

Experimental timing results were performed using the dual-rail memory system ofFIG.3and the dual-rail memory system ofFIGS.4-5. In the design ofFIG.3the transition of the output Q to 0 after the SAE signal took 33.8 ps, while the transition of Q to 1 took 26.3 ps. In the design ofFIGS.4-5the transition of the output Q to 0 after the SAE signal took 24.2 ps, while the transition of Q to 1 took 24.4 ps. Thus, the system ofFIGS.4-5shows a significant time reduction.

FIG.6provides a graph600showing the results using the circuit ofFIGS.4-5when the VDDP and VDDA voltages are reversed and VDDA is now the low voltage. The top waveform diagram shows functionality for a maximum forward split in a normal configuration with VDDA being the higher voltage. The bottom diagram shows functionality for a maximum reverse split with VDDP now being the higher voltage. The graph ofFIG.6shows the resiliency of the system should be voltages VDDP and VDDA operate in a reverse split configuration, as the circuit components will still function without damage to the system.

Circuitry described in portions of the preceding detailed descriptions is controlled in some embodiments by processors which operate in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

In the foregoing disclosure, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of implementations of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular tense, more than one element can be depicted in the figures and like elements are labeled with like numerals. The disclosure and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.