Patent ID: 12211865

DESCRIPTION

This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended semiconductor packages will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such semiconductor packages and implementing components and methods, consistent with the intended operation and methods.

Referring toFIG.1, a semiconductor package is illustrated2. The semiconductor package includes a digital signal processor4having a first side and a second side and an image sensor array6having a first side and a second side. The second side of the digital signal processor4is coupled to the first side of the image sensor array6through a hybrid bond interconnect (HBI) process. The HBI process uses a hybrid bond, the hybrid bond including conductive bonds between conductor regions (HBI bond pads) of two wafers and hybrid bonds between insulator regions of two wafers. The hybrid bonding allows for electrical connections to be formed and forms a mechanically stable structure between the two wafers. In some implementations, the HBI bond pads may be metal such as copper, nickel, gold, or other suitable metals known in the art. In other implementations, the HBI bond pads may be made of other non-metal conductive material. In this particular implementation, the HBI bond pads are copper (Cu) forming Cu—Cu bonds between the two wafers4and6and oxide-oxide bonds formed between the wafer material. The insulator regions of the wafer may include silicon dioxide (SiO2), other suitable dielectric materials, or a combination thereof.

The first side of the image sensor array6is coupled to the second side of the digital signal processor4through a plurality of HBI bond pads8and an edge seal10. The edge seal10, in this implementation, includes a first metal stack12within the digital signal processor4bonded to a second metal stack14within in the image sensor array6. The first metal stack12is bonded to the second metal stack14through HBI bonding pads16. In this particular implementation, a first opening18is formed to the right of the edge seal10. In various implementations, semiconductor packages may have one or more first openings18. In the implementation illustrated, the first opening18extends from the second side of the image sensor array6to the second side of the digital signal processor4. The first opening18extends to/into the etch stop layer20in the second side of the digital signal processor4. In various implementations, the first opening18may be coated with a sealing material22and may form a second edge seal between the plurality of HBI bond pads8and the edge seal10. In this implementation, the semiconductor package is coated with an anti-reflective coating24. The anti-reflective coating24may be the same material as the sealing material22. In various implementations, the sealing material may include one of oxynitride (ONO), silicon nitride (SiN), aluminum nitride (AlN), any combination thereof, or any other suitable material known disclosed herein or known in the art for sealing a semiconductor opening's sidewalls. In other implementations, the one or more first openings may be positioned between the active area of the semiconductor package and the edge seal10. In still other implementations, the one or more first openings may also be positioned between the edge seal10and the edge of the semiconductor package as shown inFIG.1.

Referring toFIG.2, a top view of four semiconductor packages2is illustrated. This view shows a portion of a pre-singulated image sensor array wafer28having four discrete digital signal processor chips30bonded thereto forming four semiconductor packages2. As a final step of manufacturing all material in the saw street intersection32is removed during singulation via sawing.

As previously described, hybrid bonding allows for formation of three dimensional (3D) structures with a fine pitch (<10 μm). However, the layout of the HBI bond pads is very restrictive as conventionally a uniform array of vias is required across both wafers to ensure that the copper (or other metal) height is well controlled. For example, too much dishing in high pattern density regions can cause incomplete bonding. In conventional HBI bond pad layouts, there may be gaps in the edge seal ring that may allow moisture to diffuse into the active region of the die causing oxidation of Cu vias and reliability failures of the device. Referring back toFIG.2, the one or more first openings18may be positioned between the plurality of HBI bond pads8and the edge seal10to create a second edge seal for the semiconductor package. The one or more first openings18may be continuous forming a trench-like structure to form a second edge seal. In other implementations, the one or more first openings18may be discrete openings sealing particular areas of the semiconductor packages. As previously described, the second edge seal18may be positioned on the outside the edge seal meaning on the outer edge of the semiconductor package or may be positioned inside the edge seal meaning between the edge seal and the active area of the die.

Referring now toFIG.3, another implementation of a semiconductor package40is illustrated. In this implementation, a second side of a digital signal processor42is electrically and mechanically coupled to a first side of an image sensor array44. The second side of the image sensor array44is coated with an anti-reflective coating (ARC)46. An etch stop layer48is included in the second side of the digital signal processor42. Similar to the implementation previously described, the wafers are bonded through a plurality of HBI bond pads50and an edge seal52. The edge seal52includes a first metal stack54within the digital signal processor42and a second metal stack56within the image sensor array44. In this implementation, one or more first openings58are positioned between the active area of the die and the edge seal52. The one or more first openings58form a second edge seal protecting the active area of the die. In this particular implementation, one or more second openings60extend from the second side of the image sensor array44to the second metal stack56within the image sensor array44forming a third edge seal. The one or more second openings60are coated with a sealing material62therein. The sealing material may include ONO, aluminum oxide (Al2O3), SiN, hafnium dioxide (HfO2), tantalum oxide (Ta2O5), any combination thereof, or any other suitable material disclosed herein or known in the art.

Referring toFIG.4, a top view of a semiconductor package64having one or more first openings and one or more second openings is illustrated. In this view, one or more second openings60are shown forming a third edge seal next to/adjacent to the edge seal formed by the metal stacks as described above. In this particular implementation, the second edge seal58formed by the one or more first openings is located between the edge seal52and the active area of the die. In additional implementations, one or more third openings may extend into the second side of the image sensor array to the etch stop layer in the digital signal processor forming a fourth edge seal. The one or more third openings may be positioned inside (on the active region side) or outside (on the scribe line region side) of the edge seal of the semiconductor package.

Referring now toFIG.5, a cross sectional view of an additional implementation of a semiconductor package72is illustrated. A second side of a digital sensor processor74is coupled with a first side of an image sensor array76through a plurality of HBI bond pads78and an edge seal80. A first metal stack82is included within the digital signal processor74and a second metal stack84is included within the image sensor array76. The first metal stack82and the second metal stack84are electrically coupled through a via bar86having a width that is smaller than a width of the plurality of HBI bond pads78. In the implementation illustrated, the width of the via bar86is approximately 25-75% smaller than the width of the HBI bond pads78. The via bar86forms an additional seal88inside the edge seal80. The additional seal88formed by the via bar86may be continuous or it may have spaces therein when viewed from above the via bar86. The via bar may include Cu, nickel, gold, or any suitable material known in the art.

Referring toFIG.6andFIG.7, a top view of the semiconductor package72fromFIG.5is illustrated. The additional seal88formed by the via bar is located inside the edge seal80formed by the metal stacks. Because the additional seal88formed by the via bar is located at the die corner, it may facilitate bonding between the digital signal processor and the image sensor array. Because the corner of the die is bonded all the way around the corner at the via bar, the risk of chipping and other moisture ingress during the sawing process may be reduced. Furthermore, the additional seal88may facilitate local pattern density compensation to control Cu dishing across all Cu interfaces during chemical mechanical polishing (CMP).

In various implementations, the additional seal88may be used in combination with of the one or more first opening implementations and the one or more second opening implementations to form additional edge seals as desired. In other implementations, the additional seal88may be used by itself in wafer bonding implementations disclosed herein, without any of the one or more first opening implementations and/or one or more second opening implementations.

Referring now toFIG.8, another implementation of semiconductor package96is illustrated. A second side of a digital sensor processor98is coupled with a first side of an image sensor array100through a plurality of HBI bond pads102and an edge seal104. A first metal stack106is included within the digital signal processor98and a second metal stack108is included within the image sensor array100. In this implementation, the HBI bonds102are completely separated from the edge seal104. This implementation may reduce stress between the edge seal104and the HBI102. This implementation may be used by itself as a different edge seal implementation or in combination with any of the other previously described opening implementations and/or via bar implementations. A wide variety of possible applications for edge seals like those illustrated inFIG.8may be appreciated by those of ordinary skill in the art.

In places where the description above refers to particular implementations of semiconductor packages and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other semiconductor packages.