Patent ID: 12262562

DETAILED DESCRIPTION

Embodiments of an apparatus, system, and method each including or otherwise related to an image sensor with a varying depth deep trench isolation (DTI) structure are disclosed herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols may be used interchangeably through this document (e.g., Si vs. silicon); however, both have identical meaning.

As pixel control circuitry decreases in size and photodiodes become more closely packed together the influence of electrical and/or optical crosstalk on image sensor performance increases. This is especially true for split photodiode image sensors for high dynamic range applications, in which photodiodes with differing full well capacities are adjacent to one another. For example, high angle light relative to a surface normal may be incident upon a large photodiode and propagate through the large photodiode to reach a neighboring small photodiode as optical crosstalk. This optical crosstalk may degrade the dynamic range performance of the image sensor by degrading signal-to-noise ratio (SNR) and/or color matching performance between small and large photodiodes, which can cause issues in color reproduction after color correction operation (e.g., after color correction matrix processing).

Described herein are embodiments related to an image sensor with a varying depth deep trench isolation (DTI) structure to reduce optical crosstalk and/or electrical crosstalk between at least neighboring photodiodes in a pixel array of the image sensor. The varying depth DTI structure is particularly well suited for, but not limited to, image sensors with a split-pixel layout in which the lateral distance between adjacent photodiodes is not uniform. As the lateral distance between adjacent photodiodes decreases the likelihood that optical and/or electrical crosstalk will occur increases. To compensate for the non-uniform distance between adjacent photodiodes, the varying depth DTI structure described in embodiments herein includes a plurality of segments that may respectively extend different depths through a semiconductor substrate to provide increased optical crosstalk and/or electrical crosstalk mitigation as the lateral distance decreases while still maintaining structural integrity of the semiconductor substrate.

It is appreciated that the term “photodiode” may correspond to a region within the semiconductor substrate that has been doped with an opposite polarity of the semiconductor substrate such that an outer perimeter of the region, herein referred to as a photodiode, forms a PN junction or a PIN junction. For example, an n-doped region disposed within a p-type semiconductor substrate (e.g., a p-type doped silicon wafer) forms a corresponding photodiode. In some embodiments, a given pixel may further include a pinning layer (e.g., a layer or region of the semiconductor substrate disposed between a side of the semiconductor substrate and the photodiode that has a polarity opposite of the semiconductor substrate) to form a pinned photodiode. The pinning layer may be a doped region or layer within the semiconductor substrate or otherwise coupled to the semiconductor substrate that has a polarity opposite of the photodiode (e.g., p-type region when the photodiode is n-type).

It is further appreciated that embodiments described herein associated with a varying depth DTI structure will be discussed in the context of a backside illuminated CMOS image sensor with a split pixel layout including a plurality of small photodiodes and a plurality of large photodiodes (see, e.g.,FIG.1A,FIG.1B,FIG.3A, andFIG.3B). However, it is appreciated that such embodiments are non-limiting and that the varying depth DTI structure may be implemented in other image sensor configurations not explicitly described herein (e.g., pixel layouts other than a split pixel layout, front side illumination, or the like).

FIG.1Aillustrates an example backside view of an image sensor101with a varying depth deep trench isolation structure105for reduced crosstalk, in accordance with the teachings of the present disclosure. As illustrated the image sensor101includes a plurality of small photodiodes111(e.g., first photodiode111-1), a plurality of large photodiodes112(e.g., second photodiode112-2), and a varying depth DTI structure105each disposed within, at least in part, a semiconductor substrate103(e.g., an n-doped silicon substrate, a p-doped silicon substrate, an intrinsic silicon substrate, a bulk silicon substrate, or the like). In some embodiments, one or more small photodiodes included in the plurality of small photodiodes111have a first full well capacity and one or more large photodiodes included in the plurality of large photodiodes112have a second full well capacity that is greater than the first full well capacity. Additionally, in some embodiments, each of the plurality of large photodiodes112may have a greater physical dimension (e.g., length, width, depth, area, or the like) relative to each of the plurality of small photodiodes111. In the same or other embodiments, each of the plurality of large photodiodes112may have a greater sensitivity to light or a higher quantum efficiency relative to each of the plurality of small photodiodes111.

As illustrated inFIG.1A, the image sensor101has a split-pixel layout with the plurality of small photodiodes111and the plurality of large photodiodes112arranged in rows and columns to respectively form a first array of the plurality of small photodiodes111and a second array of the plurality of large photodiodes112. In the illustrated embodiment the first array of the plurality of small photodiodes111is interspersed with the second array of the plurality of large photodiodes112such that each individual small photodiode (e.g., the first photodiode111-1) included in the plurality of small photodiodes is laterally surrounded by neighboring large photodiodes included in the plurality of large photodiodes112. In one embodiment, the first array and the second array are each two-by-two arrays, but it is appreciated that any number of photodiodes may be included in the image sensor101. In some embodiments there may be an equal number of photodiodes included in the plurality of small photodiodes111and the plurality of large photodiodes112. In other embodiments there may be a greater number of photodiodes included in the plurality of small photodiodes111relative to plurality of large photodiodes112or vice versa.

In some embodiments, photodiodes included in the plurality of small photodiodes111and the plurality of large photodiodes112are laterally surrounded by a DTI structure105with a varying depth to mitigate optical crosstalk and/or electrical crosstalk between neighboring (e.g., adjacent) photodiodes. The varying depth of the DTI structure105provides increased crosstalk mitigation as the lateral distance between adjacent photodiodes decreases. For example, in the split-pixel layout of image sensor101, each photodiode included in the plurality of small photodiodes111and the plurality of large photodiodes112are disposed proximate to one or more instances of a contiguous portion of the DTI structure105such that a corresponding instance of the contiguous portion of the DTI structure with the varying depth is disposed between each adjacent small-large photodiode pair included in a pixel array formed by the first array of the plurality of small photodiodes111interspersed with the second array of the plurality of large photodiodes112. Accordingly, the instances of the contiguous portion of the DTI structure105may collectively form a DTI grid that individually surrounds each photodiode included in the plurality of small photodiodes111and the plurality of large photodiodes112as illustrated inFIG.1A.

FIG.1Billustrates a zoomed-in view150of the example backside view of the image sensor101shown inFIG.1A, which shows an instance of the contiguous portion of the DTI structure105with the varying depth, in accordance with the teachings of the present disclosure. The zoomed-in view150shows the first photodiode111-1, the second photodiode112-2, and an instance of the contiguous portion of the DTI structure105disposed within the semiconductor substrate103. The first photodiode111-1is disposed adjacent (e.g., neighboring) to the second photodiode112-2with the contiguous portion of the DTI structure105disposed between the first photodiode111-1and the second photodiode112-2. The contiguous portion of the DTI structure105with the varying depth includes a first segment129, a second segment131, and a third segment133. As illustrated, the first segment129is coupled between the second segment131and the third segment133to form the contiguous portion of the DTI structure105with the varying depth, which extends from a first side (e.g., backside of the semiconductor substrate103or illuminated side of the semiconductor substrate103) towards a second side (e.g., front side of the semiconductor substrate103or non-illuminated side of the semiconductor substrate103). The varying depth (see, e.g.,FIG.1C,FIG.1D,FIG.1E, andFIG.1Fin the context ofFIG.1A) includes a first depth of the first segment129, a second depth of the second segment131, and a third depth of the third segment133. In some embodiments, the first depth of the first segment129is greater than the second depth of the second segment131and/or the third depth of the third segment133.

In the illustrated embodiment ofFIG.1B, a distance between the first photodiode111-1and the second photodiode112-2taken along a direction perpendicular to line D-D′ is non-uniform. In some embodiments, a first distance141between the first photodiode111-1and the second photodiode112-2that extends through the first segment129is less than a second distance143between the first photodiode111-1and the second photodiode112-2that extends through the second segment131. In the same or other embodiments the first distance141between the first photodiode111-1and the second photodiode112-2that extends through the first segment129is less than a third distance145between the first photodiode111-1and the second photodiode112-2that extends through the third segment133. In some embodiments, the first distance141, the second distance143, and the third distance145are taken along a substantially common direction (e.g., the direction perpendicular to line D-D′).

As illustrated inFIG.1B, the first photodiode111-1has a first cross-sectional shape115including a first truncated edge121and the second photodiode112-2has a second cross-sectional shape117including a second truncated edge122. Accordingly, in some embodiments the first cross-sectional shape115of the first photodiode111-1and/or the second cross-sectional shape117of the second photodiode112-2correspond to a truncated square, a truncated rectangle, a truncated circle, a squircle, a rounded square, or any other shape to optimize packing density of the plurality of small photodiodes111and the plurality of large photodiodes112. In one embodiment, the first photodiode111-1and the second photodiode112-2are positioned within the semiconductor substrate103such that the first truncated edge121of the first photodiode111-1faces the second truncated edge122of the second photodiode112-2. In some embodiments, the first segment129of the DTI structure105is disposed between the first truncated edge121of the first photodiode111-1and the second truncated edge122of the second photodiode112-2to provide optical and/or electrical isolation between photo-sensing regions of neighboring first photodiode111-1and second photodiode112-2. In the same or other embodiments, the first segment129of the DTI structure105extends a length (e.g., in a direction along the line D-D′) between the first truncated edge121and the second truncated edge122such that at least one of the second segment131or the third segment133is not directly disposed between the first truncated edge121of the first photodiode111-1and the second truncated edge122of the second photodiode112-2.

FIG.1Cillustrates a cross-sectional view of the image sensor101along the line A-A′ shown inFIG.1A, in accordance with the teachings of the present disclosure. In particular,FIG.1Cshows the first photodiode111-1adjacent to the second photodiode112-2and are each disposed within the semiconductor substrate103proximate to a first side107of the semiconductor substrate103.FIG.1Calso shows the first segment129of the contiguous portion of the DTI structure105extending a first depth181from the first side107(e.g., backside) towards a second side (e.g., front side) of the semiconductor substrate103. In some embodiments, the first segment129is formed of at least an oxide material (e.g., silicon dioxide, a high-κ oxide such as hafnium oxide, aluminum oxide, or otherwise). For example, in the illustrated embodiment, the first segment129is formed of a high-κ dielectric shell159that is filled with at least one of an oxide material157(e.g., silicon dioxide) or a metal material (e.g., tungsten or aluminum). In some embodiments, the high-κ dielectric shell159includes one or more material layers. In the same or other embodiments, the high-κ dielectric shell159is approximately 200-600 angstroms thick. It is appreciated that the term “high-κ oxide” generally corresponds to any oxide material having a dielectric constant greater than the dielectric constant of silicon dioxide. In other embodiments, the high-K dielectric shell159may be omitted or replaced with a liner material having a refractive index sufficient to reflect, refract, or otherwise mitigate high angle light from propagating through the first segment129between the first photodiode111-1and the second photodiode112-2. In some embodiments the high-κ dielectric shell159, the liner material, and/or the oxide material157may correspond to any dielectric material having an index of refraction lower than an index of refraction of the semiconductor substrate103(e.g., silicon substrate) to induce reflection (e.g., total internal reflection to prevent or otherwise reduce optical crosstalk and mitigate light from propagating from an incident photodiode to an adjacent photodiode).

As illustrated inFIG.1C, the image sensor103further includes a shallow trench isolation (STI) structure155disposed proximate to the second side109(e.g., front side) of the semiconductor substrate103between the first photodiode111-1and the second photodiode112-2. In some embodiments, the shallow trench isolation structure155extends a depth from the second side109(e.g., front side) of the semiconductor substrate103toward the first side107(e.g., backside) of the semiconductor substrate103. In some embodiments, the first segment129of the DTI structure105directly contacts a surface (e.g., a bottom surface) of the STI structure155such that an isolation barrier extends continuously from the first side107to the second side109to mitigate optical crosstalk and/or electrical crosstalk between the first photodiode111-1and the second photodiode112-2. In some embodiments, the first segment129of the DTI structure105extends and is structurally connected with the STI structure155. In one embodiment, the first segment129extends into the STI structure155such that a distal end of the first segment129is at least partially surrounded by the STI structure155. In the same or other embodiments, a width of the first segment129extending between the first photodiode111-1and the second photodiode112-2is less than a width of the STI structure155extending between the first photodiode111-1and the second photodiode112-2.

In the illustrated embodiment, the image sensor101further includes a well153disposed in the semiconductor substrate103between the first photodiode111-1and the second photodiode112-2. It is appreciated that the first photodiode111-1and the second photodiode112-2each have a first conductivity type (e.g., n-type or p-type) and that the well153has a second conductivity type (e.g., p-type when the first conductive type is n-type or n-type when the first conductivity type is p-type) opposite of the first conductivity type. In some embodiments, the well153and the semiconductor substrate103are of the same conductivity type. In some embodiments, the contiguous portion of the DTI structure105, including the first segment129, the second segment131(see, e.g.,FIG.1D), the third segment133(see, e.g., FID. IE), and the STI structure155are each disposed, at least in part, within or otherwise surrounded by the well153. In some embodiments, the well153is a region of the semiconductor substrate103that has been doped (e.g., via implantation from the second side109) to provide additional isolation extending between the first photodiode111-1and the second photodiode112-2.

As shown inFIG.1C, the first photodiode111-1and the second photodiode112-2are each pinned photodiodes and are coupled to a respective pinning layer151. It is appreciated that the pinning layer151has the second conductivity type opposite of the first conductivity type of the first photodiode111-1and the second photodiode112-2. It is appreciated that while the conductivity type of the semiconductor substrate103, the pinning layer151, and the well153may share a common conductivity type (e.g., n-type or p-type) in some embodiments, the degree of doping is not necessarily equal (e.g., differing in dopant density per unit area, doping profile, or otherwise). For example, the doping concentration of the well153may be greater than the doping concentration of the semiconductor substrate103. It is appreciated that in other embodiments the pinning layer151may be omitted.

FIG.1Dillustrates a cross-sectional view of the image sensor101along the line B-B′ shown inFIG.1A, in accordance with the teachings of the present disclosure.FIG.1Dillustrates many features similar to the view shown inFIG.1C, but corresponds to a view focused on the second segment131of the contiguous portion of the DTI structure105illustrated inFIG.1BandFIG.1A. As illustrated, the second segment131extends a second depth183from the first side107towards the second side109of the semiconductor substrate103. It is appreciated that the second depth183is different from the first depth181. In some embodiments, the first depth181extends deeper into the semiconductor substrate103than the second depth183(see, e.g.,FIG.1D). Additionally, it is appreciated that the STI structure155optionally extends from the second side109under the second segment131such that a portion of the semiconductor substrate103(e.g., a doped portion of the semiconductor substrate103corresponding to a portion of the well153) is disposed between the second segment131and the STI structure155. In other words, the second segment131does not directly contact the STI structure155. In other embodiments the STI structure155may not extend under the second segment131(e.g., the STI structure155is confined proximate to the first segment129illustrated inFIG.1C).

FIG.1Eillustrates a cross-sectional view of the image sensor101along the line C-C′ shown inFIG.1A, in accordance with the teachings of the present disclosure.FIG.1Eillustrates many features similar to the view shown inFIG.1C, but corresponds to a view focused on the third segment133of the contiguous portion of the DTI structure105illustrated inFIG.1BandFIG.1A. As illustrated, the third segment133extends a third depth185from the first side107towards the second side109of the semiconductor substrate103. It is appreciated that the third depth185is different from the first depth181. In some embodiments, the first depth181extends deeper into the semiconductor substrate103than the third depth185(see, e.g.,FIG.1E). In some embodiments the second depth183illustrated inFIG.1Dmay be substantially equal to the third depth185illustrated inFIG.1E. In other embodiments, the second depth183and the third depth185may not be equal. Additionally, it is appreciated that the STI structure155optionally extends under the third segment133such that a portion of the semiconductor substrate103(e.g., a doped portion of the semiconductor substrate103corresponding to a portion of the well153) is disposed between the third segment133and the STI structure155. In other words, the third segment133does not directly contact the STI structure155. In other embodiments the STI structure155may not extend under the third segment133(e.g., the STI structure155is confined proximate to the first segment129illustrated inFIG.1C).

FIG.1Fillustrates a cross-sectional view of the image sensor101along the line D-D′ shown inFIG.1A, in accordance with the teachings of the present disclosure. More specifically,FIG.1Fshows the varying depth of the contiguous portion of the DTI structure105(see, e.g.,FIG.1B), which includes the first depth181of the first segment129, the second depth183of the second segment131, and the third depth185of the third segment133. As illustrated, the first depth181is greater than the second depth183and the third depth185. In the illustrated embodiment, the second depth183is substantially equal to the third depth185. It is appreciated that the difference between the first depth181and the second depth183or the third depth185is equal to an extended distance187, which is achieved via a second etching step (see, e.g.,FIG.2AandFIG.2B). In one embodiment, the second depth183and/or the third depth185is approximately 1.5 μm to 2.5 μm, which may be dependent on a thickness of the semiconductor substrate103(e.g., approximately 3 μm-6 μm) such that there is at least approximately 1 μm from the distal end of the second segment131or the third segment133to the second side109of the semiconductor substrate103. In the same or other embodiments, the extended depth187is less than or equal to the second depth183or the third depth185. In another embodiment, the first depth181is approximately twice the depth as the second depth183or the third depth185. It is appreciated that the term “approximately” corresponds to ±10% of a given value.

In some embodiments, the contiguous portion of the DTI structure105abruptly transitions between the first depth181of the first segment129and the second depth183of the second segment131(e.g., Θ is 90°±5°). In other embodiments, the angle, Θ, between the first segment129and the second segment131is exactly 90°, less than 90°, or greater than 90°. In the same or other embodiments, the contiguous portion of the DTI structure105abruptly transitions between the first depth181of the first segment129and the third depth185of the third segment133such that the angle between the first segment129and the third segment133is 90°±5°. In other embodiments, the angle between the first segment129and the third segment133is exactly 90°, less than 90°, or greater than 90°. In other words, depending on the configuration of the varying depth of the contiguous portion of the DTI structure105, the transition between the different depths (e.g., first depth181and the second depth183or the third depth185) may be a vertical transition, a gradual transition, or otherwise.

As illustrated inFIG.1F, the STI structure155is aligned with the first segment129of the DTI structure105. In some embodiments the STI structure155and the first segment129of the DTI structure105have a substantially equal length (e.g., in a direction parallel to the first side107and/or second side109of the semiconductor substrate103) such that the STI structure155is not disposed between the second segment131of the DTI structure105and the second side109of the semiconductor substrate103. In other embodiments, the STI structure155may optionally extend under the second segment131and/or the third segment133. However, it is noted that in the same embodiment, a portion of the semiconductor substrate103containing the well153is disposed between the second segment131and the optional STI structure155. Similarly, in the same embodiment, a portion of the semiconductor substrate103containing the well153is disposed between the third segment133and the optional STI structure155.

FIGS.2A-2Billustrate an example process200-A and200-B for manufacturing an image sensor with a varying depth DTI structure, in accordance with the teachings of the present disclosure. Process200-A and200-B may be implemented for fabricating the DTI structure105with the varying depth of the image sensor101illustrated inFIGS.1A-1F. It is appreciated that the numbered blocks of process200-A and200-B, including blocks205-230, may occur in any order and even in parallel. Additionally, blocks may be added to, or removed from, process200-A and200-B in accordance with the teachings of the present disclosure.

Block205shows providing a semiconductor substrate having a first side and a second side opposite to the first side and further including a first photodiode and a second photodiode that are each disposed within the semiconductor substrate proximate to the second side (e.g., front side) of the semiconductor substrate. In some embodiments, the first photodiode is adjacent to (e.g., neighboring) the second photodiode. In some embodiments, the first photodiode has a full well capacity lower than the neighboring second photodiode. In the same or other embodiments, the first photodiode has light sensitivity lower than the second photodiode.

Block210illustrates forming a DTI structure within the semiconductor substrate. The DTI structure has a varying depth that extends from the first side (e.g., backside) towards the second side of the semiconductor substrate between the first photodiode and the second photodiode. The DTI structure includes a first segment coupled or structurally connected between a second segment and a third segment that collectively form a contiguous portion of the DTI structure with the varying depth. The varying depth of the contiguous portion of the DTI structure includes a first depth of the first segment, a second depth of the second segment, and a third depth of the third segment. In some embodiments, the first depth is greater than the second depth and the third depth.

Blocks215-230illustrated inFIG.2Bshow process200-B, which is a subprocess of process200-A and particularly focuses on a method of manufacturing the DTI structure with the varying depth, in accordance with the teachings of the present disclosure.

Block215shows etching a first trench that extends the second depth from the first side towards the second side of the semiconductor substrate during a first etching step using a first lithography pattern. In one embodiment the first trench is disposed between the first photodiode and the second photodiode (e.g., such that the first trench corresponds to at least a trench utilized to form the first segment129illustrated inFIG.1F).

It is appreciated that in some embodiments standard lithographic techniques may be utilized to protect portions of the semiconductor substrate proximate to the first side that are not to be etched during the first etching step. For example, a nitride hard mask and photoresist layer may be deposited on the first side of the semiconductor substrate. A mask (see, e.g.,FIGS.2C-2E) may then be utilized to selectively etch during the first etching step. Upon completion of the first etching step, the photoresist layer may be stripped and cleaned from the first side of the semiconductor substrate in order to proceed with subsequent steps in the manufacturing process.

Block220illustrates etching the first trench further during a second etching step occurring after the first etching step using a second lithography pattern such that a first portion of the first trench extends the first depth (e.g., the first portion of the first trench is etched further to extend the depth from being the second depth to being the first depth) while a second portion (e.g., corresponding to the second segment131illustrated inFIG.1F) and a third portion (e.g., corresponding to the third segment133illustrated inFIG.1F) of the first trench respectively are not further etched and have a depth that remains at or otherwise corresponds to the second depth and the third depth. In other words, the first portion of the first trench is etched twice (i.e., during both the first etching step and the second etching step) while the second portion and the third portion are only etched once (i.e., during either the first etching step or the second etching step). In such an embodiment the total etch depth of the first portion corresponds to the first depth (e.g., the first depth181illustrated inFIG.1F) while the total etch depth of the second portion and the third portion respectively corresponds to the second depth and the third depth (e.g., the second depth183and the third depth185illustrated inFIG.1F). In some embodiments, the second depth is substantially equal to the third depth. However, it is appreciated that in other embodiments additional etching steps may be utilized when more than two etch depths are to be included in the varying depth of the DTI structure.

In some embodiments, the semiconductor substrate includes a shallow trench isolation (STI) structure (see, e.g.,FIG.1F) disposed proximate to the second side of the semiconductor substrate between the first photodiode and the second photodiode. In the same embodiment, the first portion of the first trench is aligned with the STI structure and extends towards the STI structure such that the first segment of the DTI structure directly contacts the STI structure. In some embodiments, the second etching step may partially etch or otherwise extend until reaching the STI structure.

Similar to block215, it is appreciated that in some embodiments standard lithographic techniques may be utilized to protect portions of the semiconductor substrate proximate to the first side that are not to be etched during the second etching step. For example, a photoresist layer may be deposited on the first side of the semiconductor substrate (e.g., on top of the nitride hard mask formed in advance of the first etching step). A mask (see, e.g.,FIGS.2C-2E) may then be utilized to selectively etch during the second or subsequent etching step. Upon completion of the second or subsequent etching step, the photoresist layer may be stripped and cleaned from the first side of the semiconductor substrate in order to proceed with subsequent steps in the manufacturing process. In some embodiments, when the multiple etching steps have completed, the nitride hard mask may also be removed in preparing for subsequent steps for forming the DTI structure within the trenches.

Block225shows backfilling the first portion, the second portion, and the third portion of the first trench with at least one of an oxide material or a metal material to respectively form the first segment, the second segment, and the third segment of the DTI structure.

Block230illustrates optionally lining at least the first trench with a high-κ dielectric shell before the backfilling (i.e., block225) such that the first segment, the second segment, and the third segment collectively correspond to a contiguous portion of the DTI structure formed of the high-κ dielectric shell filled with at least one of the oxide material or the metal material. In some embodiments, the high-κ dielectric shell is formed of one or more high-κ dielectric material layers including at least one of a hafnium oxide (HfO2) layer, an aluminum oxide (Al2O3) layer, a zirconium oxide (ZrO2) layer, a tantalum oxide (Ta2O5) layer, a titanium oxide (TiO2) layer, or any combination thereof.

FIGS.2C-2Eillustrate example lithographic patterns from a multiple etching step process for forming the varying depth DTI structure, in accordance with the teachings of the present disclosure.FIG.2Cillustrates a repeat unit of a first lithographic pattern284andFIG.2Dillustrates a repeat unit of a second lithographic pattern286. It is appreciated that the repeat units of the first lithographic pattern284and the second lithographic pattern286can be arranged to form a pattern that laterally surrounds, when viewed from a first side of a semiconductor substrate, individual photodiodes included in a plurality of small photodiodes and a plurality of large photodiodes as illustrated inFIG.2E, which corresponds to the cross-sectional shape of the DTI structure105illustrated inFIG.1A.

In some embodiments, the first lithographic pattern284and the second lithographic pattern286may be utilized for the first etching step (see, e.g., block215ofFIG.2B) or the second etching step (see, e.g., block220) to form the DTI structure with the varying depth surrounding the individual photodiodes included in the plurality of small photodiodes and the plurality of large photodiodes. When the first lithographic pattern284and the second lithographic pattern286are arranged as shown inFIG.2E, there is partial overlap between the two patterns, to enable manufacturing of the DTI structure with the varying depth via multiple etching steps. For example, regions229illustrated inFIG.2Erepresent portions of the collective pattern that are etched twice when the first lithographic pattern284and the second lithographic pattern286are utilized for respective etching steps. In one embodiment, the first lithographic pattern284and the second lithographic pattern286are complementary patterns with overlapping patterns at the regions229to etch corresponding regions of the underlying semiconductor substrate twice. In the same embodiment, the regions229correspond to isolation regions between neighboring photodiodes (e.g., the first photodiode111-1and second photodiode112-2illustrated inFIGS.1A-1F). In one embodiment, the first trench is formed using the first lithographic pattern284, or alternatively the second lithographic pattern286, and is disposed proximate to the first side of the semiconductor substrate during the first etching step to etch a first trench with a depth corresponding to the second or third depth. In the same or another embodiment, a first portion of the first trench is further etched to the first depth using the second lithographic pattern286, or alternatively the first lithographic pattern284, and is disposed proximate to the first side of the semiconductor substrate during the second etching step. It is appreciated that during the second etching step, the first portion of the first trench is further etched while adjacent portions of the first trench (e.g., the second and third portions of the first trench) to the first portion remain at the second or third depth. As illustrated, the first lithographic pattern284is different from the second lithographic pattern286.

FIG.3Aillustrates regions392and394for circuitry associated with individual photodiodes included in an image sensor301with a varying depth deep trench isolation structure, in accordance with the teachings of the present disclosure. Image sensor301is one possible implementation of the image sensor101illustrated inFIGS.1A-1Fand may also be manufactured via process200-A and200-B illustrated inFIG.2A-2B. In the illustrated embodiment ofFIG.3A, a view from the first side (e.g., backside) of the image sensor301shows a first photodiode311(e.g., a small photodiode) adjacent to a second photodiode312(e.g., a large photodiode). In some embodiments, the first photodiode311and the second photodiode312are coupled to a floating diffusion384through respective transfer gates380and382. Disposed proximate to the first photodiode311and the second photodiode312and further proximate to second side (e.g., front side) of the semiconductor substrate are regions392and394(e.g., transistor regions), which represent example locations for control circuitry (e.g., 3T, 4T, 5T, or other pixel circuitry architectures such as source follower, reset transistor, row select transistor) for reading out image charge or otherwise controlling the operation of coupled first photodiode311or the second photodiode312. It is appreciated that regions392and394are disposed on or proximate to the second side of the semiconductor substrate and may overlap with a portion of DTI structure305disposed proximate to the first side (e.g., backside). It is further appreciated that the specific regions392and394are one possible implementation and that other locations may also be utilized for control circuitry placement. In the illustrated embodiment, the DTI structure305forms a square or diamond shape that laterally surrounds the first photodiode311and an octagonal shape that laterally surrounds the second photodiode312. However, it is appreciated that in other embodiments, the DTI structure305may have different shapes.

FIG.3Billustrates a cross-sectional view of the image sensor301along the line E-E′ shown inFIG.3A, in accordance with the teachings of the present disclosure.FIG.3Bis similar in many respects to the view of image sensor101shown inFIG.1Aand may include the same features, in accordance with the teachings of the present disclosure. One difference isFIG.3Bshows additional components that may be included in the image sensor architecture, including color filters391(e.g., red, green, blue or other color filters), a metal grid393, a small microlens395directing light to small photodiode SPD, a large microlens397directing light to large photodiode LPD, and transfer gates399coupled to small photodiode SPD and large photodiode, respectively. In the same or other embodiments, the image sensor architecture may optionally further include a light attenuation layer396. The light attenuation layer396may cover the light exposure area of first photodiode SPD to reduce intensity of light incident on the first photodiode SPD that has been directed to the first photodiode SPD by the small microlens395. In accordance with embodiments of the disclosure, the DTI structure305has a varying depth (e.g., along a direction corresponding to “into the page” or “out of the page” ofFIG.3Bthe depth of DTI structure305may change) and is disposed between the first photodiode SPD and the second photodiode LPD to provide isolation therebetween and reduce crosstalk.

FIG.4illustrates an example block diagram of an imaging system400including an image sensor401with a varying depth deep trench isolation structure, in accordance with the teachings of the present disclosure. Image sensor401of imaging system400is one possible implementation of image sensor101illustrated inFIGS.1A-1Fand image sensor301illustrated inFIGS.3A-3B. Imaging system400includes pixel array405, control circuitry421, readout circuitry411, and function logic415. In one embodiment, pixel array405is a two-dimensional (2D) array of photodiodes (see, e.g., first array of SPD111and/or second array of LPD112illustrated inFIG.1A), or image sensor pixels (e.g., pixels P1, P2. . . , Pn). As illustrated, photodiodes are arranged into rows (e.g., rows R1to Ry) and columns (e.g., column C1to Cx) to acquire image data of a person, place, object, etc., which can then be used to render an image or video of the person, place, object, etc. However, photodiodes do not have to be arranged into rows and columns and may take other configurations.

In one embodiment, after each image sensor photodiode/pixel in pixel array405has acquired its image data or image charge, the image data is readout by readout circuitry411and then transferred to function logic415. In various examples, readout circuitry411may include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or otherwise. Function logic415may simply store the image data or even manipulate the image data by applying post image effects (e.g., autofocus, crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In the same or another embodiment, readout circuitry411may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels simultaneously. In one embodiment, control circuitry421is coupled to pixel array405to control operation of the plurality of photodiodes or the image sensor pixel in the pixel array405. For example, control circuitry421may generate a shutter signal for controlling image acquisition.

It is appreciated that imaging system400may be included in a digital camera, cell phone, laptop computer, automobile, or the like. Additionally, imaging system400may be coupled to other pieces of hardware such as a processor (general purpose or otherwise), memory elements, output (USB port, wireless transmitter, HDMI port, etc.), lighting/flash, electrical input (keyboard, touch display, trackpad, mouse, microphone, etc.), and/or display. Other pieces of hardware may deliver instructions to imaging system400, extract image data from imaging system400, or manipulate image data supplied by imaging system400.

It is further appreciated that while the block diagram illustrated inFIG.4shows pixel array405, readout circuitry411, function logic415, and control circuitry421as distinct and separate elements from the pixel array, this is not necessarily the case as such features may be combined or otherwise incorporated with the pixel array directly (e.g., within and/or between individual pixels, in the form of stacked substrates, or otherwise). For example, the readout circuitry411may include one or more transistors (e.g., associated with 3T, 4T, 5T, or other pixel architectures for reading out image charge from individual pixels), elements of which may be disposed between segments of individual photodiodes in accordance with embodiments of the present disclosure. Furthermore, the image sensor401may include features not explicitly illustrated or discussed but known by one of ordinary skill in the art such as color filters, microlenses, a metal grid, and the like. Additionally, it is appreciated that image sensor401is fabricable by conventional CMOS manufacturing techniques known by one of ordinary skill in the art, which may include, but is not limited to, photolithography, chemical vapor deposition, physical vapor deposition, ion implantation or diffusion, thermal oxidation, reactive ion etching, wet chemical etching, chemical mechanical polishing, and the like.

The processes explained above may be implemented using software and/or hardware. The techniques described may constitute machine-executable instructions embodied within a tangible or non-transitory machine (e.g., computer) readable storage medium, that when executed by a machine will cause the machine to perform the operations described. Additionally, the processes may be embodied within hardware, such as an application specific integrated circuit (“ASIC”), field programmable gate array (FPGA), or otherwise.

A tangible machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a non-transitory form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine-readable storage medium includes recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.