Patent ID: 12198783

DETAILED DESCRIPTION

FIG.1is a block diagram of an apparatus100according to an example embodiment.

Referring toFIG.1, an apparatus100may include a first device (or device1)110and a second device (or device2)120. The apparatus100may be implemented to be included in, e.g., a personal computer (PC) or a mobile electronic device. Mobile electronic devices may be implemented as, e.g., laptop computers, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, portable multimedia players (PMPs), personal navigation devices or portable navigation devices (PNDs), handheld game consoles, mobile Internet devices (MIDs), wearable computers, Internet of things (IoT) devices, Internet of everything (IoE) devices, or drones.

The first device110may be implemented as, e.g., an integrated circuit (IC), a system on a chip (SoC), an application processor (AP), a mobile AP, a chipset, or a set of chips. As an example, the first device110may be a semiconductor device that performs a memory control function, and the first device110may be a component included in an AP. The AP may include, e.g., a memory controller, a random-access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), and/or a modem.

The second device120may be implemented as a memory device. The memory device may be implemented as, e.g., dynamic RAM (DRAM) or static RAM (SRAM). As an example, the second device120may correspond to double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random access memory (RDRAM), and so on. In another implementation, the second device120may be implemented as high bandwidth memory (HBM).

According to an example embodiment, the second device120may be implemented as a nonvolatile memory device. As an example, the second device120may be implemented as flash memory or resistive memory, such as phase change RAM (PRAM), magnetic RAM (MRAM), or resistive RAM (RRAM).

The second device may be a memory device that includes a plurality of signal pins, e.g., a first signal pin to receive a clock signal and a second signal pin to output a three-dimensional duty offset code. The second signal pin may be a data pin or a data clock pin.

Hereinafter, for convenience of description, the first device110is referred to as a memory controller, and the second device120is referred to as a memory device.

Although the memory device120is illustrated as a single semiconductor chip, the memory device120may include n (n is a non-zero whole number) memory devices in actuality.

The memory controller110and the memory device120may communicate with each other through a bus (e.g., a data bus (or data (DQ) bus), a clock bus, a command/address (CA) bus, etc.)130. In an example, a command and address CA are received by the memory device120through a command/address bus130, and data DQ is provided between the memory controller110and the memory device120via the data bus130. Various clock signals may be provided between the memory controller110and the memory device120via the clock bus130. The clock bus130may include signal lines for providing system clocks CLK_t and CLK_c received by the memory device120and data clocks DQS_t and DQS_c transmitted and received by the memory device120. Each bus130may include one or more signal lines to which signals are provided.

In an example embodiment, the clocks CLK_t and CLK_c provided by the memory controller110to the memory device120are used for a timing of provision and reception of commands and addresses. The clocks DQS_t and DQS_c are used for a timing of data provision. The clocks CLK_t and CLK_c are complementary, and the clocks DQS_t and DQS_c are complementary. The clock signal is complementary when a rising edge of a first clock signal coincides with a falling edge of a second clock signal and when a rising edge of the second clock signal coincides with a falling edge of the first clock signal. According to an example embodiment, the memory controller110and the memory device120may use the data clock DQS by classifying the data clock DQS as a write data clock and a read data clock.

The clocks DQS_t and DQS_c provided to the memory device120by the memory controller110may be synchronized with the clocks CLK_t and CLK_c provided to the memory device120by the memory controller110. Also, the clocks DQS_t and DQS_c may have higher clock frequencies than the clocks CLK_t and CLK_c. For example, the clocks DQS_t and DQS_c may have a clock frequency that is twice the clock frequency of the clocks CLK_t and CLK_c. Hereinafter, for convenience of description, the clocks CLK_t and CLK_c may be referred to as CLK clocks, and clocks DQS_t and DQS_c may be referred to as DQS clocks.

The memory controller110may provide a command to the memory device120to perform a memory operation. Examples of a memory command may include a timing command for controlling a timing of various operations, an access command for accessing a memory, e.g., a read command for performing a read operation and a write command for performing a write operation, a mode register write and read command for performing a mode register write and read operation, and the like.

During an operation, when a read command and a related address are provided to the memory device120by the memory controller110, the memory device120may receive a read command and a related address and perform a read operation to output read data DQ from a memory location corresponding to the related address. The read data DQ may be provided to the memory controller10by the memory device120, according to a timing related to reception of the read command. For example, when the read data DQ is provided to the memory controller110by the memory device120, a timing may be based on a read latency RL value indicating the number (referred to as tCLK) of clock cycles of CLK clocks after the read command. In an example embodiment, the read latency RL value is programmed by the memory controller110in the memory device120. For example, the read latency RL value may be programmed into each mode register of the memory device120. The mode register included in each memory device120may be programmed with information for setting various operation modes and/or for selecting characteristics for a memory operation. One of the settings may be for the read latency RL value.

When the memory device120that provides the read data DQ to the memory controller110is preparing, the memory controller110may provide an active CLK clock to the memory device120. The CLK clock may be used by the memory device120to generate a DQS clock. In an example embodiment, a clock signal is activated when the clock signal periodically transitions between a low clock level and a high clock level; conversely, the clock signal is deactivated when the clock signal maintains a constant clock level and does not transition periodically. The DQS clock may be provided to the memory controller110by the memory device120that has performed a read operation for a timing to provide read data to the memory controller110. The memory controller110may use the DQS clock to receive the read data DQ.

During an operation, when a write command and a related address are provided to the memory device120by the memory controller110, the memory device120may receive the write command and the related address, and perform a write operation to write the write data DQ from the memory controller110to a memory location corresponding to the related address. In an example embodiment, the write data DQ is provided to the memory device120by the memory controller110according to a timing related to reception of the write command. For example, when the write data DQ is provided to the memory device120by the memory controller110, a timing may be based on a write latency WL value indicating the number of clock cycles tCLK of CLK clocks after the write command DQ. The write latency WL value may be programmed by the memory controller110in the memory device120. For example, the write latency WL value may be programmed into a mode register of the memory device120.

When the memory device120that receives the write data DQ from the memory controller110is preparing, the memory controller110may provide an active CLK clock to the memory device120. The CLK clock may be used by the memory device120to generate an internal clock signal for an operation timing of a circuit receiving the write data DQ. The write data DQ may be provided by the memory controller110. The memory device120may receive the write data DQ together with the DQS clock. The write data DQ may be written to a memory corresponding to the memory address.

In order to accurately perform a memory operation according to the operation timings, the memory controller110may include a training circuit112that performs memory training on the memory device120. The training circuit112may perform memory core parameter training associated with a memory core and/or peripheral circuit parameter training for peripheral circuits other than the memory core in the memory device120, in response to a training command. The training circuit112may be a training subject to determine an optimal parameter for the memory core parameter and/or a peripheral circuit parameter.

In the present example embodiment, it is described that the training circuit112is included in the memory controller110, but the training circuit112may be included in the memory device120and the memory device120may be a subject to perform memory training.

The training circuit112may perform a clock training operation on the CLK clock and the DQS clock in connection with peripheral circuit parameter training. The training circuit112may perform a clock training operation in association with a clock training circuit124of the memory device120. This will be described in detail with reference toFIGS.3to10.

The memory device120may include a mode register (MRS)122, the clock training circuit124, and a data input/output (I/O) circuit126.

The MRS122may store information used to configure an operation of the memory device120to set an operating condition for the memory device120. The MRS122may store information for timing adjustment of a multi-phase clock associated with the CLK clock.

The information for timing adjustment of a multi-phase clock may include a three-dimensional duty offset code (3-D DOC) (FIG.2) for providing a 50% duty cycle-adjusted DQS clock. The 3-D DOC may be provided by the training circuit112of the memory controller110together with the memory core parameters and/or peripheral circuit parameters and stored in the MRS122. According to an example embodiment, the 3-D DOC may be stored by the clock training circuit124in the MRS122as a result of a 3-D duty offset search operation for a multi-phase clock.

The clock training circuit124may generate a multi-phase clock upon receiving the CLK clock, and simultaneously phase-sweep three internal clock signals in the multi-phase clock by a duty adjustment step to generate the 3-D DOC for the multi-phase clock.

The clock training circuit124may perform a first step operation of sweeping the phases between the internal clock signals in a first adjustment range of −n to +n steps, select a first phase offset point among phase offset points associated with the first step operation, and output an internal clock signal including the first phase offset point, as a first internal clock signal.

The clock training circuit124may perform a second step operation of sweeping the phases between the first internal clock signals in a second adjustment range of −n/2 to +n/2 steps based on the first phase offset point as an origin, select a second phase offset point, among phase offset points associated with the second step operation, and output a first internal clock signal including the second phase offset point, as a second internal clock signal.

The clock training circuit124may perform a third step operation of sweeping the phases between the second internal clock signals in a third adjustment range of −n/4 to +n/4 steps with the second phase offset point as an origin, select a third phase offset point, among phase offset points associated with the third step operation, and output a second internal clock signal including the third phase offset point, as a third internal clock signal. The clock training circuit124may provide the third phase offset point as the 3-D DOC to the memory controller110.

According to an example embodiment, the clock training circuit124may store the 3-D DOC123of the DQS clock in the MRS122. The 3-D DOC123stored in the MRS122may be provided to the memory controller110by a mode register read command issued by the memory controller110.

The data I/O circuit126may transmit the read data DQ synchronized with the DQS clock to the memory controller110and receive write data DQ synchronized with the DQS clock from the memory controller110. The data DQ transmitted and received by the data I/O circuit126may include a data width of 8 bits. According to an example embodiment, the data width may be 16 bits, and the 16 bits may be divided into lower bytes of 8-bit data and higher bytes of 8-bit data. Accordingly, the DQS clock may be divided into a low byte DQS clock and a high byte DQS clock to be used.

FIG.2is a block diagram illustrating the memory device120according to an example embodiment.

Referring toFIGS.1and2, the memory device120may include a memory cell array (MCA)200, a row decoder202, a word line (WL) driver204, a column decoder206, a read/write (R/W) circuit208, a clock circuit210, a control logic circuit220, an address buffer230, an MRS122, and a data I/O circuit126.

In an example embodiment, the MCA200includes a plurality of memory cells provided in a matrix form arranged in rows and columns. The MCA200includes a plurality of word lines WL and a plurality of bit lines BL respectively connected to the memory cells. The word lines WL may be respectively connected to rows of the memory cells, and the bit lines BL may be respectively connected to columns of the memory cells.

The row decoder202may select any one of the word lines WL connected to the MCA200. The row decoder202decodes a row address ROW_ADDR received through the CA bus130and the address buffer230to select any one word line WL corresponding to the row address ROW_ADDR and connect the selected word line WL to the word line driver204activating the selected word line WL. The column decoder206may select certain bit lines BL among the bit lines BL of the MCA200. The column decoder206may decode the column address COL_ADDR received from the address buffer230to generate a column selection signal, and connect bit lines BL selected by the column selection signal to the R/W circuit208.

The R/W circuit208may include read data latches for storing read data of the bit lines BL selected by the column selection signal, and a write driver for writing write data to the MCA200. The read data stored in the read data latches of the R/W circuit208may be provided to the data (DQ) bus130through a data output driver of the read data path270. The write data may be applied to the MCA200through a data input buffer of the write data path260connected to the data (DQ) bus130and through a write driver of the R/W circuit208.

The clock circuit210may receive a CLK clock through the clock bus130, and may generate an internal clock signal. The internal clock signal may include clock signals (e.g., ICLK, QCLK, IBCLK, and QBCLK) described as the multi-phase clock with reference toFIG.3. The internal clock signals ICLK, QCLK, IBCLK, and QBCLK may be used for various operation timings of internal circuits of the memory device120. The clock circuit210may monitor the DQS clock provided by the read data path270using the internal clock signals ICLK, QCLK, IBCLK, and QBCLK and adjust a DQS clock timing. The clock circuit210may include a clock training circuit124receiving the CLK clock to generate a multi-phase clock and simultaneously phase-sweeping each of the three internal clock signals in the multi-phase clock by a duty adjustment step to generate a 3-D DOC for the multi-phase clock.

The control logic circuit220may receive a command CMD through the CA bus130, and generate a control signal CTRLS for controlling an operation timing and/or a memory operation of the memory device120. The control logic circuit220may read data from the MCA200and write data to the MCA200using the control signal CTRLS.

The MRS122may store information used by the control logic circuit220to configure an operation of the memory device120to set an operating condition for the memory device120. The MRS122may include a register that stores parameter codes and/or 3-D DOCs for various operating and control parameters used to set operating conditions of the memory device120. The parameter codes and/or the 3-D DOCs may be received by the memory device120through the CA bus130. The control logic circuit220provides control signals CTRLS to circuits of the memory device120to operate as set in operating and control parameters and/or the 3-D DOC stored by the MRS122.

The data I/O circuit126may be divided into a write data path260portion including a data input buffer and a read data path270portion including a data output driver. The write data path260may include a flip-flop that receives the write data DQ. The read data path270may include a flip-flop for transmitting the read data DQ. Additionally, the read data path270may include circuits performing various functions related to a read operation, such as output drive strength, preamble/postamble length, pull-down/on die termination (ODT), and pull-up/output high level voltage (Voh) calibration, pre-emphasis, and the like. The pull-down/ODT and pull-up/Voh calibration may be provided to improve signal integrity (SI) by adjusting a swing width and/or drive strength of signals received through the CA bus130and/or the data (DQ) bus130. The pre-emphasis function may be provided to improve SI by increasing a data eye opening region of a signal transmitted through the data (DQ) bus130. The read data path270may have a propagation delay factor longer than the write data path260.

FIGS.3A and3Bare block diagrams of the clock circuit210according to an example embodiment.FIG.4is a diagram illustrating a multi-phase clock including internal clock signals ICLK/QCLK/IBCLK/QBCLK ofFIGS.3A and3B.

The clock circuit210ofFIGS.3A and3Bmay be connected to a portion of the read data path270and/or the write data path260of the memory device120ofFIG.2.

Referring toFIGS.2and3A, the clock circuit210may include a clock buffer310(e.g., a data clock buffer), a divider circuit320, a clock tree and driver circuit330, and a clock training circuit124.

The clock buffer310may buffer an external CLK clock, and provide the buffered CLK clock to the divider circuit320.

The divider circuit320may provide multi-phase clocks derived from the CLK clock.

The multi-phase clocks may have a phase relationship with respect to each other. As an example, the divider circuit320may generate four internal clock signals ICLK/QCLK/IBCLK/QBCLK having a phase relationship of 90 degrees (0 degrees, 90 degrees, 180 degrees, 270 degrees, etc.) with respect to each other.

For convenience of description, the four internal clock signals ICLK/QCLK/IBCLK/QBCLK may be used interchangeably as multi-phase clocks. However, the present embodiment is not limited to this particular number of internal clock signals, phase relationships, and/or clock frequencies.

The multi-phase clocks of the divider circuit320may be provided to a circuit that may operate according to the corresponding internal clock signals ICLK/QCLK/IBCLK/QBCLK through the clock tree and driver circuit330. For example, the internal clock signals ICLK/QCLK/IBCLK/QBCLK may be provided to the read data path270of the data I/O circuit126by the clock tree and driver circuit330for a timing of the operation of transmitting the read data.

The clock tree and driver circuit330may generate a DQS clock based on the internal clock signals ICLK/QCLK/IBCLK/QBCLK. The DQS clock may provide a timing of a read data transmission operation performed in the read data path270.

In the clock circuit210, for data having a data width including lower and upper bytes, a separate clock path may be provided for the internal clock signals ICLK/QCLK/IBCLK/QBCLK associated with each byte. In an example embodiment, each clock path includes circuits for individually monitoring the internal clock signals ICLK/QCLK/IBCLK/QBCLK for each data byte. For example, the clock training circuit124is included for providing, timing adjustment, and monitoring an internal clock signal for a first byte of data, and at least a portion of the clock training circuit124may be duplicated for providing, timing adjustment, and monitoring an internal clock signal for a second byte of the data. For convenience of description, the clock circuit210is described in connection with the operation of providing, timing adjustment, and monitoring of the internal clock signal for the first byte data, but the same may be applied to the second byte data.

The internal clock signals ICLK/QCLK/IBCLK/QBCLK provided from the clock tree and driver circuit330may have the same or different phases with respect to an external CLK clock, as shown inFIG.4. As an example, the ICLK clock may have the same phase as that of the CLK clock, the ICLK clock may have a phase difference of 180 degrees from that of the IBCLK clock, and the QCLK clock may have a phase difference of 180 degrees from that of the QBCLK clock. A DQS clock frequency may be twice a CLK clock frequency. The DQS clock may be configured to have a first even edge I synchronized with a rising edge of the ICLK clock, a first odd edge Q synchronized with a rising edge of the QCLK clock, a second even edge IB synchronized with a rising edge of the IBCLK clock, and a second odd edge QB synchronized with a rising edge of the QBCLK clock.FIG.4shows a DQS clock having an ideal 50% duty cycle.

In general, the clock tree and driver circuit330ofFIG.3may have a unique circuit characteristic that causes an undesirable timing change when providing the internal clock signals ICLK/QCLK/IBCLK/QBCLK. This unique circuit characteristic may deviate from ideal circuit characteristics due to, e.g., variations in a manufacturing process and operating variations due to changes in temperature and voltage. For example, when the clock tree and driver circuit330provides the internal clock signals ICLK/QCLK/IBCLK/QBCLK, a duty cycle may be changed so that the internal clock signals ICLK/QCLK/IBCLK/QBCLK may have a distorted duty cycle, compared with an external CLK clock. A timing of the internal clock signals ICLK/QCLK/IBCLK/QBCLK having a distorted duty cycle may cause undesirable performance of a circuit operating according to the internal clock signals ICLK/QCLK/IBCLK/QBCLK. As an example, as shown inFIG.6, a raw DQS clock600having a 50% distorted duty ratio may be generated by the internal clock signals ICLK/QCLK/IBCLK/QBCLK having a distorted duty cycle. The raw DQS clock600ofFIG.6may cause a malfunction in the read data path270.

The clock training circuit124may generate a DQS clock by adjusting the timing of the internal clock signals ICLK/QCLK/IBCLK/QBCLK provided by the clock tree and driver circuit330. The clock training circuit124may simultaneously sweep the internal clock signals ICLK/QCLK/IBCLK/QBCLK with a duty adjustment step within a certain range. The clock training circuit124may include a 3-D duty offset search circuit350generating an optimal duty offset code (3-D DOC) for the DOS clock by simultaneously sweeping three internal clock signals (e.g., QCLK/IBCLK/QBCLK) among the internal clock signals ICLK/QCLK/IBCLK/QBCLK with a certain duty adjustment.

The 3-D duty offset search circuit350may provide the duty offset code (3-D DOC) related to the DQS clock to the memory controller110(FIG.1) through the bus (FIG.1) connected to the data DQ line or the DQS clock line. The memory controller110may adjust the CLK clock using the duty offset code (3-D DOC) for the DQS clock associated with the read data DQ of the read data path270of the memory device120to have an ideal 50% duty cycle, and provide the adjusted CLK clock to the memory device120. In another implementation, the memory controller110may provide the duty offset code (3-D DOC) by the training circuit112to the mode register122of the memory device120, as clock duty offset information. The clock duty offset information may be programmed as opcodes in the mode register122, and the opcodes may correspond to specific bits of the second mode register122b.

Referring toFIG.3B, the clock circuit210may be configured to receive an external DQS clock and generate an optimal duty offset code (3-D DOC) for write data DQ using the 3-D duty offset search circuit350. The clock buffer310may buffer the external DQS clock, and the divider circuit320and the clock tree and driver circuit330may generate internal clock signals ICLK/QCLK/IBCLK/QBCLK derived from the DQS clock. The clock training circuit124may adjust a timing of the internal clock signals ICLK/QCLK/IBCLK/QBCLK provided by the clock tree and driver circuit330and receive the write data DQ, in response to the timing-adjusted internal clock signals ICLK/QCLK/IBCLK/QBCLK. The 3-D duty offset search circuit350may sweep three internal clock signals (e.g., QCLK/IBCLK/QBCLK), among the internal clock signals ICLK/QCLK/IBCLK/QBCLK, simultaneously with a certain duty adjustment step to generate an optimal duty offset code (3-D DOC) for the data DQ The 3-D duty offset search circuit350may provide the duty offset code (3-D DOC) related to the write data DQ to the memory controller110(FIG.1) through the data DQ line or the bus130(FIG.1) connected to the DQS clock line. In order for the write data DQ of the write data path260of the memory device120to have an ideal 50% duty cycle using the duty offset code 3-D DOC, the memory controller110may adjust the DQS clock and provide the adjusted DQS clock to the memory device120.

FIG.5is a block diagram illustrating the 3-D duty offset search circuit350ofFIG.3.FIGS.6and7A to7Dare diagrams illustrating the operation of the 3-D duty offset search circuit350ofFIG.3.

Referring toFIGS.3and5, the 3-D duty offset search circuit350may include a first duty adjusting unit510, a second duty adjusting unit520, and a third duty adjusting unit530.

In an implementation, the 3-D duty offset search circuit350may be implemented by software, that is, as program code, and the clock training circuit124may execute the program code in which the operation of the 3-D duty offset search circuit350is described.

Hereinafter, subscripts (e.g., a in710a, a in720a, and a in730a) of reference numbers are used to distinguish between a plurality of circuits having the same function.

The first duty adjusting unit510may receive the internal clock signals ICLK, QCLK, IBCLK, and QBCLK provided by the clock tree and driver circuit330. As illustrated inFIG.4, a DQS clock having a first even edge I synchronized with a rising edge of the ICLK clock, a first odd edge Q synchronized with a rising edge of the QCLK clock, a second even edge IB synchronized with a rising edge of the IBCLK clock, and a second odd edge QB synchronized with a rising edge of the QBCLK clock is generated, and here, the raw DQS clock600(FIG.6) having a 50% distorted duty ratio as illustrated inFIG.6may be generated.

The first duty adjusting unit510may include a first duty sweep circuit (DCS1,511, hereinafter referred to as a “first DCS circuit”) and a first duty control circuit (DCA1,512, hereinafter referred to as a “first DCA circuit”). The first duty adjusting unit510may perform a first step operation STEP1ofFIGS.6and7Aon the raw DQS clock600. The first step operation STEP1may be referred to as a coarse duty cycle adjustment operation for the raw DQS clock600. The first duty adjusting unit510may not perform a coarse duty cycle adjustment operation on the ICLK clock among the internal clock signals ICLK, QCLK, IBCLK, and QBCLK related to the raw DQS clock600but perform a coarse duty cycle adjustment operation on the other three internal clock signals QCLK, IBCLK, and QBCLK. The ICLK clock may act as a reference clock for the three internal clock signals QCLK, IBCLK, and QBCLK that are coarse duty cycle adjusted.

The first DCS circuit511may simultaneously sweep the phases of the internal clock signals QCLK, IBCLK, and QBCLK to a first adjustment range. The first adjustment range may include an adjustment range of −n to +n (n is a non-zero whole number) step. As an example, the first adjustment range may be set to −7 to +7 steps.

Adjusting the phases between the internal clock signals QCLK, IBCLK, and QBCLK means, in the first step operation STEP1ofFIG.6, except for an I edge601, phase-sweeping in −n to +n steps based on a Q edge602, phase-sweeping in −n to +n steps based on an IB edge603, and phase-sweeping in −n to +n steps based on a QB edge604. In addition, adjusting the phases between the internal clock signals QCLK, IBCLK, and QBCLK means phase-sweeping in −n to +n steps based on a Q axis indicating the Q edge602in the first step operation STEP1ofFIG.7A, phase-sweeping in −n to +n steps based on an IB axis indicating the IB edge602, and phase-sweeping in −n to +n steps based on a QB axis indicating the QB edge603. The first step operation STEP1ofFIG.7Amay have 27 (=3*3*3) phase offset points710.

As the first DCS circuit511performs phase sweeping of the internal clock signals QCLK, IBCLK, and QBCLK in −n to +n steps, each of the internal clock signals QCLK, IBCLK, and QBCLK may be toggled with a certain pulse width. The first DCA circuit512may merge the pulse width of each of the internal clock signals QCLK, IBCLK, and QBCLK appearing at each of the phase offset points710ofFIG.7A, when the first DCS circuit511performs phase sweeping in −n to +n steps. The first DCA circuit512may select the largest value among merged pulse width windows of the internal clock signals QCLK, IBCLK, and QBCLK. The first DCA circuit512may select a first phase offset point710ahaving the largest merged pulse width window.

The first phase offset point710ais an optimal duty adjustment point for adjusting a duty cycle of the DQS clock600in the first step operation STEP1. A coarse duty-adjusted DQS clock610at the first phase offset point710amay be provided. The first DCA circuit512may capture the first phase offset point710aand output the first internal clock signals ICLK_1, QCLK_1, IBCLK_1, and QBCLK_1including the first phase offset point710aas a first duty adjustment result513. The first duty adjustment result513may be provided as a coarse duty-adjusted DQS clock610to the second duty adjusting unit520.

The second duty adjusting unit520may include second DCS circuits DCS2521and a second DCA circuit DCA2522. The second step operation STEP2ofFIGS.6and7Bmay be performed on the coarse duty-adjusted DQS clock610by the second duty adjusting unit520. The second step operation STEP2may be referred to as a first fine duty cycle adjustment operation for the DQS clock610. The second duty adjusting unit520does not perform the first fine duty cycle adjustment operation on the ICLK_1clock, among the first internal clock signals ICLK_1, QCLK_1, IBCLK_1, and QBCLK_1related to the DQS clock610and may perform the first fine duty cycle adjustment operation on the other three first internal clock signals QCLK_1, IBCLK_1, and QBCLK_1. The ICLK_1clock may serve as a reference clock for the three first internal clock signals QCLK_1, IBCLK_1, and QBCLK_1that are first fine duty cycle adjusted.

The second DCS circuit521may simultaneously sweep the phases between the first internal clock signals QCLK_1, IBCLK_1, and QBCLK_1to the second adjustment range. The second adjustment range may include an adjustment range of −n/2 to +n/2 (n/2 is a non-zero whole number) step. For example, the second adjustment range may be set to −3 to +3 steps.

In the second step operation STEP2ofFIG.6, except for an I edge611, phase sweeping may be performed in −n/2 to +n/2 steps based on a Q edge612, phase sweeping may be performed in −n/2 to +n/2 steps based on an IB edge613, and phase sweeping may be performed in −n/2 to +n/2 steps based on a QB edge614. In the second step operation STEP2ofFIG.7B, with the first phase offset point710aas the origin, phase sweeping may be performed in −n/2 to +n/2 steps based on a Q axis indicating the Q edge612, phase sweeping may be performed in-n/2 to +n/2 steps based on an IB axis indicating the IB edge613, and phase sweeping may be performed in −n/2 to +n/2 steps based on a QB axis indicating the QB edge614. The second step operation STEP2ofFIG.7Bmay have 27 (=3*3*3) second phase offset points720.

As the second DCS circuit521performs phase sweeping between the first internal clock signals QCLK_1, IBCLK_1, and QBCLK_1in −n/2 to +n/2 steps, each of the first internal clock signals QCLK_1, IBCLK_1, and QBCLK_1may be toggled with a certain pulse width. When the second DCS circuit521performs phase sweeping in −n/2 to +n/2 steps, the second DCA circuit522may merge pulse widths of the first internal clock signals QCLK_1, IBCLK_1, and QBCLK_1respectively appearing in each of the second phase offset points720ofFIG.7B. The second DCA circuit522may select the largest value among the merged pulse width windows of the first internal clock signals QCLK_1, IBCLK_1, and QBCLK_1. The second DCA circuit522may select the second phase offset point720ahaving the largest merged pulse width window.

The second phase offset point720ais an optimal duty adjustment point for adjusting the duty cycle of the DQS clock610in the second step operation STEP2. The first fine duty adjusted DQS clock620may be provided at the second phase offset point720a. The second DCA circuit522may capture the second phase offset point720aand output the second internal clock signals ICLK_2, QCLK_2, IBCLK_2, and QBCLK_2including the second phase offset point720aas a second duty adjustment result523. The second duty adjustment result523may be provided as a first fine-duty-adjusted DQS clock620to the third duty adjusting unit530.

The third duty adjusting unit530may include third DCS circuits DCS3531and third DCA circuits DCA3532. A third step operation STEP3ofFIGS.6and7Cmay be performed on the first fine-duty-adjusted DQS clock620by the third duty adjusting unit530. The third step operation STEP3may be referred to as a second fine duty cycle adjustment operation for the DQS clock620. The third duty adjusting unit530may not perform the second fine duty cycle adjustment operation on the ICLK_2clock, among the second internal clock signals ICLK_2, QCLK_2, IBCLK_2, and QBCLK_2, and may perform the second fine duty cycle adjustment operation on the other three second internal clock signals QCLK_2, IBCLK_2, and QBCLK_2. The ICLK_2clock may serve as a reference clock for the three second internal clock signals QCLK_2, IBCLK_2, and QBCLK_2that are second fine-duty-adjusted.

The third DCS circuit531may simultaneously sweep the phases between the second internal clock signals QCLK_2, IBCLK_2, and QBCLK_2to the third adjustment range. The third adjustment range may include an adjustment range of −n/4 to +n/4 (n/4 is a non-zero whole number) steps. As an example, the third adjustment range may be set in −1 to +1 steps.

In the third step operation STEP3ofFIG.6, except for the I edge621, phase sweeping may be performed in −n/4 to +n/4 steps based on a Q edge622, phase sweeping may be performed in −n/4 to +n/4 steps based on an IB edge623, and phase sweeping may be performed in −n/4 to +n/4 steps based on a QB edge624. In the third step operation (STEP3) ofFIG.7C, based on the second phase offset point720aas the origin, phase sweeping may be performed in −n/4 to +n/4 steps based on the Q axis indicating the Q edge622, phase sweeping may be performed in −n/4 to +n/4 steps based on the IB axis indicating the IB edge623, and phase sweeping may be performed in −n/4 to +n/4 steps based on the QB axis indicating the QB edge624. The third step operation STEP3ofFIG.7Cmay have 27 (=3*3*3) third phase offset points730.

As the third DCS circuit531performs phase-sweeping on the second internal clock signals QCLK_2, IBCLK_2, QBCLK_2in −n/4 to +n/4 steps, each of the second internal clock signals QCLK_2, IBCLK_2, and QBCLK_2may be toggled with a certain pulse width. The third DCA circuit532may merge the pulse width of each of the second internal clock signals QCLK_2, IBCLK_2, and QBCLK_2appearing at each of the third phase offset points710ofFIG.7C, when the third DCS circuit531performs phase sweeping in −n/4 to +n/4 steps. The third DCA circuit532may select the largest value among the merged pulse width windows of the second internal clock signals QCLK_2, IBCLK_2, and QBCLK_2. The third DCA circuit532may select the third phase offset point730ahaving the largest merged pulse width window.

The third phase offset point730ais an optimal duty adjustment point for adjusting the duty cycle of the DQS clock620in the third step operation STEP3. A second fine-duty-adjusted DQS clock630may be provided at the third phase offset point730a. The third DCA circuit532may capture the third phase offset point730aand output the third internal clock signals ICLK_3, QCLK_3, IBCLK_3, and QBCLK_3including the third phase offset point730aas a third duty adjustment result533. The third duty adjustment result533may be output as a final DQS clock630having a 50% duty cycle adjusted. The final DQS clock630may be provided to the memory controller110(FIG.1) through the bus130(FIG.1) connected to the DQS clock line.

The 50% duty cycle adjusted final DQS clock630may be provided at the third phase offset point730a. As shown inFIG.7D, the third phase offset point730amay be obtained as a result of phase-sweeping the internal clock signals QCLK, IBCLK, and QBCLK related to the raw DQS clock600by a certain step value according to performing of the first to third step operations STEP1, STEP2, and STEP3ofFIGS.7A to7C. The certain step value representing the third phase offset point730amay be indicated by a 3-D DOC of the DQS clock600. The 3-D duty offset search circuit350may provide the 3-D DOC to the memory controller110through the bus130connected to the data DQ line or the DQS clock line.

FIGS.8and9are diagrams illustrating the operation of the clock training circuit124according to an example embodiment.

Referring toFIGS.3,4, and8, the clock training circuit124may perform first to fifth step operations STEP1, STEP2, STEP3, STEP4, and STEP5by expanding the first to third step operations STEP1, STEP2, and STEP3described above with reference toFIGS.6and7A to7D. The first to fifth step operations STEP1, STEP2, STEP3, STEP4, and STEP5may be executed by a program code in which the operation of the 3-D duty offset search circuit350described above with reference toFIGS.5to7Dis described.

In the first step operation STEP1, a first duty cycle adjustment operation may be performed on a raw DQS clock800generated based on the internal clock signals ICLK, QCLK, IBCLK, and QBCLK provided by the clock tree and driver circuit330. The first duty cycle adjustment operation may be performed for three internal clock signals QCLK, IBCLK, and QBCLK, among the internal clock signals ICLK, QCLK, IBCLK, and QBCLK related to the raw DQS clock800.

In the first duty cycle adjustment operation, the phases between the internal clock signals QCLK, IBCLK, and QBCLK may be phase-swept in an adjustment range of −7 to +7 steps. As shown inFIG.9, the QCLK clock has an adjustment range of {−7, 0, 7}, the IBCLK clock has an adjustment range of {−7, 0, 7}, and the QBCLK clock has an adjustment range of {−7, 0, 7}. The adjustment ranges of these QCLK, IBCLK, and QBCLK clocks may be applied simultaneously. Accordingly, the first phase offset point710amay be selected by evaluating an optimal duty adjustment point for adjusting a duty cycle of the DQS clock800, among the 27 phase offset points710(FIG.7A).

In the first step operation STEP1, the optimal duty adjustment point may be evaluated using the largest value, among the merged pulse width windows of the internal clock signals QCLK, IBCLK, and QBCLK. For example, the first phase offset points {Q1, IB1, QB1}710amay be determined as {−7, 0, 0}. A duty-adjusted DQS clock810may be generated based on the first phase offset point {−7, 0, 0}.

In the second step operation STEP2, a second duty cycle adjustment operation may be performed on the DQS clock810whose duty is adjusted based on the first phase offset point {−7, 0, 0}. In the second duty cycle adjustment operation, the phases between the internal clock signals QCLK, IBCLK, and QBCLK related to the DQS clock810may be phase-swept in an adjustment range of −4 to +4 steps. As shown inFIG.9, the QCLK clock has an adjustment range of {−4, 0, 4} based on the Q1 {−7} phase offset point as the origin, the IBCLK clock has an adjustment range of {−4, 0, 4} based on the IB1 {0} phase offset point as the origin, and the QBCLK clock has an adjustment range of {−4, 0, 4} based on the QB1 {0} phase offset point as the origin. The adjustment ranges of these QCLK, IBCLK, and QBCLK clocks may be applied simultaneously, and, among the 27 phase offset points720(FIG.7B), 14 phase points (e.g., {−7, 0, 4)}, {−7, −4, 4}, etc.) outside −4 to +4 steps may be omitted from the optimal duty adjustment point evaluation for the DQS clock810. Accordingly, the second phase offset point720amay be selected by evaluating an optimal duty adjustment point for adjusting a duty cycle of the DQS clock810, among the other 13 phase points (e.g., {−7, 0, 4}, {−7, −4, 0}, etc.). As an example, the second phase offset point {Q2, IB2, QB2}710amay be determined as {−3, 0, 4}. A duty-adjusted DQS clock820may be generated based on the second phase offset point {−3, 0, 4}.

In the third step operation STEP3, a third duty cycle adjustment operation may be performed on the duty-adjusted DQS clock820based on the second phase offset point {−3, 0, 4}. In the third duty cycle adjustment operation, the phases between the internal clock signals QCLK, IBCLK, and QBCLK related to the DQS clock820may be phase-swept in a range of −3 to +3 steps, an optimal duty adjustment point for adjusting a duty cycle of the DQS clock820, among 16 phase points (e.g., {−3, 0, 4}, {−3, 0, 1}, etc.), among 27 phase offset points, may be evaluated and determined as a third phase offset point {−3, 3, 1}, and a duty-adjusted DQS clock830may be generated based on the third phase offset point {−3, 3, 1}.

In the fourth step operation STEP4, a fourth duty cycle adjustment operation may be performed on the duty-adjusted DQS clock830based on the third phase offset point {−3, 3, 1}. In the fourth duty cycle adjustment operation, the phases between the internal clock signals QCLK, IBCLK, and QBCLK related to the DQS clock830may be phase-swept in an adjustment range of −2 to +2 steps, and an optimal duty adjustment point for adjusting a duty cycle of the DQS clock830among 18 phase points (e.g., {−3, 3, 1}, {−3, 3, 3}, etc.), among 27 phase offset points, is evaluated and determined as a fourth phase offset point {−5, 1, 3}, and a duty-adjusted DQS clock840may be generated based on the fourth phase offset point {−5, 1, 3}.

In the fifth step operation STEP5, a fifth duty cycle adjustment operation may be performed on the duty-adjusted DQS clock840based on the fourth phase offset point {−5, 1, 3}. In the fifth duty cycle adjustment operation, the phases between the internal clock signals QCLK, IBCLK, and QBCLK related to the DQS clock830may be phase-swept in an adjustment range of −1 to +1 steps, and an optimal duty adjustment point for adjusting the duty cycle of the DQS clock830among 18 phase points (e.g., {−5, 1, 2}, {−5, 2, 2}, etc.), among 27 phase offset points, is evaluated to select the fifth phase offset point (e.g.,730a). As an example, the fifth phase offset point {Q5, IB5, QB5}730amay be determined as {−4, 2, 2}.

A 50% duty cycle adjusted final DQS clock850may be provided at the fifth phase offset point {−4, 2, 2}. The fifth phase offset point {−4, 2, 2} may be represented by a 3-D DOC of the DQS clock800. The 3-D DOC may be provided to the memory controller110through the bus130connected to the data DQ line or the DQS clock line.

FIGS.10A,10B, and11are flowcharts illustrating a clock training method according to an example embodiment.

Referring toFIG.10Ain conjunction withFIGS.1to9, in operation S1010, the memory controller110may issue a clock training command to the memory device120.

In operation S1020, the memory device120may perform a 3-D duty offset search operation on a multi-phase clock by the clock training circuit124in response to a clock training command.

In operation S1030, the memory device120may transmit the 3-D DOC (obtained as a result of the 3-D duty offset search operation of the clock training circuit124) to the memory controller110. The memory device120may transmit the duty offset code (3-D DOC) to the memory controller110through the bus130connected to the data DQ line or the DQS clock line. Using the duty offset code (3-D DOC), the memory controller110may adjust a CLK clock for a DQS clock associated with the read data DQ of the read data path270of the memory device120to have an ideal 50% duty cycle or adjust a DQS clock for the write data DQ of the write data path260of the memory device120to have an ideal 50% duty cycle. The memory controller110may provide the adjusted CLK clock and/or the DQS clock to the memory device120.

Referring toFIG.10B, after operations S1010, S1020, and S1030described inFIG.10Aare performed, the memory controller110may issue a write mode register (MRW) command to the memory device120in operation S1040. In order to set an operation condition for the memory device120, the memory controller110may configure information including a memory core parameter code, a peripheral circuit parameter code, and/or a 3-D DOC with appropriate bit values provided through the command/address (CA) bus, and provide the corresponding information to the memory device120.

In operation S1050, the memory device120may store the operation and control parameters and the 3-D DOC received through the command/address (CA) bus in the MRS122. The memory device120may be controlled by the control logic circuit220to operate as set in the operation and control parameters of the MRS122. The control logic circuit220may correct the DQS clock duty cycle based on the 3-D DOC of the MRS122.

Referring toFIG.11in conjunction withFIGS.1to9, the memory controller110may issue a clock training command to the memory device120in operation S1110.

In operation S1120, the memory device120may perform a 3-D duty offset search operation on the multi-phase clock by the clock training circuit124in response to the clock training command.

In operation S1130, the memory device120may store the 3-D DOC obtained as a result of the 3-D duty offset search operation of the clock training circuit124in a multi-purpose register (MPR) of the MRS122.

In operation S1140, the memory controller110may issue a mode register read (MRR) command to the memory device120. The memory device120may transmit information including the 3-D DOC stored in the MRS122to the memory controller110through the data DQ line. The memory controller110may provide a CLK clock whose timing is adjusted based on the 3-D DOC (3-D DOC) to the memory device120.

FIG.12is a block diagram illustrating a system1000to which a clock training method according to an example embodiment is applied.

Referring toFIG.12, the system1000may include a camera1100, a display1200, an audio processor1300, a modem1400, DRAMs1500aand1500b, flash memories1600aand1600b, I/O devices1700aand1700b, and an AP1800. The system1000may be implemented as, e.g., a laptop computer, a mobile phone, a smartphone, a tablet PC, a wearable device, a healthcare device, an Internet Of things (IOT) device, a server, a PC, etc.

The camera1100may capture a still image or video according to the user's control, and may store captured image/video data or transmit the captured image/video data to the display1200. The audio processor1300may process audio data included in the flash memories1600aand1600bor content of a network. The modem1400may modulate and transmit a signal to transmit/receive wired/wireless data, and may demodulate a signal to restore an original signal thereof at a receiving end. The I/O devices1700aand1700bmay include devices providing a digital input and/or output function such as a universal serial bus (USB) or storage, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, and a touch screen.

The AP1800may control an overall operation of the system1000. The AP1800may control the display1200so that a part of the content stored in the flash memories1600aand1600bis displayed on the display1200. When a user input is received through the I/O devices1700aand1700b, the AP1800may perform a control operation corresponding to the user input. The AP1800may include an accelerator block, which is a dedicated circuit for artificial intelligence (AI) data operation, or may include an accelerator chip1820separately from the AP1800. A DRAM1500bmay be additionally mounted on the accelerator block or the accelerator chip1820. The accelerator is a function block that professionally performs a certain function of the AP1800, and the accelerator may include a graphics processing unit (GPU) as a function block that specializes in graphic data processing, a neutral processing unit (NPU) as a block that specializes in AI calculation and inference, and a data processing unit (DPU) as a block that specializes in data transfer.

The system1000may include a plurality of DRAMs1500aand1500b. The AP1800may control the DRAMs1500aand1500bthrough a command and mode register (MRS) setting conforming to the Joint Electron Device Engineering Council (JEDEC) standard, or perform communication by setting a DRAM interface protocol to use company-specific functions such as low voltage/high speed/reliability and a cyclic redundancy check (CRC)/error correction code (ECC) function. For example, the AP1800may communicate with the DRAM1500athrough an interface conforming to JEDEC standards such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip1820may perform communication by setting a new DRAM interface protocol to control a DRAM1500bfor an accelerator having a band width higher than the DRAM1500a.

Although only the DRAMs1500aand1500bare illustrated inFIG.12, example embodiments may use, e.g., any memory of a PRAM, an SRAM, an MRAM, an RRAM, an FRAM or a hybrid RAM as long as a bandwidth, a response speed, and voltage conditions of the AP1800or the accelerator chip1820are satisfied. The DRAMs1500aand1500bhave relatively smaller latency and bandwidth than the I/O devices1700aand1700bor the flash memories1600aand1600b. The DRAMs1500aand1500bmay be initialized when the system1000is powered on and loaded with an operating system and application data to be used as temporary storage locations for the operating system and application data or as execution spaces for various software codes.

In the DRAMs1500aand1500b, addition/subtraction/multiplication/division operations, vector operations, address operations, or fast Fourier transform (FFT) operations may be performed. In addition, a function used for inference may be performed in the DRAMs1500aand1500b. Here, the inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training step of learning a model through various data and an inference step of recognizing data with the learned model. As an example, an image captured by the user through the camera1100may be signal-processed and stored in the DRAM1500b, and the accelerator block or accelerator chip1820may perform an AI data calculation to recognize data using the data stored in the DRAM1500band the function used in the inference.

The system1000may include a plurality of storage or a plurality of flash memories1600aand1600bhaving a larger capacity than the DRAMs1500aand1500b. The accelerator block or accelerator chip1820may perform a training step and AI data operation by using the flash memories1600aand1600b. In an example embodiment, the flash memories1600aand1600bmay perform the training step and the inference AI data calculation performed by the AP1800and/or the accelerator chip1820using a calculation device provided in the memory controller1610. The flash memories1600aand1600bmay store pictures taken through the camera1100or data transmitted through a data network. For example, augmented reality/virtual reality, high definition (HD), or ultra HD (UHD) content may be stored.

In order to reduce a clock training time between the components and find an optimal clock duty cycle, the system1000may perform a clock training method of generating a 3-D DOC for a multi-phase clock by simultaneously phase-sweeping three internal clock signals in a multi-phase clock by a duty adjustment step in order to reduce a clock training time between components and search for an optimal clock duty cycle. In an example embodiment, the clock training method includes (i) selecting a first phase offset point among phase offset points for sweeping a phase between internal clock signals in a first adjustment range of −n to +n steps, (ii) selecting a second phase offset point, among phase offset points of sweeping phases between first internal clock signals to a second adjustment range of −n/2 to +n/2 steps based on a first phase offset point as the origin, and iii) selecting a third phase offset point, among phase offset points of sweeping phases of second internal clock signals to a third adjustment range of −n/4 to +n/4 steps based on a second phase offset point as the origin, and providing the same as 3-D DOC.

The camera1100, display1200, audio processor1300, modem1400, DRAMs1500aand1500b, flash memories1600aand1600b, I/O devices1700aand1700band/or AP1800in the system1000may partially or entirely combine the embodiments described above with reference toFIGS.1to11.

By way of summation and review, a semiconductor memory may be generally controlled by providing commands, addresses, and clocks to a memory device. Various commands, addresses, and clock signals may be provided by, e.g., a memory controller. The command may control the memory device to perform various memory operations, e.g., a read operation to retrieve data from the memory device and a write operation to store data in the memory device. Data related to a command may be provided between the memory controller and the memory device at a known timing with respect to reception and/or transmission by the memory device.

A clock, such as a system clock signal and/or a data clock signal, may be provided to the memory device by the memory controller. The system clock may be used for a command and address timing, and the data clock may be used for a data write timing provided to the memory device and a data read timing provided from the memory device. A frequency of the data clock may be higher than a frequency of the system clock. For example, the frequency of the data clock may be an integer multiple of the frequency of the system clock.

The system clock provided to the memory device may be used to generate an internal clock signal that controls a timing of various internal circuits during a memory operation. Timing of an internal circuit may be important during the memory operation, and a timing deviation of a clock may cause malfunction. An example deviation in a clock timing may be duty cycle distortion, i.e., deviation from a 50% duty cycle.

The memory controller may employ training to adjust a duty cycle of a clock transmitted to the memory device to an ideal value of 50%. The memory device may generate a multi-phase clock from the received clock for a high-speed operation. Multi-phase clock signals may have a phase relationship of 90 degrees (0 degrees, 90 degrees, 180 degrees, 270 degrees, etc.) with respect to each other. The memory device may perform clock training to adjust the duty cycle of the multi-phase clock. Clock training of a single clock sweep method (in which each multi-phase clock is individually phase-swept) may be performed. In the single clock sweep method, sweeping one clock window may affect duty characteristics of the other clock signals, and because an unaffected window may occur in the entire multi-phase clock window, it may be difficult to find an optimal clock duty cycle. In addition, in the single clock sweep method, a significant amount of time may be involved for clock training as the phase sweep is sequentially and repeatedly performed.

As described above, embodiments relate to applications and methods, and more particularly, to an apparatus, a memory device, and an operating method thereof to simultaneously perform duty cycle training on a multi-phase clock to find a three-dimensional (3-D) duty offset code and reduce a clock training time.

Embodiments may provide an apparatus, a memory device, and an operating method thereof for searching for a three-dimensional (3-D) duty offset code and reducing a clock training time by simultaneously performing duty cycle training on a multi-phase clock three-dimensionally.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.