Patent ID: 12245420

DETAILED DESCRIPTION

For better understanding of the present invention, some embodiments of the present invention are listed below with the accompanying drawings, the composition and the desired effects of the present invention are described in detail for those skilled in the art. In addition, the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure.

Please refer toFIGS.1-8, which are schematic diagram showing steps of a method for forming a semiconductor memory device300in a first embodiment of the present invention. First, as shown inFIG.1, a substrate100is provided, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator (SOI) substrate, and at least one insulation area101, such as a shallow trench isolation (STI), is formed in the substrate100to define a plurality of active areas (AAs)103on the substrate100. Preferably, a plurality of active areas103extend parallel to each other and spaced apart from each other along a first direction D1, and are alternately disposed with each other, in which the first direction D1intersects and is not perpendicular to the y direction or the x direction, as shown inFIG.1. In one embodiment, the insulation area101is formed by etching a plurality of trenches (not shown in the drawing) in the substrate100, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto.

In addition, a plurality of buried gates (not shown in the drawing) may be formed in the substrate100, for example, the buried gates extend parallel to each other along a direction (such as y direction) and cross the active area103, so as to serve as buried word lines (BWLs, not shown in the drawing) of the semiconductor memory device300. A plurality of bit lines160and a plurality of contacts180(not shown inFIG.1) may be formed on the substrate100. For example, the bit lines160respectively extend in another direction (e.g., the x direction) perpendicular to the direction and cross the active area103. Although the buried gates are not specifically depicted in the drawings of the present embodiment, it can be easily understood by those skilled in the art that the bit lines160extending in the x direction should be perpendicular to the buried gates extending in the y direction from a top view, and the bit lines160cross the active area103and the buried gates at the same time.

As shown inFIG.1, the bit lines160further includes a plurality of first bit lines162and at least one second bit line164. The first bit lines162and the at least one second bit line164are respectively disposed in a memory cell region300aand a periphery region300b) of the semiconductor memory device300, and may be used as general bit lines (BLs) and dummy bit lines (dummy BLs) respectively. In particular, the at least one second bit line164may be located at a side outside all the first bit lines162, but not limited thereto. It can be easily understood by those skilled in the art that, under actual requirements of devices, the memory cell region300aand the periphery region300bmay also have other types of arrangement, and thus the first bit lines and the at least one second bit line may be adjusted to have other arrangement patterns or the at least one second bit line may be adjusted to have other numbers. For example, in one embodiment, the semiconductor memory device preferably includes two second bit lines164, which are respectively arranged at two opposite sides (i.e., upper and lower sides) of all the first bit lines162to isolate other external devices. Furthermore, in the present embodiment, a line width W2of each second bit line164(for example, the width in the y direction) is preferably larger than a line width W1of each first bit line162, but it is not limited thereto. In another embodiment, the at least one second bit line and the first bit lines may also be selectively made to have the same line width.

In detail, as shown inFIG.2, each bit line160is formed on the substrate100apart from each other and includes a semiconductor layer (e.g., polysilicon)161, a barrier layer163(e.g., titanium and/or titanium nitride), a conductive layer165(e.g., metal with low resistance such as tungsten, aluminum or copper), and a cap layer167(e.g., silicon oxide, silicon nitride or silicon oxynitride, etc.) stacked in sequence. It should be noted that a portion of the first bit lines162are formed on a dielectric layer130above the substrate100, in which the dielectric layer130preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure, but not limited thereto. Another portion of the first bit lines162further form bit line contacts (BLCs)160abelow each of them, which extend into the substrate100and directly contact the substrate100below (the active areas103). Furthermore, the bit line contacts160aare integrally formed with the semiconductor layer161of the another portion of the first bit lines162, as shown inFIG.2. On the other hand, the contacts180are also formed on the substrate100separately from each other and alternately disposed with the bit lines160. In addition, each of the contacts180and each of the bit lines160are insulated from each other through a spacer structure170. In one embodiment, the spacer structure170may optionally have a single layer structure or a composite layer structure as shown inFIG.2, which includes, for example, a first spacer171(for example, containing silicon nitride), a second spacer173(for example, containing silicon oxide) and a third spacer173(for example, containing silicon nitride) stacked in sequence, but not limited thereto. In addition, each of the contacts180further includes a plurality of first contacts182and at least one second contact184, wherein the first contacts182are disposed in the memory cell region300aof the semiconductor memory device300and directly contacts the underlying substrate100(including the active areas103and the insulation areas101) to serve as a storage node contact (SNC) of the semiconductor memory device300, and the second contact184is disposed in the periphery region300bof the semiconductor memory device300. In one embodiment, the contacts180include low resistance metal materials such as aluminum (Al), titanium (Ti), copper (Cu) or tungsten (W).

Then, a plurality of storage node pads (SN pads)211are formed on the substrate100. In particular, the storage node pads211are formed by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but not limited thereto. Referring toFIG.3andFIG.4, a metal layer210is formed above the contacts180and the bit lines160. The metal layer210is made of a low-resistance metal material such as aluminum, titanium, copper or tungsten, preferably a metal material different from the contacts180, but not limited thereto. Then, at least two self-aligned double patterning processes are sequentially performed to form a plurality of patterned masks221extending parallel to each other along a second direction D2and a plurality of patterned masks223extending parallel to each other along a second direction D3on the metal layer210. In particular, the second direction D2and the second direction D3intersect with each other and are not perpendicular to the y direction or the x direction respectively, for example, an included angle between the second direction D2or the second direction D3and the y direction or the x direction is about 60 to 120 degrees, as shown inFIG.3, but not limited thereto. Then, the relative positions of the storage node pads211are defined by the overlapped portions between the patterned masks221and the patterned masks223, and patterned masks221,223are formed as etching masks to perform an etching process to pattern the underlying metal layer210, and thus the storage node pads211may be formed, as shown inFIGS.5-6. It should be noted that, the storage node pads211are formed by controlling the overlapping portions of the patterned masks221and the patterned masks223, and a portion of the patterned masks223are not extended over the memory cell region300ato form a serrated edge. Then, the storage node pads211formed accordingly in the present embodiment are selectively above and aligned to each of the first contacts182within the memory cell region300aas shown inFIGS.5-6, and not above the second contact184within the periphery region300bas shown inFIGS.5-6, and not above the at least one second bit line164as shown inFIGS.5,7.

Subsequently, a capacitor structure250may be formed above the storage node pads211to directly contact and electrically connect with the storage node pads211below. In one embodiment, the manufacturing process of the capacitor structure250includes but not limited to the following steps. First, as shown inFIG.8, a dielectric layer230and a supporting layer structure240are formed on the substrate100. The dielectric layer230is disposed over the contacts180(including the first contacts182and the second contact184) and the bit lines160. Preferably, the thickness of the dielectric layer230is greater than the thickness of each of the storage node pads211, and thus the storage node pads211may be located in the dielectric layer230. The supporting layer structure240includes, for example, at least one oxide layer and at least one nitride layer alternately stacked. In the present embodiment, the supporting layer structure240includes, for example, a first supporting layer241(for example, including silicon oxide), a second supporting layer243(for example, including silicon nitride or silicon carbonitride), a third supporting layer245(for example, including silicon oxide) and a fourth supporting layer247(for example, including silicon nitride or silicon carbonitride, etc.) stacked in sequence from bottom to top, but not limited thereto. Preferably, the first supporting layer241and the third supporting layer245may have relatively large thicknesses, for example, about 5 times to 10 times more than other supporting layers (the second supporting layer243or the fourth supporting layer247), but not limited thereto. Therefore, the overall thickness of the supporting layer structure240may reach but not limited to about 1600 angstroms to about 2000 angstroms. It should be understood by those skilled in the art that the specific stacking number of the aforementioned oxide layer (such as the first supporting layer241or the third supporting layer245) and the aforementioned nitride layer (such as the second supporting layer243or the fourth supporting layer247) is not limited to the aforementioned number, but may be adjusted according to actual requirements, such as 3 layers, 4 layers or other numbers. Then, a plurality of first openings242, at least one second opening246and at least one third opening244are formed in the supporting layer structure240, all of which sequentially penetrate through the fourth supporting layer247, the third supporting layer245, the second supporting layer243, the first supporting layer241and part of the dielectric layer230. The first openings242are disposed within the memory cell region300, to respectively align to the storage node pads211(and the first contacts182) underneath, so that the top surfaces of the storage node pads211may be exposed from each of the first openings242. The at least one third opening244is disposed within the periphery region300bto align to the second contact184underneath. However, because the bottom surfaces of the third opening244is lower than the top surface of the dielectric layer230without penetrating the dielectric layer230, only part of the dielectric layer230is exposed from the at least one third opening244. The at least one second opening246is also disposed within the periphery region300b, outside all the first openings242and the third opening244, wherein the at least one second opening246is aligned to the at least one second bit line164located in the periphery region300b. The at least one second opening246also does not penetrate through the dielectric layer230to partially expose the dielectric layer230therefrom, as shown inFIG.8.

Then, as shown inFIG.9, bottom electrode layers251are formed to fill the first openings242, the at least one third opening244and the at least one second opening246, respectively. In particular, each of the bottom electrode layers251includes a low-resistance metal material such as aluminum, titanium, copper or tungsten, and preferably titanium, but not limited thereto. It should be noted that the bottom electrode layers251disposed in the first openings242directly contact the storage node pads211below. The bottom electrode layers251disposed in the at least one third opening244and the at least one second opening246directly contact the dielectric layer230, and are located directly above the second contact184and the at least one second bit line164, respectively. As shown inFIG.9, after the bottom electrode layers251are formed, an etching process is performed through a mask layer (not shown) to completely remove the oxide layer (such as the first supporting layer241or the third supporting layer245) in the supporting layer structure240and partially remove the nitride layer (such as the second supporting layer243or the fourth supporting layer247) in the supporting layer structure240.

Subsequently, as shown inFIG.10, a capacitor dielectric layer253and a top electrode layer255are sequentially formed on the bottom electrode layers251. In particular, part of the capacitor dielectric layer253and part of the top electrode layer255may be further filled between the remaining second supporting layer243and the fourth supporting layer247, and between the remaining second supporting layer243and the dielectric layer230. In one embodiment, the capacitor dielectric layer253includes a high dielectric constant dielectric material selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2) and zirconia-alumina-zirconia (ZAZ), and preferably includes zirconia-alumina-zirconia. The top electrode layer255includes low resistance metal materials such as aluminum, titanium, copper or tungsten, preferably titanium, but not limited thereto.

Thus, the manufacturing process of the capacitor structure250is completed. The capacitor structure250includes the bottom electrode layer251, the capacitor dielectric layer253, and the top electrode layer255stacked in sequence, thereby forming a plurality of vertically extending capacitors250a,250b, and250c. It should be noted that the capacitor structure250includes a plurality of the first capacitors250adisposed in the memory cell region300to align to the first contacts182, respectively. In particular, each of the first capacitors250amay be electrically connected with a transistor device (not shown) of the semiconductor memory device300through the storage node pad211and a storage node plug (i.e., the first contact182) below, and each of the first capacitors250amay thereby be used as a storage node (SN) of the semiconductor memory device300to maintain a good contact relationship between the capacitor structure250and the transistor device. On the other hand, the capacitor structure250further includes at least one second capacitor250band at least one third capacitor250cdisposed in the periphery region300b. Since there is no storage node pad211disposed under the second capacitor250band the third capacitors250, the second capacitor250band the third capacitors250cmay not be electrically connected with the storage node plug (i.e., the second contact184) below. The bottom surfaces of the second capacitor250band the third capacitor250c(i.e., the bottom surfaces of the bottom electrode layer251filling the third opening244and the second opening246) only contact the dielectric layer230to form an open circuit, which become a dummy storage node (dummy SN) and are isolated from the adjacent storage nodes to maintain the overall device performance. In particular, the bottom surfaces of the second capacitor250band the third capacitor250care lower than the top surface of the dielectric layer230, as shown inFIG.10. In addition, the second capacitor250bis located outside all the first capacitors250aand the third capacitor250cto align to the second bit line164in the periphery region300b.

Although the schematic cross-sectional view shown inFIG.10only shows that a single second capacitor250bis located on the second bit line164, and a single third capacitor250cis located outside the first capacitor250awithin the periphery region300b, it should be easily understood by those skilled in the art that a plurality of third capacitors250cand a plurality of second capacitors250bare disposed within the periphery region300b. For example, if being viewed from a schematic cross-sectional view along the cross line B-B′, a plurality of the second capacitors250bis located on the second bit line164, as shown inFIG.11. Therefore, the semiconductor memory device300of the present embodiment may form a dynamic random access memory (DRAM) device, in which at least one transistor device and at least one first capacitor250aconstitute the smallest memory cell in the DRAM array to receive voltage information from the bit lines160and the buried word lines.

Thus, the semiconductor memory device300in the first embodiment of the present invention is completed. According to the forming method of the present embodiment, the storage node pads211are formed by controlling the overlapping parts of the patterned mask221and the patterned mask223, and the storage node pads211are thereby disposed above the first contacts182within the memory cell region300a, but not above the second contact184within the periphery region300b. In this way, after the capacitor structure250is formed, the first capacitors250awhich may be used as storage nodes and the at least one second capacitor250band/or the at least one third capacitors250cwhich may be used as a dummy storage node may be respectively formed. In particular, the storage nodes (i.e., the first capacitors250a) are electrically connected with the transistor device (not shown) of the semiconductor storage device300through the storage node pads211and the storage node plugs (i.e., the first contact182) below, while the dummy storage nodes (i.e., the at least one second capacitor250band/or the at least one third capacitors250c) are not provided with the storage node pad211below, and thus it may not be electrically connected with the storage node plugs (i.e., the second contact184) below. The arrangement of the dummy storage nodes may stabilize and improve the performance of the storage nodes, and may be used to isolate the adjacent storage nodes to maintain the overall device performance of the semiconductor storage device300.

In addition, it should be easily understood by those skilled in the art that, on the prerequisite for meeting the actual product requirements, there may be other types for forming the semiconductor memory device and the method for forming thereof according to the present invention, which are not limited to the foregoing. For example, the dummy storage nodes may have other types optionally. Other embodiments or variations of the forming method of the semiconductor memory device in the present invention will be further described below. To simplify the description, the follow description mainly focuses on the difference of each embodiment, and will not repeat the same description. In addition, the same components in each embodiment of the present invention are labeled with the same reference numerals, so as to facilitate cross-reference among the embodiments.

Please refer toFIG.12, which shows steps of a method for forming a semiconductor memory device400in a second embodiment of the present invention. The forming steps of the front end of the semiconductor memory device400in the present embodiment are substantially the same as those steps of the front end of the semiconductor memory device300in the first embodiment described above, and will not be repeated here. The main difference between the present embodiment and the first embodiment is that at least one second capacitor450bpenetrates through the dielectric layer230and may directly contact the cap layer167of the second bit line164.

In detail, the forming method of the present embodiment further controls the etching process conditions when forming the openings in the supporting layer structure240, and selectively makes the second opening (not shown) aligned to the second bit line164penetrate the dielectric layer230and stop on the top surface of the cap layer167of the second bit line164, therefore, the cap layer167of the second bit line164may be exposed from the second opening. Subsequently, the bottom electrode layer251, the capacitor dielectric layer253and the top electrode layer255are sequentially formed to form the capacitor structure450as shown inFIG.12. In particular, the at least one second capacitor450bis aligned to the second bit line164in the periphery region300b, and extends into the dielectric layer230and directly contacts the top surface of the cap layer167of the second bit line164through the bottom electrode layer251, therefore, the at least one second capacitor450bonly contacts the dielectric layer230and the cap layer167to form an open circuit, thereby becoming the dummy storage node. Under this arrangement, the semiconductor memory device400of the present embodiment may also form a dynamic random access memory device, and the adjacent storage nodes are isolated by the at least one second capacitor450band the at least one third capacitor250c, so as to maintain its overall device performance.

Please refer toFIG.13, which shows steps of a method for forming a semiconductor memory device500in a third embodiment of the present invention. The forming steps of the front end of the semiconductor memory device500in the present embodiment are substantially the same as the forming steps of the front end of the semiconductor memory device300in the first embodiment described above, and will not be repeated here. The main difference between the present embodiment and the first embodiment is that at least one second capacitor550bpenetrates through the dielectric layer230and further extends into a portion of the cap layer167of the second bit line164.

In detail, the forming method of the present embodiment further controls the etching process conditions when forming the openings in the supporting layer structure240, and selectively makes the second opening (not shown) aligned to the second bit line164penetrate through the dielectric layer230and part of the cap layer167of the second bit line164, therefore, the second opening may extend into part of the cap layer167. In other words, the bottom surface of the second opening may be lower than the top surface of the second bit line164, and part of the cap layer167may be exposed from the second opening. Subsequently, the bottom electrode layer251, the capacitor dielectric layer253and the top electrode layer255are sequentially formed to form the capacitor structure550as shown inFIG.13. In particular, at least one second capacitor550bis aligned to the second bit line164in the periphery region300b, and extends into the part of the cap layer167through the bottom electrode layer251and directly contacts the second bit line164. The bottom surface of at least one second capacitor550b(that is, the bottom surface of the bottom electrode layer251filling the second opening) may be lower than the top surface of the second bit line164, and the at least one second capacitor550bonly contacts the cap layer167to form an open circuit, thereby becoming the dummy storage node. Under this arrangement, the semiconductor memory device500of the present embodiment may also form a dynamic random access memory device, and the adjacent storage nodes are isolated by the second capacitor550band the third capacitors250c, so as to maintain its overall device performance.

Please refer toFIG.14, which shows steps of a method for forming a semiconductor memory device600in a fourth embodiment of the present invention. The forming steps of the front end of the semiconductor memory device600in the present embodiment are substantially the same as the forming steps of the front end of the semiconductor memory device300in the first embodiment described above, and will not be repeated here. The main difference between the present embodiment and the first embodiment is that at least one second capacitor650bis located above part of the second bit line164and part of the contact180at the same time.

In detail, as shown inFIG.14, during the process of forming the storage node pads211, each of the storage node pads211only partially overlaps with the underlying first contact182so that a larger process window can be obtained. Subsequently, the bottom electrode layer251, the capacitor dielectric layer253and the top electrode layer255are formed in sequence to form a capacitor structure650as shown inFIG.14. In this way, each of the storage node pads211may be located above a part of each first contact182, the spacer structure170and a part of each first bit line162at the same time, and the first capacitor650aformed later may also be located above the part of each first contact182, the spacer structure170and the part of each first bit line162accordingly. In addition, the second capacitor650blocated in the periphery region300bmay be located above a part of the second contact184, the spacer structure170and a part of the second bit line164at the same time. It should be noted that in the present embodiment, the etching process conditions may be further controlled to selectively make the opening (not shown) located in the peripheral region300bonly partially penetrate the dielectric layer230, so as to make the bottom surface of the second capacitor650b(that is, the bottom surface of the bottom electrode layer251filling the opening) only contact the dielectric layer230, as shown inFIG.14, but not limited thereto. Under this arrangement, the semiconductor memory device600of the present embodiment may also form a dynamic random access memory device, and the adjacent storage nodes are isolated by the second capacitor650b, so as to maintain its overall device performance.

In general, the present invention forms the storage node pads on the substrate through the self-aligned double patterning process or the self-aligned reverse patterning process, and forms the storage node pads only within the memory cell region to align to the contacts by controlling the overlapping parts of the patterning masks. In this way, after the capacitor structure is formed, the first capacitors that may be used as storage nodes and the second capacitor that may be used as a dummy storage node may be respectively formed, in which the storage nodes (i.e., the first capacitor) are electrically connected with the transistor device (not shown) of the semiconductor storage device through the storage node pads and the storage node plugs (i.e., the contacts) below. While there is no storage node pad under the dummy storage node (i.e., the second capacitor), instead, the dummy storage node directly contacts the cap layer of the dummy bit line, and are thereby not electrically connected with the storage node plug (i.e., the contact), so that the adjacent storage nodes may be isolated to maintain the overall device performance of the semiconductor storage device.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.