Patent ID: 12242725

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments set forth herein are illustrated for the purpose of clearly describing the technical ideas of the present disclosure, and are not intended to be limited to particular embodiments. The technical ideas of the present disclosure include various modifications, equivalents, and alternatives of each embodiment set forth herein, and embodiments obtained by selectively combining all or part of each embodiment. In addition, the scope of the technical ideas of the present disclosure is not limited to various embodiments or specific descriptions thereof presented below.

Terms used herein, including technical or scientific terms, may have the meaning commonly understood by those of ordinary skill in the art to which the present disclosure pertains unless defined otherwise.

As used herein, expressions such as “include(s),” “may include,” “is/are provided with”, “may be provided with,” “have/has,” “can have,” and the like mean that target features (e.g., functions, operations, components, or the like) exist, and do not preclude the presence of other additional features. That is, such expressions should be understood as open-ended terms that imply the possibility of including other embodiments.

Singular expressions herein include plural expressions unless the context clearly dictates that they are singular. Further, plural expressions include singular expressions unless the context clearly dictates that they are plural. Throughout the specification, when a part is said to include a component, this means that it may further include other components rather than excluding other components unless particularly described to the contrary.

Further, the term ‘module’ or ‘part’ used herein refers to a software or hardware component, and the ‘module’ or ‘part’ performs certain roles. However, the ‘module’ or ‘part’ is not meant to be limited to software or hardware. The ‘module’ or ‘part’ may be configured to reside on an addressable storage medium or may be configured to run one or more processors. Therefore, as one example, the ‘module’ or ‘part’ may include at least one of components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, or variables. Functions provided within the components and the ‘modules’ or ‘parts’ may be combined into a smaller number of components and ‘modules’ or ‘parts,’ or may be further separated into additional components and ‘modules’ or ‘parts.’

According to one embodiment of the present disclosure, a ‘module’ or ‘part’ may be implemented with a processor and a memory. The ‘processor’ should be interpreted broadly so as to encompass general-purpose processors, central processing units (CPUs), microprocessors, digital signal processors (DSPs), controllers, microcontrollers, state machines, and the like. In some circumstances, the ‘processor’ may also refer to an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), or the like. The ‘processor’ may also refer to, for example, a combination of processing devices, such as a combination of a DSP and a microprocessor, a combination of a plurality of microprocessors, a combination of one or more microprocessors combined with a DSP core, or a combination of any other such components. In addition, the ‘memory’ should be interpreted broadly so as to encompass any electronic component capable of storing electronic information. The ‘memory’ may also refer to various types of processor-readable media, such as random-access memory (RAM), read-only memory (ROM), non-volatile random-access memory (NVRAM), programmable read-only memory (PROM), erasable-programmable read-only memory (EPROM), electrically erasable PROM (EEPROM), flash memory, magnetic or optical data storage, registers, etc. A memory is said to be in electronic communication with a processor if the processor can read information from and/or write information to the memory. A memory integrated with a processor is in electronic communication with the processor.

As used herein, expressions such as “first” and “second” are used to distinguish one object from another when referring to a plurality of objects of the same kind unless the context indicates otherwise, and do not limit the order or importance among the relevant objects.

As used herein, expressions such as “A, B, and C,” “A, B, or C,” “A, B, and/or C,” or “at least one of A, B, and C,” “at least one of A, B, or C one,” “at least one of A, B, and/or C,” “at least one selected from A, B, and C,” “at least one selected from A, B, or C,” and “at least one selected from A, B, and/or C” may mean all possible combinations of each listed item or listed items. For example, “at least one selected from A and B” may refer to all of (1) A, (2) at least one of A's, (3) B, (4) at least one of B's, (5) at least one of A's and at least one of B's, (6) at least one of A's and B, (7) at least one of B's and A, (8) A and B.

As used herein, the expression “based on” is used to describe one or more factors that affect the action or operation of a decision or determination described in the phrase or sentence including the expression, and this expression does not preclude additional factors that affect the action or operation of that decision or determination.

As used herein, the expression that a component (e.g., a first component) is “connected” or “coupled” to another component (e.g., a second component) may mean that said component is connected or coupled to said another component directly, as well as connected or coupled via yet another component (e.g., a third component).

As used herein, the expression “configured to” may have the meaning of “set to,” “having the ability to,” “modified to,” “made to,” “capable of,” etc., depending on the context. The expression is not limited to the meaning of “designed specifically in hardware,” and for example, a processor configured to perform a particular operation may refer to a generic-purpose processor capable of performing that particular operation by executing software.

Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings and description of the drawings, identical or substantially equivalent components may be given the same reference numerals. Further, in the description of various embodiments below, repetitive descriptions of the same or corresponding components may be omitted, which, however, does not mean that such components are not included in that embodiment.

FIG.1is an example diagram conceptually illustrating a computing system100including an electronic device130according to one embodiment of the present disclosure.

A computing system100in accordance with the present disclosure may be a storage server or other kind of server that may be used in a data center. As shown inFIG.1, the computing system100may include a host processor110(e.g., x86 CPU, ARM, RISC-V), an electronic device130, and a non-volatile storage device140. The host processor110may be connected to a host memory120. The electronic device130may include a volatile memory device132.

The computing system100in accordance with the present disclosure may have a scalable device structure that can use the volatile memory device132of the electronic device130as an intermediate storage medium and the non-volatile storage device140as a final storage medium. The host processor110may recognize the total capacity of the non-volatile storage device140connected to the electronic device130.

The host processor110may communicate with the electronic device130by using a first interface150. The first interface150may be a serial interface, and may be, for example, an interface using PCIe or a compute express link (CXL) protocol. The electronic device130may communicate with the non-volatile storage device140by using a second interface160. The second interface160may be a serial interface.

In the computing system100in accordance with the present disclosure, the first interface150may be a byte-addressable protocol (or byte addressing protocol), and the second interface160may be a block-addressable protocol (or block addressing protocol). The host processor110may assign addresses in bytes and read and write data to the electronic device130. The electronic device130may assign addresses in blocks and read and write data to the non-volatile storage device140. The electronic device130may retrieve data in blocks from the non-volatile storage device140based on the byte addresses and store the data in the volatile memory device132of the electronic device130. The electronic device130may access data corresponding to the address requested by the host processor110out of data stored in the volatile memory device132.

According to one embodiment, the electronic device130may internally have a cache for data stored in the volatile memory device132to improve performance.

FIG.1illustrates that the non-volatile storage device140is configured separately from the electronic device130for the convenience of description. However, the present disclosure is not limited thereto. For example, in the present disclosure, the non-volatile storage device140may be configured to be integrated with the electronic device130.

FIG.2is a block diagram of a computing system100including an electronic device130in accordance with one embodiment of the present disclosure.

As shown inFIG.2, the computing system100includes a host processor110, an electronic device130, and a non-volatile storage device140. The host processor110may include a communication port210. The electronic device130may include a volatile memory device132and a controller240.

The host processor110may refer to a set of one or more processors. The host processor110may control at least one component of a device or terminal (e.g., the electronic device130) connected to the host processor110by driving software (e.g., commands, programs, etc.). In addition, the host processor110may perform operations such as various computations, processing, data generation or processing. Further, the host processor110may load data or the like from various memory devices or storage devices, or store data or the like in the memory devices or storage devices.

The controller240may have one or more volatile memory channels, and may communicate with individual components or the volatile memory device132via these volatile memory channels. The volatile memory device132may be, for example, a DIMM-type DRAM. The controller240may include a first communication port220. For example, the first communication port220may be a PCIe end point or a CXL end point. According to one embodiment, the controller240may further include a second communication port230. For example, the second communication port230may be a PCIe root complex port.

The controller240may communicate with the host processor110over a first interface150via the first communication port220and the communication port210. Further, the controller240may communicate with the volatile memory device132over a third interface250. In addition, the controller240may communicate with the non-volatile storage device140over a second interface160via the second communication port230. Here, the first interface150and the second interface160may be serial interfaces, and the third interface250may be a parallel interface.

The controller240may communicate with the host processor110in a first protocol. Further, the controller240may communicate with the volatile memory device132in a second protocol. Moreover, the controller240may communicate with the non-volatile storage device140in a third protocol. Here, the first protocol and the second protocol may be byte-addressable protocols that allow data to be read and written by assigning addresses in bytes, and the third protocol may be a block-addressable protocol that allows data to be read and written by assigning addresses in blocks.

The non-volatile storage device140may include one or more non-volatile storages. According to one embodiment, as many non-volatile storages as the interfaces allow may be connected directly to the second communication port230. Here, the non-volatile storages may include hard disk drives (HDDs), solid-state drives (SSDs), and the like.

The controller240in accordance with the present disclosure may receive a swap-out request or command for data in pages (hereinafter referred to as ‘page data’) from the host processor110. According to one embodiment, the host operating system (OS) may determine page data to be swapped out. For example, the host operating system may determine to swap out the page data that has not been accessed for a predetermined period of time or has a low frequency of accesses out of page data stored in the host memory120. The host processor110may transfer the swap-out request including page information to the controller240via the communication port210and the first communication port220. For example, the page information may include a process ID and an address for each program.

The controller240may determine the availability of the volatile memory device132in response to the swap-out request. If it is determined that the volatile memory device132is not available, the controller240may transfer an error message (e.g., a memory full error) to the host processor110. If it is determined that the volatile memory device132is available, the controller240may receive the page data from the host processor110and compress and store it in the volatile memory device132.

The controller240in accordance with the present disclosure may divide and manage the volatile memory device132into a compressed memory pool and a temporary memory pool. For example, the controller240may define and manage a first area of the volatile memory device132as a compressed memory pool, and define and manage a second area that is different from the first area as a temporary memory pool. When storing certain data in the volatile memory device132, the controller240may determine to store the data in the compressed memory pool or the temporary memory pool depending on whether the data is compressed.

According to one embodiment, the controller240may store the page data requested to be swapped out in a first temporary buffer in the temporary memory pool. For example, the size of the first temporary buffer may be allocated to be the same as that of the page data (e.g., 4 KB). The controller240may store the page data requested to be swapped out in a first temporary buffer in the temporary memory pool. The controller240may compress and store the page data stored in the first temporary buffer in a second temporary buffer in the temporary memory pool. For example, the size of the second temporary buffer may be allocated to be the same as that of the first temporary buffer (e.g., 4 KB). The controller240may store the compressed data stored in the second temporary buffer in a storage area in the compressed memory pool. The size of the storage area may correspond to the size of compressed data. For example, the size of the storage area may be equal to or proportional to the size of compressed data. The controller240may record the location of the storage area in the metadata of the page data requested to be swapped out. In addition, the controller240may notify the host processor110of the completion of processing of the swap-out request.

In general, even if data of the same size are compressed, the sizes of compressed data generated as a result of compression may be different. According to the controller240in accordance with the present disclosure, after compressing the page data in the temporary memory pool and identifying the size of the compressed data, a size corresponding to the size of the compressed data may be allocated in the compressed memory pool and the compressed data may be stored. With this configuration, effective management of the compressed memory pool is possible, and the availability of the compressed memory pool can be increased.

The controller240in accordance with the present disclosure may receive a swap-in request or command of data in pages from the host processor110. According to one embodiment, the host operating system may determine the page data to be swapped in and the location where it is to be stored in the host memory120. The host processor110may transfer the swap-in request including the page information and location information on the host memory120to the controller240via the communication port210and the first communication port220. For example, the page information may include a process ID and an address for each program.

The controller240may search for the compressed data in which the page data is compressed in response to the swap-in request. According to one embodiment, the controller240may identify the location of the compressed data in the volatile memory device132based on the page information and the metadata of the page data. The compressed data may be located in the compressed memory pool of the volatile memory device132. According to one embodiment, the controller240may decompress and store the compressed data in a temporary buffer in the temporary memory pool. For example, the size of the temporary buffer may be allocated to be the same as the page data (e.g., 4 KB).

The controller240may transfer the decompressed data to the host processor110. For example, the controller240may transfer the decompressed data to the location information on the host memory120included in the swap-in request. The controller240may notify the host processor110of the completion of processing of the swap-in request. In addition, the controller240may initialize the information of the metadata of the page data requested to be swapped in.

According to the computing system100in accordance with the present disclosure, since the host processor110does not have to directly perform a compression operation function or manage compressed data, overall system availability can be improved. In addition, since the electronic device130in accordance with the present disclosure provides offloading to the compression function and data transmission while expanding the capacity of the host memory120, overall system performance can be improved.

FIG.3is a block diagram of a controller240in accordance with one embodiment of the present disclosure.

As shown inFIG.3, the controller240may include a swap controller320(or may also be referred to as a ‘zswap controller’), a memory manager330, and a compression and decompression module340. In addition, the controller240may further include a direct memory access (DMA) module310, a memory controller350, and a cache memory360.

In order to process the swap-out request of the host processor110, the swap controller320may request allocation of a memory space in the volatile memory device132based on the page information on the page data included in the swap-out request and may control compression of the page data. The memory manager330may secure an empty space in the volatile memory device132according to the determination of the swap controller320. The memory manager330may divide and manage the volatile memory device132into a compressed memory pool and a temporary memory pool. The compression and decompression module340(or a compressor included in the compression and decompression module340) may compress the page data according to the determination of the swap controller320.

In order to process the swap-in request of the host processor110, the swap controller320may identify the storage location of the compressed data of the corresponding page data in the volatile memory device132based on the page information on the page data included in the swap-in request and the metadata of the page data. The swap controller320may control the decompression of the compressed data. The memory manager330may secure an empty space in the volatile memory device132according to the determination of the swap controller320. The compression and decompression module340(or a decompressor included in the compression and decompression module340) may decompress the compressed data according to the determination of the swap controller320.

The DMA module310may receive data to be swapped out from the host processor110or transmit data to be swapped in by using a predetermined protocol. In addition, the cache memory360may be configured to store data that has ever been accessed or is expected to be accessed. The memory controller350may be connected with the volatile memory device132and the cache memory360. The memory controller350may be configured to access the volatile memory device132and allow a data read or write.

The DMA module310, the swap controller320, the memory manager330, the compression and decompression module340, and the memory controller350shown inFIG.3may each be implemented as a hardware device or software code. According to one embodiment, the DMA module may be implemented as a hardware device, and the other components may be implemented as software code. According to one embodiment, the compression and decompression module340may be implemented as a mixture of hardware devices and software code. For example, the decompressor of the compression and decompression module340may be implemented as hardware, and the compressor may be implemented as software. In addition,FIG.3illustrates the components of the controller240by way of example, and the present disclosure is not limited thereto. For example, it may be implemented such that some of the components shown inFIG.3may be omitted or functions of particular components may be included in other components.

In the following, a process in which a swap-out request is processed in the electronic device130will be described with reference toFIGS.4and5, and a process in which a swap-in request is processed in the electronic device130will be described with reference toFIGS.6and7.

FIG.4is a flowchart400regarding an operation in which a controller240processes a swap-out request according to one embodiment of the present disclosure, andFIG.5is a diagram for describing an operation in which data to be swapped out is compressed in a volatile memory device132according to one embodiment of the present disclosure.

The controller240may receive a swap-out request of data in pages from the host processor110(S410). According to one embodiment, the host operating system may determine to swap out predetermined page data. The swap controller320may receive information on page data to be swapped out from the host processor110via the communication port210and the first communication port220. The swap controller320may determine the availability of the volatile memory device132. If it is determined that the volatile memory device132is not available, the swap controller320may return an error message (e.g., a memory full error) to the host processor110. If it is determined by the swap controller320that the volatile memory device132is available, the process may proceed to the next step S420.

Next, the controller240may store the page data in the temporary memory pool of the volatile memory device132(S420). According to one embodiment, the swap controller320may request the memory manager330to allocate a temporary buffer in the temporary memory pool. The memory manager330may allocate a first temporary buffer in the temporary memory pool of the volatile memory device132according to the request of the swap controller320. Once the allocation of the first temporary buffer is completed, the swap controller320may request the DMA module310to receive the page data. The DMA module310may receive the page data to be swapped out from the host processor110or the host memory120via the first communication port220according to the request of the swap controller320. The DMA module310may store the received page data in the first temporary buffer of the volatile memory device132allocated by the memory manager330.

Referring toFIG.5, the memory manager330allocates a temporary buffer (a)512of a predetermined size (e.g., 4 KB) in the temporary memory pool510of the volatile memory device500. The page data530to be swapped out may be stored in the temporary buffer (a)512.

Next, the controller240may compress and store the page data in the temporary memory pool (S430). According to one embodiment, the swap controller320may request allocation of a temporary buffer that is different from the first temporary buffer in the temporary memory pool of the memory manager330. The memory manager330may allocate a second temporary buffer in the temporary memory pool of the volatile memory device132according to the request of the swap controller320. Once the allocation of the second temporary buffer is completed, the swap controller320may request the compression and decompression module340(or the compressor included in the compression and decompression module340) to compress for the first temporary buffer. The compression and decompression module340may compress and store the page data stored in the first temporary buffer in the second temporary buffer. The compression and decompression module340may identify the size of compressed data in which the page data is compressed. The compression and decompression module340may transfer the size of the compressed data identified to the swap controller320.

Referring toFIG.5, the memory manager330allocates a temporary buffer (b)514of a predetermined size (e.g., 4 KB) in the temporary memory pool510of the volatile memory device502. The compressed data532of the page data530may be stored in the temporary buffer (b)514.

According to one embodiment, the size of the temporary buffer (b)514may be set to be equal to the size of the temporary buffer (a)512. As shown inFIG.5, as a result of compression by the compression and decompression module340, the size of the compressed data532(e.g., 2.4 KB) may be less than the size of the temporary buffer (b)514. In contrast, if the size of the compressed data532is greater than the size of the temporary buffer (b)514as a result of the compression by the compression and decompression module340, the compressed data may not be stored in the temporary buffer (b)514. In this case, the compression and decompression module340may transfer an error message (e.g., compression failed or data capacity exceeded) to the swap controller320. With this configuration, it is possible to recognize or prevent the case where the size of compressed data gets larger than the size of data before compression. As a result, the volatile memory device132can be managed more efficiently.

Next, the controller240may store the compressed data in a storage area in the compressed memory pool (S440). According to one embodiment, the swap controller320may request allocation of a storage area in the compressed memory pool of the memory manager330. For example, the size of the storage area may be equal to that of the compressed data or may be related to the size of the compressed data. The memory manager330may allocate a storage area in the compressed memory pool of the volatile memory device132according to the request of the swap controller320. Once the allocation of the storage area is completed, the swap controller320may copy the compressed data stored in the second temporary buffer to the storage area.

Referring toFIG.5, the memory manager330allocates a storage area (c)522as large as the size of the compressed data (e.g., 2.4 KB) in the compressed memory pool520of the volatile memory device504. The compressed data532may be stored in the storage area (c). With this configuration, a memory space can be allocated in the compressed memory pool only as large as the size of the compressed data, allowing for more efficient management of memory resources.

The swap controller320may request the memory manager330to deallocate the first temporary buffer. The memory manager330may return the first temporary buffer to the temporary memory pool at the request of the swap controller320. For example, the deallocation time point of the first temporary buffer may be any one of after the compressed data is stored in the second temporary buffer, after the storage area is allocated, and after the compressed data is copied to the storage area. In addition, the swap controller320may request the memory manager330to deallocate the second temporary buffer. The memory manager330may return the second temporary buffer to the temporary memory pool at the request of the swap controller320. For example, the deallocation time point of the second temporary buffer may be after the compressed data is copied to the storage area.

Referring toFIG.5, the memory manager330may return the temporary buffer (a)512to the temporary memory pool510of the volatile memory device504at any one time point of after the compressed data532is stored in the temporary buffer (b)514, after the storage area (c)522is allocated, and after the compressed data532is copied to the storage area (c)522. In addition, the memory manager330may return the temporary buffer (b)514to the temporary memory pool510of the volatile memory device506at a time point after the compressed data532is copied to the storage area (c)522. With this configuration, temporary buffers in the temporary memory pool are always returned when a series of compression and storage processes are completed, allowing for more efficient management of memory resources.

Next, the controller240may record the location of the storage area in the metadata of the page data (S450). According to one embodiment, the swap controller320may record the location of the storage area in which the compressed data is stored in the metadata of the page data requested to be swapped out. For example, the metadata may be stored in one area of the volatile memory device132. The metadata may be called by the host processor110.

Next, the controller240may notify the host processor110of the completion of processing of the swap-out request (S460). According to one embodiment, the swap controller320may notify the host processor110of the completion of processing of the swap-out request. The host operating system may recognize that the swap-out request has been processed.

Since the electronic device130in accordance with the present disclosure can take over at least part of the compression operation function of the host processor110, the performance of the entire computing system100can be improved by allowing the host processor110to be utilized for processing other than compression.

FIG.6is a flowchart600regarding an operation in which a controller240processes a swap-in request according to one embodiment of the present disclosure, andFIG.7is a diagram for describing an operation in which data to be swapped in is decompressed in a volatile memory device132according to one embodiment of the present disclosure.

The controller240may receive a swap-in request of data in pages (S610). According to one embodiment, the host operating system may determine a swap-in of predetermined page data. The swap controller320may receive information on the page data to be swapped-in (or page information) and location information to be stored in the host memory120from the host processor110via the communication port210and the first communication port220. For example, the page information may include a process ID and an address for each program.

Next, the controller240may identify the location of the compressed data in the volatile memory device132based on the metadata of the data (S620). According to one embodiment, the swap controller320may identify the location of the compressed data in the volatile memory device132based on the page information and the metadata of the page data. For example, the metadata of the page data might have been recorded by the swap controller320when the corresponding page data was swapped out. The compressed data may be located in the compressed memory pool of the volatile memory device132.

Referring toFIG.7, the swap controller320may identify the location of the storage area (a)722in which the compressed data730is stored in the compressed memory pool720of the volatile memory device700. For example, the size of the storage area (a)722(e.g., 2.4 KB) may be equal to that of the compressed data730.

Next, the controller240may decompress and store the compressed data in the temporary memory pool (S630). According to one embodiment, the swap controller320may request the memory manager330to allocate a temporary buffer in the temporary memory pool. The memory manager330may allocate a temporary buffer in the temporary memory pool of the volatile memory device132at the request of the swap controller320. Once the allocation of the temporary buffer is completed, the swap controller320may request the compression and decompression module340(or the decompressor included in the compression and decompression module340) to decompress for the temporary buffer. The compression and decompression module340may decompress the compressed data stored in the storage area and store it in the temporary buffer.

Referring toFIG.7, the memory manager330allocates a temporary buffer (b)712of a predetermined size (e.g., 4 KB) in the temporary memory pool710of the volatile memory device702. The decompressed data732in which the compressed data730has been decompressed may be stored in the temporary buffer (b)712.

Next, the controller240may transfer the decompressed data to the host processor110(S640). According to one embodiment, the swap controller320may request the DMA module310to transfer the decompressed data. The DMA module310may transfer the page data to be swapped in (i.e., the decompressed data) to the host processor110or the host memory120via the first communication port220at the request of the swap controller320.

Next, the controller240may notify the host processor110of the completion of processing of the swap-in request (S650). According to one embodiment, the swap controller320may notify the host processor110of the completion of processing of the swap-in request. The host operating system may recognize that the swap-in request has been processed.

Next, the controller240may initialize the information of the metadata of the data (S660). According to one embodiment, the swap controller320may initialize the information of the metadata of the page data requested to be swapped in.

The swap controller320may request the memory manager330to deallocate the storage area. The memory manager330may return the storage area to the compressed memory pool at the request of the swap controller320. For example, the deallocation time point of the storage area may be after the decompressed data has been transferred to the host processor110. In addition, the deallocation time point of the storage area may be substantially the same as the time point of initializing the information of the metadata of the page data requested to be swapped in. Referring toFIG.7, the memory manager330may deallocate the storage area (a)722in the compressed memory pool720of the volatile memory device702.

Further, the swap controller320may request the memory manager330to deallocate the temporary buffer (b). For example, the deallocation time point of the temporary buffer (b) may be after the decompressed data has been transferred to the host processor110. The memory manager320may return the temporary buffer (b) to the temporary memory pool710at the request of the swap controller320. Referring toFIG.7, the memory manager330may deallocate the temporary buffer (b)712in the temporary memory pool710of the volatile memory device704.

According to the electronic device130in accordance with the present disclosure, temporary buffers in the temporary memory pool are always returned when a series of decompression and transfer processes are completed, allowing for more efficient management of memory resources. In addition, since the electronic device130in accordance with the present disclosure provides offloading to the decompression function and data transmission while expanding the capacity of the host memory120, overall system performance can be improved.

FIG.8is a flowchart800regarding an operation in which an electronic device130processes a swap-out request according to another embodiment of the present disclosure.

In the present embodiment, the host operating system performs at least some functions of the management for the compressed memory pool of the volatile memory device132. Some steps of the embodiment according toFIG.8may be the same as or similar to some steps of the embodiment according toFIG.4, and detailed descriptions of the same or corresponding steps will be omitted. For example, steps S810to S830ofFIG.8may be the same as or correspond to steps S410to S430ofFIG.4, and steps S850to S870ofFIG.8may be at least partially the same as or correspond to steps S440to S460ofFIG.4.

The controller240may receive a swap-out request of data in pages from the host processor110(S810). Next, the controller240may store the page data in the temporary memory pool of the volatile memory device132(S820). Next, the controller240may compress and store the page data in the temporary memory pool (S830).

Next, the controller240may transfer the size of the compressed data to the host processor110(S840). According to one embodiment, when the compressed data in which the page data is compressed by the compression and decompression module340is generated, the swap controller320may transfer the size of the compressed data to the host processor110. The size of the compressed data may be identified by the compression and decompression module340and transferred to the swap controller320.

Next, the controller240may store the compressed data at the address received from the host processor110(S850). According to one embodiment, the host operating system may allocate a storage area in which the compressed data is to be stored in a memory area of the volatile memory device132. For example, the host operating system may allocate a predetermined area in the compressed memory pool of the volatile memory device132as the storage area. The size of the storage area may be equal to or correspond to the size of the compressed data transferred by the swap controller320. The host processor110may transfer the address of the allocated storage area to the controller240. The swap controller320may store the compressed data at the received address. For example, the swap controller320may copy the compressed data stored in the second temporary buffer to the storage area.

The swap controller320may request the memory manager330to deallocate the second temporary buffer. The memory manager330may return the second temporary buffer to the temporary memory pool at the request of the swap controller320. For example, the deallocation time point of the second temporary buffer may be after the compressed data has been copied to the storage area.

Next, the controller240may record the location of the storage area in the metadata of the data (S860). Next, the controller240may notify the host processor110of the completion of processing of the swap-out request (S870).

According to the electronic device130in accordance with the present disclosure, since the host processor110does not have to directly perform the compression operation function or manage the compressed data, overall system availability can be improved. In addition, according to the computing system100in accordance with the present disclosure, the host operating system can directly manage the compressed memory pool.

FIG.9is a block diagram of a controller240in accordance with another embodiment of the present disclosure.

The electronic device130in accordance with the present embodiment may swap out the data stored in the volatile memory device132to a non-volatile storage device140. Some components of the embodiment according toFIG.9may be the same as or similar to some components of the embodiment according toFIG.3, and detailed descriptions of the same or corresponding components will be omitted.

As shown inFIG.9, the controller240may further include a storage controller900. The storage controller900may be configured to drive the non-volatile storage device140via the second communication port230, designate addresses in blocks, and perform data reads or writes.

The controller240may determine cold data out of the data stored in the compressed memory pool in the volatile memory device132. According to one embodiment, the memory manager330may determine the cold data in the currently allocated compressed memory pool based on information such as time information when the memory was allocated and the frequency of page accesses. The cold data may refer to data that is not frequently accessed and can thus be swapped out to another device, out of the data stored in the compressed memory pool.

The controller240may transmit the cold data to the non-volatile storage device140. The storage controller900may swap out the cold data to the non-volatile storage device140. According to one embodiment, the cold data present in the compressed memory pool may be swapped out in a compressed state. In this case, the storage controller900transfers the cold data present in the compressed memory pool to the non-volatile storage device140via the second communication port230in the compressed state.

According to another embodiment, the cold data present in the compressed memory pool may be decompressed and then swapped out. In this case, the swap controller320may be allocated a temporary buffer from the temporary memory pool by requesting the memory manager330. The compression and decompression module340may generate decompressed data by decompressing the cold data at the request of the swap controller320and store the decompressed data in the temporary buffer. The storage controller900may transmit the decompressed data stored in the temporary buffer to the non-volatile storage device140. According to the embodiment in which decompressed data is transmitted, a delay may be reduced if an access to the corresponding data is needed again later, compared to the embodiment in which compressed data is transmitted.

Thereafter, the controller240may receive a request (swap-in request) for the page data that has been swapped out to the non-volatile storage device140from the host processor110. In response to the request, the swap controller320may be allocated a temporary buffer from the temporary memory pool by requesting the memory manager330. The storage controller900may bring the page data to the temporary buffer from the non-volatile storage device140. The swap controller320may transfer the page data stored in the temporary buffer to the host processor110via the DMA module310. If the data brought into the temporary buffer is compressed data, the controller240may decompress the compressed data by using the compression and decompression module340and then transfer it to the host processor110via the DMA module310.

According to the present disclosure, it is possible to selectively swap out data, which is less required to be retained in the volatile memory device132in terms of performance, to the non-volatile storage device140. According to the present disclosure, overall memory efficiency can be improved by performing a primary swap-out from the host memory120to the volatile memory device132and a secondary swap-out from the volatile memory device132to the non-volatile storage device140. According to the present disclosure, it is possible to reduce the management burden of the host operating system and improve the performance of the entire computing system100by allowing the electronic device130to process the swap-out from the volatile memory device132to the non-volatile storage device140.

FIG.10is an example diagram conceptually illustrating a computing system1000including an electronic device130in accordance with another embodiment of the present disclosure.

The computing system1000in accordance with the present embodiment may include a plurality of electronic devices130,1100, and1200. Some components of the embodiment according toFIG.10may be the same as or similar to some components of the embodiment according toFIG.1, and detailed descriptions of the same or corresponding components will be omitted.

The electronic device130in accordance with the present disclosure may be connected with the external electronic devices1100and1200. The controller240of the electronic device130may receive a swap-out request of data in pages not only from the host processor110but also from the external electronic devices1100and1200. For example, the controller240may generate compressed data by receiving and compressing the corresponding page data in response to the swap-out request of the external electronic device1100. The controller240may store the generated compressed data in the volatile memory device132.

The controller240of the electronic device130may receive a swap-in request of data in pages not only from the host processor110but also from the external electronic devices1100and1200. For example, the controller240may generate decompressed data by decompressing the compressed data in which the corresponding page data is compressed in response to the swap-in request of the external electronic device1100. The controller240may transfer the generated compressed data to the external electronic device1100.

According to the present disclosure, swap-out and swap-in requests not only from the host processor110but also from other electronic devices1100and1200can be processed. If the electronic device130is configured to be connectable with a plurality of other electronic devices1100and1200, management in consideration of the memory availability of each electronic device is possible. Accordingly, the performance of the entire computing system1000can be improved.

The methods in accordance with the present disclosure may be computer-implemented methods. Although each step of the corresponding methods has been shown and described in a given order in the present disclosure, the respective steps may also be performed in an order that can be combined arbitrarily according to the present disclosure, in addition to being performed in sequence. In one embodiment, at least some of the steps may be performed in parallel, iteratively, or heuristically. The present disclosure does not exclude making changes or modifications to the methods. In one embodiment, at least some of the steps may be omitted or other steps may be added.

Various embodiments of the present disclosure may be implemented as software recorded on a machine-readable recording medium. The software may be software for implementing the various embodiments of the present disclosure described above. Software may be inferred from the various embodiments of the present disclosure by programmers skilled in the art to which the present disclosure pertains. For example, the software may be machine-readable commands (e.g., code or code segments) or programs. A machine is a device capable of operating according to instructions called from a recording medium, and may be, for example, a computer. In one embodiment, the machine may be the host processor110, the electronic device130or the computing system100or1000including the same in accordance with the embodiments of the present disclosure. In one embodiment, the processor of the machine may execute the called command and cause the components of the machine to perform functions corresponding to the command. The recording medium may refer to any type of recording medium on which data readable by a machine are stored. The recording medium may include, for example, ROM, RAM, CD-ROM, magnetic tapes, floppy disks, optical data storage devices, and the like. In one embodiment, the recording medium may be implemented in a distributed form over networked computer systems or the like. The software may be stored in a distributed manner and executed on a computer system or the like. The recording medium may be a non-transitory recording medium. A non-transitory recording medium refers to a tangible medium regardless of whether data is stored in it semi-permanently or temporarily, and does not include signals propagating in a transitory manner.

Although the technical idea of the present disclosure has been described by various embodiments above, the technical idea of the present disclosure includes various substitutions, modifications, and changes that can be made within the scope that can be understood by those skilled in the art to which the present disclosure pertains. Further, it is to be understood that such substitutions, modifications, and changes may fall within the scope of the appended claims. The embodiments in accordance with the present disclosure may be combined with each other. The respective embodiments may be combined in various ways according to the number of cases, and the combined embodiments also fall within the scope of the present disclosure.