Patent ID: 12253563

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Operating duty cycles of a circuit can drift over time, such that the circuit may not always operated according to specification. For example, a duty cycle of a circuit may tend to deviate from 50% after a clock signal passes through several components and/or due to changes in the operating conditions, such as voltage and temperature. In order to adjust the clock signal back to its proper duty cycle, a system may seek to measure accurately the duty cycle of the clock signal.

Systems and methods, in certain embodiments, as described herein measure a duty cycle of a clock signal using a first-order delta-sigma analog-to-digital converter, whereby the duty cycle of the clock signal may be measured with relatively high accuracy. In further detail,FIG.1is a schematic block diagram illustrating an exemplary duty cycle measurement (DCM) device100in accordance with various embodiments of the present disclosure. In this exemplary embodiment, the DCM device100is operable in a measurement mode and a calibration mode. In the measurement mode, the DCM device100is configured to receive a clock signal (CLK) that has an unknown duty cycle and to generate a digital output code (DOUT) indicative of the duty cycle of the clock signal (CLK).

In the calibration mode, the DCM device100is configured to receive a clock signal (CLK′) that has a predetermined duty cycle, e.g., about 50%, and to generate a digital output code (DOUT′) indicative of the duty cycle of the clock signal (CLK′). The digital output code (DOUT) obtained during the measurement mode may be compared with the digital output code (DOUT′) obtained during the calibration mode to determine whether or not the clock signal (CLK) has a duty cycle of about 50%.

As illustrated inFIG.1, the DCM device100includes a clock select circuit110, a charge pump circuit120, and a clocked comparator circuit130. The clock select circuit110is configured to receive a clock signal (CLK) that has an unknown duty cycle, e.g., from a clock generator included in or external to the DCM device100. The clock select circuit110is further configured to generate a clock signal (CLK′) that has a predetermined duty cycle, e.g., about 50%, based on the clock signal (CLK). The clock select circuit110is further configured to provide at an output thereof either the clock signal (CLK), i.e., when the DCM device100is in the measurement mode, or the clock signal (CLK′), i.e., when the DCM device100is in the calibration mode.

The charge pump circuit120is connected to the output of the clock select circuit110so as to receive the clock signal (CLK/CLK′). The charge pump circuit120is further configured to charge and discharge a capacitor thereof, e.g., capacitor (C) inFIG.2, based on the duty cycle of the clock signal (CLK/CLK′), whereby the charge pump circuit120generates a capacitor voltage (VCAP) at an output thereof.

The clocked comparator circuit130is connected to the output of the charge pump circuit120so as to receive the capacitor voltage (VCAP). The clocked comparator circuit130is further configured to receive a reference voltage (VREF), e.g., from a voltage generator included in or external to the DCM device100. The clocked comparator circuit130is further configured to compare the capacitor voltage (VCAP) with the reference voltage (VREF), whereby the clocked comparator circuit130generates a digital output code (DOUT/DOUT′) at an output thereof. The digital output code (DOUT/DOUT′) is indicative of the duty cycle of the clock signal (CLK/CLK′). The charge pump circuit120is further connected to the output of the clocked comparator circuit130so as to receive the digital output code (DOUT/DOUT′). As will be described hereinafter, the charge pump circuit120and the clocked comparator circuit130constitute a first-order delta-sigma analog-to-digital converter.

FIG.2is a schematic circuit diagram illustrating an exemplary clock select circuit110, an exemplary charge pump circuit120, and an exemplary clocked comparator circuit130of the DCM device100in accordance with various embodiments of the present disclosure. As illustrated inFIG.2, the clock select circuit110includes a frequency divider210and a multiplexer220. The frequency divider210and the multiplexer220are configured to receive the clock signal (CLK), which has an unknown duty cycle. The frequency divider210is further configured to divide a frequency of the clock signal (CLK) by two so as to provide the clock signal (CLK′), which has a duty cycle of about 50%, at an output thereof. The multiplexer220is connected to the output of the frequency divider210so as to receive the clock signal (CLK′). The multiplexer220is further configured to receive a clock select signal (CLK_SEL), e.g., from a signal generator included in or external to the DCM device100. The clock select signal (CLK_SEL) may be asserted/de-asserted so that the multiplexer220provides the clock signal (CLK/CLK′) at an output thereof.

The charge pump circuit120includes a first current source230, a second current source240, and a capacitor (C). The first current source230has a first current source terminal configured to receive a supply voltage (VDD), e.g., from a voltage generator included in or external to the DCM device100, and a second current source terminal connected to a capacitor voltage node250.

The second current source240has a first current source terminal connected to the capacitor voltage node250, a second current source terminal connected to the electrical ground, and a third current source terminal that is connected to the output of the multiplexer220and that receives the clock signal (CLK/CLK′). The capacitor (C) is connected between the capacitor voltage node250and the electrical ground. The first current source230is configured to source a current (I1) through the capacitor voltage node250, thereby charging the capacitor (C). The second current source240is configured to sink a current (I2) through the capacitor voltage node250, thereby discharging the capacitor (C). The charging and discharging of the capacitor (C) result in a capacitor voltage (VCAP) at the capacitor voltage node250.

The clocked comparator circuit130includes a comparator260and a latch270. The comparator260has an inverting terminal connected to the capacitor voltage node250and configured to receive the capacitor voltage (VCAP) and a non-inverting terminal configured to receive the reference voltage (VREF). The latch250has a first latch terminal connected to an output terminal of the comparator260, a second latch terminal configured to receive the clock signal (CLK), and a third latch terminal that provides the digital output code (DOUT/DOUT′). The first current source230further has a third current source terminal connected to the third latch terminal of the latch270so as to receive the digital output code (DOUT/DOUT′). The comparator260is configured to compare the capacitor voltage (VCAP) with the reference voltage (VREF) and to generate the digital output code (DOUT/DOUT′) based on the result of the comparison. The latch270provides the digital output code (DOUT/DOUT′) as an output at a rising/falling edge of the clock signal (CLK).

As will be described hereinafter, the DCM device100operate first in the calibration mode to obtain the digital output code (DOUT′) and then in the measurement mode to obtain the digital output code (DOUT), whereby the digital output code (DOUT) may be compared with the digital output code (DOUT′) so as to determine whether or not the clock signal (CLK) has a duty cycle of about 50%. During the calibration mode, the clock select circuit110receives the clock signal (CLK), which has an unknown clock cycle, and divides a frequency of the clock signal (CLK) by two, thereby obtaining the clock signal (CLK′), which has a duty cycle of about 50%. The clock select signal (CLK_SEL) is asserted and the clock select circuit110provides the clock signal (CLK′) at the output thereof. When the clock signal (CLK′) transitions from a low logic state to a high logic state, the second current source240is turned on. The second current source240then sinks a current (I2) through the capacitor voltage node250. The current (I2), in turn, discharges the capacitor (C). When a capacitor voltage (VCAP) at the capacitor voltage node250decreases to less than the reference voltage (VREF), i.e., the clocked comparator circuit130detects that the reference voltage (VREF) is greater than the capacitor voltage (VCAP), the clocked comparator circuit130outputs a high logic state, turning on the first current source230. The first current source230then sources a current (I1) through the capacitor voltage node250. The current (I1), in turn, charges the capacitor (C). When the capacitor voltage (VCAP) increases to greater than the reference voltage (VREF), i.e., the clocked comparator circuit130detects that the reference voltage (VREF) is less than the capacitor voltage (VCAP), the clocked comparator circuit130outputs a low logic state, turning off the first current source230. The clock signal (CLK′) then again transitions from a low logic state to a high logic state and the procedure is repeated. When a steady state is reached, the first current source230sources a current (I1) to the capacitor (C) as much as the second current source240sinks a current (I2) from the capacitor (C), the capacitor voltage (VCAP) is substantially equal to the reference voltage (VREF), and the digital output code (DOUT′) corresponds to the duty cycle, i.e., about 50%, of the clock signal (CLK′).

Thereafter, the DCM device100enters the measurement mode. During the measurement mode, the clock select signal (CLK_SEL) is de-asserted and the clock select circuit110provides the clock signal (CLK) at the output thereof. When the clock signal (CLK) transitions from a low logic state to a high logic state, the second current source240is turned on. The second current source240then sinks a current (I2) through the capacitor voltage node250. The current (I2), in turn, discharges the capacitor (C). When a capacitor voltage (VCAP) at the capacitor voltage node250decreases to less than the reference voltage (VREF), i.e., the clocked comparator circuit130detects that the reference voltage (VREF) is greater than the capacitor voltage (VCAP), the clocked comparator circuit130outputs a high logic state, turning on the first current source230. The first current source230then sources a current (I1) through the capacitor voltage node250. The current (I1), in turn, charges the capacitor (C). When the capacitor voltage (VCAP) increases to greater than the reference voltage (VREF), i.e., the clocked comparator circuit130detects that the reference voltage (VREF) is less than the capacitor voltage (VCAP), the clocked comparator circuit130outputs a low logic state, turning off the first current source230. The clock signal (CLK) then again transitions from a low logic state to a high logic state and the procedure is repeated. When a steady state is reached, the first current source230sources a current (I1) to the capacitor (C) as much as the second current source240sinks a current (I2) from the capacitor (C), the capacitor voltage (VCAP) is substantially equal to the reference voltage (VREF), and the digital output code (DOUT) corresponds to the duty cycle of the clock signal (CLK).

FIG.3is a flow chart illustrating an exemplary method300of measuring a duty cycle of a clock signal (CLK) in accordance with various embodiments of the present disclosure. Method300will now be described with further reference toFIG.2for ease of understanding. It is understood that method300is applicable to structures other than those ofFIG.2. Further, it is understood that additional operations can be provided before, during, and after method300, and some of the operations described below can be replaced or eliminated, in an alternative embodiment of method300.

In operation305, the DCM device100operates in a calibration mode. That is, the clock select circuit110receives a clock signal (CLK) that has an unknown duty cycle and divides the frequency of the clock signal (CLK) by two, thereby obtaining a clock signal (CLK′) that has a duty cycle of about 50%. The DCM device100asserts the clock select signal (CLK_SEL) and the clock select circuit110provides the clock signal (CLK′) at the output thereof.

In operation310, the second current source240receives the clock signal (CLK′) from the clock select circuit110.

In operation315, a capacitor voltage (VCAP) is generated at the capacitor voltage node250. For example, the clock signal (CLK′) transitions from a low logic state to a high logic state. The second current source240is turned on and sinks a current (I2) through the capacitor voltage node250, thereby discharging the capacitor (C). Thereafter, the first current source230receives a digital output code (DOUT′) that has a high logic state. The first current source230is turned on and sources a current (I1) through the capacitor voltage node250, thereby charging the capacitor (C). The charging and discharging of the capacitor (C) result in the capacitor voltage (VCAP) at the capacitor voltage node250.

In operation320, the clocked comparator circuit130compares the capacitor voltage (VCAP) with a reference voltage (VREF).

In operation325, the clocked comparator circuit130generates a digital output code (DOUT′) based on the result of the comparison. For example, when the clocked comparator circuit130detects that the reference voltage (VREF) is greater than the capacitor voltage (VCAP), the clocked comparator circuit130generates a high logic state, otherwise, i.e., the clocked comparator circuit130detects that the reference voltage (VREF) is less than the capacitor voltage (VCAP), the clocked comparator circuit130generates a low logic state.

In operation330, the clocked comparator circuit130provides the digital output code (DOUT′) at the output thereof as a rising/falling edge of the clock signal (CLK).

In operation335, the DCM device100operates in a measurement mode. That is, the DCM device100de-asserts the clock select signal (CLK_SEL) and the clock select circuit110provides the clock signal (CLK) at the output thereof.

In operation340, the second current source240receives the clock signal (CLK) from the clock select circuit110.

In operation345, a capacitor voltage (VCAP) is generated at the capacitor voltage node250. For example, the second current source240receives a clock signal (CLK) that transitions from a low logic state to a high logic state. The second current source240is turned on and sinks a current (I2) through the capacitor voltage node250, thereby discharging the capacitor (C). Thereafter, the first current source230receives a digital output code (DOUT) that has a high logic state. The first current source230is turned on and sources a current (I1) through the capacitor voltage node250, thereby charging the capacitor (C). The charging and discharging of the capacitor (C) result in the capacitor voltage (VCAP) at the capacitor voltage node250.

In operation350, the clocked comparator circuit130compares the capacitor voltage (VCAP) with the reference voltage (VREF).

In operation355, the clocked comparator circuit130generates a digital output code (DOUT) based on the result of the comparison. For example, when the clocked comparator circuit130detects that the reference voltage (VREF) is greater than the capacitor voltage (VCAP), the clocked comparator circuit130generates a high logic state, otherwise, i.e., the clocked comparator circuit130detects that the reference voltage (VREF) is less than the capacitor voltage (VCAP), the clocked comparator circuit130generates a low logic state.

In operation360, the clocked comparator circuit130provides the digital output code (DOUT) at the output thereof at a rising/falling edge of the clock signal (CLK).

FIG.4is a schematic diagram illustrating another exemplary DCM device400in accordance with various embodiments of the present disclosure. The DCM device400of this embodiment differs from the DCM device100in that the DCM device400is operable only in the measurement mode. That is, as illustrated inFIG.1, the DCM device400is dispensed with the clock select circuit110. Because the construction and operation of the DCM device400are similar to those described hereinabove in connection with the DCM device100, a detailed description of the same will be dispensed with herein for the sake of brevity.

FIG.5is a flow chart illustrating another exemplary method500of measuring a duty cycle of a clock signal in accordance with various embodiments of the present disclosure. Method500will now be described with further reference toFIG.4for ease of understanding. It is understood that method500is applicable to structures other than those ofFIG.4. Further, it is understood that additional operations can be provided before, during, and after method500, and some of the operations described below can be replaced or eliminated, in an alternative embodiment of method500.

In operation510, the second current source240receives the clock signal (CLK).

In operation520, a capacitor voltage (VCAP) is generated at the capacitor voltage node250. For example, the second current source240receives a clock signal (CLK) that transitions from a low logic state to a high logic state. The second current source240is turned on and sinks a current (I2) through the capacitor voltage node250, thereby discharging the capacitor (C). Thereafter, the first current source230receives a digital output code (DOUT) that has a high logic state. The first current source230is turned on and sources a current (I1) through the capacitor voltage node250, thereby charging the capacitor (C). The charging and discharging of the capacitor (C) result in the capacitor voltage (VCAP) at the capacitor voltage node250.

In operation530, the clocked comparator circuit130compares the capacitor voltage (VCAP) with the reference voltage (VREF).

In operation540, the clocked comparator circuit130generates a digital output code (DOUT) based on the result of the comparison. For example, when the clocked comparator circuit130detects that the reference voltage (VREF) is greater than the capacitor voltage (VCAP), the clocked comparator circuit130generates a high logic state, otherwise, i.e., the clocked comparator circuit130detects that the reference voltage (VREF) is less than the capacitor voltage (VCAP), the clocked comparator circuit130generates a low logic state.

In operation550, the clocked comparator circuit130provides the digital output code (DOUT) at the output thereof at a rising/falling edge of the clock signal (CLK).

In an embodiment, a duty cycle measurement (DCM) device comprises a charge pump circuit and a clocked comparator circuit. The charge pump circuit is configured to receive a clock signal that has an unknown duty cycle and to generate a capacitor voltage based on the duty cycle of the clock signal. The clocked comparator circuit is configured to receive the capacitor voltage and a reference voltage and to generate a digital output code based on the capacitor voltage and the reference voltage. The digital output code is indicative of the duty cycle of the clock signal. The charge pump circuit is further configured to receive the digital output code.

In another embodiment, a duty cycle measurement (DCM) device comprises a clock select circuit, a charge pump circuit, and a clocked comparator circuit. The clock select circuit is configured to provide a clock signal that has predetermined duty cycle. The charge pump circuit is configured to receive the clock signal and to generate a capacitor voltage based on a duty cycle of the clock signal. The clocked comparator circuit is configured to receive the capacitor voltage and a reference voltage and to generate a digital output code based on the capacitor voltage and the reference voltage. The digital output code is indicative of the duty cycle of the clock signal. The charge pump circuit is further configured to receive the digital output code.

In another embodiment, a method of determining a duty cycle of a clock signal includes steps of operating in a calibration mode; receiving a clock signal that has a predetermined duty cycle; generating a capacitor voltage based on the duty cycle of the clock signal; comparing the capacitor voltage with a reference voltage; generating a digital output code based on the result of the comparison; and receiving the digital output code.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.