Patent ID: 12243791

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described as follows with reference to the attached drawings. The shape and size of elements in the drawings may be exaggerated or reduced for clarity.

Electronic Device

FIG.1is a block diagram schematically illustrating an exemplary embodiment of an electronic device system.

Referring to the drawings, an electronic device1000may include a main board1010. The main board1010may be physically and/or electrically connected to chip-related components1020, network-related components1030, and other components1040. They may be also combined with other components to be described later by form various signal lines1090.

The chip-related components1020may include a memory chip, such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.; an application processor chip, such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.; a logic chip, such as an analog-to-digital converter, an application-specific IC (ASICs), etc.; and the like, but are not limited thereto, and other types of chip-related components may be included. These chip-related components1020may be combined with each other.

The network-related components1030may include components designated to operate according to Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G protocol, 4G protocol, 5G protocol, and any other wireless and wired protocols designated as the later ones, but are not limited thereto, and any of other various wireless or wired standards or protocols may be further included. The network-related components1030may be combined with the chip-related components1020, as well.

Other components1040may include a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-firing ceramic (LTCC), an electro-magnetic interference (EMI) filter, and a multilayer ceramic condenser (MLCC), but is not limited thereto, and may include other passive components used for various other purposes. Other components1040may be combined with each other, in addition to combining with the chip-related components1020and/or the network-related components1030.

Depending on the type of the electronic device1000, the electronic device1000may include other components that may or may not be physically and/or electrically connected to the main board1010. Other components may include, for example, a camera1050, an antenna1060, a display1070, a battery1080, an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage device (e.g., a hard disk drive) (not illustrated), a compact disk (CD) diver (not illustrated), and a digital versatile disk (DVD) diver (not illustrated), and the like, but is not limited thereto, and other components used for various purposes may be included, depending on the type of the electronic device1000.

The electronic device1000may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game, a smartwatch, an automotive components, and the like, but is not limited thereto, and may be any other electronic device that processes data.

FIG.2is a perspective view schematically illustrating an exemplary embodiment of an electronic device.

Referring to the drawings, a semiconductor package may be applied to various electronic devices as described above for various purposes. For example, a printed circuit board1110, such as a main board, may be included in a body1101of a smartphone1100. Further, various components1120may be physically and/or electrically connected to the printed circuit board1110. In addition, other components that may or may not be physically and/or electrically connected to the printed circuit board1110, such as a camera1130, may be housed within the body1101. A portion of the components1120may be chip-related components, for example, but not limited to, a semiconductor package1121. The electronic device is not necessarily limited to the smartphone1100, and may be other electronic device as described above.

Semiconductor Package

In general, a semiconductor chip may have many microelectronic circuits integrated therein, but does not necessarily serve as a finished product of a semiconductor in itself, and the semiconductor chip may be damaged by an external physical or chemical impact. Therefore, the semiconductor chip itself may be not used as it is and may be packaged and used as an electronic device or the like in such a packaged state.

Semiconductor packaging may be used, for example in situations in which there is a difference in a circuit width between a semiconductor chip and a main board of the electronic device in view of an electrical connection. Specifically, fora semiconductor chip, the size of the connection pad and the interval between connection pads are very small and narrow, whereas the size of the component mounting pad and the interval between component mounting pads are much larger and wider than the scale of the semiconductor chip, respectively. Therefore, since it is difficult to directly mount a semiconductor chip on such a main board, there is a need for a packaging technique which may buffer the difference in a circuit width therebetween.

A semiconductor package manufactured by such a packaging technique may be classified as a fan-in semiconductor package and a fan-out semiconductor package, depending on the structure and use thereof.

Hereinafter, the fan-in semiconductor package and the fan-out semiconductor package will be described in more detail with reference to the drawings.

Fan-In Semiconductor Package

FIGS.3A and3Bare cross-sectional views schematically illustrating states of a fan-in semiconductor package, before and after being packaged.

FIG.4is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, a semiconductor chip2220may be an integrated circuit (IC) in a bare state. A body2221may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. A connection pad2222may include a conductive material, such as aluminum (Al) or the like, formed on one surface of the body2221. A passivation film2223, such as an oxide film, a nitride film, or the like, may be formed on one surface of the body2221and cover at least a portion of the connection pad2222. At this time, since the connection pad2222is very small, it may be difficult to mount the integrated circuit (IC) even on a medium size level printed circuit board (PCB) as well as a main board of the electronic device.

A connection structure2240may be formed on the semiconductor chip2220in conformity with the size of the semiconductor chip2220, to redistribute the connection pad2222. The connection structure2240may be prepared by way of forming an insulation layer2241with an insulating material such as a photo-imageable dielectric (PID) resin on the semiconductor chip2220, forming a via hole2243hfor opening the connection pad2222, and forming a wiring pattern2242and a via2243. Thereafter, a passivation layer2250for protecting the connection structure2240may be formed, an opening2251may be formed, and an under-bump metal layer2260or the like may be formed. For example, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection structure2240, the passivation layer2250, and the under-bump metal layer2260may be formed through a series of processes.

As described above, the fan-in semiconductor package may be a package type in which all the connection pads of the semiconductor chip, for example, input/output (I/O) terminals are arranged inside the element. The fan-in semiconductor package may have good electrical characteristics, and may be produced at relatively low cost. Accordingly, many elements in a smartphone may be manufactured in the form of a fan-in semiconductor package. Specifically, it is being developed in a direction of achieving a small-sized form and realizing fast signal transmission at the same time.

Since, in the fan-in semiconductor package, all of the I/O terminals should be disposed inside the semiconductor chip, there may be many limitations in space. Therefore, such a structure may be difficult to apply to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to this problem, the fan-in semiconductor package may not be directly mounted on and used in a main board of an electronic device. Even when the size and interval of the I/O terminals of the semiconductor chip are enlarged in a redistributing process, they do not have a size and an interval enough to be directly mounted on the main board of the electronic device.

FIG.5is a cross-sectional view schematically illustrating a fan-in semiconductor package mounted on a printed circuit board that is ultimately mounted on a main board of an electronic device.

FIG.6is a cross-sectional view schematically illustrating a fan-in semiconductor package embedded in a printed circuit board that is ultimately mounted on a main board of an electronic device.

Referring to the drawings, a fan-in semiconductor package2200may be configured such that connection pads2222of a semiconductor chip2220, i.e. I/O terminals are redistributed once again through a printed circuit board2301, and the fan-in semiconductor package2200mounted on the printed circuit board2301is mounted on a main board2500of an electronic device. At this time, a solder ball2270and the like may be fixed with an underfill resin2280, and an outer side of the semiconductor chip2220may be covered with a molding material2290or the like. Alternatively, the fan-in semiconductor package2200may be embedded in a separate printed circuit board2302, and the connection pads2222of the semiconductor chip2220, i.e., the I/O terminals may be redistributed once again in an embedded form, and ultimately mounted on the main board2500of the electronic device.

As above, it may be difficult to directly mount the fan-in semiconductor package on the main board of the electronic device. Therefore, it may be mounted on a separate printed circuit board, and may be then mounted on the main board of the electronic device through a packaging process, or may be mounted on the main board of the electronic device in a form embedded in the printed circuit board.

Fan-Out Semiconductor Package

FIG.7is a cross-sectional view schematically illustrating a fan-out semiconductor package.

Referring to the drawings, in a fan-out semiconductor package2100, for example, an outer side of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed to the outer side of the semiconductor chip2120through a connection structure2140. A passivation layer2150may be further formed on the connection structure2140. An under-bump metal layer2160may be further formed on an opening of the passivation layer2150. A solder ball2170may be further formed on the under-bump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, a connection pad2122, and the like. The connection structure2140may include an insulation layer2141, a wiring layer2142formed on the insulation layer2241, and a via2143for electrically connecting the connection pad2122and the wiring layer2142.

The fan-out semiconductor package may be formed by redistributing the I/O terminals to the outer side of the semiconductor chip through the connection structure formed on the semiconductor chip. As described above, in a fan-in semiconductor package, all of the I/O terminals of the semiconductor chip should be disposed inside of the semiconductor chip. When the size of the element is reduced, the size and pitch of the ball should be reduced. Therefore, the standardized ball layout may be not used. On the other hand, in a fan-out semiconductor package, the I/O terminals may be redistributed outward from the semiconductor chip through the connection structure formed on the semiconductor chip. Although the size of the semiconductor chip is reduced, the standardized ball layout may be used as it is. Therefore, the fan-out semiconductor package may be mounted on a main board of an electronic device without a separate printed circuit board, as described later.

FIG.8is a cross-sectional view schematically illustrating a fan-out semiconductor package mounted on a main board of an electronic device.

Referring to the drawings, a fan-out semiconductor package2100may be mounted on a main board2500of an electronic device through a solder ball2170or the like. For example, as described above, the fan-out semiconductor package2100may include a connection structure2140on the semiconductor chip2120that may redistribute connection pads2122to a fan-out area beyond a size of the semiconductor chip2120. The standardized ball layout may be used as it is, and as a result, it may be mounted on the main board2500of the electronic device without a separate printed circuit board or the like.

Since the fan-out semiconductor package may be mounted on the main board of the electronic device without a separate printed circuit board, as above, the fan-out semiconductor package may be made thinner than the fan-in semiconductor package using the printed circuit board. Therefore, a downsizing and thinning in the fan-out semiconductor package may be accomplished. It may be also suitable for mobile products because of its excellent thermal and electrical properties. In addition, it may be implemented more compactly than a general package-on-package (POP) type using a printed circuit board (PCB), and a problem caused by a bending phenomenon may be prevented.

The fan-out semiconductor package may refer to a package technology for mounting the semiconductor chip on a main board of the electronic device, or the like, and for protecting the semiconductor chip from an external impact, and may have a concept different from a printed circuit board (PCB), such as a printed circuit board in which a fan-in semiconductor package is embedded, which are different from each other in view of scale, use, and the like.

Hereinafter, a semiconductor package having a novel structure, which significantly reduces a mounting area of a semiconductor chip and a passive component, significantly reduces an electrical path between a semiconductor chip and a passive component, significantly reduces process defects such as undulations and cracks, and, furthermore, easily connects electrodes of passive components to connection vias by a laser-via process or the like, may be described with reference to the drawings.

FIG.9is a schematic cross-sectional view illustrating an example of a semiconductor package.

FIG.10is a schematic plan view of the semiconductor package ofFIG.9taken along line I-I′.

A semiconductor package100A (may also be referred to package100A or fan-out semiconductor package100A) according to an example embodiment may include a connection structure140including one or more redistribution layers142; a semiconductor chip120disposed on the connection structure140and having an active surface on which a connection pad122electrically connected to the redistribution layer142is disposed and an inactive surface opposite to the active surface; an encapsulant130disposed on the connection structure140and covering at least a portion of the inactive surface of the semiconductor chip120; and a heat dissipating structure180disposed on the encapsulant130and at least partially embedded in the encapsulant130. The heat dissipating structure180may include a conductor pattern layer181embedded in the encapsulant130such that one surface of the conductor pattern layer181is exposed from the encapsulant130, and a metal layer182disposed on the encapsulant130and the one exposed surface of the conductor pattern layer181. The heat dissipating structure180may further include a conductive adhesive183disposed on the metal layer182and a heat dissipating member184disposed on the conductive adhesive183.

In recent years, as functions of a semiconductor chip have improved, it has become important to effectively release heat generated therefrom. For this purpose, conventionally, the generated heat has been dissipated in such a manner that a heat dissipating member, such as a metal plate, is simply attached to an upper portion of a semiconductor package with an adhesive, or a metal layer is simply plated. In this case, since a distance between the heat dissipating member and the semiconductor chip is considerable, there may be a problem in which it is difficult to obtain a sufficient heat dissipating effect. In addition, since the heat dissipating member may be formed on the semiconductor package having been already manufactured, when a defect occurs in a process of forming the heat dissipating member, the semiconductor chip should be also discarded, thereby reducing yield of the semiconductor chip manufacturing process. Particularly, when a heat dissipating member such as a metal plate is simply attached, adhesion with an encapsulant or a molding material may be low, which causes a problem of peeling-off risk.

A semiconductor package100A according to an example embodiment may include a heat dissipating structure180disposed on an encapsulant130and at least partially embedded in the encapsulant130. The heat dissipating structure180may include a conductor pattern layer181embedded in the encapsulant130such that one surface of the conductor pattern layer181is exposed from or through the encapsulant130, and a metal layer182disposed on the encapsulant130and the one exposed surface of the conductor pattern layer181. The embedded conductor pattern layer181may be closer to an inactive surface of a semiconductor chip120(e.g., closer to the inactive surface than to the active surface of the semiconductor chip120), and may more reliably emit heat generated from the semiconductor chip120in an upward direction. The conductor pattern layer181may be embedded in the encapsulant130to have a good adhesion, and the metal layer182may be also formed to cover and contact the exposed surface of the conductor pattern layer181through the encapsulant130and the exposed surface of the encapsulant130through the conductor pattern layer181, to have excellent adhesion.

The heat dissipating structure180may further include a conductive adhesive183disposed on the metal layer182and a heat dissipating member184disposed on the conductive adhesive183for better heat dissipation. In this case, since the conductive adhesive183is disposed on the metal layer182instead of the encapsulant130(which may be formed of an organic material), a better adhesion may be also exerted. Since a semiconductor package100A according to an example embodiment has a special structure of a heat dissipating structure180, both the heat dissipating effect and the reliability may be improved as compared with the conventional one. Further, by arranging such a metal material, it may also improve a warpage problem of the package100A, and also have an electromagnetic wave shielding effect. The conductor pattern layer181and the metal layer182of the heat dissipating structure180may be separately manufactured using a carrier or the like, such that only a good product may be introduced into an upper portion of the package100A. Therefore, the yield problem of the semiconductor chip120manufacturing process may be improved, and the entire process time of the product may be not affected.

The encapsulant130may include a first encapsulant130adisposed on the connection structure140and covering at least a portion of the semiconductor chip120such as at least a portion of an inactive surface, and a second encapsulant130bdisposed on the first encapsulant130aand covering the first encapsulant130a. The first and second encapsulants130aand130bmay be provided as distinct layers separate from each other. In this case, the conductor pattern layer181may be embedded in the second encapsulant130bsuch that one exposed surface of the conductor pattern layer181is exposed from the second encapsulant130b, and the metal layer182may be disposed on the second encapsulant130bto cover the one exposed surface of the conductor pattern layer181. The conductor pattern layer181and the metal layer182may be formed on the carrier, and then the conductor pattern layer181and the metal layer182may be introduced by laminating them on the first encapsulant130aof the package100A with coverage provided by the second encapsulant130b. In this case, since the conductor pattern layer181is embedded in the second encapsulant130band the metal layer182covers the second encapsulant130bin an uncured state of the second encapsulant130b, an adhesion between heterogeneous materials may be improved to reduce the interfacial peeling-off risk. In addition, a connection of an insulation resin between the first and second encapsulants130aand130bmay have a better adhesion effect, and may further improve the reliability of the package100A.

The conductor pattern layer181may include a plurality of metal patterns181P, and at least a portion of the plurality of metal patterns181P may be spaced apart from each other and face the inactive surface of the semiconductor chip at a predetermined distance from the inactive surface of the semiconductor chip120. In this case, adhesion may be improved through an embossing effect while maintaining an excellent heat dissipating effect. The metal layer182may have the form of a single metal plate to provide a flat surface. The metal layer182may extend across spaces between the metal patterns181P of the conductor pattern layer181, and may extend integrally across the inactive surface of the semiconductor chip120. The metal layer182may contact the encapsulant130between the plurality of conductor patterns181P. In this case, the adhesion reliability of the heat dissipating member184through the conductive adhesive183may be further improved. The conductive adhesive183may include a thermally conductive interface material (TIM), and the heat dissipating member184may include a metal lump. In this case, the heat dissipating effect may be maximized.

The conductor pattern layer181may include a first conductor layer181ain contact with the metal layer182and embedded in the encapsulant130and a second conductor layer181bdisposed on the first conductor layer181aand embedded in the encapsulant130. The first conductor layer181amay be a seed layer formed on one surface of the metal layer182on the carrier by an electroless plating process such as a metal sputter, or the like, and the second conductor layer181bmay be a plated layer formed by an electroplating process using the first conductor layer181aas a seed layer. Therefore, a thickness of the second conductor layer181bmay be thicker than a thickness of the first conductor layer181a. As described above, the conductor pattern layer181may be embedded in the encapsulant130in such a manner that the seed layer and the plated layer are reversed (e.g., the seed layer may be disposed above the plated layer when the package is disposed in the orientation shown inFIG.9).

A semiconductor package100A according to an example embodiment may further include a frame110disposed on the connection structure140and having a through-hole110H. In this case, the semiconductor chip120may be disposed in the through-hole110H such that the active surface thereof faces the connection structure140, and the encapsulant130, in particular, the first encapsulant130amay cover or directly contact at least a portion of the frame110, and may fill at least a portion of the through-hole110H. When the frame110is provided, better rigidity may be introduced to the package and it may help to ensure thickness uniformity of the encapsulant130, in particular, the first encapsulant130a. The frame110may include an insulation layer111in which the through-hole110H is formed, first and second metal layers115aand115brespectively disposed on opposing lower and upper surfaces of the insulation layer111, and a third metal layer115cdisposed on a wall surface of the through-hole110H. In this case, a better heat dissipating effect may be achieved. Further, the electromagnetic wave shielding effect and the warpage improving effect may be further enhanced.

A semiconductor package100A according to an example embodiment may further include a passivation layer150disposed at a lower side of the connection structure140and having a plurality of openings for respectively opening or exposing at least a portion of a lowermost redistribution layer142among the redistribution layers142, a plurality of under-bump metals160disposed on or in the plurality of openings and electrically connected to the lowermost redistribution layer142, and a plurality of electrical connection metals170disposed at a lower side of the passivation layer150and electrically connected to the plurality of under-bump metals160, as shown.

Hereinafter, each configuration included in a semiconductor package100A according to one example will be described in more detail.

The frame110may further improve rigidity of the package100A according to a specific material of the insulation layer111, and may play a role of ensuring thickness uniformity of the first encapsulant130a. The frame110may have a through-hole110H passing through the insulation layer111. The semiconductor chip120may be disposed in the through-hole110H, and passive components (not illustrated) may be disposed together (e.g., in the through-hole110H having the semiconductor chip120, or in a different through-hole in the frame110), as needed. The through-hole110H may have a wall surface surrounding the semiconductor chip120, but the present disclosure is not limited thereto. Metal layers115a,115b, and115cmay be disposed on lower and upper surfaces of the insulation layer111and a wall surface of the through-hole110H, respectively, and may be connected to or directly contact each other. The metal layers115a,115b, and115cmay have a better heat dissipation effect, and the electromagnetic wave shielding effect and warpage improving effect may be further enhanced.

A material of the insulation layer111is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, for example, ABF (Ajinomoto Build-up Film), or the like, may be used. Alternatively, a material in which the above-mentioned resin, impregnated in a core material such as glass fiber, glass cloth, glass fabric, or the like, together with an inorganic filler, for example, a prepreg, or the like, may be used.

The metal layers115a,115b, and115cmay be formed of a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, and the like. The metal layers115a,115b, and115cmay be electrically connected to a ground pattern and/or a power pattern of the redistribution layer142, as needed, to perform a function of a ground pattern and/or a power pattern.

The semiconductor chip120may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. In this case, the integrated circuit may be an application processor chip, such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, and the like, but is not limited thereto, may be a power management IC (PMIC), or may be a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), or the like.

The semiconductor chip120may be an integrated circuit in a bare state in which no separate bump or wiring layer is formed. The present disclosure is not limited thereto, and may be a packaged type integrated circuit, as needed. The integrated circuit may be formed based on an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material of a body121of the semiconductor chip120. Various circuits may be formed in the body121. The connection pad122may be used to electrically connect the semiconductor chip120to other components, and a conductive material such as aluminum (Al) may be used as a formation material thereof without any particular limitation. A passivation film123exposing the connection pad122may be formed on the body121. The passivation film123may be an oxide film or a nitride film, or may be a double layer of an oxide film and a nitride film. An insulating film (not illustrated) or the like may be further disposed in other appropriate positions. Meanwhile, in the semiconductor chip120, a surface on which the connection pad122is disposed may become an active surface, and a surface opposite thereto may become an inactive surface. At this time, when the passivation film123is formed on the active surface of the semiconductor chip120, the active surface of the semiconductor chip120may determine a positional relationship based on the lowermost surface of the passivation film123.

The first encapsulant130amay encapsulate the frame110and the semiconductor chip120, and may also fill at least a portion of the through-hole110H. The first encapsulant130amay include an insulating material. Examples of the insulating material may include such as a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin including the above materials with a reinforcing material such as an inorganic filler, specifically ABF, FR-4, BTresin, etc. In addition, a known molding material such as EMC may be used. Further, a photosensitive material, for example, a photo imageable encapsulant (PIE) may be used as needed. A material in which an insulating resin such as a thermosetting resin or a thermoplastic resin impregnated with a core material such as an inorganic filler and/or glass fiber, glass cloth, glass fabric, or the like, may be used, as needed.

The second encapsulant130bmay further provide an insulation layer on a backside of the package100A and may embed the conductor pattern layer181therein. The second encapsulant130balso may include an insulating material. Examples of the insulating material may include such as a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin including the above materials with a reinforcing material such as an inorganic filler, specifically ABF, FR-4, BTresin, etc. Further, a photosensitive material, for example, a photo-imageable dielectric (PID) material may be used as needed. A material in which an insulating resin such as a thermosetting resin or a thermoplastic resin impregnated with a core material such as an inorganic filler and/or glass fiber, glass cloth, glass fabric, or the like, may be used, as needed. The second encapsulant130bmay be formed of the same material as the first encapsulant130a, or may be formed of different material. The first and second encapsulants130aand130bmay be provided as distinct layers separated from each other, and may be separated from each other.

The connection structure140may redistribute the connection pad122of the semiconductor chip120. Several tens to hundreds of the connection pads122having various functions of semiconductor chips120may be redistributed through the connection structure140. The connection pads122may be physically and/or may be electrically connected externally, in accordance with functions thereof, through the electrical connection metal170. The connection structure140may include an insulation layer141, a redistribution layer142disposed on the insulation layer141, and a connection via143passing through the insulation layer141and electrically connecting the connecting pad122and the redistribution layer142. The number of insulation layer, redistribution layer, connection via and connection pad may be more or less than those shown in the drawings.

As the material of the insulation layer141, an insulating material may be used. In this case, a photo-imageable dielectric (PID) material may be used as an insulating material. In this case, a fine pitch may be introduced through the photo-via process. Tens to hundreds of the connection pads122in the semiconductor chip120may be redistributed very effectively as in the conventional case. Multiple insulation layers141may be bounded to each other, or the boundaries therebetween may be unclear.

The redistribution layers142may be redistributed to electrically connect the connection pads122of the semiconductor chip120to the electrical connection metals170. As a material for forming the redistribution layers142, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used. The redistribution layers142may also perform various functions, depending on a desired design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like, may be included. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. In addition, the redistribution layer142may include various types of via pads, electrical connection metal pads, and the like. The redistribution layers142may be formed by a plating process, and may include a seed layer and a conductor layer.

The connection vias143may electrically connect the redistribution layers142formed on different layers, and may electrically connect the connection pads122of the semiconductor chip120to the redistribution layers142. The connection vias143may be in physical contact with the connection pads122, when the semiconductor chip120is a bare die. As the material for forming the connection vias143, a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used. The connection vias143may include a signal via, a power via, a ground via, etc. The power via and ground via may be the same via. The connection vias143may also be a filled type via filled with a metal material, or may be a conformal type via in which a metal material formed along a wall surface of a via hole. Further, it may have a tapered shape. The connection vias143may also be formed using a plating process, and may be composed of a seed layer and a conductor layer.

The passivation layer150may be an additional structure for protecting the connection structure140from external physical or chemical damage, or the like. The passivation layer150may include a thermosetting resin. For example, the passivation layer150may be ABF, but is not limited thereto. The passivation layer150may have openings for opening or exposing at least a portion of the lowermost redistribution layer142among the redistribution layers142. The number of openings may be in the range of tens to tens of thousands, or more or less. Each of the openings may be formed of a plurality of holes. A surface mounting component such as a capacitor may be disposed on the lower surface of the passivation layer150to be electrically connected to the redistribution layer142, and as a result, may be electrically connected to the semiconductor chip120. Although not shown in the drawing, a separate surface mounting component (not illustrated) such as a capacitor may be further disposed on the lower surface of the passivation layer150, and may be electrically connected to the connection pad122through the redistribution layer142.

The under-bump metal160may also be an additional component, which improves the connection reliability of the electrical connection metal170, and thus improve the board level reliability of a fan-out semiconductor package100A according to one example. The under-bump metal160may be provided in the number of tens to tens of thousands, and may be provided in numbers more or less than that. Each under-bump metal160may be electrically connected to the open lowermost redistribution layer142formed at the opening of the passivation layer150. The under-bump metal160may be formed by a known metallization method using a known conductive material, for example, metal, but is not limited thereto.

The electrical connection metal170may also be an additional component, a configuration for physically and/or electrically connecting a semiconductor package100A externally. For example, the semiconductor package100A may be mounted on the main board of the electronic device through the electrical connection metal170. The electrical connection metal170may be disposed on the passivation layer150, and may be electrically connected to the under-bump metal160, respectively. The electrical connection metal170may be composed of a low melting point metal, for example, tin (Sn), or an alloy including tin (Sn). More specifically, it may be formed of a solder or the like, but this may be merely an example embodiment, and the material is not particularly limited thereto.

The electrical connection metal170may be a land, a solder ball, a pin, or the like. The electrical connection metal170may be formed of multiple layers or a single layer. In a case of being formed of multiple layers, it may include a copper pillar and a solder. In a case of being formed of a single layer, tin-silver solder or copper may be included, but this may be merely an example and is not limited thereto. The number, interval, arrangement type, etc., of the electrical connection metal170are not particularly limited, and may be sufficiently modified, depending on a design specification by a skilled artisan. For example, the number of electrical connection metal170may be in the range of tens to thousands, depending on the number of connection pads122, and may be more or less than the above range.

At least one of the electrical connection metals170may be disposed in a fan-out area. The fan-out area may be an area, except for those in which the semiconductor chip120is disposed (e.g., an area outside of a zone of overlap with the semiconductor chip120). The fan-out package may be more reliable than the fan-in package, may have many I/O terminals, and may facilitate 3D interconnection. In addition, a package thinner than a ball grid array (BGA) package, a land grid array (LGA) package, and the like, may be manufactured, and may be excellent in price competitiveness.

The conductor pattern layer181may be embedded in the second encapsulant130bto provide a plurality of metal patterns181P capable of performing a heat dissipating function to the backside of the package100A. The conductor pattern layer181may also include conductive materials, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The conductor pattern layer181may be formed by a known plating process, and may include a first conductor layer181a, a seed layer, and a second conductor layer181b, a plated layer. The conductor pattern layer181may be formed relatively thick to narrow a distance from the inactive surface of the semiconductor chip120. For example, a thickness of the conductor pattern layer181may be greater than a thickness of each of the redistribution layers142.

The metal layer182may be disposed on the second encapsulant130bto provide a metal plate capable of performing a heat dissipating function to the backside of the package100A. The metal layer182may also include conductive materials, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The metal layer182may entirely cover the upper surface of the second encapsulant130band the upper surface of the exposed conductor pattern layer181.

The conductive adhesive183may be any material that is heat transferable, regardless of a type of the material, and may include, for example, a thermally conductive interfacial material (TIM). The heat dissipating member184may also be any material that has a heat dissipating effect, and may include, for example, a metal lump, more particularly a copper lump. The heat dissipating member184may be thicker than a thickness of the conductive adhesive183, a thickness of the metal layer182, and a thickness of the conductor pattern layer181for an excellent heat dissipating effect.

FIGS.11to13are schematic views illustrating an example of a manufacturing procedure of the semiconductor package ofFIG.9.

Referring toFIG.11, first, a carrier210having a metal layer182formed on at least one surface thereof may be prepared. The carrier210may include a release layer (not illustrated) disposed between the carrier210and the metal layer182for easier peeling at an interface with the metal layer182. Next, a conductor pattern layer181may be formed on the metal layer182using a plating process. The conductor pattern layer181may be formed by way of forming a first conductor layer181aas a seed layer by an electroless plating process such as a metal sputtering, and forming a second conductor layer181bas a substantial plated layer on the first conductor layer181aby an electrolytic plating process. As a plating method used, an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), a tenting process, and the like, may be used. Next, ABF or the like in an uncured state may be stacked on the metal layer182, such that the conductor pattern layer181may be embedded in the ABF or the like, and cured to form a second encapsulant130b. The curing process may proceed with a first encapsulant130alater.

Referring toFIG.12, a frame110including an insulation layer111having a through-hole110H and metal layers115a,115b, and115cmay be attached on a tape220. A semiconductor chip120formed of a body121, a connection pad122, a passivation film123, and the like, may be disposed in the through-hole110H and may be attached to the tape220in a face-down manner. An ABF or the like in an uncured state may be used to cover the frame110and the semiconductor chip120on the tape220and to form the first encapsulant130afilling the through-hole110H. The first encapsulant130amay be cured. Thereafter, the metal layer182and the conductor pattern layer181covered with the second encapsulant130bseparately manufactured may be laminated such that the first encapsulant130aand the second encapsulant130bare connected to each other. The first encapsulant130amay be cured together with the second encapsulant130bafter the lamination.

Next, the tape220may be removed, and an insulation layer141may be formed by applying and hardening a PID or the like to an area from which the tape220has been removed. After a via hole is formed by a photolithography process, an operation of forming a redistribution layer142and a connection via143may be repeated one, two, or more times to form a connection structure140. In addition, a passivation layer150may be formed using ABF or the like, as needed, and one or more openings may be formed in the passivation layer150, and a plurality of under-bump metals160may be formed by filling the openings in a plating process (referring toFIG.13).

Referring toFIG.13, the carrier210may be then peeled off from the metal layer182. Next, a conductive adhesive183may be formed on the metal layer182using a thermally conductive interfacial material (TIM) or the like, and a heat dissipating member184such as a metal lump may be attached through the conductive adhesive183. As needed, an electrical connection metal170connected to the under-bump metal160may be formed on the passivation layer150, and may be then reflowed to manufacture the semiconductor package100A according to the above-described example.

FIG.14schematically illustrates another example of a fan-out semiconductor package.

Referring to the drawings, a semiconductor package100B according to another example may have a configuration different from the frame110in the semiconductor package100A according to the above-described example. For example, a frame110may include a first insulation layer111ain contact with a connection structure140, a first wiring layer112ain contact with the connection structure140and embedded in the first insulation layer111a, a second wiring layer112bdisposed on a side of the first insulation layer111aopposite to a side on which the first wiring layer112ais disposed, a second insulation layer111bdisposed on the first insulation layer111aand covering the second wiring layer112b, and a third wiring layer112cdisposed on a side of the second insulation layer111bopposite to a side in which the second wiring layer112bis embedded. The first and second wiring layers112aand112band the second and third wiring layers112band112cmay be electrically connected to first and second wiring vias113aand113bthrough the first and second insulation layers111aand111b, respectively. The first to third wiring layers112ato112cmay be electrically connected to a connection pad122, in accordance with functions thereof, through a redistribution layer142and a connection via143. The frame110may be used as a vertical electrical connection path having the wiring layers112a,112b, and112c, and design of the redistribution layer142of the connection structure140may be simplified to facilitate a thinning thereof. Further, the yield problem of the semiconductor chip120due to defects occurring in the process of forming the connection structure140may be improved.

The material of the insulation layers111aand111bis not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins with an inorganic filler, or a resin in which the above resins are impregnated with an inorganic filler such as silica into a core material, such as a glass fiber, a glass cloth, or a glass fabric, for example, a prepreg, may be used.

The wiring layers112a,112b, and112ctogether with the wiring vias113aand113bmay provide a vertical electrical connection path for the package and may perform the role of redistributing the connection pad122. As a material for forming the wiring layers112a,112b, and112c, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used. The wiring layers112a,112b, and112cmay perform various functions, depending on a desired design of the layer. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like, may be included. Here, the signal (S) pattern may include various signal patterns except for a ground (GND) pattern, a power (PWR) pattern, and the like, for example, a data signal pattern and the like. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. The wiring layers112a,112b, and112cmay include various types of via pads and the like. The wiring layers112a,112b, and112cmay be formed by a known plating process, and may be composed of a seed layer and a conductor layer, respectively.

A thickness of each of the wiring layers112a,112b, and112cmay be thicker than a thickness of each of the redistribution layers142. For example, the frame110may have a thickness equal to or greater than a thickness of the semiconductor chip120. In order to maintain rigidity, prepregs and the like may be selected as the material of the insulation layers111aand111b, and wiring layers112a,112b, and112cmay be relatively thick. The connection structure140may provide a microcircuit and a high-density design. Therefore, a PID or the like may be selected as the material of the insulation layer141, and a thickness of the redistribution layer142obtained therefrom may be relatively thin.

The first wiring layer112amay be recessed into the first insulation layer111a. In this way, in a case in which the first wiring layer112ais recessed into the first insulation layer111ato have a step difference between a lower surface of the first insulation layer111ain contact with the connection structure140and a lower surface of the first wiring layer112ain contact with the connection structure140, when the semiconductor chip120and the frame110are encapsulated with the first encapsulant130a, the forming material (e.g., the material used to form the first encapsulant130a) may be prevented from bleeding to contaminate the first wiring layer112aand/or to contaminate a contact between the first wiring layer112aand the redistribution layers142.

The wiring vias113aand113bmay electrically connect the wiring layers112a,112b, and112cformed on different layers, thereby forming an electrical path in the frame110. As the material for forming the wiring vias113aand113b, a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used. The wiring vias113aand113bmay include a signal via, a power via, a ground via, etc. The power via and ground via may be the same via. The wiring vias113aand113bmay also be a filled type via filled with a metal material, or may be a conformal type via in which a metal material formed along a wall surface of a via hole. Further, they may each have a tapered shape. The wiring vias113aand113bmay also be formed by a plating process, and may be composed of a seed layer and a conductor layer.

A portion of the pads of the first wiring layer112amay serve as a stopper, when a hole for the first wiring via113ais formed. The first wiring via113amay have a tapered shape in which the width of the upper surface of the first wiring via113ais wider than the width of the lower surface thereof in terms of the process. In this case, the first wiring via113amay be integrated with the pad pattern of the second wiring layer112b. When a hole for the second wiring via113bis formed, a portion of the pads of the second wiring layer112bmay serve as stoppers. The second wiring via113bmay have a tapered shape in which the width of the upper surface of the second wiring via113bis wider than the width of the lower surface thereof in terms of the process. In this case, the second wiring via113bmay be integrated with the pad pattern of the third wiring layer112c.

Although not illustrated in the drawing, a metal layer (not illustrated) may be disposed on a wall surface of the through-hole110H of the frame110for the purpose of shielding electromagnetic waves or for dissipating heat, and the metal layer (not illustrated) may surround the semiconductor chip120.

Other details may be substantially the same as those described above in relation to the semiconductor package100A according to the above-described example, and a detailed description thereof will be omitted.

FIG.15schematically illustrates another example of a fan-out semiconductor package.

Referring to the drawings, a semiconductor package100C according to another example may have a configuration different from the frame110in the semiconductor package100A according to the above-described example. For example, the frame110may include a first insulation layer111a, a first wiring layer112aand a second wiring layer112brespectively disposed on opposing lower and upper surfaces of the first insulation layer111a, a second insulation layer111band a third insulation layer111crespectively disposed on opposing lower and upper sides of the first insulation layer111aand respectively covering the first and second wiring layers112aand112b, a third wiring layer112cdisposed on a lower side of the second insulation layer111bopposite to a side in which the first wiring layer112ais embedded, a fourth wiring layer112ddisposed on an upper side of the third insulation layer111copposite to a side in which the second wiring layer112bis embedded, a first wiring via113apassing through the first insulation layer111aand electrically connecting the first and second wiring layers112aand112b, a second wiring via113bpassing through the second insulation layer111band electrically connecting the first and third wiring layers112aand112c, and a third wiring via113cpassing through the third insulation layer111cand electrically connecting the second and fourth wiring layers112band112d. The first to fourth wiring layers112a,112b,112c, and112dmay be electrically connected to the connection pad122through the redistribution layer142. Since the frame110has a relative large number of wiring layers112a,112b,112c, and112d, the connection structure140may be further simplified.

The first insulation layer111amay be thicker than the second insulation layer111band the third insulation layer111c. The first insulation layer111amay be relatively thick to maintain rigidity and the second insulation layer111band the third insulation layer111cmay be introduced to have a relative larger number of wiring layers. In a similar manner, the first wiring via113apassing through the first insulation layer111amay be greater in height and average diameter than the second and third wiring vias113band113cpassing through the second and third insulating layers111band111c. Further, the first wiring via113amay have an hourglass or cylindrical shape, while the second and third wiring vias113band113cmay have tapered shapes opposite to each other. The thickness of each of the wiring layers112a,112b,112c, and112dmay be thicker than the thickness of the redistribution layer142(e.g., thicker than the thickness of wiring layers provided within the redistribution layer142).

Other details may be substantially the same as those described in relation to the semiconductor package100A according to one example described above and the semiconductor package100B according to another example described above, and a detailed description thereof will be omitted.

In the present disclosure, the words lower, lower portion, lower surface, and the like are used to refer to the downward direction (in the vertical direction of the drawings, also referred to as the thickness direction) with respect to the cross section of the drawing for convenience, while the words upper, upper portion, upper surface, and the like are used to refer to a direction opposite thereto. It should be understood that the definitions refer to directions for convenience of explanation, that the scope of the claims is not particularly limited by the description of such directions, and that the concepts of the upward/downward directions may be changed at any time.

The term of “connect” or “connection” in the present disclosure may be not only a direct connection, but also a concept including an indirect connection through an adhesive layer or the like. In addition, the term “electrically connected” or “electrical connection” means a concept including both a physical connection and a physical non-connection. Also, the expressions of “first,” “second,” etc. are used to distinguish one component from another, and do not limit the order and/or importance of the components. In some cases, without departing from the spirit of the invention, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component.

The expression “an example embodiment” used in the present disclosure do not all refer to the same embodiment, but may be provided for emphasizing and explaining different unique features. However, the above-mentioned example embodiments do not exclude that they can be implemented in combination with the features of other example embodiments. For example, although the description in the specific example embodiment may not be described in another example embodiment, it may be understood as an explanation related to another example embodiment, unless otherwise described or contradicted by the other example embodiment.

The terms used in the present disclosure are used only to illustrate an example embodiment, and are not intended to limit the present disclosure. At this time, the singular expressions include plural expressions unless the context clearly dictates otherwise.

As one of the various effects of the present disclosure, there may be provided a semiconductor package which has excellent heat dissipation characteristics and reliability as well as warpage control, electromagnetic shielding effect, and improved yield of a semiconductor chip by introducing a heat-dissipating structure.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.