Patent ID: 12224324

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within +/−10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.25 nm to 5.75 nm where manufacturing tolerances associated with depositing the material layer are known to be +/−15% by one of ordinary skill in the art. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Source/drain contacts of transistors on a substrate are used to connect source/drain features of the transistors to an interconnect structure over a front side of the substrate. As the dimensions of IC devices shrink, the process windows for forming these contacts are reduced, and parasitic capacitance associated with transistors may increase. Backside power rail (BPR) structure is a solution for performance boost on power delivery network (PDN) for advanced technology node and it eases the crowding of contacts. In some processes, an initial substrate for fabrication includes a semiconductor layer formed of silicon. Formation of backside power rails involves forming a dummy plug in the silicon layer, replacing the silicon layer with a dielectric layer, and replacing the dummy plug with a backside contact. In some implantations, to replace the silicon layer with the dielectric layer, a dry etching process may be used to remove the silicon layer. However, dry etching does not provide a good etch selectivity between the silicon layer and dummy plug, leading to a damaged and dimension-reduced dummy plug, and thus leading to a dimension-reduced backside contact. In addition, exposing frontside features (e.g., gate structures) to a bombardment of ions used in the dry etching process would disadvantageously influence performance of the device and/or induce reliability issues. In some implantations, a wet etching process may be used to selectively remove the silicon layer. However, silicon has different crystal planes. The etch rate is dependent on crystal planes of the silicon due to, for example, their different bond configurations and atomic densities. For example, a wet etching process etches silicon more slowly along the <111> crystal orientation than all the other crystal orientations (e.g., <110>, <100>) in the lattice. Due to the etch rate difference, a portion of silicon may not be fully removed by the wet etching process and would remain at the back side. The unremoved silicon would disadvantageously introduce a leakage path between the backside contact and adjacent gate structures. Additionally or alternatively, because the dielectric constant of silicon is greater than the dielectric layer that replaces the silicon layer, the unremoved or residual silicon may increase a parasitic capacitance of the semiconductor structure, inducing reliability issues of the semiconductor structure. Alternatively, if the wet etching process is allowed to completely etch away the residual silicon layer, the gate structures may be damaged.

The present disclosure provides processes for forming a backside power rail structure. In some embodiments, a fin-shape structure is formed over a semiconductor layer. A source region and a drain region of the fin-shape structure are recessed to form a source opening and a drain opening. Using photolithography techniques, the source opening is selectively extended through at least of a portion of the semiconductor layer to form an extended opening. A semiconductor plug is then formed to fill the extended opening. A source feature is formed in the source opening and over the silicon plug, and a drain feature is formed in the drain opening. After forming a functional gate structure and an interconnect structure over a front side of the workpiece, the workpiece is bonded to a carrier substrate, flipped over, and planarized to expose the semiconductor plug and the semiconductor layer. A pre-amorphous implantation (PAI) process is then performed to amorphize the lattice structure of the semiconductor layer and convert the crystalline semiconductor layer into an amorphous semiconductor layer. Without non-uniform etching due to different crystal orientations, the amorphous semiconductor layer would be uniformly etched under a wet etching process. The etchant in the wet etching process selectively removes the amorphous semiconductor layer without substantially etching the semiconductor plug. A dielectric layer is formed, and the semiconductor plug may be selectively removed to expose the source feature in a backside source contact opening. A backside source contact is then formed in the backside source contact opening. A backside power rail is then formed over the backside source contact.

The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,FIG.1is a flowchart illustrating method100of forming a semiconductor device according to embodiments of the present disclosure. Method100is described below in conjunction withFIGS.2-17, which are fragmentary cross-sectional views of a workpiece200at different stages of fabrication according to embodiments of method100.FIG.18is a flowchart illustrating exemplary operations in an alternative method100′ of forming a semiconductor device according to embodiments of the present disclosure. Method100′ is described below in conjunction withFIGS.19-22, which are fragmentary cross-sectional views of a workpiece200at different stages of fabrication according to embodiments of method100′. Methods100and100′ are merely examples and are not intended to limit the present disclosure to what is explicitly illustrated therein. Additional steps may be provided before, during and after the method100and/or method100′, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. Because the workpiece200will be fabricated into a semiconductor device200upon conclusion of the fabrication processes, the workpiece200may be referred to as the semiconductor device200as the context requires. For avoidance of doubts, the X, Y and Z directions inFIGS.2-17and19-22are perpendicular to one another and are used consistently throughoutFIGS.2-17and19-22. Throughout the present disclosure, like reference numerals denote like features unless otherwise excepted.

Referring toFIGS.1and2, method100includes a block102where a workpiece200is received. The workpiece200includes a substrate201. In an embodiment, the substrate201is a bulk silicon substrate (i.e., including bulk single-crystalline silicon). The substrate201may include other semiconductor materials in various embodiment, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some alternative embodiments, the substrate201may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In the depicted embodiment, the substrate201is an SOI substrate and includes a carrier layer202, an insulator layer203on the carrier layer202, and a semiconductor layer204on the insulator layer203. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. In some embodiments, the semiconductor layer204may be silicon, silicon germanium, germanium, or other suitable semiconductor and may be undoped or unintentionally doped with a very low dose of dopants. In this depicted example, the carrier layer202includes silicon, the insulator layer203includes silicon oxide, and the semiconductor layer204includes silicon (i.e., single-crystalline silicon).

The workpiece200includes a fin-shaped structure205disposed over the substrate201. The fin-shaped structure205extends lengthwise along the X direction and is divided into channel regions205C overlapped by dummy gate stacks210(to be described below), source regions205S, and drain regions205D. In this depicted example, two channel regions205C, one source region205S, and two drain regions205D are shown inFIG.2, but the workpiece200may include more source/drain regions and channel regions. The fin-shaped structure205may be formed from a portion of the semiconductor layer204and a vertical stack of alternating semiconductor layers206and208using a combination of lithography and etch steps. An exemplary lithography process includes spin-on coating a photoresist layer, soft baking of the photoresist layer, mask aligning, exposing, post-exposure baking, developing the photoresist layer, rinsing, and drying (e.g., hard baking). In some instances, the patterning of the fin-shaped structure205may be performed using double-patterning or multi-patterning processes to create patterns having pitches smaller than what is otherwise obtainable using a single, direct photolithography process. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. In the depicted embodiment, the vertical stack of alternating semiconductor layers206and208may include a plurality of channel layers208interleaved by a plurality of sacrificial layers206. The channel layer208may be formed of silicon (Si) and the sacrificial layer206may be formed of silicon germanium (SiGe). The channel layers208and the sacrificial layers206may be epitaxially deposited on the substrate201using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and/or other suitable epitaxial growth processes.

While not explicitly shown inFIG.2, an isolation feature is also formed around the fin-shaped structure205to isolate the fin-shaped structure205from an adjacent fin-shaped structure. In some embodiments, the isolation feature is deposited in trenches that define the fin-shaped structure205. Such trenches may extend through the channel layers208and sacrificial layers206and terminate in the substrate201. The isolation feature may also be referred to as a shallow trench isolation (STI) feature. In an exemplary process, a dielectric material for the isolation feature is deposited over the workpiece200using CVD, subatmospheric CVD (SACVD), flowable CVD (FCVD), physical vapor deposition (PVD), spin-on coating, and/or other suitable process. Then the deposited dielectric material is planarized and recessed until the fin-shaped structure205rises above the isolation feature. The dielectric material for the isolation feature may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials.

Still referring toFIG.2, the workpiece200also includes dummy gate stacks210disposed over channel regions205C of the fin-shaped structure205. The channel regions205C and the dummy gate stack210also define source regions205S and drain regions205D that are not vertically overlapped by the dummy gate stacks210. Each of the channel regions205C is disposed between a source region205S and a drain region205D along the X direction. Two dummy gate stacks210are shown inFIG.2but the workpiece200may include more dummy gate stacks210. In this embodiment, a gate replacement process (or gate-last process) is adopted where the dummy gate stacks210serve as placeholders for functional gate structures. Other processes and configuration are possible. The dummy gate stack210includes a dummy dielectric layer211, a dummy gate electrode layer212over the dummy dielectric layer211, and a gate-top hard mask layer215over the dummy gate electrode layer212. The dummy dielectric layer211may include silicon oxide. The dummy gate electrode layer212may include polysilicon. The gate-top hard mask layer215may be a multi-layer that includes a silicon oxide layer213and silicon nitride layer214formed on the silicon oxide layer213. Suitable deposition process, photolithography and etching process may be employed to form the dummy gate stack210.

As shown inFIG.2, the workpiece200also includes a gate spacer layer216disposed over the workpiece200. In this depicted example, the gate spacer layer216includes a first gate spacer layer216aand a second gate spacer layer216bdeposited conformally over the workpiece200, including over top surfaces and sidewalls of the dummy gate stacks210and top surfaces of the fin-shaped structure205. The term “conformally” may be used herein for ease of description of a layer having substantially uniform thickness over various regions. In some implementations, a dielectric constant of the second gate spacer layer216bis greater than that of the first gate spacer layer216a, and the second gate spacer layer216bis more etch resistant than the first gate spacer layer216a. In some embodiments, the first gate spacer layer216amay include silicon oxide, silicon oxycarbide, or a suitable low-k dielectric material. The second gate spacer layer216bmay include silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. The first gate spacer layer216aand the second gate spacer layer216bmay be deposited over the dummy gate stacks210using processes such as, CVD, SACVD, FCVD, atomic layer deposition (ALD), PVD, or other suitable process.

Referring toFIGS.1and3, method100includes a block104where a source region205S and two drain regions205D of the fin-shaped structure205are recessed to form a source opening218S and two drain openings218D. In some embodiments, the source region205S and drain regions205D of the fin-shaped structures205that are not covered by the dummy gate stack210and the gate spacer layer216are anisotropically etched by a dry etch or a suitable etching process to form source opening218S and two drain openings218D. The etching process at block104may be a dry etching process or a suitable etching process. An exemplary dry etching process may implement an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. In embodiments represented inFIG.3, the source opening218S and drain openings218D extend through vertical stack of channel layers208and sacrificial layers206. The source opening218S and the drain openings218D may partially extend into the semiconductor layer204of the substrate201. As illustrated inFIG.3, sidewalls of the channel layers208and the sacrificial layers206are exposed in the source opening218S and drain openings218D.

Referring toFIGS.1and4-5, method100includes a block106where inner spacer features220are formed. After the formation of the source opening218S and the drain openings218D, the sacrificial layers206are exposed in the source opening218S and the drain openings218D. As shown inFIG.4, the sacrificial layers206are selectively and partially recessed to form inner spacer recesses219, while the exposed channel layers208are substantially unetched. In an embodiment where the channel layers208consist essentially of silicon (Si) and sacrificial layers206consist essentially of silicon germanium (SiGe), the selective and partial recess of the sacrificial layers206may include use of a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent at which the sacrificial layers206are recessed is controlled by duration of the etching process. After the formation of the inner spacer recesses219, an inner spacer material layer is deposited over the workpiece200, including in the inner spacer recesses219. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excessive inner spacer material layer over sidewalls of the channel layers208, thereby forming the inner spacer features220as shown inFIG.5. In some embodiments, the etch back process at block106may be a dry etching process and in a way similar to the dry etching process used in the formation of the source opening218S and drain openings218D.

Referring toFIGS.1and6, method100includes a block108where the source opening218S is selectively extended into the semiconductor layer204to form an extended opening226. In some embodiments, a mask film222is deposited over the workpiece200using CVD or ALD and then a photoresist layer224is deposited over the mask film222using spin-on coating or a suitable process. The photoresist layer224is patterned using photolithography process to form a patterned photoresist layer224. The patterned photoresist layer224is then applied as an etch mask in an etching process to pattern the mask film222. As shown inFIG.6, the patterned photoresist layer224and the patterned mask film222cover/protect the drain openings218D while the source opening218S is exposed. An anisotropic etching process is then performed to extend the source opening218S into the semiconductor layer204to form an extended opening226. In some implementations, the anisotropic etching process at block108may be a dry etching process and in a way similar to the dry etching process used in the formation of the source opening218S and drain openings218D. In some embodiments, the mask film222may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or silicon oxycarbide.

Referring toFIGS.1and7, method100includes a block110where a semiconductor plug228is formed in the extended opening226. In some embodiments, operations at block110may include a pre-clean process to remove native oxide and the photoresist layer224. The pre-clean process may include use of RCA SC-1 (a mixture of ammonium hydroxide, hydrogen peroxide and water) and/or RCA SC-2 (a mixture of hydrochloric acid, hydrogen peroxide and water). After the pre-clean process, with the mask film222still covering sidewalls of the drain openings218D, the semiconductor plug228may be selectively formed in the extended opening226using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD)), and/or other suitable epitaxial growth processes. The composition of the semiconductor plug228is different from that of the semiconductor layer204such that the semiconductor layer204may be selectively removed in a subsequent process. For example, when the semiconductor layer204is formed of silicon, the semiconductor plug228may include SiGe, boron-doped silicon (Si:B), phosphorus-doped silicon (Si:P), boron-doped SiGe (SiGe:B), arsenic-doped silicon (Si:As) or other suitable material such that the semiconductor layer204may be selectively removed without substantially etching the semiconductor plug228. After the formation of the semiconductor plug228, the mask film222covering the drain openings218D is selectively removed using a suitable etching process.

Referring toFIGS.1and8, method100includes a block112where a source feature232S is formed in the source opening218S and a drain feature232D is formed in the drain opening218D. In this illustrated example, after removing the mask film222, an epitaxial semiconductor feature230is formed at the bottom of the source opening218S (and over the semiconductor plug228) and at the bottom of the drain openings218D to reduce or substantially prevent a leakage between the to-be-formed source/drain features232S/232D and the semiconductor layer204and/or features to be formed at the backside of the workpiece200. The epitaxial semiconductor feature230may be epitaxially and selectively formed from the exposed top surfaces of the semiconductor layer204or the semiconductor plug228by using an epitaxial process, such as an MBE process, a VPE process, an UHV-CVD process, an MOCVD process, and/or other suitable epitaxial growth processes. A bottom surface of the epitaxial semiconductor feature230generally tracks the shape of the bottom surface of the drain openings218D or the exposed top surface of the semiconductor plug228. Because surfaces of the inner spacer features220are not conducive to epitaxial deposition of the epitaxial semiconductor feature230, the epitaxial semiconductor feature230is formed in a bottom-up fashion from the exposed surface of the substrate201. A cross-sectional view of the epitaxial semiconductor feature230includes a crescent shape. Depending on the conductivity type of the overlying source feature232S, the epitaxial semiconductor feature230may have different compositions. When the source feature232S is n-type, the epitaxial semiconductor feature230may include undoped silicon (Si), phosphorus-doped silicon (Si:P), or arsenic-doped silicon (Si:As). When the source feature232S is p-type, the epitaxial semiconductor feature230may include undoped silicon germanium (SiGe) or boron-doped silicon germanium (SiGe:B). In some implementations where the epitaxial semiconductor feature230includes silicon germanium, a germanium content in the epitaxial semiconductor feature230is less than a germanium content in the semiconductor plug228to introduce etch selectivity between the epitaxial semiconductor feature230and the semiconductor plug228. When the epitaxial semiconductor feature230is doped, the epitaxial semiconductor feature230and the overlying source feature232S may share the same dopant but at a lower concentration.

The source feature232S and the drain feature232D each may be then formed over the epitaxial semiconductor feature230by using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial process may use gaseous and/or liquid precursors, which interact with the composition of the epitaxial semiconductor feature230. The source feature232S and the drain feature232D are therefore coupled to the channel layers208in the channel regions205C of the fin-shape structure205. Depending on the conductivity type of the to-be-formed transistor, the source feature232S and the drain feature232D may be n-type source/drain features or p-type source/drain features. Exemplary n-type source/drain features may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable material and may be in-situ doped during the epitaxial process by introducing an n-type dopant, such as phosphorus, arsenic, or antimony, or ex-situ doped using a junction implant process. Exemplary p-type source/drain features may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable material and may be in-situ doped during the epitaxial process by introducing a p-type dopant, such as boron or gallium, or ex-situ doped using a junction implant process. In some embodiments, a lightly doped epitaxy semiconductor layer may be formed between the source/drain feature232S/232D and the corresponding epitaxial semiconductor feature230, and a doping concentration of the second epitaxy semiconductor layer is less than a doping concentration of the source/drain feature232S/232D.

Referring toFIGS.1and9, method100includes a block114where a contact etch stop layer (CESL)234and an interlayer dielectric layer (ILD) layer236are deposited over the workpiece200. The CESL234may include silicon nitride, silicon oxynitride, and/or other materials known in the art and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. As shown inFIG.9, the CESL234may be deposited on top surfaces of the source feature232S, the drain features232D, and sidewalls of the gate spacer layer216. The ILD layer236is deposited by a PECVD process or other suitable deposition technique over the workpiece200after the deposition of the CESL234. The ILD layer236may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, after formation of the ILD layer236, the workpiece200may be annealed to improve integrity of the ILD layer236.

Referring toFIGS.1and10, method100includes a block116where the dummy gate stacks210are replaced with the functional gate structures240. A planarization process, such a chemical mechanical polishing (CMP) process may be performed to the workpiece200to remove excessive materials and expose top surfaces of the dummy gate stacks210. With the exposure of the dummy gate stacks210, block116proceeds to removal of the dummy gate stacks210. The removal of the dummy gate stacks210may include one or more etching process that are selective to the material in the dummy gate stacks210. For example, the removal of the dummy gate stacks210may be performed using a selective wet etch, a selective dry etch, or a combination thereof. After the removal of the dummy gate stacks210, the sacrificial layers206are selectively removed to release the channel layers208as channel members208in the channel regions205C. The selective removal of the sacrificial layers206may be implemented by a selective dry etch, a selective wet etch, or other selective etching process. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture).

The gate structures240are deposited to wrap over the channel members208. Each of the gate structures240includes a gate dielectric layer242and a gate electrode layer244over the gate dielectric layer242. In some embodiments, the gate dielectric layer242includes an interfacial layer disposed on the channel members208and a high-k dielectric layer over the interfacial layer. Here, a high-k dielectric layer refers to a dielectric material having a dielectric constant greater than that of silicon dioxide, which is about 3.9. In some embodiments, the interfacial layer includes silicon oxide and may be formed in a pre-clean process similar to the pre-clean process described with reference toFIG.7. The high-k dielectric layer is then deposited over the interfacial layer using ALD, CVD, and/or other suitable methods. The high-k dielectric layer may include hafnium oxide. Alternatively, the high-k dielectric layer may include other high-k dielectrics, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, SrTiO3, BaTiO3, BaZrO, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba,Sr)TiO3(BST), silicon nitride, silicon oxynitride, combinations thereof, or other suitable material.

The gate electrode layer244is then deposited over the gate dielectric layer242using ALD, PVD, CVD, e-beam evaporation, or other suitable methods. The gate electrode layer244may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the gate electrode layer244may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, tantalum silicon nitride, copper, other refractory metals, or other suitable metal materials or a combination thereof. Further, where the semiconductor device200includes n-type transistors and p-type transistors, different gate electrode layers may be formed separately for n-type transistors and p-type transistors, which may include different work function metal layers (e.g., for providing different n-type and p-type work function metal layers).

Referring toFIGS.1and11, method100includes a block118where a first interconnect structure246is formed over the workpiece200. In some embodiments, the first interconnect structure246may include multiple intermetal dielectric (IMD) layers and multiple metal lines or contact vias in each of the IMD layers. In some instances, the IMD layers and the ILD layer236may share similar composition. The metal lines and contact vias in each IMD layer may be formed of metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined by a barrier layer to insulate the metal lines and contact vias from the IMD layers and to prevent electro-migration. Because the first interconnect structure246is formed over the front side of the workpiece200, the first interconnect structure246may also be referred to as a frontside interconnect structure246.

Still referring toFIGS.1and11, method100includes a block120where a carrier substrate250is bonded to the first interconnect structure246and the workpiece200is flipped over and planarized to expose the semiconductor plug228. In some embodiments, the carrier substrate250may be bonded to the workpiece200by fusion bonding, by use of an adhesion layer, or a combination thereof. In some instances, the carrier substrate250may include semiconductor materials (such as silicon), sapphire, glass, polymeric materials, or other suitable materials. In embodiments where fusion bonding is used, the carrier substrate250includes a bottom oxide layer and the first interconnect structure246includes a top oxide layer. After both the bottom oxide layer and top oxide layer are treated, they are placed in flush contact with one another for direct bonding at room temperature or at an elevated temperature. Once the carrier substrate250is bonded to the first interconnect structure246of the workpiece200, the workpiece200is flipped over, as shown inFIG.11, the substrate201is at the top and is disposed over the channel members208. The back side of the workpiece200is then planarized to remove the carrier layer202, the insulator layer203, and a portion of the semiconductor layer204to expose the semiconductor plug228.

Referring toFIGS.1and12-13, method100includes a block122where the semiconductor layer204is selectively removed to form dielectric openings254. In this embodiment, as shown inFIG.12, the removal of the semiconductor layer204includes, at block123, performing a pre-amorphous implantation (PAI) process300to amorphize the semiconductor layer204. The PAI process300implants the semiconductor layer204with an implant species, randomizing the lattice structure of the semiconductor layer204and forming amorphous semiconductor layer204′. In PAI process300, the implant species may include Si, C, Ge, Xe, Ar, B, or other suitable species. In the depicted embodiment, the PAI process300implants Ge, Ar, or B at an implant energy from about 5 KeV to about 40 KeV, a dosage in a range from about 1 E13 atoms/cm2to about 1 E16 atoms/cm2, a temperature in a range from about −30° C. to about 30° C., and an implant angle (an angle between the implant ion beam and the −Z axis) in a range of 0° to about 30°. In this depicted example, the implant angle is about 0°. That is, the implant ion beam of the PAI process300is substantially perpendicular to the backside of the semiconductor layer204. The PAI process300is controlled such that the semiconductor layer204in the workpiece200is fully amorphized. Considering the shrunk dimensions of IC devices, misalignment during mask aligning in a lithography process, and fabrication cost, no masking layer is formed on the semiconductor plug228during the PAI process. Thus, at least a portion of the semiconductor plug228is amorphized and would include amorphous semiconductor plug (e.g., a-SiGe). The semiconductor plug228after the PAI process300is herein interchangeably referred as to amorphous semiconductor plug228′. It is observed that the PAI process300does not change the etch selectivity between the amorphous semiconductor plug228′ and the amorphous semiconductor layer204′. After the PAI process300, the gate structures240adjacent to the amorphous semiconductor layer204′ and the source feature232S adjacent to the amorphous semiconductor plug228′ may also include the implant species (e.g., Ge, Ar, or, B) used in the PAI process300.

The removal of the semiconductor layer204also includes, at block125, performing a wet etching process to selectively remove the amorphous semiconductor layer204′ and form dielectric openings254, as shown inFIG.13. The wet etching process may implement an alkaline wet etchant solution that includes KOH, TMAH (tetramethylammonium hydroxide), NH4OH, other suitable chemicals, or combinations thereof. As described above, along different crystal orientations in the lattice, wet etching etches silicon at different etch rates. Due to the etch rates difference, a portion of silicon, such as a portion of the silicon adjacent the semiconductor plug228, may not be removed without damaging the gate structures240and would remain at the back side after the wet etching. By converting the semiconductor layer204into amorphous semiconductor layer204′, the lattice structures in the semiconductor layer204are randomized, and the etch rate difference may be substantially eliminated. The amorphous semiconductor layer204′ may be substantially removed by the wet etching process to form the dielectric openings254. As alkaline etchants etch amorphous silicon more slowly than they do crystalline silicon, a concentration of the wet etchant solution used in block125may be increased to make up for the slower etching rate and thus improve fabrication efficiency. For example, when a NH4OH solution is used to remove the amorphous semiconductor layer204′, the concentration of the NH4OH solution may be between about 1:5 and about 1:20, which is higher than a concentration of NH4OH solution used for etching crystalline semiconductor layer204in block151ofFIG.18(to be described below). In some embodiments, the concentration of the NH4OH solution used for removing the amorphous semiconductor layer204′ is about 5 to about 10 times of the concentration of the NH4OH solution used for etching crystalline semiconductor layer204in block151ofFIG.18. The duration of the etching process in block125may be between about 60 seconds and about 300 seconds. The process temperature may be between about 50° C. and about 70° C.

Referring toFIGS.1and14-15, method100includes a block126where a dielectric layer256is formed in the dielectric opening254and the amorphous semiconductor plug228′ is selectively removed. The dielectric layer256may be deposited over a back side of the workpiece200by FCVD, CVD, PECVD, spin-on coating, or a suitable process. In some instances, the dielectric layer256may include silicon oxide or have a composition similar to that of the ILD layer236. As shown inFIG.14, after the dielectric layer256is formed, the drain features232D are spaced apart from the dielectric layer256by the epitaxial semiconductor feature230. A planarization process, such as a CMP process, may be performed to planarize the back side of the workpiece200and expose the amorphous semiconductor plug228′. As shown inFIG.15, the amorphous semiconductor plug228′ is then selectively removed. The selective removal of the amorphous semiconductor plug228′ may be self-aligned because the amorphous semiconductor plug228′, which is formed of a semiconductor material, is disposed among the dielectric layer256, which is formed of dielectric materials. In these embodiments, the selective removal of the amorphous semiconductor plug228′ may be performed using a selective wet etching process or a selective dry etching process. An example selective wet etching process may include use of nitric acid. An example selective dry etching process may be in a way similar to the dry etching process used in the formation of the source opening218S and drain openings218D described with reference toFIG.3. Because the selective etching process at block126etches the amorphous semiconductor plug228′ faster than it etches the dielectric layer256, the amorphous semiconductor plug228′ may be removed with little or no damage to the dielectric layer256. The etching process is stopped when the epitaxial semiconductor feature230disposed between the source feature232S and the amorphous semiconductor plug228′ is removed. Thus, the source feature232S is exposed in a backside source contact opening260from the back side of the workpiece200.

Referring toFIGS.1and16, method100includes a block128where a backside source contact266is formed in the backside source contact opening260. In this depicted example, a dielectric barrier layer262is deposited over the workpiece200and is then etched back to only cover sidewalls of the backside source contact opening260and expose the source feature232S. In some embodiments, the dielectric barrier layer262may include silicon nitride or other suitable materials. Operations at block128also includes forming a silicide layer264on the exposed surface of the source feature232S to reduce a contact resistance between the source feature232S and the to-be-formed backside source contact266. To form the silicide layer264, a metal layer is deposited over the exposed surfaces of the source feature232S and an anneal process is performed to bring about silicidation reaction between the metal layer and the source feature232S. Suitable metal layer may include titanium, tantalum, nickel, cobalt, or tungsten. In embodiments where the metal layer includes nickel and the source feature232S includes silicon germanium, the silicide layer264includes nickel silicide, nickel germanide, and nickel germanosilicide. The silicide layer264generally tracks the shape of the exposed source feature232S. Excessive metal layer that does not form the silicide layer264may be removed. After the formation of the silicide layer264, the backside source contact266may be formed in the backside source contact opening260. The backside source contact266may include aluminum, rhodium, ruthenium, copper, iridium, or tungsten. A planarization process, such as a CMP process, may follow to remove excessive materials and provide a planar surface. The backside source contact266is electrically coupled to the source feature232S by way of the silicide layer264. In other words, the silicide layer264is sandwiched between the source feature232S and the backside source contact266.

Referring toFIGS.1and17, method100includes a block130where a backside power rail270is formed. While not explicitly shown inFIG.17, the backside power rail270may be embedded in an insulation layer. In an exemplary process, an insulation layer having a composition similar to the ILD layer236may be deposited over the backside of the workpiece200, including over the dielectric layer256, the isolation feature, and the backside source contact266. Then, a power rail trench may be patterned in the insulation layer. A barrier layer and a metal fill material are then deposited into the power rail trench to form the backside power rail270. In some embodiments, the barrier layer in the backside power rail270may include titanium nitride, tantalum nitride, cobalt nitride, nickel nitride, or tungsten nitride and the metal fill material in the backside power rail270may include titanium, ruthenium, copper, nickel, cobalt, tungsten, tantalum, or molybdenum. The barrier layer and the metal fill layer may be deposited using PVD, CVD, ALD, or electroless plating. A planarization process, such as a CMP process, may be performed to remove excessive materials over the insulation layer. A second interconnect structure272is formed and has a structure in a way similar to the first interconnect structure246. Because the second interconnect structure272is formed over the back side of the workpiece200, the second interconnect structure272may also be referred to as a backside interconnect structure272.

In methods and structures depicted above, the semiconductor layer204is removed as described in block122of method100inFIG.1. As the same alkaline etchant etches crystalline semiconductor layer204at a rate much greater than it does the amorphous semiconductor layer204′, the duration of etching the amorphized semiconductor layer204′ may be prolonged. It is observed that, when an alkaline etchant is used, the etch rate of the amorphous semiconductor layer204′ may be between 0.1 and 0.5 times of the etch rate of the crystalline semiconductor layer204. An alternative method100′ of selectively and substantially removing the semiconductor layer204is described with reference toFIG.18in conjunction withFIGS.19-22. In this alternative method100′, block122of method100is replaced with block122′ to shorten the duration of the etching process used to remove the semiconductor layer204. By reducing process time, the fabrication efficiency may be improved. Like block122of method100, operations in block122′ of method100′ are configured to selectively remove the semiconductor layer204to form dielectric openings254. Different from method100, method100′ includes a first wet etching process before the PAI process400aand a second wet etching process after the PAI process400b. To take advantage of the faster pre-PAI etch rate, the first etching process is configured to remove a bulk portion of the semiconductor layer204, leaving behind residual portions of the semiconductor layer204to protect the gate structure from the PAI processes400aand400b(to be discussed in detail with references toFIGS.20-21). After the PAI processes400aand400b, a second wet etching process is performed to remove the amorphized residual portions, albeit at a slower etch rate.

Referring first toFIGS.18and19, method100′ includes block151where a first wet etching process is performed to remove a bulk portion of the semiconductor layer204, leaving behind the unetched portions204aand204b(herein interchangeably referred as to silicon residues204aand204b) of the semiconductor layer204, as shown inFIG.19. It is noted that, the first etching process is timed or controlled such that the silicon residues204aand204binclude a portion directly disposed on the gate structures240to reduce the damage suffered by the gate structures240, which is induced by a PAI process that follows.

Now referring toFIGS.18and20-21, block122′ also includes block152where a PAI process is performed to amorphize the silicon residues204aand204b. In this depicted example, as shown inFIG.20, the PAI process in block152includes a first tilted PAI process400aconfigured to amorphize the silicon residue204a. As shown inFIG.21, the PAI process in block152also includes a second tilted PAI process400bconfigured to amorphize the silicon residue204b. The first tilted PAI process400aand the second tilted PAI process400bimplant the silicon residues204aand204bwith an implant species, randomizing the lattice structure of these regions and forming amorphized silicon residues204a′ and204b′, respectively. The first tilted PAI process400aand the second tilted PAI process400bmay implant a species, such as Si, C, Ge, Xe, Ar, B, or other suitable species. In the depicted embodiment, the first tilted PAI process400aand the second tilted PAI process400bimplant Ge, Ar, or, B into the silicon residues204aand204b. A tilt angle A (shown inFIG.20) between the implant ion beam of the first tilted PAI process400aand the −Z axis may be between 45° and 85°. A tilt angle B (shown inFIG.21) between the implant ion beam of the second tilted PAI process400band the −Z axis may be between 45° and 85°. In this embodiment, after the first tilted PAI process400aand the second tilted PAI process400b, the silicon residue204aand204bare fully amorphized, and the semiconductor plug228is at least partially amorphized and includes amorphous silicon germanium (a-SiGe). The gate structures240adjacent to the amorphous semiconductor layer204′ and the source feature232S adjacent to the amorphous semiconductor plug228′ may also include the implant species used in the first and second PAI processes400aand400b.

In some embodiments, before performing the first and/or the second tilted PAI processes400aand400b, the workpiece200may be inspected, for example, by using transmission electron microscope (TEM), scanning electron microscope (SEM), or suitable optical scan methods to determine a shape, dimension, and location of the silicon residue. The first tilted PAI process400aand/or the second tilted PAI process400bmay be configured based on the shape, dimension, and/or location of the silicon residue to substantially amorphize the silicon residue204aand204b.

Referring toFIGS.15and22, block122′ includes block153where a second etching process is conducted to selectively remove the amorphous silicon residues204a′ and204b′ to form the dielectric openings254. Each of the first etching process (in block151) and the second etching process (in block153) may be a selective wet etching process that implements an alkaline wet etchant solution (e.g., includes KOH, TMAH, NH4OH, other suitable chemicals, or combinations thereof). In some embodiments, the first etch process and the second etch process may use the same etchant with different concentrations. For example, a concentration of the etchant in the second etch process may be greater than the etchant in the first etch process to make up for the slower etch rate for the amorphized residual portions. Further processes may be performed in a way similar to those described in blocks126,128and130andFIGS.14-17to form a backside source contact266and a backside power rail270.

Embodiments of the present disclosure provide advantages. For example, methods of the present disclosure include processes for replacing a semiconductor layer with a dielectric layer and replacing a semiconductor plug with a backside contact. In some embodiments, before replacing the semiconductor layer with a dielectric layer, a PAI process is performed to amorphize the semiconductor layer. By implementing the PAI, the lattice structure in the semiconductor layer are randomized, and the semiconductor layer may be substantially removed by a wet etching process. Therefore, a leakage path, which would be introduced by the semiconductor residue, may be eliminated or substantially reduced. Moreover, a parasitic capacitance of the semiconductor structure may be advantageously reduced. Therefore, reliability and performances of the semiconductor structure may be thus improved.

The present disclosure provides for many different embodiments. Semiconductor structures and methods of fabrication thereof are disclosed herein. In one exemplary aspect, the present disclosure is directed to a method. The method includes forming a fin structure extending from a front side of a substrate, forming a gate stack over a channel region of the fin structure, recessing a source region and a drain region of the fin structure to form a source opening and a drain opening, the channel region being disposed between the source region and the drain region, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize the substrate, replacing the amorphized substrate with a dielectric layer, and replacing the semiconductor plug with a backside source contact.

In some embodiments, the performing of the PAI process may include implanting germanium (Ge), argon (Ar), or boron (B) into the substrate and the semiconductor plug. In some embodiments, the replacing of the amorphized substrate with the dielectric layer may include performing a wet etching process to selectively remove the amorphized substrate to form a recess, depositing the dielectric layer in the recess, and planarizing the dielectric layer to expose the semiconductor plug. In some embodiments, the performing of the wet etching process may include implementing a KOH solution, a TMAH solution, or a NH4OH solution. In some embodiments, the substrate may include silicon, and the semiconductor plug may include silicon germanium, boron-doped silicon, or phosphorus-doped silicon. In some embodiments, the replacing of the semiconductor plug with the backside source contact may include selectively etching the semiconductor plug to release the plug opening, depositing a conductive material layer to fill the plug opening, and planarizing the conductive material layer to remove excessive conductive material layer.

In some embodiments, the fin structure may include a stack of first semiconductor layers and second semiconductor layers alternately arranged one over another, each of the first semiconductor layers may include silicon germanium, and each of the second semiconductor layers includes silicon. In some embodiments, the PAI process may include an implantation angle substantially perpendicular to the back side of the substrate.

In another exemplary aspect, the present disclosure is directed to a method. The method includes receiving a workpiece including a fin-shaped structure over a substrate, forming a source opening in the fin-shaped structure, extending the source opening into the substrate to form an extended opening, forming a sacrificial plug in the extended opening, forming a source feature in the source opening and over the sacrificial plug, planarizing a back side of the substrate to expose the sacrificial plug, after the planarizing, performing a pre-amorphous implantation (PAI) process to the workpiece to amorphize the substrate, performing a wet etching process to selectively remove the amorphized substrate, depositing a dielectric layer, and replacing the sacrificial plug with a backside source contact.

In some embodiments, the PAI process may include an implantation angle substantially perpendicular to the back side of the substrate. In some embodiments, the method may also include, before the performing of the PAI process, performing a pilot wet etching process to selectively and partially etch the substrate without substantially etching the sacrificial plug. In some embodiments, the pilot wet etching process may etch the substrate at a rate greater than a rate at which the wet etching process etches the amorphized substrate.

In some embodiments, the pilot wet etching process may include an etchant having a first concentration, the wet etching may include the etchant having a second concentration greater than the first concentration. In some embodiments, an angle between an ion beam of the PAI process and a back surface of the substrate may be between about 45° and 85°.

In some embodiments, the replacing of the sacrificial plug with the backside source contact may include selectively etching the sacrificial plug to expose the source feature in a backside source contact opening, selectively forming a dielectric liner on sidewalls of the backside source contact opening, forming a silicide layer on the source feature, and depositing a metal fill layer over the silicide layer in the backside source contact opening. In some embodiments, the method may also include, before the forming of the source feature, performing an epitaxial growth process to epitaxially grow an epitaxial layer over the sacrificial plug, wherein the epitaxial layer is formed of un-doped silicon germanium.

In yet another exemplary aspect, the present disclosure is directed to a method. The method includes providing a substrate including a first semiconductor layer on an insulator layer, forming a stack of second semiconductor layers and third semiconductor layers alternately arranged one over another on the substrate, patterning the stack to form a fin-shaped structure over the insulator layer, forming a gate structure over the fin-shaped structure, recessing the fin-shaped structure to form a source opening and a drain opening, selectively extending the source opening further into the first semiconductor layer to form a backside contact opening, forming a sacrificial layer in the backside contact opening, forming a source feature in the source opening and over the sacrificial layer, planarizing a back side of the substrate to remove the insulator layer and expose the sacrificial layer and the first semiconductor layer, implanting a dopant to the back side of the substrate to convert the first semiconductor layer into an amorphous semiconductor layer, replacing the amorphous semiconductor layer with a dielectric layer, and replacing the sacrificial layer with a backside source contact.

In some embodiments, the first semiconductor layer and the third semiconductor layers may include silicon, the second semiconductor layers may include silicon germanium (SiGe), and the sacrificial layer may include silicon germanium, boron-doped silicon, or phosphorus-doped silicon. In some embodiments, the method may also include, after the forming of the source feature, forming a first interconnect structure over the source feature and electrically connected to the gate structure, and, after forming the backside source contact, forming a second interconnect structure electrically connected to the backside source contact, wherein the second interconnect structure includes a backside power rail in contact with the backside source contact. In some embodiments, the replacing of the amorphous semiconductor layer with the dielectric layer may include performing a wet etching process to selectively remove the amorphous semiconductor layer to form a recess, depositing the dielectric layer in the recess, and planarizing the dielectric layer to expose the sacrificial layer.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.