Patent ID: 12191778

DESCRIPTION OF THE EMBODIMENTS

Some embodiments of the disclosure accompanied with the drawings will now be described in detail. In the reference numerals recited in description below, the same reference numerals shown in different drawings will be regarded as the same or similar elements. These embodiments are only a part of the disclosure and do not disclose all possible implementations of the disclosure. To be more precise, these embodiments are only examples of the appended claims of the disclosure.

With reference toFIG.1,FIG.1is a schematic diagram of waveforms according to a dynamic current and an inductor current of an existing power converter in the field of high-power applications. In the field of high-power applications, when the existing power converter performs boost conversion on an AC power, a drastically changing dynamic current value v_ID may be generated. The drastic dynamic current value v_ID may directly affect the response of inductor current switching. As shown inFIG.1, it can be found that an inductor current value v_IL has the most drastic fluctuation near the peak of the dynamic current value v_ID of a power supply. The vibration frequency generated by the fluctuation of the inductor current value v_IL is within the auditory frequency range of the human ear. As such, a user may hear noise when the inductor current value v_IL fluctuates relatively drastically.

In this disclosure, the fluctuation of the inductor current is suppressed near the peak of the dynamic current, thus suppressing noise.

With reference toFIG.2andFIG.3together,FIG.2is a schematic diagram of a power converter according to an embodiment of the disclosure, andFIG.3is a flowchart of an operation method according to an embodiment of the disclosure. In this embodiment, a power converter100includes a rectifier110, a boost circuit120, a current sensor130, and a processor140. The rectifier110rectifies an AC power VAC at an input end to generate a rectified power VR. The current value of the rectified power VR is the dynamic current value v_ID. The rectifier110of this embodiment may be a bridge rectifier. In this embodiment, the boost circuit120includes a boost inductor LM. The boost circuit120boosts the rectified power VR to generate an output power VOUT.

The boost circuit120may be a circuit with a power factor correction (PFC) function. For example, the boost circuit120also includes a power switch Q, a diode DO, and a capacitor CO (but the disclosure is not limited thereto). The boost inductor LM is coupled between an anode of the diode DO and the rectifier110. A first end of the power switch Q is coupled to the anode of the diode DO. A second end of the power switch Q is coupled to a reference low voltage (e.g., a ground). A control end of the power switch Q receives a control signal SC. Turning on or off the power switch Q determines the inductor current value v_IL of the boost inductor LM. A first end of the capacitor CO is coupled to a cathode of the diode DO. A second end of the capacitor CO is coupled to the reference low voltage. The first end of the capacitor CO serves as an output end of the boost circuit120.

In this embodiment, the current sensor130senses the inductor current value v_IL of the boost inductor LM to generate a sensed value SV corresponding to the inductor current value v_IL in step S110. The base value of the inductor current value v_IL may fluctuate along with the dynamic current value v_ID. The inductor current value v_IL may fluctuate in response to the operation of the power switch Q. It should be noted that the fluctuation of the sensed value SV may directly reflect the fluctuation of the inductor current value v_IL. For example, the sensed value SV is substantially equal to the inductor current value v_IL.

The processor140is coupled to the rectifier110, the boost circuit120, and the current sensor130. In step S120, the processor140receives an input impedance value RIN of the input end and an output voltage value v_VO of an output power VOUT, and the processor140generates a first reference value VR1according to the output voltage value v_VO, the input impedance value RIN, and a first value V1. The processor140determines whether the sensed value SV is greater than the first reference value VR1. In step S130, when the sensed value SV is determined to be greater than the first reference value VR1, the processor140enters a first operation mode. In this embodiment, in the first operation mode, the processor140controls the boost circuit120to cause the sensed value SV to be not less than the first reference value VR1. Therefore, the drastic fluctuation of the inductor current value v_IL can be reduced. Accordingly, the power converter100can suppress noise of the power converter.

With reference toFIG.2andFIG.4together,FIG.4is a schematic diagram of waveforms of a current of a power converter according to an embodiment of the disclosure. In this embodiment, the first reference value VR1may be obtained according to Formula (1):
VR1=v_VO/(V1×RIN)  Formula (1)

In other words, the processor140divides the output voltage value v_VO by a product of the first value V1and the input impedance value RIN to generate the first reference value VR1. In this embodiment, the first value V1may be set so that the first reference value VR1is close to the peak value corresponding to the dynamic current value v_ID. The first reference value VR1is, for example, 95% of the peak value (but the disclosure is not limited thereto). In this embodiment, the first value V1is, for example, equal to 4 (but the disclosure is not limited thereto).

In this embodiment, the processor140may provide the control signal SC with a first switching frequency in the first operation mode, and use the control signal SC with the first switching frequency to control the power switch Q. The first switching frequency is, for example, 35 kHz (but the disclosure is not limited thereto). In addition, when the sensed value SV drops to be equal to the first reference value VR1in the first operation mode, the processor140turns on the power switch Q. As a result, the inductor current value v_IL rises, and the sensed value SV also rises. Therefore, the fluctuation of the inductor current value v_IL can be limited by the first reference value VR1.

In this embodiment, the processor140generates a second reference value VR2according to the output voltage value v_VO, the input impedance value RIN, and a second value V2. In this embodiment, the second reference value VR2may be obtained according to Formula (2):
VR2=v_VO/(V2×RIN)  Formula (2)

The processor140divides the output voltage value v_VO by a product of the second value V2and the input impedance value RIN to generate the second reference value VR2. The second value V2is greater than the first value V1. Therefore, the second reference value VR2is less than the first reference value VR1.

In this embodiment, the second value V2may be set so that the second reference value VR2is substantially equal to the upper limit value under light load of the dynamic current value v_ID. In this embodiment, the second value V2is, for example, 5.5 (but the disclosure is not limited thereto).

In a case where the sensed value SV is less than or equal to the first reference value VR1, the processor140may further determine whether the sensed value SV is greater than the second reference value VR2. When the sensed value SV is determined to be greater than the second reference value VR2and less than or equal to the first reference value VR1, the processor140enters a second operation mode. The processor140may provide the control signal SC with a second switching frequency in the second operation mode, and use the control signal SC with the second switching frequency to control the power switch Q. The processor140controls the boost circuit120based on the second switching frequency to prevent generation of electromagnetic interference in the power converter100. In this embodiment, the second frequency is, for example, 35 kHz (but the disclosure is not limited thereto).

When the sensed value SV is determined to be less than or equal to the second reference value VR2, the processor140enters a third operation mode. In the third operation mode, the processor140controls the boost circuit based on a frequency range to maintain the optimal efficiency of the power converter under light load. The frequency range may be 65 kHz to 85 kHz, for example.

In this embodiment, the processor140may also determine whether a variation frequency of the inductor current value v_IL is abnormal. Specifically, the processor140may be coupled to the boost inductor LM through a resistor RX to sense the actual variation frequency of the inductor current value v_IL. When the variation frequency of the inductor current value v_IL obviously does not match the logic level of the control signal SC or the on/off state of the power switch Q, the processor140determines that the variation frequency of the inductor current value v_IL is abnormal. In addition, when the variation frequency of the inductor current value v_IL generally matches the logic level of the control signal SC or the on/off state of the power switch Q, the processor140determines that the variation frequency of the inductor current value v_IL is not abnormal. In this embodiment, the resistor RX is configured to serve as a protective resistor to prevent the processor140from damage from the dynamic current value v_ID.

With reference toFIG.2andFIG.5together,FIG.5is a flowchart of another operation method according to an embodiment of the disclosure. In this embodiment, the current sensor130senses the inductor current value v_IL of the boost inductor LM to generate the sensed value SV corresponding to the inductor current value v_IL in step S210. In step S220, the processor140receives the input impedance value RIN of the input end and the output voltage value v_VO of the output power VOUT, the processor140generates the first reference value VR1according to the output voltage value v_VO, the input impedance value RIN, and the first value V1, and the processor140also generates the second reference value VR2according to the output voltage value v_VO, the input impedance value RIN, and the second value V2. In step S230, the processor140determines the sensed value SV. When the sensed value SV is determined to be greater than the first reference value VR1in step S230, it means that the current value (v_ID as shown in FIG.1) of the dynamic current entering the boost inductor LM is greater than the first reference value VR1. In other words, the current value of the dynamic current is near the peak, and thus the inductor current value v_IL is greater than the first reference value VR1. As a result, the processor140enters the first operation mode in step S240. In the first operation mode, the processor140controls the boost circuit120to cause the sensed value SV to be not less than the first reference value VR1. Therefore, the fluctuation of the inductor current value v_IL can be reduced. Accordingly, the power converter100can suppress noise of the power converter.

When the sensed value SV is determined to be less than or equal to the first reference value VR1and greater than the second reference value VR2in step S230, it means that the current value of the dynamic current causes the inductor current value v_IL to be between the first reference value VR1and the second reference value VR2. As a result, the processor140enters the second operation mode in step S250. In the second operation mode, the processor140controls the boost circuit120based on a switching frequency to prevent generation of electromagnetic interference in the power converter100.

When the sensed value SV is determined to be less than or equal to the second reference value VR2in step S230, it means that the current value of the dynamic current causes the inductor current value v_IL to be less than or equal to the second reference value VR2. As a result, the processor140enters the third operation mode in step S260. In the third operation mode, the processor140controls the boost circuit120based on the frequency range to maintain the optimal efficiency of the power converter100under light load.

Examples will provided to describe the implementation details of the current sensor and the processor. With reference toFIG.6,FIG.6is a schematic circuit block diagram of a power converter according to an embodiment of the disclosure. In this embodiment, a power converter200includes a rectifier210, a boost circuit220, a current sensor230, and a processor240. The current sensor230includes a coupled inductor LN, a sensing resistor RS, and a discharging capacitor CD. The coupled inductor LN and the boost inductor LM are inductively coupled to induce the inductor current value v_IL. For example, the boost inductor LM, the coupled inductor LN, and a magnetic element (e.g., an iron core) may form an inductive coupling circuit. Nonetheless, the disclosure is not limited thereto. A first end of the sensing resistor RS is coupled to a first end of the coupled inductor LN. A second end of the sensing resistor RS is coupled to a reference low voltage. The sensing resistor RS is configured to determine the numerical relationships between the sensed value SV and the inductor current value v_IL. The sensing resistor RS of this embodiment may have a resistance value of 1Ω (but the disclosure is not limited thereto). As such, the value of the sensed value SV is substantially equal to the value of the inductor current value v_IL. A first end of the discharging capacitor CD is coupled to a second end of the coupled inductor LN. A second end of the discharging capacitor CD is coupled to the second end of the sensing resistor RS. The discharging capacitor CD serves as an energy discharge path for the sensing resistor RS and the coupled inductor LN. Accordingly, the current sensor230may have a faster response speed, so that the sensed value SV can reflect the fluctuation of the inductor current value v_IL in real-time.

In this embodiment, the processor240includes an input impedance sensor241, a calculator242, a comparator243, a mode controller244, and a driver245. The input impedance sensor241senses the real-time input impedance value RIN. The calculator242is coupled to the input impedance sensor241. The calculator242receives the output voltage value v_VO, and based on Formula (1), multiplies the input impedance value RIN and the first value V1to produce the first product and divides the output voltage value v_VO by the first product to generate the first reference value VR1. In some embodiments, the calculator242may be implemented at least by a divider. The divider may divide the output voltage value v_VO by the input impedance value RIN and then by the first value V1to generate the first reference value VR1.

Further, the resistor R1may be set between the calculator242and a reference low voltage. The resistor R1may be configured to determine the voltage value corresponding to the first reference value VR1.

In this embodiment, the comparator243is coupled to the calculator242and the current sensor230. The comparator243compares the sensed value SV with the first reference value VR1to generate a first comparison result CP1. In this embodiment, a non-inverting input end of the comparator243is coupled to the current sensor230, an inverting input end of the comparator243is coupled to the calculator242, and an output end of the comparator243is coupled to the mode controller244.

In this embodiment, the mode controller244is coupled to the comparator243. The mode controller244receives the first comparison result CP1. When the first comparison result CP1indicates that the sensed value SV is greater than the first reference value VR1, the mode controller244controls the processor240to enter the first operation mode. In this embodiment, when the first comparison result CP1indicates that the sensed value SV is greater than the first reference value VR1, the comparator243outputs the first comparison result CP1at a high voltage level, and the mode controller244controls the processor240to enter the first operation mode. In addition, when the first comparison result CP1indicates that the sensed value SV is less than or equal to the first reference value VR1, the comparator243outputs the first comparison result CP1at a low voltage level, and the mode controller244does not control the processor240to enter the first operation mode.

In this embodiment, the driver245provides the control signal SC in the first operation mode to control the boost circuit220to cause the sensed value SV to be not less than the first reference value VR1. In some embodiments, the mode controller244may directly control the driver245to provide the control signal SC.

Other examples will be provided to describe the implementation details of the processor. With reference toFIG.7,FIG.7is another schematic circuit block diagram of a power converter according to an embodiment of the disclosure. In this embodiment, a power converter300includes a rectifier310, a boost circuit320, a current sensor330, and a processor340. The circuit configuration of the current sensor330may be sufficiently taught from the embodiment ofFIG.6, which will not be repeatedly described herein. The processor340includes an impedance sensor341, calculators342_1,342_2, comparators343_1,343_2, a mode controller344, and a driver345. For the implementation of the impedance sensor341, the calculator342_1, and the comparator343_1, reference may be made to the implementation of the impedance sensor241, the calculator242, and the comparator243of the embodiment ofFIG.6, which thus will not be repeatedly described herein.

In this embodiment, the calculator342_2receives the output voltage value v_VO, and based on Formula (2), multiplies the input impedance value RIN and the second value V2to produce the second product and divides the output voltage value v_VO by the second product to generate the second reference value VR2. In some embodiments, the calculator342_2may be implemented at least by a divider. The divider may divide the output voltage value v_VO by the input impedance value RIN and then by the second value V2to generate the second reference value VR2.

Further, the resistor R2may be set between the calculator342_2and a reference low voltage. The resistor R2may be configured to determine the voltage value corresponding to the second reference value VR2.

In this embodiment, the comparator343_2is coupled to the calculator342_2and the current sensor330. The comparator343_2compares the sensed value SV with the second reference value VR2to generate a second comparison result CP2. In this embodiment, a non-inverting input end of the comparator343_2is coupled to the current sensor330, an inverting input end of the comparator343_2is coupled to the calculator342_2, and an output end of the comparator343_2is coupled to the mode controller344. When the second comparison result CP2indicates that the sensed value SV is greater than the second reference value VR2, the comparator343_2outputs the second comparison result CP2at a high voltage level. When the second comparison result CP2indicates that the sensed value SV is less than or equal to the second reference value VR2, the comparator343_2outputs the second comparison result CP2at a low voltage level.

In this embodiment, the mode controller344receives the first comparison result CP1and the second comparison result CP2, and determines the operation mode according to Table 1.

TABLE 1FirstSecondOperationcomparison resultcomparison resultmodeHigh voltage levelHigh voltage levelFirst operation modeLow voltage levelHigh voltage levelSecond operation modeLow voltage levelLow voltage levelThird operation mode

In other words, when the first comparison result CP1indicates that the sensed value SV is greater than the first reference value VR1, the mode controller344controls the processor340to enter the first operation mode. When the first comparison result CP1indicates that the sensed value SV is less than or equal to the first reference value VR1and the second comparison result CP2indicates that the sensed value SV is greater than the second reference value VR2, the mode controller344controls the processor340to enter the second operation mode. When the second comparison result CP2indicates that the sensed value SV is less than or equal to the second reference value VR2, the mode controller344controls the processor340to enter the third operation mode.

In summary of the foregoing, the power converter generates the first reference value according to the output voltage value, the input impedance value, and the first value. Moreover, when the sensed value corresponding to the inductor current value is greater than the first reference value, the power converter enters the first operation mode to cause the sensed value to be not less than the first reference value. The fluctuation of the inductor current value can be reduced because of the limitation of the first reference value. Accordingly, the power converter can suppress noise of the power converter.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.