Patent ID: 12218101

DETAILED DESCRIPTION

Specific details of several embodiments of stacked semiconductor die packages and methods of manufacturing such die packages are described below. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. A semiconductor device can include, for example, a semiconductor substrate, wafer, or die that is singulated from a wafer or substrate. Throughout the disclosure, semiconductor dies are generally described in the context of semiconductor devices but are not limited thereto.

The term “semiconductor device package” can refer to an arrangement with one or more semiconductor devices incorporated into a common package. A semiconductor package can include a housing or casing that partially or completely encapsulates at least one semiconductor device. A semiconductor device package can also include an interposer substrate that carries one or more semiconductor devices and is attached to or otherwise incorporated into the casing. The term “semiconductor device package assembly” can refer to an assembly that includes multiple stacked semiconductor device packages. As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor device or package in view of the orientation shown in the Figures. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations.

FIG.1is a schematic cross-sectional view of a semiconductor device package assembly100in accordance with an embodiment of the present technology. As shown, the semiconductor device package assembly100includes a base substrate101and multiple semiconductor device packages103stacked on the base substrate101. Although the illustrated embodiment shows thirteen (13) separate, stacked semiconductor device packages103, it will be appreciated that the semiconductor device package assembly100can include any suitable number of stacked semiconductor device packages103in other embodiments.

In some embodiments, the base substrate101can include a base wafer having one or more semiconductor components (e.g., a die; not shown) therein. In some embodiments, the base substrate101can be a circuit board or other type of substrate commonly used in semiconductor device packages. As shown, the base substrate101has a first side1011(e.g., a front/active side) and a second side1013(e.g., a back/inactive side) opposite to the first side1011.

The base substrate101can include a passivation layer1015at the first side1011configured to protect the base substrate101. In some embodiments, the passivation layer1015can include an oxide layer, an inert layer (e.g., a layer that is less likely to chemically react with air or corrode), or other suitable protective layers. In some embodiments, the passivation layer1015can include a protective film. In some embodiments, the base substrate101can be further coupled to an interposer substrate by electric couplers such as solder bumps or solder balls.

As shown, the base substrate101includes multiple metallization layers105(or a first set of metallization layers) positioned therein and configured to electrically couple to the one or more semiconductor components (not shown) in the base substrate101. In the illustrated embodiments, the metallization layers105can include first, second, and third metallization layers105a,105b, and105c. In some embodiments, the first metallization layer105acan include aluminum, or other suitable metal or conductive materials. In some embodiments, the first metallization layer105acan be implemented as an aluminum pad. In some embodiments, the second metallization layer105bcan include copper or other suitable metal or conductive material. In some embodiments, the third metallization layer105ccan include copper or other suitable metal or conductive materials.

In the illustrated embodiments, the metallization layers105can be formed during a back-end-of-line (BEOL) manufacturing process. The first metallization layer105acan include a contacting area107configured to be in contact with the semiconductor device package103(e.g., electrically and physically), when the semiconductor device package103is stacked on the base substrate101.

In the illustrated embodiments shown inFIG.1, individual semiconductor device packages103have a first side1031(e.g., a front/active side) and a second side1033(e.g., a back/inactive side) opposite to the first side1031. As shown, the individual semiconductor device packages103also can include a passivation layer1035at the first side1031of the semiconductor device package103configured to protect the semiconductor device package103. In some embodiments, the passivation layer1035can include an oxide layer, an inert layer (e.g., a layer that is less likely to chemically react with air or corrode), or other suitable protective layers. In some embodiments, the passivation layer1035can include a protective film.

As shown, the individual semiconductor device packages103can also include a dielectric layer1037at the second side1033of the semiconductor device package103. In some embodiments, the dielectric layer1037can protect the semiconductor device package103. In some embodiments, the dielectric layer1037can be a dielectric film.

The individual semiconductor device packages103can also include one or more metallization layers109(or a second set of metallization layers) configured to electrically couple to one or more semiconductor components (e.g., a die; not shown) in the semiconductor device package103. In the illustrated embodiments, the metallization layers109can include aluminum, copper, or other suitable metal or conductive materials. In some embodiments, the metallization layer109can be formed during a BEOL manufacturing process. In some embodiments, the metallization layer109can include multiple metallization layers (similar to the first, second, and third metallization layers105a,105b, and105cdiscussed above).

The semiconductor device package assembly100further includes a metal bump111located at the first side1031of the individual semiconductor device package103. The metal bump111electrically couples to the metallization layer109and is configured to be in contact with the first metallization layer105aof the base substrate101(e.g., at the contacting area107). In some embodiments, the metal bump111can include an indium bump. In other embodiments, the metal bump111can include other suitable conductive materials.

The individual semiconductor device packages103have a recess113(or a “divot”) at the second side1033. The recess113is configured to enable the metallization layer109to be in contact with another semiconductor device package103via another metal bump115. By this arrangement, the present technology enables the base substrate101to electrically couple to the semiconductor device packages103without using a TSV.

In some embodiments, the semiconductor device package assembly100can be a memory device in which the semiconductor device packages103are memory dies (e.g., DRAM, LPDRAM, SRAM, Flash, etc.). In some embodiments, the base substrate101can be a logic device, processor, and/or another memory device.

FIGS.2A-2Jare schematic cross-sectional views of a method for manufacturing a semiconductor device package203in accordance with the present technology. Like reference numbers refer to like components throughoutFIGS.2A-2J. Referring toFIG.2A, the semiconductor device package203has a first side2031(e.g., a front/active side) and a second side2033(e.g., a back/inactive side) opposite to the first side2031. The semiconductor device package203can have a substrate2037and metallization layers205formed during the BEOL manufacturing process. The metallization layers205can include first, second, and third metallization layers205a,205b, and205cin the substrate2037. In some embodiments, the first metallization layer205acan include aluminum, or other suitable metal or conductive materials. In some embodiments, the first metallization layer205acan be implemented as an aluminum pad. In some embodiments, the second metallization layer205bcan include copper or other suitable metal or conductive material. In some embodiments, the third metallization layer205ccan include copper or other suitable metal or conductive materials.

In some embodiments, the semiconductor device package203can also have a barrier layer217between a portion of the metallization layers205and the substrate2037. In some embodiments, the barrier layer217is adjacent to the second metallization layer205b. In some embodiments, the barrier layer217can be made of a metal such as tantalum. In some embodiments, the second metallization layer205bcan include copper, and the barrier layer217made of tantalum can protect the second metallization layer205bfrom diffusion or corruption.

As shown inFIG.2A, the semiconductor device package203includes a passivation layer2035at the first side2031of the semiconductor device package203configured to protect the semiconductor device package203. In some embodiments, the passivation layer2035can include an oxide layer, an inert layer (e.g., a layer that is less likely to chemically react with air or corrode), or other suitable protective layers. In some embodiments, the passivation layer2035can include a protective film. The semiconductor device package203can also include a contacting area207on the first metallization layer205aat the first side2031.

Referring toFIG.2B, the semiconductor device package203can also include a metal bump211on the contacting area207. The metal bump211is electrically coupled to the metallization layer205and configured to be in electrical contact with a metallization layer of another semiconductor device package (see e.g.,FIG.1). In some embodiments, the metal bump211can include an indium bump. In other embodiments, the metal bump211can include other suitable conductive materials.

In some embodiments, the metal bump211can have a vertical dimension VD of approximately 10-20 μm. In some embodiments, the vertical dimension VD can be approximately 15 μm. In some embodiments, the metal bump211can be formed by an electroplating process. In some embodiments, the metal bump211can be formed by having a seed material in the contact area207of the first metallization layer205a. The seed material can facilitate forming the metal bump211on the first metallization layer205a. In some embodiments, the metal bump211can be formed by an inkjet process. In other embodiments, the metal bump211can be formed by other suitable methods. In some embodiments, the metal bump211can be cold annealed.

FIG.2Cshows the semiconductor device package203after it has been coupled to a carrier215via a bonding layer213. The carrier215is configured to hold and support the semiconductor device package203in the manufacturing process described below with reference toFIGS.2D-2J. In some embodiments, the carrier215can be a reusable carrier (e.g., a glass carrier). In some embodiments, the carrier215can be a non-reusable carrier (e.g., a silicon or plastic carrier). In some embodiments, the bonding layer213can be a release tape (e.g., gas-sensitive or temperature-sensitive). In such embodiments, in response to a particular type of laser or gas, the bonding layer213can dissolve and accordingly release the semiconductor device package203from the carrier215. Relevant embodiments are discussed below with reference toFIG.3A. In some embodiments, the bonding layer213can be an adhesive layer or other suitable bonding materials.

FIG.2Dillustrates the semiconductor device package203after the substrate2037has been thinned. Referring toFIG.2D, the semiconductor device package203can be thinned such that the depth D between a thinned surface219and the first side2031of the semiconductor device package203is approximately 10 μm (e.g., excluding the depth of the passivation layer2035). In some embodiments, the depth D can range from 5-30 μm. In some embodiments, the semiconductor device package203can be thinned that the depth D is not more than 30 μm, 25 μm, 20 μm, 15 μm, 10 μm or 5 μm.

By thinning the substrate2037to this extent, the metalation layers205of the semiconductor device package203can be accessed and electrically coupled to other metalation layers or semiconductor components of another semiconductor device package without using a TSV. Generally speaking, to form a TSV in a semiconductor structure, the smallest depth of the semiconductor structure that the semiconductor structure can be thinned is around 50 μm. Therefore, the improved method provided by the present technology is advantageous at least because it can manufacture and stack semiconductor device packages with smaller depths (or vertical dimensions) and without the processing steps to form TSVs. It is particularly beneficial for manufacturing compact semiconductor devices or packages.

FIG.2Eillustrates a process of forming a first photo-resistant layer221(or a first photo-pattern mask) on the second side2033(back/inactive side) of the semiconductor device package203. As shown, the first photo-resistant layer221is formed with multiple openings223(only three are shown inFIG.2E—first, second, and third openings223a,223b, and223c). As shown, the first and third openings223a,223care formed on opposite sides of the semiconductor device package203. The first and third openings223a,223ccan be used to separate or “singulate” the semiconductor device package203later in the process. The second opening223bis aligned with at least a portion of the metal layers205.

FIG.2Fshows the semiconductor device package203after openings226have been formed through the first and third openings223a,223cto expose the passivation layer2035. The openings226can be formed by etching the substrate2037of the semiconductor device package203. In the same process, a recess225(e.g., a divot225) can be formed in the substrate2037through the second opening223b(e.g., the second opening223bextends in the direction toward the first side2031of the semiconductor device package203). The recess225can be another opening that expose the barrier layer217. As shown, the divot225are formed with sloped sidewalls (at both left and right sides of the divot225, as shown inFIG.2F), which can facilitate coupling or positioning a metal bump of another semiconductor device package to the metallization layers205. The recess225can be formed in the same etching process as the openings226.

FIG.2Gshows the semiconductor device package203after the first photo-resistant layer221has been removed and a dielectric layer227has been formed on the second side2033of the semiconductor device package203. In some embodiments, the dielectric layer227can be formed by a chemical vapor deposition (CVD) process. In some embodiments, the dielectric layer227can be formed by using tetraethyl-orthosilicate (TEOS) in a CVD process. In some embodiments, the dielectric layer227can be formed by a spinning process. In some embodiments, the dielectric layer227can be a dielectric film.

As shown inFIGS.2H and2I, a second photo-resistant layer229(or a second photo-pattern mask) can be formed on the second side2033(back/inactive side) of the semiconductor device package203. As shown, the second photo-resistant layer229fills the first and third openings223a,223c. The second photo-resistant layer229is patterned and developed to form an opening231. In the embodiment shown inFIG.2H, the opening231is aligned with the metal layers205. InFIG.2I, the dielectric layer227and the barrier layer217within the opening231are removed to expose the third metallization layer205cthrough an opening2133. In some embodiments, the barrier layer217is not removed. Factors to consider whether to remove the barrier layer217include, for example, the types of materials used in the barrier layer217, the third metallization layer205c, and the metal bump211.

FIG.2Jshows the semiconductor package203after the second photo-resistant layer229has been removed. The recess225has a lateral dimension L1that is larger than the lateral dimension L2of the metal bump211. As such, a sidewall225aof the recess225and a sidewall portion227aof the dielectric layer227are spaced apart from a sidewall211aof the metal bump211. The semiconductor device package203shown inFIG.2Jis ready for stacking.

FIGS.3A and3Billustrate methods for stacking semiconductor device packages203in accordance with an embodiment of the present technology. As shown inFIG.3A, a semiconductor device package203is coupled to or picked up by a bond tip301. In some embodiments, the bond tip301can be a flip-chip tool or other suitable devices. The bond tip301is configured to temporarily hold the semiconductor device package203such that it can be stacked on the base substrate101.

FIG.3Bshows a stage after the bonding layer213has been removed by a laser or gas to detach the semiconductor device package203from the carrier215(FIG.3A). When stacking the semiconductor device package203on the base substrate101, the metal bump211is aligned with and coupled to the contacting area107of the base substrate101. As a result, the metal bump211is electrically coupled to the metallization layer105in the base substrate101. By this arrangement, the metallization layers205of the semiconductor device package203can electrically couple to the metallization layer105in the base substrate101without a TSV. This is advantageous because it eliminates the need to form deep vias in the substrate2037, lining the substrate2037with dielectric and/or barrier layers, and electroplating conductive material into the lined vias commonly performed when forming TSVs.

Also shown inFIG.3B, a die-attaching material303can be positioned between the semiconductor device package203and the base substrate101before stacking the semiconductor device package203on the base substrate101. The die-attaching material303can bond the semiconductor device package203to the base substrate101. In some embodiments, the die-attaching material303can include a polymer such as a B-stage polymer (e.g., an epoxy film that has been heat-cured). In some embodiments, the die-attaching material303can include a non-conductive film (NCF) or a non-conductive paste (NCP). In some embodiments, the die-attaching material303can be jet-dispensed or laminated onto the base substrate101.

FIGS.4A-4Dillustrate methods of processing multiple semiconductor device package assemblies401in accordance with an embodiment of the present technology. InFIG.4A, the multiple semiconductor device package assemblies401are carried by a temporary carrier403. Each of the multiple semiconductor device package assemblies401includes a base substrate (e.g., the base substrate101) and multiple semiconductor device packages (e.g., the semiconductor device packages103or203). As shown, the back sides of the semiconductor device packages of the multiple semiconductor device package assemblies401are coupled to the temporary carrier403. The multiple semiconductor device package assemblies401are spaced apart such that the multiple semiconductor device package assemblies401can later be separated during a singulation process.

FIG.4Bshows the assembly after the multiple semiconductor device package assemblies401have been covered by an encapsulant material405. In some embodiments, the encapsulant material405can include resin, plastic, silicon, oxide, polymer, or other suitable dielectric materials.

FIG.4Cshows the assembly after the temporary carrier403has been detached from the multiple semiconductor device package assemblies401. InFIG.4C, the multiple semiconductor device package assemblies401covered by the encapsulant material405are inverted compared toFIG.4B.

FIG.4Dshows the assembly after a polymer layer407has been formed on the multiple semiconductor device package assemblies401. The method can include forming a redistribution layer409using the polymer layer407. The redistribution layer409is electrically coupled to the metallization layers (e.g., the metallization layers105or205) in individual semiconductor device package assembly401. In some embodiments, the redistribution layer409can include copper or other suitable conductive material.

As shown inFIG.4D, multiple connectors411can be formed on and electrically coupled to the redistribution layer409. The connectors411are further electrically coupled to the metallization layers of the semiconductor device packages and the base substrates in the individual semiconductor device package assembly401. In some embodiments, the connectors411can be ball grid array (BGA) connectors. In some embodiments, the connectors411can include a solder ball, a pad, or other suitable connecting devices. The multiple semiconductor device package assemblies401can then be “singulated” or separated, by cutting through the encapsulant material405at the locations indicated by dashed lines shown inFIG.4D.

Any one of the semiconductor devices having the features described above with reference toFIGS.1-4Dcan be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is a system500shown schematically inFIG.5. The system500can include a processor501, a memory503(e.g., SRAM, DRAM, flash, and/or other memory devices), input/output devices505, and/or other subsystems or components507. The semiconductor assemblies, devices, and device packages described above with reference toFIGS.1-4Dcan be included in any of the elements shown inFIG.5. The resulting system500can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system500include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system500include lights, cameras, vehicles, etc. With regard to these and other examples, the system500can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system500can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media.

This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. In some cases, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. Although steps of methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the present technology may have been disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.

Throughout this disclosure, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Similarly, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. Reference herein to “one embodiment,” “some embodiment,” or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.

From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. The present technology is not limited except as by the appended claims.