Patent ID: 12250829

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Source/drain(s) may refer to a source or a drain, individually or collectively dependent upon the context.

In some embodiments, a memory cell has an access transistor, a plurality of data storage elements, and a plurality of select transistors corresponding to the plurality of data storage elements. A gate of the access transistor is electrically coupled to a word line. Each of the data storage elements and the corresponding select transistor are electrically coupled in series between a source/drain of the access transistor and a bit line. Gates of the select transistors are electrically coupled to corresponding select bit lines. In at least one embodiment, in a reset operation of a selected data storage element, the access transistor and the select transistor corresponding to the selected data storage element are turned ON, whereas the select transistors corresponding to other data storage elements are turned OFF. As a result, a high voltage for resetting the selected data storage element is prevented from affecting data stored in the other data storage elements. In other words, reset disturb is avoidable in some embodiments. This is an improvement over other approaches. Other advantages achievable in one or more embodiments include, but are not limited to, simple and efficient three-dimensional (3D) stack structure, compatibility with back-end-of-line (BEOL) processes, increased memory density.

FIG.1is a schematic block diagram of a memory device100, in accordance with some embodiments. A memory device is a type of an IC device. In at least one embodiment, a memory device is an individual IC device. In some embodiments, a memory device is included as a part of a larger IC device which comprises circuitry other than the memory device for other functionalities.

The memory device100comprises at least one memory cell MC, and a controller (also referred to as “control circuit”)102electrically coupled to the memory cell MC and configured to control operations of the memory cell MC. In the example configuration inFIG.1, the memory device100comprises a plurality of memory cells MC arranged in a plurality of columns and rows in a memory array104. The memory device100further comprises a plurality of word lines WL_0to WL_m extending along the rows, a plurality of source lines SL_0to SL_m extending along the rows, and a plurality of bit lines (also referred to as “data lines”) BL_0to BL_k extending along the columns of the memory cells MC. Each of the memory cells MC is electrically coupled to the controller102by at least one of the word lines, at least one of the source lines, and at least one of the bit lines. Examples of word lines include, but are not limited to, read word lines for transmitting addresses of the memory cells MC to be read from, write word lines for transmitting addresses of the memory cells MC to be written to, or the like. In at least one embodiment, a set of word lines is configured to perform as both read word lines and write word lines. Examples of bit lines include read bit lines for transmitting data read from the memory cells MC indicated by corresponding word lines, write bit lines for transmitting data to be written to the memory cells MC indicated by corresponding word lines, or the like. In at least one embodiment, a set of bit lines is configured to perform as both read bit lines and write bit lines. In one or more embodiments, each memory cell MC is electrically coupled to a pair of bit lines referred to as a bit line and a bit line bar. The word lines are commonly referred to herein as WL, the source lines are commonly referred to herein as SL, and the bit lines are commonly referred to herein as BL. Various numbers of word lines and/or bit lines and/or source lines in the memory device100are within the scope of various embodiments. In at least one embodiment, the source lines SL are arranged in the columns, rather than in the rows as shown inFIG.1. In at least one embodiment, the source lines SL are omitted.

In the example configuration inFIG.1, the controller102comprises a word line driver112, a source line driver114, a bit line driver116, and a sense amplifier (SA)118which are configured to perform one or more operations including, but not limited to, a read operation, a write operation (or programming operation), and a forming operation. Example write operations include but are not limited to, a set operation and a reset operation. In at least one embodiment, the controller102further includes one or more clock generators for providing clock signals for various components of the memory device100, one or more input/output (I/O) circuits for data exchange with external devices, and/or one or more controllers for controlling various operations in the memory device100. In at least one embodiment, the source line driver114is omitted.

The word line driver112is electrically coupled to the memory array104via the word lines WL. The word line driver112is configured to decode a row address of the memory cell MC selected to be accessed in an operation, such as a read operation or a write operation. The word line driver112is configured to supply a voltage to the selected word line WL corresponding to the decoded row address, and a different voltage to the other, unselected word lines WL. The source line driver114is electrically coupled to the memory array104via the source lines SL. The source line driver114is configured to supply a voltage to the selected source line SL corresponding to the selected memory cell MC, and a different voltage to the other, unselected source lines SL. The bit line driver116(also referred as “write driver”) is electrically coupled to the memory array104via the bit lines BL. The bit line driver116is configured to decode a column address of the memory cell MC selected to be accessed in an operation, such as a read operation or a write operation. The bit line driver116is configured to supply a voltage to the selected bit line BL corresponding to the decoded column address, and a different voltage to the other, unselected bit lines BL. In a write operation, the bit line driver116is configured to supply a write voltage (also referred to as “program voltage”) to the selected bit line BL. In a read operation, the bit line driver116is configured to supply a read voltage to the selected bit line BL. The SA118is coupled to the memory array104via the bit lines BL. In a read operation, the SA118is configured to sense data read from the accessed memory cell MC and retrieved through the corresponding bit lines BL.

In some embodiments described herein, the memory device100further comprises select bit lines through which the controller102is electrically coupled to the memory cells MC. For example, the select bit lines are coupled to the bit line driver116.

The described memory device configuration is an example, and other memory device configurations are within the scopes of various embodiments. In at least one embodiment, the memory device100is a non-volatile memory, and the memory cells MC are non-volatile memory cells. In at least one embodiment, the memory device100is a non-volatile, reprogrammable memory, and the memory cells MC are non-volatile, reprogrammable memory cells. Examples of memory types applicable to the memory device100include, but are not limited to, resistive random access memory (RRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), conductive bridging random access memory (CBRAM), or the like. Other types of memory are within the scopes of various embodiments. In some embodiments, each memory cell MC is configured to store multiple bits. In at least one embodiment, each memory cell MC is configured to store one bit.

FIG.2Ais a schematic circuit diagram of a memory cell200, in accordance with some embodiments. In at least one embodiment, the memory cell200corresponds to at least one of the memory cells MC in the memory device100.

The memory cell200comprises a first transistor TA, a plurality of data storage elements R1, R2, R3, and a plurality of second transistors T1, T2, T3corresponding to the plurality of data storage elements R1, R2, R3. In some embodiments, the first transistor TA is an access transistor, and the second transistors T1, T2, T3are select transistors.

The access transistor TA has a gate202, a first source/drain204, and a second source/drain206. The gate202of the access transistor TA is electrically coupled to a word line WL, and the second source/drain206is electrically coupled to a source line SL.

Each of the data storage elements R1, R2, R3and the corresponding select transistor T1, T2, T3are electrically coupled in series between the first source/drain204of the access transistor TA and a bit line BL. Specifically, each of the data storage elements R1, R2, R3comprises a first terminal211,221,231, and a second terminal212,222,232. The first terminal is also referred to herein as “first electrode” and the second terminal is also referred to herein as “second electrode.” Each of the select transistors T1, T2, T3comprises a gate213,223,233, a first source/drain214,224,234, and a second source/drain215,225,235. The first electrodes211,221,231of the data storage elements R1, R2, R3are electrically coupled correspondingly to the first source/drains214,224,234of the select transistors T1, T2, T3. The second electrodes212,222,232of the data storage elements R1, R2, R3are electrically coupled to the first source/drain204of the access transistor TA. The second source/drains215,225,235of the select transistors T1, T2, T3are electrically coupled to the bit line BL. The gates213,223,233of the select transistors T1, T2, T3are electrically coupled correspondingly to select bit lines BLT1, BLT2, BLT3.

The data storage elements R1, R2, R3and the corresponding select transistors T1, T2, T3together form a plurality of data storage circuits (not numbered inFIG.2A) coupled in parallel between the bit line BL and the first source/drain204of the access transistor TA. For example, the data storage element R1and the corresponding select transistor T1together form a first data storage circuit, the data storage element R2and the corresponding select transistor T2together form a second data storage circuit, and the data storage element R3and the corresponding select transistor T3together form a third data storage circuit.

In at least one embodiment, the word line WL corresponds to at least one of the word lines WL in the memory device100, the source line SL corresponds to at least one of the source lines SL in the memory device100, and the bit line BL corresponds to at least one of the bit lines BL in the memory device100. The select bit lines BLT1, BLT2, BLT3are electrically coupled to a controller, such as the controller102in the memory device100. In at least one embodiment, the source line SL is omitted, and the second source/drain206of the access transistor TA is coupled to a node of a predetermined voltage. Examples of a predetermined voltage include, but are not limited to, a ground voltage VSS, a positive power supply voltage VDD, or the like.

Examples of one or more of the access transistor TA and the select transistors T1, T2, T3include, but are not limited to, thin-film transistors (TFT), metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drains, nanosheet FETs, nanowire FETs, or the like. In the example configuration described with respect toFIG.2A, the access transistor TA and the select transistors T1, T2, T3are NMOS transistors. Other configurations including one or more PMOS transistors instead of one or more of the NMOS transistors are within the scopes of various embodiments.

An example configuration of the data storage elements R1, R2, R3in some embodiments described herein is an RRAM element, although other data storage or memory configurations are within the scopes of various embodiments. An RRAM element comprises a pair of electrodes, and a dielectric material sandwiched between the pair of electrodes. For example, in the data storage element R1, the pair of electrodes comprises the first electrode211and the second electrode212. The dielectric material is not shown inFIG.2A, and one or more examples of the dielectric material are described herein with respect toFIGS.4A-4B.

The dielectric material is configured to be electrically switchable between a first state corresponding to a first logic value stored in the data storage element, and a second state corresponding to a second logic value stored in the data storage element. In some embodiments, a forming operation is performed to activate the dielectric material, for example, by applying a forming voltage between the pair of electrodes. The forming voltage is applied across the dielectric material and causes at least one conductive filament to be formed in the dielectric material and electrically couple the pair of electrodes. As a result, the activated dielectric material has a low resistance.

Once at least one conductive filament has been formed by a forming operation, it is possible to break the at least one conductive filament, by applying a reset voltage between the pair of electrodes in a reset operation. As a result, the reset dielectric material has a high resistance.

It is further possible to reform at least one conductive filament in the reset dielectric material, by applying a set voltage between the pair of electrodes in a set operation. As a result, the set dielectric material again has a low resistance. The low resistance of the dielectric material corresponds to a first state, also referred to as a low R state, of the dielectric material. The high resistance of the dielectric material corresponds to a second state, also referred to as a high R state, of the dielectric material. The low R state and high R state of the dielectric material are also referred to herein as the low R state and high R state of the corresponding data storage element.

In a read operation, a read voltage is applied between the pair of electrodes. When the dielectric material is in the low R state, a high read current is caused by the read voltage and is detected, e.g., by a sense amplifier, such as the SA118. When the dielectric material is in the high R state, a low read current (or no read current) is caused by the read voltage and is detected, e.g., by the SA118. A detected high read current corresponds to the low R state of the dielectric material and a first logic value, e.g., logic “1,” stored in the data storage element. A detected low read current (or no read current) corresponds to the high R state of the dielectric material and a second logic value, e.g., logic “0,” stored in the data storage element.

In at least one embodiment, the forming operation is performed once for each data storage element in a memory device before a very first use of the memory device to store data. After the forming operation has been performed for a data storage element, one or more reset operations and/or one or more set operations are performed to switch the dielectric material of the data storage element between the low R state and the high R state to correspondingly switch the datum stored in the data storage element between logic “1” and logic “0.” The described structure, mechanism or configuration for switching the dielectric material of a data storage element between first and second states, i.e., by forming/setting at least one conductive filament and by braking the at least one conductive filament in the dielectric material is an example. Other structures, mechanisms or configurations for switching the dielectric material of a data storage element between different states corresponding to different logic values, are within the scopes of various embodiments.

In some situations, the reset voltage is a high voltage, although not as high as the forming voltage. In other approaches, such a high reset voltage applied to reset a selected data storage element potentially affects data stored in the other data storage elements, resulting in undesired reset disturb. A memory cell and/or a memory device in accordance with some embodiments make(s) it possible to avoid reset disturb as described herein.

FIG.2Bis a schematic circuit diagram of the memory cell200in a reset operation, in accordance with some embodiments. In some embodiments, one or more operations of the memory cell200, including the reset operation, are controlled by a controller, such as the controller102of the memory device100. For simplicity, reference numerals of various elements already described with respect toFIG.2Aare omitted inFIG.2B.

In the example configuration inFIG.2B, the data storage element R1currently stores logic “1” corresponding to the low R state, the data storage element R2currently stores logic “0” corresponding to the high R state, and the data storage element R3currently stores logic “1” corresponding to the low R state. The data storage element R1currently storing logic “1” is selected to be reset in the reset operation. The other data storage elements, i.e., the data storage element R2and the data storage element R3, are not selected in the reset operation.

In the reset operation of the selected data storage element R1, the controller (not shown inFIG.2B) is configured to turn ON the access transistor TA and the select transistor T1corresponding to the selected data storage element R1, and turn OFF the select transistors T2, T3corresponding to the non-selected data storage elements R2, R3. Specifically, the controller is configured to apply a turn-ON voltage VWLvia the word line WL to the gate of the access transistor TA to turn ON the access transistor TA, and apply a further turn-ON voltage VWTrvia the corresponding select bit line BLT1to the gate of the select transistor T1corresponding to the selected data storage element R1. The controller is further configured to apply a turn-OFF voltage via the corresponding select bit lines BLT2, BLT3to the gates of the other select transistors T2, T3corresponding to the non-selected data storage elements R2, R3. In the example configuration inFIG.2B, the turn-OFF voltage is a ground voltage schematically illustrated inFIG.2Bwith the label “GND.” While the access transistor TA and the select transistor T1corresponding to the selected data storage element R1are turned ON and the other select transistors T2, T3are turned OFF, the controller is further configured to apply a reset voltage VWto the bit line BL. In at least one embodiment, the controller is further configured to apply the ground voltage to the source line SL. In one or more embodiments, the source line SL is grounded independently of control by the controller.

While the access transistor TA and the select transistor T1are turned ON, the reset voltage VWon the bit line BL and the ground voltage on the source line SL cause a reset current Ireset to flow from the bit line BL, through the data storage element R1, to the ground at the source line SL. The resistance of the dielectric material in the data storage element R1, even in the low R state corresponding to logic “1,” is still much higher than resistances of conductive patterns and the turned ON transistors TA, T1that electrically couple the data storage element R1to the bit line BL and the source line SL. As a result, a substantial portion of the reset voltage VWis applied across the dielectric material of the data storage element R1, and resets the dielectric material of the data storage element R1from the low R state to the high R state. In other words, the datum stored in the data storage element R1is switched from logic “1” to logic “0.”

In the reset operation of the selected data storage element R1, because the select transistors T2, T3corresponding to the non-selected data storage elements R2, R3are turned OFF, there is no current path through the non-selected data storage elements R2, R3even if one or more of the non-selected data storage elements are in the low R state. For example, even though the non-selected data storage element R3is in the low R state, because the corresponding select transistor T3is turned OFF, there is no current path through the non-selected data storage element R3, as schematically illustrated at236inFIG.2B. As a result, data stored in the non-selected data storage elements R2, R3are not affected by the high reset voltage VWapplied to the bit line BL in the reset operation of the selected data storage element R1. In other words, reset disturb is avoidable in one or more embodiments. This is an improvements over other approaches in which reset disturb is a concern due to a potential current path through a non-selected data storage element in the low R state. In some embodiments, other advantages of the memory cell200and/or a memory device comprising the memory cell200include, but are not limited to, simple and efficient three-dimensional (3D) stack structure, compatibility with BEOL processes, increased memory density, as described herein. In some embodiments, set disturb is avoidable.

In some embodiments, one or more other operations of the memory cell200are performed in a similar manner to the described reset operation. For example, in a set operation of the selected data storage element R1, the controller is configured to turn ON the access transistor TA and the select transistor T1corresponding to the selected data storage element R1, turn OFF the select transistors T2, T3corresponding to the non-selected data storage elements R2, R3, and apply a set voltage to the bit line BL and the ground voltage to the source line SL. For another example, in a read operation of the selected data storage element R1, the controller is configured to turn ON the access transistor TA and the select transistor T1corresponding to the selected data storage element R1, turn OFF the select transistors T2, T3corresponding to the non-selected data storage elements R2, R3, and apply a read voltage to the bit line BL and the ground voltage to the source line SL. The read voltage is smaller than the reset voltage and the set voltage. In a forming operation, the controller is configured to turn ON the access transistor TA and one or more or all of the select transistors T1, T2, T3, and apply a forming voltage to the bit line BL and the ground voltage to the source line SL. The forming voltage is higher than the reset voltage and the set voltage.

The above described reset operation is performed under control of the controller in a unipolar mode, in which a polarity of the reset voltage is the same as a polarity of the forming voltage. In some embodiments, the controller is configured to perform a reset operation in a bipolar mode, in which the polarity of the reset voltage is opposite to the polarity of the forming voltage. For example, in a reset operation of the selected data storage element R1in the bipolar mode, the controller is configured to turn ON the access transistor TA and the select transistor T1corresponding to the selected data storage element R1, and turn OFF the select transistors T2, T3corresponding to the non-selected data storage elements R2, R3, similarly to the unipolar mode. However, the reset voltage in the bipolar mode is reversed in polarity compared to the unipolar mode. Specifically, the controller is configured to apply the reset voltage VWto the source line SL, and apply the ground voltage to the bit line BL. In at least one embodiment, reset disturb is avoidable in the bipolar mode.

In the example configuration inFIGS.2A-2B, there are three data storage elements R1, R2, R3and three corresponding select transistors T1, T2, T3in the memory cell200. The described numbers of data storage elements and corresponding select transistors in a memory cell are examples. Other configurations are within the scopes of various embodiments. For example, in at least one embodiment, a memory cell comprises, besides an access transistor, n data storage elements and n corresponding select transistors, where n is a natural number greater than one. In other words, the memory cell in one or more embodiments has a (n+1)-transistor-n-resistor configuration, also referred to herein as (n+1)TnR. The example configuration inFIGS.2A-2Bis a 4T3R configuration, where n is three. In some embodiments, the number n is selected based on one or more design considerations. An example design consideration is a device pitch of the access transistor, as described herein.

FIG.3is a schematic circuit diagram of a memory device300, in accordance with some embodiments. The memory device300comprises memory cells310,320which have the 4T3R configuration described with respect toFIGS.2A-2B. Other configurations in which the memory cells310,320have a (n+1)TnR configuration, where n is other than three, are within the scopes of various embodiments.

In the example configuration inFIG.3, the memory cell310comprises an access transistor TA1, a plurality of data storage elements R1_1, R1_2, R1_3, and a plurality of corresponding select transistors T1_1, T1_2, T1_3which are electrically coupled to a word line WL1, a bit line BL1, a source line SL and a plurality of select bit lines BLT1_1, BLT1_2, BLT1_3similarly to a manner in which the access transistor TA, the data storage elements R1, R2, R3, and the select transistors T1, T2, T3of the memory cell200are electrically coupled to the word line WL, the bit line BL, the source line SL and the select bit lines BLT1, BLT2, BLT3. The memory cell320comprises an access transistor TA2, a plurality of data storage elements R2_1, R2_2, R2_3, and a plurality of corresponding select transistors T2_1, T2_2, T2_3which are electrically coupled to a word line WL2, a bit line BL2, the source line SL and a plurality of select bit lines BLT2_1, BLT2_2, BLT2_3similarly to a manner in which the access transistor TA, the data storage elements R1, R2, R3, and the select transistors T1, T2, T3of the memory cell200are electrically coupled to the word line WL, the bit line BL, the source line SL and the select bit lines BLT1, BLT2, BLT3.

In the memory device300, the second source/drain of the access transistor TA1and the second source/drain of the access transistor TA2are electrically coupled to the common source line SL. In at least one embodiment, the second source/drain of the access transistor TA1is the second source/drain of the access transistor TA2. In other words, the access transistor TA1and the access transistor TA2share a common source/drain. In at least one embodiment, one or more advantages described herein are achievable in the memory device300.

FIG.4Ais a schematic cross-sectional view of an IC device400, in accordance with some embodiments.

The IC device400comprises a first region410and a second region420arranged side by side in a first direction, e.g., the X direction. The first region410is defined between a first border line424and a center line425. The second region420is defined between the center line425and a second border line426. A distance in the X direction between the first border line424and the center line425is equal to a distance in the X direction between the center line425and the second border line426, and is referred to herein and illustrated inFIG.4Aas a device pitch. In at least one embodiment, the first border line424and the second border line426correspond to border lines of a standard memory cell which is stored in a standard cell library and based on which the IC device400is manufactured. In one or more embodiments, the first border line424and the center line425correspond to border lines of one standard memory cell, and the center line425and the second border line426correspond to border lines of another standard memory cell. For example, the first region410corresponds to the memory cell310of the memory device300, and the second region420corresponds to the memory cell320of the memory device300. The first region410and the second region420are similarly configured. In at least one embodiment, the first region410and the second region420are symmetrical to each other across the center line425. A detailed description of features of the first region410is given herein, and a detailed description of similar features of the second region420is omitted, where appropriate, for simplicity.

The IC device400comprises a substrate430having thereon at least one access transistor. For example, the access transistor TA1is arranged over the substrate430in the first region410, and the access transistor TA2is arranged over the substrate430in the second region420. Each of the access transistor TA1and the access transistor TA2comprises a gate structure and source/drains. In some embodiments, the substrate430is a semiconductor substrate, and N-type and/or P-type dopants are added to the substrate430to form source/drains431,432,433arranged at a spacing from each other along the X direction. In the example configuration inFIG.4A, the access transistor TA1comprises the source/drains431,432, whereas the access transistor TA2comprises the source/drains432,433. In other words, the access transistor TA1and the select transistor T2share the common source/drain432. The center line425bisects a width of the common source/drain432in the X direction. The gate structure of the access transistor TA1comprises a stack of a gate dielectric434and a gate435. The gate structure of the access transistor TA2comprises a stack of a gate dielectric436and a gate437. Example materials of the gate dielectrics434,436include HfO2, ZrO2, or the like. Example materials of the gates435,437include polysilicon, metal, or the like. In the example configuration inFIG.4A, spacers (not numbered) are arranged on opposite sides of the gate structures of the access transistor TA1and the access transistor TA2.

The IC device400further comprises isolation structures438,439in the substrate430for isolating the access transistor TA1and the access transistor TA2from other, adjacent transistors or logic elements. The access transistor TA1and the access transistor TA2are arranged in the X direction between the isolation structures438,439. In one or more embodiments, the IC device400further comprises another instance of the first region410placed in abutment with the second region420along the second border line426, and the second border line426becomes a center line which bisects a width of a joined isolation structure comprising the isolation structure439of the second region420and an isolation structure (corresponding to the isolation structure438) of the further instance of the first region410. Similarly, in one or more embodiments, the IC device400further comprises another instance of the second region420placed in abutment with the first region410along the first border line424, and the first border line424becomes a center line which bisects a width of a joined isolation structure comprising the isolation structure438of the first region410and an isolation structure (corresponding to the isolation structure439) of the further instance of the second region420. In at least one embodiment, the device pitch is the distance in the X direction between the center line425of the common source/drain432and the center line426(or424) of a joined isolation structure.

The IC device400further comprises source/drain contact structures441,442,443correspondingly over and in electrical contact with the source/drains431,432,433. In at least one embodiment, the IC device400further comprises gate contact structures (not shown) correspondingly over and in electrical contact with the gates435,437.

The IC device400further comprises an interconnect structure450over the substrate430. The interconnect structure450comprise a plurality of metal layers and a plurality of via layers arranged alternatingly in a thickness direction, i.e., the Z direction, of the substrate430. Examples of metal layers in the interconnect structure450comprise an M0 layer, an M1 layer, or the like. Examples of via layers in the interconnect structure450comprise a V0 layer, a V1 layer, or the like. The M0 layer is the lowest metal layer in the interconnect structure450. The V0 layer is the lowest via layer in the interconnect structure450, and electrically couples the M0 layer and the M1 layer. The interconnect structure450further comprises various interlayer dielectric (ILD) layers in which the metal layers and via layers are embedded. The metal layers and via layers of the interconnect structure450are configured to electrically couple various elements or circuits of the IC device400with each other, and with external circuitry. In the example configuration inFIG.4A, the interconnect structure450comprises the source line SL electrically coupled to the source/drain432, a conductive pattern451electrically coupled to the source/drain431of the access transistor TA1, a conductive pattern452electrically coupled to the source/drain433of the access transistor TA2. In at least one embodiment, the interconnect structure450further comprises the word lines WL1, WL2(not shown inFIG.4A) electrically coupled correspondingly to the gates435,437. The interconnect structure450further comprises an ILD layer453over the conductive patterns451,452.

The IC device400further comprises at least one metal-insulator-metal (MIM) structure over the interconnect structure450. For example, an MIM structure461is arranged over the interconnect structure450in the first region410, and an MIM structure462is arranged over the interconnect structure450in the second region420. Each of the MIM structures461,462is arranged as a via structure (not numbered) extending through a multilayer structure (not numbered) comprising a plurality of electrode layers471,472,473and ILD layers474,475,476which are stacked alternatingly in the Z direction over the interconnect structure450. The via structure of the MIM structure461comprises a conductor477, and a dielectric layer478between the conductor477and the multilayer structure. The via structure of the MIM structures461,462is similarly configured. The MIM structure461is described in detail herein, with reference to an enlarged view of a region463of the MIM structure461schematically illustrated inFIG.4A. A corresponding region464of the MIM structure462is similarly configured. In at least one embodiment, the region464of the MIM structure462is a mirror image of the region463of the MIM structure461across the center line425. The IC device400further comprises an isolation structure465electrically isolating the MIM structures461,462from each other.

As best seen in the enlarged view of the region463, the MIM structure461comprises a plurality of data storage elements R1_1, R1_2, R1_3stacked on top each other in the thickness direction of the substrate430, i.e., in the Z direction. In other words, the data storage elements R1_1, R1_2, R1_3are arranged at different heights over the substrate430. Each of the data storage elements R1_1, R1_2, R1_3comprises a first electrode defined by one of the electrode layers471,472,473, a second electrode defined by the conductor477, and a dielectric material sandwiched between the first electrode and the second electrode. For example, the data storage element R1_1comprises a first electrode defined by the electrode layer471, a second electrode defined by the conductor477, and a dielectric material defined by a portion of the dielectric layer478sandwiched in the X direction between the electrode layer471and the conductor477. The data storage element R1_2comprises a first electrode defined by the electrode layer472, a second electrode defined by the conductor477, and a dielectric material defined by a portion of the dielectric layer478sandwiched in the X direction between the electrode layer472and the conductor477. The data storage element R1_3comprises a first electrode defined by the electrode layer473, a second electrode defined by the conductor477, and a dielectric material defined by a portion of the dielectric layer478sandwiched in the X direction between the electrode layer473and the conductor477. The dielectric layer478further comprises, in the Z direction, an intervening portion479between the data storage elements R1_1, R1_2, and an intervening portion480between the data storage elements R1_2, R1_3. The intervening portion479of the dielectric layer478is sandwiched in the X direction between the ILD layer475and the conductor477, and the intervening portion480of the dielectric layer478is sandwiched in the X direction between the ILD layer476and the conductor477. In a forming operation, reset operation or set operation, a corresponding forming voltage, reset voltage or set voltage is applied to switch the dielectric materials in the data storage elements R1_1, R1_2, R1_3between the low R state and the high R state as described herein. However, the intervening portions479,480of the dielectric layer478, being sandwiched between the ILD layers475,476and the conductor477, are not affected by the forming voltage, reset voltage or set voltage, and remain electrically insulating.

The conductor477, which defines the second electrodes of the data storage elements R1_1, R1_2, R1_3, extends in the Z direction through the ILD layer453to be electrically coupled to the conductive pattern451, and then to the source/drain431of the access transistor TAL A corresponding conductor in the MIM structure462extends in the Z direction through the ILD layer453to be electrically coupled to the conductive pattern452, and then to the source/drain433of the access transistor TA2.

Example materials of one or more of the electrode layers471,472,473defining the first electrodes (also referred to as top electrodes) of the data storage elements include, but are not limited to, Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, or the like. Example materials of the conductor477defining the second electrodes (also referred to as bottom electrodes) of the data storage elements include, but are not limited to, Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, or the like. Example materials of the dielectric layer478defining the dielectric material in the data storage elements include, but are not limited to, HfO2, Hf1-xZrxO2, ZrO2, TiO2, NiO, TaOx, Cu2O, Nb2O5, Al2O3, or the like.

The IC device400further comprises a plurality of select transistors over the data storage elements, and electrically coupled correspondingly to the data storage elements. For example, a dielectric layer484is arranged over the MIM structures461,462, a plurality of select transistors T1_1, T1_2, T1_3is arranged in the first region410over a top surface485of the dielectric layer484, and a plurality of select transistors T2_1, T2_2, T2_3is arranged in the second region420over the top surface485of the dielectric layer484. The select transistors T1_1, T1_2, T1_3, T2_1, T2_2, T2_3are schematically illustrated inFIG.4A. In the first region410, via structures481,482,483are formed in the dielectric layer484to electrically couple first source/drains of the select transistors T1_1, T1_2, T1_3correspondingly to the electrode layers471,472,473which correspondingly define the first electrodes of the data storage elements R1_1, R1_2, R1_3. Similar via structures (not numbered) are formed in the second region420.

In the example configuration inFIG.4A, to provide electrical contact with the corresponding via structures481,482,483, the electrode layers471,472,473, which are arranged at different levels or heights in the Z direction, are configured to form a stepwise structure. For example, the electrode layer471which is at the highest level among the electrode layers471,472,473has a smallest dimension in the X direction among the electrode layers471,472,473. The electrode layer472which is at a middle level has a middle dimension in the X direction. The electrode layer473which is at the lowest level among the electrode layers471,472,473has the greatest dimension in the X direction among the electrode layers471,472,473. The corresponding via structures481,482,483have different heights or depths in the Z direction. For example, among the via structures481,482,483, the via structure481has the smallest height, the via structure482has a middle height, and the via structure483has the greatest height. The second region420comprises a similar stepwise structure.

By way of the interconnect structure450and the via structures481,482,483, each of the data storage elements R1_1, R1_2, R1_3in the first region410is electrically coupled in series between the first source/drain431of the access transistor TA1and the first source/drain of a corresponding select transistor T1_1, T1_2, T1_3. In the second region420, the data storage elements in the MIM structure462are electrically coupled in series between the first source/drain433of the access transistor TA2and the first source/drain of a corresponding select transistor T2_1, T2_2, T2_3in a similar manner.

In some embodiments, the data storage elements, such as the data storage elements R1_1, R1_2, R1_3, are arranged in a simple and efficient 3D stack in the form of an MIM structure, such as the MIM structure461. In at least one embodiment, the chip area occupied by the MIM structure is not changed even when the number n of data storage elements included in the MIM structure is increased. As a result, it is possible to increase or improve the memory density of the IC device400over a given chip area, in accordance with some embodiments.

However, the number n of data storage elements in an MIM structure of a memory cell corresponds to the number n of select transistors in the memory cell. As the number n of data storage elements included in the MIM structure is increased, the number n of select transistors in the memory cell is also increased. In the example configuration inFIG.4A, all select transistors T1_1, T1_2, T1_3of the memory cell310are arranged in the first region410corresponding to the device pitch between the first border line424and the center line425. In at least one embodiment, this arrangement makes it possible to arrange various memory cells in abutment to form a memory array, such as the memory array104. To physically fit n select transistors in a region corresponding to the device pitch of the access transistor, dimensions of each select transistor and the device pitch of the access transistor are design considerations. Such design considerations define a maximum number of select transistors that can be fit over the region corresponding to the device pitch, i.e., the maximum number of data storage elements that can be included in the memory cell.

FIG.4Bis a schematic perspective view of the IC device400, in accordance with some embodiments. Compared toFIG.4A,FIG.4Billustrates the select transistors in more details, and also shows how various bit lines and select bit lines are coupled to the select transistors.

In the example configuration inFIG.4B, the select transistors T1_1, T1_2, T1_3, T2_1, T2_2, T2_3are arranged over the top surface485of the dielectric layer484. Each of the select transistors comprises a source/drain region extending in a second direction, e.g., the Y direction, transverse to the X direction. Each of the select transistors further comprises a gate extending over the source/drain region in the X direction.

FIG.4Cis an enlarged schematic perspective view of a select transistor T1_1of the IC device400inFIG.4B, in accordance with some embodiments. For simplicity, connections from the select transistor T1_1to the corresponding bit line BL1and select bit line BLT1_1are omitted inFIG.4C. As shown inFIG.4C, the select transistor T1_1comprises a source/drain region or active channel layer arranged over the top surface485, and extending in the Y direction. The source/drain region comprises a source S1and a drain D1. The select transistor T1_1further comprises a gate G1extending over the source/drain region in the X direction. A gate dielectric490is arranged between the source/drain region and the gate G1. The source S1is arranged over a top end (not shown) of the corresponding via structure481, and is electrically coupled to the via structure481. The drain D1is electrically coupled to the corresponding bit line BL1, and the gate G1is electrically coupled to the corresponding select bit line BLT1_1, as described herein.

Returning toFIG.4B, sources S2, S3of the select transistors T1_2, T1_3are arranged over top ends (not shown) of the corresponding via structures482,483, and are electrically coupled to the via structures482,483. The drains of the select transistors T1_1, T1_2, T1_3are electrically coupled to the bit line BL1by corresponding via structures491,492,493. The gates of the select transistors T1_1, T1_2, T1_3are electrically coupled to the corresponding select bit lines BLT1_1, BLT1_2, BLT1_3by corresponding via structures (not numbered). The select transistors T2_1, T2_2, T2_3are electrically coupled to the bit line BL2and the select bit lines BLT2_1, BLT2_2, BLT2_3in similar manners.

In the example configuration inFIG.4B, the bit lines BL1, BL2extend in the X direction, whereas the select bit lines BLT1_1, BLT1_2, BLT1_3, BLT2_1, BLT2_2, BLT2_3extend in the Y direction. In at least one embodiment, the bit lines BL1, BL2are in one metal layer, and the select bit lines BLT1_1, BLT1_2, BLT1_3, BLT2_1, BLT2_2, BLT2_3are in a different metal layer. The conductor477is elongated in the Y direction, i.e., the conductor477has a greater dimension in the Y direction than in the X direction. In other words, the via in which the conductor477is deposited has a shape of a trench elongated in the Y direction. This configuration of the conductor477is an example. Other configurations are within the scopes of various embodiments. In at least one embodiment, one or more advantages described herein are achievable in the IC device400.

FIG.4Dis a schematic cross-sectional view of an IC device400D in accordance with some embodiments. Corresponding elements in IC device400and IC device400D are designated by the same reference numerals. Compared to the IC device400where the MIM structures461,462are arranged in the X direction between the stepwise structure of the electrode layers471,472,473in the first region410and the corresponding stepwise structure in the second region420, the IC device400D comprises a reversed arrangement in which stepwise structures are arranged between MIM structures.

The IC device400D comprises a first region410D and a second region420D. The first region410D has a configuration corresponding to the configuration of the first region410, and the second region420D has a configuration corresponding to the configuration of the second region420. Contrary to the example configuration inFIG.4where the first region410is arranged on the left and the second region420is arranged on the right, in the example configuration inFIG.4D, the first region410D is arranged on the right and the second region420D is arranged on the left. As a result, the stepwise structure of the electrode layers471,472,473in the first region410D and the corresponding stepwise structure in the second region420D are arranged in the X direction between the MIM structures461,462. The IC device400D further comprises isolation structures465A,465B,465C. The isolation structure465B electrically isolates the electrode layer473in the first region410D from a corresponding electrode layer473′ in the second region420D. The isolation structures465A,465C electrically isolate the MIM structures461,462from other circuitry in the IC device400D. In at least one embodiment, one or more of the isolation structures465A,465C are omitted. In the first region410D, a first source line SL1is electrically coupled to the source/drain432of the access transistor TA1. In the second region420D, a second source line SL2is electrically coupled to the source/drain432′ of the access transistor TA2. In at least one embodiment, the first region410D and the second region420D are symmetrical to each other across the center line425. In at least one embodiment, one or more advantages described herein are achievable in the IC device400D.

FIG.4Eis a schematic cross-sectional view of an IC device400E in accordance with some embodiments. Corresponding elements in IC device400and IC device400E are designated by the same reference numerals. Compared to the IC device400where, in each of the first region410and the second region420, the select transistors T1_1, T1_2, T1_3are arranged on the same side of the MIM structure461in the X direction, the IC device400E comprises a reversed arrangement in which the select transistors are arranged on opposite sides of the corresponding MIM structure in the X direction.

The IC device400E comprises a first region410E. The first region410E has a configuration corresponding to the configuration of the first region410, except that the select transistors T1_1, T1_3are arranged on one side (e.g., on the left side) of the MIM structure461whereas the select transistor T1_2is arranged on the other side (e.g., on the right side) of the MIM structure461in the X direction. The described arrangement is an example configuration. In another example configuration (not shown), the select transistors T1_1, T1_2are arranged on one side of the MIM structure461whereas the select transistor T1_3is arranged on the other side of the MIM structure461in the X direction. In a further example configuration (not shown), the select transistor T1_1is arranged on one side of the MIM structure461whereas the select transistors T1_2, T1_3are arranged on the other side of the MIM structure461in the X direction. Other configurations are within the scopes of various embodiments. In some embodiments, the IC device400E further comprises a second region (not shown) which is symmetrical to the first region410E across the center line425. In one or more embodiments, the second region of the IC device400E is arranged on the right side of the first region410E in a manner to similar to the second region420arranged on the right side of the first region410inFIG.4A. In at least one embodiment, the second region of the IC device400E is arranged on the left side of the first region410E in a manner to similar to the second region420D arranged on the left side of the first region410D inFIG.4D. In at least one embodiment, one or more advantages described herein are achievable in the IC device400E.

FIG.5is a schematic perspective view of an IC device500, in accordance with some embodiments. Compared to the IC device400which comprises memory cells or regions410,420having the 4T3R configuration, the IC device500comprises memory cells or regions having the (n+1)TnR configuration, where n is greater than three.FIG.5is a schematic perspective view similar toFIG.4B. However, for simplicity, the n select transistors, the bit lines BL1, BL2, and the dielectric layer484are omitted fromFIG.5.

The IC device500comprises two memory cells510,520each comprising n select transistors (not shown) having gates electrically coupled to n select bit lines. For example, the n select bit lines electrically coupled to the memory cell510include select bit lines BLT1_1, BLT1_2, BLT1_3, . . . , BLT1_n. The n select bit lines electrically coupled to the memory cell520include select bit lines BLT2_1, BLT2_2, BLT2_3, . . . , BLT2_n. Each memory cell510,520includes n electrode layers. For example, the n electrode layers in the memory cell510include electrode layers471,472,473, . . . ,57n. The n electrode layers are arranged in a stepwise structure as illustrated inFIG.5. The n electrode layers, together with the conductor477and the dielectric layer478, define an MIM structure comprising n data storage elements (not shown), in a manner similar to the MIM structure461in the IC device400. In at least one embodiment, one or more advantages described herein are achievable in the IC device500.

FIGS.6A-6Hare schematic cross-sectional views andFIGS.6I-6Jare schematic perspective views of an IC device600being manufactured at various stages of a manufacturing process, in accordance with some embodiments. In at least one embodiment, the IC device600corresponds to one or more of the memory device300and/or IC device400described herein.

InFIG.6A, the manufacturing process starts from a substrate430. The substrate430comprises, in at least one embodiment, a silicon substrate. The substrate430comprises, in at least one embodiment, silicon germanium (SiGe), Gallium arsenic, or other suitable semiconductor materials.

At least one access transistor is formed over the substrate430in a front-end-of-line (FEOL) processing. For example, the access transistor TA1and the access transistor TA2are formed over the substrate430. Specifically, source/drain regions431,432,433are formed in or over the substrate430, as described herein. Gate dielectrics434,436are deposited over the substrate430. Example materials of the gate dielectrics include, but are not limited to, a high-k dielectric layer, an interfacial layer, and/or combinations thereof. In some embodiments, the gate dielectric is deposited over the substrate430by atomic layer deposition (ALD) or other suitable techniques. Gates435,437are deposited over the gate dielectric. Example materials of the gates include, but are not limited to, polysilicon, metal, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and/or other suitable conductive materials. In some embodiments, the gates are deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD or sputtering), plating, atomic layer deposition (ALD), and/or other suitable processes. Isolation structures438,439are formed in the substrate430, e.g., by etching corresponding areas of the substrate430and filling the etched areas with insulating material.

After the FEOL processing, a back-end-of-line (BEOL) processing is performed to form an interconnect structure450over the access transistors to electrically couple various elements or circuits of the IC device600with each other, and with external circuitry. In at least one embodiment, the interconnect structure450comprises sequentially overlying metal and via layers. The overlying metal layers and via layers correspondingly comprise metal layers M0, M1, or the like, and via layers V0, V1, or the like. In at least one embodiment, the interconnect structure450is manufactured sequentially layer by layer upward from the substrate430. In the example configuration inFIG.6A, the interconnect structure450comprises a source line SL. In some embodiments, the interconnect structure450comprises word lines (not shown). The interconnect structure450is formed to comprise conductive patterns451,452electrically coupled to the corresponding source/drains of the access transistors TA1, TA2, and an ILD layer453over the conductive patterns451,452. The ILD layer453is planarized. A resulting structure600A is obtained, as shown inFIG.6A.

InFIG.6B, electrode layers for forming first electrodes of data storage elements are deposited. For example, a plurality of electrode layers601,602,603and ILD layers (not numbered) are sequentially deposited over the interconnect structure450. Example materials of one or more of the electrode layers601,602,603include, but are not limited to, Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, or the like. A resulting structure600B is obtained, as shown inFIG.6B.

InFIG.6C, an isolation structure is formed to electrically isolate first electrodes of data storage elements in one memory cell from first electrodes of data storage elements in another memory cell. For example, a via is etched through the electrode layers601,602,603and ILD layers, and is filled with insulating material to form an isolation structure465. The isolation structure465divides each of the electrode layers601,602,603into two electrically isolated parts. For example, the electrode layer601is divided into electrode layer parts611,621, the electrode layer602is divided into electrode layer parts612,622, the electrode layer603is divided into electrode layer parts613,623. The electrode layer parts611,612,613corresponding to first electrodes of data storage elements in one memory cell corresponding to the access transistor TA1. The electrode layer parts621,622,623corresponding to first electrodes of data storage elements in another memory cell corresponding to the access transistor TA2. In the example configuration inFIG.6C, the isolation structure465extends into the interconnect structure450. Other configurations are within the scopes of various embodiments. A resulting structure600C is obtained, as shown inFIG.6B.

InFIG.6D, vias or trenches for data storage elements are formed. For example, a via631is formed, e.g., by etching, to extend through the electrode layer parts611,612,613, and a via632is formed to extend through the electrode layer parts621,622,623. Each via631,632has an inner wall and a bottom wall. For example, the via631comprises an inner wall633and a bottom wall634. The bottom wall634is located, in the Z direction, between the lowest electrode layer part613and the conductive pattern451of the interconnect structure450. The conductive pattern451is not yet exposed through the bottom wall634. The via632is formed in a similar manner. A resulting structure600D is obtained, as shown inFIG.6D.

InFIG.6E, a dielectric material for data storage elements is deposited. For example, a dielectric layer635is deposited over the resulting structure600D. The dielectric layer635is deposited over the inner wall and the bottom wall of each via631,632. Example materials of the dielectric layer635include, but are not limited to, HfO2, Hf1-xZrxO2, ZrO2, TiO2, NiO, TaOx, Cu2O, Nb2O5, Al2O3, or the like. A resulting structure600E is obtained, as shown inFIG.6E.

InFIG.6F, formation of second electrodes of data storage elements is performed. The deposited dielectric layer635is removed from a top surface (not numbered) of the resulting structure600E, leaving a portion of the dielectric layer635on the inner wall of each via631,632. For example, the dielectric layer478is the portion of the dielectric layer635left on the inner wall of the via631. In some embodiments, the removal of the dielectric layer635from the top surface of the resulting structure600E also removes the portion of the dielectric layer635on the bottom wall of each via631,632, and further exposes the underlying conductive pattern451,452. In one or more embodiments, a further etching process is performed to expose the conductive pattern451,452. Subsequently, a conductive material is filled into the vias631,632to from electrical contact with the exposed conductive patterns451,452. Example materials of the conductive material include, but are not limited to, Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, or the like. As a result, conductors, such as the conductor477, are obtained in the filled vias631,632. The conductor477comprise second electrodes of the data storage elements and are electrically coupled to the corresponding source/drain431of the corresponding access transistor TA1. A corresponding conductor (not numbered) is similarly formed in the via632. A resulting structure600F is obtained, as shown inFIG.6F.

InFIG.6G, the first electrodes of the data storage elements are patterned into a stepwise structure. For example, the electrode layer parts611,612,613are patterned, e.g., by etchings, to have different dimensions in the X direction, resulting in electrode layers471,472,473arranged in a stepwise structure. The electrode layers471,472,473define the first electrodes of the data storage elements. The electrode layer parts621,622,623are patterned in a similar manner. The formation of data storage elements is completed. In some embodiments, the obtained data storage elements are RRAM elements. A resulting structure600G is obtained, as shown inFIG.6G.

InFIG.6H, formation of vias electrically coupled to the first electrodes of the data storage elements is performed. For example, a dielectric layer484is deposited over the resulting structure600G. A via structure481is formed through the dielectric layer484and an ILD portion684of the ILD layer remaining over the electrode layer471, and via structures via482,483are formed in the dielectric layer484to be electrically coupled to the corresponding electrode layers471,472,473. In some embodiments, vias having different heights and corresponding to the via structures481,482,483are formed in multiple etching operations. For example, in a first etching operation, a first mask is used to etch through the dielectric layer484and the ILD portion684to the electrode layer471to obtain a first via. In a second etching operation, a second mask is used to etch the dielectric layer484to the electrode layer472to obtain a second via. In a third etching operation, a third mask is used to etch the dielectric layer484to the electrode layer473to obtain a third via. In at least one embodiment, the first through third vias having different heights are simultaneously formed in an etching operation. For example, an etch selectivity between a dielectric material of the dielectric layer484and the ILD portion684and a conductive material of the electrode layers471,472,473is high, making it possible to form the first through third vias by a highly selective etching operation. In at least one embodiment, the ILD portion684and the dielectric layer484are of the same material. As a result, it is possible to etch the first through third vias simultaneously with high-selectivity etching to stop the etching reliably on the electrode layers471,472,473, respectively. A conductive material is filled in the first through third vias to form the corresponding via structures481,482,483. A planarization process is performed, resulting in a top surface485of the dielectric layer484. The via structures via481,482,483have corresponding upper ends641,642,643exposed at the top surface485. A resulting structure600H is obtained, as shown inFIG.6H.

FIG.6Iis a schematic perspective view of the resulting structure600H. As illustrated inFIG.6I, the upper ends641,642,643of the via structures481,482,483are exposed at the top surface485of the dielectric layer484. For simplicity, the ILD portion684is omitted inFIGS.6I-6J.

InFIG.6J, select transistors over the exposed upper ends of the via structures. An active channel layer is deposited over the top surface485of the dielectric layer484, and patterned to form a first source/drain of a select transistor over and in electrical contact with the exposed upper end of a corresponding via structure. For example, the first source/drains S1, S2, S3of select transistors T1_1, T1_2, T1_3are formed over and in electrical contact with the exposed upper ends (641,642,643inFIG.6I) of the corresponding via structures481,482,483. In some embodiments, a conductive material is formed as contact structures over the exposed upper ends of the via structures481,482,483before depositing the active channel layer. In some embodiments, a doping process and/or an annealing process is/are performed on the active channel layer. Example channel materials of the active channel layer include, but are not limited to ZnO, IGZO, IWO, ITO, polysilicon, amorphous Si, or the like. A gate dielectric is formed over the active channel layer, and a gate electrode is formed over the gate dielectric, for example, as described with respect toFIG.4C. In at least one embodiment, the gate electrode is formed by a gate replacement process. Example materials of the gate dielectric include, but are not limited to, silicon oxide, silicon nitride, or a high-k dielectric material. Example high-k dielectric materials include, but are not limited to, HfO2, HfSiO, HfSiON, HfSiO, HfTaO, HfZrO, titanium oxide, aluminum oxide, and zirconium oxide. Example materials of the gate electrode include, but are not limited to metal and polysilicon. A resulting structure600J is obtained, as shown inFIG.6J.

In at least one embodiment, the select transistors are manufactured at a temperature not greater than 400° C. which is compatible with BEOL processes. This compatibility with BEOL processes is a further advantage obtainable by memory devices and/or IC devices in accordance with some embodiments.

After the formation of the select transistors, various ILD layers and metal layers are formed over the select transistors, to form select bit lines, bit lines and electrical connections from the select bit lines and bit lines to the corresponding select transistors. In some embodiments, a resulting structure corresponds to the IC device400shown inFIG.4B. In some embodiments, one or more further metal layers and/or via layers are formed over the resulting structure to complete the IC device600. The described manufacturing process in an example. Other manufacturing processes are within the scopes of various embodiments. In at least one embodiment, one or more advantages described herein are achievable in an IC device and/or memory device manufactured in accordance with the described manufacturing process.

FIG.7is a flow chart of a method700of manufacturing an IC device, in accordance with some embodiments. In at least one embodiment, the IC device is manufactured in accordance with the manufacturing method700corresponds to one or more of the memory devices and/or IC devices described herein.

At operation705, an access transistor is formed over a substrate. For example, an access transistor TA1is formed over a substrate430, as described with respect toFIG.6A.

At operation715, an interconnect structure is formed over the substrate. For example, an interconnect structure450is formed over the substrate430, as described with respect toFIG.6A.

At operation725, a plurality of resistive random access memory (RRAM) elements is formed over the interconnect structure450. The interconnect structure450electrically couples a first electrode of each of the RRAM elements to a first source/drain of the access transistor. For example, as described with respect toFIG.4A, data storage elements R1_1, R1_2, R1_3, which are RRAM elements in at least one embodiment, are formed in a MIM structure461. A conductive pattern451in the interconnect structure450electrically couples an electrode, i.e., conductor477, of each of the data storage elements R1_1, R1_2, R1_3to a first source/drain431of the access transistor TA1. Example processes for manufacturing data storage elements R1_1, R1_2, R1_3are described with respect toFIGS.6B-6G.

At operation735, a plurality select transistors are formed as select transistors over the RRAM elements. A second electrode of each of the RRAM elements is electrically coupled to a first source/drain of a corresponding select transistor. For example, select transistors T1_1, T1_2, T1_3are formed over the data storage elements R1_1, R1_2, R1_3, as described with respect toFIG.4A. Further electrodes471,472,473of the data storage elements R1_1, R1_2, R1_3are electrically coupled to first source/drains Si, S2, S3of the corresponding select transistors T1_1, T1_2, T1_3, as described with respect toFIG.4B. Example processes for manufacturing the select transistors T1_1, T1_2, T1_3are described with respect toFIG.6J.

At operation745, a plurality bit line and select bit lines are formed over and coupled to the select transistors. For example, as described with respect toFIG.4B, a bit line BL1is formed over the select transistors T1_1, T1_2, T1_3, and is electrically coupled to second source/drains of the select transistors T1_1, T1_2, T1_3by via structures491,492,493. Select bit lines BLT1_1, BLT1_2, BLT1_3are also formed over the select transistors T1_1, T1_2, T1_3, and are electrically coupled to gates of the select transistors T1_1, T1_2, T1_3. In some embodiments, a word line WL1and a source line SL are formed in the interconnect structure450and coupled to the access transistor TA1, as described with respect toFIG.4Aand/orFIG.6A. As a result, the access transistor TA1, the data storage elements R1_1, R1_2, R1_3and the select transistors T1_1, T1_2, T1_3are electrically coupled to each other, to form a memory circuit corresponding to the memory cell310described with respect toFIG.3.

In some embodiments, one or more memory cells, memory devices, IC devices, and methods described are applicable to various types of transistor or device technologies including, but not limited to, planar transistor technology, FINFET technology, nanosheet FET technology, nanowire FET technology, or the like. One or more memory cells, memory devices, IC devices, and methods in accordance with some embodiments are also compatible with various technology nodes.

The described methods include example operations, but they are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiments of the disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art after reviewing this disclosure.

In some embodiments, a memory device comprises at least one bit line, at least one word line, at least one memory cell, at least one source line, and a controller electrically coupled to the at least one memory cell via the at least one word line, the at least one bit line, and the at least one source line. The memory cell comprises a first transistor, a plurality of data storage elements, and a plurality of second transistors corresponding to the plurality of data storage elements. The first transistor comprises a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each data storage element among the plurality of data storage elements and the corresponding second transistor are electrically coupled in series with the first source/drain of the first transistor and the bit line. The controller is configured to controllably apply a voltage other than a ground voltage to the at least one source line in an operation of a selected data storage element among the plurality of data storage elements

In some embodiments, an integrated circuit (IC) device comprises a substrate having thereon a first transistor, a plurality of data storage elements arranged at different heights over the substrate, a plurality of second transistors over the plurality of data storage elements, a word line coupled to a gate of the first transistor, and a plurality of select bit lines each electrically coupled to a gate of a corresponding second transistor among the plurality of second transistors. Each data storage element among the plurality of data storage elements is electrically coupled in series with a first source/drain of the first transistor and a first source/drain of a corresponding second transistor among the plurality of second transistors.

In some embodiments, an integrated circuit (IC) device comprises a substrate, and a plurality of data storage elements over the substrate, the plurality of data storage elements arranged at different heights along a thickness direction of the substrate. Each data storage element among the plurality of data storage elements comprises first and second electrodes, and a dielectric material sandwiched between the first and second electrodes of said data storage element in a direction transverse to the thickness direction of the substrate

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.