Patent ID: 12256547

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention improves endurance in a storage transistor to exceed 1011program-erase cycles using a device structure that ensures electrons tunneling out of a charge-trapping layer into the channel region of the storage transistor (e.g., during an erase operation) are within a desirable low energy range (“cool electrons”), such that any resulting hole generations are also low-energy and are thus less damaging to the programming window. The device structure provides a substantial direct tunneling programming current density exceeding 1.0 amps/cm2(e.g., 5.0 amps/cm2). The present invention is particularly advantageous for use in storage layers of thin-film storage transistors that are formed in 3-dimensional memory structures, such as those quasi-volatile storage transistors in the 3-dimensional arrays of NOR memory strings disclosed in the '015 Publication discussed above.

One embodiment of the present invention is illustrated by the model ofFIG.5, showing the conduction and valence energy band boundaries511and512of an exemplary storage transistor having channel region501, tunnel dielectric layer502and charge-trapping layer503. AsFIG.5illustrates, arrow514represents electrons direct tunnel from charge-trapping layer503to channel region501. The energy difference (“conduction band offset”) between the lowest energy levels in the conduction bands of charge-trapping layer503and channel region501—indicated by reference numeral515—is the expected energy loss by an electron so tunneled.

The present invention may be achieved by judiciously selecting a combination of materials for a tunnel dielectric material and a charge-trapping dielectric material, to obtain desirable conduction band offsets at these layers relative to the semiconductor substrate (i.e., the channel region) of the storage transistor.FIG.6(a)shows the lowest energy levels of the conduction bands at substrate501, tunnel dielectric502and charge-trapping layer503of the storage transistor.FIG.6(b)shows the lowest energy levels in the conduction bands of these layers of the storage transistor without application of a voltage.FIG.6(c)shows the electron energy offset515between substrate501and charge-trapping layer503, when an erase voltage is applied. Electron energy offset515depends on conduction band offsets between substrate501and each of tunnel dielectric layer502and charge-trapping layer503, as well as on the voltage applied for the erase operation. As illustrated inFIG.6(c), for tunnel dielectric layer502, using different charge-trapping materials as charge-trapping layer503, with different conduction band offsets relative to the substrate layer501, results in greater or lesser energy loss in the tunneling electrons reaching substrate501. Likewise, for charge-trapping layer503, using different tunnel dielectric materials as tunnel dielectric layer502, with different conduction band offsets relative to the substrate layer501, also results in greater or lesser energy loss in the tunneling electrons reaching substrate501.

Tunnel dielectric layer502may be as thin as 5.0-4.0 Å and may be formed out of silicon oxide (e.g., SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a combination of these materials. A silicon oxide tunnel dielectric layer may be formed using conventional oxidation techniques (e.g., a high-temperature oxidation), chemical synthesis (e.g., atomic layer deposition (ALD)), or any suitable combination of these techniques. A reactive O2process may include an ozone step (e.g., using pulsed ozone) for a precisely controlled thickness and an improved oxide quality (e.g., reduced leakage due to defect sites). The ozone step augments solidification of the oxide in a conformal manner, which is particularly advantageous for three-dimensional transistor structures. An annealing step (e.g., an H2anneal, a NH3anneal, or a rapid thermal annealing) may also fortify tunnel dielectric layer502. A silicon nitride tunnel dielectric layer may be formed using conventional nitridation, direct synthesis, chemical synthesis (e.g., by ALD), or any suitable combination of these techniques. A plasma process may be used for a precisely controlled thickness and an improved dielectric quality (e.g., reduced leakage due to defect sites).

Tunnel dielectric layer502may also include an additional thin aluminum oxide (Al2O3) layer (e.g., 10 Å or less). This additional aluminum oxide layer in the tunnel dielectric layer may be synthesized in the amorphous phase, to reduce leakage due to defect sites.

The following materials may be used to provide tunnel dielectric layer502and charge-trapping layer503:

MaterialConduction Band OffsetSilicon oxide (SiO2)3.15eVHafnium oxide (HfO2)1.5eVSilicon Nitride (Si3N4)2.4eVYttrium oxide (Y2O3)2.3eVZirconium oxide (ZrO2)1.4eVZirconium silicon oxide (ZrSiO4)1.5eVLanthanum oxide (La2O3)2.3eVSilicon oxinitrides (SiN:H)1.3-2.4eVTantalum oxide (Ta2O5)0.3eVCerium oxide (CeO2)0.6eVTitanium oxide (TiO2)0.0eVStrontium titanium oxide (SrTiO3)0.0eVSilicon-rich silicon nitride (SiN:Si)1.35eVSilicon nanodots0.0eVRuthenium nanodots−0.7eVCobalt nanodots−1.0eV

Using a lower conduction band offset in the charge-trapping layer provides an effective increase in tunneling barrier in the tunnel dielectric layer, resulting in improved data retention.

Alternatively, a barrier material of low conduction band offset may be introduced into the storage transistor between the tunnel dielectric layer and the charge-trapping layer.FIGS.7(a)-7(c)are band diagrams representative of such a structure.FIG.7(a)shows the relative conduction band offsets at substrate601, tunnel dielectric602, low conduction band offset barrier dielectric603and charge-trapping layer604of the storage transistor.FIG.7(b)is an energy band diagram of these layers of the storage transistor without application of a voltage.FIG.7(c)shows the electron energy offset615between substrate601and charge-trapping layer604, when an erase voltage is applied. Electron energy offset615depends on conduction band offsets between substrate601and each of tunnel dielectric layer602, low conduction band offset barrier layer603and charge-trapping layer604, as well as on the voltage applied for the erase operation. As shown inFIGS.7(a)-7(c), low conduction band offset (LCBO) barrier dielectric603preferably has a conduction band offset relative to substrate601that is lower than those of both tunnel dielectric layer602and charge-trapping layer604. Judiciously choosing the materials for tunnel dielectric layer602, LCBO barrier layer603, and trapping layer604, cool electron direct tunneling may be achieved for both program and erase operations, resulting in a high endurance in the storage transistor.

FIGS.8(a)-(c)illustrate the conduction band offset parameters for dielectric layers602-604illustrated inFIGS.7(a)-7(c). As shown inFIG.8(a), (i) parameter B represents the conduction band offset of tunnel dielectric layer602relative to substrate601, (ii) parameter a represents the conduction band offset of LCBO barrier layer603relative to the conduction band offset of tunnel dielectric layer602, (iii) parameter d represents the conduction band offset of LCBO barrier layer603relative to substrate601, and (iv) parameter c represents the conduction band offset of charge-trapping layer604relative to substrate601. According to one embodiment of the present invention, the conduction band offset of LCBO barrier layer603should not be greater than the conduction band offset of charge-trapping layer604(i.e., d≤c) to allow a substantial direct tunneling programming current density exceeding 1.0 amps/cm2(e.g., 5.0 amps/cm2).

FIG.8(b)shows sloping of the energy level at the bottom of the conduction band of tunnel dielectric layer602as a result of the programming voltage. The sloping lowers the energy level of tunnel dielectric layer602by parameter b over the thickness of tunnel dielectric layer602. For the programming operation to be effectuated by direct tunneling, the value of parameter b should be greater or equal to the value of parameter c (i.e., b≥c). The value of parameter b (in eV units) is the product of the voltage drop across tunnel dielectric layer602and the electron charge q (i.e., 1.6×10−19coulombs).

When the voltage drop across tunnel dielectric602is less than the conduction band offset of charge-trapping layer604(i.e., b′c), the tunneling barrier becomes wider, as at least a part of LCBO barrier layer603remains a tunneling barrier. In that case, direct tunneling may give way to a modified Fowler-Nordheim (MFN) mechanism, which provides a much smaller current than direct tunneling (e.g., less than 0.1 amps/cm2).

FIG.9(a)illustrates direct tunneling, under application of a programming voltage, andFIGS.9(b) and9(c)illustrate MFN tunneling, under a lower voltage (“intermediate”) and an even lower voltage, respectively, in the storage transistor ofFIGS.7(a)-7(c). One may recognize that MFN tunneling may occur in a region of low voltage disturbs during operations of the storage transistor. However, for a storage transistor having the structure illustrated inFIGS.7(a)-7(c), this MFN tunneling current can be very low for a range of voltages applied. The materials and the thicknesses for charge-trapping layer604and barrier layer603are selected such that read disturb voltages, programming inhibit voltages or erase inhibit voltages fall within the range of low or intermediate voltages that restrict tunneling to the MFN mechanism.

Thus, the storage transistor of the present invention provides an important advantage: high currents at the programming voltage due to direct tunneling, while having merely a low MFN tunneling current when exposed to a low voltage. This characteristic reduces disturbs during read, programming inhibit, or erase inhibit operations and improves data retention and endurance, particularly in quasi-volatile storage transistors of the present invention that use direct tunneling for fast programming and fast erase operations. In this regard, LCBO barrier layer603improves endurance by enabling cool electron-erase operations, which reduces device degradation, as the resulting holes generated in the channel region are low-energy.

By restricting tunneling at low voltages to MFN tunneling, LCBO barrier layer603also improve data retention and reduces read disturb, programming-inhibit disturbs and erase-inhibit disturbs, as the read disturbs, programming-inhibit disturbs and erase-inhibit disturbs all occur at low voltages. For example, programming-inhibit disturbs and erase-inhibit disturbs occur at half-select or a lower voltage than that used in the respective programming and erase operations. All these benefits accrue in the storage transistors biased at low voltages, while at the same time maintaining the advantages of the high efficiency of direct tunneling accrue in the storage transistors biased at the higher read, programming or erase voltages.

FIG.8(c)shows sloping of the energy level at the bottom of the conduction band of tunnel dielectric layer602during an erase operation. The sloping raises the energy level of tunnel dielectric layer602by parameter b′ over the thickness of tunnel dielectric layer602. During the erase operation, electrons in direct tunneling from charge-trapping layer604to substrate601loses an energy represented by parameter A, which is given by: A=b′+c. Note that the conduction band offset of charge-trapping layer604should be greater than the amount by which the energy level of a charge-trapping site is below the conduction band of charge-trapping layer604in order for the electrons at the charge-trapping site to be included in the direct tunneling current.

According to one embodiment of the present invention, substrate601may be implemented by a P-doped silicon, tunnel dielectric layer602may be implemented by a 1-nm thick SiO2layer (B=3.15 eV), low conduction band offset barrier layer603may be implemented by a 2-nm thick Ta2O5layer (d=0.3 eV), charge-trapping layer604may be implemented by a 4-nm thick silicon-rich silicon nitride (i.e., SiN:Si; c=1.35 eV), and another 4-nm thick SiO2layer may be used to provide a blocking dielectric layer. Unlike silicon nitride (stoichiometrically, Si3N4), silicon-rich silicon nitride includes silicon as impurity, which reduces silicon nitride's band gap from 4.6 eV to about 3.6 eV for silicon-rich silicon nitride. Also, silicon nitride has a refractive index of 2.0, while silicon-rich silicon nitride has a refractive index in the range of 2.1-2.3. Gate electrode606may be implemented by a highly-doped P-type polysilicon.FIGS.10(a) and10(b)are band diagrams for the structure during programming and erase operations, based on a one-volt drop across tunnel dielectric layer602(i.e., b=1 eV, during a programming operation and b′=1 eV, during an erase operation). As shown inFIG.10(b), as indicated by arrow1001, an electron reaching substrate601by direct tunneling loses about 1.4 eV of energy during the erase operation. Scattering in LCBO barrier layer603, as indicated by arrow1002, may further reduce this energy loss.

According to another embodiment of the present invention, substrate601may be implemented by a P-doped silicon, tunnel dielectric layer602may be implemented by a 1-nm thick SiO2layer (B=3.15 eV), low conduction band offset barrier layer603may be implemented by a 2-nm thick CeO2layer (d=0.6 eV), charge-trapping layer604may be implemented by a 4-nm thick silicon-rich silicon nitride (i.e., Si3Nr4:Si; c=1.35 eV), and another 5-nm thick SiO2layer may be used to provide a blocking dielectric layer (e.g., blocking dielectric layer605). Gate electrode606may be implemented by a highly-doped P-type polysilicon.

FIG.11(a)-11(d)show various simulation results for storage transistors of the present invention.

FIG.11(a)shows a simulation of a storage transistor having a 0.8 nm thick silicon oxide tunneling dielectric layer, a2.0 nm thick zirconium oxide LCBO barrier layer and a 5.0 nm thick silicon-rich silicon nitride trapping layer.FIG.11(a)shows that a direct-tunneling current density exceeding 1.0 amps/cm2is achieved with a programming voltage around 3.1 volts.

FIG.11(b)shows a simulation of a storage transistor having a 1.0 nm thick silicon oxide tunneling dielectric layer, a 2.0 nm thick cerium oxide LCBO barrier layer and a 4.0 nm thick silicon-rich silicon nitride trapping layer.FIG.11(b)shows that a direct-tunneling current density exceeding 1.0 amps/cm2is achieved with a programming voltage around 1.6 volts.

FIG.11(c)shows a simulation of a storage transistor having a 1.0 nm thick silicon oxide tunneling dielectric layer, a 2.0 nm thick tantalum oxide LCBO barrier layer and a 4.0 nm thick silicon-rich silicon nitride trapping layer.FIG.11(c)shows that a direct-tunneling current density exceeding 1.0 amps/cm2is achieved with a programming voltage around 1.8 volts.

FIG.11(d)shows a simulation of a storage transistor having a 1.0 nm thick silicon nitride tunneling dielectric layer, a 2.0 nm thick cerium oxide LCBO barrier layer and a 4.0 nm thick silicon-rich silicon nitride trapping layer.FIG.11(d)shows that a direct-tunneling current density exceeding 1.0 amps/cm2is achieved with a programming voltage around 2.1 volts.

FIG.12(a)illustrates a “reverse injection electrons” phenomenon that may occur during an erase operation. The reverse injection electrons may affect endurance adversely.FIG.12(a)is an energy band diagram for the conduction band of a gate stack in a storage transistor during an erase operation. As shown inFIG.12(a), the gate stack includes substrate601, tunnel dielectric602, LCBO barrier dielectric603, charge-trapping layer604, blocking dielectric layer605and gate electrode606. (Blocking dielectric layer605may be, for example, silicon oxide (SiO2)). During an erase operation, the relatively high electric field across blocking dielectric layer605may cause high-energy electrons—indicated inFIG.12(a)by arrow1201—to tunnel from the gate electrode into charge-trapping layer604, or even into tunnel dielectric layer602. These reverse injection electrons may damage these layers, adversely affecting the storage transistor's endurance.

According to one embodiment of the present invention, reverse injection electrons may be significantly reduced or substantially eliminating by including a layer of material with a high dielectric constant (“high-k material”), such as aluminum oxide (Al2O3) in the blocking dielectric layer (e.g., blocking dielectric layer605ofFIG.10(a)). In that embodiment, a high work function metal (e.g., greater than 3.8 eV, preferably not less than 4.0 eV) may be used for gate electrode. A high-k material of tHprovides an equivalent oxide thickness tEOTgiven by:

tEOT=tH×κoxκH
where Koxand KHare the relative dielectric constants of silicon oxide and the high-k material, respectively. Thus, a high-k material can provide the same desirable transistor characteristics (e.g., gate capacitance) at a thickness of tH, without incurring undesirable leakage of its silicon oxide layer counterpart at the much thinner equivalent thickness tEOT.

FIG.12(b)is an energy band diagram for the conduction band of a gate stack in a storage transistor during an erase operation, the storage transistor having additional aluminum oxide layer607in blocking dielectric layer610, according to one embodiment of the present invention. InFIG.12(b), blocking dielectric layer610includes aluminum oxide layer607and silicon oxide layer608. In one implementation, blocking dielectric layer610has an equivalent oxide thickness that is substantially the same as blocking layer dielectric605ofFIG.12(a). However, as aluminum oxide has a relative dielectric constant of 9.0, while silicon oxide's relative dielectric constant is 3.9, the actual combined physical thickness of aluminum oxide607and silicon oxide608inFIG.12(b)is greater than the thickness of blocking dielectric layer605ofFIG.12(a). Because high-k dielectric layer607has a greater relative dielectric constant than silicon oxide layer608, the electric field is lower in high-k dielectric layer607than in silicon oxide layer608. The greater combined physical thickness of blocking dielectric layer610ofFIG.12(b)—which provides a wider tunneling barrier between gate electrode606and charge-trapping layer604—and a lower electric field at the interface between gate electrode606and high-k material607reduce or eliminate reverse injection electrons, thereby resulting in an improved endurance. With high-k electric layer607(e.g., aluminum oxide), a high work function metal is preferred for gate electrode606. The high work function metal creates a high barrier (indicated by barrier height1202inFIG.12(b)) at the gate electrode-aluminum oxide interface, which significantly reduces reverse electron injection the erase operation. Suitable high work function metals include: tungsten (NV), tantalum nitride (TaN), tantalum silicon nitride (TaSiN).

According to another embodiment of the present invention,FIG.13is a cross-sectional view of thin-film storage transistor1300in a NOR memory string. As shown inFIG.13, storage transistor1300includes drain region1360, channel region1350, source region1330, gate dielectric layer1340and gate electrode1320. In one embodiment, drain region1360and source region1330may be relatively heavily-doped n+semiconductor films (e.g., polysilicon), while channel region1350may be a relatively lightly-doped p−semiconductor film (e.g., polysilicon). Storage transistor1300may be part of a NOR memory string that extends along a direction orthogonal to the cross section. The storage transistors in the NOR memory string share in common drain region1360and source region1330. InFIG.13, channel region1350is provided on opposite sides of oxide layer1365. In one embodiment, the materials of drain region1360, oxide layer1365and source region1330are successively deposited as thin-films, one atop another, above a planar surface of semiconductor substrate1380. The material layers are then photolithographically patterned and etched to create trenches that divide the material layers into multiple multi-film structures. Storage transistor1300results from further processing of one of the multi-film structures. Oxide layer1365of each multi-film structure is then recessed from the sidewalls of the multi-film structure, whereupon channel layer1350may be deposited into the recessed cavities in the sidewalls. InFIG.13, only one NOR memory string is provided in each multi-film structure. However, in a 3-dimensional NOR memory string array, multiple NOR memory strings may be provided in each multi-film structure, one atop of another, with each NOR memory string being isolated from another in the multi-film structure by an interlayer dielectric (ILD) layer (e.g., ILD layer1325). Storage transistor1300is substantially formed after conformal deposition of gate dielectric layer1340, followed by deposition of trench-filling gate electrode1320. Gate electrode1320may be a relatively heavily-doped p+semiconductor (e.g., polysilicon) film, a metal or any suitable conductive material.

As described above, gate dielectric layer1340may be formed using an ONO stack or an ONOA stack, each having a tunnel dielectric layer, a charge trap layer and one or more blocking layers. The tunnel dielectric layer is preferably very thin (e.g., less than 3.0 nm, if provided by a silicon oxide layer), so as to allow direct tunneling of charge carriers through the tunnel dielectric layer to the charge trap layer. With such a thin tunnel dielectric layer, charge accumulates (“programs”) or depletes (“erases”) very rapidly from the charge trap layer. A programming operation accumulates sufficient charge carriers in the charge trap layer until a predetermined threshold voltage change is effectuated (“programmed state”) in the storage transistor. The reverse operation, i.e., depleting charge carriers from the charge trap layer, is complete when the same threshold voltage change is effectuated (“erased state”) in the opposite direction.

For some applications, it is advantageous for the programming and erase operations to complete within the storage transistor1300as quickly as possible. In general, a thinner tunnel dielectric layer enables a faster programming or erasing operation, as a thinner tunnel dielectric layer represents a lower energy barrier for charge accumulation or depletion from the charge trap layer. However, even though a thin tunnel dielectric layer is beneficial for a faster programming or erase operation, a thin tunnel dielectric layer is detrimental for charge retention in the charge trap layer. A thinner tunnel dielectric layer facilitates charge leakage from the charge trap layer. (Charge retention in a memory cell may be characterized by a “retention time,” being the time period over which a predetermined fraction of the charge of the programmed state is leaked away from the charge trap layer.)

Another key characteristic of a storage transistor in a NOR memory string is its endurance. Endurance may be characterized by the number of program and erase cycles the storage transistor can endure, while maintaining predetermined key characteristics (e.g., threshold voltages) of the programmed and erased states. For example, in one embodiment, the threshold voltage for the programmed state is 2.5±0.5 volts, while the threshold voltage for the erased state may be 1.0±0.5 volts. The goal is for the storage transistor to maintain within its endurance these threshold voltage ranges in their programmed and erased states.

The program and the erase voltages used to achieve the programmed and the erased states, respectively, affect both endurance and the durations of the programming and the erase operations. In general, increasing the programming and the erase voltages reduces the required durations of the respective programming and erase operations. This relationship is beneficial. At the same time, however, increasing the program and erase voltages undesirably reduces the endurance of the storage transistor. In addition, smaller drive transistors may be used for providing the lower programming and erase voltages, which allows a desirable reduced chip size and a lower “cost-per-bit.”

According to one embodiment of the present invention, a silicon oxide nitride (SiON) tunnel dielectric film is used for the tunnel dielectric layer of multi-film gate dielectric layer1340. For example, gate dielectric layer1340may have a SiON tunnel dielctric layer, a silicon nitride charge trap layer and either a silicon oxide blocking layer or a composite silicon oxide and aluminum oxide blocking layer. The inventors have discovered that, relative to a silicon oxide tunnel dielectric layer of comparable thickness, the SiON tunnel dielectric layer provides superior performance for a storage transistor in a NOR memory string, such as faster programming and erase operations, lower programming and erase voltages, and greater endurance. In this detailed description, a SiON film refers to any SiOxNyfilm, where the values of x and y may each be a value between 0.01 and 0.99. Thus, SiON is also referred to in this detailed description as silicon oxynitride.

The inventors compared the performances of two multi-film layers or stacks used as gate dielectric layer1340: one with a 1.2 nm silicon oxide tunnel dielectric layer, and the other one with a 1.2 nm SiON tunnel dielectric layer. The remainder films in each stack are: a 5-nm silicon nitride charge trap layer and a 5-nm silicon oxide blocking layer. The tunnel dielectric layers are each formed using low pressure chemical vapor deposition (LPCVD). The silicon oxide tunnel dielectric layer is deposited at 755° C. and at a 300 mTorr vapor pressure, under dichlorosilane (DCS) and nitrous oxide (N2O) gas flows. The SiON tunnel dielectric layer is deposited at 755° C. and 350 mTorr vapor pressure, under DCS, N2O, and ammonia (NH3) gas flows. By varying the ratio of N2O to NH3, the relative amounts of oxygen or nitrogen in the SiON tunnel dielectric layer may be varied. The composition of the SiON tunnel dielectric layer is estimated using its index of refraction. The indices of refraction of silicon oxide and silicon nitride are, respectively, approximately 1.46 and approximately 2.0, such that an SiON film is expected to have an index of refraction between 1.46 and 2.0.

In one embodiment, the SiON tunnel dielectric layer has an index of refraction of approximately 1.7. The 1.2-nm SiON tunnel dielectric layer with an index of refraction of approximate 1.7 was deposited using an N2O to NH3gas flow ratio of about 4. The inventors have determined that a suitable range of thickness for such SiON tunnel dielectric layer in a storage transistor of a NOR memory string should be between 0.5 to 5.0 nm, with an index of refraction between 1.5 and 1.9, deposited between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, N2O, and NH3gas flows. A thin film that has in its composition more than one element (e.g., a SiON film discussed herein has a composition that includes silicon, oxygen and nitrogen) may be characterized by the atomic percentage or at % of each of its elements. For example, a silicon dioxide (SiO2) film with a refractive index (n) of 1.46 may be characterized by its 66.67 at % oxygen and 33.33 at % silicon. Similarly, a silicon nitride (Si3N4) film with a refractive index of 2.0 is characterized by its 57.1 at % nitrogen. For the SiON tunnel dielectric layer with a refractive index of 1.7 discussed herein, it may be characterized by its approximate composition of SiO0.5N0.5or 25 at % nitrogen, as reported, for example, in the article, “Deposition and Composition Of Silicon Oxynitride Films,” by A. E. T. Kuiper et al., Journal of Vacuum Science and Technology B; Microelectronics Processing and Phenomenon, vol. 1, No. 1, (January-March 1983), pp. 62-66.

The inventors discovered that the median programming pulses (i.e., comparable voltage and duration) required for achieving a desired programming window (i.e., a 1.0 volts voltage difference between the threshold voltages of the “programmed” and “erased” states) are comparable (e.g., within 0.1 volts) in storage transistors using a SiON tunnel dielectric layer, relative to storage transistors using a silicon oxide tunnel dielectric layer of equal thickness. However, a substantially lower median erase voltage (in magnitude) may be used to achieve the “erased” state of the same programming window in storage transistors using a SiON tunnel dielectric layer, relative to storage transistors using a silicon oxide tunnel dielectric layer of equal thickness. In one instance, a difference of 1.6 volts was observed between the erase voltage with a silicon oxide tunnel dielectric layer and the erase voltage with a SiON tunnel dielectric layer.

The inventors have determined that, for a storage transistor having a SiON tunnel dielectric layer of the present invention, a high-endurance window of operation (e.g., 1.0-2.0 volts difference between programmed and erased states) may be achieved using a programming voltage of about 8.0 volts and an erase voltage of about −8.0 volts. In one instance, the inventors found that the window of operation remains open beyond 1011program-erase cycles. The inventors surmise that lower programming and erase voltages may further improve endurance in the SiON tunnel dielectric layer.

The detailed description above is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.