Patent ID: 12199153

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention. In the following discussion, an N-type device is described for purposes of illustration. P-type devices may be fabricated using a similar process but with opposite conductivity types.

As is noted that the surface charges (Qss) in the termination region may impact the depletion region for the given reverse bias voltage. To resolve the aforementioned problem, the high voltage edge termination structures in according to the embodiments of the present invention are provided to minimize shrinkage of depletion spread and lower peak electric field variations at the termination region for low and high surface charge cases so as to improve tolerance to surface charge variations.

Please referring toFIG.2, a high voltage edge termination structure featuring a laterally modulated JTE structure provided in accordance with a first embodiment of the present invention will be discussed.

As illustrated inFIG.2, the high voltage edge termination structure100comprises an N-type semiconductor body110, a P-type JTE region120, a plurality of P-type lightly doped regions130a-130h, and an N-type heavily doped channel stop region140.

There is an N-type semiconductor layer112with a doping concentration higher than that of the N-type semiconductor body110formed on a lower surface of the N-type semiconductor body110. The N-type semiconductor layer112is utilized for reducing contact resistance between the N-type semiconductor body110and a cathode electrode114of the power semiconductor device.

The P-type JTE region120is formed in the top portion of the N-type semiconductor body110. The P-type JTE region120is adjacent to the active region150of the power semiconductor device and is extended from the active region150toward the edge. To be more precisely, the P-type JTE region120is extended from the P-type well151of the active region150toward the edge of the power semiconductor device. The P-type well151is electrically connected to the anode electrode154through a P-type heavily doped region152.

In accordance with an embodiment of the present invention, the P-type JTE region120may have a constant depth, and the depth of the P-type JTE region120may be equal to or greater than the depth of the P-type well151.

The P-type lightly doped regions130a-130hare formed in the upper portion of the P-type JTE region120, i.e. the portion close to the upper surface of the P-type JTE region120. These P-type lightly doped regions130a-130hare spaced apart from each other.

The N-type heavily doped channel stop region140is formed in the top portion of the N-type semiconductor body110. The N-type heavily doped channel stop region140is located outside the P-type JTE region120utilized for limiting the depletion region at the outer edge of the semiconductor device when the power semiconductor device is reverse-biased. In the present embodiment, a metal layer is formed on the N-type heavily doped channel stop region140. However, the metal layer on the N-type heavily doped channel stop region140may be skipped in some embodiments.

The P-type JTE region120and the plurality of P-type lightly doped regions130a-130htherein form a P-type laterally modulated JTE region. The N-type heavily doped channel stop region140is spaced apart from the P-type JTE region120by an N-type region, i.e. the surface portion of the N-type semiconductor body110. That is, a lateral termination structure with the P-type laterally modulated JTE region, the N-type region, and the N-type heavily doped channel stop region140extended from the active region150to the edge is formed. The P-type laterally modulated JTE region shows the structure featuring the alternatively arranged P and P-regions close to the upper surface of the semiconductor body.

The P-type laterally modulated JTE region featuring a P-type JTE region with a uniform depth and multiple alternatively arranged P and P-regions in the upper portion thereof for spreading depletion. Thus, the P-type laterally modulated JTE region may control the peak surface electric field without too much compromising the breakdown voltage. That is, the P-type laterally modulated JTE region may minimize the reduction of the reverse bias breakdown voltage due to surface charge variations.

The number, the lateral width, and the spacing of these P-type lightly doped regions130a-130hin the P-type JTE region120may be adjustable to optimize the trade-off between blocking capability and surface charge tolerance. As is further illustrated inFIG.2, in accordance with a preferred embodiment of the present invention, a lateral width of the P-type lightly doped regions130a-130hbecomes larger along a direction toward the N-type heavily doped channel stop region140, and a space between the P-type lightly doped region130ain a vicinity of the active region150and the active region150is greater than a space between the neighboring P-type lightly doped regions130b-130h. With the doping modulation in the P-type JTE region120, a shrink in the depletion expansion toward the N-type heavily doped channel stop region140will prompt depletion to expand deeper in the P-type JTE region120toward the active region150. Embodiments of the present invention are not limited to the present configuration. The variation of the lateral width of the lightly doped regions130a-130has well as the arrangement of the lightly doped regions130a-130hin the JTE region120may be adjusted according to the actual condition and should not be deemed as departing from the scope of the present invention.

For a better understanding of the effect of the laterally modulated JTE structure discussed above, please refer toFIGS.2A to2D.FIG.2Ais a simulated structure showing a potential distribution contour of a silicon based high voltage edge termination structure featuring a laterally modulated JTE structure at 1300V bias with surface charge of 5e10Cm−2.FIG.2Bis a simulated structure showing a potential distribution contour of a silicon based high voltage edge termination structure featuring a laterally modulated JTE structure at 1250V bias with surface charge of 5e11Cm−2.FIG.2Cis a graph showing the surface potential of a silicon based voltage high voltage edge termination structure featuring a laterally modulated JTE structure at 1300V bias with surface charge of 5e10Cm−2.FIG.2Dis a graph showing the surface potential of a silicon based voltage high voltage edge termination structure featuring a laterally modulated JTE structure at 1250V bias with surface charge of 5e11Cm−2.

The high voltage edge termination structure featuring a laterally modulated JTE structure shows a constant depth of P-type JTE region modulated by Phosphorus implanted via varying size mask windows is used for the simulation. The size of the Phosphorus implant windows increases and the space between these windows shrinks to increase doping modulation along the direction from the active region toward the N-type heavily doped channel stop region, i.e. the die edge. The Phosphorous compensation implant modulates the doping concentration of the P-type JTE region to form the laterally modulated JTE region.

As shown inFIG.2A, in the case of a low positive surface charge, i.e. Qss of 5e10Cm−2, this results in depletion spreading from the N-type heavily doped channel stop region toward the surface region of the P-type JTE region. As shown inFIG.2B, in the case of high positive surface charge, i.e. Qss of 5e11Cm−2, depletion expansion from the P-type JTE region toward the N-type channel stop region is shrunk, however, due to doping modulation in the P-type JTE region, a shrink in the depletion expansion toward the N-type channel stop region will prompt depletion to expand deeper in the P-type JTE region toward the active region.

As shown inFIGS.2C and2D, the simulation result for both the cases of low and high surface charge shows a uniform surface potential distribution at 1300V and 1250V bias respectively. Thus, the laterally modulated JTE structure provided in accordance with the embodiment of the present invention may effectively prevent the power device from being breakdown at lower voltage. In practice, the high voltage edge termination structure featuring a laterally modulated JTE structure may achieve a breakdown voltage over 1200V for low and high surface charge cases.

Referring toFIG.3, a high voltage edge termination structure featuring a JTE structure with field plates provided in accordance with a second embodiment of the present invention will be discussed.

As illustrated inFIG.3, the high voltage edge termination structure200comprises an N-type semiconductor body210, a P-type JTE region220, an N-type heavily doped channel stop region240, and a plurality of field plates260(three field plates are shown).

There is an N-type semiconductor layer212with a doping concentration higher than that of the N-type semiconductor body210formed on a lower surface of the N-type semiconductor body210. The N-type semiconductor layer212is utilized for reducing contact resistance between the N-type semiconductor body210and a cathode electrode214of the power semiconductor device.

The P-type JTE region220is formed in the top portion of the N-type semiconductor body210, i.e. the portion close to the upper surface thereof. The P-type JTE region220is adjacent to the active region250of the power semiconductor device and is extended from the active region250toward the edge. To be more precisely, the P-type JTE region220is extended from the P-type well251of the active region250toward the edge of the power semiconductor device. The P-type well251is electrically connected to the anode electrode254through a P-type heavily doped region252.

The N-type heavily doped channel stop region240is formed in the top portion of the N-type semiconductor body210outside the P-type JTE region220for limiting the depletion region at the outer edge of the semiconductor device when the power semiconductor device is reverse-biased. The N-type heavily doped channel stop region240is spaced apart from the P-type JTE region220by an N-type region (part of the top portion of the N-type semiconductor body210). That is, a lateral termination structure with the P-type JTE region220, an N-type region, and the N-type heavily doped channel stop region240is formed. In the present embodiment, a metal layer is formed on the N-type heavily doped channel stop region240. However, the metal layer on the N-type heavily doped channel stop region240may be skipped in some embodiments.

The plurality of field plates260is formed on the P-type JTE region220. The field plates260on the P-type JTE region220may spread the electric field generated by the surface charge so as to minimize the reduction of the reverse bias breakdown voltage due to surface charge variations.

In an embodiment of the present invention, the field plates260may be made of a metal material to form a Schottky contact with the P-type JTE region220. In an embodiment of the present invention, the field plates260may be made of a P-type poly-silicon material to form an ohmic contact with the P-type JTE region220. In an embodiment of the present invention, the field plates260may be made of an N-type poly-silicon material to form a PN junction with the P-type JTE region220.

Referring toFIG.4, a high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates provided in accordance with a third embodiment of the present invention will be discussed.

As illustrated inFIG.4, the high voltage edge termination structure300comprises an N-type semiconductor body310, a P-type JTE region320, an N-type heavily doped channel stop region340, a plurality of field plates360(three field plates are shown), and a plurality of P-type depletable guard rings370(four depletable guard rings are shown).

There is an N-type semiconductor layer312with a doping concentration higher than that of the N-type semiconductor body310formed on a lower surface of the N-type semiconductor body310. The N-type semiconductor layer312is utilized for reducing contact resistance between the N-type semiconductor body310and a cathode electrode314of the power semiconductor device.

The P-type JTE region320is formed in top portion of the N-type semiconductor body310. The P-type JTE region320is adjacent to the active region350of the power semiconductor device. To be more precisely, the P-type JTE region320is adjacent to the P-type well351of the active region350of the power semiconductor device. The P-type well351is electrically connected to the anode electrode354through a P-type heavily doped region352.

The N-type heavily doped channel stop region340is formed in the top portion of the N-type semiconductor body310outside the P-type JTE region320for limiting the depletion region at the outer edge of the semiconductor device when the power semiconductor device is reverse-biased. The N-type heavily doped channel stop region340is spaced apart from the P-type JTE region320by an N-type region (part of the top portion of the N-type semiconductor body310). In the present embodiment, a metal layer is formed on the N-type heavily doped channel stop region340. However, the metal layer on the N-type heavily doped channel stop region340may be skipped in some embodiments.

The plurality of P-type depletable guard rings370is formed in the top portion of the N-type semiconductor body310, and the P-type depletable guard rings370are formed between the P-type JTE region320and the N-type heavily doped channel stop region340. The P-type depletable guard rings370are electrically floating. When a high bias is applied, the P-type depletable guard ring370depletes to produces a charge balanced region for the N-type region between the P-type JTE region320and the N-type heavily doped channel stop region340to spread the depletion. This would be helpful for spreading the electric field generated by surface charge so as to minimize the reduction of the reverse bias breakdown voltage due to surface charge variations.

The plurality of field plates360is formed on the P-type JTE region320and the P-type depletable guard rings370. The field plates360may spread the electric field generated by the surface charge so as to minimize the reduction of the reverse bias breakdown voltage due to surface charge variations.

For a better understanding of the effect of the depletable guard rings and the field plates together with the JTE structure discussed above, please refer toFIGS.4A to4D.FIG.4Ais a simulated structure showing a potential distribution contour of a silicon based high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates at 630V bias with surface charge of 5e10Cm−2.FIG.4Bis a-simulated structure showing a potential distribution contour of a silicon based high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates at 630V bias with surface charge of 5e11Cm−2.FIG.4Cis graph showing a surface potential of a silicon based high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates at 630V bias with surface charge of 5e10Cm−2.FIG.4Dis a graph showing a surface potential of a silicon based high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates at 630V bias with surface charge of 5e11Cm−2.

The high voltage edge termination structure featuring a P-type JTE region shows a constant depth, five P-type depletable guard rings located between the P-type JTE region and the N-type channel stop region, and two field plates is used for the simulation.

Please refer toFIGS.4A and4B, in the case of high surface charge, i.e. Qss of 5e11Cm−2, depletion spreads more into P-type JTE region and less in the N-type region between the last P-type depletable guard ring and the N-type heavily doped channel stop region in comparison to the case of low surface charge, i.e. Qss of 5e10Cm−2. The field plates on the P-type depletable guard rings would be helpful for spreading the depletion region in the N-type region between last P-type depletable guard ring and the N-type heavily doped channel stop region toward the die edge to prevent breakdown voltage degradation.

As shown inFIGS.4C and4D, the simulation result for both the cases of low and high surface charge shows a uniform surface potential distribution at 630V bias. Thus, the high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates provided in accordance with the embodiment of the present invention may effectively prevent the power device from being breakdown at lower voltage. In practice, the high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates may achieve a breakdown voltage over 600V for low and high surface charge cases.

Both the high voltage edge termination structure featuring a JTE structure with depletable guard rings shown inFIG.3and the high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates shown inFIG.4work the same in principle by countering depletion region shrinkage of high surface charge cases to achieve the required breakdown voltage from the termination of a power device. The field plate may assume the potential of the P-type region which the field plate is in contact with, e.g. the P-type JTE region or the P-type depletable guard ring, regardless of the type of electrical contact formed between the field plate and the P-type region. These field plates with potential established by the P-type regions in contact with will reduce the increasing of the surface electric field as the surface charge increases by spreading surface potential to a longer depletion region.

The usage of field plates and depletable guard rings in conjunction with the JTE structure as shown inFIGS.3and4are capable to be used for the power devices up to 600V. The usage of field plates and depletable guard rings in conjunction with the laterally modulated JTE structure as shown inFIG.5andFIG.6may provide extra capability to minimize breakdown reduction with increasing surface charge for the power devices of a breakdown voltage about 1200V or higher.

Referring toFIG.5, a high voltage edge termination structure featuring a laterally modulated JTE structure with depletable guard rings and field plates provided in accordance with a fourth embodiment of the present invention will be discussed.

As illustrated inFIG.5, the high voltage edge termination structure400comprises an N-type semiconductor body410, a P-type JTE region420, a plurality of P-type lightly doped regions430a-430e, an N-type heavily doped channel stop region440, a plurality of field plates460(three field plates are shown) and a plurality of P-type depletable guard rings470(four depletable guard rings are shown).

There is an N-type semiconductor layer412with a doping concentration higher than that of the N-type semiconductor body410formed on a lower surface of the N-type semiconductor body410. The N-type semiconductor layer412is utilized for reducing contact resistance between the N-type semiconductor body410and a cathode electrode414of the power semiconductor device.

The P-type JTE region420is formed in the top portion of the N-type semiconductor body410. The P-type JTE region420is adjacent to the active region450of the power semiconductor device. To be more precisely, the P-type JTE region420is adjacent to the P-type well451of the active region450of the power semiconductor device. The P-type well451is electrically connected to the anode electrode454through a P-type heavily doped region452.

The N-type heavily doped channel stop region440is formed in the top portion of the N-type semiconductor body410outside the P-type JTE region420for limiting the depletion region at the outer edge of the semiconductor device when the power semiconductor device is reverse-biased. In the present embodiment, a metal layer is formed on the N-type heavily doped channel stop region440. However, the metal layer on the N-type heavily doped channel stop region440may be skipped in some embodiments.

Some of the P-type lightly doped regions, i.e. the P-type lightly doped region430a, is formed in the upper portion of the P-type JTE region420. The P-type JTE region420and the P-type lightly doped region430atherein form a P-type laterally modulated JTE region.

The P-type depletable guard rings470are formed in the top portion of the N-type semiconductor body410, and is located between the P-type JTE region420and the N-type heavily doped channel stop region440. The P-type depletable guard rings470are electrically floating. When a high bias is applied, the P-type depletable guard ring470depletes to produces a charge balanced region for the N-type region between the P-type JTE region420and the N-type heavily doped channel stop region440to spread the depletion. This would be helpful for spreading the electric field generated by surface charge so as to minimize the reduction of the reverse bias breakdown voltage due to surface charge variations.

The P-type lightly doped regions430a-430eare formed in the upper portion of the P-type JTE region420and the P-type depletable guard rings470for modulating the P-type JTE region420and the P-type depletable guard rings470. As shown, the P-type lightly doped region430ais located in the upper portion of the P-type JTE region420, the P-type lightly doped regions430b-430eare located in the P-type depletable guard rings470respectively. These P-type lightly doped regions430a-430eare spaced apart from each other. As shown, a lateral termination structure with the P-type laterally modulated JTE region, the P-type depletable guard rings470, the N-type region (part of the upper portion of the N-type semiconductor body), and the N-type heavily doped channel stop region440extended from the active region450to the edge is formed.

The plurality of field plates460is formed on the P-type JTE region420and the P-type depletable guard rings470. The field plates460may spread the electric field generated by the surface charge so as to minimize the reduction of the reverse bias breakdown voltage due to surface charge variations. In an embodiment of the present invention, the field plates460may be made of a metal material to form a Schottky contact with the P-type region, i.e. the P-type JTE region420or the P-type depletable guard ring470. In an embodiment of the present invention, the field plates460may be made of a P-type poly-silicon material to form an ohmic contact with the P-type region. In an embodiment of the present invention, the field plates460may be made of an N-type poly-silicon material to form a PN junction with the P-type region.

As mentioned above, the P-type laterally modulated JTE region shows the structure featuring multiple P and P-regions to minimize the reduction of the reverse bias breakdown voltage due to surface charge variations, the field plates and the depletable guard rings may counter depletion region shrinkage of high surface charge cases to achieve the required breakdown voltage from the termination of a power device.

Referring toFIG.6, a high voltage edge termination structure featuring a laterally modulated JTE structure with field plates provided in accordance with a fourth embodiment of the present invention will be discussed.

As illustrated inFIG.6, the high voltage edge termination structure500comprises an N-type semiconductor body510, a P-type JTE region520, a plurality of P-type lightly doped regions530a-530h, an N-type heavily doped channel stop region540, and a plurality of field plates560(three field plates are shown).

There is an N-type semiconductor layer512with a doping concentration higher than that of the N-type semiconductor body510formed on a lower surface of the N-type semiconductor body510. The N-type semiconductor layer512is utilized for reducing contact resistance between the N-type semiconductor body510and a cathode electrode514of the power semiconductor device.

The P-type JTE region520is formed in the top portion of the N-type semiconductor body510. The P-type JTE region520is adjacent to the active region550of the power semiconductor device and is extended from the active region550toward the edge. To be more precisely, the P-type JTE region520is adjacent to the P-type well551of the active region550of the power semiconductor device. The P-type well551is electrically connected to the anode electrode554through a P-type heavily doped region552.

The P-type lightly doped regions530a-530hare formed in the upper portion of the P-type JTE region520, i.e. the portion close to the upper surface of the P-type JTE region520. These P-type lightly doped regions530a-530hare spaced apart from each other.

The N-type heavily doped channel stop region540is formed in the top portion of the N-type semiconductor body510outside the P-type JTE region520for limiting the depletion region at the outer edge of the semiconductor device when the power semiconductor device is reverse-biased. In the present embodiment, a metal layer is formed on the N-type heavily doped channel stop region540. However, the metal layer on the N-type heavily doped channel stop region540may be skipped in some embodiments.

The P-type JTE region520and the plurality of P-type lightly doped regions530a-530htherein form a P-type laterally modulated JTE region. The N-type heavily doped channel stop region540is spaced apart from the P-type JTE region520by an N-type region, i.e. the surface portion of the N-type semiconductor body510. That is, a lateral termination structure with the P-type laterally modulated JTE region, the N-type region, and the N-type heavily doped channel stop region540extended from the active region550to the edge is formed. The P-type laterally modulated JTE region shows the structure featuring the alternatively arranged P and P-regions close to the upper surface of the semiconductor body for spreading depletion. Thus, the P-type laterally modulated JTE region may minimize the reduction of the reverse bias breakdown voltage due to surface charge variations.

Similar to the embodiment shown inFIG.2, in accordance with a preferred embodiment of the present invention, a lateral width of the P-type lightly doped regions530a-530hbecomes larger along a direction toward the N-type heavily doped channel stop region540, and a space between the P-type lightly doped region530ain a vicinity of the active region550and the active region550is greater than a space between the neighboring P-type lightly doped regions530b-530h. With the doping modulation in the P-type JTE region520, a shrink in the depletion expansion toward the N-type heavily doped channel stop region540will prompt depletion to expand deeper in the P-type JTE region520toward the active region550. Embodiments of the present invention are not limited to the present configuration. The variation of the lateral width of the lightly doped regions530a-530has well as the arrangement of the lightly doped regions530a-530hin the JTE region520may be adjusted according to the actual condition and should not be deemed as departing from the scope of the present invention.

The plurality of field plates560is formed on the P-type JTE region520. The field plates560may counter depletion region shrinkage of high surface charge cases to achieve the required breakdown voltage from the termination of a power device. That is, the field plates560are also helpful for minimizing the reduction of the reverse bias breakdown voltage due to surface charge variations. In an embodiment of the present invention, the field plates560may be made of a metal material to form a Schottky contact with the P-type JTE region520. In an embodiment of the present invention, the field plates560may be made of a P-type poly-silicon material to form an ohmic contact with the P-type JTE region520. In an embodiment of the present invention, the field plates560may be made of an N-type poly-silicon material to form a PN junction with the P-type JTE region520.

FIGS.7A to7Gare schematic illustration showing a manufacturing process of a high voltage edge termination structure featuring a JTE structure with depletable guard rings and field plates provided in accordance with an embodiment of the present invention.

Six masks are used in the manufacturing process. Mask1is for defining the channel stop region. Mask2is for executing the JTE implantation. Mask3is for forming the anode of the active region. Mask4is for forming the contact. Mask5is for forming the metal layer. Mask6is for forming the passivation/polyimide layer.

Referring toFIG.7A, firstly, an N-type semiconductor body610is provided. Then, Mask1is used to define the channel stop window for forming the channel stop region, and then an N-type heavily doped channel stop region640is formed in the N-type semiconductor body610by ion implantation or diffusion. By way of example, but not of limitation, phosphorus ions with a doping concentration ranging from 1e15Cm−2to 1e16Cm−2may be implanted into the N-type semiconductor body610to form the N-type heavily doped channel stop region640, or a POCl3diffusion process may be used to form the N-type heavily doped channel stop region640in the N-type semiconductor body610.

Afterward, referring toFIG.7B, Mask2is used to define the position of the P-type JTE region and the P-type depletable guard rings, and then an ion implantation step is carried out to form the P-type JTE region620and the P-type depletable guard rings670simultaneously. The P-type JTE region620is adjacent to the active region of the power semiconductor device and is spaced apart from the N-type heavily doped channel stop region640. The depletable guard rings670are formed between the P-type JTE region620and the N-type heavily doped channel stop region640. By way of example, but not of limitation, boron ions with a doping concentration ranging from 5e12Cm−2to 2e13Cm−2may be implanted into the N-type semiconductor body610to form the P-type JTE region620and the P-type depletable guard rings670.

Thereafter, referring toFIG.7C, after the ion implantation step ofFIG.7B, a high-temperature diffusion step is executed to drive the P-type JTE region620and the P-type depletable guard rings670deeper. By way of example, but not of limitation, the high-temperature diffusion step may have the P-type JTE region620achieves a junction depth ranging from 5 um to 10 um.

Afterward, referring toFIG.7D, Mask3is used to define the position of the anode region in the active region and then an ion implantation step may be executed to form the anode region652in the active region. By way of example, but not of limitation, boron ions with a doping concentration ranging from 1e14Cm−2to 5e15Cm−2may be implanted into the P-type well651in the active region to form the P-type anode region652.

Then, referring toFIG.7E, a dielectric layer680is deposited on the semiconductor body610. By way of example, but not of limitation, the dielectric layer680may be an oxide layer, a Phosphosilicate glass (PSG) layer or a borophosphosilicate glass (BPSG) layer. Then, Mask4is used to form the contact windows682in the dielectric layer680.

Afterward, referring toFIG.7F, a metal layer is deposited on the dielectric layer680and fills the contact window682. Thereafter, Mask5is used to define the anode electrode and the field plates, and then an etching step is carried out to form the anode electrode654and the field plates660. By way of example, but not of limitation, the metal layer may be an AlCu layer or an AlSiCu layer with or without the Ti/TiN buffer layer depending on the junction depths.

Referring toFIG.7G, after the formation of the anode electrode654and the field plates660, a passivation layer690is deposited. By way of example, but not of limitation, the passivation layer690may be a SiO2type passivation layer or a Si3N4type passivation layer. By way of example, but not of limitation, a polyimide layer may be used to replace the passivation layer. Then, after the deposition of the passivation layer690, Mask6is applied to define the bonding pad areas (not shown).

It is noted that the aforementioned manufacturing process utilizes a single mask (Mask2) to define the P-type JTE region620and the P-type depletable guard rings670, and a single mask to define the anode electrode654and the field plates660so as to reduce the masking steps.

FIGS.8A to8Gare schematic illustration showing a manufacturing process of a high voltage edge termination structure featuring a laterally modulated JTE structure provided in accordance with an embodiment of the present invention.

Seven masks are used for the manufacturing process. Mask1is for defining the channel stop region. Mask2is for executing the JTE implantation. Mask3is for forming the lightly doped regions in the JTE region to form the laterally modulated JTE region. Mask4is for forming the anode of the active region. Mask5is for forming the contact. Mask6is for forming the metal layer. Mask7is for forming the passivation/polyimide layer.

Referring toFIG.8A, firstly, an N-type semiconductor body710is provided. Then, Mask1is used to define the channel stop window for forming the channel stop region, and then the N-type heavily doped channel stop region740is formed in the N-type semiconductor body710by ion implantation or diffusion. By way of example, but not of limitation, phosphorus ions with a doping concentration ranging from 1e15Cm−2to 1e16Cm−2may be implanted into the N-type semiconductor body710to form the N-type heavily doped channel stop region740, or a POCl3diffusion process may be used to form the N-type heavily doped channel stop region740in the N-type semiconductor body710.

Afterward, referring toFIG.8B, Mask2is used to define the position of the P-type JTE region, and then the P-type JTE region720is formed by ion implantation. The P-type JTE region720is adjacent to the active region of the power semiconductor device and is spaced apart from the N-type heavily doped channel stop region740. By way of example, but not of limitation, boron ions with a doping concentration ranging from 5e12Cm−2to 2e13Cm−2may be implanted into the N-type semiconductor body710to form the P-type JTE region720.

Thereafter, referring toFIG.8C, Mask3is used to define a plurality of lightly doped regions in the P-type JTE region720, and then an ion implantation step is executed to form the plurality of lightly doped regions730a-730fin the P-type JTE region720. By way of example, but not of limitation, these P-type lightly doped regions730a-730fmay be formed by implanting N-type impurities via the dedicated Mask3with varying open areas into the P-type JTE region720to counter dope the P-type JTE region720.

These P-type lightly doped regions730a-730fmay be used to modulate the doping concentration of the P-type JTE region720from the active region toward the edge. By way of example, but not of limitation, a lateral width of these P-type lightly doped regions730a-730fbecomes larger along a direction from the active region toward the N-type heavily doped channel stop region740, and a space between the P-type lightly doped region730ain a vicinity of the active region and the active region is greater than a space between the neighboring lightly doped regions730b-730f.

After the ion implantation step, a high-temperature diffusion step is executed to drive the P-type JTE region720deeper. By way of example, but not of limitation, the high-temperature diffusion step may have the P-type JTE region720achieves a junction depth ranging from 5 um to 10 um.

Afterward, referring toFIG.8D, Mask4is used to define the position of the anode region in the active region and then an ion implantation step is executed to form the anode region752. By way of example, but not of limitation, boron ions with a doping concentration ranging from 1e14Cm−2to 5e15Cm−2may be implanted into the P-type well751in the active region to form the P-type anode region752.

Then, referring toFIG.8E, a dielectric layer780is deposited on the semiconductor body710. By way of example, but not of limitation, the dielectric layer780may be an oxide layer, a PSG layer or a BPSG layer. Then, Mask5is used to form the contact windows782in the dielectric layer780.

Referring toFIG.8F, a metal layer is deposited on the dielectric layer780and fills the contact window782. Thereafter, Mask6is used to define the anode electrode and the field plates, and then an etching step is carried out to form the anode electrode754and the field plates760. By way of example, but not of limitation, the metal layer may be an AlCu layer or an AlSiCu layer with or without the Ti/TiN buffer layer depending on the junction depths.

Referring toFIG.8G, after the formation of the anode electrode754and the field plates760, a passivation layer790is deposited. By way of example, but not of limitation, the passivation layer790may be a SiO2type passivation layer or a Si3N4type passivation layer. By way of example, but not of limitation, a polyimide layer may be used to replace the passivation layer790. Then, after the deposition of the passivation layer790, Mask6is applied to define the bonding pad areas (not shown).

It is noted that the aforementioned manufacturing process utilizes a single mask (Mask2) to define the P-type JTE region720to establish uniformity in lower portion of the P-type JTE region720and a modulation mask (Mask3) with varying implant window openings is used to counter dope the P-type JTE region720. The varying window openings enable compensation of the upper portion of the P-type JTE region720. The opening area of the modulation mask (Mask3) may be increased along the direction toward the device edge to form more P-type lightly doped regions730a-730fto spread depletion.

In the case of laterally modulated JTE structure shown inFIG.1B, the multiple-zone P-type JTE regions require a finer lithography capability which many power device fabs may not have. As a result, the JTE structure with the multiple-zone P-type JTE regions may needs a larger or a supplement area for implementation. In contrast, the present embodiment utilizes a single P-JTE mask to establish uniformity in the deeper portion of the P-type JTE region and a modulation mask with varying implant window openings to counter dope the P-type JTE region. The varying window openings enable compensation of the upper portion of the P-type JTE region to spread depletion around the surface region so as to improve surface charge tolerance of JTE structure. The high voltage edge termination structure provided in accordance with the embodiments of the present invention may increase tolerance to surface charge variation with minimal increase in area for implementation.

Although embodiments of the present invention are discussed above primarily with respect to silicon semiconductor devices, embodiments of the present invention are not limited thereto. For example, the high voltage edge termination structures in accordance with some embodiments of the present invention may be formed on the semiconductor body of silicon carbide (SiC), gallium nitride (GaN) or gallium arsenide (GaAs) without departing from the scope of the present invention.

Although embodiments of the present invention are discussed above primarily with respect to a power diode, embodiments of the present invention are not limited thereto. For example, the high voltage edge termination structures in accordance with some embodiments of the present invention may be applied to the semiconductor device with a MOSFET structure, the semiconductor device with an IGBT structure, or the semiconductor device with a thyristor type structure without departing from the scope of the present invention.

While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A”, or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for.”

The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.