Patent ID: 12212227

The appended drawings are not necessarily to scale, and may present a somewhat simplified representation of various preferred features of the present disclosure as disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes. Details associated with such features will be determined in part by the particular intended application and use environment.

DETAILED DESCRIPTION

The components of the disclosed embodiments, as described and illustrated herein, may be arranged and designed in a variety of different configurations. Thus, the following detailed description is not intended to limit the scope of the disclosure, as claimed, but is merely representative of possible embodiments thereof. In addition, while numerous specific details are set forth in the following description in order to provide a thorough understanding of the embodiments disclosed herein, some embodiments can be practiced without some of these details. Moreover, for the purpose of clarity, certain technical material that is understood in the related art has not been described in detail in order to avoid unnecessarily obscuring the disclosure.

Furthermore, the drawings are in simplified form and are not to precise scale. For purposes of convenience and clarity only, directional terms such as top, bottom, left, right, up, over, above, below, beneath, rear, and front, may be used with respect to the drawings. These and similar directional terms are not to be construed to limit the scope of the disclosure. Furthermore, the disclosure, as illustrated and described herein, may be practiced in the absence of an element that is not specifically disclosed herein. Throughout the drawings, corresponding reference numerals indicate like or corresponding parts and features.

As used herein, the term “system” may refer to one of or a combination of mechanical and electrical actuators, sensors, controllers, application-specific integrated circuits (ASIC), combinatorial logic circuits, software, firmware, and/or other components that are arranged to provide the described functionality.

Embodiments may be described herein in terms of functional and/or logical block components and various processing steps. Such block components may be realized by a combination or collection of mechanical and electrical hardware, software, and/or firmware components configured to perform the specified functions. For example, an embodiment may employ various combinations of mechanical components and electrical components, integrated circuit components, memory elements in the form of control algorithms and calibrations, digital signal processing elements, logic elements, look-up tables, or the like, which may carry out a variety of functions under the control of one or more microprocessors or other control devices. In addition, those skilled in the art will appreciate that the embodiments may be practiced in conjunction with other mechanical and/or electronic systems, and that the vehicle systems described herein are merely embodiments of possible implementations.

The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.

Referring to the drawings, wherein like reference numerals correspond to like or similar components throughout the several Figures,FIG.1, consistent with embodiments disclosed herein, illustrates a non-limiting example of a variable current gate driver10for a solid state switch (transistor)60. The transistor60is a semiconductor switch e.g., a power transistor, in one embodiment. The transistor60may be one of a field-effect transistor (FET), a metal oxide semiconductor field-effect transistor (MOSFET), an integrated gate bipolar transistor (IGBT), a gallium-nitride (GaN) transistor, a thyristor, a thermopile, a bipolar junction transistor (BJT), a thyristor, a high electron mobility transistor (HEMT), etc., without limitation.

The transistor60has a first power input61, a second power input62, and an activator63. By way of example, when the transistor60is an IGBT, the first power input61is referred to as a collector, the second power input62is referred to as an emitter, and the activator63is referred to as a gate. By way of example, when the transistor60is a FET or MOSFET, the first power input61is referred to as a drain, the second power input62is referred to as a source, and the activator63is referred to as a gate.

The first and second power inputs61,62are electrically connected to a power bus40that includes a positive bus or rail41and a negative bus or rail42, with the first power input61electrically connected to the positive bus41and the second power input62electrically connected to the negative bus42.

The activator63electrically connects to the variable current gate driver10, which controls the activator63to control flow of electric power between the first power input61and the second power input62.

The variable current gate driver10includes a first current control device22that is connected in series with a second current control device24at a junction15, wherein the junction15is electrically connected to the activator63.

Operations of the first and second current control devices22,24are controlled by a controller50. In one embodiment, the controller50is a gate driver integrated circuit or another circuit that is arranged to control the gate driver.

Electric power is input to the first current control device22via a first power input11. In one embodiment, the first power input11is electrically connected to the positive bus41. Alternatively, the first power input11is electrically connected to a reference voltage. Alternatively, the first power input11is electrically connected to a second power supply (not shown), with the second power supply being electrically isolated from the positive bus41.

Electric power is input to the second current control device24via a second power input12. In one embodiment, the second power input12is electrically connected to the negative bus42. Alternatively, the second power input12is electrically connected to a reference voltage, or alternatively, to a ground. Alternatively, the second power input12is electrically connected to the second power supply (not shown), with the second power supply being electrically isolated from the negative bus42.

As such, in one embodiment, the first power input11is electrically connected to the positive bus41and the second power input12is electrically connected to the negative bus42.

Alternatively, the first power input11is electrically connected to the positive bus41and the second power input12is electrically connected to a reference voltage.

Alternatively, the first power input11is electrically connected to the positive bus41and the second power input12is electrically connected to ground.

Alternatively, the first power input11is electrically connected to a reference voltage and the second power input12is electrically connected to the negative bus42. Alternatively, the first power input11is electrically connected to a reference voltage and the second power input12is electrically connected to ground.

The first current control device22is a variable current source, in one embodiment. Alternatively, the first current control device22is a modified voltage source having a controllable output current.

The second current control device24is a variable current source, in one embodiment. Alternatively, the second current control device24is a modified voltage source having a controllable output current.

The controller50generates a first control signal51and slew rate command53that are communicated to the first current control device22to effect control thereof, and generates a second control signal52and slew rate command54that are communicated to the second current control device24to effect control thereof.

The controller50controls the variable current gate driver10to control the first and second current control devices22,24to control a first slew rate of the transistor60during an activation-to-deactivation (i.e., ON-OFF) transition. Stated differently, the variable current gate driver10controls the first and second current control devices22,24to control a first slew rate of the transistor60during a transition in the form of a change of state from an ON state to an OFF state.

The controller50controls the variable current gate driver10to control the first and second current control devices22,24to control a first slew rate of the transistor60during an activation-to-deactivation (i.e., ON-OFF) transition. Stated differently, the variable current gate driver10controls the first and second current control devices22,24to control a first slew rate of the transistor60during a transition in the form of a change of state from an ON state to an OFF state. The controller50controls the variable current gate driver10to control the first and second current control devices22,24to control a second slew rate of the transistor60during a deactivation-to-activation (i.e., OFF-ON) transition. Stated differently, the variable current gate driver10controls the first and second current control devices22,24to control the second slew rate of the transistor60during a transition in the form of a change of state from an OFF state to an ON state. The concepts described herein may be used with transistors that operate at zero-voltage switching, including hard switched power electronic systems, and power inverters for electric vehicle (EV) and non-EV applications.

The controller50is operative to control the first current control device22independently from the second current control device24to control activation of the transistor60via the activator63to control the first and second slew rates.

In one embodiment, and/or under certain operating conditions, the first slew rate is greater than the second slew rate during the activation-to-deactivation (i.e., ON-OFF) transition.

In one embodiment, and/or under certain operating conditions, the first slew rate is less than the second slew rate during the activation-to-deactivation (i.e., ON-OFF) transition.

In one embodiment, and/or under certain operating conditions, the first slew rate is equivalent to the second slew rate during the activation-to-deactivation (i.e., ON-OFF) transition.

In one embodiment, and/or under certain operating conditions, the first slew rate is greater than the second slew rate during the deactivation-to-activation (i.e., OFF-ON) transition.

In one embodiment, and/or under certain operating conditions, the first slew rate is less than the second slew rate during the deactivation-to-activation (i.e., OFF-ON) transition.

In one embodiment, and/or under certain operating conditions, the first slew rate is equivalent to the second slew rate during the deactivation-to-activation (i.e., OFF-ON) transition.

FIG.2schematically illustrates, with continued reference to elements that are described with reference toFIG.1, a non-limiting embodiment of the variable current gate driver10. The variable current gate driver10is in communication with and controlled by controller50and is operatively connected to activator63of transistor60at junction15. The transistor60may be one of a field-effect transistor (FET), a metal oxide semiconductor field-effect transistor (MOSFET), an integrated gate bipolar transistor (IGBT), a gallium-nitride (GaN) transistor, a thyristor, a thermopile, etc., without limitation. As shown, the transistor60is a FET or MOSFET, the first power input61is referred to as a drain, the second power input62is referred to as a source, and the activator63is referred to as a gate.

The controller50is a gate driver circuit that is in communication with the variable current gate driver10. The controller50generates a plurality of control signals, including a first control signal51, a second control signal52, a first resistor control signal (or slew rate)53, and a second resistor control signal (or slew rate)54, which are communicated to the variable current gate driver10.

The variable current gate driver10includes first and second bi-polar junction transistors (BJTs)45,46, respectively, first and second variable resistors43,44, respectively, and first and second switch control circuits47,48, respectively, which are arranged between the first power input11and the second power input12. The first and second BJTs45,46are arranged in series, and form the junction15. The first switch control circuit47is arranged in series with the first variable resistor43, which connects to a gate of the first BJT45. The second switch control circuit48is arranged in series with the second variable resistor44, which connects to a gate of the second BJT46.

The first control signal51is a first command signal that is input to the first switch control circuit47. The first resistor control signal53is input to and controls the first variable resistor43. The first control signal51and the first resistor control signal53control the activation, deactivation, and slew rates of the first BJT45.

The second control signal52is a second command signal that is input to the second switch control circuit48. The second resistor control signal54is input to and controls the second variable resistor44. The second control signal52and the second resistor control signal54control the activation, deactivation, and slew rates of the second BJT46.

The first and second variable resistors43,44are employed to control the gate current, and thus control the slew rates. In one embodiment, the slew rates include an OFF-to-ON slew rate that is controlled by the first variable resistor43, and an ON-to-OFF slew rate that is controlled by the second variable resistor44.

In an alternative embodiment, a selectable resistor array composed as a set of selectable resistors of varying resistance may be employed in place of the first and second variable resistors43,44to control the gate current, and thus control the ON-to-OFF slew rate and the OFF-to-ON slew rate.

This arrangement of the variable current gate driver10and controller50enables variable current control and current amplification, which enables improved control of gate slew rates. The first and second BJTs45,46may be controlled by the first and second variable resistors43,44to output different currents to the gate thus enabling operation over a range of discretely selected slew rates. An embodiment of the variable current gate driver10may be implemented in practice as an application-specific integrated circuit (ASIC).

FIG.3graphically shows a pulsewidth-modulated (PWM) control signal310, a slew rate control signal320, and corresponding current signals330and voltage signals340that are associated with operating an embodiment of the variable current gate driver10that is described with reference toFIGS.1and2to control activator63of transistor60.

The PWM control signal310is controlled to either an OFF state (OFF), or an ON state (ON). The slew rate is defined as the rate of change during the OFF-to-ON transition, or OFF-to-ON slew rate, or the rate of change during the ON-to-OFF transition, or the ON-to-OFF slew rate. The slew rate control signal320includes a slow OFF-to-ON slew rate321, a slow ON-to-OFF slew rate322, a fast OFF-to-ON slew rate323, and a fast ON-to-OFF slew rate324. The terms “slow” and “fast” are relative to each other, and represent discrete slew rates that may be selected based upon operating conditions such as voltage, current, temperature, etc.

Changes in the current signals330and voltage signals340corresponding to the changes in the slow OFF-to-ON slew rate321, the slow ON-to-OFF slew rate322, the fast OFF-to-ON slew rate323, and the fast ON-to-OFF slew rate324are indicated. These lines graphically depict the effect of the various slew rates on the respective changes in the current signal330and voltage signal340. Current-voltage overlap regions331,332,333, and334are identified and indicate areas where power losses occur. Overlap regions331and332are associated with the slow OFF-to-ON slew rate321and the slow ON-to-OFF slew rate322, and overlap regions333and334are associated with the fast OFF-to-ON slew rate323and the fast ON-to-OFF slew rate324. The overlap regions333and334have less area than the overlap regions331and332, indicating that there is less power loss with the fast OFF-to-ON slew rate323and the fast ON-to-OFF slew rate324. However, there is less likelihood of ringing and overshoot with the overlap regions331and332that are associated with the slow OFF-to-ON slew rate321and the slow ON-to-OFF slew rate322. Higher slew rates result in smaller overlap of current and voltage leading to less switching loss but higher overshoot and ringing in voltage and current, which may lead to increased risk of exceeding current and/or voltage limits or electro-magnetic interference issues. Slower slew rates result in greater overlap of current and voltage leading to greater switching loss but less overshoot and ringing in voltage and current leading to risk of less efficient operation. Each of the OFF-to-ON slew rate321, the slow ON-to-OFF slew rate322, the fast OFF-to-ON slew rate323, and the fast ON-to-OFF slew rate324may be changed between cycles and within individual cycles.

FIG.4schematically illustrates an embodiment of a multi-phase motor drive system400that includes a rechargeable energy storage system (RESS)470that provides electric power to a multi-phase electric machine480via an inverter system410. The inverter system410is controlled by an inverter controller430via a gate driver controller450and a variable current gate driver420. The RESS470is a rechargeable device, e.g., a multi-cell lithium ion or nickel metal hydride battery.

The inverter system410electrically connects to the RESS470via a high-voltage bus440that has a positive DC voltage rail441and a negative DC voltage rail442. The inverter system410electrically connects to the multi-phase electric machine480via a plurality of phase leads444.

The inverter controller430is operatively connected to the inverter system410via the gate driver controller450and the variable current gate driver420. The variable current gate driver420is composed of a plurality of the variable current gate drivers10that are described with reference toFIG.1. In one embodiment, the variable current gate driver420acts alone and the gate driver controller450is omitted.

In one embodiment, the multi-phase electric machine480is arranged to provide propulsion torque in a vehicle. The vehicle may include, but not be limited to a mobile platform in the form of a commercial vehicle, industrial vehicle, agricultural vehicle, passenger vehicle, aircraft, watercraft, train, all-terrain vehicle, personal movement apparatus, robot and the like to accomplish the purposes of this disclosure.

The inverter system410includes a plurality of transistors460that are controlled by the inverter controller430via the variable current gate driver420that employs embodiments of the variable current gate driver10described with reference toFIG.1. The plurality of transistors460are analogous to embodiments of the transistors60that are described with reference toFIG.1. The plurality of transistors460are arranged as complementary-paired devices that are electrically connected in series between the positive bus441and the negative bus442, with each of the paired transistors460being associated with one of the phases of the electric machine480. In one embodiment, the plurality of transistors460are arranged as upper transistors461and lower transistors462. In one embodiment, the plurality of transistors460, i.e., the upper transistor461and the lower transistors462, are all the same type of transistor, e.g., each of the transistors460is an IGBT device, or each of the transistors460is a FET, a MOSFET, or another type of transistor. In one embodiment, the upper transistors461are one type of transistor, e.g., an IGBT device, and lower transistors462are a second type of transistor, e.g., a FET, a MOSFET, or another type of transistor other than an IGBT device.

The plurality of variable current gate drivers10individually connect to one of the paired transistors460of one of the phases of the electric machine480to control operation thereof. Thus, the plurality of variable current gate drivers10are arranged as three pairs or a total of six variable current gate drivers10when the electric machine480is a three-phase device. The plurality of variable current gate drivers10receive operating commands from the inverter controller430directly or via the gate driver controller450to control activation and deactivation of each of the variable current gate drivers10to provide motor drive functionality of the electric machine480that is responsive to the operating commands. During operation, each variable current gate driver10generates a pulsewidth-modulated signal in response to a control signal originating from the inverter controller430, which activates one of the transistors460and permits current flow through a half-phase of the inverter system410.

The inverter system410is configured to transform high-voltage DC electric power to high-voltage AC electric power and transform high-voltage AC electric power to high-voltage DC electric power in response to commands from the inverter controller430via the variable current gate driver420. The inverter system410may employ pulsewidth-modulating (PWM) control of the transistors460to convert stored DC electric power originating in the battery470to AC electric power to drive the electric machine480to generate torque. Similarly, the inverter system410converts mechanical power transferred to the electric machine480to DC electric power to generate electric energy that is storable in the battery470, including as part of a regenerative braking control strategy when employed on-vehicle. The inverter system410receives motor control commands from the inverter controller430and controls inverter states to provide the motor drive and regenerative braking functionality.

The inverter controller430includes a processor (P)436and tangible, non-transitory memory (M)437on which is recorded instructions embodying a slew-rate selection and control strategy435. The inverter controller430may also include an analog-to-digital converter (ADC)438. The ADC438may be embodied as an electrical circuit providing a specific sampling rate which provides quantization of the continuous/analog voltage input and outputs a representative digital signal. The memory437may include read-only memory (ROM), flash memory, optical memory, additional magnetic memory, etc., as well as random access memory (RAM), electrically-programmable read only memory (EPROM), a high-speed clock, analog-to-digital (A/D) and/or digital-to-analog (D/A) circuitry, input/output circuitry or devices, and signal conditioning and buffer circuitry.

The inverter controller430generates control signals, include, e.g., a PWM control signal432and a slew rate control signal434, which are communicated to the gate driver controller450.

The gate driver controller450generates a set of signals, including, e.g., first control signal51, second control signal52, first resistor control signal (or slew rate)53, and second resistor control signal (or slew rate)54, for each of the variable current gate drivers10of the variable current gate driver420based upon the PWM control signal432and the slew rate control signal434. These signals provide switching control and slew rate control of the input voltage to control the plurality of switches460of the inverter system410to power the multi-phase electric machine480.

The term “controller” and related terms such as microcontroller, control, control unit, processor, etc. refer to one or various combinations of Application Specific Integrated Circuit(s) (ASIC), Field-Programmable Gate Array(s) (FPGA), Complex programmable logic devices (CPLD) electronic circuit(s), central processing unit(s), e.g., microprocessor(s) and associated non-transitory memory component(s) in the form of memory and storage devices (read only, programmable read only, random access, hard drive, etc.). The non-transitory memory component is capable of storing machine readable instructions in the form of one or more software or firmware programs or routines, combinational logic circuit(s), input/output circuit(s) and devices, signal conditioning, buffer circuitry and other components, which can be accessed by and executed by one or more processors to provide a described functionality. Input/output circuit(s) and devices include analog/digital converters and related devices that monitor inputs from sensors, with such inputs monitored at a preset sampling frequency or in response to a triggering event. Software, firmware, programs, instructions, control routines, code, algorithms, and similar terms mean controller-executable instruction sets including calibrations and look-up tables. Each controller executes control routine(s) to provide desired functions. Routines may be executed at regular intervals, for example every 100 microseconds during ongoing operation. Alternatively, routines may be executed in response to occurrence of a triggering event. Communication between controllers, actuators and/or sensors may be accomplished using a direct wired point-to-point link, a networked communication bus link, a wireless link, or another communication link. Communication includes exchanging data signals, including, for example, electrical signals via a conductive medium; electromagnetic signals via air; optical signals via optical waveguides; etc. The data signals may include discrete, analog and/or digitized analog signals representing inputs from sensors, actuator commands, and communication between controllers. The term “signal” refers to a physically discernible indicator that conveys information, and may be a suitable waveform (e.g., electrical, optical, magnetic, mechanical or electromagnetic), such as DC, AC, sinusoidal-wave, triangular-wave, square-wave, vibration, and similar signals that are capable of traveling through a medium.

A parameter is defined as a measurable quantity that represents a physical property of a device or other element that is discernible using one or more sensors and/or a physical model. A parameter can have a discrete value, e.g., either “1” or “0”, or can be infinitely variable in value.

This arrangement provides an architecture that enables dynamic control of a variable gate turn-on slew rate and turn-off slew rate at every switching event to optimize system efficiency while ensuring operation of the transistors and other power devices.

FIG.5graphically illustrates speed/torque operating regions and associated slew rates for operating an embodiment of the multi-phase motor drive system400that is described with reference toFIG.4. Torque510is indicated on the vertical axis, and speed520is indicated on the horizontal axis. Operating regions include a high torque region521, normal driving region522, regenerative braking region523, high-speed region524, and high temperature region525.

Operating the multi-phase motor drive system400includes controlling the plurality of variable current gate drivers10of the variable current gate driver420employing a variable, controllable gate turn-on slew rate and a variable, controllable gate turn-off slew rate at every switching event to optimize system efficiency, reduce power losses, reduce overvoltage events or undercurrent events, avoid switching speeds that may otherwise lead to electro-magnetic interference, avoid change rates of voltage and/or current that may otherwise cause mechanical stresses in the electric machine, among other factors.

FIG.6schematically illustrates an embodiment of a variable current gate driver600that incorporates an embodiment of a variable current gate driver620to control transistor660, including controlling on and off slew rates of the transistor660. In one embodiment, the transistor660is an element of an inverter for driving an electric machine, but the concepts described herein are not so limited.

The variable current gate driver600includes an inverter controller630, a gate driver650, and a variable current gate driver620that includes a slew rate controller640.

The variable current gate driver620employs an embodiment of the variable current gate driver10described with reference toFIG.1to implement a variable, controllable gate turn-on slew rate and a variable, controllable gate turn-off slew rate at every switching event of the transistor660in a manner that optimizes system efficiency, reduces power losses, avoids switching speeds that may otherwise lead to electro-magnetic interference, reduces overvoltage events or undercurrent events, avoids change rates of voltage and/or current that may otherwise cause mechanical stresses in the electric machine, among other factors.

The inverter controller630receives information605that includes operating conditions, temperatures, voltages, etc., and determines commands for controlling the transistor660, and generates a slew rate command632and a PWM command634. The slew rate command632is input to the slew rate controller640, which generates an OFF-to-ON slew rate command653and an ON-to-OFF slew rate command654. The PWM command634is input to the gate driver650, which generates an ON command651and an OFF command652. The ON command651, the OFF command652, the OFF-to-ON slew rate command653, and the ON-to-OFF slew rate command654are input to the variable current gate driver620, which generates a control command622that is input to the gate of the transistor660, to control operation. Voltage feedback662is monitored by the variable current gate driver620.

The slew rate command632may be communicated to the slew rate controller640via a Serial Peripheral Interface (SPI) link, or directly, or via another communication link.

The variable current gate driver620may be implemented as an add-on ASIC, or integrated into another ASIC that includes the gate driver650to form a single chip implementation to reduce size, reduce cost, and improve manufacturability. The variable current gate driver620being implemented as an add-on ASIC permits circuit flexibility for ease of adoption into existing circuits.

FIG.7schematically illustrates an embodiment of a variable current gate driver700that incorporates an embodiment of a variable current gate driver720to control transistor760, including controlling on and off slew rates of the transistor760. In one embodiment, the transistor760is an element of an inverter for driving an electric machine, but the concepts described herein are not so limited.

The variable current gate driver700includes an inverter controller730, a gate driver750, and a variable current gate driver720that includes a slew rate controller740.

The variable current gate driver720employs an embodiment of the variable current gate driver10described with reference toFIG.1to implement a variable, controllable gate turn-on slew rate and a variable, controllable gate turn-off slew rate at every switching event of the transistor760in a manner that optimizes system efficiency, reduces power losses, avoids switching speeds that may otherwise lead to electro-magnetic interference, avoids change rates of voltage and/or current that may otherwise cause mechanical stresses in the electric machine, among other factors.

The inverter controller730receives information705that includes operating conditions, temperatures, voltages, etc., and determines commands for controlling the transistor760, and generates a slew rate command732and a PWM command734. The slew rate command732is input to the slew rate controller740, which generates an OFF-to-ON slew rate command753and an ON-to-OFF slew rate command754. The PWM command734is input to the gate driver750, which generates an ON command751and an OFF command752. The ON command751, the OFF command752, the OFF-to-ON slew rate command753, and the ON-to-OFF slew rate command754are input to the variable current gate driver720, which generates a control command722that is input to the gate of the transistor760, to control operation. In this embodiment, temperature724from the transistor760is monitored, and can be employed as part of the operation of the variable current gate driver720. Voltage feedback762is monitored by the variable current gate driver720.

The slew rate command732may be communicated to the slew rate controller740via a Serial Peripheral Interface (SPI) link, or directly, via analog or digital signals, or via another communication link.

The variable current gate driver720may be implemented as an add-on ASIC, or integrated into another ASIC that includes the gate driver750or integrated into another ASIC that includes the gate driver750to form a single chip implementation to reduce size, reduce cost, and improve manufacturability. The variable current gate driver720being implemented as an add-on ASIC permits circuit flexibility for ease of adoption into existing circuits.

FIG.8schematically illustrates an embodiment of a variable current gate driver800that incorporates an embodiment of a gate driver850to control transistor860, including controlling on and off slew rates of the transistor860. In one embodiment, the transistor860is an element of an inverter for driving an electric machine, but the concepts described herein are not so limited.

The variable current gate driver800includes an inverter controller830and gate driver850. The gate driver850includes the gate driver, an embodiment of a variable current gate driver, and an embodiment of a slew rate controller into a single ASIC. The gate driver850communicates with the transistor860and a resistor array845.

The variable current gate driver employs an embodiment of the variable current gate driver10described with reference toFIG.1to implement a variable, controllable gate turn-on slew rate and a variable, controllable gate turn-off slew rate at every switching event of the transistor860in a manner that optimizes system efficiency, reduces power losses, avoids switching speeds that may otherwise lead to electro-magnetic interference, avoids change rates of voltage and/or current that may otherwise cause mechanical stresses in the electric machine, among other factors.

The inverter controller830receives information805that includes operating conditions, temperatures, voltages, etc., and determines commands for controlling the transistor860, and generates a slew rate command832and a PWM command834, which are input to the gate driver850. The slew rate command832is used to generates an OFF-to-ON slew rate command853and an ON-to-OFF slew rate command854. The PWM command834is used to generate an ON command851and an OFF command852. The ON command851, the OFF command852, the OFF-to-ON slew rate command853, and the ON-to-OFF slew rate command854are input as a control command822that is input to the gate of the transistor860, to control operation. In this embodiment, temperature824from the transistor860is monitored, and can be employed as part of the operation of the variable current gate driver. Voltage feedback862is also monitored.

The gate driver850may be implemented as an ASIC to form a single chip implementation to reduce size, reduce cost, and improve manufacturability.

FIG.9schematically illustrates an embodiment of a variable current gate driver900that incorporates an embodiment of a variable current gate driver920to control a hybrid switch960, including controlling on and off slew rates of the hybrid switch960. In one embodiment, the hybrid switch960is composed as a first transistor961arranged in series with a second transistor963, wherein the first transistor961is one type of transistor, e.g., an IGBT device, and the second transistor963is a second type of transistor, e.g., a FET, a MOSFET, or another type of transistor other than an IGBT device. In one embodiment, the hybrid switch960is an element of an inverter for driving an electric machine, but the concepts described herein are not so limited.

Alternatively, the hybrid switch960is composed with the first transistor961being arranged in parallel with the second transistor963, wherein the first transistor961is one type of transistor, e.g., an IGBT device, and the second transistor963is a second type of transistor, e.g., a FET, a MOSFET, or another type of transistor other than an IGBT device.

The variable current gate driver900includes an inverter controller930, a gate driver950, and a variable current gate driver920that includes a slew rate controller940and a gate voltage regulator980.

The variable current gate driver920employs an embodiment of the variable current gate driver10described with reference toFIG.1to implement a variable, controllable gate turn-on slew rate and a variable, controllable gate turn-off slew rate at every switching event of the hybrid switch960in a manner that optimizes system efficiency, reduces power losses, avoids switching speeds that may otherwise lead to electro-magnetic interference, avoids change rates of voltage and/or current that may otherwise cause mechanical stresses in the electric machine, among other factors.

The inverter controller930receives information905that includes operating conditions, temperatures, battery and device voltages, etc., and determines commands for controlling the hybrid switch960, and generates a slew rate command932and a PWM command934. The gate voltage regulator980generates a first gate voltage command982and a second gate voltage command984. The slew rate command932is input to the slew rate controller940, which generates an OFF-to-ON slew rate command942and an ON-to-OFF slew rate command944. The PWM command934is input to the gate driver950, which generates an ON command951and an OFF command952.

The ON command951, the OFF command952, the OFF-to-ON slew rate command942, the ON-to-OFF slew rate command944, the first gate voltage command982, and the second gate voltage command984are input to the variable current gate driver920, which generates a first control command922that is input to the gate of the first transistor961of the hybrid switch960, and a second control command924that is input to the gate of the second transistor963of the hybrid switch960, to control operation. Voltage feedback962is monitored by the variable current gate driver920. The variable current gate driver920may be implemented as an add-on ASIC, or integrated into another ASIC that includes the gate driver950to form a single chip implementation to reduce size, reduce cost, and improve manufacturability. The variable current gate driver920being implemented as an add-on ASIC permits circuit flexibility for ease of adoption into existing circuits.

In one embodiment, the variable current gate driver may employ a discrete quantity of slew rates. These discrete values can be tuned to provide an optimal balance of inverter efficiency and heat generation while maintaining operation of the inverter switches. These discrete values and points can be implemented in a lookup table, and coupled to specific ranges of operating conditions. The operating conditions are used to select a target slew rate or resistance for a set of operating conditions. The variable current gate driver is configured to detect a voltage or current overshoot, and respond by changing the slew rate through a control loop or an active feedback loop.

When using the variable current gate driver, there can be controller, software, and hardware delays that can affect the responsiveness of the gate slew rate selection.

The variable current gate driver can be tuned to select and dynamically adjust the slew rate based on system latencies, delays, response times, fault events, and other factors, implementing either or both a time-based margin and a current-based margin for the gate tuning.

The variable current gate driver may be advantageously employed to control an inverter or converter systems to minimize switching losses, i.e., hard switching or zero-voltage switching power electronics, for electric vehicle (EV) and non-EV applications.

The use of the variable current gate driver enables the use of multiple gate slew rates, providing faster and smoother on and off switching that may achieve lower power loss and/or electromagnetic interference, or EMI.

The variable current gate driver includes a slew rate control strategy, which includes monitoring inverter signals and operating conditions (e.g., voltage, current, speed, torque, load, temperature, etc.), and selecting a target slew rate that optimizes efficiency, performance, and device protection simultaneously. The slew rate control strategy may include slew rate selection and control strategies that optimize switching losses in the inverter, avoid specific switching speeds that can exacerbate electromagnetic interference issues, control rates of change of current and/or voltage to mitigate specific mechanical or thermal faults, and provide flexibility in updating the switching speed using OTA (over the air) communication, facilitate feed-forward or feedback variable current gate driver controls to control and output multiple slew rates. The concepts can be implemented as an add-on ASIC for existing design, or as a stand-alone ASIC. The stand-alone ASIC may include features such as on-die temperature and voltage signals to control variable current gate driver slew rate, on-die current sense/current mirror to drive variable current gate driver slew rate, and monitoring vehicle operating conditions such as speed, torque, vehicle modes, etc.) to update switching slew rates.

The multiple slew rate capability of the variable current gate driver enables it to be used for a hybrid inverter, i.e., a i.e., an inverter that uses a combination of IGBT and MOSFET switches, etc., to optimize the slow rate control for different transistors (BJT, IGBT, MOSFET, HEMT, and JFET, etc.) in terms of their corresponding semiconductor properties (Si, SiC, GaN, or AlN, etc.) and device physics.

The detailed description and the drawings or figures are supportive and descriptive of the present teachings, but the scope of the present teachings is defined solely by the claims. While some of the best modes and other embodiments for carrying out the present teachings have been described in detail, various alternative designs and embodiments exist for practicing the present teachings defined in the claims.