Patent ID: 12261083

DETAILED DESCRIPTION

Referring toFIGS.1-2,FIGS.1-2illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention, in which the bottom portion of each figure illustrates a cross-section view for fabricating the semiconductor device and the top portion of each figure illustrates a top-view perspective for fabricating the semiconductor device. As shown inFIG.1, a substrate12is first provided, in which the substrate12is a semiconductor substrate made of semiconductor material including but not limited to for example silicon, germanium, silicon-germanium compounds, silicon carbide, or gallium arsenide. Next, a shallow trench isolation (STI)14made of silicon oxide is formed in the substrate12and active devices such as metal-oxide semiconductor (MOS) transistors16and a dielectric layer such as an interlayer dielectric (ILD) layer26is formed to cover the active devices. Specifically, planar or non-planar (such as FinFET) devices could be formed on the substrate12, in which the MOS transistors16could include gate structure elements such as gate structures18on the substrate12, spacers (not shown) adjacent to the gate structures18, source/drain regions20in the substrate12adjacent to two sides of the gate structures18, and selective epitaxial layer and/or silicides disposed on the surface of the source/drain regions20.

In this embodiment, each of the gate structures18could include a gate dielectric layer22and a gate electrode24, in which the gate dielectric layer22preferably includes silicon oxide and the gate electrode24could include polysilicon or metal. It should be noted that even though the gate structures18include gate electrodes24made of polysilicon in this embodiment, according to other embodiments of the present invention it would also be desirable to conduct a replacement metal gate (RMG) process to transform the polysilicon gate structures18into metal gates including work function metal layers, which is also within the scope of the present invention. Since the approach of using the RMG process to transform polysilicon gates into metal gates are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Preferably, the spacer could be a single spacer or a composite spacer. For instance, the spacer could further include an offset spacer (not shown) and a main spacer (not shown) and the spacer could be selected from the group consisting of SiO2, SiN, SiON, and SiCN. The source/drain region20and epitaxial layer could include different dopants or different material depending on the type of transistor being fabricated. For instance, the source/drain region20could include p-type or n-type dopants and the epitaxial layer could include SiGe, SiC, or SiP. In this embodiment, the ILD layer26could be made of silicon oxide, the ILD layer26could be disposed on the substrate12to cover the MOS transistors16, and the a plurality of contact plugs (not shown) could be disposed in the ILD layer26to electrically connect the source/drain regions20.

Next, a photo-etching process is conducted by first forming a patterned mask (not shown) such as patterned resist on the ILD layer26while exposing the top surface of part of the ILD layer26, and then conducting an etching process by using the patterned mask as mask to remove part of the ILD layer26for forming contact holes28,30directly on top of the gate structures18and/or source/drain regions20. Preferably, the contact holes28,30are formed without exposing the top surface of the gate structures18and the bottom surface of the contact holes28,30is slightly higher than the top surface of the gate structures18.

It should be noted that if viewed under a top view perspective as shown in the top portion ofFIG.1, the contact holes28,30preferably includes a contact hole28disposed in the center and a ring-shaped contact hole30surrounding the contact hole28while the ILD layer26is disposed in the middle to separate the two contact holes28,30. If viewed under a cross-section perspective as shown in the bottom portion ofFIG.1, the contact holes28,30formed after the aforementioned photo-etching process preferably includes a contact hole28in the middle and two contact holes30adjacent to two sides of the contact hole28, the bottom surface of the contact holes28,30is higher than the top surface of the gate structures18, and all three contact holes28,30are disposed directly above the gate structures18or if viewed from another perspective the leftmost and rightmost sidewalls of the contact holes30on two adjacent sides are aligned with or not exceeding the two sidewalls of each gate structure18.

Next, as shown inFIG.2, conductive materials including a barrier layer32selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and a metal layer34selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP) are deposited into the contact holes28,30, and a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of aforementioned barrier layer32and metal layer34for forming floating contact plugs36directly on top of each gate structure18.

It should be noted that since the conductive materials are deposited into the contact holes28,30shown inFIG.1for forming the floating contact holes36, the floating contact holes36formed at this stage whether being viewed under a top view perspective or cross-section perspective would share same pattern as the contact holes28,30shown inFIG.1. For instance, if viewed under a top view perspective as shown in the top portion ofFIG.2, the floating contact plug36includes an inner portion38disposed in the center and an outer portion40surrounding the inner portion38as the ILD layer26is disposed therebetween to separate the inner portion38and the outer portion40. If viewed under a cross-section perspective as shown in the bottom portion ofFIG.2, the floating contact plug36after being filled with conductive materials including the barrier layer32and metal layer34preferably includes an inner portion38in the middle and two outer portions40adjacent to two sides of the inner portion38, in which the bottom surface of the inner portion38is even with the bottom surface of the outer portions40, and both the inner portion38and the outer portions40are disposed directly on top or overlapping the gate structures18or if viewed from another perspective the outermost sidewalls of the outer portions40are aligned with or not surpassing the two sidewalls of each gate structure18.

According to an embodiment of the present invention, the distance between the top surface of the gate structures18and bottom surface of the floating contact plug36could be slightly less than, equal to, or greater than the overall height of each of the floating contact plugs36and if the distance between the top surface of the gate structures18and the bottom surface of the floating contact plugs were to be greater than the overall height of each floating contact plug36, the distance between the top surface of the gate structures18and the bottom surface of the floating contact plugs36could be twice or three times the overall height of each of the floating contact plugs36. It should further be noted that there is no additional element such as conductors, metals, or metal interconnections between the floating contact plugs36and the gate structures18except the ILD layer26. In other words, the bottom surface of the floating contact plugs36only contact the dielectric material including the ILD layer26without contacting any other conductive material directly.

Next, it would be desirable to conduct a metal interconnective process by first forming an inter-metal dielectric (IMD) layer on the floating contact plugs36and then forming metal interconnections (not shown) in the 1 MB layer, in which the metal interconnections if viewed under a cross-section perspective could directly contact or not contacting the top surface of floating contact plugs36, which are all within the scope of the present invention. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

Referring toFIGS.3-4,FIGS.3-4illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention, in which the bottom portion of each figure illustrates a cross-section view for fabricating the semiconductor device and the top portion of each figure illustrates a top-view perspective for fabricating the semiconductor device. As shown inFIG.3, it would be desirable to first form active devices such as MOS transistors16on the substrate12as shown inFIG.1and ILD layer26covering the MOS transistors16, and then conducting a photo-etching process to remove part of the ILD layer26for forming contact holes42directly on top of the gate structures18and/or source/drain regions20. Preferably, the contact holes42are formed without exposing the top surface of the gate structures18and the bottom surface of the contact holes42is slightly higher than the top surface of the gate structures18.

In contrast to the contact holes28,30if viewed under a top view perspective include a contact hole28disposed in the center and a ring-shaped contact hole30surrounding the contact hole28as shown inFIG.1, the contact hole42in this embodiment if viewed under a top view perspective as shown inFIG.3only include a ring-shape contact hole42surrounding the ILD layer26in the center. If viewed under a cross-section perspective as shown in the bottom portion ofFIG.3, the contact hole42preferably includes two contact holes42overlapping each of the gate structures18, in which the bottom surface of the contact holes42is higher than the top surface of the gate structures18and the two contact holes42are disposed directly on top of each gate structure18or if viewed from another perspective, the left sidewall of the left contact hole42and the right sidewall of the right contact hole42are both aligned with or not surpassing the two sidewalls of each of the gate structures18underneath.

Next, as shown inFIG.4, conductive materials including a barrier layer32selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and a metal layer34selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP) are deposited into the contact holes42, and a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of aforementioned barrier layer32and metal layer34for forming floating contact plugs36directly on top of each gate structure18.

Similar to the aforementioned embodiment, since the conductive materials are deposited into the contact holes42shown inFIG.3for forming the floating contact holes36, the floating contact holes36formed at this stage whether being viewed under a top view perspective or cross-section perspective would share same pattern as the contact holes42shown inFIG.3. For instance, if viewed under a top view perspective as shown in the top portion ofFIG.4, the floating contact plug36includes an outer portion40surrounding the ILD layer26in the center. If viewed under a cross-section perspective as shown in the bottom portion ofFIG.4, the floating contact plug36after being filled with conductive materials including the barrier layer32and metal layer34preferably includes two outer portions40, in which the bottom surfaces of the two outer portions40are coplanar and both the two outer portions40are disposed directly on top or overlapping the gate structures18or if viewed from another perspective, the left sidewall of the left portion40and the right sidewall of the right portion40are both aligned with or not surpassing the two sidewalls of each of the gate structures18underneath.

Moreover, according to an embodiment of the present invention, the distance between the top surface of the gate structures18and bottom surface of each floating contact plug36could be slightly less than, equal to, or greater than the overall height of each of the floating contact plugs36and if the distance between the top surface of the gate structures18and the bottom surface of the floating contact plugs were to be greater than the overall height of each floating contact plug36, the distance between the top surface of the gate structures18and the bottom surface of the floating contact plugs36could be twice or three times the overall height of each of the floating contact plugs36. It should further be noted that there is no additional element such as conductors, metals, or metal interconnections between the floating contact plugs36and the gate structures18except the ILD layer26. In other words, the bottom surface of the floating contact plugs36only contact the dielectric material including the ILD layer26without contacting any other conductive material directly.

Next, it would be desirable to conduct a metal interconnective process by first forming an inter-metal dielectric (IMD) layer on the floating contact plugs36and then forming metal interconnections (not shown) in the IMD layer, in which the metal interconnections if viewed under a cross-section perspective could directly contact or not contacting the top surface of floating contact plugs36, which are all within the scope of the present invention. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

Referring toFIG.5,FIG.5illustrates a 3-dimensional view of a floating contact plug36fabricating fromFIGS.1-2according to an embodiment of the present invention. As shown inFIG.5, in contrast to the floating contact plugs36shown inFIG.1were represented by rectangles, it would also be desirable to first conduct the photo-etching process shown inFIGS.1-2by forming contact holes and depositing conductive materials into the contact holes for forming floating contact plugs36and during the photo-etching process, adjust the pattern of the mask or conduct a calibrating procedure such as an optical proximity correction (OPC) process so that the resulting floating contact plug36reveals a substantially columnar or cone shape with circular top and bottom surfaces.

Preferably, the floating contact plug36includes an inner portion38and an outer portion40surrounding the inner portion38, the top surface of the inner portion38if viewed under a top view perspective includes a solid circle, and the top surface of the outer portion40if viewed under a top view perspective includes a circular ring. Similarly, the bottom surface of the inner portion38if viewed under a top view perspective includes a solid circle and the bottom surface of the outer portion40if viewed under a top view perspective includes a circular ring. Preferably, the area, size, diameter, and/or radius of the bottom surface of the inner portion38is less than the area, size, diameter, and/or radius of the corresponding top surface of the inner portion38, and the area, size, diameter, and/or radius of the bottom surface of the outer portion40is also less than the area, size, diameter, and/or radius of the corresponding top surface of the outer portion40.

Referring toFIG.6,FIG.6illustrates a 3-dimensional view of a floating contact plug36fabricating fromFIGS.3-4according to an embodiment of the present invention. As shown inFIG.6, it would also be desirable to first conduct the photo-etching process shown inFIGS.3-4by forming contact holes and depositing conductive materials into the contact holes for forming floating contact plugs36and during the photo-etching process, adjust the pattern of the mask or conduct a calibrating procedure such as an optical proximity correction (OPC) process so that the resulting floating contact plug36has a substantially columnar or cone shape. Preferably, the floating contact plug36could be disposed directly on top of the gate structure18and/or source/drain region20, and the body of the floating contact plug36includes a ring-shape outer portion40surrounding the ILD layer26in the center. Similar toFIG.5, the area, size, or diameter/radius of the bottom surface of the outer portion40of floating contact plug26in this embodiment is slightly less than the area, size, or diameter/radius of the top surface of the outer portion40.

Overall, it has been observed that in current fabrication of poly-gate or high-k metal transistor whether gate structures being active gates or dummy gates, contact plugs are formed in the later stage to connect to the gate structures or source/drain region and this design often induces a conduction in the original dummy gate thereby causing failure to the entire circuit. To resolve this issue, the present invention carries out the same fabrication for forming contact plugs directly on top of the gate structures and/or source/drain regions while replacing the contact plugs that are originally formed to penetrate the ILD layer and directly contact gate structures and/or source/drain regions with floating contact plugs. Preferably, the bottom surface of the floating contact plugs is higher than the top surface of the gate structures and no other conductive elements such as metal wirings are disposed between the gate structures and the floating contact plugs except the ILD layer. By using this design, it would be desirable to maintain the density of the contact plugs, provide a much more balanced stress, and reduce loading effect caused during CHIP process.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.