Patent ID: 12191346

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of the several presently contemplated embodiments of an integrated passive device and methods for fabrication of the same and is not intended to represent the only form in which such embodiments may be developed or utilized. The description sets forth the functions and features in connection with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions may be accomplished by different embodiments that are also intended to be encompassed within the scope of the present disclosure. It is further understood that the use of relational terms such as first and second and the like are used solely to distinguish one from another entity without necessarily requiring or implying any actual such relationship or order between such entities.

The embodiments of the present disclosure contemplate the creation of a metallurgical bonding layer between dissimilar metal materials in integrated passive devices, such as between aluminum and copper. It is envisioned that the aerial resistance of the device may be reduced, while improving stability and reliability.FIG.1is a cross-sectional view of a first embodiment of an integrated passive device10a, which may include a capacitor12. The capacitor12includes a device core14, which may also be referred to as a device core and is understood to be a metal sheet generally defined by a solid area metal center16, along with high surface area metal peripheries18on opposed sides of the solid area metal center16.

Relative to the orientation of the integrated passive device10ashown inFIG.1, there may be a high surface area metal upper periphery18athat is above the solid area metal center16, and a high surface area metal lower periphery18bthat is below the solid area metal center16. The device core14may thus be defined by an upper or first side20a, and a lower or second side20bopposite the first side20a. The device core14, and hence both the solid area metal center16and the high surface area metal periphery18may be aluminum, tantalum, or any other material suitable for use in capacitor cores. Although the solid area metal center16and the high surface area metal periphery18may be depicted as separate layers or sheets, it is understood to be a single contiguous structure with a gradual boundary between the two. As a single sheet of aluminum or other metal material, the device core14is also defined by two outer surfaces, including a first or upper core outer surface21a, and an opposed second or lower core outer surface21b.

The device core14may thus be an etched aluminum foil, with the high surface area metal periphery including various tunnels, voids, and/or recessed regions that provide a large surface area with continuous electrical conductivity. Optionally, instead of or in addition to etched foil, the device core14may be comprised of sintered aluminum powder supported by and in mechanical and electrical contact with an aluminum foil substrate. Further alternative techniques such as glancing angle deposition or other etching methods may be utilized to build the high surface area metal periphery18. Embodiments in which there are two high surface area metal peripheries18a,18bare depicted, though alternative embodiments in which there is a single high surface area metal periphery18are also contemplated.

The capacitor12includes conducting polymer layers22that are disposed on each of the sides20of the device core14. In further detail, there is a first or upper conducting polymer layer22athat is adjacent to the first side20a, and a second or lower conducting polymer layer22bthat is adjacent to the second side20b. The first conducting polymer layer22ais defined by an interior face24a-1that is a planar abutting relationship with the first core outer surface21a, and an opposed exterior face24a-2. The second conducting polymer layer22bis similarly defined by an interior face24b-1that is in a planar abutting relationship with the second core outer surface21b, and an opposed exterior face24b-2. In the context of these features, the device core14, and specifically the middle of the solid area metal center16, may be considered the center of the laminate assembly, such that interior or inner faces refer to those that are toward such center, while exterior or outer faces refer to those are away from such center.

The conducting polymer layers22may be, for example, poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PDOT: PSS). It will be appreciated by those having ordinary skill in the art that any other suitable conducting polymer material may be substituted, as this particular instance of utilizing PDOT: PSS is by way of example only and not of limitation. Other examples of conducting polymers include polypyrrole, polythiophene, polyaniline, polyacetylene, polyphenylene, poly(p-phenylene-vinylene), and poly(3-hexylthiophene-2,5-diyl (P3HT).

Disposed on each of the conducting polymer layers22are conducting metal layers26, and interposed between these two layers may be carbon coating layers28. On the upper half of the device structure, a first carbon coating layer28aexists between the first conducting polymer layer22aand a first conducting metal layer26a. In turn, the first conducting metal layer26ahas a planar structure defined by an interior or bottom surface30a-1, and an opposed exterior or top surface30a-2. The carbon coating layers28may be graphite, a carbon-based ink, a polymeric binder, sputtered carbon, or carbon-polymer composites, and have any suitable thickness.

The interior surface30a-1abuts against the first carbon coating layer28aand faces the exterior face24a-2of the first conducting polymer layer22a. This same structure also exists on the lower half, with a second carbon coating layer28bbetween a second conducting metal layer26band the second conducting polymer layer22b. The second conducting metal layer26blikewise has a planar structure defined by an interior or top surface30b-1, and an opposed exterior or bottom surface30b-2. The interior surface30b-1abuts against the second carbon coating layer28band faces the exterior face24b-2of the second conducting polymer layer22b. The conducting metal layers26may be copper foil, electroplated copper, or any other conductive material that may be formed to a planar structure as shown in the figures.

The capacitor12may also include landing pads32that are positioned onto the conducting metal layers26. Again, the upper half of the device structure includes an upper or first landing pad32a, while the lower half includes a lower or second landing pad32b. The landing pads32are contemplated to be fabricated from copper paste or other like material and is different from the conductive material of the conducting metal layers26. Although the present disclosure makes reference to the landing pads32and the formation thereof, it is to be understood that any other step to form an electrode contact, such as electrolytic plating and the like may be substituted without departing from the scope of the present disclosure. In this regard, the embodiments of the disclosure are intended to encompass any electrode contact, so any specific reference to the landing pads32refers to any such alternative structure. An electrical connection is understood to be made between the landing pads32and the conducting metal layers26, with the paste material adhering to the exterior surfaces30a-2,30b-2of the first and second conducting metal layers26a,26b, respectively.FIG.1depicts the landing pads32being generally defined by a rectangular portion32-1and a trapezoidal portion32-2, though this is by way of example only and not of limitation.

The foregoing laminate structure may be encapsulated within an insulating dielectric34, with the encapsulate structure being defined by a top surface36and a bottom surface38. By way of example only and not of limitation, the insulating dielectric34may be an electrically insulating polymer material which may optionally be Ajinomoto® Buildup Film (ABF), benzocyclobutene (BCB), and so forth. An exterior surface40aof the upper or first landing pad32amay be substantially coplanar with the top surface36of the encapsulate structure, and an exterior surface40bof the lower or second landing pad32bmay be substantially coplanar with the bottom surface38.

Disposed on the outer extremities of the laminate structure are terminal metal layers42. In particular, a first terminal metal layer42afaces the first landing pad32aas well as the encapsulate structure. The first terminal metal layer42ahas an exposed top surface44and an opposed interior bottom surface46that abuts against the exterior surface40aof the first landing pad32aand the top surface36of the encapsulate structure. The second terminal metal layer42bfaces the second landing pad32band the encapsulate structure and is defined by an exposed bottom surface48and an opposed interior top surface50that abuts against the exterior surface40bof the second landing pad32band the bottom surface38of the encapsulate structure. The terminal metal layers42are understood to be planar metallic structures, preferably copper foil or electroplated copper, and various patterns may be etched to separate one terminal52from another, e.g., a first terminal52aand a second terminal52b.

In accordance with various embodiments of the present disclosure, at least the conducting polymer layers22define a pattern of one or more direct recesses53to the device core14. Such direct recesses53are understood to be a part of larger openings for vias54, which may also be referred to as conductive structures.FIG.1illustrates two types of vias, including a pair of top and bottom blind vias54a-1and54a-2, and a through via54b. The top blind via54a-1extends from the top surface36to the device core14, and specifically to the solid area metal center16. The bottom blind via54a-2extends from the bottom surface38to the device core14. The through via54bextends the entire thickness of the encapsulate structure, from the top surface36to the bottom surface38. As the vias54are formed in the laminate structure, it follows that the conducting metal layers26and the carbon coating layers28likewise define recesses56that define a portion of the vias54, and are substantially overlapping with the direct recesses53defined by the conducting polymer layers22.

The blind vias54aare understood to reach the solid area metal center16, so the device core14and the high surface area metal periphery18likewise define recesses58that substantially overlap with the direct recesses53and the recesses56in the conducting metal layers26/carbon coating layers28. As the laminate structure comprised of the device core14, the conducting polymer layers22, the conducting metal layers26/carbon coating layers28are encapsulated in the insulating dielectric34, so the recesses53,56,58are partly filled with the same. The insulating dielectric34may therefore define recesses60that are filled by the vias54. The recess58extends partially into the solid area metal center16, and defines an inset portion74. In relation to the top blind via54a-1, there is an inset portion74athat extends downward into the solid area metal center16, while in relation to the bottom blind via54b-1, there is an inset portion74bthat extends upward to the solid area metal center16.

The vias54are formed of a conductive material such as the aforementioned copper paste, though any other suitable conductive material form such as electrolytic copper, or other conductive material such as silver may be substituted without departing from the scope of the present disclosure. The conductive material, e.g., copper, silver, etc., may be more generally referred to as a second material, which is different from the first material utilized in the device core14, e.g., aluminum.

The blind vias54aare connected to and establish an electrical connection with the solid area metal center16of the device core14, as illustrated. The solid area metal center16thus has a first or top surface62a, and a second or bottom surface62b. In the regions corresponding to the inset portion74, however, there is defined a top inset surface62a-1and a bottom inset surface62b-1.

The blind vias54aare understood to be formed of a copper paste material, while the device core14is aluminum. In order to improve the metallurgical bonding between these two structures, there may be a bonding material layer66that is generally coextensive with the patterns of the recesses53,56,58(or more generally the recess60). Thus, there may be a first bonding material layer66abetween the solid area metal center16and the top blind via54a-1, and a second bonding material layer66bbetween the solid area metal center16and the bottom blind via54a-2. In further detail, the first bonding material layer66ahas a first or via-side surface66a-1and a second or core-side surface66a-2, and the second bonding material layer66bhas a first or via-side surface66b-1and a second or core-side surface66b-2. The via-side surface66a-1of the first bonding material layer66afaces a bottommost face of the top blind via54a-1, referred to as a first via core-side surface62a. The via-side surface66b-1of the second bonding material layer66bfaces an uppermost face of the bottom blind via54b-1, referred to as a second via core-side surface62b. Each of the via-side surfaces66a-1and66b-1of the first and second bonding material layers66a,66b, respectively, extend beyond the limits of the top and bottom blind vias54a-1,54b-1, respectively. The first core-side surface66a-2is generally coplanar with the top inset surface62a-1and the second core-side surface66b-2is generally coplanar with the bottom inset surface62b-1.

The bonding material layers66are not understood to extend the entire width of the inset portion74. Accordingly, while some segments of the core-side surface66a-2,66b-2are coextensive with the top inset surface62a-1and bottom inset surface62b-1, respectively, the insulating dielectric34further defines a shoulder surface76athat faces the core16and is coplanar with the top inset surface62a-1, and a shoulder surface76bthat faces the core16and is coplanar with the bottom inset surface62b-1. There may also be an angled connecting surface78abetween the shoulder surface76aand the top surface62a, and another angled connecting surface78bbetween the shoulder surface76band the bottom surface62b.

As will be described in further detail below, the bonding material layer66may be a vapor phase metal that is deposited on to the top and bottom surfaces62a,62b. The bonding material layer66may thus spatially extend beyond the surface area of the interface surfaces of the blind vias54a, and may be partially encapsulated by the insulating dielectric34. As a result of the bonding material layer66, a more stable and reliable interface between the copper structure and the aluminum structure, i.e., of dissimilar metals, is understood to be possible.

FIG.2shows a cross-sectional view of a second embodiment of the integrated passive device10b, including the capacitor12that is substantially the same as in the first embodiment10a, described above. Accordingly, the integrated passive device10bincludes the device core14generally defined by the solid area metal center16and high surface area metal peripheries18. As in the first embodiment, the capacitor12includes the conducting polymer layers22that are disposed on each side of the device core14. Furthermore, disposed on each of the conducting polymer layers22are the conducting metal layers26, and interposed between these two layers may be the carbon coating layers28. The landing pads32are positioned onto the conducting metal layers26, though in the second embodiment10b, the rectangular portion32-1may be structurally separated from the trapezoidal portion32-2. The description of the first embodiment of the integrated passive device10aincluded additional details regarding various surfaces of the foregoing components of the laminate structure but will not be repeated in connection with the second embodiment10bfor the sake of brevity, unless otherwise pertinent to the features thereof differing from the first embodiment10a. However, it is to be understood that the second embodiment10bhas the same surfaces and relationships between such surfaces as in the first embodiment10a.

The foregoing laminate structure, excluding the trapezoidal portion32-2of the landing pads32, may be encapsulated within the insulating dielectric34. The resultant encapsulate structure may be defined by the top surface36and the bottom surface38.

On the outer extremities of the laminate structure, the second embodiment10bincorporates the same terminal metal layers42, including the first terminal metal layer42aand the second terminal metal layer42b. The terminal metal layers42abut against the landing pads32, as well as the encapsulate structure.

In the second embodiment of the integrated passive device10b, the conducting polymer layers22also define the pattern of one or more direct recesses53to the device core14, and are parts of larger openings for the vias54. There are again two types of vias, including the pair of top and bottom blind vias54a-1and54a-2, and the through via54b. The top blind via54a-1extends from the top surface36to the device core14, and specifically to the solid area metal center16. The bottom blind via54a-2extends from the bottom surface38to the device core14. The through via54bextends the entire thickness of the encapsulate structure, from the top surface36to the bottom surface38. The carbon coating layers28likewise define recesses56that are a part of the vias54, and are substantially overlapping with the direct recesses53defined by the conducting polymer layers22. The device core14and the high surface area metal periphery18likewise define recesses58that substantially overlap with the direct recesses53and the recesses56in the conducting metal layers26/carbon coating layers28. With the laminate structure of the device core14, the conducting polymer layers22, the conducting metal layers26/carbon coating layers28being encapsulated in the insulating dielectric34, the recesses53,56, and58are partly filled. The insulating dielectric34thus defines the recesses60filled by the vias54.

Whereas the first embodiment10aincorporated a bonding material layer at only the interface between the copper via54and the aluminum device core14, the second embodiment10bcontemplates the bonding material layer66extending across the interfaces between the insulating dielectric34and the vias54. As the rectangular portion32-1is separate from the trapezoidal portion32-2, the bonding material layer66extends between these two sections of the landing pad32. Along these lines, the bonding material layer66extends across the surfaces defining the recesses60, as well as the terminal metal layers42. The different structures of the bonding material layer66in the first embodiment10aand the second embodiment10bare understood to be the result of different fabrication methods, as will be described more fully below. The first embodiment10ais fabricated with a “front end” process in which the bonding material layer66is deposited after the recesses60for the vias54are patterned, before encapsulating the laminate structure with the insulating dielectric34. The second embodiment10bis fabricated with a “back end” process where the laminate structure is assembled and encapsulated, and then the bonding material layer66is deposited.

With reference to the flowchart ofFIG.3as well as the cross-sectional views of the first embodiment of the integrated passive device10ain various stages of completion in FIGS.4A-4H, the front-end process begins with a step100-1of fixing the conducting polymer layers22onto the device core14. As discussed above, the device core14may be a double-sided foil of aluminum, with the solid area metal center16and the high surface area metal peripheries18a,18baround the solid area metal center16, andFIG.4Abest illustrates the state of the device core14prior to the step100-1of fixing the conducting polymer layers22onto the device core.FIG.4B, in turn, illustrates the conducting polymer layers22fixed onto the device core14, along with the carbon coating layers28applied to the conducting polymer layers22.

Next, the method continues to a step100-2of etching patterns of direct recesses53into at least the conducting polymer layers22to the device core14. As shown inFIG.4C, the direct recesses53extend through the high surface area metal peripheries18, and to the solid area metal center16. The recesses58defined thereby are understood to be substantially coextensive with the direct recesses53on the conducting polymer layers22and the recesses56defined by the carbon coating layers28. Each of these recesses53,56, and58may be collectively referred to as a laminate structure recess59. Generally, the recesses are etched at any location in which the first metal material, e.g., aluminum, is to bond with the second metal material, e.g., copper.

After this etching step, the method continues with a step100-3of applying a vapor phase metal bonding material to at least an exposed surface of the device core14. The outcome of this step is shown inFIG.4D, where the bonding material layer66is disposed on the solid area metal center16, and the sidewalls of the high surface area metal peripheries18, the conducting polymer layers22, and the carbon coating layers28.

As shown inFIG.4E, the method proceeds to a step100-4of etching edge regions68of the laminate structure recesses59. In accordance with some embodiments of the present disclosure, this etching step may also include defining a through hole or slot70. The etching may be performed by a suitable laser, and so step100-4may also be referred to as a laser patterning step. Any other material removal apparatus may be substituted without departing from the present disclosure.

FIG.4Fillustrates the completion of a step100-5of forming the landing pads32onto the laminate structure or the electrode contacts more generally as referenced above, as well as a step100-6of laminating the insulating dielectric34. This may be achieved through the application of a copper foil, or electrolytic plating, and so on. As shown, the entirety of the laminate structure recess59in the case of the blind vias, and the recess80in the case of the through hole or slot70, is not filled. Rather, the recesses60afor the blind vias and the recess60bfor the through via54bremain.

In a step100-7, the completion of which results in a state as shown inFIG.4G, the recesses60a,60bare filled with the second conductive metal material, e.g., copper paste, to define the blind vias54aand the through via54b. The copper paste may be deposited into the recesses60, and may be sintered, that is, heated without reaching the melting point, with the paste material being compacted and forming the structure of the vias54.FIG.4Galso illustrates the completion of a step100-8of laminating the first terminal metal layer42aand the second terminal metal layer42bonto the insulating dielectric34. As a result, the terminal metal layers42may be connected to the landing pads32and the vias54.

FIG.4Hshows the final form of the first embodiment of the integrated passive device10afollowing a terminal metal patterning step. The terminal metal layers42may thus be separated into individual terminals72, including a first terminal72athat is connected to the top blind via54a-1, a second terminal72bis that is connected to the bottom blind via54a-2, a third terminal72cconnected to the through via54band the first landing pad32a, and a fourth terminal72dlikewise connected to the through via54band the second landing pad32b.

The flowchart ofFIG.5shows the steps involved in various embodiments of the back-end process for fabricating the second embodiment of the integrated passive device10b. The cross-sectional views ofFIGS.6A-6Jshow the device in various stages of completion following these steps. The method includes a step200-1of etching patterns of direct recesses53into a device laminate structure. As shown inFIG.6A, the device core14may be a double-sided foil of aluminum with the solid area metal center16and the high surface area metal peripheries18a,18b.FIG.6Billustrates the laminate structure following a precursor step in which the conducting polymer layers22are fixed onto the device core14, and the carbon coating layers28are applied thereto. Layered onto the carbon coating layers28are the conducting metal layers26.

In further detail, this etching step200-1according to one embodiment involves the creation of the direct recesses53in the conducting polymer layers22to the device core14, and through the high surface area metal peripheries18to the solid area metal center16. In another embodiment, the etching step200-1may be preceded by an optional step200-0of electrolytically plating to form subsequent contacts. The recesses58defined thereby are understood to be substantially coextensive with the direct recesses53on the conducting polymer layers22, the recesses56defined by the carbon coating layers28, and recesses63defined by the conducting metal layers26. Each of these recesses53,56,58, and63may be collectively referred to as a laminate structure recess59. The recesses are etched at any location in which the first metal material, e.g., aluminum, is to bond with the second metal material, e.g., copper. These etching steps may thus be referred to as patterning. The embodiments of the present disclosure contemplate both through vias and blind vias, with a first laminate structure recess59aand a second laminate structure recess59bdefining the pathway for the blind vias. A third laminate structure recess59cdefines the pathway for the through via. Additional details of the via structures will be described below.

FIG.6Dillustrates the completion of a step200-2of forming electrode contacts, and more specifically in the context of this embodiment, depositing the landing pads32onto the laminate structure, or at least the rectangular portion32-1thereof. Thereafter, in a step200-3, the method includes depositing the insulating dielectric34, encapsulating the entirety of the device laminate structure fabricated up to that point, including the device core14, the conducting polymer layers22, the carbon coating layers28, and the landing pads32. In contrast to the front-end process, the laminate structure recesses59are filled with the insulating dielectric34.

Referring now toFIG.6Fand the flowchart ofFIG.5, the method continues with a step200-4of drilling through a portion of the insulating dielectric34to define the recesses60for the vias54. Like the laminate structure recesses59discussed above, a recess60adefined in the insulating dielectric34corresponding to the first laminate structure recess59ais for a first blind via, while a recess60bdefined in the insulating dielectric34corresponding to the second laminate structure recess59bis for a second blind via. A recess60cdefined in the insulating dielectric34corresponds to the third laminate structure recess59cfor the through via. Additionally, residual dielectric material is removed from regions proximal to the landing pads32, thus defining landing pad recesses61in the insulating dielectric34.

After this step, the method continues with a step200-5of applying a vapor phase metal bonding material to at least an exposed surface of the device core14, though in this embodiment, this vapor deposition takes place around the entirety of the laminate structure fabricated up to this point. The outcome of this step is shown inFIG.6G, where the bonding material layer66is disposed on the outer periphery of the insulating dielectric34and those exposed portions of the solid area metal center16of the device core14and the landing pads32. The vapor deposition is contemplated to remove the dielectric residues and bonds directly to the first metal material.

In a step200-6, the completion of which results in a state as shown inFIG.6H, the recesses60a,60bare filled with the second conductive metal material, e.g., copper paste, to define the blind vias54aand the through via54b. Additionally, the landing pad recesses61are similarly filled with the second conductive metal material. The copper paste may be deposited into the recesses60,61, and may be sintered, that is, heated without reaching the melting point, with the paste material being compacted and forming the structure of the vias54and the trapezoidal portion32-2of the landing pads32.

FIG.6Iillustrates the completion of a step200-7of forming the first terminal metal layer42aand the second terminal metal layer42bonto the bonding material layer66, the vias54, and the landing pads32. This may be achieved with the application of a copper foil, electrolytic plating, and so on. As a result, the terminal metal layers42may be connected to the landing pads32and the vias54.

FIG.6Jshows the final form of the second embodiment of the integrated passive device10bfollowing a terminal metal patterning step. The terminal metal layers42may thus be separated into individual terminals72, including a first terminal72athat is connected to the top blind via54a-1, a second terminal72bis that is connected to the bottom blind via54a-2, a third terminal72cconnected to the through via54band the first landing pad32a, and a fourth terminal72dlikewise connected to the through via54band the second landing pad32b.

The particulars shown herein are by way of example and for purposes of illustrative discussion of the embodiments of the integrated passive device and methods for fabrication of the same and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects. In this regard, no attempt is made to show details with more particularity than is necessary, the description taken with the drawings making apparent to those skilled in the art how the several forms of the present disclosure may be embodied in practice.