Patent ID: 12219783

DETAILED DESCRIPTION

Thin film transistors are disclosed, such as may be incorporated in memory structures, memory cells, arrays including such memory cells, memory devices, switching devices, and other semiconductor devices including such arrays, systems including such arrays, and methods for fabricating and using such memory structures are also disclosed. Embodiments of the disclosure include a variety of different memory cells (e.g., volatile memory, non-volatile memory) and/or transistor configurations. Non-limiting examples include random-access memory (RAM), read-only memory (ROM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), flash memory, resistive random-access memory (ReRAM), conductive bridge random-access memory (conductive bridge RAM), magnetoresistive random-access memory (MRAM), phase change material (PCM) memory, phase change random-access memory (PCRAM), spin-torque-transfer random-access memory (STTRAM), oxygen vacancy-based memory, programmable conductor memory, ferroelectric random-access memory (FE-RAM), reference field-effect transistors (RE-FET), etc.

Some memory devices include memory arrays exhibiting memory cells arranged in a cross-point architecture including conductive lines (e.g., access lines, such as word lines) extending perpendicular (e.g., orthogonal) to additional conductive lines (e.g., data lines, such as bit lines). The memory arrays can be two-dimensional (2D) so as to exhibit a single deck (e.g., a single tier, a single level) of the memory cells, or can be three-dimensional (3D) so as to exhibit multiple decks (e.g., multiple levels, multiple tiers) of the memory cells. Select devices can be used to select particular memory cells of a 3D memory array. Embodiments additionally may include thin field transistors utilized in non-access device implementations. Non-limiting examples of which include deck selector devices, back end of line (BEOL) routing selector devices, etc.

Embodiments of the present disclosure may include different configurations of transistors (e.g., thin film transistors (TFT)), including vertically oriented transistors, horizontally oriented transistors (i.e., planar), etc. The memory cells include hybrid access transistors formed different materials exhibiting different bandgap and mobility properties.

For example, in some embodiments at least a portion of the channel region may include a channel material that is formed from an amorphous oxide semiconductor. Non-limiting examples may include zinc tin oxide (ZTO), IGZO (also referred to as gallium indium zinc oxide (GIZO)), IZO, ZnOx, InOx, In2O3, SnO2, TiOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, and other similar materials.

As used herein, the term “substrate” means and includes a base material or construction upon which components, such as those within memory cells, are formed. The substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. While materials described and illustrated herein may be formed as layers, the materials are not limited thereto and may be formed in other three-dimensional configurations. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates or silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation or other semiconductor or optoelectronic materials, such as silicon-germanium (Si1-xGex, where x may be, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The substrate may be doped or may be undoped. Furthermore, when reference is made to a “substrate” in the following description, previous process stages may have been utilized to form regions or junctions in the base semiconductor structure or foundation.

As used herein, spatially relative terms, such as “beneath” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left”, “right,” and the like, may be used for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative tens are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, reference to an element as being “on” or “over” another element means and includes the element being directly on top of, adjacent to, underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to, underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, it should be understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not limit the quantity or order of those elements, unless such limitation is explicitly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements may be employed there or that the first element must precede the second element in some manner. Also, unless stated otherwise a set of elements may comprise one or more elements.

As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the term “configured” refers to a size, shape, material composition, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, or even at least 99.9% met.

The illustrations presented herein are not meant to be actual views of any particular component, structure, device, or system, but are merely representations that are employed to describe embodiments of the present disclosure. Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as limited to the particular shapes or regions as illustrated but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box shape may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. Reference will now be made to the drawings, where like numerals refer to like components throughout. The drawings are not necessarily drawn to scale or proportionally for the different materials.

The following description provides specific details, such as material types and processing conditions, in order to provide a thorough description of embodiments of the disclosed devices and methods. However, a person of ordinary skill in the art will understand that the embodiments of the devices and methods may be practiced without employing these specific details. Indeed, the embodiments of the devices and methods may be practiced in conjunction with conventional semiconductor fabrication techniques employed in the industry.

The fabrication processes described herein do not form a complete process flow for processing semiconductor device structures. The remainder of the process flow is known to those of ordinary skill in the art. Accordingly, only the methods and semiconductor device structures necessary to understand embodiments of the present devices and methods are described herein. Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, or physical vapor deposition (“PVD”). Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. Unless the context indicates otherwise, the removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching, abrasive planarization, or other known methods.

A semiconductor device is disclosed. The semiconductor device comprises a hybrid transistor including a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a low bandgap high mobility material relative to the channel material that is high bandgap low mobility material.

Another semiconductor device is disclosed. The semiconductor device comprises a hybrid transistor including a channel region defined by a length of an adjacent gate electrode, and a drain region and a source region disposed on opposing ends of the channel region. The channel region includes at least a high bandgap low mobility material. The drain region and the source region each include at least a low bandgap high mobility material.

FIG.1Ais a cross-sectional front view of a schematic of a hybrid thin film transistor100according to an embodiment of the present disclosure.FIG.1Bis a cross-sectional perspective view of the thin film transistor100ofFIG.1A(for ease of illustration, first insulative material160is not depicted inFIG.1B).FIG.1AandFIG.1Bwill be referred to together herein.

The transistor100includes a source region120, a drain region150, and a channel region140supported by a substrate112. The channel region140may be operably coupled with both the source region120and the drain region150. The transistor100may have a generally vertical orientation with the source region120, the channel region140, and the drain region150extending in a stack substantially vertically from the substrate112. In other words, the transistor100may be a vertical transistor (i.e., a transistor in a vertical orientation).

The source region120may include a source material122coupled with a first conductive material118acting as a source contact. The first conductive material118may be disposed on a primary surface114of the substrate112. In some embodiments, the first conductive material118may be disposed across the majority (e.g., entirety) of the primary surface114of the substrate112. Alternatively, the first conductive material118may be formed within the substrate112, with an upper surface of the first conductive material118occupying the same plane defined by the primary surface114of the substrate112. In some embodiments, one or more barrier materials may be provided between the first conductive material118and the substrate112.

The drain region150may include a drain material152coupled with a second conductive material148acting as a drain contact. In embodiments in which the transistor100is vertically disposed relative to the primary surface114of the substrate112, the second conductive material148may be formed atop the drain material152.

The channel region140may include a channel material142coupled between the source material122and the drain material152. The materials122,142,152may further be situated at least partially within a first insulative material160as shown inFIG.1A(not shown inFIG.1B). The first insulative material160may surround and support the transistor100. The first insulative material160may be a conventional interlayer dielectric material. A second insulative material144may isolate the channel material142from a gate electrode126formed of a third conductive material124. The second insulative material144may be provided along sidewalls of the channel material142, and in some embodiments along the sidewalls of the source material122and the drain material152. The second insulative material144may be formed of a conventional gate insulator material, such as an oxide (e.g., silicon dioxide (SiO2), high-K materials such as HfO2, AlOx, or combinations thereof). The second insulative material144may also be referred to as a “gate oxide.”

The gate electrode126is configured to operatively interconnect with the channel region140to selectively allow current to pass through the channel region140when the transistor100is enabled (i.e., “on”). However, when the transistor100is disabled (i.e., “off”), current may leak from the drain region150to the source region120as indicated by arrow146. The gate electrode126may be configured as an access line (e.g., a word line) arranged perpendicular to the first conductive material118, which may be configured as a data/sense line (e.g., a bit line).

The transistor100may be a hybrid transistor in which the source material122, the channel material142, and the drain material152are different types of materials exhibiting different levels of mobility. In some embodiments, the source material122and the drain material152may be formed from a lower bandgap higher mobility material relative to the channel material142formed from a higher bandgap lower mobility material. For example, the source material122and the drain material152may be formed from a doped semiconductor material (e.g., Si, SiGe, Ge, SiCo, Transition Metal Dichalcogenides (TMD), etc.) and the channel material142may be formed from an oxide semiconductor material (e.g., ZTO, IGZO, IZO, ZnOx, InOx, In2O3, SnO2, TiOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, and ZrxZnySnzOa, InGaSiO, and other similar materials, etc.). The doped semiconductor material may include N-doped materials or P-doped materials. The doping may be uniform or non-uniform as desired. In some embodiments, the source material122and/or the drain material152may be formed from low bandgap metal oxides (e.g., doped or undoped).

The hybrid transistor100includes a channel material142that has a high valence band offset relative to the source and drain materials122,152, which may suppress tunneling from the valence band inside the channel region140that may reduce the gate induced drain leakage (GIDL) similar to a conventional transistor with a uniform amorphous oxide semiconductor material extending between two conductive contacts. However, the source and drain materials122,152may have higher mobility than the channel material142, which may improve contact resistance (RCON) with the source and drain contacts (conductive materials118,148) and also improve the on current (ION) relative to conventional devices. Thus, the hybrid transistor100may exhibit the combined advantage of having a high on current (ION) and low off current (IOFF) relative to conventional devices. In addition, the gate length (LG) as well as the lengths of the different materials122,142,152may be selected for tuning other device metrics (e.g., DIBL, SVTM etc.) as desired.

In some embodiments, the materials122,142,152may be discrete regions as shown. As a result, within each region, the respective material122,142,152may be at least substantially uniform with a distinct transition therebetween. In some embodiments, the materials122,142,152may blend together—particularly at the transitions—before becoming substantially uniform. In some embodiments, the bandgap from the channel material142to the source and drain materials122,152may be uniformly graded. While the length of the channel material142is shown as being approximately equal to the gate electrode126the length of the channel material142may be shorter or longer as desired. In some embodiments, it may be desirable to shorten the length of the channel material142relative to the lengths of the source and drain materials122,152to increase the on current (ION) while still maintaining an acceptable off current (IOFF).

Each of the first conductive material118and the second conductive material148may be formed of one metal, of a mixture of metals, or of layers of different metals. For example, without limitation, the first conductive material118and/or the second conductive material148may be formed of titanium nitride, copper, tungsten, tungsten nitride, molybdenum, other conductive materials, and any combination thereof.

In some embodiments, the second conductive material148may be provided in lines parallel with the third conductive material124of the gate electrode126. The second conductive material148may be formed in aligned segments (for example, as shown inFIG.4), as, for example, when more than one memory cell is to be formed of the second conductive material148. Each aligned segment of the second conductive material148may be coupled to a drain region150of a separate memory cell. Segmentation of the second conductive material148may provide electrical isolation of each segment of second conductive material148from one another.

The third conductive material124of the gate electrode126may be formed from one metal, from a mixture of metals, or from layers of different metals. For example, without limitation, the third conductive material124of the gate electrode126may be formed of titanium nitride. A barrier material (not shown) may be provided between the gate electrode126and surrounding components. The third conductive material124forming the gate electrode126may be isolated from the first conductive material118by the first insulative material160.

For embodiments in which the transistor100is incorporated within a memory structure such as a memory cell, a storage element (not shown) may be in operative communication with the transistor100to form the memory cell. The memory cell comprises an access transistor that comprises a source region, a drain region, and a channel region comprising different material types for the channel material relative to the source material and the drain material. The different material types may include different regions that are either lower bandgap higher mobility or higher bandgap lower mobility relative to each other. The memory cell further comprises a storage element in operative communication with the transistor. Different configurations of storage elements are contemplated as known by those skilled in the art. For example, storage elements (e.g., capacitors) may be configured as container structures, planar structures, etc. The access transistor enables a read and/or write operation of a charge stored in the storage element. The transistor100may be incorporated as an access transistor or other selector device within a memory device (e.g., a resistance variable memory device, such as a RRAM device, a CBRAM device, an MRAM device, a PCM memory device, a PCRAM device, a STTRAM device, an oxygen vacancy-based memory device, and/or a programmable conductor memory device), such as in a 3D cross-point memory array.

A method of operating the hybrid transistor is also disclosed. The method comprises enabling a hybrid transistor by applying a gate voltage to a gate electrode to cause a drive current to flow through a channel region coupled between a source region and a drain region, the channel region including a high bandgap low mobility material relative to the source region and drain region each including a low bandgap high mobility material.

In particular, the transistor100may be selectively turned to an “on” state (i.e., enabled) to allow current to pass through a first low bandgap high mobility material, the high bandgap low mobility material, and the second low bandgap high mobility material. The transistor100may also be selectively turned to an “off” state (i.e., disabled) to substantially stop current flow. When incorporated with a select device, enabling or disabling the transistor100may connect or disconnect to a desired structure. When incorporated as an access transistor, the transistor100may enable access to the storage element during a particular operation (e.g., read, write, etc.). However, current may “leak” from the storage element through the channel region140in the “off” state in the direction of arrow146and/or in other directions. Refreshing the memory cell may include reading and recharging each memory cell to restore the storage element to a charge corresponding to the appropriate binary value (e.g., 0 or 1).

As shown inFIGS.1A and1B, the materials122,142,152are shown as three distinct regions that alternate between a lower bandgap higher mobility material (e.g., source material122, drain material152) and a higher bandgap lower mobility material (e.g., channel material142). Other configurations are also contemplated. For example, the channel region140may include additional regions that are more than three. For example, as shown inFIG.2, the channel region140may include channel materials142A,142B,142C that may alternate between a higher bandgap lower mobility material (e.g.,142A,142C) and a lower bandgap higher mobility material (e.g.,142B).

As shown inFIGS.1A,1B, and2, the gate electrode126may include a single-side gate passing along one of the sidewalls of the channel material142. Other configurations are also contemplated. For example, as shown inFIG.3, the gate electrode126may include a dual-sided gate with electrodes provided along at least a part of each of the sidewalls of the channel material142. In some embodiments, the gate electrode126may include a tri-sided gate with electrodes provided along at least a part of each of the sidewalls and front wall or rear wall of the channel material142. Therefore, the gate electrode126may be configured as a “U” gate. In still other embodiments, the gate electrode126may include a surround gate conformally covering each of the sidewalls, front wall, and rear wall of the channel material142. In still other embodiments, the gate electrode126may include a ring gate surrounding only a portion of each of the sidewalls, front wall, and rear wall of the channel material142. Forming the various configurations of the gate electrode126may be achieved according to techniques known in the art. Therefore, details for forming these other configurations are not provided herein.

FIG.4is a perspective view of a schematic of transistors100having multiple types of materials122,142,152as discussed above. The transistors100may be utilized as access transistors for corresponding memory cells of a memory array according to an embodiment of the present disclosure. As such, the transistors100may be coupled to a corresponding storage element (not shown) to form a memory cell. As discussed above, various configurations of storage elements are contemplated as would be apparent to those of ordinary skill in the art. Each memory cell defines a cell area according to the dimensions of its sides. Each side may have a cell side dimension. The cell may have equal width and length cell side dimensions. The dimensions of the capacitor of each memory cell may be relatively small and the memory cells densely packed relative to one another. In some embodiments, cell side dimension of each memory cell of the present disclosure may be substantially equal to or less than 2F, where F is known in the art as the smallest feature size capable of fabrication by conventional fabrication techniques. Therefore, the cell area of each memory cell may be substantially equal to 4F2.

Such a memory array may include memory cells aligned in rows and columns in the same horizontal plane. The first conductive material118forming the source region120of each transistor100may be arranged perpendicular to the stacked materials122,142,152for each transistor100. Likewise, the second conductive material148forming the drain contact for each transistor100may be arranged perpendicular to the stacked materials122,142,152of each transistor100. The second insulative material144and the gate electrodes126may be arranged in parallel to the channel material142and perpendicular to the first conductive material118and the second conductive material148. Multiple memory cells within a particular row may be in operative communication with the same gate electrode126, second insulative material144, and channel material142. Therefore, for example, a gate electrode126in operative communication with the channel region140of a first memory cell may also be in operative communication with the channel region140of a second memory cell neighboring the first memory cell. Correspondingly, multiple memory cells within a particular column may be in operative communication with the same first conductive material118and second conductive material148.

A method of forming a semiconductor device is disclosed. The method comprises forming a hybrid transistor supported by a substrate comprising forming a source including a first low bandgap high mobility material, forming a channel including a high bandgap low mobility material coupled with the first low bandgap high mobility material, forming a drain including a second low bandgap high mobility material coupled with the high bandgap low mobility material, and forming a gate separated from the channel via a gate oxide material.

FIGS.5A through5Jdepict various stages of a fabrication process according to the disclosed embodiment of a method of forming a memory cell. The method may result in the fabrication of a transistor100such as that discussed above and depicted inFIGS.1A and1B.

With particular reference toFIG.5A, the method may include forming a substrate112having a primary surface114. The substrate112, or at least the primary surface114, may be formed of a semiconductor material (e.g., silicon) or other material as known in the art.

With reference toFIG.5B, the method includes forming a first conductive material118supported by the substrate112. The first conductive material118may be formed in a continuous layer covering the primary surface114of the substrate112, as shown inFIG.1B. The first conductive material118may alternatively be formed as an elongated line on or within the substrate112, as shown inFIG.5B. Elongated lines of the first conductive material118may be conducive for inclusion in embodiments that include a memory cell within an array of aligned memory cells. As such, the first conductive material118of one memory cell may extend to other memory cells in a particular row or column. A plurality of aligned elongated lines of the first conductive material118may be arranged in parallel and be separated from one another by a portion of the substrate112.

As illustrated inFIG.5B, the first conductive material118is formed as a line of metal within the substrate112such that a top surface of the first conductive material118is aligned with the plane defined by the primary surface114of the substrate112. In some embodiments, the method may include etching a trench into the substrate112and depositing the first conductive material118within the trench. Forming the first conductive material118may further include planarizing the top surfaces of the first conductive material118and the primary surface114of the substrate112or planarizing just the top surface of the first conductive material118. Planarizing the first conductive material118and substrate112may include abrasive planarization, chemical mechanical polishing or planarization (CMP), an etching process, or other known methods.

With reference toFIG.5C, the present method further includes forming a third conductive material124isolated from the first conductive material118. Forming the third conductive material124isolated from the first conductive material118may include forming the third conductive material124such that the third conductive material124appears to be floating within a first insulative material160. These techniques may include depositing a first amount of first insulative material160, forming the third conductive material124on or in the top surface of the first deposited amount of first insulative material160, and applying a second amount of first insulative material160to cover the third conductive material124. It may further include planarizing the top surface of the second amount of first insulative material160. Planarizing the top surface of the second amount of first insulative material160may be accomplished with any of the aforementioned planarizing techniques or another appropriate technique selected by one having ordinary skill in the art.

With reference toFIGS.5D and5E, the present method further includes forming an opening bordered at least in part by portions of the first conductive material118and the third conductive material124. Forming such an opening may be accomplished in one or more stages. The opening may be formed by forming a first opening128to expose a portion of the first conductive material118, as shown inFIG.2D, and then by forming a second opening130to also expose a portion of the third conductive material124, as shown inFIG.2E. Alternatively, the opening may be formed by exposing both the first conductive material118and the third conductive material124in one step. Selecting and implementing the appropriate technique or techniques to form the opening exposing a portion of the first conductive material118and the third conductive material124may be understood by those of skill in the art. These techniques may include isotropically etching the first insulative material160to form first opening128to contact a portion of the first conductive material118. The techniques may further include anisotropically etching the first insulative material160to expand the width of the previously formed first opening128until a portion of the third conductive material124is also exposed, thus forming the second opening130. For example, without limitation, the second opening130may be formed using a reactive ion etch process.

Due to the use of such techniques to form the opening bordered at least in part by the first conductive material118and the third conductive material124, the third conductive material124may be offset from the positioning of the first conductive material118. That is, in some embodiments, the third conductive material124may be formed in exact alignment with the first conductive material118such that the horizontal sides of the first conductive material118align vertically with the horizontal sides of the third conductive material124. In such an embodiment, the third conductive material124may completely overlap and align with the first conductive material118. In other embodiments, one of the third conductive material124and the first conductive material118may completely overlap the other such that vertical planes perpendicular to the primary surface114of the substrate112passing through one of the conductive materials124,118intersects with the other conductive materials118,124. In other embodiments, the third conductive material124may be formed to partially overlap the first conductive material118such that at least a portion of both the first conductive material118and the third conductive material124occupy space in a vertical plane perpendicular to the primary surface114of the substrate112. In still other embodiments, the third conductive material124may be completely offset from the first conductive material118such that no vertical plane perpendicular to the primary surface114of the substrate112intersects both the first conductive material118and the third conductive material124. Regardless of the overlapping or non-overlapping positions of the first conductive material118and the third conductive material124, in forming the second opening130, at least a portion of the first conductive material118is exposed and at least a portion of the third conductive material124is exposed.

According to the depicted embodiment, the formed second opening130is bordered at least in part along a bottom136of second opening130by an upper portion of the first conductive material118and is bordered at least in part along one of sidewalls134of the second opening130by a side portion of third conductive material124. In embodiments involving a single-sided gate electrode126, the second opening130may be formed by forming a trench through first insulative material160to expose at least a portion of first conductive material118and third conductive material124. In other embodiments, such as those in which the gate electrode126is a dual-sided gate, a surround gate, a ring gate, or a “U” gate, forming the second opening130may include removing central portions of the third conductive material124to form the second opening130passing through the third conductive material124. Such second opening130may be bordered in part along the bottom136of second opening130by an upper portion of the first conductive material118and bordered along multiple sidewalls134by side portions of the third conductive material124.

With reference toFIG.5F, the method includes forming a second insulative material144on the sidewalls134of the formed second opening130. The second insulative material144may be formed of a dielectric material, such as an oxide. The second insulative material144may be formed by depositing the material conformally on the sidewalls134. For example, without limitation, the second insulative material144may be formed by atomic layer deposition (ALD). Selecting and implementing an appropriate technique to form the second insulative material144on the sidewalls134of the second opening130may be understood by those of skill in the art. Forming the second insulative material144along the sidewalls134of the second opening130may reduce the width of second opening130, forming a slightly narrower second opening130.

Forming the second insulative material144may include forming the second insulative material144not only on the sidewalls134of the second opening130, but also on the exposed surfaces of the third conductive material124. A material-removing technique, such as a conventional spacer etching technique, may be used to remove the second insulative material144covering the upper surface of the first conductive material118, while leaving third conductive material124covered by second insulative material144.

With reference toFIGS.5G through5I, second opening130is filled with materials for the source material122(FIG.5G), the channel material142(FIG.5H), and the drain material152(FIG.5I) that form a hybrid transistor including different types of materials exhibiting different bandgap and mobility properties. In some embodiments, the source material122and the drain material152may be of the same material type whereas the second channel material142is of a different material type.

As a non-limiting example, the source material122and the drain material152may be formed from a lower bandgap higher mobility material, and the channel material142may be formed from a higher bandgap lower mobility material. For example, without limitation, the second opening130may be filled with a doped semiconductor material (e.g., N doped) to form the source material122disposed on the first conductive material118(seeFIG.5G). The second opening130may then be filled with an oxide semiconductor material to form the channel material142disposed on the source material122(seeFIG.5H). The second opening130may then be filled with a doped semiconductor material (e.g., N doped) to form the drain material152disposed on the channel material142. Conventional techniques for forming the other components of the transistor100(e.g., the first conductive material118, the third conductive material124, and the second insulative material144) at fabrication temperatures less than 800 degrees Celsius are known in the art. Such techniques may require, for example, fabrication temperatures less than 650 degrees Celsius (e.g., temperatures in the range of 200 to 600 degrees Celsius). The method may also include planarizing the upper surface of the first insulative material160, the second insulative material144, and the drain material152. Planarizing these upper surfaces may be accomplished using any planarization technique.

With reference toFIG.5J, the method further includes forming the second conductive material148atop and in contact with the drain material152. When further forming a memory cell, a storage element (e.g., capacitor) may also be formed over the second conductive material148to form a memory cell according to the various configurations of storage elements known by those of ordinary skill in the art.

In some embodiments, forming the transistor may include a gate last flow formation in which the stack of films comprising the drain, channel, and source materials are deposited, etched first to form lines, filled and etched again in perpendicular direction to form a pillar followed by gate-oxide and gate metal. Other methods of forming the transistor are further contemplated as known by those of ordinary skill in the art.

FIGS.6and7are cross-sectional front views of a schematic of transistors configured in a vertical configuration according to additional embodiments of the present disclosure. The construction of the vertical hybrid transistors600,700is generally similar to that ofFIG.1Ain that a source material122, a channel material142, and a drain material152of different types may be stacked in a vertical direction relative to a substrate112and first conductive material118. InFIG.6, however, the channel material142of the vertical hybrid transistor600may have a wide base that tapers from the top of the source material122to the bottom of the drain material152. In addition, the channel material142may extend vertically for the entire channel length L defined by the length of the gate electrode126. The gate electrode126may be slightly angled to accommodate this tapering. InFIG.7, the source material122and the drain material152may extend into the channel region defined by the length of the gate electrode126. As a result, at least a portion of the source material122may extend above the bottom of the gate electrode126, and at least a portion of the drain material152may extend below the top of the gate electrode126. Thus, the channel region140defined by length of the gate electrode126may be a hybrid channel that includes different material types (e.g., low mobility and high mobility materials). The lengths of these different materials122,142,152within the channel region140may be selected for tuning other device metrics (e.g., DIBL, SVTM etc.) as desired. The formation of such a tapered channel region may be performed as known by those of ordinary skill in the art. In some embodiments, the bandgap from the channel material142to the source and drain materials122,152may be uniformly graded. In some embodiments, the doping of the source and drain materials122,152may be non-uniform. For example, the portion of the source and drain materials122,152overlapping with the gate electrode126within the channel length L may have a lower doping concentration relative to the higher doping concentration of the source and drain materials122,152in the portions outside of the area of the gate electrode126.

In some embodiments the memory cell may be structured to include a planar access transistor (i.e., also referred to as a horizontal access transistor).FIG.8andFIG.9show non-limiting examples of such planar access transistors according to additional embodiments of the present disclosure.

Referring toFIG.8, the transistor800may include a substrate812upon which the transistor800is supported. A gate electrode824may be disposed on the substrate812. In some embodiments, an additional material814(e.g., a silicon oxide material) may be disposed between the conductive material for the gate electrode824and the substrate812. A gate oxide material840may be formed over the gate electrode824including around the side walls of the gate electrode824. The source material822, channel material842, and drain material852may be formed on the gate oxide material840and be coupled with a first conductive material818as a source contact, and with a second conductive material848as a drain contact. The materials822,842,852may be formed from different material types to form a hybrid transistor as discussed above.

As shown inFIG.8, the combined materials822,842,852may have a shorter width than the gate oxide material840, and the first conductive material818and the second conductive material848may each surround at least two sides of the channel material842. The materials822,842,852may be disposed proximate the inner ends of their respective conductive materials818,848.

Referring toFIG.9, the transistor900may include a substrate912, a gate electrode924, a gate oxide940, and a source material922, channel material942, and drain material952stacked similarly as inFIG.8. One difference between the embodiments ofFIGS.8and9is that the combined materials922,942,952and the gate oxide940may be substantially coextensive in length. In addition, the first conductive material918and the second conductive material948may be disposed on only the top side of the channel material942, and proximate the respective outer ends942A,942C of the channel material942. The transistor900may further include additional materials, such as an etch stop material960and a passivation material962formed over the channel material942. Other configurations of horizontal transistors are also contemplated including top gate or bottom gate configurations.

FIG.10AandFIG.10Bare graphs illustrating the drive current (ID) for a transistor when applying various gate voltages. In particular, graph1050ofFIG.10Bis a zoomed-in, enlarged view of a portion of the graph1000ofFIG.10A. Line1002shows the drive current IDresulting from different gate voltages (VG) for a hybrid transistor according to embodiments of the disclosure. Line1004shows the drive current (ID) resulting from different gate voltages (VG) for a conventional transistor having a uniform channel between conductive contacts. As shown inFIGS.10A and10B, the off current (IOFF=IDwhen VGis less than zero) for line1002is similar to line1004, but that the on current (ION=IDwhen VGis greater than zero) is increased in comparison to line1004. Thus, the hybrid transistor may combine the advantage of having a high on current (ION) and low off current (IOFF) relative to conventional devices.

A semiconductor device is also disclosed. The semiconductor device comprises a dynamic random-access memory (DRAM) array comprising DRAM cells that each comprise a hybrid access transistor and a storage element operably coupled with the hybrid access transistor configured as discussed above.

FIG.11is a simplified block diagram of a semiconductor device1100implemented according to one or more embodiments described herein. The semiconductor device1100includes a memory array1102and a control logic component1104. The memory array1102may include memory cells as described above. The control logic component1104may be operatively coupled with the memory array1102so as to read, write, or re-fresh any or all memory cells within the memory array1102. Accordingly, a semiconductor device comprising a dynamic random-access memory (DRAM) array is disclosed. The DRAM array comprises a plurality of DRAM cells. Each DRAM cell of the plurality comprises a hybrid access transistor having a channel region comprising an oxide semiconductor material and one or more source or drain regions comprising a doped semiconductor material as discussed above.

A system is also disclosed. The system comprises a memory array of memory cells. Each memory cell may comprise an access transistor and a storage element operably coupled with the transistor. The access transistor may be configured as discussed above.

FIG.12is a simplified block diagram of an electronic system1200implemented according to one or more embodiments described herein. The electronic system1200includes at least one input device1202. The input device1202may be a keyboard, a mouse, or a touch screen. The electronic system1200further includes at least one output device1204. The output device1204may be a monitor, touch screen, or speaker. The input device1202and the output device1204are not necessarily separable from one another. The electronic system1200further includes a storage device1206. The input device1202, output device1204, and storage device1206are coupled to a processor1208. The electronic system1200further includes a memory device1210coupled to the processor1208. The memory device1210includes at least one memory cell according to one or more embodiments described herein. The memory device1210may include an array of memory cells. The electronic system1200may include a computing, processing, industrial, or consumer product. For example, without limitation, the electronic system1200may include a personal computer or computer hardware component, a server or other networking hardware component, a handheld device, a tablet computer, an electronic notebook, a camera, a phone, a music player, a wireless device, a display, a chip set, a game, a vehicle, or other known systems.

While the present disclosure is susceptible to various modifications and alternative forms in implementation thereof, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure encompasses all modifications, combinations, equivalents, variations, and alternatives falling within the scope of the present disclosure as defined by the following appended claims and their legal equivalents.