Patent ID: 12213318

DETAILED DESCRIPTION

Specific structural or functional descriptions of embodiments are disclosed in the present specification or application to better illustrate the concept of the present disclosure. The disclosed embodiments are not exhaustive and may be carried out in various forms and should not be construed as being limiting.

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings in order to allow those of ordinary skill in the art to implement the technical idea of the present disclosure.

FIG.1is a block diagram illustrating a semiconductor memory device10according to an embodiment of the present disclosure.

Referring toFIG.1, the semiconductor memory device includes a peripheral circuit PC and a memory cell array20.

The peripheral circuit PC may be configured to control a program operation for storing data in the memory cell array20, a read operation for outputting data stored in the memory cell array20, and an erase operation for erasing data stored in the memory cell array20.

In an embodiment, the peripheral circuit PC may include a voltage generator31, a row decoder33, a control circuit35, and a page buffer group37.

The memory cell array20may include a plurality of memory blocks. The memory cell array20may be connected to the row decoder33through word lines WL, and may be connected to the page buffer group37through bit lines BL.

The control circuit35may control the voltage generator31, the row decoder33, and the page buffer group37in response to a command CMD and an address ADD.

The voltage generator31may generate various operation voltages such as an erase voltage, a ground voltage, a program voltage, a verify voltage, a pass voltage, and a read voltage used for the program operation, the read operation, and the erase operation in response to control of the control circuit35.

The row decoder33may select a memory block in response to the control of the control circuit35. The row decoder33may be configured to apply the operation voltages to the word lines WL connected to the selected memory block.

The page buffer group37may be connected to the memory cell array20through the bit lines BL. The page buffer group37may temporarily store data received from an input/output circuit (not shown) during the program operation in response to the control of the control circuit35. The page buffer group37may sense a voltage or a current of the bit lines BL during the read operation or a verify operation in response to the control of the control circuit35. The page buffer group37may select the bit lines BL in response to the control of the control circuit35.

Structurally, the memory cell array20may overlap a portion of the peripheral circuit PC.

FIG.2is a circuit diagram illustrating the memory cell array20ofFIG.1.

Referring toFIG.2, the memory cell array20may include a plurality of cell strings CS1and CS2connected between a source line SL and a plurality of bit lines BL. The plurality of cell strings CS1and CS2may be commonly connected to a plurality of word lines WL1to WLn.

Each of the plurality of cell strings CS1and CS2may include at least one source select transistor SST connected to the source line SL, at least one drain select transistor DST connected to the bit line BL, and a plurality of memory cells MC1to MCn connected in series between the source select transistor SST and the drain select transistor DST.

Gates of the plurality of memory cells MC1to MCn may be respectively connected to the plurality of word lines WL1to WLn that are spaced apart from each other and stacked. The plurality of word lines WL1to WLn may be disposed between a source select line SSL and two or more drain select lines DSL1and DSL2. The two or more drain select lines DSL1and DSL2may be spaced apart from each other at the same level.

A gate of the source select transistor SST may be connected to the source select line SSL. A gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST.

The source line SL may be connected to a source of the source select transistor SST. A drain of the drain select transistor DST may be connected to a bit line corresponding to the drain of the drain select transistor DST.

The plurality of cell strings CS1and CS2may be divided into string groups respectively connected to the two or more drain select lines DSL1and DSL2. Cell strings connected to the same bit line may be independently controlled by different drain select lines. In addition, cell strings connected to the same drain select line may be independently controlled by different bit lines.

In an embodiment, the two or more drain select lines DSL1and DSL2may include a first drain select line DSL1and a second drain select line DSL2. The plurality of cell strings CS1and CS2may include a first cell string CS1of a first string group connected to the first drain select line DSL1and a second string CS2of a second string group connected to the second drain select line DSL2.

FIG.3is a perspective view schematically illustrating the semiconductor memory device10ofFIG.1according to embodiments of the present disclosure.

Referring toFIG.3, the semiconductor memory device10may include the peripheral circuit PC disposed on a substrate SUB and gate stacks GST overlapping the peripheral circuit PC.

Each of the gate stacks GST may include the source select line SSL, the plurality of word lines WL1to WLn, and the two or more drain select lines DSL1and DSL2separated from each other at the same level by a separation structure DSM.

The source select line SSL and the plurality of word lines WL1to WLn may extend in a first direction X and a second direction Y, and may be formed in a flat plate shape parallel to an upper surface of the substrate SUB. The first direction X may be a direction in which an X-axis of an XYZ coordinate system is directed, and the second direction Y may be a direction in which a Y-axis of the XYZ coordinate system is directed.

The plurality of word lines WL1to WLn may be spaced apart from each other and stacked in a third direction Z. The third direction Z may be a direction in which a Z-axis of the XYZ coordinate system is directed. The plurality of word lines WL1to WLn may be disposed between the two or more drain select lines DSL1and DSL2and the source select line SSL.

The gate stacks GST may be separated from each other by a slit SI. The separation structure DSM may be formed shorter in the third direction Z than the slit SI and may overlap the plurality of word lines WL1to WLn.

Each of the separation structure DSM and the slit SI may extend in a straight line shape, a zigzag shape, or a wave shape. Widths of each of the separation structures DSM and the slit SI may be variously changed according to different designs.

The source select line SSL according to an embodiment may be disposed closer to the peripheral circuit PC than the two or more drain select lines DSL1and DSL2.

The semiconductor memory device10may include the source line SL disposed between the gate stacks GST and the peripheral circuit PC, and the plurality of bit lines BL may be spaced farther from the peripheral circuit PC than the source line SL. The gate stacks GST may be disposed between the plurality of bit lines BL and the source line SL.

FIG.4is a cross-sectional view of a semiconductor memory device illustrating a portion of a memory cell array of the semiconductor memory device according to an embodiment of the present disclosure.

Referring toFIG.4, the semiconductor memory device may include a lower stack B_GST, an upper stack T_GST, a vertical channel structure VS, a drain select transistor pattern DST_P, and a contact plug CT.

The lower stack B_GST may include conductive layers CP1and insulating layers ILD1and ILD2that are alternately stacked. The conductive layers CP1may be a gate electrode of a memory cell, or a word line. The conductive layers CP1may include a conductive material such as polysilicon, tungsten, molybdenum, or a metal. The insulating layers ILD1and ILD2may be for insulating the stacked conductive layers CP1from each other. The insulating layers ILD1and ILD2may include an insulating material such as an oxide, nitride, or an air gap. The insulating layer ILD2disposed at the uppermost portion among the insulating layers ILD1and ILD2may be formed to be thicker than the remaining insulating layers ILD1. The lower stack B_GST may further include a second blocking insulating layer BI2surrounding a surface of the conductive layers CP1. The second blocking insulating layer BI2may be disposed between an interface between the conductive layers CP1and the insulating layers ILD1and ILD2and an interface between the conductive layers CP1and the vertical channel structure VS.

The vertical channel structure VS may be disposed to pass through the lower stack B_GST in a vertical direction. That is, the vertical channel structure VS may extend in the vertical direction and may be surrounded by the conductive layers CP1.

The vertical channel structure VS may include a core insulating layer CO, a channel layer CH, a tunnel insulating layer TI, a data storage layer DS, and a first blocking insulating layer BI1extending in the vertical direction. The core insulating layer CO may be formed of an insulating layer such as an oxide layer. The channel layer CH may surround the core insulating layer CO and may extend in the vertical direction. The channel layer CH may include a semiconductor layer. In an embodiment, the channel layer CH may include silicon. The tunnel insulating layer TL may surround the channel layer CH and may extend in the vertical direction. The tunnel insulating layer TL may be formed of a silicon oxide layer capable of charge tunneling. The data storage layer DS may surround the tunnel insulating layer TL and may extend in the vertical direction. The data storage layer DS may be formed of a material layer capable of storing data changed using Fowler-Nordheim tunneling. In an embodiment, the data storage layer DS may be formed of a charge trap nitride layer. The first blocking insulating layer BI1may surround the data storage layer DS and extend in the vertical direction. The first blocking insulating layer BI1may include an oxide layer capable of charge blocking.

The semiconductor memory device may further include a capping layer CL that is in contact with an upper portion of the vertical channel structure VS and passes through the insulating layer ILD2. The capping layer CL may be formed of a conductive material, and may include, for example, a polysilicon layer. The capping layer CL may be included in the vertical channel structure VS.

The vertical channel structure VS may be defined as a cell plug of the memory cell array. The cell plug may be a structure corresponding to the source select transistor SST and the plurality of memory cells MC1to MCn among the cell strings CS1and CS2shown inFIG.2.

The upper stack T_GST may be stacked on the lower stack B_GST. The upper stack T_GST may include a conductive layer CP2and an insulating layer ILD3stacked on and under the conductive layer CP2. In an embodiment of the present disclosure, it has been illustrated and described that one conductive layer CP2is disposed, but a plurality of conductive layers CP2may be sequentially disposed, and the insulating layer ILD3may be disposed between the conductive layers CP2. The conductive layer CP2may be a gate electrode of the drain select transistor, or a drain select line. The conductive layer CP2may include a conductive material such as polysilicon doped with an N-type impurity, tungsten, tungsten silicide, molybdenum, or a metal.

Each of the drain select transistor patterns DST_P passes through the upper stack T_GST and is in contact with one vertical channel structure VS. For example, the drain select transistor pattern DST_P may be disposed to be in contact with the capping layer CL.

The drain select transistor pattern DST_P may include an insulating pattern IL, a channel layer surrounding one sidewall, an upper surface, and a lower surface of the insulating pattern IL, and a gate insulating layer GI that is in contact with a sidewall of the channel layer CHL.

The drain select transistor pattern DST_P may be formed in a semi-cylindrical shape. For example, one sidewall of the insulating pattern IL may be formed in a curved surface, and another sidewall may be formed in a flat surface, as illustrated inFIG.5I. The channel layer CHL may be formed to be in contact with a curved portion, which is one sidewall, an upper surface, and a lower surface of the insulating pattern IL.

The channel layer CHL may include a first channel layer CHL1that is in contact with the curved portion which is one sidewall and the lower surface of the insulating pattern IL and is in contact with the capping layer CL, and a second channel layer CHL2that is in contact with the upper surface of the insulating pattern IL. The channel layer CHL may be formed of a conductive material, and in an embodiment, the channel layer CHL may be formed of a polysilicon layer.

The gate insulating layer GI may be formed of an oxide layer or an ONO layer in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked.

The drain select transistor pattern DST_P may be defined as a drain select plug of the memory cell array. The drain select plug may be a structure corresponding to the drain select transistor DST among the cell strings CS1and CS2shown inFIG.2.

The semiconductor memory device may further include contact plugs CT passing through an upper insulating layer ILD4formed on the upper stack T_GST and being in contact with the second channel layer CHL2of the drain select transistor pattern DST_P. The contact plugs CT may be connected to the bit lines BL ofFIG.3.

FIGS.5A to5Lare cross-sectional views and plan views of a semiconductor memory device illustrating a method of manufacturing the semiconductor memory device according to an embodiment of the present disclosure.

Referring toFIG.5A, a stack ST in which first interlayer insulating layers101and105and sacrificial layers103are alternately stacked may be formed. The stack ST may be formed on a substrate (not shown) including a peripheral circuit.

The sacrificial layers103may be formed of a material different from that of the first interlayer insulating layers101and105. For example, the first interlayer insulating layers101and105may be formed of an oxide such as a silicon oxide layer. The sacrificial layers103may be formed of a material having an etch rate that is different from that of the first interlayer insulating layers101and105. For example, the sacrificial layers103may be formed of a nitride such as a silicon nitride layer.

The first interlayer insulating layer105disposed at the uppermost portion may be formed to be thicker than the other first interlayer insulating layers101.

Referring toFIG.5B, a mask pattern (not shown) in which a region where a vertical channel structure is to be formed is formed on the stack ST, and an etching process using the mask pattern is performed to form a plurality of channel holes107passing through the stack ST.

Thereafter, a vertical channel structure121is formed in each of the channel holes107. The vertical channel structure121may be formed by sequentially stacking a first blocking insulating layer111, a data storage layer113, a tunnel insulating layer115, a channel layer117, and a core insulating layer119on a sidewall of each of the channel holes107.

The first blocking insulating layer111may be formed on a sidewall of each of the channel holes107. The first blocking insulating layer111may include an oxide layer capable of charge blocking. In an embodiment, the blocking insulating layer may be formed of aluminum oxide Al2O3. The data storage layer113may be formed on a sidewall of the first blocking insulating layer111. The data storage layer113may be formed of a charge trap layer, a material layer including a conductive nanodot, or a phase change material layer. For example, the data storage layer113may store data changed using Fowler-Nordheim tunneling. To this end, the data storage layer113may be formed of a silicon nitride layer capable of charge trapping. The tunnel insulating layer115may be formed on a sidewall of the data storage layer113. The tunnel insulating layer115may be formed of a silicon oxide layer capable of charge tunneling. The channel layer117may be formed on a sidewall of the tunnel insulating layer115. The channel layer117may include a semiconductor layer. In an embodiment, the channel layer117may include silicon. The core insulating layer119may be formed by filling a central region of the channel holes107. The core insulating layer119may be formed of an oxide layer.

The vertical channel structure121may be defined as the cell plug of the memory cell array. The cell plug may be a structure corresponding to the source select transistor SST and the plurality of memory cells MC1to MCn among the cell strings CS1and CS2shown inFIG.2.

FIG.5Cis a plan view of a semiconductor memory device on which the process step related toFIG.5Bdescribed above is performed. Referring toFIG.5C, the plurality of vertical channel structures121may be regularly arranged to be spaced apart from each other by a predetermined distance.

Referring toFIG.5D, an upper portion of the plurality of vertical channel structures121may be etched at a predetermined thickness. For example, the upper portion of the plurality of vertical channel structures121may be etched at the predetermined thickness so that a height of an upper surface of the plurality of vertical channel structures121is higher than a height of an upper surface of the sacrificial layer103positioned at the uppermost portion and is lower than a height of an upper surface of the first interlayer insulating layer105positioned at the uppermost portion.

Thereafter, a capping layer123may be formed in a space where the plurality of vertical channel structures121are etched and removed. In an embodiment, the capping layer123may be formed of a doped semiconductor layer. The capping layer123may be defined as a configuration included in the vertical channel structure121.

Referring toFIG.5E, a slit SI passing through the stack ST shown inFIG.5Dmay be formed. A sidewall of the sacrificial layers103shown inFIG.5Dmay be exposed by the slit SI. Thereafter, the sacrificial layers103shown inFIG.5Dmay be removed through the slit SI. Accordingly, openings exposing a side portion of the vertical channel structure121may be formed. Openings may be defined between the first interlayer insulating layers101and105.

Referring toFIG.5F, conductive layers131may be filled in a space where the sacrificial layers are removed, that is, the openings. For example, after a conductive material is deposited to fill the openings, the conductive material inside the slit SI may be removed so that the conductive material is separated into the conductive layers131by the slit SI. Before the conductive layers131are filled in the openings, a second blocking insulating layer133may be formed along a surface of the openings.

Referring toFIG.5G, a second interlayer insulating layer135, a conductive layer137, and a second interlayer insulating layer139may be sequentially formed on the entire structure including the first interlayer insulating layer105and the capping layer123. The slit SI may be filled by the second interlayer insulating layer135.

In an embodiment, the conductive layer137may include a conductive material such as polysilicon doped with an N-type impurity, tungsten, tungsten silicide, molybdenum, or a metal.

Referring toFIG.5H, drain select transistor pattern holes DT_H are formed by etching the second interlayer insulating layer139, the conductive layer137, and the second interlayer insulating layer135so that an upper surface of the two adjacent capping layers123are exposed. Each of the drain select transistor pattern holes DT_H may be formed in an elliptical cylindrical structure.

In an embodiment of the present disclosure, each of the drain select transistor pattern holes DT_H is formed to expose the upper surface of the two adjacent capping layers123, but in another embodiment, each of the drain select transistor pattern holes may be formed so that the upper surface of one capping layer123is exposed in correspondence with one vertical channel structure.

Thereafter, a gate insulating layer141is formed on a sidewall of each of the drain select transistor pattern holes DT_H. That is, the gate insulating layer141is formed on a curved sidewall of each of the drain select transistor pattern holes DT_H. The gate insulating layer141may be formed of an oxide layer or an ONO layer in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked.

Thereafter, a first channel layer143is formed on a bottom surface of each of the drain select transistor pattern holes DT_H and a sidewall of the gate insulating layer141. The first channel layer143is in contact with the capping layer123of the vertical channel structure121. The first channel layer143may be formed as a polysilicon layer. After forming the first channel layer143, boron may be injected into the first channel layer143to prevent a leakage current.

FIG.5Iis a plan view of a semiconductor memory device on which the process step related toFIG.5Hdescribed above is performed. Referring toFIG.5I, each of the drain select transistor pattern holes DT_H may overlap the capping layer123of two vertical channel structures adjacent to each other. Each of the drain select transistor pattern holes DT_H may have an elliptical shape. In an embodiment of the present disclosure, it is illustrated that one drain select transistor pattern hole DT_H overlaps the capping layer123of two vertical channel structures adjacent in a diagonal direction, but one drain select transistor pattern hole DT_H may overlap the capping layer123of two vertical channel structures adjacent in a horizontal or vertical direction. In addition, in another embodiment, one drain select transistor pattern hole DT_H may overlap the capping layer123of one vertical channel structure.

Referring toFIG.5J, an insulating pattern145is formed by filling an insulating material inside the drain select transistor pattern holes DT_H ofFIG.5I. Thereafter, a second channel layer147covering an upper portion of the insulating pattern145and being in contact with the first channel layer143is formed. The second channel layer147may be formed of a polysilicon layer. A sidewall, an upper surface, and a lower surface of the insulating pattern145are covered by the first channel layer143and the second channel layer147. After forming the second channel layer147, boron may be injected into the second channel layer147to prevent a leakage current. The first channel layer143and the second channel layer147may be a channel layer149for the drain select transistor.

Referring toFIG.5K, a separation pattern151passing through the second interlayer insulating layer139, the conductive layer137, and the second interlayer insulating layer135is formed. The separation pattern151may pass through the drain select transistor pattern holes in a line shape. Accordingly, the gate insulating layer141, the first channel layer143, the second channel layer147, and the insulating pattern145formed inside the drain select transistor pattern hole may be separated into both ends by the separation pattern151, and each of one end and the other end of the both ends is in contact with the capping layer123which is an upper end of a corresponding vertical channel structure121. In addition, the conductive layer137surrounding a side surface of the gate insulating layer141may be patterned and separated by the separation pattern151of the line shape. That is, the conductive layer137extending in one side direction and the conductive layer137extending in the other side direction based on the separation pattern151may be separated from each other.

That is, an etching process is performed to form a trench in which the first interlayer insulating layer105between the adjacent vertical channel structures121is exposed, and the trench separates the gate insulating layer141, the first channel layer143, the second channel layer147, and the insulating pattern145formed inside the drain select transistor pattern hole into the both ends. Thereafter, the separation pattern151may be formed by filling the trench with an insulating material.

The gate insulating layer141, the first channel layer143, the second channel layer147, and the insulating pattern145separated to the both ends may be defined as a drain select plug150of the memory cell array. A curved sidewall of the drain select plug150is in contact with the conductive layer137, and a planar sidewall of the drain select plug150is in contact with the separation pattern151.

As described above, according to an embodiment of the present disclosure, the vertical channel structure121defined as the cell plug is formed in a cylindrical shape, and the drain select plug150is formed on the vertical channel structure121. One sidewall of the drain select plug150may form a curved surface and another sidewall may form a flat surface. That is, the drain select plug150may be formed in a semi-cylindrical shape.

Thereafter, the second interlayer insulating layer139, the conductive layer137, and the second interlayer insulating layer135disposed on an upper end of the slit SI are etched, and an insulating material153is filled in the etched region. Accordingly, the slit SI may be filled with the second interlayer insulating layer135and the insulating material153.

Referring toFIG.5L, an upper interlayer insulating layer161is formed on the second interlayer insulating layer139. Thereafter, the contact plugs CT passing through the upper interlayer insulating layer161to be in contact with an upper portion of the drain select plug150may be formed. The contact plugs CT may be connected to the bit lines in a subsequent process.

FIGS.6A to6Iare cross-sectional views of a semiconductor memory device illustrating a method of manufacturing the semiconductor memory device according to another embodiment of the present disclosure.

Referring toFIG.6A, a first stack ST1in which first interlayer insulating layers201and205and sacrificial layers203are alternately stacked may be formed. The first stack ST1may be formed on a substrate (not shown) including a peripheral circuit.

The sacrificial layers203may be formed of a material different from that of the first interlayer insulating layers201and205. For example, the first interlayer insulating layers201and205may be formed of an oxide such as a silicon oxide layer. The sacrificial layers203may be formed of a material of which an etch rate is different from that of the interlayer insulating layers201and205. For example, the sacrificial layers203may be formed of a nitride such as a silicon nitride layer.

The first interlayer insulating layer205disposed at the uppermost portion may be formed to be thicker than the remaining interlayer insulating layers201.

Referring toFIG.6B, a mask pattern (not shown) in which a region where a vertical channel structure is to be formed is formed on the first stack ST1, and an etching process using the mask pattern is performed to form a plurality of channel holes207passing through the first stack ST1.

Thereafter, a vertical channel structure221is formed in each of the channel holes207. The vertical channel structure221may be formed by sequentially stacking a first blocking insulating layer211, a data storage layer213, a tunnel insulating layer215, a channel layer217, and a core insulating layer219on a sidewall of each of the channel holes207.

The first blocking insulating layer211may be formed on a sidewall of each of the channel holes207. The first blocking insulating layer211may include an oxide layer capable of charge blocking. In an embodiment, the blocking insulating layer may be formed of aluminum oxide Al2O3. The data storage layer213may be formed on a sidewall of the first blocking insulating layer211. The data storage layer213may be formed of a charge trap layer, a material layer including a conductive nanodot, or a phase change material layer. For example, the data storage layer213may store data changed using Fowler-Nordheim tunneling. To this end, the data storage layer213may be formed of a silicon nitride layer capable of charge trapping. The tunnel insulating layer215may be formed on a sidewall of the data storage layer213. The tunnel insulating layer215may be formed of a silicon oxide layer capable of charge tunneling. The channel layer217may be formed on a sidewall of the tunnel insulating layer215. The channel layer217may include a semiconductor layer. In an embodiment, the channel layer217may include silicon. The core insulating layer119may be formed by filling a central region of the channel holes207. The core insulating layer219may be formed of an oxide layer.

In the semiconductor memory device on which the process step related toFIG.6Bdescribed above is performed, as shown inFIG.5C, a plurality of vertical channel structures221may be regularly arranged to be spaced apart from each other by a predetermined distance.

The vertical channel structure221may be defined as the cell plug of the memory cell array. The cell plug may be a structure corresponding to the source select transistor SST and the plurality of memory cells MC1to MCn among the cell strings CS1and CS2shown inFIG.2.

Referring toFIG.6C, an upper portion of the plurality of vertical channel structures221may be etched at a predetermined thickness. For example, the upper portion of the plurality of vertical channel structures221may be etched at the predetermined thickness so that a height of an upper surface of the plurality of vertical channel structures221is higher than a height of an upper surface of the sacrificial layer203positioned at the uppermost portion and is lower than a height of an upper surface of the first interlayer insulating layer205.

Thereafter, a capping layer223may be formed in a space where the plurality of vertical channel structures221are etched and removed. In an embodiment, the capping layer223may be formed of a doped semiconductor layer. The capping layer223may be defined as a configuration included in the vertical channel structure221.

Referring toFIG.6D, a second stack ST2may be formed on the first stack ST1. The second stack ST2may be formed by alternately stacking second interlayer insulating layers231and a sacrificial layer233sequentially on an upper surface of the capping layer223and the first interlayer insulating layer205. The sacrificial layer233may be formed of the same material as the sacrificial layer203.

Referring toFIG.6E, the drain select transistor pattern holes DT_H are formed by etching the second stack ST2so that an upper surface of two capping layers223adjacent to each other are exposed. Each of the drain select transistor pattern holes DT_H may be formed in an elliptical cylindrical structure. An elliptical shape of an elliptical cylindrical structure may have the cross-sectional shape illustrated inFIG.5Iin which one pair of opposite sides are linear and another pair of opposite sides are curved or semicircular.

In an embodiment of the present disclosure, each of the drain select transistor pattern holes DT_H is formed to expose the upper surface of the two capping layers223adjacent to each other, but in another embodiment, each of the drain select transistor pattern holes DT_H may be formed to expose an upper surface of one capping layer in correspondence with one vertical channel structure.

The drain select transistor pattern holes DT_H may overlap the capping layer223of the two vertical channel structures adjacent to each other as shown inFIG.5I, and may be formed in an elliptical shape. In addition, one drain select transistor pattern hole DT_H may overlap the capping layer223of the two vertical channel structures adjacent in a diagonal direction, or one drain select transistor pattern hole DT_H may overlap the capping layer223of the two vertical channel structures adjacent in the horizontal or vertical direction. In addition, in another embodiment, one drain select transistor pattern hole DT_H may be formed to overlap the capping layer223of one vertical channel structure.

Thereafter, a gate insulating layer241is formed on a sidewall of each of the drain select transistor pattern holes DT_H. That is, the gate insulating layer241is formed on a curved sidewall of each of the drain select transistor pattern holes DT_H. The gate insulating layer241may be formed of an oxide layer or an ONO layer in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked.

Thereafter, a first channel layer243is formed on a bottom surface of each of the drain select transistor pattern holes DT_H and a sidewall of the gate insulating layer241. The first channel layer243is in contact with the capping layer223of the vertical channel structure221. The first channel layer243may be formed of a polysilicon layer.

Referring toFIG.6F, an insulating pattern245is formed by filling an insulating material inside the drain select transistor pattern holes DT_H. Thereafter, a second channel layer247covering an upper portion of the insulating pattern245and being in contact with the first channel layer243is formed. The second channel layer247may be formed of a polysilicon layer. A sidewall, an upper surface, and a lower surface of the insulating pattern245are covered by the first channel layer243and the second channel layer247. The first channel layer243and the second channel layer247may be a channel layer249for the drain select transistor.

Referring toFIG.6G, a separation pattern251passing through the second stack ST2, the second channel layer247, the insulating pattern245, and the first channel layer243is formed. The separation pattern251may pass through the drain select transistor pattern holes DT_H in a linear shape. Accordingly, the gate insulating layer241, the first channel layer243, the second channel layer247, and the insulating pattern245formed inside the drain select transistor pattern hole DT_H may be separated into two ends by the separation pattern251, and each of the two ends may be in contact with the capping layer223, which is an upper end of a corresponding vertical channel structure221.

That is, an etching process is performed to form a trench in which the first interlayer insulating layer205between the vertical channel structures221adjacent to each other is exposed, and the trench separates the gate insulating layer241, the first channel layer243, the second channel layer247, and the insulating pattern245formed inside the drain select transistor pattern hole DT_H into the two ends. Thereafter, the separation pattern251may be formed by filling the trench with an insulating material.

The gate insulating layer241, the first channel layer243, the second channel layer247, and the insulating pattern245separated into the two ends may be defined as the drain select plug of the memory cell array. A curved sidewall of the drain select plug, that is, the gate insulating layer241and the first channel layer243, is in contact with the sacrificial layer233, and a planar sidewall, that is, the insulating pattern245, is in contact with the separation pattern251.

As described above, according to an embodiment of the present disclosure, the vertical channel structure221defined as the cell plug is formed in a cylindrical shape, and the drain select plug is formed on the vertical channel structure221. One sidewall of the drain select plug may form a curved surface and another sidewall may form a flat surface. That is, the drain select plug may be formed in a semi-cylindrical shape.

Referring toFIG.6H, a slit SI passing through the second stack between the separation patterns251and the first stack between the vertical channel structures221is formed. A sidewall of the sacrificial layers203and233shown inFIG.6Gmay be exposed by the slit SI. Thereafter, the sacrificial layers203and233shown inFIG.6Gmay be removed through the slit SI. Accordingly, openings exposing a side of the vertical channel structure221and openings exposing a side of the gate insulating layer241may be formed. The openings may be defined between the first interlayer insulating layers201and205and between the second interlayer insulating layers231.

Referring toFIG.6I, conductive layers261may be filled in a space where the sacrificial layers are removed, that is, the openings. For example, after a conductive material is deposited to fill the openings, the conductive material inside the slit SI may be removed so that the conductive material is separated into the conductive layers261by the slit SI.

After the above-described process, the slit SI may be filled with an insulating material, and the contact plugs that are in contact with the second channel layer247may be formed as shown inFIG.5Ldescribed above.

As described above, according to an embodiment of the present disclosure, after forming one elliptical cylindrical gate pattern for the drain select transistor on at least one vertical channel structure, the gate pattern for the drain select transistor and the separation pattern for separating the conductive layer for the drain select line are formed. Accordingly, during an etching process for forming the separation pattern, by etching the gate pattern for the drain select transistor of which a critical dimension is relatively larger than a critical dimension of the vertical channel structure, an alignment margin of the etching process may be easily secured.

FIG.7is a block diagram illustrating a configuration of a memory system1100according to an embodiment of the present disclosure.

Referring toFIG.7, the memory system1100includes a semiconductor memory device1120and a memory controller1110.

The semiconductor memory device1120may be configured identically to the semiconductor memory device shown inFIGS.1to4.

The semiconductor memory device1120may be a multi-chip package configured of a plurality of flash memory chips.

The memory controller1110may be configured to control the semiconductor memory device1120, and may include static random access memory (SRAM)1111, a central processing unit (CPU)1112, a host interface1113, an error correction block1114, and a memory interface1115. The SRAM1111is used as operation memory of the CPU1112, the CPU1112performs an overall control operation for data exchange of the memory controller1110, and the host interface1113includes a data exchange protocol of a host connected to the memory system1100. In addition, the error correction block1114detects and corrects errors included in data read from the semiconductor memory device1120, and the memory interface1115performs interfacing with the semiconductor memory device1120. In addition, the memory controller1110may further include read only memory (ROM) that stores code data for interfacing with the host.

FIG.8is a block diagram illustrating a configuration of a computing system1200according to an embodiment.

Referring toFIG.8, the computing system1200according to an embodiment of the present disclosure may include a CPU1220, random access memory (RAM)1230, a user interface1240, a modem1250, and a memory system1210electrically connected to a system bus1260. The computing system1200may be a mobile device.

The memory system1210may include a memory semiconductor device1212and a memory controller1211. The semiconductor memory device1212may be configured identically to the semiconductor memory device shown inFIGS.1to4.

Although the detailed description of the present disclosure describes specific embodiments, various changes and modifications are possible without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, and should be determined by the following claims and their equivalents.