Patent ID: 12249634

DETAILED DESCRIPTION

For instance,FIG.1is a cross-section through a known vertical-conduction MOSFET device1, in a Cartesian reference system XYZ comprising a first axis X, a second axis Y, and a third axis Z.

The MOSFET device1is formed by a plurality of elementary cells, only two of which are shown here, which have equal structure, are arranged adjacent in a same die2and are connected together in parallel. They consequently share a source terminal S, a drain terminal D, and a gate terminal G.

The die2comprises a substrate5of silicon carbide, having a first surface5A and a second surface5B. The substrate5accommodates a drain region7, a plurality of body regions10, and a plurality of source regions15.

The drain region7, here of an N type, extends between the first and the second surface5A,5B of the substrate5. A drain contact region9, of conductive material such as metal or silicide, extends on the second surface5B of the substrate5, in direct electrical contact with the drain region7, and forms the drain terminal D of the MOSFET device1.

The body regions10are of P type and extend in the substrate5, at a distance from each other, from the first surface5A.

A superficial portion24of the drain region7is comprised between two adjacent body regions10.

The body regions10further extend along the second axis Y and have here, in top view, the shape of strips.

The source regions15extend each, from the first surface5A of the substrate5, within a respective body region10and are of N type. Each source region15has a width, along the first axis X, smaller than the width of the respective body region10and a depth, along the third axis Z, smaller than the depth of the respective body region10.

Each source region15laterally delimits, together with the adjacent superficial portion24, a channel portion25of a respective body region10.

The MOSFET device1further comprises a plurality of insulated gate regions20. The insulated gate regions20are formed each by a gate insulating layer21, in contact with the first surface5A of the substrate5; a gate conductive region22, typically of polycrystalline silicon, directly overlying the gate insulating layer21; and an insulation layer23, surrounding and sealing the gate conductive region22, together with the gate insulating layer21.

The gate insulating layer21of each insulated gate region20extends on a respective superficial portion24of the drain region7, on two channel regions25adjacent to the respective superficial portion24, and partially on two source regions15adjacent to the respective channel regions25.

The gate conductive regions22have here the shape of strips extending parallel to the second axis Y (see alsoFIG.2) and are electrically connected in parallel to each other and to the gate terminal G of the MOSFET device1, as explained below.

The MOSFET device1further comprises a plurality of body contact regions30.

The body contact regions30are of P+type and extend each from the first surface5A of the substrate5into a respective source region15, in contact with a respective body region10. In the shown embodiment, each source region15accommodates more than one body contact region30.

The body contact regions30are arranged at a distance to each other along the second axis Y, offset to each other along the first axis X, so that, in the cross-section ofFIG.1, they are visible only in the two source regions15on the right and on the left, but not in the central source region15.

The body contact regions30and the source regions15are in direct electrical contact with a source metallization region33, which is, for example, of metal.

As may be noted in particular fromFIG.2, the source metallization region33is generally divided into two portions (designated by33A and33B inFIG.2) arranged adjacent and at a distance to each other, which cover the majority of the first surface5A of the substrate5. The two portions33A and33B of the source metallization region33also form pads for external connection of the MOSFET device1and form the source terminal S of the MOSFET device1.

In addition,FIG.2, two auxiliary source pads34and a gate pad35also extend on the first surface5A of the substrate5. The auxiliary source pads34, the gate pad35, and the source metallization region33are formed in a same layer and therefore have the same, high thickness so as to provide the desired current capability for the source terminal S.

The gate pad35is connected to the gate conductive regions22(represented dashed inFIG.2) through metal connection portions and a resistive network.

In detail, the metal connection portions are formed in the same metal layer as the pads33,34and35and comprise a gate metal ring38A and a gate metal strip or “finger”38B.

In the embodiment shown inFIG.2, the gate pad35is arranged in proximity of a side of the die2, in a median position thereof; the gate metal finger38B extends from the gate pad35towards the opposite side of the die2; and the gate metal ring38A extends peripherally to the die2, in electrical contact with, and as an extension of, the gate pad35.

In particular, in the top view ofFIG.2, the die2has a rectangular shape having a first side2A; a second side2B, opposite the first side2A; a third side2C; and a fourth side2D, opposite the third side2C, wherein the third and fourth sides2C,2D extend parallel to the first axis X, and the first and second sides2A,2B extend parallel to the second axis Y.

In this geometry, the gate pad35is arranged in proximity of the first side2A, the gate metal finger38B extends parallel to the first axis X from the gate pad35to the portion of the gate metal ring38A adjacent the second side2B, and the gate conductive regions22extend parallel to the second axis Y.

The resistive network comprises a first and a second connection portion36A,38B connected to the gate conductive regions22and to the metal connection portions38B,38A, as described hereinafter and shown inFIGS.3and4, where, for simplicity, the gate insulating layer21is not represented.

In particular,FIG.3shows a peripheral edge portion (designated by37) of the die2, for example adjacent to the fourth side2D.

An insulation oxide annular portion40A, for example of silicon oxide, extends over the first surface5A of the substrate5and is covered by a passivation layer42, connected to the insulation layer23.

A delimitation region41, having an opposite conductivity with respect to the substrate5, here of P type, and having an annular shape, extends within the substrate5, approximately underneath the inner edge of the insulation oxide annular portion40A. The delimitation region41surrounds, in the substrate5, an active area44(the limit whereof is represented schematically by a dashed line A); accommodating the conduction regions of the MOSFET device1, including the source regions15and the body regions10(not visible inFIG.3). An implanted region43, here of N+type and ring-shaped, forming a channel stopper, extends underneath the insulation oxide annular portion40A, in proximity of the outer edge thereof and of the sides2A-2D of the die2, at a distance D from the delimitation region41.

The first connection portion36A, of polycrystalline silicon, extends as a ring over and along the inner edge of the insulation oxide annular portion40A. The first connection portion36A is here in direct electrical contact with a gate conductive region22, without interruption, being obtained in the same layer.

FIG.3moreover shows the gate metal ring38A, which extends above the insulation oxide annular portion40A; the gate metal ring38A crosses the passivation layer42and is here in direct electrical contact with the first connection portion36A.

FIG.4shows the connection between the gate metal finger38B and the gate conductive regions22.

In detail, an insulation oxide finger portion40B, formed by the same layer as the insulation oxide annular portion40A, extends over the body5, parallel to the first direction X, as far as and in contact with the sides of the insulation oxide annular portion40A adjacent to the first and second sides2A,2B of the die2. The insulation oxide finger portion40B and the insulation oxide annular portion40A form an edge insulation region40.

The second connection portion36B extends over the insulation oxide finger portion40B and also has an elongated shape in the first direction X. However, the second connection portion36B has a width (in a direction parallel to the second direction Y) greater than the width (in the same direction) of the insulation oxide finger portion40B and therefore extends also on the side of the insulation oxide finger portion40B, where it is directly connected to the gate conductive regions22. Moreover, it is directly connected, at its longitudinal ends, to the insulation oxide annular portion40A.

The insulation layer23covers the second connection portion36B and has an opening46extending parallel to the first direction X, approximately throughout the length of the second connection portion36B. The gate metal finger38B extends through the opening46and is here in direct electrical contact with the second connection portion36B.

The insulation oxide finger portion40B extends on an insulation finger region45, of P type, formed in the body5and extending parallel to the first direction X, between two opposite sides of the delimitation region41, with which it is in direct contact.

The insulation oxide finger portion40B overlies an inactive area47(also referred to as central edge area) that separates two active areas44.

In the example device1, the gate metal finger38B and the gate metal ring38A have the aim of reducing the voltage drop between the gate pad35and the gate conductive regions22due to the resistivity of the resistive network formed by the connection portions36A,36B.

The presence of the metal connection portions38A,38B is, however, disadvantageous in certain applications.

In fact, the gate metal finger38B causes the source metallization to be divided into at least the two portions33A,33B (or even more, in devices that, due to their dimensions, have several gate metal fingers38B). This limits the use of the MOSFET device1in power modules that have clips sintered or soldered on the die2or need particular, costly and/or cumbersome solutions for contacting the source metallization region33.

The presence of the gate metal ring38A in the peripheral edge portion37of the die2moreover is critical during the reliability assessment of the MOSFET device1. In particular, innovative reliability tests that verify the switching behavior in high-humidity environments show that the gate metal ring38A is a weak point of the device.

The metal connection portions38A,38B cause a non-negligible encumbrance, both because of their dimensions and due to the minimum safety space to be provided between the portions33A,33B of the source metallization region33and the gate pad35.

For instance, with the shown configuration, the gate metal ring38A is designed to maintain the distance D inFIG.3between the channel-stopper region43and the delimitation region41. Furthermore, as shown inFIG.4, the distance D′ between the active areas44(areas where the central edge area47and the gate metal finger38B extend) cannot be used for the conduction of the MOSFET device1and represents a waste of area.

FIGS.5-9show a MOSFET device50, with vertical conduction, of silicon carbide.

The MOSFET device50is formed in a die52having a generally parallelepipedal shape, with four lateral surfaces or sides52A-52D and a top surface52E. In particular, in the top view ofFIG.5, the die52has a first side52A; a second side52B, opposite the first side52A; a third side52C; and a fourth side52D, opposite the third side2C, wherein the third and fourth sides52C,52D are parallel to a first axis X of a Cartesian reference system XYZ, and the first and second sides52A,52B are parallel to a second axis Y of the Cartesian reference system XYZ.

The MOSFET device50comprises a plurality of elementary cells (two shown inFIGS.6and7) adjacent to each other and connected together in parallel. They thus share a source terminal S, a drain terminal D, and a gate terminal G.

As may be seen in the cross-sections ofFIGS.6and7, the die52comprises a substrate55of silicon carbide having a first surface55A and a second surface55B. The substrate55accommodates a drain region57, a plurality of body regions60, and a plurality of source regions65, analogous to the respective same-name regions7,10and15ofFIG.1and not described any further herein.

A drain contact region59, of conductive material such as a metal and/or a silicide, extends on the second surface55B of the substrate55, in direct electrical contact with the drain region57, and forms the drain terminal D of the MOSFET device50.

A superficial portion64of the drain region57is comprised between two adjacent body regions60.

Each source region65laterally delimits, together with an adjacent superficial portion64, a channel portion75of a respective body region60.

The MOSFET device50further comprises a plurality of insulated gate regions70. The insulated gate regions70are each formed by a gate insulating region71, in some embodiments, in contact with the first surface55A of substrate55; a gate conductive region72, in some embodiments, directly overlying the gate insulating region71; and a top insulation layer73, surrounding and sealing, together with the gate insulating region71, the gate conductive region72.

Each gate conductive region72is here, in some embodiments, formed by a gate semiconductor portion76, in some embodiments, of polycrystalline silicon, and a gate metal portion77, directly overlying and in direct electrical contact with the gate semiconductor portion76. The gate metal portion77is, in some embodiments, a metal silicide, for example tungsten, titanium, nickel, cobalt, or platinum silicide.

In the embodiment ofFIG.6, the gate metal portion77has the same width (in the direction of the first axis X) as the gate semiconductor portion76; in the embodiment ofFIG.7, the gate-metal region (designated by77′) has a smaller lateral dimension, e.g., width, than the gate semiconductor portion76.

The gate insulating region71of each insulated gate region70extends over a respective superficial portion64of the drain region57, over two channel regions75adjacent to the respective superficial portion64, and partially over two source regions65adjacent to the respective channel regions75.

The gate conductive regions72are electrically connected in parallel to one another and to the gate terminal G of the MOSFET device50, as explained below.

The MOSFET device50further comprises a plurality of body contact regions80(hereinafter also referred to as P-well regions80), analogous to the body contact regions30ofFIG.1.

The P-well regions80and the source regions65are in direct electrical contact with a source metallization region83, for example of metal and/or metal silicide.

In some embodiments, a P-well region80is in lateral contact with a source region65and in vertical contact with a body60.

As may be noted fromFIG.5, the source metallization region83is here formed by a single portion occupying most of the top surface52E of the die50and forms also a pad for external connection of the MOSFET device50.

In addition, two auxiliary source pads84and a gate pad85extend on the first surface55A of the substrate55. The auxiliary source pads84, the gate pad85, and the single source metallization region83are formed in a same layer and therefore have the same high thickness, for example comprised between 1 and 10 μm, so as to provide the desired current capability of the source terminal S.

It is highlighted that, if so desired, the source metallization region83may be formed by several separate portions, instead of a single portion. In any case, in the MOSFET device50, the distance between them is not critical, and no gate metal finger (38B inFIG.1) is present, nor is a gate metal ring (38A inFIG.1).

The gate pad85(here arranged in proximity of the first side52A of the die52, in a middle position) is connected to the gate conductive regions72(represented dashed inFIG.5) through an annular connection region86, which extends in proximity of the periphery of the die52and has a widened portion forming a contact area86A arranged underneath the gate pad85. The annular connection region86is monolithic with the gate conductive regions72, is formed by the same layers, and is obtained by the same process steps for forming the gate conductive regions72, as described in detail hereinafter.

The annular connection region86is visible also in the cross-sections ofFIGS.8and9, wherein, for simplicity, the gate insulating region71is not represented.

In particular,FIG.8shows a peripheral edge portion (designated by87), of the die52, for example adjacent to the second side52B.

An edge insulation region90, here of oxide, extends on the first surface55A of the substrate55.

The edge insulation region90here comprises an oxide layer96and a passivation layer92overlying the latter. The passivation layer92, in proximity of the third and the fourth sides52C,52D of the die52, prosecutes with the top insulation layer73of the insulated gate regions70, which, in the cross-section ofFIG.8, is interrupted by the openings, where the source metallization83extends.

A delimitation region91, having a conductivity opposite that of the substrate55, here of P type and annular shape, extends in the substrate55underneath the edge insulation region90, in proximity of, but at a distance from, the inner edge of the latter. The delimitation region91surrounds, in the substrate55, an active area94(whose limit is represented schematically by a dashed line B), accommodating the conduction regions of the MOSFET device50, including the body regions60and the source regions65. A channel-stopper region93, here of N+type and annular shape, extends underneath the edge insulation region90, in proximity of the sides52A-52D of the die52, at a distance D1from the delimitation region91, to balance the potential in the edge area.

The annular connection region86extends in an annular way only along the inner edge of the edge insulation region90and does not have portions extending between active areas.

As mentioned above, the annular connection region86is formed monolithically with the gate conductive regions72as a stack of two layers.

In particular, the annular connection region86comprises a semiconductor connection portion88and a metal connection portion89, directly overlying and in direct electrical contact with the semiconductor connection portion88.

Moreover, the material of the semiconductor connection region88is the same of the gate semiconductor portions76(typically of polycrystalline silicon), and the material of the metal connection portion89is the same of the gate metal portions77(typically a metal silicide, for example tungsten, titanium, nickel, cobalt, or platinum silicide).

The stack of layers forming the gate semiconductor portions76and the annular connection region86forms a gate bias layer95.

As may be noted fromFIG.8, the annular connection region86extends only to a minimal extent on the edge insulation region90and has a very small width, for example comprised between 10 and 50 μm. In addition, the delimitation region91has also a small width (in the first direction X, in the cross-section ofFIG.8), for example comprised between 20 and 50 μm. In this way, the width of the peripheral edge portion87is reduced, and it is also possible to accordingly increase the dimensions of the active area94, for same dimensions of the dice2-52.

Furthermore, as may be seen fromFIG.9(analogous to and to be compared withFIG.4representing the known MOSFET device1), in the central area of the MOSFET device50no inactive edge area extends, due to the absence of gate metallization portions.

Consequently, in the MOSFET device50, the passivation layer92/73completely covers the metal connection portion89of the annular connection region86at the top, and there are no openings or conductive regions through the passivation layer92/73, nor are there surface metal portions providing a direct electrical contact between the top surface of the annular connection region86and the gate metallization85. Biasing of the annular connection region86occurs in fact only at its portions contiguous with the contact area86A.

The MOSFET device50thus has a wide active area94and therefore effectively exploits the area of the die52.

FIGS.10and11show two possible layouts of the gate bias layer95.

In particular,FIG.10shows the layout of the gate bias layer95corresponding to what is shown inFIG.5, with the contact area86A arranged peripherally.

As may be noted, the annular connection region86has a first and a second branch86B,86C, which extend along and in proximity of two opposite sides of the body52(and precisely, in the embodiment shown inFIG.10, along the third and fourth sides52C,52D of the die52), and the gate conductive regions72extend continuously between the first and second branches86B,86C of the annular connection region86.

FIG.11shows a different layout of the gate bias layer, here designated by95′.

Also here, the gate conductive regions72extend continuously between the first and second branches86B,86C of the annular connection region86. The gate conductive regions72arranged most centrally have a widened central portion which is common to different gate conductive regions72and forms a contact area86A′ on which the gate pad85extends.

In this case, biasing of the annular connection region86occurs only through the gate conductive regions72that connect the annular connection region86to the contact area86A′.

In general, with the MOSFET device50, the position of the gate pad85and therefore of the contact area86A,86A′ can be chosen with high freedom, according to the applications and possible customer desires.

The MOSFET device52ofFIGS.5,6and8-11may be manufactured by depositing/forming a silicide layer before or after defining the gate semiconductor portions76of the gate conductive regions72.

For instance,FIG.12Ashows a wafer100of silicon carbide (for example of a 3C—SiC, 4H—SiC or 6H—SiC type) intended to form, after dicing, the die52ofFIG.6. In particular, inFIG.12A, the source regions65, the body regions60, and the P-well regions80are already formed within the substrate55, as likewise the various edge regions (including the delimitation region91and the channel-stopper region93ofFIG.8), here not visible.

A gate insulating layer101, a gate conductive layer102, and a silicide layer103have already been deposited, in sequence, on the first surface55A of the substrate55.

The gate insulating layer101is, for example, silicon oxide and is intended to form the gate insulating regions71.

The gate conductive layer102is typically polycrystalline silicon and is designed to form the gate semiconductor portions76of the gate conductive regions72and the semiconductor connection portion88.

The silicide layer103is, for example, tungsten silicide (WSi2) and is intended to form the gate metal portions77and the metal connection portion89(FIGS.6and8).

After a stabilization annealing process, for example at a temperature comprised between 700° C. and 1000° C., the silicide layer103, the gate conductive layer102, and the gate insulating layer101are defined in a known way, by a photolithographic process and using the same etching mask (FIG.12B).

Thereby, the gate conductive regions72(FIGS.6and12B), the annular connection region86(FIG.8) and the gate insulating regions7are formed. Furthermore, the gate metal portions77and the gate semiconductor portions76are self-aligned to each other, as likewise the metal connection portion89and the semiconductor connection portion88.

Then usual steps for forming the top insulation layer73, the passivation layer92, and the metallizations83-85follow.

In particular, while forming the passivation layer92, no openings are made for directly contacting the annular connection region86.

FIGS.13A-13Cshow steps of a different embodiment of a manufacturing process of the MOSFET device50ofFIGS.5,6and8-11.

In detail,FIG.13Ashows a portion of wafer100. In the step ofFIG.13A, the source regions65, the body regions60, and the P-well regions80, as well as the various edge regions, have already been formed in the substrate55.

Moreover, the gate insulating layer101has already been deposited on the first surface55A of the substrate55, and the gate semiconductor portions76of the gate conductive regions72, as well as the semiconductor connection portion88, have already been formed, for example by depositing and photolithographically defining a polycrystalline silicon layer.

A sacrificial layer105, for example, of silicon oxide, is deposited on the gate semiconductor portions76and on the gate insulating layer101, where exposed.

Then (FIG.13B), the sacrificial layer105is etched to form spacers106(spacer etching). To this end, etching is of a non-masked, dry, directional type (plasma etching). Due to the etch anisotropy, the horizontal portions of the sacrificial layer105are removed, and the spacers106are formed on the vertical walls of the gate semiconductor portions76. In this step, also the portions of the gate insulating layer101not covered by the gate semiconductor portions76and by the spacers106, on the source regions65, are eliminated, forming the gate insulating regions71.

Similar spacers (not shown) form on the lateral surfaces of the semiconductor connection portion88(FIG.8).

Next (FIG.13C), a metal layer (for example, titanium or nickel) is deposited by sputtering and reacts with the polycrystalline silicon of the gate semiconductor portions76and (in a way not shown) of the semiconductor connection portion88(FIG.8). To this end, a first annealing is carried out at a low temperature, for example comprised 600° C. and 1000° C.

Then, the non-reacted metal material (for example, on the spacers106) is removed, and a second annealing is carried out at a higher temperature, for example comprised between 800° C. and 1100° C.

The gate metal portions77of the gate conductive regions72and the metal connection portion89of the annular connection region86(FIG.8) are thus formed.

Consequently, also in this case, then, the gate metal portions77are self-aligned with the respective gate semiconductor portions76, and the metal connection portion89is self-aligned with the semiconductor connection portion88.

In this step, a thin silicide layer may form on the exposed portions of the substrate55, in particular on the source regions65and on the P-well regions80; these portions may be removed by an appropriate etch or left, according to the specific process.

The process proceeds with the usual steps for forming the top insulation layer73, the passivation layer92, and the metallizations83-85.

FIGS.14A-14Bshow steps of an embodiment of a process for manufacturing the MOSFET device50ofFIGS.5,7and8-11.

In particular,FIG.14Ashows a wafer100′ after performing the manufacturing steps already described forFIG.13A.

In particular, in the wafer100′, the source regions65, the body regions60, and the P-well regions80, as well as the various edge regions, have already been formed in the substrate55.

The gate insulating layer101has already been deposited on the first surface55A of the substrate55.

The gate semiconductor portions76of the gate conductive regions72, as well as the semiconductor connection portion88(not visible inFIG.14A) have already been formed, for example by depositing and photolithographically defining a polycrystalline silicon layer.

A sacrificial layer115, for example, silicon oxide, has been deposited on the gate semiconductor portions76and on the gate insulating layer101, where exposed.

Then (FIG.14B), a gate contact mask (not shown) is formed on the sacrificial layer115, and the sacrificial layer115is selectively removed on the gate semiconductor portions76and on the semiconductor connection portion88(not visible inFIG.14B). Masking portions115′ covering the sides and the longitudinal edges of the gate semiconductor portions76and of the semiconductor connection portion88, as well as the gate insulating layer101, where exposed, are thus formed.

Then, a metal layer (for example, of titanium, cobalt, or platinum) is deposited by sputtering and caused to react with the polycrystalline silicon of the gate semiconductor portions76and (in a way not shown) of the semiconductor connection portion88(FIG.8). To this end, a first annealing at low temperature, for example comprised between 600° C. and 1000° C., is carried out.

Then, the non-reacted metal material (on the masking portions115′) is removed, and a second annealing is carried out at a higher temperature, for example comprised between 800° C. and 1100° C.

The gate metal portions77of the gate conductive regions72and the metal connection portion89of the annular connection region86are thus formed (FIG.8).

Next, the remaining, non-reacted, portions of the sacrificial layer105are removed, and the further steps for forming the top insulation layer73, the passivation layer92, and the metallizations83-85are carried out.

The MOSFET device50thus formed has many advantages.

In particular, it has a simplified structure, with increase of the active area, thanks to the size reduction of the peripheral edge areas and elimination of the inner edge area.

The MOSFET device50has an improved gate resistance Rg, since it has no waste of area due to the metal connection portions.

The MOSFET device50moreover has excellent robustness and may be used also in high-current and/or high-voltage applications. For instance, it is able to work at voltages up to 10 kV or currents up to 500 A.

The MOSFET device50has improved reliability because the structure is simplified and the polysilicon of the gate semiconductor portions76does not require a particular doping. Consequently, there is no precipitation of dopant (typically, phosphorus) from the gate conductive regions72into the gate insulating region71. In this way, the latter region, typically of oxide, presents a high reliability.

Since, in MOSFET devices that use silicon carbide substrates, all the junctions, implanted regions, and enriched contact regions are activated before forming the layers and regions on the surface of the substrate55, the process has a low thermal budget after forming the silicide portions77,89; consequently, these portions have excellent thermal stability.

In addition, the external contact structures (clips) that are brought into contact with the source metallization83during assembly and packaging of the MOSFET device50may be simplified, reducing costs and improving the current conduction reliability.

Finally, it is clear that modifications and variations may be made to the MOSFET device and to the manufacturing process described and shown herein, without thereby departing from the scope of the present disclosure, as defined in the attached claims.

For instance, in the embodiment of the process ofFIGS.12A-12B, the silicide layer103may be obtained by reacting a metal layer deposited on the gate conductive layer102.

A vertical-conduction MOSFET device may be summarized as including: a body of silicon carbide having a first and a second face and a peripheral zone, the body accommodating: a first current conduction region, of a first conductivity type, extending in the body from the second face and having a superficial portion facing the first face; a body region, of a second conductivity type, extending in the body from the first face; and a second current conduction region, of the first conductivity type, extending to the inside of the body region from the first face of the body, the second current conduction region delimiting in the body region, together with the superficial portion, a channel portion; an insulated gate region, extending on the first face of the body and overlying the channel portion, the insulated gate region including a gate conductive region; and a surface edge structure, extending on the first face of the body, in the peripheral zone of the body, the surface edge structure including an annular connection region, of conductive material, wherein the gate conductive region and the annular connection region are formed by a gate bias layer including a silicon layer and a metal silicide layer overlying the silicon layer.

The silicon layer may be a polycrystalline layer.

The metal silicide layer may be selected from tungsten, titanium, nickel, cobalt, or platinum silicide.

The gate conductive region may include a gate semiconductor portion formed by the silicon layer and a gate metal portion formed by the metal silicide layer, and the annular connection region may include a semiconductor connection portion formed by the silicon layer and a metal connection portion formed by the metal silicide layer.

The surface edge structure may include a passivation layer completely covering the metal connection portion of the annular connection region.

The gate semiconductor portion may have a first width, the gate metal portion may have a second width, the semiconductor connection portion may have a third width, and the metal connection portion may have a fourth width, wherein the first width is equal to the second width and the third width may be equal to the fourth width.

The gate semiconductor portion may have a first width, the gate metal portion may have a second width, the semiconductor connection portion may have a third width, and the metal connection portion may have a fourth width, wherein the first width may be greater than the second width and the third width may be greater than the fourth width.

The first face of the body has an area and a central portion, the vertical-conduction MOSFET device may further include a conduction contact metal region extending on the first face of the body in direct electrical contact with the second current conduction region, the conduction contact metal region may include a single contact portion covering most of the area of the first face and extending without interruption over the central portion of the first face.

The body may have two opposite lateral surfaces, the annular connection region may have a first and a second branch extending near the opposite lateral surfaces of the body, and the gate conductive region may extend with continuity between the first and second branches of the annular connection region.

A process for manufacturing a vertical-conduction MOSFET device according to claim1, may be summarized as including: in a body of silicon carbide having a first and a second face and a peripheral zone and accommodating a first current conduction region of a first conductivity type, extending in the body from the second face and having a superficial portion facing the first face, forming a body region, of a second conductivity type extending in the body from the second face; in the body region, forming a second current conduction region, of the first conductivity type, extending from the first face of the body, the second current conduction region delimiting in the body region, together with the superficial portion, a channel portion; forming an insulated gate region on the first face of the body, in a position overlying the channel portion, the insulated gate region including a gate conductive region; and forming a surface edge structure extending on the first face of the body, on the peripheral zone of the body, the surface edge structure including an annular connection region of conductive material, wherein forming the gate conductive region and forming the annular connection region including forming a gate bias layer including a silicon layer and a metal silicide layer overlying the silicon layer.

Forming a gate bias layer may include: depositing the silicon layer on the first face of the body; forming the metal silicide layer on the silicon layer; and photolithographically defining the silicon layer and the metal silicide layer, thereby forming the gate conductive region and the annular connection region.

Forming a gate bias layer may include: depositing the silicon layer on the first face of the body; photolithographically defining the silicon layer to form a gate semiconductor portion and a semiconductor connection portion, the gate semiconductor portion and the semiconductor connection portion having lateral surfaces; forming spacers on the lateral surfaces; depositing a metal layer in direct contact with the gate semiconductor portion and with the semiconductor connection portion; and reacting the metal layer, thus obtaining a gate metal portion in contact with the gate semiconductor portion, and a metal connection portion in contact with the semiconductor connection portion.

Forming a gate bias layer may include: depositing the silicon layer on the first face of the body; photolithographically defining the silicon layer to form a gate semiconductor portion and a semiconductor connection portion, the gate semiconductor portion and the semiconductor connection portion having lateral surfaces and longitudinal edges; forming masking portions covering the lateral surfaces and the longitudinal edges of the gate semiconductor portions and of the semiconductor connection portion; depositing a metal reaction layer in direct contact with the gate semiconductor portion and with the semiconductor connection portion, where exposed by the masking portions; and reacting the metal reaction layer, thus obtaining a gate metal portion in contact with the gate semiconductor portion, and a metal connection portion in contact with the semiconductor connection portion.

Reacting the metal reaction layer may include performing an annealing and may further include removing non-reacted portions of the metal reaction layer.

The silicon layer is polycrystalline silicon, and the metal reaction layer may be selected from tungsten, titanium, nickel, cobalt, and platinum.

The annular connection region may include a semiconductor connection portion formed by the silicon layer, and a metal connection portion formed by the metal silicide layer, and the process may further include depositing a passivation layer completely covering the metal connection portion of the annular connection region.

The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various embodiments to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.