Patent ID: 12199193

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. However, the same reference numerals may refer to like elements across different embodiments and different figures, and thus the drawings and associated descriptions may be incorporated across figures when not conflicting or may stand alone as independent embodiments. Also, varies cross-sectional views can either be associated with schematic views and/or cross-sectional views along other directions or lines, or stand alone as independent embodiments.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Still further, as used herein, the articles “a” and “an” preceding an element or component are intended to be nonrestrictive regarding the number of instances (i.e. occurrences) of the element or component. Therefore, “a” or “an” should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular.

Still further, as used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. Yet, in another aspect, the term “about” means within 1% of the reported numerical value.

For some integrated chips involving three-dimensional devices, capacitors such as metal-insulator-metal (MIM) capacitors are inserted in a back-end-of-line (BEOL) to be used as a part of the processing circuit. However, the BEOL interconnect wires introduce RC delays that may affect performance of the processing circuit. Also, the location of these capacitors in the BEOL restricts design flexibility and may affect chip integration when three-dimensional stacking of multiple dies is needed. For example, a CMOS image sensor (CIS) chip includes an image sensing die and an image signal processor (ISP) die one stacked over another. The image sensing die has color filters locating at its back-side configured to receive and filter incoming radiations and photodiodes underlying the color filters and configured to convert radiation to electrical signals. The ISP die includes a read-out circuit that receives and processes the electrical signals. The read-out circuit includes some capacitor components. These capacitor components can be metal-insulator-metal (MIM) capacitors that are inserted in the back-end-of-line (BEOL). However, the utilization of the BEOL MIM capacitors affects bonding interface of the image sensing die and the ISP die, and also introduces image distortion due to the RC delay introduced by the BEOL interconnect wires.

In view of the above, the present disclosure relates to a FinFET MOS capacitor that can be integrated in front-end-of-line (FEOL) with FinFET transistor devices. In some embodiments, the FinFET MOS capacitor comprises a capacitor fin structure extending upwardly from an upper surface of a substrate. The capacitor fin structure comprising a pair of dummy source/drain regions separated by a dummy channel region. The dummy channel region is heavily doped and function as one terminal of the FinFET MOS capacitor. A capacitor gate structure straddles on the capacitor fin structure and is separated from the capacitor fin structure by a capacitor gate dielectric. The capacitor gate structure functions as the other terminal of the FinFET MOS capacitor, and the capacitor gate dielectric function as a capacitor dielectric. The capacitor gate dielectric is thin and thus a greater capacitance can be achieved by the FinFET MOS capacitor compared to the previous MIM or metal-oxide-metal (MOM) capacitor.

In some embodiments, the dummy channel region is doped by a series of non-uniform doping steps such that multiple doped layers are one vertically stacked next to another. The dummy channel region may have a doping concentration greater than the pair of dummy source/drain regions. By controlling doped region of the dummy channel region, linearity of the FinFET MOS capacitor is enhanced. Since the dummy channel region of the capacitor fin structure may be doped by a series of ion implantation processes to form the multiple doped layers, the dummy channel region of the capacitor fin structure becomes more amorous compared to the fin structure of the FinFET transistor device. Thus, the dummy channel region of the capacitor fin structure may be consumed more when a thermal oxide process is performed to form gate dielectric. As a result, the capacitor fin structure may have a more tapered upper portion and a narrower width than the transistor fin structure, and the formed gate dielectric may have a greater width wrapping around sidewall and top surfaces of the dummy fin structure than that of the transistor fin structure.

FIG.1illustrates a schematic view of some embodiments of a FinFET MOS capacitor100. As shown inFIG.1, a substrate102may comprise an upper portion including a plurality of capacitor fin structures104extending upwardly from a planar lower portion. The isolation dielectric layer107may comprise silicon dioxide or other applicable dielectric materials. The capacitor fin structures104respectively comprises a pair of dummy source/drain regions106a/106bseparated by a dummy channel region110. Unlike channel region for a transistor device, the dummy channel region110is heavily doped to increase conductivity such that the dummy channel region110behaves more like a good conductor (metal) and function as one terminal of the FinFET MOS capacitor100. The dummy channel region110has a doped region112that have a doping type (e.g., n-type or p-type) same with the doping type of the source/drain regions106a/106b. The doped region112may have a doping concentration greater than the pair of dummy source/drain regions106a/106b. In some embodiments, the dummy channel region110may have a doping concentration more than twice greater than the pair of dummy source/drain regions106a/106b. In some embodiments, the dummy channel region110comprises multiple doped layers one vertically stacked next to another. By controlling doped region of the dummy channel region110, linearity of the FinFET MOS capacitor100is enhanced. For example, in some embodiments, the doped region112has a doping concentration about 2.5 times greater than that of the dummy source/drain regions106a/106b, and has four doped layers one vertically stacked next to another. A resulting capacitance linearity is smaller than about 3%. The capacitance linearity defines a capacitance dependence of the applied gate bias.

A capacitor gate stack120straddles on the plurality of the capacitor fin structures104overlying the dummy channel region110. The capacitor gate stack120may wrap a first sidewall, a top surface, and a second sidewall of respective capacitor fin structures104. As shown in more details associated with cross-sectional views ofFIGS.2-4below, the capacitor gate stack120comprises a capacitor gate structure118separated from the capacitor fin structure104by a capacitor gate dielectric108. The capacitor gate structure118functions as the other terminal of the FinFET MOS capacitor100, and the capacitor gate dielectric108functions as a capacitor dielectric. The capacitor gate dielectric is thin and thus a greater capacitance can be achieved by the FinFET MOS capacitor compared to the previous MIM or metal-oxide-metal (MOM) capacitor.

The substrate102may comprise any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.). The capacitor fin structures104may be bulk semiconductor material fins or other three-dimensional structures such as vertically stacked nanowires, nano-dots, or other applicable structures. An isolation dielectric layer107may be disposed on the planar lower portion of the substrate102providing isolation function for the substrate102. In some embodiments, the capacitor gate stack120has a bottom surface reaching on an upper surface of the isolation dielectric layer107.

FIG.2andFIG.3illustrate cross-sectional views of varies embodiments of a FinFET MOS capacitor along line A-A′.FIG.2may be a cross-sectional view of some embodiments of the FinFET MOS capacitor100ofFIG.1along line A-A′. As shown inFIG.2, in some embodiments, the capacitor fin structures104comprises the pair of source/drain regions106a/106bspaced apart by the dummy channel region110. The doped region112is arranged within the dummy channel region110. As shown inFIG.3, in some alternative embodiments, the pair of source/drain regions106a/106bmay be arranged at an upper portion of the capacitor fin structures104. The doped region112may be arranged across upper regions of the pair of source/drain regions106a/106band the dummy channel region110. A capacitor gate stack120is disposed between the source/drain regions106a/106boverlying the dummy channel region110. In some embodiments, the capacitor gate stack120comprises the capacitor gate structure118separated from the dummy channel region110by the capacitor gate dielectric108. The doped region112may have a doping concentration greater in an inner region of the dummy channel region110than an outer region of the dummy channel region in lateral directions along plane of the substrate102such as both X direction and Y direction.

FIG.4illustrates a cross-sectional view of some embodiments of a FinFET MOS capacitor.FIG.4may be a cross-sectional view of some embodiments of the FinFET MOS capacitor100ofFIG.1along line B-B′. As shown inFIG.3, the doped region112is arranged in an upper region of the dummy channel regions110. The capacitor gate stack120straddles on the plurality of the capacitor fin structures104overlying the dummy channel region110. The capacitor gate dielectric108is disposed between the capacitor fin structures104and the capacitor gate structure118, wrapping a first sidewall, a top surface, and a second sidewall of respective capacitor fin structures104, and functioning as a capacitor dielectric. By this multiple fin structures, the capacitor area is enlarged without increasing the lateral footprint of the capacitor, and thus a greater capacitance can be achieved by the FinFET MOS capacitor100.

FIG.5illustrates a schematic view of some embodiments of an integrated circuit500comprising a FinFET MOS capacitor100and a FinFET transistor100′ integrated in one substrate102. Similar as discussed above associated withFIGS.1-4, the FinFET MOS capacitor100comprises a plurality of capacitor fin structures104respectively having a pair of dummy source/drain regions106a/106bseparated by a dummy channel region110. A capacitor gate stack120straddles on the plurality of the capacitor fin structures104overlying the dummy channel region110. The capacitor gate stack120comprises a capacitor gate structure118separated from the capacitor fin structure104by a capacitor gate dielectric108. The FinFET transistor100′ comprises a plurality of transistor fin structures104′ respectively having a pair of source/drain regions106a′/106b′ separated by a channel region110′. A transistor gate stack120′ straddles on the plurality of the transistor fin structures104′ overlying the channel region110′. The transistor gate stack120′ comprises a transistor gate structure118′ separated from the transistor fin structures104′ by a transistor gate dielectric108′. It is noted that the FinFET MOS capacitor100and the FinFET transistor100′ are shown as one next to another for illustration convenience and simplicity. Other device components and structures may be arranged between the FinFET MOS capacitor100and the FinFET transistor100′.

FIG.6illustrates a cross-sectional view of some embodiments of an integrated circuit.FIG.6may be a cross-sectional view of some embodiments of the integrated circuit500ofFIG.5along line A-A′. For FinFET transistor100′, the channel region110′ may be intrinsic or lightly doped with a doping type opposite with that of the source/drain regions106a′/106b′, and current in the channel region110′ is controlled by a gate voltage applied to the transistor gate stack120′. The source/drain regions106a′/106b′ are heavily doped and a drain bias is applied across the source/drain regions106a′/106b′ during the operation. For FinFET MOS capacitor100, the dummy channel region110is heavily doped with a doping type same with that of the dummy source/drain regions106a/106b. A doping concentration of the dummy channel region110may be greater than the pair of dummy source/drain regions106a/106b. In some embodiments, the dummy source/drain regions106a/106band the dummy channel region110are n-type doped. In some alternative embodiments, the dummy source/drain regions106a/106band the dummy channel region110are p-type doped. The dummy source/drain regions106a/106bmay have a doping concentration substantially same with that of the source/drain regions106a′/106b′ of the same doping type. In some embodiments, the dummy channel region110comprises the doped region112with multiple doped layers one vertically stacked next to another. The doped region112may have a doping concentration greater in an inner region of the dummy channel region110than an outer region of the dummy channel region in X direction. The dummy channel region110and the dummy source/drain regions106a/106bmay collectively function as one terminal of the FinFET MOS capacitor100. By controlling doped region of the dummy channel region110, linearity of the FinFET MOS capacitor100is enhanced.

FIG.7illustrates a cross-sectional view of some embodiments of an integrated circuit.FIG.7may be a cross-sectional view of some embodiments of the integrated circuit500ofFIG.5along line B-B′. As discussed above, for FinFET MOS capacitor100, upper portions of the dummy channel regions110of the plurality of capacitor fin structures104are heavily doped. In some embodiments, the dummy channel region110comprises the doped region112with multiple doped layers one vertically stacked next to another. The doped region112may have a doping concentration greater in an inner region of the dummy channel region110than an outer region of the dummy channel region in Y direction. In comparison, for FinFET transistor100′, the channel region110′ of the plurality of transistor fin structures104′ may be intrinsic or lightly doped.

FIG.8illustrates a cross-sectional view of some additional embodiments of an integrated circuit.FIG.8may be a cross-sectional view of some embodiments of the integrated circuit500ofFIG.5along line B-B′. In some embodiments, the capacitor fin structure104has an upper portion more tapered than that of the transistor fin structure104′. The capacitor fin structure104may have a more amorphous outer peripheral than that of the transistor fin structure104′. The capacitor fin structure104may have a width smaller than that of the transistor fin structure104′. The capacitor gate dielectric108may have a width greater than that of the transistor gate dielectric108′. The capacitor fin structure104may have a height substantially equal to that of the transistor fin structure104′.

In some embodiments, the capacitor gate dielectric108and the transistor gate dielectric108′ may comprise an interfacial dielectric layer114and a high-k dielectric layer116disposed on the interfacial dielectric layer114. The capacitor gate structure118and the transistor gate structure118′ may comprise a work function metal layer122and a bulk metal gate layer124. As shown inFIG.7, the interfacial dielectric layer114may have a first width w for the FinFET MOS capacitor100and a second width w′ for the FinFET transistor100′. The first width w is greater than the second width w′.

In some embodiments, the FinFET MOS capacitor100or the integrated circuit500may be a part of a front-end-of-line (FEOL) of an image signal processor (ISP) chip that is bonded to a CMOS image sensor (CIS) chip as one integrated chip. The integrated chip may be an image sensing chip configured to receive a radiation and convert the radiation to electronic signals and may further process such electronic signals. The ISP chip may include logic core devices and I/O devices disposed on one substrate and a first interconnect structure disposed over and electrically coupled to the I/O devices. The CIS chip may include radiation sensing components such as filters and photodiodes and a second interconnect structure disposed over and electrically coupled to the sensing components. The ISP chip and the CIS chip may be bonded together by applicable bonding techniques. In some embodiments, the ISP chip and the CIS chip are bonded face to face having the first interconnect structure and the second interconnect structure face each other. The FinFET MOS capacitor may be integrated in front-end (FEOL) of the ISP chip together with other logic devices and the I/O devices, and is disposed between the first interconnect structure and the substrate of the ISP chip.

FIGS.21A-21Billustrate cross-sectional views of an integrated circuit according to some additional embodiments.FIG.21Ashows a transistor region2100aof the integrated circuit, andFIG.21Bshows a capacitor region2100bof the integrated circuit.FIG.21AandFIG.21Bmay be cross-sectional views of some embodiments of the integrated circuit500ofFIG.5along a direction of line B-B′. Similar as described above, in some embodiments, the transistor fin structure104′ of the transistor region2100aand the capacitor fin structure104of the capacitor region2100bare surrounded by an interfacial dielectric layer114, a high-k dielectric layer116disposed on the interfacial dielectric layer114, a work function metal layer122, and a bulk metal gate layer124. In some embodiments, the capacitor fin structure104is heavily doped such that the linearity of the FinFET MOS capacitor100is enhanced. In some embodiments, the capacitor fin structure104is doped with a doping concentration greater than that of the pair of dummy source/drain regions106a/106bas shown inFIG.5. In some embodiments, the capacitor fin structure104is doped with a doping concentration more than 2.5 times greater than that of the pair of dummy source/drain regions106a/106b. In some embodiments, the capacitor fin structure104has an upper portion more tapered than that of the transistor fin structure104′. Because of the high doping concentration, the capacitor fin structure104may have a more amorphous outer peripheral next to the interfacial dielectric layer114than that of the transistor fin structure104′. In some embodiments, an amorphous region104aof the capacitor fin structure104above a fin height line2102is more than about 50% of the whole volume of the capacitor fin structure104above the fin height line2102. An amorphous region104bof the capacitor fin structure104below the fin height line2102is about 10% of the whole volume of the capacitor fin structure104below the fin height line2102. The great level of amorphous is the result of the heavy doping of capacitor fin structure104, which would result in an enhanced linearity of the FinFET MOS capacitor100. For example, a resulting capacitance linearity is smaller than about 3%. Without such a high doping level or amorous level as disclosed above, the capacitance linearity may suffer. Also as a result of heavy doping of the capacitor fin structure104, the capacitor fin structure104may have a width smaller than that of the transistor fin structure104′, and the interfacial dielectric layer114may have a first width w in the capacitor region2100bgreater than a second width w′ in the transistor region2100a. In some embodiments, a surface area of the capacitor fin structure104of a sum of upper, lower and sidewall surfaces is about 2.5 times of a corresponding lateral planar surface area, and a resulting capacitance of the capacitor fin structure104is about twice of capacitance of a corresponding planar capacitor. The capacitor fin structure104is difficult to be formed and doped if the sum of upper, lower and sidewall surfaces is greater than about 5 times of the corresponding lateral planar surface area, and the benefit of enlarging surface area is minimal if the urn of upper, lower and sidewall surfaces is smaller than about 1.2 times of the corresponding lateral planar surface area.

FIGS.9-19illustrate a series of cross-sectional views900-1900of some embodiments for forming an integrated circuit having a FinFET MOS capacitor, such as the integrated circuit500shown inFIG.5.FIGS.9-19show different stages of a manufacturing process and can be cross-sectional views taken from one direction of the integrated circuit, such as taken from Y direction shown inFIG.5.

As shown inFIG.9, a substrate102is prepared. In some embodiments, a plurality of fin structures104,104′ is formed from an upper portion of the substrate102. The substrate102may comprise any type of semiconductor body (e.g., monocrystalline silicon/CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.). The fin structures104,104′ may be patterned by varies methods. For example, the fin structures104,104′ may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a mandrel layer (not shown) is formed over a hard mask layer and patterned using a photolithography process. The hard mask layer may be made of one or more dielectric material such as a silicon nitride layer on a pad oxide layer. Then, a spacer is formed alongside the patterned mandrel layer using a self-aligned process. The mandrel layer is then removed, and the spacer is used to pattern the hard mask layer to form a hard mask902that is then used to pattern the fin structures104,104′.

As shown inFIG.10, an isolation dielectric layer107is formed surrounding the fin structures104,104′. The isolation dielectric layer107may comprise silicon dioxide or other applicable dielectric materials, such as a nitride, a carbide, or the like. The isolation dielectric layer107can be formed by a deposition process followed by a planarization process to be co-planar with the hard mask902. The isolation dielectric layer107is then etched back to a position between top and bottom surfaces of the hard mask902.

As shown inFIG.11, the hard mask902is removed, and top surfaces of the fin structures104,104′ are exposed. The hard mask removal process may comprise wet etching processes and/or dry etching processes.

As shown inFIG.12, a sacrificial layer1202is formed lining the top surfaces of the fin structures104,104′. As an example, the sacrificial layer1202can be formed by a thermal oxidation process such as an in-situ steam generation (ISSG) process.

As shown inFIG.13, a series of ion implantation processes is performed to form doping wells in fin structures104,104′ and a doped region112in the capacitor fin structures104. The transistor fin structures104may be covered and protected by a protection layer1302from the implantation when forming the doped region112in the capacitor fin structures104. In some embodiments, the doped region112may be formed using an angled ion implantation process. In some embodiments, the doped region112is formed with multiple doped layers one vertically stacked next to another. The doped region112may be formed in an upper region of the dummy channel region110having a doping concentration greater in an inner region than an outer region of the dummy channel region in lateral directions. For example, in some embodiments, the doped region112is formed by four ion implantation processes with ion dosage and energy increasing from a top doped layer near surface to a bottom doped layer deep in the dummy channel region110to form four doped layers one vertically stacked next to another. The resulting doped layers may each have a greater thickness from top to bottom. A resulting capacitance linearity is smaller than about 3%. The capacitance linearity defines a capacitance dependence of the applied gate bias. By controlling doped region of the dummy channel region110, linearity of the FinFET MOS capacitor100is enhanced.

As shown inFIG.14, an annealing process is performed. The annealing process can be performed by a rapid thermal annealing (RTA) method. The doped region112is settled after the annealing process.

As shown inFIG.15, the isolation dielectric layer107is etched back to a lower position to expose an upper portion of the fin structures104,104′. The sacrificial layer1202is also removed during this process.

As shown inFIG.16, a gate dielectric layer1602and a gate electrode layer1604are formed overlying the fin structures104,104′. In some embodiments, the gate dielectric layer1602and the gate electrode layer1604are formed by a deposition process followed by a patterning process. In some embodiments, the gate dielectric1602may comprise, for example, an oxide (e.g., SiO2), a high-k dielectric material (e.g., HfO2, ZrO2, or some other dielectric material with a dielectric constant greater than about 3.9), some other dielectric material, or a combination of the foregoing. In yet further embodiments, the gate dielectric layer1602may be deposited or grown by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or some other deposition or growth process. In some embodiments, the gate electrode layer1604, may comprise, for example, polysilicon. The gate electrode layer1604may be deposited or grown by CVD, PVD, ALD, epitaxy, sputtering, or some other deposition or growth process. The gate dielectric layer1602and the gate electrode layer1604are patterned into an initial gate stack1702(seeFIG.17). In some embodiments, a process for forming the initial gate stack1702comprises forming a masking layer1704over/on the gate electrode layer1604and patterning the gate electrode layer1604and the gate dielectric layer1602according to the masking layer1704by an etch (e.g., wet/dry etch). The etch removes unmasked portions of the gate dielectric layer1602and the gate electrode layer1604. Subsequently, the masking layer1704may be stripped or etched away.

As shown inFIG.17, dummy source/drain regions106a/106bof the FinFET MOS capacitor100and source/drain regions106a′/106b′ of the FinFET transistor100′ are formed at opposite sides of the fin structures104,104′. The source/drain regions106a/106b,106a′/106b′ may be formed by a series of ion implantation processes to form doping regions. In some embodiments, the dummy source/drain regions106a/106band the source/drain regions106a′/106b′ are formed by an ion implantation process and may utilize a masking layer (not shown) to selectively implant ions into the substrate102. In further embodiments, the initial gate stack1702and a sidewall spacer (not shown) may be utilized as the masking layer to form the dummy source/drain regions106a/106band the source/drain regions106a′/106b′. In some embodiments, lightly-doped source/drain extensions (LDDs) may be formed in the substrate102on opposite sides of the initial gate stack1702. In some embodiments, the LDDs are formed by an ion implantation process and may utilize a masking layer (not shown) to selectively implant ions in the fin structures104,104′. In further embodiments, the initial gate stack1702may be utilized as the masking layer to form the LDDs.

As shown inFIG.18andFIG.19, a replacement gate process may be performed to remove the gate dielectric layer1602and a gate electrode layer1604and replace with high-k dielectric material and metal gate material.FIG.18illustrates a cross-sectional view of some embodiments of the integrated circuit along X-direction, andFIG.19illustrates a cross-sectional view of some embodiments along X-direction after the replacement gate process. Firstly, the initial gate stack1702is removed to form an opening1802(seeFIG.18). As an example, a contact etch stop layer (CESL, not shown) is formed lining previously formed structures, and an interlayer dielectric (ILD) layer126is formed on the contact etch stop layer followed by a planarization process to form a planar top surface. The ILD layer may be deposited by CVD, PVD, sputtering, or some other deposition process. The planarization process may be a chemical-mechanical planarization (CMP). Then, the initial gate stack1702(seeFIG.17) is removed, thereby forming the opening1802that is defined by inner sidewalls of the sidewall spacer128. In some embodiments, a process for removing the initial gate stack1702comprises performing an etch (e.g., dry or wet etch) to selectively remove the initial gate stack1702. In further embodiments, before the etch, a masking layer (not shown) may be formed covering the ILD layer126and the sidewall spacer128, while leaving the initial gate stack1702exposed. Thereafter, the etch is performed with the masking layer in place, thereby selectively removing the initial gate stack1702. Subsequently, the masking layer may be etched or stripped away.

Then, gate dielectric materials and metal gate materials are filled in the opening1802to form a capacitor gate stack120and a transistor gate stack120′, which may respectively include an interfacial dielectric layer114, a high-k dielectric layer116, a work function metal layer122, and a bulk metal gate layer124, for example. In some embodiments, the interfacial dielectric layer114may be formed by a thermal process that converts an outermost portion of the dummy channel region110and the channel region110′ to the interfacial dielectric layer114. Since the dummy channel region110was doped by the series of ion implantation processes to form the doped region112as described inFIG.13, the dummy channel region110of the capacitor fin structures104becomes more amorous and may be consumed more compared to the channel region110′ of the transistor fin structures104′. As a result, the capacitor fin structures104may have a more tapered upper portion and a narrower width than the transistor fin structures104′, and the interfacial dielectric layer114may have a greater width wrapping around sidewall and top surfaces of the capacitor fin structures104than that of the transistor fin structures104′ (SeeFIG.19).

The work function metal layer122and the bulk metal gate layer124may comprise tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), or the like. The interfacial dielectric layer114may comprise oxide, and the high-k dielectric layer116may comprise high-k dielectric materials such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or some other dielectric material with a dielectric constant greater than about 3.9. In some embodiments, the capacitor gate stack120and the transistor gate stack120′ may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, electrochemical plating, electroless plating, or some other deposition process. The process of removing the initial gate stack1702and replacing with the high-k dielectric and metal materials as described above may be referred to as a replacement gate process or a gate-last high-k/metal gate (HKMG) process. It will be appreciated that, in some embodiments, the capacitor gate stack120and the transistor gate stack120′ may be formed by other processes. For example, the capacitor gate stack120and the transistor gate stack120′ may be formed by a gate-first HKMG process (e.g., the metal gate electrode is formed prior to source/drain formation), a fully silicided (FUSI) metal gate process (e.g., fully siliciding a polysilicon gate), or a doped polysilicon gate process (e.g., self-aligned polysilicon gate process). Depending on the process in which the capacitor gate stack120and the transistor gate stack120′ is formed, the gate electrode material may comprise, for example, doped polysilicon (e.g., n-type/p-type polysilicon), undoped polysilicon, a metal (e.g., W, Al, Ti, Mo, or the like), a metal-nitride (e.g., TiN, TaN, or the like), some other conductive material, or a combination of the foregoing.

FIG.20illustrates a flowchart2000of some embodiments of a method for forming an integrated circuit (IC) comprising a FinFET MOS capacitor. The FinFET MOS capacitor may be the FinFET MOS capacitor shown and described above associated withFIGS.1-19. While the flowchart2000ofFIG.20is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At act2002, a fin-structured substrate is prepared. A hard mask can be patterned and then used to from the fin structures extending upwardly from an upper surface of the substrate.FIG.9illustrates a cross-sectional view900of some embodiments corresponding to act2002.

At act2004, an isolation dielectric layer is formed surrounding the fin structures. The isolation dielectric layer can be formed by a deposition process followed by a planarization process to be co-planar with the hard mask. The isolation dielectric layer is then etched back to a position between top and bottom surfaces of the hard mask.FIG.10illustrates a cross-sectional view1000of some embodiments corresponding to act2004.

At act2006, a sacrificial layer is formed lining the top surfaces of the fin structures. As an example, the sacrificial layer can be formed by a thermal oxidation process such as an in-situ steam generation (ISSG) process. The sacrificial layer may be formed after removing the hard mask from the top surfaces of the fin structures. The hard mask removal process may comprise wet etching processes and/or dry etching processes.FIGS.11-12illustrate a series of cross-sectional views1100-1200of some embodiments corresponding to act2006.

At act2008, a doped region is formed in an upper region of a dummy channel region of a FinFET MOS capacitor. In some embodiments, the doped region is formed with multiple doped layers one vertically stacked next to another. The doped region may be formed by performing a series of angled ion implantation processes first to the capacitor fin structures followed by an annealing process. The annealing process can be performed by a rapid thermal annealing (RTA) method. As a result, the doped region may be formed with a doping concentration greater in an inner region than an outer region of the dummy channel region in lateral directions. A channel region of a FinFET transistor may be covered and protected by a protection layer from the implantation when performing the implantation processes. As a result, the dummy channel region may have a doping concentration greater than that of the channel region.FIGS.13-14illustrate a series of cross-sectional views1300-1400of some embodiments corresponding to act2008.

At act2010, the isolation dielectric layer is etched back to a lower position to expose an upper portion of the fin structures. The sacrificial layer is also removed during this process.FIG.15illustrates a cross-sectional view1500of some embodiments corresponding to act2010.

At act2012, an initial gate stack is formed overlying the fin structures, the initial gate stack comprising a gate dielectric layer and an initial gate electrode layer. The initial gate dielectric layer and the initial gate electrode layer may be formed by a deposition process followed by a patterning process.FIG.16illustrates a cross-sectional view1600of some embodiments corresponding to act2012.

At act2014, dummy source/drain regions of the FinFET MOS capacitor and source/drain regions of the FinFET transistor are formed at opposite sides of the fin structures. The source/drain regions may be formed by a series of ion implantation processes. In some embodiments, lightly-doped source/drain extensions (LDDs) may also be formed on opposite sides of the initial gate stack.FIG.17illustrates a cross-sectional view1700of some embodiments corresponding to act2014.

At act2016, a replacement gate process may be performed to remove the initial gate stack and replace with high-k dielectric material and metal gate material. In some embodiments, the replacement gate process is performed by forming an interlayer dielectric (ILD) layer over the substrate and the initial gate stack. The ILD structure may be then polished to have a top surface coplanar with that of the initial gate stack. Then the initial gate stack is removed leaving an opening in the ILD. The opening is then filled with the high-k dielectric material and metal gate material.FIGS.18-19illustrate a series of cross-sectional views1800-1900of some embodiments corresponding to act2016.

In some embodiments, the present application provides a FinFET MOS capacitor. The FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

In some embodiments, the present application provides an integrated circuit (IC). The IC comprises a FinFET MOS capacitor and a FinFET transistor integrated in a substrate. The FinFET MOS capacitor comprises a capacitor fin structure extending upwardly from an upper surface of the substrate and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric. The FinFET transistor comprises a transistor fin structure extending upwardly from the upper surface of the substrate and a transistor gate structure straddling on the transistor fin structure. The transistor gate structure is separated from the transistor fin structure by a transistor gate dielectric. The capacitor fin structure has a width smaller than that of the transistor fin structure.

In some embodiments, the present application provides a method for forming a FinFET MOS capacitor. In the method, a plurality of fin structures is formed extending upwardly from an upper surface of a substrate. The plurality of fin structures has a capacitor fin structure and a transistor fin structure. Then, a shallow trench isolation (STI) structure is formed between the plurality of fin structures and a sacrificial dielectric layer on top of the plurality of fin structures and the STI structure. Then, a doping process is performed to a dummy channel region of the capacitor fin structure with the transistor fin structure protected from the doping process. Then, the STI structure is recessed to expose an upper portion of the plurality of fin structures. Then a gate dielectric layer is formed covering the top and exposed sidewall surfaces of the plurality of fin structures. Then, a gate electrode layer is formed on the gate dielectric layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.