Patent ID: 12210960

DETAILED DESCRIPTION

Hereinafter, an exemplary embodiment of the present disclosure will be described with reference to the accompanying drawings. In the following description, the same elements will be designated by the same reference numerals although they are shown in different drawings. Further, in the following description of the present disclosure, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present disclosure rather unclear.

Also, in describing the components of the present disclosure, there may be terms used like the first, second, A, B, (a), and (b). These are solely for the purpose of differentiating one component from the other but not to imply or suggest the substances, order or sequence of the components. If a component were described as ‘connected’, ‘coupled’, or ‘linked’ to another component, it may mean the components are not only directly ‘connected’, ‘coupled’, or ‘linked’ but also are indirectly ‘connected’, ‘coupled’, or ‘linked’ via a third component.

FIG.1is a block diagram illustrating a neuromorphic circuit according to an embodiment of the present invention. The neuromorphic circuit100may include a first neuron array110, a synapse array130, a second neuron array150, and a control logic170.

The first neuron array110generates a spike signal and transmits it to the synapse array130. The first neuron array110may include neuron circuits112and114that generate input spike signals. The neuron circuits112and114may perform a function of outputting signals to other neurons, similar to the axon of a biological neural network. For example, each of the neuron circuits112and114may generate an input spike signal based on data or information input from the outside. The input spike signal may be a pulse signal that toggles for a short period of time. In particular, the neuron circuits112and114of the present invention may be configured in a stable and simple structure using a flash memory type transistor (FMTR). In particular, the flash memory type transistor FMTR constituting the spike regulator included in the neuron circuits112and114may arbitrarily adjust a threshold voltage through charge injection. Accordingly, the output characteristic of the spike signal provided by the spike regulator may be adjusted, and stability may be improved.

The synapse array130may connect the first neuron array110and the second neuron array150. The synapse array130may include synapse circuits131that determine whether neuron circuits112and114of the first neuron array110and neurons of the second neuron array150are connected and the strength of the connection. The synapse circuits131may process spike signals input from the first neuron array110and may output a processing result to the second neuron array150. Devices for configuring the synapse circuits131may be devices such as flash memory, RRAM, PRAM, FRAM, and MRAM. However, the devices constituting the synapse circuits131may be variously changed, and the present disclosure is not limited thereto.

The neuron circuits151,153, and155of the second neuron array150may receive operation signals to which weights are applied to input spike signals from the synapse array130, respectively. The neuron circuits151,153, and155may perform a function of receiving signals output from other neurons, similar to the dendrites of a biological neural network. Referring toFIG.1, each of the neuron circuits152,153, and155included in the second neuron array150may be connected to synapse circuits131and may receive operation signals output from the synapse circuits131.

Operation signals provided from the synapse circuits131may be accumulated in each of the neuron circuits151,153, and155. However, the number and arrangement of the synapse circuits131connected to each of the neuron circuits151,153, and155are not limited to those shown inFIG.1. Each of neuron circuits151,153, and155may compare the sum signal in which the operation signals of the synapse circuits131are accumulated with a threshold signal (ie, a reference signal), and generate an output spike signal when the sum signal is greater than the threshold signal (namely, neurons fire). The output spike signals of the second neuron array150may be provided back to the first neuron array110, output to the outside of the neuromorphic circuit100, or output to other components of the neuromorphic circuit100.

Neuron circuits151,153, and155may also be configured in a stable and simple structure using a flash memory type transistor FMTR. That is, the flash memory type transistor FMTR constituting the spike regulator included in the neuron circuits151,153, and155may arbitrarily adjust a threshold voltage through charge injection. Therefore, it is possible to improve the flexibility and stability of the output characteristics of the spike signal output from the neuron circuits151,153, and155.

The control logic170may control an operation sequence of the neuromorphic circuit100. The control logic170may control transmission, processing, or update of spike signals of the first and second neuron arrays110and150and the synapse array130. In particular, the control logic170of the present invention may include a program circuit175that performs a program of the flash memory type transistor FMTR included in the first and second neuron arrays110and150.

The program circuit175may first program the flash memory type transistors FMTR once in a step for setting the characteristics of the neuromorphic circuit100. The threshold voltage of the flash memory type transistor FMTR is set by the program operation of the program circuit175, and the level of the spike signal output from the first and second neuron arrays110and150may be selected. Alternatively, the program circuit175may be activated when necessary according to a user's selection to program the flash memory type transistor FMTR included in the first and second neuron arrays110and150.

In the above, the basic configuration of the neuromorphic circuit100of the present invention has been briefly described. In configuring the neuromorphic circuit100by hardware, the number of transistors required by the first and second neuron arrays110and150generating spike signals is relatively large. The first and second neuron arrays110and150of the present invention may include a simple and low power spike regulator using a flash memory type transistor FMTR.

FIG.2is a block diagram illustrating an exemplary configuration of a neuron circuit illustrated inFIG.1. Referring toFIG.2, the neuron circuit112may include a control signal generator111, a spike regulator113, and a mode selection circuit115.

The neuron circuit112may operate in a normal mode for generating a spike signal and a program mode for programming a flash memory type transistor FMTR included in the spike regulator113. The normal mode is an operation mode in which the spike regulator113outputs the spike signal Vout in response to the control signal Vctrl and the input signal Vin provided from the control signal generator111. The program mode is an operation in which a mode selection circuit115is activated under the control of the program circuit175ofFIG.1described above, and charges are injected into a floating gate of a flash memory type transistor FMTR of a spike regulator113. The threshold voltage of the flash memory type transistor FMTR may be set through a program operation in which electric charges are injected into a floating gate or a charge trap layer of the flash memory type transistor FMTR.

The control signal generator111generates a control signal Vctrl for forming a waveform or a magnitude of a pulse width of the spike signal generated by the neuron circuit112in the normal mode. The control signal generator111may operate to fire a pre-spike signal corresponding to a membrane potential based on an input spike train provided to the first neuron array110. At this time, the control signal generator111will output a control signal Vctrl pulse corresponding to the input of the spike regulator113.

The spike regulator113outputs a spike signal Vout in the form of a pulse corresponding to the control signal Vctrl at a stable level. The spike regulator113may output a spike signal Vout of a constant level regardless of a level fluctuation or noise of the input voltage Vin corresponding to the power supply voltage. In order to perform this operation, the spike regulator113of the present invention may include a flash memory type transistor FMTR.

For example, the spike regulator113may output a spike signal Vout corresponding to the control signal Vctrl using only one flash memory type transistor FMTR and one switch element. A significant amount of ripple or noise included in the input voltage Vin may be removed by the flash memory type transistor FMTR programmed to have a threshold voltage of a negative voltage. A specific example of the spike regulator113will be described in more detail inFIGS.3to11to be described later.

The mode selection circuit115may provide program bias voltages Vd, Vpgm, and Vs for programming the flash memory type transistor FMTR included in the spike regulator113in response to the program enable signal PGM_En. In the normal mode, the program circuit175(refer toFIG.1) will disable the program enable signal PGM_En. Accordingly, in the normal mode, the mode selection circuit115will cut off the program bias voltages Vd, Vpgm, and Vs. On the other hand, in the program mode, the program circuit175will enable the program enable signal PGM_En. Then, the mode selection circuit115may provide program bias voltages Vd, Vpgm, and Vs to the flash memory type transistor FMTR of the spike regulator113.

The program bias voltages Vd, Vpgm, and Vs include voltages for injecting electric charges into the floating gate or charge trap layer of the flash memory type transistor FMTR. The drain voltage Vd is provided to the drain when programming the flash memory type transistor FMTR. The program voltage Vpgm is provided to the gate during programming of the flash memory type transistor FMTR. The source voltage Vs is provided to the source when programming the flash memory type transistor FMTR.

For example, during the program operation, the drain voltage Vd may be provided with a level (about 5V) for increasing the efficiency of hot electron injection, and the source voltage Vs may be provided with the ground level GND. The program voltage Vpgm may be provided as an incremental step pulse that gradually increases during a program operation. It is possible to control the level of the threshold voltage programmed in the flash memory type transistor FMTR by controlling the number of pulses of the program voltage Vpgm, the pulse width, the increase width of the pulse, the duty cycle, etc.

In the above, a simple configuration of the neuron circuit112of the present invention has been described. The neuron circuit112has been described as being included in the first neuron array110corresponding to the pre-synapse neuron ofFIG.1. However, it will be well understood the configuration of the neuron circuit112may be equally applied to the neuron circuit114and the neuron circuits151,153, and155constituting the second neuron array150corresponding to the post neuron ofFIG.1.

FIG.3is a circuit diagram showing an embodiment of the spike regulator ofFIG.2in a program mode. Referring toFIG.3, the spike regulator113aincludes a PMOS transistor PM that functions as a switch and a flash memory type transistor FMTR.

In the normal mode, by the PMOS transistor PM and the flash memory type transistor FMTR, the spike regulator113amay generate a spike signal Vout having a constant target amplitude regardless of ripple or noise included in the input voltage Vin.

In the program mode, the flash memory type transistor FMTR of the spike regulator113ais provided with program bias voltages Vd, Vpgm, and Vs provided through the mode selection circuit115(refer toFIG.2). In the program mode, the control signal Vctrl is provided at a high level, so that the PMOS transistor PM may maintain a turn-off state.

In the program mode, the program voltage Vpgm is provided to the gate of the flash memory type transistor FMTR, the drain voltage Vd is provided to the drain, and the source voltage Vs is provided to the source. The source voltage Vs and the bulk region are grounded. And in the state where the drain voltage Vd at the level for hot electron injection is provided, negative charges are injected into the floating gate or charge trap layer of the flash memory transistor FMTR adjacent to the drain by the program voltage Vpgm provided in the form of a pulse.

The injection amount of negative charges may be controlled through the number of pulses, the pulse width, the width of the step pulse, the duty cycle, etc of the program voltage Vpgm. The threshold voltage level of the flash memory type transistor FMTR is set according to the injection amount of negative charge. The flash memory type transistor FMTR of the present invention may have a threshold voltage of a negative level through execution of the program mode.

When the program mode is completed, the mode selection circuit115is deactivated, and the program bias voltages Vd, Vpgm, Vs will be cut off. Then, the spike regulator113amay operate in a normal mode for outputting a spike signal.

FIG.4is a cross-sectional view showing an exemplary structure of a flash memory type transistor FMTR according to the present invention. Referring toFIG.4, a structure of a charge trap flash transistor CTFTR is disclosed as an example of a flash memory type transistor FMTR. The charge trap type flash transistor CTFTR may include the substrate210, the insulating layer220, the drain electrode230a, the source electrode230b, the channel layer240, the charge trap layers250and260, and the gate electrode270.

A channel layer240may be formed between the drain electrode230aand source electrode230bon the substrate210formed of silicon (Si) and the insulating layer220to configure the charge trap type flash transistor CTFTR. The channel layer240may be formed of a single layer or a multi-layer of molybdenum disulfide MoS2. The drain electrode230aand source electrode230bmay be formed of gold (Au). The channel layer240of molybdenum disulfide MoS2 forming a single-layer or multi-layer may be provided between the drain electrode230aand source electrode230b. Two layers250of aluminum oxide (AL2O3) may be formed between the gate electrode270and the channel layer240. A hafnium oxide (HfO2) layer260is stacked between the two layers250of aluminum oxide (AL2O3). So a three-dimensional charge trapping layer250and260may be formed.

The charge trap type flash transistor CTFTR having the above-described structure may inject charges (electrons or holes) into a hafnium oxide (HfO2) layer260through a program. For example, under conditions of a source voltage (Vs) of a ground level and a drain voltage (Vd) of 5V, when a high voltage program pulse is provided to the gate electrode270, electrons may be trapped in the hafnium oxide (HfO2) layer260. In this case, the threshold voltage Vth_FMTR of the charge trap type flash transistor CTFTR increases.

On the other hand, when a high voltage is applied to the bulk region, electrons trapped in the hafnium oxide (HfO2) layer260are released and holes increase. In this case, the threshold voltage Vth_FMTR of the charge trap type flash transistor CTFTR is lowered. Through such a program or erase operation, the charge trap type flash transistor CTFTR may have a threshold voltage Vth_FMTR characteristic in a negative region. Here, it will be well understood that the 2D material provided as the channel layer240is not limited to molybdenum disulfide (MoS2).

In the above, the charge trap type flash transistor CTFTR has been briefly described as an example of the flash memory type transistor FMTR of the present invention. However, the charge trap type flash transistor CTFTR is not limited to the above-described materials or structures, and various types of charge trap type transistors that may be set to a negative threshold voltage through a program may be used. In addition, it will be well understood that the flash memory type transistor FMTR may be implemented not only as a charge trap type flash transistor CTFTR but also as a floating gate type flash transistor.

FIG.5is a circuit diagram illustrating an example of a normal mode operation of the spike regulator ofFIG.2. Referring toFIG.5, the spike regulator113bincludes a PMOS transistor PM that functions as a switch and a flash memory type transistor FMTR. The spike regulator113bmay generate a spike signal Vout having a constant target amplitude regardless of ripple or noise included in the input voltage Vin by the PMOS transistor PM and the flash memory type transistor FMTR.

The PMOS transistor PM performing the switch function switches the input voltage Vin in response to the control signal Vctrl. That is, the PMOS transistor PM may convert the control signal Vctrl into the level of the input voltage Vin provided as the power supply voltage and transmit it to the source terminal. However, a signal having an inverted waveform of the control signal Vctrl will be transmitted to the source terminal (corresponding to node N1) of the PMOS transistor PM.

The flash memory type transistor FMTR may have a threshold voltage Vth_FMTR in a negative region through application of a program mode. The flash memory type transistor FMTR filters the switched voltage provided through the drain terminal (corresponding to the node N1) and outputs a spike signal Vout to the source terminal. In this case, the gate terminal of the flash memory type transistor FMTR may be provided as a ground voltage GND.

If the input voltage Vin is unstable, it is assumed that noise or ripple exists. Then, the voltage switched by the PMOS transistor PM will be provided to the drain terminal N1of the flash memory type transistor FMTR. For example, the voltage at the drain terminal N1of the flash memory type transistor FMTR may include a ripple voltage. This ripple voltage provides interference to the gate terminal of the flash memory type transistor FMTR by a parasitic capacitance Cgd between the gate terminal and the drain terminal of the flash memory type transistor FMTR. An interference component due to a ripple voltage, which is an AC component, will be transmitted to the gate terminal of the flash memory type transistor FMTR by the parasitic capacitance Cgd.

Accordingly, a ripple voltage due to interference may be included in the gate terminal of the flash memory type transistor FMTR. However, the gate terminal of the flash memory type transistor FMTR is connected to the ground voltage GND. Accordingly, a significant portion of the ripple voltage transmitted to the gate terminal due to interference falls to the ground side providing the ground voltage GND, and the voltage at the gate terminal will maintain the ground level. The level of the spike signal Vout formed at the source terminal N2of the flash memory type transistor FMTR will be the difference between the gate voltage GND and the threshold voltage (GND−Vth_FMTR and Vth_FMTR are negative numbers). That is, the level of the spike signal Vout will have the level of the threshold voltage Vth_FMTR of the flash memory type transistor FMTR.

According to the above-described feature, when a switched signal is provided to the drain electrode N1of the flash memory type transistor FMTR, the spike signal Vout corresponding to the voltage at the source terminal of the flash memory type transistor FMTR may be output as a stable level.

FIG.6is a timing diagram illustrating the operation of the spike regulator ofFIG.5. Referring toFIG.6, a spike signal Vout output from the spike regulator113aunder an input voltage Vin condition in which ripple or noise is not included is shown.

The input voltage Vin is provided at the power supply voltage Vdd level without ripple or noise. Then, the PMOS transistor PM inverts the signal having the input voltage Vin amplitude by the gate voltage provided as the control signal Vctrl and outputs it to the source terminal N1of the PMOS transistor PM. The source terminal N1of the PMOS transistor PM corresponds to the drain terminal N1of the flash memory type transistor FMTR. Accordingly, the voltage Vn1of the drain terminal N1of the flash memory type transistor FMTR is provided in a form in which the input voltage Vin is inverted.

Since noise or ripple does not exist in the input voltage Vin, interference between the gate terminal and the drain terminal of the flash memory type transistor FMTR will be insignificant. Accordingly, the voltage at the gate terminal of the flash memory type transistor FMTR will maintain a stable ground level GND. Since the voltage (Vg_FMTR) at the gate terminal of the flash memory type transistor FMTR maintains the ground level (GND), the spike signal Vout formed at the source terminal N2of the flash memory type transistor FMTR may be output as a pulse signal having an amplitude of the absolute value Vth_FMTR of the threshold voltage of the flash memory type transistor FMTR.

FIG.7is a timing diagram showing another characteristic of the spike regulator ofFIG.5. Referring toFIG.7, a spike signal Vout output from the spike regulator113bunder an input voltage Vin condition including a ripple voltage Vripp is shown.

When the input voltage Vin is unstable or contains ripple or noise under certain operating conditions, the ripple voltage Vripp is added to the original power supply voltage Vdd. Then, the PMOS transistor PM inverts the signal having the input voltage Vin amplitude by the gate voltage provided as the control signal Vctrl and outputs it to the source terminal N1of the PMOS transistor PM. The source terminal N1corresponds to the drain terminal N1of the flash memory type transistor FMTR. Accordingly, the voltage Vn1of the drain terminal N1of the flash memory type transistor FMTR is provided in a form in which the input voltage Vin is inverted. In addition, a ripple component will also be included in the voltage Vn1of the drain terminal N1of the flash memory type transistor FMTR.

The voltage at the drain terminal N1of the flash memory type transistor FMTR may include a ripple voltage. This ripple voltage acts as an interference to the gate terminal of the flash memory type transistor FMTR by a parasitic capacitance Cgd between the gate terminal and the drain terminal of the flash memory type transistor FMTR. An interference component due to a ripple voltage, which is an AC component, by the parasitic capacitance Cgd will be transmitted to the gate terminal of the flash memory type transistor FMTR.

Accordingly, a ripple voltage may be transmitted to the gate terminal of the flash memory type transistor FMTR. However, the gate terminal of the flash memory type transistor FMTR is connected to the ground voltage GND. Accordingly, a significant portion of the ripple voltage transmitted to the gate terminal of the flash memory type transistor FMTR due to interference falls to the ground side, and the voltage at the gate terminal will maintain the ground level. By grounding the gate terminal of the flash memory type transistor FMTR, the level of the spike signal Vout formed at the source terminal N2of the flash memory type transistor FMTR will be the difference (0−Vth_FMTR, Vth_FMTR is negative) between the ground voltage (GND, 0V) and the threshold voltage. Accordingly, even if ripple or noise exists in the input voltage Vin, the spike signal Vout may be generated in the form of a stable pulse having an amplitude of the threshold voltage Vth_FMTR of the flash memory type transistor FMTR.

FIG.8is a circuit diagram showing another embodiment of the spike regulator ofFIG.2. Referring toFIG.8, the spike regulator113cincludes a PMOS transistor PM that functions as a switch and a flash memory type transistor FMTR that receives an ungrounded gate voltage. The spike regulator113cmay generate a spike signal Vout having a constant target amplitude regardless of ripple or noise included in the input voltage Vin by the PMOS transistor PM and the flash memory type transistor FMTR.

The PMOS transistor PM performing the switch function switches the input voltage Vin in response to the control signal Vctrl. That is, the PMOS transistor PM may convert the control signal Vctrl into the level of the input voltage Vin provided as the power supply voltage and transmit it to the source terminal. However, a signal having an inverted waveform of the control signal Vctrl will be transmitted to the source terminal (corresponding to node N1) of the PMOS transistor PM.

The flash memory type transistor FMTR filters the switched voltage provided through the drain terminal (corresponding to the node N1) and outputs a spike signal Vout to the source terminal. In this case, a regulator voltage Vreg of a specific level, not a ground voltage GND, may be provided to the gate terminal of the flash memory type transistor FMTR.

If the input voltage Vin is unstable, it is assumed that noise or ripple is included. Then, the voltage switched by the PMOS transistor PM will be provided to the drain terminal N1of the flash memory type transistor FMTR. For example, the voltage at the drain terminal N1of the flash memory type transistor FMTR may include a ripple voltage. This ripple voltage provides interference to the gate voltage Vreg of the flash memory type transistor FMTR due to a parasitic capacitance Cgd between the gate terminal and the drain terminal of the flash memory type transistor FMTR. The ripple voltage will be transmitted to the gate terminal of the flash memory type transistor FMTR due to interference such as a coupling effect.

Accordingly, the ripple voltage component may be included in the gate voltage Vreg of the flash memory type transistor FMTR. However, the magnitude of the ripple voltage transmitted to the gate voltage Vreg of the flash memory type transistor FMTR will be significantly reduced and transmitted. The level of the spike signal Vout formed at the source terminal N2of the flash memory type transistor FMTR will be the difference (Vreg−Vth_FMTR and Vth_FMTR are negative numbers) between the gate voltage Vreg and the threshold voltage.

According to the above-described feature, when a switched signal is provided to the drain electrode N1of the flash memory type transistor FMTR, the spike signal Vout corresponding to the voltage at the source terminal of the flash memory type transistor FMTR may be output as a stable level. Of course, in this case, the level of the input voltage Vin should be higher than ‘Vreg−Vth_FMTR’.

FIG.9is a timing diagram showing the operation of the spike regulator ofFIG.8. Referring toFIG.9, under an input voltage Vin condition in which ripple or noise is not included, a spike signal Vout output from the spike regulator113cis shown.

The PMOS transistor PM inverts a signal having an amplitude of the input voltage Vin by the gate voltage provided as the control signal Vctrl and outputs it to the source terminal N1of the PMOS transistor PM. The source terminal N1of the PMOS transistor PM corresponds to the drain terminal N1of the flash memory type transistor FMTR. Accordingly, the voltage Vn1of the drain terminal N1of the flash memory type transistor FMTR is provided in a form in which the input voltage Vin is inverted.

The input voltage Vin is shown to be provided at the power supply voltage Vdd level without ripple or noise. However, even if the input voltage Vin contains ripple or noise, a spike signal Vout of a stable level may be output due to the action of the flash memory type transistor FMTR. That is, the amplitude of the output spike signal Vout will correspond to ‘Vreg−Vth_FMTR’. Of course, in this case, the level of the input voltage Vin should be higher than ‘Vreg−Vth_FMTR’.

FIG.10is a circuit diagram showing another embodiment of the spike regulator ofFIG.2. Referring toFIG.10, the spike regulator113dincludes a plurality of floating gate transistors FMTR1to FMTRn connected in series with a PMOS transistor PM performing a function of a switch. By means of a PMOS transistor (PM) and a plurality of floating gate transistors (FMTR1to FMTRn), the spike regulator113dmay generate a spike signal Vout having a constant amplitude regardless of ripple or noise included in the input voltage Vin.

The PMOS transistor PM performing the switch function switches the input voltage Vin in response to the control signal Vctrl. That is, the PMOS transistor PM may convert the control signal Vctrl into the level of the input voltage Vin provided as the power supply voltage and transmit it to the source terminal. However, a signal having an inverted waveform of the control signal Vctrl will be transmitted to the source terminal (corresponding to node N1) of the PMOS transistor PM.

The plurality of floating gate transistors FMTR1to FMTRn may filter the switched voltage provided through the node N1in a chain or cascade form to output a spike signal Vout. At this time, the gate terminals of the plurality of floating gate transistors FMTR1to FMTRn are grounded.

A plurality of floating gate transistors FMTR1to FMTRn connected in a cascade form may be used for noise filtering or generating a spike signal Vout of an appropriate target level. Here, the operation characteristics of each of the plurality of floating gate transistors FMTR1to FMTRn are the same as the operation of the flash memory type transistor FMTR described inFIG.5, and thus will be omitted.

According to the above-described features, the spike regulator113daccording to the present invention may generate a spike signal Vout having a stable level even against ripple or noise.

FIG.11is a circuit diagram illustrating another embodiment of the spike regulator ofFIG.2. Referring toFIG.11, the spike regulator113eincludes a plurality of floating gate transistors FMTR1to FMTRn connected in series with a PMOS transistor PM performing a function of a switch. In this case, regulator voltages Vreg_1to Vreg_n of a specific level other than a ground level may be provided to gate terminals of the plurality of floating gate transistors FMTR1to FMTRn.

The PMOS transistor PM performing the switch function switches the input voltage Vin in response to the control signal Vctrl. That is, the PMOS transistor PM may convert the control signal Vctrl into the level of the input voltage Vin provided as the power supply voltage and transmit it to the source terminal. However, a signal having an inverted waveform of the control signal Vctrl will be transmitted to the source terminal (corresponding to node N1) of the PMOS transistor PM.

The plurality of floating gate transistors FMTR1to FMTRn may filter the switched voltage provided through the node N1in a chain or cascade form to output a spike signal Vout. In this case, each of the gate terminals of the plurality of floating gate transistors FMTR1to FMTRn may be provided with regulator voltages Vreg_1to Vreg_n other than the ground level. Here, the regulator voltages Vreg_1to Vreg_n may be provided at the same level or different levels.

A plurality of floating gate transistors FMTR1to FMTRn connected in a cascade form may be used for noise filtering or generating a spike signal Vout of an appropriate target level. Here, the operation characteristics of each of the plurality of floating gate transistors FMTR1to FMTRn are the same as those of the flash memory type transistor FMTR described inFIG.8, and thus will be omitted. According to the above-described features, the spike regulator113eaccording to the present invention may generate a spike signal Vout having a stable level even against ripple or noise.

The above-described contents are specific examples for carrying out the present invention. Although exemplary embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure. Therefore, exemplary embodiments of the present disclosure have not been described for limiting purposes. Accordingly, the scope of the disclosure is not to be limited by the above embodiments but by the claims and the equivalents thereof.

As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the inventive concept refers to “one or more embodiments of the present disclosure”. Also, the term “exemplary” is intended to refer to an example or illustration. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it may be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.