Patent ID: 12243622

DETAILED DESCRIPTION

Embodiments of the present disclosure will now be described with reference to the drawing figures, in which like reference numerals refer to like parts throughout.

Embodiments of the present disclosure provide dynamic power management for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc.

In one embodiment, a method for managing power in a memory includes receiving an access request for a memory, the access request including an address, the memory including a plurality of wordline sections, each wordline section including a number of wordlines; applying power to control circuitry; decoding the address, including determining, based on the address, an associated wordline, and determining, based on the associated wordline, an associated wordline section; and applying power to wordline control circuitry coupled to the associated wordline section, each wordline section of the plurality of wordline sections being coupled to a different wordline control circuitry.

FIG.1depicts a block diagram for SoC100, in accordance with an embodiment of the present disclosure.

In this embodiment, SoC100includes interconnect110coupled to, inter alia, processor(s)120, accelerator(s) or special processor(s)130, and memory controller(s)140coupled to system memory142and last-level (or system level) cache144. Other components may also be coupled to interconnect110, such as, for example, network controllers and I/O interfaces, etc. In other embodiments, SoC100is a general purpose computer system, and interconnect110is a bus that transfers data between processor120, special processor130, memory controller140, memory142and last-level cache144, as well as other components.

Interconnect110is a communication system that transfers data between processor120, special processor130, memory controller140, memory142and last-level cache144, as well as other components. Interconnect110may also include on-chip memory150. Certain components of SoC100may be classified as a particular type of interconnect protocol node.

Generally, interconnect110may include, inter alia, a shared or hierarchical bus, a crossbar switch, a packet-based network-on-chip (NoC), etc. In one embodiment, interconnect110has a crossbar topology that provides an ordered network with low latency, and may be particularly suitable for a small-sized interconnect with a small number of protocol nodes, switches and wire counts. In another embodiment, interconnect110has a ring topology that balances wiring efficiency with latency, which increases linearly with the number of protocol nodes, and may be particularly suitable for a medium-sized interconnect. In a further embodiment, interconnect110has a mesh topology that has more wires to provide greater bandwidth, is modular and easily scalable by adding more rows and columns of switches or routers, and may be particularly suitable for a large-sized interconnect.

Generally, interconnect110may be a coherent or incoherent interconnect. In many embodiments, interconnect110is a coherent mesh network that includes multiple switches or router logic modules (routers) arranged in a two-dimensional rectangular mesh topology, such as, for example, the Arm CoreLink Coherent Mesh Network. In this example, the switches or routers are crosspoints (i.e., XPs). Each XP may connect up to four neighboring XPs using mesh ports, and may connect to one or two components (devices) using device ports. Additionally, each XP may support four coherent hub interface (CHI) channels to transport data from a source device to a destination or target device, as described, for example, in the Arm Advanced Microcontroller Bus Architecture (AMBA) CHI specification.

In these embodiments, interconnect110may have an architecture that includes three layers, i.e., an upper protocol layer, a middle network layer, and a lower link layer. The protocol layer generates and processes requests and responses at the protocol nodes, defines the permitted cache state transitions at the protocol nodes that include caches, defines the transaction flows for each request type, and manages the protocol level flow control. The network layer packetizes the protocol message, determines, and adds to the packet, the source and target node IDs required to route the packet over interconnect110to the required destination. The link layer provides flow control between components, and manages link channels to provide deadlock free switching across interconnect110.

Processor120is a general-purpose, central processing unit (CPU) that executes instructions to perform various functions for SoC100, such as, for example, control, computation, input/output, etc. More particularly, processor120may include a single processor core or multiple processor cores (or processing circuitries), which may be arranged in a processor cluster, such as, for example the Arm Cortex A, R and M families of processors. Each processor core may include a level 1 or L1 cache (L1$), and each processor120may include a level 2 or L2 cache (L2$) coupled to each processor core. Generally, processor120may execute computer programs or modules, such as an operating system, application software, other software modules, etc., stored within a memory, such as, for example, memory142, etc.

Accelerator or special processor130is a specialized processor that is optimized to perform a specific function, such as process graphics, images and/or multimedia data, process digital signal data, process artificial neural network data, etc. For example, accelerator or special processor130may be a graphics processing unit (GPU), a digital signal processor (DSP), an image signal processor (ISP), a neural processing unit (NPU), etc. More particularly, accelerator or special processor130may include a single processor core or multiple processor cores (or processing circuitries), such as, for example the Arm Mali family of GPUs, display processors and video processors, the Arm Machine Learning processor, etc. Each processor core may include a level 1 or L1 cache (L1$), and each accelerator or special processor130may include a level 2 or L2 cache (L2$) coupled to each processor core.

Memory controller140may include a microprocessor, microcontroller, application specific integrated circuit (ASIC), field programmable gate array (FPGA), custom circuitry, programmable registers, etc., and are configured to provide access to memory142through interconnect110. Memory142may include a variety of non-transitory computer-readable medium that may be accessed by the other components of SoC100, such as processor120, accelerator or special processor130, etc., and may be located on-chip or off-chip. For example, memory142may store data and instructions for execution by processor120, accelerator or special processor130, etc.

Generally, memory controller140and memory142provide storage for retrieving, presenting, modifying, and storing data. For example, memory142stores software modules that provide functionality when executed by processor120, accelerator or special processor130, etc. The software modules include an operating system that provides operating system functionality for SoC100. Software modules provide various functionality, such as image classification, etc. Data may include data associated with the operating system, the software modules, etc.

In various embodiments, memory142may include volatile and nonvolatile medium, non-removable medium and/or removable medium. For example, memory may include any combination of random access memory (RAM), dynamic RAM (DRAM), double data rate (DDR) DRAM or synchronous DRAM (SDRAM), static RAM (SRAM), read only memory (ROM), HMC (Hybrid Memory Cube), HBM (High Bandwidth Memory), flash memory, cache memory, and/or any other type of non-transitory computer-readable medium. In certain embodiments, memory controller140is a dynamic memory controller that provides data transfers to and from high-density DDR3, DDR4 or DDR5 DRAM memory, such as, for example, the Arm CoreLink Dynamic Memory Controller (DMC) family, each of which includes a fast, single-port CHI channel interface for connecting to interconnect110.

Last-level cache144includes high-speed SRAM, etc., and is typically known as a last-level, level 3 or L3 cache (L3$) that is provided between processor120, special processor130, etc., and memory142.

On-chip memory150also includes high-speed SRAM, etc., and acts as a shared memory between processors120, special processors130and peripherals to lessen memory bottleneck issues between data sources and processors.

As suggested above, the caches form a hierarchy, so when a processor core requires access to a data item, such as a processing instruction and/or data to be handled by the processing instruction, the processor core will first attempt to obtain or access that data item in the respective L1 cache. In the case of a cache miss, a search will be performed through the next closest cache levels, with an access to memory142performed only if the attempted cache accesses all miss. When the required data item is obtained from memory142, a copy may be saved in one or more caches.

In general terms, the L1 cache is normally implemented proximate to the respective processor core to provide rapid, low latency and potentially energy efficient access to data stored by that L1 cache. The L2 cache is implemented to be further away from the respective processor core, and may be larger than the L1 cache. The L3 cache is implemented to be further still from the respective processor core, but is closest, in the hierarchy, to memory142and is much larger than the L2 cache. In the embodiment depicted inFIG.1, processor120and special processor130have multiple processor cores, and each processor core has a respective L1 cache. In other embodiments, one or more L1 caches (L1$s) may be shared between processing cores. Processor120and special processor130also have an L2 cache (L2$) that is shared between the processor cores.

Last-level cache144provides the last level of cache (L3$) between processor120and special processor130and memory142. Generally, accessing data from a cache not only reduces latency but also reduces access power consumption when compared to accessing the same data from memory142.

Rather than a last level cache, on-chip memory150provides a scratch pad memory for any processor or peripheral that connects to SoC100. The address space for on-chip memory150lies is a region of the address space of SoC100that is separate from the address space of memory142and memory-mapped1/O, such as peripherals. In certain embodiments, on-chip memory150may be a system cache.

Generally, accessing data from a cache not only reduces latency but also reduces access power consumption when compared to accessing the same data from memory142.

Additionally, the caches may operate under an inclusive or exclusive cache policy. An inclusive cache policy ensures that data stored in a particular cache is also stored in any lower level caches. For example, a value in an L1 cache would also be present in the respective L2 cache and final L3 cache. On the other hand, an exclusive cache policy ensures that data are only stored in one level of the cache. For example, a value in an L1 cache would not be present in the respective L2 cache and final L3 cache.

SoC100may also include I/O interface(s) (not depicted), coupled to interconnect110, that are configured to transmit and/or receive data from I/O devices. The I/O interfaces enable connectivity between processor120, special processor130, etc. and the I/O devices by encoding data to be sent to the I/O devices, and decoding data received from the I/O devices. Generally, data may be sent over wired and/or wireless connections. For example, the I/O interfaces may include one or more wired communications interfaces, such as PCle, USB, etc., and/or one or more wireless communications interfaces, coupled to one or more antennas, such as WiFi, Bluetooth, cellular, etc.

Generally, the I/O devices provide input to SoC100and/or output from SoC100. As discussed above, the I/O devices are operably connected to the I/O controller using a wired and/or wireless connection. The I/O devices may include a local processor coupled to a communication interface that is configured to communicate with SoC100using the wired and/or wireless connection. For example, the I/O devices may include a keyboard, mouse, touch pad, joystick, etc.

SoC100may also include network interface(s) configured to transmit data to and from one or more networks using one or more wired and/or wireless connections. The networks may include one or more local area networks, wide area networks, the Internet, etc., which may execute various network protocols, such as, for example, wired and/or wireless Ethernet, Bluetooth, etc. The networks may also include various combinations of wired and/or wireless physical layers, such as, for example, copper wire or coaxial cable networks, fiber optic networks, Bluetooth wireless networks, WiFi wireless networks, CDMA, FDMA and TDMA cellular wireless networks, etc.

FIGS.2A and2Bdepict block diagrams of on-chip memory200, in accordance with embodiments of the present disclosure. Memory200will be described with respect to system cache memory; other embodiments are also supported, such as, hierarchical cache memory, system memory, etc. These embodiments are applicable not only to physical memory but also to compiled instances, etc.

With respect toFIG.2A, memory200includes, inter alia, an array210including backbone220, memory modules (MMs)230, as well as other components not depicted for clarity. Generally, array210has a width in a lateral direction, and a height in a longitudinal direction. Backbone220is a data, address and control signal bus that includes a primary portion and a number of secondary portions that generally divide array210into regions.

In many embodiments, the primary portion of backbone220is disposed in the lateral center of array210and extends in the longitudinal direction from the lower edge to the upper edge of array210(i.e., approximately the height of array210), a first secondary portion of backbone220is disposed in the longitudinal center of array210and extends in a first lateral direction from the primary portion of backbone220to a left edge of array210(i.e., approximately 50% of the width of array210), and a second secondary portion of backbone220is disposed in the longitudinal center of array210and extends in a second lateral direction from the primary portion of backbone220to a right edge of array210(i.e., approximately 50% of the width of array210). The primary and secondary portions of backbone220divide array210into four regions, which, for convenience, are referred to as the top left (TL) region, the top right (TR) region, the bottom left (BL) region and the bottom right (BR) region.

In this embodiment, array210includes a total number of memory modules230, arranged in rows and columns, and, more particularly, arranged into four regions, i.e., TL, BL, TR and BR. Each region is bordered by backbone220(on two sides), and includes an equal number of memory modules230(i.e., 25% of the total number of memory modules230) that are serviced by backbone220.

Various numbers and arrangements of memory modules230are supported, such as, for example, 16 memory modules230arranged into 4 regions (i.e., 4 memory modules230per region), 32 memory modules230arranged into 4 regions (i.e., 8 memory modules230per region), 64 memory modules230arranged into 4 regions (i.e., 16 memory modules230per region), 128 memory modules230arranged into 4 regions (i.e., 32 memory modules230per region), etc.

Generally, each region includes “i” rows and “j” columns of memory modules230. In many embodiments, “i” and “j” are the same (e.g., 2, 4, etc.), while in other embodiments, “i” and “j” may be different (e.g., “i” equals 2 and “j” equals 4, etc.).

The TL region includes a first row, i.e., memory module23011(MM11), . . . , MM1j, (i-2) intermediate rows, and a last row, i.e., memory module230i1(MMij), . . . , MMij. The TL region also includes a first column, i.e., MM11, . . . , MMij, (j-2) intermediate columns, and a last column, i.e., MM1i, . . . , MMij.

The BL region includes a first row, i.e., memory module230i+11(MMi+11), . . . , MMi+1j, (i-2) intermediate rows, and a last row, i.e., memory module230N1(MMN1), MMNj. The BL region also includes a first column, i.e., (MMi+11), . . . , MMN1, (j-2) intermediate columns, and a last column, i.e., MMi+1j, . . . , MMNj.

The TR region includes a first row, i.e., MM1j+1, . . . , memory module2301M(MM1M), (i-2) intermediate rows, and a last row, i.e., MMij+1, . . . , memory module230iM(MMiM). The TR region also includes a first column, i.e., MM1j+1, . . . , MM1j+1, j-2) intermediate columns, and a last column, i.e., MM1M, . . . , MMiM.

The BR region includes a first row, i.e., MMi+1j+1, . . . , memory module230i+1M(MMi+1M), (i-2) intermediate rows, and a last row, i.e., MMNj+1, . . . , memory module230NM(MMNM). The BR region also includes a first column, i.e., (MMi+1j+1), . . . , MMNj+1, (j-2) intermediate columns, and a last column, i.e., MMi+1M, . . . , MMNM.

In this embodiment, N equals 2·i and M equals 2·j.

For example, for the embodiment including 16 memory modules230arranged into 4 regions (i.e., 4 memory modules230per region), i and j equal 2, N and M equal 4, and there are no intermediate rows or intermediate columns in each region.

With respect toFIG.2B, memory200includes, inter alia, an array210including backbone220, branches222, memory modules230, as well as other components not depicted for clarity. Generally, array210has a width in a lateral direction, and a height in a longitudinal direction. Backbone220is a data, address and control signal bus that includes a primary portion and a number of secondary portions, while branches222extend the data, address and control signal bus of backbone220to support larger arrays210. Backbone220and branches220generally divide array210into regions.

In many embodiments, the primary portion of backbone220is disposed in the lateral center of array210and extends in the longitudinal direction from the lower edge to the upper edge of array210(i.e., approximately the height of array210), a first secondary portion of backbone220is disposed in the longitudinal center of array210and extends in a first lateral direction from the primary portion of backbone220to a left edge of array210(i.e., approximately 50% of the width of array210), and a second secondary portion of backbone220is disposed in the longitudinal center of array210and extends in a second lateral direction from the primary portion of backbone220to a right edge of array210(i.e., approximately 50% of the width of array210).

A first branch2221extends in the longitudinal direction from the center of the first secondary portion of backbone220to the upper edge of array210(i.e., approximately 50% of the height of array210). A second branch2222extends in the longitudinal direction from the center of the first secondary portion of backbone220to the lower edge of array210(i.e., approximately 50% of the height of array210). A third branch2223extends in the longitudinal direction from the center of the second secondary portion of backbone220to the upper edge of array210(i.e., approximately 50% of the height of array210). A fourth branch2224extends in the longitudinal direction from the center of the second secondary portion of backbone220to the lower edge of array210(i.e., approximately 50% of the height of array210).

In this embodiment, the primary and secondary portions of backbone220, and branches2221,2222,2223and2224, divide array210into eight regions, which, for convenience, are referred to as the first top left (TL1) region, the second top left (TL2) region, the first bottom left (BL1) region, the second bottom left (BL2) region, the first top right (TR1) region, the second top right (TR2) region, the first bottom right (BR1) region, and the second bottom right (BR2) region. Different numbers of regions and branches222are also supported, such as, for example, 4 branches222and 12 regions, 6 branches222and 16 regions, 8 branches222and 24 regions, etc., as well as additional secondary portions of backbone220, such as 4 additional secondary portions of backbone220(for a total of 6 secondary portions), etc.

In many embodiments, branches222extend both the address bus and the data bus of backbone220; in other embodiments, each branch222extends either the address bus or the data bus of backbone220.

In this embodiment, array210includes a total number of memory modules230, arranged in rows and columns, and, more particularly, arranged into eight regions i.e., TL1, TL2, BL1, BL2, TR1, TR2, BR1and BR2. Each region is bordered by backbone220(at least on one side) and at least one of the branches220(on one side), and includes an equal number of memory modules230(i.e., 12.5% of the total number of memory modules230) that are serviced by backbone220and branches220.

Various numbers and arrangements of memory modules230are supported, such as, for example, 32 memory modules230arranged into 8 regions (i.e., 4 memory modules230per region), 64 memory modules230arranged into 8 regions (i.e., 8 memory modules230per region), 64 memory modules230arranged into 16 regions (i.e., 4 memory modules230per region), 128 memory modules230arranged into 8 regions (i.e., 16 memory modules230per region), 128 memory modules230arranged into 16 regions (i.e., 8 memory modules230per region), 128 memory modules230arranged into 32 regions (i.e., 4 memory modules230per region), etc.

Generally, each region includes “i” rows and “j” columns of memory modules230. In many embodiments, “i” and “j” are the same (e.g., 2, 4, etc.), while in other embodiments, “i” and “j” may be different (e.g., “i” equals 2 and “j” equals 4, etc.).

The TL1region includes a first row, i.e., memory module23011(MM11), . . . , MM1j, (i-2) intermediate rows, and a last row, i.e., memory module230i1(MMi1), . . . , MMij. The TL1also region includes a first column, i.e., MM11, . . . , MMi1, (j-2) intermediate columns, and a last column, i.e., MM1j, . . . , MMij. The TL2region includes a first row, i.e., MM1j+1, . . . , MM1k, (i-2) intermediate rows, and a last row, i.e., MMij+1, . . . , MMik. The TL2region also includes a first column, i.e., MM1j+1, . . . , MMij+1, (j-2) intermediate columns, and a last column, i.e., MM1k, . . . , MMik.

The BL1region includes a first row, i.e., memory module230i+11(MMi+11), . . . , MMi+1j, (i-2) intermediate rows, and a last row, i.e., memory module230N1(MMN1), . . . , MMNj. The BL1region also includes a first column, i.e., (MMi+11), . . . , MMN1, (j-2) intermediate columns, and a last column, i.e., MMi+1j, . . . , MMNj. The BL2region includes a first row, i.e., MMi+1i+1, . . . , MMi+1k, (i-2) intermediate rows, and a last row, i.e., MMNj+1, . . . , MMNk. The BL2region also includes a first column, i.e., MMi+1j+1, . . . , MMNj+1, (j-2) intermediate columns, and a last column, i.e., MMi+1k, . . . , MMNk.

The TR1region includes a first row, i.e., MM1k+1, . . . , MM1l, (i-2) intermediate rows, and a last row, i.e., MMik+1, . . . , MMil. The TR1region also includes a first column, i.e., MM1k+1, . . . , MMik+1, (j-2) intermediate columns, and a last column, i.e., MM1l, . . . , MMil. The TR2region includes a first row, i.e., MM1l+1, . . . , memory module2301M(MM1M), and a last row, i.e., MMil+1, . . . , memory module230iM(MMiM). The TR2region also includes a first column, i.e., MM1l+1, . . . , MMil+1, and a last column, i.e., MM1M, . . . , MMiM.

The BR1region includes a first row, i.e., MMi+1k+1, . . . , MMi+1l, (i-2) intermediate rows, and a last row, i.e., MMNk+1, . . . , MMNl. The BR1region also includes a first column, i.e., MMi+1k+1, . . . , MMNk+1, (j-2) intermediate columns, and a last column, i.e., MMi+1l, . . . , MMNl. The BR2region includes a first row, i.e., MMi+1l+1, . . . , memory module230i+1M(MMi+1M), (i-2) intermediate rows, and a last row, i.e., MMNl+1, . . . , memory module230NM(MMNM). The BR2region also includes a first column, i.e., MMi+1l+1, MMNl+1, (j-2) intermediate columns, and a last column, i.e., MMi+1M, . . . , MMNM.

In this embodiment, N equals 2·i, k equals 2·j, I equals 3·j, and M equals 4·j.

FIG.3depicts a block diagram of memory module230, in accordance with an embodiment of the present disclosure.

Generally, a system cache module may include memory cells that are coupled to wordlines to form rows, and to bitline pairs to form columns. More particularly, each memory cell is coupled to one wordline and one bitline pair, and stores a single bit having a value of 0 or 1. In a simple cache memory architecture, the number of columns is equal to the word length, N, of the memory, and each row of memory cells stores one word by storing one bit of the word in each memory cell of the row. For example, a memory having a word length of 32 bits (i.e., 4 bytes) has 32 columns of memory cells. Generally, a system cache module reads (i.e., outputs) or writes (inputs) one word at a time.

For both reading and writing data, each word is identified by an address, which is an m-bit number that is decoded to provide the row number (i.e., wordline) along which the word is stored. For example, an 8-bit address encodes 256 rows, i.e., M=28=256. The address may be input to an address decoder via 8 individual bit or signal lines, as an 8-bit unsigned integer value, etc. The memory size is simply the number of addresses multiplied by the word length, such as, for example, 256 addresses·4 bytes/address=1,024 bytes.

Embodiments of the present disclosure provide a more sophisticated memory architecture in which the columns are arranged into a number of bitline groups in order to store more than one word along each row of the memory, and the bitline groups are organized into ways to store even more words along each row of the memory.

Memory module230includes I/O circuitry250, control circuitry260, wordline (WL) control circuitry262, and memory regions280. I/O circuitry250includes, inter alia, bitline precharge circuits, sense amplifiers, multiplexers, buffers, I/O data bus(es), etc. Control circuitry260is disposed in the center of memory module230, and is coupled to I/O circuitry250as well as WL control circuitry262. I/O circuitry250includes a first portion that extends in a first lateral direction from control circuitry260to a left edge, e.g., I/O circuitry250L, and a second portion that extends in a second lateral direction from control circuitry260to a right edge, e.g., I/O circuitry250R. WL control circuitry262includes a first portion that extends in a first longitudinal direction from control circuitry260to a top edge, e.g., WL control circuitry262T, and a second portion that extends in a second longitudinal direction from control circuitry260to a bottom edge, e.g., WL control circuitry262B.

Generally, I/O circuitry250and WL control circuitry262divide the memory cells into a number of memory regions280, e.g., memory regions280TL,280BL,280TR, and280BR, and each memory region280includes a number of memory cells that are coupled to wordlines232to form rows, and to bitline pairs242to form columns. More particularly, each memory cell is coupled to one wordline232and one bitline pair242, and stores a single bit having a value of 0 or 1. Each memory region280has a number of wordlines232and a number of bitline pairs242, i.e., memory region280TLincludes wordlines232Tand bitline pairs242L, memory region280BLincludes wordlines232Band bitline pairs242L, memory region280TRincludes wordlines232Tand bitline pairs242R, and memory region280BRincludes wordlines232Band bitline pairs242R.

As noted above, a cache memory may be divided into a number of ways, and the number of bitline groups, N, is equal to the number of ways multiplied by the word size. For example, N is equal to 32 for a 1-way cache with 32-bit words (N=1·32=32), N is equal to 256 for an 8-way cache with 32-bit words (N=8·32=256), etc. In many embodiments, the way number may be determined by the lower w-bits of the address, while the remaining bits are decoded to determine the wordline. For example, the lower 3 bits of the address determine the way number for an 8-way cache, (i.e., 23=8). The number of columns in each group, C, is the same (e.g., 4), and each row stores N·C words. The particular word within each group of a selected way may be determined by the next c bits in the address, e.g., when C equals 4, the next 2 bits may be used to determine the word within the group (i.e., 22=4). Other address decoding schemes are also supported. Alternatively, a separate burst read request, including, inter alia, a burst address signal to select which word or words are to be selectively read from each group of a selected way, may be provided.

A more detailed discussion of various embodiments of this memory architecture, including the unique burst read functionality, may be found in related U.S. patent application Ser. No. 17/885,709 (entitled “Burst Read With Flexible Burst Length for On-Chip Memory,” filed concurrently herewith), the content of which is incorporated by reference herein in its entirety.

FIGS.4A and4Bdepict memory module230, in accordance with embodiments of the present disclosure.

Wordlines232Thave been divided into two sections, i.e., WL section 1 and WL section 2, and wordlines232Bhave been divided into two sections, i.e., WL section 3 and WL section 4. In this embodiment, each wordline section includes 256 wordlines, so memory module230includes a total of 1,024 wordlines (4·256=1,024).

WL control circuitry262Thas been divided into WL control circuitry2621and WL control circuitry2622, while WL control circuitry262Bhas been divided into WL control circuitry2623and WL control circuitry2624. WL control circuitry2621controls WL section 1, WL control circuitry2622controls WL section 2, WL control circuitry2623controls WL section 3, and WL control circuitry2623controls WL section 4.

Bitline pairs242Lhave been divided into 128 bitline groups (BLGs) and 128 flyover bitline groups (FBLGs), and each BLG and FBLG includes 4 columns, i.e., 4 bitline pairs. Similarly, bitline pairs242Rhave been divided into 128 BLGs and 128 FBLGs, and each BLG and FBLG includes 4 columns, i.e., 4 bitline pairs. Flyover bitlines reduce capacitance for switch power and speed of access. Each wordline232is coupled to one memory cell in each column, and each memory cell is coupled to a single bitline pair, so each wordline is coupled to 1,024 memory cells (i.e., 256·4=1,024). Accordingly, memory module230stores 1 Mb of data (i.e., 1,024·256·4=1 Mb).

More particularly, WL section 1 includes wordlines WL1, . . . , WL256coupled to the memory cells within BLG1, . . . , BLG256, WL section 2 includes wordlines WL257, . . . , WL512coupled to the memory cells within FBLG1, . . . , FBLG256, WL section 3 includes wordlines WL513, . . . , WL768coupled to the memory cells within BLG1, . . . , BLG256, and WL section 4 includes wordlines WL769, . . . , WL1024coupled to the memory cells within FBLG1, . . . , FBLG256. For clarity, only certain WLs, BLGs and FBLGs have been labeled, and the associated memory cells are simply represented as a squares.

FIG.4Cdepicts a power state for memory module230, in accordance with embodiments of the present disclosure.

Rather than simply power up an entire memory module230in order to service read or write requests to one or more addresses associated with the memory module230, embodiments of the present disclosure advantageously manage power to particular regions, sections and components based on these addresses. More particularly, in addition to I/O circuitry250, control circuitry260powers up wordline control circuitry262for the particular wordline section with which the address is associated which saves a significant amount of power and reduces inrush current.

For illustration purposes, memory region280TLhas been divided into memory regions2801Land2802L, memory region280BLhas been divided into memory regions2803Land2804L, memory region280TRhas been divided into memory regions2801Rand2802R, memory region280BRhas been divided into memory regions2803Rand2804R. Wordline section 1 includes memory regions2801Land2801R, wordline section 2 includes memory regions2802Land2802R, wordline section 3 includes memory regions2803Land2803R, and wordline section 4 includes memory regions2804Land2804R.

In the example depicted inFIG.4C, a read or write request has been received by memory module230that includes an address that decodes to a wordline within the range of WL1, . . . , WL256in wordline section 1. In response, control circuitry260powers up I/O circuitry250Land250R(i.e., “I/O Circuitry on”) and WL control circuitry2621(i.e., “on”) which controls the wordlines within the range of WL1, . . . , WL256(i.e., “WL on”). This process subjects the power supply for memory module230to the peak demand. In certain embodiments, control circuitry260may initially power up I/O circuitry250Land delay the power up of I/O circuitry250Rto mitigate the peak demand.

Advantageously, the remaining 75% of wordlines232(i.e., the wordlines within WL sections 2, 3 and 4) and the remaining 50% of the bitline pairs (i.e., the bitline pairs within FBLG1, . . . , FBLG256) are not powered up at this time, thereby saving a significant amount of power and reduces peak demand, inrush current, etc. compared to simply powering up the entirety of memory module230.

Additionally, when a timely read or write request is received for an address that decodes to a wordline within the range of WL1, . . . , WL256in wordline section 1, I/O circuitry250Land250R, the bitline pairs within BLG1, . . . , BLG256and WL control circuitry2621are already powered up, which improves latency when compared to an initial power up sequence.

In many embodiments, memory module230is powered down after a predetermined time after the read or write request has been serviced. Advantageously, control circuitry260automatically manages the power control for internal components of memory module230, and no external commands, e.g., via I/O pins, are needed.

Embodiments of the present disclosure advantageously provide power up (and power down) sequences for all of the wordline sections of memory module230.

FIGS.4D,4E and4Fdepict power states for memory module230, in accordance with embodiments of the present disclosure.

While one or more sequential read or write requests to memory locations within wordline section 1 (i.e., memory regions2801Land2801R) are being serviced, control circuitry260may power up the remaining wordline sections of memory module230.

As depicted inFIG.4D, control circuitry260powers up wordline section 3 (i.e., memory regions2803Land2803R) while the read or write requests to memory locations within wordline section 1 are being serviced. More particularly, control circuitry260powers up WL control circuitry2623(i.e., “pwr”) which controls the wordlines within the range of WL513, . . . , WL768(i.e., “WL power up”). Because wordline sections 1 and 3 share the same bitlines, i.e., BLG1, . . . , BLG256, less power may be required, etc. In certain embodiments, the wordlines in wordline section 1 (i.e., WL1, . . . , WL256) and wordline section 3 (i.e., WL513, . . . , WL768) may be mapped to contiguous addresses.

As depicted inFIG.4E, control circuitry260powers up wordline section 4 (i.e., memory regions2804Land2804R) while the read or write requests to memory locations within wordline section 1 are being serviced. In certain embodiments, wordline sections 3 and 4 power up processes overlap at least for a period of time.

As depicted inFIG.4F, control circuitry260powers up wordline section 3 (i.e., memory regions2802Land2802R) while the read or write requests to memory locations within wordline section 1 are being serviced. In certain embodiments, power up for wordline sections 2 and 4, or for wordline sections 2, 3 and 4, may overlap in time.

Other wordline power on sequences are also supported.

FIGS.5A and5Bdepict memory module230, in accordance with embodiments of the present disclosure.

Wordlines232Thave been divided into eight sections, i.e., WL sections 1 to 8, and wordlines232Bhave been divided into eight sections, i.e., WL sections 9 to 16. In this embodiment, each wordline section includes 64 wordlines, so memory module230includes a total of 1,024 wordlines (16·64=1,024).

WL control circuitry262Thas been divided into WL control circuitry2621, . . .2628, while WL control circuitry262Bhas been divided into WL control circuitry2629, . . .26216. WL control circuitry2621controls WL section 1, WL control circuitry2622controls WL section 2, WL control circuitry2623controls WL section 3, and WL control circuitry2623controls WL section 4, WL control circuitry2625controls WL section 5, WL control circuitry2626controls WL section 6, WL control circuitry2627controls WL section 7, and WL control circuitry2628controls WL section 8. WL control circuitry2629controls WL section 9, WL control circuitry26210controls WL section 10, WL control circuitry26211controls WL section 11, WL control circuitry26212controls WL section 12, WL control circuitry26213controls WL section 13, WL control circuitry26214controls WL section 14, WL control circuitry26215controls WL section 15, and WL control circuitry26216controls WL section 16.

Bitline pairs242Lhave been divided into 128 bitline groups (BLGs) and 128 flyover bitline groups (FBLGs), and each BLG and FBLG includes 4 columns, i.e., 4 bitline pairs. Similarly, bitline pairs242Rhave been divided into 128 BLGs and 128 FBLGs, and each BLG and FBLG includes 4 columns, i.e., 4 bitline pairs. Each wordline232is coupled to one memory cell in each column, and each memory cell is coupled to a single bitline pair, so each wordline is coupled to 1,024 memory cells (i.e., 256·4=1,024). Accordingly, memory module230stores 1 Mb of data (i.e., 1,024·256·4=1 Mb).

More particularly, WL section 1 includes wordlines WL1, . . . , WL64coupled to the memory cells within BLG1, . . . , BLG256, WL section 2 includes wordlines WL65, . . . , WL128coupled to the memory cells within BLG1, . . . , BLG256, WL section 3 includes wordlines WL129, . . . , WL192coupled to the memory cells within BLG1, . . . , BLG256, WL section 4 includes wordlines WL193, . . . , WL256coupled to the memory cells within BLG1, . . . , BLG256, WL section 5 includes wordlines WL257, . . . , WL320coupled to the memory cells within FBLG1, . . . , FBLG256, WL section 6 includes wordlines WL321, . . . , WL384coupled to the memory cells within FBLG1, . . . , FBLG256, WL section 7 includes wordlines WL385, . . . , WL448coupled to the memory cells within FBLG1, . . . , FBLG256, and WL section 8 includes wordlines WL449, . . . , WL512coupled to the memory cells within FBLG1, . . . , FBLG256.

Similarly, WL section 9 includes wordlines WL513, . . . , WL576coupled to the memory cells within BLG1, . . . , BLG256, WL section 10 includes wordlines WL577, . . . , WL640coupled to the memory cells within BLG1, . . . , BLG256, WL section 11 includes wordlines WL641, . . . , WL704coupled to the memory cells within BLG1, . . . , BLG256, WL section 12 includes wordlines WL705, . . . , WL768coupled to the memory cells within BLG1, . . . , BLG256, WL section 13 includes wordlines WL769, . . . , WL832coupled to the memory cells within FBLG1, . . . , FBLG256, WL section 14 includes wordlines WL833, . . . , WL896coupled to the memory cells within FBLG1, . . . , FBLG256, WL section 15 includes wordlines WL897, . . . , WL960coupled to the memory cells within FBLG1, . . . , FBLG256, and WL section 16 includes wordlines WL961, . . . , WL1024coupled to the memory cells within FBLG1, . . . , FBLG256.

For clarity, only certain WLs, BLGs and FBLGs have been labeled, and the associated memory cells are simply represented as a squares.

FIG.5Cdepict a power status for memory module230, in accordance with embodiments of the present disclosure.

Similar to the embodiment of memory module230depicted inFIG.4C, rather than simply power up an entire memory module230in order to service read or write requests to one or more addresses associated with the memory module230, embodiments of the present disclosure advantageously manage power to particular regions, sections and components based on these addresses. More particularly, in addition to I/O circuitry250, control circuitry260powers up (and powers down) the particular wordline section with which the address is associated which saves a significant amount of power and reduces inrush current.

For illustration purposes, memory region280TLhas been divided into memory regions2801L, . . . ,2808L, memory region280BLhas been divided into memory regions2809L, . . . ,28016L, memory region280TRhas been divided into memory regions2801R, . . . ,2808R, memory region280BRhas been divided into memory regions2809R, . . .28016R.

Wordline section 1 includes memory regions2801Land2801R, wordline section 2 includes memory regions2802Land2802R, wordline section 3 includes memory regions2803Land2803R, wordline section 4 includes memory regions2804Land2804R, wordline section 5 includes memory regions2805Land2805R, wordline section 6 includes memory regions2806Land2806R, wordline section 7 includes memory regions2807Land2807R, wordline section 8 includes memory regions2808Land2808R, wordline section 9 includes memory regions2809Land2809R, wordline section 10 includes memory regions28010Land28010R, wordline section 11 includes memory regions28011Land28011R, wordline section 12 includes memory regions28012Land28012R, wordline section 13 includes memory regions28013Land28013R, wordline section 14 includes memory regions28014Land28014R, wordline section 15 includes memory regions28015Land28015R, and wordline section 16 includes memory regions28016Land28016R.

In the example depicted inFIG.5C, a read or write request has been received by memory module230that includes an address that decodes to a wordline within the range of WL129, . . . , WL192in wordline section 3. In response, control circuitry260powers up I/O circuitry250Land250R(i.e., “I/O Circuitry on”) and WL control circuitry2623(i.e., “on”) which controls the wordlines within the range of WL129, . . . , WL192(i.e., “WL on”). This process subjects the power supply for memory module230to the peak demand. In certain embodiments, control circuitry260may initially power up I/O circuitry250Land delay the power up of I/O circuitry250Lto mitigate the peak demand.

Advantageously, the remaining ˜93% of wordlines232(i.e., the wordlines within WL sections 1, 2 and 4 to 16) are not powered up, thereby saving a significant amount of power compared to simply powering up the entirety of memory module230.

Additionally, when a timely read or write request is received for an address that decodes to a wordline within the range of WL129, . . . , WL192in wordline section 3, I/O circuitry250Land250R, and WL control circuitry2623associated with the wordlines within the range of WL129, . . . , WL192(i.e., “WL on”) are already powered up, which improves latency when compared to an initial power up sequence.

In many embodiments, memory module230is powered down after a predetermined time after the read or write request has been serviced. Advantageously, control circuitry260automatically manages the power control for internal components of memory module230, and no external commands, e.g., via I/O pins, are needed.

Embodiments of the present disclosure advantageously provide power up (and power down) sequences for all of the wordline sections of memory module230.

FIGS.5D,5E and5Fdepict power states for memory module230, in accordance with embodiments of the present disclosure.

While one or more sequential read or write requests to memory locations within wordline section 1 (i.e., memory regions2801Land2801R) are being serviced, control circuitry260may power up certain wordline sections of memory module230.

As depicted inFIG.5D, control circuitry260powers up wordline section 12 while the read or write requests to memory locations within wordline section 3 are being serviced. More particularly, control circuitry260powers up WL control circuitry26212(i.e., “pwr”) which controls the wordlines within the range of WL705, . . . , WL768(i.e., “WL power up”). Because wordline sections 3 and 12 share the same bitlines, i.e., BLG1, . . . , BLG256, less power may be required, etc.

As depicted inFIG.5E, control circuitry260powers up wordline sections 11 and 13 while the read or write requests to memory locations within wordline section 3 are being serviced. More particularly, control circuitry260powers up WL control circuitry26211(i.e., “pwr”) which controls the wordlines within the range of WL641, . . . , WL704(i.e., “WL power up”). Because wordline sections 3, 11 and 12 share the same bitlines, i.e., BLG1, . . . , BLG256, less power may be required, etc. Control circuitry260also powers up WL control circuitry26213(i.e., “pwr”) which controls the wordlines within the range of WL769, . . . , WL832(i.e., “WL power up”). In certain embodiments, wordline sections 11, 12 and 13 power up processes overlap at least for a period of time.

As depicted inFIG.5F, control circuitry260powers up wordline sections 1, 2 and 4 while the read or write requests to memory locations within wordline section 3 are being serviced. More particularly, control circuitry260powers up WL control circuitry2621(i.e., “pwr”) which controls the wordlines within the range of WL1, . . . , WL64(i.e., “WL power up”), WL control circuitry2622(i.e., “pwr”) which controls the wordlines within the range of WL65, . . . , WL128(i.e., “WL power up”), and WL control circuitry2624(i.e., “pwr”) which controls the wordlines within the range of WL193, . . . , WL256(i.e., “WL power up”). Because wordline sections 1, 2, 3, 4, 11 and 12 share the same bitlines, i.e., BLG1, . . . , BLG256, less power may be required, etc. In certain embodiments, wordline sections 1, 2 and 4 power up processes overlap at least for a period of time. In some embodiments, one or more wordline sections 1, 2, 4, 11, 12 and 13 power up processes may overlap at least for a period of time.

Other wordline power on sequences are also supported.

FIG.6depicts flow diagram300for managing the power of memory module230of a system cache (SC), in accordance with embodiments of the present disclosure.

At310, an access request for memory module230is received. The access request includes at least an address. In many embodiments, prior to receiving the access request, power was not applied to wordline control circuitry262, I/O circuitry250and control circuitry260. In other words, memory module230was generally shut down and power was gated off for instances and logic, while the memory storage elements, i.e., the memory cells, were retaining their respective values.

At320, power is applied to control circuitry260, various internal power gates are turned on in anticipation of power up, etc. Generally, these activities may form a first, or wakeup, power stage.

At330, the address is decoded by control circuitry260. In many embodiments, decoding the address includes determining, based on the address, a wordline232of memory module230, and determining, based on the wordline232, a wordline section of memory module230, such as, for example, wordline section 1, wordline section 3, etc.

At340, power is applied to certain components of memory module230. At3421, power is applied to the wordline control circuitry262; that is coupled to the wordline section determined at330, such as, for example, wordline control circuitry2621for wordline section 1, wordline control circuitry2623for wordline section 3, etc. At344, power is applied to I/O circuitry250. Generally, the activities at330and340may form a second power stage.

In one embodiment, while applying power to the wordline control circuitry2621that is coupled to the wordline section determined at330, at3422, power may be applied to a different wordline control circuitry262j, such as, for example, wordline control circuitry2622for wordline section 2, wordline control circuitry2624for wordline section 4, etc. In another embodiment, while applying power to the wordline control circuitry2621that is coupled to the wordline section determined at330, power may be sequentially applied to at least two additional wordline control circuitry262j, such as, for example, wordline control circuitry2622for wordline section 2 and wordline control circuitry2624for wordline section 4, etc. In a further embodiment, while applying power to the wordline control circuitry2621that is coupled to the wordline section determined at330, power may be sequentially applied to the remaining wordline control circuitry262, e.g., at3422, . . . ,342s.

At350, the address is accessed. For example, a read request reads the memory cells at the address, a write request writes data (included the access request) to the memory cells at the address, etc.

The embodiments described herein are combinable.

In one embodiment, a method for managing power in a memory includes receiving an access request for a memory, the access request including an address, the memory including a plurality of wordline sections, each wordline section including a number of wordlines; applying power to control circuitry; decoding the address, including determining, based on the address, an associated wordline, and determining, based on the associated wordline, an associated wordline section; and applying power to wordline control circuitry coupled to the associated wordline section, each wordline section of the plurality of wordline sections being coupled to a different wordline control circuitry.

In another embodiment, the method further includes, while applying power to the wordline control circuitry coupled to the associated wordline section, applying power to input/output (I/O) circuitry.

In another embodiment of the method, the I/O circuitry includes a first1/O circuitry portion and a second I/O circuitry portion, and said applying power to the I/O circuitry includes applying power to the first I/O circuitry portion and delaying applying power to the second I/O circuitry portion.

In another embodiment, the method further includes, while applying power to the wordline control circuitry coupled to the associated wordline section, applying power to wordline control circuitry coupled to a different wordline section.

In another embodiment, the method further includes, while applying power to the wordline control circuitry coupled to the associated wordline section, sequentially applying power to wordline control circuitry coupled to at least two different wordline sections.

In another embodiment, the method further includes, while applying power to the wordline control circuitry coupled to the associated wordline section, sequentially applying power to wordline control circuitry coupled to the remaining wordline sections.

In another embodiment of the method, prior to said receiving the access request, power was not applied to the wordline control circuitry, the I/O circuitry and the control circuitry.

In another embodiment, the method further includes accessing the address.

In another embodiment of the method, the plurality of wordline sections includes at least four wordline sections, and each wordline section includes a same number of wordlines.

In another embodiment of the method, at least two wordline sections are coupled to a number of bitline groups, each bitline group including a number of bitline pairs; and at least two wordline sections are coupled to a number of flyover bitline groups, each flyover bitline group including a number of flyover bitline pairs.

In one embodiment, a memory includes a plurality of wordline sections, each wordline section including a number of wordlines, and each wordline section coupled to a different wordline control circuitry; and control circuitry, coupled to the wordline control circuitry and input/output (I/O) circuitry, configured to, in response to receiving an access request including an address, decode the address, including determine, based on the address, an associated wordline of the memory, and determine, based on the associated wordline, an associated wordline section of the memory, and apply power to wordline control circuitry coupled to the associated wordline section.

In another embodiment of the memory, the control circuitry is further configured to, while applying power to the wordline control circuitry coupled to the associated wordline section, apply power to the I/O circuitry.

In another embodiment of the memory, the I/O circuitry includes a first I/O circuitry portion and a second I/O circuitry portion, and said apply power to the I/O circuitry includes apply power to the first I/O circuitry portion and delaying apply power to the second I/O circuitry portion.

In another embodiment of the memory, the control circuitry is further configured to, while applying power to the wordline control circuitry coupled to the associated wordline section, apply power to wordline control circuitry coupled to a different wordline section.

In another embodiment of the memory, the control circuitry is further configured to, while applying power to the wordline control circuitry coupled to the associated wordline section, sequentially apply power to wordline control circuitry coupled to at least two different wordline sections.

In another embodiment of the memory, the control circuitry is further configured to, while applying power to the wordline control circuitry coupled to the associated wordline section, sequentially apply power to wordline control circuitry coupled to the remaining wordline sections.

In another embodiment of the memory, prior to said receiving the access request, power was not applied to the wordline control circuitry, the I/O circuitry and the control circuitry.

In another embodiment of the memory, the control circuitry is further configured to access the address.

In another embodiment of the memory, the plurality of wordline sections includes at least four wordline sections, and each wordline section includes a same number of wordlines; at least two wordline sections are coupled to a number of bitline groups, each bitline group including a number of bitline pairs; and at least two wordline sections are coupled to a number of flyover bitline groups, each flyover bitline group including a number of flyover bitline pairs.

In one embodiment, a system cache includes a plurality of memories as described above.

While implementations of the disclosure are susceptible to embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the present disclosure is to be considered as an example of the principles of the disclosure and not intended to limit the disclosure to the specific embodiments shown and described. In the description above, like reference numerals may be used to describe the same, similar or corresponding parts in the several views of the drawings.

In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Reference throughout this document to “one embodiment,” “certain embodiments,” “an embodiment,” “implementation(s),” “aspect(s),” or similar terms means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of such phrases or in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.

The term “or” as used herein is to be interpreted as an inclusive or meaning any one or any combination. Therefore, “A, B or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B and C.” An exception to this definition will occur only when a combination of elements, functions, steps or acts are in some way inherently mutually exclusive. Also, grammatical conjunctions are intended to express any and all disjunctive and conjunctive combinations of conjoined clauses, sentences, words, and the like, unless otherwise stated or clear from the context. Thus, the term “or” should generally be understood to mean “and/or” and so forth. References to items in the singular should be understood to include items in the plural, and vice versa, unless explicitly stated otherwise or clear from the text.

Recitation of ranges of values herein are not intended to be limiting, referring instead individually to any and all values falling within the range, unless otherwise indicated, and each separate value within such a range is incorporated into the specification as if it were individually recited herein. The words “about,” “approximately,” or the like, when accompanying a numerical value, are to be construed as indicating a deviation as would be appreciated by one of ordinary skill in the art to operate satisfactorily for an intended purpose. Ranges of values and/or numeric values are provided herein as examples only, and do not constitute a limitation on the scope of the described embodiments. The use of any and all examples, or exemplary language (“e.g.,” “such as,” “for example,” or the like) provided herein, is intended merely to better illuminate the embodiments and does not pose a limitation on the scope of the embodiments. No language in the specification should be construed as indicating any unclaimed element as essential to the practice of the embodiments.

For simplicity and clarity of illustration, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. Numerous details are set forth to provide an understanding of the embodiments described herein. The embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have not been described in detail to avoid obscuring the embodiments described. The description is not to be considered as limited to the scope of the embodiments described herein.

In the following description, it is understood that terms such as “first,” “second,” “top,” “bottom,” “up,” “down,” “above,” “below,” and the like, are words of convenience and are not to be construed as limiting terms. Also, the terms apparatus, device, system, etc. may be used interchangeably in this text.

The many features and advantages of the disclosure are apparent from the detailed specification, and, thus, it is intended by the appended claims to cover all such features and advantages of the disclosure which fall within the scope of the disclosure. Further, since numerous modifications and variations will readily occur to those skilled in the art, it is not desired to limit the disclosure to the exact construction and operation illustrated and described, and, accordingly, all suitable modifications and equivalents may be resorted to that fall within the scope of the disclosure.