Patent ID: 12237415

DETAILED DESCRIPTION

Referring toFIGS.1-5,FIGS.1-5illustrate a method for fabricating semiconductor device according to an embodiment of the present invention. As shown inFIG.1, a substrate12is provided and gate structures14,16are formed on the substrate12. In this embodiment, the formation of the gate structures14,16could be accomplished by sequentially forming a gate dielectric layer, a gate material layer, and a hard mask on the substrate12, conducting a pattern transfer process by using a patterned resist (not shown) as mask to remove part of the hard mask, part of the gate material layer, and part of the gate dielectric layer through single or multiple etching processes, and then stripping the patterned resist. This forms gate structures14and16each composed of a patterned gate dielectric layer18, a patterned gate material layer20, and a patterned hard mask22.

It should be noted that even though two gate structures14,16are disclosed in this embodiment, the quantity or number of the gate structures14,16is not limited to two, but could all be adjusted according to the demand of the product. Moreover, only part of the gate structures14,16, such as the right portion of the gate structure14and left portion of the gate structure16are shown inFIG.1to emphasize the formation of buffer layer and epitaxial layer between gate structures14,16in later process.

In this embodiment, the substrate12could be a semiconductor substrate such as a silicon substrate, an epitaxial substrate, a SiC substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The gate dielectric layer18could include SiO2, SiN, or high-k dielectric material; the gate material layer20could include metal, polysilicon, or silicide; and the material of hard mask22could be selected from the group consisting of SiO2, SiN, SiC, and SiON.

According to an embodiment of the present invention, a plurality of doped wells or shallow trench isolations (STIs) could be selectively formed in the substrate12. Despite the present invention pertains to a planar MOS transistor, it would also be desirable to apply the process of the present invention to non-planar transistors such as FinFET devices, and in such instance, the substrate12shown inFIG.1would become a fin-shaped structure formed atop a substrate12.

Next, at least one spacer24is formed on the sidewalls of the gate structures14and16. Optionally, after a lightly doped ion implantation processes is conducted, a rapid thermal annealing processes is performed at about 930° C. to active the dopants implanted in the substrate12for forming lightly doped drains26in the substrate12adjacent to two sides of the spacer24. In this embodiment, the spacer24could be a single or composite spacer, in which the spacer24could further include an offset spacer (not shown) and a main spacer (not shown). The offset spacer and the main spacer are preferably made of different material while the offset spacer and main spacer could all be selected from the group consisting of SiO2, SiN, SiON, and SiCN, but not limited thereto.

Next, a dry etching and/or wet etching process is conducted by using the gate structures14,16and spacers24as mask to remove part of the substrate12through single or multiple etching processes for forming recesses28in the substrate12adjacent to two sides of the gate structures14,16. Preferably, the etching process could be accomplished by first conducting a dry etching process to form initial recesses (not shown) in the substrate12adjacent to two sides of the gate structure16, and then conducting a wet etching process to expand the recesses isotropically for forming recess28. According to an embodiment of the present invention, the wet etching process could be accomplished by using etchant including but not limited to for example ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH). It should be noted that the formation of the recesses28is not limited to the combination of dry etching process and wet etching process addressed previously. Instead, the recesses28could also be formed by single or multiple dry etching and/or wet etching processes, which are all within the scope of the present invention. According to an embodiment of the present invention, each of the recesses28could have various cross-section shapes, including but not limited to for example a circle, a hexagon, or an octagon. Despite the cross-section of the recess28in this embodiment pertains to be a hexagon, it would also be desirable to form the recess28with aforementioned shapes, which are all within the scope of the present invention.

Next, as shown inFIG.2, a selective epitaxial growth (SEG) is conducted by using gas such as dichlorosilane (DCS) to form an epitaxial layer30in each of the recesses28, in which the epitaxial layer30includes a buffer layer32disposed on a surface of the recess28, a first linear bulk layer34disposed on the buffer layer32, a second linear bulk layer36disposed on the first linear bulk layer34, a bulk layer38disposed on the second linear bulk layer36, and a cap layer40disposed on the bulk layer38.

In this embodiment, a top surface of the epitaxial layer30such as the top surface of the buffer layer32, the top surface of the first linear bulk layer34, the top surface of the second linear bulk layer36, and the top surface of the bulk layer38are preferably even with a top surface of the substrate12, in which the epitaxial layer30also shares substantially same cross-section shape with the recess28. For instance, the cross-section of the epitaxial layer30could also include a circle, a hexagon, or an octagon depending on the demand of the product. In this embodiment, the epitaxial layer30could also be formed to include different material depending on the type of transistor being fabricated. For instance, if the MOS transistor being fabricated were to be a PMOS transistor, the epitaxial layer30could be made of material including but not limited to for example SiGe, SiGeB, or SiGeSn. If the MOS transistor being fabricated were to be a NMOS transistor, the epitaxial layer30could be made of material including but not limited to for example SiC, SiCP, or SiP. Moreover, the SEG process could also be adjusted to form a single-layered epitaxial structure or multi-layered epitaxial structure, in which heteroatom such as germanium atom or carbon atom of the structure could be formed to have gradient while the surface of the epitaxial layer30is preferred to have less or no germanium atom at all to facilitate the formation of silicide afterwards. It should be noted that even though the top surfaces of the substrate12and buffer layer32, first linear bulk layer34, second linear bulk layer36, and bulk layer38of the epitaxial layer30are coplanar in this embodiment, it would also be desirable extend the epitaxial layer30upward so that the top surfaces of the buffer layer32, first linear bulk layer34, second linear bulk layer36, and bulk layer38are higher than the top surface of the substrate12according to another embodiment of the present invention.

Next, an ion implantation process is conducted to form a source/drain region42in part or all of the epitaxial layer30. According to another embodiment of the present invention, the source/drain region42could also be formed insituly during the SEG process. For instance, the source/drain region42could be formed by implanting p-type dopants during formation of a SiGe epitaxial layer, a SiGeB epitaxial layer, or a SiGeSn epitaxial layer for PMOS transistor, or could be formed by implanting n-type dopants during formation of a SiC epitaxial layer, SiCP epitaxial layer, or SiP epitaxial layer for NMOS transistor. By doing so, it would be desirable to eliminate the need for conducting an extra ion implantation process for forming the source/drain region. Moreover, the dopants within the source/drain region42could also be formed with a gradient, which is also within the scope of the present invention.

It should be noted the epitaxial layer30in this embodiment preferably includes SiGe and the buffer layer32, the first linear bulk layer34, the second linear bulk layer36, the bulk layer38, and the cap layer40preferably include different concentration distributions and distribution curves. For instance, the germanium (Ge) concentration of the buffer layer32is preferably less than the germanium concentration of the first linear bulk layer34, the germanium concentration of the first linear bulk layer34is less than the germanium concentration of the second linear bulk layer36, the germanium concentration of the second linear bulk layer36is less than the germanium concentration of the bulk layer38, and the germanium concentration of the cap layer40is less than the germanium concentration of the bulk layer38, in which the slope of the germanium concentration of the first linear bulk layer34is preferably less than the slope of the germanium concentration of the second linear bulk layer36, and the thickness of the second linear bulk layer36is less than the thickness of the first linear bulk layer34.

Preferably, the Ge concentration of the buffer layer32is between 30% to 33%, the Ge concentration of the first linear bulk layer34is less than 39%, the Ge concentration of the second linear bulk layer36is between 39% to 47%, the Ge concentration of the bulk layer38is between 47% to 60%, and the Ge concentration of the cap layer40is between 28% to 30%. Moreover, the thickness of the buffer layer32is preferably about 100 Angstroms, the thickness of the first linear bulk layer34is about 100 Angstroms, the thickness of the second linear bulk layer36is between 30-50 Angstroms, and the thickness of the bulk layer38is between 200-300 Angstroms.

Next, as shown inFIG.3, precursors such as silane (SiH4) and dichlorosilane (DCS) are employed with other reacting gases to form a cap layer60made of silicon on the surface of the cap layer40. It should be noted that the formation of the cap layer60is accomplished by injecting the aforementioned precursors and other reacting gases such as hydrogen chloride (HCl) and/or diborane (B2H2) without injecting any germanium-containing gas such as germane (GeH4). Preferably, the flow of germane for forming the epitaxial layer30is between 180-300 sccm, the flow of DCS is between 60-100 sccm, the flow of HCl is between 40-100 sccm, and the flow of diborane is between 200-300 sccm. Moreover, the deposition time of the cap layer60is between 120-170 seconds, the fabrication temperature is between 740-770° C., and the pressure is between 5-20 Torr.

By using the above recipe and parameters, it would be desirable to form a bowl-shape cap layer60on the surface of the cap layer40, in which the top surface of the cap layer60preferably includes a V-shape62profile and two planar surfaces64connecting and extending at two sides of the V-shape62. Preferably, this particular profile of the cap layer60could be used to protect the spacers in particular the offset spacers from forming voids as a result of damages caused by series of etching processes conducted in the later process and defect of the semiconductor device could also be reduced substantially.

Next, as shown inFIG.4, a contact etch stop layer (CESL)44could be formed on the substrate12surface to cover the gate structures14,16and the cap layer60, and an interlayer dielectric (ILD) layer46is formed on the CESL44afterwards. Next, a planarizing process such as a chemical mechanical polishing (CMP) process is conducted to remove part of the ILD layer46and part of the CESL44so that the top surfaces of the hard mask22and ILD layer46are coplanar.

Next, a replacement metal gate (RMG) process is conducted to transform the gate structures14,16into metal gates. For instance, the RMG process could be accomplished by first performing a selective dry etching or wet etching process using etchants including but not limited to for example ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard masks22, the gate material layer20, and even the gate dielectric layer18from gate structures14,16for forming recesses (not shown) in the ILD layer46. Next, a selective interfacial layer48or gate dielectric layer (not shown), a high-k dielectric layer50, a work function metal layer52, and a low resistance metal layer54are formed in the recesses, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer54, part of work function metal layer52, and part of high-k dielectric layer50to form metal gates. In this embodiment, each of the gate structures or metal gates fabricated through high-k last process of a gate last process preferably includes an interfacial layer48or gate dielectric layer (not shown), a U-shaped high-k dielectric layer50, a U-shaped work function metal layer52, and a low resistance metal layer54.

In this embodiment, the high-k dielectric layer50is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer50may be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof.

In this embodiment, the work function metal layer52is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the work function metal layer52having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer52having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer52and the low resistance metal layer54, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer54may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.

Next, part of the high-k dielectric layer50, part of the work function metal layer52, and part of the low resistance metal layer54are removed to form recesses (not shown), and hard masks56are then formed into the recesses so that the top surfaces of the hard masks56and ILD layer46are coplanar. The hard masks56could be made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof.

Next, as shown inFIG.5, a photo-etching process is conducted by using a patterned mask (not shown) as mask to remove part of the ILD layer46and part of the CESL44adjacent to the gate structures14,16for forming contact holes (not shown) exposing the cap layer40underneath. Next, conductive materials including a barrier layer selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and a metal layer selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP) are deposited into the contact holes, and a planarizing process such as CMP is conducted to remove part of aforementioned barrier layer and low resistance metal layer for forming contact plugs58electrically connecting the source/drain regions42. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

Referring again toFIG.5,FIG.5further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG.5, the semiconductor device includes at least a gate structure14disposed on the substrate12, a spacer24disposed on sidewalls of the gate structure14, epitaxial layers30disposed in the substrate12adjacent to two sides of the spacer24, and cap layers60disposed on the epitaxial layers30, in which each of the epitaxial layers30include a buffer layer32, a first linear bulk layer34, a second linear bulk layer36, a bulk layer38, and a cap layer40.

In this embodiment, the top surface of the cap layer40is higher than the top surface of the substrate12, the bottom surface of the cap layer40is even with the top surface of the substrate12, the buffer layer32, first linear bulk layer34, second linear bulk layer36, bulk layer38, and cap layer40of the epitaxial layer30are preferably made of same material such as SiGe while having germanium concentration curves as disclosed previously, the cap layer40and cap layer60are made of different materials as the cap layer60is preferably made of silicon, the bottom surface of the cap layer60is higher than the top surface of the substrate12, and the top surface of the cap layer60could be lower than or higher than half the height of the gate structure14.

Structurally the cap layer60includes a bowl-like shape overall, in which the top surface of the cap layer60includes a V-shape62and two planar surfaces64parallel to the top surface of the substrate12and connecting to two sides of the V-shape62respectively. Nevertheless, according to an embodiment of the present invention as shown inFIG.6, the bottom portion of the V-shape62shown inFIG.5could also be replaced by a curve66concave upward as the curve66is also connected to planar surfaces62adjacent to two sides of the curve66, which is also within the scope of the present invention.

As shown inFIGS.7-8,FIGS.7-8illustrate structural views of a semiconductor device according to different embodiments of the present invention. As shown inFIG.7, in contrast to the bottom surface of the contact plug58only includes a V-shape profile or the bottom surface of the contact plug58only contacts the V-shape profile of the cap layer60as shown inFIG.5, it would also be desirable to extend the width of the contact plug58so that the bottom surface of the contact plug58is standing on both the V-shape62profile and two adjacent planar surfaces64of the cap layer60or if viewed from another perspective the bottom surface of the contact plug58itself includes a V-shape62profile and two planar surfaces64adjacent to two sides of the V-shape62profile, which is also within the scope of the present invention.

Alternatively, as shown inFIG.8, it would also be desirable to further extend the width of the contact plug58as shown inFIG.7by eliminating the ILD layer46so that not only the bottom surface of the contact plug58includes a V-shape62profile and two planar surfaces64adjacent to two sides of the V-shape62profile but also the left and right sidewalls of the contact plug58contact the CESL44instead of the ILD layer46directly, which is also within the scope of the present invention.

Overall, the present invention first forms an epitaxial layer having a buffer layer, a bulk layer, and a cap layer all made of SiGe and then forms a cap layer60made of silicon having a V-shape profile and two planar surfaces connecting and adjacent to two sides of the V-shape profile on the surface of the epitaxial layer. Preferably, the particular bowl-shape profile of the cap layer60could be used to protect the spacers from forming voids as a result of damages caused by series of etching processes conducted in the later process and defect of the semiconductor device could also be minimized substantially.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.