Patent ID: 12249540

DETAILED DESCRIPTION

Trenches may be formed for a variety of reasons, including for example, to provide dicing lanes for the separation of a semiconductor wafer (e.g., a silicon wafer) into multiple dies. Additionally, the surface quality of the trench may enable the efficient coupling of the light in and/or out of the SiPhot die. A trench can be also useful for many other applications such as optical crosstalk mitigation, thermal crosstalk mitigation, and the co-integration of multi-platform opto-electrical dies. For example, trenches could be used to integrate InP-based components (e.g., lasers, optical amplifiers, optical modulators, optical filters), LiNbO3-based components (e.g., modulators, optical modulators), free-space optics components (e.g., optical isolators, optical circulators, optical filters), or even another SiPhot die.

Different applications, including the applications mentioned above, may use trenches with different depths, however, there are challenges associated with fabricating such SiPhot dies with trenches of varying depths. For the purposes of some of the examples described herein, an application of interest will be one for which a deep trench (DT) will be formed having a first depth relative to the surface of the substrate (e.g., 120 microns deep) and a shallow trench (ST) will be formed having a second depth relative to the surface of the substrate (e.g., 40 microns deep). However, other examples may include more than two different depths of trenches, and/or depths that are considered to be at intermediate depths between “shallow” trenches or “deep” trenches. The first depth of the DT may provide, for example, a cavity for the co-integration of a semiconductor optical amplifier directly on the SiPhot die, and the second depth of the ST may be used, for example, for dicing lanes and optical coupling. The ST may also be used, for example, for compatibility with flip-chip process steps (such as metallization and bumping) that may be performed for the packaging of the SiPhot dies.

FIG.1shows an example of a portion100of a SiPhot device fabricated using etching rate selectivity techniques described herein. In this example, a SOI processing technique is used in which there is a BOX layer102. In front-end-of-line (FEOL) processes, various structures, including photonic structures such as waveguides can be formed by etching and/or depositing material in any number of layers, such a structure104formed from etching Silicon deposited on top of the BOX layer102(or etching Silicon that has been grown or otherwise pre-formed during an SOI formation procedure to provide the Silicon as a top layer on top of the BOX layer in an initial SOI wafer), and a structure106formed from Germanium epitaxy. Between deposition of the various layers, additional Silicon dioxide108can be deposited surrounding the various structures and between various layers formed from various materials at different depths, such as structures110formed from Silicon Nitride (SiN). The Silicon dioxide108that is deposited has the same molecular composition as the Silicon dioxide that forms the BOX layer102, but may have different material features such as a lower density and a more porous structure. In BEOL processes, structures can be formed including metal interconnects and pads, such as the structures112formed in this example using Aluminum. Additionally, the etching rate selectivity techniques, described in more detail below, have been used to form a shallow trench114etched into the (bulk) Silicon substrate116at first depth (e.g., 40 microns) below a bottom surface118of the BOX layer102, and a deep trench120etched into the Silicon substrate116at a second depth (e.g., 120 microns) below the bottom surface118of the BOX layer102. These trenches may have structural features122,124that are characteristic of the etching rate selectivity techniques, as described in more detail below. In some cases, certain optical coupling structures, such as waveguides, can be formed in proximity to one or more of the trenches (e.g., with a core of the waveguide ending adjacent to a wall of the trench) to couple light between a device inserted into a trench and photonic circuitry within the SiPhot device.

FIGS.2A-2Cillustrate an example of an alternative procedure to fabricate a SiPhot device that has trenches with different depths other than the etching rate selectivity techniques described herein. A first step (FIG.2A) for forming the trenches includes selectively etching all the Silicon dioxide on top of the ST regions (including a shallow trench214and any other STs at that depth) and DT regions (including a deep trench220and any other DTs at that depth), down to the Silicon substrate116. The selective etching can be performed using photoresist (PR)200deposited over all regions other than the ST regions and DT regions, which are being preserved. For example, the PR is first spun over the entire wafer, and then a mask can be used to expose PR over the ST regions and DT regions to UV light, enabling the exposed PR to be selectively removed. In a subsequent step (FIG.2B), both the STs and the DTs are etched down to the ST depth250, which in this example is a few microns below the bottom of the BOX layer102. In a subsequent step (FIG.2B), additional PR202is deposited over the STs and any other portions of the wafer other than the DT regions to be further etched. In a subsequent step, the DTs are etched to their full depth, resulting in the etched device shown inFIG.2C.

Procedures such as this alternative procedure may limit the depth of the STs that may be achieved when using a standard spin coating process to deposit the PR all over the wafer. For example, if the thickness of the PR is limited to a few microns (e.g., less than 10 microns), then the depth of the STs may also be limited to a few microns so that the shallow trench depth is small enough to ensure that the top of the SiPhot dies are well covered by the PR. Also, spin-coating a PR on a topographical surface may also have practical limitations. For example, if cavities and other features (including the STs in this example) are present along the surface, the PR may fail to fill them properly, potentially leading to unintended exposed material that is not protected by PR. Moreover, topography may also result in uneven deposited film thicknesses over the wafer resulting in wrong pattern dimensions. Additionally, uneven PR thicknesses may be difficult to strip properly, which may cause PR residues in the ST areas.

Alternatives to spin-coating include spray-coating and dry film PR. However, such technologies may not be as widespread in CMOS foundries, and/or may be limited to dedicated foundries devoted to such specialized techniques as fabrication of micro-electro-mechanical systems (MEMS) and far-BEOL processes. Thus, these alternatives may not be CMOS compatible, which is useful for fabricating devices that have trenches of various depths for integration, such as devices in a SiPhot platform.

To address some or all of these limitations, the etching rate selectivity techniques described herein provide a fabrication process flow that enables the etching of two or more trenches with different depths. These techniques are based on the etching selectivity between a substrate material and a slow-etch material (e.g., the Silicon and Silicon dioxide, respectively, used in this example), where the slow-etch material has a slower etch rate than the substrate material for a given etching process. For example, the rate of the Silicon etching is typically ˜100 times faster compared to the rate of the Silicon dioxide etching for typical etching processes (e.g., deep reactive ion etching, plasma etching, and wet etching, which may be at wafer level and by immersion). Using this etching rate selectivity (also called differential etch rates), a process can be used that enables the etching of both the STs and the DTs without the limitations described above being imposed on the depth of the STs.

FIGS.3A-3Cillustrate an example of an etching rate selectivity procedure for forming trenches of varying depths. A first step (FIG.3A) includes etching all the Silicon dioxide on top of the ST regions (including the shallow trench114and any other STs at that depth) and DT regions (including the deep trench220and any other DTs at that depth), down to the Silicon substrate116. The selective etching can be performed using PR300that is selectively removed, as described above forFIG.2A. In a subsequent step (FIG.3B), a relatively thin slow-etch layer350, composed of Silicon dioxide in this example, is deposited on top of the ST regions. The thickness of this slow-etch layer350(750 nm in this example) together with the etching selectivity of the material used for the slow-etch layer350will determine the ratio of the STs depth to the DTs depth. The precision used to achieve a desired thickness of the slow-etch layer may depend on the precision that is desired for the different trench depths. For example, if one of the trench depths calls for higher precision (e.g., due to a tighter tolerance on the target depth), then the simultaneous etching step can be monitored to stop based on that trench depth, and any variation in slow-etch layer thickness would result in variation in the other (non-monitored) trench depth. This may be acceptable since some trenches (e.g., trenches for dicing lanes) may not have tight tolerances on their depth. Alternatively, if both trench depths call for relatively high precision, then the slow-etch layer thickness can be controlled using a material and/or process that results in a more precise thickness. In subsequent steps (FIG.3C), after a PR layer302is patterned to protect the non-trench regions, the etching of both the ST and the DT trenches are performed simultaneously. While the slow-etch layer will be etched slowly in the ST regions, the substrate will be etched rapidly in the DT regions. After the slow-etch layer in the ST regions is completely etched away, the substrate etching will continue in both the ST and DT areas with the same etching rate until a desired stopping point is reached, resulting in a device that achieves the desired trench depths (40 microns and 120 microns in this example for the ST114and DT120, respectively). Referring back toFIG.1, structural features122,124may remain at the bottom surfaces of the various trenches that are characteristic of the etching rate selectivity procedure used to form the trenches. In this example, the deep trench120has a relatively smooth surface topography122and the shallow trench114has a relatively rough surface topography124compared to the roughness of the topography122.

Compared to the alternative process flow described with reference toFIGS.2A-2C, this etching rate selectivity technique can easily be adapted for the etching of more than two trenches with different depths. Furthermore, there are other ways to generate the slow-etch layer. For example, for achieving more than two different depths of trenches, multiple etching rate selectivity phases can be performed. A stop layer (e.g., using silicon nitride or another appropriate protective material) can be formed over the ST regions, deposited during the process on top of a given thickness of Silicon dioxide (e.g., BOX, pre-metal dielectric (PMD), inter-metal dielectric (IMD), or a combination). This protective stop layer can be used to keep a layer of Silicon dioxide to be used later as a slow-etch layer temporarily unetched on top of the ST areas so that it can be exploited during a subsequent etching rate selectivity phase after the stop layer is removed.

Additionally, materials other than Silicon dioxide can be used to form the slow-etch layer to control the STs depth including Silicon Nitride, Silicon Oxynitride, Silicon Carbonitride, or even PR using an appropriate technique for controlling the thickness of the PR (e.g., other than spinning an arbitrary thickness of PR). Since Silicon dioxide deposition is done at wafer level, it is patterned (e.g., using PR or other selective patterning procedures before and/or after deposition) to keep only the desired thickness of a slow-etch layer over the STs, removing the deposited Silicon dioxide elsewhere (as show inFIG.3B). An alternative to depositing a thin layer of Silicon dioxide would be to use another material with slower etching rate than Silicon (or other substrate material if a different kind of photonic integrated circuit die was used other than a SiPhot die), such as a thin PR layer with a thickness between around 100-500 nm, depending on the type of PR used and the desired trench ratio. Using a PR layer could make the slow-etch layer deposition process more straightforward since the PR layer can be developed to remove the unwanted sections. In some implementations, a portion of the BOX layer102may be used to form the slow-etch layer by limiting removal of the BOX layer102over the ST regions, and completely removing the BOX layer102over the DT regions. Alternatively, different thicknesses of the BOX layer can be left to cover the ST regions and DT regions, with a thicker BOX layer remaining over the ST regions and a thinner BOX layer remaining over the DT regions.

FIGS.4A-6Gillustrate another example of an etching rate selectivity procedure for forming trenches of varying depths. In this example, two deep trenches are formed, each having a different depth. An initial state of a SOI wafer (FIG.4A) includes a bulk Silicon substrate400(also called a handle layer or base layer), a BOX layer402, and a SOI layer of Silicon404(also called a top layer or device layer). For example, the SOI wafer has the following characteristics in some implementations: a diameter of 200 mm, a bulk Silicon substrate thickness of 725 microns (±about 15 microns) and high resistivity of greater than about 750 ohm-cm, a BOX layer thickness of about 3 microns, and a SOI Silicon layer thickness of 220 nm and resistivity of 10 ohm-cm. A first step (FIG.4B) includes etching away all of the SOI layer of Silicon404(e.g., using full sheet etching) since there will not be any patterned photonic circuits in this layer in this example (other examples may preserve some or all of the SOI layer of Silicon404on portions of the wafer). In a subsequent step (FIG.4C), a layer of Silicon dioxide is deposited as an Inter Metal Dielectric (IMD) layer406(e.g., as in a SiPhot BOEL process). In a subsequent step (FIG.4D), patterning produces a first DT region408and a second DT region410both initially etched to the same depth, which can use the bulk Silicon substrate400as an etch stop layer (ESL). In a subsequent step (FIG.4E), a thin layer of Silicon dioxide412is deposited having an adapted thickness. The deposited thickness is tuned with respect to the different etch rates of Silicon and Silicon dioxide, and a targeted etch depth differences between the DT region408and the DT region410. In a subsequent step (FIG.4F), patterning is performed to locally remove Silicon dioxide at the bottom of the DT region410to expose the underlying Silicon substrate400, but preserve the thin deposited layer of Silicon dioxide412at the bottom of the DT region408. In a subsequent step (FIG.4G), a selective Silicon etch is performed at the wafer level without photoresist to etch both the DT region408and the DT region410selectively due to the time needed to fully etch away the Silicon dioxide used as the slow-etch layer in the DT region408before continuing to etch Silicon in the DT region408, compared to using the entire etch time for etching Silicon in the DT region410.

FIG.5shows an example of a cross-sectional view of a portion500of the wafer fabricated using the etching rate selectivity procedure ofFIGS.4A-4G. There are structural features502and504that remain at the bottom surfaces of the DT region408and DT region410, respectively, which are characteristic of the etching rate selectivity procedure used to form the trenches. In this example, the deeper of the two trench regions, DT region410, has a relatively smooth surface topography504and the shallower of the two trench regions, DT region408, has a relatively rough surface topography502compared to the roughness of the topography504. The relatively rough surface topography502has been caused, for example, by micro-masking effect that occurs when the Silicon dioxide on top of the shallow trench has not been etched in a perfectly uniform manner, as described herein. There is also a difference in the sidewall profiles of the two trenches, as shown inFIG.5.

FIGS.6A-6Eillustrate another example of an etching rate selectivity procedure for forming trenches of varying depths. This is another example in which two deep trenches are formed, each having a different depth, but procedure that includes additional steps that help to reduce or eliminate micro-masking effects. An initial state of a SOI wafer (FIG.6A) includes a bulk Silicon substrate600, a BOX layer602, and a SOI layer of Silicon604. The SOI wafer has the same characteristics in this simplified procedure as in the full procedure. A first step (FIG.6B) includes etching away all of the SOI layer of Silicon604(e.g., using full sheet etching). In a subsequent step (FIG.6C), a 6.3-micron thick layer of Silicon dioxide is deposited as an Inter Metal Dielectric (IMD) layer606. In a subsequent step (FIG.6D), patterning produces a first DT region608and a second DT region610both initially etched to the same depth, which penetrate into the bulk Silicon substrate600to the same target depth, which corresponds to the target final depth of the first DT region608(e.g., around 50 microns). In a subsequent step (FIG.6E), a thin layer of Silicon dioxide612is deposited having an adapted thickness. The deposited thickness is tuned with respect to the different etch rates of Silicon and Silicon dioxide, and a targeted etch depth differences between the DT region608and the DT region610. In a subsequent step (FIG.6F), patterning is performed to locally remove Silicon dioxide at the bottom of the DT region610to expose the underlying Silicon substrate600, but preserve the deposited layer of Silicon dioxide612at the bottom of the DT region608. In a subsequent step (FIG.6G), a selective Silicon etch is performed at the wafer level without photoresist to etch both the DT region608and the DT region610selectively due to the time needed to partially etch the Silicon dioxide used as the slow-etch layer in the DT region608down to a thin Silicon dioxide layer614, compared to using that etch time for etching Silicon in the DT region610. In a subsequent step (6H), the remaining thin Silicon dioxide layer614is etched away in the DT region608using Silicon as a stop-layer, while the DT region610is further etched. In a subsequent step (6I), both regions are further etched using a time-fixed Silicon etching that achieves the target depths for both the DT region608and the DT region610.

While the disclosure has been described in connection with certain embodiments, it is to be understood that the disclosure is not to be limited to the disclosed embodiments but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as is permitted under the law.